From ded06bcd1202b85f3a8d86e659b0fa1d9a354361 Mon Sep 17 00:00:00 2001 From: codetector Date: Tue, 11 Feb 2020 09:57:32 -0500 Subject: [PATCH 01/66] ram m10k fix --- rtl/shared_memory/VX_shared_memory_block.v | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/rtl/shared_memory/VX_shared_memory_block.v b/rtl/shared_memory/VX_shared_memory_block.v index 9a37b6fe..1be976c8 100644 --- a/rtl/shared_memory/VX_shared_memory_block.v +++ b/rtl/shared_memory/VX_shared_memory_block.v @@ -33,13 +33,15 @@ module VX_shared_memory_block //wire need_to_write = (|we); integer curr_ind; - always @(posedge clk, posedge reset) begin - if (reset) begin - //for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1) + initial begin for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1) begin shared_memory[curr_ind] = 0; end + end + always @(posedge clk, posedge reset) begin + if (reset) begin + //for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1) end else if(shm_write) begin shared_memory[addr][we][31:0] = wdata[we][31:0]; // - Ethan's addition //if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0]; From e82e29c855822ea0b98351bedc72cd8b0b3f21a8 Mon Sep 17 00:00:00 2001 From: codetector Date: Wed, 19 Feb 2020 23:19:05 -0500 Subject: [PATCH 02/66] remove async reset for FPGA synthesis --- rtl/cache/VX_cache_data.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/cache/VX_cache_data.v b/rtl/cache/VX_cache_data.v index 62c62bd9..b4aac41e 100644 --- a/rtl/cache/VX_cache_data.v +++ b/rtl/cache/VX_cache_data.v @@ -79,10 +79,10 @@ module VX_cache_data always @(posedge clk, posedge rst) begin : update_all if (rst) begin for (ini_ind = 0; ini_ind < NUM_IND; ini_ind=ini_ind+1) begin - data[ini_ind] <= 0; - tag[ini_ind] <= 0; + //data[ini_ind] <= 0; + //tag[ini_ind] <= 0; valid[ini_ind] <= 0; - dirty[ini_ind] <= 0; + //dirty[ini_ind] <= 0; end end else begin if (update_dirty) dirty[addr] <= dirt_new; // WRite Port From 83d1f54fcf9ea90c1cfe35dffd975d0e4869a685 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Thu, 20 Feb 2020 15:59:23 -0500 Subject: [PATCH 03/66] fix shared mem ram inference --- rtl/shared_memory/VX_shared_memory_block.v | 31 ++++++++++++---------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/rtl/shared_memory/VX_shared_memory_block.v b/rtl/shared_memory/VX_shared_memory_block.v index 1be976c8..0783583c 100644 --- a/rtl/shared_memory/VX_shared_memory_block.v +++ b/rtl/shared_memory/VX_shared_memory_block.v @@ -28,31 +28,34 @@ module VX_shared_memory_block `ifndef SYN - //reg[3:0][31:0] shared_memory[127:0]; - reg[SMB_WORDS_PER_READ-1:0][31:0] shared_memory[SMB_HEIGHT-1:0]; + reg[SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0]; //wire need_to_write = (|we); integer curr_ind; - initial begin - for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1) - begin - shared_memory[curr_ind] = 0; - end - end + // initial begin + // for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1) + // begin + // shared_memory[curr_ind] = 0; + // end + // end always @(posedge clk, posedge reset) begin if (reset) begin //for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1) end else if(shm_write) begin - shared_memory[addr][we][31:0] = wdata[we][31:0]; // - Ethan's addition - //if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0]; - //if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0]; - //if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0]; - //if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0]; + if (we == 2'b00) shared_memory[reg_addr][0] <= wdata[0]; + if (we == 2'b01) shared_memory[reg_addr][1] <= wdata[1]; + if (we == 2'b10) shared_memory[reg_addr][2] <= wdata[2]; + if (we == 2'b11) shared_memory[reg_addr][3] <= wdata[3]; end end + wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr; + assign reg_addr = addr; + // always @(posedge clk) + // reg_addr <= addr; - assign data_out = shm_write ? 0 : shared_memory[addr]; + + assign data_out = shm_write ? 0 : shared_memory[reg_addr]; `else From f2c0453702d2e83a6115bc19d8a214646e7ebe96 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Fri, 21 Feb 2020 20:50:14 -0500 Subject: [PATCH 04/66] Add multi-cycle compat module and use it in ALU --- rtl/VX_alu.v | 58 +++++++++++++--------- rtl/compat/VX_mult.v | 104 ++++++++++++++++++++++++++++++++++++++++ rtl/quartus/project.tcl | 1 + 3 files changed, 141 insertions(+), 22 deletions(-) create mode 100644 rtl/compat/VX_mult.v diff --git a/rtl/VX_alu.v b/rtl/VX_alu.v index bdafab4f..384da8cd 100644 --- a/rtl/VX_alu.v +++ b/rtl/VX_alu.v @@ -14,13 +14,17 @@ module VX_alu( output reg out_alu_stall ); - localparam div_pipeline_len = 10; + localparam div_pipeline_len = 10; + localparam mul_pipeline_len = 3; - wire[31:0] unsigned_div_result; + wire[31:0] unsigned_div_result; wire[31:0] unsigned_rem_result; wire[31:0] signed_div_result; wire[31:0] signed_rem_result; + wire[63:0] mul_data_a, mul_data_b; + wire[63:0] mul_result; + VX_divide #( .WIDTHN(32), .WIDTHD(32), @@ -53,6 +57,28 @@ module VX_alu( .remainder(signed_rem_result) ); + VX_mult #( + .WIDTHA(64), + .WIDTHB(64), + .WIDTHP(64), + .SPEED("HIGHEST"), + .PIPELINE(mul_pipeline_len) + ) multiplier ( + .clock(clk), + .aclr(1'b0), + .clken(1'b1), // TODO this could be disabled on inactive instructions + .dataa(mul_data_a), + .datab(mul_data_b), + .result(mul_result) + ); + + // MUL, MULH (signed*signed), MULHSU (signed*unsigned), MULHU (unsigned*unsigned) + wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; + wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2}; + assign mul_data_a = (in_alu_op == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed; + assign mul_data_b = (in_alu_op == `MULHU || in_alu_op == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed; + + reg [15:0] curr_inst_delay; reg [15:0] inst_delay; reg inst_was_stalling; @@ -66,6 +92,10 @@ module VX_alu( `DIVU, `REM, `REMU: curr_inst_delay = div_pipeline_len; + `MUL, + `MULH, + `MULHSU, + `MULHU: curr_inst_delay = mul_pipeline_len; default: curr_inst_delay = 0; endcase // in_alu_op end @@ -95,8 +125,6 @@ module VX_alu( wire[31:0] ALU_in1; wire[31:0] ALU_in2; - wire[63:0] ALU_in1_mult; - wire[63:0] ALU_in2_mult; wire[31:0] upper_immed; assign which_in2 = in_rs2_src == `RS2_IMMED; @@ -106,20 +134,6 @@ module VX_alu( assign upper_immed = {in_upper_immed, {12{1'b0}}}; - //always @(posedge `MUL) begin - - - /* verilator lint_off UNUSED */ - - - wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; - wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2}; - assign ALU_in1_mult = (in_alu_op == `MULHU || in_alu_op == `DIVU || in_alu_op == `REMU) ? {32'b0, ALU_in1} : alu_in1_signed; - assign ALU_in2_mult = (in_alu_op == `MULHU || in_alu_op == `MULHSU || in_alu_op == `DIVU || in_alu_op == `REMU) ? {32'b0, ALU_in2} : alu_in2_signed; - wire[63:0] mult_result = ALU_in1_mult * ALU_in2_mult; - - /* verilator lint_on UNUSED */ - always @(in_alu_op or ALU_in1 or ALU_in2) begin case(in_alu_op) `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); @@ -135,11 +149,11 @@ module VX_alu( `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; `LUI_ALU: out_alu_result = upper_immed; `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); - `MUL: out_alu_result = mult_result[31:0]; - `MULH: out_alu_result = mult_result[63:32]; - `MULHSU: out_alu_result = mult_result[63:32]; - `MULHU: out_alu_result = mult_result[63:32]; // TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? + `MUL: out_alu_result = mul_result[31:0]; + `MULH: out_alu_result = mul_result[63:32]; + `MULHSU: out_alu_result = mul_result[63:32]; + `MULHU: out_alu_result = mul_result[63:32]; `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; diff --git a/rtl/compat/VX_mult.v b/rtl/compat/VX_mult.v new file mode 100644 index 00000000..c1f14c0e --- /dev/null +++ b/rtl/compat/VX_mult.v @@ -0,0 +1,104 @@ +module VX_mult + #( + parameter WIDTHA=1, + parameter WIDTHB=1, + parameter WIDTHP=1, + parameter REP="UNSIGNED", + parameter SPEED="MIXED", // "MIXED" or "HIGHEST" + parameter PIPELINE=0 + ) + ( + input clock, aclr, clken, + + input [WIDTHA-1:0] dataa, + input [WIDTHB-1:0] datab, + + output reg [WIDTHP-1:0] result + ); + +// synthesis read_comments_as_HDL on +// localparam IMPL = "quartus"; +// synthesis read_comments_as_HDL off + +// altera translate_off + localparam IMPL="fallback"; +// altera translate_on + + generate + + if (IMPL == "quartus") begin + + localparam lpm_speed=SPEED == "HIGHEST" ? 10:5; + + lpm_mult#( + .LPM_WIDTHA(WIDTHA), + .LPM_WIDTHB(WIDTHB), + .LPM_WIDTHP(WIDTHP), + .LPM_REPRESENTATION(REP), + .LPM_PIPELINE(PIPELINE), + .MAXIMIZE_SPEED(lpm_speed) + ) quartus_mult( + .clock(clock), + .aclr(aclr), + .clken(clken), + .dataa(dataa), + .datab(datab), + .result(result) + ); + + end + else begin + + wire [WIDTHA-1:0] dataa_pipe_end; + wire [WIDTHB-1:0] datab_pipe_end; + if (PIPELINE == 0) begin + assign dataa_pipe_end = dataa; + assign datab_pipe_end = datab; + end else begin + reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1]; + reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1]; + + genvar pipe_stage; + for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages + always @(posedge clock or posedge aclr) begin + if (aclr) begin + dataa_pipe[pipe_stage+1] <= 0; + datab_pipe[pipe_stage+1] <= 0; + end + else if (clken) begin + dataa_pipe[pipe_stage+1] <= dataa_pipe[pipe_stage]; + datab_pipe[pipe_stage+1] <= datab_pipe[pipe_stage]; + end + end + end + + always @(posedge clock or posedge aclr) begin + if (aclr) begin + dataa_pipe[0] <= 0; + datab_pipe[0] <= 0; + end + else if (clken) begin + dataa_pipe[0] <= dataa; + datab_pipe[0] <= datab; + end + end + + assign dataa_pipe_end = dataa_pipe[PIPELINE-1]; + assign datab_pipe_end = datab_pipe[PIPELINE-1]; + end + + /* * * * * * * * * * * * * * * * * * * * * * */ + /* Do the actual fallback computation here */ + /* * * * * * * * * * * * * * * * * * * * * * */ + + if (REP == "SIGNED") begin + assign result = $signed($signed(dataa_pipe_end) * $signed(datab_pipe_end)); + end + else begin + assign result = dataa_pipe_end * datab_pipe_end; + end + + end + endgenerate + +endmodule : VX_mult diff --git a/rtl/quartus/project.tcl b/rtl/quartus/project.tcl index c8447092..3a19b62e 100644 --- a/rtl/quartus/project.tcl +++ b/rtl/quartus/project.tcl @@ -71,6 +71,7 @@ set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v set_global_assignment -name VERILOG_FILE ../compat/VX_divide.v +set_global_assignment -name VERILOG_FILE ../compat/VX_mult.v set_global_assignment -name VERILOG_FILE ../VX_alu.v set_global_assignment -name VERILOG_FILE ../VX_back_end.v set_global_assignment -name VERILOG_FILE ../VX_context.v From b2afe526fea5f1f30587f2c27045129076e67e6c Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Fri, 21 Feb 2020 23:20:04 -0500 Subject: [PATCH 05/66] Update multiply for not SYN_FUNC --- rtl/VX_alu.v | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) diff --git a/rtl/VX_alu.v b/rtl/VX_alu.v index 384da8cd..1415aef3 100644 --- a/rtl/VX_alu.v +++ b/rtl/VX_alu.v @@ -179,21 +179,6 @@ module VX_alu( assign upper_immed = {in_upper_immed, {12{1'b0}}}; - - - // always @(*) begin - // $display("EXECUTE CURR_PC: %h",in_curr_PC); - // end - - /* verilator lint_off UNUSED */ - wire[63:0] mult_unsigned_result = ALU_in1 * ALU_in2; - wire[63:0] mult_signed_result = $signed(ALU_in1) * $signed(ALU_in2); - - wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; - - wire[63:0] mult_signed_un_result = alu_in1_signed * ALU_in2; - /* verilator lint_on UNUSED */ - always @(in_alu_op or ALU_in1 or ALU_in2) begin case(in_alu_op) `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); @@ -209,11 +194,11 @@ module VX_alu( `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; `LUI_ALU: out_alu_result = upper_immed; `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); - `MUL: begin out_alu_result = mult_signed_result[31:0]; end - `MULH: out_alu_result = mult_signed_result[63:32]; - `MULHSU: out_alu_result = mult_signed_un_result[63:32]; - `MULHU: out_alu_result = mult_unsigned_result[63:32]; // TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? + `MUL: out_alu_result = mul_result[31:0]; + `MULH: out_alu_result = mul_result[63:32]; + `MULHSU: out_alu_result = mul_result[63:32]; + `MULHU: out_alu_result = mul_result[63:32]; `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; From 23aabbf01dca5b35eb031b84cd4e3d1241b5927d Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Sat, 22 Feb 2020 20:16:13 -0500 Subject: [PATCH 06/66] Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance --- rtl/VX_alu.v | 5 ++-- rtl/compat/VX_mult.v | 59 ++++++++++++++++++++++++++++++-------------- 2 files changed, 43 insertions(+), 21 deletions(-) diff --git a/rtl/VX_alu.v b/rtl/VX_alu.v index 1415aef3..53b05b2d 100644 --- a/rtl/VX_alu.v +++ b/rtl/VX_alu.v @@ -14,8 +14,8 @@ module VX_alu( output reg out_alu_stall ); - localparam div_pipeline_len = 10; - localparam mul_pipeline_len = 3; + localparam div_pipeline_len = 20; + localparam mul_pipeline_len = 8; wire[31:0] unsigned_div_result; wire[31:0] unsigned_rem_result; @@ -62,6 +62,7 @@ module VX_alu( .WIDTHB(64), .WIDTHP(64), .SPEED("HIGHEST"), + .FORCE_LE("YES"), .PIPELINE(mul_pipeline_len) ) multiplier ( .clock(clk), diff --git a/rtl/compat/VX_mult.v b/rtl/compat/VX_mult.v index c1f14c0e..f9a07543 100644 --- a/rtl/compat/VX_mult.v +++ b/rtl/compat/VX_mult.v @@ -5,7 +5,8 @@ module VX_mult parameter WIDTHP=1, parameter REP="UNSIGNED", parameter SPEED="MIXED", // "MIXED" or "HIGHEST" - parameter PIPELINE=0 + parameter PIPELINE=0, + parameter FORCE_LE="NO" ) ( input clock, aclr, clken, @@ -30,21 +31,41 @@ module VX_mult localparam lpm_speed=SPEED == "HIGHEST" ? 10:5; - lpm_mult#( - .LPM_WIDTHA(WIDTHA), - .LPM_WIDTHB(WIDTHB), - .LPM_WIDTHP(WIDTHP), - .LPM_REPRESENTATION(REP), - .LPM_PIPELINE(PIPELINE), - .MAXIMIZE_SPEED(lpm_speed) - ) quartus_mult( - .clock(clock), - .aclr(aclr), - .clken(clken), - .dataa(dataa), - .datab(datab), - .result(result) - ); + if (FORCE_LE == "YES") begin + lpm_mult#( + .LPM_WIDTHA(WIDTHA), + .LPM_WIDTHB(WIDTHB), + .LPM_WIDTHP(WIDTHP), + .LPM_REPRESENTATION(REP), + .LPM_PIPELINE(PIPELINE), + .DSP_BLOCK_BALANCING("LOGIC ELEMENTS"), + .MAXIMIZE_SPEED(lpm_speed) + ) quartus_mult( + .clock(clock), + .aclr(aclr), + .clken(clken), + .dataa(dataa), + .datab(datab), + .result(result) + ); + end + else begin + lpm_mult#( + .LPM_WIDTHA(WIDTHA), + .LPM_WIDTHB(WIDTHB), + .LPM_WIDTHP(WIDTHP), + .LPM_REPRESENTATION(REP), + .LPM_PIPELINE(PIPELINE), + .MAXIMIZE_SPEED(lpm_speed) + ) quartus_mult( + .clock(clock), + .aclr(aclr), + .clken(clken), + .dataa(dataa), + .datab(datab), + .result(result) + ); + end end else begin @@ -92,13 +113,13 @@ module VX_mult /* * * * * * * * * * * * * * * * * * * * * * */ if (REP == "SIGNED") begin - assign result = $signed($signed(dataa_pipe_end) * $signed(datab_pipe_end)); + assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end)); end else begin - assign result = dataa_pipe_end * datab_pipe_end; + assign result = dataa_pipe_end*datab_pipe_end; end end endgenerate -endmodule : VX_mult +endmodule: VX_mult From 6bf25b5b78bbbdfb7fc8324b1f11ab66372355de Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 1 Mar 2020 18:01:02 -0800 Subject: [PATCH 07/66] +Added icache stage -- 3rd case of AUIPC os broken? --- rtl/VX_fetch.v | 48 +++++++++++++++++++------------------ rtl/VX_front_end.v | 35 +++++++++++++++++++++------ rtl/VX_icache_stage.v | 31 ++++++++++++++++++++++++ rtl/simulate/test_bench.cpp | 19 +++++++++------ 4 files changed, 96 insertions(+), 37 deletions(-) create mode 100644 rtl/VX_icache_stage.v diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index d71df00f..391c8a1d 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -7,26 +7,39 @@ module VX_fetch ( VX_wstall_inter VX_wstall, VX_join_inter VX_join, input wire schedule_delay, - VX_icache_response_inter icache_response, - VX_icache_request_inter icache_request, + input wire icache_stage_delay, output wire out_ebreak, VX_jal_response_inter VX_jal_rsp, VX_branch_response_inter VX_branch_rsp, - VX_inst_meta_inter fe_inst_meta_fd, + VX_inst_meta_inter fe_inst_meta_fi, VX_warp_ctl_inter VX_warp_ctl ); - // Locals - wire pipe_stall; - - - assign pipe_stall = schedule_delay || icache_response.delay; - wire[`NT_M1:0] thread_mask; wire[`NW_M1:0] warp_num; wire[31:0] warp_pc; wire scheduled_warp; + + + // Only reason this is there is because there is a hidden assumption that decode is exactly after fetch + reg stall_might_be_branch; + always @(posedge clk) begin + if (reset) begin + stall_might_be_branch <= 0; + end else if (stall_might_be_branch == 1'b1) begin + stall_might_be_branch <= 0; + end else if (scheduled_warp == 1'b1) begin + stall_might_be_branch <= 1'b1; + end + end + + // Locals + wire pipe_stall; + + + assign pipe_stall = schedule_delay || icache_stage_delay || stall_might_be_branch; + VX_warp_scheduler warp_scheduler( .clk (clk), .reset (reset), @@ -82,22 +95,11 @@ module VX_fetch ( .out_ebreak (out_ebreak), .scheduled_warp (scheduled_warp) ); - - // always @(*) begin - // $display("Inside verilog instr: %h, pc: %h", icache_response.instruction, warp_pc); - // end - assign icache_request.pc_address = warp_pc; - assign icache_request.out_cache_driver_in_valid = !schedule_delay && scheduled_warp; - assign icache_request.out_cache_driver_in_mem_read = `LW_MEM_READ; - assign icache_request.out_cache_driver_in_mem_write = `NO_MEM_WRITE; - assign icache_request.out_cache_driver_in_data = 32'b0; + assign fe_inst_meta_fi.warp_num = warp_num; + assign fe_inst_meta_fi.valid = thread_mask; - assign fe_inst_meta_fd.warp_num = warp_num; - assign fe_inst_meta_fd.valid = thread_mask; - - assign fe_inst_meta_fd.instruction = (thread_mask == 0) ? 32'b0 : icache_response.instruction; - assign fe_inst_meta_fd.inst_pc = warp_pc; + assign fe_inst_meta_fi.inst_pc = warp_pc; endmodule \ No newline at end of file diff --git a/rtl/VX_front_end.v b/rtl/VX_front_end.v index eaf5e8c9..671b7ef7 100644 --- a/rtl/VX_front_end.v +++ b/rtl/VX_front_end.v @@ -20,12 +20,15 @@ module VX_front_end ( ); -VX_inst_meta_inter fe_inst_meta_fd(); +VX_inst_meta_inter fe_inst_meta_fi(); +VX_inst_meta_inter fe_inst_meta_fi2(); +VX_inst_meta_inter fe_inst_meta_id(); VX_frE_to_bckE_req_inter VX_frE_to_bckE_req(); VX_inst_meta_inter fd_inst_meta_de(); wire total_freeze = schedule_delay; +wire icache_stage_delay; /* verilator lint_off UNUSED */ // wire real_fetch_ebreak; @@ -47,20 +50,38 @@ VX_fetch vx_fetch( .VX_join (VX_join), .schedule_delay (schedule_delay), .VX_jal_rsp (VX_jal_rsp), - .icache_response (icache_response_fe), .VX_warp_ctl (VX_warp_ctl), - - .icache_request (icache_request_fe), + .icache_stage_delay (icache_stage_delay), .VX_branch_rsp (VX_branch_rsp), .out_ebreak (vortex_ebreak), // fetch_ebreak - .fe_inst_meta_fd (fe_inst_meta_fd) + .fe_inst_meta_fi (fe_inst_meta_fi) ); -VX_f_d_reg vx_f_d_reg( +wire freeze_fi_reg = total_freeze || icache_stage_delay; +VX_f_d_reg vx_f_i_reg( + .clk (clk), + .reset (reset), + .in_freeze (freeze_fi_reg), + .fe_inst_meta_fd(fe_inst_meta_fi), + .fd_inst_meta_de(fe_inst_meta_fi2) + ); + +VX_icache_stage VX_icache_stage( + .clk (clk), + .reset (reset), + .icache_stage_delay(icache_stage_delay), + .fe_inst_meta_fi (fe_inst_meta_fi2), + .fe_inst_meta_id (fe_inst_meta_id), + .icache_response (icache_response_fe), + .icache_request (icache_request_fe) + ); + + +VX_f_d_reg vx_i_d_reg( .clk (clk), .reset (reset), .in_freeze (total_freeze), - .fe_inst_meta_fd(fe_inst_meta_fd), + .fe_inst_meta_fd(fe_inst_meta_id), .fd_inst_meta_de(fd_inst_meta_de) ); diff --git a/rtl/VX_icache_stage.v b/rtl/VX_icache_stage.v new file mode 100644 index 00000000..b642f722 --- /dev/null +++ b/rtl/VX_icache_stage.v @@ -0,0 +1,31 @@ +`include "VX_define.v" + +module VX_icache_stage ( + input wire clk, + input wire reset, + output wire icache_stage_delay, + VX_inst_meta_inter fe_inst_meta_fi, + VX_inst_meta_inter fe_inst_meta_id, + VX_icache_response_inter icache_response, + VX_icache_request_inter icache_request +); + + wire valid_inst = (|fe_inst_meta_fi.valid); + + assign icache_request.pc_address = fe_inst_meta_fi.inst_pc; + assign icache_request.out_cache_driver_in_valid = fe_inst_meta_fi.valid != 0; + assign icache_request.out_cache_driver_in_mem_read = `LW_MEM_READ; + assign icache_request.out_cache_driver_in_mem_write = `NO_MEM_WRITE; + assign icache_request.out_cache_driver_in_data = 32'b0; + + + + assign icache_stage_delay = icache_response.delay; + + assign fe_inst_meta_id.instruction = (!valid_inst || icache_response.delay) ? 32'b0 : icache_response.instruction; + assign fe_inst_meta_id.inst_pc = fe_inst_meta_fi.inst_pc; + assign fe_inst_meta_id.warp_num = fe_inst_meta_fi.warp_num; + assign fe_inst_meta_id.valid = fe_inst_meta_fi.valid; + + +endmodule \ No newline at end of file diff --git a/rtl/simulate/test_bench.cpp b/rtl/simulate/test_bench.cpp index 2becfb89..8eb90aa4 100644 --- a/rtl/simulate/test_bench.cpp +++ b/rtl/simulate/test_bench.cpp @@ -67,14 +67,19 @@ int main(int argc, char **argv) for (std::string s : tests) { Vortex v; + std::cerr << DEFAULT << "\n---------------------------------------\n"; + std::cerr << s << std::endl; bool curr = v.simulate(s); if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl; if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl; + std::cerr << DEFAULT; passed = passed && curr; } + std::cerr << DEFAULT << "\n***************************************\n"; + if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n"; if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n"; @@ -82,15 +87,15 @@ int main(int argc, char **argv) #else - char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; + char testing[] = "../../emulator/riscv_tests/rv32ui-p-auipc.hex"; Vortex v; - const char *testing; + // const char *testing; - if (argc >= 2) { - testing = argv[1]; - } else { - testing = "../../kernel/vortex_test.hex"; - } + // if (argc >= 2) { + // testing = argv[1]; + // } else { + // testing = "../../kernel/vortex_test.hex"; + // } std::cerr << testing << std::endl; From abca2f7abb3db6068075d043cb15ac473b9594bb Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 1 Mar 2020 22:27:18 -0800 Subject: [PATCH 08/66] Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors --- rtl/VX_scheduler.v | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/rtl/VX_scheduler.v b/rtl/VX_scheduler.v index da9962a6..a3116744 100644 --- a/rtl/VX_scheduler.v +++ b/rtl/VX_scheduler.v @@ -17,13 +17,14 @@ module VX_scheduler ( - reg[31:0] rename_table[`NW-1:0]; + reg[31:0][`NT-1:0] rename_table[`NW-1:0]; wire valid_wb = (VX_writeback_inter.wb != 0) && (|VX_writeback_inter.wb_valid) && (VX_writeback_inter.rd != 0); wire wb_inc = (VX_bckE_req.wb != 0) && (VX_bckE_req.rd != 0); - wire rs1_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs1]; - wire rs2_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs2]; + wire rs1_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs1] != 0; + wire rs2_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs2] != 0; + wire rd_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rd ] != 0; wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE); wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ); @@ -35,19 +36,18 @@ module VX_scheduler ( wire is_exec = !is_mem && !is_gpu && !is_csr; - wire rs1_pass = ((valid_wb && (VX_writeback_inter.rd == VX_bckE_req.rs1))); - wire rs2_pass = ((valid_wb && (VX_writeback_inter.rd == VX_bckE_req.rs2))); // wire rs1_pass = 0; // wire rs2_pass = 0; wire using_rs2 = (VX_bckE_req.rs2_src == `RS2_REG) || is_store || VX_bckE_req.is_barrier || VX_bckE_req.is_wspawn; - wire rs1_rename_qual = ((rs1_rename || (rs1_pass && 0)) && (VX_bckE_req.rs1 != 0)); - wire rs2_rename_qual = ((rs2_rename || (rs2_pass && 0)) && (VX_bckE_req.rs2 != 0 && using_rs2)); + wire rs1_rename_qual = ((rs1_rename) && (VX_bckE_req.rs1 != 0)); + wire rs2_rename_qual = ((rs2_rename) && (VX_bckE_req.rs2 != 0 && using_rs2)); + wire rd_rename_qual = ((rd_rename ) && (VX_bckE_req.rd != 0)); - wire rename_valid = rs1_rename_qual || rs2_rename_qual ; + wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual; assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid)) || (memory_delay && is_mem) @@ -67,8 +67,8 @@ module VX_scheduler ( end end end else begin - if (valid_wb ) rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] <= 0; - if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.warp_num ][VX_bckE_req.rd] <= 1; + if (valid_wb ) rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] <= rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] & (~VX_writeback_inter.wb_valid); + if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.warp_num ][VX_bckE_req.rd ] <= VX_bckE_req.valid; end end From fc5621cd1dbb7162ca6151f13ce487d038c9e6a7 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 2 Mar 2020 23:08:54 -0800 Subject: [PATCH 09/66] Everything except bank internals --- rtl/Makefile | 4 +- rtl/VX_cache/VX_cache.v | 179 ++++++++++++++++++++++ rtl/VX_cache/VX_cache_bank.v | 41 +++++ rtl/VX_cache/VX_cache_config.v | 126 +++++++++++++++ rtl/VX_cache/VX_cache_core_req_bank_sel.v | 25 +++ rtl/VX_cache/VX_cache_dfq_queue.v | 78 ++++++++++ rtl/VX_cache/VX_cache_dram_req_arb.v | 68 ++++++++ rtl/VX_cache/VX_cache_wb_sel_merge.v | 65 ++++++++ rtl/VX_generic_queue.v | 49 ++++++ 9 files changed, 632 insertions(+), 3 deletions(-) create mode 100644 rtl/VX_cache/VX_cache.v create mode 100644 rtl/VX_cache/VX_cache_bank.v create mode 100644 rtl/VX_cache/VX_cache_config.v create mode 100644 rtl/VX_cache/VX_cache_core_req_bank_sel.v create mode 100644 rtl/VX_cache/VX_cache_dfq_queue.v create mode 100644 rtl/VX_cache/VX_cache_dram_req_arb.v create mode 100644 rtl/VX_cache/VX_cache_wb_sel_merge.v create mode 100644 rtl/VX_generic_queue.v diff --git a/rtl/Makefile b/rtl/Makefile index 29a658bc..980a3211 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -1,9 +1,7 @@ all: RUNFILE -# /rf2_256x128_wm1/ -BaseMEM=../models/memory/cln28hpm -INCLUDE=-I. -Ishared_memory -Icache -I$(BaseMEM)/rf2_128x128_wm1/ -I$(BaseMEM)/rf2_256x128_wm1/ -I$(BaseMEM)/rf2_256x19_wm0/ -I$(BaseMEM)/rf2_32x128_wm1/ -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate +INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate FILE=Vortex.v diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v new file mode 100644 index 00000000..a539b350 --- /dev/null +++ b/rtl/VX_cache/VX_cache.v @@ -0,0 +1,179 @@ +`include "VX_cache_config.v" + + +module VX_cache ( + input wire clk, + input wire reset, + + // Req Info + input wire [`NUMBER_REQUESTS-1:0] core_req_valid, + input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, + input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_writedata, + input wire[2:0] core_req_mem_read, + input wire[2:0] core_req_mem_write, + + // Req meta + input wire [4:0] core_req_rd, + input wire [1:0] core_req_wb, + input wire [`NW_M1:0] core_req_warp_num, + + // Core Writeback + input wire core_no_wb_slot, + output wire [`NUMBER_REQUESTS-1:0] core_wb_valid, + output wire [4:0] core_wb_req_rd, + output wire [1:0] core_wb_req_wb, + output wire [`NW_M1:0] core_wb_warp_num, + output wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, + + + // Dram Fill Response + input wire dram_fill_rsp, + input wire [31:0] dram_fill_rsp_addr, + input wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + + // Dram request + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data +); + + + wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids; + wire [`NUMBER_BANKS-1:0] per_bank_wb_pop; + wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid; + wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; + wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; + wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; + wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data; + + + wire dfqq_full; + wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req; + wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; + + wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; + wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; + wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; + wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; + + VX_cache_dram_req_arb VX_cache_dram_req_arb( + .clk (clk), + .reset (reset), + .dfqq_full (dfqq_full), + .per_bank_dram_fill_req (per_bank_dram_fill_req), + .per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr), + .per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop), + .per_bank_dram_wb_req (per_bank_dram_wb_req), + .per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr), + .per_bank_dram_wb_req_data (per_bank_dram_wb_req_data), + .dram_req (dram_req), + .dram_req_write (dram_req_write), + .dram_req_read (dram_req_read), + .dram_req_addr (dram_req_addr), + .dram_req_size (dram_req_size), + .dram_req_data (dram_req_data) + ); + + + VX_cache_core_req_bank_sel VX_cache_core_req_bank_sel( + .core_req_valid (core_req_valid), + .core_req_addr (core_req_addr), + .per_bank_valids(per_bank_valids) + ); + + + VX_cache_wb_sel_merge VX_cache_core_req_bank_sel( + .per_bank_wb_tid (per_bank_wb_tid), + .per_bank_wb_rd (per_bank_wb_rd), + .per_bank_wb_wb (per_bank_wb_wb), + .per_bank_wb_warp_num(per_bank_wb_warp_num), + .per_bank_wb_data (per_bank_wb_data), + .per_bank_wb_pop (per_bank_wb_pop), + + .core_wb_valid (core_wb_valid), + .core_wb_req_rd (core_wb_req_rd), + .core_wb_req_wb (core_wb_req_wb), + .core_wb_warp_num (core_wb_warp_num), + .core_wb_readdata (core_wb_readdata) + ); + + generate + integer curr_bank; + for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin + wire [`NUMBER_REQUESTS-1:0] curr_bank_valids; + wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; + wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; + wire [4:0] curr_bank_rd; + wire [1:0] curr_bank_wb; + wire [`NW_M1:0] curr_bank_warp_num; + wire [2:0] curr_bank_mem_read; + wire [2:0] curr_bank_mem_write; + + wire curr_bank_wb_pop; + wire [`NUMBER_REQUESTS-1:0] curr_bank_wb_tid; + wire [4:0] curr_bank_wb_rd; + wire [1:0] curr_bank_wb_wb; + wire [`NW_M1:0] curr_bank_wb_warp_num; + wire [31:0] curr_bank_wb_data; + + wire curr_bank_dram_fill_rsp; + wire [31:0] curr_bank_dram_fill_rsp_addr; + wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data; + + wire curr_bank_dfqq_full; + wire curr_bank_dram_fill_req; + wire[31:0] curr_bank_dram_fill_req_addr; + + wire curr_bank_dram_wb_queue_pop; + wire curr_bank_dram_wb_req; + wire[31:0] curr_bank_dram_wb_req_addr; + wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data; + + // Core Req + assign curr_bank_valids = per_bank_valids[curr_bank]; + assign curr_bank_addr = core_req_addr; + assign curr_bank_writedata = core_req_writedata; + assign curr_bank_rd = core_req_rd; + assign curr_bank_wb = core_req_wb; + assign curr_bank_warp_num = core_req_warp_num; + assign curr_bank_mem_read = core_req_mem_read; + assign curr_bank_mem_write = core_req_mem_write; + + // Core WB + assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank]; + assign per_bank_wb_tid [curr_bank] = curr_bank_wb_tid; + assign per_bank_wb_rd [curr_bank] = curr_bank_wb_rd; + assign per_bank_wb_wb [curr_bank] = curr_bank_wb_wb; + assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num; + assign per_bank_wb_data [curr_bank] = curr_bank_wb_data; + + // Dram fill response + assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); + assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; + assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; + + // Dram fill request + assign curr_bank_dfqq_full = dfqq_full; + assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req; + assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; + + // Dram writeback request + assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank]; + assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req; + assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr; + assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data; + + + VX_cache_bank bank ( + + ); + + end + endgenerate + + + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_bank.v b/rtl/VX_cache/VX_cache_bank.v new file mode 100644 index 00000000..1a4b4151 --- /dev/null +++ b/rtl/VX_cache/VX_cache_bank.v @@ -0,0 +1,41 @@ +`include "VX_cache_config.v" + +module VX_cache_bank ( + input wire clk, + input wire reset, + + // Input Core Request + input wire [`NUMBER_REQUESTS-1:0] bank_valids, + input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, + input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [4:0] bank_rd, + input wire [`NW_M1:0] bank_warp_num, + input wire [2:0] bank_mem_read, + input wire [2:0] bank_mem_write, + + // Output Core WB + input wire bank_wb_pop, + output wire [`NUMBER_REQUESTS-1:0] bank_wb_valid, + output wire [4:0] bank_wb_rd, + output wire [1:0] bank_wb_wb, + output wire [`NW_M1:0] bank_wb_warp_num, + output wire [31:0] bank_wb_data, + + // Dram Fill Requests + output wire dram_fill_req, + output wire[31:0] dram_fill_req_addr, + input wire dram_fill_req_queue_full, + + // Dram Fill Response + input wire dram_fill_rsp, + input wire [31:0] dram_fill_addr, + input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + + // Dram WB Requests + input wire dram_wb_queue_pop, + output wire dram_wb_req, + output wire[31:0] dram_wb_req_addr, + output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data +); + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v new file mode 100644 index 00000000..f8bd3634 --- /dev/null +++ b/rtl/VX_cache/VX_cache_config.v @@ -0,0 +1,126 @@ + +`include "../VX_define.h" + + + + +// ========================================= Configurable Knobs ========================================= +// General Cache Knobs + // Size of cache in bytes + `define CACHE_SIZE_BYTES 1024 + // Size of line inside a bank in bytes + `define BANK_LINE_SIZE_BYTES 16 + // Number of banks + `define NUMBER_BANKS 8 + // Size of a word in bytes + `define WORD_SIZE_BYTES 4 + // Number of Word requests per cycle + `define NUMBER_REQUESTS `NT + // Number of cycles to complete stage 2 (read from memory) + `define STAGE_2_CYCLES 1 + +// Queues feeding into banks Knobs + + // Core Request Queue Size + `define REQQ_SIZE `NT*`NW + // Miss Reserv Queue Knob + `define MRVQ_SIZE `REQQ_SIZE + // Dram Fill Rsp Queue Size + `define DFPQ_SIZE 2 + +// Queues for writebacks Knobs + // Core Writeback Queue Size + `define CWBQ_SIZE `REQQ_SIZE + // Dram Writeback Queue Size + `define DWBQ_SIZE 2 + // Dram Fill Req Queue Size + `define DFQQ_SIZE `REQQ_SIZE + +// Dram knobs + `define SIMULATED_DRAM_LATENCY_CYCLES 50 + +// ========================================= Configurable Knobs ========================================= + + +`define vx_clog2_h(value, x) (value == (1 << x)) ? (x) + +`define vx_clog2(value) (value == 0 ) ? 0 : \ + (value == 1 ) ? 1 : \ + `vx_clog2_h(value, 2 ) : \ + `vx_clog2_h(value, 3 ) : \ + `vx_clog2_h(value, 4 ) : \ + `vx_clog2_h(value, 5 ) : \ + `vx_clog2_h(value, 6 ) : \ + `vx_clog2_h(value, 7 ) : \ + `vx_clog2_h(value, 8 ) : \ + `vx_clog2_h(value, 9 ) : \ + `vx_clog2_h(value, 10) : \ + `vx_clog2_h(value, 11) : \ + `vx_clog2_h(value, 12) : \ + `vx_clog2_h(value, 13) : \ + `vx_clog2_h(value, 14) : \ + `vx_clog2_h(value, 15) : \ + `vx_clog2_h(value, 16) : \ + `vx_clog2_h(value, 17) : \ + `vx_clog2_h(value, 18) : \ + `vx_clog2_h(value, 19) : \ + `vx_clog2_h(value, 20) : \ + `vx_clog2_h(value, 21) : \ + `vx_clog2_h(value, 22) : \ + `vx_clog2_h(value, 23) : \ + `vx_clog2_h(value, 24) : \ + `vx_clog2_h(value, 25) : \ + `vx_clog2_h(value, 26) : \ + `vx_clog2_h(value, 27) : \ + `vx_clog2_h(value, 28) : \ + `vx_clog2_h(value, 29) : \ + `vx_clog2_h(value, 30) : \ + `vx_clog2_h(value, 31) : \ + 0 + + +`define BANK_SIZE_BYTES `CACHE_SIZE_BYTES/`NUMBER_BANKS + + +`define BANK_LINE_COUNT `BANK_SIZE_BYTES/`BANK_LINE_SIZE_BYTES +`define BANK_LINE_SIZE_WORDS `BANK_LINE_SIZE_BYTES / `WORD_SIZE_BYTES +`define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0 + +// Offset is fixed +`define OFFSET_SIZE_END 1 +`define OFFSET_ADDR_START 0 +`define OFFSET_ADDR_END 1 +`define OFFSET_ADDR_RNG `OFFSET_ADDR_START:`OFFSET_ADDR_END +`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 + +`define WORD_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_SIZE_WORDS) +`define WORD_SELECT_SIZE_END `WORD_SELECT_NUM_BITS +`define WORD_SELECT_ADDR_START 1+`OFFSET_ADDR_END +`define WORD_SELECT_ADDR_END `WORD_SELECT_SIZE_END+`OFFSET_ADDR_END +`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START +`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:WORD_SELECT_SIZE_END + +`define BANK_SELECT_NUM_BITS `vx_clog2(`NUMBER_BANKS) +`define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS +`define BANK_SELECT_ADDR_START 1+`WORD_SELECT_ADDR_END +`define BANK_SELECT_ADDR_END `BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START +`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START +`define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0 + +`define LINE_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_COUNT) +`define LINE_SELECT_SIZE_END `LINE_SELECT_NUM_BITS +`define LINE_SELECT_ADDR_START 1+`BANK_SELECT_ADDR_END +`define LINE_SELECT_ADDR_END `LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START +`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START +`define LINE_SELECT_SIZE_RNG `LINE_SELECT_SIZE_END-1:0 + +`define TAG_SELECT_NUM_BITS 32-`LINE_SELECT_ADDR_RNG+1 +`define TAG_SELECT_SIZE_END `TAG_SELECT_NUM_BITS +`define TAG_SELECT_ADDR_START 1+`LINE_SELECT_ADDR_RNG +`define TAG_SELECT_ADDR_END `TAG_SELECT_SIZE_END+`TAG_SELECT_ADDR_START +`define TAG_SELECT_ADDR_RNG `TAG_SELECT_ADDR_END:`TAG_SELECT_ADDR_START +`define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0 + + + + diff --git a/rtl/VX_cache/VX_cache_core_req_bank_sel.v b/rtl/VX_cache/VX_cache_core_req_bank_sel.v new file mode 100644 index 00000000..85a324d0 --- /dev/null +++ b/rtl/VX_cache/VX_cache_core_req_bank_sel.v @@ -0,0 +1,25 @@ + + +module VX_cache_core_req_bank_sel ( + input wire [`NUMBER_REQUESTS-1:0] core_req_valid, + input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, + + output reg [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids +); + + + generate + integer curr_req; + always @(*) begin + for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin + if (`NUMBER_BANKS == 1) begin + // If there is only one bank, then only map requests to that bank + per_bank_valids[0][curr_req] <= core_req_valid[curr_req]; + end else begin + per_bank_valids[core_req_addr[`BANK_SELECT_ADDR_RNG]][curr_req] <= core_req_valid[curr_req]; + end + end + end + endgenerate + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_dfq_queue.v b/rtl/VX_cache/VX_cache_dfq_queue.v new file mode 100644 index 00000000..e0af7a2c --- /dev/null +++ b/rtl/VX_cache/VX_cache_dfq_queue.v @@ -0,0 +1,78 @@ +`include "VX_cache_config.v" + +module VX_cache_dfq_queue + ( + input wire clk, + input wire reset, + input wire dfqq_push, + input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req, + input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, + + input wire dfqq_pop, + output wire dfqq_req, + output wire[31:0] dfqq_req_addr, + output wire dfqq_empty, + output wire dfqq_full +); + + wire[`NUMBER_BANKS-1:0] out_per_bank_dram_fill_req; + wire[`NUMBER_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr; + + + reg [`NUMBER_BANKS-1:0] use_per_bank_dram_fill_req; + reg [`NUMBER_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr; + + + wire[`NUMBER_BANKS-1:0] qual_bank_dram_fill_req; + wire[`NUMBER_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr; + + wire[`NUMBER_BANKS-1:0] updated_bank_dram_fill_req; + + wire use_empty = !(|use_per_bank_dram_fill_req); + wire out_empty = !(|out_per_bank_dram_fill_req); + + wire push_qual = dfqq_push && !dfqq_full; + wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty; + VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`dFQQ_SIZE)) dfqq_queue( + .clk (clk), + .reset (reset), + .push (push_qual), + .in_data ({per_bank_dram_fill_req, per_bank_dram_fill_req_addr}), + .pop (pop_qual), + .out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}), + .empty (dfqq_empty), + .full (dfqq_full) + ); + + + + assign qual_bank_dram_fill_req = use_empty ? out_per_bank_dram_fill_req : use_per_bank_dram_fill_req; + assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr; + + wire[`vx_clog2(`NUMBER_BANKS)-1:0] qual_request_index; + wire qual_has_request; + VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + .valids(qual_bank_dram_fill_req), + .index (qual_request_index), + .found (qual_has_request) + ); + + assign dfqq_req = qual_bank_dram_fill_req [qual_request_index]; + assign dfqq_req_addr = qual_bank_dram_fill_req_addr[qual_request_index]; + + assign updated_bank_dram_fill_req = qual_bank_dram_fill_req & (~(1 << qual_request_index)); + + always @(posedge clk or reset) begin + if (reset) begin + use_per_bank_dram_fill_req <= 0; + use_per_bank_dram_fill_req_addr <= 0; + end else begin + if (dfqq_pop && qual_has_request) begin + use_per_bank_dram_fill_req <= updated_bank_dram_fill_req; + use_per_bank_dram_fill_req_addr <= qual_bank_dram_fill_req_addr; + end + end + end + + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v new file mode 100644 index 00000000..eebb5b3e --- /dev/null +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -0,0 +1,68 @@ +`include "VX_cache_config.v" + + +module VX_cache_dram_req_arb ( + input wire clk, + input wire reset, + + + // Fill Request + output wire dfqq_full, + input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req, + input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, + + // DFQ Request + output wire[`NUMBER_BANKS-1] per_bank_dram_wb_queue_pop, + input wire[`NUMBER_BANKS-1] per_bank_dram_wb_req, + input wire[`NUMBER_BANKS-1][31:0] per_bank_dram_wb_req_addr, + input wire[`NUMBER_BANKS-1][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, + + // real Dram request + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data + +); + + + wire dfqq_req; + wire dfqq_req_addr; + wire dfqq_empty; + wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop + wire dfqq_push = (|per_bank_dram_wb_queue_pop); + VX_cache_dfq_queue VX_cache_dfq_queue( + .clk (clk), + .reset (reset), + .dfqq_push (dfqq_push), + .per_bank_dram_fill_req (per_bank_dram_fill_req), + .per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr), + .dfqq_pop (dfqq_pop), + .dfqq_req (dfqq_req), + .dfqq_req_addr (dfqq_req_addr), + .dfqq_empty (dfqq_empty), + .dfqq_full (dfqq_full) + ); + + + wire dwb_valid; + wire[`vx_log2(`NUMBER_BANKS)-1:0] dwb_bank; + VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb( + .valids(per_bank_dram_wb_req), + .index (dwb_bank), + .found (dwb_valid) + ); + + + assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & (~(1 << dwb_bank)); + + + assign dram_req = dwb_valid || dfqq_req; + assign dram_req_write = dwb_valid; + assign dram_req_read = dfqq_req && !dwb_valid; + assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr; + assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v new file mode 100644 index 00000000..83f47e82 --- /dev/null +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -0,0 +1,65 @@ +`include "VX_cache_config.v" + + +module VX_cache_wb_sel_merge ( + + // Per Bank WB + input wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid, + input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, + input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, + input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, + input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data, + output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop, + + + // Core Writeback + input wire core_no_wb_slot, + output reg [`NUMBER_REQUESTS-1:0] core_wb_valid, + output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata + output wire [4:0] core_wb_req_rd, + output wire [1:0] core_wb_req_wb, + output wire [`NW_M1:0] core_wb_warp_num, + +); + + wire [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; + assign per_bank_wb_pop = per_bank_wb_pop_unqual & {`NUMBER_BANKS{core_no_wb_slot}}; + + wire[`NUMBER_BANKS-1:0] bank_wants_wb; + generate + integer curr_bank; + for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin + assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]); + end + endgenerate + + + wire [(`vx_clog2(`NUMBER_BANKS))-1:0] main_bank_index; + wire found_bank; + + VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + .valids(bank_wants_wb), + .index (main_bank_index), + .found (found_bank) + ); + + assign core_wb_req_rd = per_bank_wb_rd [main_bank_index]; + assign core_wb_req_wb = per_bank_wb_wb [main_bank_index]; + assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index]; + + generate + integer this_bank; + for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin + if ((per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) + && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index])) begin + + assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1; + assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; + assign per_bank_wb_pop_unqual[this_bank] = 1; + end else + assign per_bank_wb_pop_unqual[this_bank] = 0; + end + end + endgenerate + +endmodule \ No newline at end of file diff --git a/rtl/VX_generic_queue.v b/rtl/VX_generic_queue.v new file mode 100644 index 00000000..ca383fae --- /dev/null +++ b/rtl/VX_generic_queue.v @@ -0,0 +1,49 @@ + + +module VX_generic_queue + #( + parameter DATAW = 4, + parameter SIZE = 16 + ) + ( + input wire clk, + input wire reset, + input wire push, + input wire[DATAW-1:0] in_data, + + input wire pop, + output wire[DATAW-1:0] out_data, + output wire empty, + output wire full +); + + + reg[SIZE-1:0] data[DATAW-1:0]; + reg[$clog2(SIZE)-1:0] head; + reg[$clog2(SIZE)-1:0] tail; + + assign empty = head == tail; + assign full = head == (tail+1); + + integer i; + always @(posedge clk or reset) begin + if (reset) begin + head <= 0; + tail <= 0; + for (i = 0; i < SIZE; i=i+1) data[i] <= DATAW'0; + end else begin + if (push && !full) begin + data[tail] <= in_data; + tail = tail+1; + end + + if (pop) begin + head = head + 1; + end + + end + end + + assign out_data = data[head]; + +endmodule \ No newline at end of file From 3a970bbe7b171262dc02a812112870e7eaedefac Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 2 Mar 2020 23:24:17 -0800 Subject: [PATCH 10/66] Connected cache to bank --- rtl/VX_cache/VX_bank.v | 42 +++++++++ rtl/VX_cache/VX_cache.v | 122 +++++++++++++++++---------- rtl/VX_cache/VX_cache_bank.v | 41 --------- rtl/VX_cache/VX_cache_wb_sel_merge.v | 24 +++--- 4 files changed, 132 insertions(+), 97 deletions(-) create mode 100644 rtl/VX_cache/VX_bank.v delete mode 100644 rtl/VX_cache/VX_cache_bank.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v new file mode 100644 index 00000000..48dd8e07 --- /dev/null +++ b/rtl/VX_cache/VX_bank.v @@ -0,0 +1,42 @@ +`include "VX_cache_config.v" + +module VX_bank ( + input wire clk, + input wire reset, + + // Input Core Request + input wire [`NUMBER_REQUESTS-1:0] bank_valids, + input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, + input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [4:0] bank_rd, + input wire [1:0] bank_wb, + input wire [`NW_M1:0] bank_warp_num, + input wire [2:0] bank_mem_read, + input wire [2:0] bank_mem_write, + + // Output Core WB + input wire bank_wb_pop, + output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid, + output wire [4:0] bank_wb_rd, + output wire [1:0] bank_wb_wb, + output wire [`NW_M1:0] bank_wb_warp_num, + output wire [31:0] bank_wb_data, + + // Dram Fill Requests + output wire dram_fill_req, + output wire[31:0] dram_fill_req_addr, + input wire dram_fill_req_queue_full, + + // Dram Fill Response + input wire dram_fill_rsp, + input wire [31:0] dram_fill_addr, + input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + + // Dram WB Requests + input wire dram_wb_queue_pop, + output wire dram_wb_req, + output wire[31:0] dram_wb_req_addr, + output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data +); + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index a539b350..487cb8b5 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -41,23 +41,23 @@ module VX_cache ( ); - wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids; - wire [`NUMBER_BANKS-1:0] per_bank_wb_pop; - wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid; - wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; - wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; - wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; - wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data; + wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids; + wire [`NUMBER_BANKS-1:0] per_bank_wb_pop; + wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid; + wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; + wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; + wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; + wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data; - wire dfqq_full; - wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req; - wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; + wire dfqq_full; + wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req; + wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; - wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; - wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; - wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; - wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; + wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; + wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; + wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; + wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; VX_cache_dram_req_arb VX_cache_dram_req_arb( .clk (clk), @@ -103,34 +103,34 @@ module VX_cache ( generate integer curr_bank; for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin - wire [`NUMBER_REQUESTS-1:0] curr_bank_valids; - wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; - wire [4:0] curr_bank_rd; - wire [1:0] curr_bank_wb; - wire [`NW_M1:0] curr_bank_warp_num; - wire [2:0] curr_bank_mem_read; - wire [2:0] curr_bank_mem_write; + wire [`NUMBER_REQUESTS-1:0] curr_bank_valids; + wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; + wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; + wire [4:0] curr_bank_rd; + wire [1:0] curr_bank_wb; + wire [`NW_M1:0] curr_bank_warp_num; + wire [2:0] curr_bank_mem_read; + wire [2:0] curr_bank_mem_write; - wire curr_bank_wb_pop; - wire [`NUMBER_REQUESTS-1:0] curr_bank_wb_tid; - wire [4:0] curr_bank_wb_rd; - wire [1:0] curr_bank_wb_wb; - wire [`NW_M1:0] curr_bank_wb_warp_num; - wire [31:0] curr_bank_wb_data; + wire curr_bank_wb_pop; + wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid; + wire [4:0] curr_bank_wb_rd; + wire [1:0] curr_bank_wb_wb; + wire [`NW_M1:0] curr_bank_wb_warp_num; + wire [31:0] curr_bank_wb_data; - wire curr_bank_dram_fill_rsp; - wire [31:0] curr_bank_dram_fill_rsp_addr; - wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data; + wire curr_bank_dram_fill_rsp; + wire [31:0] curr_bank_dram_fill_rsp_addr; + wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data; - wire curr_bank_dfqq_full; - wire curr_bank_dram_fill_req; - wire[31:0] curr_bank_dram_fill_req_addr; + wire curr_bank_dfqq_full; + wire curr_bank_dram_fill_req; + wire[31:0] curr_bank_dram_fill_req_addr; - wire curr_bank_dram_wb_queue_pop; - wire curr_bank_dram_wb_req; - wire[31:0] curr_bank_dram_wb_req_addr; - wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data; + wire curr_bank_dram_wb_queue_pop; + wire curr_bank_dram_wb_req; + wire[31:0] curr_bank_dram_wb_req_addr; + wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data; // Core Req assign curr_bank_valids = per_bank_valids[curr_bank]; @@ -150,16 +150,16 @@ module VX_cache ( assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num; assign per_bank_wb_data [curr_bank] = curr_bank_wb_data; - // Dram fill response - assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); - assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; - assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; - // Dram fill request assign curr_bank_dfqq_full = dfqq_full; assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req; assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; + // Dram fill response + assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); + assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; + assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; + // Dram writeback request assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank]; assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req; @@ -167,8 +167,42 @@ module VX_cache ( assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data; - VX_cache_bank bank ( + VX_bank bank ( + .clk (clk), + .reset (reset), + // Core req + .bank_valids (curr_bank_valids), + .bank_addr (curr_bank_addr), + .bank_writedata (curr_bank_writedata), + .bank_rd (curr_bank_rd), + .bank_wb (curr_bank_wb), + .bank_warp_num (curr_bank_warp_num), + .bank_mem_read (curr_bank_mem_read), + .bank_mem_write (curr_bank_mem_write), + // Output core wb + .bank_wb_pop (curr_bank_wb_pop), + .bank_wb_tid (curr_bank_wb_tid), + .bank_wb_rd (curr_bank_wb_rd), + .bank_wb_wb (curr_bank_wb_wb), + .bank_wb_warp_num (curr_bank_wb_warp_num), + .bank_wb_data (curr_bank_wb_data), + + // Dram fill req + .dram_fill_req (curr_bank_dram_fill_req), + .dram_fill_req_addr (curr_bank_dram_fill_req_addr), + .dram_fill_req_queue_full(curr_bank_dfqq_full), + + // Dram fill rsp + .dram_fill_rsp (curr_bank_dram_fill_rsp), + .dram_fill_addr (curr_bank_dram_fill_rsp_addr), + .dram_fill_rsp_data (curr_bank_dram_fill_rsp_data), + + // Dram writeback + .dram_wb_queue_pop (curr_bank_dram_wb_queue_pop), + .dram_wb_req (curr_bank_dram_wb_req), + .dram_wb_req_addr (curr_bank_dram_wb_req_addr), + .dram_wb_req_data (curr_bank_dram_wb_req_data) ); end diff --git a/rtl/VX_cache/VX_cache_bank.v b/rtl/VX_cache/VX_cache_bank.v deleted file mode 100644 index 1a4b4151..00000000 --- a/rtl/VX_cache/VX_cache_bank.v +++ /dev/null @@ -1,41 +0,0 @@ -`include "VX_cache_config.v" - -module VX_cache_bank ( - input wire clk, - input wire reset, - - // Input Core Request - input wire [`NUMBER_REQUESTS-1:0] bank_valids, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, - input wire [4:0] bank_rd, - input wire [`NW_M1:0] bank_warp_num, - input wire [2:0] bank_mem_read, - input wire [2:0] bank_mem_write, - - // Output Core WB - input wire bank_wb_pop, - output wire [`NUMBER_REQUESTS-1:0] bank_wb_valid, - output wire [4:0] bank_wb_rd, - output wire [1:0] bank_wb_wb, - output wire [`NW_M1:0] bank_wb_warp_num, - output wire [31:0] bank_wb_data, - - // Dram Fill Requests - output wire dram_fill_req, - output wire[31:0] dram_fill_req_addr, - input wire dram_fill_req_queue_full, - - // Dram Fill Response - input wire dram_fill_rsp, - input wire [31:0] dram_fill_addr, - input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, - - // Dram WB Requests - input wire dram_wb_queue_pop, - output wire dram_wb_req, - output wire[31:0] dram_wb_req_addr, - output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data -); - -endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v index 83f47e82..80f1d39e 100644 --- a/rtl/VX_cache/VX_cache_wb_sel_merge.v +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -4,21 +4,21 @@ module VX_cache_wb_sel_merge ( // Per Bank WB - input wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid, - input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, - input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, - input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, - input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data, - output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop, + input wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid, + input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, + input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, + input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, + input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data, + output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop, // Core Writeback - input wire core_no_wb_slot, - output reg [`NUMBER_REQUESTS-1:0] core_wb_valid, - output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata - output wire [4:0] core_wb_req_rd, - output wire [1:0] core_wb_req_wb, - output wire [`NW_M1:0] core_wb_warp_num, + input wire core_no_wb_slot, + output reg [`NUMBER_REQUESTS-1:0] core_wb_valid, + output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata + output wire [4:0] core_wb_req_rd, + output wire [1:0] core_wb_req_wb, + output wire [`NW_M1:0] core_wb_warp_num, ); From 361fc2c3fe20bd53dc3bec223ad89329a8026b4b Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 02:49:30 -0800 Subject: [PATCH 11/66] Finished st0 --- rtl/VX_cache/VX_bank.v | 172 ++++++++++++++++++++++++++++- rtl/VX_cache/VX_cache.v | 40 +++++-- rtl/VX_cache/VX_cache_config.v | 14 ++- rtl/VX_cache/VX_cache_miss_resrv.v | 109 ++++++++++++++++++ rtl/VX_cache/VX_cache_req_queue.v | 139 +++++++++++++++++++++++ 5 files changed, 457 insertions(+), 17 deletions(-) create mode 100644 rtl/VX_cache/VX_cache_miss_resrv.v create mode 100644 rtl/VX_cache/VX_cache_req_queue.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 48dd8e07..f4232388 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -5,6 +5,7 @@ module VX_bank ( input wire reset, // Input Core Request + input wire delay_req, input wire [`NUMBER_REQUESTS-1:0] bank_valids, input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, @@ -13,6 +14,7 @@ module VX_bank ( input wire [`NW_M1:0] bank_warp_num, input wire [2:0] bank_mem_read, input wire [2:0] bank_mem_write, + output wire reqq_full, // Output Core WB input wire bank_wb_pop, @@ -31,6 +33,7 @@ module VX_bank ( input wire dram_fill_rsp, input wire [31:0] dram_fill_addr, input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + output wire dram_fill_accept, // Dram WB Requests input wire dram_wb_queue_pop, @@ -39,4 +42,171 @@ module VX_bank ( output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data ); -endmodule \ No newline at end of file + + wire dfpq_pop; // Use this + wire dfpq_empty; + wire dfpq_full; + wire[31:0] dfpq_addr_st0; + wire[`BANK_LINE_SIZE_RNG][31:0] dfpq_filldata_st0; + + assign dram_fill_accept = !dfpq_full; + + VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( + .clk (clk), + .reset (reset), + .push (dram_fill_rsp), + .in_data ({dram_fill_addr, dram_fill_rsp_data}), + .pop (dfpq_pop), + .out_data({dfpq_addr_st0, dfpq_filldata_st0}), + .empty (dfpq_empty), + .full (dfpq_full) + ); + + + wire reqq_pop; // Use this + wire reqq_push; + wire reqq_empty; + wire reqq_req_st0; + wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0; + wire [31:0] reqq_req_addr_st0; + wire [31:0] reqq_req_writeword_st0; + wire [4:0] reqq_req_rd_st0; + wire [1:0] reqq_req_wb_st0; + wire [`NW_M1:0] reqq_req_warp_num_st0; + wire [2:0] reqq_req_mem_read_st0; + wire [2:0] reqq_req_mem_write_st0; + + assign reqq_push = !delay_req && (|bank_valids); + + VX_cache_req_queue mrvq_queue( + .clk (clk), + .reset (reset), + // Enqueue + .reqq_push (reqq_push), + .bank_valids (bank_valids), + .bank_addr (bank_addr), + .bank_writedata (bank_writedata), + .bank_rd (bank_rd), + .bank_wb (bank_wb), + .bank_warp_num (bank_warp_num), + .bank_mem_read (bank_mem_read), + .bank_mem_write (bank_mem_write), + + // Dequeue + .reqq_pop (reqq_pop), + .reqq_req_st0 (reqq_req_st0), + .reqq_req_tid_st0 (reqq_req_tid_st0), + .reqq_req_addr_st0 (reqq_req_addr_st0), + .reqq_req_writedata_st0(reqq_req_writeword_st0), + .reqq_req_rd_st0 (reqq_req_rd_st0), + .reqq_req_wb_st0 (reqq_req_wb_st0), + .reqq_req_warp_num_st0 (reqq_req_warp_num_st0), + .reqq_req_mem_read_st0 (reqq_req_mem_read_st0), + .reqq_req_mem_write_st0(reqq_req_mem_write_st0), + .reqq_empty (reqq_empty), + .reqq_full (reqq_full) + ); + + wire mrvq_pop; // Use this + wire mrvq_full; + wire mrvq_valid_st0; + wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] mrvq_tid_st0; + wire [31:0] mrvq_addr_st0; + wire [31:0] mrvq_writeword_st0; + wire [4:0] mrvq_rd_st0; + wire [1:0] mrvq_wb_st0; + wire [`NW_M1:0] mrvq_warp_num_st0; + wire [2:0] mrvq_mem_read_st0; + wire [2:0] mrvq_mem_write_st0; + + VX_cache_miss_resrv mrvq_queue( + .clk (clk), + .reset (reset), + // Enqueue + .miss_add (miss_add), // Need to do all + .miss_add_addr (miss_add_addr), + .miss_add_data (miss_add_data), + .miss_add_tid (miss_add_tid), + .miss_add_rd (miss_add_rd), + .miss_add_wb (miss_add_wb), + .miss_add_warp_num (miss_add_warp_num), + .miss_add_mem_read (miss_add_mem_read), + .miss_add_mem_write (miss_add_mem_write), + .miss_resrv_full (mrvq_full) + + // Broadcast + .is_fill_st1 (is_fill_st1), + .fill_addr_st1 (addr_st1), + + // Dequeue + .miss_resrv_pop (mrvq_pop), + .miss_resrv_valid_st0 (mrvq_valid_st0), + .miss_resrv_addr_st0 (mrvq_addr_st0), + .miss_resrv_data_st0 (mrvq_writeword_st0), + .miss_resrv_tid_st0 (mrvq_tid_st0), + .miss_resrv_rd_st0 (mrvq_rd_st0), + .miss_resrv_wb_st0 (mrvq_wb_st0), + .miss_resrv_warp_num_st0 (mrvq_warp_num_st0), + .miss_resrv_mem_read_st0 (mrvq_mem_read_st0), + .miss_resrv_mem_write_st0(mrvq_mem_write_st0) + ); + + wire stall_st0; + wire stall_st1; + wire stall_st2; + + assign stall_st1 = stall_st2; + assign stall_st0 = stall_st1; + + assign dfpq_pop = !dfpq_empty && !stall_st0; + assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_st0; + assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_st0; + + + wire qual_is_fill_st0; + wire qual_valid_st0; + wire [31:0] qual_addr_st0; + wire [31:0] qual_writeword_st0; + wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0; + wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0; + + wire is_fill_st1; + wire valid_st1; + wire [31:0] addr_st1; + wire [31:0] writeword_st1; + wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1; + wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1; + + assign qual_is_fill_st0 = dfpq_pop; + assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop; + + assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 : + mrvq_pop ? mrvq_addr_st0 : + reqq_pop ? reqq_req_addr_st0 : + 0; + + assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 : + reqq_pop ? reqq_req_writeword_st0 : + 0; + + assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0; + + assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0, mrvq_wb_st0, mrvq_warp_num_st0, mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} : + reqq_pop ? {reqq_rd_st0, reqq_wb_st0, reqq_warp_num_st0, reqq_mem_read_st0, reqq_mem_write_st0, reqq_tid_st0} : + 0; + + VX_generic_register #(.N(1)) s0_1 ( + .clk (clk), + .reset(reset), + .stall(stall_st1), + .flush(0), + .in ({qual_is_fill_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_writedata_st0, qual_inst_meta_st0}), + .out ({is_fill_st1 , valid_st1 , addr_st1 , writeword_st1 , writedata_st1 , inst_meta_st1 }) + ); + +endmodule + + + + + diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 487cb8b5..8ed074f8 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -16,6 +16,7 @@ module VX_cache ( input wire [4:0] core_req_rd, input wire [1:0] core_req_wb, input wire [`NW_M1:0] core_req_warp_num, + output wire delay_req, // Core Writeback input wire core_no_wb_slot, @@ -30,6 +31,7 @@ module VX_cache ( input wire dram_fill_rsp, input wire [31:0] dram_fill_rsp_addr, input wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + output wire dram_fill_accept, // Dram request output wire dram_req, @@ -53,12 +55,20 @@ module VX_cache ( wire dfqq_full; wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req; wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; + wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_accept; wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; + wire[`NUMBER_BANKS-1:0] per_bank_reqq_full; + + assign delay_req = (|per_bank_reqq_full); + + + assign dram_fill_accept = (`NUMBER_BANKS == 1) ? dram_fill_accept[0] : dram_fill_accept[dram_fill_addr[`BANK_SELECT_ADDR_RNG]]; + VX_cache_dram_req_arb VX_cache_dram_req_arb( .clk (clk), .reset (reset), @@ -122,6 +132,7 @@ module VX_cache ( wire curr_bank_dram_fill_rsp; wire [31:0] curr_bank_dram_fill_rsp_addr; wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data; + wire curr_bank_dram_fill_accept; wire curr_bank_dfqq_full; wire curr_bank_dram_fill_req; @@ -132,15 +143,18 @@ module VX_cache ( wire[31:0] curr_bank_dram_wb_req_addr; wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data; + wire curr_bank_reqq_full; + // Core Req - assign curr_bank_valids = per_bank_valids[curr_bank]; - assign curr_bank_addr = core_req_addr; - assign curr_bank_writedata = core_req_writedata; - assign curr_bank_rd = core_req_rd; - assign curr_bank_wb = core_req_wb; - assign curr_bank_warp_num = core_req_warp_num; - assign curr_bank_mem_read = core_req_mem_read; - assign curr_bank_mem_write = core_req_mem_write; + assign curr_bank_valids = per_bank_valids[curr_bank]; + assign curr_bank_addr = core_req_addr; + assign curr_bank_writedata = core_req_writedata; + assign curr_bank_rd = core_req_rd; + assign curr_bank_wb = core_req_wb; + assign curr_bank_warp_num = core_req_warp_num; + assign curr_bank_mem_read = core_req_mem_read; + assign curr_bank_mem_write = core_req_mem_write; + assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full; // Core WB assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank]; @@ -156,9 +170,10 @@ module VX_cache ( assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; // Dram fill response - assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); - assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; - assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; + assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); + assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; + assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; + assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept; // Dram writeback request assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank]; @@ -171,6 +186,7 @@ module VX_cache ( .clk (clk), .reset (reset), // Core req + .delay_req (delay_req), .bank_valids (curr_bank_valids), .bank_addr (curr_bank_addr), .bank_writedata (curr_bank_writedata), @@ -179,6 +195,7 @@ module VX_cache ( .bank_warp_num (curr_bank_warp_num), .bank_mem_read (curr_bank_mem_read), .bank_mem_write (curr_bank_mem_write), + .reqq_full (curr_bank_reqq_full), // Output core wb .bank_wb_pop (curr_bank_wb_pop), @@ -197,6 +214,7 @@ module VX_cache ( .dram_fill_rsp (curr_bank_dram_fill_rsp), .dram_fill_addr (curr_bank_dram_fill_rsp_addr), .dram_fill_rsp_data (curr_bank_dram_fill_rsp_data), + .dram_fill_accept (curr_bank_dram_fill_accept), // Dram writeback .dram_wb_queue_pop (curr_bank_dram_wb_queue_pop), diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index f8bd3634..10b1ddd9 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -10,16 +10,16 @@ `define CACHE_SIZE_BYTES 1024 // Size of line inside a bank in bytes `define BANK_LINE_SIZE_BYTES 16 - // Number of banks + // Number of banks {1, 2, 4, 8,...} `define NUMBER_BANKS 8 // Size of a word in bytes `define WORD_SIZE_BYTES 4 - // Number of Word requests per cycle + // Number of Word requests per cycle {1, 2, 4, 8, ...} `define NUMBER_REQUESTS `NT // Number of cycles to complete stage 2 (read from memory) `define STAGE_2_CYCLES 1 -// Queues feeding into banks Knobs +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size `define REQQ_SIZE `NT*`NW @@ -28,11 +28,11 @@ // Dram Fill Rsp Queue Size `define DFPQ_SIZE 2 -// Queues for writebacks Knobs +// Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size `define CWBQ_SIZE `REQQ_SIZE // Dram Writeback Queue Size - `define DWBQ_SIZE 2 + `define DWBQ_SIZE 4 // Dram Fill Req Queue Size `define DFQQ_SIZE `REQQ_SIZE @@ -41,6 +41,10 @@ // ========================================= Configurable Knobs ========================================= +// data tid rd wb warp_num read write +`define MRVQ_METADATA_SIZE (32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) + +`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + `vx_clog2(`NUMBER_REQUESTS)) `define vx_clog2_h(value, x) (value == (1 << x)) ? (x) diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v new file mode 100644 index 00000000..17df7f77 --- /dev/null +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -0,0 +1,109 @@ + +`include "VX_cache_config.v" + +module VX_cache_miss_resrv ( + input wire clk, + input wire reset, + + // Miss enqueue + input wire miss_add, + input wire[31:0] miss_add_addr, + input wire[31:0] miss_add_data, + input wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid, + input wire[4:0] miss_add_rd, + input wire[1:0] miss_add_wb, + input wire[`NW_M1:0] miss_add_warp_num, + input wire[2:0] miss_add_mem_read, + input wire[2:0] miss_add_mem_write, + output wire miss_resrv_full, + + // Broadcast Fill + input wire is_fill_st1, + input wire[31:0] fill_addr_st1, + + // Miss dequeue + input wire miss_resrv_pop, + output wire miss_resrv_valid_st0, + output wire[31:0] miss_resrv_addr_st0, + output wire[31:0] miss_resrv_data_st0, + output wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, + output wire[4:0] miss_resrv_rd_st0, + output wire[1:0] miss_resrv_wb_st0, + output wire[`NW_M1:0] miss_resrv_warp_num_st0, + output wire[2:0] miss_resrv_mem_read_st0, + output wire[2:0] miss_resrv_mem_write_st0 + +); + + // Size of metadata = 32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[`MRVQ_SIZE-1:0]; + reg[`MRVQ_SIZE-1:0][31:0] addr_table; + reg[`MRVQ_SIZE-1:0] valid_table; + reg[`MRVQ_SIZE-1:0] ready_table; + + + assign miss_resrv_full = !(&valid_table); + + + wire enqueue_possible; + wire[`vx_clog2(`MRVQ_SIZE)-1:0] enqueue_index; + VX_generic_priority_encoder #(.N(`MRVQ_SIZE)) enqueue_picker( + .valids(~valid_table), + .index (enqueue_index), + .found (enqueue_possible) + ); + + reg[`MRVQ_SIZE-1:0] make_ready; + genvar curr_e; + generate + for (curr_e = 0; curr_e < `MRVQ_SIZE; curr_e=curr_e+1) begin + assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] + && addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START]; + end + endgenerate + + wire dequeue_possible; + wire[`vx_clog2(`MRVQ_SIZE)-1:0] dequeue_index; + wire[`MRVQ_SIZE-1:0] dequeue_valid = valid_table & ready_table; + VX_generic_priority_encoder #(.N(`MRVQ_SIZE)) dequeue_picker( + .valids(dequeue_valid), + .index (dequeue_index), + .found (dequeue_possible) + ); + + assign miss_resrv_valid_st0 = dequeue_possible; + assign miss_resrv_addr_st0 = addr_table[dequeue_index]; + assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index]; + + wire update_ready = (|make_ready); + integer i; + always @(posedge clk or reset) begin + if (reset) begin + for (i = 0; i < `MRVQ_SIZE; i=i+1) metadata_table[i] <= 0; + valid_table <= 0; + ready_table <= 0; + addr_table <= 0; + end else begin + if (miss_add && enqueue_possible) begin + valid_table[enqueue_index] <= 1; + ready_table[enqueue_index] <= 0; + addr_table[enqueue_index] <= miss_add_addr; + metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write}; + end + + if (update_ready) begin + ready_table = ready_table | make_ready; + end + + if (miss_resrv_pop && dequeue_possible) begin + valid_table[dequeue_index] <= 0; + ready_table[dequeue_index] <= 0; + addr_table[dequeue_index] <= 0; + metadata_table[dequeue_index] <= 0; + end + + end + end + + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v new file mode 100644 index 00000000..422203f0 --- /dev/null +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -0,0 +1,139 @@ + +`include "VX_cache_config.v" + +module VX_cache_req_queue ( + input wire clk, + input wire reset, + + // Enqueue Data + input wire reqq_push, + input wire [`NUMBER_REQUESTS-1:0] bank_valids, + input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, + input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [4:0] bank_rd, + input wire [1:0] bank_wb, + input wire [`NW_M1:0] bank_warp_num, + input wire [2:0] bank_mem_read, + input wire [2:0] bank_mem_write, + + // Dequeue Data + input wire reqq_pop, + output wire reqq_req_st0, + output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0, + output wire [31:0] reqq_req_addr_st0, + output wire [31:0] reqq_req_writedata_st0, + output wire [4:0] reqq_req_rd_st0, + output wire [1:0] reqq_req_wb_st0, + output wire [`NW_M1:0] reqq_req_warp_num_st0, + output wire [2:0] reqq_req_mem_read_st0, + output wire [2:0] reqq_req_mem_write_st0, + + // State Data + output wire reqq_empty, + output wire reqq_full +); + + wire [`NUMBER_REQUESTS-1:0] out_per_valids; + wire [`NUMBER_REQUESTS-1:0][31:0] out_per_addr; + wire [`NUMBER_REQUESTS-1:0][31:0] out_per_writedata; + wire [4:0] out_per_rd; + wire [1:0] out_per_wb; + wire [`NW_M1:0] out_per_warp_num; + wire [2:0] out_per_mem_read; + wire [2:0] out_per_mem_write; + + + reg [`NUMBER_REQUESTS-1:0] use_per_valids; + reg [`NUMBER_REQUESTS-1:0][31:0] use_per_addr; + reg [`NUMBER_REQUESTS-1:0][31:0] use_per_writedata; + reg [4:0] use_per_rd; + reg [1:0] use_per_wb; + reg [`NW_M1:0] use_per_warp_num; + reg [2:0] use_per_mem_read; + reg [2:0] use_per_mem_write; + + + wire [`NUMBER_REQUESTS-1:0] qual_valids; + wire [`NUMBER_REQUESTS-1:0][31:0] qual_addr; + wire [`NUMBER_REQUESTS-1:0][31:0] qual_writedata; + wire [4:0] qual_rd; + wire [1:0] qual_wb; + wire [`NW_M1:0] qual_warp_num; + wire [2:0] qual_mem_read; + wire [2:0] qual_mem_write; + + wire[`NUMBER_REQUESTS-1:0] updated_valids; + + wire use_empty = !(|use_per_valids); + wire out_empty = !(|out_per_valids); + + wire push_qual = reqq_push && !reqq_full; + wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty; + VX_generic_queue #(.DATAW(`NUMBER_REQUESTS * (1+32+32+5+2+(`NW_M1+1)+3+3)), .SIZE(`REQQ_SIZE)) reqq_queue( + .clk (clk), + .reset (reset), + .push (push_qual), + .in_data ({bank_valids, bank_addr, bank_writedata, bank_rd, bank_wb, bank_warp_num, bank_mem_read, bank_mem_write}), + .pop (pop_qual), + .out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write}), + .empty (reqq_empty), + .full (reqq_full) + ); + + + + assign qual_valids = use_empty ? out_per_valids : use_per_valids; + assign qual_addr = use_empty ? out_per_addr : use_per_addr; + assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata; + assign qual_rd = use_empty ? out_per_rd : use_per_rd; + assign qual_wb = use_empty ? out_per_wb : use_per_wb; + assign qual_warp_num = use_empty ? out_per_warp_num : use_per_warp_num; + assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read; + assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write; + + wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] qual_request_index; + wire qual_has_request; + VX_generic_priority_encoder #(.N(`NUMBER_REQUESTS)) VX_sel_bank( + .valids(qual_valids), + .index (qual_request_index), + .found (qual_has_request) + ); + + assign reqq_req_st0 = qual_has_request; + assign reqq_req_tid_st0 = qual_request_index; + assign reqq_req_addr_st0 = qual_addr [qual_request_index]; + assign reqq_req_writedata_st0 = qual_writedata[qual_request_index]; + assign reqq_req_rd_st0 = qual_rd; + assign reqq_req_wb_st0 = qual_wb; + assign reqq_req_warp_num_st0 = qual_warp_num + assign reqq_req_mem_read_st0 = qual_mem_read; + assign reqq_req_mem_write_st0 = qual_mem_write; + + assign updated_valids = qual_valids & (~(1 << qual_request_index)); + + always @(posedge clk or reset) begin + if (reset) begin + use_per_valids <= 0; + use_per_addr <= 0; + use_per_writedata <= 0; + use_per_rd <= 0; + use_per_wb <= 0; + use_per_warp_num <= 0; + use_per_mem_read <= 0; + use_per_mem_write <= 0; + end else begin + if (reqq_pop && qual_has_request) begin + use_per_valids <= updated_valids; + use_per_addr <= qual_addr; + use_per_writedata <= qual_writedata; + use_per_rd <= qual_rd; + use_per_wb <= qual_wb; + use_per_warp_num <= qual_warp_num; + use_per_mem_read <= qual_mem_read; + use_per_mem_write <= qual_mem_write; + end + end + end + + +endmodule \ No newline at end of file From 80af320fdb031ba3c14744ae6fa730bb9f383d3c Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 16:57:05 -0800 Subject: [PATCH 12/66] Before fixing miss rsrv for ST->LD sequences --- rtl/VX_cache/VX_bank.v | 80 ++++++++++++++++++++++------ rtl/VX_cache/VX_cache.v | 2 + rtl/VX_cache/VX_cache_config.v | 6 +-- rtl/VX_cache/VX_cache_dram_req_arb.v | 1 + rtl/VX_cache/VX_tag_data_access.v | 26 +++++++++ rtl/VX_cache/VX_tag_data_structure.v | 15 ++++++ 6 files changed, 110 insertions(+), 20 deletions(-) create mode 100644 rtl/VX_cache/VX_tag_data_access.v create mode 100644 rtl/VX_cache/VX_tag_data_structure.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index f4232388..cf4e0e8a 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -43,7 +43,7 @@ module VX_bank ( ); - wire dfpq_pop; // Use this + wire dfpq_pop; wire dfpq_empty; wire dfpq_full; wire[31:0] dfpq_addr_st0; @@ -63,7 +63,7 @@ module VX_bank ( ); - wire reqq_pop; // Use this + wire reqq_pop; wire reqq_push; wire reqq_empty; wire reqq_req_st0; @@ -107,7 +107,7 @@ module VX_bank ( .reqq_full (reqq_full) ); - wire mrvq_pop; // Use this + wire mrvq_pop; wire mrvq_full; wire mrvq_valid_st0; wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] mrvq_tid_st0; @@ -136,7 +136,7 @@ module VX_bank ( // Broadcast .is_fill_st1 (is_fill_st1), - .fill_addr_st1 (addr_st1), + .fill_addr_st1 (addr_st1[0]), // Dequeue .miss_resrv_pop (mrvq_pop), @@ -170,12 +170,12 @@ module VX_bank ( wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0; wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0; - wire is_fill_st1; - wire valid_st1; - wire [31:0] addr_st1; - wire [31:0] writeword_st1; - wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1; - wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1; + wire valid_st1[`STAGE_1_CYCLES-1:0]; + wire [31:0] addr_st1[`STAGE_1_CYCLES-1:0]; + wire [31:0] writeword_st1[`STAGE_1_CYCLES-1:0]; + wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1[`STAGE_1_CYCLES-1:0]; + wire is_fill_st1[`STAGE_1_CYCLES-1:0]; + wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1[`STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop; @@ -195,15 +195,61 @@ module VX_bank ( reqq_pop ? {reqq_rd_st0, reqq_wb_st0, reqq_warp_num_st0, reqq_mem_read_st0, reqq_mem_write_st0, reqq_tid_st0} : 0; - VX_generic_register #(.N(1)) s0_1 ( - .clk (clk), - .reset(reset), - .stall(stall_st1), - .flush(0), - .in ({qual_is_fill_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_writedata_st0, qual_inst_meta_st0}), - .out ({is_fill_st1 , valid_st1 , addr_st1 , writeword_st1 , writedata_st1 , inst_meta_st1 }) + VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_c0 ( + .clk (clk), + .reset(reset), + .stall(stall_st1), + .flush(0), + .in ({qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), + .out ({valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]}) + ); + + genvar curr_stage; + generate + for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin + VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_cc ( + .clk (clk), + .reset(reset), + .stall(stall_st1), + .flush(is_fill_st1), + .in ({valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}), + .out ({valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] }) + ); + end + endgenerate + + + wire[31:0] readword_st1e; + wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e; + wire miss_st1e; + + VX_tag_data_access VX_tag_data_access( + .clk (clk), + .reset (reset), + .valid_st10 (valid_st10), + + // Read start + .readaddr_st10 (addr_st1[0]), + + // Write stuff + .writeaddr_st1e(addr_st1[`STAGE_1_CYCLES-1]), + .writeword_st1e(writeword_st1[`STAGE_1_CYCLES-1]), + .mem_write_st1e(mem_write_st1e), // TODO + + + // Fill info + .is_fill_st1e (is_fill_st1[`STAGE_1_CYCLES-1]), + .filldata_st1e (writedata_st1[`STAGE_1_CYCLES-1]), + + // Read stuff + result + .mem_read_st1e (mem_read_st1e), // TODO + .readword_st1e (readword_st1e), + .readdata_st1e (readdata_st1e), + .miss_st1e (miss_st1e), ); + + endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 8ed074f8..b0e139d9 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -1,5 +1,7 @@ `include "VX_cache_config.v" +`include "VX_cache_config.v" + module VX_cache ( input wire clk, diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 10b1ddd9..fbec7e5c 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -16,8 +16,8 @@ `define WORD_SIZE_BYTES 4 // Number of Word requests per cycle {1, 2, 4, 8, ...} `define NUMBER_REQUESTS `NT - // Number of cycles to complete stage 2 (read from memory) - `define STAGE_2_CYCLES 1 + // Number of cycles to complete stage 1 (read from memory) + `define STAGE_1_CYCLES 2 // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -94,7 +94,7 @@ `define OFFSET_SIZE_END 1 `define OFFSET_ADDR_START 0 `define OFFSET_ADDR_END 1 -`define OFFSET_ADDR_RNG `OFFSET_ADDR_START:`OFFSET_ADDR_END +`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START `define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 `define WORD_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_SIZE_WORDS) diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index eebb5b3e..9c54c94e 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -63,6 +63,7 @@ module VX_cache_dram_req_arb ( assign dram_req_write = dwb_valid; assign dram_req_read = dfqq_req && !dwb_valid; assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr; + assign dram_req_size = `BANK_LINE_SIZE_BYTES; assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v new file mode 100644 index 00000000..47d513d0 --- /dev/null +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -0,0 +1,26 @@ +`include "VX_cache_config.v" + +module VX_tag_data_access ( + input wire clk, + input wire reset, + + input wire valid_st10, + input wire is_fill_st10, + input wire[31:0] readaddr_st10, + input wire[`BANK_LINE_SIZE_RNG][31:0] filldata_st10, + + input wire[31:0] writeaddr_st1e, + input wire[31:0] writeword_st1e, + input wire[2:0] mem_write_st1e, + input wire[2:0] mem_read_st1e, + + output wire[31:0] readword_st1e, + output wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e, + output wire miss_st1e + +); + + + reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[`STAGE_1_CYCLES-1:0]; + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v new file mode 100644 index 00000000..4877a61f --- /dev/null +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -0,0 +1,15 @@ +module VX_tag_data_structure ( + input wire clk, + + input wire[31:0] readaddr, + output wire[`BANK_LINE_SIZE_RNG][31:0] readdata, + + input wire[`BANK_LINE_SIZE_RNG][3] writeenable, + input wire[31:0] writeaddr, + input wire[`BANK_LINE_SIZE_RNG][31:0] writedata + +); + +endmodule + +// OFFSET_SIZE_RNG \ No newline at end of file From 8ece8d889370f852ef40d7685112fe161e66840d Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 17:04:39 -0800 Subject: [PATCH 13/66] Fixed miss reserv to support ST->LD sequences --- rtl/VX_cache/VX_cache_miss_resrv.v | 34 ++++++++++++------------------ 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v index 17df7f77..5bed7ee0 100644 --- a/rtl/VX_cache/VX_cache_miss_resrv.v +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -36,22 +36,19 @@ module VX_cache_miss_resrv ( ); // Size of metadata = 32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) - reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[`MRVQ_SIZE-1:0]; - reg[`MRVQ_SIZE-1:0][31:0] addr_table; - reg[`MRVQ_SIZE-1:0] valid_table; - reg[`MRVQ_SIZE-1:0] ready_table; + reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[`MRVQ_SIZE-1:0]; + reg[`MRVQ_SIZE-1:0][31:0] addr_table; + reg[`MRVQ_SIZE-1:0] valid_table; + reg[`MRVQ_SIZE-1:0] ready_table; + reg[`vx_clog2(`MRVQ_SIZE)-1:0] head_ptr; + reg[`vx_clog2(`MRVQ_SIZE)-1:0] tail_ptr; - assign miss_resrv_full = !(&valid_table); + assign miss_resrv_full = (tail_ptr+1) == head_ptr; - wire enqueue_possible; - wire[`vx_clog2(`MRVQ_SIZE)-1:0] enqueue_index; - VX_generic_priority_encoder #(.N(`MRVQ_SIZE)) enqueue_picker( - .valids(~valid_table), - .index (enqueue_index), - .found (enqueue_possible) - ); + wire enqueue_possible = !miss_resrv_full; + wire[`vx_clog2(`MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; reg[`MRVQ_SIZE-1:0] make_ready; genvar curr_e; @@ -62,14 +59,9 @@ module VX_cache_miss_resrv ( end endgenerate - wire dequeue_possible; - wire[`vx_clog2(`MRVQ_SIZE)-1:0] dequeue_index; - wire[`MRVQ_SIZE-1:0] dequeue_valid = valid_table & ready_table; - VX_generic_priority_encoder #(.N(`MRVQ_SIZE)) dequeue_picker( - .valids(dequeue_valid), - .index (dequeue_index), - .found (dequeue_possible) - ); + + wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; + wire[`vx_clog2(`MRVQ_SIZE)-1:0] dequeue_index = head_ptr; assign miss_resrv_valid_st0 = dequeue_possible; assign miss_resrv_addr_st0 = addr_table[dequeue_index]; @@ -89,6 +81,7 @@ module VX_cache_miss_resrv ( ready_table[enqueue_index] <= 0; addr_table[enqueue_index] <= miss_add_addr; metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write}; + tail_ptr <= tail_ptr + 1; end if (update_ready) begin @@ -100,6 +93,7 @@ module VX_cache_miss_resrv ( ready_table[dequeue_index] <= 0; addr_table[dequeue_index] <= 0; metadata_table[dequeue_index] <= 0; + head_ptr <= head_ptr + 1; end end From a47f7c11ecfa10f7b53896d4a5e33b7af9329d2d Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 19:42:33 -0800 Subject: [PATCH 14/66] Finished cache, dram imp + interfaces left --- rtl/VX_cache/VX_bank.v | 140 ++++++++++++++++++---- rtl/VX_cache/VX_cache.v | 2 - rtl/VX_cache/VX_tag_data_access.v | 173 ++++++++++++++++++++++++++- rtl/VX_cache/VX_tag_data_structure.v | 52 ++++++-- 4 files changed, 329 insertions(+), 38 deletions(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index cf4e0e8a..e29c26f9 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -119,6 +119,16 @@ module VX_bank ( wire [2:0] mrvq_mem_read_st0; wire [2:0] mrvq_mem_write_st0; + wire miss_add; + wire[31:0] miss_add_addr; + wire[31:0] miss_add_data; + wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid; + wire[4:0] miss_add_rd; + wire[1:0] miss_add_wb; + wire[`NW_M1:0] miss_add_warp_num; + wire[2:0] miss_add_mem_read; + wire[2:0] miss_add_mem_write; + VX_cache_miss_resrv mrvq_queue( .clk (clk), .reset (reset), @@ -151,16 +161,12 @@ module VX_bank ( .miss_resrv_mem_write_st0(mrvq_mem_write_st0) ); - wire stall_st0; - wire stall_st1; - wire stall_st2; + wire stall_bank_pipe; - assign stall_st1 = stall_st2; - assign stall_st0 = stall_st1; - assign dfpq_pop = !dfpq_empty && !stall_st0; - assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_st0; - assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_st0; + assign dfpq_pop = !dfpq_empty && !stall_bank_pipe; + assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe; + assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0]; wire qual_is_fill_st0; @@ -191,14 +197,14 @@ module VX_bank ( assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0; - assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0, mrvq_wb_st0, mrvq_warp_num_st0, mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} : - reqq_pop ? {reqq_rd_st0, reqq_wb_st0, reqq_warp_num_st0, reqq_mem_read_st0, reqq_mem_write_st0, reqq_tid_st0} : + assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } : + reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} : 0; VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_c0 ( .clk (clk), .reset(reset), - .stall(stall_st1), + .stall(stall_bank_pipe), .flush(0), .in ({qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), .out ({valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]}) @@ -210,8 +216,8 @@ module VX_bank ( VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_cc ( .clk (clk), .reset(reset), - .stall(stall_st1), - .flush(is_fill_st1), + .stall(stall_bank_pipe), + .flush(0), .in ({valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}), .out ({valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] }) ); @@ -221,34 +227,122 @@ module VX_bank ( wire[31:0] readword_st1e; wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e; + wire[`TAG_SELECT_SIZE_RNG] readtag_st1e; wire miss_st1e; + wire dirty_st1e; + + + wire [4:0] rd_st1e; + wire [1:0] wb_st1e; + wire [`NW_M1:0] warp_num_st1e; + wire [2:0] mem_read_st1e; + wire [2:0] mem_write_st1e; + wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] tid_st1e; + + assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[`STAGE_1_CYCLES-1]; + VX_tag_data_access VX_tag_data_access( .clk (clk), .reset (reset), - .valid_st10 (valid_st10), + .stall (stall), - // Read start + // Initial Read .readaddr_st10 (addr_st1[0]), - // Write stuff + // Actual Read/Write + .valid_req_st1e(valid_st1[`STAGE_1_CYCLES-1]), + .writefill_st1e(is_fill_st1[`STAGE_1_CYCLES-1]), .writeaddr_st1e(addr_st1[`STAGE_1_CYCLES-1]), .writeword_st1e(writeword_st1[`STAGE_1_CYCLES-1]), - .mem_write_st1e(mem_write_st1e), // TODO + .writedata_st1e(writedata_st1[`STAGE_1_CYCLES-1]), + .mem_write_st1e(mem_write_st1e), + .mem_read_st1e (mem_read_st1e), - // Fill info - .is_fill_st1e (is_fill_st1[`STAGE_1_CYCLES-1]), - .filldata_st1e (writedata_st1[`STAGE_1_CYCLES-1]), - - // Read stuff + result - .mem_read_st1e (mem_read_st1e), // TODO + // Read Data .readword_st1e (readword_st1e), .readdata_st1e (readdata_st1e), + .readtag_st1e (readtag_st1e), .miss_st1e (miss_st1e), + .dirty_st1e (dirty_st1e) + ); + + wire qual_valid_st1e_2 = valid_st1[`STAGE_1_CYCLES-1] && !is_fill_st1[`STAGE_1_CYCLES-1]; + + wire valid_st2; + wire[31:0] addr_st2; + wire[31:0] writeword_st2; + wire[31:0] readword_st2; + wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st2; + wire miss_st2; + wire dirty_st2; + wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2; + wire[`TAG_SELECT_SIZE_RNG] readtag_st2; + + VX_generic_register #(.N( 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 ( + .clk (clk), + .reset(reset), + .stall(stall_bank_pipe), + .flush(0), + .in ({qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), + .out ({valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) ); + // Enqueue to miss reserv if it's a valid miss + assign miss_add = valid_st2 && miss_st2; + assign miss_add_addr = addr_st2; + assign miss_add_data = writeword_st2; + assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2; + + + // Enqueue to CWB Queue + wire cwbq_push = valid_st2 && !miss_st2; + wire [31:0] cwbq_data = readword_st2; + wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; + wire [4:0] cwbq_rd = miss_add_rd; + wire [1:0] cwbq_wb = miss_add_wb; + wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num; + + wire cwbq_full; + wire cwbq_empty; + VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( + .clk (clk), + .reset (reset), + + .push (cwbq_push), + .in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data}), + + .pop (bank_wb_pop), + .out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data}), + .empty (cwbq_empty), + .full (cwbq_full) + ); + + // Enqueue to DWB Queue + wire dwbq_push = valid_st2 && miss_st2 && dirty_st2; + wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} + wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2; + wire dwbq_empty; + wire dwbq_full; + + assign dram_wb_req = !dwbq_empty; + VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( + .clk (clk), + .reset (reset), + + .push (dwbq_push), + .in_data ({dwbq_req_addr, dwbq_req_data}), + + .pop (dram_wb_queue_pop), + .out_data({dram_wb_req_addr, dram_wb_req_data}), + .empty (dwbq_empty), + .full (dwbq_full) + ); + + + assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full); endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index b0e139d9..8ed074f8 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -1,7 +1,5 @@ `include "VX_cache_config.v" -`include "VX_cache_config.v" - module VX_cache ( input wire clk, diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 47d513d0..0c35236c 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -3,24 +3,187 @@ module VX_tag_data_access ( input wire clk, input wire reset, + input wire stall, - input wire valid_st10, - input wire is_fill_st10, + // Initial Reading input wire[31:0] readaddr_st10, - input wire[`BANK_LINE_SIZE_RNG][31:0] filldata_st10, + // Write/Read Logic + input wire valid_req_st1e, + input wire writefill_st1e, input wire[31:0] writeaddr_st1e, input wire[31:0] writeword_st1e, + input wire[`BANK_LINE_SIZE_RNG][31:0] writedata_st1e, input wire[2:0] mem_write_st1e, input wire[2:0] mem_read_st1e, output wire[31:0] readword_st1e, output wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e, - output wire miss_st1e + output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e, + output wire miss_st1e, + output wire dirty_st1e ); reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[`STAGE_1_CYCLES-1:0]; -endmodule \ No newline at end of file + reg read_valid_st1c[`STAGE_1_CYCLES-1:0]; + reg read_dirty_st1c[`STAGE_1_CYCLES-1:0]; + reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [`STAGE_1_CYCLES-1:0]; + reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [`STAGE_1_CYCLES-1:0]; + + + wire qual_read_valid_st1; + wire qual_read_dirty_st1; + wire[`TAG_SELECT_SIZE_RNG] qual_read_tag_st1; + wire[`BANK_LINE_SIZE_RNG][31:0] qual_read_data_st1; + + wire use_read_valid_st1e; + wire use_read_dirty_st1e; + wire[`TAG_SELECT_SIZE_RNG] use_read_tag_st1e; + wire[`BANK_LINE_SIZE_RNG][31:0] use_read_data_st1e; + wire[`BANK_LINE_SIZE_RNG][3:0] use_write_enable; + wire[`BANK_LINE_SIZE_RNG][31:0] use_write_data; + + VX_tag_data_structure VX_tag_data_structure( + .clk (clk), + .reset (reset), + + .read_addr (readaddr_st10), + .read_valid (qual_read_valid_st1), + .read_dirty (qual_read_dirty_st1), + .read_tag (qual_read_tag_st1), + .read_data (qual_read_data_st1) + + .write_enable(use_write_enable), + .write_fill (writefill_st1e), + .write_addr (writeaddr_st1e), + .write_data (use_write_data) + ); + + VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_RNG*32) )) s0_1_c0 ( + .clk (clk), + .reset(reset), + .stall(stall), + .flush(0), + .in ({qual_read_valid_st1, qual_read_dirty_st1, qual_read_tag_st1, qual_read_data_st1}), + .out ({read_valid_st1c[0] , read_dirty_st1c[0] , read_tag_st1c[0] , read_data_st1c[0]}) + ); + + genvar curr_stage; + generate + for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin + VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_RNG*32) )) s0_1_cc ( + .clk (clk), + .reset(reset), + .stall(stall), + .flush(0), + .in ({read_valid_st1c[curr_stage-1] , read_dirty_st1c[curr_stage-1] , read_tag_st1c[curr_stage-1] , read_data_st1c[curr_stage-1]}) + .out ({read_valid_st1c[curr_stage] , read_dirty_st1c[curr_stage] , read_tag_st1c[curr_stage] , read_data_st1c[curr_stage] }) + ); + end + endgenerate + + + assign use_read_valid_st1e = read_valid_st1c[`STAGE_1_CYCLES-1]; + assign use_read_dirty_st1e = read_dirty_st1c[`STAGE_1_CYCLES-1]; + assign use_read_tag_st1e = read_tag_st1c [`STAGE_1_CYCLES-1]; + assign use_read_data_st1e = read_data_st1c [`STAGE_1_CYCLES-1]; + +/////////////////////// LOAD LOGIC /////////////////// + + wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG]; + wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG]; + + wire lw = (mem_read_st1e == `LW_MEM_READ); + wire lb = (mem_read_st1e == `LB_MEM_READ); + wire lh = (mem_read_st1e == `LH_MEM_READ); + wire lhu = (mem_read_st1e == `LHU_MEM_READ); + wire lbu = (mem_read_st1e == `LBU_MEM_READ); + + wire b0 = (byte_select == 0); + wire b1 = (byte_select == 1); + wire b2 = (byte_select == 2); + wire b3 = (byte_select == 3); + + wire[31:0] data_unQual = (b0 || lw) ? (use_read_data_st1e[block_offset]) : + b1 ? (use_read_data_st1e[block_offset] >> 8) : + b2 ? (use_read_data_st1e[block_offset] >> 16) : + (use_read_data_st1e[block_offset] >> 24); + + + wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF); + wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF); + wire[31:0] lbu_data = (data_unQual & 32'hFF); + wire[31:0] lhu_data = (data_unQual & 32'hFFFF); + wire[31:0] lw_data = (data_unQual); + + + wire[31:0] sw_data = writedata_st1e; + + wire[31:0] sb_data = b1 ? {{16{1'b0}}, writedata_st1e[7:0], { 8{1'b0}}} : + b2 ? {{ 8{1'b0}}, writedata_st1e[7:0], {16{1'b0}}} : + b3 ? {{ 0{1'b0}}, writedata_st1e[7:0], {24{1'b0}}} : + writedata_st1e; + + wire[31:0] sh_data = b2 ? {writedata_st1e[15:0], {16{1'b0}}} : writedata_st1e; + + + + wire[31:0] use_write_dat = sb ? sb_data : + sh ? sh_data : + sw_data; + + + wire[31:0] data_Qual = lb ? lb_data : + lh ? lh_data : + lhu ? lhu_data : + lbu ? lbu_data : + lw_data; + +/////////////////////// STORE LOGIC /////////////////// + + wire sw = (mem_write_st1e == `SW_MEM_WRITE); + wire sb = (mem_write_st1e == `SB_MEM_WRITE); + wire sh = (mem_write_st1e == `SH_MEM_WRITE); + + wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); + wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); + + wire should_write = (sw || sb || sh) && valid_req_st1e && !miss_st1e; + wire force_write = writefill_st1e && valid_req_st1e; + + wire[`BANK_LINE_SIZE_RNG][3:0] we; + wire[`BANK_LINE_SIZE_RNG][31:0] data_write; + genvar g; + generate + for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin : write_enables + wire normal_write = (block_offset == g) && should_write; + + assign we[g] = (force_write) ? 4'b1111 : + (normal_write && sw) ? 4'b1111 : + (normal_write && sb) ? sb_mask : + (normal_write && sh) ? sh_mask : + 4'b0000; + + assign data_write[g] = force_write ? writedata_st1e : use_write_dat ; + end + endgenerate + + assign use_write_enable = we; + assign use_write_data = data_write; + +/////////////////////// + + assign readword_st1e = data_Qual; + assign miss_st1e = valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e) + assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e; + assign readdata_st1e = use_read_data_st1e; + assign readtag_st1e = use_read_tag_st1e; + +endmodule + + + + diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index 4877a61f..4f2cf141 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -1,15 +1,51 @@ module VX_tag_data_structure ( - input wire clk, + input wire clk, + input wire reset, - input wire[31:0] readaddr, - output wire[`BANK_LINE_SIZE_RNG][31:0] readdata, + input wire[31:0] read_addr, + output wire read_valid, + output wire read_dirty, + output wire[`TAG_SELECT_SIZE_RNG] read_tag, + output wire[`BANK_LINE_SIZE_RNG][31:0] read_data, - input wire[`BANK_LINE_SIZE_RNG][3] writeenable, - input wire[31:0] writeaddr, - input wire[`BANK_LINE_SIZE_RNG][31:0] writedata + input wire[`BANK_LINE_SIZE_RNG][3:0] write_enable, + input wire write_fill, + input wire[31:0] write_addr, + input wire[`BANK_LINE_SIZE_RNG][31:0] write_data ); -endmodule + reg[`BANK_LINE_SIZE_RNG:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; + reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0]; + reg valid[`BANK_LINE_COUNT-1:0]; + reg dirty[`BANK_LINE_COUNT-1:0]; -// OFFSET_SIZE_RNG \ No newline at end of file + + assign read_valid <= valid[read_addr[`LINE_SELECT_ADDR_RNG]]; + assign read_dirty <= dirty[read_addr[`LINE_SELECT_ADDR_RNG]]; + assign read_tag <= tag [read_addr[`LINE_SELECT_ADDR_RNG]]; + assign read_data <= data [read_addr[`LINE_SELECT_ADDR_RNG]]; + + wire going_to_write = (|write_enable); + + always @(posedge clk) begin + if (going_to_write) begin + valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1; + tag [write_addr[`LINE_SELECT_ADDR_RNG]] <= write_addr[`TAG_SELECT_ADDR_RNG]; + if (write_fill) begin + dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; + end else begin + dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1; + end + end + + for (f = 0; f < `BANK_LINE_SIZE_WORDS; f = f + 1) begin + if (write_enable[f][0]) data[addr[`LINE_SELECT_ADDR_RNG]][f][0] <= data_write[f][7 :0 ]; + if (write_enable[f][1]) data[addr[`LINE_SELECT_ADDR_RNG]][f][1] <= data_write[f][15:8 ]; + if (write_enable[f][2]) data[addr[`LINE_SELECT_ADDR_RNG]][f][2] <= data_write[f][23:16]; + if (write_enable[f][3]) data[addr[`LINE_SELECT_ADDR_RNG]][f][3] <= data_write[f][31:24]; + end + + end + +endmodule \ No newline at end of file From 08986bf1dce632dd76adccd878e2182deb3b37e2 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 20:57:20 -0800 Subject: [PATCH 15/66] Fixed incorrect valid and'ing in execute --- rtl/VX_execute_unit.v | 2 +- rtl/VX_scheduler.v | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/VX_execute_unit.v b/rtl/VX_execute_unit.v index 697c20cb..f262e0b4 100644 --- a/rtl/VX_execute_unit.v +++ b/rtl/VX_execute_unit.v @@ -115,7 +115,7 @@ module VX_execute_unit ( // Actual Writeback assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd; assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb; - assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid && !internal_stall; + assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid & {`NT{!internal_stall}}; assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num; assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result; diff --git a/rtl/VX_scheduler.v b/rtl/VX_scheduler.v index a3116744..e7308f9c 100644 --- a/rtl/VX_scheduler.v +++ b/rtl/VX_scheduler.v @@ -50,9 +50,9 @@ module VX_scheduler ( wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual; assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid)) - || (memory_delay && is_mem) - || (gpr_stage_delay && (is_mem || is_exec)) - || (exec_delay && is_exec); + || (memory_delay && is_mem) + || (gpr_stage_delay && (is_mem || is_exec)) + || (exec_delay && is_exec); integer i; integer w; From 57a96e02b1ac3e3bee1b71a744598d3c8c770dc0 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 21:15:44 -0800 Subject: [PATCH 16/66] Fixed some other timing issues --- rtl/VX_fetch.v | 8 +++++--- rtl/VX_icache_stage.v | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index 391c8a1d..bcb08c83 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -22,12 +22,15 @@ module VX_fetch ( wire scheduled_warp; + wire pipe_stall; + + // Only reason this is there is because there is a hidden assumption that decode is exactly after fetch reg stall_might_be_branch; always @(posedge clk) begin if (reset) begin stall_might_be_branch <= 0; - end else if (stall_might_be_branch == 1'b1) begin + end else if ((stall_might_be_branch == 1'b1) && !icache_stage_delay && !schedule_delay) begin stall_might_be_branch <= 0; end else if (scheduled_warp == 1'b1) begin stall_might_be_branch <= 1'b1; @@ -35,7 +38,6 @@ module VX_fetch ( end // Locals - wire pipe_stall; assign pipe_stall = schedule_delay || icache_stage_delay || stall_might_be_branch; @@ -97,7 +99,7 @@ module VX_fetch ( ); assign fe_inst_meta_fi.warp_num = warp_num; - assign fe_inst_meta_fi.valid = thread_mask; + assign fe_inst_meta_fi.valid = thread_mask && {`NT{!stall_might_be_branch}}; assign fe_inst_meta_fi.inst_pc = warp_pc; diff --git a/rtl/VX_icache_stage.v b/rtl/VX_icache_stage.v index b642f722..daeaef5b 100644 --- a/rtl/VX_icache_stage.v +++ b/rtl/VX_icache_stage.v @@ -25,7 +25,7 @@ module VX_icache_stage ( assign fe_inst_meta_id.instruction = (!valid_inst || icache_response.delay) ? 32'b0 : icache_response.instruction; assign fe_inst_meta_id.inst_pc = fe_inst_meta_fi.inst_pc; assign fe_inst_meta_id.warp_num = fe_inst_meta_fi.warp_num; - assign fe_inst_meta_id.valid = fe_inst_meta_fi.valid; + assign fe_inst_meta_id.valid = fe_inst_meta_fi.valid & {`NT{!icache_stage_delay}}; endmodule \ No newline at end of file From 73cecd38667cba58c372284cb263e498992bd91d Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 22:14:56 -0800 Subject: [PATCH 17/66] Added Core Interface --- rtl/VX_back_end.v | 4 +- rtl/VX_dmem_controller.v | 170 +++++++++++------- rtl/VX_lsu.v | 46 ++--- rtl/Vortex.v | 43 +---- rtl/interfaces/VX_gpu_dcache_dram_req_inter.v | 25 +++ rtl/interfaces/VX_gpu_dcache_dram_res_inter.v | 19 ++ rtl/interfaces/VX_gpu_dcache_req_inter.v | 27 +++ rtl/interfaces/VX_gpu_dcache_res_inter.v | 24 +++ 8 files changed, 228 insertions(+), 130 deletions(-) create mode 100644 rtl/interfaces/VX_gpu_dcache_dram_req_inter.v create mode 100644 rtl/interfaces/VX_gpu_dcache_dram_res_inter.v create mode 100644 rtl/interfaces/VX_gpu_dcache_req_inter.v create mode 100644 rtl/interfaces/VX_gpu_dcache_res_inter.v diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index 67017fc1..9a6445a9 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -16,8 +16,8 @@ module VX_back_end ( VX_warp_ctl_inter VX_warp_ctl, - VX_dcache_response_inter VX_dcache_rsp, - VX_dcache_request_inter VX_dcache_req + VX_gpu_dcache_res_inter VX_dcache_rsp, + VX_gpu_dcache_req_inter VX_dcache_req ); diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 39d10b64..fdfc6b0d 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -10,49 +10,37 @@ module VX_dmem_controller ( // MEM-Processor VX_icache_request_inter VX_icache_req, VX_icache_response_inter VX_icache_rsp, - VX_dcache_request_inter VX_dcache_req, - VX_dcache_response_inter VX_dcache_rsp + VX_gpu_dcache_req_inter VX_dcache_req, + VX_gpu_dcache_res_inter VX_dcache_rsp ); - wire to_shm = VX_dcache_req.out_cache_driver_in_address[0][31:24] == 8'hFF; + wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; - wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{to_shm}}; - wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{~to_shm}}; - - wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|cache_driver_in_valid); + wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}}; - - wire[`NT_M1:0][31:0] cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address; - wire[2:0] cache_driver_in_mem_read = !(|cache_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.out_cache_driver_in_mem_read; - wire[2:0] cache_driver_in_mem_write = !(|cache_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.out_cache_driver_in_mem_write; - wire[`NT_M1:0][31:0] cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data; - - - wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.out_cache_driver_in_mem_read; - wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.out_cache_driver_in_mem_write; + wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; + wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read; + wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write; wire[`NT_M1:0][31:0] cache_driver_out_data; wire[`NT_M1:0][31:0] sm_driver_out_data; wire[`NT_M1:0] cache_driver_out_valid; // Not used for now wire sm_delay; - wire cache_delay; // I_Cache Signals wire[31:0] icache_instruction_out; wire icache_delay; - wire icache_driver_in_valid = VX_icache_req.out_cache_driver_in_valid; + wire icache_driver_in_valid = VX_icache_req.out_cache_driver_in_valid; wire[31:0] icache_driver_in_address = VX_icache_req.pc_address; wire[2:0] icache_driver_in_mem_read = !(|icache_driver_in_valid) ? `NO_MEM_READ : VX_icache_req.out_cache_driver_in_mem_read; wire[2:0] icache_driver_in_mem_write = !(|icache_driver_in_valid) ? `NO_MEM_WRITE : VX_icache_req.out_cache_driver_in_mem_write; - wire[31:0] icache_driver_in_data = VX_icache_req.out_cache_driver_in_data; - wire read_or_write_ic = (VX_icache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|icache_driver_in_valid); - - wire valid_read_cache = !cache_delay && cache_driver_in_valid[0]; + wire[31:0] icache_driver_in_data = VX_icache_req.out_cache_driver_in_data; + wire read_or_write_ic = (VX_icache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|icache_driver_in_valid); VX_shared_memory #( @@ -86,53 +74,99 @@ module VX_dmem_controller ( ); - VX_d_cache#( - .CACHE_SIZE (`DCACHE_SIZE), - .CACHE_WAYS (`DCACHE_WAYS), - .CACHE_BLOCK (`DCACHE_BLOCK), - .CACHE_BANKS (`DCACHE_BANKS), - .LOG_NUM_BANKS (`DCACHE_LOG_NUM_BANKS), - .NUM_REQ (`DCACHE_NUM_REQ), - .LOG_NUM_REQ (`DCACHE_LOG_NUM_REQ), - .NUM_IND (`DCACHE_NUM_IND), - .CACHE_WAY_INDEX (`DCACHE_WAY_INDEX), - .NUM_WORDS_PER_BLOCK (`DCACHE_NUM_WORDS_PER_BLOCK), - .OFFSET_SIZE_START (`DCACHE_OFFSET_ST), - .OFFSET_SIZE_END (`DCACHE_OFFSET_ED), - .TAG_SIZE_START (`DCACHE_TAG_SIZE_START), - .TAG_SIZE_END (`DCACHE_TAG_SIZE_END), - .IND_SIZE_START (`DCACHE_IND_SIZE_START), - .IND_SIZE_END (`DCACHE_IND_SIZE_END), - .ADDR_TAG_START (`DCACHE_ADDR_TAG_START), - .ADDR_TAG_END (`DCACHE_ADDR_TAG_END), - .ADDR_OFFSET_START (`DCACHE_ADDR_OFFSET_ST), - .ADDR_OFFSET_END (`DCACHE_ADDR_OFFSET_ED), - .ADDR_IND_START (`DCACHE_IND_ST), - .ADDR_IND_END (`DCACHE_IND_ED), - .MEM_ADDR_REQ_MASK (`DCACHE_MEM_REQ_ADDR_MASK) - ) - dcache - ( - .clk (clk), - .rst (reset), - .i_p_valid (cache_driver_in_valid), - .i_p_addr (cache_driver_in_address), - .i_p_writedata (cache_driver_in_data), - .i_p_read_or_write (read_or_write), - .i_p_mem_read (cache_driver_in_mem_read), - .i_p_mem_write (cache_driver_in_mem_write), - .o_p_readdata (cache_driver_out_data), - .o_p_delay (cache_delay), - .o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr), - .o_m_read_addr (VX_dram_req_rsp.o_m_read_addr), - .o_m_valid (VX_dram_req_rsp.o_m_valid), - .o_m_writedata (VX_dram_req_rsp.o_m_writedata), - .o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write), - .i_m_readdata (VX_dram_req_rsp.i_m_readdata), - .i_m_ready (VX_dram_req_rsp.i_m_ready) + VX_cache gpu_dcache( + .clk (clk), + .reset (reset), + + // Core req + .core_req_valid (cache_driver_in_valid), + .core_req_addr (VX_dcache_req.core_req_addr), + .core_req_writedata(VX_dcache_req.core_req_writedata), + .core_req_mem_read (VX_dcache_req.core_req_mem_read), + .core_req_mem_write(VX_dcache_req.core_req_mem_write), + .core_req_rd (VX_dcache_req.core_req_rd), + .core_req_wb (VX_dcache_req.core_req_wb), + .core_req_warp_num (VX_dcache_req.core_req_warp_num), + + // Delay Core Req + .delay_req (VX_dcache_rsp.delay_req), + + // Core Cache Can't WB + .core_no_wb_slot (VX_dcache_req.core_no_wb_slot), + + // Cache CWB + .core_wb_valid (VX_dcache_rsp.core_wb_valid), + .core_wb_req_rd (VX_dcache_rsp.core_wb_req_rd), + .core_wb_req_wb (VX_dcache_rsp.core_wb_req_wb), + .core_wb_warp_num (VX_dcache_rsp.core_wb_warp_num), + .core_wb_readdata (VX_dcache_rsp.core_wb_readdata), + + // DRAM response + .dram_fill_rsp (dram_fill_rsp), + .dram_fill_rsp_addr(dram_fill_rsp_addr), + .dram_fill_rsp_data(dram_fill_rsp_data), + + // DRAM accept response + .dram_fill_accept (dram_fill_accept), + + // DRAM Req + .dram_req (dram_req), + .dram_req_write (dram_req_write), + .dram_req_read (dram_req_read), + .dram_req_addr (dram_req_addr), + .dram_req_size (dram_req_size), + .dram_req_data (dram_req_data), ); + + // VX_d_cache#( + // .CACHE_SIZE (`DCACHE_SIZE), + // .CACHE_WAYS (`DCACHE_WAYS), + // .CACHE_BLOCK (`DCACHE_BLOCK), + // .CACHE_BANKS (`DCACHE_BANKS), + // .LOG_NUM_BANKS (`DCACHE_LOG_NUM_BANKS), + // .NUM_REQ (`DCACHE_NUM_REQ), + // .LOG_NUM_REQ (`DCACHE_LOG_NUM_REQ), + // .NUM_IND (`DCACHE_NUM_IND), + // .CACHE_WAY_INDEX (`DCACHE_WAY_INDEX), + // .NUM_WORDS_PER_BLOCK (`DCACHE_NUM_WORDS_PER_BLOCK), + // .OFFSET_SIZE_START (`DCACHE_OFFSET_ST), + // .OFFSET_SIZE_END (`DCACHE_OFFSET_ED), + // .TAG_SIZE_START (`DCACHE_TAG_SIZE_START), + // .TAG_SIZE_END (`DCACHE_TAG_SIZE_END), + // .IND_SIZE_START (`DCACHE_IND_SIZE_START), + // .IND_SIZE_END (`DCACHE_IND_SIZE_END), + // .ADDR_TAG_START (`DCACHE_ADDR_TAG_START), + // .ADDR_TAG_END (`DCACHE_ADDR_TAG_END), + // .ADDR_OFFSET_START (`DCACHE_ADDR_OFFSET_ST), + // .ADDR_OFFSET_END (`DCACHE_ADDR_OFFSET_ED), + // .ADDR_IND_START (`DCACHE_IND_ST), + // .ADDR_IND_END (`DCACHE_IND_ED), + // .MEM_ADDR_REQ_MASK (`DCACHE_MEM_REQ_ADDR_MASK) + // ) + // dcache + // ( + // .clk (clk), + // .rst (reset), + // .i_p_valid (cache_driver_in_valid), + // .i_p_addr (cache_driver_in_address), + // .i_p_writedata (cache_driver_in_data), + // .i_p_read_or_write (read_or_write), + // .i_p_mem_read (cache_driver_in_mem_read), + // .i_p_mem_write (cache_driver_in_mem_write), + // .o_p_readdata (cache_driver_out_data), + // .o_p_delay (cache_delay), + // .o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr), + // .o_m_read_addr (VX_dram_req_rsp.o_m_read_addr), + // .o_m_valid (VX_dram_req_rsp.o_m_valid), + // .o_m_writedata (VX_dram_req_rsp.o_m_writedata), + // .o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write), + // .i_m_readdata (VX_dram_req_rsp.i_m_readdata), + // .i_m_ready (VX_dram_req_rsp.i_m_ready) + // ); + + VX_d_cache#( .CACHE_SIZE (`ICACHE_SIZE), .CACHE_WAYS (`ICACHE_WAYS), @@ -178,8 +212,8 @@ VX_d_cache#( .i_m_ready (VX_dram_req_rsp_icache.i_m_ready) ); - assign VX_dcache_rsp.in_cache_driver_out_data = to_shm ? sm_driver_out_data : cache_driver_out_data; - assign VX_dcache_rsp.delay = sm_delay || cache_delay; + // assign VX_dcache_rsp.in_cache_driver_out_data = (to_shm && 0) ? sm_driver_out_data : cache_driver_out_data; + // assign VX_dcache_rsp.delay = (sm_delay && 0) || cache_delay; assign VX_icache_rsp.instruction = icache_instruction_out; assign VX_icache_rsp.delay = icache_delay; diff --git a/rtl/VX_lsu.v b/rtl/VX_lsu.v index 78331b83..86694851 100644 --- a/rtl/VX_lsu.v +++ b/rtl/VX_lsu.v @@ -11,14 +11,12 @@ module VX_lsu ( // Write back to GPR VX_inst_mem_wb_inter VX_mem_wb, - VX_dcache_response_inter VX_dcache_rsp, - VX_dcache_request_inter VX_dcache_req, + VX_gpu_dcache_res_inter VX_dcache_rsp, + VX_gpu_dcache_req_inter VX_dcache_req, output wire out_delay ); - // VX_inst_mem_wb_inter VX_mem_wb_temp(); - assign out_delay = VX_dcache_rsp.delay || no_slot_mem; // Generate Addresses @@ -55,27 +53,33 @@ module VX_lsu ( ); - genvar index; - generate - for (index = 0; index <= `NT_M1; index = index + 1) begin : dcache_reqs - assign VX_dcache_req.out_cache_driver_in_address[index] = use_address[index]; - assign VX_dcache_req.out_cache_driver_in_data[index] = use_store_data[index]; - assign VX_dcache_req.out_cache_driver_in_valid[index] = (use_valid[index]); + // Core Request + assign VX_dcache_req.core_req_valid = use_valid; + assign VX_dcache_req.core_req_addr = use_address; + assign VX_dcache_req.core_req_writedata = use_store_data; + assign VX_dcache_req.core_req_mem_read = use_mem_read; + assign VX_dcache_req.core_req_mem_write = use_mem_write; + assign VX_dcache_req.core_req_rd = use_rd; + assign VX_dcache_req.core_req_wb = use_wb; + assign VX_dcache_req.core_req_warp_num = use_warp_num; - assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index]; - end - endgenerate - - assign VX_dcache_req.out_cache_driver_in_mem_read = use_mem_read; - assign VX_dcache_req.out_cache_driver_in_mem_write = use_mem_write; + // Cache can't accept request + assign out_delay = VX_dcache_rsp.delay_req; - assign VX_mem_wb.rd = use_rd; - assign VX_mem_wb.wb = use_wb & {!VX_dcache_rsp.delay, !VX_dcache_rsp.delay}; - assign VX_mem_wb.wb_valid = use_valid; - assign VX_mem_wb.wb_warp_num = use_warp_num; - assign VX_mem_wb.mem_wb_pc = use_pc; + // Core Response + assign VX_mem_wb.rd = VX_dcache_rsp.core_wb_req_rd; + assign VX_mem_wb.wb = VX_dcache_rsp.core_wb_req_wb; + assign VX_mem_wb.wb_valid = VX_dcache_rsp.core_wb_valid; + assign VX_mem_wb.wb_warp_num = VX_dcache_rsp.core_wb_warp_num; + assign VX_mem_wb.loaded_data = VX_dcache_rsp.core_wb_readdata; + assign VX_mem_wb.mem_wb_pc = 32'hdeadbeff; + + // Core can't accept response + assign VX_dcache_req.core_no_wb_slot = no_slot_mem; + + // integer curr_t; // always @(negedge clk) begin diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 4939d473..26c2642c 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -72,11 +72,11 @@ wire schedule_delay; // Dcache Interface -VX_dcache_response_inter VX_dcache_rsp(); -VX_dcache_request_inter VX_dcache_req(); +VX_gpu_dcache_res_inter VX_dcache_rsp(); +VX_gpu_dcache_req_inter VX_dcache_req(); -wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.out_cache_driver_in_valid) && (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.out_cache_driver_in_address[0] == 32'h00010000); -wire[31:0] temp_io_data = VX_dcache_req.out_cache_driver_in_data[0]; +wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000); +wire[31:0] temp_io_data = VX_dcache_req.core_req_valid[0]; assign io_valid = temp_io_valid; assign io_data = temp_io_data; @@ -94,31 +94,6 @@ VX_dram_req_rsp_inter #( //assign icache_response_fe.instruction = icache_response_instruction; assign icache_request_pc_address = icache_request_fe.pc_address; - // Need to fix this so that it is only 1 set of outputs - // o_m Values - - // L2 Cache - /* - assign VX_L2cache_req.out_cache_driver_in_valid = VX_dram_req_rsp.o_m_valid || VX_dram_req_rsp_icache.o_m_valid; // Ask about this (width) - // Ask about the adress - assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? icache_request_fe.pc_address: VX_dcache_req.out_cache_driver_in_address; - //assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_read_addr: VX_dram_req_rsp.o_m_read_addr; - //assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_evict_addr : VX_dram_req_rsp.o_m_evict_addr; - assign VX_L2cache_req.out_cache_driver_in_mem_read = (VX_dram_req_rsp_icache.o_m_valid) ? (VX_dram_req_rsp_icache.o_m_read_or_write ? icache_request_fe.out_cache_driver_in_mem_write : icache_request_fe.out_cache_driver_in_mem_read) - : (VX_dram_req_rsp.o_m_read_or_write ? VX_dcache_req.out_cache_driver_in_mem_write : VX_dcache_req.out_cache_driver_in_mem_read); - //assign VX_dram_req_rsp.i_m_ready = i_m_ready && !VX_dram_req_rsp_icache.o_m_valid && VX_dram_req_rsp.o_m_valid; - //assign VX_dram_req_rsp_icache.i_m_ready = i_m_ready && VX_dram_req_rsp_icache.o_m_valid; - genvar cur_bank; - genvar cur_word; - for (cur_bank = 0; cur_bank < CACHE_BANKS; cur_bank = cur_bank + 1) begin - for (cur_word = 0; cur_word < NUM_WORDS_PER_BLOCK; cur_word = cur_word + 1) begin - assign VX_L2cache_req.out_cache_driver_in_data[cur_bank][cur_word] = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_writedata[cur_bank][cur_word] - : VX_dram_req_rsp.o_m_writedata[cur_bank][cur_word]; - assign VX_dram_req_rsp.i_m_readdata[cur_bank][cur_word] = VX_dram_req_rsp_L2.i_m_readdata[cur_bank][cur_word]; // fill in correct response data - assign VX_dram_req_rsp_icache.i_m_readdata[cur_bank][cur_word] = VX_dram_req_rsp_L2.i_m_readdata[cur_bank][cur_word]; // fill in correct response data - end - end - */ assign o_m_valid_i = VX_dram_req_rsp_icache.o_m_valid; @@ -133,16 +108,6 @@ VX_dram_req_rsp_inter #( assign VX_dram_req_rsp_icache.i_m_ready = i_m_ready_i; genvar curr_bank; genvar curr_word; - /* - for (curr_bank = 0; curr_bank < CACHE_BANKS; curr_bank = curr_bank + 1) begin - for (curr_word = 0; curr_word < NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin - assign o_m_writedata_i[curr_bank][curr_word] = VX_dram_req_rsp_icache.o_m_writedata[curr_bank][curr_word]; - assign o_m_writedata_d[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word]; - assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata_d[curr_bank][curr_word]; // fixed - assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed - end - end - */ generate for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin : dcache_setup diff --git a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v new file mode 100644 index 00000000..58170aa3 --- /dev/null +++ b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v @@ -0,0 +1,25 @@ + + +`include "../VX_cache/VX_cache_config.v" + +`ifndef VX_GPU_DRAM_DCACHE_REQ + +`define VX_GPU_DRAM_DCACHE_REQ + +interface VX_gpu_dcache_dram_req_inter (); + + // DRAM Request + wire dram_req; + wire dram_req_write; + wire dram_req_read; + wire [31:0] dram_req_addr; + wire [31:0] dram_req_size; + wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data; + + // DRAM Cache can't accept response + wire dram_fill_accept; + +endinterface + + +`endif \ No newline at end of file diff --git a/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v new file mode 100644 index 00000000..24ba4dc1 --- /dev/null +++ b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v @@ -0,0 +1,19 @@ + + + +`include "../VX_cache/VX_cache_config.v" + +`ifndef VX_GPU_DRAM_DCACHE_RES + +`define VX_GPU_DRAM_DCACHE_RES + +interface VX_gpu_dcache_dram_res_inter (); + // DRAM Rsponse + wire dram_fill_rsp; + wire [31:0] dram_fill_rsp_addr; + wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data; + +endinterface + + +`endif \ No newline at end of file diff --git a/rtl/interfaces/VX_gpu_dcache_req_inter.v b/rtl/interfaces/VX_gpu_dcache_req_inter.v new file mode 100644 index 00000000..50ac04e7 --- /dev/null +++ b/rtl/interfaces/VX_gpu_dcache_req_inter.v @@ -0,0 +1,27 @@ + + +`include "../VX_cache/VX_cache_config.v" + +`ifndef VX_GPU_DCACHE_REQ + +`define VX_GPU_DCACHE_REQ + +interface VX_gpu_dcache_req_inter (); + + // Core Request + wire [`NUMBER_REQUESTS-1:0] core_req_valid; + wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr; + wire [`NUMBER_REQUESTS-1:0][31:0] core_req_writedata; + wire [2:0] core_req_mem_read; + wire [2:0] core_req_mem_write; + wire [4:0] core_req_rd; + wire [1:0] core_req_wb; + wire [`NW_M1:0] core_req_warp_num; + + // Can't WB + wire core_no_wb_slot; + +endinterface + + +`endif \ No newline at end of file diff --git a/rtl/interfaces/VX_gpu_dcache_res_inter.v b/rtl/interfaces/VX_gpu_dcache_res_inter.v new file mode 100644 index 00000000..2b5cbbbd --- /dev/null +++ b/rtl/interfaces/VX_gpu_dcache_res_inter.v @@ -0,0 +1,24 @@ + + +`include "../VX_cache/VX_cache_config.v" + +`ifndef VX_GPU_DCACHE_RES + +`define VX_GPU_DCACHE_RES + +interface VX_gpu_dcache_res_inter (); + + // Cache WB + wire [`NUMBER_REQUESTS-1:0] core_wb_valid; + wire [4:0] core_wb_req_rd; + wire [1:0] core_wb_req_wb; + wire [`NW_M1:0] core_wb_warp_num; + wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata; + + // Cache Full + wire delay_req; + +endinterface + + +`endif \ No newline at end of file From 8f001ac6f27bca42f3752ab59ae0bc5daa9e7316 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 3 Mar 2020 22:48:49 -0800 Subject: [PATCH 18/66] Added All Interfaces --- rtl/VX_dmem_controller.v | 24 +++++++------ rtl/Vortex.v | 76 ++++++++++++++++++++++------------------ 2 files changed, 55 insertions(+), 45 deletions(-) diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index fdfc6b0d..c0e57c5c 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -5,7 +5,9 @@ module VX_dmem_controller ( input wire clk, input wire reset, // MEM-RAM - VX_dram_req_rsp_inter VX_dram_req_rsp, + VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req, + VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res, + VX_dram_req_rsp_inter VX_dram_req_rsp_icache, // MEM-Processor VX_icache_request_inter VX_icache_req, @@ -102,20 +104,20 @@ module VX_dmem_controller ( .core_wb_readdata (VX_dcache_rsp.core_wb_readdata), // DRAM response - .dram_fill_rsp (dram_fill_rsp), - .dram_fill_rsp_addr(dram_fill_rsp_addr), - .dram_fill_rsp_data(dram_fill_rsp_data), + .dram_fill_rsp (VX_gpu_dcache_dram_res.dram_fill_rsp), + .dram_fill_rsp_addr(VX_gpu_dcache_dram_res.dram_fill_rsp_addr), + .dram_fill_rsp_data(VX_gpu_dcache_dram_res.dram_fill_rsp_data), // DRAM accept response - .dram_fill_accept (dram_fill_accept), + .dram_fill_accept (VX_gpu_dcache_dram_req.dram_fill_accept), // DRAM Req - .dram_req (dram_req), - .dram_req_write (dram_req_write), - .dram_req_read (dram_req_read), - .dram_req_addr (dram_req_addr), - .dram_req_size (dram_req_size), - .dram_req_data (dram_req_data), + .dram_req (VX_gpu_dcache_dram_req.dram_req), + .dram_req_write (VX_gpu_dcache_dram_req.dram_req_write), + .dram_req_read (VX_gpu_dcache_dram_req.dram_req_read), + .dram_req_addr (VX_gpu_dcache_dram_req.dram_req_addr), + .dram_req_size (VX_gpu_dcache_dram_req.dram_req_size), + .dram_req_data (VX_gpu_dcache_dram_req.dram_req_data), ); diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 26c2642c..d400ec81 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -19,16 +19,21 @@ module Vortex output wire io_valid, output wire[31:0] io_data, - // Req D Mem - output reg [31:0] o_m_read_addr_d, - output reg [31:0] o_m_evict_addr_d, - output reg o_m_valid_d, - output reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0], - output reg o_m_read_or_write_d, + // DRAM Dcache Req + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [31:0] dram_req_data[`BANK_LINE_SIZE_RNG], + output wire [31:0] dram_expected_lat, + + // DRAM Dcache Res + output wire dram_fill_accept, + input wire dram_fill_rsp, + input wire [31:0] dram_fill_rsp_addr, + input wire [31:0] dram_fill_rsp_data[`BANK_LINE_SIZE_RNG], - // Rsp D Mem - input wire [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0], - input wire i_m_ready_d, // Req I Mem output reg [31:0] o_m_read_addr_i, @@ -48,12 +53,6 @@ reg[31:0] icache_banks = `ICACHE_BANKS; reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK; -reg[31:0] dcache_banks = `DCACHE_BANKS; -reg[31:0] dcache_num_words_per_block = `DCACHE_NUM_WORDS_PER_BLOCK; - -reg[31:0] number_threads = `NT; -reg[31:0] number_warps = `NW; - always @(posedge clk) begin icache_banks <= icache_banks; icache_num_words_per_block <= icache_num_words_per_block; @@ -75,15 +74,38 @@ wire schedule_delay; VX_gpu_dcache_res_inter VX_dcache_rsp(); VX_gpu_dcache_req_inter VX_dcache_req(); +VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req(); +VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res(); + + +assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp; +assign VX_gpu_dcache_dram_res.dram_fill_rsp_addr = dram_fill_rsp_addr; + +assign dram_req = VX_gpu_dcache_dram_req.dram_req; +assign dram_req_write = VX_gpu_dcache_dram_req.dram_req_write; +assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read; +assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr; +assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size; +assign dram_expected_lat = `SIMULATED_DRAM_LATENCY_CYCLES; +assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept; + +genvar wordy; +generate + for (wordy = 0; wordy < `BANK_LINE_SIZE_WORDS; wordy=wordy+1) begin + assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy]; + assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy]; + end +endgenerate + + + wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000); wire[31:0] temp_io_data = VX_dcache_req.core_req_valid[0]; assign io_valid = temp_io_valid; assign io_data = temp_io_data; -VX_dram_req_rsp_inter #( - .NUMBER_BANKS(`DCACHE_BANKS), - .NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)) VX_dram_req_rsp(); + VX_icache_response_inter icache_response_fe(); VX_icache_request_inter icache_request_fe(); @@ -97,28 +119,13 @@ VX_dram_req_rsp_inter #( assign o_m_valid_i = VX_dram_req_rsp_icache.o_m_valid; - assign o_m_valid_d = VX_dram_req_rsp.o_m_valid; assign o_m_read_addr_i = VX_dram_req_rsp_icache.o_m_read_addr; - assign o_m_read_addr_d = VX_dram_req_rsp.o_m_read_addr; assign o_m_evict_addr_i = VX_dram_req_rsp_icache.o_m_evict_addr; - assign o_m_evict_addr_d = VX_dram_req_rsp.o_m_evict_addr; assign o_m_read_or_write_i = VX_dram_req_rsp_icache.o_m_read_or_write; - assign o_m_read_or_write_d = VX_dram_req_rsp.o_m_read_or_write; - assign VX_dram_req_rsp.i_m_ready = i_m_ready_d; assign VX_dram_req_rsp_icache.i_m_ready = i_m_ready_i; genvar curr_bank; genvar curr_word; -generate -for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin : dcache_setup - for (curr_word = 0; curr_word < `DCACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : dcache_banks_setup - - assign o_m_writedata_d[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word]; - assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata_d[curr_bank][curr_word]; // fixed - - end -end - for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin : icache_setup for (curr_word = 0; curr_word < `ICACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : icache_banks_setup @@ -192,7 +199,8 @@ VX_back_end vx_back_end( VX_dmem_controller VX_dmem_controller( .clk (clk), .reset (reset), - .VX_dram_req_rsp (VX_dram_req_rsp), + .VX_gpu_dcache_dram_req (VX_gpu_dcache_dram_req), + .VX_gpu_dcache_dram_res (VX_gpu_dcache_dram_res), .VX_dram_req_rsp_icache (VX_dram_req_rsp_icache), .VX_icache_req (icache_request_fe), .VX_icache_rsp (icache_response_fe), From b0b9b8238ea83a74f5db2e3e9dac9300e74a0887 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Wed, 4 Mar 2020 04:05:54 -0800 Subject: [PATCH 19/66] Passing some cases --- rtl/Makefile | 2 +- rtl/VX_cache/VX_bank.v | 33 +++++--- rtl/VX_cache/VX_cache.v | 16 ++-- rtl/VX_cache/VX_cache_config.v | 96 ++++++++++++----------- rtl/VX_cache/VX_cache_core_req_bank_sel.v | 6 +- rtl/VX_cache/VX_cache_dfq_queue.v | 4 +- rtl/VX_cache/VX_cache_dram_req_arb.v | 16 ++-- rtl/VX_cache/VX_cache_miss_resrv.v | 4 +- rtl/VX_cache/VX_cache_req_queue.v | 12 +-- rtl/VX_cache/VX_cache_wb_sel_merge.v | 29 +++---- rtl/VX_cache/VX_tag_data_access.v | 24 +++--- rtl/VX_cache/VX_tag_data_structure.v | 19 ++--- rtl/VX_define.v | 7 ++ rtl/VX_define_synth.v | 9 ++- rtl/VX_dmem_controller.v | 6 +- rtl/VX_fetch.v | 6 +- rtl/VX_front_end.v | 6 +- rtl/VX_generic_queue.v | 14 ++-- rtl/VX_generic_register.v | 19 ++--- rtl/Vortex.v | 11 +-- rtl/pipe_regs/VX_f_d_reg.v | 4 +- rtl/pipe_regs/VX_i_d_reg.v | 27 +++++++ 22 files changed, 217 insertions(+), 153 deletions(-) create mode 100644 rtl/pipe_regs/VX_i_d_reg.v diff --git a/rtl/Makefile b/rtl/Makefile index 980a3211..c9b2a3fb 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -9,7 +9,7 @@ EXE=--exe ./simulate/test_bench.cpp COMP=--compiler gcc -WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT +WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN # WNO= # LIGHTW= diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index e29c26f9..3167daf3 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -18,6 +18,7 @@ module VX_bank ( // Output Core WB input wire bank_wb_pop, + output wire bank_wb_valid, output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid, output wire [4:0] bank_wb_rd, output wire [1:0] bank_wb_wb, @@ -78,7 +79,7 @@ module VX_bank ( assign reqq_push = !delay_req && (|bank_valids); - VX_cache_req_queue mrvq_queue( + VX_cache_req_queue req_queue( .clk (clk), .reset (reset), // Enqueue @@ -142,11 +143,11 @@ module VX_bank ( .miss_add_warp_num (miss_add_warp_num), .miss_add_mem_read (miss_add_mem_read), .miss_add_mem_write (miss_add_mem_write), - .miss_resrv_full (mrvq_full) + .miss_resrv_full (mrvq_full), // Broadcast - .is_fill_st1 (is_fill_st1), - .fill_addr_st1 (addr_st1[0]), + .is_fill_st1 (is_fill_st2), + .fill_addr_st1 (addr_st2), // Dequeue .miss_resrv_pop (mrvq_pop), @@ -201,7 +202,7 @@ module VX_bank ( reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} : 0; - VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_c0 ( + VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_c0 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), @@ -213,7 +214,7 @@ module VX_bank ( genvar curr_stage; generate for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin - VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_RNG*32) + 1)) s0_1_cc ( + VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), @@ -245,7 +246,7 @@ module VX_bank ( VX_tag_data_access VX_tag_data_access( .clk (clk), .reset (reset), - .stall (stall), + .stall (stall_bank_pipe), // Initial Read .readaddr_st10 (addr_st1[0]), @@ -279,14 +280,15 @@ module VX_bank ( wire dirty_st2; wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2; wire[`TAG_SELECT_SIZE_RNG] readtag_st2; + wire is_fill_st2; - VX_generic_register #(.N( 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 ( + VX_generic_register #(.N( 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), - .out ({valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) + .in ({is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), + .out ({is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) ); @@ -307,6 +309,7 @@ module VX_bank ( wire cwbq_full; wire cwbq_empty; + assign bank_wb_valid = !cwbq_empty; VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( .clk (clk), .reset (reset), @@ -322,13 +325,17 @@ module VX_bank ( // Enqueue to DWB Queue wire dwbq_push = valid_st2 && miss_st2 && dirty_st2; - wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} + wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]}; wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2; wire dwbq_empty; wire dwbq_full; + // Enqueu in dram_fill_req + assign dram_fill_req = valid_st2 && miss_st2; + assign dram_fill_req_addr = addr_st2; + assign dram_wb_req = !dwbq_empty; - VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_RNG * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( + VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( .clk (clk), .reset (reset), @@ -342,7 +349,7 @@ module VX_bank ( ); - assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full); + assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full); endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 8ed074f8..661eb12b 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -45,6 +45,7 @@ module VX_cache ( wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids; wire [`NUMBER_BANKS-1:0] per_bank_wb_pop; + wire [`NUMBER_BANKS-1:0] per_bank_wb_valid; wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid; wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; @@ -60,14 +61,14 @@ module VX_cache ( wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; - wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; + wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; wire[`NUMBER_BANKS-1:0] per_bank_reqq_full; assign delay_req = (|per_bank_reqq_full); - assign dram_fill_accept = (`NUMBER_BANKS == 1) ? dram_fill_accept[0] : dram_fill_accept[dram_fill_addr[`BANK_SELECT_ADDR_RNG]]; + assign dram_fill_accept = (`NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; VX_cache_dram_req_arb VX_cache_dram_req_arb( .clk (clk), @@ -88,7 +89,7 @@ module VX_cache ( ); - VX_cache_core_req_bank_sel VX_cache_core_req_bank_sel( + VX_cache_core_req_bank_sel VX_cache_core_req_bank_sell( .core_req_valid (core_req_valid), .core_req_addr (core_req_addr), .per_bank_valids(per_bank_valids) @@ -96,6 +97,7 @@ module VX_cache ( VX_cache_wb_sel_merge VX_cache_core_req_bank_sel( + .per_bank_wb_valid (per_bank_wb_valid), .per_bank_wb_tid (per_bank_wb_tid), .per_bank_wb_rd (per_bank_wb_rd), .per_bank_wb_wb (per_bank_wb_wb), @@ -103,6 +105,7 @@ module VX_cache ( .per_bank_wb_data (per_bank_wb_data), .per_bank_wb_pop (per_bank_wb_pop), + .core_no_wb_slot (core_no_wb_slot), .core_wb_valid (core_wb_valid), .core_wb_req_rd (core_wb_req_rd), .core_wb_req_wb (core_wb_req_wb), @@ -110,8 +113,8 @@ module VX_cache ( .core_wb_readdata (core_wb_readdata) ); + genvar curr_bank; generate - integer curr_bank; for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin wire [`NUMBER_REQUESTS-1:0] curr_bank_valids; wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; @@ -123,6 +126,7 @@ module VX_cache ( wire [2:0] curr_bank_mem_write; wire curr_bank_wb_pop; + wire curr_bank_wb_valid; wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid; wire [4:0] curr_bank_wb_rd; wire [1:0] curr_bank_wb_wb; @@ -158,6 +162,7 @@ module VX_cache ( // Core WB assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank]; + assign per_bank_wb_valid [curr_bank] = curr_bank_wb_valid; assign per_bank_wb_tid [curr_bank] = curr_bank_wb_tid; assign per_bank_wb_rd [curr_bank] = curr_bank_wb_rd; assign per_bank_wb_wb [curr_bank] = curr_bank_wb_wb; @@ -170,7 +175,7 @@ module VX_cache ( assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; // Dram fill response - assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); + assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept; @@ -199,6 +204,7 @@ module VX_cache ( // Output core wb .bank_wb_pop (curr_bank_wb_pop), + .bank_wb_valid (curr_bank_wb_valid), .bank_wb_tid (curr_bank_wb_tid), .bank_wb_rd (curr_bank_wb_rd), .bank_wb_wb (curr_bank_wb_wb), diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index fbec7e5c..c1844dcc 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -1,8 +1,10 @@ -`include "../VX_define.h" +`include "../VX_define.v" +`ifndef VX_CACHE_CONFIG +`define VX_CACHE_CONFIG // ========================================= Configurable Knobs ========================================= // General Cache Knobs @@ -42,45 +44,46 @@ // ========================================= Configurable Knobs ========================================= // data tid rd wb warp_num read write -`define MRVQ_METADATA_SIZE (32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) +`define MRVQ_METADATA_SIZE (32 + $clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) -`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + `vx_clog2(`NUMBER_REQUESTS)) +`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + $clog2(`NUMBER_REQUESTS)) -`define vx_clog2_h(value, x) (value == (1 << x)) ? (x) +`define vx_clog2(value) $clog2(value) +// `define vx_clog2_h(value, x) (value == (1 << x)) ? (x) -`define vx_clog2(value) (value == 0 ) ? 0 : \ - (value == 1 ) ? 1 : \ - `vx_clog2_h(value, 2 ) : \ - `vx_clog2_h(value, 3 ) : \ - `vx_clog2_h(value, 4 ) : \ - `vx_clog2_h(value, 5 ) : \ - `vx_clog2_h(value, 6 ) : \ - `vx_clog2_h(value, 7 ) : \ - `vx_clog2_h(value, 8 ) : \ - `vx_clog2_h(value, 9 ) : \ - `vx_clog2_h(value, 10) : \ - `vx_clog2_h(value, 11) : \ - `vx_clog2_h(value, 12) : \ - `vx_clog2_h(value, 13) : \ - `vx_clog2_h(value, 14) : \ - `vx_clog2_h(value, 15) : \ - `vx_clog2_h(value, 16) : \ - `vx_clog2_h(value, 17) : \ - `vx_clog2_h(value, 18) : \ - `vx_clog2_h(value, 19) : \ - `vx_clog2_h(value, 20) : \ - `vx_clog2_h(value, 21) : \ - `vx_clog2_h(value, 22) : \ - `vx_clog2_h(value, 23) : \ - `vx_clog2_h(value, 24) : \ - `vx_clog2_h(value, 25) : \ - `vx_clog2_h(value, 26) : \ - `vx_clog2_h(value, 27) : \ - `vx_clog2_h(value, 28) : \ - `vx_clog2_h(value, 29) : \ - `vx_clog2_h(value, 30) : \ - `vx_clog2_h(value, 31) : \ - 0 +// `define vx_clog2(value) (value == 0 ) ? 0 : \ +// (value == 1 ) ? 1 : \ +// `vx_clog2_h(value, 2 ) : \ +// `vx_clog2_h(value, 3 ) : \ +// `vx_clog2_h(value, 4 ) : \ +// `vx_clog2_h(value, 5 ) : \ +// `vx_clog2_h(value, 6 ) : \ +// `vx_clog2_h(value, 7 ) : \ +// `vx_clog2_h(value, 8 ) : \ +// `vx_clog2_h(value, 9 ) : \ +// `vx_clog2_h(value, 10) : \ +// `vx_clog2_h(value, 11) : \ +// `vx_clog2_h(value, 12) : \ +// `vx_clog2_h(value, 13) : \ +// `vx_clog2_h(value, 14) : \ +// `vx_clog2_h(value, 15) : \ +// `vx_clog2_h(value, 16) : \ +// `vx_clog2_h(value, 17) : \ +// `vx_clog2_h(value, 18) : \ +// `vx_clog2_h(value, 19) : \ +// `vx_clog2_h(value, 20) : \ +// `vx_clog2_h(value, 21) : \ +// `vx_clog2_h(value, 22) : \ +// `vx_clog2_h(value, 23) : \ +// `vx_clog2_h(value, 24) : \ +// `vx_clog2_h(value, 25) : \ +// `vx_clog2_h(value, 26) : \ +// `vx_clog2_h(value, 27) : \ +// `vx_clog2_h(value, 28) : \ +// `vx_clog2_h(value, 29) : \ +// `vx_clog2_h(value, 30) : \ +// `vx_clog2_h(value, 31) : \ +// 0 `define BANK_SIZE_BYTES `CACHE_SIZE_BYTES/`NUMBER_BANKS @@ -91,40 +94,43 @@ `define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0 // Offset is fixed +`define OFFSET_ADDR_NUM_BITS 2 `define OFFSET_SIZE_END 1 `define OFFSET_ADDR_START 0 `define OFFSET_ADDR_END 1 `define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START `define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 -`define WORD_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_SIZE_WORDS) +`define WORD_SELECT_NUM_BITS $clog2(`BANK_LINE_SIZE_WORDS) `define WORD_SELECT_SIZE_END `WORD_SELECT_NUM_BITS `define WORD_SELECT_ADDR_START 1+`OFFSET_ADDR_END `define WORD_SELECT_ADDR_END `WORD_SELECT_SIZE_END+`OFFSET_ADDR_END `define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START -`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:WORD_SELECT_SIZE_END +`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:`WORD_SELECT_SIZE_END -`define BANK_SELECT_NUM_BITS `vx_clog2(`NUMBER_BANKS) +`define BANK_SELECT_NUM_BITS $clog2(`NUMBER_BANKS) `define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS `define BANK_SELECT_ADDR_START 1+`WORD_SELECT_ADDR_END `define BANK_SELECT_ADDR_END `BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START `define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START `define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0 -`define LINE_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_COUNT) +`define LINE_SELECT_NUM_BITS $clog2(`BANK_LINE_COUNT) `define LINE_SELECT_SIZE_END `LINE_SELECT_NUM_BITS `define LINE_SELECT_ADDR_START 1+`BANK_SELECT_ADDR_END `define LINE_SELECT_ADDR_END `LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START `define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START `define LINE_SELECT_SIZE_RNG `LINE_SELECT_SIZE_END-1:0 -`define TAG_SELECT_NUM_BITS 32-`LINE_SELECT_ADDR_RNG+1 +`define TAG_SELECT_NUM_BITS 32-(`OFFSET_ADDR_NUM_BITS + `WORD_SELECT_NUM_BITS + `BANK_SELECT_NUM_BITS + `LINE_SELECT_NUM_BITS) `define TAG_SELECT_SIZE_END `TAG_SELECT_NUM_BITS -`define TAG_SELECT_ADDR_START 1+`LINE_SELECT_ADDR_RNG -`define TAG_SELECT_ADDR_END `TAG_SELECT_SIZE_END+`TAG_SELECT_ADDR_START -`define TAG_SELECT_ADDR_RNG `TAG_SELECT_ADDR_END:`TAG_SELECT_ADDR_START +`define TAG_SELECT_ADDR_START 1+`LINE_SELECT_ADDR_END +`define TAG_SELECT_ADDR_RNG 31:`TAG_SELECT_ADDR_START `define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0 +`define BASE_ADDR_MASK (~((1<<`WORD_SELECT_ADDR_END)-1)) +`endif + diff --git a/rtl/VX_cache/VX_cache_core_req_bank_sel.v b/rtl/VX_cache/VX_cache_core_req_bank_sel.v index 85a324d0..841138b5 100644 --- a/rtl/VX_cache/VX_cache_core_req_bank_sel.v +++ b/rtl/VX_cache/VX_cache_core_req_bank_sel.v @@ -7,16 +7,18 @@ module VX_cache_core_req_bank_sel ( output reg [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids ); + wire[31:0] req_address; generate integer curr_req; always @(*) begin + per_bank_valids = 0; for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin if (`NUMBER_BANKS == 1) begin // If there is only one bank, then only map requests to that bank - per_bank_valids[0][curr_req] <= core_req_valid[curr_req]; + assign per_bank_valids[0][curr_req] = core_req_valid[curr_req]; end else begin - per_bank_valids[core_req_addr[`BANK_SELECT_ADDR_RNG]][curr_req] <= core_req_valid[curr_req]; + assign per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req]; end end end diff --git a/rtl/VX_cache/VX_cache_dfq_queue.v b/rtl/VX_cache/VX_cache_dfq_queue.v index e0af7a2c..6e0f2dce 100644 --- a/rtl/VX_cache/VX_cache_dfq_queue.v +++ b/rtl/VX_cache/VX_cache_dfq_queue.v @@ -33,7 +33,7 @@ module VX_cache_dfq_queue wire push_qual = dfqq_push && !dfqq_full; wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty; - VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`dFQQ_SIZE)) dfqq_queue( + VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( .clk (clk), .reset (reset), .push (push_qual), @@ -62,7 +62,7 @@ module VX_cache_dfq_queue assign updated_bank_dram_fill_req = qual_bank_dram_fill_req & (~(1 << qual_request_index)); - always @(posedge clk or reset) begin + always @(posedge clk) begin if (reset) begin use_per_bank_dram_fill_req <= 0; use_per_bank_dram_fill_req_addr <= 0; diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index 9c54c94e..6b143824 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -12,10 +12,10 @@ module VX_cache_dram_req_arb ( input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, // DFQ Request - output wire[`NUMBER_BANKS-1] per_bank_dram_wb_queue_pop, - input wire[`NUMBER_BANKS-1] per_bank_dram_wb_req, - input wire[`NUMBER_BANKS-1][31:0] per_bank_dram_wb_req_addr, - input wire[`NUMBER_BANKS-1][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, + output wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop, + input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req, + input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, + input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, // real Dram request output wire dram_req, @@ -29,10 +29,10 @@ module VX_cache_dram_req_arb ( wire dfqq_req; - wire dfqq_req_addr; + wire[31:0] dfqq_req_addr; wire dfqq_empty; wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop - wire dfqq_push = (|per_bank_dram_wb_queue_pop); + wire dfqq_push = (|per_bank_dram_fill_req); VX_cache_dfq_queue VX_cache_dfq_queue( .clk (clk), .reset (reset), @@ -48,7 +48,7 @@ module VX_cache_dram_req_arb ( wire dwb_valid; - wire[`vx_log2(`NUMBER_BANKS)-1:0] dwb_bank; + wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank; VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb( .valids(per_bank_dram_wb_req), .index (dwb_bank), @@ -62,7 +62,7 @@ module VX_cache_dram_req_arb ( assign dram_req = dwb_valid || dfqq_req; assign dram_req_write = dwb_valid; assign dram_req_read = dfqq_req && !dwb_valid; - assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr; + assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK; assign dram_req_size = `BANK_LINE_SIZE_BYTES; assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v index 5bed7ee0..9724e761 100644 --- a/rtl/VX_cache/VX_cache_miss_resrv.v +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -69,7 +69,7 @@ module VX_cache_miss_resrv ( wire update_ready = (|make_ready); integer i; - always @(posedge clk or reset) begin + always @(posedge clk) begin if (reset) begin for (i = 0; i < `MRVQ_SIZE; i=i+1) metadata_table[i] <= 0; valid_table <= 0; @@ -85,7 +85,7 @@ module VX_cache_miss_resrv ( end if (update_ready) begin - ready_table = ready_table | make_ready; + ready_table <= ready_table | make_ready; end if (miss_resrv_pop && dequeue_possible) begin diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 422203f0..5d2451ad 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -69,11 +69,11 @@ module VX_cache_req_queue ( wire push_qual = reqq_push && !reqq_full; wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty; - VX_generic_queue #(.DATAW(`NUMBER_REQUESTS * (1+32+32+5+2+(`NW_M1+1)+3+3)), .SIZE(`REQQ_SIZE)) reqq_queue( + VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), .push (push_qual), - .in_data ({bank_valids, bank_addr, bank_writedata, bank_rd, bank_wb, bank_warp_num, bank_mem_read, bank_mem_write}), + .in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write}), .pop (pop_qual), .out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write}), .empty (reqq_empty), @@ -82,7 +82,7 @@ module VX_cache_req_queue ( - assign qual_valids = use_empty ? out_per_valids : use_per_valids; + assign qual_valids = use_empty ? out_per_valids : out_empty ? 0 : use_per_valids; assign qual_addr = use_empty ? out_per_addr : use_per_addr; assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata; assign qual_rd = use_empty ? out_per_rd : use_per_rd; @@ -105,13 +105,13 @@ module VX_cache_req_queue ( assign reqq_req_writedata_st0 = qual_writedata[qual_request_index]; assign reqq_req_rd_st0 = qual_rd; assign reqq_req_wb_st0 = qual_wb; - assign reqq_req_warp_num_st0 = qual_warp_num + assign reqq_req_warp_num_st0 = qual_warp_num; assign reqq_req_mem_read_st0 = qual_mem_read; assign reqq_req_mem_write_st0 = qual_mem_write; assign updated_valids = qual_valids & (~(1 << qual_request_index)); - always @(posedge clk or reset) begin + always @(posedge clk) begin if (reset) begin use_per_valids <= 0; use_per_addr <= 0; @@ -131,6 +131,8 @@ module VX_cache_req_queue ( use_per_warp_num <= qual_warp_num; use_per_mem_read <= qual_mem_read; use_per_mem_write <= qual_mem_write; + end else if (reqq_pop) begin + use_per_valids[qual_request_index] <= updated_valids; end end end diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v index 80f1d39e..b4806dd1 100644 --- a/rtl/VX_cache/VX_cache_wb_sel_merge.v +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -4,6 +4,7 @@ module VX_cache_wb_sel_merge ( // Per Bank WB + input wire [`NUMBER_BANKS-1:0] per_bank_wb_valid, input wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid, input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, @@ -15,19 +16,19 @@ module VX_cache_wb_sel_merge ( // Core Writeback input wire core_no_wb_slot, output reg [`NUMBER_REQUESTS-1:0] core_wb_valid, - output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata + output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, output wire [4:0] core_wb_req_rd, output wire [1:0] core_wb_req_wb, - output wire [`NW_M1:0] core_wb_warp_num, + output wire [`NW_M1:0] core_wb_warp_num ); - wire [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; + reg [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; assign per_bank_wb_pop = per_bank_wb_pop_unqual & {`NUMBER_BANKS{core_no_wb_slot}}; wire[`NUMBER_BANKS-1:0] bank_wants_wb; + genvar curr_bank; generate - integer curr_bank; for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]); end @@ -47,17 +48,17 @@ module VX_cache_wb_sel_merge ( assign core_wb_req_wb = per_bank_wb_wb [main_bank_index]; assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index]; + genvar this_bank; generate - integer this_bank; - for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin - if ((per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) - && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index])) begin - - assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1; - assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; - assign per_bank_wb_pop_unqual[this_bank] = 1; - end else - assign per_bank_wb_pop_unqual[this_bank] = 0; + always @(*) begin + for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin + if (found_bank && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin + assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1; + assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; + assign per_bank_wb_pop_unqual[this_bank] = 1; + end else begin + assign per_bank_wb_pop_unqual[this_bank] = 0; + end end end endgenerate diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 0c35236c..e6452a57 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -54,7 +54,7 @@ module VX_tag_data_access ( .read_valid (qual_read_valid_st1), .read_dirty (qual_read_dirty_st1), .read_tag (qual_read_tag_st1), - .read_data (qual_read_data_st1) + .read_data (qual_read_data_st1), .write_enable(use_write_enable), .write_fill (writefill_st1e), @@ -62,7 +62,7 @@ module VX_tag_data_access ( .write_data (use_write_data) ); - VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_RNG*32) )) s0_1_c0 ( + VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_c0 ( .clk (clk), .reset(reset), .stall(stall), @@ -74,12 +74,12 @@ module VX_tag_data_access ( genvar curr_stage; generate for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin - VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_RNG*32) )) s0_1_cc ( + VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall), .flush(0), - .in ({read_valid_st1c[curr_stage-1] , read_dirty_st1c[curr_stage-1] , read_tag_st1c[curr_stage-1] , read_data_st1c[curr_stage-1]}) + .in ({read_valid_st1c[curr_stage-1] , read_dirty_st1c[curr_stage-1] , read_tag_st1c[curr_stage-1] , read_data_st1c[curr_stage-1]}), .out ({read_valid_st1c[curr_stage] , read_dirty_st1c[curr_stage] , read_tag_st1c[curr_stage] , read_data_st1c[curr_stage] }) ); end @@ -120,14 +120,14 @@ module VX_tag_data_access ( wire[31:0] lw_data = (data_unQual); - wire[31:0] sw_data = writedata_st1e; + wire[31:0] sw_data = writeword_st1e; - wire[31:0] sb_data = b1 ? {{16{1'b0}}, writedata_st1e[7:0], { 8{1'b0}}} : - b2 ? {{ 8{1'b0}}, writedata_st1e[7:0], {16{1'b0}}} : - b3 ? {{ 0{1'b0}}, writedata_st1e[7:0], {24{1'b0}}} : - writedata_st1e; + wire[31:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} : + b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} : + b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} : + writeword_st1e; - wire[31:0] sh_data = b2 ? {writedata_st1e[15:0], {16{1'b0}}} : writedata_st1e; + wire[31:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e; @@ -158,7 +158,7 @@ module VX_tag_data_access ( wire[`BANK_LINE_SIZE_RNG][31:0] data_write; genvar g; generate - for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin : write_enables + for (g = 0; g < `BANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables wire normal_write = (block_offset == g) && should_write; assign we[g] = (force_write) ? 4'b1111 : @@ -177,7 +177,7 @@ module VX_tag_data_access ( /////////////////////// assign readword_st1e = data_Qual; - assign miss_st1e = valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e) + assign miss_st1e = (valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)); assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e; assign readdata_st1e = use_read_data_st1e; assign readtag_st1e = use_read_tag_st1e; diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index 4f2cf141..da3f8b4d 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -15,19 +15,20 @@ module VX_tag_data_structure ( ); - reg[`BANK_LINE_SIZE_RNG:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; + reg[`BANK_LINE_SIZE_RNG][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0]; reg valid[`BANK_LINE_COUNT-1:0]; reg dirty[`BANK_LINE_COUNT-1:0]; - assign read_valid <= valid[read_addr[`LINE_SELECT_ADDR_RNG]]; - assign read_dirty <= dirty[read_addr[`LINE_SELECT_ADDR_RNG]]; - assign read_tag <= tag [read_addr[`LINE_SELECT_ADDR_RNG]]; - assign read_data <= data [read_addr[`LINE_SELECT_ADDR_RNG]]; + assign read_valid = valid[read_addr[`LINE_SELECT_ADDR_RNG]]; + assign read_dirty = dirty[read_addr[`LINE_SELECT_ADDR_RNG]]; + assign read_tag = tag [read_addr[`LINE_SELECT_ADDR_RNG]]; + assign read_data = data [read_addr[`LINE_SELECT_ADDR_RNG]]; wire going_to_write = (|write_enable); + integer f; always @(posedge clk) begin if (going_to_write) begin valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1; @@ -40,10 +41,10 @@ module VX_tag_data_structure ( end for (f = 0; f < `BANK_LINE_SIZE_WORDS; f = f + 1) begin - if (write_enable[f][0]) data[addr[`LINE_SELECT_ADDR_RNG]][f][0] <= data_write[f][7 :0 ]; - if (write_enable[f][1]) data[addr[`LINE_SELECT_ADDR_RNG]][f][1] <= data_write[f][15:8 ]; - if (write_enable[f][2]) data[addr[`LINE_SELECT_ADDR_RNG]][f][2] <= data_write[f][23:16]; - if (write_enable[f][3]) data[addr[`LINE_SELECT_ADDR_RNG]][f][3] <= data_write[f][31:24]; + if (write_enable[f][0]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][0] <= write_data[f][7 :0 ]; + if (write_enable[f][1]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][1] <= write_data[f][15:8 ]; + if (write_enable[f][2]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][2] <= write_data[f][23:16]; + if (write_enable[f][3]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][3] <= write_data[f][31:24]; end end diff --git a/rtl/VX_define.v b/rtl/VX_define.v index f177fbfb..c92ce429 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -1,6 +1,9 @@ `include "./VX_define_synth.v" +// `include "./VX_cache/VX_cache_config.v" +// `ifndef VX_DEFINE +// `define VX_DEFINE `define NT_M1 (`NT-1) @@ -267,3 +270,7 @@ `define SHARED_MEMORY_BLOCK_OFFSET_ED (`SHARED_MEMORY_BLOCK_OFFSET_ST +`SHARED_MEMORY_LOG_WORDS_PER_READ-1) `define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1) `define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1) + + + +// `endif diff --git a/rtl/VX_define_synth.v b/rtl/VX_define_synth.v index 0444fe94..dcb3a609 100644 --- a/rtl/VX_define_synth.v +++ b/rtl/VX_define_synth.v @@ -1,2 +1,9 @@ -`define NT 4 + +// `ifndef VX_DEFINE_SYNTH + +// `define VX_DEFINE_SYNTH + +`define NT 2 `define NW 8 + +// `endif diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index c0e57c5c..93f26e62 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -66,8 +66,8 @@ module VX_dmem_controller ( .clk (clk), .reset (reset), .in_valid (sm_driver_in_valid), - .in_address(cache_driver_in_address), - .in_data (cache_driver_in_data), + .in_address(VX_dcache_req.core_req_addr), + .in_data (VX_dcache_req.core_req_writedata), .mem_read (sm_driver_in_mem_read), .mem_write (sm_driver_in_mem_write), .out_valid (cache_driver_out_valid), @@ -117,7 +117,7 @@ module VX_dmem_controller ( .dram_req_read (VX_gpu_dcache_dram_req.dram_req_read), .dram_req_addr (VX_gpu_dcache_dram_req.dram_req_addr), .dram_req_size (VX_gpu_dcache_dram_req.dram_req_size), - .dram_req_data (VX_gpu_dcache_dram_req.dram_req_data), + .dram_req_data (VX_gpu_dcache_dram_req.dram_req_data) ); diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index bcb08c83..cde7d725 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -98,9 +98,9 @@ module VX_fetch ( .scheduled_warp (scheduled_warp) ); - assign fe_inst_meta_fi.warp_num = warp_num; - assign fe_inst_meta_fi.valid = thread_mask && {`NT{!stall_might_be_branch}}; - + assign fe_inst_meta_fi.warp_num = warp_num; + assign fe_inst_meta_fi.valid = thread_mask && {`NT{!stall_might_be_branch}}; + assign fe_inst_meta_fi.instruction = 32'h0; assign fe_inst_meta_fi.inst_pc = warp_pc; diff --git a/rtl/VX_front_end.v b/rtl/VX_front_end.v index 671b7ef7..b8d90c15 100644 --- a/rtl/VX_front_end.v +++ b/rtl/VX_front_end.v @@ -58,6 +58,10 @@ VX_fetch vx_fetch( ); wire freeze_fi_reg = total_freeze || icache_stage_delay; + + + + VX_f_d_reg vx_f_i_reg( .clk (clk), .reset (reset), @@ -77,7 +81,7 @@ VX_icache_stage VX_icache_stage( ); -VX_f_d_reg vx_i_d_reg( +VX_i_d_reg vx_i_d_reg( .clk (clk), .reset (reset), .in_freeze (total_freeze), diff --git a/rtl/VX_generic_queue.v b/rtl/VX_generic_queue.v index ca383fae..fd3d77e7 100644 --- a/rtl/VX_generic_queue.v +++ b/rtl/VX_generic_queue.v @@ -3,7 +3,7 @@ module VX_generic_queue #( parameter DATAW = 4, - parameter SIZE = 16 + parameter SIZE = 277 ) ( input wire clk, @@ -18,7 +18,7 @@ module VX_generic_queue ); - reg[SIZE-1:0] data[DATAW-1:0]; + reg[DATAW-1:0] data[SIZE-1:0]; reg[$clog2(SIZE)-1:0] head; reg[$clog2(SIZE)-1:0] tail; @@ -26,19 +26,21 @@ module VX_generic_queue assign full = head == (tail+1); integer i; - always @(posedge clk or reset) begin + always @(posedge clk) begin if (reset) begin head <= 0; tail <= 0; - for (i = 0; i < SIZE; i=i+1) data[i] <= DATAW'0; + for (i = 0; i < SIZE; i=i+1) begin + data[i] <= {DATAW{1'0}}; + end end else begin if (push && !full) begin data[tail] <= in_data; - tail = tail+1; + tail <= tail+1; end if (pop) begin - head = head + 1; + head <= head + 1; end end diff --git a/rtl/VX_generic_register.v b/rtl/VX_generic_register.v index 7a1a023d..04de60ac 100644 --- a/rtl/VX_generic_register.v +++ b/rtl/VX_generic_register.v @@ -1,20 +1,17 @@ - module VX_generic_register - #( - parameter N = 1 - ) + #( parameter N = 1) ( - input clk, - input reset, - input stall, - input flush, - input[N-1:0] in, - output [N-1:0] out + input wire clk, + input wire reset, + input wire stall, + input wire flush, + input wire[(N-1):0] in, + output wire[(N-1):0] out ); - reg[N-1:0] value; + reg[(N-1):0] value; diff --git a/rtl/Vortex.v b/rtl/Vortex.v index d400ec81..5a420873 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -1,6 +1,6 @@ -`include "VX_define.v" - +// `include "VX_define.v" +`include "./VX_cache/VX_cache_config.v" module Vortex /*#( @@ -51,15 +51,13 @@ module Vortex reg[31:0] icache_banks = `ICACHE_BANKS; reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK; - +reg[31:0] number_threads = `NT; +reg[31:0] number_warps = `NW; always @(posedge clk) begin icache_banks <= icache_banks; icache_num_words_per_block <= icache_num_words_per_block; - dcache_banks <= dcache_banks; - dcache_num_words_per_block <= dcache_num_words_per_block; - number_threads <= number_threads; number_warps <= number_warps; end @@ -133,7 +131,6 @@ for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed end end -endgenerate ///////////////////////////////////////////////////////////////////////// diff --git a/rtl/pipe_regs/VX_f_d_reg.v b/rtl/pipe_regs/VX_f_d_reg.v index 0d5d99a8..50003179 100644 --- a/rtl/pipe_regs/VX_f_d_reg.v +++ b/rtl/pipe_regs/VX_f_d_reg.v @@ -13,9 +13,7 @@ module VX_f_d_reg ( wire flush = 1'b0; wire stall = in_freeze == 1'b1; - - VX_generic_register #(.N(64 + `NW_M1 + 1 + `NT)) f_d_reg - ( + VX_generic_register #( .N(64+`NW_M1+1+`NT) ) f_d_reg ( .clk (clk), .reset(reset), .stall(stall), diff --git a/rtl/pipe_regs/VX_i_d_reg.v b/rtl/pipe_regs/VX_i_d_reg.v new file mode 100644 index 00000000..2b7740c4 --- /dev/null +++ b/rtl/pipe_regs/VX_i_d_reg.v @@ -0,0 +1,27 @@ +`include "../VX_define.v" + +module VX_i_d_reg ( + input wire clk, + input wire reset, + input wire in_freeze, + + VX_inst_meta_inter fe_inst_meta_fd, + VX_inst_meta_inter fd_inst_meta_de + +); + + wire flush = 1'b0; + wire stall = in_freeze == 1'b1; + + + VX_generic_register #( .N( 64 + `NW_M1 + 1 + `NT ) ) i_d_reg ( + .clk (clk), + .reset(reset), + .stall(stall), + .flush(flush), + .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), + .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) + ); + + +endmodule \ No newline at end of file From b038bdb491bd33daca34fe9a39fa58582a399a79 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Wed, 4 Mar 2020 23:24:32 -0800 Subject: [PATCH 20/66] New Cache Design Passing All Tests --- rtl/VX_cache/VX_bank.v | 71 ++++++++++----- rtl/VX_cache/VX_cache_config.v | 8 +- rtl/VX_cache/VX_cache_req_queue.v | 18 ++-- rtl/VX_cache/VX_cache_wb_sel_merge.v | 6 +- rtl/VX_cache/VX_tag_data_access.v | 38 +++++--- rtl/VX_cache/VX_tag_data_structure.v | 7 +- rtl/VX_fetch.v | 4 +- rtl/VX_front_end.v | 7 ++ rtl/VX_generic_queue.v | 2 +- rtl/VX_icache_stage.v | 5 ++ rtl/simulate/test_bench.cpp | 4 +- rtl/simulate/test_bench.h | 127 ++++++++++++++++----------- 12 files changed, 194 insertions(+), 103 deletions(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 3167daf3..9896efe6 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -49,6 +49,7 @@ module VX_bank ( wire dfpq_full; wire[31:0] dfpq_addr_st0; wire[`BANK_LINE_SIZE_RNG][31:0] dfpq_filldata_st0; + reg dfpq_hazard_st0; assign dram_fill_accept = !dfpq_full; @@ -76,6 +77,7 @@ module VX_bank ( wire [`NW_M1:0] reqq_req_warp_num_st0; wire [2:0] reqq_req_mem_read_st0; wire [2:0] reqq_req_mem_write_st0; + reg reqq_hazard_st0; assign reqq_push = !delay_req && (|bank_valids); @@ -119,6 +121,7 @@ module VX_bank ( wire [`NW_M1:0] mrvq_warp_num_st0; wire [2:0] mrvq_mem_read_st0; wire [2:0] mrvq_mem_write_st0; + reg mrvq_hazard_st0; wire miss_add; wire[31:0] miss_add_addr; @@ -165,9 +168,27 @@ module VX_bank ( wire stall_bank_pipe; - assign dfpq_pop = !dfpq_empty && !stall_bank_pipe; - assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe; - assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0]; + assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0; + assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0; + assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0; + + + integer st1_cycle; + + always @(*) begin + assign dfpq_hazard_st0 = 0; + assign mrvq_hazard_st0 = 0; + assign reqq_hazard_st0 = 0; + for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin + if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin + if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign dfpq_hazard_st0 = 1; + if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign mrvq_hazard_st0 = 1; + if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign reqq_hazard_st0 = 1; + end + end + end + + wire qual_is_fill_st0; @@ -176,13 +197,15 @@ module VX_bank ( wire [31:0] qual_writeword_st0; wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0; wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0; + wire qual_going_to_write_st0; - wire valid_st1[`STAGE_1_CYCLES-1:0]; - wire [31:0] addr_st1[`STAGE_1_CYCLES-1:0]; - wire [31:0] writeword_st1[`STAGE_1_CYCLES-1:0]; - wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1[`STAGE_1_CYCLES-1:0]; - wire is_fill_st1[`STAGE_1_CYCLES-1:0]; - wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1[`STAGE_1_CYCLES-1:0]; + wire valid_st1 [`STAGE_1_CYCLES-1:0]; + wire going_to_write_st1[`STAGE_1_CYCLES-1:0]; + wire [31:0] addr_st1 [`STAGE_1_CYCLES-1:0]; + wire [31:0] writeword_st1 [`STAGE_1_CYCLES-1:0]; + wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [`STAGE_1_CYCLES-1:0]; + wire is_fill_st1 [`STAGE_1_CYCLES-1:0]; + wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [`STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop; @@ -202,25 +225,30 @@ module VX_bank ( reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} : 0; - VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_c0 ( + assign qual_going_to_write_st0 = dfpq_pop ? 1 : + (mrvq_pop && (mrvq_mem_write_st0 != `NO_MEM_WRITE)) ? 1 : + (reqq_pop && (reqq_req_mem_write_st0 != `NO_MEM_WRITE)) ? 1 : + 0; + + VX_generic_register #(.N( 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_c0 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), - .out ({valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]}) + .in ({qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), + .out ({going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]}) ); genvar curr_stage; generate for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin - VX_generic_register #(.N( 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc ( + VX_generic_register #(.N( 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}), - .out ({valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] }) + .in ({going_to_write_st1[curr_stage-1], valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}), + .out ({going_to_write_st1[curr_stage] , valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] }) ); end endgenerate @@ -239,6 +267,7 @@ module VX_bank ( wire [2:0] mem_read_st1e; wire [2:0] mem_write_st1e; wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] tid_st1e; + wire fill_saw_dirty_st1e; assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[`STAGE_1_CYCLES-1]; @@ -266,7 +295,8 @@ module VX_bank ( .readdata_st1e (readdata_st1e), .readtag_st1e (readtag_st1e), .miss_st1e (miss_st1e), - .dirty_st1e (dirty_st1e) + .dirty_st1e (dirty_st1e), + .fill_saw_dirty_st1e(fill_saw_dirty_st1e) ); wire qual_valid_st1e_2 = valid_st1[`STAGE_1_CYCLES-1] && !is_fill_st1[`STAGE_1_CYCLES-1]; @@ -281,14 +311,15 @@ module VX_bank ( wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2; wire[`TAG_SELECT_SIZE_RNG] readtag_st2; wire is_fill_st2; + wire fill_saw_dirty_st2; - VX_generic_register #(.N( 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 ( + VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), - .out ({is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) + .in ({fill_saw_dirty_st1e, is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), + .out ({fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) ); @@ -324,7 +355,7 @@ module VX_bank ( ); // Enqueue to DWB Queue - wire dwbq_push = valid_st2 && miss_st2 && dirty_st2; + wire dwbq_push = (valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2; wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]}; wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2; wire dwbq_empty; diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index c1844dcc..44c993b0 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -39,7 +39,7 @@ `define DFQQ_SIZE `REQQ_SIZE // Dram knobs - `define SIMULATED_DRAM_LATENCY_CYCLES 50 + `define SIMULATED_DRAM_LATENCY_CYCLES 10 // ========================================= Configurable Knobs ========================================= @@ -89,8 +89,8 @@ `define BANK_SIZE_BYTES `CACHE_SIZE_BYTES/`NUMBER_BANKS -`define BANK_LINE_COUNT `BANK_SIZE_BYTES/`BANK_LINE_SIZE_BYTES -`define BANK_LINE_SIZE_WORDS `BANK_LINE_SIZE_BYTES / `WORD_SIZE_BYTES +`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/`BANK_LINE_SIZE_BYTES) +`define BANK_LINE_SIZE_WORDS (`BANK_LINE_SIZE_BYTES / `WORD_SIZE_BYTES) `define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0 // Offset is fixed @@ -106,7 +106,7 @@ `define WORD_SELECT_ADDR_START 1+`OFFSET_ADDR_END `define WORD_SELECT_ADDR_END `WORD_SELECT_SIZE_END+`OFFSET_ADDR_END `define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START -`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:`WORD_SELECT_SIZE_END +`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0 `define BANK_SELECT_NUM_BITS $clog2(`NUMBER_BANKS) `define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 5d2451ad..7fce8ac5 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -69,6 +69,7 @@ module VX_cache_req_queue ( wire push_qual = reqq_push && !reqq_full; wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty; + VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), @@ -81,15 +82,16 @@ module VX_cache_req_queue ( ); + wire[`NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {`NUMBER_REQUESTS{~reqq_empty}}; - assign qual_valids = use_empty ? out_per_valids : out_empty ? 0 : use_per_valids; - assign qual_addr = use_empty ? out_per_addr : use_per_addr; - assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata; - assign qual_rd = use_empty ? out_per_rd : use_per_rd; - assign qual_wb = use_empty ? out_per_wb : use_per_wb; - assign qual_warp_num = use_empty ? out_per_warp_num : use_per_warp_num; - assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read; - assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write; + assign qual_valids = use_empty ? real_out_per_valids : out_empty ? 0 : use_per_valids; + assign qual_addr = use_empty ? out_per_addr : use_per_addr; + assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata; + assign qual_rd = use_empty ? out_per_rd : use_per_rd; + assign qual_wb = use_empty ? out_per_wb : use_per_wb; + assign qual_warp_num = use_empty ? out_per_warp_num : use_per_warp_num; + assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read; + assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write; wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] qual_request_index; wire qual_has_request; diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v index b4806dd1..08d97350 100644 --- a/rtl/VX_cache/VX_cache_wb_sel_merge.v +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -24,7 +24,7 @@ module VX_cache_wb_sel_merge ( ); reg [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; - assign per_bank_wb_pop = per_bank_wb_pop_unqual & {`NUMBER_BANKS{core_no_wb_slot}}; + assign per_bank_wb_pop = per_bank_wb_pop_unqual & {`NUMBER_BANKS{~core_no_wb_slot}}; wire[`NUMBER_BANKS-1:0] bank_wants_wb; genvar curr_bank; @@ -51,8 +51,10 @@ module VX_cache_wb_sel_merge ( genvar this_bank; generate always @(*) begin + assign core_wb_valid = 0; + assign core_wb_readdata = 0; for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin - if (found_bank && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin + if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1; assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; assign per_bank_wb_pop_unqual[this_bank] = 1; diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index e6452a57..2f342ab4 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -21,7 +21,8 @@ module VX_tag_data_access ( output wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e, output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e, output wire miss_st1e, - output wire dirty_st1e + output wire dirty_st1e, + output wire fill_saw_dirty_st1e ); @@ -46,6 +47,8 @@ module VX_tag_data_access ( wire[`BANK_LINE_SIZE_RNG][3:0] use_write_enable; wire[`BANK_LINE_SIZE_RNG][31:0] use_write_data; + + wire fill_sent; VX_tag_data_structure VX_tag_data_structure( .clk (clk), .reset (reset), @@ -59,7 +62,8 @@ module VX_tag_data_access ( .write_enable(use_write_enable), .write_fill (writefill_st1e), .write_addr (writeaddr_st1e), - .write_data (use_write_data) + .write_data (use_write_data), + .fill_sent (fill_sent) ); VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_c0 ( @@ -89,7 +93,10 @@ module VX_tag_data_access ( assign use_read_valid_st1e = read_valid_st1c[`STAGE_1_CYCLES-1]; assign use_read_dirty_st1e = read_dirty_st1c[`STAGE_1_CYCLES-1]; assign use_read_tag_st1e = read_tag_st1c [`STAGE_1_CYCLES-1]; - assign use_read_data_st1e = read_data_st1c [`STAGE_1_CYCLES-1]; + + genvar curr_w; + for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[`STAGE_1_CYCLES-1][curr_w][31:0]; + // assign use_read_data_st1e = read_data_st1c [`STAGE_1_CYCLES-1]; /////////////////////// LOAD LOGIC /////////////////// @@ -107,10 +114,17 @@ module VX_tag_data_access ( wire b2 = (byte_select == 2); wire b3 = (byte_select == 3); - wire[31:0] data_unQual = (b0 || lw) ? (use_read_data_st1e[block_offset]) : - b1 ? (use_read_data_st1e[block_offset] >> 8) : - b2 ? (use_read_data_st1e[block_offset] >> 16) : - (use_read_data_st1e[block_offset] >> 24); + wire[31:0] w0 = read_data_st1c[`STAGE_1_CYCLES-1][0][31:0]; + wire[31:0] w1 = read_data_st1c[`STAGE_1_CYCLES-1][1][31:0]; + wire[31:0] w2 = read_data_st1c[`STAGE_1_CYCLES-1][2][31:0]; + wire[31:0] w3 = read_data_st1c[`STAGE_1_CYCLES-1][3][31:0]; + + wire[31:0] data_unmod = read_data_st1c[`STAGE_1_CYCLES-1][block_offset][31:0]; + + wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) : + b1 ? (data_unmod >> 8) : + b2 ? (data_unmod >> 16) : + (data_unmod >> 24); wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF); @@ -151,8 +165,8 @@ module VX_tag_data_access ( wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); - wire should_write = (sw || sb || sh) && valid_req_st1e && !miss_st1e; - wire force_write = writefill_st1e && valid_req_st1e; + wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e; + wire force_write = writefill_st1e && valid_req_st1e && miss_st1e; wire[`BANK_LINE_SIZE_RNG][3:0] we; wire[`BANK_LINE_SIZE_RNG][31:0] data_write; @@ -161,13 +175,13 @@ module VX_tag_data_access ( for (g = 0; g < `BANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables wire normal_write = (block_offset == g) && should_write; - assign we[g] = (force_write) ? 4'b1111 : + assign we[g] = (force_write) ? 4'b1111 : (normal_write && sw) ? 4'b1111 : (normal_write && sb) ? sb_mask : (normal_write && sh) ? sh_mask : 4'b0000; - assign data_write[g] = force_write ? writedata_st1e : use_write_dat ; + assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat; end endgenerate @@ -181,6 +195,8 @@ module VX_tag_data_access ( assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e; assign readdata_st1e = use_read_data_st1e; assign readtag_st1e = use_read_tag_st1e; + assign fill_sent = miss_st1e; + assign fill_saw_dirty_st1e = force_write && dirty_st1e; endmodule diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index da3f8b4d..bad6f0ea 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -11,7 +11,8 @@ module VX_tag_data_structure ( input wire[`BANK_LINE_SIZE_RNG][3:0] write_enable, input wire write_fill, input wire[31:0] write_addr, - input wire[`BANK_LINE_SIZE_RNG][31:0] write_data + input wire[`BANK_LINE_SIZE_RNG][31:0] write_data, + input wire fill_sent ); @@ -38,7 +39,9 @@ module VX_tag_data_structure ( end else begin dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1; end - end + end else if (fill_sent) begin + dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; + end for (f = 0; f < `BANK_LINE_SIZE_WORDS; f = f + 1) begin if (write_enable[f][0]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][0] <= write_data[f][7 :0 ]; diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index cde7d725..35278807 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -8,6 +8,8 @@ module VX_fetch ( VX_join_inter VX_join, input wire schedule_delay, input wire icache_stage_delay, + input wire[`NW_M1:0] icache_stage_wid, + input wire[`NT-1:0] icache_stage_valids, output wire out_ebreak, VX_jal_response_inter VX_jal_rsp, @@ -40,7 +42,7 @@ module VX_fetch ( // Locals - assign pipe_stall = schedule_delay || icache_stage_delay || stall_might_be_branch; + assign pipe_stall = schedule_delay || icache_stage_delay || (stall_might_be_branch && (icache_stage_wid == warp_num)) ; VX_warp_scheduler warp_scheduler( .clk (clk), diff --git a/rtl/VX_front_end.v b/rtl/VX_front_end.v index b8d90c15..0ab8288f 100644 --- a/rtl/VX_front_end.v +++ b/rtl/VX_front_end.v @@ -37,6 +37,9 @@ wire icache_stage_delay; wire vortex_ebreak; wire terminate_sim; +wire[`NW_M1:0] icache_stage_wid; +wire[`NT-1:0] icache_stage_valids; + assign fetch_ebreak = vortex_ebreak || terminate_sim; @@ -46,6 +49,8 @@ VX_join_inter VX_join(); VX_fetch vx_fetch( .clk (clk), .reset (reset), + .icache_stage_wid (icache_stage_wid), + .icache_stage_valids(icache_stage_valids), .VX_wstall (VX_wstall), .VX_join (VX_join), .schedule_delay (schedule_delay), @@ -74,6 +79,8 @@ VX_icache_stage VX_icache_stage( .clk (clk), .reset (reset), .icache_stage_delay(icache_stage_delay), + .icache_stage_valids(icache_stage_valids), + .icache_stage_wid (icache_stage_wid), .fe_inst_meta_fi (fe_inst_meta_fi2), .fe_inst_meta_id (fe_inst_meta_id), .icache_response (icache_response_fe), diff --git a/rtl/VX_generic_queue.v b/rtl/VX_generic_queue.v index fd3d77e7..f388c6d3 100644 --- a/rtl/VX_generic_queue.v +++ b/rtl/VX_generic_queue.v @@ -39,7 +39,7 @@ module VX_generic_queue tail <= tail+1; end - if (pop) begin + if (pop && !empty) begin head <= head + 1; end diff --git a/rtl/VX_icache_stage.v b/rtl/VX_icache_stage.v index daeaef5b..3c6b3c3d 100644 --- a/rtl/VX_icache_stage.v +++ b/rtl/VX_icache_stage.v @@ -4,6 +4,8 @@ module VX_icache_stage ( input wire clk, input wire reset, output wire icache_stage_delay, + output wire[`NW_M1:0] icache_stage_wid, + output wire[`NT-1:0] icache_stage_valids, VX_inst_meta_inter fe_inst_meta_fi, VX_inst_meta_inter fe_inst_meta_id, VX_icache_response_inter icache_response, @@ -27,5 +29,8 @@ module VX_icache_stage ( assign fe_inst_meta_id.warp_num = fe_inst_meta_fi.warp_num; assign fe_inst_meta_id.valid = fe_inst_meta_fi.valid & {`NT{!icache_stage_delay}}; + assign icache_stage_wid = fe_inst_meta_fi.warp_num; + assign icache_stage_valids = fe_inst_meta_fi.valid; + endmodule \ No newline at end of file diff --git a/rtl/simulate/test_bench.cpp b/rtl/simulate/test_bench.cpp index 8eb90aa4..8b2e7e9e 100644 --- a/rtl/simulate/test_bench.cpp +++ b/rtl/simulate/test_bench.cpp @@ -87,7 +87,9 @@ int main(int argc, char **argv) #else - char testing[] = "../../emulator/riscv_tests/rv32ui-p-auipc.hex"; + // char testing[] = "../../runtime/mains/simple/vx_simple_main.hex"; + // char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex"; + char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; Vortex v; // const char *testing; diff --git a/rtl/simulate/test_bench.h b/rtl/simulate/test_bench.h index 3a001377..72d26652 100644 --- a/rtl/simulate/test_bench.h +++ b/rtl/simulate/test_bench.h @@ -28,6 +28,14 @@ double sc_time_stamp() return time_stamp / 1000.0; } +typedef struct +{ + int cycles_left; + int data_length; + unsigned base_addr; + unsigned * data; +} dram_req_t; + class Vortex { public: @@ -69,6 +77,7 @@ class Vortex int debug_end_wait; int debug_debugAddr; double stats_sim_time; + std::vector dram_req_vec; #ifdef VCD_OUTPUT VerilatedVcdC *m_trace; #endif @@ -235,65 +244,77 @@ void Vortex::io_handler() bool Vortex::dbus_driver() { - vortex->i_m_ready_d = false; - + // Iterate through each element, and get pop index + int dequeue_index = -1; + bool dequeue_valid = false; + for (int i = 0; i < this->dram_req_vec.size(); i++) { - - // int dcache_num_words_per_block - - if (refill_d) + if (this->dram_req_vec[i].cycles_left > 0) { - refill_d = false; - vortex->i_m_ready_d = true; - - for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++) - { - for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++) - { - unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank; - unsigned curr_addr = refill_addr_d + (4*curr_index); - - unsigned curr_value; - ram.getWord(curr_addr, &curr_value); - - vortex->i_m_readdata_d[curr_bank][curr_word] = curr_value; - - } - } - } - else - { - if (vortex->o_m_valid_d) - { - - if (vortex->o_m_read_or_write_d) - { - // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); - unsigned base_addr = vortex->o_m_evict_addr_d; - - for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++) - { - for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++) - { - unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank; - unsigned curr_addr = base_addr + (4*curr_index); - - unsigned curr_value = vortex->o_m_writedata_d[curr_bank][curr_word]; - - ram.writeWord( curr_addr, &curr_value); - } - } - } - - // Respond next cycle - refill_d = true; - refill_addr_d = vortex->o_m_read_addr_d; - } + this->dram_req_vec[i].cycles_left -= 1; } + if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) + { + dequeue_index = i; + dequeue_valid = true; + } } + if (vortex->dram_req) + { + if (vortex->dram_req_read) + { + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = vortex->dram_expected_lat; + dram_req.data_length = vortex->dram_req_size / 4; + dram_req.base_addr = vortex->dram_req_addr; + dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); + + for (int i = 0; i < dram_req.data_length; i++) + { + unsigned curr_addr = dram_req.base_addr + (i*4); + unsigned data_rd; + ram.getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + this->dram_req_vec.push_back(dram_req); + } + + if (vortex->dram_req_write) + { + unsigned base_addr = vortex->dram_req_addr; + unsigned data_length = vortex->dram_req_size / 4; + + for (int i = 0; i < data_length; i++) + { + unsigned curr_addr = base_addr + (i*4); + unsigned data_wr = vortex->dram_req_data[i]; + ram.writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex->dram_fill_accept && dequeue_valid) + { + vortex->dram_fill_rsp = 1; + vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; + for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) + { + vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; + } + free(this->dram_req_vec[dequeue_index].data); + + this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index); + } + else + { + vortex->dram_fill_rsp = 0; + vortex->dram_fill_rsp_addr = 0; + } + return false; } @@ -430,4 +451,4 @@ bool Vortex::simulate(std::string file_to_simulate) return (status == 1); // return (1 == 1); -} \ No newline at end of file +} From e0620a6f6ac216b42c6024992cf753e2fe96f053 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Wed, 4 Mar 2020 23:55:02 -0800 Subject: [PATCH 21/66] Added fill_invalidator --- rtl/VX_cache/VX_bank.v | 15 ++++- rtl/VX_cache/VX_cache_config.v | 4 ++ rtl/VX_cache/VX_fill_invalidator.v | 89 ++++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+), 1 deletion(-) create mode 100644 rtl/VX_cache/VX_fill_invalidator.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 9896efe6..3025d635 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -361,8 +361,21 @@ module VX_bank ( wire dwbq_empty; wire dwbq_full; + + wire invalidate_fill; + wire possible_fill = valid_st2 && miss_st2; + VX_fill_invalidator VX_fill_invalidator( + .clk (clk), + .reset (reset), + .possible_fill (possible_fill), + .success_fill (is_fill_st2), + .fill_addr (addr_st2), + + .invalidate_fill (invalidate_fill) + ); + // Enqueu in dram_fill_req - assign dram_fill_req = valid_st2 && miss_st2; + assign dram_fill_req = valid_st2 && miss_st2 && !invalidate_fill; assign dram_fill_req_addr = addr_st2; assign dram_wb_req = !dwbq_empty; diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 44c993b0..2c5dffa2 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -37,6 +37,10 @@ `define DWBQ_SIZE 4 // Dram Fill Req Queue Size `define DFQQ_SIZE `REQQ_SIZE + // Fill Invalidator Active {Comment out define statement to invalidate} + `define FILL_INVALIDATOR_ACTIVE 1 + // Fill Invalidator Size {Fill invalidator must be active} + `define FILL_INVALIDAOR_SIZE 16 // Dram knobs `define SIMULATED_DRAM_LATENCY_CYCLES 10 diff --git a/rtl/VX_cache/VX_fill_invalidator.v b/rtl/VX_cache/VX_fill_invalidator.v new file mode 100644 index 00000000..c9546610 --- /dev/null +++ b/rtl/VX_cache/VX_fill_invalidator.v @@ -0,0 +1,89 @@ + +`include "VX_cache_config.v" + +module VX_fill_invalidator ( + input wire clk, + input wire reset, + + input wire possible_fill, + input wire success_fill, + + input wire[31:0] fill_addr, + + output reg invalidate_fill + +); + + + `ifndef FILL_INVALIDATOR_ACTIVE + + assign invalidate_fill = 0; + + `else + + reg[`FILL_INVALIDAOR_SIZE-1:0] fills_active; + reg[`FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address; + + + reg success_found; + reg[(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] success_index; + + integer curr_fill; + always @(*) begin + assign invalidate_fill = 0; + assign success_found = 0; + assign success_index = 0; + for (curr_fill = 0; curr_fill < `FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin + + if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin + if (possible_fill && fills_active[curr_fill]) begin + assign invalidate_fill = 1; + end + + if (success_fill) begin + assign success_found = 1; + assign success_index = curr_fill; + end + end + end + end + + + + + wire [(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; + wire enqueue_found; + + VX_generic_priority_encoder #(.N(`FILL_INVALIDAOR_SIZE)) VX_sel_bank( + .valids(fills_active), + .index (enqueue_index), + .found (enqueue_found) + ); + + + reg[`FILL_INVALIDAOR_SIZE-1:0] new_valids; + + + + always @(posedge clk) begin + if (reset) begin + fills_active <= 0; + fills_address <= 0; + end else begin + if (enqueue_found && !invalidate_fill) begin + fills_active[enqueue_index] <= 1; + fills_address[enqueue_index] <= fill_addr; + end + + if (success_found) begin + fills_active[success_index] <= 0; + end + + end + end + + + `endif + + +endmodule \ No newline at end of file From 457e8644f35ff8654cdc0a53f7e752cfc4768aaa Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Thu, 5 Mar 2020 01:30:16 -0800 Subject: [PATCH 22/66] Added Snoop Invalidate/Writeback Req type --- rtl/VX_cache/VX_bank.v | 74 +++++++++++++++---- rtl/VX_cache/VX_cache.v | 41 ++++++++-- rtl/VX_cache/VX_cache_config.v | 3 + rtl/VX_cache/VX_cache_dram_req_arb.v | 22 +++--- rtl/VX_cache/VX_tag_data_access.v | 7 +- rtl/VX_cache/VX_tag_data_structure.v | 5 ++ rtl/VX_dmem_controller.v | 10 ++- rtl/interfaces/VX_gpu_dcache_dram_req_inter.v | 4 + rtl/interfaces/VX_gpu_dcache_snp_req_inter.v | 18 +++++ 9 files changed, 151 insertions(+), 33 deletions(-) create mode 100644 rtl/interfaces/VX_gpu_dcache_snp_req_inter.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 3025d635..51809b4a 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -28,6 +28,8 @@ module VX_bank ( // Dram Fill Requests output wire dram_fill_req, output wire[31:0] dram_fill_req_addr, + output wire dram_because_of_snp, + output wire dram_snp_full, input wire dram_fill_req_queue_full, // Dram Fill Response @@ -40,10 +42,37 @@ module VX_bank ( input wire dram_wb_queue_pop, output wire dram_wb_req, output wire[31:0] dram_wb_req_addr, - output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data + output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data, + + // Snp Request + input wire snp_req, + input wire[31:0] snp_req_addr ); + + + wire snrq_pop; + wire snrq_empty; + wire snrq_full; + + wire snrq_valid_st0; + wire[31:0] snrq_addr_st0; + + reg snrq_hazard_st0; + + assign snrq_valid_st0 = !snrq_empty; + VX_generic_queue #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( + .clk (clk), + .reset (reset), + .push (snp_req), + .in_data (snp_req_addr), + .pop (snrq_pop), + .out_data(snrq_addr_st0), + .empty (snrq_empty), + .full (snrq_full) + ); + wire dfpq_pop; wire dfpq_empty; wire dfpq_full; @@ -171,6 +200,7 @@ module VX_bank ( assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0; assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0; assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0; + assign snrq_pop = !reqq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0; integer st1_cycle; @@ -179,11 +209,13 @@ module VX_bank ( assign dfpq_hazard_st0 = 0; assign mrvq_hazard_st0 = 0; assign reqq_hazard_st0 = 0; + assign snrq_hazard_st0 = 0; for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign dfpq_hazard_st0 = 1; if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign mrvq_hazard_st0 = 1; if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign reqq_hazard_st0 = 1; + if (snrq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign snrq_hazard_st0 = 1; end end end @@ -198,6 +230,7 @@ module VX_bank ( wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0; wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0; wire qual_going_to_write_st0; + wire qual_is_snp; wire valid_st1 [`STAGE_1_CYCLES-1:0]; wire going_to_write_st1[`STAGE_1_CYCLES-1:0]; @@ -206,13 +239,15 @@ module VX_bank ( wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [`STAGE_1_CYCLES-1:0]; wire is_fill_st1 [`STAGE_1_CYCLES-1:0]; wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [`STAGE_1_CYCLES-1:0]; + wire is_snp_st1 [`STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; - assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop; + assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop; assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 : mrvq_pop ? mrvq_addr_st0 : reqq_pop ? reqq_req_addr_st0 : + snrq_pop ? snrq_addr_st0 : 0; assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 : @@ -228,27 +263,30 @@ module VX_bank ( assign qual_going_to_write_st0 = dfpq_pop ? 1 : (mrvq_pop && (mrvq_mem_write_st0 != `NO_MEM_WRITE)) ? 1 : (reqq_pop && (reqq_req_mem_write_st0 != `NO_MEM_WRITE)) ? 1 : - 0; + (snrq_pop) ? 1 : + 0; - VX_generic_register #(.N( 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_c0 ( + assign qual_is_snp = snrq_pop ? 1 : 0; + + VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_c0 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), - .out ({going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]}) + .in ({qual_is_snp , qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}), + .out ({is_snp_st1[0], going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]}) ); genvar curr_stage; generate for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin - VX_generic_register #(.N( 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc ( + VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({going_to_write_st1[curr_stage-1], valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}), - .out ({going_to_write_st1[curr_stage] , valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] }) + .in ({is_snp_st1[curr_stage-1], going_to_write_st1[curr_stage-1], valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}), + .out ({is_snp_st1[curr_stage] , going_to_write_st1[curr_stage] , valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] }) ); end endgenerate @@ -268,6 +306,9 @@ module VX_bank ( wire [2:0] mem_write_st1e; wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] tid_st1e; wire fill_saw_dirty_st1e; + wire is_snp_st1e; + + assign is_snp_st1e = is_snp_st1[`STAGE_1_CYCLES-1]; assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[`STAGE_1_CYCLES-1]; @@ -290,6 +331,8 @@ module VX_bank ( .mem_write_st1e(mem_write_st1e), .mem_read_st1e (mem_read_st1e), + .is_snp_st1e (is_snp_st1e), + // Read Data .readword_st1e (readword_st1e), .readdata_st1e (readdata_st1e), @@ -312,14 +355,15 @@ module VX_bank ( wire[`TAG_SELECT_SIZE_RNG] readtag_st2; wire is_fill_st2; wire fill_saw_dirty_st2; + wire is_snp_st2; - VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 ( + VX_generic_register #(.N( 1 + 1 + 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({fill_saw_dirty_st1e, is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), - .out ({fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) + .in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), + .out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) ); @@ -331,7 +375,7 @@ module VX_bank ( // Enqueue to CWB Queue - wire cwbq_push = valid_st2 && !miss_st2; + wire cwbq_push = (valid_st2 && !miss_st2); wire [31:0] cwbq_data = readword_st2; wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; wire [4:0] cwbq_rd = miss_add_rd; @@ -370,12 +414,14 @@ module VX_bank ( .possible_fill (possible_fill), .success_fill (is_fill_st2), .fill_addr (addr_st2), - + .invalidate_fill (invalidate_fill) ); // Enqueu in dram_fill_req assign dram_fill_req = valid_st2 && miss_st2 && !invalidate_fill; + assign dram_because_of_snp = is_snp_st2 && valid_st2 && miss_st2; + assign dram_snp_full = snrq_full && snp_req; assign dram_fill_req_addr = addr_st2; assign dram_wb_req = !dwbq_empty; diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 661eb12b..6fbcab8c 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -39,7 +39,15 @@ module VX_cache ( output wire dram_req_read, output wire [31:0] dram_req_addr, output wire [31:0] dram_req_size, - output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data + output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data, + output wire dram_req_because_of_wb, + output wire dram_snp_full, + + + // Snoop Req + input wire snp_req, + input wire[31:0] snp_req_addr + ); @@ -60,6 +68,7 @@ module VX_cache ( wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; + wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp; wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; @@ -78,6 +87,7 @@ module VX_cache ( .per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr), .per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop), .per_bank_dram_wb_req (per_bank_dram_wb_req), + .per_bank_dram_because_of_snp(per_bank_dram_because_of_snp), .per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr), .per_bank_dram_wb_req_data (per_bank_dram_wb_req_data), .dram_req (dram_req), @@ -85,7 +95,8 @@ module VX_cache ( .dram_req_read (dram_req_read), .dram_req_addr (dram_req_addr), .dram_req_size (dram_req_size), - .dram_req_data (dram_req_data) + .dram_req_data (dram_req_data), + .dram_req_because_of_wb (dram_req_because_of_wb) ); @@ -140,6 +151,8 @@ module VX_cache ( wire curr_bank_dfqq_full; wire curr_bank_dram_fill_req; + wire curr_bank_dram_because_of_snp; + wire curr_bank_dram_snp_full; wire[31:0] curr_bank_dram_fill_req_addr; wire curr_bank_dram_wb_queue_pop; @@ -147,6 +160,9 @@ module VX_cache ( wire[31:0] curr_bank_dram_wb_req_addr; wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data; + wire curr_bank_snp_req; + wire[31:0] curr_bank_snp_req_addr; + wire curr_bank_reqq_full; // Core Req @@ -181,10 +197,15 @@ module VX_cache ( assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept; // Dram writeback request - assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank]; - assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req; - assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr; - assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data; + assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank]; + assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req; + assign per_bank_dram_because_of_snp[curr_bank] = curr_bank_dram_because_of_snp; + assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr; + assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data; + + // Snoop Request + assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); + assign curr_bank_snp_req_addr = snp_req_addr; VX_bank bank ( @@ -226,7 +247,13 @@ module VX_cache ( .dram_wb_queue_pop (curr_bank_dram_wb_queue_pop), .dram_wb_req (curr_bank_dram_wb_req), .dram_wb_req_addr (curr_bank_dram_wb_req_addr), - .dram_wb_req_data (curr_bank_dram_wb_req_data) + .dram_wb_req_data (curr_bank_dram_wb_req_data), + .dram_because_of_snp (curr_bank_dram_because_of_snp), + .dram_snp_full (curr_bank_dram_snp_full), + + // Snoop Request + .snp_req (curr_bank_snp_req), + .snp_req_addr (curr_bank_snp_req_addr) ); end diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 2c5dffa2..ea7f8a7d 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -29,6 +29,8 @@ `define MRVQ_SIZE `REQQ_SIZE // Dram Fill Rsp Queue Size `define DFPQ_SIZE 2 + // Snoop Req Queue + `define SNRQ_SIZE 8 // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size @@ -37,6 +39,7 @@ `define DWBQ_SIZE 4 // Dram Fill Req Queue Size `define DFQQ_SIZE `REQQ_SIZE + // Fill Invalidator Active {Comment out define statement to invalidate} `define FILL_INVALIDATOR_ACTIVE 1 // Fill Invalidator Size {Fill invalidator must be active} diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index 6b143824..edde582c 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -16,6 +16,7 @@ module VX_cache_dram_req_arb ( input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req, input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, + input wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp, // real Dram request output wire dram_req, @@ -23,7 +24,8 @@ module VX_cache_dram_req_arb ( output wire dram_req_read, output wire [31:0] dram_req_addr, output wire [31:0] dram_req_size, - output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data + output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data, + output wire dram_req_because_of_wb ); @@ -47,10 +49,11 @@ module VX_cache_dram_req_arb ( ); - wire dwb_valid; + wire dwb_valid; wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank; + wire[`NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb( - .valids(per_bank_dram_wb_req), + .valids(use_wb_valid), .index (dwb_bank), .found (dwb_valid) ); @@ -59,11 +62,12 @@ module VX_cache_dram_req_arb ( assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & (~(1 << dwb_bank)); - assign dram_req = dwb_valid || dfqq_req; - assign dram_req_write = dwb_valid; - assign dram_req_read = dfqq_req && !dwb_valid; - assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK; - assign dram_req_size = `BANK_LINE_SIZE_BYTES; - assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; + assign dram_req = dwb_valid || dfqq_req; + assign dram_req_write = dwb_valid; + assign dram_req_read = dfqq_req && !dwb_valid; + assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK; + assign dram_req_size = `BANK_LINE_SIZE_BYTES; + assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; + assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0; endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 2f342ab4..3ce6622c 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -4,7 +4,7 @@ module VX_tag_data_access ( input wire clk, input wire reset, input wire stall, - + input wire is_snp_st1e, // Initial Reading input wire[31:0] readaddr_st10, @@ -49,6 +49,7 @@ module VX_tag_data_access ( wire fill_sent; + wire invalidate_line; VX_tag_data_structure VX_tag_data_structure( .clk (clk), .reset (reset), @@ -59,6 +60,7 @@ module VX_tag_data_access ( .read_tag (qual_read_tag_st1), .read_data (qual_read_data_st1), + .invalidate (invalidate_line), .write_enable(use_write_enable), .write_fill (writefill_st1e), .write_addr (writeaddr_st1e), @@ -191,12 +193,13 @@ module VX_tag_data_access ( /////////////////////// assign readword_st1e = data_Qual; - assign miss_st1e = (valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)); + assign miss_st1e = ((valid_req_st1e || is_snp_st1e) && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)); assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e; assign readdata_st1e = use_read_data_st1e; assign readtag_st1e = use_read_tag_st1e; assign fill_sent = miss_st1e; assign fill_saw_dirty_st1e = force_write && dirty_st1e; + assign invalidate_line = is_snp_st1e && !miss_st1e; endmodule diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index bad6f0ea..42c5d086 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -8,6 +8,7 @@ module VX_tag_data_structure ( output wire[`TAG_SELECT_SIZE_RNG] read_tag, output wire[`BANK_LINE_SIZE_RNG][31:0] read_data, + input wire invalidate, input wire[`BANK_LINE_SIZE_RNG][3:0] write_enable, input wire write_fill, input wire[31:0] write_addr, @@ -43,6 +44,10 @@ module VX_tag_data_structure ( dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; end + if (invalidate) begin + valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; + end + for (f = 0; f < `BANK_LINE_SIZE_WORDS; f = f + 1) begin if (write_enable[f][0]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][0] <= write_data[f][7 :0 ]; if (write_enable[f][1]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][1] <= write_data[f][15:8 ]; diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 93f26e62..48749cef 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -117,7 +117,15 @@ module VX_dmem_controller ( .dram_req_read (VX_gpu_dcache_dram_req.dram_req_read), .dram_req_addr (VX_gpu_dcache_dram_req.dram_req_addr), .dram_req_size (VX_gpu_dcache_dram_req.dram_req_size), - .dram_req_data (VX_gpu_dcache_dram_req.dram_req_data) + .dram_req_data (VX_gpu_dcache_dram_req.dram_req_data), + + // Snoop Response + .dram_req_because_of_wb(VX_gpu_dcache_dram_req.dram_because_of_snp), + .dram_snp_full (VX_gpu_dcache_dram_req.dram_snp_full), + + // Snoop Request + .snp_req (0), + .snp_req_addr (0) ); diff --git a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v index 58170aa3..ccc58dc6 100644 --- a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v @@ -16,6 +16,10 @@ interface VX_gpu_dcache_dram_req_inter (); wire [31:0] dram_req_size; wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data; + // Snoop + wire dram_because_of_snp; + wire dram_snp_full; + // DRAM Cache can't accept response wire dram_fill_accept; diff --git a/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v b/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v new file mode 100644 index 00000000..bc7695d4 --- /dev/null +++ b/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v @@ -0,0 +1,18 @@ + + + +`include "../VX_cache/VX_cache_config.v" + +`ifndef VX_GPU_SNP_REQ + +`define VX_GPU_SNP_REQ + +interface VX_gpu_dcache_snp_req_inter (); + // Snoop Req + wire snp_req; + wire [31:0] snp_req_addr; + +endinterface + + +`endif \ No newline at end of file From 66a46f81ce3a0c3b3ae754d867ba687e30126a2c Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 5 Mar 2020 06:58:51 -0500 Subject: [PATCH 23/66] synthesis fixes --- rtl/VX_back_end.v | 2 - rtl/VX_cache/VX_bank.v | 12 +- rtl/VX_cache/VX_cache.v | 1 - rtl/VX_cache/VX_cache_config.v | 8 +- rtl/VX_cache/VX_cache_core_req_bank_sel.v | 5 +- rtl/VX_cache/VX_cache_dram_req_arb.v | 6 +- rtl/VX_cache/VX_cache_req_queue.v | 1 - rtl/VX_cache/VX_cache_wb_sel_merge.v | 15 +- rtl/VX_cache/quartus/Makefile | 72 + rtl/VX_cache/quartus/project.sdc | 1 + rtl/VX_cache/quartus/project.tcl | 41 + rtl/VX_csr_data.v | 1 - rtl/VX_csr_pipe.v | 130 +- rtl/VX_define.v | 17 +- rtl/VX_define_synth.v | 8 +- rtl/VX_dmem_controller.v | 7 +- rtl/VX_execute_unit.v | 280 ++-- rtl/VX_fetch.v | 1 - rtl/VX_generic_priority_encoder.v | 7 +- rtl/VX_generic_queue.v | 4 +- rtl/VX_generic_register.v | 4 - rtl/VX_generic_stack.v | 1 + rtl/VX_gpr_stage.v | 1 - rtl/VX_lsu.v | 38 +- rtl/VX_scheduler.v | 2 - rtl/VX_writeback.v | 124 +- rtl/Vortex.v | 102 +- rtl/byte_enabled_simple_dual_port_ram.v | 1 - rtl/cache/VX_Cache_Bank.v | 2 - rtl/cache/VX_cache_data.v | 2 - rtl/cache/VX_cache_data_per_index.v | 2 - rtl/cache/VX_d_cache.v | 5 +- rtl/cache/VX_d_cache_encapsulate.v | 1 - rtl/cache/quartus/Makefile | 70 + rtl/cache/quartus/project.sdc | 1 + rtl/cache/quartus/project.tcl | 41 + rtl/pipe_regs/VX_d_e_reg.v | 2 - rtl/quartus/Makefile | 41 +- rtl/quartus/VX_gpr_syn.qpf | 30 - rtl/quartus/VX_gpr_syn.qsf | 1615 --------------------- rtl/quartus/asm.chg | 1 - rtl/quartus/make_pins_virtual.tcl | 29 - rtl/quartus/map.chg | 2 +- rtl/quartus/project.tcl | 113 +- rtl/quartus/smart.log | 15 +- rtl/quartus/vortex.ini | 40 - rtl/quartus/vortex.sdc | 2 +- 47 files changed, 633 insertions(+), 2273 deletions(-) create mode 100755 rtl/VX_cache/quartus/Makefile create mode 100755 rtl/VX_cache/quartus/project.sdc create mode 100644 rtl/VX_cache/quartus/project.tcl create mode 100755 rtl/cache/quartus/Makefile create mode 100755 rtl/cache/quartus/project.sdc create mode 100644 rtl/cache/quartus/project.tcl delete mode 100644 rtl/quartus/VX_gpr_syn.qpf delete mode 100644 rtl/quartus/VX_gpr_syn.qsf delete mode 100644 rtl/quartus/asm.chg delete mode 100644 rtl/quartus/make_pins_virtual.tcl delete mode 100644 rtl/quartus/vortex.ini diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index 9a6445a9..9b51e9ed 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -18,7 +18,6 @@ module VX_back_end ( VX_gpu_dcache_res_inter VX_dcache_rsp, VX_gpu_dcache_req_inter VX_dcache_req - ); @@ -31,7 +30,6 @@ assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num; // assign VX_writeback_inter(VX_writeback_temp); - VX_mw_wb_inter VX_mw_wb(); wire no_slot_mem; wire no_slot_exec; diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 9896efe6..a7778af9 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -176,14 +176,14 @@ module VX_bank ( integer st1_cycle; always @(*) begin - assign dfpq_hazard_st0 = 0; - assign mrvq_hazard_st0 = 0; - assign reqq_hazard_st0 = 0; + dfpq_hazard_st0 = 0; + mrvq_hazard_st0 = 0; + reqq_hazard_st0 = 0; for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin - if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign dfpq_hazard_st0 = 1; - if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign mrvq_hazard_st0 = 1; - if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign reqq_hazard_st0 = 1; + if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1; + if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1; + if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) reqq_hazard_st0 = 1; end end end diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 661eb12b..4eb25663 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -1,6 +1,5 @@ `include "VX_cache_config.v" - module VX_cache ( input wire clk, input wire reset, diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 44c993b0..18ca6616 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -1,12 +1,10 @@ +`ifndef VX_CACHE_CONFIG +`define VX_CACHE_CONFIG `include "../VX_define.v" - -`ifndef VX_CACHE_CONFIG - -`define VX_CACHE_CONFIG - // ========================================= Configurable Knobs ========================================= + // General Cache Knobs // Size of cache in bytes `define CACHE_SIZE_BYTES 1024 diff --git a/rtl/VX_cache/VX_cache_core_req_bank_sel.v b/rtl/VX_cache/VX_cache_core_req_bank_sel.v index 841138b5..adef7953 100644 --- a/rtl/VX_cache/VX_cache_core_req_bank_sel.v +++ b/rtl/VX_cache/VX_cache_core_req_bank_sel.v @@ -1,5 +1,4 @@ - module VX_cache_core_req_bank_sel ( input wire [`NUMBER_REQUESTS-1:0] core_req_valid, input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, @@ -16,9 +15,9 @@ module VX_cache_core_req_bank_sel ( for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin if (`NUMBER_BANKS == 1) begin // If there is only one bank, then only map requests to that bank - assign per_bank_valids[0][curr_req] = core_req_valid[curr_req]; + per_bank_valids[0][curr_req] = core_req_valid[curr_req]; end else begin - assign per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req]; + per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req]; end end end diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index 6b143824..747a2ac6 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -1,6 +1,5 @@ `include "VX_cache_config.v" - module VX_cache_dram_req_arb ( input wire clk, input wire reset, @@ -27,12 +26,13 @@ module VX_cache_dram_req_arb ( ); - wire dfqq_req; wire[31:0] dfqq_req_addr; wire dfqq_empty; + wire dwb_valid; wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop wire dfqq_push = (|per_bank_dram_fill_req); + VX_cache_dfq_queue VX_cache_dfq_queue( .clk (clk), .reset (reset), @@ -46,8 +46,6 @@ module VX_cache_dram_req_arb ( .dfqq_full (dfqq_full) ); - - wire dwb_valid; wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank; VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb( .valids(per_bank_dram_wb_req), diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 7fce8ac5..7ebadfaa 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -1,4 +1,3 @@ - `include "VX_cache_config.v" module VX_cache_req_queue ( diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v index 08d97350..0898d66e 100644 --- a/rtl/VX_cache/VX_cache_wb_sel_merge.v +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -1,6 +1,5 @@ `include "VX_cache_config.v" - module VX_cache_wb_sel_merge ( // Per Bank WB @@ -48,18 +47,18 @@ module VX_cache_wb_sel_merge ( assign core_wb_req_wb = per_bank_wb_wb [main_bank_index]; assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index]; - genvar this_bank; + integer this_bank; generate always @(*) begin - assign core_wb_valid = 0; - assign core_wb_readdata = 0; + core_wb_valid = 0; + core_wb_readdata = 0; for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin - assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1; - assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; - assign per_bank_wb_pop_unqual[this_bank] = 1; + core_wb_valid[per_bank_wb_tid[this_bank]] = 1; + core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; + per_bank_wb_pop_unqual[this_bank] = 1; end else begin - assign per_bank_wb_pop_unqual[this_bank] = 0; + per_bank_wb_pop_unqual[this_bank] = 0; end end end diff --git a/rtl/VX_cache/quartus/Makefile b/rtl/VX_cache/quartus/Makefile new file mode 100755 index 00000000..1e1715cd --- /dev/null +++ b/rtl/VX_cache/quartus/Makefile @@ -0,0 +1,72 @@ +PROJECT = VX_cache +TOP_LEVEL_ENTITY = VX_cache +SRC_FILE = ../VX_cache.v +PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf + +QUARTUS_ROOT ?= /tools/reconfig/intel/18.0 + +# Part, Family +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG + +# Executable Configuration +SYN_ARGS = --parallel --read_settings_files=on +FIT_ARGS = --part=$(DEVICE) --read_settings_files=on +ASM_ARGS = +STA_ARGS = --do_report_timing + +# Build targets +all: $(PROJECT).sta.rpt + +syn: $(PROJECT).syn.rpt + +fit: $(PROJECT).fit.rpt + +asm: $(PROJECT).asm.rpt + +sta: $(PROJECT).sta.rpt + +smart: smart.log + +# Target implementations +STAMP = echo done > + +$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) + quartus_syn $(PROJECT) $(SYN_ARGS) + $(STAMP) fit.chg + +$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt + quartus_fit $(PROJECT) $(FIT_ARGS) + $(STAMP) asm.chg + $(STAMP) sta.chg + +$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt + quartus_asm $(PROJECT) $(ASM_ARGS) + +$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt + quartus_sta $(PROJECT) $(STA_ARGS) + +smart.log: $(PROJECT_FILES) + quartus_sh --determine_smart_action $(PROJECT) > smart.log + +# Project initialization +$(PROJECT_FILES): + quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../" + +syn.chg: + $(STAMP) syn.chg + +fit.chg: + $(STAMP) fit.chg + +sta.chg: + $(STAMP) sta.chg + +asm.chg: + $(STAMP) asm.chg + +program: $(PROJECT).sof + quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" + +clean: + rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/rtl/VX_cache/quartus/project.sdc b/rtl/VX_cache/quartus/project.sdc new file mode 100755 index 00000000..16582e56 --- /dev/null +++ b/rtl/VX_cache/quartus/project.sdc @@ -0,0 +1 @@ +create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] diff --git a/rtl/VX_cache/quartus/project.tcl b/rtl/VX_cache/quartus/project.tcl new file mode 100644 index 00000000..afe69d48 --- /dev/null +++ b/rtl/VX_cache/quartus/project.tcl @@ -0,0 +1,41 @@ +load_package flow +package require cmdline + +set options { \ + { "project.arg" "" "Project name" } \ + { "family.arg" "" "Device family name" } \ + { "device.arg" "" "Device name" } \ + { "top.arg" "" "Top level module" } \ + { "sdc.arg" "" "Timing Design Constraints file" } \ + { "src.arg" "" "Verilog source file" } \ + { "inc.arg" "." "Include path" } \ +} + +array set opts [::cmdline::getoptions quartus(args) $options] + +project_new $opts(project) -overwrite + +set_global_assignment -name FAMILY $opts(family) +set_global_assignment -name DEVICE $opts(device) +set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) +set_global_assignment -name VERILOG_FILE $opts(src) +set_global_assignment -name SEARCH_PATH $opts(inc) +set_global_assignment -name SDC_FILE $opts(sdc) +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 + +proc make_all_pins_virtual {} { + execute_module -tool map + set name_ids [get_names -filter * -node_type pin] + foreach_in_collection name_id $name_ids { + set pin_name [get_name_info -info full_path $name_id] + post_message "Making VIRTUAL_PIN assignment to $pin_name" + set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON + } + export_assignments +} + +make_all_pins_virtual + +project_close \ No newline at end of file diff --git a/rtl/VX_csr_data.v b/rtl/VX_csr_data.v index 2a3c5641..6dc899a1 100644 --- a/rtl/VX_csr_data.v +++ b/rtl/VX_csr_data.v @@ -17,7 +17,6 @@ module VX_csr_data ( ); - // wire[`NT_M1:0][31:0] thread_ids; // wire[`NT_M1:0][31:0] warp_ids; diff --git a/rtl/VX_csr_pipe.v b/rtl/VX_csr_pipe.v index f5abfc57..e9194f53 100644 --- a/rtl/VX_csr_pipe.v +++ b/rtl/VX_csr_pipe.v @@ -7,94 +7,92 @@ module VX_csr_pipe ( VX_csr_req_inter VX_csr_req, VX_wb_inter VX_writeback, VX_csr_wb_inter VX_csr_wb, - output wire stall_gpr_csr - + output wire stall_gpr_csr ); - wire[`NT_M1:0] valid_s2; - wire[`NW_M1:0] warp_num_s2; - wire[4:0] rd_s2; - wire[1:0] wb_s2; - wire[4:0] alu_op_s2; - wire is_csr_s2; - wire[11:0] csr_address_s2; - wire[31:0] csr_read_data_s2; - wire[31:0] csr_updated_data_s2; + wire[`NT_M1:0] valid_s2; + wire[`NW_M1:0] warp_num_s2; + wire[4:0] rd_s2; + wire[1:0] wb_s2; + wire[4:0] alu_op_s2; + wire is_csr_s2; + wire[11:0] csr_address_s2; + wire[31:0] csr_read_data_s2; + wire[31:0] csr_updated_data_s2; - wire[31:0] csr_read_data_unqual; - wire[31:0] csr_read_data; + wire[31:0] csr_read_data_unqual; + wire[31:0] csr_read_data; - assign stall_gpr_csr = no_slot_csr && VX_csr_req.is_csr && |(VX_csr_req.valid); + assign stall_gpr_csr = no_slot_csr && VX_csr_req.is_csr && |(VX_csr_req.valid); - assign csr_read_data = (csr_address_s2 == VX_csr_req.csr_address) ? csr_updated_data_s2 : csr_read_data_unqual; + assign csr_read_data = (csr_address_s2 == VX_csr_req.csr_address) ? csr_updated_data_s2 : csr_read_data_unqual; - wire writeback = |VX_writeback.wb_valid; - VX_csr_data VX_csr_data( - .clk (clk), - .reset (reset), - .in_read_csr_address (VX_csr_req.csr_address), + wire writeback = |VX_writeback.wb_valid; + VX_csr_data VX_csr_data( + .clk (clk), + .reset (reset), + .in_read_csr_address (VX_csr_req.csr_address), - .in_write_valid (is_csr_s2), - .in_write_csr_data (csr_updated_data_s2), - .in_write_csr_address(csr_address_s2), + .in_write_valid (is_csr_s2), + .in_write_csr_data (csr_updated_data_s2), + .in_write_csr_address(csr_address_s2), - .out_read_csr_data (csr_read_data_unqual), + .out_read_csr_data (csr_read_data_unqual), - .in_writeback_valid (writeback) - ); + .in_writeback_valid (writeback) + ); - reg[31:0] csr_updated_data; - always @(*) begin - case(VX_csr_req.alu_op) - `CSR_ALU_RW: csr_updated_data = VX_csr_req.csr_mask; - `CSR_ALU_RS: csr_updated_data = csr_read_data | VX_csr_req.csr_mask; - `CSR_ALU_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - VX_csr_req.csr_mask); - default: csr_updated_data = 32'hdeadbeef; - endcase - end + reg[31:0] csr_updated_data; + always @(*) begin + case(VX_csr_req.alu_op) + `CSR_ALU_RW: csr_updated_data = VX_csr_req.csr_mask; + `CSR_ALU_RS: csr_updated_data = csr_read_data | VX_csr_req.csr_mask; + `CSR_ALU_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - VX_csr_req.csr_mask); + default: csr_updated_data = 32'hdeadbeef; + endcase + end - wire zero = 0; + wire zero = 0; - VX_generic_register #(.N(`NT + `NW_M1 + 1 + 5 + 2 + 5 + 12 + 64)) csr_reg_s2 ( - .clk (clk), - .reset(reset), - .stall(no_slot_csr), - .flush(zero), - .in ({VX_csr_req.valid, VX_csr_req.warp_num, VX_csr_req.rd, VX_csr_req.wb, VX_csr_req.is_csr, VX_csr_req.csr_address, csr_read_data , csr_updated_data }), - .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2}) - ); + VX_generic_register #(.N(`NT + `NW_M1 + 1 + 5 + 2 + 5 + 12 + 64)) csr_reg_s2 ( + .clk (clk), + .reset(reset), + .stall(no_slot_csr), + .flush(zero), + .in ({VX_csr_req.valid, VX_csr_req.warp_num, VX_csr_req.rd, VX_csr_req.wb, VX_csr_req.is_csr, VX_csr_req.csr_address, csr_read_data , csr_updated_data }), + .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2}) + ); - wire[`NT_M1:0][31:0] final_csr_data; + wire[`NT_M1:0][31:0] final_csr_data; - wire[`NT_M1:0][31:0] thread_ids; - wire[`NT_M1:0][31:0] warp_ids; - wire[`NT_M1:0][31:0] csr_vec_read_data_s2; + wire[`NT_M1:0][31:0] thread_ids; + wire[`NT_M1:0][31:0] warp_ids; + wire[`NT_M1:0][31:0] csr_vec_read_data_s2; - genvar cur_t; - for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin - assign thread_ids[cur_t] = cur_t; - end + genvar cur_t; + for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin + assign thread_ids[cur_t] = cur_t; + end - genvar cur_tw; - for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin - assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, warp_num_s2}; - end + genvar cur_tw; + for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin + assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, warp_num_s2}; + end - genvar cur_v; - for (cur_v = 0; cur_v < `NT; cur_v = cur_v + 1) begin - assign csr_vec_read_data_s2[cur_v] = csr_read_data_s2; - end + genvar cur_v; + for (cur_v = 0; cur_v < `NT; cur_v = cur_v + 1) begin + assign csr_vec_read_data_s2[cur_v] = csr_read_data_s2; + end - wire thread_select = csr_address_s2 == 12'h20; - wire warp_select = csr_address_s2 == 12'h21; - - assign final_csr_data = thread_select ? thread_ids : - warp_select ? warp_ids : - csr_vec_read_data_s2; + wire thread_select = csr_address_s2 == 12'h20; + wire warp_select = csr_address_s2 == 12'h21; + assign final_csr_data = thread_select ? thread_ids : + warp_select ? warp_ids : + csr_vec_read_data_s2; assign VX_csr_wb.valid = valid_s2; diff --git a/rtl/VX_define.v b/rtl/VX_define.v index c92ce429..45efae34 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -1,9 +1,7 @@ +`ifndef VX_DEFINE +`define VX_DEFINE + `include "./VX_define_synth.v" -// `include "./VX_cache/VX_cache_config.v" - -// `ifndef VX_DEFINE - -// `define VX_DEFINE `define NT_M1 (`NT-1) @@ -91,8 +89,6 @@ `define REM 5'd22 `define REMU 5'd23 - - // WRITEBACK `define WB_ALU 2'h1 `define WB_MEM 2'h2 @@ -128,7 +124,6 @@ (x <= 1024) ? 10 : \ -199 - // `define PARAM // oooooo @@ -244,8 +239,6 @@ `define DCACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`DCACHE_BLOCK-1)) `define ICACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`ICACHE_BLOCK-1)) - - /////// //`define SHARED_MEMORY_SIZE 4096 @@ -271,6 +264,4 @@ `define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1) `define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1) - - -// `endif +`endif diff --git a/rtl/VX_define_synth.v b/rtl/VX_define_synth.v index dcb3a609..ac029146 100644 --- a/rtl/VX_define_synth.v +++ b/rtl/VX_define_synth.v @@ -1,9 +1,7 @@ - -// `ifndef VX_DEFINE_SYNTH - -// `define VX_DEFINE_SYNTH +`ifndef VX_DEFINE_SYNTH +`define VX_DEFINE_SYNTH `define NT 2 `define NW 8 -// `endif +`endif diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 93f26e62..d029a123 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -1,4 +1,3 @@ - `include "VX_define.v" module VX_dmem_controller ( @@ -16,23 +15,19 @@ module VX_dmem_controller ( VX_gpu_dcache_res_inter VX_dcache_rsp ); - wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}}; - wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read; wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write; - wire[`NT_M1:0][31:0] cache_driver_out_data; wire[`NT_M1:0][31:0] sm_driver_out_data; wire[`NT_M1:0] cache_driver_out_valid; // Not used for now wire sm_delay; - // I_Cache Signals wire[31:0] icache_instruction_out; @@ -169,7 +164,7 @@ module VX_dmem_controller ( // ); -VX_d_cache#( +VX_d_cache #( .CACHE_SIZE (`ICACHE_SIZE), .CACHE_WAYS (`ICACHE_WAYS), .CACHE_BLOCK (`ICACHE_BLOCK), diff --git a/rtl/VX_execute_unit.v b/rtl/VX_execute_unit.v index f262e0b4..60c7441a 100644 --- a/rtl/VX_execute_unit.v +++ b/rtl/VX_execute_unit.v @@ -18,161 +18,159 @@ module VX_execute_unit ( output wire out_delay ); + wire[`NT_M1:0][31:0] in_a_reg_data; + wire[`NT_M1:0][31:0] in_b_reg_data; + wire[4:0] in_alu_op; + wire in_rs2_src; + wire[31:0] in_itype_immed; + wire[2:0] in_branch_type; + wire[19:0] in_upper_immed; + wire in_jal; + wire[31:0] in_jal_offset; + wire[31:0] in_curr_PC; + + assign in_a_reg_data = VX_exec_unit_req.a_reg_data; + assign in_b_reg_data = VX_exec_unit_req.b_reg_data; + assign in_alu_op = VX_exec_unit_req.alu_op; + assign in_rs2_src = VX_exec_unit_req.rs2_src; + assign in_itype_immed = VX_exec_unit_req.itype_immed; + assign in_branch_type = VX_exec_unit_req.branch_type; + assign in_upper_immed = VX_exec_unit_req.upper_immed; + assign in_jal = VX_exec_unit_req.jal; + assign in_jal_offset = VX_exec_unit_req.jal_offset; + assign in_curr_PC = VX_exec_unit_req.curr_PC; - wire[`NT_M1:0][31:0] in_a_reg_data; - wire[`NT_M1:0][31:0] in_b_reg_data; - wire[4:0] in_alu_op; - wire in_rs2_src; - wire[31:0] in_itype_immed; - wire[2:0] in_branch_type; - wire[19:0] in_upper_immed; - wire in_jal; - wire[31:0] in_jal_offset; - wire[31:0] in_curr_PC; - - assign in_a_reg_data = VX_exec_unit_req.a_reg_data; - assign in_b_reg_data = VX_exec_unit_req.b_reg_data; - assign in_alu_op = VX_exec_unit_req.alu_op; - assign in_rs2_src = VX_exec_unit_req.rs2_src; - assign in_itype_immed = VX_exec_unit_req.itype_immed; - assign in_branch_type = VX_exec_unit_req.branch_type; - assign in_upper_immed = VX_exec_unit_req.upper_immed; - assign in_jal = VX_exec_unit_req.jal; - assign in_jal_offset = VX_exec_unit_req.jal_offset; - assign in_curr_PC = VX_exec_unit_req.curr_PC; - - - wire[`NT_M1:0][31:0] alu_result; - wire[`NT_M1:0] alu_stall; - genvar index_out_reg; - generate - for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) begin : alu_defs - VX_alu vx_alu( - .clk(clk), - .reset(reset), - // .in_reg_data (in_reg_data[1:0]), - .in_1 (in_a_reg_data[index_out_reg]), - .in_2 (in_b_reg_data[index_out_reg]), - .in_rs2_src (in_rs2_src), - .in_itype_immed(in_itype_immed), - .in_upper_immed(in_upper_immed), - .in_alu_op (in_alu_op), - .in_curr_PC (in_curr_PC), - .out_alu_result(alu_result[index_out_reg]), - .out_alu_stall(alu_stall[index_out_reg]) - ); - end - endgenerate - - wire internal_stall; - assign internal_stall = |alu_stall; - - assign out_delay = no_slot_exec || internal_stall; - - - wire [$clog2(`NT)-1:0] jal_branch_use_index; - wire jal_branch_found_valid; - VX_generic_priority_encoder #(.N(`NT)) choose_alu_result( - .valids(VX_exec_unit_req.valid), - .index (jal_branch_use_index), - .found (jal_branch_found_valid) + wire[`NT_M1:0][31:0] alu_result; + wire[`NT_M1:0] alu_stall; + genvar index_out_reg; + generate + for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) begin : alu_defs + VX_alu vx_alu( + .clk(clk), + .reset(reset), + // .in_reg_data (in_reg_data[1:0]), + .in_1 (in_a_reg_data[index_out_reg]), + .in_2 (in_b_reg_data[index_out_reg]), + .in_rs2_src (in_rs2_src), + .in_itype_immed(in_itype_immed), + .in_upper_immed(in_upper_immed), + .in_alu_op (in_alu_op), + .in_curr_PC (in_curr_PC), + .out_alu_result(alu_result[index_out_reg]), + .out_alu_stall(alu_stall[index_out_reg]) ); - - wire[31:0] branch_use_alu_result = alu_result[jal_branch_use_index]; - - reg temp_branch_dir; - always @(*) - begin - case(VX_exec_unit_req.branch_type) - `BEQ: temp_branch_dir = (branch_use_alu_result == 0) ? `TAKEN : `NOT_TAKEN; - `BNE: temp_branch_dir = (branch_use_alu_result == 0) ? `NOT_TAKEN : `TAKEN; - `BLT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; - `BGT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; - `BLTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; - `BGTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; - `NO_BRANCH: temp_branch_dir = `NOT_TAKEN; - default: temp_branch_dir = `NOT_TAKEN; - endcase // in_branch_type end + endgenerate + + wire internal_stall; + assign internal_stall = |alu_stall; + + assign out_delay = no_slot_exec || internal_stall; - wire[`NT_M1:0][31:0] duplicate_PC_data; - genvar i; - generate - for (i = 0; i < `NT; i=i+1) begin : pc_data_setup - assign duplicate_PC_data[i] = VX_exec_unit_req.PC_next; - end - endgenerate + wire [$clog2(`NT)-1:0] jal_branch_use_index; + wire jal_branch_found_valid; + VX_generic_priority_encoder #(.N(`NT)) choose_alu_result( + .valids(VX_exec_unit_req.valid), + .index (jal_branch_use_index), + .found (jal_branch_found_valid) + ); + + wire[31:0] branch_use_alu_result = alu_result[jal_branch_use_index]; + + reg temp_branch_dir; + always @(*) + begin + case(VX_exec_unit_req.branch_type) + `BEQ: temp_branch_dir = (branch_use_alu_result == 0) ? `TAKEN : `NOT_TAKEN; + `BNE: temp_branch_dir = (branch_use_alu_result == 0) ? `NOT_TAKEN : `TAKEN; + `BLT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; + `BGT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; + `BLTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; + `BGTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; + `NO_BRANCH: temp_branch_dir = `NOT_TAKEN; + default: temp_branch_dir = `NOT_TAKEN; + endcase // in_branch_type + end - // VX_inst_exec_wb_inter VX_inst_exec_wb_temp(); - // JAL Response - VX_jal_response_inter VX_jal_rsp_temp(); - // Branch Response - VX_branch_response_inter VX_branch_rsp_temp(); - - // Actual Writeback - assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd; - assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb; - assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid & {`NT{!internal_stall}}; - assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num; - assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result; - - assign VX_inst_exec_wb.exec_wb_pc = in_curr_PC; - // Jal rsp - assign VX_jal_rsp_temp.jal = in_jal; - assign VX_jal_rsp_temp.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); - assign VX_jal_rsp_temp.jal_warp_num = VX_exec_unit_req.warp_num; - - // Branch rsp - assign VX_branch_rsp_temp.valid_branch = (VX_exec_unit_req.branch_type != `NO_BRANCH) && (|VX_exec_unit_req.valid); - assign VX_branch_rsp_temp.branch_dir = temp_branch_dir; - assign VX_branch_rsp_temp.branch_warp_num = VX_exec_unit_req.warp_num; - assign VX_branch_rsp_temp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset + wire[`NT_M1:0][31:0] duplicate_PC_data; + genvar i; + generate + for (i = 0; i < `NT; i=i+1) begin : pc_data_setup + assign duplicate_PC_data[i] = VX_exec_unit_req.PC_next; + end + endgenerate - wire zero = 0; + // VX_inst_exec_wb_inter VX_inst_exec_wb_temp(); + // JAL Response + VX_jal_response_inter VX_jal_rsp_temp(); + // Branch Response + VX_branch_response_inter VX_branch_rsp_temp(); - // VX_generic_register #(.N(174)) exec_reg( - // .clk (clk), - // .reset(reset), - // .stall(zero), - // .flush(zero), - // .in ({VX_inst_exec_wb_temp.rd, VX_inst_exec_wb_temp.wb, VX_inst_exec_wb_temp.wb_valid, VX_inst_exec_wb_temp.wb_warp_num, VX_inst_exec_wb_temp.alu_result, VX_inst_exec_wb_temp.exec_wb_pc}), - // .out ({VX_inst_exec_wb.rd , VX_inst_exec_wb.wb , VX_inst_exec_wb.wb_valid , VX_inst_exec_wb.wb_warp_num , VX_inst_exec_wb.alu_result , VX_inst_exec_wb.exec_wb_pc }) - // ); + // Actual Writeback + assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd; + assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb; + assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid & {`NT{!internal_stall}}; + assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num; + assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result; - VX_generic_register #(.N(33 + `NW_M1 + 1)) jal_reg( - .clk (clk), - .reset(reset), - .stall(zero), - .flush(zero), - .in ({VX_jal_rsp_temp.jal, VX_jal_rsp_temp.jal_dest, VX_jal_rsp_temp.jal_warp_num}), - .out ({VX_jal_rsp.jal , VX_jal_rsp.jal_dest , VX_jal_rsp.jal_warp_num}) - ); + assign VX_inst_exec_wb.exec_wb_pc = in_curr_PC; + // Jal rsp + assign VX_jal_rsp_temp.jal = in_jal; + assign VX_jal_rsp_temp.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); + assign VX_jal_rsp_temp.jal_warp_num = VX_exec_unit_req.warp_num; - VX_generic_register #(.N(34 + `NW_M1 + 1)) branch_reg( - .clk (clk), - .reset(reset), - .stall(zero), - .flush(zero), - .in ({VX_branch_rsp_temp.valid_branch, VX_branch_rsp_temp.branch_dir, VX_branch_rsp_temp.branch_warp_num, VX_branch_rsp_temp.branch_dest}), - .out ({VX_branch_rsp.valid_branch , VX_branch_rsp.branch_dir , VX_branch_rsp.branch_warp_num , VX_branch_rsp.branch_dest }) - ); - - // always @(*) begin - // case(in_alu_op) - // `CSR_ALU_RW: out_csr_result = in_csr_mask; - // `CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask; - // `CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask); - // default: out_csr_result = 32'hdeadbeef; - // endcase - - // end + // Branch rsp + assign VX_branch_rsp_temp.valid_branch = (VX_exec_unit_req.branch_type != `NO_BRANCH) && (|VX_exec_unit_req.valid); + assign VX_branch_rsp_temp.branch_dir = temp_branch_dir; + assign VX_branch_rsp_temp.branch_warp_num = VX_exec_unit_req.warp_num; + assign VX_branch_rsp_temp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset - // assign out_is_csr = VX_exec_unit_req.is_csr; - // assign out_csr_address = VX_exec_unit_req.csr_address; + wire zero = 0; + + // VX_generic_register #(.N(174)) exec_reg( + // .clk (clk), + // .reset(reset), + // .stall(zero), + // .flush(zero), + // .in ({VX_inst_exec_wb_temp.rd, VX_inst_exec_wb_temp.wb, VX_inst_exec_wb_temp.wb_valid, VX_inst_exec_wb_temp.wb_warp_num, VX_inst_exec_wb_temp.alu_result, VX_inst_exec_wb_temp.exec_wb_pc}), + // .out ({VX_inst_exec_wb.rd , VX_inst_exec_wb.wb , VX_inst_exec_wb.wb_valid , VX_inst_exec_wb.wb_warp_num , VX_inst_exec_wb.alu_result , VX_inst_exec_wb.exec_wb_pc }) + // ); + + VX_generic_register #(.N(33 + `NW_M1 + 1)) jal_reg( + .clk (clk), + .reset(reset), + .stall(zero), + .flush(zero), + .in ({VX_jal_rsp_temp.jal, VX_jal_rsp_temp.jal_dest, VX_jal_rsp_temp.jal_warp_num}), + .out ({VX_jal_rsp.jal , VX_jal_rsp.jal_dest , VX_jal_rsp.jal_warp_num}) + ); + + VX_generic_register #(.N(34 + `NW_M1 + 1)) branch_reg( + .clk (clk), + .reset(reset), + .stall(zero), + .flush(zero), + .in ({VX_branch_rsp_temp.valid_branch, VX_branch_rsp_temp.branch_dir, VX_branch_rsp_temp.branch_warp_num, VX_branch_rsp_temp.branch_dest}), + .out ({VX_branch_rsp.valid_branch , VX_branch_rsp.branch_dir , VX_branch_rsp.branch_warp_num , VX_branch_rsp.branch_dest }) + ); + + // always @(*) begin + // case(in_alu_op) + // `CSR_ALU_RW: out_csr_result = in_csr_mask; + // `CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask; + // `CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask); + // default: out_csr_result = 32'hdeadbeef; + // endcase + + // end + + + // assign out_is_csr = VX_exec_unit_req.is_csr; + // assign out_csr_address = VX_exec_unit_req.csr_address; endmodule : VX_execute_unit \ No newline at end of file diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index 35278807..00330676 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -1,4 +1,3 @@ - `include "VX_define.v" module VX_fetch ( diff --git a/rtl/VX_generic_priority_encoder.v b/rtl/VX_generic_priority_encoder.v index b1fa2966..80df3d43 100644 --- a/rtl/VX_generic_priority_encoder.v +++ b/rtl/VX_generic_priority_encoder.v @@ -1,3 +1,6 @@ +`ifndef VX_GENERIC_PRIORITY_ENCODER +`define VX_GENERIC_PRIORITY_ENCODER + `include "VX_define.v" module VX_generic_priority_encoder @@ -24,4 +27,6 @@ module VX_generic_priority_encoder end end end -endmodule \ No newline at end of file +endmodule + +`endif \ No newline at end of file diff --git a/rtl/VX_generic_queue.v b/rtl/VX_generic_queue.v index f388c6d3..dd312dbb 100644 --- a/rtl/VX_generic_queue.v +++ b/rtl/VX_generic_queue.v @@ -1,5 +1,4 @@ - module VX_generic_queue #( parameter DATAW = 4, @@ -17,7 +16,6 @@ module VX_generic_queue output wire full ); - reg[DATAW-1:0] data[SIZE-1:0]; reg[$clog2(SIZE)-1:0] head; reg[$clog2(SIZE)-1:0] tail; @@ -31,7 +29,7 @@ module VX_generic_queue head <= 0; tail <= 0; for (i = 0; i < SIZE; i=i+1) begin - data[i] <= {DATAW{1'0}}; + data[i] <= 0; end end else begin if (push && !full) begin diff --git a/rtl/VX_generic_register.v b/rtl/VX_generic_register.v index 04de60ac..a26c09b3 100644 --- a/rtl/VX_generic_register.v +++ b/rtl/VX_generic_register.v @@ -10,11 +10,8 @@ module VX_generic_register output wire[(N-1):0] out ); - reg[(N-1):0] value; - - always @(posedge clk or posedge reset) begin if (reset) begin value <= 0; @@ -25,7 +22,6 @@ module VX_generic_register end end - assign out = value; endmodule \ No newline at end of file diff --git a/rtl/VX_generic_stack.v b/rtl/VX_generic_stack.v index cdac974f..1ecf6409 100644 --- a/rtl/VX_generic_stack.v +++ b/rtl/VX_generic_stack.v @@ -1,3 +1,4 @@ + module VX_generic_stack #( parameter WIDTH = 40, diff --git a/rtl/VX_gpr_stage.v b/rtl/VX_gpr_stage.v index ab027e19..e9ffc48d 100644 --- a/rtl/VX_gpr_stage.v +++ b/rtl/VX_gpr_stage.v @@ -1,4 +1,3 @@ - `include "VX_define.v" module VX_gpr_stage ( diff --git a/rtl/VX_lsu.v b/rtl/VX_lsu.v index 86694851..c177480e 100644 --- a/rtl/VX_lsu.v +++ b/rtl/VX_lsu.v @@ -1,7 +1,5 @@ - `include "VX_define.v" - module VX_lsu ( input wire clk, input wire reset, @@ -16,9 +14,6 @@ module VX_lsu ( output wire out_delay ); - - - // Generate Addresses wire[`NT_M1:0][31:0] address; VX_lsu_addr_gen VX_lsu_addr_gen @@ -28,7 +23,6 @@ module VX_lsu ( .address (address) ); - wire[`NT_M1:0][31:0] use_address; wire[`NT_M1:0][31:0] use_store_data; wire[`NT_M1:0] use_valid; @@ -37,9 +31,7 @@ module VX_lsu ( wire[4:0] use_rd; wire[`NW_M1:0] use_warp_num; wire[1:0] use_wb; - wire[31:0] use_pc; - - + wire[31:0] use_pc; wire zero = 0; @@ -66,8 +58,6 @@ module VX_lsu ( // Cache can't accept request assign out_delay = VX_dcache_rsp.delay_req; - - // Core Response assign VX_mem_wb.rd = VX_dcache_rsp.core_wb_req_rd; assign VX_mem_wb.wb = VX_dcache_rsp.core_wb_req_wb; @@ -79,21 +69,19 @@ module VX_lsu ( // Core can't accept response assign VX_dcache_req.core_no_wb_slot = no_slot_mem; + // integer curr_t; + // always @(negedge clk) begin + // for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1) + // if ((VX_dcache_req.out_cache_driver_in_valid[curr_t]) && !out_delay) begin + // if (VX_dcache_req.out_cache_driver_in_mem_read != `NO_MEM_READ) begin + // $display("Reading addr: %x val: %x", address[0], VX_mem_wb.loaded_data[0]); + // end - - // integer curr_t; - // always @(negedge clk) begin - // for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1) - // if ((VX_dcache_req.out_cache_driver_in_valid[curr_t]) && !out_delay) begin - // if (VX_dcache_req.out_cache_driver_in_mem_read != `NO_MEM_READ) begin - // $display("Reading addr: %x val: %x", address[0], VX_mem_wb.loaded_data[0]); - // end - - // if (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) begin - // $display("Writing addr: %x val: %x", address[0], VX_dcache_req.out_cache_driver_in_data[0]); - // end - // end - // end + // if (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) begin + // $display("Writing addr: %x val: %x", address[0], VX_dcache_req.out_cache_driver_in_data[0]); + // end + // end + // end // wire zero_temp = 0; // VX_generic_register #(.N(142)) register_wb_data diff --git a/rtl/VX_scheduler.v b/rtl/VX_scheduler.v index e7308f9c..c6247ab8 100644 --- a/rtl/VX_scheduler.v +++ b/rtl/VX_scheduler.v @@ -1,5 +1,3 @@ - - `include "VX_define.v" module VX_scheduler ( diff --git a/rtl/VX_writeback.v b/rtl/VX_writeback.v index 5be10a16..ee65dca8 100644 --- a/rtl/VX_writeback.v +++ b/rtl/VX_writeback.v @@ -1,90 +1,88 @@ - `include "VX_define.v" - module VX_writeback ( - input wire clk, - input wire reset, - // Mem WB info - VX_inst_mem_wb_inter VX_mem_wb, - // EXEC Unit WB info - VX_inst_exec_wb_inter VX_inst_exec_wb, - // CSR Unit WB info - VX_csr_wb_inter VX_csr_wb, + input wire clk, + input wire reset, + // Mem WB info + VX_inst_mem_wb_inter VX_mem_wb, + // EXEC Unit WB info + VX_inst_exec_wb_inter VX_inst_exec_wb, + // CSR Unit WB info + VX_csr_wb_inter VX_csr_wb, - // Actual WB to GPR - VX_wb_inter VX_writeback_inter, - output wire no_slot_mem, - output wire no_slot_exec, - output wire no_slot_csr - ); + // Actual WB to GPR + VX_wb_inter VX_writeback_inter, + output wire no_slot_mem, + output wire no_slot_exec, + output wire no_slot_csr +); - VX_wb_inter VX_writeback_tempp(); + VX_wb_inter VX_writeback_tempp(); - wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid); - wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid); - wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid); + wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid); + wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid); + wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid); - assign no_slot_mem = mem_wb && (exec_wb || csr_wb); - assign no_slot_csr = csr_wb && (exec_wb); - assign no_slot_exec = 0; + assign no_slot_mem = mem_wb && (exec_wb || csr_wb); + assign no_slot_csr = csr_wb && (exec_wb); + assign no_slot_exec = 0; - assign VX_writeback_tempp.write_data = exec_wb ? VX_inst_exec_wb.alu_result : - csr_wb ? VX_csr_wb.csr_result : - mem_wb ? VX_mem_wb.loaded_data : - 0; + assign VX_writeback_tempp.write_data = exec_wb ? VX_inst_exec_wb.alu_result : + csr_wb ? VX_csr_wb.csr_result : + mem_wb ? VX_mem_wb.loaded_data : + 0; - assign VX_writeback_tempp.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid : - csr_wb ? VX_csr_wb.valid : - mem_wb ? VX_mem_wb.wb_valid : - 0; + assign VX_writeback_tempp.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid : + csr_wb ? VX_csr_wb.valid : + mem_wb ? VX_mem_wb.wb_valid : + 0; - assign VX_writeback_tempp.rd = exec_wb ? VX_inst_exec_wb.rd : - csr_wb ? VX_csr_wb.rd : - mem_wb ? VX_mem_wb.rd : - 0; + assign VX_writeback_tempp.rd = exec_wb ? VX_inst_exec_wb.rd : + csr_wb ? VX_csr_wb.rd : + mem_wb ? VX_mem_wb.rd : + 0; - assign VX_writeback_tempp.wb = exec_wb ? VX_inst_exec_wb.wb : - csr_wb ? VX_csr_wb.wb : - mem_wb ? VX_mem_wb.wb : - 0; + assign VX_writeback_tempp.wb = exec_wb ? VX_inst_exec_wb.wb : + csr_wb ? VX_csr_wb.wb : + mem_wb ? VX_mem_wb.wb : + 0; - assign VX_writeback_tempp.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num : - csr_wb ? VX_csr_wb.warp_num : - mem_wb ? VX_mem_wb.wb_warp_num : - 0; + assign VX_writeback_tempp.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num : + csr_wb ? VX_csr_wb.warp_num : + mem_wb ? VX_mem_wb.wb_warp_num : + 0; - assign VX_writeback_tempp.wb_pc = exec_wb ? VX_inst_exec_wb.exec_wb_pc : - csr_wb ? 32'hdeadbeef : - mem_wb ? VX_mem_wb.mem_wb_pc : - 32'hdeadbeef; + assign VX_writeback_tempp.wb_pc = exec_wb ? VX_inst_exec_wb.exec_wb_pc : + csr_wb ? 32'hdeadbeef : + mem_wb ? VX_mem_wb.mem_wb_pc : + 32'hdeadbeef; - wire zero = 0; + wire zero = 0; - wire[`NT-1:0][31:0] use_wb_data; + wire[`NT-1:0][31:0] use_wb_data; - VX_generic_register #(.N(39 + `NW_M1 + 1 + `NT*33)) wb_register( - .clk (clk), - .reset(reset), - .stall(zero), - .flush(zero), - .in ({VX_writeback_tempp.write_data, VX_writeback_tempp.wb_valid, VX_writeback_tempp.rd, VX_writeback_tempp.wb, VX_writeback_tempp.wb_warp_num, VX_writeback_tempp.wb_pc}), - .out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc}) - ); + VX_generic_register #(.N(39 + `NW_M1 + 1 + `NT*33)) wb_register( + .clk (clk), + .reset(reset), + .stall(zero), + .flush(zero), + .in ({VX_writeback_tempp.write_data, VX_writeback_tempp.wb_valid, VX_writeback_tempp.rd, VX_writeback_tempp.wb, VX_writeback_tempp.wb_warp_num, VX_writeback_tempp.wb_pc}), + .out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc}) + ); - reg[31:0] last_data_wb; - always @(posedge clk) begin - if ((|VX_writeback_inter.wb_valid) && (VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd == 28)) begin - last_data_wb <= use_wb_data[0]; - end + reg[31:0] last_data_wb; + always @(posedge clk) begin + if ((|VX_writeback_inter.wb_valid) && (VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd == 28)) begin + last_data_wb <= use_wb_data[0]; end + end - assign VX_writeback_inter.write_data = use_wb_data; + assign VX_writeback_inter.write_data = use_wb_data; endmodule : VX_writeback diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 5a420873..78ffa535 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -1,6 +1,5 @@ - -// `include "VX_define.v" -`include "./VX_cache/VX_cache_config.v" +`include "VX_define.v" +`include "VX_cache_config.v" module Vortex /*#( @@ -49,60 +48,56 @@ module Vortex ); -reg[31:0] icache_banks = `ICACHE_BANKS; -reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK; -reg[31:0] number_threads = `NT; -reg[31:0] number_warps = `NW; + reg[31:0] icache_banks = `ICACHE_BANKS; + reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK; + reg[31:0] number_threads = `NT; + reg[31:0] number_warps = `NW; -always @(posedge clk) begin - icache_banks <= icache_banks; - icache_num_words_per_block <= icache_num_words_per_block; + always @(posedge clk) begin + icache_banks <= icache_banks; + icache_num_words_per_block <= icache_num_words_per_block; - number_threads <= number_threads; - number_warps <= number_warps; -end - -wire memory_delay; -wire exec_delay; -wire gpr_stage_delay; -wire schedule_delay; - - -// Dcache Interface -VX_gpu_dcache_res_inter VX_dcache_rsp(); -VX_gpu_dcache_req_inter VX_dcache_req(); - -VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req(); -VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res(); - - -assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp; -assign VX_gpu_dcache_dram_res.dram_fill_rsp_addr = dram_fill_rsp_addr; - -assign dram_req = VX_gpu_dcache_dram_req.dram_req; -assign dram_req_write = VX_gpu_dcache_dram_req.dram_req_write; -assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read; -assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr; -assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size; -assign dram_expected_lat = `SIMULATED_DRAM_LATENCY_CYCLES; -assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept; - -genvar wordy; -generate - for (wordy = 0; wordy < `BANK_LINE_SIZE_WORDS; wordy=wordy+1) begin - assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy]; - assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy]; + number_threads <= number_threads; + number_warps <= number_warps; end -endgenerate + + wire memory_delay; + wire exec_delay; + wire gpr_stage_delay; + wire schedule_delay; + // Dcache Interface + VX_gpu_dcache_res_inter VX_dcache_rsp(); + VX_gpu_dcache_req_inter VX_dcache_req(); -wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000); -wire[31:0] temp_io_data = VX_dcache_req.core_req_valid[0]; -assign io_valid = temp_io_valid; -assign io_data = temp_io_data; + VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req(); + VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res(); + assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp; + assign VX_gpu_dcache_dram_res.dram_fill_rsp_addr = dram_fill_rsp_addr; + + assign dram_req = VX_gpu_dcache_dram_req.dram_req; + assign dram_req_write = VX_gpu_dcache_dram_req.dram_req_write; + assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read; + assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr; + assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size; + assign dram_expected_lat = `SIMULATED_DRAM_LATENCY_CYCLES; + assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept; + + genvar wordy; + generate + for (wordy = 0; wordy < `BANK_LINE_SIZE_WORDS; wordy=wordy+1) begin + assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy]; + assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy]; + end + endgenerate + + wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000); + wire[31:0] temp_io_data = VX_dcache_req.core_req_valid[0]; + assign io_valid = temp_io_valid; + assign io_data = temp_io_data; VX_icache_response_inter icache_response_fe(); @@ -114,8 +109,6 @@ assign io_data = temp_io_data; //assign icache_response_fe.instruction = icache_response_instruction; assign icache_request_pc_address = icache_request_fe.pc_address; - - assign o_m_valid_i = VX_dram_req_rsp_icache.o_m_valid; assign o_m_read_addr_i = VX_dram_req_rsp_icache.o_m_read_addr; assign o_m_evict_addr_i = VX_dram_req_rsp_icache.o_m_evict_addr; @@ -132,11 +125,8 @@ for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin end end - ///////////////////////////////////////////////////////////////////////// - - // Front-end to Back-end VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM @@ -204,6 +194,7 @@ VX_dmem_controller VX_dmem_controller( .VX_dcache_req (VX_dcache_req), .VX_dcache_rsp (VX_dcache_rsp) ); + // VX_csr_handler vx_csr_handler( // .clk (clk), // .in_decode_csr_address(decode_csr_address), @@ -213,9 +204,6 @@ VX_dmem_controller VX_dmem_controller( // .out_decode_csr_data (csr_decode_csr_data) // ); - - - endmodule // Vortex diff --git a/rtl/byte_enabled_simple_dual_port_ram.v b/rtl/byte_enabled_simple_dual_port_ram.v index bc5f82f1..73b923f4 100644 --- a/rtl/byte_enabled_simple_dual_port_ram.v +++ b/rtl/byte_enabled_simple_dual_port_ram.v @@ -1,7 +1,6 @@ `include "VX_define.v" - module byte_enabled_simple_dual_port_ram ( input we, clk, diff --git a/rtl/cache/VX_Cache_Bank.v b/rtl/cache/VX_Cache_Bank.v index b3701b68..62d53f3a 100644 --- a/rtl/cache/VX_Cache_Bank.v +++ b/rtl/cache/VX_Cache_Bank.v @@ -3,8 +3,6 @@ // Also make sure all possible output states are transmitted back to the bank correctly `include "VX_define.v" -// `include "VX_cache_data.v" - module VX_Cache_Bank #( diff --git a/rtl/cache/VX_cache_data.v b/rtl/cache/VX_cache_data.v index b4aac41e..b9c523c1 100644 --- a/rtl/cache/VX_cache_data.v +++ b/rtl/cache/VX_cache_data.v @@ -1,5 +1,3 @@ - - `include "VX_define.v" module VX_cache_data diff --git a/rtl/cache/VX_cache_data_per_index.v b/rtl/cache/VX_cache_data_per_index.v index 4fffd329..6d1dc89a 100644 --- a/rtl/cache/VX_cache_data_per_index.v +++ b/rtl/cache/VX_cache_data_per_index.v @@ -1,5 +1,3 @@ - - `include "VX_define.v" module VX_cache_data_per_index diff --git a/rtl/cache/VX_d_cache.v b/rtl/cache/VX_d_cache.v index ccb266a8..cce71c98 100644 --- a/rtl/cache/VX_d_cache.v +++ b/rtl/cache/VX_d_cache.v @@ -9,9 +9,10 @@ // - Send in a response from memory of what the data is from the test bench `include "VX_define.v" +//`include "VX_Cache_Bank.v" +//`include "VX_cache_bank_valid.v" //`include "VX_priority_encoder.v" -// `include "VX_Cache_Bank.v" -//`include "cache_set.v" +//`include "VX_priority_encoder_w_mask.v" module VX_d_cache #( diff --git a/rtl/cache/VX_d_cache_encapsulate.v b/rtl/cache/VX_d_cache_encapsulate.v index ca488152..b7560436 100644 --- a/rtl/cache/VX_d_cache_encapsulate.v +++ b/rtl/cache/VX_d_cache_encapsulate.v @@ -1,4 +1,3 @@ - `include "VX_define.v" `define NUM_WORDS_PER_BLOCK 4 diff --git a/rtl/cache/quartus/Makefile b/rtl/cache/quartus/Makefile new file mode 100755 index 00000000..49d0d173 --- /dev/null +++ b/rtl/cache/quartus/Makefile @@ -0,0 +1,70 @@ +PROJECT = VX_d_cache +TOP_LEVEL_ENTITY = VX_d_cache +SRC_FILE = ../VX_d_cache.v +PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf + +# Part, Family +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG + +# Executable Configuration +SYN_ARGS = --parallel --read_settings_files=on +FIT_ARGS = --part=$(DEVICE) --read_settings_files=on +ASM_ARGS = +STA_ARGS = --do_report_timing + +# Build targets +all: $(PROJECT).sta.rpt + +syn: $(PROJECT).syn.rpt + +fit: $(PROJECT).fit.rpt + +asm: $(PROJECT).asm.rpt + +sta: $(PROJECT).sta.rpt + +smart: smart.log + +# Target implementations +STAMP = echo done > + +$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) + quartus_syn $(PROJECT) $(SYN_ARGS) + $(STAMP) fit.chg + +$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt + quartus_fit $(PROJECT) $(FIT_ARGS) + $(STAMP) asm.chg + $(STAMP) sta.chg + +$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt + quartus_asm $(PROJECT) $(ASM_ARGS) + +$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt + quartus_sta $(PROJECT) $(STA_ARGS) + +smart.log: $(PROJECT_FILES) + quartus_sh --determine_smart_action $(PROJECT) > smart.log + +# Project initialization +$(PROJECT_FILES): + quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../" + +syn.chg: + $(STAMP) syn.chg + +fit.chg: + $(STAMP) fit.chg + +sta.chg: + $(STAMP) sta.chg + +asm.chg: + $(STAMP) asm.chg + +program: $(PROJECT).sof + quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" + +clean: + rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/rtl/cache/quartus/project.sdc b/rtl/cache/quartus/project.sdc new file mode 100755 index 00000000..16582e56 --- /dev/null +++ b/rtl/cache/quartus/project.sdc @@ -0,0 +1 @@ +create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] diff --git a/rtl/cache/quartus/project.tcl b/rtl/cache/quartus/project.tcl new file mode 100644 index 00000000..afe69d48 --- /dev/null +++ b/rtl/cache/quartus/project.tcl @@ -0,0 +1,41 @@ +load_package flow +package require cmdline + +set options { \ + { "project.arg" "" "Project name" } \ + { "family.arg" "" "Device family name" } \ + { "device.arg" "" "Device name" } \ + { "top.arg" "" "Top level module" } \ + { "sdc.arg" "" "Timing Design Constraints file" } \ + { "src.arg" "" "Verilog source file" } \ + { "inc.arg" "." "Include path" } \ +} + +array set opts [::cmdline::getoptions quartus(args) $options] + +project_new $opts(project) -overwrite + +set_global_assignment -name FAMILY $opts(family) +set_global_assignment -name DEVICE $opts(device) +set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) +set_global_assignment -name VERILOG_FILE $opts(src) +set_global_assignment -name SEARCH_PATH $opts(inc) +set_global_assignment -name SDC_FILE $opts(sdc) +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 + +proc make_all_pins_virtual {} { + execute_module -tool map + set name_ids [get_names -filter * -node_type pin] + foreach_in_collection name_id $name_ids { + set pin_name [get_name_info -info full_path $name_id] + post_message "Making VIRTUAL_PIN assignment to $pin_name" + set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON + } + export_assignments +} + +make_all_pins_virtual + +project_close \ No newline at end of file diff --git a/rtl/pipe_regs/VX_d_e_reg.v b/rtl/pipe_regs/VX_d_e_reg.v index e25a0d88..6fed097e 100644 --- a/rtl/pipe_regs/VX_d_e_reg.v +++ b/rtl/pipe_regs/VX_d_e_reg.v @@ -1,5 +1,3 @@ - - `include "../VX_define.v" module VX_d_e_reg ( diff --git a/rtl/quartus/Makefile b/rtl/quartus/Makefile index b968c608..8d6fe2f3 100644 --- a/rtl/quartus/Makefile +++ b/rtl/quartus/Makefile @@ -1,60 +1,57 @@ PROJECT = Vortex TOP_LEVEL_ENTITY = Vortex -SRC_FILE = Vortex.v +SRC_FILE = ../Vortex.v PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf QUARTUS_ROOT ?= /tools/reconfig/intel/18.0 # Part, Family FAMILY = "Arria 10" -DEVICE = 10AX115N4F45I3SG +DEVICE = 10AX115N3F40E2SG # Executable Configuration -SYN_ARGS = --read_settings_files=on +SYN_ARGS = --parallel --read_settings_files=on FIT_ARGS = --part=$(DEVICE) --read_settings_files=on ASM_ARGS = STA_ARGS = --do_report_timing # Build targets -all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt +all: $(PROJECT).sta.rpt -syn: smart.log $(PROJECT).syn.rpt +syn: $(PROJECT).syn.rpt -fit: smart.log $(PROJECT).fit.rpt +fit: $(PROJECT).fit.rpt -asm: smart.log $(PROJECT).asm.rpt +asm: $(PROJECT).asm.rpt -sta: smart.log $(PROJECT).sta.rpt +sta: $(PROJECT).sta.rpt smart: smart.log # Target implementations STAMP = echo done > -$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES) - $(QUARTUS_ROOT)/quartus/bin/quartus_sh -t make_pins_virtual.tcl - $(QUARTUS_ROOT)/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS) - # $(QUARTUS_ROOT)/quartus/bin/quartus_sh -t make_pins_virtual.tcl +$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) + quartus_syn $(PROJECT) $(SYN_ARGS) $(STAMP) fit.chg -$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt - $(QUARTUS_ROOT)/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS) +$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt + quartus_fit $(PROJECT) $(FIT_ARGS) $(STAMP) asm.chg $(STAMP) sta.chg -$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt - $(QUARTUS_ROOT)/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS) +$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt + quartus_asm $(PROJECT) $(ASM_ARGS) -$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt - $(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS) - $(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl +$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt + quartus_sta $(PROJECT) $(STA_ARGS) smart.log: $(PROJECT_FILES) - $(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log + quartus_sh --determine_smart_action $(PROJECT) > smart.log # Project initialization $(PROJECT_FILES): - $(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc + quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../VX_cache;../shared_memory;../compat" syn.chg: $(STAMP) syn.chg @@ -72,4 +69,4 @@ program: $(PROJECT).sof quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" clean: - rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox bin/ + rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/rtl/quartus/VX_gpr_syn.qpf b/rtl/quartus/VX_gpr_syn.qpf deleted file mode 100644 index 8938d2a9..00000000 --- a/rtl/quartus/VX_gpr_syn.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2018 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition -# Date created = 00:18:19 September 11, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "18.0" -DATE = "00:18:19 September 11, 2019" - -# Revisions - -PROJECT_REVISION = "VX_gpr_syn" diff --git a/rtl/quartus/VX_gpr_syn.qsf b/rtl/quartus/VX_gpr_syn.qsf deleted file mode 100644 index 62b5701d..00000000 --- a/rtl/quartus/VX_gpr_syn.qsf +++ /dev/null @@ -1,1615 +0,0 @@ -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:18:19 SEPTEMBER 11, 2019" -set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition" -set_global_assignment -name FAMILY "Arria 10" -set_global_assignment -name DEVICE 10AX115N4F45I3SG -set_global_assignment -name TOP_LEVEL_ENTITY Vortex -set_global_assignment -name SEARCH_PATH ../ -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL - -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name VERILOG_FILE ../cache/cache_set.v -set_global_assignment -name VERILOG_FILE ../VX_define.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dram_req_rsp_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_wstall_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_join_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_data_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_exec_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpu_inst_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_lsu_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_exec_unit_req_inter.v -set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v -set_global_assignment -name VERILOG_FILE ../cache/VX_generic_pe.v -set_global_assignment -name VERILOG_FILE ../cache/VX_cache_data_per_index.v -set_global_assignment -name VERILOG_FILE ../cache/VX_cache_data.v -set_global_assignment -name VERILOG_FILE ../cache/VX_cache_bank_valid.v -set_global_assignment -name VERILOG_FILE ../cache/VX_Cache_Bank.v -set_global_assignment -name VERILOG_FILE ../cache/VX_d_cache.v -set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory_block.v -set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v -set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v -set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v -set_global_assignment -name VERILOG_FILE ../VX_alu.v -set_global_assignment -name VERILOG_FILE ../VX_back_end.v -set_global_assignment -name VERILOG_FILE ../VX_context.v -set_global_assignment -name VERILOG_FILE ../VX_context_slave.v -set_global_assignment -name VERILOG_FILE ../VX_decode.v -set_global_assignment -name VERILOG_FILE ../VX_execute.v -set_global_assignment -name VERILOG_FILE ../VX_fetch.v -set_global_assignment -name VERILOG_FILE ../VX_forwarding.v -set_global_assignment -name VERILOG_FILE ../VX_front_end.v -set_global_assignment -name VERILOG_FILE ../VX_generic_register.v -set_global_assignment -name VERILOG_FILE ../VX_gpr.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_stage.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v -set_global_assignment -name VERILOG_FILE ../VX_inst_multiplex.v -set_global_assignment -name VERILOG_FILE ../VX_memory.v -set_global_assignment -name VERILOG_FILE ../VX_register_file.v -set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v -set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v -set_global_assignment -name VERILOG_FILE ../VX_warp.v -set_global_assignment -name VERILOG_FILE ../VX_writeback.v -set_global_assignment -name VERILOG_FILE ../VX_csr_wrapper.v -set_global_assignment -name VERILOG_FILE ../VX_gpgpu_inst.v -set_global_assignment -name VERILOG_FILE ../VX_execute_unit.v -set_global_assignment -name VERILOG_FILE ../VX_lsu.v -set_global_assignment -name VERILOG_FILE ../VX_scheduler.v -set_global_assignment -name VERILOG_FILE ../VX_dmem_controller.v -set_global_assignment -name VERILOG_FILE ../Vortex.v -set_global_assignment -name SDC_FILE vortex.sdc -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932 -set_global_assignment -name TCL_SCRIPT_FILE make_pins_virtual.tcl -set_instance_assignment -name VIRTUAL_PIN ON -to clk -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[0][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[1][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[2][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_d[3][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_readdata_i[0][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_ready_d -set_instance_assignment -name VIRTUAL_PIN ON -to i_m_ready_i -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[0] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[1] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[2] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[3] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[4] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[5] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[6] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[7] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[8] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[9] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[10] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[11] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[12] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[13] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[14] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[15] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[16] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[17] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[18] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[19] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[20] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[21] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[22] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[23] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[24] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[25] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[26] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[27] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[28] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[29] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[30] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_request_pc_address[31] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[0] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[1] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[2] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[3] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[4] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[5] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[6] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[7] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[8] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[9] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[10] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[11] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[12] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[13] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[14] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[15] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[16] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[17] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[18] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[19] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[20] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[21] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[22] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[23] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[24] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[25] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[26] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[27] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[28] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[29] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[30] -set_instance_assignment -name VIRTUAL_PIN ON -to icache_response_instruction[31] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[0] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[1] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[2] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[3] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[4] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[5] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[6] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[7] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[8] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[9] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[10] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[11] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[12] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[13] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[14] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[15] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[16] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[17] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[18] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[19] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[20] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[21] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[22] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[23] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[24] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[25] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[26] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[27] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[28] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[29] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[30] -set_instance_assignment -name VIRTUAL_PIN ON -to io_data[31] -set_instance_assignment -name VIRTUAL_PIN ON -to io_valid -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_d[31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_evict_addr_i[31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_d[31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_addr_i[31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_or_write_d -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_read_or_write_i -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_valid_d -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_valid_i -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[0][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[1][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[2][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_d[3][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][0][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][1][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][2][31] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][0] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][1] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][2] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][3] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][4] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][5] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][6] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][7] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][8] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][9] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][10] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][11] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][12] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][13] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][14] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][15] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][16] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][17] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][18] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][19] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][20] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][21] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][22] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][23] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][24] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][25] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][26] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][27] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][28] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][29] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][30] -set_instance_assignment -name VIRTUAL_PIN ON -to o_m_writedata_i[0][3][31] -set_instance_assignment -name VIRTUAL_PIN ON -to out_ebreak -set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/rtl/quartus/asm.chg b/rtl/quartus/asm.chg deleted file mode 100644 index 19f86f49..00000000 --- a/rtl/quartus/asm.chg +++ /dev/null @@ -1 +0,0 @@ -done diff --git a/rtl/quartus/make_pins_virtual.tcl b/rtl/quartus/make_pins_virtual.tcl deleted file mode 100644 index 976e639d..00000000 --- a/rtl/quartus/make_pins_virtual.tcl +++ /dev/null @@ -1,29 +0,0 @@ -load_package flow - -package require cmdline - -project_open Vortex - -proc make_all_pins_virtual { args } { - - remove_all_instance_assignments -name VIRTUAL_PIN - execute_module -tool map - set name_ids [get_names -filter * -node_type pin] - - foreach_in_collection name_id $name_ids { - set pin_name [get_name_info -info full_path $name_id] - - if { -1 == [lsearch -exact { clk, reset } $pin_name] } { - post_message "Making VIRTUAL_PIN assignment to $pin_name" - set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON - } else { - post_message "Skipping VIRTUAL_PIN assignment to $pin_name" - } - } - export_assignments -} - - -make_all_pins_virtual - - diff --git a/rtl/quartus/map.chg b/rtl/quartus/map.chg index d155914e..62711209 100644 --- a/rtl/quartus/map.chg +++ b/rtl/quartus/map.chg @@ -1 +1 @@ -Wed Sep 11 00:18:22 2019 +Thu Mar 05 06:08:03 2020 diff --git a/rtl/quartus/project.tcl b/rtl/quartus/project.tcl index 3a19b62e..afe69d48 100644 --- a/rtl/quartus/project.tcl +++ b/rtl/quartus/project.tcl @@ -1,3 +1,4 @@ +load_package flow package require cmdline set options { \ @@ -7,6 +8,7 @@ set options { \ { "top.arg" "" "Top level module" } \ { "sdc.arg" "" "Timing Design Constraints file" } \ { "src.arg" "" "Verilog source file" } \ + { "inc.arg" "." "Include path" } \ } array set opts [::cmdline::getoptions quartus(args) $options] @@ -16,103 +18,24 @@ project_new $opts(project) -overwrite set_global_assignment -name FAMILY $opts(family) set_global_assignment -name DEVICE $opts(device) set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) - -set_global_assignment -name SEARCH_PATH ../ - -set_global_assignment -name VERILOG_FILE ../VX_define.v -set_global_assignment -name VERILOG_FILE ../cache/cache_set.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dram_req_rsp_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_wstall_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_join_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_data_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_exec_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpu_inst_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_lsu_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_exec_unit_req_inter.v -set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v -set_global_assignment -name VERILOG_FILE ../cache/VX_generic_pe.v -set_global_assignment -name VERILOG_FILE ../cache/VX_cache_data_per_index.v -set_global_assignment -name VERILOG_FILE ../cache/VX_cache_data.v -set_global_assignment -name VERILOG_FILE ../cache/VX_cache_bank_valid.v -set_global_assignment -name VERILOG_FILE ../cache/VX_Cache_Bank.v -set_global_assignment -name VERILOG_FILE ../cache/VX_d_cache.v -set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory_block.v -set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v -set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v -set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v -set_global_assignment -name VERILOG_FILE ../compat/VX_divide.v -set_global_assignment -name VERILOG_FILE ../compat/VX_mult.v -set_global_assignment -name VERILOG_FILE ../VX_alu.v -set_global_assignment -name VERILOG_FILE ../VX_back_end.v -set_global_assignment -name VERILOG_FILE ../VX_context.v -set_global_assignment -name VERILOG_FILE ../VX_context_slave.v -set_global_assignment -name VERILOG_FILE ../VX_decode.v -set_global_assignment -name VERILOG_FILE ../VX_execute.v -set_global_assignment -name VERILOG_FILE ../VX_fetch.v -set_global_assignment -name VERILOG_FILE ../VX_forwarding.v -set_global_assignment -name VERILOG_FILE ../VX_front_end.v -set_global_assignment -name VERILOG_FILE ../VX_generic_register.v -set_global_assignment -name VERILOG_FILE ../VX_gpr.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_stage.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v -set_global_assignment -name VERILOG_FILE ../VX_inst_multiplex.v -set_global_assignment -name VERILOG_FILE ../VX_memory.v -set_global_assignment -name VERILOG_FILE ../VX_register_file.v -set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v -set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v -set_global_assignment -name VERILOG_FILE ../VX_warp.v -set_global_assignment -name VERILOG_FILE ../VX_writeback.v -set_global_assignment -name VERILOG_FILE ../VX_csr_wrapper.v -set_global_assignment -name VERILOG_FILE ../VX_gpgpu_inst.v -set_global_assignment -name VERILOG_FILE ../VX_execute_unit.v -set_global_assignment -name VERILOG_FILE ../VX_lsu.v -set_global_assignment -name VERILOG_FILE ../VX_scheduler.v -set_global_assignment -name VERILOG_FILE ../VX_dmem_controller.v -set_global_assignment -name VERILOG_FILE ../Vortex.v - - -set_global_assignment -name SDC_FILE vortex.sdc -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name VERILOG_FILE $opts(src) +set_global_assignment -name SEARCH_PATH $opts(inc) +set_global_assignment -name SDC_FILE $opts(sdc) set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 +proc make_all_pins_virtual {} { + execute_module -tool map + set name_ids [get_names -filter * -node_type pin] + foreach_in_collection name_id $name_ids { + set pin_name [get_name_info -info full_path $name_id] + post_message "Making VIRTUAL_PIN assignment to $pin_name" + set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON + } + export_assignments +} -# set where [file dirname [info script]] -# source [file join $where make_pins_virtual.tcl] - -project_close - -# set_global_assignment -name VERILOG_FILE $opts(src) +make_all_pins_virtual +project_close \ No newline at end of file diff --git a/rtl/quartus/smart.log b/rtl/quartus/smart.log index 540778b5..2fedba0b 100644 --- a/rtl/quartus/smart.log +++ b/rtl/quartus/smart.log @@ -1,4 +1,3 @@ -Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support. Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition @@ -15,13 +14,13 @@ Info: Running Quartus Prime Shell Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. - Info: Processing started: Wed Sep 11 00:18:22 2019 -Info: Command: quartus_sh --determine_smart_action VX_gpr_syn -Info: Quartus(args): VX_gpr_syn + Info: Processing started: Thu Mar 5 06:08:03 2020 +Info: Command: quartus_sh --determine_smart_action Vortex +Info: Quartus(args): Vortex Info: SMART_ACTION = SOURCE Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 687 megabytes - Info: Processing ended: Wed Sep 11 00:18:22 2019 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 + Info: Peak virtual memory: 689 megabytes + Info: Processing ended: Thu Mar 5 06:08:04 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/rtl/quartus/vortex.ini b/rtl/quartus/vortex.ini deleted file mode 100644 index e2fb4516..00000000 --- a/rtl/quartus/vortex.ini +++ /dev/null @@ -1,40 +0,0 @@ -load_package flow - - -set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v -set_global_assignment -name VERILOG_FILE ../VX_gpr.v -set_global_assignment -name SDC_FILE vortex.sdc -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL - -# pins configuration -package require cmdline - -proc make_all_pins_virtual { args } { - - set options {\ - { "exclude.arg" "" "List of signals to exclude" } \ - } - array set opts [::cmdline::getoptions quartus(args) $options] - - remove_all_instance_assignments -name VIRTUAL_PIN - execute_module -tool map - set name_ids [get_names -filter * -node_type pin] - - foreach_in_collection name_id $name_ids { - set pin_name [get_name_info -info full_path $name_id] - - if { -1 == [lsearch -exact $opts(excludes) $pin_name] } { - post_message "Making VIRTUAL_PIN assignment to $pin_name" - set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON - } else { - post_message "Skipping VIRTUAL_PIN assignment to $pin_name" - } - } - export_assignments -} - - -make_all_pins_virtual -exclude { clk, reset } \ No newline at end of file diff --git a/rtl/quartus/vortex.sdc b/rtl/quartus/vortex.sdc index b1fc92c0..3c588f3b 100644 --- a/rtl/quartus/vortex.sdc +++ b/rtl/quartus/vortex.sdc @@ -1,6 +1,6 @@ set_time_format -unit ns -decimal_places 3 -create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] +create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] derive_pll_clocks -create_base_clocks derive_clock_uncertainty From 9c56a10f154ebef26b2a1ddadb7b8fd50fdb586f Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 5 Mar 2020 09:11:43 -0500 Subject: [PATCH 24/66] synthesis fixes --- rtl/VX_cache/VX_cache_core_req_bank_sel.v | 2 ++ rtl/VX_cache/VX_fill_invalidator.v | 13 ++++++------ rtl/VX_cache/VX_tag_data_structure.v | 2 ++ rtl/quartus/fit.chg | 1 - rtl/quartus/map.chg | 1 - rtl/quartus/smart.log | 26 ----------------------- rtl/quartus/sta.chg | 1 - rtl/quartus/syn.chg | 1 - 8 files changed, 10 insertions(+), 37 deletions(-) delete mode 100644 rtl/quartus/fit.chg delete mode 100644 rtl/quartus/map.chg delete mode 100644 rtl/quartus/smart.log delete mode 100644 rtl/quartus/sta.chg delete mode 100644 rtl/quartus/syn.chg diff --git a/rtl/VX_cache/VX_cache_core_req_bank_sel.v b/rtl/VX_cache/VX_cache_core_req_bank_sel.v index adef7953..fb968fcf 100644 --- a/rtl/VX_cache/VX_cache_core_req_bank_sel.v +++ b/rtl/VX_cache/VX_cache_core_req_bank_sel.v @@ -1,4 +1,6 @@ +`include "VX_cache_config.v" + module VX_cache_core_req_bank_sel ( input wire [`NUMBER_REQUESTS-1:0] core_req_valid, input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, diff --git a/rtl/VX_cache/VX_fill_invalidator.v b/rtl/VX_cache/VX_fill_invalidator.v index c9546610..4cf0d79f 100644 --- a/rtl/VX_cache/VX_fill_invalidator.v +++ b/rtl/VX_cache/VX_fill_invalidator.v @@ -1,4 +1,3 @@ - `include "VX_cache_config.v" module VX_fill_invalidator ( @@ -30,19 +29,19 @@ module VX_fill_invalidator ( integer curr_fill; always @(*) begin - assign invalidate_fill = 0; - assign success_found = 0; - assign success_index = 0; + invalidate_fill = 0; + success_found = 0; + success_index = 0; for (curr_fill = 0; curr_fill < `FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin if (possible_fill && fills_active[curr_fill]) begin - assign invalidate_fill = 1; + invalidate_fill = 1; end if (success_fill) begin - assign success_found = 1; - assign success_index = curr_fill; + success_found = 1; + success_index = curr_fill; end end end diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index 42c5d086..3a5f822b 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -1,3 +1,5 @@ +`include "VX_cache_config.v" + module VX_tag_data_structure ( input wire clk, input wire reset, diff --git a/rtl/quartus/fit.chg b/rtl/quartus/fit.chg deleted file mode 100644 index 19f86f49..00000000 --- a/rtl/quartus/fit.chg +++ /dev/null @@ -1 +0,0 @@ -done diff --git a/rtl/quartus/map.chg b/rtl/quartus/map.chg deleted file mode 100644 index 62711209..00000000 --- a/rtl/quartus/map.chg +++ /dev/null @@ -1 +0,0 @@ -Thu Mar 05 06:08:03 2020 diff --git a/rtl/quartus/smart.log b/rtl/quartus/smart.log deleted file mode 100644 index 2fedba0b..00000000 --- a/rtl/quartus/smart.log +++ /dev/null @@ -1,26 +0,0 @@ -Info: ******************************************************************* -Info: Running Quartus Prime Shell - Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition - Info: Copyright (C) 2018 Intel Corporation. All rights reserved. - Info: Your use of Intel Corporation's design tools, logic functions - Info: and other software and tools, and its AMPP partner logic - Info: functions, and any output files from any of the foregoing - Info: (including device programming or simulation files), and any - Info: associated documentation or information are expressly subject - Info: to the terms and conditions of the Intel Program License - Info: Subscription Agreement, the Intel Quartus Prime License Agreement, - Info: the Intel FPGA IP License Agreement, or other applicable license - Info: agreement, including, without limitation, that your use is for - Info: the sole purpose of programming logic devices manufactured by - Info: Intel and sold by Intel or its authorized distributors. Please - Info: refer to the applicable agreement for further details. - Info: Processing started: Thu Mar 5 06:08:03 2020 -Info: Command: quartus_sh --determine_smart_action Vortex -Info: Quartus(args): Vortex -Info: SMART_ACTION = SOURCE -Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful -Info: Quartus Prime Shell was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 689 megabytes - Info: Processing ended: Thu Mar 5 06:08:04 2020 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 diff --git a/rtl/quartus/sta.chg b/rtl/quartus/sta.chg deleted file mode 100644 index 19f86f49..00000000 --- a/rtl/quartus/sta.chg +++ /dev/null @@ -1 +0,0 @@ -done diff --git a/rtl/quartus/syn.chg b/rtl/quartus/syn.chg deleted file mode 100644 index 19f86f49..00000000 --- a/rtl/quartus/syn.chg +++ /dev/null @@ -1 +0,0 @@ -done From 9f5235dc3ddb082f2a0a677925066d9d7a55e73d Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 5 Mar 2020 10:43:15 -0500 Subject: [PATCH 25/66] added generic_queue_ll --- rtl/VX_cache/VX_bank.v | 8 +-- rtl/VX_cache/VX_cache_dfq_queue.v | 2 +- rtl/VX_cache/VX_cache_req_queue.v | 2 +- rtl/VX_generic_queue_ll.v | 106 ++++++++++++++++++++++++++++++ 4 files changed, 112 insertions(+), 6 deletions(-) create mode 100644 rtl/VX_generic_queue_ll.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 143a5ab6..0f0a4df1 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -62,7 +62,7 @@ module VX_bank ( reg snrq_hazard_st0; assign snrq_valid_st0 = !snrq_empty; - VX_generic_queue #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( + VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( .clk (clk), .reset (reset), .push (snp_req), @@ -82,7 +82,7 @@ module VX_bank ( assign dram_fill_accept = !dfpq_full; - VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( + VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( .clk (clk), .reset (reset), .push (dram_fill_rsp), @@ -385,7 +385,7 @@ module VX_bank ( wire cwbq_full; wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; - VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( + VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( .clk (clk), .reset (reset), @@ -425,7 +425,7 @@ module VX_bank ( assign dram_fill_req_addr = addr_st2; assign dram_wb_req = !dwbq_empty; - VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( + VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( .clk (clk), .reset (reset), diff --git a/rtl/VX_cache/VX_cache_dfq_queue.v b/rtl/VX_cache/VX_cache_dfq_queue.v index 6e0f2dce..69d1ddb3 100644 --- a/rtl/VX_cache/VX_cache_dfq_queue.v +++ b/rtl/VX_cache/VX_cache_dfq_queue.v @@ -33,7 +33,7 @@ module VX_cache_dfq_queue wire push_qual = dfqq_push && !dfqq_full; wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty; - VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( + VX_generic_queue_ll #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( .clk (clk), .reset (reset), .push (push_qual), diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 7ebadfaa..e96998fd 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -69,7 +69,7 @@ module VX_cache_req_queue ( wire push_qual = reqq_push && !reqq_full; wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty; - VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( + VX_generic_queue_ll #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), .push (push_qual), diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v new file mode 100644 index 00000000..2113350b --- /dev/null +++ b/rtl/VX_generic_queue_ll.v @@ -0,0 +1,106 @@ + +module VX_generic_queue_ll + #( + parameter DATAW = 4, + parameter SIZE = 277 + ) + ( + input wire clk, + input wire reset, + input wire push, + input wire[DATAW-1:0] in_data, + + input wire pop, + output wire[DATAW-1:0] out_data, + output wire empty, + output wire full +); + + reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r; + reg[$clog2(SIZE+1)-1:0] size_r; + reg[$clog2(SIZE)-1:0] wr_ctr_r; + reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r; + reg empty_r, full_r, bypass_r; + wire reading, writing; + + assign reading = pop && !empty; + assign writing = push && !full; + + if (SIZE == 1) begin + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= 1; + end else if (reading && !writing) begin + size_r <= 0; + end + + if (writing) begin + head_r <= in_data; + end + end + end + + assign out_data = head_r; + assign empty = (size_r == 0); + assign full = (size_r != 0) && !pop; + end else begin + always @(posedge clk) begin + if (reset) begin + wr_ctr_r <= 0; + end else begin + if (writing) + wr_ctr_r <= wr_ctr_r + 1; + end + end + + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + empty_r <= 1; + full_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= size_r + 1; + empty_r <= 0; + if (size_r == SIZE-1) + full_r <= 1; + end else if (reading && !writing) begin + size_r <= size_r - 1; + if (size_r == 1) + empty_r <= 1; + full_r <= 0; + end + end + end + + always @(posedge clk) begin + if (reset) begin + rd_ptr_r <= 0; + rd_next_ptr_r <= 1; + bypass_r <= 0; + end else begin + if (reading) begin + if (SIZE == 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= ~rd_next_ptr_r; + end else if (SIZE > 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= rd_ptr_r + 2; + end + end + + bypass_r <= writing && (empty_r || (1 == size_r && reading)); + curr_r <= in_data; + head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; + end + end + + assign out_data = bypass_r ? curr_r : head_r; + assign empty = empty_r; + assign full = full_r; + end + +endmodule \ No newline at end of file From 08164266622a7b0f482772e4ac608e6825811163 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 6 Mar 2020 10:31:31 -0500 Subject: [PATCH 26/66] added unit_test --- rtl/VX_cache/VX_bank.v | 8 +-- rtl/VX_cache/VX_cache_dfq_queue.v | 2 +- rtl/VX_cache/VX_cache_req_queue.v | 2 +- rtl/results.txt | 7 --- rtl/unit_tests/generic_queue/Makefile | 11 ++++ rtl/unit_tests/generic_queue/testbench.v | 74 ++++++++++++++++++++++++ 6 files changed, 91 insertions(+), 13 deletions(-) create mode 100644 rtl/unit_tests/generic_queue/Makefile create mode 100644 rtl/unit_tests/generic_queue/testbench.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 0f0a4df1..143a5ab6 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -62,7 +62,7 @@ module VX_bank ( reg snrq_hazard_st0; assign snrq_valid_st0 = !snrq_empty; - VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( + VX_generic_queue #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( .clk (clk), .reset (reset), .push (snp_req), @@ -82,7 +82,7 @@ module VX_bank ( assign dram_fill_accept = !dfpq_full; - VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( + VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( .clk (clk), .reset (reset), .push (dram_fill_rsp), @@ -385,7 +385,7 @@ module VX_bank ( wire cwbq_full; wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; - VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( + VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( .clk (clk), .reset (reset), @@ -425,7 +425,7 @@ module VX_bank ( assign dram_fill_req_addr = addr_st2; assign dram_wb_req = !dwbq_empty; - VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( + VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( .clk (clk), .reset (reset), diff --git a/rtl/VX_cache/VX_cache_dfq_queue.v b/rtl/VX_cache/VX_cache_dfq_queue.v index 69d1ddb3..6e0f2dce 100644 --- a/rtl/VX_cache/VX_cache_dfq_queue.v +++ b/rtl/VX_cache/VX_cache_dfq_queue.v @@ -33,7 +33,7 @@ module VX_cache_dfq_queue wire push_qual = dfqq_push && !dfqq_full; wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty; - VX_generic_queue_ll #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( + VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( .clk (clk), .reset (reset), .push (push_qual), diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index e96998fd..7ebadfaa 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -69,7 +69,7 @@ module VX_cache_req_queue ( wire push_qual = reqq_push && !reqq_full; wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty; - VX_generic_queue_ll #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( + VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), .push (push_qual), diff --git a/rtl/results.txt b/rtl/results.txt index 083332ec..e69de29b 100644 --- a/rtl/results.txt +++ b/rtl/results.txt @@ -1,7 +0,0 @@ -# Dynamic Instructions: 51711 -# of total cycles: 51728 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.00033 -# time to simulate: 0 milliseconds -# GRADE: Failed on test: 4294967295 diff --git a/rtl/unit_tests/generic_queue/Makefile b/rtl/unit_tests/generic_queue/Makefile new file mode 100644 index 00000000..da6eadcc --- /dev/null +++ b/rtl/unit_tests/generic_queue/Makefile @@ -0,0 +1,11 @@ +all: testbench.iv + +testbench.iv: testbench.v + iverilog testbench.v -o testbench.iv -I ../.. + +run: testbench.iv + ! vvp testbench.iv | grep 'ERROR' || false + +clean: + rm testbench.iv + diff --git a/rtl/unit_tests/generic_queue/testbench.v b/rtl/unit_tests/generic_queue/testbench.v new file mode 100644 index 00000000..a406abd5 --- /dev/null +++ b/rtl/unit_tests/generic_queue/testbench.v @@ -0,0 +1,74 @@ +`timescale 1ns/1ns +`include "VX_generic_queue_ll.v" + +`define check(x, y) if ((x == y) !== 1) if ((x == y) === 0) $error("x=%h, expected=%h", x, y); else $warning("x=%h, expected=%h", x, y) + +module testbench(); + + reg clk; + reg reset; + reg[3:0] in_data; + reg push; + reg pop; + wire io_enq_ready; + wire[3:0] out_data; + wire io_deq_valid; + + wire full, empty; + + assign io_enq_ready = !full; + assign io_deq_valid = !empty; + + VX_generic_queue_ll #(.DATAW(4), .SIZE(4)) dut ( + .clk(clk), + .reset(reset), + .in_data(in_data), + .push(push), + .pop(pop), + .out_data(out_data), + .empty(empty), + .full(full)); + + always begin + #1 clk = !clk; + end + + initial begin + $monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h", $time, clk, reset, push, pop, in_data, empty, full, out_data); + #0 clk=0; reset=1; in_data=4'hd; push=1; pop=1; + #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0); + #0 reset=0; in_data=4'ha; pop=0; + #1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0); + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #0 in_data=4'hb; + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #0 in_data=4'hc; + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #0 in_data=4'hd; + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #0 push=0; pop=1; + #1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0); + #0 in_data=4'ha; push=1; pop=0; + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0); + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #0 in_data=4'hb; pop=1; + #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); + #0 push=0; + #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); + #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 0); + #1 $finish; + end + +endmodule From 44f6c68fe998057ebd555c80adac56fb273056c9 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Fri, 6 Mar 2020 22:50:20 -0800 Subject: [PATCH 27/66] Got queue_ll to work by modifying when to update bypass --- rtl/VX_cache/VX_bank.v | 10 +++++----- rtl/VX_cache/VX_cache_dfq_queue.v | 13 ++++++++----- rtl/VX_cache/VX_cache_req_queue.v | 20 ++++++++++++-------- rtl/VX_cache/VX_tag_data_access.v | 16 ++++++++-------- rtl/VX_generic_queue_ll.v | 6 ++++-- 5 files changed, 37 insertions(+), 28 deletions(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 143a5ab6..2deec479 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -62,7 +62,7 @@ module VX_bank ( reg snrq_hazard_st0; assign snrq_valid_st0 = !snrq_empty; - VX_generic_queue #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( + VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( .clk (clk), .reset (reset), .push (snp_req), @@ -82,7 +82,7 @@ module VX_bank ( assign dram_fill_accept = !dfpq_full; - VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( + VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( .clk (clk), .reset (reset), .push (dram_fill_rsp), @@ -199,7 +199,7 @@ module VX_bank ( assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0; assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0; - assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0; + assign reqq_pop = !mrvq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0; assign snrq_pop = !reqq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0; @@ -385,7 +385,7 @@ module VX_bank ( wire cwbq_full; wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; - VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( + VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( .clk (clk), .reset (reset), @@ -425,7 +425,7 @@ module VX_bank ( assign dram_fill_req_addr = addr_st2; assign dram_wb_req = !dwbq_empty; - VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( + VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( .clk (clk), .reset (reset), diff --git a/rtl/VX_cache/VX_cache_dfq_queue.v b/rtl/VX_cache/VX_cache_dfq_queue.v index 6e0f2dce..214d183f 100644 --- a/rtl/VX_cache/VX_cache_dfq_queue.v +++ b/rtl/VX_cache/VX_cache_dfq_queue.v @@ -28,24 +28,26 @@ module VX_cache_dfq_queue wire[`NUMBER_BANKS-1:0] updated_bank_dram_fill_req; + + wire o_empty; + wire use_empty = !(|use_per_bank_dram_fill_req); - wire out_empty = !(|out_per_bank_dram_fill_req); + wire out_empty = !(|out_per_bank_dram_fill_req) || o_empty; wire push_qual = dfqq_push && !dfqq_full; - wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty; - VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( + wire pop_qual = dfqq_pop && use_empty && !out_empty; + VX_generic_queue_ll #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( .clk (clk), .reset (reset), .push (push_qual), .in_data ({per_bank_dram_fill_req, per_bank_dram_fill_req_addr}), .pop (pop_qual), .out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}), - .empty (dfqq_empty), + .empty (o_empty), .full (dfqq_full) ); - assign qual_bank_dram_fill_req = use_empty ? out_per_bank_dram_fill_req : use_per_bank_dram_fill_req; assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr; @@ -57,6 +59,7 @@ module VX_cache_dfq_queue .found (qual_has_request) ); + assign dfqq_empty = !qual_has_request; assign dfqq_req = qual_bank_dram_fill_req [qual_request_index]; assign dfqq_req_addr = qual_bank_dram_fill_req_addr[qual_request_index]; diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 7ebadfaa..2b1e4d98 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -63,25 +63,27 @@ module VX_cache_req_queue ( wire[`NUMBER_REQUESTS-1:0] updated_valids; + wire o_empty; + wire use_empty = !(|use_per_valids); - wire out_empty = !(|out_per_valids); + wire out_empty = !(|out_per_valids) || o_empty; wire push_qual = reqq_push && !reqq_full; - wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty; + wire pop_qual = reqq_pop && use_empty && !out_empty; - VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( + VX_generic_queue_ll #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), .push (push_qual), .in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write}), .pop (pop_qual), .out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write}), - .empty (reqq_empty), + .empty (o_empty), .full (reqq_full) ); - wire[`NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {`NUMBER_REQUESTS{~reqq_empty}}; + wire[`NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {`NUMBER_REQUESTS{~out_empty}}; assign qual_valids = use_empty ? real_out_per_valids : out_empty ? 0 : use_per_valids; assign qual_addr = use_empty ? out_per_addr : use_per_addr; @@ -100,6 +102,7 @@ module VX_cache_req_queue ( .found (qual_has_request) ); + assign reqq_empty = !qual_has_request; assign reqq_req_st0 = qual_has_request; assign reqq_req_tid_st0 = qual_request_index; assign reqq_req_addr_st0 = qual_addr [qual_request_index]; @@ -132,9 +135,10 @@ module VX_cache_req_queue ( use_per_warp_num <= qual_warp_num; use_per_mem_read <= qual_mem_read; use_per_mem_write <= qual_mem_write; - end else if (reqq_pop) begin - use_per_valids[qual_request_index] <= updated_valids; - end + end + // else if (reqq_pop) begin + // use_per_valids[qual_request_index] <= updated_valids; + // end end end diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 3ce6622c..e96d4eea 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -105,11 +105,11 @@ module VX_tag_data_access ( wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG]; wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG]; - wire lw = (mem_read_st1e == `LW_MEM_READ); - wire lb = (mem_read_st1e == `LB_MEM_READ); - wire lh = (mem_read_st1e == `LH_MEM_READ); - wire lhu = (mem_read_st1e == `LHU_MEM_READ); - wire lbu = (mem_read_st1e == `LBU_MEM_READ); + wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ); + wire lb = valid_req_st1e && (mem_read_st1e == `LB_MEM_READ); + wire lh = valid_req_st1e && (mem_read_st1e == `LH_MEM_READ); + wire lhu = valid_req_st1e && (mem_read_st1e == `LHU_MEM_READ); + wire lbu = valid_req_st1e && (mem_read_st1e == `LBU_MEM_READ); wire b0 = (byte_select == 0); wire b1 = (byte_select == 1); @@ -160,9 +160,9 @@ module VX_tag_data_access ( /////////////////////// STORE LOGIC /////////////////// - wire sw = (mem_write_st1e == `SW_MEM_WRITE); - wire sb = (mem_write_st1e == `SB_MEM_WRITE); - wire sh = (mem_write_st1e == `SH_MEM_WRITE); + wire sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE); + wire sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE); + wire sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE); wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v index 2113350b..d92ff164 100644 --- a/rtl/VX_generic_queue_ll.v +++ b/rtl/VX_generic_queue_ll.v @@ -92,8 +92,10 @@ module VX_generic_queue_ll end end - bypass_r <= writing && (empty_r || (1 == size_r && reading)); - curr_r <= in_data; + if (!(!reading && bypass_r)) begin + bypass_r <= writing && (empty_r || (1 == size_r && reading)); + curr_r <= in_data; + end head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; end end From fb23812e95ddbf11132629463b833e82b469d189 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Fri, 6 Mar 2020 23:04:42 -0800 Subject: [PATCH 28/66] Added Lower Level Cache Hit Queue --- rtl/VX_cache/VX_bank.v | 31 ++++++++++++- rtl/VX_cache/VX_cache.v | 51 +++++++++++++++++++++- rtl/VX_cache/VX_cache_config.v | 2 + rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v | 41 +++++++++++++++++ rtl/results.txt | 0 5 files changed, 122 insertions(+), 3 deletions(-) create mode 100644 rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v delete mode 100644 rtl/results.txt diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 2deec479..f1d3a354 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -46,7 +46,14 @@ module VX_bank ( // Snp Request input wire snp_req, - input wire[31:0] snp_req_addr + input wire[31:0] snp_req_addr, + + // Lower Level Cache Response + input wire llvq_pop, + output wire llvq_valid, + output wire[31:0] llvq_res_addr, + output wire[`BANK_LINE_SIZE_RNG][31:0] llvq_res_data, + output wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] llvq_res_tid ); @@ -439,6 +446,28 @@ module VX_bank ( ); + // Lower Cache Hit + wire llvq_empty; + wire llvq_full; + wire llvq_push = valid_st2 && !miss_st2; + wire[`BANK_LINE_SIZE_RNG][31:0] llvq_push_data = readdata_st2; + wire llvq_addr = addr_st2; + wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid; + + assign llvq_valid = !llvq_empty; + + VX_generic_queue_ll #(.DATAW(`vx_clog2(`NUMBER_REQUESTS) + 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(`LLVQ_SIZE)) llv_queue( + .clk (clk), + .reset (reset), + .push (llvq_push), + .in_data ({llvq_tid , llvq_addr , llvq_push_data}), + .pop (llvq_pop), + .out_data({llvq_res_tid, llvq_res_addr, llvq_res_data}), + .empty (llvq_empty), + .full (llvq_full) + ); + + assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full); endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 62210c02..67ec6737 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -45,7 +45,13 @@ module VX_cache ( // Snoop Req input wire snp_req, - input wire[31:0] snp_req_addr + input wire[31:0] snp_req_addr, + + // Lower Level Cache + input wire llvq_pop, + output wire[`NUMBER_REQUESTS-1:0] llvq_valid, + output wire[`NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, + output wire[`NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data ); @@ -73,11 +79,31 @@ module VX_cache ( wire[`NUMBER_BANKS-1:0] per_bank_reqq_full; + + wire[`NUMBER_BANKS-1:0] per_bank_llvq_pop; + wire[`NUMBER_BANKS-1:0] per_bank_llvq_valid; + wire[`NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr; + wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data; + wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid; + assign delay_req = (|per_bank_reqq_full); assign dram_fill_accept = (`NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; + + VX_dcache_llv_resp_bank_sel VX_dcache_llv_resp_bank_sel( + .per_bank_llvq_pop (per_bank_llvq_pop), + .per_bank_llvq_valid (per_bank_llvq_valid), + .per_bank_llvq_res_addr(per_bank_llvq_res_addr), + .per_bank_llvq_res_data(per_bank_llvq_res_data), + .per_bank_llvq_res_tid (per_bank_llvq_res_tid), + .llvq_pop (llvq_pop), + .llvq_valid (llvq_valid), + .llvq_res_addr (llvq_res_addr), + .llvq_res_data (llvq_res_data) + ); + VX_cache_dram_req_arb VX_cache_dram_req_arb( .clk (clk), .reset (reset), @@ -164,6 +190,14 @@ module VX_cache ( wire curr_bank_reqq_full; + + wire curr_bank_llvq_pop; + wire curr_bank_llvq_valid; + wire[31:0] curr_bank_llvq_res_addr; + wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_llvq_res_data; + wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_llvq_res_tid; + + // Core Req assign curr_bank_valids = per_bank_valids[curr_bank]; assign curr_bank_addr = core_req_addr; @@ -207,6 +241,13 @@ module VX_cache ( assign curr_bank_snp_req_addr = snp_req_addr; + // LLVQ + assign curr_bank_llvq_pop = per_bank_llvq_pop[curr_bank]; + assign per_bank_llvq_valid[curr_bank] = curr_bank_llvq_valid; + assign per_bank_llvq_res_data[curr_bank] = curr_bank_llvq_res_data; + assign per_bank_llvq_res_addr[curr_bank] = curr_bank_llvq_res_addr; + assign per_bank_llvq_res_tid[curr_bank] = curr_bank_llvq_res_tid; + VX_bank bank ( .clk (clk), .reset (reset), @@ -252,7 +293,13 @@ module VX_cache ( // Snoop Request .snp_req (curr_bank_snp_req), - .snp_req_addr (curr_bank_snp_req_addr) + .snp_req_addr (curr_bank_snp_req_addr), + + .llvq_pop (curr_bank_llvq_pop), + .llvq_valid (curr_bank_llvq_valid), + .llvq_res_addr (curr_bank_llvq_res_addr), + .llvq_res_data (curr_bank_llvq_res_data), + .llvq_res_tid (curr_bank_llvq_res_tid) ); end diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 07a49242..648c2137 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -37,6 +37,8 @@ `define DWBQ_SIZE 4 // Dram Fill Req Queue Size `define DFQQ_SIZE `REQQ_SIZE + // Lower Level Cache Hit Queue Size + `define LLVQ_SIZE 16 // Fill Invalidator Active {Comment out define statement to invalidate} `define FILL_INVALIDATOR_ACTIVE 1 diff --git a/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v b/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v new file mode 100644 index 00000000..97dc22d2 --- /dev/null +++ b/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v @@ -0,0 +1,41 @@ +`include "VX_cache_config.v" + +module VX_dcache_llv_resp_bank_sel ( + output reg [`NUMBER_BANKS-1:0] per_bank_llvq_pop, + input wire[`NUMBER_BANKS-1:0] per_bank_llvq_valid, + input wire[`NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr, + input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data, + input wire[`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid, + + input wire llvq_pop, + output reg[`NUMBER_REQUESTS-1:0] llvq_valid, + output reg[`NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, + output reg[`NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data + + +); + + wire [(`vx_clog2(`NUMBER_BANKS))-1:0] main_bank_index; + wire found_bank; + + VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + .valids(per_bank_llvq_valid), + .index (main_bank_index), + .found (found_bank) + ); + + + always @(*) begin + llvq_valid = 0; + llvq_res_addr = 0; + llvq_res_data = 0; + per_bank_llvq_pop = 0; + if (found_bank && llvq_pop) begin + llvq_valid [per_bank_llvq_res_tid] = 1; + llvq_res_addr[per_bank_llvq_res_tid] = per_bank_llvq_res_addr[main_bank_index]; + llvq_res_data[per_bank_llvq_res_tid] = per_bank_llvq_res_data[main_bank_index]; + per_bank_llvq_pop[main_bank_index] = 1; + end + end + +endmodule diff --git a/rtl/results.txt b/rtl/results.txt deleted file mode 100644 index e69de29b..00000000 From 9bf0add93732bc7ca56780a0c39e561b4a1f12ee Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sat, 7 Mar 2020 00:49:40 -0800 Subject: [PATCH 29/66] Made the cache module configurable for multi-instantiation --- rtl/VX_back_end.v | 8 +- rtl/VX_cache/VX_bank.v | 200 ++++++++++++--- rtl/VX_cache/VX_cache.v | 227 ++++++++++++++---- rtl/VX_cache/VX_cache_config.v | 58 +---- rtl/VX_cache/VX_cache_core_req_bank_sel.v | 56 ++++- rtl/VX_cache/VX_cache_dfq_queue.v | 67 +++++- rtl/VX_cache/VX_cache_dram_req_arb.v | 68 +++++- rtl/VX_cache/VX_cache_miss_resrv.v | 164 ++++++++----- rtl/VX_cache/VX_cache_req_queue.v | 82 +++++-- rtl/VX_cache/VX_cache_wb_sel_merge.v | 78 ++++-- rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v | 66 ++++- rtl/VX_cache/VX_fill_invalidator.v | 106 +++++--- rtl/VX_cache/VX_tag_data_access.v | 99 ++++++-- rtl/VX_cache/VX_tag_data_structure.v | 46 +++- rtl/VX_define.v | 115 ++++----- rtl/VX_dmem_controller.v | 33 ++- rtl/VX_generic_queue_ll.v | 168 +++++++------ rtl/Vortex.v | 23 +- rtl/interfaces/VX_gpu_dcache_dram_req_inter.v | 8 +- rtl/interfaces/VX_gpu_dcache_dram_res_inter.v | 8 +- rtl/interfaces/VX_gpu_dcache_req_inter.v | 12 +- rtl/interfaces/VX_gpu_dcache_res_inter.v | 10 +- 22 files changed, 1209 insertions(+), 493 deletions(-) diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index 9b51e9ed..fdbcfd5f 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -5,6 +5,9 @@ module VX_back_end ( input wire reset, input wire schedule_delay, + VX_gpu_dcache_res_inter VX_dcache_rsp, + VX_gpu_dcache_req_inter VX_dcache_req, + output wire out_mem_delay, output wire out_exec_delay, output wire gpr_stage_delay, @@ -14,10 +17,7 @@ module VX_back_end ( VX_frE_to_bckE_req_inter VX_bckE_req, VX_wb_inter VX_writeback_inter, - VX_warp_ctl_inter VX_warp_ctl, - - VX_gpu_dcache_res_inter VX_dcache_rsp, - VX_gpu_dcache_req_inter VX_dcache_req + VX_warp_ctl_inter VX_warp_ctl ); diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index f1d3a354..6e1468f6 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -1,14 +1,58 @@ `include "VX_cache_config.v" -module VX_bank ( +module VX_bank + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, // Input Core Request input wire delay_req, - input wire [`NUMBER_REQUESTS-1:0] bank_valids, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [NUMBER_REQUESTS-1:0] bank_valids, + input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr, + input wire [NUMBER_REQUESTS-1:0][31:0] bank_writedata, input wire [4:0] bank_rd, input wire [1:0] bank_wb, input wire [`NW_M1:0] bank_warp_num, @@ -19,7 +63,7 @@ module VX_bank ( // Output Core WB input wire bank_wb_pop, output wire bank_wb_valid, - output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid, + output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] bank_wb_tid, output wire [4:0] bank_wb_rd, output wire [1:0] bank_wb_wb, output wire [`NW_M1:0] bank_wb_warp_num, @@ -53,7 +97,7 @@ module VX_bank ( output wire llvq_valid, output wire[31:0] llvq_res_addr, output wire[`BANK_LINE_SIZE_RNG][31:0] llvq_res_data, - output wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] llvq_res_tid + output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_res_tid ); @@ -69,7 +113,7 @@ module VX_bank ( reg snrq_hazard_st0; assign snrq_valid_st0 = !snrq_empty; - VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue( + VX_generic_queue_ll #(.DATAW(32), .SIZE(SNRQ_SIZE)) snr_queue( .clk (clk), .reset (reset), .push (snp_req), @@ -89,7 +133,7 @@ module VX_bank ( assign dram_fill_accept = !dfpq_full; - VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue( + VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(DFPQ_SIZE)) dfp_queue( .clk (clk), .reset (reset), .push (dram_fill_rsp), @@ -105,7 +149,7 @@ module VX_bank ( wire reqq_push; wire reqq_empty; wire reqq_req_st0; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0; wire [31:0] reqq_req_addr_st0; wire [31:0] reqq_req_writeword_st0; wire [4:0] reqq_req_rd_st0; @@ -117,7 +161,26 @@ module VX_bank ( assign reqq_push = !delay_req && (|bank_valids); - VX_cache_req_queue req_queue( + VX_cache_req_queue #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + req_queue + ( .clk (clk), .reset (reset), // Enqueue @@ -149,7 +212,7 @@ module VX_bank ( wire mrvq_pop; wire mrvq_full; wire mrvq_valid_st0; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] mrvq_tid_st0; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] mrvq_tid_st0; wire [31:0] mrvq_addr_st0; wire [31:0] mrvq_writeword_st0; wire [4:0] mrvq_rd_st0; @@ -162,14 +225,33 @@ module VX_bank ( wire miss_add; wire[31:0] miss_add_addr; wire[31:0] miss_add_data; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid; wire[4:0] miss_add_rd; wire[1:0] miss_add_wb; wire[`NW_M1:0] miss_add_warp_num; wire[2:0] miss_add_mem_read; wire[2:0] miss_add_mem_write; - VX_cache_miss_resrv mrvq_queue( + VX_cache_miss_resrv #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + mrvq_queue + ( .clk (clk), .reset (reset), // Enqueue @@ -217,7 +299,7 @@ module VX_bank ( mrvq_hazard_st0 = 0; reqq_hazard_st0 = 0; snrq_hazard_st0 = 0; - for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin + for (st1_cycle = 0; st1_cycle < STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1; if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1; @@ -239,14 +321,14 @@ module VX_bank ( wire qual_going_to_write_st0; wire qual_is_snp; - wire valid_st1 [`STAGE_1_CYCLES-1:0]; - wire going_to_write_st1[`STAGE_1_CYCLES-1:0]; - wire [31:0] addr_st1 [`STAGE_1_CYCLES-1:0]; - wire [31:0] writeword_st1 [`STAGE_1_CYCLES-1:0]; - wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [`STAGE_1_CYCLES-1:0]; - wire is_fill_st1 [`STAGE_1_CYCLES-1:0]; - wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [`STAGE_1_CYCLES-1:0]; - wire is_snp_st1 [`STAGE_1_CYCLES-1:0]; + wire valid_st1 [STAGE_1_CYCLES-1:0]; + wire going_to_write_st1[STAGE_1_CYCLES-1:0]; + wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0]; + wire [31:0] writeword_st1 [STAGE_1_CYCLES-1:0]; + wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; + wire is_fill_st1 [STAGE_1_CYCLES-1:0]; + wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [STAGE_1_CYCLES-1:0]; + wire is_snp_st1 [STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop; @@ -286,7 +368,7 @@ module VX_bank ( genvar curr_stage; generate - for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin + for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc ( .clk (clk), .reset(reset), @@ -311,16 +393,35 @@ module VX_bank ( wire [`NW_M1:0] warp_num_st1e; wire [2:0] mem_read_st1e; wire [2:0] mem_write_st1e; - wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] tid_st1e; + wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e; wire fill_saw_dirty_st1e; wire is_snp_st1e; - assign is_snp_st1e = is_snp_st1[`STAGE_1_CYCLES-1]; + assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1]; - assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[`STAGE_1_CYCLES-1]; + assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; - VX_tag_data_access VX_tag_data_access( + VX_tag_data_access #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_tag_data_access + ( .clk (clk), .reset (reset), .stall (stall_bank_pipe), @@ -329,11 +430,11 @@ module VX_bank ( .readaddr_st10 (addr_st1[0]), // Actual Read/Write - .valid_req_st1e(valid_st1[`STAGE_1_CYCLES-1]), - .writefill_st1e(is_fill_st1[`STAGE_1_CYCLES-1]), - .writeaddr_st1e(addr_st1[`STAGE_1_CYCLES-1]), - .writeword_st1e(writeword_st1[`STAGE_1_CYCLES-1]), - .writedata_st1e(writedata_st1[`STAGE_1_CYCLES-1]), + .valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]), + .writefill_st1e(is_fill_st1[STAGE_1_CYCLES-1]), + .writeaddr_st1e(addr_st1[STAGE_1_CYCLES-1]), + .writeword_st1e(writeword_st1[STAGE_1_CYCLES-1]), + .writedata_st1e(writedata_st1[STAGE_1_CYCLES-1]), .mem_write_st1e(mem_write_st1e), .mem_read_st1e (mem_read_st1e), @@ -349,7 +450,7 @@ module VX_bank ( .fill_saw_dirty_st1e(fill_saw_dirty_st1e) ); - wire qual_valid_st1e_2 = valid_st1[`STAGE_1_CYCLES-1] && !is_fill_st1[`STAGE_1_CYCLES-1]; + wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1]; wire valid_st2; wire[31:0] addr_st2; @@ -369,7 +470,7 @@ module VX_bank ( .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}), + .in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), .out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 }) ); @@ -384,7 +485,7 @@ module VX_bank ( // Enqueue to CWB Queue wire cwbq_push = (valid_st2 && !miss_st2); wire [31:0] cwbq_data = readword_st2; - wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; + wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; wire [4:0] cwbq_rd = miss_add_rd; wire [1:0] cwbq_wb = miss_add_wb; wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num; @@ -392,7 +493,7 @@ module VX_bank ( wire cwbq_full; wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; - VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue( + VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(CWBQ_SIZE)) cwb_queue( .clk (clk), .reset (reset), @@ -415,7 +516,26 @@ module VX_bank ( wire invalidate_fill; wire possible_fill = valid_st2 && miss_st2; - VX_fill_invalidator VX_fill_invalidator( + VX_fill_invalidator #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_fill_invalidator + ( .clk (clk), .reset (reset), .possible_fill (possible_fill), @@ -432,7 +552,7 @@ module VX_bank ( assign dram_fill_req_addr = addr_st2; assign dram_wb_req = !dwbq_empty; - VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue( + VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(DWBQ_SIZE)) dwb_queue( .clk (clk), .reset (reset), @@ -452,11 +572,11 @@ module VX_bank ( wire llvq_push = valid_st2 && !miss_st2; wire[`BANK_LINE_SIZE_RNG][31:0] llvq_push_data = readdata_st2; wire llvq_addr = addr_st2; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid; assign llvq_valid = !llvq_empty; - VX_generic_queue_ll #(.DATAW(`vx_clog2(`NUMBER_REQUESTS) + 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(`LLVQ_SIZE)) llv_queue( + VX_generic_queue_ll #(.DATAW(`vx_clog2(NUMBER_REQUESTS) + 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(LLVQ_SIZE)) llv_queue( .clk (clk), .reset (reset), .push (llvq_push), diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 67ec6737..e00680ef 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -1,13 +1,57 @@ `include "VX_cache_config.v" -module VX_cache ( +module VX_cache + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, // Req Info - input wire [`NUMBER_REQUESTS-1:0] core_req_valid, - input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, - input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_writedata, + input wire [NUMBER_REQUESTS-1:0] core_req_valid, + input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr, + input wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata, input wire[2:0] core_req_mem_read, input wire[2:0] core_req_mem_write, @@ -19,11 +63,11 @@ module VX_cache ( // Core Writeback input wire core_no_wb_slot, - output wire [`NUMBER_REQUESTS-1:0] core_wb_valid, + output wire [NUMBER_REQUESTS-1:0] core_wb_valid, output wire [4:0] core_wb_req_rd, output wire [1:0] core_wb_req_wb, output wire [`NW_M1:0] core_wb_warp_num, - output wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, + output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, // Dram Fill Response @@ -49,50 +93,69 @@ module VX_cache ( // Lower Level Cache input wire llvq_pop, - output wire[`NUMBER_REQUESTS-1:0] llvq_valid, - output wire[`NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, - output wire[`NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data + output wire[NUMBER_REQUESTS-1:0] llvq_valid, + output wire[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, + output wire[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data ); - wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids; - wire [`NUMBER_BANKS-1:0] per_bank_wb_pop; - wire [`NUMBER_BANKS-1:0] per_bank_wb_valid; - wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid; - wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; - wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; - wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; - wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data; + wire [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids; + wire [NUMBER_BANKS-1:0] per_bank_wb_pop; + wire [NUMBER_BANKS-1:0] per_bank_wb_valid; + wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid; + wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; + wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; + wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; + wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_data; wire dfqq_full; - wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req; - wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; - wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_accept; + wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req; + wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; + wire[NUMBER_BANKS-1:0] per_bank_dram_fill_accept; - wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; - wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; - wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp; - wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; - wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; + wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; + wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req; + wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp; + wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; + wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; - wire[`NUMBER_BANKS-1:0] per_bank_reqq_full; + wire[NUMBER_BANKS-1:0] per_bank_reqq_full; - wire[`NUMBER_BANKS-1:0] per_bank_llvq_pop; - wire[`NUMBER_BANKS-1:0] per_bank_llvq_valid; - wire[`NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr; - wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data; - wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid; + wire[NUMBER_BANKS-1:0] per_bank_llvq_pop; + wire[NUMBER_BANKS-1:0] per_bank_llvq_valid; + wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr; + wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data; + wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid; assign delay_req = (|per_bank_reqq_full); - assign dram_fill_accept = (`NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; + assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; - VX_dcache_llv_resp_bank_sel VX_dcache_llv_resp_bank_sel( + VX_dcache_llv_resp_bank_sel #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_dcache_llv_resp_bank_sel + ( .per_bank_llvq_pop (per_bank_llvq_pop), .per_bank_llvq_valid (per_bank_llvq_valid), .per_bank_llvq_res_addr(per_bank_llvq_res_addr), @@ -104,7 +167,26 @@ module VX_cache ( .llvq_res_data (llvq_res_data) ); - VX_cache_dram_req_arb VX_cache_dram_req_arb( + VX_cache_dram_req_arb #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_cache_dram_req_arb + ( .clk (clk), .reset (reset), .dfqq_full (dfqq_full), @@ -125,14 +207,52 @@ module VX_cache ( ); - VX_cache_core_req_bank_sel VX_cache_core_req_bank_sell( + VX_cache_core_req_bank_sel #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_cache_core_req_bank_sell + ( .core_req_valid (core_req_valid), .core_req_addr (core_req_addr), .per_bank_valids(per_bank_valids) ); - VX_cache_wb_sel_merge VX_cache_core_req_bank_sel( + VX_cache_wb_sel_merge #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_cache_core_req_bank_sel + ( .per_bank_wb_valid (per_bank_wb_valid), .per_bank_wb_tid (per_bank_wb_tid), .per_bank_wb_rd (per_bank_wb_rd), @@ -151,10 +271,10 @@ module VX_cache ( genvar curr_bank; generate - for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin - wire [`NUMBER_REQUESTS-1:0] curr_bank_valids; - wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; + for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin + wire [NUMBER_REQUESTS-1:0] curr_bank_valids; + wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; + wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; wire [4:0] curr_bank_rd; wire [1:0] curr_bank_wb; wire [`NW_M1:0] curr_bank_warp_num; @@ -163,7 +283,7 @@ module VX_cache ( wire curr_bank_wb_pop; wire curr_bank_wb_valid; - wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid; + wire [`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_wb_tid; wire [4:0] curr_bank_wb_rd; wire [1:0] curr_bank_wb_wb; wire [`NW_M1:0] curr_bank_wb_warp_num; @@ -195,7 +315,7 @@ module VX_cache ( wire curr_bank_llvq_valid; wire[31:0] curr_bank_llvq_res_addr; wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_llvq_res_data; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_llvq_res_tid; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_llvq_res_tid; // Core Req @@ -224,7 +344,7 @@ module VX_cache ( assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; // Dram fill response - assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); + assign curr_bank_dram_fill_rsp = (NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank)); assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr; assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data; assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept; @@ -248,7 +368,26 @@ module VX_cache ( assign per_bank_llvq_res_addr[curr_bank] = curr_bank_llvq_res_addr; assign per_bank_llvq_res_tid[curr_bank] = curr_bank_llvq_res_tid; - VX_bank bank ( + VX_bank #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + bank + ( .clk (clk), .reset (reset), // Core req diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 648c2137..0757d15a 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -3,57 +3,11 @@ `include "../VX_define.v" -// ========================================= Configurable Knobs ========================================= - -// General Cache Knobs - // Size of cache in bytes - `define CACHE_SIZE_BYTES 1024 - // Size of line inside a bank in bytes - `define BANK_LINE_SIZE_BYTES 16 - // Number of banks {1, 2, 4, 8,...} - `define NUMBER_BANKS 8 - // Size of a word in bytes - `define WORD_SIZE_BYTES 4 - // Number of Word requests per cycle {1, 2, 4, 8, ...} - `define NUMBER_REQUESTS `NT - // Number of cycles to complete stage 1 (read from memory) - `define STAGE_1_CYCLES 2 - -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - - // Core Request Queue Size - `define REQQ_SIZE `NT*`NW - // Miss Reserv Queue Knob - `define MRVQ_SIZE `REQQ_SIZE - // Dram Fill Rsp Queue Size - `define DFPQ_SIZE 2 - // Snoop Req Queue - `define SNRQ_SIZE 8 - -// Queues for writebacks Knobs {1, 2, 4, 8, ...} - // Core Writeback Queue Size - `define CWBQ_SIZE `REQQ_SIZE - // Dram Writeback Queue Size - `define DWBQ_SIZE 4 - // Dram Fill Req Queue Size - `define DFQQ_SIZE `REQQ_SIZE - // Lower Level Cache Hit Queue Size - `define LLVQ_SIZE 16 - - // Fill Invalidator Active {Comment out define statement to invalidate} - `define FILL_INVALIDATOR_ACTIVE 1 - // Fill Invalidator Size {Fill invalidator must be active} - `define FILL_INVALIDAOR_SIZE 16 - -// Dram knobs - `define SIMULATED_DRAM_LATENCY_CYCLES 10 - -// ========================================= Configurable Knobs ========================================= // data tid rd wb warp_num read write -`define MRVQ_METADATA_SIZE (32 + $clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) +`define MRVQ_METADATA_SIZE (32 + $clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) -`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + $clog2(`NUMBER_REQUESTS)) +`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + $clog2(NUMBER_REQUESTS)) `define vx_clog2(value) $clog2(value) // `define vx_clog2_h(value, x) (value == (1 << x)) ? (x) @@ -93,11 +47,11 @@ // 0 -`define BANK_SIZE_BYTES `CACHE_SIZE_BYTES/`NUMBER_BANKS +`define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUMBER_BANKS -`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/`BANK_LINE_SIZE_BYTES) -`define BANK_LINE_SIZE_WORDS (`BANK_LINE_SIZE_BYTES / `WORD_SIZE_BYTES) +`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/BANK_LINE_SIZE_BYTES) +`define BANK_LINE_SIZE_WORDS (BANK_LINE_SIZE_BYTES / NUMBER_BANKS) `define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0 // Offset is fixed @@ -115,7 +69,7 @@ `define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START `define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0 -`define BANK_SELECT_NUM_BITS $clog2(`NUMBER_BANKS) +`define BANK_SELECT_NUM_BITS $clog2(NUMBER_BANKS) `define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS `define BANK_SELECT_ADDR_START 1+`WORD_SELECT_ADDR_END `define BANK_SELECT_ADDR_END `BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START diff --git a/rtl/VX_cache/VX_cache_core_req_bank_sel.v b/rtl/VX_cache/VX_cache_core_req_bank_sel.v index fb968fcf..cf47d063 100644 --- a/rtl/VX_cache/VX_cache_core_req_bank_sel.v +++ b/rtl/VX_cache/VX_cache_core_req_bank_sel.v @@ -1,11 +1,55 @@ `include "VX_cache_config.v" -module VX_cache_core_req_bank_sel ( - input wire [`NUMBER_REQUESTS-1:0] core_req_valid, - input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, +module VX_cache_core_req_bank_sel + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( + input wire [NUMBER_REQUESTS-1:0] core_req_valid, + input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr, - output reg [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids + output reg [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids ); wire[31:0] req_address; @@ -14,8 +58,8 @@ module VX_cache_core_req_bank_sel ( integer curr_req; always @(*) begin per_bank_valids = 0; - for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin - if (`NUMBER_BANKS == 1) begin + for (curr_req = 0; curr_req < NUMBER_REQUESTS; curr_req = curr_req + 1) begin + if (NUMBER_BANKS == 1) begin // If there is only one bank, then only map requests to that bank per_bank_valids[0][curr_req] = core_req_valid[curr_req]; end else begin diff --git a/rtl/VX_cache/VX_cache_dfq_queue.v b/rtl/VX_cache/VX_cache_dfq_queue.v index 214d183f..b2d4743a 100644 --- a/rtl/VX_cache/VX_cache_dfq_queue.v +++ b/rtl/VX_cache/VX_cache_dfq_queue.v @@ -1,12 +1,55 @@ `include "VX_cache_config.v" module VX_cache_dfq_queue + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) ( input wire clk, input wire reset, input wire dfqq_push, - input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req, - input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, + input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, input wire dfqq_pop, output wire dfqq_req, @@ -15,18 +58,18 @@ module VX_cache_dfq_queue output wire dfqq_full ); - wire[`NUMBER_BANKS-1:0] out_per_bank_dram_fill_req; - wire[`NUMBER_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr; + wire[NUMBER_BANKS-1:0] out_per_bank_dram_fill_req; + wire[NUMBER_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr; - reg [`NUMBER_BANKS-1:0] use_per_bank_dram_fill_req; - reg [`NUMBER_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr; + reg [NUMBER_BANKS-1:0] use_per_bank_dram_fill_req; + reg [NUMBER_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr; - wire[`NUMBER_BANKS-1:0] qual_bank_dram_fill_req; - wire[`NUMBER_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr; + wire[NUMBER_BANKS-1:0] qual_bank_dram_fill_req; + wire[NUMBER_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr; - wire[`NUMBER_BANKS-1:0] updated_bank_dram_fill_req; + wire[NUMBER_BANKS-1:0] updated_bank_dram_fill_req; wire o_empty; @@ -36,7 +79,7 @@ module VX_cache_dfq_queue wire push_qual = dfqq_push && !dfqq_full; wire pop_qual = dfqq_pop && use_empty && !out_empty; - VX_generic_queue_ll #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue( + VX_generic_queue_ll #(.DATAW(NUMBER_BANKS * (1+32)), .SIZE(DFQQ_SIZE)) dfqq_queue( .clk (clk), .reset (reset), .push (push_qual), @@ -51,9 +94,9 @@ module VX_cache_dfq_queue assign qual_bank_dram_fill_req = use_empty ? out_per_bank_dram_fill_req : use_per_bank_dram_fill_req; assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr; - wire[`vx_clog2(`NUMBER_BANKS)-1:0] qual_request_index; + wire[`vx_clog2(NUMBER_BANKS)-1:0] qual_request_index; wire qual_has_request; - VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( .valids(qual_bank_dram_fill_req), .index (qual_request_index), .found (qual_has_request) diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index af5f9ba6..01e699ed 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -1,21 +1,65 @@ `include "VX_cache_config.v" -module VX_cache_dram_req_arb ( +module VX_cache_dram_req_arb + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, // Fill Request output wire dfqq_full, - input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req, - input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, + input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr, // DFQ Request - output wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop, - input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req, - input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, - input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, - input wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp, + output wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop, + input wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, + input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, + input wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp, // real Dram request output wire dram_req, @@ -48,9 +92,9 @@ module VX_cache_dram_req_arb ( .dfqq_full (dfqq_full) ); - wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank; - wire[`NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; - VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb( + wire[`vx_clog2(NUMBER_BANKS)-1:0] dwb_bank; + wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_dwb( .valids(use_wb_valid), .index (dwb_bank), .found (dwb_valid) @@ -64,7 +108,7 @@ module VX_cache_dram_req_arb ( assign dram_req_write = dwb_valid; assign dram_req_read = dfqq_req && !dwb_valid; assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK; - assign dram_req_size = `BANK_LINE_SIZE_BYTES; + assign dram_req_size = BANK_LINE_SIZE_BYTES; assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0; diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v index 9724e761..9c2be799 100644 --- a/rtl/VX_cache/VX_cache_miss_resrv.v +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -1,7 +1,51 @@ `include "VX_cache_config.v" -module VX_cache_miss_resrv ( +module VX_cache_miss_resrv + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, @@ -9,7 +53,7 @@ module VX_cache_miss_resrv ( input wire miss_add, input wire[31:0] miss_add_addr, input wire[31:0] miss_add_data, - input wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid, + input wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid, input wire[4:0] miss_add_rd, input wire[1:0] miss_add_wb, input wire[`NW_M1:0] miss_add_warp_num, @@ -26,7 +70,7 @@ module VX_cache_miss_resrv ( output wire miss_resrv_valid_st0, output wire[31:0] miss_resrv_addr_st0, output wire[31:0] miss_resrv_data_st0, - output wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, + output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, output wire[4:0] miss_resrv_rd_st0, output wire[1:0] miss_resrv_wb_st0, output wire[`NW_M1:0] miss_resrv_warp_num_st0, @@ -35,69 +79,71 @@ module VX_cache_miss_resrv ( ); - // Size of metadata = 32 + `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) - reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[`MRVQ_SIZE-1:0]; - reg[`MRVQ_SIZE-1:0][31:0] addr_table; - reg[`MRVQ_SIZE-1:0] valid_table; - reg[`MRVQ_SIZE-1:0] ready_table; - reg[`vx_clog2(`MRVQ_SIZE)-1:0] head_ptr; - reg[`vx_clog2(`MRVQ_SIZE)-1:0] tail_ptr; + // Size of metadata = 32 + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0]; + reg[MRVQ_SIZE-1:0][31:0] addr_table; + reg[MRVQ_SIZE-1:0] valid_table; + reg[MRVQ_SIZE-1:0] ready_table; + reg[`vx_clog2(MRVQ_SIZE)-1:0] head_ptr; + reg[`vx_clog2(MRVQ_SIZE)-1:0] tail_ptr; - assign miss_resrv_full = (tail_ptr+1) == head_ptr; + assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr; - wire enqueue_possible = !miss_resrv_full; - wire[`vx_clog2(`MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; + wire enqueue_possible = !miss_resrv_full; + wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; - reg[`MRVQ_SIZE-1:0] make_ready; - genvar curr_e; - generate - for (curr_e = 0; curr_e < `MRVQ_SIZE; curr_e=curr_e+1) begin - assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] - && addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START]; + reg[MRVQ_SIZE-1:0] make_ready; + genvar curr_e; + generate + for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin + assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] + && addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START]; + end + endgenerate + + + wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; + wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; + + assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible; + + assign miss_resrv_addr_st0 = addr_table[dequeue_index]; + assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index]; + + wire update_ready = (|make_ready); + integer i; + always @(posedge clk) begin + if (reset) begin + for (i = 0; i < MRVQ_SIZE; i=i+1) metadata_table[i] <= 0; + valid_table <= 0; + ready_table <= 0; + addr_table <= 0; + end else begin + if (miss_add && enqueue_possible && (MRVQ_SIZE != 2)) begin + valid_table[enqueue_index] <= 1; + ready_table[enqueue_index] <= 0; + addr_table[enqueue_index] <= miss_add_addr; + metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write}; + tail_ptr <= tail_ptr + 1; + end + + if (update_ready) begin + ready_table <= ready_table | make_ready; + end + + if (miss_resrv_pop && dequeue_possible) begin + valid_table[dequeue_index] <= 0; + ready_table[dequeue_index] <= 0; + addr_table[dequeue_index] <= 0; + metadata_table[dequeue_index] <= 0; + head_ptr <= head_ptr + 1; + end + + end end - endgenerate - wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; - wire[`vx_clog2(`MRVQ_SIZE)-1:0] dequeue_index = head_ptr; - - assign miss_resrv_valid_st0 = dequeue_possible; - assign miss_resrv_addr_st0 = addr_table[dequeue_index]; - assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index]; - - wire update_ready = (|make_ready); - integer i; - always @(posedge clk) begin - if (reset) begin - for (i = 0; i < `MRVQ_SIZE; i=i+1) metadata_table[i] <= 0; - valid_table <= 0; - ready_table <= 0; - addr_table <= 0; - end else begin - if (miss_add && enqueue_possible) begin - valid_table[enqueue_index] <= 1; - ready_table[enqueue_index] <= 0; - addr_table[enqueue_index] <= miss_add_addr; - metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write}; - tail_ptr <= tail_ptr + 1; - end - - if (update_ready) begin - ready_table <= ready_table | make_ready; - end - - if (miss_resrv_pop && dequeue_possible) begin - valid_table[dequeue_index] <= 0; - ready_table[dequeue_index] <= 0; - addr_table[dequeue_index] <= 0; - metadata_table[dequeue_index] <= 0; - head_ptr <= head_ptr + 1; - end - - end - end - endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 2b1e4d98..cbc4ce67 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -1,14 +1,58 @@ `include "VX_cache_config.v" -module VX_cache_req_queue ( +module VX_cache_req_queue + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, // Enqueue Data input wire reqq_push, - input wire [`NUMBER_REQUESTS-1:0] bank_valids, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [NUMBER_REQUESTS-1:0] bank_valids, + input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr, + input wire [NUMBER_REQUESTS-1:0][31:0] bank_writedata, input wire [4:0] bank_rd, input wire [1:0] bank_wb, input wire [`NW_M1:0] bank_warp_num, @@ -18,7 +62,7 @@ module VX_cache_req_queue ( // Dequeue Data input wire reqq_pop, output wire reqq_req_st0, - output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0, + output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0, output wire [31:0] reqq_req_addr_st0, output wire [31:0] reqq_req_writedata_st0, output wire [4:0] reqq_req_rd_st0, @@ -32,9 +76,9 @@ module VX_cache_req_queue ( output wire reqq_full ); - wire [`NUMBER_REQUESTS-1:0] out_per_valids; - wire [`NUMBER_REQUESTS-1:0][31:0] out_per_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] out_per_writedata; + wire [NUMBER_REQUESTS-1:0] out_per_valids; + wire [NUMBER_REQUESTS-1:0][31:0] out_per_addr; + wire [NUMBER_REQUESTS-1:0][31:0] out_per_writedata; wire [4:0] out_per_rd; wire [1:0] out_per_wb; wire [`NW_M1:0] out_per_warp_num; @@ -42,9 +86,9 @@ module VX_cache_req_queue ( wire [2:0] out_per_mem_write; - reg [`NUMBER_REQUESTS-1:0] use_per_valids; - reg [`NUMBER_REQUESTS-1:0][31:0] use_per_addr; - reg [`NUMBER_REQUESTS-1:0][31:0] use_per_writedata; + reg [NUMBER_REQUESTS-1:0] use_per_valids; + reg [NUMBER_REQUESTS-1:0][31:0] use_per_addr; + reg [NUMBER_REQUESTS-1:0][31:0] use_per_writedata; reg [4:0] use_per_rd; reg [1:0] use_per_wb; reg [`NW_M1:0] use_per_warp_num; @@ -52,16 +96,16 @@ module VX_cache_req_queue ( reg [2:0] use_per_mem_write; - wire [`NUMBER_REQUESTS-1:0] qual_valids; - wire [`NUMBER_REQUESTS-1:0][31:0] qual_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] qual_writedata; + wire [NUMBER_REQUESTS-1:0] qual_valids; + wire [NUMBER_REQUESTS-1:0][31:0] qual_addr; + wire [NUMBER_REQUESTS-1:0][31:0] qual_writedata; wire [4:0] qual_rd; wire [1:0] qual_wb; wire [`NW_M1:0] qual_warp_num; wire [2:0] qual_mem_read; wire [2:0] qual_mem_write; - wire[`NUMBER_REQUESTS-1:0] updated_valids; + wire[NUMBER_REQUESTS-1:0] updated_valids; wire o_empty; @@ -71,7 +115,7 @@ module VX_cache_req_queue ( wire push_qual = reqq_push && !reqq_full; wire pop_qual = reqq_pop && use_empty && !out_empty; - VX_generic_queue_ll #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue( + VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), .push (push_qual), @@ -83,7 +127,7 @@ module VX_cache_req_queue ( ); - wire[`NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {`NUMBER_REQUESTS{~out_empty}}; + wire[NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUMBER_REQUESTS{~out_empty}}; assign qual_valids = use_empty ? real_out_per_valids : out_empty ? 0 : use_per_valids; assign qual_addr = use_empty ? out_per_addr : use_per_addr; @@ -94,9 +138,9 @@ module VX_cache_req_queue ( assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read; assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write; - wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] qual_request_index; + wire[`vx_clog2(NUMBER_REQUESTS)-1:0] qual_request_index; wire qual_has_request; - VX_generic_priority_encoder #(.N(`NUMBER_REQUESTS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUMBER_REQUESTS)) VX_sel_bank( .valids(qual_valids), .index (qual_request_index), .found (qual_has_request) diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v index 0898d66e..99048f0a 100644 --- a/rtl/VX_cache/VX_cache_wb_sel_merge.v +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -1,43 +1,87 @@ `include "VX_cache_config.v" -module VX_cache_wb_sel_merge ( +module VX_cache_wb_sel_merge + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( // Per Bank WB - input wire [`NUMBER_BANKS-1:0] per_bank_wb_valid, - input wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid, - input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, - input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, - input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, - input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data, - output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop, + input wire [NUMBER_BANKS-1:0] per_bank_wb_valid, + input wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid, + input wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, + input wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, + input wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, + input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_data, + output wire [NUMBER_BANKS-1:0] per_bank_wb_pop, // Core Writeback input wire core_no_wb_slot, - output reg [`NUMBER_REQUESTS-1:0] core_wb_valid, - output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, + output reg [NUMBER_REQUESTS-1:0] core_wb_valid, + output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, output wire [4:0] core_wb_req_rd, output wire [1:0] core_wb_req_wb, output wire [`NW_M1:0] core_wb_warp_num ); - reg [`NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; - assign per_bank_wb_pop = per_bank_wb_pop_unqual & {`NUMBER_BANKS{~core_no_wb_slot}}; + reg [NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; + assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUMBER_BANKS{~core_no_wb_slot}}; - wire[`NUMBER_BANKS-1:0] bank_wants_wb; + wire[NUMBER_BANKS-1:0] bank_wants_wb; genvar curr_bank; generate - for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin + for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]); end endgenerate - wire [(`vx_clog2(`NUMBER_BANKS))-1:0] main_bank_index; + wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index; wire found_bank; - VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( .valids(bank_wants_wb), .index (main_bank_index), .found (found_bank) @@ -52,7 +96,7 @@ module VX_cache_wb_sel_merge ( always @(*) begin core_wb_valid = 0; core_wb_readdata = 0; - for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin + for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin core_wb_valid[per_bank_wb_tid[this_bank]] = 1; core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; diff --git a/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v b/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v index 97dc22d2..61dec330 100644 --- a/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v +++ b/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v @@ -1,24 +1,68 @@ `include "VX_cache_config.v" -module VX_dcache_llv_resp_bank_sel ( - output reg [`NUMBER_BANKS-1:0] per_bank_llvq_pop, - input wire[`NUMBER_BANKS-1:0] per_bank_llvq_valid, - input wire[`NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr, - input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data, - input wire[`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid, +module VX_dcache_llv_resp_bank_sel + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( + output reg [NUMBER_BANKS-1:0] per_bank_llvq_pop, + input wire[NUMBER_BANKS-1:0] per_bank_llvq_valid, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr, + input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data, + input wire[NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid, input wire llvq_pop, - output reg[`NUMBER_REQUESTS-1:0] llvq_valid, - output reg[`NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, - output reg[`NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data + output reg[NUMBER_REQUESTS-1:0] llvq_valid, + output reg[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, + output reg[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data ); - wire [(`vx_clog2(`NUMBER_BANKS))-1:0] main_bank_index; + wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index; wire found_bank; - VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank( + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( .valids(per_bank_llvq_valid), .index (main_bank_index), .found (found_bank) diff --git a/rtl/VX_cache/VX_fill_invalidator.v b/rtl/VX_cache/VX_fill_invalidator.v index 4cf0d79f..decdfb15 100644 --- a/rtl/VX_cache/VX_fill_invalidator.v +++ b/rtl/VX_cache/VX_fill_invalidator.v @@ -1,6 +1,50 @@ `include "VX_cache_config.v" -module VX_fill_invalidator ( +module VX_fill_invalidator + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, @@ -14,25 +58,25 @@ module VX_fill_invalidator ( ); - `ifndef FILL_INVALIDATOR_ACTIVE + if (FILL_INVALIDAOR_SIZE == 0) begin assign invalidate_fill = 0; - `else + end else begin - reg[`FILL_INVALIDAOR_SIZE-1:0] fills_active; - reg[`FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address; + reg[FILL_INVALIDAOR_SIZE-1:0] fills_active; + reg[FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address; reg success_found; - reg[(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] success_index; + reg[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] success_index; integer curr_fill; always @(*) begin invalidate_fill = 0; success_found = 0; success_index = 0; - for (curr_fill = 0; curr_fill < `FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin + for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin if (possible_fill && fills_active[curr_fill]) begin @@ -50,39 +94,39 @@ module VX_fill_invalidator ( - wire [(`vx_clog2(`FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; - wire enqueue_found; + wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index; + wire enqueue_found; - VX_generic_priority_encoder #(.N(`FILL_INVALIDAOR_SIZE)) VX_sel_bank( - .valids(fills_active), - .index (enqueue_index), - .found (enqueue_found) - ); + VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank( + .valids(fills_active), + .index (enqueue_index), + .found (enqueue_found) + ); - reg[`FILL_INVALIDAOR_SIZE-1:0] new_valids; + reg[FILL_INVALIDAOR_SIZE-1:0] new_valids; - always @(posedge clk) begin - if (reset) begin - fills_active <= 0; - fills_address <= 0; - end else begin - if (enqueue_found && !invalidate_fill) begin - fills_active[enqueue_index] <= 1; - fills_address[enqueue_index] <= fill_addr; + always @(posedge clk) begin + if (reset) begin + fills_active <= 0; + fills_address <= 0; + end else begin + if (enqueue_found && !invalidate_fill) begin + fills_active[enqueue_index] <= 1; + fills_address[enqueue_index] <= fill_addr; + end + + if (success_found) begin + fills_active[success_index] <= 0; + end + end - - if (success_found) begin - fills_active[success_index] <= 0; - end - end + + end - `endif - - endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index e96d4eea..2ff175cd 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -1,6 +1,50 @@ `include "VX_cache_config.v" -module VX_tag_data_access ( +module VX_tag_data_access + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, input wire stall, @@ -27,12 +71,12 @@ module VX_tag_data_access ( ); - reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[`STAGE_1_CYCLES-1:0]; + reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-1:0]; - reg read_valid_st1c[`STAGE_1_CYCLES-1:0]; - reg read_dirty_st1c[`STAGE_1_CYCLES-1:0]; - reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [`STAGE_1_CYCLES-1:0]; - reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [`STAGE_1_CYCLES-1:0]; + reg read_valid_st1c[STAGE_1_CYCLES-1:0]; + reg read_dirty_st1c[STAGE_1_CYCLES-1:0]; + reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-1:0]; + reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-1:0]; wire qual_read_valid_st1; @@ -50,7 +94,26 @@ module VX_tag_data_access ( wire fill_sent; wire invalidate_line; - VX_tag_data_structure VX_tag_data_structure( + VX_tag_data_structure #( + .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (NUMBER_BANKS), + .WORD_SIZE_BYTES (WORD_SIZE_BYTES), + .NUMBER_REQUESTS (NUMBER_REQUESTS), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .REQQ_SIZE (REQQ_SIZE), + .MRVQ_SIZE (MRVQ_SIZE), + .DFPQ_SIZE (DFPQ_SIZE), + .SNRQ_SIZE (SNRQ_SIZE), + .CWBQ_SIZE (CWBQ_SIZE), + .DWBQ_SIZE (DWBQ_SIZE), + .DFQQ_SIZE (DFQQ_SIZE), + .LLVQ_SIZE (LLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) + ) + VX_tag_data_structure + ( .clk (clk), .reset (reset), @@ -79,7 +142,7 @@ module VX_tag_data_access ( genvar curr_stage; generate - for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin + for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_cc ( .clk (clk), .reset(reset), @@ -92,13 +155,13 @@ module VX_tag_data_access ( endgenerate - assign use_read_valid_st1e = read_valid_st1c[`STAGE_1_CYCLES-1]; - assign use_read_dirty_st1e = read_dirty_st1c[`STAGE_1_CYCLES-1]; - assign use_read_tag_st1e = read_tag_st1c [`STAGE_1_CYCLES-1]; + assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1]; + assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1]; + assign use_read_tag_st1e = read_tag_st1c [STAGE_1_CYCLES-1]; genvar curr_w; - for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[`STAGE_1_CYCLES-1][curr_w][31:0]; - // assign use_read_data_st1e = read_data_st1c [`STAGE_1_CYCLES-1]; + for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-1][curr_w][31:0]; + // assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-1]; /////////////////////// LOAD LOGIC /////////////////// @@ -116,12 +179,12 @@ module VX_tag_data_access ( wire b2 = (byte_select == 2); wire b3 = (byte_select == 3); - wire[31:0] w0 = read_data_st1c[`STAGE_1_CYCLES-1][0][31:0]; - wire[31:0] w1 = read_data_st1c[`STAGE_1_CYCLES-1][1][31:0]; - wire[31:0] w2 = read_data_st1c[`STAGE_1_CYCLES-1][2][31:0]; - wire[31:0] w3 = read_data_st1c[`STAGE_1_CYCLES-1][3][31:0]; + wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0]; + wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0]; + wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0]; + wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0]; - wire[31:0] data_unmod = read_data_st1c[`STAGE_1_CYCLES-1][block_offset][31:0]; + wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset][31:0]; wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) : b1 ? (data_unmod >> 8) : diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index 3a5f822b..c817698d 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -1,6 +1,50 @@ `include "VX_cache_config.v" -module VX_tag_data_structure ( +module VX_tag_data_structure + #( + // Size of cache in bytes + parameter CACHE_SIZE_BYTES = 1024, + // Size of line inside a bank in bytes + parameter BANK_LINE_SIZE_BYTES = 16, + // Number of banks {1, 2, 4, 8,...} + parameter NUMBER_BANKS = 8, + // Size of a word in bytes + parameter WORD_SIZE_BYTES = 4, + // Number of Word requests per cycle {1, 2, 4, 8, ...} + parameter NUMBER_REQUESTS = 2, + // Number of cycles to complete stage 1 (read from memory) + parameter STAGE_1_CYCLES = 2, + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + parameter REQQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MRVQ_SIZE = 8, + // Dram Fill Rsp Queue Size + parameter DFPQ_SIZE = 2, + // Snoop Req Queue + parameter SNRQ_SIZE = 8, + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + parameter CWBQ_SIZE = 8, + // Dram Writeback Queue Size + parameter DWBQ_SIZE = 4, + // Dram Fill Req Queue Size + parameter DFQQ_SIZE = 8, + // Lower Level Cache Hit Queue Size + parameter LLVQ_SIZE = 16, + + // Fill Invalidator Size {Fill invalidator must be active} + parameter FILL_INVALIDAOR_SIZE = 16, + +// Dram knobs + parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 + + + ) + ( input wire clk, input wire reset, diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 45efae34..b2938dcf 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -181,62 +181,6 @@ `define ICACHE_TAG_SIZE_END (32-(`ICACHE_IND_ED+1)-1) `define ICACHE_ADDR_TAG_START (`ICACHE_IND_ED+1) `define ICACHE_ADDR_TAG_END 31 - -//Cache configurations -//Bytes -`define DCACHE_SIZE 4096 -`define DCACHE_WAYS 2 - -//Bytes -`define DCACHE_BLOCK 64 -`define DCACHE_BANKS 4 -`define DCACHE_LOG_NUM_BANKS $clog2(`DCACHE_BANKS) -`define DCACHE_NUM_WORDS_PER_BLOCK (`DCACHE_BLOCK / (`DCACHE_BANKS * 4)) -`define DCACHE_NUM_REQ `NT -`define DCACHE_LOG_NUM_REQ $clog2(`DCACHE_NUM_REQ) - -//set this to 1 if CACHE_WAYS is 1 -`define DCACHE_WAY_INDEX $clog2(`DCACHE_WAYS) -//`define DCACHE_WAY_INDEX 1 -`define DCACHE_BLOCK_PER_BANK (`DCACHE_BLOCK / `DCACHE_BANKS) - -// Offset -`define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)) - -`define DCACHE_ADDR_OFFSET_ST (2+$clog2(`DCACHE_BANKS)) -`define DCACHE_ADDR_OFFSET_ED (`DCACHE_ADDR_OFFSET_ST+(`DCACHE_OFFSET_NB)-1) - - -`define DCACHE_ADDR_OFFSET_RNG `DCACHE_ADDR_OFFSET_ED:`DCACHE_ADDR_OFFSET_ST -`define DCACHE_OFFSET_SIZE_RNG ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1):0 -`define DCACHE_OFFSET_ST 0 -`define DCACHE_OFFSET_ED ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1) - -// Index -// `define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK_PER_BANK)) -`define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK)) -`define DCACHE_IND_NB ($clog2(`DCACHE_NUM_IND)) - -`define DCACHE_IND_ST (`DCACHE_ADDR_OFFSET_ED+1) -`define DCACHE_IND_ED (`DCACHE_IND_ST+`DCACHE_IND_NB-1) - -`define DCACHE_ADDR_IND_RNG `DCACHE_IND_ED:`DCACHE_IND_ST -`define DCACHE_IND_SIZE_RNG `DCACHE_IND_NB-1:0 - -`define DCACHE_IND_SIZE_START 0 -`define DCACHE_IND_SIZE_END `DCACHE_IND_NB-1 - - -// Tag -`define DCACHE_ADDR_TAG_RNG 31:(`DCACHE_IND_ED+1) -`define DCACHE_TAG_SIZE_RNG (32-(`DCACHE_IND_ED+1)-1):0 -`define DCACHE_TAG_SIZE_START 0 -`define DCACHE_TAG_SIZE_END (32-(`DCACHE_IND_ED+1)-1) -`define DCACHE_ADDR_TAG_START (`DCACHE_IND_ED+1) -`define DCACHE_ADDR_TAG_END 31 - -// Mask -`define DCACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`DCACHE_BLOCK-1)) `define ICACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`ICACHE_BLOCK-1)) /////// @@ -264,4 +208,63 @@ `define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1) `define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1) + + + + + +// ========================================= Dcache Configurable Knobs ========================================= + +// General Cache Knobs + // Size of cache in bytes + `define DCACHE_SIZE_BYTES 1024 + // Size of line inside a bank in bytes + `define DBANK_LINE_SIZE_BYTES 16 + // Number of banks {1, 2, 4, 8,...} + `define DNUMBER_BANKS 8 + // Size of a word in bytes + `define DWORD_SIZE_BYTES 4 + // Number of Word requests per cycle {1, 2, 4, 8, ...} + `define DNUMBER_REQUESTS `NT + // Number of cycles to complete stage 1 (read from memory) + `define DSTAGE_1_CYCLES 2 + + // Bank Number of words in a line + `define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DNUMBER_BANKS) + `define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0 +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + `define DREQQ_SIZE `NT*`NW + // Miss Reserv Queue Knob + `define DMRVQ_SIZE `DREQQ_SIZE + // Dram Fill Rsp Queue Size + `define DDFPQ_SIZE 2 + // Snoop Req Queue + `define DSNRQ_SIZE 8 + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + `define DCWBQ_SIZE `DREQQ_SIZE + // Dram Writeback Queue Size + `define DDWBQ_SIZE 4 + // Dram Fill Req Queue Size + `define DDFQQ_SIZE `DREQQ_SIZE + // Lower Level Cache Hit Queue Size + `define DLLVQ_SIZE 0 + + // Fill Invalidator Size {Fill invalidator must be active} + `define DFILL_INVALIDAOR_SIZE 16 + +// Dram knobs + `define DSIMULATED_DRAM_LATENCY_CYCLES 10 + +// ========================================= Dcache Configurable Knobs ========================================= + + + + + + + `endif diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 18226a3b..0a3cecd4 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -3,16 +3,18 @@ module VX_dmem_controller ( input wire clk, input wire reset, - // MEM-RAM + // Dcache VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req, VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res, + VX_gpu_dcache_res_inter VX_dcache_rsp, + VX_gpu_dcache_req_inter VX_dcache_req, + + VX_dram_req_rsp_inter VX_dram_req_rsp_icache, // MEM-Processor VX_icache_request_inter VX_icache_req, - VX_icache_response_inter VX_icache_rsp, - VX_gpu_dcache_req_inter VX_dcache_req, - VX_gpu_dcache_res_inter VX_dcache_rsp + VX_icache_response_inter VX_icache_rsp ); wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; @@ -42,7 +44,7 @@ module VX_dmem_controller ( VX_shared_memory #( .SM_SIZE (`SHARED_MEMORY_SIZE), - .SM_BANKS (`SHARED_MEMORY_BANKS), + .SM_BANKS (`SHARED_MEMORY_BANKS), .SM_BYTES_PER_READ (`SHARED_MEMORY_BYTES_PER_READ), .SM_WORDS_PER_READ (`SHARED_MEMORY_WORDS_PER_READ), .SM_LOG_WORDS_PER_READ (`SHARED_MEMORY_LOG_WORDS_PER_READ), @@ -71,7 +73,26 @@ module VX_dmem_controller ( ); - VX_cache gpu_dcache( + VX_cache #( + .CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`DBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`DNUMBER_BANKS), + .WORD_SIZE_BYTES (`DWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`DNUMBER_REQUESTS), + .STAGE_1_CYCLES (`DSTAGE_1_CYCLES), + .REQQ_SIZE (`DREQQ_SIZE), + .MRVQ_SIZE (`DMRVQ_SIZE), + .DFPQ_SIZE (`DDFPQ_SIZE), + .SNRQ_SIZE (`DSNRQ_SIZE), + .CWBQ_SIZE (`DCWBQ_SIZE), + .DWBQ_SIZE (`DDWBQ_SIZE), + .DFQQ_SIZE (`DDFQQ_SIZE), + .LLVQ_SIZE (`DLLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_dcache + ( .clk (clk), .reset (reset), diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v index d92ff164..a54a2403 100644 --- a/rtl/VX_generic_queue_ll.v +++ b/rtl/VX_generic_queue_ll.v @@ -16,93 +16,103 @@ module VX_generic_queue_ll output wire full ); - reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r; - reg[$clog2(SIZE+1)-1:0] size_r; - reg[$clog2(SIZE)-1:0] wr_ctr_r; - reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r; - reg empty_r, full_r, bypass_r; - wire reading, writing; - - assign reading = pop && !empty; - assign writing = push && !full; - - if (SIZE == 1) begin - always @(posedge clk) begin - if (reset) begin - size_r <= 0; - end else begin - if (writing && !reading) begin - size_r <= 1; - end else if (reading && !writing) begin - size_r <= 0; - end - - if (writing) begin - head_r <= in_data; - end - end - end - - assign out_data = head_r; - assign empty = (size_r == 0); - assign full = (size_r != 0) && !pop; + if (SIZE == 0) begin + assign empty = 1; + assign out_data = 0; + assign full = 0; end else begin - always @(posedge clk) begin - if (reset) begin - wr_ctr_r <= 0; - end else begin - if (writing) - wr_ctr_r <= wr_ctr_r + 1; - end - end - always @(posedge clk) begin - if (reset) begin - size_r <= 0; - empty_r <= 1; - full_r <= 0; - end else begin - if (writing && !reading) begin - size_r <= size_r + 1; - empty_r <= 0; - if (size_r == SIZE-1) - full_r <= 1; - end else if (reading && !writing) begin - size_r <= size_r - 1; - if (size_r == 1) - empty_r <= 1; - full_r <= 0; - end - end - end - - always @(posedge clk) begin - if (reset) begin - rd_ptr_r <= 0; - rd_next_ptr_r <= 1; - bypass_r <= 0; - end else begin - if (reading) begin - if (SIZE == 2) begin - rd_ptr_r <= rd_next_ptr_r; - rd_next_ptr_r <= ~rd_next_ptr_r; - end else if (SIZE > 2) begin - rd_ptr_r <= rd_next_ptr_r; - rd_next_ptr_r <= rd_ptr_r + 2; + reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r; + reg[$clog2(SIZE+1)-1:0] size_r; + reg[$clog2(SIZE)-1:0] wr_ctr_r; + reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r; + reg empty_r, full_r, bypass_r; + wire reading, writing; + + assign reading = pop && !empty; + assign writing = push && !full; + + if (SIZE == 1) begin + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= 1; + end else if (reading && !writing) begin + size_r <= 0; + end + + if (writing) begin + head_r <= in_data; end end + end - if (!(!reading && bypass_r)) begin - bypass_r <= writing && (empty_r || (1 == size_r && reading)); - curr_r <= in_data; - end - head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; + assign out_data = head_r; + assign empty = (size_r == 0); + assign full = (size_r != 0) && !pop; + end else begin + always @(posedge clk) begin + if (reset) begin + wr_ctr_r <= 0; + end else begin + if (writing) + wr_ctr_r <= wr_ctr_r + 1; + end end + + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + empty_r <= 1; + full_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= size_r + 1; + empty_r <= 0; + if (size_r == SIZE-1) + full_r <= 1; + end else if (reading && !writing) begin + size_r <= size_r - 1; + if (size_r == 1) + empty_r <= 1; + full_r <= 0; + end + end + end + + always @(posedge clk) begin + if (reset) begin + rd_ptr_r <= 0; + rd_next_ptr_r <= 1; + bypass_r <= 0; + end else begin + if (reading) begin + if (SIZE == 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= ~rd_next_ptr_r; + end else if (SIZE > 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= rd_ptr_r + 2; + end + end + + if (!(!reading && bypass_r)) begin + bypass_r <= writing && (empty_r || (1 == size_r && reading)); + curr_r <= in_data; + end + head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; + end + end + + assign out_data = bypass_r ? curr_r : head_r; + assign empty = empty_r; + assign full = full_r; end - assign out_data = bypass_r ? curr_r : head_r; - assign empty = empty_r; - assign full = full_r; end + + endmodule \ No newline at end of file diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 78ffa535..cdfa50c2 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -2,13 +2,6 @@ `include "VX_cache_config.v" module Vortex - /*#( - parameter CACHE_SIZE = 4096, // Bytes - parameter CACHE_WAYS = 2, - parameter CACHE_BLOCK = 128, // Bytes - parameter CACHE_BANKS = 8, - parameter NUM_WORDS_PER_BLOCK = 4 - )*/ ( input wire clk, input wire reset, @@ -24,14 +17,14 @@ module Vortex output wire dram_req_read, output wire [31:0] dram_req_addr, output wire [31:0] dram_req_size, - output wire [31:0] dram_req_data[`BANK_LINE_SIZE_RNG], + output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], output wire [31:0] dram_expected_lat, // DRAM Dcache Res output wire dram_fill_accept, input wire dram_fill_rsp, input wire [31:0] dram_fill_rsp_addr, - input wire [31:0] dram_fill_rsp_data[`BANK_LINE_SIZE_RNG], + input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], // Req I Mem @@ -68,11 +61,11 @@ module Vortex // Dcache Interface - VX_gpu_dcache_res_inter VX_dcache_rsp(); - VX_gpu_dcache_req_inter VX_dcache_req(); + VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp(); + VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req(); - VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req(); - VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res(); + VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_req(); + VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_res(); assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp; @@ -83,12 +76,12 @@ module Vortex assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read; assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr; assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size; - assign dram_expected_lat = `SIMULATED_DRAM_LATENCY_CYCLES; + assign dram_expected_lat = `DSIMULATED_DRAM_LATENCY_CYCLES; assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept; genvar wordy; generate - for (wordy = 0; wordy < `BANK_LINE_SIZE_WORDS; wordy=wordy+1) begin + for (wordy = 0; wordy < `DBANK_LINE_SIZE_WORDS; wordy=wordy+1) begin assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy]; assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy]; end diff --git a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v index ccc58dc6..c088b553 100644 --- a/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v @@ -6,7 +6,11 @@ `define VX_GPU_DRAM_DCACHE_REQ -interface VX_gpu_dcache_dram_req_inter (); +interface VX_gpu_dcache_dram_req_inter + #( + parameter BANK_LINE_SIZE_WORDS = 2 + ) + (); // DRAM Request wire dram_req; @@ -14,7 +18,7 @@ interface VX_gpu_dcache_dram_req_inter (); wire dram_req_read; wire [31:0] dram_req_addr; wire [31:0] dram_req_size; - wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data; + wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_req_data; // Snoop wire dram_because_of_snp; diff --git a/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v index 24ba4dc1..a6bd0ff8 100644 --- a/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v @@ -7,11 +7,15 @@ `define VX_GPU_DRAM_DCACHE_RES -interface VX_gpu_dcache_dram_res_inter (); +interface VX_gpu_dcache_dram_res_inter + #( + parameter BANK_LINE_SIZE_WORDS = 2 + ) + (); // DRAM Rsponse wire dram_fill_rsp; wire [31:0] dram_fill_rsp_addr; - wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data; + wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_fill_rsp_data; endinterface diff --git a/rtl/interfaces/VX_gpu_dcache_req_inter.v b/rtl/interfaces/VX_gpu_dcache_req_inter.v index 50ac04e7..003ea4c1 100644 --- a/rtl/interfaces/VX_gpu_dcache_req_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_req_inter.v @@ -6,12 +6,16 @@ `define VX_GPU_DCACHE_REQ -interface VX_gpu_dcache_req_inter (); +interface VX_gpu_dcache_req_inter + #( + parameter NUMBER_REQUESTS = 32 + ) + (); // Core Request - wire [`NUMBER_REQUESTS-1:0] core_req_valid; - wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr; - wire [`NUMBER_REQUESTS-1:0][31:0] core_req_writedata; + wire [NUMBER_REQUESTS-1:0] core_req_valid; + wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr; + wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata; wire [2:0] core_req_mem_read; wire [2:0] core_req_mem_write; wire [4:0] core_req_rd; diff --git a/rtl/interfaces/VX_gpu_dcache_res_inter.v b/rtl/interfaces/VX_gpu_dcache_res_inter.v index 2b5cbbbd..bd32e801 100644 --- a/rtl/interfaces/VX_gpu_dcache_res_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_res_inter.v @@ -6,14 +6,18 @@ `define VX_GPU_DCACHE_RES -interface VX_gpu_dcache_res_inter (); +interface VX_gpu_dcache_res_inter + #( + parameter NUMBER_REQUESTS = 32 + ) + (); // Cache WB - wire [`NUMBER_REQUESTS-1:0] core_wb_valid; + wire [NUMBER_REQUESTS-1:0] core_wb_valid; wire [4:0] core_wb_req_rd; wire [1:0] core_wb_req_wb; wire [`NW_M1:0] core_wb_warp_num; - wire [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata; + wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata; // Cache Full wire delay_req; From 3953a711808dfe5adc58136b0a48cb4bd9593998 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 7 Mar 2020 06:56:11 -0500 Subject: [PATCH 30/66] fixed write logic in generic_queue_ll --- rtl/Makefile | 3 ++ rtl/VX_generic_queue_ll.v | 16 ++++--- rtl/unit_tests/generic_queue/testbench.v | 55 ++++++++---------------- 3 files changed, 32 insertions(+), 42 deletions(-) diff --git a/rtl/Makefile b/rtl/Makefile index c9b2a3fb..5fb2eb5b 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -46,5 +46,8 @@ debug: compdebug w: VERILATORnoWarnings $(MAKECPP) +run: w + (cd obj_dir && ./VVortex) + clean: rm obj_dir/* diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v index d92ff164..233355e5 100644 --- a/rtl/VX_generic_queue_ll.v +++ b/rtl/VX_generic_queue_ll.v @@ -75,6 +75,12 @@ module VX_generic_queue_ll end end end + + always @(posedge clk) begin + if (writing) begin + data[wr_ctr_r] <= in_data; + end + end always @(posedge clk) begin if (reset) begin @@ -92,15 +98,13 @@ module VX_generic_queue_ll end end - if (!(!reading && bypass_r)) begin - bypass_r <= writing && (empty_r || (1 == size_r && reading)); - curr_r <= in_data; - end + bypass_r <= writing && (empty_r || (1 == size_r) && reading); + curr_r <= in_data; head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; end end - - assign out_data = bypass_r ? curr_r : head_r; + + assign out_data = bypass_r ? curr_r : head_r; assign empty = empty_r; assign full = full_r; end diff --git a/rtl/unit_tests/generic_queue/testbench.v b/rtl/unit_tests/generic_queue/testbench.v index a406abd5..b2dc8720 100644 --- a/rtl/unit_tests/generic_queue/testbench.v +++ b/rtl/unit_tests/generic_queue/testbench.v @@ -10,14 +10,9 @@ module testbench(); reg[3:0] in_data; reg push; reg pop; - wire io_enq_ready; wire[3:0] out_data; - wire io_deq_valid; - - wire full, empty; - - assign io_enq_ready = !full; - assign io_deq_valid = !empty; + wire full; + wire empty; VX_generic_queue_ll #(.DATAW(4), .SIZE(4)) dut ( .clk(clk), @@ -34,40 +29,28 @@ module testbench(); end initial begin - $monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h", $time, clk, reset, push, pop, in_data, empty, full, out_data); - #0 clk=0; reset=1; in_data=4'hd; push=1; pop=1; - #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0); - #0 reset=0; in_data=4'ha; pop=0; - #1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0); - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + $monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h", + $time, clk, reset, push, pop, in_data, empty, full, out_data); + #0 clk=0; reset=1; pop=0; push=0; + #2 reset=0; in_data=4'ha; pop=0; push=1; + #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0); #0 in_data=4'hb; - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0); #0 in_data=4'hc; - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 0); #0 in_data=4'hd; - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1); + #2 `check(full, 1); `check(out_data, 4'ha); `check(empty, 0); #0 push=0; pop=1; - #1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0); - #0 in_data=4'ha; push=1; pop=0; - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0); - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); - #0 in_data=4'hb; pop=1; - #1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); + #2 `check(full, 0); `check(out_data, 4'hb); `check(empty, 0); + #2 `check(full, 0); `check(out_data, 4'hc); `check(empty, 0); + #2 `check(full, 0); `check(out_data, 4'hd); `check(empty, 0); + #2 `check(full, 0); `check(out_data, 4'ha); `check(empty, 1); + #0 in_data=4'he; push=1; pop=0; + #2 `check(full, 0); `check(out_data, 4'he); `check(empty, 0); + #0 in_data=4'hf; pop=1; + #2 `check(full, 0); `check(out_data, 4'hf); `check(empty, 0); #0 push=0; - #1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1); - #1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 0); + #2 `check(full, 0); `check(out_data, 4'hc); `check(empty, 1); #1 $finish; end From 507d20f41336679b95d156d885a0a5548b083d35 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 8 Mar 2020 01:55:15 -0800 Subject: [PATCH 31/66] Cache Working on Mem Copy --- rtl/VX_back_end.v | 1 + rtl/VX_cache/VX_bank.v | 33 ++++-- rtl/VX_cache/VX_cache.v | 2 +- rtl/VX_cache/VX_cache_config.v | 2 +- rtl/VX_cache/VX_cache_dfq_queue.v | 2 +- rtl/VX_cache/VX_cache_dram_req_arb.v | 2 +- rtl/VX_cache/VX_cache_miss_resrv.v | 2 +- rtl/VX_cache/VX_fill_invalidator.v | 6 +- rtl/VX_cache/VX_mrv_queue.v | 122 +++++++++++++++++++++++ rtl/VX_cache/VX_tag_data_access.v | 36 +++---- rtl/VX_fetch.v | 18 ++-- rtl/VX_icache_stage.v | 2 +- rtl/VX_scheduler.v | 9 +- rtl/VX_warp_scheduler.v | 24 ++++- rtl/Vortex.v | 26 ++++- rtl/interfaces/VX_gpu_dcache_req_inter.v | 2 +- 16 files changed, 228 insertions(+), 61 deletions(-) create mode 100644 rtl/VX_cache/VX_mrv_queue.v diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index fdbcfd5f..cbdd452e 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -27,6 +27,7 @@ assign VX_writeback_inter.rd = VX_writeback_temp.rd; assign VX_writeback_inter.write_data = VX_writeback_temp.write_data; assign VX_writeback_inter.wb_valid = VX_writeback_temp.wb_valid; assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num; +assign VX_writeback_inter.wb_pc = VX_writeback_temp.wb_pc; // assign VX_writeback_inter(VX_writeback_temp); diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index f12018da..d2b24462 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -294,11 +294,22 @@ module VX_bank ); wire stall_bank_pipe; + reg is_fill_in_pipe; + genvar p_stage; + always @(*) begin + assign is_fill_in_pipe = 0; + for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin + if (is_fill_st1[p_stage]) assign is_fill_in_pipe = 1; + end + + if (is_fill_st2) assign is_fill_in_pipe = 1; + end + assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0; assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0; - assign reqq_pop = !mrvq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0; + assign reqq_pop = !mrvq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe; assign snrq_pop = !reqq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0; @@ -495,14 +506,15 @@ module VX_bank // Enqueue to miss reserv if it's a valid miss - assign miss_add = valid_st2 && miss_st2; + assign miss_add = valid_st2 && miss_st2 && !stall_bank_pipe && !mrvq_full && !(dirty_st2 && dwbq_full); + assign miss_add_pc = pc_st2; assign miss_add_addr = addr_st2; assign miss_add_data = writeword_st2; assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2; // Enqueue to CWB Queue - wire cwbq_push = (valid_st2 && !miss_st2); + wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full & !llvq_full; wire [31:0] cwbq_data = readword_st2; wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; wire [4:0] cwbq_rd = miss_add_rd; @@ -527,8 +539,8 @@ module VX_bank ); // Enqueue to DWB Queue - wire dwbq_push = (valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2; - wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]}; + wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !(!fill_saw_dirty_st2 && mrvq_full); + wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK; wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2; wire dwbq_empty; wire dwbq_full; @@ -536,6 +548,7 @@ module VX_bank wire invalidate_fill; wire possible_fill = valid_st2 && miss_st2; + wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK; VX_fill_invalidator #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), @@ -560,16 +573,16 @@ module VX_bank .reset (reset), .possible_fill (possible_fill), .success_fill (is_fill_st2), - .fill_addr (addr_st2), + .fill_addr (fill_invalidator_addr), .invalidate_fill (invalidate_fill) ); // Enqueu in dram_fill_req - assign dram_fill_req = valid_st2 && miss_st2 && !invalidate_fill; + assign dram_fill_req = valid_st2 && miss_st2 && !invalidate_fill && !dram_fill_req_queue_full; assign dram_because_of_snp = is_snp_st2 && valid_st2 && miss_st2; assign dram_snp_full = snrq_full && snp_req; - assign dram_fill_req_addr = addr_st2; + assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK; assign dram_wb_req = !dwbq_empty; VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(DWBQ_SIZE)) dwb_queue( @@ -589,7 +602,7 @@ module VX_bank // Lower Cache Hit wire llvq_empty; wire llvq_full; - wire llvq_push = valid_st2 && !miss_st2; + wire llvq_push = valid_st2 && !miss_st2 && !llvq_full && !cwbq_full; wire[`BANK_LINE_SIZE_RNG][31:0] llvq_push_data = readdata_st2; wire[31:0] llvq_addr = addr_st2; wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid; @@ -608,7 +621,7 @@ module VX_bank ); - assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full); + assign stall_bank_pipe = (cwbq_push && cwbq_full) || (llvq_push && llvq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full); endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index c8f5d352..855b0905 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -254,7 +254,7 @@ module VX_cache .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) ) - VX_cache_core_req_bank_sel + VX_cache_core_wb_sel_merge ( .per_bank_wb_valid (per_bank_wb_valid), .per_bank_wb_tid (per_bank_wb_tid), diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 5dba0c7e..68d80446 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -115,7 +115,7 @@ `define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0 -`define BASE_ADDR_MASK (~((1<<`WORD_SELECT_ADDR_END)-1)) +`define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1)) `endif diff --git a/rtl/VX_cache/VX_cache_dfq_queue.v b/rtl/VX_cache/VX_cache_dfq_queue.v index b2d4743a..1b95dd02 100644 --- a/rtl/VX_cache/VX_cache_dfq_queue.v +++ b/rtl/VX_cache/VX_cache_dfq_queue.v @@ -91,7 +91,7 @@ module VX_cache_dfq_queue ); - assign qual_bank_dram_fill_req = use_empty ? out_per_bank_dram_fill_req : use_per_bank_dram_fill_req; + assign qual_bank_dram_fill_req = use_empty ? (out_per_bank_dram_fill_req & {NUMBER_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req & {NUMBER_BANKS{!use_empty}}); assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr; wire[`vx_clog2(NUMBER_BANKS)-1:0] qual_request_index; diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index 01e699ed..b2cfab9a 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -101,7 +101,7 @@ module VX_cache_dram_req_arb ); - assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & (~(1 << dwb_bank)); + assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & ((1 << dwb_bank)); assign dram_req = dwb_valid || dfqq_req; diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v index d175aeeb..fcbd5ba7 100644 --- a/rtl/VX_cache/VX_cache_miss_resrv.v +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -95,7 +95,7 @@ module VX_cache_miss_resrv wire enqueue_possible = !miss_resrv_full; - wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; + wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; reg[MRVQ_SIZE-1:0] make_ready; genvar curr_e; diff --git a/rtl/VX_cache/VX_fill_invalidator.v b/rtl/VX_cache/VX_fill_invalidator.v index 33e6eead..e5c0ae10 100644 --- a/rtl/VX_cache/VX_fill_invalidator.v +++ b/rtl/VX_cache/VX_fill_invalidator.v @@ -98,14 +98,12 @@ module VX_fill_invalidator wire enqueue_found; VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank( - .valids(fills_active), + .valids(~fills_active), .index (enqueue_index), .found (enqueue_found) ); - reg[FILL_INVALIDAOR_SIZE-1:0] new_valids; - always @(posedge clk) begin @@ -113,7 +111,7 @@ module VX_fill_invalidator fills_active <= 0; fills_address <= 0; end else begin - if (enqueue_found && !invalidate_fill) begin + if (possible_fill && !invalidate_fill) begin fills_active[enqueue_index] <= 1; fills_address[enqueue_index] <= fill_addr; end diff --git a/rtl/VX_cache/VX_mrv_queue.v b/rtl/VX_cache/VX_mrv_queue.v new file mode 100644 index 00000000..36fedd7a --- /dev/null +++ b/rtl/VX_cache/VX_mrv_queue.v @@ -0,0 +1,122 @@ + +module VX_mrv_queue + #( + parameter DATAW = 4, + parameter SIZE = 277 + ) + ( + input wire clk, + input wire reset, + input wire push, + input wire[DATAW-1:0] in_data, + + input wire pop, + output wire[DATAW-1:0] out_data, + output wire empty, + output wire full +); + + if (SIZE == 0) begin + assign empty = 1; + assign out_data = 0; + assign full = 0; + end else begin + + reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r; + reg[$clog2(SIZE+1)-1:0] size_r; + reg[$clog2(SIZE)-1:0] wr_ctr_r; + reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r; + reg empty_r, full_r, bypass_r; + wire reading, writing; + + assign reading = pop && !empty; + assign writing = push && !full; + + if (SIZE == 1) begin + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= 1; + end else if (reading && !writing) begin + size_r <= 0; + end + + if (writing) begin + head_r <= in_data; + end + end + end + + assign out_data = head_r; + assign empty = (size_r == 0); + assign full = (size_r != 0) && !pop; + end else begin + always @(posedge clk) begin + if (reset) begin + wr_ctr_r <= 0; + end else begin + if (writing) + wr_ctr_r <= wr_ctr_r + 1; + end + end + + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + empty_r <= 1; + full_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= size_r + 1; + empty_r <= 0; + if (size_r == SIZE-1) + full_r <= 1; + end else if (reading && !writing) begin + size_r <= size_r - 1; + if (size_r == 1) + empty_r <= 1; + full_r <= 0; + end + end + end + + always @(posedge clk) begin + if (writing) begin + data[wr_ctr_r] <= in_data; + end + end + + always @(posedge clk) begin + if (reset) begin + rd_ptr_r <= 0; + rd_next_ptr_r <= 1; + bypass_r <= 0; + end else begin + if (reading) begin + if (SIZE == 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= ~rd_next_ptr_r; + end else if (SIZE > 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= rd_ptr_r + 2; + end + end + + bypass_r <= writing && (empty_r || (1 == size_r) && reading); + curr_r <= in_data; + head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; + end + end + + assign out_data = bypass_r ? curr_r : head_r; + assign empty = empty_r; + assign full = full_r; + end + + end + + + +endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 2ff175cd..71710636 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -71,12 +71,12 @@ module VX_tag_data_access ); - reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-1:0]; + reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-2:0]; - reg read_valid_st1c[STAGE_1_CYCLES-1:0]; - reg read_dirty_st1c[STAGE_1_CYCLES-1:0]; - reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-1:0]; - reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-1:0]; + reg read_valid_st1c[STAGE_1_CYCLES-2:0]; + reg read_dirty_st1c[STAGE_1_CYCLES-2:0]; + reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-2:0]; + reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-2:0]; wire qual_read_valid_st1; @@ -142,7 +142,7 @@ module VX_tag_data_access genvar curr_stage; generate - for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin + for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-2; curr_stage = curr_stage + 1) begin VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_cc ( .clk (clk), .reset(reset), @@ -155,13 +155,13 @@ module VX_tag_data_access endgenerate - assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1]; - assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1]; - assign use_read_tag_st1e = read_tag_st1c [STAGE_1_CYCLES-1]; + assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-2]; + assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-2]; + assign use_read_tag_st1e = read_tag_st1c [STAGE_1_CYCLES-2]; genvar curr_w; - for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-1][curr_w][31:0]; - // assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-1]; + for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-2][curr_w][31:0]; + // assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-2]; /////////////////////// LOAD LOGIC /////////////////// @@ -179,12 +179,12 @@ module VX_tag_data_access wire b2 = (byte_select == 2); wire b3 = (byte_select == 3); - wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0]; - wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0]; - wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0]; - wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0]; + wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-2][0][31:0]; + wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-2][1][31:0]; + wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-2][2][31:0]; + wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-2][3][31:0]; - wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset][31:0]; + wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-2][block_offset][31:0]; wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) : b1 ? (data_unmod >> 8) : @@ -231,14 +231,14 @@ module VX_tag_data_access wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e; - wire force_write = writefill_st1e && valid_req_st1e && miss_st1e; + wire force_write = writefill_st1e && valid_req_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e)); wire[`BANK_LINE_SIZE_RNG][3:0] we; wire[`BANK_LINE_SIZE_RNG][31:0] data_write; genvar g; generate for (g = 0; g < `BANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables - wire normal_write = (block_offset == g) && should_write; + wire normal_write = (block_offset == g) && should_write && !writefill_st1e; assign we[g] = (force_write) ? 4'b1111 : (normal_write && sw) ? 4'b1111 : diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index 00330676..923a7294 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -27,21 +27,11 @@ module VX_fetch ( // Only reason this is there is because there is a hidden assumption that decode is exactly after fetch - reg stall_might_be_branch; - always @(posedge clk) begin - if (reset) begin - stall_might_be_branch <= 0; - end else if ((stall_might_be_branch == 1'b1) && !icache_stage_delay && !schedule_delay) begin - stall_might_be_branch <= 0; - end else if (scheduled_warp == 1'b1) begin - stall_might_be_branch <= 1'b1; - end - end // Locals - assign pipe_stall = schedule_delay || icache_stage_delay || (stall_might_be_branch && (icache_stage_wid == warp_num)) ; + assign pipe_stall = schedule_delay || icache_stage_delay; VX_warp_scheduler warp_scheduler( .clk (clk), @@ -68,6 +58,10 @@ module VX_fetch ( .wstall (VX_wstall.wstall), .wstall_warp_num (VX_wstall.warp_num), + // Lock/release Stuff + .icache_stage_valids(icache_stage_valids), + .icache_stage_wid (icache_stage_wid), + // Join .is_join (VX_join.is_join), .join_warp_num (VX_join.join_warp_num), @@ -100,7 +94,7 @@ module VX_fetch ( ); assign fe_inst_meta_fi.warp_num = warp_num; - assign fe_inst_meta_fi.valid = thread_mask && {`NT{!stall_might_be_branch}}; + assign fe_inst_meta_fi.valid = thread_mask; assign fe_inst_meta_fi.instruction = 32'h0; assign fe_inst_meta_fi.inst_pc = warp_pc; diff --git a/rtl/VX_icache_stage.v b/rtl/VX_icache_stage.v index 3c6b3c3d..54233e1b 100644 --- a/rtl/VX_icache_stage.v +++ b/rtl/VX_icache_stage.v @@ -30,7 +30,7 @@ module VX_icache_stage ( assign fe_inst_meta_id.valid = fe_inst_meta_fi.valid & {`NT{!icache_stage_delay}}; assign icache_stage_wid = fe_inst_meta_fi.warp_num; - assign icache_stage_valids = fe_inst_meta_fi.valid; + assign icache_stage_valids = fe_inst_meta_fi.valid & {`NT{!icache_stage_delay}}; endmodule \ No newline at end of file diff --git a/rtl/VX_scheduler.v b/rtl/VX_scheduler.v index c6247ab8..ed796e65 100644 --- a/rtl/VX_scheduler.v +++ b/rtl/VX_scheduler.v @@ -9,11 +9,14 @@ module VX_scheduler ( VX_frE_to_bckE_req_inter VX_bckE_req, VX_wb_inter VX_writeback_inter, - output wire schedule_delay + output wire schedule_delay, + output wire is_empty ); + reg[31:0] count_valid; + assign is_empty = count_valid == 0; reg[31:0][`NT-1:0] rename_table[`NW-1:0]; @@ -67,6 +70,10 @@ module VX_scheduler ( end else begin if (valid_wb ) rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] <= rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] & (~VX_writeback_inter.wb_valid); if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.warp_num ][VX_bckE_req.rd ] <= VX_bckE_req.valid; + + if (valid_wb && ((rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] & (~VX_writeback_inter.wb_valid)) == 0)) count_valid = count_valid - 1; + if (!schedule_delay && wb_inc) count_valid = count_valid + 1; + end end diff --git a/rtl/VX_warp_scheduler.v b/rtl/VX_warp_scheduler.v index 8fcc5a32..42014786 100644 --- a/rtl/VX_warp_scheduler.v +++ b/rtl/VX_warp_scheduler.v @@ -54,7 +54,10 @@ module VX_warp_scheduler ( output wire[`NW_M1:0] warp_num, output wire[31:0] warp_pc, output wire out_ebreak, - output wire scheduled_warp + output wire scheduled_warp, + + input wire[`NW_M1:0] icache_stage_wid, + input wire[`NT-1:0] icache_stage_valids ); @@ -76,8 +79,10 @@ module VX_warp_scheduler ( reg[`NW-1:0] warp_active; reg[`NW-1:0] warp_stalled; - reg[`NW-1:0] visible_active; - wire[`NW-1:0] use_active; + reg [`NW-1:0] visible_active; + wire[`NW-1:0] use_active; + + reg [`NW-1:0] warp_lock; wire wstall_this_cycle; @@ -188,7 +193,7 @@ module VX_warp_scheduler ( // Refilling active warps if (update_visible_active) begin - visible_active <= warp_active & (~warp_stalled) & (~total_barrier_stall); + visible_active <= warp_active & (~warp_stalled) & (~total_barrier_stall) & ~warp_lock; end // Don't change state if stall @@ -208,6 +213,15 @@ module VX_warp_scheduler ( if (branch_dir) warp_pcs[branch_warp_num] <= branch_dest; warp_stalled[branch_warp_num] <= 0; end + + // Lock/Release + if (scheduled_warp && !stall) begin + warp_lock[warp_num] <= 1'b1; + end + if (|icache_stage_valids && !stall) begin + warp_lock[icache_stage_wid] <= 1'b0; + end + end end @@ -294,7 +308,7 @@ module VX_warp_scheduler ( assign new_pc = warp_pc + 4; - assign use_active = (count_visible_active < 1) ? (warp_active & (~warp_stalled) & (~total_barrier_stall)) : visible_active; + assign use_active = (count_visible_active < 1) ? (warp_active & (~warp_stalled) & (~total_barrier_stall) & (~warp_lock)) : visible_active; // Choosing a warp to schedule VX_priority_encoder choose_schedule( diff --git a/rtl/Vortex.v b/rtl/Vortex.v index cdfa50c2..eacfc257 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -40,6 +40,11 @@ module Vortex output wire out_ebreak ); + wire scheduler_empty; + wire out_ebreak_unqual; + + assign out_ebreak = out_ebreak_unqual && (scheduler_empty && 1); + reg[31:0] icache_banks = `ICACHE_BANKS; reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK; @@ -63,6 +68,7 @@ module Vortex // Dcache Interface VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp(); VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req(); + VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_qual(); VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_req(); VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_res(); @@ -88,10 +94,21 @@ module Vortex endgenerate wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000); - wire[31:0] temp_io_data = VX_dcache_req.core_req_valid[0]; + wire[31:0] temp_io_data = VX_dcache_req.core_req_writedata[0]; assign io_valid = temp_io_valid; assign io_data = temp_io_data; + assign VX_dcache_req_qual.core_req_valid = VX_dcache_req.core_req_valid & {`NT{~io_valid}}; + assign VX_dcache_req_qual.core_req_addr = VX_dcache_req.core_req_addr; + assign VX_dcache_req_qual.core_req_writedata = VX_dcache_req.core_req_writedata; + assign VX_dcache_req_qual.core_req_mem_read = VX_dcache_req.core_req_mem_read; + assign VX_dcache_req_qual.core_req_mem_write = VX_dcache_req.core_req_mem_write; + assign VX_dcache_req_qual.core_req_rd = VX_dcache_req.core_req_rd; + assign VX_dcache_req_qual.core_req_wb = VX_dcache_req.core_req_wb; + assign VX_dcache_req_qual.core_req_warp_num = VX_dcache_req.core_req_warp_num; + assign VX_dcache_req_qual.core_req_pc = VX_dcache_req.core_req_pc; + assign VX_dcache_req_qual.core_no_wb_slot = VX_dcache_req.core_no_wb_slot; + VX_icache_response_inter icache_response_fe(); VX_icache_request_inter icache_request_fe(); @@ -145,7 +162,7 @@ VX_front_end vx_front_end( .icache_request_fe (icache_request_fe), .VX_jal_rsp (VX_jal_rsp), .VX_branch_rsp (VX_branch_rsp), - .fetch_ebreak (out_ebreak) + .fetch_ebreak (out_ebreak_unqual) ); VX_scheduler schedule( @@ -156,7 +173,8 @@ VX_scheduler schedule( .gpr_stage_delay (gpr_stage_delay), .VX_bckE_req (VX_bckE_req), .VX_writeback_inter(VX_writeback_inter), - .schedule_delay (schedule_delay) + .schedule_delay (schedule_delay), + .is_empty (scheduler_empty) ); VX_back_end vx_back_end( @@ -184,7 +202,7 @@ VX_dmem_controller VX_dmem_controller( .VX_dram_req_rsp_icache (VX_dram_req_rsp_icache), .VX_icache_req (icache_request_fe), .VX_icache_rsp (icache_response_fe), - .VX_dcache_req (VX_dcache_req), + .VX_dcache_req (VX_dcache_req_qual), .VX_dcache_rsp (VX_dcache_rsp) ); diff --git a/rtl/interfaces/VX_gpu_dcache_req_inter.v b/rtl/interfaces/VX_gpu_dcache_req_inter.v index 2c37f355..83b507fd 100644 --- a/rtl/interfaces/VX_gpu_dcache_req_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_req_inter.v @@ -24,7 +24,7 @@ interface VX_gpu_dcache_req_inter wire [31:0] core_req_pc; // Can't WB - wire core_no_wb_slot; + wire core_no_wb_slot; endinterface From 2f94b26af02d3d943b12576a5258642558a011f3 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 8 Mar 2020 13:59:35 -0700 Subject: [PATCH 32/66] Icache working --- rtl/VX_define.v | 46 ++++++++++++ rtl/VX_dmem_controller.v | 151 ++++++++++++++++++++++---------------- rtl/VX_front_end.v | 21 +++--- rtl/VX_lsu.v | 29 +------- rtl/Vortex.v | 100 +++++++++++++------------ rtl/simulate/test_bench.h | 132 ++++++++++++++++++++------------- 6 files changed, 279 insertions(+), 200 deletions(-) diff --git a/rtl/VX_define.v b/rtl/VX_define.v index ab496034..f9b9d9f5 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -262,7 +262,53 @@ // ========================================= Dcache Configurable Knobs ========================================= +// ========================================= Icache Configurable Knobs ========================================= +// General Cache Knobs + // Size of cache in bytes + `define ICACHE_SIZE_BYTES 1024 + // Size of line inside a bank in bytes + `define IBANK_LINE_SIZE_BYTES 16 + // Number of banks {1, 2, 4, 8,...} + `define INUMBER_BANKS 8 + // Size of a word in bytes + `define IWORD_SIZE_BYTES 4 + // Number of Word requests per cycle {1, 2, 4, 8, ...} + `define INUMBER_REQUESTS 1 + // Number of cycles to complete stage 1 (read from memory) + `define ISTAGE_1_CYCLES 2 + + // Bank Number of words in a line + `define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES) + `define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0 +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + `define IREQQ_SIZE `NW + // Miss Reserv Queue Knob + `define IMRVQ_SIZE `DREQQ_SIZE + // Dram Fill Rsp Queue Size + `define IDFPQ_SIZE 2 + // Snoop Req Queue + `define ISNRQ_SIZE 8 + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + `define ICWBQ_SIZE `DREQQ_SIZE + // Dram Writeback Queue Size + `define IDWBQ_SIZE 4 + // Dram Fill Req Queue Size + `define IDFQQ_SIZE `DREQQ_SIZE + // Lower Level Cache Hit Queue Size + `define ILLVQ_SIZE 0 + + // Fill Invalidator Size {Fill invalidator must be active} + `define IFILL_INVALIDAOR_SIZE 16 + +// Dram knobs + `define ISIMULATED_DRAM_LATENCY_CYCLES 10 + +// ========================================= Icache Configurable Knobs ========================================= diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 451f65d4..19b31caf 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -3,18 +3,22 @@ module VX_dmem_controller ( input wire clk, input wire reset, - // Dcache + + // Dram <-> Dcache VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req, VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res, + // Dram <-> Icache + VX_gpu_dcache_dram_req_inter VX_gpu_icache_dram_req, + VX_gpu_dcache_dram_res_inter VX_gpu_icache_dram_res, + + // Core <-> Dcache VX_gpu_dcache_res_inter VX_dcache_rsp, VX_gpu_dcache_req_inter VX_dcache_req, - - VX_dram_req_rsp_inter VX_dram_req_rsp_icache, - // MEM-Processor - VX_icache_request_inter VX_icache_req, - VX_icache_response_inter VX_icache_rsp + // Core <-> Icache + VX_gpu_dcache_res_inter VX_icache_rsp, + VX_gpu_dcache_req_inter VX_icache_req ); wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; @@ -30,17 +34,6 @@ module VX_dmem_controller ( wire[`NT_M1:0] cache_driver_out_valid; // Not used for now wire sm_delay; - // I_Cache Signals - - wire[31:0] icache_instruction_out; - wire icache_delay; - wire icache_driver_in_valid = VX_icache_req.out_cache_driver_in_valid; - wire[31:0] icache_driver_in_address = VX_icache_req.pc_address; - wire[2:0] icache_driver_in_mem_read = !(|icache_driver_in_valid) ? `NO_MEM_READ : VX_icache_req.out_cache_driver_in_mem_read; - wire[2:0] icache_driver_in_mem_write = !(|icache_driver_in_valid) ? `NO_MEM_WRITE : VX_icache_req.out_cache_driver_in_mem_write; - wire[31:0] icache_driver_in_data = VX_icache_req.out_cache_driver_in_data; - wire read_or_write_ic = (VX_icache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|icache_driver_in_valid); - VX_shared_memory #( .SM_SIZE (`SHARED_MEMORY_SIZE), @@ -159,56 +152,86 @@ module VX_dmem_controller ( ); -VX_d_cache #( - .CACHE_SIZE (`ICACHE_SIZE), - .CACHE_WAYS (`ICACHE_WAYS), - .CACHE_BLOCK (`ICACHE_BLOCK), - .CACHE_BANKS (`ICACHE_BANKS), - .LOG_NUM_BANKS (`ICACHE_LOG_NUM_BANKS), - .NUM_REQ (`ICACHE_NUM_REQ), - .LOG_NUM_REQ (`ICACHE_LOG_NUM_REQ), - .NUM_IND (`ICACHE_NUM_IND), - .CACHE_WAY_INDEX (`ICACHE_WAY_INDEX), - .NUM_WORDS_PER_BLOCK (`ICACHE_NUM_WORDS_PER_BLOCK), - .OFFSET_SIZE_START (`ICACHE_OFFSET_ST), - .OFFSET_SIZE_END (`ICACHE_OFFSET_ED), - .TAG_SIZE_START (`ICACHE_TAG_SIZE_START), - .TAG_SIZE_END (`ICACHE_TAG_SIZE_END), - .IND_SIZE_START (`ICACHE_IND_SIZE_START), - .IND_SIZE_END (`ICACHE_IND_SIZE_END), - .ADDR_TAG_START (`ICACHE_ADDR_TAG_START), - .ADDR_TAG_END (`ICACHE_ADDR_TAG_END), - .ADDR_OFFSET_START (`ICACHE_ADDR_OFFSET_ST), - .ADDR_OFFSET_END (`ICACHE_ADDR_OFFSET_ED), - .ADDR_IND_START (`ICACHE_IND_ST), - .ADDR_IND_END (`ICACHE_IND_ED), - .MEM_ADDR_REQ_MASK (`ICACHE_MEM_REQ_ADDR_MASK) - ) icache + + VX_cache #( + .CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`IBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`INUMBER_BANKS), + .WORD_SIZE_BYTES (`IWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`INUMBER_REQUESTS), + .STAGE_1_CYCLES (`ISTAGE_1_CYCLES), + .REQQ_SIZE (`IREQQ_SIZE), + .MRVQ_SIZE (`IMRVQ_SIZE), + .DFPQ_SIZE (`IDFPQ_SIZE), + .SNRQ_SIZE (`ISNRQ_SIZE), + .CWBQ_SIZE (`ICWBQ_SIZE), + .DWBQ_SIZE (`IDWBQ_SIZE), + .DFQQ_SIZE (`IDFQQ_SIZE), + .LLVQ_SIZE (`ILLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`ISIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_icache ( - .clk (clk), - .rst (reset), - .i_p_valid (icache_driver_in_valid), - .i_p_addr (icache_driver_in_address), - .i_p_writedata (icache_driver_in_data), - .i_p_read_or_write (read_or_write_ic), - .i_p_mem_read (icache_driver_in_mem_read), - .i_p_mem_write (icache_driver_in_mem_write), - .o_p_readdata (icache_instruction_out), - .o_p_delay (icache_delay), - .o_m_evict_addr (VX_dram_req_rsp_icache.o_m_evict_addr), - .o_m_read_addr (VX_dram_req_rsp_icache.o_m_read_addr), - .o_m_valid (VX_dram_req_rsp_icache.o_m_valid), - .o_m_writedata (VX_dram_req_rsp_icache.o_m_writedata), - .o_m_read_or_write (VX_dram_req_rsp_icache.o_m_read_or_write), - .i_m_readdata (VX_dram_req_rsp_icache.i_m_readdata), - .i_m_ready (VX_dram_req_rsp_icache.i_m_ready) - ); + .clk (clk), + .reset (reset), - // assign VX_dcache_rsp.in_cache_driver_out_data = (to_shm && 0) ? sm_driver_out_data : cache_driver_out_data; - // assign VX_dcache_rsp.delay = (sm_delay && 0) || cache_delay; + // Core req + .core_req_valid (VX_icache_req.core_req_valid), + .core_req_addr (VX_icache_req.core_req_addr), + .core_req_writedata(VX_icache_req.core_req_writedata), + .core_req_mem_read (VX_icache_req.core_req_mem_read), + .core_req_mem_write(VX_icache_req.core_req_mem_write), + .core_req_rd (VX_icache_req.core_req_rd), + .core_req_wb (VX_icache_req.core_req_wb), + .core_req_warp_num (VX_icache_req.core_req_warp_num), + .core_req_pc (VX_icache_req.core_req_pc), + + // Delay Core Req + .delay_req (VX_icache_rsp.delay_req), + + // Core Cache Can't WB + .core_no_wb_slot (VX_icache_req.core_no_wb_slot), + + // Cache CWB + .core_wb_valid (VX_icache_rsp.core_wb_valid), + .core_wb_req_rd (VX_icache_rsp.core_wb_req_rd), + .core_wb_req_wb (VX_icache_rsp.core_wb_req_wb), + .core_wb_warp_num (VX_icache_rsp.core_wb_warp_num), + .core_wb_readdata (VX_icache_rsp.core_wb_readdata), + .core_wb_pc (VX_icache_rsp.core_wb_pc), + + // DRAM response + .dram_fill_rsp (VX_gpu_icache_dram_res.dram_fill_rsp), + .dram_fill_rsp_addr(VX_gpu_icache_dram_res.dram_fill_rsp_addr), + .dram_fill_rsp_data(VX_gpu_icache_dram_res.dram_fill_rsp_data), + + // DRAM accept response + .dram_fill_accept (VX_gpu_icache_dram_req.dram_fill_accept), + + // DRAM Req + .dram_req (VX_gpu_icache_dram_req.dram_req), + .dram_req_write (VX_gpu_icache_dram_req.dram_req_write), + .dram_req_read (VX_gpu_icache_dram_req.dram_req_read), + .dram_req_addr (VX_gpu_icache_dram_req.dram_req_addr), + .dram_req_size (VX_gpu_icache_dram_req.dram_req_size), + .dram_req_data (VX_gpu_icache_dram_req.dram_req_data), + + // Snoop Response + .dram_req_because_of_wb(VX_gpu_icache_dram_req.dram_because_of_snp), + .dram_snp_full (VX_gpu_icache_dram_req.dram_snp_full), + + // Snoop Request + .snp_req (0), + .snp_req_addr (0), + + // LLVQ stuff + .llvq_pop (Dllvq_pop), + .llvq_valid (Dllvq_valid), + .llvq_res_addr (Dllvq_res_addr), + .llvq_res_data (Dllvq_res_data) + ); - assign VX_icache_rsp.instruction = icache_instruction_out; - assign VX_icache_rsp.delay = icache_delay; endmodule diff --git a/rtl/VX_front_end.v b/rtl/VX_front_end.v index 0ab8288f..902e9a5c 100644 --- a/rtl/VX_front_end.v +++ b/rtl/VX_front_end.v @@ -8,8 +8,8 @@ module VX_front_end ( VX_warp_ctl_inter VX_warp_ctl, - VX_icache_response_inter icache_response_fe, - VX_icache_request_inter icache_request_fe, + VX_gpu_dcache_res_inter VX_icache_rsp, + VX_gpu_dcache_req_inter VX_icache_req, VX_jal_response_inter VX_jal_rsp, VX_branch_response_inter VX_branch_rsp, @@ -76,15 +76,16 @@ VX_f_d_reg vx_f_i_reg( ); VX_icache_stage VX_icache_stage( - .clk (clk), - .reset (reset), - .icache_stage_delay(icache_stage_delay), + .clk (clk), + .reset (reset), + .total_freeze (total_freeze), + .icache_stage_delay (icache_stage_delay), .icache_stage_valids(icache_stage_valids), - .icache_stage_wid (icache_stage_wid), - .fe_inst_meta_fi (fe_inst_meta_fi2), - .fe_inst_meta_id (fe_inst_meta_id), - .icache_response (icache_response_fe), - .icache_request (icache_request_fe) + .icache_stage_wid (icache_stage_wid), + .fe_inst_meta_fi (fe_inst_meta_fi2), + .fe_inst_meta_id (fe_inst_meta_id), + .VX_icache_rsp (VX_icache_rsp), + .VX_icache_req (VX_icache_req) ); diff --git a/rtl/VX_lsu.v b/rtl/VX_lsu.v index 0081dba8..c8b7aeeb 100644 --- a/rtl/VX_lsu.v +++ b/rtl/VX_lsu.v @@ -56,6 +56,10 @@ module VX_lsu ( assign VX_dcache_req.core_req_warp_num = use_warp_num; assign VX_dcache_req.core_req_pc = use_pc; + // Core can't accept response + assign VX_dcache_req.core_no_wb_slot = no_slot_mem; + + // Cache can't accept request assign out_delay = VX_dcache_rsp.delay_req; @@ -67,33 +71,8 @@ module VX_lsu ( assign VX_mem_wb.loaded_data = VX_dcache_rsp.core_wb_readdata; assign VX_mem_wb.mem_wb_pc = VX_dcache_rsp.core_wb_pc[0]; - // Core can't accept response - assign VX_dcache_req.core_no_wb_slot = no_slot_mem; - // integer curr_t; - // always @(negedge clk) begin - // for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1) - // if ((VX_dcache_req.out_cache_driver_in_valid[curr_t]) && !out_delay) begin - // if (VX_dcache_req.out_cache_driver_in_mem_read != `NO_MEM_READ) begin - // $display("Reading addr: %x val: %x", address[0], VX_mem_wb.loaded_data[0]); - // end - // if (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) begin - // $display("Writing addr: %x val: %x", address[0], VX_dcache_req.out_cache_driver_in_data[0]); - // end - // end - // end - - // wire zero_temp = 0; - // VX_generic_register #(.N(142)) register_wb_data - // ( - // .clk (clk), - // .reset(reset), - // .stall(zero_temp), - // .flush(out_delay), - // .in ({VX_mem_wb_temp.loaded_data, VX_mem_wb_temp.rd, VX_mem_wb_temp.wb, VX_mem_wb_temp.wb_valid, VX_mem_wb_temp.wb_warp_num}), - // .out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num }) - // ); endmodule // Memory diff --git a/rtl/Vortex.v b/rtl/Vortex.v index eacfc257..9fcf3028 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -27,16 +27,22 @@ module Vortex input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], - // Req I Mem - output reg [31:0] o_m_read_addr_i, - output reg [31:0] o_m_evict_addr_i, - output reg o_m_valid_i, - output reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], - output reg o_m_read_or_write_i, + // DRAM Icache Req + output wire I_dram_req, + output wire I_dram_req_write, + output wire I_dram_req_read, + output wire [31:0] I_dram_req_addr, + output wire [31:0] I_dram_req_size, + output wire [31:0] I_dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] I_dram_expected_lat, + + // DRAM Icache Res + output wire I_dram_fill_accept, + input wire I_dram_fill_rsp, + input wire [31:0] I_dram_fill_rsp_addr, + input wire [31:0] I_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + - // Rsp I Mem - input wire [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], - input wire i_m_ready_i, output wire out_ebreak ); @@ -46,19 +52,6 @@ module Vortex assign out_ebreak = out_ebreak_unqual && (scheduler_empty && 1); - reg[31:0] icache_banks = `ICACHE_BANKS; - reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK; - reg[31:0] number_threads = `NT; - reg[31:0] number_warps = `NW; - - always @(posedge clk) begin - icache_banks <= icache_banks; - icache_num_words_per_block <= icache_num_words_per_block; - - number_threads <= number_threads; - number_warps <= number_warps; - end - wire memory_delay; wire exec_delay; wire gpr_stage_delay; @@ -110,30 +103,32 @@ module Vortex assign VX_dcache_req_qual.core_no_wb_slot = VX_dcache_req.core_no_wb_slot; - VX_icache_response_inter icache_response_fe(); - VX_icache_request_inter icache_request_fe(); - VX_dram_req_rsp_inter #( - .NUMBER_BANKS(`ICACHE_BANKS), - .NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK)) VX_dram_req_rsp_icache(); + VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_rsp(); + VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_req(); - //assign icache_response_fe.instruction = icache_response_instruction; - assign icache_request_pc_address = icache_request_fe.pc_address; - - assign o_m_valid_i = VX_dram_req_rsp_icache.o_m_valid; - assign o_m_read_addr_i = VX_dram_req_rsp_icache.o_m_read_addr; - assign o_m_evict_addr_i = VX_dram_req_rsp_icache.o_m_evict_addr; - assign o_m_read_or_write_i = VX_dram_req_rsp_icache.o_m_read_or_write; - assign VX_dram_req_rsp_icache.i_m_ready = i_m_ready_i; - genvar curr_bank; - genvar curr_word; + VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`IBANK_LINE_SIZE_WORDS)) VX_gpu_icache_dram_req(); + VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`IBANK_LINE_SIZE_WORDS)) VX_gpu_icache_dram_res(); -for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin : icache_setup - for (curr_word = 0; curr_word < `ICACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : icache_banks_setup - assign o_m_writedata_i[curr_bank][curr_word] = VX_dram_req_rsp_icache.o_m_writedata[curr_bank][curr_word]; - assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed - end -end + assign VX_gpu_icache_dram_res.dram_fill_rsp = I_dram_fill_rsp; + assign VX_gpu_icache_dram_res.dram_fill_rsp_addr = I_dram_fill_rsp_addr; + + assign I_dram_req = VX_gpu_icache_dram_req.dram_req; + assign I_dram_req_write = VX_gpu_icache_dram_req.dram_req_write; + assign I_dram_req_read = VX_gpu_icache_dram_req.dram_req_read; + assign I_dram_req_addr = VX_gpu_icache_dram_req.dram_req_addr; + assign I_dram_req_size = VX_gpu_icache_dram_req.dram_req_size; + assign I_dram_expected_lat = `ISIMULATED_DRAM_LATENCY_CYCLES; + assign I_dram_fill_accept = VX_gpu_icache_dram_req.dram_fill_accept; + + genvar iwordy; + generate + for (iwordy = 0; iwordy < `IBANK_LINE_SIZE_WORDS; iwordy=iwordy+1) begin + assign VX_gpu_icache_dram_res.dram_fill_rsp_data[iwordy] = I_dram_fill_rsp_data[iwordy]; + assign I_dram_req_data[iwordy] = VX_gpu_icache_dram_req.dram_req_data[iwordy]; + end + endgenerate + ///////////////////////////////////////////////////////////////////////// @@ -158,8 +153,8 @@ VX_front_end vx_front_end( .VX_warp_ctl (VX_warp_ctl), .VX_bckE_req (VX_bckE_req), .schedule_delay (schedule_delay), - .icache_response_fe (icache_response_fe), - .icache_request_fe (icache_request_fe), + .VX_icache_rsp (VX_icache_rsp), + .VX_icache_req (VX_icache_req), .VX_jal_rsp (VX_jal_rsp), .VX_branch_rsp (VX_branch_rsp), .fetch_ebreak (out_ebreak_unqual) @@ -197,11 +192,20 @@ VX_back_end vx_back_end( VX_dmem_controller VX_dmem_controller( .clk (clk), .reset (reset), + + // Dram <-> Dcache .VX_gpu_dcache_dram_req (VX_gpu_dcache_dram_req), .VX_gpu_dcache_dram_res (VX_gpu_dcache_dram_res), - .VX_dram_req_rsp_icache (VX_dram_req_rsp_icache), - .VX_icache_req (icache_request_fe), - .VX_icache_rsp (icache_response_fe), + + // Dram <-> Icache + .VX_gpu_icache_dram_req (VX_gpu_icache_dram_req), + .VX_gpu_icache_dram_res (VX_gpu_icache_dram_res), + + // Core <-> Icache + .VX_icache_req (VX_icache_req), + .VX_icache_rsp (VX_icache_rsp), + + // Core <-> Dcache .VX_dcache_req (VX_dcache_req_qual), .VX_dcache_rsp (VX_dcache_rsp) ); diff --git a/rtl/simulate/test_bench.h b/rtl/simulate/test_bench.h index 72d26652..69e2d257 100644 --- a/rtl/simulate/test_bench.h +++ b/rtl/simulate/test_bench.h @@ -78,6 +78,7 @@ class Vortex int debug_debugAddr; double stats_sim_time; std::vector dram_req_vec; + std::vector I_dram_req_vec; #ifdef VCD_OUTPUT VerilatedVcdC *m_trace; #endif @@ -165,78 +166,100 @@ void Vortex::print_stats(bool cycle_test) bool Vortex::ibus_driver() { - vortex->i_m_ready_i = false; - + // Iterate through each element, and get pop index + int dequeue_index = -1; + bool dequeue_valid = false; + for (int i = 0; i < this->I_dram_req_vec.size(); i++) { - - // int dcache_num_words_per_block - - if (refill_i) + if (this->I_dram_req_vec[i].cycles_left > 0) { - refill_i = false; - vortex->i_m_ready_i = true; - - for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++) - { - for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++) - { - unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank; - unsigned curr_addr = refill_addr_i + (4*curr_index); - - unsigned curr_value; - ram.getWord(curr_addr, &curr_value); - - vortex->i_m_readdata_i[curr_bank][curr_word] = curr_value; - - } - } - } - else - { - if (vortex->o_m_valid_i) - { - - if (vortex->o_m_read_or_write_i) - { - // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); - unsigned base_addr = vortex->o_m_evict_addr_i; - - for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++) - { - for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++) - { - unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank; - unsigned curr_addr = base_addr + (4*curr_index); - - unsigned curr_value = vortex->o_m_writedata_i[curr_bank][curr_word]; - - ram.writeWord( curr_addr, &curr_value); - } - } - } - - // Respond next cycle - refill_i = true; - refill_addr_i = vortex->o_m_read_addr_i; - } + this->I_dram_req_vec[i].cycles_left -= 1; } + if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) + { + dequeue_index = i; + dequeue_valid = true; + } } + if (vortex->I_dram_req) + { + // std::cout << "Icache Dram Request received!\n"; + if (vortex->I_dram_req_read) + { + // std::cout << "Icache Dram Request is read!\n"; + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = vortex->I_dram_expected_lat; + dram_req.data_length = vortex->I_dram_req_size / 4; + dram_req.base_addr = vortex->I_dram_req_addr; + dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); + + for (int i = 0; i < dram_req.data_length; i++) + { + unsigned curr_addr = dram_req.base_addr + (i*4); + unsigned data_rd; + ram.getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; + this->I_dram_req_vec.push_back(dram_req); + } + + if (vortex->I_dram_req_write) + { + unsigned base_addr = vortex->I_dram_req_addr; + unsigned data_length = vortex->I_dram_req_size / 4; + + for (int i = 0; i < data_length; i++) + { + unsigned curr_addr = base_addr + (i*4); + unsigned data_wr = vortex->I_dram_req_data[i]; + ram.writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex->I_dram_fill_accept && dequeue_valid) + { + // std::cout << "Icache Dram Response Sending...!\n"; + + vortex->I_dram_fill_rsp = 1; + vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr; + // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; + + for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++) + { + vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i]; + } + free(this->I_dram_req_vec[dequeue_index].data); + + this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index); + } + else + { + vortex->I_dram_fill_rsp = 0; + vortex->I_dram_fill_rsp_addr = 0; + } + return false; } void Vortex::io_handler() { + // std::cout << "Checking\n"; if (vortex->io_valid) { uint32_t data_write = (uint32_t) vortex->io_data; - + // std::cout << "IO VALID!\n"; char c = (char) data_write; std::cerr << c; // std::cout << c; + + std::cout << std::flush; } } @@ -280,6 +303,7 @@ bool Vortex::dbus_driver() ram.getWord(curr_addr, &data_rd); dram_req.data[i] = data_rd; } + // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; this->dram_req_vec.push_back(dram_req); } @@ -301,6 +325,8 @@ bool Vortex::dbus_driver() { vortex->dram_fill_rsp = 1; vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; + // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; + for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) { vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; From b9a95631bc9666969b8ca172232c4d3deb3009c7 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 8 Mar 2020 14:04:55 -0700 Subject: [PATCH 33/66] Icache stage mods + removed shared memory --- rtl/VX_dmem_controller.v | 72 ++++++++++++++++++++-------------------- rtl/VX_icache_stage.v | 52 +++++++++++++++++++++-------- 2 files changed, 74 insertions(+), 50 deletions(-) diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 19b31caf..00a6aa37 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -25,45 +25,45 @@ module VX_dmem_controller ( wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}}; - wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; - wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read; - wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write; + // wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; + // wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read; + // wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write; - wire[`NT_M1:0][31:0] cache_driver_out_data; - wire[`NT_M1:0][31:0] sm_driver_out_data; - wire[`NT_M1:0] cache_driver_out_valid; // Not used for now - wire sm_delay; + // wire[`NT_M1:0][31:0] cache_driver_out_data; + // wire[`NT_M1:0][31:0] sm_driver_out_data; + // wire[`NT_M1:0] cache_driver_out_valid; // Not used for now + // wire sm_delay; - VX_shared_memory #( - .SM_SIZE (`SHARED_MEMORY_SIZE), - .SM_BANKS (`SHARED_MEMORY_BANKS), - .SM_BYTES_PER_READ (`SHARED_MEMORY_BYTES_PER_READ), - .SM_WORDS_PER_READ (`SHARED_MEMORY_WORDS_PER_READ), - .SM_LOG_WORDS_PER_READ (`SHARED_MEMORY_LOG_WORDS_PER_READ), - .SM_BANK_OFFSET_START (`SHARED_MEMORY_BANK_OFFSET_ST), - .SM_BANK_OFFSET_END (`SHARED_MEMORY_BANK_OFFSET_ED), - .SM_BLOCK_OFFSET_START (`SHARED_MEMORY_BLOCK_OFFSET_ST), - .SM_BLOCK_OFFSET_END (`SHARED_MEMORY_BLOCK_OFFSET_ED), - .SM_INDEX_START (`SHARED_MEMORY_INDEX_OFFSET_ST), - .SM_INDEX_END (`SHARED_MEMORY_INDEX_OFFSET_ED), - .SM_HEIGHT (`SHARED_MEMORY_HEIGHT), - .NUM_REQ (`SHARED_MEMORY_NUM_REQ), - .BITS_PER_BANK (`SHARED_MEMORY_BITS_PER_BANK) - ) - shared_memory - ( - .clk (clk), - .reset (reset), - .in_valid (sm_driver_in_valid), - .in_address(VX_dcache_req.core_req_addr), - .in_data (VX_dcache_req.core_req_writedata), - .mem_read (sm_driver_in_mem_read), - .mem_write (sm_driver_in_mem_write), - .out_valid (cache_driver_out_valid), - .out_data (sm_driver_out_data), - .stall (sm_delay) - ); + // VX_shared_memory #( + // .SM_SIZE (`SHARED_MEMORY_SIZE), + // .SM_BANKS (`SHARED_MEMORY_BANKS), + // .SM_BYTES_PER_READ (`SHARED_MEMORY_BYTES_PER_READ), + // .SM_WORDS_PER_READ (`SHARED_MEMORY_WORDS_PER_READ), + // .SM_LOG_WORDS_PER_READ (`SHARED_MEMORY_LOG_WORDS_PER_READ), + // .SM_BANK_OFFSET_START (`SHARED_MEMORY_BANK_OFFSET_ST), + // .SM_BANK_OFFSET_END (`SHARED_MEMORY_BANK_OFFSET_ED), + // .SM_BLOCK_OFFSET_START (`SHARED_MEMORY_BLOCK_OFFSET_ST), + // .SM_BLOCK_OFFSET_END (`SHARED_MEMORY_BLOCK_OFFSET_ED), + // .SM_INDEX_START (`SHARED_MEMORY_INDEX_OFFSET_ST), + // .SM_INDEX_END (`SHARED_MEMORY_INDEX_OFFSET_ED), + // .SM_HEIGHT (`SHARED_MEMORY_HEIGHT), + // .NUM_REQ (`SHARED_MEMORY_NUM_REQ), + // .BITS_PER_BANK (`SHARED_MEMORY_BITS_PER_BANK) + // ) + // shared_memory + // ( + // .clk (clk), + // .reset (reset), + // .in_valid (sm_driver_in_valid), + // .in_address(VX_dcache_req.core_req_addr), + // .in_data (VX_dcache_req.core_req_writedata), + // .mem_read (sm_driver_in_mem_read), + // .mem_write (sm_driver_in_mem_write), + // .out_valid (cache_driver_out_valid), + // .out_data (sm_driver_out_data), + // .stall (sm_delay) + // ); wire Dllvq_pop; diff --git a/rtl/VX_icache_stage.v b/rtl/VX_icache_stage.v index 54233e1b..373c11f7 100644 --- a/rtl/VX_icache_stage.v +++ b/rtl/VX_icache_stage.v @@ -3,34 +3,58 @@ module VX_icache_stage ( input wire clk, input wire reset, + input wire total_freeze, output wire icache_stage_delay, output wire[`NW_M1:0] icache_stage_wid, output wire[`NT-1:0] icache_stage_valids, VX_inst_meta_inter fe_inst_meta_fi, VX_inst_meta_inter fe_inst_meta_id, - VX_icache_response_inter icache_response, - VX_icache_request_inter icache_request + + VX_gpu_dcache_res_inter VX_icache_rsp, + VX_gpu_dcache_req_inter VX_icache_req ); + reg[`NT-1:0] threads_active[`NW-1:0]; + wire valid_inst = (|fe_inst_meta_fi.valid); - assign icache_request.pc_address = fe_inst_meta_fi.inst_pc; - assign icache_request.out_cache_driver_in_valid = fe_inst_meta_fi.valid != 0; - assign icache_request.out_cache_driver_in_mem_read = `LW_MEM_READ; - assign icache_request.out_cache_driver_in_mem_write = `NO_MEM_WRITE; - assign icache_request.out_cache_driver_in_data = 32'b0; + // Icache Request + assign VX_icache_req.core_req_valid = valid_inst && !total_freeze; + assign VX_icache_req.core_req_addr = fe_inst_meta_fi.inst_pc; + assign VX_icache_req.core_req_writedata = 32'b0; + assign VX_icache_req.core_req_mem_read = `LW_MEM_READ; + assign VX_icache_req.core_req_mem_write = `NO_MEM_WRITE; + assign VX_icache_req.core_req_rd = 5'b0; + assign VX_icache_req.core_req_wb = 2'b0; + assign VX_icache_req.core_req_warp_num = fe_inst_meta_fi.warp_num; + assign VX_icache_req.core_req_pc = fe_inst_meta_fi.inst_pc; + assign fe_inst_meta_id.instruction = VX_icache_rsp.core_wb_readdata[0][31:0]; + assign fe_inst_meta_id.inst_pc = VX_icache_rsp.core_wb_pc[0]; + assign fe_inst_meta_id.warp_num = VX_icache_rsp.core_wb_warp_num; + assign fe_inst_meta_id.valid = VX_icache_rsp.core_wb_valid ? threads_active[VX_icache_rsp.core_wb_warp_num] : 0; - assign icache_stage_delay = icache_response.delay; + assign icache_stage_wid = fe_inst_meta_id.warp_num; + assign icache_stage_valids = fe_inst_meta_id.valid & {`NT{!icache_stage_delay}}; - assign fe_inst_meta_id.instruction = (!valid_inst || icache_response.delay) ? 32'b0 : icache_response.instruction; - assign fe_inst_meta_id.inst_pc = fe_inst_meta_fi.inst_pc; - assign fe_inst_meta_id.warp_num = fe_inst_meta_fi.warp_num; - assign fe_inst_meta_id.valid = fe_inst_meta_fi.valid & {`NT{!icache_stage_delay}}; + // Cache can't accept request + assign icache_stage_delay = VX_icache_rsp.delay_req; + + // Core can't accept response + assign VX_icache_req.core_no_wb_slot = total_freeze; + + integer curr_w; + always @(posedge clk) begin + if (reset) begin + for (curr_w = 0; curr_w < `NW; curr_w=curr_w+1) threads_active[curr_w] <= 0; + end else begin + if (valid_inst && !icache_stage_delay) begin + threads_active[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid; + end + end + end - assign icache_stage_wid = fe_inst_meta_fi.warp_num; - assign icache_stage_valids = fe_inst_meta_fi.valid & {`NT{!icache_stage_delay}}; endmodule \ No newline at end of file From b5b04a707083091929e6724d0fee611e4f06472b Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 8 Mar 2020 15:00:53 -0700 Subject: [PATCH 34/66] Added Shared Memory --- rtl/VX_cache/VX_bank.v | 3 + rtl/VX_cache/VX_cache.v | 3 + rtl/VX_cache/VX_tag_data_access.v | 9 +- rtl/VX_cache/VX_tag_data_structure.v | 4 +- rtl/VX_define.v | 60 ++++++- rtl/VX_dmem_controller.v | 229 ++++++++++++++++++++------- 6 files changed, 239 insertions(+), 69 deletions(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index d2b24462..281f0ee8 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -14,6 +14,8 @@ module VX_bank parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -438,6 +440,7 @@ module VX_bank .WORD_SIZE_BYTES (WORD_SIZE_BYTES), .NUMBER_REQUESTS (NUMBER_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), + .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), .DFPQ_SIZE (DFPQ_SIZE), diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 855b0905..b9ef9373 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -14,6 +14,8 @@ module VX_cache parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -384,6 +386,7 @@ module VX_cache .WORD_SIZE_BYTES (WORD_SIZE_BYTES), .NUMBER_REQUESTS (NUMBER_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), + .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), .DFPQ_SIZE (DFPQ_SIZE), diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 71710636..d717e02c 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -14,6 +14,8 @@ module VX_tag_data_access parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -101,6 +103,7 @@ module VX_tag_data_access .WORD_SIZE_BYTES (WORD_SIZE_BYTES), .NUMBER_REQUESTS (NUMBER_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), + .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), .DFPQ_SIZE (DFPQ_SIZE), @@ -155,9 +158,9 @@ module VX_tag_data_access endgenerate - assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-2]; - assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-2]; - assign use_read_tag_st1e = read_tag_st1c [STAGE_1_CYCLES-2]; + assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-2] || (FUNC_ID == `SFUNC_ID); // If shared memory, always valid + assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-2] && (FUNC_ID == `DFUNC_ID); // Dirty only applies in Dcache + assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-2]; // Tag is always the same in SM genvar curr_w; for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-2][curr_w][31:0]; diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index d869f35e..de8544c5 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -14,7 +14,9 @@ module VX_tag_data_structure parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, - + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size diff --git a/rtl/VX_define.v b/rtl/VX_define.v index f9b9d9f5..ad2c1a96 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -228,6 +228,8 @@ `define DNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) `define DSTAGE_1_CYCLES 2 + // Function ID + `define DFUNC_ID 0 // Bank Number of words in a line `define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES) @@ -277,6 +279,8 @@ `define INUMBER_REQUESTS 1 // Number of cycles to complete stage 1 (read from memory) `define ISTAGE_1_CYCLES 2 + // Function ID + `define IFUNC_ID 1 // Bank Number of words in a line `define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES) @@ -286,7 +290,7 @@ // Core Request Queue Size `define IREQQ_SIZE `NW // Miss Reserv Queue Knob - `define IMRVQ_SIZE `DREQQ_SIZE + `define IMRVQ_SIZE `IREQQ_SIZE // Dram Fill Rsp Queue Size `define IDFPQ_SIZE 2 // Snoop Req Queue @@ -294,11 +298,11 @@ // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size - `define ICWBQ_SIZE `DREQQ_SIZE + `define ICWBQ_SIZE `IREQQ_SIZE // Dram Writeback Queue Size - `define IDWBQ_SIZE 4 + `define IDWBQ_SIZE 0 // Dram Fill Req Queue Size - `define IDFQQ_SIZE `DREQQ_SIZE + `define IDFQQ_SIZE `IREQQ_SIZE // Lower Level Cache Hit Queue Size `define ILLVQ_SIZE 0 @@ -310,7 +314,55 @@ // ========================================= Icache Configurable Knobs ========================================= +// ========================================= Icache Configurable Knobs ========================================= +// General Cache Knobs + // Size of cache in bytes + `define SCACHE_SIZE_BYTES 1024 + // Size of line inside a bank in bytes + `define SBANK_LINE_SIZE_BYTES 16 + // Number of banks {1, 2, 4, 8,...} + `define SNUMBER_BANKS 8 + // Size of a word in bytes + `define SWORD_SIZE_BYTES 4 + // Number of Word requests per cycle {1, 2, 4, 8, ...} + `define SNUMBER_REQUESTS 1 + // Number of cycles to complete stage 1 (read from memory) + `define SSTAGE_1_CYCLES 2 + // Function ID + `define SFUNC_ID 2 + + // Bank Number of words in a line + `define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES) + `define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0 +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + `define SREQQ_SIZE `NW + // Miss Reserv Queue Knob + `define SMRVQ_SIZE `SREQQ_SIZE + // Dram Fill Rsp Queue Size + `define SDFPQ_SIZE 0 + // Snoop Req Queue + `define SSNRQ_SIZE 0 + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + `define SCWBQ_SIZE `SREQQ_SIZE + // Dram Writeback Queue Size + `define SDWBQ_SIZE 0 + // Dram Fill Req Queue Size + `define SDFQQ_SIZE 0 + // Lower Level Cache Hit Queue Size + `define SLLVQ_SIZE 0 + + // Fill Invalidator Size {Fill invalidator must be active} + `define SFILL_INVALIDAOR_SIZE 16 + +// Dram knobs + `define SSIMULATED_DRAM_LATENCY_CYCLES 10 + +// ========================================= Icache Configurable Knobs ========================================= `endif diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 00a6aa37..29ba47dd 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -21,49 +21,148 @@ module VX_dmem_controller ( VX_gpu_dcache_req_inter VX_icache_req ); - wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; - wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}}; - - // wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; - // wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read; - // wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write; - - // wire[`NT_M1:0][31:0] cache_driver_out_data; - // wire[`NT_M1:0][31:0] sm_driver_out_data; - // wire[`NT_M1:0] cache_driver_out_valid; // Not used for now - // wire sm_delay; + VX_gpu_dcache_res_inter VX_dcache_rsp_smem(); + VX_gpu_dcache_req_inter VX_dcache_req_smem(); - // VX_shared_memory #( - // .SM_SIZE (`SHARED_MEMORY_SIZE), - // .SM_BANKS (`SHARED_MEMORY_BANKS), - // .SM_BYTES_PER_READ (`SHARED_MEMORY_BYTES_PER_READ), - // .SM_WORDS_PER_READ (`SHARED_MEMORY_WORDS_PER_READ), - // .SM_LOG_WORDS_PER_READ (`SHARED_MEMORY_LOG_WORDS_PER_READ), - // .SM_BANK_OFFSET_START (`SHARED_MEMORY_BANK_OFFSET_ST), - // .SM_BANK_OFFSET_END (`SHARED_MEMORY_BANK_OFFSET_ED), - // .SM_BLOCK_OFFSET_START (`SHARED_MEMORY_BLOCK_OFFSET_ST), - // .SM_BLOCK_OFFSET_END (`SHARED_MEMORY_BLOCK_OFFSET_ED), - // .SM_INDEX_START (`SHARED_MEMORY_INDEX_OFFSET_ST), - // .SM_INDEX_END (`SHARED_MEMORY_INDEX_OFFSET_ED), - // .SM_HEIGHT (`SHARED_MEMORY_HEIGHT), - // .NUM_REQ (`SHARED_MEMORY_NUM_REQ), - // .BITS_PER_BANK (`SHARED_MEMORY_BITS_PER_BANK) - // ) - // shared_memory - // ( - // .clk (clk), - // .reset (reset), - // .in_valid (sm_driver_in_valid), - // .in_address(VX_dcache_req.core_req_addr), - // .in_data (VX_dcache_req.core_req_writedata), - // .mem_read (sm_driver_in_mem_read), - // .mem_write (sm_driver_in_mem_write), - // .out_valid (cache_driver_out_valid), - // .out_data (sm_driver_out_data), - // .stall (sm_delay) - // ); + VX_gpu_dcache_res_inter VX_dcache_rsp_dcache(); + VX_gpu_dcache_req_inter VX_dcache_req_dcache(); + + + wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; + wire dcache_wants_wb = (|VX_dcache_rsp_dcache.core_wb_valid); + + // Dcache Request + assign VX_dcache_req_dcache.core_req_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}}; + assign VX_dcache_req_dcache.core_req_addr = VX_dcache_req.core_req_addr; + assign VX_dcache_req_dcache.core_req_writedata = VX_dcache_req.core_req_writedata; + assign VX_dcache_req_dcache.core_req_mem_read = VX_dcache_req.core_req_mem_read; + assign VX_dcache_req_dcache.core_req_mem_write = VX_dcache_req.core_req_mem_write; + assign VX_dcache_req_dcache.core_req_rd = VX_dcache_req.core_req_rd; + assign VX_dcache_req_dcache.core_req_wb = VX_dcache_req.core_req_wb; + assign VX_dcache_req_dcache.core_req_warp_num = VX_dcache_req.core_req_warp_num; + assign VX_dcache_req_dcache.core_req_pc = VX_dcache_req.core_req_pc; + assign VX_dcache_req_dcache.core_no_wb_slot = VX_dcache_req.core_no_wb_slot; + + + // Shred Memory Request + assign VX_dcache_req_smem.core_req_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; + assign VX_dcache_req_smem.core_req_addr = VX_dcache_req.core_req_addr; + assign VX_dcache_req_smem.core_req_writedata = VX_dcache_req.core_req_writedata; + assign VX_dcache_req_smem.core_req_mem_read = VX_dcache_req.core_req_mem_read; + assign VX_dcache_req_smem.core_req_mem_write = VX_dcache_req.core_req_mem_write; + assign VX_dcache_req_smem.core_req_rd = VX_dcache_req.core_req_rd; + assign VX_dcache_req_smem.core_req_wb = VX_dcache_req.core_req_wb; + assign VX_dcache_req_smem.core_req_warp_num = VX_dcache_req.core_req_warp_num; + assign VX_dcache_req_smem.core_req_pc = VX_dcache_req.core_req_pc; + assign VX_dcache_req_smem.core_no_wb_slot = VX_dcache_req.core_no_wb_slot || dcache_wants_wb; + + + // Dcache Response + assign VX_dcache_rsp.core_wb_valid = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_valid : VX_dcache_rsp_smem.core_wb_valid; + assign VX_dcache_rsp.core_wb_req_rd = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_req_rd : VX_dcache_rsp_smem.core_wb_req_rd; + assign VX_dcache_rsp.core_wb_req_wb = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_req_wb : VX_dcache_rsp_smem.core_wb_req_wb; + assign VX_dcache_rsp.core_wb_warp_num = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_warp_num : VX_dcache_rsp_smem.core_wb_warp_num; + assign VX_dcache_rsp.core_wb_readdata = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_readdata : VX_dcache_rsp_smem.core_wb_readdata; + assign VX_dcache_rsp.core_wb_pc = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_pc : VX_dcache_rsp_smem.core_wb_pc; + + assign VX_dcache_rsp.delay_req = to_shm ? VX_dcache_rsp_smem.delay_req : VX_dcache_rsp_dcache.delay_req; + + + + + + wire Sllvq_pop; + wire[`DNUMBER_REQUESTS-1:0] Sllvq_valid; + wire[`DNUMBER_REQUESTS-1:0][31:0] Sllvq_res_addr; + wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Sllvq_res_data; + + VX_gpu_dcache_dram_req_inter VX_gpu_smem_dram_req(); + VX_gpu_dcache_dram_res_inter VX_gpu_smem_dram_res(); + + + + assign Sllvq_pop = 0; + VX_cache #( + .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`SBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`SNUMBER_BANKS), + .WORD_SIZE_BYTES (`SWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`SNUMBER_REQUESTS), + .STAGE_1_CYCLES (`SSTAGE_1_CYCLES), + .FUNC_ID (`SFUNC_ID), + .REQQ_SIZE (`SREQQ_SIZE), + .MRVQ_SIZE (`SMRVQ_SIZE), + .DFPQ_SIZE (`SDFPQ_SIZE), + .SNRQ_SIZE (`SSNRQ_SIZE), + .CWBQ_SIZE (`SCWBQ_SIZE), + .DWBQ_SIZE (`SDWBQ_SIZE), + .DFQQ_SIZE (`SDFQQ_SIZE), + .LLVQ_SIZE (`SLLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`SSIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_smem + ( + .clk (clk), + .reset (reset), + + // Core req + .core_req_valid (VX_dcache_req_smem.core_req_valid), + .core_req_addr (VX_dcache_req_smem.core_req_addr), + .core_req_writedata(VX_dcache_req_smem.core_req_writedata), + .core_req_mem_read (VX_dcache_req_smem.core_req_mem_read), + .core_req_mem_write(VX_dcache_req_smem.core_req_mem_write), + .core_req_rd (VX_dcache_req_smem.core_req_rd), + .core_req_wb (VX_dcache_req_smem.core_req_wb), + .core_req_warp_num (VX_dcache_req_smem.core_req_warp_num), + .core_req_pc (VX_dcache_req_smem.core_req_pc), + + // Delay Core Req + .delay_req (VX_dcache_rsp_smem.delay_req), + + // Core Cache Can't WB + .core_no_wb_slot (VX_dcache_req_smem.core_no_wb_slot), + + // Cache CWB + .core_wb_valid (VX_dcache_rsp_smem.core_wb_valid), + .core_wb_req_rd (VX_dcache_rsp_smem.core_wb_req_rd), + .core_wb_req_wb (VX_dcache_rsp_smem.core_wb_req_wb), + .core_wb_warp_num (VX_dcache_rsp_smem.core_wb_warp_num), + .core_wb_readdata (VX_dcache_rsp_smem.core_wb_readdata), + .core_wb_pc (VX_dcache_rsp_smem.core_wb_pc), + + // DRAM response + .dram_fill_rsp (VX_gpu_smem_dram_res.dram_fill_rsp), + .dram_fill_rsp_addr(VX_gpu_smem_dram_res.dram_fill_rsp_addr), + .dram_fill_rsp_data(VX_gpu_smem_dram_res.dram_fill_rsp_data), + + // DRAM accept response + .dram_fill_accept (VX_gpu_smem_dram_req.dram_fill_accept), + + // DRAM Req + .dram_req (VX_gpu_smem_dram_req.dram_req), + .dram_req_write (VX_gpu_smem_dram_req.dram_req_write), + .dram_req_read (VX_gpu_smem_dram_req.dram_req_read), + .dram_req_addr (VX_gpu_smem_dram_req.dram_req_addr), + .dram_req_size (VX_gpu_smem_dram_req.dram_req_size), + .dram_req_data (VX_gpu_smem_dram_req.dram_req_data), + + // Snoop Response + .dram_req_because_of_wb(VX_gpu_smem_dram_req.dram_because_of_snp), + .dram_snp_full (VX_gpu_smem_dram_req.dram_snp_full), + + // Snoop Request + .snp_req (0), + .snp_req_addr (0), + + // LLVQ stuff + .llvq_pop (Sllvq_pop), + .llvq_valid (Sllvq_valid), + .llvq_res_addr (Sllvq_res_addr), + .llvq_res_data (Sllvq_res_data) + ); wire Dllvq_pop; @@ -71,6 +170,7 @@ module VX_dmem_controller ( wire[`DNUMBER_REQUESTS-1:0][31:0] Dllvq_res_addr; wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Dllvq_res_data; + assign Dllvq_pop = 0; VX_cache #( .CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES), @@ -79,6 +179,7 @@ module VX_dmem_controller ( .WORD_SIZE_BYTES (`DWORD_SIZE_BYTES), .NUMBER_REQUESTS (`DNUMBER_REQUESTS), .STAGE_1_CYCLES (`DSTAGE_1_CYCLES), + .FUNC_ID (`DFUNC_ID), .REQQ_SIZE (`DREQQ_SIZE), .MRVQ_SIZE (`DMRVQ_SIZE), .DFPQ_SIZE (`DDFPQ_SIZE), @@ -96,29 +197,29 @@ module VX_dmem_controller ( .reset (reset), // Core req - .core_req_valid (cache_driver_in_valid), - .core_req_addr (VX_dcache_req.core_req_addr), - .core_req_writedata(VX_dcache_req.core_req_writedata), - .core_req_mem_read (VX_dcache_req.core_req_mem_read), - .core_req_mem_write(VX_dcache_req.core_req_mem_write), - .core_req_rd (VX_dcache_req.core_req_rd), - .core_req_wb (VX_dcache_req.core_req_wb), - .core_req_warp_num (VX_dcache_req.core_req_warp_num), - .core_req_pc (VX_dcache_req.core_req_pc), + .core_req_valid (VX_dcache_req_dcache.core_req_valid), + .core_req_addr (VX_dcache_req_dcache.core_req_addr), + .core_req_writedata(VX_dcache_req_dcache.core_req_writedata), + .core_req_mem_read (VX_dcache_req_dcache.core_req_mem_read), + .core_req_mem_write(VX_dcache_req_dcache.core_req_mem_write), + .core_req_rd (VX_dcache_req_dcache.core_req_rd), + .core_req_wb (VX_dcache_req_dcache.core_req_wb), + .core_req_warp_num (VX_dcache_req_dcache.core_req_warp_num), + .core_req_pc (VX_dcache_req_dcache.core_req_pc), // Delay Core Req - .delay_req (VX_dcache_rsp.delay_req), + .delay_req (VX_dcache_rsp_dcache.delay_req), // Core Cache Can't WB - .core_no_wb_slot (VX_dcache_req.core_no_wb_slot), + .core_no_wb_slot (VX_dcache_req_dcache.core_no_wb_slot), // Cache CWB - .core_wb_valid (VX_dcache_rsp.core_wb_valid), - .core_wb_req_rd (VX_dcache_rsp.core_wb_req_rd), - .core_wb_req_wb (VX_dcache_rsp.core_wb_req_wb), - .core_wb_warp_num (VX_dcache_rsp.core_wb_warp_num), - .core_wb_readdata (VX_dcache_rsp.core_wb_readdata), - .core_wb_pc (VX_dcache_rsp.core_wb_pc), + .core_wb_valid (VX_dcache_rsp_dcache.core_wb_valid), + .core_wb_req_rd (VX_dcache_rsp_dcache.core_wb_req_rd), + .core_wb_req_wb (VX_dcache_rsp_dcache.core_wb_req_wb), + .core_wb_warp_num (VX_dcache_rsp_dcache.core_wb_warp_num), + .core_wb_readdata (VX_dcache_rsp_dcache.core_wb_readdata), + .core_wb_pc (VX_dcache_rsp_dcache.core_wb_pc), // DRAM response .dram_fill_rsp (VX_gpu_dcache_dram_res.dram_fill_rsp), @@ -153,6 +254,11 @@ module VX_dmem_controller ( + wire Illvq_pop; + wire[`DNUMBER_REQUESTS-1:0] Illvq_valid; + wire[`DNUMBER_REQUESTS-1:0][31:0] Illvq_res_addr; + wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Illvq_res_data; + assign Illvq_pop = 0; VX_cache #( .CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`IBANK_LINE_SIZE_BYTES), @@ -160,6 +266,7 @@ module VX_dmem_controller ( .WORD_SIZE_BYTES (`IWORD_SIZE_BYTES), .NUMBER_REQUESTS (`INUMBER_REQUESTS), .STAGE_1_CYCLES (`ISTAGE_1_CYCLES), + .FUNC_ID (`IFUNC_ID), .REQQ_SIZE (`IREQQ_SIZE), .MRVQ_SIZE (`IMRVQ_SIZE), .DFPQ_SIZE (`IDFPQ_SIZE), @@ -226,10 +333,10 @@ module VX_dmem_controller ( .snp_req_addr (0), // LLVQ stuff - .llvq_pop (Dllvq_pop), - .llvq_valid (Dllvq_valid), - .llvq_res_addr (Dllvq_res_addr), - .llvq_res_data (Dllvq_res_data) + .llvq_pop (Illvq_pop), + .llvq_valid (Illvq_valid), + .llvq_res_addr (Illvq_res_addr), + .llvq_res_data (Illvq_res_data) ); From a539630a0aadf331e118eeafd2d0e203a1f32cd5 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 8 Mar 2020 15:24:21 -0700 Subject: [PATCH 35/66] Added Vortex SOC --- rtl/Makefile | 19 +- rtl/Vortex_SOC.v | 88 ++++++ rtl/simulate/multi_test_bench.cpp | 112 +++++++ rtl/simulate/multi_test_bench.h | 481 ++++++++++++++++++++++++++++++ 4 files changed, 696 insertions(+), 4 deletions(-) create mode 100644 rtl/Vortex_SOC.v create mode 100644 rtl/simulate/multi_test_bench.cpp create mode 100644 rtl/simulate/multi_test_bench.h diff --git a/rtl/Makefile b/rtl/Makefile index 5fb2eb5b..b0dcdf6f 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -3,9 +3,11 @@ all: RUNFILE INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate -FILE=Vortex.v +SINGLE_CORE=Vortex.v +MULTI_CORE=Vortex_SOC.v EXE=--exe ./simulate/test_bench.cpp +MULTI_EXE=--exe ./simulate/multi_test_bench.cpp COMP=--compiler gcc @@ -24,18 +26,24 @@ DEB=--trace --prof-cfuncs -DVL_DEBUG=1 MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) +MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) + # -LDFLAGS '-lsystemc' VERILATOR: echo "#define VCD_OFF" > simulate/tb_debug.h - verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW) + verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW) VERILATORnoWarnings: echo "#define VCD_OFF" > simulate/tb_debug.h - verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB) + verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB) + +VERILATORMULTInoWarnings: + echo "#define VCD_OFF" > simulate/tb_debug.h + verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) $(CF) $(WNO) $(DEB) compdebug: echo "#define VCD_OUTPUT" > simulate/tb_debug.h - verilator_bin_dbg $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) + verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) RUNFILE: VERILATOR $(MAKECPP) @@ -46,6 +54,9 @@ debug: compdebug w: VERILATORnoWarnings $(MAKECPP) +multicore: VERILATORMULTInoWarnings + $(MAKEMULTICPP) + run: w (cd obj_dir && ./VVortex) diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v new file mode 100644 index 00000000..56f50f36 --- /dev/null +++ b/rtl/Vortex_SOC.v @@ -0,0 +1,88 @@ +`include "VX_define.v" +`include "VX_cache_config.v" + +module Vortex_SOC ( + input wire clk, + input wire reset, + input wire[31:0] icache_response_instruction, + output wire[31:0] icache_request_pc_address, + // IO + output wire io_valid, + output wire[31:0] io_data, + + // DRAM Dcache Req + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] dram_expected_lat, + + // DRAM Dcache Res + output wire dram_fill_accept, + input wire dram_fill_rsp, + input wire [31:0] dram_fill_rsp_addr, + input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + + + // DRAM Icache Req + output wire I_dram_req, + output wire I_dram_req_write, + output wire I_dram_req_read, + output wire [31:0] I_dram_req_addr, + output wire [31:0] I_dram_req_size, + output wire [31:0] I_dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] I_dram_expected_lat, + + // DRAM Icache Res + output wire I_dram_fill_accept, + input wire I_dram_fill_rsp, + input wire [31:0] I_dram_fill_rsp_addr, + input wire [31:0] I_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + + + output wire out_ebreak + ); + + + Vortex vortex_core( + .clk (clk), + .reset (reset), + .icache_response_instruction(icache_response_instruction), + .icache_request_pc_address (icache_request_pc_address), + .io_valid (io_valid), + .io_data (io_data), + .dram_req (dram_req), + .dram_req_write (dram_req_write), + .dram_req_read (dram_req_read), + .dram_req_addr (dram_req_addr), + .dram_req_size (dram_req_size), + .dram_req_data (dram_req_data), + .dram_expected_lat (dram_expected_lat), + .dram_fill_accept (dram_fill_accept), + .dram_fill_rsp (dram_fill_rsp), + .dram_fill_rsp_addr (dram_fill_rsp_addr), + .dram_fill_rsp_data (dram_fill_rsp_data), + .I_dram_req (I_dram_req), + .I_dram_req_write (I_dram_req_write), + .I_dram_req_read (I_dram_req_read), + .I_dram_req_addr (I_dram_req_addr), + .I_dram_req_size (I_dram_req_size), + .I_dram_req_data (I_dram_req_data), + .I_dram_expected_lat (I_dram_expected_lat), + .I_dram_fill_accept (I_dram_fill_accept), + .I_dram_fill_rsp (I_dram_fill_rsp), + .I_dram_fill_rsp_addr (I_dram_fill_rsp_addr), + .I_dram_fill_rsp_data (I_dram_fill_rsp_data), + .out_ebreak (out_ebreak) + ); + + + + + + + + +endmodule \ No newline at end of file diff --git a/rtl/simulate/multi_test_bench.cpp b/rtl/simulate/multi_test_bench.cpp new file mode 100644 index 00000000..6da0928e --- /dev/null +++ b/rtl/simulate/multi_test_bench.cpp @@ -0,0 +1,112 @@ +#include "multi_test_bench.h" + +#define NUM_TESTS 46 + +int main(int argc, char **argv) +{ + + // Verilated::debug(1); + + Verilated::commandArgs(argc, argv); + + Verilated::traceEverOn(true); + + +// #define ALL_TESTS +#ifdef ALL_TESTS + bool passed = true; + std::string tests[NUM_TESTS] = { + "../../emulator/riscv_tests/rv32ui-p-add.hex", + "../../emulator/riscv_tests/rv32ui-p-addi.hex", + "../../emulator/riscv_tests/rv32ui-p-and.hex", + "../../emulator/riscv_tests/rv32ui-p-andi.hex", + "../../emulator/riscv_tests/rv32ui-p-auipc.hex", + "../../emulator/riscv_tests/rv32ui-p-beq.hex", + "../../emulator/riscv_tests/rv32ui-p-bge.hex", + "../../emulator/riscv_tests/rv32ui-p-bgeu.hex", + "../../emulator/riscv_tests/rv32ui-p-blt.hex", + "../../emulator/riscv_tests/rv32ui-p-bltu.hex", + "../../emulator/riscv_tests/rv32ui-p-bne.hex", + "../../emulator/riscv_tests/rv32ui-p-jal.hex", + "../../emulator/riscv_tests/rv32ui-p-jalr.hex", + "../../emulator/riscv_tests/rv32ui-p-lw.hex", + "../../emulator/riscv_tests/rv32ui-p-lb.hex", + "../../emulator/riscv_tests/rv32ui-p-lbu.hex", + "../../emulator/riscv_tests/rv32ui-p-lh.hex", + "../../emulator/riscv_tests/rv32ui-p-lhu.hex", + "../../emulator/riscv_tests/rv32ui-p-lui.hex", + "../../emulator/riscv_tests/rv32ui-p-or.hex", + "../../emulator/riscv_tests/rv32ui-p-ori.hex", + "../../emulator/riscv_tests/rv32ui-p-sb.hex", + "../../emulator/riscv_tests/rv32ui-p-sh.hex", + "../../emulator/riscv_tests/rv32ui-p-simple.hex", + "../../emulator/riscv_tests/rv32ui-p-sll.hex", + "../../emulator/riscv_tests/rv32ui-p-slli.hex", + "../../emulator/riscv_tests/rv32ui-p-slt.hex", + "../../emulator/riscv_tests/rv32ui-p-slti.hex", + "../../emulator/riscv_tests/rv32ui-p-sltiu.hex", + "../../emulator/riscv_tests/rv32ui-p-sltu.hex", + "../../emulator/riscv_tests/rv32ui-p-sra.hex", + "../../emulator/riscv_tests/rv32ui-p-srai.hex", + "../../emulator/riscv_tests/rv32ui-p-srl.hex", + "../../emulator/riscv_tests/rv32ui-p-srli.hex", + "../../emulator/riscv_tests/rv32ui-p-sub.hex", + "../../emulator/riscv_tests/rv32ui-p-sw.hex", + "../../emulator/riscv_tests/rv32ui-p-xor.hex", + "../../emulator/riscv_tests/rv32ui-p-xori.hex", + "../../emulator/riscv_tests/rv32um-p-div.hex", + "../../emulator/riscv_tests/rv32um-p-divu.hex", + "../../emulator/riscv_tests/rv32um-p-mul.hex", + "../../emulator/riscv_tests/rv32um-p-mulh.hex", + "../../emulator/riscv_tests/rv32um-p-mulhsu.hex", + "../../emulator/riscv_tests/rv32um-p-mulhu.hex", + "../../emulator/riscv_tests/rv32um-p-rem.hex", + "../../emulator/riscv_tests/rv32um-p-remu.hex" + }; + + for (std::string s : tests) { + Vortex v; + + std::cerr << DEFAULT << "\n---------------------------------------\n"; + + std::cerr << s << std::endl; + + bool curr = v.simulate(s); + if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl; + if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl; + std::cerr << DEFAULT; + passed = passed && curr; + } + + std::cerr << DEFAULT << "\n***************************************\n"; + + if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n"; + if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n"; + + return !passed; + + #else + + char testing[] = "../../runtime/mains/simple/vx_simple_main.hex"; + // char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex"; + // char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; + Vortex v; + // const char *testing; + + // if (argc >= 2) { + // testing = argv[1]; + // } else { + // testing = "../../kernel/vortex_test.hex"; + // } + + std::cerr << testing << std::endl; + + + bool curr = v.simulate(testing); + if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; + if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; + + return !curr; + +#endif +} diff --git a/rtl/simulate/multi_test_bench.h b/rtl/simulate/multi_test_bench.h new file mode 100644 index 00000000..06850e5a --- /dev/null +++ b/rtl/simulate/multi_test_bench.h @@ -0,0 +1,481 @@ +// C++ libraries +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "VX_define.h" +#include "ram.h" +#include "VVortex_SOC.h" +#include "verilated.h" + +#include "tb_debug.h" + +#ifdef VCD_OUTPUT +#include +#endif + +unsigned long time_stamp = 0; + +double sc_time_stamp() +{ + return time_stamp / 1000.0; +} + +typedef struct +{ + int cycles_left; + int data_length; + unsigned base_addr; + unsigned * data; +} dram_req_t; + +class Vortex +{ + public: + Vortex(); + ~Vortex(); + bool simulate(std::string); + private: + void ProcessFile(void); + void print_stats(bool = true); + bool ibus_driver(); + bool dbus_driver(); + void io_handler(); + + RAM ram; + + VVortex_SOC * vortex; + + unsigned start_pc; + bool refill_d; + unsigned refill_addr_d; + bool refill_i; + unsigned refill_addr_i; + long int curr_cycle; + bool stop; + bool unit_test; + std::string instruction_file_name; + std::ofstream results; + int stats_static_inst; + int stats_dynamic_inst; + int stats_total_cycles; + int stats_fwd_stalls; + int stats_branch_stalls; + int debug_state; + int ibus_state; + int dbus_state; + int debug_return; + int debug_wait_num; + int debug_inst_num; + int debug_end_wait; + int debug_debugAddr; + double stats_sim_time; + std::vector dram_req_vec; + std::vector I_dram_req_vec; + #ifdef VCD_OUTPUT + VerilatedVcdC *m_trace; + #endif +}; + + + +Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), + stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), + debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), + debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) +{ + this->vortex = new VVortex_SOC; + #ifdef VCD_OUTPUT + this->m_trace = new VerilatedVcdC; + this->vortex->trace(m_trace, 99); + this->m_trace->open("trace.vcd"); + #endif + this->results.open("../results.txt"); +} + +Vortex::~Vortex() +{ + #ifdef VCD_OUTPUT + m_trace->close(); + #endif + this->results.close(); + delete this->vortex; +} + + +void Vortex::ProcessFile(void) +{ + loadHexImpl(this->instruction_file_name.c_str(), &this->ram); +} + +void Vortex::print_stats(bool cycle_test) +{ + + if (cycle_test) + { + this->results << std::left; + // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; + this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; + this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; + this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } + else + { + this->results << std::left; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } + + + uint32_t status; + ram.getWord(0, &status); + + if (this->unit_test) + { + if (status == 1) + { + this->results << std::setw(24) << "# GRADE:" << "PASSING\n"; + } else + { + this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n"; + } + } + else + { + this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n"; + } + + this->stats_static_inst = 0; + this->stats_dynamic_inst = -1; + this->stats_total_cycles = 0; + this->stats_fwd_stalls = 0; + this->stats_branch_stalls = 0; + +} + +bool Vortex::ibus_driver() +{ + + // Iterate through each element, and get pop index + int dequeue_index = -1; + bool dequeue_valid = false; + for (int i = 0; i < this->I_dram_req_vec.size(); i++) + { + if (this->I_dram_req_vec[i].cycles_left > 0) + { + this->I_dram_req_vec[i].cycles_left -= 1; + } + + if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) + { + dequeue_index = i; + dequeue_valid = true; + } + } + + + if (vortex->I_dram_req) + { + // std::cout << "Icache Dram Request received!\n"; + if (vortex->I_dram_req_read) + { + // std::cout << "Icache Dram Request is read!\n"; + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = vortex->I_dram_expected_lat; + dram_req.data_length = vortex->I_dram_req_size / 4; + dram_req.base_addr = vortex->I_dram_req_addr; + dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); + + for (int i = 0; i < dram_req.data_length; i++) + { + unsigned curr_addr = dram_req.base_addr + (i*4); + unsigned data_rd; + ram.getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; + this->I_dram_req_vec.push_back(dram_req); + } + + if (vortex->I_dram_req_write) + { + unsigned base_addr = vortex->I_dram_req_addr; + unsigned data_length = vortex->I_dram_req_size / 4; + + for (int i = 0; i < data_length; i++) + { + unsigned curr_addr = base_addr + (i*4); + unsigned data_wr = vortex->I_dram_req_data[i]; + ram.writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex->I_dram_fill_accept && dequeue_valid) + { + // std::cout << "Icache Dram Response Sending...!\n"; + + vortex->I_dram_fill_rsp = 1; + vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr; + // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; + + for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++) + { + vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i]; + } + free(this->I_dram_req_vec[dequeue_index].data); + + this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index); + } + else + { + vortex->I_dram_fill_rsp = 0; + vortex->I_dram_fill_rsp_addr = 0; + } + + return false; + +} + +void Vortex::io_handler() +{ + // std::cout << "Checking\n"; + if (vortex->io_valid) + { + uint32_t data_write = (uint32_t) vortex->io_data; + // std::cout << "IO VALID!\n"; + char c = (char) data_write; + std::cerr << c; + // std::cout << c; + + std::cout << std::flush; + } +} + + +bool Vortex::dbus_driver() +{ + + // Iterate through each element, and get pop index + int dequeue_index = -1; + bool dequeue_valid = false; + for (int i = 0; i < this->dram_req_vec.size(); i++) + { + if (this->dram_req_vec[i].cycles_left > 0) + { + this->dram_req_vec[i].cycles_left -= 1; + } + + if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) + { + dequeue_index = i; + dequeue_valid = true; + } + } + + + if (vortex->dram_req) + { + if (vortex->dram_req_read) + { + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = vortex->dram_expected_lat; + dram_req.data_length = vortex->dram_req_size / 4; + dram_req.base_addr = vortex->dram_req_addr; + dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); + + for (int i = 0; i < dram_req.data_length; i++) + { + unsigned curr_addr = dram_req.base_addr + (i*4); + unsigned data_rd; + ram.getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; + this->dram_req_vec.push_back(dram_req); + } + + if (vortex->dram_req_write) + { + unsigned base_addr = vortex->dram_req_addr; + unsigned data_length = vortex->dram_req_size / 4; + + for (int i = 0; i < data_length; i++) + { + unsigned curr_addr = base_addr + (i*4); + unsigned data_wr = vortex->dram_req_data[i]; + ram.writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex->dram_fill_accept && dequeue_valid) + { + vortex->dram_fill_rsp = 1; + vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; + // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; + + for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) + { + vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; + } + free(this->dram_req_vec[dequeue_index].data); + + this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index); + } + else + { + vortex->dram_fill_rsp = 0; + vortex->dram_fill_rsp_addr = 0; + } + + return false; +} + + + +bool Vortex::simulate(std::string file_to_simulate) +{ + + this->instruction_file_name = file_to_simulate; + // this->results << "\n****************\t" << file_to_simulate << "\t****************\n"; + + this->ProcessFile(); + + // auto start_time = std::chrono::high_resolution_clock::now(); + + + static bool stop = false; + static int counter = 0; + counter = 0; + stop = false; + + // auto start_time = clock(); + + + // vortex->reset = 1; + + + // vortex->reset = 0; + + unsigned curr_inst; + unsigned new_PC; + + // while (this->stop && (!(stop && (counter > 5)))) + // { + + // // std::cout << "************* Cycle: " << cycle << "\n"; + // bool istop = ibus_driver(); + // bool dstop = !dbus_driver(); + + // vortex->clk = 1; + // vortex->eval(); + + + + // vortex->clk = 0; + // vortex->eval(); + + + // stop = istop && dstop; + + // if (stop) + // { + // counter++; + // } else + // { + // counter = 0; + // } + + // cycle++; + // } + + bool istop; + bool dstop; + bool cont = false; + // for (int i = 0; i < 500; i++) + + vortex->reset = 1; + vortex->clk = 0; + vortex->eval(); + // m_trace->dump(10); + vortex->reset = 1; + vortex->clk = 1; + vortex->eval(); + // m_trace->dump(11); + vortex->reset = 0; + vortex->clk = 0; + + // unsigned cycles; + counter = 0; + this->stats_total_cycles = 12; + while (this->stop && ((counter < 5))) + // while (this->stats_total_cycles < 10) + { + + // printf("-------------------------\n"); + // std::cout << "Counter: " << counter << "\n"; + // if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n"; + // dstop = !dbus_driver(); + #ifdef VCD_OUTPUT + m_trace->dump(2*this->stats_total_cycles); + #endif + vortex->clk = 1; + vortex->eval(); + istop = ibus_driver(); + dstop = !dbus_driver(); + io_handler(); + + #ifdef VCD_OUTPUT + m_trace->dump((2*this->stats_total_cycles)+1); + #endif + vortex->clk = 0; + vortex->eval(); + // stop = istop && dstop; + stop = vortex->out_ebreak; + + if (stop || cont) + // if (istop) + { + cont = true; + counter++; + } else + { + counter = 0; + } + + ++time_stamp; + ++stats_total_cycles; + } + + std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; + + int status = 0; + // int status = (unsigned int) vortex->Vortex_SOC__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf; + + // std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n"; + + // std::cout << "Something: " << result << '\n'; + + // uint32_t status; + // ram.getWord(0, &status); + + this->print_stats(); + + + + return (status == 1); + // return (1 == 1); +} From e2ffbcf14b1d2a01f12bbaa54d28a99549cd3ba5 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 9 Mar 2020 01:17:11 -0700 Subject: [PATCH 36/66] MULTICORE WITH L2 WORKING --- rtl/Makefile | 7 + rtl/VX_back_end.v | 8 +- rtl/VX_cache/VX_bank.v | 127 ++++---- rtl/VX_cache/VX_cache.v | 116 ++----- rtl/VX_cache/VX_cache_config.v | 22 +- rtl/VX_cache/VX_cache_core_req_bank_sel.v | 2 + rtl/VX_cache/VX_cache_dram_req_arb.v | 6 +- rtl/VX_cache/VX_cache_miss_resrv.v | 4 +- rtl/VX_cache/VX_cache_req_queue.v | 42 +-- rtl/VX_cache/VX_cache_wb_sel_merge.v | 14 +- rtl/VX_cache/VX_tag_data_access.v | 54 ++-- rtl/VX_cache/VX_tag_data_structure.v | 10 +- rtl/VX_csr_data.v | 3 + rtl/VX_csr_pipe.v | 18 +- rtl/VX_define.v | 155 ++++----- rtl/VX_dmem_controller.v | 60 +--- rtl/VX_generic_queue_ll.v | 4 +- rtl/VX_icache_stage.v | 7 +- rtl/VX_lsu.v | 6 +- rtl/VX_scheduler.v | 2 + rtl/VX_warp_scheduler.v | 3 +- rtl/Vortex.v | 116 ++++--- rtl/Vortex_SOC.v | 299 +++++++++++++++--- rtl/interfaces/VX_gpu_dcache_dram_res_inter.v | 4 +- rtl/interfaces/VX_gpu_dcache_req_inter.v | 6 +- rtl/simulate/multi_test_bench.h | 96 +----- runtime/intrinsics/vx_intrinsics.h | 2 + runtime/intrinsics/vx_intrinsics.s | 6 +- 28 files changed, 642 insertions(+), 557 deletions(-) diff --git a/rtl/Makefile b/rtl/Makefile index b0dcdf6f..44fabb61 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -45,6 +45,10 @@ compdebug: echo "#define VCD_OUTPUT" > simulate/tb_debug.h verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) +compdebugmulti: + echo "#define VCD_OUTPUT" > simulate/tb_debug.h + verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) + RUNFILE: VERILATOR $(MAKECPP) @@ -57,6 +61,9 @@ w: VERILATORnoWarnings multicore: VERILATORMULTInoWarnings $(MAKEMULTICPP) +dmulticore: compdebugmulti + $(MAKEMULTICPP) + run: w (cd obj_dir && ./VVortex) diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index cbdd452e..933e9a1d 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -1,6 +1,10 @@ `include "VX_define.v" -module VX_back_end ( +module VX_back_end + #( + parameter CORE_ID = 0 + ) + ( input wire clk, input wire reset, input wire schedule_delay, @@ -112,7 +116,7 @@ VX_gpgpu_inst VX_gpgpu_inst( // .VX_csr_wb (VX_csr_wb) // ); -VX_csr_pipe VX_csr_pipe( +VX_csr_pipe #(.CORE_ID(CORE_ID)) VX_csr_pipe( .clk (clk), .reset (reset), .no_slot_csr (no_slot_csr), diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 281f0ee8..92f3d81a 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -1,5 +1,5 @@ `include "VX_cache_config.v" - +`include "VX_define.v" module VX_bank #( // Size of cache in bytes @@ -54,13 +54,13 @@ module VX_bank input wire delay_req, input wire [NUMBER_REQUESTS-1:0] bank_valids, input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata, input wire [4:0] bank_rd, - input wire [1:0] bank_wb, + input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb, input wire [31:0] bank_pc, input wire [`NW_M1:0] bank_warp_num, - input wire [2:0] bank_mem_read, - input wire [2:0] bank_mem_write, + input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read, + input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write, output wire reqq_full, // Output Core WB @@ -70,8 +70,9 @@ module VX_bank output wire [4:0] bank_wb_rd, output wire [1:0] bank_wb_wb, output wire [`NW_M1:0] bank_wb_warp_num, - output wire [31:0] bank_wb_data, + output wire [`WORD_SIZE_RNG] bank_wb_data, output wire [31:0] bank_wb_pc, + output wire [31:0] bank_wb_address, // Dram Fill Requests output wire dram_fill_req, @@ -83,25 +84,18 @@ module VX_bank // Dram Fill Response input wire dram_fill_rsp, input wire [31:0] dram_fill_addr, - input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + input wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dram_fill_rsp_data, output wire dram_fill_accept, // Dram WB Requests input wire dram_wb_queue_pop, output wire dram_wb_req, output wire[31:0] dram_wb_req_addr, - output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data, + output wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dram_wb_req_data, // Snp Request input wire snp_req, - input wire[31:0] snp_req_addr, - - // Lower Level Cache Response - input wire llvq_pop, - output wire llvq_valid, - output wire[31:0] llvq_res_addr, - output wire[`BANK_LINE_SIZE_RNG][31:0] llvq_res_data, - output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_res_tid + input wire[31:0] snp_req_addr ); @@ -132,12 +126,12 @@ module VX_bank wire dfpq_empty; wire dfpq_full; wire[31:0] dfpq_addr_st0; - wire[`BANK_LINE_SIZE_RNG][31:0] dfpq_filldata_st0; + wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dfpq_filldata_st0; reg dfpq_hazard_st0; assign dram_fill_accept = !dfpq_full; - VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(DFPQ_SIZE)) dfp_queue( + VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*`WORD_SIZE)), .SIZE(DFPQ_SIZE)) dfp_queue( .clk (clk), .reset (reset), .push (dram_fill_rsp), @@ -155,7 +149,7 @@ module VX_bank wire reqq_req_st0; wire[`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0; wire [31:0] reqq_req_addr_st0; - wire [31:0] reqq_req_writeword_st0; + wire [`WORD_SIZE_RNG] reqq_req_writeword_st0; wire [4:0] reqq_req_rd_st0; wire [1:0] reqq_req_wb_st0; wire [`NW_M1:0] reqq_req_warp_num_st0; @@ -221,7 +215,7 @@ module VX_bank wire mrvq_valid_st0; wire[`vx_clog2(NUMBER_REQUESTS)-1:0] mrvq_tid_st0; wire [31:0] mrvq_addr_st0; - wire [31:0] mrvq_writeword_st0; + wire [`WORD_SIZE_RNG] mrvq_writeword_st0; wire [4:0] mrvq_rd_st0; wire [1:0] mrvq_wb_st0; wire [31:0] miss_resrv_pc_st0; @@ -232,7 +226,7 @@ module VX_bank wire miss_add; wire[31:0] miss_add_addr; - wire[31:0] miss_add_data; + wire[`WORD_SIZE_RNG] miss_add_data; wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid; wire[4:0] miss_add_rd; wire[1:0] miss_add_wb; @@ -311,8 +305,8 @@ module VX_bank assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0; assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0; - assign reqq_pop = !mrvq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe; - assign snrq_pop = !reqq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0; + assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe; + assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0; integer st1_cycle; @@ -338,8 +332,8 @@ module VX_bank wire qual_is_fill_st0; wire qual_valid_st0; wire [31:0] qual_addr_st0; - wire [31:0] qual_writeword_st0; - wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0; + wire [`WORD_SIZE_RNG] qual_writeword_st0; + wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] qual_writedata_st0; wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0; wire qual_going_to_write_st0; wire qual_is_snp; @@ -348,14 +342,21 @@ module VX_bank wire valid_st1 [STAGE_1_CYCLES-1:0]; wire going_to_write_st1[STAGE_1_CYCLES-1:0]; wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0]; - wire [31:0] writeword_st1 [STAGE_1_CYCLES-1:0]; + wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0]; wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; wire is_fill_st1 [STAGE_1_CYCLES-1:0]; - wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [STAGE_1_CYCLES-1:0]; + wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0]; wire is_snp_st1 [STAGE_1_CYCLES-1:0]; wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0]; assign qual_is_fill_st0 = dfpq_pop; + + // always @(*) begin + // if (qual_is_fill_st0 && (FUNC_ID == 3)) begin + // $display("WHAT THE FUCK FUNC_ID: %x", FUNC_ID); + // end + // end + assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop; assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 : @@ -364,11 +365,7 @@ module VX_bank snrq_pop ? snrq_addr_st0 : 0; - assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 : - reqq_pop ? reqq_req_writeword_st0 : - 0; - - assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0; + assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 57; assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } : reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} : @@ -387,7 +384,11 @@ module VX_bank 32'h0; assign qual_is_snp = snrq_pop ? 1 : 0; - VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1 + 32)) s0_1_c0 ( + assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 : + reqq_pop ? reqq_req_writeword_st0 : + 0; + + VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_c0 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), @@ -399,7 +400,7 @@ module VX_bank genvar curr_stage; generate for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin - VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1 + 32)) s0_1_cc ( + VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), @@ -411,8 +412,8 @@ module VX_bank endgenerate - wire[31:0] readword_st1e; - wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e; + wire[`WORD_SIZE_RNG] readword_st1e; + wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st1e; wire[`TAG_SELECT_SIZE_RNG] readtag_st1e; wire miss_st1e; wire dirty_st1e; @@ -424,7 +425,7 @@ module VX_bank wire [`NW_M1:0] warp_num_st1e; wire [2:0] mem_read_st1e; wire [2:0] mem_write_st1e; - wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e; + wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e; wire fill_saw_dirty_st1e; wire is_snp_st1e; @@ -486,9 +487,9 @@ module VX_bank wire valid_st2; wire[31:0] addr_st2; - wire[31:0] writeword_st2; - wire[31:0] readword_st2; - wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st2; + wire[`WORD_SIZE_RNG] writeword_st2; + wire[`WORD_SIZE_RNG] readword_st2; + wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st2; wire miss_st2; wire dirty_st2; wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2; @@ -498,18 +499,19 @@ module VX_bank wire is_snp_st2; wire [31:0] pc_st2; - VX_generic_register #(.N( 1 + 1 + 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32)) st_1e_2 ( + + VX_generic_register #(.N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_SIZE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2)) st_1e_2 ( .clk (clk), .reset(reset), .stall(stall_bank_pipe), .flush(0), - .in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, pc_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), - .out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 }) + .in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, pc_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}), + .out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 }) ); // Enqueue to miss reserv if it's a valid miss - assign miss_add = valid_st2 && miss_st2 && !stall_bank_pipe && !mrvq_full && !(dirty_st2 && dwbq_full); + assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (dram_fill_req && dram_fill_req_queue_full)); assign miss_add_pc = pc_st2; assign miss_add_addr = addr_st2; assign miss_add_data = writeword_st2; @@ -517,8 +519,8 @@ module VX_bank // Enqueue to CWB Queue - wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full & !llvq_full; - wire [31:0] cwbq_data = readword_st2; + wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)); + wire [`WORD_SIZE_RNG] cwbq_data = readword_st2; wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; wire [4:0] cwbq_rd = miss_add_rd; wire [1:0] cwbq_wb = miss_add_wb; @@ -528,15 +530,15 @@ module VX_bank wire cwbq_full; wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; - VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue( + VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue( .clk (clk), .reset (reset), .push (cwbq_push), - .in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc}), + .in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}), .pop (bank_wb_pop), - .out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data, bank_wb_pc}), + .out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data, bank_wb_pc, bank_wb_address}), .empty (cwbq_empty), .full (cwbq_full) ); @@ -544,7 +546,7 @@ module VX_bank // Enqueue to DWB Queue wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !(!fill_saw_dirty_st2 && mrvq_full); wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK; - wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2; + wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2; wire dwbq_empty; wire dwbq_full; @@ -588,7 +590,7 @@ module VX_bank assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK; assign dram_wb_req = !dwbq_empty; - VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(DWBQ_SIZE)) dwb_queue( + VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_SIZE_WORDS * `WORD_SIZE)), .SIZE(DWBQ_SIZE)) dwb_queue( .clk (clk), .reset (reset), @@ -602,29 +604,8 @@ module VX_bank ); - // Lower Cache Hit - wire llvq_empty; - wire llvq_full; - wire llvq_push = valid_st2 && !miss_st2 && !llvq_full && !cwbq_full; - wire[`BANK_LINE_SIZE_RNG][31:0] llvq_push_data = readdata_st2; - wire[31:0] llvq_addr = addr_st2; - wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid; - assign llvq_valid = !llvq_empty; - - VX_generic_queue_ll #(.DATAW(`vx_clog2(NUMBER_REQUESTS) + 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(LLVQ_SIZE)) llv_queue( - .clk (clk), - .reset (reset), - .push (llvq_push), - .in_data ({llvq_tid , llvq_addr , llvq_push_data}), - .pop (llvq_pop), - .out_data({llvq_res_tid, llvq_res_addr, llvq_res_data}), - .empty (llvq_empty), - .full (llvq_full) - ); - - - assign stall_bank_pipe = (cwbq_push && cwbq_full) || (llvq_push && llvq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full); + assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full); endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index b9ef9373..3ca9b52a 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -9,13 +9,13 @@ module VX_cache // Number of banks {1, 2, 4, 8,...} parameter NUMBER_BANKS = 8, // Size of a word in bytes - parameter WORD_SIZE_BYTES = 4, + parameter WORD_SIZE_BYTES = 16, // Number of Word requests per cycle {1, 2, 4, 8, ...} parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} - parameter FUNC_ID = 0, + parameter FUNC_ID = 3, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -51,15 +51,15 @@ module VX_cache input wire reset, // Req Info - input wire [NUMBER_REQUESTS-1:0] core_req_valid, - input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr, - input wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata, - input wire[2:0] core_req_mem_read, - input wire[2:0] core_req_mem_write, + input wire [NUMBER_REQUESTS-1:0] core_req_valid, + input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr, + input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata, + input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_read, + input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_write, // Req meta input wire [4:0] core_req_rd, - input wire [1:0] core_req_wb, + input wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb, input wire [`NW_M1:0] core_req_warp_num, input wire [31:0] core_req_pc, output wire delay_req, @@ -70,14 +70,15 @@ module VX_cache output wire [4:0] core_wb_req_rd, output wire [1:0] core_wb_req_wb, output wire [`NW_M1:0] core_wb_warp_num, - output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, + output wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata, output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc, + output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_address, // Dram Fill Response input wire dram_fill_rsp, input wire [31:0] dram_fill_rsp_addr, - input wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + input wire [`IBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, output wire dram_fill_accept, // Dram request @@ -86,20 +87,14 @@ module VX_cache output wire dram_req_read, output wire [31:0] dram_req_addr, output wire [31:0] dram_req_size, - output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data, + output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data, output wire dram_req_because_of_wb, output wire dram_snp_full, // Snoop Req input wire snp_req, - input wire[31:0] snp_req_addr, - - // Lower Level Cache - input wire llvq_pop, - output wire[NUMBER_REQUESTS-1:0] llvq_valid, - output wire[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr, - output wire[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data + input wire[31:0] snp_req_addr ); @@ -111,8 +106,9 @@ module VX_cache wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; - wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_data; + wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data; wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc; + wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address; wire dfqq_full; @@ -124,54 +120,15 @@ module VX_cache wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req; wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp; wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; - wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; + wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] per_bank_dram_wb_req_data; wire[NUMBER_BANKS-1:0] per_bank_reqq_full; - - wire[NUMBER_BANKS-1:0] per_bank_llvq_pop; - wire[NUMBER_BANKS-1:0] per_bank_llvq_valid; - wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr; - wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data; - wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid; - assign delay_req = (|per_bank_reqq_full); assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; - - VX_dcache_llv_resp_bank_sel #( - .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), - .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (NUMBER_BANKS), - .WORD_SIZE_BYTES (WORD_SIZE_BYTES), - .NUMBER_REQUESTS (NUMBER_REQUESTS), - .STAGE_1_CYCLES (STAGE_1_CYCLES), - .REQQ_SIZE (REQQ_SIZE), - .MRVQ_SIZE (MRVQ_SIZE), - .DFPQ_SIZE (DFPQ_SIZE), - .SNRQ_SIZE (SNRQ_SIZE), - .CWBQ_SIZE (CWBQ_SIZE), - .DWBQ_SIZE (DWBQ_SIZE), - .DFQQ_SIZE (DFQQ_SIZE), - .LLVQ_SIZE (LLVQ_SIZE), - .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), - .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) - ) - VX_dcache_llv_resp_bank_sel - ( - .per_bank_llvq_pop (per_bank_llvq_pop), - .per_bank_llvq_valid (per_bank_llvq_valid), - .per_bank_llvq_res_addr(per_bank_llvq_res_addr), - .per_bank_llvq_res_data(per_bank_llvq_res_data), - .per_bank_llvq_res_tid (per_bank_llvq_res_tid), - .llvq_pop (llvq_pop), - .llvq_valid (llvq_valid), - .llvq_res_addr (llvq_res_addr), - .llvq_res_data (llvq_res_data) - ); - VX_cache_dram_req_arb #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), @@ -245,6 +202,7 @@ module VX_cache .WORD_SIZE_BYTES (WORD_SIZE_BYTES), .NUMBER_REQUESTS (NUMBER_REQUESTS), .STAGE_1_CYCLES (STAGE_1_CYCLES), + .FUNC_ID (FUNC_ID), .REQQ_SIZE (REQQ_SIZE), .MRVQ_SIZE (MRVQ_SIZE), .DFPQ_SIZE (DFPQ_SIZE), @@ -266,6 +224,7 @@ module VX_cache .per_bank_wb_warp_num(per_bank_wb_warp_num), .per_bank_wb_data (per_bank_wb_data), .per_bank_wb_pop (per_bank_wb_pop), + .per_bank_wb_address (per_bank_wb_address), .core_no_wb_slot (core_no_wb_slot), .core_wb_valid (core_wb_valid), @@ -273,6 +232,7 @@ module VX_cache .core_wb_req_wb (core_wb_req_wb), .core_wb_warp_num (core_wb_warp_num), .core_wb_readdata (core_wb_readdata), + .core_wb_address (core_wb_address), .core_wb_pc (core_wb_pc) ); @@ -281,12 +241,12 @@ module VX_cache for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin wire [NUMBER_REQUESTS-1:0] curr_bank_valids; wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; - wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; + wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata; wire [4:0] curr_bank_rd; - wire [1:0] curr_bank_wb; + wire [NUMBER_REQUESTS-1:0][1:0] curr_bank_wb; wire [`NW_M1:0] curr_bank_warp_num; - wire [2:0] curr_bank_mem_read; - wire [2:0] curr_bank_mem_write; + wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_read; + wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_write; wire [31:0] curr_bank_pc; wire curr_bank_wb_pop; @@ -296,11 +256,12 @@ module VX_cache wire [4:0] curr_bank_wb_rd; wire [1:0] curr_bank_wb_wb; wire [`NW_M1:0] curr_bank_wb_warp_num; - wire [31:0] curr_bank_wb_data; + wire [`WORD_SIZE_RNG] curr_bank_wb_data; + wire [31:0] curr_bank_wb_address; wire curr_bank_dram_fill_rsp; wire [31:0] curr_bank_dram_fill_rsp_addr; - wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data; + wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data; wire curr_bank_dram_fill_accept; wire curr_bank_dfqq_full; @@ -312,19 +273,13 @@ module VX_cache wire curr_bank_dram_wb_queue_pop; wire curr_bank_dram_wb_req; wire[31:0] curr_bank_dram_wb_req_addr; - wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data; + wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data; wire curr_bank_snp_req; wire[31:0] curr_bank_snp_req_addr; wire curr_bank_reqq_full; - - wire curr_bank_llvq_pop; - wire curr_bank_llvq_valid; - wire[31:0] curr_bank_llvq_res_addr; - wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_llvq_res_data; - wire[`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_llvq_res_tid; // Core Req @@ -348,6 +303,7 @@ module VX_cache assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num; assign per_bank_wb_data [curr_bank] = curr_bank_wb_data; assign per_bank_wb_pc [curr_bank] = curr_bank_wb_pc; + assign per_bank_wb_address [curr_bank] = curr_bank_wb_address; // Dram fill request assign curr_bank_dfqq_full = dfqq_full; @@ -370,14 +326,6 @@ module VX_cache // Snoop Request assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); assign curr_bank_snp_req_addr = snp_req_addr; - - - // LLVQ - assign curr_bank_llvq_pop = per_bank_llvq_pop[curr_bank]; - assign per_bank_llvq_valid[curr_bank] = curr_bank_llvq_valid; - assign per_bank_llvq_res_data[curr_bank] = curr_bank_llvq_res_data; - assign per_bank_llvq_res_addr[curr_bank] = curr_bank_llvq_res_addr; - assign per_bank_llvq_res_tid[curr_bank] = curr_bank_llvq_res_tid; VX_bank #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), @@ -424,6 +372,7 @@ module VX_cache .bank_wb_warp_num (curr_bank_wb_warp_num), .bank_wb_data (curr_bank_wb_data), .bank_wb_pc (curr_bank_wb_pc), + .bank_wb_address (curr_bank_wb_address), // Dram fill req .dram_fill_req (curr_bank_dram_fill_req), @@ -446,13 +395,8 @@ module VX_cache // Snoop Request .snp_req (curr_bank_snp_req), - .snp_req_addr (curr_bank_snp_req_addr), + .snp_req_addr (curr_bank_snp_req_addr) - .llvq_pop (curr_bank_llvq_pop), - .llvq_valid (curr_bank_llvq_valid), - .llvq_res_addr (curr_bank_llvq_res_addr), - .llvq_res_data (curr_bank_llvq_res_data), - .llvq_res_tid (curr_bank_llvq_res_tid) ); end diff --git a/rtl/VX_cache/VX_cache_config.v b/rtl/VX_cache/VX_cache_config.v index 68d80446..360b5352 100644 --- a/rtl/VX_cache/VX_cache_config.v +++ b/rtl/VX_cache/VX_cache_config.v @@ -4,12 +4,17 @@ `include "../VX_define.v" -// data tid rd wb warp_num read write -`define MRVQ_METADATA_SIZE (32 + $clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) +// data tid rd wb warp_num read write -`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + $clog2(NUMBER_REQUESTS)) -`define vx_clog2(value) $clog2(value) +`define vx_clog2(value) ((value == 1) ? 1 : $clog2(value)) + + +`define MRVQ_METADATA_SIZE (`WORD_SIZE + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3) + +// 5 + 2 + 4 + 3 + 3 + 1 +`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + `vx_clog2(NUMBER_REQUESTS)) + // `define vx_clog2_h(value, x) (value == (1 << x)) ? (x) // `define vx_clog2(value) (value == 0 ) ? 0 : \ @@ -46,6 +51,9 @@ // `vx_clog2_h(value, 31) : \ // 0 +`define WORD_SIZE (8*WORD_SIZE_BYTES) +`define WORD_SIZE_RNG (`WORD_SIZE)-1:0 + // 128 `define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUMBER_BANKS @@ -65,7 +73,7 @@ `define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0 // 2 -`define WORD_SELECT_NUM_BITS ($clog2(`BANK_LINE_SIZE_WORDS)) +`define WORD_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_SIZE_WORDS)) // 2 `define WORD_SELECT_SIZE_END (`WORD_SELECT_NUM_BITS) // 2 @@ -77,7 +85,7 @@ `define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0 // 3 -`define BANK_SELECT_NUM_BITS ($clog2(NUMBER_BANKS)) +`define BANK_SELECT_NUM_BITS (`vx_clog2(NUMBER_BANKS)) // 3 `define BANK_SELECT_SIZE_END (`BANK_SELECT_NUM_BITS) // 4 @@ -90,7 +98,7 @@ `define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0 // 3 -`define LINE_SELECT_NUM_BITS ($clog2(`BANK_LINE_COUNT)) +`define LINE_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_COUNT)) // 3 `define LINE_SELECT_SIZE_END (`LINE_SELECT_NUM_BITS) // 7 diff --git a/rtl/VX_cache/VX_cache_core_req_bank_sel.v b/rtl/VX_cache/VX_cache_core_req_bank_sel.v index cf47d063..e19531d1 100644 --- a/rtl/VX_cache/VX_cache_core_req_bank_sel.v +++ b/rtl/VX_cache/VX_cache_core_req_bank_sel.v @@ -15,6 +15,8 @@ module VX_cache_core_req_bank_sel parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} diff --git a/rtl/VX_cache/VX_cache_dram_req_arb.v b/rtl/VX_cache/VX_cache_dram_req_arb.v index b2cfab9a..119ea9ad 100644 --- a/rtl/VX_cache/VX_cache_dram_req_arb.v +++ b/rtl/VX_cache/VX_cache_dram_req_arb.v @@ -58,7 +58,7 @@ module VX_cache_dram_req_arb output wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop, input wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req, input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr, - input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data, + input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] per_bank_dram_wb_req_data, input wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp, // real Dram request @@ -67,7 +67,7 @@ module VX_cache_dram_req_arb output wire dram_req_read, output wire [31:0] dram_req_addr, output wire [31:0] dram_req_size, - output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data, + output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data, output wire dram_req_because_of_wb ); @@ -109,7 +109,7 @@ module VX_cache_dram_req_arb assign dram_req_read = dfqq_req && !dwb_valid; assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK; assign dram_req_size = BANK_LINE_SIZE_BYTES; - assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0; + assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0; assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0; endmodule \ No newline at end of file diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v index fcbd5ba7..3da09745 100644 --- a/rtl/VX_cache/VX_cache_miss_resrv.v +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -52,7 +52,7 @@ module VX_cache_miss_resrv // Miss enqueue input wire miss_add, input wire[31:0] miss_add_addr, - input wire[31:0] miss_add_data, + input wire[`WORD_SIZE_RNG] miss_add_data, input wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid, input wire[4:0] miss_add_rd, input wire[1:0] miss_add_wb, @@ -70,7 +70,7 @@ module VX_cache_miss_resrv input wire miss_resrv_pop, output wire miss_resrv_valid_st0, output wire[31:0] miss_resrv_addr_st0, - output wire[31:0] miss_resrv_data_st0, + output wire[`WORD_SIZE_RNG] miss_resrv_data_st0, output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, output wire[4:0] miss_resrv_rd_st0, output wire[1:0] miss_resrv_wb_st0, diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index d9c71294..937fa7fb 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -52,12 +52,12 @@ module VX_cache_req_queue input wire reqq_push, input wire [NUMBER_REQUESTS-1:0] bank_valids, input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr, - input wire [NUMBER_REQUESTS-1:0][31:0] bank_writedata, + input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata, input wire [4:0] bank_rd, - input wire [1:0] bank_wb, + input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb, input wire [`NW_M1:0] bank_warp_num, - input wire [2:0] bank_mem_read, - input wire [2:0] bank_mem_write, + input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read, + input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write, input wire [31:0] bank_pc, // Dequeue Data @@ -65,7 +65,7 @@ module VX_cache_req_queue output wire reqq_req_st0, output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0, output wire [31:0] reqq_req_addr_st0, - output wire [31:0] reqq_req_writedata_st0, + output wire [`WORD_SIZE_RNG] reqq_req_writedata_st0, output wire [4:0] reqq_req_rd_st0, output wire [1:0] reqq_req_wb_st0, output wire [`NW_M1:0] reqq_req_warp_num_st0, @@ -80,34 +80,34 @@ module VX_cache_req_queue wire [NUMBER_REQUESTS-1:0] out_per_valids; wire [NUMBER_REQUESTS-1:0][31:0] out_per_addr; - wire [NUMBER_REQUESTS-1:0][31:0] out_per_writedata; + wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] out_per_writedata; wire [4:0] out_per_rd; - wire [1:0] out_per_wb; + wire [NUMBER_REQUESTS-1:0][1:0] out_per_wb; wire [`NW_M1:0] out_per_warp_num; - wire [2:0] out_per_mem_read; - wire [2:0] out_per_mem_write; + wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_read; + wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_write; wire [31:0] out_per_pc; reg [NUMBER_REQUESTS-1:0] use_per_valids; reg [NUMBER_REQUESTS-1:0][31:0] use_per_addr; - reg [NUMBER_REQUESTS-1:0][31:0] use_per_writedata; + reg [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] use_per_writedata; reg [4:0] use_per_rd; - reg [1:0] use_per_wb; + reg [NUMBER_REQUESTS-1:0][1:0] use_per_wb; reg [31:0] use_per_pc; reg [`NW_M1:0] use_per_warp_num; - reg [2:0] use_per_mem_read; - reg [2:0] use_per_mem_write; + reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_read; + reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_write; wire [NUMBER_REQUESTS-1:0] qual_valids; wire [NUMBER_REQUESTS-1:0][31:0] qual_addr; - wire [NUMBER_REQUESTS-1:0][31:0] qual_writedata; + wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata; wire [4:0] qual_rd; - wire [1:0] qual_wb; + wire [NUMBER_REQUESTS-1:0][1:0] qual_wb; wire [`NW_M1:0] qual_warp_num; - wire [2:0] qual_mem_read; - wire [2:0] qual_mem_write; + wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_read; + wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_write; wire [31:0] qual_pc; wire[NUMBER_REQUESTS-1:0] updated_valids; @@ -120,7 +120,7 @@ module VX_cache_req_queue wire push_qual = reqq_push && !reqq_full; wire pop_qual = reqq_pop && use_empty && !out_empty; - VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 + 32 ), .SIZE(REQQ_SIZE)) reqq_queue( + VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUMBER_REQUESTS*2) + (`NW_M1+1) + (NUMBER_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue( .clk (clk), .reset (reset), .push (push_qual), @@ -158,10 +158,10 @@ module VX_cache_req_queue assign reqq_req_addr_st0 = qual_addr [qual_request_index]; assign reqq_req_writedata_st0 = qual_writedata[qual_request_index]; assign reqq_req_rd_st0 = qual_rd; - assign reqq_req_wb_st0 = qual_wb; + assign reqq_req_wb_st0 = qual_wb[qual_request_index]; assign reqq_req_warp_num_st0 = qual_warp_num; - assign reqq_req_mem_read_st0 = qual_mem_read; - assign reqq_req_mem_write_st0 = qual_mem_write; + assign reqq_req_mem_read_st0 = qual_mem_read [qual_request_index]; + assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index]; assign reqq_req_pc_st0 = qual_pc; assign updated_valids = qual_valids & (~(1 << qual_request_index)); diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v index 99c5d815..7199c483 100644 --- a/rtl/VX_cache/VX_cache_wb_sel_merge.v +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -14,6 +14,8 @@ module VX_cache_wb_sel_merge parameter NUMBER_REQUESTS = 2, // Number of cycles to complete stage 1 (read from memory) parameter STAGE_1_CYCLES = 2, + // Function ID, {Dcache=0, Icache=1, Sharedmemory=2} + parameter FUNC_ID = 0, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} @@ -52,19 +54,21 @@ module VX_cache_wb_sel_merge input wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, input wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, input wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, - input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_data, + input wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data, input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc, + input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address, output wire [NUMBER_BANKS-1:0] per_bank_wb_pop, // Core Writeback input wire core_no_wb_slot, output reg [NUMBER_REQUESTS-1:0] core_wb_valid, - output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata, + output reg [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata, output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_pc, output wire [4:0] core_wb_req_rd, output wire [1:0] core_wb_req_wb, - output wire [`NW_M1:0] core_wb_warp_num + output wire [`NW_M1:0] core_wb_warp_num, + output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_address ); @@ -99,11 +103,13 @@ module VX_cache_wb_sel_merge core_wb_valid = 0; core_wb_readdata = 0; core_wb_pc = 0; + core_wb_address = 0; for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin - if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin + if (((FUNC_ID == `LLFUNC_ID) && found_bank && per_bank_wb_valid[this_bank]) || (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index]))) begin core_wb_valid[per_bank_wb_tid[this_bank]] = 1; core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; + core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank]; per_bank_wb_pop_unqual[this_bank] = 1; end else begin per_bank_wb_pop_unqual[this_bank] = 0; diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index d717e02c..25f04692 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -58,13 +58,13 @@ module VX_tag_data_access input wire valid_req_st1e, input wire writefill_st1e, input wire[31:0] writeaddr_st1e, - input wire[31:0] writeword_st1e, - input wire[`BANK_LINE_SIZE_RNG][31:0] writedata_st1e, + input wire[`WORD_SIZE_RNG] writeword_st1e, + input wire[`DBANK_LINE_SIZE_RNG][31:0] writedata_st1e, input wire[2:0] mem_write_st1e, input wire[2:0] mem_read_st1e, - output wire[31:0] readword_st1e, - output wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e, + output wire[`WORD_SIZE_RNG] readword_st1e, + output wire[`DBANK_LINE_SIZE_RNG][31:0] readdata_st1e, output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e, output wire miss_st1e, output wire dirty_st1e, @@ -73,25 +73,25 @@ module VX_tag_data_access ); - reg[`BANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-2:0]; + reg[`DBANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-2:0]; reg read_valid_st1c[STAGE_1_CYCLES-2:0]; reg read_dirty_st1c[STAGE_1_CYCLES-2:0]; reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-2:0]; - reg[`BANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-2:0]; + reg[`DBANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-2:0]; wire qual_read_valid_st1; wire qual_read_dirty_st1; wire[`TAG_SELECT_SIZE_RNG] qual_read_tag_st1; - wire[`BANK_LINE_SIZE_RNG][31:0] qual_read_data_st1; + wire[`DBANK_LINE_SIZE_RNG][31:0] qual_read_data_st1; wire use_read_valid_st1e; wire use_read_dirty_st1e; wire[`TAG_SELECT_SIZE_RNG] use_read_tag_st1e; - wire[`BANK_LINE_SIZE_RNG][31:0] use_read_data_st1e; - wire[`BANK_LINE_SIZE_RNG][3:0] use_write_enable; - wire[`BANK_LINE_SIZE_RNG][31:0] use_write_data; + wire[`DBANK_LINE_SIZE_RNG][31:0] use_read_data_st1e; + wire[`DBANK_LINE_SIZE_RNG][3:0] use_write_enable; + wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data; wire fill_sent; @@ -134,7 +134,7 @@ module VX_tag_data_access .fill_sent (fill_sent) ); - VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_c0 ( + VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_c0 ( .clk (clk), .reset(reset), .stall(stall), @@ -146,7 +146,7 @@ module VX_tag_data_access genvar curr_stage; generate for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-2; curr_stage = curr_stage + 1) begin - VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`BANK_LINE_SIZE_WORDS*32) )) s0_1_cc ( + VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_cc ( .clk (clk), .reset(reset), .stall(stall), @@ -163,7 +163,7 @@ module VX_tag_data_access assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-2]; // Tag is always the same in SM genvar curr_w; - for (curr_w = 0; curr_w < `BANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-2][curr_w][31:0]; + for (curr_w = 0; curr_w < `DBANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-2][curr_w][31:0]; // assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-2]; /////////////////////// LOAD LOGIC /////////////////// @@ -202,14 +202,14 @@ module VX_tag_data_access wire[31:0] lw_data = (data_unQual); - wire[31:0] sw_data = writeword_st1e; + wire[31:0] sw_data = writeword_st1e[31:0]; wire[31:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} : b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} : b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} : - writeword_st1e; + writeword_st1e[31:0]; - wire[31:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e; + wire[31:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e[31:0]; @@ -236,20 +236,24 @@ module VX_tag_data_access wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e; wire force_write = writefill_st1e && valid_req_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e)); - wire[`BANK_LINE_SIZE_RNG][3:0] we; - wire[`BANK_LINE_SIZE_RNG][31:0] data_write; + wire[`DBANK_LINE_SIZE_RNG][3:0] we; + wire[`DBANK_LINE_SIZE_RNG][31:0] data_write; genvar g; generate - for (g = 0; g < `BANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables - wire normal_write = (block_offset == g) && should_write && !writefill_st1e; + for (g = 0; g < `DBANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables + wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !writefill_st1e; assign we[g] = (force_write) ? 4'b1111 : + (normal_write && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 : (normal_write && sw) ? 4'b1111 : (normal_write && sb) ? sb_mask : (normal_write && sh) ? sh_mask : 4'b0000; - assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat; + if (!(FUNC_ID == `LLFUNC_ID)) assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat; + end + if ((FUNC_ID == `LLFUNC_ID)) begin + assign data_write = force_write ? writedata_st1e : writeword_st1e; end endgenerate @@ -257,8 +261,12 @@ module VX_tag_data_access assign use_write_data = data_write; /////////////////////// - - assign readword_st1e = data_Qual; + if (FUNC_ID == `LLFUNC_ID) begin + assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-2]; + end else begin + assign readword_st1e = data_Qual; + end + assign miss_st1e = ((valid_req_st1e || is_snp_st1e) && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && !writefill_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)); assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e; assign readdata_st1e = use_read_data_st1e; diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index de8544c5..c7edb6a6 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -54,18 +54,18 @@ module VX_tag_data_structure output wire read_valid, output wire read_dirty, output wire[`TAG_SELECT_SIZE_RNG] read_tag, - output wire[`BANK_LINE_SIZE_RNG][31:0] read_data, + output wire[`DBANK_LINE_SIZE_RNG][31:0] read_data, input wire invalidate, - input wire[`BANK_LINE_SIZE_RNG][3:0] write_enable, + input wire[`DBANK_LINE_SIZE_RNG][3:0] write_enable, input wire write_fill, input wire[31:0] write_addr, - input wire[`BANK_LINE_SIZE_RNG][31:0] write_data, + input wire[`DBANK_LINE_SIZE_RNG][31:0] write_data, input wire fill_sent ); - reg[`BANK_LINE_SIZE_RNG][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; + reg[`DBANK_LINE_SIZE_RNG][3:0][7:0] data [`BANK_LINE_COUNT-1:0]; reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0]; reg valid[`BANK_LINE_COUNT-1:0]; reg dirty[`BANK_LINE_COUNT-1:0]; @@ -98,7 +98,7 @@ module VX_tag_data_structure valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; end - for (f = 0; f < `BANK_LINE_SIZE_WORDS; f = f + 1) begin + for (f = 0; f < `DBANK_LINE_SIZE_WORDS; f = f + 1) begin if (write_enable[f][0]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][0] <= write_data[f][7 :0 ]; if (write_enable[f][1]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][1] <= write_data[f][15:8 ]; if (write_enable[f][2]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][2] <= write_data[f][23:16]; diff --git a/rtl/VX_csr_data.v b/rtl/VX_csr_data.v index 6dc899a1..5fce2eb1 100644 --- a/rtl/VX_csr_data.v +++ b/rtl/VX_csr_data.v @@ -17,6 +17,8 @@ module VX_csr_data ( ); + /* verilator lint_off WIDTH */ + // wire[`NT_M1:0][31:0] thread_ids; // wire[`NT_M1:0][31:0] warp_ids; @@ -83,4 +85,5 @@ module VX_csr_data ( read_instreth ? instret[63:32] : {{20{1'b0}}, csr[in_read_csr_address]}; + /* verilator lint_on WIDTH */ endmodule : VX_csr_data diff --git a/rtl/VX_csr_pipe.v b/rtl/VX_csr_pipe.v index e9194f53..a04f51de 100644 --- a/rtl/VX_csr_pipe.v +++ b/rtl/VX_csr_pipe.v @@ -1,6 +1,10 @@ `include "VX_define.v" -module VX_csr_pipe ( +module VX_csr_pipe + #( + parameter CORE_ID = 0 + ) + ( input wire clk, // Clock input wire reset, input wire no_slot_csr, @@ -56,7 +60,7 @@ module VX_csr_pipe ( wire zero = 0; - VX_generic_register #(.N(`NT + `NW_M1 + 1 + 5 + 2 + 5 + 12 + 64)) csr_reg_s2 ( + VX_generic_register #(.N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_M1+1) + `NT)) csr_reg_s2 ( .clk (clk), .reset(reset), .stall(no_slot_csr), @@ -70,6 +74,7 @@ module VX_csr_pipe ( wire[`NT_M1:0][31:0] thread_ids; wire[`NT_M1:0][31:0] warp_ids; + wire[`NT_M1:0][31:0] warp_idz; wire[`NT_M1:0][31:0] csr_vec_read_data_s2; genvar cur_t; @@ -80,8 +85,11 @@ module VX_csr_pipe ( genvar cur_tw; for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, warp_num_s2}; + assign warp_idz[cur_tw] = (warp_num_s2 + (CORE_ID*`NW)); end + + genvar cur_v; for (cur_v = 0; cur_v < `NT; cur_v = cur_v + 1) begin assign csr_vec_read_data_s2[cur_v] = csr_read_data_s2; @@ -89,9 +97,11 @@ module VX_csr_pipe ( wire thread_select = csr_address_s2 == 12'h20; wire warp_select = csr_address_s2 == 12'h21; + wire warp_id_select = csr_address_s2 == 12'h22; - assign final_csr_data = thread_select ? thread_ids : - warp_select ? warp_ids : + assign final_csr_data = thread_select ? thread_ids : + warp_select ? warp_ids : + warp_id_select ? warp_idz : csr_vec_read_data_s2; diff --git a/rtl/VX_define.v b/rtl/VX_define.v index ad2c1a96..d1f23636 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -124,102 +124,17 @@ (x <= 1024) ? 10 : \ -199 -// `define PARAM - -// oooooo - -//Cache configurations -//Cache configurations - //Bytes -`define ICACHE_SIZE 4096 -`define ICACHE_WAYS 2 -//Bytes -`define ICACHE_BLOCK 64 -`define ICACHE_BANKS 4 -`define ICACHE_LOG_NUM_BANKS `CLOG2(`ICACHE_BANKS) - -`define ICACHE_NUM_WORDS_PER_BLOCK (`ICACHE_BLOCK / (`ICACHE_BANKS * 4)) -`define ICACHE_NUM_REQ 1 -`define ICACHE_LOG_NUM_REQ `CLOG2(`ICACHE_NUM_REQ) - - //set this to 1 if CACHE_WAYS is 1 -`define ICACHE_WAY_INDEX `CLOG2(`ICACHE_WAYS) -//`define ICACHE_WAY_INDEX 1 -`define ICACHE_BLOCK_PER_BANK (`ICACHE_BLOCK / `ICACHE_BANKS) - -// Offset -`define ICACHE_OFFSET_NB (`CLOG2(`ICACHE_NUM_WORDS_PER_BLOCK)) - -`define ICACHE_ADDR_OFFSET_ST (2+$clog2(`ICACHE_BANKS)) -`define ICACHE_ADDR_OFFSET_ED (`ICACHE_ADDR_OFFSET_ST+(`ICACHE_OFFSET_NB)-1) - - -`define ICACHE_ADDR_OFFSET_RNG `ICACHE_ADDR_OFFSET_ED:`ICACHE_ADDR_OFFSET_ST -`define ICACHE_OFFSET_SIZE_RNG (`CLOG2(`ICACHE_NUM_WORDS_PER_BLOCK)-1):0 -`define ICACHE_OFFSET_ST 0 -`define ICACHE_OFFSET_ED ($clog2(`ICACHE_NUM_WORDS_PER_BLOCK)-1) - -// Index -// `define ICACHE_NUM_IND (`ICACHE_SIZE / (`ICACHE_WAYS * `ICACHE_BLOCK_PER_BANK)) -`define ICACHE_NUM_IND (`ICACHE_SIZE / (`ICACHE_WAYS * `ICACHE_BLOCK)) -`define ICACHE_IND_NB ($clog2(`ICACHE_NUM_IND)) - -`define ICACHE_IND_ST (`ICACHE_ADDR_OFFSET_ED+1) -`define ICACHE_IND_ED (`ICACHE_IND_ST+`ICACHE_IND_NB-1) - -`define ICACHE_ADDR_IND_RNG `ICACHE_IND_ED:`ICACHE_IND_ST -`define ICACHE_IND_SIZE_RNG `ICACHE_IND_NB-1:0 - -`define ICACHE_IND_SIZE_START 0 -`define ICACHE_IND_SIZE_END `ICACHE_IND_NB-1 - - -// Tag -`define ICACHE_ADDR_TAG_RNG 31:(`ICACHE_IND_ED+1) -`define ICACHE_TAG_SIZE_RNG (32-(`ICACHE_IND_ED+1)-1):0 -`define ICACHE_TAG_SIZE_START 0 -`define ICACHE_TAG_SIZE_END (32-(`ICACHE_IND_ED+1)-1) -`define ICACHE_ADDR_TAG_START (`ICACHE_IND_ED+1) -`define ICACHE_ADDR_TAG_END 31 -`define ICACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`ICACHE_BLOCK-1)) - -/////// - -//`define SHARED_MEMORY_SIZE 4096 -`define SHARED_MEMORY_SIZE 8192 -`define SHARED_MEMORY_BANKS 4 -//`define SHARED_MEMORY_BYTES_PER_READ 16 -//`define SHARED_MEMORY_HEIGHT ((`SHARED_MEMORY_SIZE) / (`SHARED_MEMORY_BANKS * `SHARED_MEMORY_BYTES_PER_READ)) - -//`define SHARED_MEMORY_SIZE 16384 -//`define SHARED_MEMORY_BANKS 8 -`define SHARED_MEMORY_BYTES_PER_READ 16 -//`define SHARED_MEMORY_BITS_PER_BANK 3 -`define SHARED_MEMORY_BITS_PER_BANK `CLOG2(`SHARED_MEMORY_BANKS) -`define SHARED_MEMORY_NUM_REQ `NT -`define SHARED_MEMORY_WORDS_PER_READ (`SHARED_MEMORY_BYTES_PER_READ / 4) -`define SHARED_MEMORY_LOG_WORDS_PER_READ $clog2(`SHARED_MEMORY_WORDS_PER_READ) -`define SHARED_MEMORY_HEIGHT ((`SHARED_MEMORY_SIZE) / (`SHARED_MEMORY_BANKS * `SHARED_MEMORY_BYTES_PER_READ)) - -`define SHARED_MEMORY_BANK_OFFSET_ST (2) -`define SHARED_MEMORY_BANK_OFFSET_ED (2+$clog2(`SHARED_MEMORY_BANKS)-1) -`define SHARED_MEMORY_BLOCK_OFFSET_ST (`SHARED_MEMORY_BANK_OFFSET_ED + 1) -`define SHARED_MEMORY_BLOCK_OFFSET_ED (`SHARED_MEMORY_BLOCK_OFFSET_ST +`SHARED_MEMORY_LOG_WORDS_PER_READ-1) -`define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1) -`define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1) - - - - - +`define NUMBER_CORES 2 +// `define SINGLE_CORE_BENCH 0 +`define GLOBAL_BLOCK_SIZE_BYTES 16 // ========================================= Dcache Configurable Knobs ========================================= // General Cache Knobs // Size of cache in bytes `define DCACHE_SIZE_BYTES 1024 // Size of line inside a bank in bytes - `define DBANK_LINE_SIZE_BYTES 16 + `define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES // Number of banks {1, 2, 4, 8,...} `define DNUMBER_BANKS 8 // Size of a word in bytes @@ -270,7 +185,7 @@ // Size of cache in bytes `define ICACHE_SIZE_BYTES 1024 // Size of line inside a bank in bytes - `define IBANK_LINE_SIZE_BYTES 16 + `define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES // Number of banks {1, 2, 4, 8,...} `define INUMBER_BANKS 8 // Size of a word in bytes @@ -314,19 +229,19 @@ // ========================================= Icache Configurable Knobs ========================================= -// ========================================= Icache Configurable Knobs ========================================= +// ========================================= SM Configurable Knobs ========================================= // General Cache Knobs // Size of cache in bytes `define SCACHE_SIZE_BYTES 1024 // Size of line inside a bank in bytes - `define SBANK_LINE_SIZE_BYTES 16 + `define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES // Number of banks {1, 2, 4, 8,...} `define SNUMBER_BANKS 8 // Size of a word in bytes `define SWORD_SIZE_BYTES 4 // Number of Word requests per cycle {1, 2, 4, 8, ...} - `define SNUMBER_REQUESTS 1 + `define SNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) `define SSTAGE_1_CYCLES 2 // Function ID @@ -362,7 +277,59 @@ // Dram knobs `define SSIMULATED_DRAM_LATENCY_CYCLES 10 -// ========================================= Icache Configurable Knobs ========================================= +// ========================================= SM Configurable Knobs ========================================= + + + +// ========================================= L2cache Configurable Knobs ========================================= + +// General Cache Knobs + // Size of cache in bytes + `define LLCACHE_SIZE_BYTES 1024 + // Size of line inside a bank in bytes + `define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES + // Number of banks {1, 2, 4, 8,...} + `define LLNUMBER_BANKS 8 + // Size of a word in bytes + `define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) + // Number of Word requests per cycle {1, 2, 4, 8, ...} + `define LLNUMBER_REQUESTS (2*`NUMBER_CORES) + // Number of cycles to complete stage 1 (read from memory) + `define LLSTAGE_1_CYCLES 2 + // Function ID + `define LLFUNC_ID 3 + + // Bank Number of words in a line + `define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES) + `define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0 +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + `define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES) + // Miss Reserv Queue Knob + `define LLMRVQ_SIZE `LLREQQ_SIZE + // Dram Fill Rsp Queue Size + `define LLDFPQ_SIZE 2 + // Snoop Req Queue + `define LLSNRQ_SIZE 8 + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + `define LLCWBQ_SIZE `LLREQQ_SIZE + // Dram Writeback Queue Size + `define LLDWBQ_SIZE 4 + // Dram Fill Req Queue Size + `define LLDFQQ_SIZE `LLREQQ_SIZE + // Lower Level Cache Hit Queue Size + `define LLLLVQ_SIZE 0 + + // Fill Invalidator Size {Fill invalidator must be active} + `define LLFILL_INVALIDAOR_SIZE 16 + +// Dram knobs + `define LLSIMULATED_DRAM_LATENCY_CYCLES 10 + +// ========================================= L2cache Configurable Knobs ========================================= `endif diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 29ba47dd..4e1596b7 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -22,12 +22,12 @@ module VX_dmem_controller ( ); - VX_gpu_dcache_res_inter VX_dcache_rsp_smem(); - VX_gpu_dcache_req_inter VX_dcache_req_smem(); + VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp_smem(); + VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_smem(); - VX_gpu_dcache_res_inter VX_dcache_rsp_dcache(); - VX_gpu_dcache_req_inter VX_dcache_req_dcache(); + VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp_dcache(); + VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_dcache(); wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; @@ -71,19 +71,11 @@ module VX_dmem_controller ( - - - wire Sllvq_pop; - wire[`DNUMBER_REQUESTS-1:0] Sllvq_valid; - wire[`DNUMBER_REQUESTS-1:0][31:0] Sllvq_res_addr; - wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Sllvq_res_data; - - VX_gpu_dcache_dram_req_inter VX_gpu_smem_dram_req(); - VX_gpu_dcache_dram_res_inter VX_gpu_smem_dram_res(); + VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_smem_dram_req(); + VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_smem_dram_res(); - assign Sllvq_pop = 0; VX_cache #( .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`SBANK_LINE_SIZE_BYTES), @@ -132,6 +124,7 @@ module VX_dmem_controller ( .core_wb_warp_num (VX_dcache_rsp_smem.core_wb_warp_num), .core_wb_readdata (VX_dcache_rsp_smem.core_wb_readdata), .core_wb_pc (VX_dcache_rsp_smem.core_wb_pc), + .core_wb_address (), // DRAM response .dram_fill_rsp (VX_gpu_smem_dram_res.dram_fill_rsp), @@ -155,23 +148,9 @@ module VX_dmem_controller ( // Snoop Request .snp_req (0), - .snp_req_addr (0), - - // LLVQ stuff - .llvq_pop (Sllvq_pop), - .llvq_valid (Sllvq_valid), - .llvq_res_addr (Sllvq_res_addr), - .llvq_res_data (Sllvq_res_data) + .snp_req_addr (0) ); - - wire Dllvq_pop; - wire[`DNUMBER_REQUESTS-1:0] Dllvq_valid; - wire[`DNUMBER_REQUESTS-1:0][31:0] Dllvq_res_addr; - wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Dllvq_res_data; - - - assign Dllvq_pop = 0; VX_cache #( .CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`DBANK_LINE_SIZE_BYTES), @@ -220,6 +199,7 @@ module VX_dmem_controller ( .core_wb_warp_num (VX_dcache_rsp_dcache.core_wb_warp_num), .core_wb_readdata (VX_dcache_rsp_dcache.core_wb_readdata), .core_wb_pc (VX_dcache_rsp_dcache.core_wb_pc), + .core_wb_address (), // DRAM response .dram_fill_rsp (VX_gpu_dcache_dram_res.dram_fill_rsp), @@ -243,22 +223,11 @@ module VX_dmem_controller ( // Snoop Request .snp_req (0), - .snp_req_addr (0), - - // LLVQ stuff - .llvq_pop (Dllvq_pop), - .llvq_valid (Dllvq_valid), - .llvq_res_addr (Dllvq_res_addr), - .llvq_res_data (Dllvq_res_data) + .snp_req_addr (0) ); - wire Illvq_pop; - wire[`DNUMBER_REQUESTS-1:0] Illvq_valid; - wire[`DNUMBER_REQUESTS-1:0][31:0] Illvq_res_addr; - wire[`DNUMBER_REQUESTS-1:0][`DBANK_LINE_SIZE_RNG][31:0] Illvq_res_data; - assign Illvq_pop = 0; VX_cache #( .CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (`IBANK_LINE_SIZE_BYTES), @@ -307,6 +276,7 @@ module VX_dmem_controller ( .core_wb_warp_num (VX_icache_rsp.core_wb_warp_num), .core_wb_readdata (VX_icache_rsp.core_wb_readdata), .core_wb_pc (VX_icache_rsp.core_wb_pc), + .core_wb_address (), // DRAM response .dram_fill_rsp (VX_gpu_icache_dram_res.dram_fill_rsp), @@ -330,13 +300,7 @@ module VX_dmem_controller ( // Snoop Request .snp_req (0), - .snp_req_addr (0), - - // LLVQ stuff - .llvq_pop (Illvq_pop), - .llvq_valid (Illvq_valid), - .llvq_res_addr (Illvq_res_addr), - .llvq_res_data (Illvq_res_data) + .snp_req_addr (0) ); diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v index 4ffe34e6..dfe7828b 100644 --- a/rtl/VX_generic_queue_ll.v +++ b/rtl/VX_generic_queue_ll.v @@ -16,6 +16,8 @@ module VX_generic_queue_ll output wire full ); + /* verilator lint_off WIDTH */ + if (SIZE == 0) begin assign empty = 1; assign out_data = 0; @@ -117,6 +119,6 @@ module VX_generic_queue_ll end - + /* verilator lint_on WIDTH */ endmodule \ No newline at end of file diff --git a/rtl/VX_icache_stage.v b/rtl/VX_icache_stage.v index 373c11f7..1c8975d0 100644 --- a/rtl/VX_icache_stage.v +++ b/rtl/VX_icache_stage.v @@ -25,7 +25,7 @@ module VX_icache_stage ( assign VX_icache_req.core_req_mem_read = `LW_MEM_READ; assign VX_icache_req.core_req_mem_write = `NO_MEM_WRITE; assign VX_icache_req.core_req_rd = 5'b0; - assign VX_icache_req.core_req_wb = 2'b0; + assign VX_icache_req.core_req_wb = {1{2'b1}}; assign VX_icache_req.core_req_warp_num = fe_inst_meta_fi.warp_num; assign VX_icache_req.core_req_pc = fe_inst_meta_fi.inst_pc; @@ -33,7 +33,10 @@ module VX_icache_stage ( assign fe_inst_meta_id.instruction = VX_icache_rsp.core_wb_readdata[0][31:0]; assign fe_inst_meta_id.inst_pc = VX_icache_rsp.core_wb_pc[0]; assign fe_inst_meta_id.warp_num = VX_icache_rsp.core_wb_warp_num; + + /* verilator lint_off WIDTH */ assign fe_inst_meta_id.valid = VX_icache_rsp.core_wb_valid ? threads_active[VX_icache_rsp.core_wb_warp_num] : 0; + /* verilator lint_off WIDTH */ assign icache_stage_wid = fe_inst_meta_id.warp_num; assign icache_stage_valids = fe_inst_meta_id.valid & {`NT{!icache_stage_delay}}; @@ -50,7 +53,9 @@ module VX_icache_stage ( for (curr_w = 0; curr_w < `NW; curr_w=curr_w+1) threads_active[curr_w] <= 0; end else begin if (valid_inst && !icache_stage_delay) begin + /* verilator lint_off WIDTH */ threads_active[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid; + /* verilator lint_on WIDTH */ end end end diff --git a/rtl/VX_lsu.v b/rtl/VX_lsu.v index c8b7aeeb..b962b738 100644 --- a/rtl/VX_lsu.v +++ b/rtl/VX_lsu.v @@ -49,10 +49,10 @@ module VX_lsu ( assign VX_dcache_req.core_req_valid = use_valid; assign VX_dcache_req.core_req_addr = use_address; assign VX_dcache_req.core_req_writedata = use_store_data; - assign VX_dcache_req.core_req_mem_read = use_mem_read; - assign VX_dcache_req.core_req_mem_write = use_mem_write; + assign VX_dcache_req.core_req_mem_read = {`NT{use_mem_read}}; + assign VX_dcache_req.core_req_mem_write = {`NT{use_mem_write}}; assign VX_dcache_req.core_req_rd = use_rd; - assign VX_dcache_req.core_req_wb = use_wb; + assign VX_dcache_req.core_req_wb = {`NT{use_wb}}; assign VX_dcache_req.core_req_warp_num = use_warp_num; assign VX_dcache_req.core_req_pc = use_pc; diff --git a/rtl/VX_scheduler.v b/rtl/VX_scheduler.v index ed796e65..47e582a3 100644 --- a/rtl/VX_scheduler.v +++ b/rtl/VX_scheduler.v @@ -14,6 +14,7 @@ module VX_scheduler ( ); + /* verilator lint_off WIDTH */ reg[31:0] count_valid; assign is_empty = count_valid == 0; @@ -77,5 +78,6 @@ module VX_scheduler ( end end + /* verilator lint_on WIDTH */ endmodule \ No newline at end of file diff --git a/rtl/VX_warp_scheduler.v b/rtl/VX_warp_scheduler.v index 42014786..a976bcf0 100644 --- a/rtl/VX_warp_scheduler.v +++ b/rtl/VX_warp_scheduler.v @@ -61,6 +61,7 @@ module VX_warp_scheduler ( ); + /* verilator lint_off WIDTH */ wire update_use_wspawn; wire update_visible_active; @@ -334,6 +335,6 @@ module VX_warp_scheduler ( wire ebreak = (warp_active == 0); assign out_ebreak = ebreak; - + /* verilator lint_on WIDTH */ endmodule \ No newline at end of file diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 9fcf3028..862e7007 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -2,48 +2,92 @@ `include "VX_cache_config.v" module Vortex + #( + parameter CORE_ID = 0 + ) ( - input wire clk, - input wire reset, - input wire[31:0] icache_response_instruction, - output wire[31:0] icache_request_pc_address, - // IO - output wire io_valid, - output wire[31:0] io_data, - // DRAM Dcache Req - output wire dram_req, - output wire dram_req_write, - output wire dram_req_read, - output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, - output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], - output wire [31:0] dram_expected_lat, + `ifdef SINGLE_CORE_BENCH + input wire clk, + input wire reset, + // IO + output wire io_valid, + output wire[31:0] io_data, - // DRAM Dcache Res - output wire dram_fill_accept, - input wire dram_fill_rsp, - input wire [31:0] dram_fill_rsp_addr, - input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + // DRAM Dcache Req + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] dram_expected_lat, + + // DRAM Dcache Res + output wire dram_fill_accept, + input wire dram_fill_rsp, + input wire [31:0] dram_fill_rsp_addr, + input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], - // DRAM Icache Req - output wire I_dram_req, - output wire I_dram_req_write, - output wire I_dram_req_read, - output wire [31:0] I_dram_req_addr, - output wire [31:0] I_dram_req_size, - output wire [31:0] I_dram_req_data[`DBANK_LINE_SIZE_RNG], - output wire [31:0] I_dram_expected_lat, + // DRAM Icache Req + output wire I_dram_req, + output wire I_dram_req_write, + output wire I_dram_req_read, + output wire [31:0] I_dram_req_addr, + output wire [31:0] I_dram_req_size, + output wire [31:0] I_dram_req_data[`IBANK_LINE_SIZE_RNG], + output wire [31:0] I_dram_expected_lat, - // DRAM Icache Res - output wire I_dram_fill_accept, - input wire I_dram_fill_rsp, - input wire [31:0] I_dram_fill_rsp_addr, - input wire [31:0] I_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + // DRAM Icache Res + output wire I_dram_fill_accept, + input wire I_dram_fill_rsp, + input wire [31:0] I_dram_fill_rsp_addr, + input wire [31:0] I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG], - output wire out_ebreak + output wire out_ebreak + `else + input wire clk, + input wire reset, + // IO + output wire io_valid, + output wire[31:0] io_data, + + // DRAM Dcache Req + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data, + output wire [31:0] dram_expected_lat, + + // DRAM Dcache Res + output wire dram_fill_accept, + input wire dram_fill_rsp, + input wire [31:0] dram_fill_rsp_addr, + input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + + + // DRAM Icache Req + output wire I_dram_req, + output wire I_dram_req_write, + output wire I_dram_req_read, + output wire [31:0] I_dram_req_addr, + output wire [31:0] I_dram_req_size, + output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data, + output wire [31:0] I_dram_expected_lat, + + // DRAM Icache Res + output wire I_dram_fill_accept, + input wire I_dram_fill_rsp, + input wire [31:0] I_dram_fill_rsp_addr, + input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data, + + + output wire out_ebreak + `endif ); wire scheduler_empty; @@ -86,7 +130,7 @@ module Vortex end endgenerate - wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000); + wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write[0] != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000); wire[31:0] temp_io_data = VX_dcache_req.core_req_writedata[0]; assign io_valid = temp_io_valid; assign io_data = temp_io_data; @@ -172,7 +216,7 @@ VX_scheduler schedule( .is_empty (scheduler_empty) ); -VX_back_end vx_back_end( +VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end( .clk (clk), .reset (reset), .schedule_delay (schedule_delay), diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index 56f50f36..2305e55c 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -4,11 +4,11 @@ module Vortex_SOC ( input wire clk, input wire reset, - input wire[31:0] icache_response_instruction, - output wire[31:0] icache_request_pc_address, // IO - output wire io_valid, - output wire[31:0] io_data, + output wire io_valid[`NUMBER_CORES-1:0], + output wire[31:0] io_data [`NUMBER_CORES-1:0], + + output wire[31:0] number_cores, // DRAM Dcache Req output wire dram_req, @@ -26,61 +26,258 @@ module Vortex_SOC ( input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], - // DRAM Icache Req - output wire I_dram_req, - output wire I_dram_req_write, - output wire I_dram_req_read, - output wire [31:0] I_dram_req_addr, - output wire [31:0] I_dram_req_size, - output wire [31:0] I_dram_req_data[`DBANK_LINE_SIZE_RNG], - output wire [31:0] I_dram_expected_lat, - - // DRAM Icache Res - output wire I_dram_fill_accept, - input wire I_dram_fill_rsp, - input wire [31:0] I_dram_fill_rsp_addr, - input wire [31:0] I_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], - - output wire out_ebreak ); - Vortex vortex_core( - .clk (clk), - .reset (reset), - .icache_response_instruction(icache_response_instruction), - .icache_request_pc_address (icache_request_pc_address), - .io_valid (io_valid), - .io_data (io_data), - .dram_req (dram_req), - .dram_req_write (dram_req_write), - .dram_req_read (dram_req_read), - .dram_req_addr (dram_req_addr), - .dram_req_size (dram_req_size), - .dram_req_data (dram_req_data), - .dram_expected_lat (dram_expected_lat), - .dram_fill_accept (dram_fill_accept), - .dram_fill_rsp (dram_fill_rsp), - .dram_fill_rsp_addr (dram_fill_rsp_addr), - .dram_fill_rsp_data (dram_fill_rsp_data), - .I_dram_req (I_dram_req), - .I_dram_req_write (I_dram_req_write), - .I_dram_req_read (I_dram_req_read), - .I_dram_req_addr (I_dram_req_addr), - .I_dram_req_size (I_dram_req_size), - .I_dram_req_data (I_dram_req_data), - .I_dram_expected_lat (I_dram_expected_lat), - .I_dram_fill_accept (I_dram_fill_accept), - .I_dram_fill_rsp (I_dram_fill_rsp), - .I_dram_fill_rsp_addr (I_dram_fill_rsp_addr), - .I_dram_fill_rsp_data (I_dram_fill_rsp_data), - .out_ebreak (out_ebreak) + assign number_cores = `NUMBER_CORES; + + // IO + wire per_core_io_valid[`NUMBER_CORES-1:0]; + wire[31:0] per_core_io_data[`NUMBER_CORES-1:0]; + + // DRAM Dcache Req + wire[`NUMBER_CORES-1:0] per_core_dram_req; + wire[`NUMBER_CORES-1:0] per_core_dram_req_write; + wire[`NUMBER_CORES-1:0] per_core_dram_req_read; + wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_req_addr; + wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_req_size; + wire[`NUMBER_CORES-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data; + wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_expected_lat; + + // DRAM Dcache Res + wire[`NUMBER_CORES-1:0] per_core_dram_fill_accept; + wire[`NUMBER_CORES-1:0] per_core_dram_fill_rsp; + wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_fill_rsp_addr; + wire[`NUMBER_CORES-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data; + + + // DRAM Icache Req + wire[`NUMBER_CORES-1:0] per_core_I_dram_req; + wire[`NUMBER_CORES-1:0] per_core_I_dram_req_write; + wire[`NUMBER_CORES-1:0] per_core_I_dram_req_read; + wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_req_addr; + wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_req_size; + wire[`NUMBER_CORES-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data; + wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_expected_lat; + + // DRAM Icache Res + wire[`NUMBER_CORES-1:0] per_core_I_dram_fill_accept; + wire[`NUMBER_CORES-1:0] per_core_I_dram_fill_rsp; + wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_fill_rsp_addr; + wire[`NUMBER_CORES-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; + + // Out ebreak + wire[`NUMBER_CORES-1:0] per_core_out_ebreak; + + assign out_ebreak = (&per_core_out_ebreak); + + genvar curr_core; + generate + + for (curr_core = 0; curr_core < `NUMBER_CORES; curr_core=curr_core+1) begin + + wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data; + wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ; + + assign io_valid[curr_core] = per_core_io_valid[curr_core]; + assign io_data [curr_core] = per_core_io_data [curr_core]; + Vortex #(.CORE_ID(curr_core)) vortex_core( + .clk (clk), + .reset (reset), + .io_valid (per_core_io_valid [curr_core]), + .io_data (per_core_io_data [curr_core]), + .dram_req (per_core_dram_req [curr_core]), + .dram_req_write (per_core_dram_req_write [curr_core]), + .dram_req_read (per_core_dram_req_read [curr_core]), + .dram_req_addr (per_core_dram_req_addr [curr_core]), + .dram_req_size (per_core_dram_req_size [curr_core]), + .dram_req_data (curr_core_dram_req_data ), + .dram_expected_lat (per_core_dram_expected_lat [curr_core]), + .dram_fill_accept (per_core_dram_fill_accept [curr_core]), + .dram_fill_rsp (per_core_dram_fill_rsp [curr_core]), + .dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]), + .dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]), + .I_dram_req (per_core_I_dram_req [curr_core]), + .I_dram_req_write (per_core_I_dram_req_write [curr_core]), + .I_dram_req_read (per_core_I_dram_req_read [curr_core]), + .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), + .I_dram_req_size (per_core_I_dram_req_size [curr_core]), + .I_dram_req_data (curr_core_I_dram_req_data ), + .I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]), + .I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]), + .I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]), + .I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]), + .I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]), + .out_ebreak (per_core_out_ebreak [curr_core]) + ); + + assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; + assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data; + end + endgenerate + + + //////////////////// L2 Cache //////////////////// + wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req; + wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write; + wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read; + wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr; + wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data; + wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb; + + wire l2c_core_accept; + + + wire[`LLNUMBER_REQUESTS-1:0] l2c_wb; + wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr; + wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data; + + + wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port; + wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port; + + genvar llb_index; + generate + for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin + assign dram_req_data [llb_index] = dram_req_data_port[llb_index]; + assign dram_fill_rsp_data_port[llb_index] = dram_fill_rsp_data[llb_index]; + end + endgenerate + + // genvar l2c_index; + // genvar l2c_bank_index; + // generate + // for (l2c_index = 0; l2c_index < `LLNUMBER_REQUESTS; l2c_index=l2c_index+1) begin + // assign l2c_wb [l2c_index] = l2c_wb_port [l2c_index]; + // assign l2c_wb_addr[l2c_index] = l2c_wb_addr_port[l2c_index]; + // for (l2c_bank_index = 0; l2c_bank_index < `LLNUMBER_REQUESTS; l2c_bank_index=l2c_bank_index+1) begin + // assign l2c_wb_data[l2c_index][l2c_bank_index] = l2c_wb_data_port[l2c_index][l2c_bank_index]; + // end + // end + // endgenerate + + + + // + genvar l2c_curr_core; + generate + for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin + // Core Request + assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; + assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; + + assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write ? `SW_MEM_WRITE : `NO_MEM_WRITE; + assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write + + assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read ? `LW_MEM_READ : `NO_MEM_READ; + assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write + + assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read ? 1 : 0; + assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write + + assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)]; + assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)]; + + assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)]; + assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)]; + + // L2 can't accept requests + assign per_core_dram_fill_accept [(l2c_curr_core/2)] = l2c_core_accept; + assign per_core_I_dram_fill_accept[(l2c_curr_core/2)] = l2c_core_accept; + + // Cache Fill Response + assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; + assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; + + assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; + assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; + + assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; + assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; + end + endgenerate + + wire dram_snp_full; + wire dram_req_because_of_wb; + VX_cache #( + .CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`LLNUMBER_BANKS), + .WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`LLNUMBER_REQUESTS), + .STAGE_1_CYCLES (`LLSTAGE_1_CYCLES), + .FUNC_ID (`LLFUNC_ID), + .REQQ_SIZE (`LLREQQ_SIZE), + .MRVQ_SIZE (`LLMRVQ_SIZE), + .DFPQ_SIZE (`LLDFPQ_SIZE), + .SNRQ_SIZE (`LLSNRQ_SIZE), + .CWBQ_SIZE (`LLCWBQ_SIZE), + .DWBQ_SIZE (`LLDWBQ_SIZE), + .DFQQ_SIZE (`LLDFQQ_SIZE), + .LLVQ_SIZE (`LLLLVQ_SIZE), + .FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_l2cache + ( + .clk (clk), + .reset (reset), + + // Core Req (DRAM Fills/WB) To L2 Request + .core_req_valid (l2c_core_req), + .core_req_addr (l2c_core_req_addr), + .core_req_writedata({l2c_core_req_data}), + .core_req_mem_read (l2c_core_req_mem_read), + .core_req_mem_write(l2c_core_req_mem_write), + .core_req_rd (0), + .core_req_wb (l2c_core_req_wb), + .core_req_warp_num (0), + .core_req_pc (0), + + // L2 can't accept Core Request + .delay_req (l2c_core_accept), + + // Core can't accept L2 Request + .core_no_wb_slot (0), + + // Core Writeback + .core_wb_valid (l2c_wb), + .core_wb_req_rd (), + .core_wb_req_wb (), + .core_wb_warp_num (), + .core_wb_readdata ({l2c_wb_data}), + .core_wb_address (l2c_wb_addr), + .core_wb_pc (), + + // L2 Cache DRAM Fill response + .dram_fill_rsp (dram_fill_rsp), + .dram_fill_rsp_addr(dram_fill_rsp_addr), + .dram_fill_rsp_data({dram_fill_rsp_data_port}), + + // L2 Cache can't accept Fill Response + .dram_fill_accept (dram_fill_accept), + + // L2 Cache DRAM Fill Request + .dram_req (dram_req), + .dram_req_write (dram_req_write), + .dram_req_read (dram_req_read), + .dram_req_addr (dram_req_addr), + .dram_req_size (dram_req_size), + .dram_req_data ({dram_req_data_port}), + + // Snoop Response + .dram_req_because_of_wb(dram_req_because_of_wb), + .dram_snp_full (dram_snp_full), + + // Snoop Request + .snp_req (0), + .snp_req_addr (0) ); - + //////////////////// L2 Cache //////////////////// diff --git a/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v index a6bd0ff8..95364b5f 100644 --- a/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v @@ -13,8 +13,8 @@ interface VX_gpu_dcache_dram_res_inter ) (); // DRAM Rsponse - wire dram_fill_rsp; - wire [31:0] dram_fill_rsp_addr; + wire dram_fill_rsp; + wire [31:0] dram_fill_rsp_addr; wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_fill_rsp_data; endinterface diff --git a/rtl/interfaces/VX_gpu_dcache_req_inter.v b/rtl/interfaces/VX_gpu_dcache_req_inter.v index 83b507fd..108db514 100644 --- a/rtl/interfaces/VX_gpu_dcache_req_inter.v +++ b/rtl/interfaces/VX_gpu_dcache_req_inter.v @@ -16,10 +16,10 @@ interface VX_gpu_dcache_req_inter wire [NUMBER_REQUESTS-1:0] core_req_valid; wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr; wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata; - wire [2:0] core_req_mem_read; - wire [2:0] core_req_mem_write; + wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_read; + wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_write; wire [4:0] core_req_rd; - wire [1:0] core_req_wb; + wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb; wire [`NW_M1:0] core_req_warp_num; wire [31:0] core_req_pc; diff --git a/rtl/simulate/multi_test_bench.h b/rtl/simulate/multi_test_bench.h index 06850e5a..1b26b483 100644 --- a/rtl/simulate/multi_test_bench.h +++ b/rtl/simulate/multi_test_bench.h @@ -78,7 +78,6 @@ class Vortex int debug_debugAddr; double stats_sim_time; std::vector dram_req_vec; - std::vector I_dram_req_vec; #ifdef VCD_OUTPUT VerilatedVcdC *m_trace; #endif @@ -165,84 +164,6 @@ void Vortex::print_stats(bool cycle_test) bool Vortex::ibus_driver() { - - // Iterate through each element, and get pop index - int dequeue_index = -1; - bool dequeue_valid = false; - for (int i = 0; i < this->I_dram_req_vec.size(); i++) - { - if (this->I_dram_req_vec[i].cycles_left > 0) - { - this->I_dram_req_vec[i].cycles_left -= 1; - } - - if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) - { - dequeue_index = i; - dequeue_valid = true; - } - } - - - if (vortex->I_dram_req) - { - // std::cout << "Icache Dram Request received!\n"; - if (vortex->I_dram_req_read) - { - // std::cout << "Icache Dram Request is read!\n"; - // Need to add an element - dram_req_t dram_req; - dram_req.cycles_left = vortex->I_dram_expected_lat; - dram_req.data_length = vortex->I_dram_req_size / 4; - dram_req.base_addr = vortex->I_dram_req_addr; - dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); - - for (int i = 0; i < dram_req.data_length; i++) - { - unsigned curr_addr = dram_req.base_addr + (i*4); - unsigned data_rd; - ram.getWord(curr_addr, &data_rd); - dram_req.data[i] = data_rd; - } - // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; - this->I_dram_req_vec.push_back(dram_req); - } - - if (vortex->I_dram_req_write) - { - unsigned base_addr = vortex->I_dram_req_addr; - unsigned data_length = vortex->I_dram_req_size / 4; - - for (int i = 0; i < data_length; i++) - { - unsigned curr_addr = base_addr + (i*4); - unsigned data_wr = vortex->I_dram_req_data[i]; - ram.writeWord(curr_addr, &data_wr); - } - } - } - - if (vortex->I_dram_fill_accept && dequeue_valid) - { - // std::cout << "Icache Dram Response Sending...!\n"; - - vortex->I_dram_fill_rsp = 1; - vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr; - // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; - - for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++) - { - vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i]; - } - free(this->I_dram_req_vec[dequeue_index].data); - - this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index); - } - else - { - vortex->I_dram_fill_rsp = 0; - vortex->I_dram_fill_rsp_addr = 0; - } return false; @@ -251,15 +172,18 @@ bool Vortex::ibus_driver() void Vortex::io_handler() { // std::cout << "Checking\n"; - if (vortex->io_valid) + for (int c = 0; c < vortex->number_cores; c++) { - uint32_t data_write = (uint32_t) vortex->io_data; - // std::cout << "IO VALID!\n"; - char c = (char) data_write; - std::cerr << c; - // std::cout << c; + if (vortex->io_valid[c]) + { + uint32_t data_write = (uint32_t) vortex->io_data[c]; + // std::cout << "IO VALID!\n"; + char c = (char) data_write; + std::cerr << c; + // std::cout << c; - std::cout << std::flush; + std::cout << std::flush; + } } } diff --git a/runtime/intrinsics/vx_intrinsics.h b/runtime/intrinsics/vx_intrinsics.h index df85807a..e7e097a2 100644 --- a/runtime/intrinsics/vx_intrinsics.h +++ b/runtime/intrinsics/vx_intrinsics.h @@ -31,6 +31,8 @@ unsigned vx_threadID(void); // Get hardware warp ID unsigned vx_warpID(void); +unsigned vx_warpNum(void); + // Get Number cycles/Inst unsigned vx_getCycles(void); unsigned vx_getInst(void); diff --git a/runtime/intrinsics/vx_intrinsics.s b/runtime/intrinsics/vx_intrinsics.s index a9904840..5b328ee8 100644 --- a/runtime/intrinsics/vx_intrinsics.s +++ b/runtime/intrinsics/vx_intrinsics.s @@ -41,7 +41,11 @@ vx_join: vx_warpID: csrr a0, 0x21 # read warp IDs ret - +.type vx_warpNum, @function +.global vx_warpNum +vx_warpNum: + csrr a0, 0x22 # read warp IDs + ret .type vx_threadID, @function .global vx_threadID From cf0173ae15911c29851352619e95a973bba4a9d4 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 9 Mar 2020 22:08:46 -0700 Subject: [PATCH 37/66] Fixed Stall Pipeline Logic --- rtl/VX_cache/VX_bank.v | 18 +++++++--- rtl/VX_cache/VX_cache.v | 3 ++ rtl/VX_define.v | 71 ++++++++++++++++++++++++++++++++++++++-- rtl/VX_dmem_controller.v | 3 ++ rtl/Vortex_SOC.v | 1 + 5 files changed, 88 insertions(+), 8 deletions(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 92f3d81a..d61a0b9c 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -37,6 +37,8 @@ module VX_bank parameter DFQQ_SIZE = 8, // Lower Level Cache Hit Queue Size parameter LLVQ_SIZE = 16, + // Fill Forward SNP Queue + parameter FFSQ_SIZE = 8, // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, @@ -95,7 +97,10 @@ module VX_bank // Snp Request input wire snp_req, - input wire[31:0] snp_req_addr + input wire[31:0] snp_req_addr, + + output wire snp_fwd, + output wire[31:0] snp_fwd_addr ); @@ -511,7 +516,7 @@ module VX_bank // Enqueue to miss reserv if it's a valid miss - assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (dram_fill_req && dram_fill_req_queue_full)); + assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full)); assign miss_add_pc = pc_st2; assign miss_add_addr = addr_st2; assign miss_add_data = writeword_st2; @@ -519,7 +524,7 @@ module VX_bank // Enqueue to CWB Queue - wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)); + wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)) && !( (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); wire [`WORD_SIZE_RNG] cwbq_data = readword_st2; wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; wire [4:0] cwbq_rd = miss_add_rd; @@ -544,7 +549,7 @@ module VX_bank ); // Enqueue to DWB Queue - wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !(!fill_saw_dirty_st2 && mrvq_full); + wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK; wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2; wire dwbq_empty; @@ -603,9 +608,12 @@ module VX_bank .full (dwbq_full) ); + wire snp_fwd_push; + wire snp_fwd_pop; - assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full); + + assign stall_bank_pipe = ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full); endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 3ca9b52a..2c30a0b1 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -37,6 +37,8 @@ module VX_cache parameter DFQQ_SIZE = 8, // Lower Level Cache Hit Queue Size parameter LLVQ_SIZE = 16, + // Fill Forward SNP Queue + parameter FFSQ_SIZE = 8, // Fill Invalidator Size {Fill invalidator must be active} parameter FILL_INVALIDAOR_SIZE = 16, @@ -343,6 +345,7 @@ module VX_cache .DWBQ_SIZE (DWBQ_SIZE), .DFQQ_SIZE (DFQQ_SIZE), .LLVQ_SIZE (LLVQ_SIZE), + .FFSQ_SIZE (FFSQ_SIZE), .FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES) ) diff --git a/rtl/VX_define.v b/rtl/VX_define.v index d1f23636..45c6c375 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -125,7 +125,11 @@ -199 -`define NUMBER_CORES 2 + +`define NUMBER_CORES_PER_CLUSTERS (2) +`define NUMBER_CLUSTERS (1) +`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTERS*`NUMBER_CLUSTERS) + // `define SINGLE_CORE_BENCH 0 `define GLOBAL_BLOCK_SIZE_BYTES 16 // ========================================= Dcache Configurable Knobs ========================================= @@ -169,6 +173,8 @@ `define DDFQQ_SIZE `DREQQ_SIZE // Lower Level Cache Hit Queue Size `define DLLVQ_SIZE 0 + // Fill Forward SNP Queue + `define DFFSQ_SIZE 8 // Fill Invalidator Size {Fill invalidator must be active} `define DFILL_INVALIDAOR_SIZE 16 @@ -220,6 +226,8 @@ `define IDFQQ_SIZE `IREQQ_SIZE // Lower Level Cache Hit Queue Size `define ILLVQ_SIZE 0 + // Fill Forward SNP Queue + `define IFFSQ_SIZE 8 // Fill Invalidator Size {Fill invalidator must be active} `define IFILL_INVALIDAOR_SIZE 16 @@ -270,6 +278,8 @@ `define SDFQQ_SIZE 0 // Lower Level Cache Hit Queue Size `define SLLVQ_SIZE 0 + // Fill Forward SNP Queue + `define SFFSQ_SIZE 0 // Fill Invalidator Size {Fill invalidator must be active} `define SFILL_INVALIDAOR_SIZE 16 @@ -293,7 +303,7 @@ // Size of a word in bytes `define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) // Number of Word requests per cycle {1, 2, 4, 8, ...} - `define LLNUMBER_REQUESTS (2*`NUMBER_CORES) + `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTERS) // Number of cycles to complete stage 1 (read from memory) `define LLSTAGE_1_CYCLES 2 // Function ID @@ -305,7 +315,7 @@ // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size - `define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES) + `define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES_PER_CLUSTERS) // Miss Reserv Queue Knob `define LLMRVQ_SIZE `LLREQQ_SIZE // Dram Fill Rsp Queue Size @@ -322,6 +332,8 @@ `define LLDFQQ_SIZE `LLREQQ_SIZE // Lower Level Cache Hit Queue Size `define LLLLVQ_SIZE 0 + // Fill Forward SNP Queue + `define LLFFSQ_SIZE 8 // Fill Invalidator Size {Fill invalidator must be active} `define LLFILL_INVALIDAOR_SIZE 16 @@ -332,4 +344,57 @@ // ========================================= L2cache Configurable Knobs ========================================= +// ========================================= L3cache Configurable Knobs ========================================= + +// General Cache Knobs + // Size of cache in bytes + `define L3CACHE_SIZE_BYTES 1024 + // Size of line inside a bank in bytes + `define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES + // Number of banks {1, 2, 4, 8,...} + `define L3NUMBER_BANKS 8 + // Size of a word in bytes + `define L3WORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) + // Number of Word requests per cycle {1, 2, 4, 8, ...} + `define L3NUMBER_REQUESTS (2*`NUMBER_CLUSTERS) + // Number of cycles to complete stage 1 (read from memory) + `define L3STAGE_1_CYCLES 2 + // Function ID + `define L3FUNC_ID 3 + + // Bank Number of words in a line + `define L3BANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES) + `define L3BANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0 +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + + // Core Request Queue Size + `define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS) + // Miss Reserv Queue Knob + `define L3MRVQ_SIZE `LLREQQ_SIZE + // Dram Fill Rsp Queue Size + `define L3DFPQ_SIZE 2 + // Snoop Req Queue + `define L3SNRQ_SIZE 8 + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size + `define L3CWBQ_SIZE `LLREQQ_SIZE + // Dram Writeback Queue Size + `define L3DWBQ_SIZE 4 + // Dram Fill Req Queue Size + `define L3DFQQ_SIZE `LLREQQ_SIZE + // Lower Level Cache Hit Queue Size + `define L3LLVQ_SIZE 0 + // Fill Forward SNP Queue + `define L3FFSQ_SIZE 8 + + // Fill Invalidator Size {Fill invalidator must be active} + `define L3FILL_INVALIDAOR_SIZE 16 + +// Dram knobs + `define L3SIMULATED_DRAM_LATENCY_CYCLES 10 + +// ========================================= L3cache Configurable Knobs ========================================= + + `endif diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 4e1596b7..75ba5c00 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -92,6 +92,7 @@ module VX_dmem_controller ( .DWBQ_SIZE (`SDWBQ_SIZE), .DFQQ_SIZE (`SDFQQ_SIZE), .LLVQ_SIZE (`SLLVQ_SIZE), + .FFSQ_SIZE (`SFFSQ_SIZE), .FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`SSIMULATED_DRAM_LATENCY_CYCLES) ) @@ -167,6 +168,7 @@ module VX_dmem_controller ( .DWBQ_SIZE (`DDWBQ_SIZE), .DFQQ_SIZE (`DDFQQ_SIZE), .LLVQ_SIZE (`DLLVQ_SIZE), + .FFSQ_SIZE (`DFFSQ_SIZE), .FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES) ) @@ -244,6 +246,7 @@ module VX_dmem_controller ( .DWBQ_SIZE (`IDWBQ_SIZE), .DFQQ_SIZE (`IDFQQ_SIZE), .LLVQ_SIZE (`ILLVQ_SIZE), + .FFSQ_SIZE (`IFFSQ_SIZE), .FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`ISIMULATED_DRAM_LATENCY_CYCLES) ) diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index 2305e55c..d2b47e25 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -216,6 +216,7 @@ module Vortex_SOC ( .DWBQ_SIZE (`LLDWBQ_SIZE), .DFQQ_SIZE (`LLDFQQ_SIZE), .LLVQ_SIZE (`LLLLVQ_SIZE), + .FFSQ_SIZE (`LLFFSQ_SIZE), .FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES) ) From 13c6cbfa5dc926d2b6069fb30b466dd44633e7cb Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 10 Mar 2020 02:41:47 -0700 Subject: [PATCH 38/66] L3 and CLUSTRING WORKS --- rtl/VX_cache/VX_bank.v | 29 +- rtl/VX_cache/VX_cache.v | 57 ++- rtl/VX_cache/VX_cache_req_queue.v | 55 +-- rtl/VX_cache/VX_cache_wb_sel_merge.v | 18 +- rtl/VX_cache/VX_snp_fwd_arb.v | 39 ++ rtl/VX_define.v | 22 +- rtl/VX_dmem_controller.v | 31 +- rtl/Vortex.v | 31 ++ rtl/Vortex_SOC.v | 584 ++++++++++++++++++--------- rtl/interfaces/VX_gpu_snp_req_rsp.v | 20 + rtl/simulate/multi_test_bench.h | 30 +- 11 files changed, 654 insertions(+), 262 deletions(-) create mode 100644 rtl/VX_cache/VX_snp_fwd_arb.v create mode 100644 rtl/interfaces/VX_gpu_snp_req_rsp.v diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index d61a0b9c..d61cc297 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -98,9 +98,11 @@ module VX_bank // Snp Request input wire snp_req, input wire[31:0] snp_req_addr, + output wire snrq_full, output wire snp_fwd, - output wire[31:0] snp_fwd_addr + output wire[31:0] snp_fwd_addr, + input wire snp_fwd_pop ); @@ -108,7 +110,6 @@ module VX_bank wire snrq_pop; wire snrq_empty; - wire snrq_full; wire snrq_valid_st0; wire[31:0] snrq_addr_st0; @@ -516,7 +517,7 @@ module VX_bank // Enqueue to miss reserv if it's a valid miss - assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full)); + assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full)); assign miss_add_pc = pc_st2; assign miss_add_addr = addr_st2; assign miss_add_data = writeword_st2; @@ -524,7 +525,7 @@ module VX_bank // Enqueue to CWB Queue - wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)) && !( (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); + wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); wire [`WORD_SIZE_RNG] cwbq_data = readword_st2; wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid; wire [4:0] cwbq_rd = miss_add_rd; @@ -549,7 +550,7 @@ module VX_bank ); // Enqueue to DWB Queue - wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); + wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK; wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2; wire dwbq_empty; @@ -609,11 +610,25 @@ module VX_bank ); wire snp_fwd_push; - wire snp_fwd_pop; + wire ffsq_full; + wire ffsq_empty; + + assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); + assign snp_fwd = !ffsq_empty; + VX_generic_queue_ll #(.DATAW(32), .SIZE(FFSQ_SIZE)) ffs_queue( + .clk (clk), + .reset (reset), + .push (snp_fwd_push), + .in_data ({addr_st2}), + .pop (snp_fwd_pop), + .out_data({snp_fwd_addr}), + .empty (ffsq_empty), + .full (ffsq_full) + ); - assign stall_bank_pipe = ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full); + assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full); endmodule diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 2c30a0b1..05b01f37 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -96,7 +96,13 @@ module VX_cache // Snoop Req input wire snp_req, - input wire[31:0] snp_req_addr + input wire[31:0] snp_req_addr, + output wire snp_req_delay, + + // Snoop Forward + output wire snp_fwd, + output wire[31:0] snp_fwd_addr, + input wire snp_fwd_delay ); @@ -126,9 +132,19 @@ module VX_cache wire[NUMBER_BANKS-1:0] per_bank_reqq_full; + wire[NUMBER_BANKS-1:0] per_bank_snrq_full; + + wire[NUMBER_BANKS-1:0] per_bank_snp_fwd; + wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr; + wire[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop; + + assign delay_req = (|per_bank_reqq_full); + assign snp_req_delay = (|per_bank_snrq_full); + + assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; VX_cache_dram_req_arb #( @@ -238,6 +254,21 @@ module VX_cache .core_wb_pc (core_wb_pc) ); + + + + // Snoop Forward Logic + VX_snp_fwd_arb #(.NUMBER_BANKS(NUMBER_BANKS)) VX_snp_fwd_arb( + .per_bank_snp_fwd (per_bank_snp_fwd), + .per_bank_snp_fwd_addr(per_bank_snp_fwd_addr), + .per_bank_snp_fwd_pop (per_bank_snp_fwd_pop), + .snp_fwd (snp_fwd), + .snp_fwd_addr (snp_fwd_addr), + .snp_fwd_delay (snp_fwd_delay) + ); + + // Snoop Forward Logic + genvar curr_bank; generate for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin @@ -282,6 +313,11 @@ module VX_cache wire curr_bank_reqq_full; + wire curr_bank_snp_fwd; + wire[31:0] curr_bank_snp_fwd_addr; + wire curr_bank_snp_fwd_pop; + wire curr_bank_snrq_full; + // Core Req @@ -326,8 +362,15 @@ module VX_cache assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data; // Snoop Request - assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); - assign curr_bank_snp_req_addr = snp_req_addr; + assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); + assign curr_bank_snp_req_addr = snp_req_addr; + assign per_bank_snrq_full[curr_bank] = curr_bank_snrq_full; + + // Snoop Fwd + assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank]; + assign per_bank_snp_fwd[curr_bank] = curr_bank_snp_fwd; + assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr; + VX_bank #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), @@ -398,7 +441,13 @@ module VX_cache // Snoop Request .snp_req (curr_bank_snp_req), - .snp_req_addr (curr_bank_snp_req_addr) + .snp_req_addr (curr_bank_snp_req_addr), + .snrq_full (curr_bank_snrq_full), + + // Snoop Fwd + .snp_fwd (curr_bank_snp_fwd), + .snp_fwd_addr (curr_bank_snp_fwd_addr), + .snp_fwd_pop (curr_bank_snp_fwd_pop) ); diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 937fa7fb..5938d349 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -110,7 +110,7 @@ module VX_cache_req_queue wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_write; wire [31:0] qual_pc; - wire[NUMBER_REQUESTS-1:0] updated_valids; + reg [NUMBER_REQUESTS-1:0] updated_valids; wire o_empty; @@ -118,7 +118,7 @@ module VX_cache_req_queue wire out_empty = !(|out_per_valids) || o_empty; wire push_qual = reqq_push && !reqq_full; - wire pop_qual = reqq_pop && use_empty && !out_empty; + wire pop_qual = !out_empty && use_empty; VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUMBER_REQUESTS*2) + (`NW_M1+1) + (NUMBER_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue( .clk (clk), @@ -134,15 +134,15 @@ module VX_cache_req_queue wire[NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUMBER_REQUESTS{~out_empty}}; - assign qual_valids = use_empty ? real_out_per_valids : out_empty ? 0 : use_per_valids; - assign qual_addr = use_empty ? out_per_addr : use_per_addr; - assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata; - assign qual_rd = use_empty ? out_per_rd : use_per_rd; - assign qual_wb = use_empty ? out_per_wb : use_per_wb; - assign qual_warp_num = use_empty ? out_per_warp_num : use_per_warp_num; - assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read; - assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write; - assign qual_pc = use_empty ? out_per_pc : use_per_pc; + assign qual_valids = use_per_valids; + assign qual_addr = use_per_addr; + assign qual_writedata = use_per_writedata; + assign qual_rd = use_per_rd; + assign qual_wb = use_per_wb; + assign qual_warp_num = use_per_warp_num; + assign qual_mem_read = use_per_mem_read; + assign qual_mem_write = use_per_mem_write; + assign qual_pc = use_per_pc; wire[`vx_clog2(NUMBER_REQUESTS)-1:0] qual_request_index; wire qual_has_request; @@ -164,7 +164,14 @@ module VX_cache_req_queue assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index]; assign reqq_req_pc_st0 = qual_pc; - assign updated_valids = qual_valids & (~(1 << qual_request_index)); + + always @(*) begin + assign updated_valids = qual_valids; + if (qual_has_request) begin + assign updated_valids[qual_request_index] = 0; + end + end + always @(posedge clk) begin if (reset) begin @@ -178,17 +185,19 @@ module VX_cache_req_queue use_per_mem_write <= 0; use_per_pc <= 0; end else begin - if (reqq_pop && qual_has_request) begin - use_per_valids <= updated_valids; - use_per_addr <= qual_addr; - use_per_writedata <= qual_writedata; - use_per_rd <= qual_rd; - use_per_wb <= qual_wb; - use_per_warp_num <= qual_warp_num; - use_per_mem_read <= qual_mem_read; - use_per_mem_write <= qual_mem_write; - use_per_pc <= qual_pc; - end + if (pop_qual) begin + use_per_valids <= real_out_per_valids; + use_per_addr <= out_per_addr; + use_per_writedata <= out_per_writedata; + use_per_rd <= out_per_rd; + use_per_wb <= out_per_wb; + use_per_warp_num <= out_per_warp_num; + use_per_mem_read <= out_per_mem_read; + use_per_mem_write <= out_per_mem_write; + use_per_pc <= out_per_pc; + end else if (reqq_pop) begin + use_per_valids[qual_request_index] <= 0; + end // else if (reqq_pop) begin // use_per_valids[qual_request_index] <= updated_valids; // end diff --git a/rtl/VX_cache/VX_cache_wb_sel_merge.v b/rtl/VX_cache/VX_cache_wb_sel_merge.v index 7199c483..148b443b 100644 --- a/rtl/VX_cache/VX_cache_wb_sel_merge.v +++ b/rtl/VX_cache/VX_cache_wb_sel_merge.v @@ -75,20 +75,20 @@ module VX_cache_wb_sel_merge reg [NUMBER_BANKS-1:0] per_bank_wb_pop_unqual; assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUMBER_BANKS{~core_no_wb_slot}}; - wire[NUMBER_BANKS-1:0] bank_wants_wb; - genvar curr_bank; - generate - for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin - assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]); - end - endgenerate + // wire[NUMBER_BANKS-1:0] bank_wants_wb; + // genvar curr_bank; + // generate + // for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin + // assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]); + // end + // endgenerate wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index; wire found_bank; VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank( - .valids(bank_wants_wb), + .valids(per_bank_wb_valid), .index (main_bank_index), .found (found_bank) ); @@ -105,7 +105,7 @@ module VX_cache_wb_sel_merge core_wb_pc = 0; core_wb_address = 0; for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin - if (((FUNC_ID == `LLFUNC_ID) && found_bank && per_bank_wb_valid[this_bank]) || (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index]))) begin + if (((FUNC_ID == `LLFUNC_ID) && found_bank && per_bank_wb_valid[this_bank] && ((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) || ((FUNC_ID != `LLFUNC_ID) && ((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index])) && found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index]))) begin core_wb_valid[per_bank_wb_tid[this_bank]] = 1; core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank]; diff --git a/rtl/VX_cache/VX_snp_fwd_arb.v b/rtl/VX_cache/VX_snp_fwd_arb.v new file mode 100644 index 00000000..7f2d3e64 --- /dev/null +++ b/rtl/VX_cache/VX_snp_fwd_arb.v @@ -0,0 +1,39 @@ + +module VX_snp_fwd_arb + #( + parameter NUMBER_BANKS = 8 + ) + ( + input wire[NUMBER_BANKS-1:0] per_bank_snp_fwd, + input wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr, + output reg[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop, + + output wire snp_fwd, + output wire[31:0] snp_fwd_addr, + input wire snp_fwd_delay + +); + + + wire[NUMBER_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUMBER_BANKS{!snp_fwd_delay}}; + + wire[`vx_clog2(NUMBER_BANKS)-1:0] fsq_bank; + wire fsq_valid; + + VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_ffsq( + .valids(qual_per_bank_snp_fwd), + .index (fsq_bank), + .found (fsq_valid) + ); + + assign snp_fwd = fsq_valid; + assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank]; + + always @(*) begin + assign per_bank_snp_fwd_pop = 0; + if (fsq_valid) begin + per_bank_snp_fwd_pop[fsq_bank] = 1; + end + end + +endmodule \ No newline at end of file diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 45c6c375..19cf8fac 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -126,9 +126,9 @@ -`define NUMBER_CORES_PER_CLUSTERS (2) -`define NUMBER_CLUSTERS (1) -`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTERS*`NUMBER_CLUSTERS) +`define NUMBER_CORES_PER_CLUSTER 2 +`define NUMBER_CLUSTERS 2 +`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) // `define SINGLE_CORE_BENCH 0 `define GLOBAL_BLOCK_SIZE_BYTES 16 @@ -303,7 +303,7 @@ // Size of a word in bytes `define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) // Number of Word requests per cycle {1, 2, 4, 8, ...} - `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTERS) + `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER) // Number of cycles to complete stage 1 (read from memory) `define LLSTAGE_1_CYCLES 2 // Function ID @@ -315,7 +315,7 @@ // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size - `define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES_PER_CLUSTERS) + `define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES_PER_CLUSTER) // Miss Reserv Queue Knob `define LLMRVQ_SIZE `LLREQQ_SIZE // Dram Fill Rsp Queue Size @@ -354,17 +354,17 @@ // Number of banks {1, 2, 4, 8,...} `define L3NUMBER_BANKS 8 // Size of a word in bytes - `define L3WORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) + `define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES) // Number of Word requests per cycle {1, 2, 4, 8, ...} - `define L3NUMBER_REQUESTS (2*`NUMBER_CLUSTERS) + `define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS) // Number of cycles to complete stage 1 (read from memory) `define L3STAGE_1_CYCLES 2 // Function ID `define L3FUNC_ID 3 // Bank Number of words in a line - `define L3BANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES) - `define L3BANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0 + `define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES) + `define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0 // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size @@ -378,11 +378,11 @@ // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size - `define L3CWBQ_SIZE `LLREQQ_SIZE + `define L3CWBQ_SIZE `L3REQQ_SIZE // Dram Writeback Queue Size `define L3DWBQ_SIZE 4 // Dram Fill Req Queue Size - `define L3DFQQ_SIZE `LLREQQ_SIZE + `define L3DFQQ_SIZE `L3REQQ_SIZE // Lower Level Cache Hit Queue Size `define L3LLVQ_SIZE 0 // Fill Forward SNP Queue diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 75ba5c00..b9cff01b 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -7,10 +7,12 @@ module VX_dmem_controller ( // Dram <-> Dcache VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req, VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res, + VX_gpu_snp_req_rsp VX_gpu_dcache_snp_req, // Dram <-> Icache VX_gpu_dcache_dram_req_inter VX_gpu_icache_dram_req, VX_gpu_dcache_dram_res_inter VX_gpu_icache_dram_res, + VX_gpu_snp_req_rsp VX_gpu_icache_snp_req, // Core <-> Dcache VX_gpu_dcache_res_inter VX_dcache_rsp, @@ -149,7 +151,12 @@ module VX_dmem_controller ( // Snoop Request .snp_req (0), - .snp_req_addr (0) + .snp_req_addr (0), + + // Snoop Forward + .snp_fwd (), + .snp_fwd_addr (), + .snp_fwd_delay (0) ); VX_cache #( @@ -224,8 +231,15 @@ module VX_dmem_controller ( .dram_snp_full (VX_gpu_dcache_dram_req.dram_snp_full), // Snoop Request - .snp_req (0), - .snp_req_addr (0) + .snp_req (VX_gpu_dcache_snp_req.snp_req), + .snp_req_addr (VX_gpu_dcache_snp_req.snp_req_addr), + .snp_req_delay (VX_gpu_dcache_snp_req.snp_delay), + + + // Snoop Forward + .snp_fwd (), + .snp_fwd_addr (), + .snp_fwd_delay (0) ); @@ -301,9 +315,16 @@ module VX_dmem_controller ( .dram_req_because_of_wb(VX_gpu_icache_dram_req.dram_because_of_snp), .dram_snp_full (VX_gpu_icache_dram_req.dram_snp_full), + // Snoop Request - .snp_req (0), - .snp_req_addr (0) + .snp_req (VX_gpu_icache_snp_req.snp_req), + .snp_req_addr (VX_gpu_icache_snp_req.snp_req_addr), + .snp_req_delay (VX_gpu_icache_snp_req.snp_delay), + + // Snoop Forward + .snp_fwd (), + .snp_fwd_addr (), + .snp_fwd_delay (0) ); diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 862e7007..d5454d7d 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -45,6 +45,15 @@ module Vortex input wire [31:0] I_dram_fill_rsp_addr, input wire [31:0] I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG], + input wire snp_req, + input wire [31:0] snp_req_addr, + output wire snp_req_delay, + + input wire I_snp_req, + input wire [31:0] I_snp_req_addr, + output wire I_snp_req_delay, + + output wire out_ebreak `else @@ -86,6 +95,15 @@ module Vortex input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data, + input wire snp_req, + input wire [31:0] snp_req_addr, + output wire snp_req_delay, + + input wire I_snp_req, + input wire [31:0] I_snp_req_addr, + output wire I_snp_req_delay, + + output wire out_ebreak `endif ); @@ -191,6 +209,17 @@ VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch VX_warp_ctl_inter VX_warp_ctl(); +VX_gpu_snp_req_rsp VX_gpu_icache_snp_req(); +VX_gpu_snp_req_rsp VX_gpu_dcache_snp_req(); + +assign VX_gpu_icache_snp_req.snp_req = I_snp_req; +assign VX_gpu_icache_snp_req.snp_req_addr = I_snp_req_addr; +assign I_snp_req_delay = VX_gpu_icache_snp_req.snp_delay; + +assign VX_gpu_dcache_snp_req.snp_req = snp_req; +assign VX_gpu_dcache_snp_req.snp_req_addr = snp_req_addr; +assign snp_req_delay = VX_gpu_dcache_snp_req.snp_delay; + VX_front_end vx_front_end( .clk (clk), .reset (reset), @@ -240,10 +269,12 @@ VX_dmem_controller VX_dmem_controller( // Dram <-> Dcache .VX_gpu_dcache_dram_req (VX_gpu_dcache_dram_req), .VX_gpu_dcache_dram_res (VX_gpu_dcache_dram_res), + .VX_gpu_dcache_snp_req (VX_gpu_dcache_snp_req), // Dram <-> Icache .VX_gpu_icache_dram_req (VX_gpu_icache_dram_req), .VX_gpu_icache_dram_res (VX_gpu_icache_dram_res), + .VX_gpu_icache_snp_req (VX_gpu_icache_snp_req), // Core <-> Icache .VX_icache_req (VX_icache_req), diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index d2b47e25..9e9210fe 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -11,274 +11,482 @@ module Vortex_SOC ( output wire[31:0] number_cores, // DRAM Dcache Req - output wire dram_req, - output wire dram_req_write, - output wire dram_req_read, - output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, - output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], - output wire [31:0] dram_expected_lat, + output wire out_dram_req, + output wire out_dram_req_write, + output wire out_dram_req_read, + output wire [31:0] out_dram_req_addr, + output wire [31:0] out_dram_req_size, + output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] out_dram_expected_lat, // DRAM Dcache Res - output wire dram_fill_accept, - input wire dram_fill_rsp, - input wire [31:0] dram_fill_rsp_addr, - input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + output wire out_dram_fill_accept, + input wire out_dram_fill_rsp, + input wire [31:0] out_dram_fill_rsp_addr, + input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + + input wire l3c_snp_req, + input wire l3c_snp_req_addr, + output wire l3c_snp_req_delay, output wire out_ebreak ); + + // DRAM Dcache Req + wire [`NUMBER_CLUSTERS-1:0] dram_req; + wire [`NUMBER_CLUSTERS-1:0] dram_req_write; + wire [`NUMBER_CLUSTERS-1:0] dram_req_read; + wire [`NUMBER_CLUSTERS-1:0][31:0] dram_req_addr; + wire [`NUMBER_CLUSTERS-1:0][31:0] dram_req_size; + wire [`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG][31:0] dram_req_data; + wire [`NUMBER_CLUSTERS-1:0][31:0] dram_expected_lat; + + // DRAM Dcache Res + wire [`NUMBER_CLUSTERS-1:0] dram_fill_accept; + wire [`NUMBER_CLUSTERS-1:0] dram_fill_rsp; + wire [`NUMBER_CLUSTERS-1:0][31:0] dram_fill_rsp_addr; + wire [`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data; + assign number_cores = `NUMBER_CORES; // IO - wire per_core_io_valid[`NUMBER_CORES-1:0]; - wire[31:0] per_core_io_data[`NUMBER_CORES-1:0]; - - // DRAM Dcache Req - wire[`NUMBER_CORES-1:0] per_core_dram_req; - wire[`NUMBER_CORES-1:0] per_core_dram_req_write; - wire[`NUMBER_CORES-1:0] per_core_dram_req_read; - wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_req_addr; - wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_req_size; - wire[`NUMBER_CORES-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data; - wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_expected_lat; - - // DRAM Dcache Res - wire[`NUMBER_CORES-1:0] per_core_dram_fill_accept; - wire[`NUMBER_CORES-1:0] per_core_dram_fill_rsp; - wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_fill_rsp_addr; - wire[`NUMBER_CORES-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data; - - - // DRAM Icache Req - wire[`NUMBER_CORES-1:0] per_core_I_dram_req; - wire[`NUMBER_CORES-1:0] per_core_I_dram_req_write; - wire[`NUMBER_CORES-1:0] per_core_I_dram_req_read; - wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_req_addr; - wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_req_size; - wire[`NUMBER_CORES-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data; - wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_expected_lat; - - // DRAM Icache Res - wire[`NUMBER_CORES-1:0] per_core_I_dram_fill_accept; - wire[`NUMBER_CORES-1:0] per_core_I_dram_fill_rsp; - wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_fill_rsp_addr; - wire[`NUMBER_CORES-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; + // wire per_core_io_valid[`NUMBER_CORES-1:0]; + // wire[31:0] per_core_io_data[`NUMBER_CORES-1:0]; // Out ebreak wire[`NUMBER_CORES-1:0] per_core_out_ebreak; - assign out_ebreak = (&per_core_out_ebreak); - genvar curr_core; + wire[`L3NUMBER_REQUESTS-1:0] l3c_core_req; + wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_write; + wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_read; + wire[`L3NUMBER_REQUESTS-1:0][31:0] l3c_core_req_addr; + wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_core_req_data; + wire[`L3NUMBER_REQUESTS-1:0][1:0] l3c_core_req_wb; + + wire l3c_core_accept; + + + wire l3c_snp_fwd; + wire[31:0] l3c_snp_fwd_addr; + wire[`L3NUMBER_REQUESTS-1:0] l3c_snp_fwd_delay_temp; + wire l3c_snp_fwd_delay; + + assign l3c_snp_fwd_delay = (|l3c_snp_fwd_delay_temp); + + + wire[`L3NUMBER_REQUESTS-1:0] l3c_wb; + wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr; + wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data; + + wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_req_data; + wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_fill_rsp_data; + + genvar curr_l; generate - - for (curr_core = 0; curr_core < `NUMBER_CORES; curr_core=curr_core+1) begin - - wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data; - wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ; - - assign io_valid[curr_core] = per_core_io_valid[curr_core]; - assign io_data [curr_core] = per_core_io_data [curr_core]; - Vortex #(.CORE_ID(curr_core)) vortex_core( - .clk (clk), - .reset (reset), - .io_valid (per_core_io_valid [curr_core]), - .io_data (per_core_io_data [curr_core]), - .dram_req (per_core_dram_req [curr_core]), - .dram_req_write (per_core_dram_req_write [curr_core]), - .dram_req_read (per_core_dram_req_read [curr_core]), - .dram_req_addr (per_core_dram_req_addr [curr_core]), - .dram_req_size (per_core_dram_req_size [curr_core]), - .dram_req_data (curr_core_dram_req_data ), - .dram_expected_lat (per_core_dram_expected_lat [curr_core]), - .dram_fill_accept (per_core_dram_fill_accept [curr_core]), - .dram_fill_rsp (per_core_dram_fill_rsp [curr_core]), - .dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]), - .dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]), - .I_dram_req (per_core_I_dram_req [curr_core]), - .I_dram_req_write (per_core_I_dram_req_write [curr_core]), - .I_dram_req_read (per_core_I_dram_req_read [curr_core]), - .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), - .I_dram_req_size (per_core_I_dram_req_size [curr_core]), - .I_dram_req_data (curr_core_I_dram_req_data ), - .I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]), - .I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]), - .I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]), - .I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]), - .I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]), - .out_ebreak (per_core_out_ebreak [curr_core]) - ); - - assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; - assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data; + for (curr_l = 0; curr_l < `IBANK_LINE_SIZE_WORDS; curr_l=curr_l+1) begin + assign out_dram_req_data[curr_l][31:0] = l3c_dram_req_data[curr_l][31:0]; + assign l3c_dram_fill_rsp_data[curr_l][31:0] = out_dram_fill_rsp_data[curr_l][31:0]; end endgenerate - //////////////////// L2 Cache //////////////////// - wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req; - wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write; - wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read; - wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr; - wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data; - wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb; - - wire l2c_core_accept; - - - wire[`LLNUMBER_REQUESTS-1:0] l2c_wb; - wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr; - wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data; - - - wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port; - wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port; - - genvar llb_index; - generate - for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin - assign dram_req_data [llb_index] = dram_req_data_port[llb_index]; - assign dram_fill_rsp_data_port[llb_index] = dram_fill_rsp_data[llb_index]; - end - endgenerate - - // genvar l2c_index; - // genvar l2c_bank_index; - // generate - // for (l2c_index = 0; l2c_index < `LLNUMBER_REQUESTS; l2c_index=l2c_index+1) begin - // assign l2c_wb [l2c_index] = l2c_wb_port [l2c_index]; - // assign l2c_wb_addr[l2c_index] = l2c_wb_addr_port[l2c_index]; - // for (l2c_bank_index = 0; l2c_bank_index < `LLNUMBER_REQUESTS; l2c_bank_index=l2c_bank_index+1) begin - // assign l2c_wb_data[l2c_index][l2c_bank_index] = l2c_wb_data_port[l2c_index][l2c_bank_index]; - // end - // end - // endgenerate - // - genvar l2c_curr_core; + genvar l3c_curr_core; generate - for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin + for (l3c_curr_core = 0; l3c_curr_core < `L3NUMBER_REQUESTS; l3c_curr_core=l3c_curr_core+1) begin // Core Request - assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; - assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; + assign l3c_core_req [l3c_curr_core] = dram_req [(l3c_curr_core)]; - assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write ? `SW_MEM_WRITE : `NO_MEM_WRITE; - assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write + assign l3c_core_req_mem_write [l3c_curr_core] = dram_req_write ? `SW_MEM_WRITE : `NO_MEM_WRITE; - assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read ? `LW_MEM_READ : `NO_MEM_READ; - assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write + assign l3c_core_req_mem_read [l3c_curr_core] = dram_req_read ? `LW_MEM_READ : `NO_MEM_READ; - assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read ? 1 : 0; - assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write + assign l3c_core_req_wb [l3c_curr_core] = dram_req_read ? 1 : 0; - assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)]; - assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)]; + assign l3c_core_req_addr [l3c_curr_core] = dram_req_addr [(l3c_curr_core)]; - assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)]; - assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)]; + assign l3c_core_req_data [l3c_curr_core] = dram_req_data [(l3c_curr_core)]; // L2 can't accept requests - assign per_core_dram_fill_accept [(l2c_curr_core/2)] = l2c_core_accept; - assign per_core_I_dram_fill_accept[(l2c_curr_core/2)] = l2c_core_accept; + assign dram_fill_accept [(l3c_curr_core)] = l3c_core_accept; // Cache Fill Response - assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; - assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; + assign dram_fill_rsp [(l3c_curr_core)] = l3c_wb[l3c_curr_core]; - assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; - assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; + assign dram_fill_rsp_data[(l3c_curr_core)] = l3c_wb_data[l3c_curr_core]; - assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; - assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; + assign dram_fill_rsp_addr[(l3c_curr_core)] = l3c_wb_addr[l3c_curr_core]; end endgenerate wire dram_snp_full; wire dram_req_because_of_wb; + + VX_cache #( - .CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES), - .BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES), - .NUMBER_BANKS (`LLNUMBER_BANKS), - .WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES), - .NUMBER_REQUESTS (`LLNUMBER_REQUESTS), - .STAGE_1_CYCLES (`LLSTAGE_1_CYCLES), + .CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`L3NUMBER_BANKS), + .WORD_SIZE_BYTES (`L3WORD_SIZE_BYTES), + .NUMBER_REQUESTS (`L3NUMBER_REQUESTS), + .STAGE_1_CYCLES (`L3STAGE_1_CYCLES), .FUNC_ID (`LLFUNC_ID), - .REQQ_SIZE (`LLREQQ_SIZE), - .MRVQ_SIZE (`LLMRVQ_SIZE), - .DFPQ_SIZE (`LLDFPQ_SIZE), - .SNRQ_SIZE (`LLSNRQ_SIZE), - .CWBQ_SIZE (`LLCWBQ_SIZE), - .DWBQ_SIZE (`LLDWBQ_SIZE), - .DFQQ_SIZE (`LLDFQQ_SIZE), - .LLVQ_SIZE (`LLLLVQ_SIZE), - .FFSQ_SIZE (`LLFFSQ_SIZE), - .FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE), - .SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES) + .REQQ_SIZE (`L3REQQ_SIZE), + .MRVQ_SIZE (`L3MRVQ_SIZE), + .DFPQ_SIZE (`L3DFPQ_SIZE), + .SNRQ_SIZE (`L3SNRQ_SIZE), + .CWBQ_SIZE (`L3CWBQ_SIZE), + .DWBQ_SIZE (`L3DWBQ_SIZE), + .DFQQ_SIZE (`L3DFQQ_SIZE), + .LLVQ_SIZE (`L3LLVQ_SIZE), + .FFSQ_SIZE (`L3FFSQ_SIZE), + .FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`L3SIMULATED_DRAM_LATENCY_CYCLES) ) - gpu_l2cache + gpu_l3cache ( .clk (clk), .reset (reset), // Core Req (DRAM Fills/WB) To L2 Request - .core_req_valid (l2c_core_req), - .core_req_addr (l2c_core_req_addr), - .core_req_writedata({l2c_core_req_data}), - .core_req_mem_read (l2c_core_req_mem_read), - .core_req_mem_write(l2c_core_req_mem_write), + .core_req_valid (l3c_core_req), + .core_req_addr (l3c_core_req_addr), + .core_req_writedata({l3c_core_req_data}), + .core_req_mem_read (l3c_core_req_mem_read), + .core_req_mem_write(l3c_core_req_mem_write), .core_req_rd (0), - .core_req_wb (l2c_core_req_wb), + .core_req_wb (l3c_core_req_wb), .core_req_warp_num (0), .core_req_pc (0), // L2 can't accept Core Request - .delay_req (l2c_core_accept), + .delay_req (l3c_core_accept), // Core can't accept L2 Request .core_no_wb_slot (0), // Core Writeback - .core_wb_valid (l2c_wb), + .core_wb_valid (l3c_wb), .core_wb_req_rd (), .core_wb_req_wb (), .core_wb_warp_num (), - .core_wb_readdata ({l2c_wb_data}), - .core_wb_address (l2c_wb_addr), + .core_wb_readdata ({l3c_wb_data}), + .core_wb_address (l3c_wb_addr), .core_wb_pc (), // L2 Cache DRAM Fill response - .dram_fill_rsp (dram_fill_rsp), - .dram_fill_rsp_addr(dram_fill_rsp_addr), - .dram_fill_rsp_data({dram_fill_rsp_data_port}), + .dram_fill_rsp (out_dram_fill_rsp), + .dram_fill_rsp_addr(out_dram_fill_rsp_addr), + .dram_fill_rsp_data({l3c_dram_fill_rsp_data}), // L2 Cache can't accept Fill Response - .dram_fill_accept (dram_fill_accept), + .dram_fill_accept (out_dram_fill_accept), // L2 Cache DRAM Fill Request - .dram_req (dram_req), - .dram_req_write (dram_req_write), - .dram_req_read (dram_req_read), - .dram_req_addr (dram_req_addr), - .dram_req_size (dram_req_size), - .dram_req_data ({dram_req_data_port}), + .dram_req (out_dram_req), + .dram_req_write (out_dram_req_write), + .dram_req_read (out_dram_req_read), + .dram_req_addr (out_dram_req_addr), + .dram_req_size (out_dram_req_size), + .dram_req_data ({l3c_dram_req_data}), // Snoop Response .dram_req_because_of_wb(dram_req_because_of_wb), .dram_snp_full (dram_snp_full), // Snoop Request - .snp_req (0), - .snp_req_addr (0) + .snp_req (l3c_snp_req), + .snp_req_addr (l3c_snp_req_addr), + .snp_req_delay (l3c_snp_req_delay), + + .snp_fwd (l3c_snp_fwd), + .snp_fwd_addr (l3c_snp_fwd_addr), + .snp_fwd_delay (l3c_snp_fwd_delay) ); - //////////////////// L2 Cache //////////////////// + //////////////////// L3 Cache //////////////////// + + + + genvar curr_cluster; + genvar curr_core; + genvar llb_index; + genvar l2c_curr_core; + + generate + for (curr_cluster = 0; curr_cluster < `NUMBER_CLUSTERS; curr_cluster=curr_cluster+1) begin + ////////////////////// BEGIN CLUSTER ///////////////// + + + + // DRAM Dcache Req + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_read; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat; + + // DRAM Dcache Res + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data; + + + // DRAM Icache Req + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat; + + // DRAM Icache Res + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; + + + + // Snoop Requests + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dcache_snp_req; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_dcache_snp_req_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dcache_snp_req_delay; + + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_icache_snp_req; + wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_icache_snp_req_addr; + wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_icache_snp_req_delay; + + + // generate + for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin + + wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data; + wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ; + + // assign io_valid[curr_core*curr_cluster] = per_core_io_valid[curr_core]; + // assign io_data [curr_core*curr_cluster] = per_core_io_data [curr_core]; + Vortex #(.CORE_ID(curr_core+(curr_cluster*`NUMBER_CORES_PER_CLUSTER))) vortex_core( + .clk (clk), + .reset (reset), + .io_valid (io_valid [curr_core+(curr_cluster*`NUMBER_CORES_PER_CLUSTER)]), + .io_data (io_data [curr_core+(curr_cluster*`NUMBER_CORES_PER_CLUSTER)]), + .out_ebreak (per_core_out_ebreak [curr_core+(curr_cluster*`NUMBER_CORES_PER_CLUSTER)]), + .dram_req (per_core_dram_req [curr_core]), + .dram_req_write (per_core_dram_req_write [curr_core]), + .dram_req_read (per_core_dram_req_read [curr_core]), + .dram_req_addr (per_core_dram_req_addr [curr_core]), + .dram_req_size (per_core_dram_req_size [curr_core]), + .dram_req_data (curr_core_dram_req_data ), + .dram_expected_lat (per_core_dram_expected_lat [curr_core]), + .dram_fill_accept (per_core_dram_fill_accept [curr_core]), + .dram_fill_rsp (per_core_dram_fill_rsp [curr_core]), + .dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]), + .dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]), + .I_dram_req (per_core_I_dram_req [curr_core]), + .I_dram_req_write (per_core_I_dram_req_write [curr_core]), + .I_dram_req_read (per_core_I_dram_req_read [curr_core]), + .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), + .I_dram_req_size (per_core_I_dram_req_size [curr_core]), + .I_dram_req_data (curr_core_I_dram_req_data ), + .I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]), + .I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]), + .I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]), + .I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]), + .I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]), + .snp_req (per_core_dcache_snp_req [curr_core]), + .snp_req_addr (per_core_dcache_snp_req_addr [curr_core]), + .snp_req_delay (per_core_dcache_snp_req_delay[curr_core]), + .I_snp_req (per_core_icache_snp_req [curr_core]), + .I_snp_req_addr (per_core_icache_snp_req_addr [curr_core]), + .I_snp_req_delay (per_core_icache_snp_req_delay[curr_core]) + ); + + assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; + assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data; + end + // endgenerate + + + //////////////////// L2 Cache //////////////////// + wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req; + wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write; + wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read; + wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr; + wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data; + wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb; + + wire l2c_core_accept; + + wire l2c_snp_fwd; + wire[31:0] l2c_snp_fwd_addr; + wire l2c_snp_fwd_delay; + + assign l2c_snp_fwd_delay = (|per_core_dcache_snp_req_delay) || (|per_core_icache_snp_req_delay); + + + wire[`LLNUMBER_REQUESTS-1:0] l2c_wb; + wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr; + wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data; + + // endgenerate + + + + // + // generate + for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin + // Core Request + assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; + assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; + + assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write ? `SW_MEM_WRITE : `NO_MEM_WRITE; + assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write + + assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read ? `LW_MEM_READ : `NO_MEM_READ; + assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write + + assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read ? 1 : 0; + assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write + + assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)]; + assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)]; + + assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)]; + assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)]; + + // L2 can't accept requests + assign per_core_dram_fill_accept [(l2c_curr_core/2)] = l2c_core_accept; + assign per_core_I_dram_fill_accept[(l2c_curr_core/2)] = l2c_core_accept; + + // Cache Fill Response + assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; + assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; + + assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; + assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; + + assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; + assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; + + assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; + assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; + + assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; + assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; + end + // endgenerate + + wire dram_snp_full; + wire dram_req_because_of_wb; + + + VX_cache #( + .CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`LLNUMBER_BANKS), + .WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`LLNUMBER_REQUESTS), + .STAGE_1_CYCLES (`LLSTAGE_1_CYCLES), + .FUNC_ID (`LLFUNC_ID), + .REQQ_SIZE (`LLREQQ_SIZE), + .MRVQ_SIZE (`LLMRVQ_SIZE), + .DFPQ_SIZE (`LLDFPQ_SIZE), + .SNRQ_SIZE (`LLSNRQ_SIZE), + .CWBQ_SIZE (`LLCWBQ_SIZE), + .DWBQ_SIZE (`LLDWBQ_SIZE), + .DFQQ_SIZE (`LLDFQQ_SIZE), + .LLVQ_SIZE (`LLLLVQ_SIZE), + .FFSQ_SIZE (`LLFFSQ_SIZE), + .FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_l2cache + ( + .clk (clk), + .reset (reset), + + // Core Req (DRAM Fills/WB) To L2 Request + .core_req_valid (l2c_core_req), + .core_req_addr (l2c_core_req_addr), + .core_req_writedata({l2c_core_req_data}), + .core_req_mem_read (l2c_core_req_mem_read), + .core_req_mem_write(l2c_core_req_mem_write), + .core_req_rd (0), + .core_req_wb (l2c_core_req_wb), + .core_req_warp_num (0), + .core_req_pc (0), + + // L2 can't accept Core Request + .delay_req (l2c_core_accept), + + // Core can't accept L2 Request + .core_no_wb_slot (0), + + // Core Writeback + .core_wb_valid (l2c_wb), + .core_wb_req_rd (), + .core_wb_req_wb (), + .core_wb_warp_num (), + .core_wb_readdata ({l2c_wb_data}), + .core_wb_address (l2c_wb_addr), + .core_wb_pc (), + + // L2 Cache DRAM Fill response + .dram_fill_rsp (dram_fill_rsp[curr_cluster]), + .dram_fill_rsp_addr(dram_fill_rsp_addr[curr_cluster]), + .dram_fill_rsp_data({dram_fill_rsp_data[curr_cluster]}), + + // L2 Cache can't accept Fill Response + .dram_fill_accept (dram_fill_accept), + + // L2 Cache DRAM Fill Request + .dram_req (dram_req[curr_cluster]), + .dram_req_write (dram_req_write[curr_cluster]), + .dram_req_read (dram_req_read[curr_cluster]), + .dram_req_addr (dram_req_addr[curr_cluster]), + .dram_req_size (dram_req_size[curr_cluster]), + .dram_req_data ({dram_req_data[curr_cluster]}), + + // Snoop Response + .dram_req_because_of_wb(dram_req_because_of_wb), + .dram_snp_full (dram_snp_full), + + // Snoop Request + .snp_req (l3c_snp_fwd), + .snp_req_addr (l3c_snp_fwd_addr), + .snp_req_delay (l3c_snp_fwd_delay_temp[curr_cluster]), + + .snp_fwd (l2c_snp_fwd), + .snp_fwd_addr (l2c_snp_fwd_addr), + .snp_fwd_delay (l2c_snp_fwd_delay) + ); + + // // Snoop Request + // .snp_req (VX_gpu_icache_snp_req.snp_req), + // .snp_req_addr (VX_gpu_icache_snp_req.snp_req_addr), + // .snp_req_delay (VX_gpu_icache_snp_req.snp_delay), + + + + //////////////////// L2 Cache //////////////////// + + + //////////////////// END CLUSTER /////////////////// + end + endgenerate diff --git a/rtl/interfaces/VX_gpu_snp_req_rsp.v b/rtl/interfaces/VX_gpu_snp_req_rsp.v new file mode 100644 index 00000000..154abc0b --- /dev/null +++ b/rtl/interfaces/VX_gpu_snp_req_rsp.v @@ -0,0 +1,20 @@ +`include "../VX_cache/VX_cache_config.v" + +`ifndef VX_GPU_SNP_REQ_RSP + +`define VX_GPU_SNP_REQ_RSP + +interface VX_gpu_snp_req_rsp + (); + + // Snoop request + wire snp_req; + wire[31:0] snp_req_addr; + + // Snoop Response + wire snp_delay; + +endinterface + + +`endif \ No newline at end of file diff --git a/rtl/simulate/multi_test_bench.h b/rtl/simulate/multi_test_bench.h index 1b26b483..1e783ca0 100644 --- a/rtl/simulate/multi_test_bench.h +++ b/rtl/simulate/multi_test_bench.h @@ -209,15 +209,15 @@ bool Vortex::dbus_driver() } - if (vortex->dram_req) + if (vortex->out_dram_req) { - if (vortex->dram_req_read) + if (vortex->out_dram_req_read) { // Need to add an element dram_req_t dram_req; - dram_req.cycles_left = vortex->dram_expected_lat; - dram_req.data_length = vortex->dram_req_size / 4; - dram_req.base_addr = vortex->dram_req_addr; + dram_req.cycles_left = vortex->out_dram_expected_lat; + dram_req.data_length = vortex->out_dram_req_size / 4; + dram_req.base_addr = vortex->out_dram_req_addr; dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); for (int i = 0; i < dram_req.data_length; i++) @@ -231,29 +231,29 @@ bool Vortex::dbus_driver() this->dram_req_vec.push_back(dram_req); } - if (vortex->dram_req_write) + if (vortex->out_dram_req_write) { - unsigned base_addr = vortex->dram_req_addr; - unsigned data_length = vortex->dram_req_size / 4; + unsigned base_addr = vortex->out_dram_req_addr; + unsigned data_length = vortex->out_dram_req_size / 4; for (int i = 0; i < data_length; i++) { unsigned curr_addr = base_addr + (i*4); - unsigned data_wr = vortex->dram_req_data[i]; + unsigned data_wr = vortex->out_dram_req_data[i]; ram.writeWord(curr_addr, &data_wr); } } } - if (vortex->dram_fill_accept && dequeue_valid) + if (vortex->out_dram_fill_accept && dequeue_valid) { - vortex->dram_fill_rsp = 1; - vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; + vortex->out_dram_fill_rsp = 1; + vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) { - vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; + vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; } free(this->dram_req_vec[dequeue_index].data); @@ -261,8 +261,8 @@ bool Vortex::dbus_driver() } else { - vortex->dram_fill_rsp = 0; - vortex->dram_fill_rsp_addr = 0; + vortex->out_dram_fill_rsp = 0; + vortex->out_dram_fill_rsp_addr = 0; } return false; From 372a1ad905eb187831382149723199073e8295f8 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Tue, 10 Mar 2020 04:05:01 -0400 Subject: [PATCH 39/66] minor tweaks to appease quartus re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support --- rtl/Makefile | 2 +- rtl/VX_cache/VX_bank.v | 16 +++++++++------- rtl/VX_define.v | 8 ++++---- rtl/quartus/Makefile | 15 ++++++++------- rtl/quartus/VX_timing.tcl | 2 +- 5 files changed, 23 insertions(+), 20 deletions(-) diff --git a/rtl/Makefile b/rtl/Makefile index 44fabb61..32d21d2e 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -19,7 +19,7 @@ LIGHTW=-Wno-UNOPTFLAT # LIB=-LDFLAGS '-L/usr/local/systemc/' LIB= -CF=-CFLAGS '-std=c++11 -O3' +CF=-CFLAGS '-std=c++11 -fms-extensions' DEB=--trace --prof-cfuncs -DVL_DEBUG=1 diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index d61cc297..f0596d97 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -296,17 +296,19 @@ module VX_bank ); wire stall_bank_pipe; - reg is_fill_in_pipe; + reg is_fill_in_pipe; - genvar p_stage; + reg[16:0] p_stage; always @(*) begin - assign is_fill_in_pipe = 0; + is_fill_in_pipe = 0; for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin - if (is_fill_st1[p_stage]) assign is_fill_in_pipe = 1; + if (is_fill_st1[p_stage]) is_fill_in_pipe = 1; end - - if (is_fill_st2) assign is_fill_in_pipe = 1; + + if (is_fill_st2) is_fill_in_pipe = 1; end + +// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2; assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0; @@ -630,7 +632,7 @@ module VX_bank assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full); -endmodule +endmodule : VX_bank diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 19cf8fac..46948280 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -146,7 +146,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define DNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) - `define DSTAGE_1_CYCLES 2 + `define DSTAGE_1_CYCLES 4 // Function ID `define DFUNC_ID 0 @@ -199,7 +199,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define INUMBER_REQUESTS 1 // Number of cycles to complete stage 1 (read from memory) - `define ISTAGE_1_CYCLES 2 + `define ISTAGE_1_CYCLES 4 // Function ID `define IFUNC_ID 1 @@ -251,7 +251,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define SNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) - `define SSTAGE_1_CYCLES 2 + `define SSTAGE_1_CYCLES 4 // Function ID `define SFUNC_ID 2 @@ -305,7 +305,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER) // Number of cycles to complete stage 1 (read from memory) - `define LLSTAGE_1_CYCLES 2 + `define LLSTAGE_1_CYCLES 4 // Function ID `define LLFUNC_ID 3 diff --git a/rtl/quartus/Makefile b/rtl/quartus/Makefile index 8d6fe2f3..eb45c48d 100644 --- a/rtl/quartus/Makefile +++ b/rtl/quartus/Makefile @@ -32,26 +32,27 @@ smart: smart.log STAMP = echo done > $(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) + $(QUARTUS_ROOT)/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS) $(STAMP) fit.chg $(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) + $(QUARTUS_ROOT)/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS) $(STAMP) asm.chg $(STAMP) sta.chg $(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) + $(QUARTUS_ROOT)/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS) $(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) + $(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS) + $(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log + $(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log # Project initialization $(PROJECT_FILES): - quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../VX_cache;../shared_memory;../compat" + $(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../VX_cache;../shared_memory;../compat" syn.chg: $(STAMP) syn.chg @@ -66,7 +67,7 @@ asm.chg: $(STAMP) asm.chg program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" + $(QUARTUS_ROOT)/quartus/bin/quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" clean: rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/rtl/quartus/VX_timing.tcl b/rtl/quartus/VX_timing.tcl index 290c6054..d5408ad1 100644 --- a/rtl/quartus/VX_timing.tcl +++ b/rtl/quartus/VX_timing.tcl @@ -10,7 +10,7 @@ update_timing_netlist foreach_in_collection op [get_available_operating_conditions] { set_operating_conditions $op - report_timing -setup -npaths 20 -detail full_path -multi_corner \ + report_timing -setup -npaths 150 -detail full_path -multi_corner -pairs_only -nworst 8 \ -file "bin/timing_paths_$op.html" \ -panel_name "Critical paths for $op" From b1e77bec44bfc6ca43cfa66296c405634c05364f Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Tue, 10 Mar 2020 17:46:48 -0400 Subject: [PATCH 40/66] replace procedural continuous assignments and force MLAB inference for generic_queue_ll --- rtl/VX_cache/VX_cache_req_queue.v | 4 ++-- rtl/VX_cache/VX_snp_fwd_arb.v | 2 +- rtl/VX_generic_queue_ll.v | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index 5938d349..e4b20e80 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -166,9 +166,9 @@ module VX_cache_req_queue always @(*) begin - assign updated_valids = qual_valids; + updated_valids = qual_valids; if (qual_has_request) begin - assign updated_valids[qual_request_index] = 0; + updated_valids[qual_request_index] = 0; end end diff --git a/rtl/VX_cache/VX_snp_fwd_arb.v b/rtl/VX_cache/VX_snp_fwd_arb.v index 7f2d3e64..354e1fdd 100644 --- a/rtl/VX_cache/VX_snp_fwd_arb.v +++ b/rtl/VX_cache/VX_snp_fwd_arb.v @@ -30,7 +30,7 @@ module VX_snp_fwd_arb assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank]; always @(*) begin - assign per_bank_snp_fwd_pop = 0; + per_bank_snp_fwd_pop = 0; if (fsq_valid) begin per_bank_snp_fwd_pop[fsq_bank] = 1; end diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v index dfe7828b..40b4d8c7 100644 --- a/rtl/VX_generic_queue_ll.v +++ b/rtl/VX_generic_queue_ll.v @@ -24,7 +24,8 @@ module VX_generic_queue_ll assign full = 0; end else begin - reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r; + (* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0]; + reg[DATAW-1:0] curr_r, head_r; reg[$clog2(SIZE+1)-1:0] size_r; reg[$clog2(SIZE)-1:0] wr_ctr_r; reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r; From dd2c9cd9d79ed83c139237808c21a1dfbd9c9606 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Thu, 12 Mar 2020 13:14:50 -0400 Subject: [PATCH 41/66] Add power analysis Make target --- rtl/quartus/Makefile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/rtl/quartus/Makefile b/rtl/quartus/Makefile index eb45c48d..9c34e330 100644 --- a/rtl/quartus/Makefile +++ b/rtl/quartus/Makefile @@ -1,5 +1,5 @@ PROJECT = Vortex -TOP_LEVEL_ENTITY = Vortex +TOP_LEVEL_ENTITY = Vortex_SOC SRC_FILE = ../Vortex.v PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf @@ -16,7 +16,7 @@ ASM_ARGS = STA_ARGS = --do_report_timing # Build targets -all: $(PROJECT).sta.rpt +all: $(PROJECT).sta.rpt $(PROJECT).pow.rpt syn: $(PROJECT).syn.rpt @@ -26,6 +26,8 @@ asm: $(PROJECT).asm.rpt sta: $(PROJECT).sta.rpt +pow: $(PROJECT).pow.rpt + smart: smart.log # Target implementations @@ -47,6 +49,9 @@ $(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt $(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS) $(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl +$(PROJECT).pow.rpt: smart.log pow.chg $(PROJECT).fit.rpt + $(QUARTUS_ROOT)/quartus/bin/quartus_pow $(PROJECT) + smart.log: $(PROJECT_FILES) $(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log @@ -66,6 +71,9 @@ sta.chg: asm.chg: $(STAMP) asm.chg +pow.chg: + $(STAMP) pow.chg + program: $(PROJECT).sof $(QUARTUS_ROOT)/quartus/bin/quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" From fc94168e32e83cca2517b2085b727d6f802bcc8f Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Fri, 13 Mar 2020 15:01:46 -0700 Subject: [PATCH 42/66] Removed L3 for synthesis --- rtl/VX_define.v | 8 +- rtl/Vortex_SOC.v | 288 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 292 insertions(+), 4 deletions(-) diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 46948280..28eae94c 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -127,7 +127,7 @@ `define NUMBER_CORES_PER_CLUSTER 2 -`define NUMBER_CLUSTERS 2 +`define NUMBER_CLUSTERS 1 `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) // `define SINGLE_CORE_BENCH 0 @@ -251,7 +251,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define SNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) - `define SSTAGE_1_CYCLES 4 + `define SSTAGE_1_CYCLES 2 // Function ID `define SFUNC_ID 2 @@ -305,7 +305,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER) // Number of cycles to complete stage 1 (read from memory) - `define LLSTAGE_1_CYCLES 4 + `define LLSTAGE_1_CYCLES 2 // Function ID `define LLFUNC_ID 3 @@ -345,7 +345,7 @@ // ========================================= L3cache Configurable Knobs ========================================= - +// `define L3C 1 // General Cache Knobs // Size of cache in bytes `define L3CACHE_SIZE_BYTES 1024 diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index 9e9210fe..2a454d11 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -2,6 +2,8 @@ `include "VX_cache_config.v" module Vortex_SOC ( + +`ifdef L3C input wire clk, input wire reset, // IO @@ -31,8 +33,39 @@ module Vortex_SOC ( output wire out_ebreak + +`else + + input wire clk, + input wire reset, + // IO + output wire io_valid[`NUMBER_CORES-1:0], + output wire[31:0] io_data [`NUMBER_CORES-1:0], + + output wire[31:0] number_cores, + + // DRAM Dcache Req + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] dram_expected_lat, + + // DRAM Dcache Res + output wire dram_fill_accept, + input wire dram_fill_rsp, + input wire [31:0] dram_fill_rsp_addr, + input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + + + output wire out_ebreak + +`endif ); +`ifdef L3C // DRAM Dcache Req @@ -488,7 +521,262 @@ module Vortex_SOC ( end endgenerate +`else + + assign number_cores = `NUMBER_CORES; + + // IO + wire per_core_io_valid[`NUMBER_CORES-1:0]; + wire[31:0] per_core_io_data[`NUMBER_CORES-1:0]; + + // DRAM Dcache Req + wire[`NUMBER_CORES-1:0] per_core_dram_req; + wire[`NUMBER_CORES-1:0] per_core_dram_req_write; + wire[`NUMBER_CORES-1:0] per_core_dram_req_read; + wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_req_addr; + wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_req_size; + wire[`NUMBER_CORES-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data; + wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_expected_lat; + + // DRAM Dcache Res + wire[`NUMBER_CORES-1:0] per_core_dram_fill_accept; + wire[`NUMBER_CORES-1:0] per_core_dram_fill_rsp; + wire[`NUMBER_CORES-1:0] [31:0] per_core_dram_fill_rsp_addr; + wire[`NUMBER_CORES-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data; + + + // DRAM Icache Req + wire[`NUMBER_CORES-1:0] per_core_I_dram_req; + wire[`NUMBER_CORES-1:0] per_core_I_dram_req_write; + wire[`NUMBER_CORES-1:0] per_core_I_dram_req_read; + wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_req_addr; + wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_req_size; + wire[`NUMBER_CORES-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data; + wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_expected_lat; + + // DRAM Icache Res + wire[`NUMBER_CORES-1:0] per_core_I_dram_fill_accept; + wire[`NUMBER_CORES-1:0] per_core_I_dram_fill_rsp; + wire[`NUMBER_CORES-1:0] [31:0] per_core_I_dram_fill_rsp_addr; + wire[`NUMBER_CORES-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; + + // Out ebreak + wire[`NUMBER_CORES-1:0] per_core_out_ebreak; + + assign out_ebreak = (&per_core_out_ebreak); + + genvar curr_core; + generate + + for (curr_core = 0; curr_core < `NUMBER_CORES; curr_core=curr_core+1) begin + + wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data; + wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ; + + assign io_valid[curr_core] = per_core_io_valid[curr_core]; + assign io_data [curr_core] = per_core_io_data [curr_core]; + Vortex #(.CORE_ID(curr_core)) vortex_core( + .clk (clk), + .reset (reset), + .io_valid (per_core_io_valid [curr_core]), + .io_data (per_core_io_data [curr_core]), + .dram_req (per_core_dram_req [curr_core]), + .dram_req_write (per_core_dram_req_write [curr_core]), + .dram_req_read (per_core_dram_req_read [curr_core]), + .dram_req_addr (per_core_dram_req_addr [curr_core]), + .dram_req_size (per_core_dram_req_size [curr_core]), + .dram_req_data (curr_core_dram_req_data ), + .dram_expected_lat (per_core_dram_expected_lat [curr_core]), + .dram_fill_accept (per_core_dram_fill_accept [curr_core]), + .dram_fill_rsp (per_core_dram_fill_rsp [curr_core]), + .dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]), + .dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]), + .I_dram_req (per_core_I_dram_req [curr_core]), + .I_dram_req_write (per_core_I_dram_req_write [curr_core]), + .I_dram_req_read (per_core_I_dram_req_read [curr_core]), + .I_dram_req_addr (per_core_I_dram_req_addr [curr_core]), + .I_dram_req_size (per_core_I_dram_req_size [curr_core]), + .I_dram_req_data (curr_core_I_dram_req_data ), + .I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]), + .I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]), + .I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]), + .I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]), + .I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]), + .out_ebreak (per_core_out_ebreak [curr_core]) + ); + + assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data; + assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data; + end + endgenerate + + + //////////////////// L2 Cache //////////////////// + wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req; + wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write; + wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read; + wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr; + wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data; + wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb; + + wire l2c_core_accept; + + + wire[`LLNUMBER_REQUESTS-1:0] l2c_wb; + wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr; + wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data; + + + wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port; + wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port; + + genvar llb_index; + generate + for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin + assign dram_req_data [llb_index] = dram_req_data_port[llb_index]; + assign dram_fill_rsp_data_port[llb_index] = dram_fill_rsp_data[llb_index]; + end + endgenerate + + // genvar l2c_index; + // genvar l2c_bank_index; + // generate + // for (l2c_index = 0; l2c_index < `LLNUMBER_REQUESTS; l2c_index=l2c_index+1) begin + // assign l2c_wb [l2c_index] = l2c_wb_port [l2c_index]; + // assign l2c_wb_addr[l2c_index] = l2c_wb_addr_port[l2c_index]; + // for (l2c_bank_index = 0; l2c_bank_index < `LLNUMBER_REQUESTS; l2c_bank_index=l2c_bank_index+1) begin + // assign l2c_wb_data[l2c_index][l2c_bank_index] = l2c_wb_data_port[l2c_index][l2c_bank_index]; + // end + // end + // endgenerate + + + + // + genvar l2c_curr_core; + generate + for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin + // Core Request + assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)]; + assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)]; + + assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write ? `SW_MEM_WRITE : `NO_MEM_WRITE; + assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write + + assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read ? `LW_MEM_READ : `NO_MEM_READ; + assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write + + assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read ? 1 : 0; + assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write + + assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)]; + assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)]; + + assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)]; + assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)]; + + // L2 can't accept requests + assign per_core_dram_fill_accept [(l2c_curr_core/2)] = l2c_core_accept; + assign per_core_I_dram_fill_accept[(l2c_curr_core/2)] = l2c_core_accept; + + // Cache Fill Response + assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core]; + assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1]; + + assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core]; + assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1]; + + assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; + assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; + end + endgenerate + + wire dram_snp_full; + wire dram_req_because_of_wb; + VX_cache #( + .CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES), + .BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES), + .NUMBER_BANKS (`LLNUMBER_BANKS), + .WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES), + .NUMBER_REQUESTS (`LLNUMBER_REQUESTS), + .STAGE_1_CYCLES (`LLSTAGE_1_CYCLES), + .FUNC_ID (`LLFUNC_ID), + .REQQ_SIZE (`LLREQQ_SIZE), + .MRVQ_SIZE (`LLMRVQ_SIZE), + .DFPQ_SIZE (`LLDFPQ_SIZE), + .SNRQ_SIZE (`LLSNRQ_SIZE), + .CWBQ_SIZE (`LLCWBQ_SIZE), + .DWBQ_SIZE (`LLDWBQ_SIZE), + .DFQQ_SIZE (`LLDFQQ_SIZE), + .LLVQ_SIZE (`LLLLVQ_SIZE), + .FFSQ_SIZE (`LLFFSQ_SIZE), + .FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE), + .SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES) + ) + gpu_l2cache + ( + .clk (clk), + .reset (reset), + + // Core Req (DRAM Fills/WB) To L2 Request + .core_req_valid (l2c_core_req), + .core_req_addr (l2c_core_req_addr), + .core_req_writedata({l2c_core_req_data}), + .core_req_mem_read (l2c_core_req_mem_read), + .core_req_mem_write(l2c_core_req_mem_write), + .core_req_rd (0), + .core_req_wb (l2c_core_req_wb), + .core_req_warp_num (0), + .core_req_pc (0), + + // L2 can't accept Core Request + .delay_req (l2c_core_accept), + + // Core can't accept L2 Request + .core_no_wb_slot (0), + + // Core Writeback + .core_wb_valid (l2c_wb), + .core_wb_req_rd (), + .core_wb_req_wb (), + .core_wb_warp_num (), + .core_wb_readdata ({l2c_wb_data}), + .core_wb_address (l2c_wb_addr), + .core_wb_pc (), + + // L2 Cache DRAM Fill response + .dram_fill_rsp (dram_fill_rsp), + .dram_fill_rsp_addr(dram_fill_rsp_addr), + .dram_fill_rsp_data({dram_fill_rsp_data_port}), + + // L2 Cache can't accept Fill Response + .dram_fill_accept (dram_fill_accept), + + // L2 Cache DRAM Fill Request + .dram_req (dram_req), + .dram_req_write (dram_req_write), + .dram_req_read (dram_req_read), + .dram_req_addr (dram_req_addr), + .dram_req_size (dram_req_size), + .dram_req_data ({dram_req_data_port}), + + // Snoop Response + .dram_req_because_of_wb(dram_req_because_of_wb), + .dram_snp_full (dram_snp_full), + + // Snoop Request + .snp_req (0), + .snp_req_addr (0) + ); + + + + //////////////////// L2 Cache //////////////////// + + + +`endif endmodule \ No newline at end of file From 65f3ced608b9b1b57d2decb51f3ecadec465a392 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Fri, 13 Mar 2020 15:11:20 -0700 Subject: [PATCH 43/66] Fixed no L3 Verilator issues --- rtl/Vortex_SOC.v | 55 +++++++++++------------------------------------- 1 file changed, 12 insertions(+), 43 deletions(-) diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index 2a454d11..1d37b36d 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -3,7 +3,6 @@ module Vortex_SOC ( -`ifdef L3C input wire clk, input wire reset, // IO @@ -33,36 +32,6 @@ module Vortex_SOC ( output wire out_ebreak - -`else - - input wire clk, - input wire reset, - // IO - output wire io_valid[`NUMBER_CORES-1:0], - output wire[31:0] io_data [`NUMBER_CORES-1:0], - - output wire[31:0] number_cores, - - // DRAM Dcache Req - output wire dram_req, - output wire dram_req_write, - output wire dram_req_read, - output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, - output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], - output wire [31:0] dram_expected_lat, - - // DRAM Dcache Res - output wire dram_fill_accept, - input wire dram_fill_rsp, - input wire [31:0] dram_fill_rsp_addr, - input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], - - - output wire out_ebreak - -`endif ); `ifdef L3C @@ -634,8 +603,8 @@ module Vortex_SOC ( genvar llb_index; generate for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin - assign dram_req_data [llb_index] = dram_req_data_port[llb_index]; - assign dram_fill_rsp_data_port[llb_index] = dram_fill_rsp_data[llb_index]; + assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index]; + assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index]; end endgenerate @@ -746,19 +715,19 @@ module Vortex_SOC ( .core_wb_pc (), // L2 Cache DRAM Fill response - .dram_fill_rsp (dram_fill_rsp), - .dram_fill_rsp_addr(dram_fill_rsp_addr), + .dram_fill_rsp (out_dram_fill_rsp), + .dram_fill_rsp_addr(out_dram_fill_rsp_addr), .dram_fill_rsp_data({dram_fill_rsp_data_port}), // L2 Cache can't accept Fill Response - .dram_fill_accept (dram_fill_accept), + .dram_fill_accept (out_dram_fill_accept), // L2 Cache DRAM Fill Request - .dram_req (dram_req), - .dram_req_write (dram_req_write), - .dram_req_read (dram_req_read), - .dram_req_addr (dram_req_addr), - .dram_req_size (dram_req_size), + .dram_req (out_dram_req), + .dram_req_write (out_dram_req_write), + .dram_req_read (out_dram_req_read), + .dram_req_addr (out_dram_req_addr), + .dram_req_size (out_dram_req_size), .dram_req_data ({dram_req_data_port}), // Snoop Response @@ -766,8 +735,8 @@ module Vortex_SOC ( .dram_snp_full (dram_snp_full), // Snoop Request - .snp_req (0), - .snp_req_addr (0) + .snp_req (l3c_snp_req), + .snp_req_addr (l3c_snp_req_addr) ); From 05b7ffff129b2d0e1517f8c888a56e78fea86dec Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Fri, 20 Mar 2020 04:04:15 -0400 Subject: [PATCH 44/66] Add modified RTL files for parameterized builds with VX_define_synth.v --- .gitignore | 2 ++ rtl/Makefile | 2 +- rtl/VX_define.v | 18 ++++-------------- rtl/VX_define_synth.v | 16 +++++++++++++++- rtl/VX_generic_queue_ll.v | 8 +++++++- 5 files changed, 29 insertions(+), 17 deletions(-) diff --git a/.gitignore b/.gitignore index 925952d0..736cd776 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,5 @@ ./rtl/modelsim/*.vcd *.vcd .* +*.pyc +__pycache__ \ No newline at end of file diff --git a/rtl/Makefile b/rtl/Makefile index 32d21d2e..f685efd6 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -9,7 +9,7 @@ MULTI_CORE=Vortex_SOC.v EXE=--exe ./simulate/test_bench.cpp MULTI_EXE=--exe ./simulate/multi_test_bench.cpp -COMP=--compiler gcc +COMP=--compiler gcc --language 1800-2009 WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN # WNO= diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 28eae94c..9b0aa1bf 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -125,9 +125,6 @@ -199 - -`define NUMBER_CORES_PER_CLUSTER 2 -`define NUMBER_CLUSTERS 1 `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) // `define SINGLE_CORE_BENCH 0 @@ -135,8 +132,6 @@ // ========================================= Dcache Configurable Knobs ========================================= // General Cache Knobs - // Size of cache in bytes - `define DCACHE_SIZE_BYTES 1024 // Size of line inside a bank in bytes `define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES // Number of banks {1, 2, 4, 8,...} @@ -156,9 +151,9 @@ // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size - `define DREQQ_SIZE `NT*`NW + `define DREQQ_SIZE `NW // Miss Reserv Queue Knob - `define DMRVQ_SIZE `DREQQ_SIZE + `define DMRVQ_SIZE (`NW*`NT) // Dram Fill Rsp Queue Size `define DDFPQ_SIZE 2 // Snoop Req Queue @@ -188,8 +183,6 @@ // ========================================= Icache Configurable Knobs ========================================= // General Cache Knobs - // Size of cache in bytes - `define ICACHE_SIZE_BYTES 1024 // Size of line inside a bank in bytes `define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES // Number of banks {1, 2, 4, 8,...} @@ -294,8 +287,6 @@ // ========================================= L2cache Configurable Knobs ========================================= // General Cache Knobs - // Size of cache in bytes - `define LLCACHE_SIZE_BYTES 1024 // Size of line inside a bank in bytes `define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES // Number of banks {1, 2, 4, 8,...} @@ -315,9 +306,9 @@ // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size - `define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES_PER_CLUSTER) + `define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER) // Miss Reserv Queue Knob - `define LLMRVQ_SIZE `LLREQQ_SIZE + `define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER) // Dram Fill Rsp Queue Size `define LLDFPQ_SIZE 2 // Snoop Req Queue @@ -345,7 +336,6 @@ // ========================================= L3cache Configurable Knobs ========================================= -// `define L3C 1 // General Cache Knobs // Size of cache in bytes `define L3CACHE_SIZE_BYTES 1024 diff --git a/rtl/VX_define_synth.v b/rtl/VX_define_synth.v index ac029146..9a4eedaa 100644 --- a/rtl/VX_define_synth.v +++ b/rtl/VX_define_synth.v @@ -1,7 +1,21 @@ + `ifndef VX_DEFINE_SYNTH `define VX_DEFINE_SYNTH -`define NT 2 +`define NT 4 `define NW 8 +`define NUMBER_CORES_PER_CLUSTER 2 +`define NUMBER_CLUSTERS 1 +`define DCACHE_SIZE_BYTES 4096 +`define ICACHE_SIZE_BYTES 1024 + +// L2 Cache size +`define LLCACHE_SIZE_BYTES 8192 + + +// `define QUEUE_FORCE_MLAB 1 + +// Use l3 cache (required for cluster behavior) +// `define L3C 1 `endif diff --git a/rtl/VX_generic_queue_ll.v b/rtl/VX_generic_queue_ll.v index 40b4d8c7..75215486 100644 --- a/rtl/VX_generic_queue_ll.v +++ b/rtl/VX_generic_queue_ll.v @@ -1,3 +1,4 @@ +`include "VX_define_synth.v" module VX_generic_queue_ll #( @@ -24,7 +25,12 @@ module VX_generic_queue_ll assign full = 0; end else begin - (* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0]; + `ifdef QUEUE_FORCE_MLAB + (* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0]; + `else + reg[DATAW-1:0] data[SIZE-1:0]; + `endif + reg[DATAW-1:0] curr_r, head_r; reg[$clog2(SIZE+1)-1:0] size_r; reg[$clog2(SIZE)-1:0] wr_ctr_r; From 1c82f9a11d4cc68e032eb814b4a95cc9a10a4881 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Fri, 20 Mar 2020 04:49:02 -0400 Subject: [PATCH 45/66] revert saxpy change and fix stage_1_cycles not working --- benchmarks/opencl/saxpy/main.cc | 2 +- rtl/VX_define.v | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/benchmarks/opencl/saxpy/main.cc b/benchmarks/opencl/saxpy/main.cc index 865bedf9..9cf5d774 100644 --- a/benchmarks/opencl/saxpy/main.cc +++ b/benchmarks/opencl/saxpy/main.cc @@ -153,7 +153,7 @@ int main(int argc, char **argv) { } cl_event kernel_completion; - size_t global_work_size[1] = {NUM_DATA/2,NUM_DATA/2}; + size_t global_work_size[1] = {NUM_DATA}; printf("attempting to enqueue kernel\n"); fflush(stdout); CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, global_work_size, diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 9b0aa1bf..57ba27f7 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -141,7 +141,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define DNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) - `define DSTAGE_1_CYCLES 4 + `define DSTAGE_1_CYCLES 2 // Function ID `define DFUNC_ID 0 @@ -192,7 +192,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define INUMBER_REQUESTS 1 // Number of cycles to complete stage 1 (read from memory) - `define ISTAGE_1_CYCLES 4 + `define ISTAGE_1_CYCLES 2 // Function ID `define IFUNC_ID 1 From 902aa685b1520f1670be0efb75dffa559555bd42 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Fri, 20 Mar 2020 18:15:49 -0400 Subject: [PATCH 46/66] Add threaded -O3 build mode --- rtl/Makefile | 17 +++++++++++++++++ rtl/VX_writeback.v | 3 ++- rtl/simulate/test_bench.cpp | 3 ++- rtl/simulate/test_bench.h | 3 ++- 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/rtl/Makefile b/rtl/Makefile index f685efd6..a99fd562 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -21,13 +21,19 @@ LIB= CF=-CFLAGS '-std=c++11 -fms-extensions' +CFRel=-CFLAGS '-std=c++11 -fms-extensions -O3 -DVL_THREADED' + DEB=--trace --prof-cfuncs -DVL_DEBUG=1 MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) +MAKECPPRel=(cd obj_dir && make -j -f VVortex.mk) + MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) +THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))' ) + # -LDFLAGS '-lsystemc' VERILATOR: echo "#define VCD_OFF" > simulate/tb_debug.h @@ -37,6 +43,11 @@ VERILATORnoWarnings: echo "#define VCD_OFF" > simulate/tb_debug.h verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB) +VERILATORnoWarningsRel: + echo "#define VCD_OFF" > simulate/tb_debug.h + verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CFRel) $(WNO) --threads $(THREADS) + + VERILATORMULTInoWarnings: echo "#define VCD_OFF" > simulate/tb_debug.h verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) $(CF) $(WNO) $(DEB) @@ -58,6 +69,9 @@ debug: compdebug w: VERILATORnoWarnings $(MAKECPP) +wRel: VERILATORnoWarningsRel + $(MAKECPPRel) + multicore: VERILATORMULTInoWarnings $(MAKEMULTICPP) @@ -67,5 +81,8 @@ dmulticore: compdebugmulti run: w (cd obj_dir && ./VVortex) +runRel: wRel + (cd obj_dir && ./VVortex) + clean: rm obj_dir/* diff --git a/rtl/VX_writeback.v b/rtl/VX_writeback.v index ee65dca8..2cba499a 100644 --- a/rtl/VX_writeback.v +++ b/rtl/VX_writeback.v @@ -75,7 +75,8 @@ module VX_writeback ( .out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc}) ); - reg[31:0] last_data_wb; + + reg[31:0] last_data_wb /* verilator public */ ; always @(posedge clk) begin if ((|VX_writeback_inter.wb_valid) && (VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd == 28)) begin last_data_wb <= use_wb_data[0]; diff --git a/rtl/simulate/test_bench.cpp b/rtl/simulate/test_bench.cpp index 8b2e7e9e..0d03f4bf 100644 --- a/rtl/simulate/test_bench.cpp +++ b/rtl/simulate/test_bench.cpp @@ -15,7 +15,8 @@ int main(int argc, char **argv) #define ALL_TESTS #ifdef ALL_TESTS bool passed = true; - std::string tests[NUM_TESTS] = { + + std::string tests[NUM_TESTS] = { "../../emulator/riscv_tests/rv32ui-p-add.hex", "../../emulator/riscv_tests/rv32ui-p-addi.hex", "../../emulator/riscv_tests/rv32ui-p-and.hex", diff --git a/rtl/simulate/test_bench.h b/rtl/simulate/test_bench.h index 69e2d257..e8c5f222 100644 --- a/rtl/simulate/test_bench.h +++ b/rtl/simulate/test_bench.h @@ -13,6 +13,7 @@ #include "VX_define.h" #include "ram.h" #include "VVortex.h" +#include "VVortex__Syms.h" #include "verilated.h" #include "tb_debug.h" @@ -462,7 +463,7 @@ bool Vortex::simulate(std::string file_to_simulate) std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; - int status = (unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf; + int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf; // std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n"; From d146070275638e96a9d436f02cae9d80d91f844a Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 22 Mar 2020 14:44:46 -0700 Subject: [PATCH 47/66] Fix for Single-Threaded --- rtl/VX_cache/VX_bank.v | 4 +- rtl/VX_cache/VX_fill_invalidator.v | 2 +- rtl/VX_cache/VX_tag_data_access.v | 46 +- rtl/VX_cache/VX_tag_data_structure.v | 1 + rtl/VX_define.v | 40 +- rtl/VX_define_synth.v | 4 +- rtl/VX_generic_register.v | 30 +- rtl/VX_gpgpu_inst.v | 10 +- rtl/VX_warp_scheduler.v | 4 +- runtime/mains/simple/Makefile | 8 +- runtime/mains/simple/vx_simple_main.c | 12 + runtime/mains/simple/vx_simple_main.dump | 82323 ++++++++++----------- runtime/mains/simple/vx_simple_main.elf | Bin 256980 -> 256904 bytes runtime/mains/simple/vx_simple_main.hex | 11269 +-- runtime/startup/vx_start.s | 26 +- runtime/tests/tests.c | 2 + 16 files changed, 46894 insertions(+), 46887 deletions(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index f0596d97..355e15c8 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -311,8 +311,8 @@ module VX_bank // assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2; - assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0; - assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0; + assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0; + assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0; assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe; assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0; diff --git a/rtl/VX_cache/VX_fill_invalidator.v b/rtl/VX_cache/VX_fill_invalidator.v index e5c0ae10..10b7c73c 100644 --- a/rtl/VX_cache/VX_fill_invalidator.v +++ b/rtl/VX_cache/VX_fill_invalidator.v @@ -85,7 +85,7 @@ module VX_fill_invalidator if (success_fill) begin success_found = 1; - success_index = curr_fill[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0]; + success_index = curr_fill; end end end diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 25f04692..2c75745b 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -73,12 +73,12 @@ module VX_tag_data_access ); - reg[`DBANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-2:0]; + reg[`DBANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-1:0]; - reg read_valid_st1c[STAGE_1_CYCLES-2:0]; - reg read_dirty_st1c[STAGE_1_CYCLES-2:0]; - reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-2:0]; - reg[`DBANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-2:0]; + reg read_valid_st1c[STAGE_1_CYCLES-1:0]; + reg read_dirty_st1c[STAGE_1_CYCLES-1:0]; + reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-1:0]; + reg[`DBANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-1:0]; wire qual_read_valid_st1; @@ -94,6 +94,9 @@ module VX_tag_data_access wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data; + wire real_writefill = writefill_st1e && miss_st1e; + + wire fill_sent; wire invalidate_line; VX_tag_data_structure #( @@ -128,13 +131,14 @@ module VX_tag_data_access .invalidate (invalidate_line), .write_enable(use_write_enable), - .write_fill (writefill_st1e), + .write_fill (real_writefill), .write_addr (writeaddr_st1e), .write_data (use_write_data), .fill_sent (fill_sent) ); - VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_c0 ( + // VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_c0 ( + VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) ), .Valid(0)) s0_1_c0 ( .clk (clk), .reset(reset), .stall(stall), @@ -145,7 +149,7 @@ module VX_tag_data_access genvar curr_stage; generate - for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-2; curr_stage = curr_stage + 1) begin + for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-1; curr_stage = curr_stage + 1) begin VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_cc ( .clk (clk), .reset(reset), @@ -158,13 +162,13 @@ module VX_tag_data_access endgenerate - assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-2] || (FUNC_ID == `SFUNC_ID); // If shared memory, always valid - assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-2] && (FUNC_ID == `DFUNC_ID); // Dirty only applies in Dcache - assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-2]; // Tag is always the same in SM + assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || (FUNC_ID == `SFUNC_ID); // If shared memory, always valid + assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && (FUNC_ID != `SFUNC_ID); // Dirty only applies in Dcache + assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-1]; // Tag is always the same in SM genvar curr_w; - for (curr_w = 0; curr_w < `DBANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-2][curr_w][31:0]; - // assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-2]; + for (curr_w = 0; curr_w < `DBANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-1][curr_w][31:0]; + // assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-1]; /////////////////////// LOAD LOGIC /////////////////// @@ -182,12 +186,12 @@ module VX_tag_data_access wire b2 = (byte_select == 2); wire b3 = (byte_select == 3); - wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-2][0][31:0]; - wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-2][1][31:0]; - wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-2][2][31:0]; - wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-2][3][31:0]; + wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0]; + wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0]; + wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0]; + wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0]; - wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-2][block_offset][31:0]; + wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset][31:0]; wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) : b1 ? (data_unmod >> 8) : @@ -234,7 +238,7 @@ module VX_tag_data_access wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e; - wire force_write = writefill_st1e && valid_req_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e)); + wire force_write = writefill_st1e && valid_req_st1e && miss_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e)); wire[`DBANK_LINE_SIZE_RNG][3:0] we; wire[`DBANK_LINE_SIZE_RNG][31:0] data_write; @@ -262,7 +266,7 @@ module VX_tag_data_access /////////////////////// if (FUNC_ID == `LLFUNC_ID) begin - assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-2]; + assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-1]; end else begin assign readword_st1e = data_Qual; end @@ -272,7 +276,7 @@ module VX_tag_data_access assign readdata_st1e = use_read_data_st1e; assign readtag_st1e = use_read_tag_st1e; assign fill_sent = miss_st1e; - assign fill_saw_dirty_st1e = force_write && dirty_st1e; + assign fill_saw_dirty_st1e = force_write && dirty_st1e && miss_st1e; assign invalidate_line = is_snp_st1e && !miss_st1e; endmodule diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index c7edb6a6..55b9cc9e 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -92,6 +92,7 @@ module VX_tag_data_structure end end else if (fill_sent) begin dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; + valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0; end if (invalidate) begin diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 57ba27f7..3d1b0a5f 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -127,7 +127,7 @@ `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) -// `define SINGLE_CORE_BENCH 0 +`define SINGLE_CORE_BENCH 1 `define GLOBAL_BLOCK_SIZE_BYTES 16 // ========================================= Dcache Configurable Knobs ========================================= @@ -141,7 +141,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define DNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) - `define DSTAGE_1_CYCLES 2 + `define DSTAGE_1_CYCLES 1 // Function ID `define DFUNC_ID 0 @@ -172,7 +172,7 @@ `define DFFSQ_SIZE 8 // Fill Invalidator Size {Fill invalidator must be active} - `define DFILL_INVALIDAOR_SIZE 16 + `define DFILL_INVALIDAOR_SIZE 0 // Dram knobs `define DSIMULATED_DRAM_LATENCY_CYCLES 10 @@ -192,7 +192,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define INUMBER_REQUESTS 1 // Number of cycles to complete stage 1 (read from memory) - `define ISTAGE_1_CYCLES 2 + `define ISTAGE_1_CYCLES 1 // Function ID `define IFUNC_ID 1 @@ -214,16 +214,16 @@ // Core Writeback Queue Size `define ICWBQ_SIZE `IREQQ_SIZE // Dram Writeback Queue Size - `define IDWBQ_SIZE 0 + `define IDWBQ_SIZE 16 // Dram Fill Req Queue Size `define IDFQQ_SIZE `IREQQ_SIZE // Lower Level Cache Hit Queue Size - `define ILLVQ_SIZE 0 + `define ILLVQ_SIZE 16 // Fill Forward SNP Queue `define IFFSQ_SIZE 8 // Fill Invalidator Size {Fill invalidator must be active} - `define IFILL_INVALIDAOR_SIZE 16 + `define IFILL_INVALIDAOR_SIZE 0 // Dram knobs `define ISIMULATED_DRAM_LATENCY_CYCLES 10 @@ -244,7 +244,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define SNUMBER_REQUESTS `NT // Number of cycles to complete stage 1 (read from memory) - `define SSTAGE_1_CYCLES 2 + `define SSTAGE_1_CYCLES 1 // Function ID `define SFUNC_ID 2 @@ -258,24 +258,24 @@ // Miss Reserv Queue Knob `define SMRVQ_SIZE `SREQQ_SIZE // Dram Fill Rsp Queue Size - `define SDFPQ_SIZE 0 + `define SDFPQ_SIZE 16 // Snoop Req Queue - `define SSNRQ_SIZE 0 + `define SSNRQ_SIZE 16 // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size `define SCWBQ_SIZE `SREQQ_SIZE // Dram Writeback Queue Size - `define SDWBQ_SIZE 0 + `define SDWBQ_SIZE 16 // Dram Fill Req Queue Size - `define SDFQQ_SIZE 0 + `define SDFQQ_SIZE 16 // Lower Level Cache Hit Queue Size - `define SLLVQ_SIZE 0 + `define SLLVQ_SIZE 16 // Fill Forward SNP Queue - `define SFFSQ_SIZE 0 + `define SFFSQ_SIZE 16 // Fill Invalidator Size {Fill invalidator must be active} - `define SFILL_INVALIDAOR_SIZE 16 + `define SFILL_INVALIDAOR_SIZE 0 // Dram knobs `define SSIMULATED_DRAM_LATENCY_CYCLES 10 @@ -296,7 +296,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER) // Number of cycles to complete stage 1 (read from memory) - `define LLSTAGE_1_CYCLES 2 + `define LLSTAGE_1_CYCLES 1 // Function ID `define LLFUNC_ID 3 @@ -322,12 +322,12 @@ // Dram Fill Req Queue Size `define LLDFQQ_SIZE `LLREQQ_SIZE // Lower Level Cache Hit Queue Size - `define LLLLVQ_SIZE 0 + `define LLLLVQ_SIZE 16 // Fill Forward SNP Queue `define LLFFSQ_SIZE 8 // Fill Invalidator Size {Fill invalidator must be active} - `define LLFILL_INVALIDAOR_SIZE 16 + `define LLFILL_INVALIDAOR_SIZE 0 // Dram knobs `define LLSIMULATED_DRAM_LATENCY_CYCLES 10 @@ -348,7 +348,7 @@ // Number of Word requests per cycle {1, 2, 4, 8, ...} `define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS) // Number of cycles to complete stage 1 (read from memory) - `define L3STAGE_1_CYCLES 2 + `define L3STAGE_1_CYCLES 1 // Function ID `define L3FUNC_ID 3 @@ -379,7 +379,7 @@ `define L3FFSQ_SIZE 8 // Fill Invalidator Size {Fill invalidator must be active} - `define L3FILL_INVALIDAOR_SIZE 16 + `define L3FILL_INVALIDAOR_SIZE 0 // Dram knobs `define L3SIMULATED_DRAM_LATENCY_CYCLES 10 diff --git a/rtl/VX_define_synth.v b/rtl/VX_define_synth.v index 9a4eedaa..a55023d9 100644 --- a/rtl/VX_define_synth.v +++ b/rtl/VX_define_synth.v @@ -2,9 +2,9 @@ `ifndef VX_DEFINE_SYNTH `define VX_DEFINE_SYNTH -`define NT 4 +`define NT 8 `define NW 8 -`define NUMBER_CORES_PER_CLUSTER 2 +`define NUMBER_CORES_PER_CLUSTER 1 `define NUMBER_CLUSTERS 1 `define DCACHE_SIZE_BYTES 4096 `define ICACHE_SIZE_BYTES 1024 diff --git a/rtl/VX_generic_register.v b/rtl/VX_generic_register.v index a26c09b3..b960fa8c 100644 --- a/rtl/VX_generic_register.v +++ b/rtl/VX_generic_register.v @@ -1,6 +1,6 @@ module VX_generic_register - #( parameter N = 1) + #( parameter N = 1, parameter Valid = 1) ( input wire clk, input wire reset, @@ -10,18 +10,26 @@ module VX_generic_register output wire[(N-1):0] out ); - reg[(N-1):0] value; + if (Valid == 0) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - value <= 0; - end else if (flush) begin - value <= 0; - end else if (~stall) begin - value <= in; + assign out = in; + + end else begin + + reg[(N-1):0] value; + + always @(posedge clk or posedge reset) begin + if (reset) begin + value <= 0; + end else if (flush) begin + value <= 0; + end else if (~stall) begin + value <= in; + end end + + assign out = value; + end - assign out = value; - endmodule \ No newline at end of file diff --git a/rtl/VX_gpgpu_inst.v b/rtl/VX_gpgpu_inst.v index dc81d718..6219eeb2 100644 --- a/rtl/VX_gpgpu_inst.v +++ b/rtl/VX_gpgpu_inst.v @@ -13,10 +13,11 @@ module VX_gpgpu_inst ( wire is_split = (VX_gpu_inst_req.is_split); wire[`NT_M1:0] tmc_new_mask; + wire all_threads = `NT < VX_gpu_inst_req.a_reg_data[0]; genvar curr_t; generate for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin : tmc_new_mask_init - assign tmc_new_mask[curr_t] = curr_t < VX_gpu_inst_req.a_reg_data[0]; + assign tmc_new_mask[curr_t] = all_threads ? 1 : curr_t < VX_gpu_inst_req.a_reg_data[0]; end endgenerate @@ -30,13 +31,14 @@ module VX_gpgpu_inst ( assign VX_warp_ctl.ebreak = VX_warp_ctl.change_mask && (VX_warp_ctl.thread_mask == 0); - wire wspawn = VX_gpu_inst_req.is_wspawn; - wire[31:0] wspawn_pc = VX_gpu_inst_req.rd2; + wire wspawn = VX_gpu_inst_req.is_wspawn; + wire[31:0] wspawn_pc = VX_gpu_inst_req.rd2; + wire all_active = `NW < VX_gpu_inst_req.a_reg_data[0]; wire[`NW-1:0] wspawn_new_active; genvar curr_w; generate for (curr_w = 0; curr_w < `NW; curr_w=curr_w+1) begin : wspawn_new_active_init - assign wspawn_new_active[curr_w] = curr_w < VX_gpu_inst_req.a_reg_data[0]; + assign wspawn_new_active[curr_w] = all_active ? 1 : curr_w < VX_gpu_inst_req.a_reg_data[0]; end endgenerate diff --git a/rtl/VX_warp_scheduler.v b/rtl/VX_warp_scheduler.v index a976bcf0..a20af31e 100644 --- a/rtl/VX_warp_scheduler.v +++ b/rtl/VX_warp_scheduler.v @@ -218,9 +218,11 @@ module VX_warp_scheduler ( // Lock/Release if (scheduled_warp && !stall) begin warp_lock[warp_num] <= 1'b1; + // warp_lock <= {`NW{1'b1}}; end if (|icache_stage_valids && !stall) begin warp_lock[icache_stage_wid] <= 1'b0; + // warp_lock <= {`NW{1'b0}}; end end @@ -292,7 +294,7 @@ module VX_warp_scheduler ( assign hazard = (should_jal || should_bra) && schedule; - assign real_schedule = schedule && !warp_stalled[warp_to_schedule] && !total_barrier_stall[warp_to_schedule]; + assign real_schedule = schedule && !warp_stalled[warp_to_schedule] && !total_barrier_stall[warp_to_schedule] && !warp_lock[0]; assign global_stall = (stall || wstall_this_cycle || hazard || !real_schedule || is_join); diff --git a/runtime/mains/simple/Makefile b/runtime/mains/simple/Makefile index 1d2cedae..d1823e85 100644 --- a/runtime/mains/simple/Makefile +++ b/runtime/mains/simple/Makefile @@ -1,9 +1,9 @@ -COMP = riscv32-unknown-elf-gcc +COMP = /opt/riscv-new/drops/bin/riscv32-unknown-elf-gcc CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,../vortex_link.ld -ffreestanding -nostdlib -DMP = riscv32-unknown-elf-objdump -CPY = riscv32-unknown-elf-objcopy +DMP = /opt/riscv-new/drops/bin/riscv32-unknown-elf-objdump +CPY = /opt/riscv-new/drops/bin/riscv32-unknown-elf-objcopy NEWLIB = ../../newlib/newlib.c @@ -13,7 +13,7 @@ VX_IO = ../../io/vx_io.s ../../io/vx_io.c VX_API = ../../vx_api/vx_api.c VX_TEST = ../../tests/tests.c VX_FIO = ../../fileio/fileio.s -LIBS = ../../../../riscv-gnu-toolchain/drops/riscv32-unknown-elf/lib/libc.a ../../../../riscv-gnu-toolchain/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc +LIBS = /opt/riscv-new/drops/riscv32-unknown-elf/lib/libc.a /opt/riscv-new/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc VX_MAIN = vx_simple_main diff --git a/runtime/mains/simple/vx_simple_main.c b/runtime/mains/simple/vx_simple_main.c index a5ffd350..05bfea84 100644 --- a/runtime/mains/simple/vx_simple_main.c +++ b/runtime/mains/simple/vx_simple_main.c @@ -52,6 +52,18 @@ int main() // Main is called with all threads active of warp 0 vx_tmc(1); + vx_print_str("Let's start...\n"); + unsigned what[36]; + for (int i = 0; i < 36; i++) + { + what[i] = i; + } + + for (int i = 0; i < 36; i++) + { + vx_printf("Value: ", what[i]); + } + vx_print_str("Simple Main\n"); diff --git a/runtime/mains/simple/vx_simple_main.dump b/runtime/mains/simple/vx_simple_main.dump index 97c6482b..c1e051f4 100644 --- a/runtime/mains/simple/vx_simple_main.dump +++ b/runtime/mains/simple/vx_simple_main.dump @@ -6,23247 +6,23206 @@ Disassembly of section .init: 80000000 <_start>: 80000000: 00000597 auipc a1,0x0 -80000004: 06c58593 addi a1,a1,108 # 8000006c +80000004: 03858593 addi a1,a1,56 # 80000038 80000008: 00400513 li a0,4 8000000c: 00b5106b 0xb5106b -80000010: 05c000ef jal ra,8000006c -80000014: 00100513 li a0,1 -80000018: 0005006b 0x5006b -8000001c: 36c18513 addi a0,gp,876 # 80016b74 <_edata> -80000020: 42818613 addi a2,gp,1064 # 80016c30 <__BSS_END__> -80000024: 40a60633 sub a2,a2,a0 -80000028: 00000593 li a1,0 -8000002c: 30c010ef jal ra,80001338 -80000030: 00001517 auipc a0,0x1 -80000034: 21050513 addi a0,a0,528 # 80001240 <__libc_fini_array> -80000038: 1c4010ef jal ra,800011fc -8000003c: 260010ef jal ra,8000129c <__libc_init_array> -80000040: 00400513 li a0,4 -80000044: 0005006b 0x5006b -80000048: 7ad000ef jal ra,80000ff4
-8000004c: 1c40106f j 80001210 +80000010: 028000ef jal ra,80000038 +80000014: 0b8010ef jal ra,800010cc
+80000018: 3440106f j 8000135c Disassembly of section .text: -80000050 : -80000050: 000007b7 lui a5,0x0 -80000054: 00078793 mv a5,a5 -80000058: 00078863 beqz a5,80000068 -8000005c: 80001537 lui a0,0x80001 -80000060: 24050513 addi a0,a0,576 # 80001240 <__BSS_END__+0xfffea610> -80000064: 1980106f j 800011fc -80000068: 00008067 ret +8000001c : +8000001c: 000007b7 lui a5,0x0 +80000020: 00078793 mv a5,a5 +80000024: 00078863 beqz a5,80000034 +80000028: 80005537 lui a0,0x80005 +8000002c: 84850513 addi a0,a0,-1976 # 80004848 <__BSS_END__+0xfffedc0c> +80000030: 1cc0406f j 800041fc +80000034: 00008067 ret -8000006c : -8000006c: 00400513 li a0,4 -80000070: 0005006b 0x5006b -80000074: 00016197 auipc gp,0x16 -80000078: 79418193 addi gp,gp,1940 # 80016808 <__global_pointer$> -8000007c: 021026f3 csrr a3,0x21 -80000080: 01a69693 slli a3,a3,0x1a -80000084: 02002673 csrr a2,0x20 -80000088: 00a61593 slli a1,a2,0xa -8000008c: 00261613 slli a2,a2,0x2 -80000090: 6ffff137 lui sp,0x6ffff -80000094: 40b10133 sub sp,sp,a1 -80000098: 40d10133 sub sp,sp,a3 -8000009c: 00c10133 add sp,sp,a2 -800000a0: 021026f3 csrr a3,0x21 -800000a4: 00068663 beqz a3,800000b0 -800000a8: 00000513 li a0,0 -800000ac: 0005006b 0x5006b +80000038 : +80000038: 00400513 li a0,4 +8000003c: 0005006b 0x5006b +80000040: 00016197 auipc gp,0x16 +80000044: 7c818193 addi gp,gp,1992 # 80016808 <__global_pointer$> +80000048: 022026f3 csrr a3,0x22 +8000004c: 01a69693 slli a3,a3,0x1a +80000050: 02002673 csrr a2,0x20 +80000054: 00a61593 slli a1,a2,0xa +80000058: 00261613 slli a2,a2,0x2 +8000005c: 6ffff137 lui sp,0x6ffff +80000060: 40b10133 sub sp,sp,a1 +80000064: 40d10133 sub sp,sp,a3 +80000068: 00c10133 add sp,sp,a2 +8000006c: 021026f3 csrr a3,0x21 +80000070: 00068663 beqz a3,8000007c +80000074: 00000513 li a0,0 +80000078: 0005006b 0x5006b -800000b0 : -800000b0: 00008067 ret +8000007c : +8000007c: 00008067 ret -800000b4 : -800000b4: fd010113 addi sp,sp,-48 # 6fffefd0 <_start-0x10001030> -800000b8: 02812623 sw s0,44(sp) -800000bc: 03010413 addi s0,sp,48 -800000c0: fca42e23 sw a0,-36(s0) -800000c4: fcb42c23 sw a1,-40(s0) -800000c8: fcc42a23 sw a2,-44(s0) -800000cc: fdc42783 lw a5,-36(s0) -800000d0: 0007a783 lw a5,0(a5) # 0 <_start-0x80000000> -800000d4: fef42623 sw a5,-20(s0) -800000d8: fd440793 addi a5,s0,-44 -800000dc: fef42223 sw a5,-28(s0) -800000e0: fe442783 lw a5,-28(s0) -800000e4: 0007c703 lbu a4,0(a5) -800000e8: fec42783 lw a5,-20(s0) -800000ec: 00e78023 sb a4,0(a5) -800000f0: fec42783 lw a5,-20(s0) -800000f4: 00178793 addi a5,a5,1 -800000f8: fe442703 lw a4,-28(s0) -800000fc: 00174703 lbu a4,1(a4) -80000100: 00e78023 sb a4,0(a5) -80000104: fec42783 lw a5,-20(s0) -80000108: 00278793 addi a5,a5,2 -8000010c: fe442703 lw a4,-28(s0) -80000110: 00274703 lbu a4,2(a4) -80000114: 00e78023 sb a4,0(a5) -80000118: fec42783 lw a5,-20(s0) -8000011c: 00378793 addi a5,a5,3 -80000120: fe442703 lw a4,-28(s0) -80000124: 00374703 lbu a4,3(a4) -80000128: 00e78023 sb a4,0(a5) -8000012c: fec42783 lw a5,-20(s0) -80000130: 00478793 addi a5,a5,4 -80000134: fef42623 sw a5,-20(s0) -80000138: fe042423 sw zero,-24(s0) -8000013c: 0340006f j 80000170 -80000140: fe842783 lw a5,-24(s0) -80000144: fd842703 lw a4,-40(s0) -80000148: 00f707b3 add a5,a4,a5 -8000014c: 0007c703 lbu a4,0(a5) -80000150: fec42783 lw a5,-20(s0) -80000154: 00e78023 sb a4,0(a5) -80000158: fec42783 lw a5,-20(s0) -8000015c: 00178793 addi a5,a5,1 -80000160: fef42623 sw a5,-20(s0) -80000164: fe842783 lw a5,-24(s0) -80000168: 00178793 addi a5,a5,1 -8000016c: fef42423 sw a5,-24(s0) -80000170: fd442783 lw a5,-44(s0) -80000174: fe842703 lw a4,-24(s0) -80000178: fcf744e3 blt a4,a5,80000140 -8000017c: fec42783 lw a5,-20(s0) -80000180: fef42023 sw a5,-32(s0) -80000184: fe042783 lw a5,-32(s0) -80000188: 0037f793 andi a5,a5,3 -8000018c: fe042703 lw a4,-32(s0) -80000190: 00f707b3 add a5,a4,a5 -80000194: fef42023 sw a5,-32(s0) -80000198: fe042783 lw a5,-32(s0) -8000019c: fef42623 sw a5,-20(s0) -800001a0: fdc42783 lw a5,-36(s0) -800001a4: fec42703 lw a4,-20(s0) -800001a8: 00e7a023 sw a4,0(a5) -800001ac: 00000013 nop -800001b0: 02c12403 lw s0,44(sp) -800001b4: 03010113 addi sp,sp,48 -800001b8: 00008067 ret +80000080 : +80000080: fd010113 addi sp,sp,-48 # 6fffefd0 <_start-0x10001030> +80000084: 02812623 sw s0,44(sp) +80000088: 03010413 addi s0,sp,48 +8000008c: fca42e23 sw a0,-36(s0) +80000090: fcb42c23 sw a1,-40(s0) +80000094: fcc42a23 sw a2,-44(s0) +80000098: fdc42783 lw a5,-36(s0) +8000009c: 0007a783 lw a5,0(a5) # 0 <_start-0x80000000> +800000a0: fef42623 sw a5,-20(s0) +800000a4: fd440793 addi a5,s0,-44 +800000a8: fef42223 sw a5,-28(s0) +800000ac: fe442783 lw a5,-28(s0) +800000b0: 0007c703 lbu a4,0(a5) +800000b4: fec42783 lw a5,-20(s0) +800000b8: 00e78023 sb a4,0(a5) +800000bc: fec42783 lw a5,-20(s0) +800000c0: 00178793 addi a5,a5,1 +800000c4: fe442703 lw a4,-28(s0) +800000c8: 00174703 lbu a4,1(a4) +800000cc: 00e78023 sb a4,0(a5) +800000d0: fec42783 lw a5,-20(s0) +800000d4: 00278793 addi a5,a5,2 +800000d8: fe442703 lw a4,-28(s0) +800000dc: 00274703 lbu a4,2(a4) +800000e0: 00e78023 sb a4,0(a5) +800000e4: fec42783 lw a5,-20(s0) +800000e8: 00378793 addi a5,a5,3 +800000ec: fe442703 lw a4,-28(s0) +800000f0: 00374703 lbu a4,3(a4) +800000f4: 00e78023 sb a4,0(a5) +800000f8: fec42783 lw a5,-20(s0) +800000fc: 00478793 addi a5,a5,4 +80000100: fef42623 sw a5,-20(s0) +80000104: fe042423 sw zero,-24(s0) +80000108: 0340006f j 8000013c +8000010c: fe842783 lw a5,-24(s0) +80000110: fd842703 lw a4,-40(s0) +80000114: 00f707b3 add a5,a4,a5 +80000118: 0007c703 lbu a4,0(a5) +8000011c: fec42783 lw a5,-20(s0) +80000120: 00e78023 sb a4,0(a5) +80000124: fec42783 lw a5,-20(s0) +80000128: 00178793 addi a5,a5,1 +8000012c: fef42623 sw a5,-20(s0) +80000130: fe842783 lw a5,-24(s0) +80000134: 00178793 addi a5,a5,1 +80000138: fef42423 sw a5,-24(s0) +8000013c: fd442783 lw a5,-44(s0) +80000140: fe842703 lw a4,-24(s0) +80000144: fcf744e3 blt a4,a5,8000010c +80000148: fec42783 lw a5,-20(s0) +8000014c: fef42023 sw a5,-32(s0) +80000150: fe042783 lw a5,-32(s0) +80000154: 0037f793 andi a5,a5,3 +80000158: fe042703 lw a4,-32(s0) +8000015c: 00f707b3 add a5,a4,a5 +80000160: fef42023 sw a5,-32(s0) +80000164: fe042783 lw a5,-32(s0) +80000168: fef42623 sw a5,-20(s0) +8000016c: fdc42783 lw a5,-36(s0) +80000170: fec42703 lw a4,-20(s0) +80000174: 00e7a023 sw a4,0(a5) +80000178: 00000013 nop +8000017c: 02c12403 lw s0,44(sp) +80000180: 03010113 addi sp,sp,48 +80000184: 00008067 ret -800001bc : -800001bc: fc010113 addi sp,sp,-64 -800001c0: 02812e23 sw s0,60(sp) -800001c4: 04010413 addi s0,sp,64 -800001c8: fca42623 sw a0,-52(s0) -800001cc: fcb42423 sw a1,-56(s0) -800001d0: fcc42783 lw a5,-52(s0) -800001d4: 0007a783 lw a5,0(a5) -800001d8: fef42623 sw a5,-20(s0) -800001dc: fdc40793 addi a5,s0,-36 -800001e0: fef42223 sw a5,-28(s0) -800001e4: fec42783 lw a5,-20(s0) -800001e8: 0007c703 lbu a4,0(a5) -800001ec: fe442783 lw a5,-28(s0) -800001f0: 00e78023 sb a4,0(a5) -800001f4: fe442783 lw a5,-28(s0) -800001f8: 00178793 addi a5,a5,1 -800001fc: fec42703 lw a4,-20(s0) -80000200: 00174703 lbu a4,1(a4) -80000204: 00e78023 sb a4,0(a5) -80000208: fe442783 lw a5,-28(s0) -8000020c: 00278793 addi a5,a5,2 -80000210: fec42703 lw a4,-20(s0) -80000214: 00274703 lbu a4,2(a4) -80000218: 00e78023 sb a4,0(a5) -8000021c: fe442783 lw a5,-28(s0) -80000220: 00378793 addi a5,a5,3 -80000224: fec42703 lw a4,-20(s0) -80000228: 00374703 lbu a4,3(a4) -8000022c: 00e78023 sb a4,0(a5) -80000230: fec42783 lw a5,-20(s0) -80000234: 00478793 addi a5,a5,4 -80000238: fef42623 sw a5,-20(s0) -8000023c: fe042423 sw zero,-24(s0) -80000240: 0340006f j 80000274 -80000244: fe842783 lw a5,-24(s0) -80000248: fc842703 lw a4,-56(s0) -8000024c: 00f707b3 add a5,a4,a5 -80000250: fec42703 lw a4,-20(s0) -80000254: 00074703 lbu a4,0(a4) -80000258: 00e78023 sb a4,0(a5) -8000025c: fec42783 lw a5,-20(s0) -80000260: 00178793 addi a5,a5,1 -80000264: fef42623 sw a5,-20(s0) -80000268: fe842783 lw a5,-24(s0) -8000026c: 00178793 addi a5,a5,1 -80000270: fef42423 sw a5,-24(s0) -80000274: fdc42783 lw a5,-36(s0) -80000278: fe842703 lw a4,-24(s0) -8000027c: fcf744e3 blt a4,a5,80000244 -80000280: fec42783 lw a5,-20(s0) -80000284: fef42023 sw a5,-32(s0) -80000288: fe042783 lw a5,-32(s0) -8000028c: 0037f793 andi a5,a5,3 -80000290: fe042703 lw a4,-32(s0) -80000294: 00f707b3 add a5,a4,a5 -80000298: fef42023 sw a5,-32(s0) -8000029c: fe042783 lw a5,-32(s0) -800002a0: fef42623 sw a5,-20(s0) -800002a4: fcc42783 lw a5,-52(s0) -800002a8: fec42703 lw a4,-20(s0) -800002ac: 00e7a023 sw a4,0(a5) -800002b0: 00000013 nop -800002b4: 03c12403 lw s0,60(sp) -800002b8: 04010113 addi sp,sp,64 -800002bc: 00008067 ret +80000188 : +80000188: fc010113 addi sp,sp,-64 +8000018c: 02812e23 sw s0,60(sp) +80000190: 04010413 addi s0,sp,64 +80000194: fca42623 sw a0,-52(s0) +80000198: fcb42423 sw a1,-56(s0) +8000019c: fcc42783 lw a5,-52(s0) +800001a0: 0007a783 lw a5,0(a5) +800001a4: fef42623 sw a5,-20(s0) +800001a8: fdc40793 addi a5,s0,-36 +800001ac: fef42223 sw a5,-28(s0) +800001b0: fec42783 lw a5,-20(s0) +800001b4: 0007c703 lbu a4,0(a5) +800001b8: fe442783 lw a5,-28(s0) +800001bc: 00e78023 sb a4,0(a5) +800001c0: fe442783 lw a5,-28(s0) +800001c4: 00178793 addi a5,a5,1 +800001c8: fec42703 lw a4,-20(s0) +800001cc: 00174703 lbu a4,1(a4) +800001d0: 00e78023 sb a4,0(a5) +800001d4: fe442783 lw a5,-28(s0) +800001d8: 00278793 addi a5,a5,2 +800001dc: fec42703 lw a4,-20(s0) +800001e0: 00274703 lbu a4,2(a4) +800001e4: 00e78023 sb a4,0(a5) +800001e8: fe442783 lw a5,-28(s0) +800001ec: 00378793 addi a5,a5,3 +800001f0: fec42703 lw a4,-20(s0) +800001f4: 00374703 lbu a4,3(a4) +800001f8: 00e78023 sb a4,0(a5) +800001fc: fec42783 lw a5,-20(s0) +80000200: 00478793 addi a5,a5,4 +80000204: fef42623 sw a5,-20(s0) +80000208: fe042423 sw zero,-24(s0) +8000020c: 0340006f j 80000240 +80000210: fe842783 lw a5,-24(s0) +80000214: fc842703 lw a4,-56(s0) +80000218: 00f707b3 add a5,a4,a5 +8000021c: fec42703 lw a4,-20(s0) +80000220: 00074703 lbu a4,0(a4) +80000224: 00e78023 sb a4,0(a5) +80000228: fec42783 lw a5,-20(s0) +8000022c: 00178793 addi a5,a5,1 +80000230: fef42623 sw a5,-20(s0) +80000234: fe842783 lw a5,-24(s0) +80000238: 00178793 addi a5,a5,1 +8000023c: fef42423 sw a5,-24(s0) +80000240: fdc42783 lw a5,-36(s0) +80000244: fe842703 lw a4,-24(s0) +80000248: fcf744e3 blt a4,a5,80000210 +8000024c: fec42783 lw a5,-20(s0) +80000250: fef42023 sw a5,-32(s0) +80000254: fe042783 lw a5,-32(s0) +80000258: 0037f793 andi a5,a5,3 +8000025c: fe042703 lw a4,-32(s0) +80000260: 00f707b3 add a5,a4,a5 +80000264: fef42023 sw a5,-32(s0) +80000268: fe042783 lw a5,-32(s0) +8000026c: fef42623 sw a5,-20(s0) +80000270: fcc42783 lw a5,-52(s0) +80000274: fec42703 lw a4,-20(s0) +80000278: 00e7a023 sw a4,0(a5) +8000027c: 00000013 nop +80000280: 03c12403 lw s0,60(sp) +80000284: 04010113 addi sp,sp,64 +80000288: 00008067 ret -800002c0 <_close>: -800002c0: ff010113 addi sp,sp,-16 -800002c4: 00812623 sw s0,12(sp) -800002c8: 01010413 addi s0,sp,16 -800002cc: 00000013 nop -800002d0: 00c12403 lw s0,12(sp) -800002d4: 01010113 addi sp,sp,16 +8000028c <_close>: +8000028c: ff010113 addi sp,sp,-16 +80000290: 00812623 sw s0,12(sp) +80000294: 01010413 addi s0,sp,16 +80000298: 00000013 nop +8000029c: 00c12403 lw s0,12(sp) +800002a0: 01010113 addi sp,sp,16 +800002a4: 00008067 ret + +800002a8 <_fstat>: +800002a8: fe010113 addi sp,sp,-32 +800002ac: 00812e23 sw s0,28(sp) +800002b0: 02010413 addi s0,sp,32 +800002b4: fea42623 sw a0,-20(s0) +800002b8: feb42423 sw a1,-24(s0) +800002bc: fe842783 lw a5,-24(s0) +800002c0: 00002737 lui a4,0x2 +800002c4: 00e7a223 sw a4,4(a5) +800002c8: 00000793 li a5,0 +800002cc: 00078513 mv a0,a5 +800002d0: 01c12403 lw s0,28(sp) +800002d4: 02010113 addi sp,sp,32 800002d8: 00008067 ret -800002dc <_fstat>: +800002dc <_isatty>: 800002dc: fe010113 addi sp,sp,-32 800002e0: 00812e23 sw s0,28(sp) 800002e4: 02010413 addi s0,sp,32 800002e8: fea42623 sw a0,-20(s0) -800002ec: feb42423 sw a1,-24(s0) -800002f0: fe842783 lw a5,-24(s0) -800002f4: 00002737 lui a4,0x2 -800002f8: 00e7a223 sw a4,4(a5) -800002fc: 00000793 li a5,0 -80000300: 00078513 mv a0,a5 -80000304: 01c12403 lw s0,28(sp) -80000308: 02010113 addi sp,sp,32 -8000030c: 00008067 ret +800002ec: 00100793 li a5,1 +800002f0: 00078513 mv a0,a5 +800002f4: 01c12403 lw s0,28(sp) +800002f8: 02010113 addi sp,sp,32 +800002fc: 00008067 ret -80000310 <_isatty>: -80000310: fe010113 addi sp,sp,-32 -80000314: 00112e23 sw ra,28(sp) -80000318: 00812c23 sw s0,24(sp) -8000031c: 02010413 addi s0,sp,32 -80000320: fea42623 sw a0,-20(s0) -80000324: 800157b7 lui a5,0x80015 -80000328: 99078513 addi a0,a5,-1648 # 80014990 <__BSS_END__+0xffffdd60> -8000032c: 4fc000ef jal ra,80000828 -80000330: 00100793 li a5,1 -80000334: 00078513 mv a0,a5 -80000338: 01c12083 lw ra,28(sp) -8000033c: 01812403 lw s0,24(sp) -80000340: 02010113 addi sp,sp,32 -80000344: 00008067 ret - -80000348 <_lseek>: -80000348: fd010113 addi sp,sp,-48 -8000034c: 02112623 sw ra,44(sp) -80000350: 02812423 sw s0,40(sp) -80000354: 03010413 addi s0,sp,48 -80000358: fca42e23 sw a0,-36(s0) -8000035c: fcb42c23 sw a1,-40(s0) -80000360: fcc42a23 sw a2,-44(s0) -80000364: 710007b7 lui a5,0x71000 -80000368: fef42623 sw a5,-20(s0) -8000036c: 720007b7 lui a5,0x72000 -80000370: fef42423 sw a5,-24(s0) -80000374: 00300793 li a5,3 -80000378: fef42223 sw a5,-28(s0) -8000037c: fe440713 addi a4,s0,-28 +80000300 <_lseek>: +80000300: fd010113 addi sp,sp,-48 +80000304: 02112623 sw ra,44(sp) +80000308: 02812423 sw s0,40(sp) +8000030c: 03010413 addi s0,sp,48 +80000310: fca42e23 sw a0,-36(s0) +80000314: fcb42c23 sw a1,-40(s0) +80000318: fcc42a23 sw a2,-44(s0) +8000031c: 710007b7 lui a5,0x71000 +80000320: fef42623 sw a5,-20(s0) +80000324: 720007b7 lui a5,0x72000 +80000328: fef42423 sw a5,-24(s0) +8000032c: 00300793 li a5,3 +80000330: fef42223 sw a5,-28(s0) +80000334: fe440713 addi a4,s0,-28 +80000338: fec40793 addi a5,s0,-20 +8000033c: 00400613 li a2,4 +80000340: 00070593 mv a1,a4 +80000344: 00078513 mv a0,a5 +80000348: d39ff0ef jal ra,80000080 +8000034c: fdc40713 addi a4,s0,-36 +80000350: fec40793 addi a5,s0,-20 +80000354: 00400613 li a2,4 +80000358: 00070593 mv a1,a4 +8000035c: 00078513 mv a0,a5 +80000360: d21ff0ef jal ra,80000080 +80000364: fd840713 addi a4,s0,-40 +80000368: fec40793 addi a5,s0,-20 +8000036c: 00400613 li a2,4 +80000370: 00070593 mv a1,a4 +80000374: 00078513 mv a0,a5 +80000378: d09ff0ef jal ra,80000080 +8000037c: fd440713 addi a4,s0,-44 80000380: fec40793 addi a5,s0,-20 80000384: 00400613 li a2,4 80000388: 00070593 mv a1,a4 8000038c: 00078513 mv a0,a5 -80000390: d25ff0ef jal ra,800000b4 -80000394: fdc40713 addi a4,s0,-36 -80000398: fec40793 addi a5,s0,-20 -8000039c: 00400613 li a2,4 -800003a0: 00070593 mv a1,a4 -800003a4: 00078513 mv a0,a5 -800003a8: d0dff0ef jal ra,800000b4 -800003ac: fd840713 addi a4,s0,-40 -800003b0: fec40793 addi a5,s0,-20 -800003b4: 00400613 li a2,4 -800003b8: 00070593 mv a1,a4 -800003bc: 00078513 mv a0,a5 -800003c0: cf5ff0ef jal ra,800000b4 -800003c4: fd440713 addi a4,s0,-44 -800003c8: fec40793 addi a5,s0,-20 -800003cc: 00400613 li a2,4 -800003d0: 00070593 mv a1,a4 -800003d4: 00078513 mv a0,a5 -800003d8: cddff0ef jal ra,800000b4 -800003dc: 3541a783 lw a5,852(gp) # 80016b5c -800003e0: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -800003e4: fe040713 addi a4,s0,-32 -800003e8: fe840793 addi a5,s0,-24 -800003ec: 00070593 mv a1,a4 -800003f0: 00078513 mv a0,a5 -800003f4: dc9ff0ef jal ra,800001bc -800003f8: fe042783 lw a5,-32(s0) -800003fc: 00078513 mv a0,a5 -80000400: 02c12083 lw ra,44(sp) -80000404: 02812403 lw s0,40(sp) -80000408: 03010113 addi sp,sp,48 -8000040c: 00008067 ret +80000390: cf1ff0ef jal ra,80000080 +80000394: 3541a783 lw a5,852(gp) # 80016b5c +80000398: 000780e7 jalr a5 # 72000000 <_start-0xe000000> +8000039c: fe040713 addi a4,s0,-32 +800003a0: fe840793 addi a5,s0,-24 +800003a4: 00070593 mv a1,a4 +800003a8: 00078513 mv a0,a5 +800003ac: dddff0ef jal ra,80000188 +800003b0: fe042783 lw a5,-32(s0) +800003b4: 00078513 mv a0,a5 +800003b8: 02c12083 lw ra,44(sp) +800003bc: 02812403 lw s0,40(sp) +800003c0: 03010113 addi sp,sp,48 +800003c4: 00008067 ret -80000410 <_read>: -80000410: fd010113 addi sp,sp,-48 -80000414: 02112623 sw ra,44(sp) -80000418: 02812423 sw s0,40(sp) -8000041c: 03010413 addi s0,sp,48 -80000420: fca42e23 sw a0,-36(s0) -80000424: fcb42c23 sw a1,-40(s0) -80000428: fcc42a23 sw a2,-44(s0) -8000042c: 710007b7 lui a5,0x71000 -80000430: fef42423 sw a5,-24(s0) -80000434: 720007b7 lui a5,0x72000 -80000438: fef42623 sw a5,-20(s0) -8000043c: 00400793 li a5,4 -80000440: fef42223 sw a5,-28(s0) -80000444: fe440713 addi a4,s0,-28 +800003c8 <_read>: +800003c8: fd010113 addi sp,sp,-48 +800003cc: 02112623 sw ra,44(sp) +800003d0: 02812423 sw s0,40(sp) +800003d4: 03010413 addi s0,sp,48 +800003d8: fca42e23 sw a0,-36(s0) +800003dc: fcb42c23 sw a1,-40(s0) +800003e0: fcc42a23 sw a2,-44(s0) +800003e4: 710007b7 lui a5,0x71000 +800003e8: fef42423 sw a5,-24(s0) +800003ec: 720007b7 lui a5,0x72000 +800003f0: fef42623 sw a5,-20(s0) +800003f4: 00400793 li a5,4 +800003f8: fef42223 sw a5,-28(s0) +800003fc: fe440713 addi a4,s0,-28 +80000400: fe840793 addi a5,s0,-24 +80000404: 00400613 li a2,4 +80000408: 00070593 mv a1,a4 +8000040c: 00078513 mv a0,a5 +80000410: c71ff0ef jal ra,80000080 +80000414: fdc40713 addi a4,s0,-36 +80000418: fe840793 addi a5,s0,-24 +8000041c: 00400613 li a2,4 +80000420: 00070593 mv a1,a4 +80000424: 00078513 mv a0,a5 +80000428: c59ff0ef jal ra,80000080 +8000042c: fd840713 addi a4,s0,-40 +80000430: fe840793 addi a5,s0,-24 +80000434: 00400613 li a2,4 +80000438: 00070593 mv a1,a4 +8000043c: 00078513 mv a0,a5 +80000440: c41ff0ef jal ra,80000080 +80000444: fd440713 addi a4,s0,-44 80000448: fe840793 addi a5,s0,-24 8000044c: 00400613 li a2,4 80000450: 00070593 mv a1,a4 80000454: 00078513 mv a0,a5 -80000458: c5dff0ef jal ra,800000b4 -8000045c: fdc40713 addi a4,s0,-36 -80000460: fe840793 addi a5,s0,-24 -80000464: 00400613 li a2,4 -80000468: 00070593 mv a1,a4 -8000046c: 00078513 mv a0,a5 -80000470: c45ff0ef jal ra,800000b4 -80000474: fd840713 addi a4,s0,-40 -80000478: fe840793 addi a5,s0,-24 -8000047c: 00400613 li a2,4 -80000480: 00070593 mv a1,a4 -80000484: 00078513 mv a0,a5 -80000488: c2dff0ef jal ra,800000b4 -8000048c: fd440713 addi a4,s0,-44 -80000490: fe840793 addi a5,s0,-24 -80000494: 00400613 li a2,4 -80000498: 00070593 mv a1,a4 -8000049c: 00078513 mv a0,a5 -800004a0: c15ff0ef jal ra,800000b4 -800004a4: 3541a783 lw a5,852(gp) # 80016b5c -800004a8: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -800004ac: fd442783 lw a5,-44(s0) -800004b0: 00078513 mv a0,a5 -800004b4: 02c12083 lw ra,44(sp) -800004b8: 02812403 lw s0,40(sp) -800004bc: 03010113 addi sp,sp,48 -800004c0: 00008067 ret +80000458: c29ff0ef jal ra,80000080 +8000045c: 3541a783 lw a5,852(gp) # 80016b5c +80000460: 000780e7 jalr a5 # 72000000 <_start-0xe000000> +80000464: fd442783 lw a5,-44(s0) +80000468: 00078513 mv a0,a5 +8000046c: 02c12083 lw ra,44(sp) +80000470: 02812403 lw s0,40(sp) +80000474: 03010113 addi sp,sp,48 +80000478: 00008067 ret -800004c4 <_write>: -800004c4: fd010113 addi sp,sp,-48 -800004c8: 02112623 sw ra,44(sp) -800004cc: 02812423 sw s0,40(sp) -800004d0: 03010413 addi s0,sp,48 -800004d4: fca42e23 sw a0,-36(s0) -800004d8: fcb42c23 sw a1,-40(s0) -800004dc: fcc42a23 sw a2,-44(s0) -800004e0: 710007b7 lui a5,0x71000 -800004e4: fef42623 sw a5,-20(s0) -800004e8: 00500793 li a5,5 -800004ec: fef42423 sw a5,-24(s0) -800004f0: fe840713 addi a4,s0,-24 -800004f4: fec40793 addi a5,s0,-20 -800004f8: 00400613 li a2,4 -800004fc: 00070593 mv a1,a4 -80000500: 00078513 mv a0,a5 -80000504: bb1ff0ef jal ra,800000b4 -80000508: fdc40713 addi a4,s0,-36 -8000050c: fec40793 addi a5,s0,-20 -80000510: 00400613 li a2,4 -80000514: 00070593 mv a1,a4 -80000518: 00078513 mv a0,a5 -8000051c: b99ff0ef jal ra,800000b4 -80000520: fec40793 addi a5,s0,-20 -80000524: fd442603 lw a2,-44(s0) -80000528: fd842583 lw a1,-40(s0) -8000052c: 00078513 mv a0,a5 -80000530: b85ff0ef jal ra,800000b4 -80000534: 3541a783 lw a5,852(gp) # 80016b5c -80000538: 000780e7 jalr a5 # 71000000 <_start-0xf000000> -8000053c: fd442783 lw a5,-44(s0) -80000540: 00078513 mv a0,a5 -80000544: 02c12083 lw ra,44(sp) -80000548: 02812403 lw s0,40(sp) -8000054c: 03010113 addi sp,sp,48 -80000550: 00008067 ret +8000047c <_write>: +8000047c: fd010113 addi sp,sp,-48 +80000480: 02112623 sw ra,44(sp) +80000484: 02812423 sw s0,40(sp) +80000488: 03010413 addi s0,sp,48 +8000048c: fca42e23 sw a0,-36(s0) +80000490: fcb42c23 sw a1,-40(s0) +80000494: fcc42a23 sw a2,-44(s0) +80000498: 710007b7 lui a5,0x71000 +8000049c: fef42623 sw a5,-20(s0) +800004a0: 00500793 li a5,5 +800004a4: fef42423 sw a5,-24(s0) +800004a8: fe840713 addi a4,s0,-24 +800004ac: fec40793 addi a5,s0,-20 +800004b0: 00400613 li a2,4 +800004b4: 00070593 mv a1,a4 +800004b8: 00078513 mv a0,a5 +800004bc: bc5ff0ef jal ra,80000080 +800004c0: fdc40713 addi a4,s0,-36 +800004c4: fec40793 addi a5,s0,-20 +800004c8: 00400613 li a2,4 +800004cc: 00070593 mv a1,a4 +800004d0: 00078513 mv a0,a5 +800004d4: badff0ef jal ra,80000080 +800004d8: fec40793 addi a5,s0,-20 +800004dc: fd442603 lw a2,-44(s0) +800004e0: fd842583 lw a1,-40(s0) +800004e4: 00078513 mv a0,a5 +800004e8: b99ff0ef jal ra,80000080 +800004ec: 3541a783 lw a5,852(gp) # 80016b5c +800004f0: 000780e7 jalr a5 # 71000000 <_start-0xf000000> +800004f4: fd442783 lw a5,-44(s0) +800004f8: 00078513 mv a0,a5 +800004fc: 02c12083 lw ra,44(sp) +80000500: 02812403 lw s0,40(sp) +80000504: 03010113 addi sp,sp,48 +80000508: 00008067 ret -80000554 <_sbrk>: -80000554: fd010113 addi sp,sp,-48 -80000558: 02812623 sw s0,44(sp) -8000055c: 03010413 addi s0,sp,48 -80000560: fca42e23 sw a0,-36(s0) -80000564: fdc42783 lw a5,-36(s0) -80000568: 0007d863 bgez a5,80000578 <_sbrk+0x24> -8000056c: fdc42783 lw a5,-36(s0) -80000570: 40f007b3 neg a5,a5 -80000574: fcf42e23 sw a5,-36(s0) -80000578: fdc42703 lw a4,-36(s0) -8000057c: 000037b7 lui a5,0x3 -80000580: 80078793 addi a5,a5,-2048 # 2800 <_start-0x7fffd800> -80000584: 00e7d863 bge a5,a4,80000594 <_sbrk+0x40> -80000588: 000037b7 lui a5,0x3 -8000058c: 80078793 addi a5,a5,-2048 # 2800 <_start-0x7fffd800> -80000590: fcf42e23 sw a5,-36(s0) -80000594: 3581a783 lw a5,856(gp) # 80016b60 -80000598: fef42623 sw a5,-20(s0) -8000059c: 3581a703 lw a4,856(gp) # 80016b60 -800005a0: fdc42783 lw a5,-36(s0) -800005a4: 00f70733 add a4,a4,a5 -800005a8: 34e1ac23 sw a4,856(gp) # 80016b60 -800005ac: fec42783 lw a5,-20(s0) -800005b0: 00078513 mv a0,a5 -800005b4: 02c12403 lw s0,44(sp) -800005b8: 03010113 addi sp,sp,48 -800005bc: 00008067 ret +8000050c <_sbrk>: +8000050c: fd010113 addi sp,sp,-48 +80000510: 02812623 sw s0,44(sp) +80000514: 03010413 addi s0,sp,48 +80000518: fca42e23 sw a0,-36(s0) +8000051c: fdc42783 lw a5,-36(s0) +80000520: 0007d863 bgez a5,80000530 <_sbrk+0x24> +80000524: fdc42783 lw a5,-36(s0) +80000528: 40f007b3 neg a5,a5 +8000052c: fcf42e23 sw a5,-36(s0) +80000530: 3581a783 lw a5,856(gp) # 80016b60 +80000534: fef42623 sw a5,-20(s0) +80000538: 3581a703 lw a4,856(gp) # 80016b60 +8000053c: fdc42783 lw a5,-36(s0) +80000540: 00f70733 add a4,a4,a5 +80000544: 34e1ac23 sw a4,856(gp) # 80016b60 +80000548: fec42783 lw a5,-20(s0) +8000054c: 00078513 mv a0,a5 +80000550: 02c12403 lw s0,44(sp) +80000554: 03010113 addi sp,sp,48 +80000558: 00008067 ret -800005c0 <_exit>: -800005c0: fe010113 addi sp,sp,-32 -800005c4: 00112e23 sw ra,28(sp) -800005c8: 00812c23 sw s0,24(sp) -800005cc: 02010413 addi s0,sp,32 -800005d0: fea42623 sw a0,-20(s0) -800005d4: 00000513 li a0,0 -800005d8: 1e0000ef jal ra,800007b8 -800005dc: 00000013 nop -800005e0: 01c12083 lw ra,28(sp) -800005e4: 01812403 lw s0,24(sp) -800005e8: 02010113 addi sp,sp,32 -800005ec: 00008067 ret +8000055c <_exit>: +8000055c: fe010113 addi sp,sp,-32 +80000560: 00112e23 sw ra,28(sp) +80000564: 00812c23 sw s0,24(sp) +80000568: 02010413 addi s0,sp,32 +8000056c: fea42623 sw a0,-20(s0) +80000570: 00000513 li a0,0 +80000574: 1c8000ef jal ra,8000073c +80000578: 00000013 nop +8000057c: 01c12083 lw ra,28(sp) +80000580: 01812403 lw s0,24(sp) +80000584: 02010113 addi sp,sp,32 +80000588: 00008067 ret -800005f0 <_open>: -800005f0: fd010113 addi sp,sp,-48 -800005f4: 02112623 sw ra,44(sp) -800005f8: 02812423 sw s0,40(sp) -800005fc: 03010413 addi s0,sp,48 -80000600: fca42e23 sw a0,-36(s0) -80000604: fcb42c23 sw a1,-40(s0) -80000608: fcc42a23 sw a2,-44(s0) -8000060c: 710007b7 lui a5,0x71000 -80000610: fef42623 sw a5,-20(s0) -80000614: 720007b7 lui a5,0x72000 -80000618: fef42423 sw a5,-24(s0) -8000061c: 00700793 li a5,7 -80000620: fef42223 sw a5,-28(s0) -80000624: fe440713 addi a4,s0,-28 -80000628: fec40793 addi a5,s0,-20 -8000062c: 00400613 li a2,4 +8000058c <_open>: +8000058c: fd010113 addi sp,sp,-48 +80000590: 02112623 sw ra,44(sp) +80000594: 02812423 sw s0,40(sp) +80000598: 03010413 addi s0,sp,48 +8000059c: fca42e23 sw a0,-36(s0) +800005a0: fcb42c23 sw a1,-40(s0) +800005a4: fcc42a23 sw a2,-44(s0) +800005a8: 710007b7 lui a5,0x71000 +800005ac: fef42623 sw a5,-20(s0) +800005b0: 720007b7 lui a5,0x72000 +800005b4: fef42423 sw a5,-24(s0) +800005b8: 00700793 li a5,7 +800005bc: fef42223 sw a5,-28(s0) +800005c0: fe440713 addi a4,s0,-28 +800005c4: fec40793 addi a5,s0,-20 +800005c8: 00400613 li a2,4 +800005cc: 00070593 mv a1,a4 +800005d0: 00078513 mv a0,a5 +800005d4: aadff0ef jal ra,80000080 +800005d8: fdc40713 addi a4,s0,-36 +800005dc: fec40793 addi a5,s0,-20 +800005e0: 00400613 li a2,4 +800005e4: 00070593 mv a1,a4 +800005e8: 00078513 mv a0,a5 +800005ec: a95ff0ef jal ra,80000080 +800005f0: fd840713 addi a4,s0,-40 +800005f4: fec40793 addi a5,s0,-20 +800005f8: 00400613 li a2,4 +800005fc: 00070593 mv a1,a4 +80000600: 00078513 mv a0,a5 +80000604: a7dff0ef jal ra,80000080 +80000608: fd440713 addi a4,s0,-44 +8000060c: fec40793 addi a5,s0,-20 +80000610: 00400613 li a2,4 +80000614: 00070593 mv a1,a4 +80000618: 00078513 mv a0,a5 +8000061c: a65ff0ef jal ra,80000080 +80000620: 3541a783 lw a5,852(gp) # 80016b5c +80000624: 000780e7 jalr a5 # 72000000 <_start-0xe000000> +80000628: fe040713 addi a4,s0,-32 +8000062c: fe840793 addi a5,s0,-24 80000630: 00070593 mv a1,a4 80000634: 00078513 mv a0,a5 -80000638: a7dff0ef jal ra,800000b4 -8000063c: fdc40713 addi a4,s0,-36 -80000640: fec40793 addi a5,s0,-20 -80000644: 00400613 li a2,4 -80000648: 00070593 mv a1,a4 -8000064c: 00078513 mv a0,a5 -80000650: a65ff0ef jal ra,800000b4 -80000654: fd840713 addi a4,s0,-40 -80000658: fec40793 addi a5,s0,-20 -8000065c: 00400613 li a2,4 -80000660: 00070593 mv a1,a4 -80000664: 00078513 mv a0,a5 -80000668: a4dff0ef jal ra,800000b4 -8000066c: fd440713 addi a4,s0,-44 -80000670: fec40793 addi a5,s0,-20 -80000674: 00400613 li a2,4 -80000678: 00070593 mv a1,a4 -8000067c: 00078513 mv a0,a5 -80000680: a35ff0ef jal ra,800000b4 -80000684: 3541a783 lw a5,852(gp) # 80016b5c -80000688: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -8000068c: fe040713 addi a4,s0,-32 -80000690: fe840793 addi a5,s0,-24 -80000694: 00070593 mv a1,a4 +80000638: b51ff0ef jal ra,80000188 +8000063c: fe042783 lw a5,-32(s0) +80000640: 00078513 mv a0,a5 +80000644: 02c12083 lw ra,44(sp) +80000648: 02812403 lw s0,40(sp) +8000064c: 03010113 addi sp,sp,48 +80000650: 00008067 ret + +80000654 <_kill>: +80000654: ff010113 addi sp,sp,-16 +80000658: 00112623 sw ra,12(sp) +8000065c: 00812423 sw s0,8(sp) +80000660: 01010413 addi s0,sp,16 +80000664: 00000513 li a0,0 +80000668: 0d4000ef jal ra,8000073c +8000066c: 00000013 nop +80000670: 00c12083 lw ra,12(sp) +80000674: 00812403 lw s0,8(sp) +80000678: 01010113 addi sp,sp,16 +8000067c: 00008067 ret + +80000680 <_getpid>: +80000680: ff010113 addi sp,sp,-16 +80000684: 00112623 sw ra,12(sp) +80000688: 00812423 sw s0,8(sp) +8000068c: 01010413 addi s0,sp,16 +80000690: 0dc000ef jal ra,8000076c +80000694: 00050793 mv a5,a0 80000698: 00078513 mv a0,a5 -8000069c: b21ff0ef jal ra,800001bc -800006a0: fe042783 lw a5,-32(s0) -800006a4: 00078513 mv a0,a5 -800006a8: 02c12083 lw ra,44(sp) -800006ac: 02812403 lw s0,40(sp) -800006b0: 03010113 addi sp,sp,48 -800006b4: 00008067 ret +8000069c: 00c12083 lw ra,12(sp) +800006a0: 00812403 lw s0,8(sp) +800006a4: 01010113 addi sp,sp,16 +800006a8: 00008067 ret -800006b8 <_kill>: -800006b8: ff010113 addi sp,sp,-16 -800006bc: 00112623 sw ra,12(sp) -800006c0: 00812423 sw s0,8(sp) -800006c4: 01010413 addi s0,sp,16 -800006c8: 800157b7 lui a5,0x80015 -800006cc: 9a478513 addi a0,a5,-1628 # 800149a4 <__BSS_END__+0xffffdd74> -800006d0: 158000ef jal ra,80000828 -800006d4: 00000013 nop -800006d8: 00c12083 lw ra,12(sp) -800006dc: 00812403 lw s0,8(sp) -800006e0: 01010113 addi sp,sp,16 -800006e4: 00008067 ret +800006ac <_unlink>: +800006ac: ff010113 addi sp,sp,-16 +800006b0: 00112623 sw ra,12(sp) +800006b4: 00812423 sw s0,8(sp) +800006b8: 01010413 addi s0,sp,16 +800006bc: 800157b7 lui a5,0x80015 +800006c0: a5878513 addi a0,a5,-1448 # 80014a58 <__BSS_END__+0xffffde1c> +800006c4: 100000ef jal ra,800007c4 +800006c8: 00000013 nop +800006cc: 00c12083 lw ra,12(sp) +800006d0: 00812403 lw s0,8(sp) +800006d4: 01010113 addi sp,sp,16 +800006d8: 00008067 ret -800006e8 <_getpid>: -800006e8: ff010113 addi sp,sp,-16 -800006ec: 00112623 sw ra,12(sp) -800006f0: 00812423 sw s0,8(sp) -800006f4: 01010413 addi s0,sp,16 -800006f8: 0e8000ef jal ra,800007e0 -800006fc: 00050793 mv a5,a0 -80000700: 00078513 mv a0,a5 -80000704: 00c12083 lw ra,12(sp) -80000708: 00812403 lw s0,8(sp) -8000070c: 01010113 addi sp,sp,16 -80000710: 00008067 ret +800006dc <_gettimeofday>: +800006dc: ff010113 addi sp,sp,-16 +800006e0: 00812623 sw s0,12(sp) +800006e4: 01010413 addi s0,sp,16 +800006e8: 37c1a783 lw a5,892(gp) # 80016b84 +800006ec: 00178693 addi a3,a5,1 +800006f0: 36d1ae23 sw a3,892(gp) # 80016b84 +800006f4: 00078513 mv a0,a5 +800006f8: 00c12403 lw s0,12(sp) +800006fc: 01010113 addi sp,sp,16 +80000700: 00008067 ret -80000714 <_unlink>: -80000714: ff010113 addi sp,sp,-16 -80000718: 00112623 sw ra,12(sp) -8000071c: 00812423 sw s0,8(sp) -80000720: 01010413 addi s0,sp,16 -80000724: 800157b7 lui a5,0x80015 -80000728: 9c878513 addi a0,a5,-1592 # 800149c8 <__BSS_END__+0xffffdd98> -8000072c: 0fc000ef jal ra,80000828 -80000730: 00000013 nop -80000734: 00c12083 lw ra,12(sp) -80000738: 00812403 lw s0,8(sp) -8000073c: 01010113 addi sp,sp,16 +80000704 <_link>: +80000704: ff010113 addi sp,sp,-16 +80000708: 00112623 sw ra,12(sp) +8000070c: 00812423 sw s0,8(sp) +80000710: 01010413 addi s0,sp,16 +80000714: 800157b7 lui a5,0x80015 +80000718: a7c78513 addi a0,a5,-1412 # 80014a7c <__BSS_END__+0xffffde40> +8000071c: 0a8000ef jal ra,800007c4 +80000720: 00000013 nop +80000724: 00c12083 lw ra,12(sp) +80000728: 00812403 lw s0,8(sp) +8000072c: 01010113 addi sp,sp,16 +80000730: 00008067 ret + +80000734 : +80000734: 00b5106b 0xb5106b +80000738: 00008067 ret + +8000073c : +8000073c: 0005006b 0x5006b 80000740: 00008067 ret -80000744 <_gettimeofday>: -80000744: ff010113 addi sp,sp,-16 -80000748: 00112623 sw ra,12(sp) -8000074c: 00812423 sw s0,8(sp) -80000750: 01010413 addi s0,sp,16 -80000754: 800157b7 lui a5,0x80015 -80000758: 9ec78513 addi a0,a5,-1556 # 800149ec <__BSS_END__+0xffffddbc> -8000075c: 0cc000ef jal ra,80000828 -80000760: 37c1a783 lw a5,892(gp) # 80016b84 -80000764: 00178693 addi a3,a5,1 -80000768: 36d1ae23 sw a3,892(gp) # 80016b84 -8000076c: 00078513 mv a0,a5 -80000770: 00c12083 lw ra,12(sp) -80000774: 00812403 lw s0,8(sp) -80000778: 01010113 addi sp,sp,16 -8000077c: 00008067 ret +80000744 : +80000744: 00b5406b 0xb5406b +80000748: 00008067 ret -80000780 <_link>: -80000780: ff010113 addi sp,sp,-16 -80000784: 00112623 sw ra,12(sp) -80000788: 00812423 sw s0,8(sp) -8000078c: 01010413 addi s0,sp,16 -80000790: 800157b7 lui a5,0x80015 -80000794: a1878513 addi a0,a5,-1512 # 80014a18 <__BSS_END__+0xffffdde8> -80000798: 090000ef jal ra,80000828 -8000079c: 00000013 nop -800007a0: 00c12083 lw ra,12(sp) -800007a4: 00812403 lw s0,8(sp) -800007a8: 01010113 addi sp,sp,16 -800007ac: 00008067 ret +8000074c : +8000074c: 0005206b 0x5206b +80000750: 00008067 ret -800007b0 : -800007b0: 00b5106b 0xb5106b -800007b4: 00008067 ret +80000754 : +80000754: 0000306b 0x306b +80000758: 00008067 ret -800007b8 : -800007b8: 0005006b 0x5006b -800007bc: 00008067 ret +8000075c : +8000075c: 02102573 csrr a0,0x21 +80000760: 00008067 ret -800007c0 : -800007c0: 00b5406b 0xb5406b -800007c4: 00008067 ret +80000764 : +80000764: 02202573 csrr a0,0x22 +80000768: 00008067 ret -800007c8 : -800007c8: 0005206b 0x5206b -800007cc: 00008067 ret +8000076c : +8000076c: 02002573 csrr a0,0x20 +80000770: 00008067 ret -800007d0 : -800007d0: 0000306b 0x306b -800007d4: 00008067 ret +80000774 : +80000774: 02602573 csrr a0,0x26 +80000778: 00008067 ret -800007d8 : -800007d8: 02102573 csrr a0,0x21 -800007dc: 00008067 ret +8000077c : +8000077c: 02502573 csrr a0,0x25 +80000780: 00008067 ret -800007e0 : -800007e0: 02002573 csrr a0,0x20 -800007e4: 00008067 ret +80000784 : +80000784: 00400513 li a0,4 +80000788: 0005006b 0x5006b +8000078c: 021026f3 csrr a3,0x21 +80000790: 00f69693 slli a3,a3,0xf +80000794: 02002673 csrr a2,0x20 +80000798: 00a61593 slli a1,a2,0xa +8000079c: 00261613 slli a2,a2,0x2 +800007a0: 6ffff137 lui sp,0x6ffff +800007a4: 40b10133 sub sp,sp,a1 +800007a8: 40d10133 sub sp,sp,a3 +800007ac: 00c10133 add sp,sp,a2 +800007b0: 021026f3 csrr a3,0x21 +800007b4: 00068663 beqz a3,800007c0 +800007b8: 00000513 li a0,0 +800007bc: 0005006b 0x5006b -800007e8 : -800007e8: 00400513 li a0,4 -800007ec: 0005006b 0x5006b -800007f0: 021026f3 csrr a3,0x21 -800007f4: 00f69693 slli a3,a3,0xf -800007f8: 02002673 csrr a2,0x20 -800007fc: 00a61593 slli a1,a2,0xa -80000800: 00261613 slli a2,a2,0x2 -80000804: 6ffff137 lui sp,0x6ffff -80000808: 40b10133 sub sp,sp,a1 -8000080c: 40d10133 sub sp,sp,a3 -80000810: 00c10133 add sp,sp,a2 -80000814: 021026f3 csrr a3,0x21 -80000818: 00068663 beqz a3,80000824 -8000081c: 00000513 li a0,0 -80000820: 0005006b 0x5006b +800007c0 : +800007c0: 00008067 ret -80000824 : -80000824: 00008067 ret +800007c4 : +800007c4: ff410113 addi sp,sp,-12 # 6fffeff4 <_start-0x1000100c> +800007c8: 00112023 sw ra,0(sp) +800007cc: 00b12223 sw a1,4(sp) -80000828 : -80000828: ff410113 addi sp,sp,-12 # 6fffeff4 <_start-0x1000100c> -8000082c: 00112023 sw ra,0(sp) -80000830: 00b12223 sw a1,4(sp) +800007d0 : +800007d0: 00054583 lbu a1,0(a0) +800007d4: 00058863 beqz a1,800007e4 +800007d8: 01c000ef jal ra,800007f4 +800007dc: 00150513 addi a0,a0,1 +800007e0: ff1ff06f j 800007d0 -80000834 : -80000834: 00054583 lbu a1,0(a0) -80000838: 00058863 beqz a1,80000848 -8000083c: 01c000ef jal ra,80000858 -80000840: 00150513 addi a0,a0,1 -80000844: ff1ff06f j 80000834 +800007e4 : +800007e4: 00012083 lw ra,0(sp) +800007e8: 00412583 lw a1,4(sp) +800007ec: 00c10113 addi sp,sp,12 +800007f0: 00008067 ret -80000848 : -80000848: 00012083 lw ra,0(sp) -8000084c: 00412583 lw a1,4(sp) -80000850: 00c10113 addi sp,sp,12 -80000854: 00008067 ret +800007f4 : +800007f4: 000102b7 lui t0,0x10 +800007f8: 00b2a023 sw a1,0(t0) # 10000 <_start-0x7fff0000> +800007fc: 00008067 ret -80000858 : -80000858: 000102b7 lui t0,0x10 -8000085c: 00b2a023 sw a1,0(t0) # 10000 <_start-0x7fff0000> -80000860: 00008067 ret +80000800 : +80000800: fd010113 addi sp,sp,-48 +80000804: 02112623 sw ra,44(sp) +80000808: 02812423 sw s0,40(sp) +8000080c: 03010413 addi s0,sp,48 +80000810: fca42e23 sw a0,-36(s0) +80000814: fdc42703 lw a4,-36(s0) +80000818: 00f00793 li a5,15 +8000081c: 02e7e463 bltu a5,a4,80000844 +80000820: 800167b7 lui a5,0x80016 +80000824: 04c78713 addi a4,a5,76 # 8001604c <__BSS_END__+0xfffff410> +80000828: fdc42783 lw a5,-36(s0) +8000082c: 00279793 slli a5,a5,0x2 +80000830: 00f707b3 add a5,a4,a5 +80000834: 0007a783 lw a5,0(a5) +80000838: 00078513 mv a0,a5 +8000083c: f89ff0ef jal ra,800007c4 +80000840: 0740006f j 800008b4 +80000844: 02000793 li a5,32 +80000848: fef42623 sw a5,-20(s0) +8000084c: fe0405a3 sb zero,-21(s0) +80000850: fec42783 lw a5,-20(s0) +80000854: ffc78793 addi a5,a5,-4 +80000858: fdc42703 lw a4,-36(s0) +8000085c: 00f757b3 srl a5,a4,a5 +80000860: 00f7f793 andi a5,a5,15 +80000864: fef42223 sw a5,-28(s0) +80000868: fe442783 lw a5,-28(s0) +8000086c: 00078663 beqz a5,80000878 +80000870: 00100793 li a5,1 +80000874: fef405a3 sb a5,-21(s0) +80000878: feb44783 lbu a5,-21(s0) +8000087c: 02078263 beqz a5,800008a0 +80000880: 800167b7 lui a5,0x80016 +80000884: 04c78713 addi a4,a5,76 # 8001604c <__BSS_END__+0xfffff410> +80000888: fe442783 lw a5,-28(s0) +8000088c: 00279793 slli a5,a5,0x2 +80000890: 00f707b3 add a5,a4,a5 +80000894: 0007a783 lw a5,0(a5) +80000898: 00078513 mv a0,a5 +8000089c: f29ff0ef jal ra,800007c4 +800008a0: fec42783 lw a5,-20(s0) +800008a4: ffc78793 addi a5,a5,-4 +800008a8: fef42623 sw a5,-20(s0) +800008ac: fec42783 lw a5,-20(s0) +800008b0: faf040e3 bgtz a5,80000850 +800008b4: 02c12083 lw ra,44(sp) +800008b8: 02812403 lw s0,40(sp) +800008bc: 03010113 addi sp,sp,48 +800008c0: 00008067 ret -80000864 : -80000864: fd010113 addi sp,sp,-48 -80000868: 02112623 sw ra,44(sp) -8000086c: 02812423 sw s0,40(sp) -80000870: 03010413 addi s0,sp,48 -80000874: fca42e23 sw a0,-36(s0) -80000878: fdc42703 lw a4,-36(s0) -8000087c: 00f00793 li a5,15 -80000880: 02e7e463 bltu a5,a4,800008a8 -80000884: 800167b7 lui a5,0x80016 -80000888: 04c78713 addi a4,a5,76 # 8001604c <__BSS_END__+0xfffff41c> -8000088c: fdc42783 lw a5,-36(s0) -80000890: 00279793 slli a5,a5,0x2 -80000894: 00f707b3 add a5,a4,a5 -80000898: 0007a783 lw a5,0(a5) -8000089c: 00078513 mv a0,a5 -800008a0: f89ff0ef jal ra,80000828 -800008a4: 0740006f j 80000918 -800008a8: 02000793 li a5,32 -800008ac: fef42623 sw a5,-20(s0) -800008b0: fe0405a3 sb zero,-21(s0) -800008b4: fec42783 lw a5,-20(s0) -800008b8: ffc78793 addi a5,a5,-4 -800008bc: fdc42703 lw a4,-36(s0) -800008c0: 00f757b3 srl a5,a4,a5 -800008c4: 00f7f793 andi a5,a5,15 -800008c8: fef42223 sw a5,-28(s0) -800008cc: fe442783 lw a5,-28(s0) -800008d0: 00078663 beqz a5,800008dc -800008d4: 00100793 li a5,1 -800008d8: fef405a3 sb a5,-21(s0) -800008dc: feb44783 lbu a5,-21(s0) -800008e0: 02078263 beqz a5,80000904 -800008e4: 800167b7 lui a5,0x80016 -800008e8: 04c78713 addi a4,a5,76 # 8001604c <__BSS_END__+0xfffff41c> -800008ec: fe442783 lw a5,-28(s0) -800008f0: 00279793 slli a5,a5,0x2 -800008f4: 00f707b3 add a5,a4,a5 -800008f8: 0007a783 lw a5,0(a5) -800008fc: 00078513 mv a0,a5 -80000900: f29ff0ef jal ra,80000828 -80000904: fec42783 lw a5,-20(s0) -80000908: ffc78793 addi a5,a5,-4 -8000090c: fef42623 sw a5,-20(s0) -80000910: fec42783 lw a5,-20(s0) -80000914: faf040e3 bgtz a5,800008b4 -80000918: 02c12083 lw ra,44(sp) -8000091c: 02812403 lw s0,40(sp) -80000920: 03010113 addi sp,sp,48 -80000924: 00008067 ret +800008c4 : +800008c4: fe010113 addi sp,sp,-32 +800008c8: 00112e23 sw ra,28(sp) +800008cc: 00812c23 sw s0,24(sp) +800008d0: 02010413 addi s0,sp,32 +800008d4: fea42623 sw a0,-20(s0) +800008d8: feb42423 sw a1,-24(s0) +800008dc: fec42503 lw a0,-20(s0) +800008e0: ee5ff0ef jal ra,800007c4 +800008e4: fe842503 lw a0,-24(s0) +800008e8: f19ff0ef jal ra,80000800 +800008ec: 800157b7 lui a5,0x80015 +800008f0: ae078513 addi a0,a5,-1312 # 80014ae0 <__BSS_END__+0xffffdea4> +800008f4: ed1ff0ef jal ra,800007c4 +800008f8: 00000013 nop +800008fc: 01c12083 lw ra,28(sp) +80000900: 01812403 lw s0,24(sp) +80000904: 02010113 addi sp,sp,32 +80000908: 00008067 ret -80000928 : -80000928: fe010113 addi sp,sp,-32 -8000092c: 00112e23 sw ra,28(sp) -80000930: 00812c23 sw s0,24(sp) -80000934: 02010413 addi s0,sp,32 -80000938: fea42623 sw a0,-20(s0) -8000093c: feb42423 sw a1,-24(s0) -80000940: fec42503 lw a0,-20(s0) -80000944: ee5ff0ef jal ra,80000828 -80000948: fe842503 lw a0,-24(s0) -8000094c: f19ff0ef jal ra,80000864 -80000950: 800157b7 lui a5,0x80015 -80000954: a7c78513 addi a0,a5,-1412 # 80014a7c <__BSS_END__+0xffffde4c> -80000958: ed1ff0ef jal ra,80000828 +8000090c : +8000090c: fe010113 addi sp,sp,-32 +80000910: 00112e23 sw ra,28(sp) +80000914: 00812c23 sw s0,24(sp) +80000918: 02010413 addi s0,sp,32 +8000091c: 40c1a783 lw a5,1036(gp) # 80016c14 +80000920: 00078513 mv a0,a5 +80000924: e19ff0ef jal ra,8000073c +80000928: 3f41a703 lw a4,1012(gp) # 80016bfc +8000092c: 3ec1a783 lw a5,1004(gp) # 80016bf4 +80000930: 00078513 mv a0,a5 +80000934: 000700e7 jalr a4 # 2000 <_start-0x7fffe000> +80000938: e25ff0ef jal ra,8000075c +8000093c: fea42623 sw a0,-20(s0) +80000940: fec42783 lw a5,-20(s0) +80000944: 00078863 beqz a5,80000954 +80000948: 00000513 li a0,0 +8000094c: df1ff0ef jal ra,8000073c +80000950: 00c0006f j 8000095c +80000954: 00100513 li a0,1 +80000958: de5ff0ef jal ra,8000073c 8000095c: 00000013 nop 80000960: 01c12083 lw ra,28(sp) 80000964: 01812403 lw s0,24(sp) 80000968: 02010113 addi sp,sp,32 8000096c: 00008067 ret -80000970 : +80000970 : 80000970: fe010113 addi sp,sp,-32 80000974: 00112e23 sw ra,28(sp) 80000978: 00812c23 sw s0,24(sp) 8000097c: 02010413 addi s0,sp,32 -80000980: 4001a783 lw a5,1024(gp) # 80016c08 -80000984: 00078513 mv a0,a5 -80000988: e31ff0ef jal ra,800007b8 -8000098c: 3f01a703 lw a4,1008(gp) # 80016bf8 -80000990: 3ec1a783 lw a5,1004(gp) # 80016bf4 -80000994: 00078513 mv a0,a5 -80000998: 000700e7 jalr a4 # 2000 <_start-0x7fffe000> -8000099c: e3dff0ef jal ra,800007d8 -800009a0: fea42623 sw a0,-20(s0) -800009a4: fec42783 lw a5,-20(s0) -800009a8: 00078863 beqz a5,800009b8 -800009ac: 00000513 li a0,0 -800009b0: e09ff0ef jal ra,800007b8 -800009b4: 00c0006f j 800009c0 -800009b8: 00100513 li a0,1 -800009bc: dfdff0ef jal ra,800007b8 +80000980: fea42623 sw a0,-20(s0) +80000984: feb42423 sw a1,-24(s0) +80000988: fec42223 sw a2,-28(s0) +8000098c: fed42023 sw a3,-32(s0) +80000990: fe442703 lw a4,-28(s0) +80000994: 3ee1aa23 sw a4,1012(gp) # 80016bfc +80000998: fe042703 lw a4,-32(s0) +8000099c: 3ee1a623 sw a4,1004(gp) # 80016bf4 +800009a0: fe842703 lw a4,-24(s0) +800009a4: 40e1a623 sw a4,1036(gp) # 80016c14 +800009a8: 800017b7 lui a5,0x80001 +800009ac: 90c78793 addi a5,a5,-1780 # 8000090c <__BSS_END__+0xfffe9cd0> +800009b0: 00078593 mv a1,a5 +800009b4: fec42503 lw a0,-20(s0) +800009b8: d7dff0ef jal ra,80000734 +800009bc: f51ff0ef jal ra,8000090c 800009c0: 00000013 nop 800009c4: 01c12083 lw ra,28(sp) 800009c8: 01812403 lw s0,24(sp) 800009cc: 02010113 addi sp,sp,32 800009d0: 00008067 ret -800009d4 : -800009d4: fe010113 addi sp,sp,-32 -800009d8: 00112e23 sw ra,28(sp) -800009dc: 00812c23 sw s0,24(sp) -800009e0: 02010413 addi s0,sp,32 -800009e4: fea42623 sw a0,-20(s0) -800009e8: feb42423 sw a1,-24(s0) -800009ec: fec42223 sw a2,-28(s0) -800009f0: fed42023 sw a3,-32(s0) -800009f4: fe442703 lw a4,-28(s0) -800009f8: 3ee1a823 sw a4,1008(gp) # 80016bf8 -800009fc: fe042703 lw a4,-32(s0) -80000a00: 3ee1a623 sw a4,1004(gp) # 80016bf4 -80000a04: fe842703 lw a4,-24(s0) -80000a08: 40e1a023 sw a4,1024(gp) # 80016c08 -80000a0c: 800017b7 lui a5,0x80001 -80000a10: 97078793 addi a5,a5,-1680 # 80000970 <__BSS_END__+0xfffe9d40> -80000a14: 00078593 mv a1,a5 -80000a18: fec42503 lw a0,-20(s0) -80000a1c: d95ff0ef jal ra,800007b0 -80000a20: f51ff0ef jal ra,80000970 -80000a24: 00000013 nop -80000a28: 01c12083 lw ra,28(sp) -80000a2c: 01812403 lw s0,24(sp) -80000a30: 02010113 addi sp,sp,32 -80000a34: 00008067 ret +800009d4 : +800009d4: fd010113 addi sp,sp,-48 +800009d8: 02112623 sw ra,44(sp) +800009dc: 02812423 sw s0,40(sp) +800009e0: 03010413 addi s0,sp,48 +800009e4: 3fc1a783 lw a5,1020(gp) # 80016c04 +800009e8: 00078513 mv a0,a5 +800009ec: d51ff0ef jal ra,8000073c +800009f0: d7dff0ef jal ra,8000076c +800009f4: 00050793 mv a5,a0 +800009f8: fef42023 sw a5,-32(s0) +800009fc: d61ff0ef jal ra,8000075c +80000a00: 00050793 mv a5,a0 +80000a04: fcf42e23 sw a5,-36(s0) +80000a08: fe042623 sw zero,-20(s0) +80000a0c: 0980006f j 80000aa4 +80000a10: fe042423 sw zero,-24(s0) +80000a14: 0780006f j 80000a8c +80000a18: fe042223 sw zero,-28(s0) +80000a1c: 0580006f j 80000a74 +80000a20: fe842783 lw a5,-24(s0) +80000a24: 00279793 slli a5,a5,0x2 +80000a28: fe042703 lw a4,-32(s0) +80000a2c: 00f707b3 add a5,a4,a5 +80000a30: fcf42c23 sw a5,-40(s0) +80000a34: fe442783 lw a5,-28(s0) +80000a38: 00279793 slli a5,a5,0x2 +80000a3c: fdc42703 lw a4,-36(s0) +80000a40: 00f707b3 add a5,a4,a5 +80000a44: fcf42a23 sw a5,-44(s0) +80000a48: 3e81a803 lw a6,1000(gp) # 80016bf0 +80000a4c: 4041a503 lw a0,1028(gp) # 80016c0c +80000a50: 4081a783 lw a5,1032(gp) # 80016c10 +80000a54: fd842603 lw a2,-40(s0) +80000a58: fd442683 lw a3,-44(s0) +80000a5c: fec42703 lw a4,-20(s0) +80000a60: 00078593 mv a1,a5 +80000a64: 000800e7 jalr a6 +80000a68: fe442783 lw a5,-28(s0) +80000a6c: 00178793 addi a5,a5,1 +80000a70: fef42223 sw a5,-28(s0) +80000a74: fe442703 lw a4,-28(s0) +80000a78: 3f01a783 lw a5,1008(gp) # 80016bf8 +80000a7c: faf762e3 bltu a4,a5,80000a20 +80000a80: fe842783 lw a5,-24(s0) +80000a84: 00178793 addi a5,a5,1 +80000a88: fef42423 sw a5,-24(s0) +80000a8c: fe842703 lw a4,-24(s0) +80000a90: 4001a783 lw a5,1024(gp) # 80016c08 +80000a94: f8f762e3 bltu a4,a5,80000a18 +80000a98: fec42783 lw a5,-20(s0) +80000a9c: 00178793 addi a5,a5,1 +80000aa0: fef42623 sw a5,-20(s0) +80000aa4: fec42703 lw a4,-20(s0) +80000aa8: 3f81a783 lw a5,1016(gp) # 80016c00 +80000aac: f6f762e3 bltu a4,a5,80000a10 +80000ab0: fdc42783 lw a5,-36(s0) +80000ab4: 00078663 beqz a5,80000ac0 +80000ab8: 00000513 li a0,0 +80000abc: c81ff0ef jal ra,8000073c +80000ac0: 00100513 li a0,1 +80000ac4: c79ff0ef jal ra,8000073c +80000ac8: 00000013 nop +80000acc: 02c12083 lw ra,44(sp) +80000ad0: 02812403 lw s0,40(sp) +80000ad4: 03010113 addi sp,sp,48 +80000ad8: 00008067 ret -80000a38 : -80000a38: fe010113 addi sp,sp,-32 -80000a3c: 00112e23 sw ra,28(sp) -80000a40: 00812c23 sw s0,24(sp) -80000a44: 02010413 addi s0,sp,32 -80000a48: 3f41a783 lw a5,1012(gp) # 80016bfc -80000a4c: 00078513 mv a0,a5 -80000a50: d69ff0ef jal ra,800007b8 -80000a54: d8dff0ef jal ra,800007e0 -80000a58: 00050793 mv a5,a0 -80000a5c: fef42623 sw a5,-20(s0) -80000a60: d79ff0ef jal ra,800007d8 -80000a64: 00050793 mv a5,a0 -80000a68: fef42423 sw a5,-24(s0) -80000a6c: 3e81a803 lw a6,1000(gp) # 80016bf0 -80000a70: 3f81a503 lw a0,1016(gp) # 80016c00 -80000a74: 3fc1a783 lw a5,1020(gp) # 80016c04 -80000a78: fec42603 lw a2,-20(s0) -80000a7c: fe842683 lw a3,-24(s0) -80000a80: 00000713 li a4,0 -80000a84: 00078593 mv a1,a5 -80000a88: 000800e7 jalr a6 -80000a8c: fe842783 lw a5,-24(s0) -80000a90: 00078663 beqz a5,80000a9c -80000a94: 00000513 li a0,0 -80000a98: d21ff0ef jal ra,800007b8 -80000a9c: 00100513 li a0,1 -80000aa0: d19ff0ef jal ra,800007b8 -80000aa4: 00000013 nop -80000aa8: 01c12083 lw ra,28(sp) -80000aac: 01812403 lw s0,24(sp) -80000ab0: 02010113 addi sp,sp,32 -80000ab4: 00008067 ret - -80000ab8 : -80000ab8: fe010113 addi sp,sp,-32 -80000abc: 00112e23 sw ra,28(sp) -80000ac0: 00812c23 sw s0,24(sp) -80000ac4: 02010413 addi s0,sp,32 -80000ac8: fea42623 sw a0,-20(s0) -80000acc: feb42423 sw a1,-24(s0) -80000ad0: fec42223 sw a2,-28(s0) -80000ad4: fec42783 lw a5,-20(s0) -80000ad8: 0087a703 lw a4,8(a5) -80000adc: 00100793 li a5,1 -80000ae0: 00e7fa63 bgeu a5,a4,80000af4 -80000ae4: 800157b7 lui a5,0x80015 -80000ae8: a8078513 addi a0,a5,-1408 # 80014a80 <__BSS_END__+0xffffde50> -80000aec: 169000ef jal ra,80001454 -80000af0: 0580006f j 80000b48 -80000af4: fec42783 lw a5,-20(s0) -80000af8: 0007a703 lw a4,0(a5) -80000afc: 3ee1aa23 sw a4,1012(gp) # 80016bfc -80000b00: fe842703 lw a4,-24(s0) -80000b04: 3ee1a423 sw a4,1000(gp) # 80016bf0 -80000b08: fec42703 lw a4,-20(s0) -80000b0c: 3ee1ae23 sw a4,1020(gp) # 80016c04 -80000b10: fe442703 lw a4,-28(s0) -80000b14: 3ee1ac23 sw a4,1016(gp) # 80016c00 -80000b18: fec42783 lw a5,-20(s0) -80000b1c: 0047a703 lw a4,4(a5) -80000b20: 00100793 li a5,1 -80000b24: 02e7f063 bgeu a5,a4,80000b44 -80000b28: fec42783 lw a5,-20(s0) -80000b2c: 0047a703 lw a4,4(a5) -80000b30: 800017b7 lui a5,0x80001 -80000b34: a3878793 addi a5,a5,-1480 # 80000a38 <__BSS_END__+0xfffe9e08> -80000b38: 00078593 mv a1,a5 -80000b3c: 00070513 mv a0,a4 -80000b40: c71ff0ef jal ra,800007b0 -80000b44: ef5ff0ef jal ra,80000a38 -80000b48: 01c12083 lw ra,28(sp) -80000b4c: 01812403 lw s0,24(sp) -80000b50: 02010113 addi sp,sp,32 -80000b54: 00008067 ret - -80000b58 : -80000b58: fe010113 addi sp,sp,-32 -80000b5c: 00112e23 sw ra,28(sp) -80000b60: 00812c23 sw s0,24(sp) -80000b64: 02010413 addi s0,sp,32 -80000b68: 800157b7 lui a5,0x80015 -80000b6c: af478513 addi a0,a5,-1292 # 80014af4 <__BSS_END__+0xffffdec4> -80000b70: cb9ff0ef jal ra,80000828 -80000b74: 00400513 li a0,4 -80000b78: c41ff0ef jal ra,800007b8 -80000b7c: c65ff0ef jal ra,800007e0 -80000b80: fea42623 sw a0,-20(s0) -80000b84: fec42703 lw a4,-20(s0) -80000b88: 8c418693 addi a3,gp,-1852 # 800160cc -80000b8c: fec42783 lw a5,-20(s0) -80000b90: 00279793 slli a5,a5,0x2 -80000b94: 00f687b3 add a5,a3,a5 -80000b98: 00e7a023 sw a4,0(a5) -80000b9c: 00100513 li a0,1 -80000ba0: c19ff0ef jal ra,800007b8 -80000ba4: 8c418793 addi a5,gp,-1852 # 800160cc -80000ba8: 0007a783 lw a5,0(a5) -80000bac: 00078513 mv a0,a5 -80000bb0: cb5ff0ef jal ra,80000864 -80000bb4: 800157b7 lui a5,0x80015 -80000bb8: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000bbc: c6dff0ef jal ra,80000828 -80000bc0: 8c418793 addi a5,gp,-1852 # 800160cc -80000bc4: 0047a783 lw a5,4(a5) -80000bc8: 00078513 mv a0,a5 -80000bcc: c99ff0ef jal ra,80000864 -80000bd0: 800157b7 lui a5,0x80015 -80000bd4: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000bd8: c51ff0ef jal ra,80000828 -80000bdc: 8c418793 addi a5,gp,-1852 # 800160cc -80000be0: 0087a783 lw a5,8(a5) -80000be4: 00078513 mv a0,a5 -80000be8: c7dff0ef jal ra,80000864 -80000bec: 800157b7 lui a5,0x80015 -80000bf0: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000bf4: c35ff0ef jal ra,80000828 -80000bf8: 8c418793 addi a5,gp,-1852 # 800160cc -80000bfc: 00c7a783 lw a5,12(a5) -80000c00: 00078513 mv a0,a5 -80000c04: c61ff0ef jal ra,80000864 -80000c08: 800157b7 lui a5,0x80015 -80000c0c: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000c10: c19ff0ef jal ra,80000828 +80000adc : +80000adc: fc010113 addi sp,sp,-64 +80000ae0: 02112e23 sw ra,60(sp) +80000ae4: 02812c23 sw s0,56(sp) +80000ae8: 04010413 addi s0,sp,64 +80000aec: fca42623 sw a0,-52(s0) +80000af0: fcb42423 sw a1,-56(s0) +80000af4: fcc42223 sw a2,-60(s0) +80000af8: fcc42783 lw a5,-52(s0) +80000afc: 0007a703 lw a4,0(a5) +80000b00: 00400793 li a5,4 +80000b04: 02e7f063 bgeu a5,a4,80000b24 +80000b08: 00400713 li a4,4 +80000b0c: 3ee1ae23 sw a4,1020(gp) # 80016c04 +80000b10: fcc42783 lw a5,-52(s0) +80000b14: 0007a783 lw a5,0(a5) +80000b18: 0027d713 srli a4,a5,0x2 +80000b1c: 40e1a023 sw a4,1024(gp) # 80016c08 +80000b20: 0180006f j 80000b38 +80000b24: fcc42783 lw a5,-52(s0) +80000b28: 0007a703 lw a4,0(a5) +80000b2c: 3ee1ae23 sw a4,1020(gp) # 80016c04 +80000b30: 00100713 li a4,1 +80000b34: 40e1a023 sw a4,1024(gp) # 80016c08 +80000b38: fcc42783 lw a5,-52(s0) +80000b3c: 0087a703 lw a4,8(a5) +80000b40: 3ee1ac23 sw a4,1016(gp) # 80016c00 +80000b44: fc842703 lw a4,-56(s0) +80000b48: 3ee1a423 sw a4,1000(gp) # 80016bf0 +80000b4c: fcc42703 lw a4,-52(s0) +80000b50: 40e1a423 sw a4,1032(gp) # 80016c10 +80000b54: fc442703 lw a4,-60(s0) +80000b58: 40e1a223 sw a4,1028(gp) # 80016c0c +80000b5c: fcc42783 lw a5,-52(s0) +80000b60: 0047a703 lw a4,4(a5) +80000b64: 00100793 li a5,1 +80000b68: 06e7f063 bgeu a5,a4,80000bc8 +80000b6c: fcc42783 lw a5,-52(s0) +80000b70: 0047a703 lw a4,4(a5) +80000b74: 00400793 li a5,4 +80000b78: 02e7f663 bgeu a5,a4,80000ba4 +80000b7c: fcc42783 lw a5,-52(s0) +80000b80: 0047a783 lw a5,4(a5) +80000b84: 0027d713 srli a4,a5,0x2 +80000b88: 3ee1a823 sw a4,1008(gp) # 80016bf8 +80000b8c: 800017b7 lui a5,0x80001 +80000b90: 9d478793 addi a5,a5,-1580 # 800009d4 <__BSS_END__+0xfffe9d98> +80000b94: 00078593 mv a1,a5 +80000b98: 00400513 li a0,4 +80000b9c: b99ff0ef jal ra,80000734 +80000ba0: 0280006f j 80000bc8 +80000ba4: 00100713 li a4,1 +80000ba8: 3ee1a823 sw a4,1008(gp) # 80016bf8 +80000bac: fcc42783 lw a5,-52(s0) +80000bb0: 0047a703 lw a4,4(a5) +80000bb4: 800017b7 lui a5,0x80001 +80000bb8: 9d478793 addi a5,a5,-1580 # 800009d4 <__BSS_END__+0xfffe9d98> +80000bbc: 00078593 mv a1,a5 +80000bc0: 00070513 mv a0,a4 +80000bc4: b71ff0ef jal ra,80000734 +80000bc8: badff0ef jal ra,80000774 +80000bcc: fea42623 sw a0,-20(s0) +80000bd0: badff0ef jal ra,8000077c +80000bd4: fea42423 sw a0,-24(s0) +80000bd8: dfdff0ef jal ra,800009d4 +80000bdc: b99ff0ef jal ra,80000774 +80000be0: fea42223 sw a0,-28(s0) +80000be4: b99ff0ef jal ra,8000077c +80000be8: fea42023 sw a0,-32(s0) +80000bec: fe442703 lw a4,-28(s0) +80000bf0: fec42783 lw a5,-20(s0) +80000bf4: 40f707b3 sub a5,a4,a5 +80000bf8: fcf42e23 sw a5,-36(s0) +80000bfc: fdc42583 lw a1,-36(s0) +80000c00: 800157b7 lui a5,0x80015 +80000c04: ae478513 addi a0,a5,-1308 # 80014ae4 <__BSS_END__+0xffffdea8> +80000c08: 7c4000ef jal ra,800013cc +80000c0c: 00000513 li a0,0 +80000c10: b2dff0ef jal ra,8000073c 80000c14: 00000013 nop -80000c18: 01c12083 lw ra,28(sp) -80000c1c: 01812403 lw s0,24(sp) -80000c20: 02010113 addi sp,sp,32 +80000c18: 03c12083 lw ra,60(sp) +80000c1c: 03812403 lw s0,56(sp) +80000c20: 04010113 addi sp,sp,64 80000c24: 00008067 ret -80000c28 : +80000c28 : 80000c28: fe010113 addi sp,sp,-32 80000c2c: 00112e23 sw ra,28(sp) 80000c30: 00812c23 sw s0,24(sp) 80000c34: 02010413 addi s0,sp,32 -80000c38: ba9ff0ef jal ra,800007e0 -80000c3c: fea42623 sw a0,-20(s0) -80000c40: fec42783 lw a5,-20(s0) -80000c44: 0027b793 sltiu a5,a5,2 -80000c48: fef405a3 sb a5,-21(s0) -80000c4c: feb44783 lbu a5,-21(s0) -80000c50: 00078513 mv a0,a5 -80000c54: b75ff0ef jal ra,800007c8 -80000c58: feb44783 lbu a5,-21(s0) -80000c5c: 06078063 beqz a5,80000cbc -80000c60: fec42783 lw a5,-20(s0) -80000c64: 0017b793 seqz a5,a5 -80000c68: fef404a3 sb a5,-23(s0) -80000c6c: fe944783 lbu a5,-23(s0) -80000c70: 00078513 mv a0,a5 -80000c74: b55ff0ef jal ra,800007c8 -80000c78: fe944783 lbu a5,-23(s0) -80000c7c: 02078063 beqz a5,80000c9c -80000c80: 41418713 addi a4,gp,1044 # 80016c1c -80000c84: fec42783 lw a5,-20(s0) -80000c88: 00279793 slli a5,a5,0x2 -80000c8c: 00f707b3 add a5,a4,a5 -80000c90: 00a00713 li a4,10 -80000c94: 00e7a023 sw a4,0(a5) -80000c98: 01c0006f j 80000cb4 -80000c9c: 41418713 addi a4,gp,1044 # 80016c1c -80000ca0: fec42783 lw a5,-20(s0) -80000ca4: 00279793 slli a5,a5,0x2 -80000ca8: 00f707b3 add a5,a4,a5 -80000cac: 00b00713 li a4,11 -80000cb0: 00e7a023 sw a4,0(a5) -80000cb4: b1dff0ef jal ra,800007d0 -80000cb8: 05c0006f j 80000d14 -80000cbc: fec42783 lw a5,-20(s0) -80000cc0: 0037b793 sltiu a5,a5,3 -80000cc4: fef40523 sb a5,-22(s0) -80000cc8: fea44783 lbu a5,-22(s0) -80000ccc: 00078513 mv a0,a5 -80000cd0: af9ff0ef jal ra,800007c8 -80000cd4: fea44783 lbu a5,-22(s0) -80000cd8: 02078063 beqz a5,80000cf8 -80000cdc: 41418713 addi a4,gp,1044 # 80016c1c -80000ce0: fec42783 lw a5,-20(s0) -80000ce4: 00279793 slli a5,a5,0x2 -80000ce8: 00f707b3 add a5,a4,a5 -80000cec: 00c00713 li a4,12 -80000cf0: 00e7a023 sw a4,0(a5) -80000cf4: 01c0006f j 80000d10 -80000cf8: 41418713 addi a4,gp,1044 # 80016c1c -80000cfc: fec42783 lw a5,-20(s0) -80000d00: 00279793 slli a5,a5,0x2 -80000d04: 00f707b3 add a5,a4,a5 -80000d08: 00d00713 li a4,13 -80000d0c: 00e7a023 sw a4,0(a5) -80000d10: ac1ff0ef jal ra,800007d0 -80000d14: abdff0ef jal ra,800007d0 -80000d18: 41418793 addi a5,gp,1044 # 80016c1c -80000d1c: 0007a783 lw a5,0(a5) +80000c38: 800157b7 lui a5,0x80015 +80000c3c: b2878513 addi a0,a5,-1240 # 80014b28 <__BSS_END__+0xffffdeec> +80000c40: b85ff0ef jal ra,800007c4 +80000c44: 00400513 li a0,4 +80000c48: af5ff0ef jal ra,8000073c +80000c4c: b21ff0ef jal ra,8000076c +80000c50: fea42623 sw a0,-20(s0) +80000c54: fec42703 lw a4,-20(s0) +80000c58: 8c418693 addi a3,gp,-1852 # 800160cc +80000c5c: fec42783 lw a5,-20(s0) +80000c60: 00279793 slli a5,a5,0x2 +80000c64: 00f687b3 add a5,a3,a5 +80000c68: 00e7a023 sw a4,0(a5) +80000c6c: 00100513 li a0,1 +80000c70: acdff0ef jal ra,8000073c +80000c74: 8c418793 addi a5,gp,-1852 # 800160cc +80000c78: 0007a783 lw a5,0(a5) +80000c7c: 00078513 mv a0,a5 +80000c80: b81ff0ef jal ra,80000800 +80000c84: 800157b7 lui a5,0x80015 +80000c88: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000c8c: b39ff0ef jal ra,800007c4 +80000c90: 8c418793 addi a5,gp,-1852 # 800160cc +80000c94: 0047a783 lw a5,4(a5) +80000c98: 00078513 mv a0,a5 +80000c9c: b65ff0ef jal ra,80000800 +80000ca0: 800157b7 lui a5,0x80015 +80000ca4: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000ca8: b1dff0ef jal ra,800007c4 +80000cac: 8c418793 addi a5,gp,-1852 # 800160cc +80000cb0: 0087a783 lw a5,8(a5) +80000cb4: 00078513 mv a0,a5 +80000cb8: b49ff0ef jal ra,80000800 +80000cbc: 800157b7 lui a5,0x80015 +80000cc0: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000cc4: b01ff0ef jal ra,800007c4 +80000cc8: 8c418793 addi a5,gp,-1852 # 800160cc +80000ccc: 00c7a783 lw a5,12(a5) +80000cd0: 00078513 mv a0,a5 +80000cd4: b2dff0ef jal ra,80000800 +80000cd8: 800157b7 lui a5,0x80015 +80000cdc: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000ce0: ae5ff0ef jal ra,800007c4 +80000ce4: 00000013 nop +80000ce8: 01c12083 lw ra,28(sp) +80000cec: 01812403 lw s0,24(sp) +80000cf0: 02010113 addi sp,sp,32 +80000cf4: 00008067 ret + +80000cf8 : +80000cf8: fe010113 addi sp,sp,-32 +80000cfc: 00112e23 sw ra,28(sp) +80000d00: 00812c23 sw s0,24(sp) +80000d04: 02010413 addi s0,sp,32 +80000d08: a65ff0ef jal ra,8000076c +80000d0c: fea42623 sw a0,-20(s0) +80000d10: fec42783 lw a5,-20(s0) +80000d14: 0027b793 sltiu a5,a5,2 +80000d18: fef405a3 sb a5,-21(s0) +80000d1c: feb44783 lbu a5,-21(s0) 80000d20: 00078513 mv a0,a5 -80000d24: b41ff0ef jal ra,80000864 -80000d28: 800157b7 lui a5,0x80015 -80000d2c: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000d30: af9ff0ef jal ra,80000828 -80000d34: 41418793 addi a5,gp,1044 # 80016c1c -80000d38: 0047a783 lw a5,4(a5) -80000d3c: 00078513 mv a0,a5 -80000d40: b25ff0ef jal ra,80000864 -80000d44: 800157b7 lui a5,0x80015 -80000d48: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000d4c: addff0ef jal ra,80000828 -80000d50: 41418793 addi a5,gp,1044 # 80016c1c -80000d54: 0087a783 lw a5,8(a5) -80000d58: 00078513 mv a0,a5 -80000d5c: b09ff0ef jal ra,80000864 -80000d60: 800157b7 lui a5,0x80015 -80000d64: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000d68: ac1ff0ef jal ra,80000828 -80000d6c: 41418793 addi a5,gp,1044 # 80016c1c -80000d70: 00c7a783 lw a5,12(a5) -80000d74: 00078513 mv a0,a5 -80000d78: aedff0ef jal ra,80000864 -80000d7c: 800157b7 lui a5,0x80015 -80000d80: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000d84: aa5ff0ef jal ra,80000828 -80000d88: 00000013 nop -80000d8c: 01c12083 lw ra,28(sp) -80000d90: 01812403 lw s0,24(sp) -80000d94: 02010113 addi sp,sp,32 -80000d98: 00008067 ret - -80000d9c : -80000d9c: fe010113 addi sp,sp,-32 -80000da0: 00112e23 sw ra,28(sp) -80000da4: 00812c23 sw s0,24(sp) -80000da8: 02010413 addi s0,sp,32 -80000dac: a2dff0ef jal ra,800007d8 -80000db0: fea42623 sw a0,-20(s0) -80000db4: 40418713 addi a4,gp,1028 # 80016c0c -80000db8: fec42783 lw a5,-20(s0) -80000dbc: 00279793 slli a5,a5,0x2 -80000dc0: 00f707b3 add a5,a4,a5 -80000dc4: fec42703 lw a4,-20(s0) -80000dc8: 00e7a023 sw a4,0(a5) +80000d24: a29ff0ef jal ra,8000074c +80000d28: feb44783 lbu a5,-21(s0) +80000d2c: 06078063 beqz a5,80000d8c +80000d30: fec42783 lw a5,-20(s0) +80000d34: 0017b793 seqz a5,a5 +80000d38: fef404a3 sb a5,-23(s0) +80000d3c: fe944783 lbu a5,-23(s0) +80000d40: 00078513 mv a0,a5 +80000d44: a09ff0ef jal ra,8000074c +80000d48: fe944783 lbu a5,-23(s0) +80000d4c: 02078063 beqz a5,80000d6c +80000d50: 42018713 addi a4,gp,1056 # 80016c28 +80000d54: fec42783 lw a5,-20(s0) +80000d58: 00279793 slli a5,a5,0x2 +80000d5c: 00f707b3 add a5,a4,a5 +80000d60: 00a00713 li a4,10 +80000d64: 00e7a023 sw a4,0(a5) +80000d68: 01c0006f j 80000d84 +80000d6c: 42018713 addi a4,gp,1056 # 80016c28 +80000d70: fec42783 lw a5,-20(s0) +80000d74: 00279793 slli a5,a5,0x2 +80000d78: 00f707b3 add a5,a4,a5 +80000d7c: 00b00713 li a4,11 +80000d80: 00e7a023 sw a4,0(a5) +80000d84: 9d1ff0ef jal ra,80000754 +80000d88: 05c0006f j 80000de4 +80000d8c: fec42783 lw a5,-20(s0) +80000d90: 0037b793 sltiu a5,a5,3 +80000d94: fef40523 sb a5,-22(s0) +80000d98: fea44783 lbu a5,-22(s0) +80000d9c: 00078513 mv a0,a5 +80000da0: 9adff0ef jal ra,8000074c +80000da4: fea44783 lbu a5,-22(s0) +80000da8: 02078063 beqz a5,80000dc8 +80000dac: 42018713 addi a4,gp,1056 # 80016c28 +80000db0: fec42783 lw a5,-20(s0) +80000db4: 00279793 slli a5,a5,0x2 +80000db8: 00f707b3 add a5,a4,a5 +80000dbc: 00c00713 li a4,12 +80000dc0: 00e7a023 sw a4,0(a5) +80000dc4: 01c0006f j 80000de0 +80000dc8: 42018713 addi a4,gp,1056 # 80016c28 80000dcc: fec42783 lw a5,-20(s0) -80000dd0: 00078663 beqz a5,80000ddc -80000dd4: 00000513 li a0,0 -80000dd8: 9e1ff0ef jal ra,800007b8 -80000ddc: 00000013 nop -80000de0: 01c12083 lw ra,28(sp) -80000de4: 01812403 lw s0,24(sp) -80000de8: 02010113 addi sp,sp,32 -80000dec: 00008067 ret +80000dd0: 00279793 slli a5,a5,0x2 +80000dd4: 00f707b3 add a5,a4,a5 +80000dd8: 00d00713 li a4,13 +80000ddc: 00e7a023 sw a4,0(a5) +80000de0: 975ff0ef jal ra,80000754 +80000de4: 971ff0ef jal ra,80000754 +80000de8: 42018793 addi a5,gp,1056 # 80016c28 +80000dec: 0007a783 lw a5,0(a5) +80000df0: 00078513 mv a0,a5 +80000df4: a0dff0ef jal ra,80000800 +80000df8: 800157b7 lui a5,0x80015 +80000dfc: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000e00: 9c5ff0ef jal ra,800007c4 +80000e04: 42018793 addi a5,gp,1056 # 80016c28 +80000e08: 0047a783 lw a5,4(a5) +80000e0c: 00078513 mv a0,a5 +80000e10: 9f1ff0ef jal ra,80000800 +80000e14: 800157b7 lui a5,0x80015 +80000e18: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000e1c: 9a9ff0ef jal ra,800007c4 +80000e20: 42018793 addi a5,gp,1056 # 80016c28 +80000e24: 0087a783 lw a5,8(a5) +80000e28: 00078513 mv a0,a5 +80000e2c: 9d5ff0ef jal ra,80000800 +80000e30: 800157b7 lui a5,0x80015 +80000e34: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000e38: 98dff0ef jal ra,800007c4 +80000e3c: 42018793 addi a5,gp,1056 # 80016c28 +80000e40: 00c7a783 lw a5,12(a5) +80000e44: 00078513 mv a0,a5 +80000e48: 9b9ff0ef jal ra,80000800 +80000e4c: 800157b7 lui a5,0x80015 +80000e50: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000e54: 971ff0ef jal ra,800007c4 +80000e58: 00000013 nop +80000e5c: 01c12083 lw ra,28(sp) +80000e60: 01812403 lw s0,24(sp) +80000e64: 02010113 addi sp,sp,32 +80000e68: 00008067 ret -80000df0 : -80000df0: fe010113 addi sp,sp,-32 -80000df4: 00112e23 sw ra,28(sp) -80000df8: 00812c23 sw s0,24(sp) -80000dfc: 02010413 addi s0,sp,32 -80000e00: 800017b7 lui a5,0x80001 -80000e04: d9c78793 addi a5,a5,-612 # 80000d9c <__BSS_END__+0xfffea16c> -80000e08: fef42623 sw a5,-20(s0) -80000e0c: fec42583 lw a1,-20(s0) -80000e10: 00400513 li a0,4 -80000e14: 99dff0ef jal ra,800007b0 -80000e18: f85ff0ef jal ra,80000d9c -80000e1c: 40418793 addi a5,gp,1028 # 80016c0c -80000e20: 0007a783 lw a5,0(a5) -80000e24: 00078513 mv a0,a5 -80000e28: a3dff0ef jal ra,80000864 -80000e2c: 800157b7 lui a5,0x80015 -80000e30: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000e34: 9f5ff0ef jal ra,80000828 -80000e38: 40418793 addi a5,gp,1028 # 80016c0c -80000e3c: 0047a783 lw a5,4(a5) -80000e40: 00078513 mv a0,a5 -80000e44: a21ff0ef jal ra,80000864 -80000e48: 800157b7 lui a5,0x80015 -80000e4c: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000e50: 9d9ff0ef jal ra,80000828 -80000e54: 40418793 addi a5,gp,1028 # 80016c0c -80000e58: 0087a783 lw a5,8(a5) -80000e5c: 00078513 mv a0,a5 -80000e60: a05ff0ef jal ra,80000864 -80000e64: 800157b7 lui a5,0x80015 -80000e68: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000e6c: 9bdff0ef jal ra,80000828 -80000e70: 40418793 addi a5,gp,1028 # 80016c0c -80000e74: 00c7a783 lw a5,12(a5) -80000e78: 00078513 mv a0,a5 -80000e7c: 9e9ff0ef jal ra,80000864 -80000e80: 800157b7 lui a5,0x80015 -80000e84: b0478513 addi a0,a5,-1276 # 80014b04 <__BSS_END__+0xffffded4> -80000e88: 9a1ff0ef jal ra,80000828 -80000e8c: 00000013 nop -80000e90: 01c12083 lw ra,28(sp) -80000e94: 01812403 lw s0,24(sp) -80000e98: 02010113 addi sp,sp,32 -80000e9c: 00008067 ret +80000e6c : +80000e6c: fe010113 addi sp,sp,-32 +80000e70: 00112e23 sw ra,28(sp) +80000e74: 00812c23 sw s0,24(sp) +80000e78: 02010413 addi s0,sp,32 +80000e7c: 8e1ff0ef jal ra,8000075c +80000e80: fea42623 sw a0,-20(s0) +80000e84: 41018713 addi a4,gp,1040 # 80016c18 +80000e88: fec42783 lw a5,-20(s0) +80000e8c: 00279793 slli a5,a5,0x2 +80000e90: 00f707b3 add a5,a4,a5 +80000e94: fec42703 lw a4,-20(s0) +80000e98: 00e7a023 sw a4,0(a5) +80000e9c: 8c1ff0ef jal ra,8000075c +80000ea0: fea42623 sw a0,-20(s0) +80000ea4: fec42783 lw a5,-20(s0) +80000ea8: 00078663 beqz a5,80000eb4 +80000eac: 00000513 li a0,0 +80000eb0: 88dff0ef jal ra,8000073c +80000eb4: 00000013 nop +80000eb8: 01c12083 lw ra,28(sp) +80000ebc: 01812403 lw s0,24(sp) +80000ec0: 02010113 addi sp,sp,32 +80000ec4: 00008067 ret -80000ea0 : -80000ea0: ff010113 addi sp,sp,-16 -80000ea4: 00112623 sw ra,12(sp) -80000ea8: 00812423 sw s0,8(sp) -80000eac: 01010413 addi s0,sp,16 -80000eb0: ca9ff0ef jal ra,80000b58 -80000eb4: 800157b7 lui a5,0x80015 -80000eb8: b0878513 addi a0,a5,-1272 # 80014b08 <__BSS_END__+0xffffded8> -80000ebc: 96dff0ef jal ra,80000828 -80000ec0: 00400513 li a0,4 -80000ec4: 8f5ff0ef jal ra,800007b8 -80000ec8: d61ff0ef jal ra,80000c28 -80000ecc: 00100513 li a0,1 -80000ed0: 8e9ff0ef jal ra,800007b8 -80000ed4: 800157b7 lui a5,0x80015 -80000ed8: b1c78513 addi a0,a5,-1252 # 80014b1c <__BSS_END__+0xffffdeec> -80000edc: 94dff0ef jal ra,80000828 -80000ee0: f11ff0ef jal ra,80000df0 -80000ee4: 00000013 nop -80000ee8: 00c12083 lw ra,12(sp) -80000eec: 00812403 lw s0,8(sp) -80000ef0: 01010113 addi sp,sp,16 -80000ef4: 00008067 ret +80000ec8 : +80000ec8: fe010113 addi sp,sp,-32 +80000ecc: 00112e23 sw ra,28(sp) +80000ed0: 00812c23 sw s0,24(sp) +80000ed4: 02010413 addi s0,sp,32 +80000ed8: 800017b7 lui a5,0x80001 +80000edc: e6c78793 addi a5,a5,-404 # 80000e6c <__BSS_END__+0xfffea230> +80000ee0: fef42623 sw a5,-20(s0) +80000ee4: fec42583 lw a1,-20(s0) +80000ee8: 00400513 li a0,4 +80000eec: 849ff0ef jal ra,80000734 +80000ef0: f7dff0ef jal ra,80000e6c +80000ef4: 41018793 addi a5,gp,1040 # 80016c18 +80000ef8: 0007a783 lw a5,0(a5) +80000efc: 00078513 mv a0,a5 +80000f00: 901ff0ef jal ra,80000800 +80000f04: 800157b7 lui a5,0x80015 +80000f08: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000f0c: 8b9ff0ef jal ra,800007c4 +80000f10: 41018793 addi a5,gp,1040 # 80016c18 +80000f14: 0047a783 lw a5,4(a5) +80000f18: 00078513 mv a0,a5 +80000f1c: 8e5ff0ef jal ra,80000800 +80000f20: 800157b7 lui a5,0x80015 +80000f24: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000f28: 89dff0ef jal ra,800007c4 +80000f2c: 41018793 addi a5,gp,1040 # 80016c18 +80000f30: 0087a783 lw a5,8(a5) +80000f34: 00078513 mv a0,a5 +80000f38: 8c9ff0ef jal ra,80000800 +80000f3c: 800157b7 lui a5,0x80015 +80000f40: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000f44: 881ff0ef jal ra,800007c4 +80000f48: 41018793 addi a5,gp,1040 # 80016c18 +80000f4c: 00c7a783 lw a5,12(a5) +80000f50: 00078513 mv a0,a5 +80000f54: 8adff0ef jal ra,80000800 +80000f58: 800157b7 lui a5,0x80015 +80000f5c: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> +80000f60: 865ff0ef jal ra,800007c4 +80000f64: 00000013 nop +80000f68: 01c12083 lw ra,28(sp) +80000f6c: 01812403 lw s0,24(sp) +80000f70: 02010113 addi sp,sp,32 +80000f74: 00008067 ret -80000ef8 : -80000ef8: fc010113 addi sp,sp,-64 -80000efc: 02112e23 sw ra,60(sp) -80000f00: 02812c23 sw s0,56(sp) -80000f04: 04010413 addi s0,sp,64 -80000f08: fca42623 sw a0,-52(s0) -80000f0c: fcc42783 lw a5,-52(s0) -80000f10: fef42623 sw a5,-20(s0) -80000f14: 8c5ff0ef jal ra,800007d8 -80000f18: fea42423 sw a0,-24(s0) -80000f1c: 8c5ff0ef jal ra,800007e0 -80000f20: fea42223 sw a0,-28(s0) -80000f24: fec42783 lw a5,-20(s0) -80000f28: 0107a783 lw a5,16(a5) -80000f2c: fe842703 lw a4,-24(s0) -80000f30: 00f77e63 bgeu a4,a5,80000f4c -80000f34: fec42783 lw a5,-20(s0) -80000f38: 00c7a783 lw a5,12(a5) -80000f3c: fe442703 lw a4,-28(s0) -80000f40: 00f77663 bgeu a4,a5,80000f4c -80000f44: 00100793 li a5,1 -80000f48: 0080006f j 80000f50 -80000f4c: 00000793 li a5,0 -80000f50: fef401a3 sb a5,-29(s0) -80000f54: fe344783 lbu a5,-29(s0) -80000f58: 0017f793 andi a5,a5,1 -80000f5c: fef401a3 sb a5,-29(s0) -80000f60: fe344783 lbu a5,-29(s0) -80000f64: 00078513 mv a0,a5 -80000f68: 861ff0ef jal ra,800007c8 -80000f6c: fe344783 lbu a5,-29(s0) -80000f70: 06078663 beqz a5,80000fdc -80000f74: fec42783 lw a5,-20(s0) -80000f78: 00c7a703 lw a4,12(a5) -80000f7c: fe842783 lw a5,-24(s0) -80000f80: 02f707b3 mul a5,a4,a5 -80000f84: fe442703 lw a4,-28(s0) -80000f88: 00f707b3 add a5,a4,a5 -80000f8c: fcf42e23 sw a5,-36(s0) -80000f90: fec42783 lw a5,-20(s0) -80000f94: 0007a703 lw a4,0(a5) -80000f98: fdc42783 lw a5,-36(s0) -80000f9c: 00279793 slli a5,a5,0x2 -80000fa0: 00f707b3 add a5,a4,a5 -80000fa4: 0007a683 lw a3,0(a5) -80000fa8: fec42783 lw a5,-20(s0) -80000fac: 0047a703 lw a4,4(a5) -80000fb0: fdc42783 lw a5,-36(s0) -80000fb4: 00279793 slli a5,a5,0x2 -80000fb8: 00f707b3 add a5,a4,a5 -80000fbc: 0007a703 lw a4,0(a5) -80000fc0: fec42783 lw a5,-20(s0) -80000fc4: 0087a603 lw a2,8(a5) -80000fc8: fdc42783 lw a5,-36(s0) -80000fcc: 00279793 slli a5,a5,0x2 -80000fd0: 00f607b3 add a5,a2,a5 -80000fd4: 00e68733 add a4,a3,a4 -80000fd8: 00e7a023 sw a4,0(a5) -80000fdc: ff4ff0ef jal ra,800007d0 -80000fe0: 00000013 nop -80000fe4: 03c12083 lw ra,60(sp) -80000fe8: 03812403 lw s0,56(sp) -80000fec: 04010113 addi sp,sp,64 -80000ff0: 00008067 ret +80000f78 : +80000f78: ff010113 addi sp,sp,-16 +80000f7c: 00112623 sw ra,12(sp) +80000f80: 00812423 sw s0,8(sp) +80000f84: 01010413 addi s0,sp,16 +80000f88: ca1ff0ef jal ra,80000c28 +80000f8c: 800157b7 lui a5,0x80015 +80000f90: b3c78513 addi a0,a5,-1220 # 80014b3c <__BSS_END__+0xffffdf00> +80000f94: 831ff0ef jal ra,800007c4 +80000f98: 00400513 li a0,4 +80000f9c: fa0ff0ef jal ra,8000073c +80000fa0: d59ff0ef jal ra,80000cf8 +80000fa4: 00100513 li a0,1 +80000fa8: f94ff0ef jal ra,8000073c +80000fac: 800157b7 lui a5,0x80015 +80000fb0: b5078513 addi a0,a5,-1200 # 80014b50 <__BSS_END__+0xffffdf14> +80000fb4: 811ff0ef jal ra,800007c4 +80000fb8: f11ff0ef jal ra,80000ec8 +80000fbc: 00000013 nop +80000fc0: 00c12083 lw ra,12(sp) +80000fc4: 00812403 lw s0,8(sp) +80000fc8: 01010113 addi sp,sp,16 +80000fcc: 00008067 ret -80000ff4
: -80000ff4: fb010113 addi sp,sp,-80 -80000ff8: 04112623 sw ra,76(sp) -80000ffc: 04812423 sw s0,72(sp) -80001000: 05010413 addi s0,sp,80 -80001004: 00100513 li a0,1 -80001008: fb0ff0ef jal ra,800007b8 -8000100c: 800157b7 lui a5,0x80015 -80001010: b6878513 addi a0,a5,-1176 # 80014b68 <__BSS_END__+0xffffdf38> -80001014: 815ff0ef jal ra,80000828 -80001018: b41ff0ef jal ra,80000b58 -8000101c: 800157b7 lui a5,0x80015 -80001020: b7878513 addi a0,a5,-1160 # 80014b78 <__BSS_END__+0xffffdf48> -80001024: 805ff0ef jal ra,80000828 -80001028: 00400513 li a0,4 -8000102c: f8cff0ef jal ra,800007b8 -80001030: bf9ff0ef jal ra,80000c28 -80001034: 00100513 li a0,1 -80001038: f80ff0ef jal ra,800007b8 -8000103c: 800157b7 lui a5,0x80015 -80001040: b8c78513 addi a0,a5,-1140 # 80014b8c <__BSS_END__+0xffffdf5c> -80001044: fe4ff0ef jal ra,80000828 -80001048: da9ff0ef jal ra,80000df0 -8000104c: 800157b7 lui a5,0x80015 -80001050: b9c78513 addi a0,a5,-1124 # 80014b9c <__BSS_END__+0xffffdf6c> -80001054: fd4ff0ef jal ra,80000828 -80001058: ffff07b7 lui a5,0xffff0 -8000105c: fef42623 sw a5,-20(s0) -80001060: fe042423 sw zero,-24(s0) -80001064: fe042223 sw zero,-28(s0) -80001068: 0800006f j 800010e8 -8000106c: fec42783 lw a5,-20(s0) -80001070: fe842703 lw a4,-24(s0) -80001074: 00e7a023 sw a4,0(a5) # ffff0000 <__BSS_END__+0x7ffd93d0> -80001078: fec42783 lw a5,-20(s0) -8000107c: 0007a783 lw a5,0(a5) -80001080: fcf42623 sw a5,-52(s0) -80001084: fec42783 lw a5,-20(s0) -80001088: 00078593 mv a1,a5 -8000108c: 800157b7 lui a5,0x80015 -80001090: bb078513 addi a0,a5,-1104 # 80014bb0 <__BSS_END__+0xffffdf80> -80001094: 895ff0ef jal ra,80000928 -80001098: fe842583 lw a1,-24(s0) -8000109c: 800157b7 lui a5,0x80015 -800010a0: bb878513 addi a0,a5,-1096 # 80014bb8 <__BSS_END__+0xffffdf88> -800010a4: 885ff0ef jal ra,80000928 -800010a8: fcc42583 lw a1,-52(s0) -800010ac: 800157b7 lui a5,0x80015 -800010b0: bcc78513 addi a0,a5,-1076 # 80014bcc <__BSS_END__+0xffffdf9c> -800010b4: 875ff0ef jal ra,80000928 -800010b8: 800157b7 lui a5,0x80015 -800010bc: bdc78513 addi a0,a5,-1060 # 80014bdc <__BSS_END__+0xffffdfac> -800010c0: f68ff0ef jal ra,80000828 -800010c4: fe842783 lw a5,-24(s0) -800010c8: 00178793 addi a5,a5,1 -800010cc: fef42423 sw a5,-24(s0) -800010d0: fec42783 lw a5,-20(s0) -800010d4: 00478793 addi a5,a5,4 -800010d8: fef42623 sw a5,-20(s0) -800010dc: fe442783 lw a5,-28(s0) -800010e0: 00178793 addi a5,a5,1 -800010e4: fef42223 sw a5,-28(s0) -800010e8: fe442703 lw a4,-28(s0) -800010ec: 00400793 li a5,4 -800010f0: f6e7dee3 bge a5,a4,8000106c -800010f4: 800157b7 lui a5,0x80015 -800010f8: bf478513 addi a0,a5,-1036 # 80014bf4 <__BSS_END__+0xffffdfc4> -800010fc: f2cff0ef jal ra,80000828 -80001100: 91418793 addi a5,gp,-1772 # 8001611c -80001104: faf42c23 sw a5,-72(s0) -80001108: 95418793 addi a5,gp,-1708 # 8001615c -8000110c: faf42e23 sw a5,-68(s0) -80001110: 38018793 addi a5,gp,896 # 80016b88 -80001114: fcf42023 sw a5,-64(s0) -80001118: 00400793 li a5,4 -8000111c: fcf42223 sw a5,-60(s0) -80001120: 00400793 li a5,4 -80001124: fcf42423 sw a5,-56(s0) -80001128: 00400793 li a5,4 -8000112c: fcf42c23 sw a5,-40(s0) -80001130: 00400793 li a5,4 -80001134: fcf42a23 sw a5,-44(s0) -80001138: fd842703 lw a4,-40(s0) -8000113c: fd442583 lw a1,-44(s0) -80001140: fb840793 addi a5,s0,-72 -80001144: 00078693 mv a3,a5 -80001148: 800017b7 lui a5,0x80001 -8000114c: ef878613 addi a2,a5,-264 # 80000ef8 <__BSS_END__+0xfffea2c8> -80001150: 00070513 mv a0,a4 -80001154: 881ff0ef jal ra,800009d4 -80001158: fe042023 sw zero,-32(s0) -8000115c: 07c0006f j 800011d8 -80001160: fc042e23 sw zero,-36(s0) -80001164: 0500006f j 800011b4 -80001168: fc442703 lw a4,-60(s0) -8000116c: fe042783 lw a5,-32(s0) -80001170: 02f70733 mul a4,a4,a5 -80001174: fdc42783 lw a5,-36(s0) -80001178: 00f707b3 add a5,a4,a5 -8000117c: fcf42823 sw a5,-48(s0) -80001180: 38018713 addi a4,gp,896 # 80016b88 -80001184: fd042783 lw a5,-48(s0) -80001188: 00279793 slli a5,a5,0x2 -8000118c: 00f707b3 add a5,a4,a5 -80001190: 0007a783 lw a5,0(a5) -80001194: 00078513 mv a0,a5 -80001198: eccff0ef jal ra,80000864 +80000fd0 : +80000fd0: fc010113 addi sp,sp,-64 +80000fd4: 02112e23 sw ra,60(sp) +80000fd8: 02812c23 sw s0,56(sp) +80000fdc: 04010413 addi s0,sp,64 +80000fe0: fca42623 sw a0,-52(s0) +80000fe4: fcc42783 lw a5,-52(s0) +80000fe8: fef42623 sw a5,-20(s0) +80000fec: f70ff0ef jal ra,8000075c +80000ff0: fea42423 sw a0,-24(s0) +80000ff4: f78ff0ef jal ra,8000076c +80000ff8: fea42223 sw a0,-28(s0) +80000ffc: fec42783 lw a5,-20(s0) +80001000: 0107a783 lw a5,16(a5) +80001004: fe842703 lw a4,-24(s0) +80001008: 00f77e63 bgeu a4,a5,80001024 +8000100c: fec42783 lw a5,-20(s0) +80001010: 00c7a783 lw a5,12(a5) +80001014: fe442703 lw a4,-28(s0) +80001018: 00f77663 bgeu a4,a5,80001024 +8000101c: 00100793 li a5,1 +80001020: 0080006f j 80001028 +80001024: 00000793 li a5,0 +80001028: fef401a3 sb a5,-29(s0) +8000102c: fe344783 lbu a5,-29(s0) +80001030: 0017f793 andi a5,a5,1 +80001034: fef401a3 sb a5,-29(s0) +80001038: fe344783 lbu a5,-29(s0) +8000103c: 00078513 mv a0,a5 +80001040: f0cff0ef jal ra,8000074c +80001044: fe344783 lbu a5,-29(s0) +80001048: 06078663 beqz a5,800010b4 +8000104c: fec42783 lw a5,-20(s0) +80001050: 00c7a703 lw a4,12(a5) +80001054: fe842783 lw a5,-24(s0) +80001058: 02f707b3 mul a5,a4,a5 +8000105c: fe442703 lw a4,-28(s0) +80001060: 00f707b3 add a5,a4,a5 +80001064: fcf42e23 sw a5,-36(s0) +80001068: fec42783 lw a5,-20(s0) +8000106c: 0007a703 lw a4,0(a5) +80001070: fdc42783 lw a5,-36(s0) +80001074: 00279793 slli a5,a5,0x2 +80001078: 00f707b3 add a5,a4,a5 +8000107c: 0007a683 lw a3,0(a5) +80001080: fec42783 lw a5,-20(s0) +80001084: 0047a703 lw a4,4(a5) +80001088: fdc42783 lw a5,-36(s0) +8000108c: 00279793 slli a5,a5,0x2 +80001090: 00f707b3 add a5,a4,a5 +80001094: 0007a703 lw a4,0(a5) +80001098: fec42783 lw a5,-20(s0) +8000109c: 0087a603 lw a2,8(a5) +800010a0: fdc42783 lw a5,-36(s0) +800010a4: 00279793 slli a5,a5,0x2 +800010a8: 00f607b3 add a5,a2,a5 +800010ac: 00e68733 add a4,a3,a4 +800010b0: 00e7a023 sw a4,0(a5) +800010b4: ea0ff0ef jal ra,80000754 +800010b8: 00000013 nop +800010bc: 03c12083 lw ra,60(sp) +800010c0: 03812403 lw s0,56(sp) +800010c4: 04010113 addi sp,sp,64 +800010c8: 00008067 ret + +800010cc
: +800010cc: f2010113 addi sp,sp,-224 +800010d0: 0c112e23 sw ra,220(sp) +800010d4: 0c812c23 sw s0,216(sp) +800010d8: 0e010413 addi s0,sp,224 +800010dc: 00100513 li a0,1 +800010e0: e5cff0ef jal ra,8000073c +800010e4: 800157b7 lui a5,0x80015 +800010e8: b9c78513 addi a0,a5,-1124 # 80014b9c <__BSS_END__+0xffffdf60> +800010ec: ed8ff0ef jal ra,800007c4 +800010f0: fe042623 sw zero,-20(s0) +800010f4: 0280006f j 8000111c +800010f8: fec42703 lw a4,-20(s0) +800010fc: fec42783 lw a5,-20(s0) +80001100: 00279793 slli a5,a5,0x2 +80001104: ff040693 addi a3,s0,-16 +80001108: 00f687b3 add a5,a3,a5 +8000110c: f4e7a223 sw a4,-188(a5) +80001110: fec42783 lw a5,-20(s0) +80001114: 00178793 addi a5,a5,1 +80001118: fef42623 sw a5,-20(s0) +8000111c: fec42703 lw a4,-20(s0) +80001120: 02300793 li a5,35 +80001124: fce7dae3 bge a5,a4,800010f8 +80001128: fe042423 sw zero,-24(s0) +8000112c: 0340006f j 80001160 +80001130: fe842783 lw a5,-24(s0) +80001134: 00279793 slli a5,a5,0x2 +80001138: ff040713 addi a4,s0,-16 +8000113c: 00f707b3 add a5,a4,a5 +80001140: f447a783 lw a5,-188(a5) +80001144: 00078593 mv a1,a5 +80001148: 800157b7 lui a5,0x80015 +8000114c: bac78513 addi a0,a5,-1108 # 80014bac <__BSS_END__+0xffffdf70> +80001150: f74ff0ef jal ra,800008c4 +80001154: fe842783 lw a5,-24(s0) +80001158: 00178793 addi a5,a5,1 +8000115c: fef42423 sw a5,-24(s0) +80001160: fe842703 lw a4,-24(s0) +80001164: 02300793 li a5,35 +80001168: fce7d4e3 bge a5,a4,80001130 +8000116c: 800157b7 lui a5,0x80015 +80001170: bb478513 addi a0,a5,-1100 # 80014bb4 <__BSS_END__+0xffffdf78> +80001174: e50ff0ef jal ra,800007c4 +80001178: ab1ff0ef jal ra,80000c28 +8000117c: 800157b7 lui a5,0x80015 +80001180: bc478513 addi a0,a5,-1084 # 80014bc4 <__BSS_END__+0xffffdf88> +80001184: e40ff0ef jal ra,800007c4 +80001188: 00400513 li a0,4 +8000118c: db0ff0ef jal ra,8000073c +80001190: b69ff0ef jal ra,80000cf8 +80001194: 00100513 li a0,1 +80001198: da4ff0ef jal ra,8000073c 8000119c: 800157b7 lui a5,0x80015 -800011a0: c1478513 addi a0,a5,-1004 # 80014c14 <__BSS_END__+0xffffdfe4> -800011a4: e84ff0ef jal ra,80000828 -800011a8: fdc42783 lw a5,-36(s0) -800011ac: 00178793 addi a5,a5,1 -800011b0: fcf42e23 sw a5,-36(s0) -800011b4: fc442703 lw a4,-60(s0) -800011b8: fdc42783 lw a5,-36(s0) -800011bc: fae7e6e3 bltu a5,a4,80001168 -800011c0: 800157b7 lui a5,0x80015 -800011c4: c1878513 addi a0,a5,-1000 # 80014c18 <__BSS_END__+0xffffdfe8> -800011c8: e60ff0ef jal ra,80000828 -800011cc: fe042783 lw a5,-32(s0) -800011d0: 00178793 addi a5,a5,1 -800011d4: fef42023 sw a5,-32(s0) -800011d8: fc842703 lw a4,-56(s0) -800011dc: fe042783 lw a5,-32(s0) -800011e0: f8e7e0e3 bltu a5,a4,80001160 -800011e4: 00000793 li a5,0 -800011e8: 00078513 mv a0,a5 -800011ec: 04c12083 lw ra,76(sp) -800011f0: 04812403 lw s0,72(sp) -800011f4: 05010113 addi sp,sp,80 -800011f8: 00008067 ret +800011a0: bd878513 addi a0,a5,-1064 # 80014bd8 <__BSS_END__+0xffffdf9c> +800011a4: e20ff0ef jal ra,800007c4 +800011a8: d21ff0ef jal ra,80000ec8 +800011ac: 800157b7 lui a5,0x80015 +800011b0: be878513 addi a0,a5,-1048 # 80014be8 <__BSS_END__+0xffffdfac> +800011b4: e10ff0ef jal ra,800007c4 +800011b8: ffff07b7 lui a5,0xffff0 +800011bc: fef42223 sw a5,-28(s0) +800011c0: fe042023 sw zero,-32(s0) +800011c4: fc042e23 sw zero,-36(s0) +800011c8: 0800006f j 80001248 +800011cc: fe442783 lw a5,-28(s0) +800011d0: fe042703 lw a4,-32(s0) +800011d4: 00e7a023 sw a4,0(a5) # ffff0000 <__BSS_END__+0x7ffd93c4> +800011d8: fe442783 lw a5,-28(s0) +800011dc: 0007a783 lw a5,0(a5) +800011e0: fcf42223 sw a5,-60(s0) +800011e4: fe442783 lw a5,-28(s0) +800011e8: 00078593 mv a1,a5 +800011ec: 800157b7 lui a5,0x80015 +800011f0: bfc78513 addi a0,a5,-1028 # 80014bfc <__BSS_END__+0xffffdfc0> +800011f4: ed0ff0ef jal ra,800008c4 +800011f8: fe042583 lw a1,-32(s0) +800011fc: 800157b7 lui a5,0x80015 +80001200: c0478513 addi a0,a5,-1020 # 80014c04 <__BSS_END__+0xffffdfc8> +80001204: ec0ff0ef jal ra,800008c4 +80001208: fc442583 lw a1,-60(s0) +8000120c: 800157b7 lui a5,0x80015 +80001210: c1878513 addi a0,a5,-1000 # 80014c18 <__BSS_END__+0xffffdfdc> +80001214: eb0ff0ef jal ra,800008c4 +80001218: 800157b7 lui a5,0x80015 +8000121c: c2878513 addi a0,a5,-984 # 80014c28 <__BSS_END__+0xffffdfec> +80001220: da4ff0ef jal ra,800007c4 +80001224: fe042783 lw a5,-32(s0) +80001228: 00178793 addi a5,a5,1 +8000122c: fef42023 sw a5,-32(s0) +80001230: fe442783 lw a5,-28(s0) +80001234: 00478793 addi a5,a5,4 +80001238: fef42223 sw a5,-28(s0) +8000123c: fdc42783 lw a5,-36(s0) +80001240: 00178793 addi a5,a5,1 +80001244: fcf42e23 sw a5,-36(s0) +80001248: fdc42703 lw a4,-36(s0) +8000124c: 00400793 li a5,4 +80001250: f6e7dee3 bge a5,a4,800011cc +80001254: 800157b7 lui a5,0x80015 +80001258: c4078513 addi a0,a5,-960 # 80014c40 <__BSS_END__+0xffffe004> +8000125c: d68ff0ef jal ra,800007c4 +80001260: 91418793 addi a5,gp,-1772 # 8001611c +80001264: f2f42023 sw a5,-224(s0) +80001268: 95418793 addi a5,gp,-1708 # 8001615c +8000126c: f2f42223 sw a5,-220(s0) +80001270: 38018793 addi a5,gp,896 # 80016b88 +80001274: f2f42423 sw a5,-216(s0) +80001278: 00400793 li a5,4 +8000127c: f2f42623 sw a5,-212(s0) +80001280: 00400793 li a5,4 +80001284: f2f42823 sw a5,-208(s0) +80001288: 00400793 li a5,4 +8000128c: fcf42823 sw a5,-48(s0) +80001290: 00400793 li a5,4 +80001294: fcf42623 sw a5,-52(s0) +80001298: fd042703 lw a4,-48(s0) +8000129c: fcc42583 lw a1,-52(s0) +800012a0: f2040793 addi a5,s0,-224 +800012a4: 00078693 mv a3,a5 +800012a8: 800017b7 lui a5,0x80001 +800012ac: fd078613 addi a2,a5,-48 # 80000fd0 <__BSS_END__+0xfffea394> +800012b0: 00070513 mv a0,a4 +800012b4: ebcff0ef jal ra,80000970 +800012b8: fc042c23 sw zero,-40(s0) +800012bc: 07c0006f j 80001338 +800012c0: fc042a23 sw zero,-44(s0) +800012c4: 0500006f j 80001314 +800012c8: f2c42703 lw a4,-212(s0) +800012cc: fd842783 lw a5,-40(s0) +800012d0: 02f70733 mul a4,a4,a5 +800012d4: fd442783 lw a5,-44(s0) +800012d8: 00f707b3 add a5,a4,a5 +800012dc: fcf42423 sw a5,-56(s0) +800012e0: 38018713 addi a4,gp,896 # 80016b88 +800012e4: fc842783 lw a5,-56(s0) +800012e8: 00279793 slli a5,a5,0x2 +800012ec: 00f707b3 add a5,a4,a5 +800012f0: 0007a783 lw a5,0(a5) +800012f4: 00078513 mv a0,a5 +800012f8: d08ff0ef jal ra,80000800 +800012fc: 800157b7 lui a5,0x80015 +80001300: c6078513 addi a0,a5,-928 # 80014c60 <__BSS_END__+0xffffe024> +80001304: cc0ff0ef jal ra,800007c4 +80001308: fd442783 lw a5,-44(s0) +8000130c: 00178793 addi a5,a5,1 +80001310: fcf42a23 sw a5,-44(s0) +80001314: f2c42703 lw a4,-212(s0) +80001318: fd442783 lw a5,-44(s0) +8000131c: fae7e6e3 bltu a5,a4,800012c8 +80001320: 800157b7 lui a5,0x80015 +80001324: c6478513 addi a0,a5,-924 # 80014c64 <__BSS_END__+0xffffe028> +80001328: c9cff0ef jal ra,800007c4 +8000132c: fd842783 lw a5,-40(s0) +80001330: 00178793 addi a5,a5,1 +80001334: fcf42c23 sw a5,-40(s0) +80001338: f3042703 lw a4,-208(s0) +8000133c: fd842783 lw a5,-40(s0) +80001340: f8e7e0e3 bltu a5,a4,800012c0 +80001344: 00000793 li a5,0 +80001348: 00078513 mv a0,a5 +8000134c: 0dc12083 lw ra,220(sp) +80001350: 0d812403 lw s0,216(sp) +80001354: 0e010113 addi sp,sp,224 +80001358: 00008067 ret -800011fc : -800011fc: 00050593 mv a1,a0 -80001200: 00000693 li a3,0 -80001204: 00000613 li a2,0 -80001208: 00000513 li a0,0 -8000120c: 7590206f j 80004164 <__register_exitproc> +8000135c : +8000135c: ff010113 addi sp,sp,-16 +80001360: 00000593 li a1,0 +80001364: 00812423 sw s0,8(sp) +80001368: 00112623 sw ra,12(sp) +8000136c: 00050413 mv s0,a0 +80001370: 56d020ef jal ra,800040dc <__call_exitprocs> +80001374: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> +80001378: 03c52783 lw a5,60(a0) +8000137c: 00078463 beqz a5,80001384 +80001380: 000780e7 jalr a5 +80001384: 00040513 mv a0,s0 +80001388: 9d4ff0ef jal ra,8000055c <_exit> -80001210 : -80001210: ff010113 addi sp,sp,-16 -80001214: 00000593 li a1,0 -80001218: 00812423 sw s0,8(sp) -8000121c: 00112623 sw ra,12(sp) -80001220: 00050413 mv s0,a0 -80001224: 7d9020ef jal ra,800041fc <__call_exitprocs> -80001228: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> -8000122c: 03c52783 lw a5,60(a0) -80001230: 00078463 beqz a5,80001238 -80001234: 000780e7 jalr a5 -80001238: 00040513 mv a0,s0 -8000123c: b84ff0ef jal ra,800005c0 <_exit> +8000138c <_printf_r>: +8000138c: fc010113 addi sp,sp,-64 +80001390: 02c12423 sw a2,40(sp) +80001394: 02d12623 sw a3,44(sp) +80001398: 02e12823 sw a4,48(sp) +8000139c: 02f12a23 sw a5,52(sp) +800013a0: 03012c23 sw a6,56(sp) +800013a4: 03112e23 sw a7,60(sp) +800013a8: 00058613 mv a2,a1 +800013ac: 00852583 lw a1,8(a0) +800013b0: 02810693 addi a3,sp,40 +800013b4: 00112e23 sw ra,28(sp) +800013b8: 00d12623 sw a3,12(sp) +800013bc: 05c000ef jal ra,80001418 <_vfprintf_r> +800013c0: 01c12083 lw ra,28(sp) +800013c4: 04010113 addi sp,sp,64 +800013c8: 00008067 ret -80001240 <__libc_fini_array>: -80001240: ff010113 addi sp,sp,-16 -80001244: 00812423 sw s0,8(sp) -80001248: 800167b7 lui a5,0x80016 -8000124c: 80016437 lui s0,0x80016 -80001250: 00440413 addi s0,s0,4 # 80016004 <__BSS_END__+0xfffff3d4> -80001254: 00478793 addi a5,a5,4 # 80016004 <__BSS_END__+0xfffff3d4> -80001258: 408787b3 sub a5,a5,s0 -8000125c: 00912223 sw s1,4(sp) -80001260: 00112623 sw ra,12(sp) -80001264: 4027d493 srai s1,a5,0x2 -80001268: 02048063 beqz s1,80001288 <__libc_fini_array+0x48> -8000126c: ffc78793 addi a5,a5,-4 -80001270: 00878433 add s0,a5,s0 -80001274: 00042783 lw a5,0(s0) -80001278: fff48493 addi s1,s1,-1 -8000127c: ffc40413 addi s0,s0,-4 -80001280: 000780e7 jalr a5 -80001284: fe0498e3 bnez s1,80001274 <__libc_fini_array+0x34> -80001288: 00c12083 lw ra,12(sp) -8000128c: 00812403 lw s0,8(sp) -80001290: 00412483 lw s1,4(sp) -80001294: 01010113 addi sp,sp,16 -80001298: 00008067 ret +800013cc : +800013cc: 3601a303 lw t1,864(gp) # 80016b68 <_impure_ptr> +800013d0: fc010113 addi sp,sp,-64 +800013d4: 02c12423 sw a2,40(sp) +800013d8: 02d12623 sw a3,44(sp) +800013dc: 02b12223 sw a1,36(sp) +800013e0: 02e12823 sw a4,48(sp) +800013e4: 02f12a23 sw a5,52(sp) +800013e8: 03012c23 sw a6,56(sp) +800013ec: 03112e23 sw a7,60(sp) +800013f0: 00832583 lw a1,8(t1) +800013f4: 02410693 addi a3,sp,36 +800013f8: 00050613 mv a2,a0 +800013fc: 00030513 mv a0,t1 +80001400: 00112e23 sw ra,28(sp) +80001404: 00d12623 sw a3,12(sp) +80001408: 010000ef jal ra,80001418 <_vfprintf_r> +8000140c: 01c12083 lw ra,28(sp) +80001410: 04010113 addi sp,sp,64 +80001414: 00008067 ret -8000129c <__libc_init_array>: -8000129c: ff010113 addi sp,sp,-16 -800012a0: 00812423 sw s0,8(sp) -800012a4: 01212023 sw s2,0(sp) -800012a8: 80016437 lui s0,0x80016 -800012ac: 80016937 lui s2,0x80016 -800012b0: 00040793 mv a5,s0 -800012b4: 00090913 mv s2,s2 -800012b8: 40f90933 sub s2,s2,a5 -800012bc: 00112623 sw ra,12(sp) -800012c0: 00912223 sw s1,4(sp) -800012c4: 40295913 srai s2,s2,0x2 -800012c8: 02090063 beqz s2,800012e8 <__libc_init_array+0x4c> -800012cc: 00040413 mv s0,s0 -800012d0: 00000493 li s1,0 -800012d4: 00042783 lw a5,0(s0) # 80016000 <__BSS_END__+0xfffff3d0> -800012d8: 00148493 addi s1,s1,1 -800012dc: 00440413 addi s0,s0,4 -800012e0: 000780e7 jalr a5 -800012e4: fe9918e3 bne s2,s1,800012d4 <__libc_init_array+0x38> -800012e8: 80016437 lui s0,0x80016 -800012ec: 80016937 lui s2,0x80016 -800012f0: 00040793 mv a5,s0 -800012f4: 00490913 addi s2,s2,4 # 80016004 <__BSS_END__+0xfffff3d4> -800012f8: 40f90933 sub s2,s2,a5 -800012fc: 40295913 srai s2,s2,0x2 -80001300: 02090063 beqz s2,80001320 <__libc_init_array+0x84> -80001304: 00040413 mv s0,s0 -80001308: 00000493 li s1,0 -8000130c: 00042783 lw a5,0(s0) # 80016000 <__BSS_END__+0xfffff3d0> -80001310: 00148493 addi s1,s1,1 -80001314: 00440413 addi s0,s0,4 -80001318: 000780e7 jalr a5 -8000131c: fe9918e3 bne s2,s1,8000130c <__libc_init_array+0x70> -80001320: 00c12083 lw ra,12(sp) -80001324: 00812403 lw s0,8(sp) -80001328: 00412483 lw s1,4(sp) -8000132c: 00012903 lw s2,0(sp) -80001330: 01010113 addi sp,sp,16 -80001334: 00008067 ret - -80001338 : -80001338: 00f00313 li t1,15 -8000133c: 00050713 mv a4,a0 -80001340: 02c37e63 bgeu t1,a2,8000137c -80001344: 00f77793 andi a5,a4,15 -80001348: 0a079063 bnez a5,800013e8 -8000134c: 08059263 bnez a1,800013d0 -80001350: ff067693 andi a3,a2,-16 -80001354: 00f67613 andi a2,a2,15 -80001358: 00e686b3 add a3,a3,a4 -8000135c: 00b72023 sw a1,0(a4) -80001360: 00b72223 sw a1,4(a4) -80001364: 00b72423 sw a1,8(a4) -80001368: 00b72623 sw a1,12(a4) -8000136c: 01070713 addi a4,a4,16 -80001370: fed766e3 bltu a4,a3,8000135c -80001374: 00061463 bnez a2,8000137c -80001378: 00008067 ret -8000137c: 40c306b3 sub a3,t1,a2 -80001380: 00269693 slli a3,a3,0x2 -80001384: 00000297 auipc t0,0x0 -80001388: 005686b3 add a3,a3,t0 -8000138c: 00c68067 jr 12(a3) -80001390: 00b70723 sb a1,14(a4) -80001394: 00b706a3 sb a1,13(a4) -80001398: 00b70623 sb a1,12(a4) -8000139c: 00b705a3 sb a1,11(a4) -800013a0: 00b70523 sb a1,10(a4) -800013a4: 00b704a3 sb a1,9(a4) -800013a8: 00b70423 sb a1,8(a4) -800013ac: 00b703a3 sb a1,7(a4) -800013b0: 00b70323 sb a1,6(a4) -800013b4: 00b702a3 sb a1,5(a4) -800013b8: 00b70223 sb a1,4(a4) -800013bc: 00b701a3 sb a1,3(a4) -800013c0: 00b70123 sb a1,2(a4) -800013c4: 00b700a3 sb a1,1(a4) -800013c8: 00b70023 sb a1,0(a4) -800013cc: 00008067 ret -800013d0: 0ff5f593 andi a1,a1,255 -800013d4: 00859693 slli a3,a1,0x8 -800013d8: 00d5e5b3 or a1,a1,a3 -800013dc: 01059693 slli a3,a1,0x10 -800013e0: 00d5e5b3 or a1,a1,a3 -800013e4: f6dff06f j 80001350 -800013e8: 00279693 slli a3,a5,0x2 -800013ec: 00000297 auipc t0,0x0 -800013f0: 005686b3 add a3,a3,t0 -800013f4: 00008293 mv t0,ra -800013f8: fa0680e7 jalr -96(a3) -800013fc: 00028093 mv ra,t0 -80001400: ff078793 addi a5,a5,-16 -80001404: 40f70733 sub a4,a4,a5 -80001408: 00f60633 add a2,a2,a5 -8000140c: f6c378e3 bgeu t1,a2,8000137c -80001410: f3dff06f j 8000134c - -80001414 <_printf_r>: -80001414: fc010113 addi sp,sp,-64 -80001418: 02c12423 sw a2,40(sp) -8000141c: 02d12623 sw a3,44(sp) -80001420: 02e12823 sw a4,48(sp) -80001424: 02f12a23 sw a5,52(sp) -80001428: 03012c23 sw a6,56(sp) -8000142c: 03112e23 sw a7,60(sp) -80001430: 00058613 mv a2,a1 -80001434: 00852583 lw a1,8(a0) -80001438: 02810693 addi a3,sp,40 -8000143c: 00112e23 sw ra,28(sp) -80001440: 00d12623 sw a3,12(sp) -80001444: 05c000ef jal ra,800014a0 <_vfprintf_r> -80001448: 01c12083 lw ra,28(sp) -8000144c: 04010113 addi sp,sp,64 -80001450: 00008067 ret - -80001454 : -80001454: 3601a303 lw t1,864(gp) # 80016b68 <_impure_ptr> -80001458: fc010113 addi sp,sp,-64 -8000145c: 02c12423 sw a2,40(sp) -80001460: 02d12623 sw a3,44(sp) -80001464: 02b12223 sw a1,36(sp) -80001468: 02e12823 sw a4,48(sp) -8000146c: 02f12a23 sw a5,52(sp) -80001470: 03012c23 sw a6,56(sp) -80001474: 03112e23 sw a7,60(sp) -80001478: 00832583 lw a1,8(t1) -8000147c: 02410693 addi a3,sp,36 -80001480: 00050613 mv a2,a0 -80001484: 00030513 mv a0,t1 -80001488: 00112e23 sw ra,28(sp) -8000148c: 00d12623 sw a3,12(sp) -80001490: 010000ef jal ra,800014a0 <_vfprintf_r> -80001494: 01c12083 lw ra,28(sp) -80001498: 04010113 addi sp,sp,64 -8000149c: 00008067 ret - -800014a0 <_vfprintf_r>: -800014a0: e1010113 addi sp,sp,-496 -800014a4: 1e112623 sw ra,492(sp) -800014a8: 1f212023 sw s2,480(sp) -800014ac: 1d812423 sw s8,456(sp) -800014b0: 1da12023 sw s10,448(sp) -800014b4: 00058c13 mv s8,a1 -800014b8: 00060913 mv s2,a2 -800014bc: 00d12a23 sw a3,20(sp) -800014c0: 1e812423 sw s0,488(sp) -800014c4: 1e912223 sw s1,484(sp) -800014c8: 1d312e23 sw s3,476(sp) -800014cc: 1d412c23 sw s4,472(sp) -800014d0: 1d512a23 sw s5,468(sp) -800014d4: 1d612823 sw s6,464(sp) -800014d8: 1d712623 sw s7,460(sp) -800014dc: 1d912223 sw s9,452(sp) -800014e0: 1bb12e23 sw s11,444(sp) -800014e4: 00050d13 mv s10,a0 -800014e8: 570060ef jal ra,80007a58 <_localeconv_r> -800014ec: 00052783 lw a5,0(a0) -800014f0: 00078513 mv a0,a5 -800014f4: 02f12823 sw a5,48(sp) -800014f8: 6c0080ef jal ra,80009bb8 -800014fc: 02a12623 sw a0,44(sp) -80001500: 0e012823 sw zero,240(sp) -80001504: 0e012a23 sw zero,244(sp) -80001508: 0e012c23 sw zero,248(sp) -8000150c: 0e012e23 sw zero,252(sp) -80001510: 000d0663 beqz s10,8000151c <_vfprintf_r+0x7c> -80001514: 038d2703 lw a4,56(s10) -80001518: 0a0708e3 beqz a4,80001dc8 <_vfprintf_r+0x928> -8000151c: 00cc1683 lh a3,12(s8) -80001520: 01069713 slli a4,a3,0x10 -80001524: 01269793 slli a5,a3,0x12 -80001528: 01075713 srli a4,a4,0x10 -8000152c: 0207ca63 bltz a5,80001560 <_vfprintf_r+0xc0> -80001530: 00002737 lui a4,0x2 -80001534: 064c2603 lw a2,100(s8) -80001538: 00e6e733 or a4,a3,a4 -8000153c: 01071713 slli a4,a4,0x10 -80001540: ffffe6b7 lui a3,0xffffe -80001544: 41075713 srai a4,a4,0x10 -80001548: fff68693 addi a3,a3,-1 # ffffdfff <__BSS_END__+0x7ffe73cf> -8000154c: 00d676b3 and a3,a2,a3 -80001550: 00ec1623 sh a4,12(s8) -80001554: 01071713 slli a4,a4,0x10 -80001558: 06dc2223 sw a3,100(s8) -8000155c: 01075713 srli a4,a4,0x10 -80001560: 00877693 andi a3,a4,8 -80001564: 2e068863 beqz a3,80001854 <_vfprintf_r+0x3b4> -80001568: 010c2683 lw a3,16(s8) -8000156c: 2e068463 beqz a3,80001854 <_vfprintf_r+0x3b4> -80001570: 01a77713 andi a4,a4,26 -80001574: 00a00693 li a3,10 -80001578: 30d70063 beq a4,a3,80001878 <_vfprintf_r+0x3d8> -8000157c: 10c10793 addi a5,sp,268 -80001580: 80015737 lui a4,0x80015 -80001584: 0ef12223 sw a5,228(sp) -80001588: 00078893 mv a7,a5 -8000158c: c6070793 addi a5,a4,-928 # 80014c60 <__BSS_END__+0xffffe030> -80001590: 80015737 lui a4,0x80015 -80001594: 00f12c23 sw a5,24(sp) -80001598: 00090b13 mv s6,s2 -8000159c: ddc70793 addi a5,a4,-548 # 80014ddc <__BSS_END__+0xffffe1ac> -800015a0: 00f12423 sw a5,8(sp) -800015a4: 000b4783 lbu a5,0(s6) -800015a8: 0e012623 sw zero,236(sp) -800015ac: 0e012423 sw zero,232(sp) -800015b0: 02012023 sw zero,32(sp) -800015b4: 02012a23 sw zero,52(sp) -800015b8: 02012c23 sw zero,56(sp) -800015bc: 02012e23 sw zero,60(sp) -800015c0: 04012423 sw zero,72(sp) -800015c4: 04012623 sw zero,76(sp) -800015c8: 00012623 sw zero,12(sp) -800015cc: 22078663 beqz a5,800017f8 <_vfprintf_r+0x358> -800015d0: 000b0413 mv s0,s6 -800015d4: 02500693 li a3,37 -800015d8: 30d78a63 beq a5,a3,800018ec <_vfprintf_r+0x44c> -800015dc: 00144783 lbu a5,1(s0) -800015e0: 00140413 addi s0,s0,1 -800015e4: fe079ae3 bnez a5,800015d8 <_vfprintf_r+0x138> -800015e8: 416404b3 sub s1,s0,s6 -800015ec: 21640663 beq s0,s6,800017f8 <_vfprintf_r+0x358> -800015f0: 0ec12683 lw a3,236(sp) -800015f4: 0e812783 lw a5,232(sp) -800015f8: 0168a023 sw s6,0(a7) -800015fc: 009686b3 add a3,a3,s1 -80001600: 00178793 addi a5,a5,1 -80001604: 0098a223 sw s1,4(a7) -80001608: 0ed12623 sw a3,236(sp) -8000160c: 0ef12423 sw a5,232(sp) -80001610: 00700693 li a3,7 -80001614: 00888893 addi a7,a7,8 -80001618: 2ef6c263 blt a3,a5,800018fc <_vfprintf_r+0x45c> -8000161c: 00c12703 lw a4,12(sp) -80001620: 00044783 lbu a5,0(s0) -80001624: 00970733 add a4,a4,s1 -80001628: 00e12623 sw a4,12(sp) -8000162c: 1c078663 beqz a5,800017f8 <_vfprintf_r+0x358> -80001630: 00144483 lbu s1,1(s0) -80001634: 0c0103a3 sb zero,199(sp) -80001638: 00140413 addi s0,s0,1 -8000163c: fff00d93 li s11,-1 -80001640: 00000993 li s3,0 -80001644: 00000a13 li s4,0 -80001648: 05a00913 li s2,90 -8000164c: 00900a93 li s5,9 -80001650: 02a00b93 li s7,42 -80001654: 00088c93 mv s9,a7 -80001658: 00140413 addi s0,s0,1 -8000165c: fe048793 addi a5,s1,-32 -80001660: 04f96463 bltu s2,a5,800016a8 <_vfprintf_r+0x208> -80001664: 01812703 lw a4,24(sp) -80001668: 00279793 slli a5,a5,0x2 -8000166c: 00e787b3 add a5,a5,a4 -80001670: 0007a783 lw a5,0(a5) -80001674: 00078067 jr a5 -80001678: 00000993 li s3,0 -8000167c: fd048693 addi a3,s1,-48 -80001680: 00044483 lbu s1,0(s0) -80001684: 00299793 slli a5,s3,0x2 -80001688: 013787b3 add a5,a5,s3 -8000168c: 00179793 slli a5,a5,0x1 -80001690: 00f689b3 add s3,a3,a5 -80001694: fd048693 addi a3,s1,-48 -80001698: 00140413 addi s0,s0,1 -8000169c: fedaf2e3 bgeu s5,a3,80001680 <_vfprintf_r+0x1e0> -800016a0: fe048793 addi a5,s1,-32 -800016a4: fcf970e3 bgeu s2,a5,80001664 <_vfprintf_r+0x1c4> -800016a8: 000c8893 mv a7,s9 -800016ac: 14048663 beqz s1,800017f8 <_vfprintf_r+0x358> -800016b0: 14910623 sb s1,332(sp) -800016b4: 0c0103a3 sb zero,199(sp) -800016b8: 00100a93 li s5,1 -800016bc: 00100c93 li s9,1 -800016c0: 14c10b13 addi s6,sp,332 -800016c4: 00012823 sw zero,16(sp) -800016c8: 00000d93 li s11,0 -800016cc: 02012423 sw zero,40(sp) -800016d0: 02012223 sw zero,36(sp) -800016d4: 00012e23 sw zero,28(sp) -800016d8: 002a7b93 andi s7,s4,2 -800016dc: 000b8463 beqz s7,800016e4 <_vfprintf_r+0x244> -800016e0: 002a8a93 addi s5,s5,2 -800016e4: 084a7913 andi s2,s4,132 -800016e8: 0ec12783 lw a5,236(sp) -800016ec: 00091663 bnez s2,800016f8 <_vfprintf_r+0x258> -800016f0: 41598833 sub a6,s3,s5 -800016f4: 710046e3 bgtz a6,80002600 <_vfprintf_r+0x1160> -800016f8: 0c714683 lbu a3,199(sp) -800016fc: 02068a63 beqz a3,80001730 <_vfprintf_r+0x290> -80001700: 0e812683 lw a3,232(sp) -80001704: 0c710613 addi a2,sp,199 -80001708: 00c8a023 sw a2,0(a7) -8000170c: 00178793 addi a5,a5,1 -80001710: 00100613 li a2,1 -80001714: 00168693 addi a3,a3,1 -80001718: 00c8a223 sw a2,4(a7) -8000171c: 0ef12623 sw a5,236(sp) -80001720: 0ed12423 sw a3,232(sp) -80001724: 00700613 li a2,7 -80001728: 00888893 addi a7,a7,8 -8000172c: 52d64263 blt a2,a3,80001c50 <_vfprintf_r+0x7b0> -80001730: 020b8c63 beqz s7,80001768 <_vfprintf_r+0x2c8> -80001734: 0e812683 lw a3,232(sp) -80001738: 0c810613 addi a2,sp,200 -8000173c: 00c8a023 sw a2,0(a7) -80001740: 00278793 addi a5,a5,2 -80001744: 00200613 li a2,2 -80001748: 00168693 addi a3,a3,1 -8000174c: 00c8a223 sw a2,4(a7) -80001750: 0ef12623 sw a5,236(sp) -80001754: 0ed12423 sw a3,232(sp) -80001758: 00700613 li a2,7 -8000175c: 00888893 addi a7,a7,8 -80001760: 00d65463 bge a2,a3,80001768 <_vfprintf_r+0x2c8> -80001764: 78d0006f j 800026f0 <_vfprintf_r+0x1250> -80001768: 08000693 li a3,128 -8000176c: 3cd90ee3 beq s2,a3,80002348 <_vfprintf_r+0xea8> -80001770: 419d8db3 sub s11,s11,s9 -80001774: 49b04ae3 bgtz s11,80002408 <_vfprintf_r+0xf68> -80001778: 100a7693 andi a3,s4,256 -8000177c: 280698e3 bnez a3,8000220c <_vfprintf_r+0xd6c> -80001780: 0e812703 lw a4,232(sp) -80001784: 019787b3 add a5,a5,s9 -80001788: 0168a023 sw s6,0(a7) -8000178c: 00170713 addi a4,a4,1 -80001790: 0198a223 sw s9,4(a7) -80001794: 0ef12623 sw a5,236(sp) -80001798: 0ee12423 sw a4,232(sp) -8000179c: 00700693 li a3,7 -800017a0: 54e6c863 blt a3,a4,80001cf0 <_vfprintf_r+0x850> -800017a4: 00888893 addi a7,a7,8 -800017a8: 004a7a13 andi s4,s4,4 -800017ac: 000a0663 beqz s4,800017b8 <_vfprintf_r+0x318> -800017b0: 415984b3 sub s1,s3,s5 -800017b4: 54904e63 bgtz s1,80001d10 <_vfprintf_r+0x870> -800017b8: 0159d463 bge s3,s5,800017c0 <_vfprintf_r+0x320> -800017bc: 000a8993 mv s3,s5 -800017c0: 00c12703 lw a4,12(sp) -800017c4: 01370733 add a4,a4,s3 -800017c8: 00e12623 sw a4,12(sp) -800017cc: 4e0798e3 bnez a5,800024bc <_vfprintf_r+0x101c> -800017d0: 01012783 lw a5,16(sp) -800017d4: 0e012423 sw zero,232(sp) -800017d8: 00078863 beqz a5,800017e8 <_vfprintf_r+0x348> -800017dc: 01012583 lw a1,16(sp) -800017e0: 000d0513 mv a0,s10 -800017e4: 2a0030ef jal ra,80004a84 <_free_r> -800017e8: 10c10893 addi a7,sp,268 -800017ec: 00040b13 mv s6,s0 -800017f0: 000b4783 lbu a5,0(s6) -800017f4: dc079ee3 bnez a5,800015d0 <_vfprintf_r+0x130> -800017f8: 0ec12783 lw a5,236(sp) -800017fc: 00078463 beqz a5,80001804 <_vfprintf_r+0x364> -80001800: 3250106f j 80003324 <_vfprintf_r+0x1e84> -80001804: 00cc5783 lhu a5,12(s8) -80001808: 0407f793 andi a5,a5,64 -8000180c: 00078463 beqz a5,80001814 <_vfprintf_r+0x374> -80001810: 2300206f j 80003a40 <_vfprintf_r+0x25a0> -80001814: 1ec12083 lw ra,492(sp) -80001818: 1e812403 lw s0,488(sp) -8000181c: 00c12503 lw a0,12(sp) -80001820: 1e412483 lw s1,484(sp) -80001824: 1e012903 lw s2,480(sp) -80001828: 1dc12983 lw s3,476(sp) -8000182c: 1d812a03 lw s4,472(sp) -80001830: 1d412a83 lw s5,468(sp) -80001834: 1d012b03 lw s6,464(sp) -80001838: 1cc12b83 lw s7,460(sp) -8000183c: 1c812c03 lw s8,456(sp) -80001840: 1c412c83 lw s9,452(sp) -80001844: 1c012d03 lw s10,448(sp) -80001848: 1bc12d83 lw s11,444(sp) -8000184c: 1f010113 addi sp,sp,496 -80001850: 00008067 ret -80001854: 000c0593 mv a1,s8 -80001858: 000d0513 mv a0,s10 -8000185c: 7ac020ef jal ra,80004008 <__swsetup_r> -80001860: 00050463 beqz a0,80001868 <_vfprintf_r+0x3c8> -80001864: 1dc0206f j 80003a40 <_vfprintf_r+0x25a0> -80001868: 00cc5703 lhu a4,12(s8) -8000186c: 00a00693 li a3,10 -80001870: 01a77713 andi a4,a4,26 -80001874: d0d714e3 bne a4,a3,8000157c <_vfprintf_r+0xdc> -80001878: 00ec1703 lh a4,14(s8) -8000187c: d00740e3 bltz a4,8000157c <_vfprintf_r+0xdc> -80001880: 01412683 lw a3,20(sp) -80001884: 00090613 mv a2,s2 -80001888: 000c0593 mv a1,s8 -8000188c: 000d0513 mv a0,s10 -80001890: 6b8020ef jal ra,80003f48 <__sbprintf> -80001894: 00a12623 sw a0,12(sp) -80001898: f7dff06f j 80001814 <_vfprintf_r+0x374> -8000189c: 000d0513 mv a0,s10 -800018a0: 1b8060ef jal ra,80007a58 <_localeconv_r> -800018a4: 00452783 lw a5,4(a0) -800018a8: 00078513 mv a0,a5 -800018ac: 04f12623 sw a5,76(sp) -800018b0: 308080ef jal ra,80009bb8 -800018b4: 00050793 mv a5,a0 -800018b8: 000d0513 mv a0,s10 -800018bc: 00078493 mv s1,a5 -800018c0: 04f12423 sw a5,72(sp) -800018c4: 194060ef jal ra,80007a58 <_localeconv_r> -800018c8: 00852783 lw a5,8(a0) -800018cc: 02f12e23 sw a5,60(sp) -800018d0: 00048463 beqz s1,800018d8 <_vfprintf_r+0x438> -800018d4: 12c0106f j 80002a00 <_vfprintf_r+0x1560> -800018d8: 00044483 lbu s1,0(s0) -800018dc: d7dff06f j 80001658 <_vfprintf_r+0x1b8> -800018e0: 00044483 lbu s1,0(s0) -800018e4: 020a6a13 ori s4,s4,32 -800018e8: d71ff06f j 80001658 <_vfprintf_r+0x1b8> -800018ec: 416404b3 sub s1,s0,s6 -800018f0: d16410e3 bne s0,s6,800015f0 <_vfprintf_r+0x150> -800018f4: 00044783 lbu a5,0(s0) -800018f8: d35ff06f j 8000162c <_vfprintf_r+0x18c> -800018fc: 0e410613 addi a2,sp,228 -80001900: 000c0593 mv a1,s8 -80001904: 000d0513 mv a0,s10 -80001908: 6e90a0ef jal ra,8000c7f0 <__sprint_r> -8000190c: ee051ce3 bnez a0,80001804 <_vfprintf_r+0x364> -80001910: 10c10893 addi a7,sp,268 -80001914: d09ff06f j 8000161c <_vfprintf_r+0x17c> -80001918: 008a7793 andi a5,s4,8 -8000191c: 000c8893 mv a7,s9 -80001920: 00078463 beqz a5,80001928 <_vfprintf_r+0x488> -80001924: 12c0106f j 80002a50 <_vfprintf_r+0x15b0> -80001928: 01412783 lw a5,20(sp) -8000192c: 0b010513 addi a0,sp,176 -80001930: 01912823 sw s9,16(sp) -80001934: 00778793 addi a5,a5,7 -80001938: ff87f793 andi a5,a5,-8 -8000193c: 0007a583 lw a1,0(a5) -80001940: 0047a603 lw a2,4(a5) -80001944: 00878793 addi a5,a5,8 -80001948: 00f12a23 sw a5,20(sp) -8000194c: 279120ef jal ra,800143c4 <__extenddftf2> -80001950: 0b012783 lw a5,176(sp) -80001954: 01012883 lw a7,16(sp) -80001958: 0ef12823 sw a5,240(sp) -8000195c: 0b412783 lw a5,180(sp) -80001960: 0ef12a23 sw a5,244(sp) -80001964: 0b812783 lw a5,184(sp) -80001968: 0ef12c23 sw a5,248(sp) -8000196c: 0bc12783 lw a5,188(sp) -80001970: 0ef12e23 sw a5,252(sp) -80001974: 0f010513 addi a0,sp,240 -80001978: 01112823 sw a7,16(sp) -8000197c: 070060ef jal ra,800079ec <_ldcheck> -80001980: 0ca12623 sw a0,204(sp) -80001984: 00200793 li a5,2 -80001988: 01012883 lw a7,16(sp) -8000198c: 00f51463 bne a0,a5,80001994 <_vfprintf_r+0x4f4> -80001990: 4fc0106f j 80002e8c <_vfprintf_r+0x19ec> -80001994: 00100793 li a5,1 -80001998: 00f51463 bne a0,a5,800019a0 <_vfprintf_r+0x500> -8000199c: 6440106f j 80002fe0 <_vfprintf_r+0x1b40> -800019a0: 06100793 li a5,97 -800019a4: 00f49463 bne s1,a5,800019ac <_vfprintf_r+0x50c> -800019a8: 1c40206f j 80003b6c <_vfprintf_r+0x26cc> -800019ac: 04100793 li a5,65 -800019b0: 00f49463 bne s1,a5,800019b8 <_vfprintf_r+0x518> -800019b4: 1910106f j 80003344 <_vfprintf_r+0x1ea4> -800019b8: fdf4fb93 andi s7,s1,-33 -800019bc: fff00793 li a5,-1 -800019c0: 05712223 sw s7,68(sp) -800019c4: 00fd9463 bne s11,a5,800019cc <_vfprintf_r+0x52c> -800019c8: 2800206f j 80003c48 <_vfprintf_r+0x27a8> -800019cc: 04700793 li a5,71 -800019d0: 00fb9463 bne s7,a5,800019d8 <_vfprintf_r+0x538> -800019d4: 1e00206f j 80003bb4 <_vfprintf_r+0x2714> -800019d8: 0fc12303 lw t1,252(sp) -800019dc: 03412423 sw s4,40(sp) -800019e0: 0f012e03 lw t3,240(sp) -800019e4: 0f412e83 lw t4,244(sp) -800019e8: 0f812f03 lw t5,248(sp) -800019ec: 100a6793 ori a5,s4,256 -800019f0: 00035463 bgez t1,800019f8 <_vfprintf_r+0x558> -800019f4: 3e00206f j 80003dd4 <_vfprintf_r+0x2934> -800019f8: 04012c23 sw zero,88(sp) -800019fc: 00078a13 mv s4,a5 -80001a00: 00012823 sw zero,16(sp) -80001a04: 04600793 li a5,70 -80001a08: 00fb9463 bne s7,a5,80001a10 <_vfprintf_r+0x570> -80001a0c: 6990106f j 800038a4 <_vfprintf_r+0x2404> -80001a10: 04500793 li a5,69 -80001a14: 05112823 sw a7,80(sp) -80001a18: 00fb8463 beq s7,a5,80001a20 <_vfprintf_r+0x580> -80001a1c: 6090106f j 80003824 <_vfprintf_r+0x2384> -80001a20: 001d8913 addi s2,s11,1 -80001a24: 0b010a93 addi s5,sp,176 -80001a28: 00090693 mv a3,s2 -80001a2c: 0dc10813 addi a6,sp,220 -80001a30: 0d010793 addi a5,sp,208 -80001a34: 0cc10713 addi a4,sp,204 -80001a38: 00200613 li a2,2 -80001a3c: 000a8593 mv a1,s5 -80001a40: 000d0513 mv a0,s10 -80001a44: 0bc12823 sw t3,176(sp) -80001a48: 05c12023 sw t3,64(sp) -80001a4c: 0bd12a23 sw t4,180(sp) -80001a50: 03d12223 sw t4,36(sp) -80001a54: 0be12c23 sw t5,184(sp) -80001a58: 03e12023 sw t5,32(sp) -80001a5c: 0a612e23 sw t1,188(sp) -80001a60: 00612e23 sw t1,28(sp) -80001a64: 4f1040ef jal ra,80006754 <_ldtoa_r> -80001a68: 01c12303 lw t1,28(sp) -80001a6c: 02012f03 lw t5,32(sp) -80001a70: 02412e83 lw t4,36(sp) -80001a74: 04012e03 lw t3,64(sp) -80001a78: 05012883 lw a7,80(sp) -80001a7c: 00050b13 mv s6,a0 -80001a80: 01250933 add s2,a0,s2 -80001a84: 0a010c93 addi s9,sp,160 -80001a88: 000c8593 mv a1,s9 -80001a8c: 000a8513 mv a0,s5 -80001a90: 01112e23 sw a7,28(sp) -80001a94: 0bc12823 sw t3,176(sp) -80001a98: 0bd12a23 sw t4,180(sp) -80001a9c: 0be12c23 sw t5,184(sp) -80001aa0: 0a612e23 sw t1,188(sp) -80001aa4: 0a012023 sw zero,160(sp) -80001aa8: 0a012223 sw zero,164(sp) -80001aac: 0a012423 sw zero,168(sp) -80001ab0: 0a012623 sw zero,172(sp) -80001ab4: 6350f0ef jal ra,800118e8 <__eqtf2> -80001ab8: 01c12883 lw a7,28(sp) -80001abc: 00090713 mv a4,s2 -80001ac0: 02050263 beqz a0,80001ae4 <_vfprintf_r+0x644> -80001ac4: 0dc12703 lw a4,220(sp) -80001ac8: 01277e63 bgeu a4,s2,80001ae4 <_vfprintf_r+0x644> -80001acc: 03000693 li a3,48 -80001ad0: 00170793 addi a5,a4,1 -80001ad4: 0cf12e23 sw a5,220(sp) -80001ad8: 00d70023 sb a3,0(a4) -80001adc: 0dc12703 lw a4,220(sp) -80001ae0: ff2768e3 bltu a4,s2,80001ad0 <_vfprintf_r+0x630> -80001ae4: 416707b3 sub a5,a4,s6 -80001ae8: 02f12023 sw a5,32(sp) -80001aec: 0cc12703 lw a4,204(sp) -80001af0: 04700793 li a5,71 -80001af4: 00e12e23 sw a4,28(sp) -80001af8: 04412703 lw a4,68(sp) -80001afc: 00f71463 bne a4,a5,80001b04 <_vfprintf_r+0x664> -80001b00: 43d0106f j 8000373c <_vfprintf_r+0x229c> -80001b04: 04412703 lw a4,68(sp) -80001b08: 04600793 li a5,70 -80001b0c: 00f71463 bne a4,a5,80001b14 <_vfprintf_r+0x674> -80001b10: 67d0106f j 8000398c <_vfprintf_r+0x24ec> -80001b14: 01c12783 lw a5,28(sp) -80001b18: 04412703 lw a4,68(sp) -80001b1c: 04100593 li a1,65 -80001b20: fff78793 addi a5,a5,-1 -80001b24: 0cf12623 sw a5,204(sp) -80001b28: 0ff4f693 andi a3,s1,255 -80001b2c: 00000613 li a2,0 -80001b30: 00b71863 bne a4,a1,80001b40 <_vfprintf_r+0x6a0> -80001b34: 00f68693 addi a3,a3,15 -80001b38: 0ff6f693 andi a3,a3,255 -80001b3c: 00100613 li a2,1 -80001b40: 0cd10a23 sb a3,212(sp) -80001b44: 02b00693 li a3,43 -80001b48: 0007da63 bgez a5,80001b5c <_vfprintf_r+0x6bc> -80001b4c: 01c12703 lw a4,28(sp) -80001b50: 00100793 li a5,1 -80001b54: 02d00693 li a3,45 -80001b58: 40e787b3 sub a5,a5,a4 -80001b5c: 0cd10aa3 sb a3,213(sp) -80001b60: 00900693 li a3,9 -80001b64: 00f6c463 blt a3,a5,80001b6c <_vfprintf_r+0x6cc> -80001b68: 28c0206f j 80003df4 <_vfprintf_r+0x2954> -80001b6c: 0e310813 addi a6,sp,227 -80001b70: 00080513 mv a0,a6 -80001b74: 00a00613 li a2,10 -80001b78: 06300e13 li t3,99 -80001b7c: 02c7e733 rem a4,a5,a2 -80001b80: 00050593 mv a1,a0 -80001b84: 00078693 mv a3,a5 -80001b88: fff50513 addi a0,a0,-1 -80001b8c: 03070713 addi a4,a4,48 -80001b90: fee58fa3 sb a4,-1(a1) -80001b94: 02c7c7b3 div a5,a5,a2 -80001b98: fede42e3 blt t3,a3,80001b7c <_vfprintf_r+0x6dc> -80001b9c: 03078793 addi a5,a5,48 -80001ba0: 0ff7f613 andi a2,a5,255 -80001ba4: fec50fa3 sb a2,-1(a0) -80001ba8: ffe58793 addi a5,a1,-2 -80001bac: 0107e463 bltu a5,a6,80001bb4 <_vfprintf_r+0x714> -80001bb0: 3740206f j 80003f24 <_vfprintf_r+0x2a84> -80001bb4: 0d610693 addi a3,sp,214 -80001bb8: 0080006f j 80001bc0 <_vfprintf_r+0x720> -80001bbc: 0007c603 lbu a2,0(a5) -80001bc0: 00c68023 sb a2,0(a3) -80001bc4: 00178793 addi a5,a5,1 -80001bc8: 00168693 addi a3,a3,1 -80001bcc: ff0798e3 bne a5,a6,80001bbc <_vfprintf_r+0x71c> -80001bd0: 0e510793 addi a5,sp,229 -80001bd4: 40b787b3 sub a5,a5,a1 -80001bd8: 0d610713 addi a4,sp,214 -80001bdc: 00f707b3 add a5,a4,a5 -80001be0: 0d410693 addi a3,sp,212 -80001be4: 40d787b3 sub a5,a5,a3 -80001be8: 02f12c23 sw a5,56(sp) -80001bec: 02012703 lw a4,32(sp) -80001bf0: 03812683 lw a3,56(sp) -80001bf4: 00100793 li a5,1 -80001bf8: 00d70cb3 add s9,a4,a3 -80001bfc: 00e7c463 blt a5,a4,80001c04 <_vfprintf_r+0x764> -80001c00: 2940206f j 80003e94 <_vfprintf_r+0x29f4> -80001c04: 02c12783 lw a5,44(sp) -80001c08: 00fc8cb3 add s9,s9,a5 -80001c0c: 02812783 lw a5,40(sp) -80001c10: fffcca93 not s5,s9 -80001c14: 41fada93 srai s5,s5,0x1f -80001c18: bff7fa13 andi s4,a5,-1025 -80001c1c: 100a6a13 ori s4,s4,256 -80001c20: 015cfab3 and s5,s9,s5 -80001c24: 02012423 sw zero,40(sp) -80001c28: 02012223 sw zero,36(sp) -80001c2c: 00012e23 sw zero,28(sp) -80001c30: 05812783 lw a5,88(sp) -80001c34: 00079463 bnez a5,80001c3c <_vfprintf_r+0x79c> -80001c38: 3790106f j 800037b0 <_vfprintf_r+0x2310> -80001c3c: 02d00793 li a5,45 -80001c40: 0cf103a3 sb a5,199(sp) -80001c44: 00000d93 li s11,0 -80001c48: 001a8a93 addi s5,s5,1 -80001c4c: a8dff06f j 800016d8 <_vfprintf_r+0x238> -80001c50: 0e410613 addi a2,sp,228 -80001c54: 000c0593 mv a1,s8 -80001c58: 000d0513 mv a0,s10 -80001c5c: 3950a0ef jal ra,8000c7f0 <__sprint_r> -80001c60: 060518e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80001c64: 0ec12783 lw a5,236(sp) -80001c68: 10c10893 addi a7,sp,268 -80001c6c: ac5ff06f j 80001730 <_vfprintf_r+0x290> -80001c70: 03012683 lw a3,48(sp) -80001c74: 02c12703 lw a4,44(sp) -80001c78: 00700613 li a2,7 -80001c7c: 00d8a023 sw a3,0(a7) -80001c80: 0e812683 lw a3,232(sp) -80001c84: 00f707b3 add a5,a4,a5 -80001c88: 00e8a223 sw a4,4(a7) -80001c8c: 00168693 addi a3,a3,1 -80001c90: 0ef12623 sw a5,236(sp) -80001c94: 0ed12423 sw a3,232(sp) -80001c98: 00888893 addi a7,a7,8 -80001c9c: 02d65463 bge a2,a3,80001cc4 <_vfprintf_r+0x824> -80001ca0: 0e410613 addi a2,sp,228 -80001ca4: 000c0593 mv a1,s8 -80001ca8: 000d0513 mv a0,s10 -80001cac: 3450a0ef jal ra,8000c7f0 <__sprint_r> -80001cb0: 020510e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80001cb4: 0cc12583 lw a1,204(sp) -80001cb8: 0ec12783 lw a5,236(sp) -80001cbc: 0e812683 lw a3,232(sp) -80001cc0: 10c10893 addi a7,sp,268 -80001cc4: 0005d463 bgez a1,80001ccc <_vfprintf_r+0x82c> -80001cc8: 5850106f j 80003a4c <_vfprintf_r+0x25ac> -80001ccc: 02012703 lw a4,32(sp) -80001cd0: 00168693 addi a3,a3,1 -80001cd4: 0168a023 sw s6,0(a7) -80001cd8: 00f707b3 add a5,a4,a5 -80001cdc: 00e8a223 sw a4,4(a7) -80001ce0: 0ef12623 sw a5,236(sp) -80001ce4: 0ed12423 sw a3,232(sp) -80001ce8: 00700713 li a4,7 -80001cec: aad75ce3 bge a4,a3,800017a4 <_vfprintf_r+0x304> -80001cf0: 0e410613 addi a2,sp,228 -80001cf4: 000c0593 mv a1,s8 -80001cf8: 000d0513 mv a0,s10 -80001cfc: 2f50a0ef jal ra,8000c7f0 <__sprint_r> -80001d00: 7c051863 bnez a0,800024d0 <_vfprintf_r+0x1030> -80001d04: 0ec12783 lw a5,236(sp) -80001d08: 10c10893 addi a7,sp,268 -80001d0c: a9dff06f j 800017a8 <_vfprintf_r+0x308> -80001d10: 01000693 li a3,16 -80001d14: 0e812703 lw a4,232(sp) -80001d18: 0096c463 blt a3,s1,80001d20 <_vfprintf_r+0x880> -80001d1c: 5190106f j 80003a34 <_vfprintf_r+0x2594> -80001d20: 800156b7 lui a3,0x80015 -80001d24: dcc68e93 addi t4,a3,-564 # 80014dcc <__BSS_END__+0xffffe19c> -80001d28: 01000913 li s2,16 -80001d2c: 00700a13 li s4,7 -80001d30: 000e8b13 mv s6,t4 -80001d34: 00c0006f j 80001d40 <_vfprintf_r+0x8a0> -80001d38: ff048493 addi s1,s1,-16 -80001d3c: 04995663 bge s2,s1,80001d88 <_vfprintf_r+0x8e8> -80001d40: 01078793 addi a5,a5,16 -80001d44: 00170713 addi a4,a4,1 -80001d48: 0168a023 sw s6,0(a7) -80001d4c: 0128a223 sw s2,4(a7) -80001d50: 0ef12623 sw a5,236(sp) -80001d54: 0ee12423 sw a4,232(sp) -80001d58: 00888893 addi a7,a7,8 -80001d5c: fcea5ee3 bge s4,a4,80001d38 <_vfprintf_r+0x898> -80001d60: 0e410613 addi a2,sp,228 -80001d64: 000c0593 mv a1,s8 -80001d68: 000d0513 mv a0,s10 -80001d6c: 2850a0ef jal ra,8000c7f0 <__sprint_r> -80001d70: 76051063 bnez a0,800024d0 <_vfprintf_r+0x1030> -80001d74: ff048493 addi s1,s1,-16 -80001d78: 0ec12783 lw a5,236(sp) -80001d7c: 0e812703 lw a4,232(sp) -80001d80: 10c10893 addi a7,sp,268 -80001d84: fa994ee3 blt s2,s1,80001d40 <_vfprintf_r+0x8a0> -80001d88: 000b0e93 mv t4,s6 -80001d8c: 009787b3 add a5,a5,s1 -80001d90: 00170713 addi a4,a4,1 -80001d94: 01d8a023 sw t4,0(a7) -80001d98: 0098a223 sw s1,4(a7) -80001d9c: 0ef12623 sw a5,236(sp) -80001da0: 0ee12423 sw a4,232(sp) -80001da4: 00700693 li a3,7 -80001da8: a0e6d8e3 bge a3,a4,800017b8 <_vfprintf_r+0x318> -80001dac: 0e410613 addi a2,sp,228 -80001db0: 000c0593 mv a1,s8 -80001db4: 000d0513 mv a0,s10 -80001db8: 2390a0ef jal ra,8000c7f0 <__sprint_r> -80001dbc: 70051a63 bnez a0,800024d0 <_vfprintf_r+0x1030> -80001dc0: 0ec12783 lw a5,236(sp) -80001dc4: 9f5ff06f j 800017b8 <_vfprintf_r+0x318> -80001dc8: 000d0513 mv a0,s10 -80001dcc: 349020ef jal ra,80004914 <__sinit> -80001dd0: f4cff06f j 8000151c <_vfprintf_r+0x7c> -80001dd4: 01412703 lw a4,20(sp) -80001dd8: 000c8893 mv a7,s9 -80001ddc: 0c0103a3 sb zero,199(sp) -80001de0: 00072783 lw a5,0(a4) -80001de4: 00470713 addi a4,a4,4 -80001de8: 00e12a23 sw a4,20(sp) -80001dec: 14f10623 sb a5,332(sp) -80001df0: 00100a93 li s5,1 -80001df4: 00100c93 li s9,1 -80001df8: 14c10b13 addi s6,sp,332 -80001dfc: 8c9ff06f j 800016c4 <_vfprintf_r+0x224> -80001e00: 01412783 lw a5,20(sp) -80001e04: 0c0103a3 sb zero,199(sp) -80001e08: 000c8893 mv a7,s9 -80001e0c: 0007ab03 lw s6,0(a5) -80001e10: 00478913 addi s2,a5,4 -80001e14: 5a0b0ee3 beqz s6,80002bd0 <_vfprintf_r+0x1730> -80001e18: fff00793 li a5,-1 -80001e1c: 00fd9463 bne s11,a5,80001e24 <_vfprintf_r+0x984> -80001e20: 1000106f j 80002f20 <_vfprintf_r+0x1a80> -80001e24: 000d8613 mv a2,s11 -80001e28: 00000593 li a1,0 -80001e2c: 000b0513 mv a0,s6 -80001e30: 01912a23 sw s9,20(sp) -80001e34: 6c4060ef jal ra,800084f8 -80001e38: 00a12823 sw a0,16(sp) -80001e3c: 01412883 lw a7,20(sp) -80001e40: 00051463 bnez a0,80001e48 <_vfprintf_r+0x9a8> -80001e44: 31d0106f j 80003960 <_vfprintf_r+0x24c0> -80001e48: 01012783 lw a5,16(sp) -80001e4c: 01212a23 sw s2,20(sp) -80001e50: 00012823 sw zero,16(sp) -80001e54: 41678cb3 sub s9,a5,s6 -80001e58: 0c714783 lbu a5,199(sp) -80001e5c: fffcca93 not s5,s9 -80001e60: 41fada93 srai s5,s5,0x1f -80001e64: 02012423 sw zero,40(sp) -80001e68: 02012223 sw zero,36(sp) -80001e6c: 00012e23 sw zero,28(sp) -80001e70: 015cfab3 and s5,s9,s5 -80001e74: 00000d93 li s11,0 -80001e78: 860780e3 beqz a5,800016d8 <_vfprintf_r+0x238> -80001e7c: 001a8a93 addi s5,s5,1 -80001e80: 859ff06f j 800016d8 <_vfprintf_r+0x238> -80001e84: 00044483 lbu s1,0(s0) -80001e88: 004a6a13 ori s4,s4,4 -80001e8c: fccff06f j 80001658 <_vfprintf_r+0x1b8> -80001e90: 01412683 lw a3,20(sp) -80001e94: 020a7793 andi a5,s4,32 -80001e98: 000c8893 mv a7,s9 -80001e9c: 0006a703 lw a4,0(a3) -80001ea0: 00468693 addi a3,a3,4 -80001ea4: 00d12a23 sw a3,20(sp) -80001ea8: 36079ee3 bnez a5,80002a24 <_vfprintf_r+0x1584> -80001eac: 010a7793 andi a5,s4,16 -80001eb0: 00078463 beqz a5,80001eb8 <_vfprintf_r+0xa18> -80001eb4: 05c0106f j 80002f10 <_vfprintf_r+0x1a70> -80001eb8: 040a7793 andi a5,s4,64 -80001ebc: 00078463 beqz a5,80001ec4 <_vfprintf_r+0xa24> -80001ec0: 3fc0106f j 800032bc <_vfprintf_r+0x1e1c> -80001ec4: 200a7a13 andi s4,s4,512 -80001ec8: 000a1463 bnez s4,80001ed0 <_vfprintf_r+0xa30> -80001ecc: 0440106f j 80002f10 <_vfprintf_r+0x1a70> -80001ed0: 00c12783 lw a5,12(sp) -80001ed4: 00040b13 mv s6,s0 -80001ed8: 00f70023 sb a5,0(a4) -80001edc: 915ff06f j 800017f0 <_vfprintf_r+0x350> -80001ee0: 00044483 lbu s1,0(s0) -80001ee4: 06c00793 li a5,108 -80001ee8: 4cf484e3 beq s1,a5,80002bb0 <_vfprintf_r+0x1710> -80001eec: 010a6a13 ori s4,s4,16 -80001ef0: f68ff06f j 80001658 <_vfprintf_r+0x1b8> -80001ef4: 01412703 lw a4,20(sp) -80001ef8: ffff87b7 lui a5,0xffff8 -80001efc: 8307c793 xori a5,a5,-2000 -80001f00: 0cf11423 sh a5,200(sp) -80001f04: 00470793 addi a5,a4,4 -80001f08: 00f12a23 sw a5,20(sp) -80001f0c: 00072903 lw s2,0(a4) -80001f10: 800157b7 lui a5,0x80015 -80001f14: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -80001f18: 000c8893 mv a7,s9 -80001f1c: 02f12a23 sw a5,52(sp) -80001f20: 00000c93 li s9,0 -80001f24: 002a6b93 ori s7,s4,2 -80001f28: 00200793 li a5,2 -80001f2c: 07800493 li s1,120 -80001f30: 0c0103a3 sb zero,199(sp) -80001f34: fff00713 li a4,-1 -80001f38: 20ed8663 beq s11,a4,80002144 <_vfprintf_r+0xca4> -80001f3c: 01996733 or a4,s2,s9 -80001f40: f7fbfa13 andi s4,s7,-129 -80001f44: 1e071e63 bnez a4,80002140 <_vfprintf_r+0xca0> -80001f48: 260d9463 bnez s11,800021b0 <_vfprintf_r+0xd10> -80001f4c: 1c079063 bnez a5,8000210c <_vfprintf_r+0xc6c> -80001f50: 001bfc93 andi s9,s7,1 -80001f54: 1b010b13 addi s6,sp,432 -80001f58: 280c9ce3 bnez s9,800029f0 <_vfprintf_r+0x1550> -80001f5c: 000c8a93 mv s5,s9 -80001f60: 01bcd463 bge s9,s11,80001f68 <_vfprintf_r+0xac8> -80001f64: 000d8a93 mv s5,s11 -80001f68: 0c714783 lbu a5,199(sp) -80001f6c: 00012823 sw zero,16(sp) -80001f70: 02012423 sw zero,40(sp) -80001f74: 02012223 sw zero,36(sp) -80001f78: 00012e23 sw zero,28(sp) -80001f7c: f00790e3 bnez a5,80001e7c <_vfprintf_r+0x9dc> -80001f80: f58ff06f j 800016d8 <_vfprintf_r+0x238> -80001f84: 00044483 lbu s1,0(s0) -80001f88: 06800793 li a5,104 -80001f8c: 42f48ae3 beq s1,a5,80002bc0 <_vfprintf_r+0x1720> -80001f90: 040a6a13 ori s4,s4,64 -80001f94: ec4ff06f j 80001658 <_vfprintf_r+0x1b8> -80001f98: 02b00793 li a5,43 -80001f9c: 00044483 lbu s1,0(s0) -80001fa0: 0cf103a3 sb a5,199(sp) -80001fa4: eb4ff06f j 80001658 <_vfprintf_r+0x1b8> -80001fa8: 00044483 lbu s1,0(s0) -80001fac: 080a6a13 ori s4,s4,128 -80001fb0: ea8ff06f j 80001658 <_vfprintf_r+0x1b8> -80001fb4: 00044483 lbu s1,0(s0) -80001fb8: 00140713 addi a4,s0,1 -80001fbc: 01749463 bne s1,s7,80001fc4 <_vfprintf_r+0xb24> -80001fc0: 7250106f j 80003ee4 <_vfprintf_r+0x2a44> -80001fc4: fd048693 addi a3,s1,-48 -80001fc8: 00070413 mv s0,a4 -80001fcc: 00000d93 li s11,0 -80001fd0: e8dae663 bltu s5,a3,8000165c <_vfprintf_r+0x1bc> -80001fd4: 00044483 lbu s1,0(s0) -80001fd8: 002d9793 slli a5,s11,0x2 -80001fdc: 01b787b3 add a5,a5,s11 -80001fe0: 00179793 slli a5,a5,0x1 -80001fe4: 00d78db3 add s11,a5,a3 -80001fe8: fd048693 addi a3,s1,-48 -80001fec: 00140413 addi s0,s0,1 -80001ff0: fedaf2e3 bgeu s5,a3,80001fd4 <_vfprintf_r+0xb34> -80001ff4: e68ff06f j 8000165c <_vfprintf_r+0x1bc> -80001ff8: 01412783 lw a5,20(sp) -80001ffc: 00044483 lbu s1,0(s0) -80002000: 0007a983 lw s3,0(a5) -80002004: 00478793 addi a5,a5,4 -80002008: 00f12a23 sw a5,20(sp) -8000200c: e409d663 bgez s3,80001658 <_vfprintf_r+0x1b8> -80002010: 413009b3 neg s3,s3 -80002014: 004a6a13 ori s4,s4,4 -80002018: e40ff06f j 80001658 <_vfprintf_r+0x1b8> -8000201c: 00044483 lbu s1,0(s0) -80002020: 001a6a13 ori s4,s4,1 -80002024: e34ff06f j 80001658 <_vfprintf_r+0x1b8> -80002028: 0c714783 lbu a5,199(sp) -8000202c: 00044483 lbu s1,0(s0) -80002030: e2079463 bnez a5,80001658 <_vfprintf_r+0x1b8> -80002034: 02000793 li a5,32 -80002038: 0cf103a3 sb a5,199(sp) -8000203c: e1cff06f j 80001658 <_vfprintf_r+0x1b8> -80002040: 000c8893 mv a7,s9 -80002044: 010a6a13 ori s4,s4,16 -80002048: 020a7793 andi a5,s4,32 -8000204c: 0c078ee3 beqz a5,80002928 <_vfprintf_r+0x1488> -80002050: 01412783 lw a5,20(sp) -80002054: 00778b13 addi s6,a5,7 -80002058: ff8b7b13 andi s6,s6,-8 -8000205c: 000b2903 lw s2,0(s6) -80002060: 004b2c83 lw s9,4(s6) -80002064: 008b0793 addi a5,s6,8 -80002068: 00f12a23 sw a5,20(sp) -8000206c: bffa7b93 andi s7,s4,-1025 -80002070: 00000793 li a5,0 -80002074: ebdff06f j 80001f30 <_vfprintf_r+0xa90> -80002078: 000c8893 mv a7,s9 -8000207c: 010a6b93 ori s7,s4,16 -80002080: 020bf793 andi a5,s7,32 -80002084: 0c0788e3 beqz a5,80002954 <_vfprintf_r+0x14b4> -80002088: 01412783 lw a5,20(sp) -8000208c: 00778b13 addi s6,a5,7 -80002090: ff8b7b13 andi s6,s6,-8 -80002094: 008b0793 addi a5,s6,8 -80002098: 00f12a23 sw a5,20(sp) -8000209c: 000b2903 lw s2,0(s6) -800020a0: 004b2c83 lw s9,4(s6) -800020a4: 00100793 li a5,1 -800020a8: e89ff06f j 80001f30 <_vfprintf_r+0xa90> -800020ac: 00044483 lbu s1,0(s0) -800020b0: 008a6a13 ori s4,s4,8 -800020b4: da4ff06f j 80001658 <_vfprintf_r+0x1b8> -800020b8: 000c8893 mv a7,s9 -800020bc: 010a6a13 ori s4,s4,16 -800020c0: 020a7793 andi a5,s4,32 -800020c4: 0c0780e3 beqz a5,80002984 <_vfprintf_r+0x14e4> -800020c8: 01412783 lw a5,20(sp) -800020cc: 00778b13 addi s6,a5,7 -800020d0: ff8b7b13 andi s6,s6,-8 -800020d4: 004b2783 lw a5,4(s6) -800020d8: 000b2903 lw s2,0(s6) -800020dc: 008b0713 addi a4,s6,8 -800020e0: 00e12a23 sw a4,20(sp) -800020e4: 00078c93 mv s9,a5 -800020e8: 0c07c6e3 bltz a5,800029b4 <_vfprintf_r+0x1514> -800020ec: fff00793 li a5,-1 -800020f0: 000a0b93 mv s7,s4 -800020f4: 02fd8463 beq s11,a5,8000211c <_vfprintf_r+0xc7c> -800020f8: 019967b3 or a5,s2,s9 -800020fc: f7fa7b93 andi s7,s4,-129 -80002100: 00079e63 bnez a5,8000211c <_vfprintf_r+0xc7c> -80002104: 020d9263 bnez s11,80002128 <_vfprintf_r+0xc88> -80002108: 000b8a13 mv s4,s7 -8000210c: 00000d93 li s11,0 -80002110: 00000c93 li s9,0 -80002114: 1b010b13 addi s6,sp,432 -80002118: e45ff06f j 80001f5c <_vfprintf_r+0xabc> -8000211c: 3a0c92e3 bnez s9,80002cc0 <_vfprintf_r+0x1820> -80002120: 00900793 li a5,9 -80002124: 3927eee3 bltu a5,s2,80002cc0 <_vfprintf_r+0x1820> -80002128: 03090913 addi s2,s2,48 -8000212c: 1b2107a3 sb s2,431(sp) -80002130: 000b8a13 mv s4,s7 -80002134: 00100c93 li s9,1 -80002138: 1af10b13 addi s6,sp,431 -8000213c: e21ff06f j 80001f5c <_vfprintf_r+0xabc> -80002140: 000a0b93 mv s7,s4 -80002144: 00100713 li a4,1 -80002148: fce78ae3 beq a5,a4,8000211c <_vfprintf_r+0xc7c> -8000214c: 00200713 li a4,2 -80002150: 06e78c63 beq a5,a4,800021c8 <_vfprintf_r+0xd28> -80002154: 1b010b13 addi s6,sp,432 -80002158: 01dc9713 slli a4,s9,0x1d -8000215c: 00797793 andi a5,s2,7 -80002160: 00395913 srli s2,s2,0x3 -80002164: 03078793 addi a5,a5,48 -80002168: 01276933 or s2,a4,s2 -8000216c: 003cdc93 srli s9,s9,0x3 -80002170: fefb0fa3 sb a5,-1(s6) -80002174: 01996733 or a4,s2,s9 -80002178: 000b0613 mv a2,s6 -8000217c: fffb0b13 addi s6,s6,-1 -80002180: fc071ce3 bnez a4,80002158 <_vfprintf_r+0xcb8> -80002184: 001bf693 andi a3,s7,1 -80002188: 06068a63 beqz a3,800021fc <_vfprintf_r+0xd5c> -8000218c: 03000693 li a3,48 -80002190: 06d78663 beq a5,a3,800021fc <_vfprintf_r+0xd5c> -80002194: ffe60613 addi a2,a2,-2 -80002198: 1b010793 addi a5,sp,432 -8000219c: fedb0fa3 sb a3,-1(s6) -800021a0: 40c78cb3 sub s9,a5,a2 -800021a4: 000b8a13 mv s4,s7 -800021a8: 00060b13 mv s6,a2 -800021ac: db1ff06f j 80001f5c <_vfprintf_r+0xabc> -800021b0: 00100713 li a4,1 -800021b4: 00e79463 bne a5,a4,800021bc <_vfprintf_r+0xd1c> -800021b8: 14d0106f j 80003b04 <_vfprintf_r+0x2664> -800021bc: 00200713 li a4,2 -800021c0: 000a0b93 mv s7,s4 -800021c4: f8e798e3 bne a5,a4,80002154 <_vfprintf_r+0xcb4> -800021c8: 03412683 lw a3,52(sp) -800021cc: 1b010b13 addi s6,sp,432 -800021d0: 00f97793 andi a5,s2,15 -800021d4: 00f687b3 add a5,a3,a5 -800021d8: 0007c703 lbu a4,0(a5) -800021dc: 00495913 srli s2,s2,0x4 -800021e0: 01cc9793 slli a5,s9,0x1c -800021e4: 0127e933 or s2,a5,s2 -800021e8: 004cdc93 srli s9,s9,0x4 -800021ec: feeb0fa3 sb a4,-1(s6) -800021f0: 019967b3 or a5,s2,s9 -800021f4: fffb0b13 addi s6,s6,-1 -800021f8: fc079ce3 bnez a5,800021d0 <_vfprintf_r+0xd30> -800021fc: 1b010793 addi a5,sp,432 -80002200: 41678cb3 sub s9,a5,s6 -80002204: 000b8a13 mv s4,s7 -80002208: d55ff06f j 80001f5c <_vfprintf_r+0xabc> -8000220c: 06500693 li a3,101 -80002210: 2c96dc63 bge a3,s1,800024e8 <_vfprintf_r+0x1048> -80002214: 0f012683 lw a3,240(sp) -80002218: 0a010593 addi a1,sp,160 -8000221c: 0b010513 addi a0,sp,176 -80002220: 0ad12823 sw a3,176(sp) -80002224: 0f412683 lw a3,244(sp) -80002228: 05112223 sw a7,68(sp) -8000222c: 04f12023 sw a5,64(sp) -80002230: 0ad12a23 sw a3,180(sp) -80002234: 0f812683 lw a3,248(sp) -80002238: 0a012023 sw zero,160(sp) -8000223c: 0a012223 sw zero,164(sp) -80002240: 0ad12c23 sw a3,184(sp) -80002244: 0fc12683 lw a3,252(sp) -80002248: 0a012423 sw zero,168(sp) -8000224c: 0a012623 sw zero,172(sp) -80002250: 0ad12e23 sw a3,188(sp) -80002254: 6940f0ef jal ra,800118e8 <__eqtf2> -80002258: 04012783 lw a5,64(sp) -8000225c: 04412883 lw a7,68(sp) -80002260: 4a051863 bnez a0,80002710 <_vfprintf_r+0x1270> -80002264: 0e812703 lw a4,232(sp) -80002268: 800156b7 lui a3,0x80015 -8000226c: c5c68693 addi a3,a3,-932 # 80014c5c <__BSS_END__+0xffffe02c> -80002270: 00d8a023 sw a3,0(a7) -80002274: 00178793 addi a5,a5,1 -80002278: 00100693 li a3,1 -8000227c: 00170713 addi a4,a4,1 -80002280: 00d8a223 sw a3,4(a7) -80002284: 0ef12623 sw a5,236(sp) -80002288: 0ee12423 sw a4,232(sp) -8000228c: 00700693 li a3,7 -80002290: 00888893 addi a7,a7,8 -80002294: 3ae6c6e3 blt a3,a4,80002e40 <_vfprintf_r+0x19a0> -80002298: 0cc12703 lw a4,204(sp) -8000229c: 02012683 lw a3,32(sp) -800022a0: 72d75c63 bge a4,a3,800029d8 <_vfprintf_r+0x1538> -800022a4: 03012703 lw a4,48(sp) -800022a8: 02c12683 lw a3,44(sp) -800022ac: 00888893 addi a7,a7,8 -800022b0: fee8ac23 sw a4,-8(a7) +80001418 <_vfprintf_r>: +80001418: e1010113 addi sp,sp,-496 +8000141c: 1e112623 sw ra,492(sp) +80001420: 1f212023 sw s2,480(sp) +80001424: 1d812423 sw s8,456(sp) +80001428: 1da12023 sw s10,448(sp) +8000142c: 00058c13 mv s8,a1 +80001430: 00060913 mv s2,a2 +80001434: 00d12a23 sw a3,20(sp) +80001438: 1e812423 sw s0,488(sp) +8000143c: 1e912223 sw s1,484(sp) +80001440: 1d312e23 sw s3,476(sp) +80001444: 1d412c23 sw s4,472(sp) +80001448: 1d512a23 sw s5,468(sp) +8000144c: 1d612823 sw s6,464(sp) +80001450: 1d712623 sw s7,460(sp) +80001454: 1d912223 sw s9,452(sp) +80001458: 1bb12e23 sw s11,444(sp) +8000145c: 00050d13 mv s10,a0 +80001460: 548060ef jal ra,800079a8 <_localeconv_r> +80001464: 00052783 lw a5,0(a0) +80001468: 00078513 mv a0,a5 +8000146c: 02f12823 sw a5,48(sp) +80001470: 4f0080ef jal ra,80009960 +80001474: 02a12623 sw a0,44(sp) +80001478: 0e012823 sw zero,240(sp) +8000147c: 0e012a23 sw zero,244(sp) +80001480: 0e012c23 sw zero,248(sp) +80001484: 0e012e23 sw zero,252(sp) +80001488: 000d0663 beqz s10,80001494 <_vfprintf_r+0x7c> +8000148c: 038d2703 lw a4,56(s10) +80001490: 0a0708e3 beqz a4,80001d40 <_vfprintf_r+0x928> +80001494: 00cc1683 lh a3,12(s8) +80001498: 01069713 slli a4,a3,0x10 +8000149c: 01269793 slli a5,a3,0x12 +800014a0: 01075713 srli a4,a4,0x10 +800014a4: 0207ca63 bltz a5,800014d8 <_vfprintf_r+0xc0> +800014a8: 00002737 lui a4,0x2 +800014ac: 064c2603 lw a2,100(s8) +800014b0: 00e6e733 or a4,a3,a4 +800014b4: 01071713 slli a4,a4,0x10 +800014b8: ffffe6b7 lui a3,0xffffe +800014bc: 41075713 srai a4,a4,0x10 +800014c0: fff68693 addi a3,a3,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> +800014c4: 00d676b3 and a3,a2,a3 +800014c8: 00ec1623 sh a4,12(s8) +800014cc: 01071713 slli a4,a4,0x10 +800014d0: 06dc2223 sw a3,100(s8) +800014d4: 01075713 srli a4,a4,0x10 +800014d8: 00877693 andi a3,a4,8 +800014dc: 2e068863 beqz a3,800017cc <_vfprintf_r+0x3b4> +800014e0: 010c2683 lw a3,16(s8) +800014e4: 2e068463 beqz a3,800017cc <_vfprintf_r+0x3b4> +800014e8: 01a77713 andi a4,a4,26 +800014ec: 00a00693 li a3,10 +800014f0: 30d70063 beq a4,a3,800017f0 <_vfprintf_r+0x3d8> +800014f4: 10c10793 addi a5,sp,268 +800014f8: 80015737 lui a4,0x80015 +800014fc: 0ef12223 sw a5,228(sp) +80001500: 00078893 mv a7,a5 +80001504: cac70793 addi a5,a4,-852 # 80014cac <__BSS_END__+0xffffe070> +80001508: 80015737 lui a4,0x80015 +8000150c: 00f12c23 sw a5,24(sp) +80001510: 00090b13 mv s6,s2 +80001514: e2870793 addi a5,a4,-472 # 80014e28 <__BSS_END__+0xffffe1ec> +80001518: 00f12423 sw a5,8(sp) +8000151c: 000b4783 lbu a5,0(s6) +80001520: 0e012623 sw zero,236(sp) +80001524: 0e012423 sw zero,232(sp) +80001528: 02012023 sw zero,32(sp) +8000152c: 02012a23 sw zero,52(sp) +80001530: 02012c23 sw zero,56(sp) +80001534: 02012e23 sw zero,60(sp) +80001538: 04012423 sw zero,72(sp) +8000153c: 04012623 sw zero,76(sp) +80001540: 00012623 sw zero,12(sp) +80001544: 22078663 beqz a5,80001770 <_vfprintf_r+0x358> +80001548: 000b0413 mv s0,s6 +8000154c: 02500693 li a3,37 +80001550: 30d78a63 beq a5,a3,80001864 <_vfprintf_r+0x44c> +80001554: 00144783 lbu a5,1(s0) +80001558: 00140413 addi s0,s0,1 +8000155c: fe079ae3 bnez a5,80001550 <_vfprintf_r+0x138> +80001560: 416404b3 sub s1,s0,s6 +80001564: 21640663 beq s0,s6,80001770 <_vfprintf_r+0x358> +80001568: 0ec12683 lw a3,236(sp) +8000156c: 0e812783 lw a5,232(sp) +80001570: 0168a023 sw s6,0(a7) +80001574: 009686b3 add a3,a3,s1 +80001578: 00178793 addi a5,a5,1 +8000157c: 0098a223 sw s1,4(a7) +80001580: 0ed12623 sw a3,236(sp) +80001584: 0ef12423 sw a5,232(sp) +80001588: 00700693 li a3,7 +8000158c: 00888893 addi a7,a7,8 +80001590: 2ef6c263 blt a3,a5,80001874 <_vfprintf_r+0x45c> +80001594: 00c12703 lw a4,12(sp) +80001598: 00044783 lbu a5,0(s0) +8000159c: 00970733 add a4,a4,s1 +800015a0: 00e12623 sw a4,12(sp) +800015a4: 1c078663 beqz a5,80001770 <_vfprintf_r+0x358> +800015a8: 00144483 lbu s1,1(s0) +800015ac: 0c0103a3 sb zero,199(sp) +800015b0: 00140413 addi s0,s0,1 +800015b4: fff00d93 li s11,-1 +800015b8: 00000993 li s3,0 +800015bc: 00000a13 li s4,0 +800015c0: 05a00913 li s2,90 +800015c4: 00900a93 li s5,9 +800015c8: 02a00b93 li s7,42 +800015cc: 00088c93 mv s9,a7 +800015d0: 00140413 addi s0,s0,1 +800015d4: fe048793 addi a5,s1,-32 +800015d8: 04f96463 bltu s2,a5,80001620 <_vfprintf_r+0x208> +800015dc: 01812703 lw a4,24(sp) +800015e0: 00279793 slli a5,a5,0x2 +800015e4: 00e787b3 add a5,a5,a4 +800015e8: 0007a783 lw a5,0(a5) +800015ec: 00078067 jr a5 +800015f0: 00000993 li s3,0 +800015f4: fd048693 addi a3,s1,-48 +800015f8: 00044483 lbu s1,0(s0) +800015fc: 00299793 slli a5,s3,0x2 +80001600: 013787b3 add a5,a5,s3 +80001604: 00179793 slli a5,a5,0x1 +80001608: 00f689b3 add s3,a3,a5 +8000160c: fd048693 addi a3,s1,-48 +80001610: 00140413 addi s0,s0,1 +80001614: fedaf2e3 bgeu s5,a3,800015f8 <_vfprintf_r+0x1e0> +80001618: fe048793 addi a5,s1,-32 +8000161c: fcf970e3 bgeu s2,a5,800015dc <_vfprintf_r+0x1c4> +80001620: 000c8893 mv a7,s9 +80001624: 14048663 beqz s1,80001770 <_vfprintf_r+0x358> +80001628: 14910623 sb s1,332(sp) +8000162c: 0c0103a3 sb zero,199(sp) +80001630: 00100a93 li s5,1 +80001634: 00100c93 li s9,1 +80001638: 14c10b13 addi s6,sp,332 +8000163c: 00012823 sw zero,16(sp) +80001640: 00000d93 li s11,0 +80001644: 02012423 sw zero,40(sp) +80001648: 02012223 sw zero,36(sp) +8000164c: 00012e23 sw zero,28(sp) +80001650: 002a7b93 andi s7,s4,2 +80001654: 000b8463 beqz s7,8000165c <_vfprintf_r+0x244> +80001658: 002a8a93 addi s5,s5,2 +8000165c: 084a7913 andi s2,s4,132 +80001660: 0ec12783 lw a5,236(sp) +80001664: 00091663 bnez s2,80001670 <_vfprintf_r+0x258> +80001668: 41598833 sub a6,s3,s5 +8000166c: 710046e3 bgtz a6,80002578 <_vfprintf_r+0x1160> +80001670: 0c714683 lbu a3,199(sp) +80001674: 02068a63 beqz a3,800016a8 <_vfprintf_r+0x290> +80001678: 0e812683 lw a3,232(sp) +8000167c: 0c710613 addi a2,sp,199 +80001680: 00c8a023 sw a2,0(a7) +80001684: 00178793 addi a5,a5,1 +80001688: 00100613 li a2,1 +8000168c: 00168693 addi a3,a3,1 +80001690: 00c8a223 sw a2,4(a7) +80001694: 0ef12623 sw a5,236(sp) +80001698: 0ed12423 sw a3,232(sp) +8000169c: 00700613 li a2,7 +800016a0: 00888893 addi a7,a7,8 +800016a4: 52d64263 blt a2,a3,80001bc8 <_vfprintf_r+0x7b0> +800016a8: 020b8c63 beqz s7,800016e0 <_vfprintf_r+0x2c8> +800016ac: 0e812683 lw a3,232(sp) +800016b0: 0c810613 addi a2,sp,200 +800016b4: 00c8a023 sw a2,0(a7) +800016b8: 00278793 addi a5,a5,2 +800016bc: 00200613 li a2,2 +800016c0: 00168693 addi a3,a3,1 +800016c4: 00c8a223 sw a2,4(a7) +800016c8: 0ef12623 sw a5,236(sp) +800016cc: 0ed12423 sw a3,232(sp) +800016d0: 00700613 li a2,7 +800016d4: 00888893 addi a7,a7,8 +800016d8: 00d65463 bge a2,a3,800016e0 <_vfprintf_r+0x2c8> +800016dc: 78d0006f j 80002668 <_vfprintf_r+0x1250> +800016e0: 08000693 li a3,128 +800016e4: 3cd90ee3 beq s2,a3,800022c0 <_vfprintf_r+0xea8> +800016e8: 419d8db3 sub s11,s11,s9 +800016ec: 49b04ae3 bgtz s11,80002380 <_vfprintf_r+0xf68> +800016f0: 100a7693 andi a3,s4,256 +800016f4: 280698e3 bnez a3,80002184 <_vfprintf_r+0xd6c> +800016f8: 0e812703 lw a4,232(sp) +800016fc: 019787b3 add a5,a5,s9 +80001700: 0168a023 sw s6,0(a7) +80001704: 00170713 addi a4,a4,1 +80001708: 0198a223 sw s9,4(a7) +8000170c: 0ef12623 sw a5,236(sp) +80001710: 0ee12423 sw a4,232(sp) +80001714: 00700693 li a3,7 +80001718: 54e6c863 blt a3,a4,80001c68 <_vfprintf_r+0x850> +8000171c: 00888893 addi a7,a7,8 +80001720: 004a7a13 andi s4,s4,4 +80001724: 000a0663 beqz s4,80001730 <_vfprintf_r+0x318> +80001728: 415984b3 sub s1,s3,s5 +8000172c: 54904e63 bgtz s1,80001c88 <_vfprintf_r+0x870> +80001730: 0159d463 bge s3,s5,80001738 <_vfprintf_r+0x320> +80001734: 000a8993 mv s3,s5 +80001738: 00c12703 lw a4,12(sp) +8000173c: 01370733 add a4,a4,s3 +80001740: 00e12623 sw a4,12(sp) +80001744: 4e0798e3 bnez a5,80002434 <_vfprintf_r+0x101c> +80001748: 01012783 lw a5,16(sp) +8000174c: 0e012423 sw zero,232(sp) +80001750: 00078863 beqz a5,80001760 <_vfprintf_r+0x348> +80001754: 01012583 lw a1,16(sp) +80001758: 000d0513 mv a0,s10 +8000175c: 278030ef jal ra,800049d4 <_free_r> +80001760: 10c10893 addi a7,sp,268 +80001764: 00040b13 mv s6,s0 +80001768: 000b4783 lbu a5,0(s6) +8000176c: dc079ee3 bnez a5,80001548 <_vfprintf_r+0x130> +80001770: 0ec12783 lw a5,236(sp) +80001774: 00078463 beqz a5,8000177c <_vfprintf_r+0x364> +80001778: 3250106f j 8000329c <_vfprintf_r+0x1e84> +8000177c: 00cc5783 lhu a5,12(s8) +80001780: 0407f793 andi a5,a5,64 +80001784: 00078463 beqz a5,8000178c <_vfprintf_r+0x374> +80001788: 2300206f j 800039b8 <_vfprintf_r+0x25a0> +8000178c: 1ec12083 lw ra,492(sp) +80001790: 1e812403 lw s0,488(sp) +80001794: 00c12503 lw a0,12(sp) +80001798: 1e412483 lw s1,484(sp) +8000179c: 1e012903 lw s2,480(sp) +800017a0: 1dc12983 lw s3,476(sp) +800017a4: 1d812a03 lw s4,472(sp) +800017a8: 1d412a83 lw s5,468(sp) +800017ac: 1d012b03 lw s6,464(sp) +800017b0: 1cc12b83 lw s7,460(sp) +800017b4: 1c812c03 lw s8,456(sp) +800017b8: 1c412c83 lw s9,452(sp) +800017bc: 1c012d03 lw s10,448(sp) +800017c0: 1bc12d83 lw s11,444(sp) +800017c4: 1f010113 addi sp,sp,496 +800017c8: 00008067 ret +800017cc: 000c0593 mv a1,s8 +800017d0: 000d0513 mv a0,s10 +800017d4: 7ac020ef jal ra,80003f80 <__swsetup_r> +800017d8: 00050463 beqz a0,800017e0 <_vfprintf_r+0x3c8> +800017dc: 1dc0206f j 800039b8 <_vfprintf_r+0x25a0> +800017e0: 00cc5703 lhu a4,12(s8) +800017e4: 00a00693 li a3,10 +800017e8: 01a77713 andi a4,a4,26 +800017ec: d0d714e3 bne a4,a3,800014f4 <_vfprintf_r+0xdc> +800017f0: 00ec1703 lh a4,14(s8) +800017f4: d00740e3 bltz a4,800014f4 <_vfprintf_r+0xdc> +800017f8: 01412683 lw a3,20(sp) +800017fc: 00090613 mv a2,s2 +80001800: 000c0593 mv a1,s8 +80001804: 000d0513 mv a0,s10 +80001808: 6b8020ef jal ra,80003ec0 <__sbprintf> +8000180c: 00a12623 sw a0,12(sp) +80001810: f7dff06f j 8000178c <_vfprintf_r+0x374> +80001814: 000d0513 mv a0,s10 +80001818: 190060ef jal ra,800079a8 <_localeconv_r> +8000181c: 00452783 lw a5,4(a0) +80001820: 00078513 mv a0,a5 +80001824: 04f12623 sw a5,76(sp) +80001828: 138080ef jal ra,80009960 +8000182c: 00050793 mv a5,a0 +80001830: 000d0513 mv a0,s10 +80001834: 00078493 mv s1,a5 +80001838: 04f12423 sw a5,72(sp) +8000183c: 16c060ef jal ra,800079a8 <_localeconv_r> +80001840: 00852783 lw a5,8(a0) +80001844: 02f12e23 sw a5,60(sp) +80001848: 00048463 beqz s1,80001850 <_vfprintf_r+0x438> +8000184c: 12c0106f j 80002978 <_vfprintf_r+0x1560> +80001850: 00044483 lbu s1,0(s0) +80001854: d7dff06f j 800015d0 <_vfprintf_r+0x1b8> +80001858: 00044483 lbu s1,0(s0) +8000185c: 020a6a13 ori s4,s4,32 +80001860: d71ff06f j 800015d0 <_vfprintf_r+0x1b8> +80001864: 416404b3 sub s1,s0,s6 +80001868: d16410e3 bne s0,s6,80001568 <_vfprintf_r+0x150> +8000186c: 00044783 lbu a5,0(s0) +80001870: d35ff06f j 800015a4 <_vfprintf_r+0x18c> +80001874: 0e410613 addi a2,sp,228 +80001878: 000c0593 mv a1,s8 +8000187c: 000d0513 mv a0,s10 +80001880: 5190a0ef jal ra,8000c598 <__sprint_r> +80001884: ee051ce3 bnez a0,8000177c <_vfprintf_r+0x364> +80001888: 10c10893 addi a7,sp,268 +8000188c: d09ff06f j 80001594 <_vfprintf_r+0x17c> +80001890: 008a7793 andi a5,s4,8 +80001894: 000c8893 mv a7,s9 +80001898: 00078463 beqz a5,800018a0 <_vfprintf_r+0x488> +8000189c: 12c0106f j 800029c8 <_vfprintf_r+0x15b0> +800018a0: 01412783 lw a5,20(sp) +800018a4: 0b010513 addi a0,sp,176 +800018a8: 01912823 sw s9,16(sp) +800018ac: 00778793 addi a5,a5,7 +800018b0: ff87f793 andi a5,a5,-8 +800018b4: 0007a583 lw a1,0(a5) +800018b8: 0047a603 lw a2,4(a5) +800018bc: 00878793 addi a5,a5,8 +800018c0: 00f12a23 sw a5,20(sp) +800018c4: 3c5120ef jal ra,80014488 <__extenddftf2> +800018c8: 0b012783 lw a5,176(sp) +800018cc: 01012883 lw a7,16(sp) +800018d0: 0ef12823 sw a5,240(sp) +800018d4: 0b412783 lw a5,180(sp) +800018d8: 0ef12a23 sw a5,244(sp) +800018dc: 0b812783 lw a5,184(sp) +800018e0: 0ef12c23 sw a5,248(sp) +800018e4: 0bc12783 lw a5,188(sp) +800018e8: 0ef12e23 sw a5,252(sp) +800018ec: 0f010513 addi a0,sp,240 +800018f0: 01112823 sw a7,16(sp) +800018f4: 048060ef jal ra,8000793c <_ldcheck> +800018f8: 0ca12623 sw a0,204(sp) +800018fc: 00200793 li a5,2 +80001900: 01012883 lw a7,16(sp) +80001904: 00f51463 bne a0,a5,8000190c <_vfprintf_r+0x4f4> +80001908: 4fc0106f j 80002e04 <_vfprintf_r+0x19ec> +8000190c: 00100793 li a5,1 +80001910: 00f51463 bne a0,a5,80001918 <_vfprintf_r+0x500> +80001914: 6440106f j 80002f58 <_vfprintf_r+0x1b40> +80001918: 06100793 li a5,97 +8000191c: 00f49463 bne s1,a5,80001924 <_vfprintf_r+0x50c> +80001920: 1c40206f j 80003ae4 <_vfprintf_r+0x26cc> +80001924: 04100793 li a5,65 +80001928: 00f49463 bne s1,a5,80001930 <_vfprintf_r+0x518> +8000192c: 1910106f j 800032bc <_vfprintf_r+0x1ea4> +80001930: fdf4fb93 andi s7,s1,-33 +80001934: fff00793 li a5,-1 +80001938: 05712223 sw s7,68(sp) +8000193c: 00fd9463 bne s11,a5,80001944 <_vfprintf_r+0x52c> +80001940: 2800206f j 80003bc0 <_vfprintf_r+0x27a8> +80001944: 04700793 li a5,71 +80001948: 00fb9463 bne s7,a5,80001950 <_vfprintf_r+0x538> +8000194c: 1e00206f j 80003b2c <_vfprintf_r+0x2714> +80001950: 0fc12303 lw t1,252(sp) +80001954: 03412423 sw s4,40(sp) +80001958: 0f012e03 lw t3,240(sp) +8000195c: 0f412e83 lw t4,244(sp) +80001960: 0f812f03 lw t5,248(sp) +80001964: 100a6793 ori a5,s4,256 +80001968: 00035463 bgez t1,80001970 <_vfprintf_r+0x558> +8000196c: 3e00206f j 80003d4c <_vfprintf_r+0x2934> +80001970: 04012c23 sw zero,88(sp) +80001974: 00078a13 mv s4,a5 +80001978: 00012823 sw zero,16(sp) +8000197c: 04600793 li a5,70 +80001980: 00fb9463 bne s7,a5,80001988 <_vfprintf_r+0x570> +80001984: 6990106f j 8000381c <_vfprintf_r+0x2404> +80001988: 04500793 li a5,69 +8000198c: 05112823 sw a7,80(sp) +80001990: 00fb8463 beq s7,a5,80001998 <_vfprintf_r+0x580> +80001994: 6090106f j 8000379c <_vfprintf_r+0x2384> +80001998: 001d8913 addi s2,s11,1 +8000199c: 0b010a93 addi s5,sp,176 +800019a0: 00090693 mv a3,s2 +800019a4: 0dc10813 addi a6,sp,220 +800019a8: 0d010793 addi a5,sp,208 +800019ac: 0cc10713 addi a4,sp,204 +800019b0: 00200613 li a2,2 +800019b4: 000a8593 mv a1,s5 +800019b8: 000d0513 mv a0,s10 +800019bc: 0bc12823 sw t3,176(sp) +800019c0: 05c12023 sw t3,64(sp) +800019c4: 0bd12a23 sw t4,180(sp) +800019c8: 03d12223 sw t4,36(sp) +800019cc: 0be12c23 sw t5,184(sp) +800019d0: 03e12023 sw t5,32(sp) +800019d4: 0a612e23 sw t1,188(sp) +800019d8: 00612e23 sw t1,28(sp) +800019dc: 4c9040ef jal ra,800066a4 <_ldtoa_r> +800019e0: 01c12303 lw t1,28(sp) +800019e4: 02012f03 lw t5,32(sp) +800019e8: 02412e83 lw t4,36(sp) +800019ec: 04012e03 lw t3,64(sp) +800019f0: 05012883 lw a7,80(sp) +800019f4: 00050b13 mv s6,a0 +800019f8: 01250933 add s2,a0,s2 +800019fc: 0a010c93 addi s9,sp,160 +80001a00: 000c8593 mv a1,s9 +80001a04: 000a8513 mv a0,s5 +80001a08: 01112e23 sw a7,28(sp) +80001a0c: 0bc12823 sw t3,176(sp) +80001a10: 0bd12a23 sw t4,180(sp) +80001a14: 0be12c23 sw t5,184(sp) +80001a18: 0a612e23 sw t1,188(sp) +80001a1c: 0a012023 sw zero,160(sp) +80001a20: 0a012223 sw zero,164(sp) +80001a24: 0a012423 sw zero,168(sp) +80001a28: 0a012623 sw zero,172(sp) +80001a2c: 7810f0ef jal ra,800119ac <__eqtf2> +80001a30: 01c12883 lw a7,28(sp) +80001a34: 00090713 mv a4,s2 +80001a38: 02050263 beqz a0,80001a5c <_vfprintf_r+0x644> +80001a3c: 0dc12703 lw a4,220(sp) +80001a40: 01277e63 bgeu a4,s2,80001a5c <_vfprintf_r+0x644> +80001a44: 03000693 li a3,48 +80001a48: 00170793 addi a5,a4,1 +80001a4c: 0cf12e23 sw a5,220(sp) +80001a50: 00d70023 sb a3,0(a4) +80001a54: 0dc12703 lw a4,220(sp) +80001a58: ff2768e3 bltu a4,s2,80001a48 <_vfprintf_r+0x630> +80001a5c: 416707b3 sub a5,a4,s6 +80001a60: 02f12023 sw a5,32(sp) +80001a64: 0cc12703 lw a4,204(sp) +80001a68: 04700793 li a5,71 +80001a6c: 00e12e23 sw a4,28(sp) +80001a70: 04412703 lw a4,68(sp) +80001a74: 00f71463 bne a4,a5,80001a7c <_vfprintf_r+0x664> +80001a78: 43d0106f j 800036b4 <_vfprintf_r+0x229c> +80001a7c: 04412703 lw a4,68(sp) +80001a80: 04600793 li a5,70 +80001a84: 00f71463 bne a4,a5,80001a8c <_vfprintf_r+0x674> +80001a88: 67d0106f j 80003904 <_vfprintf_r+0x24ec> +80001a8c: 01c12783 lw a5,28(sp) +80001a90: 04412703 lw a4,68(sp) +80001a94: 04100593 li a1,65 +80001a98: fff78793 addi a5,a5,-1 +80001a9c: 0cf12623 sw a5,204(sp) +80001aa0: 0ff4f693 andi a3,s1,255 +80001aa4: 00000613 li a2,0 +80001aa8: 00b71863 bne a4,a1,80001ab8 <_vfprintf_r+0x6a0> +80001aac: 00f68693 addi a3,a3,15 +80001ab0: 0ff6f693 andi a3,a3,255 +80001ab4: 00100613 li a2,1 +80001ab8: 0cd10a23 sb a3,212(sp) +80001abc: 02b00693 li a3,43 +80001ac0: 0007da63 bgez a5,80001ad4 <_vfprintf_r+0x6bc> +80001ac4: 01c12703 lw a4,28(sp) +80001ac8: 00100793 li a5,1 +80001acc: 02d00693 li a3,45 +80001ad0: 40e787b3 sub a5,a5,a4 +80001ad4: 0cd10aa3 sb a3,213(sp) +80001ad8: 00900693 li a3,9 +80001adc: 00f6c463 blt a3,a5,80001ae4 <_vfprintf_r+0x6cc> +80001ae0: 28c0206f j 80003d6c <_vfprintf_r+0x2954> +80001ae4: 0e310813 addi a6,sp,227 +80001ae8: 00080513 mv a0,a6 +80001aec: 00a00613 li a2,10 +80001af0: 06300e13 li t3,99 +80001af4: 02c7e733 rem a4,a5,a2 +80001af8: 00050593 mv a1,a0 +80001afc: 00078693 mv a3,a5 +80001b00: fff50513 addi a0,a0,-1 +80001b04: 03070713 addi a4,a4,48 +80001b08: fee58fa3 sb a4,-1(a1) +80001b0c: 02c7c7b3 div a5,a5,a2 +80001b10: fede42e3 blt t3,a3,80001af4 <_vfprintf_r+0x6dc> +80001b14: 03078793 addi a5,a5,48 +80001b18: 0ff7f613 andi a2,a5,255 +80001b1c: fec50fa3 sb a2,-1(a0) +80001b20: ffe58793 addi a5,a1,-2 +80001b24: 0107e463 bltu a5,a6,80001b2c <_vfprintf_r+0x714> +80001b28: 3740206f j 80003e9c <_vfprintf_r+0x2a84> +80001b2c: 0d610693 addi a3,sp,214 +80001b30: 0080006f j 80001b38 <_vfprintf_r+0x720> +80001b34: 0007c603 lbu a2,0(a5) +80001b38: 00c68023 sb a2,0(a3) +80001b3c: 00178793 addi a5,a5,1 +80001b40: 00168693 addi a3,a3,1 +80001b44: ff0798e3 bne a5,a6,80001b34 <_vfprintf_r+0x71c> +80001b48: 0e510793 addi a5,sp,229 +80001b4c: 40b787b3 sub a5,a5,a1 +80001b50: 0d610713 addi a4,sp,214 +80001b54: 00f707b3 add a5,a4,a5 +80001b58: 0d410693 addi a3,sp,212 +80001b5c: 40d787b3 sub a5,a5,a3 +80001b60: 02f12c23 sw a5,56(sp) +80001b64: 02012703 lw a4,32(sp) +80001b68: 03812683 lw a3,56(sp) +80001b6c: 00100793 li a5,1 +80001b70: 00d70cb3 add s9,a4,a3 +80001b74: 00e7c463 blt a5,a4,80001b7c <_vfprintf_r+0x764> +80001b78: 2940206f j 80003e0c <_vfprintf_r+0x29f4> +80001b7c: 02c12783 lw a5,44(sp) +80001b80: 00fc8cb3 add s9,s9,a5 +80001b84: 02812783 lw a5,40(sp) +80001b88: fffcca93 not s5,s9 +80001b8c: 41fada93 srai s5,s5,0x1f +80001b90: bff7fa13 andi s4,a5,-1025 +80001b94: 100a6a13 ori s4,s4,256 +80001b98: 015cfab3 and s5,s9,s5 +80001b9c: 02012423 sw zero,40(sp) +80001ba0: 02012223 sw zero,36(sp) +80001ba4: 00012e23 sw zero,28(sp) +80001ba8: 05812783 lw a5,88(sp) +80001bac: 00079463 bnez a5,80001bb4 <_vfprintf_r+0x79c> +80001bb0: 3790106f j 80003728 <_vfprintf_r+0x2310> +80001bb4: 02d00793 li a5,45 +80001bb8: 0cf103a3 sb a5,199(sp) +80001bbc: 00000d93 li s11,0 +80001bc0: 001a8a93 addi s5,s5,1 +80001bc4: a8dff06f j 80001650 <_vfprintf_r+0x238> +80001bc8: 0e410613 addi a2,sp,228 +80001bcc: 000c0593 mv a1,s8 +80001bd0: 000d0513 mv a0,s10 +80001bd4: 1c50a0ef jal ra,8000c598 <__sprint_r> +80001bd8: 060518e3 bnez a0,80002448 <_vfprintf_r+0x1030> +80001bdc: 0ec12783 lw a5,236(sp) +80001be0: 10c10893 addi a7,sp,268 +80001be4: ac5ff06f j 800016a8 <_vfprintf_r+0x290> +80001be8: 03012683 lw a3,48(sp) +80001bec: 02c12703 lw a4,44(sp) +80001bf0: 00700613 li a2,7 +80001bf4: 00d8a023 sw a3,0(a7) +80001bf8: 0e812683 lw a3,232(sp) +80001bfc: 00f707b3 add a5,a4,a5 +80001c00: 00e8a223 sw a4,4(a7) +80001c04: 00168693 addi a3,a3,1 +80001c08: 0ef12623 sw a5,236(sp) +80001c0c: 0ed12423 sw a3,232(sp) +80001c10: 00888893 addi a7,a7,8 +80001c14: 02d65463 bge a2,a3,80001c3c <_vfprintf_r+0x824> +80001c18: 0e410613 addi a2,sp,228 +80001c1c: 000c0593 mv a1,s8 +80001c20: 000d0513 mv a0,s10 +80001c24: 1750a0ef jal ra,8000c598 <__sprint_r> +80001c28: 020510e3 bnez a0,80002448 <_vfprintf_r+0x1030> +80001c2c: 0cc12583 lw a1,204(sp) +80001c30: 0ec12783 lw a5,236(sp) +80001c34: 0e812683 lw a3,232(sp) +80001c38: 10c10893 addi a7,sp,268 +80001c3c: 0005d463 bgez a1,80001c44 <_vfprintf_r+0x82c> +80001c40: 5850106f j 800039c4 <_vfprintf_r+0x25ac> +80001c44: 02012703 lw a4,32(sp) +80001c48: 00168693 addi a3,a3,1 +80001c4c: 0168a023 sw s6,0(a7) +80001c50: 00f707b3 add a5,a4,a5 +80001c54: 00e8a223 sw a4,4(a7) +80001c58: 0ef12623 sw a5,236(sp) +80001c5c: 0ed12423 sw a3,232(sp) +80001c60: 00700713 li a4,7 +80001c64: aad75ce3 bge a4,a3,8000171c <_vfprintf_r+0x304> +80001c68: 0e410613 addi a2,sp,228 +80001c6c: 000c0593 mv a1,s8 +80001c70: 000d0513 mv a0,s10 +80001c74: 1250a0ef jal ra,8000c598 <__sprint_r> +80001c78: 7c051863 bnez a0,80002448 <_vfprintf_r+0x1030> +80001c7c: 0ec12783 lw a5,236(sp) +80001c80: 10c10893 addi a7,sp,268 +80001c84: a9dff06f j 80001720 <_vfprintf_r+0x308> +80001c88: 01000693 li a3,16 +80001c8c: 0e812703 lw a4,232(sp) +80001c90: 0096c463 blt a3,s1,80001c98 <_vfprintf_r+0x880> +80001c94: 5190106f j 800039ac <_vfprintf_r+0x2594> +80001c98: 800156b7 lui a3,0x80015 +80001c9c: e1868e93 addi t4,a3,-488 # 80014e18 <__BSS_END__+0xffffe1dc> +80001ca0: 01000913 li s2,16 +80001ca4: 00700a13 li s4,7 +80001ca8: 000e8b13 mv s6,t4 +80001cac: 00c0006f j 80001cb8 <_vfprintf_r+0x8a0> +80001cb0: ff048493 addi s1,s1,-16 +80001cb4: 04995663 bge s2,s1,80001d00 <_vfprintf_r+0x8e8> +80001cb8: 01078793 addi a5,a5,16 +80001cbc: 00170713 addi a4,a4,1 +80001cc0: 0168a023 sw s6,0(a7) +80001cc4: 0128a223 sw s2,4(a7) +80001cc8: 0ef12623 sw a5,236(sp) +80001ccc: 0ee12423 sw a4,232(sp) +80001cd0: 00888893 addi a7,a7,8 +80001cd4: fcea5ee3 bge s4,a4,80001cb0 <_vfprintf_r+0x898> +80001cd8: 0e410613 addi a2,sp,228 +80001cdc: 000c0593 mv a1,s8 +80001ce0: 000d0513 mv a0,s10 +80001ce4: 0b50a0ef jal ra,8000c598 <__sprint_r> +80001ce8: 76051063 bnez a0,80002448 <_vfprintf_r+0x1030> +80001cec: ff048493 addi s1,s1,-16 +80001cf0: 0ec12783 lw a5,236(sp) +80001cf4: 0e812703 lw a4,232(sp) +80001cf8: 10c10893 addi a7,sp,268 +80001cfc: fa994ee3 blt s2,s1,80001cb8 <_vfprintf_r+0x8a0> +80001d00: 000b0e93 mv t4,s6 +80001d04: 009787b3 add a5,a5,s1 +80001d08: 00170713 addi a4,a4,1 +80001d0c: 01d8a023 sw t4,0(a7) +80001d10: 0098a223 sw s1,4(a7) +80001d14: 0ef12623 sw a5,236(sp) +80001d18: 0ee12423 sw a4,232(sp) +80001d1c: 00700693 li a3,7 +80001d20: a0e6d8e3 bge a3,a4,80001730 <_vfprintf_r+0x318> +80001d24: 0e410613 addi a2,sp,228 +80001d28: 000c0593 mv a1,s8 +80001d2c: 000d0513 mv a0,s10 +80001d30: 0690a0ef jal ra,8000c598 <__sprint_r> +80001d34: 70051a63 bnez a0,80002448 <_vfprintf_r+0x1030> +80001d38: 0ec12783 lw a5,236(sp) +80001d3c: 9f5ff06f j 80001730 <_vfprintf_r+0x318> +80001d40: 000d0513 mv a0,s10 +80001d44: 2c5020ef jal ra,80004808 <__sinit> +80001d48: f4cff06f j 80001494 <_vfprintf_r+0x7c> +80001d4c: 01412703 lw a4,20(sp) +80001d50: 000c8893 mv a7,s9 +80001d54: 0c0103a3 sb zero,199(sp) +80001d58: 00072783 lw a5,0(a4) +80001d5c: 00470713 addi a4,a4,4 +80001d60: 00e12a23 sw a4,20(sp) +80001d64: 14f10623 sb a5,332(sp) +80001d68: 00100a93 li s5,1 +80001d6c: 00100c93 li s9,1 +80001d70: 14c10b13 addi s6,sp,332 +80001d74: 8c9ff06f j 8000163c <_vfprintf_r+0x224> +80001d78: 01412783 lw a5,20(sp) +80001d7c: 0c0103a3 sb zero,199(sp) +80001d80: 000c8893 mv a7,s9 +80001d84: 0007ab03 lw s6,0(a5) +80001d88: 00478913 addi s2,a5,4 +80001d8c: 5a0b0ee3 beqz s6,80002b48 <_vfprintf_r+0x1730> +80001d90: fff00793 li a5,-1 +80001d94: 00fd9463 bne s11,a5,80001d9c <_vfprintf_r+0x984> +80001d98: 1000106f j 80002e98 <_vfprintf_r+0x1a80> +80001d9c: 000d8613 mv a2,s11 +80001da0: 00000593 li a1,0 +80001da4: 000b0513 mv a0,s6 +80001da8: 01912a23 sw s9,20(sp) +80001dac: 594060ef jal ra,80008340 +80001db0: 00a12823 sw a0,16(sp) +80001db4: 01412883 lw a7,20(sp) +80001db8: 00051463 bnez a0,80001dc0 <_vfprintf_r+0x9a8> +80001dbc: 31d0106f j 800038d8 <_vfprintf_r+0x24c0> +80001dc0: 01012783 lw a5,16(sp) +80001dc4: 01212a23 sw s2,20(sp) +80001dc8: 00012823 sw zero,16(sp) +80001dcc: 41678cb3 sub s9,a5,s6 +80001dd0: 0c714783 lbu a5,199(sp) +80001dd4: fffcca93 not s5,s9 +80001dd8: 41fada93 srai s5,s5,0x1f +80001ddc: 02012423 sw zero,40(sp) +80001de0: 02012223 sw zero,36(sp) +80001de4: 00012e23 sw zero,28(sp) +80001de8: 015cfab3 and s5,s9,s5 +80001dec: 00000d93 li s11,0 +80001df0: 860780e3 beqz a5,80001650 <_vfprintf_r+0x238> +80001df4: 001a8a93 addi s5,s5,1 +80001df8: 859ff06f j 80001650 <_vfprintf_r+0x238> +80001dfc: 00044483 lbu s1,0(s0) +80001e00: 004a6a13 ori s4,s4,4 +80001e04: fccff06f j 800015d0 <_vfprintf_r+0x1b8> +80001e08: 01412683 lw a3,20(sp) +80001e0c: 020a7793 andi a5,s4,32 +80001e10: 000c8893 mv a7,s9 +80001e14: 0006a703 lw a4,0(a3) +80001e18: 00468693 addi a3,a3,4 +80001e1c: 00d12a23 sw a3,20(sp) +80001e20: 36079ee3 bnez a5,8000299c <_vfprintf_r+0x1584> +80001e24: 010a7793 andi a5,s4,16 +80001e28: 00078463 beqz a5,80001e30 <_vfprintf_r+0xa18> +80001e2c: 05c0106f j 80002e88 <_vfprintf_r+0x1a70> +80001e30: 040a7793 andi a5,s4,64 +80001e34: 00078463 beqz a5,80001e3c <_vfprintf_r+0xa24> +80001e38: 3fc0106f j 80003234 <_vfprintf_r+0x1e1c> +80001e3c: 200a7a13 andi s4,s4,512 +80001e40: 000a1463 bnez s4,80001e48 <_vfprintf_r+0xa30> +80001e44: 0440106f j 80002e88 <_vfprintf_r+0x1a70> +80001e48: 00c12783 lw a5,12(sp) +80001e4c: 00040b13 mv s6,s0 +80001e50: 00f70023 sb a5,0(a4) +80001e54: 915ff06f j 80001768 <_vfprintf_r+0x350> +80001e58: 00044483 lbu s1,0(s0) +80001e5c: 06c00793 li a5,108 +80001e60: 4cf484e3 beq s1,a5,80002b28 <_vfprintf_r+0x1710> +80001e64: 010a6a13 ori s4,s4,16 +80001e68: f68ff06f j 800015d0 <_vfprintf_r+0x1b8> +80001e6c: 01412703 lw a4,20(sp) +80001e70: ffff87b7 lui a5,0xffff8 +80001e74: 8307c793 xori a5,a5,-2000 +80001e78: 0cf11423 sh a5,200(sp) +80001e7c: 00470793 addi a5,a4,4 +80001e80: 00f12a23 sw a5,20(sp) +80001e84: 00072903 lw s2,0(a4) +80001e88: 800157b7 lui a5,0x80015 +80001e8c: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +80001e90: 000c8893 mv a7,s9 +80001e94: 02f12a23 sw a5,52(sp) +80001e98: 00000c93 li s9,0 +80001e9c: 002a6b93 ori s7,s4,2 +80001ea0: 00200793 li a5,2 +80001ea4: 07800493 li s1,120 +80001ea8: 0c0103a3 sb zero,199(sp) +80001eac: fff00713 li a4,-1 +80001eb0: 20ed8663 beq s11,a4,800020bc <_vfprintf_r+0xca4> +80001eb4: 01996733 or a4,s2,s9 +80001eb8: f7fbfa13 andi s4,s7,-129 +80001ebc: 1e071e63 bnez a4,800020b8 <_vfprintf_r+0xca0> +80001ec0: 260d9463 bnez s11,80002128 <_vfprintf_r+0xd10> +80001ec4: 1c079063 bnez a5,80002084 <_vfprintf_r+0xc6c> +80001ec8: 001bfc93 andi s9,s7,1 +80001ecc: 1b010b13 addi s6,sp,432 +80001ed0: 280c9ce3 bnez s9,80002968 <_vfprintf_r+0x1550> +80001ed4: 000c8a93 mv s5,s9 +80001ed8: 01bcd463 bge s9,s11,80001ee0 <_vfprintf_r+0xac8> +80001edc: 000d8a93 mv s5,s11 +80001ee0: 0c714783 lbu a5,199(sp) +80001ee4: 00012823 sw zero,16(sp) +80001ee8: 02012423 sw zero,40(sp) +80001eec: 02012223 sw zero,36(sp) +80001ef0: 00012e23 sw zero,28(sp) +80001ef4: f00790e3 bnez a5,80001df4 <_vfprintf_r+0x9dc> +80001ef8: f58ff06f j 80001650 <_vfprintf_r+0x238> +80001efc: 00044483 lbu s1,0(s0) +80001f00: 06800793 li a5,104 +80001f04: 42f48ae3 beq s1,a5,80002b38 <_vfprintf_r+0x1720> +80001f08: 040a6a13 ori s4,s4,64 +80001f0c: ec4ff06f j 800015d0 <_vfprintf_r+0x1b8> +80001f10: 02b00793 li a5,43 +80001f14: 00044483 lbu s1,0(s0) +80001f18: 0cf103a3 sb a5,199(sp) +80001f1c: eb4ff06f j 800015d0 <_vfprintf_r+0x1b8> +80001f20: 00044483 lbu s1,0(s0) +80001f24: 080a6a13 ori s4,s4,128 +80001f28: ea8ff06f j 800015d0 <_vfprintf_r+0x1b8> +80001f2c: 00044483 lbu s1,0(s0) +80001f30: 00140713 addi a4,s0,1 +80001f34: 01749463 bne s1,s7,80001f3c <_vfprintf_r+0xb24> +80001f38: 7250106f j 80003e5c <_vfprintf_r+0x2a44> +80001f3c: fd048693 addi a3,s1,-48 +80001f40: 00070413 mv s0,a4 +80001f44: 00000d93 li s11,0 +80001f48: e8dae663 bltu s5,a3,800015d4 <_vfprintf_r+0x1bc> +80001f4c: 00044483 lbu s1,0(s0) +80001f50: 002d9793 slli a5,s11,0x2 +80001f54: 01b787b3 add a5,a5,s11 +80001f58: 00179793 slli a5,a5,0x1 +80001f5c: 00d78db3 add s11,a5,a3 +80001f60: fd048693 addi a3,s1,-48 +80001f64: 00140413 addi s0,s0,1 +80001f68: fedaf2e3 bgeu s5,a3,80001f4c <_vfprintf_r+0xb34> +80001f6c: e68ff06f j 800015d4 <_vfprintf_r+0x1bc> +80001f70: 01412783 lw a5,20(sp) +80001f74: 00044483 lbu s1,0(s0) +80001f78: 0007a983 lw s3,0(a5) +80001f7c: 00478793 addi a5,a5,4 +80001f80: 00f12a23 sw a5,20(sp) +80001f84: e409d663 bgez s3,800015d0 <_vfprintf_r+0x1b8> +80001f88: 413009b3 neg s3,s3 +80001f8c: 004a6a13 ori s4,s4,4 +80001f90: e40ff06f j 800015d0 <_vfprintf_r+0x1b8> +80001f94: 00044483 lbu s1,0(s0) +80001f98: 001a6a13 ori s4,s4,1 +80001f9c: e34ff06f j 800015d0 <_vfprintf_r+0x1b8> +80001fa0: 0c714783 lbu a5,199(sp) +80001fa4: 00044483 lbu s1,0(s0) +80001fa8: e2079463 bnez a5,800015d0 <_vfprintf_r+0x1b8> +80001fac: 02000793 li a5,32 +80001fb0: 0cf103a3 sb a5,199(sp) +80001fb4: e1cff06f j 800015d0 <_vfprintf_r+0x1b8> +80001fb8: 000c8893 mv a7,s9 +80001fbc: 010a6a13 ori s4,s4,16 +80001fc0: 020a7793 andi a5,s4,32 +80001fc4: 0c078ee3 beqz a5,800028a0 <_vfprintf_r+0x1488> +80001fc8: 01412783 lw a5,20(sp) +80001fcc: 00778b13 addi s6,a5,7 +80001fd0: ff8b7b13 andi s6,s6,-8 +80001fd4: 000b2903 lw s2,0(s6) +80001fd8: 004b2c83 lw s9,4(s6) +80001fdc: 008b0793 addi a5,s6,8 +80001fe0: 00f12a23 sw a5,20(sp) +80001fe4: bffa7b93 andi s7,s4,-1025 +80001fe8: 00000793 li a5,0 +80001fec: ebdff06f j 80001ea8 <_vfprintf_r+0xa90> +80001ff0: 000c8893 mv a7,s9 +80001ff4: 010a6b93 ori s7,s4,16 +80001ff8: 020bf793 andi a5,s7,32 +80001ffc: 0c0788e3 beqz a5,800028cc <_vfprintf_r+0x14b4> +80002000: 01412783 lw a5,20(sp) +80002004: 00778b13 addi s6,a5,7 +80002008: ff8b7b13 andi s6,s6,-8 +8000200c: 008b0793 addi a5,s6,8 +80002010: 00f12a23 sw a5,20(sp) +80002014: 000b2903 lw s2,0(s6) +80002018: 004b2c83 lw s9,4(s6) +8000201c: 00100793 li a5,1 +80002020: e89ff06f j 80001ea8 <_vfprintf_r+0xa90> +80002024: 00044483 lbu s1,0(s0) +80002028: 008a6a13 ori s4,s4,8 +8000202c: da4ff06f j 800015d0 <_vfprintf_r+0x1b8> +80002030: 000c8893 mv a7,s9 +80002034: 010a6a13 ori s4,s4,16 +80002038: 020a7793 andi a5,s4,32 +8000203c: 0c0780e3 beqz a5,800028fc <_vfprintf_r+0x14e4> +80002040: 01412783 lw a5,20(sp) +80002044: 00778b13 addi s6,a5,7 +80002048: ff8b7b13 andi s6,s6,-8 +8000204c: 004b2783 lw a5,4(s6) +80002050: 000b2903 lw s2,0(s6) +80002054: 008b0713 addi a4,s6,8 +80002058: 00e12a23 sw a4,20(sp) +8000205c: 00078c93 mv s9,a5 +80002060: 0c07c6e3 bltz a5,8000292c <_vfprintf_r+0x1514> +80002064: fff00793 li a5,-1 +80002068: 000a0b93 mv s7,s4 +8000206c: 02fd8463 beq s11,a5,80002094 <_vfprintf_r+0xc7c> +80002070: 019967b3 or a5,s2,s9 +80002074: f7fa7b93 andi s7,s4,-129 +80002078: 00079e63 bnez a5,80002094 <_vfprintf_r+0xc7c> +8000207c: 020d9263 bnez s11,800020a0 <_vfprintf_r+0xc88> +80002080: 000b8a13 mv s4,s7 +80002084: 00000d93 li s11,0 +80002088: 00000c93 li s9,0 +8000208c: 1b010b13 addi s6,sp,432 +80002090: e45ff06f j 80001ed4 <_vfprintf_r+0xabc> +80002094: 3a0c92e3 bnez s9,80002c38 <_vfprintf_r+0x1820> +80002098: 00900793 li a5,9 +8000209c: 3927eee3 bltu a5,s2,80002c38 <_vfprintf_r+0x1820> +800020a0: 03090913 addi s2,s2,48 +800020a4: 1b2107a3 sb s2,431(sp) +800020a8: 000b8a13 mv s4,s7 +800020ac: 00100c93 li s9,1 +800020b0: 1af10b13 addi s6,sp,431 +800020b4: e21ff06f j 80001ed4 <_vfprintf_r+0xabc> +800020b8: 000a0b93 mv s7,s4 +800020bc: 00100713 li a4,1 +800020c0: fce78ae3 beq a5,a4,80002094 <_vfprintf_r+0xc7c> +800020c4: 00200713 li a4,2 +800020c8: 06e78c63 beq a5,a4,80002140 <_vfprintf_r+0xd28> +800020cc: 1b010b13 addi s6,sp,432 +800020d0: 01dc9713 slli a4,s9,0x1d +800020d4: 00797793 andi a5,s2,7 +800020d8: 00395913 srli s2,s2,0x3 +800020dc: 03078793 addi a5,a5,48 +800020e0: 01276933 or s2,a4,s2 +800020e4: 003cdc93 srli s9,s9,0x3 +800020e8: fefb0fa3 sb a5,-1(s6) +800020ec: 01996733 or a4,s2,s9 +800020f0: 000b0613 mv a2,s6 +800020f4: fffb0b13 addi s6,s6,-1 +800020f8: fc071ce3 bnez a4,800020d0 <_vfprintf_r+0xcb8> +800020fc: 001bf693 andi a3,s7,1 +80002100: 06068a63 beqz a3,80002174 <_vfprintf_r+0xd5c> +80002104: 03000693 li a3,48 +80002108: 06d78663 beq a5,a3,80002174 <_vfprintf_r+0xd5c> +8000210c: ffe60613 addi a2,a2,-2 +80002110: 1b010793 addi a5,sp,432 +80002114: fedb0fa3 sb a3,-1(s6) +80002118: 40c78cb3 sub s9,a5,a2 +8000211c: 000b8a13 mv s4,s7 +80002120: 00060b13 mv s6,a2 +80002124: db1ff06f j 80001ed4 <_vfprintf_r+0xabc> +80002128: 00100713 li a4,1 +8000212c: 00e79463 bne a5,a4,80002134 <_vfprintf_r+0xd1c> +80002130: 14d0106f j 80003a7c <_vfprintf_r+0x2664> +80002134: 00200713 li a4,2 +80002138: 000a0b93 mv s7,s4 +8000213c: f8e798e3 bne a5,a4,800020cc <_vfprintf_r+0xcb4> +80002140: 03412683 lw a3,52(sp) +80002144: 1b010b13 addi s6,sp,432 +80002148: 00f97793 andi a5,s2,15 +8000214c: 00f687b3 add a5,a3,a5 +80002150: 0007c703 lbu a4,0(a5) +80002154: 00495913 srli s2,s2,0x4 +80002158: 01cc9793 slli a5,s9,0x1c +8000215c: 0127e933 or s2,a5,s2 +80002160: 004cdc93 srli s9,s9,0x4 +80002164: feeb0fa3 sb a4,-1(s6) +80002168: 019967b3 or a5,s2,s9 +8000216c: fffb0b13 addi s6,s6,-1 +80002170: fc079ce3 bnez a5,80002148 <_vfprintf_r+0xd30> +80002174: 1b010793 addi a5,sp,432 +80002178: 41678cb3 sub s9,a5,s6 +8000217c: 000b8a13 mv s4,s7 +80002180: d55ff06f j 80001ed4 <_vfprintf_r+0xabc> +80002184: 06500693 li a3,101 +80002188: 2c96dc63 bge a3,s1,80002460 <_vfprintf_r+0x1048> +8000218c: 0f012683 lw a3,240(sp) +80002190: 0a010593 addi a1,sp,160 +80002194: 0b010513 addi a0,sp,176 +80002198: 0ad12823 sw a3,176(sp) +8000219c: 0f412683 lw a3,244(sp) +800021a0: 05112223 sw a7,68(sp) +800021a4: 04f12023 sw a5,64(sp) +800021a8: 0ad12a23 sw a3,180(sp) +800021ac: 0f812683 lw a3,248(sp) +800021b0: 0a012023 sw zero,160(sp) +800021b4: 0a012223 sw zero,164(sp) +800021b8: 0ad12c23 sw a3,184(sp) +800021bc: 0fc12683 lw a3,252(sp) +800021c0: 0a012423 sw zero,168(sp) +800021c4: 0a012623 sw zero,172(sp) +800021c8: 0ad12e23 sw a3,188(sp) +800021cc: 7e00f0ef jal ra,800119ac <__eqtf2> +800021d0: 04012783 lw a5,64(sp) +800021d4: 04412883 lw a7,68(sp) +800021d8: 4a051863 bnez a0,80002688 <_vfprintf_r+0x1270> +800021dc: 0e812703 lw a4,232(sp) +800021e0: 800156b7 lui a3,0x80015 +800021e4: ca868693 addi a3,a3,-856 # 80014ca8 <__BSS_END__+0xffffe06c> +800021e8: 00d8a023 sw a3,0(a7) +800021ec: 00178793 addi a5,a5,1 +800021f0: 00100693 li a3,1 +800021f4: 00170713 addi a4,a4,1 +800021f8: 00d8a223 sw a3,4(a7) +800021fc: 0ef12623 sw a5,236(sp) +80002200: 0ee12423 sw a4,232(sp) +80002204: 00700693 li a3,7 +80002208: 00888893 addi a7,a7,8 +8000220c: 3ae6c6e3 blt a3,a4,80002db8 <_vfprintf_r+0x19a0> +80002210: 0cc12703 lw a4,204(sp) +80002214: 02012683 lw a3,32(sp) +80002218: 72d75c63 bge a4,a3,80002950 <_vfprintf_r+0x1538> +8000221c: 03012703 lw a4,48(sp) +80002220: 02c12683 lw a3,44(sp) +80002224: 00888893 addi a7,a7,8 +80002228: fee8ac23 sw a4,-8(a7) +8000222c: 0e812703 lw a4,232(sp) +80002230: 00d787b3 add a5,a5,a3 +80002234: fed8ae23 sw a3,-4(a7) +80002238: 00170713 addi a4,a4,1 +8000223c: 0ef12623 sw a5,236(sp) +80002240: 0ee12423 sw a4,232(sp) +80002244: 00700693 li a3,7 +80002248: 0ce6c0e3 blt a3,a4,80002b08 <_vfprintf_r+0x16f0> +8000224c: 02012703 lw a4,32(sp) +80002250: fff70493 addi s1,a4,-1 +80002254: cc905663 blez s1,80001720 <_vfprintf_r+0x308> +80002258: 01000693 li a3,16 +8000225c: 0e812703 lw a4,232(sp) +80002260: 3696dce3 bge a3,s1,80002dd8 <_vfprintf_r+0x19c0> +80002264: 01000913 li s2,16 +80002268: 00700c93 li s9,7 +8000226c: 00c0006f j 80002278 <_vfprintf_r+0xe60> +80002270: ff048493 addi s1,s1,-16 +80002274: 369952e3 bge s2,s1,80002dd8 <_vfprintf_r+0x19c0> +80002278: 00812683 lw a3,8(sp) +8000227c: 01078793 addi a5,a5,16 +80002280: 00170713 addi a4,a4,1 +80002284: 00d8a023 sw a3,0(a7) +80002288: 0128a223 sw s2,4(a7) +8000228c: 0ef12623 sw a5,236(sp) +80002290: 0ee12423 sw a4,232(sp) +80002294: 00888893 addi a7,a7,8 +80002298: fcecdce3 bge s9,a4,80002270 <_vfprintf_r+0xe58> +8000229c: 0e410613 addi a2,sp,228 +800022a0: 000c0593 mv a1,s8 +800022a4: 000d0513 mv a0,s10 +800022a8: 2f00a0ef jal ra,8000c598 <__sprint_r> +800022ac: 18051e63 bnez a0,80002448 <_vfprintf_r+0x1030> +800022b0: 0ec12783 lw a5,236(sp) 800022b4: 0e812703 lw a4,232(sp) -800022b8: 00d787b3 add a5,a5,a3 -800022bc: fed8ae23 sw a3,-4(a7) -800022c0: 00170713 addi a4,a4,1 -800022c4: 0ef12623 sw a5,236(sp) -800022c8: 0ee12423 sw a4,232(sp) -800022cc: 00700693 li a3,7 -800022d0: 0ce6c0e3 blt a3,a4,80002b90 <_vfprintf_r+0x16f0> -800022d4: 02012703 lw a4,32(sp) -800022d8: fff70493 addi s1,a4,-1 -800022dc: cc905663 blez s1,800017a8 <_vfprintf_r+0x308> -800022e0: 01000693 li a3,16 -800022e4: 0e812703 lw a4,232(sp) -800022e8: 3696dce3 bge a3,s1,80002e60 <_vfprintf_r+0x19c0> -800022ec: 01000913 li s2,16 -800022f0: 00700c93 li s9,7 -800022f4: 00c0006f j 80002300 <_vfprintf_r+0xe60> -800022f8: ff048493 addi s1,s1,-16 -800022fc: 369952e3 bge s2,s1,80002e60 <_vfprintf_r+0x19c0> -80002300: 00812683 lw a3,8(sp) -80002304: 01078793 addi a5,a5,16 -80002308: 00170713 addi a4,a4,1 -8000230c: 00d8a023 sw a3,0(a7) -80002310: 0128a223 sw s2,4(a7) -80002314: 0ef12623 sw a5,236(sp) -80002318: 0ee12423 sw a4,232(sp) -8000231c: 00888893 addi a7,a7,8 -80002320: fcecdce3 bge s9,a4,800022f8 <_vfprintf_r+0xe58> -80002324: 0e410613 addi a2,sp,228 -80002328: 000c0593 mv a1,s8 -8000232c: 000d0513 mv a0,s10 -80002330: 4c00a0ef jal ra,8000c7f0 <__sprint_r> -80002334: 18051e63 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002338: 0ec12783 lw a5,236(sp) -8000233c: 0e812703 lw a4,232(sp) -80002340: 10c10893 addi a7,sp,268 -80002344: fb5ff06f j 800022f8 <_vfprintf_r+0xe58> -80002348: 41598933 sub s2,s3,s5 -8000234c: c3205263 blez s2,80001770 <_vfprintf_r+0x2d0> -80002350: 01000613 li a2,16 -80002354: 0e812683 lw a3,232(sp) -80002358: 07265463 bge a2,s2,800023c0 <_vfprintf_r+0xf20> -8000235c: 01000e13 li t3,16 -80002360: 00700b93 li s7,7 -80002364: 00c0006f j 80002370 <_vfprintf_r+0xed0> -80002368: ff090913 addi s2,s2,-16 -8000236c: 052e5a63 bge t3,s2,800023c0 <_vfprintf_r+0xf20> -80002370: 00812703 lw a4,8(sp) -80002374: 01078793 addi a5,a5,16 -80002378: 00168693 addi a3,a3,1 -8000237c: 00e8a023 sw a4,0(a7) -80002380: 01c8a223 sw t3,4(a7) -80002384: 0ef12623 sw a5,236(sp) -80002388: 0ed12423 sw a3,232(sp) -8000238c: 00888893 addi a7,a7,8 -80002390: fcdbdce3 bge s7,a3,80002368 <_vfprintf_r+0xec8> -80002394: 0e410613 addi a2,sp,228 -80002398: 000c0593 mv a1,s8 -8000239c: 000d0513 mv a0,s10 -800023a0: 4500a0ef jal ra,8000c7f0 <__sprint_r> -800023a4: 12051663 bnez a0,800024d0 <_vfprintf_r+0x1030> -800023a8: 01000e13 li t3,16 -800023ac: ff090913 addi s2,s2,-16 -800023b0: 0ec12783 lw a5,236(sp) -800023b4: 0e812683 lw a3,232(sp) -800023b8: 10c10893 addi a7,sp,268 -800023bc: fb2e4ae3 blt t3,s2,80002370 <_vfprintf_r+0xed0> -800023c0: 00812703 lw a4,8(sp) -800023c4: 012787b3 add a5,a5,s2 -800023c8: 00168693 addi a3,a3,1 -800023cc: 00e8a023 sw a4,0(a7) -800023d0: 0128a223 sw s2,4(a7) -800023d4: 0ef12623 sw a5,236(sp) -800023d8: 0ed12423 sw a3,232(sp) -800023dc: 00700613 li a2,7 -800023e0: 00888893 addi a7,a7,8 -800023e4: b8d65663 bge a2,a3,80001770 <_vfprintf_r+0x2d0> -800023e8: 0e410613 addi a2,sp,228 -800023ec: 000c0593 mv a1,s8 -800023f0: 000d0513 mv a0,s10 -800023f4: 3fc0a0ef jal ra,8000c7f0 <__sprint_r> -800023f8: 0c051c63 bnez a0,800024d0 <_vfprintf_r+0x1030> -800023fc: 0ec12783 lw a5,236(sp) -80002400: 10c10893 addi a7,sp,268 -80002404: b6cff06f j 80001770 <_vfprintf_r+0x2d0> -80002408: 01000613 li a2,16 -8000240c: 0e812683 lw a3,232(sp) -80002410: 07b65263 bge a2,s11,80002474 <_vfprintf_r+0xfd4> -80002414: 01000b93 li s7,16 -80002418: 00700913 li s2,7 -8000241c: 00c0006f j 80002428 <_vfprintf_r+0xf88> -80002420: ff0d8d93 addi s11,s11,-16 -80002424: 05bbd863 bge s7,s11,80002474 <_vfprintf_r+0xfd4> -80002428: 00812703 lw a4,8(sp) -8000242c: 01078793 addi a5,a5,16 -80002430: 00168693 addi a3,a3,1 -80002434: 00e8a023 sw a4,0(a7) -80002438: 0178a223 sw s7,4(a7) -8000243c: 0ef12623 sw a5,236(sp) -80002440: 0ed12423 sw a3,232(sp) -80002444: 00888893 addi a7,a7,8 -80002448: fcd95ce3 bge s2,a3,80002420 <_vfprintf_r+0xf80> -8000244c: 0e410613 addi a2,sp,228 -80002450: 000c0593 mv a1,s8 +800022b8: 10c10893 addi a7,sp,268 +800022bc: fb5ff06f j 80002270 <_vfprintf_r+0xe58> +800022c0: 41598933 sub s2,s3,s5 +800022c4: c3205263 blez s2,800016e8 <_vfprintf_r+0x2d0> +800022c8: 01000613 li a2,16 +800022cc: 0e812683 lw a3,232(sp) +800022d0: 07265463 bge a2,s2,80002338 <_vfprintf_r+0xf20> +800022d4: 01000e13 li t3,16 +800022d8: 00700b93 li s7,7 +800022dc: 00c0006f j 800022e8 <_vfprintf_r+0xed0> +800022e0: ff090913 addi s2,s2,-16 +800022e4: 052e5a63 bge t3,s2,80002338 <_vfprintf_r+0xf20> +800022e8: 00812703 lw a4,8(sp) +800022ec: 01078793 addi a5,a5,16 +800022f0: 00168693 addi a3,a3,1 +800022f4: 00e8a023 sw a4,0(a7) +800022f8: 01c8a223 sw t3,4(a7) +800022fc: 0ef12623 sw a5,236(sp) +80002300: 0ed12423 sw a3,232(sp) +80002304: 00888893 addi a7,a7,8 +80002308: fcdbdce3 bge s7,a3,800022e0 <_vfprintf_r+0xec8> +8000230c: 0e410613 addi a2,sp,228 +80002310: 000c0593 mv a1,s8 +80002314: 000d0513 mv a0,s10 +80002318: 2800a0ef jal ra,8000c598 <__sprint_r> +8000231c: 12051663 bnez a0,80002448 <_vfprintf_r+0x1030> +80002320: 01000e13 li t3,16 +80002324: ff090913 addi s2,s2,-16 +80002328: 0ec12783 lw a5,236(sp) +8000232c: 0e812683 lw a3,232(sp) +80002330: 10c10893 addi a7,sp,268 +80002334: fb2e4ae3 blt t3,s2,800022e8 <_vfprintf_r+0xed0> +80002338: 00812703 lw a4,8(sp) +8000233c: 012787b3 add a5,a5,s2 +80002340: 00168693 addi a3,a3,1 +80002344: 00e8a023 sw a4,0(a7) +80002348: 0128a223 sw s2,4(a7) +8000234c: 0ef12623 sw a5,236(sp) +80002350: 0ed12423 sw a3,232(sp) +80002354: 00700613 li a2,7 +80002358: 00888893 addi a7,a7,8 +8000235c: b8d65663 bge a2,a3,800016e8 <_vfprintf_r+0x2d0> +80002360: 0e410613 addi a2,sp,228 +80002364: 000c0593 mv a1,s8 +80002368: 000d0513 mv a0,s10 +8000236c: 22c0a0ef jal ra,8000c598 <__sprint_r> +80002370: 0c051c63 bnez a0,80002448 <_vfprintf_r+0x1030> +80002374: 0ec12783 lw a5,236(sp) +80002378: 10c10893 addi a7,sp,268 +8000237c: b6cff06f j 800016e8 <_vfprintf_r+0x2d0> +80002380: 01000613 li a2,16 +80002384: 0e812683 lw a3,232(sp) +80002388: 07b65263 bge a2,s11,800023ec <_vfprintf_r+0xfd4> +8000238c: 01000b93 li s7,16 +80002390: 00700913 li s2,7 +80002394: 00c0006f j 800023a0 <_vfprintf_r+0xf88> +80002398: ff0d8d93 addi s11,s11,-16 +8000239c: 05bbd863 bge s7,s11,800023ec <_vfprintf_r+0xfd4> +800023a0: 00812703 lw a4,8(sp) +800023a4: 01078793 addi a5,a5,16 +800023a8: 00168693 addi a3,a3,1 +800023ac: 00e8a023 sw a4,0(a7) +800023b0: 0178a223 sw s7,4(a7) +800023b4: 0ef12623 sw a5,236(sp) +800023b8: 0ed12423 sw a3,232(sp) +800023bc: 00888893 addi a7,a7,8 +800023c0: fcd95ce3 bge s2,a3,80002398 <_vfprintf_r+0xf80> +800023c4: 0e410613 addi a2,sp,228 +800023c8: 000c0593 mv a1,s8 +800023cc: 000d0513 mv a0,s10 +800023d0: 1c80a0ef jal ra,8000c598 <__sprint_r> +800023d4: 06051a63 bnez a0,80002448 <_vfprintf_r+0x1030> +800023d8: ff0d8d93 addi s11,s11,-16 +800023dc: 0ec12783 lw a5,236(sp) +800023e0: 0e812683 lw a3,232(sp) +800023e4: 10c10893 addi a7,sp,268 +800023e8: fbbbcce3 blt s7,s11,800023a0 <_vfprintf_r+0xf88> +800023ec: 00812703 lw a4,8(sp) +800023f0: 01b787b3 add a5,a5,s11 +800023f4: 00168693 addi a3,a3,1 +800023f8: 00e8a023 sw a4,0(a7) +800023fc: 01b8a223 sw s11,4(a7) +80002400: 0ef12623 sw a5,236(sp) +80002404: 0ed12423 sw a3,232(sp) +80002408: 00700613 li a2,7 +8000240c: 00888893 addi a7,a7,8 +80002410: aed65063 bge a2,a3,800016f0 <_vfprintf_r+0x2d8> +80002414: 0e410613 addi a2,sp,228 +80002418: 000c0593 mv a1,s8 +8000241c: 000d0513 mv a0,s10 +80002420: 1780a0ef jal ra,8000c598 <__sprint_r> +80002424: 02051263 bnez a0,80002448 <_vfprintf_r+0x1030> +80002428: 0ec12783 lw a5,236(sp) +8000242c: 10c10893 addi a7,sp,268 +80002430: ac0ff06f j 800016f0 <_vfprintf_r+0x2d8> +80002434: 0e410613 addi a2,sp,228 +80002438: 000c0593 mv a1,s8 +8000243c: 000d0513 mv a0,s10 +80002440: 1580a0ef jal ra,8000c598 <__sprint_r> +80002444: b0050263 beqz a0,80001748 <_vfprintf_r+0x330> +80002448: 01012b83 lw s7,16(sp) +8000244c: b20b8863 beqz s7,8000177c <_vfprintf_r+0x364> +80002450: 000b8593 mv a1,s7 80002454: 000d0513 mv a0,s10 -80002458: 3980a0ef jal ra,8000c7f0 <__sprint_r> -8000245c: 06051a63 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002460: ff0d8d93 addi s11,s11,-16 -80002464: 0ec12783 lw a5,236(sp) -80002468: 0e812683 lw a3,232(sp) -8000246c: 10c10893 addi a7,sp,268 -80002470: fbbbcce3 blt s7,s11,80002428 <_vfprintf_r+0xf88> -80002474: 00812703 lw a4,8(sp) -80002478: 01b787b3 add a5,a5,s11 -8000247c: 00168693 addi a3,a3,1 -80002480: 00e8a023 sw a4,0(a7) -80002484: 01b8a223 sw s11,4(a7) -80002488: 0ef12623 sw a5,236(sp) -8000248c: 0ed12423 sw a3,232(sp) -80002490: 00700613 li a2,7 -80002494: 00888893 addi a7,a7,8 -80002498: aed65063 bge a2,a3,80001778 <_vfprintf_r+0x2d8> -8000249c: 0e410613 addi a2,sp,228 -800024a0: 000c0593 mv a1,s8 -800024a4: 000d0513 mv a0,s10 -800024a8: 3480a0ef jal ra,8000c7f0 <__sprint_r> -800024ac: 02051263 bnez a0,800024d0 <_vfprintf_r+0x1030> -800024b0: 0ec12783 lw a5,236(sp) -800024b4: 10c10893 addi a7,sp,268 -800024b8: ac0ff06f j 80001778 <_vfprintf_r+0x2d8> -800024bc: 0e410613 addi a2,sp,228 -800024c0: 000c0593 mv a1,s8 -800024c4: 000d0513 mv a0,s10 -800024c8: 3280a0ef jal ra,8000c7f0 <__sprint_r> -800024cc: b0050263 beqz a0,800017d0 <_vfprintf_r+0x330> -800024d0: 01012b83 lw s7,16(sp) -800024d4: b20b8863 beqz s7,80001804 <_vfprintf_r+0x364> -800024d8: 000b8593 mv a1,s7 -800024dc: 000d0513 mv a0,s10 -800024e0: 5a4020ef jal ra,80004a84 <_free_r> -800024e4: b20ff06f j 80001804 <_vfprintf_r+0x364> -800024e8: 0e812683 lw a3,232(sp) -800024ec: 00178c93 addi s9,a5,1 -800024f0: 02012783 lw a5,32(sp) -800024f4: 00100613 li a2,1 -800024f8: 0168a023 sw s6,0(a7) -800024fc: 00168493 addi s1,a3,1 -80002500: 00888913 addi s2,a7,8 -80002504: 38f65663 bge a2,a5,80002890 <_vfprintf_r+0x13f0> -80002508: 00100793 li a5,1 -8000250c: 00f8a223 sw a5,4(a7) -80002510: 0f912623 sw s9,236(sp) -80002514: 0e912423 sw s1,232(sp) -80002518: 00700793 li a5,7 -8000251c: 7497ce63 blt a5,s1,80002c78 <_vfprintf_r+0x17d8> -80002520: 02c12783 lw a5,44(sp) -80002524: 03012703 lw a4,48(sp) -80002528: 00148493 addi s1,s1,1 -8000252c: 00fc8cb3 add s9,s9,a5 -80002530: 00f92223 sw a5,4(s2) -80002534: 00e92023 sw a4,0(s2) -80002538: 0f912623 sw s9,236(sp) -8000253c: 0e912423 sw s1,232(sp) -80002540: 00700793 li a5,7 -80002544: 00890913 addi s2,s2,8 -80002548: 7497ca63 blt a5,s1,80002c9c <_vfprintf_r+0x17fc> -8000254c: 0f012783 lw a5,240(sp) -80002550: 00148613 addi a2,s1,1 -80002554: 0a010593 addi a1,sp,160 -80002558: 0af12823 sw a5,176(sp) -8000255c: 0f412783 lw a5,244(sp) -80002560: 0b010513 addi a0,sp,176 -80002564: 00c12e23 sw a2,28(sp) -80002568: 0af12a23 sw a5,180(sp) -8000256c: 0f812783 lw a5,248(sp) -80002570: 0a012023 sw zero,160(sp) -80002574: 0a012223 sw zero,164(sp) -80002578: 0af12c23 sw a5,184(sp) -8000257c: 0fc12783 lw a5,252(sp) -80002580: 0a012423 sw zero,168(sp) -80002584: 0a012623 sw zero,172(sp) -80002588: 0af12e23 sw a5,188(sp) -8000258c: 35c0f0ef jal ra,800118e8 <__eqtf2> -80002590: 01c12603 lw a2,28(sp) -80002594: 02012783 lw a5,32(sp) -80002598: 00890893 addi a7,s2,8 -8000259c: 00060693 mv a3,a2 -800025a0: fff78d93 addi s11,a5,-1 -800025a4: 30050a63 beqz a0,800028b8 <_vfprintf_r+0x1418> -800025a8: 001b0713 addi a4,s6,1 -800025ac: 01bc8cb3 add s9,s9,s11 -800025b0: 00e92023 sw a4,0(s2) -800025b4: 01b92223 sw s11,4(s2) -800025b8: 0f912623 sw s9,236(sp) -800025bc: 0ec12423 sw a2,232(sp) -800025c0: 00700793 li a5,7 -800025c4: 50c7cc63 blt a5,a2,80002adc <_vfprintf_r+0x163c> -800025c8: 01090793 addi a5,s2,16 -800025cc: 00248693 addi a3,s1,2 -800025d0: 00088913 mv s2,a7 -800025d4: 00078893 mv a7,a5 -800025d8: 03812603 lw a2,56(sp) -800025dc: 0d410713 addi a4,sp,212 -800025e0: 00e92023 sw a4,0(s2) -800025e4: 019607b3 add a5,a2,s9 -800025e8: 00c92223 sw a2,4(s2) -800025ec: 0ef12623 sw a5,236(sp) -800025f0: 0ed12423 sw a3,232(sp) -800025f4: 00700713 li a4,7 -800025f8: 9ad75863 bge a4,a3,800017a8 <_vfprintf_r+0x308> -800025fc: ef4ff06f j 80001cf0 <_vfprintf_r+0x850> -80002600: 80015737 lui a4,0x80015 -80002604: 01000613 li a2,16 -80002608: 0e812683 lw a3,232(sp) -8000260c: dcc70e93 addi t4,a4,-564 # 80014dcc <__BSS_END__+0xffffe19c> -80002610: 09065c63 bge a2,a6,800026a8 <_vfprintf_r+0x1208> -80002614: 04812023 sw s0,64(sp) -80002618: 04912223 sw s1,68(sp) -8000261c: 000d0413 mv s0,s10 -80002620: 000c0493 mv s1,s8 -80002624: 01000e13 li t3,16 -80002628: 00700293 li t0,7 -8000262c: 00080c13 mv s8,a6 -80002630: 000e8d13 mv s10,t4 -80002634: 00c0006f j 80002640 <_vfprintf_r+0x11a0> -80002638: ff0c0c13 addi s8,s8,-16 -8000263c: 058e5a63 bge t3,s8,80002690 <_vfprintf_r+0x11f0> -80002640: 01078793 addi a5,a5,16 -80002644: 00168693 addi a3,a3,1 -80002648: 01a8a023 sw s10,0(a7) -8000264c: 01c8a223 sw t3,4(a7) -80002650: 0ef12623 sw a5,236(sp) -80002654: 0ed12423 sw a3,232(sp) -80002658: 00888893 addi a7,a7,8 -8000265c: fcd2dee3 bge t0,a3,80002638 <_vfprintf_r+0x1198> -80002660: 0e410613 addi a2,sp,228 -80002664: 00048593 mv a1,s1 -80002668: 00040513 mv a0,s0 -8000266c: 1840a0ef jal ra,8000c7f0 <__sprint_r> -80002670: 7a051263 bnez a0,80002e14 <_vfprintf_r+0x1974> -80002674: 01000e13 li t3,16 -80002678: ff0c0c13 addi s8,s8,-16 +80002458: 57c020ef jal ra,800049d4 <_free_r> +8000245c: b20ff06f j 8000177c <_vfprintf_r+0x364> +80002460: 0e812683 lw a3,232(sp) +80002464: 00178c93 addi s9,a5,1 +80002468: 02012783 lw a5,32(sp) +8000246c: 00100613 li a2,1 +80002470: 0168a023 sw s6,0(a7) +80002474: 00168493 addi s1,a3,1 +80002478: 00888913 addi s2,a7,8 +8000247c: 38f65663 bge a2,a5,80002808 <_vfprintf_r+0x13f0> +80002480: 00100793 li a5,1 +80002484: 00f8a223 sw a5,4(a7) +80002488: 0f912623 sw s9,236(sp) +8000248c: 0e912423 sw s1,232(sp) +80002490: 00700793 li a5,7 +80002494: 7497ce63 blt a5,s1,80002bf0 <_vfprintf_r+0x17d8> +80002498: 02c12783 lw a5,44(sp) +8000249c: 03012703 lw a4,48(sp) +800024a0: 00148493 addi s1,s1,1 +800024a4: 00fc8cb3 add s9,s9,a5 +800024a8: 00f92223 sw a5,4(s2) +800024ac: 00e92023 sw a4,0(s2) +800024b0: 0f912623 sw s9,236(sp) +800024b4: 0e912423 sw s1,232(sp) +800024b8: 00700793 li a5,7 +800024bc: 00890913 addi s2,s2,8 +800024c0: 7497ca63 blt a5,s1,80002c14 <_vfprintf_r+0x17fc> +800024c4: 0f012783 lw a5,240(sp) +800024c8: 00148613 addi a2,s1,1 +800024cc: 0a010593 addi a1,sp,160 +800024d0: 0af12823 sw a5,176(sp) +800024d4: 0f412783 lw a5,244(sp) +800024d8: 0b010513 addi a0,sp,176 +800024dc: 00c12e23 sw a2,28(sp) +800024e0: 0af12a23 sw a5,180(sp) +800024e4: 0f812783 lw a5,248(sp) +800024e8: 0a012023 sw zero,160(sp) +800024ec: 0a012223 sw zero,164(sp) +800024f0: 0af12c23 sw a5,184(sp) +800024f4: 0fc12783 lw a5,252(sp) +800024f8: 0a012423 sw zero,168(sp) +800024fc: 0a012623 sw zero,172(sp) +80002500: 0af12e23 sw a5,188(sp) +80002504: 4a80f0ef jal ra,800119ac <__eqtf2> +80002508: 01c12603 lw a2,28(sp) +8000250c: 02012783 lw a5,32(sp) +80002510: 00890893 addi a7,s2,8 +80002514: 00060693 mv a3,a2 +80002518: fff78d93 addi s11,a5,-1 +8000251c: 30050a63 beqz a0,80002830 <_vfprintf_r+0x1418> +80002520: 001b0713 addi a4,s6,1 +80002524: 01bc8cb3 add s9,s9,s11 +80002528: 00e92023 sw a4,0(s2) +8000252c: 01b92223 sw s11,4(s2) +80002530: 0f912623 sw s9,236(sp) +80002534: 0ec12423 sw a2,232(sp) +80002538: 00700793 li a5,7 +8000253c: 50c7cc63 blt a5,a2,80002a54 <_vfprintf_r+0x163c> +80002540: 01090793 addi a5,s2,16 +80002544: 00248693 addi a3,s1,2 +80002548: 00088913 mv s2,a7 +8000254c: 00078893 mv a7,a5 +80002550: 03812603 lw a2,56(sp) +80002554: 0d410713 addi a4,sp,212 +80002558: 00e92023 sw a4,0(s2) +8000255c: 019607b3 add a5,a2,s9 +80002560: 00c92223 sw a2,4(s2) +80002564: 0ef12623 sw a5,236(sp) +80002568: 0ed12423 sw a3,232(sp) +8000256c: 00700713 li a4,7 +80002570: 9ad75863 bge a4,a3,80001720 <_vfprintf_r+0x308> +80002574: ef4ff06f j 80001c68 <_vfprintf_r+0x850> +80002578: 80015737 lui a4,0x80015 +8000257c: 01000613 li a2,16 +80002580: 0e812683 lw a3,232(sp) +80002584: e1870e93 addi t4,a4,-488 # 80014e18 <__BSS_END__+0xffffe1dc> +80002588: 09065c63 bge a2,a6,80002620 <_vfprintf_r+0x1208> +8000258c: 04812023 sw s0,64(sp) +80002590: 04912223 sw s1,68(sp) +80002594: 000d0413 mv s0,s10 +80002598: 000c0493 mv s1,s8 +8000259c: 01000e13 li t3,16 +800025a0: 00700293 li t0,7 +800025a4: 00080c13 mv s8,a6 +800025a8: 000e8d13 mv s10,t4 +800025ac: 00c0006f j 800025b8 <_vfprintf_r+0x11a0> +800025b0: ff0c0c13 addi s8,s8,-16 +800025b4: 058e5a63 bge t3,s8,80002608 <_vfprintf_r+0x11f0> +800025b8: 01078793 addi a5,a5,16 +800025bc: 00168693 addi a3,a3,1 +800025c0: 01a8a023 sw s10,0(a7) +800025c4: 01c8a223 sw t3,4(a7) +800025c8: 0ef12623 sw a5,236(sp) +800025cc: 0ed12423 sw a3,232(sp) +800025d0: 00888893 addi a7,a7,8 +800025d4: fcd2dee3 bge t0,a3,800025b0 <_vfprintf_r+0x1198> +800025d8: 0e410613 addi a2,sp,228 +800025dc: 00048593 mv a1,s1 +800025e0: 00040513 mv a0,s0 +800025e4: 7b5090ef jal ra,8000c598 <__sprint_r> +800025e8: 7a051263 bnez a0,80002d8c <_vfprintf_r+0x1974> +800025ec: 01000e13 li t3,16 +800025f0: ff0c0c13 addi s8,s8,-16 +800025f4: 0ec12783 lw a5,236(sp) +800025f8: 0e812683 lw a3,232(sp) +800025fc: 10c10893 addi a7,sp,268 +80002600: 00700293 li t0,7 +80002604: fb8e4ae3 blt t3,s8,800025b8 <_vfprintf_r+0x11a0> +80002608: 000c0813 mv a6,s8 +8000260c: 000d0e93 mv t4,s10 +80002610: 00048c13 mv s8,s1 +80002614: 00040d13 mv s10,s0 +80002618: 04412483 lw s1,68(sp) +8000261c: 04012403 lw s0,64(sp) +80002620: 010787b3 add a5,a5,a6 +80002624: 00168693 addi a3,a3,1 +80002628: 01d8a023 sw t4,0(a7) +8000262c: 0108a223 sw a6,4(a7) +80002630: 0ef12623 sw a5,236(sp) +80002634: 0ed12423 sw a3,232(sp) +80002638: 00700613 li a2,7 +8000263c: 00888893 addi a7,a7,8 +80002640: 00d64463 blt a2,a3,80002648 <_vfprintf_r+0x1230> +80002644: 82cff06f j 80001670 <_vfprintf_r+0x258> +80002648: 0e410613 addi a2,sp,228 +8000264c: 000c0593 mv a1,s8 +80002650: 000d0513 mv a0,s10 +80002654: 745090ef jal ra,8000c598 <__sprint_r> +80002658: de0518e3 bnez a0,80002448 <_vfprintf_r+0x1030> +8000265c: 0ec12783 lw a5,236(sp) +80002660: 10c10893 addi a7,sp,268 +80002664: 80cff06f j 80001670 <_vfprintf_r+0x258> +80002668: 0e410613 addi a2,sp,228 +8000266c: 000c0593 mv a1,s8 +80002670: 000d0513 mv a0,s10 +80002674: 725090ef jal ra,8000c598 <__sprint_r> +80002678: dc0518e3 bnez a0,80002448 <_vfprintf_r+0x1030> 8000267c: 0ec12783 lw a5,236(sp) -80002680: 0e812683 lw a3,232(sp) -80002684: 10c10893 addi a7,sp,268 -80002688: 00700293 li t0,7 -8000268c: fb8e4ae3 blt t3,s8,80002640 <_vfprintf_r+0x11a0> -80002690: 000c0813 mv a6,s8 -80002694: 000d0e93 mv t4,s10 -80002698: 00048c13 mv s8,s1 -8000269c: 00040d13 mv s10,s0 -800026a0: 04412483 lw s1,68(sp) -800026a4: 04012403 lw s0,64(sp) -800026a8: 010787b3 add a5,a5,a6 -800026ac: 00168693 addi a3,a3,1 -800026b0: 01d8a023 sw t4,0(a7) -800026b4: 0108a223 sw a6,4(a7) +80002680: 10c10893 addi a7,sp,268 +80002684: 85cff06f j 800016e0 <_vfprintf_r+0x2c8> +80002688: 0cc12583 lw a1,204(sp) +8000268c: 66b05c63 blez a1,80002d04 <_vfprintf_r+0x18ec> +80002690: 01c12703 lw a4,28(sp) +80002694: 02012683 lw a3,32(sp) +80002698: 00070493 mv s1,a4 +8000269c: 38e6c263 blt a3,a4,80002a20 <_vfprintf_r+0x1608> +800026a0: 02905663 blez s1,800026cc <_vfprintf_r+0x12b4> +800026a4: 0e812683 lw a3,232(sp) +800026a8: 009787b3 add a5,a5,s1 +800026ac: 0168a023 sw s6,0(a7) +800026b0: 00168693 addi a3,a3,1 +800026b4: 0098a223 sw s1,4(a7) 800026b8: 0ef12623 sw a5,236(sp) 800026bc: 0ed12423 sw a3,232(sp) 800026c0: 00700613 li a2,7 800026c4: 00888893 addi a7,a7,8 -800026c8: 00d64463 blt a2,a3,800026d0 <_vfprintf_r+0x1230> -800026cc: 82cff06f j 800016f8 <_vfprintf_r+0x258> -800026d0: 0e410613 addi a2,sp,228 -800026d4: 000c0593 mv a1,s8 -800026d8: 000d0513 mv a0,s10 -800026dc: 1140a0ef jal ra,8000c7f0 <__sprint_r> -800026e0: de0518e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -800026e4: 0ec12783 lw a5,236(sp) -800026e8: 10c10893 addi a7,sp,268 -800026ec: 80cff06f j 800016f8 <_vfprintf_r+0x258> -800026f0: 0e410613 addi a2,sp,228 -800026f4: 000c0593 mv a1,s8 -800026f8: 000d0513 mv a0,s10 -800026fc: 0f40a0ef jal ra,8000c7f0 <__sprint_r> -80002700: dc0518e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002704: 0ec12783 lw a5,236(sp) -80002708: 10c10893 addi a7,sp,268 -8000270c: 85cff06f j 80001768 <_vfprintf_r+0x2c8> -80002710: 0cc12583 lw a1,204(sp) -80002714: 66b05c63 blez a1,80002d8c <_vfprintf_r+0x18ec> -80002718: 01c12703 lw a4,28(sp) -8000271c: 02012683 lw a3,32(sp) -80002720: 00070493 mv s1,a4 -80002724: 38e6c263 blt a3,a4,80002aa8 <_vfprintf_r+0x1608> -80002728: 02905663 blez s1,80002754 <_vfprintf_r+0x12b4> -8000272c: 0e812683 lw a3,232(sp) -80002730: 009787b3 add a5,a5,s1 -80002734: 0168a023 sw s6,0(a7) -80002738: 00168693 addi a3,a3,1 -8000273c: 0098a223 sw s1,4(a7) -80002740: 0ef12623 sw a5,236(sp) -80002744: 0ed12423 sw a3,232(sp) -80002748: 00700613 li a2,7 -8000274c: 00888893 addi a7,a7,8 -80002750: 32d642e3 blt a2,a3,80003274 <_vfprintf_r+0x1dd4> -80002754: fff4c693 not a3,s1 -80002758: 01c12703 lw a4,28(sp) -8000275c: 41f6d693 srai a3,a3,0x1f -80002760: 00d4f4b3 and s1,s1,a3 -80002764: 409704b3 sub s1,a4,s1 -80002768: 48904463 bgtz s1,80002bf0 <_vfprintf_r+0x1750> -8000276c: 01c12703 lw a4,28(sp) -80002770: 400a7693 andi a3,s4,1024 -80002774: 00eb0db3 add s11,s6,a4 -80002778: 0c0698e3 bnez a3,80003048 <_vfprintf_r+0x1ba8> -8000277c: 0cc12483 lw s1,204(sp) -80002780: 02012703 lw a4,32(sp) -80002784: 00e4c663 blt s1,a4,80002790 <_vfprintf_r+0x12f0> -80002788: 001a7693 andi a3,s4,1 -8000278c: 300688e3 beqz a3,8000329c <_vfprintf_r+0x1dfc> -80002790: 03012683 lw a3,48(sp) -80002794: 02c12703 lw a4,44(sp) -80002798: 00700613 li a2,7 -8000279c: 00d8a023 sw a3,0(a7) -800027a0: 0e812683 lw a3,232(sp) -800027a4: 00e787b3 add a5,a5,a4 -800027a8: 00e8a223 sw a4,4(a7) -800027ac: 00168693 addi a3,a3,1 -800027b0: 0ef12623 sw a5,236(sp) -800027b4: 0ed12423 sw a3,232(sp) -800027b8: 00888893 addi a7,a7,8 -800027bc: 00d65463 bge a2,a3,800027c4 <_vfprintf_r+0x1324> -800027c0: 1780106f j 80003938 <_vfprintf_r+0x2498> -800027c4: 02012683 lw a3,32(sp) -800027c8: 00db0733 add a4,s6,a3 -800027cc: 409684b3 sub s1,a3,s1 -800027d0: 41b70733 sub a4,a4,s11 -800027d4: 00048913 mv s2,s1 -800027d8: 00975463 bge a4,s1,800027e0 <_vfprintf_r+0x1340> -800027dc: 00070913 mv s2,a4 -800027e0: 03205863 blez s2,80002810 <_vfprintf_r+0x1370> -800027e4: 0e812703 lw a4,232(sp) -800027e8: 012787b3 add a5,a5,s2 -800027ec: 01b8a023 sw s11,0(a7) -800027f0: 00170713 addi a4,a4,1 -800027f4: 0128a223 sw s2,4(a7) -800027f8: 0ef12623 sw a5,236(sp) -800027fc: 0ee12423 sw a4,232(sp) -80002800: 00700693 li a3,7 -80002804: 00888893 addi a7,a7,8 -80002808: 00e6d463 bge a3,a4,80002810 <_vfprintf_r+0x1370> -8000280c: 1c80106f j 800039d4 <_vfprintf_r+0x2534> -80002810: fff94713 not a4,s2 -80002814: 41f75713 srai a4,a4,0x1f -80002818: 00e97733 and a4,s2,a4 -8000281c: 40e484b3 sub s1,s1,a4 -80002820: 00904463 bgtz s1,80002828 <_vfprintf_r+0x1388> -80002824: f85fe06f j 800017a8 <_vfprintf_r+0x308> -80002828: 01000693 li a3,16 -8000282c: 0e812703 lw a4,232(sp) -80002830: 6296d863 bge a3,s1,80002e60 <_vfprintf_r+0x19c0> -80002834: 01000913 li s2,16 -80002838: 00700c93 li s9,7 -8000283c: 00c0006f j 80002848 <_vfprintf_r+0x13a8> -80002840: ff048493 addi s1,s1,-16 -80002844: 60995e63 bge s2,s1,80002e60 <_vfprintf_r+0x19c0> -80002848: 00812683 lw a3,8(sp) -8000284c: 01078793 addi a5,a5,16 -80002850: 00170713 addi a4,a4,1 -80002854: 00d8a023 sw a3,0(a7) -80002858: 0128a223 sw s2,4(a7) -8000285c: 0ef12623 sw a5,236(sp) -80002860: 0ee12423 sw a4,232(sp) -80002864: 00888893 addi a7,a7,8 -80002868: fcecdce3 bge s9,a4,80002840 <_vfprintf_r+0x13a0> -8000286c: 0e410613 addi a2,sp,228 -80002870: 000c0593 mv a1,s8 -80002874: 000d0513 mv a0,s10 -80002878: 779090ef jal ra,8000c7f0 <__sprint_r> -8000287c: c4051ae3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002880: 0ec12783 lw a5,236(sp) -80002884: 0e812703 lw a4,232(sp) -80002888: 10c10893 addi a7,sp,268 -8000288c: fb5ff06f j 80002840 <_vfprintf_r+0x13a0> -80002890: 001a7793 andi a5,s4,1 -80002894: c6079ae3 bnez a5,80002508 <_vfprintf_r+0x1068> -80002898: 00c8a223 sw a2,4(a7) -8000289c: 0f912623 sw s9,236(sp) -800028a0: 0e912423 sw s1,232(sp) -800028a4: 00700793 li a5,7 -800028a8: 2297ca63 blt a5,s1,80002adc <_vfprintf_r+0x163c> -800028ac: 00268693 addi a3,a3,2 -800028b0: 01088893 addi a7,a7,16 -800028b4: d25ff06f j 800025d8 <_vfprintf_r+0x1138> -800028b8: d3b050e3 blez s11,800025d8 <_vfprintf_r+0x1138> -800028bc: 01000713 li a4,16 -800028c0: 01b74463 blt a4,s11,800028c8 <_vfprintf_r+0x1428> -800028c4: 6180106f j 80003edc <_vfprintf_r+0x2a3c> -800028c8: 00700b13 li s6,7 -800028cc: 00060493 mv s1,a2 -800028d0: 0100006f j 800028e0 <_vfprintf_r+0x1440> -800028d4: ff0d8d93 addi s11,s11,-16 -800028d8: 1db75e63 bge a4,s11,80002ab4 <_vfprintf_r+0x1614> -800028dc: 00148493 addi s1,s1,1 -800028e0: 00812783 lw a5,8(sp) -800028e4: 010c8c93 addi s9,s9,16 -800028e8: 00e92223 sw a4,4(s2) -800028ec: 00f92023 sw a5,0(s2) -800028f0: 0f912623 sw s9,236(sp) -800028f4: 0e912423 sw s1,232(sp) -800028f8: 00890913 addi s2,s2,8 -800028fc: fc9b5ce3 bge s6,s1,800028d4 <_vfprintf_r+0x1434> -80002900: 0e410613 addi a2,sp,228 -80002904: 000c0593 mv a1,s8 -80002908: 000d0513 mv a0,s10 -8000290c: 6e5090ef jal ra,8000c7f0 <__sprint_r> -80002910: bc0510e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002914: 0ec12c83 lw s9,236(sp) -80002918: 0e812483 lw s1,232(sp) -8000291c: 10c10913 addi s2,sp,268 -80002920: 01000713 li a4,16 -80002924: fb1ff06f j 800028d4 <_vfprintf_r+0x1434> -80002928: 01412683 lw a3,20(sp) -8000292c: 010a7793 andi a5,s4,16 -80002930: 00468713 addi a4,a3,4 -80002934: 16079263 bnez a5,80002a98 <_vfprintf_r+0x15f8> -80002938: 040a7793 andi a5,s4,64 -8000293c: 68078463 beqz a5,80002fc4 <_vfprintf_r+0x1b24> -80002940: 01412783 lw a5,20(sp) -80002944: 00000c93 li s9,0 -80002948: 00e12a23 sw a4,20(sp) -8000294c: 0007d903 lhu s2,0(a5) -80002950: f1cff06f j 8000206c <_vfprintf_r+0xbcc> -80002954: 01412683 lw a3,20(sp) -80002958: 010bf793 andi a5,s7,16 -8000295c: 00468713 addi a4,a3,4 -80002960: 0c079e63 bnez a5,80002a3c <_vfprintf_r+0x159c> -80002964: 040bf793 andi a5,s7,64 -80002968: 60078e63 beqz a5,80002f84 <_vfprintf_r+0x1ae4> -8000296c: 01412783 lw a5,20(sp) -80002970: 00000c93 li s9,0 -80002974: 00e12a23 sw a4,20(sp) -80002978: 0007d903 lhu s2,0(a5) -8000297c: 00100793 li a5,1 -80002980: db0ff06f j 80001f30 <_vfprintf_r+0xa90> -80002984: 01412683 lw a3,20(sp) -80002988: 010a7793 andi a5,s4,16 -8000298c: 00468713 addi a4,a3,4 -80002990: 0e079a63 bnez a5,80002a84 <_vfprintf_r+0x15e4> -80002994: 040a7793 andi a5,s4,64 -80002998: 60078663 beqz a5,80002fa4 <_vfprintf_r+0x1b04> -8000299c: 01412783 lw a5,20(sp) -800029a0: 00e12a23 sw a4,20(sp) -800029a4: 00079903 lh s2,0(a5) -800029a8: 41f95c93 srai s9,s2,0x1f -800029ac: 000c8793 mv a5,s9 -800029b0: f207de63 bgez a5,800020ec <_vfprintf_r+0xc4c> -800029b4: 012037b3 snez a5,s2 -800029b8: 41900cb3 neg s9,s9 -800029bc: 40fc8cb3 sub s9,s9,a5 -800029c0: 02d00793 li a5,45 -800029c4: 0cf103a3 sb a5,199(sp) -800029c8: 41200933 neg s2,s2 -800029cc: 000a0b93 mv s7,s4 -800029d0: 00100793 li a5,1 -800029d4: d60ff06f j 80001f34 <_vfprintf_r+0xa94> -800029d8: 001a7713 andi a4,s4,1 -800029dc: 00071463 bnez a4,800029e4 <_vfprintf_r+0x1544> -800029e0: dc9fe06f j 800017a8 <_vfprintf_r+0x308> -800029e4: 8c1ff06f j 800022a4 <_vfprintf_r+0xe04> -800029e8: 000c8893 mv a7,s9 -800029ec: ed4ff06f j 800020c0 <_vfprintf_r+0xc20> -800029f0: 03000793 li a5,48 -800029f4: 1af107a3 sb a5,431(sp) -800029f8: 1af10b13 addi s6,sp,431 -800029fc: d60ff06f j 80001f5c <_vfprintf_r+0xabc> -80002a00: 03c12783 lw a5,60(sp) -80002a04: 00044483 lbu s1,0(s0) -80002a08: 00079463 bnez a5,80002a10 <_vfprintf_r+0x1570> -80002a0c: c4dfe06f j 80001658 <_vfprintf_r+0x1b8> -80002a10: 0007c783 lbu a5,0(a5) -80002a14: 00079463 bnez a5,80002a1c <_vfprintf_r+0x157c> -80002a18: c41fe06f j 80001658 <_vfprintf_r+0x1b8> -80002a1c: 400a6a13 ori s4,s4,1024 -80002a20: c39fe06f j 80001658 <_vfprintf_r+0x1b8> -80002a24: 00c12683 lw a3,12(sp) -80002a28: 00040b13 mv s6,s0 -80002a2c: 41f6d793 srai a5,a3,0x1f -80002a30: 00d72023 sw a3,0(a4) -80002a34: 00f72223 sw a5,4(a4) -80002a38: db9fe06f j 800017f0 <_vfprintf_r+0x350> -80002a3c: 0006a903 lw s2,0(a3) -80002a40: 00000c93 li s9,0 -80002a44: 00e12a23 sw a4,20(sp) -80002a48: 00100793 li a5,1 -80002a4c: ce4ff06f j 80001f30 <_vfprintf_r+0xa90> -80002a50: 01412703 lw a4,20(sp) -80002a54: 00072783 lw a5,0(a4) -80002a58: 00470713 addi a4,a4,4 -80002a5c: 00e12a23 sw a4,20(sp) -80002a60: 0007a583 lw a1,0(a5) -80002a64: 0047a603 lw a2,4(a5) -80002a68: 0087a683 lw a3,8(a5) -80002a6c: 00c7a783 lw a5,12(a5) -80002a70: 0eb12823 sw a1,240(sp) -80002a74: 0ec12a23 sw a2,244(sp) -80002a78: 0ed12c23 sw a3,248(sp) -80002a7c: 0ef12e23 sw a5,252(sp) -80002a80: ef5fe06f j 80001974 <_vfprintf_r+0x4d4> -80002a84: 0006a903 lw s2,0(a3) -80002a88: 00e12a23 sw a4,20(sp) -80002a8c: 41f95c93 srai s9,s2,0x1f -80002a90: 000c8793 mv a5,s9 -80002a94: e54ff06f j 800020e8 <_vfprintf_r+0xc48> -80002a98: 0006a903 lw s2,0(a3) -80002a9c: 00000c93 li s9,0 -80002aa0: 00e12a23 sw a4,20(sp) -80002aa4: dc8ff06f j 8000206c <_vfprintf_r+0xbcc> -80002aa8: 00068493 mv s1,a3 -80002aac: c89040e3 bgtz s1,8000272c <_vfprintf_r+0x128c> -80002ab0: ca5ff06f j 80002754 <_vfprintf_r+0x12b4> -80002ab4: 00148693 addi a3,s1,1 -80002ab8: 00890713 addi a4,s2,8 -80002abc: 00812783 lw a5,8(sp) -80002ac0: 01bc8cb3 add s9,s9,s11 -80002ac4: 01b92223 sw s11,4(s2) -80002ac8: 00f92023 sw a5,0(s2) -80002acc: 0f912623 sw s9,236(sp) -80002ad0: 0ed12423 sw a3,232(sp) -80002ad4: 00700793 li a5,7 -80002ad8: 74d7de63 bge a5,a3,80003234 <_vfprintf_r+0x1d94> -80002adc: 0e410613 addi a2,sp,228 -80002ae0: 000c0593 mv a1,s8 -80002ae4: 000d0513 mv a0,s10 -80002ae8: 509090ef jal ra,8000c7f0 <__sprint_r> -80002aec: 9e0512e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002af0: 0e812683 lw a3,232(sp) -80002af4: 0ec12c83 lw s9,236(sp) -80002af8: 11410893 addi a7,sp,276 -80002afc: 00168693 addi a3,a3,1 -80002b00: 10c10913 addi s2,sp,268 -80002b04: ad5ff06f j 800025d8 <_vfprintf_r+0x1138> -80002b08: 000c8893 mv a7,s9 -80002b0c: 000a0b93 mv s7,s4 -80002b10: d70ff06f j 80002080 <_vfprintf_r+0xbe0> -80002b14: 800157b7 lui a5,0x80015 -80002b18: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -80002b1c: 000c8893 mv a7,s9 -80002b20: 02f12a23 sw a5,52(sp) -80002b24: 020a7793 andi a5,s4,32 -80002b28: 12078863 beqz a5,80002c58 <_vfprintf_r+0x17b8> -80002b2c: 01412783 lw a5,20(sp) -80002b30: 00778b13 addi s6,a5,7 -80002b34: ff8b7b13 andi s6,s6,-8 -80002b38: 000b2903 lw s2,0(s6) -80002b3c: 004b2c83 lw s9,4(s6) -80002b40: 008b0793 addi a5,s6,8 -80002b44: 00f12a23 sw a5,20(sp) -80002b48: 001a7793 andi a5,s4,1 -80002b4c: 00078e63 beqz a5,80002b68 <_vfprintf_r+0x16c8> -80002b50: 019967b3 or a5,s2,s9 -80002b54: 00078a63 beqz a5,80002b68 <_vfprintf_r+0x16c8> -80002b58: 03000793 li a5,48 -80002b5c: 0cf10423 sb a5,200(sp) -80002b60: 0c9104a3 sb s1,201(sp) -80002b64: 002a6a13 ori s4,s4,2 -80002b68: bffa7b93 andi s7,s4,-1025 -80002b6c: 00200793 li a5,2 -80002b70: bc0ff06f j 80001f30 <_vfprintf_r+0xa90> -80002b74: 800157b7 lui a5,0x80015 -80002b78: c4078793 addi a5,a5,-960 # 80014c40 <__BSS_END__+0xffffe010> -80002b7c: 000c8893 mv a7,s9 -80002b80: 02f12a23 sw a5,52(sp) -80002b84: fa1ff06f j 80002b24 <_vfprintf_r+0x1684> -80002b88: 000c8893 mv a7,s9 -80002b8c: cbcff06f j 80002048 <_vfprintf_r+0xba8> -80002b90: 0e410613 addi a2,sp,228 -80002b94: 000c0593 mv a1,s8 -80002b98: 000d0513 mv a0,s10 -80002b9c: 455090ef jal ra,8000c7f0 <__sprint_r> -80002ba0: 920518e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002ba4: 0ec12783 lw a5,236(sp) -80002ba8: 10c10893 addi a7,sp,268 -80002bac: f28ff06f j 800022d4 <_vfprintf_r+0xe34> -80002bb0: 00144483 lbu s1,1(s0) -80002bb4: 020a6a13 ori s4,s4,32 -80002bb8: 00140413 addi s0,s0,1 -80002bbc: a9dfe06f j 80001658 <_vfprintf_r+0x1b8> -80002bc0: 00144483 lbu s1,1(s0) -80002bc4: 200a6a13 ori s4,s4,512 -80002bc8: 00140413 addi s0,s0,1 -80002bcc: a8dfe06f j 80001658 <_vfprintf_r+0x1b8> -80002bd0: 00600793 li a5,6 -80002bd4: 000d8c93 mv s9,s11 -80002bd8: 6bb7ee63 bltu a5,s11,80003294 <_vfprintf_r+0x1df4> -80002bdc: 80015737 lui a4,0x80015 -80002be0: 000c8a93 mv s5,s9 -80002be4: 01212a23 sw s2,20(sp) -80002be8: c5470b13 addi s6,a4,-940 # 80014c54 <__BSS_END__+0xffffe024> -80002bec: ad9fe06f j 800016c4 <_vfprintf_r+0x224> -80002bf0: 01000613 li a2,16 -80002bf4: 0e812683 lw a3,232(sp) -80002bf8: 40965463 bge a2,s1,80003000 <_vfprintf_r+0x1b60> -80002bfc: 01000c93 li s9,16 -80002c00: 00700d93 li s11,7 -80002c04: 00c0006f j 80002c10 <_vfprintf_r+0x1770> -80002c08: ff048493 addi s1,s1,-16 -80002c0c: 3e9cda63 bge s9,s1,80003000 <_vfprintf_r+0x1b60> -80002c10: 00812703 lw a4,8(sp) -80002c14: 01078793 addi a5,a5,16 -80002c18: 00168693 addi a3,a3,1 -80002c1c: 00e8a023 sw a4,0(a7) -80002c20: 0198a223 sw s9,4(a7) -80002c24: 0ef12623 sw a5,236(sp) -80002c28: 0ed12423 sw a3,232(sp) -80002c2c: 00888893 addi a7,a7,8 -80002c30: fcdddce3 bge s11,a3,80002c08 <_vfprintf_r+0x1768> -80002c34: 0e410613 addi a2,sp,228 -80002c38: 000c0593 mv a1,s8 -80002c3c: 000d0513 mv a0,s10 -80002c40: 3b1090ef jal ra,8000c7f0 <__sprint_r> -80002c44: 880516e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002c48: 0ec12783 lw a5,236(sp) -80002c4c: 0e812683 lw a3,232(sp) -80002c50: 10c10893 addi a7,sp,268 -80002c54: fb5ff06f j 80002c08 <_vfprintf_r+0x1768> -80002c58: 01412683 lw a3,20(sp) -80002c5c: 010a7793 andi a5,s4,16 -80002c60: 00468713 addi a4,a3,4 -80002c64: 1c078063 beqz a5,80002e24 <_vfprintf_r+0x1984> -80002c68: 0006a903 lw s2,0(a3) -80002c6c: 00000c93 li s9,0 -80002c70: 00e12a23 sw a4,20(sp) -80002c74: ed5ff06f j 80002b48 <_vfprintf_r+0x16a8> -80002c78: 0e410613 addi a2,sp,228 -80002c7c: 000c0593 mv a1,s8 -80002c80: 000d0513 mv a0,s10 -80002c84: 36d090ef jal ra,8000c7f0 <__sprint_r> -80002c88: 840514e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002c8c: 0ec12c83 lw s9,236(sp) -80002c90: 0e812483 lw s1,232(sp) -80002c94: 10c10913 addi s2,sp,268 -80002c98: 889ff06f j 80002520 <_vfprintf_r+0x1080> -80002c9c: 0e410613 addi a2,sp,228 -80002ca0: 000c0593 mv a1,s8 -80002ca4: 000d0513 mv a0,s10 -80002ca8: 349090ef jal ra,8000c7f0 <__sprint_r> -80002cac: 820512e3 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002cb0: 0ec12c83 lw s9,236(sp) -80002cb4: 0e812483 lw s1,232(sp) -80002cb8: 10c10913 addi s2,sp,268 -80002cbc: 891ff06f j 8000254c <_vfprintf_r+0x10ac> -80002cc0: 1b010b13 addi s6,sp,432 -80002cc4: 00000793 li a5,0 -80002cc8: 00812823 sw s0,16(sp) -80002ccc: 00912e23 sw s1,28(sp) -80002cd0: 000b0413 mv s0,s6 -80002cd4: 03312223 sw s3,36(sp) -80002cd8: 000c0b13 mv s6,s8 -80002cdc: 00090493 mv s1,s2 -80002ce0: 000c8993 mv s3,s9 -80002ce4: 400bfa13 andi s4,s7,1024 -80002ce8: 03c12c83 lw s9,60(sp) -80002cec: 0ff00a93 li s5,255 -80002cf0: 00088c13 mv s8,a7 -80002cf4: 00078913 mv s2,a5 -80002cf8: 0240006f j 80002d1c <_vfprintf_r+0x187c> -80002cfc: 00a00613 li a2,10 -80002d00: 00000693 li a3,0 -80002d04: 00048513 mv a0,s1 -80002d08: 00098593 mv a1,s3 -80002d0c: 6f40d0ef jal ra,80010400 <__udivdi3> -80002d10: 2a098ae3 beqz s3,800037c4 <_vfprintf_r+0x2324> -80002d14: 00050493 mv s1,a0 -80002d18: 00058993 mv s3,a1 -80002d1c: 00a00613 li a2,10 -80002d20: 00000693 li a3,0 -80002d24: 00048513 mv a0,s1 -80002d28: 00098593 mv a1,s3 -80002d2c: 3090d0ef jal ra,80010834 <__umoddi3> -80002d30: 03050513 addi a0,a0,48 -80002d34: fea40fa3 sb a0,-1(s0) -80002d38: 00190913 addi s2,s2,1 -80002d3c: fff40413 addi s0,s0,-1 -80002d40: fa0a0ee3 beqz s4,80002cfc <_vfprintf_r+0x185c> -80002d44: 000cc683 lbu a3,0(s9) -80002d48: fad91ae3 bne s2,a3,80002cfc <_vfprintf_r+0x185c> -80002d4c: fb5908e3 beq s2,s5,80002cfc <_vfprintf_r+0x185c> -80002d50: 4a099263 bnez s3,800031f4 <_vfprintf_r+0x1d54> -80002d54: 00900793 li a5,9 -80002d58: 4897ee63 bltu a5,s1,800031f4 <_vfprintf_r+0x1d54> -80002d5c: 000c0893 mv a7,s8 -80002d60: 1b010793 addi a5,sp,432 -80002d64: 000b0c13 mv s8,s6 -80002d68: 00040b13 mv s6,s0 -80002d6c: 03912e23 sw s9,60(sp) -80002d70: 01c12483 lw s1,28(sp) -80002d74: 02412983 lw s3,36(sp) -80002d78: 01012403 lw s0,16(sp) -80002d7c: 03212023 sw s2,32(sp) -80002d80: 41678cb3 sub s9,a5,s6 -80002d84: 000b8a13 mv s4,s7 -80002d88: 9d4ff06f j 80001f5c <_vfprintf_r+0xabc> -80002d8c: 0e812683 lw a3,232(sp) -80002d90: 80015637 lui a2,0x80015 -80002d94: c5c60613 addi a2,a2,-932 # 80014c5c <__BSS_END__+0xffffe02c> -80002d98: 00c8a023 sw a2,0(a7) -80002d9c: 00178793 addi a5,a5,1 -80002da0: 00100613 li a2,1 -80002da4: 00168693 addi a3,a3,1 -80002da8: 00c8a223 sw a2,4(a7) -80002dac: 0ef12623 sw a5,236(sp) -80002db0: 0ed12423 sw a3,232(sp) -80002db4: 00700613 li a2,7 -80002db8: 00888893 addi a7,a7,8 -80002dbc: 48d64463 blt a2,a3,80003244 <_vfprintf_r+0x1da4> -80002dc0: 00058463 beqz a1,80002dc8 <_vfprintf_r+0x1928> -80002dc4: eadfe06f j 80001c70 <_vfprintf_r+0x7d0> -80002dc8: 02012703 lw a4,32(sp) -80002dcc: 001a7693 andi a3,s4,1 -80002dd0: 00e6e6b3 or a3,a3,a4 -80002dd4: 00069463 bnez a3,80002ddc <_vfprintf_r+0x193c> -80002dd8: 9d1fe06f j 800017a8 <_vfprintf_r+0x308> -80002ddc: 03012683 lw a3,48(sp) -80002de0: 02c12703 lw a4,44(sp) -80002de4: 00700613 li a2,7 -80002de8: 00d8a023 sw a3,0(a7) -80002dec: 0e812683 lw a3,232(sp) -80002df0: 00f707b3 add a5,a4,a5 -80002df4: 00e8a223 sw a4,4(a7) -80002df8: 00168693 addi a3,a3,1 -80002dfc: 0ef12623 sw a5,236(sp) -80002e00: 0ed12423 sw a3,232(sp) -80002e04: 00d65463 bge a2,a3,80002e0c <_vfprintf_r+0x196c> -80002e08: e99fe06f j 80001ca0 <_vfprintf_r+0x800> -80002e0c: 00888893 addi a7,a7,8 -80002e10: ebdfe06f j 80001ccc <_vfprintf_r+0x82c> -80002e14: 01012b83 lw s7,16(sp) -80002e18: 00040d13 mv s10,s0 -80002e1c: 00048c13 mv s8,s1 -80002e20: eb4ff06f j 800024d4 <_vfprintf_r+0x1034> -80002e24: 040a7793 andi a5,s4,64 -80002e28: 14078063 beqz a5,80002f68 <_vfprintf_r+0x1ac8> -80002e2c: 01412783 lw a5,20(sp) -80002e30: 00000c93 li s9,0 -80002e34: 00e12a23 sw a4,20(sp) -80002e38: 0007d903 lhu s2,0(a5) -80002e3c: d0dff06f j 80002b48 <_vfprintf_r+0x16a8> -80002e40: 0e410613 addi a2,sp,228 -80002e44: 000c0593 mv a1,s8 -80002e48: 000d0513 mv a0,s10 -80002e4c: 1a5090ef jal ra,8000c7f0 <__sprint_r> -80002e50: e8051063 bnez a0,800024d0 <_vfprintf_r+0x1030> -80002e54: 0ec12783 lw a5,236(sp) -80002e58: 10c10893 addi a7,sp,268 -80002e5c: c3cff06f j 80002298 <_vfprintf_r+0xdf8> -80002e60: 00812683 lw a3,8(sp) -80002e64: 009787b3 add a5,a5,s1 -80002e68: 0098a223 sw s1,4(a7) -80002e6c: 00d8a023 sw a3,0(a7) -80002e70: 00170713 addi a4,a4,1 -80002e74: 0ef12623 sw a5,236(sp) -80002e78: 0ee12423 sw a4,232(sp) -80002e7c: 00700693 li a3,7 -80002e80: 00e6c463 blt a3,a4,80002e88 <_vfprintf_r+0x19e8> -80002e84: 921fe06f j 800017a4 <_vfprintf_r+0x304> -80002e88: e69fe06f j 80001cf0 <_vfprintf_r+0x850> -80002e8c: 0f012783 lw a5,240(sp) -80002e90: 0a010593 addi a1,sp,160 -80002e94: 0b010513 addi a0,sp,176 -80002e98: 0af12823 sw a5,176(sp) -80002e9c: 0f412783 lw a5,244(sp) -80002ea0: 0a012023 sw zero,160(sp) -80002ea4: 0a012223 sw zero,164(sp) -80002ea8: 0af12a23 sw a5,180(sp) -80002eac: 0f812783 lw a5,248(sp) -80002eb0: 0a012423 sw zero,168(sp) -80002eb4: 0a012623 sw zero,172(sp) -80002eb8: 0af12c23 sw a5,184(sp) -80002ebc: 0fc12783 lw a5,252(sp) -80002ec0: 0af12e23 sw a5,188(sp) -80002ec4: 4350e0ef jal ra,80011af8 <__letf2> -80002ec8: 01012883 lw a7,16(sp) -80002ecc: 260540e3 bltz a0,8000392c <_vfprintf_r+0x248c> -80002ed0: 0c714783 lbu a5,199(sp) -80002ed4: 04700713 li a4,71 -80002ed8: 38975863 bge a4,s1,80003268 <_vfprintf_r+0x1dc8> -80002edc: 80015737 lui a4,0x80015 -80002ee0: c2070b13 addi s6,a4,-992 # 80014c20 <__BSS_END__+0xffffdff0> -80002ee4: 00012823 sw zero,16(sp) -80002ee8: 02012423 sw zero,40(sp) -80002eec: 02012223 sw zero,36(sp) -80002ef0: 00012e23 sw zero,28(sp) -80002ef4: f7fa7a13 andi s4,s4,-129 -80002ef8: 00300a93 li s5,3 -80002efc: 00300c93 li s9,3 -80002f00: 00000d93 li s11,0 -80002f04: 00078463 beqz a5,80002f0c <_vfprintf_r+0x1a6c> -80002f08: f75fe06f j 80001e7c <_vfprintf_r+0x9dc> -80002f0c: fccfe06f j 800016d8 <_vfprintf_r+0x238> -80002f10: 00c12783 lw a5,12(sp) -80002f14: 00040b13 mv s6,s0 -80002f18: 00f72023 sw a5,0(a4) -80002f1c: 8d5fe06f j 800017f0 <_vfprintf_r+0x350> -80002f20: 000b0513 mv a0,s6 -80002f24: 05912023 sw s9,64(sp) -80002f28: 491060ef jal ra,80009bb8 -80002f2c: 0c714783 lbu a5,199(sp) -80002f30: fff54a93 not s5,a0 -80002f34: 41fada93 srai s5,s5,0x1f -80002f38: 01212a23 sw s2,20(sp) -80002f3c: 00012823 sw zero,16(sp) -80002f40: 02012423 sw zero,40(sp) -80002f44: 02012223 sw zero,36(sp) -80002f48: 00012e23 sw zero,28(sp) -80002f4c: 04012883 lw a7,64(sp) -80002f50: 00050c93 mv s9,a0 -80002f54: 01557ab3 and s5,a0,s5 -80002f58: 00000d93 li s11,0 -80002f5c: 00078463 beqz a5,80002f64 <_vfprintf_r+0x1ac4> -80002f60: f1dfe06f j 80001e7c <_vfprintf_r+0x9dc> -80002f64: f74fe06f j 800016d8 <_vfprintf_r+0x238> -80002f68: 200a7793 andi a5,s4,512 -80002f6c: 3a078263 beqz a5,80003310 <_vfprintf_r+0x1e70> -80002f70: 01412783 lw a5,20(sp) -80002f74: 00000c93 li s9,0 -80002f78: 00e12a23 sw a4,20(sp) -80002f7c: 0007c903 lbu s2,0(a5) -80002f80: bc9ff06f j 80002b48 <_vfprintf_r+0x16a8> -80002f84: 200bf793 andi a5,s7,512 -80002f88: 36078863 beqz a5,800032f8 <_vfprintf_r+0x1e58> -80002f8c: 01412783 lw a5,20(sp) -80002f90: 00000c93 li s9,0 -80002f94: 00e12a23 sw a4,20(sp) -80002f98: 0007c903 lbu s2,0(a5) -80002f9c: 00100793 li a5,1 -80002fa0: f91fe06f j 80001f30 <_vfprintf_r+0xa90> -80002fa4: 200a7793 andi a5,s4,512 -80002fa8: 32078c63 beqz a5,800032e0 <_vfprintf_r+0x1e40> -80002fac: 01412783 lw a5,20(sp) -80002fb0: 00e12a23 sw a4,20(sp) -80002fb4: 00078903 lb s2,0(a5) -80002fb8: 41f95c93 srai s9,s2,0x1f -80002fbc: 000c8793 mv a5,s9 -80002fc0: 928ff06f j 800020e8 <_vfprintf_r+0xc48> -80002fc4: 200a7793 andi a5,s4,512 -80002fc8: 30078263 beqz a5,800032cc <_vfprintf_r+0x1e2c> -80002fcc: 01412783 lw a5,20(sp) -80002fd0: 00000c93 li s9,0 -80002fd4: 00e12a23 sw a4,20(sp) -80002fd8: 0007c903 lbu s2,0(a5) -80002fdc: 890ff06f j 8000206c <_vfprintf_r+0xbcc> -80002fe0: 0fc12783 lw a5,252(sp) -80002fe4: 3407ca63 bltz a5,80003338 <_vfprintf_r+0x1e98> -80002fe8: 0c714783 lbu a5,199(sp) -80002fec: 04700713 li a4,71 -80002ff0: 1c975ce3 bge a4,s1,800039c8 <_vfprintf_r+0x2528> -80002ff4: 80015737 lui a4,0x80015 -80002ff8: c2870b13 addi s6,a4,-984 # 80014c28 <__BSS_END__+0xffffdff8> -80002ffc: ee9ff06f j 80002ee4 <_vfprintf_r+0x1a44> -80003000: 00812703 lw a4,8(sp) -80003004: 009787b3 add a5,a5,s1 -80003008: 00168693 addi a3,a3,1 -8000300c: 00e8a023 sw a4,0(a7) -80003010: 0098a223 sw s1,4(a7) -80003014: 0ef12623 sw a5,236(sp) -80003018: 0ed12423 sw a3,232(sp) -8000301c: 00700613 li a2,7 -80003020: 00888893 addi a7,a7,8 -80003024: f4d65463 bge a2,a3,8000276c <_vfprintf_r+0x12cc> -80003028: 0e410613 addi a2,sp,228 -8000302c: 000c0593 mv a1,s8 -80003030: 000d0513 mv a0,s10 -80003034: 7bc090ef jal ra,8000c7f0 <__sprint_r> -80003038: c8051c63 bnez a0,800024d0 <_vfprintf_r+0x1030> -8000303c: 0ec12783 lw a5,236(sp) -80003040: 10c10893 addi a7,sp,268 -80003044: f28ff06f j 8000276c <_vfprintf_r+0x12cc> -80003048: 02012703 lw a4,32(sp) -8000304c: 02412c83 lw s9,36(sp) -80003050: 01412e23 sw s4,28(sp) -80003054: 04812023 sw s0,64(sp) -80003058: 05312223 sw s3,68(sp) -8000305c: 03512223 sw s5,36(sp) -80003060: 02812983 lw s3,40(sp) -80003064: 03612423 sw s6,40(sp) -80003068: 00eb0bb3 add s7,s6,a4 -8000306c: 03c12403 lw s0,60(sp) -80003070: 04812a03 lw s4,72(sp) -80003074: 04c12a83 lw s5,76(sp) -80003078: 00700493 li s1,7 -8000307c: 01000913 li s2,16 -80003080: 000c0b13 mv s6,s8 -80003084: 080c8863 beqz s9,80003114 <_vfprintf_r+0x1c74> -80003088: 08099863 bnez s3,80003118 <_vfprintf_r+0x1c78> -8000308c: fff40413 addi s0,s0,-1 -80003090: fffc8c93 addi s9,s9,-1 -80003094: 0e812703 lw a4,232(sp) -80003098: 014787b3 add a5,a5,s4 -8000309c: 0158a023 sw s5,0(a7) -800030a0: 00170713 addi a4,a4,1 -800030a4: 0148a223 sw s4,4(a7) -800030a8: 0ef12623 sw a5,236(sp) -800030ac: 0ee12423 sw a4,232(sp) -800030b0: 00888893 addi a7,a7,8 -800030b4: 0ee4ce63 blt s1,a4,800031b0 <_vfprintf_r+0x1d10> -800030b8: 00044683 lbu a3,0(s0) -800030bc: 41bb8633 sub a2,s7,s11 -800030c0: 00068c13 mv s8,a3 -800030c4: 00d65463 bge a2,a3,800030cc <_vfprintf_r+0x1c2c> -800030c8: 00060c13 mv s8,a2 -800030cc: 03805663 blez s8,800030f8 <_vfprintf_r+0x1c58> -800030d0: 0e812683 lw a3,232(sp) -800030d4: 018787b3 add a5,a5,s8 -800030d8: 01b8a023 sw s11,0(a7) -800030dc: 00168693 addi a3,a3,1 -800030e0: 0188a223 sw s8,4(a7) -800030e4: 0ef12623 sw a5,236(sp) -800030e8: 0ed12423 sw a3,232(sp) -800030ec: 0ed4c263 blt s1,a3,800031d0 <_vfprintf_r+0x1d30> -800030f0: 00044683 lbu a3,0(s0) -800030f4: 00888893 addi a7,a7,8 -800030f8: fffc4613 not a2,s8 -800030fc: 41f65613 srai a2,a2,0x1f -80003100: 00cc7733 and a4,s8,a2 -80003104: 40e68c33 sub s8,a3,a4 -80003108: 01804c63 bgtz s8,80003120 <_vfprintf_r+0x1c80> -8000310c: 00dd8db3 add s11,s11,a3 -80003110: f60c9ce3 bnez s9,80003088 <_vfprintf_r+0x1be8> -80003114: 5e098a63 beqz s3,80003708 <_vfprintf_r+0x2268> -80003118: fff98993 addi s3,s3,-1 -8000311c: f79ff06f j 80003094 <_vfprintf_r+0x1bf4> -80003120: 0e812683 lw a3,232(sp) -80003124: 01894863 blt s2,s8,80003134 <_vfprintf_r+0x1c94> -80003128: 0580006f j 80003180 <_vfprintf_r+0x1ce0> -8000312c: ff0c0c13 addi s8,s8,-16 -80003130: 05895863 bge s2,s8,80003180 <_vfprintf_r+0x1ce0> -80003134: 00812703 lw a4,8(sp) -80003138: 01078793 addi a5,a5,16 -8000313c: 00168693 addi a3,a3,1 -80003140: 00e8a023 sw a4,0(a7) -80003144: 0128a223 sw s2,4(a7) -80003148: 0ef12623 sw a5,236(sp) -8000314c: 0ed12423 sw a3,232(sp) -80003150: 00888893 addi a7,a7,8 -80003154: fcd4dce3 bge s1,a3,8000312c <_vfprintf_r+0x1c8c> -80003158: 0e410613 addi a2,sp,228 -8000315c: 000b0593 mv a1,s6 -80003160: 000d0513 mv a0,s10 -80003164: 68c090ef jal ra,8000c7f0 <__sprint_r> -80003168: 66051463 bnez a0,800037d0 <_vfprintf_r+0x2330> -8000316c: ff0c0c13 addi s8,s8,-16 -80003170: 0ec12783 lw a5,236(sp) -80003174: 0e812683 lw a3,232(sp) -80003178: 10c10893 addi a7,sp,268 -8000317c: fb894ce3 blt s2,s8,80003134 <_vfprintf_r+0x1c94> -80003180: 00812703 lw a4,8(sp) -80003184: 018787b3 add a5,a5,s8 -80003188: 00168693 addi a3,a3,1 -8000318c: 00e8a023 sw a4,0(a7) -80003190: 0188a223 sw s8,4(a7) -80003194: 0ef12623 sw a5,236(sp) -80003198: 0ed12423 sw a3,232(sp) -8000319c: 66d4c063 blt s1,a3,800037fc <_vfprintf_r+0x235c> -800031a0: 00044683 lbu a3,0(s0) -800031a4: 00888893 addi a7,a7,8 -800031a8: 00dd8db3 add s11,s11,a3 -800031ac: f65ff06f j 80003110 <_vfprintf_r+0x1c70> -800031b0: 0e410613 addi a2,sp,228 -800031b4: 000b0593 mv a1,s6 -800031b8: 000d0513 mv a0,s10 -800031bc: 634090ef jal ra,8000c7f0 <__sprint_r> -800031c0: 60051863 bnez a0,800037d0 <_vfprintf_r+0x2330> -800031c4: 0ec12783 lw a5,236(sp) -800031c8: 10c10893 addi a7,sp,268 -800031cc: eedff06f j 800030b8 <_vfprintf_r+0x1c18> -800031d0: 0e410613 addi a2,sp,228 -800031d4: 000b0593 mv a1,s6 -800031d8: 000d0513 mv a0,s10 -800031dc: 614090ef jal ra,8000c7f0 <__sprint_r> -800031e0: 5e051863 bnez a0,800037d0 <_vfprintf_r+0x2330> -800031e4: 00044683 lbu a3,0(s0) -800031e8: 0ec12783 lw a5,236(sp) -800031ec: 10c10893 addi a7,sp,268 -800031f0: f09ff06f j 800030f8 <_vfprintf_r+0x1c58> -800031f4: 04812783 lw a5,72(sp) -800031f8: 04c12583 lw a1,76(sp) -800031fc: 00000913 li s2,0 -80003200: 40f40433 sub s0,s0,a5 -80003204: 00078613 mv a2,a5 -80003208: 00040513 mv a0,s0 -8000320c: 239060ef jal ra,80009c44 -80003210: 001cc583 lbu a1,1(s9) -80003214: 00a00613 li a2,10 -80003218: 00000693 li a3,0 -8000321c: 00b03833 snez a6,a1 -80003220: 00048513 mv a0,s1 -80003224: 00098593 mv a1,s3 -80003228: 010c8cb3 add s9,s9,a6 -8000322c: 1d40d0ef jal ra,80010400 <__udivdi3> -80003230: ae5ff06f j 80002d14 <_vfprintf_r+0x1874> -80003234: 00168693 addi a3,a3,1 -80003238: 00870893 addi a7,a4,8 -8000323c: 00070913 mv s2,a4 -80003240: b98ff06f j 800025d8 <_vfprintf_r+0x1138> -80003244: 0e410613 addi a2,sp,228 -80003248: 000c0593 mv a1,s8 -8000324c: 000d0513 mv a0,s10 -80003250: 5a0090ef jal ra,8000c7f0 <__sprint_r> -80003254: a6051e63 bnez a0,800024d0 <_vfprintf_r+0x1030> -80003258: 0cc12583 lw a1,204(sp) -8000325c: 0ec12783 lw a5,236(sp) -80003260: 10c10893 addi a7,sp,268 -80003264: b5dff06f j 80002dc0 <_vfprintf_r+0x1920> -80003268: 80015737 lui a4,0x80015 -8000326c: c1c70b13 addi s6,a4,-996 # 80014c1c <__BSS_END__+0xffffdfec> -80003270: c75ff06f j 80002ee4 <_vfprintf_r+0x1a44> -80003274: 0e410613 addi a2,sp,228 -80003278: 000c0593 mv a1,s8 -8000327c: 000d0513 mv a0,s10 -80003280: 570090ef jal ra,8000c7f0 <__sprint_r> -80003284: a4051663 bnez a0,800024d0 <_vfprintf_r+0x1030> -80003288: 0ec12783 lw a5,236(sp) -8000328c: 10c10893 addi a7,sp,268 -80003290: cc4ff06f j 80002754 <_vfprintf_r+0x12b4> -80003294: 00600c93 li s9,6 -80003298: 945ff06f j 80002bdc <_vfprintf_r+0x173c> -8000329c: 02012683 lw a3,32(sp) -800032a0: 00db0733 add a4,s6,a3 -800032a4: 409684b3 sub s1,a3,s1 -800032a8: 41b70833 sub a6,a4,s11 -800032ac: 00048913 mv s2,s1 -800032b0: d6985063 bge a6,s1,80002810 <_vfprintf_r+0x1370> -800032b4: 00080913 mv s2,a6 -800032b8: d58ff06f j 80002810 <_vfprintf_r+0x1370> -800032bc: 00c12783 lw a5,12(sp) -800032c0: 00040b13 mv s6,s0 -800032c4: 00f71023 sh a5,0(a4) -800032c8: d28fe06f j 800017f0 <_vfprintf_r+0x350> -800032cc: 01412783 lw a5,20(sp) -800032d0: 00000c93 li s9,0 -800032d4: 00e12a23 sw a4,20(sp) -800032d8: 0007a903 lw s2,0(a5) -800032dc: d91fe06f j 8000206c <_vfprintf_r+0xbcc> -800032e0: 01412783 lw a5,20(sp) -800032e4: 00e12a23 sw a4,20(sp) -800032e8: 0007a903 lw s2,0(a5) -800032ec: 41f95c93 srai s9,s2,0x1f -800032f0: 000c8793 mv a5,s9 -800032f4: df5fe06f j 800020e8 <_vfprintf_r+0xc48> -800032f8: 01412783 lw a5,20(sp) -800032fc: 00000c93 li s9,0 -80003300: 00e12a23 sw a4,20(sp) -80003304: 0007a903 lw s2,0(a5) -80003308: 00100793 li a5,1 -8000330c: c25fe06f j 80001f30 <_vfprintf_r+0xa90> -80003310: 01412783 lw a5,20(sp) -80003314: 00000c93 li s9,0 -80003318: 00e12a23 sw a4,20(sp) -8000331c: 0007a903 lw s2,0(a5) -80003320: 829ff06f j 80002b48 <_vfprintf_r+0x16a8> -80003324: 0e410613 addi a2,sp,228 -80003328: 000c0593 mv a1,s8 -8000332c: 000d0513 mv a0,s10 -80003330: 4c0090ef jal ra,8000c7f0 <__sprint_r> -80003334: cd0fe06f j 80001804 <_vfprintf_r+0x364> -80003338: 02d00793 li a5,45 -8000333c: 0cf103a3 sb a5,199(sp) -80003340: cadff06f j 80002fec <_vfprintf_r+0x1b4c> -80003344: 03000793 li a5,48 -80003348: 0cf10423 sb a5,200(sp) -8000334c: 05800793 li a5,88 -80003350: 002a6713 ori a4,s4,2 -80003354: 0cf104a3 sb a5,201(sp) -80003358: 02e12423 sw a4,40(sp) -8000335c: 06300793 li a5,99 -80003360: 00012823 sw zero,16(sp) -80003364: 14c10b13 addi s6,sp,332 -80003368: 03b7c4e3 blt a5,s11,80003b90 <_vfprintf_r+0x26f0> -8000336c: 0fc12303 lw t1,252(sp) -80003370: fdf4fb93 andi s7,s1,-33 -80003374: 05712223 sw s7,68(sp) -80003378: 04012c23 sw zero,88(sp) -8000337c: 0f012e03 lw t3,240(sp) -80003380: 0f412e83 lw t4,244(sp) -80003384: 0f812f03 lw t5,248(sp) -80003388: 102a6a13 ori s4,s4,258 -8000338c: 44034e63 bltz t1,800037e8 <_vfprintf_r+0x2348> -80003390: 06100793 li a5,97 -80003394: 0af48ee3 beq s1,a5,80003c50 <_vfprintf_r+0x27b0> -80003398: 04100793 li a5,65 -8000339c: 00f48463 beq s1,a5,800033a4 <_vfprintf_r+0x1f04> -800033a0: e64fe06f j 80001a04 <_vfprintf_r+0x564> -800033a4: 0b010a93 addi s5,sp,176 -800033a8: 000a8513 mv a0,s5 -800033ac: 05112a23 sw a7,84(sp) -800033b0: 0bc12823 sw t3,176(sp) -800033b4: 0bd12a23 sw t4,180(sp) -800033b8: 0be12c23 sw t5,184(sp) -800033bc: 0a612e23 sw t1,188(sp) -800033c0: 1f8110ef jal ra,800145b8 <__trunctfdf2> -800033c4: 0cc10613 addi a2,sp,204 -800033c8: 2dc060ef jal ra,800096a4 -800033cc: 00058613 mv a2,a1 -800033d0: 00050593 mv a1,a0 -800033d4: 000a8513 mv a0,s5 -800033d8: 7ed100ef jal ra,800143c4 <__extenddftf2> -800033dc: 0b012783 lw a5,176(sp) -800033e0: 0a010c93 addi s9,sp,160 -800033e4: 09010913 addi s2,sp,144 -800033e8: 08f12823 sw a5,144(sp) -800033ec: 0b412783 lw a5,180(sp) -800033f0: 08010613 addi a2,sp,128 -800033f4: 00090593 mv a1,s2 -800033f8: 08f12a23 sw a5,148(sp) -800033fc: 0b812783 lw a5,184(sp) -80003400: 000c8513 mv a0,s9 -80003404: 04c12023 sw a2,64(sp) -80003408: 08f12c23 sw a5,152(sp) -8000340c: 0bc12783 lw a5,188(sp) -80003410: 08012023 sw zero,128(sp) -80003414: 08012223 sw zero,132(sp) -80003418: 08f12e23 sw a5,156(sp) -8000341c: 3ffc07b7 lui a5,0x3ffc0 -80003420: 08f12623 sw a5,140(sp) -80003424: 08012423 sw zero,136(sp) -80003428: 0150e0ef jal ra,80011c3c <__multf3> -8000342c: 0a012803 lw a6,160(sp) -80003430: 0a412e03 lw t3,164(sp) -80003434: 0a812e83 lw t4,168(sp) -80003438: 0ac12f03 lw t5,172(sp) -8000343c: 000c8593 mv a1,s9 -80003440: 000a8513 mv a0,s5 -80003444: 0b012823 sw a6,176(sp) -80003448: 05012823 sw a6,80(sp) -8000344c: 0bc12a23 sw t3,180(sp) -80003450: 03c12223 sw t3,36(sp) -80003454: 0bd12c23 sw t4,184(sp) -80003458: 03d12023 sw t4,32(sp) -8000345c: 0be12e23 sw t5,188(sp) -80003460: 01e12e23 sw t5,28(sp) -80003464: 0a012023 sw zero,160(sp) -80003468: 0a012223 sw zero,164(sp) -8000346c: 0a012423 sw zero,168(sp) -80003470: 0a012623 sw zero,172(sp) -80003474: 4740e0ef jal ra,800118e8 <__eqtf2> -80003478: 01c12f03 lw t5,28(sp) -8000347c: 02012e83 lw t4,32(sp) -80003480: 02412e03 lw t3,36(sp) -80003484: 05012803 lw a6,80(sp) -80003488: 05412883 lw a7,84(sp) -8000348c: 00051663 bnez a0,80003498 <_vfprintf_r+0x1ff8> -80003490: 00100793 li a5,1 -80003494: 0cf12623 sw a5,204(sp) -80003498: 800157b7 lui a5,0x80015 -8000349c: c4078793 addi a5,a5,-960 # 80014c40 <__BSS_END__+0xffffe010> -800034a0: 02f12223 sw a5,36(sp) -800034a4: fffd8693 addi a3,s11,-1 -800034a8: 05412e23 sw s4,92(sp) -800034ac: 06912223 sw s1,100(sp) -800034b0: 07b12623 sw s11,108(sp) -800034b4: 07a12a23 sw s10,116(sp) -800034b8: 07812c23 sw s8,120(sp) -800034bc: 06812023 sw s0,96(sp) -800034c0: 07312423 sw s3,104(sp) -800034c4: 07112823 sw a7,112(sp) -800034c8: 000b0c13 mv s8,s6 -800034cc: 00068b93 mv s7,a3 -800034d0: 07612e23 sw s6,124(sp) -800034d4: 00080d13 mv s10,a6 -800034d8: 000e0d93 mv s11,t3 -800034dc: 000e8493 mv s1,t4 -800034e0: 000f0a13 mv s4,t5 -800034e4: 0480006f j 8000352c <_vfprintf_r+0x208c> -800034e8: 000c8593 mv a1,s9 -800034ec: 000a8513 mv a0,s5 -800034f0: 02c12023 sw a2,32(sp) -800034f4: 01f12e23 sw t6,28(sp) -800034f8: 0bf12c23 sw t6,184(sp) -800034fc: 0ac12e23 sw a2,188(sp) -80003500: 0b612823 sw s6,176(sp) -80003504: 0b312a23 sw s3,180(sp) -80003508: 0a012023 sw zero,160(sp) -8000350c: 0a012223 sw zero,164(sp) -80003510: 0a012423 sw zero,168(sp) -80003514: 0a012623 sw zero,172(sp) -80003518: 3d00e0ef jal ra,800118e8 <__eqtf2> -8000351c: 01c12f83 lw t6,28(sp) -80003520: 02012603 lw a2,32(sp) -80003524: fffb8b93 addi s7,s7,-1 -80003528: 0e050263 beqz a0,8000360c <_vfprintf_r+0x216c> -8000352c: 400307b7 lui a5,0x40030 -80003530: 00090613 mv a2,s2 -80003534: 000c8593 mv a1,s9 -80003538: 000a8513 mv a0,s5 -8000353c: 08f12e23 sw a5,156(sp) -80003540: 0ba12023 sw s10,160(sp) -80003544: 0bb12223 sw s11,164(sp) -80003548: 0a912423 sw s1,168(sp) -8000354c: 0b412623 sw s4,172(sp) -80003550: 08012823 sw zero,144(sp) -80003554: 08012a23 sw zero,148(sp) -80003558: 08012c23 sw zero,152(sp) -8000355c: 6e00e0ef jal ra,80011c3c <__multf3> -80003560: 000a8513 mv a0,s5 -80003564: 3fd100ef jal ra,80014160 <__fixtfsi> -80003568: 00050593 mv a1,a0 -8000356c: 00050413 mv s0,a0 -80003570: 000a8513 mv a0,s5 -80003574: 0b012983 lw s3,176(sp) -80003578: 0b412483 lw s1,180(sp) -8000357c: 0b812b03 lw s6,184(sp) -80003580: 0bc12a03 lw s4,188(sp) -80003584: 4f1100ef jal ra,80014274 <__floatsitf> -80003588: 0b012703 lw a4,176(sp) -8000358c: 04012603 lw a2,64(sp) -80003590: 00090593 mv a1,s2 -80003594: 08e12023 sw a4,128(sp) -80003598: 0b412703 lw a4,180(sp) -8000359c: 000c8513 mv a0,s9 -800035a0: 09312823 sw s3,144(sp) -800035a4: 08e12223 sw a4,132(sp) -800035a8: 0b812703 lw a4,184(sp) -800035ac: 08912a23 sw s1,148(sp) -800035b0: 09612c23 sw s6,152(sp) -800035b4: 08e12423 sw a4,136(sp) -800035b8: 0bc12703 lw a4,188(sp) -800035bc: 09412e23 sw s4,156(sp) -800035c0: 08e12623 sw a4,140(sp) -800035c4: 67c0f0ef jal ra,80012c40 <__subtf3> -800035c8: 02412783 lw a5,36(sp) -800035cc: 0a012b03 lw s6,160(sp) -800035d0: 0a412983 lw s3,164(sp) -800035d4: 00878733 add a4,a5,s0 -800035d8: 00074703 lbu a4,0(a4) -800035dc: 0a812f83 lw t6,168(sp) -800035e0: 0ac12603 lw a2,172(sp) -800035e4: 05812a23 sw s8,84(sp) -800035e8: 00ec0023 sb a4,0(s8) -800035ec: 05712823 sw s7,80(sp) -800035f0: fff00793 li a5,-1 -800035f4: 001c0c13 addi s8,s8,1 -800035f8: 000b0d13 mv s10,s6 -800035fc: 00098d93 mv s11,s3 -80003600: 000f8493 mv s1,t6 -80003604: 00060a13 mv s4,a2 -80003608: eefb90e3 bne s7,a5,800034e8 <_vfprintf_r+0x2048> -8000360c: 07012883 lw a7,112(sp) -80003610: 000b0393 mv t2,s6 -80003614: 00098293 mv t0,s3 -80003618: 3ffe0937 lui s2,0x3ffe0 -8000361c: 000c8593 mv a1,s9 -80003620: 000a8513 mv a0,s5 -80003624: 03112023 sw a7,32(sp) -80003628: 00812e23 sw s0,28(sp) -8000362c: 05c12a03 lw s4,92(sp) -80003630: 06412483 lw s1,100(sp) -80003634: 06012403 lw s0,96(sp) -80003638: 0a712823 sw t2,176(sp) -8000363c: 06712223 sw t2,100(sp) -80003640: 0a512a23 sw t0,180(sp) -80003644: 06512023 sw t0,96(sp) -80003648: 0bf12c23 sw t6,184(sp) -8000364c: 05f12e23 sw t6,92(sp) -80003650: 0ac12e23 sw a2,188(sp) -80003654: 04c12023 sw a2,64(sp) -80003658: 0a012023 sw zero,160(sp) -8000365c: 0a012223 sw zero,164(sp) -80003660: 0a012423 sw zero,168(sp) -80003664: 0b212623 sw s2,172(sp) -80003668: 34c0e0ef jal ra,800119b4 <__getf2> -8000366c: 000c0b93 mv s7,s8 -80003670: 06c12d83 lw s11,108(sp) -80003674: 07412d03 lw s10,116(sp) -80003678: 07812c03 lw s8,120(sp) -8000367c: 07c12b03 lw s6,124(sp) -80003680: 06812983 lw s3,104(sp) -80003684: 02012883 lw a7,32(sp) -80003688: 48a04263 bgtz a0,80003b0c <_vfprintf_r+0x266c> -8000368c: 06412383 lw t2,100(sp) -80003690: 06012283 lw t0,96(sp) -80003694: 05c12f83 lw t6,92(sp) -80003698: 04012603 lw a2,64(sp) -8000369c: 000c8593 mv a1,s9 -800036a0: 000a8513 mv a0,s5 -800036a4: 0a712823 sw t2,176(sp) -800036a8: 0a512a23 sw t0,180(sp) -800036ac: 0bf12c23 sw t6,184(sp) -800036b0: 0ac12e23 sw a2,188(sp) -800036b4: 0a012023 sw zero,160(sp) -800036b8: 0a012223 sw zero,164(sp) -800036bc: 0a012423 sw zero,168(sp) -800036c0: 0b212623 sw s2,172(sp) -800036c4: 2240e0ef jal ra,800118e8 <__eqtf2> -800036c8: 02012883 lw a7,32(sp) -800036cc: 00051863 bnez a0,800036dc <_vfprintf_r+0x223c> -800036d0: 01c12783 lw a5,28(sp) -800036d4: 0017fc93 andi s9,a5,1 -800036d8: 420c9a63 bnez s9,80003b0c <_vfprintf_r+0x266c> -800036dc: 05012783 lw a5,80(sp) -800036e0: 03000613 li a2,48 -800036e4: 00178693 addi a3,a5,1 # 40030001 <_start-0x3ffcffff> -800036e8: 00db86b3 add a3,s7,a3 -800036ec: 0007c863 bltz a5,800036fc <_vfprintf_r+0x225c> -800036f0: 001b8b93 addi s7,s7,1 -800036f4: fecb8fa3 sb a2,-1(s7) -800036f8: ff769ce3 bne a3,s7,800036f0 <_vfprintf_r+0x2250> -800036fc: 416b87b3 sub a5,s7,s6 -80003700: 02f12023 sw a5,32(sp) -80003704: be8fe06f j 80001aec <_vfprintf_r+0x64c> -80003708: 02012703 lw a4,32(sp) -8000370c: 000b0c13 mv s8,s6 -80003710: 02812b03 lw s6,40(sp) -80003714: 02812e23 sw s0,60(sp) -80003718: 01c12a03 lw s4,28(sp) -8000371c: 00eb06b3 add a3,s6,a4 -80003720: 04012403 lw s0,64(sp) -80003724: 04412983 lw s3,68(sp) -80003728: 02412a83 lw s5,36(sp) -8000372c: 01b6e463 bltu a3,s11,80003734 <_vfprintf_r+0x2294> -80003730: 84cff06f j 8000277c <_vfprintf_r+0x12dc> -80003734: 00068d93 mv s11,a3 -80003738: 844ff06f j 8000277c <_vfprintf_r+0x12dc> -8000373c: 01c12703 lw a4,28(sp) -80003740: ffd00793 li a5,-3 -80003744: 00f74463 blt a4,a5,8000374c <_vfprintf_r+0x22ac> -80003748: 00edda63 bge s11,a4,8000375c <_vfprintf_r+0x22bc> -8000374c: ffe48493 addi s1,s1,-2 -80003750: fdf4f793 andi a5,s1,-33 -80003754: 04f12223 sw a5,68(sp) -80003758: bbcfe06f j 80001b14 <_vfprintf_r+0x674> -8000375c: 02012783 lw a5,32(sp) -80003760: 01c12703 lw a4,28(sp) -80003764: 2af74063 blt a4,a5,80003a04 <_vfprintf_r+0x2564> -80003768: 02812783 lw a5,40(sp) -8000376c: 00070c93 mv s9,a4 -80003770: 0017f793 andi a5,a5,1 -80003774: 00078663 beqz a5,80003780 <_vfprintf_r+0x22e0> -80003778: 02c12783 lw a5,44(sp) -8000377c: 00f70cb3 add s9,a4,a5 -80003780: 02812783 lw a5,40(sp) -80003784: 4007f793 andi a5,a5,1024 -80003788: 00078663 beqz a5,80003794 <_vfprintf_r+0x22f4> -8000378c: 01c12783 lw a5,28(sp) -80003790: 5cf04263 bgtz a5,80003d54 <_vfprintf_r+0x28b4> -80003794: fffcca93 not s5,s9 -80003798: 41fada93 srai s5,s5,0x1f -8000379c: 015cfab3 and s5,s9,s5 -800037a0: 06700493 li s1,103 -800037a4: 02012423 sw zero,40(sp) -800037a8: 02012223 sw zero,36(sp) -800037ac: c84fe06f j 80001c30 <_vfprintf_r+0x790> -800037b0: 0c714783 lbu a5,199(sp) -800037b4: 00000d93 li s11,0 -800037b8: 00078463 beqz a5,800037c0 <_vfprintf_r+0x2320> -800037bc: ec0fe06f j 80001e7c <_vfprintf_r+0x9dc> -800037c0: f19fd06f j 800016d8 <_vfprintf_r+0x238> -800037c4: 00900793 li a5,9 -800037c8: d497e663 bltu a5,s1,80002d14 <_vfprintf_r+0x1874> -800037cc: d90ff06f j 80002d5c <_vfprintf_r+0x18bc> -800037d0: 01012b83 lw s7,16(sp) -800037d4: 000b0c13 mv s8,s6 -800037d8: cfdfe06f j 800024d4 <_vfprintf_r+0x1034> -800037dc: 03412423 sw s4,40(sp) -800037e0: 00012823 sw zero,16(sp) -800037e4: 00090a13 mv s4,s2 -800037e8: 800007b7 lui a5,0x80000 -800037ec: 0067c333 xor t1,a5,t1 -800037f0: 02d00793 li a5,45 -800037f4: 04f12c23 sw a5,88(sp) -800037f8: b99ff06f j 80003390 <_vfprintf_r+0x1ef0> -800037fc: 0e410613 addi a2,sp,228 -80003800: 000b0593 mv a1,s6 -80003804: 000d0513 mv a0,s10 -80003808: 7e9080ef jal ra,8000c7f0 <__sprint_r> -8000380c: fc0512e3 bnez a0,800037d0 <_vfprintf_r+0x2330> -80003810: 00044683 lbu a3,0(s0) -80003814: 0ec12783 lw a5,236(sp) -80003818: 10c10893 addi a7,sp,268 -8000381c: 00dd8db3 add s11,s11,a3 -80003820: 8f1ff06f j 80003110 <_vfprintf_r+0x1c70> -80003824: 0b010a93 addi s5,sp,176 -80003828: 0d010793 addi a5,sp,208 -8000382c: 0dc10813 addi a6,sp,220 -80003830: 0cc10713 addi a4,sp,204 -80003834: 000d8693 mv a3,s11 -80003838: 00200613 li a2,2 -8000383c: 000a8593 mv a1,s5 -80003840: 000d0513 mv a0,s10 -80003844: 0bc12823 sw t3,176(sp) -80003848: 05c12023 sw t3,64(sp) -8000384c: 0bd12a23 sw t4,180(sp) -80003850: 03d12223 sw t4,36(sp) -80003854: 0be12c23 sw t5,184(sp) -80003858: 03e12023 sw t5,32(sp) -8000385c: 0a612e23 sw t1,188(sp) -80003860: 00612e23 sw t1,28(sp) -80003864: 6f1020ef jal ra,80006754 <_ldtoa_r> -80003868: 04700793 li a5,71 -8000386c: 01c12303 lw t1,28(sp) -80003870: 02012f03 lw t5,32(sp) -80003874: 02412e83 lw t4,36(sp) -80003878: 04012e03 lw t3,64(sp) -8000387c: 05012883 lw a7,80(sp) -80003880: 00050b13 mv s6,a0 -80003884: 08fb9063 bne s7,a5,80003904 <_vfprintf_r+0x2464> -80003888: 02812783 lw a5,40(sp) -8000388c: 0017f793 andi a5,a5,1 -80003890: 2e079663 bnez a5,80003b7c <_vfprintf_r+0x26dc> -80003894: 04700793 li a5,71 -80003898: 0dc12703 lw a4,220(sp) -8000389c: 04f12223 sw a5,68(sp) -800038a0: a44fe06f j 80001ae4 <_vfprintf_r+0x644> -800038a4: 0b010a93 addi s5,sp,176 -800038a8: 0dc10813 addi a6,sp,220 -800038ac: 0d010793 addi a5,sp,208 -800038b0: 0cc10713 addi a4,sp,204 -800038b4: 000d8693 mv a3,s11 -800038b8: 00300613 li a2,3 -800038bc: 000a8593 mv a1,s5 -800038c0: 000d0513 mv a0,s10 -800038c4: 05112823 sw a7,80(sp) -800038c8: 0bc12823 sw t3,176(sp) -800038cc: 05c12023 sw t3,64(sp) -800038d0: 0bd12a23 sw t4,180(sp) -800038d4: 03d12223 sw t4,36(sp) -800038d8: 0be12c23 sw t5,184(sp) -800038dc: 03e12023 sw t5,32(sp) -800038e0: 0a612e23 sw t1,188(sp) -800038e4: 00612e23 sw t1,28(sp) -800038e8: 66d020ef jal ra,80006754 <_ldtoa_r> -800038ec: 01c12303 lw t1,28(sp) -800038f0: 02012f03 lw t5,32(sp) -800038f4: 02412e83 lw t4,36(sp) -800038f8: 04012e03 lw t3,64(sp) -800038fc: 05012883 lw a7,80(sp) -80003900: 00050b13 mv s6,a0 -80003904: 04600793 li a5,70 -80003908: 01bb0933 add s2,s6,s11 -8000390c: 26fb9e63 bne s7,a5,80003b88 <_vfprintf_r+0x26e8> -80003910: 000b4683 lbu a3,0(s6) -80003914: 03000793 li a5,48 -80003918: 50f68663 beq a3,a5,80003e24 <_vfprintf_r+0x2984> -8000391c: 0a010c93 addi s9,sp,160 -80003920: 0cc12783 lw a5,204(sp) -80003924: 00f90933 add s2,s2,a5 -80003928: 960fe06f j 80001a88 <_vfprintf_r+0x5e8> -8000392c: 02d00793 li a5,45 -80003930: 0cf103a3 sb a5,199(sp) -80003934: da0ff06f j 80002ed4 <_vfprintf_r+0x1a34> -80003938: 0e410613 addi a2,sp,228 -8000393c: 000c0593 mv a1,s8 -80003940: 000d0513 mv a0,s10 -80003944: 6ad080ef jal ra,8000c7f0 <__sprint_r> -80003948: 00050463 beqz a0,80003950 <_vfprintf_r+0x24b0> -8000394c: b85fe06f j 800024d0 <_vfprintf_r+0x1030> -80003950: 0cc12483 lw s1,204(sp) -80003954: 0ec12783 lw a5,236(sp) -80003958: 10c10893 addi a7,sp,268 -8000395c: e69fe06f j 800027c4 <_vfprintf_r+0x1324> -80003960: 0c714783 lbu a5,199(sp) -80003964: 01212a23 sw s2,20(sp) -80003968: 02012423 sw zero,40(sp) -8000396c: 02012223 sw zero,36(sp) -80003970: 00012e23 sw zero,28(sp) -80003974: 000d8a93 mv s5,s11 -80003978: 000d8c93 mv s9,s11 -8000397c: 00000d93 li s11,0 -80003980: 00078463 beqz a5,80003988 <_vfprintf_r+0x24e8> -80003984: cf8fe06f j 80001e7c <_vfprintf_r+0x9dc> -80003988: d51fd06f j 800016d8 <_vfprintf_r+0x238> -8000398c: 02812783 lw a5,40(sp) -80003990: 01c12703 lw a4,28(sp) -80003994: 0017f793 andi a5,a5,1 -80003998: 01b7e7b3 or a5,a5,s11 -8000399c: 50e05663 blez a4,80003ea8 <_vfprintf_r+0x2a08> -800039a0: 44079063 bnez a5,80003de0 <_vfprintf_r+0x2940> -800039a4: 01c12c83 lw s9,28(sp) -800039a8: 06600493 li s1,102 -800039ac: 02812783 lw a5,40(sp) -800039b0: 4007f793 andi a5,a5,1024 -800039b4: 3a079263 bnez a5,80003d58 <_vfprintf_r+0x28b8> -800039b8: fffcca93 not s5,s9 -800039bc: 41fada93 srai s5,s5,0x1f -800039c0: 015cfab3 and s5,s9,s5 -800039c4: de1ff06f j 800037a4 <_vfprintf_r+0x2304> -800039c8: 80015737 lui a4,0x80015 -800039cc: c2470b13 addi s6,a4,-988 # 80014c24 <__BSS_END__+0xffffdff4> -800039d0: d14ff06f j 80002ee4 <_vfprintf_r+0x1a44> -800039d4: 0e410613 addi a2,sp,228 -800039d8: 000c0593 mv a1,s8 -800039dc: 000d0513 mv a0,s10 -800039e0: 611080ef jal ra,8000c7f0 <__sprint_r> -800039e4: 00050463 beqz a0,800039ec <_vfprintf_r+0x254c> -800039e8: ae9fe06f j 800024d0 <_vfprintf_r+0x1030> -800039ec: 0cc12483 lw s1,204(sp) -800039f0: 02012703 lw a4,32(sp) -800039f4: 0ec12783 lw a5,236(sp) -800039f8: 10c10893 addi a7,sp,268 -800039fc: 409704b3 sub s1,a4,s1 -80003a00: e11fe06f j 80002810 <_vfprintf_r+0x1370> -80003a04: 02012783 lw a5,32(sp) -80003a08: 02c12703 lw a4,44(sp) -80003a0c: 06700493 li s1,103 -80003a10: 00e78cb3 add s9,a5,a4 -80003a14: 01c12783 lw a5,28(sp) -80003a18: f8f04ae3 bgtz a5,800039ac <_vfprintf_r+0x250c> -80003a1c: 40fc8cb3 sub s9,s9,a5 -80003a20: 001c8c93 addi s9,s9,1 -80003a24: fffcca93 not s5,s9 -80003a28: 41fada93 srai s5,s5,0x1f -80003a2c: 015cfab3 and s5,s9,s5 -80003a30: d75ff06f j 800037a4 <_vfprintf_r+0x2304> -80003a34: 800156b7 lui a3,0x80015 -80003a38: dcc68e93 addi t4,a3,-564 # 80014dcc <__BSS_END__+0xffffe19c> -80003a3c: b50fe06f j 80001d8c <_vfprintf_r+0x8ec> -80003a40: fff00793 li a5,-1 -80003a44: 00f12623 sw a5,12(sp) -80003a48: dcdfd06f j 80001814 <_vfprintf_r+0x374> -80003a4c: ff000613 li a2,-16 -80003a50: 40b004b3 neg s1,a1 -80003a54: 06c5d263 bge a1,a2,80003ab8 <_vfprintf_r+0x2618> -80003a58: 01000913 li s2,16 -80003a5c: 00700c93 li s9,7 -80003a60: 00c0006f j 80003a6c <_vfprintf_r+0x25cc> -80003a64: ff048493 addi s1,s1,-16 -80003a68: 04995863 bge s2,s1,80003ab8 <_vfprintf_r+0x2618> -80003a6c: 00812703 lw a4,8(sp) -80003a70: 01078793 addi a5,a5,16 # 80000010 <__BSS_END__+0xfffe93e0> -80003a74: 00168693 addi a3,a3,1 -80003a78: 00e8a023 sw a4,0(a7) -80003a7c: 0128a223 sw s2,4(a7) -80003a80: 0ef12623 sw a5,236(sp) -80003a84: 0ed12423 sw a3,232(sp) -80003a88: 00888893 addi a7,a7,8 -80003a8c: fcdcdce3 bge s9,a3,80003a64 <_vfprintf_r+0x25c4> -80003a90: 0e410613 addi a2,sp,228 -80003a94: 000c0593 mv a1,s8 -80003a98: 000d0513 mv a0,s10 -80003a9c: 555080ef jal ra,8000c7f0 <__sprint_r> -80003aa0: 00050463 beqz a0,80003aa8 <_vfprintf_r+0x2608> -80003aa4: a2dfe06f j 800024d0 <_vfprintf_r+0x1030> -80003aa8: 0ec12783 lw a5,236(sp) -80003aac: 0e812683 lw a3,232(sp) -80003ab0: 10c10893 addi a7,sp,268 -80003ab4: fb1ff06f j 80003a64 <_vfprintf_r+0x25c4> -80003ab8: 00812703 lw a4,8(sp) -80003abc: 009787b3 add a5,a5,s1 -80003ac0: 00168693 addi a3,a3,1 -80003ac4: 00e8a023 sw a4,0(a7) -80003ac8: 0098a223 sw s1,4(a7) -80003acc: 0ef12623 sw a5,236(sp) -80003ad0: 0ed12423 sw a3,232(sp) -80003ad4: 00700613 li a2,7 -80003ad8: b2d65a63 bge a2,a3,80002e0c <_vfprintf_r+0x196c> -80003adc: 0e410613 addi a2,sp,228 -80003ae0: 000c0593 mv a1,s8 -80003ae4: 000d0513 mv a0,s10 -80003ae8: 509080ef jal ra,8000c7f0 <__sprint_r> -80003aec: 00050463 beqz a0,80003af4 <_vfprintf_r+0x2654> -80003af0: 9e1fe06f j 800024d0 <_vfprintf_r+0x1030> -80003af4: 0ec12783 lw a5,236(sp) -80003af8: 0e812683 lw a3,232(sp) -80003afc: 10c10893 addi a7,sp,268 -80003b00: 9ccfe06f j 80001ccc <_vfprintf_r+0x82c> -80003b04: 000a0b93 mv s7,s4 -80003b08: e20fe06f j 80002128 <_vfprintf_r+0xc88> -80003b0c: 05412783 lw a5,84(sp) -80003b10: 000b8693 mv a3,s7 -80003b14: 0cf12e23 sw a5,220(sp) -80003b18: 02412783 lw a5,36(sp) -80003b1c: fffbc603 lbu a2,-1(s7) -80003b20: 00f7c583 lbu a1,15(a5) -80003b24: 02b61063 bne a2,a1,80003b44 <_vfprintf_r+0x26a4> -80003b28: 03000513 li a0,48 -80003b2c: fea68fa3 sb a0,-1(a3) -80003b30: 0dc12683 lw a3,220(sp) -80003b34: fff68793 addi a5,a3,-1 -80003b38: 0cf12e23 sw a5,220(sp) -80003b3c: fff6c603 lbu a2,-1(a3) -80003b40: fec586e3 beq a1,a2,80003b2c <_vfprintf_r+0x268c> -80003b44: 00160593 addi a1,a2,1 -80003b48: 03900513 li a0,57 -80003b4c: 0ff5f593 andi a1,a1,255 -80003b50: 00a60663 beq a2,a0,80003b5c <_vfprintf_r+0x26bc> -80003b54: feb68fa3 sb a1,-1(a3) -80003b58: ba5ff06f j 800036fc <_vfprintf_r+0x225c> -80003b5c: 02412783 lw a5,36(sp) -80003b60: 00a7c583 lbu a1,10(a5) -80003b64: feb68fa3 sb a1,-1(a3) -80003b68: b95ff06f j 800036fc <_vfprintf_r+0x225c> -80003b6c: 03000793 li a5,48 -80003b70: 0cf10423 sb a5,200(sp) -80003b74: 07800793 li a5,120 -80003b78: fd8ff06f j 80003350 <_vfprintf_r+0x1eb0> -80003b7c: 04700793 li a5,71 -80003b80: 01bb0933 add s2,s6,s11 -80003b84: 04f12223 sw a5,68(sp) -80003b88: 0a010c93 addi s9,sp,160 -80003b8c: efdfd06f j 80001a88 <_vfprintf_r+0x5e8> -80003b90: 001d8593 addi a1,s11,1 -80003b94: 000d0513 mv a0,s10 -80003b98: 01112823 sw a7,16(sp) -80003b9c: 154040ef jal ra,80007cf0 <_malloc_r> -80003ba0: 01012883 lw a7,16(sp) -80003ba4: 00050b13 mv s6,a0 -80003ba8: 36050063 beqz a0,80003f08 <_vfprintf_r+0x2a68> -80003bac: 00a12823 sw a0,16(sp) -80003bb0: fbcff06f j 8000336c <_vfprintf_r+0x1ecc> -80003bb4: 000d9463 bnez s11,80003bbc <_vfprintf_r+0x271c> -80003bb8: 00100d93 li s11,1 -80003bbc: 0fc12303 lw t1,252(sp) -80003bc0: 0f012e03 lw t3,240(sp) -80003bc4: 0f412e83 lw t4,244(sp) -80003bc8: 0f812f03 lw t5,248(sp) -80003bcc: 100a6913 ori s2,s4,256 -80003bd0: c00346e3 bltz t1,800037dc <_vfprintf_r+0x233c> -80003bd4: 0b010a93 addi s5,sp,176 -80003bd8: 0dc10813 addi a6,sp,220 -80003bdc: 0d010793 addi a5,sp,208 -80003be0: 0cc10713 addi a4,sp,204 -80003be4: 000d8693 mv a3,s11 -80003be8: 00200613 li a2,2 -80003bec: 000a8593 mv a1,s5 -80003bf0: 000d0513 mv a0,s10 -80003bf4: 05112223 sw a7,68(sp) -80003bf8: 0bc12823 sw t3,176(sp) -80003bfc: 05c12023 sw t3,64(sp) -80003c00: 0bd12a23 sw t4,180(sp) -80003c04: 03d12223 sw t4,36(sp) -80003c08: 0be12c23 sw t5,184(sp) -80003c0c: 03e12023 sw t5,32(sp) -80003c10: 0a612e23 sw t1,188(sp) -80003c14: 00612e23 sw t1,28(sp) -80003c18: 33d020ef jal ra,80006754 <_ldtoa_r> -80003c1c: 01c12303 lw t1,28(sp) -80003c20: 03412423 sw s4,40(sp) -80003c24: 02012f03 lw t5,32(sp) -80003c28: 02412e83 lw t4,36(sp) -80003c2c: 04012e03 lw t3,64(sp) -80003c30: 04412883 lw a7,68(sp) -80003c34: 00050b13 mv s6,a0 -80003c38: 00090a13 mv s4,s2 -80003c3c: 04012c23 sw zero,88(sp) -80003c40: 00012823 sw zero,16(sp) -80003c44: c45ff06f j 80003888 <_vfprintf_r+0x23e8> -80003c48: 00600d93 li s11,6 -80003c4c: d8dfd06f j 800019d8 <_vfprintf_r+0x538> -80003c50: 0b010a93 addi s5,sp,176 -80003c54: 000a8513 mv a0,s5 -80003c58: 05112a23 sw a7,84(sp) -80003c5c: 0bc12823 sw t3,176(sp) -80003c60: 0bd12a23 sw t4,180(sp) -80003c64: 0be12c23 sw t5,184(sp) -80003c68: 0a612e23 sw t1,188(sp) -80003c6c: 14d100ef jal ra,800145b8 <__trunctfdf2> -80003c70: 0cc10613 addi a2,sp,204 -80003c74: 231050ef jal ra,800096a4 -80003c78: 00058613 mv a2,a1 -80003c7c: 00050593 mv a1,a0 -80003c80: 000a8513 mv a0,s5 -80003c84: 740100ef jal ra,800143c4 <__extenddftf2> -80003c88: 0b012783 lw a5,176(sp) -80003c8c: 0a010c93 addi s9,sp,160 -80003c90: 09010913 addi s2,sp,144 -80003c94: 08f12823 sw a5,144(sp) -80003c98: 0b412783 lw a5,180(sp) -80003c9c: 08010613 addi a2,sp,128 -80003ca0: 00090593 mv a1,s2 -80003ca4: 08f12a23 sw a5,148(sp) -80003ca8: 0b812783 lw a5,184(sp) -80003cac: 000c8513 mv a0,s9 -80003cb0: 04c12023 sw a2,64(sp) -80003cb4: 08f12c23 sw a5,152(sp) -80003cb8: 0bc12783 lw a5,188(sp) -80003cbc: 08012023 sw zero,128(sp) -80003cc0: 08012223 sw zero,132(sp) -80003cc4: 08f12e23 sw a5,156(sp) -80003cc8: 3ffc07b7 lui a5,0x3ffc0 -80003ccc: 08f12623 sw a5,140(sp) -80003cd0: 08012423 sw zero,136(sp) -80003cd4: 7690d0ef jal ra,80011c3c <__multf3> -80003cd8: 0a012803 lw a6,160(sp) -80003cdc: 0a412e03 lw t3,164(sp) -80003ce0: 0a812e83 lw t4,168(sp) -80003ce4: 0ac12f03 lw t5,172(sp) -80003ce8: 000c8593 mv a1,s9 -80003cec: 000a8513 mv a0,s5 -80003cf0: 0b012823 sw a6,176(sp) -80003cf4: 05012823 sw a6,80(sp) -80003cf8: 0bc12a23 sw t3,180(sp) -80003cfc: 03c12223 sw t3,36(sp) -80003d00: 0bd12c23 sw t4,184(sp) -80003d04: 03d12023 sw t4,32(sp) -80003d08: 0be12e23 sw t5,188(sp) -80003d0c: 01e12e23 sw t5,28(sp) -80003d10: 0a012023 sw zero,160(sp) -80003d14: 0a012223 sw zero,164(sp) -80003d18: 0a012423 sw zero,168(sp) -80003d1c: 0a012623 sw zero,172(sp) -80003d20: 3c90d0ef jal ra,800118e8 <__eqtf2> -80003d24: 01c12f03 lw t5,28(sp) -80003d28: 02012e83 lw t4,32(sp) -80003d2c: 02412e03 lw t3,36(sp) -80003d30: 05012803 lw a6,80(sp) -80003d34: 05412883 lw a7,84(sp) -80003d38: 00051663 bnez a0,80003d44 <_vfprintf_r+0x28a4> -80003d3c: 00100793 li a5,1 -80003d40: 0cf12623 sw a5,204(sp) -80003d44: 800157b7 lui a5,0x80015 -80003d48: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -80003d4c: 02f12223 sw a5,36(sp) -80003d50: f54ff06f j 800034a4 <_vfprintf_r+0x2004> -80003d54: 06700493 li s1,103 -80003d58: 03c12603 lw a2,60(sp) -80003d5c: 0ff00693 li a3,255 -80003d60: 00064783 lbu a5,0(a2) -80003d64: 1ad78a63 beq a5,a3,80003f18 <_vfprintf_r+0x2a78> -80003d68: 01c12703 lw a4,28(sp) -80003d6c: 00000513 li a0,0 -80003d70: 00000593 li a1,0 -80003d74: 00e7de63 bge a5,a4,80003d90 <_vfprintf_r+0x28f0> -80003d78: 40f70733 sub a4,a4,a5 -80003d7c: 00164783 lbu a5,1(a2) -80003d80: 04078463 beqz a5,80003dc8 <_vfprintf_r+0x2928> -80003d84: 00158593 addi a1,a1,1 -80003d88: 00160613 addi a2,a2,1 -80003d8c: fed794e3 bne a5,a3,80003d74 <_vfprintf_r+0x28d4> -80003d90: 02c12e23 sw a2,60(sp) -80003d94: 00e12e23 sw a4,28(sp) -80003d98: 02b12223 sw a1,36(sp) -80003d9c: 02a12423 sw a0,40(sp) -80003da0: 02812703 lw a4,40(sp) -80003da4: 02412783 lw a5,36(sp) -80003da8: 00e787b3 add a5,a5,a4 -80003dac: 04812703 lw a4,72(sp) -80003db0: 02e787b3 mul a5,a5,a4 -80003db4: 01978cb3 add s9,a5,s9 -80003db8: fffcca93 not s5,s9 -80003dbc: 41fada93 srai s5,s5,0x1f -80003dc0: 015cfab3 and s5,s9,s5 -80003dc4: e6dfd06f j 80001c30 <_vfprintf_r+0x790> -80003dc8: 00064783 lbu a5,0(a2) -80003dcc: 00150513 addi a0,a0,1 -80003dd0: fbdff06f j 80003d8c <_vfprintf_r+0x28ec> -80003dd4: 00012823 sw zero,16(sp) -80003dd8: 00078a13 mv s4,a5 -80003ddc: a0dff06f j 800037e8 <_vfprintf_r+0x2348> -80003de0: 02c12783 lw a5,44(sp) -80003de4: 06600493 li s1,102 -80003de8: 00f70cb3 add s9,a4,a5 -80003dec: 01bc8cb3 add s9,s9,s11 -80003df0: bbdff06f j 800039ac <_vfprintf_r+0x250c> -80003df4: 0d610693 addi a3,sp,214 -80003df8: 00061863 bnez a2,80003e08 <_vfprintf_r+0x2968> -80003dfc: 03000693 li a3,48 -80003e00: 0cd10b23 sb a3,214(sp) -80003e04: 0d710693 addi a3,sp,215 -80003e08: 1b010713 addi a4,sp,432 -80003e0c: 03078793 addi a5,a5,48 -80003e10: 40e68633 sub a2,a3,a4 -80003e14: 00f68023 sb a5,0(a3) -80003e18: 0dd60793 addi a5,a2,221 -80003e1c: 02f12c23 sw a5,56(sp) -80003e20: dcdfd06f j 80001bec <_vfprintf_r+0x74c> -80003e24: 0a010c93 addi s9,sp,160 -80003e28: 000c8593 mv a1,s9 -80003e2c: 000a8513 mv a0,s5 -80003e30: 05112823 sw a7,80(sp) -80003e34: 0bc12823 sw t3,176(sp) -80003e38: 05c12023 sw t3,64(sp) -80003e3c: 0bd12a23 sw t4,180(sp) -80003e40: 03d12223 sw t4,36(sp) -80003e44: 0be12c23 sw t5,184(sp) -80003e48: 03e12023 sw t5,32(sp) -80003e4c: 0a612e23 sw t1,188(sp) -80003e50: 00612e23 sw t1,28(sp) -80003e54: 0a012023 sw zero,160(sp) -80003e58: 0a012223 sw zero,164(sp) -80003e5c: 0a012423 sw zero,168(sp) -80003e60: 0a012623 sw zero,172(sp) -80003e64: 2850d0ef jal ra,800118e8 <__eqtf2> -80003e68: 01c12303 lw t1,28(sp) -80003e6c: 02012f03 lw t5,32(sp) -80003e70: 02412e83 lw t4,36(sp) -80003e74: 04012e03 lw t3,64(sp) -80003e78: 05012883 lw a7,80(sp) -80003e7c: aa0502e3 beqz a0,80003920 <_vfprintf_r+0x2480> -80003e80: 00100793 li a5,1 -80003e84: 41b787b3 sub a5,a5,s11 -80003e88: 0cf12623 sw a5,204(sp) -80003e8c: 00f90933 add s2,s2,a5 -80003e90: bf9fd06f j 80001a88 <_vfprintf_r+0x5e8> -80003e94: 02812783 lw a5,40(sp) -80003e98: 0017f793 andi a5,a5,1 -80003e9c: 00079463 bnez a5,80003ea4 <_vfprintf_r+0x2a04> -80003ea0: d6dfd06f j 80001c0c <_vfprintf_r+0x76c> -80003ea4: d61fd06f j 80001c04 <_vfprintf_r+0x764> -80003ea8: 00079a63 bnez a5,80003ebc <_vfprintf_r+0x2a1c> -80003eac: 00100a93 li s5,1 -80003eb0: 06600493 li s1,102 -80003eb4: 00100c93 li s9,1 -80003eb8: 8edff06f j 800037a4 <_vfprintf_r+0x2304> -80003ebc: 02c12783 lw a5,44(sp) -80003ec0: 06600493 li s1,102 -80003ec4: 00178c93 addi s9,a5,1 -80003ec8: 01bc8cb3 add s9,s9,s11 -80003ecc: fffcca93 not s5,s9 -80003ed0: 41fada93 srai s5,s5,0x1f -80003ed4: 015cfab3 and s5,s9,s5 -80003ed8: 8cdff06f j 800037a4 <_vfprintf_r+0x2304> -80003edc: 00088713 mv a4,a7 -80003ee0: bddfe06f j 80002abc <_vfprintf_r+0x161c> -80003ee4: 01412783 lw a5,20(sp) -80003ee8: 0007ad83 lw s11,0(a5) -80003eec: 00478793 addi a5,a5,4 -80003ef0: 000dd463 bgez s11,80003ef8 <_vfprintf_r+0x2a58> -80003ef4: fff00d93 li s11,-1 -80003ef8: 00144483 lbu s1,1(s0) -80003efc: 00f12a23 sw a5,20(sp) -80003f00: 00070413 mv s0,a4 -80003f04: f54fd06f j 80001658 <_vfprintf_r+0x1b8> -80003f08: 00cc5783 lhu a5,12(s8) -80003f0c: 0407e793 ori a5,a5,64 -80003f10: 00fc1623 sh a5,12(s8) -80003f14: 8f1fd06f j 80001804 <_vfprintf_r+0x364> -80003f18: 02012423 sw zero,40(sp) -80003f1c: 02012223 sw zero,36(sp) -80003f20: e81ff06f j 80003da0 <_vfprintf_r+0x2900> -80003f24: 00200793 li a5,2 -80003f28: 02f12c23 sw a5,56(sp) -80003f2c: cc1fd06f j 80001bec <_vfprintf_r+0x74c> +800026c8: 32d642e3 blt a2,a3,800031ec <_vfprintf_r+0x1dd4> +800026cc: fff4c693 not a3,s1 +800026d0: 01c12703 lw a4,28(sp) +800026d4: 41f6d693 srai a3,a3,0x1f +800026d8: 00d4f4b3 and s1,s1,a3 +800026dc: 409704b3 sub s1,a4,s1 +800026e0: 48904463 bgtz s1,80002b68 <_vfprintf_r+0x1750> +800026e4: 01c12703 lw a4,28(sp) +800026e8: 400a7693 andi a3,s4,1024 +800026ec: 00eb0db3 add s11,s6,a4 +800026f0: 0c0698e3 bnez a3,80002fc0 <_vfprintf_r+0x1ba8> +800026f4: 0cc12483 lw s1,204(sp) +800026f8: 02012703 lw a4,32(sp) +800026fc: 00e4c663 blt s1,a4,80002708 <_vfprintf_r+0x12f0> +80002700: 001a7693 andi a3,s4,1 +80002704: 300688e3 beqz a3,80003214 <_vfprintf_r+0x1dfc> +80002708: 03012683 lw a3,48(sp) +8000270c: 02c12703 lw a4,44(sp) +80002710: 00700613 li a2,7 +80002714: 00d8a023 sw a3,0(a7) +80002718: 0e812683 lw a3,232(sp) +8000271c: 00e787b3 add a5,a5,a4 +80002720: 00e8a223 sw a4,4(a7) +80002724: 00168693 addi a3,a3,1 +80002728: 0ef12623 sw a5,236(sp) +8000272c: 0ed12423 sw a3,232(sp) +80002730: 00888893 addi a7,a7,8 +80002734: 00d65463 bge a2,a3,8000273c <_vfprintf_r+0x1324> +80002738: 1780106f j 800038b0 <_vfprintf_r+0x2498> +8000273c: 02012683 lw a3,32(sp) +80002740: 00db0733 add a4,s6,a3 +80002744: 409684b3 sub s1,a3,s1 +80002748: 41b70733 sub a4,a4,s11 +8000274c: 00048913 mv s2,s1 +80002750: 00975463 bge a4,s1,80002758 <_vfprintf_r+0x1340> +80002754: 00070913 mv s2,a4 +80002758: 03205863 blez s2,80002788 <_vfprintf_r+0x1370> +8000275c: 0e812703 lw a4,232(sp) +80002760: 012787b3 add a5,a5,s2 +80002764: 01b8a023 sw s11,0(a7) +80002768: 00170713 addi a4,a4,1 +8000276c: 0128a223 sw s2,4(a7) +80002770: 0ef12623 sw a5,236(sp) +80002774: 0ee12423 sw a4,232(sp) +80002778: 00700693 li a3,7 +8000277c: 00888893 addi a7,a7,8 +80002780: 00e6d463 bge a3,a4,80002788 <_vfprintf_r+0x1370> +80002784: 1c80106f j 8000394c <_vfprintf_r+0x2534> +80002788: fff94713 not a4,s2 +8000278c: 41f75713 srai a4,a4,0x1f +80002790: 00e97733 and a4,s2,a4 +80002794: 40e484b3 sub s1,s1,a4 +80002798: 00904463 bgtz s1,800027a0 <_vfprintf_r+0x1388> +8000279c: f85fe06f j 80001720 <_vfprintf_r+0x308> +800027a0: 01000693 li a3,16 +800027a4: 0e812703 lw a4,232(sp) +800027a8: 6296d863 bge a3,s1,80002dd8 <_vfprintf_r+0x19c0> +800027ac: 01000913 li s2,16 +800027b0: 00700c93 li s9,7 +800027b4: 00c0006f j 800027c0 <_vfprintf_r+0x13a8> +800027b8: ff048493 addi s1,s1,-16 +800027bc: 60995e63 bge s2,s1,80002dd8 <_vfprintf_r+0x19c0> +800027c0: 00812683 lw a3,8(sp) +800027c4: 01078793 addi a5,a5,16 +800027c8: 00170713 addi a4,a4,1 +800027cc: 00d8a023 sw a3,0(a7) +800027d0: 0128a223 sw s2,4(a7) +800027d4: 0ef12623 sw a5,236(sp) +800027d8: 0ee12423 sw a4,232(sp) +800027dc: 00888893 addi a7,a7,8 +800027e0: fcecdce3 bge s9,a4,800027b8 <_vfprintf_r+0x13a0> +800027e4: 0e410613 addi a2,sp,228 +800027e8: 000c0593 mv a1,s8 +800027ec: 000d0513 mv a0,s10 +800027f0: 5a9090ef jal ra,8000c598 <__sprint_r> +800027f4: c4051ae3 bnez a0,80002448 <_vfprintf_r+0x1030> +800027f8: 0ec12783 lw a5,236(sp) +800027fc: 0e812703 lw a4,232(sp) +80002800: 10c10893 addi a7,sp,268 +80002804: fb5ff06f j 800027b8 <_vfprintf_r+0x13a0> +80002808: 001a7793 andi a5,s4,1 +8000280c: c6079ae3 bnez a5,80002480 <_vfprintf_r+0x1068> +80002810: 00c8a223 sw a2,4(a7) +80002814: 0f912623 sw s9,236(sp) +80002818: 0e912423 sw s1,232(sp) +8000281c: 00700793 li a5,7 +80002820: 2297ca63 blt a5,s1,80002a54 <_vfprintf_r+0x163c> +80002824: 00268693 addi a3,a3,2 +80002828: 01088893 addi a7,a7,16 +8000282c: d25ff06f j 80002550 <_vfprintf_r+0x1138> +80002830: d3b050e3 blez s11,80002550 <_vfprintf_r+0x1138> +80002834: 01000713 li a4,16 +80002838: 01b74463 blt a4,s11,80002840 <_vfprintf_r+0x1428> +8000283c: 6180106f j 80003e54 <_vfprintf_r+0x2a3c> +80002840: 00700b13 li s6,7 +80002844: 00060493 mv s1,a2 +80002848: 0100006f j 80002858 <_vfprintf_r+0x1440> +8000284c: ff0d8d93 addi s11,s11,-16 +80002850: 1db75e63 bge a4,s11,80002a2c <_vfprintf_r+0x1614> +80002854: 00148493 addi s1,s1,1 +80002858: 00812783 lw a5,8(sp) +8000285c: 010c8c93 addi s9,s9,16 +80002860: 00e92223 sw a4,4(s2) +80002864: 00f92023 sw a5,0(s2) +80002868: 0f912623 sw s9,236(sp) +8000286c: 0e912423 sw s1,232(sp) +80002870: 00890913 addi s2,s2,8 +80002874: fc9b5ce3 bge s6,s1,8000284c <_vfprintf_r+0x1434> +80002878: 0e410613 addi a2,sp,228 +8000287c: 000c0593 mv a1,s8 +80002880: 000d0513 mv a0,s10 +80002884: 515090ef jal ra,8000c598 <__sprint_r> +80002888: bc0510e3 bnez a0,80002448 <_vfprintf_r+0x1030> +8000288c: 0ec12c83 lw s9,236(sp) +80002890: 0e812483 lw s1,232(sp) +80002894: 10c10913 addi s2,sp,268 +80002898: 01000713 li a4,16 +8000289c: fb1ff06f j 8000284c <_vfprintf_r+0x1434> +800028a0: 01412683 lw a3,20(sp) +800028a4: 010a7793 andi a5,s4,16 +800028a8: 00468713 addi a4,a3,4 +800028ac: 16079263 bnez a5,80002a10 <_vfprintf_r+0x15f8> +800028b0: 040a7793 andi a5,s4,64 +800028b4: 68078463 beqz a5,80002f3c <_vfprintf_r+0x1b24> +800028b8: 01412783 lw a5,20(sp) +800028bc: 00000c93 li s9,0 +800028c0: 00e12a23 sw a4,20(sp) +800028c4: 0007d903 lhu s2,0(a5) +800028c8: f1cff06f j 80001fe4 <_vfprintf_r+0xbcc> +800028cc: 01412683 lw a3,20(sp) +800028d0: 010bf793 andi a5,s7,16 +800028d4: 00468713 addi a4,a3,4 +800028d8: 0c079e63 bnez a5,800029b4 <_vfprintf_r+0x159c> +800028dc: 040bf793 andi a5,s7,64 +800028e0: 60078e63 beqz a5,80002efc <_vfprintf_r+0x1ae4> +800028e4: 01412783 lw a5,20(sp) +800028e8: 00000c93 li s9,0 +800028ec: 00e12a23 sw a4,20(sp) +800028f0: 0007d903 lhu s2,0(a5) +800028f4: 00100793 li a5,1 +800028f8: db0ff06f j 80001ea8 <_vfprintf_r+0xa90> +800028fc: 01412683 lw a3,20(sp) +80002900: 010a7793 andi a5,s4,16 +80002904: 00468713 addi a4,a3,4 +80002908: 0e079a63 bnez a5,800029fc <_vfprintf_r+0x15e4> +8000290c: 040a7793 andi a5,s4,64 +80002910: 60078663 beqz a5,80002f1c <_vfprintf_r+0x1b04> +80002914: 01412783 lw a5,20(sp) +80002918: 00e12a23 sw a4,20(sp) +8000291c: 00079903 lh s2,0(a5) +80002920: 41f95c93 srai s9,s2,0x1f +80002924: 000c8793 mv a5,s9 +80002928: f207de63 bgez a5,80002064 <_vfprintf_r+0xc4c> +8000292c: 012037b3 snez a5,s2 +80002930: 41900cb3 neg s9,s9 +80002934: 40fc8cb3 sub s9,s9,a5 +80002938: 02d00793 li a5,45 +8000293c: 0cf103a3 sb a5,199(sp) +80002940: 41200933 neg s2,s2 +80002944: 000a0b93 mv s7,s4 +80002948: 00100793 li a5,1 +8000294c: d60ff06f j 80001eac <_vfprintf_r+0xa94> +80002950: 001a7713 andi a4,s4,1 +80002954: 00071463 bnez a4,8000295c <_vfprintf_r+0x1544> +80002958: dc9fe06f j 80001720 <_vfprintf_r+0x308> +8000295c: 8c1ff06f j 8000221c <_vfprintf_r+0xe04> +80002960: 000c8893 mv a7,s9 +80002964: ed4ff06f j 80002038 <_vfprintf_r+0xc20> +80002968: 03000793 li a5,48 +8000296c: 1af107a3 sb a5,431(sp) +80002970: 1af10b13 addi s6,sp,431 +80002974: d60ff06f j 80001ed4 <_vfprintf_r+0xabc> +80002978: 03c12783 lw a5,60(sp) +8000297c: 00044483 lbu s1,0(s0) +80002980: 00079463 bnez a5,80002988 <_vfprintf_r+0x1570> +80002984: c4dfe06f j 800015d0 <_vfprintf_r+0x1b8> +80002988: 0007c783 lbu a5,0(a5) +8000298c: 00079463 bnez a5,80002994 <_vfprintf_r+0x157c> +80002990: c41fe06f j 800015d0 <_vfprintf_r+0x1b8> +80002994: 400a6a13 ori s4,s4,1024 +80002998: c39fe06f j 800015d0 <_vfprintf_r+0x1b8> +8000299c: 00c12683 lw a3,12(sp) +800029a0: 00040b13 mv s6,s0 +800029a4: 41f6d793 srai a5,a3,0x1f +800029a8: 00d72023 sw a3,0(a4) +800029ac: 00f72223 sw a5,4(a4) +800029b0: db9fe06f j 80001768 <_vfprintf_r+0x350> +800029b4: 0006a903 lw s2,0(a3) +800029b8: 00000c93 li s9,0 +800029bc: 00e12a23 sw a4,20(sp) +800029c0: 00100793 li a5,1 +800029c4: ce4ff06f j 80001ea8 <_vfprintf_r+0xa90> +800029c8: 01412703 lw a4,20(sp) +800029cc: 00072783 lw a5,0(a4) +800029d0: 00470713 addi a4,a4,4 +800029d4: 00e12a23 sw a4,20(sp) +800029d8: 0007a583 lw a1,0(a5) +800029dc: 0047a603 lw a2,4(a5) +800029e0: 0087a683 lw a3,8(a5) +800029e4: 00c7a783 lw a5,12(a5) +800029e8: 0eb12823 sw a1,240(sp) +800029ec: 0ec12a23 sw a2,244(sp) +800029f0: 0ed12c23 sw a3,248(sp) +800029f4: 0ef12e23 sw a5,252(sp) +800029f8: ef5fe06f j 800018ec <_vfprintf_r+0x4d4> +800029fc: 0006a903 lw s2,0(a3) +80002a00: 00e12a23 sw a4,20(sp) +80002a04: 41f95c93 srai s9,s2,0x1f +80002a08: 000c8793 mv a5,s9 +80002a0c: e54ff06f j 80002060 <_vfprintf_r+0xc48> +80002a10: 0006a903 lw s2,0(a3) +80002a14: 00000c93 li s9,0 +80002a18: 00e12a23 sw a4,20(sp) +80002a1c: dc8ff06f j 80001fe4 <_vfprintf_r+0xbcc> +80002a20: 00068493 mv s1,a3 +80002a24: c89040e3 bgtz s1,800026a4 <_vfprintf_r+0x128c> +80002a28: ca5ff06f j 800026cc <_vfprintf_r+0x12b4> +80002a2c: 00148693 addi a3,s1,1 +80002a30: 00890713 addi a4,s2,8 +80002a34: 00812783 lw a5,8(sp) +80002a38: 01bc8cb3 add s9,s9,s11 +80002a3c: 01b92223 sw s11,4(s2) +80002a40: 00f92023 sw a5,0(s2) +80002a44: 0f912623 sw s9,236(sp) +80002a48: 0ed12423 sw a3,232(sp) +80002a4c: 00700793 li a5,7 +80002a50: 74d7de63 bge a5,a3,800031ac <_vfprintf_r+0x1d94> +80002a54: 0e410613 addi a2,sp,228 +80002a58: 000c0593 mv a1,s8 +80002a5c: 000d0513 mv a0,s10 +80002a60: 339090ef jal ra,8000c598 <__sprint_r> +80002a64: 9e0512e3 bnez a0,80002448 <_vfprintf_r+0x1030> +80002a68: 0e812683 lw a3,232(sp) +80002a6c: 0ec12c83 lw s9,236(sp) +80002a70: 11410893 addi a7,sp,276 +80002a74: 00168693 addi a3,a3,1 +80002a78: 10c10913 addi s2,sp,268 +80002a7c: ad5ff06f j 80002550 <_vfprintf_r+0x1138> +80002a80: 000c8893 mv a7,s9 +80002a84: 000a0b93 mv s7,s4 +80002a88: d70ff06f j 80001ff8 <_vfprintf_r+0xbe0> +80002a8c: 800157b7 lui a5,0x80015 +80002a90: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +80002a94: 000c8893 mv a7,s9 +80002a98: 02f12a23 sw a5,52(sp) +80002a9c: 020a7793 andi a5,s4,32 +80002aa0: 12078863 beqz a5,80002bd0 <_vfprintf_r+0x17b8> +80002aa4: 01412783 lw a5,20(sp) +80002aa8: 00778b13 addi s6,a5,7 +80002aac: ff8b7b13 andi s6,s6,-8 +80002ab0: 000b2903 lw s2,0(s6) +80002ab4: 004b2c83 lw s9,4(s6) +80002ab8: 008b0793 addi a5,s6,8 +80002abc: 00f12a23 sw a5,20(sp) +80002ac0: 001a7793 andi a5,s4,1 +80002ac4: 00078e63 beqz a5,80002ae0 <_vfprintf_r+0x16c8> +80002ac8: 019967b3 or a5,s2,s9 +80002acc: 00078a63 beqz a5,80002ae0 <_vfprintf_r+0x16c8> +80002ad0: 03000793 li a5,48 +80002ad4: 0cf10423 sb a5,200(sp) +80002ad8: 0c9104a3 sb s1,201(sp) +80002adc: 002a6a13 ori s4,s4,2 +80002ae0: bffa7b93 andi s7,s4,-1025 +80002ae4: 00200793 li a5,2 +80002ae8: bc0ff06f j 80001ea8 <_vfprintf_r+0xa90> +80002aec: 800157b7 lui a5,0x80015 +80002af0: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> +80002af4: 000c8893 mv a7,s9 +80002af8: 02f12a23 sw a5,52(sp) +80002afc: fa1ff06f j 80002a9c <_vfprintf_r+0x1684> +80002b00: 000c8893 mv a7,s9 +80002b04: cbcff06f j 80001fc0 <_vfprintf_r+0xba8> +80002b08: 0e410613 addi a2,sp,228 +80002b0c: 000c0593 mv a1,s8 +80002b10: 000d0513 mv a0,s10 +80002b14: 285090ef jal ra,8000c598 <__sprint_r> +80002b18: 920518e3 bnez a0,80002448 <_vfprintf_r+0x1030> +80002b1c: 0ec12783 lw a5,236(sp) +80002b20: 10c10893 addi a7,sp,268 +80002b24: f28ff06f j 8000224c <_vfprintf_r+0xe34> +80002b28: 00144483 lbu s1,1(s0) +80002b2c: 020a6a13 ori s4,s4,32 +80002b30: 00140413 addi s0,s0,1 +80002b34: a9dfe06f j 800015d0 <_vfprintf_r+0x1b8> +80002b38: 00144483 lbu s1,1(s0) +80002b3c: 200a6a13 ori s4,s4,512 +80002b40: 00140413 addi s0,s0,1 +80002b44: a8dfe06f j 800015d0 <_vfprintf_r+0x1b8> +80002b48: 00600793 li a5,6 +80002b4c: 000d8c93 mv s9,s11 +80002b50: 6bb7ee63 bltu a5,s11,8000320c <_vfprintf_r+0x1df4> +80002b54: 80015737 lui a4,0x80015 +80002b58: 000c8a93 mv s5,s9 +80002b5c: 01212a23 sw s2,20(sp) +80002b60: ca070b13 addi s6,a4,-864 # 80014ca0 <__BSS_END__+0xffffe064> +80002b64: ad9fe06f j 8000163c <_vfprintf_r+0x224> +80002b68: 01000613 li a2,16 +80002b6c: 0e812683 lw a3,232(sp) +80002b70: 40965463 bge a2,s1,80002f78 <_vfprintf_r+0x1b60> +80002b74: 01000c93 li s9,16 +80002b78: 00700d93 li s11,7 +80002b7c: 00c0006f j 80002b88 <_vfprintf_r+0x1770> +80002b80: ff048493 addi s1,s1,-16 +80002b84: 3e9cda63 bge s9,s1,80002f78 <_vfprintf_r+0x1b60> +80002b88: 00812703 lw a4,8(sp) +80002b8c: 01078793 addi a5,a5,16 +80002b90: 00168693 addi a3,a3,1 +80002b94: 00e8a023 sw a4,0(a7) +80002b98: 0198a223 sw s9,4(a7) +80002b9c: 0ef12623 sw a5,236(sp) +80002ba0: 0ed12423 sw a3,232(sp) +80002ba4: 00888893 addi a7,a7,8 +80002ba8: fcdddce3 bge s11,a3,80002b80 <_vfprintf_r+0x1768> +80002bac: 0e410613 addi a2,sp,228 +80002bb0: 000c0593 mv a1,s8 +80002bb4: 000d0513 mv a0,s10 +80002bb8: 1e1090ef jal ra,8000c598 <__sprint_r> +80002bbc: 880516e3 bnez a0,80002448 <_vfprintf_r+0x1030> +80002bc0: 0ec12783 lw a5,236(sp) +80002bc4: 0e812683 lw a3,232(sp) +80002bc8: 10c10893 addi a7,sp,268 +80002bcc: fb5ff06f j 80002b80 <_vfprintf_r+0x1768> +80002bd0: 01412683 lw a3,20(sp) +80002bd4: 010a7793 andi a5,s4,16 +80002bd8: 00468713 addi a4,a3,4 +80002bdc: 1c078063 beqz a5,80002d9c <_vfprintf_r+0x1984> +80002be0: 0006a903 lw s2,0(a3) +80002be4: 00000c93 li s9,0 +80002be8: 00e12a23 sw a4,20(sp) +80002bec: ed5ff06f j 80002ac0 <_vfprintf_r+0x16a8> +80002bf0: 0e410613 addi a2,sp,228 +80002bf4: 000c0593 mv a1,s8 +80002bf8: 000d0513 mv a0,s10 +80002bfc: 19d090ef jal ra,8000c598 <__sprint_r> +80002c00: 840514e3 bnez a0,80002448 <_vfprintf_r+0x1030> +80002c04: 0ec12c83 lw s9,236(sp) +80002c08: 0e812483 lw s1,232(sp) +80002c0c: 10c10913 addi s2,sp,268 +80002c10: 889ff06f j 80002498 <_vfprintf_r+0x1080> +80002c14: 0e410613 addi a2,sp,228 +80002c18: 000c0593 mv a1,s8 +80002c1c: 000d0513 mv a0,s10 +80002c20: 179090ef jal ra,8000c598 <__sprint_r> +80002c24: 820512e3 bnez a0,80002448 <_vfprintf_r+0x1030> +80002c28: 0ec12c83 lw s9,236(sp) +80002c2c: 0e812483 lw s1,232(sp) +80002c30: 10c10913 addi s2,sp,268 +80002c34: 891ff06f j 800024c4 <_vfprintf_r+0x10ac> +80002c38: 1b010b13 addi s6,sp,432 +80002c3c: 00000793 li a5,0 +80002c40: 00812823 sw s0,16(sp) +80002c44: 00912e23 sw s1,28(sp) +80002c48: 000b0413 mv s0,s6 +80002c4c: 03312223 sw s3,36(sp) +80002c50: 000c0b13 mv s6,s8 +80002c54: 00090493 mv s1,s2 +80002c58: 000c8993 mv s3,s9 +80002c5c: 400bfa13 andi s4,s7,1024 +80002c60: 03c12c83 lw s9,60(sp) +80002c64: 0ff00a93 li s5,255 +80002c68: 00088c13 mv s8,a7 +80002c6c: 00078913 mv s2,a5 +80002c70: 0240006f j 80002c94 <_vfprintf_r+0x187c> +80002c74: 00a00613 li a2,10 +80002c78: 00000693 li a3,0 +80002c7c: 00048513 mv a0,s1 +80002c80: 00098593 mv a1,s3 +80002c84: 0410d0ef jal ra,800104c4 <__udivdi3> +80002c88: 2a098ae3 beqz s3,8000373c <_vfprintf_r+0x2324> +80002c8c: 00050493 mv s1,a0 +80002c90: 00058993 mv s3,a1 +80002c94: 00a00613 li a2,10 +80002c98: 00000693 li a3,0 +80002c9c: 00048513 mv a0,s1 +80002ca0: 00098593 mv a1,s3 +80002ca4: 4550d0ef jal ra,800108f8 <__umoddi3> +80002ca8: 03050513 addi a0,a0,48 +80002cac: fea40fa3 sb a0,-1(s0) +80002cb0: 00190913 addi s2,s2,1 +80002cb4: fff40413 addi s0,s0,-1 +80002cb8: fa0a0ee3 beqz s4,80002c74 <_vfprintf_r+0x185c> +80002cbc: 000cc683 lbu a3,0(s9) +80002cc0: fad91ae3 bne s2,a3,80002c74 <_vfprintf_r+0x185c> +80002cc4: fb5908e3 beq s2,s5,80002c74 <_vfprintf_r+0x185c> +80002cc8: 4a099263 bnez s3,8000316c <_vfprintf_r+0x1d54> +80002ccc: 00900793 li a5,9 +80002cd0: 4897ee63 bltu a5,s1,8000316c <_vfprintf_r+0x1d54> +80002cd4: 000c0893 mv a7,s8 +80002cd8: 1b010793 addi a5,sp,432 +80002cdc: 000b0c13 mv s8,s6 +80002ce0: 00040b13 mv s6,s0 +80002ce4: 03912e23 sw s9,60(sp) +80002ce8: 01c12483 lw s1,28(sp) +80002cec: 02412983 lw s3,36(sp) +80002cf0: 01012403 lw s0,16(sp) +80002cf4: 03212023 sw s2,32(sp) +80002cf8: 41678cb3 sub s9,a5,s6 +80002cfc: 000b8a13 mv s4,s7 +80002d00: 9d4ff06f j 80001ed4 <_vfprintf_r+0xabc> +80002d04: 0e812683 lw a3,232(sp) +80002d08: 80015637 lui a2,0x80015 +80002d0c: ca860613 addi a2,a2,-856 # 80014ca8 <__BSS_END__+0xffffe06c> +80002d10: 00c8a023 sw a2,0(a7) +80002d14: 00178793 addi a5,a5,1 +80002d18: 00100613 li a2,1 +80002d1c: 00168693 addi a3,a3,1 +80002d20: 00c8a223 sw a2,4(a7) +80002d24: 0ef12623 sw a5,236(sp) +80002d28: 0ed12423 sw a3,232(sp) +80002d2c: 00700613 li a2,7 +80002d30: 00888893 addi a7,a7,8 +80002d34: 48d64463 blt a2,a3,800031bc <_vfprintf_r+0x1da4> +80002d38: 00058463 beqz a1,80002d40 <_vfprintf_r+0x1928> +80002d3c: eadfe06f j 80001be8 <_vfprintf_r+0x7d0> +80002d40: 02012703 lw a4,32(sp) +80002d44: 001a7693 andi a3,s4,1 +80002d48: 00e6e6b3 or a3,a3,a4 +80002d4c: 00069463 bnez a3,80002d54 <_vfprintf_r+0x193c> +80002d50: 9d1fe06f j 80001720 <_vfprintf_r+0x308> +80002d54: 03012683 lw a3,48(sp) +80002d58: 02c12703 lw a4,44(sp) +80002d5c: 00700613 li a2,7 +80002d60: 00d8a023 sw a3,0(a7) +80002d64: 0e812683 lw a3,232(sp) +80002d68: 00f707b3 add a5,a4,a5 +80002d6c: 00e8a223 sw a4,4(a7) +80002d70: 00168693 addi a3,a3,1 +80002d74: 0ef12623 sw a5,236(sp) +80002d78: 0ed12423 sw a3,232(sp) +80002d7c: 00d65463 bge a2,a3,80002d84 <_vfprintf_r+0x196c> +80002d80: e99fe06f j 80001c18 <_vfprintf_r+0x800> +80002d84: 00888893 addi a7,a7,8 +80002d88: ebdfe06f j 80001c44 <_vfprintf_r+0x82c> +80002d8c: 01012b83 lw s7,16(sp) +80002d90: 00040d13 mv s10,s0 +80002d94: 00048c13 mv s8,s1 +80002d98: eb4ff06f j 8000244c <_vfprintf_r+0x1034> +80002d9c: 040a7793 andi a5,s4,64 +80002da0: 14078063 beqz a5,80002ee0 <_vfprintf_r+0x1ac8> +80002da4: 01412783 lw a5,20(sp) +80002da8: 00000c93 li s9,0 +80002dac: 00e12a23 sw a4,20(sp) +80002db0: 0007d903 lhu s2,0(a5) +80002db4: d0dff06f j 80002ac0 <_vfprintf_r+0x16a8> +80002db8: 0e410613 addi a2,sp,228 +80002dbc: 000c0593 mv a1,s8 +80002dc0: 000d0513 mv a0,s10 +80002dc4: 7d4090ef jal ra,8000c598 <__sprint_r> +80002dc8: e8051063 bnez a0,80002448 <_vfprintf_r+0x1030> +80002dcc: 0ec12783 lw a5,236(sp) +80002dd0: 10c10893 addi a7,sp,268 +80002dd4: c3cff06f j 80002210 <_vfprintf_r+0xdf8> +80002dd8: 00812683 lw a3,8(sp) +80002ddc: 009787b3 add a5,a5,s1 +80002de0: 0098a223 sw s1,4(a7) +80002de4: 00d8a023 sw a3,0(a7) +80002de8: 00170713 addi a4,a4,1 +80002dec: 0ef12623 sw a5,236(sp) +80002df0: 0ee12423 sw a4,232(sp) +80002df4: 00700693 li a3,7 +80002df8: 00e6c463 blt a3,a4,80002e00 <_vfprintf_r+0x19e8> +80002dfc: 921fe06f j 8000171c <_vfprintf_r+0x304> +80002e00: e69fe06f j 80001c68 <_vfprintf_r+0x850> +80002e04: 0f012783 lw a5,240(sp) +80002e08: 0a010593 addi a1,sp,160 +80002e0c: 0b010513 addi a0,sp,176 +80002e10: 0af12823 sw a5,176(sp) +80002e14: 0f412783 lw a5,244(sp) +80002e18: 0a012023 sw zero,160(sp) +80002e1c: 0a012223 sw zero,164(sp) +80002e20: 0af12a23 sw a5,180(sp) +80002e24: 0f812783 lw a5,248(sp) +80002e28: 0a012423 sw zero,168(sp) +80002e2c: 0a012623 sw zero,172(sp) +80002e30: 0af12c23 sw a5,184(sp) +80002e34: 0fc12783 lw a5,252(sp) +80002e38: 0af12e23 sw a5,188(sp) +80002e3c: 5810e0ef jal ra,80011bbc <__letf2> +80002e40: 01012883 lw a7,16(sp) +80002e44: 260540e3 bltz a0,800038a4 <_vfprintf_r+0x248c> +80002e48: 0c714783 lbu a5,199(sp) +80002e4c: 04700713 li a4,71 +80002e50: 38975863 bge a4,s1,800031e0 <_vfprintf_r+0x1dc8> +80002e54: 80015737 lui a4,0x80015 +80002e58: c6c70b13 addi s6,a4,-916 # 80014c6c <__BSS_END__+0xffffe030> +80002e5c: 00012823 sw zero,16(sp) +80002e60: 02012423 sw zero,40(sp) +80002e64: 02012223 sw zero,36(sp) +80002e68: 00012e23 sw zero,28(sp) +80002e6c: f7fa7a13 andi s4,s4,-129 +80002e70: 00300a93 li s5,3 +80002e74: 00300c93 li s9,3 +80002e78: 00000d93 li s11,0 +80002e7c: 00078463 beqz a5,80002e84 <_vfprintf_r+0x1a6c> +80002e80: f75fe06f j 80001df4 <_vfprintf_r+0x9dc> +80002e84: fccfe06f j 80001650 <_vfprintf_r+0x238> +80002e88: 00c12783 lw a5,12(sp) +80002e8c: 00040b13 mv s6,s0 +80002e90: 00f72023 sw a5,0(a4) +80002e94: 8d5fe06f j 80001768 <_vfprintf_r+0x350> +80002e98: 000b0513 mv a0,s6 +80002e9c: 05912023 sw s9,64(sp) +80002ea0: 2c1060ef jal ra,80009960 +80002ea4: 0c714783 lbu a5,199(sp) +80002ea8: fff54a93 not s5,a0 +80002eac: 41fada93 srai s5,s5,0x1f +80002eb0: 01212a23 sw s2,20(sp) +80002eb4: 00012823 sw zero,16(sp) +80002eb8: 02012423 sw zero,40(sp) +80002ebc: 02012223 sw zero,36(sp) +80002ec0: 00012e23 sw zero,28(sp) +80002ec4: 04012883 lw a7,64(sp) +80002ec8: 00050c93 mv s9,a0 +80002ecc: 01557ab3 and s5,a0,s5 +80002ed0: 00000d93 li s11,0 +80002ed4: 00078463 beqz a5,80002edc <_vfprintf_r+0x1ac4> +80002ed8: f1dfe06f j 80001df4 <_vfprintf_r+0x9dc> +80002edc: f74fe06f j 80001650 <_vfprintf_r+0x238> +80002ee0: 200a7793 andi a5,s4,512 +80002ee4: 3a078263 beqz a5,80003288 <_vfprintf_r+0x1e70> +80002ee8: 01412783 lw a5,20(sp) +80002eec: 00000c93 li s9,0 +80002ef0: 00e12a23 sw a4,20(sp) +80002ef4: 0007c903 lbu s2,0(a5) +80002ef8: bc9ff06f j 80002ac0 <_vfprintf_r+0x16a8> +80002efc: 200bf793 andi a5,s7,512 +80002f00: 36078863 beqz a5,80003270 <_vfprintf_r+0x1e58> +80002f04: 01412783 lw a5,20(sp) +80002f08: 00000c93 li s9,0 +80002f0c: 00e12a23 sw a4,20(sp) +80002f10: 0007c903 lbu s2,0(a5) +80002f14: 00100793 li a5,1 +80002f18: f91fe06f j 80001ea8 <_vfprintf_r+0xa90> +80002f1c: 200a7793 andi a5,s4,512 +80002f20: 32078c63 beqz a5,80003258 <_vfprintf_r+0x1e40> +80002f24: 01412783 lw a5,20(sp) +80002f28: 00e12a23 sw a4,20(sp) +80002f2c: 00078903 lb s2,0(a5) +80002f30: 41f95c93 srai s9,s2,0x1f +80002f34: 000c8793 mv a5,s9 +80002f38: 928ff06f j 80002060 <_vfprintf_r+0xc48> +80002f3c: 200a7793 andi a5,s4,512 +80002f40: 30078263 beqz a5,80003244 <_vfprintf_r+0x1e2c> +80002f44: 01412783 lw a5,20(sp) +80002f48: 00000c93 li s9,0 +80002f4c: 00e12a23 sw a4,20(sp) +80002f50: 0007c903 lbu s2,0(a5) +80002f54: 890ff06f j 80001fe4 <_vfprintf_r+0xbcc> +80002f58: 0fc12783 lw a5,252(sp) +80002f5c: 3407ca63 bltz a5,800032b0 <_vfprintf_r+0x1e98> +80002f60: 0c714783 lbu a5,199(sp) +80002f64: 04700713 li a4,71 +80002f68: 1c975ce3 bge a4,s1,80003940 <_vfprintf_r+0x2528> +80002f6c: 80015737 lui a4,0x80015 +80002f70: c7470b13 addi s6,a4,-908 # 80014c74 <__BSS_END__+0xffffe038> +80002f74: ee9ff06f j 80002e5c <_vfprintf_r+0x1a44> +80002f78: 00812703 lw a4,8(sp) +80002f7c: 009787b3 add a5,a5,s1 +80002f80: 00168693 addi a3,a3,1 +80002f84: 00e8a023 sw a4,0(a7) +80002f88: 0098a223 sw s1,4(a7) +80002f8c: 0ef12623 sw a5,236(sp) +80002f90: 0ed12423 sw a3,232(sp) +80002f94: 00700613 li a2,7 +80002f98: 00888893 addi a7,a7,8 +80002f9c: f4d65463 bge a2,a3,800026e4 <_vfprintf_r+0x12cc> +80002fa0: 0e410613 addi a2,sp,228 +80002fa4: 000c0593 mv a1,s8 +80002fa8: 000d0513 mv a0,s10 +80002fac: 5ec090ef jal ra,8000c598 <__sprint_r> +80002fb0: c8051c63 bnez a0,80002448 <_vfprintf_r+0x1030> +80002fb4: 0ec12783 lw a5,236(sp) +80002fb8: 10c10893 addi a7,sp,268 +80002fbc: f28ff06f j 800026e4 <_vfprintf_r+0x12cc> +80002fc0: 02012703 lw a4,32(sp) +80002fc4: 02412c83 lw s9,36(sp) +80002fc8: 01412e23 sw s4,28(sp) +80002fcc: 04812023 sw s0,64(sp) +80002fd0: 05312223 sw s3,68(sp) +80002fd4: 03512223 sw s5,36(sp) +80002fd8: 02812983 lw s3,40(sp) +80002fdc: 03612423 sw s6,40(sp) +80002fe0: 00eb0bb3 add s7,s6,a4 +80002fe4: 03c12403 lw s0,60(sp) +80002fe8: 04812a03 lw s4,72(sp) +80002fec: 04c12a83 lw s5,76(sp) +80002ff0: 00700493 li s1,7 +80002ff4: 01000913 li s2,16 +80002ff8: 000c0b13 mv s6,s8 +80002ffc: 080c8863 beqz s9,8000308c <_vfprintf_r+0x1c74> +80003000: 08099863 bnez s3,80003090 <_vfprintf_r+0x1c78> +80003004: fff40413 addi s0,s0,-1 +80003008: fffc8c93 addi s9,s9,-1 +8000300c: 0e812703 lw a4,232(sp) +80003010: 014787b3 add a5,a5,s4 +80003014: 0158a023 sw s5,0(a7) +80003018: 00170713 addi a4,a4,1 +8000301c: 0148a223 sw s4,4(a7) +80003020: 0ef12623 sw a5,236(sp) +80003024: 0ee12423 sw a4,232(sp) +80003028: 00888893 addi a7,a7,8 +8000302c: 0ee4ce63 blt s1,a4,80003128 <_vfprintf_r+0x1d10> +80003030: 00044683 lbu a3,0(s0) +80003034: 41bb8633 sub a2,s7,s11 +80003038: 00068c13 mv s8,a3 +8000303c: 00d65463 bge a2,a3,80003044 <_vfprintf_r+0x1c2c> +80003040: 00060c13 mv s8,a2 +80003044: 03805663 blez s8,80003070 <_vfprintf_r+0x1c58> +80003048: 0e812683 lw a3,232(sp) +8000304c: 018787b3 add a5,a5,s8 +80003050: 01b8a023 sw s11,0(a7) +80003054: 00168693 addi a3,a3,1 +80003058: 0188a223 sw s8,4(a7) +8000305c: 0ef12623 sw a5,236(sp) +80003060: 0ed12423 sw a3,232(sp) +80003064: 0ed4c263 blt s1,a3,80003148 <_vfprintf_r+0x1d30> +80003068: 00044683 lbu a3,0(s0) +8000306c: 00888893 addi a7,a7,8 +80003070: fffc4613 not a2,s8 +80003074: 41f65613 srai a2,a2,0x1f +80003078: 00cc7733 and a4,s8,a2 +8000307c: 40e68c33 sub s8,a3,a4 +80003080: 01804c63 bgtz s8,80003098 <_vfprintf_r+0x1c80> +80003084: 00dd8db3 add s11,s11,a3 +80003088: f60c9ce3 bnez s9,80003000 <_vfprintf_r+0x1be8> +8000308c: 5e098a63 beqz s3,80003680 <_vfprintf_r+0x2268> +80003090: fff98993 addi s3,s3,-1 +80003094: f79ff06f j 8000300c <_vfprintf_r+0x1bf4> +80003098: 0e812683 lw a3,232(sp) +8000309c: 01894863 blt s2,s8,800030ac <_vfprintf_r+0x1c94> +800030a0: 0580006f j 800030f8 <_vfprintf_r+0x1ce0> +800030a4: ff0c0c13 addi s8,s8,-16 +800030a8: 05895863 bge s2,s8,800030f8 <_vfprintf_r+0x1ce0> +800030ac: 00812703 lw a4,8(sp) +800030b0: 01078793 addi a5,a5,16 +800030b4: 00168693 addi a3,a3,1 +800030b8: 00e8a023 sw a4,0(a7) +800030bc: 0128a223 sw s2,4(a7) +800030c0: 0ef12623 sw a5,236(sp) +800030c4: 0ed12423 sw a3,232(sp) +800030c8: 00888893 addi a7,a7,8 +800030cc: fcd4dce3 bge s1,a3,800030a4 <_vfprintf_r+0x1c8c> +800030d0: 0e410613 addi a2,sp,228 +800030d4: 000b0593 mv a1,s6 +800030d8: 000d0513 mv a0,s10 +800030dc: 4bc090ef jal ra,8000c598 <__sprint_r> +800030e0: 66051463 bnez a0,80003748 <_vfprintf_r+0x2330> +800030e4: ff0c0c13 addi s8,s8,-16 +800030e8: 0ec12783 lw a5,236(sp) +800030ec: 0e812683 lw a3,232(sp) +800030f0: 10c10893 addi a7,sp,268 +800030f4: fb894ce3 blt s2,s8,800030ac <_vfprintf_r+0x1c94> +800030f8: 00812703 lw a4,8(sp) +800030fc: 018787b3 add a5,a5,s8 +80003100: 00168693 addi a3,a3,1 +80003104: 00e8a023 sw a4,0(a7) +80003108: 0188a223 sw s8,4(a7) +8000310c: 0ef12623 sw a5,236(sp) +80003110: 0ed12423 sw a3,232(sp) +80003114: 66d4c063 blt s1,a3,80003774 <_vfprintf_r+0x235c> +80003118: 00044683 lbu a3,0(s0) +8000311c: 00888893 addi a7,a7,8 +80003120: 00dd8db3 add s11,s11,a3 +80003124: f65ff06f j 80003088 <_vfprintf_r+0x1c70> +80003128: 0e410613 addi a2,sp,228 +8000312c: 000b0593 mv a1,s6 +80003130: 000d0513 mv a0,s10 +80003134: 464090ef jal ra,8000c598 <__sprint_r> +80003138: 60051863 bnez a0,80003748 <_vfprintf_r+0x2330> +8000313c: 0ec12783 lw a5,236(sp) +80003140: 10c10893 addi a7,sp,268 +80003144: eedff06f j 80003030 <_vfprintf_r+0x1c18> +80003148: 0e410613 addi a2,sp,228 +8000314c: 000b0593 mv a1,s6 +80003150: 000d0513 mv a0,s10 +80003154: 444090ef jal ra,8000c598 <__sprint_r> +80003158: 5e051863 bnez a0,80003748 <_vfprintf_r+0x2330> +8000315c: 00044683 lbu a3,0(s0) +80003160: 0ec12783 lw a5,236(sp) +80003164: 10c10893 addi a7,sp,268 +80003168: f09ff06f j 80003070 <_vfprintf_r+0x1c58> +8000316c: 04812783 lw a5,72(sp) +80003170: 04c12583 lw a1,76(sp) +80003174: 00000913 li s2,0 +80003178: 40f40433 sub s0,s0,a5 +8000317c: 00078613 mv a2,a5 +80003180: 00040513 mv a0,s0 +80003184: 069060ef jal ra,800099ec +80003188: 001cc583 lbu a1,1(s9) +8000318c: 00a00613 li a2,10 +80003190: 00000693 li a3,0 +80003194: 00b03833 snez a6,a1 +80003198: 00048513 mv a0,s1 +8000319c: 00098593 mv a1,s3 +800031a0: 010c8cb3 add s9,s9,a6 +800031a4: 3200d0ef jal ra,800104c4 <__udivdi3> +800031a8: ae5ff06f j 80002c8c <_vfprintf_r+0x1874> +800031ac: 00168693 addi a3,a3,1 +800031b0: 00870893 addi a7,a4,8 +800031b4: 00070913 mv s2,a4 +800031b8: b98ff06f j 80002550 <_vfprintf_r+0x1138> +800031bc: 0e410613 addi a2,sp,228 +800031c0: 000c0593 mv a1,s8 +800031c4: 000d0513 mv a0,s10 +800031c8: 3d0090ef jal ra,8000c598 <__sprint_r> +800031cc: a6051e63 bnez a0,80002448 <_vfprintf_r+0x1030> +800031d0: 0cc12583 lw a1,204(sp) +800031d4: 0ec12783 lw a5,236(sp) +800031d8: 10c10893 addi a7,sp,268 +800031dc: b5dff06f j 80002d38 <_vfprintf_r+0x1920> +800031e0: 80015737 lui a4,0x80015 +800031e4: c6870b13 addi s6,a4,-920 # 80014c68 <__BSS_END__+0xffffe02c> +800031e8: c75ff06f j 80002e5c <_vfprintf_r+0x1a44> +800031ec: 0e410613 addi a2,sp,228 +800031f0: 000c0593 mv a1,s8 +800031f4: 000d0513 mv a0,s10 +800031f8: 3a0090ef jal ra,8000c598 <__sprint_r> +800031fc: a4051663 bnez a0,80002448 <_vfprintf_r+0x1030> +80003200: 0ec12783 lw a5,236(sp) +80003204: 10c10893 addi a7,sp,268 +80003208: cc4ff06f j 800026cc <_vfprintf_r+0x12b4> +8000320c: 00600c93 li s9,6 +80003210: 945ff06f j 80002b54 <_vfprintf_r+0x173c> +80003214: 02012683 lw a3,32(sp) +80003218: 00db0733 add a4,s6,a3 +8000321c: 409684b3 sub s1,a3,s1 +80003220: 41b70833 sub a6,a4,s11 +80003224: 00048913 mv s2,s1 +80003228: d6985063 bge a6,s1,80002788 <_vfprintf_r+0x1370> +8000322c: 00080913 mv s2,a6 +80003230: d58ff06f j 80002788 <_vfprintf_r+0x1370> +80003234: 00c12783 lw a5,12(sp) +80003238: 00040b13 mv s6,s0 +8000323c: 00f71023 sh a5,0(a4) +80003240: d28fe06f j 80001768 <_vfprintf_r+0x350> +80003244: 01412783 lw a5,20(sp) +80003248: 00000c93 li s9,0 +8000324c: 00e12a23 sw a4,20(sp) +80003250: 0007a903 lw s2,0(a5) +80003254: d91fe06f j 80001fe4 <_vfprintf_r+0xbcc> +80003258: 01412783 lw a5,20(sp) +8000325c: 00e12a23 sw a4,20(sp) +80003260: 0007a903 lw s2,0(a5) +80003264: 41f95c93 srai s9,s2,0x1f +80003268: 000c8793 mv a5,s9 +8000326c: df5fe06f j 80002060 <_vfprintf_r+0xc48> +80003270: 01412783 lw a5,20(sp) +80003274: 00000c93 li s9,0 +80003278: 00e12a23 sw a4,20(sp) +8000327c: 0007a903 lw s2,0(a5) +80003280: 00100793 li a5,1 +80003284: c25fe06f j 80001ea8 <_vfprintf_r+0xa90> +80003288: 01412783 lw a5,20(sp) +8000328c: 00000c93 li s9,0 +80003290: 00e12a23 sw a4,20(sp) +80003294: 0007a903 lw s2,0(a5) +80003298: 829ff06f j 80002ac0 <_vfprintf_r+0x16a8> +8000329c: 0e410613 addi a2,sp,228 +800032a0: 000c0593 mv a1,s8 +800032a4: 000d0513 mv a0,s10 +800032a8: 2f0090ef jal ra,8000c598 <__sprint_r> +800032ac: cd0fe06f j 8000177c <_vfprintf_r+0x364> +800032b0: 02d00793 li a5,45 +800032b4: 0cf103a3 sb a5,199(sp) +800032b8: cadff06f j 80002f64 <_vfprintf_r+0x1b4c> +800032bc: 03000793 li a5,48 +800032c0: 0cf10423 sb a5,200(sp) +800032c4: 05800793 li a5,88 +800032c8: 002a6713 ori a4,s4,2 +800032cc: 0cf104a3 sb a5,201(sp) +800032d0: 02e12423 sw a4,40(sp) +800032d4: 06300793 li a5,99 +800032d8: 00012823 sw zero,16(sp) +800032dc: 14c10b13 addi s6,sp,332 +800032e0: 03b7c4e3 blt a5,s11,80003b08 <_vfprintf_r+0x26f0> +800032e4: 0fc12303 lw t1,252(sp) +800032e8: fdf4fb93 andi s7,s1,-33 +800032ec: 05712223 sw s7,68(sp) +800032f0: 04012c23 sw zero,88(sp) +800032f4: 0f012e03 lw t3,240(sp) +800032f8: 0f412e83 lw t4,244(sp) +800032fc: 0f812f03 lw t5,248(sp) +80003300: 102a6a13 ori s4,s4,258 +80003304: 44034e63 bltz t1,80003760 <_vfprintf_r+0x2348> +80003308: 06100793 li a5,97 +8000330c: 0af48ee3 beq s1,a5,80003bc8 <_vfprintf_r+0x27b0> +80003310: 04100793 li a5,65 +80003314: 00f48463 beq s1,a5,8000331c <_vfprintf_r+0x1f04> +80003318: e64fe06f j 8000197c <_vfprintf_r+0x564> +8000331c: 0b010a93 addi s5,sp,176 +80003320: 000a8513 mv a0,s5 +80003324: 05112a23 sw a7,84(sp) +80003328: 0bc12823 sw t3,176(sp) +8000332c: 0bd12a23 sw t4,180(sp) +80003330: 0be12c23 sw t5,184(sp) +80003334: 0a612e23 sw t1,188(sp) +80003338: 344110ef jal ra,8001467c <__trunctfdf2> +8000333c: 0cc10613 addi a2,sp,204 +80003340: 22c060ef jal ra,8000956c +80003344: 00058613 mv a2,a1 +80003348: 00050593 mv a1,a0 +8000334c: 000a8513 mv a0,s5 +80003350: 138110ef jal ra,80014488 <__extenddftf2> +80003354: 0b012783 lw a5,176(sp) +80003358: 0a010c93 addi s9,sp,160 +8000335c: 09010913 addi s2,sp,144 +80003360: 08f12823 sw a5,144(sp) +80003364: 0b412783 lw a5,180(sp) +80003368: 08010613 addi a2,sp,128 +8000336c: 00090593 mv a1,s2 +80003370: 08f12a23 sw a5,148(sp) +80003374: 0b812783 lw a5,184(sp) +80003378: 000c8513 mv a0,s9 +8000337c: 04c12023 sw a2,64(sp) +80003380: 08f12c23 sw a5,152(sp) +80003384: 0bc12783 lw a5,188(sp) +80003388: 08012023 sw zero,128(sp) +8000338c: 08012223 sw zero,132(sp) +80003390: 08f12e23 sw a5,156(sp) +80003394: 3ffc07b7 lui a5,0x3ffc0 +80003398: 08f12623 sw a5,140(sp) +8000339c: 08012423 sw zero,136(sp) +800033a0: 1610e0ef jal ra,80011d00 <__multf3> +800033a4: 0a012803 lw a6,160(sp) +800033a8: 0a412e03 lw t3,164(sp) +800033ac: 0a812e83 lw t4,168(sp) +800033b0: 0ac12f03 lw t5,172(sp) +800033b4: 000c8593 mv a1,s9 +800033b8: 000a8513 mv a0,s5 +800033bc: 0b012823 sw a6,176(sp) +800033c0: 05012823 sw a6,80(sp) +800033c4: 0bc12a23 sw t3,180(sp) +800033c8: 03c12223 sw t3,36(sp) +800033cc: 0bd12c23 sw t4,184(sp) +800033d0: 03d12023 sw t4,32(sp) +800033d4: 0be12e23 sw t5,188(sp) +800033d8: 01e12e23 sw t5,28(sp) +800033dc: 0a012023 sw zero,160(sp) +800033e0: 0a012223 sw zero,164(sp) +800033e4: 0a012423 sw zero,168(sp) +800033e8: 0a012623 sw zero,172(sp) +800033ec: 5c00e0ef jal ra,800119ac <__eqtf2> +800033f0: 01c12f03 lw t5,28(sp) +800033f4: 02012e83 lw t4,32(sp) +800033f8: 02412e03 lw t3,36(sp) +800033fc: 05012803 lw a6,80(sp) +80003400: 05412883 lw a7,84(sp) +80003404: 00051663 bnez a0,80003410 <_vfprintf_r+0x1ff8> +80003408: 00100793 li a5,1 +8000340c: 0cf12623 sw a5,204(sp) +80003410: 800157b7 lui a5,0x80015 +80003414: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> +80003418: 02f12223 sw a5,36(sp) +8000341c: fffd8693 addi a3,s11,-1 +80003420: 05412e23 sw s4,92(sp) +80003424: 06912223 sw s1,100(sp) +80003428: 07b12623 sw s11,108(sp) +8000342c: 07a12a23 sw s10,116(sp) +80003430: 07812c23 sw s8,120(sp) +80003434: 06812023 sw s0,96(sp) +80003438: 07312423 sw s3,104(sp) +8000343c: 07112823 sw a7,112(sp) +80003440: 000b0c13 mv s8,s6 +80003444: 00068b93 mv s7,a3 +80003448: 07612e23 sw s6,124(sp) +8000344c: 00080d13 mv s10,a6 +80003450: 000e0d93 mv s11,t3 +80003454: 000e8493 mv s1,t4 +80003458: 000f0a13 mv s4,t5 +8000345c: 0480006f j 800034a4 <_vfprintf_r+0x208c> +80003460: 000c8593 mv a1,s9 +80003464: 000a8513 mv a0,s5 +80003468: 02c12023 sw a2,32(sp) +8000346c: 01f12e23 sw t6,28(sp) +80003470: 0bf12c23 sw t6,184(sp) +80003474: 0ac12e23 sw a2,188(sp) +80003478: 0b612823 sw s6,176(sp) +8000347c: 0b312a23 sw s3,180(sp) +80003480: 0a012023 sw zero,160(sp) +80003484: 0a012223 sw zero,164(sp) +80003488: 0a012423 sw zero,168(sp) +8000348c: 0a012623 sw zero,172(sp) +80003490: 51c0e0ef jal ra,800119ac <__eqtf2> +80003494: 01c12f83 lw t6,28(sp) +80003498: 02012603 lw a2,32(sp) +8000349c: fffb8b93 addi s7,s7,-1 +800034a0: 0e050263 beqz a0,80003584 <_vfprintf_r+0x216c> +800034a4: 400307b7 lui a5,0x40030 +800034a8: 00090613 mv a2,s2 +800034ac: 000c8593 mv a1,s9 +800034b0: 000a8513 mv a0,s5 +800034b4: 08f12e23 sw a5,156(sp) +800034b8: 0ba12023 sw s10,160(sp) +800034bc: 0bb12223 sw s11,164(sp) +800034c0: 0a912423 sw s1,168(sp) +800034c4: 0b412623 sw s4,172(sp) +800034c8: 08012823 sw zero,144(sp) +800034cc: 08012a23 sw zero,148(sp) +800034d0: 08012c23 sw zero,152(sp) +800034d4: 02d0e0ef jal ra,80011d00 <__multf3> +800034d8: 000a8513 mv a0,s5 +800034dc: 549100ef jal ra,80014224 <__fixtfsi> +800034e0: 00050593 mv a1,a0 +800034e4: 00050413 mv s0,a0 +800034e8: 000a8513 mv a0,s5 +800034ec: 0b012983 lw s3,176(sp) +800034f0: 0b412483 lw s1,180(sp) +800034f4: 0b812b03 lw s6,184(sp) +800034f8: 0bc12a03 lw s4,188(sp) +800034fc: 63d100ef jal ra,80014338 <__floatsitf> +80003500: 0b012703 lw a4,176(sp) +80003504: 04012603 lw a2,64(sp) +80003508: 00090593 mv a1,s2 +8000350c: 08e12023 sw a4,128(sp) +80003510: 0b412703 lw a4,180(sp) +80003514: 000c8513 mv a0,s9 +80003518: 09312823 sw s3,144(sp) +8000351c: 08e12223 sw a4,132(sp) +80003520: 0b812703 lw a4,184(sp) +80003524: 08912a23 sw s1,148(sp) +80003528: 09612c23 sw s6,152(sp) +8000352c: 08e12423 sw a4,136(sp) +80003530: 0bc12703 lw a4,188(sp) +80003534: 09412e23 sw s4,156(sp) +80003538: 08e12623 sw a4,140(sp) +8000353c: 7c80f0ef jal ra,80012d04 <__subtf3> +80003540: 02412783 lw a5,36(sp) +80003544: 0a012b03 lw s6,160(sp) +80003548: 0a412983 lw s3,164(sp) +8000354c: 00878733 add a4,a5,s0 +80003550: 00074703 lbu a4,0(a4) +80003554: 0a812f83 lw t6,168(sp) +80003558: 0ac12603 lw a2,172(sp) +8000355c: 05812a23 sw s8,84(sp) +80003560: 00ec0023 sb a4,0(s8) +80003564: 05712823 sw s7,80(sp) +80003568: fff00793 li a5,-1 +8000356c: 001c0c13 addi s8,s8,1 +80003570: 000b0d13 mv s10,s6 +80003574: 00098d93 mv s11,s3 +80003578: 000f8493 mv s1,t6 +8000357c: 00060a13 mv s4,a2 +80003580: eefb90e3 bne s7,a5,80003460 <_vfprintf_r+0x2048> +80003584: 07012883 lw a7,112(sp) +80003588: 000b0393 mv t2,s6 +8000358c: 00098293 mv t0,s3 +80003590: 3ffe0937 lui s2,0x3ffe0 +80003594: 000c8593 mv a1,s9 +80003598: 000a8513 mv a0,s5 +8000359c: 03112023 sw a7,32(sp) +800035a0: 00812e23 sw s0,28(sp) +800035a4: 05c12a03 lw s4,92(sp) +800035a8: 06412483 lw s1,100(sp) +800035ac: 06012403 lw s0,96(sp) +800035b0: 0a712823 sw t2,176(sp) +800035b4: 06712223 sw t2,100(sp) +800035b8: 0a512a23 sw t0,180(sp) +800035bc: 06512023 sw t0,96(sp) +800035c0: 0bf12c23 sw t6,184(sp) +800035c4: 05f12e23 sw t6,92(sp) +800035c8: 0ac12e23 sw a2,188(sp) +800035cc: 04c12023 sw a2,64(sp) +800035d0: 0a012023 sw zero,160(sp) +800035d4: 0a012223 sw zero,164(sp) +800035d8: 0a012423 sw zero,168(sp) +800035dc: 0b212623 sw s2,172(sp) +800035e0: 4980e0ef jal ra,80011a78 <__getf2> +800035e4: 000c0b93 mv s7,s8 +800035e8: 06c12d83 lw s11,108(sp) +800035ec: 07412d03 lw s10,116(sp) +800035f0: 07812c03 lw s8,120(sp) +800035f4: 07c12b03 lw s6,124(sp) +800035f8: 06812983 lw s3,104(sp) +800035fc: 02012883 lw a7,32(sp) +80003600: 48a04263 bgtz a0,80003a84 <_vfprintf_r+0x266c> +80003604: 06412383 lw t2,100(sp) +80003608: 06012283 lw t0,96(sp) +8000360c: 05c12f83 lw t6,92(sp) +80003610: 04012603 lw a2,64(sp) +80003614: 000c8593 mv a1,s9 +80003618: 000a8513 mv a0,s5 +8000361c: 0a712823 sw t2,176(sp) +80003620: 0a512a23 sw t0,180(sp) +80003624: 0bf12c23 sw t6,184(sp) +80003628: 0ac12e23 sw a2,188(sp) +8000362c: 0a012023 sw zero,160(sp) +80003630: 0a012223 sw zero,164(sp) +80003634: 0a012423 sw zero,168(sp) +80003638: 0b212623 sw s2,172(sp) +8000363c: 3700e0ef jal ra,800119ac <__eqtf2> +80003640: 02012883 lw a7,32(sp) +80003644: 00051863 bnez a0,80003654 <_vfprintf_r+0x223c> +80003648: 01c12783 lw a5,28(sp) +8000364c: 0017fc93 andi s9,a5,1 +80003650: 420c9a63 bnez s9,80003a84 <_vfprintf_r+0x266c> +80003654: 05012783 lw a5,80(sp) +80003658: 03000613 li a2,48 +8000365c: 00178693 addi a3,a5,1 # 40030001 <_start-0x3ffcffff> +80003660: 00db86b3 add a3,s7,a3 +80003664: 0007c863 bltz a5,80003674 <_vfprintf_r+0x225c> +80003668: 001b8b93 addi s7,s7,1 +8000366c: fecb8fa3 sb a2,-1(s7) +80003670: ff769ce3 bne a3,s7,80003668 <_vfprintf_r+0x2250> +80003674: 416b87b3 sub a5,s7,s6 +80003678: 02f12023 sw a5,32(sp) +8000367c: be8fe06f j 80001a64 <_vfprintf_r+0x64c> +80003680: 02012703 lw a4,32(sp) +80003684: 000b0c13 mv s8,s6 +80003688: 02812b03 lw s6,40(sp) +8000368c: 02812e23 sw s0,60(sp) +80003690: 01c12a03 lw s4,28(sp) +80003694: 00eb06b3 add a3,s6,a4 +80003698: 04012403 lw s0,64(sp) +8000369c: 04412983 lw s3,68(sp) +800036a0: 02412a83 lw s5,36(sp) +800036a4: 01b6e463 bltu a3,s11,800036ac <_vfprintf_r+0x2294> +800036a8: 84cff06f j 800026f4 <_vfprintf_r+0x12dc> +800036ac: 00068d93 mv s11,a3 +800036b0: 844ff06f j 800026f4 <_vfprintf_r+0x12dc> +800036b4: 01c12703 lw a4,28(sp) +800036b8: ffd00793 li a5,-3 +800036bc: 00f74463 blt a4,a5,800036c4 <_vfprintf_r+0x22ac> +800036c0: 00edda63 bge s11,a4,800036d4 <_vfprintf_r+0x22bc> +800036c4: ffe48493 addi s1,s1,-2 +800036c8: fdf4f793 andi a5,s1,-33 +800036cc: 04f12223 sw a5,68(sp) +800036d0: bbcfe06f j 80001a8c <_vfprintf_r+0x674> +800036d4: 02012783 lw a5,32(sp) +800036d8: 01c12703 lw a4,28(sp) +800036dc: 2af74063 blt a4,a5,8000397c <_vfprintf_r+0x2564> +800036e0: 02812783 lw a5,40(sp) +800036e4: 00070c93 mv s9,a4 +800036e8: 0017f793 andi a5,a5,1 +800036ec: 00078663 beqz a5,800036f8 <_vfprintf_r+0x22e0> +800036f0: 02c12783 lw a5,44(sp) +800036f4: 00f70cb3 add s9,a4,a5 +800036f8: 02812783 lw a5,40(sp) +800036fc: 4007f793 andi a5,a5,1024 +80003700: 00078663 beqz a5,8000370c <_vfprintf_r+0x22f4> +80003704: 01c12783 lw a5,28(sp) +80003708: 5cf04263 bgtz a5,80003ccc <_vfprintf_r+0x28b4> +8000370c: fffcca93 not s5,s9 +80003710: 41fada93 srai s5,s5,0x1f +80003714: 015cfab3 and s5,s9,s5 +80003718: 06700493 li s1,103 +8000371c: 02012423 sw zero,40(sp) +80003720: 02012223 sw zero,36(sp) +80003724: c84fe06f j 80001ba8 <_vfprintf_r+0x790> +80003728: 0c714783 lbu a5,199(sp) +8000372c: 00000d93 li s11,0 +80003730: 00078463 beqz a5,80003738 <_vfprintf_r+0x2320> +80003734: ec0fe06f j 80001df4 <_vfprintf_r+0x9dc> +80003738: f19fd06f j 80001650 <_vfprintf_r+0x238> +8000373c: 00900793 li a5,9 +80003740: d497e663 bltu a5,s1,80002c8c <_vfprintf_r+0x1874> +80003744: d90ff06f j 80002cd4 <_vfprintf_r+0x18bc> +80003748: 01012b83 lw s7,16(sp) +8000374c: 000b0c13 mv s8,s6 +80003750: cfdfe06f j 8000244c <_vfprintf_r+0x1034> +80003754: 03412423 sw s4,40(sp) +80003758: 00012823 sw zero,16(sp) +8000375c: 00090a13 mv s4,s2 +80003760: 800007b7 lui a5,0x80000 +80003764: 0067c333 xor t1,a5,t1 +80003768: 02d00793 li a5,45 +8000376c: 04f12c23 sw a5,88(sp) +80003770: b99ff06f j 80003308 <_vfprintf_r+0x1ef0> +80003774: 0e410613 addi a2,sp,228 +80003778: 000b0593 mv a1,s6 +8000377c: 000d0513 mv a0,s10 +80003780: 619080ef jal ra,8000c598 <__sprint_r> +80003784: fc0512e3 bnez a0,80003748 <_vfprintf_r+0x2330> +80003788: 00044683 lbu a3,0(s0) +8000378c: 0ec12783 lw a5,236(sp) +80003790: 10c10893 addi a7,sp,268 +80003794: 00dd8db3 add s11,s11,a3 +80003798: 8f1ff06f j 80003088 <_vfprintf_r+0x1c70> +8000379c: 0b010a93 addi s5,sp,176 +800037a0: 0d010793 addi a5,sp,208 +800037a4: 0dc10813 addi a6,sp,220 +800037a8: 0cc10713 addi a4,sp,204 +800037ac: 000d8693 mv a3,s11 +800037b0: 00200613 li a2,2 +800037b4: 000a8593 mv a1,s5 +800037b8: 000d0513 mv a0,s10 +800037bc: 0bc12823 sw t3,176(sp) +800037c0: 05c12023 sw t3,64(sp) +800037c4: 0bd12a23 sw t4,180(sp) +800037c8: 03d12223 sw t4,36(sp) +800037cc: 0be12c23 sw t5,184(sp) +800037d0: 03e12023 sw t5,32(sp) +800037d4: 0a612e23 sw t1,188(sp) +800037d8: 00612e23 sw t1,28(sp) +800037dc: 6c9020ef jal ra,800066a4 <_ldtoa_r> +800037e0: 04700793 li a5,71 +800037e4: 01c12303 lw t1,28(sp) +800037e8: 02012f03 lw t5,32(sp) +800037ec: 02412e83 lw t4,36(sp) +800037f0: 04012e03 lw t3,64(sp) +800037f4: 05012883 lw a7,80(sp) +800037f8: 00050b13 mv s6,a0 +800037fc: 08fb9063 bne s7,a5,8000387c <_vfprintf_r+0x2464> +80003800: 02812783 lw a5,40(sp) +80003804: 0017f793 andi a5,a5,1 +80003808: 2e079663 bnez a5,80003af4 <_vfprintf_r+0x26dc> +8000380c: 04700793 li a5,71 +80003810: 0dc12703 lw a4,220(sp) +80003814: 04f12223 sw a5,68(sp) +80003818: a44fe06f j 80001a5c <_vfprintf_r+0x644> +8000381c: 0b010a93 addi s5,sp,176 +80003820: 0dc10813 addi a6,sp,220 +80003824: 0d010793 addi a5,sp,208 +80003828: 0cc10713 addi a4,sp,204 +8000382c: 000d8693 mv a3,s11 +80003830: 00300613 li a2,3 +80003834: 000a8593 mv a1,s5 +80003838: 000d0513 mv a0,s10 +8000383c: 05112823 sw a7,80(sp) +80003840: 0bc12823 sw t3,176(sp) +80003844: 05c12023 sw t3,64(sp) +80003848: 0bd12a23 sw t4,180(sp) +8000384c: 03d12223 sw t4,36(sp) +80003850: 0be12c23 sw t5,184(sp) +80003854: 03e12023 sw t5,32(sp) +80003858: 0a612e23 sw t1,188(sp) +8000385c: 00612e23 sw t1,28(sp) +80003860: 645020ef jal ra,800066a4 <_ldtoa_r> +80003864: 01c12303 lw t1,28(sp) +80003868: 02012f03 lw t5,32(sp) +8000386c: 02412e83 lw t4,36(sp) +80003870: 04012e03 lw t3,64(sp) +80003874: 05012883 lw a7,80(sp) +80003878: 00050b13 mv s6,a0 +8000387c: 04600793 li a5,70 +80003880: 01bb0933 add s2,s6,s11 +80003884: 26fb9e63 bne s7,a5,80003b00 <_vfprintf_r+0x26e8> +80003888: 000b4683 lbu a3,0(s6) +8000388c: 03000793 li a5,48 +80003890: 50f68663 beq a3,a5,80003d9c <_vfprintf_r+0x2984> +80003894: 0a010c93 addi s9,sp,160 +80003898: 0cc12783 lw a5,204(sp) +8000389c: 00f90933 add s2,s2,a5 +800038a0: 960fe06f j 80001a00 <_vfprintf_r+0x5e8> +800038a4: 02d00793 li a5,45 +800038a8: 0cf103a3 sb a5,199(sp) +800038ac: da0ff06f j 80002e4c <_vfprintf_r+0x1a34> +800038b0: 0e410613 addi a2,sp,228 +800038b4: 000c0593 mv a1,s8 +800038b8: 000d0513 mv a0,s10 +800038bc: 4dd080ef jal ra,8000c598 <__sprint_r> +800038c0: 00050463 beqz a0,800038c8 <_vfprintf_r+0x24b0> +800038c4: b85fe06f j 80002448 <_vfprintf_r+0x1030> +800038c8: 0cc12483 lw s1,204(sp) +800038cc: 0ec12783 lw a5,236(sp) +800038d0: 10c10893 addi a7,sp,268 +800038d4: e69fe06f j 8000273c <_vfprintf_r+0x1324> +800038d8: 0c714783 lbu a5,199(sp) +800038dc: 01212a23 sw s2,20(sp) +800038e0: 02012423 sw zero,40(sp) +800038e4: 02012223 sw zero,36(sp) +800038e8: 00012e23 sw zero,28(sp) +800038ec: 000d8a93 mv s5,s11 +800038f0: 000d8c93 mv s9,s11 +800038f4: 00000d93 li s11,0 +800038f8: 00078463 beqz a5,80003900 <_vfprintf_r+0x24e8> +800038fc: cf8fe06f j 80001df4 <_vfprintf_r+0x9dc> +80003900: d51fd06f j 80001650 <_vfprintf_r+0x238> +80003904: 02812783 lw a5,40(sp) +80003908: 01c12703 lw a4,28(sp) +8000390c: 0017f793 andi a5,a5,1 +80003910: 01b7e7b3 or a5,a5,s11 +80003914: 50e05663 blez a4,80003e20 <_vfprintf_r+0x2a08> +80003918: 44079063 bnez a5,80003d58 <_vfprintf_r+0x2940> +8000391c: 01c12c83 lw s9,28(sp) +80003920: 06600493 li s1,102 +80003924: 02812783 lw a5,40(sp) +80003928: 4007f793 andi a5,a5,1024 +8000392c: 3a079263 bnez a5,80003cd0 <_vfprintf_r+0x28b8> +80003930: fffcca93 not s5,s9 +80003934: 41fada93 srai s5,s5,0x1f +80003938: 015cfab3 and s5,s9,s5 +8000393c: de1ff06f j 8000371c <_vfprintf_r+0x2304> +80003940: 80015737 lui a4,0x80015 +80003944: c7070b13 addi s6,a4,-912 # 80014c70 <__BSS_END__+0xffffe034> +80003948: d14ff06f j 80002e5c <_vfprintf_r+0x1a44> +8000394c: 0e410613 addi a2,sp,228 +80003950: 000c0593 mv a1,s8 +80003954: 000d0513 mv a0,s10 +80003958: 441080ef jal ra,8000c598 <__sprint_r> +8000395c: 00050463 beqz a0,80003964 <_vfprintf_r+0x254c> +80003960: ae9fe06f j 80002448 <_vfprintf_r+0x1030> +80003964: 0cc12483 lw s1,204(sp) +80003968: 02012703 lw a4,32(sp) +8000396c: 0ec12783 lw a5,236(sp) +80003970: 10c10893 addi a7,sp,268 +80003974: 409704b3 sub s1,a4,s1 +80003978: e11fe06f j 80002788 <_vfprintf_r+0x1370> +8000397c: 02012783 lw a5,32(sp) +80003980: 02c12703 lw a4,44(sp) +80003984: 06700493 li s1,103 +80003988: 00e78cb3 add s9,a5,a4 +8000398c: 01c12783 lw a5,28(sp) +80003990: f8f04ae3 bgtz a5,80003924 <_vfprintf_r+0x250c> +80003994: 40fc8cb3 sub s9,s9,a5 +80003998: 001c8c93 addi s9,s9,1 +8000399c: fffcca93 not s5,s9 +800039a0: 41fada93 srai s5,s5,0x1f +800039a4: 015cfab3 and s5,s9,s5 +800039a8: d75ff06f j 8000371c <_vfprintf_r+0x2304> +800039ac: 800156b7 lui a3,0x80015 +800039b0: e1868e93 addi t4,a3,-488 # 80014e18 <__BSS_END__+0xffffe1dc> +800039b4: b50fe06f j 80001d04 <_vfprintf_r+0x8ec> +800039b8: fff00793 li a5,-1 +800039bc: 00f12623 sw a5,12(sp) +800039c0: dcdfd06f j 8000178c <_vfprintf_r+0x374> +800039c4: ff000613 li a2,-16 +800039c8: 40b004b3 neg s1,a1 +800039cc: 06c5d263 bge a1,a2,80003a30 <_vfprintf_r+0x2618> +800039d0: 01000913 li s2,16 +800039d4: 00700c93 li s9,7 +800039d8: 00c0006f j 800039e4 <_vfprintf_r+0x25cc> +800039dc: ff048493 addi s1,s1,-16 +800039e0: 04995863 bge s2,s1,80003a30 <_vfprintf_r+0x2618> +800039e4: 00812703 lw a4,8(sp) +800039e8: 01078793 addi a5,a5,16 # 80000010 <__BSS_END__+0xfffe93d4> +800039ec: 00168693 addi a3,a3,1 +800039f0: 00e8a023 sw a4,0(a7) +800039f4: 0128a223 sw s2,4(a7) +800039f8: 0ef12623 sw a5,236(sp) +800039fc: 0ed12423 sw a3,232(sp) +80003a00: 00888893 addi a7,a7,8 +80003a04: fcdcdce3 bge s9,a3,800039dc <_vfprintf_r+0x25c4> +80003a08: 0e410613 addi a2,sp,228 +80003a0c: 000c0593 mv a1,s8 +80003a10: 000d0513 mv a0,s10 +80003a14: 385080ef jal ra,8000c598 <__sprint_r> +80003a18: 00050463 beqz a0,80003a20 <_vfprintf_r+0x2608> +80003a1c: a2dfe06f j 80002448 <_vfprintf_r+0x1030> +80003a20: 0ec12783 lw a5,236(sp) +80003a24: 0e812683 lw a3,232(sp) +80003a28: 10c10893 addi a7,sp,268 +80003a2c: fb1ff06f j 800039dc <_vfprintf_r+0x25c4> +80003a30: 00812703 lw a4,8(sp) +80003a34: 009787b3 add a5,a5,s1 +80003a38: 00168693 addi a3,a3,1 +80003a3c: 00e8a023 sw a4,0(a7) +80003a40: 0098a223 sw s1,4(a7) +80003a44: 0ef12623 sw a5,236(sp) +80003a48: 0ed12423 sw a3,232(sp) +80003a4c: 00700613 li a2,7 +80003a50: b2d65a63 bge a2,a3,80002d84 <_vfprintf_r+0x196c> +80003a54: 0e410613 addi a2,sp,228 +80003a58: 000c0593 mv a1,s8 +80003a5c: 000d0513 mv a0,s10 +80003a60: 339080ef jal ra,8000c598 <__sprint_r> +80003a64: 00050463 beqz a0,80003a6c <_vfprintf_r+0x2654> +80003a68: 9e1fe06f j 80002448 <_vfprintf_r+0x1030> +80003a6c: 0ec12783 lw a5,236(sp) +80003a70: 0e812683 lw a3,232(sp) +80003a74: 10c10893 addi a7,sp,268 +80003a78: 9ccfe06f j 80001c44 <_vfprintf_r+0x82c> +80003a7c: 000a0b93 mv s7,s4 +80003a80: e20fe06f j 800020a0 <_vfprintf_r+0xc88> +80003a84: 05412783 lw a5,84(sp) +80003a88: 000b8693 mv a3,s7 +80003a8c: 0cf12e23 sw a5,220(sp) +80003a90: 02412783 lw a5,36(sp) +80003a94: fffbc603 lbu a2,-1(s7) +80003a98: 00f7c583 lbu a1,15(a5) +80003a9c: 02b61063 bne a2,a1,80003abc <_vfprintf_r+0x26a4> +80003aa0: 03000513 li a0,48 +80003aa4: fea68fa3 sb a0,-1(a3) +80003aa8: 0dc12683 lw a3,220(sp) +80003aac: fff68793 addi a5,a3,-1 +80003ab0: 0cf12e23 sw a5,220(sp) +80003ab4: fff6c603 lbu a2,-1(a3) +80003ab8: fec586e3 beq a1,a2,80003aa4 <_vfprintf_r+0x268c> +80003abc: 00160593 addi a1,a2,1 +80003ac0: 03900513 li a0,57 +80003ac4: 0ff5f593 andi a1,a1,255 +80003ac8: 00a60663 beq a2,a0,80003ad4 <_vfprintf_r+0x26bc> +80003acc: feb68fa3 sb a1,-1(a3) +80003ad0: ba5ff06f j 80003674 <_vfprintf_r+0x225c> +80003ad4: 02412783 lw a5,36(sp) +80003ad8: 00a7c583 lbu a1,10(a5) +80003adc: feb68fa3 sb a1,-1(a3) +80003ae0: b95ff06f j 80003674 <_vfprintf_r+0x225c> +80003ae4: 03000793 li a5,48 +80003ae8: 0cf10423 sb a5,200(sp) +80003aec: 07800793 li a5,120 +80003af0: fd8ff06f j 800032c8 <_vfprintf_r+0x1eb0> +80003af4: 04700793 li a5,71 +80003af8: 01bb0933 add s2,s6,s11 +80003afc: 04f12223 sw a5,68(sp) +80003b00: 0a010c93 addi s9,sp,160 +80003b04: efdfd06f j 80001a00 <_vfprintf_r+0x5e8> +80003b08: 001d8593 addi a1,s11,1 +80003b0c: 000d0513 mv a0,s10 +80003b10: 01112823 sw a7,16(sp) +80003b14: 094040ef jal ra,80007ba8 <_malloc_r> +80003b18: 01012883 lw a7,16(sp) +80003b1c: 00050b13 mv s6,a0 +80003b20: 36050063 beqz a0,80003e80 <_vfprintf_r+0x2a68> +80003b24: 00a12823 sw a0,16(sp) +80003b28: fbcff06f j 800032e4 <_vfprintf_r+0x1ecc> +80003b2c: 000d9463 bnez s11,80003b34 <_vfprintf_r+0x271c> +80003b30: 00100d93 li s11,1 +80003b34: 0fc12303 lw t1,252(sp) +80003b38: 0f012e03 lw t3,240(sp) +80003b3c: 0f412e83 lw t4,244(sp) +80003b40: 0f812f03 lw t5,248(sp) +80003b44: 100a6913 ori s2,s4,256 +80003b48: c00346e3 bltz t1,80003754 <_vfprintf_r+0x233c> +80003b4c: 0b010a93 addi s5,sp,176 +80003b50: 0dc10813 addi a6,sp,220 +80003b54: 0d010793 addi a5,sp,208 +80003b58: 0cc10713 addi a4,sp,204 +80003b5c: 000d8693 mv a3,s11 +80003b60: 00200613 li a2,2 +80003b64: 000a8593 mv a1,s5 +80003b68: 000d0513 mv a0,s10 +80003b6c: 05112223 sw a7,68(sp) +80003b70: 0bc12823 sw t3,176(sp) +80003b74: 05c12023 sw t3,64(sp) +80003b78: 0bd12a23 sw t4,180(sp) +80003b7c: 03d12223 sw t4,36(sp) +80003b80: 0be12c23 sw t5,184(sp) +80003b84: 03e12023 sw t5,32(sp) +80003b88: 0a612e23 sw t1,188(sp) +80003b8c: 00612e23 sw t1,28(sp) +80003b90: 315020ef jal ra,800066a4 <_ldtoa_r> +80003b94: 01c12303 lw t1,28(sp) +80003b98: 03412423 sw s4,40(sp) +80003b9c: 02012f03 lw t5,32(sp) +80003ba0: 02412e83 lw t4,36(sp) +80003ba4: 04012e03 lw t3,64(sp) +80003ba8: 04412883 lw a7,68(sp) +80003bac: 00050b13 mv s6,a0 +80003bb0: 00090a13 mv s4,s2 +80003bb4: 04012c23 sw zero,88(sp) +80003bb8: 00012823 sw zero,16(sp) +80003bbc: c45ff06f j 80003800 <_vfprintf_r+0x23e8> +80003bc0: 00600d93 li s11,6 +80003bc4: d8dfd06f j 80001950 <_vfprintf_r+0x538> +80003bc8: 0b010a93 addi s5,sp,176 +80003bcc: 000a8513 mv a0,s5 +80003bd0: 05112a23 sw a7,84(sp) +80003bd4: 0bc12823 sw t3,176(sp) +80003bd8: 0bd12a23 sw t4,180(sp) +80003bdc: 0be12c23 sw t5,184(sp) +80003be0: 0a612e23 sw t1,188(sp) +80003be4: 299100ef jal ra,8001467c <__trunctfdf2> +80003be8: 0cc10613 addi a2,sp,204 +80003bec: 181050ef jal ra,8000956c +80003bf0: 00058613 mv a2,a1 +80003bf4: 00050593 mv a1,a0 +80003bf8: 000a8513 mv a0,s5 +80003bfc: 08d100ef jal ra,80014488 <__extenddftf2> +80003c00: 0b012783 lw a5,176(sp) +80003c04: 0a010c93 addi s9,sp,160 +80003c08: 09010913 addi s2,sp,144 +80003c0c: 08f12823 sw a5,144(sp) +80003c10: 0b412783 lw a5,180(sp) +80003c14: 08010613 addi a2,sp,128 +80003c18: 00090593 mv a1,s2 +80003c1c: 08f12a23 sw a5,148(sp) +80003c20: 0b812783 lw a5,184(sp) +80003c24: 000c8513 mv a0,s9 +80003c28: 04c12023 sw a2,64(sp) +80003c2c: 08f12c23 sw a5,152(sp) +80003c30: 0bc12783 lw a5,188(sp) +80003c34: 08012023 sw zero,128(sp) +80003c38: 08012223 sw zero,132(sp) +80003c3c: 08f12e23 sw a5,156(sp) +80003c40: 3ffc07b7 lui a5,0x3ffc0 +80003c44: 08f12623 sw a5,140(sp) +80003c48: 08012423 sw zero,136(sp) +80003c4c: 0b40e0ef jal ra,80011d00 <__multf3> +80003c50: 0a012803 lw a6,160(sp) +80003c54: 0a412e03 lw t3,164(sp) +80003c58: 0a812e83 lw t4,168(sp) +80003c5c: 0ac12f03 lw t5,172(sp) +80003c60: 000c8593 mv a1,s9 +80003c64: 000a8513 mv a0,s5 +80003c68: 0b012823 sw a6,176(sp) +80003c6c: 05012823 sw a6,80(sp) +80003c70: 0bc12a23 sw t3,180(sp) +80003c74: 03c12223 sw t3,36(sp) +80003c78: 0bd12c23 sw t4,184(sp) +80003c7c: 03d12023 sw t4,32(sp) +80003c80: 0be12e23 sw t5,188(sp) +80003c84: 01e12e23 sw t5,28(sp) +80003c88: 0a012023 sw zero,160(sp) +80003c8c: 0a012223 sw zero,164(sp) +80003c90: 0a012423 sw zero,168(sp) +80003c94: 0a012623 sw zero,172(sp) +80003c98: 5150d0ef jal ra,800119ac <__eqtf2> +80003c9c: 01c12f03 lw t5,28(sp) +80003ca0: 02012e83 lw t4,32(sp) +80003ca4: 02412e03 lw t3,36(sp) +80003ca8: 05012803 lw a6,80(sp) +80003cac: 05412883 lw a7,84(sp) +80003cb0: 00051663 bnez a0,80003cbc <_vfprintf_r+0x28a4> +80003cb4: 00100793 li a5,1 +80003cb8: 0cf12623 sw a5,204(sp) +80003cbc: 800157b7 lui a5,0x80015 +80003cc0: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +80003cc4: 02f12223 sw a5,36(sp) +80003cc8: f54ff06f j 8000341c <_vfprintf_r+0x2004> +80003ccc: 06700493 li s1,103 +80003cd0: 03c12603 lw a2,60(sp) +80003cd4: 0ff00693 li a3,255 +80003cd8: 00064783 lbu a5,0(a2) +80003cdc: 1ad78a63 beq a5,a3,80003e90 <_vfprintf_r+0x2a78> +80003ce0: 01c12703 lw a4,28(sp) +80003ce4: 00000513 li a0,0 +80003ce8: 00000593 li a1,0 +80003cec: 00e7de63 bge a5,a4,80003d08 <_vfprintf_r+0x28f0> +80003cf0: 40f70733 sub a4,a4,a5 +80003cf4: 00164783 lbu a5,1(a2) +80003cf8: 04078463 beqz a5,80003d40 <_vfprintf_r+0x2928> +80003cfc: 00158593 addi a1,a1,1 +80003d00: 00160613 addi a2,a2,1 +80003d04: fed794e3 bne a5,a3,80003cec <_vfprintf_r+0x28d4> +80003d08: 02c12e23 sw a2,60(sp) +80003d0c: 00e12e23 sw a4,28(sp) +80003d10: 02b12223 sw a1,36(sp) +80003d14: 02a12423 sw a0,40(sp) +80003d18: 02812703 lw a4,40(sp) +80003d1c: 02412783 lw a5,36(sp) +80003d20: 00e787b3 add a5,a5,a4 +80003d24: 04812703 lw a4,72(sp) +80003d28: 02e787b3 mul a5,a5,a4 +80003d2c: 01978cb3 add s9,a5,s9 +80003d30: fffcca93 not s5,s9 +80003d34: 41fada93 srai s5,s5,0x1f +80003d38: 015cfab3 and s5,s9,s5 +80003d3c: e6dfd06f j 80001ba8 <_vfprintf_r+0x790> +80003d40: 00064783 lbu a5,0(a2) +80003d44: 00150513 addi a0,a0,1 +80003d48: fbdff06f j 80003d04 <_vfprintf_r+0x28ec> +80003d4c: 00012823 sw zero,16(sp) +80003d50: 00078a13 mv s4,a5 +80003d54: a0dff06f j 80003760 <_vfprintf_r+0x2348> +80003d58: 02c12783 lw a5,44(sp) +80003d5c: 06600493 li s1,102 +80003d60: 00f70cb3 add s9,a4,a5 +80003d64: 01bc8cb3 add s9,s9,s11 +80003d68: bbdff06f j 80003924 <_vfprintf_r+0x250c> +80003d6c: 0d610693 addi a3,sp,214 +80003d70: 00061863 bnez a2,80003d80 <_vfprintf_r+0x2968> +80003d74: 03000693 li a3,48 +80003d78: 0cd10b23 sb a3,214(sp) +80003d7c: 0d710693 addi a3,sp,215 +80003d80: 1b010713 addi a4,sp,432 +80003d84: 03078793 addi a5,a5,48 +80003d88: 40e68633 sub a2,a3,a4 +80003d8c: 00f68023 sb a5,0(a3) +80003d90: 0dd60793 addi a5,a2,221 +80003d94: 02f12c23 sw a5,56(sp) +80003d98: dcdfd06f j 80001b64 <_vfprintf_r+0x74c> +80003d9c: 0a010c93 addi s9,sp,160 +80003da0: 000c8593 mv a1,s9 +80003da4: 000a8513 mv a0,s5 +80003da8: 05112823 sw a7,80(sp) +80003dac: 0bc12823 sw t3,176(sp) +80003db0: 05c12023 sw t3,64(sp) +80003db4: 0bd12a23 sw t4,180(sp) +80003db8: 03d12223 sw t4,36(sp) +80003dbc: 0be12c23 sw t5,184(sp) +80003dc0: 03e12023 sw t5,32(sp) +80003dc4: 0a612e23 sw t1,188(sp) +80003dc8: 00612e23 sw t1,28(sp) +80003dcc: 0a012023 sw zero,160(sp) +80003dd0: 0a012223 sw zero,164(sp) +80003dd4: 0a012423 sw zero,168(sp) +80003dd8: 0a012623 sw zero,172(sp) +80003ddc: 3d10d0ef jal ra,800119ac <__eqtf2> +80003de0: 01c12303 lw t1,28(sp) +80003de4: 02012f03 lw t5,32(sp) +80003de8: 02412e83 lw t4,36(sp) +80003dec: 04012e03 lw t3,64(sp) +80003df0: 05012883 lw a7,80(sp) +80003df4: aa0502e3 beqz a0,80003898 <_vfprintf_r+0x2480> +80003df8: 00100793 li a5,1 +80003dfc: 41b787b3 sub a5,a5,s11 +80003e00: 0cf12623 sw a5,204(sp) +80003e04: 00f90933 add s2,s2,a5 +80003e08: bf9fd06f j 80001a00 <_vfprintf_r+0x5e8> +80003e0c: 02812783 lw a5,40(sp) +80003e10: 0017f793 andi a5,a5,1 +80003e14: 00079463 bnez a5,80003e1c <_vfprintf_r+0x2a04> +80003e18: d6dfd06f j 80001b84 <_vfprintf_r+0x76c> +80003e1c: d61fd06f j 80001b7c <_vfprintf_r+0x764> +80003e20: 00079a63 bnez a5,80003e34 <_vfprintf_r+0x2a1c> +80003e24: 00100a93 li s5,1 +80003e28: 06600493 li s1,102 +80003e2c: 00100c93 li s9,1 +80003e30: 8edff06f j 8000371c <_vfprintf_r+0x2304> +80003e34: 02c12783 lw a5,44(sp) +80003e38: 06600493 li s1,102 +80003e3c: 00178c93 addi s9,a5,1 +80003e40: 01bc8cb3 add s9,s9,s11 +80003e44: fffcca93 not s5,s9 +80003e48: 41fada93 srai s5,s5,0x1f +80003e4c: 015cfab3 and s5,s9,s5 +80003e50: 8cdff06f j 8000371c <_vfprintf_r+0x2304> +80003e54: 00088713 mv a4,a7 +80003e58: bddfe06f j 80002a34 <_vfprintf_r+0x161c> +80003e5c: 01412783 lw a5,20(sp) +80003e60: 0007ad83 lw s11,0(a5) +80003e64: 00478793 addi a5,a5,4 +80003e68: 000dd463 bgez s11,80003e70 <_vfprintf_r+0x2a58> +80003e6c: fff00d93 li s11,-1 +80003e70: 00144483 lbu s1,1(s0) +80003e74: 00f12a23 sw a5,20(sp) +80003e78: 00070413 mv s0,a4 +80003e7c: f54fd06f j 800015d0 <_vfprintf_r+0x1b8> +80003e80: 00cc5783 lhu a5,12(s8) +80003e84: 0407e793 ori a5,a5,64 +80003e88: 00fc1623 sh a5,12(s8) +80003e8c: 8f1fd06f j 8000177c <_vfprintf_r+0x364> +80003e90: 02012423 sw zero,40(sp) +80003e94: 02012223 sw zero,36(sp) +80003e98: e81ff06f j 80003d18 <_vfprintf_r+0x2900> +80003e9c: 00200793 li a5,2 +80003ea0: 02f12c23 sw a5,56(sp) +80003ea4: cc1fd06f j 80001b64 <_vfprintf_r+0x74c> -80003f30 : -80003f30: 00050793 mv a5,a0 -80003f34: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -80003f38: 00060693 mv a3,a2 -80003f3c: 00058613 mv a2,a1 -80003f40: 00078593 mv a1,a5 -80003f44: d5cfd06f j 800014a0 <_vfprintf_r> +80003ea8 : +80003ea8: 00050793 mv a5,a0 +80003eac: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +80003eb0: 00060693 mv a3,a2 +80003eb4: 00058613 mv a2,a1 +80003eb8: 00078593 mv a1,a5 +80003ebc: d5cfd06f j 80001418 <_vfprintf_r> -80003f48 <__sbprintf>: -80003f48: 00c5d783 lhu a5,12(a1) -80003f4c: 0645ae03 lw t3,100(a1) -80003f50: 00e5d303 lhu t1,14(a1) -80003f54: 01c5a883 lw a7,28(a1) -80003f58: 0245a803 lw a6,36(a1) -80003f5c: b8010113 addi sp,sp,-1152 -80003f60: ffd7f793 andi a5,a5,-3 -80003f64: 40000713 li a4,1024 -80003f68: 46812c23 sw s0,1144(sp) -80003f6c: 00f11a23 sh a5,20(sp) -80003f70: 00058413 mv s0,a1 -80003f74: 07010793 addi a5,sp,112 -80003f78: 00810593 addi a1,sp,8 -80003f7c: 46912a23 sw s1,1140(sp) -80003f80: 47212823 sw s2,1136(sp) -80003f84: 46112e23 sw ra,1148(sp) -80003f88: 00050913 mv s2,a0 -80003f8c: 07c12623 sw t3,108(sp) -80003f90: 00611b23 sh t1,22(sp) -80003f94: 03112223 sw a7,36(sp) -80003f98: 03012623 sw a6,44(sp) -80003f9c: 00f12423 sw a5,8(sp) -80003fa0: 00f12c23 sw a5,24(sp) -80003fa4: 00e12823 sw a4,16(sp) -80003fa8: 00e12e23 sw a4,28(sp) -80003fac: 02012023 sw zero,32(sp) -80003fb0: cf0fd0ef jal ra,800014a0 <_vfprintf_r> -80003fb4: 00050493 mv s1,a0 -80003fb8: 02055c63 bgez a0,80003ff0 <__sbprintf+0xa8> -80003fbc: 01415783 lhu a5,20(sp) -80003fc0: 0407f793 andi a5,a5,64 -80003fc4: 00078863 beqz a5,80003fd4 <__sbprintf+0x8c> -80003fc8: 00c45783 lhu a5,12(s0) -80003fcc: 0407e793 ori a5,a5,64 -80003fd0: 00f41623 sh a5,12(s0) -80003fd4: 47c12083 lw ra,1148(sp) -80003fd8: 47812403 lw s0,1144(sp) -80003fdc: 47012903 lw s2,1136(sp) -80003fe0: 00048513 mv a0,s1 -80003fe4: 47412483 lw s1,1140(sp) -80003fe8: 48010113 addi sp,sp,1152 -80003fec: 00008067 ret -80003ff0: 00810593 addi a1,sp,8 -80003ff4: 00090513 mv a0,s2 -80003ff8: 580000ef jal ra,80004578 <_fflush_r> -80003ffc: fc0500e3 beqz a0,80003fbc <__sbprintf+0x74> -80004000: fff00493 li s1,-1 -80004004: fb9ff06f j 80003fbc <__sbprintf+0x74> +80003ec0 <__sbprintf>: +80003ec0: 00c5d783 lhu a5,12(a1) +80003ec4: 0645ae03 lw t3,100(a1) +80003ec8: 00e5d303 lhu t1,14(a1) +80003ecc: 01c5a883 lw a7,28(a1) +80003ed0: 0245a803 lw a6,36(a1) +80003ed4: b8010113 addi sp,sp,-1152 +80003ed8: ffd7f793 andi a5,a5,-3 +80003edc: 40000713 li a4,1024 +80003ee0: 46812c23 sw s0,1144(sp) +80003ee4: 00f11a23 sh a5,20(sp) +80003ee8: 00058413 mv s0,a1 +80003eec: 07010793 addi a5,sp,112 +80003ef0: 00810593 addi a1,sp,8 +80003ef4: 46912a23 sw s1,1140(sp) +80003ef8: 47212823 sw s2,1136(sp) +80003efc: 46112e23 sw ra,1148(sp) +80003f00: 00050913 mv s2,a0 +80003f04: 07c12623 sw t3,108(sp) +80003f08: 00611b23 sh t1,22(sp) +80003f0c: 03112223 sw a7,36(sp) +80003f10: 03012623 sw a6,44(sp) +80003f14: 00f12423 sw a5,8(sp) +80003f18: 00f12c23 sw a5,24(sp) +80003f1c: 00e12823 sw a4,16(sp) +80003f20: 00e12e23 sw a4,28(sp) +80003f24: 02012023 sw zero,32(sp) +80003f28: cf0fd0ef jal ra,80001418 <_vfprintf_r> +80003f2c: 00050493 mv s1,a0 +80003f30: 02055c63 bgez a0,80003f68 <__sbprintf+0xa8> +80003f34: 01415783 lhu a5,20(sp) +80003f38: 0407f793 andi a5,a5,64 +80003f3c: 00078863 beqz a5,80003f4c <__sbprintf+0x8c> +80003f40: 00c45783 lhu a5,12(s0) +80003f44: 0407e793 ori a5,a5,64 +80003f48: 00f41623 sh a5,12(s0) +80003f4c: 47c12083 lw ra,1148(sp) +80003f50: 47812403 lw s0,1144(sp) +80003f54: 47012903 lw s2,1136(sp) +80003f58: 00048513 mv a0,s1 +80003f5c: 47412483 lw s1,1140(sp) +80003f60: 48010113 addi sp,sp,1152 +80003f64: 00008067 ret +80003f68: 00810593 addi a1,sp,8 +80003f6c: 00090513 mv a0,s2 +80003f70: 4fc000ef jal ra,8000446c <_fflush_r> +80003f74: fc0500e3 beqz a0,80003f34 <__sbprintf+0x74> +80003f78: fff00493 li s1,-1 +80003f7c: fb9ff06f j 80003f34 <__sbprintf+0x74> -80004008 <__swsetup_r>: -80004008: 3601a783 lw a5,864(gp) # 80016b68 <_impure_ptr> -8000400c: ff010113 addi sp,sp,-16 -80004010: 00812423 sw s0,8(sp) -80004014: 00912223 sw s1,4(sp) -80004018: 00112623 sw ra,12(sp) -8000401c: 00050493 mv s1,a0 -80004020: 00058413 mv s0,a1 -80004024: 00078663 beqz a5,80004030 <__swsetup_r+0x28> -80004028: 0387a703 lw a4,56(a5) -8000402c: 0e070063 beqz a4,8000410c <__swsetup_r+0x104> -80004030: 00c41703 lh a4,12(s0) -80004034: 01071793 slli a5,a4,0x10 -80004038: 00877693 andi a3,a4,8 -8000403c: 0107d793 srli a5,a5,0x10 -80004040: 04068063 beqz a3,80004080 <__swsetup_r+0x78> -80004044: 01042683 lw a3,16(s0) -80004048: 06068063 beqz a3,800040a8 <__swsetup_r+0xa0> -8000404c: 0017f613 andi a2,a5,1 -80004050: 08060463 beqz a2,800040d8 <__swsetup_r+0xd0> -80004054: 01442603 lw a2,20(s0) -80004058: 00042423 sw zero,8(s0) -8000405c: 00000513 li a0,0 -80004060: 40c00633 neg a2,a2 -80004064: 00c42c23 sw a2,24(s0) -80004068: 08068663 beqz a3,800040f4 <__swsetup_r+0xec> -8000406c: 00c12083 lw ra,12(sp) -80004070: 00812403 lw s0,8(sp) -80004074: 00412483 lw s1,4(sp) -80004078: 01010113 addi sp,sp,16 -8000407c: 00008067 ret -80004080: 0107f693 andi a3,a5,16 -80004084: 0c068463 beqz a3,8000414c <__swsetup_r+0x144> -80004088: 0047f793 andi a5,a5,4 -8000408c: 08079663 bnez a5,80004118 <__swsetup_r+0x110> -80004090: 01042683 lw a3,16(s0) -80004094: 00876713 ori a4,a4,8 -80004098: 01071793 slli a5,a4,0x10 -8000409c: 00e41623 sh a4,12(s0) -800040a0: 0107d793 srli a5,a5,0x10 -800040a4: fa0694e3 bnez a3,8000404c <__swsetup_r+0x44> -800040a8: 2807f613 andi a2,a5,640 -800040ac: 20000593 li a1,512 -800040b0: f8b60ee3 beq a2,a1,8000404c <__swsetup_r+0x44> -800040b4: 00040593 mv a1,s0 -800040b8: 00048513 mv a0,s1 -800040bc: 315030ef jal ra,80007bd0 <__smakebuf_r> -800040c0: 00c41703 lh a4,12(s0) -800040c4: 01042683 lw a3,16(s0) -800040c8: 01071793 slli a5,a4,0x10 -800040cc: 0107d793 srli a5,a5,0x10 -800040d0: 0017f613 andi a2,a5,1 -800040d4: f80610e3 bnez a2,80004054 <__swsetup_r+0x4c> -800040d8: 0027f613 andi a2,a5,2 -800040dc: 00000593 li a1,0 -800040e0: 00061463 bnez a2,800040e8 <__swsetup_r+0xe0> -800040e4: 01442583 lw a1,20(s0) -800040e8: 00b42423 sw a1,8(s0) -800040ec: 00000513 li a0,0 -800040f0: f6069ee3 bnez a3,8000406c <__swsetup_r+0x64> -800040f4: 0807f793 andi a5,a5,128 -800040f8: f6078ae3 beqz a5,8000406c <__swsetup_r+0x64> -800040fc: 04076713 ori a4,a4,64 -80004100: 00e41623 sh a4,12(s0) -80004104: fff00513 li a0,-1 -80004108: f65ff06f j 8000406c <__swsetup_r+0x64> -8000410c: 00078513 mv a0,a5 -80004110: 005000ef jal ra,80004914 <__sinit> -80004114: f1dff06f j 80004030 <__swsetup_r+0x28> -80004118: 03042583 lw a1,48(s0) -8000411c: 00058e63 beqz a1,80004138 <__swsetup_r+0x130> -80004120: 04040793 addi a5,s0,64 -80004124: 00f58863 beq a1,a5,80004134 <__swsetup_r+0x12c> -80004128: 00048513 mv a0,s1 -8000412c: 159000ef jal ra,80004a84 <_free_r> -80004130: 00c41703 lh a4,12(s0) -80004134: 02042823 sw zero,48(s0) -80004138: 01042683 lw a3,16(s0) -8000413c: fdb77713 andi a4,a4,-37 -80004140: 00042223 sw zero,4(s0) -80004144: 00d42023 sw a3,0(s0) -80004148: f4dff06f j 80004094 <__swsetup_r+0x8c> -8000414c: 00900793 li a5,9 -80004150: 00f4a023 sw a5,0(s1) -80004154: 04076713 ori a4,a4,64 -80004158: 00e41623 sh a4,12(s0) -8000415c: fff00513 li a0,-1 -80004160: f0dff06f j 8000406c <__swsetup_r+0x64> +80003f80 <__swsetup_r>: +80003f80: 3601a783 lw a5,864(gp) # 80016b68 <_impure_ptr> +80003f84: ff010113 addi sp,sp,-16 +80003f88: 00812423 sw s0,8(sp) +80003f8c: 00912223 sw s1,4(sp) +80003f90: 00112623 sw ra,12(sp) +80003f94: 00050493 mv s1,a0 +80003f98: 00058413 mv s0,a1 +80003f9c: 00078663 beqz a5,80003fa8 <__swsetup_r+0x28> +80003fa0: 0387a703 lw a4,56(a5) +80003fa4: 0e070063 beqz a4,80004084 <__swsetup_r+0x104> +80003fa8: 00c41703 lh a4,12(s0) +80003fac: 01071793 slli a5,a4,0x10 +80003fb0: 00877693 andi a3,a4,8 +80003fb4: 0107d793 srli a5,a5,0x10 +80003fb8: 04068063 beqz a3,80003ff8 <__swsetup_r+0x78> +80003fbc: 01042683 lw a3,16(s0) +80003fc0: 06068063 beqz a3,80004020 <__swsetup_r+0xa0> +80003fc4: 0017f613 andi a2,a5,1 +80003fc8: 08060463 beqz a2,80004050 <__swsetup_r+0xd0> +80003fcc: 01442603 lw a2,20(s0) +80003fd0: 00042423 sw zero,8(s0) +80003fd4: 00000513 li a0,0 +80003fd8: 40c00633 neg a2,a2 +80003fdc: 00c42c23 sw a2,24(s0) +80003fe0: 08068663 beqz a3,8000406c <__swsetup_r+0xec> +80003fe4: 00c12083 lw ra,12(sp) +80003fe8: 00812403 lw s0,8(sp) +80003fec: 00412483 lw s1,4(sp) +80003ff0: 01010113 addi sp,sp,16 +80003ff4: 00008067 ret +80003ff8: 0107f693 andi a3,a5,16 +80003ffc: 0c068463 beqz a3,800040c4 <__swsetup_r+0x144> +80004000: 0047f793 andi a5,a5,4 +80004004: 08079663 bnez a5,80004090 <__swsetup_r+0x110> +80004008: 01042683 lw a3,16(s0) +8000400c: 00876713 ori a4,a4,8 +80004010: 01071793 slli a5,a4,0x10 +80004014: 00e41623 sh a4,12(s0) +80004018: 0107d793 srli a5,a5,0x10 +8000401c: fa0694e3 bnez a3,80003fc4 <__swsetup_r+0x44> +80004020: 2807f613 andi a2,a5,640 +80004024: 20000593 li a1,512 +80004028: f8b60ee3 beq a2,a1,80003fc4 <__swsetup_r+0x44> +8000402c: 00040593 mv a1,s0 +80004030: 00048513 mv a0,s1 +80004034: 255030ef jal ra,80007a88 <__smakebuf_r> +80004038: 00c41703 lh a4,12(s0) +8000403c: 01042683 lw a3,16(s0) +80004040: 01071793 slli a5,a4,0x10 +80004044: 0107d793 srli a5,a5,0x10 +80004048: 0017f613 andi a2,a5,1 +8000404c: f80610e3 bnez a2,80003fcc <__swsetup_r+0x4c> +80004050: 0027f613 andi a2,a5,2 +80004054: 00000593 li a1,0 +80004058: 00061463 bnez a2,80004060 <__swsetup_r+0xe0> +8000405c: 01442583 lw a1,20(s0) +80004060: 00b42423 sw a1,8(s0) +80004064: 00000513 li a0,0 +80004068: f6069ee3 bnez a3,80003fe4 <__swsetup_r+0x64> +8000406c: 0807f793 andi a5,a5,128 +80004070: f6078ae3 beqz a5,80003fe4 <__swsetup_r+0x64> +80004074: 04076713 ori a4,a4,64 +80004078: 00e41623 sh a4,12(s0) +8000407c: fff00513 li a0,-1 +80004080: f65ff06f j 80003fe4 <__swsetup_r+0x64> +80004084: 00078513 mv a0,a5 +80004088: 780000ef jal ra,80004808 <__sinit> +8000408c: f1dff06f j 80003fa8 <__swsetup_r+0x28> +80004090: 03042583 lw a1,48(s0) +80004094: 00058e63 beqz a1,800040b0 <__swsetup_r+0x130> +80004098: 04040793 addi a5,s0,64 +8000409c: 00f58863 beq a1,a5,800040ac <__swsetup_r+0x12c> +800040a0: 00048513 mv a0,s1 +800040a4: 131000ef jal ra,800049d4 <_free_r> +800040a8: 00c41703 lh a4,12(s0) +800040ac: 02042823 sw zero,48(s0) +800040b0: 01042683 lw a3,16(s0) +800040b4: fdb77713 andi a4,a4,-37 +800040b8: 00042223 sw zero,4(s0) +800040bc: 00d42023 sw a3,0(s0) +800040c0: f4dff06f j 8000400c <__swsetup_r+0x8c> +800040c4: 00900793 li a5,9 +800040c8: 00f4a023 sw a5,0(s1) +800040cc: 04076713 ori a4,a4,64 +800040d0: 00e41623 sh a4,12(s0) +800040d4: fff00513 li a0,-1 +800040d8: f0dff06f j 80003fe4 <__swsetup_r+0x64> -80004164 <__register_exitproc>: -80004164: 3501a703 lw a4,848(gp) # 80016b58 <_global_impure_ptr> -80004168: 14872783 lw a5,328(a4) -8000416c: 04078c63 beqz a5,800041c4 <__register_exitproc+0x60> -80004170: 0047a703 lw a4,4(a5) -80004174: 01f00813 li a6,31 -80004178: 06e84e63 blt a6,a4,800041f4 <__register_exitproc+0x90> -8000417c: 00271813 slli a6,a4,0x2 -80004180: 02050663 beqz a0,800041ac <__register_exitproc+0x48> -80004184: 01078333 add t1,a5,a6 -80004188: 08c32423 sw a2,136(t1) -8000418c: 1887a883 lw a7,392(a5) -80004190: 00100613 li a2,1 -80004194: 00e61633 sll a2,a2,a4 -80004198: 00c8e8b3 or a7,a7,a2 -8000419c: 1917a423 sw a7,392(a5) -800041a0: 10d32423 sw a3,264(t1) -800041a4: 00200693 li a3,2 -800041a8: 02d50463 beq a0,a3,800041d0 <__register_exitproc+0x6c> -800041ac: 00170713 addi a4,a4,1 -800041b0: 00e7a223 sw a4,4(a5) -800041b4: 010787b3 add a5,a5,a6 -800041b8: 00b7a423 sw a1,8(a5) -800041bc: 00000513 li a0,0 -800041c0: 00008067 ret -800041c4: 14c70793 addi a5,a4,332 -800041c8: 14f72423 sw a5,328(a4) -800041cc: fa5ff06f j 80004170 <__register_exitproc+0xc> -800041d0: 18c7a683 lw a3,396(a5) -800041d4: 00170713 addi a4,a4,1 -800041d8: 00e7a223 sw a4,4(a5) -800041dc: 00c6e633 or a2,a3,a2 -800041e0: 18c7a623 sw a2,396(a5) -800041e4: 010787b3 add a5,a5,a6 -800041e8: 00b7a423 sw a1,8(a5) -800041ec: 00000513 li a0,0 -800041f0: 00008067 ret -800041f4: fff00513 li a0,-1 -800041f8: 00008067 ret +800040dc <__call_exitprocs>: +800040dc: fd010113 addi sp,sp,-48 +800040e0: 01412c23 sw s4,24(sp) +800040e4: 3501aa03 lw s4,848(gp) # 80016b58 <_global_impure_ptr> +800040e8: 03212023 sw s2,32(sp) +800040ec: 02112623 sw ra,44(sp) +800040f0: 148a2903 lw s2,328(s4) +800040f4: 02812423 sw s0,40(sp) +800040f8: 02912223 sw s1,36(sp) +800040fc: 01312e23 sw s3,28(sp) +80004100: 01512a23 sw s5,20(sp) +80004104: 01612823 sw s6,16(sp) +80004108: 01712623 sw s7,12(sp) +8000410c: 01812423 sw s8,8(sp) +80004110: 04090063 beqz s2,80004150 <__call_exitprocs+0x74> +80004114: 00050b13 mv s6,a0 +80004118: 00058b93 mv s7,a1 +8000411c: 00100a93 li s5,1 +80004120: fff00993 li s3,-1 +80004124: 00492483 lw s1,4(s2) # 3ffe0004 <_start-0x4001fffc> +80004128: fff48413 addi s0,s1,-1 +8000412c: 02044263 bltz s0,80004150 <__call_exitprocs+0x74> +80004130: 00249493 slli s1,s1,0x2 +80004134: 009904b3 add s1,s2,s1 +80004138: 040b8463 beqz s7,80004180 <__call_exitprocs+0xa4> +8000413c: 1044a783 lw a5,260(s1) +80004140: 05778063 beq a5,s7,80004180 <__call_exitprocs+0xa4> +80004144: fff40413 addi s0,s0,-1 +80004148: ffc48493 addi s1,s1,-4 +8000414c: ff3416e3 bne s0,s3,80004138 <__call_exitprocs+0x5c> +80004150: 02c12083 lw ra,44(sp) +80004154: 02812403 lw s0,40(sp) +80004158: 02412483 lw s1,36(sp) +8000415c: 02012903 lw s2,32(sp) +80004160: 01c12983 lw s3,28(sp) +80004164: 01812a03 lw s4,24(sp) +80004168: 01412a83 lw s5,20(sp) +8000416c: 01012b03 lw s6,16(sp) +80004170: 00c12b83 lw s7,12(sp) +80004174: 00812c03 lw s8,8(sp) +80004178: 03010113 addi sp,sp,48 +8000417c: 00008067 ret +80004180: 00492783 lw a5,4(s2) +80004184: 0044a683 lw a3,4(s1) +80004188: fff78793 addi a5,a5,-1 +8000418c: 04878e63 beq a5,s0,800041e8 <__call_exitprocs+0x10c> +80004190: 0004a223 sw zero,4(s1) +80004194: fa0688e3 beqz a3,80004144 <__call_exitprocs+0x68> +80004198: 18892783 lw a5,392(s2) +8000419c: 008a9733 sll a4,s5,s0 +800041a0: 00492c03 lw s8,4(s2) +800041a4: 00f777b3 and a5,a4,a5 +800041a8: 02079263 bnez a5,800041cc <__call_exitprocs+0xf0> +800041ac: 000680e7 jalr a3 +800041b0: 00492703 lw a4,4(s2) +800041b4: 148a2783 lw a5,328(s4) +800041b8: 01871463 bne a4,s8,800041c0 <__call_exitprocs+0xe4> +800041bc: f8f904e3 beq s2,a5,80004144 <__call_exitprocs+0x68> +800041c0: f80788e3 beqz a5,80004150 <__call_exitprocs+0x74> +800041c4: 00078913 mv s2,a5 +800041c8: f5dff06f j 80004124 <__call_exitprocs+0x48> +800041cc: 18c92783 lw a5,396(s2) +800041d0: 0844a583 lw a1,132(s1) +800041d4: 00f77733 and a4,a4,a5 +800041d8: 00071c63 bnez a4,800041f0 <__call_exitprocs+0x114> +800041dc: 000b0513 mv a0,s6 +800041e0: 000680e7 jalr a3 +800041e4: fcdff06f j 800041b0 <__call_exitprocs+0xd4> +800041e8: 00892223 sw s0,4(s2) +800041ec: fa9ff06f j 80004194 <__call_exitprocs+0xb8> +800041f0: 00058513 mv a0,a1 +800041f4: 000680e7 jalr a3 +800041f8: fb9ff06f j 800041b0 <__call_exitprocs+0xd4> -800041fc <__call_exitprocs>: -800041fc: fd010113 addi sp,sp,-48 -80004200: 01412c23 sw s4,24(sp) -80004204: 3501aa03 lw s4,848(gp) # 80016b58 <_global_impure_ptr> -80004208: 03212023 sw s2,32(sp) -8000420c: 02112623 sw ra,44(sp) -80004210: 148a2903 lw s2,328(s4) -80004214: 02812423 sw s0,40(sp) -80004218: 02912223 sw s1,36(sp) -8000421c: 01312e23 sw s3,28(sp) -80004220: 01512a23 sw s5,20(sp) -80004224: 01612823 sw s6,16(sp) -80004228: 01712623 sw s7,12(sp) -8000422c: 01812423 sw s8,8(sp) -80004230: 04090063 beqz s2,80004270 <__call_exitprocs+0x74> -80004234: 00050b13 mv s6,a0 -80004238: 00058b93 mv s7,a1 -8000423c: 00100a93 li s5,1 -80004240: fff00993 li s3,-1 -80004244: 00492483 lw s1,4(s2) # 3ffe0004 <_start-0x4001fffc> -80004248: fff48413 addi s0,s1,-1 -8000424c: 02044263 bltz s0,80004270 <__call_exitprocs+0x74> -80004250: 00249493 slli s1,s1,0x2 -80004254: 009904b3 add s1,s2,s1 -80004258: 040b8463 beqz s7,800042a0 <__call_exitprocs+0xa4> -8000425c: 1044a783 lw a5,260(s1) -80004260: 05778063 beq a5,s7,800042a0 <__call_exitprocs+0xa4> -80004264: fff40413 addi s0,s0,-1 -80004268: ffc48493 addi s1,s1,-4 -8000426c: ff3416e3 bne s0,s3,80004258 <__call_exitprocs+0x5c> -80004270: 02c12083 lw ra,44(sp) -80004274: 02812403 lw s0,40(sp) -80004278: 02412483 lw s1,36(sp) -8000427c: 02012903 lw s2,32(sp) -80004280: 01c12983 lw s3,28(sp) -80004284: 01812a03 lw s4,24(sp) -80004288: 01412a83 lw s5,20(sp) -8000428c: 01012b03 lw s6,16(sp) -80004290: 00c12b83 lw s7,12(sp) -80004294: 00812c03 lw s8,8(sp) -80004298: 03010113 addi sp,sp,48 -8000429c: 00008067 ret -800042a0: 00492783 lw a5,4(s2) -800042a4: 0044a683 lw a3,4(s1) -800042a8: fff78793 addi a5,a5,-1 -800042ac: 04878e63 beq a5,s0,80004308 <__call_exitprocs+0x10c> -800042b0: 0004a223 sw zero,4(s1) -800042b4: fa0688e3 beqz a3,80004264 <__call_exitprocs+0x68> -800042b8: 18892783 lw a5,392(s2) -800042bc: 008a9733 sll a4,s5,s0 -800042c0: 00492c03 lw s8,4(s2) -800042c4: 00f777b3 and a5,a4,a5 -800042c8: 02079263 bnez a5,800042ec <__call_exitprocs+0xf0> -800042cc: 000680e7 jalr a3 -800042d0: 00492703 lw a4,4(s2) -800042d4: 148a2783 lw a5,328(s4) -800042d8: 01871463 bne a4,s8,800042e0 <__call_exitprocs+0xe4> -800042dc: f8f904e3 beq s2,a5,80004264 <__call_exitprocs+0x68> -800042e0: f80788e3 beqz a5,80004270 <__call_exitprocs+0x74> -800042e4: 00078913 mv s2,a5 -800042e8: f5dff06f j 80004244 <__call_exitprocs+0x48> -800042ec: 18c92783 lw a5,396(s2) -800042f0: 0844a583 lw a1,132(s1) -800042f4: 00f77733 and a4,a4,a5 -800042f8: 00071c63 bnez a4,80004310 <__call_exitprocs+0x114> -800042fc: 000b0513 mv a0,s6 -80004300: 000680e7 jalr a3 -80004304: fcdff06f j 800042d0 <__call_exitprocs+0xd4> -80004308: 00892223 sw s0,4(s2) -8000430c: fa9ff06f j 800042b4 <__call_exitprocs+0xb8> -80004310: 00058513 mv a0,a1 -80004314: 000680e7 jalr a3 -80004318: fb9ff06f j 800042d0 <__call_exitprocs+0xd4> +800041fc : +800041fc: 00050593 mv a1,a0 +80004200: 00000693 li a3,0 +80004204: 00000613 li a2,0 +80004208: 00000513 li a0,0 +8000420c: 7280906f j 8000d934 <__register_exitproc> -8000431c <__sflush_r>: -8000431c: 00c59783 lh a5,12(a1) -80004320: fe010113 addi sp,sp,-32 -80004324: 00812c23 sw s0,24(sp) -80004328: 01312623 sw s3,12(sp) -8000432c: 00112e23 sw ra,28(sp) -80004330: 00912a23 sw s1,20(sp) -80004334: 01212823 sw s2,16(sp) -80004338: 0087f693 andi a3,a5,8 -8000433c: 00058413 mv s0,a1 -80004340: 00050993 mv s3,a0 -80004344: 10069a63 bnez a3,80004458 <__sflush_r+0x13c> -80004348: 00001737 lui a4,0x1 -8000434c: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> -80004350: 0045a683 lw a3,4(a1) -80004354: 00e7e7b3 or a5,a5,a4 -80004358: 00f59623 sh a5,12(a1) -8000435c: 18d05463 blez a3,800044e4 <__sflush_r+0x1c8> -80004360: 02842703 lw a4,40(s0) -80004364: 0c070a63 beqz a4,80004438 <__sflush_r+0x11c> -80004368: 0009a483 lw s1,0(s3) -8000436c: 01079693 slli a3,a5,0x10 -80004370: 0009a023 sw zero,0(s3) -80004374: 01379613 slli a2,a5,0x13 -80004378: 01c42583 lw a1,28(s0) -8000437c: 0106d693 srli a3,a3,0x10 -80004380: 16064863 bltz a2,800044f0 <__sflush_r+0x1d4> -80004384: 00100693 li a3,1 -80004388: 00000613 li a2,0 -8000438c: 00098513 mv a0,s3 -80004390: 000700e7 jalr a4 -80004394: fff00793 li a5,-1 -80004398: 18f50c63 beq a0,a5,80004530 <__sflush_r+0x214> -8000439c: 00c45683 lhu a3,12(s0) -800043a0: 02842703 lw a4,40(s0) -800043a4: 01c42583 lw a1,28(s0) -800043a8: 0046f693 andi a3,a3,4 -800043ac: 00068e63 beqz a3,800043c8 <__sflush_r+0xac> -800043b0: 00442683 lw a3,4(s0) -800043b4: 03042783 lw a5,48(s0) -800043b8: 40d50533 sub a0,a0,a3 -800043bc: 00078663 beqz a5,800043c8 <__sflush_r+0xac> -800043c0: 03c42783 lw a5,60(s0) -800043c4: 40f50533 sub a0,a0,a5 -800043c8: 00050613 mv a2,a0 -800043cc: 00000693 li a3,0 -800043d0: 00098513 mv a0,s3 -800043d4: 000700e7 jalr a4 -800043d8: fff00793 li a5,-1 -800043dc: 10f51e63 bne a0,a5,800044f8 <__sflush_r+0x1dc> -800043e0: 0009a703 lw a4,0(s3) -800043e4: 00c41783 lh a5,12(s0) -800043e8: 16070863 beqz a4,80004558 <__sflush_r+0x23c> -800043ec: 01d00693 li a3,29 -800043f0: 00d70663 beq a4,a3,800043fc <__sflush_r+0xe0> -800043f4: 01600693 li a3,22 -800043f8: 0cd71463 bne a4,a3,800044c0 <__sflush_r+0x1a4> +80004210 <__sflush_r>: +80004210: 00c59783 lh a5,12(a1) +80004214: fe010113 addi sp,sp,-32 +80004218: 00812c23 sw s0,24(sp) +8000421c: 01312623 sw s3,12(sp) +80004220: 00112e23 sw ra,28(sp) +80004224: 00912a23 sw s1,20(sp) +80004228: 01212823 sw s2,16(sp) +8000422c: 0087f693 andi a3,a5,8 +80004230: 00058413 mv s0,a1 +80004234: 00050993 mv s3,a0 +80004238: 10069a63 bnez a3,8000434c <__sflush_r+0x13c> +8000423c: 00001737 lui a4,0x1 +80004240: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> +80004244: 0045a683 lw a3,4(a1) +80004248: 00e7e7b3 or a5,a5,a4 +8000424c: 00f59623 sh a5,12(a1) +80004250: 18d05463 blez a3,800043d8 <__sflush_r+0x1c8> +80004254: 02842703 lw a4,40(s0) +80004258: 0c070a63 beqz a4,8000432c <__sflush_r+0x11c> +8000425c: 0009a483 lw s1,0(s3) +80004260: 01079693 slli a3,a5,0x10 +80004264: 0009a023 sw zero,0(s3) +80004268: 01379613 slli a2,a5,0x13 +8000426c: 01c42583 lw a1,28(s0) +80004270: 0106d693 srli a3,a3,0x10 +80004274: 16064863 bltz a2,800043e4 <__sflush_r+0x1d4> +80004278: 00100693 li a3,1 +8000427c: 00000613 li a2,0 +80004280: 00098513 mv a0,s3 +80004284: 000700e7 jalr a4 +80004288: fff00793 li a5,-1 +8000428c: 18f50c63 beq a0,a5,80004424 <__sflush_r+0x214> +80004290: 00c45683 lhu a3,12(s0) +80004294: 02842703 lw a4,40(s0) +80004298: 01c42583 lw a1,28(s0) +8000429c: 0046f693 andi a3,a3,4 +800042a0: 00068e63 beqz a3,800042bc <__sflush_r+0xac> +800042a4: 00442683 lw a3,4(s0) +800042a8: 03042783 lw a5,48(s0) +800042ac: 40d50533 sub a0,a0,a3 +800042b0: 00078663 beqz a5,800042bc <__sflush_r+0xac> +800042b4: 03c42783 lw a5,60(s0) +800042b8: 40f50533 sub a0,a0,a5 +800042bc: 00050613 mv a2,a0 +800042c0: 00000693 li a3,0 +800042c4: 00098513 mv a0,s3 +800042c8: 000700e7 jalr a4 +800042cc: fff00793 li a5,-1 +800042d0: 10f51e63 bne a0,a5,800043ec <__sflush_r+0x1dc> +800042d4: 0009a703 lw a4,0(s3) +800042d8: 00c41783 lh a5,12(s0) +800042dc: 16070863 beqz a4,8000444c <__sflush_r+0x23c> +800042e0: 01d00693 li a3,29 +800042e4: 00d70663 beq a4,a3,800042f0 <__sflush_r+0xe0> +800042e8: 01600693 li a3,22 +800042ec: 0cd71463 bne a4,a3,800043b4 <__sflush_r+0x1a4> +800042f0: 01042683 lw a3,16(s0) +800042f4: fffff737 lui a4,0xfffff +800042f8: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> +800042fc: 00e7f7b3 and a5,a5,a4 +80004300: 00f41623 sh a5,12(s0) +80004304: 00042223 sw zero,4(s0) +80004308: 00d42023 sw a3,0(s0) +8000430c: 03042583 lw a1,48(s0) +80004310: 0099a023 sw s1,0(s3) +80004314: 00058c63 beqz a1,8000432c <__sflush_r+0x11c> +80004318: 04040793 addi a5,s0,64 +8000431c: 00f58663 beq a1,a5,80004328 <__sflush_r+0x118> +80004320: 00098513 mv a0,s3 +80004324: 6b0000ef jal ra,800049d4 <_free_r> +80004328: 02042823 sw zero,48(s0) +8000432c: 00000513 li a0,0 +80004330: 01c12083 lw ra,28(sp) +80004334: 01812403 lw s0,24(sp) +80004338: 01412483 lw s1,20(sp) +8000433c: 01012903 lw s2,16(sp) +80004340: 00c12983 lw s3,12(sp) +80004344: 02010113 addi sp,sp,32 +80004348: 00008067 ret +8000434c: 0105a903 lw s2,16(a1) +80004350: fc090ee3 beqz s2,8000432c <__sflush_r+0x11c> +80004354: 0005a483 lw s1,0(a1) +80004358: 01079713 slli a4,a5,0x10 +8000435c: 01075713 srli a4,a4,0x10 +80004360: 00377713 andi a4,a4,3 +80004364: 0125a023 sw s2,0(a1) +80004368: 412484b3 sub s1,s1,s2 +8000436c: 00000793 li a5,0 +80004370: 00071463 bnez a4,80004378 <__sflush_r+0x168> +80004374: 0145a783 lw a5,20(a1) +80004378: 00f42423 sw a5,8(s0) +8000437c: 00904863 bgtz s1,8000438c <__sflush_r+0x17c> +80004380: fadff06f j 8000432c <__sflush_r+0x11c> +80004384: 00a90933 add s2,s2,a0 +80004388: fa9052e3 blez s1,8000432c <__sflush_r+0x11c> +8000438c: 02442783 lw a5,36(s0) +80004390: 01c42583 lw a1,28(s0) +80004394: 00048693 mv a3,s1 +80004398: 00090613 mv a2,s2 +8000439c: 00098513 mv a0,s3 +800043a0: 000780e7 jalr a5 +800043a4: 40a484b3 sub s1,s1,a0 +800043a8: fca04ee3 bgtz a0,80004384 <__sflush_r+0x174> +800043ac: 00c45783 lhu a5,12(s0) +800043b0: fff00513 li a0,-1 +800043b4: 0407e793 ori a5,a5,64 +800043b8: 01c12083 lw ra,28(sp) +800043bc: 00f41623 sh a5,12(s0) +800043c0: 01812403 lw s0,24(sp) +800043c4: 01412483 lw s1,20(sp) +800043c8: 01012903 lw s2,16(sp) +800043cc: 00c12983 lw s3,12(sp) +800043d0: 02010113 addi sp,sp,32 +800043d4: 00008067 ret +800043d8: 03c5a703 lw a4,60(a1) +800043dc: e6e04ce3 bgtz a4,80004254 <__sflush_r+0x44> +800043e0: f4dff06f j 8000432c <__sflush_r+0x11c> +800043e4: 05042503 lw a0,80(s0) +800043e8: eb5ff06f j 8000429c <__sflush_r+0x8c> +800043ec: 00c45783 lhu a5,12(s0) +800043f0: fffff737 lui a4,0xfffff +800043f4: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> +800043f8: 00e7f7b3 and a5,a5,a4 800043fc: 01042683 lw a3,16(s0) -80004400: fffff737 lui a4,0xfffff -80004404: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bcf> -80004408: 00e7f7b3 and a5,a5,a4 -8000440c: 00f41623 sh a5,12(s0) -80004410: 00042223 sw zero,4(s0) -80004414: 00d42023 sw a3,0(s0) -80004418: 03042583 lw a1,48(s0) -8000441c: 0099a023 sw s1,0(s3) -80004420: 00058c63 beqz a1,80004438 <__sflush_r+0x11c> -80004424: 04040793 addi a5,s0,64 -80004428: 00f58663 beq a1,a5,80004434 <__sflush_r+0x118> -8000442c: 00098513 mv a0,s3 -80004430: 654000ef jal ra,80004a84 <_free_r> -80004434: 02042823 sw zero,48(s0) -80004438: 00000513 li a0,0 -8000443c: 01c12083 lw ra,28(sp) -80004440: 01812403 lw s0,24(sp) -80004444: 01412483 lw s1,20(sp) -80004448: 01012903 lw s2,16(sp) -8000444c: 00c12983 lw s3,12(sp) -80004450: 02010113 addi sp,sp,32 -80004454: 00008067 ret -80004458: 0105a903 lw s2,16(a1) -8000445c: fc090ee3 beqz s2,80004438 <__sflush_r+0x11c> -80004460: 0005a483 lw s1,0(a1) -80004464: 01079713 slli a4,a5,0x10 -80004468: 01075713 srli a4,a4,0x10 -8000446c: 00377713 andi a4,a4,3 -80004470: 0125a023 sw s2,0(a1) -80004474: 412484b3 sub s1,s1,s2 -80004478: 00000793 li a5,0 -8000447c: 00071463 bnez a4,80004484 <__sflush_r+0x168> -80004480: 0145a783 lw a5,20(a1) -80004484: 00f42423 sw a5,8(s0) -80004488: 00904863 bgtz s1,80004498 <__sflush_r+0x17c> -8000448c: fadff06f j 80004438 <__sflush_r+0x11c> -80004490: 00a90933 add s2,s2,a0 -80004494: fa9052e3 blez s1,80004438 <__sflush_r+0x11c> -80004498: 02442783 lw a5,36(s0) -8000449c: 01c42583 lw a1,28(s0) -800044a0: 00048693 mv a3,s1 -800044a4: 00090613 mv a2,s2 -800044a8: 00098513 mv a0,s3 -800044ac: 000780e7 jalr a5 -800044b0: 40a484b3 sub s1,s1,a0 -800044b4: fca04ee3 bgtz a0,80004490 <__sflush_r+0x174> -800044b8: 00c45783 lhu a5,12(s0) -800044bc: fff00513 li a0,-1 -800044c0: 0407e793 ori a5,a5,64 -800044c4: 01c12083 lw ra,28(sp) -800044c8: 00f41623 sh a5,12(s0) -800044cc: 01812403 lw s0,24(sp) -800044d0: 01412483 lw s1,20(sp) -800044d4: 01012903 lw s2,16(sp) -800044d8: 00c12983 lw s3,12(sp) -800044dc: 02010113 addi sp,sp,32 -800044e0: 00008067 ret -800044e4: 03c5a703 lw a4,60(a1) -800044e8: e6e04ce3 bgtz a4,80004360 <__sflush_r+0x44> -800044ec: f4dff06f j 80004438 <__sflush_r+0x11c> -800044f0: 05042503 lw a0,80(s0) -800044f4: eb5ff06f j 800043a8 <__sflush_r+0x8c> -800044f8: 00c45783 lhu a5,12(s0) -800044fc: fffff737 lui a4,0xfffff -80004500: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bcf> -80004504: 00e7f7b3 and a5,a5,a4 -80004508: 01042683 lw a3,16(s0) -8000450c: 01079793 slli a5,a5,0x10 -80004510: 4107d793 srai a5,a5,0x10 -80004514: 00f41623 sh a5,12(s0) -80004518: 00042223 sw zero,4(s0) -8000451c: 00d42023 sw a3,0(s0) -80004520: 01379713 slli a4,a5,0x13 -80004524: ee075ae3 bgez a4,80004418 <__sflush_r+0xfc> -80004528: 04a42823 sw a0,80(s0) -8000452c: eedff06f j 80004418 <__sflush_r+0xfc> -80004530: 0009a783 lw a5,0(s3) -80004534: e60784e3 beqz a5,8000439c <__sflush_r+0x80> -80004538: 01d00713 li a4,29 -8000453c: 02e78863 beq a5,a4,8000456c <__sflush_r+0x250> -80004540: 01600713 li a4,22 -80004544: 02e78463 beq a5,a4,8000456c <__sflush_r+0x250> -80004548: 00c45783 lhu a5,12(s0) -8000454c: 0407e793 ori a5,a5,64 -80004550: 00f41623 sh a5,12(s0) -80004554: ee9ff06f j 8000443c <__sflush_r+0x120> -80004558: fffff737 lui a4,0xfffff -8000455c: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bcf> -80004560: 01042683 lw a3,16(s0) -80004564: 00e7f7b3 and a5,a5,a4 -80004568: fadff06f j 80004514 <__sflush_r+0x1f8> -8000456c: 0099a023 sw s1,0(s3) -80004570: 00000513 li a0,0 -80004574: ec9ff06f j 8000443c <__sflush_r+0x120> +80004400: 01079793 slli a5,a5,0x10 +80004404: 4107d793 srai a5,a5,0x10 +80004408: 00f41623 sh a5,12(s0) +8000440c: 00042223 sw zero,4(s0) +80004410: 00d42023 sw a3,0(s0) +80004414: 01379713 slli a4,a5,0x13 +80004418: ee075ae3 bgez a4,8000430c <__sflush_r+0xfc> +8000441c: 04a42823 sw a0,80(s0) +80004420: eedff06f j 8000430c <__sflush_r+0xfc> +80004424: 0009a783 lw a5,0(s3) +80004428: e60784e3 beqz a5,80004290 <__sflush_r+0x80> +8000442c: 01d00713 li a4,29 +80004430: 02e78863 beq a5,a4,80004460 <__sflush_r+0x250> +80004434: 01600713 li a4,22 +80004438: 02e78463 beq a5,a4,80004460 <__sflush_r+0x250> +8000443c: 00c45783 lhu a5,12(s0) +80004440: 0407e793 ori a5,a5,64 +80004444: 00f41623 sh a5,12(s0) +80004448: ee9ff06f j 80004330 <__sflush_r+0x120> +8000444c: fffff737 lui a4,0xfffff +80004450: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> +80004454: 01042683 lw a3,16(s0) +80004458: 00e7f7b3 and a5,a5,a4 +8000445c: fadff06f j 80004408 <__sflush_r+0x1f8> +80004460: 0099a023 sw s1,0(s3) +80004464: 00000513 li a0,0 +80004468: ec9ff06f j 80004330 <__sflush_r+0x120> -80004578 <_fflush_r>: -80004578: fe010113 addi sp,sp,-32 -8000457c: 00812c23 sw s0,24(sp) -80004580: 00112e23 sw ra,28(sp) -80004584: 00050413 mv s0,a0 -80004588: 00050663 beqz a0,80004594 <_fflush_r+0x1c> -8000458c: 03852783 lw a5,56(a0) -80004590: 02078063 beqz a5,800045b0 <_fflush_r+0x38> -80004594: 00c59783 lh a5,12(a1) -80004598: 02079663 bnez a5,800045c4 <_fflush_r+0x4c> -8000459c: 01c12083 lw ra,28(sp) -800045a0: 01812403 lw s0,24(sp) -800045a4: 00000513 li a0,0 -800045a8: 02010113 addi sp,sp,32 -800045ac: 00008067 ret -800045b0: 00b12623 sw a1,12(sp) -800045b4: 360000ef jal ra,80004914 <__sinit> -800045b8: 00c12583 lw a1,12(sp) -800045bc: 00c59783 lh a5,12(a1) -800045c0: fc078ee3 beqz a5,8000459c <_fflush_r+0x24> -800045c4: 00040513 mv a0,s0 -800045c8: 01812403 lw s0,24(sp) -800045cc: 01c12083 lw ra,28(sp) -800045d0: 02010113 addi sp,sp,32 -800045d4: d49ff06f j 8000431c <__sflush_r> +8000446c <_fflush_r>: +8000446c: fe010113 addi sp,sp,-32 +80004470: 00812c23 sw s0,24(sp) +80004474: 00112e23 sw ra,28(sp) +80004478: 00050413 mv s0,a0 +8000447c: 00050663 beqz a0,80004488 <_fflush_r+0x1c> +80004480: 03852783 lw a5,56(a0) +80004484: 02078063 beqz a5,800044a4 <_fflush_r+0x38> +80004488: 00c59783 lh a5,12(a1) +8000448c: 02079663 bnez a5,800044b8 <_fflush_r+0x4c> +80004490: 01c12083 lw ra,28(sp) +80004494: 01812403 lw s0,24(sp) +80004498: 00000513 li a0,0 +8000449c: 02010113 addi sp,sp,32 +800044a0: 00008067 ret +800044a4: 00b12623 sw a1,12(sp) +800044a8: 360000ef jal ra,80004808 <__sinit> +800044ac: 00c12583 lw a1,12(sp) +800044b0: 00c59783 lh a5,12(a1) +800044b4: fc078ee3 beqz a5,80004490 <_fflush_r+0x24> +800044b8: 00040513 mv a0,s0 +800044bc: 01812403 lw s0,24(sp) +800044c0: 01c12083 lw ra,28(sp) +800044c4: 02010113 addi sp,sp,32 +800044c8: d49ff06f j 80004210 <__sflush_r> -800045d8 : -800045d8: 00050593 mv a1,a0 -800045dc: 00050663 beqz a0,800045e8 -800045e0: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -800045e4: f95ff06f j 80004578 <_fflush_r> -800045e8: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> -800045ec: 800045b7 lui a1,0x80004 -800045f0: 57858593 addi a1,a1,1400 # 80004578 <__BSS_END__+0xfffed948> -800045f4: 0350006f j 80004e28 <_fwalk_reent> +800044cc : +800044cc: 00050593 mv a1,a0 +800044d0: 00050663 beqz a0,800044dc +800044d4: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +800044d8: f95ff06f j 8000446c <_fflush_r> +800044dc: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> +800044e0: 800045b7 lui a1,0x80004 +800044e4: 46c58593 addi a1,a1,1132 # 8000446c <__BSS_END__+0xfffed830> +800044e8: 0910006f j 80004d78 <_fwalk_reent> -800045f8 <__fp_lock>: -800045f8: 00000513 li a0,0 -800045fc: 00008067 ret +800044ec <__fp_lock>: +800044ec: 00000513 li a0,0 +800044f0: 00008067 ret -80004600 <_cleanup_r>: -80004600: 8000e5b7 lui a1,0x8000e -80004604: cd058593 addi a1,a1,-816 # 8000dcd0 <__BSS_END__+0xffff70a0> -80004608: 0210006f j 80004e28 <_fwalk_reent> +800044f4 <_cleanup_r>: +800044f4: 8000e5b7 lui a1,0x8000e +800044f8: ad858593 addi a1,a1,-1320 # 8000dad8 <__BSS_END__+0xffff6e9c> +800044fc: 07d0006f j 80004d78 <_fwalk_reent> -8000460c <__sinit.part.0>: -8000460c: fe010113 addi sp,sp,-32 -80004610: 800047b7 lui a5,0x80004 -80004614: 00112e23 sw ra,28(sp) -80004618: 00812c23 sw s0,24(sp) -8000461c: 00912a23 sw s1,20(sp) -80004620: 01212823 sw s2,16(sp) -80004624: 01312623 sw s3,12(sp) -80004628: 01412423 sw s4,8(sp) -8000462c: 01512223 sw s5,4(sp) -80004630: 01612023 sw s6,0(sp) -80004634: 00452403 lw s0,4(a0) -80004638: 60078793 addi a5,a5,1536 # 80004600 <__BSS_END__+0xfffed9d0> -8000463c: 02f52e23 sw a5,60(a0) -80004640: 2ec50713 addi a4,a0,748 -80004644: 00300793 li a5,3 -80004648: 2ee52423 sw a4,744(a0) -8000464c: 2ef52223 sw a5,740(a0) -80004650: 2e052023 sw zero,736(a0) -80004654: 00400793 li a5,4 -80004658: 00050913 mv s2,a0 -8000465c: 00f42623 sw a5,12(s0) -80004660: 00800613 li a2,8 -80004664: 00000593 li a1,0 -80004668: 06042223 sw zero,100(s0) -8000466c: 00042023 sw zero,0(s0) -80004670: 00042223 sw zero,4(s0) -80004674: 00042423 sw zero,8(s0) -80004678: 00042823 sw zero,16(s0) -8000467c: 00042a23 sw zero,20(s0) -80004680: 00042c23 sw zero,24(s0) -80004684: 05c40513 addi a0,s0,92 -80004688: cb1fc0ef jal ra,80001338 -8000468c: 8000ab37 lui s6,0x8000a -80004690: 00892483 lw s1,8(s2) -80004694: 8000aab7 lui s5,0x8000a -80004698: 8000aa37 lui s4,0x8000a -8000469c: 8000a9b7 lui s3,0x8000a -800046a0: 830b0b13 addi s6,s6,-2000 # 80009830 <__BSS_END__+0xffff2c00> -800046a4: 894a8a93 addi s5,s5,-1900 # 80009894 <__BSS_END__+0xffff2c64> -800046a8: 91ca0a13 addi s4,s4,-1764 # 8000991c <__BSS_END__+0xffff2cec> -800046ac: 98498993 addi s3,s3,-1660 # 80009984 <__BSS_END__+0xffff2d54> -800046b0: 000107b7 lui a5,0x10 -800046b4: 03642023 sw s6,32(s0) -800046b8: 03542223 sw s5,36(s0) -800046bc: 03442423 sw s4,40(s0) -800046c0: 03342623 sw s3,44(s0) -800046c4: 00842e23 sw s0,28(s0) -800046c8: 00978793 addi a5,a5,9 # 10009 <_start-0x7ffefff7> -800046cc: 00f4a623 sw a5,12(s1) -800046d0: 00800613 li a2,8 +80004500 <__sinit.part.0>: +80004500: fe010113 addi sp,sp,-32 +80004504: 800047b7 lui a5,0x80004 +80004508: 00112e23 sw ra,28(sp) +8000450c: 00812c23 sw s0,24(sp) +80004510: 00912a23 sw s1,20(sp) +80004514: 01212823 sw s2,16(sp) +80004518: 01312623 sw s3,12(sp) +8000451c: 01412423 sw s4,8(sp) +80004520: 01512223 sw s5,4(sp) +80004524: 01612023 sw s6,0(sp) +80004528: 00452403 lw s0,4(a0) +8000452c: 4f478793 addi a5,a5,1268 # 800044f4 <__BSS_END__+0xfffed8b8> +80004530: 02f52e23 sw a5,60(a0) +80004534: 2ec50713 addi a4,a0,748 +80004538: 00300793 li a5,3 +8000453c: 2ee52423 sw a4,744(a0) +80004540: 2ef52223 sw a5,740(a0) +80004544: 2e052023 sw zero,736(a0) +80004548: 00400793 li a5,4 +8000454c: 00050913 mv s2,a0 +80004550: 00f42623 sw a5,12(s0) +80004554: 00800613 li a2,8 +80004558: 00000593 li a1,0 +8000455c: 06042223 sw zero,100(s0) +80004560: 00042023 sw zero,0(s0) +80004564: 00042223 sw zero,4(s0) +80004568: 00042423 sw zero,8(s0) +8000456c: 00042823 sw zero,16(s0) +80004570: 00042a23 sw zero,20(s0) +80004574: 00042c23 sw zero,24(s0) +80004578: 05c40513 addi a0,s0,92 +8000457c: 699030ef jal ra,80008414 +80004580: 80009b37 lui s6,0x80009 +80004584: 00892483 lw s1,8(s2) +80004588: 80009ab7 lui s5,0x80009 +8000458c: 8000aa37 lui s4,0x8000a +80004590: 8000a9b7 lui s3,0x8000a +80004594: 754b0b13 addi s6,s6,1876 # 80009754 <__BSS_END__+0xffff2b18> +80004598: 7b8a8a93 addi s5,s5,1976 # 800097b8 <__BSS_END__+0xffff2b7c> +8000459c: 840a0a13 addi s4,s4,-1984 # 80009840 <__BSS_END__+0xffff2c04> +800045a0: 8a898993 addi s3,s3,-1880 # 800098a8 <__BSS_END__+0xffff2c6c> +800045a4: 000107b7 lui a5,0x10 +800045a8: 03642023 sw s6,32(s0) +800045ac: 03542223 sw s5,36(s0) +800045b0: 03442423 sw s4,40(s0) +800045b4: 03342623 sw s3,44(s0) +800045b8: 00842e23 sw s0,28(s0) +800045bc: 00978793 addi a5,a5,9 # 10009 <_start-0x7ffefff7> +800045c0: 00f4a623 sw a5,12(s1) +800045c4: 00800613 li a2,8 +800045c8: 00000593 li a1,0 +800045cc: 0604a223 sw zero,100(s1) +800045d0: 0004a023 sw zero,0(s1) +800045d4: 0004a223 sw zero,4(s1) +800045d8: 0004a423 sw zero,8(s1) +800045dc: 0004a823 sw zero,16(s1) +800045e0: 0004aa23 sw zero,20(s1) +800045e4: 0004ac23 sw zero,24(s1) +800045e8: 05c48513 addi a0,s1,92 +800045ec: 629030ef jal ra,80008414 +800045f0: 00c92403 lw s0,12(s2) +800045f4: 000207b7 lui a5,0x20 +800045f8: 0364a023 sw s6,32(s1) +800045fc: 0354a223 sw s5,36(s1) +80004600: 0344a423 sw s4,40(s1) +80004604: 0334a623 sw s3,44(s1) +80004608: 0094ae23 sw s1,28(s1) +8000460c: 01278793 addi a5,a5,18 # 20012 <_start-0x7ffdffee> +80004610: 00f42623 sw a5,12(s0) +80004614: 06042223 sw zero,100(s0) +80004618: 00042023 sw zero,0(s0) +8000461c: 00042223 sw zero,4(s0) +80004620: 00042423 sw zero,8(s0) +80004624: 00042823 sw zero,16(s0) +80004628: 00042a23 sw zero,20(s0) +8000462c: 00042c23 sw zero,24(s0) +80004630: 05c40513 addi a0,s0,92 +80004634: 00800613 li a2,8 +80004638: 00000593 li a1,0 +8000463c: 5d9030ef jal ra,80008414 +80004640: 01c12083 lw ra,28(sp) +80004644: 03642023 sw s6,32(s0) +80004648: 03542223 sw s5,36(s0) +8000464c: 03442423 sw s4,40(s0) +80004650: 03342623 sw s3,44(s0) +80004654: 00842e23 sw s0,28(s0) +80004658: 01812403 lw s0,24(sp) +8000465c: 00100793 li a5,1 +80004660: 02f92c23 sw a5,56(s2) +80004664: 01412483 lw s1,20(sp) +80004668: 01012903 lw s2,16(sp) +8000466c: 00c12983 lw s3,12(sp) +80004670: 00812a03 lw s4,8(sp) +80004674: 00412a83 lw s5,4(sp) +80004678: 00012b03 lw s6,0(sp) +8000467c: 02010113 addi sp,sp,32 +80004680: 00008067 ret + +80004684 <__fp_unlock>: +80004684: 00000513 li a0,0 +80004688: 00008067 ret + +8000468c <__sfmoreglue>: +8000468c: ff010113 addi sp,sp,-16 +80004690: 00912223 sw s1,4(sp) +80004694: 06800613 li a2,104 +80004698: fff58493 addi s1,a1,-1 +8000469c: 02c484b3 mul s1,s1,a2 +800046a0: 01212023 sw s2,0(sp) +800046a4: 00058913 mv s2,a1 +800046a8: 00812423 sw s0,8(sp) +800046ac: 00112623 sw ra,12(sp) +800046b0: 07448593 addi a1,s1,116 +800046b4: 4f4030ef jal ra,80007ba8 <_malloc_r> +800046b8: 00050413 mv s0,a0 +800046bc: 02050063 beqz a0,800046dc <__sfmoreglue+0x50> +800046c0: 00c50513 addi a0,a0,12 +800046c4: 00042023 sw zero,0(s0) +800046c8: 01242223 sw s2,4(s0) +800046cc: 00a42423 sw a0,8(s0) +800046d0: 06848613 addi a2,s1,104 800046d4: 00000593 li a1,0 -800046d8: 0604a223 sw zero,100(s1) -800046dc: 0004a023 sw zero,0(s1) -800046e0: 0004a223 sw zero,4(s1) -800046e4: 0004a423 sw zero,8(s1) -800046e8: 0004a823 sw zero,16(s1) -800046ec: 0004aa23 sw zero,20(s1) -800046f0: 0004ac23 sw zero,24(s1) -800046f4: 05c48513 addi a0,s1,92 -800046f8: c41fc0ef jal ra,80001338 -800046fc: 00c92403 lw s0,12(s2) -80004700: 000207b7 lui a5,0x20 -80004704: 0364a023 sw s6,32(s1) -80004708: 0354a223 sw s5,36(s1) -8000470c: 0344a423 sw s4,40(s1) -80004710: 0334a623 sw s3,44(s1) -80004714: 0094ae23 sw s1,28(s1) -80004718: 01278793 addi a5,a5,18 # 20012 <_start-0x7ffdffee> -8000471c: 00f42623 sw a5,12(s0) -80004720: 06042223 sw zero,100(s0) -80004724: 00042023 sw zero,0(s0) -80004728: 00042223 sw zero,4(s0) -8000472c: 00042423 sw zero,8(s0) -80004730: 00042823 sw zero,16(s0) -80004734: 00042a23 sw zero,20(s0) -80004738: 00042c23 sw zero,24(s0) -8000473c: 05c40513 addi a0,s0,92 -80004740: 00800613 li a2,8 -80004744: 00000593 li a1,0 -80004748: bf1fc0ef jal ra,80001338 -8000474c: 01c12083 lw ra,28(sp) -80004750: 03642023 sw s6,32(s0) -80004754: 03542223 sw s5,36(s0) -80004758: 03442423 sw s4,40(s0) -8000475c: 03342623 sw s3,44(s0) -80004760: 00842e23 sw s0,28(s0) -80004764: 01812403 lw s0,24(sp) -80004768: 00100793 li a5,1 -8000476c: 02f92c23 sw a5,56(s2) -80004770: 01412483 lw s1,20(sp) -80004774: 01012903 lw s2,16(sp) -80004778: 00c12983 lw s3,12(sp) -8000477c: 00812a03 lw s4,8(sp) -80004780: 00412a83 lw s5,4(sp) -80004784: 00012b03 lw s6,0(sp) -80004788: 02010113 addi sp,sp,32 -8000478c: 00008067 ret +800046d8: 53d030ef jal ra,80008414 +800046dc: 00c12083 lw ra,12(sp) +800046e0: 00040513 mv a0,s0 +800046e4: 00812403 lw s0,8(sp) +800046e8: 00412483 lw s1,4(sp) +800046ec: 00012903 lw s2,0(sp) +800046f0: 01010113 addi sp,sp,16 +800046f4: 00008067 ret -80004790 <__fp_unlock>: -80004790: 00000513 li a0,0 -80004794: 00008067 ret +800046f8 <__sfp>: +800046f8: fe010113 addi sp,sp,-32 +800046fc: 01212823 sw s2,16(sp) +80004700: 3501a903 lw s2,848(gp) # 80016b58 <_global_impure_ptr> +80004704: 01312623 sw s3,12(sp) +80004708: 00112e23 sw ra,28(sp) +8000470c: 03892783 lw a5,56(s2) +80004710: 00812c23 sw s0,24(sp) +80004714: 00912a23 sw s1,20(sp) +80004718: 00050993 mv s3,a0 +8000471c: 0a078663 beqz a5,800047c8 <__sfp+0xd0> +80004720: 2e090913 addi s2,s2,736 +80004724: fff00493 li s1,-1 +80004728: 00492783 lw a5,4(s2) +8000472c: 00892403 lw s0,8(s2) +80004730: fff78793 addi a5,a5,-1 +80004734: 0007d863 bgez a5,80004744 <__sfp+0x4c> +80004738: 0800006f j 800047b8 <__sfp+0xc0> +8000473c: 06840413 addi s0,s0,104 +80004740: 06978c63 beq a5,s1,800047b8 <__sfp+0xc0> +80004744: 00c41703 lh a4,12(s0) +80004748: fff78793 addi a5,a5,-1 +8000474c: fe0718e3 bnez a4,8000473c <__sfp+0x44> +80004750: ffff07b7 lui a5,0xffff0 +80004754: 00178793 addi a5,a5,1 # ffff0001 <__BSS_END__+0x7ffd93c5> +80004758: 06042223 sw zero,100(s0) +8000475c: 00042023 sw zero,0(s0) +80004760: 00042223 sw zero,4(s0) +80004764: 00042423 sw zero,8(s0) +80004768: 00f42623 sw a5,12(s0) +8000476c: 00042823 sw zero,16(s0) +80004770: 00042a23 sw zero,20(s0) +80004774: 00042c23 sw zero,24(s0) +80004778: 00800613 li a2,8 +8000477c: 00000593 li a1,0 +80004780: 05c40513 addi a0,s0,92 +80004784: 491030ef jal ra,80008414 +80004788: 02042823 sw zero,48(s0) +8000478c: 02042a23 sw zero,52(s0) +80004790: 04042223 sw zero,68(s0) +80004794: 04042423 sw zero,72(s0) +80004798: 01c12083 lw ra,28(sp) +8000479c: 00040513 mv a0,s0 +800047a0: 01812403 lw s0,24(sp) +800047a4: 01412483 lw s1,20(sp) +800047a8: 01012903 lw s2,16(sp) +800047ac: 00c12983 lw s3,12(sp) +800047b0: 02010113 addi sp,sp,32 +800047b4: 00008067 ret +800047b8: 00092403 lw s0,0(s2) +800047bc: 00040c63 beqz s0,800047d4 <__sfp+0xdc> +800047c0: 00040913 mv s2,s0 +800047c4: f65ff06f j 80004728 <__sfp+0x30> +800047c8: 00090513 mv a0,s2 +800047cc: d35ff0ef jal ra,80004500 <__sinit.part.0> +800047d0: f51ff06f j 80004720 <__sfp+0x28> +800047d4: 00400593 li a1,4 +800047d8: 00098513 mv a0,s3 +800047dc: eb1ff0ef jal ra,8000468c <__sfmoreglue> +800047e0: 00a92023 sw a0,0(s2) +800047e4: 00050413 mv s0,a0 +800047e8: fc051ce3 bnez a0,800047c0 <__sfp+0xc8> +800047ec: 00c00793 li a5,12 +800047f0: 00f9a023 sw a5,0(s3) +800047f4: fa5ff06f j 80004798 <__sfp+0xa0> -80004798 <__sfmoreglue>: -80004798: ff010113 addi sp,sp,-16 -8000479c: 00912223 sw s1,4(sp) -800047a0: 06800613 li a2,104 -800047a4: fff58493 addi s1,a1,-1 -800047a8: 02c484b3 mul s1,s1,a2 -800047ac: 01212023 sw s2,0(sp) -800047b0: 00058913 mv s2,a1 -800047b4: 00812423 sw s0,8(sp) -800047b8: 00112623 sw ra,12(sp) -800047bc: 07448593 addi a1,s1,116 -800047c0: 530030ef jal ra,80007cf0 <_malloc_r> -800047c4: 00050413 mv s0,a0 -800047c8: 02050063 beqz a0,800047e8 <__sfmoreglue+0x50> -800047cc: 00c50513 addi a0,a0,12 -800047d0: 00042023 sw zero,0(s0) -800047d4: 01242223 sw s2,4(s0) -800047d8: 00a42423 sw a0,8(s0) -800047dc: 06848613 addi a2,s1,104 -800047e0: 00000593 li a1,0 -800047e4: b55fc0ef jal ra,80001338 -800047e8: 00c12083 lw ra,12(sp) -800047ec: 00040513 mv a0,s0 -800047f0: 00812403 lw s0,8(sp) -800047f4: 00412483 lw s1,4(sp) -800047f8: 00012903 lw s2,0(sp) -800047fc: 01010113 addi sp,sp,16 -80004800: 00008067 ret +800047f8 <_cleanup>: +800047f8: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> +800047fc: 8000e5b7 lui a1,0x8000e +80004800: ad858593 addi a1,a1,-1320 # 8000dad8 <__BSS_END__+0xffff6e9c> +80004804: 5740006f j 80004d78 <_fwalk_reent> -80004804 <__sfp>: -80004804: fe010113 addi sp,sp,-32 -80004808: 01212823 sw s2,16(sp) -8000480c: 3501a903 lw s2,848(gp) # 80016b58 <_global_impure_ptr> -80004810: 01312623 sw s3,12(sp) -80004814: 00112e23 sw ra,28(sp) -80004818: 03892783 lw a5,56(s2) -8000481c: 00812c23 sw s0,24(sp) -80004820: 00912a23 sw s1,20(sp) -80004824: 00050993 mv s3,a0 -80004828: 0a078663 beqz a5,800048d4 <__sfp+0xd0> -8000482c: 2e090913 addi s2,s2,736 -80004830: fff00493 li s1,-1 -80004834: 00492783 lw a5,4(s2) -80004838: 00892403 lw s0,8(s2) -8000483c: fff78793 addi a5,a5,-1 -80004840: 0007d863 bgez a5,80004850 <__sfp+0x4c> -80004844: 0800006f j 800048c4 <__sfp+0xc0> -80004848: 06840413 addi s0,s0,104 -8000484c: 06978c63 beq a5,s1,800048c4 <__sfp+0xc0> -80004850: 00c41703 lh a4,12(s0) -80004854: fff78793 addi a5,a5,-1 -80004858: fe0718e3 bnez a4,80004848 <__sfp+0x44> -8000485c: ffff07b7 lui a5,0xffff0 -80004860: 00178793 addi a5,a5,1 # ffff0001 <__BSS_END__+0x7ffd93d1> -80004864: 06042223 sw zero,100(s0) -80004868: 00042023 sw zero,0(s0) -8000486c: 00042223 sw zero,4(s0) -80004870: 00042423 sw zero,8(s0) -80004874: 00f42623 sw a5,12(s0) -80004878: 00042823 sw zero,16(s0) -8000487c: 00042a23 sw zero,20(s0) -80004880: 00042c23 sw zero,24(s0) -80004884: 00800613 li a2,8 -80004888: 00000593 li a1,0 -8000488c: 05c40513 addi a0,s0,92 -80004890: aa9fc0ef jal ra,80001338 -80004894: 02042823 sw zero,48(s0) -80004898: 02042a23 sw zero,52(s0) -8000489c: 04042223 sw zero,68(s0) -800048a0: 04042423 sw zero,72(s0) -800048a4: 01c12083 lw ra,28(sp) -800048a8: 00040513 mv a0,s0 -800048ac: 01812403 lw s0,24(sp) -800048b0: 01412483 lw s1,20(sp) -800048b4: 01012903 lw s2,16(sp) -800048b8: 00c12983 lw s3,12(sp) -800048bc: 02010113 addi sp,sp,32 -800048c0: 00008067 ret -800048c4: 00092403 lw s0,0(s2) -800048c8: 00040c63 beqz s0,800048e0 <__sfp+0xdc> -800048cc: 00040913 mv s2,s0 -800048d0: f65ff06f j 80004834 <__sfp+0x30> -800048d4: 00090513 mv a0,s2 -800048d8: d35ff0ef jal ra,8000460c <__sinit.part.0> -800048dc: f51ff06f j 8000482c <__sfp+0x28> -800048e0: 00400593 li a1,4 -800048e4: 00098513 mv a0,s3 -800048e8: eb1ff0ef jal ra,80004798 <__sfmoreglue> -800048ec: 00a92023 sw a0,0(s2) -800048f0: 00050413 mv s0,a0 -800048f4: fc051ce3 bnez a0,800048cc <__sfp+0xc8> -800048f8: 00c00793 li a5,12 -800048fc: 00f9a023 sw a5,0(s3) -80004900: fa5ff06f j 800048a4 <__sfp+0xa0> +80004808 <__sinit>: +80004808: 03852783 lw a5,56(a0) +8000480c: 00078463 beqz a5,80004814 <__sinit+0xc> +80004810: 00008067 ret +80004814: cedff06f j 80004500 <__sinit.part.0> -80004904 <_cleanup>: -80004904: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> -80004908: 8000e5b7 lui a1,0x8000e -8000490c: cd058593 addi a1,a1,-816 # 8000dcd0 <__BSS_END__+0xffff70a0> -80004910: 5180006f j 80004e28 <_fwalk_reent> +80004818 <__sfp_lock_acquire>: +80004818: 00008067 ret -80004914 <__sinit>: -80004914: 03852783 lw a5,56(a0) -80004918: 00078463 beqz a5,80004920 <__sinit+0xc> -8000491c: 00008067 ret -80004920: cedff06f j 8000460c <__sinit.part.0> +8000481c <__sfp_lock_release>: +8000481c: 00008067 ret -80004924 <__sfp_lock_acquire>: -80004924: 00008067 ret +80004820 <__sinit_lock_acquire>: +80004820: 00008067 ret -80004928 <__sfp_lock_release>: -80004928: 00008067 ret +80004824 <__sinit_lock_release>: +80004824: 00008067 ret -8000492c <__sinit_lock_acquire>: -8000492c: 00008067 ret +80004828 <__fp_lock_all>: +80004828: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +8000482c: 800045b7 lui a1,0x80004 +80004830: 4ec58593 addi a1,a1,1260 # 800044ec <__BSS_END__+0xfffed8b0> +80004834: 4a00006f j 80004cd4 <_fwalk> -80004930 <__sinit_lock_release>: -80004930: 00008067 ret +80004838 <__fp_unlock_all>: +80004838: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +8000483c: 800045b7 lui a1,0x80004 +80004840: 68458593 addi a1,a1,1668 # 80004684 <__BSS_END__+0xfffeda48> +80004844: 4900006f j 80004cd4 <_fwalk> -80004934 <__fp_lock_all>: -80004934: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -80004938: 800045b7 lui a1,0x80004 -8000493c: 5f858593 addi a1,a1,1528 # 800045f8 <__BSS_END__+0xfffed9c8> -80004940: 4440006f j 80004d84 <_fwalk> +80004848 <__libc_fini_array>: +80004848: ff010113 addi sp,sp,-16 +8000484c: 00812423 sw s0,8(sp) +80004850: 800167b7 lui a5,0x80016 +80004854: 80016437 lui s0,0x80016 +80004858: 00440413 addi s0,s0,4 # 80016004 <__BSS_END__+0xfffff3c8> +8000485c: 00478793 addi a5,a5,4 # 80016004 <__BSS_END__+0xfffff3c8> +80004860: 408787b3 sub a5,a5,s0 +80004864: 00912223 sw s1,4(sp) +80004868: 00112623 sw ra,12(sp) +8000486c: 4027d493 srai s1,a5,0x2 +80004870: 02048063 beqz s1,80004890 <__libc_fini_array+0x48> +80004874: ffc78793 addi a5,a5,-4 +80004878: 00878433 add s0,a5,s0 +8000487c: 00042783 lw a5,0(s0) +80004880: fff48493 addi s1,s1,-1 +80004884: ffc40413 addi s0,s0,-4 +80004888: 000780e7 jalr a5 +8000488c: fe0498e3 bnez s1,8000487c <__libc_fini_array+0x34> +80004890: 00c12083 lw ra,12(sp) +80004894: 00812403 lw s0,8(sp) +80004898: 00412483 lw s1,4(sp) +8000489c: 01010113 addi sp,sp,16 +800048a0: 00008067 ret -80004944 <__fp_unlock_all>: -80004944: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -80004948: 800045b7 lui a1,0x80004 -8000494c: 79058593 addi a1,a1,1936 # 80004790 <__BSS_END__+0xfffedb60> -80004950: 4340006f j 80004d84 <_fwalk> +800048a4 <_malloc_trim_r>: +800048a4: fe010113 addi sp,sp,-32 +800048a8: 01312623 sw s3,12(sp) +800048ac: 00812c23 sw s0,24(sp) +800048b0: 00912a23 sw s1,20(sp) +800048b4: 01212823 sw s2,16(sp) +800048b8: 01412423 sw s4,8(sp) +800048bc: 00112e23 sw ra,28(sp) +800048c0: 00058a13 mv s4,a1 +800048c4: 00050913 mv s2,a0 +800048c8: dc018993 addi s3,gp,-576 # 800165c8 <__malloc_av_> +800048cc: 425030ef jal ra,800084f0 <__malloc_lock> +800048d0: 0089a703 lw a4,8(s3) +800048d4: 000017b7 lui a5,0x1 +800048d8: fef78413 addi s0,a5,-17 # fef <_start-0x7ffff011> +800048dc: 00472483 lw s1,4(a4) +800048e0: 41440433 sub s0,s0,s4 +800048e4: ffc4f493 andi s1,s1,-4 +800048e8: 00940433 add s0,s0,s1 +800048ec: 00c45413 srli s0,s0,0xc +800048f0: fff40413 addi s0,s0,-1 +800048f4: 00c41413 slli s0,s0,0xc +800048f8: 00f44e63 blt s0,a5,80004914 <_malloc_trim_r+0x70> +800048fc: 00000593 li a1,0 +80004900: 00090513 mv a0,s2 +80004904: 511040ef jal ra,80009614 <_sbrk_r> +80004908: 0089a783 lw a5,8(s3) +8000490c: 009787b3 add a5,a5,s1 +80004910: 02f50863 beq a0,a5,80004940 <_malloc_trim_r+0x9c> +80004914: 00090513 mv a0,s2 +80004918: 3dd030ef jal ra,800084f4 <__malloc_unlock> +8000491c: 01c12083 lw ra,28(sp) +80004920: 01812403 lw s0,24(sp) +80004924: 01412483 lw s1,20(sp) +80004928: 01012903 lw s2,16(sp) +8000492c: 00c12983 lw s3,12(sp) +80004930: 00812a03 lw s4,8(sp) +80004934: 00000513 li a0,0 +80004938: 02010113 addi sp,sp,32 +8000493c: 00008067 ret +80004940: 408005b3 neg a1,s0 +80004944: 00090513 mv a0,s2 +80004948: 4cd040ef jal ra,80009614 <_sbrk_r> +8000494c: fff00793 li a5,-1 +80004950: 04f50863 beq a0,a5,800049a0 <_malloc_trim_r+0xfc> +80004954: 3c018793 addi a5,gp,960 # 80016bc8 <__malloc_current_mallinfo> +80004958: 0007a703 lw a4,0(a5) +8000495c: 0089a683 lw a3,8(s3) +80004960: 408484b3 sub s1,s1,s0 +80004964: 0014e493 ori s1,s1,1 +80004968: 40870433 sub s0,a4,s0 +8000496c: 00090513 mv a0,s2 +80004970: 0096a223 sw s1,4(a3) +80004974: 0087a023 sw s0,0(a5) +80004978: 37d030ef jal ra,800084f4 <__malloc_unlock> +8000497c: 01c12083 lw ra,28(sp) +80004980: 01812403 lw s0,24(sp) +80004984: 01412483 lw s1,20(sp) +80004988: 01012903 lw s2,16(sp) +8000498c: 00c12983 lw s3,12(sp) +80004990: 00812a03 lw s4,8(sp) +80004994: 00100513 li a0,1 +80004998: 02010113 addi sp,sp,32 +8000499c: 00008067 ret +800049a0: 00000593 li a1,0 +800049a4: 00090513 mv a0,s2 +800049a8: 46d040ef jal ra,80009614 <_sbrk_r> +800049ac: 0089a703 lw a4,8(s3) +800049b0: 00f00693 li a3,15 +800049b4: 40e507b3 sub a5,a0,a4 +800049b8: f4f6dee3 bge a3,a5,80004914 <_malloc_trim_r+0x70> +800049bc: 3641a683 lw a3,868(gp) # 80016b6c <__malloc_sbrk_base> +800049c0: 0017e793 ori a5,a5,1 +800049c4: 00f72223 sw a5,4(a4) +800049c8: 40d50533 sub a0,a0,a3 +800049cc: 3ca1a023 sw a0,960(gp) # 80016bc8 <__malloc_current_mallinfo> +800049d0: f45ff06f j 80004914 <_malloc_trim_r+0x70> -80004954 <_malloc_trim_r>: -80004954: fe010113 addi sp,sp,-32 -80004958: 01312623 sw s3,12(sp) -8000495c: 00812c23 sw s0,24(sp) -80004960: 00912a23 sw s1,20(sp) -80004964: 01212823 sw s2,16(sp) -80004968: 01412423 sw s4,8(sp) -8000496c: 00112e23 sw ra,28(sp) -80004970: 00058a13 mv s4,a1 -80004974: 00050913 mv s2,a0 -80004978: f2c18993 addi s3,gp,-212 # 80016734 <__malloc_av_> -8000497c: 451030ef jal ra,800085cc <__malloc_lock> -80004980: 0089a703 lw a4,8(s3) -80004984: 000017b7 lui a5,0x1 -80004988: fef78413 addi s0,a5,-17 # fef <_start-0x7ffff011> -8000498c: 00472483 lw s1,4(a4) -80004990: 41440433 sub s0,s0,s4 -80004994: ffc4f493 andi s1,s1,-4 -80004998: 00940433 add s0,s0,s1 -8000499c: 00c45413 srli s0,s0,0xc -800049a0: fff40413 addi s0,s0,-1 -800049a4: 00c41413 slli s0,s0,0xc -800049a8: 00f44e63 blt s0,a5,800049c4 <_malloc_trim_r+0x70> -800049ac: 00000593 li a1,0 -800049b0: 00090513 mv a0,s2 -800049b4: 495040ef jal ra,80009648 <_sbrk_r> -800049b8: 0089a783 lw a5,8(s3) -800049bc: 009787b3 add a5,a5,s1 -800049c0: 02f50863 beq a0,a5,800049f0 <_malloc_trim_r+0x9c> -800049c4: 00090513 mv a0,s2 -800049c8: 409030ef jal ra,800085d0 <__malloc_unlock> -800049cc: 01c12083 lw ra,28(sp) -800049d0: 01812403 lw s0,24(sp) -800049d4: 01412483 lw s1,20(sp) -800049d8: 01012903 lw s2,16(sp) -800049dc: 00c12983 lw s3,12(sp) -800049e0: 00812a03 lw s4,8(sp) -800049e4: 00000513 li a0,0 -800049e8: 02010113 addi sp,sp,32 -800049ec: 00008067 ret -800049f0: 408005b3 neg a1,s0 -800049f4: 00090513 mv a0,s2 -800049f8: 451040ef jal ra,80009648 <_sbrk_r> -800049fc: fff00793 li a5,-1 -80004a00: 04f50863 beq a0,a5,80004a50 <_malloc_trim_r+0xfc> -80004a04: 3c018793 addi a5,gp,960 # 80016bc8 <__malloc_current_mallinfo> -80004a08: 0007a703 lw a4,0(a5) -80004a0c: 0089a683 lw a3,8(s3) -80004a10: 408484b3 sub s1,s1,s0 -80004a14: 0014e493 ori s1,s1,1 -80004a18: 40870433 sub s0,a4,s0 -80004a1c: 00090513 mv a0,s2 -80004a20: 0096a223 sw s1,4(a3) -80004a24: 0087a023 sw s0,0(a5) -80004a28: 3a9030ef jal ra,800085d0 <__malloc_unlock> -80004a2c: 01c12083 lw ra,28(sp) -80004a30: 01812403 lw s0,24(sp) -80004a34: 01412483 lw s1,20(sp) -80004a38: 01012903 lw s2,16(sp) -80004a3c: 00c12983 lw s3,12(sp) -80004a40: 00812a03 lw s4,8(sp) -80004a44: 00100513 li a0,1 -80004a48: 02010113 addi sp,sp,32 -80004a4c: 00008067 ret -80004a50: 00000593 li a1,0 -80004a54: 00090513 mv a0,s2 -80004a58: 3f1040ef jal ra,80009648 <_sbrk_r> -80004a5c: 0089a703 lw a4,8(s3) -80004a60: 00f00693 li a3,15 -80004a64: 40e507b3 sub a5,a0,a4 -80004a68: f4f6dee3 bge a3,a5,800049c4 <_malloc_trim_r+0x70> -80004a6c: 3641a683 lw a3,868(gp) # 80016b6c <__malloc_sbrk_base> -80004a70: 0017e793 ori a5,a5,1 -80004a74: 00f72223 sw a5,4(a4) -80004a78: 40d50533 sub a0,a0,a3 -80004a7c: 3ca1a023 sw a0,960(gp) # 80016bc8 <__malloc_current_mallinfo> -80004a80: f45ff06f j 800049c4 <_malloc_trim_r+0x70> +800049d4 <_free_r>: +800049d4: 12058463 beqz a1,80004afc <_free_r+0x128> +800049d8: ff010113 addi sp,sp,-16 +800049dc: 00812423 sw s0,8(sp) +800049e0: 00912223 sw s1,4(sp) +800049e4: 00058413 mv s0,a1 +800049e8: 00050493 mv s1,a0 +800049ec: 00112623 sw ra,12(sp) +800049f0: 301030ef jal ra,800084f0 <__malloc_lock> +800049f4: ffc42803 lw a6,-4(s0) +800049f8: ff840713 addi a4,s0,-8 +800049fc: ffe87793 andi a5,a6,-2 +80004a00: 00f70633 add a2,a4,a5 +80004a04: dc018593 addi a1,gp,-576 # 800165c8 <__malloc_av_> +80004a08: 00462683 lw a3,4(a2) +80004a0c: 0085a503 lw a0,8(a1) +80004a10: ffc6f693 andi a3,a3,-4 +80004a14: 1ac50663 beq a0,a2,80004bc0 <_free_r+0x1ec> +80004a18: 00d62223 sw a3,4(a2) +80004a1c: 00187813 andi a6,a6,1 +80004a20: 00d60533 add a0,a2,a3 +80004a24: 08081e63 bnez a6,80004ac0 <_free_r+0xec> +80004a28: ff842303 lw t1,-8(s0) +80004a2c: 00452803 lw a6,4(a0) +80004a30: 40670733 sub a4,a4,t1 +80004a34: 00872883 lw a7,8(a4) +80004a38: dc818513 addi a0,gp,-568 # 800165d0 <__malloc_av_+0x8> +80004a3c: 006787b3 add a5,a5,t1 +80004a40: 00187813 andi a6,a6,1 +80004a44: 12a88e63 beq a7,a0,80004b80 <_free_r+0x1ac> +80004a48: 00c72303 lw t1,12(a4) +80004a4c: 0068a623 sw t1,12(a7) +80004a50: 01132423 sw a7,8(t1) +80004a54: 1c080e63 beqz a6,80004c30 <_free_r+0x25c> +80004a58: 0017e693 ori a3,a5,1 +80004a5c: 00d72223 sw a3,4(a4) +80004a60: 00f62023 sw a5,0(a2) +80004a64: 1ff00693 li a3,511 +80004a68: 0af6e663 bltu a3,a5,80004b14 <_free_r+0x140> +80004a6c: ff87f693 andi a3,a5,-8 +80004a70: 00868693 addi a3,a3,8 +80004a74: 0045a503 lw a0,4(a1) +80004a78: 00d586b3 add a3,a1,a3 +80004a7c: 0006a603 lw a2,0(a3) +80004a80: 0057d813 srli a6,a5,0x5 +80004a84: 00100793 li a5,1 +80004a88: 010797b3 sll a5,a5,a6 +80004a8c: 00a7e7b3 or a5,a5,a0 +80004a90: ff868513 addi a0,a3,-8 +80004a94: 00a72623 sw a0,12(a4) +80004a98: 00c72423 sw a2,8(a4) +80004a9c: 00f5a223 sw a5,4(a1) +80004aa0: 00e6a023 sw a4,0(a3) +80004aa4: 00e62623 sw a4,12(a2) +80004aa8: 00812403 lw s0,8(sp) +80004aac: 00c12083 lw ra,12(sp) +80004ab0: 00048513 mv a0,s1 +80004ab4: 00412483 lw s1,4(sp) +80004ab8: 01010113 addi sp,sp,16 +80004abc: 2390306f j 800084f4 <__malloc_unlock> +80004ac0: 00452503 lw a0,4(a0) +80004ac4: 00157513 andi a0,a0,1 +80004ac8: 02051c63 bnez a0,80004b00 <_free_r+0x12c> +80004acc: 00d787b3 add a5,a5,a3 +80004ad0: dc818513 addi a0,gp,-568 # 800165d0 <__malloc_av_+0x8> +80004ad4: 00862683 lw a3,8(a2) +80004ad8: 0017e893 ori a7,a5,1 +80004adc: 00f70833 add a6,a4,a5 +80004ae0: 16a68463 beq a3,a0,80004c48 <_free_r+0x274> +80004ae4: 00c62603 lw a2,12(a2) +80004ae8: 00c6a623 sw a2,12(a3) +80004aec: 00d62423 sw a3,8(a2) +80004af0: 01172223 sw a7,4(a4) +80004af4: 00f82023 sw a5,0(a6) +80004af8: f6dff06f j 80004a64 <_free_r+0x90> +80004afc: 00008067 ret +80004b00: 0017e693 ori a3,a5,1 +80004b04: fed42e23 sw a3,-4(s0) +80004b08: 00f62023 sw a5,0(a2) +80004b0c: 1ff00693 li a3,511 +80004b10: f4f6fee3 bgeu a3,a5,80004a6c <_free_r+0x98> +80004b14: 0097d693 srli a3,a5,0x9 +80004b18: 00400613 li a2,4 +80004b1c: 0ed66863 bltu a2,a3,80004c0c <_free_r+0x238> +80004b20: 0067d693 srli a3,a5,0x6 +80004b24: 03968813 addi a6,a3,57 +80004b28: 03868613 addi a2,a3,56 +80004b2c: 00381813 slli a6,a6,0x3 +80004b30: 01058833 add a6,a1,a6 +80004b34: 00082683 lw a3,0(a6) +80004b38: ff880813 addi a6,a6,-8 +80004b3c: 12d80463 beq a6,a3,80004c64 <_free_r+0x290> +80004b40: 0046a603 lw a2,4(a3) +80004b44: ffc67613 andi a2,a2,-4 +80004b48: 00c7f663 bgeu a5,a2,80004b54 <_free_r+0x180> +80004b4c: 0086a683 lw a3,8(a3) +80004b50: fed818e3 bne a6,a3,80004b40 <_free_r+0x16c> +80004b54: 00c6a803 lw a6,12(a3) +80004b58: 01072623 sw a6,12(a4) +80004b5c: 00d72423 sw a3,8(a4) +80004b60: 00812403 lw s0,8(sp) +80004b64: 00c12083 lw ra,12(sp) +80004b68: 00e82423 sw a4,8(a6) +80004b6c: 00048513 mv a0,s1 +80004b70: 00412483 lw s1,4(sp) +80004b74: 00e6a623 sw a4,12(a3) +80004b78: 01010113 addi sp,sp,16 +80004b7c: 1790306f j 800084f4 <__malloc_unlock> +80004b80: 14081263 bnez a6,80004cc4 <_free_r+0x2f0> +80004b84: 00c62583 lw a1,12(a2) +80004b88: 00862603 lw a2,8(a2) +80004b8c: 00f687b3 add a5,a3,a5 +80004b90: 00812403 lw s0,8(sp) +80004b94: 00b62623 sw a1,12(a2) +80004b98: 00c5a423 sw a2,8(a1) +80004b9c: 0017e693 ori a3,a5,1 +80004ba0: 00c12083 lw ra,12(sp) +80004ba4: 00d72223 sw a3,4(a4) +80004ba8: 00048513 mv a0,s1 +80004bac: 00f70733 add a4,a4,a5 +80004bb0: 00412483 lw s1,4(sp) +80004bb4: 00f72023 sw a5,0(a4) +80004bb8: 01010113 addi sp,sp,16 +80004bbc: 1390306f j 800084f4 <__malloc_unlock> +80004bc0: 00187813 andi a6,a6,1 +80004bc4: 00d787b3 add a5,a5,a3 +80004bc8: 02081063 bnez a6,80004be8 <_free_r+0x214> +80004bcc: ff842503 lw a0,-8(s0) +80004bd0: 40a70733 sub a4,a4,a0 +80004bd4: 00c72683 lw a3,12(a4) +80004bd8: 00872603 lw a2,8(a4) +80004bdc: 00a787b3 add a5,a5,a0 +80004be0: 00d62623 sw a3,12(a2) +80004be4: 00c6a423 sw a2,8(a3) +80004be8: 0017e613 ori a2,a5,1 +80004bec: 3681a683 lw a3,872(gp) # 80016b70 <__malloc_trim_threshold> +80004bf0: 00c72223 sw a2,4(a4) +80004bf4: 00e5a423 sw a4,8(a1) +80004bf8: ead7e8e3 bltu a5,a3,80004aa8 <_free_r+0xd4> +80004bfc: 3741a583 lw a1,884(gp) # 80016b7c <__malloc_top_pad> +80004c00: 00048513 mv a0,s1 +80004c04: ca1ff0ef jal ra,800048a4 <_malloc_trim_r> +80004c08: ea1ff06f j 80004aa8 <_free_r+0xd4> +80004c0c: 01400613 li a2,20 +80004c10: 02d67463 bgeu a2,a3,80004c38 <_free_r+0x264> +80004c14: 05400613 li a2,84 +80004c18: 06d66463 bltu a2,a3,80004c80 <_free_r+0x2ac> +80004c1c: 00c7d693 srli a3,a5,0xc +80004c20: 06f68813 addi a6,a3,111 +80004c24: 06e68613 addi a2,a3,110 +80004c28: 00381813 slli a6,a6,0x3 +80004c2c: f05ff06f j 80004b30 <_free_r+0x15c> +80004c30: 00d787b3 add a5,a5,a3 +80004c34: ea1ff06f j 80004ad4 <_free_r+0x100> +80004c38: 05c68813 addi a6,a3,92 +80004c3c: 05b68613 addi a2,a3,91 +80004c40: 00381813 slli a6,a6,0x3 +80004c44: eedff06f j 80004b30 <_free_r+0x15c> +80004c48: 00e5aa23 sw a4,20(a1) +80004c4c: 00e5a823 sw a4,16(a1) +80004c50: 00a72623 sw a0,12(a4) +80004c54: 00a72423 sw a0,8(a4) +80004c58: 01172223 sw a7,4(a4) +80004c5c: 00f82023 sw a5,0(a6) +80004c60: e49ff06f j 80004aa8 <_free_r+0xd4> +80004c64: 0045a503 lw a0,4(a1) +80004c68: 40265613 srai a2,a2,0x2 +80004c6c: 00100793 li a5,1 +80004c70: 00c79633 sll a2,a5,a2 +80004c74: 00a66633 or a2,a2,a0 +80004c78: 00c5a223 sw a2,4(a1) +80004c7c: eddff06f j 80004b58 <_free_r+0x184> +80004c80: 15400613 li a2,340 +80004c84: 00d66c63 bltu a2,a3,80004c9c <_free_r+0x2c8> +80004c88: 00f7d693 srli a3,a5,0xf +80004c8c: 07868813 addi a6,a3,120 +80004c90: 07768613 addi a2,a3,119 +80004c94: 00381813 slli a6,a6,0x3 +80004c98: e99ff06f j 80004b30 <_free_r+0x15c> +80004c9c: 55400613 li a2,1364 +80004ca0: 00d66c63 bltu a2,a3,80004cb8 <_free_r+0x2e4> +80004ca4: 0127d693 srli a3,a5,0x12 +80004ca8: 07d68813 addi a6,a3,125 +80004cac: 07c68613 addi a2,a3,124 +80004cb0: 00381813 slli a6,a6,0x3 +80004cb4: e7dff06f j 80004b30 <_free_r+0x15c> +80004cb8: 3f800813 li a6,1016 +80004cbc: 07e00613 li a2,126 +80004cc0: e71ff06f j 80004b30 <_free_r+0x15c> +80004cc4: 0017e693 ori a3,a5,1 +80004cc8: 00d72223 sw a3,4(a4) +80004ccc: 00f62023 sw a5,0(a2) +80004cd0: dd9ff06f j 80004aa8 <_free_r+0xd4> -80004a84 <_free_r>: -80004a84: 12058463 beqz a1,80004bac <_free_r+0x128> -80004a88: ff010113 addi sp,sp,-16 -80004a8c: 00812423 sw s0,8(sp) -80004a90: 00912223 sw s1,4(sp) -80004a94: 00058413 mv s0,a1 -80004a98: 00050493 mv s1,a0 -80004a9c: 00112623 sw ra,12(sp) -80004aa0: 32d030ef jal ra,800085cc <__malloc_lock> -80004aa4: ffc42803 lw a6,-4(s0) -80004aa8: ff840713 addi a4,s0,-8 -80004aac: ffe87793 andi a5,a6,-2 -80004ab0: 00f70633 add a2,a4,a5 -80004ab4: f2c18593 addi a1,gp,-212 # 80016734 <__malloc_av_> -80004ab8: 00462683 lw a3,4(a2) -80004abc: 0085a503 lw a0,8(a1) -80004ac0: ffc6f693 andi a3,a3,-4 -80004ac4: 1ac50663 beq a0,a2,80004c70 <_free_r+0x1ec> -80004ac8: 00d62223 sw a3,4(a2) -80004acc: 00187813 andi a6,a6,1 -80004ad0: 00d60533 add a0,a2,a3 -80004ad4: 08081e63 bnez a6,80004b70 <_free_r+0xec> -80004ad8: ff842303 lw t1,-8(s0) -80004adc: 00452803 lw a6,4(a0) -80004ae0: 40670733 sub a4,a4,t1 -80004ae4: 00872883 lw a7,8(a4) -80004ae8: f3418513 addi a0,gp,-204 # 8001673c <__malloc_av_+0x8> -80004aec: 006787b3 add a5,a5,t1 -80004af0: 00187813 andi a6,a6,1 -80004af4: 12a88e63 beq a7,a0,80004c30 <_free_r+0x1ac> -80004af8: 00c72303 lw t1,12(a4) -80004afc: 0068a623 sw t1,12(a7) -80004b00: 01132423 sw a7,8(t1) -80004b04: 1c080e63 beqz a6,80004ce0 <_free_r+0x25c> -80004b08: 0017e693 ori a3,a5,1 -80004b0c: 00d72223 sw a3,4(a4) -80004b10: 00f62023 sw a5,0(a2) -80004b14: 1ff00693 li a3,511 -80004b18: 0af6e663 bltu a3,a5,80004bc4 <_free_r+0x140> -80004b1c: ff87f693 andi a3,a5,-8 -80004b20: 00868693 addi a3,a3,8 -80004b24: 0045a503 lw a0,4(a1) -80004b28: 00d586b3 add a3,a1,a3 -80004b2c: 0006a603 lw a2,0(a3) -80004b30: 0057d813 srli a6,a5,0x5 -80004b34: 00100793 li a5,1 -80004b38: 010797b3 sll a5,a5,a6 -80004b3c: 00a7e7b3 or a5,a5,a0 -80004b40: ff868513 addi a0,a3,-8 -80004b44: 00a72623 sw a0,12(a4) -80004b48: 00c72423 sw a2,8(a4) -80004b4c: 00f5a223 sw a5,4(a1) -80004b50: 00e6a023 sw a4,0(a3) -80004b54: 00e62623 sw a4,12(a2) -80004b58: 00812403 lw s0,8(sp) -80004b5c: 00c12083 lw ra,12(sp) -80004b60: 00048513 mv a0,s1 -80004b64: 00412483 lw s1,4(sp) -80004b68: 01010113 addi sp,sp,16 -80004b6c: 2650306f j 800085d0 <__malloc_unlock> -80004b70: 00452503 lw a0,4(a0) -80004b74: 00157513 andi a0,a0,1 -80004b78: 02051c63 bnez a0,80004bb0 <_free_r+0x12c> -80004b7c: 00d787b3 add a5,a5,a3 -80004b80: f3418513 addi a0,gp,-204 # 8001673c <__malloc_av_+0x8> -80004b84: 00862683 lw a3,8(a2) -80004b88: 0017e893 ori a7,a5,1 -80004b8c: 00f70833 add a6,a4,a5 -80004b90: 16a68463 beq a3,a0,80004cf8 <_free_r+0x274> -80004b94: 00c62603 lw a2,12(a2) -80004b98: 00c6a623 sw a2,12(a3) -80004b9c: 00d62423 sw a3,8(a2) -80004ba0: 01172223 sw a7,4(a4) -80004ba4: 00f82023 sw a5,0(a6) -80004ba8: f6dff06f j 80004b14 <_free_r+0x90> -80004bac: 00008067 ret -80004bb0: 0017e693 ori a3,a5,1 -80004bb4: fed42e23 sw a3,-4(s0) -80004bb8: 00f62023 sw a5,0(a2) -80004bbc: 1ff00693 li a3,511 -80004bc0: f4f6fee3 bgeu a3,a5,80004b1c <_free_r+0x98> -80004bc4: 0097d693 srli a3,a5,0x9 -80004bc8: 00400613 li a2,4 -80004bcc: 0ed66863 bltu a2,a3,80004cbc <_free_r+0x238> -80004bd0: 0067d693 srli a3,a5,0x6 -80004bd4: 03968813 addi a6,a3,57 -80004bd8: 03868613 addi a2,a3,56 -80004bdc: 00381813 slli a6,a6,0x3 -80004be0: 01058833 add a6,a1,a6 -80004be4: 00082683 lw a3,0(a6) -80004be8: ff880813 addi a6,a6,-8 -80004bec: 12d80463 beq a6,a3,80004d14 <_free_r+0x290> -80004bf0: 0046a603 lw a2,4(a3) -80004bf4: ffc67613 andi a2,a2,-4 -80004bf8: 00c7f663 bgeu a5,a2,80004c04 <_free_r+0x180> -80004bfc: 0086a683 lw a3,8(a3) -80004c00: fed818e3 bne a6,a3,80004bf0 <_free_r+0x16c> -80004c04: 00c6a803 lw a6,12(a3) -80004c08: 01072623 sw a6,12(a4) -80004c0c: 00d72423 sw a3,8(a4) -80004c10: 00812403 lw s0,8(sp) -80004c14: 00c12083 lw ra,12(sp) -80004c18: 00e82423 sw a4,8(a6) -80004c1c: 00048513 mv a0,s1 -80004c20: 00412483 lw s1,4(sp) -80004c24: 00e6a623 sw a4,12(a3) -80004c28: 01010113 addi sp,sp,16 -80004c2c: 1a50306f j 800085d0 <__malloc_unlock> -80004c30: 14081263 bnez a6,80004d74 <_free_r+0x2f0> -80004c34: 00c62583 lw a1,12(a2) -80004c38: 00862603 lw a2,8(a2) -80004c3c: 00f687b3 add a5,a3,a5 -80004c40: 00812403 lw s0,8(sp) -80004c44: 00b62623 sw a1,12(a2) -80004c48: 00c5a423 sw a2,8(a1) -80004c4c: 0017e693 ori a3,a5,1 -80004c50: 00c12083 lw ra,12(sp) -80004c54: 00d72223 sw a3,4(a4) -80004c58: 00048513 mv a0,s1 -80004c5c: 00f70733 add a4,a4,a5 -80004c60: 00412483 lw s1,4(sp) -80004c64: 00f72023 sw a5,0(a4) -80004c68: 01010113 addi sp,sp,16 -80004c6c: 1650306f j 800085d0 <__malloc_unlock> -80004c70: 00187813 andi a6,a6,1 -80004c74: 00d787b3 add a5,a5,a3 -80004c78: 02081063 bnez a6,80004c98 <_free_r+0x214> -80004c7c: ff842503 lw a0,-8(s0) -80004c80: 40a70733 sub a4,a4,a0 -80004c84: 00c72683 lw a3,12(a4) -80004c88: 00872603 lw a2,8(a4) -80004c8c: 00a787b3 add a5,a5,a0 -80004c90: 00d62623 sw a3,12(a2) -80004c94: 00c6a423 sw a2,8(a3) -80004c98: 0017e613 ori a2,a5,1 -80004c9c: 3681a683 lw a3,872(gp) # 80016b70 <__malloc_trim_threshold> -80004ca0: 00c72223 sw a2,4(a4) -80004ca4: 00e5a423 sw a4,8(a1) -80004ca8: ead7e8e3 bltu a5,a3,80004b58 <_free_r+0xd4> -80004cac: 3781a583 lw a1,888(gp) # 80016b80 <__malloc_top_pad> -80004cb0: 00048513 mv a0,s1 -80004cb4: ca1ff0ef jal ra,80004954 <_malloc_trim_r> -80004cb8: ea1ff06f j 80004b58 <_free_r+0xd4> -80004cbc: 01400613 li a2,20 -80004cc0: 02d67463 bgeu a2,a3,80004ce8 <_free_r+0x264> -80004cc4: 05400613 li a2,84 -80004cc8: 06d66463 bltu a2,a3,80004d30 <_free_r+0x2ac> -80004ccc: 00c7d693 srli a3,a5,0xc -80004cd0: 06f68813 addi a6,a3,111 -80004cd4: 06e68613 addi a2,a3,110 -80004cd8: 00381813 slli a6,a6,0x3 -80004cdc: f05ff06f j 80004be0 <_free_r+0x15c> -80004ce0: 00d787b3 add a5,a5,a3 -80004ce4: ea1ff06f j 80004b84 <_free_r+0x100> -80004ce8: 05c68813 addi a6,a3,92 -80004cec: 05b68613 addi a2,a3,91 -80004cf0: 00381813 slli a6,a6,0x3 -80004cf4: eedff06f j 80004be0 <_free_r+0x15c> -80004cf8: 00e5aa23 sw a4,20(a1) -80004cfc: 00e5a823 sw a4,16(a1) -80004d00: 00a72623 sw a0,12(a4) -80004d04: 00a72423 sw a0,8(a4) -80004d08: 01172223 sw a7,4(a4) -80004d0c: 00f82023 sw a5,0(a6) -80004d10: e49ff06f j 80004b58 <_free_r+0xd4> -80004d14: 0045a503 lw a0,4(a1) -80004d18: 40265613 srai a2,a2,0x2 -80004d1c: 00100793 li a5,1 -80004d20: 00c79633 sll a2,a5,a2 -80004d24: 00a66633 or a2,a2,a0 -80004d28: 00c5a223 sw a2,4(a1) -80004d2c: eddff06f j 80004c08 <_free_r+0x184> -80004d30: 15400613 li a2,340 -80004d34: 00d66c63 bltu a2,a3,80004d4c <_free_r+0x2c8> -80004d38: 00f7d693 srli a3,a5,0xf -80004d3c: 07868813 addi a6,a3,120 -80004d40: 07768613 addi a2,a3,119 -80004d44: 00381813 slli a6,a6,0x3 -80004d48: e99ff06f j 80004be0 <_free_r+0x15c> -80004d4c: 55400613 li a2,1364 -80004d50: 00d66c63 bltu a2,a3,80004d68 <_free_r+0x2e4> -80004d54: 0127d693 srli a3,a5,0x12 -80004d58: 07d68813 addi a6,a3,125 -80004d5c: 07c68613 addi a2,a3,124 -80004d60: 00381813 slli a6,a6,0x3 -80004d64: e7dff06f j 80004be0 <_free_r+0x15c> -80004d68: 3f800813 li a6,1016 -80004d6c: 07e00613 li a2,126 -80004d70: e71ff06f j 80004be0 <_free_r+0x15c> -80004d74: 0017e693 ori a3,a5,1 -80004d78: 00d72223 sw a3,4(a4) -80004d7c: 00f62023 sw a5,0(a2) -80004d80: dd9ff06f j 80004b58 <_free_r+0xd4> +80004cd4 <_fwalk>: +80004cd4: fe010113 addi sp,sp,-32 +80004cd8: 01212823 sw s2,16(sp) +80004cdc: 01312623 sw s3,12(sp) +80004ce0: 01412423 sw s4,8(sp) +80004ce4: 01512223 sw s5,4(sp) +80004ce8: 01612023 sw s6,0(sp) +80004cec: 00112e23 sw ra,28(sp) +80004cf0: 00812c23 sw s0,24(sp) +80004cf4: 00912a23 sw s1,20(sp) +80004cf8: 00058b13 mv s6,a1 +80004cfc: 2e050a93 addi s5,a0,736 +80004d00: 00000a13 li s4,0 +80004d04: 00100993 li s3,1 +80004d08: fff00913 li s2,-1 +80004d0c: 004aa483 lw s1,4(s5) +80004d10: 008aa403 lw s0,8(s5) +80004d14: fff48493 addi s1,s1,-1 +80004d18: 0204c663 bltz s1,80004d44 <_fwalk+0x70> +80004d1c: 00c45783 lhu a5,12(s0) +80004d20: fff48493 addi s1,s1,-1 +80004d24: 00f9fc63 bgeu s3,a5,80004d3c <_fwalk+0x68> +80004d28: 00e41783 lh a5,14(s0) +80004d2c: 00040513 mv a0,s0 +80004d30: 01278663 beq a5,s2,80004d3c <_fwalk+0x68> +80004d34: 000b00e7 jalr s6 +80004d38: 00aa6a33 or s4,s4,a0 +80004d3c: 06840413 addi s0,s0,104 +80004d40: fd249ee3 bne s1,s2,80004d1c <_fwalk+0x48> +80004d44: 000aaa83 lw s5,0(s5) +80004d48: fc0a92e3 bnez s5,80004d0c <_fwalk+0x38> +80004d4c: 01c12083 lw ra,28(sp) +80004d50: 01812403 lw s0,24(sp) +80004d54: 01412483 lw s1,20(sp) +80004d58: 01012903 lw s2,16(sp) +80004d5c: 00c12983 lw s3,12(sp) +80004d60: 00412a83 lw s5,4(sp) +80004d64: 00012b03 lw s6,0(sp) +80004d68: 000a0513 mv a0,s4 +80004d6c: 00812a03 lw s4,8(sp) +80004d70: 02010113 addi sp,sp,32 +80004d74: 00008067 ret -80004d84 <_fwalk>: -80004d84: fe010113 addi sp,sp,-32 -80004d88: 01212823 sw s2,16(sp) -80004d8c: 01312623 sw s3,12(sp) -80004d90: 01412423 sw s4,8(sp) -80004d94: 01512223 sw s5,4(sp) -80004d98: 01612023 sw s6,0(sp) -80004d9c: 00112e23 sw ra,28(sp) -80004da0: 00812c23 sw s0,24(sp) -80004da4: 00912a23 sw s1,20(sp) -80004da8: 00058b13 mv s6,a1 -80004dac: 2e050a93 addi s5,a0,736 -80004db0: 00000a13 li s4,0 -80004db4: 00100993 li s3,1 -80004db8: fff00913 li s2,-1 -80004dbc: 004aa483 lw s1,4(s5) -80004dc0: 008aa403 lw s0,8(s5) -80004dc4: fff48493 addi s1,s1,-1 -80004dc8: 0204c663 bltz s1,80004df4 <_fwalk+0x70> -80004dcc: 00c45783 lhu a5,12(s0) -80004dd0: fff48493 addi s1,s1,-1 -80004dd4: 00f9fc63 bgeu s3,a5,80004dec <_fwalk+0x68> -80004dd8: 00e41783 lh a5,14(s0) -80004ddc: 00040513 mv a0,s0 -80004de0: 01278663 beq a5,s2,80004dec <_fwalk+0x68> -80004de4: 000b00e7 jalr s6 +80004d78 <_fwalk_reent>: +80004d78: fd010113 addi sp,sp,-48 +80004d7c: 03212023 sw s2,32(sp) +80004d80: 01312e23 sw s3,28(sp) +80004d84: 01412c23 sw s4,24(sp) +80004d88: 01512a23 sw s5,20(sp) +80004d8c: 01612823 sw s6,16(sp) +80004d90: 01712623 sw s7,12(sp) +80004d94: 02112623 sw ra,44(sp) +80004d98: 02812423 sw s0,40(sp) +80004d9c: 02912223 sw s1,36(sp) +80004da0: 00050a93 mv s5,a0 +80004da4: 00058b93 mv s7,a1 +80004da8: 2e050b13 addi s6,a0,736 +80004dac: 00000a13 li s4,0 +80004db0: 00100993 li s3,1 +80004db4: fff00913 li s2,-1 +80004db8: 004b2483 lw s1,4(s6) +80004dbc: 008b2403 lw s0,8(s6) +80004dc0: fff48493 addi s1,s1,-1 +80004dc4: 0204c863 bltz s1,80004df4 <_fwalk_reent+0x7c> +80004dc8: 00c45783 lhu a5,12(s0) +80004dcc: fff48493 addi s1,s1,-1 +80004dd0: 00f9fe63 bgeu s3,a5,80004dec <_fwalk_reent+0x74> +80004dd4: 00e41783 lh a5,14(s0) +80004dd8: 00040593 mv a1,s0 +80004ddc: 000a8513 mv a0,s5 +80004de0: 01278663 beq a5,s2,80004dec <_fwalk_reent+0x74> +80004de4: 000b80e7 jalr s7 80004de8: 00aa6a33 or s4,s4,a0 80004dec: 06840413 addi s0,s0,104 -80004df0: fd249ee3 bne s1,s2,80004dcc <_fwalk+0x48> -80004df4: 000aaa83 lw s5,0(s5) -80004df8: fc0a92e3 bnez s5,80004dbc <_fwalk+0x38> -80004dfc: 01c12083 lw ra,28(sp) -80004e00: 01812403 lw s0,24(sp) -80004e04: 01412483 lw s1,20(sp) -80004e08: 01012903 lw s2,16(sp) -80004e0c: 00c12983 lw s3,12(sp) -80004e10: 00412a83 lw s5,4(sp) -80004e14: 00012b03 lw s6,0(sp) -80004e18: 000a0513 mv a0,s4 -80004e1c: 00812a03 lw s4,8(sp) -80004e20: 02010113 addi sp,sp,32 -80004e24: 00008067 ret +80004df0: fd249ce3 bne s1,s2,80004dc8 <_fwalk_reent+0x50> +80004df4: 000b2b03 lw s6,0(s6) +80004df8: fc0b10e3 bnez s6,80004db8 <_fwalk_reent+0x40> +80004dfc: 02c12083 lw ra,44(sp) +80004e00: 02812403 lw s0,40(sp) +80004e04: 02412483 lw s1,36(sp) +80004e08: 02012903 lw s2,32(sp) +80004e0c: 01c12983 lw s3,28(sp) +80004e10: 01412a83 lw s5,20(sp) +80004e14: 01012b03 lw s6,16(sp) +80004e18: 00c12b83 lw s7,12(sp) +80004e1c: 000a0513 mv a0,s4 +80004e20: 01812a03 lw s4,24(sp) +80004e24: 03010113 addi sp,sp,48 +80004e28: 00008067 ret -80004e28 <_fwalk_reent>: -80004e28: fd010113 addi sp,sp,-48 -80004e2c: 03212023 sw s2,32(sp) -80004e30: 01312e23 sw s3,28(sp) -80004e34: 01412c23 sw s4,24(sp) -80004e38: 01512a23 sw s5,20(sp) -80004e3c: 01612823 sw s6,16(sp) -80004e40: 01712623 sw s7,12(sp) -80004e44: 02112623 sw ra,44(sp) -80004e48: 02812423 sw s0,40(sp) -80004e4c: 02912223 sw s1,36(sp) -80004e50: 00050a93 mv s5,a0 -80004e54: 00058b93 mv s7,a1 -80004e58: 2e050b13 addi s6,a0,736 -80004e5c: 00000a13 li s4,0 -80004e60: 00100993 li s3,1 -80004e64: fff00913 li s2,-1 -80004e68: 004b2483 lw s1,4(s6) -80004e6c: 008b2403 lw s0,8(s6) -80004e70: fff48493 addi s1,s1,-1 -80004e74: 0204c863 bltz s1,80004ea4 <_fwalk_reent+0x7c> -80004e78: 00c45783 lhu a5,12(s0) -80004e7c: fff48493 addi s1,s1,-1 -80004e80: 00f9fe63 bgeu s3,a5,80004e9c <_fwalk_reent+0x74> -80004e84: 00e41783 lh a5,14(s0) -80004e88: 00040593 mv a1,s0 -80004e8c: 000a8513 mv a0,s5 -80004e90: 01278663 beq a5,s2,80004e9c <_fwalk_reent+0x74> -80004e94: 000b80e7 jalr s7 -80004e98: 00aa6a33 or s4,s4,a0 -80004e9c: 06840413 addi s0,s0,104 -80004ea0: fd249ce3 bne s1,s2,80004e78 <_fwalk_reent+0x50> -80004ea4: 000b2b03 lw s6,0(s6) -80004ea8: fc0b10e3 bnez s6,80004e68 <_fwalk_reent+0x40> -80004eac: 02c12083 lw ra,44(sp) -80004eb0: 02812403 lw s0,40(sp) -80004eb4: 02412483 lw s1,36(sp) -80004eb8: 02012903 lw s2,32(sp) -80004ebc: 01c12983 lw s3,28(sp) -80004ec0: 01412a83 lw s5,20(sp) -80004ec4: 01012b03 lw s6,16(sp) -80004ec8: 00c12b83 lw s7,12(sp) -80004ecc: 000a0513 mv a0,s4 -80004ed0: 01812a03 lw s4,24(sp) -80004ed4: 03010113 addi sp,sp,48 -80004ed8: 00008067 ret +80004e2c : +80004e2c: 00450693 addi a3,a0,4 +80004e30: 00000793 li a5,0 +80004e34: 01a50513 addi a0,a0,26 +80004e38: ffff8837 lui a6,0xffff8 +80004e3c: 01c0006f j 80004e58 +80004e40: 00179793 slli a5,a5,0x1 +80004e44: 00e69023 sh a4,0(a3) +80004e48: 01079793 slli a5,a5,0x10 +80004e4c: 00268693 addi a3,a3,2 +80004e50: 0107d793 srli a5,a5,0x10 +80004e54: 02d50e63 beq a0,a3,80004e90 +80004e58: 0006d703 lhu a4,0(a3) +80004e5c: 00177613 andi a2,a4,1 +80004e60: 00060463 beqz a2,80004e68 +80004e64: 0017e793 ori a5,a5,1 +80004e68: 00175713 srli a4,a4,0x1 +80004e6c: 0027f613 andi a2,a5,2 +80004e70: 010765b3 or a1,a4,a6 +80004e74: fc0606e3 beqz a2,80004e40 +80004e78: 00179793 slli a5,a5,0x1 +80004e7c: 00b69023 sh a1,0(a3) +80004e80: 01079793 slli a5,a5,0x10 +80004e84: 00268693 addi a3,a3,2 +80004e88: 0107d793 srli a5,a5,0x10 +80004e8c: fcd516e3 bne a0,a3,80004e58 +80004e90: 00008067 ret -80004edc : -80004edc: 00450693 addi a3,a0,4 -80004ee0: 00000793 li a5,0 -80004ee4: 01a50513 addi a0,a0,26 -80004ee8: ffff8837 lui a6,0xffff8 -80004eec: 01c0006f j 80004f08 -80004ef0: 00179793 slli a5,a5,0x1 -80004ef4: 00e69023 sh a4,0(a3) -80004ef8: 01079793 slli a5,a5,0x10 -80004efc: 00268693 addi a3,a3,2 -80004f00: 0107d793 srli a5,a5,0x10 -80004f04: 02d50e63 beq a0,a3,80004f40 -80004f08: 0006d703 lhu a4,0(a3) -80004f0c: 00177613 andi a2,a4,1 -80004f10: 00060463 beqz a2,80004f18 -80004f14: 0017e793 ori a5,a5,1 -80004f18: 00175713 srli a4,a4,0x1 -80004f1c: 0027f613 andi a2,a5,2 -80004f20: 010765b3 or a1,a4,a6 -80004f24: fc0606e3 beqz a2,80004ef0 -80004f28: 00179793 slli a5,a5,0x1 -80004f2c: 00b69023 sh a1,0(a3) -80004f30: 01079793 slli a5,a5,0x10 -80004f34: 00268693 addi a3,a3,2 -80004f38: 0107d793 srli a5,a5,0x10 -80004f3c: fcd516e3 bne a0,a3,80004f08 -80004f40: 00008067 ret +80004e94 : +80004e94: 01850693 addi a3,a0,24 +80004e98: 00000713 li a4,0 +80004e9c: 00250513 addi a0,a0,2 +80004ea0: 01c0006f j 80004ebc +80004ea4: 00171713 slli a4,a4,0x1 +80004ea8: 00f69023 sh a5,0(a3) +80004eac: 01071713 slli a4,a4,0x10 +80004eb0: ffe68693 addi a3,a3,-2 +80004eb4: 01075713 srli a4,a4,0x10 +80004eb8: 04d50463 beq a0,a3,80004f00 +80004ebc: 0006d783 lhu a5,0(a3) +80004ec0: 01079613 slli a2,a5,0x10 +80004ec4: 41065613 srai a2,a2,0x10 +80004ec8: 00179793 slli a5,a5,0x1 +80004ecc: 00065463 bgez a2,80004ed4 +80004ed0: 00176713 ori a4,a4,1 +80004ed4: 01079793 slli a5,a5,0x10 +80004ed8: 0107d793 srli a5,a5,0x10 +80004edc: 00277613 andi a2,a4,2 +80004ee0: 0017e593 ori a1,a5,1 +80004ee4: fc0600e3 beqz a2,80004ea4 +80004ee8: 00171713 slli a4,a4,0x1 +80004eec: 00b69023 sh a1,0(a3) +80004ef0: 01071713 slli a4,a4,0x10 +80004ef4: ffe68693 addi a3,a3,-2 +80004ef8: 01075713 srli a4,a4,0x10 +80004efc: fcd510e3 bne a0,a3,80004ebc +80004f00: 00008067 ret -80004f44 : -80004f44: 01850693 addi a3,a0,24 -80004f48: 00000713 li a4,0 -80004f4c: 00250513 addi a0,a0,2 -80004f50: 01c0006f j 80004f6c -80004f54: 00171713 slli a4,a4,0x1 -80004f58: 00f69023 sh a5,0(a3) -80004f5c: 01071713 slli a4,a4,0x10 -80004f60: ffe68693 addi a3,a3,-2 -80004f64: 01075713 srli a4,a4,0x10 -80004f68: 04d50463 beq a0,a3,80004fb0 -80004f6c: 0006d783 lhu a5,0(a3) -80004f70: 01079613 slli a2,a5,0x10 -80004f74: 41065613 srai a2,a2,0x10 -80004f78: 00179793 slli a5,a5,0x1 -80004f7c: 00065463 bgez a2,80004f84 -80004f80: 00176713 ori a4,a4,1 -80004f84: 01079793 slli a5,a5,0x10 -80004f88: 0107d793 srli a5,a5,0x10 -80004f8c: 00277613 andi a2,a4,2 -80004f90: 0017e593 ori a1,a5,1 -80004f94: fc0600e3 beqz a2,80004f54 -80004f98: 00171713 slli a4,a4,0x1 -80004f9c: 00b69023 sh a1,0(a3) -80004fa0: 01071713 slli a4,a4,0x10 -80004fa4: ffe68693 addi a3,a3,-2 -80004fa8: 01075713 srli a4,a4,0x10 -80004fac: fcd510e3 bne a0,a3,80004f6c -80004fb0: 00008067 ret +80004f04 : +80004f04: fe010113 addi sp,sp,-32 +80004f08: 00010e37 lui t3,0x10 +80004f0c: 00011d23 sh zero,26(sp) +80004f10: 00011e23 sh zero,28(sp) +80004f14: 01858593 addi a1,a1,24 +80004f18: 01c10793 addi a5,sp,28 +80004f1c: 00810813 addi a6,sp,8 +80004f20: fffe0e13 addi t3,t3,-1 # ffff <_start-0x7fff0001> +80004f24: 0005d703 lhu a4,0(a1) +80004f28: ffe78793 addi a5,a5,-2 +80004f2c: ffe58593 addi a1,a1,-2 +80004f30: 02071863 bnez a4,80004f60 +80004f34: fe079f23 sh zero,-2(a5) +80004f38: ff0796e3 bne a5,a6,80004f24 +80004f3c: 00460613 addi a2,a2,4 +80004f40: 01e10693 addi a3,sp,30 +80004f44: 0007d703 lhu a4,0(a5) +80004f48: 00278793 addi a5,a5,2 +80004f4c: 00260613 addi a2,a2,2 +80004f50: fee61f23 sh a4,-2(a2) +80004f54: fed798e3 bne a5,a3,80004f44 +80004f58: 02010113 addi sp,sp,32 +80004f5c: 00008067 ret +80004f60: 02a70733 mul a4,a4,a0 +80004f64: 0027d883 lhu a7,2(a5) +80004f68: 0007d303 lhu t1,0(a5) +80004f6c: 01c776b3 and a3,a4,t3 +80004f70: 011686b3 add a3,a3,a7 +80004f74: 01075713 srli a4,a4,0x10 +80004f78: 0106d893 srli a7,a3,0x10 +80004f7c: 00670733 add a4,a4,t1 +80004f80: 01170733 add a4,a4,a7 +80004f84: 01075893 srli a7,a4,0x10 +80004f88: 00d79123 sh a3,2(a5) +80004f8c: 00e79023 sh a4,0(a5) +80004f90: ff179f23 sh a7,-2(a5) +80004f94: f90798e3 bne a5,a6,80004f24 +80004f98: fa5ff06f j 80004f3c -80004fb4 : -80004fb4: fe010113 addi sp,sp,-32 -80004fb8: 00010e37 lui t3,0x10 -80004fbc: 00011d23 sh zero,26(sp) -80004fc0: 00011e23 sh zero,28(sp) -80004fc4: 01858593 addi a1,a1,24 -80004fc8: 01c10793 addi a5,sp,28 -80004fcc: 00810813 addi a6,sp,8 -80004fd0: fffe0e13 addi t3,t3,-1 # ffff <_start-0x7fff0001> -80004fd4: 0005d703 lhu a4,0(a1) -80004fd8: ffe78793 addi a5,a5,-2 -80004fdc: ffe58593 addi a1,a1,-2 -80004fe0: 02071863 bnez a4,80005010 -80004fe4: fe079f23 sh zero,-2(a5) -80004fe8: ff0796e3 bne a5,a6,80004fd4 -80004fec: 00460613 addi a2,a2,4 -80004ff0: 01e10693 addi a3,sp,30 -80004ff4: 0007d703 lhu a4,0(a5) -80004ff8: 00278793 addi a5,a5,2 -80004ffc: 00260613 addi a2,a2,2 -80005000: fee61f23 sh a4,-2(a2) -80005004: fed798e3 bne a5,a3,80004ff4 -80005008: 02010113 addi sp,sp,32 -8000500c: 00008067 ret -80005010: 02a70733 mul a4,a4,a0 -80005014: 0027d883 lhu a7,2(a5) -80005018: 0007d303 lhu t1,0(a5) -8000501c: 01c776b3 and a3,a4,t3 -80005020: 011686b3 add a3,a3,a7 -80005024: 01075713 srli a4,a4,0x10 -80005028: 0106d893 srli a7,a3,0x10 -8000502c: 00670733 add a4,a4,t1 -80005030: 01170733 add a4,a4,a7 -80005034: 01075893 srli a7,a4,0x10 -80005038: 00d79123 sh a3,2(a5) -8000503c: 00e79023 sh a4,0(a5) -80005040: ff179f23 sh a7,-2(a5) -80005044: f90798e3 bne a5,a6,80004fd4 -80005048: fa5ff06f j 80004fec +80004f9c : +80004f9c: 01250713 addi a4,a0,18 +80004fa0: 00055783 lhu a5,0(a0) +80004fa4: 00250513 addi a0,a0,2 +80004fa8: 00079863 bnez a5,80004fb8 +80004fac: fee51ae3 bne a0,a4,80004fa0 +80004fb0: 00000513 li a0,0 +80004fb4: 00008067 ret +80004fb8: 00100513 li a0,1 +80004fbc: 00008067 ret -8000504c : -8000504c: 01250713 addi a4,a0,18 -80005050: 00055783 lhu a5,0(a0) -80005054: 00250513 addi a0,a0,2 -80005058: 00079863 bnez a5,80005068 -8000505c: fee51ae3 bne a0,a4,80005050 -80005060: 00000513 li a0,0 -80005064: 00008067 ret -80005068: 00100513 li a0,1 -8000506c: 00008067 ret +80004fc0 : +80004fc0: ff010113 addi sp,sp,-16 +80004fc4: 00912223 sw s1,4(sp) +80004fc8: 01255483 lhu s1,18(a0) +80004fcc: 00812423 sw s0,8(sp) +80004fd0: 00112623 sw ra,12(sp) +80004fd4: fff4c793 not a5,s1 +80004fd8: 01179713 slli a4,a5,0x11 +80004fdc: 00050413 mv s0,a0 +80004fe0: 00071663 bnez a4,80004fec +80004fe4: fb9ff0ef jal ra,80004f9c +80004fe8: 00051863 bnez a0,80004ff8 +80004fec: ffff87b7 lui a5,0xffff8 +80004ff0: 00f4c4b3 xor s1,s1,a5 +80004ff4: 00941923 sh s1,18(s0) +80004ff8: 00c12083 lw ra,12(sp) +80004ffc: 00812403 lw s0,8(sp) +80005000: 00412483 lw s1,4(sp) +80005004: 01010113 addi sp,sp,16 +80005008: 00008067 ret -80005070 : -80005070: ff010113 addi sp,sp,-16 -80005074: 00912223 sw s1,4(sp) -80005078: 01255483 lhu s1,18(a0) -8000507c: 00812423 sw s0,8(sp) -80005080: 00112623 sw ra,12(sp) -80005084: fff4c793 not a5,s1 -80005088: 01179713 slli a4,a5,0x11 -8000508c: 00050413 mv s0,a0 -80005090: 00071663 bnez a4,8000509c -80005094: fb9ff0ef jal ra,8000504c -80005098: 00051863 bnez a0,800050a8 -8000509c: ffff87b7 lui a5,0xffff8 -800050a0: 00f4c4b3 xor s1,s1,a5 -800050a4: 00941923 sh s1,18(s0) -800050a8: 00c12083 lw ra,12(sp) -800050ac: 00812403 lw s0,8(sp) -800050b0: 00412483 lw s1,4(sp) -800050b4: 01010113 addi sp,sp,16 -800050b8: 00008067 ret +8000500c : +8000500c: ff010113 addi sp,sp,-16 +80005010: 00812423 sw s0,8(sp) +80005014: 01255403 lhu s0,18(a0) +80005018: 00112623 sw ra,12(sp) +8000501c: fff44793 not a5,s0 +80005020: 01179713 slli a4,a5,0x11 +80005024: 00071a63 bnez a4,80005038 +80005028: f75ff0ef jal ra,80004f9c +8000502c: 00050793 mv a5,a0 +80005030: 00000513 li a0,0 +80005034: 00079463 bnez a5,8000503c +80005038: 00f45513 srli a0,s0,0xf +8000503c: 00c12083 lw ra,12(sp) +80005040: 00812403 lw s0,8(sp) +80005044: 01010113 addi sp,sp,16 +80005048: 00008067 ret -800050bc : -800050bc: ff010113 addi sp,sp,-16 -800050c0: 00812423 sw s0,8(sp) -800050c4: 01255403 lhu s0,18(a0) -800050c8: 00112623 sw ra,12(sp) -800050cc: fff44793 not a5,s0 -800050d0: 01179713 slli a4,a5,0x11 -800050d4: 00071a63 bnez a4,800050e8 -800050d8: f75ff0ef jal ra,8000504c -800050dc: 00050793 mv a5,a0 -800050e0: 00000513 li a0,0 -800050e4: 00079463 bnez a5,800050ec -800050e8: 00f45513 srli a0,s0,0xf -800050ec: 00c12083 lw ra,12(sp) -800050f0: 00812403 lw s0,8(sp) -800050f4: 01010113 addi sp,sp,16 -800050f8: 00008067 ret +8000504c : +8000504c: 01255783 lhu a5,18(a0) +80005050: fd010113 addi sp,sp,-48 +80005054: 02812423 sw s0,40(sp) +80005058: 00f7d793 srli a5,a5,0xf +8000505c: 02912223 sw s1,36(sp) +80005060: 02112623 sw ra,44(sp) +80005064: 03212023 sw s2,32(sp) +80005068: 01312e23 sw s3,28(sp) +8000506c: 40f007b3 neg a5,a5 +80005070: 00f59023 sh a5,0(a1) +80005074: 01255783 lhu a5,18(a0) +80005078: 00008737 lui a4,0x8 +8000507c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80005080: 00f777b3 and a5,a4,a5 +80005084: 00f59123 sh a5,2(a1) +80005088: 00050493 mv s1,a0 +8000508c: 01050413 addi s0,a0,16 +80005090: 04e78263 beq a5,a4,800050d4 +80005094: 00658793 addi a5,a1,6 +80005098: 00059223 sh zero,4(a1) +8000509c: ffe50513 addi a0,a0,-2 +800050a0: 00045703 lhu a4,0(s0) +800050a4: ffe40413 addi s0,s0,-2 +800050a8: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe13c6> +800050ac: fee79f23 sh a4,-2(a5) +800050b0: fe8518e3 bne a0,s0,800050a0 +800050b4: 00059c23 sh zero,24(a1) +800050b8: 02c12083 lw ra,44(sp) +800050bc: 02812403 lw s0,40(sp) +800050c0: 02412483 lw s1,36(sp) +800050c4: 02012903 lw s2,32(sp) +800050c8: 01c12983 lw s3,28(sp) +800050cc: 03010113 addi sp,sp,48 +800050d0: 00008067 ret +800050d4: 01255703 lhu a4,18(a0) +800050d8: 00458913 addi s2,a1,4 +800050dc: 00e7f733 and a4,a5,a4 +800050e0: 02f71c63 bne a4,a5,80005118 +800050e4: 00b12623 sw a1,12(sp) +800050e8: eb5ff0ef jal ra,80004f9c +800050ec: 00c12583 lw a1,12(sp) +800050f0: 02050463 beqz a0,80005118 +800050f4: 00658793 addi a5,a1,6 +800050f8: 00059223 sh zero,4(a1) +800050fc: ffc48513 addi a0,s1,-4 +80005100: 00045703 lhu a4,0(s0) +80005104: ffe40413 addi s0,s0,-2 +80005108: 00278793 addi a5,a5,2 +8000510c: fee79f23 sh a4,-2(a5) +80005110: fe8518e3 bne a0,s0,80005100 +80005114: fa5ff06f j 800050b8 +80005118: 01a58993 addi s3,a1,26 +8000511c: 00290913 addi s2,s2,2 +80005120: fe091f23 sh zero,-2(s2) +80005124: ff299ce3 bne s3,s2,8000511c +80005128: 02c12083 lw ra,44(sp) +8000512c: 02812403 lw s0,40(sp) +80005130: 02412483 lw s1,36(sp) +80005134: 02012903 lw s2,32(sp) +80005138: 01c12983 lw s3,28(sp) +8000513c: 03010113 addi sp,sp,48 +80005140: 00008067 ret -800050fc : -800050fc: 01255783 lhu a5,18(a0) -80005100: fd010113 addi sp,sp,-48 -80005104: 02812423 sw s0,40(sp) -80005108: 00f7d793 srli a5,a5,0xf -8000510c: 02912223 sw s1,36(sp) -80005110: 02112623 sw ra,44(sp) -80005114: 03212023 sw s2,32(sp) -80005118: 01312e23 sw s3,28(sp) -8000511c: 40f007b3 neg a5,a5 -80005120: 00f59023 sh a5,0(a1) -80005124: 01255783 lhu a5,18(a0) -80005128: 00008737 lui a4,0x8 -8000512c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80005130: 00f777b3 and a5,a4,a5 -80005134: 00f59123 sh a5,2(a1) -80005138: 00050493 mv s1,a0 -8000513c: 01050413 addi s0,a0,16 -80005140: 04e78263 beq a5,a4,80005184 -80005144: 00658793 addi a5,a1,6 -80005148: 00059223 sh zero,4(a1) -8000514c: ffe50513 addi a0,a0,-2 -80005150: 00045703 lhu a4,0(s0) -80005154: ffe40413 addi s0,s0,-2 -80005158: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe13d2> -8000515c: fee79f23 sh a4,-2(a5) -80005160: fe8518e3 bne a0,s0,80005150 -80005164: 00059c23 sh zero,24(a1) -80005168: 02c12083 lw ra,44(sp) -8000516c: 02812403 lw s0,40(sp) -80005170: 02412483 lw s1,36(sp) -80005174: 02012903 lw s2,32(sp) -80005178: 01c12983 lw s3,28(sp) -8000517c: 03010113 addi sp,sp,48 -80005180: 00008067 ret -80005184: 01255703 lhu a4,18(a0) -80005188: 00458913 addi s2,a1,4 -8000518c: 00e7f733 and a4,a5,a4 -80005190: 02f71c63 bne a4,a5,800051c8 -80005194: 00b12623 sw a1,12(sp) -80005198: eb5ff0ef jal ra,8000504c -8000519c: 00c12583 lw a1,12(sp) -800051a0: 02050463 beqz a0,800051c8 -800051a4: 00658793 addi a5,a1,6 -800051a8: 00059223 sh zero,4(a1) -800051ac: ffc48513 addi a0,s1,-4 -800051b0: 00045703 lhu a4,0(s0) -800051b4: ffe40413 addi s0,s0,-2 +80005144 : +80005144: 01255783 lhu a5,18(a0) +80005148: fb010113 addi sp,sp,-80 +8000514c: 04812423 sw s0,72(sp) +80005150: fff7c793 not a5,a5 +80005154: 04912223 sw s1,68(sp) +80005158: 04112623 sw ra,76(sp) +8000515c: 01179713 slli a4,a5,0x11 +80005160: 00050493 mv s1,a0 +80005164: 00058413 mv s0,a1 +80005168: 00071663 bnez a4,80005174 +8000516c: e31ff0ef jal ra,80004f9c +80005170: 08051263 bnez a0,800051f4 +80005174: 01245783 lhu a5,18(s0) +80005178: fff7c793 not a5,a5 +8000517c: 01179713 slli a4,a5,0x11 +80005180: 06070463 beqz a4,800051e8 +80005184: 00810593 addi a1,sp,8 +80005188: 00048513 mv a0,s1 +8000518c: ec1ff0ef jal ra,8000504c +80005190: 02410593 addi a1,sp,36 +80005194: 00040513 mv a0,s0 +80005198: eb5ff0ef jal ra,8000504c +8000519c: 00815583 lhu a1,8(sp) +800051a0: 02415503 lhu a0,36(sp) +800051a4: 04b50c63 beq a0,a1,800051fc +800051a8: 00a10793 addi a5,sp,10 +800051ac: 02610713 addi a4,sp,38 +800051b0: 02010613 addi a2,sp,32 +800051b4: 0007d683 lhu a3,0(a5) 800051b8: 00278793 addi a5,a5,2 -800051bc: fee79f23 sh a4,-2(a5) -800051c0: fe8518e3 bne a0,s0,800051b0 -800051c4: fa5ff06f j 80005168 -800051c8: 01a58993 addi s3,a1,26 -800051cc: 00290913 addi s2,s2,2 -800051d0: fe091f23 sh zero,-2(s2) -800051d4: ff299ce3 bne s3,s2,800051cc -800051d8: 02c12083 lw ra,44(sp) -800051dc: 02812403 lw s0,40(sp) -800051e0: 02412483 lw s1,36(sp) -800051e4: 02012903 lw s2,32(sp) -800051e8: 01c12983 lw s3,28(sp) -800051ec: 03010113 addi sp,sp,48 -800051f0: 00008067 ret +800051bc: 08069a63 bnez a3,80005250 +800051c0: 00075683 lhu a3,0(a4) +800051c4: 00270713 addi a4,a4,2 +800051c8: 08069463 bnez a3,80005250 +800051cc: fec794e3 bne a5,a2,800051b4 +800051d0: 00000513 li a0,0 +800051d4: 04c12083 lw ra,76(sp) +800051d8: 04812403 lw s0,72(sp) +800051dc: 04412483 lw s1,68(sp) +800051e0: 05010113 addi sp,sp,80 +800051e4: 00008067 ret +800051e8: 00040513 mv a0,s0 +800051ec: db1ff0ef jal ra,80004f9c +800051f0: f8050ae3 beqz a0,80005184 +800051f4: ffe00513 li a0,-2 +800051f8: fddff06f j 800051d4 +800051fc: 00153513 seqz a0,a0 +80005200: 00a15603 lhu a2,10(sp) +80005204: 02615683 lhu a3,38(sp) +80005208: 40a00533 neg a0,a0 +8000520c: 00a10713 addi a4,sp,10 +80005210: 02610793 addi a5,sp,38 +80005214: 00257513 andi a0,a0,2 +80005218: fff50513 addi a0,a0,-1 +8000521c: 03c10593 addi a1,sp,60 +80005220: 00278793 addi a5,a5,2 +80005224: 00270713 addi a4,a4,2 +80005228: 00d61e63 bne a2,a3,80005244 +8000522c: fab782e3 beq a5,a1,800051d0 +80005230: 00075603 lhu a2,0(a4) +80005234: 0007d683 lhu a3,0(a5) +80005238: 00270713 addi a4,a4,2 +8000523c: 00278793 addi a5,a5,2 +80005240: fed606e3 beq a2,a3,8000522c +80005244: f8c6e8e3 bltu a3,a2,800051d4 +80005248: 40a00533 neg a0,a0 +8000524c: f89ff06f j 800051d4 +80005250: 00100513 li a0,1 +80005254: f80580e3 beqz a1,800051d4 +80005258: fff00513 li a0,-1 +8000525c: f79ff06f j 800051d4 -800051f4 : -800051f4: 01255783 lhu a5,18(a0) -800051f8: fb010113 addi sp,sp,-80 -800051fc: 04812423 sw s0,72(sp) -80005200: fff7c793 not a5,a5 -80005204: 04912223 sw s1,68(sp) -80005208: 04112623 sw ra,76(sp) -8000520c: 01179713 slli a4,a5,0x11 -80005210: 00050493 mv s1,a0 -80005214: 00058413 mv s0,a1 -80005218: 00071663 bnez a4,80005224 -8000521c: e31ff0ef jal ra,8000504c -80005220: 08051263 bnez a0,800052a4 -80005224: 01245783 lhu a5,18(s0) -80005228: fff7c793 not a5,a5 -8000522c: 01179713 slli a4,a5,0x11 -80005230: 06070463 beqz a4,80005298 -80005234: 00810593 addi a1,sp,8 -80005238: 00048513 mv a0,s1 -8000523c: ec1ff0ef jal ra,800050fc -80005240: 02410593 addi a1,sp,36 -80005244: 00040513 mv a0,s0 -80005248: eb5ff0ef jal ra,800050fc -8000524c: 00815583 lhu a1,8(sp) -80005250: 02415503 lhu a0,36(sp) -80005254: 04b50c63 beq a0,a1,800052ac -80005258: 00a10793 addi a5,sp,10 -8000525c: 02610713 addi a4,sp,38 -80005260: 02010613 addi a2,sp,32 -80005264: 0007d683 lhu a3,0(a5) -80005268: 00278793 addi a5,a5,2 -8000526c: 08069a63 bnez a3,80005300 -80005270: 00075683 lhu a3,0(a4) -80005274: 00270713 addi a4,a4,2 -80005278: 08069463 bnez a3,80005300 -8000527c: fec794e3 bne a5,a2,80005264 -80005280: 00000513 li a0,0 -80005284: 04c12083 lw ra,76(sp) -80005288: 04812403 lw s0,72(sp) -8000528c: 04412483 lw s1,68(sp) -80005290: 05010113 addi sp,sp,80 -80005294: 00008067 ret -80005298: 00040513 mv a0,s0 -8000529c: db1ff0ef jal ra,8000504c -800052a0: f8050ae3 beqz a0,80005234 -800052a4: ffe00513 li a0,-2 -800052a8: fddff06f j 80005284 -800052ac: 00153513 seqz a0,a0 -800052b0: 00a15603 lhu a2,10(sp) -800052b4: 02615683 lhu a3,38(sp) -800052b8: 40a00533 neg a0,a0 -800052bc: 00a10713 addi a4,sp,10 -800052c0: 02610793 addi a5,sp,38 -800052c4: 00257513 andi a0,a0,2 -800052c8: fff50513 addi a0,a0,-1 -800052cc: 03c10593 addi a1,sp,60 -800052d0: 00278793 addi a5,a5,2 -800052d4: 00270713 addi a4,a4,2 -800052d8: 00d61e63 bne a2,a3,800052f4 -800052dc: fab782e3 beq a5,a1,80005280 -800052e0: 00075603 lhu a2,0(a4) -800052e4: 0007d683 lhu a3,0(a5) -800052e8: 00270713 addi a4,a4,2 -800052ec: 00278793 addi a5,a5,2 -800052f0: fed606e3 beq a2,a3,800052dc -800052f4: f8c6e8e3 bltu a3,a2,80005284 -800052f8: 40a00533 neg a0,a0 -800052fc: f89ff06f j 80005284 -80005300: 00100513 li a0,1 -80005304: f80580e3 beqz a1,80005284 -80005308: fff00513 li a0,-1 -8000530c: f79ff06f j 80005284 +80005260 : +80005260: ff010113 addi sp,sp,-16 +80005264: 00112623 sw ra,12(sp) +80005268: d35ff0ef jal ra,80004f9c +8000526c: 00c12083 lw ra,12(sp) +80005270: 00153513 seqz a0,a0 +80005274: 01010113 addi sp,sp,16 +80005278: 00008067 ret -80005310 : -80005310: ff010113 addi sp,sp,-16 -80005314: 00112623 sw ra,12(sp) -80005318: d35ff0ef jal ra,8000504c -8000531c: 00c12083 lw ra,12(sp) -80005320: 00153513 seqz a0,a0 -80005324: 01010113 addi sp,sp,16 -80005328: 00008067 ret +8000527c : +8000527c: fe010113 addi sp,sp,-32 +80005280: 00812c23 sw s0,24(sp) +80005284: 00912a23 sw s1,20(sp) +80005288: 00112e23 sw ra,28(sp) +8000528c: 01212823 sw s2,16(sp) +80005290: 01312623 sw s3,12(sp) +80005294: 00058493 mv s1,a1 +80005298: 00050413 mv s0,a0 +8000529c: 0a05c463 bltz a1,80005344 +800052a0: 00f00793 li a5,15 +800052a4: 00058613 mv a2,a1 +800052a8: 00450513 addi a0,a0,4 +800052ac: 01840693 addi a3,s0,24 +800052b0: 00f00593 li a1,15 +800052b4: 0297d463 bge a5,s1,800052dc +800052b8: 00050793 mv a5,a0 +800052bc: 0027d703 lhu a4,2(a5) +800052c0: 00278793 addi a5,a5,2 +800052c4: fee79f23 sh a4,-2(a5) +800052c8: fed79ae3 bne a5,a3,800052bc +800052cc: 00041c23 sh zero,24(s0) +800052d0: ff060613 addi a2,a2,-16 +800052d4: fec5c2e3 blt a1,a2,800052b8 +800052d8: 00f4f493 andi s1,s1,15 +800052dc: 00700793 li a5,7 +800052e0: 0297d863 bge a5,s1,80005310 +800052e4: 01840713 addi a4,s0,24 +800052e8: 00240593 addi a1,s0,2 +800052ec: 00000793 li a5,0 +800052f0: 00075683 lhu a3,0(a4) +800052f4: ffe70713 addi a4,a4,-2 +800052f8: 00869613 slli a2,a3,0x8 +800052fc: 00c7e7b3 or a5,a5,a2 +80005300: 00f71123 sh a5,2(a4) +80005304: 0086d793 srli a5,a3,0x8 +80005308: feb714e3 bne a4,a1,800052f0 +8000530c: ff848493 addi s1,s1,-8 +80005310: 00048a63 beqz s1,80005324 +80005314: fff48493 addi s1,s1,-1 +80005318: 00040513 mv a0,s0 +8000531c: b79ff0ef jal ra,80004e94 +80005320: fe049ae3 bnez s1,80005314 +80005324: 00000513 li a0,0 +80005328: 01c12083 lw ra,28(sp) +8000532c: 01812403 lw s0,24(sp) +80005330: 01412483 lw s1,20(sp) +80005334: 01012903 lw s2,16(sp) +80005338: 00c12983 lw s3,12(sp) +8000533c: 02010113 addi sp,sp,32 +80005340: 00008067 ret +80005344: ff100793 li a5,-15 +80005348: 40b00933 neg s2,a1 +8000534c: 12f5dc63 bge a1,a5,80005484 +80005350: 01850593 addi a1,a0,24 +80005354: 00000993 li s3,0 +80005358: 00450693 addi a3,a0,4 +8000535c: 00f00613 li a2,15 +80005360: 01845703 lhu a4,24(s0) +80005364: 00058793 mv a5,a1 +80005368: 00e9e9b3 or s3,s3,a4 +8000536c: ffe7d703 lhu a4,-2(a5) +80005370: ffe78793 addi a5,a5,-2 +80005374: 00e79123 sh a4,2(a5) +80005378: fed79ae3 bne a5,a3,8000536c +8000537c: 00041223 sh zero,4(s0) +80005380: ff090913 addi s2,s2,-16 +80005384: fd264ee3 blt a2,s2,80005360 +80005388: ff000793 li a5,-16 +8000538c: ff100713 li a4,-15 +80005390: 409787b3 sub a5,a5,s1 +80005394: 00000913 li s2,0 +80005398: 0ae4c463 blt s1,a4,80005440 +8000539c: 00f90933 add s2,s2,a5 +800053a0: 00700793 li a5,7 +800053a4: 0527d663 bge a5,s2,800053f0 +800053a8: 01099993 slli s3,s3,0x10 +800053ac: 4109d993 srai s3,s3,0x10 +800053b0: 01844783 lbu a5,24(s0) +800053b4: 01a40593 addi a1,s0,26 +800053b8: 00f9e9b3 or s3,s3,a5 +800053bc: 01099993 slli s3,s3,0x10 +800053c0: 0109d993 srli s3,s3,0x10 +800053c4: 00000793 li a5,0 +800053c8: 0006d603 lhu a2,0(a3) +800053cc: 00268693 addi a3,a3,2 +800053d0: 00865713 srli a4,a2,0x8 +800053d4: 00e7e733 or a4,a5,a4 +800053d8: 00861793 slli a5,a2,0x8 +800053dc: 01079793 slli a5,a5,0x10 +800053e0: fee69f23 sh a4,-2(a3) +800053e4: 0107d793 srli a5,a5,0x10 +800053e8: feb690e3 bne a3,a1,800053c8 +800053ec: ff890913 addi s2,s2,-8 +800053f0: 06090c63 beqz s2,80005468 +800053f4: 01845783 lhu a5,24(s0) +800053f8: fff90913 addi s2,s2,-1 +800053fc: 00040513 mv a0,s0 +80005400: 0017f793 andi a5,a5,1 +80005404: 0137e9b3 or s3,a5,s3 +80005408: a25ff0ef jal ra,80004e2c +8000540c: fe0914e3 bnez s2,800053f4 +80005410: 01099793 slli a5,s3,0x10 +80005414: 4107d793 srai a5,a5,0x10 +80005418: 04079063 bnez a5,80005458 +8000541c: 01099513 slli a0,s3,0x10 +80005420: 01055513 srli a0,a0,0x10 +80005424: 01c12083 lw ra,28(sp) +80005428: 01812403 lw s0,24(sp) +8000542c: 01412483 lw s1,20(sp) +80005430: 01012903 lw s2,16(sp) +80005434: 00c12983 lw s3,12(sp) +80005438: 02010113 addi sp,sp,32 +8000543c: 00008067 ret +80005440: ff07f913 andi s2,a5,-16 +80005444: 41200933 neg s2,s2 +80005448: 00f90933 add s2,s2,a5 +8000544c: 00700793 li a5,7 +80005450: fb27d0e3 bge a5,s2,800053f0 +80005454: f55ff06f j 800053a8 +80005458: 00100993 li s3,1 +8000545c: 01099513 slli a0,s3,0x10 +80005460: 01055513 srli a0,a0,0x10 +80005464: fc1ff06f j 80005424 +80005468: 00098513 mv a0,s3 +8000546c: 00099863 bnez s3,8000547c +80005470: 01051513 slli a0,a0,0x10 +80005474: 01055513 srli a0,a0,0x10 +80005478: eb1ff06f j 80005328 +8000547c: 00100513 li a0,1 +80005480: ff1ff06f j 80005470 +80005484: ff900793 li a5,-7 +80005488: 00000993 li s3,0 +8000548c: f6f5d4e3 bge a1,a5,800053f4 +80005490: 00440693 addi a3,s0,4 +80005494: f1dff06f j 800053b0 -8000532c : -8000532c: fe010113 addi sp,sp,-32 -80005330: 00812c23 sw s0,24(sp) -80005334: 00912a23 sw s1,20(sp) -80005338: 00112e23 sw ra,28(sp) -8000533c: 01212823 sw s2,16(sp) -80005340: 01312623 sw s3,12(sp) -80005344: 00058493 mv s1,a1 -80005348: 00050413 mv s0,a0 -8000534c: 0a05c463 bltz a1,800053f4 -80005350: 00f00793 li a5,15 -80005354: 00058613 mv a2,a1 -80005358: 00450513 addi a0,a0,4 -8000535c: 01840693 addi a3,s0,24 -80005360: 00f00593 li a1,15 -80005364: 0297d463 bge a5,s1,8000538c -80005368: 00050793 mv a5,a0 -8000536c: 0027d703 lhu a4,2(a5) -80005370: 00278793 addi a5,a5,2 -80005374: fee79f23 sh a4,-2(a5) -80005378: fed79ae3 bne a5,a3,8000536c -8000537c: 00041c23 sh zero,24(s0) -80005380: ff060613 addi a2,a2,-16 -80005384: fec5c2e3 blt a1,a2,80005368 -80005388: 00f4f493 andi s1,s1,15 -8000538c: 00700793 li a5,7 -80005390: 0297d863 bge a5,s1,800053c0 -80005394: 01840713 addi a4,s0,24 -80005398: 00240593 addi a1,s0,2 -8000539c: 00000793 li a5,0 -800053a0: 00075683 lhu a3,0(a4) -800053a4: ffe70713 addi a4,a4,-2 -800053a8: 00869613 slli a2,a3,0x8 -800053ac: 00c7e7b3 or a5,a5,a2 -800053b0: 00f71123 sh a5,2(a4) -800053b4: 0086d793 srli a5,a3,0x8 -800053b8: feb714e3 bne a4,a1,800053a0 -800053bc: ff848493 addi s1,s1,-8 -800053c0: 00048a63 beqz s1,800053d4 -800053c4: fff48493 addi s1,s1,-1 -800053c8: 00040513 mv a0,s0 -800053cc: b79ff0ef jal ra,80004f44 -800053d0: fe049ae3 bnez s1,800053c4 -800053d4: 00000513 li a0,0 -800053d8: 01c12083 lw ra,28(sp) -800053dc: 01812403 lw s0,24(sp) -800053e0: 01412483 lw s1,20(sp) -800053e4: 01012903 lw s2,16(sp) -800053e8: 00c12983 lw s3,12(sp) -800053ec: 02010113 addi sp,sp,32 -800053f0: 00008067 ret -800053f4: ff100793 li a5,-15 -800053f8: 40b00933 neg s2,a1 -800053fc: 12f5dc63 bge a1,a5,80005534 -80005400: 01850593 addi a1,a0,24 -80005404: 00000993 li s3,0 -80005408: 00450693 addi a3,a0,4 -8000540c: 00f00613 li a2,15 -80005410: 01845703 lhu a4,24(s0) -80005414: 00058793 mv a5,a1 -80005418: 00e9e9b3 or s3,s3,a4 -8000541c: ffe7d703 lhu a4,-2(a5) -80005420: ffe78793 addi a5,a5,-2 -80005424: 00e79123 sh a4,2(a5) -80005428: fed79ae3 bne a5,a3,8000541c -8000542c: 00041223 sh zero,4(s0) -80005430: ff090913 addi s2,s2,-16 -80005434: fd264ee3 blt a2,s2,80005410 -80005438: ff000793 li a5,-16 -8000543c: ff100713 li a4,-15 -80005440: 409787b3 sub a5,a5,s1 -80005444: 00000913 li s2,0 -80005448: 0ae4c463 blt s1,a4,800054f0 -8000544c: 00f90933 add s2,s2,a5 -80005450: 00700793 li a5,7 -80005454: 0527d663 bge a5,s2,800054a0 -80005458: 01099993 slli s3,s3,0x10 -8000545c: 4109d993 srai s3,s3,0x10 -80005460: 01844783 lbu a5,24(s0) -80005464: 01a40593 addi a1,s0,26 -80005468: 00f9e9b3 or s3,s3,a5 -8000546c: 01099993 slli s3,s3,0x10 -80005470: 0109d993 srli s3,s3,0x10 -80005474: 00000793 li a5,0 -80005478: 0006d603 lhu a2,0(a3) -8000547c: 00268693 addi a3,a3,2 -80005480: 00865713 srli a4,a2,0x8 -80005484: 00e7e733 or a4,a5,a4 -80005488: 00861793 slli a5,a2,0x8 -8000548c: 01079793 slli a5,a5,0x10 -80005490: fee69f23 sh a4,-2(a3) -80005494: 0107d793 srli a5,a5,0x10 -80005498: feb690e3 bne a3,a1,80005478 -8000549c: ff890913 addi s2,s2,-8 -800054a0: 06090c63 beqz s2,80005518 -800054a4: 01845783 lhu a5,24(s0) -800054a8: fff90913 addi s2,s2,-1 -800054ac: 00040513 mv a0,s0 -800054b0: 0017f793 andi a5,a5,1 -800054b4: 0137e9b3 or s3,a5,s3 -800054b8: a25ff0ef jal ra,80004edc -800054bc: fe0914e3 bnez s2,800054a4 -800054c0: 01099793 slli a5,s3,0x10 +80005498 : +80005498: 00455783 lhu a5,4(a0) +8000549c: ff010113 addi sp,sp,-16 +800054a0: 00912223 sw s1,4(sp) +800054a4: 00112623 sw ra,12(sp) +800054a8: 00812423 sw s0,8(sp) +800054ac: 01212023 sw s2,0(sp) +800054b0: 00050493 mv s1,a0 +800054b4: 0c079c63 bnez a5,8000558c +800054b8: 00655703 lhu a4,6(a0) +800054bc: 00000413 li s0,0 +800054c0: 01071793 slli a5,a4,0x10 800054c4: 4107d793 srai a5,a5,0x10 -800054c8: 04079063 bnez a5,80005508 -800054cc: 01099513 slli a0,s3,0x10 -800054d0: 01055513 srli a0,a0,0x10 -800054d4: 01c12083 lw ra,28(sp) -800054d8: 01812403 lw s0,24(sp) -800054dc: 01412483 lw s1,20(sp) -800054e0: 01012903 lw s2,16(sp) -800054e4: 00c12983 lw s3,12(sp) -800054e8: 02010113 addi sp,sp,32 -800054ec: 00008067 ret -800054f0: ff07f913 andi s2,a5,-16 -800054f4: 41200933 neg s2,s2 -800054f8: 00f90933 add s2,s2,a5 -800054fc: 00700793 li a5,7 -80005500: fb27d0e3 bge a5,s2,800054a0 -80005504: f55ff06f j 80005458 -80005508: 00100993 li s3,1 -8000550c: 01099513 slli a0,s3,0x10 -80005510: 01055513 srli a0,a0,0x10 -80005514: fc1ff06f j 800054d4 -80005518: 00098513 mv a0,s3 -8000551c: 00099863 bnez s3,8000552c -80005520: 01051513 slli a0,a0,0x10 -80005524: 01055513 srli a0,a0,0x10 -80005528: eb1ff06f j 800053d8 -8000552c: 00100513 li a0,1 -80005530: ff1ff06f j 80005520 -80005534: ff900793 li a5,-7 -80005538: 00000993 li s3,0 -8000553c: f6f5d4e3 bge a1,a5,800054a4 -80005540: 00440693 addi a3,s0,4 -80005544: f1dff06f j 80005460 +800054c8: 0a07c463 bltz a5,80005570 +800054cc: 01a50693 addi a3,a0,26 +800054d0: 0a000613 li a2,160 +800054d4: 02071863 bnez a4,80005504 +800054d8: 00648793 addi a5,s1,6 +800054dc: 0080006f j 800054e4 +800054e0: 0007d703 lhu a4,0(a5) +800054e4: 00278793 addi a5,a5,2 +800054e8: fee79e23 sh a4,-4(a5) +800054ec: fef69ae3 bne a3,a5,800054e0 +800054f0: 00049c23 sh zero,24(s1) +800054f4: 01040413 addi s0,s0,16 +800054f8: 06c40c63 beq s0,a2,80005570 +800054fc: 0064d703 lhu a4,6(s1) +80005500: fc070ce3 beqz a4,800054d8 +80005504: f0077793 andi a5,a4,-256 +80005508: 04079063 bnez a5,80005548 +8000550c: 01848513 addi a0,s1,24 +80005510: 00248593 addi a1,s1,2 +80005514: 00000793 li a5,0 +80005518: 00050713 mv a4,a0 +8000551c: 00075683 lhu a3,0(a4) +80005520: ffe70713 addi a4,a4,-2 +80005524: 00869613 slli a2,a3,0x8 +80005528: 00c7e7b3 or a5,a5,a2 +8000552c: 00f71123 sh a5,2(a4) +80005530: 0086d793 srli a5,a3,0x8 +80005534: fee594e3 bne a1,a4,8000551c +80005538: 0064d703 lhu a4,6(s1) +8000553c: 00840413 addi s0,s0,8 +80005540: f0077793 andi a5,a4,-256 +80005544: fc0788e3 beqz a5,80005514 +80005548: 0a000913 li s2,160 +8000554c: 0140006f j 80005560 +80005550: 00140413 addi s0,s0,1 +80005554: 941ff0ef jal ra,80004e94 +80005558: 00894c63 blt s2,s0,80005570 +8000555c: 0064d703 lhu a4,6(s1) +80005560: 01071713 slli a4,a4,0x10 +80005564: 41075713 srai a4,a4,0x10 +80005568: 00048513 mv a0,s1 +8000556c: fe0752e3 bgez a4,80005550 +80005570: 00c12083 lw ra,12(sp) +80005574: 00040513 mv a0,s0 +80005578: 00812403 lw s0,8(sp) +8000557c: 00412483 lw s1,4(sp) +80005580: 00012903 lw s2,0(sp) +80005584: 01010113 addi sp,sp,16 +80005588: 00008067 ret +8000558c: f007f713 andi a4,a5,-256 +80005590: 00000413 li s0,0 +80005594: 04071063 bnez a4,800055d4 +80005598: f6f00913 li s2,-145 +8000559c: 0140006f j 800055b0 +800055a0: fff40413 addi s0,s0,-1 +800055a4: 889ff0ef jal ra,80004e2c +800055a8: fd2404e3 beq s0,s2,80005570 +800055ac: 0044d783 lhu a5,4(s1) +800055b0: 00048513 mv a0,s1 +800055b4: fe0796e3 bnez a5,800055a0 +800055b8: 00c12083 lw ra,12(sp) +800055bc: 00040513 mv a0,s0 +800055c0: 00812403 lw s0,8(sp) +800055c4: 00412483 lw s1,4(sp) +800055c8: 00012903 lw s2,0(sp) +800055cc: 01010113 addi sp,sp,16 +800055d0: 00008067 ret +800055d4: 00450693 addi a3,a0,4 +800055d8: 01a50593 addi a1,a0,26 +800055dc: 00000713 li a4,0 +800055e0: 0080006f j 800055e8 +800055e4: 0006d783 lhu a5,0(a3) +800055e8: 0087d613 srli a2,a5,0x8 +800055ec: 00c76733 or a4,a4,a2 +800055f0: 00879793 slli a5,a5,0x8 +800055f4: 00e69023 sh a4,0(a3) +800055f8: 01079713 slli a4,a5,0x10 +800055fc: 00268693 addi a3,a3,2 +80005600: 01075713 srli a4,a4,0x10 +80005604: feb690e3 bne a3,a1,800055e4 +80005608: 0044d783 lhu a5,4(s1) +8000560c: ff800413 li s0,-8 +80005610: f89ff06f j 80005598 -80005548 : -80005548: 00455783 lhu a5,4(a0) -8000554c: ff010113 addi sp,sp,-16 -80005550: 00912223 sw s1,4(sp) -80005554: 00112623 sw ra,12(sp) -80005558: 00812423 sw s0,8(sp) -8000555c: 01212023 sw s2,0(sp) -80005560: 00050493 mv s1,a0 -80005564: 0c079c63 bnez a5,8000563c -80005568: 00655703 lhu a4,6(a0) -8000556c: 00000413 li s0,0 -80005570: 01071793 slli a5,a4,0x10 -80005574: 4107d793 srai a5,a5,0x10 -80005578: 0a07c463 bltz a5,80005620 -8000557c: 01a50693 addi a3,a0,26 -80005580: 0a000613 li a2,160 -80005584: 02071863 bnez a4,800055b4 -80005588: 00648793 addi a5,s1,6 -8000558c: 0080006f j 80005594 -80005590: 0007d703 lhu a4,0(a5) -80005594: 00278793 addi a5,a5,2 -80005598: fee79e23 sh a4,-4(a5) -8000559c: fef69ae3 bne a3,a5,80005590 -800055a0: 00049c23 sh zero,24(s1) -800055a4: 01040413 addi s0,s0,16 -800055a8: 06c40c63 beq s0,a2,80005620 -800055ac: 0064d703 lhu a4,6(s1) -800055b0: fc070ce3 beqz a4,80005588 -800055b4: f0077793 andi a5,a4,-256 -800055b8: 04079063 bnez a5,800055f8 -800055bc: 01848513 addi a0,s1,24 -800055c0: 00248593 addi a1,s1,2 -800055c4: 00000793 li a5,0 -800055c8: 00050713 mv a4,a0 -800055cc: 00075683 lhu a3,0(a4) -800055d0: ffe70713 addi a4,a4,-2 -800055d4: 00869613 slli a2,a3,0x8 -800055d8: 00c7e7b3 or a5,a5,a2 -800055dc: 00f71123 sh a5,2(a4) -800055e0: 0086d793 srli a5,a3,0x8 -800055e4: fee594e3 bne a1,a4,800055cc -800055e8: 0064d703 lhu a4,6(s1) -800055ec: 00840413 addi s0,s0,8 -800055f0: f0077793 andi a5,a4,-256 -800055f4: fc0788e3 beqz a5,800055c4 -800055f8: 0a000913 li s2,160 -800055fc: 0140006f j 80005610 -80005600: 00140413 addi s0,s0,1 -80005604: 941ff0ef jal ra,80004f44 -80005608: 00894c63 blt s2,s0,80005620 -8000560c: 0064d703 lhu a4,6(s1) -80005610: 01071713 slli a4,a4,0x10 -80005614: 41075713 srai a4,a4,0x10 -80005618: 00048513 mv a0,s1 -8000561c: fe0752e3 bgez a4,80005600 -80005620: 00c12083 lw ra,12(sp) -80005624: 00040513 mv a0,s0 -80005628: 00812403 lw s0,8(sp) -8000562c: 00412483 lw s1,4(sp) -80005630: 00012903 lw s2,0(sp) -80005634: 01010113 addi sp,sp,16 -80005638: 00008067 ret -8000563c: f007f713 andi a4,a5,-256 -80005640: 00000413 li s0,0 -80005644: 04071063 bnez a4,80005684 -80005648: f6f00913 li s2,-145 -8000564c: 0140006f j 80005660 -80005650: fff40413 addi s0,s0,-1 -80005654: 889ff0ef jal ra,80004edc -80005658: fd2404e3 beq s0,s2,80005620 -8000565c: 0044d783 lhu a5,4(s1) -80005660: 00048513 mv a0,s1 -80005664: fe0796e3 bnez a5,80005650 -80005668: 00c12083 lw ra,12(sp) -8000566c: 00040513 mv a0,s0 -80005670: 00812403 lw s0,8(sp) -80005674: 00412483 lw s1,4(sp) -80005678: 00012903 lw s2,0(sp) -8000567c: 01010113 addi sp,sp,16 -80005680: 00008067 ret -80005684: 00450693 addi a3,a0,4 -80005688: 01a50593 addi a1,a0,26 -8000568c: 00000713 li a4,0 -80005690: 0080006f j 80005698 -80005694: 0006d783 lhu a5,0(a3) -80005698: 0087d613 srli a2,a5,0x8 -8000569c: 00c76733 or a4,a4,a2 -800056a0: 00879793 slli a5,a5,0x8 -800056a4: 00e69023 sh a4,0(a3) -800056a8: 01079713 slli a4,a5,0x10 -800056ac: 00268693 addi a3,a3,2 -800056b0: 01075713 srli a4,a4,0x10 -800056b4: feb690e3 bne a3,a1,80005694 -800056b8: 0044d783 lhu a5,4(s1) -800056bc: ff800413 li s0,-8 -800056c0: f89ff06f j 80005648 - -800056c4 : -800056c4: fe010113 addi sp,sp,-32 -800056c8: 00812c23 sw s0,24(sp) -800056cc: 00912a23 sw s1,20(sp) -800056d0: 01212823 sw s2,16(sp) -800056d4: 01312623 sw s3,12(sp) -800056d8: 01412423 sw s4,8(sp) -800056dc: 01512223 sw s5,4(sp) -800056e0: 00068913 mv s2,a3 -800056e4: 00078493 mv s1,a5 -800056e8: 00112e23 sw ra,28(sp) -800056ec: 00050413 mv s0,a0 -800056f0: 00058993 mv s3,a1 -800056f4: 00060a13 mv s4,a2 -800056f8: 00070a93 mv s5,a4 -800056fc: e4dff0ef jal ra,80005548 -80005700: 09000793 li a5,144 -80005704: 40a90933 sub s2,s2,a0 -80005708: 16a7dc63 bge a5,a0,80005880 -8000570c: 000087b7 lui a5,0x8 -80005710: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -80005714: 1f27da63 bge a5,s2,80005908 -80005718: 1c0a8463 beqz s5,800058e0 -8000571c: 0044a503 lw a0,4(s1) -80005720: 0004a783 lw a5,0(s1) -80005724: 06f50a63 beq a0,a5,80005798 -80005728: 01a48713 addi a4,s1,26 -8000572c: 03448793 addi a5,s1,52 -80005730: 00270713 addi a4,a4,2 -80005734: fe071f23 sh zero,-2(a4) -80005738: fef71ce3 bne a4,a5,80005730 -8000573c: 03800793 li a5,56 -80005740: 32f50c63 beq a0,a5,80005a78 -80005744: 16a7d063 bge a5,a0,800058a4 -80005748: 04000793 li a5,64 -8000574c: 2ef50c63 beq a0,a5,80005a44 -80005750: 07100793 li a5,113 -80005754: 34f51863 bne a0,a5,80005aa4 -80005758: 400087b7 lui a5,0x40008 -8000575c: fff78793 addi a5,a5,-1 # 40007fff <_start-0x3fff8001> -80005760: 00a00713 li a4,10 -80005764: 00f4aa23 sw a5,20(s1) -80005768: ffff87b7 lui a5,0xffff8 -8000576c: 00e4a423 sw a4,8(s1) -80005770: 00f49c23 sh a5,24(s1) -80005774: 00e4a623 sw a4,12(s1) -80005778: 00a00793 li a5,10 -8000577c: 00008737 lui a4,0x8 -80005780: 00878793 addi a5,a5,8 # ffff8008 <__BSS_END__+0x7ffe13d8> -80005784: 00179793 slli a5,a5,0x1 -80005788: 00f487b3 add a5,s1,a5 -8000578c: 00e79523 sh a4,10(a5) -80005790: 00a4a023 sw a0,0(s1) -80005794: 1b205863 blez s2,80005944 -80005798: 0084a583 lw a1,8(s1) -8000579c: 0144d783 lhu a5,20(s1) -800057a0: 08f00813 li a6,143 -800057a4: 00159613 slli a2,a1,0x1 -800057a8: 00c40633 add a2,s0,a2 -800057ac: 00065703 lhu a4,0(a2) -800057b0: 00f776b3 and a3,a4,a5 -800057b4: 02a84a63 blt a6,a0,800057e8 -800057b8: 00b00813 li a6,11 -800057bc: 02b84663 blt a6,a1,800057e8 -800057c0: 00060793 mv a5,a2 -800057c4: 01840593 addi a1,s0,24 -800057c8: 0027d703 lhu a4,2(a5) -800057cc: 00070463 beqz a4,800057d4 -800057d0: 0016e693 ori a3,a3,1 -800057d4: 00079123 sh zero,2(a5) -800057d8: 00278793 addi a5,a5,2 -800057dc: fef596e3 bne a1,a5,800057c8 -800057e0: 00065703 lhu a4,0(a2) -800057e4: 0144d783 lhu a5,20(s1) -800057e8: fff7c793 not a5,a5 -800057ec: 00e7f7b3 and a5,a5,a4 -800057f0: 00f61023 sh a5,0(a2) -800057f4: 0164d783 lhu a5,22(s1) -800057f8: 00d7f733 and a4,a5,a3 -800057fc: 04070063 beqz a4,8000583c -80005800: 1ad78463 beq a5,a3,800059a8 -80005804: 03248613 addi a2,s1,50 -80005808: 01840693 addi a3,s0,24 -8000580c: 01c48493 addi s1,s1,28 -80005810: 00000713 li a4,0 -80005814: 00065783 lhu a5,0(a2) -80005818: 0006d583 lhu a1,0(a3) -8000581c: ffe68693 addi a3,a3,-2 -80005820: ffe60613 addi a2,a2,-2 -80005824: 00b787b3 add a5,a5,a1 -80005828: 00e787b3 add a5,a5,a4 -8000582c: 0107d713 srli a4,a5,0x10 -80005830: 00f69123 sh a5,2(a3) -80005834: 00177713 andi a4,a4,1 -80005838: fc961ee3 bne a2,s1,80005814 -8000583c: 19205863 blez s2,800059cc -80005840: 00445783 lhu a5,4(s0) -80005844: 12079e63 bnez a5,80005980 -80005848: 000087b7 lui a5,0x8 -8000584c: 00041c23 sh zero,24(s0) -80005850: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -80005854: 0927c863 blt a5,s2,800058e4 -80005858: 01241123 sh s2,2(s0) -8000585c: 01c12083 lw ra,28(sp) -80005860: 01812403 lw s0,24(sp) -80005864: 01412483 lw s1,20(sp) -80005868: 01012903 lw s2,16(sp) -8000586c: 00c12983 lw s3,12(sp) -80005870: 00812a03 lw s4,8(sp) -80005874: 00412a83 lw s5,4(sp) -80005878: 02010113 addi sp,sp,32 -8000587c: 00008067 ret -80005880: 0e095463 bgez s2,80005968 -80005884: f7000793 li a5,-144 -80005888: 08f95c63 bge s2,a5,80005920 -8000588c: 00240793 addi a5,s0,2 -80005890: 01a40413 addi s0,s0,26 -80005894: 00278793 addi a5,a5,2 -80005898: fe079f23 sh zero,-2(a5) -8000589c: fe879ce3 bne a5,s0,80005894 -800058a0: fbdff06f j 8000585c -800058a4: 01800793 li a5,24 -800058a8: 16f50863 beq a0,a5,80005a18 -800058ac: 03500793 li a5,53 -800058b0: 1ef51a63 bne a0,a5,80005aa4 -800058b4: 00001737 lui a4,0x1 -800058b8: 040007b7 lui a5,0x4000 -800058bc: 00600693 li a3,6 -800058c0: 7ff78793 addi a5,a5,2047 # 40007ff <_start-0x7bfff801> -800058c4: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> -800058c8: 00f4aa23 sw a5,20(s1) -800058cc: 00d4a423 sw a3,8(s1) -800058d0: 00e49c23 sh a4,24(s1) -800058d4: 00d4a623 sw a3,12(s1) -800058d8: 00600793 li a5,6 -800058dc: ea5ff06f j 80005780 +80005614 : +80005614: fe010113 addi sp,sp,-32 +80005618: 00812c23 sw s0,24(sp) +8000561c: 00912a23 sw s1,20(sp) +80005620: 01212823 sw s2,16(sp) +80005624: 01312623 sw s3,12(sp) +80005628: 01412423 sw s4,8(sp) +8000562c: 01512223 sw s5,4(sp) +80005630: 00068913 mv s2,a3 +80005634: 00078493 mv s1,a5 +80005638: 00112e23 sw ra,28(sp) +8000563c: 00050413 mv s0,a0 +80005640: 00058993 mv s3,a1 +80005644: 00060a13 mv s4,a2 +80005648: 00070a93 mv s5,a4 +8000564c: e4dff0ef jal ra,80005498 +80005650: 09000793 li a5,144 +80005654: 40a90933 sub s2,s2,a0 +80005658: 16a7dc63 bge a5,a0,800057d0 +8000565c: 000087b7 lui a5,0x8 +80005660: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> +80005664: 1f27da63 bge a5,s2,80005858 +80005668: 1c0a8463 beqz s5,80005830 +8000566c: 0044a503 lw a0,4(s1) +80005670: 0004a783 lw a5,0(s1) +80005674: 06f50a63 beq a0,a5,800056e8 +80005678: 01a48713 addi a4,s1,26 +8000567c: 03448793 addi a5,s1,52 +80005680: 00270713 addi a4,a4,2 +80005684: fe071f23 sh zero,-2(a4) +80005688: fef71ce3 bne a4,a5,80005680 +8000568c: 03800793 li a5,56 +80005690: 32f50c63 beq a0,a5,800059c8 +80005694: 16a7d063 bge a5,a0,800057f4 +80005698: 04000793 li a5,64 +8000569c: 2ef50c63 beq a0,a5,80005994 +800056a0: 07100793 li a5,113 +800056a4: 34f51863 bne a0,a5,800059f4 +800056a8: 400087b7 lui a5,0x40008 +800056ac: fff78793 addi a5,a5,-1 # 40007fff <_start-0x3fff8001> +800056b0: 00a00713 li a4,10 +800056b4: 00f4aa23 sw a5,20(s1) +800056b8: ffff87b7 lui a5,0xffff8 +800056bc: 00e4a423 sw a4,8(s1) +800056c0: 00f49c23 sh a5,24(s1) +800056c4: 00e4a623 sw a4,12(s1) +800056c8: 00a00793 li a5,10 +800056cc: 00008737 lui a4,0x8 +800056d0: 00878793 addi a5,a5,8 # ffff8008 <__BSS_END__+0x7ffe13cc> +800056d4: 00179793 slli a5,a5,0x1 +800056d8: 00f487b3 add a5,s1,a5 +800056dc: 00e79523 sh a4,10(a5) +800056e0: 00a4a023 sw a0,0(s1) +800056e4: 1b205863 blez s2,80005894 +800056e8: 0084a583 lw a1,8(s1) +800056ec: 0144d783 lhu a5,20(s1) +800056f0: 08f00813 li a6,143 +800056f4: 00159613 slli a2,a1,0x1 +800056f8: 00c40633 add a2,s0,a2 +800056fc: 00065703 lhu a4,0(a2) +80005700: 00f776b3 and a3,a4,a5 +80005704: 02a84a63 blt a6,a0,80005738 +80005708: 00b00813 li a6,11 +8000570c: 02b84663 blt a6,a1,80005738 +80005710: 00060793 mv a5,a2 +80005714: 01840593 addi a1,s0,24 +80005718: 0027d703 lhu a4,2(a5) +8000571c: 00070463 beqz a4,80005724 +80005720: 0016e693 ori a3,a3,1 +80005724: 00079123 sh zero,2(a5) +80005728: 00278793 addi a5,a5,2 +8000572c: fef596e3 bne a1,a5,80005718 +80005730: 00065703 lhu a4,0(a2) +80005734: 0144d783 lhu a5,20(s1) +80005738: fff7c793 not a5,a5 +8000573c: 00e7f7b3 and a5,a5,a4 +80005740: 00f61023 sh a5,0(a2) +80005744: 0164d783 lhu a5,22(s1) +80005748: 00d7f733 and a4,a5,a3 +8000574c: 04070063 beqz a4,8000578c +80005750: 1ad78463 beq a5,a3,800058f8 +80005754: 03248613 addi a2,s1,50 +80005758: 01840693 addi a3,s0,24 +8000575c: 01c48493 addi s1,s1,28 +80005760: 00000713 li a4,0 +80005764: 00065783 lhu a5,0(a2) +80005768: 0006d583 lhu a1,0(a3) +8000576c: ffe68693 addi a3,a3,-2 +80005770: ffe60613 addi a2,a2,-2 +80005774: 00b787b3 add a5,a5,a1 +80005778: 00e787b3 add a5,a5,a4 +8000577c: 0107d713 srli a4,a5,0x10 +80005780: 00f69123 sh a5,2(a3) +80005784: 00177713 andi a4,a4,1 +80005788: fc961ee3 bne a2,s1,80005764 +8000578c: 19205863 blez s2,8000591c +80005790: 00445783 lhu a5,4(s0) +80005794: 12079e63 bnez a5,800058d0 +80005798: 000087b7 lui a5,0x8 +8000579c: 00041c23 sh zero,24(s0) +800057a0: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> +800057a4: 0927c863 blt a5,s2,80005834 +800057a8: 01241123 sh s2,2(s0) +800057ac: 01c12083 lw ra,28(sp) +800057b0: 01812403 lw s0,24(sp) +800057b4: 01412483 lw s1,20(sp) +800057b8: 01012903 lw s2,16(sp) +800057bc: 00c12983 lw s3,12(sp) +800057c0: 00812a03 lw s4,8(sp) +800057c4: 00412a83 lw s5,4(sp) +800057c8: 02010113 addi sp,sp,32 +800057cc: 00008067 ret +800057d0: 0e095463 bgez s2,800058b8 +800057d4: f7000793 li a5,-144 +800057d8: 08f95c63 bge s2,a5,80005870 +800057dc: 00240793 addi a5,s0,2 +800057e0: 01a40413 addi s0,s0,26 +800057e4: 00278793 addi a5,a5,2 +800057e8: fe079f23 sh zero,-2(a5) +800057ec: fe879ce3 bne a5,s0,800057e4 +800057f0: fbdff06f j 800057ac +800057f4: 01800793 li a5,24 +800057f8: 16f50863 beq a0,a5,80005968 +800057fc: 03500793 li a5,53 +80005800: 1ef51a63 bne a0,a5,800059f4 +80005804: 00001737 lui a4,0x1 +80005808: 040007b7 lui a5,0x4000 +8000580c: 00600693 li a3,6 +80005810: 7ff78793 addi a5,a5,2047 # 40007ff <_start-0x7bfff801> +80005814: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> +80005818: 00f4aa23 sw a5,20(s1) +8000581c: 00d4a423 sw a3,8(s1) +80005820: 00e49c23 sh a4,24(s1) +80005824: 00d4a623 sw a3,12(s1) +80005828: 00600793 li a5,6 +8000582c: ea5ff06f j 800056d0 +80005830: 00041c23 sh zero,24(s0) +80005834: ffff87b7 lui a5,0xffff8 +80005838: fff7c793 not a5,a5 +8000583c: 00f41123 sh a5,2(s0) +80005840: 00440793 addi a5,s0,4 +80005844: 01840413 addi s0,s0,24 +80005848: 00079023 sh zero,0(a5) # ffff8000 <__BSS_END__+0x7ffe13c4> +8000584c: 00278793 addi a5,a5,2 +80005850: fef41ce3 bne s0,a5,80005848 +80005854: f59ff06f j 800057ac +80005858: 00240793 addi a5,s0,2 +8000585c: 01a40413 addi s0,s0,26 +80005860: 00278793 addi a5,a5,2 +80005864: fe079f23 sh zero,-2(a5) +80005868: fe879ce3 bne a5,s0,80005860 +8000586c: f41ff06f j 800057ac +80005870: 00090593 mv a1,s2 +80005874: 00040513 mv a0,s0 +80005878: a05ff0ef jal ra,8000527c +8000587c: 00050463 beqz a0,80005884 +80005880: 00100993 li s3,1 +80005884: 0c0a8c63 beqz s5,8000595c +80005888: 0044a503 lw a0,4(s1) +8000588c: 0004a783 lw a5,0(s1) +80005890: def514e3 bne a0,a5,80005678 +80005894: 09000793 li a5,144 +80005898: 0af50463 beq a0,a5,80005940 +8000589c: 01845783 lhu a5,24(s0) +800058a0: 00040513 mv a0,s0 +800058a4: 0017f793 andi a5,a5,1 +800058a8: 00f9e9b3 or s3,s3,a5 +800058ac: d80ff0ef jal ra,80004e2c +800058b0: 0044a503 lw a0,4(s1) +800058b4: e35ff06f j 800056e8 +800058b8: ee0a80e3 beqz s5,80005798 +800058bc: 0044a503 lw a0,4(s1) +800058c0: 0004a783 lw a5,0(s1) +800058c4: daf51ae3 bne a0,a5,80005678 +800058c8: e32040e3 bgtz s2,800056e8 +800058cc: fc9ff06f j 80005894 +800058d0: 00040513 mv a0,s0 +800058d4: d58ff0ef jal ra,80004e2c +800058d8: 000087b7 lui a5,0x8 +800058dc: 00190913 addi s2,s2,1 800058e0: 00041c23 sh zero,24(s0) -800058e4: ffff87b7 lui a5,0xffff8 -800058e8: fff7c793 not a5,a5 -800058ec: 00f41123 sh a5,2(s0) -800058f0: 00440793 addi a5,s0,4 -800058f4: 01840413 addi s0,s0,24 -800058f8: 00079023 sh zero,0(a5) # ffff8000 <__BSS_END__+0x7ffe13d0> -800058fc: 00278793 addi a5,a5,2 -80005900: fef41ce3 bne s0,a5,800058f8 -80005904: f59ff06f j 8000585c -80005908: 00240793 addi a5,s0,2 -8000590c: 01a40413 addi s0,s0,26 -80005910: 00278793 addi a5,a5,2 -80005914: fe079f23 sh zero,-2(a5) -80005918: fe879ce3 bne a5,s0,80005910 -8000591c: f41ff06f j 8000585c -80005920: 00090593 mv a1,s2 +800058e4: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> +800058e8: f527c6e3 blt a5,s2,80005834 +800058ec: ea095ee3 bgez s2,800057a8 +800058f0: 00041123 sh zero,2(s0) +800058f4: eb9ff06f j 800057ac +800058f8: 0c099463 bnez s3,800059c0 +800058fc: 00c4a783 lw a5,12(s1) +80005900: 0184d703 lhu a4,24(s1) +80005904: 00179793 slli a5,a5,0x1 +80005908: 00f407b3 add a5,s0,a5 +8000590c: 0007d783 lhu a5,0(a5) +80005910: 00e7f7b3 and a5,a5,a4 +80005914: e40790e3 bnez a5,80005754 +80005918: e7204ce3 bgtz s2,80005790 +8000591c: 09000793 li a5,144 +80005920: 00f50663 beq a0,a5,8000592c 80005924: 00040513 mv a0,s0 -80005928: a05ff0ef jal ra,8000532c -8000592c: 00050463 beqz a0,80005934 -80005930: 00100993 li s3,1 -80005934: 0c0a8c63 beqz s5,80005a0c -80005938: 0044a503 lw a0,4(s1) -8000593c: 0004a783 lw a5,0(s1) -80005940: def514e3 bne a0,a5,80005728 -80005944: 09000793 li a5,144 -80005948: 0af50463 beq a0,a5,800059f0 -8000594c: 01845783 lhu a5,24(s0) -80005950: 00040513 mv a0,s0 -80005954: 0017f793 andi a5,a5,1 -80005958: 00f9e9b3 or s3,s3,a5 -8000595c: d80ff0ef jal ra,80004edc -80005960: 0044a503 lw a0,4(s1) -80005964: e35ff06f j 80005798 -80005968: ee0a80e3 beqz s5,80005848 -8000596c: 0044a503 lw a0,4(s1) -80005970: 0004a783 lw a5,0(s1) -80005974: daf51ae3 bne a0,a5,80005728 -80005978: e32040e3 bgtz s2,80005798 -8000597c: fc9ff06f j 80005944 -80005980: 00040513 mv a0,s0 -80005984: d58ff0ef jal ra,80004edc -80005988: 000087b7 lui a5,0x8 -8000598c: 00190913 addi s2,s2,1 -80005990: 00041c23 sh zero,24(s0) -80005994: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -80005998: f527c6e3 blt a5,s2,800058e4 -8000599c: ea095ee3 bgez s2,80005858 -800059a0: 00041123 sh zero,2(s0) -800059a4: eb9ff06f j 8000585c -800059a8: 0c099463 bnez s3,80005a70 -800059ac: 00c4a783 lw a5,12(s1) -800059b0: 0184d703 lhu a4,24(s1) -800059b4: 00179793 slli a5,a5,0x1 -800059b8: 00f407b3 add a5,s0,a5 -800059bc: 0007d783 lhu a5,0(a5) -800059c0: 00e7f7b3 and a5,a5,a4 -800059c4: e40790e3 bnez a5,80005804 -800059c8: e7204ce3 bgtz s2,80005840 -800059cc: 09000793 li a5,144 -800059d0: 00f50663 beq a0,a5,800059dc -800059d4: 00040513 mv a0,s0 -800059d8: d6cff0ef jal ra,80004f44 -800059dc: 00445783 lhu a5,4(s0) -800059e0: fa0790e3 bnez a5,80005980 -800059e4: 00041c23 sh zero,24(s0) -800059e8: fa094ce3 bltz s2,800059a0 -800059ec: e6dff06f j 80005858 -800059f0: 0084a603 lw a2,8(s1) -800059f4: 0144d783 lhu a5,20(s1) -800059f8: 00161613 slli a2,a2,0x1 -800059fc: 00c40633 add a2,s0,a2 -80005a00: 00065703 lhu a4,0(a2) -80005a04: 00e7f6b3 and a3,a5,a4 -80005a08: de1ff06f j 800057e8 -80005a0c: 00041c23 sh zero,24(s0) -80005a10: 00041123 sh zero,2(s0) -80005a14: e49ff06f j 8000585c -80005a18: 008007b7 lui a5,0x800 -80005a1c: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> -80005a20: 00400713 li a4,4 -80005a24: 00f4aa23 sw a5,20(s1) -80005a28: 10000793 li a5,256 -80005a2c: 00e4a423 sw a4,8(s1) -80005a30: 00f49c23 sh a5,24(s1) -80005a34: 00e4a623 sw a4,12(s1) -80005a38: 00400793 li a5,4 -80005a3c: 10000713 li a4,256 -80005a40: d41ff06f j 80005780 -80005a44: 00700793 li a5,7 -80005a48: 00f4a423 sw a5,8(s1) -80005a4c: 800107b7 lui a5,0x80010 -80005a50: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff93cf> -80005a54: 00f4aa23 sw a5,20(s1) -80005a58: 00100793 li a5,1 -80005a5c: 00f49c23 sh a5,24(s1) -80005a60: 00600793 li a5,6 -80005a64: 00f4a623 sw a5,12(s1) -80005a68: 00100713 li a4,1 -80005a6c: d15ff06f j 80005780 -80005a70: d80a0ae3 beqz s4,80005804 -80005a74: dc9ff06f j 8000583c -80005a78: 008007b7 lui a5,0x800 -80005a7c: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> -80005a80: 00600713 li a4,6 -80005a84: 00f4aa23 sw a5,20(s1) -80005a88: 10000793 li a5,256 -80005a8c: 00e4a423 sw a4,8(s1) -80005a90: 00f49c23 sh a5,24(s1) -80005a94: 00e4a623 sw a4,12(s1) -80005a98: 00600793 li a5,6 -80005a9c: 10000713 li a4,256 -80005aa0: ce1ff06f j 80005780 -80005aa4: 00c00793 li a5,12 -80005aa8: 00f4a423 sw a5,8(s1) -80005aac: 800107b7 lui a5,0x80010 -80005ab0: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff93cf> -80005ab4: 00f4aa23 sw a5,20(s1) -80005ab8: 00100793 li a5,1 -80005abc: 00f49c23 sh a5,24(s1) -80005ac0: 00b00793 li a5,11 -80005ac4: 00f4a623 sw a5,12(s1) -80005ac8: 00100713 li a4,1 -80005acc: cb5ff06f j 80005780 +80005928: d6cff0ef jal ra,80004e94 +8000592c: 00445783 lhu a5,4(s0) +80005930: fa0790e3 bnez a5,800058d0 +80005934: 00041c23 sh zero,24(s0) +80005938: fa094ce3 bltz s2,800058f0 +8000593c: e6dff06f j 800057a8 +80005940: 0084a603 lw a2,8(s1) +80005944: 0144d783 lhu a5,20(s1) +80005948: 00161613 slli a2,a2,0x1 +8000594c: 00c40633 add a2,s0,a2 +80005950: 00065703 lhu a4,0(a2) +80005954: 00e7f6b3 and a3,a5,a4 +80005958: de1ff06f j 80005738 +8000595c: 00041c23 sh zero,24(s0) +80005960: 00041123 sh zero,2(s0) +80005964: e49ff06f j 800057ac +80005968: 008007b7 lui a5,0x800 +8000596c: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> +80005970: 00400713 li a4,4 +80005974: 00f4aa23 sw a5,20(s1) +80005978: 10000793 li a5,256 +8000597c: 00e4a423 sw a4,8(s1) +80005980: 00f49c23 sh a5,24(s1) +80005984: 00e4a623 sw a4,12(s1) +80005988: 00400793 li a5,4 +8000598c: 10000713 li a4,256 +80005990: d41ff06f j 800056d0 +80005994: 00700793 li a5,7 +80005998: 00f4a423 sw a5,8(s1) +8000599c: 800107b7 lui a5,0x80010 +800059a0: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff93c3> +800059a4: 00f4aa23 sw a5,20(s1) +800059a8: 00100793 li a5,1 +800059ac: 00f49c23 sh a5,24(s1) +800059b0: 00600793 li a5,6 +800059b4: 00f4a623 sw a5,12(s1) +800059b8: 00100713 li a4,1 +800059bc: d15ff06f j 800056d0 +800059c0: d80a0ae3 beqz s4,80005754 +800059c4: dc9ff06f j 8000578c +800059c8: 008007b7 lui a5,0x800 +800059cc: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> +800059d0: 00600713 li a4,6 +800059d4: 00f4aa23 sw a5,20(s1) +800059d8: 10000793 li a5,256 +800059dc: 00e4a423 sw a4,8(s1) +800059e0: 00f49c23 sh a5,24(s1) +800059e4: 00e4a623 sw a4,12(s1) +800059e8: 00600793 li a5,6 +800059ec: 10000713 li a4,256 +800059f0: ce1ff06f j 800056d0 +800059f4: 00c00793 li a5,12 +800059f8: 00f4a423 sw a5,8(s1) +800059fc: 800107b7 lui a5,0x80010 +80005a00: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff93c3> +80005a04: 00f4aa23 sw a5,20(s1) +80005a08: 00100793 li a5,1 +80005a0c: 00f49c23 sh a5,24(s1) +80005a10: 00b00793 li a5,11 +80005a14: 00f4a623 sw a5,12(s1) +80005a18: 00100713 li a4,1 +80005a1c: cb5ff06f j 800056d0 -80005ad0 : -80005ad0: fd010113 addi sp,sp,-48 -80005ad4: 02912223 sw s1,36(sp) -80005ad8: 01312e23 sw s3,28(sp) -80005adc: 00058493 mv s1,a1 -80005ae0: 00255983 lhu s3,2(a0) -80005ae4: 02112623 sw ra,44(sp) -80005ae8: 02812423 sw s0,40(sp) -80005aec: 03212023 sw s2,32(sp) -80005af0: 01412c23 sw s4,24(sp) -80005af4: 00060913 mv s2,a2 -80005af8: 01512a23 sw s5,20(sp) -80005afc: 01612823 sw s6,16(sp) -80005b00: 01712623 sw s7,12(sp) -80005b04: 01812423 sw s8,8(sp) -80005b08: 01912223 sw s9,4(sp) -80005b0c: 01a12023 sw s10,0(sp) -80005b10: 00050a13 mv s4,a0 -80005b14: a35ff0ef jal ra,80005548 -80005b18: 0024d403 lhu s0,2(s1) -80005b1c: 00050793 mv a5,a0 -80005b20: 00048513 mv a0,s1 -80005b24: 40f989b3 sub s3,s3,a5 -80005b28: 03490a93 addi s5,s2,52 -80005b2c: a1dff0ef jal ra,80005548 -80005b30: 40a40433 sub s0,s0,a0 -80005b34: 04e90713 addi a4,s2,78 -80005b38: 000a8793 mv a5,s5 -80005b3c: 00278793 addi a5,a5,2 -80005b40: fe079f23 sh zero,-2(a5) -80005b44: fee79ce3 bne a5,a4,80005b3c -80005b48: 09344a63 blt s0,s3,80005bdc -80005b4c: 004a0b93 addi s7,s4,4 -80005b50: 00448b13 addi s6,s1,4 -80005b54: fff98993 addi s3,s3,-1 -80005b58: 01aa0c93 addi s9,s4,26 -80005b5c: 00248c13 addi s8,s1,2 -80005b60: 000b0713 mv a4,s6 -80005b64: 000b8793 mv a5,s7 -80005b68: 0007d603 lhu a2,0(a5) -80005b6c: 00075683 lhu a3,0(a4) -80005b70: 00278793 addi a5,a5,2 -80005b74: 00270713 addi a4,a4,2 -80005b78: 0ad61a63 bne a2,a3,80005c2c -80005b7c: ff9796e3 bne a5,s9,80005b68 -80005b80: 018a0613 addi a2,s4,24 -80005b84: 01848713 addi a4,s1,24 -80005b88: 00000693 li a3,0 -80005b8c: 00075783 lhu a5,0(a4) -80005b90: 00065583 lhu a1,0(a2) -80005b94: ffe70713 addi a4,a4,-2 -80005b98: 40d787b3 sub a5,a5,a3 -80005b9c: 40b787b3 sub a5,a5,a1 -80005ba0: 0107d693 srli a3,a5,0x10 -80005ba4: 00f71123 sh a5,2(a4) -80005ba8: 0016f693 andi a3,a3,1 -80005bac: ffe60613 addi a2,a2,-2 -80005bb0: fcec1ee3 bne s8,a4,80005b8c -80005bb4: 00100d13 li s10,1 -80005bb8: 000a8513 mv a0,s5 -80005bbc: b88ff0ef jal ra,80004f44 -80005bc0: 04c95783 lhu a5,76(s2) -80005bc4: fff40413 addi s0,s0,-1 -80005bc8: 00048513 mv a0,s1 -80005bcc: 00fd6d33 or s10,s10,a5 -80005bd0: 05a91623 sh s10,76(s2) -80005bd4: b70ff0ef jal ra,80004f44 -80005bd8: f93414e3 bne s0,s3,80005b60 -80005bdc: 00040693 mv a3,s0 -80005be0: 02812403 lw s0,40(sp) -80005be4: 02c12083 lw ra,44(sp) -80005be8: 01c12983 lw s3,28(sp) -80005bec: 01812a03 lw s4,24(sp) -80005bf0: 01412a83 lw s5,20(sp) -80005bf4: 01012b03 lw s6,16(sp) -80005bf8: 00c12b83 lw s7,12(sp) -80005bfc: 00812c03 lw s8,8(sp) -80005c00: 00412c83 lw s9,4(sp) -80005c04: 00012d03 lw s10,0(sp) -80005c08: 00090793 mv a5,s2 -80005c0c: 00048513 mv a0,s1 -80005c10: 02012903 lw s2,32(sp) -80005c14: 02412483 lw s1,36(sp) -80005c18: 00000713 li a4,0 -80005c1c: 00000613 li a2,0 -80005c20: 00000593 li a1,0 -80005c24: 03010113 addi sp,sp,48 -80005c28: a9dff06f j 800056c4 -80005c2c: 00000d13 li s10,0 -80005c30: f8c6e4e3 bltu a3,a2,80005bb8 -80005c34: f4dff06f j 80005b80 +80005a20 : +80005a20: fd010113 addi sp,sp,-48 +80005a24: 02912223 sw s1,36(sp) +80005a28: 01312e23 sw s3,28(sp) +80005a2c: 00058493 mv s1,a1 +80005a30: 00255983 lhu s3,2(a0) +80005a34: 02112623 sw ra,44(sp) +80005a38: 02812423 sw s0,40(sp) +80005a3c: 03212023 sw s2,32(sp) +80005a40: 01412c23 sw s4,24(sp) +80005a44: 00060913 mv s2,a2 +80005a48: 01512a23 sw s5,20(sp) +80005a4c: 01612823 sw s6,16(sp) +80005a50: 01712623 sw s7,12(sp) +80005a54: 01812423 sw s8,8(sp) +80005a58: 01912223 sw s9,4(sp) +80005a5c: 01a12023 sw s10,0(sp) +80005a60: 00050a13 mv s4,a0 +80005a64: a35ff0ef jal ra,80005498 +80005a68: 0024d403 lhu s0,2(s1) +80005a6c: 00050793 mv a5,a0 +80005a70: 00048513 mv a0,s1 +80005a74: 40f989b3 sub s3,s3,a5 +80005a78: 03490a93 addi s5,s2,52 +80005a7c: a1dff0ef jal ra,80005498 +80005a80: 40a40433 sub s0,s0,a0 +80005a84: 04e90713 addi a4,s2,78 +80005a88: 000a8793 mv a5,s5 +80005a8c: 00278793 addi a5,a5,2 +80005a90: fe079f23 sh zero,-2(a5) +80005a94: fee79ce3 bne a5,a4,80005a8c +80005a98: 09344a63 blt s0,s3,80005b2c +80005a9c: 004a0b93 addi s7,s4,4 +80005aa0: 00448b13 addi s6,s1,4 +80005aa4: fff98993 addi s3,s3,-1 +80005aa8: 01aa0c93 addi s9,s4,26 +80005aac: 00248c13 addi s8,s1,2 +80005ab0: 000b0713 mv a4,s6 +80005ab4: 000b8793 mv a5,s7 +80005ab8: 0007d603 lhu a2,0(a5) +80005abc: 00075683 lhu a3,0(a4) +80005ac0: 00278793 addi a5,a5,2 +80005ac4: 00270713 addi a4,a4,2 +80005ac8: 0ad61a63 bne a2,a3,80005b7c +80005acc: ff9796e3 bne a5,s9,80005ab8 +80005ad0: 018a0613 addi a2,s4,24 +80005ad4: 01848713 addi a4,s1,24 +80005ad8: 00000693 li a3,0 +80005adc: 00075783 lhu a5,0(a4) +80005ae0: 00065583 lhu a1,0(a2) +80005ae4: ffe70713 addi a4,a4,-2 +80005ae8: 40d787b3 sub a5,a5,a3 +80005aec: 40b787b3 sub a5,a5,a1 +80005af0: 0107d693 srli a3,a5,0x10 +80005af4: 00f71123 sh a5,2(a4) +80005af8: 0016f693 andi a3,a3,1 +80005afc: ffe60613 addi a2,a2,-2 +80005b00: fcec1ee3 bne s8,a4,80005adc +80005b04: 00100d13 li s10,1 +80005b08: 000a8513 mv a0,s5 +80005b0c: b88ff0ef jal ra,80004e94 +80005b10: 04c95783 lhu a5,76(s2) +80005b14: fff40413 addi s0,s0,-1 +80005b18: 00048513 mv a0,s1 +80005b1c: 00fd6d33 or s10,s10,a5 +80005b20: 05a91623 sh s10,76(s2) +80005b24: b70ff0ef jal ra,80004e94 +80005b28: f93414e3 bne s0,s3,80005ab0 +80005b2c: 00040693 mv a3,s0 +80005b30: 02812403 lw s0,40(sp) +80005b34: 02c12083 lw ra,44(sp) +80005b38: 01c12983 lw s3,28(sp) +80005b3c: 01812a03 lw s4,24(sp) +80005b40: 01412a83 lw s5,20(sp) +80005b44: 01012b03 lw s6,16(sp) +80005b48: 00c12b83 lw s7,12(sp) +80005b4c: 00812c03 lw s8,8(sp) +80005b50: 00412c83 lw s9,4(sp) +80005b54: 00012d03 lw s10,0(sp) +80005b58: 00090793 mv a5,s2 +80005b5c: 00048513 mv a0,s1 +80005b60: 02012903 lw s2,32(sp) +80005b64: 02412483 lw s1,36(sp) +80005b68: 00000713 li a4,0 +80005b6c: 00000613 li a2,0 +80005b70: 00000593 li a1,0 +80005b74: 03010113 addi sp,sp,48 +80005b78: a9dff06f j 80005614 +80005b7c: 00000d13 li s10,0 +80005b80: f8c6e4e3 bltu a3,a2,80005b08 +80005b84: f4dff06f j 80005ad0 -80005c38 : -80005c38: 00055703 lhu a4,0(a0) -80005c3c: 00255783 lhu a5,2(a0) -80005c40: 00070663 beqz a4,80005c4c -80005c44: 00008737 lui a4,0x8 -80005c48: 00e7e7b3 or a5,a5,a4 -80005c4c: 00f59923 sh a5,18(a1) -80005c50: 00255703 lhu a4,2(a0) -80005c54: 000087b7 lui a5,0x8 -80005c58: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005c5c: 02f70463 beq a4,a5,80005c84 -80005c60: 00650793 addi a5,a0,6 -80005c64: 01058593 addi a1,a1,16 -80005c68: 01850513 addi a0,a0,24 -80005c6c: 0007d703 lhu a4,0(a5) -80005c70: 00278793 addi a5,a5,2 -80005c74: ffe58593 addi a1,a1,-2 -80005c78: 00e59123 sh a4,2(a1) -80005c7c: fea798e3 bne a5,a0,80005c6c -80005c80: 00008067 ret -80005c84: 00650793 addi a5,a0,6 -80005c88: 01a50513 addi a0,a0,26 -80005c8c: 0007d703 lhu a4,0(a5) -80005c90: 00278793 addi a5,a5,2 -80005c94: 02071a63 bnez a4,80005cc8 -80005c98: fea79ae3 bne a5,a0,80005c8c -80005c9c: 01258713 addi a4,a1,18 -80005ca0: 00058793 mv a5,a1 -80005ca4: 00278793 addi a5,a5,2 -80005ca8: fe079f23 sh zero,-2(a5) -80005cac: fef71ce3 bne a4,a5,80005ca4 -80005cb0: 0125d783 lhu a5,18(a1) -80005cb4: 00008737 lui a4,0x8 -80005cb8: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80005cbc: 00e7e7b3 or a5,a5,a4 -80005cc0: 00f59923 sh a5,18(a1) -80005cc4: 00008067 ret -80005cc8: 01058713 addi a4,a1,16 -80005ccc: 00058793 mv a5,a1 -80005cd0: 00278793 addi a5,a5,2 -80005cd4: fe079f23 sh zero,-2(a5) -80005cd8: fef71ce3 bne a4,a5,80005cd0 -80005cdc: 7fffc7b7 lui a5,0x7fffc -80005ce0: 00f5a823 sw a5,16(a1) -80005ce4: 00008067 ret +80005b88 : +80005b88: 00055703 lhu a4,0(a0) +80005b8c: 00255783 lhu a5,2(a0) +80005b90: 00070663 beqz a4,80005b9c +80005b94: 00008737 lui a4,0x8 +80005b98: 00e7e7b3 or a5,a5,a4 +80005b9c: 00f59923 sh a5,18(a1) +80005ba0: 00255703 lhu a4,2(a0) +80005ba4: 000087b7 lui a5,0x8 +80005ba8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80005bac: 02f70463 beq a4,a5,80005bd4 +80005bb0: 00650793 addi a5,a0,6 +80005bb4: 01058593 addi a1,a1,16 +80005bb8: 01850513 addi a0,a0,24 +80005bbc: 0007d703 lhu a4,0(a5) +80005bc0: 00278793 addi a5,a5,2 +80005bc4: ffe58593 addi a1,a1,-2 +80005bc8: 00e59123 sh a4,2(a1) +80005bcc: fea798e3 bne a5,a0,80005bbc +80005bd0: 00008067 ret +80005bd4: 00650793 addi a5,a0,6 +80005bd8: 01a50513 addi a0,a0,26 +80005bdc: 0007d703 lhu a4,0(a5) +80005be0: 00278793 addi a5,a5,2 +80005be4: 02071a63 bnez a4,80005c18 +80005be8: fea79ae3 bne a5,a0,80005bdc +80005bec: 01258713 addi a4,a1,18 +80005bf0: 00058793 mv a5,a1 +80005bf4: 00278793 addi a5,a5,2 +80005bf8: fe079f23 sh zero,-2(a5) +80005bfc: fef71ce3 bne a4,a5,80005bf4 +80005c00: 0125d783 lhu a5,18(a1) +80005c04: 00008737 lui a4,0x8 +80005c08: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80005c0c: 00e7e7b3 or a5,a5,a4 +80005c10: 00f59923 sh a5,18(a1) +80005c14: 00008067 ret +80005c18: 01058713 addi a4,a1,16 +80005c1c: 00058793 mv a5,a1 +80005c20: 00278793 addi a5,a5,2 +80005c24: fe079f23 sh zero,-2(a5) +80005c28: fef71ce3 bne a4,a5,80005c20 +80005c2c: 7fffc7b7 lui a5,0x7fffc +80005c30: 00f5a823 sw a5,16(a1) +80005c34: 00008067 ret -80005ce8 : -80005ce8: f7010113 addi sp,sp,-144 -80005cec: 07612823 sw s6,112(sp) -80005cf0: 01255b03 lhu s6,18(a0) -80005cf4: 000087b7 lui a5,0x8 -80005cf8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005cfc: 07412c23 sw s4,120(sp) -80005d00: 0167fa33 and s4,a5,s6 -80005d04: 010a1a13 slli s4,s4,0x10 -80005d08: 08812423 sw s0,136(sp) -80005d0c: 08912223 sw s1,132(sp) -80005d10: 09212023 sw s2,128(sp) -80005d14: 07312e23 sw s3,124(sp) -80005d18: 08112623 sw ra,140(sp) -80005d1c: 07512a23 sw s5,116(sp) -80005d20: 07712623 sw s7,108(sp) -80005d24: 07812423 sw s8,104(sp) -80005d28: 07912223 sw s9,100(sp) -80005d2c: 010a5a13 srli s4,s4,0x10 -80005d30: 00050493 mv s1,a0 -80005d34: 00058913 mv s2,a1 -80005d38: 00060413 mv s0,a2 -80005d3c: 00068993 mv s3,a3 -80005d40: 10fa1263 bne s4,a5,80005e44 -80005d44: b08ff0ef jal ra,8000504c -80005d48: 28051a63 bnez a0,80005fdc -80005d4c: 01295a83 lhu s5,18(s2) -80005d50: 015a77b3 and a5,s4,s5 -80005d54: 2b478263 beq a5,s4,80005ff8 -80005d58: 00048513 mv a0,s1 -80005d5c: db4ff0ef jal ra,80005310 -80005d60: 2e050e63 beqz a0,8000605c -80005d64: 800155b7 lui a1,0x80015 -80005d68: e1458593 addi a1,a1,-492 # 80014e14 <__BSS_END__+0xffffe1e4> -80005d6c: 00090513 mv a0,s2 -80005d70: c84ff0ef jal ra,800051f4 -80005d74: 36050663 beqz a0,800060e0 -80005d78: 01295a83 lhu s5,18(s2) -80005d7c: 000087b7 lui a5,0x8 -80005d80: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005d84: 0157fab3 and s5,a5,s5 -80005d88: 010a9a93 slli s5,s5,0x10 -80005d8c: 010ada93 srli s5,s5,0x10 -80005d90: 2cfa9463 bne s5,a5,80006058 -80005d94: 00090513 mv a0,s2 -80005d98: d78ff0ef jal ra,80005310 -80005d9c: 32051063 bnez a0,800060bc -80005da0: 0124d783 lhu a5,18(s1) -80005da4: 00faf7b3 and a5,s5,a5 -80005da8: 0b579863 bne a5,s5,80005e58 -80005dac: 00048513 mv a0,s1 -80005db0: d60ff0ef jal ra,80005310 -80005db4: 00051863 bnez a0,80005dc4 -80005db8: 00090513 mv a0,s2 -80005dbc: d54ff0ef jal ra,80005310 -80005dc0: 08050c63 beqz a0,80005e58 -80005dc4: 00048513 mv a0,s1 -80005dc8: af4ff0ef jal ra,800050bc -80005dcc: 00050493 mv s1,a0 -80005dd0: 00090513 mv a0,s2 -80005dd4: ae8ff0ef jal ra,800050bc -80005dd8: 40a484b3 sub s1,s1,a0 -80005ddc: 009034b3 snez s1,s1 -80005de0: 00f49493 slli s1,s1,0xf -80005de4: 00941923 sh s1,18(s0) -80005de8: 01240713 addi a4,s0,18 -80005dec: 00040793 mv a5,s0 -80005df0: 00278793 addi a5,a5,2 -80005df4: fe079f23 sh zero,-2(a5) -80005df8: fef71ce3 bne a4,a5,80005df0 -80005dfc: 01245783 lhu a5,18(s0) -80005e00: 00008737 lui a4,0x8 -80005e04: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80005e08: 00e7e7b3 or a5,a5,a4 -80005e0c: 00f41923 sh a5,18(s0) -80005e10: 08c12083 lw ra,140(sp) -80005e14: 08812403 lw s0,136(sp) -80005e18: 08412483 lw s1,132(sp) -80005e1c: 08012903 lw s2,128(sp) -80005e20: 07c12983 lw s3,124(sp) -80005e24: 07812a03 lw s4,120(sp) -80005e28: 07412a83 lw s5,116(sp) -80005e2c: 07012b03 lw s6,112(sp) -80005e30: 06c12b83 lw s7,108(sp) -80005e34: 06812c03 lw s8,104(sp) -80005e38: 06412c83 lw s9,100(sp) -80005e3c: 09010113 addi sp,sp,144 -80005e40: 00008067 ret -80005e44: 0125da83 lhu s5,18(a1) -80005e48: 0157f733 and a4,a5,s5 -80005e4c: 01071713 slli a4,a4,0x10 -80005e50: 01075713 srli a4,a4,0x10 -80005e54: 04f70a63 beq a4,a5,80005ea8 -80005e58: 00048513 mv a0,s1 -80005e5c: 00c10593 addi a1,sp,12 -80005e60: a9cff0ef jal ra,800050fc -80005e64: 00090513 mv a0,s2 -80005e68: 02810593 addi a1,sp,40 -80005e6c: a90ff0ef jal ra,800050fc -80005e70: 00e15483 lhu s1,14(sp) -80005e74: 02a15903 lhu s2,42(sp) -80005e78: 04049c63 bnez s1,80005ed0 -80005e7c: 01010793 addi a5,sp,16 -80005e80: 02410693 addi a3,sp,36 -80005e84: 20d78863 beq a5,a3,80006094 -80005e88: 0007d703 lhu a4,0(a5) -80005e8c: 00278793 addi a5,a5,2 -80005e90: fe070ae3 beqz a4,80005e84 -80005e94: 00c10513 addi a0,sp,12 -80005e98: eb0ff0ef jal ra,80005548 -80005e9c: 02a15703 lhu a4,42(sp) -80005ea0: 40a004b3 neg s1,a0 -80005ea4: 0300006f j 80005ed4 -80005ea8: 00058513 mv a0,a1 -80005eac: 9a0ff0ef jal ra,8000504c -80005eb0: ec0506e3 beqz a0,80005d7c -80005eb4: 01490713 addi a4,s2,20 -80005eb8: 00095783 lhu a5,0(s2) -80005ebc: 00290913 addi s2,s2,2 -80005ec0: 00240413 addi s0,s0,2 -80005ec4: fef41f23 sh a5,-2(s0) -80005ec8: fee918e3 bne s2,a4,80005eb8 -80005ecc: f45ff06f j 80005e10 -80005ed0: 00090713 mv a4,s2 -80005ed4: 00090a93 mv s5,s2 -80005ed8: 02c10793 addi a5,sp,44 -80005edc: 04010693 addi a3,sp,64 -80005ee0: 02071263 bnez a4,80005f04 -80005ee4: 1cf68263 beq a3,a5,800060a8 -80005ee8: 0007d703 lhu a4,0(a5) -80005eec: 00278793 addi a5,a5,2 -80005ef0: fe070ae3 beqz a4,80005ee4 -80005ef4: 02810513 addi a0,sp,40 -80005ef8: e50ff0ef jal ra,80005548 -80005efc: 02a15703 lhu a4,42(sp) -80005f00: 40a90ab3 sub s5,s2,a0 -80005f04: 02815783 lhu a5,40(sp) -80005f08: 03898c13 addi s8,s3,56 -80005f0c: 02e99b23 sh a4,54(s3) -80005f10: 02f99a23 sh a5,52(s3) -80005f14: 04e98713 addi a4,s3,78 -80005f18: 000c0793 mv a5,s8 -80005f1c: 00079023 sh zero,0(a5) -80005f20: 00278793 addi a5,a5,2 -80005f24: fef71ce3 bne a4,a5,80005f1c -80005f28: 04c98a13 addi s4,s3,76 -80005f2c: 00000b93 li s7,0 -80005f30: 02410913 addi s2,sp,36 -80005f34: 01010c93 addi s9,sp,16 -80005f38: 04610b13 addi s6,sp,70 -80005f3c: 00095503 lhu a0,0(s2) -80005f40: ffe90913 addi s2,s2,-2 -80005f44: 0c051863 bnez a0,80006014 -80005f48: 04c9d703 lhu a4,76(s3) -80005f4c: 000a0793 mv a5,s4 -80005f50: 00ebebb3 or s7,s7,a4 -80005f54: ffe7d703 lhu a4,-2(a5) -80005f58: ffe78793 addi a5,a5,-2 -80005f5c: 00e79123 sh a4,2(a5) -80005f60: ff879ae3 bne a5,s8,80005f54 -80005f64: 02099c23 sh zero,56(s3) -80005f68: fd991ae3 bne s2,s9,80005f3c -80005f6c: 03498713 addi a4,s3,52 -80005f70: 02810793 addi a5,sp,40 -80005f74: 04210593 addi a1,sp,66 -80005f78: 00075603 lhu a2,0(a4) -80005f7c: 00278793 addi a5,a5,2 -80005f80: 00270713 addi a4,a4,2 -80005f84: fec79f23 sh a2,-2(a5) -80005f88: fef598e3 bne a1,a5,80005f78 -80005f8c: ffffc6b7 lui a3,0xffffc -80005f90: 015484b3 add s1,s1,s5 -80005f94: 00268693 addi a3,a3,2 # ffffc002 <__BSS_END__+0x7ffe53d2> -80005f98: 000b8593 mv a1,s7 -80005f9c: 02810513 addi a0,sp,40 -80005fa0: 00098793 mv a5,s3 -80005fa4: 04000713 li a4,64 -80005fa8: 00d486b3 add a3,s1,a3 -80005fac: 00000613 li a2,0 -80005fb0: f14ff0ef jal ra,800056c4 -80005fb4: 02815703 lhu a4,40(sp) -80005fb8: 00c15783 lhu a5,12(sp) -80005fbc: 00040593 mv a1,s0 -80005fc0: 02810513 addi a0,sp,40 -80005fc4: 40e787b3 sub a5,a5,a4 -80005fc8: 00f037b3 snez a5,a5 -80005fcc: 40f007b3 neg a5,a5 -80005fd0: 02f11423 sh a5,40(sp) -80005fd4: c65ff0ef jal ra,80005c38 -80005fd8: e39ff06f j 80005e10 -80005fdc: 01448713 addi a4,s1,20 -80005fe0: 0004d783 lhu a5,0(s1) -80005fe4: 00248493 addi s1,s1,2 +80005c38 : +80005c38: f7010113 addi sp,sp,-144 +80005c3c: 07612823 sw s6,112(sp) +80005c40: 01255b03 lhu s6,18(a0) +80005c44: 000087b7 lui a5,0x8 +80005c48: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80005c4c: 07412c23 sw s4,120(sp) +80005c50: 0167fa33 and s4,a5,s6 +80005c54: 010a1a13 slli s4,s4,0x10 +80005c58: 08812423 sw s0,136(sp) +80005c5c: 08912223 sw s1,132(sp) +80005c60: 09212023 sw s2,128(sp) +80005c64: 07312e23 sw s3,124(sp) +80005c68: 08112623 sw ra,140(sp) +80005c6c: 07512a23 sw s5,116(sp) +80005c70: 07712623 sw s7,108(sp) +80005c74: 07812423 sw s8,104(sp) +80005c78: 07912223 sw s9,100(sp) +80005c7c: 010a5a13 srli s4,s4,0x10 +80005c80: 00050493 mv s1,a0 +80005c84: 00058913 mv s2,a1 +80005c88: 00060413 mv s0,a2 +80005c8c: 00068993 mv s3,a3 +80005c90: 10fa1263 bne s4,a5,80005d94 +80005c94: b08ff0ef jal ra,80004f9c +80005c98: 28051a63 bnez a0,80005f2c +80005c9c: 01295a83 lhu s5,18(s2) +80005ca0: 015a77b3 and a5,s4,s5 +80005ca4: 2b478263 beq a5,s4,80005f48 +80005ca8: 00048513 mv a0,s1 +80005cac: db4ff0ef jal ra,80005260 +80005cb0: 2e050e63 beqz a0,80005fac +80005cb4: 800155b7 lui a1,0x80015 +80005cb8: e6058593 addi a1,a1,-416 # 80014e60 <__BSS_END__+0xffffe224> +80005cbc: 00090513 mv a0,s2 +80005cc0: c84ff0ef jal ra,80005144 +80005cc4: 36050663 beqz a0,80006030 +80005cc8: 01295a83 lhu s5,18(s2) +80005ccc: 000087b7 lui a5,0x8 +80005cd0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80005cd4: 0157fab3 and s5,a5,s5 +80005cd8: 010a9a93 slli s5,s5,0x10 +80005cdc: 010ada93 srli s5,s5,0x10 +80005ce0: 2cfa9463 bne s5,a5,80005fa8 +80005ce4: 00090513 mv a0,s2 +80005ce8: d78ff0ef jal ra,80005260 +80005cec: 32051063 bnez a0,8000600c +80005cf0: 0124d783 lhu a5,18(s1) +80005cf4: 00faf7b3 and a5,s5,a5 +80005cf8: 0b579863 bne a5,s5,80005da8 +80005cfc: 00048513 mv a0,s1 +80005d00: d60ff0ef jal ra,80005260 +80005d04: 00051863 bnez a0,80005d14 +80005d08: 00090513 mv a0,s2 +80005d0c: d54ff0ef jal ra,80005260 +80005d10: 08050c63 beqz a0,80005da8 +80005d14: 00048513 mv a0,s1 +80005d18: af4ff0ef jal ra,8000500c +80005d1c: 00050493 mv s1,a0 +80005d20: 00090513 mv a0,s2 +80005d24: ae8ff0ef jal ra,8000500c +80005d28: 40a484b3 sub s1,s1,a0 +80005d2c: 009034b3 snez s1,s1 +80005d30: 00f49493 slli s1,s1,0xf +80005d34: 00941923 sh s1,18(s0) +80005d38: 01240713 addi a4,s0,18 +80005d3c: 00040793 mv a5,s0 +80005d40: 00278793 addi a5,a5,2 +80005d44: fe079f23 sh zero,-2(a5) +80005d48: fef71ce3 bne a4,a5,80005d40 +80005d4c: 01245783 lhu a5,18(s0) +80005d50: 00008737 lui a4,0x8 +80005d54: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80005d58: 00e7e7b3 or a5,a5,a4 +80005d5c: 00f41923 sh a5,18(s0) +80005d60: 08c12083 lw ra,140(sp) +80005d64: 08812403 lw s0,136(sp) +80005d68: 08412483 lw s1,132(sp) +80005d6c: 08012903 lw s2,128(sp) +80005d70: 07c12983 lw s3,124(sp) +80005d74: 07812a03 lw s4,120(sp) +80005d78: 07412a83 lw s5,116(sp) +80005d7c: 07012b03 lw s6,112(sp) +80005d80: 06c12b83 lw s7,108(sp) +80005d84: 06812c03 lw s8,104(sp) +80005d88: 06412c83 lw s9,100(sp) +80005d8c: 09010113 addi sp,sp,144 +80005d90: 00008067 ret +80005d94: 0125da83 lhu s5,18(a1) +80005d98: 0157f733 and a4,a5,s5 +80005d9c: 01071713 slli a4,a4,0x10 +80005da0: 01075713 srli a4,a4,0x10 +80005da4: 04f70a63 beq a4,a5,80005df8 +80005da8: 00048513 mv a0,s1 +80005dac: 00c10593 addi a1,sp,12 +80005db0: a9cff0ef jal ra,8000504c +80005db4: 00090513 mv a0,s2 +80005db8: 02810593 addi a1,sp,40 +80005dbc: a90ff0ef jal ra,8000504c +80005dc0: 00e15483 lhu s1,14(sp) +80005dc4: 02a15903 lhu s2,42(sp) +80005dc8: 04049c63 bnez s1,80005e20 +80005dcc: 01010793 addi a5,sp,16 +80005dd0: 02410693 addi a3,sp,36 +80005dd4: 20d78863 beq a5,a3,80005fe4 +80005dd8: 0007d703 lhu a4,0(a5) +80005ddc: 00278793 addi a5,a5,2 +80005de0: fe070ae3 beqz a4,80005dd4 +80005de4: 00c10513 addi a0,sp,12 +80005de8: eb0ff0ef jal ra,80005498 +80005dec: 02a15703 lhu a4,42(sp) +80005df0: 40a004b3 neg s1,a0 +80005df4: 0300006f j 80005e24 +80005df8: 00058513 mv a0,a1 +80005dfc: 9a0ff0ef jal ra,80004f9c +80005e00: ec0506e3 beqz a0,80005ccc +80005e04: 01490713 addi a4,s2,20 +80005e08: 00095783 lhu a5,0(s2) +80005e0c: 00290913 addi s2,s2,2 +80005e10: 00240413 addi s0,s0,2 +80005e14: fef41f23 sh a5,-2(s0) +80005e18: fee918e3 bne s2,a4,80005e08 +80005e1c: f45ff06f j 80005d60 +80005e20: 00090713 mv a4,s2 +80005e24: 00090a93 mv s5,s2 +80005e28: 02c10793 addi a5,sp,44 +80005e2c: 04010693 addi a3,sp,64 +80005e30: 02071263 bnez a4,80005e54 +80005e34: 1cf68263 beq a3,a5,80005ff8 +80005e38: 0007d703 lhu a4,0(a5) +80005e3c: 00278793 addi a5,a5,2 +80005e40: fe070ae3 beqz a4,80005e34 +80005e44: 02810513 addi a0,sp,40 +80005e48: e50ff0ef jal ra,80005498 +80005e4c: 02a15703 lhu a4,42(sp) +80005e50: 40a90ab3 sub s5,s2,a0 +80005e54: 02815783 lhu a5,40(sp) +80005e58: 03898c13 addi s8,s3,56 +80005e5c: 02e99b23 sh a4,54(s3) +80005e60: 02f99a23 sh a5,52(s3) +80005e64: 04e98713 addi a4,s3,78 +80005e68: 000c0793 mv a5,s8 +80005e6c: 00079023 sh zero,0(a5) +80005e70: 00278793 addi a5,a5,2 +80005e74: fef71ce3 bne a4,a5,80005e6c +80005e78: 04c98a13 addi s4,s3,76 +80005e7c: 00000b93 li s7,0 +80005e80: 02410913 addi s2,sp,36 +80005e84: 01010c93 addi s9,sp,16 +80005e88: 04610b13 addi s6,sp,70 +80005e8c: 00095503 lhu a0,0(s2) +80005e90: ffe90913 addi s2,s2,-2 +80005e94: 0c051863 bnez a0,80005f64 +80005e98: 04c9d703 lhu a4,76(s3) +80005e9c: 000a0793 mv a5,s4 +80005ea0: 00ebebb3 or s7,s7,a4 +80005ea4: ffe7d703 lhu a4,-2(a5) +80005ea8: ffe78793 addi a5,a5,-2 +80005eac: 00e79123 sh a4,2(a5) +80005eb0: ff879ae3 bne a5,s8,80005ea4 +80005eb4: 02099c23 sh zero,56(s3) +80005eb8: fd991ae3 bne s2,s9,80005e8c +80005ebc: 03498713 addi a4,s3,52 +80005ec0: 02810793 addi a5,sp,40 +80005ec4: 04210593 addi a1,sp,66 +80005ec8: 00075603 lhu a2,0(a4) +80005ecc: 00278793 addi a5,a5,2 +80005ed0: 00270713 addi a4,a4,2 +80005ed4: fec79f23 sh a2,-2(a5) +80005ed8: fef598e3 bne a1,a5,80005ec8 +80005edc: ffffc6b7 lui a3,0xffffc +80005ee0: 015484b3 add s1,s1,s5 +80005ee4: 00268693 addi a3,a3,2 # ffffc002 <__BSS_END__+0x7ffe53c6> +80005ee8: 000b8593 mv a1,s7 +80005eec: 02810513 addi a0,sp,40 +80005ef0: 00098793 mv a5,s3 +80005ef4: 04000713 li a4,64 +80005ef8: 00d486b3 add a3,s1,a3 +80005efc: 00000613 li a2,0 +80005f00: f14ff0ef jal ra,80005614 +80005f04: 02815703 lhu a4,40(sp) +80005f08: 00c15783 lhu a5,12(sp) +80005f0c: 00040593 mv a1,s0 +80005f10: 02810513 addi a0,sp,40 +80005f14: 40e787b3 sub a5,a5,a4 +80005f18: 00f037b3 snez a5,a5 +80005f1c: 40f007b3 neg a5,a5 +80005f20: 02f11423 sh a5,40(sp) +80005f24: c65ff0ef jal ra,80005b88 +80005f28: e39ff06f j 80005d60 +80005f2c: 01448713 addi a4,s1,20 +80005f30: 0004d783 lhu a5,0(s1) +80005f34: 00248493 addi s1,s1,2 +80005f38: 00240413 addi s0,s0,2 +80005f3c: fef41f23 sh a5,-2(s0) +80005f40: fee498e3 bne s1,a4,80005f30 +80005f44: e1dff06f j 80005d60 +80005f48: 00090513 mv a0,s2 +80005f4c: 850ff0ef jal ra,80004f9c +80005f50: ea051ae3 bnez a0,80005e04 +80005f54: 00048513 mv a0,s1 +80005f58: b08ff0ef jal ra,80005260 +80005f5c: d60508e3 beqz a0,80005ccc +80005f60: d55ff06f j 80005cb4 +80005f64: 04410613 addi a2,sp,68 +80005f68: 02810593 addi a1,sp,40 +80005f6c: f99fe0ef jal ra,80004f04 +80005f70: 000a0593 mv a1,s4 +80005f74: 00000613 li a2,0 +80005f78: 05c10713 addi a4,sp,92 +80005f7c: 0005d803 lhu a6,0(a1) +80005f80: 00075783 lhu a5,0(a4) +80005f84: ffe58593 addi a1,a1,-2 +80005f88: ffe70713 addi a4,a4,-2 +80005f8c: 010787b3 add a5,a5,a6 +80005f90: 00c787b3 add a5,a5,a2 +80005f94: 0107d613 srli a2,a5,0x10 +80005f98: 00f59123 sh a5,2(a1) +80005f9c: 00167613 andi a2,a2,1 +80005fa0: fd671ee3 bne a4,s6,80005f7c +80005fa4: ef5ff06f j 80005e98 +80005fa8: 0124db03 lhu s6,18(s1) +80005fac: 000087b7 lui a5,0x8 +80005fb0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80005fb4: 0167fb33 and s6,a5,s6 +80005fb8: 010b1b13 slli s6,s6,0x10 +80005fbc: 010b5b13 srli s6,s6,0x10 +80005fc0: defb14e3 bne s6,a5,80005da8 +80005fc4: 00048513 mv a0,s1 +80005fc8: a98ff0ef jal ra,80005260 +80005fcc: d40514e3 bnez a0,80005d14 +80005fd0: 01295783 lhu a5,18(s2) +80005fd4: fff7c793 not a5,a5 +80005fd8: 01179713 slli a4,a5,0x11 +80005fdc: dc0716e3 bnez a4,80005da8 +80005fe0: d29ff06f j 80005d08 +80005fe4: 01440793 addi a5,s0,20 80005fe8: 00240413 addi s0,s0,2 -80005fec: fef41f23 sh a5,-2(s0) -80005ff0: fee498e3 bne s1,a4,80005fe0 -80005ff4: e1dff06f j 80005e10 -80005ff8: 00090513 mv a0,s2 -80005ffc: 850ff0ef jal ra,8000504c -80006000: ea051ae3 bnez a0,80005eb4 -80006004: 00048513 mv a0,s1 -80006008: b08ff0ef jal ra,80005310 -8000600c: d60508e3 beqz a0,80005d7c -80006010: d55ff06f j 80005d64 -80006014: 04410613 addi a2,sp,68 -80006018: 02810593 addi a1,sp,40 -8000601c: f99fe0ef jal ra,80004fb4 -80006020: 000a0593 mv a1,s4 -80006024: 00000613 li a2,0 -80006028: 05c10713 addi a4,sp,92 -8000602c: 0005d803 lhu a6,0(a1) -80006030: 00075783 lhu a5,0(a4) -80006034: ffe58593 addi a1,a1,-2 -80006038: ffe70713 addi a4,a4,-2 -8000603c: 010787b3 add a5,a5,a6 -80006040: 00c787b3 add a5,a5,a2 -80006044: 0107d613 srli a2,a5,0x10 -80006048: 00f59123 sh a5,2(a1) -8000604c: 00167613 andi a2,a2,1 -80006050: fd671ee3 bne a4,s6,8000602c -80006054: ef5ff06f j 80005f48 -80006058: 0124db03 lhu s6,18(s1) -8000605c: 000087b7 lui a5,0x8 -80006060: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80006064: 0167fb33 and s6,a5,s6 -80006068: 010b1b13 slli s6,s6,0x10 -8000606c: 010b5b13 srli s6,s6,0x10 -80006070: defb14e3 bne s6,a5,80005e58 -80006074: 00048513 mv a0,s1 -80006078: a98ff0ef jal ra,80005310 -8000607c: d40514e3 bnez a0,80005dc4 -80006080: 01295783 lhu a5,18(s2) -80006084: fff7c793 not a5,a5 -80006088: 01179713 slli a4,a5,0x11 -8000608c: dc0716e3 bnez a4,80005e58 -80006090: d29ff06f j 80005db8 -80006094: 01440793 addi a5,s0,20 -80006098: 00240413 addi s0,s0,2 -8000609c: fe041f23 sh zero,-2(s0) -800060a0: fe879ce3 bne a5,s0,80006098 -800060a4: d6dff06f j 80005e10 -800060a8: 01440793 addi a5,s0,20 -800060ac: 00240413 addi s0,s0,2 -800060b0: fe041f23 sh zero,-2(s0) -800060b4: fef41ce3 bne s0,a5,800060ac -800060b8: d59ff06f j 80005e10 -800060bc: 800155b7 lui a1,0x80015 -800060c0: e1458593 addi a1,a1,-492 # 80014e14 <__BSS_END__+0xffffe1e4> -800060c4: 00048513 mv a0,s1 -800060c8: 92cff0ef jal ra,800051f4 -800060cc: 00050a63 beqz a0,800060e0 -800060d0: 0124d783 lhu a5,18(s1) -800060d4: 00faf7b3 and a5,s5,a5 -800060d8: f9578ee3 beq a5,s5,80006074 -800060dc: fa5ff06f j 80006080 -800060e0: 01040713 addi a4,s0,16 -800060e4: 00040793 mv a5,s0 -800060e8: 00278793 addi a5,a5,2 -800060ec: fe079f23 sh zero,-2(a5) -800060f0: fee79ce3 bne a5,a4,800060e8 -800060f4: 7fffc7b7 lui a5,0x7fffc -800060f8: 00f42823 sw a5,16(s0) -800060fc: d15ff06f j 80005e10 +80005fec: fe041f23 sh zero,-2(s0) +80005ff0: fe879ce3 bne a5,s0,80005fe8 +80005ff4: d6dff06f j 80005d60 +80005ff8: 01440793 addi a5,s0,20 +80005ffc: 00240413 addi s0,s0,2 +80006000: fe041f23 sh zero,-2(s0) +80006004: fef41ce3 bne s0,a5,80005ffc +80006008: d59ff06f j 80005d60 +8000600c: 800155b7 lui a1,0x80015 +80006010: e6058593 addi a1,a1,-416 # 80014e60 <__BSS_END__+0xffffe224> +80006014: 00048513 mv a0,s1 +80006018: 92cff0ef jal ra,80005144 +8000601c: 00050a63 beqz a0,80006030 +80006020: 0124d783 lhu a5,18(s1) +80006024: 00faf7b3 and a5,s5,a5 +80006028: f9578ee3 beq a5,s5,80005fc4 +8000602c: fa5ff06f j 80005fd0 +80006030: 01040713 addi a4,s0,16 +80006034: 00040793 mv a5,s0 +80006038: 00278793 addi a5,a5,2 +8000603c: fe079f23 sh zero,-2(a5) +80006040: fee79ce3 bne a5,a4,80006038 +80006044: 7fffc7b7 lui a5,0x7fffc +80006048: 00f42823 sw a5,16(s0) +8000604c: d15ff06f j 80005d60 -80006100 : -80006100: 01255783 lhu a5,18(a0) -80006104: f5010113 addi sp,sp,-176 -80006108: 0a812423 sw s0,168(sp) -8000610c: fff7c793 not a5,a5 -80006110: 0a912223 sw s1,164(sp) -80006114: 0b212023 sw s2,160(sp) -80006118: 09312e23 sw s3,156(sp) -8000611c: 0a112623 sw ra,172(sp) -80006120: 09412c23 sw s4,152(sp) -80006124: 09512a23 sw s5,148(sp) -80006128: 09612823 sw s6,144(sp) -8000612c: 09712623 sw s7,140(sp) -80006130: 09812423 sw s8,136(sp) -80006134: 09912223 sw s9,132(sp) -80006138: 09a12023 sw s10,128(sp) -8000613c: 07b12e23 sw s11,124(sp) -80006140: 01179713 slli a4,a5,0x11 -80006144: 00050913 mv s2,a0 -80006148: 00058993 mv s3,a1 -8000614c: 00060413 mv s0,a2 -80006150: 00068493 mv s1,a3 -80006154: 00071663 bnez a4,80006160 -80006158: ef5fe0ef jal ra,8000504c -8000615c: 38051863 bnez a0,800064ec -80006160: 0129d783 lhu a5,18(s3) -80006164: fff7c793 not a5,a5 -80006168: 01179713 slli a4,a5,0x11 -8000616c: 08070e63 beqz a4,80006208 -80006170: 80015a37 lui s4,0x80015 -80006174: e14a0593 addi a1,s4,-492 # 80014e14 <__BSS_END__+0xffffe1e4> -80006178: 00090513 mv a0,s2 -8000617c: 878ff0ef jal ra,800051f4 -80006180: 10050463 beqz a0,80006288 -80006184: 01295a03 lhu s4,18(s2) -80006188: 0129d703 lhu a4,18(s3) -8000618c: 000087b7 lui a5,0x8 -80006190: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80006194: 0147fa33 and s4,a5,s4 -80006198: 00e7fab3 and s5,a5,a4 -8000619c: 08fa1a63 bne s4,a5,80006230 -800061a0: 00090513 mv a0,s2 -800061a4: 96cff0ef jal ra,80005310 -800061a8: 10050863 beqz a0,800062b8 -800061ac: 014a9863 bne s5,s4,800061bc -800061b0: 00098513 mv a0,s3 -800061b4: 95cff0ef jal ra,80005310 -800061b8: 0e051063 bnez a0,80006298 -800061bc: 01440793 addi a5,s0,20 -800061c0: 00240413 addi s0,s0,2 -800061c4: fe041f23 sh zero,-2(s0) -800061c8: fef41ce3 bne s0,a5,800061c0 -800061cc: 0ac12083 lw ra,172(sp) -800061d0: 0a812403 lw s0,168(sp) -800061d4: 0a412483 lw s1,164(sp) -800061d8: 0a012903 lw s2,160(sp) -800061dc: 09c12983 lw s3,156(sp) -800061e0: 09812a03 lw s4,152(sp) -800061e4: 09412a83 lw s5,148(sp) -800061e8: 09012b03 lw s6,144(sp) -800061ec: 08c12b83 lw s7,140(sp) -800061f0: 08812c03 lw s8,136(sp) -800061f4: 08412c83 lw s9,132(sp) -800061f8: 08012d03 lw s10,128(sp) -800061fc: 07c12d83 lw s11,124(sp) -80006200: 0b010113 addi sp,sp,176 -80006204: 00008067 ret -80006208: 00098513 mv a0,s3 -8000620c: e41fe0ef jal ra,8000504c -80006210: f60500e3 beqz a0,80006170 -80006214: 01498713 addi a4,s3,20 -80006218: 0009d783 lhu a5,0(s3) -8000621c: 00298993 addi s3,s3,2 -80006220: 00240413 addi s0,s0,2 -80006224: fef41f23 sh a5,-2(s0) -80006228: fee998e3 bne s3,a4,80006218 -8000622c: fa1ff06f j 800061cc -80006230: 08fa8663 beq s5,a5,800062bc -80006234: 00090513 mv a0,s2 -80006238: 01c10593 addi a1,sp,28 -8000623c: ec1fe0ef jal ra,800050fc -80006240: 03810593 addi a1,sp,56 -80006244: 00098513 mv a0,s3 -80006248: eb5fe0ef jal ra,800050fc -8000624c: 03a15b83 lhu s7,58(sp) -80006250: 01e15903 lhu s2,30(sp) -80006254: 0c0b9263 bnez s7,80006318 -80006258: 03c10793 addi a5,sp,60 -8000625c: 05010d93 addi s11,sp,80 -80006260: 34fd8e63 beq s11,a5,800065bc -80006264: 0007d703 lhu a4,0(a5) -80006268: 00278793 addi a5,a5,2 -8000626c: fe070ae3 beqz a4,80006260 -80006270: 03810513 addi a0,sp,56 -80006274: ad4ff0ef jal ra,80005548 -80006278: 40a007b3 neg a5,a0 -8000627c: 01e15603 lhu a2,30(sp) -80006280: 00f12623 sw a5,12(sp) -80006284: 09c0006f j 80006320 -80006288: e14a0593 addi a1,s4,-492 -8000628c: 00098513 mv a0,s3 -80006290: f65fe0ef jal ra,800051f4 -80006294: ee0518e3 bnez a0,80006184 -80006298: 01040713 addi a4,s0,16 -8000629c: 00040793 mv a5,s0 -800062a0: 00278793 addi a5,a5,2 -800062a4: fe079f23 sh zero,-2(a5) -800062a8: fee79ce3 bne a5,a4,800062a0 -800062ac: 7fffc7b7 lui a5,0x7fffc -800062b0: 00f42823 sw a5,16(s0) -800062b4: f19ff06f j 800061cc -800062b8: f74a9ee3 bne s5,s4,80006234 -800062bc: 00098513 mv a0,s3 -800062c0: 850ff0ef jal ra,80005310 -800062c4: f60508e3 beqz a0,80006234 -800062c8: 00090513 mv a0,s2 -800062cc: df1fe0ef jal ra,800050bc -800062d0: 00050493 mv s1,a0 -800062d4: 00098513 mv a0,s3 -800062d8: de5fe0ef jal ra,800050bc -800062dc: 40a487b3 sub a5,s1,a0 -800062e0: 00f037b3 snez a5,a5 -800062e4: 00f79793 slli a5,a5,0xf -800062e8: 00f41923 sh a5,18(s0) -800062ec: 01240713 addi a4,s0,18 -800062f0: 00040793 mv a5,s0 -800062f4: 00278793 addi a5,a5,2 # 7fffc002 <_start-0x3ffe> -800062f8: fe079f23 sh zero,-2(a5) -800062fc: fee79ce3 bne a5,a4,800062f4 -80006300: 01245783 lhu a5,18(s0) -80006304: 00008737 lui a4,0x8 -80006308: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -8000630c: 00e7e7b3 or a5,a5,a4 -80006310: 00f41923 sh a5,18(s0) -80006314: eb9ff06f j 800061cc -80006318: 01712623 sw s7,12(sp) -8000631c: 00090613 mv a2,s2 -80006320: 01212423 sw s2,8(sp) -80006324: 02010793 addi a5,sp,32 -80006328: 03410693 addi a3,sp,52 -8000632c: 02061263 bnez a2,80006350 -80006330: 2af68063 beq a3,a5,800065d0 -80006334: 0007d703 lhu a4,0(a5) -80006338: 00278793 addi a5,a5,2 -8000633c: fe070ae3 beqz a4,80006330 -80006340: 01c10513 addi a0,sp,28 -80006344: a04ff0ef jal ra,80005548 -80006348: 40a907b3 sub a5,s2,a0 -8000634c: 00f12423 sw a5,8(sp) -80006350: 03812703 lw a4,56(sp) -80006354: 03848d13 addi s10,s1,56 -80006358: 000d0793 mv a5,s10 -8000635c: 02e4aa23 sw a4,52(s1) -80006360: 04e48913 addi s2,s1,78 -80006364: 00278793 addi a5,a5,2 -80006368: fe079f23 sh zero,-2(a5) -8000636c: fef91ce3 bne s2,a5,80006364 -80006370: 03810513 addi a0,sp,56 -80006374: b69fe0ef jal ra,80004edc -80006378: 02215c03 lhu s8,34(sp) -8000637c: 00010a37 lui s4,0x10 -80006380: 05010d93 addi s11,sp,80 -80006384: 010c1a93 slli s5,s8,0x10 -80006388: 418a8ab3 sub s5,s5,s8 -8000638c: 03a10b13 addi s6,sp,58 -80006390: fffa0a13 addi s4,s4,-1 # ffff <_start-0x7fff0001> -80006394: 06e10c93 addi s9,sp,110 -80006398: 05610993 addi s3,sp,86 -8000639c: 03c15783 lhu a5,60(sp) -800063a0: 03e15703 lhu a4,62(sp) -800063a4: 000a0b93 mv s7,s4 -800063a8: 01079793 slli a5,a5,0x10 -800063ac: 00e787b3 add a5,a5,a4 -800063b0: 00fae863 bltu s5,a5,800063c0 -800063b4: 0387d7b3 divu a5,a5,s8 -800063b8: 01079b93 slli s7,a5,0x10 -800063bc: 010bdb93 srli s7,s7,0x10 -800063c0: 05410613 addi a2,sp,84 -800063c4: 01c10593 addi a1,sp,28 -800063c8: 000b8513 mv a0,s7 -800063cc: be9fe0ef jal ra,80004fb4 -800063d0: 03c10713 addi a4,sp,60 -800063d4: 05810793 addi a5,sp,88 -800063d8: 0007d583 lhu a1,0(a5) -800063dc: 00075603 lhu a2,0(a4) -800063e0: 00278793 addi a5,a5,2 -800063e4: 00270713 addi a4,a4,2 -800063e8: 12c59063 bne a1,a2,80006508 -800063ec: ff9796e3 bne a5,s9,800063d8 -800063f0: 00000793 li a5,0 -800063f4: 06c10593 addi a1,sp,108 -800063f8: 000d8613 mv a2,s11 -800063fc: 00065703 lhu a4,0(a2) -80006400: 0005d803 lhu a6,0(a1) -80006404: ffe60613 addi a2,a2,-2 -80006408: 40f70733 sub a4,a4,a5 -8000640c: 41070733 sub a4,a4,a6 -80006410: 01075793 srli a5,a4,0x10 -80006414: 00e61123 sh a4,2(a2) -80006418: 0017f793 andi a5,a5,1 -8000641c: ffe58593 addi a1,a1,-2 -80006420: fd661ee3 bne a2,s6,800063fc -80006424: 017d1023 sh s7,0(s10) -80006428: 03c10793 addi a5,sp,60 -8000642c: 0027d703 lhu a4,2(a5) -80006430: 00278793 addi a5,a5,2 -80006434: fee79f23 sh a4,-2(a5) -80006438: ffb79ae3 bne a5,s11,8000642c -8000643c: 04011823 sh zero,80(sp) -80006440: 002d0d13 addi s10,s10,2 -80006444: f5a91ce3 bne s2,s10,8000639c -80006448: 00000593 li a1,0 -8000644c: 03c10793 addi a5,sp,60 -80006450: 05210693 addi a3,sp,82 -80006454: 0007d703 lhu a4,0(a5) -80006458: 00278793 addi a5,a5,2 -8000645c: 00e5e5b3 or a1,a1,a4 -80006460: fed79ae3 bne a5,a3,80006454 -80006464: 01059793 slli a5,a1,0x10 -80006468: 4107d793 srai a5,a5,0x10 -8000646c: 00078463 beqz a5,80006474 -80006470: 00100593 li a1,1 -80006474: 01059593 slli a1,a1,0x10 -80006478: 0105d593 srli a1,a1,0x10 -8000647c: 03448713 addi a4,s1,52 -80006480: 03810793 addi a5,sp,56 -80006484: 00075603 lhu a2,0(a4) -80006488: 00278793 addi a5,a5,2 -8000648c: 00270713 addi a4,a4,2 -80006490: fec79f23 sh a2,-2(a5) -80006494: fef698e3 bne a3,a5,80006484 -80006498: 00c12783 lw a5,12(sp) -8000649c: 00812703 lw a4,8(sp) -800064a0: 000046b7 lui a3,0x4 -800064a4: fff68693 addi a3,a3,-1 # 3fff <_start-0x7fffc001> -800064a8: 40e78bb3 sub s7,a5,a4 -800064ac: 03810513 addi a0,sp,56 -800064b0: 00048793 mv a5,s1 -800064b4: 04000713 li a4,64 -800064b8: 00db86b3 add a3,s7,a3 -800064bc: 00000613 li a2,0 -800064c0: a04ff0ef jal ra,800056c4 -800064c4: 03815703 lhu a4,56(sp) -800064c8: 01c15783 lhu a5,28(sp) -800064cc: 00040593 mv a1,s0 -800064d0: 03810513 addi a0,sp,56 -800064d4: 40e787b3 sub a5,a5,a4 -800064d8: 00f037b3 snez a5,a5 -800064dc: 40f007b3 neg a5,a5 -800064e0: 02f11c23 sh a5,56(sp) -800064e4: f54ff0ef jal ra,80005c38 -800064e8: ce5ff06f j 800061cc -800064ec: 01490713 addi a4,s2,20 -800064f0: 00095783 lhu a5,0(s2) -800064f4: 00290913 addi s2,s2,2 -800064f8: 00240413 addi s0,s0,2 -800064fc: fef41f23 sh a5,-2(s0) -80006500: fee918e3 bne s2,a4,800064f0 -80006504: cc9ff06f j 800061cc -80006508: eeb674e3 bgeu a2,a1,800063f0 -8000650c: fffb8793 addi a5,s7,-1 -80006510: 01079893 slli a7,a5,0x10 -80006514: 0108d893 srli a7,a7,0x10 -80006518: 00000793 li a5,0 -8000651c: 03410593 addi a1,sp,52 -80006520: 06c10613 addi a2,sp,108 -80006524: 00065703 lhu a4,0(a2) -80006528: 0005d803 lhu a6,0(a1) -8000652c: ffe60613 addi a2,a2,-2 -80006530: 40f70733 sub a4,a4,a5 -80006534: 41070733 sub a4,a4,a6 -80006538: 01075793 srli a5,a4,0x10 -8000653c: 00e61123 sh a4,2(a2) -80006540: 0017f793 andi a5,a5,1 -80006544: ffe58593 addi a1,a1,-2 -80006548: fd361ee3 bne a2,s3,80006524 -8000654c: 03c10713 addi a4,sp,60 -80006550: 05810793 addi a5,sp,88 -80006554: 0007d583 lhu a1,0(a5) -80006558: 00075603 lhu a2,0(a4) -8000655c: 00278793 addi a5,a5,2 -80006560: 00270713 addi a4,a4,2 -80006564: 00c59863 bne a1,a2,80006574 -80006568: ff9796e3 bne a5,s9,80006554 -8000656c: 00088b93 mv s7,a7 -80006570: e81ff06f j 800063f0 -80006574: feb67ce3 bgeu a2,a1,8000656c -80006578: ffeb8793 addi a5,s7,-2 -8000657c: 01079b93 slli s7,a5,0x10 -80006580: 010bdb93 srli s7,s7,0x10 -80006584: 00000613 li a2,0 -80006588: 03410593 addi a1,sp,52 -8000658c: 06c10713 addi a4,sp,108 -80006590: 00075783 lhu a5,0(a4) -80006594: 0005d803 lhu a6,0(a1) -80006598: ffe70713 addi a4,a4,-2 -8000659c: 40c787b3 sub a5,a5,a2 -800065a0: 410787b3 sub a5,a5,a6 -800065a4: 0107d613 srli a2,a5,0x10 -800065a8: 00f71123 sh a5,2(a4) -800065ac: 00167613 andi a2,a2,1 -800065b0: ffe58593 addi a1,a1,-2 -800065b4: fd371ee3 bne a4,s3,80006590 -800065b8: e39ff06f j 800063f0 -800065bc: 01440793 addi a5,s0,20 -800065c0: 00240413 addi s0,s0,2 -800065c4: fe041f23 sh zero,-2(s0) -800065c8: fe879ce3 bne a5,s0,800065c0 -800065cc: c01ff06f j 800061cc -800065d0: 01c15703 lhu a4,28(sp) -800065d4: 03815783 lhu a5,56(sp) -800065d8: 00f70463 beq a4,a5,800065e0 -800065dc: 00008637 lui a2,0x8 -800065e0: 00c41923 sh a2,18(s0) -800065e4: 01240713 addi a4,s0,18 -800065e8: 00040793 mv a5,s0 -800065ec: 00278793 addi a5,a5,2 -800065f0: fe079f23 sh zero,-2(a5) -800065f4: fef71ce3 bne a4,a5,800065ec -800065f8: 01245783 lhu a5,18(s0) -800065fc: 00008737 lui a4,0x8 -80006600: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80006604: 00e7e7b3 or a5,a5,a4 -80006608: 00f41923 sh a5,18(s0) -8000660c: bc1ff06f j 800061cc +80006050 : +80006050: 01255783 lhu a5,18(a0) +80006054: f5010113 addi sp,sp,-176 +80006058: 0a812423 sw s0,168(sp) +8000605c: fff7c793 not a5,a5 +80006060: 0a912223 sw s1,164(sp) +80006064: 0b212023 sw s2,160(sp) +80006068: 09312e23 sw s3,156(sp) +8000606c: 0a112623 sw ra,172(sp) +80006070: 09412c23 sw s4,152(sp) +80006074: 09512a23 sw s5,148(sp) +80006078: 09612823 sw s6,144(sp) +8000607c: 09712623 sw s7,140(sp) +80006080: 09812423 sw s8,136(sp) +80006084: 09912223 sw s9,132(sp) +80006088: 09a12023 sw s10,128(sp) +8000608c: 07b12e23 sw s11,124(sp) +80006090: 01179713 slli a4,a5,0x11 +80006094: 00050913 mv s2,a0 +80006098: 00058993 mv s3,a1 +8000609c: 00060413 mv s0,a2 +800060a0: 00068493 mv s1,a3 +800060a4: 00071663 bnez a4,800060b0 +800060a8: ef5fe0ef jal ra,80004f9c +800060ac: 38051863 bnez a0,8000643c +800060b0: 0129d783 lhu a5,18(s3) +800060b4: fff7c793 not a5,a5 +800060b8: 01179713 slli a4,a5,0x11 +800060bc: 08070e63 beqz a4,80006158 +800060c0: 80015a37 lui s4,0x80015 +800060c4: e60a0593 addi a1,s4,-416 # 80014e60 <__BSS_END__+0xffffe224> +800060c8: 00090513 mv a0,s2 +800060cc: 878ff0ef jal ra,80005144 +800060d0: 10050463 beqz a0,800061d8 +800060d4: 01295a03 lhu s4,18(s2) +800060d8: 0129d703 lhu a4,18(s3) +800060dc: 000087b7 lui a5,0x8 +800060e0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800060e4: 0147fa33 and s4,a5,s4 +800060e8: 00e7fab3 and s5,a5,a4 +800060ec: 08fa1a63 bne s4,a5,80006180 +800060f0: 00090513 mv a0,s2 +800060f4: 96cff0ef jal ra,80005260 +800060f8: 10050863 beqz a0,80006208 +800060fc: 014a9863 bne s5,s4,8000610c +80006100: 00098513 mv a0,s3 +80006104: 95cff0ef jal ra,80005260 +80006108: 0e051063 bnez a0,800061e8 +8000610c: 01440793 addi a5,s0,20 +80006110: 00240413 addi s0,s0,2 +80006114: fe041f23 sh zero,-2(s0) +80006118: fef41ce3 bne s0,a5,80006110 +8000611c: 0ac12083 lw ra,172(sp) +80006120: 0a812403 lw s0,168(sp) +80006124: 0a412483 lw s1,164(sp) +80006128: 0a012903 lw s2,160(sp) +8000612c: 09c12983 lw s3,156(sp) +80006130: 09812a03 lw s4,152(sp) +80006134: 09412a83 lw s5,148(sp) +80006138: 09012b03 lw s6,144(sp) +8000613c: 08c12b83 lw s7,140(sp) +80006140: 08812c03 lw s8,136(sp) +80006144: 08412c83 lw s9,132(sp) +80006148: 08012d03 lw s10,128(sp) +8000614c: 07c12d83 lw s11,124(sp) +80006150: 0b010113 addi sp,sp,176 +80006154: 00008067 ret +80006158: 00098513 mv a0,s3 +8000615c: e41fe0ef jal ra,80004f9c +80006160: f60500e3 beqz a0,800060c0 +80006164: 01498713 addi a4,s3,20 +80006168: 0009d783 lhu a5,0(s3) +8000616c: 00298993 addi s3,s3,2 +80006170: 00240413 addi s0,s0,2 +80006174: fef41f23 sh a5,-2(s0) +80006178: fee998e3 bne s3,a4,80006168 +8000617c: fa1ff06f j 8000611c +80006180: 08fa8663 beq s5,a5,8000620c +80006184: 00090513 mv a0,s2 +80006188: 01c10593 addi a1,sp,28 +8000618c: ec1fe0ef jal ra,8000504c +80006190: 03810593 addi a1,sp,56 +80006194: 00098513 mv a0,s3 +80006198: eb5fe0ef jal ra,8000504c +8000619c: 03a15b83 lhu s7,58(sp) +800061a0: 01e15903 lhu s2,30(sp) +800061a4: 0c0b9263 bnez s7,80006268 +800061a8: 03c10793 addi a5,sp,60 +800061ac: 05010d93 addi s11,sp,80 +800061b0: 34fd8e63 beq s11,a5,8000650c +800061b4: 0007d703 lhu a4,0(a5) +800061b8: 00278793 addi a5,a5,2 +800061bc: fe070ae3 beqz a4,800061b0 +800061c0: 03810513 addi a0,sp,56 +800061c4: ad4ff0ef jal ra,80005498 +800061c8: 40a007b3 neg a5,a0 +800061cc: 01e15603 lhu a2,30(sp) +800061d0: 00f12623 sw a5,12(sp) +800061d4: 09c0006f j 80006270 +800061d8: e60a0593 addi a1,s4,-416 +800061dc: 00098513 mv a0,s3 +800061e0: f65fe0ef jal ra,80005144 +800061e4: ee0518e3 bnez a0,800060d4 +800061e8: 01040713 addi a4,s0,16 +800061ec: 00040793 mv a5,s0 +800061f0: 00278793 addi a5,a5,2 +800061f4: fe079f23 sh zero,-2(a5) +800061f8: fee79ce3 bne a5,a4,800061f0 +800061fc: 7fffc7b7 lui a5,0x7fffc +80006200: 00f42823 sw a5,16(s0) +80006204: f19ff06f j 8000611c +80006208: f74a9ee3 bne s5,s4,80006184 +8000620c: 00098513 mv a0,s3 +80006210: 850ff0ef jal ra,80005260 +80006214: f60508e3 beqz a0,80006184 +80006218: 00090513 mv a0,s2 +8000621c: df1fe0ef jal ra,8000500c +80006220: 00050493 mv s1,a0 +80006224: 00098513 mv a0,s3 +80006228: de5fe0ef jal ra,8000500c +8000622c: 40a487b3 sub a5,s1,a0 +80006230: 00f037b3 snez a5,a5 +80006234: 00f79793 slli a5,a5,0xf +80006238: 00f41923 sh a5,18(s0) +8000623c: 01240713 addi a4,s0,18 +80006240: 00040793 mv a5,s0 +80006244: 00278793 addi a5,a5,2 # 7fffc002 <_start-0x3ffe> +80006248: fe079f23 sh zero,-2(a5) +8000624c: fee79ce3 bne a5,a4,80006244 +80006250: 01245783 lhu a5,18(s0) +80006254: 00008737 lui a4,0x8 +80006258: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +8000625c: 00e7e7b3 or a5,a5,a4 +80006260: 00f41923 sh a5,18(s0) +80006264: eb9ff06f j 8000611c +80006268: 01712623 sw s7,12(sp) +8000626c: 00090613 mv a2,s2 +80006270: 01212423 sw s2,8(sp) +80006274: 02010793 addi a5,sp,32 +80006278: 03410693 addi a3,sp,52 +8000627c: 02061263 bnez a2,800062a0 +80006280: 2af68063 beq a3,a5,80006520 +80006284: 0007d703 lhu a4,0(a5) +80006288: 00278793 addi a5,a5,2 +8000628c: fe070ae3 beqz a4,80006280 +80006290: 01c10513 addi a0,sp,28 +80006294: a04ff0ef jal ra,80005498 +80006298: 40a907b3 sub a5,s2,a0 +8000629c: 00f12423 sw a5,8(sp) +800062a0: 03812703 lw a4,56(sp) +800062a4: 03848d13 addi s10,s1,56 +800062a8: 000d0793 mv a5,s10 +800062ac: 02e4aa23 sw a4,52(s1) +800062b0: 04e48913 addi s2,s1,78 +800062b4: 00278793 addi a5,a5,2 +800062b8: fe079f23 sh zero,-2(a5) +800062bc: fef91ce3 bne s2,a5,800062b4 +800062c0: 03810513 addi a0,sp,56 +800062c4: b69fe0ef jal ra,80004e2c +800062c8: 02215c03 lhu s8,34(sp) +800062cc: 00010a37 lui s4,0x10 +800062d0: 05010d93 addi s11,sp,80 +800062d4: 010c1a93 slli s5,s8,0x10 +800062d8: 418a8ab3 sub s5,s5,s8 +800062dc: 03a10b13 addi s6,sp,58 +800062e0: fffa0a13 addi s4,s4,-1 # ffff <_start-0x7fff0001> +800062e4: 06e10c93 addi s9,sp,110 +800062e8: 05610993 addi s3,sp,86 +800062ec: 03c15783 lhu a5,60(sp) +800062f0: 03e15703 lhu a4,62(sp) +800062f4: 000a0b93 mv s7,s4 +800062f8: 01079793 slli a5,a5,0x10 +800062fc: 00e787b3 add a5,a5,a4 +80006300: 00fae863 bltu s5,a5,80006310 +80006304: 0387d7b3 divu a5,a5,s8 +80006308: 01079b93 slli s7,a5,0x10 +8000630c: 010bdb93 srli s7,s7,0x10 +80006310: 05410613 addi a2,sp,84 +80006314: 01c10593 addi a1,sp,28 +80006318: 000b8513 mv a0,s7 +8000631c: be9fe0ef jal ra,80004f04 +80006320: 03c10713 addi a4,sp,60 +80006324: 05810793 addi a5,sp,88 +80006328: 0007d583 lhu a1,0(a5) +8000632c: 00075603 lhu a2,0(a4) +80006330: 00278793 addi a5,a5,2 +80006334: 00270713 addi a4,a4,2 +80006338: 12c59063 bne a1,a2,80006458 +8000633c: ff9796e3 bne a5,s9,80006328 +80006340: 00000793 li a5,0 +80006344: 06c10593 addi a1,sp,108 +80006348: 000d8613 mv a2,s11 +8000634c: 00065703 lhu a4,0(a2) +80006350: 0005d803 lhu a6,0(a1) +80006354: ffe60613 addi a2,a2,-2 +80006358: 40f70733 sub a4,a4,a5 +8000635c: 41070733 sub a4,a4,a6 +80006360: 01075793 srli a5,a4,0x10 +80006364: 00e61123 sh a4,2(a2) +80006368: 0017f793 andi a5,a5,1 +8000636c: ffe58593 addi a1,a1,-2 +80006370: fd661ee3 bne a2,s6,8000634c +80006374: 017d1023 sh s7,0(s10) +80006378: 03c10793 addi a5,sp,60 +8000637c: 0027d703 lhu a4,2(a5) +80006380: 00278793 addi a5,a5,2 +80006384: fee79f23 sh a4,-2(a5) +80006388: ffb79ae3 bne a5,s11,8000637c +8000638c: 04011823 sh zero,80(sp) +80006390: 002d0d13 addi s10,s10,2 +80006394: f5a91ce3 bne s2,s10,800062ec +80006398: 00000593 li a1,0 +8000639c: 03c10793 addi a5,sp,60 +800063a0: 05210693 addi a3,sp,82 +800063a4: 0007d703 lhu a4,0(a5) +800063a8: 00278793 addi a5,a5,2 +800063ac: 00e5e5b3 or a1,a1,a4 +800063b0: fed79ae3 bne a5,a3,800063a4 +800063b4: 01059793 slli a5,a1,0x10 +800063b8: 4107d793 srai a5,a5,0x10 +800063bc: 00078463 beqz a5,800063c4 +800063c0: 00100593 li a1,1 +800063c4: 01059593 slli a1,a1,0x10 +800063c8: 0105d593 srli a1,a1,0x10 +800063cc: 03448713 addi a4,s1,52 +800063d0: 03810793 addi a5,sp,56 +800063d4: 00075603 lhu a2,0(a4) +800063d8: 00278793 addi a5,a5,2 +800063dc: 00270713 addi a4,a4,2 +800063e0: fec79f23 sh a2,-2(a5) +800063e4: fef698e3 bne a3,a5,800063d4 +800063e8: 00c12783 lw a5,12(sp) +800063ec: 00812703 lw a4,8(sp) +800063f0: 000046b7 lui a3,0x4 +800063f4: fff68693 addi a3,a3,-1 # 3fff <_start-0x7fffc001> +800063f8: 40e78bb3 sub s7,a5,a4 +800063fc: 03810513 addi a0,sp,56 +80006400: 00048793 mv a5,s1 +80006404: 04000713 li a4,64 +80006408: 00db86b3 add a3,s7,a3 +8000640c: 00000613 li a2,0 +80006410: a04ff0ef jal ra,80005614 +80006414: 03815703 lhu a4,56(sp) +80006418: 01c15783 lhu a5,28(sp) +8000641c: 00040593 mv a1,s0 +80006420: 03810513 addi a0,sp,56 +80006424: 40e787b3 sub a5,a5,a4 +80006428: 00f037b3 snez a5,a5 +8000642c: 40f007b3 neg a5,a5 +80006430: 02f11c23 sh a5,56(sp) +80006434: f54ff0ef jal ra,80005b88 +80006438: ce5ff06f j 8000611c +8000643c: 01490713 addi a4,s2,20 +80006440: 00095783 lhu a5,0(s2) +80006444: 00290913 addi s2,s2,2 +80006448: 00240413 addi s0,s0,2 +8000644c: fef41f23 sh a5,-2(s0) +80006450: fee918e3 bne s2,a4,80006440 +80006454: cc9ff06f j 8000611c +80006458: eeb674e3 bgeu a2,a1,80006340 +8000645c: fffb8793 addi a5,s7,-1 +80006460: 01079893 slli a7,a5,0x10 +80006464: 0108d893 srli a7,a7,0x10 +80006468: 00000793 li a5,0 +8000646c: 03410593 addi a1,sp,52 +80006470: 06c10613 addi a2,sp,108 +80006474: 00065703 lhu a4,0(a2) +80006478: 0005d803 lhu a6,0(a1) +8000647c: ffe60613 addi a2,a2,-2 +80006480: 40f70733 sub a4,a4,a5 +80006484: 41070733 sub a4,a4,a6 +80006488: 01075793 srli a5,a4,0x10 +8000648c: 00e61123 sh a4,2(a2) +80006490: 0017f793 andi a5,a5,1 +80006494: ffe58593 addi a1,a1,-2 +80006498: fd361ee3 bne a2,s3,80006474 +8000649c: 03c10713 addi a4,sp,60 +800064a0: 05810793 addi a5,sp,88 +800064a4: 0007d583 lhu a1,0(a5) +800064a8: 00075603 lhu a2,0(a4) +800064ac: 00278793 addi a5,a5,2 +800064b0: 00270713 addi a4,a4,2 +800064b4: 00c59863 bne a1,a2,800064c4 +800064b8: ff9796e3 bne a5,s9,800064a4 +800064bc: 00088b93 mv s7,a7 +800064c0: e81ff06f j 80006340 +800064c4: feb67ce3 bgeu a2,a1,800064bc +800064c8: ffeb8793 addi a5,s7,-2 +800064cc: 01079b93 slli s7,a5,0x10 +800064d0: 010bdb93 srli s7,s7,0x10 +800064d4: 00000613 li a2,0 +800064d8: 03410593 addi a1,sp,52 +800064dc: 06c10713 addi a4,sp,108 +800064e0: 00075783 lhu a5,0(a4) +800064e4: 0005d803 lhu a6,0(a1) +800064e8: ffe70713 addi a4,a4,-2 +800064ec: 40c787b3 sub a5,a5,a2 +800064f0: 410787b3 sub a5,a5,a6 +800064f4: 0107d613 srli a2,a5,0x10 +800064f8: 00f71123 sh a5,2(a4) +800064fc: 00167613 andi a2,a2,1 +80006500: ffe58593 addi a1,a1,-2 +80006504: fd371ee3 bne a4,s3,800064e0 +80006508: e39ff06f j 80006340 +8000650c: 01440793 addi a5,s0,20 +80006510: 00240413 addi s0,s0,2 +80006514: fe041f23 sh zero,-2(s0) +80006518: fe879ce3 bne a5,s0,80006510 +8000651c: c01ff06f j 8000611c +80006520: 01c15703 lhu a4,28(sp) +80006524: 03815783 lhu a5,56(sp) +80006528: 00f70463 beq a4,a5,80006530 +8000652c: 00008637 lui a2,0x8 +80006530: 00c41923 sh a2,18(s0) +80006534: 01240713 addi a4,s0,18 +80006538: 00040793 mv a5,s0 +8000653c: 00278793 addi a5,a5,2 +80006540: fe079f23 sh zero,-2(a5) +80006544: fef71ce3 bne a4,a5,8000653c +80006548: 01245783 lhu a5,18(s0) +8000654c: 00008737 lui a4,0x8 +80006550: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80006554: 00e7e7b3 or a5,a5,a4 +80006558: 00f41923 sh a5,18(s0) +8000655c: bc1ff06f j 8000611c -80006610 : -80006610: fd010113 addi sp,sp,-48 -80006614: 02812423 sw s0,40(sp) -80006618: 02112623 sw ra,44(sp) -8000661c: 00058413 mv s0,a1 -80006620: 00410793 addi a5,sp,4 -80006624: 01e10713 addi a4,sp,30 +80006560 : +80006560: fd010113 addi sp,sp,-48 +80006564: 02812423 sw s0,40(sp) +80006568: 02112623 sw ra,44(sp) +8000656c: 00058413 mv s0,a1 +80006570: 00410793 addi a5,sp,4 +80006574: 01e10713 addi a4,sp,30 +80006578: 00278793 addi a5,a5,2 +8000657c: fe079f23 sh zero,-2(a5) +80006580: fee79ce3 bne a5,a4,80006578 +80006584: 00e55603 lhu a2,14(a0) +80006588: 01061793 slli a5,a2,0x10 +8000658c: 4107d793 srai a5,a5,0x10 +80006590: 0607ca63 bltz a5,80006604 +80006594: 000087b7 lui a5,0x8 +80006598: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +8000659c: 00011223 sh zero,4(sp) +800065a0: 00f67633 and a2,a2,a5 +800065a4: 06f60c63 beq a2,a5,8000661c +800065a8: 00e50793 addi a5,a0,14 +800065ac: 00c11323 sh a2,6(sp) +800065b0: 00a10713 addi a4,sp,10 +800065b4: ffe7d683 lhu a3,-2(a5) +800065b8: ffe78793 addi a5,a5,-2 +800065bc: 00270713 addi a4,a4,2 +800065c0: fed71f23 sh a3,-2(a4) +800065c4: fef518e3 bne a0,a5,800065b4 +800065c8: 02061263 bnez a2,800065ec +800065cc: 00011423 sh zero,8(sp) +800065d0: 00040593 mv a1,s0 +800065d4: 00410513 addi a0,sp,4 +800065d8: db0ff0ef jal ra,80005b88 +800065dc: 02c12083 lw ra,44(sp) +800065e0: 02812403 lw s0,40(sp) +800065e4: 03010113 addi sp,sp,48 +800065e8: 00008067 ret +800065ec: 00100793 li a5,1 +800065f0: fff00593 li a1,-1 +800065f4: 00410513 addi a0,sp,4 +800065f8: 00f11423 sh a5,8(sp) +800065fc: c81fe0ef jal ra,8000527c +80006600: fd1ff06f j 800065d0 +80006604: fff00793 li a5,-1 +80006608: 00f11223 sh a5,4(sp) +8000660c: 000087b7 lui a5,0x8 +80006610: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80006614: 00f67633 and a2,a2,a5 +80006618: f8f618e3 bne a2,a5,800065a8 +8000661c: 00050793 mv a5,a0 +80006620: 00e50693 addi a3,a0,14 +80006624: 0007d703 lhu a4,0(a5) 80006628: 00278793 addi a5,a5,2 -8000662c: fe079f23 sh zero,-2(a5) -80006630: fee79ce3 bne a5,a4,80006628 -80006634: 00e55603 lhu a2,14(a0) -80006638: 01061793 slli a5,a2,0x10 -8000663c: 4107d793 srai a5,a5,0x10 -80006640: 0607ca63 bltz a5,800066b4 -80006644: 000087b7 lui a5,0x8 -80006648: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -8000664c: 00011223 sh zero,4(sp) -80006650: 00f67633 and a2,a2,a5 -80006654: 06f60c63 beq a2,a5,800066cc -80006658: 00e50793 addi a5,a0,14 -8000665c: 00c11323 sh a2,6(sp) -80006660: 00a10713 addi a4,sp,10 -80006664: ffe7d683 lhu a3,-2(a5) -80006668: ffe78793 addi a5,a5,-2 -8000666c: 00270713 addi a4,a4,2 -80006670: fed71f23 sh a3,-2(a4) -80006674: fef518e3 bne a0,a5,80006664 -80006678: 02061263 bnez a2,8000669c -8000667c: 00011423 sh zero,8(sp) -80006680: 00040593 mv a1,s0 -80006684: 00410513 addi a0,sp,4 -80006688: db0ff0ef jal ra,80005c38 -8000668c: 02c12083 lw ra,44(sp) -80006690: 02812403 lw s0,40(sp) -80006694: 03010113 addi sp,sp,48 -80006698: 00008067 ret -8000669c: 00100793 li a5,1 -800066a0: fff00593 li a1,-1 -800066a4: 00410513 addi a0,sp,4 -800066a8: 00f11423 sh a5,8(sp) -800066ac: c81fe0ef jal ra,8000532c -800066b0: fd1ff06f j 80006680 -800066b4: fff00793 li a5,-1 -800066b8: 00f11223 sh a5,4(sp) -800066bc: 000087b7 lui a5,0x8 -800066c0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800066c4: 00f67633 and a2,a2,a5 -800066c8: f8f618e3 bne a2,a5,80006658 -800066cc: 00050793 mv a5,a0 -800066d0: 00e50693 addi a3,a0,14 -800066d4: 0007d703 lhu a4,0(a5) -800066d8: 00278793 addi a5,a5,2 -800066dc: 04071c63 bnez a4,80006734 -800066e0: fed79ae3 bne a5,a3,800066d4 -800066e4: 01440713 addi a4,s0,20 -800066e8: 00040793 mv a5,s0 -800066ec: 00278793 addi a5,a5,2 -800066f0: fe079f23 sh zero,-2(a5) -800066f4: fef71ce3 bne a4,a5,800066ec -800066f8: 01240713 addi a4,s0,18 -800066fc: 00040793 mv a5,s0 -80006700: 00278793 addi a5,a5,2 -80006704: fe079f23 sh zero,-2(a5) -80006708: fef71ce3 bne a4,a5,80006700 -8000670c: 01245783 lhu a5,18(s0) -80006710: 00008737 lui a4,0x8 -80006714: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80006718: 00e7e7b3 or a5,a5,a4 -8000671c: 00f41923 sh a5,18(s0) -80006720: 00e51783 lh a5,14(a0) -80006724: f607d4e3 bgez a5,8000668c -80006728: 00040513 mv a0,s0 -8000672c: 945fe0ef jal ra,80005070 -80006730: f5dff06f j 8000668c -80006734: 01040713 addi a4,s0,16 -80006738: 00040793 mv a5,s0 -8000673c: 00278793 addi a5,a5,2 -80006740: fe079f23 sh zero,-2(a5) -80006744: fef71ce3 bne a4,a5,8000673c -80006748: 7fffc7b7 lui a5,0x7fffc -8000674c: 00f42823 sw a5,16(s0) -80006750: f3dff06f j 8000668c +8000662c: 04071c63 bnez a4,80006684 +80006630: fed79ae3 bne a5,a3,80006624 +80006634: 01440713 addi a4,s0,20 +80006638: 00040793 mv a5,s0 +8000663c: 00278793 addi a5,a5,2 +80006640: fe079f23 sh zero,-2(a5) +80006644: fef71ce3 bne a4,a5,8000663c +80006648: 01240713 addi a4,s0,18 +8000664c: 00040793 mv a5,s0 +80006650: 00278793 addi a5,a5,2 +80006654: fe079f23 sh zero,-2(a5) +80006658: fef71ce3 bne a4,a5,80006650 +8000665c: 01245783 lhu a5,18(s0) +80006660: 00008737 lui a4,0x8 +80006664: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80006668: 00e7e7b3 or a5,a5,a4 +8000666c: 00f41923 sh a5,18(s0) +80006670: 00e51783 lh a5,14(a0) +80006674: f607d4e3 bgez a5,800065dc +80006678: 00040513 mv a0,s0 +8000667c: 945fe0ef jal ra,80004fc0 +80006680: f5dff06f j 800065dc +80006684: 01040713 addi a4,s0,16 +80006688: 00040793 mv a5,s0 +8000668c: 00278793 addi a5,a5,2 +80006690: fe079f23 sh zero,-2(a5) +80006694: fef71ce3 bne a4,a5,8000668c +80006698: 7fffc7b7 lui a5,0x7fffc +8000669c: 00f42823 sw a5,16(s0) +800066a0: f3dff06f j 800065dc -80006754 <_ldtoa_r>: -80006754: 00c5a883 lw a7,12(a1) -80006758: e1010113 addi sp,sp,-496 -8000675c: 0005ae83 lw t4,0(a1) -80006760: 0045ae03 lw t3,4(a1) -80006764: 0085a303 lw t1,8(a1) -80006768: 03112e23 sw a7,60(sp) -8000676c: 04052583 lw a1,64(a0) -80006770: fff00893 li a7,-1 -80006774: 17112023 sw a7,352(sp) -80006778: 09000893 li a7,144 -8000677c: 1e812423 sw s0,488(sp) -80006780: 1d412c23 sw s4,472(sp) -80006784: 1e112623 sw ra,492(sp) -80006788: 1e912223 sw s1,484(sp) -8000678c: 1f212023 sw s2,480(sp) -80006790: 1d312e23 sw s3,476(sp) -80006794: 1d512a23 sw s5,468(sp) -80006798: 1d612823 sw s6,464(sp) -8000679c: 1d712623 sw s7,460(sp) -800067a0: 1d812423 sw s8,456(sp) -800067a4: 1d912223 sw s9,452(sp) -800067a8: 1da12023 sw s10,448(sp) -800067ac: 1bb12e23 sw s11,444(sp) -800067b0: 03d12823 sw t4,48(sp) -800067b4: 03c12a23 sw t3,52(sp) -800067b8: 02612c23 sw t1,56(sp) -800067bc: 17112223 sw a7,356(sp) -800067c0: 00c12023 sw a2,0(sp) -800067c4: 00d12423 sw a3,8(sp) -800067c8: 00e12623 sw a4,12(sp) -800067cc: 01012c23 sw a6,24(sp) -800067d0: 00050a13 mv s4,a0 -800067d4: 00078413 mv s0,a5 -800067d8: 02058063 beqz a1,800067f8 <_ldtoa_r+0xa4> -800067dc: 04452703 lw a4,68(a0) -800067e0: 00100793 li a5,1 -800067e4: 00e797b3 sll a5,a5,a4 -800067e8: 00e5a223 sw a4,4(a1) -800067ec: 00f5a423 sw a5,8(a1) -800067f0: 68d010ef jal ra,8000867c <_Bfree> -800067f4: 040a2023 sw zero,64(s4) -800067f8: 06010993 addi s3,sp,96 -800067fc: 00098593 mv a1,s3 -80006800: 03010513 addi a0,sp,48 -80006804: e0dff0ef jal ra,80006610 -80006808: 00098513 mv a0,s3 -8000680c: 8b1fe0ef jal ra,800050bc -80006810: 00012703 lw a4,0(sp) -80006814: 00a03533 snez a0,a0 -80006818: 00a42023 sw a0,0(s0) -8000681c: 00300793 li a5,3 -80006820: 14f702e3 beq a4,a5,80007164 <_ldtoa_r+0xa10> -80006824: 01400793 li a5,20 -80006828: 00f12223 sw a5,4(sp) -8000682c: 5e0718e3 bnez a4,8000761c <_ldtoa_r+0xec8> -80006830: 07215783 lhu a5,114(sp) -80006834: 16412703 lw a4,356(sp) -80006838: fff7c793 not a5,a5 -8000683c: 00e12a23 sw a4,20(sp) -80006840: 01179713 slli a4,a5,0x11 -80006844: 00071863 bnez a4,80006854 <_ldtoa_r+0x100> -80006848: 00098513 mv a0,s3 -8000684c: 801fe0ef jal ra,8000504c -80006850: 400514e3 bnez a0,80007458 <_ldtoa_r+0xd04> -80006854: 09000793 li a5,144 -80006858: 16f12223 sw a5,356(sp) -8000685c: 07c10713 addi a4,sp,124 -80006860: 00098793 mv a5,s3 -80006864: 07410613 addi a2,sp,116 -80006868: 0007d683 lhu a3,0(a5) # 7fffc000 <_start-0x4000> -8000686c: 00278793 addi a5,a5,2 -80006870: 00270713 addi a4,a4,2 -80006874: fed71f23 sh a3,-2(a4) -80006878: fec798e3 bne a5,a2,80006868 <_ldtoa_r+0x114> -8000687c: 08e15603 lhu a2,142(sp) -80006880: 00012823 sw zero,16(sp) -80006884: 01061793 slli a5,a2,0x10 -80006888: 4107d793 srai a5,a5,0x10 -8000688c: 0007de63 bgez a5,800068a8 <_ldtoa_r+0x154> -80006890: 01161613 slli a2,a2,0x11 -80006894: 000107b7 lui a5,0x10 -80006898: 01165613 srli a2,a2,0x11 -8000689c: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -800068a0: 08c11723 sh a2,142(sp) -800068a4: 00f12823 sw a5,16(sp) -800068a8: 80015b37 lui s6,0x80015 -800068ac: e14b0d93 addi s11,s6,-492 # 80014e14 <__BSS_END__+0xffffe1e4> -800068b0: 014d8c13 addi s8,s11,20 -800068b4: 00000693 li a3,0 -800068b8: 09810793 addi a5,sp,152 -800068bc: 000c0713 mv a4,s8 -800068c0: 0ac10d13 addi s10,sp,172 -800068c4: 0080006f j 800068cc <_ldtoa_r+0x178> -800068c8: 00075683 lhu a3,0(a4) -800068cc: 00278793 addi a5,a5,2 -800068d0: fed79f23 sh a3,-2(a5) -800068d4: 00270713 addi a4,a4,2 -800068d8: ffa798e3 bne a5,s10,800068c8 <_ldtoa_r+0x174> -800068dc: 14060863 beqz a2,80006a2c <_ldtoa_r+0x2d8> -800068e0: 000087b7 lui a5,0x8 -800068e4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800068e8: 56f606e3 beq a2,a5,80007654 <_ldtoa_r+0xf00> -800068ec: 08c11783 lh a5,140(sp) -800068f0: 5a07d8e3 bgez a5,800076a0 <_ldtoa_r+0xf4c> -800068f4: 07c10593 addi a1,sp,124 -800068f8: 000c0513 mv a0,s8 -800068fc: 8f9fe0ef jal ra,800051f4 -80006900: 14050263 beqz a0,80006a44 <_ldtoa_r+0x2f0> -80006904: 0c054ce3 bltz a0,800071dc <_ldtoa_r+0xa88> -80006908: 08e15783 lhu a5,142(sp) -8000690c: 62079ce3 bnez a5,80007744 <_ldtoa_r+0xff0> -80006910: 08c11783 lh a5,140(sp) -80006914: 00000493 li s1,0 -80006918: 16010913 addi s2,sp,352 -8000691c: 0207c463 bltz a5,80006944 <_ldtoa_r+0x1f0> -80006920: 118d8413 addi s0,s11,280 -80006924: 07c10613 addi a2,sp,124 -80006928: 00090693 mv a3,s2 -8000692c: 00060593 mv a1,a2 -80006930: 00040513 mv a0,s0 -80006934: bb4ff0ef jal ra,80005ce8 -80006938: 08c11783 lh a5,140(sp) -8000693c: fff48493 addi s1,s1,-1 -80006940: fe07d2e3 bgez a5,80006924 <_ldtoa_r+0x1d0> -80006944: 0d010413 addi s0,sp,208 -80006948: 0e810b93 addi s7,sp,232 -8000694c: 00040713 mv a4,s0 -80006950: 07c10793 addi a5,sp,124 -80006954: 09010613 addi a2,sp,144 -80006958: 0007d683 lhu a3,0(a5) -8000695c: 00278793 addi a5,a5,2 -80006960: 00270713 addi a4,a4,2 -80006964: fed71f23 sh a3,-2(a4) -80006968: fec798e3 bne a5,a2,80006958 <_ldtoa_r+0x204> -8000696c: 00000693 li a3,0 -80006970: 09810793 addi a5,sp,152 -80006974: 000c0713 mv a4,s8 -80006978: 0080006f j 80006980 <_ldtoa_r+0x22c> -8000697c: 00075683 lhu a3,0(a4) -80006980: 00278793 addi a5,a5,2 -80006984: fed79f23 sh a3,-2(a5) -80006988: 00270713 addi a4,a4,2 -8000698c: ffa798e3 bne a5,s10,8000697c <_ldtoa_r+0x228> -80006990: 028d8c93 addi s9,s11,40 -80006994: 12cd8d13 addi s10,s11,300 -80006998: fffffab7 lui s5,0xfffff -8000699c: 118d8d93 addi s11,s11,280 -800069a0: 00c0006f j 800069ac <_ldtoa_r+0x258> -800069a4: 014d0d13 addi s10,s10,20 -800069a8: 014c8c93 addi s9,s9,20 -800069ac: 00040593 mv a1,s0 -800069b0: 000c0513 mv a0,s8 -800069b4: 841fe0ef jal ra,800051f4 -800069b8: 00050793 mv a5,a0 -800069bc: 00040593 mv a1,s0 -800069c0: 000d0513 mv a0,s10 -800069c4: 04f05663 blez a5,80006a10 <_ldtoa_r+0x2bc> -800069c8: 82dfe0ef jal ra,800051f4 -800069cc: 00050793 mv a5,a0 -800069d0: 00090693 mv a3,s2 -800069d4: 00040613 mv a2,s0 -800069d8: 00040593 mv a1,s0 -800069dc: 000c8513 mv a0,s9 -800069e0: 0207c063 bltz a5,80006a00 <_ldtoa_r+0x2ac> -800069e4: b04ff0ef jal ra,80005ce8 -800069e8: 09810613 addi a2,sp,152 -800069ec: 00090693 mv a3,s2 -800069f0: 00060593 mv a1,a2 -800069f4: 000c8513 mv a0,s9 -800069f8: af0ff0ef jal ra,80005ce8 -800069fc: 015484b3 add s1,s1,s5 -80006a00: 01fad793 srli a5,s5,0x1f -80006a04: 015787b3 add a5,a5,s5 -80006a08: 4017da93 srai s5,a5,0x1 -80006a0c: f9bc9ce3 bne s9,s11,800069a4 <_ldtoa_r+0x250> -80006a10: 09810613 addi a2,sp,152 -80006a14: 00090693 mv a3,s2 -80006a18: 000c0593 mv a1,s8 -80006a1c: 00060513 mv a0,a2 -80006a20: ee0ff0ef jal ra,80006100 -80006a24: 12410a93 addi s5,sp,292 -80006a28: 0300006f j 80006a58 <_ldtoa_r+0x304> -80006a2c: 07c10793 addi a5,sp,124 -80006a30: 08e10693 addi a3,sp,142 -80006a34: 0007d703 lhu a4,0(a5) -80006a38: 00278793 addi a5,a5,2 -80006a3c: ea071ce3 bnez a4,800068f4 <_ldtoa_r+0x1a0> -80006a40: fed79ae3 bne a5,a3,80006a34 <_ldtoa_r+0x2e0> -80006a44: 00000493 li s1,0 -80006a48: 12410a93 addi s5,sp,292 -80006a4c: 16010913 addi s2,sp,352 -80006a50: 0d010413 addi s0,sp,208 -80006a54: 0e810b93 addi s7,sp,232 -80006a58: 00040593 mv a1,s0 -80006a5c: 09810513 addi a0,sp,152 -80006a60: e9cfe0ef jal ra,800050fc -80006a64: 09810713 addi a4,sp,152 -80006a68: 00040793 mv a5,s0 -80006a6c: 0007d683 lhu a3,0(a5) -80006a70: 00278793 addi a5,a5,2 -80006a74: 00270713 addi a4,a4,2 -80006a78: fed71f23 sh a3,-2(a4) -80006a7c: ff7798e3 bne a5,s7,80006a6c <_ldtoa_r+0x318> -80006a80: 00040593 mv a1,s0 -80006a84: 07c10513 addi a0,sp,124 -80006a88: 0a011823 sh zero,176(sp) -80006a8c: e70fe0ef jal ra,800050fc -80006a90: 07c10793 addi a5,sp,124 -80006a94: 00045703 lhu a4,0(s0) -80006a98: 00240413 addi s0,s0,2 -80006a9c: 00278793 addi a5,a5,2 -80006aa0: fee79f23 sh a4,-2(a5) -80006aa4: ff7418e3 bne s0,s7,80006a94 <_ldtoa_r+0x340> -80006aa8: 09810513 addi a0,sp,152 -80006aac: 00090613 mv a2,s2 -80006ab0: 07c10593 addi a1,sp,124 -80006ab4: 08011a23 sh zero,148(sp) -80006ab8: 818ff0ef jal ra,80005ad0 -80006abc: 1ac15503 lhu a0,428(sp) -80006ac0: 1c051463 bnez a0,80006c88 <_ldtoa_r+0x534> -80006ac4: 09410c93 addi s9,sp,148 -80006ac8: 07e10413 addi s0,sp,126 -80006acc: 0b610c13 addi s8,sp,182 -80006ad0: e14b0593 addi a1,s6,-492 -80006ad4: 07c10513 addi a0,sp,124 -80006ad8: f1cfe0ef jal ra,800051f4 -80006adc: 1a050663 beqz a0,80006c88 <_ldtoa_r+0x534> -80006ae0: 00000713 li a4,0 -80006ae4: 000c8693 mv a3,s9 -80006ae8: 01c0006f j 80006b04 <_ldtoa_r+0x3b0> -80006aec: 00171713 slli a4,a4,0x1 -80006af0: 00f69023 sh a5,0(a3) -80006af4: 01071713 slli a4,a4,0x10 -80006af8: ffe68693 addi a3,a3,-2 -80006afc: 01075713 srli a4,a4,0x10 -80006b00: 04868463 beq a3,s0,80006b48 <_ldtoa_r+0x3f4> -80006b04: 0006d783 lhu a5,0(a3) -80006b08: 01079613 slli a2,a5,0x10 -80006b0c: 41065613 srai a2,a2,0x10 -80006b10: 00179793 slli a5,a5,0x1 -80006b14: 00065463 bgez a2,80006b1c <_ldtoa_r+0x3c8> -80006b18: 00176713 ori a4,a4,1 -80006b1c: 01079793 slli a5,a5,0x10 -80006b20: 0107d793 srli a5,a5,0x10 -80006b24: 00277613 andi a2,a4,2 -80006b28: 0017e593 ori a1,a5,1 -80006b2c: fc0600e3 beqz a2,80006aec <_ldtoa_r+0x398> -80006b30: 00171713 slli a4,a4,0x1 -80006b34: 00b69023 sh a1,0(a3) -80006b38: 01071713 slli a4,a4,0x10 -80006b3c: ffe68693 addi a3,a3,-2 -80006b40: 01075713 srli a4,a4,0x10 -80006b44: fc8690e3 bne a3,s0,80006b04 <_ldtoa_r+0x3b0> -80006b48: 0b410713 addi a4,sp,180 -80006b4c: 07c10793 addi a5,sp,124 -80006b50: 0007d683 lhu a3,0(a5) -80006b54: 00278793 addi a5,a5,2 -80006b58: 00270713 addi a4,a4,2 -80006b5c: fed71f23 sh a3,-2(a4) -80006b60: ff9798e3 bne a5,s9,80006b50 <_ldtoa_r+0x3fc> -80006b64: 0c011623 sh zero,204(sp) -80006b68: 00000713 li a4,0 -80006b6c: 0cc10693 addi a3,sp,204 -80006b70: 01c0006f j 80006b8c <_ldtoa_r+0x438> -80006b74: 00171713 slli a4,a4,0x1 -80006b78: 00f69023 sh a5,0(a3) -80006b7c: 01071713 slli a4,a4,0x10 -80006b80: ffe68693 addi a3,a3,-2 -80006b84: 01075713 srli a4,a4,0x10 -80006b88: 05868463 beq a3,s8,80006bd0 <_ldtoa_r+0x47c> -80006b8c: 0006d783 lhu a5,0(a3) -80006b90: 01079613 slli a2,a5,0x10 -80006b94: 41065613 srai a2,a2,0x10 -80006b98: 00179793 slli a5,a5,0x1 -80006b9c: 00065463 bgez a2,80006ba4 <_ldtoa_r+0x450> -80006ba0: 00176713 ori a4,a4,1 -80006ba4: 01079793 slli a5,a5,0x10 -80006ba8: 0107d793 srli a5,a5,0x10 -80006bac: 00277613 andi a2,a4,2 -80006bb0: 0017e593 ori a1,a5,1 -80006bb4: fc0600e3 beqz a2,80006b74 <_ldtoa_r+0x420> -80006bb8: 00171713 slli a4,a4,0x1 -80006bbc: 00b69023 sh a1,0(a3) -80006bc0: 01071713 slli a4,a4,0x10 -80006bc4: ffe68693 addi a3,a3,-2 -80006bc8: 01075713 srli a4,a4,0x10 -80006bcc: fd8690e3 bne a3,s8,80006b8c <_ldtoa_r+0x438> -80006bd0: 00000713 li a4,0 -80006bd4: 0cc10693 addi a3,sp,204 -80006bd8: 01c0006f j 80006bf4 <_ldtoa_r+0x4a0> -80006bdc: 00171713 slli a4,a4,0x1 -80006be0: 00f69023 sh a5,0(a3) -80006be4: 01071713 slli a4,a4,0x10 -80006be8: ffe68693 addi a3,a3,-2 -80006bec: 01075713 srli a4,a4,0x10 -80006bf0: 05868463 beq a3,s8,80006c38 <_ldtoa_r+0x4e4> -80006bf4: 0006d783 lhu a5,0(a3) -80006bf8: 01079613 slli a2,a5,0x10 -80006bfc: 41065613 srai a2,a2,0x10 -80006c00: 00179793 slli a5,a5,0x1 -80006c04: 00065463 bgez a2,80006c0c <_ldtoa_r+0x4b8> -80006c08: 00176713 ori a4,a4,1 -80006c0c: 01079793 slli a5,a5,0x10 -80006c10: 0107d793 srli a5,a5,0x10 -80006c14: 00277613 andi a2,a4,2 -80006c18: 0017e593 ori a1,a5,1 -80006c1c: fc0600e3 beqz a2,80006bdc <_ldtoa_r+0x488> -80006c20: 00171713 slli a4,a4,0x1 -80006c24: 00b69023 sh a1,0(a3) -80006c28: 01071713 slli a4,a4,0x10 -80006c2c: ffe68693 addi a3,a3,-2 -80006c30: 01075713 srli a4,a4,0x10 -80006c34: fd8690e3 bne a3,s8,80006bf4 <_ldtoa_r+0x4a0> -80006c38: 00000613 li a2,0 -80006c3c: 000c8693 mv a3,s9 -80006c40: 0cc10713 addi a4,sp,204 -80006c44: 0006d583 lhu a1,0(a3) -80006c48: 00075783 lhu a5,0(a4) -80006c4c: ffe68693 addi a3,a3,-2 -80006c50: ffe70713 addi a4,a4,-2 -80006c54: 00b787b3 add a5,a5,a1 -80006c58: 00c787b3 add a5,a5,a2 -80006c5c: 0107d613 srli a2,a5,0x10 -80006c60: 00f69123 sh a5,2(a3) -80006c64: 00167613 andi a2,a2,1 -80006c68: fd871ee3 bne a4,s8,80006c44 <_ldtoa_r+0x4f0> -80006c6c: 09810513 addi a0,sp,152 -80006c70: 00090613 mv a2,s2 -80006c74: 07c10593 addi a1,sp,124 -80006c78: e59fe0ef jal ra,80005ad0 -80006c7c: 1ac15503 lhu a0,428(sp) -80006c80: fff48493 addi s1,s1,-1 -80006c84: e40506e3 beqz a0,80006ad0 <_ldtoa_r+0x37c> -80006c88: 01012783 lw a5,16(sp) -80006c8c: 00012683 lw a3,0(sp) -80006c90: 00300713 li a4,3 -80006c94: 00f037b3 snez a5,a5 -80006c98: 40f007b3 neg a5,a5 -80006c9c: 00d7f793 andi a5,a5,13 -80006ca0: 02078793 addi a5,a5,32 -80006ca4: 12f10223 sb a5,292(sp) -80006ca8: 00412783 lw a5,4(sp) -80006cac: 00e69463 bne a3,a4,80006cb4 <_ldtoa_r+0x560> -80006cb0: 009787b3 add a5,a5,s1 -80006cb4: 02a00713 li a4,42 -80006cb8: 00078413 mv s0,a5 -80006cbc: 00f75463 bge a4,a5,80006cc4 <_ldtoa_r+0x570> -80006cc0: 02a00413 li s0,42 -80006cc4: 00a00713 li a4,10 -80006cc8: 4ee50263 beq a0,a4,800071ac <_ldtoa_r+0xa58> -80006ccc: 03050513 addi a0,a0,48 -80006cd0: 02e00713 li a4,46 -80006cd4: 12a102a3 sb a0,293(sp) -80006cd8: 12e10323 sb a4,294(sp) -80006cdc: 1e07c2e3 bltz a5,800076c0 <_ldtoa_r+0xf6c> -80006ce0: 12710793 addi a5,sp,295 -80006ce4: 00f12823 sw a5,16(sp) -80006ce8: 00000c13 li s8,0 -80006cec: 00912e23 sw s1,28(sp) -80006cf0: 000c0493 mv s1,s8 -80006cf4: 00090c13 mv s8,s2 -80006cf8: 01012903 lw s2,16(sp) -80006cfc: 0b410c93 addi s9,sp,180 -80006d00: 09410d93 addi s11,sp,148 -80006d04: 07e10b93 addi s7,sp,126 -80006d08: 0b610d13 addi s10,sp,182 -80006d0c: 00000713 li a4,0 -80006d10: 000d8613 mv a2,s11 -80006d14: 01c0006f j 80006d30 <_ldtoa_r+0x5dc> -80006d18: 00171713 slli a4,a4,0x1 -80006d1c: 00f61023 sh a5,0(a2) # 8000 <_start-0x7fff8000> -80006d20: 01071713 slli a4,a4,0x10 -80006d24: ffe60613 addi a2,a2,-2 -80006d28: 01075713 srli a4,a4,0x10 -80006d2c: 05760463 beq a2,s7,80006d74 <_ldtoa_r+0x620> -80006d30: 00065783 lhu a5,0(a2) -80006d34: 01079593 slli a1,a5,0x10 -80006d38: 4105d593 srai a1,a1,0x10 -80006d3c: 00179793 slli a5,a5,0x1 -80006d40: 0005d463 bgez a1,80006d48 <_ldtoa_r+0x5f4> -80006d44: 00176713 ori a4,a4,1 -80006d48: 01079793 slli a5,a5,0x10 -80006d4c: 0107d793 srli a5,a5,0x10 -80006d50: 00277593 andi a1,a4,2 -80006d54: 0017e513 ori a0,a5,1 -80006d58: fc0580e3 beqz a1,80006d18 <_ldtoa_r+0x5c4> -80006d5c: 00171713 slli a4,a4,0x1 -80006d60: 00a61023 sh a0,0(a2) -80006d64: 01071713 slli a4,a4,0x10 -80006d68: ffe60613 addi a2,a2,-2 -80006d6c: 01075713 srli a4,a4,0x10 -80006d70: fd7610e3 bne a2,s7,80006d30 <_ldtoa_r+0x5dc> -80006d74: 000c8713 mv a4,s9 -80006d78: 07c10793 addi a5,sp,124 -80006d7c: 0007d603 lhu a2,0(a5) -80006d80: 00278793 addi a5,a5,2 -80006d84: 00270713 addi a4,a4,2 -80006d88: fec71f23 sh a2,-2(a4) -80006d8c: ffb798e3 bne a5,s11,80006d7c <_ldtoa_r+0x628> -80006d90: 0c011623 sh zero,204(sp) -80006d94: 00000713 li a4,0 -80006d98: 0cc10613 addi a2,sp,204 -80006d9c: 01c0006f j 80006db8 <_ldtoa_r+0x664> -80006da0: 00171713 slli a4,a4,0x1 -80006da4: 00f61023 sh a5,0(a2) -80006da8: 01071713 slli a4,a4,0x10 -80006dac: ffe60613 addi a2,a2,-2 -80006db0: 01075713 srli a4,a4,0x10 -80006db4: 05a60463 beq a2,s10,80006dfc <_ldtoa_r+0x6a8> -80006db8: 00065783 lhu a5,0(a2) -80006dbc: 01079593 slli a1,a5,0x10 -80006dc0: 4105d593 srai a1,a1,0x10 -80006dc4: 00179793 slli a5,a5,0x1 -80006dc8: 0005d463 bgez a1,80006dd0 <_ldtoa_r+0x67c> -80006dcc: 00176713 ori a4,a4,1 -80006dd0: 01079793 slli a5,a5,0x10 -80006dd4: 0107d793 srli a5,a5,0x10 -80006dd8: 00277593 andi a1,a4,2 -80006ddc: 0017e513 ori a0,a5,1 -80006de0: fc0580e3 beqz a1,80006da0 <_ldtoa_r+0x64c> -80006de4: 00171713 slli a4,a4,0x1 -80006de8: 00a61023 sh a0,0(a2) -80006dec: 01071713 slli a4,a4,0x10 -80006df0: ffe60613 addi a2,a2,-2 -80006df4: 01075713 srli a4,a4,0x10 -80006df8: fda610e3 bne a2,s10,80006db8 <_ldtoa_r+0x664> -80006dfc: 00000713 li a4,0 -80006e00: 0cc10613 addi a2,sp,204 -80006e04: 01c0006f j 80006e20 <_ldtoa_r+0x6cc> -80006e08: 00171713 slli a4,a4,0x1 -80006e0c: 00f61023 sh a5,0(a2) -80006e10: 01071713 slli a4,a4,0x10 -80006e14: ffe60613 addi a2,a2,-2 -80006e18: 01075713 srli a4,a4,0x10 -80006e1c: 05a60463 beq a2,s10,80006e64 <_ldtoa_r+0x710> -80006e20: 00065783 lhu a5,0(a2) -80006e24: 01079593 slli a1,a5,0x10 -80006e28: 4105d593 srai a1,a1,0x10 -80006e2c: 00179793 slli a5,a5,0x1 -80006e30: 0005d463 bgez a1,80006e38 <_ldtoa_r+0x6e4> -80006e34: 00176713 ori a4,a4,1 -80006e38: 01079793 slli a5,a5,0x10 -80006e3c: 0107d793 srli a5,a5,0x10 -80006e40: 00277593 andi a1,a4,2 -80006e44: 0017e513 ori a0,a5,1 -80006e48: fc0580e3 beqz a1,80006e08 <_ldtoa_r+0x6b4> -80006e4c: 00171713 slli a4,a4,0x1 -80006e50: 00a61023 sh a0,0(a2) -80006e54: 01071713 slli a4,a4,0x10 -80006e58: ffe60613 addi a2,a2,-2 -80006e5c: 01075713 srli a4,a4,0x10 -80006e60: fda610e3 bne a2,s10,80006e20 <_ldtoa_r+0x6cc> -80006e64: 00000593 li a1,0 -80006e68: 000d8613 mv a2,s11 -80006e6c: 0cc10713 addi a4,sp,204 -80006e70: 00065503 lhu a0,0(a2) -80006e74: 00075783 lhu a5,0(a4) -80006e78: ffe60613 addi a2,a2,-2 -80006e7c: ffe70713 addi a4,a4,-2 -80006e80: 00a787b3 add a5,a5,a0 -80006e84: 00b787b3 add a5,a5,a1 -80006e88: 0107d593 srli a1,a5,0x10 -80006e8c: 00f61123 sh a5,2(a2) -80006e90: 0015f593 andi a1,a1,1 -80006e94: fda71ee3 bne a4,s10,80006e70 <_ldtoa_r+0x71c> -80006e98: 000c0613 mv a2,s8 -80006e9c: 07c10593 addi a1,sp,124 -80006ea0: 09810513 addi a0,sp,152 -80006ea4: c2dfe0ef jal ra,80005ad0 -80006ea8: 1ac15783 lhu a5,428(sp) -80006eac: 00990733 add a4,s2,s1 -80006eb0: 00148493 addi s1,s1,1 -80006eb4: 03078613 addi a2,a5,48 -80006eb8: 00c70023 sb a2,0(a4) -80006ebc: e49458e3 bge s0,s1,80006d0c <_ldtoa_r+0x5b8> -80006ec0: fff44513 not a0,s0 -80006ec4: 01012703 lw a4,16(sp) -80006ec8: 41f55513 srai a0,a0,0x1f -80006ecc: 00a47533 and a0,s0,a0 -80006ed0: 01c12483 lw s1,28(sp) -80006ed4: 00150913 addi s2,a0,1 -80006ed8: 01270933 add s2,a4,s2 -80006edc: 00a70c33 add s8,a4,a0 -80006ee0: 00400713 li a4,4 -80006ee4: 04f75e63 bge a4,a5,80006f40 <_ldtoa_r+0x7ec> -80006ee8: 00500713 li a4,5 -80006eec: 00e780e3 beq a5,a4,800076ec <_ldtoa_r+0xf98> -80006ef0: ffe94783 lbu a5,-2(s2) -80006ef4: ffe90713 addi a4,s2,-2 -80006ef8: 07f7f793 andi a5,a5,127 -80006efc: 78044463 bltz s0,80007684 <_ldtoa_r+0xf30> -80006f00: 02e00693 li a3,46 -80006f04: 03800613 li a2,56 -80006f08: 03000593 li a1,48 -80006f0c: 00d78e63 beq a5,a3,80006f28 <_ldtoa_r+0x7d4> -80006f10: 78f65263 bge a2,a5,80007694 <_ldtoa_r+0xf40> -80006f14: fff74783 lbu a5,-1(a4) -80006f18: 00b70023 sb a1,0(a4) -80006f1c: fff70713 addi a4,a4,-1 -80006f20: 07f7f793 andi a5,a5,127 -80006f24: fe9ff06f j 80006f0c <_ldtoa_r+0x7b8> -80006f28: fff74783 lbu a5,-1(a4) -80006f2c: 03800693 li a3,56 -80006f30: 00f6f4e3 bgeu a3,a5,80007738 <_ldtoa_r+0xfe4> -80006f34: 03100793 li a5,49 -80006f38: 00148493 addi s1,s1,1 -80006f3c: fef70fa3 sb a5,-1(a4) -80006f40: 800155b7 lui a1,0x80015 -80006f44: 00048613 mv a2,s1 -80006f48: e1058593 addi a1,a1,-496 # 80014e10 <__BSS_END__+0xffffe1e0> -80006f4c: 000c0513 mv a0,s8 -80006f50: 069020ef jal ra,800097b8 -80006f54: 07215783 lhu a5,114(sp) -80006f58: 01412703 lw a4,20(sp) -80006f5c: 16912823 sw s1,368(sp) -80006f60: fff7c793 not a5,a5 -80006f64: 16e12223 sw a4,356(sp) -80006f68: 01179713 slli a4,a5,0x11 -80006f6c: 00071e63 bnez a4,80006f88 <_ldtoa_r+0x834> -80006f70: 00098513 mv a0,s3 -80006f74: b9cfe0ef jal ra,80005310 -80006f78: 22051063 bnez a0,80007198 <_ldtoa_r+0xa44> -80006f7c: 00098513 mv a0,s3 -80006f80: 8ccfe0ef jal ra,8000504c -80006f84: 20051a63 bnez a0,80007198 <_ldtoa_r+0xa44> -80006f88: 00c12683 lw a3,12(sp) -80006f8c: 12414703 lbu a4,292(sp) -80006f90: 00148793 addi a5,s1,1 -80006f94: 00f6a023 sw a5,0(a3) -80006f98: 000a8793 mv a5,s5 -80006f9c: 02070a63 beqz a4,80006fd0 <_ldtoa_r+0x87c> -80006fa0: 02e00693 li a3,46 -80006fa4: 1cd70c63 beq a4,a3,8000717c <_ldtoa_r+0xa28> -80006fa8: 0017c703 lbu a4,1(a5) -80006fac: 00178793 addi a5,a5,1 -80006fb0: fe071ae3 bnez a4,80006fa4 <_ldtoa_r+0x850> -80006fb4: 04500693 li a3,69 -80006fb8: 00fae663 bltu s5,a5,80006fc4 <_ldtoa_r+0x870> -80006fbc: 0140006f j 80006fd0 <_ldtoa_r+0x87c> -80006fc0: 01578863 beq a5,s5,80006fd0 <_ldtoa_r+0x87c> -80006fc4: fff7c703 lbu a4,-1(a5) -80006fc8: fff78793 addi a5,a5,-1 -80006fcc: fed71ae3 bne a4,a3,80006fc0 <_ldtoa_r+0x86c> -80006fd0: 00078023 sb zero,0(a5) -80006fd4: 000a8793 mv a5,s5 -80006fd8: 02000693 li a3,32 -80006fdc: 02d00613 li a2,45 -80006fe0: 0007c703 lbu a4,0(a5) -80006fe4: 00d70463 beq a4,a3,80006fec <_ldtoa_r+0x898> -80006fe8: 00c71663 bne a4,a2,80006ff4 <_ldtoa_r+0x8a0> -80006fec: 00178793 addi a5,a5,1 -80006ff0: ff1ff06f j 80006fe0 <_ldtoa_r+0x88c> -80006ff4: 000a8413 mv s0,s5 -80006ff8: 00c0006f j 80007004 <_ldtoa_r+0x8b0> -80006ffc: 0007c703 lbu a4,0(a5) -80007000: 00068413 mv s0,a3 -80007004: 00e40023 sb a4,0(s0) -80007008: 00140693 addi a3,s0,1 -8000700c: 00178793 addi a5,a5,1 -80007010: fe0716e3 bnez a4,80006ffc <_ldtoa_r+0x8a8> -80007014: 00012683 lw a3,0(sp) -80007018: 00200793 li a5,2 -8000701c: fff44703 lbu a4,-1(s0) -80007020: 12f68663 beq a3,a5,8000714c <_ldtoa_r+0x9f8> -80007024: 00412783 lw a5,4(sp) -80007028: 00078693 mv a3,a5 -8000702c: 0097d463 bge a5,s1,80007034 <_ldtoa_r+0x8e0> -80007030: 00048693 mv a3,s1 -80007034: 03000793 li a5,48 -80007038: 02f71663 bne a4,a5,80007064 <_ldtoa_r+0x910> -8000703c: 415407b3 sub a5,s0,s5 -80007040: 02f6d263 bge a3,a5,80007064 <_ldtoa_r+0x910> -80007044: 03000613 li a2,48 -80007048: 0080006f j 80007050 <_ldtoa_r+0x8fc> -8000704c: 00e6dc63 bge a3,a4,80007064 <_ldtoa_r+0x910> -80007050: ffe44783 lbu a5,-2(s0) -80007054: fe040fa3 sb zero,-1(s0) -80007058: fff40413 addi s0,s0,-1 -8000705c: 41540733 sub a4,s0,s5 -80007060: fec786e3 beq a5,a2,8000704c <_ldtoa_r+0x8f8> -80007064: 00012703 lw a4,0(sp) -80007068: 00300793 li a5,3 -8000706c: 0af70263 beq a4,a5,80007110 <_ldtoa_r+0x9bc> -80007070: 00812783 lw a5,8(sp) -80007074: 040a2223 sw zero,68(s4) -80007078: 00978693 addi a3,a5,9 -8000707c: 01700793 li a5,23 -80007080: 0cd7f263 bgeu a5,a3,80007144 <_ldtoa_r+0x9f0> -80007084: 00100713 li a4,1 -80007088: 00400793 li a5,4 -8000708c: 00179793 slli a5,a5,0x1 -80007090: 01478613 addi a2,a5,20 -80007094: 00070593 mv a1,a4 -80007098: 00170713 addi a4,a4,1 -8000709c: fec6f8e3 bgeu a3,a2,8000708c <_ldtoa_r+0x938> -800070a0: 04ba2223 sw a1,68(s4) -800070a4: 000a0513 mv a0,s4 -800070a8: 52c010ef jal ra,800085d4 <_Balloc> -800070ac: 04aa2023 sw a0,64(s4) -800070b0: 000a8593 mv a1,s5 -800070b4: 00050493 mv s1,a0 -800070b8: 251020ef jal ra,80009b08 -800070bc: 01812783 lw a5,24(sp) -800070c0: 00078863 beqz a5,800070d0 <_ldtoa_r+0x97c> -800070c4: 41540433 sub s0,s0,s5 -800070c8: 00848433 add s0,s1,s0 -800070cc: 0087a023 sw s0,0(a5) -800070d0: 1ec12083 lw ra,492(sp) -800070d4: 1e812403 lw s0,488(sp) -800070d8: 1e012903 lw s2,480(sp) -800070dc: 1dc12983 lw s3,476(sp) -800070e0: 1d812a03 lw s4,472(sp) -800070e4: 1d412a83 lw s5,468(sp) -800070e8: 1d012b03 lw s6,464(sp) -800070ec: 1cc12b83 lw s7,460(sp) -800070f0: 1c812c03 lw s8,456(sp) -800070f4: 1c412c83 lw s9,452(sp) -800070f8: 1c012d03 lw s10,448(sp) -800070fc: 1bc12d83 lw s11,444(sp) -80007100: 00048513 mv a0,s1 -80007104: 1e412483 lw s1,484(sp) -80007108: 1f010113 addi sp,sp,496 -8000710c: 00008067 ret -80007110: 00412783 lw a5,4(sp) -80007114: 009784b3 add s1,a5,s1 -80007118: 5004c863 bltz s1,80007628 <_ldtoa_r+0xed4> -8000711c: 00c12783 lw a5,12(sp) -80007120: 00812703 lw a4,8(sp) -80007124: 0007a783 lw a5,0(a5) -80007128: 00f707b3 add a5,a4,a5 -8000712c: 00f12423 sw a5,8(sp) -80007130: 00812783 lw a5,8(sp) -80007134: 040a2223 sw zero,68(s4) -80007138: 00378693 addi a3,a5,3 -8000713c: 01700793 li a5,23 -80007140: f4d7e2e3 bltu a5,a3,80007084 <_ldtoa_r+0x930> -80007144: 00000593 li a1,0 -80007148: f5dff06f j 800070a4 <_ldtoa_r+0x950> -8000714c: 03000793 li a5,48 -80007150: f2f710e3 bne a4,a5,80007070 <_ldtoa_r+0x91c> -80007154: 415407b3 sub a5,s0,s5 -80007158: 00100693 li a3,1 -8000715c: eef6c4e3 blt a3,a5,80007044 <_ldtoa_r+0x8f0> -80007160: f11ff06f j 80007070 <_ldtoa_r+0x91c> -80007164: 00812483 lw s1,8(sp) -80007168: 00912223 sw s1,4(sp) -8000716c: 02a00793 li a5,42 -80007170: ec97d063 bge a5,s1,80006830 <_ldtoa_r+0xdc> -80007174: 00f12223 sw a5,4(sp) -80007178: eb8ff06f j 80006830 <_ldtoa_r+0xdc> -8000717c: 0007c703 lbu a4,0(a5) -80007180: e2070ae3 beqz a4,80006fb4 <_ldtoa_r+0x860> -80007184: 0017c703 lbu a4,1(a5) -80007188: 00178793 addi a5,a5,1 -8000718c: fee78fa3 sb a4,-1(a5) -80007190: fe071ae3 bnez a4,80007184 <_ldtoa_r+0xa30> -80007194: e21ff06f j 80006fb4 <_ldtoa_r+0x860> -80007198: 00c12703 lw a4,12(sp) -8000719c: 000027b7 lui a5,0x2 -800071a0: 70f78793 addi a5,a5,1807 # 270f <_start-0x7fffd8f1> -800071a4: 00f72023 sw a5,0(a4) -800071a8: e2dff06f j 80006fd4 <_ldtoa_r+0x880> -800071ac: 03100713 li a4,49 -800071b0: 12e102a3 sb a4,293(sp) -800071b4: 02e00713 li a4,46 -800071b8: 12e10323 sb a4,294(sp) -800071bc: 00148493 addi s1,s1,1 -800071c0: 2af05c63 blez a5,80007478 <_ldtoa_r+0xd24> -800071c4: 03000793 li a5,48 -800071c8: 12f103a3 sb a5,295(sp) -800071cc: 12810793 addi a5,sp,296 -800071d0: fff40413 addi s0,s0,-1 -800071d4: 00f12823 sw a5,16(sp) -800071d8: b11ff06f j 80006ce8 <_ldtoa_r+0x594> -800071dc: 0b410c93 addi s9,sp,180 -800071e0: 000c8713 mv a4,s9 -800071e4: 07c10793 addi a5,sp,124 -800071e8: 09010613 addi a2,sp,144 -800071ec: 0007d683 lhu a3,0(a5) -800071f0: 00278793 addi a5,a5,2 -800071f4: 00270713 addi a4,a4,2 -800071f8: fed71f23 sh a3,-2(a4) -800071fc: fec798e3 bne a5,a2,800071ec <_ldtoa_r+0xa98> -80007200: 000047b7 lui a5,0x4 -80007204: 08e78793 addi a5,a5,142 # 408e <_start-0x7fffbf72> -80007208: 0cf11323 sh a5,198(sp) -8000720c: 000087b7 lui a5,0x8 -80007210: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80007214: 00f12e23 sw a5,28(sp) -80007218: ffffc7b7 lui a5,0xffffc -8000721c: 12410a93 addi s5,sp,292 -80007220: 0d010413 addi s0,sp,208 -80007224: 01000e13 li t3,16 -80007228: 0c8d8313 addi t1,s11,200 -8000722c: 00278793 addi a5,a5,2 # ffffc002 <__BSS_END__+0x7ffe53d2> -80007230: 03412423 sw s4,40(sp) -80007234: 03512223 sw s5,36(sp) -80007238: 00000493 li s1,0 -8000723c: 000c8a93 mv s5,s9 -80007240: 16010913 addi s2,sp,352 -80007244: 00040c93 mv s9,s0 -80007248: 0aa10b93 addi s7,sp,170 -8000724c: 02f12023 sw a5,32(sp) -80007250: 000e0a13 mv s4,t3 -80007254: 00030413 mv s0,t1 -80007258: 00090693 mv a3,s2 -8000725c: 09810613 addi a2,sp,152 -80007260: 000a8593 mv a1,s5 -80007264: 00040513 mv a0,s0 -80007268: e99fe0ef jal ra,80006100 -8000726c: 04c10713 addi a4,sp,76 -80007270: 09810793 addi a5,sp,152 -80007274: 0007d683 lhu a3,0(a5) -80007278: 00278793 addi a5,a5,2 -8000727c: 00270713 addi a4,a4,2 -80007280: fed71f23 sh a3,-2(a4) -80007284: ffa798e3 bne a5,s10,80007274 <_ldtoa_r+0xb20> -80007288: 01c12783 lw a5,28(sp) -8000728c: 05e15583 lhu a1,94(sp) -80007290: 00f5f633 and a2,a1,a5 -80007294: 02012783 lw a5,32(sp) -80007298: 00f60533 add a0,a2,a5 -8000729c: 3aa05063 blez a0,8000763c <_ldtoa_r+0xee8> -800072a0: 09000613 li a2,144 -800072a4: 40a60633 sub a2,a2,a0 -800072a8: 000c8713 mv a4,s9 -800072ac: 04c10793 addi a5,sp,76 -800072b0: 0007d683 lhu a3,0(a5) -800072b4: 00278793 addi a5,a5,2 -800072b8: 00270713 addi a4,a4,2 -800072bc: fed71f23 sh a3,-2(a4) -800072c0: ff3798e3 bne a5,s3,800072b0 <_ldtoa_r+0xb5c> -800072c4: 06c05463 blez a2,8000732c <_ldtoa_r+0xbd8> -800072c8: 00f00793 li a5,15 -800072cc: 000c8713 mv a4,s9 -800072d0: 02c7dc63 bge a5,a2,80007308 <_ldtoa_r+0xbb4> -800072d4: ff060613 addi a2,a2,-16 -800072d8: 00465693 srli a3,a2,0x4 -800072dc: 00168713 addi a4,a3,1 -800072e0: 00171713 slli a4,a4,0x1 -800072e4: 00ec8733 add a4,s9,a4 -800072e8: 000c8793 mv a5,s9 -800072ec: 00278793 addi a5,a5,2 -800072f0: fe079f23 sh zero,-2(a5) -800072f4: fee79ce3 bne a5,a4,800072ec <_ldtoa_r+0xb98> -800072f8: 08000613 li a2,128 -800072fc: 40a60633 sub a2,a2,a0 -80007300: 00469693 slli a3,a3,0x4 -80007304: 40d60633 sub a2,a2,a3 -80007308: 00161613 slli a2,a2,0x1 -8000730c: 00cd8633 add a2,s11,a2 -80007310: 00075783 lhu a5,0(a4) -80007314: 23065683 lhu a3,560(a2) -80007318: 00d7f7b3 and a5,a5,a3 -8000731c: 00f71023 sh a5,0(a4) -80007320: 01059593 slli a1,a1,0x10 -80007324: 4105d593 srai a1,a1,0x10 -80007328: 1605c063 bltz a1,80007488 <_ldtoa_r+0xd34> -8000732c: 09810793 addi a5,sp,152 -80007330: 000c8713 mv a4,s9 -80007334: 0007d603 lhu a2,0(a5) -80007338: 00075683 lhu a3,0(a4) -8000733c: 00278793 addi a5,a5,2 -80007340: 00270713 addi a4,a4,2 -80007344: 02d61463 bne a2,a3,8000736c <_ldtoa_r+0xc18> -80007348: fefb96e3 bne s7,a5,80007334 <_ldtoa_r+0xbe0> -8000734c: 000a8713 mv a4,s5 -80007350: 09810793 addi a5,sp,152 -80007354: 0007d683 lhu a3,0(a5) -80007358: 00278793 addi a5,a5,2 -8000735c: 00270713 addi a4,a4,2 -80007360: fed71f23 sh a3,-2(a4) -80007364: ffa798e3 bne a5,s10,80007354 <_ldtoa_r+0xc00> -80007368: 014484b3 add s1,s1,s4 -8000736c: 01440413 addi s0,s0,20 -80007370: 12cd8793 addi a5,s11,300 -80007374: 001a5a13 srli s4,s4,0x1 -80007378: eef410e3 bne s0,a5,80007258 <_ldtoa_r+0xb04> -8000737c: 0c615783 lhu a5,198(sp) -80007380: 08e15703 lhu a4,142(sp) -80007384: 000c8413 mv s0,s9 -80007388: 02812a03 lw s4,40(sp) -8000738c: 00e787b3 add a5,a5,a4 -80007390: ffffc737 lui a4,0xffffc -80007394: 000a8c93 mv s9,s5 -80007398: f7270713 addi a4,a4,-142 # ffffbf72 <__BSS_END__+0x7ffe5342> -8000739c: 02412a83 lw s5,36(sp) -800073a0: 00e787b3 add a5,a5,a4 -800073a4: 0cf11323 sh a5,198(sp) -800073a8: 07c10713 addi a4,sp,124 -800073ac: 000c8793 mv a5,s9 -800073b0: 0c810613 addi a2,sp,200 -800073b4: 0007d683 lhu a3,0(a5) -800073b8: 00278793 addi a5,a5,2 -800073bc: 00270713 addi a4,a4,2 -800073c0: fed71f23 sh a3,-2(a4) -800073c4: fec798e3 bne a5,a2,800073b4 <_ldtoa_r+0xc60> -800073c8: 00000713 li a4,0 -800073cc: 09810793 addi a5,sp,152 -800073d0: 0080006f j 800073d8 <_ldtoa_r+0xc84> -800073d4: 000c5703 lhu a4,0(s8) -800073d8: 00278793 addi a5,a5,2 -800073dc: fee79f23 sh a4,-2(a5) -800073e0: 002c0c13 addi s8,s8,2 -800073e4: ffa798e3 bne a5,s10,800073d4 <_ldtoa_r+0xc80> -800073e8: 028d8d13 addi s10,s11,40 -800073ec: 00001c37 lui s8,0x1 -800073f0: 118d8d93 addi s11,s11,280 -800073f4: 0100006f j 80007404 <_ldtoa_r+0xcb0> -800073f8: 001c5c13 srli s8,s8,0x1 -800073fc: 29bd0063 beq s10,s11,8000767c <_ldtoa_r+0xf28> -80007400: 014d0d13 addi s10,s10,20 -80007404: 000c8593 mv a1,s9 -80007408: 000d8513 mv a0,s11 -8000740c: de9fd0ef jal ra,800051f4 -80007410: 00050793 mv a5,a0 -80007414: 000c8593 mv a1,s9 -80007418: 000d0513 mv a0,s10 -8000741c: 26f04063 bgtz a5,8000767c <_ldtoa_r+0xf28> -80007420: dd5fd0ef jal ra,800051f4 -80007424: fca04ae3 bgtz a0,800073f8 <_ldtoa_r+0xca4> -80007428: 00090693 mv a3,s2 -8000742c: 000c8613 mv a2,s9 -80007430: 000c8593 mv a1,s9 -80007434: 000d0513 mv a0,s10 -80007438: cc9fe0ef jal ra,80006100 -8000743c: 09810613 addi a2,sp,152 -80007440: 00090693 mv a3,s2 -80007444: 00060593 mv a1,a2 -80007448: 000d0513 mv a0,s10 -8000744c: 89dfe0ef jal ra,80005ce8 -80007450: 018484b3 add s1,s1,s8 -80007454: fa5ff06f j 800073f8 <_ldtoa_r+0xca4> -80007458: 12410a93 addi s5,sp,292 -8000745c: 800155b7 lui a1,0x80015 -80007460: dec58593 addi a1,a1,-532 # 80014dec <__BSS_END__+0xffffe1bc> -80007464: 000a8513 mv a0,s5 -80007468: 000024b7 lui s1,0x2 -8000746c: 34c020ef jal ra,800097b8 -80007470: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -80007474: ae1ff06f j 80006f54 <_ldtoa_r+0x800> -80007478: 12710c13 addi s8,sp,295 -8000747c: ac0792e3 bnez a5,80006f40 <_ldtoa_r+0x7ec> -80007480: 01812823 sw s8,16(sp) -80007484: 865ff06f j 80006ce8 <_ldtoa_r+0x594> -80007488: 04c10793 addi a5,sp,76 -8000748c: 000c8713 mv a4,s9 -80007490: 00c0006f j 8000749c <_ldtoa_r+0xd48> -80007494: 05e10693 addi a3,sp,94 -80007498: e8f68ae3 beq a3,a5,8000732c <_ldtoa_r+0xbd8> -8000749c: 0007d603 lhu a2,0(a5) -800074a0: 00075683 lhu a3,0(a4) -800074a4: 00278793 addi a5,a5,2 -800074a8: 00270713 addi a4,a4,2 -800074ac: fed604e3 beq a2,a3,80007494 <_ldtoa_r+0xd40> -800074b0: 0e215783 lhu a5,226(sp) -800074b4: 01c12703 lw a4,28(sp) -800074b8: 00f777b3 and a5,a4,a5 -800074bc: 00e79e63 bne a5,a4,800074d8 <_ldtoa_r+0xd84> -800074c0: 000c8513 mv a0,s9 -800074c4: b89fd0ef jal ra,8000504c -800074c8: e60512e3 bnez a0,8000732c <_ldtoa_r+0xbd8> -800074cc: 000c8513 mv a0,s9 -800074d0: e41fd0ef jal ra,80005310 -800074d4: e4051ce3 bnez a0,8000732c <_ldtoa_r+0xbd8> -800074d8: 0ec10593 addi a1,sp,236 -800074dc: 000c0513 mv a0,s8 -800074e0: c1dfd0ef jal ra,800050fc -800074e4: 10810593 addi a1,sp,264 -800074e8: 000c8513 mv a0,s9 -800074ec: c11fd0ef jal ra,800050fc -800074f0: 0ec15603 lhu a2,236(sp) -800074f4: 10a15503 lhu a0,266(sp) -800074f8: 0ee15883 lhu a7,238(sp) -800074fc: fff64613 not a2,a2 -80007500: 01061613 slli a2,a2,0x10 -80007504: 01065613 srli a2,a2,0x10 -80007508: 0ec11623 sh a2,236(sp) -8000750c: 40a885b3 sub a1,a7,a0 -80007510: 00050693 mv a3,a0 -80007514: 06b05e63 blez a1,80007590 <_ldtoa_r+0xe3c> -80007518: 02412683 lw a3,36(sp) -8000751c: 10810713 addi a4,sp,264 -80007520: 12010793 addi a5,sp,288 -80007524: 00075583 lhu a1,0(a4) -80007528: 00270713 addi a4,a4,2 -8000752c: 00268693 addi a3,a3,2 -80007530: feb69f23 sh a1,-2(a3) -80007534: fef718e3 bne a4,a5,80007524 <_ldtoa_r+0xdd0> -80007538: 12011e23 sh zero,316(sp) -8000753c: 10810713 addi a4,sp,264 -80007540: 0ec10693 addi a3,sp,236 -80007544: 0080006f j 8000754c <_ldtoa_r+0xdf8> -80007548: 0006d603 lhu a2,0(a3) -8000754c: 00270713 addi a4,a4,2 -80007550: fec71f23 sh a2,-2(a4) -80007554: 00268693 addi a3,a3,2 -80007558: fef718e3 bne a4,a5,80007548 <_ldtoa_r+0xdf4> -8000755c: 02412783 lw a5,36(sp) -80007560: 12011023 sh zero,288(sp) -80007564: 0ec10713 addi a4,sp,236 -80007568: 13c10613 addi a2,sp,316 -8000756c: 0007d683 lhu a3,0(a5) -80007570: 00278793 addi a5,a5,2 -80007574: 00270713 addi a4,a4,2 -80007578: fed71f23 sh a3,-2(a4) -8000757c: fec798e3 bne a5,a2,8000756c <_ldtoa_r+0xe18> -80007580: 10a15683 lhu a3,266(sp) -80007584: 411505b3 sub a1,a0,a7 -80007588: 10011223 sh zero,260(sp) -8000758c: 00068513 mv a0,a3 -80007590: 2c058663 beqz a1,8000785c <_ldtoa_r+0x1108> -80007594: 02d12623 sw a3,44(sp) -80007598: f6f00793 li a5,-145 -8000759c: 06f5c863 blt a1,a5,8000760c <_ldtoa_r+0xeb8> -800075a0: 0ec10513 addi a0,sp,236 -800075a4: d89fd0ef jal ra,8000532c -800075a8: 02c12683 lw a3,44(sp) -800075ac: 00050593 mv a1,a0 -800075b0: 12010793 addi a5,sp,288 -800075b4: 10410513 addi a0,sp,260 -800075b8: 0ec15603 lhu a2,236(sp) -800075bc: 10815703 lhu a4,264(sp) -800075c0: 2ee60a63 beq a2,a4,800078b4 <_ldtoa_r+0x1160> -800075c4: 00000713 li a4,0 -800075c8: 00070613 mv a2,a4 -800075cc: 0007d703 lhu a4,0(a5) -800075d0: 00055803 lhu a6,0(a0) -800075d4: ffe78793 addi a5,a5,-2 -800075d8: 40c70733 sub a4,a4,a2 -800075dc: 41070733 sub a4,a4,a6 -800075e0: 01075613 srli a2,a4,0x10 -800075e4: 00e79123 sh a4,2(a5) -800075e8: 10a10713 addi a4,sp,266 -800075ec: 00167613 andi a2,a2,1 -800075f0: ffe50513 addi a0,a0,-2 -800075f4: fce79ce3 bne a5,a4,800075cc <_ldtoa_r+0xe78> -800075f8: 00100613 li a2,1 -800075fc: 00090793 mv a5,s2 -80007600: 04000713 li a4,64 -80007604: 10810513 addi a0,sp,264 -80007608: 8bcfe0ef jal ra,800056c4 -8000760c: 000c8593 mv a1,s9 -80007610: 10810513 addi a0,sp,264 -80007614: e24fe0ef jal ra,80005c38 -80007618: d15ff06f j 8000732c <_ldtoa_r+0xbd8> -8000761c: 00812783 lw a5,8(sp) -80007620: fff78493 addi s1,a5,-1 -80007624: b45ff06f j 80007168 <_ldtoa_r+0xa14> -80007628: 00c12783 lw a5,12(sp) -8000762c: 12010223 sb zero,292(sp) -80007630: 000a8413 mv s0,s5 -80007634: 0007a023 sw zero,0(a5) -80007638: af9ff06f j 80007130 <_ldtoa_r+0x9dc> -8000763c: 000c8793 mv a5,s9 -80007640: 0e410713 addi a4,sp,228 -80007644: 00278793 addi a5,a5,2 -80007648: fe079f23 sh zero,-2(a5) -8000764c: fee79ce3 bne a5,a4,80007644 <_ldtoa_r+0xef0> -80007650: cd1ff06f j 80007320 <_ldtoa_r+0xbcc> -80007654: 01012783 lw a5,16(sp) -80007658: 12410a93 addi s5,sp,292 -8000765c: 06078a63 beqz a5,800076d0 <_ldtoa_r+0xf7c> -80007660: 800155b7 lui a1,0x80015 -80007664: df458593 addi a1,a1,-524 # 80014df4 <__BSS_END__+0xffffe1c4> -80007668: 000a8513 mv a0,s5 -8000766c: 000024b7 lui s1,0x2 -80007670: 148020ef jal ra,800097b8 -80007674: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -80007678: 8ddff06f j 80006f54 <_ldtoa_r+0x800> -8000767c: 0e810b93 addi s7,sp,232 -80007680: bd8ff06f j 80006a58 <_ldtoa_r+0x304> -80007684: 03100793 li a5,49 -80007688: fef90f23 sb a5,-2(s2) -8000768c: 00148493 addi s1,s1,1 -80007690: 8b1ff06f j 80006f40 <_ldtoa_r+0x7ec> -80007694: 00178793 addi a5,a5,1 -80007698: 00f70023 sb a5,0(a4) -8000769c: 8a5ff06f j 80006f40 <_ldtoa_r+0x7ec> -800076a0: 12410a93 addi s5,sp,292 -800076a4: 800155b7 lui a1,0x80015 -800076a8: e0c58593 addi a1,a1,-500 # 80014e0c <__BSS_END__+0xffffe1dc> -800076ac: 000a8513 mv a0,s5 -800076b0: 000024b7 lui s1,0x2 -800076b4: 104020ef jal ra,800097b8 -800076b8: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -800076bc: 899ff06f j 80006f54 <_ldtoa_r+0x800> -800076c0: 1ac15783 lhu a5,428(sp) -800076c4: 12610c13 addi s8,sp,294 -800076c8: 12710913 addi s2,sp,295 -800076cc: 815ff06f j 80006ee0 <_ldtoa_r+0x78c> -800076d0: 800155b7 lui a1,0x80015 -800076d4: e0058593 addi a1,a1,-512 # 80014e00 <__BSS_END__+0xffffe1d0> -800076d8: 000a8513 mv a0,s5 -800076dc: 000024b7 lui s1,0x2 -800076e0: 0d8020ef jal ra,800097b8 -800076e4: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -800076e8: 86dff06f j 80006f54 <_ldtoa_r+0x800> -800076ec: 09810593 addi a1,sp,152 -800076f0: 07c10513 addi a0,sp,124 -800076f4: d44fe0ef jal ra,80005c38 -800076f8: e14b0593 addi a1,s6,-492 -800076fc: 09810513 addi a0,sp,152 -80007700: af5fd0ef jal ra,800051f4 -80007704: fe051663 bnez a0,80006ef0 <_ldtoa_r+0x79c> -80007708: 82044ce3 bltz s0,80006f40 <_ldtoa_r+0x7ec> -8000770c: ffe94783 lbu a5,-2(s2) -80007710: fd278713 addi a4,a5,-46 -80007714: 00173713 seqz a4,a4 -80007718: fff74713 not a4,a4 -8000771c: 00ec0733 add a4,s8,a4 -80007720: 00074703 lbu a4,0(a4) -80007724: 00177713 andi a4,a4,1 -80007728: 80070ce3 beqz a4,80006f40 <_ldtoa_r+0x7ec> -8000772c: ffe90713 addi a4,s2,-2 -80007730: 07f7f793 andi a5,a5,127 -80007734: fccff06f j 80006f00 <_ldtoa_r+0x7ac> -80007738: 00178793 addi a5,a5,1 -8000773c: fef70fa3 sb a5,-1(a4) -80007740: 801ff06f j 80006f40 <_ldtoa_r+0x7ec> -80007744: 0d010413 addi s0,sp,208 -80007748: 00040593 mv a1,s0 -8000774c: 07c10513 addi a0,sp,124 -80007750: 00004cb7 lui s9,0x4 -80007754: 9a9fd0ef jal ra,800050fc -80007758: 00000493 li s1,0 -8000775c: 0e810b93 addi s7,sp,232 -80007760: 0cc10913 addi s2,sp,204 -80007764: 0d210a93 addi s5,sp,210 -80007768: ffec8c93 addi s9,s9,-2 # 3ffe <_start-0x7fffc002> -8000776c: 0e815783 lhu a5,232(sp) -80007770: 0077f793 andi a5,a5,7 -80007774: 0c079a63 bnez a5,80007848 <_ldtoa_r+0x10f4> -80007778: 0b410713 addi a4,sp,180 -8000777c: 00040793 mv a5,s0 -80007780: 0007d683 lhu a3,0(a5) -80007784: 00278793 addi a5,a5,2 -80007788: 00270713 addi a4,a4,2 -8000778c: fed71f23 sh a3,-2(a4) -80007790: ff7798e3 bne a5,s7,80007780 <_ldtoa_r+0x102c> -80007794: 0b410513 addi a0,sp,180 -80007798: 0c011623 sh zero,204(sp) -8000779c: f40fd0ef jal ra,80004edc -800077a0: 0b410513 addi a0,sp,180 -800077a4: f38fd0ef jal ra,80004edc -800077a8: 00000613 li a2,0 -800077ac: 00090693 mv a3,s2 -800077b0: 000b8713 mv a4,s7 -800077b4: 0006d583 lhu a1,0(a3) -800077b8: 00075783 lhu a5,0(a4) -800077bc: ffe68693 addi a3,a3,-2 -800077c0: ffe70713 addi a4,a4,-2 -800077c4: 00b787b3 add a5,a5,a1 -800077c8: 00c787b3 add a5,a5,a2 -800077cc: 0107d613 srli a2,a5,0x10 -800077d0: 00f69123 sh a5,2(a3) -800077d4: 00167613 andi a2,a2,1 -800077d8: fd571ee3 bne a4,s5,800077b4 <_ldtoa_r+0x1060> -800077dc: 0b615783 lhu a5,182(sp) -800077e0: 0b815703 lhu a4,184(sp) -800077e4: 00378793 addi a5,a5,3 -800077e8: 0af11b23 sh a5,182(sp) -800077ec: 02070063 beqz a4,8000780c <_ldtoa_r+0x10b8> -800077f0: 0b410513 addi a0,sp,180 -800077f4: ee8fd0ef jal ra,80004edc -800077f8: 0b615783 lhu a5,182(sp) -800077fc: 0b815703 lhu a4,184(sp) -80007800: 00178793 addi a5,a5,1 -80007804: 0af11b23 sh a5,182(sp) -80007808: fe0714e3 bnez a4,800077f0 <_ldtoa_r+0x109c> -8000780c: 0cc15783 lhu a5,204(sp) -80007810: 02079c63 bnez a5,80007848 <_ldtoa_r+0x10f4> -80007814: 0b615783 lhu a5,182(sp) -80007818: 02fce863 bltu s9,a5,80007848 <_ldtoa_r+0x10f4> -8000781c: 00040713 mv a4,s0 -80007820: 0b410793 addi a5,sp,180 -80007824: 0007d683 lhu a3,0(a5) -80007828: 00278793 addi a5,a5,2 -8000782c: 00270713 addi a4,a4,2 -80007830: fed71f23 sh a3,-2(a4) -80007834: ff2798e3 bne a5,s2,80007824 <_ldtoa_r+0x10d0> -80007838: 0e011423 sh zero,232(sp) -8000783c: fff48493 addi s1,s1,-1 -80007840: fd500793 li a5,-43 -80007844: f2f494e3 bne s1,a5,8000776c <_ldtoa_r+0x1018> -80007848: 07c10593 addi a1,sp,124 -8000784c: 00040513 mv a0,s0 -80007850: be8fe0ef jal ra,80005c38 -80007854: 16010913 addi s2,sp,352 -80007858: 8f4ff06f j 8000694c <_ldtoa_r+0x1f8> -8000785c: 10c10713 addi a4,sp,268 -80007860: 0f010793 addi a5,sp,240 -80007864: 0007d883 lhu a7,0(a5) -80007868: 00075603 lhu a2,0(a4) -8000786c: 00278793 addi a5,a5,2 -80007870: 00270713 addi a4,a4,2 -80007874: 02c89863 bne a7,a2,800078a4 <_ldtoa_r+0x1150> -80007878: 10610613 addi a2,sp,262 -8000787c: fec794e3 bne a5,a2,80007864 <_ldtoa_r+0x1110> -80007880: 0ec15703 lhu a4,236(sp) -80007884: 10815783 lhu a5,264(sp) -80007888: 06f70263 beq a4,a5,800078ec <_ldtoa_r+0x1198> -8000788c: 000c8793 mv a5,s9 -80007890: 0e410713 addi a4,sp,228 -80007894: 00278793 addi a5,a5,2 -80007898: fe079f23 sh zero,-2(a5) -8000789c: fee79ce3 bne a5,a4,80007894 <_ldtoa_r+0x1140> -800078a0: a8dff06f j 8000732c <_ldtoa_r+0xbd8> -800078a4: 0d166663 bltu a2,a7,80007970 <_ldtoa_r+0x121c> +800066a4 <_ldtoa_r>: +800066a4: 00c5a883 lw a7,12(a1) +800066a8: e1010113 addi sp,sp,-496 +800066ac: 0005ae83 lw t4,0(a1) +800066b0: 0045ae03 lw t3,4(a1) +800066b4: 0085a303 lw t1,8(a1) +800066b8: 03112e23 sw a7,60(sp) +800066bc: 04052583 lw a1,64(a0) +800066c0: fff00893 li a7,-1 +800066c4: 17112023 sw a7,352(sp) +800066c8: 09000893 li a7,144 +800066cc: 1e812423 sw s0,488(sp) +800066d0: 1d412c23 sw s4,472(sp) +800066d4: 1e112623 sw ra,492(sp) +800066d8: 1e912223 sw s1,484(sp) +800066dc: 1f212023 sw s2,480(sp) +800066e0: 1d312e23 sw s3,476(sp) +800066e4: 1d512a23 sw s5,468(sp) +800066e8: 1d612823 sw s6,464(sp) +800066ec: 1d712623 sw s7,460(sp) +800066f0: 1d812423 sw s8,456(sp) +800066f4: 1d912223 sw s9,452(sp) +800066f8: 1da12023 sw s10,448(sp) +800066fc: 1bb12e23 sw s11,444(sp) +80006700: 03d12823 sw t4,48(sp) +80006704: 03c12a23 sw t3,52(sp) +80006708: 02612c23 sw t1,56(sp) +8000670c: 17112223 sw a7,356(sp) +80006710: 00c12023 sw a2,0(sp) +80006714: 00d12423 sw a3,8(sp) +80006718: 00e12623 sw a4,12(sp) +8000671c: 01012c23 sw a6,24(sp) +80006720: 00050a13 mv s4,a0 +80006724: 00078413 mv s0,a5 +80006728: 02058063 beqz a1,80006748 <_ldtoa_r+0xa4> +8000672c: 04452703 lw a4,68(a0) +80006730: 00100793 li a5,1 +80006734: 00e797b3 sll a5,a5,a4 +80006738: 00e5a223 sw a4,4(a1) +8000673c: 00f5a423 sw a5,8(a1) +80006740: 661010ef jal ra,800085a0 <_Bfree> +80006744: 040a2023 sw zero,64(s4) +80006748: 06010993 addi s3,sp,96 +8000674c: 00098593 mv a1,s3 +80006750: 03010513 addi a0,sp,48 +80006754: e0dff0ef jal ra,80006560 +80006758: 00098513 mv a0,s3 +8000675c: 8b1fe0ef jal ra,8000500c +80006760: 00012703 lw a4,0(sp) +80006764: 00a03533 snez a0,a0 +80006768: 00a42023 sw a0,0(s0) +8000676c: 00300793 li a5,3 +80006770: 14f702e3 beq a4,a5,800070b4 <_ldtoa_r+0xa10> +80006774: 01400793 li a5,20 +80006778: 00f12223 sw a5,4(sp) +8000677c: 5e0718e3 bnez a4,8000756c <_ldtoa_r+0xec8> +80006780: 07215783 lhu a5,114(sp) +80006784: 16412703 lw a4,356(sp) +80006788: fff7c793 not a5,a5 +8000678c: 00e12a23 sw a4,20(sp) +80006790: 01179713 slli a4,a5,0x11 +80006794: 00071863 bnez a4,800067a4 <_ldtoa_r+0x100> +80006798: 00098513 mv a0,s3 +8000679c: 801fe0ef jal ra,80004f9c +800067a0: 400514e3 bnez a0,800073a8 <_ldtoa_r+0xd04> +800067a4: 09000793 li a5,144 +800067a8: 16f12223 sw a5,356(sp) +800067ac: 07c10713 addi a4,sp,124 +800067b0: 00098793 mv a5,s3 +800067b4: 07410613 addi a2,sp,116 +800067b8: 0007d683 lhu a3,0(a5) # 7fffc000 <_start-0x4000> +800067bc: 00278793 addi a5,a5,2 +800067c0: 00270713 addi a4,a4,2 +800067c4: fed71f23 sh a3,-2(a4) +800067c8: fec798e3 bne a5,a2,800067b8 <_ldtoa_r+0x114> +800067cc: 08e15603 lhu a2,142(sp) +800067d0: 00012823 sw zero,16(sp) +800067d4: 01061793 slli a5,a2,0x10 +800067d8: 4107d793 srai a5,a5,0x10 +800067dc: 0007de63 bgez a5,800067f8 <_ldtoa_r+0x154> +800067e0: 01161613 slli a2,a2,0x11 +800067e4: 000107b7 lui a5,0x10 +800067e8: 01165613 srli a2,a2,0x11 +800067ec: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +800067f0: 08c11723 sh a2,142(sp) +800067f4: 00f12823 sw a5,16(sp) +800067f8: 80015b37 lui s6,0x80015 +800067fc: e60b0d93 addi s11,s6,-416 # 80014e60 <__BSS_END__+0xffffe224> +80006800: 014d8c13 addi s8,s11,20 +80006804: 00000693 li a3,0 +80006808: 09810793 addi a5,sp,152 +8000680c: 000c0713 mv a4,s8 +80006810: 0ac10d13 addi s10,sp,172 +80006814: 0080006f j 8000681c <_ldtoa_r+0x178> +80006818: 00075683 lhu a3,0(a4) +8000681c: 00278793 addi a5,a5,2 +80006820: fed79f23 sh a3,-2(a5) +80006824: 00270713 addi a4,a4,2 +80006828: ffa798e3 bne a5,s10,80006818 <_ldtoa_r+0x174> +8000682c: 14060863 beqz a2,8000697c <_ldtoa_r+0x2d8> +80006830: 000087b7 lui a5,0x8 +80006834: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80006838: 56f606e3 beq a2,a5,800075a4 <_ldtoa_r+0xf00> +8000683c: 08c11783 lh a5,140(sp) +80006840: 5a07d8e3 bgez a5,800075f0 <_ldtoa_r+0xf4c> +80006844: 07c10593 addi a1,sp,124 +80006848: 000c0513 mv a0,s8 +8000684c: 8f9fe0ef jal ra,80005144 +80006850: 14050263 beqz a0,80006994 <_ldtoa_r+0x2f0> +80006854: 0c054ce3 bltz a0,8000712c <_ldtoa_r+0xa88> +80006858: 08e15783 lhu a5,142(sp) +8000685c: 62079ce3 bnez a5,80007694 <_ldtoa_r+0xff0> +80006860: 08c11783 lh a5,140(sp) +80006864: 00000493 li s1,0 +80006868: 16010913 addi s2,sp,352 +8000686c: 0207c463 bltz a5,80006894 <_ldtoa_r+0x1f0> +80006870: 118d8413 addi s0,s11,280 +80006874: 07c10613 addi a2,sp,124 +80006878: 00090693 mv a3,s2 +8000687c: 00060593 mv a1,a2 +80006880: 00040513 mv a0,s0 +80006884: bb4ff0ef jal ra,80005c38 +80006888: 08c11783 lh a5,140(sp) +8000688c: fff48493 addi s1,s1,-1 +80006890: fe07d2e3 bgez a5,80006874 <_ldtoa_r+0x1d0> +80006894: 0d010413 addi s0,sp,208 +80006898: 0e810b93 addi s7,sp,232 +8000689c: 00040713 mv a4,s0 +800068a0: 07c10793 addi a5,sp,124 +800068a4: 09010613 addi a2,sp,144 +800068a8: 0007d683 lhu a3,0(a5) +800068ac: 00278793 addi a5,a5,2 +800068b0: 00270713 addi a4,a4,2 +800068b4: fed71f23 sh a3,-2(a4) +800068b8: fec798e3 bne a5,a2,800068a8 <_ldtoa_r+0x204> +800068bc: 00000693 li a3,0 +800068c0: 09810793 addi a5,sp,152 +800068c4: 000c0713 mv a4,s8 +800068c8: 0080006f j 800068d0 <_ldtoa_r+0x22c> +800068cc: 00075683 lhu a3,0(a4) +800068d0: 00278793 addi a5,a5,2 +800068d4: fed79f23 sh a3,-2(a5) +800068d8: 00270713 addi a4,a4,2 +800068dc: ffa798e3 bne a5,s10,800068cc <_ldtoa_r+0x228> +800068e0: 028d8c93 addi s9,s11,40 +800068e4: 12cd8d13 addi s10,s11,300 +800068e8: fffffab7 lui s5,0xfffff +800068ec: 118d8d93 addi s11,s11,280 +800068f0: 00c0006f j 800068fc <_ldtoa_r+0x258> +800068f4: 014d0d13 addi s10,s10,20 +800068f8: 014c8c93 addi s9,s9,20 +800068fc: 00040593 mv a1,s0 +80006900: 000c0513 mv a0,s8 +80006904: 841fe0ef jal ra,80005144 +80006908: 00050793 mv a5,a0 +8000690c: 00040593 mv a1,s0 +80006910: 000d0513 mv a0,s10 +80006914: 04f05663 blez a5,80006960 <_ldtoa_r+0x2bc> +80006918: 82dfe0ef jal ra,80005144 +8000691c: 00050793 mv a5,a0 +80006920: 00090693 mv a3,s2 +80006924: 00040613 mv a2,s0 +80006928: 00040593 mv a1,s0 +8000692c: 000c8513 mv a0,s9 +80006930: 0207c063 bltz a5,80006950 <_ldtoa_r+0x2ac> +80006934: b04ff0ef jal ra,80005c38 +80006938: 09810613 addi a2,sp,152 +8000693c: 00090693 mv a3,s2 +80006940: 00060593 mv a1,a2 +80006944: 000c8513 mv a0,s9 +80006948: af0ff0ef jal ra,80005c38 +8000694c: 015484b3 add s1,s1,s5 +80006950: 01fad793 srli a5,s5,0x1f +80006954: 015787b3 add a5,a5,s5 +80006958: 4017da93 srai s5,a5,0x1 +8000695c: f9bc9ce3 bne s9,s11,800068f4 <_ldtoa_r+0x250> +80006960: 09810613 addi a2,sp,152 +80006964: 00090693 mv a3,s2 +80006968: 000c0593 mv a1,s8 +8000696c: 00060513 mv a0,a2 +80006970: ee0ff0ef jal ra,80006050 +80006974: 12410a93 addi s5,sp,292 +80006978: 0300006f j 800069a8 <_ldtoa_r+0x304> +8000697c: 07c10793 addi a5,sp,124 +80006980: 08e10693 addi a3,sp,142 +80006984: 0007d703 lhu a4,0(a5) +80006988: 00278793 addi a5,a5,2 +8000698c: ea071ce3 bnez a4,80006844 <_ldtoa_r+0x1a0> +80006990: fed79ae3 bne a5,a3,80006984 <_ldtoa_r+0x2e0> +80006994: 00000493 li s1,0 +80006998: 12410a93 addi s5,sp,292 +8000699c: 16010913 addi s2,sp,352 +800069a0: 0d010413 addi s0,sp,208 +800069a4: 0e810b93 addi s7,sp,232 +800069a8: 00040593 mv a1,s0 +800069ac: 09810513 addi a0,sp,152 +800069b0: e9cfe0ef jal ra,8000504c +800069b4: 09810713 addi a4,sp,152 +800069b8: 00040793 mv a5,s0 +800069bc: 0007d683 lhu a3,0(a5) +800069c0: 00278793 addi a5,a5,2 +800069c4: 00270713 addi a4,a4,2 +800069c8: fed71f23 sh a3,-2(a4) +800069cc: ff7798e3 bne a5,s7,800069bc <_ldtoa_r+0x318> +800069d0: 00040593 mv a1,s0 +800069d4: 07c10513 addi a0,sp,124 +800069d8: 0a011823 sh zero,176(sp) +800069dc: e70fe0ef jal ra,8000504c +800069e0: 07c10793 addi a5,sp,124 +800069e4: 00045703 lhu a4,0(s0) +800069e8: 00240413 addi s0,s0,2 +800069ec: 00278793 addi a5,a5,2 +800069f0: fee79f23 sh a4,-2(a5) +800069f4: ff7418e3 bne s0,s7,800069e4 <_ldtoa_r+0x340> +800069f8: 09810513 addi a0,sp,152 +800069fc: 00090613 mv a2,s2 +80006a00: 07c10593 addi a1,sp,124 +80006a04: 08011a23 sh zero,148(sp) +80006a08: 818ff0ef jal ra,80005a20 +80006a0c: 1ac15503 lhu a0,428(sp) +80006a10: 1c051463 bnez a0,80006bd8 <_ldtoa_r+0x534> +80006a14: 09410c93 addi s9,sp,148 +80006a18: 07e10413 addi s0,sp,126 +80006a1c: 0b610c13 addi s8,sp,182 +80006a20: e60b0593 addi a1,s6,-416 +80006a24: 07c10513 addi a0,sp,124 +80006a28: f1cfe0ef jal ra,80005144 +80006a2c: 1a050663 beqz a0,80006bd8 <_ldtoa_r+0x534> +80006a30: 00000713 li a4,0 +80006a34: 000c8693 mv a3,s9 +80006a38: 01c0006f j 80006a54 <_ldtoa_r+0x3b0> +80006a3c: 00171713 slli a4,a4,0x1 +80006a40: 00f69023 sh a5,0(a3) +80006a44: 01071713 slli a4,a4,0x10 +80006a48: ffe68693 addi a3,a3,-2 +80006a4c: 01075713 srli a4,a4,0x10 +80006a50: 04868463 beq a3,s0,80006a98 <_ldtoa_r+0x3f4> +80006a54: 0006d783 lhu a5,0(a3) +80006a58: 01079613 slli a2,a5,0x10 +80006a5c: 41065613 srai a2,a2,0x10 +80006a60: 00179793 slli a5,a5,0x1 +80006a64: 00065463 bgez a2,80006a6c <_ldtoa_r+0x3c8> +80006a68: 00176713 ori a4,a4,1 +80006a6c: 01079793 slli a5,a5,0x10 +80006a70: 0107d793 srli a5,a5,0x10 +80006a74: 00277613 andi a2,a4,2 +80006a78: 0017e593 ori a1,a5,1 +80006a7c: fc0600e3 beqz a2,80006a3c <_ldtoa_r+0x398> +80006a80: 00171713 slli a4,a4,0x1 +80006a84: 00b69023 sh a1,0(a3) +80006a88: 01071713 slli a4,a4,0x10 +80006a8c: ffe68693 addi a3,a3,-2 +80006a90: 01075713 srli a4,a4,0x10 +80006a94: fc8690e3 bne a3,s0,80006a54 <_ldtoa_r+0x3b0> +80006a98: 0b410713 addi a4,sp,180 +80006a9c: 07c10793 addi a5,sp,124 +80006aa0: 0007d683 lhu a3,0(a5) +80006aa4: 00278793 addi a5,a5,2 +80006aa8: 00270713 addi a4,a4,2 +80006aac: fed71f23 sh a3,-2(a4) +80006ab0: ff9798e3 bne a5,s9,80006aa0 <_ldtoa_r+0x3fc> +80006ab4: 0c011623 sh zero,204(sp) +80006ab8: 00000713 li a4,0 +80006abc: 0cc10693 addi a3,sp,204 +80006ac0: 01c0006f j 80006adc <_ldtoa_r+0x438> +80006ac4: 00171713 slli a4,a4,0x1 +80006ac8: 00f69023 sh a5,0(a3) +80006acc: 01071713 slli a4,a4,0x10 +80006ad0: ffe68693 addi a3,a3,-2 +80006ad4: 01075713 srli a4,a4,0x10 +80006ad8: 05868463 beq a3,s8,80006b20 <_ldtoa_r+0x47c> +80006adc: 0006d783 lhu a5,0(a3) +80006ae0: 01079613 slli a2,a5,0x10 +80006ae4: 41065613 srai a2,a2,0x10 +80006ae8: 00179793 slli a5,a5,0x1 +80006aec: 00065463 bgez a2,80006af4 <_ldtoa_r+0x450> +80006af0: 00176713 ori a4,a4,1 +80006af4: 01079793 slli a5,a5,0x10 +80006af8: 0107d793 srli a5,a5,0x10 +80006afc: 00277613 andi a2,a4,2 +80006b00: 0017e593 ori a1,a5,1 +80006b04: fc0600e3 beqz a2,80006ac4 <_ldtoa_r+0x420> +80006b08: 00171713 slli a4,a4,0x1 +80006b0c: 00b69023 sh a1,0(a3) +80006b10: 01071713 slli a4,a4,0x10 +80006b14: ffe68693 addi a3,a3,-2 +80006b18: 01075713 srli a4,a4,0x10 +80006b1c: fd8690e3 bne a3,s8,80006adc <_ldtoa_r+0x438> +80006b20: 00000713 li a4,0 +80006b24: 0cc10693 addi a3,sp,204 +80006b28: 01c0006f j 80006b44 <_ldtoa_r+0x4a0> +80006b2c: 00171713 slli a4,a4,0x1 +80006b30: 00f69023 sh a5,0(a3) +80006b34: 01071713 slli a4,a4,0x10 +80006b38: ffe68693 addi a3,a3,-2 +80006b3c: 01075713 srli a4,a4,0x10 +80006b40: 05868463 beq a3,s8,80006b88 <_ldtoa_r+0x4e4> +80006b44: 0006d783 lhu a5,0(a3) +80006b48: 01079613 slli a2,a5,0x10 +80006b4c: 41065613 srai a2,a2,0x10 +80006b50: 00179793 slli a5,a5,0x1 +80006b54: 00065463 bgez a2,80006b5c <_ldtoa_r+0x4b8> +80006b58: 00176713 ori a4,a4,1 +80006b5c: 01079793 slli a5,a5,0x10 +80006b60: 0107d793 srli a5,a5,0x10 +80006b64: 00277613 andi a2,a4,2 +80006b68: 0017e593 ori a1,a5,1 +80006b6c: fc0600e3 beqz a2,80006b2c <_ldtoa_r+0x488> +80006b70: 00171713 slli a4,a4,0x1 +80006b74: 00b69023 sh a1,0(a3) +80006b78: 01071713 slli a4,a4,0x10 +80006b7c: ffe68693 addi a3,a3,-2 +80006b80: 01075713 srli a4,a4,0x10 +80006b84: fd8690e3 bne a3,s8,80006b44 <_ldtoa_r+0x4a0> +80006b88: 00000613 li a2,0 +80006b8c: 000c8693 mv a3,s9 +80006b90: 0cc10713 addi a4,sp,204 +80006b94: 0006d583 lhu a1,0(a3) +80006b98: 00075783 lhu a5,0(a4) +80006b9c: ffe68693 addi a3,a3,-2 +80006ba0: ffe70713 addi a4,a4,-2 +80006ba4: 00b787b3 add a5,a5,a1 +80006ba8: 00c787b3 add a5,a5,a2 +80006bac: 0107d613 srli a2,a5,0x10 +80006bb0: 00f69123 sh a5,2(a3) +80006bb4: 00167613 andi a2,a2,1 +80006bb8: fd871ee3 bne a4,s8,80006b94 <_ldtoa_r+0x4f0> +80006bbc: 09810513 addi a0,sp,152 +80006bc0: 00090613 mv a2,s2 +80006bc4: 07c10593 addi a1,sp,124 +80006bc8: e59fe0ef jal ra,80005a20 +80006bcc: 1ac15503 lhu a0,428(sp) +80006bd0: fff48493 addi s1,s1,-1 +80006bd4: e40506e3 beqz a0,80006a20 <_ldtoa_r+0x37c> +80006bd8: 01012783 lw a5,16(sp) +80006bdc: 00012683 lw a3,0(sp) +80006be0: 00300713 li a4,3 +80006be4: 00f037b3 snez a5,a5 +80006be8: 40f007b3 neg a5,a5 +80006bec: 00d7f793 andi a5,a5,13 +80006bf0: 02078793 addi a5,a5,32 +80006bf4: 12f10223 sb a5,292(sp) +80006bf8: 00412783 lw a5,4(sp) +80006bfc: 00e69463 bne a3,a4,80006c04 <_ldtoa_r+0x560> +80006c00: 009787b3 add a5,a5,s1 +80006c04: 02a00713 li a4,42 +80006c08: 00078413 mv s0,a5 +80006c0c: 00f75463 bge a4,a5,80006c14 <_ldtoa_r+0x570> +80006c10: 02a00413 li s0,42 +80006c14: 00a00713 li a4,10 +80006c18: 4ee50263 beq a0,a4,800070fc <_ldtoa_r+0xa58> +80006c1c: 03050513 addi a0,a0,48 +80006c20: 02e00713 li a4,46 +80006c24: 12a102a3 sb a0,293(sp) +80006c28: 12e10323 sb a4,294(sp) +80006c2c: 1e07c2e3 bltz a5,80007610 <_ldtoa_r+0xf6c> +80006c30: 12710793 addi a5,sp,295 +80006c34: 00f12823 sw a5,16(sp) +80006c38: 00000c13 li s8,0 +80006c3c: 00912e23 sw s1,28(sp) +80006c40: 000c0493 mv s1,s8 +80006c44: 00090c13 mv s8,s2 +80006c48: 01012903 lw s2,16(sp) +80006c4c: 0b410c93 addi s9,sp,180 +80006c50: 09410d93 addi s11,sp,148 +80006c54: 07e10b93 addi s7,sp,126 +80006c58: 0b610d13 addi s10,sp,182 +80006c5c: 00000713 li a4,0 +80006c60: 000d8613 mv a2,s11 +80006c64: 01c0006f j 80006c80 <_ldtoa_r+0x5dc> +80006c68: 00171713 slli a4,a4,0x1 +80006c6c: 00f61023 sh a5,0(a2) # 8000 <_start-0x7fff8000> +80006c70: 01071713 slli a4,a4,0x10 +80006c74: ffe60613 addi a2,a2,-2 +80006c78: 01075713 srli a4,a4,0x10 +80006c7c: 05760463 beq a2,s7,80006cc4 <_ldtoa_r+0x620> +80006c80: 00065783 lhu a5,0(a2) +80006c84: 01079593 slli a1,a5,0x10 +80006c88: 4105d593 srai a1,a1,0x10 +80006c8c: 00179793 slli a5,a5,0x1 +80006c90: 0005d463 bgez a1,80006c98 <_ldtoa_r+0x5f4> +80006c94: 00176713 ori a4,a4,1 +80006c98: 01079793 slli a5,a5,0x10 +80006c9c: 0107d793 srli a5,a5,0x10 +80006ca0: 00277593 andi a1,a4,2 +80006ca4: 0017e513 ori a0,a5,1 +80006ca8: fc0580e3 beqz a1,80006c68 <_ldtoa_r+0x5c4> +80006cac: 00171713 slli a4,a4,0x1 +80006cb0: 00a61023 sh a0,0(a2) +80006cb4: 01071713 slli a4,a4,0x10 +80006cb8: ffe60613 addi a2,a2,-2 +80006cbc: 01075713 srli a4,a4,0x10 +80006cc0: fd7610e3 bne a2,s7,80006c80 <_ldtoa_r+0x5dc> +80006cc4: 000c8713 mv a4,s9 +80006cc8: 07c10793 addi a5,sp,124 +80006ccc: 0007d603 lhu a2,0(a5) +80006cd0: 00278793 addi a5,a5,2 +80006cd4: 00270713 addi a4,a4,2 +80006cd8: fec71f23 sh a2,-2(a4) +80006cdc: ffb798e3 bne a5,s11,80006ccc <_ldtoa_r+0x628> +80006ce0: 0c011623 sh zero,204(sp) +80006ce4: 00000713 li a4,0 +80006ce8: 0cc10613 addi a2,sp,204 +80006cec: 01c0006f j 80006d08 <_ldtoa_r+0x664> +80006cf0: 00171713 slli a4,a4,0x1 +80006cf4: 00f61023 sh a5,0(a2) +80006cf8: 01071713 slli a4,a4,0x10 +80006cfc: ffe60613 addi a2,a2,-2 +80006d00: 01075713 srli a4,a4,0x10 +80006d04: 05a60463 beq a2,s10,80006d4c <_ldtoa_r+0x6a8> +80006d08: 00065783 lhu a5,0(a2) +80006d0c: 01079593 slli a1,a5,0x10 +80006d10: 4105d593 srai a1,a1,0x10 +80006d14: 00179793 slli a5,a5,0x1 +80006d18: 0005d463 bgez a1,80006d20 <_ldtoa_r+0x67c> +80006d1c: 00176713 ori a4,a4,1 +80006d20: 01079793 slli a5,a5,0x10 +80006d24: 0107d793 srli a5,a5,0x10 +80006d28: 00277593 andi a1,a4,2 +80006d2c: 0017e513 ori a0,a5,1 +80006d30: fc0580e3 beqz a1,80006cf0 <_ldtoa_r+0x64c> +80006d34: 00171713 slli a4,a4,0x1 +80006d38: 00a61023 sh a0,0(a2) +80006d3c: 01071713 slli a4,a4,0x10 +80006d40: ffe60613 addi a2,a2,-2 +80006d44: 01075713 srli a4,a4,0x10 +80006d48: fda610e3 bne a2,s10,80006d08 <_ldtoa_r+0x664> +80006d4c: 00000713 li a4,0 +80006d50: 0cc10613 addi a2,sp,204 +80006d54: 01c0006f j 80006d70 <_ldtoa_r+0x6cc> +80006d58: 00171713 slli a4,a4,0x1 +80006d5c: 00f61023 sh a5,0(a2) +80006d60: 01071713 slli a4,a4,0x10 +80006d64: ffe60613 addi a2,a2,-2 +80006d68: 01075713 srli a4,a4,0x10 +80006d6c: 05a60463 beq a2,s10,80006db4 <_ldtoa_r+0x710> +80006d70: 00065783 lhu a5,0(a2) +80006d74: 01079593 slli a1,a5,0x10 +80006d78: 4105d593 srai a1,a1,0x10 +80006d7c: 00179793 slli a5,a5,0x1 +80006d80: 0005d463 bgez a1,80006d88 <_ldtoa_r+0x6e4> +80006d84: 00176713 ori a4,a4,1 +80006d88: 01079793 slli a5,a5,0x10 +80006d8c: 0107d793 srli a5,a5,0x10 +80006d90: 00277593 andi a1,a4,2 +80006d94: 0017e513 ori a0,a5,1 +80006d98: fc0580e3 beqz a1,80006d58 <_ldtoa_r+0x6b4> +80006d9c: 00171713 slli a4,a4,0x1 +80006da0: 00a61023 sh a0,0(a2) +80006da4: 01071713 slli a4,a4,0x10 +80006da8: ffe60613 addi a2,a2,-2 +80006dac: 01075713 srli a4,a4,0x10 +80006db0: fda610e3 bne a2,s10,80006d70 <_ldtoa_r+0x6cc> +80006db4: 00000593 li a1,0 +80006db8: 000d8613 mv a2,s11 +80006dbc: 0cc10713 addi a4,sp,204 +80006dc0: 00065503 lhu a0,0(a2) +80006dc4: 00075783 lhu a5,0(a4) +80006dc8: ffe60613 addi a2,a2,-2 +80006dcc: ffe70713 addi a4,a4,-2 +80006dd0: 00a787b3 add a5,a5,a0 +80006dd4: 00b787b3 add a5,a5,a1 +80006dd8: 0107d593 srli a1,a5,0x10 +80006ddc: 00f61123 sh a5,2(a2) +80006de0: 0015f593 andi a1,a1,1 +80006de4: fda71ee3 bne a4,s10,80006dc0 <_ldtoa_r+0x71c> +80006de8: 000c0613 mv a2,s8 +80006dec: 07c10593 addi a1,sp,124 +80006df0: 09810513 addi a0,sp,152 +80006df4: c2dfe0ef jal ra,80005a20 +80006df8: 1ac15783 lhu a5,428(sp) +80006dfc: 00990733 add a4,s2,s1 +80006e00: 00148493 addi s1,s1,1 +80006e04: 03078613 addi a2,a5,48 +80006e08: 00c70023 sb a2,0(a4) +80006e0c: e49458e3 bge s0,s1,80006c5c <_ldtoa_r+0x5b8> +80006e10: fff44513 not a0,s0 +80006e14: 01012703 lw a4,16(sp) +80006e18: 41f55513 srai a0,a0,0x1f +80006e1c: 00a47533 and a0,s0,a0 +80006e20: 01c12483 lw s1,28(sp) +80006e24: 00150913 addi s2,a0,1 +80006e28: 01270933 add s2,a4,s2 +80006e2c: 00a70c33 add s8,a4,a0 +80006e30: 00400713 li a4,4 +80006e34: 04f75e63 bge a4,a5,80006e90 <_ldtoa_r+0x7ec> +80006e38: 00500713 li a4,5 +80006e3c: 00e780e3 beq a5,a4,8000763c <_ldtoa_r+0xf98> +80006e40: ffe94783 lbu a5,-2(s2) +80006e44: ffe90713 addi a4,s2,-2 +80006e48: 07f7f793 andi a5,a5,127 +80006e4c: 78044463 bltz s0,800075d4 <_ldtoa_r+0xf30> +80006e50: 02e00693 li a3,46 +80006e54: 03800613 li a2,56 +80006e58: 03000593 li a1,48 +80006e5c: 00d78e63 beq a5,a3,80006e78 <_ldtoa_r+0x7d4> +80006e60: 78f65263 bge a2,a5,800075e4 <_ldtoa_r+0xf40> +80006e64: fff74783 lbu a5,-1(a4) +80006e68: 00b70023 sb a1,0(a4) +80006e6c: fff70713 addi a4,a4,-1 +80006e70: 07f7f793 andi a5,a5,127 +80006e74: fe9ff06f j 80006e5c <_ldtoa_r+0x7b8> +80006e78: fff74783 lbu a5,-1(a4) +80006e7c: 03800693 li a3,56 +80006e80: 00f6f4e3 bgeu a3,a5,80007688 <_ldtoa_r+0xfe4> +80006e84: 03100793 li a5,49 +80006e88: 00148493 addi s1,s1,1 +80006e8c: fef70fa3 sb a5,-1(a4) +80006e90: 800155b7 lui a1,0x80015 +80006e94: 00048613 mv a2,s1 +80006e98: e5c58593 addi a1,a1,-420 # 80014e5c <__BSS_END__+0xffffe220> +80006e9c: 000c0513 mv a0,s8 +80006ea0: 03d020ef jal ra,800096dc +80006ea4: 07215783 lhu a5,114(sp) +80006ea8: 01412703 lw a4,20(sp) +80006eac: 16912823 sw s1,368(sp) +80006eb0: fff7c793 not a5,a5 +80006eb4: 16e12223 sw a4,356(sp) +80006eb8: 01179713 slli a4,a5,0x11 +80006ebc: 00071e63 bnez a4,80006ed8 <_ldtoa_r+0x834> +80006ec0: 00098513 mv a0,s3 +80006ec4: b9cfe0ef jal ra,80005260 +80006ec8: 22051063 bnez a0,800070e8 <_ldtoa_r+0xa44> +80006ecc: 00098513 mv a0,s3 +80006ed0: 8ccfe0ef jal ra,80004f9c +80006ed4: 20051a63 bnez a0,800070e8 <_ldtoa_r+0xa44> +80006ed8: 00c12683 lw a3,12(sp) +80006edc: 12414703 lbu a4,292(sp) +80006ee0: 00148793 addi a5,s1,1 +80006ee4: 00f6a023 sw a5,0(a3) +80006ee8: 000a8793 mv a5,s5 +80006eec: 02070a63 beqz a4,80006f20 <_ldtoa_r+0x87c> +80006ef0: 02e00693 li a3,46 +80006ef4: 1cd70c63 beq a4,a3,800070cc <_ldtoa_r+0xa28> +80006ef8: 0017c703 lbu a4,1(a5) +80006efc: 00178793 addi a5,a5,1 +80006f00: fe071ae3 bnez a4,80006ef4 <_ldtoa_r+0x850> +80006f04: 04500693 li a3,69 +80006f08: 00fae663 bltu s5,a5,80006f14 <_ldtoa_r+0x870> +80006f0c: 0140006f j 80006f20 <_ldtoa_r+0x87c> +80006f10: 01578863 beq a5,s5,80006f20 <_ldtoa_r+0x87c> +80006f14: fff7c703 lbu a4,-1(a5) +80006f18: fff78793 addi a5,a5,-1 +80006f1c: fed71ae3 bne a4,a3,80006f10 <_ldtoa_r+0x86c> +80006f20: 00078023 sb zero,0(a5) +80006f24: 000a8793 mv a5,s5 +80006f28: 02000693 li a3,32 +80006f2c: 02d00613 li a2,45 +80006f30: 0007c703 lbu a4,0(a5) +80006f34: 00d70463 beq a4,a3,80006f3c <_ldtoa_r+0x898> +80006f38: 00c71663 bne a4,a2,80006f44 <_ldtoa_r+0x8a0> +80006f3c: 00178793 addi a5,a5,1 +80006f40: ff1ff06f j 80006f30 <_ldtoa_r+0x88c> +80006f44: 000a8413 mv s0,s5 +80006f48: 00c0006f j 80006f54 <_ldtoa_r+0x8b0> +80006f4c: 0007c703 lbu a4,0(a5) +80006f50: 00068413 mv s0,a3 +80006f54: 00e40023 sb a4,0(s0) +80006f58: 00140693 addi a3,s0,1 +80006f5c: 00178793 addi a5,a5,1 +80006f60: fe0716e3 bnez a4,80006f4c <_ldtoa_r+0x8a8> +80006f64: 00012683 lw a3,0(sp) +80006f68: 00200793 li a5,2 +80006f6c: fff44703 lbu a4,-1(s0) +80006f70: 12f68663 beq a3,a5,8000709c <_ldtoa_r+0x9f8> +80006f74: 00412783 lw a5,4(sp) +80006f78: 00078693 mv a3,a5 +80006f7c: 0097d463 bge a5,s1,80006f84 <_ldtoa_r+0x8e0> +80006f80: 00048693 mv a3,s1 +80006f84: 03000793 li a5,48 +80006f88: 02f71663 bne a4,a5,80006fb4 <_ldtoa_r+0x910> +80006f8c: 415407b3 sub a5,s0,s5 +80006f90: 02f6d263 bge a3,a5,80006fb4 <_ldtoa_r+0x910> +80006f94: 03000613 li a2,48 +80006f98: 0080006f j 80006fa0 <_ldtoa_r+0x8fc> +80006f9c: 00e6dc63 bge a3,a4,80006fb4 <_ldtoa_r+0x910> +80006fa0: ffe44783 lbu a5,-2(s0) +80006fa4: fe040fa3 sb zero,-1(s0) +80006fa8: fff40413 addi s0,s0,-1 +80006fac: 41540733 sub a4,s0,s5 +80006fb0: fec786e3 beq a5,a2,80006f9c <_ldtoa_r+0x8f8> +80006fb4: 00012703 lw a4,0(sp) +80006fb8: 00300793 li a5,3 +80006fbc: 0af70263 beq a4,a5,80007060 <_ldtoa_r+0x9bc> +80006fc0: 00812783 lw a5,8(sp) +80006fc4: 040a2223 sw zero,68(s4) +80006fc8: 00978693 addi a3,a5,9 +80006fcc: 01700793 li a5,23 +80006fd0: 0cd7f263 bgeu a5,a3,80007094 <_ldtoa_r+0x9f0> +80006fd4: 00100713 li a4,1 +80006fd8: 00400793 li a5,4 +80006fdc: 00179793 slli a5,a5,0x1 +80006fe0: 01478613 addi a2,a5,20 +80006fe4: 00070593 mv a1,a4 +80006fe8: 00170713 addi a4,a4,1 +80006fec: fec6f8e3 bgeu a3,a2,80006fdc <_ldtoa_r+0x938> +80006ff0: 04ba2223 sw a1,68(s4) +80006ff4: 000a0513 mv a0,s4 +80006ff8: 500010ef jal ra,800084f8 <_Balloc> +80006ffc: 04aa2023 sw a0,64(s4) +80007000: 000a8593 mv a1,s5 +80007004: 00050493 mv s1,a0 +80007008: 0a9020ef jal ra,800098b0 +8000700c: 01812783 lw a5,24(sp) +80007010: 00078863 beqz a5,80007020 <_ldtoa_r+0x97c> +80007014: 41540433 sub s0,s0,s5 +80007018: 00848433 add s0,s1,s0 +8000701c: 0087a023 sw s0,0(a5) +80007020: 1ec12083 lw ra,492(sp) +80007024: 1e812403 lw s0,488(sp) +80007028: 1e012903 lw s2,480(sp) +8000702c: 1dc12983 lw s3,476(sp) +80007030: 1d812a03 lw s4,472(sp) +80007034: 1d412a83 lw s5,468(sp) +80007038: 1d012b03 lw s6,464(sp) +8000703c: 1cc12b83 lw s7,460(sp) +80007040: 1c812c03 lw s8,456(sp) +80007044: 1c412c83 lw s9,452(sp) +80007048: 1c012d03 lw s10,448(sp) +8000704c: 1bc12d83 lw s11,444(sp) +80007050: 00048513 mv a0,s1 +80007054: 1e412483 lw s1,484(sp) +80007058: 1f010113 addi sp,sp,496 +8000705c: 00008067 ret +80007060: 00412783 lw a5,4(sp) +80007064: 009784b3 add s1,a5,s1 +80007068: 5004c863 bltz s1,80007578 <_ldtoa_r+0xed4> +8000706c: 00c12783 lw a5,12(sp) +80007070: 00812703 lw a4,8(sp) +80007074: 0007a783 lw a5,0(a5) +80007078: 00f707b3 add a5,a4,a5 +8000707c: 00f12423 sw a5,8(sp) +80007080: 00812783 lw a5,8(sp) +80007084: 040a2223 sw zero,68(s4) +80007088: 00378693 addi a3,a5,3 +8000708c: 01700793 li a5,23 +80007090: f4d7e2e3 bltu a5,a3,80006fd4 <_ldtoa_r+0x930> +80007094: 00000593 li a1,0 +80007098: f5dff06f j 80006ff4 <_ldtoa_r+0x950> +8000709c: 03000793 li a5,48 +800070a0: f2f710e3 bne a4,a5,80006fc0 <_ldtoa_r+0x91c> +800070a4: 415407b3 sub a5,s0,s5 +800070a8: 00100693 li a3,1 +800070ac: eef6c4e3 blt a3,a5,80006f94 <_ldtoa_r+0x8f0> +800070b0: f11ff06f j 80006fc0 <_ldtoa_r+0x91c> +800070b4: 00812483 lw s1,8(sp) +800070b8: 00912223 sw s1,4(sp) +800070bc: 02a00793 li a5,42 +800070c0: ec97d063 bge a5,s1,80006780 <_ldtoa_r+0xdc> +800070c4: 00f12223 sw a5,4(sp) +800070c8: eb8ff06f j 80006780 <_ldtoa_r+0xdc> +800070cc: 0007c703 lbu a4,0(a5) +800070d0: e2070ae3 beqz a4,80006f04 <_ldtoa_r+0x860> +800070d4: 0017c703 lbu a4,1(a5) +800070d8: 00178793 addi a5,a5,1 +800070dc: fee78fa3 sb a4,-1(a5) +800070e0: fe071ae3 bnez a4,800070d4 <_ldtoa_r+0xa30> +800070e4: e21ff06f j 80006f04 <_ldtoa_r+0x860> +800070e8: 00c12703 lw a4,12(sp) +800070ec: 000027b7 lui a5,0x2 +800070f0: 70f78793 addi a5,a5,1807 # 270f <_start-0x7fffd8f1> +800070f4: 00f72023 sw a5,0(a4) +800070f8: e2dff06f j 80006f24 <_ldtoa_r+0x880> +800070fc: 03100713 li a4,49 +80007100: 12e102a3 sb a4,293(sp) +80007104: 02e00713 li a4,46 +80007108: 12e10323 sb a4,294(sp) +8000710c: 00148493 addi s1,s1,1 +80007110: 2af05c63 blez a5,800073c8 <_ldtoa_r+0xd24> +80007114: 03000793 li a5,48 +80007118: 12f103a3 sb a5,295(sp) +8000711c: 12810793 addi a5,sp,296 +80007120: fff40413 addi s0,s0,-1 +80007124: 00f12823 sw a5,16(sp) +80007128: b11ff06f j 80006c38 <_ldtoa_r+0x594> +8000712c: 0b410c93 addi s9,sp,180 +80007130: 000c8713 mv a4,s9 +80007134: 07c10793 addi a5,sp,124 +80007138: 09010613 addi a2,sp,144 +8000713c: 0007d683 lhu a3,0(a5) +80007140: 00278793 addi a5,a5,2 +80007144: 00270713 addi a4,a4,2 +80007148: fed71f23 sh a3,-2(a4) +8000714c: fec798e3 bne a5,a2,8000713c <_ldtoa_r+0xa98> +80007150: 000047b7 lui a5,0x4 +80007154: 08e78793 addi a5,a5,142 # 408e <_start-0x7fffbf72> +80007158: 0cf11323 sh a5,198(sp) +8000715c: 000087b7 lui a5,0x8 +80007160: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80007164: 00f12e23 sw a5,28(sp) +80007168: ffffc7b7 lui a5,0xffffc +8000716c: 12410a93 addi s5,sp,292 +80007170: 0d010413 addi s0,sp,208 +80007174: 01000e13 li t3,16 +80007178: 0c8d8313 addi t1,s11,200 +8000717c: 00278793 addi a5,a5,2 # ffffc002 <__BSS_END__+0x7ffe53c6> +80007180: 03412423 sw s4,40(sp) +80007184: 03512223 sw s5,36(sp) +80007188: 00000493 li s1,0 +8000718c: 000c8a93 mv s5,s9 +80007190: 16010913 addi s2,sp,352 +80007194: 00040c93 mv s9,s0 +80007198: 0aa10b93 addi s7,sp,170 +8000719c: 02f12023 sw a5,32(sp) +800071a0: 000e0a13 mv s4,t3 +800071a4: 00030413 mv s0,t1 +800071a8: 00090693 mv a3,s2 +800071ac: 09810613 addi a2,sp,152 +800071b0: 000a8593 mv a1,s5 +800071b4: 00040513 mv a0,s0 +800071b8: e99fe0ef jal ra,80006050 +800071bc: 04c10713 addi a4,sp,76 +800071c0: 09810793 addi a5,sp,152 +800071c4: 0007d683 lhu a3,0(a5) +800071c8: 00278793 addi a5,a5,2 +800071cc: 00270713 addi a4,a4,2 +800071d0: fed71f23 sh a3,-2(a4) +800071d4: ffa798e3 bne a5,s10,800071c4 <_ldtoa_r+0xb20> +800071d8: 01c12783 lw a5,28(sp) +800071dc: 05e15583 lhu a1,94(sp) +800071e0: 00f5f633 and a2,a1,a5 +800071e4: 02012783 lw a5,32(sp) +800071e8: 00f60533 add a0,a2,a5 +800071ec: 3aa05063 blez a0,8000758c <_ldtoa_r+0xee8> +800071f0: 09000613 li a2,144 +800071f4: 40a60633 sub a2,a2,a0 +800071f8: 000c8713 mv a4,s9 +800071fc: 04c10793 addi a5,sp,76 +80007200: 0007d683 lhu a3,0(a5) +80007204: 00278793 addi a5,a5,2 +80007208: 00270713 addi a4,a4,2 +8000720c: fed71f23 sh a3,-2(a4) +80007210: ff3798e3 bne a5,s3,80007200 <_ldtoa_r+0xb5c> +80007214: 06c05463 blez a2,8000727c <_ldtoa_r+0xbd8> +80007218: 00f00793 li a5,15 +8000721c: 000c8713 mv a4,s9 +80007220: 02c7dc63 bge a5,a2,80007258 <_ldtoa_r+0xbb4> +80007224: ff060613 addi a2,a2,-16 +80007228: 00465693 srli a3,a2,0x4 +8000722c: 00168713 addi a4,a3,1 +80007230: 00171713 slli a4,a4,0x1 +80007234: 00ec8733 add a4,s9,a4 +80007238: 000c8793 mv a5,s9 +8000723c: 00278793 addi a5,a5,2 +80007240: fe079f23 sh zero,-2(a5) +80007244: fee79ce3 bne a5,a4,8000723c <_ldtoa_r+0xb98> +80007248: 08000613 li a2,128 +8000724c: 40a60633 sub a2,a2,a0 +80007250: 00469693 slli a3,a3,0x4 +80007254: 40d60633 sub a2,a2,a3 +80007258: 00161613 slli a2,a2,0x1 +8000725c: 00cd8633 add a2,s11,a2 +80007260: 00075783 lhu a5,0(a4) +80007264: 23065683 lhu a3,560(a2) +80007268: 00d7f7b3 and a5,a5,a3 +8000726c: 00f71023 sh a5,0(a4) +80007270: 01059593 slli a1,a1,0x10 +80007274: 4105d593 srai a1,a1,0x10 +80007278: 1605c063 bltz a1,800073d8 <_ldtoa_r+0xd34> +8000727c: 09810793 addi a5,sp,152 +80007280: 000c8713 mv a4,s9 +80007284: 0007d603 lhu a2,0(a5) +80007288: 00075683 lhu a3,0(a4) +8000728c: 00278793 addi a5,a5,2 +80007290: 00270713 addi a4,a4,2 +80007294: 02d61463 bne a2,a3,800072bc <_ldtoa_r+0xc18> +80007298: fefb96e3 bne s7,a5,80007284 <_ldtoa_r+0xbe0> +8000729c: 000a8713 mv a4,s5 +800072a0: 09810793 addi a5,sp,152 +800072a4: 0007d683 lhu a3,0(a5) +800072a8: 00278793 addi a5,a5,2 +800072ac: 00270713 addi a4,a4,2 +800072b0: fed71f23 sh a3,-2(a4) +800072b4: ffa798e3 bne a5,s10,800072a4 <_ldtoa_r+0xc00> +800072b8: 014484b3 add s1,s1,s4 +800072bc: 01440413 addi s0,s0,20 +800072c0: 12cd8793 addi a5,s11,300 +800072c4: 001a5a13 srli s4,s4,0x1 +800072c8: eef410e3 bne s0,a5,800071a8 <_ldtoa_r+0xb04> +800072cc: 0c615783 lhu a5,198(sp) +800072d0: 08e15703 lhu a4,142(sp) +800072d4: 000c8413 mv s0,s9 +800072d8: 02812a03 lw s4,40(sp) +800072dc: 00e787b3 add a5,a5,a4 +800072e0: ffffc737 lui a4,0xffffc +800072e4: 000a8c93 mv s9,s5 +800072e8: f7270713 addi a4,a4,-142 # ffffbf72 <__BSS_END__+0x7ffe5336> +800072ec: 02412a83 lw s5,36(sp) +800072f0: 00e787b3 add a5,a5,a4 +800072f4: 0cf11323 sh a5,198(sp) +800072f8: 07c10713 addi a4,sp,124 +800072fc: 000c8793 mv a5,s9 +80007300: 0c810613 addi a2,sp,200 +80007304: 0007d683 lhu a3,0(a5) +80007308: 00278793 addi a5,a5,2 +8000730c: 00270713 addi a4,a4,2 +80007310: fed71f23 sh a3,-2(a4) +80007314: fec798e3 bne a5,a2,80007304 <_ldtoa_r+0xc60> +80007318: 00000713 li a4,0 +8000731c: 09810793 addi a5,sp,152 +80007320: 0080006f j 80007328 <_ldtoa_r+0xc84> +80007324: 000c5703 lhu a4,0(s8) +80007328: 00278793 addi a5,a5,2 +8000732c: fee79f23 sh a4,-2(a5) +80007330: 002c0c13 addi s8,s8,2 +80007334: ffa798e3 bne a5,s10,80007324 <_ldtoa_r+0xc80> +80007338: 028d8d13 addi s10,s11,40 +8000733c: 00001c37 lui s8,0x1 +80007340: 118d8d93 addi s11,s11,280 +80007344: 0100006f j 80007354 <_ldtoa_r+0xcb0> +80007348: 001c5c13 srli s8,s8,0x1 +8000734c: 29bd0063 beq s10,s11,800075cc <_ldtoa_r+0xf28> +80007350: 014d0d13 addi s10,s10,20 +80007354: 000c8593 mv a1,s9 +80007358: 000d8513 mv a0,s11 +8000735c: de9fd0ef jal ra,80005144 +80007360: 00050793 mv a5,a0 +80007364: 000c8593 mv a1,s9 +80007368: 000d0513 mv a0,s10 +8000736c: 26f04063 bgtz a5,800075cc <_ldtoa_r+0xf28> +80007370: dd5fd0ef jal ra,80005144 +80007374: fca04ae3 bgtz a0,80007348 <_ldtoa_r+0xca4> +80007378: 00090693 mv a3,s2 +8000737c: 000c8613 mv a2,s9 +80007380: 000c8593 mv a1,s9 +80007384: 000d0513 mv a0,s10 +80007388: cc9fe0ef jal ra,80006050 +8000738c: 09810613 addi a2,sp,152 +80007390: 00090693 mv a3,s2 +80007394: 00060593 mv a1,a2 +80007398: 000d0513 mv a0,s10 +8000739c: 89dfe0ef jal ra,80005c38 +800073a0: 018484b3 add s1,s1,s8 +800073a4: fa5ff06f j 80007348 <_ldtoa_r+0xca4> +800073a8: 12410a93 addi s5,sp,292 +800073ac: 800155b7 lui a1,0x80015 +800073b0: e3858593 addi a1,a1,-456 # 80014e38 <__BSS_END__+0xffffe1fc> +800073b4: 000a8513 mv a0,s5 +800073b8: 000024b7 lui s1,0x2 +800073bc: 320020ef jal ra,800096dc +800073c0: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> +800073c4: ae1ff06f j 80006ea4 <_ldtoa_r+0x800> +800073c8: 12710c13 addi s8,sp,295 +800073cc: ac0792e3 bnez a5,80006e90 <_ldtoa_r+0x7ec> +800073d0: 01812823 sw s8,16(sp) +800073d4: 865ff06f j 80006c38 <_ldtoa_r+0x594> +800073d8: 04c10793 addi a5,sp,76 +800073dc: 000c8713 mv a4,s9 +800073e0: 00c0006f j 800073ec <_ldtoa_r+0xd48> +800073e4: 05e10693 addi a3,sp,94 +800073e8: e8f68ae3 beq a3,a5,8000727c <_ldtoa_r+0xbd8> +800073ec: 0007d603 lhu a2,0(a5) +800073f0: 00075683 lhu a3,0(a4) +800073f4: 00278793 addi a5,a5,2 +800073f8: 00270713 addi a4,a4,2 +800073fc: fed604e3 beq a2,a3,800073e4 <_ldtoa_r+0xd40> +80007400: 0e215783 lhu a5,226(sp) +80007404: 01c12703 lw a4,28(sp) +80007408: 00f777b3 and a5,a4,a5 +8000740c: 00e79e63 bne a5,a4,80007428 <_ldtoa_r+0xd84> +80007410: 000c8513 mv a0,s9 +80007414: b89fd0ef jal ra,80004f9c +80007418: e60512e3 bnez a0,8000727c <_ldtoa_r+0xbd8> +8000741c: 000c8513 mv a0,s9 +80007420: e41fd0ef jal ra,80005260 +80007424: e4051ce3 bnez a0,8000727c <_ldtoa_r+0xbd8> +80007428: 0ec10593 addi a1,sp,236 +8000742c: 000c0513 mv a0,s8 +80007430: c1dfd0ef jal ra,8000504c +80007434: 10810593 addi a1,sp,264 +80007438: 000c8513 mv a0,s9 +8000743c: c11fd0ef jal ra,8000504c +80007440: 0ec15603 lhu a2,236(sp) +80007444: 10a15503 lhu a0,266(sp) +80007448: 0ee15883 lhu a7,238(sp) +8000744c: fff64613 not a2,a2 +80007450: 01061613 slli a2,a2,0x10 +80007454: 01065613 srli a2,a2,0x10 +80007458: 0ec11623 sh a2,236(sp) +8000745c: 40a885b3 sub a1,a7,a0 +80007460: 00050693 mv a3,a0 +80007464: 06b05e63 blez a1,800074e0 <_ldtoa_r+0xe3c> +80007468: 02412683 lw a3,36(sp) +8000746c: 10810713 addi a4,sp,264 +80007470: 12010793 addi a5,sp,288 +80007474: 00075583 lhu a1,0(a4) +80007478: 00270713 addi a4,a4,2 +8000747c: 00268693 addi a3,a3,2 +80007480: feb69f23 sh a1,-2(a3) +80007484: fef718e3 bne a4,a5,80007474 <_ldtoa_r+0xdd0> +80007488: 12011e23 sh zero,316(sp) +8000748c: 10810713 addi a4,sp,264 +80007490: 0ec10693 addi a3,sp,236 +80007494: 0080006f j 8000749c <_ldtoa_r+0xdf8> +80007498: 0006d603 lhu a2,0(a3) +8000749c: 00270713 addi a4,a4,2 +800074a0: fec71f23 sh a2,-2(a4) +800074a4: 00268693 addi a3,a3,2 +800074a8: fef718e3 bne a4,a5,80007498 <_ldtoa_r+0xdf4> +800074ac: 02412783 lw a5,36(sp) +800074b0: 12011023 sh zero,288(sp) +800074b4: 0ec10713 addi a4,sp,236 +800074b8: 13c10613 addi a2,sp,316 +800074bc: 0007d683 lhu a3,0(a5) +800074c0: 00278793 addi a5,a5,2 +800074c4: 00270713 addi a4,a4,2 +800074c8: fed71f23 sh a3,-2(a4) +800074cc: fec798e3 bne a5,a2,800074bc <_ldtoa_r+0xe18> +800074d0: 10a15683 lhu a3,266(sp) +800074d4: 411505b3 sub a1,a0,a7 +800074d8: 10011223 sh zero,260(sp) +800074dc: 00068513 mv a0,a3 +800074e0: 2c058663 beqz a1,800077ac <_ldtoa_r+0x1108> +800074e4: 02d12623 sw a3,44(sp) +800074e8: f6f00793 li a5,-145 +800074ec: 06f5c863 blt a1,a5,8000755c <_ldtoa_r+0xeb8> +800074f0: 0ec10513 addi a0,sp,236 +800074f4: d89fd0ef jal ra,8000527c +800074f8: 02c12683 lw a3,44(sp) +800074fc: 00050593 mv a1,a0 +80007500: 12010793 addi a5,sp,288 +80007504: 10410513 addi a0,sp,260 +80007508: 0ec15603 lhu a2,236(sp) +8000750c: 10815703 lhu a4,264(sp) +80007510: 2ee60a63 beq a2,a4,80007804 <_ldtoa_r+0x1160> +80007514: 00000713 li a4,0 +80007518: 00070613 mv a2,a4 +8000751c: 0007d703 lhu a4,0(a5) +80007520: 00055803 lhu a6,0(a0) +80007524: ffe78793 addi a5,a5,-2 +80007528: 40c70733 sub a4,a4,a2 +8000752c: 41070733 sub a4,a4,a6 +80007530: 01075613 srli a2,a4,0x10 +80007534: 00e79123 sh a4,2(a5) +80007538: 10a10713 addi a4,sp,266 +8000753c: 00167613 andi a2,a2,1 +80007540: ffe50513 addi a0,a0,-2 +80007544: fce79ce3 bne a5,a4,8000751c <_ldtoa_r+0xe78> +80007548: 00100613 li a2,1 +8000754c: 00090793 mv a5,s2 +80007550: 04000713 li a4,64 +80007554: 10810513 addi a0,sp,264 +80007558: 8bcfe0ef jal ra,80005614 +8000755c: 000c8593 mv a1,s9 +80007560: 10810513 addi a0,sp,264 +80007564: e24fe0ef jal ra,80005b88 +80007568: d15ff06f j 8000727c <_ldtoa_r+0xbd8> +8000756c: 00812783 lw a5,8(sp) +80007570: fff78493 addi s1,a5,-1 +80007574: b45ff06f j 800070b8 <_ldtoa_r+0xa14> +80007578: 00c12783 lw a5,12(sp) +8000757c: 12010223 sb zero,292(sp) +80007580: 000a8413 mv s0,s5 +80007584: 0007a023 sw zero,0(a5) +80007588: af9ff06f j 80007080 <_ldtoa_r+0x9dc> +8000758c: 000c8793 mv a5,s9 +80007590: 0e410713 addi a4,sp,228 +80007594: 00278793 addi a5,a5,2 +80007598: fe079f23 sh zero,-2(a5) +8000759c: fee79ce3 bne a5,a4,80007594 <_ldtoa_r+0xef0> +800075a0: cd1ff06f j 80007270 <_ldtoa_r+0xbcc> +800075a4: 01012783 lw a5,16(sp) +800075a8: 12410a93 addi s5,sp,292 +800075ac: 06078a63 beqz a5,80007620 <_ldtoa_r+0xf7c> +800075b0: 800155b7 lui a1,0x80015 +800075b4: e4058593 addi a1,a1,-448 # 80014e40 <__BSS_END__+0xffffe204> +800075b8: 000a8513 mv a0,s5 +800075bc: 000024b7 lui s1,0x2 +800075c0: 11c020ef jal ra,800096dc +800075c4: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> +800075c8: 8ddff06f j 80006ea4 <_ldtoa_r+0x800> +800075cc: 0e810b93 addi s7,sp,232 +800075d0: bd8ff06f j 800069a8 <_ldtoa_r+0x304> +800075d4: 03100793 li a5,49 +800075d8: fef90f23 sb a5,-2(s2) +800075dc: 00148493 addi s1,s1,1 +800075e0: 8b1ff06f j 80006e90 <_ldtoa_r+0x7ec> +800075e4: 00178793 addi a5,a5,1 +800075e8: 00f70023 sb a5,0(a4) +800075ec: 8a5ff06f j 80006e90 <_ldtoa_r+0x7ec> +800075f0: 12410a93 addi s5,sp,292 +800075f4: 800155b7 lui a1,0x80015 +800075f8: e5858593 addi a1,a1,-424 # 80014e58 <__BSS_END__+0xffffe21c> +800075fc: 000a8513 mv a0,s5 +80007600: 000024b7 lui s1,0x2 +80007604: 0d8020ef jal ra,800096dc +80007608: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> +8000760c: 899ff06f j 80006ea4 <_ldtoa_r+0x800> +80007610: 1ac15783 lhu a5,428(sp) +80007614: 12610c13 addi s8,sp,294 +80007618: 12710913 addi s2,sp,295 +8000761c: 815ff06f j 80006e30 <_ldtoa_r+0x78c> +80007620: 800155b7 lui a1,0x80015 +80007624: e4c58593 addi a1,a1,-436 # 80014e4c <__BSS_END__+0xffffe210> +80007628: 000a8513 mv a0,s5 +8000762c: 000024b7 lui s1,0x2 +80007630: 0ac020ef jal ra,800096dc +80007634: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> +80007638: 86dff06f j 80006ea4 <_ldtoa_r+0x800> +8000763c: 09810593 addi a1,sp,152 +80007640: 07c10513 addi a0,sp,124 +80007644: d44fe0ef jal ra,80005b88 +80007648: e60b0593 addi a1,s6,-416 +8000764c: 09810513 addi a0,sp,152 +80007650: af5fd0ef jal ra,80005144 +80007654: fe051663 bnez a0,80006e40 <_ldtoa_r+0x79c> +80007658: 82044ce3 bltz s0,80006e90 <_ldtoa_r+0x7ec> +8000765c: ffe94783 lbu a5,-2(s2) +80007660: fd278713 addi a4,a5,-46 +80007664: 00173713 seqz a4,a4 +80007668: fff74713 not a4,a4 +8000766c: 00ec0733 add a4,s8,a4 +80007670: 00074703 lbu a4,0(a4) +80007674: 00177713 andi a4,a4,1 +80007678: 80070ce3 beqz a4,80006e90 <_ldtoa_r+0x7ec> +8000767c: ffe90713 addi a4,s2,-2 +80007680: 07f7f793 andi a5,a5,127 +80007684: fccff06f j 80006e50 <_ldtoa_r+0x7ac> +80007688: 00178793 addi a5,a5,1 +8000768c: fef70fa3 sb a5,-1(a4) +80007690: 801ff06f j 80006e90 <_ldtoa_r+0x7ec> +80007694: 0d010413 addi s0,sp,208 +80007698: 00040593 mv a1,s0 +8000769c: 07c10513 addi a0,sp,124 +800076a0: 00004cb7 lui s9,0x4 +800076a4: 9a9fd0ef jal ra,8000504c +800076a8: 00000493 li s1,0 +800076ac: 0e810b93 addi s7,sp,232 +800076b0: 0cc10913 addi s2,sp,204 +800076b4: 0d210a93 addi s5,sp,210 +800076b8: ffec8c93 addi s9,s9,-2 # 3ffe <_start-0x7fffc002> +800076bc: 0e815783 lhu a5,232(sp) +800076c0: 0077f793 andi a5,a5,7 +800076c4: 0c079a63 bnez a5,80007798 <_ldtoa_r+0x10f4> +800076c8: 0b410713 addi a4,sp,180 +800076cc: 00040793 mv a5,s0 +800076d0: 0007d683 lhu a3,0(a5) +800076d4: 00278793 addi a5,a5,2 +800076d8: 00270713 addi a4,a4,2 +800076dc: fed71f23 sh a3,-2(a4) +800076e0: ff7798e3 bne a5,s7,800076d0 <_ldtoa_r+0x102c> +800076e4: 0b410513 addi a0,sp,180 +800076e8: 0c011623 sh zero,204(sp) +800076ec: f40fd0ef jal ra,80004e2c +800076f0: 0b410513 addi a0,sp,180 +800076f4: f38fd0ef jal ra,80004e2c +800076f8: 00000613 li a2,0 +800076fc: 00090693 mv a3,s2 +80007700: 000b8713 mv a4,s7 +80007704: 0006d583 lhu a1,0(a3) +80007708: 00075783 lhu a5,0(a4) +8000770c: ffe68693 addi a3,a3,-2 +80007710: ffe70713 addi a4,a4,-2 +80007714: 00b787b3 add a5,a5,a1 +80007718: 00c787b3 add a5,a5,a2 +8000771c: 0107d613 srli a2,a5,0x10 +80007720: 00f69123 sh a5,2(a3) +80007724: 00167613 andi a2,a2,1 +80007728: fd571ee3 bne a4,s5,80007704 <_ldtoa_r+0x1060> +8000772c: 0b615783 lhu a5,182(sp) +80007730: 0b815703 lhu a4,184(sp) +80007734: 00378793 addi a5,a5,3 +80007738: 0af11b23 sh a5,182(sp) +8000773c: 02070063 beqz a4,8000775c <_ldtoa_r+0x10b8> +80007740: 0b410513 addi a0,sp,180 +80007744: ee8fd0ef jal ra,80004e2c +80007748: 0b615783 lhu a5,182(sp) +8000774c: 0b815703 lhu a4,184(sp) +80007750: 00178793 addi a5,a5,1 +80007754: 0af11b23 sh a5,182(sp) +80007758: fe0714e3 bnez a4,80007740 <_ldtoa_r+0x109c> +8000775c: 0cc15783 lhu a5,204(sp) +80007760: 02079c63 bnez a5,80007798 <_ldtoa_r+0x10f4> +80007764: 0b615783 lhu a5,182(sp) +80007768: 02fce863 bltu s9,a5,80007798 <_ldtoa_r+0x10f4> +8000776c: 00040713 mv a4,s0 +80007770: 0b410793 addi a5,sp,180 +80007774: 0007d683 lhu a3,0(a5) +80007778: 00278793 addi a5,a5,2 +8000777c: 00270713 addi a4,a4,2 +80007780: fed71f23 sh a3,-2(a4) +80007784: ff2798e3 bne a5,s2,80007774 <_ldtoa_r+0x10d0> +80007788: 0e011423 sh zero,232(sp) +8000778c: fff48493 addi s1,s1,-1 +80007790: fd500793 li a5,-43 +80007794: f2f494e3 bne s1,a5,800076bc <_ldtoa_r+0x1018> +80007798: 07c10593 addi a1,sp,124 +8000779c: 00040513 mv a0,s0 +800077a0: be8fe0ef jal ra,80005b88 +800077a4: 16010913 addi s2,sp,352 +800077a8: 8f4ff06f j 8000689c <_ldtoa_r+0x1f8> +800077ac: 10c10713 addi a4,sp,268 +800077b0: 0f010793 addi a5,sp,240 +800077b4: 0007d883 lhu a7,0(a5) +800077b8: 00075603 lhu a2,0(a4) +800077bc: 00278793 addi a5,a5,2 +800077c0: 00270713 addi a4,a4,2 +800077c4: 02c89863 bne a7,a2,800077f4 <_ldtoa_r+0x1150> +800077c8: 10610613 addi a2,sp,262 +800077cc: fec794e3 bne a5,a2,800077b4 <_ldtoa_r+0x1110> +800077d0: 0ec15703 lhu a4,236(sp) +800077d4: 10815783 lhu a5,264(sp) +800077d8: 06f70263 beq a4,a5,8000783c <_ldtoa_r+0x1198> +800077dc: 000c8793 mv a5,s9 +800077e0: 0e410713 addi a4,sp,228 +800077e4: 00278793 addi a5,a5,2 +800077e8: fe079f23 sh zero,-2(a5) +800077ec: fee79ce3 bne a5,a4,800077e4 <_ldtoa_r+0x1140> +800077f0: a8dff06f j 8000727c <_ldtoa_r+0xbd8> +800077f4: 0d166663 bltu a2,a7,800078c0 <_ldtoa_r+0x121c> +800077f8: 12010793 addi a5,sp,288 +800077fc: 10410513 addi a0,sp,260 +80007800: d09ff06f j 80007508 <_ldtoa_r+0xe64> +80007804: 00000713 li a4,0 +80007808: 0ee10313 addi t1,sp,238 +8000780c: 0007d803 lhu a6,0(a5) +80007810: 00055603 lhu a2,0(a0) +80007814: ffe78793 addi a5,a5,-2 +80007818: ffe50513 addi a0,a0,-2 +8000781c: 01060633 add a2,a2,a6 +80007820: 00e60733 add a4,a2,a4 +80007824: 01075613 srli a2,a4,0x10 +80007828: 00e79123 sh a4,2(a5) +8000782c: 00167713 andi a4,a2,1 +80007830: fc651ee3 bne a0,t1,8000780c <_ldtoa_r+0x1168> +80007834: 00000613 li a2,0 +80007838: d15ff06f j 8000754c <_ldtoa_r+0xea8> +8000783c: 00068713 mv a4,a3 +80007840: 06069263 bnez a3,800078a4 <_ldtoa_r+0x1200> +80007844: 10e11783 lh a5,270(sp) +80007848: 0407ce63 bltz a5,800078a4 <_ldtoa_r+0x1200> +8000784c: 12010693 addi a3,sp,288 +80007850: 0200006f j 80007870 <_ldtoa_r+0x11cc> +80007854: 00f69023 sh a5,0(a3) +80007858: 00171713 slli a4,a4,0x1 +8000785c: 01071713 slli a4,a4,0x10 +80007860: ffe68693 addi a3,a3,-2 +80007864: 10a10793 addi a5,sp,266 +80007868: 01075713 srli a4,a4,0x10 +8000786c: cef688e3 beq a3,a5,8000755c <_ldtoa_r+0xeb8> +80007870: 0006d783 lhu a5,0(a3) +80007874: 01079613 slli a2,a5,0x10 +80007878: 41065613 srai a2,a2,0x10 +8000787c: 00179793 slli a5,a5,0x1 +80007880: 00065463 bgez a2,80007888 <_ldtoa_r+0x11e4> +80007884: 00176713 ori a4,a4,1 +80007888: 01079793 slli a5,a5,0x10 +8000788c: 0107d793 srli a5,a5,0x10 +80007890: 00277613 andi a2,a4,2 +80007894: 0017e593 ori a1,a5,1 +80007898: fa060ee3 beqz a2,80007854 <_ldtoa_r+0x11b0> +8000789c: 00b69023 sh a1,0(a3) +800078a0: fb9ff06f j 80007858 <_ldtoa_r+0x11b4> +800078a4: 10c10613 addi a2,sp,268 800078a8: 12010793 addi a5,sp,288 -800078ac: 10410513 addi a0,sp,260 -800078b0: d09ff06f j 800075b8 <_ldtoa_r+0xe64> -800078b4: 00000713 li a4,0 -800078b8: 0ee10313 addi t1,sp,238 -800078bc: 0007d803 lhu a6,0(a5) -800078c0: 00055603 lhu a2,0(a0) -800078c4: ffe78793 addi a5,a5,-2 -800078c8: ffe50513 addi a0,a0,-2 -800078cc: 01060633 add a2,a2,a6 -800078d0: 00e60733 add a4,a2,a4 -800078d4: 01075613 srli a2,a4,0x10 -800078d8: 00e79123 sh a4,2(a5) -800078dc: 00167713 andi a4,a2,1 -800078e0: fc651ee3 bne a0,t1,800078bc <_ldtoa_r+0x1168> -800078e4: 00000613 li a2,0 -800078e8: d15ff06f j 800075fc <_ldtoa_r+0xea8> -800078ec: 00068713 mv a4,a3 -800078f0: 06069263 bnez a3,80007954 <_ldtoa_r+0x1200> -800078f4: 10e11783 lh a5,270(sp) -800078f8: 0407ce63 bltz a5,80007954 <_ldtoa_r+0x1200> -800078fc: 12010693 addi a3,sp,288 -80007900: 0200006f j 80007920 <_ldtoa_r+0x11cc> -80007904: 00f69023 sh a5,0(a3) -80007908: 00171713 slli a4,a4,0x1 -8000790c: 01071713 slli a4,a4,0x10 -80007910: ffe68693 addi a3,a3,-2 -80007914: 10a10793 addi a5,sp,266 -80007918: 01075713 srli a4,a4,0x10 -8000791c: cef688e3 beq a3,a5,8000760c <_ldtoa_r+0xeb8> -80007920: 0006d783 lhu a5,0(a3) -80007924: 01079613 slli a2,a5,0x10 -80007928: 41065613 srai a2,a2,0x10 -8000792c: 00179793 slli a5,a5,0x1 -80007930: 00065463 bgez a2,80007938 <_ldtoa_r+0x11e4> -80007934: 00176713 ori a4,a4,1 -80007938: 01079793 slli a5,a5,0x10 -8000793c: 0107d793 srli a5,a5,0x10 -80007940: 00277613 andi a2,a4,2 -80007944: 0017e593 ori a1,a5,1 -80007948: fa060ee3 beqz a2,80007904 <_ldtoa_r+0x11b0> -8000794c: 00b69023 sh a1,0(a3) -80007950: fb9ff06f j 80007908 <_ldtoa_r+0x11b4> -80007954: 10c10613 addi a2,sp,268 -80007958: 12010793 addi a5,sp,288 -8000795c: 08071263 bnez a4,800079e0 <_ldtoa_r+0x128c> -80007960: 08c78263 beq a5,a2,800079e4 <_ldtoa_r+0x1290> -80007964: 00065703 lhu a4,0(a2) -80007968: 00260613 addi a2,a2,2 -8000796c: ff1ff06f j 8000795c <_ldtoa_r+0x1208> -80007970: 02412603 lw a2,36(sp) -80007974: 10810713 addi a4,sp,264 -80007978: 12010793 addi a5,sp,288 -8000797c: 00075503 lhu a0,0(a4) -80007980: 00270713 addi a4,a4,2 -80007984: 00260613 addi a2,a2,2 -80007988: fea61f23 sh a0,-2(a2) -8000798c: fef718e3 bne a4,a5,8000797c <_ldtoa_r+0x1228> -80007990: 12011e23 sh zero,316(sp) -80007994: 10810613 addi a2,sp,264 -80007998: 0ec10713 addi a4,sp,236 -8000799c: 10410513 addi a0,sp,260 -800079a0: 00075803 lhu a6,0(a4) -800079a4: 00270713 addi a4,a4,2 -800079a8: 00260613 addi a2,a2,2 -800079ac: ff061f23 sh a6,-2(a2) -800079b0: fea718e3 bne a4,a0,800079a0 <_ldtoa_r+0x124c> -800079b4: 02412703 lw a4,36(sp) -800079b8: 12011023 sh zero,288(sp) -800079bc: 0ec10893 addi a7,sp,236 -800079c0: 13c10613 addi a2,sp,316 -800079c4: 00075803 lhu a6,0(a4) -800079c8: 00270713 addi a4,a4,2 -800079cc: 00288893 addi a7,a7,2 -800079d0: ff089f23 sh a6,-2(a7) -800079d4: fec718e3 bne a4,a2,800079c4 <_ldtoa_r+0x1270> -800079d8: 10011223 sh zero,260(sp) -800079dc: bddff06f j 800075b8 <_ldtoa_r+0xe64> -800079e0: 00168513 addi a0,a3,1 -800079e4: 10a11523 sh a0,266(sp) -800079e8: c25ff06f j 8000760c <_ldtoa_r+0xeb8> +800078ac: 08071263 bnez a4,80007930 <_ldtoa_r+0x128c> +800078b0: 08c78263 beq a5,a2,80007934 <_ldtoa_r+0x1290> +800078b4: 00065703 lhu a4,0(a2) +800078b8: 00260613 addi a2,a2,2 +800078bc: ff1ff06f j 800078ac <_ldtoa_r+0x1208> +800078c0: 02412603 lw a2,36(sp) +800078c4: 10810713 addi a4,sp,264 +800078c8: 12010793 addi a5,sp,288 +800078cc: 00075503 lhu a0,0(a4) +800078d0: 00270713 addi a4,a4,2 +800078d4: 00260613 addi a2,a2,2 +800078d8: fea61f23 sh a0,-2(a2) +800078dc: fef718e3 bne a4,a5,800078cc <_ldtoa_r+0x1228> +800078e0: 12011e23 sh zero,316(sp) +800078e4: 10810613 addi a2,sp,264 +800078e8: 0ec10713 addi a4,sp,236 +800078ec: 10410513 addi a0,sp,260 +800078f0: 00075803 lhu a6,0(a4) +800078f4: 00270713 addi a4,a4,2 +800078f8: 00260613 addi a2,a2,2 +800078fc: ff061f23 sh a6,-2(a2) +80007900: fea718e3 bne a4,a0,800078f0 <_ldtoa_r+0x124c> +80007904: 02412703 lw a4,36(sp) +80007908: 12011023 sh zero,288(sp) +8000790c: 0ec10893 addi a7,sp,236 +80007910: 13c10613 addi a2,sp,316 +80007914: 00075803 lhu a6,0(a4) +80007918: 00270713 addi a4,a4,2 +8000791c: 00288893 addi a7,a7,2 +80007920: ff089f23 sh a6,-2(a7) +80007924: fec718e3 bne a4,a2,80007914 <_ldtoa_r+0x1270> +80007928: 10011223 sh zero,260(sp) +8000792c: bddff06f j 80007508 <_ldtoa_r+0xe64> +80007930: 00168513 addi a0,a3,1 +80007934: 10a11523 sh a0,266(sp) +80007938: c25ff06f j 8000755c <_ldtoa_r+0xeb8> -800079ec <_ldcheck>: -800079ec: 00852703 lw a4,8(a0) -800079f0: 00c52783 lw a5,12(a0) -800079f4: 00052603 lw a2,0(a0) -800079f8: 00452683 lw a3,4(a0) -800079fc: fc010113 addi sp,sp,-64 -80007a00: 00010513 mv a0,sp -80007a04: 01410593 addi a1,sp,20 -80007a08: 00e12423 sw a4,8(sp) -80007a0c: 00f12623 sw a5,12(sp) -80007a10: 02112e23 sw ra,60(sp) -80007a14: 00c12023 sw a2,0(sp) -80007a18: 00d12223 sw a3,4(sp) -80007a1c: bf5fe0ef jal ra,80006610 -80007a20: 02615783 lhu a5,38(sp) -80007a24: 00000513 li a0,0 -80007a28: fff7c793 not a5,a5 -80007a2c: 01179713 slli a4,a5,0x11 -80007a30: 00071a63 bnez a4,80007a44 <_ldcheck+0x58> -80007a34: 01410513 addi a0,sp,20 -80007a38: e14fd0ef jal ra,8000504c -80007a3c: 00153513 seqz a0,a0 -80007a40: 00150513 addi a0,a0,1 -80007a44: 03c12083 lw ra,60(sp) -80007a48: 04010113 addi sp,sp,64 -80007a4c: 00008067 ret +8000793c <_ldcheck>: +8000793c: 00852703 lw a4,8(a0) +80007940: 00c52783 lw a5,12(a0) +80007944: 00052603 lw a2,0(a0) +80007948: 00452683 lw a3,4(a0) +8000794c: fc010113 addi sp,sp,-64 +80007950: 00010513 mv a0,sp +80007954: 01410593 addi a1,sp,20 +80007958: 00e12423 sw a4,8(sp) +8000795c: 00f12623 sw a5,12(sp) +80007960: 02112e23 sw ra,60(sp) +80007964: 00c12023 sw a2,0(sp) +80007968: 00d12223 sw a3,4(sp) +8000796c: bf5fe0ef jal ra,80006560 +80007970: 02615783 lhu a5,38(sp) +80007974: 00000513 li a0,0 +80007978: fff7c793 not a5,a5 +8000797c: 01179713 slli a4,a5,0x11 +80007980: 00071a63 bnez a4,80007994 <_ldcheck+0x58> +80007984: 01410513 addi a0,sp,20 +80007988: e14fd0ef jal ra,80004f9c +8000798c: 00153513 seqz a0,a0 +80007990: 00150513 addi a0,a0,1 +80007994: 03c12083 lw ra,60(sp) +80007998: 04010113 addi sp,sp,64 +8000799c: 00008067 ret -80007a50 <__localeconv_l>: -80007a50: 0f050513 addi a0,a0,240 -80007a54: 00008067 ret +800079a0 <__localeconv_l>: +800079a0: 0f050513 addi a0,a0,240 +800079a4: 00008067 ret -80007a58 <_localeconv_r>: -80007a58: eb018513 addi a0,gp,-336 # 800166b8 <__global_locale+0xf0> -80007a5c: 00008067 ret +800079a8 <_localeconv_r>: +800079a8: 2b818513 addi a0,gp,696 # 80016ac0 <__global_locale+0xf0> +800079ac: 00008067 ret -80007a60 : -80007a60: eb018513 addi a0,gp,-336 # 800166b8 <__global_locale+0xf0> -80007a64: 00008067 ret +800079b0 : +800079b0: 2b818513 addi a0,gp,696 # 80016ac0 <__global_locale+0xf0> +800079b4: 00008067 ret -80007a68 <_setlocale_r>: -80007a68: ff010113 addi sp,sp,-16 -80007a6c: 00112623 sw ra,12(sp) -80007a70: 00812423 sw s0,8(sp) -80007a74: 00912223 sw s1,4(sp) -80007a78: 02060c63 beqz a2,80007ab0 <_setlocale_r+0x48> -80007a7c: 800155b7 lui a1,0x80015 -80007a80: 06c58593 addi a1,a1,108 # 8001506c <__BSS_END__+0xffffe43c> -80007a84: 00060513 mv a0,a2 -80007a88: 00060413 mv s0,a2 -80007a8c: 701010ef jal ra,8000998c -80007a90: 800154b7 lui s1,0x80015 -80007a94: 02051263 bnez a0,80007ab8 <_setlocale_r+0x50> -80007a98: 06848513 addi a0,s1,104 # 80015068 <__BSS_END__+0xffffe438> -80007a9c: 00c12083 lw ra,12(sp) -80007aa0: 00812403 lw s0,8(sp) -80007aa4: 00412483 lw s1,4(sp) -80007aa8: 01010113 addi sp,sp,16 -80007aac: 00008067 ret -80007ab0: 800154b7 lui s1,0x80015 -80007ab4: fe5ff06f j 80007a98 <_setlocale_r+0x30> -80007ab8: 06848593 addi a1,s1,104 # 80015068 <__BSS_END__+0xffffe438> -80007abc: 00040513 mv a0,s0 -80007ac0: 6cd010ef jal ra,8000998c -80007ac4: fc050ae3 beqz a0,80007a98 <_setlocale_r+0x30> -80007ac8: 800155b7 lui a1,0x80015 -80007acc: c5058593 addi a1,a1,-944 # 80014c50 <__BSS_END__+0xffffe020> -80007ad0: 00040513 mv a0,s0 -80007ad4: 6b9010ef jal ra,8000998c -80007ad8: fc0500e3 beqz a0,80007a98 <_setlocale_r+0x30> -80007adc: 00000513 li a0,0 -80007ae0: fbdff06f j 80007a9c <_setlocale_r+0x34> +800079b8 <__swhatbuf_r>: +800079b8: f9010113 addi sp,sp,-112 +800079bc: 06812423 sw s0,104(sp) +800079c0: 00058413 mv s0,a1 +800079c4: 00e59583 lh a1,14(a1) +800079c8: 06912223 sw s1,100(sp) +800079cc: 07212023 sw s2,96(sp) +800079d0: 06112623 sw ra,108(sp) +800079d4: 00060493 mv s1,a2 +800079d8: 00068913 mv s2,a3 +800079dc: 0405ca63 bltz a1,80007a30 <__swhatbuf_r+0x78> +800079e0: 00810613 addi a2,sp,8 +800079e4: 3e4060ef jal ra,8000ddc8 <_fstat_r> +800079e8: 04054463 bltz a0,80007a30 <__swhatbuf_r+0x78> +800079ec: 00c12703 lw a4,12(sp) +800079f0: 0000f7b7 lui a5,0xf +800079f4: 06c12083 lw ra,108(sp) +800079f8: 00e7f7b3 and a5,a5,a4 +800079fc: ffffe737 lui a4,0xffffe +80007a00: 00e787b3 add a5,a5,a4 +80007a04: 06812403 lw s0,104(sp) +80007a08: 0017b793 seqz a5,a5 +80007a0c: 00f92023 sw a5,0(s2) +80007a10: 40000793 li a5,1024 +80007a14: 00f4a023 sw a5,0(s1) +80007a18: 00001537 lui a0,0x1 +80007a1c: 06412483 lw s1,100(sp) +80007a20: 06012903 lw s2,96(sp) +80007a24: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800> +80007a28: 07010113 addi sp,sp,112 +80007a2c: 00008067 ret +80007a30: 00c45783 lhu a5,12(s0) +80007a34: 00092023 sw zero,0(s2) +80007a38: 0807f793 andi a5,a5,128 +80007a3c: 02078463 beqz a5,80007a64 <__swhatbuf_r+0xac> +80007a40: 06c12083 lw ra,108(sp) +80007a44: 06812403 lw s0,104(sp) +80007a48: 04000793 li a5,64 +80007a4c: 00f4a023 sw a5,0(s1) +80007a50: 06012903 lw s2,96(sp) +80007a54: 06412483 lw s1,100(sp) +80007a58: 00000513 li a0,0 +80007a5c: 07010113 addi sp,sp,112 +80007a60: 00008067 ret +80007a64: 06c12083 lw ra,108(sp) +80007a68: 06812403 lw s0,104(sp) +80007a6c: 40000793 li a5,1024 +80007a70: 00f4a023 sw a5,0(s1) +80007a74: 06012903 lw s2,96(sp) +80007a78: 06412483 lw s1,100(sp) +80007a7c: 00000513 li a0,0 +80007a80: 07010113 addi sp,sp,112 +80007a84: 00008067 ret -80007ae4 <__locale_mb_cur_max>: -80007ae4: ee81c503 lbu a0,-280(gp) # 800166f0 <__global_locale+0x128> -80007ae8: 00008067 ret +80007a88 <__smakebuf_r>: +80007a88: 00c5d783 lhu a5,12(a1) +80007a8c: fe010113 addi sp,sp,-32 +80007a90: 00812c23 sw s0,24(sp) +80007a94: 00112e23 sw ra,28(sp) +80007a98: 00912a23 sw s1,20(sp) +80007a9c: 01212823 sw s2,16(sp) +80007aa0: 0027f793 andi a5,a5,2 +80007aa4: 00058413 mv s0,a1 +80007aa8: 02078863 beqz a5,80007ad8 <__smakebuf_r+0x50> +80007aac: 04358793 addi a5,a1,67 +80007ab0: 00f5a023 sw a5,0(a1) +80007ab4: 00f5a823 sw a5,16(a1) +80007ab8: 00100793 li a5,1 +80007abc: 00f5aa23 sw a5,20(a1) +80007ac0: 01c12083 lw ra,28(sp) +80007ac4: 01812403 lw s0,24(sp) +80007ac8: 01412483 lw s1,20(sp) +80007acc: 01012903 lw s2,16(sp) +80007ad0: 02010113 addi sp,sp,32 +80007ad4: 00008067 ret +80007ad8: 00c10693 addi a3,sp,12 +80007adc: 00810613 addi a2,sp,8 +80007ae0: 00050493 mv s1,a0 +80007ae4: ed5ff0ef jal ra,800079b8 <__swhatbuf_r> +80007ae8: 00812583 lw a1,8(sp) +80007aec: 00050913 mv s2,a0 +80007af0: 00048513 mv a0,s1 +80007af4: 0b4000ef jal ra,80007ba8 <_malloc_r> +80007af8: 00c41783 lh a5,12(s0) +80007afc: 04050863 beqz a0,80007b4c <__smakebuf_r+0xc4> +80007b00: 80004737 lui a4,0x80004 +80007b04: 4f470713 addi a4,a4,1268 # 800044f4 <__BSS_END__+0xfffed8b8> +80007b08: 02e4ae23 sw a4,60(s1) +80007b0c: 00812703 lw a4,8(sp) +80007b10: 00c12683 lw a3,12(sp) +80007b14: 0807e793 ori a5,a5,128 +80007b18: 00f41623 sh a5,12(s0) +80007b1c: 00a42023 sw a0,0(s0) +80007b20: 00a42823 sw a0,16(s0) +80007b24: 00e42a23 sw a4,20(s0) +80007b28: 04069863 bnez a3,80007b78 <__smakebuf_r+0xf0> +80007b2c: 0127e7b3 or a5,a5,s2 +80007b30: 01c12083 lw ra,28(sp) +80007b34: 00f41623 sh a5,12(s0) +80007b38: 01812403 lw s0,24(sp) +80007b3c: 01412483 lw s1,20(sp) +80007b40: 01012903 lw s2,16(sp) +80007b44: 02010113 addi sp,sp,32 +80007b48: 00008067 ret +80007b4c: 2007f713 andi a4,a5,512 +80007b50: f60718e3 bnez a4,80007ac0 <__smakebuf_r+0x38> +80007b54: ffc7f793 andi a5,a5,-4 +80007b58: 0027e793 ori a5,a5,2 +80007b5c: 04340713 addi a4,s0,67 +80007b60: 00f41623 sh a5,12(s0) +80007b64: 00100793 li a5,1 +80007b68: 00e42023 sw a4,0(s0) +80007b6c: 00e42823 sw a4,16(s0) +80007b70: 00f42a23 sw a5,20(s0) +80007b74: f4dff06f j 80007ac0 <__smakebuf_r+0x38> +80007b78: 00e41583 lh a1,14(s0) +80007b7c: 00048513 mv a0,s1 +80007b80: 754060ef jal ra,8000e2d4 <_isatty_r> +80007b84: 00051663 bnez a0,80007b90 <__smakebuf_r+0x108> +80007b88: 00c41783 lh a5,12(s0) +80007b8c: fa1ff06f j 80007b2c <__smakebuf_r+0xa4> +80007b90: 00c45703 lhu a4,12(s0) +80007b94: ffc77713 andi a4,a4,-4 +80007b98: 00176713 ori a4,a4,1 +80007b9c: 01071793 slli a5,a4,0x10 +80007ba0: 4107d793 srai a5,a5,0x10 +80007ba4: f89ff06f j 80007b2c <__smakebuf_r+0xa4> -80007aec : -80007aec: 00050793 mv a5,a0 -80007af0: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -80007af4: 00058613 mv a2,a1 -80007af8: 00078593 mv a1,a5 -80007afc: f6dff06f j 80007a68 <_setlocale_r> +80007ba8 <_malloc_r>: +80007ba8: fd010113 addi sp,sp,-48 +80007bac: 01312e23 sw s3,28(sp) +80007bb0: 02112623 sw ra,44(sp) +80007bb4: 02812423 sw s0,40(sp) +80007bb8: 02912223 sw s1,36(sp) +80007bbc: 03212023 sw s2,32(sp) +80007bc0: 01412c23 sw s4,24(sp) +80007bc4: 01512a23 sw s5,20(sp) +80007bc8: 01612823 sw s6,16(sp) +80007bcc: 01712623 sw s7,12(sp) +80007bd0: 01812423 sw s8,8(sp) +80007bd4: 01912223 sw s9,4(sp) +80007bd8: 00b58793 addi a5,a1,11 +80007bdc: 01600713 li a4,22 +80007be0: 00050993 mv s3,a0 +80007be4: 06f76463 bltu a4,a5,80007c4c <_malloc_r+0xa4> +80007be8: 01000793 li a5,16 +80007bec: 1eb7e263 bltu a5,a1,80007dd0 <_malloc_r+0x228> +80007bf0: 101000ef jal ra,800084f0 <__malloc_lock> +80007bf4: 01000493 li s1,16 +80007bf8: 00200613 li a2,2 +80007bfc: 01800793 li a5,24 +80007c00: dc018913 addi s2,gp,-576 # 800165c8 <__malloc_av_> +80007c04: 00f907b3 add a5,s2,a5 +80007c08: 0047a403 lw s0,4(a5) # f004 <_start-0x7fff0ffc> +80007c0c: ff878713 addi a4,a5,-8 +80007c10: 20e40863 beq s0,a4,80007e20 <_malloc_r+0x278> +80007c14: 00442783 lw a5,4(s0) +80007c18: 00c42683 lw a3,12(s0) +80007c1c: 00842603 lw a2,8(s0) +80007c20: ffc7f793 andi a5,a5,-4 +80007c24: 00f407b3 add a5,s0,a5 +80007c28: 0047a703 lw a4,4(a5) +80007c2c: 00d62623 sw a3,12(a2) +80007c30: 00c6a423 sw a2,8(a3) +80007c34: 00176713 ori a4,a4,1 +80007c38: 00098513 mv a0,s3 +80007c3c: 00e7a223 sw a4,4(a5) +80007c40: 0b5000ef jal ra,800084f4 <__malloc_unlock> +80007c44: 00840513 addi a0,s0,8 +80007c48: 1940006f j 80007ddc <_malloc_r+0x234> +80007c4c: ff87f493 andi s1,a5,-8 +80007c50: 1807c063 bltz a5,80007dd0 <_malloc_r+0x228> +80007c54: 16b4ee63 bltu s1,a1,80007dd0 <_malloc_r+0x228> +80007c58: 099000ef jal ra,800084f0 <__malloc_lock> +80007c5c: 1f700793 li a5,503 +80007c60: 4497fa63 bgeu a5,s1,800080b4 <_malloc_r+0x50c> +80007c64: 0094d793 srli a5,s1,0x9 +80007c68: 1a078463 beqz a5,80007e10 <_malloc_r+0x268> +80007c6c: 00400713 li a4,4 +80007c70: 3cf76063 bltu a4,a5,80008030 <_malloc_r+0x488> +80007c74: 0064d793 srli a5,s1,0x6 +80007c78: 03978613 addi a2,a5,57 +80007c7c: 03878513 addi a0,a5,56 +80007c80: 00361693 slli a3,a2,0x3 +80007c84: dc018913 addi s2,gp,-576 # 800165c8 <__malloc_av_> +80007c88: 00d906b3 add a3,s2,a3 +80007c8c: 0046a403 lw s0,4(a3) +80007c90: ff868693 addi a3,a3,-8 +80007c94: 02868663 beq a3,s0,80007cc0 <_malloc_r+0x118> +80007c98: 00f00593 li a1,15 +80007c9c: 0100006f j 80007cac <_malloc_r+0x104> +80007ca0: 32075263 bgez a4,80007fc4 <_malloc_r+0x41c> +80007ca4: 00c42403 lw s0,12(s0) +80007ca8: 00868c63 beq a3,s0,80007cc0 <_malloc_r+0x118> +80007cac: 00442783 lw a5,4(s0) +80007cb0: ffc7f793 andi a5,a5,-4 +80007cb4: 40978733 sub a4,a5,s1 +80007cb8: fee5d4e3 bge a1,a4,80007ca0 <_malloc_r+0xf8> +80007cbc: 00050613 mv a2,a0 +80007cc0: 01092403 lw s0,16(s2) +80007cc4: 00890893 addi a7,s2,8 +80007cc8: 17140863 beq s0,a7,80007e38 <_malloc_r+0x290> +80007ccc: 00442503 lw a0,4(s0) +80007cd0: 00f00693 li a3,15 +80007cd4: ffc57513 andi a0,a0,-4 +80007cd8: 409507b3 sub a5,a0,s1 +80007cdc: 40f6c263 blt a3,a5,800080e0 <_malloc_r+0x538> +80007ce0: 01192a23 sw a7,20(s2) +80007ce4: 01192823 sw a7,16(s2) +80007ce8: 3c07dc63 bgez a5,800080c0 <_malloc_r+0x518> +80007cec: 1ff00793 li a5,511 +80007cf0: 2ea7e063 bltu a5,a0,80007fd0 <_malloc_r+0x428> +80007cf4: ff857793 andi a5,a0,-8 +80007cf8: 00878793 addi a5,a5,8 +80007cfc: 00492583 lw a1,4(s2) +80007d00: 00f907b3 add a5,s2,a5 +80007d04: 0007a683 lw a3,0(a5) +80007d08: 00555513 srli a0,a0,0x5 +80007d0c: 00100713 li a4,1 +80007d10: 00a71733 sll a4,a4,a0 +80007d14: 00b76733 or a4,a4,a1 +80007d18: ff878593 addi a1,a5,-8 +80007d1c: 00b42623 sw a1,12(s0) +80007d20: 00d42423 sw a3,8(s0) +80007d24: 00e92223 sw a4,4(s2) +80007d28: 0087a023 sw s0,0(a5) +80007d2c: 0086a623 sw s0,12(a3) +80007d30: 40265793 srai a5,a2,0x2 +80007d34: 00100593 li a1,1 +80007d38: 00f595b3 sll a1,a1,a5 +80007d3c: 10b76863 bltu a4,a1,80007e4c <_malloc_r+0x2a4> +80007d40: 00e5f7b3 and a5,a1,a4 +80007d44: 02079463 bnez a5,80007d6c <_malloc_r+0x1c4> +80007d48: 00159593 slli a1,a1,0x1 +80007d4c: ffc67613 andi a2,a2,-4 +80007d50: 00e5f7b3 and a5,a1,a4 +80007d54: 00460613 addi a2,a2,4 +80007d58: 00079a63 bnez a5,80007d6c <_malloc_r+0x1c4> +80007d5c: 00159593 slli a1,a1,0x1 +80007d60: 00e5f7b3 and a5,a1,a4 +80007d64: 00460613 addi a2,a2,4 +80007d68: fe078ae3 beqz a5,80007d5c <_malloc_r+0x1b4> +80007d6c: 00f00813 li a6,15 +80007d70: 00361313 slli t1,a2,0x3 +80007d74: 00690333 add t1,s2,t1 +80007d78: 00030513 mv a0,t1 +80007d7c: 00c52783 lw a5,12(a0) +80007d80: 00060e13 mv t3,a2 +80007d84: 2cf50863 beq a0,a5,80008054 <_malloc_r+0x4ac> +80007d88: 0047a703 lw a4,4(a5) +80007d8c: 00078413 mv s0,a5 +80007d90: 00c7a783 lw a5,12(a5) +80007d94: ffc77713 andi a4,a4,-4 +80007d98: 409706b3 sub a3,a4,s1 +80007d9c: 2cd84863 blt a6,a3,8000806c <_malloc_r+0x4c4> +80007da0: fe06c2e3 bltz a3,80007d84 <_malloc_r+0x1dc> +80007da4: 00e40733 add a4,s0,a4 +80007da8: 00472683 lw a3,4(a4) +80007dac: 00842603 lw a2,8(s0) +80007db0: 00098513 mv a0,s3 +80007db4: 0016e693 ori a3,a3,1 +80007db8: 00d72223 sw a3,4(a4) +80007dbc: 00f62623 sw a5,12(a2) +80007dc0: 00c7a423 sw a2,8(a5) +80007dc4: 730000ef jal ra,800084f4 <__malloc_unlock> +80007dc8: 00840513 addi a0,s0,8 +80007dcc: 0100006f j 80007ddc <_malloc_r+0x234> +80007dd0: 00c00793 li a5,12 +80007dd4: 00f9a023 sw a5,0(s3) +80007dd8: 00000513 li a0,0 +80007ddc: 02c12083 lw ra,44(sp) +80007de0: 02812403 lw s0,40(sp) +80007de4: 02412483 lw s1,36(sp) +80007de8: 02012903 lw s2,32(sp) +80007dec: 01c12983 lw s3,28(sp) +80007df0: 01812a03 lw s4,24(sp) +80007df4: 01412a83 lw s5,20(sp) +80007df8: 01012b03 lw s6,16(sp) +80007dfc: 00c12b83 lw s7,12(sp) +80007e00: 00812c03 lw s8,8(sp) +80007e04: 00412c83 lw s9,4(sp) +80007e08: 03010113 addi sp,sp,48 +80007e0c: 00008067 ret +80007e10: 20000693 li a3,512 +80007e14: 04000613 li a2,64 +80007e18: 03f00513 li a0,63 +80007e1c: e69ff06f j 80007c84 <_malloc_r+0xdc> +80007e20: 00c7a403 lw s0,12(a5) +80007e24: 00260613 addi a2,a2,2 +80007e28: de8796e3 bne a5,s0,80007c14 <_malloc_r+0x6c> +80007e2c: 01092403 lw s0,16(s2) +80007e30: 00890893 addi a7,s2,8 +80007e34: e9141ce3 bne s0,a7,80007ccc <_malloc_r+0x124> +80007e38: 00492703 lw a4,4(s2) +80007e3c: 40265793 srai a5,a2,0x2 +80007e40: 00100593 li a1,1 +80007e44: 00f595b3 sll a1,a1,a5 +80007e48: eeb77ce3 bgeu a4,a1,80007d40 <_malloc_r+0x198> +80007e4c: 00892403 lw s0,8(s2) +80007e50: 00442a83 lw s5,4(s0) +80007e54: ffcafb13 andi s6,s5,-4 +80007e58: 009b6863 bltu s6,s1,80007e68 <_malloc_r+0x2c0> +80007e5c: 409b07b3 sub a5,s6,s1 +80007e60: 00f00713 li a4,15 +80007e64: 12f74c63 blt a4,a5,80007f9c <_malloc_r+0x3f4> +80007e68: 3741aa83 lw s5,884(gp) # 80016b7c <__malloc_top_pad> +80007e6c: 3641a703 lw a4,868(gp) # 80016b6c <__malloc_sbrk_base> +80007e70: fff00793 li a5,-1 +80007e74: 01640a33 add s4,s0,s6 +80007e78: 01548ab3 add s5,s1,s5 +80007e7c: 34f70463 beq a4,a5,800081c4 <_malloc_r+0x61c> +80007e80: 000017b7 lui a5,0x1 +80007e84: 00f78793 addi a5,a5,15 # 100f <_start-0x7fffeff1> +80007e88: 00fa8ab3 add s5,s5,a5 +80007e8c: fffff7b7 lui a5,0xfffff +80007e90: 00fafab3 and s5,s5,a5 +80007e94: 000a8593 mv a1,s5 +80007e98: 00098513 mv a0,s3 +80007e9c: 778010ef jal ra,80009614 <_sbrk_r> +80007ea0: fff00793 li a5,-1 +80007ea4: 00050b93 mv s7,a0 +80007ea8: 28f50663 beq a0,a5,80008134 <_malloc_r+0x58c> +80007eac: 29456263 bltu a0,s4,80008130 <_malloc_r+0x588> +80007eb0: 3c018c13 addi s8,gp,960 # 80016bc8 <__malloc_current_mallinfo> +80007eb4: 000c2583 lw a1,0(s8) # 1000 <_start-0x7ffff000> +80007eb8: 00ba85b3 add a1,s5,a1 +80007ebc: 00bc2023 sw a1,0(s8) +80007ec0: 00058793 mv a5,a1 +80007ec4: 38aa0e63 beq s4,a0,80008260 <_malloc_r+0x6b8> +80007ec8: 3641a683 lw a3,868(gp) # 80016b6c <__malloc_sbrk_base> +80007ecc: fff00713 li a4,-1 +80007ed0: 3ae68663 beq a3,a4,8000827c <_malloc_r+0x6d4> +80007ed4: 414b8a33 sub s4,s7,s4 +80007ed8: 00fa07b3 add a5,s4,a5 +80007edc: 00fc2023 sw a5,0(s8) +80007ee0: 007bfc93 andi s9,s7,7 +80007ee4: 300c8263 beqz s9,800081e8 <_malloc_r+0x640> +80007ee8: 000017b7 lui a5,0x1 +80007eec: 419b8bb3 sub s7,s7,s9 +80007ef0: 00878593 addi a1,a5,8 # 1008 <_start-0x7fffeff8> +80007ef4: 008b8b93 addi s7,s7,8 +80007ef8: 419585b3 sub a1,a1,s9 +80007efc: 015b8ab3 add s5,s7,s5 +80007f00: fff78793 addi a5,a5,-1 +80007f04: 415585b3 sub a1,a1,s5 +80007f08: 00f5fa33 and s4,a1,a5 +80007f0c: 000a0593 mv a1,s4 +80007f10: 00098513 mv a0,s3 +80007f14: 700010ef jal ra,80009614 <_sbrk_r> +80007f18: fff00793 li a5,-1 +80007f1c: 3af50a63 beq a0,a5,800082d0 <_malloc_r+0x728> +80007f20: 41750533 sub a0,a0,s7 +80007f24: 01450ab3 add s5,a0,s4 +80007f28: 000c2583 lw a1,0(s8) +80007f2c: 01792423 sw s7,8(s2) +80007f30: 001aea93 ori s5,s5,1 +80007f34: 00ba05b3 add a1,s4,a1 +80007f38: 00bc2023 sw a1,0(s8) +80007f3c: 015ba223 sw s5,4(s7) +80007f40: 35240263 beq s0,s2,80008284 <_malloc_r+0x6dc> +80007f44: 00f00693 li a3,15 +80007f48: 3566f263 bgeu a3,s6,8000828c <_malloc_r+0x6e4> +80007f4c: 00442703 lw a4,4(s0) +80007f50: ff4b0793 addi a5,s6,-12 +80007f54: ff87f793 andi a5,a5,-8 +80007f58: 00177713 andi a4,a4,1 +80007f5c: 00f76733 or a4,a4,a5 +80007f60: 00e42223 sw a4,4(s0) +80007f64: 00500613 li a2,5 +80007f68: 00f40733 add a4,s0,a5 +80007f6c: 00c72223 sw a2,4(a4) +80007f70: 00c72423 sw a2,8(a4) +80007f74: 36f6e863 bltu a3,a5,800082e4 <_malloc_r+0x73c> +80007f78: 004baa83 lw s5,4(s7) +80007f7c: 000b8413 mv s0,s7 +80007f80: 3701a703 lw a4,880(gp) # 80016b78 <__malloc_max_sbrked_mem> +80007f84: 00b77463 bgeu a4,a1,80007f8c <_malloc_r+0x3e4> +80007f88: 36b1a823 sw a1,880(gp) # 80016b78 <__malloc_max_sbrked_mem> +80007f8c: 36c1a703 lw a4,876(gp) # 80016b74 <_edata> +80007f90: 1ab77663 bgeu a4,a1,8000813c <_malloc_r+0x594> +80007f94: 36b1a623 sw a1,876(gp) # 80016b74 <_edata> +80007f98: 1a40006f j 8000813c <_malloc_r+0x594> +80007f9c: 0014e713 ori a4,s1,1 +80007fa0: 00e42223 sw a4,4(s0) +80007fa4: 009404b3 add s1,s0,s1 +80007fa8: 00992423 sw s1,8(s2) +80007fac: 0017e793 ori a5,a5,1 +80007fb0: 00098513 mv a0,s3 +80007fb4: 00f4a223 sw a5,4(s1) +80007fb8: 53c000ef jal ra,800084f4 <__malloc_unlock> +80007fbc: 00840513 addi a0,s0,8 +80007fc0: e1dff06f j 80007ddc <_malloc_r+0x234> +80007fc4: 00c42683 lw a3,12(s0) +80007fc8: 00842603 lw a2,8(s0) +80007fcc: c59ff06f j 80007c24 <_malloc_r+0x7c> +80007fd0: 00955793 srli a5,a0,0x9 +80007fd4: 00400713 li a4,4 +80007fd8: 14f77263 bgeu a4,a5,8000811c <_malloc_r+0x574> +80007fdc: 01400713 li a4,20 +80007fe0: 22f76a63 bltu a4,a5,80008214 <_malloc_r+0x66c> +80007fe4: 05c78693 addi a3,a5,92 +80007fe8: 05b78593 addi a1,a5,91 +80007fec: 00369693 slli a3,a3,0x3 +80007ff0: 00d906b3 add a3,s2,a3 +80007ff4: 0006a783 lw a5,0(a3) +80007ff8: ff868693 addi a3,a3,-8 +80007ffc: 1cf68863 beq a3,a5,800081cc <_malloc_r+0x624> +80008000: 0047a703 lw a4,4(a5) +80008004: ffc77713 andi a4,a4,-4 +80008008: 00e57663 bgeu a0,a4,80008014 <_malloc_r+0x46c> +8000800c: 0087a783 lw a5,8(a5) +80008010: fef698e3 bne a3,a5,80008000 <_malloc_r+0x458> +80008014: 00c7a683 lw a3,12(a5) +80008018: 00492703 lw a4,4(s2) +8000801c: 00d42623 sw a3,12(s0) +80008020: 00f42423 sw a5,8(s0) +80008024: 0086a423 sw s0,8(a3) +80008028: 0087a623 sw s0,12(a5) +8000802c: d05ff06f j 80007d30 <_malloc_r+0x188> +80008030: 01400713 li a4,20 +80008034: 12f77663 bgeu a4,a5,80008160 <_malloc_r+0x5b8> +80008038: 05400713 li a4,84 +8000803c: 1ef76a63 bltu a4,a5,80008230 <_malloc_r+0x688> +80008040: 00c4d793 srli a5,s1,0xc +80008044: 06f78613 addi a2,a5,111 +80008048: 06e78513 addi a0,a5,110 +8000804c: 00361693 slli a3,a2,0x3 +80008050: c35ff06f j 80007c84 <_malloc_r+0xdc> +80008054: 001e0e13 addi t3,t3,1 +80008058: 003e7793 andi a5,t3,3 +8000805c: 00850513 addi a0,a0,8 +80008060: 10078e63 beqz a5,8000817c <_malloc_r+0x5d4> +80008064: 00c52783 lw a5,12(a0) +80008068: d1dff06f j 80007d84 <_malloc_r+0x1dc> +8000806c: 00842603 lw a2,8(s0) +80008070: 0014e593 ori a1,s1,1 +80008074: 00b42223 sw a1,4(s0) +80008078: 00f62623 sw a5,12(a2) +8000807c: 00c7a423 sw a2,8(a5) +80008080: 009404b3 add s1,s0,s1 +80008084: 00992a23 sw s1,20(s2) +80008088: 00992823 sw s1,16(s2) +8000808c: 0016e793 ori a5,a3,1 +80008090: 0114a623 sw a7,12(s1) +80008094: 0114a423 sw a7,8(s1) +80008098: 00f4a223 sw a5,4(s1) +8000809c: 00e40733 add a4,s0,a4 +800080a0: 00098513 mv a0,s3 +800080a4: 00d72023 sw a3,0(a4) +800080a8: 44c000ef jal ra,800084f4 <__malloc_unlock> +800080ac: 00840513 addi a0,s0,8 +800080b0: d2dff06f j 80007ddc <_malloc_r+0x234> +800080b4: 0034d613 srli a2,s1,0x3 +800080b8: 00848793 addi a5,s1,8 +800080bc: b45ff06f j 80007c00 <_malloc_r+0x58> +800080c0: 00a40733 add a4,s0,a0 +800080c4: 00472783 lw a5,4(a4) +800080c8: 00098513 mv a0,s3 +800080cc: 0017e793 ori a5,a5,1 +800080d0: 00f72223 sw a5,4(a4) +800080d4: 420000ef jal ra,800084f4 <__malloc_unlock> +800080d8: 00840513 addi a0,s0,8 +800080dc: d01ff06f j 80007ddc <_malloc_r+0x234> +800080e0: 0014e713 ori a4,s1,1 +800080e4: 00e42223 sw a4,4(s0) +800080e8: 009404b3 add s1,s0,s1 +800080ec: 00992a23 sw s1,20(s2) +800080f0: 00992823 sw s1,16(s2) +800080f4: 0017e713 ori a4,a5,1 +800080f8: 0114a623 sw a7,12(s1) +800080fc: 0114a423 sw a7,8(s1) +80008100: 00e4a223 sw a4,4(s1) +80008104: 00a40533 add a0,s0,a0 +80008108: 00f52023 sw a5,0(a0) +8000810c: 00098513 mv a0,s3 +80008110: 3e4000ef jal ra,800084f4 <__malloc_unlock> +80008114: 00840513 addi a0,s0,8 +80008118: cc5ff06f j 80007ddc <_malloc_r+0x234> +8000811c: 00655793 srli a5,a0,0x6 +80008120: 03978693 addi a3,a5,57 +80008124: 03878593 addi a1,a5,56 +80008128: 00369693 slli a3,a3,0x3 +8000812c: ec5ff06f j 80007ff0 <_malloc_r+0x448> +80008130: 11240e63 beq s0,s2,8000824c <_malloc_r+0x6a4> +80008134: 00892403 lw s0,8(s2) +80008138: 00442a83 lw s5,4(s0) +8000813c: ffcafa93 andi s5,s5,-4 +80008140: 409a87b3 sub a5,s5,s1 +80008144: 009ae663 bltu s5,s1,80008150 <_malloc_r+0x5a8> +80008148: 00f00713 li a4,15 +8000814c: e4f748e3 blt a4,a5,80007f9c <_malloc_r+0x3f4> +80008150: 00098513 mv a0,s3 +80008154: 3a0000ef jal ra,800084f4 <__malloc_unlock> +80008158: 00000513 li a0,0 +8000815c: c81ff06f j 80007ddc <_malloc_r+0x234> +80008160: 05c78613 addi a2,a5,92 +80008164: 05b78513 addi a0,a5,91 +80008168: 00361693 slli a3,a2,0x3 +8000816c: b19ff06f j 80007c84 <_malloc_r+0xdc> +80008170: 00832783 lw a5,8(t1) +80008174: fff60613 addi a2,a2,-1 +80008178: 1c679063 bne a5,t1,80008338 <_malloc_r+0x790> +8000817c: 00367793 andi a5,a2,3 +80008180: ff830313 addi t1,t1,-8 +80008184: fe0796e3 bnez a5,80008170 <_malloc_r+0x5c8> +80008188: 00492703 lw a4,4(s2) +8000818c: fff5c793 not a5,a1 +80008190: 00e7f7b3 and a5,a5,a4 +80008194: 00f92223 sw a5,4(s2) +80008198: 00159593 slli a1,a1,0x1 +8000819c: cab7e8e3 bltu a5,a1,80007e4c <_malloc_r+0x2a4> +800081a0: ca0586e3 beqz a1,80007e4c <_malloc_r+0x2a4> +800081a4: 00f5f733 and a4,a1,a5 +800081a8: 00071a63 bnez a4,800081bc <_malloc_r+0x614> +800081ac: 00159593 slli a1,a1,0x1 +800081b0: 00f5f733 and a4,a1,a5 +800081b4: 004e0e13 addi t3,t3,4 +800081b8: fe070ae3 beqz a4,800081ac <_malloc_r+0x604> +800081bc: 000e0613 mv a2,t3 +800081c0: bb1ff06f j 80007d70 <_malloc_r+0x1c8> +800081c4: 010a8a93 addi s5,s5,16 # fffff010 <__BSS_END__+0x7ffe83d4> +800081c8: ccdff06f j 80007e94 <_malloc_r+0x2ec> +800081cc: 00492503 lw a0,4(s2) +800081d0: 4025d593 srai a1,a1,0x2 +800081d4: 00100713 li a4,1 +800081d8: 00b71733 sll a4,a4,a1 +800081dc: 00a76733 or a4,a4,a0 +800081e0: 00e92223 sw a4,4(s2) +800081e4: e39ff06f j 8000801c <_malloc_r+0x474> +800081e8: 015b85b3 add a1,s7,s5 +800081ec: 40b005b3 neg a1,a1 +800081f0: 01459593 slli a1,a1,0x14 +800081f4: 0145da13 srli s4,a1,0x14 +800081f8: 000a0593 mv a1,s4 +800081fc: 00098513 mv a0,s3 +80008200: 414010ef jal ra,80009614 <_sbrk_r> +80008204: fff00793 li a5,-1 +80008208: d0f51ce3 bne a0,a5,80007f20 <_malloc_r+0x378> +8000820c: 00000a13 li s4,0 +80008210: d19ff06f j 80007f28 <_malloc_r+0x380> +80008214: 05400713 li a4,84 +80008218: 08f76063 bltu a4,a5,80008298 <_malloc_r+0x6f0> +8000821c: 00c55793 srli a5,a0,0xc +80008220: 06f78693 addi a3,a5,111 +80008224: 06e78593 addi a1,a5,110 +80008228: 00369693 slli a3,a3,0x3 +8000822c: dc5ff06f j 80007ff0 <_malloc_r+0x448> +80008230: 15400713 li a4,340 +80008234: 08f76063 bltu a4,a5,800082b4 <_malloc_r+0x70c> +80008238: 00f4d793 srli a5,s1,0xf +8000823c: 07878613 addi a2,a5,120 +80008240: 07778513 addi a0,a5,119 +80008244: 00361693 slli a3,a2,0x3 +80008248: a3dff06f j 80007c84 <_malloc_r+0xdc> +8000824c: 3c018c13 addi s8,gp,960 # 80016bc8 <__malloc_current_mallinfo> +80008250: 000c2783 lw a5,0(s8) +80008254: 00fa87b3 add a5,s5,a5 +80008258: 00fc2023 sw a5,0(s8) +8000825c: c6dff06f j 80007ec8 <_malloc_r+0x320> +80008260: 014a1713 slli a4,s4,0x14 +80008264: c60712e3 bnez a4,80007ec8 <_malloc_r+0x320> +80008268: 00892403 lw s0,8(s2) +8000826c: 015b0ab3 add s5,s6,s5 +80008270: 001aea93 ori s5,s5,1 +80008274: 01542223 sw s5,4(s0) +80008278: d09ff06f j 80007f80 <_malloc_r+0x3d8> +8000827c: 3771a223 sw s7,868(gp) # 80016b6c <__malloc_sbrk_base> +80008280: c61ff06f j 80007ee0 <_malloc_r+0x338> +80008284: 000b8413 mv s0,s7 +80008288: cf9ff06f j 80007f80 <_malloc_r+0x3d8> +8000828c: 00100793 li a5,1 +80008290: 00fba223 sw a5,4(s7) +80008294: ebdff06f j 80008150 <_malloc_r+0x5a8> +80008298: 15400713 li a4,340 +8000829c: 06f76263 bltu a4,a5,80008300 <_malloc_r+0x758> +800082a0: 00f55793 srli a5,a0,0xf +800082a4: 07878693 addi a3,a5,120 +800082a8: 07778593 addi a1,a5,119 +800082ac: 00369693 slli a3,a3,0x3 +800082b0: d41ff06f j 80007ff0 <_malloc_r+0x448> +800082b4: 55400713 li a4,1364 +800082b8: 06f76263 bltu a4,a5,8000831c <_malloc_r+0x774> +800082bc: 0124d793 srli a5,s1,0x12 +800082c0: 07d78613 addi a2,a5,125 +800082c4: 07c78513 addi a0,a5,124 +800082c8: 00361693 slli a3,a2,0x3 +800082cc: 9b9ff06f j 80007c84 <_malloc_r+0xdc> +800082d0: ff8c8c93 addi s9,s9,-8 +800082d4: 019a8ab3 add s5,s5,s9 +800082d8: 417a8ab3 sub s5,s5,s7 +800082dc: 00000a13 li s4,0 +800082e0: c49ff06f j 80007f28 <_malloc_r+0x380> +800082e4: 00840593 addi a1,s0,8 +800082e8: 00098513 mv a0,s3 +800082ec: ee8fc0ef jal ra,800049d4 <_free_r> +800082f0: 00892403 lw s0,8(s2) +800082f4: 000c2583 lw a1,0(s8) +800082f8: 00442a83 lw s5,4(s0) +800082fc: c85ff06f j 80007f80 <_malloc_r+0x3d8> +80008300: 55400713 li a4,1364 +80008304: 02f76463 bltu a4,a5,8000832c <_malloc_r+0x784> +80008308: 01255793 srli a5,a0,0x12 +8000830c: 07d78693 addi a3,a5,125 +80008310: 07c78593 addi a1,a5,124 +80008314: 00369693 slli a3,a3,0x3 +80008318: cd9ff06f j 80007ff0 <_malloc_r+0x448> +8000831c: 3f800693 li a3,1016 +80008320: 07f00613 li a2,127 +80008324: 07e00513 li a0,126 +80008328: 95dff06f j 80007c84 <_malloc_r+0xdc> +8000832c: 3f800693 li a3,1016 +80008330: 07e00593 li a1,126 +80008334: cbdff06f j 80007ff0 <_malloc_r+0x448> +80008338: 00492783 lw a5,4(s2) +8000833c: e5dff06f j 80008198 <_malloc_r+0x5f0> -80007b00 <__swhatbuf_r>: -80007b00: f9010113 addi sp,sp,-112 -80007b04: 06812423 sw s0,104(sp) -80007b08: 00058413 mv s0,a1 -80007b0c: 00e59583 lh a1,14(a1) -80007b10: 06912223 sw s1,100(sp) -80007b14: 07212023 sw s2,96(sp) -80007b18: 06112623 sw ra,108(sp) -80007b1c: 00060493 mv s1,a2 -80007b20: 00068913 mv s2,a3 -80007b24: 0405ca63 bltz a1,80007b78 <__swhatbuf_r+0x78> -80007b28: 00810613 addi a2,sp,8 -80007b2c: 494060ef jal ra,8000dfc0 <_fstat_r> -80007b30: 04054463 bltz a0,80007b78 <__swhatbuf_r+0x78> -80007b34: 00c12703 lw a4,12(sp) -80007b38: 0000f7b7 lui a5,0xf -80007b3c: 06c12083 lw ra,108(sp) -80007b40: 00e7f7b3 and a5,a5,a4 -80007b44: ffffe737 lui a4,0xffffe -80007b48: 00e787b3 add a5,a5,a4 -80007b4c: 06812403 lw s0,104(sp) -80007b50: 0017b793 seqz a5,a5 -80007b54: 00f92023 sw a5,0(s2) -80007b58: 40000793 li a5,1024 -80007b5c: 00f4a023 sw a5,0(s1) -80007b60: 00001537 lui a0,0x1 -80007b64: 06412483 lw s1,100(sp) -80007b68: 06012903 lw s2,96(sp) -80007b6c: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800> -80007b70: 07010113 addi sp,sp,112 -80007b74: 00008067 ret -80007b78: 00c45783 lhu a5,12(s0) -80007b7c: 00092023 sw zero,0(s2) -80007b80: 0807f793 andi a5,a5,128 -80007b84: 02078463 beqz a5,80007bac <__swhatbuf_r+0xac> -80007b88: 06c12083 lw ra,108(sp) -80007b8c: 06812403 lw s0,104(sp) -80007b90: 04000793 li a5,64 -80007b94: 00f4a023 sw a5,0(s1) -80007b98: 06012903 lw s2,96(sp) -80007b9c: 06412483 lw s1,100(sp) -80007ba0: 00000513 li a0,0 -80007ba4: 07010113 addi sp,sp,112 -80007ba8: 00008067 ret -80007bac: 06c12083 lw ra,108(sp) -80007bb0: 06812403 lw s0,104(sp) -80007bb4: 40000793 li a5,1024 -80007bb8: 00f4a023 sw a5,0(s1) -80007bbc: 06012903 lw s2,96(sp) -80007bc0: 06412483 lw s1,100(sp) -80007bc4: 00000513 li a0,0 -80007bc8: 07010113 addi sp,sp,112 -80007bcc: 00008067 ret +80008340 : +80008340: 00357793 andi a5,a0,3 +80008344: 0ff5f693 andi a3,a1,255 +80008348: 02078a63 beqz a5,8000837c +8000834c: fff60793 addi a5,a2,-1 +80008350: 02060e63 beqz a2,8000838c +80008354: fff00613 li a2,-1 +80008358: 0180006f j 80008370 +8000835c: 00150513 addi a0,a0,1 +80008360: 00357713 andi a4,a0,3 +80008364: 00070e63 beqz a4,80008380 +80008368: fff78793 addi a5,a5,-1 +8000836c: 02c78063 beq a5,a2,8000838c +80008370: 00054703 lbu a4,0(a0) +80008374: fed714e3 bne a4,a3,8000835c +80008378: 00008067 ret +8000837c: 00060793 mv a5,a2 +80008380: 00300713 li a4,3 +80008384: 02f76663 bltu a4,a5,800083b0 +80008388: 00079663 bnez a5,80008394 +8000838c: 00000513 li a0,0 +80008390: 00008067 ret +80008394: 00f507b3 add a5,a0,a5 +80008398: 00c0006f j 800083a4 +8000839c: 00150513 addi a0,a0,1 +800083a0: fea786e3 beq a5,a0,8000838c +800083a4: 00054703 lbu a4,0(a0) +800083a8: fed71ae3 bne a4,a3,8000839c +800083ac: 00008067 ret +800083b0: 00010737 lui a4,0x10 +800083b4: 00859893 slli a7,a1,0x8 +800083b8: fff70713 addi a4,a4,-1 # ffff <_start-0x7fff0001> +800083bc: 00e8f8b3 and a7,a7,a4 +800083c0: 0ff5f593 andi a1,a1,255 +800083c4: 00b8e5b3 or a1,a7,a1 +800083c8: 01059893 slli a7,a1,0x10 +800083cc: 00b8e8b3 or a7,a7,a1 +800083d0: feff0837 lui a6,0xfeff0 +800083d4: 808085b7 lui a1,0x80808 +800083d8: eff80813 addi a6,a6,-257 # fefefeff <__BSS_END__+0x7efd92c3> +800083dc: 08058593 addi a1,a1,128 # 80808080 <__BSS_END__+0x7f1444> +800083e0: 00300313 li t1,3 +800083e4: 00052703 lw a4,0(a0) +800083e8: 00e8c733 xor a4,a7,a4 +800083ec: 01070633 add a2,a4,a6 +800083f0: fff74713 not a4,a4 +800083f4: 00e67733 and a4,a2,a4 +800083f8: 00b77733 and a4,a4,a1 +800083fc: f8071ce3 bnez a4,80008394 +80008400: ffc78793 addi a5,a5,-4 +80008404: 00450513 addi a0,a0,4 +80008408: fcf36ee3 bltu t1,a5,800083e4 +8000840c: f80794e3 bnez a5,80008394 +80008410: f7dff06f j 8000838c -80007bd0 <__smakebuf_r>: -80007bd0: 00c5d783 lhu a5,12(a1) -80007bd4: fe010113 addi sp,sp,-32 -80007bd8: 00812c23 sw s0,24(sp) -80007bdc: 00112e23 sw ra,28(sp) -80007be0: 00912a23 sw s1,20(sp) -80007be4: 01212823 sw s2,16(sp) -80007be8: 0027f793 andi a5,a5,2 -80007bec: 00058413 mv s0,a1 -80007bf0: 02078863 beqz a5,80007c20 <__smakebuf_r+0x50> -80007bf4: 04358793 addi a5,a1,67 -80007bf8: 00f5a023 sw a5,0(a1) -80007bfc: 00f5a823 sw a5,16(a1) -80007c00: 00100793 li a5,1 -80007c04: 00f5aa23 sw a5,20(a1) -80007c08: 01c12083 lw ra,28(sp) -80007c0c: 01812403 lw s0,24(sp) -80007c10: 01412483 lw s1,20(sp) -80007c14: 01012903 lw s2,16(sp) -80007c18: 02010113 addi sp,sp,32 -80007c1c: 00008067 ret -80007c20: 00c10693 addi a3,sp,12 -80007c24: 00810613 addi a2,sp,8 -80007c28: 00050493 mv s1,a0 -80007c2c: ed5ff0ef jal ra,80007b00 <__swhatbuf_r> -80007c30: 00812583 lw a1,8(sp) -80007c34: 00050913 mv s2,a0 -80007c38: 00048513 mv a0,s1 -80007c3c: 0b4000ef jal ra,80007cf0 <_malloc_r> -80007c40: 00c41783 lh a5,12(s0) -80007c44: 04050863 beqz a0,80007c94 <__smakebuf_r+0xc4> -80007c48: 80004737 lui a4,0x80004 -80007c4c: 60070713 addi a4,a4,1536 # 80004600 <__BSS_END__+0xfffed9d0> -80007c50: 02e4ae23 sw a4,60(s1) -80007c54: 00812703 lw a4,8(sp) -80007c58: 00c12683 lw a3,12(sp) -80007c5c: 0807e793 ori a5,a5,128 -80007c60: 00f41623 sh a5,12(s0) -80007c64: 00a42023 sw a0,0(s0) -80007c68: 00a42823 sw a0,16(s0) -80007c6c: 00e42a23 sw a4,20(s0) -80007c70: 04069863 bnez a3,80007cc0 <__smakebuf_r+0xf0> -80007c74: 0127e7b3 or a5,a5,s2 -80007c78: 01c12083 lw ra,28(sp) -80007c7c: 00f41623 sh a5,12(s0) -80007c80: 01812403 lw s0,24(sp) -80007c84: 01412483 lw s1,20(sp) -80007c88: 01012903 lw s2,16(sp) -80007c8c: 02010113 addi sp,sp,32 -80007c90: 00008067 ret -80007c94: 2007f713 andi a4,a5,512 -80007c98: f60718e3 bnez a4,80007c08 <__smakebuf_r+0x38> -80007c9c: ffc7f793 andi a5,a5,-4 -80007ca0: 0027e793 ori a5,a5,2 -80007ca4: 04340713 addi a4,s0,67 -80007ca8: 00f41623 sh a5,12(s0) -80007cac: 00100793 li a5,1 -80007cb0: 00e42023 sw a4,0(s0) -80007cb4: 00e42823 sw a4,16(s0) -80007cb8: 00f42a23 sw a5,20(s0) -80007cbc: f4dff06f j 80007c08 <__smakebuf_r+0x38> -80007cc0: 00e41583 lh a1,14(s0) -80007cc4: 00048513 mv a0,s1 -80007cc8: 005060ef jal ra,8000e4cc <_isatty_r> -80007ccc: 00051663 bnez a0,80007cd8 <__smakebuf_r+0x108> -80007cd0: 00c41783 lh a5,12(s0) -80007cd4: fa1ff06f j 80007c74 <__smakebuf_r+0xa4> -80007cd8: 00c45703 lhu a4,12(s0) -80007cdc: ffc77713 andi a4,a4,-4 -80007ce0: 00176713 ori a4,a4,1 -80007ce4: 01071793 slli a5,a4,0x10 -80007ce8: 4107d793 srai a5,a5,0x10 -80007cec: f89ff06f j 80007c74 <__smakebuf_r+0xa4> +80008414 : +80008414: 00f00313 li t1,15 +80008418: 00050713 mv a4,a0 +8000841c: 02c37e63 bgeu t1,a2,80008458 +80008420: 00f77793 andi a5,a4,15 +80008424: 0a079063 bnez a5,800084c4 +80008428: 08059263 bnez a1,800084ac +8000842c: ff067693 andi a3,a2,-16 +80008430: 00f67613 andi a2,a2,15 +80008434: 00e686b3 add a3,a3,a4 +80008438: 00b72023 sw a1,0(a4) +8000843c: 00b72223 sw a1,4(a4) +80008440: 00b72423 sw a1,8(a4) +80008444: 00b72623 sw a1,12(a4) +80008448: 01070713 addi a4,a4,16 +8000844c: fed766e3 bltu a4,a3,80008438 +80008450: 00061463 bnez a2,80008458 +80008454: 00008067 ret +80008458: 40c306b3 sub a3,t1,a2 +8000845c: 00269693 slli a3,a3,0x2 +80008460: 00000297 auipc t0,0x0 +80008464: 005686b3 add a3,a3,t0 +80008468: 00c68067 jr 12(a3) +8000846c: 00b70723 sb a1,14(a4) +80008470: 00b706a3 sb a1,13(a4) +80008474: 00b70623 sb a1,12(a4) +80008478: 00b705a3 sb a1,11(a4) +8000847c: 00b70523 sb a1,10(a4) +80008480: 00b704a3 sb a1,9(a4) +80008484: 00b70423 sb a1,8(a4) +80008488: 00b703a3 sb a1,7(a4) +8000848c: 00b70323 sb a1,6(a4) +80008490: 00b702a3 sb a1,5(a4) +80008494: 00b70223 sb a1,4(a4) +80008498: 00b701a3 sb a1,3(a4) +8000849c: 00b70123 sb a1,2(a4) +800084a0: 00b700a3 sb a1,1(a4) +800084a4: 00b70023 sb a1,0(a4) +800084a8: 00008067 ret +800084ac: 0ff5f593 andi a1,a1,255 +800084b0: 00859693 slli a3,a1,0x8 +800084b4: 00d5e5b3 or a1,a1,a3 +800084b8: 01059693 slli a3,a1,0x10 +800084bc: 00d5e5b3 or a1,a1,a3 +800084c0: f6dff06f j 8000842c +800084c4: 00279693 slli a3,a5,0x2 +800084c8: 00000297 auipc t0,0x0 +800084cc: 005686b3 add a3,a3,t0 +800084d0: 00008293 mv t0,ra +800084d4: fa0680e7 jalr -96(a3) +800084d8: 00028093 mv ra,t0 +800084dc: ff078793 addi a5,a5,-16 +800084e0: 40f70733 sub a4,a4,a5 +800084e4: 00f60633 add a2,a2,a5 +800084e8: f6c378e3 bgeu t1,a2,80008458 +800084ec: f3dff06f j 80008428 -80007cf0 <_malloc_r>: -80007cf0: fd010113 addi sp,sp,-48 -80007cf4: 01312e23 sw s3,28(sp) -80007cf8: 02112623 sw ra,44(sp) -80007cfc: 02812423 sw s0,40(sp) -80007d00: 02912223 sw s1,36(sp) -80007d04: 03212023 sw s2,32(sp) -80007d08: 01412c23 sw s4,24(sp) -80007d0c: 01512a23 sw s5,20(sp) -80007d10: 01612823 sw s6,16(sp) -80007d14: 01712623 sw s7,12(sp) -80007d18: 01812423 sw s8,8(sp) -80007d1c: 01912223 sw s9,4(sp) -80007d20: 00b58793 addi a5,a1,11 -80007d24: 01600713 li a4,22 -80007d28: 00050993 mv s3,a0 -80007d2c: 06f76463 bltu a4,a5,80007d94 <_malloc_r+0xa4> -80007d30: 01000793 li a5,16 -80007d34: 1eb7e263 bltu a5,a1,80007f18 <_malloc_r+0x228> -80007d38: 095000ef jal ra,800085cc <__malloc_lock> -80007d3c: 01000493 li s1,16 -80007d40: 00200613 li a2,2 -80007d44: 01800793 li a5,24 -80007d48: f2c18913 addi s2,gp,-212 # 80016734 <__malloc_av_> -80007d4c: 00f907b3 add a5,s2,a5 -80007d50: 0047a403 lw s0,4(a5) # f004 <_start-0x7fff0ffc> -80007d54: ff878713 addi a4,a5,-8 -80007d58: 20e40863 beq s0,a4,80007f68 <_malloc_r+0x278> -80007d5c: 00442783 lw a5,4(s0) -80007d60: 00c42683 lw a3,12(s0) -80007d64: 00842603 lw a2,8(s0) -80007d68: ffc7f793 andi a5,a5,-4 -80007d6c: 00f407b3 add a5,s0,a5 -80007d70: 0047a703 lw a4,4(a5) -80007d74: 00d62623 sw a3,12(a2) -80007d78: 00c6a423 sw a2,8(a3) -80007d7c: 00176713 ori a4,a4,1 -80007d80: 00098513 mv a0,s3 -80007d84: 00e7a223 sw a4,4(a5) -80007d88: 049000ef jal ra,800085d0 <__malloc_unlock> -80007d8c: 00840513 addi a0,s0,8 -80007d90: 1940006f j 80007f24 <_malloc_r+0x234> -80007d94: ff87f493 andi s1,a5,-8 -80007d98: 1807c063 bltz a5,80007f18 <_malloc_r+0x228> -80007d9c: 16b4ee63 bltu s1,a1,80007f18 <_malloc_r+0x228> -80007da0: 02d000ef jal ra,800085cc <__malloc_lock> -80007da4: 1f700793 li a5,503 -80007da8: 4497fa63 bgeu a5,s1,800081fc <_malloc_r+0x50c> -80007dac: 0094d793 srli a5,s1,0x9 -80007db0: 1a078463 beqz a5,80007f58 <_malloc_r+0x268> -80007db4: 00400713 li a4,4 -80007db8: 3cf76063 bltu a4,a5,80008178 <_malloc_r+0x488> -80007dbc: 0064d793 srli a5,s1,0x6 -80007dc0: 03978613 addi a2,a5,57 -80007dc4: 03878513 addi a0,a5,56 -80007dc8: 00361693 slli a3,a2,0x3 -80007dcc: f2c18913 addi s2,gp,-212 # 80016734 <__malloc_av_> -80007dd0: 00d906b3 add a3,s2,a3 -80007dd4: 0046a403 lw s0,4(a3) -80007dd8: ff868693 addi a3,a3,-8 -80007ddc: 02868663 beq a3,s0,80007e08 <_malloc_r+0x118> -80007de0: 00f00593 li a1,15 -80007de4: 0100006f j 80007df4 <_malloc_r+0x104> -80007de8: 32075263 bgez a4,8000810c <_malloc_r+0x41c> -80007dec: 00c42403 lw s0,12(s0) -80007df0: 00868c63 beq a3,s0,80007e08 <_malloc_r+0x118> -80007df4: 00442783 lw a5,4(s0) -80007df8: ffc7f793 andi a5,a5,-4 -80007dfc: 40978733 sub a4,a5,s1 -80007e00: fee5d4e3 bge a1,a4,80007de8 <_malloc_r+0xf8> -80007e04: 00050613 mv a2,a0 -80007e08: 01092403 lw s0,16(s2) -80007e0c: 00890893 addi a7,s2,8 -80007e10: 17140863 beq s0,a7,80007f80 <_malloc_r+0x290> -80007e14: 00442503 lw a0,4(s0) -80007e18: 00f00693 li a3,15 -80007e1c: ffc57513 andi a0,a0,-4 -80007e20: 409507b3 sub a5,a0,s1 -80007e24: 40f6c263 blt a3,a5,80008228 <_malloc_r+0x538> -80007e28: 01192a23 sw a7,20(s2) -80007e2c: 01192823 sw a7,16(s2) -80007e30: 3c07dc63 bgez a5,80008208 <_malloc_r+0x518> -80007e34: 1ff00793 li a5,511 -80007e38: 2ea7e063 bltu a5,a0,80008118 <_malloc_r+0x428> -80007e3c: ff857793 andi a5,a0,-8 -80007e40: 00878793 addi a5,a5,8 -80007e44: 00492583 lw a1,4(s2) -80007e48: 00f907b3 add a5,s2,a5 -80007e4c: 0007a683 lw a3,0(a5) -80007e50: 00555513 srli a0,a0,0x5 -80007e54: 00100713 li a4,1 -80007e58: 00a71733 sll a4,a4,a0 -80007e5c: 00b76733 or a4,a4,a1 -80007e60: ff878593 addi a1,a5,-8 -80007e64: 00b42623 sw a1,12(s0) -80007e68: 00d42423 sw a3,8(s0) -80007e6c: 00e92223 sw a4,4(s2) -80007e70: 0087a023 sw s0,0(a5) -80007e74: 0086a623 sw s0,12(a3) -80007e78: 40265793 srai a5,a2,0x2 -80007e7c: 00100593 li a1,1 -80007e80: 00f595b3 sll a1,a1,a5 -80007e84: 10b76863 bltu a4,a1,80007f94 <_malloc_r+0x2a4> -80007e88: 00e5f7b3 and a5,a1,a4 -80007e8c: 02079463 bnez a5,80007eb4 <_malloc_r+0x1c4> -80007e90: 00159593 slli a1,a1,0x1 -80007e94: ffc67613 andi a2,a2,-4 -80007e98: 00e5f7b3 and a5,a1,a4 -80007e9c: 00460613 addi a2,a2,4 -80007ea0: 00079a63 bnez a5,80007eb4 <_malloc_r+0x1c4> -80007ea4: 00159593 slli a1,a1,0x1 -80007ea8: 00e5f7b3 and a5,a1,a4 -80007eac: 00460613 addi a2,a2,4 -80007eb0: fe078ae3 beqz a5,80007ea4 <_malloc_r+0x1b4> -80007eb4: 00f00813 li a6,15 -80007eb8: 00361313 slli t1,a2,0x3 -80007ebc: 00690333 add t1,s2,t1 -80007ec0: 00030513 mv a0,t1 -80007ec4: 00c52783 lw a5,12(a0) -80007ec8: 00060e13 mv t3,a2 -80007ecc: 2cf50863 beq a0,a5,8000819c <_malloc_r+0x4ac> -80007ed0: 0047a703 lw a4,4(a5) -80007ed4: 00078413 mv s0,a5 -80007ed8: 00c7a783 lw a5,12(a5) -80007edc: ffc77713 andi a4,a4,-4 -80007ee0: 409706b3 sub a3,a4,s1 -80007ee4: 2cd84863 blt a6,a3,800081b4 <_malloc_r+0x4c4> -80007ee8: fe06c2e3 bltz a3,80007ecc <_malloc_r+0x1dc> -80007eec: 00e40733 add a4,s0,a4 -80007ef0: 00472683 lw a3,4(a4) -80007ef4: 00842603 lw a2,8(s0) -80007ef8: 00098513 mv a0,s3 -80007efc: 0016e693 ori a3,a3,1 -80007f00: 00d72223 sw a3,4(a4) -80007f04: 00f62623 sw a5,12(a2) -80007f08: 00c7a423 sw a2,8(a5) -80007f0c: 6c4000ef jal ra,800085d0 <__malloc_unlock> -80007f10: 00840513 addi a0,s0,8 -80007f14: 0100006f j 80007f24 <_malloc_r+0x234> -80007f18: 00c00793 li a5,12 -80007f1c: 00f9a023 sw a5,0(s3) -80007f20: 00000513 li a0,0 -80007f24: 02c12083 lw ra,44(sp) -80007f28: 02812403 lw s0,40(sp) -80007f2c: 02412483 lw s1,36(sp) -80007f30: 02012903 lw s2,32(sp) -80007f34: 01c12983 lw s3,28(sp) -80007f38: 01812a03 lw s4,24(sp) -80007f3c: 01412a83 lw s5,20(sp) -80007f40: 01012b03 lw s6,16(sp) -80007f44: 00c12b83 lw s7,12(sp) -80007f48: 00812c03 lw s8,8(sp) -80007f4c: 00412c83 lw s9,4(sp) -80007f50: 03010113 addi sp,sp,48 -80007f54: 00008067 ret -80007f58: 20000693 li a3,512 -80007f5c: 04000613 li a2,64 -80007f60: 03f00513 li a0,63 -80007f64: e69ff06f j 80007dcc <_malloc_r+0xdc> -80007f68: 00c7a403 lw s0,12(a5) -80007f6c: 00260613 addi a2,a2,2 -80007f70: de8796e3 bne a5,s0,80007d5c <_malloc_r+0x6c> -80007f74: 01092403 lw s0,16(s2) -80007f78: 00890893 addi a7,s2,8 -80007f7c: e9141ce3 bne s0,a7,80007e14 <_malloc_r+0x124> -80007f80: 00492703 lw a4,4(s2) -80007f84: 40265793 srai a5,a2,0x2 -80007f88: 00100593 li a1,1 -80007f8c: 00f595b3 sll a1,a1,a5 -80007f90: eeb77ce3 bgeu a4,a1,80007e88 <_malloc_r+0x198> -80007f94: 00892403 lw s0,8(s2) -80007f98: 00442a83 lw s5,4(s0) -80007f9c: ffcafb13 andi s6,s5,-4 -80007fa0: 009b6863 bltu s6,s1,80007fb0 <_malloc_r+0x2c0> -80007fa4: 409b07b3 sub a5,s6,s1 -80007fa8: 00f00713 li a4,15 -80007fac: 12f74c63 blt a4,a5,800080e4 <_malloc_r+0x3f4> -80007fb0: 3781aa83 lw s5,888(gp) # 80016b80 <__malloc_top_pad> -80007fb4: 3641a703 lw a4,868(gp) # 80016b6c <__malloc_sbrk_base> -80007fb8: fff00793 li a5,-1 -80007fbc: 01640a33 add s4,s0,s6 -80007fc0: 01548ab3 add s5,s1,s5 -80007fc4: 34f70463 beq a4,a5,8000830c <_malloc_r+0x61c> -80007fc8: 000017b7 lui a5,0x1 -80007fcc: 00f78793 addi a5,a5,15 # 100f <_start-0x7fffeff1> -80007fd0: 00fa8ab3 add s5,s5,a5 -80007fd4: fffff7b7 lui a5,0xfffff -80007fd8: 00fafab3 and s5,s5,a5 -80007fdc: 000a8593 mv a1,s5 -80007fe0: 00098513 mv a0,s3 -80007fe4: 664010ef jal ra,80009648 <_sbrk_r> -80007fe8: fff00793 li a5,-1 -80007fec: 00050b93 mv s7,a0 -80007ff0: 28f50663 beq a0,a5,8000827c <_malloc_r+0x58c> -80007ff4: 29456263 bltu a0,s4,80008278 <_malloc_r+0x588> -80007ff8: 3c018c13 addi s8,gp,960 # 80016bc8 <__malloc_current_mallinfo> -80007ffc: 000c2583 lw a1,0(s8) # 1000 <_start-0x7ffff000> -80008000: 00ba85b3 add a1,s5,a1 -80008004: 00bc2023 sw a1,0(s8) -80008008: 00058793 mv a5,a1 -8000800c: 38aa0e63 beq s4,a0,800083a8 <_malloc_r+0x6b8> -80008010: 3641a683 lw a3,868(gp) # 80016b6c <__malloc_sbrk_base> -80008014: fff00713 li a4,-1 -80008018: 3ae68663 beq a3,a4,800083c4 <_malloc_r+0x6d4> -8000801c: 414b8a33 sub s4,s7,s4 -80008020: 00fa07b3 add a5,s4,a5 -80008024: 00fc2023 sw a5,0(s8) -80008028: 007bfc93 andi s9,s7,7 -8000802c: 300c8263 beqz s9,80008330 <_malloc_r+0x640> -80008030: 000017b7 lui a5,0x1 -80008034: 419b8bb3 sub s7,s7,s9 -80008038: 00878593 addi a1,a5,8 # 1008 <_start-0x7fffeff8> -8000803c: 008b8b93 addi s7,s7,8 -80008040: 419585b3 sub a1,a1,s9 -80008044: 015b8ab3 add s5,s7,s5 -80008048: fff78793 addi a5,a5,-1 -8000804c: 415585b3 sub a1,a1,s5 -80008050: 00f5fa33 and s4,a1,a5 -80008054: 000a0593 mv a1,s4 -80008058: 00098513 mv a0,s3 -8000805c: 5ec010ef jal ra,80009648 <_sbrk_r> -80008060: fff00793 li a5,-1 -80008064: 3af50a63 beq a0,a5,80008418 <_malloc_r+0x728> -80008068: 41750533 sub a0,a0,s7 -8000806c: 01450ab3 add s5,a0,s4 -80008070: 000c2583 lw a1,0(s8) -80008074: 01792423 sw s7,8(s2) -80008078: 001aea93 ori s5,s5,1 -8000807c: 00ba05b3 add a1,s4,a1 -80008080: 00bc2023 sw a1,0(s8) -80008084: 015ba223 sw s5,4(s7) -80008088: 35240263 beq s0,s2,800083cc <_malloc_r+0x6dc> -8000808c: 00f00693 li a3,15 -80008090: 3566f263 bgeu a3,s6,800083d4 <_malloc_r+0x6e4> -80008094: 00442703 lw a4,4(s0) -80008098: ff4b0793 addi a5,s6,-12 -8000809c: ff87f793 andi a5,a5,-8 -800080a0: 00177713 andi a4,a4,1 -800080a4: 00f76733 or a4,a4,a5 -800080a8: 00e42223 sw a4,4(s0) -800080ac: 00500613 li a2,5 -800080b0: 00f40733 add a4,s0,a5 -800080b4: 00c72223 sw a2,4(a4) -800080b8: 00c72423 sw a2,8(a4) -800080bc: 36f6e863 bltu a3,a5,8000842c <_malloc_r+0x73c> -800080c0: 004baa83 lw s5,4(s7) -800080c4: 000b8413 mv s0,s7 -800080c8: 3741a703 lw a4,884(gp) # 80016b7c <__malloc_max_sbrked_mem> -800080cc: 00b77463 bgeu a4,a1,800080d4 <_malloc_r+0x3e4> -800080d0: 36b1aa23 sw a1,884(gp) # 80016b7c <__malloc_max_sbrked_mem> -800080d4: 3701a703 lw a4,880(gp) # 80016b78 <__malloc_max_total_mem> -800080d8: 1ab77663 bgeu a4,a1,80008284 <_malloc_r+0x594> -800080dc: 36b1a823 sw a1,880(gp) # 80016b78 <__malloc_max_total_mem> -800080e0: 1a40006f j 80008284 <_malloc_r+0x594> -800080e4: 0014e713 ori a4,s1,1 -800080e8: 00e42223 sw a4,4(s0) -800080ec: 009404b3 add s1,s0,s1 -800080f0: 00992423 sw s1,8(s2) -800080f4: 0017e793 ori a5,a5,1 -800080f8: 00098513 mv a0,s3 -800080fc: 00f4a223 sw a5,4(s1) -80008100: 4d0000ef jal ra,800085d0 <__malloc_unlock> -80008104: 00840513 addi a0,s0,8 -80008108: e1dff06f j 80007f24 <_malloc_r+0x234> -8000810c: 00c42683 lw a3,12(s0) -80008110: 00842603 lw a2,8(s0) -80008114: c59ff06f j 80007d6c <_malloc_r+0x7c> -80008118: 00955793 srli a5,a0,0x9 -8000811c: 00400713 li a4,4 -80008120: 14f77263 bgeu a4,a5,80008264 <_malloc_r+0x574> -80008124: 01400713 li a4,20 -80008128: 22f76a63 bltu a4,a5,8000835c <_malloc_r+0x66c> -8000812c: 05c78693 addi a3,a5,92 -80008130: 05b78593 addi a1,a5,91 -80008134: 00369693 slli a3,a3,0x3 -80008138: 00d906b3 add a3,s2,a3 -8000813c: 0006a783 lw a5,0(a3) -80008140: ff868693 addi a3,a3,-8 -80008144: 1cf68863 beq a3,a5,80008314 <_malloc_r+0x624> -80008148: 0047a703 lw a4,4(a5) -8000814c: ffc77713 andi a4,a4,-4 -80008150: 00e57663 bgeu a0,a4,8000815c <_malloc_r+0x46c> -80008154: 0087a783 lw a5,8(a5) -80008158: fef698e3 bne a3,a5,80008148 <_malloc_r+0x458> -8000815c: 00c7a683 lw a3,12(a5) -80008160: 00492703 lw a4,4(s2) -80008164: 00d42623 sw a3,12(s0) -80008168: 00f42423 sw a5,8(s0) -8000816c: 0086a423 sw s0,8(a3) -80008170: 0087a623 sw s0,12(a5) -80008174: d05ff06f j 80007e78 <_malloc_r+0x188> -80008178: 01400713 li a4,20 -8000817c: 12f77663 bgeu a4,a5,800082a8 <_malloc_r+0x5b8> -80008180: 05400713 li a4,84 -80008184: 1ef76a63 bltu a4,a5,80008378 <_malloc_r+0x688> -80008188: 00c4d793 srli a5,s1,0xc -8000818c: 06f78613 addi a2,a5,111 -80008190: 06e78513 addi a0,a5,110 -80008194: 00361693 slli a3,a2,0x3 -80008198: c35ff06f j 80007dcc <_malloc_r+0xdc> -8000819c: 001e0e13 addi t3,t3,1 -800081a0: 003e7793 andi a5,t3,3 -800081a4: 00850513 addi a0,a0,8 -800081a8: 10078e63 beqz a5,800082c4 <_malloc_r+0x5d4> -800081ac: 00c52783 lw a5,12(a0) -800081b0: d1dff06f j 80007ecc <_malloc_r+0x1dc> -800081b4: 00842603 lw a2,8(s0) -800081b8: 0014e593 ori a1,s1,1 -800081bc: 00b42223 sw a1,4(s0) -800081c0: 00f62623 sw a5,12(a2) -800081c4: 00c7a423 sw a2,8(a5) -800081c8: 009404b3 add s1,s0,s1 -800081cc: 00992a23 sw s1,20(s2) -800081d0: 00992823 sw s1,16(s2) -800081d4: 0016e793 ori a5,a3,1 -800081d8: 0114a623 sw a7,12(s1) -800081dc: 0114a423 sw a7,8(s1) -800081e0: 00f4a223 sw a5,4(s1) -800081e4: 00e40733 add a4,s0,a4 -800081e8: 00098513 mv a0,s3 -800081ec: 00d72023 sw a3,0(a4) -800081f0: 3e0000ef jal ra,800085d0 <__malloc_unlock> -800081f4: 00840513 addi a0,s0,8 -800081f8: d2dff06f j 80007f24 <_malloc_r+0x234> -800081fc: 0034d613 srli a2,s1,0x3 -80008200: 00848793 addi a5,s1,8 -80008204: b45ff06f j 80007d48 <_malloc_r+0x58> -80008208: 00a40733 add a4,s0,a0 -8000820c: 00472783 lw a5,4(a4) -80008210: 00098513 mv a0,s3 -80008214: 0017e793 ori a5,a5,1 -80008218: 00f72223 sw a5,4(a4) -8000821c: 3b4000ef jal ra,800085d0 <__malloc_unlock> -80008220: 00840513 addi a0,s0,8 -80008224: d01ff06f j 80007f24 <_malloc_r+0x234> -80008228: 0014e713 ori a4,s1,1 -8000822c: 00e42223 sw a4,4(s0) -80008230: 009404b3 add s1,s0,s1 -80008234: 00992a23 sw s1,20(s2) -80008238: 00992823 sw s1,16(s2) -8000823c: 0017e713 ori a4,a5,1 -80008240: 0114a623 sw a7,12(s1) -80008244: 0114a423 sw a7,8(s1) -80008248: 00e4a223 sw a4,4(s1) -8000824c: 00a40533 add a0,s0,a0 -80008250: 00f52023 sw a5,0(a0) -80008254: 00098513 mv a0,s3 -80008258: 378000ef jal ra,800085d0 <__malloc_unlock> -8000825c: 00840513 addi a0,s0,8 -80008260: cc5ff06f j 80007f24 <_malloc_r+0x234> -80008264: 00655793 srli a5,a0,0x6 -80008268: 03978693 addi a3,a5,57 -8000826c: 03878593 addi a1,a5,56 -80008270: 00369693 slli a3,a3,0x3 -80008274: ec5ff06f j 80008138 <_malloc_r+0x448> -80008278: 11240e63 beq s0,s2,80008394 <_malloc_r+0x6a4> -8000827c: 00892403 lw s0,8(s2) -80008280: 00442a83 lw s5,4(s0) -80008284: ffcafa93 andi s5,s5,-4 -80008288: 409a87b3 sub a5,s5,s1 -8000828c: 009ae663 bltu s5,s1,80008298 <_malloc_r+0x5a8> -80008290: 00f00713 li a4,15 -80008294: e4f748e3 blt a4,a5,800080e4 <_malloc_r+0x3f4> -80008298: 00098513 mv a0,s3 -8000829c: 334000ef jal ra,800085d0 <__malloc_unlock> -800082a0: 00000513 li a0,0 -800082a4: c81ff06f j 80007f24 <_malloc_r+0x234> -800082a8: 05c78613 addi a2,a5,92 -800082ac: 05b78513 addi a0,a5,91 -800082b0: 00361693 slli a3,a2,0x3 -800082b4: b19ff06f j 80007dcc <_malloc_r+0xdc> -800082b8: 00832783 lw a5,8(t1) -800082bc: fff60613 addi a2,a2,-1 -800082c0: 1c679063 bne a5,t1,80008480 <_malloc_r+0x790> -800082c4: 00367793 andi a5,a2,3 -800082c8: ff830313 addi t1,t1,-8 -800082cc: fe0796e3 bnez a5,800082b8 <_malloc_r+0x5c8> -800082d0: 00492703 lw a4,4(s2) -800082d4: fff5c793 not a5,a1 -800082d8: 00e7f7b3 and a5,a5,a4 -800082dc: 00f92223 sw a5,4(s2) -800082e0: 00159593 slli a1,a1,0x1 -800082e4: cab7e8e3 bltu a5,a1,80007f94 <_malloc_r+0x2a4> -800082e8: ca0586e3 beqz a1,80007f94 <_malloc_r+0x2a4> -800082ec: 00f5f733 and a4,a1,a5 -800082f0: 00071a63 bnez a4,80008304 <_malloc_r+0x614> -800082f4: 00159593 slli a1,a1,0x1 -800082f8: 00f5f733 and a4,a1,a5 -800082fc: 004e0e13 addi t3,t3,4 -80008300: fe070ae3 beqz a4,800082f4 <_malloc_r+0x604> -80008304: 000e0613 mv a2,t3 -80008308: bb1ff06f j 80007eb8 <_malloc_r+0x1c8> -8000830c: 010a8a93 addi s5,s5,16 # fffff010 <__BSS_END__+0x7ffe83e0> -80008310: ccdff06f j 80007fdc <_malloc_r+0x2ec> -80008314: 00492503 lw a0,4(s2) -80008318: 4025d593 srai a1,a1,0x2 -8000831c: 00100713 li a4,1 -80008320: 00b71733 sll a4,a4,a1 -80008324: 00a76733 or a4,a4,a0 -80008328: 00e92223 sw a4,4(s2) -8000832c: e39ff06f j 80008164 <_malloc_r+0x474> -80008330: 015b85b3 add a1,s7,s5 -80008334: 40b005b3 neg a1,a1 -80008338: 01459593 slli a1,a1,0x14 -8000833c: 0145da13 srli s4,a1,0x14 -80008340: 000a0593 mv a1,s4 -80008344: 00098513 mv a0,s3 -80008348: 300010ef jal ra,80009648 <_sbrk_r> -8000834c: fff00793 li a5,-1 -80008350: d0f51ce3 bne a0,a5,80008068 <_malloc_r+0x378> -80008354: 00000a13 li s4,0 -80008358: d19ff06f j 80008070 <_malloc_r+0x380> -8000835c: 05400713 li a4,84 -80008360: 08f76063 bltu a4,a5,800083e0 <_malloc_r+0x6f0> -80008364: 00c55793 srli a5,a0,0xc -80008368: 06f78693 addi a3,a5,111 -8000836c: 06e78593 addi a1,a5,110 -80008370: 00369693 slli a3,a3,0x3 -80008374: dc5ff06f j 80008138 <_malloc_r+0x448> -80008378: 15400713 li a4,340 -8000837c: 08f76063 bltu a4,a5,800083fc <_malloc_r+0x70c> -80008380: 00f4d793 srli a5,s1,0xf -80008384: 07878613 addi a2,a5,120 -80008388: 07778513 addi a0,a5,119 -8000838c: 00361693 slli a3,a2,0x3 -80008390: a3dff06f j 80007dcc <_malloc_r+0xdc> -80008394: 3c018c13 addi s8,gp,960 # 80016bc8 <__malloc_current_mallinfo> -80008398: 000c2783 lw a5,0(s8) -8000839c: 00fa87b3 add a5,s5,a5 -800083a0: 00fc2023 sw a5,0(s8) -800083a4: c6dff06f j 80008010 <_malloc_r+0x320> -800083a8: 014a1713 slli a4,s4,0x14 -800083ac: c60712e3 bnez a4,80008010 <_malloc_r+0x320> -800083b0: 00892403 lw s0,8(s2) -800083b4: 015b0ab3 add s5,s6,s5 -800083b8: 001aea93 ori s5,s5,1 -800083bc: 01542223 sw s5,4(s0) -800083c0: d09ff06f j 800080c8 <_malloc_r+0x3d8> -800083c4: 3771a223 sw s7,868(gp) # 80016b6c <__malloc_sbrk_base> -800083c8: c61ff06f j 80008028 <_malloc_r+0x338> -800083cc: 000b8413 mv s0,s7 -800083d0: cf9ff06f j 800080c8 <_malloc_r+0x3d8> -800083d4: 00100793 li a5,1 -800083d8: 00fba223 sw a5,4(s7) -800083dc: ebdff06f j 80008298 <_malloc_r+0x5a8> -800083e0: 15400713 li a4,340 -800083e4: 06f76263 bltu a4,a5,80008448 <_malloc_r+0x758> -800083e8: 00f55793 srli a5,a0,0xf -800083ec: 07878693 addi a3,a5,120 -800083f0: 07778593 addi a1,a5,119 -800083f4: 00369693 slli a3,a3,0x3 -800083f8: d41ff06f j 80008138 <_malloc_r+0x448> -800083fc: 55400713 li a4,1364 -80008400: 06f76263 bltu a4,a5,80008464 <_malloc_r+0x774> -80008404: 0124d793 srli a5,s1,0x12 -80008408: 07d78613 addi a2,a5,125 -8000840c: 07c78513 addi a0,a5,124 -80008410: 00361693 slli a3,a2,0x3 -80008414: 9b9ff06f j 80007dcc <_malloc_r+0xdc> -80008418: ff8c8c93 addi s9,s9,-8 -8000841c: 019a8ab3 add s5,s5,s9 -80008420: 417a8ab3 sub s5,s5,s7 -80008424: 00000a13 li s4,0 -80008428: c49ff06f j 80008070 <_malloc_r+0x380> -8000842c: 00840593 addi a1,s0,8 -80008430: 00098513 mv a0,s3 -80008434: e50fc0ef jal ra,80004a84 <_free_r> -80008438: 00892403 lw s0,8(s2) -8000843c: 000c2583 lw a1,0(s8) -80008440: 00442a83 lw s5,4(s0) -80008444: c85ff06f j 800080c8 <_malloc_r+0x3d8> -80008448: 55400713 li a4,1364 -8000844c: 02f76463 bltu a4,a5,80008474 <_malloc_r+0x784> -80008450: 01255793 srli a5,a0,0x12 -80008454: 07d78693 addi a3,a5,125 -80008458: 07c78593 addi a1,a5,124 -8000845c: 00369693 slli a3,a3,0x3 -80008460: cd9ff06f j 80008138 <_malloc_r+0x448> -80008464: 3f800693 li a3,1016 -80008468: 07f00613 li a2,127 -8000846c: 07e00513 li a0,126 -80008470: 95dff06f j 80007dcc <_malloc_r+0xdc> -80008474: 3f800693 li a3,1016 -80008478: 07e00593 li a1,126 -8000847c: cbdff06f j 80008138 <_malloc_r+0x448> -80008480: 00492783 lw a5,4(s2) -80008484: e5dff06f j 800082e0 <_malloc_r+0x5f0> +800084f0 <__malloc_lock>: +800084f0: 00008067 ret -80008488 <_mbtowc_r>: -80008488: ea41a303 lw t1,-348(gp) # 800166ac <__global_locale+0xe4> -8000848c: 00030067 jr t1 +800084f4 <__malloc_unlock>: +800084f4: 00008067 ret -80008490 <__ascii_mbtowc>: -80008490: 02058063 beqz a1,800084b0 <__ascii_mbtowc+0x20> -80008494: 04060263 beqz a2,800084d8 <__ascii_mbtowc+0x48> -80008498: 04068863 beqz a3,800084e8 <__ascii_mbtowc+0x58> -8000849c: 00064783 lbu a5,0(a2) -800084a0: 00f5a023 sw a5,0(a1) -800084a4: 00064503 lbu a0,0(a2) -800084a8: 00a03533 snez a0,a0 -800084ac: 00008067 ret -800084b0: ff010113 addi sp,sp,-16 -800084b4: 00c10593 addi a1,sp,12 -800084b8: 02060463 beqz a2,800084e0 <__ascii_mbtowc+0x50> -800084bc: 02068a63 beqz a3,800084f0 <__ascii_mbtowc+0x60> -800084c0: 00064783 lbu a5,0(a2) -800084c4: 00f5a023 sw a5,0(a1) -800084c8: 00064503 lbu a0,0(a2) -800084cc: 00a03533 snez a0,a0 -800084d0: 01010113 addi sp,sp,16 -800084d4: 00008067 ret -800084d8: 00000513 li a0,0 -800084dc: 00008067 ret -800084e0: 00000513 li a0,0 -800084e4: fedff06f j 800084d0 <__ascii_mbtowc+0x40> -800084e8: ffe00513 li a0,-2 -800084ec: 00008067 ret -800084f0: ffe00513 li a0,-2 -800084f4: fddff06f j 800084d0 <__ascii_mbtowc+0x40> +800084f8 <_Balloc>: +800084f8: 04c52783 lw a5,76(a0) +800084fc: ff010113 addi sp,sp,-16 +80008500: 00812423 sw s0,8(sp) +80008504: 00912223 sw s1,4(sp) +80008508: 00112623 sw ra,12(sp) +8000850c: 01212023 sw s2,0(sp) +80008510: 00050413 mv s0,a0 +80008514: 00058493 mv s1,a1 +80008518: 02078e63 beqz a5,80008554 <_Balloc+0x5c> +8000851c: 00249513 slli a0,s1,0x2 +80008520: 00a787b3 add a5,a5,a0 +80008524: 0007a503 lw a0,0(a5) +80008528: 04050663 beqz a0,80008574 <_Balloc+0x7c> +8000852c: 00052703 lw a4,0(a0) +80008530: 00e7a023 sw a4,0(a5) +80008534: 00052823 sw zero,16(a0) +80008538: 00052623 sw zero,12(a0) +8000853c: 00c12083 lw ra,12(sp) +80008540: 00812403 lw s0,8(sp) +80008544: 00412483 lw s1,4(sp) +80008548: 00012903 lw s2,0(sp) +8000854c: 01010113 addi sp,sp,16 +80008550: 00008067 ret +80008554: 02100613 li a2,33 +80008558: 00400593 li a1,4 +8000855c: 470050ef jal ra,8000d9cc <_calloc_r> +80008560: 04a42623 sw a0,76(s0) +80008564: 00050793 mv a5,a0 +80008568: fa051ae3 bnez a0,8000851c <_Balloc+0x24> +8000856c: 00000513 li a0,0 +80008570: fcdff06f j 8000853c <_Balloc+0x44> +80008574: 00100913 li s2,1 +80008578: 00991933 sll s2,s2,s1 +8000857c: 00590613 addi a2,s2,5 +80008580: 00261613 slli a2,a2,0x2 +80008584: 00100593 li a1,1 +80008588: 00040513 mv a0,s0 +8000858c: 440050ef jal ra,8000d9cc <_calloc_r> +80008590: fc050ee3 beqz a0,8000856c <_Balloc+0x74> +80008594: 00952223 sw s1,4(a0) +80008598: 01252423 sw s2,8(a0) +8000859c: f99ff06f j 80008534 <_Balloc+0x3c> -800084f8 : -800084f8: 00357793 andi a5,a0,3 -800084fc: 0ff5f693 andi a3,a1,255 -80008500: 02078a63 beqz a5,80008534 -80008504: fff60793 addi a5,a2,-1 -80008508: 02060e63 beqz a2,80008544 -8000850c: fff00613 li a2,-1 -80008510: 0180006f j 80008528 -80008514: 00150513 addi a0,a0,1 -80008518: 00357713 andi a4,a0,3 -8000851c: 00070e63 beqz a4,80008538 -80008520: fff78793 addi a5,a5,-1 -80008524: 02c78063 beq a5,a2,80008544 -80008528: 00054703 lbu a4,0(a0) -8000852c: fed714e3 bne a4,a3,80008514 -80008530: 00008067 ret -80008534: 00060793 mv a5,a2 -80008538: 00300713 li a4,3 -8000853c: 02f76663 bltu a4,a5,80008568 -80008540: 00079663 bnez a5,8000854c -80008544: 00000513 li a0,0 -80008548: 00008067 ret -8000854c: 00f507b3 add a5,a0,a5 -80008550: 00c0006f j 8000855c -80008554: 00150513 addi a0,a0,1 -80008558: fea786e3 beq a5,a0,80008544 -8000855c: 00054703 lbu a4,0(a0) -80008560: fed71ae3 bne a4,a3,80008554 -80008564: 00008067 ret -80008568: 00010737 lui a4,0x10 -8000856c: 00859893 slli a7,a1,0x8 -80008570: fff70713 addi a4,a4,-1 # ffff <_start-0x7fff0001> -80008574: 00e8f8b3 and a7,a7,a4 -80008578: 0ff5f593 andi a1,a1,255 -8000857c: 00b8e5b3 or a1,a7,a1 -80008580: 01059893 slli a7,a1,0x10 -80008584: 00b8e8b3 or a7,a7,a1 -80008588: feff0837 lui a6,0xfeff0 -8000858c: 808085b7 lui a1,0x80808 -80008590: eff80813 addi a6,a6,-257 # fefefeff <__BSS_END__+0x7efd92cf> -80008594: 08058593 addi a1,a1,128 # 80808080 <__BSS_END__+0x7f1450> -80008598: 00300313 li t1,3 -8000859c: 00052703 lw a4,0(a0) -800085a0: 00e8c733 xor a4,a7,a4 -800085a4: 01070633 add a2,a4,a6 -800085a8: fff74713 not a4,a4 -800085ac: 00e67733 and a4,a2,a4 -800085b0: 00b77733 and a4,a4,a1 -800085b4: f8071ce3 bnez a4,8000854c -800085b8: ffc78793 addi a5,a5,-4 -800085bc: 00450513 addi a0,a0,4 -800085c0: fcf36ee3 bltu t1,a5,8000859c -800085c4: f80794e3 bnez a5,8000854c -800085c8: f7dff06f j 80008544 +800085a0 <_Bfree>: +800085a0: 02058063 beqz a1,800085c0 <_Bfree+0x20> +800085a4: 0045a703 lw a4,4(a1) +800085a8: 04c52783 lw a5,76(a0) +800085ac: 00271713 slli a4,a4,0x2 +800085b0: 00e787b3 add a5,a5,a4 +800085b4: 0007a703 lw a4,0(a5) +800085b8: 00e5a023 sw a4,0(a1) +800085bc: 00b7a023 sw a1,0(a5) +800085c0: 00008067 ret -800085cc <__malloc_lock>: -800085cc: 00008067 ret +800085c4 <__multadd>: +800085c4: fe010113 addi sp,sp,-32 +800085c8: 00912a23 sw s1,20(sp) +800085cc: 0105a483 lw s1,16(a1) +800085d0: 00010337 lui t1,0x10 +800085d4: 00812c23 sw s0,24(sp) +800085d8: 01212823 sw s2,16(sp) +800085dc: 01312623 sw s3,12(sp) +800085e0: 00112e23 sw ra,28(sp) +800085e4: 01412423 sw s4,8(sp) +800085e8: 00058913 mv s2,a1 +800085ec: 00050993 mv s3,a0 +800085f0: 00068413 mv s0,a3 +800085f4: 01458813 addi a6,a1,20 +800085f8: 00000893 li a7,0 +800085fc: fff30313 addi t1,t1,-1 # ffff <_start-0x7fff0001> +80008600: 00082783 lw a5,0(a6) +80008604: 00480813 addi a6,a6,4 +80008608: 00188893 addi a7,a7,1 +8000860c: 0067f6b3 and a3,a5,t1 +80008610: 02c686b3 mul a3,a3,a2 +80008614: 0107d793 srli a5,a5,0x10 +80008618: 02c787b3 mul a5,a5,a2 +8000861c: 008686b3 add a3,a3,s0 +80008620: 0106de13 srli t3,a3,0x10 +80008624: 0066f733 and a4,a3,t1 +80008628: 01c786b3 add a3,a5,t3 +8000862c: 01069793 slli a5,a3,0x10 +80008630: 00e78733 add a4,a5,a4 +80008634: fee82e23 sw a4,-4(a6) +80008638: 0106d413 srli s0,a3,0x10 +8000863c: fc98c2e3 blt a7,s1,80008600 <__multadd+0x3c> +80008640: 02040263 beqz s0,80008664 <__multadd+0xa0> +80008644: 00892783 lw a5,8(s2) +80008648: 04f4d063 bge s1,a5,80008688 <__multadd+0xc4> +8000864c: 00448793 addi a5,s1,4 +80008650: 00279793 slli a5,a5,0x2 +80008654: 00f907b3 add a5,s2,a5 +80008658: 0087a223 sw s0,4(a5) +8000865c: 00148493 addi s1,s1,1 +80008660: 00992823 sw s1,16(s2) +80008664: 01c12083 lw ra,28(sp) +80008668: 01812403 lw s0,24(sp) +8000866c: 01412483 lw s1,20(sp) +80008670: 00c12983 lw s3,12(sp) +80008674: 00812a03 lw s4,8(sp) +80008678: 00090513 mv a0,s2 +8000867c: 01012903 lw s2,16(sp) +80008680: 02010113 addi sp,sp,32 +80008684: 00008067 ret +80008688: 00492583 lw a1,4(s2) +8000868c: 00098513 mv a0,s3 +80008690: 00158593 addi a1,a1,1 +80008694: e65ff0ef jal ra,800084f8 <_Balloc> +80008698: 01092603 lw a2,16(s2) +8000869c: 00050a13 mv s4,a0 +800086a0: 00c90593 addi a1,s2,12 +800086a4: 00260613 addi a2,a2,2 +800086a8: 00261613 slli a2,a2,0x2 +800086ac: 00c50513 addi a0,a0,12 +800086b0: 5f1050ef jal ra,8000e4a0 +800086b4: 00492703 lw a4,4(s2) +800086b8: 04c9a783 lw a5,76(s3) +800086bc: 00271713 slli a4,a4,0x2 +800086c0: 00e787b3 add a5,a5,a4 +800086c4: 0007a703 lw a4,0(a5) +800086c8: 00e92023 sw a4,0(s2) +800086cc: 0127a023 sw s2,0(a5) +800086d0: 000a0913 mv s2,s4 +800086d4: f79ff06f j 8000864c <__multadd+0x88> -800085d0 <__malloc_unlock>: -800085d0: 00008067 ret +800086d8 <__s2b>: +800086d8: fe010113 addi sp,sp,-32 +800086dc: 00812c23 sw s0,24(sp) +800086e0: 00912a23 sw s1,20(sp) +800086e4: 01212823 sw s2,16(sp) +800086e8: 01312623 sw s3,12(sp) +800086ec: 01412423 sw s4,8(sp) +800086f0: 00868813 addi a6,a3,8 +800086f4: 00900793 li a5,9 +800086f8: 00112e23 sw ra,28(sp) +800086fc: 01512223 sw s5,4(sp) +80008700: 02f84833 div a6,a6,a5 +80008704: 00068993 mv s3,a3 +80008708: 00050913 mv s2,a0 +8000870c: 00058413 mv s0,a1 +80008710: 00060a13 mv s4,a2 +80008714: 00070493 mv s1,a4 +80008718: 0cd7d663 bge a5,a3,800087e4 <__s2b+0x10c> +8000871c: 00100793 li a5,1 +80008720: 00000593 li a1,0 +80008724: 00179793 slli a5,a5,0x1 +80008728: 00158593 addi a1,a1,1 +8000872c: ff07cce3 blt a5,a6,80008724 <__s2b+0x4c> +80008730: 00090513 mv a0,s2 +80008734: dc5ff0ef jal ra,800084f8 <_Balloc> +80008738: 00100793 li a5,1 +8000873c: 00f52823 sw a5,16(a0) +80008740: 00952a23 sw s1,20(a0) +80008744: 00900793 li a5,9 +80008748: 00050593 mv a1,a0 +8000874c: 0947d663 bge a5,s4,800087d8 <__s2b+0x100> +80008750: 00940a93 addi s5,s0,9 +80008754: 000a8493 mv s1,s5 +80008758: 01440433 add s0,s0,s4 +8000875c: 0004c683 lbu a3,0(s1) +80008760: 00a00613 li a2,10 +80008764: 00090513 mv a0,s2 +80008768: fd068693 addi a3,a3,-48 +8000876c: e59ff0ef jal ra,800085c4 <__multadd> +80008770: 00148493 addi s1,s1,1 +80008774: 00050593 mv a1,a0 +80008778: fe8492e3 bne s1,s0,8000875c <__s2b+0x84> +8000877c: ff8a0413 addi s0,s4,-8 +80008780: 008a8433 add s0,s5,s0 +80008784: 033a5663 bge s4,s3,800087b0 <__s2b+0xd8> +80008788: 414989b3 sub s3,s3,s4 +8000878c: 013409b3 add s3,s0,s3 +80008790: 00044683 lbu a3,0(s0) +80008794: 00a00613 li a2,10 +80008798: 00090513 mv a0,s2 +8000879c: fd068693 addi a3,a3,-48 +800087a0: e25ff0ef jal ra,800085c4 <__multadd> +800087a4: 00140413 addi s0,s0,1 +800087a8: 00050593 mv a1,a0 +800087ac: fe8992e3 bne s3,s0,80008790 <__s2b+0xb8> +800087b0: 01c12083 lw ra,28(sp) +800087b4: 01812403 lw s0,24(sp) +800087b8: 01412483 lw s1,20(sp) +800087bc: 01012903 lw s2,16(sp) +800087c0: 00c12983 lw s3,12(sp) +800087c4: 00812a03 lw s4,8(sp) +800087c8: 00412a83 lw s5,4(sp) +800087cc: 00058513 mv a0,a1 +800087d0: 02010113 addi sp,sp,32 +800087d4: 00008067 ret +800087d8: 00a40413 addi s0,s0,10 +800087dc: 00900a13 li s4,9 +800087e0: fa5ff06f j 80008784 <__s2b+0xac> +800087e4: 00000593 li a1,0 +800087e8: f49ff06f j 80008730 <__s2b+0x58> -800085d4 <_Balloc>: -800085d4: 04c52783 lw a5,76(a0) -800085d8: ff010113 addi sp,sp,-16 -800085dc: 00812423 sw s0,8(sp) -800085e0: 00912223 sw s1,4(sp) -800085e4: 00112623 sw ra,12(sp) -800085e8: 01212023 sw s2,0(sp) -800085ec: 00050413 mv s0,a0 -800085f0: 00058493 mv s1,a1 -800085f4: 02078e63 beqz a5,80008630 <_Balloc+0x5c> -800085f8: 00249513 slli a0,s1,0x2 -800085fc: 00a787b3 add a5,a5,a0 -80008600: 0007a503 lw a0,0(a5) -80008604: 04050663 beqz a0,80008650 <_Balloc+0x7c> -80008608: 00052703 lw a4,0(a0) -8000860c: 00e7a023 sw a4,0(a5) -80008610: 00052823 sw zero,16(a0) -80008614: 00052623 sw zero,12(a0) -80008618: 00c12083 lw ra,12(sp) -8000861c: 00812403 lw s0,8(sp) -80008620: 00412483 lw s1,4(sp) -80008624: 00012903 lw s2,0(sp) -80008628: 01010113 addi sp,sp,16 -8000862c: 00008067 ret -80008630: 02100613 li a2,33 -80008634: 00400593 li a1,4 -80008638: 58c050ef jal ra,8000dbc4 <_calloc_r> -8000863c: 04a42623 sw a0,76(s0) -80008640: 00050793 mv a5,a0 -80008644: fa051ae3 bnez a0,800085f8 <_Balloc+0x24> -80008648: 00000513 li a0,0 -8000864c: fcdff06f j 80008618 <_Balloc+0x44> -80008650: 00100913 li s2,1 -80008654: 00991933 sll s2,s2,s1 -80008658: 00590613 addi a2,s2,5 -8000865c: 00261613 slli a2,a2,0x2 -80008660: 00100593 li a1,1 -80008664: 00040513 mv a0,s0 -80008668: 55c050ef jal ra,8000dbc4 <_calloc_r> -8000866c: fc050ee3 beqz a0,80008648 <_Balloc+0x74> -80008670: 00952223 sw s1,4(a0) -80008674: 01252423 sw s2,8(a0) -80008678: f99ff06f j 80008610 <_Balloc+0x3c> +800087ec <__hi0bits>: +800087ec: ffff0737 lui a4,0xffff0 +800087f0: 00e57733 and a4,a0,a4 +800087f4: 00050793 mv a5,a0 +800087f8: 00000513 li a0,0 +800087fc: 00071663 bnez a4,80008808 <__hi0bits+0x1c> +80008800: 01079793 slli a5,a5,0x10 +80008804: 01000513 li a0,16 +80008808: ff000737 lui a4,0xff000 +8000880c: 00e7f733 and a4,a5,a4 +80008810: 00071663 bnez a4,8000881c <__hi0bits+0x30> +80008814: 00850513 addi a0,a0,8 +80008818: 00879793 slli a5,a5,0x8 +8000881c: f0000737 lui a4,0xf0000 +80008820: 00e7f733 and a4,a5,a4 +80008824: 00071663 bnez a4,80008830 <__hi0bits+0x44> +80008828: 00450513 addi a0,a0,4 +8000882c: 00479793 slli a5,a5,0x4 +80008830: c0000737 lui a4,0xc0000 +80008834: 00e7f733 and a4,a5,a4 +80008838: 00071663 bnez a4,80008844 <__hi0bits+0x58> +8000883c: 00250513 addi a0,a0,2 +80008840: 00279793 slli a5,a5,0x2 +80008844: 0007c863 bltz a5,80008854 <__hi0bits+0x68> +80008848: 00179713 slli a4,a5,0x1 +8000884c: 00150513 addi a0,a0,1 +80008850: 00075463 bgez a4,80008858 <__hi0bits+0x6c> +80008854: 00008067 ret +80008858: 02000513 li a0,32 +8000885c: 00008067 ret -8000867c <_Bfree>: -8000867c: 02058063 beqz a1,8000869c <_Bfree+0x20> -80008680: 0045a703 lw a4,4(a1) -80008684: 04c52783 lw a5,76(a0) -80008688: 00271713 slli a4,a4,0x2 -8000868c: 00e787b3 add a5,a5,a4 -80008690: 0007a703 lw a4,0(a5) -80008694: 00e5a023 sw a4,0(a1) -80008698: 00b7a023 sw a1,0(a5) -8000869c: 00008067 ret +80008860 <__lo0bits>: +80008860: 00052783 lw a5,0(a0) +80008864: 00050713 mv a4,a0 +80008868: 0077f693 andi a3,a5,7 +8000886c: 02068463 beqz a3,80008894 <__lo0bits+0x34> +80008870: 0017f693 andi a3,a5,1 +80008874: 00000513 li a0,0 +80008878: 06069e63 bnez a3,800088f4 <__lo0bits+0x94> +8000887c: 0027f693 andi a3,a5,2 +80008880: 08068063 beqz a3,80008900 <__lo0bits+0xa0> +80008884: 0017d793 srli a5,a5,0x1 +80008888: 00f72023 sw a5,0(a4) # c0000000 <__BSS_END__+0x3ffe93c4> +8000888c: 00100513 li a0,1 +80008890: 00008067 ret +80008894: 01079693 slli a3,a5,0x10 +80008898: 0106d693 srli a3,a3,0x10 +8000889c: 00000513 li a0,0 +800088a0: 00069663 bnez a3,800088ac <__lo0bits+0x4c> +800088a4: 0107d793 srli a5,a5,0x10 +800088a8: 01000513 li a0,16 +800088ac: 0ff7f693 andi a3,a5,255 +800088b0: 00069663 bnez a3,800088bc <__lo0bits+0x5c> +800088b4: 00850513 addi a0,a0,8 +800088b8: 0087d793 srli a5,a5,0x8 +800088bc: 00f7f693 andi a3,a5,15 +800088c0: 00069663 bnez a3,800088cc <__lo0bits+0x6c> +800088c4: 00450513 addi a0,a0,4 +800088c8: 0047d793 srli a5,a5,0x4 +800088cc: 0037f693 andi a3,a5,3 +800088d0: 00069663 bnez a3,800088dc <__lo0bits+0x7c> +800088d4: 00250513 addi a0,a0,2 +800088d8: 0027d793 srli a5,a5,0x2 +800088dc: 0017f693 andi a3,a5,1 +800088e0: 00069c63 bnez a3,800088f8 <__lo0bits+0x98> +800088e4: 0017d793 srli a5,a5,0x1 +800088e8: 00150513 addi a0,a0,1 +800088ec: 00079663 bnez a5,800088f8 <__lo0bits+0x98> +800088f0: 02000513 li a0,32 +800088f4: 00008067 ret +800088f8: 00f72023 sw a5,0(a4) +800088fc: 00008067 ret +80008900: 0027d793 srli a5,a5,0x2 +80008904: 00f72023 sw a5,0(a4) +80008908: 00200513 li a0,2 +8000890c: 00008067 ret -800086a0 <__multadd>: -800086a0: fe010113 addi sp,sp,-32 -800086a4: 00912a23 sw s1,20(sp) -800086a8: 0105a483 lw s1,16(a1) -800086ac: 00010337 lui t1,0x10 -800086b0: 00812c23 sw s0,24(sp) -800086b4: 01212823 sw s2,16(sp) -800086b8: 01312623 sw s3,12(sp) -800086bc: 00112e23 sw ra,28(sp) -800086c0: 01412423 sw s4,8(sp) -800086c4: 00058913 mv s2,a1 -800086c8: 00050993 mv s3,a0 -800086cc: 00068413 mv s0,a3 -800086d0: 01458813 addi a6,a1,20 -800086d4: 00000893 li a7,0 -800086d8: fff30313 addi t1,t1,-1 # ffff <_start-0x7fff0001> -800086dc: 00082783 lw a5,0(a6) -800086e0: 00480813 addi a6,a6,4 -800086e4: 00188893 addi a7,a7,1 -800086e8: 0067f6b3 and a3,a5,t1 -800086ec: 02c686b3 mul a3,a3,a2 -800086f0: 0107d793 srli a5,a5,0x10 -800086f4: 02c787b3 mul a5,a5,a2 -800086f8: 008686b3 add a3,a3,s0 -800086fc: 0106de13 srli t3,a3,0x10 -80008700: 0066f733 and a4,a3,t1 -80008704: 01c786b3 add a3,a5,t3 -80008708: 01069793 slli a5,a3,0x10 -8000870c: 00e78733 add a4,a5,a4 -80008710: fee82e23 sw a4,-4(a6) -80008714: 0106d413 srli s0,a3,0x10 -80008718: fc98c2e3 blt a7,s1,800086dc <__multadd+0x3c> -8000871c: 02040263 beqz s0,80008740 <__multadd+0xa0> -80008720: 00892783 lw a5,8(s2) -80008724: 04f4d063 bge s1,a5,80008764 <__multadd+0xc4> -80008728: 00448793 addi a5,s1,4 -8000872c: 00279793 slli a5,a5,0x2 -80008730: 00f907b3 add a5,s2,a5 -80008734: 0087a223 sw s0,4(a5) -80008738: 00148493 addi s1,s1,1 -8000873c: 00992823 sw s1,16(s2) -80008740: 01c12083 lw ra,28(sp) -80008744: 01812403 lw s0,24(sp) -80008748: 01412483 lw s1,20(sp) -8000874c: 00c12983 lw s3,12(sp) -80008750: 00812a03 lw s4,8(sp) -80008754: 00090513 mv a0,s2 -80008758: 01012903 lw s2,16(sp) -8000875c: 02010113 addi sp,sp,32 -80008760: 00008067 ret -80008764: 00492583 lw a1,4(s2) -80008768: 00098513 mv a0,s3 -8000876c: 00158593 addi a1,a1,1 -80008770: e65ff0ef jal ra,800085d4 <_Balloc> -80008774: 01092603 lw a2,16(s2) -80008778: 00050a13 mv s4,a0 -8000877c: 00c90593 addi a1,s2,12 -80008780: 00260613 addi a2,a2,2 -80008784: 00261613 slli a2,a2,0x2 -80008788: 00c50513 addi a0,a0,12 -8000878c: 605050ef jal ra,8000e590 -80008790: 00492703 lw a4,4(s2) -80008794: 04c9a783 lw a5,76(s3) -80008798: 00271713 slli a4,a4,0x2 -8000879c: 00e787b3 add a5,a5,a4 -800087a0: 0007a703 lw a4,0(a5) -800087a4: 00e92023 sw a4,0(s2) -800087a8: 0127a023 sw s2,0(a5) -800087ac: 000a0913 mv s2,s4 -800087b0: f79ff06f j 80008728 <__multadd+0x88> +80008910 <__i2b>: +80008910: ff010113 addi sp,sp,-16 +80008914: 00812423 sw s0,8(sp) +80008918: 00058413 mv s0,a1 +8000891c: 00100593 li a1,1 +80008920: 00112623 sw ra,12(sp) +80008924: bd5ff0ef jal ra,800084f8 <_Balloc> +80008928: 00c12083 lw ra,12(sp) +8000892c: 00852a23 sw s0,20(a0) +80008930: 00812403 lw s0,8(sp) +80008934: 00100713 li a4,1 +80008938: 00e52823 sw a4,16(a0) +8000893c: 01010113 addi sp,sp,16 +80008940: 00008067 ret -800087b4 <__s2b>: -800087b4: fe010113 addi sp,sp,-32 -800087b8: 00812c23 sw s0,24(sp) -800087bc: 00912a23 sw s1,20(sp) -800087c0: 01212823 sw s2,16(sp) -800087c4: 01312623 sw s3,12(sp) -800087c8: 01412423 sw s4,8(sp) -800087cc: 00868813 addi a6,a3,8 -800087d0: 00900793 li a5,9 -800087d4: 00112e23 sw ra,28(sp) -800087d8: 01512223 sw s5,4(sp) -800087dc: 02f84833 div a6,a6,a5 -800087e0: 00068993 mv s3,a3 -800087e4: 00050913 mv s2,a0 -800087e8: 00058413 mv s0,a1 -800087ec: 00060a13 mv s4,a2 -800087f0: 00070493 mv s1,a4 -800087f4: 0cd7d663 bge a5,a3,800088c0 <__s2b+0x10c> -800087f8: 00100793 li a5,1 -800087fc: 00000593 li a1,0 -80008800: 00179793 slli a5,a5,0x1 -80008804: 00158593 addi a1,a1,1 -80008808: ff07cce3 blt a5,a6,80008800 <__s2b+0x4c> -8000880c: 00090513 mv a0,s2 -80008810: dc5ff0ef jal ra,800085d4 <_Balloc> -80008814: 00100793 li a5,1 -80008818: 00f52823 sw a5,16(a0) -8000881c: 00952a23 sw s1,20(a0) -80008820: 00900793 li a5,9 -80008824: 00050593 mv a1,a0 -80008828: 0947d663 bge a5,s4,800088b4 <__s2b+0x100> -8000882c: 00940a93 addi s5,s0,9 -80008830: 000a8493 mv s1,s5 -80008834: 01440433 add s0,s0,s4 -80008838: 0004c683 lbu a3,0(s1) -8000883c: 00a00613 li a2,10 -80008840: 00090513 mv a0,s2 -80008844: fd068693 addi a3,a3,-48 -80008848: e59ff0ef jal ra,800086a0 <__multadd> -8000884c: 00148493 addi s1,s1,1 -80008850: 00050593 mv a1,a0 -80008854: fe8492e3 bne s1,s0,80008838 <__s2b+0x84> -80008858: ff8a0413 addi s0,s4,-8 -8000885c: 008a8433 add s0,s5,s0 -80008860: 033a5663 bge s4,s3,8000888c <__s2b+0xd8> -80008864: 414989b3 sub s3,s3,s4 -80008868: 013409b3 add s3,s0,s3 -8000886c: 00044683 lbu a3,0(s0) -80008870: 00a00613 li a2,10 -80008874: 00090513 mv a0,s2 -80008878: fd068693 addi a3,a3,-48 -8000887c: e25ff0ef jal ra,800086a0 <__multadd> -80008880: 00140413 addi s0,s0,1 -80008884: 00050593 mv a1,a0 -80008888: fe8992e3 bne s3,s0,8000886c <__s2b+0xb8> -8000888c: 01c12083 lw ra,28(sp) -80008890: 01812403 lw s0,24(sp) -80008894: 01412483 lw s1,20(sp) -80008898: 01012903 lw s2,16(sp) -8000889c: 00c12983 lw s3,12(sp) -800088a0: 00812a03 lw s4,8(sp) -800088a4: 00412a83 lw s5,4(sp) -800088a8: 00058513 mv a0,a1 -800088ac: 02010113 addi sp,sp,32 -800088b0: 00008067 ret -800088b4: 00a40413 addi s0,s0,10 -800088b8: 00900a13 li s4,9 -800088bc: fa5ff06f j 80008860 <__s2b+0xac> -800088c0: 00000593 li a1,0 -800088c4: f49ff06f j 8000880c <__s2b+0x58> +80008944 <__multiply>: +80008944: fe010113 addi sp,sp,-32 +80008948: 01212823 sw s2,16(sp) +8000894c: 01312623 sw s3,12(sp) +80008950: 0105a903 lw s2,16(a1) +80008954: 01062983 lw s3,16(a2) +80008958: 00912a23 sw s1,20(sp) +8000895c: 01412423 sw s4,8(sp) +80008960: 00112e23 sw ra,28(sp) +80008964: 00812c23 sw s0,24(sp) +80008968: 00058a13 mv s4,a1 +8000896c: 00060493 mv s1,a2 +80008970: 01394c63 blt s2,s3,80008988 <__multiply+0x44> +80008974: 00098713 mv a4,s3 +80008978: 00058493 mv s1,a1 +8000897c: 00090993 mv s3,s2 +80008980: 00060a13 mv s4,a2 +80008984: 00070913 mv s2,a4 +80008988: 0084a783 lw a5,8(s1) +8000898c: 0044a583 lw a1,4(s1) +80008990: 01298433 add s0,s3,s2 +80008994: 0087a7b3 slt a5,a5,s0 +80008998: 00f585b3 add a1,a1,a5 +8000899c: b5dff0ef jal ra,800084f8 <_Balloc> +800089a0: 01450313 addi t1,a0,20 +800089a4: 00241893 slli a7,s0,0x2 +800089a8: 011308b3 add a7,t1,a7 +800089ac: 00030793 mv a5,t1 +800089b0: 01137863 bgeu t1,a7,800089c0 <__multiply+0x7c> +800089b4: 0007a023 sw zero,0(a5) +800089b8: 00478793 addi a5,a5,4 +800089bc: ff17ece3 bltu a5,a7,800089b4 <__multiply+0x70> +800089c0: 014a0813 addi a6,s4,20 +800089c4: 00291e13 slli t3,s2,0x2 +800089c8: 01448e93 addi t4,s1,20 +800089cc: 00299593 slli a1,s3,0x2 +800089d0: 01c80e33 add t3,a6,t3 +800089d4: 00be85b3 add a1,t4,a1 +800089d8: 13c87663 bgeu a6,t3,80008b04 <__multiply+0x1c0> +800089dc: 01548793 addi a5,s1,21 +800089e0: 00400f13 li t5,4 +800089e4: 16f5f063 bgeu a1,a5,80008b44 <__multiply+0x200> +800089e8: 00010637 lui a2,0x10 +800089ec: fff60613 addi a2,a2,-1 # ffff <_start-0x7fff0001> +800089f0: 0180006f j 80008a08 <__multiply+0xc4> +800089f4: 010fdf93 srli t6,t6,0x10 +800089f8: 080f9863 bnez t6,80008a88 <__multiply+0x144> +800089fc: 00480813 addi a6,a6,4 +80008a00: 00430313 addi t1,t1,4 +80008a04: 11c87063 bgeu a6,t3,80008b04 <__multiply+0x1c0> +80008a08: 00082f83 lw t6,0(a6) +80008a0c: 00cff4b3 and s1,t6,a2 +80008a10: fe0482e3 beqz s1,800089f4 <__multiply+0xb0> +80008a14: 00030393 mv t2,t1 +80008a18: 000e8293 mv t0,t4 +80008a1c: 00000913 li s2,0 +80008a20: 0002a703 lw a4,0(t0) # 800084c8 +80008a24: 0003af83 lw t6,0(t2) +80008a28: 00438393 addi t2,t2,4 +80008a2c: 00c776b3 and a3,a4,a2 +80008a30: 029686b3 mul a3,a3,s1 +80008a34: 01075793 srli a5,a4,0x10 +80008a38: 00cff733 and a4,t6,a2 +80008a3c: 010fdf93 srli t6,t6,0x10 +80008a40: 00428293 addi t0,t0,4 +80008a44: 029787b3 mul a5,a5,s1 +80008a48: 00e686b3 add a3,a3,a4 +80008a4c: 012686b3 add a3,a3,s2 +80008a50: 0106d713 srli a4,a3,0x10 +80008a54: 00c6f6b3 and a3,a3,a2 +80008a58: 01f787b3 add a5,a5,t6 +80008a5c: 00e787b3 add a5,a5,a4 +80008a60: 01079713 slli a4,a5,0x10 +80008a64: 00d766b3 or a3,a4,a3 +80008a68: fed3ae23 sw a3,-4(t2) +80008a6c: 0107d913 srli s2,a5,0x10 +80008a70: fab2e8e3 bltu t0,a1,80008a20 <__multiply+0xdc> +80008a74: 01e307b3 add a5,t1,t5 +80008a78: 0127a023 sw s2,0(a5) +80008a7c: 00082f83 lw t6,0(a6) +80008a80: 010fdf93 srli t6,t6,0x10 +80008a84: f60f8ce3 beqz t6,800089fc <__multiply+0xb8> +80008a88: 00032703 lw a4,0(t1) +80008a8c: 00030293 mv t0,t1 +80008a90: 000e8693 mv a3,t4 +80008a94: 00070493 mv s1,a4 +80008a98: 00000393 li t2,0 +80008a9c: 0006a783 lw a5,0(a3) +80008aa0: 0104d993 srli s3,s1,0x10 +80008aa4: 00c77733 and a4,a4,a2 +80008aa8: 00c7f7b3 and a5,a5,a2 +80008aac: 03f787b3 mul a5,a5,t6 +80008ab0: 0042a483 lw s1,4(t0) +80008ab4: 00428293 addi t0,t0,4 +80008ab8: 00468693 addi a3,a3,4 +80008abc: 00c4f933 and s2,s1,a2 +80008ac0: 013787b3 add a5,a5,s3 +80008ac4: 007787b3 add a5,a5,t2 +80008ac8: 01079393 slli t2,a5,0x10 +80008acc: 00e3e733 or a4,t2,a4 +80008ad0: fee2ae23 sw a4,-4(t0) +80008ad4: ffe6d703 lhu a4,-2(a3) +80008ad8: 0107d793 srli a5,a5,0x10 +80008adc: 03f70733 mul a4,a4,t6 +80008ae0: 01270733 add a4,a4,s2 +80008ae4: 00f70733 add a4,a4,a5 +80008ae8: 01075393 srli t2,a4,0x10 +80008aec: fab6e8e3 bltu a3,a1,80008a9c <__multiply+0x158> +80008af0: 01e307b3 add a5,t1,t5 +80008af4: 00e7a023 sw a4,0(a5) +80008af8: 00480813 addi a6,a6,4 +80008afc: 00430313 addi t1,t1,4 +80008b00: f1c864e3 bltu a6,t3,80008a08 <__multiply+0xc4> +80008b04: 00804863 bgtz s0,80008b14 <__multiply+0x1d0> +80008b08: 0180006f j 80008b20 <__multiply+0x1dc> +80008b0c: fff40413 addi s0,s0,-1 +80008b10: 00040863 beqz s0,80008b20 <__multiply+0x1dc> +80008b14: ffc8a783 lw a5,-4(a7) +80008b18: ffc88893 addi a7,a7,-4 +80008b1c: fe0788e3 beqz a5,80008b0c <__multiply+0x1c8> +80008b20: 01c12083 lw ra,28(sp) +80008b24: 00852823 sw s0,16(a0) +80008b28: 01812403 lw s0,24(sp) +80008b2c: 01412483 lw s1,20(sp) +80008b30: 01012903 lw s2,16(sp) +80008b34: 00c12983 lw s3,12(sp) +80008b38: 00812a03 lw s4,8(sp) +80008b3c: 02010113 addi sp,sp,32 +80008b40: 00008067 ret +80008b44: 40958f33 sub t5,a1,s1 +80008b48: febf0f13 addi t5,t5,-21 +80008b4c: ffcf7f13 andi t5,t5,-4 +80008b50: 004f0f13 addi t5,t5,4 +80008b54: e95ff06f j 800089e8 <__multiply+0xa4> -800088c8 <__hi0bits>: -800088c8: ffff0737 lui a4,0xffff0 -800088cc: 00e57733 and a4,a0,a4 -800088d0: 00050793 mv a5,a0 -800088d4: 00000513 li a0,0 -800088d8: 00071663 bnez a4,800088e4 <__hi0bits+0x1c> -800088dc: 01079793 slli a5,a5,0x10 -800088e0: 01000513 li a0,16 -800088e4: ff000737 lui a4,0xff000 -800088e8: 00e7f733 and a4,a5,a4 -800088ec: 00071663 bnez a4,800088f8 <__hi0bits+0x30> -800088f0: 00850513 addi a0,a0,8 -800088f4: 00879793 slli a5,a5,0x8 -800088f8: f0000737 lui a4,0xf0000 -800088fc: 00e7f733 and a4,a5,a4 -80008900: 00071663 bnez a4,8000890c <__hi0bits+0x44> -80008904: 00450513 addi a0,a0,4 -80008908: 00479793 slli a5,a5,0x4 -8000890c: c0000737 lui a4,0xc0000 -80008910: 00e7f733 and a4,a5,a4 -80008914: 00071663 bnez a4,80008920 <__hi0bits+0x58> -80008918: 00250513 addi a0,a0,2 -8000891c: 00279793 slli a5,a5,0x2 -80008920: 0007c863 bltz a5,80008930 <__hi0bits+0x68> -80008924: 00179713 slli a4,a5,0x1 -80008928: 00150513 addi a0,a0,1 -8000892c: 00075463 bgez a4,80008934 <__hi0bits+0x6c> -80008930: 00008067 ret -80008934: 02000513 li a0,32 -80008938: 00008067 ret - -8000893c <__lo0bits>: -8000893c: 00052783 lw a5,0(a0) -80008940: 00050713 mv a4,a0 -80008944: 0077f693 andi a3,a5,7 -80008948: 02068463 beqz a3,80008970 <__lo0bits+0x34> -8000894c: 0017f693 andi a3,a5,1 -80008950: 00000513 li a0,0 -80008954: 06069e63 bnez a3,800089d0 <__lo0bits+0x94> -80008958: 0027f693 andi a3,a5,2 -8000895c: 08068063 beqz a3,800089dc <__lo0bits+0xa0> -80008960: 0017d793 srli a5,a5,0x1 -80008964: 00f72023 sw a5,0(a4) # c0000000 <__BSS_END__+0x3ffe93d0> -80008968: 00100513 li a0,1 -8000896c: 00008067 ret -80008970: 01079693 slli a3,a5,0x10 -80008974: 0106d693 srli a3,a3,0x10 -80008978: 00000513 li a0,0 -8000897c: 00069663 bnez a3,80008988 <__lo0bits+0x4c> -80008980: 0107d793 srli a5,a5,0x10 -80008984: 01000513 li a0,16 -80008988: 0ff7f693 andi a3,a5,255 -8000898c: 00069663 bnez a3,80008998 <__lo0bits+0x5c> -80008990: 00850513 addi a0,a0,8 -80008994: 0087d793 srli a5,a5,0x8 -80008998: 00f7f693 andi a3,a5,15 -8000899c: 00069663 bnez a3,800089a8 <__lo0bits+0x6c> -800089a0: 00450513 addi a0,a0,4 -800089a4: 0047d793 srli a5,a5,0x4 -800089a8: 0037f693 andi a3,a5,3 -800089ac: 00069663 bnez a3,800089b8 <__lo0bits+0x7c> -800089b0: 00250513 addi a0,a0,2 -800089b4: 0027d793 srli a5,a5,0x2 -800089b8: 0017f693 andi a3,a5,1 -800089bc: 00069c63 bnez a3,800089d4 <__lo0bits+0x98> -800089c0: 0017d793 srli a5,a5,0x1 -800089c4: 00150513 addi a0,a0,1 -800089c8: 00079663 bnez a5,800089d4 <__lo0bits+0x98> -800089cc: 02000513 li a0,32 -800089d0: 00008067 ret -800089d4: 00f72023 sw a5,0(a4) -800089d8: 00008067 ret -800089dc: 0027d793 srli a5,a5,0x2 -800089e0: 00f72023 sw a5,0(a4) -800089e4: 00200513 li a0,2 -800089e8: 00008067 ret - -800089ec <__i2b>: -800089ec: ff010113 addi sp,sp,-16 -800089f0: 00812423 sw s0,8(sp) -800089f4: 00058413 mv s0,a1 -800089f8: 00100593 li a1,1 -800089fc: 00112623 sw ra,12(sp) -80008a00: bd5ff0ef jal ra,800085d4 <_Balloc> -80008a04: 00c12083 lw ra,12(sp) -80008a08: 00852a23 sw s0,20(a0) -80008a0c: 00812403 lw s0,8(sp) -80008a10: 00100713 li a4,1 -80008a14: 00e52823 sw a4,16(a0) -80008a18: 01010113 addi sp,sp,16 -80008a1c: 00008067 ret - -80008a20 <__multiply>: -80008a20: fe010113 addi sp,sp,-32 -80008a24: 01212823 sw s2,16(sp) -80008a28: 01312623 sw s3,12(sp) -80008a2c: 0105a903 lw s2,16(a1) -80008a30: 01062983 lw s3,16(a2) -80008a34: 00912a23 sw s1,20(sp) -80008a38: 01412423 sw s4,8(sp) -80008a3c: 00112e23 sw ra,28(sp) -80008a40: 00812c23 sw s0,24(sp) -80008a44: 00058a13 mv s4,a1 -80008a48: 00060493 mv s1,a2 -80008a4c: 01394c63 blt s2,s3,80008a64 <__multiply+0x44> -80008a50: 00098713 mv a4,s3 -80008a54: 00058493 mv s1,a1 -80008a58: 00090993 mv s3,s2 -80008a5c: 00060a13 mv s4,a2 -80008a60: 00070913 mv s2,a4 -80008a64: 0084a783 lw a5,8(s1) -80008a68: 0044a583 lw a1,4(s1) -80008a6c: 01298433 add s0,s3,s2 -80008a70: 0087a7b3 slt a5,a5,s0 -80008a74: 00f585b3 add a1,a1,a5 -80008a78: b5dff0ef jal ra,800085d4 <_Balloc> -80008a7c: 01450313 addi t1,a0,20 -80008a80: 00241893 slli a7,s0,0x2 -80008a84: 011308b3 add a7,t1,a7 -80008a88: 00030793 mv a5,t1 -80008a8c: 01137863 bgeu t1,a7,80008a9c <__multiply+0x7c> -80008a90: 0007a023 sw zero,0(a5) -80008a94: 00478793 addi a5,a5,4 -80008a98: ff17ece3 bltu a5,a7,80008a90 <__multiply+0x70> -80008a9c: 014a0813 addi a6,s4,20 -80008aa0: 00291e13 slli t3,s2,0x2 -80008aa4: 01448e93 addi t4,s1,20 -80008aa8: 00299593 slli a1,s3,0x2 -80008aac: 01c80e33 add t3,a6,t3 -80008ab0: 00be85b3 add a1,t4,a1 -80008ab4: 13c87663 bgeu a6,t3,80008be0 <__multiply+0x1c0> -80008ab8: 01548793 addi a5,s1,21 -80008abc: 00400f13 li t5,4 -80008ac0: 16f5f063 bgeu a1,a5,80008c20 <__multiply+0x200> -80008ac4: 00010637 lui a2,0x10 -80008ac8: fff60613 addi a2,a2,-1 # ffff <_start-0x7fff0001> -80008acc: 0180006f j 80008ae4 <__multiply+0xc4> -80008ad0: 010fdf93 srli t6,t6,0x10 -80008ad4: 080f9863 bnez t6,80008b64 <__multiply+0x144> -80008ad8: 00480813 addi a6,a6,4 -80008adc: 00430313 addi t1,t1,4 -80008ae0: 11c87063 bgeu a6,t3,80008be0 <__multiply+0x1c0> -80008ae4: 00082f83 lw t6,0(a6) -80008ae8: 00cff4b3 and s1,t6,a2 -80008aec: fe0482e3 beqz s1,80008ad0 <__multiply+0xb0> -80008af0: 00030393 mv t2,t1 -80008af4: 000e8293 mv t0,t4 -80008af8: 00000913 li s2,0 -80008afc: 0002a703 lw a4,0(t0) # 800013ec -80008b00: 0003af83 lw t6,0(t2) -80008b04: 00438393 addi t2,t2,4 -80008b08: 00c776b3 and a3,a4,a2 -80008b0c: 029686b3 mul a3,a3,s1 -80008b10: 01075793 srli a5,a4,0x10 -80008b14: 00cff733 and a4,t6,a2 -80008b18: 010fdf93 srli t6,t6,0x10 -80008b1c: 00428293 addi t0,t0,4 -80008b20: 029787b3 mul a5,a5,s1 -80008b24: 00e686b3 add a3,a3,a4 -80008b28: 012686b3 add a3,a3,s2 -80008b2c: 0106d713 srli a4,a3,0x10 -80008b30: 00c6f6b3 and a3,a3,a2 -80008b34: 01f787b3 add a5,a5,t6 -80008b38: 00e787b3 add a5,a5,a4 -80008b3c: 01079713 slli a4,a5,0x10 -80008b40: 00d766b3 or a3,a4,a3 -80008b44: fed3ae23 sw a3,-4(t2) -80008b48: 0107d913 srli s2,a5,0x10 -80008b4c: fab2e8e3 bltu t0,a1,80008afc <__multiply+0xdc> -80008b50: 01e307b3 add a5,t1,t5 -80008b54: 0127a023 sw s2,0(a5) -80008b58: 00082f83 lw t6,0(a6) -80008b5c: 010fdf93 srli t6,t6,0x10 -80008b60: f60f8ce3 beqz t6,80008ad8 <__multiply+0xb8> -80008b64: 00032703 lw a4,0(t1) -80008b68: 00030293 mv t0,t1 -80008b6c: 000e8693 mv a3,t4 -80008b70: 00070493 mv s1,a4 -80008b74: 00000393 li t2,0 -80008b78: 0006a783 lw a5,0(a3) -80008b7c: 0104d993 srli s3,s1,0x10 -80008b80: 00c77733 and a4,a4,a2 -80008b84: 00c7f7b3 and a5,a5,a2 -80008b88: 03f787b3 mul a5,a5,t6 -80008b8c: 0042a483 lw s1,4(t0) -80008b90: 00428293 addi t0,t0,4 -80008b94: 00468693 addi a3,a3,4 -80008b98: 00c4f933 and s2,s1,a2 -80008b9c: 013787b3 add a5,a5,s3 -80008ba0: 007787b3 add a5,a5,t2 -80008ba4: 01079393 slli t2,a5,0x10 -80008ba8: 00e3e733 or a4,t2,a4 -80008bac: fee2ae23 sw a4,-4(t0) -80008bb0: ffe6d703 lhu a4,-2(a3) -80008bb4: 0107d793 srli a5,a5,0x10 -80008bb8: 03f70733 mul a4,a4,t6 -80008bbc: 01270733 add a4,a4,s2 -80008bc0: 00f70733 add a4,a4,a5 -80008bc4: 01075393 srli t2,a4,0x10 -80008bc8: fab6e8e3 bltu a3,a1,80008b78 <__multiply+0x158> -80008bcc: 01e307b3 add a5,t1,t5 -80008bd0: 00e7a023 sw a4,0(a5) -80008bd4: 00480813 addi a6,a6,4 -80008bd8: 00430313 addi t1,t1,4 -80008bdc: f1c864e3 bltu a6,t3,80008ae4 <__multiply+0xc4> -80008be0: 00804863 bgtz s0,80008bf0 <__multiply+0x1d0> -80008be4: 0180006f j 80008bfc <__multiply+0x1dc> -80008be8: fff40413 addi s0,s0,-1 -80008bec: 00040863 beqz s0,80008bfc <__multiply+0x1dc> -80008bf0: ffc8a783 lw a5,-4(a7) -80008bf4: ffc88893 addi a7,a7,-4 -80008bf8: fe0788e3 beqz a5,80008be8 <__multiply+0x1c8> -80008bfc: 01c12083 lw ra,28(sp) -80008c00: 00852823 sw s0,16(a0) +80008b58 <__pow5mult>: +80008b58: fe010113 addi sp,sp,-32 +80008b5c: 00812c23 sw s0,24(sp) +80008b60: 01312623 sw s3,12(sp) +80008b64: 01412423 sw s4,8(sp) +80008b68: 00112e23 sw ra,28(sp) +80008b6c: 00912a23 sw s1,20(sp) +80008b70: 01212823 sw s2,16(sp) +80008b74: 00367793 andi a5,a2,3 +80008b78: 00060413 mv s0,a2 +80008b7c: 00050993 mv s3,a0 +80008b80: 00058a13 mv s4,a1 +80008b84: 0c079463 bnez a5,80008c4c <__pow5mult+0xf4> +80008b88: 40245413 srai s0,s0,0x2 +80008b8c: 000a0913 mv s2,s4 +80008b90: 06040863 beqz s0,80008c00 <__pow5mult+0xa8> +80008b94: 0489a483 lw s1,72(s3) +80008b98: 0c048e63 beqz s1,80008c74 <__pow5mult+0x11c> +80008b9c: 00147793 andi a5,s0,1 +80008ba0: 000a0913 mv s2,s4 +80008ba4: 02079063 bnez a5,80008bc4 <__pow5mult+0x6c> +80008ba8: 40145413 srai s0,s0,0x1 +80008bac: 04040a63 beqz s0,80008c00 <__pow5mult+0xa8> +80008bb0: 0004a503 lw a0,0(s1) +80008bb4: 06050863 beqz a0,80008c24 <__pow5mult+0xcc> +80008bb8: 00050493 mv s1,a0 +80008bbc: 00147793 andi a5,s0,1 +80008bc0: fe0784e3 beqz a5,80008ba8 <__pow5mult+0x50> +80008bc4: 00048613 mv a2,s1 +80008bc8: 00090593 mv a1,s2 +80008bcc: 00098513 mv a0,s3 +80008bd0: d75ff0ef jal ra,80008944 <__multiply> +80008bd4: 06090863 beqz s2,80008c44 <__pow5mult+0xec> +80008bd8: 00492703 lw a4,4(s2) +80008bdc: 04c9a783 lw a5,76(s3) +80008be0: 40145413 srai s0,s0,0x1 +80008be4: 00271713 slli a4,a4,0x2 +80008be8: 00e787b3 add a5,a5,a4 +80008bec: 0007a703 lw a4,0(a5) +80008bf0: 00e92023 sw a4,0(s2) +80008bf4: 0127a023 sw s2,0(a5) +80008bf8: 00050913 mv s2,a0 +80008bfc: fa041ae3 bnez s0,80008bb0 <__pow5mult+0x58> +80008c00: 01c12083 lw ra,28(sp) 80008c04: 01812403 lw s0,24(sp) 80008c08: 01412483 lw s1,20(sp) -80008c0c: 01012903 lw s2,16(sp) -80008c10: 00c12983 lw s3,12(sp) -80008c14: 00812a03 lw s4,8(sp) -80008c18: 02010113 addi sp,sp,32 -80008c1c: 00008067 ret -80008c20: 40958f33 sub t5,a1,s1 -80008c24: febf0f13 addi t5,t5,-21 -80008c28: ffcf7f13 andi t5,t5,-4 -80008c2c: 004f0f13 addi t5,t5,4 -80008c30: e95ff06f j 80008ac4 <__multiply+0xa4> - -80008c34 <__pow5mult>: -80008c34: fe010113 addi sp,sp,-32 -80008c38: 00812c23 sw s0,24(sp) -80008c3c: 01312623 sw s3,12(sp) -80008c40: 01412423 sw s4,8(sp) -80008c44: 00112e23 sw ra,28(sp) -80008c48: 00912a23 sw s1,20(sp) -80008c4c: 01212823 sw s2,16(sp) -80008c50: 00367793 andi a5,a2,3 -80008c54: 00060413 mv s0,a2 -80008c58: 00050993 mv s3,a0 -80008c5c: 00058a13 mv s4,a1 -80008c60: 0c079463 bnez a5,80008d28 <__pow5mult+0xf4> -80008c64: 40245413 srai s0,s0,0x2 -80008c68: 000a0913 mv s2,s4 -80008c6c: 06040863 beqz s0,80008cdc <__pow5mult+0xa8> -80008c70: 0489a483 lw s1,72(s3) -80008c74: 0c048e63 beqz s1,80008d50 <__pow5mult+0x11c> -80008c78: 00147793 andi a5,s0,1 -80008c7c: 000a0913 mv s2,s4 -80008c80: 02079063 bnez a5,80008ca0 <__pow5mult+0x6c> -80008c84: 40145413 srai s0,s0,0x1 -80008c88: 04040a63 beqz s0,80008cdc <__pow5mult+0xa8> -80008c8c: 0004a503 lw a0,0(s1) -80008c90: 06050863 beqz a0,80008d00 <__pow5mult+0xcc> +80008c0c: 00c12983 lw s3,12(sp) +80008c10: 00812a03 lw s4,8(sp) +80008c14: 00090513 mv a0,s2 +80008c18: 01012903 lw s2,16(sp) +80008c1c: 02010113 addi sp,sp,32 +80008c20: 00008067 ret +80008c24: 00048613 mv a2,s1 +80008c28: 00048593 mv a1,s1 +80008c2c: 00098513 mv a0,s3 +80008c30: d15ff0ef jal ra,80008944 <__multiply> +80008c34: 00a4a023 sw a0,0(s1) +80008c38: 00052023 sw zero,0(a0) +80008c3c: 00050493 mv s1,a0 +80008c40: f7dff06f j 80008bbc <__pow5mult+0x64> +80008c44: 00050913 mv s2,a0 +80008c48: f61ff06f j 80008ba8 <__pow5mult+0x50> +80008c4c: fff78793 addi a5,a5,-1 +80008c50: 80015737 lui a4,0x80015 +80008c54: 0b870713 addi a4,a4,184 # 800150b8 <__BSS_END__+0xffffe47c> +80008c58: 00279793 slli a5,a5,0x2 +80008c5c: 00f707b3 add a5,a4,a5 +80008c60: 0007a603 lw a2,0(a5) +80008c64: 00000693 li a3,0 +80008c68: 95dff0ef jal ra,800085c4 <__multadd> +80008c6c: 00050a13 mv s4,a0 +80008c70: f19ff06f j 80008b88 <__pow5mult+0x30> +80008c74: 00100593 li a1,1 +80008c78: 00098513 mv a0,s3 +80008c7c: 87dff0ef jal ra,800084f8 <_Balloc> +80008c80: 27100793 li a5,625 +80008c84: 00f52a23 sw a5,20(a0) +80008c88: 00100793 li a5,1 +80008c8c: 00f52823 sw a5,16(a0) +80008c90: 04a9a423 sw a0,72(s3) 80008c94: 00050493 mv s1,a0 -80008c98: 00147793 andi a5,s0,1 -80008c9c: fe0784e3 beqz a5,80008c84 <__pow5mult+0x50> -80008ca0: 00048613 mv a2,s1 -80008ca4: 00090593 mv a1,s2 -80008ca8: 00098513 mv a0,s3 -80008cac: d75ff0ef jal ra,80008a20 <__multiply> -80008cb0: 06090863 beqz s2,80008d20 <__pow5mult+0xec> -80008cb4: 00492703 lw a4,4(s2) -80008cb8: 04c9a783 lw a5,76(s3) -80008cbc: 40145413 srai s0,s0,0x1 -80008cc0: 00271713 slli a4,a4,0x2 -80008cc4: 00e787b3 add a5,a5,a4 -80008cc8: 0007a703 lw a4,0(a5) -80008ccc: 00e92023 sw a4,0(s2) -80008cd0: 0127a023 sw s2,0(a5) -80008cd4: 00050913 mv s2,a0 -80008cd8: fa041ae3 bnez s0,80008c8c <__pow5mult+0x58> -80008cdc: 01c12083 lw ra,28(sp) -80008ce0: 01812403 lw s0,24(sp) -80008ce4: 01412483 lw s1,20(sp) -80008ce8: 00c12983 lw s3,12(sp) -80008cec: 00812a03 lw s4,8(sp) -80008cf0: 00090513 mv a0,s2 -80008cf4: 01012903 lw s2,16(sp) -80008cf8: 02010113 addi sp,sp,32 -80008cfc: 00008067 ret -80008d00: 00048613 mv a2,s1 -80008d04: 00048593 mv a1,s1 -80008d08: 00098513 mv a0,s3 -80008d0c: d15ff0ef jal ra,80008a20 <__multiply> -80008d10: 00a4a023 sw a0,0(s1) -80008d14: 00052023 sw zero,0(a0) -80008d18: 00050493 mv s1,a0 -80008d1c: f7dff06f j 80008c98 <__pow5mult+0x64> -80008d20: 00050913 mv s2,a0 -80008d24: f61ff06f j 80008c84 <__pow5mult+0x50> -80008d28: fff78793 addi a5,a5,-1 -80008d2c: 80015737 lui a4,0x80015 -80008d30: 07870713 addi a4,a4,120 # 80015078 <__BSS_END__+0xffffe448> -80008d34: 00279793 slli a5,a5,0x2 -80008d38: 00f707b3 add a5,a4,a5 -80008d3c: 0007a603 lw a2,0(a5) -80008d40: 00000693 li a3,0 -80008d44: 95dff0ef jal ra,800086a0 <__multadd> -80008d48: 00050a13 mv s4,a0 -80008d4c: f19ff06f j 80008c64 <__pow5mult+0x30> -80008d50: 00100593 li a1,1 -80008d54: 00098513 mv a0,s3 -80008d58: 87dff0ef jal ra,800085d4 <_Balloc> -80008d5c: 27100793 li a5,625 -80008d60: 00f52a23 sw a5,20(a0) -80008d64: 00100793 li a5,1 -80008d68: 00f52823 sw a5,16(a0) -80008d6c: 04a9a423 sw a0,72(s3) -80008d70: 00050493 mv s1,a0 -80008d74: 00052023 sw zero,0(a0) -80008d78: f01ff06f j 80008c78 <__pow5mult+0x44> +80008c98: 00052023 sw zero,0(a0) +80008c9c: f01ff06f j 80008b9c <__pow5mult+0x44> -80008d7c <__lshift>: -80008d7c: fe010113 addi sp,sp,-32 -80008d80: 01412423 sw s4,8(sp) -80008d84: 0105aa03 lw s4,16(a1) -80008d88: 0085a783 lw a5,8(a1) -80008d8c: 01312623 sw s3,12(sp) -80008d90: 40565993 srai s3,a2,0x5 -80008d94: 01498a33 add s4,s3,s4 -80008d98: 00812c23 sw s0,24(sp) -80008d9c: 00912a23 sw s1,20(sp) -80008da0: 01212823 sw s2,16(sp) -80008da4: 01512223 sw s5,4(sp) -80008da8: 00112e23 sw ra,28(sp) -80008dac: 001a0913 addi s2,s4,1 -80008db0: 00058493 mv s1,a1 -80008db4: 00060413 mv s0,a2 -80008db8: 0045a583 lw a1,4(a1) -80008dbc: 00050a93 mv s5,a0 -80008dc0: 0127d863 bge a5,s2,80008dd0 <__lshift+0x54> -80008dc4: 00179793 slli a5,a5,0x1 -80008dc8: 00158593 addi a1,a1,1 -80008dcc: ff27cce3 blt a5,s2,80008dc4 <__lshift+0x48> -80008dd0: 000a8513 mv a0,s5 -80008dd4: 801ff0ef jal ra,800085d4 <_Balloc> -80008dd8: 01450813 addi a6,a0,20 -80008ddc: 03305463 blez s3,80008e04 <__lshift+0x88> -80008de0: 00598993 addi s3,s3,5 -80008de4: 00299993 slli s3,s3,0x2 -80008de8: 01350733 add a4,a0,s3 -80008dec: 00080793 mv a5,a6 -80008df0: 00478793 addi a5,a5,4 -80008df4: fe07ae23 sw zero,-4(a5) -80008df8: fee79ce3 bne a5,a4,80008df0 <__lshift+0x74> -80008dfc: fec98993 addi s3,s3,-20 -80008e00: 01380833 add a6,a6,s3 -80008e04: 0104a703 lw a4,16(s1) -80008e08: 01448793 addi a5,s1,20 -80008e0c: 01f47313 andi t1,s0,31 -80008e10: 00271613 slli a2,a4,0x2 -80008e14: 00c78633 add a2,a5,a2 -80008e18: 08030c63 beqz t1,80008eb0 <__lshift+0x134> -80008e1c: 02000593 li a1,32 -80008e20: 406585b3 sub a1,a1,t1 -80008e24: 00080893 mv a7,a6 -80008e28: 00000693 li a3,0 -80008e2c: 0007a703 lw a4,0(a5) -80008e30: 00488893 addi a7,a7,4 -80008e34: 00478793 addi a5,a5,4 -80008e38: 00671733 sll a4,a4,t1 -80008e3c: 00d76733 or a4,a4,a3 -80008e40: fee8ae23 sw a4,-4(a7) -80008e44: ffc7a703 lw a4,-4(a5) -80008e48: 00b756b3 srl a3,a4,a1 -80008e4c: fec7e0e3 bltu a5,a2,80008e2c <__lshift+0xb0> -80008e50: 01548713 addi a4,s1,21 -80008e54: 00400793 li a5,4 -80008e58: 08e67263 bgeu a2,a4,80008edc <__lshift+0x160> -80008e5c: 00f80833 add a6,a6,a5 -80008e60: 00d82023 sw a3,0(a6) -80008e64: 00068463 beqz a3,80008e6c <__lshift+0xf0> -80008e68: 00090a13 mv s4,s2 -80008e6c: 0044a703 lw a4,4(s1) -80008e70: 04caa783 lw a5,76(s5) -80008e74: 01c12083 lw ra,28(sp) -80008e78: 00271713 slli a4,a4,0x2 -80008e7c: 00e787b3 add a5,a5,a4 -80008e80: 0007a703 lw a4,0(a5) -80008e84: 01452823 sw s4,16(a0) -80008e88: 01812403 lw s0,24(sp) -80008e8c: 00e4a023 sw a4,0(s1) -80008e90: 0097a023 sw s1,0(a5) -80008e94: 01012903 lw s2,16(sp) -80008e98: 01412483 lw s1,20(sp) -80008e9c: 00c12983 lw s3,12(sp) -80008ea0: 00812a03 lw s4,8(sp) -80008ea4: 00412a83 lw s5,4(sp) -80008ea8: 02010113 addi sp,sp,32 -80008eac: 00008067 ret -80008eb0: 0007a703 lw a4,0(a5) -80008eb4: 00478793 addi a5,a5,4 -80008eb8: 00480813 addi a6,a6,4 -80008ebc: fee82e23 sw a4,-4(a6) -80008ec0: fac7f6e3 bgeu a5,a2,80008e6c <__lshift+0xf0> -80008ec4: 0007a703 lw a4,0(a5) -80008ec8: 00478793 addi a5,a5,4 -80008ecc: 00480813 addi a6,a6,4 -80008ed0: fee82e23 sw a4,-4(a6) -80008ed4: fcc7eee3 bltu a5,a2,80008eb0 <__lshift+0x134> -80008ed8: f95ff06f j 80008e6c <__lshift+0xf0> -80008edc: 409607b3 sub a5,a2,s1 -80008ee0: feb78793 addi a5,a5,-21 -80008ee4: ffc7f793 andi a5,a5,-4 -80008ee8: 00478793 addi a5,a5,4 -80008eec: 00f80833 add a6,a6,a5 -80008ef0: 00d82023 sw a3,0(a6) -80008ef4: f6068ce3 beqz a3,80008e6c <__lshift+0xf0> -80008ef8: f71ff06f j 80008e68 <__lshift+0xec> +80008ca0 <__lshift>: +80008ca0: fe010113 addi sp,sp,-32 +80008ca4: 01412423 sw s4,8(sp) +80008ca8: 0105aa03 lw s4,16(a1) +80008cac: 0085a783 lw a5,8(a1) +80008cb0: 01312623 sw s3,12(sp) +80008cb4: 40565993 srai s3,a2,0x5 +80008cb8: 01498a33 add s4,s3,s4 +80008cbc: 00812c23 sw s0,24(sp) +80008cc0: 00912a23 sw s1,20(sp) +80008cc4: 01212823 sw s2,16(sp) +80008cc8: 01512223 sw s5,4(sp) +80008ccc: 00112e23 sw ra,28(sp) +80008cd0: 001a0913 addi s2,s4,1 +80008cd4: 00058493 mv s1,a1 +80008cd8: 00060413 mv s0,a2 +80008cdc: 0045a583 lw a1,4(a1) +80008ce0: 00050a93 mv s5,a0 +80008ce4: 0127d863 bge a5,s2,80008cf4 <__lshift+0x54> +80008ce8: 00179793 slli a5,a5,0x1 +80008cec: 00158593 addi a1,a1,1 +80008cf0: ff27cce3 blt a5,s2,80008ce8 <__lshift+0x48> +80008cf4: 000a8513 mv a0,s5 +80008cf8: 801ff0ef jal ra,800084f8 <_Balloc> +80008cfc: 01450813 addi a6,a0,20 +80008d00: 03305463 blez s3,80008d28 <__lshift+0x88> +80008d04: 00598993 addi s3,s3,5 +80008d08: 00299993 slli s3,s3,0x2 +80008d0c: 01350733 add a4,a0,s3 +80008d10: 00080793 mv a5,a6 +80008d14: 00478793 addi a5,a5,4 +80008d18: fe07ae23 sw zero,-4(a5) +80008d1c: fee79ce3 bne a5,a4,80008d14 <__lshift+0x74> +80008d20: fec98993 addi s3,s3,-20 +80008d24: 01380833 add a6,a6,s3 +80008d28: 0104a703 lw a4,16(s1) +80008d2c: 01448793 addi a5,s1,20 +80008d30: 01f47313 andi t1,s0,31 +80008d34: 00271613 slli a2,a4,0x2 +80008d38: 00c78633 add a2,a5,a2 +80008d3c: 08030c63 beqz t1,80008dd4 <__lshift+0x134> +80008d40: 02000593 li a1,32 +80008d44: 406585b3 sub a1,a1,t1 +80008d48: 00080893 mv a7,a6 +80008d4c: 00000693 li a3,0 +80008d50: 0007a703 lw a4,0(a5) +80008d54: 00488893 addi a7,a7,4 +80008d58: 00478793 addi a5,a5,4 +80008d5c: 00671733 sll a4,a4,t1 +80008d60: 00d76733 or a4,a4,a3 +80008d64: fee8ae23 sw a4,-4(a7) +80008d68: ffc7a703 lw a4,-4(a5) +80008d6c: 00b756b3 srl a3,a4,a1 +80008d70: fec7e0e3 bltu a5,a2,80008d50 <__lshift+0xb0> +80008d74: 01548713 addi a4,s1,21 +80008d78: 00400793 li a5,4 +80008d7c: 08e67263 bgeu a2,a4,80008e00 <__lshift+0x160> +80008d80: 00f80833 add a6,a6,a5 +80008d84: 00d82023 sw a3,0(a6) +80008d88: 00068463 beqz a3,80008d90 <__lshift+0xf0> +80008d8c: 00090a13 mv s4,s2 +80008d90: 0044a703 lw a4,4(s1) +80008d94: 04caa783 lw a5,76(s5) +80008d98: 01c12083 lw ra,28(sp) +80008d9c: 00271713 slli a4,a4,0x2 +80008da0: 00e787b3 add a5,a5,a4 +80008da4: 0007a703 lw a4,0(a5) +80008da8: 01452823 sw s4,16(a0) +80008dac: 01812403 lw s0,24(sp) +80008db0: 00e4a023 sw a4,0(s1) +80008db4: 0097a023 sw s1,0(a5) +80008db8: 01012903 lw s2,16(sp) +80008dbc: 01412483 lw s1,20(sp) +80008dc0: 00c12983 lw s3,12(sp) +80008dc4: 00812a03 lw s4,8(sp) +80008dc8: 00412a83 lw s5,4(sp) +80008dcc: 02010113 addi sp,sp,32 +80008dd0: 00008067 ret +80008dd4: 0007a703 lw a4,0(a5) +80008dd8: 00478793 addi a5,a5,4 +80008ddc: 00480813 addi a6,a6,4 +80008de0: fee82e23 sw a4,-4(a6) +80008de4: fac7f6e3 bgeu a5,a2,80008d90 <__lshift+0xf0> +80008de8: 0007a703 lw a4,0(a5) +80008dec: 00478793 addi a5,a5,4 +80008df0: 00480813 addi a6,a6,4 +80008df4: fee82e23 sw a4,-4(a6) +80008df8: fcc7eee3 bltu a5,a2,80008dd4 <__lshift+0x134> +80008dfc: f95ff06f j 80008d90 <__lshift+0xf0> +80008e00: 409607b3 sub a5,a2,s1 +80008e04: feb78793 addi a5,a5,-21 +80008e08: ffc7f793 andi a5,a5,-4 +80008e0c: 00478793 addi a5,a5,4 +80008e10: 00f80833 add a6,a6,a5 +80008e14: 00d82023 sw a3,0(a6) +80008e18: f6068ce3 beqz a3,80008d90 <__lshift+0xf0> +80008e1c: f71ff06f j 80008d8c <__lshift+0xec> -80008efc <__mcmp>: -80008efc: 01052703 lw a4,16(a0) -80008f00: 0105a783 lw a5,16(a1) -80008f04: 00050813 mv a6,a0 -80008f08: 40f70533 sub a0,a4,a5 -80008f0c: 04f71463 bne a4,a5,80008f54 <__mcmp+0x58> -80008f10: 00279793 slli a5,a5,0x2 -80008f14: 01480813 addi a6,a6,20 -80008f18: 01458593 addi a1,a1,20 -80008f1c: 00f80733 add a4,a6,a5 -80008f20: 00f587b3 add a5,a1,a5 -80008f24: 0080006f j 80008f2c <__mcmp+0x30> -80008f28: 02e87663 bgeu a6,a4,80008f54 <__mcmp+0x58> -80008f2c: ffc72683 lw a3,-4(a4) -80008f30: ffc7a603 lw a2,-4(a5) -80008f34: ffc70713 addi a4,a4,-4 -80008f38: ffc78793 addi a5,a5,-4 -80008f3c: fec686e3 beq a3,a2,80008f28 <__mcmp+0x2c> -80008f40: 00c6b6b3 sltu a3,a3,a2 -80008f44: 40d00533 neg a0,a3 -80008f48: ffe57513 andi a0,a0,-2 -80008f4c: 00150513 addi a0,a0,1 -80008f50: 00008067 ret -80008f54: 00008067 ret +80008e20 <__mcmp>: +80008e20: 01052703 lw a4,16(a0) +80008e24: 0105a783 lw a5,16(a1) +80008e28: 00050813 mv a6,a0 +80008e2c: 40f70533 sub a0,a4,a5 +80008e30: 04f71463 bne a4,a5,80008e78 <__mcmp+0x58> +80008e34: 00279793 slli a5,a5,0x2 +80008e38: 01480813 addi a6,a6,20 +80008e3c: 01458593 addi a1,a1,20 +80008e40: 00f80733 add a4,a6,a5 +80008e44: 00f587b3 add a5,a1,a5 +80008e48: 0080006f j 80008e50 <__mcmp+0x30> +80008e4c: 02e87663 bgeu a6,a4,80008e78 <__mcmp+0x58> +80008e50: ffc72683 lw a3,-4(a4) +80008e54: ffc7a603 lw a2,-4(a5) +80008e58: ffc70713 addi a4,a4,-4 +80008e5c: ffc78793 addi a5,a5,-4 +80008e60: fec686e3 beq a3,a2,80008e4c <__mcmp+0x2c> +80008e64: 00c6b6b3 sltu a3,a3,a2 +80008e68: 40d00533 neg a0,a3 +80008e6c: ffe57513 andi a0,a0,-2 +80008e70: 00150513 addi a0,a0,1 +80008e74: 00008067 ret +80008e78: 00008067 ret -80008f58 <__mdiff>: -80008f58: 0105a783 lw a5,16(a1) -80008f5c: 01062703 lw a4,16(a2) -80008f60: fe010113 addi sp,sp,-32 -80008f64: 00812c23 sw s0,24(sp) -80008f68: 00912a23 sw s1,20(sp) -80008f6c: 01212823 sw s2,16(sp) -80008f70: 01312623 sw s3,12(sp) -80008f74: 01412423 sw s4,8(sp) -80008f78: 00112e23 sw ra,28(sp) -80008f7c: 00058913 mv s2,a1 -80008f80: 00060993 mv s3,a2 -80008f84: 40e78a33 sub s4,a5,a4 -80008f88: 01458413 addi s0,a1,20 -80008f8c: 01460493 addi s1,a2,20 -80008f90: 04e79863 bne a5,a4,80008fe0 <__mdiff+0x88> -80008f94: 00271713 slli a4,a4,0x2 -80008f98: 00e407b3 add a5,s0,a4 -80008f9c: 00e48733 add a4,s1,a4 -80008fa0: 0080006f j 80008fa8 <__mdiff+0x50> -80008fa4: 1af47063 bgeu s0,a5,80009144 <__mdiff+0x1ec> -80008fa8: ffc7a803 lw a6,-4(a5) -80008fac: ffc72683 lw a3,-4(a4) -80008fb0: ffc78793 addi a5,a5,-4 -80008fb4: ffc70713 addi a4,a4,-4 -80008fb8: fed806e3 beq a6,a3,80008fa4 <__mdiff+0x4c> -80008fbc: 02d87663 bgeu a6,a3,80008fe8 <__mdiff+0x90> -80008fc0: 00040713 mv a4,s0 -80008fc4: 00090793 mv a5,s2 -80008fc8: 00048413 mv s0,s1 -80008fcc: 00098913 mv s2,s3 -80008fd0: 00070493 mv s1,a4 -80008fd4: 00078993 mv s3,a5 -80008fd8: 00100a13 li s4,1 -80008fdc: 00c0006f j 80008fe8 <__mdiff+0x90> -80008fe0: fe0a40e3 bltz s4,80008fc0 <__mdiff+0x68> -80008fe4: 00000a13 li s4,0 -80008fe8: 00492583 lw a1,4(s2) -80008fec: de8ff0ef jal ra,800085d4 <_Balloc> -80008ff0: 01092e03 lw t3,16(s2) -80008ff4: 0109af83 lw t6,16(s3) -80008ff8: 01450293 addi t0,a0,20 -80008ffc: 002e1e93 slli t4,t3,0x2 -80009000: 002f9f93 slli t6,t6,0x2 -80009004: 000108b7 lui a7,0x10 -80009008: 01452623 sw s4,12(a0) -8000900c: 01d40eb3 add t4,s0,t4 -80009010: 01f48fb3 add t6,s1,t6 -80009014: 00028f13 mv t5,t0 -80009018: 00048813 mv a6,s1 -8000901c: 00040313 mv t1,s0 -80009020: 00000793 li a5,0 -80009024: fff88893 addi a7,a7,-1 # ffff <_start-0x7fff0001> -80009028: 00032703 lw a4,0(t1) -8000902c: 00082583 lw a1,0(a6) -80009030: 004f0f13 addi t5,t5,4 -80009034: 011776b3 and a3,a4,a7 -80009038: 00f686b3 add a3,a3,a5 -8000903c: 0115f7b3 and a5,a1,a7 -80009040: 40f686b3 sub a3,a3,a5 -80009044: 0105d593 srli a1,a1,0x10 -80009048: 01075793 srli a5,a4,0x10 -8000904c: 40b787b3 sub a5,a5,a1 -80009050: 4106d713 srai a4,a3,0x10 -80009054: 00e787b3 add a5,a5,a4 -80009058: 01079713 slli a4,a5,0x10 -8000905c: 0116f6b3 and a3,a3,a7 -80009060: 00d766b3 or a3,a4,a3 -80009064: 00480813 addi a6,a6,4 -80009068: fedf2e23 sw a3,-4(t5) -8000906c: 00430313 addi t1,t1,4 -80009070: 4107d793 srai a5,a5,0x10 -80009074: fbf86ae3 bltu a6,t6,80009028 <__mdiff+0xd0> -80009078: fff4c613 not a2,s1 -8000907c: 00cf8633 add a2,t6,a2 -80009080: 00148493 addi s1,s1,1 -80009084: 00265613 srli a2,a2,0x2 -80009088: 00000713 li a4,0 -8000908c: 009fe463 bltu t6,s1,80009094 <__mdiff+0x13c> -80009090: 00261713 slli a4,a2,0x2 -80009094: 00e28733 add a4,t0,a4 -80009098: 00400593 li a1,4 -8000909c: 009fe663 bltu t6,s1,800090a8 <__mdiff+0x150> -800090a0: 00160613 addi a2,a2,1 -800090a4: 00261593 slli a1,a2,0x2 -800090a8: 00b40433 add s0,s0,a1 -800090ac: 00b282b3 add t0,t0,a1 -800090b0: 05d47e63 bgeu s0,t4,8000910c <__mdiff+0x1b4> -800090b4: 000108b7 lui a7,0x10 -800090b8: 00028813 mv a6,t0 -800090bc: 00040593 mv a1,s0 -800090c0: fff88893 addi a7,a7,-1 # ffff <_start-0x7fff0001> -800090c4: 0005a703 lw a4,0(a1) -800090c8: 00480813 addi a6,a6,4 -800090cc: 00458593 addi a1,a1,4 -800090d0: 01177633 and a2,a4,a7 -800090d4: 00f60633 add a2,a2,a5 -800090d8: 41065693 srai a3,a2,0x10 -800090dc: 01075793 srli a5,a4,0x10 -800090e0: 00d787b3 add a5,a5,a3 -800090e4: 01079693 slli a3,a5,0x10 -800090e8: 01167633 and a2,a2,a7 -800090ec: 00c6e6b3 or a3,a3,a2 -800090f0: fed82e23 sw a3,-4(a6) -800090f4: 4107d793 srai a5,a5,0x10 -800090f8: fdd5e6e3 bltu a1,t4,800090c4 <__mdiff+0x16c> -800090fc: fffe8713 addi a4,t4,-1 -80009100: 40870733 sub a4,a4,s0 -80009104: ffc77713 andi a4,a4,-4 -80009108: 00e28733 add a4,t0,a4 -8000910c: 00069a63 bnez a3,80009120 <__mdiff+0x1c8> -80009110: ffc72783 lw a5,-4(a4) -80009114: fffe0e13 addi t3,t3,-1 -80009118: ffc70713 addi a4,a4,-4 -8000911c: fe078ae3 beqz a5,80009110 <__mdiff+0x1b8> -80009120: 01c12083 lw ra,28(sp) -80009124: 01812403 lw s0,24(sp) -80009128: 01c52823 sw t3,16(a0) -8000912c: 01412483 lw s1,20(sp) -80009130: 01012903 lw s2,16(sp) -80009134: 00c12983 lw s3,12(sp) -80009138: 00812a03 lw s4,8(sp) -8000913c: 02010113 addi sp,sp,32 -80009140: 00008067 ret -80009144: 00000593 li a1,0 -80009148: c8cff0ef jal ra,800085d4 <_Balloc> -8000914c: 01c12083 lw ra,28(sp) -80009150: 01812403 lw s0,24(sp) -80009154: 00100793 li a5,1 -80009158: 00f52823 sw a5,16(a0) -8000915c: 00052a23 sw zero,20(a0) -80009160: 01412483 lw s1,20(sp) -80009164: 01012903 lw s2,16(sp) -80009168: 00c12983 lw s3,12(sp) -8000916c: 00812a03 lw s4,8(sp) -80009170: 02010113 addi sp,sp,32 -80009174: 00008067 ret +80008e7c <__mdiff>: +80008e7c: 0105a783 lw a5,16(a1) +80008e80: 01062703 lw a4,16(a2) +80008e84: fe010113 addi sp,sp,-32 +80008e88: 00812c23 sw s0,24(sp) +80008e8c: 00912a23 sw s1,20(sp) +80008e90: 01212823 sw s2,16(sp) +80008e94: 01312623 sw s3,12(sp) +80008e98: 01412423 sw s4,8(sp) +80008e9c: 00112e23 sw ra,28(sp) +80008ea0: 00058913 mv s2,a1 +80008ea4: 00060993 mv s3,a2 +80008ea8: 40e78a33 sub s4,a5,a4 +80008eac: 01458413 addi s0,a1,20 +80008eb0: 01460493 addi s1,a2,20 +80008eb4: 04e79863 bne a5,a4,80008f04 <__mdiff+0x88> +80008eb8: 00271713 slli a4,a4,0x2 +80008ebc: 00e407b3 add a5,s0,a4 +80008ec0: 00e48733 add a4,s1,a4 +80008ec4: 0080006f j 80008ecc <__mdiff+0x50> +80008ec8: 1af47063 bgeu s0,a5,80009068 <__mdiff+0x1ec> +80008ecc: ffc7a803 lw a6,-4(a5) +80008ed0: ffc72683 lw a3,-4(a4) +80008ed4: ffc78793 addi a5,a5,-4 +80008ed8: ffc70713 addi a4,a4,-4 +80008edc: fed806e3 beq a6,a3,80008ec8 <__mdiff+0x4c> +80008ee0: 02d87663 bgeu a6,a3,80008f0c <__mdiff+0x90> +80008ee4: 00040713 mv a4,s0 +80008ee8: 00090793 mv a5,s2 +80008eec: 00048413 mv s0,s1 +80008ef0: 00098913 mv s2,s3 +80008ef4: 00070493 mv s1,a4 +80008ef8: 00078993 mv s3,a5 +80008efc: 00100a13 li s4,1 +80008f00: 00c0006f j 80008f0c <__mdiff+0x90> +80008f04: fe0a40e3 bltz s4,80008ee4 <__mdiff+0x68> +80008f08: 00000a13 li s4,0 +80008f0c: 00492583 lw a1,4(s2) +80008f10: de8ff0ef jal ra,800084f8 <_Balloc> +80008f14: 01092e03 lw t3,16(s2) +80008f18: 0109af83 lw t6,16(s3) +80008f1c: 01450293 addi t0,a0,20 +80008f20: 002e1e93 slli t4,t3,0x2 +80008f24: 002f9f93 slli t6,t6,0x2 +80008f28: 000108b7 lui a7,0x10 +80008f2c: 01452623 sw s4,12(a0) +80008f30: 01d40eb3 add t4,s0,t4 +80008f34: 01f48fb3 add t6,s1,t6 +80008f38: 00028f13 mv t5,t0 +80008f3c: 00048813 mv a6,s1 +80008f40: 00040313 mv t1,s0 +80008f44: 00000793 li a5,0 +80008f48: fff88893 addi a7,a7,-1 # ffff <_start-0x7fff0001> +80008f4c: 00032703 lw a4,0(t1) +80008f50: 00082583 lw a1,0(a6) +80008f54: 004f0f13 addi t5,t5,4 +80008f58: 011776b3 and a3,a4,a7 +80008f5c: 00f686b3 add a3,a3,a5 +80008f60: 0115f7b3 and a5,a1,a7 +80008f64: 40f686b3 sub a3,a3,a5 +80008f68: 0105d593 srli a1,a1,0x10 +80008f6c: 01075793 srli a5,a4,0x10 +80008f70: 40b787b3 sub a5,a5,a1 +80008f74: 4106d713 srai a4,a3,0x10 +80008f78: 00e787b3 add a5,a5,a4 +80008f7c: 01079713 slli a4,a5,0x10 +80008f80: 0116f6b3 and a3,a3,a7 +80008f84: 00d766b3 or a3,a4,a3 +80008f88: 00480813 addi a6,a6,4 +80008f8c: fedf2e23 sw a3,-4(t5) +80008f90: 00430313 addi t1,t1,4 +80008f94: 4107d793 srai a5,a5,0x10 +80008f98: fbf86ae3 bltu a6,t6,80008f4c <__mdiff+0xd0> +80008f9c: fff4c613 not a2,s1 +80008fa0: 00cf8633 add a2,t6,a2 +80008fa4: 00148493 addi s1,s1,1 +80008fa8: 00265613 srli a2,a2,0x2 +80008fac: 00000713 li a4,0 +80008fb0: 009fe463 bltu t6,s1,80008fb8 <__mdiff+0x13c> +80008fb4: 00261713 slli a4,a2,0x2 +80008fb8: 00e28733 add a4,t0,a4 +80008fbc: 00400593 li a1,4 +80008fc0: 009fe663 bltu t6,s1,80008fcc <__mdiff+0x150> +80008fc4: 00160613 addi a2,a2,1 +80008fc8: 00261593 slli a1,a2,0x2 +80008fcc: 00b40433 add s0,s0,a1 +80008fd0: 00b282b3 add t0,t0,a1 +80008fd4: 05d47e63 bgeu s0,t4,80009030 <__mdiff+0x1b4> +80008fd8: 000108b7 lui a7,0x10 +80008fdc: 00028813 mv a6,t0 +80008fe0: 00040593 mv a1,s0 +80008fe4: fff88893 addi a7,a7,-1 # ffff <_start-0x7fff0001> +80008fe8: 0005a703 lw a4,0(a1) +80008fec: 00480813 addi a6,a6,4 +80008ff0: 00458593 addi a1,a1,4 +80008ff4: 01177633 and a2,a4,a7 +80008ff8: 00f60633 add a2,a2,a5 +80008ffc: 41065693 srai a3,a2,0x10 +80009000: 01075793 srli a5,a4,0x10 +80009004: 00d787b3 add a5,a5,a3 +80009008: 01079693 slli a3,a5,0x10 +8000900c: 01167633 and a2,a2,a7 +80009010: 00c6e6b3 or a3,a3,a2 +80009014: fed82e23 sw a3,-4(a6) +80009018: 4107d793 srai a5,a5,0x10 +8000901c: fdd5e6e3 bltu a1,t4,80008fe8 <__mdiff+0x16c> +80009020: fffe8713 addi a4,t4,-1 +80009024: 40870733 sub a4,a4,s0 +80009028: ffc77713 andi a4,a4,-4 +8000902c: 00e28733 add a4,t0,a4 +80009030: 00069a63 bnez a3,80009044 <__mdiff+0x1c8> +80009034: ffc72783 lw a5,-4(a4) +80009038: fffe0e13 addi t3,t3,-1 +8000903c: ffc70713 addi a4,a4,-4 +80009040: fe078ae3 beqz a5,80009034 <__mdiff+0x1b8> +80009044: 01c12083 lw ra,28(sp) +80009048: 01812403 lw s0,24(sp) +8000904c: 01c52823 sw t3,16(a0) +80009050: 01412483 lw s1,20(sp) +80009054: 01012903 lw s2,16(sp) +80009058: 00c12983 lw s3,12(sp) +8000905c: 00812a03 lw s4,8(sp) +80009060: 02010113 addi sp,sp,32 +80009064: 00008067 ret +80009068: 00000593 li a1,0 +8000906c: c8cff0ef jal ra,800084f8 <_Balloc> +80009070: 01c12083 lw ra,28(sp) +80009074: 01812403 lw s0,24(sp) +80009078: 00100793 li a5,1 +8000907c: 00f52823 sw a5,16(a0) +80009080: 00052a23 sw zero,20(a0) +80009084: 01412483 lw s1,20(sp) +80009088: 01012903 lw s2,16(sp) +8000908c: 00c12983 lw s3,12(sp) +80009090: 00812a03 lw s4,8(sp) +80009094: 02010113 addi sp,sp,32 +80009098: 00008067 ret -80009178 <__ulp>: -80009178: 7ff007b7 lui a5,0x7ff00 -8000917c: 00b7f5b3 and a1,a5,a1 -80009180: fcc007b7 lui a5,0xfcc00 -80009184: 00f585b3 add a1,a1,a5 -80009188: 00b05863 blez a1,80009198 <__ulp+0x20> -8000918c: 00000793 li a5,0 -80009190: 00078513 mv a0,a5 -80009194: 00008067 ret -80009198: 40b005b3 neg a1,a1 -8000919c: 4145d593 srai a1,a1,0x14 -800091a0: 01300793 li a5,19 -800091a4: 00b7c863 blt a5,a1,800091b4 <__ulp+0x3c> -800091a8: 000807b7 lui a5,0x80 -800091ac: 40b7d5b3 sra a1,a5,a1 -800091b0: fddff06f j 8000918c <__ulp+0x14> -800091b4: fec58713 addi a4,a1,-20 -800091b8: 01e00693 li a3,30 -800091bc: 00000593 li a1,0 -800091c0: 00100793 li a5,1 -800091c4: fce6c6e3 blt a3,a4,80009190 <__ulp+0x18> -800091c8: 800007b7 lui a5,0x80000 -800091cc: 00e7d7b3 srl a5,a5,a4 -800091d0: 00078513 mv a0,a5 -800091d4: 00008067 ret +8000909c <__ulp>: +8000909c: 7ff007b7 lui a5,0x7ff00 +800090a0: 00b7f5b3 and a1,a5,a1 +800090a4: fcc007b7 lui a5,0xfcc00 +800090a8: 00f585b3 add a1,a1,a5 +800090ac: 00b05863 blez a1,800090bc <__ulp+0x20> +800090b0: 00000793 li a5,0 +800090b4: 00078513 mv a0,a5 +800090b8: 00008067 ret +800090bc: 40b005b3 neg a1,a1 +800090c0: 4145d593 srai a1,a1,0x14 +800090c4: 01300793 li a5,19 +800090c8: 00b7c863 blt a5,a1,800090d8 <__ulp+0x3c> +800090cc: 000807b7 lui a5,0x80 +800090d0: 40b7d5b3 sra a1,a5,a1 +800090d4: fddff06f j 800090b0 <__ulp+0x14> +800090d8: fec58713 addi a4,a1,-20 +800090dc: 01e00693 li a3,30 +800090e0: 00000593 li a1,0 +800090e4: 00100793 li a5,1 +800090e8: fce6c6e3 blt a3,a4,800090b4 <__ulp+0x18> +800090ec: 800007b7 lui a5,0x80000 +800090f0: 00e7d7b3 srl a5,a5,a4 +800090f4: 00078513 mv a0,a5 +800090f8: 00008067 ret -800091d8 <__b2d>: -800091d8: fe010113 addi sp,sp,-32 -800091dc: 00912a23 sw s1,20(sp) -800091e0: 01052483 lw s1,16(a0) -800091e4: 00812c23 sw s0,24(sp) -800091e8: 01450413 addi s0,a0,20 -800091ec: 00249493 slli s1,s1,0x2 -800091f0: 009404b3 add s1,s0,s1 -800091f4: 01212823 sw s2,16(sp) -800091f8: ffc4a903 lw s2,-4(s1) -800091fc: 01312623 sw s3,12(sp) -80009200: 01412423 sw s4,8(sp) -80009204: 00090513 mv a0,s2 -80009208: 00058993 mv s3,a1 -8000920c: 00112e23 sw ra,28(sp) -80009210: eb8ff0ef jal ra,800088c8 <__hi0bits> -80009214: 02000713 li a4,32 -80009218: 40a707b3 sub a5,a4,a0 -8000921c: 00f9a023 sw a5,0(s3) -80009220: 00a00793 li a5,10 -80009224: ffc48a13 addi s4,s1,-4 -80009228: 08a7d063 bge a5,a0,800092a8 <__b2d+0xd0> -8000922c: ff550513 addi a0,a0,-11 -80009230: 05447063 bgeu s0,s4,80009270 <__b2d+0x98> -80009234: ff84a783 lw a5,-8(s1) -80009238: 04050063 beqz a0,80009278 <__b2d+0xa0> -8000923c: 40a706b3 sub a3,a4,a0 -80009240: 00d7d733 srl a4,a5,a3 -80009244: 00a91933 sll s2,s2,a0 -80009248: 00e96933 or s2,s2,a4 -8000924c: ff848613 addi a2,s1,-8 -80009250: 3ff00737 lui a4,0x3ff00 -80009254: 00e96733 or a4,s2,a4 -80009258: 00a797b3 sll a5,a5,a0 -8000925c: 02c47263 bgeu s0,a2,80009280 <__b2d+0xa8> -80009260: ff44a603 lw a2,-12(s1) -80009264: 00d656b3 srl a3,a2,a3 -80009268: 00d7e7b3 or a5,a5,a3 -8000926c: 0140006f j 80009280 <__b2d+0xa8> -80009270: 00000793 li a5,0 -80009274: 06051463 bnez a0,800092dc <__b2d+0x104> -80009278: 3ff00737 lui a4,0x3ff00 -8000927c: 00e96733 or a4,s2,a4 -80009280: 01c12083 lw ra,28(sp) -80009284: 01812403 lw s0,24(sp) -80009288: 01412483 lw s1,20(sp) -8000928c: 01012903 lw s2,16(sp) -80009290: 00c12983 lw s3,12(sp) -80009294: 00812a03 lw s4,8(sp) -80009298: 00078513 mv a0,a5 -8000929c: 00070593 mv a1,a4 -800092a0: 02010113 addi sp,sp,32 -800092a4: 00008067 ret -800092a8: 00b00693 li a3,11 -800092ac: 40a686b3 sub a3,a3,a0 -800092b0: 3ff007b7 lui a5,0x3ff00 -800092b4: 00d95733 srl a4,s2,a3 -800092b8: 00f76733 or a4,a4,a5 -800092bc: 00000793 li a5,0 -800092c0: 01447663 bgeu s0,s4,800092cc <__b2d+0xf4> -800092c4: ff84a783 lw a5,-8(s1) -800092c8: 00d7d7b3 srl a5,a5,a3 -800092cc: 01550513 addi a0,a0,21 -800092d0: 00a91533 sll a0,s2,a0 -800092d4: 00f567b3 or a5,a0,a5 -800092d8: fa9ff06f j 80009280 <__b2d+0xa8> -800092dc: 00a91533 sll a0,s2,a0 -800092e0: 3ff00737 lui a4,0x3ff00 -800092e4: 00e56733 or a4,a0,a4 -800092e8: 00000793 li a5,0 -800092ec: f95ff06f j 80009280 <__b2d+0xa8> +800090fc <__b2d>: +800090fc: fe010113 addi sp,sp,-32 +80009100: 00912a23 sw s1,20(sp) +80009104: 01052483 lw s1,16(a0) +80009108: 00812c23 sw s0,24(sp) +8000910c: 01450413 addi s0,a0,20 +80009110: 00249493 slli s1,s1,0x2 +80009114: 009404b3 add s1,s0,s1 +80009118: 01212823 sw s2,16(sp) +8000911c: ffc4a903 lw s2,-4(s1) +80009120: 01312623 sw s3,12(sp) +80009124: 01412423 sw s4,8(sp) +80009128: 00090513 mv a0,s2 +8000912c: 00058993 mv s3,a1 +80009130: 00112e23 sw ra,28(sp) +80009134: eb8ff0ef jal ra,800087ec <__hi0bits> +80009138: 02000713 li a4,32 +8000913c: 40a707b3 sub a5,a4,a0 +80009140: 00f9a023 sw a5,0(s3) +80009144: 00a00793 li a5,10 +80009148: ffc48a13 addi s4,s1,-4 +8000914c: 08a7d063 bge a5,a0,800091cc <__b2d+0xd0> +80009150: ff550513 addi a0,a0,-11 +80009154: 05447063 bgeu s0,s4,80009194 <__b2d+0x98> +80009158: ff84a783 lw a5,-8(s1) +8000915c: 04050063 beqz a0,8000919c <__b2d+0xa0> +80009160: 40a706b3 sub a3,a4,a0 +80009164: 00d7d733 srl a4,a5,a3 +80009168: 00a91933 sll s2,s2,a0 +8000916c: 00e96933 or s2,s2,a4 +80009170: ff848613 addi a2,s1,-8 +80009174: 3ff00737 lui a4,0x3ff00 +80009178: 00e96733 or a4,s2,a4 +8000917c: 00a797b3 sll a5,a5,a0 +80009180: 02c47263 bgeu s0,a2,800091a4 <__b2d+0xa8> +80009184: ff44a603 lw a2,-12(s1) +80009188: 00d656b3 srl a3,a2,a3 +8000918c: 00d7e7b3 or a5,a5,a3 +80009190: 0140006f j 800091a4 <__b2d+0xa8> +80009194: 00000793 li a5,0 +80009198: 06051463 bnez a0,80009200 <__b2d+0x104> +8000919c: 3ff00737 lui a4,0x3ff00 +800091a0: 00e96733 or a4,s2,a4 +800091a4: 01c12083 lw ra,28(sp) +800091a8: 01812403 lw s0,24(sp) +800091ac: 01412483 lw s1,20(sp) +800091b0: 01012903 lw s2,16(sp) +800091b4: 00c12983 lw s3,12(sp) +800091b8: 00812a03 lw s4,8(sp) +800091bc: 00078513 mv a0,a5 +800091c0: 00070593 mv a1,a4 +800091c4: 02010113 addi sp,sp,32 +800091c8: 00008067 ret +800091cc: 00b00693 li a3,11 +800091d0: 40a686b3 sub a3,a3,a0 +800091d4: 3ff007b7 lui a5,0x3ff00 +800091d8: 00d95733 srl a4,s2,a3 +800091dc: 00f76733 or a4,a4,a5 +800091e0: 00000793 li a5,0 +800091e4: 01447663 bgeu s0,s4,800091f0 <__b2d+0xf4> +800091e8: ff84a783 lw a5,-8(s1) +800091ec: 00d7d7b3 srl a5,a5,a3 +800091f0: 01550513 addi a0,a0,21 +800091f4: 00a91533 sll a0,s2,a0 +800091f8: 00f567b3 or a5,a0,a5 +800091fc: fa9ff06f j 800091a4 <__b2d+0xa8> +80009200: 00a91533 sll a0,s2,a0 +80009204: 3ff00737 lui a4,0x3ff00 +80009208: 00e56733 or a4,a0,a4 +8000920c: 00000793 li a5,0 +80009210: f95ff06f j 800091a4 <__b2d+0xa8> -800092f0 <__d2b>: -800092f0: fd010113 addi sp,sp,-48 -800092f4: 01512a23 sw s5,20(sp) -800092f8: 00058a93 mv s5,a1 -800092fc: 00100593 li a1,1 -80009300: 02812423 sw s0,40(sp) -80009304: 02912223 sw s1,36(sp) -80009308: 03212023 sw s2,32(sp) -8000930c: 00060493 mv s1,a2 -80009310: 01312e23 sw s3,28(sp) -80009314: 01412c23 sw s4,24(sp) -80009318: 00068993 mv s3,a3 -8000931c: 00070913 mv s2,a4 -80009320: 02112623 sw ra,44(sp) -80009324: ab0ff0ef jal ra,800085d4 <_Balloc> -80009328: 0144d713 srli a4,s1,0x14 -8000932c: 00100637 lui a2,0x100 -80009330: fff60793 addi a5,a2,-1 # fffff <_start-0x7ff00001> -80009334: 01571693 slli a3,a4,0x15 -80009338: 00050413 mv s0,a0 -8000933c: 0097f7b3 and a5,a5,s1 -80009340: 7ff77a13 andi s4,a4,2047 -80009344: 00068463 beqz a3,8000934c <__d2b+0x5c> -80009348: 00c7e7b3 or a5,a5,a2 -8000934c: 00f12623 sw a5,12(sp) -80009350: 060a8c63 beqz s5,800093c8 <__d2b+0xd8> -80009354: 00810513 addi a0,sp,8 -80009358: 01512423 sw s5,8(sp) -8000935c: de0ff0ef jal ra,8000893c <__lo0bits> -80009360: 00c12703 lw a4,12(sp) -80009364: 00050793 mv a5,a0 -80009368: 0a051663 bnez a0,80009414 <__d2b+0x124> -8000936c: 00812683 lw a3,8(sp) -80009370: 00d42a23 sw a3,20(s0) -80009374: 00e034b3 snez s1,a4 -80009378: 00148493 addi s1,s1,1 -8000937c: 00e42c23 sw a4,24(s0) -80009380: 00942823 sw s1,16(s0) -80009384: 060a0463 beqz s4,800093ec <__d2b+0xfc> -80009388: bcda0a13 addi s4,s4,-1075 -8000938c: 00fa0a33 add s4,s4,a5 -80009390: 03500513 li a0,53 -80009394: 0149a023 sw s4,0(s3) -80009398: 40f507b3 sub a5,a0,a5 -8000939c: 00f92023 sw a5,0(s2) -800093a0: 02c12083 lw ra,44(sp) -800093a4: 00040513 mv a0,s0 -800093a8: 02812403 lw s0,40(sp) -800093ac: 02412483 lw s1,36(sp) -800093b0: 02012903 lw s2,32(sp) -800093b4: 01c12983 lw s3,28(sp) -800093b8: 01812a03 lw s4,24(sp) -800093bc: 01412a83 lw s5,20(sp) -800093c0: 03010113 addi sp,sp,48 -800093c4: 00008067 ret -800093c8: 00c10513 addi a0,sp,12 -800093cc: d70ff0ef jal ra,8000893c <__lo0bits> -800093d0: 00100793 li a5,1 -800093d4: 00f42823 sw a5,16(s0) -800093d8: 00c12783 lw a5,12(sp) -800093dc: 00100493 li s1,1 -800093e0: 00f42a23 sw a5,20(s0) -800093e4: 02050793 addi a5,a0,32 -800093e8: fa0a10e3 bnez s4,80009388 <__d2b+0x98> -800093ec: 00249713 slli a4,s1,0x2 -800093f0: 00e40733 add a4,s0,a4 -800093f4: 01072503 lw a0,16(a4) # 3ff00010 <_start-0x400ffff0> -800093f8: bce78793 addi a5,a5,-1074 # 3feffbce <_start-0x40100432> -800093fc: 00f9a023 sw a5,0(s3) -80009400: cc8ff0ef jal ra,800088c8 <__hi0bits> -80009404: 00549493 slli s1,s1,0x5 -80009408: 40a484b3 sub s1,s1,a0 -8000940c: 00992023 sw s1,0(s2) -80009410: f91ff06f j 800093a0 <__d2b+0xb0> -80009414: 00812603 lw a2,8(sp) -80009418: 02000693 li a3,32 -8000941c: 40a686b3 sub a3,a3,a0 -80009420: 00d716b3 sll a3,a4,a3 -80009424: 00c6e6b3 or a3,a3,a2 -80009428: 00a75733 srl a4,a4,a0 -8000942c: 00d42a23 sw a3,20(s0) -80009430: 00e12623 sw a4,12(sp) -80009434: f41ff06f j 80009374 <__d2b+0x84> +80009214 <__d2b>: +80009214: fd010113 addi sp,sp,-48 +80009218: 01512a23 sw s5,20(sp) +8000921c: 00058a93 mv s5,a1 +80009220: 00100593 li a1,1 +80009224: 02812423 sw s0,40(sp) +80009228: 02912223 sw s1,36(sp) +8000922c: 03212023 sw s2,32(sp) +80009230: 00060493 mv s1,a2 +80009234: 01312e23 sw s3,28(sp) +80009238: 01412c23 sw s4,24(sp) +8000923c: 00068993 mv s3,a3 +80009240: 00070913 mv s2,a4 +80009244: 02112623 sw ra,44(sp) +80009248: ab0ff0ef jal ra,800084f8 <_Balloc> +8000924c: 0144d713 srli a4,s1,0x14 +80009250: 00100637 lui a2,0x100 +80009254: fff60793 addi a5,a2,-1 # fffff <_start-0x7ff00001> +80009258: 01571693 slli a3,a4,0x15 +8000925c: 00050413 mv s0,a0 +80009260: 0097f7b3 and a5,a5,s1 +80009264: 7ff77a13 andi s4,a4,2047 +80009268: 00068463 beqz a3,80009270 <__d2b+0x5c> +8000926c: 00c7e7b3 or a5,a5,a2 +80009270: 00f12623 sw a5,12(sp) +80009274: 060a8c63 beqz s5,800092ec <__d2b+0xd8> +80009278: 00810513 addi a0,sp,8 +8000927c: 01512423 sw s5,8(sp) +80009280: de0ff0ef jal ra,80008860 <__lo0bits> +80009284: 00c12703 lw a4,12(sp) +80009288: 00050793 mv a5,a0 +8000928c: 0a051663 bnez a0,80009338 <__d2b+0x124> +80009290: 00812683 lw a3,8(sp) +80009294: 00d42a23 sw a3,20(s0) +80009298: 00e034b3 snez s1,a4 +8000929c: 00148493 addi s1,s1,1 +800092a0: 00e42c23 sw a4,24(s0) +800092a4: 00942823 sw s1,16(s0) +800092a8: 060a0463 beqz s4,80009310 <__d2b+0xfc> +800092ac: bcda0a13 addi s4,s4,-1075 +800092b0: 00fa0a33 add s4,s4,a5 +800092b4: 03500513 li a0,53 +800092b8: 0149a023 sw s4,0(s3) +800092bc: 40f507b3 sub a5,a0,a5 +800092c0: 00f92023 sw a5,0(s2) +800092c4: 02c12083 lw ra,44(sp) +800092c8: 00040513 mv a0,s0 +800092cc: 02812403 lw s0,40(sp) +800092d0: 02412483 lw s1,36(sp) +800092d4: 02012903 lw s2,32(sp) +800092d8: 01c12983 lw s3,28(sp) +800092dc: 01812a03 lw s4,24(sp) +800092e0: 01412a83 lw s5,20(sp) +800092e4: 03010113 addi sp,sp,48 +800092e8: 00008067 ret +800092ec: 00c10513 addi a0,sp,12 +800092f0: d70ff0ef jal ra,80008860 <__lo0bits> +800092f4: 00100793 li a5,1 +800092f8: 00f42823 sw a5,16(s0) +800092fc: 00c12783 lw a5,12(sp) +80009300: 00100493 li s1,1 +80009304: 00f42a23 sw a5,20(s0) +80009308: 02050793 addi a5,a0,32 +8000930c: fa0a10e3 bnez s4,800092ac <__d2b+0x98> +80009310: 00249713 slli a4,s1,0x2 +80009314: 00e40733 add a4,s0,a4 +80009318: 01072503 lw a0,16(a4) # 3ff00010 <_start-0x400ffff0> +8000931c: bce78793 addi a5,a5,-1074 # 3feffbce <_start-0x40100432> +80009320: 00f9a023 sw a5,0(s3) +80009324: cc8ff0ef jal ra,800087ec <__hi0bits> +80009328: 00549493 slli s1,s1,0x5 +8000932c: 40a484b3 sub s1,s1,a0 +80009330: 00992023 sw s1,0(s2) +80009334: f91ff06f j 800092c4 <__d2b+0xb0> +80009338: 00812603 lw a2,8(sp) +8000933c: 02000693 li a3,32 +80009340: 40a686b3 sub a3,a3,a0 +80009344: 00d716b3 sll a3,a4,a3 +80009348: 00c6e6b3 or a3,a3,a2 +8000934c: 00a75733 srl a4,a4,a0 +80009350: 00d42a23 sw a3,20(s0) +80009354: 00e12623 sw a4,12(sp) +80009358: f41ff06f j 80009298 <__d2b+0x84> -80009438 <__ratio>: -80009438: fd010113 addi sp,sp,-48 -8000943c: 03212023 sw s2,32(sp) -80009440: 00058913 mv s2,a1 -80009444: 00810593 addi a1,sp,8 -80009448: 02112623 sw ra,44(sp) -8000944c: 02812423 sw s0,40(sp) -80009450: 02912223 sw s1,36(sp) -80009454: 01312e23 sw s3,28(sp) -80009458: 00050993 mv s3,a0 -8000945c: d7dff0ef jal ra,800091d8 <__b2d> -80009460: 00050493 mv s1,a0 -80009464: 00058413 mv s0,a1 -80009468: 00090513 mv a0,s2 -8000946c: 00c10593 addi a1,sp,12 -80009470: d69ff0ef jal ra,800091d8 <__b2d> -80009474: 01092783 lw a5,16(s2) -80009478: 0109a703 lw a4,16(s3) -8000947c: 00c12683 lw a3,12(sp) -80009480: 40f70733 sub a4,a4,a5 -80009484: 00812783 lw a5,8(sp) -80009488: 00571713 slli a4,a4,0x5 -8000948c: 40d787b3 sub a5,a5,a3 -80009490: 00f707b3 add a5,a4,a5 -80009494: 00050693 mv a3,a0 -80009498: 02f05e63 blez a5,800094d4 <__ratio+0x9c> -8000949c: 01479793 slli a5,a5,0x14 -800094a0: 00878433 add s0,a5,s0 -800094a4: 00068613 mv a2,a3 -800094a8: 00048513 mv a0,s1 -800094ac: 00058693 mv a3,a1 -800094b0: 00040593 mv a1,s0 -800094b4: 790070ef jal ra,80010c44 <__divdf3> -800094b8: 02c12083 lw ra,44(sp) -800094bc: 02812403 lw s0,40(sp) -800094c0: 02412483 lw s1,36(sp) -800094c4: 02012903 lw s2,32(sp) -800094c8: 01c12983 lw s3,28(sp) -800094cc: 03010113 addi sp,sp,48 -800094d0: 00008067 ret -800094d4: 01479713 slli a4,a5,0x14 -800094d8: 40e585b3 sub a1,a1,a4 -800094dc: fc9ff06f j 800094a4 <__ratio+0x6c> +8000935c <__ratio>: +8000935c: fd010113 addi sp,sp,-48 +80009360: 03212023 sw s2,32(sp) +80009364: 00058913 mv s2,a1 +80009368: 00810593 addi a1,sp,8 +8000936c: 02112623 sw ra,44(sp) +80009370: 02812423 sw s0,40(sp) +80009374: 02912223 sw s1,36(sp) +80009378: 01312e23 sw s3,28(sp) +8000937c: 00050993 mv s3,a0 +80009380: d7dff0ef jal ra,800090fc <__b2d> +80009384: 00050493 mv s1,a0 +80009388: 00058413 mv s0,a1 +8000938c: 00090513 mv a0,s2 +80009390: 00c10593 addi a1,sp,12 +80009394: d69ff0ef jal ra,800090fc <__b2d> +80009398: 01092783 lw a5,16(s2) +8000939c: 0109a703 lw a4,16(s3) +800093a0: 00c12683 lw a3,12(sp) +800093a4: 40f70733 sub a4,a4,a5 +800093a8: 00812783 lw a5,8(sp) +800093ac: 00571713 slli a4,a4,0x5 +800093b0: 40d787b3 sub a5,a5,a3 +800093b4: 00f707b3 add a5,a4,a5 +800093b8: 00050693 mv a3,a0 +800093bc: 02f05e63 blez a5,800093f8 <__ratio+0x9c> +800093c0: 01479793 slli a5,a5,0x14 +800093c4: 00878433 add s0,a5,s0 +800093c8: 00068613 mv a2,a3 +800093cc: 00048513 mv a0,s1 +800093d0: 00058693 mv a3,a1 +800093d4: 00040593 mv a1,s0 +800093d8: 131070ef jal ra,80010d08 <__divdf3> +800093dc: 02c12083 lw ra,44(sp) +800093e0: 02812403 lw s0,40(sp) +800093e4: 02412483 lw s1,36(sp) +800093e8: 02012903 lw s2,32(sp) +800093ec: 01c12983 lw s3,28(sp) +800093f0: 03010113 addi sp,sp,48 +800093f4: 00008067 ret +800093f8: 01479713 slli a4,a5,0x14 +800093fc: 40e585b3 sub a1,a1,a4 +80009400: fc9ff06f j 800093c8 <__ratio+0x6c> -800094e0 <_mprec_log10>: -800094e0: ff010113 addi sp,sp,-16 -800094e4: 01212023 sw s2,0(sp) -800094e8: 00112623 sw ra,12(sp) -800094ec: 00812423 sw s0,8(sp) -800094f0: 00912223 sw s1,4(sp) -800094f4: 01700793 li a5,23 -800094f8: 00050913 mv s2,a0 -800094fc: 04a7d663 bge a5,a0,80009548 <_mprec_log10+0x68> -80009500: 3381a783 lw a5,824(gp) # 80016b40 <__SDATA_BEGIN__> -80009504: 33c1a583 lw a1,828(gp) # 80016b44 <__SDATA_BEGIN__+0x4> -80009508: 3401a403 lw s0,832(gp) # 80016b48 <__SDATA_BEGIN__+0x8> -8000950c: 3441a483 lw s1,836(gp) # 80016b4c <__SDATA_BEGIN__+0xc> -80009510: 00078513 mv a0,a5 -80009514: 00040613 mv a2,s0 -80009518: 00048693 mv a3,s1 -8000951c: 609070ef jal ra,80011324 <__muldf3> -80009520: fff90913 addi s2,s2,-1 -80009524: 00050793 mv a5,a0 -80009528: fe0914e3 bnez s2,80009510 <_mprec_log10+0x30> -8000952c: 00c12083 lw ra,12(sp) -80009530: 00812403 lw s0,8(sp) -80009534: 00412483 lw s1,4(sp) -80009538: 00012903 lw s2,0(sp) -8000953c: 00078513 mv a0,a5 -80009540: 01010113 addi sp,sp,16 -80009544: 00008067 ret -80009548: 800157b7 lui a5,0x80015 -8000954c: 00351913 slli s2,a0,0x3 -80009550: 07878793 addi a5,a5,120 # 80015078 <__BSS_END__+0xffffe448> -80009554: 01278933 add s2,a5,s2 -80009558: 01092783 lw a5,16(s2) -8000955c: 00c12083 lw ra,12(sp) -80009560: 00812403 lw s0,8(sp) -80009564: 01492583 lw a1,20(s2) -80009568: 00412483 lw s1,4(sp) -8000956c: 00012903 lw s2,0(sp) -80009570: 00078513 mv a0,a5 -80009574: 01010113 addi sp,sp,16 -80009578: 00008067 ret +80009404 <_mprec_log10>: +80009404: ff010113 addi sp,sp,-16 +80009408: 01212023 sw s2,0(sp) +8000940c: 00112623 sw ra,12(sp) +80009410: 00812423 sw s0,8(sp) +80009414: 00912223 sw s1,4(sp) +80009418: 01700793 li a5,23 +8000941c: 00050913 mv s2,a0 +80009420: 04a7d663 bge a5,a0,8000946c <_mprec_log10+0x68> +80009424: 3381a783 lw a5,824(gp) # 80016b40 <__SDATA_BEGIN__> +80009428: 33c1a583 lw a1,828(gp) # 80016b44 <__SDATA_BEGIN__+0x4> +8000942c: 3401a403 lw s0,832(gp) # 80016b48 <__SDATA_BEGIN__+0x8> +80009430: 3441a483 lw s1,836(gp) # 80016b4c <__SDATA_BEGIN__+0xc> +80009434: 00078513 mv a0,a5 +80009438: 00040613 mv a2,s0 +8000943c: 00048693 mv a3,s1 +80009440: 7a9070ef jal ra,800113e8 <__muldf3> +80009444: fff90913 addi s2,s2,-1 +80009448: 00050793 mv a5,a0 +8000944c: fe0914e3 bnez s2,80009434 <_mprec_log10+0x30> +80009450: 00c12083 lw ra,12(sp) +80009454: 00812403 lw s0,8(sp) +80009458: 00412483 lw s1,4(sp) +8000945c: 00012903 lw s2,0(sp) +80009460: 00078513 mv a0,a5 +80009464: 01010113 addi sp,sp,16 +80009468: 00008067 ret +8000946c: 800157b7 lui a5,0x80015 +80009470: 00351913 slli s2,a0,0x3 +80009474: 0b878793 addi a5,a5,184 # 800150b8 <__BSS_END__+0xffffe47c> +80009478: 01278933 add s2,a5,s2 +8000947c: 01092783 lw a5,16(s2) +80009480: 00c12083 lw ra,12(sp) +80009484: 00812403 lw s0,8(sp) +80009488: 01492583 lw a1,20(s2) +8000948c: 00412483 lw s1,4(sp) +80009490: 00012903 lw s2,0(sp) +80009494: 00078513 mv a0,a5 +80009498: 01010113 addi sp,sp,16 +8000949c: 00008067 ret -8000957c <__copybits>: -8000957c: 01062683 lw a3,16(a2) -80009580: fff58593 addi a1,a1,-1 -80009584: 4055d593 srai a1,a1,0x5 -80009588: 00158593 addi a1,a1,1 -8000958c: 01460793 addi a5,a2,20 -80009590: 00269693 slli a3,a3,0x2 -80009594: 00259593 slli a1,a1,0x2 -80009598: 00d786b3 add a3,a5,a3 -8000959c: 00b505b3 add a1,a0,a1 -800095a0: 02d7f863 bgeu a5,a3,800095d0 <__copybits+0x54> -800095a4: 00050713 mv a4,a0 -800095a8: 0007a803 lw a6,0(a5) -800095ac: 00478793 addi a5,a5,4 -800095b0: 00470713 addi a4,a4,4 -800095b4: ff072e23 sw a6,-4(a4) -800095b8: fed7e8e3 bltu a5,a3,800095a8 <__copybits+0x2c> -800095bc: 40c687b3 sub a5,a3,a2 -800095c0: feb78793 addi a5,a5,-21 -800095c4: ffc7f793 andi a5,a5,-4 -800095c8: 00478793 addi a5,a5,4 -800095cc: 00f50533 add a0,a0,a5 -800095d0: 00b57863 bgeu a0,a1,800095e0 <__copybits+0x64> -800095d4: 00450513 addi a0,a0,4 -800095d8: fe052e23 sw zero,-4(a0) -800095dc: feb56ce3 bltu a0,a1,800095d4 <__copybits+0x58> -800095e0: 00008067 ret +800094a0 <__copybits>: +800094a0: 01062683 lw a3,16(a2) +800094a4: fff58593 addi a1,a1,-1 +800094a8: 4055d593 srai a1,a1,0x5 +800094ac: 00158593 addi a1,a1,1 +800094b0: 01460793 addi a5,a2,20 +800094b4: 00269693 slli a3,a3,0x2 +800094b8: 00259593 slli a1,a1,0x2 +800094bc: 00d786b3 add a3,a5,a3 +800094c0: 00b505b3 add a1,a0,a1 +800094c4: 02d7f863 bgeu a5,a3,800094f4 <__copybits+0x54> +800094c8: 00050713 mv a4,a0 +800094cc: 0007a803 lw a6,0(a5) +800094d0: 00478793 addi a5,a5,4 +800094d4: 00470713 addi a4,a4,4 +800094d8: ff072e23 sw a6,-4(a4) +800094dc: fed7e8e3 bltu a5,a3,800094cc <__copybits+0x2c> +800094e0: 40c687b3 sub a5,a3,a2 +800094e4: feb78793 addi a5,a5,-21 +800094e8: ffc7f793 andi a5,a5,-4 +800094ec: 00478793 addi a5,a5,4 +800094f0: 00f50533 add a0,a0,a5 +800094f4: 00b57863 bgeu a0,a1,80009504 <__copybits+0x64> +800094f8: 00450513 addi a0,a0,4 +800094fc: fe052e23 sw zero,-4(a0) +80009500: feb56ce3 bltu a0,a1,800094f8 <__copybits+0x58> +80009504: 00008067 ret -800095e4 <__any_on>: -800095e4: 01052703 lw a4,16(a0) -800095e8: 4055d613 srai a2,a1,0x5 -800095ec: 01450693 addi a3,a0,20 -800095f0: 02c75263 bge a4,a2,80009614 <__any_on+0x30> -800095f4: 00271793 slli a5,a4,0x2 -800095f8: 00f687b3 add a5,a3,a5 -800095fc: 04f6f263 bgeu a3,a5,80009640 <__any_on+0x5c> -80009600: ffc7a703 lw a4,-4(a5) -80009604: ffc78793 addi a5,a5,-4 -80009608: fe070ae3 beqz a4,800095fc <__any_on+0x18> -8000960c: 00100513 li a0,1 +80009508 <__any_on>: +80009508: 01052703 lw a4,16(a0) +8000950c: 4055d613 srai a2,a1,0x5 +80009510: 01450693 addi a3,a0,20 +80009514: 02c75263 bge a4,a2,80009538 <__any_on+0x30> +80009518: 00271793 slli a5,a4,0x2 +8000951c: 00f687b3 add a5,a3,a5 +80009520: 04f6f263 bgeu a3,a5,80009564 <__any_on+0x5c> +80009524: ffc7a703 lw a4,-4(a5) +80009528: ffc78793 addi a5,a5,-4 +8000952c: fe070ae3 beqz a4,80009520 <__any_on+0x18> +80009530: 00100513 li a0,1 +80009534: 00008067 ret +80009538: 00261793 slli a5,a2,0x2 +8000953c: 00f687b3 add a5,a3,a5 +80009540: fee650e3 bge a2,a4,80009520 <__any_on+0x18> +80009544: 01f5f593 andi a1,a1,31 +80009548: fc058ce3 beqz a1,80009520 <__any_on+0x18> +8000954c: 0007a603 lw a2,0(a5) +80009550: 00100513 li a0,1 +80009554: 00b65733 srl a4,a2,a1 +80009558: 00b715b3 sll a1,a4,a1 +8000955c: fcb602e3 beq a2,a1,80009520 <__any_on+0x18> +80009560: 00008067 ret +80009564: 00000513 li a0,0 +80009568: 00008067 ret + +8000956c : +8000956c: ff010113 addi sp,sp,-16 +80009570: 00912223 sw s1,4(sp) +80009574: 800004b7 lui s1,0x80000 +80009578: 00812423 sw s0,8(sp) +8000957c: 00112623 sw ra,12(sp) +80009580: fff4c493 not s1,s1 +80009584: 00060413 mv s0,a2 +80009588: 00062023 sw zero,0(a2) +8000958c: 00b4f6b3 and a3,s1,a1 +80009590: 7ff00637 lui a2,0x7ff00 +80009594: 00058793 mv a5,a1 +80009598: 00050713 mv a4,a0 +8000959c: 04c6de63 bge a3,a2,800095f8 +800095a0: 00a6e8b3 or a7,a3,a0 +800095a4: 04088a63 beqz a7,800095f8 +800095a8: 00c5f633 and a2,a1,a2 +800095ac: 00058813 mv a6,a1 +800095b0: 00000893 li a7,0 +800095b4: 02061063 bnez a2,800095d4 +800095b8: 34c1a683 lw a3,844(gp) # 80016b54 <__SDATA_BEGIN__+0x14> +800095bc: 3481a603 lw a2,840(gp) # 80016b50 <__SDATA_BEGIN__+0x10> +800095c0: 629070ef jal ra,800113e8 <__muldf3> +800095c4: 00050713 mv a4,a0 +800095c8: 00058813 mv a6,a1 +800095cc: 00b4f6b3 and a3,s1,a1 +800095d0: fca00893 li a7,-54 +800095d4: 4146d693 srai a3,a3,0x14 +800095d8: 801007b7 lui a5,0x80100 +800095dc: fff78793 addi a5,a5,-1 # 800fffff <__BSS_END__+0xe93c3> +800095e0: c0268693 addi a3,a3,-1022 +800095e4: 00f87833 and a6,a6,a5 +800095e8: 011686b3 add a3,a3,a7 +800095ec: 3fe007b7 lui a5,0x3fe00 +800095f0: 00f867b3 or a5,a6,a5 +800095f4: 00d42023 sw a3,0(s0) +800095f8: 00c12083 lw ra,12(sp) +800095fc: 00812403 lw s0,8(sp) +80009600: 00412483 lw s1,4(sp) +80009604: 00070513 mv a0,a4 +80009608: 00078593 mv a1,a5 +8000960c: 01010113 addi sp,sp,16 80009610: 00008067 ret -80009614: 00261793 slli a5,a2,0x2 -80009618: 00f687b3 add a5,a3,a5 -8000961c: fee650e3 bge a2,a4,800095fc <__any_on+0x18> -80009620: 01f5f593 andi a1,a1,31 -80009624: fc058ce3 beqz a1,800095fc <__any_on+0x18> -80009628: 0007a603 lw a2,0(a5) -8000962c: 00100513 li a0,1 -80009630: 00b65733 srl a4,a2,a1 -80009634: 00b715b3 sll a1,a4,a1 -80009638: fcb602e3 beq a2,a1,800095fc <__any_on+0x18> -8000963c: 00008067 ret -80009640: 00000513 li a0,0 -80009644: 00008067 ret -80009648 <_sbrk_r>: -80009648: ff010113 addi sp,sp,-16 -8000964c: 00812423 sw s0,8(sp) -80009650: 00912223 sw s1,4(sp) -80009654: 00050413 mv s0,a0 -80009658: 00058513 mv a0,a1 -8000965c: 00112623 sw ra,12(sp) -80009660: 4201a223 sw zero,1060(gp) # 80016c2c -80009664: ef1f60ef jal ra,80000554 <_sbrk> -80009668: fff00793 li a5,-1 -8000966c: 00f50c63 beq a0,a5,80009684 <_sbrk_r+0x3c> -80009670: 00c12083 lw ra,12(sp) -80009674: 00812403 lw s0,8(sp) -80009678: 00412483 lw s1,4(sp) -8000967c: 01010113 addi sp,sp,16 -80009680: 00008067 ret -80009684: 4241a783 lw a5,1060(gp) # 80016c2c -80009688: fe0784e3 beqz a5,80009670 <_sbrk_r+0x28> -8000968c: 00c12083 lw ra,12(sp) -80009690: 00f42023 sw a5,0(s0) -80009694: 00812403 lw s0,8(sp) -80009698: 00412483 lw s1,4(sp) -8000969c: 01010113 addi sp,sp,16 -800096a0: 00008067 ret +80009614 <_sbrk_r>: +80009614: ff010113 addi sp,sp,-16 +80009618: 00812423 sw s0,8(sp) +8000961c: 00912223 sw s1,4(sp) +80009620: 00050413 mv s0,a0 +80009624: 00058513 mv a0,a1 +80009628: 00112623 sw ra,12(sp) +8000962c: 4201a823 sw zero,1072(gp) # 80016c38 +80009630: eddf60ef jal ra,8000050c <_sbrk> +80009634: fff00793 li a5,-1 +80009638: 00f50c63 beq a0,a5,80009650 <_sbrk_r+0x3c> +8000963c: 00c12083 lw ra,12(sp) +80009640: 00812403 lw s0,8(sp) +80009644: 00412483 lw s1,4(sp) +80009648: 01010113 addi sp,sp,16 +8000964c: 00008067 ret +80009650: 4301a783 lw a5,1072(gp) # 80016c38 +80009654: fe0784e3 beqz a5,8000963c <_sbrk_r+0x28> +80009658: 00c12083 lw ra,12(sp) +8000965c: 00f42023 sw a5,0(s0) +80009660: 00812403 lw s0,8(sp) +80009664: 00412483 lw s1,4(sp) +80009668: 01010113 addi sp,sp,16 +8000966c: 00008067 ret -800096a4 : -800096a4: ff010113 addi sp,sp,-16 -800096a8: 00912223 sw s1,4(sp) -800096ac: 800004b7 lui s1,0x80000 -800096b0: 00812423 sw s0,8(sp) -800096b4: 00112623 sw ra,12(sp) -800096b8: fff4c493 not s1,s1 -800096bc: 00060413 mv s0,a2 -800096c0: 00062023 sw zero,0(a2) -800096c4: 00b4f6b3 and a3,s1,a1 -800096c8: 7ff00637 lui a2,0x7ff00 -800096cc: 00058793 mv a5,a1 -800096d0: 00050713 mv a4,a0 -800096d4: 04c6de63 bge a3,a2,80009730 -800096d8: 00a6e8b3 or a7,a3,a0 -800096dc: 04088a63 beqz a7,80009730 -800096e0: 00c5f633 and a2,a1,a2 -800096e4: 00058813 mv a6,a1 -800096e8: 00000893 li a7,0 -800096ec: 02061063 bnez a2,8000970c -800096f0: 34c1a683 lw a3,844(gp) # 80016b54 <__SDATA_BEGIN__+0x14> -800096f4: 3481a603 lw a2,840(gp) # 80016b50 <__SDATA_BEGIN__+0x10> -800096f8: 42d070ef jal ra,80011324 <__muldf3> -800096fc: 00050713 mv a4,a0 -80009700: 00058813 mv a6,a1 -80009704: 00b4f6b3 and a3,s1,a1 -80009708: fca00893 li a7,-54 -8000970c: 4146d693 srai a3,a3,0x14 -80009710: 801007b7 lui a5,0x80100 -80009714: fff78793 addi a5,a5,-1 # 800fffff <__BSS_END__+0xe93cf> -80009718: c0268693 addi a3,a3,-1022 -8000971c: 00f87833 and a6,a6,a5 -80009720: 011686b3 add a3,a3,a7 -80009724: 3fe007b7 lui a5,0x3fe00 -80009728: 00f867b3 or a5,a6,a5 -8000972c: 00d42023 sw a3,0(s0) -80009730: 00c12083 lw ra,12(sp) -80009734: 00812403 lw s0,8(sp) -80009738: 00412483 lw s1,4(sp) -8000973c: 00070513 mv a0,a4 -80009740: 00078593 mv a1,a5 -80009744: 01010113 addi sp,sp,16 -80009748: 00008067 ret +80009670 <_sprintf_r>: +80009670: f6010113 addi sp,sp,-160 +80009674: 08c10e93 addi t4,sp,140 +80009678: 08f12a23 sw a5,148(sp) +8000967c: 80000337 lui t1,0x80000 +80009680: ffff07b7 lui a5,0xffff0 +80009684: 00058e13 mv t3,a1 +80009688: fff34313 not t1,t1 +8000968c: 08d12623 sw a3,140(sp) +80009690: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd95cc> +80009694: 00810593 addi a1,sp,8 +80009698: 000e8693 mv a3,t4 +8000969c: 06112e23 sw ra,124(sp) +800096a0: 00f12a23 sw a5,20(sp) +800096a4: 08e12823 sw a4,144(sp) +800096a8: 09012c23 sw a6,152(sp) +800096ac: 09112e23 sw a7,156(sp) +800096b0: 01c12423 sw t3,8(sp) +800096b4: 01c12c23 sw t3,24(sp) +800096b8: 00612e23 sw t1,28(sp) +800096bc: 00612823 sw t1,16(sp) +800096c0: 01d12223 sw t4,4(sp) +800096c4: 3d0000ef jal ra,80009a94 <_svfprintf_r> +800096c8: 00812783 lw a5,8(sp) +800096cc: 00078023 sb zero,0(a5) +800096d0: 07c12083 lw ra,124(sp) +800096d4: 0a010113 addi sp,sp,160 +800096d8: 00008067 ret -8000974c <_sprintf_r>: -8000974c: f6010113 addi sp,sp,-160 -80009750: 08c10e93 addi t4,sp,140 -80009754: 08f12a23 sw a5,148(sp) -80009758: 80000337 lui t1,0x80000 -8000975c: ffff07b7 lui a5,0xffff0 -80009760: 00058e13 mv t3,a1 -80009764: fff34313 not t1,t1 -80009768: 08d12623 sw a3,140(sp) -8000976c: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd95d8> -80009770: 00810593 addi a1,sp,8 -80009774: 000e8693 mv a3,t4 -80009778: 06112e23 sw ra,124(sp) -8000977c: 00f12a23 sw a5,20(sp) -80009780: 08e12823 sw a4,144(sp) -80009784: 09012c23 sw a6,152(sp) -80009788: 09112e23 sw a7,156(sp) -8000978c: 01c12423 sw t3,8(sp) -80009790: 01c12c23 sw t3,24(sp) -80009794: 00612e23 sw t1,28(sp) -80009798: 00612823 sw t1,16(sp) -8000979c: 01d12223 sw t4,4(sp) -800097a0: 54c000ef jal ra,80009cec <_svfprintf_r> -800097a4: 00812783 lw a5,8(sp) -800097a8: 00078023 sb zero,0(a5) -800097ac: 07c12083 lw ra,124(sp) -800097b0: 0a010113 addi sp,sp,160 +800096dc : +800096dc: 00050e13 mv t3,a0 +800096e0: f6010113 addi sp,sp,-160 +800096e4: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +800096e8: 08810e93 addi t4,sp,136 +800096ec: 08f12a23 sw a5,148(sp) +800096f0: 80000337 lui t1,0x80000 +800096f4: ffff07b7 lui a5,0xffff0 +800096f8: fff34313 not t1,t1 +800096fc: 08c12423 sw a2,136(sp) +80009700: 08d12623 sw a3,140(sp) +80009704: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd95cc> +80009708: 00058613 mv a2,a1 +8000970c: 000e8693 mv a3,t4 +80009710: 00810593 addi a1,sp,8 +80009714: 06112e23 sw ra,124(sp) +80009718: 00f12a23 sw a5,20(sp) +8000971c: 08e12823 sw a4,144(sp) +80009720: 09012c23 sw a6,152(sp) +80009724: 09112e23 sw a7,156(sp) +80009728: 01c12423 sw t3,8(sp) +8000972c: 01c12c23 sw t3,24(sp) +80009730: 00612e23 sw t1,28(sp) +80009734: 00612823 sw t1,16(sp) +80009738: 01d12223 sw t4,4(sp) +8000973c: 358000ef jal ra,80009a94 <_svfprintf_r> +80009740: 00812783 lw a5,8(sp) +80009744: 00078023 sb zero,0(a5) +80009748: 07c12083 lw ra,124(sp) +8000974c: 0a010113 addi sp,sp,160 +80009750: 00008067 ret + +80009754 <__sread>: +80009754: ff010113 addi sp,sp,-16 +80009758: 00812423 sw s0,8(sp) +8000975c: 00058413 mv s0,a1 +80009760: 00e59583 lh a1,14(a1) +80009764: 00112623 sw ra,12(sp) +80009768: 775040ef jal ra,8000e6dc <_read_r> +8000976c: 02054063 bltz a0,8000978c <__sread+0x38> +80009770: 05042783 lw a5,80(s0) +80009774: 00c12083 lw ra,12(sp) +80009778: 00a787b3 add a5,a5,a0 +8000977c: 04f42823 sw a5,80(s0) +80009780: 00812403 lw s0,8(sp) +80009784: 01010113 addi sp,sp,16 +80009788: 00008067 ret +8000978c: 00c45783 lhu a5,12(s0) +80009790: fffff737 lui a4,0xfffff +80009794: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> +80009798: 00e7f7b3 and a5,a5,a4 +8000979c: 00c12083 lw ra,12(sp) +800097a0: 00f41623 sh a5,12(s0) +800097a4: 00812403 lw s0,8(sp) +800097a8: 01010113 addi sp,sp,16 +800097ac: 00008067 ret + +800097b0 <__seofread>: +800097b0: 00000513 li a0,0 800097b4: 00008067 ret -800097b8 : -800097b8: 00050e13 mv t3,a0 -800097bc: f6010113 addi sp,sp,-160 -800097c0: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -800097c4: 08810e93 addi t4,sp,136 -800097c8: 08f12a23 sw a5,148(sp) -800097cc: 80000337 lui t1,0x80000 -800097d0: ffff07b7 lui a5,0xffff0 -800097d4: fff34313 not t1,t1 -800097d8: 08c12423 sw a2,136(sp) -800097dc: 08d12623 sw a3,140(sp) -800097e0: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd95d8> -800097e4: 00058613 mv a2,a1 -800097e8: 000e8693 mv a3,t4 -800097ec: 00810593 addi a1,sp,8 -800097f0: 06112e23 sw ra,124(sp) -800097f4: 00f12a23 sw a5,20(sp) -800097f8: 08e12823 sw a4,144(sp) -800097fc: 09012c23 sw a6,152(sp) -80009800: 09112e23 sw a7,156(sp) -80009804: 01c12423 sw t3,8(sp) -80009808: 01c12c23 sw t3,24(sp) -8000980c: 00612e23 sw t1,28(sp) -80009810: 00612823 sw t1,16(sp) -80009814: 01d12223 sw t4,4(sp) -80009818: 4d4000ef jal ra,80009cec <_svfprintf_r> -8000981c: 00812783 lw a5,8(sp) -80009820: 00078023 sb zero,0(a5) -80009824: 07c12083 lw ra,124(sp) -80009828: 0a010113 addi sp,sp,160 -8000982c: 00008067 ret +800097b8 <__swrite>: +800097b8: 00c59783 lh a5,12(a1) +800097bc: fe010113 addi sp,sp,-32 +800097c0: 00812c23 sw s0,24(sp) +800097c4: 00912a23 sw s1,20(sp) +800097c8: 01212823 sw s2,16(sp) +800097cc: 01312623 sw s3,12(sp) +800097d0: 00112e23 sw ra,28(sp) +800097d4: 1007f713 andi a4,a5,256 +800097d8: 00058413 mv s0,a1 +800097dc: 00050493 mv s1,a0 +800097e0: 00e59583 lh a1,14(a1) +800097e4: 00060913 mv s2,a2 +800097e8: 00068993 mv s3,a3 +800097ec: 02071e63 bnez a4,80009828 <__swrite+0x70> +800097f0: fffff737 lui a4,0xfffff +800097f4: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> +800097f8: 00e7f7b3 and a5,a5,a4 +800097fc: 00f41623 sh a5,12(s0) +80009800: 01812403 lw s0,24(sp) +80009804: 01c12083 lw ra,28(sp) +80009808: 00098693 mv a3,s3 +8000980c: 00090613 mv a2,s2 +80009810: 00c12983 lw s3,12(sp) +80009814: 01012903 lw s2,16(sp) +80009818: 00048513 mv a0,s1 +8000981c: 01412483 lw s1,20(sp) +80009820: 02010113 addi sp,sp,32 +80009824: 0a80406f j 8000d8cc <_write_r> +80009828: 00200693 li a3,2 +8000982c: 00000613 li a2,0 +80009830: 399040ef jal ra,8000e3c8 <_lseek_r> +80009834: 00c41783 lh a5,12(s0) +80009838: 00e41583 lh a1,14(s0) +8000983c: fb5ff06f j 800097f0 <__swrite+0x38> -80009830 <__sread>: -80009830: ff010113 addi sp,sp,-16 -80009834: 00812423 sw s0,8(sp) -80009838: 00058413 mv s0,a1 -8000983c: 00e59583 lh a1,14(a1) -80009840: 00112623 sw ra,12(sp) -80009844: 789040ef jal ra,8000e7cc <_read_r> -80009848: 02054063 bltz a0,80009868 <__sread+0x38> -8000984c: 05042783 lw a5,80(s0) -80009850: 00c12083 lw ra,12(sp) -80009854: 00a787b3 add a5,a5,a0 -80009858: 04f42823 sw a5,80(s0) -8000985c: 00812403 lw s0,8(sp) -80009860: 01010113 addi sp,sp,16 -80009864: 00008067 ret -80009868: 00c45783 lhu a5,12(s0) -8000986c: fffff737 lui a4,0xfffff -80009870: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83cf> -80009874: 00e7f7b3 and a5,a5,a4 -80009878: 00c12083 lw ra,12(sp) -8000987c: 00f41623 sh a5,12(s0) -80009880: 00812403 lw s0,8(sp) -80009884: 01010113 addi sp,sp,16 -80009888: 00008067 ret +80009840 <__sseek>: +80009840: ff010113 addi sp,sp,-16 +80009844: 00812423 sw s0,8(sp) +80009848: 00058413 mv s0,a1 +8000984c: 00e59583 lh a1,14(a1) +80009850: 00112623 sw ra,12(sp) +80009854: 375040ef jal ra,8000e3c8 <_lseek_r> +80009858: fff00793 li a5,-1 +8000985c: 02f50463 beq a0,a5,80009884 <__sseek+0x44> +80009860: 00c45783 lhu a5,12(s0) +80009864: 00001737 lui a4,0x1 +80009868: 00c12083 lw ra,12(sp) +8000986c: 00e7e7b3 or a5,a5,a4 +80009870: 04a42823 sw a0,80(s0) +80009874: 00f41623 sh a5,12(s0) +80009878: 00812403 lw s0,8(sp) +8000987c: 01010113 addi sp,sp,16 +80009880: 00008067 ret +80009884: 00c45783 lhu a5,12(s0) +80009888: fffff737 lui a4,0xfffff +8000988c: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> +80009890: 00e7f7b3 and a5,a5,a4 +80009894: 00c12083 lw ra,12(sp) +80009898: 00f41623 sh a5,12(s0) +8000989c: 00812403 lw s0,8(sp) +800098a0: 01010113 addi sp,sp,16 +800098a4: 00008067 ret -8000988c <__seofread>: -8000988c: 00000513 li a0,0 -80009890: 00008067 ret +800098a8 <__sclose>: +800098a8: 00e59583 lh a1,14(a1) +800098ac: 1d00406f j 8000da7c <_close_r> -80009894 <__swrite>: -80009894: 00c59783 lh a5,12(a1) -80009898: fe010113 addi sp,sp,-32 -8000989c: 00812c23 sw s0,24(sp) -800098a0: 00912a23 sw s1,20(sp) -800098a4: 01212823 sw s2,16(sp) -800098a8: 01312623 sw s3,12(sp) -800098ac: 00112e23 sw ra,28(sp) -800098b0: 1007f713 andi a4,a5,256 -800098b4: 00058413 mv s0,a1 -800098b8: 00050493 mv s1,a0 -800098bc: 00e59583 lh a1,14(a1) -800098c0: 00060913 mv s2,a2 -800098c4: 00068993 mv s3,a3 -800098c8: 02071e63 bnez a4,80009904 <__swrite+0x70> -800098cc: fffff737 lui a4,0xfffff -800098d0: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83cf> -800098d4: 00e7f7b3 and a5,a5,a4 -800098d8: 00f41623 sh a5,12(s0) -800098dc: 01812403 lw s0,24(sp) -800098e0: 01c12083 lw ra,28(sp) -800098e4: 00098693 mv a3,s3 -800098e8: 00090613 mv a2,s2 -800098ec: 00c12983 lw s3,12(sp) -800098f0: 01012903 lw s2,16(sp) -800098f4: 00048513 mv a0,s1 -800098f8: 01412483 lw s1,20(sp) -800098fc: 02010113 addi sp,sp,32 -80009900: 25c0406f j 8000db5c <_write_r> -80009904: 00200693 li a3,2 -80009908: 00000613 li a2,0 -8000990c: 41d040ef jal ra,8000e528 <_lseek_r> -80009910: 00c41783 lh a5,12(s0) -80009914: 00e41583 lh a1,14(s0) -80009918: fb5ff06f j 800098cc <__swrite+0x38> +800098b0 : +800098b0: 00b567b3 or a5,a0,a1 +800098b4: 0037f793 andi a5,a5,3 +800098b8: 08079263 bnez a5,8000993c +800098bc: 0005a703 lw a4,0(a1) +800098c0: 7f7f86b7 lui a3,0x7f7f8 +800098c4: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> +800098c8: 00d777b3 and a5,a4,a3 +800098cc: 00d787b3 add a5,a5,a3 +800098d0: 00e7e7b3 or a5,a5,a4 +800098d4: 00d7e7b3 or a5,a5,a3 +800098d8: fff00613 li a2,-1 +800098dc: 06c79e63 bne a5,a2,80009958 +800098e0: 00050613 mv a2,a0 +800098e4: fff00813 li a6,-1 +800098e8: 00e62023 sw a4,0(a2) # 7ff00000 <_start-0x100000> +800098ec: 0045a703 lw a4,4(a1) +800098f0: 00458593 addi a1,a1,4 +800098f4: 00460613 addi a2,a2,4 +800098f8: 00d777b3 and a5,a4,a3 +800098fc: 00d787b3 add a5,a5,a3 +80009900: 00e7e7b3 or a5,a5,a4 +80009904: 00d7e7b3 or a5,a5,a3 +80009908: ff0780e3 beq a5,a6,800098e8 +8000990c: 0005c783 lbu a5,0(a1) +80009910: 0015c703 lbu a4,1(a1) +80009914: 0025c683 lbu a3,2(a1) +80009918: 00f60023 sb a5,0(a2) +8000991c: 00078a63 beqz a5,80009930 +80009920: 00e600a3 sb a4,1(a2) +80009924: 00070663 beqz a4,80009930 +80009928: 00d60123 sb a3,2(a2) +8000992c: 00069463 bnez a3,80009934 +80009930: 00008067 ret +80009934: 000601a3 sb zero,3(a2) +80009938: 00008067 ret +8000993c: 00050793 mv a5,a0 +80009940: 0005c703 lbu a4,0(a1) +80009944: 00178793 addi a5,a5,1 +80009948: 00158593 addi a1,a1,1 +8000994c: fee78fa3 sb a4,-1(a5) +80009950: fe0718e3 bnez a4,80009940 +80009954: 00008067 ret +80009958: 00050613 mv a2,a0 +8000995c: fb1ff06f j 8000990c -8000991c <__sseek>: -8000991c: ff010113 addi sp,sp,-16 -80009920: 00812423 sw s0,8(sp) -80009924: 00058413 mv s0,a1 -80009928: 00e59583 lh a1,14(a1) -8000992c: 00112623 sw ra,12(sp) -80009930: 3f9040ef jal ra,8000e528 <_lseek_r> -80009934: fff00793 li a5,-1 -80009938: 02f50463 beq a0,a5,80009960 <__sseek+0x44> -8000993c: 00c45783 lhu a5,12(s0) -80009940: 00001737 lui a4,0x1 -80009944: 00c12083 lw ra,12(sp) -80009948: 00e7e7b3 or a5,a5,a4 -8000994c: 04a42823 sw a0,80(s0) -80009950: 00f41623 sh a5,12(s0) -80009954: 00812403 lw s0,8(sp) -80009958: 01010113 addi sp,sp,16 -8000995c: 00008067 ret -80009960: 00c45783 lhu a5,12(s0) -80009964: fffff737 lui a4,0xfffff -80009968: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83cf> -8000996c: 00e7f7b3 and a5,a5,a4 -80009970: 00c12083 lw ra,12(sp) -80009974: 00f41623 sh a5,12(s0) -80009978: 00812403 lw s0,8(sp) -8000997c: 01010113 addi sp,sp,16 -80009980: 00008067 ret +80009960 : +80009960: 00357793 andi a5,a0,3 +80009964: 00050713 mv a4,a0 +80009968: 04079c63 bnez a5,800099c0 +8000996c: 7f7f86b7 lui a3,0x7f7f8 +80009970: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> +80009974: fff00593 li a1,-1 +80009978: 00072603 lw a2,0(a4) +8000997c: 00470713 addi a4,a4,4 +80009980: 00d677b3 and a5,a2,a3 +80009984: 00d787b3 add a5,a5,a3 +80009988: 00c7e7b3 or a5,a5,a2 +8000998c: 00d7e7b3 or a5,a5,a3 +80009990: feb784e3 beq a5,a1,80009978 +80009994: ffc74683 lbu a3,-4(a4) +80009998: ffd74603 lbu a2,-3(a4) +8000999c: ffe74783 lbu a5,-2(a4) +800099a0: 40a70733 sub a4,a4,a0 +800099a4: 04068063 beqz a3,800099e4 +800099a8: 02060a63 beqz a2,800099dc +800099ac: 00f03533 snez a0,a5 +800099b0: 00e50533 add a0,a0,a4 +800099b4: ffe50513 addi a0,a0,-2 +800099b8: 00008067 ret +800099bc: fa0688e3 beqz a3,8000996c +800099c0: 00074783 lbu a5,0(a4) +800099c4: 00170713 addi a4,a4,1 +800099c8: 00377693 andi a3,a4,3 +800099cc: fe0798e3 bnez a5,800099bc +800099d0: 40a70733 sub a4,a4,a0 +800099d4: fff70513 addi a0,a4,-1 +800099d8: 00008067 ret +800099dc: ffd70513 addi a0,a4,-3 +800099e0: 00008067 ret +800099e4: ffc70513 addi a0,a4,-4 +800099e8: 00008067 ret -80009984 <__sclose>: -80009984: 00e59583 lh a1,14(a1) -80009988: 2ec0406f j 8000dc74 <_close_r> +800099ec : +800099ec: 00a5e7b3 or a5,a1,a0 +800099f0: 0037f793 andi a5,a5,3 +800099f4: 00050713 mv a4,a0 +800099f8: 06079863 bnez a5,80009a68 +800099fc: 00300793 li a5,3 +80009a00: 06c7f463 bgeu a5,a2,80009a68 +80009a04: feff0337 lui t1,0xfeff0 +80009a08: 808088b7 lui a7,0x80808 +80009a0c: eff30313 addi t1,t1,-257 # fefefeff <__BSS_END__+0x7efd92c3> +80009a10: 08088893 addi a7,a7,128 # 80808080 <__BSS_END__+0x7f1444> +80009a14: 00300e13 li t3,3 +80009a18: 0005a683 lw a3,0(a1) +80009a1c: 006687b3 add a5,a3,t1 +80009a20: fff6c813 not a6,a3 +80009a24: 0107f7b3 and a5,a5,a6 +80009a28: 0117f7b3 and a5,a5,a7 +80009a2c: 02079e63 bnez a5,80009a68 +80009a30: 00d72023 sw a3,0(a4) +80009a34: ffc60613 addi a2,a2,-4 +80009a38: 00470713 addi a4,a4,4 +80009a3c: 00458593 addi a1,a1,4 +80009a40: fcce6ce3 bltu t3,a2,80009a18 +80009a44: 00158593 addi a1,a1,1 +80009a48: 00170793 addi a5,a4,1 +80009a4c: 02060463 beqz a2,80009a74 +80009a50: fff5c683 lbu a3,-1(a1) +80009a54: fff60813 addi a6,a2,-1 +80009a58: fed78fa3 sb a3,-1(a5) +80009a5c: 00068e63 beqz a3,80009a78 +80009a60: 00078713 mv a4,a5 +80009a64: 00080613 mv a2,a6 +80009a68: 00158593 addi a1,a1,1 +80009a6c: 00170793 addi a5,a4,1 +80009a70: fe0610e3 bnez a2,80009a50 +80009a74: 00008067 ret +80009a78: 00c70633 add a2,a4,a2 +80009a7c: 00080a63 beqz a6,80009a90 +80009a80: 00178793 addi a5,a5,1 +80009a84: fe078fa3 sb zero,-1(a5) +80009a88: fec79ce3 bne a5,a2,80009a80 +80009a8c: 00008067 ret +80009a90: 00008067 ret -8000998c : -8000998c: 00b56733 or a4,a0,a1 -80009990: fff00393 li t2,-1 -80009994: 00377713 andi a4,a4,3 -80009998: 10071063 bnez a4,80009a98 -8000999c: 7f7f87b7 lui a5,0x7f7f8 -800099a0: f7f78793 addi a5,a5,-129 # 7f7f7f7f <_start-0x808081> -800099a4: 00052603 lw a2,0(a0) -800099a8: 0005a683 lw a3,0(a1) -800099ac: 00f672b3 and t0,a2,a5 -800099b0: 00f66333 or t1,a2,a5 -800099b4: 00f282b3 add t0,t0,a5 -800099b8: 0062e2b3 or t0,t0,t1 -800099bc: 10729263 bne t0,t2,80009ac0 -800099c0: 08d61663 bne a2,a3,80009a4c -800099c4: 00452603 lw a2,4(a0) -800099c8: 0045a683 lw a3,4(a1) -800099cc: 00f672b3 and t0,a2,a5 -800099d0: 00f66333 or t1,a2,a5 -800099d4: 00f282b3 add t0,t0,a5 -800099d8: 0062e2b3 or t0,t0,t1 -800099dc: 0c729e63 bne t0,t2,80009ab8 -800099e0: 06d61663 bne a2,a3,80009a4c -800099e4: 00852603 lw a2,8(a0) -800099e8: 0085a683 lw a3,8(a1) -800099ec: 00f672b3 and t0,a2,a5 -800099f0: 00f66333 or t1,a2,a5 -800099f4: 00f282b3 add t0,t0,a5 -800099f8: 0062e2b3 or t0,t0,t1 -800099fc: 0c729863 bne t0,t2,80009acc -80009a00: 04d61663 bne a2,a3,80009a4c -80009a04: 00c52603 lw a2,12(a0) -80009a08: 00c5a683 lw a3,12(a1) -80009a0c: 00f672b3 and t0,a2,a5 -80009a10: 00f66333 or t1,a2,a5 -80009a14: 00f282b3 add t0,t0,a5 -80009a18: 0062e2b3 or t0,t0,t1 -80009a1c: 0c729263 bne t0,t2,80009ae0 -80009a20: 02d61663 bne a2,a3,80009a4c -80009a24: 01052603 lw a2,16(a0) -80009a28: 0105a683 lw a3,16(a1) -80009a2c: 00f672b3 and t0,a2,a5 -80009a30: 00f66333 or t1,a2,a5 -80009a34: 00f282b3 add t0,t0,a5 -80009a38: 0062e2b3 or t0,t0,t1 -80009a3c: 0a729c63 bne t0,t2,80009af4 -80009a40: 01450513 addi a0,a0,20 -80009a44: 01458593 addi a1,a1,20 -80009a48: f4d60ee3 beq a2,a3,800099a4 -80009a4c: 01061713 slli a4,a2,0x10 -80009a50: 01069793 slli a5,a3,0x10 -80009a54: 00f71e63 bne a4,a5,80009a70 -80009a58: 01065713 srli a4,a2,0x10 -80009a5c: 0106d793 srli a5,a3,0x10 -80009a60: 40f70533 sub a0,a4,a5 -80009a64: 0ff57593 andi a1,a0,255 -80009a68: 02059063 bnez a1,80009a88 -80009a6c: 00008067 ret -80009a70: 01075713 srli a4,a4,0x10 -80009a74: 0107d793 srli a5,a5,0x10 -80009a78: 40f70533 sub a0,a4,a5 -80009a7c: 0ff57593 andi a1,a0,255 -80009a80: 00059463 bnez a1,80009a88 -80009a84: 00008067 ret -80009a88: 0ff77713 andi a4,a4,255 -80009a8c: 0ff7f793 andi a5,a5,255 -80009a90: 40f70533 sub a0,a4,a5 -80009a94: 00008067 ret -80009a98: 00054603 lbu a2,0(a0) -80009a9c: 0005c683 lbu a3,0(a1) -80009aa0: 00150513 addi a0,a0,1 -80009aa4: 00158593 addi a1,a1,1 -80009aa8: 00d61463 bne a2,a3,80009ab0 -80009aac: fe0616e3 bnez a2,80009a98 -80009ab0: 40d60533 sub a0,a2,a3 -80009ab4: 00008067 ret -80009ab8: 00450513 addi a0,a0,4 -80009abc: 00458593 addi a1,a1,4 -80009ac0: fcd61ce3 bne a2,a3,80009a98 -80009ac4: 00000513 li a0,0 -80009ac8: 00008067 ret -80009acc: 00850513 addi a0,a0,8 -80009ad0: 00858593 addi a1,a1,8 -80009ad4: fcd612e3 bne a2,a3,80009a98 -80009ad8: 00000513 li a0,0 -80009adc: 00008067 ret -80009ae0: 00c50513 addi a0,a0,12 -80009ae4: 00c58593 addi a1,a1,12 -80009ae8: fad618e3 bne a2,a3,80009a98 -80009aec: 00000513 li a0,0 -80009af0: 00008067 ret -80009af4: 01050513 addi a0,a0,16 -80009af8: 01058593 addi a1,a1,16 -80009afc: f8d61ee3 bne a2,a3,80009a98 -80009b00: 00000513 li a0,0 -80009b04: 00008067 ret - -80009b08 : -80009b08: 00b567b3 or a5,a0,a1 -80009b0c: 0037f793 andi a5,a5,3 -80009b10: 08079263 bnez a5,80009b94 -80009b14: 0005a703 lw a4,0(a1) -80009b18: 7f7f86b7 lui a3,0x7f7f8 -80009b1c: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> -80009b20: 00d777b3 and a5,a4,a3 -80009b24: 00d787b3 add a5,a5,a3 -80009b28: 00e7e7b3 or a5,a5,a4 -80009b2c: 00d7e7b3 or a5,a5,a3 -80009b30: fff00613 li a2,-1 -80009b34: 06c79e63 bne a5,a2,80009bb0 -80009b38: 00050613 mv a2,a0 -80009b3c: fff00813 li a6,-1 -80009b40: 00e62023 sw a4,0(a2) # 7ff00000 <_start-0x100000> -80009b44: 0045a703 lw a4,4(a1) -80009b48: 00458593 addi a1,a1,4 -80009b4c: 00460613 addi a2,a2,4 -80009b50: 00d777b3 and a5,a4,a3 -80009b54: 00d787b3 add a5,a5,a3 -80009b58: 00e7e7b3 or a5,a5,a4 -80009b5c: 00d7e7b3 or a5,a5,a3 -80009b60: ff0780e3 beq a5,a6,80009b40 -80009b64: 0005c783 lbu a5,0(a1) -80009b68: 0015c703 lbu a4,1(a1) -80009b6c: 0025c683 lbu a3,2(a1) -80009b70: 00f60023 sb a5,0(a2) -80009b74: 00078a63 beqz a5,80009b88 -80009b78: 00e600a3 sb a4,1(a2) -80009b7c: 00070663 beqz a4,80009b88 -80009b80: 00d60123 sb a3,2(a2) -80009b84: 00069463 bnez a3,80009b8c -80009b88: 00008067 ret -80009b8c: 000601a3 sb zero,3(a2) -80009b90: 00008067 ret -80009b94: 00050793 mv a5,a0 -80009b98: 0005c703 lbu a4,0(a1) -80009b9c: 00178793 addi a5,a5,1 -80009ba0: 00158593 addi a1,a1,1 -80009ba4: fee78fa3 sb a4,-1(a5) -80009ba8: fe0718e3 bnez a4,80009b98 -80009bac: 00008067 ret -80009bb0: 00050613 mv a2,a0 -80009bb4: fb1ff06f j 80009b64 - -80009bb8 : -80009bb8: 00357793 andi a5,a0,3 -80009bbc: 00050713 mv a4,a0 -80009bc0: 04079c63 bnez a5,80009c18 -80009bc4: 7f7f86b7 lui a3,0x7f7f8 -80009bc8: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> -80009bcc: fff00593 li a1,-1 -80009bd0: 00072603 lw a2,0(a4) -80009bd4: 00470713 addi a4,a4,4 -80009bd8: 00d677b3 and a5,a2,a3 -80009bdc: 00d787b3 add a5,a5,a3 -80009be0: 00c7e7b3 or a5,a5,a2 -80009be4: 00d7e7b3 or a5,a5,a3 -80009be8: feb784e3 beq a5,a1,80009bd0 -80009bec: ffc74683 lbu a3,-4(a4) -80009bf0: ffd74603 lbu a2,-3(a4) -80009bf4: ffe74783 lbu a5,-2(a4) -80009bf8: 40a70733 sub a4,a4,a0 -80009bfc: 04068063 beqz a3,80009c3c -80009c00: 02060a63 beqz a2,80009c34 -80009c04: 00f03533 snez a0,a5 -80009c08: 00e50533 add a0,a0,a4 -80009c0c: ffe50513 addi a0,a0,-2 -80009c10: 00008067 ret -80009c14: fa0688e3 beqz a3,80009bc4 -80009c18: 00074783 lbu a5,0(a4) -80009c1c: 00170713 addi a4,a4,1 -80009c20: 00377693 andi a3,a4,3 -80009c24: fe0798e3 bnez a5,80009c14 -80009c28: 40a70733 sub a4,a4,a0 -80009c2c: fff70513 addi a0,a4,-1 -80009c30: 00008067 ret -80009c34: ffd70513 addi a0,a4,-3 -80009c38: 00008067 ret -80009c3c: ffc70513 addi a0,a4,-4 -80009c40: 00008067 ret - -80009c44 : -80009c44: 00a5e7b3 or a5,a1,a0 -80009c48: 0037f793 andi a5,a5,3 -80009c4c: 00050713 mv a4,a0 -80009c50: 06079863 bnez a5,80009cc0 -80009c54: 00300793 li a5,3 -80009c58: 06c7f463 bgeu a5,a2,80009cc0 -80009c5c: feff0337 lui t1,0xfeff0 -80009c60: 808088b7 lui a7,0x80808 -80009c64: eff30313 addi t1,t1,-257 # fefefeff <__BSS_END__+0x7efd92cf> -80009c68: 08088893 addi a7,a7,128 # 80808080 <__BSS_END__+0x7f1450> -80009c6c: 00300e13 li t3,3 -80009c70: 0005a683 lw a3,0(a1) -80009c74: 006687b3 add a5,a3,t1 -80009c78: fff6c813 not a6,a3 -80009c7c: 0107f7b3 and a5,a5,a6 -80009c80: 0117f7b3 and a5,a5,a7 -80009c84: 02079e63 bnez a5,80009cc0 -80009c88: 00d72023 sw a3,0(a4) -80009c8c: ffc60613 addi a2,a2,-4 -80009c90: 00470713 addi a4,a4,4 -80009c94: 00458593 addi a1,a1,4 -80009c98: fcce6ce3 bltu t3,a2,80009c70 -80009c9c: 00158593 addi a1,a1,1 -80009ca0: 00170793 addi a5,a4,1 -80009ca4: 02060463 beqz a2,80009ccc -80009ca8: fff5c683 lbu a3,-1(a1) -80009cac: fff60813 addi a6,a2,-1 -80009cb0: fed78fa3 sb a3,-1(a5) -80009cb4: 00068e63 beqz a3,80009cd0 -80009cb8: 00078713 mv a4,a5 -80009cbc: 00080613 mv a2,a6 -80009cc0: 00158593 addi a1,a1,1 -80009cc4: 00170793 addi a5,a4,1 -80009cc8: fe0610e3 bnez a2,80009ca8 -80009ccc: 00008067 ret -80009cd0: 00c70633 add a2,a4,a2 -80009cd4: 00080a63 beqz a6,80009ce8 -80009cd8: 00178793 addi a5,a5,1 -80009cdc: fe078fa3 sb zero,-1(a5) -80009ce0: fec79ce3 bne a5,a2,80009cd8 -80009ce4: 00008067 ret -80009ce8: 00008067 ret - -80009cec <_svfprintf_r>: -80009cec: e1010113 addi sp,sp,-496 -80009cf0: 1e112623 sw ra,492(sp) -80009cf4: 1f212023 sw s2,480(sp) -80009cf8: 1d812423 sw s8,456(sp) -80009cfc: 1da12023 sw s10,448(sp) -80009d00: 00058c13 mv s8,a1 -80009d04: 00060913 mv s2,a2 -80009d08: 00d12a23 sw a3,20(sp) -80009d0c: 1e812423 sw s0,488(sp) -80009d10: 1e912223 sw s1,484(sp) -80009d14: 1d312e23 sw s3,476(sp) -80009d18: 1d412c23 sw s4,472(sp) -80009d1c: 1d512a23 sw s5,468(sp) -80009d20: 1d612823 sw s6,464(sp) -80009d24: 1d712623 sw s7,460(sp) -80009d28: 1d912223 sw s9,452(sp) -80009d2c: 1bb12e23 sw s11,444(sp) -80009d30: 00050d13 mv s10,a0 -80009d34: d25fd0ef jal ra,80007a58 <_localeconv_r> -80009d38: 00052783 lw a5,0(a0) -80009d3c: 00078513 mv a0,a5 -80009d40: 02f12823 sw a5,48(sp) -80009d44: e75ff0ef jal ra,80009bb8 -80009d48: 00cc5703 lhu a4,12(s8) -80009d4c: 0e012823 sw zero,240(sp) -80009d50: 0e012a23 sw zero,244(sp) -80009d54: 0e012c23 sw zero,248(sp) -80009d58: 0e012e23 sw zero,252(sp) -80009d5c: 08077713 andi a4,a4,128 -80009d60: 02a12623 sw a0,44(sp) -80009d64: 00070863 beqz a4,80009d74 <_svfprintf_r+0x88> -80009d68: 010c2703 lw a4,16(s8) -80009d6c: 00071463 bnez a4,80009d74 <_svfprintf_r+0x88> -80009d70: 56c0106f j 8000b2dc <_svfprintf_r+0x15f0> -80009d74: 10c10793 addi a5,sp,268 -80009d78: 80015737 lui a4,0x80015 -80009d7c: 0ef12223 sw a5,228(sp) -80009d80: 00078893 mv a7,a5 -80009d84: 1a070793 addi a5,a4,416 # 800151a0 <__BSS_END__+0xffffe570> -80009d88: 80015737 lui a4,0x80015 -80009d8c: 00f12c23 sw a5,24(sp) -80009d90: 00090b13 mv s6,s2 -80009d94: 31c70793 addi a5,a4,796 # 8001531c <__BSS_END__+0xffffe6ec> -80009d98: 00f12423 sw a5,8(sp) -80009d9c: 000b4783 lbu a5,0(s6) -80009da0: 0e012623 sw zero,236(sp) -80009da4: 0e012423 sw zero,232(sp) -80009da8: 02012023 sw zero,32(sp) -80009dac: 02012a23 sw zero,52(sp) -80009db0: 02012c23 sw zero,56(sp) -80009db4: 02012e23 sw zero,60(sp) -80009db8: 04012423 sw zero,72(sp) -80009dbc: 04012623 sw zero,76(sp) -80009dc0: 00012623 sw zero,12(sp) -80009dc4: 22078463 beqz a5,80009fec <_svfprintf_r+0x300> -80009dc8: 000b0413 mv s0,s6 -80009dcc: 02500693 li a3,37 -80009dd0: 2cd78463 beq a5,a3,8000a098 <_svfprintf_r+0x3ac> -80009dd4: 00144783 lbu a5,1(s0) -80009dd8: 00140413 addi s0,s0,1 -80009ddc: fe079ae3 bnez a5,80009dd0 <_svfprintf_r+0xe4> -80009de0: 416404b3 sub s1,s0,s6 -80009de4: 21640463 beq s0,s6,80009fec <_svfprintf_r+0x300> -80009de8: 0ec12683 lw a3,236(sp) -80009dec: 0e812783 lw a5,232(sp) -80009df0: 0168a023 sw s6,0(a7) -80009df4: 009686b3 add a3,a3,s1 -80009df8: 00178793 addi a5,a5,1 -80009dfc: 0098a223 sw s1,4(a7) -80009e00: 0ed12623 sw a3,236(sp) -80009e04: 0ef12423 sw a5,232(sp) -80009e08: 00700693 li a3,7 -80009e0c: 00888893 addi a7,a7,8 -80009e10: 28f6cc63 blt a3,a5,8000a0a8 <_svfprintf_r+0x3bc> -80009e14: 00c12703 lw a4,12(sp) -80009e18: 00044783 lbu a5,0(s0) -80009e1c: 00970733 add a4,a4,s1 -80009e20: 00e12623 sw a4,12(sp) -80009e24: 1c078463 beqz a5,80009fec <_svfprintf_r+0x300> -80009e28: 00144483 lbu s1,1(s0) -80009e2c: 0c0103a3 sb zero,199(sp) -80009e30: 00140413 addi s0,s0,1 -80009e34: fff00d93 li s11,-1 -80009e38: 00000993 li s3,0 -80009e3c: 00000a13 li s4,0 -80009e40: 05a00913 li s2,90 -80009e44: 00900a93 li s5,9 -80009e48: 02a00b93 li s7,42 -80009e4c: 00088c93 mv s9,a7 -80009e50: 00140413 addi s0,s0,1 -80009e54: fe048793 addi a5,s1,-32 # 7fffffe0 <__BSS_END__+0xfffe93b0> -80009e58: 04f96463 bltu s2,a5,80009ea0 <_svfprintf_r+0x1b4> -80009e5c: 01812703 lw a4,24(sp) -80009e60: 00279793 slli a5,a5,0x2 -80009e64: 00e787b3 add a5,a5,a4 -80009e68: 0007a783 lw a5,0(a5) -80009e6c: 00078067 jr a5 -80009e70: 00000993 li s3,0 -80009e74: fd048693 addi a3,s1,-48 -80009e78: 00044483 lbu s1,0(s0) -80009e7c: 00299793 slli a5,s3,0x2 -80009e80: 013787b3 add a5,a5,s3 -80009e84: 00179793 slli a5,a5,0x1 -80009e88: 00f689b3 add s3,a3,a5 -80009e8c: fd048693 addi a3,s1,-48 -80009e90: 00140413 addi s0,s0,1 -80009e94: fedaf2e3 bgeu s5,a3,80009e78 <_svfprintf_r+0x18c> -80009e98: fe048793 addi a5,s1,-32 -80009e9c: fcf970e3 bgeu s2,a5,80009e5c <_svfprintf_r+0x170> -80009ea0: 000c8893 mv a7,s9 -80009ea4: 14048463 beqz s1,80009fec <_svfprintf_r+0x300> -80009ea8: 14910623 sb s1,332(sp) -80009eac: 0c0103a3 sb zero,199(sp) -80009eb0: 00100a93 li s5,1 -80009eb4: 00100c93 li s9,1 -80009eb8: 14c10b13 addi s6,sp,332 -80009ebc: 00012823 sw zero,16(sp) -80009ec0: 00000d93 li s11,0 -80009ec4: 02012423 sw zero,40(sp) -80009ec8: 02012223 sw zero,36(sp) -80009ecc: 00012e23 sw zero,28(sp) -80009ed0: 002a7b93 andi s7,s4,2 -80009ed4: 000b8463 beqz s7,80009edc <_svfprintf_r+0x1f0> -80009ed8: 002a8a93 addi s5,s5,2 -80009edc: 084a7913 andi s2,s4,132 -80009ee0: 0ec12783 lw a5,236(sp) -80009ee4: 00091663 bnez s2,80009ef0 <_svfprintf_r+0x204> -80009ee8: 41598833 sub a6,s3,s5 -80009eec: 63004ce3 bgtz a6,8000ad24 <_svfprintf_r+0x1038> -80009ef0: 0c714683 lbu a3,199(sp) -80009ef4: 02068a63 beqz a3,80009f28 <_svfprintf_r+0x23c> -80009ef8: 0e812683 lw a3,232(sp) -80009efc: 0c710613 addi a2,sp,199 -80009f00: 00c8a023 sw a2,0(a7) -80009f04: 00178793 addi a5,a5,1 -80009f08: 00100613 li a2,1 -80009f0c: 00168693 addi a3,a3,1 -80009f10: 00c8a223 sw a2,4(a7) -80009f14: 0ef12623 sw a5,236(sp) -80009f18: 0ed12423 sw a3,232(sp) -80009f1c: 00700613 li a2,7 -80009f20: 00888893 addi a7,a7,8 -80009f24: 4cd64c63 blt a2,a3,8000a3fc <_svfprintf_r+0x710> -80009f28: 020b8a63 beqz s7,80009f5c <_svfprintf_r+0x270> -80009f2c: 0e812683 lw a3,232(sp) -80009f30: 0c810613 addi a2,sp,200 -80009f34: 00c8a023 sw a2,0(a7) -80009f38: 00278793 addi a5,a5,2 -80009f3c: 00200613 li a2,2 -80009f40: 00168693 addi a3,a3,1 -80009f44: 00c8a223 sw a2,4(a7) -80009f48: 0ef12623 sw a5,236(sp) -80009f4c: 0ed12423 sw a3,232(sp) -80009f50: 00700613 li a2,7 -80009f54: 00888893 addi a7,a7,8 -80009f58: 6ad64ce3 blt a2,a3,8000ae10 <_svfprintf_r+0x1124> -80009f5c: 08000693 li a3,128 -80009f60: 42d900e3 beq s2,a3,8000ab80 <_svfprintf_r+0xe94> -80009f64: 419d8db3 sub s11,s11,s9 -80009f68: 4db04ee3 bgtz s11,8000ac44 <_svfprintf_r+0xf58> -80009f6c: 100a7693 andi a3,s4,256 -80009f70: 2c069ae3 bnez a3,8000aa44 <_svfprintf_r+0xd58> -80009f74: 0e812703 lw a4,232(sp) -80009f78: 019787b3 add a5,a5,s9 -80009f7c: 0168a023 sw s6,0(a7) -80009f80: 00170713 addi a4,a4,1 -80009f84: 0198a223 sw s9,4(a7) -80009f88: 0ef12623 sw a5,236(sp) -80009f8c: 0ee12423 sw a4,232(sp) -80009f90: 00700693 li a3,7 -80009f94: 5ae6c063 blt a3,a4,8000a534 <_svfprintf_r+0x848> -80009f98: 00888893 addi a7,a7,8 -80009f9c: 004a7a13 andi s4,s4,4 -80009fa0: 000a0663 beqz s4,80009fac <_svfprintf_r+0x2c0> -80009fa4: 415984b3 sub s1,s3,s5 -80009fa8: 5a904663 bgtz s1,8000a554 <_svfprintf_r+0x868> -80009fac: 0159d463 bge s3,s5,80009fb4 <_svfprintf_r+0x2c8> -80009fb0: 000a8993 mv s3,s5 -80009fb4: 00c12703 lw a4,12(sp) -80009fb8: 01370733 add a4,a4,s3 -80009fbc: 00e12623 sw a4,12(sp) -80009fc0: 52079ce3 bnez a5,8000acf8 <_svfprintf_r+0x100c> -80009fc4: 01012783 lw a5,16(sp) -80009fc8: 0e012423 sw zero,232(sp) -80009fcc: 00078863 beqz a5,80009fdc <_svfprintf_r+0x2f0> -80009fd0: 01012583 lw a1,16(sp) -80009fd4: 000d0513 mv a0,s10 -80009fd8: aadfa0ef jal ra,80004a84 <_free_r> -80009fdc: 10c10893 addi a7,sp,268 -80009fe0: 00040b13 mv s6,s0 -80009fe4: 000b4783 lbu a5,0(s6) -80009fe8: de0790e3 bnez a5,80009dc8 <_svfprintf_r+0xdc> -80009fec: 0ec12783 lw a5,236(sp) -80009ff0: 00078463 beqz a5,80009ff8 <_svfprintf_r+0x30c> -80009ff4: 3450106f j 8000bb38 <_svfprintf_r+0x1e4c> -80009ff8: 00cc5703 lhu a4,12(s8) -80009ffc: 04077713 andi a4,a4,64 -8000a000: 00070463 beqz a4,8000a008 <_svfprintf_r+0x31c> -8000a004: 3f80206f j 8000c3fc <_svfprintf_r+0x2710> -8000a008: 1ec12083 lw ra,492(sp) -8000a00c: 1e812403 lw s0,488(sp) -8000a010: 00c12503 lw a0,12(sp) -8000a014: 1e412483 lw s1,484(sp) -8000a018: 1e012903 lw s2,480(sp) -8000a01c: 1dc12983 lw s3,476(sp) -8000a020: 1d812a03 lw s4,472(sp) -8000a024: 1d412a83 lw s5,468(sp) -8000a028: 1d012b03 lw s6,464(sp) -8000a02c: 1cc12b83 lw s7,460(sp) -8000a030: 1c812c03 lw s8,456(sp) -8000a034: 1c412c83 lw s9,452(sp) -8000a038: 1c012d03 lw s10,448(sp) -8000a03c: 1bc12d83 lw s11,444(sp) -8000a040: 1f010113 addi sp,sp,496 -8000a044: 00008067 ret -8000a048: 000d0513 mv a0,s10 -8000a04c: a0dfd0ef jal ra,80007a58 <_localeconv_r> -8000a050: 00452783 lw a5,4(a0) -8000a054: 00078513 mv a0,a5 -8000a058: 04f12623 sw a5,76(sp) -8000a05c: b5dff0ef jal ra,80009bb8 -8000a060: 00050793 mv a5,a0 -8000a064: 000d0513 mv a0,s10 -8000a068: 00078493 mv s1,a5 -8000a06c: 04f12423 sw a5,72(sp) -8000a070: 9e9fd0ef jal ra,80007a58 <_localeconv_r> -8000a074: 00852783 lw a5,8(a0) -8000a078: 02f12e23 sw a5,60(sp) -8000a07c: 00048463 beqz s1,8000a084 <_svfprintf_r+0x398> -8000a080: 1640106f j 8000b1e4 <_svfprintf_r+0x14f8> -8000a084: 00044483 lbu s1,0(s0) -8000a088: dc9ff06f j 80009e50 <_svfprintf_r+0x164> -8000a08c: 00044483 lbu s1,0(s0) -8000a090: 020a6a13 ori s4,s4,32 -8000a094: dbdff06f j 80009e50 <_svfprintf_r+0x164> -8000a098: 416404b3 sub s1,s0,s6 -8000a09c: d56416e3 bne s0,s6,80009de8 <_svfprintf_r+0xfc> -8000a0a0: 00044783 lbu a5,0(s0) -8000a0a4: d81ff06f j 80009e24 <_svfprintf_r+0x138> -8000a0a8: 0e410613 addi a2,sp,228 -8000a0ac: 000c0593 mv a1,s8 -8000a0b0: 000d0513 mv a0,s10 -8000a0b4: 63d040ef jal ra,8000eef0 <__ssprint_r> -8000a0b8: f40510e3 bnez a0,80009ff8 <_svfprintf_r+0x30c> -8000a0bc: 10c10893 addi a7,sp,268 -8000a0c0: d55ff06f j 80009e14 <_svfprintf_r+0x128> -8000a0c4: 008a7793 andi a5,s4,8 -8000a0c8: 000c8893 mv a7,s9 -8000a0cc: 00078463 beqz a5,8000a0d4 <_svfprintf_r+0x3e8> -8000a0d0: 0a80106f j 8000b178 <_svfprintf_r+0x148c> -8000a0d4: 01412783 lw a5,20(sp) -8000a0d8: 0b010513 addi a0,sp,176 -8000a0dc: 01912823 sw s9,16(sp) -8000a0e0: 00778793 addi a5,a5,7 -8000a0e4: ff87f793 andi a5,a5,-8 -8000a0e8: 0007a583 lw a1,0(a5) -8000a0ec: 0047a603 lw a2,4(a5) -8000a0f0: 00878793 addi a5,a5,8 -8000a0f4: 00f12a23 sw a5,20(sp) -8000a0f8: 2cc0a0ef jal ra,800143c4 <__extenddftf2> -8000a0fc: 0b012783 lw a5,176(sp) -8000a100: 01012883 lw a7,16(sp) -8000a104: 0ef12823 sw a5,240(sp) -8000a108: 0b412783 lw a5,180(sp) -8000a10c: 0ef12a23 sw a5,244(sp) -8000a110: 0b812783 lw a5,184(sp) -8000a114: 0ef12c23 sw a5,248(sp) -8000a118: 0bc12783 lw a5,188(sp) -8000a11c: 0ef12e23 sw a5,252(sp) -8000a120: 0f010513 addi a0,sp,240 -8000a124: 01112823 sw a7,16(sp) -8000a128: 8c5fd0ef jal ra,800079ec <_ldcheck> -8000a12c: 0ca12623 sw a0,204(sp) -8000a130: 00200793 li a5,2 -8000a134: 01012883 lw a7,16(sp) -8000a138: 00f51463 bne a0,a5,8000a140 <_svfprintf_r+0x454> -8000a13c: 6580106f j 8000b794 <_svfprintf_r+0x1aa8> -8000a140: 00100793 li a5,1 -8000a144: 00f51463 bne a0,a5,8000a14c <_svfprintf_r+0x460> -8000a148: 0750106f j 8000b9bc <_svfprintf_r+0x1cd0> -8000a14c: 06100793 li a5,97 -8000a150: 00f49463 bne s1,a5,8000a158 <_svfprintf_r+0x46c> -8000a154: 19c0206f j 8000c2f0 <_svfprintf_r+0x2604> -8000a158: 04100793 li a5,65 -8000a15c: 00f49463 bne s1,a5,8000a164 <_svfprintf_r+0x478> -8000a160: 52d0106f j 8000be8c <_svfprintf_r+0x21a0> -8000a164: fdf4fb93 andi s7,s1,-33 -8000a168: fff00793 li a5,-1 -8000a16c: 05712a23 sw s7,84(sp) -8000a170: 00fd9463 bne s11,a5,8000a178 <_svfprintf_r+0x48c> -8000a174: 2150106f j 8000bb88 <_svfprintf_r+0x1e9c> -8000a178: 04700793 li a5,71 -8000a17c: 00fb9463 bne s7,a5,8000a184 <_svfprintf_r+0x498> -8000a180: 1e80206f j 8000c368 <_svfprintf_r+0x267c> -8000a184: 0fc12303 lw t1,252(sp) -8000a188: 03412423 sw s4,40(sp) -8000a18c: 0f012e03 lw t3,240(sp) -8000a190: 0f412e83 lw t4,244(sp) -8000a194: 0f812f03 lw t5,248(sp) -8000a198: 100a6793 ori a5,s4,256 -8000a19c: 00035463 bgez t1,8000a1a4 <_svfprintf_r+0x4b8> -8000a1a0: 39c0206f j 8000c53c <_svfprintf_r+0x2850> -8000a1a4: 04012c23 sw zero,88(sp) -8000a1a8: 00078a13 mv s4,a5 -8000a1ac: 00012823 sw zero,16(sp) -8000a1b0: 04600793 li a5,70 -8000a1b4: 00fb9463 bne s7,a5,8000a1bc <_svfprintf_r+0x4d0> -8000a1b8: 2b90106f j 8000bc70 <_svfprintf_r+0x1f84> -8000a1bc: 04500793 li a5,69 -8000a1c0: 05112223 sw a7,68(sp) -8000a1c4: 00fb8463 beq s7,a5,8000a1cc <_svfprintf_r+0x4e0> -8000a1c8: 33d0106f j 8000bd04 <_svfprintf_r+0x2018> -8000a1cc: 001d8913 addi s2,s11,1 -8000a1d0: 0b010a93 addi s5,sp,176 -8000a1d4: 00090693 mv a3,s2 -8000a1d8: 0dc10813 addi a6,sp,220 -8000a1dc: 0d010793 addi a5,sp,208 -8000a1e0: 0cc10713 addi a4,sp,204 -8000a1e4: 00200613 li a2,2 -8000a1e8: 000a8593 mv a1,s5 -8000a1ec: 000d0513 mv a0,s10 -8000a1f0: 0bc12823 sw t3,176(sp) -8000a1f4: 05c12023 sw t3,64(sp) -8000a1f8: 0bd12a23 sw t4,180(sp) -8000a1fc: 03d12223 sw t4,36(sp) -8000a200: 0be12c23 sw t5,184(sp) -8000a204: 03e12023 sw t5,32(sp) -8000a208: 0a612e23 sw t1,188(sp) -8000a20c: 00612e23 sw t1,28(sp) -8000a210: d44fc0ef jal ra,80006754 <_ldtoa_r> -8000a214: 01c12303 lw t1,28(sp) -8000a218: 02012f03 lw t5,32(sp) -8000a21c: 02412e83 lw t4,36(sp) -8000a220: 04012e03 lw t3,64(sp) -8000a224: 04412883 lw a7,68(sp) -8000a228: 00050b13 mv s6,a0 -8000a22c: 01250933 add s2,a0,s2 -8000a230: 0a010c93 addi s9,sp,160 -8000a234: 000c8593 mv a1,s9 -8000a238: 000a8513 mv a0,s5 -8000a23c: 01112e23 sw a7,28(sp) -8000a240: 0bc12823 sw t3,176(sp) -8000a244: 0bd12a23 sw t4,180(sp) -8000a248: 0be12c23 sw t5,184(sp) -8000a24c: 0a612e23 sw t1,188(sp) -8000a250: 0a012023 sw zero,160(sp) -8000a254: 0a012223 sw zero,164(sp) -8000a258: 0a012423 sw zero,168(sp) -8000a25c: 0a012623 sw zero,172(sp) -8000a260: 688070ef jal ra,800118e8 <__eqtf2> -8000a264: 01c12883 lw a7,28(sp) -8000a268: 00090713 mv a4,s2 -8000a26c: 02050263 beqz a0,8000a290 <_svfprintf_r+0x5a4> -8000a270: 0dc12703 lw a4,220(sp) -8000a274: 01277e63 bgeu a4,s2,8000a290 <_svfprintf_r+0x5a4> -8000a278: 03000693 li a3,48 -8000a27c: 00170793 addi a5,a4,1 -8000a280: 0cf12e23 sw a5,220(sp) -8000a284: 00d70023 sb a3,0(a4) -8000a288: 0dc12703 lw a4,220(sp) -8000a28c: ff2768e3 bltu a4,s2,8000a27c <_svfprintf_r+0x590> -8000a290: 416707b3 sub a5,a4,s6 -8000a294: 02f12023 sw a5,32(sp) -8000a298: 0cc12703 lw a4,204(sp) -8000a29c: 04700793 li a5,71 -8000a2a0: 00e12e23 sw a4,28(sp) -8000a2a4: 05412703 lw a4,84(sp) -8000a2a8: 00f71463 bne a4,a5,8000a2b0 <_svfprintf_r+0x5c4> -8000a2ac: 1150106f j 8000bbc0 <_svfprintf_r+0x1ed4> -8000a2b0: 05412703 lw a4,84(sp) -8000a2b4: 04600793 li a5,70 -8000a2b8: 00f71463 bne a4,a5,8000a2c0 <_svfprintf_r+0x5d4> -8000a2bc: 34d0106f j 8000be08 <_svfprintf_r+0x211c> -8000a2c0: 01c12783 lw a5,28(sp) -8000a2c4: 05412703 lw a4,84(sp) -8000a2c8: 04100593 li a1,65 -8000a2cc: fff78793 addi a5,a5,-1 -8000a2d0: 0cf12623 sw a5,204(sp) -8000a2d4: 0ff4f693 andi a3,s1,255 -8000a2d8: 00000613 li a2,0 -8000a2dc: 00b71863 bne a4,a1,8000a2ec <_svfprintf_r+0x600> -8000a2e0: 00f68693 addi a3,a3,15 -8000a2e4: 0ff6f693 andi a3,a3,255 -8000a2e8: 00100613 li a2,1 -8000a2ec: 0cd10a23 sb a3,212(sp) -8000a2f0: 02b00693 li a3,43 -8000a2f4: 0007da63 bgez a5,8000a308 <_svfprintf_r+0x61c> -8000a2f8: 01c12703 lw a4,28(sp) -8000a2fc: 00100793 li a5,1 -8000a300: 02d00693 li a3,45 -8000a304: 40e787b3 sub a5,a5,a4 -8000a308: 0cd10aa3 sb a3,213(sp) -8000a30c: 00900693 li a3,9 -8000a310: 00f6c463 blt a3,a5,8000a318 <_svfprintf_r+0x62c> -8000a314: 0f40206f j 8000c408 <_svfprintf_r+0x271c> -8000a318: 0e310813 addi a6,sp,227 -8000a31c: 00080513 mv a0,a6 -8000a320: 00a00613 li a2,10 -8000a324: 06300e13 li t3,99 -8000a328: 02c7e733 rem a4,a5,a2 -8000a32c: 00050593 mv a1,a0 -8000a330: 00078693 mv a3,a5 -8000a334: fff50513 addi a0,a0,-1 -8000a338: 03070713 addi a4,a4,48 -8000a33c: fee58fa3 sb a4,-1(a1) -8000a340: 02c7c7b3 div a5,a5,a2 -8000a344: fede42e3 blt t3,a3,8000a328 <_svfprintf_r+0x63c> -8000a348: 03078793 addi a5,a5,48 -8000a34c: 0ff7f613 andi a2,a5,255 -8000a350: fec50fa3 sb a2,-1(a0) -8000a354: ffe58793 addi a5,a1,-2 -8000a358: 0107e463 bltu a5,a6,8000a360 <_svfprintf_r+0x674> -8000a35c: 3980206f j 8000c6f4 <_svfprintf_r+0x2a08> -8000a360: 0d610693 addi a3,sp,214 -8000a364: 0080006f j 8000a36c <_svfprintf_r+0x680> -8000a368: 0007c603 lbu a2,0(a5) -8000a36c: 00c68023 sb a2,0(a3) -8000a370: 00178793 addi a5,a5,1 -8000a374: 00168693 addi a3,a3,1 -8000a378: ff0798e3 bne a5,a6,8000a368 <_svfprintf_r+0x67c> -8000a37c: 0e510793 addi a5,sp,229 -8000a380: 40b787b3 sub a5,a5,a1 -8000a384: 0d610713 addi a4,sp,214 -8000a388: 00f707b3 add a5,a4,a5 -8000a38c: 0d410693 addi a3,sp,212 -8000a390: 40d787b3 sub a5,a5,a3 -8000a394: 02f12c23 sw a5,56(sp) -8000a398: 02012703 lw a4,32(sp) -8000a39c: 03812683 lw a3,56(sp) -8000a3a0: 00100793 li a5,1 -8000a3a4: 00d70cb3 add s9,a4,a3 -8000a3a8: 00e7c463 blt a5,a4,8000a3b0 <_svfprintf_r+0x6c4> -8000a3ac: 2300206f j 8000c5dc <_svfprintf_r+0x28f0> -8000a3b0: 02c12783 lw a5,44(sp) -8000a3b4: 00fc8cb3 add s9,s9,a5 -8000a3b8: 02812783 lw a5,40(sp) -8000a3bc: fffcca93 not s5,s9 -8000a3c0: 41fada93 srai s5,s5,0x1f -8000a3c4: bff7fa13 andi s4,a5,-1025 -8000a3c8: 100a6a13 ori s4,s4,256 -8000a3cc: 015cfab3 and s5,s9,s5 -8000a3d0: 02012423 sw zero,40(sp) -8000a3d4: 02012223 sw zero,36(sp) -8000a3d8: 00012e23 sw zero,28(sp) -8000a3dc: 05812783 lw a5,88(sp) -8000a3e0: 00079463 bnez a5,8000a3e8 <_svfprintf_r+0x6fc> -8000a3e4: 0510106f j 8000bc34 <_svfprintf_r+0x1f48> -8000a3e8: 02d00793 li a5,45 -8000a3ec: 0cf103a3 sb a5,199(sp) -8000a3f0: 00000d93 li s11,0 -8000a3f4: 001a8a93 addi s5,s5,1 -8000a3f8: ad9ff06f j 80009ed0 <_svfprintf_r+0x1e4> -8000a3fc: 0e410613 addi a2,sp,228 -8000a400: 000c0593 mv a1,s8 -8000a404: 000d0513 mv a0,s10 -8000a408: 2e9040ef jal ra,8000eef0 <__ssprint_r> -8000a40c: 100510e3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000a410: 0ec12783 lw a5,236(sp) -8000a414: 10c10893 addi a7,sp,268 -8000a418: b11ff06f j 80009f28 <_svfprintf_r+0x23c> -8000a41c: 0e812683 lw a3,232(sp) -8000a420: 00178c93 addi s9,a5,1 -8000a424: 02012783 lw a5,32(sp) -8000a428: 00100613 li a2,1 -8000a42c: 0168a023 sw s6,0(a7) -8000a430: 00168493 addi s1,a3,1 -8000a434: 00888913 addi s2,a7,8 -8000a438: 36f658e3 bge a2,a5,8000afa8 <_svfprintf_r+0x12bc> -8000a43c: 00100793 li a5,1 -8000a440: 00f8a223 sw a5,4(a7) -8000a444: 0f912623 sw s9,236(sp) -8000a448: 0e912423 sw s1,232(sp) -8000a44c: 00700793 li a5,7 -8000a450: 4a97c0e3 blt a5,s1,8000b0f0 <_svfprintf_r+0x1404> -8000a454: 02c12783 lw a5,44(sp) -8000a458: 03012703 lw a4,48(sp) -8000a45c: 00148493 addi s1,s1,1 -8000a460: 00fc8cb3 add s9,s9,a5 -8000a464: 00f92223 sw a5,4(s2) -8000a468: 00e92023 sw a4,0(s2) -8000a46c: 0f912623 sw s9,236(sp) -8000a470: 0e912423 sw s1,232(sp) -8000a474: 00700793 li a5,7 -8000a478: 00890913 addi s2,s2,8 -8000a47c: 4897cce3 blt a5,s1,8000b114 <_svfprintf_r+0x1428> -8000a480: 0f012783 lw a5,240(sp) -8000a484: 00148613 addi a2,s1,1 -8000a488: 0a010593 addi a1,sp,160 -8000a48c: 0af12823 sw a5,176(sp) -8000a490: 0f412783 lw a5,244(sp) -8000a494: 0b010513 addi a0,sp,176 -8000a498: 00c12e23 sw a2,28(sp) -8000a49c: 0af12a23 sw a5,180(sp) -8000a4a0: 0f812783 lw a5,248(sp) -8000a4a4: 0a012023 sw zero,160(sp) -8000a4a8: 0a012223 sw zero,164(sp) -8000a4ac: 0af12c23 sw a5,184(sp) -8000a4b0: 0fc12783 lw a5,252(sp) -8000a4b4: 0a012423 sw zero,168(sp) -8000a4b8: 0a012623 sw zero,172(sp) -8000a4bc: 0af12e23 sw a5,188(sp) -8000a4c0: 428070ef jal ra,800118e8 <__eqtf2> -8000a4c4: 01c12603 lw a2,28(sp) -8000a4c8: 02012783 lw a5,32(sp) -8000a4cc: 00890893 addi a7,s2,8 -8000a4d0: 00060693 mv a3,a2 -8000a4d4: fff78d93 addi s11,a5,-1 -8000a4d8: 2e050ce3 beqz a0,8000afd0 <_svfprintf_r+0x12e4> -8000a4dc: 001b0713 addi a4,s6,1 -8000a4e0: 01bc8cb3 add s9,s9,s11 -8000a4e4: 00e92023 sw a4,0(s2) -8000a4e8: 01b92223 sw s11,4(s2) -8000a4ec: 0f912623 sw s9,236(sp) -8000a4f0: 0ec12423 sw a2,232(sp) -8000a4f4: 00700793 li a5,7 -8000a4f8: 00c7d463 bge a5,a2,8000a500 <_svfprintf_r+0x814> -8000a4fc: 0180106f j 8000b514 <_svfprintf_r+0x1828> -8000a500: 01090793 addi a5,s2,16 -8000a504: 00248693 addi a3,s1,2 -8000a508: 00088913 mv s2,a7 -8000a50c: 00078893 mv a7,a5 -8000a510: 03812603 lw a2,56(sp) -8000a514: 0d410713 addi a4,sp,212 -8000a518: 00e92023 sw a4,0(s2) -8000a51c: 019607b3 add a5,a2,s9 -8000a520: 00c92223 sw a2,4(s2) -8000a524: 0ef12623 sw a5,236(sp) -8000a528: 0ed12423 sw a3,232(sp) -8000a52c: 00700713 li a4,7 -8000a530: a6d756e3 bge a4,a3,80009f9c <_svfprintf_r+0x2b0> -8000a534: 0e410613 addi a2,sp,228 -8000a538: 000c0593 mv a1,s8 -8000a53c: 000d0513 mv a0,s10 -8000a540: 1b1040ef jal ra,8000eef0 <__ssprint_r> -8000a544: 7c051463 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000a548: 0ec12783 lw a5,236(sp) -8000a54c: 10c10893 addi a7,sp,268 -8000a550: a4dff06f j 80009f9c <_svfprintf_r+0x2b0> -8000a554: 01000693 li a3,16 -8000a558: 0e812703 lw a4,232(sp) -8000a55c: 0096c463 blt a3,s1,8000a564 <_svfprintf_r+0x878> -8000a560: 1210106f j 8000be80 <_svfprintf_r+0x2194> -8000a564: 800156b7 lui a3,0x80015 -8000a568: 30c68e93 addi t4,a3,780 # 8001530c <__BSS_END__+0xffffe6dc> -8000a56c: 01000913 li s2,16 -8000a570: 00700a13 li s4,7 -8000a574: 000e8b13 mv s6,t4 -8000a578: 00c0006f j 8000a584 <_svfprintf_r+0x898> -8000a57c: ff048493 addi s1,s1,-16 -8000a580: 04995663 bge s2,s1,8000a5cc <_svfprintf_r+0x8e0> -8000a584: 01078793 addi a5,a5,16 -8000a588: 00170713 addi a4,a4,1 -8000a58c: 0168a023 sw s6,0(a7) -8000a590: 0128a223 sw s2,4(a7) -8000a594: 0ef12623 sw a5,236(sp) -8000a598: 0ee12423 sw a4,232(sp) -8000a59c: 00888893 addi a7,a7,8 -8000a5a0: fcea5ee3 bge s4,a4,8000a57c <_svfprintf_r+0x890> -8000a5a4: 0e410613 addi a2,sp,228 -8000a5a8: 000c0593 mv a1,s8 -8000a5ac: 000d0513 mv a0,s10 -8000a5b0: 141040ef jal ra,8000eef0 <__ssprint_r> -8000a5b4: 74051c63 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000a5b8: ff048493 addi s1,s1,-16 -8000a5bc: 0ec12783 lw a5,236(sp) -8000a5c0: 0e812703 lw a4,232(sp) -8000a5c4: 10c10893 addi a7,sp,268 -8000a5c8: fa994ee3 blt s2,s1,8000a584 <_svfprintf_r+0x898> -8000a5cc: 000b0e93 mv t4,s6 -8000a5d0: 009787b3 add a5,a5,s1 -8000a5d4: 00170713 addi a4,a4,1 -8000a5d8: 01d8a023 sw t4,0(a7) -8000a5dc: 0098a223 sw s1,4(a7) -8000a5e0: 0ef12623 sw a5,236(sp) -8000a5e4: 0ee12423 sw a4,232(sp) -8000a5e8: 00700693 li a3,7 -8000a5ec: 9ce6d0e3 bge a3,a4,80009fac <_svfprintf_r+0x2c0> -8000a5f0: 0e410613 addi a2,sp,228 -8000a5f4: 000c0593 mv a1,s8 -8000a5f8: 000d0513 mv a0,s10 -8000a5fc: 0f5040ef jal ra,8000eef0 <__ssprint_r> -8000a600: 70051663 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000a604: 0ec12783 lw a5,236(sp) -8000a608: 9a5ff06f j 80009fac <_svfprintf_r+0x2c0> -8000a60c: 01412783 lw a5,20(sp) -8000a610: 0c0103a3 sb zero,199(sp) -8000a614: 000c8893 mv a7,s9 -8000a618: 0007ab03 lw s6,0(a5) -8000a61c: 00478913 addi s2,a5,4 -8000a620: 4e0b02e3 beqz s6,8000b304 <_svfprintf_r+0x1618> -8000a624: fff00793 li a5,-1 -8000a628: 00fd9463 bne s11,a5,8000a630 <_svfprintf_r+0x944> -8000a62c: 1fc0106f j 8000b828 <_svfprintf_r+0x1b3c> -8000a630: 000d8613 mv a2,s11 -8000a634: 00000593 li a1,0 -8000a638: 000b0513 mv a0,s6 -8000a63c: 01912a23 sw s9,20(sp) -8000a640: eb9fd0ef jal ra,800084f8 -8000a644: 00a12823 sw a0,16(sp) -8000a648: 01412883 lw a7,20(sp) -8000a64c: 00051463 bnez a0,8000a654 <_svfprintf_r+0x968> -8000a650: 75c0106f j 8000bdac <_svfprintf_r+0x20c0> -8000a654: 01012783 lw a5,16(sp) -8000a658: 01212a23 sw s2,20(sp) -8000a65c: 00012823 sw zero,16(sp) -8000a660: 41678cb3 sub s9,a5,s6 -8000a664: 0c714783 lbu a5,199(sp) -8000a668: fffcca93 not s5,s9 -8000a66c: 41fada93 srai s5,s5,0x1f -8000a670: 02012423 sw zero,40(sp) -8000a674: 02012223 sw zero,36(sp) -8000a678: 00012e23 sw zero,28(sp) -8000a67c: 015cfab3 and s5,s9,s5 -8000a680: 00000d93 li s11,0 -8000a684: 840786e3 beqz a5,80009ed0 <_svfprintf_r+0x1e4> -8000a688: 001a8a93 addi s5,s5,1 -8000a68c: 845ff06f j 80009ed0 <_svfprintf_r+0x1e4> -8000a690: 01412703 lw a4,20(sp) -8000a694: 000c8893 mv a7,s9 -8000a698: 0c0103a3 sb zero,199(sp) -8000a69c: 00072783 lw a5,0(a4) -8000a6a0: 00470713 addi a4,a4,4 -8000a6a4: 00e12a23 sw a4,20(sp) -8000a6a8: 14f10623 sb a5,332(sp) -8000a6ac: 00100a93 li s5,1 -8000a6b0: 00100c93 li s9,1 -8000a6b4: 14c10b13 addi s6,sp,332 -8000a6b8: 805ff06f j 80009ebc <_svfprintf_r+0x1d0> -8000a6bc: 00044483 lbu s1,0(s0) -8000a6c0: 004a6a13 ori s4,s4,4 -8000a6c4: f8cff06f j 80009e50 <_svfprintf_r+0x164> -8000a6c8: 01412683 lw a3,20(sp) -8000a6cc: 020a7793 andi a5,s4,32 -8000a6d0: 000c8893 mv a7,s9 -8000a6d4: 0006a703 lw a4,0(a3) -8000a6d8: 00468693 addi a3,a3,4 -8000a6dc: 00d12a23 sw a3,20(sp) -8000a6e0: 280790e3 bnez a5,8000b160 <_svfprintf_r+0x1474> -8000a6e4: 010a7793 andi a5,s4,16 -8000a6e8: 00078463 beqz a5,8000a6f0 <_svfprintf_r+0xa04> -8000a6ec: 12c0106f j 8000b818 <_svfprintf_r+0x1b2c> -8000a6f0: 040a7793 andi a5,s4,64 -8000a6f4: 00078463 beqz a5,8000a6fc <_svfprintf_r+0xa10> -8000a6f8: 3d80106f j 8000bad0 <_svfprintf_r+0x1de4> -8000a6fc: 200a7a13 andi s4,s4,512 -8000a700: 000a1463 bnez s4,8000a708 <_svfprintf_r+0xa1c> -8000a704: 1140106f j 8000b818 <_svfprintf_r+0x1b2c> -8000a708: 00c12783 lw a5,12(sp) -8000a70c: 00040b13 mv s6,s0 -8000a710: 00f70023 sb a5,0(a4) -8000a714: 8d1ff06f j 80009fe4 <_svfprintf_r+0x2f8> -8000a718: 00044483 lbu s1,0(s0) -8000a71c: 06c00793 li a5,108 -8000a720: 38f48ee3 beq s1,a5,8000b2bc <_svfprintf_r+0x15d0> -8000a724: 010a6a13 ori s4,s4,16 -8000a728: f28ff06f j 80009e50 <_svfprintf_r+0x164> -8000a72c: 01412703 lw a4,20(sp) -8000a730: ffff87b7 lui a5,0xffff8 -8000a734: 8307c793 xori a5,a5,-2000 -8000a738: 0cf11423 sh a5,200(sp) -8000a73c: 00470793 addi a5,a4,4 -8000a740: 00f12a23 sw a5,20(sp) -8000a744: 00072903 lw s2,0(a4) -8000a748: 800157b7 lui a5,0x80015 -8000a74c: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -8000a750: 000c8893 mv a7,s9 -8000a754: 02f12a23 sw a5,52(sp) -8000a758: 00000c93 li s9,0 -8000a75c: 002a6b93 ori s7,s4,2 -8000a760: 00200793 li a5,2 -8000a764: 07800493 li s1,120 -8000a768: 0c0103a3 sb zero,199(sp) -8000a76c: fff00713 li a4,-1 -8000a770: 20ed8663 beq s11,a4,8000a97c <_svfprintf_r+0xc90> -8000a774: 01996733 or a4,s2,s9 -8000a778: f7fbfa13 andi s4,s7,-129 -8000a77c: 1e071e63 bnez a4,8000a978 <_svfprintf_r+0xc8c> -8000a780: 260d9463 bnez s11,8000a9e8 <_svfprintf_r+0xcfc> -8000a784: 1c079063 bnez a5,8000a944 <_svfprintf_r+0xc58> -8000a788: 001bfc93 andi s9,s7,1 -8000a78c: 1b010b13 addi s6,sp,432 -8000a790: 1c0c90e3 bnez s9,8000b150 <_svfprintf_r+0x1464> -8000a794: 000c8a93 mv s5,s9 -8000a798: 01bcd463 bge s9,s11,8000a7a0 <_svfprintf_r+0xab4> -8000a79c: 000d8a93 mv s5,s11 -8000a7a0: 0c714783 lbu a5,199(sp) -8000a7a4: 00012823 sw zero,16(sp) -8000a7a8: 02012423 sw zero,40(sp) -8000a7ac: 02012223 sw zero,36(sp) -8000a7b0: 00012e23 sw zero,28(sp) -8000a7b4: ec079ae3 bnez a5,8000a688 <_svfprintf_r+0x99c> -8000a7b8: f18ff06f j 80009ed0 <_svfprintf_r+0x1e4> -8000a7bc: 000c8893 mv a7,s9 -8000a7c0: 010a6a13 ori s4,s4,16 -8000a7c4: 020a7793 andi a5,s4,32 -8000a7c8: 06078ce3 beqz a5,8000b040 <_svfprintf_r+0x1354> -8000a7cc: 01412783 lw a5,20(sp) -8000a7d0: 00778b13 addi s6,a5,7 -8000a7d4: ff8b7b13 andi s6,s6,-8 -8000a7d8: 000b2903 lw s2,0(s6) -8000a7dc: 004b2c83 lw s9,4(s6) -8000a7e0: 008b0793 addi a5,s6,8 -8000a7e4: 00f12a23 sw a5,20(sp) -8000a7e8: bffa7b93 andi s7,s4,-1025 -8000a7ec: 00000793 li a5,0 -8000a7f0: f79ff06f j 8000a768 <_svfprintf_r+0xa7c> -8000a7f4: 00044483 lbu s1,0(s0) -8000a7f8: 06800793 li a5,104 -8000a7fc: 2cf488e3 beq s1,a5,8000b2cc <_svfprintf_r+0x15e0> -8000a800: 040a6a13 ori s4,s4,64 -8000a804: e4cff06f j 80009e50 <_svfprintf_r+0x164> -8000a808: 000c8893 mv a7,s9 -8000a80c: 010a6b93 ori s7,s4,16 -8000a810: 020bf793 andi a5,s7,32 -8000a814: 04078ce3 beqz a5,8000b06c <_svfprintf_r+0x1380> -8000a818: 01412783 lw a5,20(sp) -8000a81c: 00778b13 addi s6,a5,7 -8000a820: ff8b7b13 andi s6,s6,-8 -8000a824: 008b0793 addi a5,s6,8 -8000a828: 00f12a23 sw a5,20(sp) -8000a82c: 000b2903 lw s2,0(s6) -8000a830: 004b2c83 lw s9,4(s6) -8000a834: 00100793 li a5,1 -8000a838: f31ff06f j 8000a768 <_svfprintf_r+0xa7c> -8000a83c: 00044483 lbu s1,0(s0) -8000a840: 008a6a13 ori s4,s4,8 -8000a844: e0cff06f j 80009e50 <_svfprintf_r+0x164> -8000a848: 01412783 lw a5,20(sp) -8000a84c: 00044483 lbu s1,0(s0) -8000a850: 0007a983 lw s3,0(a5) -8000a854: 00478793 addi a5,a5,4 -8000a858: 00f12a23 sw a5,20(sp) -8000a85c: de09da63 bgez s3,80009e50 <_svfprintf_r+0x164> -8000a860: 413009b3 neg s3,s3 -8000a864: 004a6a13 ori s4,s4,4 -8000a868: de8ff06f j 80009e50 <_svfprintf_r+0x164> -8000a86c: 00044483 lbu s1,0(s0) -8000a870: 001a6a13 ori s4,s4,1 -8000a874: ddcff06f j 80009e50 <_svfprintf_r+0x164> -8000a878: 0c714783 lbu a5,199(sp) -8000a87c: 00044483 lbu s1,0(s0) -8000a880: dc079863 bnez a5,80009e50 <_svfprintf_r+0x164> -8000a884: 02000793 li a5,32 -8000a888: 0cf103a3 sb a5,199(sp) -8000a88c: dc4ff06f j 80009e50 <_svfprintf_r+0x164> -8000a890: 00044483 lbu s1,0(s0) -8000a894: 080a6a13 ori s4,s4,128 -8000a898: db8ff06f j 80009e50 <_svfprintf_r+0x164> -8000a89c: 00044483 lbu s1,0(s0) -8000a8a0: 00140713 addi a4,s0,1 -8000a8a4: 01749463 bne s1,s7,8000a8ac <_svfprintf_r+0xbc0> -8000a8a8: 5f50106f j 8000c69c <_svfprintf_r+0x29b0> -8000a8ac: fd048693 addi a3,s1,-48 -8000a8b0: 00070413 mv s0,a4 -8000a8b4: 00000d93 li s11,0 -8000a8b8: d8daee63 bltu s5,a3,80009e54 <_svfprintf_r+0x168> -8000a8bc: 00044483 lbu s1,0(s0) -8000a8c0: 002d9793 slli a5,s11,0x2 -8000a8c4: 01b787b3 add a5,a5,s11 -8000a8c8: 00179793 slli a5,a5,0x1 -8000a8cc: 00d78db3 add s11,a5,a3 -8000a8d0: fd048693 addi a3,s1,-48 -8000a8d4: 00140413 addi s0,s0,1 -8000a8d8: fedaf2e3 bgeu s5,a3,8000a8bc <_svfprintf_r+0xbd0> -8000a8dc: d78ff06f j 80009e54 <_svfprintf_r+0x168> -8000a8e0: 02b00793 li a5,43 -8000a8e4: 00044483 lbu s1,0(s0) -8000a8e8: 0cf103a3 sb a5,199(sp) -8000a8ec: d64ff06f j 80009e50 <_svfprintf_r+0x164> -8000a8f0: 000c8893 mv a7,s9 -8000a8f4: 010a6a13 ori s4,s4,16 -8000a8f8: 020a7793 andi a5,s4,32 -8000a8fc: 7a078063 beqz a5,8000b09c <_svfprintf_r+0x13b0> -8000a900: 01412783 lw a5,20(sp) -8000a904: 00778b13 addi s6,a5,7 -8000a908: ff8b7b13 andi s6,s6,-8 -8000a90c: 004b2783 lw a5,4(s6) -8000a910: 000b2903 lw s2,0(s6) -8000a914: 008b0713 addi a4,s6,8 -8000a918: 00e12a23 sw a4,20(sp) -8000a91c: 00078c93 mv s9,a5 -8000a920: 7a07c663 bltz a5,8000b0cc <_svfprintf_r+0x13e0> -8000a924: fff00793 li a5,-1 -8000a928: 000a0b93 mv s7,s4 -8000a92c: 02fd8463 beq s11,a5,8000a954 <_svfprintf_r+0xc68> -8000a930: 019967b3 or a5,s2,s9 -8000a934: f7fa7b93 andi s7,s4,-129 -8000a938: 00079e63 bnez a5,8000a954 <_svfprintf_r+0xc68> -8000a93c: 020d9263 bnez s11,8000a960 <_svfprintf_r+0xc74> -8000a940: 000b8a13 mv s4,s7 -8000a944: 00000d93 li s11,0 -8000a948: 00000c93 li s9,0 -8000a94c: 1b010b13 addi s6,sp,432 -8000a950: e45ff06f j 8000a794 <_svfprintf_r+0xaa8> -8000a954: 400c96e3 bnez s9,8000b560 <_svfprintf_r+0x1874> -8000a958: 00900793 li a5,9 -8000a95c: 4127e2e3 bltu a5,s2,8000b560 <_svfprintf_r+0x1874> -8000a960: 03090913 addi s2,s2,48 -8000a964: 1b2107a3 sb s2,431(sp) -8000a968: 000b8a13 mv s4,s7 -8000a96c: 00100c93 li s9,1 -8000a970: 1af10b13 addi s6,sp,431 -8000a974: e21ff06f j 8000a794 <_svfprintf_r+0xaa8> -8000a978: 000a0b93 mv s7,s4 -8000a97c: 00100713 li a4,1 -8000a980: fce78ae3 beq a5,a4,8000a954 <_svfprintf_r+0xc68> -8000a984: 00200713 li a4,2 -8000a988: 06e78c63 beq a5,a4,8000aa00 <_svfprintf_r+0xd14> -8000a98c: 1b010b13 addi s6,sp,432 -8000a990: 01dc9713 slli a4,s9,0x1d -8000a994: 00797793 andi a5,s2,7 -8000a998: 00395913 srli s2,s2,0x3 -8000a99c: 03078793 addi a5,a5,48 -8000a9a0: 01276933 or s2,a4,s2 -8000a9a4: 003cdc93 srli s9,s9,0x3 -8000a9a8: fefb0fa3 sb a5,-1(s6) -8000a9ac: 01996733 or a4,s2,s9 -8000a9b0: 000b0613 mv a2,s6 -8000a9b4: fffb0b13 addi s6,s6,-1 -8000a9b8: fc071ce3 bnez a4,8000a990 <_svfprintf_r+0xca4> -8000a9bc: 001bf693 andi a3,s7,1 -8000a9c0: 06068a63 beqz a3,8000aa34 <_svfprintf_r+0xd48> -8000a9c4: 03000693 li a3,48 -8000a9c8: 06d78663 beq a5,a3,8000aa34 <_svfprintf_r+0xd48> -8000a9cc: ffe60613 addi a2,a2,-2 -8000a9d0: 1b010793 addi a5,sp,432 -8000a9d4: fedb0fa3 sb a3,-1(s6) -8000a9d8: 40c78cb3 sub s9,a5,a2 -8000a9dc: 000b8a13 mv s4,s7 -8000a9e0: 00060b13 mv s6,a2 -8000a9e4: db1ff06f j 8000a794 <_svfprintf_r+0xaa8> -8000a9e8: 00100713 li a4,1 -8000a9ec: 00e79463 bne a5,a4,8000a9f4 <_svfprintf_r+0xd08> -8000a9f0: 1710106f j 8000c360 <_svfprintf_r+0x2674> -8000a9f4: 00200713 li a4,2 -8000a9f8: 000a0b93 mv s7,s4 -8000a9fc: f8e798e3 bne a5,a4,8000a98c <_svfprintf_r+0xca0> -8000aa00: 03412683 lw a3,52(sp) -8000aa04: 1b010b13 addi s6,sp,432 -8000aa08: 00f97793 andi a5,s2,15 -8000aa0c: 00f687b3 add a5,a3,a5 -8000aa10: 0007c703 lbu a4,0(a5) -8000aa14: 00495913 srli s2,s2,0x4 -8000aa18: 01cc9793 slli a5,s9,0x1c -8000aa1c: 0127e933 or s2,a5,s2 -8000aa20: 004cdc93 srli s9,s9,0x4 -8000aa24: feeb0fa3 sb a4,-1(s6) -8000aa28: 019967b3 or a5,s2,s9 -8000aa2c: fffb0b13 addi s6,s6,-1 -8000aa30: fc079ce3 bnez a5,8000aa08 <_svfprintf_r+0xd1c> -8000aa34: 1b010793 addi a5,sp,432 -8000aa38: 41678cb3 sub s9,a5,s6 -8000aa3c: 000b8a13 mv s4,s7 -8000aa40: d55ff06f j 8000a794 <_svfprintf_r+0xaa8> -8000aa44: 06500693 li a3,101 -8000aa48: 9c96dae3 bge a3,s1,8000a41c <_svfprintf_r+0x730> -8000aa4c: 0f012683 lw a3,240(sp) -8000aa50: 0a010593 addi a1,sp,160 -8000aa54: 0b010513 addi a0,sp,176 -8000aa58: 0ad12823 sw a3,176(sp) -8000aa5c: 0f412683 lw a3,244(sp) -8000aa60: 05112223 sw a7,68(sp) -8000aa64: 04f12023 sw a5,64(sp) -8000aa68: 0ad12a23 sw a3,180(sp) -8000aa6c: 0f812683 lw a3,248(sp) -8000aa70: 0a012023 sw zero,160(sp) -8000aa74: 0a012223 sw zero,164(sp) -8000aa78: 0ad12c23 sw a3,184(sp) -8000aa7c: 0fc12683 lw a3,252(sp) -8000aa80: 0a012423 sw zero,168(sp) -8000aa84: 0a012623 sw zero,172(sp) -8000aa88: 0ad12e23 sw a3,188(sp) -8000aa8c: 65d060ef jal ra,800118e8 <__eqtf2> -8000aa90: 04012783 lw a5,64(sp) -8000aa94: 04412883 lw a7,68(sp) -8000aa98: 38051c63 bnez a0,8000ae30 <_svfprintf_r+0x1144> -8000aa9c: 0e812703 lw a4,232(sp) -8000aaa0: 800156b7 lui a3,0x80015 -8000aaa4: c5c68693 addi a3,a3,-932 # 80014c5c <__BSS_END__+0xffffe02c> -8000aaa8: 00d8a023 sw a3,0(a7) -8000aaac: 00178793 addi a5,a5,1 -8000aab0: 00100693 li a3,1 -8000aab4: 00170713 addi a4,a4,1 -8000aab8: 00d8a223 sw a3,4(a7) -8000aabc: 0ef12623 sw a5,236(sp) -8000aac0: 0ee12423 sw a4,232(sp) -8000aac4: 00700693 li a3,7 -8000aac8: 00888893 addi a7,a7,8 -8000aacc: 44e6cce3 blt a3,a4,8000b724 <_svfprintf_r+0x1a38> -8000aad0: 0cc12703 lw a4,204(sp) -8000aad4: 02012683 lw a3,32(sp) -8000aad8: 66d75063 bge a4,a3,8000b138 <_svfprintf_r+0x144c> -8000aadc: 03012703 lw a4,48(sp) -8000aae0: 02c12683 lw a3,44(sp) -8000aae4: 00888893 addi a7,a7,8 -8000aae8: fee8ac23 sw a4,-8(a7) -8000aaec: 0e812703 lw a4,232(sp) -8000aaf0: 00d787b3 add a5,a5,a3 -8000aaf4: fed8ae23 sw a3,-4(a7) -8000aaf8: 00170713 addi a4,a4,1 -8000aafc: 0ef12623 sw a5,236(sp) -8000ab00: 0ee12423 sw a4,232(sp) -8000ab04: 00700693 li a3,7 -8000ab08: 76e6cc63 blt a3,a4,8000b280 <_svfprintf_r+0x1594> -8000ab0c: 02012703 lw a4,32(sp) -8000ab10: fff70493 addi s1,a4,-1 -8000ab14: c8905463 blez s1,80009f9c <_svfprintf_r+0x2b0> -8000ab18: 01000693 li a3,16 -8000ab1c: 0e812703 lw a4,232(sp) -8000ab20: 4296d2e3 bge a3,s1,8000b744 <_svfprintf_r+0x1a58> -8000ab24: 01000913 li s2,16 -8000ab28: 00700c93 li s9,7 -8000ab2c: 00c0006f j 8000ab38 <_svfprintf_r+0xe4c> -8000ab30: ff048493 addi s1,s1,-16 -8000ab34: 409958e3 bge s2,s1,8000b744 <_svfprintf_r+0x1a58> -8000ab38: 00812683 lw a3,8(sp) -8000ab3c: 01078793 addi a5,a5,16 -8000ab40: 00170713 addi a4,a4,1 -8000ab44: 00d8a023 sw a3,0(a7) -8000ab48: 0128a223 sw s2,4(a7) -8000ab4c: 0ef12623 sw a5,236(sp) -8000ab50: 0ee12423 sw a4,232(sp) -8000ab54: 00888893 addi a7,a7,8 -8000ab58: fcecdce3 bge s9,a4,8000ab30 <_svfprintf_r+0xe44> -8000ab5c: 0e410613 addi a2,sp,228 -8000ab60: 000c0593 mv a1,s8 -8000ab64: 000d0513 mv a0,s10 -8000ab68: 388040ef jal ra,8000eef0 <__ssprint_r> -8000ab6c: 1a051063 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000ab70: 0ec12783 lw a5,236(sp) -8000ab74: 0e812703 lw a4,232(sp) -8000ab78: 10c10893 addi a7,sp,268 -8000ab7c: fb5ff06f j 8000ab30 <_svfprintf_r+0xe44> -8000ab80: 41598933 sub s2,s3,s5 -8000ab84: bf205063 blez s2,80009f64 <_svfprintf_r+0x278> -8000ab88: 01000613 li a2,16 -8000ab8c: 0e812683 lw a3,232(sp) -8000ab90: 07265463 bge a2,s2,8000abf8 <_svfprintf_r+0xf0c> -8000ab94: 01000e13 li t3,16 -8000ab98: 00700b93 li s7,7 -8000ab9c: 00c0006f j 8000aba8 <_svfprintf_r+0xebc> -8000aba0: ff090913 addi s2,s2,-16 -8000aba4: 052e5a63 bge t3,s2,8000abf8 <_svfprintf_r+0xf0c> -8000aba8: 00812703 lw a4,8(sp) -8000abac: 01078793 addi a5,a5,16 -8000abb0: 00168693 addi a3,a3,1 -8000abb4: 00e8a023 sw a4,0(a7) -8000abb8: 01c8a223 sw t3,4(a7) -8000abbc: 0ef12623 sw a5,236(sp) -8000abc0: 0ed12423 sw a3,232(sp) -8000abc4: 00888893 addi a7,a7,8 -8000abc8: fcdbdce3 bge s7,a3,8000aba0 <_svfprintf_r+0xeb4> -8000abcc: 0e410613 addi a2,sp,228 -8000abd0: 000c0593 mv a1,s8 -8000abd4: 000d0513 mv a0,s10 -8000abd8: 318040ef jal ra,8000eef0 <__ssprint_r> -8000abdc: 12051863 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000abe0: 01000e13 li t3,16 -8000abe4: ff090913 addi s2,s2,-16 -8000abe8: 0ec12783 lw a5,236(sp) -8000abec: 0e812683 lw a3,232(sp) -8000abf0: 10c10893 addi a7,sp,268 -8000abf4: fb2e4ae3 blt t3,s2,8000aba8 <_svfprintf_r+0xebc> -8000abf8: 00812703 lw a4,8(sp) -8000abfc: 012787b3 add a5,a5,s2 +80009a94 <_svfprintf_r>: +80009a94: e1010113 addi sp,sp,-496 +80009a98: 1e112623 sw ra,492(sp) +80009a9c: 1f212023 sw s2,480(sp) +80009aa0: 1d812423 sw s8,456(sp) +80009aa4: 1da12023 sw s10,448(sp) +80009aa8: 00058c13 mv s8,a1 +80009aac: 00060913 mv s2,a2 +80009ab0: 00d12a23 sw a3,20(sp) +80009ab4: 1e812423 sw s0,488(sp) +80009ab8: 1e912223 sw s1,484(sp) +80009abc: 1d312e23 sw s3,476(sp) +80009ac0: 1d412c23 sw s4,472(sp) +80009ac4: 1d512a23 sw s5,468(sp) +80009ac8: 1d612823 sw s6,464(sp) +80009acc: 1d712623 sw s7,460(sp) +80009ad0: 1d912223 sw s9,452(sp) +80009ad4: 1bb12e23 sw s11,444(sp) +80009ad8: 00050d13 mv s10,a0 +80009adc: ecdfd0ef jal ra,800079a8 <_localeconv_r> +80009ae0: 00052783 lw a5,0(a0) +80009ae4: 00078513 mv a0,a5 +80009ae8: 02f12823 sw a5,48(sp) +80009aec: e75ff0ef jal ra,80009960 +80009af0: 00cc5703 lhu a4,12(s8) +80009af4: 0e012823 sw zero,240(sp) +80009af8: 0e012a23 sw zero,244(sp) +80009afc: 0e012c23 sw zero,248(sp) +80009b00: 0e012e23 sw zero,252(sp) +80009b04: 08077713 andi a4,a4,128 +80009b08: 02a12623 sw a0,44(sp) +80009b0c: 00070863 beqz a4,80009b1c <_svfprintf_r+0x88> +80009b10: 010c2703 lw a4,16(s8) +80009b14: 00071463 bnez a4,80009b1c <_svfprintf_r+0x88> +80009b18: 56c0106f j 8000b084 <_svfprintf_r+0x15f0> +80009b1c: 10c10793 addi a5,sp,268 +80009b20: 80015737 lui a4,0x80015 +80009b24: 0ef12223 sw a5,228(sp) +80009b28: 00078893 mv a7,a5 +80009b2c: 1e070793 addi a5,a4,480 # 800151e0 <__BSS_END__+0xffffe5a4> +80009b30: 80015737 lui a4,0x80015 +80009b34: 00f12c23 sw a5,24(sp) +80009b38: 00090b13 mv s6,s2 +80009b3c: 35c70793 addi a5,a4,860 # 8001535c <__BSS_END__+0xffffe720> +80009b40: 00f12423 sw a5,8(sp) +80009b44: 000b4783 lbu a5,0(s6) +80009b48: 0e012623 sw zero,236(sp) +80009b4c: 0e012423 sw zero,232(sp) +80009b50: 02012023 sw zero,32(sp) +80009b54: 02012a23 sw zero,52(sp) +80009b58: 02012c23 sw zero,56(sp) +80009b5c: 02012e23 sw zero,60(sp) +80009b60: 04012423 sw zero,72(sp) +80009b64: 04012623 sw zero,76(sp) +80009b68: 00012623 sw zero,12(sp) +80009b6c: 22078463 beqz a5,80009d94 <_svfprintf_r+0x300> +80009b70: 000b0413 mv s0,s6 +80009b74: 02500693 li a3,37 +80009b78: 2cd78463 beq a5,a3,80009e40 <_svfprintf_r+0x3ac> +80009b7c: 00144783 lbu a5,1(s0) +80009b80: 00140413 addi s0,s0,1 +80009b84: fe079ae3 bnez a5,80009b78 <_svfprintf_r+0xe4> +80009b88: 416404b3 sub s1,s0,s6 +80009b8c: 21640463 beq s0,s6,80009d94 <_svfprintf_r+0x300> +80009b90: 0ec12683 lw a3,236(sp) +80009b94: 0e812783 lw a5,232(sp) +80009b98: 0168a023 sw s6,0(a7) +80009b9c: 009686b3 add a3,a3,s1 +80009ba0: 00178793 addi a5,a5,1 +80009ba4: 0098a223 sw s1,4(a7) +80009ba8: 0ed12623 sw a3,236(sp) +80009bac: 0ef12423 sw a5,232(sp) +80009bb0: 00700693 li a3,7 +80009bb4: 00888893 addi a7,a7,8 +80009bb8: 28f6cc63 blt a3,a5,80009e50 <_svfprintf_r+0x3bc> +80009bbc: 00c12703 lw a4,12(sp) +80009bc0: 00044783 lbu a5,0(s0) +80009bc4: 00970733 add a4,a4,s1 +80009bc8: 00e12623 sw a4,12(sp) +80009bcc: 1c078463 beqz a5,80009d94 <_svfprintf_r+0x300> +80009bd0: 00144483 lbu s1,1(s0) +80009bd4: 0c0103a3 sb zero,199(sp) +80009bd8: 00140413 addi s0,s0,1 +80009bdc: fff00d93 li s11,-1 +80009be0: 00000993 li s3,0 +80009be4: 00000a13 li s4,0 +80009be8: 05a00913 li s2,90 +80009bec: 00900a93 li s5,9 +80009bf0: 02a00b93 li s7,42 +80009bf4: 00088c93 mv s9,a7 +80009bf8: 00140413 addi s0,s0,1 +80009bfc: fe048793 addi a5,s1,-32 # 7fffffe0 <__BSS_END__+0xfffe93a4> +80009c00: 04f96463 bltu s2,a5,80009c48 <_svfprintf_r+0x1b4> +80009c04: 01812703 lw a4,24(sp) +80009c08: 00279793 slli a5,a5,0x2 +80009c0c: 00e787b3 add a5,a5,a4 +80009c10: 0007a783 lw a5,0(a5) +80009c14: 00078067 jr a5 +80009c18: 00000993 li s3,0 +80009c1c: fd048693 addi a3,s1,-48 +80009c20: 00044483 lbu s1,0(s0) +80009c24: 00299793 slli a5,s3,0x2 +80009c28: 013787b3 add a5,a5,s3 +80009c2c: 00179793 slli a5,a5,0x1 +80009c30: 00f689b3 add s3,a3,a5 +80009c34: fd048693 addi a3,s1,-48 +80009c38: 00140413 addi s0,s0,1 +80009c3c: fedaf2e3 bgeu s5,a3,80009c20 <_svfprintf_r+0x18c> +80009c40: fe048793 addi a5,s1,-32 +80009c44: fcf970e3 bgeu s2,a5,80009c04 <_svfprintf_r+0x170> +80009c48: 000c8893 mv a7,s9 +80009c4c: 14048463 beqz s1,80009d94 <_svfprintf_r+0x300> +80009c50: 14910623 sb s1,332(sp) +80009c54: 0c0103a3 sb zero,199(sp) +80009c58: 00100a93 li s5,1 +80009c5c: 00100c93 li s9,1 +80009c60: 14c10b13 addi s6,sp,332 +80009c64: 00012823 sw zero,16(sp) +80009c68: 00000d93 li s11,0 +80009c6c: 02012423 sw zero,40(sp) +80009c70: 02012223 sw zero,36(sp) +80009c74: 00012e23 sw zero,28(sp) +80009c78: 002a7b93 andi s7,s4,2 +80009c7c: 000b8463 beqz s7,80009c84 <_svfprintf_r+0x1f0> +80009c80: 002a8a93 addi s5,s5,2 +80009c84: 084a7913 andi s2,s4,132 +80009c88: 0ec12783 lw a5,236(sp) +80009c8c: 00091663 bnez s2,80009c98 <_svfprintf_r+0x204> +80009c90: 41598833 sub a6,s3,s5 +80009c94: 63004ce3 bgtz a6,8000aacc <_svfprintf_r+0x1038> +80009c98: 0c714683 lbu a3,199(sp) +80009c9c: 02068a63 beqz a3,80009cd0 <_svfprintf_r+0x23c> +80009ca0: 0e812683 lw a3,232(sp) +80009ca4: 0c710613 addi a2,sp,199 +80009ca8: 00c8a023 sw a2,0(a7) +80009cac: 00178793 addi a5,a5,1 +80009cb0: 00100613 li a2,1 +80009cb4: 00168693 addi a3,a3,1 +80009cb8: 00c8a223 sw a2,4(a7) +80009cbc: 0ef12623 sw a5,236(sp) +80009cc0: 0ed12423 sw a3,232(sp) +80009cc4: 00700613 li a2,7 +80009cc8: 00888893 addi a7,a7,8 +80009ccc: 4cd64c63 blt a2,a3,8000a1a4 <_svfprintf_r+0x710> +80009cd0: 020b8a63 beqz s7,80009d04 <_svfprintf_r+0x270> +80009cd4: 0e812683 lw a3,232(sp) +80009cd8: 0c810613 addi a2,sp,200 +80009cdc: 00c8a023 sw a2,0(a7) +80009ce0: 00278793 addi a5,a5,2 +80009ce4: 00200613 li a2,2 +80009ce8: 00168693 addi a3,a3,1 +80009cec: 00c8a223 sw a2,4(a7) +80009cf0: 0ef12623 sw a5,236(sp) +80009cf4: 0ed12423 sw a3,232(sp) +80009cf8: 00700613 li a2,7 +80009cfc: 00888893 addi a7,a7,8 +80009d00: 6ad64ce3 blt a2,a3,8000abb8 <_svfprintf_r+0x1124> +80009d04: 08000693 li a3,128 +80009d08: 42d900e3 beq s2,a3,8000a928 <_svfprintf_r+0xe94> +80009d0c: 419d8db3 sub s11,s11,s9 +80009d10: 4db04ee3 bgtz s11,8000a9ec <_svfprintf_r+0xf58> +80009d14: 100a7693 andi a3,s4,256 +80009d18: 2c069ae3 bnez a3,8000a7ec <_svfprintf_r+0xd58> +80009d1c: 0e812703 lw a4,232(sp) +80009d20: 019787b3 add a5,a5,s9 +80009d24: 0168a023 sw s6,0(a7) +80009d28: 00170713 addi a4,a4,1 +80009d2c: 0198a223 sw s9,4(a7) +80009d30: 0ef12623 sw a5,236(sp) +80009d34: 0ee12423 sw a4,232(sp) +80009d38: 00700693 li a3,7 +80009d3c: 5ae6c063 blt a3,a4,8000a2dc <_svfprintf_r+0x848> +80009d40: 00888893 addi a7,a7,8 +80009d44: 004a7a13 andi s4,s4,4 +80009d48: 000a0663 beqz s4,80009d54 <_svfprintf_r+0x2c0> +80009d4c: 415984b3 sub s1,s3,s5 +80009d50: 5a904663 bgtz s1,8000a2fc <_svfprintf_r+0x868> +80009d54: 0159d463 bge s3,s5,80009d5c <_svfprintf_r+0x2c8> +80009d58: 000a8993 mv s3,s5 +80009d5c: 00c12703 lw a4,12(sp) +80009d60: 01370733 add a4,a4,s3 +80009d64: 00e12623 sw a4,12(sp) +80009d68: 52079ce3 bnez a5,8000aaa0 <_svfprintf_r+0x100c> +80009d6c: 01012783 lw a5,16(sp) +80009d70: 0e012423 sw zero,232(sp) +80009d74: 00078863 beqz a5,80009d84 <_svfprintf_r+0x2f0> +80009d78: 01012583 lw a1,16(sp) +80009d7c: 000d0513 mv a0,s10 +80009d80: c55fa0ef jal ra,800049d4 <_free_r> +80009d84: 10c10893 addi a7,sp,268 +80009d88: 00040b13 mv s6,s0 +80009d8c: 000b4783 lbu a5,0(s6) +80009d90: de0790e3 bnez a5,80009b70 <_svfprintf_r+0xdc> +80009d94: 0ec12783 lw a5,236(sp) +80009d98: 00078463 beqz a5,80009da0 <_svfprintf_r+0x30c> +80009d9c: 3450106f j 8000b8e0 <_svfprintf_r+0x1e4c> +80009da0: 00cc5703 lhu a4,12(s8) +80009da4: 04077713 andi a4,a4,64 +80009da8: 00070463 beqz a4,80009db0 <_svfprintf_r+0x31c> +80009dac: 3f80206f j 8000c1a4 <_svfprintf_r+0x2710> +80009db0: 1ec12083 lw ra,492(sp) +80009db4: 1e812403 lw s0,488(sp) +80009db8: 00c12503 lw a0,12(sp) +80009dbc: 1e412483 lw s1,484(sp) +80009dc0: 1e012903 lw s2,480(sp) +80009dc4: 1dc12983 lw s3,476(sp) +80009dc8: 1d812a03 lw s4,472(sp) +80009dcc: 1d412a83 lw s5,468(sp) +80009dd0: 1d012b03 lw s6,464(sp) +80009dd4: 1cc12b83 lw s7,460(sp) +80009dd8: 1c812c03 lw s8,456(sp) +80009ddc: 1c412c83 lw s9,452(sp) +80009de0: 1c012d03 lw s10,448(sp) +80009de4: 1bc12d83 lw s11,444(sp) +80009de8: 1f010113 addi sp,sp,496 +80009dec: 00008067 ret +80009df0: 000d0513 mv a0,s10 +80009df4: bb5fd0ef jal ra,800079a8 <_localeconv_r> +80009df8: 00452783 lw a5,4(a0) +80009dfc: 00078513 mv a0,a5 +80009e00: 04f12623 sw a5,76(sp) +80009e04: b5dff0ef jal ra,80009960 +80009e08: 00050793 mv a5,a0 +80009e0c: 000d0513 mv a0,s10 +80009e10: 00078493 mv s1,a5 +80009e14: 04f12423 sw a5,72(sp) +80009e18: b91fd0ef jal ra,800079a8 <_localeconv_r> +80009e1c: 00852783 lw a5,8(a0) +80009e20: 02f12e23 sw a5,60(sp) +80009e24: 00048463 beqz s1,80009e2c <_svfprintf_r+0x398> +80009e28: 1640106f j 8000af8c <_svfprintf_r+0x14f8> +80009e2c: 00044483 lbu s1,0(s0) +80009e30: dc9ff06f j 80009bf8 <_svfprintf_r+0x164> +80009e34: 00044483 lbu s1,0(s0) +80009e38: 020a6a13 ori s4,s4,32 +80009e3c: dbdff06f j 80009bf8 <_svfprintf_r+0x164> +80009e40: 416404b3 sub s1,s0,s6 +80009e44: d56416e3 bne s0,s6,80009b90 <_svfprintf_r+0xfc> +80009e48: 00044783 lbu a5,0(s0) +80009e4c: d81ff06f j 80009bcc <_svfprintf_r+0x138> +80009e50: 0e410613 addi a2,sp,228 +80009e54: 000c0593 mv a1,s8 +80009e58: 000d0513 mv a0,s10 +80009e5c: 120050ef jal ra,8000ef7c <__ssprint_r> +80009e60: f40510e3 bnez a0,80009da0 <_svfprintf_r+0x30c> +80009e64: 10c10893 addi a7,sp,268 +80009e68: d55ff06f j 80009bbc <_svfprintf_r+0x128> +80009e6c: 008a7793 andi a5,s4,8 +80009e70: 000c8893 mv a7,s9 +80009e74: 00078463 beqz a5,80009e7c <_svfprintf_r+0x3e8> +80009e78: 0a80106f j 8000af20 <_svfprintf_r+0x148c> +80009e7c: 01412783 lw a5,20(sp) +80009e80: 0b010513 addi a0,sp,176 +80009e84: 01912823 sw s9,16(sp) +80009e88: 00778793 addi a5,a5,7 +80009e8c: ff87f793 andi a5,a5,-8 +80009e90: 0007a583 lw a1,0(a5) +80009e94: 0047a603 lw a2,4(a5) +80009e98: 00878793 addi a5,a5,8 +80009e9c: 00f12a23 sw a5,20(sp) +80009ea0: 5e80a0ef jal ra,80014488 <__extenddftf2> +80009ea4: 0b012783 lw a5,176(sp) +80009ea8: 01012883 lw a7,16(sp) +80009eac: 0ef12823 sw a5,240(sp) +80009eb0: 0b412783 lw a5,180(sp) +80009eb4: 0ef12a23 sw a5,244(sp) +80009eb8: 0b812783 lw a5,184(sp) +80009ebc: 0ef12c23 sw a5,248(sp) +80009ec0: 0bc12783 lw a5,188(sp) +80009ec4: 0ef12e23 sw a5,252(sp) +80009ec8: 0f010513 addi a0,sp,240 +80009ecc: 01112823 sw a7,16(sp) +80009ed0: a6dfd0ef jal ra,8000793c <_ldcheck> +80009ed4: 0ca12623 sw a0,204(sp) +80009ed8: 00200793 li a5,2 +80009edc: 01012883 lw a7,16(sp) +80009ee0: 00f51463 bne a0,a5,80009ee8 <_svfprintf_r+0x454> +80009ee4: 6580106f j 8000b53c <_svfprintf_r+0x1aa8> +80009ee8: 00100793 li a5,1 +80009eec: 00f51463 bne a0,a5,80009ef4 <_svfprintf_r+0x460> +80009ef0: 0750106f j 8000b764 <_svfprintf_r+0x1cd0> +80009ef4: 06100793 li a5,97 +80009ef8: 00f49463 bne s1,a5,80009f00 <_svfprintf_r+0x46c> +80009efc: 19c0206f j 8000c098 <_svfprintf_r+0x2604> +80009f00: 04100793 li a5,65 +80009f04: 00f49463 bne s1,a5,80009f0c <_svfprintf_r+0x478> +80009f08: 52d0106f j 8000bc34 <_svfprintf_r+0x21a0> +80009f0c: fdf4fb93 andi s7,s1,-33 +80009f10: fff00793 li a5,-1 +80009f14: 05712a23 sw s7,84(sp) +80009f18: 00fd9463 bne s11,a5,80009f20 <_svfprintf_r+0x48c> +80009f1c: 2150106f j 8000b930 <_svfprintf_r+0x1e9c> +80009f20: 04700793 li a5,71 +80009f24: 00fb9463 bne s7,a5,80009f2c <_svfprintf_r+0x498> +80009f28: 1e80206f j 8000c110 <_svfprintf_r+0x267c> +80009f2c: 0fc12303 lw t1,252(sp) +80009f30: 03412423 sw s4,40(sp) +80009f34: 0f012e03 lw t3,240(sp) +80009f38: 0f412e83 lw t4,244(sp) +80009f3c: 0f812f03 lw t5,248(sp) +80009f40: 100a6793 ori a5,s4,256 +80009f44: 00035463 bgez t1,80009f4c <_svfprintf_r+0x4b8> +80009f48: 39c0206f j 8000c2e4 <_svfprintf_r+0x2850> +80009f4c: 04012c23 sw zero,88(sp) +80009f50: 00078a13 mv s4,a5 +80009f54: 00012823 sw zero,16(sp) +80009f58: 04600793 li a5,70 +80009f5c: 00fb9463 bne s7,a5,80009f64 <_svfprintf_r+0x4d0> +80009f60: 2b90106f j 8000ba18 <_svfprintf_r+0x1f84> +80009f64: 04500793 li a5,69 +80009f68: 05112223 sw a7,68(sp) +80009f6c: 00fb8463 beq s7,a5,80009f74 <_svfprintf_r+0x4e0> +80009f70: 33d0106f j 8000baac <_svfprintf_r+0x2018> +80009f74: 001d8913 addi s2,s11,1 +80009f78: 0b010a93 addi s5,sp,176 +80009f7c: 00090693 mv a3,s2 +80009f80: 0dc10813 addi a6,sp,220 +80009f84: 0d010793 addi a5,sp,208 +80009f88: 0cc10713 addi a4,sp,204 +80009f8c: 00200613 li a2,2 +80009f90: 000a8593 mv a1,s5 +80009f94: 000d0513 mv a0,s10 +80009f98: 0bc12823 sw t3,176(sp) +80009f9c: 05c12023 sw t3,64(sp) +80009fa0: 0bd12a23 sw t4,180(sp) +80009fa4: 03d12223 sw t4,36(sp) +80009fa8: 0be12c23 sw t5,184(sp) +80009fac: 03e12023 sw t5,32(sp) +80009fb0: 0a612e23 sw t1,188(sp) +80009fb4: 00612e23 sw t1,28(sp) +80009fb8: eecfc0ef jal ra,800066a4 <_ldtoa_r> +80009fbc: 01c12303 lw t1,28(sp) +80009fc0: 02012f03 lw t5,32(sp) +80009fc4: 02412e83 lw t4,36(sp) +80009fc8: 04012e03 lw t3,64(sp) +80009fcc: 04412883 lw a7,68(sp) +80009fd0: 00050b13 mv s6,a0 +80009fd4: 01250933 add s2,a0,s2 +80009fd8: 0a010c93 addi s9,sp,160 +80009fdc: 000c8593 mv a1,s9 +80009fe0: 000a8513 mv a0,s5 +80009fe4: 01112e23 sw a7,28(sp) +80009fe8: 0bc12823 sw t3,176(sp) +80009fec: 0bd12a23 sw t4,180(sp) +80009ff0: 0be12c23 sw t5,184(sp) +80009ff4: 0a612e23 sw t1,188(sp) +80009ff8: 0a012023 sw zero,160(sp) +80009ffc: 0a012223 sw zero,164(sp) +8000a000: 0a012423 sw zero,168(sp) +8000a004: 0a012623 sw zero,172(sp) +8000a008: 1a5070ef jal ra,800119ac <__eqtf2> +8000a00c: 01c12883 lw a7,28(sp) +8000a010: 00090713 mv a4,s2 +8000a014: 02050263 beqz a0,8000a038 <_svfprintf_r+0x5a4> +8000a018: 0dc12703 lw a4,220(sp) +8000a01c: 01277e63 bgeu a4,s2,8000a038 <_svfprintf_r+0x5a4> +8000a020: 03000693 li a3,48 +8000a024: 00170793 addi a5,a4,1 +8000a028: 0cf12e23 sw a5,220(sp) +8000a02c: 00d70023 sb a3,0(a4) +8000a030: 0dc12703 lw a4,220(sp) +8000a034: ff2768e3 bltu a4,s2,8000a024 <_svfprintf_r+0x590> +8000a038: 416707b3 sub a5,a4,s6 +8000a03c: 02f12023 sw a5,32(sp) +8000a040: 0cc12703 lw a4,204(sp) +8000a044: 04700793 li a5,71 +8000a048: 00e12e23 sw a4,28(sp) +8000a04c: 05412703 lw a4,84(sp) +8000a050: 00f71463 bne a4,a5,8000a058 <_svfprintf_r+0x5c4> +8000a054: 1150106f j 8000b968 <_svfprintf_r+0x1ed4> +8000a058: 05412703 lw a4,84(sp) +8000a05c: 04600793 li a5,70 +8000a060: 00f71463 bne a4,a5,8000a068 <_svfprintf_r+0x5d4> +8000a064: 34d0106f j 8000bbb0 <_svfprintf_r+0x211c> +8000a068: 01c12783 lw a5,28(sp) +8000a06c: 05412703 lw a4,84(sp) +8000a070: 04100593 li a1,65 +8000a074: fff78793 addi a5,a5,-1 +8000a078: 0cf12623 sw a5,204(sp) +8000a07c: 0ff4f693 andi a3,s1,255 +8000a080: 00000613 li a2,0 +8000a084: 00b71863 bne a4,a1,8000a094 <_svfprintf_r+0x600> +8000a088: 00f68693 addi a3,a3,15 +8000a08c: 0ff6f693 andi a3,a3,255 +8000a090: 00100613 li a2,1 +8000a094: 0cd10a23 sb a3,212(sp) +8000a098: 02b00693 li a3,43 +8000a09c: 0007da63 bgez a5,8000a0b0 <_svfprintf_r+0x61c> +8000a0a0: 01c12703 lw a4,28(sp) +8000a0a4: 00100793 li a5,1 +8000a0a8: 02d00693 li a3,45 +8000a0ac: 40e787b3 sub a5,a5,a4 +8000a0b0: 0cd10aa3 sb a3,213(sp) +8000a0b4: 00900693 li a3,9 +8000a0b8: 00f6c463 blt a3,a5,8000a0c0 <_svfprintf_r+0x62c> +8000a0bc: 0f40206f j 8000c1b0 <_svfprintf_r+0x271c> +8000a0c0: 0e310813 addi a6,sp,227 +8000a0c4: 00080513 mv a0,a6 +8000a0c8: 00a00613 li a2,10 +8000a0cc: 06300e13 li t3,99 +8000a0d0: 02c7e733 rem a4,a5,a2 +8000a0d4: 00050593 mv a1,a0 +8000a0d8: 00078693 mv a3,a5 +8000a0dc: fff50513 addi a0,a0,-1 +8000a0e0: 03070713 addi a4,a4,48 +8000a0e4: fee58fa3 sb a4,-1(a1) +8000a0e8: 02c7c7b3 div a5,a5,a2 +8000a0ec: fede42e3 blt t3,a3,8000a0d0 <_svfprintf_r+0x63c> +8000a0f0: 03078793 addi a5,a5,48 +8000a0f4: 0ff7f613 andi a2,a5,255 +8000a0f8: fec50fa3 sb a2,-1(a0) +8000a0fc: ffe58793 addi a5,a1,-2 +8000a100: 0107e463 bltu a5,a6,8000a108 <_svfprintf_r+0x674> +8000a104: 3980206f j 8000c49c <_svfprintf_r+0x2a08> +8000a108: 0d610693 addi a3,sp,214 +8000a10c: 0080006f j 8000a114 <_svfprintf_r+0x680> +8000a110: 0007c603 lbu a2,0(a5) +8000a114: 00c68023 sb a2,0(a3) +8000a118: 00178793 addi a5,a5,1 +8000a11c: 00168693 addi a3,a3,1 +8000a120: ff0798e3 bne a5,a6,8000a110 <_svfprintf_r+0x67c> +8000a124: 0e510793 addi a5,sp,229 +8000a128: 40b787b3 sub a5,a5,a1 +8000a12c: 0d610713 addi a4,sp,214 +8000a130: 00f707b3 add a5,a4,a5 +8000a134: 0d410693 addi a3,sp,212 +8000a138: 40d787b3 sub a5,a5,a3 +8000a13c: 02f12c23 sw a5,56(sp) +8000a140: 02012703 lw a4,32(sp) +8000a144: 03812683 lw a3,56(sp) +8000a148: 00100793 li a5,1 +8000a14c: 00d70cb3 add s9,a4,a3 +8000a150: 00e7c463 blt a5,a4,8000a158 <_svfprintf_r+0x6c4> +8000a154: 2300206f j 8000c384 <_svfprintf_r+0x28f0> +8000a158: 02c12783 lw a5,44(sp) +8000a15c: 00fc8cb3 add s9,s9,a5 +8000a160: 02812783 lw a5,40(sp) +8000a164: fffcca93 not s5,s9 +8000a168: 41fada93 srai s5,s5,0x1f +8000a16c: bff7fa13 andi s4,a5,-1025 +8000a170: 100a6a13 ori s4,s4,256 +8000a174: 015cfab3 and s5,s9,s5 +8000a178: 02012423 sw zero,40(sp) +8000a17c: 02012223 sw zero,36(sp) +8000a180: 00012e23 sw zero,28(sp) +8000a184: 05812783 lw a5,88(sp) +8000a188: 00079463 bnez a5,8000a190 <_svfprintf_r+0x6fc> +8000a18c: 0510106f j 8000b9dc <_svfprintf_r+0x1f48> +8000a190: 02d00793 li a5,45 +8000a194: 0cf103a3 sb a5,199(sp) +8000a198: 00000d93 li s11,0 +8000a19c: 001a8a93 addi s5,s5,1 +8000a1a0: ad9ff06f j 80009c78 <_svfprintf_r+0x1e4> +8000a1a4: 0e410613 addi a2,sp,228 +8000a1a8: 000c0593 mv a1,s8 +8000a1ac: 000d0513 mv a0,s10 +8000a1b0: 5cd040ef jal ra,8000ef7c <__ssprint_r> +8000a1b4: 100510e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000a1b8: 0ec12783 lw a5,236(sp) +8000a1bc: 10c10893 addi a7,sp,268 +8000a1c0: b11ff06f j 80009cd0 <_svfprintf_r+0x23c> +8000a1c4: 0e812683 lw a3,232(sp) +8000a1c8: 00178c93 addi s9,a5,1 +8000a1cc: 02012783 lw a5,32(sp) +8000a1d0: 00100613 li a2,1 +8000a1d4: 0168a023 sw s6,0(a7) +8000a1d8: 00168493 addi s1,a3,1 +8000a1dc: 00888913 addi s2,a7,8 +8000a1e0: 36f658e3 bge a2,a5,8000ad50 <_svfprintf_r+0x12bc> +8000a1e4: 00100793 li a5,1 +8000a1e8: 00f8a223 sw a5,4(a7) +8000a1ec: 0f912623 sw s9,236(sp) +8000a1f0: 0e912423 sw s1,232(sp) +8000a1f4: 00700793 li a5,7 +8000a1f8: 4a97c0e3 blt a5,s1,8000ae98 <_svfprintf_r+0x1404> +8000a1fc: 02c12783 lw a5,44(sp) +8000a200: 03012703 lw a4,48(sp) +8000a204: 00148493 addi s1,s1,1 +8000a208: 00fc8cb3 add s9,s9,a5 +8000a20c: 00f92223 sw a5,4(s2) +8000a210: 00e92023 sw a4,0(s2) +8000a214: 0f912623 sw s9,236(sp) +8000a218: 0e912423 sw s1,232(sp) +8000a21c: 00700793 li a5,7 +8000a220: 00890913 addi s2,s2,8 +8000a224: 4897cce3 blt a5,s1,8000aebc <_svfprintf_r+0x1428> +8000a228: 0f012783 lw a5,240(sp) +8000a22c: 00148613 addi a2,s1,1 +8000a230: 0a010593 addi a1,sp,160 +8000a234: 0af12823 sw a5,176(sp) +8000a238: 0f412783 lw a5,244(sp) +8000a23c: 0b010513 addi a0,sp,176 +8000a240: 00c12e23 sw a2,28(sp) +8000a244: 0af12a23 sw a5,180(sp) +8000a248: 0f812783 lw a5,248(sp) +8000a24c: 0a012023 sw zero,160(sp) +8000a250: 0a012223 sw zero,164(sp) +8000a254: 0af12c23 sw a5,184(sp) +8000a258: 0fc12783 lw a5,252(sp) +8000a25c: 0a012423 sw zero,168(sp) +8000a260: 0a012623 sw zero,172(sp) +8000a264: 0af12e23 sw a5,188(sp) +8000a268: 744070ef jal ra,800119ac <__eqtf2> +8000a26c: 01c12603 lw a2,28(sp) +8000a270: 02012783 lw a5,32(sp) +8000a274: 00890893 addi a7,s2,8 +8000a278: 00060693 mv a3,a2 +8000a27c: fff78d93 addi s11,a5,-1 +8000a280: 2e050ce3 beqz a0,8000ad78 <_svfprintf_r+0x12e4> +8000a284: 001b0713 addi a4,s6,1 +8000a288: 01bc8cb3 add s9,s9,s11 +8000a28c: 00e92023 sw a4,0(s2) +8000a290: 01b92223 sw s11,4(s2) +8000a294: 0f912623 sw s9,236(sp) +8000a298: 0ec12423 sw a2,232(sp) +8000a29c: 00700793 li a5,7 +8000a2a0: 00c7d463 bge a5,a2,8000a2a8 <_svfprintf_r+0x814> +8000a2a4: 0180106f j 8000b2bc <_svfprintf_r+0x1828> +8000a2a8: 01090793 addi a5,s2,16 +8000a2ac: 00248693 addi a3,s1,2 +8000a2b0: 00088913 mv s2,a7 +8000a2b4: 00078893 mv a7,a5 +8000a2b8: 03812603 lw a2,56(sp) +8000a2bc: 0d410713 addi a4,sp,212 +8000a2c0: 00e92023 sw a4,0(s2) +8000a2c4: 019607b3 add a5,a2,s9 +8000a2c8: 00c92223 sw a2,4(s2) +8000a2cc: 0ef12623 sw a5,236(sp) +8000a2d0: 0ed12423 sw a3,232(sp) +8000a2d4: 00700713 li a4,7 +8000a2d8: a6d756e3 bge a4,a3,80009d44 <_svfprintf_r+0x2b0> +8000a2dc: 0e410613 addi a2,sp,228 +8000a2e0: 000c0593 mv a1,s8 +8000a2e4: 000d0513 mv a0,s10 +8000a2e8: 495040ef jal ra,8000ef7c <__ssprint_r> +8000a2ec: 7c051463 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000a2f0: 0ec12783 lw a5,236(sp) +8000a2f4: 10c10893 addi a7,sp,268 +8000a2f8: a4dff06f j 80009d44 <_svfprintf_r+0x2b0> +8000a2fc: 01000693 li a3,16 +8000a300: 0e812703 lw a4,232(sp) +8000a304: 0096c463 blt a3,s1,8000a30c <_svfprintf_r+0x878> +8000a308: 1210106f j 8000bc28 <_svfprintf_r+0x2194> +8000a30c: 800156b7 lui a3,0x80015 +8000a310: 34c68e93 addi t4,a3,844 # 8001534c <__BSS_END__+0xffffe710> +8000a314: 01000913 li s2,16 +8000a318: 00700a13 li s4,7 +8000a31c: 000e8b13 mv s6,t4 +8000a320: 00c0006f j 8000a32c <_svfprintf_r+0x898> +8000a324: ff048493 addi s1,s1,-16 +8000a328: 04995663 bge s2,s1,8000a374 <_svfprintf_r+0x8e0> +8000a32c: 01078793 addi a5,a5,16 +8000a330: 00170713 addi a4,a4,1 +8000a334: 0168a023 sw s6,0(a7) +8000a338: 0128a223 sw s2,4(a7) +8000a33c: 0ef12623 sw a5,236(sp) +8000a340: 0ee12423 sw a4,232(sp) +8000a344: 00888893 addi a7,a7,8 +8000a348: fcea5ee3 bge s4,a4,8000a324 <_svfprintf_r+0x890> +8000a34c: 0e410613 addi a2,sp,228 +8000a350: 000c0593 mv a1,s8 +8000a354: 000d0513 mv a0,s10 +8000a358: 425040ef jal ra,8000ef7c <__ssprint_r> +8000a35c: 74051c63 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000a360: ff048493 addi s1,s1,-16 +8000a364: 0ec12783 lw a5,236(sp) +8000a368: 0e812703 lw a4,232(sp) +8000a36c: 10c10893 addi a7,sp,268 +8000a370: fa994ee3 blt s2,s1,8000a32c <_svfprintf_r+0x898> +8000a374: 000b0e93 mv t4,s6 +8000a378: 009787b3 add a5,a5,s1 +8000a37c: 00170713 addi a4,a4,1 +8000a380: 01d8a023 sw t4,0(a7) +8000a384: 0098a223 sw s1,4(a7) +8000a388: 0ef12623 sw a5,236(sp) +8000a38c: 0ee12423 sw a4,232(sp) +8000a390: 00700693 li a3,7 +8000a394: 9ce6d0e3 bge a3,a4,80009d54 <_svfprintf_r+0x2c0> +8000a398: 0e410613 addi a2,sp,228 +8000a39c: 000c0593 mv a1,s8 +8000a3a0: 000d0513 mv a0,s10 +8000a3a4: 3d9040ef jal ra,8000ef7c <__ssprint_r> +8000a3a8: 70051663 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000a3ac: 0ec12783 lw a5,236(sp) +8000a3b0: 9a5ff06f j 80009d54 <_svfprintf_r+0x2c0> +8000a3b4: 01412783 lw a5,20(sp) +8000a3b8: 0c0103a3 sb zero,199(sp) +8000a3bc: 000c8893 mv a7,s9 +8000a3c0: 0007ab03 lw s6,0(a5) +8000a3c4: 00478913 addi s2,a5,4 +8000a3c8: 4e0b02e3 beqz s6,8000b0ac <_svfprintf_r+0x1618> +8000a3cc: fff00793 li a5,-1 +8000a3d0: 00fd9463 bne s11,a5,8000a3d8 <_svfprintf_r+0x944> +8000a3d4: 1fc0106f j 8000b5d0 <_svfprintf_r+0x1b3c> +8000a3d8: 000d8613 mv a2,s11 +8000a3dc: 00000593 li a1,0 +8000a3e0: 000b0513 mv a0,s6 +8000a3e4: 01912a23 sw s9,20(sp) +8000a3e8: f59fd0ef jal ra,80008340 +8000a3ec: 00a12823 sw a0,16(sp) +8000a3f0: 01412883 lw a7,20(sp) +8000a3f4: 00051463 bnez a0,8000a3fc <_svfprintf_r+0x968> +8000a3f8: 75c0106f j 8000bb54 <_svfprintf_r+0x20c0> +8000a3fc: 01012783 lw a5,16(sp) +8000a400: 01212a23 sw s2,20(sp) +8000a404: 00012823 sw zero,16(sp) +8000a408: 41678cb3 sub s9,a5,s6 +8000a40c: 0c714783 lbu a5,199(sp) +8000a410: fffcca93 not s5,s9 +8000a414: 41fada93 srai s5,s5,0x1f +8000a418: 02012423 sw zero,40(sp) +8000a41c: 02012223 sw zero,36(sp) +8000a420: 00012e23 sw zero,28(sp) +8000a424: 015cfab3 and s5,s9,s5 +8000a428: 00000d93 li s11,0 +8000a42c: 840786e3 beqz a5,80009c78 <_svfprintf_r+0x1e4> +8000a430: 001a8a93 addi s5,s5,1 +8000a434: 845ff06f j 80009c78 <_svfprintf_r+0x1e4> +8000a438: 01412703 lw a4,20(sp) +8000a43c: 000c8893 mv a7,s9 +8000a440: 0c0103a3 sb zero,199(sp) +8000a444: 00072783 lw a5,0(a4) +8000a448: 00470713 addi a4,a4,4 +8000a44c: 00e12a23 sw a4,20(sp) +8000a450: 14f10623 sb a5,332(sp) +8000a454: 00100a93 li s5,1 +8000a458: 00100c93 li s9,1 +8000a45c: 14c10b13 addi s6,sp,332 +8000a460: 805ff06f j 80009c64 <_svfprintf_r+0x1d0> +8000a464: 00044483 lbu s1,0(s0) +8000a468: 004a6a13 ori s4,s4,4 +8000a46c: f8cff06f j 80009bf8 <_svfprintf_r+0x164> +8000a470: 01412683 lw a3,20(sp) +8000a474: 020a7793 andi a5,s4,32 +8000a478: 000c8893 mv a7,s9 +8000a47c: 0006a703 lw a4,0(a3) +8000a480: 00468693 addi a3,a3,4 +8000a484: 00d12a23 sw a3,20(sp) +8000a488: 280790e3 bnez a5,8000af08 <_svfprintf_r+0x1474> +8000a48c: 010a7793 andi a5,s4,16 +8000a490: 00078463 beqz a5,8000a498 <_svfprintf_r+0xa04> +8000a494: 12c0106f j 8000b5c0 <_svfprintf_r+0x1b2c> +8000a498: 040a7793 andi a5,s4,64 +8000a49c: 00078463 beqz a5,8000a4a4 <_svfprintf_r+0xa10> +8000a4a0: 3d80106f j 8000b878 <_svfprintf_r+0x1de4> +8000a4a4: 200a7a13 andi s4,s4,512 +8000a4a8: 000a1463 bnez s4,8000a4b0 <_svfprintf_r+0xa1c> +8000a4ac: 1140106f j 8000b5c0 <_svfprintf_r+0x1b2c> +8000a4b0: 00c12783 lw a5,12(sp) +8000a4b4: 00040b13 mv s6,s0 +8000a4b8: 00f70023 sb a5,0(a4) +8000a4bc: 8d1ff06f j 80009d8c <_svfprintf_r+0x2f8> +8000a4c0: 00044483 lbu s1,0(s0) +8000a4c4: 06c00793 li a5,108 +8000a4c8: 38f48ee3 beq s1,a5,8000b064 <_svfprintf_r+0x15d0> +8000a4cc: 010a6a13 ori s4,s4,16 +8000a4d0: f28ff06f j 80009bf8 <_svfprintf_r+0x164> +8000a4d4: 01412703 lw a4,20(sp) +8000a4d8: ffff87b7 lui a5,0xffff8 +8000a4dc: 8307c793 xori a5,a5,-2000 +8000a4e0: 0cf11423 sh a5,200(sp) +8000a4e4: 00470793 addi a5,a4,4 +8000a4e8: 00f12a23 sw a5,20(sp) +8000a4ec: 00072903 lw s2,0(a4) +8000a4f0: 800157b7 lui a5,0x80015 +8000a4f4: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +8000a4f8: 000c8893 mv a7,s9 +8000a4fc: 02f12a23 sw a5,52(sp) +8000a500: 00000c93 li s9,0 +8000a504: 002a6b93 ori s7,s4,2 +8000a508: 00200793 li a5,2 +8000a50c: 07800493 li s1,120 +8000a510: 0c0103a3 sb zero,199(sp) +8000a514: fff00713 li a4,-1 +8000a518: 20ed8663 beq s11,a4,8000a724 <_svfprintf_r+0xc90> +8000a51c: 01996733 or a4,s2,s9 +8000a520: f7fbfa13 andi s4,s7,-129 +8000a524: 1e071e63 bnez a4,8000a720 <_svfprintf_r+0xc8c> +8000a528: 260d9463 bnez s11,8000a790 <_svfprintf_r+0xcfc> +8000a52c: 1c079063 bnez a5,8000a6ec <_svfprintf_r+0xc58> +8000a530: 001bfc93 andi s9,s7,1 +8000a534: 1b010b13 addi s6,sp,432 +8000a538: 1c0c90e3 bnez s9,8000aef8 <_svfprintf_r+0x1464> +8000a53c: 000c8a93 mv s5,s9 +8000a540: 01bcd463 bge s9,s11,8000a548 <_svfprintf_r+0xab4> +8000a544: 000d8a93 mv s5,s11 +8000a548: 0c714783 lbu a5,199(sp) +8000a54c: 00012823 sw zero,16(sp) +8000a550: 02012423 sw zero,40(sp) +8000a554: 02012223 sw zero,36(sp) +8000a558: 00012e23 sw zero,28(sp) +8000a55c: ec079ae3 bnez a5,8000a430 <_svfprintf_r+0x99c> +8000a560: f18ff06f j 80009c78 <_svfprintf_r+0x1e4> +8000a564: 000c8893 mv a7,s9 +8000a568: 010a6a13 ori s4,s4,16 +8000a56c: 020a7793 andi a5,s4,32 +8000a570: 06078ce3 beqz a5,8000ade8 <_svfprintf_r+0x1354> +8000a574: 01412783 lw a5,20(sp) +8000a578: 00778b13 addi s6,a5,7 +8000a57c: ff8b7b13 andi s6,s6,-8 +8000a580: 000b2903 lw s2,0(s6) +8000a584: 004b2c83 lw s9,4(s6) +8000a588: 008b0793 addi a5,s6,8 +8000a58c: 00f12a23 sw a5,20(sp) +8000a590: bffa7b93 andi s7,s4,-1025 +8000a594: 00000793 li a5,0 +8000a598: f79ff06f j 8000a510 <_svfprintf_r+0xa7c> +8000a59c: 00044483 lbu s1,0(s0) +8000a5a0: 06800793 li a5,104 +8000a5a4: 2cf488e3 beq s1,a5,8000b074 <_svfprintf_r+0x15e0> +8000a5a8: 040a6a13 ori s4,s4,64 +8000a5ac: e4cff06f j 80009bf8 <_svfprintf_r+0x164> +8000a5b0: 000c8893 mv a7,s9 +8000a5b4: 010a6b93 ori s7,s4,16 +8000a5b8: 020bf793 andi a5,s7,32 +8000a5bc: 04078ce3 beqz a5,8000ae14 <_svfprintf_r+0x1380> +8000a5c0: 01412783 lw a5,20(sp) +8000a5c4: 00778b13 addi s6,a5,7 +8000a5c8: ff8b7b13 andi s6,s6,-8 +8000a5cc: 008b0793 addi a5,s6,8 +8000a5d0: 00f12a23 sw a5,20(sp) +8000a5d4: 000b2903 lw s2,0(s6) +8000a5d8: 004b2c83 lw s9,4(s6) +8000a5dc: 00100793 li a5,1 +8000a5e0: f31ff06f j 8000a510 <_svfprintf_r+0xa7c> +8000a5e4: 00044483 lbu s1,0(s0) +8000a5e8: 008a6a13 ori s4,s4,8 +8000a5ec: e0cff06f j 80009bf8 <_svfprintf_r+0x164> +8000a5f0: 01412783 lw a5,20(sp) +8000a5f4: 00044483 lbu s1,0(s0) +8000a5f8: 0007a983 lw s3,0(a5) +8000a5fc: 00478793 addi a5,a5,4 +8000a600: 00f12a23 sw a5,20(sp) +8000a604: de09da63 bgez s3,80009bf8 <_svfprintf_r+0x164> +8000a608: 413009b3 neg s3,s3 +8000a60c: 004a6a13 ori s4,s4,4 +8000a610: de8ff06f j 80009bf8 <_svfprintf_r+0x164> +8000a614: 00044483 lbu s1,0(s0) +8000a618: 001a6a13 ori s4,s4,1 +8000a61c: ddcff06f j 80009bf8 <_svfprintf_r+0x164> +8000a620: 0c714783 lbu a5,199(sp) +8000a624: 00044483 lbu s1,0(s0) +8000a628: dc079863 bnez a5,80009bf8 <_svfprintf_r+0x164> +8000a62c: 02000793 li a5,32 +8000a630: 0cf103a3 sb a5,199(sp) +8000a634: dc4ff06f j 80009bf8 <_svfprintf_r+0x164> +8000a638: 00044483 lbu s1,0(s0) +8000a63c: 080a6a13 ori s4,s4,128 +8000a640: db8ff06f j 80009bf8 <_svfprintf_r+0x164> +8000a644: 00044483 lbu s1,0(s0) +8000a648: 00140713 addi a4,s0,1 +8000a64c: 01749463 bne s1,s7,8000a654 <_svfprintf_r+0xbc0> +8000a650: 5f50106f j 8000c444 <_svfprintf_r+0x29b0> +8000a654: fd048693 addi a3,s1,-48 +8000a658: 00070413 mv s0,a4 +8000a65c: 00000d93 li s11,0 +8000a660: d8daee63 bltu s5,a3,80009bfc <_svfprintf_r+0x168> +8000a664: 00044483 lbu s1,0(s0) +8000a668: 002d9793 slli a5,s11,0x2 +8000a66c: 01b787b3 add a5,a5,s11 +8000a670: 00179793 slli a5,a5,0x1 +8000a674: 00d78db3 add s11,a5,a3 +8000a678: fd048693 addi a3,s1,-48 +8000a67c: 00140413 addi s0,s0,1 +8000a680: fedaf2e3 bgeu s5,a3,8000a664 <_svfprintf_r+0xbd0> +8000a684: d78ff06f j 80009bfc <_svfprintf_r+0x168> +8000a688: 02b00793 li a5,43 +8000a68c: 00044483 lbu s1,0(s0) +8000a690: 0cf103a3 sb a5,199(sp) +8000a694: d64ff06f j 80009bf8 <_svfprintf_r+0x164> +8000a698: 000c8893 mv a7,s9 +8000a69c: 010a6a13 ori s4,s4,16 +8000a6a0: 020a7793 andi a5,s4,32 +8000a6a4: 7a078063 beqz a5,8000ae44 <_svfprintf_r+0x13b0> +8000a6a8: 01412783 lw a5,20(sp) +8000a6ac: 00778b13 addi s6,a5,7 +8000a6b0: ff8b7b13 andi s6,s6,-8 +8000a6b4: 004b2783 lw a5,4(s6) +8000a6b8: 000b2903 lw s2,0(s6) +8000a6bc: 008b0713 addi a4,s6,8 +8000a6c0: 00e12a23 sw a4,20(sp) +8000a6c4: 00078c93 mv s9,a5 +8000a6c8: 7a07c663 bltz a5,8000ae74 <_svfprintf_r+0x13e0> +8000a6cc: fff00793 li a5,-1 +8000a6d0: 000a0b93 mv s7,s4 +8000a6d4: 02fd8463 beq s11,a5,8000a6fc <_svfprintf_r+0xc68> +8000a6d8: 019967b3 or a5,s2,s9 +8000a6dc: f7fa7b93 andi s7,s4,-129 +8000a6e0: 00079e63 bnez a5,8000a6fc <_svfprintf_r+0xc68> +8000a6e4: 020d9263 bnez s11,8000a708 <_svfprintf_r+0xc74> +8000a6e8: 000b8a13 mv s4,s7 +8000a6ec: 00000d93 li s11,0 +8000a6f0: 00000c93 li s9,0 +8000a6f4: 1b010b13 addi s6,sp,432 +8000a6f8: e45ff06f j 8000a53c <_svfprintf_r+0xaa8> +8000a6fc: 400c96e3 bnez s9,8000b308 <_svfprintf_r+0x1874> +8000a700: 00900793 li a5,9 +8000a704: 4127e2e3 bltu a5,s2,8000b308 <_svfprintf_r+0x1874> +8000a708: 03090913 addi s2,s2,48 +8000a70c: 1b2107a3 sb s2,431(sp) +8000a710: 000b8a13 mv s4,s7 +8000a714: 00100c93 li s9,1 +8000a718: 1af10b13 addi s6,sp,431 +8000a71c: e21ff06f j 8000a53c <_svfprintf_r+0xaa8> +8000a720: 000a0b93 mv s7,s4 +8000a724: 00100713 li a4,1 +8000a728: fce78ae3 beq a5,a4,8000a6fc <_svfprintf_r+0xc68> +8000a72c: 00200713 li a4,2 +8000a730: 06e78c63 beq a5,a4,8000a7a8 <_svfprintf_r+0xd14> +8000a734: 1b010b13 addi s6,sp,432 +8000a738: 01dc9713 slli a4,s9,0x1d +8000a73c: 00797793 andi a5,s2,7 +8000a740: 00395913 srli s2,s2,0x3 +8000a744: 03078793 addi a5,a5,48 +8000a748: 01276933 or s2,a4,s2 +8000a74c: 003cdc93 srli s9,s9,0x3 +8000a750: fefb0fa3 sb a5,-1(s6) +8000a754: 01996733 or a4,s2,s9 +8000a758: 000b0613 mv a2,s6 +8000a75c: fffb0b13 addi s6,s6,-1 +8000a760: fc071ce3 bnez a4,8000a738 <_svfprintf_r+0xca4> +8000a764: 001bf693 andi a3,s7,1 +8000a768: 06068a63 beqz a3,8000a7dc <_svfprintf_r+0xd48> +8000a76c: 03000693 li a3,48 +8000a770: 06d78663 beq a5,a3,8000a7dc <_svfprintf_r+0xd48> +8000a774: ffe60613 addi a2,a2,-2 +8000a778: 1b010793 addi a5,sp,432 +8000a77c: fedb0fa3 sb a3,-1(s6) +8000a780: 40c78cb3 sub s9,a5,a2 +8000a784: 000b8a13 mv s4,s7 +8000a788: 00060b13 mv s6,a2 +8000a78c: db1ff06f j 8000a53c <_svfprintf_r+0xaa8> +8000a790: 00100713 li a4,1 +8000a794: 00e79463 bne a5,a4,8000a79c <_svfprintf_r+0xd08> +8000a798: 1710106f j 8000c108 <_svfprintf_r+0x2674> +8000a79c: 00200713 li a4,2 +8000a7a0: 000a0b93 mv s7,s4 +8000a7a4: f8e798e3 bne a5,a4,8000a734 <_svfprintf_r+0xca0> +8000a7a8: 03412683 lw a3,52(sp) +8000a7ac: 1b010b13 addi s6,sp,432 +8000a7b0: 00f97793 andi a5,s2,15 +8000a7b4: 00f687b3 add a5,a3,a5 +8000a7b8: 0007c703 lbu a4,0(a5) +8000a7bc: 00495913 srli s2,s2,0x4 +8000a7c0: 01cc9793 slli a5,s9,0x1c +8000a7c4: 0127e933 or s2,a5,s2 +8000a7c8: 004cdc93 srli s9,s9,0x4 +8000a7cc: feeb0fa3 sb a4,-1(s6) +8000a7d0: 019967b3 or a5,s2,s9 +8000a7d4: fffb0b13 addi s6,s6,-1 +8000a7d8: fc079ce3 bnez a5,8000a7b0 <_svfprintf_r+0xd1c> +8000a7dc: 1b010793 addi a5,sp,432 +8000a7e0: 41678cb3 sub s9,a5,s6 +8000a7e4: 000b8a13 mv s4,s7 +8000a7e8: d55ff06f j 8000a53c <_svfprintf_r+0xaa8> +8000a7ec: 06500693 li a3,101 +8000a7f0: 9c96dae3 bge a3,s1,8000a1c4 <_svfprintf_r+0x730> +8000a7f4: 0f012683 lw a3,240(sp) +8000a7f8: 0a010593 addi a1,sp,160 +8000a7fc: 0b010513 addi a0,sp,176 +8000a800: 0ad12823 sw a3,176(sp) +8000a804: 0f412683 lw a3,244(sp) +8000a808: 05112223 sw a7,68(sp) +8000a80c: 04f12023 sw a5,64(sp) +8000a810: 0ad12a23 sw a3,180(sp) +8000a814: 0f812683 lw a3,248(sp) +8000a818: 0a012023 sw zero,160(sp) +8000a81c: 0a012223 sw zero,164(sp) +8000a820: 0ad12c23 sw a3,184(sp) +8000a824: 0fc12683 lw a3,252(sp) +8000a828: 0a012423 sw zero,168(sp) +8000a82c: 0a012623 sw zero,172(sp) +8000a830: 0ad12e23 sw a3,188(sp) +8000a834: 178070ef jal ra,800119ac <__eqtf2> +8000a838: 04012783 lw a5,64(sp) +8000a83c: 04412883 lw a7,68(sp) +8000a840: 38051c63 bnez a0,8000abd8 <_svfprintf_r+0x1144> +8000a844: 0e812703 lw a4,232(sp) +8000a848: 800156b7 lui a3,0x80015 +8000a84c: ca868693 addi a3,a3,-856 # 80014ca8 <__BSS_END__+0xffffe06c> +8000a850: 00d8a023 sw a3,0(a7) +8000a854: 00178793 addi a5,a5,1 +8000a858: 00100693 li a3,1 +8000a85c: 00170713 addi a4,a4,1 +8000a860: 00d8a223 sw a3,4(a7) +8000a864: 0ef12623 sw a5,236(sp) +8000a868: 0ee12423 sw a4,232(sp) +8000a86c: 00700693 li a3,7 +8000a870: 00888893 addi a7,a7,8 +8000a874: 44e6cce3 blt a3,a4,8000b4cc <_svfprintf_r+0x1a38> +8000a878: 0cc12703 lw a4,204(sp) +8000a87c: 02012683 lw a3,32(sp) +8000a880: 66d75063 bge a4,a3,8000aee0 <_svfprintf_r+0x144c> +8000a884: 03012703 lw a4,48(sp) +8000a888: 02c12683 lw a3,44(sp) +8000a88c: 00888893 addi a7,a7,8 +8000a890: fee8ac23 sw a4,-8(a7) +8000a894: 0e812703 lw a4,232(sp) +8000a898: 00d787b3 add a5,a5,a3 +8000a89c: fed8ae23 sw a3,-4(a7) +8000a8a0: 00170713 addi a4,a4,1 +8000a8a4: 0ef12623 sw a5,236(sp) +8000a8a8: 0ee12423 sw a4,232(sp) +8000a8ac: 00700693 li a3,7 +8000a8b0: 76e6cc63 blt a3,a4,8000b028 <_svfprintf_r+0x1594> +8000a8b4: 02012703 lw a4,32(sp) +8000a8b8: fff70493 addi s1,a4,-1 +8000a8bc: c8905463 blez s1,80009d44 <_svfprintf_r+0x2b0> +8000a8c0: 01000693 li a3,16 +8000a8c4: 0e812703 lw a4,232(sp) +8000a8c8: 4296d2e3 bge a3,s1,8000b4ec <_svfprintf_r+0x1a58> +8000a8cc: 01000913 li s2,16 +8000a8d0: 00700c93 li s9,7 +8000a8d4: 00c0006f j 8000a8e0 <_svfprintf_r+0xe4c> +8000a8d8: ff048493 addi s1,s1,-16 +8000a8dc: 409958e3 bge s2,s1,8000b4ec <_svfprintf_r+0x1a58> +8000a8e0: 00812683 lw a3,8(sp) +8000a8e4: 01078793 addi a5,a5,16 +8000a8e8: 00170713 addi a4,a4,1 +8000a8ec: 00d8a023 sw a3,0(a7) +8000a8f0: 0128a223 sw s2,4(a7) +8000a8f4: 0ef12623 sw a5,236(sp) +8000a8f8: 0ee12423 sw a4,232(sp) +8000a8fc: 00888893 addi a7,a7,8 +8000a900: fcecdce3 bge s9,a4,8000a8d8 <_svfprintf_r+0xe44> +8000a904: 0e410613 addi a2,sp,228 +8000a908: 000c0593 mv a1,s8 +8000a90c: 000d0513 mv a0,s10 +8000a910: 66c040ef jal ra,8000ef7c <__ssprint_r> +8000a914: 1a051063 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000a918: 0ec12783 lw a5,236(sp) +8000a91c: 0e812703 lw a4,232(sp) +8000a920: 10c10893 addi a7,sp,268 +8000a924: fb5ff06f j 8000a8d8 <_svfprintf_r+0xe44> +8000a928: 41598933 sub s2,s3,s5 +8000a92c: bf205063 blez s2,80009d0c <_svfprintf_r+0x278> +8000a930: 01000613 li a2,16 +8000a934: 0e812683 lw a3,232(sp) +8000a938: 07265463 bge a2,s2,8000a9a0 <_svfprintf_r+0xf0c> +8000a93c: 01000e13 li t3,16 +8000a940: 00700b93 li s7,7 +8000a944: 00c0006f j 8000a950 <_svfprintf_r+0xebc> +8000a948: ff090913 addi s2,s2,-16 +8000a94c: 052e5a63 bge t3,s2,8000a9a0 <_svfprintf_r+0xf0c> +8000a950: 00812703 lw a4,8(sp) +8000a954: 01078793 addi a5,a5,16 +8000a958: 00168693 addi a3,a3,1 +8000a95c: 00e8a023 sw a4,0(a7) +8000a960: 01c8a223 sw t3,4(a7) +8000a964: 0ef12623 sw a5,236(sp) +8000a968: 0ed12423 sw a3,232(sp) +8000a96c: 00888893 addi a7,a7,8 +8000a970: fcdbdce3 bge s7,a3,8000a948 <_svfprintf_r+0xeb4> +8000a974: 0e410613 addi a2,sp,228 +8000a978: 000c0593 mv a1,s8 +8000a97c: 000d0513 mv a0,s10 +8000a980: 5fc040ef jal ra,8000ef7c <__ssprint_r> +8000a984: 12051863 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000a988: 01000e13 li t3,16 +8000a98c: ff090913 addi s2,s2,-16 +8000a990: 0ec12783 lw a5,236(sp) +8000a994: 0e812683 lw a3,232(sp) +8000a998: 10c10893 addi a7,sp,268 +8000a99c: fb2e4ae3 blt t3,s2,8000a950 <_svfprintf_r+0xebc> +8000a9a0: 00812703 lw a4,8(sp) +8000a9a4: 012787b3 add a5,a5,s2 +8000a9a8: 00168693 addi a3,a3,1 +8000a9ac: 00e8a023 sw a4,0(a7) +8000a9b0: 0128a223 sw s2,4(a7) +8000a9b4: 0ef12623 sw a5,236(sp) +8000a9b8: 0ed12423 sw a3,232(sp) +8000a9bc: 00700613 li a2,7 +8000a9c0: 00888893 addi a7,a7,8 +8000a9c4: b4d65463 bge a2,a3,80009d0c <_svfprintf_r+0x278> +8000a9c8: 0e410613 addi a2,sp,228 +8000a9cc: 000c0593 mv a1,s8 +8000a9d0: 000d0513 mv a0,s10 +8000a9d4: 5a8040ef jal ra,8000ef7c <__ssprint_r> +8000a9d8: 0c051e63 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000a9dc: 419d8db3 sub s11,s11,s9 +8000a9e0: 0ec12783 lw a5,236(sp) +8000a9e4: 10c10893 addi a7,sp,268 +8000a9e8: b3b05663 blez s11,80009d14 <_svfprintf_r+0x280> +8000a9ec: 01000613 li a2,16 +8000a9f0: 0e812683 lw a3,232(sp) +8000a9f4: 07b65263 bge a2,s11,8000aa58 <_svfprintf_r+0xfc4> +8000a9f8: 01000b93 li s7,16 +8000a9fc: 00700913 li s2,7 +8000aa00: 00c0006f j 8000aa0c <_svfprintf_r+0xf78> +8000aa04: ff0d8d93 addi s11,s11,-16 +8000aa08: 05bbd863 bge s7,s11,8000aa58 <_svfprintf_r+0xfc4> +8000aa0c: 00812703 lw a4,8(sp) +8000aa10: 01078793 addi a5,a5,16 +8000aa14: 00168693 addi a3,a3,1 +8000aa18: 00e8a023 sw a4,0(a7) +8000aa1c: 0178a223 sw s7,4(a7) +8000aa20: 0ef12623 sw a5,236(sp) +8000aa24: 0ed12423 sw a3,232(sp) +8000aa28: 00888893 addi a7,a7,8 +8000aa2c: fcd95ce3 bge s2,a3,8000aa04 <_svfprintf_r+0xf70> +8000aa30: 0e410613 addi a2,sp,228 +8000aa34: 000c0593 mv a1,s8 +8000aa38: 000d0513 mv a0,s10 +8000aa3c: 540040ef jal ra,8000ef7c <__ssprint_r> +8000aa40: 06051a63 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000aa44: ff0d8d93 addi s11,s11,-16 +8000aa48: 0ec12783 lw a5,236(sp) +8000aa4c: 0e812683 lw a3,232(sp) +8000aa50: 10c10893 addi a7,sp,268 +8000aa54: fbbbcce3 blt s7,s11,8000aa0c <_svfprintf_r+0xf78> +8000aa58: 00812703 lw a4,8(sp) +8000aa5c: 01b787b3 add a5,a5,s11 +8000aa60: 00168693 addi a3,a3,1 +8000aa64: 00e8a023 sw a4,0(a7) +8000aa68: 01b8a223 sw s11,4(a7) +8000aa6c: 0ef12623 sw a5,236(sp) +8000aa70: 0ed12423 sw a3,232(sp) +8000aa74: 00700613 li a2,7 +8000aa78: 00888893 addi a7,a7,8 +8000aa7c: a8d65c63 bge a2,a3,80009d14 <_svfprintf_r+0x280> +8000aa80: 0e410613 addi a2,sp,228 +8000aa84: 000c0593 mv a1,s8 +8000aa88: 000d0513 mv a0,s10 +8000aa8c: 4f0040ef jal ra,8000ef7c <__ssprint_r> +8000aa90: 02051263 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000aa94: 0ec12783 lw a5,236(sp) +8000aa98: 10c10893 addi a7,sp,268 +8000aa9c: a78ff06f j 80009d14 <_svfprintf_r+0x280> +8000aaa0: 0e410613 addi a2,sp,228 +8000aaa4: 000c0593 mv a1,s8 +8000aaa8: 000d0513 mv a0,s10 +8000aaac: 4d0040ef jal ra,8000ef7c <__ssprint_r> +8000aab0: aa050e63 beqz a0,80009d6c <_svfprintf_r+0x2d8> +8000aab4: 01012b83 lw s7,16(sp) +8000aab8: ae0b8463 beqz s7,80009da0 <_svfprintf_r+0x30c> +8000aabc: 000b8593 mv a1,s7 +8000aac0: 000d0513 mv a0,s10 +8000aac4: f11f90ef jal ra,800049d4 <_free_r> +8000aac8: ad8ff06f j 80009da0 <_svfprintf_r+0x30c> +8000aacc: 80015737 lui a4,0x80015 +8000aad0: 01000613 li a2,16 +8000aad4: 0e812683 lw a3,232(sp) +8000aad8: 34c70e93 addi t4,a4,844 # 8001534c <__BSS_END__+0xffffe710> +8000aadc: 09065c63 bge a2,a6,8000ab74 <_svfprintf_r+0x10e0> +8000aae0: 04812023 sw s0,64(sp) +8000aae4: 04912223 sw s1,68(sp) +8000aae8: 000d0413 mv s0,s10 +8000aaec: 000c0493 mv s1,s8 +8000aaf0: 01000e13 li t3,16 +8000aaf4: 00700293 li t0,7 +8000aaf8: 00080c13 mv s8,a6 +8000aafc: 000e8d13 mv s10,t4 +8000ab00: 00c0006f j 8000ab0c <_svfprintf_r+0x1078> +8000ab04: ff0c0c13 addi s8,s8,-16 +8000ab08: 058e5a63 bge t3,s8,8000ab5c <_svfprintf_r+0x10c8> +8000ab0c: 01078793 addi a5,a5,16 +8000ab10: 00168693 addi a3,a3,1 +8000ab14: 01a8a023 sw s10,0(a7) +8000ab18: 01c8a223 sw t3,4(a7) +8000ab1c: 0ef12623 sw a5,236(sp) +8000ab20: 0ed12423 sw a3,232(sp) +8000ab24: 00888893 addi a7,a7,8 +8000ab28: fcd2dee3 bge t0,a3,8000ab04 <_svfprintf_r+0x1070> +8000ab2c: 0e410613 addi a2,sp,228 +8000ab30: 00048593 mv a1,s1 +8000ab34: 00040513 mv a0,s0 +8000ab38: 444040ef jal ra,8000ef7c <__ssprint_r> +8000ab3c: 160512e3 bnez a0,8000b4a0 <_svfprintf_r+0x1a0c> +8000ab40: 01000e13 li t3,16 +8000ab44: ff0c0c13 addi s8,s8,-16 +8000ab48: 0ec12783 lw a5,236(sp) +8000ab4c: 0e812683 lw a3,232(sp) +8000ab50: 10c10893 addi a7,sp,268 +8000ab54: 00700293 li t0,7 +8000ab58: fb8e4ae3 blt t3,s8,8000ab0c <_svfprintf_r+0x1078> +8000ab5c: 000c0813 mv a6,s8 +8000ab60: 000d0e93 mv t4,s10 +8000ab64: 00048c13 mv s8,s1 +8000ab68: 00040d13 mv s10,s0 +8000ab6c: 04412483 lw s1,68(sp) +8000ab70: 04012403 lw s0,64(sp) +8000ab74: 010787b3 add a5,a5,a6 +8000ab78: 00168693 addi a3,a3,1 +8000ab7c: 01d8a023 sw t4,0(a7) +8000ab80: 0108a223 sw a6,4(a7) +8000ab84: 0ef12623 sw a5,236(sp) +8000ab88: 0ed12423 sw a3,232(sp) +8000ab8c: 00700613 li a2,7 +8000ab90: 00888893 addi a7,a7,8 +8000ab94: 90d65263 bge a2,a3,80009c98 <_svfprintf_r+0x204> +8000ab98: 0e410613 addi a2,sp,228 +8000ab9c: 000c0593 mv a1,s8 +8000aba0: 000d0513 mv a0,s10 +8000aba4: 3d8040ef jal ra,8000ef7c <__ssprint_r> +8000aba8: f00516e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000abac: 0ec12783 lw a5,236(sp) +8000abb0: 10c10893 addi a7,sp,268 +8000abb4: 8e4ff06f j 80009c98 <_svfprintf_r+0x204> +8000abb8: 0e410613 addi a2,sp,228 +8000abbc: 000c0593 mv a1,s8 +8000abc0: 000d0513 mv a0,s10 +8000abc4: 3b8040ef jal ra,8000ef7c <__ssprint_r> +8000abc8: ee0516e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000abcc: 0ec12783 lw a5,236(sp) +8000abd0: 10c10893 addi a7,sp,268 +8000abd4: 930ff06f j 80009d04 <_svfprintf_r+0x270> +8000abd8: 0cc12583 lw a1,204(sp) +8000abdc: 7eb05c63 blez a1,8000b3d4 <_svfprintf_r+0x1940> +8000abe0: 01c12703 lw a4,28(sp) +8000abe4: 02012683 lw a3,32(sp) +8000abe8: 00070493 mv s1,a4 +8000abec: 3ce6c263 blt a3,a4,8000afb0 <_svfprintf_r+0x151c> +8000abf0: 02905663 blez s1,8000ac1c <_svfprintf_r+0x1188> +8000abf4: 0e812683 lw a3,232(sp) +8000abf8: 009787b3 add a5,a5,s1 +8000abfc: 0168a023 sw s6,0(a7) 8000ac00: 00168693 addi a3,a3,1 -8000ac04: 00e8a023 sw a4,0(a7) -8000ac08: 0128a223 sw s2,4(a7) -8000ac0c: 0ef12623 sw a5,236(sp) -8000ac10: 0ed12423 sw a3,232(sp) -8000ac14: 00700613 li a2,7 -8000ac18: 00888893 addi a7,a7,8 -8000ac1c: b4d65463 bge a2,a3,80009f64 <_svfprintf_r+0x278> -8000ac20: 0e410613 addi a2,sp,228 -8000ac24: 000c0593 mv a1,s8 -8000ac28: 000d0513 mv a0,s10 -8000ac2c: 2c4040ef jal ra,8000eef0 <__ssprint_r> -8000ac30: 0c051e63 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000ac34: 419d8db3 sub s11,s11,s9 -8000ac38: 0ec12783 lw a5,236(sp) -8000ac3c: 10c10893 addi a7,sp,268 -8000ac40: b3b05663 blez s11,80009f6c <_svfprintf_r+0x280> -8000ac44: 01000613 li a2,16 -8000ac48: 0e812683 lw a3,232(sp) -8000ac4c: 07b65263 bge a2,s11,8000acb0 <_svfprintf_r+0xfc4> -8000ac50: 01000b93 li s7,16 -8000ac54: 00700913 li s2,7 -8000ac58: 00c0006f j 8000ac64 <_svfprintf_r+0xf78> -8000ac5c: ff0d8d93 addi s11,s11,-16 -8000ac60: 05bbd863 bge s7,s11,8000acb0 <_svfprintf_r+0xfc4> -8000ac64: 00812703 lw a4,8(sp) -8000ac68: 01078793 addi a5,a5,16 -8000ac6c: 00168693 addi a3,a3,1 -8000ac70: 00e8a023 sw a4,0(a7) -8000ac74: 0178a223 sw s7,4(a7) +8000ac04: 0098a223 sw s1,4(a7) +8000ac08: 0ef12623 sw a5,236(sp) +8000ac0c: 0ed12423 sw a3,232(sp) +8000ac10: 00700613 li a2,7 +8000ac14: 00888893 addi a7,a7,8 +8000ac18: 40d64ce3 blt a2,a3,8000b830 <_svfprintf_r+0x1d9c> +8000ac1c: fff4c693 not a3,s1 +8000ac20: 01c12703 lw a4,28(sp) +8000ac24: 41f6d693 srai a3,a3,0x1f +8000ac28: 00d4f4b3 and s1,s1,a3 +8000ac2c: 409704b3 sub s1,a4,s1 +8000ac30: 48904e63 bgtz s1,8000b0cc <_svfprintf_r+0x1638> +8000ac34: 01c12703 lw a4,28(sp) +8000ac38: 400a7693 andi a3,s4,1024 +8000ac3c: 00eb0db3 add s11,s6,a4 +8000ac40: 4e069a63 bnez a3,8000b134 <_svfprintf_r+0x16a0> +8000ac44: 0cc12483 lw s1,204(sp) +8000ac48: 02012703 lw a4,32(sp) +8000ac4c: 00e4c663 blt s1,a4,8000ac58 <_svfprintf_r+0x11c4> +8000ac50: 001a7693 andi a3,s4,1 +8000ac54: 400682e3 beqz a3,8000b858 <_svfprintf_r+0x1dc4> +8000ac58: 03012683 lw a3,48(sp) +8000ac5c: 02c12703 lw a4,44(sp) +8000ac60: 00700613 li a2,7 +8000ac64: 00d8a023 sw a3,0(a7) +8000ac68: 0e812683 lw a3,232(sp) +8000ac6c: 00e787b3 add a5,a5,a4 +8000ac70: 00e8a223 sw a4,4(a7) +8000ac74: 00168693 addi a3,a3,1 8000ac78: 0ef12623 sw a5,236(sp) 8000ac7c: 0ed12423 sw a3,232(sp) 8000ac80: 00888893 addi a7,a7,8 -8000ac84: fcd95ce3 bge s2,a3,8000ac5c <_svfprintf_r+0xf70> -8000ac88: 0e410613 addi a2,sp,228 -8000ac8c: 000c0593 mv a1,s8 -8000ac90: 000d0513 mv a0,s10 -8000ac94: 25c040ef jal ra,8000eef0 <__ssprint_r> -8000ac98: 06051a63 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000ac9c: ff0d8d93 addi s11,s11,-16 -8000aca0: 0ec12783 lw a5,236(sp) -8000aca4: 0e812683 lw a3,232(sp) -8000aca8: 10c10893 addi a7,sp,268 -8000acac: fbbbcce3 blt s7,s11,8000ac64 <_svfprintf_r+0xf78> -8000acb0: 00812703 lw a4,8(sp) -8000acb4: 01b787b3 add a5,a5,s11 -8000acb8: 00168693 addi a3,a3,1 -8000acbc: 00e8a023 sw a4,0(a7) -8000acc0: 01b8a223 sw s11,4(a7) -8000acc4: 0ef12623 sw a5,236(sp) -8000acc8: 0ed12423 sw a3,232(sp) -8000accc: 00700613 li a2,7 -8000acd0: 00888893 addi a7,a7,8 -8000acd4: a8d65c63 bge a2,a3,80009f6c <_svfprintf_r+0x280> -8000acd8: 0e410613 addi a2,sp,228 -8000acdc: 000c0593 mv a1,s8 -8000ace0: 000d0513 mv a0,s10 -8000ace4: 20c040ef jal ra,8000eef0 <__ssprint_r> -8000ace8: 02051263 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000acec: 0ec12783 lw a5,236(sp) -8000acf0: 10c10893 addi a7,sp,268 -8000acf4: a78ff06f j 80009f6c <_svfprintf_r+0x280> -8000acf8: 0e410613 addi a2,sp,228 -8000acfc: 000c0593 mv a1,s8 -8000ad00: 000d0513 mv a0,s10 -8000ad04: 1ec040ef jal ra,8000eef0 <__ssprint_r> -8000ad08: aa050e63 beqz a0,80009fc4 <_svfprintf_r+0x2d8> -8000ad0c: 01012b83 lw s7,16(sp) -8000ad10: ae0b8463 beqz s7,80009ff8 <_svfprintf_r+0x30c> -8000ad14: 000b8593 mv a1,s7 -8000ad18: 000d0513 mv a0,s10 -8000ad1c: d69f90ef jal ra,80004a84 <_free_r> -8000ad20: ad8ff06f j 80009ff8 <_svfprintf_r+0x30c> -8000ad24: 80015737 lui a4,0x80015 -8000ad28: 01000613 li a2,16 -8000ad2c: 0e812683 lw a3,232(sp) -8000ad30: 30c70e93 addi t4,a4,780 # 8001530c <__BSS_END__+0xffffe6dc> -8000ad34: 09065c63 bge a2,a6,8000adcc <_svfprintf_r+0x10e0> -8000ad38: 04812023 sw s0,64(sp) -8000ad3c: 04912223 sw s1,68(sp) -8000ad40: 000d0413 mv s0,s10 -8000ad44: 000c0493 mv s1,s8 -8000ad48: 01000e13 li t3,16 -8000ad4c: 00700293 li t0,7 -8000ad50: 00080c13 mv s8,a6 -8000ad54: 000e8d13 mv s10,t4 -8000ad58: 00c0006f j 8000ad64 <_svfprintf_r+0x1078> -8000ad5c: ff0c0c13 addi s8,s8,-16 -8000ad60: 058e5a63 bge t3,s8,8000adb4 <_svfprintf_r+0x10c8> -8000ad64: 01078793 addi a5,a5,16 -8000ad68: 00168693 addi a3,a3,1 -8000ad6c: 01a8a023 sw s10,0(a7) -8000ad70: 01c8a223 sw t3,4(a7) -8000ad74: 0ef12623 sw a5,236(sp) -8000ad78: 0ed12423 sw a3,232(sp) -8000ad7c: 00888893 addi a7,a7,8 -8000ad80: fcd2dee3 bge t0,a3,8000ad5c <_svfprintf_r+0x1070> -8000ad84: 0e410613 addi a2,sp,228 -8000ad88: 00048593 mv a1,s1 -8000ad8c: 00040513 mv a0,s0 -8000ad90: 160040ef jal ra,8000eef0 <__ssprint_r> -8000ad94: 160512e3 bnez a0,8000b6f8 <_svfprintf_r+0x1a0c> -8000ad98: 01000e13 li t3,16 -8000ad9c: ff0c0c13 addi s8,s8,-16 -8000ada0: 0ec12783 lw a5,236(sp) -8000ada4: 0e812683 lw a3,232(sp) -8000ada8: 10c10893 addi a7,sp,268 -8000adac: 00700293 li t0,7 -8000adb0: fb8e4ae3 blt t3,s8,8000ad64 <_svfprintf_r+0x1078> -8000adb4: 000c0813 mv a6,s8 -8000adb8: 000d0e93 mv t4,s10 -8000adbc: 00048c13 mv s8,s1 -8000adc0: 00040d13 mv s10,s0 -8000adc4: 04412483 lw s1,68(sp) -8000adc8: 04012403 lw s0,64(sp) -8000adcc: 010787b3 add a5,a5,a6 -8000add0: 00168693 addi a3,a3,1 -8000add4: 01d8a023 sw t4,0(a7) -8000add8: 0108a223 sw a6,4(a7) -8000addc: 0ef12623 sw a5,236(sp) -8000ade0: 0ed12423 sw a3,232(sp) -8000ade4: 00700613 li a2,7 -8000ade8: 00888893 addi a7,a7,8 -8000adec: 90d65263 bge a2,a3,80009ef0 <_svfprintf_r+0x204> -8000adf0: 0e410613 addi a2,sp,228 -8000adf4: 000c0593 mv a1,s8 -8000adf8: 000d0513 mv a0,s10 -8000adfc: 0f4040ef jal ra,8000eef0 <__ssprint_r> -8000ae00: f00516e3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000ae04: 0ec12783 lw a5,236(sp) -8000ae08: 10c10893 addi a7,sp,268 -8000ae0c: 8e4ff06f j 80009ef0 <_svfprintf_r+0x204> -8000ae10: 0e410613 addi a2,sp,228 -8000ae14: 000c0593 mv a1,s8 -8000ae18: 000d0513 mv a0,s10 -8000ae1c: 0d4040ef jal ra,8000eef0 <__ssprint_r> -8000ae20: ee0516e3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000ae24: 0ec12783 lw a5,236(sp) -8000ae28: 10c10893 addi a7,sp,268 -8000ae2c: 930ff06f j 80009f5c <_svfprintf_r+0x270> -8000ae30: 0cc12583 lw a1,204(sp) -8000ae34: 7eb05c63 blez a1,8000b62c <_svfprintf_r+0x1940> -8000ae38: 01c12703 lw a4,28(sp) -8000ae3c: 02012683 lw a3,32(sp) -8000ae40: 00070493 mv s1,a4 -8000ae44: 3ce6c263 blt a3,a4,8000b208 <_svfprintf_r+0x151c> -8000ae48: 02905663 blez s1,8000ae74 <_svfprintf_r+0x1188> -8000ae4c: 0e812683 lw a3,232(sp) -8000ae50: 009787b3 add a5,a5,s1 -8000ae54: 0168a023 sw s6,0(a7) -8000ae58: 00168693 addi a3,a3,1 -8000ae5c: 0098a223 sw s1,4(a7) -8000ae60: 0ef12623 sw a5,236(sp) -8000ae64: 0ed12423 sw a3,232(sp) -8000ae68: 00700613 li a2,7 -8000ae6c: 00888893 addi a7,a7,8 -8000ae70: 40d64ce3 blt a2,a3,8000ba88 <_svfprintf_r+0x1d9c> -8000ae74: fff4c693 not a3,s1 -8000ae78: 01c12703 lw a4,28(sp) -8000ae7c: 41f6d693 srai a3,a3,0x1f -8000ae80: 00d4f4b3 and s1,s1,a3 -8000ae84: 409704b3 sub s1,a4,s1 -8000ae88: 48904e63 bgtz s1,8000b324 <_svfprintf_r+0x1638> -8000ae8c: 01c12703 lw a4,28(sp) -8000ae90: 400a7693 andi a3,s4,1024 -8000ae94: 00eb0db3 add s11,s6,a4 -8000ae98: 4e069a63 bnez a3,8000b38c <_svfprintf_r+0x16a0> -8000ae9c: 0cc12483 lw s1,204(sp) -8000aea0: 02012703 lw a4,32(sp) -8000aea4: 00e4c663 blt s1,a4,8000aeb0 <_svfprintf_r+0x11c4> -8000aea8: 001a7693 andi a3,s4,1 -8000aeac: 400682e3 beqz a3,8000bab0 <_svfprintf_r+0x1dc4> -8000aeb0: 03012683 lw a3,48(sp) -8000aeb4: 02c12703 lw a4,44(sp) -8000aeb8: 00700613 li a2,7 -8000aebc: 00d8a023 sw a3,0(a7) -8000aec0: 0e812683 lw a3,232(sp) -8000aec4: 00e787b3 add a5,a5,a4 -8000aec8: 00e8a223 sw a4,4(a7) -8000aecc: 00168693 addi a3,a3,1 -8000aed0: 0ef12623 sw a5,236(sp) -8000aed4: 0ed12423 sw a3,232(sp) -8000aed8: 00888893 addi a7,a7,8 -8000aedc: 6ad644e3 blt a2,a3,8000bd84 <_svfprintf_r+0x2098> -8000aee0: 02012683 lw a3,32(sp) -8000aee4: 00db0733 add a4,s6,a3 -8000aee8: 409684b3 sub s1,a3,s1 -8000aeec: 41b70733 sub a4,a4,s11 -8000aef0: 00048913 mv s2,s1 -8000aef4: 00975463 bge a4,s1,8000aefc <_svfprintf_r+0x1210> -8000aef8: 00070913 mv s2,a4 -8000aefc: 03205663 blez s2,8000af28 <_svfprintf_r+0x123c> -8000af00: 0e812703 lw a4,232(sp) -8000af04: 012787b3 add a5,a5,s2 -8000af08: 01b8a023 sw s11,0(a7) -8000af0c: 00170713 addi a4,a4,1 -8000af10: 0128a223 sw s2,4(a7) -8000af14: 0ef12623 sw a5,236(sp) -8000af18: 0ee12423 sw a4,232(sp) -8000af1c: 00700693 li a3,7 -8000af20: 00888893 addi a7,a7,8 -8000af24: 6ae6cae3 blt a3,a4,8000bdd8 <_svfprintf_r+0x20ec> -8000af28: fff94713 not a4,s2 -8000af2c: 41f75713 srai a4,a4,0x1f -8000af30: 00e97733 and a4,s2,a4 -8000af34: 40e484b3 sub s1,s1,a4 -8000af38: 00904463 bgtz s1,8000af40 <_svfprintf_r+0x1254> -8000af3c: 860ff06f j 80009f9c <_svfprintf_r+0x2b0> -8000af40: 01000693 li a3,16 -8000af44: 0e812703 lw a4,232(sp) -8000af48: 7e96de63 bge a3,s1,8000b744 <_svfprintf_r+0x1a58> -8000af4c: 01000913 li s2,16 -8000af50: 00700c93 li s9,7 -8000af54: 00c0006f j 8000af60 <_svfprintf_r+0x1274> -8000af58: ff048493 addi s1,s1,-16 -8000af5c: 7e995463 bge s2,s1,8000b744 <_svfprintf_r+0x1a58> -8000af60: 00812683 lw a3,8(sp) -8000af64: 01078793 addi a5,a5,16 -8000af68: 00170713 addi a4,a4,1 -8000af6c: 00d8a023 sw a3,0(a7) -8000af70: 0128a223 sw s2,4(a7) -8000af74: 0ef12623 sw a5,236(sp) -8000af78: 0ee12423 sw a4,232(sp) -8000af7c: 00888893 addi a7,a7,8 -8000af80: fcecdce3 bge s9,a4,8000af58 <_svfprintf_r+0x126c> -8000af84: 0e410613 addi a2,sp,228 -8000af88: 000c0593 mv a1,s8 -8000af8c: 000d0513 mv a0,s10 -8000af90: 761030ef jal ra,8000eef0 <__ssprint_r> -8000af94: d6051ce3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000af98: 0ec12783 lw a5,236(sp) -8000af9c: 0e812703 lw a4,232(sp) -8000afa0: 10c10893 addi a7,sp,268 -8000afa4: fb5ff06f j 8000af58 <_svfprintf_r+0x126c> -8000afa8: 001a7793 andi a5,s4,1 -8000afac: c8079863 bnez a5,8000a43c <_svfprintf_r+0x750> -8000afb0: 00c8a223 sw a2,4(a7) -8000afb4: 0f912623 sw s9,236(sp) -8000afb8: 0e912423 sw s1,232(sp) -8000afbc: 00700793 li a5,7 -8000afc0: 5497ca63 blt a5,s1,8000b514 <_svfprintf_r+0x1828> -8000afc4: 00268693 addi a3,a3,2 -8000afc8: 01088893 addi a7,a7,16 -8000afcc: d44ff06f j 8000a510 <_svfprintf_r+0x824> -8000afd0: d5b05063 blez s11,8000a510 <_svfprintf_r+0x824> -8000afd4: 01000713 li a4,16 -8000afd8: 01b74463 blt a4,s11,8000afe0 <_svfprintf_r+0x12f4> -8000afdc: 6b80106f j 8000c694 <_svfprintf_r+0x29a8> -8000afe0: 00700b13 li s6,7 -8000afe4: 00060493 mv s1,a2 -8000afe8: 0100006f j 8000aff8 <_svfprintf_r+0x130c> -8000afec: ff0d8d93 addi s11,s11,-16 -8000aff0: 11b75ee3 bge a4,s11,8000b90c <_svfprintf_r+0x1c20> -8000aff4: 00148493 addi s1,s1,1 -8000aff8: 00812783 lw a5,8(sp) -8000affc: 010c8c93 addi s9,s9,16 -8000b000: 00e92223 sw a4,4(s2) -8000b004: 00f92023 sw a5,0(s2) -8000b008: 0f912623 sw s9,236(sp) -8000b00c: 0e912423 sw s1,232(sp) -8000b010: 00890913 addi s2,s2,8 -8000b014: fc9b5ce3 bge s6,s1,8000afec <_svfprintf_r+0x1300> -8000b018: 0e410613 addi a2,sp,228 -8000b01c: 000c0593 mv a1,s8 -8000b020: 000d0513 mv a0,s10 -8000b024: 6cd030ef jal ra,8000eef0 <__ssprint_r> -8000b028: ce0512e3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b02c: 0ec12c83 lw s9,236(sp) -8000b030: 0e812483 lw s1,232(sp) -8000b034: 10c10913 addi s2,sp,268 -8000b038: 01000713 li a4,16 -8000b03c: fb1ff06f j 8000afec <_svfprintf_r+0x1300> -8000b040: 01412683 lw a3,20(sp) -8000b044: 010a7793 andi a5,s4,16 -8000b048: 00468713 addi a4,a3,4 -8000b04c: 18079463 bnez a5,8000b1d4 <_svfprintf_r+0x14e8> -8000b050: 040a7793 andi a5,s4,64 -8000b054: 140786e3 beqz a5,8000b9a0 <_svfprintf_r+0x1cb4> -8000b058: 01412783 lw a5,20(sp) -8000b05c: 00000c93 li s9,0 -8000b060: 00e12a23 sw a4,20(sp) -8000b064: 0007d903 lhu s2,0(a5) -8000b068: f80ff06f j 8000a7e8 <_svfprintf_r+0xafc> -8000b06c: 01412683 lw a3,20(sp) -8000b070: 010bf793 andi a5,s7,16 -8000b074: 00468713 addi a4,a3,4 -8000b078: 14079463 bnez a5,8000b1c0 <_svfprintf_r+0x14d4> -8000b07c: 040bf793 andi a5,s7,64 -8000b080: 100780e3 beqz a5,8000b980 <_svfprintf_r+0x1c94> -8000b084: 01412783 lw a5,20(sp) -8000b088: 00000c93 li s9,0 -8000b08c: 00e12a23 sw a4,20(sp) -8000b090: 0007d903 lhu s2,0(a5) -8000b094: 00100793 li a5,1 -8000b098: ed0ff06f j 8000a768 <_svfprintf_r+0xa7c> -8000b09c: 01412683 lw a3,20(sp) -8000b0a0: 010a7793 andi a5,s4,16 -8000b0a4: 00468713 addi a4,a3,4 -8000b0a8: 10079263 bnez a5,8000b1ac <_svfprintf_r+0x14c0> -8000b0ac: 040a7793 andi a5,s4,64 -8000b0b0: 0a0788e3 beqz a5,8000b960 <_svfprintf_r+0x1c74> -8000b0b4: 01412783 lw a5,20(sp) -8000b0b8: 00e12a23 sw a4,20(sp) -8000b0bc: 00079903 lh s2,0(a5) -8000b0c0: 41f95c93 srai s9,s2,0x1f -8000b0c4: 000c8793 mv a5,s9 -8000b0c8: 8407dee3 bgez a5,8000a924 <_svfprintf_r+0xc38> -8000b0cc: 012037b3 snez a5,s2 -8000b0d0: 41900cb3 neg s9,s9 -8000b0d4: 40fc8cb3 sub s9,s9,a5 -8000b0d8: 02d00793 li a5,45 -8000b0dc: 0cf103a3 sb a5,199(sp) -8000b0e0: 41200933 neg s2,s2 -8000b0e4: 000a0b93 mv s7,s4 -8000b0e8: 00100793 li a5,1 -8000b0ec: e80ff06f j 8000a76c <_svfprintf_r+0xa80> -8000b0f0: 0e410613 addi a2,sp,228 -8000b0f4: 000c0593 mv a1,s8 -8000b0f8: 000d0513 mv a0,s10 -8000b0fc: 5f5030ef jal ra,8000eef0 <__ssprint_r> -8000b100: c00516e3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b104: 0ec12c83 lw s9,236(sp) -8000b108: 0e812483 lw s1,232(sp) -8000b10c: 10c10913 addi s2,sp,268 -8000b110: b44ff06f j 8000a454 <_svfprintf_r+0x768> -8000b114: 0e410613 addi a2,sp,228 -8000b118: 000c0593 mv a1,s8 -8000b11c: 000d0513 mv a0,s10 -8000b120: 5d1030ef jal ra,8000eef0 <__ssprint_r> -8000b124: be0514e3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b128: 0ec12c83 lw s9,236(sp) -8000b12c: 0e812483 lw s1,232(sp) -8000b130: 10c10913 addi s2,sp,268 -8000b134: b4cff06f j 8000a480 <_svfprintf_r+0x794> -8000b138: 001a7713 andi a4,s4,1 -8000b13c: 00071463 bnez a4,8000b144 <_svfprintf_r+0x1458> -8000b140: e5dfe06f j 80009f9c <_svfprintf_r+0x2b0> -8000b144: 999ff06f j 8000aadc <_svfprintf_r+0xdf0> -8000b148: 000c8893 mv a7,s9 -8000b14c: facff06f j 8000a8f8 <_svfprintf_r+0xc0c> -8000b150: 03000793 li a5,48 -8000b154: 1af107a3 sb a5,431(sp) -8000b158: 1af10b13 addi s6,sp,431 -8000b15c: e38ff06f j 8000a794 <_svfprintf_r+0xaa8> -8000b160: 00c12683 lw a3,12(sp) -8000b164: 00040b13 mv s6,s0 -8000b168: 41f6d793 srai a5,a3,0x1f -8000b16c: 00d72023 sw a3,0(a4) -8000b170: 00f72223 sw a5,4(a4) -8000b174: e71fe06f j 80009fe4 <_svfprintf_r+0x2f8> -8000b178: 01412703 lw a4,20(sp) -8000b17c: 00072783 lw a5,0(a4) -8000b180: 00470713 addi a4,a4,4 -8000b184: 00e12a23 sw a4,20(sp) -8000b188: 0007a583 lw a1,0(a5) -8000b18c: 0047a603 lw a2,4(a5) -8000b190: 0087a683 lw a3,8(a5) -8000b194: 00c7a783 lw a5,12(a5) -8000b198: 0eb12823 sw a1,240(sp) -8000b19c: 0ec12a23 sw a2,244(sp) -8000b1a0: 0ed12c23 sw a3,248(sp) -8000b1a4: 0ef12e23 sw a5,252(sp) -8000b1a8: f79fe06f j 8000a120 <_svfprintf_r+0x434> -8000b1ac: 0006a903 lw s2,0(a3) -8000b1b0: 00e12a23 sw a4,20(sp) -8000b1b4: 41f95c93 srai s9,s2,0x1f -8000b1b8: 000c8793 mv a5,s9 -8000b1bc: f64ff06f j 8000a920 <_svfprintf_r+0xc34> -8000b1c0: 0006a903 lw s2,0(a3) -8000b1c4: 00000c93 li s9,0 -8000b1c8: 00e12a23 sw a4,20(sp) -8000b1cc: 00100793 li a5,1 -8000b1d0: d98ff06f j 8000a768 <_svfprintf_r+0xa7c> -8000b1d4: 0006a903 lw s2,0(a3) -8000b1d8: 00000c93 li s9,0 -8000b1dc: 00e12a23 sw a4,20(sp) -8000b1e0: e08ff06f j 8000a7e8 <_svfprintf_r+0xafc> -8000b1e4: 03c12783 lw a5,60(sp) -8000b1e8: 00044483 lbu s1,0(s0) -8000b1ec: 00079463 bnez a5,8000b1f4 <_svfprintf_r+0x1508> -8000b1f0: c61fe06f j 80009e50 <_svfprintf_r+0x164> -8000b1f4: 0007c783 lbu a5,0(a5) -8000b1f8: 00079463 bnez a5,8000b200 <_svfprintf_r+0x1514> -8000b1fc: c55fe06f j 80009e50 <_svfprintf_r+0x164> -8000b200: 400a6a13 ori s4,s4,1024 -8000b204: c4dfe06f j 80009e50 <_svfprintf_r+0x164> -8000b208: 00068493 mv s1,a3 -8000b20c: c49040e3 bgtz s1,8000ae4c <_svfprintf_r+0x1160> -8000b210: c65ff06f j 8000ae74 <_svfprintf_r+0x1188> -8000b214: 000c8893 mv a7,s9 -8000b218: 000a0b93 mv s7,s4 -8000b21c: df4ff06f j 8000a810 <_svfprintf_r+0xb24> -8000b220: 800157b7 lui a5,0x80015 -8000b224: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -8000b228: 000c8893 mv a7,s9 -8000b22c: 02f12a23 sw a5,52(sp) -8000b230: 020a7793 andi a5,s4,32 -8000b234: 2c078063 beqz a5,8000b4f4 <_svfprintf_r+0x1808> -8000b238: 01412783 lw a5,20(sp) -8000b23c: 00778b13 addi s6,a5,7 -8000b240: ff8b7b13 andi s6,s6,-8 -8000b244: 000b2903 lw s2,0(s6) -8000b248: 004b2c83 lw s9,4(s6) -8000b24c: 008b0793 addi a5,s6,8 -8000b250: 00f12a23 sw a5,20(sp) -8000b254: 001a7793 andi a5,s4,1 -8000b258: 00078e63 beqz a5,8000b274 <_svfprintf_r+0x1588> -8000b25c: 019967b3 or a5,s2,s9 -8000b260: 00078a63 beqz a5,8000b274 <_svfprintf_r+0x1588> -8000b264: 03000793 li a5,48 -8000b268: 0cf10423 sb a5,200(sp) -8000b26c: 0c9104a3 sb s1,201(sp) -8000b270: 002a6a13 ori s4,s4,2 -8000b274: bffa7b93 andi s7,s4,-1025 -8000b278: 00200793 li a5,2 -8000b27c: cecff06f j 8000a768 <_svfprintf_r+0xa7c> -8000b280: 0e410613 addi a2,sp,228 -8000b284: 000c0593 mv a1,s8 -8000b288: 000d0513 mv a0,s10 -8000b28c: 465030ef jal ra,8000eef0 <__ssprint_r> -8000b290: a6051ee3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b294: 0ec12783 lw a5,236(sp) -8000b298: 10c10893 addi a7,sp,268 -8000b29c: 871ff06f j 8000ab0c <_svfprintf_r+0xe20> -8000b2a0: 800157b7 lui a5,0x80015 -8000b2a4: c4078793 addi a5,a5,-960 # 80014c40 <__BSS_END__+0xffffe010> -8000b2a8: 000c8893 mv a7,s9 -8000b2ac: 02f12a23 sw a5,52(sp) -8000b2b0: f81ff06f j 8000b230 <_svfprintf_r+0x1544> -8000b2b4: 000c8893 mv a7,s9 -8000b2b8: d0cff06f j 8000a7c4 <_svfprintf_r+0xad8> -8000b2bc: 00144483 lbu s1,1(s0) -8000b2c0: 020a6a13 ori s4,s4,32 -8000b2c4: 00140413 addi s0,s0,1 -8000b2c8: b89fe06f j 80009e50 <_svfprintf_r+0x164> -8000b2cc: 00144483 lbu s1,1(s0) -8000b2d0: 200a6a13 ori s4,s4,512 -8000b2d4: 00140413 addi s0,s0,1 -8000b2d8: b79fe06f j 80009e50 <_svfprintf_r+0x164> -8000b2dc: 04000593 li a1,64 -8000b2e0: 000d0513 mv a0,s10 -8000b2e4: a0dfc0ef jal ra,80007cf0 <_malloc_r> -8000b2e8: 00ac2023 sw a0,0(s8) -8000b2ec: 00ac2823 sw a0,16(s8) -8000b2f0: 00051463 bnez a0,8000b2f8 <_svfprintf_r+0x160c> -8000b2f4: 3cc0106f j 8000c6c0 <_svfprintf_r+0x29d4> -8000b2f8: 04000713 li a4,64 -8000b2fc: 00ec2a23 sw a4,20(s8) -8000b300: a75fe06f j 80009d74 <_svfprintf_r+0x88> -8000b304: 00600793 li a5,6 -8000b308: 000d8c93 mv s9,s11 -8000b30c: 79b7ee63 bltu a5,s11,8000baa8 <_svfprintf_r+0x1dbc> -8000b310: 80015737 lui a4,0x80015 -8000b314: 000c8a93 mv s5,s9 -8000b318: 01212a23 sw s2,20(sp) -8000b31c: c5470b13 addi s6,a4,-940 # 80014c54 <__BSS_END__+0xffffe024> -8000b320: b9dfe06f j 80009ebc <_svfprintf_r+0x1d0> -8000b324: 01000613 li a2,16 -8000b328: 0e812683 lw a3,232(sp) -8000b32c: 6a965863 bge a2,s1,8000b9dc <_svfprintf_r+0x1cf0> -8000b330: 01000c93 li s9,16 -8000b334: 00700d93 li s11,7 -8000b338: 00c0006f j 8000b344 <_svfprintf_r+0x1658> -8000b33c: ff048493 addi s1,s1,-16 -8000b340: 689cde63 bge s9,s1,8000b9dc <_svfprintf_r+0x1cf0> -8000b344: 00812703 lw a4,8(sp) -8000b348: 01078793 addi a5,a5,16 -8000b34c: 00168693 addi a3,a3,1 -8000b350: 00e8a023 sw a4,0(a7) -8000b354: 0198a223 sw s9,4(a7) -8000b358: 0ef12623 sw a5,236(sp) -8000b35c: 0ed12423 sw a3,232(sp) -8000b360: 00888893 addi a7,a7,8 -8000b364: fcdddce3 bge s11,a3,8000b33c <_svfprintf_r+0x1650> -8000b368: 0e410613 addi a2,sp,228 -8000b36c: 000c0593 mv a1,s8 -8000b370: 000d0513 mv a0,s10 -8000b374: 37d030ef jal ra,8000eef0 <__ssprint_r> -8000b378: 98051ae3 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b37c: 0ec12783 lw a5,236(sp) -8000b380: 0e812683 lw a3,232(sp) -8000b384: 10c10893 addi a7,sp,268 -8000b388: fb5ff06f j 8000b33c <_svfprintf_r+0x1650> -8000b38c: 02012703 lw a4,32(sp) -8000b390: 02412c83 lw s9,36(sp) -8000b394: 01412e23 sw s4,28(sp) -8000b398: 04812023 sw s0,64(sp) -8000b39c: 05312223 sw s3,68(sp) -8000b3a0: 03512223 sw s5,36(sp) -8000b3a4: 02812983 lw s3,40(sp) -8000b3a8: 03612423 sw s6,40(sp) -8000b3ac: 00eb0bb3 add s7,s6,a4 -8000b3b0: 03c12403 lw s0,60(sp) -8000b3b4: 04812a03 lw s4,72(sp) -8000b3b8: 04c12a83 lw s5,76(sp) -8000b3bc: 00700493 li s1,7 -8000b3c0: 01000913 li s2,16 -8000b3c4: 000c0b13 mv s6,s8 -8000b3c8: 080c8863 beqz s9,8000b458 <_svfprintf_r+0x176c> -8000b3cc: 08099863 bnez s3,8000b45c <_svfprintf_r+0x1770> -8000b3d0: fff40413 addi s0,s0,-1 -8000b3d4: fffc8c93 addi s9,s9,-1 -8000b3d8: 0e812703 lw a4,232(sp) -8000b3dc: 014787b3 add a5,a5,s4 -8000b3e0: 0158a023 sw s5,0(a7) -8000b3e4: 00170713 addi a4,a4,1 -8000b3e8: 0148a223 sw s4,4(a7) -8000b3ec: 0ef12623 sw a5,236(sp) -8000b3f0: 0ee12423 sw a4,232(sp) -8000b3f4: 00888893 addi a7,a7,8 -8000b3f8: 14e4c463 blt s1,a4,8000b540 <_svfprintf_r+0x1854> -8000b3fc: 00044683 lbu a3,0(s0) -8000b400: 41bb8633 sub a2,s7,s11 -8000b404: 00068c13 mv s8,a3 -8000b408: 00d65463 bge a2,a3,8000b410 <_svfprintf_r+0x1724> -8000b40c: 00060c13 mv s8,a2 -8000b410: 03805663 blez s8,8000b43c <_svfprintf_r+0x1750> -8000b414: 0e812683 lw a3,232(sp) -8000b418: 018787b3 add a5,a5,s8 -8000b41c: 01b8a023 sw s11,0(a7) -8000b420: 00168693 addi a3,a3,1 -8000b424: 0188a223 sw s8,4(a7) -8000b428: 0ef12623 sw a5,236(sp) -8000b42c: 0ed12423 sw a3,232(sp) -8000b430: 34d4c063 blt s1,a3,8000b770 <_svfprintf_r+0x1a84> -8000b434: 00044683 lbu a3,0(s0) -8000b438: 00888893 addi a7,a7,8 -8000b43c: fffc4613 not a2,s8 -8000b440: 41f65613 srai a2,a2,0x1f -8000b444: 00cc7733 and a4,s8,a2 -8000b448: 40e68c33 sub s8,a3,a4 -8000b44c: 01804c63 bgtz s8,8000b464 <_svfprintf_r+0x1778> -8000b450: 00dd8db3 add s11,s11,a3 -8000b454: f60c9ce3 bnez s9,8000b3cc <_svfprintf_r+0x16e0> -8000b458: 72098c63 beqz s3,8000bb90 <_svfprintf_r+0x1ea4> -8000b45c: fff98993 addi s3,s3,-1 -8000b460: f79ff06f j 8000b3d8 <_svfprintf_r+0x16ec> -8000b464: 0e812683 lw a3,232(sp) -8000b468: 01894863 blt s2,s8,8000b478 <_svfprintf_r+0x178c> -8000b46c: 0580006f j 8000b4c4 <_svfprintf_r+0x17d8> -8000b470: ff0c0c13 addi s8,s8,-16 -8000b474: 05895863 bge s2,s8,8000b4c4 <_svfprintf_r+0x17d8> -8000b478: 00812703 lw a4,8(sp) -8000b47c: 01078793 addi a5,a5,16 -8000b480: 00168693 addi a3,a3,1 -8000b484: 00e8a023 sw a4,0(a7) -8000b488: 0128a223 sw s2,4(a7) -8000b48c: 0ef12623 sw a5,236(sp) -8000b490: 0ed12423 sw a3,232(sp) -8000b494: 00888893 addi a7,a7,8 -8000b498: fcd4dce3 bge s1,a3,8000b470 <_svfprintf_r+0x1784> -8000b49c: 0e410613 addi a2,sp,228 -8000b4a0: 000b0593 mv a1,s6 -8000b4a4: 000d0513 mv a0,s10 -8000b4a8: 249030ef jal ra,8000eef0 <__ssprint_r> -8000b4ac: 5a051c63 bnez a0,8000ba64 <_svfprintf_r+0x1d78> -8000b4b0: ff0c0c13 addi s8,s8,-16 -8000b4b4: 0ec12783 lw a5,236(sp) -8000b4b8: 0e812683 lw a3,232(sp) -8000b4bc: 10c10893 addi a7,sp,268 -8000b4c0: fb894ce3 blt s2,s8,8000b478 <_svfprintf_r+0x178c> -8000b4c4: 00812703 lw a4,8(sp) -8000b4c8: 018787b3 add a5,a5,s8 -8000b4cc: 00168693 addi a3,a3,1 -8000b4d0: 00e8a023 sw a4,0(a7) -8000b4d4: 0188a223 sw s8,4(a7) -8000b4d8: 0ef12623 sw a5,236(sp) -8000b4dc: 0ed12423 sw a3,232(sp) -8000b4e0: 76d4c463 blt s1,a3,8000bc48 <_svfprintf_r+0x1f5c> -8000b4e4: 00044683 lbu a3,0(s0) -8000b4e8: 00888893 addi a7,a7,8 -8000b4ec: 00dd8db3 add s11,s11,a3 -8000b4f0: f65ff06f j 8000b454 <_svfprintf_r+0x1768> -8000b4f4: 01412683 lw a3,20(sp) -8000b4f8: 010a7793 andi a5,s4,16 -8000b4fc: 00468713 addi a4,a3,4 -8000b500: 20078463 beqz a5,8000b708 <_svfprintf_r+0x1a1c> -8000b504: 0006a903 lw s2,0(a3) -8000b508: 00000c93 li s9,0 -8000b50c: 00e12a23 sw a4,20(sp) -8000b510: d45ff06f j 8000b254 <_svfprintf_r+0x1568> -8000b514: 0e410613 addi a2,sp,228 -8000b518: 000c0593 mv a1,s8 -8000b51c: 000d0513 mv a0,s10 -8000b520: 1d1030ef jal ra,8000eef0 <__ssprint_r> -8000b524: fe051463 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b528: 0e812683 lw a3,232(sp) -8000b52c: 0ec12c83 lw s9,236(sp) -8000b530: 11410893 addi a7,sp,276 -8000b534: 00168693 addi a3,a3,1 -8000b538: 10c10913 addi s2,sp,268 -8000b53c: fd5fe06f j 8000a510 <_svfprintf_r+0x824> -8000b540: 0e410613 addi a2,sp,228 -8000b544: 000b0593 mv a1,s6 -8000b548: 000d0513 mv a0,s10 -8000b54c: 1a5030ef jal ra,8000eef0 <__ssprint_r> -8000b550: 50051a63 bnez a0,8000ba64 <_svfprintf_r+0x1d78> -8000b554: 0ec12783 lw a5,236(sp) -8000b558: 10c10893 addi a7,sp,268 -8000b55c: ea1ff06f j 8000b3fc <_svfprintf_r+0x1710> -8000b560: 1b010b13 addi s6,sp,432 -8000b564: 00000793 li a5,0 -8000b568: 00812823 sw s0,16(sp) -8000b56c: 00912e23 sw s1,28(sp) -8000b570: 000b0413 mv s0,s6 -8000b574: 03312223 sw s3,36(sp) -8000b578: 000c0b13 mv s6,s8 -8000b57c: 00090493 mv s1,s2 -8000b580: 000c8993 mv s3,s9 -8000b584: 400bfa13 andi s4,s7,1024 -8000b588: 03c12c83 lw s9,60(sp) -8000b58c: 0ff00a93 li s5,255 -8000b590: 00088c13 mv s8,a7 -8000b594: 00078913 mv s2,a5 -8000b598: 0240006f j 8000b5bc <_svfprintf_r+0x18d0> -8000b59c: 00a00613 li a2,10 -8000b5a0: 00000693 li a3,0 -8000b5a4: 00048513 mv a0,s1 -8000b5a8: 00098593 mv a1,s3 -8000b5ac: 655040ef jal ra,80010400 <__udivdi3> -8000b5b0: 4c098063 beqz s3,8000ba70 <_svfprintf_r+0x1d84> -8000b5b4: 00050493 mv s1,a0 -8000b5b8: 00058993 mv s3,a1 -8000b5bc: 00a00613 li a2,10 -8000b5c0: 00000693 li a3,0 -8000b5c4: 00048513 mv a0,s1 -8000b5c8: 00098593 mv a1,s3 -8000b5cc: 268050ef jal ra,80010834 <__umoddi3> -8000b5d0: 03050513 addi a0,a0,48 -8000b5d4: fea40fa3 sb a0,-1(s0) -8000b5d8: 00190913 addi s2,s2,1 -8000b5dc: fff40413 addi s0,s0,-1 -8000b5e0: fa0a0ee3 beqz s4,8000b59c <_svfprintf_r+0x18b0> -8000b5e4: 000cc683 lbu a3,0(s9) -8000b5e8: fad91ae3 bne s2,a3,8000b59c <_svfprintf_r+0x18b0> -8000b5ec: fb5908e3 beq s2,s5,8000b59c <_svfprintf_r+0x18b0> -8000b5f0: 42099a63 bnez s3,8000ba24 <_svfprintf_r+0x1d38> -8000b5f4: 00900793 li a5,9 -8000b5f8: 4297e663 bltu a5,s1,8000ba24 <_svfprintf_r+0x1d38> -8000b5fc: 000c0893 mv a7,s8 -8000b600: 1b010793 addi a5,sp,432 -8000b604: 000b0c13 mv s8,s6 -8000b608: 00040b13 mv s6,s0 -8000b60c: 03912e23 sw s9,60(sp) -8000b610: 01c12483 lw s1,28(sp) -8000b614: 02412983 lw s3,36(sp) -8000b618: 01012403 lw s0,16(sp) -8000b61c: 03212023 sw s2,32(sp) -8000b620: 41678cb3 sub s9,a5,s6 -8000b624: 000b8a13 mv s4,s7 -8000b628: 96cff06f j 8000a794 <_svfprintf_r+0xaa8> -8000b62c: 0e812683 lw a3,232(sp) -8000b630: 80015637 lui a2,0x80015 -8000b634: c5c60613 addi a2,a2,-932 # 80014c5c <__BSS_END__+0xffffe02c> -8000b638: 00c8a023 sw a2,0(a7) -8000b63c: 00178793 addi a5,a5,1 -8000b640: 00100613 li a2,1 -8000b644: 00168693 addi a3,a3,1 -8000b648: 00c8a223 sw a2,4(a7) -8000b64c: 0ef12623 sw a5,236(sp) -8000b650: 0ed12423 sw a3,232(sp) -8000b654: 00700613 li a2,7 -8000b658: 00888893 addi a7,a7,8 -8000b65c: 06d64c63 blt a2,a3,8000b6d4 <_svfprintf_r+0x19e8> -8000b660: 20059863 bnez a1,8000b870 <_svfprintf_r+0x1b84> -8000b664: 02012703 lw a4,32(sp) -8000b668: 001a7693 andi a3,s4,1 -8000b66c: 00e6e6b3 or a3,a3,a4 -8000b670: 00069463 bnez a3,8000b678 <_svfprintf_r+0x198c> -8000b674: 929fe06f j 80009f9c <_svfprintf_r+0x2b0> -8000b678: 03012683 lw a3,48(sp) -8000b67c: 02c12703 lw a4,44(sp) -8000b680: 00700613 li a2,7 -8000b684: 00d8a023 sw a3,0(a7) -8000b688: 0e812683 lw a3,232(sp) -8000b68c: 00e787b3 add a5,a5,a4 -8000b690: 00e8a223 sw a4,4(a7) -8000b694: 00168693 addi a3,a3,1 -8000b698: 0ef12623 sw a5,236(sp) -8000b69c: 0ed12423 sw a3,232(sp) -8000b6a0: 4ad64e63 blt a2,a3,8000bb5c <_svfprintf_r+0x1e70> -8000b6a4: 00888893 addi a7,a7,8 -8000b6a8: 02012703 lw a4,32(sp) -8000b6ac: 00168693 addi a3,a3,1 -8000b6b0: 0168a023 sw s6,0(a7) -8000b6b4: 00e787b3 add a5,a5,a4 -8000b6b8: 00e8a223 sw a4,4(a7) -8000b6bc: 0ef12623 sw a5,236(sp) -8000b6c0: 0ed12423 sw a3,232(sp) -8000b6c4: 00700713 li a4,7 -8000b6c8: 00d74463 blt a4,a3,8000b6d0 <_svfprintf_r+0x19e4> -8000b6cc: 8cdfe06f j 80009f98 <_svfprintf_r+0x2ac> -8000b6d0: e65fe06f j 8000a534 <_svfprintf_r+0x848> -8000b6d4: 0e410613 addi a2,sp,228 -8000b6d8: 000c0593 mv a1,s8 -8000b6dc: 000d0513 mv a0,s10 -8000b6e0: 011030ef jal ra,8000eef0 <__ssprint_r> -8000b6e4: e2051463 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b6e8: 0cc12583 lw a1,204(sp) -8000b6ec: 0ec12783 lw a5,236(sp) -8000b6f0: 10c10893 addi a7,sp,268 -8000b6f4: f6dff06f j 8000b660 <_svfprintf_r+0x1974> -8000b6f8: 01012b83 lw s7,16(sp) -8000b6fc: 00040d13 mv s10,s0 -8000b700: 00048c13 mv s8,s1 -8000b704: e0cff06f j 8000ad10 <_svfprintf_r+0x1024> -8000b708: 040a7793 andi a5,s4,64 -8000b70c: 22078c63 beqz a5,8000b944 <_svfprintf_r+0x1c58> +8000ac84: 6ad644e3 blt a2,a3,8000bb2c <_svfprintf_r+0x2098> +8000ac88: 02012683 lw a3,32(sp) +8000ac8c: 00db0733 add a4,s6,a3 +8000ac90: 409684b3 sub s1,a3,s1 +8000ac94: 41b70733 sub a4,a4,s11 +8000ac98: 00048913 mv s2,s1 +8000ac9c: 00975463 bge a4,s1,8000aca4 <_svfprintf_r+0x1210> +8000aca0: 00070913 mv s2,a4 +8000aca4: 03205663 blez s2,8000acd0 <_svfprintf_r+0x123c> +8000aca8: 0e812703 lw a4,232(sp) +8000acac: 012787b3 add a5,a5,s2 +8000acb0: 01b8a023 sw s11,0(a7) +8000acb4: 00170713 addi a4,a4,1 +8000acb8: 0128a223 sw s2,4(a7) +8000acbc: 0ef12623 sw a5,236(sp) +8000acc0: 0ee12423 sw a4,232(sp) +8000acc4: 00700693 li a3,7 +8000acc8: 00888893 addi a7,a7,8 +8000accc: 6ae6cae3 blt a3,a4,8000bb80 <_svfprintf_r+0x20ec> +8000acd0: fff94713 not a4,s2 +8000acd4: 41f75713 srai a4,a4,0x1f +8000acd8: 00e97733 and a4,s2,a4 +8000acdc: 40e484b3 sub s1,s1,a4 +8000ace0: 00904463 bgtz s1,8000ace8 <_svfprintf_r+0x1254> +8000ace4: 860ff06f j 80009d44 <_svfprintf_r+0x2b0> +8000ace8: 01000693 li a3,16 +8000acec: 0e812703 lw a4,232(sp) +8000acf0: 7e96de63 bge a3,s1,8000b4ec <_svfprintf_r+0x1a58> +8000acf4: 01000913 li s2,16 +8000acf8: 00700c93 li s9,7 +8000acfc: 00c0006f j 8000ad08 <_svfprintf_r+0x1274> +8000ad00: ff048493 addi s1,s1,-16 +8000ad04: 7e995463 bge s2,s1,8000b4ec <_svfprintf_r+0x1a58> +8000ad08: 00812683 lw a3,8(sp) +8000ad0c: 01078793 addi a5,a5,16 +8000ad10: 00170713 addi a4,a4,1 +8000ad14: 00d8a023 sw a3,0(a7) +8000ad18: 0128a223 sw s2,4(a7) +8000ad1c: 0ef12623 sw a5,236(sp) +8000ad20: 0ee12423 sw a4,232(sp) +8000ad24: 00888893 addi a7,a7,8 +8000ad28: fcecdce3 bge s9,a4,8000ad00 <_svfprintf_r+0x126c> +8000ad2c: 0e410613 addi a2,sp,228 +8000ad30: 000c0593 mv a1,s8 +8000ad34: 000d0513 mv a0,s10 +8000ad38: 244040ef jal ra,8000ef7c <__ssprint_r> +8000ad3c: d6051ce3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000ad40: 0ec12783 lw a5,236(sp) +8000ad44: 0e812703 lw a4,232(sp) +8000ad48: 10c10893 addi a7,sp,268 +8000ad4c: fb5ff06f j 8000ad00 <_svfprintf_r+0x126c> +8000ad50: 001a7793 andi a5,s4,1 +8000ad54: c8079863 bnez a5,8000a1e4 <_svfprintf_r+0x750> +8000ad58: 00c8a223 sw a2,4(a7) +8000ad5c: 0f912623 sw s9,236(sp) +8000ad60: 0e912423 sw s1,232(sp) +8000ad64: 00700793 li a5,7 +8000ad68: 5497ca63 blt a5,s1,8000b2bc <_svfprintf_r+0x1828> +8000ad6c: 00268693 addi a3,a3,2 +8000ad70: 01088893 addi a7,a7,16 +8000ad74: d44ff06f j 8000a2b8 <_svfprintf_r+0x824> +8000ad78: d5b05063 blez s11,8000a2b8 <_svfprintf_r+0x824> +8000ad7c: 01000713 li a4,16 +8000ad80: 01b74463 blt a4,s11,8000ad88 <_svfprintf_r+0x12f4> +8000ad84: 6b80106f j 8000c43c <_svfprintf_r+0x29a8> +8000ad88: 00700b13 li s6,7 +8000ad8c: 00060493 mv s1,a2 +8000ad90: 0100006f j 8000ada0 <_svfprintf_r+0x130c> +8000ad94: ff0d8d93 addi s11,s11,-16 +8000ad98: 11b75ee3 bge a4,s11,8000b6b4 <_svfprintf_r+0x1c20> +8000ad9c: 00148493 addi s1,s1,1 +8000ada0: 00812783 lw a5,8(sp) +8000ada4: 010c8c93 addi s9,s9,16 +8000ada8: 00e92223 sw a4,4(s2) +8000adac: 00f92023 sw a5,0(s2) +8000adb0: 0f912623 sw s9,236(sp) +8000adb4: 0e912423 sw s1,232(sp) +8000adb8: 00890913 addi s2,s2,8 +8000adbc: fc9b5ce3 bge s6,s1,8000ad94 <_svfprintf_r+0x1300> +8000adc0: 0e410613 addi a2,sp,228 +8000adc4: 000c0593 mv a1,s8 +8000adc8: 000d0513 mv a0,s10 +8000adcc: 1b0040ef jal ra,8000ef7c <__ssprint_r> +8000add0: ce0512e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000add4: 0ec12c83 lw s9,236(sp) +8000add8: 0e812483 lw s1,232(sp) +8000addc: 10c10913 addi s2,sp,268 +8000ade0: 01000713 li a4,16 +8000ade4: fb1ff06f j 8000ad94 <_svfprintf_r+0x1300> +8000ade8: 01412683 lw a3,20(sp) +8000adec: 010a7793 andi a5,s4,16 +8000adf0: 00468713 addi a4,a3,4 +8000adf4: 18079463 bnez a5,8000af7c <_svfprintf_r+0x14e8> +8000adf8: 040a7793 andi a5,s4,64 +8000adfc: 140786e3 beqz a5,8000b748 <_svfprintf_r+0x1cb4> +8000ae00: 01412783 lw a5,20(sp) +8000ae04: 00000c93 li s9,0 +8000ae08: 00e12a23 sw a4,20(sp) +8000ae0c: 0007d903 lhu s2,0(a5) +8000ae10: f80ff06f j 8000a590 <_svfprintf_r+0xafc> +8000ae14: 01412683 lw a3,20(sp) +8000ae18: 010bf793 andi a5,s7,16 +8000ae1c: 00468713 addi a4,a3,4 +8000ae20: 14079463 bnez a5,8000af68 <_svfprintf_r+0x14d4> +8000ae24: 040bf793 andi a5,s7,64 +8000ae28: 100780e3 beqz a5,8000b728 <_svfprintf_r+0x1c94> +8000ae2c: 01412783 lw a5,20(sp) +8000ae30: 00000c93 li s9,0 +8000ae34: 00e12a23 sw a4,20(sp) +8000ae38: 0007d903 lhu s2,0(a5) +8000ae3c: 00100793 li a5,1 +8000ae40: ed0ff06f j 8000a510 <_svfprintf_r+0xa7c> +8000ae44: 01412683 lw a3,20(sp) +8000ae48: 010a7793 andi a5,s4,16 +8000ae4c: 00468713 addi a4,a3,4 +8000ae50: 10079263 bnez a5,8000af54 <_svfprintf_r+0x14c0> +8000ae54: 040a7793 andi a5,s4,64 +8000ae58: 0a0788e3 beqz a5,8000b708 <_svfprintf_r+0x1c74> +8000ae5c: 01412783 lw a5,20(sp) +8000ae60: 00e12a23 sw a4,20(sp) +8000ae64: 00079903 lh s2,0(a5) +8000ae68: 41f95c93 srai s9,s2,0x1f +8000ae6c: 000c8793 mv a5,s9 +8000ae70: 8407dee3 bgez a5,8000a6cc <_svfprintf_r+0xc38> +8000ae74: 012037b3 snez a5,s2 +8000ae78: 41900cb3 neg s9,s9 +8000ae7c: 40fc8cb3 sub s9,s9,a5 +8000ae80: 02d00793 li a5,45 +8000ae84: 0cf103a3 sb a5,199(sp) +8000ae88: 41200933 neg s2,s2 +8000ae8c: 000a0b93 mv s7,s4 +8000ae90: 00100793 li a5,1 +8000ae94: e80ff06f j 8000a514 <_svfprintf_r+0xa80> +8000ae98: 0e410613 addi a2,sp,228 +8000ae9c: 000c0593 mv a1,s8 +8000aea0: 000d0513 mv a0,s10 +8000aea4: 0d8040ef jal ra,8000ef7c <__ssprint_r> +8000aea8: c00516e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000aeac: 0ec12c83 lw s9,236(sp) +8000aeb0: 0e812483 lw s1,232(sp) +8000aeb4: 10c10913 addi s2,sp,268 +8000aeb8: b44ff06f j 8000a1fc <_svfprintf_r+0x768> +8000aebc: 0e410613 addi a2,sp,228 +8000aec0: 000c0593 mv a1,s8 +8000aec4: 000d0513 mv a0,s10 +8000aec8: 0b4040ef jal ra,8000ef7c <__ssprint_r> +8000aecc: be0514e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000aed0: 0ec12c83 lw s9,236(sp) +8000aed4: 0e812483 lw s1,232(sp) +8000aed8: 10c10913 addi s2,sp,268 +8000aedc: b4cff06f j 8000a228 <_svfprintf_r+0x794> +8000aee0: 001a7713 andi a4,s4,1 +8000aee4: 00071463 bnez a4,8000aeec <_svfprintf_r+0x1458> +8000aee8: e5dfe06f j 80009d44 <_svfprintf_r+0x2b0> +8000aeec: 999ff06f j 8000a884 <_svfprintf_r+0xdf0> +8000aef0: 000c8893 mv a7,s9 +8000aef4: facff06f j 8000a6a0 <_svfprintf_r+0xc0c> +8000aef8: 03000793 li a5,48 +8000aefc: 1af107a3 sb a5,431(sp) +8000af00: 1af10b13 addi s6,sp,431 +8000af04: e38ff06f j 8000a53c <_svfprintf_r+0xaa8> +8000af08: 00c12683 lw a3,12(sp) +8000af0c: 00040b13 mv s6,s0 +8000af10: 41f6d793 srai a5,a3,0x1f +8000af14: 00d72023 sw a3,0(a4) +8000af18: 00f72223 sw a5,4(a4) +8000af1c: e71fe06f j 80009d8c <_svfprintf_r+0x2f8> +8000af20: 01412703 lw a4,20(sp) +8000af24: 00072783 lw a5,0(a4) +8000af28: 00470713 addi a4,a4,4 +8000af2c: 00e12a23 sw a4,20(sp) +8000af30: 0007a583 lw a1,0(a5) +8000af34: 0047a603 lw a2,4(a5) +8000af38: 0087a683 lw a3,8(a5) +8000af3c: 00c7a783 lw a5,12(a5) +8000af40: 0eb12823 sw a1,240(sp) +8000af44: 0ec12a23 sw a2,244(sp) +8000af48: 0ed12c23 sw a3,248(sp) +8000af4c: 0ef12e23 sw a5,252(sp) +8000af50: f79fe06f j 80009ec8 <_svfprintf_r+0x434> +8000af54: 0006a903 lw s2,0(a3) +8000af58: 00e12a23 sw a4,20(sp) +8000af5c: 41f95c93 srai s9,s2,0x1f +8000af60: 000c8793 mv a5,s9 +8000af64: f64ff06f j 8000a6c8 <_svfprintf_r+0xc34> +8000af68: 0006a903 lw s2,0(a3) +8000af6c: 00000c93 li s9,0 +8000af70: 00e12a23 sw a4,20(sp) +8000af74: 00100793 li a5,1 +8000af78: d98ff06f j 8000a510 <_svfprintf_r+0xa7c> +8000af7c: 0006a903 lw s2,0(a3) +8000af80: 00000c93 li s9,0 +8000af84: 00e12a23 sw a4,20(sp) +8000af88: e08ff06f j 8000a590 <_svfprintf_r+0xafc> +8000af8c: 03c12783 lw a5,60(sp) +8000af90: 00044483 lbu s1,0(s0) +8000af94: 00079463 bnez a5,8000af9c <_svfprintf_r+0x1508> +8000af98: c61fe06f j 80009bf8 <_svfprintf_r+0x164> +8000af9c: 0007c783 lbu a5,0(a5) +8000afa0: 00079463 bnez a5,8000afa8 <_svfprintf_r+0x1514> +8000afa4: c55fe06f j 80009bf8 <_svfprintf_r+0x164> +8000afa8: 400a6a13 ori s4,s4,1024 +8000afac: c4dfe06f j 80009bf8 <_svfprintf_r+0x164> +8000afb0: 00068493 mv s1,a3 +8000afb4: c49040e3 bgtz s1,8000abf4 <_svfprintf_r+0x1160> +8000afb8: c65ff06f j 8000ac1c <_svfprintf_r+0x1188> +8000afbc: 000c8893 mv a7,s9 +8000afc0: 000a0b93 mv s7,s4 +8000afc4: df4ff06f j 8000a5b8 <_svfprintf_r+0xb24> +8000afc8: 800157b7 lui a5,0x80015 +8000afcc: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +8000afd0: 000c8893 mv a7,s9 +8000afd4: 02f12a23 sw a5,52(sp) +8000afd8: 020a7793 andi a5,s4,32 +8000afdc: 2c078063 beqz a5,8000b29c <_svfprintf_r+0x1808> +8000afe0: 01412783 lw a5,20(sp) +8000afe4: 00778b13 addi s6,a5,7 +8000afe8: ff8b7b13 andi s6,s6,-8 +8000afec: 000b2903 lw s2,0(s6) +8000aff0: 004b2c83 lw s9,4(s6) +8000aff4: 008b0793 addi a5,s6,8 +8000aff8: 00f12a23 sw a5,20(sp) +8000affc: 001a7793 andi a5,s4,1 +8000b000: 00078e63 beqz a5,8000b01c <_svfprintf_r+0x1588> +8000b004: 019967b3 or a5,s2,s9 +8000b008: 00078a63 beqz a5,8000b01c <_svfprintf_r+0x1588> +8000b00c: 03000793 li a5,48 +8000b010: 0cf10423 sb a5,200(sp) +8000b014: 0c9104a3 sb s1,201(sp) +8000b018: 002a6a13 ori s4,s4,2 +8000b01c: bffa7b93 andi s7,s4,-1025 +8000b020: 00200793 li a5,2 +8000b024: cecff06f j 8000a510 <_svfprintf_r+0xa7c> +8000b028: 0e410613 addi a2,sp,228 +8000b02c: 000c0593 mv a1,s8 +8000b030: 000d0513 mv a0,s10 +8000b034: 749030ef jal ra,8000ef7c <__ssprint_r> +8000b038: a6051ee3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b03c: 0ec12783 lw a5,236(sp) +8000b040: 10c10893 addi a7,sp,268 +8000b044: 871ff06f j 8000a8b4 <_svfprintf_r+0xe20> +8000b048: 800157b7 lui a5,0x80015 +8000b04c: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> +8000b050: 000c8893 mv a7,s9 +8000b054: 02f12a23 sw a5,52(sp) +8000b058: f81ff06f j 8000afd8 <_svfprintf_r+0x1544> +8000b05c: 000c8893 mv a7,s9 +8000b060: d0cff06f j 8000a56c <_svfprintf_r+0xad8> +8000b064: 00144483 lbu s1,1(s0) +8000b068: 020a6a13 ori s4,s4,32 +8000b06c: 00140413 addi s0,s0,1 +8000b070: b89fe06f j 80009bf8 <_svfprintf_r+0x164> +8000b074: 00144483 lbu s1,1(s0) +8000b078: 200a6a13 ori s4,s4,512 +8000b07c: 00140413 addi s0,s0,1 +8000b080: b79fe06f j 80009bf8 <_svfprintf_r+0x164> +8000b084: 04000593 li a1,64 +8000b088: 000d0513 mv a0,s10 +8000b08c: b1dfc0ef jal ra,80007ba8 <_malloc_r> +8000b090: 00ac2023 sw a0,0(s8) +8000b094: 00ac2823 sw a0,16(s8) +8000b098: 00051463 bnez a0,8000b0a0 <_svfprintf_r+0x160c> +8000b09c: 3cc0106f j 8000c468 <_svfprintf_r+0x29d4> +8000b0a0: 04000713 li a4,64 +8000b0a4: 00ec2a23 sw a4,20(s8) +8000b0a8: a75fe06f j 80009b1c <_svfprintf_r+0x88> +8000b0ac: 00600793 li a5,6 +8000b0b0: 000d8c93 mv s9,s11 +8000b0b4: 79b7ee63 bltu a5,s11,8000b850 <_svfprintf_r+0x1dbc> +8000b0b8: 80015737 lui a4,0x80015 +8000b0bc: 000c8a93 mv s5,s9 +8000b0c0: 01212a23 sw s2,20(sp) +8000b0c4: ca070b13 addi s6,a4,-864 # 80014ca0 <__BSS_END__+0xffffe064> +8000b0c8: b9dfe06f j 80009c64 <_svfprintf_r+0x1d0> +8000b0cc: 01000613 li a2,16 +8000b0d0: 0e812683 lw a3,232(sp) +8000b0d4: 6a965863 bge a2,s1,8000b784 <_svfprintf_r+0x1cf0> +8000b0d8: 01000c93 li s9,16 +8000b0dc: 00700d93 li s11,7 +8000b0e0: 00c0006f j 8000b0ec <_svfprintf_r+0x1658> +8000b0e4: ff048493 addi s1,s1,-16 +8000b0e8: 689cde63 bge s9,s1,8000b784 <_svfprintf_r+0x1cf0> +8000b0ec: 00812703 lw a4,8(sp) +8000b0f0: 01078793 addi a5,a5,16 +8000b0f4: 00168693 addi a3,a3,1 +8000b0f8: 00e8a023 sw a4,0(a7) +8000b0fc: 0198a223 sw s9,4(a7) +8000b100: 0ef12623 sw a5,236(sp) +8000b104: 0ed12423 sw a3,232(sp) +8000b108: 00888893 addi a7,a7,8 +8000b10c: fcdddce3 bge s11,a3,8000b0e4 <_svfprintf_r+0x1650> +8000b110: 0e410613 addi a2,sp,228 +8000b114: 000c0593 mv a1,s8 +8000b118: 000d0513 mv a0,s10 +8000b11c: 661030ef jal ra,8000ef7c <__ssprint_r> +8000b120: 98051ae3 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b124: 0ec12783 lw a5,236(sp) +8000b128: 0e812683 lw a3,232(sp) +8000b12c: 10c10893 addi a7,sp,268 +8000b130: fb5ff06f j 8000b0e4 <_svfprintf_r+0x1650> +8000b134: 02012703 lw a4,32(sp) +8000b138: 02412c83 lw s9,36(sp) +8000b13c: 01412e23 sw s4,28(sp) +8000b140: 04812023 sw s0,64(sp) +8000b144: 05312223 sw s3,68(sp) +8000b148: 03512223 sw s5,36(sp) +8000b14c: 02812983 lw s3,40(sp) +8000b150: 03612423 sw s6,40(sp) +8000b154: 00eb0bb3 add s7,s6,a4 +8000b158: 03c12403 lw s0,60(sp) +8000b15c: 04812a03 lw s4,72(sp) +8000b160: 04c12a83 lw s5,76(sp) +8000b164: 00700493 li s1,7 +8000b168: 01000913 li s2,16 +8000b16c: 000c0b13 mv s6,s8 +8000b170: 080c8863 beqz s9,8000b200 <_svfprintf_r+0x176c> +8000b174: 08099863 bnez s3,8000b204 <_svfprintf_r+0x1770> +8000b178: fff40413 addi s0,s0,-1 +8000b17c: fffc8c93 addi s9,s9,-1 +8000b180: 0e812703 lw a4,232(sp) +8000b184: 014787b3 add a5,a5,s4 +8000b188: 0158a023 sw s5,0(a7) +8000b18c: 00170713 addi a4,a4,1 +8000b190: 0148a223 sw s4,4(a7) +8000b194: 0ef12623 sw a5,236(sp) +8000b198: 0ee12423 sw a4,232(sp) +8000b19c: 00888893 addi a7,a7,8 +8000b1a0: 14e4c463 blt s1,a4,8000b2e8 <_svfprintf_r+0x1854> +8000b1a4: 00044683 lbu a3,0(s0) +8000b1a8: 41bb8633 sub a2,s7,s11 +8000b1ac: 00068c13 mv s8,a3 +8000b1b0: 00d65463 bge a2,a3,8000b1b8 <_svfprintf_r+0x1724> +8000b1b4: 00060c13 mv s8,a2 +8000b1b8: 03805663 blez s8,8000b1e4 <_svfprintf_r+0x1750> +8000b1bc: 0e812683 lw a3,232(sp) +8000b1c0: 018787b3 add a5,a5,s8 +8000b1c4: 01b8a023 sw s11,0(a7) +8000b1c8: 00168693 addi a3,a3,1 +8000b1cc: 0188a223 sw s8,4(a7) +8000b1d0: 0ef12623 sw a5,236(sp) +8000b1d4: 0ed12423 sw a3,232(sp) +8000b1d8: 34d4c063 blt s1,a3,8000b518 <_svfprintf_r+0x1a84> +8000b1dc: 00044683 lbu a3,0(s0) +8000b1e0: 00888893 addi a7,a7,8 +8000b1e4: fffc4613 not a2,s8 +8000b1e8: 41f65613 srai a2,a2,0x1f +8000b1ec: 00cc7733 and a4,s8,a2 +8000b1f0: 40e68c33 sub s8,a3,a4 +8000b1f4: 01804c63 bgtz s8,8000b20c <_svfprintf_r+0x1778> +8000b1f8: 00dd8db3 add s11,s11,a3 +8000b1fc: f60c9ce3 bnez s9,8000b174 <_svfprintf_r+0x16e0> +8000b200: 72098c63 beqz s3,8000b938 <_svfprintf_r+0x1ea4> +8000b204: fff98993 addi s3,s3,-1 +8000b208: f79ff06f j 8000b180 <_svfprintf_r+0x16ec> +8000b20c: 0e812683 lw a3,232(sp) +8000b210: 01894863 blt s2,s8,8000b220 <_svfprintf_r+0x178c> +8000b214: 0580006f j 8000b26c <_svfprintf_r+0x17d8> +8000b218: ff0c0c13 addi s8,s8,-16 +8000b21c: 05895863 bge s2,s8,8000b26c <_svfprintf_r+0x17d8> +8000b220: 00812703 lw a4,8(sp) +8000b224: 01078793 addi a5,a5,16 +8000b228: 00168693 addi a3,a3,1 +8000b22c: 00e8a023 sw a4,0(a7) +8000b230: 0128a223 sw s2,4(a7) +8000b234: 0ef12623 sw a5,236(sp) +8000b238: 0ed12423 sw a3,232(sp) +8000b23c: 00888893 addi a7,a7,8 +8000b240: fcd4dce3 bge s1,a3,8000b218 <_svfprintf_r+0x1784> +8000b244: 0e410613 addi a2,sp,228 +8000b248: 000b0593 mv a1,s6 +8000b24c: 000d0513 mv a0,s10 +8000b250: 52d030ef jal ra,8000ef7c <__ssprint_r> +8000b254: 5a051c63 bnez a0,8000b80c <_svfprintf_r+0x1d78> +8000b258: ff0c0c13 addi s8,s8,-16 +8000b25c: 0ec12783 lw a5,236(sp) +8000b260: 0e812683 lw a3,232(sp) +8000b264: 10c10893 addi a7,sp,268 +8000b268: fb894ce3 blt s2,s8,8000b220 <_svfprintf_r+0x178c> +8000b26c: 00812703 lw a4,8(sp) +8000b270: 018787b3 add a5,a5,s8 +8000b274: 00168693 addi a3,a3,1 +8000b278: 00e8a023 sw a4,0(a7) +8000b27c: 0188a223 sw s8,4(a7) +8000b280: 0ef12623 sw a5,236(sp) +8000b284: 0ed12423 sw a3,232(sp) +8000b288: 76d4c463 blt s1,a3,8000b9f0 <_svfprintf_r+0x1f5c> +8000b28c: 00044683 lbu a3,0(s0) +8000b290: 00888893 addi a7,a7,8 +8000b294: 00dd8db3 add s11,s11,a3 +8000b298: f65ff06f j 8000b1fc <_svfprintf_r+0x1768> +8000b29c: 01412683 lw a3,20(sp) +8000b2a0: 010a7793 andi a5,s4,16 +8000b2a4: 00468713 addi a4,a3,4 +8000b2a8: 20078463 beqz a5,8000b4b0 <_svfprintf_r+0x1a1c> +8000b2ac: 0006a903 lw s2,0(a3) +8000b2b0: 00000c93 li s9,0 +8000b2b4: 00e12a23 sw a4,20(sp) +8000b2b8: d45ff06f j 8000affc <_svfprintf_r+0x1568> +8000b2bc: 0e410613 addi a2,sp,228 +8000b2c0: 000c0593 mv a1,s8 +8000b2c4: 000d0513 mv a0,s10 +8000b2c8: 4b5030ef jal ra,8000ef7c <__ssprint_r> +8000b2cc: fe051463 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b2d0: 0e812683 lw a3,232(sp) +8000b2d4: 0ec12c83 lw s9,236(sp) +8000b2d8: 11410893 addi a7,sp,276 +8000b2dc: 00168693 addi a3,a3,1 +8000b2e0: 10c10913 addi s2,sp,268 +8000b2e4: fd5fe06f j 8000a2b8 <_svfprintf_r+0x824> +8000b2e8: 0e410613 addi a2,sp,228 +8000b2ec: 000b0593 mv a1,s6 +8000b2f0: 000d0513 mv a0,s10 +8000b2f4: 489030ef jal ra,8000ef7c <__ssprint_r> +8000b2f8: 50051a63 bnez a0,8000b80c <_svfprintf_r+0x1d78> +8000b2fc: 0ec12783 lw a5,236(sp) +8000b300: 10c10893 addi a7,sp,268 +8000b304: ea1ff06f j 8000b1a4 <_svfprintf_r+0x1710> +8000b308: 1b010b13 addi s6,sp,432 +8000b30c: 00000793 li a5,0 +8000b310: 00812823 sw s0,16(sp) +8000b314: 00912e23 sw s1,28(sp) +8000b318: 000b0413 mv s0,s6 +8000b31c: 03312223 sw s3,36(sp) +8000b320: 000c0b13 mv s6,s8 +8000b324: 00090493 mv s1,s2 +8000b328: 000c8993 mv s3,s9 +8000b32c: 400bfa13 andi s4,s7,1024 +8000b330: 03c12c83 lw s9,60(sp) +8000b334: 0ff00a93 li s5,255 +8000b338: 00088c13 mv s8,a7 +8000b33c: 00078913 mv s2,a5 +8000b340: 0240006f j 8000b364 <_svfprintf_r+0x18d0> +8000b344: 00a00613 li a2,10 +8000b348: 00000693 li a3,0 +8000b34c: 00048513 mv a0,s1 +8000b350: 00098593 mv a1,s3 +8000b354: 170050ef jal ra,800104c4 <__udivdi3> +8000b358: 4c098063 beqz s3,8000b818 <_svfprintf_r+0x1d84> +8000b35c: 00050493 mv s1,a0 +8000b360: 00058993 mv s3,a1 +8000b364: 00a00613 li a2,10 +8000b368: 00000693 li a3,0 +8000b36c: 00048513 mv a0,s1 +8000b370: 00098593 mv a1,s3 +8000b374: 584050ef jal ra,800108f8 <__umoddi3> +8000b378: 03050513 addi a0,a0,48 +8000b37c: fea40fa3 sb a0,-1(s0) +8000b380: 00190913 addi s2,s2,1 +8000b384: fff40413 addi s0,s0,-1 +8000b388: fa0a0ee3 beqz s4,8000b344 <_svfprintf_r+0x18b0> +8000b38c: 000cc683 lbu a3,0(s9) +8000b390: fad91ae3 bne s2,a3,8000b344 <_svfprintf_r+0x18b0> +8000b394: fb5908e3 beq s2,s5,8000b344 <_svfprintf_r+0x18b0> +8000b398: 42099a63 bnez s3,8000b7cc <_svfprintf_r+0x1d38> +8000b39c: 00900793 li a5,9 +8000b3a0: 4297e663 bltu a5,s1,8000b7cc <_svfprintf_r+0x1d38> +8000b3a4: 000c0893 mv a7,s8 +8000b3a8: 1b010793 addi a5,sp,432 +8000b3ac: 000b0c13 mv s8,s6 +8000b3b0: 00040b13 mv s6,s0 +8000b3b4: 03912e23 sw s9,60(sp) +8000b3b8: 01c12483 lw s1,28(sp) +8000b3bc: 02412983 lw s3,36(sp) +8000b3c0: 01012403 lw s0,16(sp) +8000b3c4: 03212023 sw s2,32(sp) +8000b3c8: 41678cb3 sub s9,a5,s6 +8000b3cc: 000b8a13 mv s4,s7 +8000b3d0: 96cff06f j 8000a53c <_svfprintf_r+0xaa8> +8000b3d4: 0e812683 lw a3,232(sp) +8000b3d8: 80015637 lui a2,0x80015 +8000b3dc: ca860613 addi a2,a2,-856 # 80014ca8 <__BSS_END__+0xffffe06c> +8000b3e0: 00c8a023 sw a2,0(a7) +8000b3e4: 00178793 addi a5,a5,1 +8000b3e8: 00100613 li a2,1 +8000b3ec: 00168693 addi a3,a3,1 +8000b3f0: 00c8a223 sw a2,4(a7) +8000b3f4: 0ef12623 sw a5,236(sp) +8000b3f8: 0ed12423 sw a3,232(sp) +8000b3fc: 00700613 li a2,7 +8000b400: 00888893 addi a7,a7,8 +8000b404: 06d64c63 blt a2,a3,8000b47c <_svfprintf_r+0x19e8> +8000b408: 20059863 bnez a1,8000b618 <_svfprintf_r+0x1b84> +8000b40c: 02012703 lw a4,32(sp) +8000b410: 001a7693 andi a3,s4,1 +8000b414: 00e6e6b3 or a3,a3,a4 +8000b418: 00069463 bnez a3,8000b420 <_svfprintf_r+0x198c> +8000b41c: 929fe06f j 80009d44 <_svfprintf_r+0x2b0> +8000b420: 03012683 lw a3,48(sp) +8000b424: 02c12703 lw a4,44(sp) +8000b428: 00700613 li a2,7 +8000b42c: 00d8a023 sw a3,0(a7) +8000b430: 0e812683 lw a3,232(sp) +8000b434: 00e787b3 add a5,a5,a4 +8000b438: 00e8a223 sw a4,4(a7) +8000b43c: 00168693 addi a3,a3,1 +8000b440: 0ef12623 sw a5,236(sp) +8000b444: 0ed12423 sw a3,232(sp) +8000b448: 4ad64e63 blt a2,a3,8000b904 <_svfprintf_r+0x1e70> +8000b44c: 00888893 addi a7,a7,8 +8000b450: 02012703 lw a4,32(sp) +8000b454: 00168693 addi a3,a3,1 +8000b458: 0168a023 sw s6,0(a7) +8000b45c: 00e787b3 add a5,a5,a4 +8000b460: 00e8a223 sw a4,4(a7) +8000b464: 0ef12623 sw a5,236(sp) +8000b468: 0ed12423 sw a3,232(sp) +8000b46c: 00700713 li a4,7 +8000b470: 00d74463 blt a4,a3,8000b478 <_svfprintf_r+0x19e4> +8000b474: 8cdfe06f j 80009d40 <_svfprintf_r+0x2ac> +8000b478: e65fe06f j 8000a2dc <_svfprintf_r+0x848> +8000b47c: 0e410613 addi a2,sp,228 +8000b480: 000c0593 mv a1,s8 +8000b484: 000d0513 mv a0,s10 +8000b488: 2f5030ef jal ra,8000ef7c <__ssprint_r> +8000b48c: e2051463 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b490: 0cc12583 lw a1,204(sp) +8000b494: 0ec12783 lw a5,236(sp) +8000b498: 10c10893 addi a7,sp,268 +8000b49c: f6dff06f j 8000b408 <_svfprintf_r+0x1974> +8000b4a0: 01012b83 lw s7,16(sp) +8000b4a4: 00040d13 mv s10,s0 +8000b4a8: 00048c13 mv s8,s1 +8000b4ac: e0cff06f j 8000aab8 <_svfprintf_r+0x1024> +8000b4b0: 040a7793 andi a5,s4,64 +8000b4b4: 22078c63 beqz a5,8000b6ec <_svfprintf_r+0x1c58> +8000b4b8: 01412783 lw a5,20(sp) +8000b4bc: 00000c93 li s9,0 +8000b4c0: 00e12a23 sw a4,20(sp) +8000b4c4: 0007d903 lhu s2,0(a5) +8000b4c8: b35ff06f j 8000affc <_svfprintf_r+0x1568> +8000b4cc: 0e410613 addi a2,sp,228 +8000b4d0: 000c0593 mv a1,s8 +8000b4d4: 000d0513 mv a0,s10 +8000b4d8: 2a5030ef jal ra,8000ef7c <__ssprint_r> +8000b4dc: dc051c63 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b4e0: 0ec12783 lw a5,236(sp) +8000b4e4: 10c10893 addi a7,sp,268 +8000b4e8: b90ff06f j 8000a878 <_svfprintf_r+0xde4> +8000b4ec: 00812683 lw a3,8(sp) +8000b4f0: 009787b3 add a5,a5,s1 +8000b4f4: 0098a223 sw s1,4(a7) +8000b4f8: 00d8a023 sw a3,0(a7) +8000b4fc: 00170713 addi a4,a4,1 +8000b500: 0ef12623 sw a5,236(sp) +8000b504: 0ee12423 sw a4,232(sp) +8000b508: 00700693 li a3,7 +8000b50c: 00e6c463 blt a3,a4,8000b514 <_svfprintf_r+0x1a80> +8000b510: 831fe06f j 80009d40 <_svfprintf_r+0x2ac> +8000b514: dc9fe06f j 8000a2dc <_svfprintf_r+0x848> +8000b518: 0e410613 addi a2,sp,228 +8000b51c: 000b0593 mv a1,s6 +8000b520: 000d0513 mv a0,s10 +8000b524: 259030ef jal ra,8000ef7c <__ssprint_r> +8000b528: 2e051263 bnez a0,8000b80c <_svfprintf_r+0x1d78> +8000b52c: 00044683 lbu a3,0(s0) +8000b530: 0ec12783 lw a5,236(sp) +8000b534: 10c10893 addi a7,sp,268 +8000b538: cadff06f j 8000b1e4 <_svfprintf_r+0x1750> +8000b53c: 0f012783 lw a5,240(sp) +8000b540: 0a010593 addi a1,sp,160 +8000b544: 0b010513 addi a0,sp,176 +8000b548: 0af12823 sw a5,176(sp) +8000b54c: 0f412783 lw a5,244(sp) +8000b550: 0a012023 sw zero,160(sp) +8000b554: 0a012223 sw zero,164(sp) +8000b558: 0af12a23 sw a5,180(sp) +8000b55c: 0f812783 lw a5,248(sp) +8000b560: 0a012423 sw zero,168(sp) +8000b564: 0a012623 sw zero,172(sp) +8000b568: 0af12c23 sw a5,184(sp) +8000b56c: 0fc12783 lw a5,252(sp) +8000b570: 0af12e23 sw a5,188(sp) +8000b574: 648060ef jal ra,80011bbc <__letf2> +8000b578: 01012883 lw a7,16(sp) +8000b57c: 52054263 bltz a0,8000baa0 <_svfprintf_r+0x200c> +8000b580: 0c714783 lbu a5,199(sp) +8000b584: 04700713 li a4,71 +8000b588: 28975e63 bge a4,s1,8000b824 <_svfprintf_r+0x1d90> +8000b58c: 80015737 lui a4,0x80015 +8000b590: c6c70b13 addi s6,a4,-916 # 80014c6c <__BSS_END__+0xffffe030> +8000b594: 00012823 sw zero,16(sp) +8000b598: 02012423 sw zero,40(sp) +8000b59c: 02012223 sw zero,36(sp) +8000b5a0: 00012e23 sw zero,28(sp) +8000b5a4: f7fa7a13 andi s4,s4,-129 +8000b5a8: 00300a93 li s5,3 +8000b5ac: 00300c93 li s9,3 +8000b5b0: 00000d93 li s11,0 +8000b5b4: 00078463 beqz a5,8000b5bc <_svfprintf_r+0x1b28> +8000b5b8: e79fe06f j 8000a430 <_svfprintf_r+0x99c> +8000b5bc: ebcfe06f j 80009c78 <_svfprintf_r+0x1e4> +8000b5c0: 00c12783 lw a5,12(sp) +8000b5c4: 00040b13 mv s6,s0 +8000b5c8: 00f72023 sw a5,0(a4) +8000b5cc: fc0fe06f j 80009d8c <_svfprintf_r+0x2f8> +8000b5d0: 000b0513 mv a0,s6 +8000b5d4: 05912023 sw s9,64(sp) +8000b5d8: b88fe0ef jal ra,80009960 +8000b5dc: 0c714783 lbu a5,199(sp) +8000b5e0: fff54a93 not s5,a0 +8000b5e4: 41fada93 srai s5,s5,0x1f +8000b5e8: 01212a23 sw s2,20(sp) +8000b5ec: 00012823 sw zero,16(sp) +8000b5f0: 02012423 sw zero,40(sp) +8000b5f4: 02012223 sw zero,36(sp) +8000b5f8: 00012e23 sw zero,28(sp) +8000b5fc: 04012883 lw a7,64(sp) +8000b600: 00050c93 mv s9,a0 +8000b604: 01557ab3 and s5,a0,s5 +8000b608: 00000d93 li s11,0 +8000b60c: 00078463 beqz a5,8000b614 <_svfprintf_r+0x1b80> +8000b610: e21fe06f j 8000a430 <_svfprintf_r+0x99c> +8000b614: e64fe06f j 80009c78 <_svfprintf_r+0x1e4> +8000b618: 03012683 lw a3,48(sp) +8000b61c: 02c12703 lw a4,44(sp) +8000b620: 00700613 li a2,7 +8000b624: 00d8a023 sw a3,0(a7) +8000b628: 0e812683 lw a3,232(sp) +8000b62c: 00e787b3 add a5,a5,a4 +8000b630: 00e8a223 sw a4,4(a7) +8000b634: 00168693 addi a3,a3,1 +8000b638: 0ef12623 sw a5,236(sp) +8000b63c: 0ed12423 sw a3,232(sp) +8000b640: 00888893 addi a7,a7,8 +8000b644: 2cd64063 blt a2,a3,8000b904 <_svfprintf_r+0x1e70> +8000b648: e005d4e3 bgez a1,8000b450 <_svfprintf_r+0x19bc> +8000b64c: ff000613 li a2,-16 +8000b650: 40b004b3 neg s1,a1 +8000b654: 26c5d4e3 bge a1,a2,8000c0bc <_svfprintf_r+0x2628> +8000b658: 01000913 li s2,16 +8000b65c: 00700c93 li s9,7 +8000b660: 00c0006f j 8000b66c <_svfprintf_r+0x1bd8> +8000b664: ff048493 addi s1,s1,-16 +8000b668: 24995ae3 bge s2,s1,8000c0bc <_svfprintf_r+0x2628> +8000b66c: 00812703 lw a4,8(sp) +8000b670: 01078793 addi a5,a5,16 +8000b674: 00168693 addi a3,a3,1 +8000b678: 00e8a023 sw a4,0(a7) +8000b67c: 0128a223 sw s2,4(a7) +8000b680: 0ef12623 sw a5,236(sp) +8000b684: 0ed12423 sw a3,232(sp) +8000b688: 00888893 addi a7,a7,8 +8000b68c: fcdcdce3 bge s9,a3,8000b664 <_svfprintf_r+0x1bd0> +8000b690: 0e410613 addi a2,sp,228 +8000b694: 000c0593 mv a1,s8 +8000b698: 000d0513 mv a0,s10 +8000b69c: 0e1030ef jal ra,8000ef7c <__ssprint_r> +8000b6a0: c0051a63 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b6a4: 0ec12783 lw a5,236(sp) +8000b6a8: 0e812683 lw a3,232(sp) +8000b6ac: 10c10893 addi a7,sp,268 +8000b6b0: fb5ff06f j 8000b664 <_svfprintf_r+0x1bd0> +8000b6b4: 00148693 addi a3,s1,1 +8000b6b8: 00890713 addi a4,s2,8 +8000b6bc: 00812783 lw a5,8(sp) +8000b6c0: 01bc8cb3 add s9,s9,s11 +8000b6c4: 01b92223 sw s11,4(s2) +8000b6c8: 00f92023 sw a5,0(s2) +8000b6cc: 0f912623 sw s9,236(sp) +8000b6d0: 0ed12423 sw a3,232(sp) +8000b6d4: 00700793 li a5,7 +8000b6d8: bed7c2e3 blt a5,a3,8000b2bc <_svfprintf_r+0x1828> +8000b6dc: 00168693 addi a3,a3,1 +8000b6e0: 00870893 addi a7,a4,8 +8000b6e4: 00070913 mv s2,a4 +8000b6e8: bd1fe06f j 8000a2b8 <_svfprintf_r+0x824> +8000b6ec: 200a7793 andi a5,s4,512 +8000b6f0: 1c078e63 beqz a5,8000b8cc <_svfprintf_r+0x1e38> +8000b6f4: 01412783 lw a5,20(sp) +8000b6f8: 00000c93 li s9,0 +8000b6fc: 00e12a23 sw a4,20(sp) +8000b700: 0007c903 lbu s2,0(a5) +8000b704: 8f9ff06f j 8000affc <_svfprintf_r+0x1568> +8000b708: 200a7793 andi a5,s4,512 +8000b70c: 1a078463 beqz a5,8000b8b4 <_svfprintf_r+0x1e20> 8000b710: 01412783 lw a5,20(sp) -8000b714: 00000c93 li s9,0 -8000b718: 00e12a23 sw a4,20(sp) -8000b71c: 0007d903 lhu s2,0(a5) -8000b720: b35ff06f j 8000b254 <_svfprintf_r+0x1568> -8000b724: 0e410613 addi a2,sp,228 -8000b728: 000c0593 mv a1,s8 -8000b72c: 000d0513 mv a0,s10 -8000b730: 7c0030ef jal ra,8000eef0 <__ssprint_r> -8000b734: dc051c63 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b738: 0ec12783 lw a5,236(sp) -8000b73c: 10c10893 addi a7,sp,268 -8000b740: b90ff06f j 8000aad0 <_svfprintf_r+0xde4> -8000b744: 00812683 lw a3,8(sp) -8000b748: 009787b3 add a5,a5,s1 -8000b74c: 0098a223 sw s1,4(a7) -8000b750: 00d8a023 sw a3,0(a7) -8000b754: 00170713 addi a4,a4,1 -8000b758: 0ef12623 sw a5,236(sp) -8000b75c: 0ee12423 sw a4,232(sp) -8000b760: 00700693 li a3,7 -8000b764: 00e6c463 blt a3,a4,8000b76c <_svfprintf_r+0x1a80> -8000b768: 831fe06f j 80009f98 <_svfprintf_r+0x2ac> -8000b76c: dc9fe06f j 8000a534 <_svfprintf_r+0x848> -8000b770: 0e410613 addi a2,sp,228 -8000b774: 000b0593 mv a1,s6 -8000b778: 000d0513 mv a0,s10 -8000b77c: 774030ef jal ra,8000eef0 <__ssprint_r> -8000b780: 2e051263 bnez a0,8000ba64 <_svfprintf_r+0x1d78> -8000b784: 00044683 lbu a3,0(s0) -8000b788: 0ec12783 lw a5,236(sp) -8000b78c: 10c10893 addi a7,sp,268 -8000b790: cadff06f j 8000b43c <_svfprintf_r+0x1750> -8000b794: 0f012783 lw a5,240(sp) -8000b798: 0a010593 addi a1,sp,160 -8000b79c: 0b010513 addi a0,sp,176 -8000b7a0: 0af12823 sw a5,176(sp) -8000b7a4: 0f412783 lw a5,244(sp) -8000b7a8: 0a012023 sw zero,160(sp) -8000b7ac: 0a012223 sw zero,164(sp) -8000b7b0: 0af12a23 sw a5,180(sp) -8000b7b4: 0f812783 lw a5,248(sp) -8000b7b8: 0a012423 sw zero,168(sp) -8000b7bc: 0a012623 sw zero,172(sp) -8000b7c0: 0af12c23 sw a5,184(sp) -8000b7c4: 0fc12783 lw a5,252(sp) -8000b7c8: 0af12e23 sw a5,188(sp) -8000b7cc: 32c060ef jal ra,80011af8 <__letf2> -8000b7d0: 01012883 lw a7,16(sp) -8000b7d4: 52054263 bltz a0,8000bcf8 <_svfprintf_r+0x200c> -8000b7d8: 0c714783 lbu a5,199(sp) -8000b7dc: 04700713 li a4,71 -8000b7e0: 28975e63 bge a4,s1,8000ba7c <_svfprintf_r+0x1d90> -8000b7e4: 80015737 lui a4,0x80015 -8000b7e8: c2070b13 addi s6,a4,-992 # 80014c20 <__BSS_END__+0xffffdff0> -8000b7ec: 00012823 sw zero,16(sp) -8000b7f0: 02012423 sw zero,40(sp) -8000b7f4: 02012223 sw zero,36(sp) -8000b7f8: 00012e23 sw zero,28(sp) -8000b7fc: f7fa7a13 andi s4,s4,-129 -8000b800: 00300a93 li s5,3 -8000b804: 00300c93 li s9,3 -8000b808: 00000d93 li s11,0 -8000b80c: 00078463 beqz a5,8000b814 <_svfprintf_r+0x1b28> -8000b810: e79fe06f j 8000a688 <_svfprintf_r+0x99c> -8000b814: ebcfe06f j 80009ed0 <_svfprintf_r+0x1e4> -8000b818: 00c12783 lw a5,12(sp) -8000b81c: 00040b13 mv s6,s0 -8000b820: 00f72023 sw a5,0(a4) -8000b824: fc0fe06f j 80009fe4 <_svfprintf_r+0x2f8> -8000b828: 000b0513 mv a0,s6 -8000b82c: 05912023 sw s9,64(sp) -8000b830: b88fe0ef jal ra,80009bb8 -8000b834: 0c714783 lbu a5,199(sp) -8000b838: fff54a93 not s5,a0 -8000b83c: 41fada93 srai s5,s5,0x1f -8000b840: 01212a23 sw s2,20(sp) -8000b844: 00012823 sw zero,16(sp) -8000b848: 02012423 sw zero,40(sp) -8000b84c: 02012223 sw zero,36(sp) -8000b850: 00012e23 sw zero,28(sp) -8000b854: 04012883 lw a7,64(sp) -8000b858: 00050c93 mv s9,a0 -8000b85c: 01557ab3 and s5,a0,s5 -8000b860: 00000d93 li s11,0 -8000b864: 00078463 beqz a5,8000b86c <_svfprintf_r+0x1b80> -8000b868: e21fe06f j 8000a688 <_svfprintf_r+0x99c> -8000b86c: e64fe06f j 80009ed0 <_svfprintf_r+0x1e4> -8000b870: 03012683 lw a3,48(sp) -8000b874: 02c12703 lw a4,44(sp) -8000b878: 00700613 li a2,7 -8000b87c: 00d8a023 sw a3,0(a7) -8000b880: 0e812683 lw a3,232(sp) -8000b884: 00e787b3 add a5,a5,a4 -8000b888: 00e8a223 sw a4,4(a7) -8000b88c: 00168693 addi a3,a3,1 -8000b890: 0ef12623 sw a5,236(sp) -8000b894: 0ed12423 sw a3,232(sp) -8000b898: 00888893 addi a7,a7,8 -8000b89c: 2cd64063 blt a2,a3,8000bb5c <_svfprintf_r+0x1e70> -8000b8a0: e005d4e3 bgez a1,8000b6a8 <_svfprintf_r+0x19bc> -8000b8a4: ff000613 li a2,-16 -8000b8a8: 40b004b3 neg s1,a1 -8000b8ac: 26c5d4e3 bge a1,a2,8000c314 <_svfprintf_r+0x2628> -8000b8b0: 01000913 li s2,16 -8000b8b4: 00700c93 li s9,7 -8000b8b8: 00c0006f j 8000b8c4 <_svfprintf_r+0x1bd8> -8000b8bc: ff048493 addi s1,s1,-16 -8000b8c0: 24995ae3 bge s2,s1,8000c314 <_svfprintf_r+0x2628> -8000b8c4: 00812703 lw a4,8(sp) -8000b8c8: 01078793 addi a5,a5,16 -8000b8cc: 00168693 addi a3,a3,1 -8000b8d0: 00e8a023 sw a4,0(a7) -8000b8d4: 0128a223 sw s2,4(a7) -8000b8d8: 0ef12623 sw a5,236(sp) -8000b8dc: 0ed12423 sw a3,232(sp) -8000b8e0: 00888893 addi a7,a7,8 -8000b8e4: fcdcdce3 bge s9,a3,8000b8bc <_svfprintf_r+0x1bd0> -8000b8e8: 0e410613 addi a2,sp,228 -8000b8ec: 000c0593 mv a1,s8 -8000b8f0: 000d0513 mv a0,s10 -8000b8f4: 5fc030ef jal ra,8000eef0 <__ssprint_r> -8000b8f8: c0051a63 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000b8fc: 0ec12783 lw a5,236(sp) -8000b900: 0e812683 lw a3,232(sp) -8000b904: 10c10893 addi a7,sp,268 -8000b908: fb5ff06f j 8000b8bc <_svfprintf_r+0x1bd0> -8000b90c: 00148693 addi a3,s1,1 -8000b910: 00890713 addi a4,s2,8 -8000b914: 00812783 lw a5,8(sp) -8000b918: 01bc8cb3 add s9,s9,s11 -8000b91c: 01b92223 sw s11,4(s2) -8000b920: 00f92023 sw a5,0(s2) -8000b924: 0f912623 sw s9,236(sp) -8000b928: 0ed12423 sw a3,232(sp) -8000b92c: 00700793 li a5,7 -8000b930: bed7c2e3 blt a5,a3,8000b514 <_svfprintf_r+0x1828> -8000b934: 00168693 addi a3,a3,1 -8000b938: 00870893 addi a7,a4,8 -8000b93c: 00070913 mv s2,a4 -8000b940: bd1fe06f j 8000a510 <_svfprintf_r+0x824> -8000b944: 200a7793 andi a5,s4,512 -8000b948: 1c078e63 beqz a5,8000bb24 <_svfprintf_r+0x1e38> -8000b94c: 01412783 lw a5,20(sp) -8000b950: 00000c93 li s9,0 -8000b954: 00e12a23 sw a4,20(sp) -8000b958: 0007c903 lbu s2,0(a5) -8000b95c: 8f9ff06f j 8000b254 <_svfprintf_r+0x1568> -8000b960: 200a7793 andi a5,s4,512 -8000b964: 1a078463 beqz a5,8000bb0c <_svfprintf_r+0x1e20> -8000b968: 01412783 lw a5,20(sp) -8000b96c: 00e12a23 sw a4,20(sp) -8000b970: 00078903 lb s2,0(a5) -8000b974: 41f95c93 srai s9,s2,0x1f -8000b978: 000c8793 mv a5,s9 -8000b97c: fa5fe06f j 8000a920 <_svfprintf_r+0xc34> -8000b980: 200bf793 andi a5,s7,512 -8000b984: 16078863 beqz a5,8000baf4 <_svfprintf_r+0x1e08> -8000b988: 01412783 lw a5,20(sp) -8000b98c: 00000c93 li s9,0 -8000b990: 00e12a23 sw a4,20(sp) -8000b994: 0007c903 lbu s2,0(a5) -8000b998: 00100793 li a5,1 -8000b99c: dcdfe06f j 8000a768 <_svfprintf_r+0xa7c> -8000b9a0: 200a7793 andi a5,s4,512 -8000b9a4: 12078e63 beqz a5,8000bae0 <_svfprintf_r+0x1df4> -8000b9a8: 01412783 lw a5,20(sp) -8000b9ac: 00000c93 li s9,0 -8000b9b0: 00e12a23 sw a4,20(sp) -8000b9b4: 0007c903 lbu s2,0(a5) -8000b9b8: e31fe06f j 8000a7e8 <_svfprintf_r+0xafc> -8000b9bc: 0fc12783 lw a5,252(sp) -8000b9c0: 1807c863 bltz a5,8000bb50 <_svfprintf_r+0x1e64> -8000b9c4: 0c714783 lbu a5,199(sp) -8000b9c8: 04700713 li a4,71 -8000b9cc: 46975c63 bge a4,s1,8000be44 <_svfprintf_r+0x2158> -8000b9d0: 80015737 lui a4,0x80015 -8000b9d4: c2870b13 addi s6,a4,-984 # 80014c28 <__BSS_END__+0xffffdff8> -8000b9d8: e15ff06f j 8000b7ec <_svfprintf_r+0x1b00> -8000b9dc: 00812703 lw a4,8(sp) -8000b9e0: 009787b3 add a5,a5,s1 -8000b9e4: 00168693 addi a3,a3,1 -8000b9e8: 00e8a023 sw a4,0(a7) -8000b9ec: 0098a223 sw s1,4(a7) -8000b9f0: 0ef12623 sw a5,236(sp) -8000b9f4: 0ed12423 sw a3,232(sp) -8000b9f8: 00700613 li a2,7 -8000b9fc: 00888893 addi a7,a7,8 -8000ba00: c8d65663 bge a2,a3,8000ae8c <_svfprintf_r+0x11a0> -8000ba04: 0e410613 addi a2,sp,228 -8000ba08: 000c0593 mv a1,s8 -8000ba0c: 000d0513 mv a0,s10 -8000ba10: 4e0030ef jal ra,8000eef0 <__ssprint_r> -8000ba14: ae051c63 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000ba18: 0ec12783 lw a5,236(sp) -8000ba1c: 10c10893 addi a7,sp,268 -8000ba20: c6cff06f j 8000ae8c <_svfprintf_r+0x11a0> -8000ba24: 04812783 lw a5,72(sp) -8000ba28: 04c12583 lw a1,76(sp) -8000ba2c: 00000913 li s2,0 -8000ba30: 40f40433 sub s0,s0,a5 -8000ba34: 00078613 mv a2,a5 -8000ba38: 00040513 mv a0,s0 -8000ba3c: a08fe0ef jal ra,80009c44 -8000ba40: 001cc583 lbu a1,1(s9) -8000ba44: 00a00613 li a2,10 -8000ba48: 00000693 li a3,0 -8000ba4c: 00b03833 snez a6,a1 -8000ba50: 00048513 mv a0,s1 -8000ba54: 00098593 mv a1,s3 -8000ba58: 010c8cb3 add s9,s9,a6 -8000ba5c: 1a5040ef jal ra,80010400 <__udivdi3> -8000ba60: b55ff06f j 8000b5b4 <_svfprintf_r+0x18c8> -8000ba64: 01012b83 lw s7,16(sp) -8000ba68: 000b0c13 mv s8,s6 -8000ba6c: aa4ff06f j 8000ad10 <_svfprintf_r+0x1024> -8000ba70: 00900793 li a5,9 -8000ba74: b497e0e3 bltu a5,s1,8000b5b4 <_svfprintf_r+0x18c8> -8000ba78: b85ff06f j 8000b5fc <_svfprintf_r+0x1910> -8000ba7c: 80015737 lui a4,0x80015 -8000ba80: c1c70b13 addi s6,a4,-996 # 80014c1c <__BSS_END__+0xffffdfec> -8000ba84: d69ff06f j 8000b7ec <_svfprintf_r+0x1b00> -8000ba88: 0e410613 addi a2,sp,228 -8000ba8c: 000c0593 mv a1,s8 -8000ba90: 000d0513 mv a0,s10 -8000ba94: 45c030ef jal ra,8000eef0 <__ssprint_r> -8000ba98: a6051a63 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000ba9c: 0ec12783 lw a5,236(sp) -8000baa0: 10c10893 addi a7,sp,268 -8000baa4: bd0ff06f j 8000ae74 <_svfprintf_r+0x1188> -8000baa8: 00600c93 li s9,6 -8000baac: 865ff06f j 8000b310 <_svfprintf_r+0x1624> -8000bab0: 02012683 lw a3,32(sp) -8000bab4: 00db0733 add a4,s6,a3 -8000bab8: 409684b3 sub s1,a3,s1 -8000babc: 41b70833 sub a6,a4,s11 -8000bac0: 00048913 mv s2,s1 -8000bac4: c6985263 bge a6,s1,8000af28 <_svfprintf_r+0x123c> -8000bac8: 00080913 mv s2,a6 -8000bacc: c5cff06f j 8000af28 <_svfprintf_r+0x123c> -8000bad0: 00c12783 lw a5,12(sp) -8000bad4: 00040b13 mv s6,s0 -8000bad8: 00f71023 sh a5,0(a4) -8000badc: d08fe06f j 80009fe4 <_svfprintf_r+0x2f8> -8000bae0: 01412783 lw a5,20(sp) -8000bae4: 00000c93 li s9,0 -8000bae8: 00e12a23 sw a4,20(sp) -8000baec: 0007a903 lw s2,0(a5) -8000baf0: cf9fe06f j 8000a7e8 <_svfprintf_r+0xafc> -8000baf4: 01412783 lw a5,20(sp) -8000baf8: 00000c93 li s9,0 -8000bafc: 00e12a23 sw a4,20(sp) -8000bb00: 0007a903 lw s2,0(a5) -8000bb04: 00100793 li a5,1 -8000bb08: c61fe06f j 8000a768 <_svfprintf_r+0xa7c> -8000bb0c: 01412783 lw a5,20(sp) -8000bb10: 00e12a23 sw a4,20(sp) -8000bb14: 0007a903 lw s2,0(a5) -8000bb18: 41f95c93 srai s9,s2,0x1f -8000bb1c: 000c8793 mv a5,s9 -8000bb20: e01fe06f j 8000a920 <_svfprintf_r+0xc34> -8000bb24: 01412783 lw a5,20(sp) -8000bb28: 00000c93 li s9,0 -8000bb2c: 00e12a23 sw a4,20(sp) -8000bb30: 0007a903 lw s2,0(a5) -8000bb34: f20ff06f j 8000b254 <_svfprintf_r+0x1568> -8000bb38: 0e410613 addi a2,sp,228 -8000bb3c: 000c0593 mv a1,s8 -8000bb40: 000d0513 mv a0,s10 -8000bb44: 3ac030ef jal ra,8000eef0 <__ssprint_r> -8000bb48: 00cc5703 lhu a4,12(s8) -8000bb4c: cb0fe06f j 80009ffc <_svfprintf_r+0x310> -8000bb50: 02d00793 li a5,45 -8000bb54: 0cf103a3 sb a5,199(sp) -8000bb58: e71ff06f j 8000b9c8 <_svfprintf_r+0x1cdc> -8000bb5c: 0e410613 addi a2,sp,228 -8000bb60: 000c0593 mv a1,s8 -8000bb64: 000d0513 mv a0,s10 -8000bb68: 388030ef jal ra,8000eef0 <__ssprint_r> -8000bb6c: 9a051063 bnez a0,8000ad0c <_svfprintf_r+0x1020> -8000bb70: 0cc12583 lw a1,204(sp) -8000bb74: 0ec12783 lw a5,236(sp) -8000bb78: 0e812683 lw a3,232(sp) -8000bb7c: 10c10893 addi a7,sp,268 -8000bb80: b205d4e3 bgez a1,8000b6a8 <_svfprintf_r+0x19bc> -8000bb84: d21ff06f j 8000b8a4 <_svfprintf_r+0x1bb8> -8000bb88: 00600d93 li s11,6 -8000bb8c: df8fe06f j 8000a184 <_svfprintf_r+0x498> -8000bb90: 02012703 lw a4,32(sp) -8000bb94: 000b0c13 mv s8,s6 -8000bb98: 02812b03 lw s6,40(sp) -8000bb9c: 02812e23 sw s0,60(sp) -8000bba0: 01c12a03 lw s4,28(sp) -8000bba4: 00eb06b3 add a3,s6,a4 -8000bba8: 04012403 lw s0,64(sp) -8000bbac: 04412983 lw s3,68(sp) -8000bbb0: 02412a83 lw s5,36(sp) -8000bbb4: afb6f463 bgeu a3,s11,8000ae9c <_svfprintf_r+0x11b0> -8000bbb8: 00068d93 mv s11,a3 -8000bbbc: ae0ff06f j 8000ae9c <_svfprintf_r+0x11b0> -8000bbc0: 01c12703 lw a4,28(sp) -8000bbc4: ffd00793 li a5,-3 -8000bbc8: 00f74463 blt a4,a5,8000bbd0 <_svfprintf_r+0x1ee4> -8000bbcc: 00edda63 bge s11,a4,8000bbe0 <_svfprintf_r+0x1ef4> -8000bbd0: ffe48493 addi s1,s1,-2 -8000bbd4: fdf4f793 andi a5,s1,-33 -8000bbd8: 04f12a23 sw a5,84(sp) -8000bbdc: ee4fe06f j 8000a2c0 <_svfprintf_r+0x5d4> -8000bbe0: 02012783 lw a5,32(sp) -8000bbe4: 01c12703 lw a4,28(sp) -8000bbe8: 26f74463 blt a4,a5,8000be50 <_svfprintf_r+0x2164> -8000bbec: 02812783 lw a5,40(sp) -8000bbf0: 00070c93 mv s9,a4 -8000bbf4: 0017f793 andi a5,a5,1 -8000bbf8: 00078663 beqz a5,8000bc04 <_svfprintf_r+0x1f18> -8000bbfc: 02c12783 lw a5,44(sp) -8000bc00: 00f70cb3 add s9,a4,a5 -8000bc04: 02812783 lw a5,40(sp) -8000bc08: 4007f793 andi a5,a5,1024 -8000bc0c: 00078663 beqz a5,8000bc18 <_svfprintf_r+0x1f2c> -8000bc10: 01c12783 lw a5,28(sp) -8000bc14: 12f04ae3 bgtz a5,8000c548 <_svfprintf_r+0x285c> +8000b714: 00e12a23 sw a4,20(sp) +8000b718: 00078903 lb s2,0(a5) +8000b71c: 41f95c93 srai s9,s2,0x1f +8000b720: 000c8793 mv a5,s9 +8000b724: fa5fe06f j 8000a6c8 <_svfprintf_r+0xc34> +8000b728: 200bf793 andi a5,s7,512 +8000b72c: 16078863 beqz a5,8000b89c <_svfprintf_r+0x1e08> +8000b730: 01412783 lw a5,20(sp) +8000b734: 00000c93 li s9,0 +8000b738: 00e12a23 sw a4,20(sp) +8000b73c: 0007c903 lbu s2,0(a5) +8000b740: 00100793 li a5,1 +8000b744: dcdfe06f j 8000a510 <_svfprintf_r+0xa7c> +8000b748: 200a7793 andi a5,s4,512 +8000b74c: 12078e63 beqz a5,8000b888 <_svfprintf_r+0x1df4> +8000b750: 01412783 lw a5,20(sp) +8000b754: 00000c93 li s9,0 +8000b758: 00e12a23 sw a4,20(sp) +8000b75c: 0007c903 lbu s2,0(a5) +8000b760: e31fe06f j 8000a590 <_svfprintf_r+0xafc> +8000b764: 0fc12783 lw a5,252(sp) +8000b768: 1807c863 bltz a5,8000b8f8 <_svfprintf_r+0x1e64> +8000b76c: 0c714783 lbu a5,199(sp) +8000b770: 04700713 li a4,71 +8000b774: 46975c63 bge a4,s1,8000bbec <_svfprintf_r+0x2158> +8000b778: 80015737 lui a4,0x80015 +8000b77c: c7470b13 addi s6,a4,-908 # 80014c74 <__BSS_END__+0xffffe038> +8000b780: e15ff06f j 8000b594 <_svfprintf_r+0x1b00> +8000b784: 00812703 lw a4,8(sp) +8000b788: 009787b3 add a5,a5,s1 +8000b78c: 00168693 addi a3,a3,1 +8000b790: 00e8a023 sw a4,0(a7) +8000b794: 0098a223 sw s1,4(a7) +8000b798: 0ef12623 sw a5,236(sp) +8000b79c: 0ed12423 sw a3,232(sp) +8000b7a0: 00700613 li a2,7 +8000b7a4: 00888893 addi a7,a7,8 +8000b7a8: c8d65663 bge a2,a3,8000ac34 <_svfprintf_r+0x11a0> +8000b7ac: 0e410613 addi a2,sp,228 +8000b7b0: 000c0593 mv a1,s8 +8000b7b4: 000d0513 mv a0,s10 +8000b7b8: 7c4030ef jal ra,8000ef7c <__ssprint_r> +8000b7bc: ae051c63 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b7c0: 0ec12783 lw a5,236(sp) +8000b7c4: 10c10893 addi a7,sp,268 +8000b7c8: c6cff06f j 8000ac34 <_svfprintf_r+0x11a0> +8000b7cc: 04812783 lw a5,72(sp) +8000b7d0: 04c12583 lw a1,76(sp) +8000b7d4: 00000913 li s2,0 +8000b7d8: 40f40433 sub s0,s0,a5 +8000b7dc: 00078613 mv a2,a5 +8000b7e0: 00040513 mv a0,s0 +8000b7e4: a08fe0ef jal ra,800099ec +8000b7e8: 001cc583 lbu a1,1(s9) +8000b7ec: 00a00613 li a2,10 +8000b7f0: 00000693 li a3,0 +8000b7f4: 00b03833 snez a6,a1 +8000b7f8: 00048513 mv a0,s1 +8000b7fc: 00098593 mv a1,s3 +8000b800: 010c8cb3 add s9,s9,a6 +8000b804: 4c1040ef jal ra,800104c4 <__udivdi3> +8000b808: b55ff06f j 8000b35c <_svfprintf_r+0x18c8> +8000b80c: 01012b83 lw s7,16(sp) +8000b810: 000b0c13 mv s8,s6 +8000b814: aa4ff06f j 8000aab8 <_svfprintf_r+0x1024> +8000b818: 00900793 li a5,9 +8000b81c: b497e0e3 bltu a5,s1,8000b35c <_svfprintf_r+0x18c8> +8000b820: b85ff06f j 8000b3a4 <_svfprintf_r+0x1910> +8000b824: 80015737 lui a4,0x80015 +8000b828: c6870b13 addi s6,a4,-920 # 80014c68 <__BSS_END__+0xffffe02c> +8000b82c: d69ff06f j 8000b594 <_svfprintf_r+0x1b00> +8000b830: 0e410613 addi a2,sp,228 +8000b834: 000c0593 mv a1,s8 +8000b838: 000d0513 mv a0,s10 +8000b83c: 740030ef jal ra,8000ef7c <__ssprint_r> +8000b840: a6051a63 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b844: 0ec12783 lw a5,236(sp) +8000b848: 10c10893 addi a7,sp,268 +8000b84c: bd0ff06f j 8000ac1c <_svfprintf_r+0x1188> +8000b850: 00600c93 li s9,6 +8000b854: 865ff06f j 8000b0b8 <_svfprintf_r+0x1624> +8000b858: 02012683 lw a3,32(sp) +8000b85c: 00db0733 add a4,s6,a3 +8000b860: 409684b3 sub s1,a3,s1 +8000b864: 41b70833 sub a6,a4,s11 +8000b868: 00048913 mv s2,s1 +8000b86c: c6985263 bge a6,s1,8000acd0 <_svfprintf_r+0x123c> +8000b870: 00080913 mv s2,a6 +8000b874: c5cff06f j 8000acd0 <_svfprintf_r+0x123c> +8000b878: 00c12783 lw a5,12(sp) +8000b87c: 00040b13 mv s6,s0 +8000b880: 00f71023 sh a5,0(a4) +8000b884: d08fe06f j 80009d8c <_svfprintf_r+0x2f8> +8000b888: 01412783 lw a5,20(sp) +8000b88c: 00000c93 li s9,0 +8000b890: 00e12a23 sw a4,20(sp) +8000b894: 0007a903 lw s2,0(a5) +8000b898: cf9fe06f j 8000a590 <_svfprintf_r+0xafc> +8000b89c: 01412783 lw a5,20(sp) +8000b8a0: 00000c93 li s9,0 +8000b8a4: 00e12a23 sw a4,20(sp) +8000b8a8: 0007a903 lw s2,0(a5) +8000b8ac: 00100793 li a5,1 +8000b8b0: c61fe06f j 8000a510 <_svfprintf_r+0xa7c> +8000b8b4: 01412783 lw a5,20(sp) +8000b8b8: 00e12a23 sw a4,20(sp) +8000b8bc: 0007a903 lw s2,0(a5) +8000b8c0: 41f95c93 srai s9,s2,0x1f +8000b8c4: 000c8793 mv a5,s9 +8000b8c8: e01fe06f j 8000a6c8 <_svfprintf_r+0xc34> +8000b8cc: 01412783 lw a5,20(sp) +8000b8d0: 00000c93 li s9,0 +8000b8d4: 00e12a23 sw a4,20(sp) +8000b8d8: 0007a903 lw s2,0(a5) +8000b8dc: f20ff06f j 8000affc <_svfprintf_r+0x1568> +8000b8e0: 0e410613 addi a2,sp,228 +8000b8e4: 000c0593 mv a1,s8 +8000b8e8: 000d0513 mv a0,s10 +8000b8ec: 690030ef jal ra,8000ef7c <__ssprint_r> +8000b8f0: 00cc5703 lhu a4,12(s8) +8000b8f4: cb0fe06f j 80009da4 <_svfprintf_r+0x310> +8000b8f8: 02d00793 li a5,45 +8000b8fc: 0cf103a3 sb a5,199(sp) +8000b900: e71ff06f j 8000b770 <_svfprintf_r+0x1cdc> +8000b904: 0e410613 addi a2,sp,228 +8000b908: 000c0593 mv a1,s8 +8000b90c: 000d0513 mv a0,s10 +8000b910: 66c030ef jal ra,8000ef7c <__ssprint_r> +8000b914: 9a051063 bnez a0,8000aab4 <_svfprintf_r+0x1020> +8000b918: 0cc12583 lw a1,204(sp) +8000b91c: 0ec12783 lw a5,236(sp) +8000b920: 0e812683 lw a3,232(sp) +8000b924: 10c10893 addi a7,sp,268 +8000b928: b205d4e3 bgez a1,8000b450 <_svfprintf_r+0x19bc> +8000b92c: d21ff06f j 8000b64c <_svfprintf_r+0x1bb8> +8000b930: 00600d93 li s11,6 +8000b934: df8fe06f j 80009f2c <_svfprintf_r+0x498> +8000b938: 02012703 lw a4,32(sp) +8000b93c: 000b0c13 mv s8,s6 +8000b940: 02812b03 lw s6,40(sp) +8000b944: 02812e23 sw s0,60(sp) +8000b948: 01c12a03 lw s4,28(sp) +8000b94c: 00eb06b3 add a3,s6,a4 +8000b950: 04012403 lw s0,64(sp) +8000b954: 04412983 lw s3,68(sp) +8000b958: 02412a83 lw s5,36(sp) +8000b95c: afb6f463 bgeu a3,s11,8000ac44 <_svfprintf_r+0x11b0> +8000b960: 00068d93 mv s11,a3 +8000b964: ae0ff06f j 8000ac44 <_svfprintf_r+0x11b0> +8000b968: 01c12703 lw a4,28(sp) +8000b96c: ffd00793 li a5,-3 +8000b970: 00f74463 blt a4,a5,8000b978 <_svfprintf_r+0x1ee4> +8000b974: 00edda63 bge s11,a4,8000b988 <_svfprintf_r+0x1ef4> +8000b978: ffe48493 addi s1,s1,-2 +8000b97c: fdf4f793 andi a5,s1,-33 +8000b980: 04f12a23 sw a5,84(sp) +8000b984: ee4fe06f j 8000a068 <_svfprintf_r+0x5d4> +8000b988: 02012783 lw a5,32(sp) +8000b98c: 01c12703 lw a4,28(sp) +8000b990: 26f74463 blt a4,a5,8000bbf8 <_svfprintf_r+0x2164> +8000b994: 02812783 lw a5,40(sp) +8000b998: 00070c93 mv s9,a4 +8000b99c: 0017f793 andi a5,a5,1 +8000b9a0: 00078663 beqz a5,8000b9ac <_svfprintf_r+0x1f18> +8000b9a4: 02c12783 lw a5,44(sp) +8000b9a8: 00f70cb3 add s9,a4,a5 +8000b9ac: 02812783 lw a5,40(sp) +8000b9b0: 4007f793 andi a5,a5,1024 +8000b9b4: 00078663 beqz a5,8000b9c0 <_svfprintf_r+0x1f2c> +8000b9b8: 01c12783 lw a5,28(sp) +8000b9bc: 12f04ae3 bgtz a5,8000c2f0 <_svfprintf_r+0x285c> +8000b9c0: fffcca93 not s5,s9 +8000b9c4: 41fada93 srai s5,s5,0x1f +8000b9c8: 015cfab3 and s5,s9,s5 +8000b9cc: 06700493 li s1,103 +8000b9d0: 02012423 sw zero,40(sp) +8000b9d4: 02012223 sw zero,36(sp) +8000b9d8: facfe06f j 8000a184 <_svfprintf_r+0x6f0> +8000b9dc: 0c714783 lbu a5,199(sp) +8000b9e0: 00000d93 li s11,0 +8000b9e4: 00078463 beqz a5,8000b9ec <_svfprintf_r+0x1f58> +8000b9e8: a49fe06f j 8000a430 <_svfprintf_r+0x99c> +8000b9ec: a8cfe06f j 80009c78 <_svfprintf_r+0x1e4> +8000b9f0: 0e410613 addi a2,sp,228 +8000b9f4: 000b0593 mv a1,s6 +8000b9f8: 000d0513 mv a0,s10 +8000b9fc: 580030ef jal ra,8000ef7c <__ssprint_r> +8000ba00: e00516e3 bnez a0,8000b80c <_svfprintf_r+0x1d78> +8000ba04: 00044683 lbu a3,0(s0) +8000ba08: 0ec12783 lw a5,236(sp) +8000ba0c: 10c10893 addi a7,sp,268 +8000ba10: 00dd8db3 add s11,s11,a3 +8000ba14: fe8ff06f j 8000b1fc <_svfprintf_r+0x1768> +8000ba18: 0b010a93 addi s5,sp,176 +8000ba1c: 0dc10813 addi a6,sp,220 +8000ba20: 0d010793 addi a5,sp,208 +8000ba24: 0cc10713 addi a4,sp,204 +8000ba28: 000d8693 mv a3,s11 +8000ba2c: 00300613 li a2,3 +8000ba30: 000a8593 mv a1,s5 +8000ba34: 000d0513 mv a0,s10 +8000ba38: 05112223 sw a7,68(sp) +8000ba3c: 0bc12823 sw t3,176(sp) +8000ba40: 05c12023 sw t3,64(sp) +8000ba44: 0bd12a23 sw t4,180(sp) +8000ba48: 03d12223 sw t4,36(sp) +8000ba4c: 0be12c23 sw t5,184(sp) +8000ba50: 03e12023 sw t5,32(sp) +8000ba54: 0a612e23 sw t1,188(sp) +8000ba58: 00612e23 sw t1,28(sp) +8000ba5c: c49fa0ef jal ra,800066a4 <_ldtoa_r> +8000ba60: 01c12303 lw t1,28(sp) +8000ba64: 02012f03 lw t5,32(sp) +8000ba68: 02412e83 lw t4,36(sp) +8000ba6c: 04012e03 lw t3,64(sp) +8000ba70: 04412883 lw a7,68(sp) +8000ba74: 00050b13 mv s6,a0 +8000ba78: 04600793 li a5,70 +8000ba7c: 01bb0933 add s2,s6,s11 +8000ba80: 62fb9a63 bne s7,a5,8000c0b4 <_svfprintf_r+0x2620> +8000ba84: 000b4683 lbu a3,0(s6) +8000ba88: 03000793 li a5,48 +8000ba8c: 10f686e3 beq a3,a5,8000c398 <_svfprintf_r+0x2904> +8000ba90: 0a010c93 addi s9,sp,160 +8000ba94: 0cc12783 lw a5,204(sp) +8000ba98: 00f90933 add s2,s2,a5 +8000ba9c: d40fe06f j 80009fdc <_svfprintf_r+0x548> +8000baa0: 02d00793 li a5,45 +8000baa4: 0cf103a3 sb a5,199(sp) +8000baa8: addff06f j 8000b584 <_svfprintf_r+0x1af0> +8000baac: 0b010a93 addi s5,sp,176 +8000bab0: 0d010793 addi a5,sp,208 +8000bab4: 0dc10813 addi a6,sp,220 +8000bab8: 0cc10713 addi a4,sp,204 +8000babc: 000d8693 mv a3,s11 +8000bac0: 00200613 li a2,2 +8000bac4: 000a8593 mv a1,s5 +8000bac8: 000d0513 mv a0,s10 +8000bacc: 0bc12823 sw t3,176(sp) +8000bad0: 05c12023 sw t3,64(sp) +8000bad4: 0bd12a23 sw t4,180(sp) +8000bad8: 03d12223 sw t4,36(sp) +8000badc: 0be12c23 sw t5,184(sp) +8000bae0: 03e12023 sw t5,32(sp) +8000bae4: 0a612e23 sw t1,188(sp) +8000bae8: 00612e23 sw t1,28(sp) +8000baec: bb9fa0ef jal ra,800066a4 <_ldtoa_r> +8000baf0: 04700793 li a5,71 +8000baf4: 01c12303 lw t1,28(sp) +8000baf8: 02012f03 lw t5,32(sp) +8000bafc: 02412e83 lw t4,36(sp) +8000bb00: 04012e03 lw t3,64(sp) +8000bb04: 04412883 lw a7,68(sp) +8000bb08: 00050b13 mv s6,a0 +8000bb0c: f6fb96e3 bne s7,a5,8000ba78 <_svfprintf_r+0x1fe4> +8000bb10: 02812783 lw a5,40(sp) +8000bb14: 0017f793 andi a5,a5,1 +8000bb18: 58079863 bnez a5,8000c0a8 <_svfprintf_r+0x2614> +8000bb1c: 04700793 li a5,71 +8000bb20: 0dc12703 lw a4,220(sp) +8000bb24: 04f12a23 sw a5,84(sp) +8000bb28: d10fe06f j 8000a038 <_svfprintf_r+0x5a4> +8000bb2c: 0e410613 addi a2,sp,228 +8000bb30: 000c0593 mv a1,s8 +8000bb34: 000d0513 mv a0,s10 +8000bb38: 444030ef jal ra,8000ef7c <__ssprint_r> +8000bb3c: 00050463 beqz a0,8000bb44 <_svfprintf_r+0x20b0> +8000bb40: f75fe06f j 8000aab4 <_svfprintf_r+0x1020> +8000bb44: 0cc12483 lw s1,204(sp) +8000bb48: 0ec12783 lw a5,236(sp) +8000bb4c: 10c10893 addi a7,sp,268 +8000bb50: 938ff06f j 8000ac88 <_svfprintf_r+0x11f4> +8000bb54: 0c714783 lbu a5,199(sp) +8000bb58: 01212a23 sw s2,20(sp) +8000bb5c: 02012423 sw zero,40(sp) +8000bb60: 02012223 sw zero,36(sp) +8000bb64: 00012e23 sw zero,28(sp) +8000bb68: 000d8a93 mv s5,s11 +8000bb6c: 000d8c93 mv s9,s11 +8000bb70: 00000d93 li s11,0 +8000bb74: 00078463 beqz a5,8000bb7c <_svfprintf_r+0x20e8> +8000bb78: 8b9fe06f j 8000a430 <_svfprintf_r+0x99c> +8000bb7c: 8fcfe06f j 80009c78 <_svfprintf_r+0x1e4> +8000bb80: 0e410613 addi a2,sp,228 +8000bb84: 000c0593 mv a1,s8 +8000bb88: 000d0513 mv a0,s10 +8000bb8c: 3f0030ef jal ra,8000ef7c <__ssprint_r> +8000bb90: 00050463 beqz a0,8000bb98 <_svfprintf_r+0x2104> +8000bb94: f21fe06f j 8000aab4 <_svfprintf_r+0x1020> +8000bb98: 0cc12483 lw s1,204(sp) +8000bb9c: 02012703 lw a4,32(sp) +8000bba0: 0ec12783 lw a5,236(sp) +8000bba4: 10c10893 addi a7,sp,268 +8000bba8: 409704b3 sub s1,a4,s1 +8000bbac: 924ff06f j 8000acd0 <_svfprintf_r+0x123c> +8000bbb0: 02812783 lw a5,40(sp) +8000bbb4: 01c12703 lw a4,28(sp) +8000bbb8: 0017f793 andi a5,a5,1 +8000bbbc: 01b7e7b3 or a5,a5,s11 +8000bbc0: 04e054e3 blez a4,8000c408 <_svfprintf_r+0x2974> +8000bbc4: 7a079663 bnez a5,8000c370 <_svfprintf_r+0x28dc> +8000bbc8: 01c12c83 lw s9,28(sp) +8000bbcc: 06600493 li s1,102 +8000bbd0: 02812783 lw a5,40(sp) +8000bbd4: 4007f793 andi a5,a5,1024 +8000bbd8: 70079e63 bnez a5,8000c2f4 <_svfprintf_r+0x2860> +8000bbdc: fffcca93 not s5,s9 +8000bbe0: 41fada93 srai s5,s5,0x1f +8000bbe4: 015cfab3 and s5,s9,s5 +8000bbe8: de9ff06f j 8000b9d0 <_svfprintf_r+0x1f3c> +8000bbec: 80015737 lui a4,0x80015 +8000bbf0: c7070b13 addi s6,a4,-912 # 80014c70 <__BSS_END__+0xffffe034> +8000bbf4: 9a1ff06f j 8000b594 <_svfprintf_r+0x1b00> +8000bbf8: 02012783 lw a5,32(sp) +8000bbfc: 02c12703 lw a4,44(sp) +8000bc00: 06700493 li s1,103 +8000bc04: 00e78cb3 add s9,a5,a4 +8000bc08: 01c12783 lw a5,28(sp) +8000bc0c: fcf042e3 bgtz a5,8000bbd0 <_svfprintf_r+0x213c> +8000bc10: 40fc8cb3 sub s9,s9,a5 +8000bc14: 001c8c93 addi s9,s9,1 8000bc18: fffcca93 not s5,s9 8000bc1c: 41fada93 srai s5,s5,0x1f 8000bc20: 015cfab3 and s5,s9,s5 -8000bc24: 06700493 li s1,103 -8000bc28: 02012423 sw zero,40(sp) -8000bc2c: 02012223 sw zero,36(sp) -8000bc30: facfe06f j 8000a3dc <_svfprintf_r+0x6f0> -8000bc34: 0c714783 lbu a5,199(sp) -8000bc38: 00000d93 li s11,0 -8000bc3c: 00078463 beqz a5,8000bc44 <_svfprintf_r+0x1f58> -8000bc40: a49fe06f j 8000a688 <_svfprintf_r+0x99c> -8000bc44: a8cfe06f j 80009ed0 <_svfprintf_r+0x1e4> -8000bc48: 0e410613 addi a2,sp,228 -8000bc4c: 000b0593 mv a1,s6 -8000bc50: 000d0513 mv a0,s10 -8000bc54: 29c030ef jal ra,8000eef0 <__ssprint_r> -8000bc58: e00516e3 bnez a0,8000ba64 <_svfprintf_r+0x1d78> -8000bc5c: 00044683 lbu a3,0(s0) -8000bc60: 0ec12783 lw a5,236(sp) -8000bc64: 10c10893 addi a7,sp,268 -8000bc68: 00dd8db3 add s11,s11,a3 -8000bc6c: fe8ff06f j 8000b454 <_svfprintf_r+0x1768> -8000bc70: 0b010a93 addi s5,sp,176 -8000bc74: 0dc10813 addi a6,sp,220 -8000bc78: 0d010793 addi a5,sp,208 -8000bc7c: 0cc10713 addi a4,sp,204 -8000bc80: 000d8693 mv a3,s11 -8000bc84: 00300613 li a2,3 -8000bc88: 000a8593 mv a1,s5 -8000bc8c: 000d0513 mv a0,s10 -8000bc90: 05112223 sw a7,68(sp) -8000bc94: 0bc12823 sw t3,176(sp) -8000bc98: 05c12023 sw t3,64(sp) -8000bc9c: 0bd12a23 sw t4,180(sp) -8000bca0: 03d12223 sw t4,36(sp) -8000bca4: 0be12c23 sw t5,184(sp) -8000bca8: 03e12023 sw t5,32(sp) +8000bc24: dadff06f j 8000b9d0 <_svfprintf_r+0x1f3c> +8000bc28: 800156b7 lui a3,0x80015 +8000bc2c: 34c68e93 addi t4,a3,844 # 8001534c <__BSS_END__+0xffffe710> +8000bc30: f48fe06f j 8000a378 <_svfprintf_r+0x8e4> +8000bc34: 03000793 li a5,48 +8000bc38: 0cf10423 sb a5,200(sp) +8000bc3c: 05800793 li a5,88 +8000bc40: 002a6713 ori a4,s4,2 +8000bc44: 0cf104a3 sb a5,201(sp) +8000bc48: 02e12423 sw a4,40(sp) +8000bc4c: 06300793 li a5,99 +8000bc50: 00012823 sw zero,16(sp) +8000bc54: 14c10b13 addi s6,sp,332 +8000bc58: 41b7ce63 blt a5,s11,8000c074 <_svfprintf_r+0x25e0> +8000bc5c: 0fc12303 lw t1,252(sp) +8000bc60: fdf4fb93 andi s7,s1,-33 +8000bc64: 05712a23 sw s7,84(sp) +8000bc68: 04012c23 sw zero,88(sp) +8000bc6c: 0f012e03 lw t3,240(sp) +8000bc70: 0f412e83 lw t4,244(sp) +8000bc74: 0f812f03 lw t5,248(sp) +8000bc78: 102a6a13 ori s4,s4,258 +8000bc7c: 38034263 bltz t1,8000c000 <_svfprintf_r+0x256c> +8000bc80: 06100793 li a5,97 +8000bc84: 54f48e63 beq s1,a5,8000c1e0 <_svfprintf_r+0x274c> +8000bc88: 04100793 li a5,65 +8000bc8c: 00f48463 beq s1,a5,8000bc94 <_svfprintf_r+0x2200> +8000bc90: ac8fe06f j 80009f58 <_svfprintf_r+0x4c4> +8000bc94: 0b010a93 addi s5,sp,176 +8000bc98: 000a8513 mv a0,s5 +8000bc9c: 05112823 sw a7,80(sp) +8000bca0: 0bc12823 sw t3,176(sp) +8000bca4: 0bd12a23 sw t4,180(sp) +8000bca8: 0be12c23 sw t5,184(sp) 8000bcac: 0a612e23 sw t1,188(sp) -8000bcb0: 00612e23 sw t1,28(sp) -8000bcb4: aa1fa0ef jal ra,80006754 <_ldtoa_r> -8000bcb8: 01c12303 lw t1,28(sp) -8000bcbc: 02012f03 lw t5,32(sp) -8000bcc0: 02412e83 lw t4,36(sp) -8000bcc4: 04012e03 lw t3,64(sp) -8000bcc8: 04412883 lw a7,68(sp) -8000bccc: 00050b13 mv s6,a0 -8000bcd0: 04600793 li a5,70 -8000bcd4: 01bb0933 add s2,s6,s11 -8000bcd8: 62fb9a63 bne s7,a5,8000c30c <_svfprintf_r+0x2620> -8000bcdc: 000b4683 lbu a3,0(s6) -8000bce0: 03000793 li a5,48 -8000bce4: 10f686e3 beq a3,a5,8000c5f0 <_svfprintf_r+0x2904> -8000bce8: 0a010c93 addi s9,sp,160 -8000bcec: 0cc12783 lw a5,204(sp) -8000bcf0: 00f90933 add s2,s2,a5 -8000bcf4: d40fe06f j 8000a234 <_svfprintf_r+0x548> -8000bcf8: 02d00793 li a5,45 -8000bcfc: 0cf103a3 sb a5,199(sp) -8000bd00: addff06f j 8000b7dc <_svfprintf_r+0x1af0> -8000bd04: 0b010a93 addi s5,sp,176 -8000bd08: 0d010793 addi a5,sp,208 -8000bd0c: 0dc10813 addi a6,sp,220 -8000bd10: 0cc10713 addi a4,sp,204 -8000bd14: 000d8693 mv a3,s11 -8000bd18: 00200613 li a2,2 -8000bd1c: 000a8593 mv a1,s5 -8000bd20: 000d0513 mv a0,s10 -8000bd24: 0bc12823 sw t3,176(sp) -8000bd28: 05c12023 sw t3,64(sp) -8000bd2c: 0bd12a23 sw t4,180(sp) -8000bd30: 03d12223 sw t4,36(sp) -8000bd34: 0be12c23 sw t5,184(sp) -8000bd38: 03e12023 sw t5,32(sp) -8000bd3c: 0a612e23 sw t1,188(sp) -8000bd40: 00612e23 sw t1,28(sp) -8000bd44: a11fa0ef jal ra,80006754 <_ldtoa_r> -8000bd48: 04700793 li a5,71 -8000bd4c: 01c12303 lw t1,28(sp) -8000bd50: 02012f03 lw t5,32(sp) -8000bd54: 02412e83 lw t4,36(sp) -8000bd58: 04012e03 lw t3,64(sp) -8000bd5c: 04412883 lw a7,68(sp) -8000bd60: 00050b13 mv s6,a0 -8000bd64: f6fb96e3 bne s7,a5,8000bcd0 <_svfprintf_r+0x1fe4> -8000bd68: 02812783 lw a5,40(sp) -8000bd6c: 0017f793 andi a5,a5,1 -8000bd70: 58079863 bnez a5,8000c300 <_svfprintf_r+0x2614> -8000bd74: 04700793 li a5,71 -8000bd78: 0dc12703 lw a4,220(sp) -8000bd7c: 04f12a23 sw a5,84(sp) -8000bd80: d10fe06f j 8000a290 <_svfprintf_r+0x5a4> -8000bd84: 0e410613 addi a2,sp,228 -8000bd88: 000c0593 mv a1,s8 -8000bd8c: 000d0513 mv a0,s10 -8000bd90: 160030ef jal ra,8000eef0 <__ssprint_r> -8000bd94: 00050463 beqz a0,8000bd9c <_svfprintf_r+0x20b0> -8000bd98: f75fe06f j 8000ad0c <_svfprintf_r+0x1020> -8000bd9c: 0cc12483 lw s1,204(sp) -8000bda0: 0ec12783 lw a5,236(sp) -8000bda4: 10c10893 addi a7,sp,268 -8000bda8: 938ff06f j 8000aee0 <_svfprintf_r+0x11f4> -8000bdac: 0c714783 lbu a5,199(sp) -8000bdb0: 01212a23 sw s2,20(sp) -8000bdb4: 02012423 sw zero,40(sp) -8000bdb8: 02012223 sw zero,36(sp) -8000bdbc: 00012e23 sw zero,28(sp) -8000bdc0: 000d8a93 mv s5,s11 -8000bdc4: 000d8c93 mv s9,s11 -8000bdc8: 00000d93 li s11,0 -8000bdcc: 00078463 beqz a5,8000bdd4 <_svfprintf_r+0x20e8> -8000bdd0: 8b9fe06f j 8000a688 <_svfprintf_r+0x99c> -8000bdd4: 8fcfe06f j 80009ed0 <_svfprintf_r+0x1e4> -8000bdd8: 0e410613 addi a2,sp,228 -8000bddc: 000c0593 mv a1,s8 -8000bde0: 000d0513 mv a0,s10 -8000bde4: 10c030ef jal ra,8000eef0 <__ssprint_r> -8000bde8: 00050463 beqz a0,8000bdf0 <_svfprintf_r+0x2104> -8000bdec: f21fe06f j 8000ad0c <_svfprintf_r+0x1020> -8000bdf0: 0cc12483 lw s1,204(sp) -8000bdf4: 02012703 lw a4,32(sp) -8000bdf8: 0ec12783 lw a5,236(sp) -8000bdfc: 10c10893 addi a7,sp,268 -8000be00: 409704b3 sub s1,a4,s1 -8000be04: 924ff06f j 8000af28 <_svfprintf_r+0x123c> -8000be08: 02812783 lw a5,40(sp) -8000be0c: 01c12703 lw a4,28(sp) -8000be10: 0017f793 andi a5,a5,1 -8000be14: 01b7e7b3 or a5,a5,s11 -8000be18: 04e054e3 blez a4,8000c660 <_svfprintf_r+0x2974> -8000be1c: 7a079663 bnez a5,8000c5c8 <_svfprintf_r+0x28dc> -8000be20: 01c12c83 lw s9,28(sp) -8000be24: 06600493 li s1,102 -8000be28: 02812783 lw a5,40(sp) -8000be2c: 4007f793 andi a5,a5,1024 -8000be30: 70079e63 bnez a5,8000c54c <_svfprintf_r+0x2860> -8000be34: fffcca93 not s5,s9 -8000be38: 41fada93 srai s5,s5,0x1f -8000be3c: 015cfab3 and s5,s9,s5 -8000be40: de9ff06f j 8000bc28 <_svfprintf_r+0x1f3c> -8000be44: 80015737 lui a4,0x80015 -8000be48: c2470b13 addi s6,a4,-988 # 80014c24 <__BSS_END__+0xffffdff4> -8000be4c: 9a1ff06f j 8000b7ec <_svfprintf_r+0x1b00> -8000be50: 02012783 lw a5,32(sp) -8000be54: 02c12703 lw a4,44(sp) -8000be58: 06700493 li s1,103 -8000be5c: 00e78cb3 add s9,a5,a4 -8000be60: 01c12783 lw a5,28(sp) -8000be64: fcf042e3 bgtz a5,8000be28 <_svfprintf_r+0x213c> -8000be68: 40fc8cb3 sub s9,s9,a5 -8000be6c: 001c8c93 addi s9,s9,1 -8000be70: fffcca93 not s5,s9 -8000be74: 41fada93 srai s5,s5,0x1f -8000be78: 015cfab3 and s5,s9,s5 -8000be7c: dadff06f j 8000bc28 <_svfprintf_r+0x1f3c> -8000be80: 800156b7 lui a3,0x80015 -8000be84: 30c68e93 addi t4,a3,780 # 8001530c <__BSS_END__+0xffffe6dc> -8000be88: f48fe06f j 8000a5d0 <_svfprintf_r+0x8e4> -8000be8c: 03000793 li a5,48 -8000be90: 0cf10423 sb a5,200(sp) -8000be94: 05800793 li a5,88 -8000be98: 002a6713 ori a4,s4,2 -8000be9c: 0cf104a3 sb a5,201(sp) -8000bea0: 02e12423 sw a4,40(sp) -8000bea4: 06300793 li a5,99 -8000bea8: 00012823 sw zero,16(sp) -8000beac: 14c10b13 addi s6,sp,332 -8000beb0: 41b7ce63 blt a5,s11,8000c2cc <_svfprintf_r+0x25e0> -8000beb4: 0fc12303 lw t1,252(sp) -8000beb8: fdf4fb93 andi s7,s1,-33 -8000bebc: 05712a23 sw s7,84(sp) -8000bec0: 04012c23 sw zero,88(sp) -8000bec4: 0f012e03 lw t3,240(sp) -8000bec8: 0f412e83 lw t4,244(sp) -8000becc: 0f812f03 lw t5,248(sp) -8000bed0: 102a6a13 ori s4,s4,258 -8000bed4: 38034263 bltz t1,8000c258 <_svfprintf_r+0x256c> -8000bed8: 06100793 li a5,97 -8000bedc: 54f48e63 beq s1,a5,8000c438 <_svfprintf_r+0x274c> -8000bee0: 04100793 li a5,65 -8000bee4: 00f48463 beq s1,a5,8000beec <_svfprintf_r+0x2200> -8000bee8: ac8fe06f j 8000a1b0 <_svfprintf_r+0x4c4> -8000beec: 0b010a93 addi s5,sp,176 -8000bef0: 000a8513 mv a0,s5 -8000bef4: 05112823 sw a7,80(sp) -8000bef8: 0bc12823 sw t3,176(sp) -8000befc: 0bd12a23 sw t4,180(sp) -8000bf00: 0be12c23 sw t5,184(sp) -8000bf04: 0a612e23 sw t1,188(sp) -8000bf08: 6b0080ef jal ra,800145b8 <__trunctfdf2> -8000bf0c: 0cc10613 addi a2,sp,204 -8000bf10: f94fd0ef jal ra,800096a4 -8000bf14: 00058613 mv a2,a1 -8000bf18: 00050593 mv a1,a0 -8000bf1c: 000a8513 mv a0,s5 -8000bf20: 4a4080ef jal ra,800143c4 <__extenddftf2> -8000bf24: 0b012783 lw a5,176(sp) -8000bf28: 0a010c93 addi s9,sp,160 -8000bf2c: 09010913 addi s2,sp,144 -8000bf30: 08f12823 sw a5,144(sp) -8000bf34: 0b412783 lw a5,180(sp) -8000bf38: 08010613 addi a2,sp,128 -8000bf3c: 00090593 mv a1,s2 -8000bf40: 08f12a23 sw a5,148(sp) -8000bf44: 0b812783 lw a5,184(sp) -8000bf48: 000c8513 mv a0,s9 -8000bf4c: 04c12023 sw a2,64(sp) -8000bf50: 08f12c23 sw a5,152(sp) -8000bf54: 0bc12783 lw a5,188(sp) -8000bf58: 08012023 sw zero,128(sp) -8000bf5c: 08012223 sw zero,132(sp) -8000bf60: 08f12e23 sw a5,156(sp) -8000bf64: 3ffc07b7 lui a5,0x3ffc0 -8000bf68: 08f12623 sw a5,140(sp) -8000bf6c: 08012423 sw zero,136(sp) -8000bf70: 4cd050ef jal ra,80011c3c <__multf3> -8000bf74: 0a012803 lw a6,160(sp) -8000bf78: 0a412e03 lw t3,164(sp) -8000bf7c: 0a812e83 lw t4,168(sp) -8000bf80: 0ac12f03 lw t5,172(sp) -8000bf84: 000c8593 mv a1,s9 -8000bf88: 000a8513 mv a0,s5 -8000bf8c: 0b012823 sw a6,176(sp) -8000bf90: 05012223 sw a6,68(sp) -8000bf94: 0bc12a23 sw t3,180(sp) -8000bf98: 03c12223 sw t3,36(sp) -8000bf9c: 0bd12c23 sw t4,184(sp) -8000bfa0: 03d12023 sw t4,32(sp) -8000bfa4: 0be12e23 sw t5,188(sp) -8000bfa8: 01e12e23 sw t5,28(sp) -8000bfac: 0a012023 sw zero,160(sp) -8000bfb0: 0a012223 sw zero,164(sp) -8000bfb4: 0a012423 sw zero,168(sp) -8000bfb8: 0a012623 sw zero,172(sp) -8000bfbc: 12d050ef jal ra,800118e8 <__eqtf2> -8000bfc0: 01c12f03 lw t5,28(sp) -8000bfc4: 02012e83 lw t4,32(sp) -8000bfc8: 02412e03 lw t3,36(sp) -8000bfcc: 04412803 lw a6,68(sp) -8000bfd0: 05012883 lw a7,80(sp) -8000bfd4: 00051663 bnez a0,8000bfe0 <_svfprintf_r+0x22f4> -8000bfd8: 00100793 li a5,1 -8000bfdc: 0cf12623 sw a5,204(sp) -8000bfe0: 800157b7 lui a5,0x80015 -8000bfe4: c4078793 addi a5,a5,-960 # 80014c40 <__BSS_END__+0xffffe010> -8000bfe8: 02f12223 sw a5,36(sp) -8000bfec: fffd8693 addi a3,s11,-1 -8000bff0: 05412e23 sw s4,92(sp) -8000bff4: 06912223 sw s1,100(sp) -8000bff8: 07b12623 sw s11,108(sp) -8000bffc: 07a12a23 sw s10,116(sp) -8000c000: 07812c23 sw s8,120(sp) -8000c004: 000b0b93 mv s7,s6 -8000c008: 06812023 sw s0,96(sp) -8000c00c: 07312423 sw s3,104(sp) -8000c010: 07112823 sw a7,112(sp) -8000c014: 00068c13 mv s8,a3 -8000c018: 07612e23 sw s6,124(sp) -8000c01c: 00080d13 mv s10,a6 -8000c020: 000e0d93 mv s11,t3 -8000c024: 000e8493 mv s1,t4 -8000c028: 000f0a13 mv s4,t5 -8000c02c: 0480006f j 8000c074 <_svfprintf_r+0x2388> -8000c030: 000c8593 mv a1,s9 -8000c034: 000a8513 mv a0,s5 -8000c038: 02c12023 sw a2,32(sp) -8000c03c: 01f12e23 sw t6,28(sp) -8000c040: 0bf12c23 sw t6,184(sp) -8000c044: 0ac12e23 sw a2,188(sp) -8000c048: 0b612823 sw s6,176(sp) -8000c04c: 0b312a23 sw s3,180(sp) -8000c050: 0a012023 sw zero,160(sp) -8000c054: 0a012223 sw zero,164(sp) -8000c058: 0a012423 sw zero,168(sp) -8000c05c: 0a012623 sw zero,172(sp) -8000c060: 089050ef jal ra,800118e8 <__eqtf2> -8000c064: 01c12f83 lw t6,28(sp) -8000c068: 02012603 lw a2,32(sp) -8000c06c: fffc0c13 addi s8,s8,-1 -8000c070: 0e050263 beqz a0,8000c154 <_svfprintf_r+0x2468> -8000c074: 400307b7 lui a5,0x40030 -8000c078: 00090613 mv a2,s2 -8000c07c: 000c8593 mv a1,s9 -8000c080: 000a8513 mv a0,s5 -8000c084: 08f12e23 sw a5,156(sp) -8000c088: 0ba12023 sw s10,160(sp) -8000c08c: 0bb12223 sw s11,164(sp) -8000c090: 0a912423 sw s1,168(sp) -8000c094: 0b412623 sw s4,172(sp) -8000c098: 08012823 sw zero,144(sp) -8000c09c: 08012a23 sw zero,148(sp) -8000c0a0: 08012c23 sw zero,152(sp) -8000c0a4: 399050ef jal ra,80011c3c <__multf3> -8000c0a8: 000a8513 mv a0,s5 -8000c0ac: 0b4080ef jal ra,80014160 <__fixtfsi> -8000c0b0: 00050593 mv a1,a0 -8000c0b4: 00050413 mv s0,a0 -8000c0b8: 000a8513 mv a0,s5 -8000c0bc: 0b012983 lw s3,176(sp) -8000c0c0: 0b412483 lw s1,180(sp) -8000c0c4: 0b812b03 lw s6,184(sp) -8000c0c8: 0bc12a03 lw s4,188(sp) -8000c0cc: 1a8080ef jal ra,80014274 <__floatsitf> -8000c0d0: 0b012703 lw a4,176(sp) -8000c0d4: 04012603 lw a2,64(sp) -8000c0d8: 00090593 mv a1,s2 -8000c0dc: 08e12023 sw a4,128(sp) -8000c0e0: 0b412703 lw a4,180(sp) -8000c0e4: 000c8513 mv a0,s9 -8000c0e8: 09312823 sw s3,144(sp) -8000c0ec: 08e12223 sw a4,132(sp) -8000c0f0: 0b812703 lw a4,184(sp) -8000c0f4: 08912a23 sw s1,148(sp) -8000c0f8: 09612c23 sw s6,152(sp) -8000c0fc: 08e12423 sw a4,136(sp) -8000c100: 0bc12703 lw a4,188(sp) -8000c104: 09412e23 sw s4,156(sp) -8000c108: 08e12623 sw a4,140(sp) -8000c10c: 335060ef jal ra,80012c40 <__subtf3> -8000c110: 02412783 lw a5,36(sp) -8000c114: 0a012b03 lw s6,160(sp) -8000c118: 0a412983 lw s3,164(sp) -8000c11c: 00878733 add a4,a5,s0 -8000c120: 00074703 lbu a4,0(a4) -8000c124: 0a812f83 lw t6,168(sp) -8000c128: 0ac12603 lw a2,172(sp) -8000c12c: 05712823 sw s7,80(sp) -8000c130: 00eb8023 sb a4,0(s7) -8000c134: 05812223 sw s8,68(sp) -8000c138: fff00793 li a5,-1 -8000c13c: 001b8b93 addi s7,s7,1 -8000c140: 000b0d13 mv s10,s6 -8000c144: 00098d93 mv s11,s3 -8000c148: 000f8493 mv s1,t6 -8000c14c: 00060a13 mv s4,a2 -8000c150: eefc10e3 bne s8,a5,8000c030 <_svfprintf_r+0x2344> -8000c154: 07012883 lw a7,112(sp) -8000c158: 000b0393 mv t2,s6 -8000c15c: 00098293 mv t0,s3 -8000c160: 3ffe0937 lui s2,0x3ffe0 -8000c164: 000c8593 mv a1,s9 -8000c168: 000a8513 mv a0,s5 -8000c16c: 03112023 sw a7,32(sp) -8000c170: 00812e23 sw s0,28(sp) -8000c174: 05c12a03 lw s4,92(sp) -8000c178: 06412483 lw s1,100(sp) -8000c17c: 06012403 lw s0,96(sp) -8000c180: 0a712823 sw t2,176(sp) -8000c184: 06712223 sw t2,100(sp) -8000c188: 0a512a23 sw t0,180(sp) -8000c18c: 06512023 sw t0,96(sp) -8000c190: 0bf12c23 sw t6,184(sp) -8000c194: 05f12e23 sw t6,92(sp) -8000c198: 0ac12e23 sw a2,188(sp) -8000c19c: 04c12023 sw a2,64(sp) -8000c1a0: 0a012023 sw zero,160(sp) -8000c1a4: 0a012223 sw zero,164(sp) -8000c1a8: 0a012423 sw zero,168(sp) -8000c1ac: 0b212623 sw s2,172(sp) -8000c1b0: 005050ef jal ra,800119b4 <__getf2> -8000c1b4: 06c12d83 lw s11,108(sp) -8000c1b8: 07412d03 lw s10,116(sp) -8000c1bc: 07812c03 lw s8,120(sp) -8000c1c0: 07c12b03 lw s6,124(sp) -8000c1c4: 06812983 lw s3,104(sp) -8000c1c8: 02012883 lw a7,32(sp) -8000c1cc: 0aa04063 bgtz a0,8000c26c <_svfprintf_r+0x2580> -8000c1d0: 06412383 lw t2,100(sp) -8000c1d4: 06012283 lw t0,96(sp) -8000c1d8: 05c12f83 lw t6,92(sp) -8000c1dc: 04012603 lw a2,64(sp) -8000c1e0: 000c8593 mv a1,s9 +8000bcb0: 1cd080ef jal ra,8001467c <__trunctfdf2> +8000bcb4: 0cc10613 addi a2,sp,204 +8000bcb8: 8b5fd0ef jal ra,8000956c +8000bcbc: 00058613 mv a2,a1 +8000bcc0: 00050593 mv a1,a0 +8000bcc4: 000a8513 mv a0,s5 +8000bcc8: 7c0080ef jal ra,80014488 <__extenddftf2> +8000bccc: 0b012783 lw a5,176(sp) +8000bcd0: 0a010c93 addi s9,sp,160 +8000bcd4: 09010913 addi s2,sp,144 +8000bcd8: 08f12823 sw a5,144(sp) +8000bcdc: 0b412783 lw a5,180(sp) +8000bce0: 08010613 addi a2,sp,128 +8000bce4: 00090593 mv a1,s2 +8000bce8: 08f12a23 sw a5,148(sp) +8000bcec: 0b812783 lw a5,184(sp) +8000bcf0: 000c8513 mv a0,s9 +8000bcf4: 04c12023 sw a2,64(sp) +8000bcf8: 08f12c23 sw a5,152(sp) +8000bcfc: 0bc12783 lw a5,188(sp) +8000bd00: 08012023 sw zero,128(sp) +8000bd04: 08012223 sw zero,132(sp) +8000bd08: 08f12e23 sw a5,156(sp) +8000bd0c: 3ffc07b7 lui a5,0x3ffc0 +8000bd10: 08f12623 sw a5,140(sp) +8000bd14: 08012423 sw zero,136(sp) +8000bd18: 7e9050ef jal ra,80011d00 <__multf3> +8000bd1c: 0a012803 lw a6,160(sp) +8000bd20: 0a412e03 lw t3,164(sp) +8000bd24: 0a812e83 lw t4,168(sp) +8000bd28: 0ac12f03 lw t5,172(sp) +8000bd2c: 000c8593 mv a1,s9 +8000bd30: 000a8513 mv a0,s5 +8000bd34: 0b012823 sw a6,176(sp) +8000bd38: 05012223 sw a6,68(sp) +8000bd3c: 0bc12a23 sw t3,180(sp) +8000bd40: 03c12223 sw t3,36(sp) +8000bd44: 0bd12c23 sw t4,184(sp) +8000bd48: 03d12023 sw t4,32(sp) +8000bd4c: 0be12e23 sw t5,188(sp) +8000bd50: 01e12e23 sw t5,28(sp) +8000bd54: 0a012023 sw zero,160(sp) +8000bd58: 0a012223 sw zero,164(sp) +8000bd5c: 0a012423 sw zero,168(sp) +8000bd60: 0a012623 sw zero,172(sp) +8000bd64: 449050ef jal ra,800119ac <__eqtf2> +8000bd68: 01c12f03 lw t5,28(sp) +8000bd6c: 02012e83 lw t4,32(sp) +8000bd70: 02412e03 lw t3,36(sp) +8000bd74: 04412803 lw a6,68(sp) +8000bd78: 05012883 lw a7,80(sp) +8000bd7c: 00051663 bnez a0,8000bd88 <_svfprintf_r+0x22f4> +8000bd80: 00100793 li a5,1 +8000bd84: 0cf12623 sw a5,204(sp) +8000bd88: 800157b7 lui a5,0x80015 +8000bd8c: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> +8000bd90: 02f12223 sw a5,36(sp) +8000bd94: fffd8693 addi a3,s11,-1 +8000bd98: 05412e23 sw s4,92(sp) +8000bd9c: 06912223 sw s1,100(sp) +8000bda0: 07b12623 sw s11,108(sp) +8000bda4: 07a12a23 sw s10,116(sp) +8000bda8: 07812c23 sw s8,120(sp) +8000bdac: 000b0b93 mv s7,s6 +8000bdb0: 06812023 sw s0,96(sp) +8000bdb4: 07312423 sw s3,104(sp) +8000bdb8: 07112823 sw a7,112(sp) +8000bdbc: 00068c13 mv s8,a3 +8000bdc0: 07612e23 sw s6,124(sp) +8000bdc4: 00080d13 mv s10,a6 +8000bdc8: 000e0d93 mv s11,t3 +8000bdcc: 000e8493 mv s1,t4 +8000bdd0: 000f0a13 mv s4,t5 +8000bdd4: 0480006f j 8000be1c <_svfprintf_r+0x2388> +8000bdd8: 000c8593 mv a1,s9 +8000bddc: 000a8513 mv a0,s5 +8000bde0: 02c12023 sw a2,32(sp) +8000bde4: 01f12e23 sw t6,28(sp) +8000bde8: 0bf12c23 sw t6,184(sp) +8000bdec: 0ac12e23 sw a2,188(sp) +8000bdf0: 0b612823 sw s6,176(sp) +8000bdf4: 0b312a23 sw s3,180(sp) +8000bdf8: 0a012023 sw zero,160(sp) +8000bdfc: 0a012223 sw zero,164(sp) +8000be00: 0a012423 sw zero,168(sp) +8000be04: 0a012623 sw zero,172(sp) +8000be08: 3a5050ef jal ra,800119ac <__eqtf2> +8000be0c: 01c12f83 lw t6,28(sp) +8000be10: 02012603 lw a2,32(sp) +8000be14: fffc0c13 addi s8,s8,-1 +8000be18: 0e050263 beqz a0,8000befc <_svfprintf_r+0x2468> +8000be1c: 400307b7 lui a5,0x40030 +8000be20: 00090613 mv a2,s2 +8000be24: 000c8593 mv a1,s9 +8000be28: 000a8513 mv a0,s5 +8000be2c: 08f12e23 sw a5,156(sp) +8000be30: 0ba12023 sw s10,160(sp) +8000be34: 0bb12223 sw s11,164(sp) +8000be38: 0a912423 sw s1,168(sp) +8000be3c: 0b412623 sw s4,172(sp) +8000be40: 08012823 sw zero,144(sp) +8000be44: 08012a23 sw zero,148(sp) +8000be48: 08012c23 sw zero,152(sp) +8000be4c: 6b5050ef jal ra,80011d00 <__multf3> +8000be50: 000a8513 mv a0,s5 +8000be54: 3d0080ef jal ra,80014224 <__fixtfsi> +8000be58: 00050593 mv a1,a0 +8000be5c: 00050413 mv s0,a0 +8000be60: 000a8513 mv a0,s5 +8000be64: 0b012983 lw s3,176(sp) +8000be68: 0b412483 lw s1,180(sp) +8000be6c: 0b812b03 lw s6,184(sp) +8000be70: 0bc12a03 lw s4,188(sp) +8000be74: 4c4080ef jal ra,80014338 <__floatsitf> +8000be78: 0b012703 lw a4,176(sp) +8000be7c: 04012603 lw a2,64(sp) +8000be80: 00090593 mv a1,s2 +8000be84: 08e12023 sw a4,128(sp) +8000be88: 0b412703 lw a4,180(sp) +8000be8c: 000c8513 mv a0,s9 +8000be90: 09312823 sw s3,144(sp) +8000be94: 08e12223 sw a4,132(sp) +8000be98: 0b812703 lw a4,184(sp) +8000be9c: 08912a23 sw s1,148(sp) +8000bea0: 09612c23 sw s6,152(sp) +8000bea4: 08e12423 sw a4,136(sp) +8000bea8: 0bc12703 lw a4,188(sp) +8000beac: 09412e23 sw s4,156(sp) +8000beb0: 08e12623 sw a4,140(sp) +8000beb4: 651060ef jal ra,80012d04 <__subtf3> +8000beb8: 02412783 lw a5,36(sp) +8000bebc: 0a012b03 lw s6,160(sp) +8000bec0: 0a412983 lw s3,164(sp) +8000bec4: 00878733 add a4,a5,s0 +8000bec8: 00074703 lbu a4,0(a4) +8000becc: 0a812f83 lw t6,168(sp) +8000bed0: 0ac12603 lw a2,172(sp) +8000bed4: 05712823 sw s7,80(sp) +8000bed8: 00eb8023 sb a4,0(s7) +8000bedc: 05812223 sw s8,68(sp) +8000bee0: fff00793 li a5,-1 +8000bee4: 001b8b93 addi s7,s7,1 +8000bee8: 000b0d13 mv s10,s6 +8000beec: 00098d93 mv s11,s3 +8000bef0: 000f8493 mv s1,t6 +8000bef4: 00060a13 mv s4,a2 +8000bef8: eefc10e3 bne s8,a5,8000bdd8 <_svfprintf_r+0x2344> +8000befc: 07012883 lw a7,112(sp) +8000bf00: 000b0393 mv t2,s6 +8000bf04: 00098293 mv t0,s3 +8000bf08: 3ffe0937 lui s2,0x3ffe0 +8000bf0c: 000c8593 mv a1,s9 +8000bf10: 000a8513 mv a0,s5 +8000bf14: 03112023 sw a7,32(sp) +8000bf18: 00812e23 sw s0,28(sp) +8000bf1c: 05c12a03 lw s4,92(sp) +8000bf20: 06412483 lw s1,100(sp) +8000bf24: 06012403 lw s0,96(sp) +8000bf28: 0a712823 sw t2,176(sp) +8000bf2c: 06712223 sw t2,100(sp) +8000bf30: 0a512a23 sw t0,180(sp) +8000bf34: 06512023 sw t0,96(sp) +8000bf38: 0bf12c23 sw t6,184(sp) +8000bf3c: 05f12e23 sw t6,92(sp) +8000bf40: 0ac12e23 sw a2,188(sp) +8000bf44: 04c12023 sw a2,64(sp) +8000bf48: 0a012023 sw zero,160(sp) +8000bf4c: 0a012223 sw zero,164(sp) +8000bf50: 0a012423 sw zero,168(sp) +8000bf54: 0b212623 sw s2,172(sp) +8000bf58: 321050ef jal ra,80011a78 <__getf2> +8000bf5c: 06c12d83 lw s11,108(sp) +8000bf60: 07412d03 lw s10,116(sp) +8000bf64: 07812c03 lw s8,120(sp) +8000bf68: 07c12b03 lw s6,124(sp) +8000bf6c: 06812983 lw s3,104(sp) +8000bf70: 02012883 lw a7,32(sp) +8000bf74: 0aa04063 bgtz a0,8000c014 <_svfprintf_r+0x2580> +8000bf78: 06412383 lw t2,100(sp) +8000bf7c: 06012283 lw t0,96(sp) +8000bf80: 05c12f83 lw t6,92(sp) +8000bf84: 04012603 lw a2,64(sp) +8000bf88: 000c8593 mv a1,s9 +8000bf8c: 000a8513 mv a0,s5 +8000bf90: 0a712823 sw t2,176(sp) +8000bf94: 0a512a23 sw t0,180(sp) +8000bf98: 0bf12c23 sw t6,184(sp) +8000bf9c: 0ac12e23 sw a2,188(sp) +8000bfa0: 0a012023 sw zero,160(sp) +8000bfa4: 0a012223 sw zero,164(sp) +8000bfa8: 0a012423 sw zero,168(sp) +8000bfac: 0b212623 sw s2,172(sp) +8000bfb0: 1fd050ef jal ra,800119ac <__eqtf2> +8000bfb4: 02012883 lw a7,32(sp) +8000bfb8: 00051863 bnez a0,8000bfc8 <_svfprintf_r+0x2534> +8000bfbc: 01c12783 lw a5,28(sp) +8000bfc0: 0017fc93 andi s9,a5,1 +8000bfc4: 040c9863 bnez s9,8000c014 <_svfprintf_r+0x2580> +8000bfc8: 04412783 lw a5,68(sp) +8000bfcc: 03000613 li a2,48 +8000bfd0: 00178693 addi a3,a5,1 # 40030001 <_start-0x3ffcffff> +8000bfd4: 00db86b3 add a3,s7,a3 +8000bfd8: 0007c863 bltz a5,8000bfe8 <_svfprintf_r+0x2554> +8000bfdc: 001b8b93 addi s7,s7,1 +8000bfe0: fecb8fa3 sb a2,-1(s7) +8000bfe4: fedb9ce3 bne s7,a3,8000bfdc <_svfprintf_r+0x2548> +8000bfe8: 416b87b3 sub a5,s7,s6 +8000bfec: 02f12023 sw a5,32(sp) +8000bff0: 850fe06f j 8000a040 <_svfprintf_r+0x5ac> +8000bff4: 03412423 sw s4,40(sp) +8000bff8: 00012823 sw zero,16(sp) +8000bffc: 00090a13 mv s4,s2 +8000c000: 800007b7 lui a5,0x80000 +8000c004: 0067c333 xor t1,a5,t1 +8000c008: 02d00793 li a5,45 +8000c00c: 04f12c23 sw a5,88(sp) +8000c010: c71ff06f j 8000bc80 <_svfprintf_r+0x21ec> +8000c014: 05012783 lw a5,80(sp) +8000c018: 000b8693 mv a3,s7 +8000c01c: 0cf12e23 sw a5,220(sp) +8000c020: 02412783 lw a5,36(sp) +8000c024: fffbc603 lbu a2,-1(s7) +8000c028: 00f7c583 lbu a1,15(a5) # 8000000f <__BSS_END__+0xfffe93d3> +8000c02c: 02b61063 bne a2,a1,8000c04c <_svfprintf_r+0x25b8> +8000c030: 03000513 li a0,48 +8000c034: fea68fa3 sb a0,-1(a3) +8000c038: 0dc12683 lw a3,220(sp) +8000c03c: fff68793 addi a5,a3,-1 +8000c040: 0cf12e23 sw a5,220(sp) +8000c044: fff6c603 lbu a2,-1(a3) +8000c048: fec586e3 beq a1,a2,8000c034 <_svfprintf_r+0x25a0> +8000c04c: 00160593 addi a1,a2,1 +8000c050: 03900513 li a0,57 +8000c054: 0ff5f593 andi a1,a1,255 +8000c058: 00a60663 beq a2,a0,8000c064 <_svfprintf_r+0x25d0> +8000c05c: feb68fa3 sb a1,-1(a3) +8000c060: f89ff06f j 8000bfe8 <_svfprintf_r+0x2554> +8000c064: 02412783 lw a5,36(sp) +8000c068: 00a7c583 lbu a1,10(a5) +8000c06c: feb68fa3 sb a1,-1(a3) +8000c070: f79ff06f j 8000bfe8 <_svfprintf_r+0x2554> +8000c074: 001d8593 addi a1,s11,1 +8000c078: 000d0513 mv a0,s10 +8000c07c: 01112823 sw a7,16(sp) +8000c080: b29fb0ef jal ra,80007ba8 <_malloc_r> +8000c084: 01012883 lw a7,16(sp) +8000c088: 00050b13 mv s6,a0 +8000c08c: 3e050863 beqz a0,8000c47c <_svfprintf_r+0x29e8> +8000c090: 00a12823 sw a0,16(sp) +8000c094: bc9ff06f j 8000bc5c <_svfprintf_r+0x21c8> +8000c098: 03000793 li a5,48 +8000c09c: 0cf10423 sb a5,200(sp) +8000c0a0: 07800793 li a5,120 +8000c0a4: b9dff06f j 8000bc40 <_svfprintf_r+0x21ac> +8000c0a8: 04700793 li a5,71 +8000c0ac: 01bb0933 add s2,s6,s11 +8000c0b0: 04f12a23 sw a5,84(sp) +8000c0b4: 0a010c93 addi s9,sp,160 +8000c0b8: f25fd06f j 80009fdc <_svfprintf_r+0x548> +8000c0bc: 00812703 lw a4,8(sp) +8000c0c0: 009787b3 add a5,a5,s1 +8000c0c4: 00168693 addi a3,a3,1 +8000c0c8: 00e8a023 sw a4,0(a7) +8000c0cc: 0098a223 sw s1,4(a7) +8000c0d0: 0ef12623 sw a5,236(sp) +8000c0d4: 0ed12423 sw a3,232(sp) +8000c0d8: 00700613 li a2,7 +8000c0dc: b6d65863 bge a2,a3,8000b44c <_svfprintf_r+0x19b8> +8000c0e0: 0e410613 addi a2,sp,228 +8000c0e4: 000c0593 mv a1,s8 +8000c0e8: 000d0513 mv a0,s10 +8000c0ec: 691020ef jal ra,8000ef7c <__ssprint_r> +8000c0f0: 00050463 beqz a0,8000c0f8 <_svfprintf_r+0x2664> +8000c0f4: 9c1fe06f j 8000aab4 <_svfprintf_r+0x1020> +8000c0f8: 0ec12783 lw a5,236(sp) +8000c0fc: 0e812683 lw a3,232(sp) +8000c100: 10c10893 addi a7,sp,268 +8000c104: b4cff06f j 8000b450 <_svfprintf_r+0x19bc> +8000c108: 000a0b93 mv s7,s4 +8000c10c: dfcfe06f j 8000a708 <_svfprintf_r+0xc74> +8000c110: 000d9463 bnez s11,8000c118 <_svfprintf_r+0x2684> +8000c114: 00100d93 li s11,1 +8000c118: 0fc12303 lw t1,252(sp) +8000c11c: 0f012e03 lw t3,240(sp) +8000c120: 0f412e83 lw t4,244(sp) +8000c124: 0f812f03 lw t5,248(sp) +8000c128: 100a6913 ori s2,s4,256 +8000c12c: ec0344e3 bltz t1,8000bff4 <_svfprintf_r+0x2560> +8000c130: 0b010a93 addi s5,sp,176 +8000c134: 0dc10813 addi a6,sp,220 +8000c138: 0d010793 addi a5,sp,208 +8000c13c: 0cc10713 addi a4,sp,204 +8000c140: 000d8693 mv a3,s11 +8000c144: 00200613 li a2,2 +8000c148: 000a8593 mv a1,s5 +8000c14c: 000d0513 mv a0,s10 +8000c150: 05112223 sw a7,68(sp) +8000c154: 0bc12823 sw t3,176(sp) +8000c158: 05c12023 sw t3,64(sp) +8000c15c: 0bd12a23 sw t4,180(sp) +8000c160: 03d12223 sw t4,36(sp) +8000c164: 0be12c23 sw t5,184(sp) +8000c168: 03e12023 sw t5,32(sp) +8000c16c: 0a612e23 sw t1,188(sp) +8000c170: 00612e23 sw t1,28(sp) +8000c174: d30fa0ef jal ra,800066a4 <_ldtoa_r> +8000c178: 01c12303 lw t1,28(sp) +8000c17c: 03412423 sw s4,40(sp) +8000c180: 02012f03 lw t5,32(sp) +8000c184: 02412e83 lw t4,36(sp) +8000c188: 04012e03 lw t3,64(sp) +8000c18c: 04412883 lw a7,68(sp) +8000c190: 00050b13 mv s6,a0 +8000c194: 00090a13 mv s4,s2 +8000c198: 00012823 sw zero,16(sp) +8000c19c: 04012c23 sw zero,88(sp) +8000c1a0: 971ff06f j 8000bb10 <_svfprintf_r+0x207c> +8000c1a4: fff00793 li a5,-1 +8000c1a8: 00f12623 sw a5,12(sp) +8000c1ac: c05fd06f j 80009db0 <_svfprintf_r+0x31c> +8000c1b0: 0d610693 addi a3,sp,214 +8000c1b4: 00061863 bnez a2,8000c1c4 <_svfprintf_r+0x2730> +8000c1b8: 03000693 li a3,48 +8000c1bc: 0cd10b23 sb a3,214(sp) +8000c1c0: 0d710693 addi a3,sp,215 +8000c1c4: 1b010713 addi a4,sp,432 +8000c1c8: 03078793 addi a5,a5,48 +8000c1cc: 40e68633 sub a2,a3,a4 +8000c1d0: 00f68023 sb a5,0(a3) +8000c1d4: 0dd60793 addi a5,a2,221 +8000c1d8: 02f12c23 sw a5,56(sp) +8000c1dc: f65fd06f j 8000a140 <_svfprintf_r+0x6ac> +8000c1e0: 0b010a93 addi s5,sp,176 8000c1e4: 000a8513 mv a0,s5 -8000c1e8: 0a712823 sw t2,176(sp) -8000c1ec: 0a512a23 sw t0,180(sp) -8000c1f0: 0bf12c23 sw t6,184(sp) -8000c1f4: 0ac12e23 sw a2,188(sp) -8000c1f8: 0a012023 sw zero,160(sp) -8000c1fc: 0a012223 sw zero,164(sp) -8000c200: 0a012423 sw zero,168(sp) -8000c204: 0b212623 sw s2,172(sp) -8000c208: 6e0050ef jal ra,800118e8 <__eqtf2> -8000c20c: 02012883 lw a7,32(sp) -8000c210: 00051863 bnez a0,8000c220 <_svfprintf_r+0x2534> -8000c214: 01c12783 lw a5,28(sp) -8000c218: 0017fc93 andi s9,a5,1 -8000c21c: 040c9863 bnez s9,8000c26c <_svfprintf_r+0x2580> -8000c220: 04412783 lw a5,68(sp) -8000c224: 03000613 li a2,48 -8000c228: 00178693 addi a3,a5,1 # 40030001 <_start-0x3ffcffff> -8000c22c: 00db86b3 add a3,s7,a3 -8000c230: 0007c863 bltz a5,8000c240 <_svfprintf_r+0x2554> -8000c234: 001b8b93 addi s7,s7,1 -8000c238: fecb8fa3 sb a2,-1(s7) -8000c23c: fedb9ce3 bne s7,a3,8000c234 <_svfprintf_r+0x2548> -8000c240: 416b87b3 sub a5,s7,s6 -8000c244: 02f12023 sw a5,32(sp) -8000c248: 850fe06f j 8000a298 <_svfprintf_r+0x5ac> -8000c24c: 03412423 sw s4,40(sp) -8000c250: 00012823 sw zero,16(sp) -8000c254: 00090a13 mv s4,s2 -8000c258: 800007b7 lui a5,0x80000 -8000c25c: 0067c333 xor t1,a5,t1 -8000c260: 02d00793 li a5,45 -8000c264: 04f12c23 sw a5,88(sp) -8000c268: c71ff06f j 8000bed8 <_svfprintf_r+0x21ec> -8000c26c: 05012783 lw a5,80(sp) -8000c270: 000b8693 mv a3,s7 -8000c274: 0cf12e23 sw a5,220(sp) -8000c278: 02412783 lw a5,36(sp) -8000c27c: fffbc603 lbu a2,-1(s7) -8000c280: 00f7c583 lbu a1,15(a5) # 8000000f <__BSS_END__+0xfffe93df> -8000c284: 02b61063 bne a2,a1,8000c2a4 <_svfprintf_r+0x25b8> -8000c288: 03000513 li a0,48 -8000c28c: fea68fa3 sb a0,-1(a3) -8000c290: 0dc12683 lw a3,220(sp) -8000c294: fff68793 addi a5,a3,-1 -8000c298: 0cf12e23 sw a5,220(sp) -8000c29c: fff6c603 lbu a2,-1(a3) -8000c2a0: fec586e3 beq a1,a2,8000c28c <_svfprintf_r+0x25a0> -8000c2a4: 00160593 addi a1,a2,1 -8000c2a8: 03900513 li a0,57 -8000c2ac: 0ff5f593 andi a1,a1,255 -8000c2b0: 00a60663 beq a2,a0,8000c2bc <_svfprintf_r+0x25d0> -8000c2b4: feb68fa3 sb a1,-1(a3) -8000c2b8: f89ff06f j 8000c240 <_svfprintf_r+0x2554> -8000c2bc: 02412783 lw a5,36(sp) -8000c2c0: 00a7c583 lbu a1,10(a5) -8000c2c4: feb68fa3 sb a1,-1(a3) -8000c2c8: f79ff06f j 8000c240 <_svfprintf_r+0x2554> -8000c2cc: 001d8593 addi a1,s11,1 -8000c2d0: 000d0513 mv a0,s10 -8000c2d4: 01112823 sw a7,16(sp) -8000c2d8: a19fb0ef jal ra,80007cf0 <_malloc_r> -8000c2dc: 01012883 lw a7,16(sp) -8000c2e0: 00050b13 mv s6,a0 -8000c2e4: 3e050863 beqz a0,8000c6d4 <_svfprintf_r+0x29e8> -8000c2e8: 00a12823 sw a0,16(sp) -8000c2ec: bc9ff06f j 8000beb4 <_svfprintf_r+0x21c8> -8000c2f0: 03000793 li a5,48 -8000c2f4: 0cf10423 sb a5,200(sp) -8000c2f8: 07800793 li a5,120 -8000c2fc: b9dff06f j 8000be98 <_svfprintf_r+0x21ac> -8000c300: 04700793 li a5,71 -8000c304: 01bb0933 add s2,s6,s11 -8000c308: 04f12a23 sw a5,84(sp) -8000c30c: 0a010c93 addi s9,sp,160 -8000c310: f25fd06f j 8000a234 <_svfprintf_r+0x548> -8000c314: 00812703 lw a4,8(sp) -8000c318: 009787b3 add a5,a5,s1 -8000c31c: 00168693 addi a3,a3,1 -8000c320: 00e8a023 sw a4,0(a7) -8000c324: 0098a223 sw s1,4(a7) -8000c328: 0ef12623 sw a5,236(sp) -8000c32c: 0ed12423 sw a3,232(sp) -8000c330: 00700613 li a2,7 -8000c334: b6d65863 bge a2,a3,8000b6a4 <_svfprintf_r+0x19b8> -8000c338: 0e410613 addi a2,sp,228 -8000c33c: 000c0593 mv a1,s8 -8000c340: 000d0513 mv a0,s10 -8000c344: 3ad020ef jal ra,8000eef0 <__ssprint_r> -8000c348: 00050463 beqz a0,8000c350 <_svfprintf_r+0x2664> -8000c34c: 9c1fe06f j 8000ad0c <_svfprintf_r+0x1020> -8000c350: 0ec12783 lw a5,236(sp) -8000c354: 0e812683 lw a3,232(sp) -8000c358: 10c10893 addi a7,sp,268 -8000c35c: b4cff06f j 8000b6a8 <_svfprintf_r+0x19bc> -8000c360: 000a0b93 mv s7,s4 -8000c364: dfcfe06f j 8000a960 <_svfprintf_r+0xc74> -8000c368: 000d9463 bnez s11,8000c370 <_svfprintf_r+0x2684> -8000c36c: 00100d93 li s11,1 -8000c370: 0fc12303 lw t1,252(sp) -8000c374: 0f012e03 lw t3,240(sp) -8000c378: 0f412e83 lw t4,244(sp) -8000c37c: 0f812f03 lw t5,248(sp) -8000c380: 100a6913 ori s2,s4,256 -8000c384: ec0344e3 bltz t1,8000c24c <_svfprintf_r+0x2560> -8000c388: 0b010a93 addi s5,sp,176 -8000c38c: 0dc10813 addi a6,sp,220 -8000c390: 0d010793 addi a5,sp,208 -8000c394: 0cc10713 addi a4,sp,204 -8000c398: 000d8693 mv a3,s11 -8000c39c: 00200613 li a2,2 -8000c3a0: 000a8593 mv a1,s5 -8000c3a4: 000d0513 mv a0,s10 -8000c3a8: 05112223 sw a7,68(sp) -8000c3ac: 0bc12823 sw t3,176(sp) -8000c3b0: 05c12023 sw t3,64(sp) -8000c3b4: 0bd12a23 sw t4,180(sp) -8000c3b8: 03d12223 sw t4,36(sp) -8000c3bc: 0be12c23 sw t5,184(sp) -8000c3c0: 03e12023 sw t5,32(sp) -8000c3c4: 0a612e23 sw t1,188(sp) -8000c3c8: 00612e23 sw t1,28(sp) -8000c3cc: b88fa0ef jal ra,80006754 <_ldtoa_r> -8000c3d0: 01c12303 lw t1,28(sp) -8000c3d4: 03412423 sw s4,40(sp) -8000c3d8: 02012f03 lw t5,32(sp) -8000c3dc: 02412e83 lw t4,36(sp) -8000c3e0: 04012e03 lw t3,64(sp) -8000c3e4: 04412883 lw a7,68(sp) -8000c3e8: 00050b13 mv s6,a0 -8000c3ec: 00090a13 mv s4,s2 -8000c3f0: 00012823 sw zero,16(sp) -8000c3f4: 04012c23 sw zero,88(sp) -8000c3f8: 971ff06f j 8000bd68 <_svfprintf_r+0x207c> -8000c3fc: fff00793 li a5,-1 -8000c400: 00f12623 sw a5,12(sp) -8000c404: c05fd06f j 8000a008 <_svfprintf_r+0x31c> -8000c408: 0d610693 addi a3,sp,214 -8000c40c: 00061863 bnez a2,8000c41c <_svfprintf_r+0x2730> -8000c410: 03000693 li a3,48 -8000c414: 0cd10b23 sb a3,214(sp) -8000c418: 0d710693 addi a3,sp,215 -8000c41c: 1b010713 addi a4,sp,432 -8000c420: 03078793 addi a5,a5,48 -8000c424: 40e68633 sub a2,a3,a4 -8000c428: 00f68023 sb a5,0(a3) -8000c42c: 0dd60793 addi a5,a2,221 -8000c430: 02f12c23 sw a5,56(sp) -8000c434: f65fd06f j 8000a398 <_svfprintf_r+0x6ac> -8000c438: 0b010a93 addi s5,sp,176 -8000c43c: 000a8513 mv a0,s5 -8000c440: 05112823 sw a7,80(sp) -8000c444: 0bc12823 sw t3,176(sp) -8000c448: 0bd12a23 sw t4,180(sp) -8000c44c: 0be12c23 sw t5,184(sp) -8000c450: 0a612e23 sw t1,188(sp) -8000c454: 164080ef jal ra,800145b8 <__trunctfdf2> -8000c458: 0cc10613 addi a2,sp,204 -8000c45c: a48fd0ef jal ra,800096a4 -8000c460: 00058613 mv a2,a1 -8000c464: 00050593 mv a1,a0 -8000c468: 000a8513 mv a0,s5 -8000c46c: 759070ef jal ra,800143c4 <__extenddftf2> -8000c470: 0b012783 lw a5,176(sp) -8000c474: 0a010c93 addi s9,sp,160 -8000c478: 09010913 addi s2,sp,144 -8000c47c: 08f12823 sw a5,144(sp) -8000c480: 0b412783 lw a5,180(sp) -8000c484: 08010613 addi a2,sp,128 -8000c488: 00090593 mv a1,s2 -8000c48c: 08f12a23 sw a5,148(sp) -8000c490: 0b812783 lw a5,184(sp) -8000c494: 000c8513 mv a0,s9 -8000c498: 04c12023 sw a2,64(sp) -8000c49c: 08f12c23 sw a5,152(sp) -8000c4a0: 0bc12783 lw a5,188(sp) -8000c4a4: 08012023 sw zero,128(sp) -8000c4a8: 08012223 sw zero,132(sp) -8000c4ac: 08f12e23 sw a5,156(sp) -8000c4b0: 3ffc07b7 lui a5,0x3ffc0 -8000c4b4: 08f12623 sw a5,140(sp) -8000c4b8: 08012423 sw zero,136(sp) -8000c4bc: 780050ef jal ra,80011c3c <__multf3> -8000c4c0: 0a012803 lw a6,160(sp) -8000c4c4: 0a412e03 lw t3,164(sp) -8000c4c8: 0a812e83 lw t4,168(sp) -8000c4cc: 0ac12f03 lw t5,172(sp) -8000c4d0: 000c8593 mv a1,s9 -8000c4d4: 000a8513 mv a0,s5 -8000c4d8: 0b012823 sw a6,176(sp) -8000c4dc: 05012223 sw a6,68(sp) -8000c4e0: 0bc12a23 sw t3,180(sp) -8000c4e4: 03c12223 sw t3,36(sp) -8000c4e8: 0bd12c23 sw t4,184(sp) -8000c4ec: 03d12023 sw t4,32(sp) -8000c4f0: 0be12e23 sw t5,188(sp) -8000c4f4: 01e12e23 sw t5,28(sp) -8000c4f8: 0a012023 sw zero,160(sp) -8000c4fc: 0a012223 sw zero,164(sp) -8000c500: 0a012423 sw zero,168(sp) -8000c504: 0a012623 sw zero,172(sp) -8000c508: 3e0050ef jal ra,800118e8 <__eqtf2> -8000c50c: 01c12f03 lw t5,28(sp) -8000c510: 02012e83 lw t4,32(sp) -8000c514: 02412e03 lw t3,36(sp) -8000c518: 04412803 lw a6,68(sp) -8000c51c: 05012883 lw a7,80(sp) -8000c520: 00051663 bnez a0,8000c52c <_svfprintf_r+0x2840> -8000c524: 00100793 li a5,1 -8000c528: 0cf12623 sw a5,204(sp) -8000c52c: 800157b7 lui a5,0x80015 -8000c530: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -8000c534: 02f12223 sw a5,36(sp) -8000c538: ab5ff06f j 8000bfec <_svfprintf_r+0x2300> -8000c53c: 00012823 sw zero,16(sp) -8000c540: 00078a13 mv s4,a5 -8000c544: d15ff06f j 8000c258 <_svfprintf_r+0x256c> -8000c548: 06700493 li s1,103 -8000c54c: 03c12603 lw a2,60(sp) -8000c550: 0ff00693 li a3,255 -8000c554: 00064783 lbu a5,0(a2) -8000c558: 18d78863 beq a5,a3,8000c6e8 <_svfprintf_r+0x29fc> -8000c55c: 01c12703 lw a4,28(sp) -8000c560: 00000513 li a0,0 -8000c564: 00000593 li a1,0 -8000c568: 00e7de63 bge a5,a4,8000c584 <_svfprintf_r+0x2898> -8000c56c: 40f70733 sub a4,a4,a5 -8000c570: 00164783 lbu a5,1(a2) -8000c574: 04078463 beqz a5,8000c5bc <_svfprintf_r+0x28d0> -8000c578: 00158593 addi a1,a1,1 -8000c57c: 00160613 addi a2,a2,1 -8000c580: fed794e3 bne a5,a3,8000c568 <_svfprintf_r+0x287c> -8000c584: 02c12e23 sw a2,60(sp) -8000c588: 00e12e23 sw a4,28(sp) -8000c58c: 02b12223 sw a1,36(sp) -8000c590: 02a12423 sw a0,40(sp) -8000c594: 02812703 lw a4,40(sp) -8000c598: 02412783 lw a5,36(sp) -8000c59c: 00e787b3 add a5,a5,a4 -8000c5a0: 04812703 lw a4,72(sp) -8000c5a4: 02e787b3 mul a5,a5,a4 -8000c5a8: 01978cb3 add s9,a5,s9 -8000c5ac: fffcca93 not s5,s9 -8000c5b0: 41fada93 srai s5,s5,0x1f -8000c5b4: 015cfab3 and s5,s9,s5 -8000c5b8: e25fd06f j 8000a3dc <_svfprintf_r+0x6f0> -8000c5bc: 00064783 lbu a5,0(a2) -8000c5c0: 00150513 addi a0,a0,1 -8000c5c4: fbdff06f j 8000c580 <_svfprintf_r+0x2894> -8000c5c8: 02c12783 lw a5,44(sp) -8000c5cc: 06600493 li s1,102 -8000c5d0: 00f70cb3 add s9,a4,a5 -8000c5d4: 01bc8cb3 add s9,s9,s11 -8000c5d8: 851ff06f j 8000be28 <_svfprintf_r+0x213c> -8000c5dc: 02812783 lw a5,40(sp) -8000c5e0: 0017f793 andi a5,a5,1 -8000c5e4: 00079463 bnez a5,8000c5ec <_svfprintf_r+0x2900> -8000c5e8: dd1fd06f j 8000a3b8 <_svfprintf_r+0x6cc> -8000c5ec: dc5fd06f j 8000a3b0 <_svfprintf_r+0x6c4> -8000c5f0: 0a010c93 addi s9,sp,160 -8000c5f4: 000c8593 mv a1,s9 -8000c5f8: 000a8513 mv a0,s5 -8000c5fc: 05112223 sw a7,68(sp) -8000c600: 0bc12823 sw t3,176(sp) -8000c604: 05c12023 sw t3,64(sp) -8000c608: 0bd12a23 sw t4,180(sp) -8000c60c: 03d12223 sw t4,36(sp) -8000c610: 0be12c23 sw t5,184(sp) -8000c614: 03e12023 sw t5,32(sp) -8000c618: 0a612e23 sw t1,188(sp) -8000c61c: 00612e23 sw t1,28(sp) -8000c620: 0a012023 sw zero,160(sp) -8000c624: 0a012223 sw zero,164(sp) -8000c628: 0a012423 sw zero,168(sp) -8000c62c: 0a012623 sw zero,172(sp) -8000c630: 2b8050ef jal ra,800118e8 <__eqtf2> -8000c634: 01c12303 lw t1,28(sp) -8000c638: 02012f03 lw t5,32(sp) -8000c63c: 02412e83 lw t4,36(sp) -8000c640: 04012e03 lw t3,64(sp) -8000c644: 04412883 lw a7,68(sp) -8000c648: ea050263 beqz a0,8000bcec <_svfprintf_r+0x2000> -8000c64c: 00100793 li a5,1 -8000c650: 41b787b3 sub a5,a5,s11 -8000c654: 0cf12623 sw a5,204(sp) -8000c658: 00f90933 add s2,s2,a5 -8000c65c: bd9fd06f j 8000a234 <_svfprintf_r+0x548> -8000c660: 00079a63 bnez a5,8000c674 <_svfprintf_r+0x2988> -8000c664: 00100a93 li s5,1 -8000c668: 06600493 li s1,102 -8000c66c: 00100c93 li s9,1 -8000c670: db8ff06f j 8000bc28 <_svfprintf_r+0x1f3c> -8000c674: 02c12783 lw a5,44(sp) -8000c678: 06600493 li s1,102 -8000c67c: 00178c93 addi s9,a5,1 -8000c680: 01bc8cb3 add s9,s9,s11 -8000c684: fffcca93 not s5,s9 -8000c688: 41fada93 srai s5,s5,0x1f -8000c68c: 015cfab3 and s5,s9,s5 -8000c690: d98ff06f j 8000bc28 <_svfprintf_r+0x1f3c> -8000c694: 00088713 mv a4,a7 -8000c698: a7cff06f j 8000b914 <_svfprintf_r+0x1c28> -8000c69c: 01412783 lw a5,20(sp) -8000c6a0: 0007ad83 lw s11,0(a5) -8000c6a4: 00478793 addi a5,a5,4 -8000c6a8: 000dd463 bgez s11,8000c6b0 <_svfprintf_r+0x29c4> -8000c6ac: fff00d93 li s11,-1 -8000c6b0: 00144483 lbu s1,1(s0) -8000c6b4: 00f12a23 sw a5,20(sp) -8000c6b8: 00070413 mv s0,a4 -8000c6bc: f94fd06f j 80009e50 <_svfprintf_r+0x164> -8000c6c0: 00c00793 li a5,12 -8000c6c4: 00fd2023 sw a5,0(s10) -8000c6c8: fff00793 li a5,-1 -8000c6cc: 00f12623 sw a5,12(sp) -8000c6d0: 939fd06f j 8000a008 <_svfprintf_r+0x31c> -8000c6d4: 00cc5703 lhu a4,12(s8) -8000c6d8: 04076793 ori a5,a4,64 -8000c6dc: 00078713 mv a4,a5 -8000c6e0: 00fc1623 sh a5,12(s8) -8000c6e4: 919fd06f j 80009ffc <_svfprintf_r+0x310> -8000c6e8: 02012423 sw zero,40(sp) -8000c6ec: 02012223 sw zero,36(sp) -8000c6f0: ea5ff06f j 8000c594 <_svfprintf_r+0x28a8> -8000c6f4: 00200793 li a5,2 -8000c6f8: 02f12c23 sw a5,56(sp) -8000c6fc: c9dfd06f j 8000a398 <_svfprintf_r+0x6ac> +8000c1e8: 05112823 sw a7,80(sp) +8000c1ec: 0bc12823 sw t3,176(sp) +8000c1f0: 0bd12a23 sw t4,180(sp) +8000c1f4: 0be12c23 sw t5,184(sp) +8000c1f8: 0a612e23 sw t1,188(sp) +8000c1fc: 480080ef jal ra,8001467c <__trunctfdf2> +8000c200: 0cc10613 addi a2,sp,204 +8000c204: b68fd0ef jal ra,8000956c +8000c208: 00058613 mv a2,a1 +8000c20c: 00050593 mv a1,a0 +8000c210: 000a8513 mv a0,s5 +8000c214: 274080ef jal ra,80014488 <__extenddftf2> +8000c218: 0b012783 lw a5,176(sp) +8000c21c: 0a010c93 addi s9,sp,160 +8000c220: 09010913 addi s2,sp,144 +8000c224: 08f12823 sw a5,144(sp) +8000c228: 0b412783 lw a5,180(sp) +8000c22c: 08010613 addi a2,sp,128 +8000c230: 00090593 mv a1,s2 +8000c234: 08f12a23 sw a5,148(sp) +8000c238: 0b812783 lw a5,184(sp) +8000c23c: 000c8513 mv a0,s9 +8000c240: 04c12023 sw a2,64(sp) +8000c244: 08f12c23 sw a5,152(sp) +8000c248: 0bc12783 lw a5,188(sp) +8000c24c: 08012023 sw zero,128(sp) +8000c250: 08012223 sw zero,132(sp) +8000c254: 08f12e23 sw a5,156(sp) +8000c258: 3ffc07b7 lui a5,0x3ffc0 +8000c25c: 08f12623 sw a5,140(sp) +8000c260: 08012423 sw zero,136(sp) +8000c264: 29d050ef jal ra,80011d00 <__multf3> +8000c268: 0a012803 lw a6,160(sp) +8000c26c: 0a412e03 lw t3,164(sp) +8000c270: 0a812e83 lw t4,168(sp) +8000c274: 0ac12f03 lw t5,172(sp) +8000c278: 000c8593 mv a1,s9 +8000c27c: 000a8513 mv a0,s5 +8000c280: 0b012823 sw a6,176(sp) +8000c284: 05012223 sw a6,68(sp) +8000c288: 0bc12a23 sw t3,180(sp) +8000c28c: 03c12223 sw t3,36(sp) +8000c290: 0bd12c23 sw t4,184(sp) +8000c294: 03d12023 sw t4,32(sp) +8000c298: 0be12e23 sw t5,188(sp) +8000c29c: 01e12e23 sw t5,28(sp) +8000c2a0: 0a012023 sw zero,160(sp) +8000c2a4: 0a012223 sw zero,164(sp) +8000c2a8: 0a012423 sw zero,168(sp) +8000c2ac: 0a012623 sw zero,172(sp) +8000c2b0: 6fc050ef jal ra,800119ac <__eqtf2> +8000c2b4: 01c12f03 lw t5,28(sp) +8000c2b8: 02012e83 lw t4,32(sp) +8000c2bc: 02412e03 lw t3,36(sp) +8000c2c0: 04412803 lw a6,68(sp) +8000c2c4: 05012883 lw a7,80(sp) +8000c2c8: 00051663 bnez a0,8000c2d4 <_svfprintf_r+0x2840> +8000c2cc: 00100793 li a5,1 +8000c2d0: 0cf12623 sw a5,204(sp) +8000c2d4: 800157b7 lui a5,0x80015 +8000c2d8: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +8000c2dc: 02f12223 sw a5,36(sp) +8000c2e0: ab5ff06f j 8000bd94 <_svfprintf_r+0x2300> +8000c2e4: 00012823 sw zero,16(sp) +8000c2e8: 00078a13 mv s4,a5 +8000c2ec: d15ff06f j 8000c000 <_svfprintf_r+0x256c> +8000c2f0: 06700493 li s1,103 +8000c2f4: 03c12603 lw a2,60(sp) +8000c2f8: 0ff00693 li a3,255 +8000c2fc: 00064783 lbu a5,0(a2) +8000c300: 18d78863 beq a5,a3,8000c490 <_svfprintf_r+0x29fc> +8000c304: 01c12703 lw a4,28(sp) +8000c308: 00000513 li a0,0 +8000c30c: 00000593 li a1,0 +8000c310: 00e7de63 bge a5,a4,8000c32c <_svfprintf_r+0x2898> +8000c314: 40f70733 sub a4,a4,a5 +8000c318: 00164783 lbu a5,1(a2) +8000c31c: 04078463 beqz a5,8000c364 <_svfprintf_r+0x28d0> +8000c320: 00158593 addi a1,a1,1 +8000c324: 00160613 addi a2,a2,1 +8000c328: fed794e3 bne a5,a3,8000c310 <_svfprintf_r+0x287c> +8000c32c: 02c12e23 sw a2,60(sp) +8000c330: 00e12e23 sw a4,28(sp) +8000c334: 02b12223 sw a1,36(sp) +8000c338: 02a12423 sw a0,40(sp) +8000c33c: 02812703 lw a4,40(sp) +8000c340: 02412783 lw a5,36(sp) +8000c344: 00e787b3 add a5,a5,a4 +8000c348: 04812703 lw a4,72(sp) +8000c34c: 02e787b3 mul a5,a5,a4 +8000c350: 01978cb3 add s9,a5,s9 +8000c354: fffcca93 not s5,s9 +8000c358: 41fada93 srai s5,s5,0x1f +8000c35c: 015cfab3 and s5,s9,s5 +8000c360: e25fd06f j 8000a184 <_svfprintf_r+0x6f0> +8000c364: 00064783 lbu a5,0(a2) +8000c368: 00150513 addi a0,a0,1 +8000c36c: fbdff06f j 8000c328 <_svfprintf_r+0x2894> +8000c370: 02c12783 lw a5,44(sp) +8000c374: 06600493 li s1,102 +8000c378: 00f70cb3 add s9,a4,a5 +8000c37c: 01bc8cb3 add s9,s9,s11 +8000c380: 851ff06f j 8000bbd0 <_svfprintf_r+0x213c> +8000c384: 02812783 lw a5,40(sp) +8000c388: 0017f793 andi a5,a5,1 +8000c38c: 00079463 bnez a5,8000c394 <_svfprintf_r+0x2900> +8000c390: dd1fd06f j 8000a160 <_svfprintf_r+0x6cc> +8000c394: dc5fd06f j 8000a158 <_svfprintf_r+0x6c4> +8000c398: 0a010c93 addi s9,sp,160 +8000c39c: 000c8593 mv a1,s9 +8000c3a0: 000a8513 mv a0,s5 +8000c3a4: 05112223 sw a7,68(sp) +8000c3a8: 0bc12823 sw t3,176(sp) +8000c3ac: 05c12023 sw t3,64(sp) +8000c3b0: 0bd12a23 sw t4,180(sp) +8000c3b4: 03d12223 sw t4,36(sp) +8000c3b8: 0be12c23 sw t5,184(sp) +8000c3bc: 03e12023 sw t5,32(sp) +8000c3c0: 0a612e23 sw t1,188(sp) +8000c3c4: 00612e23 sw t1,28(sp) +8000c3c8: 0a012023 sw zero,160(sp) +8000c3cc: 0a012223 sw zero,164(sp) +8000c3d0: 0a012423 sw zero,168(sp) +8000c3d4: 0a012623 sw zero,172(sp) +8000c3d8: 5d4050ef jal ra,800119ac <__eqtf2> +8000c3dc: 01c12303 lw t1,28(sp) +8000c3e0: 02012f03 lw t5,32(sp) +8000c3e4: 02412e83 lw t4,36(sp) +8000c3e8: 04012e03 lw t3,64(sp) +8000c3ec: 04412883 lw a7,68(sp) +8000c3f0: ea050263 beqz a0,8000ba94 <_svfprintf_r+0x2000> +8000c3f4: 00100793 li a5,1 +8000c3f8: 41b787b3 sub a5,a5,s11 +8000c3fc: 0cf12623 sw a5,204(sp) +8000c400: 00f90933 add s2,s2,a5 +8000c404: bd9fd06f j 80009fdc <_svfprintf_r+0x548> +8000c408: 00079a63 bnez a5,8000c41c <_svfprintf_r+0x2988> +8000c40c: 00100a93 li s5,1 +8000c410: 06600493 li s1,102 +8000c414: 00100c93 li s9,1 +8000c418: db8ff06f j 8000b9d0 <_svfprintf_r+0x1f3c> +8000c41c: 02c12783 lw a5,44(sp) +8000c420: 06600493 li s1,102 +8000c424: 00178c93 addi s9,a5,1 +8000c428: 01bc8cb3 add s9,s9,s11 +8000c42c: fffcca93 not s5,s9 +8000c430: 41fada93 srai s5,s5,0x1f +8000c434: 015cfab3 and s5,s9,s5 +8000c438: d98ff06f j 8000b9d0 <_svfprintf_r+0x1f3c> +8000c43c: 00088713 mv a4,a7 +8000c440: a7cff06f j 8000b6bc <_svfprintf_r+0x1c28> +8000c444: 01412783 lw a5,20(sp) +8000c448: 0007ad83 lw s11,0(a5) +8000c44c: 00478793 addi a5,a5,4 +8000c450: 000dd463 bgez s11,8000c458 <_svfprintf_r+0x29c4> +8000c454: fff00d93 li s11,-1 +8000c458: 00144483 lbu s1,1(s0) +8000c45c: 00f12a23 sw a5,20(sp) +8000c460: 00070413 mv s0,a4 +8000c464: f94fd06f j 80009bf8 <_svfprintf_r+0x164> +8000c468: 00c00793 li a5,12 +8000c46c: 00fd2023 sw a5,0(s10) +8000c470: fff00793 li a5,-1 +8000c474: 00f12623 sw a5,12(sp) +8000c478: 939fd06f j 80009db0 <_svfprintf_r+0x31c> +8000c47c: 00cc5703 lhu a4,12(s8) +8000c480: 04076793 ori a5,a4,64 +8000c484: 00078713 mv a4,a5 +8000c488: 00fc1623 sh a5,12(s8) +8000c48c: 919fd06f j 80009da4 <_svfprintf_r+0x310> +8000c490: 02012423 sw zero,40(sp) +8000c494: 02012223 sw zero,36(sp) +8000c498: ea5ff06f j 8000c33c <_svfprintf_r+0x28a8> +8000c49c: 00200793 li a5,2 +8000c4a0: 02f12c23 sw a5,56(sp) +8000c4a4: c9dfd06f j 8000a140 <_svfprintf_r+0x6ac> -8000c700 <__sprint_r.part.0>: -8000c700: 0645a783 lw a5,100(a1) -8000c704: fd010113 addi sp,sp,-48 -8000c708: 01612823 sw s6,16(sp) -8000c70c: 02112623 sw ra,44(sp) -8000c710: 02812423 sw s0,40(sp) -8000c714: 02912223 sw s1,36(sp) -8000c718: 03212023 sw s2,32(sp) -8000c71c: 01312e23 sw s3,28(sp) -8000c720: 01412c23 sw s4,24(sp) -8000c724: 01512a23 sw s5,20(sp) -8000c728: 01712623 sw s7,12(sp) -8000c72c: 01812423 sw s8,8(sp) -8000c730: 01279713 slli a4,a5,0x12 -8000c734: 00060b13 mv s6,a2 -8000c738: 0a075863 bgez a4,8000c7e8 <__sprint_r.part.0+0xe8> -8000c73c: 00862783 lw a5,8(a2) -8000c740: 00062b83 lw s7,0(a2) -8000c744: 00058913 mv s2,a1 -8000c748: 00050993 mv s3,a0 -8000c74c: fff00a93 li s5,-1 -8000c750: 08078863 beqz a5,8000c7e0 <__sprint_r.part.0+0xe0> -8000c754: 004bac03 lw s8,4(s7) -8000c758: 000ba403 lw s0,0(s7) -8000c75c: 002c5a13 srli s4,s8,0x2 -8000c760: 060a0663 beqz s4,8000c7cc <__sprint_r.part.0+0xcc> -8000c764: 00000493 li s1,0 -8000c768: 00c0006f j 8000c774 <__sprint_r.part.0+0x74> -8000c76c: 00440413 addi s0,s0,4 -8000c770: 049a0c63 beq s4,s1,8000c7c8 <__sprint_r.part.0+0xc8> -8000c774: 00042583 lw a1,0(s0) -8000c778: 00090613 mv a2,s2 -8000c77c: 00098513 mv a0,s3 -8000c780: 798010ef jal ra,8000df18 <_fputwc_r> -8000c784: 00148493 addi s1,s1,1 -8000c788: ff5512e3 bne a0,s5,8000c76c <__sprint_r.part.0+0x6c> -8000c78c: fff00513 li a0,-1 -8000c790: 02c12083 lw ra,44(sp) -8000c794: 02812403 lw s0,40(sp) -8000c798: 000b2423 sw zero,8(s6) -8000c79c: 000b2223 sw zero,4(s6) -8000c7a0: 02412483 lw s1,36(sp) -8000c7a4: 02012903 lw s2,32(sp) -8000c7a8: 01c12983 lw s3,28(sp) -8000c7ac: 01812a03 lw s4,24(sp) -8000c7b0: 01412a83 lw s5,20(sp) -8000c7b4: 01012b03 lw s6,16(sp) -8000c7b8: 00c12b83 lw s7,12(sp) -8000c7bc: 00812c03 lw s8,8(sp) -8000c7c0: 03010113 addi sp,sp,48 -8000c7c4: 00008067 ret -8000c7c8: 008b2783 lw a5,8(s6) -8000c7cc: ffcc7c13 andi s8,s8,-4 -8000c7d0: 418787b3 sub a5,a5,s8 -8000c7d4: 00fb2423 sw a5,8(s6) -8000c7d8: 008b8b93 addi s7,s7,8 -8000c7dc: f6079ce3 bnez a5,8000c754 <__sprint_r.part.0+0x54> -8000c7e0: 00000513 li a0,0 -8000c7e4: fadff06f j 8000c790 <__sprint_r.part.0+0x90> -8000c7e8: 03d010ef jal ra,8000e024 <__sfvwrite_r> -8000c7ec: fa5ff06f j 8000c790 <__sprint_r.part.0+0x90> +8000c4a8 <__sprint_r.part.0>: +8000c4a8: 0645a783 lw a5,100(a1) +8000c4ac: fd010113 addi sp,sp,-48 +8000c4b0: 01612823 sw s6,16(sp) +8000c4b4: 02112623 sw ra,44(sp) +8000c4b8: 02812423 sw s0,40(sp) +8000c4bc: 02912223 sw s1,36(sp) +8000c4c0: 03212023 sw s2,32(sp) +8000c4c4: 01312e23 sw s3,28(sp) +8000c4c8: 01412c23 sw s4,24(sp) +8000c4cc: 01512a23 sw s5,20(sp) +8000c4d0: 01712623 sw s7,12(sp) +8000c4d4: 01812423 sw s8,8(sp) +8000c4d8: 01279713 slli a4,a5,0x12 +8000c4dc: 00060b13 mv s6,a2 +8000c4e0: 0a075863 bgez a4,8000c590 <__sprint_r.part.0+0xe8> +8000c4e4: 00862783 lw a5,8(a2) +8000c4e8: 00062b83 lw s7,0(a2) +8000c4ec: 00058913 mv s2,a1 +8000c4f0: 00050993 mv s3,a0 +8000c4f4: fff00a93 li s5,-1 +8000c4f8: 08078863 beqz a5,8000c588 <__sprint_r.part.0+0xe0> +8000c4fc: 004bac03 lw s8,4(s7) +8000c500: 000ba403 lw s0,0(s7) +8000c504: 002c5a13 srli s4,s8,0x2 +8000c508: 060a0663 beqz s4,8000c574 <__sprint_r.part.0+0xcc> +8000c50c: 00000493 li s1,0 +8000c510: 00c0006f j 8000c51c <__sprint_r.part.0+0x74> +8000c514: 00440413 addi s0,s0,4 +8000c518: 049a0c63 beq s4,s1,8000c570 <__sprint_r.part.0+0xc8> +8000c51c: 00042583 lw a1,0(s0) +8000c520: 00090613 mv a2,s2 +8000c524: 00098513 mv a0,s3 +8000c528: 7f8010ef jal ra,8000dd20 <_fputwc_r> +8000c52c: 00148493 addi s1,s1,1 +8000c530: ff5512e3 bne a0,s5,8000c514 <__sprint_r.part.0+0x6c> +8000c534: fff00513 li a0,-1 +8000c538: 02c12083 lw ra,44(sp) +8000c53c: 02812403 lw s0,40(sp) +8000c540: 000b2423 sw zero,8(s6) +8000c544: 000b2223 sw zero,4(s6) +8000c548: 02412483 lw s1,36(sp) +8000c54c: 02012903 lw s2,32(sp) +8000c550: 01c12983 lw s3,28(sp) +8000c554: 01812a03 lw s4,24(sp) +8000c558: 01412a83 lw s5,20(sp) +8000c55c: 01012b03 lw s6,16(sp) +8000c560: 00c12b83 lw s7,12(sp) +8000c564: 00812c03 lw s8,8(sp) +8000c568: 03010113 addi sp,sp,48 +8000c56c: 00008067 ret +8000c570: 008b2783 lw a5,8(s6) +8000c574: ffcc7c13 andi s8,s8,-4 +8000c578: 418787b3 sub a5,a5,s8 +8000c57c: 00fb2423 sw a5,8(s6) +8000c580: 008b8b93 addi s7,s7,8 +8000c584: f6079ce3 bnez a5,8000c4fc <__sprint_r.part.0+0x54> +8000c588: 00000513 li a0,0 +8000c58c: fadff06f j 8000c538 <__sprint_r.part.0+0x90> +8000c590: 09d010ef jal ra,8000de2c <__sfvwrite_r> +8000c594: fa5ff06f j 8000c538 <__sprint_r.part.0+0x90> -8000c7f0 <__sprint_r>: -8000c7f0: 00862703 lw a4,8(a2) -8000c7f4: 00070463 beqz a4,8000c7fc <__sprint_r+0xc> -8000c7f8: f09ff06f j 8000c700 <__sprint_r.part.0> -8000c7fc: 00062223 sw zero,4(a2) -8000c800: 00000513 li a0,0 -8000c804: 00008067 ret +8000c598 <__sprint_r>: +8000c598: 00862703 lw a4,8(a2) +8000c59c: 00070463 beqz a4,8000c5a4 <__sprint_r+0xc> +8000c5a0: f09ff06f j 8000c4a8 <__sprint_r.part.0> +8000c5a4: 00062223 sw zero,4(a2) +8000c5a8: 00000513 li a0,0 +8000c5ac: 00008067 ret -8000c808 <_vfiprintf_r>: -8000c808: ed010113 addi sp,sp,-304 -8000c80c: 11312e23 sw s3,284(sp) -8000c810: 11412c23 sw s4,280(sp) -8000c814: 11712623 sw s7,268(sp) -8000c818: 12112623 sw ra,300(sp) -8000c81c: 12812423 sw s0,296(sp) -8000c820: 12912223 sw s1,292(sp) -8000c824: 13212023 sw s2,288(sp) -8000c828: 11512a23 sw s5,276(sp) -8000c82c: 11612823 sw s6,272(sp) -8000c830: 11812423 sw s8,264(sp) -8000c834: 11912223 sw s9,260(sp) -8000c838: 11a12023 sw s10,256(sp) -8000c83c: 0fb12e23 sw s11,252(sp) -8000c840: 00d12823 sw a3,16(sp) -8000c844: 00050a13 mv s4,a0 -8000c848: 00058993 mv s3,a1 -8000c84c: 00060b93 mv s7,a2 -8000c850: 00050663 beqz a0,8000c85c <_vfiprintf_r+0x54> -8000c854: 03852783 lw a5,56(a0) -8000c858: 5e078e63 beqz a5,8000ce54 <_vfiprintf_r+0x64c> -8000c85c: 00c99703 lh a4,12(s3) -8000c860: 01071793 slli a5,a4,0x10 -8000c864: 01271693 slli a3,a4,0x12 -8000c868: 0107d793 srli a5,a5,0x10 -8000c86c: 0206ca63 bltz a3,8000c8a0 <_vfiprintf_r+0x98> -8000c870: 000027b7 lui a5,0x2 -8000c874: 0649a683 lw a3,100(s3) -8000c878: 00f767b3 or a5,a4,a5 -8000c87c: 01079793 slli a5,a5,0x10 -8000c880: ffffe737 lui a4,0xffffe -8000c884: 4107d793 srai a5,a5,0x10 -8000c888: fff70713 addi a4,a4,-1 # ffffdfff <__BSS_END__+0x7ffe73cf> -8000c88c: 00e6f733 and a4,a3,a4 -8000c890: 00f99623 sh a5,12(s3) -8000c894: 01079793 slli a5,a5,0x10 -8000c898: 06e9a223 sw a4,100(s3) -8000c89c: 0107d793 srli a5,a5,0x10 -8000c8a0: 0087f713 andi a4,a5,8 -8000c8a4: 40070063 beqz a4,8000cca4 <_vfiprintf_r+0x49c> -8000c8a8: 0109a703 lw a4,16(s3) -8000c8ac: 3e070c63 beqz a4,8000cca4 <_vfiprintf_r+0x49c> -8000c8b0: 01a7f793 andi a5,a5,26 -8000c8b4: 00a00713 li a4,10 -8000c8b8: 40e78663 beq a5,a4,8000ccc4 <_vfiprintf_r+0x4bc> -8000c8bc: 800157b7 lui a5,0x80015 -8000c8c0: 32c78793 addi a5,a5,812 # 8001532c <__BSS_END__+0xffffe6fc> -8000c8c4: 80015b37 lui s6,0x80015 -8000c8c8: 04c10493 addi s1,sp,76 -8000c8cc: 00f12a23 sw a5,20(sp) -8000c8d0: 80015937 lui s2,0x80015 -8000c8d4: 498b0793 addi a5,s6,1176 # 80015498 <__BSS_END__+0xffffe868> -8000c8d8: 000b8c13 mv s8,s7 -8000c8dc: 04912023 sw s1,64(sp) -8000c8e0: 04012423 sw zero,72(sp) -8000c8e4: 04012223 sw zero,68(sp) -8000c8e8: 00012c23 sw zero,24(sp) -8000c8ec: 00012e23 sw zero,28(sp) -8000c8f0: 02012223 sw zero,36(sp) -8000c8f4: 02012023 sw zero,32(sp) -8000c8f8: 00012623 sw zero,12(sp) -8000c8fc: 00f12423 sw a5,8(sp) -8000c900: 4a890913 addi s2,s2,1192 # 800154a8 <__BSS_END__+0xffffe878> -8000c904: 00048b93 mv s7,s1 -8000c908: 000c4783 lbu a5,0(s8) -8000c90c: 26078863 beqz a5,8000cb7c <_vfiprintf_r+0x374> -8000c910: 000c0413 mv s0,s8 -8000c914: 02500713 li a4,37 -8000c918: 42e78e63 beq a5,a4,8000cd54 <_vfiprintf_r+0x54c> -8000c91c: 00144783 lbu a5,1(s0) -8000c920: 00140413 addi s0,s0,1 -8000c924: fe079ae3 bnez a5,8000c918 <_vfiprintf_r+0x110> -8000c928: 41840cb3 sub s9,s0,s8 -8000c92c: 25840863 beq s0,s8,8000cb7c <_vfiprintf_r+0x374> -8000c930: 04812703 lw a4,72(sp) -8000c934: 04412783 lw a5,68(sp) -8000c938: 018ba023 sw s8,0(s7) -8000c93c: 00ec8733 add a4,s9,a4 -8000c940: 00178793 addi a5,a5,1 -8000c944: 019ba223 sw s9,4(s7) -8000c948: 04e12423 sw a4,72(sp) -8000c94c: 04f12223 sw a5,68(sp) -8000c950: 00700693 li a3,7 -8000c954: 008b8b93 addi s7,s7,8 -8000c958: 02f6d063 bge a3,a5,8000c978 <_vfiprintf_r+0x170> -8000c95c: 3a070ae3 beqz a4,8000d510 <_vfiprintf_r+0xd08> -8000c960: 04010613 addi a2,sp,64 -8000c964: 00098593 mv a1,s3 -8000c968: 000a0513 mv a0,s4 -8000c96c: d95ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000c970: 20051a63 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000c974: 00048b93 mv s7,s1 -8000c978: 00c12703 lw a4,12(sp) -8000c97c: 00044783 lbu a5,0(s0) -8000c980: 01970733 add a4,a4,s9 -8000c984: 00e12623 sw a4,12(sp) -8000c988: 1e078a63 beqz a5,8000cb7c <_vfiprintf_r+0x374> -8000c98c: 00144703 lbu a4,1(s0) -8000c990: 00140c13 addi s8,s0,1 -8000c994: 02010da3 sb zero,59(sp) -8000c998: fff00a93 li s5,-1 -8000c99c: 00012223 sw zero,4(sp) -8000c9a0: 00000b13 li s6,0 -8000c9a4: 05a00c93 li s9,90 -8000c9a8: 00900d13 li s10,9 -8000c9ac: 02a00613 li a2,42 -8000c9b0: 001c0c13 addi s8,s8,1 -8000c9b4: fe070793 addi a5,a4,-32 -8000c9b8: 04fce863 bltu s9,a5,8000ca08 <_vfiprintf_r+0x200> -8000c9bc: 01412683 lw a3,20(sp) -8000c9c0: 00279793 slli a5,a5,0x2 -8000c9c4: 00d787b3 add a5,a5,a3 -8000c9c8: 0007a783 lw a5,0(a5) -8000c9cc: 00078067 jr a5 -8000c9d0: 00012223 sw zero,4(sp) -8000c9d4: fd070793 addi a5,a4,-48 -8000c9d8: 00412583 lw a1,4(sp) -8000c9dc: 000c4703 lbu a4,0(s8) -8000c9e0: 001c0c13 addi s8,s8,1 -8000c9e4: 00259693 slli a3,a1,0x2 -8000c9e8: 00b686b3 add a3,a3,a1 -8000c9ec: 00169693 slli a3,a3,0x1 -8000c9f0: 00d787b3 add a5,a5,a3 -8000c9f4: 00f12223 sw a5,4(sp) -8000c9f8: fd070793 addi a5,a4,-48 -8000c9fc: fcfd7ee3 bgeu s10,a5,8000c9d8 <_vfiprintf_r+0x1d0> -8000ca00: fe070793 addi a5,a4,-32 -8000ca04: fafcfce3 bgeu s9,a5,8000c9bc <_vfiprintf_r+0x1b4> -8000ca08: 16070a63 beqz a4,8000cb7c <_vfiprintf_r+0x374> -8000ca0c: 08e10623 sb a4,140(sp) -8000ca10: 02010da3 sb zero,59(sp) -8000ca14: 00100c93 li s9,1 -8000ca18: 00100d13 li s10,1 -8000ca1c: 08c10413 addi s0,sp,140 -8000ca20: 00000a93 li s5,0 -8000ca24: 002b7f93 andi t6,s6,2 -8000ca28: 000f8463 beqz t6,8000ca30 <_vfiprintf_r+0x228> -8000ca2c: 002c8c93 addi s9,s9,2 -8000ca30: 04412703 lw a4,68(sp) -8000ca34: 084b7f13 andi t5,s6,132 -8000ca38: 04812783 lw a5,72(sp) -8000ca3c: 00170693 addi a3,a4,1 -8000ca40: 00068613 mv a2,a3 -8000ca44: 000f1863 bnez t5,8000ca54 <_vfiprintf_r+0x24c> -8000ca48: 00412583 lw a1,4(sp) -8000ca4c: 41958db3 sub s11,a1,s9 -8000ca50: 09b042e3 bgtz s11,8000d2d4 <_vfiprintf_r+0xacc> -8000ca54: 03b14583 lbu a1,59(sp) -8000ca58: 008b8693 addi a3,s7,8 -8000ca5c: 02058c63 beqz a1,8000ca94 <_vfiprintf_r+0x28c> -8000ca60: 03b10713 addi a4,sp,59 -8000ca64: 00178793 addi a5,a5,1 -8000ca68: 00eba023 sw a4,0(s7) -8000ca6c: 00100713 li a4,1 -8000ca70: 00eba223 sw a4,4(s7) -8000ca74: 04f12423 sw a5,72(sp) -8000ca78: 04c12223 sw a2,68(sp) -8000ca7c: 00700713 li a4,7 -8000ca80: 7ec74063 blt a4,a2,8000d260 <_vfiprintf_r+0xa58> -8000ca84: 00060713 mv a4,a2 -8000ca88: 00068b93 mv s7,a3 -8000ca8c: 00160613 addi a2,a2,1 -8000ca90: 00868693 addi a3,a3,8 -8000ca94: 040f8e63 beqz t6,8000caf0 <_vfiprintf_r+0x2e8> -8000ca98: 03c10713 addi a4,sp,60 -8000ca9c: 00278793 addi a5,a5,2 -8000caa0: 00eba023 sw a4,0(s7) -8000caa4: 00200713 li a4,2 -8000caa8: 00eba223 sw a4,4(s7) -8000caac: 04f12423 sw a5,72(sp) -8000cab0: 04c12223 sw a2,68(sp) -8000cab4: 00700713 li a4,7 -8000cab8: 00c750e3 bge a4,a2,8000d2b8 <_vfiprintf_r+0xab0> -8000cabc: 2a0784e3 beqz a5,8000d564 <_vfiprintf_r+0xd5c> -8000cac0: 04010613 addi a2,sp,64 -8000cac4: 00098593 mv a1,s3 -8000cac8: 000a0513 mv a0,s4 -8000cacc: 03e12423 sw t5,40(sp) -8000cad0: c31ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000cad4: 0a051863 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000cad8: 04412703 lw a4,68(sp) -8000cadc: 04812783 lw a5,72(sp) -8000cae0: 02812f03 lw t5,40(sp) -8000cae4: 05410693 addi a3,sp,84 -8000cae8: 00170613 addi a2,a4,1 -8000caec: 00048b93 mv s7,s1 -8000caf0: 08000593 li a1,128 -8000caf4: 5abf0663 beq t5,a1,8000d0a0 <_vfiprintf_r+0x898> -8000caf8: 41aa8ab3 sub s5,s5,s10 -8000cafc: 69504263 bgtz s5,8000d180 <_vfiprintf_r+0x978> -8000cb00: 00fd07b3 add a5,s10,a5 -8000cb04: 008ba023 sw s0,0(s7) -8000cb08: 01aba223 sw s10,4(s7) -8000cb0c: 04f12423 sw a5,72(sp) -8000cb10: 04c12223 sw a2,68(sp) -8000cb14: 00700713 li a4,7 -8000cb18: 02c75263 bge a4,a2,8000cb3c <_vfiprintf_r+0x334> -8000cb1c: 0a078ee3 beqz a5,8000d3d8 <_vfiprintf_r+0xbd0> -8000cb20: 04010613 addi a2,sp,64 -8000cb24: 00098593 mv a1,s3 -8000cb28: 000a0513 mv a0,s4 -8000cb2c: bd5ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000cb30: 04051a63 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000cb34: 04812783 lw a5,72(sp) -8000cb38: 00048693 mv a3,s1 -8000cb3c: 004b7313 andi t1,s6,4 -8000cb40: 00030863 beqz t1,8000cb50 <_vfiprintf_r+0x348> -8000cb44: 00412703 lw a4,4(sp) -8000cb48: 41970bb3 sub s7,a4,s9 -8000cb4c: 0b7044e3 bgtz s7,8000d3f4 <_vfiprintf_r+0xbec> -8000cb50: 00412403 lw s0,4(sp) -8000cb54: 01945463 bge s0,s9,8000cb5c <_vfiprintf_r+0x354> -8000cb58: 000c8413 mv s0,s9 -8000cb5c: 00c12703 lw a4,12(sp) -8000cb60: 00870733 add a4,a4,s0 -8000cb64: 00e12623 sw a4,12(sp) -8000cb68: 6c079863 bnez a5,8000d238 <_vfiprintf_r+0xa30> -8000cb6c: 000c4783 lbu a5,0(s8) -8000cb70: 04012223 sw zero,68(sp) -8000cb74: 00048b93 mv s7,s1 -8000cb78: d8079ce3 bnez a5,8000c910 <_vfiprintf_r+0x108> -8000cb7c: 04812783 lw a5,72(sp) -8000cb80: 64079ae3 bnez a5,8000d9d4 <_vfiprintf_r+0x11cc> -8000cb84: 00c9d783 lhu a5,12(s3) -8000cb88: 0407f793 andi a5,a5,64 -8000cb8c: 680792e3 bnez a5,8000da10 <_vfiprintf_r+0x1208> -8000cb90: 12c12083 lw ra,300(sp) -8000cb94: 12812403 lw s0,296(sp) -8000cb98: 00c12503 lw a0,12(sp) -8000cb9c: 12412483 lw s1,292(sp) -8000cba0: 12012903 lw s2,288(sp) -8000cba4: 11c12983 lw s3,284(sp) -8000cba8: 11812a03 lw s4,280(sp) -8000cbac: 11412a83 lw s5,276(sp) -8000cbb0: 11012b03 lw s6,272(sp) -8000cbb4: 10c12b83 lw s7,268(sp) -8000cbb8: 10812c03 lw s8,264(sp) -8000cbbc: 10412c83 lw s9,260(sp) -8000cbc0: 10012d03 lw s10,256(sp) -8000cbc4: 0fc12d83 lw s11,252(sp) -8000cbc8: 13010113 addi sp,sp,304 -8000cbcc: 00008067 ret -8000cbd0: 000a0513 mv a0,s4 -8000cbd4: e85fa0ef jal ra,80007a58 <_localeconv_r> -8000cbd8: 00452783 lw a5,4(a0) -8000cbdc: 00078513 mv a0,a5 -8000cbe0: 02f12023 sw a5,32(sp) -8000cbe4: fd5fc0ef jal ra,80009bb8 -8000cbe8: 00050793 mv a5,a0 -8000cbec: 000a0513 mv a0,s4 -8000cbf0: 00078413 mv s0,a5 -8000cbf4: 02f12223 sw a5,36(sp) -8000cbf8: e61fa0ef jal ra,80007a58 <_localeconv_r> -8000cbfc: 00852783 lw a5,8(a0) -8000cc00: 02a00613 li a2,42 -8000cc04: 00f12e23 sw a5,28(sp) -8000cc08: 2a0418e3 bnez s0,8000d6b8 <_vfiprintf_r+0xeb0> -8000cc0c: 000c4703 lbu a4,0(s8) -8000cc10: da1ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cc14: 000c4703 lbu a4,0(s8) -8000cc18: 020b6b13 ori s6,s6,32 -8000cc1c: d95ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cc20: 010b6b13 ori s6,s6,16 -8000cc24: 020b7793 andi a5,s6,32 -8000cc28: 16078463 beqz a5,8000cd90 <_vfiprintf_r+0x588> -8000cc2c: 01012783 lw a5,16(sp) -8000cc30: 00778793 addi a5,a5,7 -8000cc34: ff87f793 andi a5,a5,-8 -8000cc38: 0047a703 lw a4,4(a5) -8000cc3c: 0007ad03 lw s10,0(a5) -8000cc40: 00878793 addi a5,a5,8 -8000cc44: 00f12823 sw a5,16(sp) -8000cc48: 00070c93 mv s9,a4 -8000cc4c: 16074a63 bltz a4,8000cdc0 <_vfiprintf_r+0x5b8> -8000cc50: fff00713 li a4,-1 -8000cc54: 000b0d93 mv s11,s6 -8000cc58: 00ea8863 beq s5,a4,8000cc68 <_vfiprintf_r+0x460> -8000cc5c: 019d6733 or a4,s10,s9 -8000cc60: f7fb7d93 andi s11,s6,-129 -8000cc64: 0a070ce3 beqz a4,8000d51c <_vfiprintf_r+0xd14> -8000cc68: 160c96e3 bnez s9,8000d5d4 <_vfiprintf_r+0xdcc> -8000cc6c: 00900713 li a4,9 -8000cc70: 17a762e3 bltu a4,s10,8000d5d4 <_vfiprintf_r+0xdcc> -8000cc74: 030d0793 addi a5,s10,48 -8000cc78: 0ef107a3 sb a5,239(sp) -8000cc7c: 000d8b13 mv s6,s11 -8000cc80: 00100d13 li s10,1 -8000cc84: 0ef10413 addi s0,sp,239 -8000cc88: 000a8c93 mv s9,s5 -8000cc8c: 01aad463 bge s5,s10,8000cc94 <_vfiprintf_r+0x48c> -8000cc90: 000d0c93 mv s9,s10 -8000cc94: 03b14783 lbu a5,59(sp) -8000cc98: 00f037b3 snez a5,a5 -8000cc9c: 00fc8cb3 add s9,s9,a5 -8000cca0: d85ff06f j 8000ca24 <_vfiprintf_r+0x21c> -8000cca4: 00098593 mv a1,s3 -8000cca8: 000a0513 mv a0,s4 -8000ccac: b5cf70ef jal ra,80004008 <__swsetup_r> -8000ccb0: 560510e3 bnez a0,8000da10 <_vfiprintf_r+0x1208> -8000ccb4: 00c9d783 lhu a5,12(s3) -8000ccb8: 00a00713 li a4,10 -8000ccbc: 01a7f793 andi a5,a5,26 -8000ccc0: bee79ee3 bne a5,a4,8000c8bc <_vfiprintf_r+0xb4> -8000ccc4: 00e99783 lh a5,14(s3) -8000ccc8: be07cae3 bltz a5,8000c8bc <_vfiprintf_r+0xb4> -8000cccc: 01012683 lw a3,16(sp) -8000ccd0: 000b8613 mv a2,s7 -8000ccd4: 00098593 mv a1,s3 -8000ccd8: 000a0513 mv a0,s4 -8000ccdc: 589000ef jal ra,8000da64 <__sbprintf> -8000cce0: 00a12623 sw a0,12(sp) -8000cce4: eadff06f j 8000cb90 <_vfiprintf_r+0x388> -8000cce8: 010b6b13 ori s6,s6,16 -8000ccec: 020b7793 andi a5,s6,32 -8000ccf0: 06078a63 beqz a5,8000cd64 <_vfiprintf_r+0x55c> -8000ccf4: 01012783 lw a5,16(sp) -8000ccf8: 00778793 addi a5,a5,7 -8000ccfc: ff87f793 andi a5,a5,-8 -8000cd00: 0007ad03 lw s10,0(a5) -8000cd04: 0047ac83 lw s9,4(a5) -8000cd08: 00878793 addi a5,a5,8 -8000cd0c: 00f12823 sw a5,16(sp) -8000cd10: bffb7d93 andi s11,s6,-1025 -8000cd14: 00000713 li a4,0 -8000cd18: 02010da3 sb zero,59(sp) -8000cd1c: fff00693 li a3,-1 -8000cd20: 0cda8463 beq s5,a3,8000cde8 <_vfiprintf_r+0x5e0> -8000cd24: 019d66b3 or a3,s10,s9 -8000cd28: f7fdfb13 andi s6,s11,-129 -8000cd2c: 5a069063 bnez a3,8000d2cc <_vfiprintf_r+0xac4> -8000cd30: 300a9c63 bnez s5,8000d048 <_vfiprintf_r+0x840> -8000cd34: 7e071863 bnez a4,8000d524 <_vfiprintf_r+0xd1c> -8000cd38: 001dfd13 andi s10,s11,1 -8000cd3c: 0f010413 addi s0,sp,240 -8000cd40: f40d04e3 beqz s10,8000cc88 <_vfiprintf_r+0x480> -8000cd44: 03000793 li a5,48 -8000cd48: 0ef107a3 sb a5,239(sp) -8000cd4c: 0ef10413 addi s0,sp,239 -8000cd50: f39ff06f j 8000cc88 <_vfiprintf_r+0x480> -8000cd54: 41840cb3 sub s9,s0,s8 -8000cd58: bd841ce3 bne s0,s8,8000c930 <_vfiprintf_r+0x128> -8000cd5c: 00044783 lbu a5,0(s0) -8000cd60: c29ff06f j 8000c988 <_vfiprintf_r+0x180> -8000cd64: 01012683 lw a3,16(sp) -8000cd68: 010b7793 andi a5,s6,16 -8000cd6c: 00468713 addi a4,a3,4 -8000cd70: 16079ce3 bnez a5,8000d6e8 <_vfiprintf_r+0xee0> -8000cd74: 040b7793 andi a5,s6,64 -8000cd78: 380788e3 beqz a5,8000d908 <_vfiprintf_r+0x1100> -8000cd7c: 01012783 lw a5,16(sp) -8000cd80: 00000c93 li s9,0 -8000cd84: 00e12823 sw a4,16(sp) -8000cd88: 0007dd03 lhu s10,0(a5) -8000cd8c: f85ff06f j 8000cd10 <_vfiprintf_r+0x508> -8000cd90: 01012683 lw a3,16(sp) -8000cd94: 010b7793 andi a5,s6,16 -8000cd98: 00468713 addi a4,a3,4 -8000cd9c: 100794e3 bnez a5,8000d6a4 <_vfiprintf_r+0xe9c> -8000cda0: 040b7793 andi a5,s6,64 -8000cda4: 320782e3 beqz a5,8000d8c8 <_vfiprintf_r+0x10c0> -8000cda8: 01012783 lw a5,16(sp) -8000cdac: 00e12823 sw a4,16(sp) -8000cdb0: 00079d03 lh s10,0(a5) -8000cdb4: 41fd5c93 srai s9,s10,0x1f -8000cdb8: 000c8713 mv a4,s9 -8000cdbc: e8075ae3 bgez a4,8000cc50 <_vfiprintf_r+0x448> -8000cdc0: 01a03733 snez a4,s10 -8000cdc4: 41900eb3 neg t4,s9 -8000cdc8: 40ee8cb3 sub s9,t4,a4 -8000cdcc: 02d00713 li a4,45 -8000cdd0: 02e10da3 sb a4,59(sp) -8000cdd4: fff00693 li a3,-1 -8000cdd8: 41a00d33 neg s10,s10 -8000cddc: 000b0d93 mv s11,s6 -8000cde0: 00100713 li a4,1 -8000cde4: f4da90e3 bne s5,a3,8000cd24 <_vfiprintf_r+0x51c> -8000cde8: 00100693 li a3,1 -8000cdec: e6d70ee3 beq a4,a3,8000cc68 <_vfiprintf_r+0x460> -8000cdf0: 00200693 li a3,2 -8000cdf4: 26d70463 beq a4,a3,8000d05c <_vfiprintf_r+0x854> -8000cdf8: 0f010413 addi s0,sp,240 -8000cdfc: 01dc9793 slli a5,s9,0x1d -8000ce00: 007d7713 andi a4,s10,7 -8000ce04: 003d5d13 srli s10,s10,0x3 -8000ce08: 03070713 addi a4,a4,48 -8000ce0c: 01a7ed33 or s10,a5,s10 -8000ce10: 003cdc93 srli s9,s9,0x3 -8000ce14: fee40fa3 sb a4,-1(s0) -8000ce18: 019d67b3 or a5,s10,s9 -8000ce1c: 00040613 mv a2,s0 -8000ce20: fff40413 addi s0,s0,-1 -8000ce24: fc079ce3 bnez a5,8000cdfc <_vfiprintf_r+0x5f4> -8000ce28: 001df793 andi a5,s11,1 -8000ce2c: 26078263 beqz a5,8000d090 <_vfiprintf_r+0x888> -8000ce30: 03000793 li a5,48 -8000ce34: 24f70e63 beq a4,a5,8000d090 <_vfiprintf_r+0x888> -8000ce38: ffe60613 addi a2,a2,-2 -8000ce3c: fef40fa3 sb a5,-1(s0) -8000ce40: 0f010793 addi a5,sp,240 -8000ce44: 40c78d33 sub s10,a5,a2 -8000ce48: 000d8b13 mv s6,s11 -8000ce4c: 00060413 mv s0,a2 -8000ce50: e39ff06f j 8000cc88 <_vfiprintf_r+0x480> -8000ce54: ac1f70ef jal ra,80004914 <__sinit> -8000ce58: a05ff06f j 8000c85c <_vfiprintf_r+0x54> -8000ce5c: 01012783 lw a5,16(sp) -8000ce60: 02010da3 sb zero,59(sp) -8000ce64: 0007a403 lw s0,0(a5) -8000ce68: 00478d93 addi s11,a5,4 -8000ce6c: 220400e3 beqz s0,8000d88c <_vfiprintf_r+0x1084> -8000ce70: fff00793 li a5,-1 -8000ce74: 12fa88e3 beq s5,a5,8000d7a4 <_vfiprintf_r+0xf9c> -8000ce78: 000a8613 mv a2,s5 -8000ce7c: 00000593 li a1,0 -8000ce80: 00040513 mv a0,s0 -8000ce84: e74fb0ef jal ra,800084f8 -8000ce88: 360500e3 beqz a0,8000d9e8 <_vfiprintf_r+0x11e0> -8000ce8c: 40850d33 sub s10,a0,s0 -8000ce90: 01b12823 sw s11,16(sp) -8000ce94: 00000a93 li s5,0 -8000ce98: df1ff06f j 8000cc88 <_vfiprintf_r+0x480> -8000ce9c: 01012703 lw a4,16(sp) -8000cea0: 02010da3 sb zero,59(sp) -8000cea4: 00100c93 li s9,1 -8000cea8: 00072783 lw a5,0(a4) -8000ceac: 00470713 addi a4,a4,4 -8000ceb0: 00e12823 sw a4,16(sp) -8000ceb4: 08f10623 sb a5,140(sp) -8000ceb8: 00100d13 li s10,1 -8000cebc: 08c10413 addi s0,sp,140 -8000cec0: b61ff06f j 8000ca20 <_vfiprintf_r+0x218> -8000cec4: 01012783 lw a5,16(sp) -8000cec8: ffff8737 lui a4,0xffff8 -8000cecc: 83074713 xori a4,a4,-2000 -8000ced0: 0007ad03 lw s10,0(a5) -8000ced4: 00478793 addi a5,a5,4 -8000ced8: 00f12823 sw a5,16(sp) -8000cedc: 800157b7 lui a5,0x80015 -8000cee0: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -8000cee4: 02e11e23 sh a4,60(sp) -8000cee8: 00000c93 li s9,0 -8000ceec: 002b6d93 ori s11,s6,2 -8000cef0: 00f12c23 sw a5,24(sp) -8000cef4: 00200713 li a4,2 -8000cef8: e21ff06f j 8000cd18 <_vfiprintf_r+0x510> -8000cefc: 000c4703 lbu a4,0(s8) -8000cf00: 06c00793 li a5,108 -8000cf04: 16f706e3 beq a4,a5,8000d870 <_vfiprintf_r+0x1068> -8000cf08: 010b6b13 ori s6,s6,16 -8000cf0c: aa5ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cf10: 000c4703 lbu a4,0(s8) -8000cf14: 06800793 li a5,104 -8000cf18: 14f704e3 beq a4,a5,8000d860 <_vfiprintf_r+0x1058> -8000cf1c: 040b6b13 ori s6,s6,64 -8000cf20: a91ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cf24: 010b6d93 ori s11,s6,16 -8000cf28: 020df793 andi a5,s11,32 -8000cf2c: 60078463 beqz a5,8000d534 <_vfiprintf_r+0xd2c> -8000cf30: 01012783 lw a5,16(sp) -8000cf34: 00100713 li a4,1 -8000cf38: 00778793 addi a5,a5,7 -8000cf3c: ff87f793 andi a5,a5,-8 -8000cf40: 0007ad03 lw s10,0(a5) -8000cf44: 0047ac83 lw s9,4(a5) -8000cf48: 00878793 addi a5,a5,8 -8000cf4c: 00f12823 sw a5,16(sp) -8000cf50: dc9ff06f j 8000cd18 <_vfiprintf_r+0x510> -8000cf54: 000c4703 lbu a4,0(s8) -8000cf58: 080b6b13 ori s6,s6,128 -8000cf5c: a55ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cf60: 01012683 lw a3,16(sp) -8000cf64: 000c4703 lbu a4,0(s8) -8000cf68: 0006a783 lw a5,0(a3) -8000cf6c: 00468693 addi a3,a3,4 -8000cf70: 00d12823 sw a3,16(sp) -8000cf74: 00f12223 sw a5,4(sp) -8000cf78: a207dce3 bgez a5,8000c9b0 <_vfiprintf_r+0x1a8> -8000cf7c: 40f007b3 neg a5,a5 -8000cf80: 00f12223 sw a5,4(sp) -8000cf84: 004b6b13 ori s6,s6,4 -8000cf88: a29ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cf8c: 000c4703 lbu a4,0(s8) -8000cf90: 001b6b13 ori s6,s6,1 -8000cf94: a1dff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cf98: 03b14783 lbu a5,59(sp) -8000cf9c: 000c4703 lbu a4,0(s8) -8000cfa0: a00798e3 bnez a5,8000c9b0 <_vfiprintf_r+0x1a8> -8000cfa4: 02000793 li a5,32 -8000cfa8: 02f10da3 sb a5,59(sp) -8000cfac: a05ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cfb0: 000c4703 lbu a4,0(s8) -8000cfb4: 004b6b13 ori s6,s6,4 -8000cfb8: 9f9ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cfbc: 02b00793 li a5,43 -8000cfc0: 000c4703 lbu a4,0(s8) -8000cfc4: 02f10da3 sb a5,59(sp) -8000cfc8: 9e9ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000cfcc: 000c4703 lbu a4,0(s8) -8000cfd0: 001c0693 addi a3,s8,1 -8000cfd4: 24c70ae3 beq a4,a2,8000da28 <_vfiprintf_r+0x1220> -8000cfd8: fd070793 addi a5,a4,-48 # ffff7fd0 <__BSS_END__+0x7ffe13a0> -8000cfdc: 00068c13 mv s8,a3 -8000cfe0: 00000a93 li s5,0 -8000cfe4: 9cfd68e3 bltu s10,a5,8000c9b4 <_vfiprintf_r+0x1ac> -8000cfe8: 000c4703 lbu a4,0(s8) -8000cfec: 002a9693 slli a3,s5,0x2 -8000cff0: 01568ab3 add s5,a3,s5 -8000cff4: 001a9a93 slli s5,s5,0x1 -8000cff8: 00fa8ab3 add s5,s5,a5 -8000cffc: fd070793 addi a5,a4,-48 -8000d000: 001c0c13 addi s8,s8,1 -8000d004: fefd72e3 bgeu s10,a5,8000cfe8 <_vfiprintf_r+0x7e0> -8000d008: 9adff06f j 8000c9b4 <_vfiprintf_r+0x1ac> -8000d00c: 01012683 lw a3,16(sp) -8000d010: 020b7793 andi a5,s6,32 -8000d014: 0006a703 lw a4,0(a3) -8000d018: 00468693 addi a3,a3,4 -8000d01c: 00d12823 sw a3,16(sp) -8000d020: 6a079a63 bnez a5,8000d6d4 <_vfiprintf_r+0xecc> -8000d024: 010b7793 andi a5,s6,16 -8000d028: 04079ce3 bnez a5,8000d880 <_vfiprintf_r+0x1078> -8000d02c: 040b7793 andi a5,s6,64 -8000d030: 140790e3 bnez a5,8000d970 <_vfiprintf_r+0x1168> -8000d034: 200b7313 andi t1,s6,512 -8000d038: 040304e3 beqz t1,8000d880 <_vfiprintf_r+0x1078> -8000d03c: 00c12783 lw a5,12(sp) -8000d040: 00f70023 sb a5,0(a4) -8000d044: 8c5ff06f j 8000c908 <_vfiprintf_r+0x100> -8000d048: 00100693 li a3,1 -8000d04c: 1ad70ee3 beq a4,a3,8000da08 <_vfiprintf_r+0x1200> -8000d050: 00200693 li a3,2 -8000d054: 000b0d93 mv s11,s6 -8000d058: dad710e3 bne a4,a3,8000cdf8 <_vfiprintf_r+0x5f0> -8000d05c: 01812683 lw a3,24(sp) -8000d060: 0f010413 addi s0,sp,240 -8000d064: 00fd7793 andi a5,s10,15 -8000d068: 00f687b3 add a5,a3,a5 -8000d06c: 0007c703 lbu a4,0(a5) -8000d070: 004d5d13 srli s10,s10,0x4 -8000d074: 01cc9793 slli a5,s9,0x1c -8000d078: 01a7ed33 or s10,a5,s10 -8000d07c: 004cdc93 srli s9,s9,0x4 -8000d080: fee40fa3 sb a4,-1(s0) -8000d084: 019d67b3 or a5,s10,s9 -8000d088: fff40413 addi s0,s0,-1 -8000d08c: fc079ce3 bnez a5,8000d064 <_vfiprintf_r+0x85c> -8000d090: 0f010793 addi a5,sp,240 -8000d094: 40878d33 sub s10,a5,s0 -8000d098: 000d8b13 mv s6,s11 -8000d09c: bedff06f j 8000cc88 <_vfiprintf_r+0x480> -8000d0a0: 00412583 lw a1,4(sp) -8000d0a4: 41958db3 sub s11,a1,s9 -8000d0a8: a5b058e3 blez s11,8000caf8 <_vfiprintf_r+0x2f0> -8000d0ac: 01000593 li a1,16 -8000d0b0: 17b5d6e3 bge a1,s11,8000da1c <_vfiprintf_r+0x1214> -8000d0b4: 01000e93 li t4,16 -8000d0b8: 00700f13 li t5,7 -8000d0bc: 0180006f j 8000d0d4 <_vfiprintf_r+0x8cc> -8000d0c0: 00270613 addi a2,a4,2 -8000d0c4: 008b8b93 addi s7,s7,8 -8000d0c8: 00068713 mv a4,a3 -8000d0cc: ff0d8d93 addi s11,s11,-16 -8000d0d0: 05bedc63 bge t4,s11,8000d128 <_vfiprintf_r+0x920> -8000d0d4: 01078793 addi a5,a5,16 -8000d0d8: 00170693 addi a3,a4,1 -8000d0dc: 012ba023 sw s2,0(s7) -8000d0e0: 01dba223 sw t4,4(s7) -8000d0e4: 04f12423 sw a5,72(sp) -8000d0e8: 04d12223 sw a3,68(sp) -8000d0ec: fcdf5ae3 bge t5,a3,8000d0c0 <_vfiprintf_r+0x8b8> -8000d0f0: 16078063 beqz a5,8000d250 <_vfiprintf_r+0xa48> -8000d0f4: 04010613 addi a2,sp,64 -8000d0f8: 00098593 mv a1,s3 -8000d0fc: 000a0513 mv a0,s4 -8000d100: e00ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d104: a80510e3 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000d108: 04412703 lw a4,68(sp) -8000d10c: 01000e93 li t4,16 -8000d110: ff0d8d93 addi s11,s11,-16 -8000d114: 04812783 lw a5,72(sp) -8000d118: 00048b93 mv s7,s1 -8000d11c: 00170613 addi a2,a4,1 -8000d120: 00700f13 li t5,7 -8000d124: fbbec8e3 blt t4,s11,8000d0d4 <_vfiprintf_r+0x8cc> -8000d128: 00060593 mv a1,a2 -8000d12c: 008b8513 addi a0,s7,8 -8000d130: 01b787b3 add a5,a5,s11 -8000d134: 012ba023 sw s2,0(s7) -8000d138: 01bba223 sw s11,4(s7) -8000d13c: 04f12423 sw a5,72(sp) -8000d140: 04b12223 sw a1,68(sp) -8000d144: 00700713 li a4,7 -8000d148: 52b75a63 bge a4,a1,8000d67c <_vfiprintf_r+0xe74> -8000d14c: 7e078663 beqz a5,8000d938 <_vfiprintf_r+0x1130> -8000d150: 04010613 addi a2,sp,64 -8000d154: 00098593 mv a1,s3 -8000d158: 000a0513 mv a0,s4 -8000d15c: da4ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d160: a20512e3 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000d164: 04412703 lw a4,68(sp) -8000d168: 41aa8ab3 sub s5,s5,s10 -8000d16c: 04812783 lw a5,72(sp) -8000d170: 05410693 addi a3,sp,84 -8000d174: 00170613 addi a2,a4,1 -8000d178: 00048b93 mv s7,s1 -8000d17c: 995052e3 blez s5,8000cb00 <_vfiprintf_r+0x2f8> -8000d180: 01000593 li a1,16 -8000d184: 7b55d063 bge a1,s5,8000d924 <_vfiprintf_r+0x111c> -8000d188: 01000893 li a7,16 -8000d18c: 00700d93 li s11,7 -8000d190: 0180006f j 8000d1a8 <_vfiprintf_r+0x9a0> -8000d194: 00270613 addi a2,a4,2 -8000d198: 008b8b93 addi s7,s7,8 -8000d19c: 00068713 mv a4,a3 -8000d1a0: ff0a8a93 addi s5,s5,-16 -8000d1a4: 0558da63 bge a7,s5,8000d1f8 <_vfiprintf_r+0x9f0> -8000d1a8: 01078793 addi a5,a5,16 -8000d1ac: 00170693 addi a3,a4,1 -8000d1b0: 012ba023 sw s2,0(s7) -8000d1b4: 011ba223 sw a7,4(s7) -8000d1b8: 04f12423 sw a5,72(sp) -8000d1bc: 04d12223 sw a3,68(sp) -8000d1c0: fcdddae3 bge s11,a3,8000d194 <_vfiprintf_r+0x98c> -8000d1c4: 06078263 beqz a5,8000d228 <_vfiprintf_r+0xa20> -8000d1c8: 04010613 addi a2,sp,64 -8000d1cc: 00098593 mv a1,s3 -8000d1d0: 000a0513 mv a0,s4 -8000d1d4: d2cff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d1d8: 9a0516e3 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000d1dc: 04412703 lw a4,68(sp) -8000d1e0: 01000893 li a7,16 -8000d1e4: ff0a8a93 addi s5,s5,-16 -8000d1e8: 04812783 lw a5,72(sp) -8000d1ec: 00048b93 mv s7,s1 -8000d1f0: 00170613 addi a2,a4,1 -8000d1f4: fb58cae3 blt a7,s5,8000d1a8 <_vfiprintf_r+0x9a0> -8000d1f8: 008b8593 addi a1,s7,8 -8000d1fc: 015787b3 add a5,a5,s5 -8000d200: 012ba023 sw s2,0(s7) -8000d204: 015ba223 sw s5,4(s7) -8000d208: 04f12423 sw a5,72(sp) -8000d20c: 04c12223 sw a2,68(sp) -8000d210: 00700713 li a4,7 -8000d214: 2cc74663 blt a4,a2,8000d4e0 <_vfiprintf_r+0xcd8> -8000d218: 00160613 addi a2,a2,1 -8000d21c: 00858693 addi a3,a1,8 -8000d220: 00058b93 mv s7,a1 -8000d224: 8ddff06f j 8000cb00 <_vfiprintf_r+0x2f8> -8000d228: 00100613 li a2,1 -8000d22c: 00000713 li a4,0 -8000d230: 00048b93 mv s7,s1 -8000d234: f6dff06f j 8000d1a0 <_vfiprintf_r+0x998> -8000d238: 04010613 addi a2,sp,64 -8000d23c: 00098593 mv a1,s3 -8000d240: 000a0513 mv a0,s4 -8000d244: cbcff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d248: 920502e3 beqz a0,8000cb6c <_vfiprintf_r+0x364> -8000d24c: 939ff06f j 8000cb84 <_vfiprintf_r+0x37c> -8000d250: 00100613 li a2,1 -8000d254: 00000713 li a4,0 -8000d258: 00048b93 mv s7,s1 -8000d25c: e71ff06f j 8000d0cc <_vfiprintf_r+0x8c4> -8000d260: 30078c63 beqz a5,8000d578 <_vfiprintf_r+0xd70> -8000d264: 04010613 addi a2,sp,64 -8000d268: 00098593 mv a1,s3 -8000d26c: 000a0513 mv a0,s4 -8000d270: 03e12623 sw t5,44(sp) -8000d274: 03f12423 sw t6,40(sp) -8000d278: c88ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d27c: 900514e3 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000d280: 04412703 lw a4,68(sp) -8000d284: 04812783 lw a5,72(sp) -8000d288: 02c12f03 lw t5,44(sp) -8000d28c: 02812f83 lw t6,40(sp) -8000d290: 05410693 addi a3,sp,84 -8000d294: 00170613 addi a2,a4,1 -8000d298: 00048b93 mv s7,s1 -8000d29c: ff8ff06f j 8000ca94 <_vfiprintf_r+0x28c> -8000d2a0: 03c10793 addi a5,sp,60 -8000d2a4: 04f12623 sw a5,76(sp) -8000d2a8: 00200793 li a5,2 -8000d2ac: 04f12823 sw a5,80(sp) -8000d2b0: 00100613 li a2,1 -8000d2b4: 05410693 addi a3,sp,84 -8000d2b8: 00060713 mv a4,a2 -8000d2bc: 00068b93 mv s7,a3 -8000d2c0: 00170613 addi a2,a4,1 -8000d2c4: 008b8693 addi a3,s7,8 -8000d2c8: 829ff06f j 8000caf0 <_vfiprintf_r+0x2e8> -8000d2cc: 000b0d93 mv s11,s6 -8000d2d0: b19ff06f j 8000cde8 <_vfiprintf_r+0x5e0> -8000d2d4: 01000613 li a2,16 -8000d2d8: 73b65063 bge a2,s11,8000d9f8 <_vfiprintf_r+0x11f0> -8000d2dc: 000b8613 mv a2,s7 -8000d2e0: 01000e93 li t4,16 -8000d2e4: 00040b93 mv s7,s0 -8000d2e8: 00700293 li t0,7 -8000d2ec: 00098413 mv s0,s3 -8000d2f0: 03f12423 sw t6,40(sp) -8000d2f4: 000d8993 mv s3,s11 -8000d2f8: 000c0d93 mv s11,s8 -8000d2fc: 000a8c13 mv s8,s5 -8000d300: 000f0a93 mv s5,t5 -8000d304: 01c0006f j 8000d320 <_vfiprintf_r+0xb18> -8000d308: 00270513 addi a0,a4,2 -8000d30c: 00860613 addi a2,a2,8 -8000d310: 00068713 mv a4,a3 -8000d314: ff098993 addi s3,s3,-16 -8000d318: 053ede63 bge t4,s3,8000d374 <_vfiprintf_r+0xb6c> -8000d31c: 00170693 addi a3,a4,1 -8000d320: 00812583 lw a1,8(sp) -8000d324: 01078793 addi a5,a5,16 -8000d328: 01d62223 sw t4,4(a2) -8000d32c: 00b62023 sw a1,0(a2) -8000d330: 04f12423 sw a5,72(sp) -8000d334: 04d12223 sw a3,68(sp) -8000d338: fcd2d8e3 bge t0,a3,8000d308 <_vfiprintf_r+0xb00> -8000d33c: 08078663 beqz a5,8000d3c8 <_vfiprintf_r+0xbc0> -8000d340: 04010613 addi a2,sp,64 -8000d344: 00040593 mv a1,s0 -8000d348: 000a0513 mv a0,s4 -8000d34c: bb4ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d350: 4c051663 bnez a0,8000d81c <_vfiprintf_r+0x1014> -8000d354: 04412703 lw a4,68(sp) -8000d358: 01000e93 li t4,16 -8000d35c: ff098993 addi s3,s3,-16 -8000d360: 04812783 lw a5,72(sp) -8000d364: 00048613 mv a2,s1 -8000d368: 00170513 addi a0,a4,1 -8000d36c: 00700293 li t0,7 -8000d370: fb3ec6e3 blt t4,s3,8000d31c <_vfiprintf_r+0xb14> -8000d374: 02812f83 lw t6,40(sp) -8000d378: 000a8f13 mv t5,s5 -8000d37c: 00050593 mv a1,a0 -8000d380: 000c0a93 mv s5,s8 -8000d384: 000d8c13 mv s8,s11 -8000d388: 00098d93 mv s11,s3 -8000d38c: 00040993 mv s3,s0 -8000d390: 000b8413 mv s0,s7 -8000d394: 00060b93 mv s7,a2 -8000d398: 00812703 lw a4,8(sp) -8000d39c: 01b787b3 add a5,a5,s11 -8000d3a0: 01bba223 sw s11,4(s7) -8000d3a4: 00eba023 sw a4,0(s7) -8000d3a8: 04f12423 sw a5,72(sp) -8000d3ac: 04b12223 sw a1,68(sp) -8000d3b0: 00700713 li a4,7 -8000d3b4: 1eb74263 blt a4,a1,8000d598 <_vfiprintf_r+0xd90> -8000d3b8: 008b8b93 addi s7,s7,8 -8000d3bc: 00158613 addi a2,a1,1 -8000d3c0: 00058713 mv a4,a1 -8000d3c4: e90ff06f j 8000ca54 <_vfiprintf_r+0x24c> -8000d3c8: 00000713 li a4,0 -8000d3cc: 00100513 li a0,1 -8000d3d0: 00048613 mv a2,s1 -8000d3d4: f41ff06f j 8000d314 <_vfiprintf_r+0xb0c> -8000d3d8: 04012223 sw zero,68(sp) -8000d3dc: 004b7313 andi t1,s6,4 -8000d3e0: 0e030263 beqz t1,8000d4c4 <_vfiprintf_r+0xcbc> -8000d3e4: 00412703 lw a4,4(sp) -8000d3e8: 41970bb3 sub s7,a4,s9 -8000d3ec: 0d705c63 blez s7,8000d4c4 <_vfiprintf_r+0xcbc> -8000d3f0: 00048693 mv a3,s1 -8000d3f4: 01000713 li a4,16 -8000d3f8: 04412603 lw a2,68(sp) -8000d3fc: 61775263 bge a4,s7,8000da00 <_vfiprintf_r+0x11f8> -8000d400: 01000d13 li s10,16 -8000d404: 00700d93 li s11,7 -8000d408: 0180006f j 8000d420 <_vfiprintf_r+0xc18> -8000d40c: 00260513 addi a0,a2,2 -8000d410: 00868693 addi a3,a3,8 -8000d414: 00070613 mv a2,a4 -8000d418: ff0b8b93 addi s7,s7,-16 -8000d41c: 057d5a63 bge s10,s7,8000d470 <_vfiprintf_r+0xc68> -8000d420: 00812583 lw a1,8(sp) -8000d424: 01078793 addi a5,a5,16 -8000d428: 00160713 addi a4,a2,1 -8000d42c: 00b6a023 sw a1,0(a3) -8000d430: 01a6a223 sw s10,4(a3) -8000d434: 04f12423 sw a5,72(sp) -8000d438: 04e12223 sw a4,68(sp) -8000d43c: fcedd8e3 bge s11,a4,8000d40c <_vfiprintf_r+0xc04> -8000d440: 06078a63 beqz a5,8000d4b4 <_vfiprintf_r+0xcac> -8000d444: 04010613 addi a2,sp,64 -8000d448: 00098593 mv a1,s3 -8000d44c: 000a0513 mv a0,s4 -8000d450: ab0ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d454: f2051863 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000d458: 04412603 lw a2,68(sp) -8000d45c: ff0b8b93 addi s7,s7,-16 -8000d460: 04812783 lw a5,72(sp) -8000d464: 00048693 mv a3,s1 -8000d468: 00160513 addi a0,a2,1 -8000d46c: fb7d4ae3 blt s10,s7,8000d420 <_vfiprintf_r+0xc18> -8000d470: 00050593 mv a1,a0 -8000d474: 00812703 lw a4,8(sp) -8000d478: 017787b3 add a5,a5,s7 -8000d47c: 0176a223 sw s7,4(a3) -8000d480: 00e6a023 sw a4,0(a3) -8000d484: 04f12423 sw a5,72(sp) -8000d488: 04b12223 sw a1,68(sp) -8000d48c: 00700713 li a4,7 -8000d490: ecb75063 bge a4,a1,8000cb50 <_vfiprintf_r+0x348> -8000d494: 02078863 beqz a5,8000d4c4 <_vfiprintf_r+0xcbc> -8000d498: 04010613 addi a2,sp,64 -8000d49c: 00098593 mv a1,s3 -8000d4a0: 000a0513 mv a0,s4 -8000d4a4: a5cff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d4a8: ec051e63 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000d4ac: 04812783 lw a5,72(sp) -8000d4b0: ea0ff06f j 8000cb50 <_vfiprintf_r+0x348> -8000d4b4: 00100513 li a0,1 -8000d4b8: 00000613 li a2,0 -8000d4bc: 00048693 mv a3,s1 -8000d4c0: f59ff06f j 8000d418 <_vfiprintf_r+0xc10> -8000d4c4: 00412403 lw s0,4(sp) -8000d4c8: 01945463 bge s0,s9,8000d4d0 <_vfiprintf_r+0xcc8> -8000d4cc: 000c8413 mv s0,s9 -8000d4d0: 00c12783 lw a5,12(sp) -8000d4d4: 008787b3 add a5,a5,s0 -8000d4d8: 00f12623 sw a5,12(sp) -8000d4dc: e90ff06f j 8000cb6c <_vfiprintf_r+0x364> -8000d4e0: 34078263 beqz a5,8000d824 <_vfiprintf_r+0x101c> -8000d4e4: 04010613 addi a2,sp,64 -8000d4e8: 00098593 mv a1,s3 -8000d4ec: 000a0513 mv a0,s4 -8000d4f0: a10ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d4f4: e8051863 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000d4f8: 04412603 lw a2,68(sp) -8000d4fc: 04812783 lw a5,72(sp) -8000d500: 05410693 addi a3,sp,84 -8000d504: 00160613 addi a2,a2,1 -8000d508: 00048b93 mv s7,s1 -8000d50c: df4ff06f j 8000cb00 <_vfiprintf_r+0x2f8> -8000d510: 04012223 sw zero,68(sp) -8000d514: 00048b93 mv s7,s1 -8000d518: c60ff06f j 8000c978 <_vfiprintf_r+0x170> -8000d51c: f40a9c63 bnez s5,8000cc74 <_vfiprintf_r+0x46c> -8000d520: 000d8b13 mv s6,s11 -8000d524: 00000a93 li s5,0 -8000d528: 00000d13 li s10,0 -8000d52c: 0f010413 addi s0,sp,240 -8000d530: f58ff06f j 8000cc88 <_vfiprintf_r+0x480> -8000d534: 01012683 lw a3,16(sp) -8000d538: 010df793 andi a5,s11,16 -8000d53c: 00468713 addi a4,a3,4 -8000d540: 14079863 bnez a5,8000d690 <_vfiprintf_r+0xe88> -8000d544: 040df793 andi a5,s11,64 -8000d548: 3a078063 beqz a5,8000d8e8 <_vfiprintf_r+0x10e0> -8000d54c: 01012783 lw a5,16(sp) -8000d550: 00000c93 li s9,0 -8000d554: 00e12823 sw a4,16(sp) -8000d558: 0007dd03 lhu s10,0(a5) -8000d55c: 00100713 li a4,1 -8000d560: fb8ff06f j 8000cd18 <_vfiprintf_r+0x510> -8000d564: 05410693 addi a3,sp,84 -8000d568: 00100613 li a2,1 -8000d56c: 00000713 li a4,0 -8000d570: 00048b93 mv s7,s1 -8000d574: d7cff06f j 8000caf0 <_vfiprintf_r+0x2e8> -8000d578: 180f8063 beqz t6,8000d6f8 <_vfiprintf_r+0xef0> -8000d57c: 03c10793 addi a5,sp,60 -8000d580: 04f12623 sw a5,76(sp) -8000d584: 00200793 li a5,2 -8000d588: 04f12823 sw a5,80(sp) -8000d58c: 00100713 li a4,1 -8000d590: 05410b93 addi s7,sp,84 -8000d594: d2dff06f j 8000d2c0 <_vfiprintf_r+0xab8> -8000d598: 22078263 beqz a5,8000d7bc <_vfiprintf_r+0xfb4> -8000d59c: 04010613 addi a2,sp,64 -8000d5a0: 00098593 mv a1,s3 -8000d5a4: 000a0513 mv a0,s4 -8000d5a8: 03e12623 sw t5,44(sp) -8000d5ac: 03f12423 sw t6,40(sp) -8000d5b0: 950ff0ef jal ra,8000c700 <__sprint_r.part.0> -8000d5b4: dc051863 bnez a0,8000cb84 <_vfiprintf_r+0x37c> -8000d5b8: 04412703 lw a4,68(sp) -8000d5bc: 04812783 lw a5,72(sp) -8000d5c0: 02c12f03 lw t5,44(sp) -8000d5c4: 02812f83 lw t6,40(sp) -8000d5c8: 00048b93 mv s7,s1 -8000d5cc: 00170613 addi a2,a4,1 -8000d5d0: c84ff06f j 8000ca54 <_vfiprintf_r+0x24c> -8000d5d4: 400df793 andi a5,s11,1024 -8000d5d8: 03412423 sw s4,40(sp) -8000d5dc: 03312623 sw s3,44(sp) -8000d5e0: 000c8a13 mv s4,s9 -8000d5e4: 000d0993 mv s3,s10 -8000d5e8: 00000b13 li s6,0 -8000d5ec: 01c12d03 lw s10,28(sp) -8000d5f0: 0f010413 addi s0,sp,240 -8000d5f4: 00078c93 mv s9,a5 -8000d5f8: 0240006f j 8000d61c <_vfiprintf_r+0xe14> -8000d5fc: 00a00613 li a2,10 -8000d600: 00000693 li a3,0 -8000d604: 00098513 mv a0,s3 -8000d608: 000a0593 mv a1,s4 -8000d60c: 5f5020ef jal ra,80010400 <__udivdi3> -8000d610: 300a0e63 beqz s4,8000d92c <_vfiprintf_r+0x1124> -8000d614: 00050993 mv s3,a0 -8000d618: 00058a13 mv s4,a1 -8000d61c: 00a00613 li a2,10 -8000d620: 00000693 li a3,0 -8000d624: 00098513 mv a0,s3 -8000d628: 000a0593 mv a1,s4 -8000d62c: 208030ef jal ra,80010834 <__umoddi3> -8000d630: 03050513 addi a0,a0,48 -8000d634: fea40fa3 sb a0,-1(s0) -8000d638: 001b0b13 addi s6,s6,1 -8000d63c: fff40413 addi s0,s0,-1 -8000d640: fa0c8ee3 beqz s9,8000d5fc <_vfiprintf_r+0xdf4> -8000d644: 000d4683 lbu a3,0(s10) -8000d648: fb669ae3 bne a3,s6,8000d5fc <_vfiprintf_r+0xdf4> -8000d64c: 0ff00793 li a5,255 -8000d650: fafb06e3 beq s6,a5,8000d5fc <_vfiprintf_r+0xdf4> -8000d654: 180a1463 bnez s4,8000d7dc <_vfiprintf_r+0xfd4> -8000d658: 00900793 li a5,9 -8000d65c: 1937e063 bltu a5,s3,8000d7dc <_vfiprintf_r+0xfd4> -8000d660: 0f010793 addi a5,sp,240 -8000d664: 01a12e23 sw s10,28(sp) -8000d668: 02812a03 lw s4,40(sp) -8000d66c: 02c12983 lw s3,44(sp) -8000d670: 40878d33 sub s10,a5,s0 -8000d674: 000d8b13 mv s6,s11 -8000d678: e10ff06f j 8000cc88 <_vfiprintf_r+0x480> -8000d67c: 00158613 addi a2,a1,1 -8000d680: 00850693 addi a3,a0,8 -8000d684: 00058713 mv a4,a1 -8000d688: 00050b93 mv s7,a0 -8000d68c: c6cff06f j 8000caf8 <_vfiprintf_r+0x2f0> -8000d690: 00e12823 sw a4,16(sp) -8000d694: 0006ad03 lw s10,0(a3) -8000d698: 00000c93 li s9,0 -8000d69c: 00100713 li a4,1 -8000d6a0: e78ff06f j 8000cd18 <_vfiprintf_r+0x510> -8000d6a4: 0006ad03 lw s10,0(a3) -8000d6a8: 00e12823 sw a4,16(sp) -8000d6ac: 41fd5c93 srai s9,s10,0x1f -8000d6b0: 000c8713 mv a4,s9 -8000d6b4: d98ff06f j 8000cc4c <_vfiprintf_r+0x444> -8000d6b8: 01c12783 lw a5,28(sp) -8000d6bc: 000c4703 lbu a4,0(s8) -8000d6c0: ae078863 beqz a5,8000c9b0 <_vfiprintf_r+0x1a8> -8000d6c4: 0007c783 lbu a5,0(a5) -8000d6c8: ae078463 beqz a5,8000c9b0 <_vfiprintf_r+0x1a8> -8000d6cc: 400b6b13 ori s6,s6,1024 -8000d6d0: ae0ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000d6d4: 00c12683 lw a3,12(sp) -8000d6d8: 41f6d793 srai a5,a3,0x1f -8000d6dc: 00d72023 sw a3,0(a4) -8000d6e0: 00f72223 sw a5,4(a4) -8000d6e4: a24ff06f j 8000c908 <_vfiprintf_r+0x100> -8000d6e8: 0006ad03 lw s10,0(a3) -8000d6ec: 00000c93 li s9,0 -8000d6f0: 00e12823 sw a4,16(sp) -8000d6f4: e1cff06f j 8000cd10 <_vfiprintf_r+0x508> -8000d6f8: 00000713 li a4,0 -8000d6fc: 05410693 addi a3,sp,84 -8000d700: 00100613 li a2,1 -8000d704: 00048b93 mv s7,s1 -8000d708: be8ff06f j 8000caf0 <_vfiprintf_r+0x2e8> -8000d70c: 000b0d93 mv s11,s6 -8000d710: 819ff06f j 8000cf28 <_vfiprintf_r+0x720> -8000d714: 800157b7 lui a5,0x80015 -8000d718: c4078793 addi a5,a5,-960 # 80014c40 <__BSS_END__+0xffffe010> -8000d71c: 00f12c23 sw a5,24(sp) -8000d720: 020b7793 andi a5,s6,32 -8000d724: 06078063 beqz a5,8000d784 <_vfiprintf_r+0xf7c> -8000d728: 01012783 lw a5,16(sp) -8000d72c: 00778793 addi a5,a5,7 -8000d730: ff87f793 andi a5,a5,-8 -8000d734: 0007ad03 lw s10,0(a5) -8000d738: 0047ac83 lw s9,4(a5) -8000d73c: 00878793 addi a5,a5,8 -8000d740: 00f12823 sw a5,16(sp) -8000d744: 001b7693 andi a3,s6,1 -8000d748: 00068e63 beqz a3,8000d764 <_vfiprintf_r+0xf5c> -8000d74c: 019d66b3 or a3,s10,s9 -8000d750: 00068a63 beqz a3,8000d764 <_vfiprintf_r+0xf5c> -8000d754: 03000693 li a3,48 -8000d758: 02d10e23 sb a3,60(sp) -8000d75c: 02e10ea3 sb a4,61(sp) -8000d760: 002b6b13 ori s6,s6,2 -8000d764: bffb7d93 andi s11,s6,-1025 -8000d768: 00200713 li a4,2 -8000d76c: dacff06f j 8000cd18 <_vfiprintf_r+0x510> -8000d770: 800157b7 lui a5,0x80015 -8000d774: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -8000d778: 00f12c23 sw a5,24(sp) -8000d77c: 020b7793 andi a5,s6,32 -8000d780: fa0794e3 bnez a5,8000d728 <_vfiprintf_r+0xf20> -8000d784: 01012603 lw a2,16(sp) -8000d788: 010b7793 andi a5,s6,16 -8000d78c: 00460693 addi a3,a2,4 -8000d790: 0a078a63 beqz a5,8000d844 <_vfiprintf_r+0x103c> -8000d794: 00062d03 lw s10,0(a2) -8000d798: 00000c93 li s9,0 -8000d79c: 00d12823 sw a3,16(sp) -8000d7a0: fa5ff06f j 8000d744 <_vfiprintf_r+0xf3c> -8000d7a4: 00040513 mv a0,s0 -8000d7a8: c10fc0ef jal ra,80009bb8 -8000d7ac: 00050d13 mv s10,a0 -8000d7b0: 01b12823 sw s11,16(sp) -8000d7b4: 00000a93 li s5,0 -8000d7b8: cd0ff06f j 8000cc88 <_vfiprintf_r+0x480> -8000d7bc: 03b14703 lbu a4,59(sp) -8000d7c0: 18071a63 bnez a4,8000d954 <_vfiprintf_r+0x114c> -8000d7c4: ac0f9ee3 bnez t6,8000d2a0 <_vfiprintf_r+0xa98> -8000d7c8: 00000713 li a4,0 -8000d7cc: 00100613 li a2,1 -8000d7d0: 05410693 addi a3,sp,84 -8000d7d4: 00048b93 mv s7,s1 -8000d7d8: b18ff06f j 8000caf0 <_vfiprintf_r+0x2e8> -8000d7dc: 02412783 lw a5,36(sp) -8000d7e0: 02012583 lw a1,32(sp) -8000d7e4: 00000b13 li s6,0 -8000d7e8: 40f40433 sub s0,s0,a5 -8000d7ec: 00078613 mv a2,a5 -8000d7f0: 00040513 mv a0,s0 -8000d7f4: c50fc0ef jal ra,80009c44 -8000d7f8: 001d4583 lbu a1,1(s10) -8000d7fc: 00a00613 li a2,10 -8000d800: 00000693 li a3,0 -8000d804: 00b03733 snez a4,a1 -8000d808: 00098513 mv a0,s3 -8000d80c: 000a0593 mv a1,s4 -8000d810: 00ed0d33 add s10,s10,a4 -8000d814: 3ed020ef jal ra,80010400 <__udivdi3> -8000d818: dfdff06f j 8000d614 <_vfiprintf_r+0xe0c> -8000d81c: 00040993 mv s3,s0 -8000d820: b64ff06f j 8000cb84 <_vfiprintf_r+0x37c> -8000d824: 00100713 li a4,1 -8000d828: 000d0793 mv a5,s10 -8000d82c: 04812623 sw s0,76(sp) -8000d830: 05a12823 sw s10,80(sp) -8000d834: 05a12423 sw s10,72(sp) -8000d838: 04e12223 sw a4,68(sp) -8000d83c: 05410693 addi a3,sp,84 -8000d840: afcff06f j 8000cb3c <_vfiprintf_r+0x334> -8000d844: 040b7793 andi a5,s6,64 -8000d848: 06078263 beqz a5,8000d8ac <_vfiprintf_r+0x10a4> -8000d84c: 01012783 lw a5,16(sp) -8000d850: 00000c93 li s9,0 -8000d854: 00d12823 sw a3,16(sp) -8000d858: 0007dd03 lhu s10,0(a5) -8000d85c: ee9ff06f j 8000d744 <_vfiprintf_r+0xf3c> -8000d860: 001c4703 lbu a4,1(s8) -8000d864: 200b6b13 ori s6,s6,512 -8000d868: 001c0c13 addi s8,s8,1 -8000d86c: 944ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000d870: 001c4703 lbu a4,1(s8) -8000d874: 020b6b13 ori s6,s6,32 -8000d878: 001c0c13 addi s8,s8,1 -8000d87c: 934ff06f j 8000c9b0 <_vfiprintf_r+0x1a8> -8000d880: 00c12783 lw a5,12(sp) -8000d884: 00f72023 sw a5,0(a4) -8000d888: 880ff06f j 8000c908 <_vfiprintf_r+0x100> -8000d88c: 00600793 li a5,6 -8000d890: 000a8d13 mv s10,s5 -8000d894: 0b57ec63 bltu a5,s5,8000d94c <_vfiprintf_r+0x1144> -8000d898: 80015e37 lui t3,0x80015 -8000d89c: 000d0c93 mv s9,s10 -8000d8a0: 01b12823 sw s11,16(sp) -8000d8a4: c54e0413 addi s0,t3,-940 # 80014c54 <__BSS_END__+0xffffe024> -8000d8a8: 978ff06f j 8000ca20 <_vfiprintf_r+0x218> -8000d8ac: 200b7793 andi a5,s6,512 -8000d8b0: 10078863 beqz a5,8000d9c0 <_vfiprintf_r+0x11b8> -8000d8b4: 01012783 lw a5,16(sp) -8000d8b8: 00000c93 li s9,0 -8000d8bc: 00d12823 sw a3,16(sp) -8000d8c0: 0007cd03 lbu s10,0(a5) -8000d8c4: e81ff06f j 8000d744 <_vfiprintf_r+0xf3c> -8000d8c8: 200b7793 andi a5,s6,512 -8000d8cc: 0c078e63 beqz a5,8000d9a8 <_vfiprintf_r+0x11a0> -8000d8d0: 01012783 lw a5,16(sp) -8000d8d4: 00e12823 sw a4,16(sp) -8000d8d8: 00078d03 lb s10,0(a5) -8000d8dc: 41fd5c93 srai s9,s10,0x1f -8000d8e0: 000c8713 mv a4,s9 -8000d8e4: b68ff06f j 8000cc4c <_vfiprintf_r+0x444> -8000d8e8: 200df793 andi a5,s11,512 -8000d8ec: 0a078263 beqz a5,8000d990 <_vfiprintf_r+0x1188> -8000d8f0: 01012783 lw a5,16(sp) -8000d8f4: 00000c93 li s9,0 -8000d8f8: 00e12823 sw a4,16(sp) -8000d8fc: 0007cd03 lbu s10,0(a5) -8000d900: 00100713 li a4,1 -8000d904: c14ff06f j 8000cd18 <_vfiprintf_r+0x510> -8000d908: 200b7793 andi a5,s6,512 -8000d90c: 06078863 beqz a5,8000d97c <_vfiprintf_r+0x1174> -8000d910: 01012783 lw a5,16(sp) -8000d914: 00000c93 li s9,0 -8000d918: 00e12823 sw a4,16(sp) -8000d91c: 0007cd03 lbu s10,0(a5) -8000d920: bf0ff06f j 8000cd10 <_vfiprintf_r+0x508> -8000d924: 00068593 mv a1,a3 -8000d928: 8d5ff06f j 8000d1fc <_vfiprintf_r+0x9f4> -8000d92c: 00900793 li a5,9 -8000d930: cf37e2e3 bltu a5,s3,8000d614 <_vfiprintf_r+0xe0c> -8000d934: d2dff06f j 8000d660 <_vfiprintf_r+0xe58> -8000d938: 05410693 addi a3,sp,84 -8000d93c: 00100613 li a2,1 -8000d940: 00000713 li a4,0 -8000d944: 00048b93 mv s7,s1 -8000d948: 9b0ff06f j 8000caf8 <_vfiprintf_r+0x2f0> -8000d94c: 00600d13 li s10,6 -8000d950: f49ff06f j 8000d898 <_vfiprintf_r+0x1090> -8000d954: 03b10793 addi a5,sp,59 -8000d958: 04f12623 sw a5,76(sp) -8000d95c: 00100793 li a5,1 -8000d960: 04f12823 sw a5,80(sp) -8000d964: 00100613 li a2,1 -8000d968: 05410693 addi a3,sp,84 -8000d96c: 918ff06f j 8000ca84 <_vfiprintf_r+0x27c> -8000d970: 00c12783 lw a5,12(sp) -8000d974: 00f71023 sh a5,0(a4) -8000d978: f91fe06f j 8000c908 <_vfiprintf_r+0x100> -8000d97c: 01012783 lw a5,16(sp) -8000d980: 00000c93 li s9,0 -8000d984: 00e12823 sw a4,16(sp) -8000d988: 0007ad03 lw s10,0(a5) -8000d98c: b84ff06f j 8000cd10 <_vfiprintf_r+0x508> -8000d990: 01012783 lw a5,16(sp) -8000d994: 00000c93 li s9,0 -8000d998: 00e12823 sw a4,16(sp) -8000d99c: 0007ad03 lw s10,0(a5) -8000d9a0: 00100713 li a4,1 -8000d9a4: b74ff06f j 8000cd18 <_vfiprintf_r+0x510> -8000d9a8: 01012783 lw a5,16(sp) -8000d9ac: 00e12823 sw a4,16(sp) -8000d9b0: 0007ad03 lw s10,0(a5) -8000d9b4: 41fd5c93 srai s9,s10,0x1f -8000d9b8: 000c8713 mv a4,s9 -8000d9bc: a90ff06f j 8000cc4c <_vfiprintf_r+0x444> -8000d9c0: 01012783 lw a5,16(sp) -8000d9c4: 00000c93 li s9,0 -8000d9c8: 00d12823 sw a3,16(sp) -8000d9cc: 0007ad03 lw s10,0(a5) -8000d9d0: d75ff06f j 8000d744 <_vfiprintf_r+0xf3c> -8000d9d4: 04010613 addi a2,sp,64 -8000d9d8: 00098593 mv a1,s3 -8000d9dc: 000a0513 mv a0,s4 -8000d9e0: d21fe0ef jal ra,8000c700 <__sprint_r.part.0> -8000d9e4: 9a0ff06f j 8000cb84 <_vfiprintf_r+0x37c> -8000d9e8: 000a8d13 mv s10,s5 -8000d9ec: 01b12823 sw s11,16(sp) -8000d9f0: 00000a93 li s5,0 -8000d9f4: a94ff06f j 8000cc88 <_vfiprintf_r+0x480> -8000d9f8: 00068593 mv a1,a3 -8000d9fc: 99dff06f j 8000d398 <_vfiprintf_r+0xb90> -8000da00: 00160593 addi a1,a2,1 -8000da04: a71ff06f j 8000d474 <_vfiprintf_r+0xc6c> -8000da08: 000b0d93 mv s11,s6 -8000da0c: a68ff06f j 8000cc74 <_vfiprintf_r+0x46c> -8000da10: fff00793 li a5,-1 -8000da14: 00f12623 sw a5,12(sp) -8000da18: 978ff06f j 8000cb90 <_vfiprintf_r+0x388> -8000da1c: 00068513 mv a0,a3 -8000da20: 00060593 mv a1,a2 -8000da24: f0cff06f j 8000d130 <_vfiprintf_r+0x928> -8000da28: 01012783 lw a5,16(sp) -8000da2c: 0007aa83 lw s5,0(a5) -8000da30: 00478793 addi a5,a5,4 -8000da34: 000ad463 bgez s5,8000da3c <_vfiprintf_r+0x1234> -8000da38: fff00a93 li s5,-1 -8000da3c: 001c4703 lbu a4,1(s8) -8000da40: 00f12823 sw a5,16(sp) -8000da44: 00068c13 mv s8,a3 -8000da48: f69fe06f j 8000c9b0 <_vfiprintf_r+0x1a8> +8000c5b0 <_vfiprintf_r>: +8000c5b0: ed010113 addi sp,sp,-304 +8000c5b4: 11312e23 sw s3,284(sp) +8000c5b8: 11412c23 sw s4,280(sp) +8000c5bc: 11712623 sw s7,268(sp) +8000c5c0: 12112623 sw ra,300(sp) +8000c5c4: 12812423 sw s0,296(sp) +8000c5c8: 12912223 sw s1,292(sp) +8000c5cc: 13212023 sw s2,288(sp) +8000c5d0: 11512a23 sw s5,276(sp) +8000c5d4: 11612823 sw s6,272(sp) +8000c5d8: 11812423 sw s8,264(sp) +8000c5dc: 11912223 sw s9,260(sp) +8000c5e0: 11a12023 sw s10,256(sp) +8000c5e4: 0fb12e23 sw s11,252(sp) +8000c5e8: 00d12823 sw a3,16(sp) +8000c5ec: 00050a13 mv s4,a0 +8000c5f0: 00058993 mv s3,a1 +8000c5f4: 00060b93 mv s7,a2 +8000c5f8: 00050663 beqz a0,8000c604 <_vfiprintf_r+0x54> +8000c5fc: 03852783 lw a5,56(a0) +8000c600: 5e078e63 beqz a5,8000cbfc <_vfiprintf_r+0x64c> +8000c604: 00c99703 lh a4,12(s3) +8000c608: 01071793 slli a5,a4,0x10 +8000c60c: 01271693 slli a3,a4,0x12 +8000c610: 0107d793 srli a5,a5,0x10 +8000c614: 0206ca63 bltz a3,8000c648 <_vfiprintf_r+0x98> +8000c618: 000027b7 lui a5,0x2 +8000c61c: 0649a683 lw a3,100(s3) +8000c620: 00f767b3 or a5,a4,a5 +8000c624: 01079793 slli a5,a5,0x10 +8000c628: ffffe737 lui a4,0xffffe +8000c62c: 4107d793 srai a5,a5,0x10 +8000c630: fff70713 addi a4,a4,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> +8000c634: 00e6f733 and a4,a3,a4 +8000c638: 00f99623 sh a5,12(s3) +8000c63c: 01079793 slli a5,a5,0x10 +8000c640: 06e9a223 sw a4,100(s3) +8000c644: 0107d793 srli a5,a5,0x10 +8000c648: 0087f713 andi a4,a5,8 +8000c64c: 40070063 beqz a4,8000ca4c <_vfiprintf_r+0x49c> +8000c650: 0109a703 lw a4,16(s3) +8000c654: 3e070c63 beqz a4,8000ca4c <_vfiprintf_r+0x49c> +8000c658: 01a7f793 andi a5,a5,26 +8000c65c: 00a00713 li a4,10 +8000c660: 40e78663 beq a5,a4,8000ca6c <_vfiprintf_r+0x4bc> +8000c664: 800157b7 lui a5,0x80015 +8000c668: 36c78793 addi a5,a5,876 # 8001536c <__BSS_END__+0xffffe730> +8000c66c: 80015b37 lui s6,0x80015 +8000c670: 04c10493 addi s1,sp,76 +8000c674: 00f12a23 sw a5,20(sp) +8000c678: 80015937 lui s2,0x80015 +8000c67c: 4d8b0793 addi a5,s6,1240 # 800154d8 <__BSS_END__+0xffffe89c> +8000c680: 000b8c13 mv s8,s7 +8000c684: 04912023 sw s1,64(sp) +8000c688: 04012423 sw zero,72(sp) +8000c68c: 04012223 sw zero,68(sp) +8000c690: 00012c23 sw zero,24(sp) +8000c694: 00012e23 sw zero,28(sp) +8000c698: 02012223 sw zero,36(sp) +8000c69c: 02012023 sw zero,32(sp) +8000c6a0: 00012623 sw zero,12(sp) +8000c6a4: 00f12423 sw a5,8(sp) +8000c6a8: 4e890913 addi s2,s2,1256 # 800154e8 <__BSS_END__+0xffffe8ac> +8000c6ac: 00048b93 mv s7,s1 +8000c6b0: 000c4783 lbu a5,0(s8) +8000c6b4: 26078863 beqz a5,8000c924 <_vfiprintf_r+0x374> +8000c6b8: 000c0413 mv s0,s8 +8000c6bc: 02500713 li a4,37 +8000c6c0: 42e78e63 beq a5,a4,8000cafc <_vfiprintf_r+0x54c> +8000c6c4: 00144783 lbu a5,1(s0) +8000c6c8: 00140413 addi s0,s0,1 +8000c6cc: fe079ae3 bnez a5,8000c6c0 <_vfiprintf_r+0x110> +8000c6d0: 41840cb3 sub s9,s0,s8 +8000c6d4: 25840863 beq s0,s8,8000c924 <_vfiprintf_r+0x374> +8000c6d8: 04812703 lw a4,72(sp) +8000c6dc: 04412783 lw a5,68(sp) +8000c6e0: 018ba023 sw s8,0(s7) +8000c6e4: 00ec8733 add a4,s9,a4 +8000c6e8: 00178793 addi a5,a5,1 +8000c6ec: 019ba223 sw s9,4(s7) +8000c6f0: 04e12423 sw a4,72(sp) +8000c6f4: 04f12223 sw a5,68(sp) +8000c6f8: 00700693 li a3,7 +8000c6fc: 008b8b93 addi s7,s7,8 +8000c700: 02f6d063 bge a3,a5,8000c720 <_vfiprintf_r+0x170> +8000c704: 3a070ae3 beqz a4,8000d2b8 <_vfiprintf_r+0xd08> +8000c708: 04010613 addi a2,sp,64 +8000c70c: 00098593 mv a1,s3 +8000c710: 000a0513 mv a0,s4 +8000c714: d95ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000c718: 20051a63 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000c71c: 00048b93 mv s7,s1 +8000c720: 00c12703 lw a4,12(sp) +8000c724: 00044783 lbu a5,0(s0) +8000c728: 01970733 add a4,a4,s9 +8000c72c: 00e12623 sw a4,12(sp) +8000c730: 1e078a63 beqz a5,8000c924 <_vfiprintf_r+0x374> +8000c734: 00144703 lbu a4,1(s0) +8000c738: 00140c13 addi s8,s0,1 +8000c73c: 02010da3 sb zero,59(sp) +8000c740: fff00a93 li s5,-1 +8000c744: 00012223 sw zero,4(sp) +8000c748: 00000b13 li s6,0 +8000c74c: 05a00c93 li s9,90 +8000c750: 00900d13 li s10,9 +8000c754: 02a00613 li a2,42 +8000c758: 001c0c13 addi s8,s8,1 +8000c75c: fe070793 addi a5,a4,-32 +8000c760: 04fce863 bltu s9,a5,8000c7b0 <_vfiprintf_r+0x200> +8000c764: 01412683 lw a3,20(sp) +8000c768: 00279793 slli a5,a5,0x2 +8000c76c: 00d787b3 add a5,a5,a3 +8000c770: 0007a783 lw a5,0(a5) +8000c774: 00078067 jr a5 +8000c778: 00012223 sw zero,4(sp) +8000c77c: fd070793 addi a5,a4,-48 +8000c780: 00412583 lw a1,4(sp) +8000c784: 000c4703 lbu a4,0(s8) +8000c788: 001c0c13 addi s8,s8,1 +8000c78c: 00259693 slli a3,a1,0x2 +8000c790: 00b686b3 add a3,a3,a1 +8000c794: 00169693 slli a3,a3,0x1 +8000c798: 00d787b3 add a5,a5,a3 +8000c79c: 00f12223 sw a5,4(sp) +8000c7a0: fd070793 addi a5,a4,-48 +8000c7a4: fcfd7ee3 bgeu s10,a5,8000c780 <_vfiprintf_r+0x1d0> +8000c7a8: fe070793 addi a5,a4,-32 +8000c7ac: fafcfce3 bgeu s9,a5,8000c764 <_vfiprintf_r+0x1b4> +8000c7b0: 16070a63 beqz a4,8000c924 <_vfiprintf_r+0x374> +8000c7b4: 08e10623 sb a4,140(sp) +8000c7b8: 02010da3 sb zero,59(sp) +8000c7bc: 00100c93 li s9,1 +8000c7c0: 00100d13 li s10,1 +8000c7c4: 08c10413 addi s0,sp,140 +8000c7c8: 00000a93 li s5,0 +8000c7cc: 002b7f93 andi t6,s6,2 +8000c7d0: 000f8463 beqz t6,8000c7d8 <_vfiprintf_r+0x228> +8000c7d4: 002c8c93 addi s9,s9,2 +8000c7d8: 04412703 lw a4,68(sp) +8000c7dc: 084b7f13 andi t5,s6,132 +8000c7e0: 04812783 lw a5,72(sp) +8000c7e4: 00170693 addi a3,a4,1 +8000c7e8: 00068613 mv a2,a3 +8000c7ec: 000f1863 bnez t5,8000c7fc <_vfiprintf_r+0x24c> +8000c7f0: 00412583 lw a1,4(sp) +8000c7f4: 41958db3 sub s11,a1,s9 +8000c7f8: 09b042e3 bgtz s11,8000d07c <_vfiprintf_r+0xacc> +8000c7fc: 03b14583 lbu a1,59(sp) +8000c800: 008b8693 addi a3,s7,8 +8000c804: 02058c63 beqz a1,8000c83c <_vfiprintf_r+0x28c> +8000c808: 03b10713 addi a4,sp,59 +8000c80c: 00178793 addi a5,a5,1 +8000c810: 00eba023 sw a4,0(s7) +8000c814: 00100713 li a4,1 +8000c818: 00eba223 sw a4,4(s7) +8000c81c: 04f12423 sw a5,72(sp) +8000c820: 04c12223 sw a2,68(sp) +8000c824: 00700713 li a4,7 +8000c828: 7ec74063 blt a4,a2,8000d008 <_vfiprintf_r+0xa58> +8000c82c: 00060713 mv a4,a2 +8000c830: 00068b93 mv s7,a3 +8000c834: 00160613 addi a2,a2,1 +8000c838: 00868693 addi a3,a3,8 +8000c83c: 040f8e63 beqz t6,8000c898 <_vfiprintf_r+0x2e8> +8000c840: 03c10713 addi a4,sp,60 +8000c844: 00278793 addi a5,a5,2 +8000c848: 00eba023 sw a4,0(s7) +8000c84c: 00200713 li a4,2 +8000c850: 00eba223 sw a4,4(s7) +8000c854: 04f12423 sw a5,72(sp) +8000c858: 04c12223 sw a2,68(sp) +8000c85c: 00700713 li a4,7 +8000c860: 00c750e3 bge a4,a2,8000d060 <_vfiprintf_r+0xab0> +8000c864: 2a0784e3 beqz a5,8000d30c <_vfiprintf_r+0xd5c> +8000c868: 04010613 addi a2,sp,64 +8000c86c: 00098593 mv a1,s3 +8000c870: 000a0513 mv a0,s4 +8000c874: 03e12423 sw t5,40(sp) +8000c878: c31ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000c87c: 0a051863 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000c880: 04412703 lw a4,68(sp) +8000c884: 04812783 lw a5,72(sp) +8000c888: 02812f03 lw t5,40(sp) +8000c88c: 05410693 addi a3,sp,84 +8000c890: 00170613 addi a2,a4,1 +8000c894: 00048b93 mv s7,s1 +8000c898: 08000593 li a1,128 +8000c89c: 5abf0663 beq t5,a1,8000ce48 <_vfiprintf_r+0x898> +8000c8a0: 41aa8ab3 sub s5,s5,s10 +8000c8a4: 69504263 bgtz s5,8000cf28 <_vfiprintf_r+0x978> +8000c8a8: 00fd07b3 add a5,s10,a5 +8000c8ac: 008ba023 sw s0,0(s7) +8000c8b0: 01aba223 sw s10,4(s7) +8000c8b4: 04f12423 sw a5,72(sp) +8000c8b8: 04c12223 sw a2,68(sp) +8000c8bc: 00700713 li a4,7 +8000c8c0: 02c75263 bge a4,a2,8000c8e4 <_vfiprintf_r+0x334> +8000c8c4: 0a078ee3 beqz a5,8000d180 <_vfiprintf_r+0xbd0> +8000c8c8: 04010613 addi a2,sp,64 +8000c8cc: 00098593 mv a1,s3 +8000c8d0: 000a0513 mv a0,s4 +8000c8d4: bd5ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000c8d8: 04051a63 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000c8dc: 04812783 lw a5,72(sp) +8000c8e0: 00048693 mv a3,s1 +8000c8e4: 004b7313 andi t1,s6,4 +8000c8e8: 00030863 beqz t1,8000c8f8 <_vfiprintf_r+0x348> +8000c8ec: 00412703 lw a4,4(sp) +8000c8f0: 41970bb3 sub s7,a4,s9 +8000c8f4: 0b7044e3 bgtz s7,8000d19c <_vfiprintf_r+0xbec> +8000c8f8: 00412403 lw s0,4(sp) +8000c8fc: 01945463 bge s0,s9,8000c904 <_vfiprintf_r+0x354> +8000c900: 000c8413 mv s0,s9 +8000c904: 00c12703 lw a4,12(sp) +8000c908: 00870733 add a4,a4,s0 +8000c90c: 00e12623 sw a4,12(sp) +8000c910: 6c079863 bnez a5,8000cfe0 <_vfiprintf_r+0xa30> +8000c914: 000c4783 lbu a5,0(s8) +8000c918: 04012223 sw zero,68(sp) +8000c91c: 00048b93 mv s7,s1 +8000c920: d8079ce3 bnez a5,8000c6b8 <_vfiprintf_r+0x108> +8000c924: 04812783 lw a5,72(sp) +8000c928: 64079ae3 bnez a5,8000d77c <_vfiprintf_r+0x11cc> +8000c92c: 00c9d783 lhu a5,12(s3) +8000c930: 0407f793 andi a5,a5,64 +8000c934: 680792e3 bnez a5,8000d7b8 <_vfiprintf_r+0x1208> +8000c938: 12c12083 lw ra,300(sp) +8000c93c: 12812403 lw s0,296(sp) +8000c940: 00c12503 lw a0,12(sp) +8000c944: 12412483 lw s1,292(sp) +8000c948: 12012903 lw s2,288(sp) +8000c94c: 11c12983 lw s3,284(sp) +8000c950: 11812a03 lw s4,280(sp) +8000c954: 11412a83 lw s5,276(sp) +8000c958: 11012b03 lw s6,272(sp) +8000c95c: 10c12b83 lw s7,268(sp) +8000c960: 10812c03 lw s8,264(sp) +8000c964: 10412c83 lw s9,260(sp) +8000c968: 10012d03 lw s10,256(sp) +8000c96c: 0fc12d83 lw s11,252(sp) +8000c970: 13010113 addi sp,sp,304 +8000c974: 00008067 ret +8000c978: 000a0513 mv a0,s4 +8000c97c: 82cfb0ef jal ra,800079a8 <_localeconv_r> +8000c980: 00452783 lw a5,4(a0) +8000c984: 00078513 mv a0,a5 +8000c988: 02f12023 sw a5,32(sp) +8000c98c: fd5fc0ef jal ra,80009960 +8000c990: 00050793 mv a5,a0 +8000c994: 000a0513 mv a0,s4 +8000c998: 00078413 mv s0,a5 +8000c99c: 02f12223 sw a5,36(sp) +8000c9a0: 808fb0ef jal ra,800079a8 <_localeconv_r> +8000c9a4: 00852783 lw a5,8(a0) +8000c9a8: 02a00613 li a2,42 +8000c9ac: 00f12e23 sw a5,28(sp) +8000c9b0: 2a0418e3 bnez s0,8000d460 <_vfiprintf_r+0xeb0> +8000c9b4: 000c4703 lbu a4,0(s8) +8000c9b8: da1ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000c9bc: 000c4703 lbu a4,0(s8) +8000c9c0: 020b6b13 ori s6,s6,32 +8000c9c4: d95ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000c9c8: 010b6b13 ori s6,s6,16 +8000c9cc: 020b7793 andi a5,s6,32 +8000c9d0: 16078463 beqz a5,8000cb38 <_vfiprintf_r+0x588> +8000c9d4: 01012783 lw a5,16(sp) +8000c9d8: 00778793 addi a5,a5,7 +8000c9dc: ff87f793 andi a5,a5,-8 +8000c9e0: 0047a703 lw a4,4(a5) +8000c9e4: 0007ad03 lw s10,0(a5) +8000c9e8: 00878793 addi a5,a5,8 +8000c9ec: 00f12823 sw a5,16(sp) +8000c9f0: 00070c93 mv s9,a4 +8000c9f4: 16074a63 bltz a4,8000cb68 <_vfiprintf_r+0x5b8> +8000c9f8: fff00713 li a4,-1 +8000c9fc: 000b0d93 mv s11,s6 +8000ca00: 00ea8863 beq s5,a4,8000ca10 <_vfiprintf_r+0x460> +8000ca04: 019d6733 or a4,s10,s9 +8000ca08: f7fb7d93 andi s11,s6,-129 +8000ca0c: 0a070ce3 beqz a4,8000d2c4 <_vfiprintf_r+0xd14> +8000ca10: 160c96e3 bnez s9,8000d37c <_vfiprintf_r+0xdcc> +8000ca14: 00900713 li a4,9 +8000ca18: 17a762e3 bltu a4,s10,8000d37c <_vfiprintf_r+0xdcc> +8000ca1c: 030d0793 addi a5,s10,48 +8000ca20: 0ef107a3 sb a5,239(sp) +8000ca24: 000d8b13 mv s6,s11 +8000ca28: 00100d13 li s10,1 +8000ca2c: 0ef10413 addi s0,sp,239 +8000ca30: 000a8c93 mv s9,s5 +8000ca34: 01aad463 bge s5,s10,8000ca3c <_vfiprintf_r+0x48c> +8000ca38: 000d0c93 mv s9,s10 +8000ca3c: 03b14783 lbu a5,59(sp) +8000ca40: 00f037b3 snez a5,a5 +8000ca44: 00fc8cb3 add s9,s9,a5 +8000ca48: d85ff06f j 8000c7cc <_vfiprintf_r+0x21c> +8000ca4c: 00098593 mv a1,s3 +8000ca50: 000a0513 mv a0,s4 +8000ca54: d2cf70ef jal ra,80003f80 <__swsetup_r> +8000ca58: 560510e3 bnez a0,8000d7b8 <_vfiprintf_r+0x1208> +8000ca5c: 00c9d783 lhu a5,12(s3) +8000ca60: 00a00713 li a4,10 +8000ca64: 01a7f793 andi a5,a5,26 +8000ca68: bee79ee3 bne a5,a4,8000c664 <_vfiprintf_r+0xb4> +8000ca6c: 00e99783 lh a5,14(s3) +8000ca70: be07cae3 bltz a5,8000c664 <_vfiprintf_r+0xb4> +8000ca74: 01012683 lw a3,16(sp) +8000ca78: 000b8613 mv a2,s7 +8000ca7c: 00098593 mv a1,s3 +8000ca80: 000a0513 mv a0,s4 +8000ca84: 589000ef jal ra,8000d80c <__sbprintf> +8000ca88: 00a12623 sw a0,12(sp) +8000ca8c: eadff06f j 8000c938 <_vfiprintf_r+0x388> +8000ca90: 010b6b13 ori s6,s6,16 +8000ca94: 020b7793 andi a5,s6,32 +8000ca98: 06078a63 beqz a5,8000cb0c <_vfiprintf_r+0x55c> +8000ca9c: 01012783 lw a5,16(sp) +8000caa0: 00778793 addi a5,a5,7 +8000caa4: ff87f793 andi a5,a5,-8 +8000caa8: 0007ad03 lw s10,0(a5) +8000caac: 0047ac83 lw s9,4(a5) +8000cab0: 00878793 addi a5,a5,8 +8000cab4: 00f12823 sw a5,16(sp) +8000cab8: bffb7d93 andi s11,s6,-1025 +8000cabc: 00000713 li a4,0 +8000cac0: 02010da3 sb zero,59(sp) +8000cac4: fff00693 li a3,-1 +8000cac8: 0cda8463 beq s5,a3,8000cb90 <_vfiprintf_r+0x5e0> +8000cacc: 019d66b3 or a3,s10,s9 +8000cad0: f7fdfb13 andi s6,s11,-129 +8000cad4: 5a069063 bnez a3,8000d074 <_vfiprintf_r+0xac4> +8000cad8: 300a9c63 bnez s5,8000cdf0 <_vfiprintf_r+0x840> +8000cadc: 7e071863 bnez a4,8000d2cc <_vfiprintf_r+0xd1c> +8000cae0: 001dfd13 andi s10,s11,1 +8000cae4: 0f010413 addi s0,sp,240 +8000cae8: f40d04e3 beqz s10,8000ca30 <_vfiprintf_r+0x480> +8000caec: 03000793 li a5,48 +8000caf0: 0ef107a3 sb a5,239(sp) +8000caf4: 0ef10413 addi s0,sp,239 +8000caf8: f39ff06f j 8000ca30 <_vfiprintf_r+0x480> +8000cafc: 41840cb3 sub s9,s0,s8 +8000cb00: bd841ce3 bne s0,s8,8000c6d8 <_vfiprintf_r+0x128> +8000cb04: 00044783 lbu a5,0(s0) +8000cb08: c29ff06f j 8000c730 <_vfiprintf_r+0x180> +8000cb0c: 01012683 lw a3,16(sp) +8000cb10: 010b7793 andi a5,s6,16 +8000cb14: 00468713 addi a4,a3,4 +8000cb18: 16079ce3 bnez a5,8000d490 <_vfiprintf_r+0xee0> +8000cb1c: 040b7793 andi a5,s6,64 +8000cb20: 380788e3 beqz a5,8000d6b0 <_vfiprintf_r+0x1100> +8000cb24: 01012783 lw a5,16(sp) +8000cb28: 00000c93 li s9,0 +8000cb2c: 00e12823 sw a4,16(sp) +8000cb30: 0007dd03 lhu s10,0(a5) +8000cb34: f85ff06f j 8000cab8 <_vfiprintf_r+0x508> +8000cb38: 01012683 lw a3,16(sp) +8000cb3c: 010b7793 andi a5,s6,16 +8000cb40: 00468713 addi a4,a3,4 +8000cb44: 100794e3 bnez a5,8000d44c <_vfiprintf_r+0xe9c> +8000cb48: 040b7793 andi a5,s6,64 +8000cb4c: 320782e3 beqz a5,8000d670 <_vfiprintf_r+0x10c0> +8000cb50: 01012783 lw a5,16(sp) +8000cb54: 00e12823 sw a4,16(sp) +8000cb58: 00079d03 lh s10,0(a5) +8000cb5c: 41fd5c93 srai s9,s10,0x1f +8000cb60: 000c8713 mv a4,s9 +8000cb64: e8075ae3 bgez a4,8000c9f8 <_vfiprintf_r+0x448> +8000cb68: 01a03733 snez a4,s10 +8000cb6c: 41900eb3 neg t4,s9 +8000cb70: 40ee8cb3 sub s9,t4,a4 +8000cb74: 02d00713 li a4,45 +8000cb78: 02e10da3 sb a4,59(sp) +8000cb7c: fff00693 li a3,-1 +8000cb80: 41a00d33 neg s10,s10 +8000cb84: 000b0d93 mv s11,s6 +8000cb88: 00100713 li a4,1 +8000cb8c: f4da90e3 bne s5,a3,8000cacc <_vfiprintf_r+0x51c> +8000cb90: 00100693 li a3,1 +8000cb94: e6d70ee3 beq a4,a3,8000ca10 <_vfiprintf_r+0x460> +8000cb98: 00200693 li a3,2 +8000cb9c: 26d70463 beq a4,a3,8000ce04 <_vfiprintf_r+0x854> +8000cba0: 0f010413 addi s0,sp,240 +8000cba4: 01dc9793 slli a5,s9,0x1d +8000cba8: 007d7713 andi a4,s10,7 +8000cbac: 003d5d13 srli s10,s10,0x3 +8000cbb0: 03070713 addi a4,a4,48 +8000cbb4: 01a7ed33 or s10,a5,s10 +8000cbb8: 003cdc93 srli s9,s9,0x3 +8000cbbc: fee40fa3 sb a4,-1(s0) +8000cbc0: 019d67b3 or a5,s10,s9 +8000cbc4: 00040613 mv a2,s0 +8000cbc8: fff40413 addi s0,s0,-1 +8000cbcc: fc079ce3 bnez a5,8000cba4 <_vfiprintf_r+0x5f4> +8000cbd0: 001df793 andi a5,s11,1 +8000cbd4: 26078263 beqz a5,8000ce38 <_vfiprintf_r+0x888> +8000cbd8: 03000793 li a5,48 +8000cbdc: 24f70e63 beq a4,a5,8000ce38 <_vfiprintf_r+0x888> +8000cbe0: ffe60613 addi a2,a2,-2 +8000cbe4: fef40fa3 sb a5,-1(s0) +8000cbe8: 0f010793 addi a5,sp,240 +8000cbec: 40c78d33 sub s10,a5,a2 +8000cbf0: 000d8b13 mv s6,s11 +8000cbf4: 00060413 mv s0,a2 +8000cbf8: e39ff06f j 8000ca30 <_vfiprintf_r+0x480> +8000cbfc: c0df70ef jal ra,80004808 <__sinit> +8000cc00: a05ff06f j 8000c604 <_vfiprintf_r+0x54> +8000cc04: 01012783 lw a5,16(sp) +8000cc08: 02010da3 sb zero,59(sp) +8000cc0c: 0007a403 lw s0,0(a5) +8000cc10: 00478d93 addi s11,a5,4 +8000cc14: 220400e3 beqz s0,8000d634 <_vfiprintf_r+0x1084> +8000cc18: fff00793 li a5,-1 +8000cc1c: 12fa88e3 beq s5,a5,8000d54c <_vfiprintf_r+0xf9c> +8000cc20: 000a8613 mv a2,s5 +8000cc24: 00000593 li a1,0 +8000cc28: 00040513 mv a0,s0 +8000cc2c: f14fb0ef jal ra,80008340 +8000cc30: 360500e3 beqz a0,8000d790 <_vfiprintf_r+0x11e0> +8000cc34: 40850d33 sub s10,a0,s0 +8000cc38: 01b12823 sw s11,16(sp) +8000cc3c: 00000a93 li s5,0 +8000cc40: df1ff06f j 8000ca30 <_vfiprintf_r+0x480> +8000cc44: 01012703 lw a4,16(sp) +8000cc48: 02010da3 sb zero,59(sp) +8000cc4c: 00100c93 li s9,1 +8000cc50: 00072783 lw a5,0(a4) +8000cc54: 00470713 addi a4,a4,4 +8000cc58: 00e12823 sw a4,16(sp) +8000cc5c: 08f10623 sb a5,140(sp) +8000cc60: 00100d13 li s10,1 +8000cc64: 08c10413 addi s0,sp,140 +8000cc68: b61ff06f j 8000c7c8 <_vfiprintf_r+0x218> +8000cc6c: 01012783 lw a5,16(sp) +8000cc70: ffff8737 lui a4,0xffff8 +8000cc74: 83074713 xori a4,a4,-2000 +8000cc78: 0007ad03 lw s10,0(a5) +8000cc7c: 00478793 addi a5,a5,4 +8000cc80: 00f12823 sw a5,16(sp) +8000cc84: 800157b7 lui a5,0x80015 +8000cc88: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +8000cc8c: 02e11e23 sh a4,60(sp) +8000cc90: 00000c93 li s9,0 +8000cc94: 002b6d93 ori s11,s6,2 +8000cc98: 00f12c23 sw a5,24(sp) +8000cc9c: 00200713 li a4,2 +8000cca0: e21ff06f j 8000cac0 <_vfiprintf_r+0x510> +8000cca4: 000c4703 lbu a4,0(s8) +8000cca8: 06c00793 li a5,108 +8000ccac: 16f706e3 beq a4,a5,8000d618 <_vfiprintf_r+0x1068> +8000ccb0: 010b6b13 ori s6,s6,16 +8000ccb4: aa5ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000ccb8: 000c4703 lbu a4,0(s8) +8000ccbc: 06800793 li a5,104 +8000ccc0: 14f704e3 beq a4,a5,8000d608 <_vfiprintf_r+0x1058> +8000ccc4: 040b6b13 ori s6,s6,64 +8000ccc8: a91ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000cccc: 010b6d93 ori s11,s6,16 +8000ccd0: 020df793 andi a5,s11,32 +8000ccd4: 60078463 beqz a5,8000d2dc <_vfiprintf_r+0xd2c> +8000ccd8: 01012783 lw a5,16(sp) +8000ccdc: 00100713 li a4,1 +8000cce0: 00778793 addi a5,a5,7 +8000cce4: ff87f793 andi a5,a5,-8 +8000cce8: 0007ad03 lw s10,0(a5) +8000ccec: 0047ac83 lw s9,4(a5) +8000ccf0: 00878793 addi a5,a5,8 +8000ccf4: 00f12823 sw a5,16(sp) +8000ccf8: dc9ff06f j 8000cac0 <_vfiprintf_r+0x510> +8000ccfc: 000c4703 lbu a4,0(s8) +8000cd00: 080b6b13 ori s6,s6,128 +8000cd04: a55ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000cd08: 01012683 lw a3,16(sp) +8000cd0c: 000c4703 lbu a4,0(s8) +8000cd10: 0006a783 lw a5,0(a3) +8000cd14: 00468693 addi a3,a3,4 +8000cd18: 00d12823 sw a3,16(sp) +8000cd1c: 00f12223 sw a5,4(sp) +8000cd20: a207dce3 bgez a5,8000c758 <_vfiprintf_r+0x1a8> +8000cd24: 40f007b3 neg a5,a5 +8000cd28: 00f12223 sw a5,4(sp) +8000cd2c: 004b6b13 ori s6,s6,4 +8000cd30: a29ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000cd34: 000c4703 lbu a4,0(s8) +8000cd38: 001b6b13 ori s6,s6,1 +8000cd3c: a1dff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000cd40: 03b14783 lbu a5,59(sp) +8000cd44: 000c4703 lbu a4,0(s8) +8000cd48: a00798e3 bnez a5,8000c758 <_vfiprintf_r+0x1a8> +8000cd4c: 02000793 li a5,32 +8000cd50: 02f10da3 sb a5,59(sp) +8000cd54: a05ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000cd58: 000c4703 lbu a4,0(s8) +8000cd5c: 004b6b13 ori s6,s6,4 +8000cd60: 9f9ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000cd64: 02b00793 li a5,43 +8000cd68: 000c4703 lbu a4,0(s8) +8000cd6c: 02f10da3 sb a5,59(sp) +8000cd70: 9e9ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000cd74: 000c4703 lbu a4,0(s8) +8000cd78: 001c0693 addi a3,s8,1 +8000cd7c: 24c70ae3 beq a4,a2,8000d7d0 <_vfiprintf_r+0x1220> +8000cd80: fd070793 addi a5,a4,-48 # ffff7fd0 <__BSS_END__+0x7ffe1394> +8000cd84: 00068c13 mv s8,a3 +8000cd88: 00000a93 li s5,0 +8000cd8c: 9cfd68e3 bltu s10,a5,8000c75c <_vfiprintf_r+0x1ac> +8000cd90: 000c4703 lbu a4,0(s8) +8000cd94: 002a9693 slli a3,s5,0x2 +8000cd98: 01568ab3 add s5,a3,s5 +8000cd9c: 001a9a93 slli s5,s5,0x1 +8000cda0: 00fa8ab3 add s5,s5,a5 +8000cda4: fd070793 addi a5,a4,-48 +8000cda8: 001c0c13 addi s8,s8,1 +8000cdac: fefd72e3 bgeu s10,a5,8000cd90 <_vfiprintf_r+0x7e0> +8000cdb0: 9adff06f j 8000c75c <_vfiprintf_r+0x1ac> +8000cdb4: 01012683 lw a3,16(sp) +8000cdb8: 020b7793 andi a5,s6,32 +8000cdbc: 0006a703 lw a4,0(a3) +8000cdc0: 00468693 addi a3,a3,4 +8000cdc4: 00d12823 sw a3,16(sp) +8000cdc8: 6a079a63 bnez a5,8000d47c <_vfiprintf_r+0xecc> +8000cdcc: 010b7793 andi a5,s6,16 +8000cdd0: 04079ce3 bnez a5,8000d628 <_vfiprintf_r+0x1078> +8000cdd4: 040b7793 andi a5,s6,64 +8000cdd8: 140790e3 bnez a5,8000d718 <_vfiprintf_r+0x1168> +8000cddc: 200b7313 andi t1,s6,512 +8000cde0: 040304e3 beqz t1,8000d628 <_vfiprintf_r+0x1078> +8000cde4: 00c12783 lw a5,12(sp) +8000cde8: 00f70023 sb a5,0(a4) +8000cdec: 8c5ff06f j 8000c6b0 <_vfiprintf_r+0x100> +8000cdf0: 00100693 li a3,1 +8000cdf4: 1ad70ee3 beq a4,a3,8000d7b0 <_vfiprintf_r+0x1200> +8000cdf8: 00200693 li a3,2 +8000cdfc: 000b0d93 mv s11,s6 +8000ce00: dad710e3 bne a4,a3,8000cba0 <_vfiprintf_r+0x5f0> +8000ce04: 01812683 lw a3,24(sp) +8000ce08: 0f010413 addi s0,sp,240 +8000ce0c: 00fd7793 andi a5,s10,15 +8000ce10: 00f687b3 add a5,a3,a5 +8000ce14: 0007c703 lbu a4,0(a5) +8000ce18: 004d5d13 srli s10,s10,0x4 +8000ce1c: 01cc9793 slli a5,s9,0x1c +8000ce20: 01a7ed33 or s10,a5,s10 +8000ce24: 004cdc93 srli s9,s9,0x4 +8000ce28: fee40fa3 sb a4,-1(s0) +8000ce2c: 019d67b3 or a5,s10,s9 +8000ce30: fff40413 addi s0,s0,-1 +8000ce34: fc079ce3 bnez a5,8000ce0c <_vfiprintf_r+0x85c> +8000ce38: 0f010793 addi a5,sp,240 +8000ce3c: 40878d33 sub s10,a5,s0 +8000ce40: 000d8b13 mv s6,s11 +8000ce44: bedff06f j 8000ca30 <_vfiprintf_r+0x480> +8000ce48: 00412583 lw a1,4(sp) +8000ce4c: 41958db3 sub s11,a1,s9 +8000ce50: a5b058e3 blez s11,8000c8a0 <_vfiprintf_r+0x2f0> +8000ce54: 01000593 li a1,16 +8000ce58: 17b5d6e3 bge a1,s11,8000d7c4 <_vfiprintf_r+0x1214> +8000ce5c: 01000e93 li t4,16 +8000ce60: 00700f13 li t5,7 +8000ce64: 0180006f j 8000ce7c <_vfiprintf_r+0x8cc> +8000ce68: 00270613 addi a2,a4,2 +8000ce6c: 008b8b93 addi s7,s7,8 +8000ce70: 00068713 mv a4,a3 +8000ce74: ff0d8d93 addi s11,s11,-16 +8000ce78: 05bedc63 bge t4,s11,8000ced0 <_vfiprintf_r+0x920> +8000ce7c: 01078793 addi a5,a5,16 +8000ce80: 00170693 addi a3,a4,1 +8000ce84: 012ba023 sw s2,0(s7) +8000ce88: 01dba223 sw t4,4(s7) +8000ce8c: 04f12423 sw a5,72(sp) +8000ce90: 04d12223 sw a3,68(sp) +8000ce94: fcdf5ae3 bge t5,a3,8000ce68 <_vfiprintf_r+0x8b8> +8000ce98: 16078063 beqz a5,8000cff8 <_vfiprintf_r+0xa48> +8000ce9c: 04010613 addi a2,sp,64 +8000cea0: 00098593 mv a1,s3 +8000cea4: 000a0513 mv a0,s4 +8000cea8: e00ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000ceac: a80510e3 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000ceb0: 04412703 lw a4,68(sp) +8000ceb4: 01000e93 li t4,16 +8000ceb8: ff0d8d93 addi s11,s11,-16 +8000cebc: 04812783 lw a5,72(sp) +8000cec0: 00048b93 mv s7,s1 +8000cec4: 00170613 addi a2,a4,1 +8000cec8: 00700f13 li t5,7 +8000cecc: fbbec8e3 blt t4,s11,8000ce7c <_vfiprintf_r+0x8cc> +8000ced0: 00060593 mv a1,a2 +8000ced4: 008b8513 addi a0,s7,8 +8000ced8: 01b787b3 add a5,a5,s11 +8000cedc: 012ba023 sw s2,0(s7) +8000cee0: 01bba223 sw s11,4(s7) +8000cee4: 04f12423 sw a5,72(sp) +8000cee8: 04b12223 sw a1,68(sp) +8000ceec: 00700713 li a4,7 +8000cef0: 52b75a63 bge a4,a1,8000d424 <_vfiprintf_r+0xe74> +8000cef4: 7e078663 beqz a5,8000d6e0 <_vfiprintf_r+0x1130> +8000cef8: 04010613 addi a2,sp,64 +8000cefc: 00098593 mv a1,s3 +8000cf00: 000a0513 mv a0,s4 +8000cf04: da4ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000cf08: a20512e3 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000cf0c: 04412703 lw a4,68(sp) +8000cf10: 41aa8ab3 sub s5,s5,s10 +8000cf14: 04812783 lw a5,72(sp) +8000cf18: 05410693 addi a3,sp,84 +8000cf1c: 00170613 addi a2,a4,1 +8000cf20: 00048b93 mv s7,s1 +8000cf24: 995052e3 blez s5,8000c8a8 <_vfiprintf_r+0x2f8> +8000cf28: 01000593 li a1,16 +8000cf2c: 7b55d063 bge a1,s5,8000d6cc <_vfiprintf_r+0x111c> +8000cf30: 01000893 li a7,16 +8000cf34: 00700d93 li s11,7 +8000cf38: 0180006f j 8000cf50 <_vfiprintf_r+0x9a0> +8000cf3c: 00270613 addi a2,a4,2 +8000cf40: 008b8b93 addi s7,s7,8 +8000cf44: 00068713 mv a4,a3 +8000cf48: ff0a8a93 addi s5,s5,-16 +8000cf4c: 0558da63 bge a7,s5,8000cfa0 <_vfiprintf_r+0x9f0> +8000cf50: 01078793 addi a5,a5,16 +8000cf54: 00170693 addi a3,a4,1 +8000cf58: 012ba023 sw s2,0(s7) +8000cf5c: 011ba223 sw a7,4(s7) +8000cf60: 04f12423 sw a5,72(sp) +8000cf64: 04d12223 sw a3,68(sp) +8000cf68: fcdddae3 bge s11,a3,8000cf3c <_vfiprintf_r+0x98c> +8000cf6c: 06078263 beqz a5,8000cfd0 <_vfiprintf_r+0xa20> +8000cf70: 04010613 addi a2,sp,64 +8000cf74: 00098593 mv a1,s3 +8000cf78: 000a0513 mv a0,s4 +8000cf7c: d2cff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000cf80: 9a0516e3 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000cf84: 04412703 lw a4,68(sp) +8000cf88: 01000893 li a7,16 +8000cf8c: ff0a8a93 addi s5,s5,-16 +8000cf90: 04812783 lw a5,72(sp) +8000cf94: 00048b93 mv s7,s1 +8000cf98: 00170613 addi a2,a4,1 +8000cf9c: fb58cae3 blt a7,s5,8000cf50 <_vfiprintf_r+0x9a0> +8000cfa0: 008b8593 addi a1,s7,8 +8000cfa4: 015787b3 add a5,a5,s5 +8000cfa8: 012ba023 sw s2,0(s7) +8000cfac: 015ba223 sw s5,4(s7) +8000cfb0: 04f12423 sw a5,72(sp) +8000cfb4: 04c12223 sw a2,68(sp) +8000cfb8: 00700713 li a4,7 +8000cfbc: 2cc74663 blt a4,a2,8000d288 <_vfiprintf_r+0xcd8> +8000cfc0: 00160613 addi a2,a2,1 +8000cfc4: 00858693 addi a3,a1,8 +8000cfc8: 00058b93 mv s7,a1 +8000cfcc: 8ddff06f j 8000c8a8 <_vfiprintf_r+0x2f8> +8000cfd0: 00100613 li a2,1 +8000cfd4: 00000713 li a4,0 +8000cfd8: 00048b93 mv s7,s1 +8000cfdc: f6dff06f j 8000cf48 <_vfiprintf_r+0x998> +8000cfe0: 04010613 addi a2,sp,64 +8000cfe4: 00098593 mv a1,s3 +8000cfe8: 000a0513 mv a0,s4 +8000cfec: cbcff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000cff0: 920502e3 beqz a0,8000c914 <_vfiprintf_r+0x364> +8000cff4: 939ff06f j 8000c92c <_vfiprintf_r+0x37c> +8000cff8: 00100613 li a2,1 +8000cffc: 00000713 li a4,0 +8000d000: 00048b93 mv s7,s1 +8000d004: e71ff06f j 8000ce74 <_vfiprintf_r+0x8c4> +8000d008: 30078c63 beqz a5,8000d320 <_vfiprintf_r+0xd70> +8000d00c: 04010613 addi a2,sp,64 +8000d010: 00098593 mv a1,s3 +8000d014: 000a0513 mv a0,s4 +8000d018: 03e12623 sw t5,44(sp) +8000d01c: 03f12423 sw t6,40(sp) +8000d020: c88ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000d024: 900514e3 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000d028: 04412703 lw a4,68(sp) +8000d02c: 04812783 lw a5,72(sp) +8000d030: 02c12f03 lw t5,44(sp) +8000d034: 02812f83 lw t6,40(sp) +8000d038: 05410693 addi a3,sp,84 +8000d03c: 00170613 addi a2,a4,1 +8000d040: 00048b93 mv s7,s1 +8000d044: ff8ff06f j 8000c83c <_vfiprintf_r+0x28c> +8000d048: 03c10793 addi a5,sp,60 +8000d04c: 04f12623 sw a5,76(sp) +8000d050: 00200793 li a5,2 +8000d054: 04f12823 sw a5,80(sp) +8000d058: 00100613 li a2,1 +8000d05c: 05410693 addi a3,sp,84 +8000d060: 00060713 mv a4,a2 +8000d064: 00068b93 mv s7,a3 +8000d068: 00170613 addi a2,a4,1 +8000d06c: 008b8693 addi a3,s7,8 +8000d070: 829ff06f j 8000c898 <_vfiprintf_r+0x2e8> +8000d074: 000b0d93 mv s11,s6 +8000d078: b19ff06f j 8000cb90 <_vfiprintf_r+0x5e0> +8000d07c: 01000613 li a2,16 +8000d080: 73b65063 bge a2,s11,8000d7a0 <_vfiprintf_r+0x11f0> +8000d084: 000b8613 mv a2,s7 +8000d088: 01000e93 li t4,16 +8000d08c: 00040b93 mv s7,s0 +8000d090: 00700293 li t0,7 +8000d094: 00098413 mv s0,s3 +8000d098: 03f12423 sw t6,40(sp) +8000d09c: 000d8993 mv s3,s11 +8000d0a0: 000c0d93 mv s11,s8 +8000d0a4: 000a8c13 mv s8,s5 +8000d0a8: 000f0a93 mv s5,t5 +8000d0ac: 01c0006f j 8000d0c8 <_vfiprintf_r+0xb18> +8000d0b0: 00270513 addi a0,a4,2 +8000d0b4: 00860613 addi a2,a2,8 +8000d0b8: 00068713 mv a4,a3 +8000d0bc: ff098993 addi s3,s3,-16 +8000d0c0: 053ede63 bge t4,s3,8000d11c <_vfiprintf_r+0xb6c> +8000d0c4: 00170693 addi a3,a4,1 +8000d0c8: 00812583 lw a1,8(sp) +8000d0cc: 01078793 addi a5,a5,16 +8000d0d0: 01d62223 sw t4,4(a2) +8000d0d4: 00b62023 sw a1,0(a2) +8000d0d8: 04f12423 sw a5,72(sp) +8000d0dc: 04d12223 sw a3,68(sp) +8000d0e0: fcd2d8e3 bge t0,a3,8000d0b0 <_vfiprintf_r+0xb00> +8000d0e4: 08078663 beqz a5,8000d170 <_vfiprintf_r+0xbc0> +8000d0e8: 04010613 addi a2,sp,64 +8000d0ec: 00040593 mv a1,s0 +8000d0f0: 000a0513 mv a0,s4 +8000d0f4: bb4ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000d0f8: 4c051663 bnez a0,8000d5c4 <_vfiprintf_r+0x1014> +8000d0fc: 04412703 lw a4,68(sp) +8000d100: 01000e93 li t4,16 +8000d104: ff098993 addi s3,s3,-16 +8000d108: 04812783 lw a5,72(sp) +8000d10c: 00048613 mv a2,s1 +8000d110: 00170513 addi a0,a4,1 +8000d114: 00700293 li t0,7 +8000d118: fb3ec6e3 blt t4,s3,8000d0c4 <_vfiprintf_r+0xb14> +8000d11c: 02812f83 lw t6,40(sp) +8000d120: 000a8f13 mv t5,s5 +8000d124: 00050593 mv a1,a0 +8000d128: 000c0a93 mv s5,s8 +8000d12c: 000d8c13 mv s8,s11 +8000d130: 00098d93 mv s11,s3 +8000d134: 00040993 mv s3,s0 +8000d138: 000b8413 mv s0,s7 +8000d13c: 00060b93 mv s7,a2 +8000d140: 00812703 lw a4,8(sp) +8000d144: 01b787b3 add a5,a5,s11 +8000d148: 01bba223 sw s11,4(s7) +8000d14c: 00eba023 sw a4,0(s7) +8000d150: 04f12423 sw a5,72(sp) +8000d154: 04b12223 sw a1,68(sp) +8000d158: 00700713 li a4,7 +8000d15c: 1eb74263 blt a4,a1,8000d340 <_vfiprintf_r+0xd90> +8000d160: 008b8b93 addi s7,s7,8 +8000d164: 00158613 addi a2,a1,1 +8000d168: 00058713 mv a4,a1 +8000d16c: e90ff06f j 8000c7fc <_vfiprintf_r+0x24c> +8000d170: 00000713 li a4,0 +8000d174: 00100513 li a0,1 +8000d178: 00048613 mv a2,s1 +8000d17c: f41ff06f j 8000d0bc <_vfiprintf_r+0xb0c> +8000d180: 04012223 sw zero,68(sp) +8000d184: 004b7313 andi t1,s6,4 +8000d188: 0e030263 beqz t1,8000d26c <_vfiprintf_r+0xcbc> +8000d18c: 00412703 lw a4,4(sp) +8000d190: 41970bb3 sub s7,a4,s9 +8000d194: 0d705c63 blez s7,8000d26c <_vfiprintf_r+0xcbc> +8000d198: 00048693 mv a3,s1 +8000d19c: 01000713 li a4,16 +8000d1a0: 04412603 lw a2,68(sp) +8000d1a4: 61775263 bge a4,s7,8000d7a8 <_vfiprintf_r+0x11f8> +8000d1a8: 01000d13 li s10,16 +8000d1ac: 00700d93 li s11,7 +8000d1b0: 0180006f j 8000d1c8 <_vfiprintf_r+0xc18> +8000d1b4: 00260513 addi a0,a2,2 +8000d1b8: 00868693 addi a3,a3,8 +8000d1bc: 00070613 mv a2,a4 +8000d1c0: ff0b8b93 addi s7,s7,-16 +8000d1c4: 057d5a63 bge s10,s7,8000d218 <_vfiprintf_r+0xc68> +8000d1c8: 00812583 lw a1,8(sp) +8000d1cc: 01078793 addi a5,a5,16 +8000d1d0: 00160713 addi a4,a2,1 +8000d1d4: 00b6a023 sw a1,0(a3) +8000d1d8: 01a6a223 sw s10,4(a3) +8000d1dc: 04f12423 sw a5,72(sp) +8000d1e0: 04e12223 sw a4,68(sp) +8000d1e4: fcedd8e3 bge s11,a4,8000d1b4 <_vfiprintf_r+0xc04> +8000d1e8: 06078a63 beqz a5,8000d25c <_vfiprintf_r+0xcac> +8000d1ec: 04010613 addi a2,sp,64 +8000d1f0: 00098593 mv a1,s3 +8000d1f4: 000a0513 mv a0,s4 +8000d1f8: ab0ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000d1fc: f2051863 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000d200: 04412603 lw a2,68(sp) +8000d204: ff0b8b93 addi s7,s7,-16 +8000d208: 04812783 lw a5,72(sp) +8000d20c: 00048693 mv a3,s1 +8000d210: 00160513 addi a0,a2,1 +8000d214: fb7d4ae3 blt s10,s7,8000d1c8 <_vfiprintf_r+0xc18> +8000d218: 00050593 mv a1,a0 +8000d21c: 00812703 lw a4,8(sp) +8000d220: 017787b3 add a5,a5,s7 +8000d224: 0176a223 sw s7,4(a3) +8000d228: 00e6a023 sw a4,0(a3) +8000d22c: 04f12423 sw a5,72(sp) +8000d230: 04b12223 sw a1,68(sp) +8000d234: 00700713 li a4,7 +8000d238: ecb75063 bge a4,a1,8000c8f8 <_vfiprintf_r+0x348> +8000d23c: 02078863 beqz a5,8000d26c <_vfiprintf_r+0xcbc> +8000d240: 04010613 addi a2,sp,64 +8000d244: 00098593 mv a1,s3 +8000d248: 000a0513 mv a0,s4 +8000d24c: a5cff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000d250: ec051e63 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000d254: 04812783 lw a5,72(sp) +8000d258: ea0ff06f j 8000c8f8 <_vfiprintf_r+0x348> +8000d25c: 00100513 li a0,1 +8000d260: 00000613 li a2,0 +8000d264: 00048693 mv a3,s1 +8000d268: f59ff06f j 8000d1c0 <_vfiprintf_r+0xc10> +8000d26c: 00412403 lw s0,4(sp) +8000d270: 01945463 bge s0,s9,8000d278 <_vfiprintf_r+0xcc8> +8000d274: 000c8413 mv s0,s9 +8000d278: 00c12783 lw a5,12(sp) +8000d27c: 008787b3 add a5,a5,s0 +8000d280: 00f12623 sw a5,12(sp) +8000d284: e90ff06f j 8000c914 <_vfiprintf_r+0x364> +8000d288: 34078263 beqz a5,8000d5cc <_vfiprintf_r+0x101c> +8000d28c: 04010613 addi a2,sp,64 +8000d290: 00098593 mv a1,s3 +8000d294: 000a0513 mv a0,s4 +8000d298: a10ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000d29c: e8051863 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000d2a0: 04412603 lw a2,68(sp) +8000d2a4: 04812783 lw a5,72(sp) +8000d2a8: 05410693 addi a3,sp,84 +8000d2ac: 00160613 addi a2,a2,1 +8000d2b0: 00048b93 mv s7,s1 +8000d2b4: df4ff06f j 8000c8a8 <_vfiprintf_r+0x2f8> +8000d2b8: 04012223 sw zero,68(sp) +8000d2bc: 00048b93 mv s7,s1 +8000d2c0: c60ff06f j 8000c720 <_vfiprintf_r+0x170> +8000d2c4: f40a9c63 bnez s5,8000ca1c <_vfiprintf_r+0x46c> +8000d2c8: 000d8b13 mv s6,s11 +8000d2cc: 00000a93 li s5,0 +8000d2d0: 00000d13 li s10,0 +8000d2d4: 0f010413 addi s0,sp,240 +8000d2d8: f58ff06f j 8000ca30 <_vfiprintf_r+0x480> +8000d2dc: 01012683 lw a3,16(sp) +8000d2e0: 010df793 andi a5,s11,16 +8000d2e4: 00468713 addi a4,a3,4 +8000d2e8: 14079863 bnez a5,8000d438 <_vfiprintf_r+0xe88> +8000d2ec: 040df793 andi a5,s11,64 +8000d2f0: 3a078063 beqz a5,8000d690 <_vfiprintf_r+0x10e0> +8000d2f4: 01012783 lw a5,16(sp) +8000d2f8: 00000c93 li s9,0 +8000d2fc: 00e12823 sw a4,16(sp) +8000d300: 0007dd03 lhu s10,0(a5) +8000d304: 00100713 li a4,1 +8000d308: fb8ff06f j 8000cac0 <_vfiprintf_r+0x510> +8000d30c: 05410693 addi a3,sp,84 +8000d310: 00100613 li a2,1 +8000d314: 00000713 li a4,0 +8000d318: 00048b93 mv s7,s1 +8000d31c: d7cff06f j 8000c898 <_vfiprintf_r+0x2e8> +8000d320: 180f8063 beqz t6,8000d4a0 <_vfiprintf_r+0xef0> +8000d324: 03c10793 addi a5,sp,60 +8000d328: 04f12623 sw a5,76(sp) +8000d32c: 00200793 li a5,2 +8000d330: 04f12823 sw a5,80(sp) +8000d334: 00100713 li a4,1 +8000d338: 05410b93 addi s7,sp,84 +8000d33c: d2dff06f j 8000d068 <_vfiprintf_r+0xab8> +8000d340: 22078263 beqz a5,8000d564 <_vfiprintf_r+0xfb4> +8000d344: 04010613 addi a2,sp,64 +8000d348: 00098593 mv a1,s3 +8000d34c: 000a0513 mv a0,s4 +8000d350: 03e12623 sw t5,44(sp) +8000d354: 03f12423 sw t6,40(sp) +8000d358: 950ff0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000d35c: dc051863 bnez a0,8000c92c <_vfiprintf_r+0x37c> +8000d360: 04412703 lw a4,68(sp) +8000d364: 04812783 lw a5,72(sp) +8000d368: 02c12f03 lw t5,44(sp) +8000d36c: 02812f83 lw t6,40(sp) +8000d370: 00048b93 mv s7,s1 +8000d374: 00170613 addi a2,a4,1 +8000d378: c84ff06f j 8000c7fc <_vfiprintf_r+0x24c> +8000d37c: 400df793 andi a5,s11,1024 +8000d380: 03412423 sw s4,40(sp) +8000d384: 03312623 sw s3,44(sp) +8000d388: 000c8a13 mv s4,s9 +8000d38c: 000d0993 mv s3,s10 +8000d390: 00000b13 li s6,0 +8000d394: 01c12d03 lw s10,28(sp) +8000d398: 0f010413 addi s0,sp,240 +8000d39c: 00078c93 mv s9,a5 +8000d3a0: 0240006f j 8000d3c4 <_vfiprintf_r+0xe14> +8000d3a4: 00a00613 li a2,10 +8000d3a8: 00000693 li a3,0 +8000d3ac: 00098513 mv a0,s3 +8000d3b0: 000a0593 mv a1,s4 +8000d3b4: 110030ef jal ra,800104c4 <__udivdi3> +8000d3b8: 300a0e63 beqz s4,8000d6d4 <_vfiprintf_r+0x1124> +8000d3bc: 00050993 mv s3,a0 +8000d3c0: 00058a13 mv s4,a1 +8000d3c4: 00a00613 li a2,10 +8000d3c8: 00000693 li a3,0 +8000d3cc: 00098513 mv a0,s3 +8000d3d0: 000a0593 mv a1,s4 +8000d3d4: 524030ef jal ra,800108f8 <__umoddi3> +8000d3d8: 03050513 addi a0,a0,48 +8000d3dc: fea40fa3 sb a0,-1(s0) +8000d3e0: 001b0b13 addi s6,s6,1 +8000d3e4: fff40413 addi s0,s0,-1 +8000d3e8: fa0c8ee3 beqz s9,8000d3a4 <_vfiprintf_r+0xdf4> +8000d3ec: 000d4683 lbu a3,0(s10) +8000d3f0: fb669ae3 bne a3,s6,8000d3a4 <_vfiprintf_r+0xdf4> +8000d3f4: 0ff00793 li a5,255 +8000d3f8: fafb06e3 beq s6,a5,8000d3a4 <_vfiprintf_r+0xdf4> +8000d3fc: 180a1463 bnez s4,8000d584 <_vfiprintf_r+0xfd4> +8000d400: 00900793 li a5,9 +8000d404: 1937e063 bltu a5,s3,8000d584 <_vfiprintf_r+0xfd4> +8000d408: 0f010793 addi a5,sp,240 +8000d40c: 01a12e23 sw s10,28(sp) +8000d410: 02812a03 lw s4,40(sp) +8000d414: 02c12983 lw s3,44(sp) +8000d418: 40878d33 sub s10,a5,s0 +8000d41c: 000d8b13 mv s6,s11 +8000d420: e10ff06f j 8000ca30 <_vfiprintf_r+0x480> +8000d424: 00158613 addi a2,a1,1 +8000d428: 00850693 addi a3,a0,8 +8000d42c: 00058713 mv a4,a1 +8000d430: 00050b93 mv s7,a0 +8000d434: c6cff06f j 8000c8a0 <_vfiprintf_r+0x2f0> +8000d438: 00e12823 sw a4,16(sp) +8000d43c: 0006ad03 lw s10,0(a3) +8000d440: 00000c93 li s9,0 +8000d444: 00100713 li a4,1 +8000d448: e78ff06f j 8000cac0 <_vfiprintf_r+0x510> +8000d44c: 0006ad03 lw s10,0(a3) +8000d450: 00e12823 sw a4,16(sp) +8000d454: 41fd5c93 srai s9,s10,0x1f +8000d458: 000c8713 mv a4,s9 +8000d45c: d98ff06f j 8000c9f4 <_vfiprintf_r+0x444> +8000d460: 01c12783 lw a5,28(sp) +8000d464: 000c4703 lbu a4,0(s8) +8000d468: ae078863 beqz a5,8000c758 <_vfiprintf_r+0x1a8> +8000d46c: 0007c783 lbu a5,0(a5) +8000d470: ae078463 beqz a5,8000c758 <_vfiprintf_r+0x1a8> +8000d474: 400b6b13 ori s6,s6,1024 +8000d478: ae0ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000d47c: 00c12683 lw a3,12(sp) +8000d480: 41f6d793 srai a5,a3,0x1f +8000d484: 00d72023 sw a3,0(a4) +8000d488: 00f72223 sw a5,4(a4) +8000d48c: a24ff06f j 8000c6b0 <_vfiprintf_r+0x100> +8000d490: 0006ad03 lw s10,0(a3) +8000d494: 00000c93 li s9,0 +8000d498: 00e12823 sw a4,16(sp) +8000d49c: e1cff06f j 8000cab8 <_vfiprintf_r+0x508> +8000d4a0: 00000713 li a4,0 +8000d4a4: 05410693 addi a3,sp,84 +8000d4a8: 00100613 li a2,1 +8000d4ac: 00048b93 mv s7,s1 +8000d4b0: be8ff06f j 8000c898 <_vfiprintf_r+0x2e8> +8000d4b4: 000b0d93 mv s11,s6 +8000d4b8: 819ff06f j 8000ccd0 <_vfiprintf_r+0x720> +8000d4bc: 800157b7 lui a5,0x80015 +8000d4c0: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> +8000d4c4: 00f12c23 sw a5,24(sp) +8000d4c8: 020b7793 andi a5,s6,32 +8000d4cc: 06078063 beqz a5,8000d52c <_vfiprintf_r+0xf7c> +8000d4d0: 01012783 lw a5,16(sp) +8000d4d4: 00778793 addi a5,a5,7 +8000d4d8: ff87f793 andi a5,a5,-8 +8000d4dc: 0007ad03 lw s10,0(a5) +8000d4e0: 0047ac83 lw s9,4(a5) +8000d4e4: 00878793 addi a5,a5,8 +8000d4e8: 00f12823 sw a5,16(sp) +8000d4ec: 001b7693 andi a3,s6,1 +8000d4f0: 00068e63 beqz a3,8000d50c <_vfiprintf_r+0xf5c> +8000d4f4: 019d66b3 or a3,s10,s9 +8000d4f8: 00068a63 beqz a3,8000d50c <_vfiprintf_r+0xf5c> +8000d4fc: 03000693 li a3,48 +8000d500: 02d10e23 sb a3,60(sp) +8000d504: 02e10ea3 sb a4,61(sp) +8000d508: 002b6b13 ori s6,s6,2 +8000d50c: bffb7d93 andi s11,s6,-1025 +8000d510: 00200713 li a4,2 +8000d514: dacff06f j 8000cac0 <_vfiprintf_r+0x510> +8000d518: 800157b7 lui a5,0x80015 +8000d51c: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +8000d520: 00f12c23 sw a5,24(sp) +8000d524: 020b7793 andi a5,s6,32 +8000d528: fa0794e3 bnez a5,8000d4d0 <_vfiprintf_r+0xf20> +8000d52c: 01012603 lw a2,16(sp) +8000d530: 010b7793 andi a5,s6,16 +8000d534: 00460693 addi a3,a2,4 +8000d538: 0a078a63 beqz a5,8000d5ec <_vfiprintf_r+0x103c> +8000d53c: 00062d03 lw s10,0(a2) +8000d540: 00000c93 li s9,0 +8000d544: 00d12823 sw a3,16(sp) +8000d548: fa5ff06f j 8000d4ec <_vfiprintf_r+0xf3c> +8000d54c: 00040513 mv a0,s0 +8000d550: c10fc0ef jal ra,80009960 +8000d554: 00050d13 mv s10,a0 +8000d558: 01b12823 sw s11,16(sp) +8000d55c: 00000a93 li s5,0 +8000d560: cd0ff06f j 8000ca30 <_vfiprintf_r+0x480> +8000d564: 03b14703 lbu a4,59(sp) +8000d568: 18071a63 bnez a4,8000d6fc <_vfiprintf_r+0x114c> +8000d56c: ac0f9ee3 bnez t6,8000d048 <_vfiprintf_r+0xa98> +8000d570: 00000713 li a4,0 +8000d574: 00100613 li a2,1 +8000d578: 05410693 addi a3,sp,84 +8000d57c: 00048b93 mv s7,s1 +8000d580: b18ff06f j 8000c898 <_vfiprintf_r+0x2e8> +8000d584: 02412783 lw a5,36(sp) +8000d588: 02012583 lw a1,32(sp) +8000d58c: 00000b13 li s6,0 +8000d590: 40f40433 sub s0,s0,a5 +8000d594: 00078613 mv a2,a5 +8000d598: 00040513 mv a0,s0 +8000d59c: c50fc0ef jal ra,800099ec +8000d5a0: 001d4583 lbu a1,1(s10) +8000d5a4: 00a00613 li a2,10 +8000d5a8: 00000693 li a3,0 +8000d5ac: 00b03733 snez a4,a1 +8000d5b0: 00098513 mv a0,s3 +8000d5b4: 000a0593 mv a1,s4 +8000d5b8: 00ed0d33 add s10,s10,a4 +8000d5bc: 709020ef jal ra,800104c4 <__udivdi3> +8000d5c0: dfdff06f j 8000d3bc <_vfiprintf_r+0xe0c> +8000d5c4: 00040993 mv s3,s0 +8000d5c8: b64ff06f j 8000c92c <_vfiprintf_r+0x37c> +8000d5cc: 00100713 li a4,1 +8000d5d0: 000d0793 mv a5,s10 +8000d5d4: 04812623 sw s0,76(sp) +8000d5d8: 05a12823 sw s10,80(sp) +8000d5dc: 05a12423 sw s10,72(sp) +8000d5e0: 04e12223 sw a4,68(sp) +8000d5e4: 05410693 addi a3,sp,84 +8000d5e8: afcff06f j 8000c8e4 <_vfiprintf_r+0x334> +8000d5ec: 040b7793 andi a5,s6,64 +8000d5f0: 06078263 beqz a5,8000d654 <_vfiprintf_r+0x10a4> +8000d5f4: 01012783 lw a5,16(sp) +8000d5f8: 00000c93 li s9,0 +8000d5fc: 00d12823 sw a3,16(sp) +8000d600: 0007dd03 lhu s10,0(a5) +8000d604: ee9ff06f j 8000d4ec <_vfiprintf_r+0xf3c> +8000d608: 001c4703 lbu a4,1(s8) +8000d60c: 200b6b13 ori s6,s6,512 +8000d610: 001c0c13 addi s8,s8,1 +8000d614: 944ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000d618: 001c4703 lbu a4,1(s8) +8000d61c: 020b6b13 ori s6,s6,32 +8000d620: 001c0c13 addi s8,s8,1 +8000d624: 934ff06f j 8000c758 <_vfiprintf_r+0x1a8> +8000d628: 00c12783 lw a5,12(sp) +8000d62c: 00f72023 sw a5,0(a4) +8000d630: 880ff06f j 8000c6b0 <_vfiprintf_r+0x100> +8000d634: 00600793 li a5,6 +8000d638: 000a8d13 mv s10,s5 +8000d63c: 0b57ec63 bltu a5,s5,8000d6f4 <_vfiprintf_r+0x1144> +8000d640: 80015e37 lui t3,0x80015 +8000d644: 000d0c93 mv s9,s10 +8000d648: 01b12823 sw s11,16(sp) +8000d64c: ca0e0413 addi s0,t3,-864 # 80014ca0 <__BSS_END__+0xffffe064> +8000d650: 978ff06f j 8000c7c8 <_vfiprintf_r+0x218> +8000d654: 200b7793 andi a5,s6,512 +8000d658: 10078863 beqz a5,8000d768 <_vfiprintf_r+0x11b8> +8000d65c: 01012783 lw a5,16(sp) +8000d660: 00000c93 li s9,0 +8000d664: 00d12823 sw a3,16(sp) +8000d668: 0007cd03 lbu s10,0(a5) +8000d66c: e81ff06f j 8000d4ec <_vfiprintf_r+0xf3c> +8000d670: 200b7793 andi a5,s6,512 +8000d674: 0c078e63 beqz a5,8000d750 <_vfiprintf_r+0x11a0> +8000d678: 01012783 lw a5,16(sp) +8000d67c: 00e12823 sw a4,16(sp) +8000d680: 00078d03 lb s10,0(a5) +8000d684: 41fd5c93 srai s9,s10,0x1f +8000d688: 000c8713 mv a4,s9 +8000d68c: b68ff06f j 8000c9f4 <_vfiprintf_r+0x444> +8000d690: 200df793 andi a5,s11,512 +8000d694: 0a078263 beqz a5,8000d738 <_vfiprintf_r+0x1188> +8000d698: 01012783 lw a5,16(sp) +8000d69c: 00000c93 li s9,0 +8000d6a0: 00e12823 sw a4,16(sp) +8000d6a4: 0007cd03 lbu s10,0(a5) +8000d6a8: 00100713 li a4,1 +8000d6ac: c14ff06f j 8000cac0 <_vfiprintf_r+0x510> +8000d6b0: 200b7793 andi a5,s6,512 +8000d6b4: 06078863 beqz a5,8000d724 <_vfiprintf_r+0x1174> +8000d6b8: 01012783 lw a5,16(sp) +8000d6bc: 00000c93 li s9,0 +8000d6c0: 00e12823 sw a4,16(sp) +8000d6c4: 0007cd03 lbu s10,0(a5) +8000d6c8: bf0ff06f j 8000cab8 <_vfiprintf_r+0x508> +8000d6cc: 00068593 mv a1,a3 +8000d6d0: 8d5ff06f j 8000cfa4 <_vfiprintf_r+0x9f4> +8000d6d4: 00900793 li a5,9 +8000d6d8: cf37e2e3 bltu a5,s3,8000d3bc <_vfiprintf_r+0xe0c> +8000d6dc: d2dff06f j 8000d408 <_vfiprintf_r+0xe58> +8000d6e0: 05410693 addi a3,sp,84 +8000d6e4: 00100613 li a2,1 +8000d6e8: 00000713 li a4,0 +8000d6ec: 00048b93 mv s7,s1 +8000d6f0: 9b0ff06f j 8000c8a0 <_vfiprintf_r+0x2f0> +8000d6f4: 00600d13 li s10,6 +8000d6f8: f49ff06f j 8000d640 <_vfiprintf_r+0x1090> +8000d6fc: 03b10793 addi a5,sp,59 +8000d700: 04f12623 sw a5,76(sp) +8000d704: 00100793 li a5,1 +8000d708: 04f12823 sw a5,80(sp) +8000d70c: 00100613 li a2,1 +8000d710: 05410693 addi a3,sp,84 +8000d714: 918ff06f j 8000c82c <_vfiprintf_r+0x27c> +8000d718: 00c12783 lw a5,12(sp) +8000d71c: 00f71023 sh a5,0(a4) +8000d720: f91fe06f j 8000c6b0 <_vfiprintf_r+0x100> +8000d724: 01012783 lw a5,16(sp) +8000d728: 00000c93 li s9,0 +8000d72c: 00e12823 sw a4,16(sp) +8000d730: 0007ad03 lw s10,0(a5) +8000d734: b84ff06f j 8000cab8 <_vfiprintf_r+0x508> +8000d738: 01012783 lw a5,16(sp) +8000d73c: 00000c93 li s9,0 +8000d740: 00e12823 sw a4,16(sp) +8000d744: 0007ad03 lw s10,0(a5) +8000d748: 00100713 li a4,1 +8000d74c: b74ff06f j 8000cac0 <_vfiprintf_r+0x510> +8000d750: 01012783 lw a5,16(sp) +8000d754: 00e12823 sw a4,16(sp) +8000d758: 0007ad03 lw s10,0(a5) +8000d75c: 41fd5c93 srai s9,s10,0x1f +8000d760: 000c8713 mv a4,s9 +8000d764: a90ff06f j 8000c9f4 <_vfiprintf_r+0x444> +8000d768: 01012783 lw a5,16(sp) +8000d76c: 00000c93 li s9,0 +8000d770: 00d12823 sw a3,16(sp) +8000d774: 0007ad03 lw s10,0(a5) +8000d778: d75ff06f j 8000d4ec <_vfiprintf_r+0xf3c> +8000d77c: 04010613 addi a2,sp,64 +8000d780: 00098593 mv a1,s3 +8000d784: 000a0513 mv a0,s4 +8000d788: d21fe0ef jal ra,8000c4a8 <__sprint_r.part.0> +8000d78c: 9a0ff06f j 8000c92c <_vfiprintf_r+0x37c> +8000d790: 000a8d13 mv s10,s5 +8000d794: 01b12823 sw s11,16(sp) +8000d798: 00000a93 li s5,0 +8000d79c: a94ff06f j 8000ca30 <_vfiprintf_r+0x480> +8000d7a0: 00068593 mv a1,a3 +8000d7a4: 99dff06f j 8000d140 <_vfiprintf_r+0xb90> +8000d7a8: 00160593 addi a1,a2,1 +8000d7ac: a71ff06f j 8000d21c <_vfiprintf_r+0xc6c> +8000d7b0: 000b0d93 mv s11,s6 +8000d7b4: a68ff06f j 8000ca1c <_vfiprintf_r+0x46c> +8000d7b8: fff00793 li a5,-1 +8000d7bc: 00f12623 sw a5,12(sp) +8000d7c0: 978ff06f j 8000c938 <_vfiprintf_r+0x388> +8000d7c4: 00068513 mv a0,a3 +8000d7c8: 00060593 mv a1,a2 +8000d7cc: f0cff06f j 8000ced8 <_vfiprintf_r+0x928> +8000d7d0: 01012783 lw a5,16(sp) +8000d7d4: 0007aa83 lw s5,0(a5) +8000d7d8: 00478793 addi a5,a5,4 +8000d7dc: 000ad463 bgez s5,8000d7e4 <_vfiprintf_r+0x1234> +8000d7e0: fff00a93 li s5,-1 +8000d7e4: 001c4703 lbu a4,1(s8) +8000d7e8: 00f12823 sw a5,16(sp) +8000d7ec: 00068c13 mv s8,a3 +8000d7f0: f69fe06f j 8000c758 <_vfiprintf_r+0x1a8> -8000da4c : -8000da4c: 00050793 mv a5,a0 -8000da50: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -8000da54: 00060693 mv a3,a2 -8000da58: 00058613 mv a2,a1 -8000da5c: 00078593 mv a1,a5 -8000da60: da9fe06f j 8000c808 <_vfiprintf_r> +8000d7f4 : +8000d7f4: 00050793 mv a5,a0 +8000d7f8: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +8000d7fc: 00060693 mv a3,a2 +8000d800: 00058613 mv a2,a1 +8000d804: 00078593 mv a1,a5 +8000d808: da9fe06f j 8000c5b0 <_vfiprintf_r> -8000da64 <__sbprintf>: -8000da64: 00c5d783 lhu a5,12(a1) -8000da68: 0645ae03 lw t3,100(a1) -8000da6c: 00e5d303 lhu t1,14(a1) -8000da70: 01c5a883 lw a7,28(a1) -8000da74: 0245a803 lw a6,36(a1) -8000da78: b8010113 addi sp,sp,-1152 -8000da7c: ffd7f793 andi a5,a5,-3 -8000da80: 40000713 li a4,1024 -8000da84: 46812c23 sw s0,1144(sp) -8000da88: 00f11a23 sh a5,20(sp) -8000da8c: 00058413 mv s0,a1 -8000da90: 07010793 addi a5,sp,112 -8000da94: 00810593 addi a1,sp,8 -8000da98: 46912a23 sw s1,1140(sp) -8000da9c: 47212823 sw s2,1136(sp) -8000daa0: 46112e23 sw ra,1148(sp) -8000daa4: 00050913 mv s2,a0 -8000daa8: 07c12623 sw t3,108(sp) -8000daac: 00611b23 sh t1,22(sp) -8000dab0: 03112223 sw a7,36(sp) -8000dab4: 03012623 sw a6,44(sp) -8000dab8: 00f12423 sw a5,8(sp) -8000dabc: 00f12c23 sw a5,24(sp) -8000dac0: 00e12823 sw a4,16(sp) -8000dac4: 00e12e23 sw a4,28(sp) -8000dac8: 02012023 sw zero,32(sp) -8000dacc: d3dfe0ef jal ra,8000c808 <_vfiprintf_r> -8000dad0: 00050493 mv s1,a0 -8000dad4: 02055c63 bgez a0,8000db0c <__sbprintf+0xa8> -8000dad8: 01415783 lhu a5,20(sp) -8000dadc: 0407f793 andi a5,a5,64 -8000dae0: 00078863 beqz a5,8000daf0 <__sbprintf+0x8c> -8000dae4: 00c45783 lhu a5,12(s0) -8000dae8: 0407e793 ori a5,a5,64 -8000daec: 00f41623 sh a5,12(s0) -8000daf0: 47c12083 lw ra,1148(sp) -8000daf4: 47812403 lw s0,1144(sp) -8000daf8: 47012903 lw s2,1136(sp) -8000dafc: 00048513 mv a0,s1 -8000db00: 47412483 lw s1,1140(sp) -8000db04: 48010113 addi sp,sp,1152 -8000db08: 00008067 ret -8000db0c: 00810593 addi a1,sp,8 -8000db10: 00090513 mv a0,s2 -8000db14: a65f60ef jal ra,80004578 <_fflush_r> -8000db18: fc0500e3 beqz a0,8000dad8 <__sbprintf+0x74> -8000db1c: fff00493 li s1,-1 -8000db20: fb9ff06f j 8000dad8 <__sbprintf+0x74> +8000d80c <__sbprintf>: +8000d80c: 00c5d783 lhu a5,12(a1) +8000d810: 0645ae03 lw t3,100(a1) +8000d814: 00e5d303 lhu t1,14(a1) +8000d818: 01c5a883 lw a7,28(a1) +8000d81c: 0245a803 lw a6,36(a1) +8000d820: b8010113 addi sp,sp,-1152 +8000d824: ffd7f793 andi a5,a5,-3 +8000d828: 40000713 li a4,1024 +8000d82c: 46812c23 sw s0,1144(sp) +8000d830: 00f11a23 sh a5,20(sp) +8000d834: 00058413 mv s0,a1 +8000d838: 07010793 addi a5,sp,112 +8000d83c: 00810593 addi a1,sp,8 +8000d840: 46912a23 sw s1,1140(sp) +8000d844: 47212823 sw s2,1136(sp) +8000d848: 46112e23 sw ra,1148(sp) +8000d84c: 00050913 mv s2,a0 +8000d850: 07c12623 sw t3,108(sp) +8000d854: 00611b23 sh t1,22(sp) +8000d858: 03112223 sw a7,36(sp) +8000d85c: 03012623 sw a6,44(sp) +8000d860: 00f12423 sw a5,8(sp) +8000d864: 00f12c23 sw a5,24(sp) +8000d868: 00e12823 sw a4,16(sp) +8000d86c: 00e12e23 sw a4,28(sp) +8000d870: 02012023 sw zero,32(sp) +8000d874: d3dfe0ef jal ra,8000c5b0 <_vfiprintf_r> +8000d878: 00050493 mv s1,a0 +8000d87c: 02055c63 bgez a0,8000d8b4 <__sbprintf+0xa8> +8000d880: 01415783 lhu a5,20(sp) +8000d884: 0407f793 andi a5,a5,64 +8000d888: 00078863 beqz a5,8000d898 <__sbprintf+0x8c> +8000d88c: 00c45783 lhu a5,12(s0) +8000d890: 0407e793 ori a5,a5,64 +8000d894: 00f41623 sh a5,12(s0) +8000d898: 47c12083 lw ra,1148(sp) +8000d89c: 47812403 lw s0,1144(sp) +8000d8a0: 47012903 lw s2,1136(sp) +8000d8a4: 00048513 mv a0,s1 +8000d8a8: 47412483 lw s1,1140(sp) +8000d8ac: 48010113 addi sp,sp,1152 +8000d8b0: 00008067 ret +8000d8b4: 00810593 addi a1,sp,8 +8000d8b8: 00090513 mv a0,s2 +8000d8bc: bb1f60ef jal ra,8000446c <_fflush_r> +8000d8c0: fc0500e3 beqz a0,8000d880 <__sbprintf+0x74> +8000d8c4: fff00493 li s1,-1 +8000d8c8: fb9ff06f j 8000d880 <__sbprintf+0x74> -8000db24 <_wctomb_r>: -8000db24: ea01a303 lw t1,-352(gp) # 800166a8 <__global_locale+0xe0> -8000db28: 00030067 jr t1 +8000d8cc <_write_r>: +8000d8cc: ff010113 addi sp,sp,-16 +8000d8d0: 00058713 mv a4,a1 +8000d8d4: 00812423 sw s0,8(sp) +8000d8d8: 00912223 sw s1,4(sp) +8000d8dc: 00060593 mv a1,a2 +8000d8e0: 00050413 mv s0,a0 +8000d8e4: 00068613 mv a2,a3 +8000d8e8: 00070513 mv a0,a4 +8000d8ec: 00112623 sw ra,12(sp) +8000d8f0: 4201a823 sw zero,1072(gp) # 80016c38 +8000d8f4: b89f20ef jal ra,8000047c <_write> +8000d8f8: fff00793 li a5,-1 +8000d8fc: 00f50c63 beq a0,a5,8000d914 <_write_r+0x48> +8000d900: 00c12083 lw ra,12(sp) +8000d904: 00812403 lw s0,8(sp) +8000d908: 00412483 lw s1,4(sp) +8000d90c: 01010113 addi sp,sp,16 +8000d910: 00008067 ret +8000d914: 4301a783 lw a5,1072(gp) # 80016c38 +8000d918: fe0784e3 beqz a5,8000d900 <_write_r+0x34> +8000d91c: 00c12083 lw ra,12(sp) +8000d920: 00f42023 sw a5,0(s0) +8000d924: 00812403 lw s0,8(sp) +8000d928: 00412483 lw s1,4(sp) +8000d92c: 01010113 addi sp,sp,16 +8000d930: 00008067 ret -8000db2c <__ascii_wctomb>: -8000db2c: 02058463 beqz a1,8000db54 <__ascii_wctomb+0x28> -8000db30: 0ff00793 li a5,255 -8000db34: 00c7e863 bltu a5,a2,8000db44 <__ascii_wctomb+0x18> -8000db38: 00c58023 sb a2,0(a1) -8000db3c: 00100513 li a0,1 -8000db40: 00008067 ret -8000db44: 08a00793 li a5,138 -8000db48: 00f52023 sw a5,0(a0) -8000db4c: fff00513 li a0,-1 -8000db50: 00008067 ret -8000db54: 00000513 li a0,0 -8000db58: 00008067 ret +8000d934 <__register_exitproc>: +8000d934: 3501a703 lw a4,848(gp) # 80016b58 <_global_impure_ptr> +8000d938: 14872783 lw a5,328(a4) +8000d93c: 04078c63 beqz a5,8000d994 <__register_exitproc+0x60> +8000d940: 0047a703 lw a4,4(a5) +8000d944: 01f00813 li a6,31 +8000d948: 06e84e63 blt a6,a4,8000d9c4 <__register_exitproc+0x90> +8000d94c: 00271813 slli a6,a4,0x2 +8000d950: 02050663 beqz a0,8000d97c <__register_exitproc+0x48> +8000d954: 01078333 add t1,a5,a6 +8000d958: 08c32423 sw a2,136(t1) +8000d95c: 1887a883 lw a7,392(a5) +8000d960: 00100613 li a2,1 +8000d964: 00e61633 sll a2,a2,a4 +8000d968: 00c8e8b3 or a7,a7,a2 +8000d96c: 1917a423 sw a7,392(a5) +8000d970: 10d32423 sw a3,264(t1) +8000d974: 00200693 li a3,2 +8000d978: 02d50463 beq a0,a3,8000d9a0 <__register_exitproc+0x6c> +8000d97c: 00170713 addi a4,a4,1 +8000d980: 00e7a223 sw a4,4(a5) +8000d984: 010787b3 add a5,a5,a6 +8000d988: 00b7a423 sw a1,8(a5) +8000d98c: 00000513 li a0,0 +8000d990: 00008067 ret +8000d994: 14c70793 addi a5,a4,332 +8000d998: 14f72423 sw a5,328(a4) +8000d99c: fa5ff06f j 8000d940 <__register_exitproc+0xc> +8000d9a0: 18c7a683 lw a3,396(a5) +8000d9a4: 00170713 addi a4,a4,1 +8000d9a8: 00e7a223 sw a4,4(a5) +8000d9ac: 00c6e633 or a2,a3,a2 +8000d9b0: 18c7a623 sw a2,396(a5) +8000d9b4: 010787b3 add a5,a5,a6 +8000d9b8: 00b7a423 sw a1,8(a5) +8000d9bc: 00000513 li a0,0 +8000d9c0: 00008067 ret +8000d9c4: fff00513 li a0,-1 +8000d9c8: 00008067 ret -8000db5c <_write_r>: -8000db5c: ff010113 addi sp,sp,-16 -8000db60: 00058713 mv a4,a1 -8000db64: 00812423 sw s0,8(sp) -8000db68: 00912223 sw s1,4(sp) -8000db6c: 00060593 mv a1,a2 -8000db70: 00050413 mv s0,a0 -8000db74: 00068613 mv a2,a3 -8000db78: 00070513 mv a0,a4 -8000db7c: 00112623 sw ra,12(sp) -8000db80: 4201a223 sw zero,1060(gp) # 80016c2c -8000db84: 941f20ef jal ra,800004c4 <_write> -8000db88: fff00793 li a5,-1 -8000db8c: 00f50c63 beq a0,a5,8000dba4 <_write_r+0x48> -8000db90: 00c12083 lw ra,12(sp) -8000db94: 00812403 lw s0,8(sp) -8000db98: 00412483 lw s1,4(sp) -8000db9c: 01010113 addi sp,sp,16 -8000dba0: 00008067 ret -8000dba4: 4241a783 lw a5,1060(gp) # 80016c2c -8000dba8: fe0784e3 beqz a5,8000db90 <_write_r+0x34> -8000dbac: 00c12083 lw ra,12(sp) -8000dbb0: 00f42023 sw a5,0(s0) -8000dbb4: 00812403 lw s0,8(sp) -8000dbb8: 00412483 lw s1,4(sp) -8000dbbc: 01010113 addi sp,sp,16 -8000dbc0: 00008067 ret +8000d9cc <_calloc_r>: +8000d9cc: 02c585b3 mul a1,a1,a2 +8000d9d0: ff010113 addi sp,sp,-16 +8000d9d4: 00812423 sw s0,8(sp) +8000d9d8: 00112623 sw ra,12(sp) +8000d9dc: 9ccfa0ef jal ra,80007ba8 <_malloc_r> +8000d9e0: 00050413 mv s0,a0 +8000d9e4: 02050863 beqz a0,8000da14 <_calloc_r+0x48> +8000d9e8: ffc52603 lw a2,-4(a0) +8000d9ec: 02400713 li a4,36 +8000d9f0: ffc67613 andi a2,a2,-4 +8000d9f4: ffc60613 addi a2,a2,-4 +8000d9f8: 06c76063 bltu a4,a2,8000da58 <_calloc_r+0x8c> +8000d9fc: 01300693 li a3,19 +8000da00: 00050793 mv a5,a0 +8000da04: 02c6e263 bltu a3,a2,8000da28 <_calloc_r+0x5c> +8000da08: 0007a023 sw zero,0(a5) +8000da0c: 0007a223 sw zero,4(a5) +8000da10: 0007a423 sw zero,8(a5) +8000da14: 00c12083 lw ra,12(sp) +8000da18: 00040513 mv a0,s0 +8000da1c: 00812403 lw s0,8(sp) +8000da20: 01010113 addi sp,sp,16 +8000da24: 00008067 ret +8000da28: 00052023 sw zero,0(a0) +8000da2c: 00052223 sw zero,4(a0) +8000da30: 01b00793 li a5,27 +8000da34: 04c7f063 bgeu a5,a2,8000da74 <_calloc_r+0xa8> +8000da38: 00052423 sw zero,8(a0) +8000da3c: 00052623 sw zero,12(a0) +8000da40: 01050793 addi a5,a0,16 +8000da44: fce612e3 bne a2,a4,8000da08 <_calloc_r+0x3c> +8000da48: 00052823 sw zero,16(a0) +8000da4c: 01850793 addi a5,a0,24 +8000da50: 00052a23 sw zero,20(a0) +8000da54: fb5ff06f j 8000da08 <_calloc_r+0x3c> +8000da58: 00000593 li a1,0 +8000da5c: 9b9fa0ef jal ra,80008414 +8000da60: 00c12083 lw ra,12(sp) +8000da64: 00040513 mv a0,s0 +8000da68: 00812403 lw s0,8(sp) +8000da6c: 01010113 addi sp,sp,16 +8000da70: 00008067 ret +8000da74: 00850793 addi a5,a0,8 +8000da78: f91ff06f j 8000da08 <_calloc_r+0x3c> -8000dbc4 <_calloc_r>: -8000dbc4: 02c585b3 mul a1,a1,a2 -8000dbc8: ff010113 addi sp,sp,-16 -8000dbcc: 00812423 sw s0,8(sp) -8000dbd0: 00112623 sw ra,12(sp) -8000dbd4: 91cfa0ef jal ra,80007cf0 <_malloc_r> -8000dbd8: 00050413 mv s0,a0 -8000dbdc: 02050863 beqz a0,8000dc0c <_calloc_r+0x48> -8000dbe0: ffc52603 lw a2,-4(a0) -8000dbe4: 02400713 li a4,36 -8000dbe8: ffc67613 andi a2,a2,-4 -8000dbec: ffc60613 addi a2,a2,-4 -8000dbf0: 06c76063 bltu a4,a2,8000dc50 <_calloc_r+0x8c> -8000dbf4: 01300693 li a3,19 -8000dbf8: 00050793 mv a5,a0 -8000dbfc: 02c6e263 bltu a3,a2,8000dc20 <_calloc_r+0x5c> -8000dc00: 0007a023 sw zero,0(a5) -8000dc04: 0007a223 sw zero,4(a5) -8000dc08: 0007a423 sw zero,8(a5) -8000dc0c: 00c12083 lw ra,12(sp) -8000dc10: 00040513 mv a0,s0 -8000dc14: 00812403 lw s0,8(sp) -8000dc18: 01010113 addi sp,sp,16 -8000dc1c: 00008067 ret -8000dc20: 00052023 sw zero,0(a0) -8000dc24: 00052223 sw zero,4(a0) -8000dc28: 01b00793 li a5,27 -8000dc2c: 04c7f063 bgeu a5,a2,8000dc6c <_calloc_r+0xa8> -8000dc30: 00052423 sw zero,8(a0) -8000dc34: 00052623 sw zero,12(a0) -8000dc38: 01050793 addi a5,a0,16 -8000dc3c: fce612e3 bne a2,a4,8000dc00 <_calloc_r+0x3c> -8000dc40: 00052823 sw zero,16(a0) -8000dc44: 01850793 addi a5,a0,24 -8000dc48: 00052a23 sw zero,20(a0) -8000dc4c: fb5ff06f j 8000dc00 <_calloc_r+0x3c> -8000dc50: 00000593 li a1,0 -8000dc54: ee4f30ef jal ra,80001338 -8000dc58: 00c12083 lw ra,12(sp) -8000dc5c: 00040513 mv a0,s0 -8000dc60: 00812403 lw s0,8(sp) -8000dc64: 01010113 addi sp,sp,16 -8000dc68: 00008067 ret -8000dc6c: 00850793 addi a5,a0,8 -8000dc70: f91ff06f j 8000dc00 <_calloc_r+0x3c> +8000da7c <_close_r>: +8000da7c: ff010113 addi sp,sp,-16 +8000da80: 00812423 sw s0,8(sp) +8000da84: 00912223 sw s1,4(sp) +8000da88: 00050413 mv s0,a0 +8000da8c: 00058513 mv a0,a1 +8000da90: 00112623 sw ra,12(sp) +8000da94: 4201a823 sw zero,1072(gp) # 80016c38 +8000da98: ff4f20ef jal ra,8000028c <_close> +8000da9c: fff00793 li a5,-1 +8000daa0: 00f50c63 beq a0,a5,8000dab8 <_close_r+0x3c> +8000daa4: 00c12083 lw ra,12(sp) +8000daa8: 00812403 lw s0,8(sp) +8000daac: 00412483 lw s1,4(sp) +8000dab0: 01010113 addi sp,sp,16 +8000dab4: 00008067 ret +8000dab8: 4301a783 lw a5,1072(gp) # 80016c38 +8000dabc: fe0784e3 beqz a5,8000daa4 <_close_r+0x28> +8000dac0: 00c12083 lw ra,12(sp) +8000dac4: 00f42023 sw a5,0(s0) +8000dac8: 00812403 lw s0,8(sp) +8000dacc: 00412483 lw s1,4(sp) +8000dad0: 01010113 addi sp,sp,16 +8000dad4: 00008067 ret -8000dc74 <_close_r>: -8000dc74: ff010113 addi sp,sp,-16 -8000dc78: 00812423 sw s0,8(sp) -8000dc7c: 00912223 sw s1,4(sp) -8000dc80: 00050413 mv s0,a0 -8000dc84: 00058513 mv a0,a1 -8000dc88: 00112623 sw ra,12(sp) -8000dc8c: 4201a223 sw zero,1060(gp) # 80016c2c -8000dc90: e30f20ef jal ra,800002c0 <_close> -8000dc94: fff00793 li a5,-1 -8000dc98: 00f50c63 beq a0,a5,8000dcb0 <_close_r+0x3c> -8000dc9c: 00c12083 lw ra,12(sp) -8000dca0: 00812403 lw s0,8(sp) -8000dca4: 00412483 lw s1,4(sp) -8000dca8: 01010113 addi sp,sp,16 -8000dcac: 00008067 ret -8000dcb0: 4241a783 lw a5,1060(gp) # 80016c2c -8000dcb4: fe0784e3 beqz a5,8000dc9c <_close_r+0x28> -8000dcb8: 00c12083 lw ra,12(sp) -8000dcbc: 00f42023 sw a5,0(s0) -8000dcc0: 00812403 lw s0,8(sp) -8000dcc4: 00412483 lw s1,4(sp) -8000dcc8: 01010113 addi sp,sp,16 -8000dccc: 00008067 ret +8000dad8 <_fclose_r>: +8000dad8: ff010113 addi sp,sp,-16 +8000dadc: 00112623 sw ra,12(sp) +8000dae0: 00812423 sw s0,8(sp) +8000dae4: 00912223 sw s1,4(sp) +8000dae8: 01212023 sw s2,0(sp) +8000daec: 02058063 beqz a1,8000db0c <_fclose_r+0x34> +8000daf0: 00058413 mv s0,a1 +8000daf4: 00050493 mv s1,a0 +8000daf8: 00050663 beqz a0,8000db04 <_fclose_r+0x2c> +8000dafc: 03852783 lw a5,56(a0) +8000db00: 0a078c63 beqz a5,8000dbb8 <_fclose_r+0xe0> +8000db04: 00c41783 lh a5,12(s0) +8000db08: 02079263 bnez a5,8000db2c <_fclose_r+0x54> +8000db0c: 00c12083 lw ra,12(sp) +8000db10: 00812403 lw s0,8(sp) +8000db14: 00000913 li s2,0 +8000db18: 00412483 lw s1,4(sp) +8000db1c: 00090513 mv a0,s2 +8000db20: 00012903 lw s2,0(sp) +8000db24: 01010113 addi sp,sp,16 +8000db28: 00008067 ret +8000db2c: 00040593 mv a1,s0 +8000db30: 00048513 mv a0,s1 +8000db34: edcf60ef jal ra,80004210 <__sflush_r> +8000db38: 02c42783 lw a5,44(s0) +8000db3c: 00050913 mv s2,a0 +8000db40: 00078a63 beqz a5,8000db54 <_fclose_r+0x7c> +8000db44: 01c42583 lw a1,28(s0) +8000db48: 00048513 mv a0,s1 +8000db4c: 000780e7 jalr a5 +8000db50: 06054c63 bltz a0,8000dbc8 <_fclose_r+0xf0> +8000db54: 00c45783 lhu a5,12(s0) +8000db58: 0807f793 andi a5,a5,128 +8000db5c: 06079e63 bnez a5,8000dbd8 <_fclose_r+0x100> +8000db60: 03042583 lw a1,48(s0) +8000db64: 00058c63 beqz a1,8000db7c <_fclose_r+0xa4> +8000db68: 04040793 addi a5,s0,64 +8000db6c: 00f58663 beq a1,a5,8000db78 <_fclose_r+0xa0> +8000db70: 00048513 mv a0,s1 +8000db74: e61f60ef jal ra,800049d4 <_free_r> +8000db78: 02042823 sw zero,48(s0) +8000db7c: 04442583 lw a1,68(s0) +8000db80: 00058863 beqz a1,8000db90 <_fclose_r+0xb8> +8000db84: 00048513 mv a0,s1 +8000db88: e4df60ef jal ra,800049d4 <_free_r> +8000db8c: 04042223 sw zero,68(s0) +8000db90: c89f60ef jal ra,80004818 <__sfp_lock_acquire> +8000db94: 00041623 sh zero,12(s0) +8000db98: c85f60ef jal ra,8000481c <__sfp_lock_release> +8000db9c: 00c12083 lw ra,12(sp) +8000dba0: 00812403 lw s0,8(sp) +8000dba4: 00412483 lw s1,4(sp) +8000dba8: 00090513 mv a0,s2 +8000dbac: 00012903 lw s2,0(sp) +8000dbb0: 01010113 addi sp,sp,16 +8000dbb4: 00008067 ret +8000dbb8: c51f60ef jal ra,80004808 <__sinit> +8000dbbc: 00c41783 lh a5,12(s0) +8000dbc0: f40786e3 beqz a5,8000db0c <_fclose_r+0x34> +8000dbc4: f69ff06f j 8000db2c <_fclose_r+0x54> +8000dbc8: 00c45783 lhu a5,12(s0) +8000dbcc: fff00913 li s2,-1 +8000dbd0: 0807f793 andi a5,a5,128 +8000dbd4: f80786e3 beqz a5,8000db60 <_fclose_r+0x88> +8000dbd8: 01042583 lw a1,16(s0) +8000dbdc: 00048513 mv a0,s1 +8000dbe0: df5f60ef jal ra,800049d4 <_free_r> +8000dbe4: f7dff06f j 8000db60 <_fclose_r+0x88> -8000dcd0 <_fclose_r>: -8000dcd0: ff010113 addi sp,sp,-16 -8000dcd4: 00112623 sw ra,12(sp) -8000dcd8: 00812423 sw s0,8(sp) -8000dcdc: 00912223 sw s1,4(sp) -8000dce0: 01212023 sw s2,0(sp) -8000dce4: 02058063 beqz a1,8000dd04 <_fclose_r+0x34> -8000dce8: 00058413 mv s0,a1 -8000dcec: 00050493 mv s1,a0 -8000dcf0: 00050663 beqz a0,8000dcfc <_fclose_r+0x2c> -8000dcf4: 03852783 lw a5,56(a0) -8000dcf8: 0a078c63 beqz a5,8000ddb0 <_fclose_r+0xe0> -8000dcfc: 00c41783 lh a5,12(s0) -8000dd00: 02079263 bnez a5,8000dd24 <_fclose_r+0x54> -8000dd04: 00c12083 lw ra,12(sp) -8000dd08: 00812403 lw s0,8(sp) -8000dd0c: 00000913 li s2,0 -8000dd10: 00412483 lw s1,4(sp) -8000dd14: 00090513 mv a0,s2 -8000dd18: 00012903 lw s2,0(sp) -8000dd1c: 01010113 addi sp,sp,16 -8000dd20: 00008067 ret -8000dd24: 00040593 mv a1,s0 -8000dd28: 00048513 mv a0,s1 -8000dd2c: df0f60ef jal ra,8000431c <__sflush_r> -8000dd30: 02c42783 lw a5,44(s0) -8000dd34: 00050913 mv s2,a0 -8000dd38: 00078a63 beqz a5,8000dd4c <_fclose_r+0x7c> -8000dd3c: 01c42583 lw a1,28(s0) -8000dd40: 00048513 mv a0,s1 -8000dd44: 000780e7 jalr a5 -8000dd48: 06054c63 bltz a0,8000ddc0 <_fclose_r+0xf0> -8000dd4c: 00c45783 lhu a5,12(s0) -8000dd50: 0807f793 andi a5,a5,128 -8000dd54: 06079e63 bnez a5,8000ddd0 <_fclose_r+0x100> -8000dd58: 03042583 lw a1,48(s0) -8000dd5c: 00058c63 beqz a1,8000dd74 <_fclose_r+0xa4> -8000dd60: 04040793 addi a5,s0,64 -8000dd64: 00f58663 beq a1,a5,8000dd70 <_fclose_r+0xa0> -8000dd68: 00048513 mv a0,s1 -8000dd6c: d19f60ef jal ra,80004a84 <_free_r> -8000dd70: 02042823 sw zero,48(s0) -8000dd74: 04442583 lw a1,68(s0) -8000dd78: 00058863 beqz a1,8000dd88 <_fclose_r+0xb8> -8000dd7c: 00048513 mv a0,s1 -8000dd80: d05f60ef jal ra,80004a84 <_free_r> -8000dd84: 04042223 sw zero,68(s0) -8000dd88: b9df60ef jal ra,80004924 <__sfp_lock_acquire> -8000dd8c: 00041623 sh zero,12(s0) -8000dd90: b99f60ef jal ra,80004928 <__sfp_lock_release> -8000dd94: 00c12083 lw ra,12(sp) -8000dd98: 00812403 lw s0,8(sp) -8000dd9c: 00412483 lw s1,4(sp) -8000dda0: 00090513 mv a0,s2 -8000dda4: 00012903 lw s2,0(sp) -8000dda8: 01010113 addi sp,sp,16 -8000ddac: 00008067 ret -8000ddb0: b65f60ef jal ra,80004914 <__sinit> -8000ddb4: 00c41783 lh a5,12(s0) -8000ddb8: f40786e3 beqz a5,8000dd04 <_fclose_r+0x34> -8000ddbc: f69ff06f j 8000dd24 <_fclose_r+0x54> -8000ddc0: 00c45783 lhu a5,12(s0) -8000ddc4: fff00913 li s2,-1 -8000ddc8: 0807f793 andi a5,a5,128 -8000ddcc: f80786e3 beqz a5,8000dd58 <_fclose_r+0x88> -8000ddd0: 01042583 lw a1,16(s0) -8000ddd4: 00048513 mv a0,s1 -8000ddd8: cadf60ef jal ra,80004a84 <_free_r> -8000dddc: f7dff06f j 8000dd58 <_fclose_r+0x88> +8000dbe8 : +8000dbe8: 00050593 mv a1,a0 +8000dbec: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +8000dbf0: ee9ff06f j 8000dad8 <_fclose_r> -8000dde0 : -8000dde0: 00050593 mv a1,a0 -8000dde4: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -8000dde8: ee9ff06f j 8000dcd0 <_fclose_r> +8000dbf4 <__fputwc>: +8000dbf4: fd010113 addi sp,sp,-48 +8000dbf8: 02812423 sw s0,40(sp) +8000dbfc: 01312e23 sw s3,28(sp) +8000dc00: 01612823 sw s6,16(sp) +8000dc04: 02112623 sw ra,44(sp) +8000dc08: 02912223 sw s1,36(sp) +8000dc0c: 03212023 sw s2,32(sp) +8000dc10: 01412c23 sw s4,24(sp) +8000dc14: 01512a23 sw s5,20(sp) +8000dc18: 00050b13 mv s6,a0 +8000dc1c: 00058993 mv s3,a1 +8000dc20: 00060413 mv s0,a2 +8000dc24: 788000ef jal ra,8000e3ac <__locale_mb_cur_max> +8000dc28: 00100793 li a5,1 +8000dc2c: 02f51063 bne a0,a5,8000dc4c <__fputwc+0x58> +8000dc30: fff98793 addi a5,s3,-1 +8000dc34: 0fe00713 li a4,254 +8000dc38: 00f76a63 bltu a4,a5,8000dc4c <__fputwc+0x58> +8000dc3c: 0ff9f713 andi a4,s3,255 +8000dc40: 00e10623 sb a4,12(sp) +8000dc44: 00100913 li s2,1 +8000dc48: 02c0006f j 8000dc74 <__fputwc+0x80> +8000dc4c: 05c40693 addi a3,s0,92 +8000dc50: 00098613 mv a2,s3 +8000dc54: 00c10593 addi a1,sp,12 +8000dc58: 000b0513 mv a0,s6 +8000dc5c: 730020ef jal ra,8001038c <_wcrtomb_r> +8000dc60: fff00793 li a5,-1 +8000dc64: 00050913 mv s2,a0 +8000dc68: 0af50463 beq a0,a5,8000dd10 <__fputwc+0x11c> +8000dc6c: 08050e63 beqz a0,8000dd08 <__fputwc+0x114> +8000dc70: 00c14703 lbu a4,12(sp) +8000dc74: 00000493 li s1,0 +8000dc78: fff00a13 li s4,-1 +8000dc7c: 00a00a93 li s5,10 +8000dc80: 0280006f j 8000dca8 <__fputwc+0xb4> +8000dc84: 00042783 lw a5,0(s0) +8000dc88: 00178693 addi a3,a5,1 +8000dc8c: 00d42023 sw a3,0(s0) +8000dc90: 00e78023 sb a4,0(a5) +8000dc94: 00148493 addi s1,s1,1 +8000dc98: 00c10793 addi a5,sp,12 +8000dc9c: 009787b3 add a5,a5,s1 +8000dca0: 0724f463 bgeu s1,s2,8000dd08 <__fputwc+0x114> +8000dca4: 0007c703 lbu a4,0(a5) +8000dca8: 00842783 lw a5,8(s0) +8000dcac: fff78793 addi a5,a5,-1 +8000dcb0: 00f42423 sw a5,8(s0) +8000dcb4: fc07d8e3 bgez a5,8000dc84 <__fputwc+0x90> +8000dcb8: 01842683 lw a3,24(s0) +8000dcbc: 00070593 mv a1,a4 +8000dcc0: 00040613 mv a2,s0 +8000dcc4: 000b0513 mv a0,s6 +8000dcc8: 00d7c463 blt a5,a3,8000dcd0 <__fputwc+0xdc> +8000dccc: fb571ce3 bne a4,s5,8000dc84 <__fputwc+0x90> +8000dcd0: 524020ef jal ra,800101f4 <__swbuf_r> +8000dcd4: fd4510e3 bne a0,s4,8000dc94 <__fputwc+0xa0> +8000dcd8: fff00913 li s2,-1 +8000dcdc: 02c12083 lw ra,44(sp) +8000dce0: 02812403 lw s0,40(sp) +8000dce4: 02412483 lw s1,36(sp) +8000dce8: 01c12983 lw s3,28(sp) +8000dcec: 01812a03 lw s4,24(sp) +8000dcf0: 01412a83 lw s5,20(sp) +8000dcf4: 01012b03 lw s6,16(sp) +8000dcf8: 00090513 mv a0,s2 +8000dcfc: 02012903 lw s2,32(sp) +8000dd00: 03010113 addi sp,sp,48 +8000dd04: 00008067 ret +8000dd08: 00098913 mv s2,s3 +8000dd0c: fd1ff06f j 8000dcdc <__fputwc+0xe8> +8000dd10: 00c45783 lhu a5,12(s0) +8000dd14: 0407e793 ori a5,a5,64 +8000dd18: 00f41623 sh a5,12(s0) +8000dd1c: fc1ff06f j 8000dcdc <__fputwc+0xe8> -8000ddec <__fputwc>: -8000ddec: fd010113 addi sp,sp,-48 -8000ddf0: 02812423 sw s0,40(sp) -8000ddf4: 01312e23 sw s3,28(sp) -8000ddf8: 01612823 sw s6,16(sp) -8000ddfc: 02112623 sw ra,44(sp) -8000de00: 02912223 sw s1,36(sp) -8000de04: 03212023 sw s2,32(sp) -8000de08: 01412c23 sw s4,24(sp) -8000de0c: 01512a23 sw s5,20(sp) -8000de10: 00050b13 mv s6,a0 -8000de14: 00058993 mv s3,a1 -8000de18: 00060413 mv s0,a2 -8000de1c: cc9f90ef jal ra,80007ae4 <__locale_mb_cur_max> -8000de20: 00100793 li a5,1 -8000de24: 02f51063 bne a0,a5,8000de44 <__fputwc+0x58> -8000de28: fff98793 addi a5,s3,-1 -8000de2c: 0fe00713 li a4,254 -8000de30: 00f76a63 bltu a4,a5,8000de44 <__fputwc+0x58> -8000de34: 0ff9f713 andi a4,s3,255 -8000de38: 00e10623 sb a4,12(sp) -8000de3c: 00100913 li s2,1 -8000de40: 02c0006f j 8000de6c <__fputwc+0x80> -8000de44: 05c40693 addi a3,s0,92 -8000de48: 00098613 mv a2,s3 -8000de4c: 00c10593 addi a1,sp,12 -8000de50: 000b0513 mv a0,s6 -8000de54: 4ac020ef jal ra,80010300 <_wcrtomb_r> -8000de58: fff00793 li a5,-1 -8000de5c: 00050913 mv s2,a0 -8000de60: 0af50463 beq a0,a5,8000df08 <__fputwc+0x11c> -8000de64: 08050e63 beqz a0,8000df00 <__fputwc+0x114> -8000de68: 00c14703 lbu a4,12(sp) -8000de6c: 00000493 li s1,0 -8000de70: fff00a13 li s4,-1 -8000de74: 00a00a93 li s5,10 -8000de78: 0280006f j 8000dea0 <__fputwc+0xb4> -8000de7c: 00042783 lw a5,0(s0) -8000de80: 00178693 addi a3,a5,1 -8000de84: 00d42023 sw a3,0(s0) -8000de88: 00e78023 sb a4,0(a5) -8000de8c: 00148493 addi s1,s1,1 -8000de90: 00c10793 addi a5,sp,12 -8000de94: 009787b3 add a5,a5,s1 -8000de98: 0724f463 bgeu s1,s2,8000df00 <__fputwc+0x114> -8000de9c: 0007c703 lbu a4,0(a5) -8000dea0: 00842783 lw a5,8(s0) -8000dea4: fff78793 addi a5,a5,-1 -8000dea8: 00f42423 sw a5,8(s0) -8000deac: fc07d8e3 bgez a5,8000de7c <__fputwc+0x90> -8000deb0: 01842683 lw a3,24(s0) -8000deb4: 00070593 mv a1,a4 -8000deb8: 00040613 mv a2,s0 -8000debc: 000b0513 mv a0,s6 -8000dec0: 00d7c463 blt a5,a3,8000dec8 <__fputwc+0xdc> -8000dec4: fb571ce3 bne a4,s5,8000de7c <__fputwc+0x90> -8000dec8: 2a0020ef jal ra,80010168 <__swbuf_r> -8000decc: fd4510e3 bne a0,s4,8000de8c <__fputwc+0xa0> -8000ded0: fff00913 li s2,-1 -8000ded4: 02c12083 lw ra,44(sp) -8000ded8: 02812403 lw s0,40(sp) -8000dedc: 02412483 lw s1,36(sp) -8000dee0: 01c12983 lw s3,28(sp) -8000dee4: 01812a03 lw s4,24(sp) -8000dee8: 01412a83 lw s5,20(sp) -8000deec: 01012b03 lw s6,16(sp) -8000def0: 00090513 mv a0,s2 -8000def4: 02012903 lw s2,32(sp) -8000def8: 03010113 addi sp,sp,48 -8000defc: 00008067 ret -8000df00: 00098913 mv s2,s3 -8000df04: fd1ff06f j 8000ded4 <__fputwc+0xe8> -8000df08: 00c45783 lhu a5,12(s0) -8000df0c: 0407e793 ori a5,a5,64 -8000df10: 00f41623 sh a5,12(s0) -8000df14: fc1ff06f j 8000ded4 <__fputwc+0xe8> +8000dd20 <_fputwc_r>: +8000dd20: 00c61783 lh a5,12(a2) +8000dd24: 01279713 slli a4,a5,0x12 +8000dd28: 02074063 bltz a4,8000dd48 <_fputwc_r+0x28> +8000dd2c: 06462703 lw a4,100(a2) +8000dd30: 000026b7 lui a3,0x2 +8000dd34: 00d7e7b3 or a5,a5,a3 +8000dd38: 000026b7 lui a3,0x2 +8000dd3c: 00d76733 or a4,a4,a3 +8000dd40: 00f61623 sh a5,12(a2) +8000dd44: 06e62223 sw a4,100(a2) +8000dd48: eadff06f j 8000dbf4 <__fputwc> -8000df18 <_fputwc_r>: -8000df18: 00c61783 lh a5,12(a2) -8000df1c: 01279713 slli a4,a5,0x12 -8000df20: 02074063 bltz a4,8000df40 <_fputwc_r+0x28> -8000df24: 06462703 lw a4,100(a2) -8000df28: 000026b7 lui a3,0x2 -8000df2c: 00d7e7b3 or a5,a5,a3 -8000df30: 000026b7 lui a3,0x2 -8000df34: 00d76733 or a4,a4,a3 -8000df38: 00f61623 sh a5,12(a2) -8000df3c: 06e62223 sw a4,100(a2) -8000df40: eadff06f j 8000ddec <__fputwc> +8000dd4c : +8000dd4c: fe010113 addi sp,sp,-32 +8000dd50: 00812c23 sw s0,24(sp) +8000dd54: 3601a403 lw s0,864(gp) # 80016b68 <_impure_ptr> +8000dd58: 00112e23 sw ra,28(sp) +8000dd5c: 00058613 mv a2,a1 +8000dd60: 00050593 mv a1,a0 +8000dd64: 00040663 beqz s0,8000dd70 +8000dd68: 03842783 lw a5,56(s0) +8000dd6c: 04078063 beqz a5,8000ddac +8000dd70: 00c61783 lh a5,12(a2) +8000dd74: 01279713 slli a4,a5,0x12 +8000dd78: 02074063 bltz a4,8000dd98 +8000dd7c: 06462703 lw a4,100(a2) +8000dd80: 000026b7 lui a3,0x2 +8000dd84: 00d7e7b3 or a5,a5,a3 +8000dd88: 000026b7 lui a3,0x2 +8000dd8c: 00d76733 or a4,a4,a3 +8000dd90: 00f61623 sh a5,12(a2) +8000dd94: 06e62223 sw a4,100(a2) +8000dd98: 00040513 mv a0,s0 +8000dd9c: 01812403 lw s0,24(sp) +8000dda0: 01c12083 lw ra,28(sp) +8000dda4: 02010113 addi sp,sp,32 +8000dda8: e4dff06f j 8000dbf4 <__fputwc> +8000ddac: 00a12423 sw a0,8(sp) +8000ddb0: 00040513 mv a0,s0 +8000ddb4: 00c12623 sw a2,12(sp) +8000ddb8: a51f60ef jal ra,80004808 <__sinit> +8000ddbc: 00c12603 lw a2,12(sp) +8000ddc0: 00812583 lw a1,8(sp) +8000ddc4: fadff06f j 8000dd70 -8000df44 : -8000df44: fe010113 addi sp,sp,-32 -8000df48: 00812c23 sw s0,24(sp) -8000df4c: 3601a403 lw s0,864(gp) # 80016b68 <_impure_ptr> -8000df50: 00112e23 sw ra,28(sp) -8000df54: 00058613 mv a2,a1 -8000df58: 00050593 mv a1,a0 -8000df5c: 00040663 beqz s0,8000df68 -8000df60: 03842783 lw a5,56(s0) -8000df64: 04078063 beqz a5,8000dfa4 -8000df68: 00c61783 lh a5,12(a2) -8000df6c: 01279713 slli a4,a5,0x12 -8000df70: 02074063 bltz a4,8000df90 -8000df74: 06462703 lw a4,100(a2) -8000df78: 000026b7 lui a3,0x2 -8000df7c: 00d7e7b3 or a5,a5,a3 -8000df80: 000026b7 lui a3,0x2 -8000df84: 00d76733 or a4,a4,a3 -8000df88: 00f61623 sh a5,12(a2) -8000df8c: 06e62223 sw a4,100(a2) -8000df90: 00040513 mv a0,s0 -8000df94: 01812403 lw s0,24(sp) -8000df98: 01c12083 lw ra,28(sp) -8000df9c: 02010113 addi sp,sp,32 -8000dfa0: e4dff06f j 8000ddec <__fputwc> -8000dfa4: 00a12423 sw a0,8(sp) -8000dfa8: 00040513 mv a0,s0 -8000dfac: 00c12623 sw a2,12(sp) -8000dfb0: 965f60ef jal ra,80004914 <__sinit> -8000dfb4: 00c12603 lw a2,12(sp) -8000dfb8: 00812583 lw a1,8(sp) -8000dfbc: fadff06f j 8000df68 +8000ddc8 <_fstat_r>: +8000ddc8: ff010113 addi sp,sp,-16 +8000ddcc: 00058713 mv a4,a1 +8000ddd0: 00812423 sw s0,8(sp) +8000ddd4: 00912223 sw s1,4(sp) +8000ddd8: 00050413 mv s0,a0 +8000dddc: 00060593 mv a1,a2 +8000dde0: 00070513 mv a0,a4 +8000dde4: 00112623 sw ra,12(sp) +8000dde8: 4201a823 sw zero,1072(gp) # 80016c38 +8000ddec: cbcf20ef jal ra,800002a8 <_fstat> +8000ddf0: fff00793 li a5,-1 +8000ddf4: 00f50c63 beq a0,a5,8000de0c <_fstat_r+0x44> +8000ddf8: 00c12083 lw ra,12(sp) +8000ddfc: 00812403 lw s0,8(sp) +8000de00: 00412483 lw s1,4(sp) +8000de04: 01010113 addi sp,sp,16 +8000de08: 00008067 ret +8000de0c: 4301a783 lw a5,1072(gp) # 80016c38 +8000de10: fe0784e3 beqz a5,8000ddf8 <_fstat_r+0x30> +8000de14: 00c12083 lw ra,12(sp) +8000de18: 00f42023 sw a5,0(s0) +8000de1c: 00812403 lw s0,8(sp) +8000de20: 00412483 lw s1,4(sp) +8000de24: 01010113 addi sp,sp,16 +8000de28: 00008067 ret -8000dfc0 <_fstat_r>: -8000dfc0: ff010113 addi sp,sp,-16 -8000dfc4: 00058713 mv a4,a1 -8000dfc8: 00812423 sw s0,8(sp) -8000dfcc: 00912223 sw s1,4(sp) -8000dfd0: 00050413 mv s0,a0 -8000dfd4: 00060593 mv a1,a2 -8000dfd8: 00070513 mv a0,a4 -8000dfdc: 00112623 sw ra,12(sp) -8000dfe0: 4201a223 sw zero,1060(gp) # 80016c2c -8000dfe4: af8f20ef jal ra,800002dc <_fstat> -8000dfe8: fff00793 li a5,-1 -8000dfec: 00f50c63 beq a0,a5,8000e004 <_fstat_r+0x44> -8000dff0: 00c12083 lw ra,12(sp) -8000dff4: 00812403 lw s0,8(sp) -8000dff8: 00412483 lw s1,4(sp) -8000dffc: 01010113 addi sp,sp,16 -8000e000: 00008067 ret -8000e004: 4241a783 lw a5,1060(gp) # 80016c2c -8000e008: fe0784e3 beqz a5,8000dff0 <_fstat_r+0x30> -8000e00c: 00c12083 lw ra,12(sp) -8000e010: 00f42023 sw a5,0(s0) -8000e014: 00812403 lw s0,8(sp) -8000e018: 00412483 lw s1,4(sp) -8000e01c: 01010113 addi sp,sp,16 -8000e020: 00008067 ret +8000de2c <__sfvwrite_r>: +8000de2c: 00862783 lw a5,8(a2) +8000de30: 32078e63 beqz a5,8000e16c <__sfvwrite_r+0x340> +8000de34: 00c5d783 lhu a5,12(a1) +8000de38: fd010113 addi sp,sp,-48 +8000de3c: 02812423 sw s0,40(sp) +8000de40: 01412c23 sw s4,24(sp) +8000de44: 01512a23 sw s5,20(sp) +8000de48: 02112623 sw ra,44(sp) +8000de4c: 02912223 sw s1,36(sp) +8000de50: 03212023 sw s2,32(sp) +8000de54: 01312e23 sw s3,28(sp) +8000de58: 01612823 sw s6,16(sp) +8000de5c: 01712623 sw s7,12(sp) +8000de60: 01812423 sw s8,8(sp) +8000de64: 01912223 sw s9,4(sp) +8000de68: 01a12023 sw s10,0(sp) +8000de6c: 0087f713 andi a4,a5,8 +8000de70: 00060a13 mv s4,a2 +8000de74: 00050a93 mv s5,a0 +8000de78: 00058413 mv s0,a1 +8000de7c: 08070663 beqz a4,8000df08 <__sfvwrite_r+0xdc> +8000de80: 0105a703 lw a4,16(a1) +8000de84: 08070263 beqz a4,8000df08 <__sfvwrite_r+0xdc> +8000de88: 0027f713 andi a4,a5,2 +8000de8c: 000a2483 lw s1,0(s4) +8000de90: 08070c63 beqz a4,8000df28 <__sfvwrite_r+0xfc> +8000de94: 02442783 lw a5,36(s0) +8000de98: 01c42583 lw a1,28(s0) +8000de9c: 80000b37 lui s6,0x80000 +8000dea0: 00000993 li s3,0 +8000dea4: 00000913 li s2,0 +8000dea8: c00b4b13 xori s6,s6,-1024 +8000deac: 00098613 mv a2,s3 +8000deb0: 000a8513 mv a0,s5 +8000deb4: 04090263 beqz s2,8000def8 <__sfvwrite_r+0xcc> +8000deb8: 00090693 mv a3,s2 +8000debc: 012b7463 bgeu s6,s2,8000dec4 <__sfvwrite_r+0x98> +8000dec0: 000b0693 mv a3,s6 +8000dec4: 000780e7 jalr a5 +8000dec8: 28a05863 blez a0,8000e158 <__sfvwrite_r+0x32c> +8000decc: 008a2783 lw a5,8(s4) +8000ded0: 00a989b3 add s3,s3,a0 +8000ded4: 40a90933 sub s2,s2,a0 +8000ded8: 40a78533 sub a0,a5,a0 +8000dedc: 00aa2423 sw a0,8(s4) +8000dee0: 20050a63 beqz a0,8000e0f4 <__sfvwrite_r+0x2c8> +8000dee4: 02442783 lw a5,36(s0) +8000dee8: 01c42583 lw a1,28(s0) +8000deec: 00098613 mv a2,s3 +8000def0: 000a8513 mv a0,s5 +8000def4: fc0912e3 bnez s2,8000deb8 <__sfvwrite_r+0x8c> +8000def8: 0004a983 lw s3,0(s1) +8000defc: 0044a903 lw s2,4(s1) +8000df00: 00848493 addi s1,s1,8 +8000df04: fa9ff06f j 8000deac <__sfvwrite_r+0x80> +8000df08: 00040593 mv a1,s0 +8000df0c: 000a8513 mv a0,s5 +8000df10: 870f60ef jal ra,80003f80 <__swsetup_r> +8000df14: 3a051c63 bnez a0,8000e2cc <__sfvwrite_r+0x4a0> +8000df18: 00c45783 lhu a5,12(s0) +8000df1c: 000a2483 lw s1,0(s4) +8000df20: 0027f713 andi a4,a5,2 +8000df24: f60718e3 bnez a4,8000de94 <__sfvwrite_r+0x68> +8000df28: 0017f713 andi a4,a5,1 +8000df2c: 24071463 bnez a4,8000e174 <__sfvwrite_r+0x348> +8000df30: 00842c83 lw s9,8(s0) +8000df34: 00042503 lw a0,0(s0) +8000df38: 80000b37 lui s6,0x80000 +8000df3c: ffeb4b93 xori s7,s6,-2 +8000df40: 00000c13 li s8,0 +8000df44: 00000913 li s2,0 +8000df48: fffb4b13 not s6,s6 +8000df4c: 0e090e63 beqz s2,8000e048 <__sfvwrite_r+0x21c> +8000df50: 2007f713 andi a4,a5,512 +8000df54: 24070c63 beqz a4,8000e1ac <__sfvwrite_r+0x380> +8000df58: 000c8d13 mv s10,s9 +8000df5c: 2f996263 bltu s2,s9,8000e240 <__sfvwrite_r+0x414> +8000df60: 4807f713 andi a4,a5,1152 +8000df64: 08070a63 beqz a4,8000dff8 <__sfvwrite_r+0x1cc> +8000df68: 01442983 lw s3,20(s0) +8000df6c: 01042583 lw a1,16(s0) +8000df70: 00190713 addi a4,s2,1 +8000df74: 00199693 slli a3,s3,0x1 +8000df78: 013686b3 add a3,a3,s3 +8000df7c: 01f6d993 srli s3,a3,0x1f +8000df80: 40b50d33 sub s10,a0,a1 +8000df84: 00d989b3 add s3,s3,a3 +8000df88: 4019d993 srai s3,s3,0x1 +8000df8c: 01a70733 add a4,a4,s10 +8000df90: 00098613 mv a2,s3 +8000df94: 00e9f663 bgeu s3,a4,8000dfa0 <__sfvwrite_r+0x174> +8000df98: 00070993 mv s3,a4 +8000df9c: 00070613 mv a2,a4 +8000dfa0: 4007f793 andi a5,a5,1024 +8000dfa4: 2e078463 beqz a5,8000e28c <__sfvwrite_r+0x460> +8000dfa8: 00060593 mv a1,a2 +8000dfac: 000a8513 mv a0,s5 +8000dfb0: bf9f90ef jal ra,80007ba8 <_malloc_r> +8000dfb4: 00050c93 mv s9,a0 +8000dfb8: 30050263 beqz a0,8000e2bc <__sfvwrite_r+0x490> +8000dfbc: 01042583 lw a1,16(s0) +8000dfc0: 000d0613 mv a2,s10 +8000dfc4: 4dc000ef jal ra,8000e4a0 +8000dfc8: 00c45783 lhu a5,12(s0) +8000dfcc: b7f7f793 andi a5,a5,-1153 +8000dfd0: 0807e793 ori a5,a5,128 +8000dfd4: 00f41623 sh a5,12(s0) +8000dfd8: 01ac8533 add a0,s9,s10 +8000dfdc: 41a987b3 sub a5,s3,s10 +8000dfe0: 01942823 sw s9,16(s0) +8000dfe4: 00a42023 sw a0,0(s0) +8000dfe8: 01342a23 sw s3,20(s0) +8000dfec: 00090c93 mv s9,s2 +8000dff0: 00f42423 sw a5,8(s0) +8000dff4: 00090d13 mv s10,s2 +8000dff8: 000d0613 mv a2,s10 +8000dffc: 000c0593 mv a1,s8 +8000e000: 5bc000ef jal ra,8000e5bc +8000e004: 00842703 lw a4,8(s0) +8000e008: 00042783 lw a5,0(s0) +8000e00c: 00090993 mv s3,s2 +8000e010: 41970cb3 sub s9,a4,s9 +8000e014: 01a787b3 add a5,a5,s10 +8000e018: 01942423 sw s9,8(s0) +8000e01c: 00f42023 sw a5,0(s0) +8000e020: 00000913 li s2,0 +8000e024: 008a2603 lw a2,8(s4) +8000e028: 013c0c33 add s8,s8,s3 +8000e02c: 413609b3 sub s3,a2,s3 +8000e030: 013a2423 sw s3,8(s4) +8000e034: 0c098063 beqz s3,8000e0f4 <__sfvwrite_r+0x2c8> +8000e038: 00842c83 lw s9,8(s0) +8000e03c: 00042503 lw a0,0(s0) +8000e040: 00c45783 lhu a5,12(s0) +8000e044: f00916e3 bnez s2,8000df50 <__sfvwrite_r+0x124> +8000e048: 0004ac03 lw s8,0(s1) +8000e04c: 0044a903 lw s2,4(s1) +8000e050: 00848493 addi s1,s1,8 +8000e054: ef9ff06f j 8000df4c <__sfvwrite_r+0x120> +8000e058: 0044a983 lw s3,4(s1) +8000e05c: 0004ac03 lw s8,0(s1) +8000e060: 00848493 addi s1,s1,8 +8000e064: fe098ae3 beqz s3,8000e058 <__sfvwrite_r+0x22c> +8000e068: 00098613 mv a2,s3 +8000e06c: 00a00593 li a1,10 +8000e070: 000c0513 mv a0,s8 +8000e074: accfa0ef jal ra,80008340 +8000e078: 12050463 beqz a0,8000e1a0 <__sfvwrite_r+0x374> +8000e07c: 00150513 addi a0,a0,1 +8000e080: 41850b33 sub s6,a0,s8 +8000e084: 000b0793 mv a5,s6 +8000e088: 00098b93 mv s7,s3 +8000e08c: 0137f463 bgeu a5,s3,8000e094 <__sfvwrite_r+0x268> +8000e090: 00078b93 mv s7,a5 +8000e094: 00042503 lw a0,0(s0) +8000e098: 01042783 lw a5,16(s0) +8000e09c: 01442683 lw a3,20(s0) +8000e0a0: 00a7f863 bgeu a5,a0,8000e0b0 <__sfvwrite_r+0x284> +8000e0a4: 00842903 lw s2,8(s0) +8000e0a8: 01268933 add s2,a3,s2 +8000e0ac: 09794263 blt s2,s7,8000e130 <__sfvwrite_r+0x304> +8000e0b0: 1adbc863 blt s7,a3,8000e260 <__sfvwrite_r+0x434> +8000e0b4: 02442783 lw a5,36(s0) +8000e0b8: 01c42583 lw a1,28(s0) +8000e0bc: 000c0613 mv a2,s8 +8000e0c0: 000a8513 mv a0,s5 +8000e0c4: 000780e7 jalr a5 +8000e0c8: 00050913 mv s2,a0 +8000e0cc: 08a05663 blez a0,8000e158 <__sfvwrite_r+0x32c> +8000e0d0: 412b0b33 sub s6,s6,s2 +8000e0d4: 00100513 li a0,1 +8000e0d8: 160b0a63 beqz s6,8000e24c <__sfvwrite_r+0x420> +8000e0dc: 008a2603 lw a2,8(s4) +8000e0e0: 012c0c33 add s8,s8,s2 +8000e0e4: 412989b3 sub s3,s3,s2 +8000e0e8: 41260933 sub s2,a2,s2 +8000e0ec: 012a2423 sw s2,8(s4) +8000e0f0: 08091a63 bnez s2,8000e184 <__sfvwrite_r+0x358> +8000e0f4: 00000513 li a0,0 +8000e0f8: 02c12083 lw ra,44(sp) +8000e0fc: 02812403 lw s0,40(sp) +8000e100: 02412483 lw s1,36(sp) +8000e104: 02012903 lw s2,32(sp) +8000e108: 01c12983 lw s3,28(sp) +8000e10c: 01812a03 lw s4,24(sp) +8000e110: 01412a83 lw s5,20(sp) +8000e114: 01012b03 lw s6,16(sp) +8000e118: 00c12b83 lw s7,12(sp) +8000e11c: 00812c03 lw s8,8(sp) +8000e120: 00412c83 lw s9,4(sp) +8000e124: 00012d03 lw s10,0(sp) +8000e128: 03010113 addi sp,sp,48 +8000e12c: 00008067 ret +8000e130: 000c0593 mv a1,s8 +8000e134: 00090613 mv a2,s2 +8000e138: 484000ef jal ra,8000e5bc +8000e13c: 00042783 lw a5,0(s0) +8000e140: 00040593 mv a1,s0 +8000e144: 000a8513 mv a0,s5 +8000e148: 012787b3 add a5,a5,s2 +8000e14c: 00f42023 sw a5,0(s0) +8000e150: b1cf60ef jal ra,8000446c <_fflush_r> +8000e154: f6050ee3 beqz a0,8000e0d0 <__sfvwrite_r+0x2a4> +8000e158: 00c41783 lh a5,12(s0) +8000e15c: 0407e793 ori a5,a5,64 +8000e160: 00f41623 sh a5,12(s0) +8000e164: fff00513 li a0,-1 +8000e168: f91ff06f j 8000e0f8 <__sfvwrite_r+0x2cc> +8000e16c: 00000513 li a0,0 +8000e170: 00008067 ret +8000e174: 00000b13 li s6,0 +8000e178: 00000513 li a0,0 +8000e17c: 00000c13 li s8,0 +8000e180: 00000993 li s3,0 +8000e184: ec098ae3 beqz s3,8000e058 <__sfvwrite_r+0x22c> +8000e188: ee051ee3 bnez a0,8000e084 <__sfvwrite_r+0x258> +8000e18c: 00098613 mv a2,s3 +8000e190: 00a00593 li a1,10 +8000e194: 000c0513 mv a0,s8 +8000e198: 9a8fa0ef jal ra,80008340 +8000e19c: ee0510e3 bnez a0,8000e07c <__sfvwrite_r+0x250> +8000e1a0: 00198793 addi a5,s3,1 +8000e1a4: 00078b13 mv s6,a5 +8000e1a8: ee1ff06f j 8000e088 <__sfvwrite_r+0x25c> +8000e1ac: 01042783 lw a5,16(s0) +8000e1b0: 04a7e263 bltu a5,a0,8000e1f4 <__sfvwrite_r+0x3c8> +8000e1b4: 01442783 lw a5,20(s0) +8000e1b8: 02f96e63 bltu s2,a5,8000e1f4 <__sfvwrite_r+0x3c8> +8000e1bc: 00090693 mv a3,s2 +8000e1c0: 012bf463 bgeu s7,s2,8000e1c8 <__sfvwrite_r+0x39c> +8000e1c4: 000b0693 mv a3,s6 +8000e1c8: 02f6c6b3 div a3,a3,a5 +8000e1cc: 02442703 lw a4,36(s0) +8000e1d0: 01c42583 lw a1,28(s0) +8000e1d4: 000c0613 mv a2,s8 +8000e1d8: 000a8513 mv a0,s5 +8000e1dc: 02f686b3 mul a3,a3,a5 +8000e1e0: 000700e7 jalr a4 +8000e1e4: 00050993 mv s3,a0 +8000e1e8: f6a058e3 blez a0,8000e158 <__sfvwrite_r+0x32c> +8000e1ec: 41390933 sub s2,s2,s3 +8000e1f0: e35ff06f j 8000e024 <__sfvwrite_r+0x1f8> +8000e1f4: 000c8993 mv s3,s9 +8000e1f8: 01997463 bgeu s2,s9,8000e200 <__sfvwrite_r+0x3d4> +8000e1fc: 00090993 mv s3,s2 +8000e200: 00098613 mv a2,s3 +8000e204: 000c0593 mv a1,s8 +8000e208: 3b4000ef jal ra,8000e5bc +8000e20c: 00842783 lw a5,8(s0) +8000e210: 00042703 lw a4,0(s0) +8000e214: 413787b3 sub a5,a5,s3 +8000e218: 01370733 add a4,a4,s3 +8000e21c: 00f42423 sw a5,8(s0) +8000e220: 00e42023 sw a4,0(s0) +8000e224: fc0794e3 bnez a5,8000e1ec <__sfvwrite_r+0x3c0> +8000e228: 00040593 mv a1,s0 +8000e22c: 000a8513 mv a0,s5 +8000e230: a3cf60ef jal ra,8000446c <_fflush_r> +8000e234: f20512e3 bnez a0,8000e158 <__sfvwrite_r+0x32c> +8000e238: 41390933 sub s2,s2,s3 +8000e23c: de9ff06f j 8000e024 <__sfvwrite_r+0x1f8> +8000e240: 00090c93 mv s9,s2 +8000e244: 00090d13 mv s10,s2 +8000e248: db1ff06f j 8000dff8 <__sfvwrite_r+0x1cc> +8000e24c: 00040593 mv a1,s0 +8000e250: 000a8513 mv a0,s5 +8000e254: a18f60ef jal ra,8000446c <_fflush_r> +8000e258: e80502e3 beqz a0,8000e0dc <__sfvwrite_r+0x2b0> +8000e25c: efdff06f j 8000e158 <__sfvwrite_r+0x32c> +8000e260: 000b8613 mv a2,s7 +8000e264: 000c0593 mv a1,s8 +8000e268: 354000ef jal ra,8000e5bc +8000e26c: 00842783 lw a5,8(s0) +8000e270: 00042603 lw a2,0(s0) +8000e274: 000b8913 mv s2,s7 +8000e278: 417787b3 sub a5,a5,s7 +8000e27c: 01760633 add a2,a2,s7 +8000e280: 00f42423 sw a5,8(s0) +8000e284: 00c42023 sw a2,0(s0) +8000e288: e49ff06f j 8000e0d0 <__sfvwrite_r+0x2a4> +8000e28c: 000a8513 mv a0,s5 +8000e290: 4b4000ef jal ra,8000e744 <_realloc_r> +8000e294: 00050c93 mv s9,a0 +8000e298: d40510e3 bnez a0,8000dfd8 <__sfvwrite_r+0x1ac> +8000e29c: 01042583 lw a1,16(s0) +8000e2a0: 000a8513 mv a0,s5 +8000e2a4: f30f60ef jal ra,800049d4 <_free_r> +8000e2a8: 00c41783 lh a5,12(s0) +8000e2ac: 00c00713 li a4,12 +8000e2b0: 00eaa023 sw a4,0(s5) +8000e2b4: f7f7f793 andi a5,a5,-129 +8000e2b8: ea5ff06f j 8000e15c <__sfvwrite_r+0x330> +8000e2bc: 00c00713 li a4,12 +8000e2c0: 00c41783 lh a5,12(s0) +8000e2c4: 00eaa023 sw a4,0(s5) +8000e2c8: e95ff06f j 8000e15c <__sfvwrite_r+0x330> +8000e2cc: fff00513 li a0,-1 +8000e2d0: e29ff06f j 8000e0f8 <__sfvwrite_r+0x2cc> -8000e024 <__sfvwrite_r>: -8000e024: 00862783 lw a5,8(a2) -8000e028: 32078e63 beqz a5,8000e364 <__sfvwrite_r+0x340> -8000e02c: 00c5d783 lhu a5,12(a1) -8000e030: fd010113 addi sp,sp,-48 -8000e034: 02812423 sw s0,40(sp) -8000e038: 01412c23 sw s4,24(sp) -8000e03c: 01512a23 sw s5,20(sp) -8000e040: 02112623 sw ra,44(sp) -8000e044: 02912223 sw s1,36(sp) -8000e048: 03212023 sw s2,32(sp) -8000e04c: 01312e23 sw s3,28(sp) -8000e050: 01612823 sw s6,16(sp) -8000e054: 01712623 sw s7,12(sp) -8000e058: 01812423 sw s8,8(sp) -8000e05c: 01912223 sw s9,4(sp) -8000e060: 01a12023 sw s10,0(sp) -8000e064: 0087f713 andi a4,a5,8 -8000e068: 00060a13 mv s4,a2 -8000e06c: 00050a93 mv s5,a0 -8000e070: 00058413 mv s0,a1 -8000e074: 08070663 beqz a4,8000e100 <__sfvwrite_r+0xdc> -8000e078: 0105a703 lw a4,16(a1) -8000e07c: 08070263 beqz a4,8000e100 <__sfvwrite_r+0xdc> -8000e080: 0027f713 andi a4,a5,2 -8000e084: 000a2483 lw s1,0(s4) -8000e088: 08070c63 beqz a4,8000e120 <__sfvwrite_r+0xfc> -8000e08c: 02442783 lw a5,36(s0) -8000e090: 01c42583 lw a1,28(s0) -8000e094: 80000b37 lui s6,0x80000 -8000e098: 00000993 li s3,0 -8000e09c: 00000913 li s2,0 -8000e0a0: c00b4b13 xori s6,s6,-1024 -8000e0a4: 00098613 mv a2,s3 -8000e0a8: 000a8513 mv a0,s5 -8000e0ac: 04090263 beqz s2,8000e0f0 <__sfvwrite_r+0xcc> -8000e0b0: 00090693 mv a3,s2 -8000e0b4: 012b7463 bgeu s6,s2,8000e0bc <__sfvwrite_r+0x98> -8000e0b8: 000b0693 mv a3,s6 -8000e0bc: 000780e7 jalr a5 -8000e0c0: 28a05863 blez a0,8000e350 <__sfvwrite_r+0x32c> -8000e0c4: 008a2783 lw a5,8(s4) -8000e0c8: 00a989b3 add s3,s3,a0 -8000e0cc: 40a90933 sub s2,s2,a0 -8000e0d0: 40a78533 sub a0,a5,a0 -8000e0d4: 00aa2423 sw a0,8(s4) -8000e0d8: 20050a63 beqz a0,8000e2ec <__sfvwrite_r+0x2c8> -8000e0dc: 02442783 lw a5,36(s0) -8000e0e0: 01c42583 lw a1,28(s0) -8000e0e4: 00098613 mv a2,s3 -8000e0e8: 000a8513 mv a0,s5 -8000e0ec: fc0912e3 bnez s2,8000e0b0 <__sfvwrite_r+0x8c> -8000e0f0: 0004a983 lw s3,0(s1) -8000e0f4: 0044a903 lw s2,4(s1) -8000e0f8: 00848493 addi s1,s1,8 -8000e0fc: fa9ff06f j 8000e0a4 <__sfvwrite_r+0x80> -8000e100: 00040593 mv a1,s0 -8000e104: 000a8513 mv a0,s5 -8000e108: f01f50ef jal ra,80004008 <__swsetup_r> -8000e10c: 3a051c63 bnez a0,8000e4c4 <__sfvwrite_r+0x4a0> -8000e110: 00c45783 lhu a5,12(s0) -8000e114: 000a2483 lw s1,0(s4) -8000e118: 0027f713 andi a4,a5,2 -8000e11c: f60718e3 bnez a4,8000e08c <__sfvwrite_r+0x68> -8000e120: 0017f713 andi a4,a5,1 -8000e124: 24071463 bnez a4,8000e36c <__sfvwrite_r+0x348> -8000e128: 00842c83 lw s9,8(s0) -8000e12c: 00042503 lw a0,0(s0) -8000e130: 80000b37 lui s6,0x80000 -8000e134: ffeb4b93 xori s7,s6,-2 -8000e138: 00000c13 li s8,0 -8000e13c: 00000913 li s2,0 -8000e140: fffb4b13 not s6,s6 -8000e144: 0e090e63 beqz s2,8000e240 <__sfvwrite_r+0x21c> -8000e148: 2007f713 andi a4,a5,512 -8000e14c: 24070c63 beqz a4,8000e3a4 <__sfvwrite_r+0x380> -8000e150: 000c8d13 mv s10,s9 -8000e154: 2f996263 bltu s2,s9,8000e438 <__sfvwrite_r+0x414> -8000e158: 4807f713 andi a4,a5,1152 -8000e15c: 08070a63 beqz a4,8000e1f0 <__sfvwrite_r+0x1cc> -8000e160: 01442983 lw s3,20(s0) -8000e164: 01042583 lw a1,16(s0) -8000e168: 00190713 addi a4,s2,1 -8000e16c: 00199693 slli a3,s3,0x1 -8000e170: 013686b3 add a3,a3,s3 -8000e174: 01f6d993 srli s3,a3,0x1f -8000e178: 40b50d33 sub s10,a0,a1 -8000e17c: 00d989b3 add s3,s3,a3 -8000e180: 4019d993 srai s3,s3,0x1 -8000e184: 01a70733 add a4,a4,s10 -8000e188: 00098613 mv a2,s3 -8000e18c: 00e9f663 bgeu s3,a4,8000e198 <__sfvwrite_r+0x174> -8000e190: 00070993 mv s3,a4 -8000e194: 00070613 mv a2,a4 -8000e198: 4007f793 andi a5,a5,1024 -8000e19c: 2e078463 beqz a5,8000e484 <__sfvwrite_r+0x460> -8000e1a0: 00060593 mv a1,a2 -8000e1a4: 000a8513 mv a0,s5 -8000e1a8: b49f90ef jal ra,80007cf0 <_malloc_r> -8000e1ac: 00050c93 mv s9,a0 -8000e1b0: 30050263 beqz a0,8000e4b4 <__sfvwrite_r+0x490> -8000e1b4: 01042583 lw a1,16(s0) -8000e1b8: 000d0613 mv a2,s10 -8000e1bc: 3d4000ef jal ra,8000e590 -8000e1c0: 00c45783 lhu a5,12(s0) -8000e1c4: b7f7f793 andi a5,a5,-1153 -8000e1c8: 0807e793 ori a5,a5,128 -8000e1cc: 00f41623 sh a5,12(s0) -8000e1d0: 01ac8533 add a0,s9,s10 -8000e1d4: 41a987b3 sub a5,s3,s10 -8000e1d8: 01942823 sw s9,16(s0) -8000e1dc: 00a42023 sw a0,0(s0) -8000e1e0: 01342a23 sw s3,20(s0) -8000e1e4: 00090c93 mv s9,s2 -8000e1e8: 00f42423 sw a5,8(s0) -8000e1ec: 00090d13 mv s10,s2 -8000e1f0: 000d0613 mv a2,s10 -8000e1f4: 000c0593 mv a1,s8 -8000e1f8: 4b4000ef jal ra,8000e6ac -8000e1fc: 00842703 lw a4,8(s0) -8000e200: 00042783 lw a5,0(s0) -8000e204: 00090993 mv s3,s2 -8000e208: 41970cb3 sub s9,a4,s9 -8000e20c: 01a787b3 add a5,a5,s10 -8000e210: 01942423 sw s9,8(s0) -8000e214: 00f42023 sw a5,0(s0) -8000e218: 00000913 li s2,0 -8000e21c: 008a2603 lw a2,8(s4) -8000e220: 013c0c33 add s8,s8,s3 -8000e224: 413609b3 sub s3,a2,s3 -8000e228: 013a2423 sw s3,8(s4) -8000e22c: 0c098063 beqz s3,8000e2ec <__sfvwrite_r+0x2c8> -8000e230: 00842c83 lw s9,8(s0) -8000e234: 00042503 lw a0,0(s0) -8000e238: 00c45783 lhu a5,12(s0) -8000e23c: f00916e3 bnez s2,8000e148 <__sfvwrite_r+0x124> -8000e240: 0004ac03 lw s8,0(s1) -8000e244: 0044a903 lw s2,4(s1) -8000e248: 00848493 addi s1,s1,8 -8000e24c: ef9ff06f j 8000e144 <__sfvwrite_r+0x120> -8000e250: 0044a983 lw s3,4(s1) -8000e254: 0004ac03 lw s8,0(s1) -8000e258: 00848493 addi s1,s1,8 -8000e25c: fe098ae3 beqz s3,8000e250 <__sfvwrite_r+0x22c> -8000e260: 00098613 mv a2,s3 -8000e264: 00a00593 li a1,10 -8000e268: 000c0513 mv a0,s8 -8000e26c: a8cfa0ef jal ra,800084f8 -8000e270: 12050463 beqz a0,8000e398 <__sfvwrite_r+0x374> -8000e274: 00150513 addi a0,a0,1 -8000e278: 41850b33 sub s6,a0,s8 -8000e27c: 000b0793 mv a5,s6 -8000e280: 00098b93 mv s7,s3 -8000e284: 0137f463 bgeu a5,s3,8000e28c <__sfvwrite_r+0x268> -8000e288: 00078b93 mv s7,a5 -8000e28c: 00042503 lw a0,0(s0) -8000e290: 01042783 lw a5,16(s0) -8000e294: 01442683 lw a3,20(s0) -8000e298: 00a7f863 bgeu a5,a0,8000e2a8 <__sfvwrite_r+0x284> -8000e29c: 00842903 lw s2,8(s0) -8000e2a0: 01268933 add s2,a3,s2 -8000e2a4: 09794263 blt s2,s7,8000e328 <__sfvwrite_r+0x304> -8000e2a8: 1adbc863 blt s7,a3,8000e458 <__sfvwrite_r+0x434> -8000e2ac: 02442783 lw a5,36(s0) -8000e2b0: 01c42583 lw a1,28(s0) -8000e2b4: 000c0613 mv a2,s8 -8000e2b8: 000a8513 mv a0,s5 -8000e2bc: 000780e7 jalr a5 -8000e2c0: 00050913 mv s2,a0 -8000e2c4: 08a05663 blez a0,8000e350 <__sfvwrite_r+0x32c> -8000e2c8: 412b0b33 sub s6,s6,s2 -8000e2cc: 00100513 li a0,1 -8000e2d0: 160b0a63 beqz s6,8000e444 <__sfvwrite_r+0x420> -8000e2d4: 008a2603 lw a2,8(s4) -8000e2d8: 012c0c33 add s8,s8,s2 -8000e2dc: 412989b3 sub s3,s3,s2 -8000e2e0: 41260933 sub s2,a2,s2 -8000e2e4: 012a2423 sw s2,8(s4) -8000e2e8: 08091a63 bnez s2,8000e37c <__sfvwrite_r+0x358> -8000e2ec: 00000513 li a0,0 -8000e2f0: 02c12083 lw ra,44(sp) -8000e2f4: 02812403 lw s0,40(sp) -8000e2f8: 02412483 lw s1,36(sp) -8000e2fc: 02012903 lw s2,32(sp) -8000e300: 01c12983 lw s3,28(sp) -8000e304: 01812a03 lw s4,24(sp) -8000e308: 01412a83 lw s5,20(sp) -8000e30c: 01012b03 lw s6,16(sp) -8000e310: 00c12b83 lw s7,12(sp) -8000e314: 00812c03 lw s8,8(sp) -8000e318: 00412c83 lw s9,4(sp) -8000e31c: 00012d03 lw s10,0(sp) -8000e320: 03010113 addi sp,sp,48 -8000e324: 00008067 ret -8000e328: 000c0593 mv a1,s8 -8000e32c: 00090613 mv a2,s2 -8000e330: 37c000ef jal ra,8000e6ac -8000e334: 00042783 lw a5,0(s0) -8000e338: 00040593 mv a1,s0 -8000e33c: 000a8513 mv a0,s5 -8000e340: 012787b3 add a5,a5,s2 -8000e344: 00f42023 sw a5,0(s0) -8000e348: a30f60ef jal ra,80004578 <_fflush_r> -8000e34c: f6050ee3 beqz a0,8000e2c8 <__sfvwrite_r+0x2a4> -8000e350: 00c41783 lh a5,12(s0) -8000e354: 0407e793 ori a5,a5,64 -8000e358: 00f41623 sh a5,12(s0) -8000e35c: fff00513 li a0,-1 -8000e360: f91ff06f j 8000e2f0 <__sfvwrite_r+0x2cc> -8000e364: 00000513 li a0,0 -8000e368: 00008067 ret -8000e36c: 00000b13 li s6,0 -8000e370: 00000513 li a0,0 -8000e374: 00000c13 li s8,0 -8000e378: 00000993 li s3,0 -8000e37c: ec098ae3 beqz s3,8000e250 <__sfvwrite_r+0x22c> -8000e380: ee051ee3 bnez a0,8000e27c <__sfvwrite_r+0x258> -8000e384: 00098613 mv a2,s3 -8000e388: 00a00593 li a1,10 -8000e38c: 000c0513 mv a0,s8 -8000e390: 968fa0ef jal ra,800084f8 -8000e394: ee0510e3 bnez a0,8000e274 <__sfvwrite_r+0x250> -8000e398: 00198793 addi a5,s3,1 -8000e39c: 00078b13 mv s6,a5 -8000e3a0: ee1ff06f j 8000e280 <__sfvwrite_r+0x25c> -8000e3a4: 01042783 lw a5,16(s0) -8000e3a8: 04a7e263 bltu a5,a0,8000e3ec <__sfvwrite_r+0x3c8> -8000e3ac: 01442783 lw a5,20(s0) -8000e3b0: 02f96e63 bltu s2,a5,8000e3ec <__sfvwrite_r+0x3c8> -8000e3b4: 00090693 mv a3,s2 -8000e3b8: 012bf463 bgeu s7,s2,8000e3c0 <__sfvwrite_r+0x39c> -8000e3bc: 000b0693 mv a3,s6 -8000e3c0: 02f6c6b3 div a3,a3,a5 -8000e3c4: 02442703 lw a4,36(s0) -8000e3c8: 01c42583 lw a1,28(s0) -8000e3cc: 000c0613 mv a2,s8 -8000e3d0: 000a8513 mv a0,s5 -8000e3d4: 02f686b3 mul a3,a3,a5 -8000e3d8: 000700e7 jalr a4 -8000e3dc: 00050993 mv s3,a0 -8000e3e0: f6a058e3 blez a0,8000e350 <__sfvwrite_r+0x32c> -8000e3e4: 41390933 sub s2,s2,s3 -8000e3e8: e35ff06f j 8000e21c <__sfvwrite_r+0x1f8> -8000e3ec: 000c8993 mv s3,s9 -8000e3f0: 01997463 bgeu s2,s9,8000e3f8 <__sfvwrite_r+0x3d4> -8000e3f4: 00090993 mv s3,s2 -8000e3f8: 00098613 mv a2,s3 -8000e3fc: 000c0593 mv a1,s8 -8000e400: 2ac000ef jal ra,8000e6ac -8000e404: 00842783 lw a5,8(s0) -8000e408: 00042703 lw a4,0(s0) -8000e40c: 413787b3 sub a5,a5,s3 -8000e410: 01370733 add a4,a4,s3 -8000e414: 00f42423 sw a5,8(s0) -8000e418: 00e42023 sw a4,0(s0) -8000e41c: fc0794e3 bnez a5,8000e3e4 <__sfvwrite_r+0x3c0> -8000e420: 00040593 mv a1,s0 -8000e424: 000a8513 mv a0,s5 -8000e428: 950f60ef jal ra,80004578 <_fflush_r> -8000e42c: f20512e3 bnez a0,8000e350 <__sfvwrite_r+0x32c> -8000e430: 41390933 sub s2,s2,s3 -8000e434: de9ff06f j 8000e21c <__sfvwrite_r+0x1f8> -8000e438: 00090c93 mv s9,s2 -8000e43c: 00090d13 mv s10,s2 -8000e440: db1ff06f j 8000e1f0 <__sfvwrite_r+0x1cc> -8000e444: 00040593 mv a1,s0 -8000e448: 000a8513 mv a0,s5 -8000e44c: 92cf60ef jal ra,80004578 <_fflush_r> -8000e450: e80502e3 beqz a0,8000e2d4 <__sfvwrite_r+0x2b0> -8000e454: efdff06f j 8000e350 <__sfvwrite_r+0x32c> -8000e458: 000b8613 mv a2,s7 -8000e45c: 000c0593 mv a1,s8 -8000e460: 24c000ef jal ra,8000e6ac -8000e464: 00842783 lw a5,8(s0) -8000e468: 00042603 lw a2,0(s0) -8000e46c: 000b8913 mv s2,s7 -8000e470: 417787b3 sub a5,a5,s7 -8000e474: 01760633 add a2,a2,s7 -8000e478: 00f42423 sw a5,8(s0) -8000e47c: 00c42023 sw a2,0(s0) -8000e480: e49ff06f j 8000e2c8 <__sfvwrite_r+0x2a4> -8000e484: 000a8513 mv a0,s5 -8000e488: 3ac000ef jal ra,8000e834 <_realloc_r> -8000e48c: 00050c93 mv s9,a0 -8000e490: d40510e3 bnez a0,8000e1d0 <__sfvwrite_r+0x1ac> -8000e494: 01042583 lw a1,16(s0) -8000e498: 000a8513 mv a0,s5 -8000e49c: de8f60ef jal ra,80004a84 <_free_r> -8000e4a0: 00c41783 lh a5,12(s0) -8000e4a4: 00c00713 li a4,12 -8000e4a8: 00eaa023 sw a4,0(s5) -8000e4ac: f7f7f793 andi a5,a5,-129 -8000e4b0: ea5ff06f j 8000e354 <__sfvwrite_r+0x330> -8000e4b4: 00c00713 li a4,12 -8000e4b8: 00c41783 lh a5,12(s0) -8000e4bc: 00eaa023 sw a4,0(s5) -8000e4c0: e95ff06f j 8000e354 <__sfvwrite_r+0x330> -8000e4c4: fff00513 li a0,-1 -8000e4c8: e29ff06f j 8000e2f0 <__sfvwrite_r+0x2cc> +8000e2d4 <_isatty_r>: +8000e2d4: ff010113 addi sp,sp,-16 +8000e2d8: 00812423 sw s0,8(sp) +8000e2dc: 00912223 sw s1,4(sp) +8000e2e0: 00050413 mv s0,a0 +8000e2e4: 00058513 mv a0,a1 +8000e2e8: 00112623 sw ra,12(sp) +8000e2ec: 4201a823 sw zero,1072(gp) # 80016c38 +8000e2f0: fedf10ef jal ra,800002dc <_isatty> +8000e2f4: fff00793 li a5,-1 +8000e2f8: 00f50c63 beq a0,a5,8000e310 <_isatty_r+0x3c> +8000e2fc: 00c12083 lw ra,12(sp) +8000e300: 00812403 lw s0,8(sp) +8000e304: 00412483 lw s1,4(sp) +8000e308: 01010113 addi sp,sp,16 +8000e30c: 00008067 ret +8000e310: 4301a783 lw a5,1072(gp) # 80016c38 +8000e314: fe0784e3 beqz a5,8000e2fc <_isatty_r+0x28> +8000e318: 00c12083 lw ra,12(sp) +8000e31c: 00f42023 sw a5,0(s0) +8000e320: 00812403 lw s0,8(sp) +8000e324: 00412483 lw s1,4(sp) +8000e328: 01010113 addi sp,sp,16 +8000e32c: 00008067 ret -8000e4cc <_isatty_r>: -8000e4cc: ff010113 addi sp,sp,-16 -8000e4d0: 00812423 sw s0,8(sp) -8000e4d4: 00912223 sw s1,4(sp) -8000e4d8: 00050413 mv s0,a0 -8000e4dc: 00058513 mv a0,a1 -8000e4e0: 00112623 sw ra,12(sp) -8000e4e4: 4201a223 sw zero,1060(gp) # 80016c2c -8000e4e8: e29f10ef jal ra,80000310 <_isatty> -8000e4ec: fff00793 li a5,-1 -8000e4f0: 00f50c63 beq a0,a5,8000e508 <_isatty_r+0x3c> -8000e4f4: 00c12083 lw ra,12(sp) -8000e4f8: 00812403 lw s0,8(sp) -8000e4fc: 00412483 lw s1,4(sp) -8000e500: 01010113 addi sp,sp,16 -8000e504: 00008067 ret -8000e508: 4241a783 lw a5,1060(gp) # 80016c2c -8000e50c: fe0784e3 beqz a5,8000e4f4 <_isatty_r+0x28> -8000e510: 00c12083 lw ra,12(sp) -8000e514: 00f42023 sw a5,0(s0) -8000e518: 00812403 lw s0,8(sp) -8000e51c: 00412483 lw s1,4(sp) -8000e520: 01010113 addi sp,sp,16 -8000e524: 00008067 ret +8000e330 <_setlocale_r>: +8000e330: ff010113 addi sp,sp,-16 +8000e334: 00112623 sw ra,12(sp) +8000e338: 00812423 sw s0,8(sp) +8000e33c: 00912223 sw s1,4(sp) +8000e340: 02060c63 beqz a2,8000e378 <_setlocale_r+0x48> +8000e344: 800155b7 lui a1,0x80015 +8000e348: 4fc58593 addi a1,a1,1276 # 800154fc <__BSS_END__+0xffffe8c0> +8000e34c: 00060513 mv a0,a2 +8000e350: 00060413 mv s0,a2 +8000e354: 2ad000ef jal ra,8000ee00 +8000e358: 800154b7 lui s1,0x80015 +8000e35c: 02051263 bnez a0,8000e380 <_setlocale_r+0x50> +8000e360: 4f848513 addi a0,s1,1272 # 800154f8 <__BSS_END__+0xffffe8bc> +8000e364: 00c12083 lw ra,12(sp) +8000e368: 00812403 lw s0,8(sp) +8000e36c: 00412483 lw s1,4(sp) +8000e370: 01010113 addi sp,sp,16 +8000e374: 00008067 ret +8000e378: 800154b7 lui s1,0x80015 +8000e37c: fe5ff06f j 8000e360 <_setlocale_r+0x30> +8000e380: 4f848593 addi a1,s1,1272 # 800154f8 <__BSS_END__+0xffffe8bc> +8000e384: 00040513 mv a0,s0 +8000e388: 279000ef jal ra,8000ee00 +8000e38c: fc050ae3 beqz a0,8000e360 <_setlocale_r+0x30> +8000e390: 800155b7 lui a1,0x80015 +8000e394: c9c58593 addi a1,a1,-868 # 80014c9c <__BSS_END__+0xffffe060> +8000e398: 00040513 mv a0,s0 +8000e39c: 265000ef jal ra,8000ee00 +8000e3a0: fc0500e3 beqz a0,8000e360 <_setlocale_r+0x30> +8000e3a4: 00000513 li a0,0 +8000e3a8: fbdff06f j 8000e364 <_setlocale_r+0x34> -8000e528 <_lseek_r>: -8000e528: ff010113 addi sp,sp,-16 -8000e52c: 00058713 mv a4,a1 -8000e530: 00812423 sw s0,8(sp) -8000e534: 00912223 sw s1,4(sp) -8000e538: 00060593 mv a1,a2 -8000e53c: 00050413 mv s0,a0 -8000e540: 00068613 mv a2,a3 -8000e544: 00070513 mv a0,a4 -8000e548: 00112623 sw ra,12(sp) -8000e54c: 4201a223 sw zero,1060(gp) # 80016c2c -8000e550: df9f10ef jal ra,80000348 <_lseek> -8000e554: fff00793 li a5,-1 -8000e558: 00f50c63 beq a0,a5,8000e570 <_lseek_r+0x48> -8000e55c: 00c12083 lw ra,12(sp) -8000e560: 00812403 lw s0,8(sp) -8000e564: 00412483 lw s1,4(sp) -8000e568: 01010113 addi sp,sp,16 -8000e56c: 00008067 ret -8000e570: 4241a783 lw a5,1060(gp) # 80016c2c -8000e574: fe0784e3 beqz a5,8000e55c <_lseek_r+0x34> -8000e578: 00c12083 lw ra,12(sp) -8000e57c: 00f42023 sw a5,0(s0) -8000e580: 00812403 lw s0,8(sp) -8000e584: 00412483 lw s1,4(sp) -8000e588: 01010113 addi sp,sp,16 -8000e58c: 00008067 ret +8000e3ac <__locale_mb_cur_max>: +8000e3ac: 2f01c503 lbu a0,752(gp) # 80016af8 <__global_locale+0x128> +8000e3b0: 00008067 ret -8000e590 : -8000e590: 00a5c7b3 xor a5,a1,a0 -8000e594: 0037f793 andi a5,a5,3 -8000e598: 00c508b3 add a7,a0,a2 -8000e59c: 06079263 bnez a5,8000e600 -8000e5a0: 00300793 li a5,3 -8000e5a4: 04c7fe63 bgeu a5,a2,8000e600 -8000e5a8: 00357793 andi a5,a0,3 -8000e5ac: 00050713 mv a4,a0 -8000e5b0: 06079863 bnez a5,8000e620 -8000e5b4: ffc8f613 andi a2,a7,-4 -8000e5b8: fe060793 addi a5,a2,-32 -8000e5bc: 08f76c63 bltu a4,a5,8000e654 -8000e5c0: 02c77c63 bgeu a4,a2,8000e5f8 -8000e5c4: 00058693 mv a3,a1 -8000e5c8: 00070793 mv a5,a4 -8000e5cc: 0006a803 lw a6,0(a3) # 2000 <_start-0x7fffe000> -8000e5d0: 00478793 addi a5,a5,4 -8000e5d4: 00468693 addi a3,a3,4 -8000e5d8: ff07ae23 sw a6,-4(a5) -8000e5dc: fec7e8e3 bltu a5,a2,8000e5cc -8000e5e0: fff60793 addi a5,a2,-1 -8000e5e4: 40e787b3 sub a5,a5,a4 -8000e5e8: ffc7f793 andi a5,a5,-4 -8000e5ec: 00478793 addi a5,a5,4 -8000e5f0: 00f70733 add a4,a4,a5 -8000e5f4: 00f585b3 add a1,a1,a5 -8000e5f8: 01176863 bltu a4,a7,8000e608 -8000e5fc: 00008067 ret -8000e600: 00050713 mv a4,a0 -8000e604: ff157ce3 bgeu a0,a7,8000e5fc -8000e608: 0005c783 lbu a5,0(a1) -8000e60c: 00170713 addi a4,a4,1 -8000e610: 00158593 addi a1,a1,1 -8000e614: fef70fa3 sb a5,-1(a4) -8000e618: ff1768e3 bltu a4,a7,8000e608 -8000e61c: 00008067 ret -8000e620: 0005c683 lbu a3,0(a1) -8000e624: 00170713 addi a4,a4,1 -8000e628: 00377793 andi a5,a4,3 -8000e62c: fed70fa3 sb a3,-1(a4) -8000e630: 00158593 addi a1,a1,1 -8000e634: f80780e3 beqz a5,8000e5b4 -8000e638: 0005c683 lbu a3,0(a1) -8000e63c: 00170713 addi a4,a4,1 -8000e640: 00377793 andi a5,a4,3 -8000e644: fed70fa3 sb a3,-1(a4) -8000e648: 00158593 addi a1,a1,1 -8000e64c: fc079ae3 bnez a5,8000e620 -8000e650: f65ff06f j 8000e5b4 -8000e654: 0045a683 lw a3,4(a1) -8000e658: 0005a283 lw t0,0(a1) -8000e65c: 0085af83 lw t6,8(a1) -8000e660: 00c5af03 lw t5,12(a1) -8000e664: 0105ae83 lw t4,16(a1) -8000e668: 0145ae03 lw t3,20(a1) -8000e66c: 0185a303 lw t1,24(a1) -8000e670: 01c5a803 lw a6,28(a1) -8000e674: 00d72223 sw a3,4(a4) -8000e678: 0205a683 lw a3,32(a1) -8000e67c: 00572023 sw t0,0(a4) -8000e680: 01f72423 sw t6,8(a4) -8000e684: 01e72623 sw t5,12(a4) -8000e688: 01d72823 sw t4,16(a4) -8000e68c: 01c72a23 sw t3,20(a4) -8000e690: 00672c23 sw t1,24(a4) -8000e694: 01072e23 sw a6,28(a4) -8000e698: 02d72023 sw a3,32(a4) -8000e69c: 02470713 addi a4,a4,36 -8000e6a0: 02458593 addi a1,a1,36 -8000e6a4: faf768e3 bltu a4,a5,8000e654 -8000e6a8: f19ff06f j 8000e5c0 +8000e3b4 : +8000e3b4: 00050793 mv a5,a0 +8000e3b8: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +8000e3bc: 00058613 mv a2,a1 +8000e3c0: 00078593 mv a1,a5 +8000e3c4: f6dff06f j 8000e330 <_setlocale_r> -8000e6ac : -8000e6ac: 02a5f663 bgeu a1,a0,8000e6d8 -8000e6b0: 00c587b3 add a5,a1,a2 -8000e6b4: 02f57263 bgeu a0,a5,8000e6d8 -8000e6b8: 00c50733 add a4,a0,a2 -8000e6bc: 0e060a63 beqz a2,8000e7b0 -8000e6c0: fff7c683 lbu a3,-1(a5) -8000e6c4: fff78793 addi a5,a5,-1 -8000e6c8: fff70713 addi a4,a4,-1 -8000e6cc: 00d70023 sb a3,0(a4) -8000e6d0: fef598e3 bne a1,a5,8000e6c0 -8000e6d4: 00008067 ret -8000e6d8: 00f00793 li a5,15 -8000e6dc: 02c7e863 bltu a5,a2,8000e70c -8000e6e0: 00050793 mv a5,a0 -8000e6e4: fff60693 addi a3,a2,-1 -8000e6e8: 0c060c63 beqz a2,8000e7c0 -8000e6ec: 00168693 addi a3,a3,1 -8000e6f0: 00d786b3 add a3,a5,a3 -8000e6f4: 0005c703 lbu a4,0(a1) -8000e6f8: 00178793 addi a5,a5,1 -8000e6fc: 00158593 addi a1,a1,1 -8000e700: fee78fa3 sb a4,-1(a5) -8000e704: fed798e3 bne a5,a3,8000e6f4 -8000e708: 00008067 ret -8000e70c: 00a5e7b3 or a5,a1,a0 -8000e710: 0037f793 andi a5,a5,3 -8000e714: 0a079063 bnez a5,8000e7b4 -8000e718: ff060893 addi a7,a2,-16 -8000e71c: ff08f893 andi a7,a7,-16 -8000e720: 01088893 addi a7,a7,16 -8000e724: 01150833 add a6,a0,a7 -8000e728: 00058713 mv a4,a1 -8000e72c: 00050793 mv a5,a0 -8000e730: 00072683 lw a3,0(a4) -8000e734: 01070713 addi a4,a4,16 -8000e738: 01078793 addi a5,a5,16 -8000e73c: fed7a823 sw a3,-16(a5) -8000e740: ff472683 lw a3,-12(a4) -8000e744: fed7aa23 sw a3,-12(a5) -8000e748: ff872683 lw a3,-8(a4) -8000e74c: fed7ac23 sw a3,-8(a5) -8000e750: ffc72683 lw a3,-4(a4) -8000e754: fed7ae23 sw a3,-4(a5) -8000e758: fcf81ce3 bne a6,a5,8000e730 -8000e75c: 00c67713 andi a4,a2,12 -8000e760: 011585b3 add a1,a1,a7 -8000e764: 00f67813 andi a6,a2,15 -8000e768: 04070e63 beqz a4,8000e7c4 -8000e76c: 00058713 mv a4,a1 -8000e770: 00078893 mv a7,a5 -8000e774: 00300e13 li t3,3 -8000e778: 00072303 lw t1,0(a4) -8000e77c: 00470713 addi a4,a4,4 -8000e780: 40e806b3 sub a3,a6,a4 -8000e784: 0068a023 sw t1,0(a7) -8000e788: 00d586b3 add a3,a1,a3 -8000e78c: 00488893 addi a7,a7,4 -8000e790: fede64e3 bltu t3,a3,8000e778 -8000e794: ffc80713 addi a4,a6,-4 -8000e798: ffc77713 andi a4,a4,-4 -8000e79c: 00470713 addi a4,a4,4 -8000e7a0: 00367613 andi a2,a2,3 -8000e7a4: 00e787b3 add a5,a5,a4 -8000e7a8: 00e585b3 add a1,a1,a4 -8000e7ac: f39ff06f j 8000e6e4 -8000e7b0: 00008067 ret -8000e7b4: fff60693 addi a3,a2,-1 -8000e7b8: 00050793 mv a5,a0 -8000e7bc: f31ff06f j 8000e6ec -8000e7c0: 00008067 ret -8000e7c4: 00080613 mv a2,a6 -8000e7c8: f1dff06f j 8000e6e4 +8000e3c8 <_lseek_r>: +8000e3c8: ff010113 addi sp,sp,-16 +8000e3cc: 00058713 mv a4,a1 +8000e3d0: 00812423 sw s0,8(sp) +8000e3d4: 00912223 sw s1,4(sp) +8000e3d8: 00060593 mv a1,a2 +8000e3dc: 00050413 mv s0,a0 +8000e3e0: 00068613 mv a2,a3 +8000e3e4: 00070513 mv a0,a4 +8000e3e8: 00112623 sw ra,12(sp) +8000e3ec: 4201a823 sw zero,1072(gp) # 80016c38 +8000e3f0: f11f10ef jal ra,80000300 <_lseek> +8000e3f4: fff00793 li a5,-1 +8000e3f8: 00f50c63 beq a0,a5,8000e410 <_lseek_r+0x48> +8000e3fc: 00c12083 lw ra,12(sp) +8000e400: 00812403 lw s0,8(sp) +8000e404: 00412483 lw s1,4(sp) +8000e408: 01010113 addi sp,sp,16 +8000e40c: 00008067 ret +8000e410: 4301a783 lw a5,1072(gp) # 80016c38 +8000e414: fe0784e3 beqz a5,8000e3fc <_lseek_r+0x34> +8000e418: 00c12083 lw ra,12(sp) +8000e41c: 00f42023 sw a5,0(s0) +8000e420: 00812403 lw s0,8(sp) +8000e424: 00412483 lw s1,4(sp) +8000e428: 01010113 addi sp,sp,16 +8000e42c: 00008067 ret -8000e7cc <_read_r>: -8000e7cc: ff010113 addi sp,sp,-16 -8000e7d0: 00058713 mv a4,a1 -8000e7d4: 00812423 sw s0,8(sp) -8000e7d8: 00912223 sw s1,4(sp) -8000e7dc: 00060593 mv a1,a2 -8000e7e0: 00050413 mv s0,a0 -8000e7e4: 00068613 mv a2,a3 -8000e7e8: 00070513 mv a0,a4 -8000e7ec: 00112623 sw ra,12(sp) -8000e7f0: 4201a223 sw zero,1060(gp) # 80016c2c -8000e7f4: c1df10ef jal ra,80000410 <_read> -8000e7f8: fff00793 li a5,-1 -8000e7fc: 00f50c63 beq a0,a5,8000e814 <_read_r+0x48> -8000e800: 00c12083 lw ra,12(sp) -8000e804: 00812403 lw s0,8(sp) -8000e808: 00412483 lw s1,4(sp) -8000e80c: 01010113 addi sp,sp,16 -8000e810: 00008067 ret -8000e814: 4241a783 lw a5,1060(gp) # 80016c2c -8000e818: fe0784e3 beqz a5,8000e800 <_read_r+0x34> -8000e81c: 00c12083 lw ra,12(sp) -8000e820: 00f42023 sw a5,0(s0) -8000e824: 00812403 lw s0,8(sp) -8000e828: 00412483 lw s1,4(sp) -8000e82c: 01010113 addi sp,sp,16 -8000e830: 00008067 ret +8000e430 <_mbtowc_r>: +8000e430: 2ac1a303 lw t1,684(gp) # 80016ab4 <__global_locale+0xe4> +8000e434: 00030067 jr t1 -8000e834 <_realloc_r>: -8000e834: fd010113 addi sp,sp,-48 -8000e838: 03212023 sw s2,32(sp) -8000e83c: 02112623 sw ra,44(sp) -8000e840: 02812423 sw s0,40(sp) -8000e844: 02912223 sw s1,36(sp) -8000e848: 01312e23 sw s3,28(sp) -8000e84c: 01412c23 sw s4,24(sp) -8000e850: 01512a23 sw s5,20(sp) -8000e854: 01612823 sw s6,16(sp) -8000e858: 01712623 sw s7,12(sp) -8000e85c: 01812423 sw s8,8(sp) -8000e860: 00060913 mv s2,a2 -8000e864: 22058263 beqz a1,8000ea88 <_realloc_r+0x254> -8000e868: 00058413 mv s0,a1 -8000e86c: 00050993 mv s3,a0 -8000e870: d5df90ef jal ra,800085cc <__malloc_lock> -8000e874: 00b90493 addi s1,s2,11 -8000e878: 01600793 li a5,22 -8000e87c: 0e97fc63 bgeu a5,s1,8000e974 <_realloc_r+0x140> -8000e880: ff84f493 andi s1,s1,-8 -8000e884: 00048713 mv a4,s1 -8000e888: 0e04cc63 bltz s1,8000e980 <_realloc_r+0x14c> -8000e88c: 0f24ea63 bltu s1,s2,8000e980 <_realloc_r+0x14c> -8000e890: ffc42783 lw a5,-4(s0) -8000e894: ff840a93 addi s5,s0,-8 -8000e898: ffc7fa13 andi s4,a5,-4 -8000e89c: 014a8b33 add s6,s5,s4 -8000e8a0: 18ea5a63 bge s4,a4,8000ea34 <_realloc_r+0x200> -8000e8a4: f2c18b93 addi s7,gp,-212 # 80016734 <__malloc_av_> -8000e8a8: 008ba603 lw a2,8(s7) -8000e8ac: 004b2683 lw a3,4(s6) # 80000004 <__BSS_END__+0xfffe93d4> -8000e8b0: 23660e63 beq a2,s6,8000eaec <_realloc_r+0x2b8> -8000e8b4: ffe6f613 andi a2,a3,-2 -8000e8b8: 00cb0633 add a2,s6,a2 -8000e8bc: 00462603 lw a2,4(a2) -8000e8c0: 00167613 andi a2,a2,1 -8000e8c4: 1a061463 bnez a2,8000ea6c <_realloc_r+0x238> -8000e8c8: ffc6f693 andi a3,a3,-4 -8000e8cc: 00da0633 add a2,s4,a3 -8000e8d0: 32e65e63 bge a2,a4,8000ec0c <_realloc_r+0x3d8> -8000e8d4: 0017f793 andi a5,a5,1 -8000e8d8: 02079463 bnez a5,8000e900 <_realloc_r+0xcc> -8000e8dc: ff842c03 lw s8,-8(s0) -8000e8e0: 418a8c33 sub s8,s5,s8 -8000e8e4: 004c2783 lw a5,4(s8) -8000e8e8: ffc7f793 andi a5,a5,-4 -8000e8ec: 00d786b3 add a3,a5,a3 -8000e8f0: 01468bb3 add s7,a3,s4 -8000e8f4: 34ebda63 bge s7,a4,8000ec48 <_realloc_r+0x414> -8000e8f8: 00fa0bb3 add s7,s4,a5 -8000e8fc: 0cebd263 bge s7,a4,8000e9c0 <_realloc_r+0x18c> -8000e900: 00090593 mv a1,s2 -8000e904: 00098513 mv a0,s3 -8000e908: be8f90ef jal ra,80007cf0 <_malloc_r> -8000e90c: 00050913 mv s2,a0 -8000e910: 04050c63 beqz a0,8000e968 <_realloc_r+0x134> -8000e914: ffc42783 lw a5,-4(s0) -8000e918: ff850713 addi a4,a0,-8 -8000e91c: ffe7f793 andi a5,a5,-2 -8000e920: 00fa87b3 add a5,s5,a5 -8000e924: 30e78263 beq a5,a4,8000ec28 <_realloc_r+0x3f4> -8000e928: ffca0613 addi a2,s4,-4 -8000e92c: 02400793 li a5,36 -8000e930: 30c7e663 bltu a5,a2,8000ec3c <_realloc_r+0x408> -8000e934: 01300713 li a4,19 -8000e938: 00042683 lw a3,0(s0) -8000e93c: 26c76c63 bltu a4,a2,8000ebb4 <_realloc_r+0x380> -8000e940: 00050793 mv a5,a0 -8000e944: 00040713 mv a4,s0 -8000e948: 00d7a023 sw a3,0(a5) -8000e94c: 00472683 lw a3,4(a4) -8000e950: 00d7a223 sw a3,4(a5) -8000e954: 00872703 lw a4,8(a4) -8000e958: 00e7a423 sw a4,8(a5) -8000e95c: 00040593 mv a1,s0 -8000e960: 00098513 mv a0,s3 -8000e964: 920f60ef jal ra,80004a84 <_free_r> -8000e968: 00098513 mv a0,s3 -8000e96c: c65f90ef jal ra,800085d0 <__malloc_unlock> -8000e970: 01c0006f j 8000e98c <_realloc_r+0x158> -8000e974: 01000493 li s1,16 -8000e978: 01000713 li a4,16 -8000e97c: f124fae3 bgeu s1,s2,8000e890 <_realloc_r+0x5c> -8000e980: 00c00793 li a5,12 -8000e984: 00f9a023 sw a5,0(s3) -8000e988: 00000913 li s2,0 -8000e98c: 02c12083 lw ra,44(sp) -8000e990: 02812403 lw s0,40(sp) -8000e994: 02412483 lw s1,36(sp) -8000e998: 01c12983 lw s3,28(sp) -8000e99c: 01812a03 lw s4,24(sp) -8000e9a0: 01412a83 lw s5,20(sp) -8000e9a4: 01012b03 lw s6,16(sp) -8000e9a8: 00c12b83 lw s7,12(sp) -8000e9ac: 00812c03 lw s8,8(sp) -8000e9b0: 00090513 mv a0,s2 -8000e9b4: 02012903 lw s2,32(sp) -8000e9b8: 03010113 addi sp,sp,48 -8000e9bc: 00008067 ret -8000e9c0: 00cc2783 lw a5,12(s8) -8000e9c4: 008c2703 lw a4,8(s8) -8000e9c8: ffca0613 addi a2,s4,-4 -8000e9cc: 02400693 li a3,36 -8000e9d0: 00f72623 sw a5,12(a4) -8000e9d4: 00e7a423 sw a4,8(a5) -8000e9d8: 008c0913 addi s2,s8,8 -8000e9dc: 017c0b33 add s6,s8,s7 -8000e9e0: 2ec6e463 bltu a3,a2,8000ecc8 <_realloc_r+0x494> -8000e9e4: 01300593 li a1,19 -8000e9e8: 00042703 lw a4,0(s0) -8000e9ec: 00090793 mv a5,s2 -8000e9f0: 02c5f263 bgeu a1,a2,8000ea14 <_realloc_r+0x1e0> -8000e9f4: 00ec2423 sw a4,8(s8) -8000e9f8: 00442703 lw a4,4(s0) -8000e9fc: 01b00793 li a5,27 -8000ea00: 00ec2623 sw a4,12(s8) -8000ea04: 30c7e263 bltu a5,a2,8000ed08 <_realloc_r+0x4d4> -8000ea08: 00842703 lw a4,8(s0) -8000ea0c: 010c0793 addi a5,s8,16 -8000ea10: 00840413 addi s0,s0,8 -8000ea14: 00e7a023 sw a4,0(a5) -8000ea18: 00442703 lw a4,4(s0) -8000ea1c: 000b8a13 mv s4,s7 -8000ea20: 000c0a93 mv s5,s8 -8000ea24: 00e7a223 sw a4,4(a5) -8000ea28: 00842703 lw a4,8(s0) -8000ea2c: 00090413 mv s0,s2 -8000ea30: 00e7a423 sw a4,8(a5) -8000ea34: 004aa783 lw a5,4(s5) -8000ea38: 409a0733 sub a4,s4,s1 -8000ea3c: 00f00693 li a3,15 -8000ea40: 0017f793 andi a5,a5,1 -8000ea44: 06e6ec63 bltu a3,a4,8000eabc <_realloc_r+0x288> -8000ea48: 00fa67b3 or a5,s4,a5 -8000ea4c: 00faa223 sw a5,4(s5) -8000ea50: 004b2783 lw a5,4(s6) -8000ea54: 0017e793 ori a5,a5,1 -8000ea58: 00fb2223 sw a5,4(s6) -8000ea5c: 00098513 mv a0,s3 -8000ea60: b71f90ef jal ra,800085d0 <__malloc_unlock> -8000ea64: 00040913 mv s2,s0 -8000ea68: f25ff06f j 8000e98c <_realloc_r+0x158> -8000ea6c: 0017f793 andi a5,a5,1 -8000ea70: e80798e3 bnez a5,8000e900 <_realloc_r+0xcc> -8000ea74: ff842c03 lw s8,-8(s0) -8000ea78: 418a8c33 sub s8,s5,s8 -8000ea7c: 004c2783 lw a5,4(s8) -8000ea80: ffc7f793 andi a5,a5,-4 -8000ea84: e75ff06f j 8000e8f8 <_realloc_r+0xc4> -8000ea88: 02812403 lw s0,40(sp) -8000ea8c: 02c12083 lw ra,44(sp) -8000ea90: 02412483 lw s1,36(sp) -8000ea94: 02012903 lw s2,32(sp) -8000ea98: 01c12983 lw s3,28(sp) -8000ea9c: 01812a03 lw s4,24(sp) -8000eaa0: 01412a83 lw s5,20(sp) -8000eaa4: 01012b03 lw s6,16(sp) -8000eaa8: 00c12b83 lw s7,12(sp) -8000eaac: 00812c03 lw s8,8(sp) -8000eab0: 00060593 mv a1,a2 -8000eab4: 03010113 addi sp,sp,48 -8000eab8: a38f906f j 80007cf0 <_malloc_r> -8000eabc: 0097e7b3 or a5,a5,s1 -8000eac0: 00faa223 sw a5,4(s5) -8000eac4: 009a85b3 add a1,s5,s1 -8000eac8: 00176713 ori a4,a4,1 -8000eacc: 00e5a223 sw a4,4(a1) -8000ead0: 004b2783 lw a5,4(s6) -8000ead4: 00858593 addi a1,a1,8 -8000ead8: 00098513 mv a0,s3 -8000eadc: 0017e793 ori a5,a5,1 -8000eae0: 00fb2223 sw a5,4(s6) -8000eae4: fa1f50ef jal ra,80004a84 <_free_r> -8000eae8: f75ff06f j 8000ea5c <_realloc_r+0x228> -8000eaec: ffc6f693 andi a3,a3,-4 -8000eaf0: 00da0633 add a2,s4,a3 -8000eaf4: 01048593 addi a1,s1,16 -8000eaf8: 0eb65063 bge a2,a1,8000ebd8 <_realloc_r+0x3a4> -8000eafc: 0017f793 andi a5,a5,1 -8000eb00: e00790e3 bnez a5,8000e900 <_realloc_r+0xcc> -8000eb04: ff842c03 lw s8,-8(s0) -8000eb08: 418a8c33 sub s8,s5,s8 -8000eb0c: 004c2783 lw a5,4(s8) -8000eb10: ffc7f793 andi a5,a5,-4 -8000eb14: 00d786b3 add a3,a5,a3 -8000eb18: 01468b33 add s6,a3,s4 -8000eb1c: dcbb4ee3 blt s6,a1,8000e8f8 <_realloc_r+0xc4> -8000eb20: 00cc2783 lw a5,12(s8) -8000eb24: 008c2703 lw a4,8(s8) -8000eb28: ffca0613 addi a2,s4,-4 -8000eb2c: 02400693 li a3,36 -8000eb30: 00f72623 sw a5,12(a4) -8000eb34: 00e7a423 sw a4,8(a5) -8000eb38: 008c0913 addi s2,s8,8 -8000eb3c: 20c6ee63 bltu a3,a2,8000ed58 <_realloc_r+0x524> -8000eb40: 01300593 li a1,19 -8000eb44: 00042703 lw a4,0(s0) -8000eb48: 00090793 mv a5,s2 -8000eb4c: 02c5f263 bgeu a1,a2,8000eb70 <_realloc_r+0x33c> -8000eb50: 00ec2423 sw a4,8(s8) -8000eb54: 00442703 lw a4,4(s0) -8000eb58: 01b00793 li a5,27 -8000eb5c: 00ec2623 sw a4,12(s8) -8000eb60: 20c7e463 bltu a5,a2,8000ed68 <_realloc_r+0x534> -8000eb64: 00842703 lw a4,8(s0) -8000eb68: 010c0793 addi a5,s8,16 -8000eb6c: 00840413 addi s0,s0,8 -8000eb70: 00e7a023 sw a4,0(a5) -8000eb74: 00442703 lw a4,4(s0) -8000eb78: 00e7a223 sw a4,4(a5) -8000eb7c: 00842703 lw a4,8(s0) -8000eb80: 00e7a423 sw a4,8(a5) -8000eb84: 009c0733 add a4,s8,s1 -8000eb88: 409b07b3 sub a5,s6,s1 -8000eb8c: 00eba423 sw a4,8(s7) -8000eb90: 0017e793 ori a5,a5,1 -8000eb94: 00f72223 sw a5,4(a4) -8000eb98: 004c2783 lw a5,4(s8) -8000eb9c: 00098513 mv a0,s3 -8000eba0: 0017f793 andi a5,a5,1 -8000eba4: 0097e4b3 or s1,a5,s1 -8000eba8: 009c2223 sw s1,4(s8) -8000ebac: a25f90ef jal ra,800085d0 <__malloc_unlock> -8000ebb0: dddff06f j 8000e98c <_realloc_r+0x158> -8000ebb4: 00d52023 sw a3,0(a0) -8000ebb8: 00442683 lw a3,4(s0) -8000ebbc: 01b00713 li a4,27 -8000ebc0: 00d52223 sw a3,4(a0) -8000ebc4: 12c76063 bltu a4,a2,8000ece4 <_realloc_r+0x4b0> -8000ebc8: 00842683 lw a3,8(s0) -8000ebcc: 00840713 addi a4,s0,8 -8000ebd0: 00850793 addi a5,a0,8 -8000ebd4: d75ff06f j 8000e948 <_realloc_r+0x114> -8000ebd8: 009a8ab3 add s5,s5,s1 -8000ebdc: 409607b3 sub a5,a2,s1 -8000ebe0: 015ba423 sw s5,8(s7) -8000ebe4: 0017e793 ori a5,a5,1 -8000ebe8: 00faa223 sw a5,4(s5) -8000ebec: ffc42783 lw a5,-4(s0) -8000ebf0: 00098513 mv a0,s3 -8000ebf4: 00040913 mv s2,s0 -8000ebf8: 0017f793 andi a5,a5,1 -8000ebfc: 0097e4b3 or s1,a5,s1 -8000ec00: fe942e23 sw s1,-4(s0) -8000ec04: 9cdf90ef jal ra,800085d0 <__malloc_unlock> -8000ec08: d85ff06f j 8000e98c <_realloc_r+0x158> -8000ec0c: 00cb2783 lw a5,12(s6) -8000ec10: 008b2703 lw a4,8(s6) -8000ec14: 00060a13 mv s4,a2 -8000ec18: 00ca8b33 add s6,s5,a2 -8000ec1c: 00f72623 sw a5,12(a4) -8000ec20: 00e7a423 sw a4,8(a5) -8000ec24: e11ff06f j 8000ea34 <_realloc_r+0x200> -8000ec28: ffc52783 lw a5,-4(a0) -8000ec2c: ffc7f793 andi a5,a5,-4 -8000ec30: 00fa0a33 add s4,s4,a5 -8000ec34: 014a8b33 add s6,s5,s4 -8000ec38: dfdff06f j 8000ea34 <_realloc_r+0x200> -8000ec3c: 00040593 mv a1,s0 -8000ec40: a6dff0ef jal ra,8000e6ac -8000ec44: d19ff06f j 8000e95c <_realloc_r+0x128> -8000ec48: 00cb2783 lw a5,12(s6) -8000ec4c: 008b2703 lw a4,8(s6) -8000ec50: ffca0613 addi a2,s4,-4 -8000ec54: 02400693 li a3,36 -8000ec58: 00f72623 sw a5,12(a4) -8000ec5c: 00e7a423 sw a4,8(a5) -8000ec60: 008c2703 lw a4,8(s8) -8000ec64: 00cc2783 lw a5,12(s8) -8000ec68: 008c0913 addi s2,s8,8 -8000ec6c: 017c0b33 add s6,s8,s7 -8000ec70: 00f72623 sw a5,12(a4) -8000ec74: 00e7a423 sw a4,8(a5) -8000ec78: 04c6e863 bltu a3,a2,8000ecc8 <_realloc_r+0x494> -8000ec7c: 01300693 li a3,19 -8000ec80: 00042703 lw a4,0(s0) -8000ec84: 00090793 mv a5,s2 -8000ec88: d8c6f6e3 bgeu a3,a2,8000ea14 <_realloc_r+0x1e0> -8000ec8c: 00ec2423 sw a4,8(s8) -8000ec90: 00442703 lw a4,4(s0) -8000ec94: 01b00793 li a5,27 -8000ec98: 00ec2623 sw a4,12(s8) -8000ec9c: 00842703 lw a4,8(s0) -8000eca0: d6c7f6e3 bgeu a5,a2,8000ea0c <_realloc_r+0x1d8> -8000eca4: 00ec2823 sw a4,16(s8) -8000eca8: 00c42703 lw a4,12(s0) -8000ecac: 02400793 li a5,36 -8000ecb0: 00ec2a23 sw a4,20(s8) -8000ecb4: 01042703 lw a4,16(s0) -8000ecb8: 06f60463 beq a2,a5,8000ed20 <_realloc_r+0x4ec> -8000ecbc: 018c0793 addi a5,s8,24 -8000ecc0: 01040413 addi s0,s0,16 -8000ecc4: d51ff06f j 8000ea14 <_realloc_r+0x1e0> -8000ecc8: 00040593 mv a1,s0 -8000eccc: 00090513 mv a0,s2 -8000ecd0: 9ddff0ef jal ra,8000e6ac -8000ecd4: 00090413 mv s0,s2 -8000ecd8: 000b8a13 mv s4,s7 -8000ecdc: 000c0a93 mv s5,s8 -8000ece0: d55ff06f j 8000ea34 <_realloc_r+0x200> -8000ece4: 00842703 lw a4,8(s0) -8000ece8: 00e52423 sw a4,8(a0) -8000ecec: 00c42703 lw a4,12(s0) -8000ecf0: 00e52623 sw a4,12(a0) -8000ecf4: 01042683 lw a3,16(s0) -8000ecf8: 04f60263 beq a2,a5,8000ed3c <_realloc_r+0x508> -8000ecfc: 01040713 addi a4,s0,16 -8000ed00: 01050793 addi a5,a0,16 -8000ed04: c45ff06f j 8000e948 <_realloc_r+0x114> -8000ed08: 00842783 lw a5,8(s0) -8000ed0c: 00fc2823 sw a5,16(s8) -8000ed10: 00c42783 lw a5,12(s0) -8000ed14: 00fc2a23 sw a5,20(s8) -8000ed18: 01042703 lw a4,16(s0) -8000ed1c: fad610e3 bne a2,a3,8000ecbc <_realloc_r+0x488> -8000ed20: 00ec2c23 sw a4,24(s8) -8000ed24: 01442703 lw a4,20(s0) -8000ed28: 020c0793 addi a5,s8,32 -8000ed2c: 01840413 addi s0,s0,24 -8000ed30: 00ec2e23 sw a4,28(s8) -8000ed34: 00042703 lw a4,0(s0) -8000ed38: cddff06f j 8000ea14 <_realloc_r+0x1e0> -8000ed3c: 00d52823 sw a3,16(a0) -8000ed40: 01442683 lw a3,20(s0) -8000ed44: 01840713 addi a4,s0,24 -8000ed48: 01850793 addi a5,a0,24 -8000ed4c: 00d52a23 sw a3,20(a0) -8000ed50: 01842683 lw a3,24(s0) -8000ed54: bf5ff06f j 8000e948 <_realloc_r+0x114> -8000ed58: 00040593 mv a1,s0 -8000ed5c: 00090513 mv a0,s2 -8000ed60: 94dff0ef jal ra,8000e6ac -8000ed64: e21ff06f j 8000eb84 <_realloc_r+0x350> -8000ed68: 00842783 lw a5,8(s0) -8000ed6c: 00fc2823 sw a5,16(s8) -8000ed70: 00c42783 lw a5,12(s0) -8000ed74: 00fc2a23 sw a5,20(s8) -8000ed78: 01042703 lw a4,16(s0) -8000ed7c: 00d60863 beq a2,a3,8000ed8c <_realloc_r+0x558> -8000ed80: 018c0793 addi a5,s8,24 -8000ed84: 01040413 addi s0,s0,16 -8000ed88: de9ff06f j 8000eb70 <_realloc_r+0x33c> -8000ed8c: 00ec2c23 sw a4,24(s8) -8000ed90: 01442703 lw a4,20(s0) -8000ed94: 020c0793 addi a5,s8,32 -8000ed98: 01840413 addi s0,s0,24 -8000ed9c: 00ec2e23 sw a4,28(s8) -8000eda0: 00042703 lw a4,0(s0) -8000eda4: dcdff06f j 8000eb70 <_realloc_r+0x33c> +8000e438 <__ascii_mbtowc>: +8000e438: 02058063 beqz a1,8000e458 <__ascii_mbtowc+0x20> +8000e43c: 04060263 beqz a2,8000e480 <__ascii_mbtowc+0x48> +8000e440: 04068863 beqz a3,8000e490 <__ascii_mbtowc+0x58> +8000e444: 00064783 lbu a5,0(a2) +8000e448: 00f5a023 sw a5,0(a1) +8000e44c: 00064503 lbu a0,0(a2) +8000e450: 00a03533 snez a0,a0 +8000e454: 00008067 ret +8000e458: ff010113 addi sp,sp,-16 +8000e45c: 00c10593 addi a1,sp,12 +8000e460: 02060463 beqz a2,8000e488 <__ascii_mbtowc+0x50> +8000e464: 02068a63 beqz a3,8000e498 <__ascii_mbtowc+0x60> +8000e468: 00064783 lbu a5,0(a2) +8000e46c: 00f5a023 sw a5,0(a1) +8000e470: 00064503 lbu a0,0(a2) +8000e474: 00a03533 snez a0,a0 +8000e478: 01010113 addi sp,sp,16 +8000e47c: 00008067 ret +8000e480: 00000513 li a0,0 +8000e484: 00008067 ret +8000e488: 00000513 li a0,0 +8000e48c: fedff06f j 8000e478 <__ascii_mbtowc+0x40> +8000e490: ffe00513 li a0,-2 +8000e494: 00008067 ret +8000e498: ffe00513 li a0,-2 +8000e49c: fddff06f j 8000e478 <__ascii_mbtowc+0x40> -8000eda8 : -8000eda8: ff010113 addi sp,sp,-16 -8000edac: 00812423 sw s0,8(sp) -8000edb0: 00058413 mv s0,a1 -8000edb4: 0005a583 lw a1,0(a1) -8000edb8: 00912223 sw s1,4(sp) -8000edbc: 00112623 sw ra,12(sp) -8000edc0: 00050493 mv s1,a0 -8000edc4: 00058463 beqz a1,8000edcc -8000edc8: fe1ff0ef jal ra,8000eda8 -8000edcc: 00040593 mv a1,s0 -8000edd0: 00812403 lw s0,8(sp) -8000edd4: 00c12083 lw ra,12(sp) -8000edd8: 00048513 mv a0,s1 -8000eddc: 00412483 lw s1,4(sp) -8000ede0: 01010113 addi sp,sp,16 -8000ede4: ca1f506f j 80004a84 <_free_r> +8000e4a0 : +8000e4a0: 00a5c7b3 xor a5,a1,a0 +8000e4a4: 0037f793 andi a5,a5,3 +8000e4a8: 00c508b3 add a7,a0,a2 +8000e4ac: 06079263 bnez a5,8000e510 +8000e4b0: 00300793 li a5,3 +8000e4b4: 04c7fe63 bgeu a5,a2,8000e510 +8000e4b8: 00357793 andi a5,a0,3 +8000e4bc: 00050713 mv a4,a0 +8000e4c0: 06079863 bnez a5,8000e530 +8000e4c4: ffc8f613 andi a2,a7,-4 +8000e4c8: fe060793 addi a5,a2,-32 +8000e4cc: 08f76c63 bltu a4,a5,8000e564 +8000e4d0: 02c77c63 bgeu a4,a2,8000e508 +8000e4d4: 00058693 mv a3,a1 +8000e4d8: 00070793 mv a5,a4 +8000e4dc: 0006a803 lw a6,0(a3) # 2000 <_start-0x7fffe000> +8000e4e0: 00478793 addi a5,a5,4 +8000e4e4: 00468693 addi a3,a3,4 +8000e4e8: ff07ae23 sw a6,-4(a5) +8000e4ec: fec7e8e3 bltu a5,a2,8000e4dc +8000e4f0: fff60793 addi a5,a2,-1 +8000e4f4: 40e787b3 sub a5,a5,a4 +8000e4f8: ffc7f793 andi a5,a5,-4 +8000e4fc: 00478793 addi a5,a5,4 +8000e500: 00f70733 add a4,a4,a5 +8000e504: 00f585b3 add a1,a1,a5 +8000e508: 01176863 bltu a4,a7,8000e518 +8000e50c: 00008067 ret +8000e510: 00050713 mv a4,a0 +8000e514: ff157ce3 bgeu a0,a7,8000e50c +8000e518: 0005c783 lbu a5,0(a1) +8000e51c: 00170713 addi a4,a4,1 +8000e520: 00158593 addi a1,a1,1 +8000e524: fef70fa3 sb a5,-1(a4) +8000e528: ff1768e3 bltu a4,a7,8000e518 +8000e52c: 00008067 ret +8000e530: 0005c683 lbu a3,0(a1) +8000e534: 00170713 addi a4,a4,1 +8000e538: 00377793 andi a5,a4,3 +8000e53c: fed70fa3 sb a3,-1(a4) +8000e540: 00158593 addi a1,a1,1 +8000e544: f80780e3 beqz a5,8000e4c4 +8000e548: 0005c683 lbu a3,0(a1) +8000e54c: 00170713 addi a4,a4,1 +8000e550: 00377793 andi a5,a4,3 +8000e554: fed70fa3 sb a3,-1(a4) +8000e558: 00158593 addi a1,a1,1 +8000e55c: fc079ae3 bnez a5,8000e530 +8000e560: f65ff06f j 8000e4c4 +8000e564: 0045a683 lw a3,4(a1) +8000e568: 0005a283 lw t0,0(a1) +8000e56c: 0085af83 lw t6,8(a1) +8000e570: 00c5af03 lw t5,12(a1) +8000e574: 0105ae83 lw t4,16(a1) +8000e578: 0145ae03 lw t3,20(a1) +8000e57c: 0185a303 lw t1,24(a1) +8000e580: 01c5a803 lw a6,28(a1) +8000e584: 00d72223 sw a3,4(a4) +8000e588: 0205a683 lw a3,32(a1) +8000e58c: 00572023 sw t0,0(a4) +8000e590: 01f72423 sw t6,8(a4) +8000e594: 01e72623 sw t5,12(a4) +8000e598: 01d72823 sw t4,16(a4) +8000e59c: 01c72a23 sw t3,20(a4) +8000e5a0: 00672c23 sw t1,24(a4) +8000e5a4: 01072e23 sw a6,28(a4) +8000e5a8: 02d72023 sw a3,32(a4) +8000e5ac: 02470713 addi a4,a4,36 +8000e5b0: 02458593 addi a1,a1,36 +8000e5b4: faf768e3 bltu a4,a5,8000e564 +8000e5b8: f19ff06f j 8000e4d0 -8000ede8 <_reclaim_reent>: -8000ede8: 3601a783 lw a5,864(gp) # 80016b68 <_impure_ptr> -8000edec: 10a78063 beq a5,a0,8000eeec <_reclaim_reent+0x104> -8000edf0: 04c52583 lw a1,76(a0) -8000edf4: fe010113 addi sp,sp,-32 -8000edf8: 00912a23 sw s1,20(sp) -8000edfc: 00112e23 sw ra,28(sp) -8000ee00: 00812c23 sw s0,24(sp) -8000ee04: 01212823 sw s2,16(sp) -8000ee08: 01312623 sw s3,12(sp) -8000ee0c: 00050493 mv s1,a0 -8000ee10: 04058063 beqz a1,8000ee50 <_reclaim_reent+0x68> -8000ee14: 00000913 li s2,0 -8000ee18: 08000993 li s3,128 -8000ee1c: 012587b3 add a5,a1,s2 -8000ee20: 0007a403 lw s0,0(a5) -8000ee24: 00040e63 beqz s0,8000ee40 <_reclaim_reent+0x58> -8000ee28: 00040593 mv a1,s0 -8000ee2c: 00042403 lw s0,0(s0) -8000ee30: 00048513 mv a0,s1 -8000ee34: c51f50ef jal ra,80004a84 <_free_r> -8000ee38: fe0418e3 bnez s0,8000ee28 <_reclaim_reent+0x40> -8000ee3c: 04c4a583 lw a1,76(s1) -8000ee40: 00490913 addi s2,s2,4 -8000ee44: fd391ce3 bne s2,s3,8000ee1c <_reclaim_reent+0x34> -8000ee48: 00048513 mv a0,s1 -8000ee4c: c39f50ef jal ra,80004a84 <_free_r> -8000ee50: 0404a583 lw a1,64(s1) -8000ee54: 00058663 beqz a1,8000ee60 <_reclaim_reent+0x78> -8000ee58: 00048513 mv a0,s1 -8000ee5c: c29f50ef jal ra,80004a84 <_free_r> -8000ee60: 1484a403 lw s0,328(s1) -8000ee64: 02040063 beqz s0,8000ee84 <_reclaim_reent+0x9c> -8000ee68: 14c48913 addi s2,s1,332 -8000ee6c: 01240c63 beq s0,s2,8000ee84 <_reclaim_reent+0x9c> -8000ee70: 00040593 mv a1,s0 -8000ee74: 00042403 lw s0,0(s0) -8000ee78: 00048513 mv a0,s1 -8000ee7c: c09f50ef jal ra,80004a84 <_free_r> -8000ee80: fe8918e3 bne s2,s0,8000ee70 <_reclaim_reent+0x88> -8000ee84: 0544a583 lw a1,84(s1) -8000ee88: 00058663 beqz a1,8000ee94 <_reclaim_reent+0xac> -8000ee8c: 00048513 mv a0,s1 -8000ee90: bf5f50ef jal ra,80004a84 <_free_r> -8000ee94: 0384a783 lw a5,56(s1) -8000ee98: 02078c63 beqz a5,8000eed0 <_reclaim_reent+0xe8> -8000ee9c: 03c4a783 lw a5,60(s1) -8000eea0: 00048513 mv a0,s1 -8000eea4: 000780e7 jalr a5 -8000eea8: 2e04a583 lw a1,736(s1) -8000eeac: 02058263 beqz a1,8000eed0 <_reclaim_reent+0xe8> -8000eeb0: 01812403 lw s0,24(sp) -8000eeb4: 01c12083 lw ra,28(sp) -8000eeb8: 01012903 lw s2,16(sp) -8000eebc: 00c12983 lw s3,12(sp) -8000eec0: 00048513 mv a0,s1 -8000eec4: 01412483 lw s1,20(sp) -8000eec8: 02010113 addi sp,sp,32 -8000eecc: eddff06f j 8000eda8 -8000eed0: 01c12083 lw ra,28(sp) -8000eed4: 01812403 lw s0,24(sp) -8000eed8: 01412483 lw s1,20(sp) -8000eedc: 01012903 lw s2,16(sp) -8000eee0: 00c12983 lw s3,12(sp) -8000eee4: 02010113 addi sp,sp,32 -8000eee8: 00008067 ret -8000eeec: 00008067 ret +8000e5bc : +8000e5bc: 02a5f663 bgeu a1,a0,8000e5e8 +8000e5c0: 00c587b3 add a5,a1,a2 +8000e5c4: 02f57263 bgeu a0,a5,8000e5e8 +8000e5c8: 00c50733 add a4,a0,a2 +8000e5cc: 0e060a63 beqz a2,8000e6c0 +8000e5d0: fff7c683 lbu a3,-1(a5) +8000e5d4: fff78793 addi a5,a5,-1 +8000e5d8: fff70713 addi a4,a4,-1 +8000e5dc: 00d70023 sb a3,0(a4) +8000e5e0: fef598e3 bne a1,a5,8000e5d0 +8000e5e4: 00008067 ret +8000e5e8: 00f00793 li a5,15 +8000e5ec: 02c7e863 bltu a5,a2,8000e61c +8000e5f0: 00050793 mv a5,a0 +8000e5f4: fff60693 addi a3,a2,-1 +8000e5f8: 0c060c63 beqz a2,8000e6d0 +8000e5fc: 00168693 addi a3,a3,1 +8000e600: 00d786b3 add a3,a5,a3 +8000e604: 0005c703 lbu a4,0(a1) +8000e608: 00178793 addi a5,a5,1 +8000e60c: 00158593 addi a1,a1,1 +8000e610: fee78fa3 sb a4,-1(a5) +8000e614: fed798e3 bne a5,a3,8000e604 +8000e618: 00008067 ret +8000e61c: 00a5e7b3 or a5,a1,a0 +8000e620: 0037f793 andi a5,a5,3 +8000e624: 0a079063 bnez a5,8000e6c4 +8000e628: ff060893 addi a7,a2,-16 +8000e62c: ff08f893 andi a7,a7,-16 +8000e630: 01088893 addi a7,a7,16 +8000e634: 01150833 add a6,a0,a7 +8000e638: 00058713 mv a4,a1 +8000e63c: 00050793 mv a5,a0 +8000e640: 00072683 lw a3,0(a4) +8000e644: 01070713 addi a4,a4,16 +8000e648: 01078793 addi a5,a5,16 +8000e64c: fed7a823 sw a3,-16(a5) +8000e650: ff472683 lw a3,-12(a4) +8000e654: fed7aa23 sw a3,-12(a5) +8000e658: ff872683 lw a3,-8(a4) +8000e65c: fed7ac23 sw a3,-8(a5) +8000e660: ffc72683 lw a3,-4(a4) +8000e664: fed7ae23 sw a3,-4(a5) +8000e668: fcf81ce3 bne a6,a5,8000e640 +8000e66c: 00c67713 andi a4,a2,12 +8000e670: 011585b3 add a1,a1,a7 +8000e674: 00f67813 andi a6,a2,15 +8000e678: 04070e63 beqz a4,8000e6d4 +8000e67c: 00058713 mv a4,a1 +8000e680: 00078893 mv a7,a5 +8000e684: 00300e13 li t3,3 +8000e688: 00072303 lw t1,0(a4) +8000e68c: 00470713 addi a4,a4,4 +8000e690: 40e806b3 sub a3,a6,a4 +8000e694: 0068a023 sw t1,0(a7) +8000e698: 00d586b3 add a3,a1,a3 +8000e69c: 00488893 addi a7,a7,4 +8000e6a0: fede64e3 bltu t3,a3,8000e688 +8000e6a4: ffc80713 addi a4,a6,-4 +8000e6a8: ffc77713 andi a4,a4,-4 +8000e6ac: 00470713 addi a4,a4,4 +8000e6b0: 00367613 andi a2,a2,3 +8000e6b4: 00e787b3 add a5,a5,a4 +8000e6b8: 00e585b3 add a1,a1,a4 +8000e6bc: f39ff06f j 8000e5f4 +8000e6c0: 00008067 ret +8000e6c4: fff60693 addi a3,a2,-1 +8000e6c8: 00050793 mv a5,a0 +8000e6cc: f31ff06f j 8000e5fc +8000e6d0: 00008067 ret +8000e6d4: 00080613 mv a2,a6 +8000e6d8: f1dff06f j 8000e5f4 -8000eef0 <__ssprint_r>: -8000eef0: 00862783 lw a5,8(a2) -8000eef4: fd010113 addi sp,sp,-48 -8000eef8: 01512a23 sw s5,20(sp) -8000eefc: 02112623 sw ra,44(sp) -8000ef00: 02812423 sw s0,40(sp) -8000ef04: 02912223 sw s1,36(sp) -8000ef08: 03212023 sw s2,32(sp) -8000ef0c: 01312e23 sw s3,28(sp) -8000ef10: 01412c23 sw s4,24(sp) -8000ef14: 01612823 sw s6,16(sp) -8000ef18: 01712623 sw s7,12(sp) -8000ef1c: 01812423 sw s8,8(sp) -8000ef20: 00060a93 mv s5,a2 -8000ef24: 14078863 beqz a5,8000f074 <__ssprint_r+0x184> -8000ef28: 00050b13 mv s6,a0 -8000ef2c: 00062983 lw s3,0(a2) -8000ef30: 0005a503 lw a0,0(a1) -8000ef34: 0085a483 lw s1,8(a1) -8000ef38: 00058413 mv s0,a1 -8000ef3c: 0d40006f j 8000f010 <__ssprint_r+0x120> -8000ef40: 00c45783 lhu a5,12(s0) -8000ef44: 4807f713 andi a4,a5,1152 -8000ef48: 08070a63 beqz a4,8000efdc <__ssprint_r+0xec> -8000ef4c: 01442683 lw a3,20(s0) -8000ef50: 01042583 lw a1,16(s0) -8000ef54: 00190713 addi a4,s2,1 -8000ef58: 00169493 slli s1,a3,0x1 -8000ef5c: 00d486b3 add a3,s1,a3 -8000ef60: 01f6d493 srli s1,a3,0x1f -8000ef64: 40b50a33 sub s4,a0,a1 -8000ef68: 00d484b3 add s1,s1,a3 -8000ef6c: 4014d493 srai s1,s1,0x1 -8000ef70: 01470733 add a4,a4,s4 -8000ef74: 00048613 mv a2,s1 -8000ef78: 00e4f663 bgeu s1,a4,8000ef84 <__ssprint_r+0x94> -8000ef7c: 00070493 mv s1,a4 -8000ef80: 00070613 mv a2,a4 -8000ef84: 4007f793 andi a5,a5,1024 -8000ef88: 0a078663 beqz a5,8000f034 <__ssprint_r+0x144> -8000ef8c: 00060593 mv a1,a2 -8000ef90: 000b0513 mv a0,s6 -8000ef94: d5df80ef jal ra,80007cf0 <_malloc_r> -8000ef98: 00050c13 mv s8,a0 -8000ef9c: 0a050a63 beqz a0,8000f050 <__ssprint_r+0x160> -8000efa0: 01042583 lw a1,16(s0) -8000efa4: 000a0613 mv a2,s4 -8000efa8: de8ff0ef jal ra,8000e590 -8000efac: 00c45783 lhu a5,12(s0) -8000efb0: b7f7f793 andi a5,a5,-1153 -8000efb4: 0807e793 ori a5,a5,128 -8000efb8: 00f41623 sh a5,12(s0) -8000efbc: 014c0533 add a0,s8,s4 -8000efc0: 41448a33 sub s4,s1,s4 -8000efc4: 00942a23 sw s1,20(s0) -8000efc8: 01442423 sw s4,8(s0) -8000efcc: 01842823 sw s8,16(s0) -8000efd0: 00a42023 sw a0,0(s0) -8000efd4: 00090493 mv s1,s2 -8000efd8: 00090a13 mv s4,s2 -8000efdc: 000a0613 mv a2,s4 -8000efe0: 000b8593 mv a1,s7 -8000efe4: ec8ff0ef jal ra,8000e6ac -8000efe8: 00842703 lw a4,8(s0) -8000efec: 00042503 lw a0,0(s0) -8000eff0: 008aa783 lw a5,8(s5) -8000eff4: 409704b3 sub s1,a4,s1 -8000eff8: 01450533 add a0,a0,s4 -8000effc: 00942423 sw s1,8(s0) -8000f000: 00a42023 sw a0,0(s0) -8000f004: 41278933 sub s2,a5,s2 -8000f008: 012aa423 sw s2,8(s5) -8000f00c: 06090463 beqz s2,8000f074 <__ssprint_r+0x184> -8000f010: 0049a903 lw s2,4(s3) -8000f014: 0009ab83 lw s7,0(s3) -8000f018: 00048a13 mv s4,s1 -8000f01c: 00898993 addi s3,s3,8 -8000f020: fe0908e3 beqz s2,8000f010 <__ssprint_r+0x120> -8000f024: f0997ee3 bgeu s2,s1,8000ef40 <__ssprint_r+0x50> -8000f028: 00090493 mv s1,s2 -8000f02c: 00090a13 mv s4,s2 -8000f030: fadff06f j 8000efdc <__ssprint_r+0xec> -8000f034: 000b0513 mv a0,s6 -8000f038: ffcff0ef jal ra,8000e834 <_realloc_r> -8000f03c: 00050c13 mv s8,a0 -8000f040: f6051ee3 bnez a0,8000efbc <__ssprint_r+0xcc> -8000f044: 01042583 lw a1,16(s0) -8000f048: 000b0513 mv a0,s6 -8000f04c: a39f50ef jal ra,80004a84 <_free_r> -8000f050: 00c00793 li a5,12 -8000f054: 00fb2023 sw a5,0(s6) -8000f058: 00c45783 lhu a5,12(s0) -8000f05c: fff00513 li a0,-1 -8000f060: 0407e793 ori a5,a5,64 -8000f064: 00f41623 sh a5,12(s0) -8000f068: 000aa423 sw zero,8(s5) -8000f06c: 000aa223 sw zero,4(s5) -8000f070: 00c0006f j 8000f07c <__ssprint_r+0x18c> -8000f074: 000aa223 sw zero,4(s5) -8000f078: 00000513 li a0,0 -8000f07c: 02c12083 lw ra,44(sp) -8000f080: 02812403 lw s0,40(sp) -8000f084: 02412483 lw s1,36(sp) -8000f088: 02012903 lw s2,32(sp) -8000f08c: 01c12983 lw s3,28(sp) -8000f090: 01812a03 lw s4,24(sp) -8000f094: 01412a83 lw s5,20(sp) -8000f098: 01012b03 lw s6,16(sp) -8000f09c: 00c12b83 lw s7,12(sp) -8000f0a0: 00812c03 lw s8,8(sp) -8000f0a4: 03010113 addi sp,sp,48 -8000f0a8: 00008067 ret +8000e6dc <_read_r>: +8000e6dc: ff010113 addi sp,sp,-16 +8000e6e0: 00058713 mv a4,a1 +8000e6e4: 00812423 sw s0,8(sp) +8000e6e8: 00912223 sw s1,4(sp) +8000e6ec: 00060593 mv a1,a2 +8000e6f0: 00050413 mv s0,a0 +8000e6f4: 00068613 mv a2,a3 +8000e6f8: 00070513 mv a0,a4 +8000e6fc: 00112623 sw ra,12(sp) +8000e700: 4201a823 sw zero,1072(gp) # 80016c38 +8000e704: cc5f10ef jal ra,800003c8 <_read> +8000e708: fff00793 li a5,-1 +8000e70c: 00f50c63 beq a0,a5,8000e724 <_read_r+0x48> +8000e710: 00c12083 lw ra,12(sp) +8000e714: 00812403 lw s0,8(sp) +8000e718: 00412483 lw s1,4(sp) +8000e71c: 01010113 addi sp,sp,16 +8000e720: 00008067 ret +8000e724: 4301a783 lw a5,1072(gp) # 80016c38 +8000e728: fe0784e3 beqz a5,8000e710 <_read_r+0x34> +8000e72c: 00c12083 lw ra,12(sp) +8000e730: 00f42023 sw a5,0(s0) +8000e734: 00812403 lw s0,8(sp) +8000e738: 00412483 lw s1,4(sp) +8000e73c: 01010113 addi sp,sp,16 +8000e740: 00008067 ret -8000f0ac <_svfiprintf_r>: -8000f0ac: 00c5d783 lhu a5,12(a1) -8000f0b0: ed010113 addi sp,sp,-304 -8000f0b4: 11412c23 sw s4,280(sp) -8000f0b8: 11612823 sw s6,272(sp) -8000f0bc: 11a12023 sw s10,256(sp) -8000f0c0: 12112623 sw ra,300(sp) -8000f0c4: 12812423 sw s0,296(sp) -8000f0c8: 12912223 sw s1,292(sp) -8000f0cc: 13212023 sw s2,288(sp) -8000f0d0: 11312e23 sw s3,284(sp) -8000f0d4: 11512a23 sw s5,276(sp) -8000f0d8: 11712623 sw s7,268(sp) -8000f0dc: 11812423 sw s8,264(sp) -8000f0e0: 11912223 sw s9,260(sp) -8000f0e4: 0fb12e23 sw s11,252(sp) -8000f0e8: 0807f793 andi a5,a5,128 -8000f0ec: 00d12623 sw a3,12(sp) -8000f0f0: 00058a13 mv s4,a1 -8000f0f4: 00050b13 mv s6,a0 -8000f0f8: 00060d13 mv s10,a2 -8000f0fc: 00078663 beqz a5,8000f108 <_svfiprintf_r+0x5c> -8000f100: 0105a783 lw a5,16(a1) -8000f104: 5e0784e3 beqz a5,8000feec <_svfiprintf_r+0xe40> -8000f108: 800157b7 lui a5,0x80015 -8000f10c: 04c10a93 addi s5,sp,76 -8000f110: 5bc78793 addi a5,a5,1468 # 800155bc <__BSS_END__+0xffffe98c> -8000f114: 80015bb7 lui s7,0x80015 -8000f118: 800154b7 lui s1,0x80015 -8000f11c: 000d0993 mv s3,s10 -8000f120: 05512023 sw s5,64(sp) -8000f124: 04012423 sw zero,72(sp) -8000f128: 04012223 sw zero,68(sp) -8000f12c: 00012a23 sw zero,20(sp) -8000f130: 00012c23 sw zero,24(sp) -8000f134: 02012023 sw zero,32(sp) -8000f138: 00012e23 sw zero,28(sp) -8000f13c: 00012423 sw zero,8(sp) -8000f140: 00f12823 sw a5,16(sp) -8000f144: 728b8b93 addi s7,s7,1832 # 80015728 <__BSS_END__+0xffffeaf8> -8000f148: 73848493 addi s1,s1,1848 # 80015738 <__BSS_END__+0xffffeb08> -8000f14c: 000a8d13 mv s10,s5 -8000f150: 0009c783 lbu a5,0(s3) -8000f154: 20078c63 beqz a5,8000f36c <_svfiprintf_r+0x2c0> -8000f158: 00098413 mv s0,s3 -8000f15c: 02500693 li a3,37 -8000f160: 2ad78863 beq a5,a3,8000f410 <_svfiprintf_r+0x364> -8000f164: 00144783 lbu a5,1(s0) -8000f168: 00140413 addi s0,s0,1 -8000f16c: fe079ae3 bnez a5,8000f160 <_svfiprintf_r+0xb4> -8000f170: 41340c33 sub s8,s0,s3 -8000f174: 1f340c63 beq s0,s3,8000f36c <_svfiprintf_r+0x2c0> -8000f178: 04812683 lw a3,72(sp) -8000f17c: 04412783 lw a5,68(sp) -8000f180: 013d2023 sw s3,0(s10) -8000f184: 018686b3 add a3,a3,s8 -8000f188: 00178793 addi a5,a5,1 -8000f18c: 018d2223 sw s8,4(s10) -8000f190: 04d12423 sw a3,72(sp) -8000f194: 04f12223 sw a5,68(sp) -8000f198: 00700693 li a3,7 -8000f19c: 008d0d13 addi s10,s10,8 -8000f1a0: 28f6c063 blt a3,a5,8000f420 <_svfiprintf_r+0x374> -8000f1a4: 00812703 lw a4,8(sp) -8000f1a8: 00044783 lbu a5,0(s0) -8000f1ac: 01870733 add a4,a4,s8 -8000f1b0: 00e12423 sw a4,8(sp) -8000f1b4: 1a078c63 beqz a5,8000f36c <_svfiprintf_r+0x2c0> -8000f1b8: fff00893 li a7,-1 -8000f1bc: 00144683 lbu a3,1(s0) -8000f1c0: 00140993 addi s3,s0,1 -8000f1c4: 02010da3 sb zero,59(sp) -8000f1c8: 00012223 sw zero,4(sp) -8000f1cc: 00000913 li s2,0 -8000f1d0: 05a00c13 li s8,90 -8000f1d4: 00900c93 li s9,9 -8000f1d8: 02a00593 li a1,42 -8000f1dc: 00088413 mv s0,a7 -8000f1e0: 00198993 addi s3,s3,1 -8000f1e4: fe068793 addi a5,a3,-32 -8000f1e8: 04fc6863 bltu s8,a5,8000f238 <_svfiprintf_r+0x18c> -8000f1ec: 01012703 lw a4,16(sp) -8000f1f0: 00279793 slli a5,a5,0x2 -8000f1f4: 00e787b3 add a5,a5,a4 -8000f1f8: 0007a783 lw a5,0(a5) -8000f1fc: 00078067 jr a5 -8000f200: 00012223 sw zero,4(sp) -8000f204: fd068793 addi a5,a3,-48 -8000f208: 00412603 lw a2,4(sp) -8000f20c: 0009c683 lbu a3,0(s3) -8000f210: 00198993 addi s3,s3,1 -8000f214: 00261713 slli a4,a2,0x2 -8000f218: 00c70733 add a4,a4,a2 -8000f21c: 00171713 slli a4,a4,0x1 -8000f220: 00e787b3 add a5,a5,a4 -8000f224: 00f12223 sw a5,4(sp) -8000f228: fd068793 addi a5,a3,-48 -8000f22c: fcfcfee3 bgeu s9,a5,8000f208 <_svfiprintf_r+0x15c> -8000f230: fe068793 addi a5,a3,-32 -8000f234: fafc7ce3 bgeu s8,a5,8000f1ec <_svfiprintf_r+0x140> -8000f238: 12068a63 beqz a3,8000f36c <_svfiprintf_r+0x2c0> -8000f23c: 08d10623 sb a3,140(sp) -8000f240: 02010da3 sb zero,59(sp) -8000f244: 00100c13 li s8,1 -8000f248: 00100c93 li s9,1 -8000f24c: 08c10413 addi s0,sp,140 -8000f250: 00000893 li a7,0 -8000f254: 00297f13 andi t5,s2,2 -8000f258: 000f0463 beqz t5,8000f260 <_svfiprintf_r+0x1b4> -8000f25c: 002c0c13 addi s8,s8,2 -8000f260: 08497e93 andi t4,s2,132 -8000f264: 04812783 lw a5,72(sp) -8000f268: 04412603 lw a2,68(sp) -8000f26c: 000e9863 bnez t4,8000f27c <_svfiprintf_r+0x1d0> -8000f270: 00412703 lw a4,4(sp) -8000f274: 41870db3 sub s11,a4,s8 -8000f278: 7bb04a63 bgtz s11,8000fa2c <_svfiprintf_r+0x980> -8000f27c: 03b14503 lbu a0,59(sp) -8000f280: 00160593 addi a1,a2,1 -8000f284: 008d0693 addi a3,s10,8 -8000f288: 04050063 beqz a0,8000f2c8 <_svfiprintf_r+0x21c> -8000f28c: 03b10513 addi a0,sp,59 -8000f290: 00178793 addi a5,a5,1 -8000f294: 00ad2023 sw a0,0(s10) -8000f298: 00100513 li a0,1 -8000f29c: 00ad2223 sw a0,4(s10) -8000f2a0: 04f12423 sw a5,72(sp) -8000f2a4: 04b12223 sw a1,68(sp) -8000f2a8: 00700513 li a0,7 -8000f2ac: 0ab540e3 blt a0,a1,8000fb4c <_svfiprintf_r+0xaa0> -8000f2b0: 00260f93 addi t6,a2,2 -8000f2b4: 010d0513 addi a0,s10,16 -8000f2b8: 00058613 mv a2,a1 -8000f2bc: 00068d13 mv s10,a3 -8000f2c0: 000f8593 mv a1,t6 -8000f2c4: 00050693 mv a3,a0 -8000f2c8: 020f0c63 beqz t5,8000f300 <_svfiprintf_r+0x254> -8000f2cc: 03c10613 addi a2,sp,60 -8000f2d0: 00278793 addi a5,a5,2 -8000f2d4: 00cd2023 sw a2,0(s10) -8000f2d8: 00200613 li a2,2 -8000f2dc: 00cd2223 sw a2,4(s10) -8000f2e0: 04f12423 sw a5,72(sp) -8000f2e4: 04b12223 sw a1,68(sp) -8000f2e8: 00700713 li a4,7 -8000f2ec: 0ab742e3 blt a4,a1,8000fb90 <_svfiprintf_r+0xae4> -8000f2f0: 00058613 mv a2,a1 -8000f2f4: 00068d13 mv s10,a3 -8000f2f8: 00158593 addi a1,a1,1 -8000f2fc: 00868693 addi a3,a3,8 -8000f300: 08000513 li a0,128 -8000f304: 54ae8c63 beq t4,a0,8000f85c <_svfiprintf_r+0x7b0> -8000f308: 41988db3 sub s11,a7,s9 -8000f30c: 63b04463 bgtz s11,8000f934 <_svfiprintf_r+0x888> -8000f310: 00fc87b3 add a5,s9,a5 -8000f314: 008d2023 sw s0,0(s10) -8000f318: 019d2223 sw s9,4(s10) -8000f31c: 04f12423 sw a5,72(sp) -8000f320: 04b12223 sw a1,68(sp) -8000f324: 00700713 li a4,7 -8000f328: 6cb74263 blt a4,a1,8000f9ec <_svfiprintf_r+0x940> -8000f32c: 00497313 andi t1,s2,4 -8000f330: 00030863 beqz t1,8000f340 <_svfiprintf_r+0x294> -8000f334: 00412703 lw a4,4(sp) -8000f338: 41870cb3 sub s9,a4,s8 -8000f33c: 099048e3 bgtz s9,8000fbcc <_svfiprintf_r+0xb20> -8000f340: 00412403 lw s0,4(sp) -8000f344: 01845463 bge s0,s8,8000f34c <_svfiprintf_r+0x2a0> -8000f348: 000c0413 mv s0,s8 -8000f34c: 00812703 lw a4,8(sp) -8000f350: 00870733 add a4,a4,s0 -8000f354: 00e12423 sw a4,8(sp) -8000f358: 6a079a63 bnez a5,8000fa0c <_svfiprintf_r+0x960> -8000f35c: 0009c783 lbu a5,0(s3) -8000f360: 04012223 sw zero,68(sp) -8000f364: 000a8d13 mv s10,s5 -8000f368: de0798e3 bnez a5,8000f158 <_svfiprintf_r+0xac> -8000f36c: 04812783 lw a5,72(sp) -8000f370: 56079ee3 bnez a5,800100ec <_svfiprintf_r+0x1040> -8000f374: 00ca5783 lhu a5,12(s4) -8000f378: 0407f793 andi a5,a5,64 -8000f37c: 5a0794e3 bnez a5,80010124 <_svfiprintf_r+0x1078> -8000f380: 12c12083 lw ra,300(sp) -8000f384: 12812403 lw s0,296(sp) -8000f388: 00812503 lw a0,8(sp) -8000f38c: 12412483 lw s1,292(sp) -8000f390: 12012903 lw s2,288(sp) -8000f394: 11c12983 lw s3,284(sp) -8000f398: 11812a03 lw s4,280(sp) -8000f39c: 11412a83 lw s5,276(sp) -8000f3a0: 11012b03 lw s6,272(sp) -8000f3a4: 10c12b83 lw s7,268(sp) -8000f3a8: 10812c03 lw s8,264(sp) -8000f3ac: 10412c83 lw s9,260(sp) -8000f3b0: 10012d03 lw s10,256(sp) -8000f3b4: 0fc12d83 lw s11,252(sp) -8000f3b8: 13010113 addi sp,sp,304 -8000f3bc: 00008067 ret -8000f3c0: 000b0513 mv a0,s6 -8000f3c4: e94f80ef jal ra,80007a58 <_localeconv_r> -8000f3c8: 00452783 lw a5,4(a0) -8000f3cc: 00078513 mv a0,a5 -8000f3d0: 00f12e23 sw a5,28(sp) -8000f3d4: fe4fa0ef jal ra,80009bb8 -8000f3d8: 00050793 mv a5,a0 -8000f3dc: 000b0513 mv a0,s6 -8000f3e0: 00078d93 mv s11,a5 -8000f3e4: 02f12023 sw a5,32(sp) -8000f3e8: e70f80ef jal ra,80007a58 <_localeconv_r> -8000f3ec: 00852783 lw a5,8(a0) -8000f3f0: 02a00593 li a1,42 -8000f3f4: 00f12c23 sw a5,24(sp) -8000f3f8: 1e0d98e3 bnez s11,8000fde8 <_svfiprintf_r+0xd3c> -8000f3fc: 0009c683 lbu a3,0(s3) -8000f400: de1ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f404: 0009c683 lbu a3,0(s3) -8000f408: 02096913 ori s2,s2,32 -8000f40c: dd5ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f410: 41340c33 sub s8,s0,s3 -8000f414: d73412e3 bne s0,s3,8000f178 <_svfiprintf_r+0xcc> -8000f418: 00044783 lbu a5,0(s0) -8000f41c: d99ff06f j 8000f1b4 <_svfiprintf_r+0x108> -8000f420: 04010613 addi a2,sp,64 -8000f424: 000a0593 mv a1,s4 -8000f428: 000b0513 mv a0,s6 -8000f42c: ac5ff0ef jal ra,8000eef0 <__ssprint_r> -8000f430: f40512e3 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000f434: 000a8d13 mv s10,s5 -8000f438: d6dff06f j 8000f1a4 <_svfiprintf_r+0xf8> -8000f43c: 00c12783 lw a5,12(sp) -8000f440: 00040893 mv a7,s0 -8000f444: 02010da3 sb zero,59(sp) -8000f448: 0007a403 lw s0,0(a5) -8000f44c: 00478d93 addi s11,a5,4 -8000f450: 380404e3 beqz s0,8000ffd8 <_svfiprintf_r+0xf2c> -8000f454: fff00793 li a5,-1 -8000f458: 26f88ee3 beq a7,a5,8000fed4 <_svfiprintf_r+0xe28> -8000f45c: 00088613 mv a2,a7 -8000f460: 00000593 li a1,0 -8000f464: 00040513 mv a0,s0 -8000f468: 01112623 sw a7,12(sp) -8000f46c: 88cf90ef jal ra,800084f8 -8000f470: 00c12883 lw a7,12(sp) -8000f474: 480506e3 beqz a0,80010100 <_svfiprintf_r+0x1054> -8000f478: 40850cb3 sub s9,a0,s0 -8000f47c: 01b12623 sw s11,12(sp) -8000f480: 00000893 li a7,0 -8000f484: 0940006f j 8000f518 <_svfiprintf_r+0x46c> -8000f488: 00c12703 lw a4,12(sp) -8000f48c: 02010da3 sb zero,59(sp) -8000f490: 00100c13 li s8,1 -8000f494: 00072783 lw a5,0(a4) -8000f498: 00470713 addi a4,a4,4 -8000f49c: 00e12623 sw a4,12(sp) -8000f4a0: 08f10623 sb a5,140(sp) -8000f4a4: 00100c93 li s9,1 -8000f4a8: 08c10413 addi s0,sp,140 -8000f4ac: da5ff06f j 8000f250 <_svfiprintf_r+0x1a4> -8000f4b0: 02097793 andi a5,s2,32 -8000f4b4: 00040893 mv a7,s0 -8000f4b8: 0e078e63 beqz a5,8000f5b4 <_svfiprintf_r+0x508> -8000f4bc: 00c12783 lw a5,12(sp) -8000f4c0: 00778793 addi a5,a5,7 -8000f4c4: ff87f793 andi a5,a5,-8 -8000f4c8: 0047a683 lw a3,4(a5) -8000f4cc: 0007ac83 lw s9,0(a5) -8000f4d0: 00878793 addi a5,a5,8 -8000f4d4: 00f12623 sw a5,12(sp) -8000f4d8: 00068c13 mv s8,a3 -8000f4dc: 1006c463 bltz a3,8000f5e4 <_svfiprintf_r+0x538> -8000f4e0: fff00693 li a3,-1 -8000f4e4: 00090d93 mv s11,s2 -8000f4e8: 00d88863 beq a7,a3,8000f4f8 <_svfiprintf_r+0x44c> -8000f4ec: 018ce6b3 or a3,s9,s8 -8000f4f0: f7f97d93 andi s11,s2,-129 -8000f4f4: 76068e63 beqz a3,8000fc70 <_svfiprintf_r+0xbc4> -8000f4f8: 000c1ce3 bnez s8,8000fd10 <_svfiprintf_r+0xc64> -8000f4fc: 00900693 li a3,9 -8000f500: 0196e8e3 bltu a3,s9,8000fd10 <_svfiprintf_r+0xc64> -8000f504: 030c8793 addi a5,s9,48 -8000f508: 0ef107a3 sb a5,239(sp) -8000f50c: 000d8913 mv s2,s11 -8000f510: 00100c93 li s9,1 -8000f514: 0ef10413 addi s0,sp,239 -8000f518: 00088c13 mv s8,a7 -8000f51c: 0198d463 bge a7,s9,8000f524 <_svfiprintf_r+0x478> -8000f520: 000c8c13 mv s8,s9 -8000f524: 03b14783 lbu a5,59(sp) -8000f528: 00f037b3 snez a5,a5 -8000f52c: 00fc0c33 add s8,s8,a5 -8000f530: d25ff06f j 8000f254 <_svfiprintf_r+0x1a8> -8000f534: 00040893 mv a7,s0 -8000f538: 01096913 ori s2,s2,16 +8000e744 <_realloc_r>: +8000e744: fd010113 addi sp,sp,-48 +8000e748: 03212023 sw s2,32(sp) +8000e74c: 02112623 sw ra,44(sp) +8000e750: 02812423 sw s0,40(sp) +8000e754: 02912223 sw s1,36(sp) +8000e758: 01312e23 sw s3,28(sp) +8000e75c: 01412c23 sw s4,24(sp) +8000e760: 01512a23 sw s5,20(sp) +8000e764: 01612823 sw s6,16(sp) +8000e768: 01712623 sw s7,12(sp) +8000e76c: 01812423 sw s8,8(sp) +8000e770: 00060913 mv s2,a2 +8000e774: 22058263 beqz a1,8000e998 <_realloc_r+0x254> +8000e778: 00058413 mv s0,a1 +8000e77c: 00050993 mv s3,a0 +8000e780: d71f90ef jal ra,800084f0 <__malloc_lock> +8000e784: 00b90493 addi s1,s2,11 +8000e788: 01600793 li a5,22 +8000e78c: 0e97fc63 bgeu a5,s1,8000e884 <_realloc_r+0x140> +8000e790: ff84f493 andi s1,s1,-8 +8000e794: 00048713 mv a4,s1 +8000e798: 0e04cc63 bltz s1,8000e890 <_realloc_r+0x14c> +8000e79c: 0f24ea63 bltu s1,s2,8000e890 <_realloc_r+0x14c> +8000e7a0: ffc42783 lw a5,-4(s0) +8000e7a4: ff840a93 addi s5,s0,-8 +8000e7a8: ffc7fa13 andi s4,a5,-4 +8000e7ac: 014a8b33 add s6,s5,s4 +8000e7b0: 18ea5a63 bge s4,a4,8000e944 <_realloc_r+0x200> +8000e7b4: dc018b93 addi s7,gp,-576 # 800165c8 <__malloc_av_> +8000e7b8: 008ba603 lw a2,8(s7) +8000e7bc: 004b2683 lw a3,4(s6) # 80000004 <__BSS_END__+0xfffe93c8> +8000e7c0: 23660e63 beq a2,s6,8000e9fc <_realloc_r+0x2b8> +8000e7c4: ffe6f613 andi a2,a3,-2 +8000e7c8: 00cb0633 add a2,s6,a2 +8000e7cc: 00462603 lw a2,4(a2) +8000e7d0: 00167613 andi a2,a2,1 +8000e7d4: 1a061463 bnez a2,8000e97c <_realloc_r+0x238> +8000e7d8: ffc6f693 andi a3,a3,-4 +8000e7dc: 00da0633 add a2,s4,a3 +8000e7e0: 32e65e63 bge a2,a4,8000eb1c <_realloc_r+0x3d8> +8000e7e4: 0017f793 andi a5,a5,1 +8000e7e8: 02079463 bnez a5,8000e810 <_realloc_r+0xcc> +8000e7ec: ff842c03 lw s8,-8(s0) +8000e7f0: 418a8c33 sub s8,s5,s8 +8000e7f4: 004c2783 lw a5,4(s8) +8000e7f8: ffc7f793 andi a5,a5,-4 +8000e7fc: 00d786b3 add a3,a5,a3 +8000e800: 01468bb3 add s7,a3,s4 +8000e804: 34ebda63 bge s7,a4,8000eb58 <_realloc_r+0x414> +8000e808: 00fa0bb3 add s7,s4,a5 +8000e80c: 0cebd263 bge s7,a4,8000e8d0 <_realloc_r+0x18c> +8000e810: 00090593 mv a1,s2 +8000e814: 00098513 mv a0,s3 +8000e818: b90f90ef jal ra,80007ba8 <_malloc_r> +8000e81c: 00050913 mv s2,a0 +8000e820: 04050c63 beqz a0,8000e878 <_realloc_r+0x134> +8000e824: ffc42783 lw a5,-4(s0) +8000e828: ff850713 addi a4,a0,-8 +8000e82c: ffe7f793 andi a5,a5,-2 +8000e830: 00fa87b3 add a5,s5,a5 +8000e834: 30e78263 beq a5,a4,8000eb38 <_realloc_r+0x3f4> +8000e838: ffca0613 addi a2,s4,-4 +8000e83c: 02400793 li a5,36 +8000e840: 30c7e663 bltu a5,a2,8000eb4c <_realloc_r+0x408> +8000e844: 01300713 li a4,19 +8000e848: 00042683 lw a3,0(s0) +8000e84c: 26c76c63 bltu a4,a2,8000eac4 <_realloc_r+0x380> +8000e850: 00050793 mv a5,a0 +8000e854: 00040713 mv a4,s0 +8000e858: 00d7a023 sw a3,0(a5) +8000e85c: 00472683 lw a3,4(a4) +8000e860: 00d7a223 sw a3,4(a5) +8000e864: 00872703 lw a4,8(a4) +8000e868: 00e7a423 sw a4,8(a5) +8000e86c: 00040593 mv a1,s0 +8000e870: 00098513 mv a0,s3 +8000e874: 960f60ef jal ra,800049d4 <_free_r> +8000e878: 00098513 mv a0,s3 +8000e87c: c79f90ef jal ra,800084f4 <__malloc_unlock> +8000e880: 01c0006f j 8000e89c <_realloc_r+0x158> +8000e884: 01000493 li s1,16 +8000e888: 01000713 li a4,16 +8000e88c: f124fae3 bgeu s1,s2,8000e7a0 <_realloc_r+0x5c> +8000e890: 00c00793 li a5,12 +8000e894: 00f9a023 sw a5,0(s3) +8000e898: 00000913 li s2,0 +8000e89c: 02c12083 lw ra,44(sp) +8000e8a0: 02812403 lw s0,40(sp) +8000e8a4: 02412483 lw s1,36(sp) +8000e8a8: 01c12983 lw s3,28(sp) +8000e8ac: 01812a03 lw s4,24(sp) +8000e8b0: 01412a83 lw s5,20(sp) +8000e8b4: 01012b03 lw s6,16(sp) +8000e8b8: 00c12b83 lw s7,12(sp) +8000e8bc: 00812c03 lw s8,8(sp) +8000e8c0: 00090513 mv a0,s2 +8000e8c4: 02012903 lw s2,32(sp) +8000e8c8: 03010113 addi sp,sp,48 +8000e8cc: 00008067 ret +8000e8d0: 00cc2783 lw a5,12(s8) +8000e8d4: 008c2703 lw a4,8(s8) +8000e8d8: ffca0613 addi a2,s4,-4 +8000e8dc: 02400693 li a3,36 +8000e8e0: 00f72623 sw a5,12(a4) +8000e8e4: 00e7a423 sw a4,8(a5) +8000e8e8: 008c0913 addi s2,s8,8 +8000e8ec: 017c0b33 add s6,s8,s7 +8000e8f0: 2ec6e463 bltu a3,a2,8000ebd8 <_realloc_r+0x494> +8000e8f4: 01300593 li a1,19 +8000e8f8: 00042703 lw a4,0(s0) +8000e8fc: 00090793 mv a5,s2 +8000e900: 02c5f263 bgeu a1,a2,8000e924 <_realloc_r+0x1e0> +8000e904: 00ec2423 sw a4,8(s8) +8000e908: 00442703 lw a4,4(s0) +8000e90c: 01b00793 li a5,27 +8000e910: 00ec2623 sw a4,12(s8) +8000e914: 30c7e263 bltu a5,a2,8000ec18 <_realloc_r+0x4d4> +8000e918: 00842703 lw a4,8(s0) +8000e91c: 010c0793 addi a5,s8,16 +8000e920: 00840413 addi s0,s0,8 +8000e924: 00e7a023 sw a4,0(a5) +8000e928: 00442703 lw a4,4(s0) +8000e92c: 000b8a13 mv s4,s7 +8000e930: 000c0a93 mv s5,s8 +8000e934: 00e7a223 sw a4,4(a5) +8000e938: 00842703 lw a4,8(s0) +8000e93c: 00090413 mv s0,s2 +8000e940: 00e7a423 sw a4,8(a5) +8000e944: 004aa783 lw a5,4(s5) +8000e948: 409a0733 sub a4,s4,s1 +8000e94c: 00f00693 li a3,15 +8000e950: 0017f793 andi a5,a5,1 +8000e954: 06e6ec63 bltu a3,a4,8000e9cc <_realloc_r+0x288> +8000e958: 00fa67b3 or a5,s4,a5 +8000e95c: 00faa223 sw a5,4(s5) +8000e960: 004b2783 lw a5,4(s6) +8000e964: 0017e793 ori a5,a5,1 +8000e968: 00fb2223 sw a5,4(s6) +8000e96c: 00098513 mv a0,s3 +8000e970: b85f90ef jal ra,800084f4 <__malloc_unlock> +8000e974: 00040913 mv s2,s0 +8000e978: f25ff06f j 8000e89c <_realloc_r+0x158> +8000e97c: 0017f793 andi a5,a5,1 +8000e980: e80798e3 bnez a5,8000e810 <_realloc_r+0xcc> +8000e984: ff842c03 lw s8,-8(s0) +8000e988: 418a8c33 sub s8,s5,s8 +8000e98c: 004c2783 lw a5,4(s8) +8000e990: ffc7f793 andi a5,a5,-4 +8000e994: e75ff06f j 8000e808 <_realloc_r+0xc4> +8000e998: 02812403 lw s0,40(sp) +8000e99c: 02c12083 lw ra,44(sp) +8000e9a0: 02412483 lw s1,36(sp) +8000e9a4: 02012903 lw s2,32(sp) +8000e9a8: 01c12983 lw s3,28(sp) +8000e9ac: 01812a03 lw s4,24(sp) +8000e9b0: 01412a83 lw s5,20(sp) +8000e9b4: 01012b03 lw s6,16(sp) +8000e9b8: 00c12b83 lw s7,12(sp) +8000e9bc: 00812c03 lw s8,8(sp) +8000e9c0: 00060593 mv a1,a2 +8000e9c4: 03010113 addi sp,sp,48 +8000e9c8: 9e0f906f j 80007ba8 <_malloc_r> +8000e9cc: 0097e7b3 or a5,a5,s1 +8000e9d0: 00faa223 sw a5,4(s5) +8000e9d4: 009a85b3 add a1,s5,s1 +8000e9d8: 00176713 ori a4,a4,1 +8000e9dc: 00e5a223 sw a4,4(a1) +8000e9e0: 004b2783 lw a5,4(s6) +8000e9e4: 00858593 addi a1,a1,8 +8000e9e8: 00098513 mv a0,s3 +8000e9ec: 0017e793 ori a5,a5,1 +8000e9f0: 00fb2223 sw a5,4(s6) +8000e9f4: fe1f50ef jal ra,800049d4 <_free_r> +8000e9f8: f75ff06f j 8000e96c <_realloc_r+0x228> +8000e9fc: ffc6f693 andi a3,a3,-4 +8000ea00: 00da0633 add a2,s4,a3 +8000ea04: 01048593 addi a1,s1,16 +8000ea08: 0eb65063 bge a2,a1,8000eae8 <_realloc_r+0x3a4> +8000ea0c: 0017f793 andi a5,a5,1 +8000ea10: e00790e3 bnez a5,8000e810 <_realloc_r+0xcc> +8000ea14: ff842c03 lw s8,-8(s0) +8000ea18: 418a8c33 sub s8,s5,s8 +8000ea1c: 004c2783 lw a5,4(s8) +8000ea20: ffc7f793 andi a5,a5,-4 +8000ea24: 00d786b3 add a3,a5,a3 +8000ea28: 01468b33 add s6,a3,s4 +8000ea2c: dcbb4ee3 blt s6,a1,8000e808 <_realloc_r+0xc4> +8000ea30: 00cc2783 lw a5,12(s8) +8000ea34: 008c2703 lw a4,8(s8) +8000ea38: ffca0613 addi a2,s4,-4 +8000ea3c: 02400693 li a3,36 +8000ea40: 00f72623 sw a5,12(a4) +8000ea44: 00e7a423 sw a4,8(a5) +8000ea48: 008c0913 addi s2,s8,8 +8000ea4c: 20c6ee63 bltu a3,a2,8000ec68 <_realloc_r+0x524> +8000ea50: 01300593 li a1,19 +8000ea54: 00042703 lw a4,0(s0) +8000ea58: 00090793 mv a5,s2 +8000ea5c: 02c5f263 bgeu a1,a2,8000ea80 <_realloc_r+0x33c> +8000ea60: 00ec2423 sw a4,8(s8) +8000ea64: 00442703 lw a4,4(s0) +8000ea68: 01b00793 li a5,27 +8000ea6c: 00ec2623 sw a4,12(s8) +8000ea70: 20c7e463 bltu a5,a2,8000ec78 <_realloc_r+0x534> +8000ea74: 00842703 lw a4,8(s0) +8000ea78: 010c0793 addi a5,s8,16 +8000ea7c: 00840413 addi s0,s0,8 +8000ea80: 00e7a023 sw a4,0(a5) +8000ea84: 00442703 lw a4,4(s0) +8000ea88: 00e7a223 sw a4,4(a5) +8000ea8c: 00842703 lw a4,8(s0) +8000ea90: 00e7a423 sw a4,8(a5) +8000ea94: 009c0733 add a4,s8,s1 +8000ea98: 409b07b3 sub a5,s6,s1 +8000ea9c: 00eba423 sw a4,8(s7) +8000eaa0: 0017e793 ori a5,a5,1 +8000eaa4: 00f72223 sw a5,4(a4) +8000eaa8: 004c2783 lw a5,4(s8) +8000eaac: 00098513 mv a0,s3 +8000eab0: 0017f793 andi a5,a5,1 +8000eab4: 0097e4b3 or s1,a5,s1 +8000eab8: 009c2223 sw s1,4(s8) +8000eabc: a39f90ef jal ra,800084f4 <__malloc_unlock> +8000eac0: dddff06f j 8000e89c <_realloc_r+0x158> +8000eac4: 00d52023 sw a3,0(a0) +8000eac8: 00442683 lw a3,4(s0) +8000eacc: 01b00713 li a4,27 +8000ead0: 00d52223 sw a3,4(a0) +8000ead4: 12c76063 bltu a4,a2,8000ebf4 <_realloc_r+0x4b0> +8000ead8: 00842683 lw a3,8(s0) +8000eadc: 00840713 addi a4,s0,8 +8000eae0: 00850793 addi a5,a0,8 +8000eae4: d75ff06f j 8000e858 <_realloc_r+0x114> +8000eae8: 009a8ab3 add s5,s5,s1 +8000eaec: 409607b3 sub a5,a2,s1 +8000eaf0: 015ba423 sw s5,8(s7) +8000eaf4: 0017e793 ori a5,a5,1 +8000eaf8: 00faa223 sw a5,4(s5) +8000eafc: ffc42783 lw a5,-4(s0) +8000eb00: 00098513 mv a0,s3 +8000eb04: 00040913 mv s2,s0 +8000eb08: 0017f793 andi a5,a5,1 +8000eb0c: 0097e4b3 or s1,a5,s1 +8000eb10: fe942e23 sw s1,-4(s0) +8000eb14: 9e1f90ef jal ra,800084f4 <__malloc_unlock> +8000eb18: d85ff06f j 8000e89c <_realloc_r+0x158> +8000eb1c: 00cb2783 lw a5,12(s6) +8000eb20: 008b2703 lw a4,8(s6) +8000eb24: 00060a13 mv s4,a2 +8000eb28: 00ca8b33 add s6,s5,a2 +8000eb2c: 00f72623 sw a5,12(a4) +8000eb30: 00e7a423 sw a4,8(a5) +8000eb34: e11ff06f j 8000e944 <_realloc_r+0x200> +8000eb38: ffc52783 lw a5,-4(a0) +8000eb3c: ffc7f793 andi a5,a5,-4 +8000eb40: 00fa0a33 add s4,s4,a5 +8000eb44: 014a8b33 add s6,s5,s4 +8000eb48: dfdff06f j 8000e944 <_realloc_r+0x200> +8000eb4c: 00040593 mv a1,s0 +8000eb50: a6dff0ef jal ra,8000e5bc +8000eb54: d19ff06f j 8000e86c <_realloc_r+0x128> +8000eb58: 00cb2783 lw a5,12(s6) +8000eb5c: 008b2703 lw a4,8(s6) +8000eb60: ffca0613 addi a2,s4,-4 +8000eb64: 02400693 li a3,36 +8000eb68: 00f72623 sw a5,12(a4) +8000eb6c: 00e7a423 sw a4,8(a5) +8000eb70: 008c2703 lw a4,8(s8) +8000eb74: 00cc2783 lw a5,12(s8) +8000eb78: 008c0913 addi s2,s8,8 +8000eb7c: 017c0b33 add s6,s8,s7 +8000eb80: 00f72623 sw a5,12(a4) +8000eb84: 00e7a423 sw a4,8(a5) +8000eb88: 04c6e863 bltu a3,a2,8000ebd8 <_realloc_r+0x494> +8000eb8c: 01300693 li a3,19 +8000eb90: 00042703 lw a4,0(s0) +8000eb94: 00090793 mv a5,s2 +8000eb98: d8c6f6e3 bgeu a3,a2,8000e924 <_realloc_r+0x1e0> +8000eb9c: 00ec2423 sw a4,8(s8) +8000eba0: 00442703 lw a4,4(s0) +8000eba4: 01b00793 li a5,27 +8000eba8: 00ec2623 sw a4,12(s8) +8000ebac: 00842703 lw a4,8(s0) +8000ebb0: d6c7f6e3 bgeu a5,a2,8000e91c <_realloc_r+0x1d8> +8000ebb4: 00ec2823 sw a4,16(s8) +8000ebb8: 00c42703 lw a4,12(s0) +8000ebbc: 02400793 li a5,36 +8000ebc0: 00ec2a23 sw a4,20(s8) +8000ebc4: 01042703 lw a4,16(s0) +8000ebc8: 06f60463 beq a2,a5,8000ec30 <_realloc_r+0x4ec> +8000ebcc: 018c0793 addi a5,s8,24 +8000ebd0: 01040413 addi s0,s0,16 +8000ebd4: d51ff06f j 8000e924 <_realloc_r+0x1e0> +8000ebd8: 00040593 mv a1,s0 +8000ebdc: 00090513 mv a0,s2 +8000ebe0: 9ddff0ef jal ra,8000e5bc +8000ebe4: 00090413 mv s0,s2 +8000ebe8: 000b8a13 mv s4,s7 +8000ebec: 000c0a93 mv s5,s8 +8000ebf0: d55ff06f j 8000e944 <_realloc_r+0x200> +8000ebf4: 00842703 lw a4,8(s0) +8000ebf8: 00e52423 sw a4,8(a0) +8000ebfc: 00c42703 lw a4,12(s0) +8000ec00: 00e52623 sw a4,12(a0) +8000ec04: 01042683 lw a3,16(s0) +8000ec08: 04f60263 beq a2,a5,8000ec4c <_realloc_r+0x508> +8000ec0c: 01040713 addi a4,s0,16 +8000ec10: 01050793 addi a5,a0,16 +8000ec14: c45ff06f j 8000e858 <_realloc_r+0x114> +8000ec18: 00842783 lw a5,8(s0) +8000ec1c: 00fc2823 sw a5,16(s8) +8000ec20: 00c42783 lw a5,12(s0) +8000ec24: 00fc2a23 sw a5,20(s8) +8000ec28: 01042703 lw a4,16(s0) +8000ec2c: fad610e3 bne a2,a3,8000ebcc <_realloc_r+0x488> +8000ec30: 00ec2c23 sw a4,24(s8) +8000ec34: 01442703 lw a4,20(s0) +8000ec38: 020c0793 addi a5,s8,32 +8000ec3c: 01840413 addi s0,s0,24 +8000ec40: 00ec2e23 sw a4,28(s8) +8000ec44: 00042703 lw a4,0(s0) +8000ec48: cddff06f j 8000e924 <_realloc_r+0x1e0> +8000ec4c: 00d52823 sw a3,16(a0) +8000ec50: 01442683 lw a3,20(s0) +8000ec54: 01840713 addi a4,s0,24 +8000ec58: 01850793 addi a5,a0,24 +8000ec5c: 00d52a23 sw a3,20(a0) +8000ec60: 01842683 lw a3,24(s0) +8000ec64: bf5ff06f j 8000e858 <_realloc_r+0x114> +8000ec68: 00040593 mv a1,s0 +8000ec6c: 00090513 mv a0,s2 +8000ec70: 94dff0ef jal ra,8000e5bc +8000ec74: e21ff06f j 8000ea94 <_realloc_r+0x350> +8000ec78: 00842783 lw a5,8(s0) +8000ec7c: 00fc2823 sw a5,16(s8) +8000ec80: 00c42783 lw a5,12(s0) +8000ec84: 00fc2a23 sw a5,20(s8) +8000ec88: 01042703 lw a4,16(s0) +8000ec8c: 00d60863 beq a2,a3,8000ec9c <_realloc_r+0x558> +8000ec90: 018c0793 addi a5,s8,24 +8000ec94: 01040413 addi s0,s0,16 +8000ec98: de9ff06f j 8000ea80 <_realloc_r+0x33c> +8000ec9c: 00ec2c23 sw a4,24(s8) +8000eca0: 01442703 lw a4,20(s0) +8000eca4: 020c0793 addi a5,s8,32 +8000eca8: 01840413 addi s0,s0,24 +8000ecac: 00ec2e23 sw a4,28(s8) +8000ecb0: 00042703 lw a4,0(s0) +8000ecb4: dcdff06f j 8000ea80 <_realloc_r+0x33c> + +8000ecb8 : +8000ecb8: ff010113 addi sp,sp,-16 +8000ecbc: 00812423 sw s0,8(sp) +8000ecc0: 00058413 mv s0,a1 +8000ecc4: 0005a583 lw a1,0(a1) +8000ecc8: 00912223 sw s1,4(sp) +8000eccc: 00112623 sw ra,12(sp) +8000ecd0: 00050493 mv s1,a0 +8000ecd4: 00058463 beqz a1,8000ecdc +8000ecd8: fe1ff0ef jal ra,8000ecb8 +8000ecdc: 00040593 mv a1,s0 +8000ece0: 00812403 lw s0,8(sp) +8000ece4: 00c12083 lw ra,12(sp) +8000ece8: 00048513 mv a0,s1 +8000ecec: 00412483 lw s1,4(sp) +8000ecf0: 01010113 addi sp,sp,16 +8000ecf4: ce1f506f j 800049d4 <_free_r> + +8000ecf8 <_reclaim_reent>: +8000ecf8: 3601a783 lw a5,864(gp) # 80016b68 <_impure_ptr> +8000ecfc: 10a78063 beq a5,a0,8000edfc <_reclaim_reent+0x104> +8000ed00: 04c52583 lw a1,76(a0) +8000ed04: fe010113 addi sp,sp,-32 +8000ed08: 00912a23 sw s1,20(sp) +8000ed0c: 00112e23 sw ra,28(sp) +8000ed10: 00812c23 sw s0,24(sp) +8000ed14: 01212823 sw s2,16(sp) +8000ed18: 01312623 sw s3,12(sp) +8000ed1c: 00050493 mv s1,a0 +8000ed20: 04058063 beqz a1,8000ed60 <_reclaim_reent+0x68> +8000ed24: 00000913 li s2,0 +8000ed28: 08000993 li s3,128 +8000ed2c: 012587b3 add a5,a1,s2 +8000ed30: 0007a403 lw s0,0(a5) +8000ed34: 00040e63 beqz s0,8000ed50 <_reclaim_reent+0x58> +8000ed38: 00040593 mv a1,s0 +8000ed3c: 00042403 lw s0,0(s0) +8000ed40: 00048513 mv a0,s1 +8000ed44: c91f50ef jal ra,800049d4 <_free_r> +8000ed48: fe0418e3 bnez s0,8000ed38 <_reclaim_reent+0x40> +8000ed4c: 04c4a583 lw a1,76(s1) +8000ed50: 00490913 addi s2,s2,4 +8000ed54: fd391ce3 bne s2,s3,8000ed2c <_reclaim_reent+0x34> +8000ed58: 00048513 mv a0,s1 +8000ed5c: c79f50ef jal ra,800049d4 <_free_r> +8000ed60: 0404a583 lw a1,64(s1) +8000ed64: 00058663 beqz a1,8000ed70 <_reclaim_reent+0x78> +8000ed68: 00048513 mv a0,s1 +8000ed6c: c69f50ef jal ra,800049d4 <_free_r> +8000ed70: 1484a403 lw s0,328(s1) +8000ed74: 02040063 beqz s0,8000ed94 <_reclaim_reent+0x9c> +8000ed78: 14c48913 addi s2,s1,332 +8000ed7c: 01240c63 beq s0,s2,8000ed94 <_reclaim_reent+0x9c> +8000ed80: 00040593 mv a1,s0 +8000ed84: 00042403 lw s0,0(s0) +8000ed88: 00048513 mv a0,s1 +8000ed8c: c49f50ef jal ra,800049d4 <_free_r> +8000ed90: fe8918e3 bne s2,s0,8000ed80 <_reclaim_reent+0x88> +8000ed94: 0544a583 lw a1,84(s1) +8000ed98: 00058663 beqz a1,8000eda4 <_reclaim_reent+0xac> +8000ed9c: 00048513 mv a0,s1 +8000eda0: c35f50ef jal ra,800049d4 <_free_r> +8000eda4: 0384a783 lw a5,56(s1) +8000eda8: 02078c63 beqz a5,8000ede0 <_reclaim_reent+0xe8> +8000edac: 03c4a783 lw a5,60(s1) +8000edb0: 00048513 mv a0,s1 +8000edb4: 000780e7 jalr a5 +8000edb8: 2e04a583 lw a1,736(s1) +8000edbc: 02058263 beqz a1,8000ede0 <_reclaim_reent+0xe8> +8000edc0: 01812403 lw s0,24(sp) +8000edc4: 01c12083 lw ra,28(sp) +8000edc8: 01012903 lw s2,16(sp) +8000edcc: 00c12983 lw s3,12(sp) +8000edd0: 00048513 mv a0,s1 +8000edd4: 01412483 lw s1,20(sp) +8000edd8: 02010113 addi sp,sp,32 +8000eddc: eddff06f j 8000ecb8 +8000ede0: 01c12083 lw ra,28(sp) +8000ede4: 01812403 lw s0,24(sp) +8000ede8: 01412483 lw s1,20(sp) +8000edec: 01012903 lw s2,16(sp) +8000edf0: 00c12983 lw s3,12(sp) +8000edf4: 02010113 addi sp,sp,32 +8000edf8: 00008067 ret +8000edfc: 00008067 ret + +8000ee00 : +8000ee00: 00b56733 or a4,a0,a1 +8000ee04: fff00393 li t2,-1 +8000ee08: 00377713 andi a4,a4,3 +8000ee0c: 10071063 bnez a4,8000ef0c +8000ee10: 7f7f87b7 lui a5,0x7f7f8 +8000ee14: f7f78793 addi a5,a5,-129 # 7f7f7f7f <_start-0x808081> +8000ee18: 00052603 lw a2,0(a0) +8000ee1c: 0005a683 lw a3,0(a1) +8000ee20: 00f672b3 and t0,a2,a5 +8000ee24: 00f66333 or t1,a2,a5 +8000ee28: 00f282b3 add t0,t0,a5 +8000ee2c: 0062e2b3 or t0,t0,t1 +8000ee30: 10729263 bne t0,t2,8000ef34 +8000ee34: 08d61663 bne a2,a3,8000eec0 +8000ee38: 00452603 lw a2,4(a0) +8000ee3c: 0045a683 lw a3,4(a1) +8000ee40: 00f672b3 and t0,a2,a5 +8000ee44: 00f66333 or t1,a2,a5 +8000ee48: 00f282b3 add t0,t0,a5 +8000ee4c: 0062e2b3 or t0,t0,t1 +8000ee50: 0c729e63 bne t0,t2,8000ef2c +8000ee54: 06d61663 bne a2,a3,8000eec0 +8000ee58: 00852603 lw a2,8(a0) +8000ee5c: 0085a683 lw a3,8(a1) +8000ee60: 00f672b3 and t0,a2,a5 +8000ee64: 00f66333 or t1,a2,a5 +8000ee68: 00f282b3 add t0,t0,a5 +8000ee6c: 0062e2b3 or t0,t0,t1 +8000ee70: 0c729863 bne t0,t2,8000ef40 +8000ee74: 04d61663 bne a2,a3,8000eec0 +8000ee78: 00c52603 lw a2,12(a0) +8000ee7c: 00c5a683 lw a3,12(a1) +8000ee80: 00f672b3 and t0,a2,a5 +8000ee84: 00f66333 or t1,a2,a5 +8000ee88: 00f282b3 add t0,t0,a5 +8000ee8c: 0062e2b3 or t0,t0,t1 +8000ee90: 0c729263 bne t0,t2,8000ef54 +8000ee94: 02d61663 bne a2,a3,8000eec0 +8000ee98: 01052603 lw a2,16(a0) +8000ee9c: 0105a683 lw a3,16(a1) +8000eea0: 00f672b3 and t0,a2,a5 +8000eea4: 00f66333 or t1,a2,a5 +8000eea8: 00f282b3 add t0,t0,a5 +8000eeac: 0062e2b3 or t0,t0,t1 +8000eeb0: 0a729c63 bne t0,t2,8000ef68 +8000eeb4: 01450513 addi a0,a0,20 +8000eeb8: 01458593 addi a1,a1,20 +8000eebc: f4d60ee3 beq a2,a3,8000ee18 +8000eec0: 01061713 slli a4,a2,0x10 +8000eec4: 01069793 slli a5,a3,0x10 +8000eec8: 00f71e63 bne a4,a5,8000eee4 +8000eecc: 01065713 srli a4,a2,0x10 +8000eed0: 0106d793 srli a5,a3,0x10 +8000eed4: 40f70533 sub a0,a4,a5 +8000eed8: 0ff57593 andi a1,a0,255 +8000eedc: 02059063 bnez a1,8000eefc +8000eee0: 00008067 ret +8000eee4: 01075713 srli a4,a4,0x10 +8000eee8: 0107d793 srli a5,a5,0x10 +8000eeec: 40f70533 sub a0,a4,a5 +8000eef0: 0ff57593 andi a1,a0,255 +8000eef4: 00059463 bnez a1,8000eefc +8000eef8: 00008067 ret +8000eefc: 0ff77713 andi a4,a4,255 +8000ef00: 0ff7f793 andi a5,a5,255 +8000ef04: 40f70533 sub a0,a4,a5 +8000ef08: 00008067 ret +8000ef0c: 00054603 lbu a2,0(a0) +8000ef10: 0005c683 lbu a3,0(a1) +8000ef14: 00150513 addi a0,a0,1 +8000ef18: 00158593 addi a1,a1,1 +8000ef1c: 00d61463 bne a2,a3,8000ef24 +8000ef20: fe0616e3 bnez a2,8000ef0c +8000ef24: 40d60533 sub a0,a2,a3 +8000ef28: 00008067 ret +8000ef2c: 00450513 addi a0,a0,4 +8000ef30: 00458593 addi a1,a1,4 +8000ef34: fcd61ce3 bne a2,a3,8000ef0c +8000ef38: 00000513 li a0,0 +8000ef3c: 00008067 ret +8000ef40: 00850513 addi a0,a0,8 +8000ef44: 00858593 addi a1,a1,8 +8000ef48: fcd612e3 bne a2,a3,8000ef0c +8000ef4c: 00000513 li a0,0 +8000ef50: 00008067 ret +8000ef54: 00c50513 addi a0,a0,12 +8000ef58: 00c58593 addi a1,a1,12 +8000ef5c: fad618e3 bne a2,a3,8000ef0c +8000ef60: 00000513 li a0,0 +8000ef64: 00008067 ret +8000ef68: 01050513 addi a0,a0,16 +8000ef6c: 01058593 addi a1,a1,16 +8000ef70: f8d61ee3 bne a2,a3,8000ef0c +8000ef74: 00000513 li a0,0 +8000ef78: 00008067 ret + +8000ef7c <__ssprint_r>: +8000ef7c: 00862783 lw a5,8(a2) +8000ef80: fd010113 addi sp,sp,-48 +8000ef84: 01512a23 sw s5,20(sp) +8000ef88: 02112623 sw ra,44(sp) +8000ef8c: 02812423 sw s0,40(sp) +8000ef90: 02912223 sw s1,36(sp) +8000ef94: 03212023 sw s2,32(sp) +8000ef98: 01312e23 sw s3,28(sp) +8000ef9c: 01412c23 sw s4,24(sp) +8000efa0: 01612823 sw s6,16(sp) +8000efa4: 01712623 sw s7,12(sp) +8000efa8: 01812423 sw s8,8(sp) +8000efac: 00060a93 mv s5,a2 +8000efb0: 14078863 beqz a5,8000f100 <__ssprint_r+0x184> +8000efb4: 00050b13 mv s6,a0 +8000efb8: 00062983 lw s3,0(a2) +8000efbc: 0005a503 lw a0,0(a1) +8000efc0: 0085a483 lw s1,8(a1) +8000efc4: 00058413 mv s0,a1 +8000efc8: 0d40006f j 8000f09c <__ssprint_r+0x120> +8000efcc: 00c45783 lhu a5,12(s0) +8000efd0: 4807f713 andi a4,a5,1152 +8000efd4: 08070a63 beqz a4,8000f068 <__ssprint_r+0xec> +8000efd8: 01442683 lw a3,20(s0) +8000efdc: 01042583 lw a1,16(s0) +8000efe0: 00190713 addi a4,s2,1 +8000efe4: 00169493 slli s1,a3,0x1 +8000efe8: 00d486b3 add a3,s1,a3 +8000efec: 01f6d493 srli s1,a3,0x1f +8000eff0: 40b50a33 sub s4,a0,a1 +8000eff4: 00d484b3 add s1,s1,a3 +8000eff8: 4014d493 srai s1,s1,0x1 +8000effc: 01470733 add a4,a4,s4 +8000f000: 00048613 mv a2,s1 +8000f004: 00e4f663 bgeu s1,a4,8000f010 <__ssprint_r+0x94> +8000f008: 00070493 mv s1,a4 +8000f00c: 00070613 mv a2,a4 +8000f010: 4007f793 andi a5,a5,1024 +8000f014: 0a078663 beqz a5,8000f0c0 <__ssprint_r+0x144> +8000f018: 00060593 mv a1,a2 +8000f01c: 000b0513 mv a0,s6 +8000f020: b89f80ef jal ra,80007ba8 <_malloc_r> +8000f024: 00050c13 mv s8,a0 +8000f028: 0a050a63 beqz a0,8000f0dc <__ssprint_r+0x160> +8000f02c: 01042583 lw a1,16(s0) +8000f030: 000a0613 mv a2,s4 +8000f034: c6cff0ef jal ra,8000e4a0 +8000f038: 00c45783 lhu a5,12(s0) +8000f03c: b7f7f793 andi a5,a5,-1153 +8000f040: 0807e793 ori a5,a5,128 +8000f044: 00f41623 sh a5,12(s0) +8000f048: 014c0533 add a0,s8,s4 +8000f04c: 41448a33 sub s4,s1,s4 +8000f050: 00942a23 sw s1,20(s0) +8000f054: 01442423 sw s4,8(s0) +8000f058: 01842823 sw s8,16(s0) +8000f05c: 00a42023 sw a0,0(s0) +8000f060: 00090493 mv s1,s2 +8000f064: 00090a13 mv s4,s2 +8000f068: 000a0613 mv a2,s4 +8000f06c: 000b8593 mv a1,s7 +8000f070: d4cff0ef jal ra,8000e5bc +8000f074: 00842703 lw a4,8(s0) +8000f078: 00042503 lw a0,0(s0) +8000f07c: 008aa783 lw a5,8(s5) +8000f080: 409704b3 sub s1,a4,s1 +8000f084: 01450533 add a0,a0,s4 +8000f088: 00942423 sw s1,8(s0) +8000f08c: 00a42023 sw a0,0(s0) +8000f090: 41278933 sub s2,a5,s2 +8000f094: 012aa423 sw s2,8(s5) +8000f098: 06090463 beqz s2,8000f100 <__ssprint_r+0x184> +8000f09c: 0049a903 lw s2,4(s3) +8000f0a0: 0009ab83 lw s7,0(s3) +8000f0a4: 00048a13 mv s4,s1 +8000f0a8: 00898993 addi s3,s3,8 +8000f0ac: fe0908e3 beqz s2,8000f09c <__ssprint_r+0x120> +8000f0b0: f0997ee3 bgeu s2,s1,8000efcc <__ssprint_r+0x50> +8000f0b4: 00090493 mv s1,s2 +8000f0b8: 00090a13 mv s4,s2 +8000f0bc: fadff06f j 8000f068 <__ssprint_r+0xec> +8000f0c0: 000b0513 mv a0,s6 +8000f0c4: e80ff0ef jal ra,8000e744 <_realloc_r> +8000f0c8: 00050c13 mv s8,a0 +8000f0cc: f6051ee3 bnez a0,8000f048 <__ssprint_r+0xcc> +8000f0d0: 01042583 lw a1,16(s0) +8000f0d4: 000b0513 mv a0,s6 +8000f0d8: 8fdf50ef jal ra,800049d4 <_free_r> +8000f0dc: 00c00793 li a5,12 +8000f0e0: 00fb2023 sw a5,0(s6) +8000f0e4: 00c45783 lhu a5,12(s0) +8000f0e8: fff00513 li a0,-1 +8000f0ec: 0407e793 ori a5,a5,64 +8000f0f0: 00f41623 sh a5,12(s0) +8000f0f4: 000aa423 sw zero,8(s5) +8000f0f8: 000aa223 sw zero,4(s5) +8000f0fc: 00c0006f j 8000f108 <__ssprint_r+0x18c> +8000f100: 000aa223 sw zero,4(s5) +8000f104: 00000513 li a0,0 +8000f108: 02c12083 lw ra,44(sp) +8000f10c: 02812403 lw s0,40(sp) +8000f110: 02412483 lw s1,36(sp) +8000f114: 02012903 lw s2,32(sp) +8000f118: 01c12983 lw s3,28(sp) +8000f11c: 01812a03 lw s4,24(sp) +8000f120: 01412a83 lw s5,20(sp) +8000f124: 01012b03 lw s6,16(sp) +8000f128: 00c12b83 lw s7,12(sp) +8000f12c: 00812c03 lw s8,8(sp) +8000f130: 03010113 addi sp,sp,48 +8000f134: 00008067 ret + +8000f138 <_svfiprintf_r>: +8000f138: 00c5d783 lhu a5,12(a1) +8000f13c: ed010113 addi sp,sp,-304 +8000f140: 11412c23 sw s4,280(sp) +8000f144: 11612823 sw s6,272(sp) +8000f148: 11a12023 sw s10,256(sp) +8000f14c: 12112623 sw ra,300(sp) +8000f150: 12812423 sw s0,296(sp) +8000f154: 12912223 sw s1,292(sp) +8000f158: 13212023 sw s2,288(sp) +8000f15c: 11312e23 sw s3,284(sp) +8000f160: 11512a23 sw s5,276(sp) +8000f164: 11712623 sw s7,268(sp) +8000f168: 11812423 sw s8,264(sp) +8000f16c: 11912223 sw s9,260(sp) +8000f170: 0fb12e23 sw s11,252(sp) +8000f174: 0807f793 andi a5,a5,128 +8000f178: 00d12623 sw a3,12(sp) +8000f17c: 00058a13 mv s4,a1 +8000f180: 00050b13 mv s6,a0 +8000f184: 00060d13 mv s10,a2 +8000f188: 00078663 beqz a5,8000f194 <_svfiprintf_r+0x5c> +8000f18c: 0105a783 lw a5,16(a1) +8000f190: 5e0784e3 beqz a5,8000ff78 <_svfiprintf_r+0xe40> +8000f194: 800157b7 lui a5,0x80015 +8000f198: 04c10a93 addi s5,sp,76 +8000f19c: 50878793 addi a5,a5,1288 # 80015508 <__BSS_END__+0xffffe8cc> +8000f1a0: 80015bb7 lui s7,0x80015 +8000f1a4: 800154b7 lui s1,0x80015 +8000f1a8: 000d0993 mv s3,s10 +8000f1ac: 05512023 sw s5,64(sp) +8000f1b0: 04012423 sw zero,72(sp) +8000f1b4: 04012223 sw zero,68(sp) +8000f1b8: 00012a23 sw zero,20(sp) +8000f1bc: 00012c23 sw zero,24(sp) +8000f1c0: 02012023 sw zero,32(sp) +8000f1c4: 00012e23 sw zero,28(sp) +8000f1c8: 00012423 sw zero,8(sp) +8000f1cc: 00f12823 sw a5,16(sp) +8000f1d0: 674b8b93 addi s7,s7,1652 # 80015674 <__BSS_END__+0xffffea38> +8000f1d4: 68448493 addi s1,s1,1668 # 80015684 <__BSS_END__+0xffffea48> +8000f1d8: 000a8d13 mv s10,s5 +8000f1dc: 0009c783 lbu a5,0(s3) +8000f1e0: 20078c63 beqz a5,8000f3f8 <_svfiprintf_r+0x2c0> +8000f1e4: 00098413 mv s0,s3 +8000f1e8: 02500693 li a3,37 +8000f1ec: 2ad78863 beq a5,a3,8000f49c <_svfiprintf_r+0x364> +8000f1f0: 00144783 lbu a5,1(s0) +8000f1f4: 00140413 addi s0,s0,1 +8000f1f8: fe079ae3 bnez a5,8000f1ec <_svfiprintf_r+0xb4> +8000f1fc: 41340c33 sub s8,s0,s3 +8000f200: 1f340c63 beq s0,s3,8000f3f8 <_svfiprintf_r+0x2c0> +8000f204: 04812683 lw a3,72(sp) +8000f208: 04412783 lw a5,68(sp) +8000f20c: 013d2023 sw s3,0(s10) +8000f210: 018686b3 add a3,a3,s8 +8000f214: 00178793 addi a5,a5,1 +8000f218: 018d2223 sw s8,4(s10) +8000f21c: 04d12423 sw a3,72(sp) +8000f220: 04f12223 sw a5,68(sp) +8000f224: 00700693 li a3,7 +8000f228: 008d0d13 addi s10,s10,8 +8000f22c: 28f6c063 blt a3,a5,8000f4ac <_svfiprintf_r+0x374> +8000f230: 00812703 lw a4,8(sp) +8000f234: 00044783 lbu a5,0(s0) +8000f238: 01870733 add a4,a4,s8 +8000f23c: 00e12423 sw a4,8(sp) +8000f240: 1a078c63 beqz a5,8000f3f8 <_svfiprintf_r+0x2c0> +8000f244: fff00893 li a7,-1 +8000f248: 00144683 lbu a3,1(s0) +8000f24c: 00140993 addi s3,s0,1 +8000f250: 02010da3 sb zero,59(sp) +8000f254: 00012223 sw zero,4(sp) +8000f258: 00000913 li s2,0 +8000f25c: 05a00c13 li s8,90 +8000f260: 00900c93 li s9,9 +8000f264: 02a00593 li a1,42 +8000f268: 00088413 mv s0,a7 +8000f26c: 00198993 addi s3,s3,1 +8000f270: fe068793 addi a5,a3,-32 +8000f274: 04fc6863 bltu s8,a5,8000f2c4 <_svfiprintf_r+0x18c> +8000f278: 01012703 lw a4,16(sp) +8000f27c: 00279793 slli a5,a5,0x2 +8000f280: 00e787b3 add a5,a5,a4 +8000f284: 0007a783 lw a5,0(a5) +8000f288: 00078067 jr a5 +8000f28c: 00012223 sw zero,4(sp) +8000f290: fd068793 addi a5,a3,-48 +8000f294: 00412603 lw a2,4(sp) +8000f298: 0009c683 lbu a3,0(s3) +8000f29c: 00198993 addi s3,s3,1 +8000f2a0: 00261713 slli a4,a2,0x2 +8000f2a4: 00c70733 add a4,a4,a2 +8000f2a8: 00171713 slli a4,a4,0x1 +8000f2ac: 00e787b3 add a5,a5,a4 +8000f2b0: 00f12223 sw a5,4(sp) +8000f2b4: fd068793 addi a5,a3,-48 +8000f2b8: fcfcfee3 bgeu s9,a5,8000f294 <_svfiprintf_r+0x15c> +8000f2bc: fe068793 addi a5,a3,-32 +8000f2c0: fafc7ce3 bgeu s8,a5,8000f278 <_svfiprintf_r+0x140> +8000f2c4: 12068a63 beqz a3,8000f3f8 <_svfiprintf_r+0x2c0> +8000f2c8: 08d10623 sb a3,140(sp) +8000f2cc: 02010da3 sb zero,59(sp) +8000f2d0: 00100c13 li s8,1 +8000f2d4: 00100c93 li s9,1 +8000f2d8: 08c10413 addi s0,sp,140 +8000f2dc: 00000893 li a7,0 +8000f2e0: 00297f13 andi t5,s2,2 +8000f2e4: 000f0463 beqz t5,8000f2ec <_svfiprintf_r+0x1b4> +8000f2e8: 002c0c13 addi s8,s8,2 +8000f2ec: 08497e93 andi t4,s2,132 +8000f2f0: 04812783 lw a5,72(sp) +8000f2f4: 04412603 lw a2,68(sp) +8000f2f8: 000e9863 bnez t4,8000f308 <_svfiprintf_r+0x1d0> +8000f2fc: 00412703 lw a4,4(sp) +8000f300: 41870db3 sub s11,a4,s8 +8000f304: 7bb04a63 bgtz s11,8000fab8 <_svfiprintf_r+0x980> +8000f308: 03b14503 lbu a0,59(sp) +8000f30c: 00160593 addi a1,a2,1 +8000f310: 008d0693 addi a3,s10,8 +8000f314: 04050063 beqz a0,8000f354 <_svfiprintf_r+0x21c> +8000f318: 03b10513 addi a0,sp,59 +8000f31c: 00178793 addi a5,a5,1 +8000f320: 00ad2023 sw a0,0(s10) +8000f324: 00100513 li a0,1 +8000f328: 00ad2223 sw a0,4(s10) +8000f32c: 04f12423 sw a5,72(sp) +8000f330: 04b12223 sw a1,68(sp) +8000f334: 00700513 li a0,7 +8000f338: 0ab540e3 blt a0,a1,8000fbd8 <_svfiprintf_r+0xaa0> +8000f33c: 00260f93 addi t6,a2,2 +8000f340: 010d0513 addi a0,s10,16 +8000f344: 00058613 mv a2,a1 +8000f348: 00068d13 mv s10,a3 +8000f34c: 000f8593 mv a1,t6 +8000f350: 00050693 mv a3,a0 +8000f354: 020f0c63 beqz t5,8000f38c <_svfiprintf_r+0x254> +8000f358: 03c10613 addi a2,sp,60 +8000f35c: 00278793 addi a5,a5,2 +8000f360: 00cd2023 sw a2,0(s10) +8000f364: 00200613 li a2,2 +8000f368: 00cd2223 sw a2,4(s10) +8000f36c: 04f12423 sw a5,72(sp) +8000f370: 04b12223 sw a1,68(sp) +8000f374: 00700713 li a4,7 +8000f378: 0ab742e3 blt a4,a1,8000fc1c <_svfiprintf_r+0xae4> +8000f37c: 00058613 mv a2,a1 +8000f380: 00068d13 mv s10,a3 +8000f384: 00158593 addi a1,a1,1 +8000f388: 00868693 addi a3,a3,8 +8000f38c: 08000513 li a0,128 +8000f390: 54ae8c63 beq t4,a0,8000f8e8 <_svfiprintf_r+0x7b0> +8000f394: 41988db3 sub s11,a7,s9 +8000f398: 63b04463 bgtz s11,8000f9c0 <_svfiprintf_r+0x888> +8000f39c: 00fc87b3 add a5,s9,a5 +8000f3a0: 008d2023 sw s0,0(s10) +8000f3a4: 019d2223 sw s9,4(s10) +8000f3a8: 04f12423 sw a5,72(sp) +8000f3ac: 04b12223 sw a1,68(sp) +8000f3b0: 00700713 li a4,7 +8000f3b4: 6cb74263 blt a4,a1,8000fa78 <_svfiprintf_r+0x940> +8000f3b8: 00497313 andi t1,s2,4 +8000f3bc: 00030863 beqz t1,8000f3cc <_svfiprintf_r+0x294> +8000f3c0: 00412703 lw a4,4(sp) +8000f3c4: 41870cb3 sub s9,a4,s8 +8000f3c8: 099048e3 bgtz s9,8000fc58 <_svfiprintf_r+0xb20> +8000f3cc: 00412403 lw s0,4(sp) +8000f3d0: 01845463 bge s0,s8,8000f3d8 <_svfiprintf_r+0x2a0> +8000f3d4: 000c0413 mv s0,s8 +8000f3d8: 00812703 lw a4,8(sp) +8000f3dc: 00870733 add a4,a4,s0 +8000f3e0: 00e12423 sw a4,8(sp) +8000f3e4: 6a079a63 bnez a5,8000fa98 <_svfiprintf_r+0x960> +8000f3e8: 0009c783 lbu a5,0(s3) +8000f3ec: 04012223 sw zero,68(sp) +8000f3f0: 000a8d13 mv s10,s5 +8000f3f4: de0798e3 bnez a5,8000f1e4 <_svfiprintf_r+0xac> +8000f3f8: 04812783 lw a5,72(sp) +8000f3fc: 56079ee3 bnez a5,80010178 <_svfiprintf_r+0x1040> +8000f400: 00ca5783 lhu a5,12(s4) +8000f404: 0407f793 andi a5,a5,64 +8000f408: 5a0794e3 bnez a5,800101b0 <_svfiprintf_r+0x1078> +8000f40c: 12c12083 lw ra,300(sp) +8000f410: 12812403 lw s0,296(sp) +8000f414: 00812503 lw a0,8(sp) +8000f418: 12412483 lw s1,292(sp) +8000f41c: 12012903 lw s2,288(sp) +8000f420: 11c12983 lw s3,284(sp) +8000f424: 11812a03 lw s4,280(sp) +8000f428: 11412a83 lw s5,276(sp) +8000f42c: 11012b03 lw s6,272(sp) +8000f430: 10c12b83 lw s7,268(sp) +8000f434: 10812c03 lw s8,264(sp) +8000f438: 10412c83 lw s9,260(sp) +8000f43c: 10012d03 lw s10,256(sp) +8000f440: 0fc12d83 lw s11,252(sp) +8000f444: 13010113 addi sp,sp,304 +8000f448: 00008067 ret +8000f44c: 000b0513 mv a0,s6 +8000f450: d58f80ef jal ra,800079a8 <_localeconv_r> +8000f454: 00452783 lw a5,4(a0) +8000f458: 00078513 mv a0,a5 +8000f45c: 00f12e23 sw a5,28(sp) +8000f460: d00fa0ef jal ra,80009960 +8000f464: 00050793 mv a5,a0 +8000f468: 000b0513 mv a0,s6 +8000f46c: 00078d93 mv s11,a5 +8000f470: 02f12023 sw a5,32(sp) +8000f474: d34f80ef jal ra,800079a8 <_localeconv_r> +8000f478: 00852783 lw a5,8(a0) +8000f47c: 02a00593 li a1,42 +8000f480: 00f12c23 sw a5,24(sp) +8000f484: 1e0d98e3 bnez s11,8000fe74 <_svfiprintf_r+0xd3c> +8000f488: 0009c683 lbu a3,0(s3) +8000f48c: de1ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f490: 0009c683 lbu a3,0(s3) +8000f494: 02096913 ori s2,s2,32 +8000f498: dd5ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f49c: 41340c33 sub s8,s0,s3 +8000f4a0: d73412e3 bne s0,s3,8000f204 <_svfiprintf_r+0xcc> +8000f4a4: 00044783 lbu a5,0(s0) +8000f4a8: d99ff06f j 8000f240 <_svfiprintf_r+0x108> +8000f4ac: 04010613 addi a2,sp,64 +8000f4b0: 000a0593 mv a1,s4 +8000f4b4: 000b0513 mv a0,s6 +8000f4b8: ac5ff0ef jal ra,8000ef7c <__ssprint_r> +8000f4bc: f40512e3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000f4c0: 000a8d13 mv s10,s5 +8000f4c4: d6dff06f j 8000f230 <_svfiprintf_r+0xf8> +8000f4c8: 00c12783 lw a5,12(sp) +8000f4cc: 00040893 mv a7,s0 +8000f4d0: 02010da3 sb zero,59(sp) +8000f4d4: 0007a403 lw s0,0(a5) +8000f4d8: 00478d93 addi s11,a5,4 +8000f4dc: 380404e3 beqz s0,80010064 <_svfiprintf_r+0xf2c> +8000f4e0: fff00793 li a5,-1 +8000f4e4: 26f88ee3 beq a7,a5,8000ff60 <_svfiprintf_r+0xe28> +8000f4e8: 00088613 mv a2,a7 +8000f4ec: 00000593 li a1,0 +8000f4f0: 00040513 mv a0,s0 +8000f4f4: 01112623 sw a7,12(sp) +8000f4f8: e49f80ef jal ra,80008340 +8000f4fc: 00c12883 lw a7,12(sp) +8000f500: 480506e3 beqz a0,8001018c <_svfiprintf_r+0x1054> +8000f504: 40850cb3 sub s9,a0,s0 +8000f508: 01b12623 sw s11,12(sp) +8000f50c: 00000893 li a7,0 +8000f510: 0940006f j 8000f5a4 <_svfiprintf_r+0x46c> +8000f514: 00c12703 lw a4,12(sp) +8000f518: 02010da3 sb zero,59(sp) +8000f51c: 00100c13 li s8,1 +8000f520: 00072783 lw a5,0(a4) +8000f524: 00470713 addi a4,a4,4 +8000f528: 00e12623 sw a4,12(sp) +8000f52c: 08f10623 sb a5,140(sp) +8000f530: 00100c93 li s9,1 +8000f534: 08c10413 addi s0,sp,140 +8000f538: da5ff06f j 8000f2dc <_svfiprintf_r+0x1a4> 8000f53c: 02097793 andi a5,s2,32 -8000f540: 74078463 beqz a5,8000fc88 <_svfiprintf_r+0xbdc> -8000f544: 00c12783 lw a5,12(sp) -8000f548: 00778793 addi a5,a5,7 -8000f54c: ff87f793 andi a5,a5,-8 -8000f550: 0007ac83 lw s9,0(a5) -8000f554: 0047ac03 lw s8,4(a5) -8000f558: 00878793 addi a5,a5,8 -8000f55c: 00f12623 sw a5,12(sp) -8000f560: bff97d93 andi s11,s2,-1025 -8000f564: 00000693 li a3,0 -8000f568: 02010da3 sb zero,59(sp) -8000f56c: fff00613 li a2,-1 -8000f570: 08c88e63 beq a7,a2,8000f60c <_svfiprintf_r+0x560> -8000f574: 018ce633 or a2,s9,s8 -8000f578: f7fdf913 andi s2,s11,-129 -8000f57c: 4a061463 bnez a2,8000fa24 <_svfiprintf_r+0x978> -8000f580: 28089263 bnez a7,8000f804 <_svfiprintf_r+0x758> -8000f584: 6e069a63 bnez a3,8000fc78 <_svfiprintf_r+0xbcc> -8000f588: 001dfc93 andi s9,s11,1 -8000f58c: 0f010413 addi s0,sp,240 -8000f590: f80c84e3 beqz s9,8000f518 <_svfiprintf_r+0x46c> -8000f594: 03000793 li a5,48 -8000f598: 0ef107a3 sb a5,239(sp) -8000f59c: 0ef10413 addi s0,sp,239 -8000f5a0: f79ff06f j 8000f518 <_svfiprintf_r+0x46c> -8000f5a4: 01096913 ori s2,s2,16 -8000f5a8: 02097793 andi a5,s2,32 -8000f5ac: 00040893 mv a7,s0 -8000f5b0: f00796e3 bnez a5,8000f4bc <_svfiprintf_r+0x410> -8000f5b4: 00c12703 lw a4,12(sp) -8000f5b8: 01097793 andi a5,s2,16 -8000f5bc: 00470693 addi a3,a4,4 -8000f5c0: 040792e3 bnez a5,8000fe04 <_svfiprintf_r+0xd58> -8000f5c4: 04097793 andi a5,s2,64 -8000f5c8: 260786e3 beqz a5,80010034 <_svfiprintf_r+0xf88> -8000f5cc: 00c12783 lw a5,12(sp) -8000f5d0: 00d12623 sw a3,12(sp) -8000f5d4: 00079c83 lh s9,0(a5) -8000f5d8: 41fcdc13 srai s8,s9,0x1f -8000f5dc: 000c0693 mv a3,s8 -8000f5e0: f006d0e3 bgez a3,8000f4e0 <_svfiprintf_r+0x434> -8000f5e4: 019036b3 snez a3,s9 -8000f5e8: 41800eb3 neg t4,s8 -8000f5ec: 40de8c33 sub s8,t4,a3 -8000f5f0: 02d00693 li a3,45 -8000f5f4: 02d10da3 sb a3,59(sp) +8000f540: 00040893 mv a7,s0 +8000f544: 0e078e63 beqz a5,8000f640 <_svfiprintf_r+0x508> +8000f548: 00c12783 lw a5,12(sp) +8000f54c: 00778793 addi a5,a5,7 +8000f550: ff87f793 andi a5,a5,-8 +8000f554: 0047a683 lw a3,4(a5) +8000f558: 0007ac83 lw s9,0(a5) +8000f55c: 00878793 addi a5,a5,8 +8000f560: 00f12623 sw a5,12(sp) +8000f564: 00068c13 mv s8,a3 +8000f568: 1006c463 bltz a3,8000f670 <_svfiprintf_r+0x538> +8000f56c: fff00693 li a3,-1 +8000f570: 00090d93 mv s11,s2 +8000f574: 00d88863 beq a7,a3,8000f584 <_svfiprintf_r+0x44c> +8000f578: 018ce6b3 or a3,s9,s8 +8000f57c: f7f97d93 andi s11,s2,-129 +8000f580: 76068e63 beqz a3,8000fcfc <_svfiprintf_r+0xbc4> +8000f584: 000c1ce3 bnez s8,8000fd9c <_svfiprintf_r+0xc64> +8000f588: 00900693 li a3,9 +8000f58c: 0196e8e3 bltu a3,s9,8000fd9c <_svfiprintf_r+0xc64> +8000f590: 030c8793 addi a5,s9,48 +8000f594: 0ef107a3 sb a5,239(sp) +8000f598: 000d8913 mv s2,s11 +8000f59c: 00100c93 li s9,1 +8000f5a0: 0ef10413 addi s0,sp,239 +8000f5a4: 00088c13 mv s8,a7 +8000f5a8: 0198d463 bge a7,s9,8000f5b0 <_svfiprintf_r+0x478> +8000f5ac: 000c8c13 mv s8,s9 +8000f5b0: 03b14783 lbu a5,59(sp) +8000f5b4: 00f037b3 snez a5,a5 +8000f5b8: 00fc0c33 add s8,s8,a5 +8000f5bc: d25ff06f j 8000f2e0 <_svfiprintf_r+0x1a8> +8000f5c0: 00040893 mv a7,s0 +8000f5c4: 01096913 ori s2,s2,16 +8000f5c8: 02097793 andi a5,s2,32 +8000f5cc: 74078463 beqz a5,8000fd14 <_svfiprintf_r+0xbdc> +8000f5d0: 00c12783 lw a5,12(sp) +8000f5d4: 00778793 addi a5,a5,7 +8000f5d8: ff87f793 andi a5,a5,-8 +8000f5dc: 0007ac83 lw s9,0(a5) +8000f5e0: 0047ac03 lw s8,4(a5) +8000f5e4: 00878793 addi a5,a5,8 +8000f5e8: 00f12623 sw a5,12(sp) +8000f5ec: bff97d93 andi s11,s2,-1025 +8000f5f0: 00000693 li a3,0 +8000f5f4: 02010da3 sb zero,59(sp) 8000f5f8: fff00613 li a2,-1 -8000f5fc: 41900cb3 neg s9,s9 -8000f600: 00090d93 mv s11,s2 -8000f604: 00100693 li a3,1 -8000f608: f6c896e3 bne a7,a2,8000f574 <_svfiprintf_r+0x4c8> -8000f60c: 00100613 li a2,1 -8000f610: eec684e3 beq a3,a2,8000f4f8 <_svfiprintf_r+0x44c> -8000f614: 00200613 li a2,2 -8000f618: 20c68063 beq a3,a2,8000f818 <_svfiprintf_r+0x76c> -8000f61c: 0f010413 addi s0,sp,240 -8000f620: 01dc1793 slli a5,s8,0x1d -8000f624: 007cf693 andi a3,s9,7 -8000f628: 003cdc93 srli s9,s9,0x3 -8000f62c: 03068693 addi a3,a3,48 -8000f630: 0197ecb3 or s9,a5,s9 -8000f634: 003c5c13 srli s8,s8,0x3 -8000f638: fed40fa3 sb a3,-1(s0) -8000f63c: 018ce7b3 or a5,s9,s8 -8000f640: 00040593 mv a1,s0 -8000f644: fff40413 addi s0,s0,-1 -8000f648: fc079ce3 bnez a5,8000f620 <_svfiprintf_r+0x574> -8000f64c: 001df793 andi a5,s11,1 -8000f650: 1e078e63 beqz a5,8000f84c <_svfiprintf_r+0x7a0> -8000f654: 03000793 li a5,48 -8000f658: 1ef68a63 beq a3,a5,8000f84c <_svfiprintf_r+0x7a0> -8000f65c: ffe58593 addi a1,a1,-2 -8000f660: fef40fa3 sb a5,-1(s0) -8000f664: 0f010793 addi a5,sp,240 -8000f668: 40b78cb3 sub s9,a5,a1 -8000f66c: 000d8913 mv s2,s11 -8000f670: 00058413 mv s0,a1 -8000f674: ea5ff06f j 8000f518 <_svfiprintf_r+0x46c> -8000f678: 00040893 mv a7,s0 -8000f67c: 01096d93 ori s11,s2,16 -8000f680: 020df793 andi a5,s11,32 -8000f684: 62078863 beqz a5,8000fcb4 <_svfiprintf_r+0xc08> -8000f688: 00c12783 lw a5,12(sp) -8000f68c: 00100693 li a3,1 -8000f690: 00778913 addi s2,a5,7 -8000f694: ff897913 andi s2,s2,-8 -8000f698: 00890793 addi a5,s2,8 -8000f69c: 00092c83 lw s9,0(s2) -8000f6a0: 00492c03 lw s8,4(s2) -8000f6a4: 00f12623 sw a5,12(sp) -8000f6a8: ec1ff06f j 8000f568 <_svfiprintf_r+0x4bc> -8000f6ac: 00c12783 lw a5,12(sp) -8000f6b0: ffff86b7 lui a3,0xffff8 -8000f6b4: 8306c693 xori a3,a3,-2000 -8000f6b8: 0007ac83 lw s9,0(a5) -8000f6bc: 00478793 addi a5,a5,4 -8000f6c0: 00f12623 sw a5,12(sp) -8000f6c4: 800157b7 lui a5,0x80015 -8000f6c8: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -8000f6cc: 02d11e23 sh a3,60(sp) -8000f6d0: 00040893 mv a7,s0 -8000f6d4: 00000c13 li s8,0 -8000f6d8: 00296d93 ori s11,s2,2 -8000f6dc: 00f12a23 sw a5,20(sp) -8000f6e0: 00200693 li a3,2 -8000f6e4: e85ff06f j 8000f568 <_svfiprintf_r+0x4bc> -8000f6e8: 0009c683 lbu a3,0(s3) -8000f6ec: 08096913 ori s2,s2,128 -8000f6f0: af1ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f6f4: 0009c683 lbu a3,0(s3) -8000f6f8: 00198713 addi a4,s3,1 -8000f6fc: 22b68ae3 beq a3,a1,80010130 <_svfiprintf_r+0x1084> -8000f700: fd068793 addi a5,a3,-48 # ffff7fd0 <__BSS_END__+0x7ffe13a0> -8000f704: 00070993 mv s3,a4 -8000f708: 00000413 li s0,0 -8000f70c: acfcece3 bltu s9,a5,8000f1e4 <_svfiprintf_r+0x138> -8000f710: 0009c683 lbu a3,0(s3) -8000f714: 00241713 slli a4,s0,0x2 -8000f718: 008708b3 add a7,a4,s0 -8000f71c: 00189893 slli a7,a7,0x1 -8000f720: 00f88433 add s0,a7,a5 -8000f724: fd068793 addi a5,a3,-48 -8000f728: 00198993 addi s3,s3,1 -8000f72c: fefcf2e3 bgeu s9,a5,8000f710 <_svfiprintf_r+0x664> -8000f730: ab5ff06f j 8000f1e4 <_svfiprintf_r+0x138> -8000f734: 0009c683 lbu a3,0(s3) -8000f738: 00496913 ori s2,s2,4 -8000f73c: aa5ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f740: 02b00793 li a5,43 -8000f744: 0009c683 lbu a3,0(s3) -8000f748: 02f10da3 sb a5,59(sp) -8000f74c: a95ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f750: 00c12703 lw a4,12(sp) -8000f754: 0009c683 lbu a3,0(s3) -8000f758: 00072783 lw a5,0(a4) -8000f75c: 00470713 addi a4,a4,4 -8000f760: 00e12623 sw a4,12(sp) -8000f764: 00f12223 sw a5,4(sp) -8000f768: a607dce3 bgez a5,8000f1e0 <_svfiprintf_r+0x134> -8000f76c: 40f007b3 neg a5,a5 -8000f770: 00f12223 sw a5,4(sp) -8000f774: 00496913 ori s2,s2,4 -8000f778: a69ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f77c: 0009c683 lbu a3,0(s3) -8000f780: 00196913 ori s2,s2,1 -8000f784: a5dff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f788: 03b14783 lbu a5,59(sp) -8000f78c: 0009c683 lbu a3,0(s3) -8000f790: a40798e3 bnez a5,8000f1e0 <_svfiprintf_r+0x134> -8000f794: 02000793 li a5,32 -8000f798: 02f10da3 sb a5,59(sp) -8000f79c: a45ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f7a0: 0009c683 lbu a3,0(s3) -8000f7a4: 06800793 li a5,104 -8000f7a8: 7ef68e63 beq a3,a5,8000ffa4 <_svfiprintf_r+0xef8> -8000f7ac: 04096913 ori s2,s2,64 -8000f7b0: a31ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f7b4: 00c12703 lw a4,12(sp) -8000f7b8: 02097793 andi a5,s2,32 -8000f7bc: 00072683 lw a3,0(a4) -8000f7c0: 00470713 addi a4,a4,4 -8000f7c4: 00e12623 sw a4,12(sp) -8000f7c8: 5e079c63 bnez a5,8000fdc0 <_svfiprintf_r+0xd14> -8000f7cc: 01097793 andi a5,s2,16 -8000f7d0: 7e079e63 bnez a5,8000ffcc <_svfiprintf_r+0xf20> -8000f7d4: 04097793 andi a5,s2,64 -8000f7d8: 100794e3 bnez a5,800100e0 <_svfiprintf_r+0x1034> -8000f7dc: 20097313 andi t1,s2,512 -8000f7e0: 7e030663 beqz t1,8000ffcc <_svfiprintf_r+0xf20> -8000f7e4: 00812783 lw a5,8(sp) -8000f7e8: 00f68023 sb a5,0(a3) -8000f7ec: 965ff06f j 8000f150 <_svfiprintf_r+0xa4> -8000f7f0: 0009c683 lbu a3,0(s3) -8000f7f4: 06c00793 li a5,108 -8000f7f8: 7af68e63 beq a3,a5,8000ffb4 <_svfiprintf_r+0xf08> -8000f7fc: 01096913 ori s2,s2,16 -8000f800: 9e1ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000f804: 00100613 li a2,1 -8000f808: 10c684e3 beq a3,a2,80010110 <_svfiprintf_r+0x1064> -8000f80c: 00200613 li a2,2 -8000f810: 00090d93 mv s11,s2 -8000f814: e0c694e3 bne a3,a2,8000f61c <_svfiprintf_r+0x570> -8000f818: 01412683 lw a3,20(sp) -8000f81c: 0f010413 addi s0,sp,240 -8000f820: 00fcf793 andi a5,s9,15 -8000f824: 00f687b3 add a5,a3,a5 -8000f828: 0007c703 lbu a4,0(a5) -8000f82c: 004cdc93 srli s9,s9,0x4 -8000f830: 01cc1793 slli a5,s8,0x1c -8000f834: 0197ecb3 or s9,a5,s9 -8000f838: 004c5c13 srli s8,s8,0x4 -8000f83c: fee40fa3 sb a4,-1(s0) -8000f840: 018ce7b3 or a5,s9,s8 -8000f844: fff40413 addi s0,s0,-1 -8000f848: fc079ce3 bnez a5,8000f820 <_svfiprintf_r+0x774> -8000f84c: 0f010793 addi a5,sp,240 -8000f850: 40878cb3 sub s9,a5,s0 -8000f854: 000d8913 mv s2,s11 -8000f858: cc1ff06f j 8000f518 <_svfiprintf_r+0x46c> -8000f85c: 00412703 lw a4,4(sp) -8000f860: 41870db3 sub s11,a4,s8 -8000f864: abb052e3 blez s11,8000f308 <_svfiprintf_r+0x25c> -8000f868: 01000513 li a0,16 -8000f86c: 0bb556e3 bge a0,s11,80010118 <_svfiprintf_r+0x106c> -8000f870: 02812223 sw s0,36(sp) -8000f874: 01000693 li a3,16 -8000f878: 000a0413 mv s0,s4 -8000f87c: 00700e93 li t4,7 -8000f880: 000d8a13 mv s4,s11 -8000f884: 00098d93 mv s11,s3 -8000f888: 00088993 mv s3,a7 -8000f88c: 00c0006f j 8000f898 <_svfiprintf_r+0x7ec> -8000f890: ff0a0a13 addi s4,s4,-16 -8000f894: 0546da63 bge a3,s4,8000f8e8 <_svfiprintf_r+0x83c> -8000f898: 01078793 addi a5,a5,16 -8000f89c: 00160613 addi a2,a2,1 -8000f8a0: 009d2023 sw s1,0(s10) -8000f8a4: 00dd2223 sw a3,4(s10) -8000f8a8: 04f12423 sw a5,72(sp) -8000f8ac: 04c12223 sw a2,68(sp) -8000f8b0: 008d0d13 addi s10,s10,8 -8000f8b4: fccedee3 bge t4,a2,8000f890 <_svfiprintf_r+0x7e4> -8000f8b8: 04010613 addi a2,sp,64 -8000f8bc: 00040593 mv a1,s0 -8000f8c0: 000b0513 mv a0,s6 -8000f8c4: e2cff0ef jal ra,8000eef0 <__ssprint_r> -8000f8c8: 6e051e63 bnez a0,8000ffc4 <_svfiprintf_r+0xf18> -8000f8cc: 01000693 li a3,16 -8000f8d0: ff0a0a13 addi s4,s4,-16 -8000f8d4: 04812783 lw a5,72(sp) -8000f8d8: 04412603 lw a2,68(sp) -8000f8dc: 000a8d13 mv s10,s5 -8000f8e0: 00700e93 li t4,7 -8000f8e4: fb46cae3 blt a3,s4,8000f898 <_svfiprintf_r+0x7ec> -8000f8e8: 00098893 mv a7,s3 -8000f8ec: 000d8993 mv s3,s11 -8000f8f0: 000a0d93 mv s11,s4 -8000f8f4: 00040a13 mv s4,s0 -8000f8f8: 02412403 lw s0,36(sp) -8000f8fc: 00160613 addi a2,a2,1 -8000f900: 008d0513 addi a0,s10,8 -8000f904: 01b787b3 add a5,a5,s11 -8000f908: 009d2023 sw s1,0(s10) -8000f90c: 01bd2223 sw s11,4(s10) -8000f910: 04f12423 sw a5,72(sp) -8000f914: 04c12223 sw a2,68(sp) -8000f918: 00700713 li a4,7 -8000f91c: 64c74a63 blt a4,a2,8000ff70 <_svfiprintf_r+0xec4> -8000f920: 41988db3 sub s11,a7,s9 -8000f924: 00160593 addi a1,a2,1 -8000f928: 00850693 addi a3,a0,8 -8000f92c: 00050d13 mv s10,a0 -8000f930: 9fb050e3 blez s11,8000f310 <_svfiprintf_r+0x264> -8000f934: 01000513 li a0,16 -8000f938: 73b55e63 bge a0,s11,80010074 <_svfiprintf_r+0xfc8> -8000f93c: 01000693 li a3,16 -8000f940: 00700893 li a7,7 -8000f944: 00c0006f j 8000f950 <_svfiprintf_r+0x8a4> -8000f948: ff0d8d93 addi s11,s11,-16 -8000f94c: 05b6da63 bge a3,s11,8000f9a0 <_svfiprintf_r+0x8f4> -8000f950: 01078793 addi a5,a5,16 -8000f954: 00160613 addi a2,a2,1 -8000f958: 009d2023 sw s1,0(s10) -8000f95c: 00dd2223 sw a3,4(s10) -8000f960: 04f12423 sw a5,72(sp) -8000f964: 04c12223 sw a2,68(sp) -8000f968: 008d0d13 addi s10,s10,8 -8000f96c: fcc8dee3 bge a7,a2,8000f948 <_svfiprintf_r+0x89c> -8000f970: 04010613 addi a2,sp,64 -8000f974: 000a0593 mv a1,s4 -8000f978: 000b0513 mv a0,s6 -8000f97c: d74ff0ef jal ra,8000eef0 <__ssprint_r> -8000f980: 9e051ae3 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000f984: 01000693 li a3,16 -8000f988: ff0d8d93 addi s11,s11,-16 -8000f98c: 04812783 lw a5,72(sp) -8000f990: 04412603 lw a2,68(sp) -8000f994: 000a8d13 mv s10,s5 -8000f998: 00700893 li a7,7 -8000f99c: fbb6cae3 blt a3,s11,8000f950 <_svfiprintf_r+0x8a4> -8000f9a0: 00160593 addi a1,a2,1 -8000f9a4: 008d0613 addi a2,s10,8 -8000f9a8: 01b787b3 add a5,a5,s11 -8000f9ac: 009d2023 sw s1,0(s10) -8000f9b0: 01bd2223 sw s11,4(s10) -8000f9b4: 04f12423 sw a5,72(sp) -8000f9b8: 04b12223 sw a1,68(sp) -8000f9bc: 00700713 li a4,7 -8000f9c0: 32b74263 blt a4,a1,8000fce4 <_svfiprintf_r+0xc38> -8000f9c4: 00060d13 mv s10,a2 -8000f9c8: 00158593 addi a1,a1,1 -8000f9cc: 00fc87b3 add a5,s9,a5 -8000f9d0: 008d2023 sw s0,0(s10) -8000f9d4: 019d2223 sw s9,4(s10) -8000f9d8: 04f12423 sw a5,72(sp) -8000f9dc: 04b12223 sw a1,68(sp) -8000f9e0: 00700713 li a4,7 -8000f9e4: 00860693 addi a3,a2,8 -8000f9e8: 94b752e3 bge a4,a1,8000f32c <_svfiprintf_r+0x280> -8000f9ec: 04010613 addi a2,sp,64 -8000f9f0: 000a0593 mv a1,s4 -8000f9f4: 000b0513 mv a0,s6 -8000f9f8: cf8ff0ef jal ra,8000eef0 <__ssprint_r> -8000f9fc: 96051ce3 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000fa00: 04812783 lw a5,72(sp) -8000fa04: 000a8693 mv a3,s5 -8000fa08: 925ff06f j 8000f32c <_svfiprintf_r+0x280> -8000fa0c: 04010613 addi a2,sp,64 -8000fa10: 000a0593 mv a1,s4 -8000fa14: 000b0513 mv a0,s6 -8000fa18: cd8ff0ef jal ra,8000eef0 <__ssprint_r> -8000fa1c: 940500e3 beqz a0,8000f35c <_svfiprintf_r+0x2b0> -8000fa20: 955ff06f j 8000f374 <_svfiprintf_r+0x2c8> -8000fa24: 00090d93 mv s11,s2 -8000fa28: be5ff06f j 8000f60c <_svfiprintf_r+0x560> -8000fa2c: 01000693 li a3,16 -8000fa30: 0bb6de63 bge a3,s11,8000faec <_svfiprintf_r+0xa40> -8000fa34: 000d0713 mv a4,s10 -8000fa38: 00700f93 li t6,7 -8000fa3c: 000c0d13 mv s10,s8 -8000fa40: 03e12223 sw t5,36(sp) -8000fa44: 00090c13 mv s8,s2 -8000fa48: 03d12423 sw t4,40(sp) -8000fa4c: 000a0913 mv s2,s4 -8000fa50: 00098a13 mv s4,s3 -8000fa54: 00040993 mv s3,s0 -8000fa58: 000d8413 mv s0,s11 -8000fa5c: 000c8d93 mv s11,s9 -8000fa60: 00088c93 mv s9,a7 -8000fa64: 00c0006f j 8000fa70 <_svfiprintf_r+0x9c4> -8000fa68: ff040413 addi s0,s0,-16 -8000fa6c: 0486da63 bge a3,s0,8000fac0 <_svfiprintf_r+0xa14> -8000fa70: 01078793 addi a5,a5,16 -8000fa74: 00160613 addi a2,a2,1 -8000fa78: 01772023 sw s7,0(a4) -8000fa7c: 00d72223 sw a3,4(a4) -8000fa80: 04f12423 sw a5,72(sp) -8000fa84: 04c12223 sw a2,68(sp) -8000fa88: 00870713 addi a4,a4,8 -8000fa8c: fccfdee3 bge t6,a2,8000fa68 <_svfiprintf_r+0x9bc> -8000fa90: 04010613 addi a2,sp,64 -8000fa94: 00090593 mv a1,s2 -8000fa98: 000b0513 mv a0,s6 -8000fa9c: c54ff0ef jal ra,8000eef0 <__ssprint_r> -8000faa0: 4a051663 bnez a0,8000ff4c <_svfiprintf_r+0xea0> -8000faa4: 01000693 li a3,16 -8000faa8: ff040413 addi s0,s0,-16 -8000faac: 04812783 lw a5,72(sp) -8000fab0: 04412603 lw a2,68(sp) -8000fab4: 000a8713 mv a4,s5 -8000fab8: 00700f93 li t6,7 -8000fabc: fa86cae3 blt a3,s0,8000fa70 <_svfiprintf_r+0x9c4> -8000fac0: 02412f03 lw t5,36(sp) -8000fac4: 02812e83 lw t4,40(sp) -8000fac8: 000c8893 mv a7,s9 -8000facc: 000d8c93 mv s9,s11 -8000fad0: 00040d93 mv s11,s0 -8000fad4: 00098413 mv s0,s3 -8000fad8: 000a0993 mv s3,s4 -8000fadc: 00090a13 mv s4,s2 -8000fae0: 000c0913 mv s2,s8 -8000fae4: 000d0c13 mv s8,s10 -8000fae8: 00070d13 mv s10,a4 -8000faec: 01b787b3 add a5,a5,s11 -8000faf0: 00160613 addi a2,a2,1 -8000faf4: 017d2023 sw s7,0(s10) -8000faf8: 01bd2223 sw s11,4(s10) -8000fafc: 04f12423 sw a5,72(sp) -8000fb00: 04c12223 sw a2,68(sp) -8000fb04: 00700693 li a3,7 -8000fb08: 008d0d13 addi s10,s10,8 -8000fb0c: f6c6d863 bge a3,a2,8000f27c <_svfiprintf_r+0x1d0> -8000fb10: 04010613 addi a2,sp,64 -8000fb14: 000a0593 mv a1,s4 -8000fb18: 000b0513 mv a0,s6 -8000fb1c: 03112623 sw a7,44(sp) -8000fb20: 03d12423 sw t4,40(sp) -8000fb24: 03e12223 sw t5,36(sp) -8000fb28: bc8ff0ef jal ra,8000eef0 <__ssprint_r> -8000fb2c: 840514e3 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000fb30: 04812783 lw a5,72(sp) -8000fb34: 04412603 lw a2,68(sp) -8000fb38: 02c12883 lw a7,44(sp) -8000fb3c: 02812e83 lw t4,40(sp) -8000fb40: 02412f03 lw t5,36(sp) -8000fb44: 000a8d13 mv s10,s5 -8000fb48: f34ff06f j 8000f27c <_svfiprintf_r+0x1d0> -8000fb4c: 04010613 addi a2,sp,64 -8000fb50: 000a0593 mv a1,s4 -8000fb54: 000b0513 mv a0,s6 -8000fb58: 03112623 sw a7,44(sp) -8000fb5c: 03d12423 sw t4,40(sp) -8000fb60: 03e12223 sw t5,36(sp) -8000fb64: b8cff0ef jal ra,8000eef0 <__ssprint_r> -8000fb68: 800516e3 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000fb6c: 04412603 lw a2,68(sp) -8000fb70: 04812783 lw a5,72(sp) -8000fb74: 02c12883 lw a7,44(sp) -8000fb78: 02812e83 lw t4,40(sp) -8000fb7c: 02412f03 lw t5,36(sp) -8000fb80: 05410693 addi a3,sp,84 -8000fb84: 00160593 addi a1,a2,1 -8000fb88: 000a8d13 mv s10,s5 -8000fb8c: f3cff06f j 8000f2c8 <_svfiprintf_r+0x21c> -8000fb90: 04010613 addi a2,sp,64 -8000fb94: 000a0593 mv a1,s4 -8000fb98: 000b0513 mv a0,s6 -8000fb9c: 03112423 sw a7,40(sp) -8000fba0: 03d12223 sw t4,36(sp) -8000fba4: b4cff0ef jal ra,8000eef0 <__ssprint_r> -8000fba8: fc051663 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000fbac: 04412603 lw a2,68(sp) -8000fbb0: 04812783 lw a5,72(sp) -8000fbb4: 02812883 lw a7,40(sp) -8000fbb8: 02412e83 lw t4,36(sp) -8000fbbc: 05410693 addi a3,sp,84 -8000fbc0: 00160593 addi a1,a2,1 -8000fbc4: 000a8d13 mv s10,s5 -8000fbc8: f38ff06f j 8000f300 <_svfiprintf_r+0x254> -8000fbcc: 01000613 li a2,16 -8000fbd0: 04412703 lw a4,68(sp) -8000fbd4: 07965063 bge a2,s9,8000fc34 <_svfiprintf_r+0xb88> -8000fbd8: 01000d93 li s11,16 -8000fbdc: 00700413 li s0,7 -8000fbe0: 00c0006f j 8000fbec <_svfiprintf_r+0xb40> -8000fbe4: ff0c8c93 addi s9,s9,-16 -8000fbe8: 059dd663 bge s11,s9,8000fc34 <_svfiprintf_r+0xb88> -8000fbec: 01078793 addi a5,a5,16 -8000fbf0: 00170713 addi a4,a4,1 -8000fbf4: 0176a023 sw s7,0(a3) -8000fbf8: 01b6a223 sw s11,4(a3) -8000fbfc: 04f12423 sw a5,72(sp) -8000fc00: 04e12223 sw a4,68(sp) -8000fc04: 00868693 addi a3,a3,8 -8000fc08: fce45ee3 bge s0,a4,8000fbe4 <_svfiprintf_r+0xb38> -8000fc0c: 04010613 addi a2,sp,64 -8000fc10: 000a0593 mv a1,s4 -8000fc14: 000b0513 mv a0,s6 -8000fc18: ad8ff0ef jal ra,8000eef0 <__ssprint_r> -8000fc1c: f4051c63 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000fc20: ff0c8c93 addi s9,s9,-16 -8000fc24: 04812783 lw a5,72(sp) -8000fc28: 04412703 lw a4,68(sp) -8000fc2c: 000a8693 mv a3,s5 -8000fc30: fb9dcee3 blt s11,s9,8000fbec <_svfiprintf_r+0xb40> -8000fc34: 019787b3 add a5,a5,s9 -8000fc38: 00170713 addi a4,a4,1 -8000fc3c: 0176a023 sw s7,0(a3) -8000fc40: 0196a223 sw s9,4(a3) -8000fc44: 04f12423 sw a5,72(sp) -8000fc48: 04e12223 sw a4,68(sp) -8000fc4c: 00700693 li a3,7 -8000fc50: eee6d863 bge a3,a4,8000f340 <_svfiprintf_r+0x294> -8000fc54: 04010613 addi a2,sp,64 -8000fc58: 000a0593 mv a1,s4 -8000fc5c: 000b0513 mv a0,s6 -8000fc60: a90ff0ef jal ra,8000eef0 <__ssprint_r> -8000fc64: f0051863 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000fc68: 04812783 lw a5,72(sp) -8000fc6c: ed4ff06f j 8000f340 <_svfiprintf_r+0x294> -8000fc70: 88089ae3 bnez a7,8000f504 <_svfiprintf_r+0x458> -8000fc74: 000d8913 mv s2,s11 -8000fc78: 00000893 li a7,0 -8000fc7c: 00000c93 li s9,0 -8000fc80: 0f010413 addi s0,sp,240 -8000fc84: 895ff06f j 8000f518 <_svfiprintf_r+0x46c> -8000fc88: 00c12703 lw a4,12(sp) -8000fc8c: 01097793 andi a5,s2,16 -8000fc90: 00470693 addi a3,a4,4 -8000fc94: 18079263 bnez a5,8000fe18 <_svfiprintf_r+0xd6c> -8000fc98: 04097793 andi a5,s2,64 -8000fc9c: 36078e63 beqz a5,80010018 <_svfiprintf_r+0xf6c> -8000fca0: 00c12783 lw a5,12(sp) -8000fca4: 00000c13 li s8,0 -8000fca8: 00d12623 sw a3,12(sp) -8000fcac: 0007dc83 lhu s9,0(a5) -8000fcb0: 8b1ff06f j 8000f560 <_svfiprintf_r+0x4b4> -8000fcb4: 00c12703 lw a4,12(sp) -8000fcb8: 010df793 andi a5,s11,16 -8000fcbc: 00470693 addi a3,a4,4 -8000fcc0: 10079a63 bnez a5,8000fdd4 <_svfiprintf_r+0xd28> -8000fcc4: 040df793 andi a5,s11,64 -8000fcc8: 38078663 beqz a5,80010054 <_svfiprintf_r+0xfa8> -8000fccc: 00c12783 lw a5,12(sp) -8000fcd0: 00000c13 li s8,0 -8000fcd4: 00d12623 sw a3,12(sp) -8000fcd8: 0007dc83 lhu s9,0(a5) -8000fcdc: 00100693 li a3,1 -8000fce0: 889ff06f j 8000f568 <_svfiprintf_r+0x4bc> -8000fce4: 04010613 addi a2,sp,64 -8000fce8: 000a0593 mv a1,s4 -8000fcec: 000b0513 mv a0,s6 -8000fcf0: a00ff0ef jal ra,8000eef0 <__ssprint_r> -8000fcf4: e8051063 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000fcf8: 04412583 lw a1,68(sp) -8000fcfc: 04812783 lw a5,72(sp) -8000fd00: 05410693 addi a3,sp,84 -8000fd04: 00158593 addi a1,a1,1 -8000fd08: 000a8d13 mv s10,s5 -8000fd0c: e04ff06f j 8000f310 <_svfiprintf_r+0x264> -8000fd10: 400df793 andi a5,s11,1024 -8000fd14: 03412423 sw s4,40(sp) -8000fd18: 03312623 sw s3,44(sp) -8000fd1c: 000c0a13 mv s4,s8 -8000fd20: 000c8993 mv s3,s9 -8000fd24: 00000913 li s2,0 -8000fd28: 01812c83 lw s9,24(sp) -8000fd2c: 0f010413 addi s0,sp,240 -8000fd30: 03112223 sw a7,36(sp) -8000fd34: 00078c13 mv s8,a5 -8000fd38: 0240006f j 8000fd5c <_svfiprintf_r+0xcb0> -8000fd3c: 00a00613 li a2,10 -8000fd40: 00000693 li a3,0 -8000fd44: 00098513 mv a0,s3 -8000fd48: 000a0593 mv a1,s4 -8000fd4c: 6b4000ef jal ra,80010400 <__udivdi3> -8000fd50: 320a0663 beqz s4,8001007c <_svfiprintf_r+0xfd0> -8000fd54: 00050993 mv s3,a0 -8000fd58: 00058a13 mv s4,a1 -8000fd5c: 00a00613 li a2,10 -8000fd60: 00000693 li a3,0 -8000fd64: 00098513 mv a0,s3 -8000fd68: 000a0593 mv a1,s4 -8000fd6c: 2c9000ef jal ra,80010834 <__umoddi3> -8000fd70: 03050513 addi a0,a0,48 -8000fd74: fea40fa3 sb a0,-1(s0) -8000fd78: 00190913 addi s2,s2,1 -8000fd7c: fff40413 addi s0,s0,-1 -8000fd80: fa0c0ee3 beqz s8,8000fd3c <_svfiprintf_r+0xc90> -8000fd84: 000cc683 lbu a3,0(s9) -8000fd88: fb269ae3 bne a3,s2,8000fd3c <_svfiprintf_r+0xc90> -8000fd8c: 0ff00793 li a5,255 -8000fd90: faf906e3 beq s2,a5,8000fd3c <_svfiprintf_r+0xc90> -8000fd94: 160a1c63 bnez s4,8000ff0c <_svfiprintf_r+0xe60> -8000fd98: 00900793 li a5,9 -8000fd9c: 1737e863 bltu a5,s3,8000ff0c <_svfiprintf_r+0xe60> -8000fda0: 0f010793 addi a5,sp,240 -8000fda4: 01912c23 sw s9,24(sp) -8000fda8: 02412883 lw a7,36(sp) -8000fdac: 02812a03 lw s4,40(sp) -8000fdb0: 02c12983 lw s3,44(sp) -8000fdb4: 40878cb3 sub s9,a5,s0 -8000fdb8: 000d8913 mv s2,s11 -8000fdbc: f5cff06f j 8000f518 <_svfiprintf_r+0x46c> -8000fdc0: 00812703 lw a4,8(sp) -8000fdc4: 41f75793 srai a5,a4,0x1f -8000fdc8: 00e6a023 sw a4,0(a3) -8000fdcc: 00f6a223 sw a5,4(a3) -8000fdd0: b80ff06f j 8000f150 <_svfiprintf_r+0xa4> -8000fdd4: 00d12623 sw a3,12(sp) -8000fdd8: 00072c83 lw s9,0(a4) -8000fddc: 00000c13 li s8,0 -8000fde0: 00100693 li a3,1 -8000fde4: f84ff06f j 8000f568 <_svfiprintf_r+0x4bc> -8000fde8: 01812783 lw a5,24(sp) -8000fdec: 0009c683 lbu a3,0(s3) -8000fdf0: be078863 beqz a5,8000f1e0 <_svfiprintf_r+0x134> -8000fdf4: 0007c783 lbu a5,0(a5) -8000fdf8: be078463 beqz a5,8000f1e0 <_svfiprintf_r+0x134> -8000fdfc: 40096913 ori s2,s2,1024 -8000fe00: be0ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000fe04: 00072c83 lw s9,0(a4) -8000fe08: 00d12623 sw a3,12(sp) -8000fe0c: 41fcdc13 srai s8,s9,0x1f -8000fe10: 000c0693 mv a3,s8 -8000fe14: ec8ff06f j 8000f4dc <_svfiprintf_r+0x430> -8000fe18: 00072c83 lw s9,0(a4) -8000fe1c: 00000c13 li s8,0 -8000fe20: 00d12623 sw a3,12(sp) -8000fe24: f3cff06f j 8000f560 <_svfiprintf_r+0x4b4> -8000fe28: 800157b7 lui a5,0x80015 -8000fe2c: c4078793 addi a5,a5,-960 # 80014c40 <__BSS_END__+0xffffe010> -8000fe30: 00f12a23 sw a5,20(sp) -8000fe34: 02097793 andi a5,s2,32 -8000fe38: 00040893 mv a7,s0 -8000fe3c: 06078c63 beqz a5,8000feb4 <_svfiprintf_r+0xe08> -8000fe40: 00c12783 lw a5,12(sp) -8000fe44: 00778793 addi a5,a5,7 -8000fe48: ff87f793 andi a5,a5,-8 -8000fe4c: 0007ac83 lw s9,0(a5) -8000fe50: 0047ac03 lw s8,4(a5) -8000fe54: 00878793 addi a5,a5,8 -8000fe58: 00f12623 sw a5,12(sp) -8000fe5c: 00197613 andi a2,s2,1 -8000fe60: 00060e63 beqz a2,8000fe7c <_svfiprintf_r+0xdd0> -8000fe64: 018ce633 or a2,s9,s8 -8000fe68: 00060a63 beqz a2,8000fe7c <_svfiprintf_r+0xdd0> -8000fe6c: 03000613 li a2,48 -8000fe70: 02c10e23 sb a2,60(sp) -8000fe74: 02d10ea3 sb a3,61(sp) -8000fe78: 00296913 ori s2,s2,2 -8000fe7c: bff97d93 andi s11,s2,-1025 -8000fe80: 00200693 li a3,2 -8000fe84: ee4ff06f j 8000f568 <_svfiprintf_r+0x4bc> -8000fe88: 00040893 mv a7,s0 -8000fe8c: 00090d93 mv s11,s2 -8000fe90: ff0ff06f j 8000f680 <_svfiprintf_r+0x5d4> -8000fe94: 00040893 mv a7,s0 -8000fe98: ea4ff06f j 8000f53c <_svfiprintf_r+0x490> -8000fe9c: 800157b7 lui a5,0x80015 -8000fea0: c2c78793 addi a5,a5,-980 # 80014c2c <__BSS_END__+0xffffdffc> -8000fea4: 00f12a23 sw a5,20(sp) -8000fea8: 02097793 andi a5,s2,32 -8000feac: 00040893 mv a7,s0 -8000feb0: f80798e3 bnez a5,8000fe40 <_svfiprintf_r+0xd94> -8000feb4: 00c12703 lw a4,12(sp) -8000feb8: 01097793 andi a5,s2,16 -8000febc: 00470613 addi a2,a4,4 -8000fec0: 08078a63 beqz a5,8000ff54 <_svfiprintf_r+0xea8> -8000fec4: 00072c83 lw s9,0(a4) -8000fec8: 00000c13 li s8,0 -8000fecc: 00c12623 sw a2,12(sp) -8000fed0: f8dff06f j 8000fe5c <_svfiprintf_r+0xdb0> -8000fed4: 00040513 mv a0,s0 -8000fed8: ce1f90ef jal ra,80009bb8 -8000fedc: 00050c93 mv s9,a0 -8000fee0: 01b12623 sw s11,12(sp) -8000fee4: 00000893 li a7,0 -8000fee8: e30ff06f j 8000f518 <_svfiprintf_r+0x46c> -8000feec: 04000593 li a1,64 -8000fef0: e01f70ef jal ra,80007cf0 <_malloc_r> -8000fef4: 00aa2023 sw a0,0(s4) -8000fef8: 00aa2823 sw a0,16(s4) -8000fefc: 24050c63 beqz a0,80010154 <_svfiprintf_r+0x10a8> -8000ff00: 04000793 li a5,64 -8000ff04: 00fa2a23 sw a5,20(s4) -8000ff08: a00ff06f j 8000f108 <_svfiprintf_r+0x5c> -8000ff0c: 02012783 lw a5,32(sp) -8000ff10: 01c12583 lw a1,28(sp) -8000ff14: 00000913 li s2,0 -8000ff18: 40f40433 sub s0,s0,a5 -8000ff1c: 00078613 mv a2,a5 -8000ff20: 00040513 mv a0,s0 -8000ff24: d21f90ef jal ra,80009c44 -8000ff28: 001cc583 lbu a1,1(s9) -8000ff2c: 00a00613 li a2,10 -8000ff30: 00000693 li a3,0 -8000ff34: 00b03833 snez a6,a1 -8000ff38: 00098513 mv a0,s3 -8000ff3c: 000a0593 mv a1,s4 -8000ff40: 010c8cb3 add s9,s9,a6 -8000ff44: 4bc000ef jal ra,80010400 <__udivdi3> -8000ff48: e0dff06f j 8000fd54 <_svfiprintf_r+0xca8> -8000ff4c: 00090a13 mv s4,s2 -8000ff50: c24ff06f j 8000f374 <_svfiprintf_r+0x2c8> -8000ff54: 04097793 andi a5,s2,64 -8000ff58: 0a078263 beqz a5,8000fffc <_svfiprintf_r+0xf50> -8000ff5c: 00c12783 lw a5,12(sp) -8000ff60: 00000c13 li s8,0 -8000ff64: 00c12623 sw a2,12(sp) -8000ff68: 0007dc83 lhu s9,0(a5) -8000ff6c: ef1ff06f j 8000fe5c <_svfiprintf_r+0xdb0> -8000ff70: 04010613 addi a2,sp,64 -8000ff74: 000a0593 mv a1,s4 -8000ff78: 000b0513 mv a0,s6 -8000ff7c: 03112223 sw a7,36(sp) -8000ff80: f71fe0ef jal ra,8000eef0 <__ssprint_r> -8000ff84: be051863 bnez a0,8000f374 <_svfiprintf_r+0x2c8> -8000ff88: 04412603 lw a2,68(sp) -8000ff8c: 04812783 lw a5,72(sp) -8000ff90: 02412883 lw a7,36(sp) -8000ff94: 05410693 addi a3,sp,84 -8000ff98: 00160593 addi a1,a2,1 -8000ff9c: 000a8d13 mv s10,s5 -8000ffa0: b68ff06f j 8000f308 <_svfiprintf_r+0x25c> -8000ffa4: 0019c683 lbu a3,1(s3) -8000ffa8: 20096913 ori s2,s2,512 -8000ffac: 00198993 addi s3,s3,1 -8000ffb0: a30ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000ffb4: 0019c683 lbu a3,1(s3) -8000ffb8: 02096913 ori s2,s2,32 -8000ffbc: 00198993 addi s3,s3,1 -8000ffc0: a20ff06f j 8000f1e0 <_svfiprintf_r+0x134> -8000ffc4: 00040a13 mv s4,s0 -8000ffc8: bacff06f j 8000f374 <_svfiprintf_r+0x2c8> -8000ffcc: 00812783 lw a5,8(sp) -8000ffd0: 00f6a023 sw a5,0(a3) -8000ffd4: 97cff06f j 8000f150 <_svfiprintf_r+0xa4> -8000ffd8: 00600793 li a5,6 -8000ffdc: 00088c93 mv s9,a7 -8000ffe0: 0117f463 bgeu a5,a7,8000ffe8 <_svfiprintf_r+0xf3c> -8000ffe4: 00600c93 li s9,6 -8000ffe8: 80015e37 lui t3,0x80015 -8000ffec: 000c8c13 mv s8,s9 -8000fff0: 01b12623 sw s11,12(sp) -8000fff4: c54e0413 addi s0,t3,-940 # 80014c54 <__BSS_END__+0xffffe024> -8000fff8: a58ff06f j 8000f250 <_svfiprintf_r+0x1a4> -8000fffc: 20097793 andi a5,s2,512 -80010000: 0c078663 beqz a5,800100cc <_svfiprintf_r+0x1020> -80010004: 00c12783 lw a5,12(sp) -80010008: 00000c13 li s8,0 -8001000c: 00c12623 sw a2,12(sp) -80010010: 0007cc83 lbu s9,0(a5) -80010014: e49ff06f j 8000fe5c <_svfiprintf_r+0xdb0> -80010018: 20097793 andi a5,s2,512 -8001001c: 08078e63 beqz a5,800100b8 <_svfiprintf_r+0x100c> -80010020: 00c12783 lw a5,12(sp) -80010024: 00000c13 li s8,0 -80010028: 00d12623 sw a3,12(sp) -8001002c: 0007cc83 lbu s9,0(a5) -80010030: d30ff06f j 8000f560 <_svfiprintf_r+0x4b4> -80010034: 20097793 andi a5,s2,512 -80010038: 06078463 beqz a5,800100a0 <_svfiprintf_r+0xff4> -8001003c: 00c12783 lw a5,12(sp) -80010040: 00d12623 sw a3,12(sp) -80010044: 00078c83 lb s9,0(a5) -80010048: 41fcdc13 srai s8,s9,0x1f -8001004c: 000c0693 mv a3,s8 -80010050: c8cff06f j 8000f4dc <_svfiprintf_r+0x430> -80010054: 200df793 andi a5,s11,512 -80010058: 02078863 beqz a5,80010088 <_svfiprintf_r+0xfdc> -8001005c: 00c12783 lw a5,12(sp) -80010060: 00000c13 li s8,0 -80010064: 00d12623 sw a3,12(sp) -80010068: 0007cc83 lbu s9,0(a5) -8001006c: 00100693 li a3,1 -80010070: cf8ff06f j 8000f568 <_svfiprintf_r+0x4bc> -80010074: 00068613 mv a2,a3 -80010078: 931ff06f j 8000f9a8 <_svfiprintf_r+0x8fc> -8001007c: 00900793 li a5,9 -80010080: cd37eae3 bltu a5,s3,8000fd54 <_svfiprintf_r+0xca8> -80010084: d1dff06f j 8000fda0 <_svfiprintf_r+0xcf4> -80010088: 00c12783 lw a5,12(sp) -8001008c: 00000c13 li s8,0 -80010090: 00d12623 sw a3,12(sp) -80010094: 0007ac83 lw s9,0(a5) -80010098: 00100693 li a3,1 -8001009c: cccff06f j 8000f568 <_svfiprintf_r+0x4bc> -800100a0: 00c12783 lw a5,12(sp) -800100a4: 00d12623 sw a3,12(sp) -800100a8: 0007ac83 lw s9,0(a5) -800100ac: 41fcdc13 srai s8,s9,0x1f -800100b0: 000c0693 mv a3,s8 -800100b4: c28ff06f j 8000f4dc <_svfiprintf_r+0x430> -800100b8: 00c12783 lw a5,12(sp) -800100bc: 00000c13 li s8,0 -800100c0: 00d12623 sw a3,12(sp) -800100c4: 0007ac83 lw s9,0(a5) -800100c8: c98ff06f j 8000f560 <_svfiprintf_r+0x4b4> -800100cc: 00c12783 lw a5,12(sp) -800100d0: 00000c13 li s8,0 -800100d4: 00c12623 sw a2,12(sp) -800100d8: 0007ac83 lw s9,0(a5) -800100dc: d81ff06f j 8000fe5c <_svfiprintf_r+0xdb0> -800100e0: 00812783 lw a5,8(sp) -800100e4: 00f69023 sh a5,0(a3) -800100e8: 868ff06f j 8000f150 <_svfiprintf_r+0xa4> -800100ec: 04010613 addi a2,sp,64 -800100f0: 000a0593 mv a1,s4 -800100f4: 000b0513 mv a0,s6 -800100f8: df9fe0ef jal ra,8000eef0 <__ssprint_r> -800100fc: a78ff06f j 8000f374 <_svfiprintf_r+0x2c8> -80010100: 00088c93 mv s9,a7 -80010104: 01b12623 sw s11,12(sp) -80010108: 00000893 li a7,0 -8001010c: c0cff06f j 8000f518 <_svfiprintf_r+0x46c> -80010110: 00090d93 mv s11,s2 -80010114: bf0ff06f j 8000f504 <_svfiprintf_r+0x458> -80010118: 00068513 mv a0,a3 -8001011c: 00058613 mv a2,a1 -80010120: fe4ff06f j 8000f904 <_svfiprintf_r+0x858> -80010124: fff00793 li a5,-1 -80010128: 00f12423 sw a5,8(sp) -8001012c: a54ff06f j 8000f380 <_svfiprintf_r+0x2d4> -80010130: 00c12783 lw a5,12(sp) -80010134: 0007a403 lw s0,0(a5) -80010138: 00478793 addi a5,a5,4 -8001013c: 00045463 bgez s0,80010144 <_svfiprintf_r+0x1098> -80010140: fff00413 li s0,-1 -80010144: 0019c683 lbu a3,1(s3) -80010148: 00f12623 sw a5,12(sp) -8001014c: 00070993 mv s3,a4 -80010150: 890ff06f j 8000f1e0 <_svfiprintf_r+0x134> -80010154: 00c00793 li a5,12 -80010158: 00fb2023 sw a5,0(s6) -8001015c: fff00793 li a5,-1 -80010160: 00f12423 sw a5,8(sp) -80010164: a1cff06f j 8000f380 <_svfiprintf_r+0x2d4> +8000f5fc: 08c88e63 beq a7,a2,8000f698 <_svfiprintf_r+0x560> +8000f600: 018ce633 or a2,s9,s8 +8000f604: f7fdf913 andi s2,s11,-129 +8000f608: 4a061463 bnez a2,8000fab0 <_svfiprintf_r+0x978> +8000f60c: 28089263 bnez a7,8000f890 <_svfiprintf_r+0x758> +8000f610: 6e069a63 bnez a3,8000fd04 <_svfiprintf_r+0xbcc> +8000f614: 001dfc93 andi s9,s11,1 +8000f618: 0f010413 addi s0,sp,240 +8000f61c: f80c84e3 beqz s9,8000f5a4 <_svfiprintf_r+0x46c> +8000f620: 03000793 li a5,48 +8000f624: 0ef107a3 sb a5,239(sp) +8000f628: 0ef10413 addi s0,sp,239 +8000f62c: f79ff06f j 8000f5a4 <_svfiprintf_r+0x46c> +8000f630: 01096913 ori s2,s2,16 +8000f634: 02097793 andi a5,s2,32 +8000f638: 00040893 mv a7,s0 +8000f63c: f00796e3 bnez a5,8000f548 <_svfiprintf_r+0x410> +8000f640: 00c12703 lw a4,12(sp) +8000f644: 01097793 andi a5,s2,16 +8000f648: 00470693 addi a3,a4,4 +8000f64c: 040792e3 bnez a5,8000fe90 <_svfiprintf_r+0xd58> +8000f650: 04097793 andi a5,s2,64 +8000f654: 260786e3 beqz a5,800100c0 <_svfiprintf_r+0xf88> +8000f658: 00c12783 lw a5,12(sp) +8000f65c: 00d12623 sw a3,12(sp) +8000f660: 00079c83 lh s9,0(a5) +8000f664: 41fcdc13 srai s8,s9,0x1f +8000f668: 000c0693 mv a3,s8 +8000f66c: f006d0e3 bgez a3,8000f56c <_svfiprintf_r+0x434> +8000f670: 019036b3 snez a3,s9 +8000f674: 41800eb3 neg t4,s8 +8000f678: 40de8c33 sub s8,t4,a3 +8000f67c: 02d00693 li a3,45 +8000f680: 02d10da3 sb a3,59(sp) +8000f684: fff00613 li a2,-1 +8000f688: 41900cb3 neg s9,s9 +8000f68c: 00090d93 mv s11,s2 +8000f690: 00100693 li a3,1 +8000f694: f6c896e3 bne a7,a2,8000f600 <_svfiprintf_r+0x4c8> +8000f698: 00100613 li a2,1 +8000f69c: eec684e3 beq a3,a2,8000f584 <_svfiprintf_r+0x44c> +8000f6a0: 00200613 li a2,2 +8000f6a4: 20c68063 beq a3,a2,8000f8a4 <_svfiprintf_r+0x76c> +8000f6a8: 0f010413 addi s0,sp,240 +8000f6ac: 01dc1793 slli a5,s8,0x1d +8000f6b0: 007cf693 andi a3,s9,7 +8000f6b4: 003cdc93 srli s9,s9,0x3 +8000f6b8: 03068693 addi a3,a3,48 +8000f6bc: 0197ecb3 or s9,a5,s9 +8000f6c0: 003c5c13 srli s8,s8,0x3 +8000f6c4: fed40fa3 sb a3,-1(s0) +8000f6c8: 018ce7b3 or a5,s9,s8 +8000f6cc: 00040593 mv a1,s0 +8000f6d0: fff40413 addi s0,s0,-1 +8000f6d4: fc079ce3 bnez a5,8000f6ac <_svfiprintf_r+0x574> +8000f6d8: 001df793 andi a5,s11,1 +8000f6dc: 1e078e63 beqz a5,8000f8d8 <_svfiprintf_r+0x7a0> +8000f6e0: 03000793 li a5,48 +8000f6e4: 1ef68a63 beq a3,a5,8000f8d8 <_svfiprintf_r+0x7a0> +8000f6e8: ffe58593 addi a1,a1,-2 +8000f6ec: fef40fa3 sb a5,-1(s0) +8000f6f0: 0f010793 addi a5,sp,240 +8000f6f4: 40b78cb3 sub s9,a5,a1 +8000f6f8: 000d8913 mv s2,s11 +8000f6fc: 00058413 mv s0,a1 +8000f700: ea5ff06f j 8000f5a4 <_svfiprintf_r+0x46c> +8000f704: 00040893 mv a7,s0 +8000f708: 01096d93 ori s11,s2,16 +8000f70c: 020df793 andi a5,s11,32 +8000f710: 62078863 beqz a5,8000fd40 <_svfiprintf_r+0xc08> +8000f714: 00c12783 lw a5,12(sp) +8000f718: 00100693 li a3,1 +8000f71c: 00778913 addi s2,a5,7 +8000f720: ff897913 andi s2,s2,-8 +8000f724: 00890793 addi a5,s2,8 +8000f728: 00092c83 lw s9,0(s2) +8000f72c: 00492c03 lw s8,4(s2) +8000f730: 00f12623 sw a5,12(sp) +8000f734: ec1ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> +8000f738: 00c12783 lw a5,12(sp) +8000f73c: ffff86b7 lui a3,0xffff8 +8000f740: 8306c693 xori a3,a3,-2000 +8000f744: 0007ac83 lw s9,0(a5) +8000f748: 00478793 addi a5,a5,4 +8000f74c: 00f12623 sw a5,12(sp) +8000f750: 800157b7 lui a5,0x80015 +8000f754: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +8000f758: 02d11e23 sh a3,60(sp) +8000f75c: 00040893 mv a7,s0 +8000f760: 00000c13 li s8,0 +8000f764: 00296d93 ori s11,s2,2 +8000f768: 00f12a23 sw a5,20(sp) +8000f76c: 00200693 li a3,2 +8000f770: e85ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> +8000f774: 0009c683 lbu a3,0(s3) +8000f778: 08096913 ori s2,s2,128 +8000f77c: af1ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f780: 0009c683 lbu a3,0(s3) +8000f784: 00198713 addi a4,s3,1 +8000f788: 22b68ae3 beq a3,a1,800101bc <_svfiprintf_r+0x1084> +8000f78c: fd068793 addi a5,a3,-48 # ffff7fd0 <__BSS_END__+0x7ffe1394> +8000f790: 00070993 mv s3,a4 +8000f794: 00000413 li s0,0 +8000f798: acfcece3 bltu s9,a5,8000f270 <_svfiprintf_r+0x138> +8000f79c: 0009c683 lbu a3,0(s3) +8000f7a0: 00241713 slli a4,s0,0x2 +8000f7a4: 008708b3 add a7,a4,s0 +8000f7a8: 00189893 slli a7,a7,0x1 +8000f7ac: 00f88433 add s0,a7,a5 +8000f7b0: fd068793 addi a5,a3,-48 +8000f7b4: 00198993 addi s3,s3,1 +8000f7b8: fefcf2e3 bgeu s9,a5,8000f79c <_svfiprintf_r+0x664> +8000f7bc: ab5ff06f j 8000f270 <_svfiprintf_r+0x138> +8000f7c0: 0009c683 lbu a3,0(s3) +8000f7c4: 00496913 ori s2,s2,4 +8000f7c8: aa5ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f7cc: 02b00793 li a5,43 +8000f7d0: 0009c683 lbu a3,0(s3) +8000f7d4: 02f10da3 sb a5,59(sp) +8000f7d8: a95ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f7dc: 00c12703 lw a4,12(sp) +8000f7e0: 0009c683 lbu a3,0(s3) +8000f7e4: 00072783 lw a5,0(a4) +8000f7e8: 00470713 addi a4,a4,4 +8000f7ec: 00e12623 sw a4,12(sp) +8000f7f0: 00f12223 sw a5,4(sp) +8000f7f4: a607dce3 bgez a5,8000f26c <_svfiprintf_r+0x134> +8000f7f8: 40f007b3 neg a5,a5 +8000f7fc: 00f12223 sw a5,4(sp) +8000f800: 00496913 ori s2,s2,4 +8000f804: a69ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f808: 0009c683 lbu a3,0(s3) +8000f80c: 00196913 ori s2,s2,1 +8000f810: a5dff06f j 8000f26c <_svfiprintf_r+0x134> +8000f814: 03b14783 lbu a5,59(sp) +8000f818: 0009c683 lbu a3,0(s3) +8000f81c: a40798e3 bnez a5,8000f26c <_svfiprintf_r+0x134> +8000f820: 02000793 li a5,32 +8000f824: 02f10da3 sb a5,59(sp) +8000f828: a45ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f82c: 0009c683 lbu a3,0(s3) +8000f830: 06800793 li a5,104 +8000f834: 7ef68e63 beq a3,a5,80010030 <_svfiprintf_r+0xef8> +8000f838: 04096913 ori s2,s2,64 +8000f83c: a31ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f840: 00c12703 lw a4,12(sp) +8000f844: 02097793 andi a5,s2,32 +8000f848: 00072683 lw a3,0(a4) +8000f84c: 00470713 addi a4,a4,4 +8000f850: 00e12623 sw a4,12(sp) +8000f854: 5e079c63 bnez a5,8000fe4c <_svfiprintf_r+0xd14> +8000f858: 01097793 andi a5,s2,16 +8000f85c: 7e079e63 bnez a5,80010058 <_svfiprintf_r+0xf20> +8000f860: 04097793 andi a5,s2,64 +8000f864: 100794e3 bnez a5,8001016c <_svfiprintf_r+0x1034> +8000f868: 20097313 andi t1,s2,512 +8000f86c: 7e030663 beqz t1,80010058 <_svfiprintf_r+0xf20> +8000f870: 00812783 lw a5,8(sp) +8000f874: 00f68023 sb a5,0(a3) +8000f878: 965ff06f j 8000f1dc <_svfiprintf_r+0xa4> +8000f87c: 0009c683 lbu a3,0(s3) +8000f880: 06c00793 li a5,108 +8000f884: 7af68e63 beq a3,a5,80010040 <_svfiprintf_r+0xf08> +8000f888: 01096913 ori s2,s2,16 +8000f88c: 9e1ff06f j 8000f26c <_svfiprintf_r+0x134> +8000f890: 00100613 li a2,1 +8000f894: 10c684e3 beq a3,a2,8001019c <_svfiprintf_r+0x1064> +8000f898: 00200613 li a2,2 +8000f89c: 00090d93 mv s11,s2 +8000f8a0: e0c694e3 bne a3,a2,8000f6a8 <_svfiprintf_r+0x570> +8000f8a4: 01412683 lw a3,20(sp) +8000f8a8: 0f010413 addi s0,sp,240 +8000f8ac: 00fcf793 andi a5,s9,15 +8000f8b0: 00f687b3 add a5,a3,a5 +8000f8b4: 0007c703 lbu a4,0(a5) +8000f8b8: 004cdc93 srli s9,s9,0x4 +8000f8bc: 01cc1793 slli a5,s8,0x1c +8000f8c0: 0197ecb3 or s9,a5,s9 +8000f8c4: 004c5c13 srli s8,s8,0x4 +8000f8c8: fee40fa3 sb a4,-1(s0) +8000f8cc: 018ce7b3 or a5,s9,s8 +8000f8d0: fff40413 addi s0,s0,-1 +8000f8d4: fc079ce3 bnez a5,8000f8ac <_svfiprintf_r+0x774> +8000f8d8: 0f010793 addi a5,sp,240 +8000f8dc: 40878cb3 sub s9,a5,s0 +8000f8e0: 000d8913 mv s2,s11 +8000f8e4: cc1ff06f j 8000f5a4 <_svfiprintf_r+0x46c> +8000f8e8: 00412703 lw a4,4(sp) +8000f8ec: 41870db3 sub s11,a4,s8 +8000f8f0: abb052e3 blez s11,8000f394 <_svfiprintf_r+0x25c> +8000f8f4: 01000513 li a0,16 +8000f8f8: 0bb556e3 bge a0,s11,800101a4 <_svfiprintf_r+0x106c> +8000f8fc: 02812223 sw s0,36(sp) +8000f900: 01000693 li a3,16 +8000f904: 000a0413 mv s0,s4 +8000f908: 00700e93 li t4,7 +8000f90c: 000d8a13 mv s4,s11 +8000f910: 00098d93 mv s11,s3 +8000f914: 00088993 mv s3,a7 +8000f918: 00c0006f j 8000f924 <_svfiprintf_r+0x7ec> +8000f91c: ff0a0a13 addi s4,s4,-16 +8000f920: 0546da63 bge a3,s4,8000f974 <_svfiprintf_r+0x83c> +8000f924: 01078793 addi a5,a5,16 +8000f928: 00160613 addi a2,a2,1 +8000f92c: 009d2023 sw s1,0(s10) +8000f930: 00dd2223 sw a3,4(s10) +8000f934: 04f12423 sw a5,72(sp) +8000f938: 04c12223 sw a2,68(sp) +8000f93c: 008d0d13 addi s10,s10,8 +8000f940: fccedee3 bge t4,a2,8000f91c <_svfiprintf_r+0x7e4> +8000f944: 04010613 addi a2,sp,64 +8000f948: 00040593 mv a1,s0 +8000f94c: 000b0513 mv a0,s6 +8000f950: e2cff0ef jal ra,8000ef7c <__ssprint_r> +8000f954: 6e051e63 bnez a0,80010050 <_svfiprintf_r+0xf18> +8000f958: 01000693 li a3,16 +8000f95c: ff0a0a13 addi s4,s4,-16 +8000f960: 04812783 lw a5,72(sp) +8000f964: 04412603 lw a2,68(sp) +8000f968: 000a8d13 mv s10,s5 +8000f96c: 00700e93 li t4,7 +8000f970: fb46cae3 blt a3,s4,8000f924 <_svfiprintf_r+0x7ec> +8000f974: 00098893 mv a7,s3 +8000f978: 000d8993 mv s3,s11 +8000f97c: 000a0d93 mv s11,s4 +8000f980: 00040a13 mv s4,s0 +8000f984: 02412403 lw s0,36(sp) +8000f988: 00160613 addi a2,a2,1 +8000f98c: 008d0513 addi a0,s10,8 +8000f990: 01b787b3 add a5,a5,s11 +8000f994: 009d2023 sw s1,0(s10) +8000f998: 01bd2223 sw s11,4(s10) +8000f99c: 04f12423 sw a5,72(sp) +8000f9a0: 04c12223 sw a2,68(sp) +8000f9a4: 00700713 li a4,7 +8000f9a8: 64c74a63 blt a4,a2,8000fffc <_svfiprintf_r+0xec4> +8000f9ac: 41988db3 sub s11,a7,s9 +8000f9b0: 00160593 addi a1,a2,1 +8000f9b4: 00850693 addi a3,a0,8 +8000f9b8: 00050d13 mv s10,a0 +8000f9bc: 9fb050e3 blez s11,8000f39c <_svfiprintf_r+0x264> +8000f9c0: 01000513 li a0,16 +8000f9c4: 73b55e63 bge a0,s11,80010100 <_svfiprintf_r+0xfc8> +8000f9c8: 01000693 li a3,16 +8000f9cc: 00700893 li a7,7 +8000f9d0: 00c0006f j 8000f9dc <_svfiprintf_r+0x8a4> +8000f9d4: ff0d8d93 addi s11,s11,-16 +8000f9d8: 05b6da63 bge a3,s11,8000fa2c <_svfiprintf_r+0x8f4> +8000f9dc: 01078793 addi a5,a5,16 +8000f9e0: 00160613 addi a2,a2,1 +8000f9e4: 009d2023 sw s1,0(s10) +8000f9e8: 00dd2223 sw a3,4(s10) +8000f9ec: 04f12423 sw a5,72(sp) +8000f9f0: 04c12223 sw a2,68(sp) +8000f9f4: 008d0d13 addi s10,s10,8 +8000f9f8: fcc8dee3 bge a7,a2,8000f9d4 <_svfiprintf_r+0x89c> +8000f9fc: 04010613 addi a2,sp,64 +8000fa00: 000a0593 mv a1,s4 +8000fa04: 000b0513 mv a0,s6 +8000fa08: d74ff0ef jal ra,8000ef7c <__ssprint_r> +8000fa0c: 9e051ae3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000fa10: 01000693 li a3,16 +8000fa14: ff0d8d93 addi s11,s11,-16 +8000fa18: 04812783 lw a5,72(sp) +8000fa1c: 04412603 lw a2,68(sp) +8000fa20: 000a8d13 mv s10,s5 +8000fa24: 00700893 li a7,7 +8000fa28: fbb6cae3 blt a3,s11,8000f9dc <_svfiprintf_r+0x8a4> +8000fa2c: 00160593 addi a1,a2,1 +8000fa30: 008d0613 addi a2,s10,8 +8000fa34: 01b787b3 add a5,a5,s11 +8000fa38: 009d2023 sw s1,0(s10) +8000fa3c: 01bd2223 sw s11,4(s10) +8000fa40: 04f12423 sw a5,72(sp) +8000fa44: 04b12223 sw a1,68(sp) +8000fa48: 00700713 li a4,7 +8000fa4c: 32b74263 blt a4,a1,8000fd70 <_svfiprintf_r+0xc38> +8000fa50: 00060d13 mv s10,a2 +8000fa54: 00158593 addi a1,a1,1 +8000fa58: 00fc87b3 add a5,s9,a5 +8000fa5c: 008d2023 sw s0,0(s10) +8000fa60: 019d2223 sw s9,4(s10) +8000fa64: 04f12423 sw a5,72(sp) +8000fa68: 04b12223 sw a1,68(sp) +8000fa6c: 00700713 li a4,7 +8000fa70: 00860693 addi a3,a2,8 +8000fa74: 94b752e3 bge a4,a1,8000f3b8 <_svfiprintf_r+0x280> +8000fa78: 04010613 addi a2,sp,64 +8000fa7c: 000a0593 mv a1,s4 +8000fa80: 000b0513 mv a0,s6 +8000fa84: cf8ff0ef jal ra,8000ef7c <__ssprint_r> +8000fa88: 96051ce3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000fa8c: 04812783 lw a5,72(sp) +8000fa90: 000a8693 mv a3,s5 +8000fa94: 925ff06f j 8000f3b8 <_svfiprintf_r+0x280> +8000fa98: 04010613 addi a2,sp,64 +8000fa9c: 000a0593 mv a1,s4 +8000faa0: 000b0513 mv a0,s6 +8000faa4: cd8ff0ef jal ra,8000ef7c <__ssprint_r> +8000faa8: 940500e3 beqz a0,8000f3e8 <_svfiprintf_r+0x2b0> +8000faac: 955ff06f j 8000f400 <_svfiprintf_r+0x2c8> +8000fab0: 00090d93 mv s11,s2 +8000fab4: be5ff06f j 8000f698 <_svfiprintf_r+0x560> +8000fab8: 01000693 li a3,16 +8000fabc: 0bb6de63 bge a3,s11,8000fb78 <_svfiprintf_r+0xa40> +8000fac0: 000d0713 mv a4,s10 +8000fac4: 00700f93 li t6,7 +8000fac8: 000c0d13 mv s10,s8 +8000facc: 03e12223 sw t5,36(sp) +8000fad0: 00090c13 mv s8,s2 +8000fad4: 03d12423 sw t4,40(sp) +8000fad8: 000a0913 mv s2,s4 +8000fadc: 00098a13 mv s4,s3 +8000fae0: 00040993 mv s3,s0 +8000fae4: 000d8413 mv s0,s11 +8000fae8: 000c8d93 mv s11,s9 +8000faec: 00088c93 mv s9,a7 +8000faf0: 00c0006f j 8000fafc <_svfiprintf_r+0x9c4> +8000faf4: ff040413 addi s0,s0,-16 +8000faf8: 0486da63 bge a3,s0,8000fb4c <_svfiprintf_r+0xa14> +8000fafc: 01078793 addi a5,a5,16 +8000fb00: 00160613 addi a2,a2,1 +8000fb04: 01772023 sw s7,0(a4) +8000fb08: 00d72223 sw a3,4(a4) +8000fb0c: 04f12423 sw a5,72(sp) +8000fb10: 04c12223 sw a2,68(sp) +8000fb14: 00870713 addi a4,a4,8 +8000fb18: fccfdee3 bge t6,a2,8000faf4 <_svfiprintf_r+0x9bc> +8000fb1c: 04010613 addi a2,sp,64 +8000fb20: 00090593 mv a1,s2 +8000fb24: 000b0513 mv a0,s6 +8000fb28: c54ff0ef jal ra,8000ef7c <__ssprint_r> +8000fb2c: 4a051663 bnez a0,8000ffd8 <_svfiprintf_r+0xea0> +8000fb30: 01000693 li a3,16 +8000fb34: ff040413 addi s0,s0,-16 +8000fb38: 04812783 lw a5,72(sp) +8000fb3c: 04412603 lw a2,68(sp) +8000fb40: 000a8713 mv a4,s5 +8000fb44: 00700f93 li t6,7 +8000fb48: fa86cae3 blt a3,s0,8000fafc <_svfiprintf_r+0x9c4> +8000fb4c: 02412f03 lw t5,36(sp) +8000fb50: 02812e83 lw t4,40(sp) +8000fb54: 000c8893 mv a7,s9 +8000fb58: 000d8c93 mv s9,s11 +8000fb5c: 00040d93 mv s11,s0 +8000fb60: 00098413 mv s0,s3 +8000fb64: 000a0993 mv s3,s4 +8000fb68: 00090a13 mv s4,s2 +8000fb6c: 000c0913 mv s2,s8 +8000fb70: 000d0c13 mv s8,s10 +8000fb74: 00070d13 mv s10,a4 +8000fb78: 01b787b3 add a5,a5,s11 +8000fb7c: 00160613 addi a2,a2,1 +8000fb80: 017d2023 sw s7,0(s10) +8000fb84: 01bd2223 sw s11,4(s10) +8000fb88: 04f12423 sw a5,72(sp) +8000fb8c: 04c12223 sw a2,68(sp) +8000fb90: 00700693 li a3,7 +8000fb94: 008d0d13 addi s10,s10,8 +8000fb98: f6c6d863 bge a3,a2,8000f308 <_svfiprintf_r+0x1d0> +8000fb9c: 04010613 addi a2,sp,64 +8000fba0: 000a0593 mv a1,s4 +8000fba4: 000b0513 mv a0,s6 +8000fba8: 03112623 sw a7,44(sp) +8000fbac: 03d12423 sw t4,40(sp) +8000fbb0: 03e12223 sw t5,36(sp) +8000fbb4: bc8ff0ef jal ra,8000ef7c <__ssprint_r> +8000fbb8: 840514e3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000fbbc: 04812783 lw a5,72(sp) +8000fbc0: 04412603 lw a2,68(sp) +8000fbc4: 02c12883 lw a7,44(sp) +8000fbc8: 02812e83 lw t4,40(sp) +8000fbcc: 02412f03 lw t5,36(sp) +8000fbd0: 000a8d13 mv s10,s5 +8000fbd4: f34ff06f j 8000f308 <_svfiprintf_r+0x1d0> +8000fbd8: 04010613 addi a2,sp,64 +8000fbdc: 000a0593 mv a1,s4 +8000fbe0: 000b0513 mv a0,s6 +8000fbe4: 03112623 sw a7,44(sp) +8000fbe8: 03d12423 sw t4,40(sp) +8000fbec: 03e12223 sw t5,36(sp) +8000fbf0: b8cff0ef jal ra,8000ef7c <__ssprint_r> +8000fbf4: 800516e3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000fbf8: 04412603 lw a2,68(sp) +8000fbfc: 04812783 lw a5,72(sp) +8000fc00: 02c12883 lw a7,44(sp) +8000fc04: 02812e83 lw t4,40(sp) +8000fc08: 02412f03 lw t5,36(sp) +8000fc0c: 05410693 addi a3,sp,84 +8000fc10: 00160593 addi a1,a2,1 +8000fc14: 000a8d13 mv s10,s5 +8000fc18: f3cff06f j 8000f354 <_svfiprintf_r+0x21c> +8000fc1c: 04010613 addi a2,sp,64 +8000fc20: 000a0593 mv a1,s4 +8000fc24: 000b0513 mv a0,s6 +8000fc28: 03112423 sw a7,40(sp) +8000fc2c: 03d12223 sw t4,36(sp) +8000fc30: b4cff0ef jal ra,8000ef7c <__ssprint_r> +8000fc34: fc051663 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000fc38: 04412603 lw a2,68(sp) +8000fc3c: 04812783 lw a5,72(sp) +8000fc40: 02812883 lw a7,40(sp) +8000fc44: 02412e83 lw t4,36(sp) +8000fc48: 05410693 addi a3,sp,84 +8000fc4c: 00160593 addi a1,a2,1 +8000fc50: 000a8d13 mv s10,s5 +8000fc54: f38ff06f j 8000f38c <_svfiprintf_r+0x254> +8000fc58: 01000613 li a2,16 +8000fc5c: 04412703 lw a4,68(sp) +8000fc60: 07965063 bge a2,s9,8000fcc0 <_svfiprintf_r+0xb88> +8000fc64: 01000d93 li s11,16 +8000fc68: 00700413 li s0,7 +8000fc6c: 00c0006f j 8000fc78 <_svfiprintf_r+0xb40> +8000fc70: ff0c8c93 addi s9,s9,-16 +8000fc74: 059dd663 bge s11,s9,8000fcc0 <_svfiprintf_r+0xb88> +8000fc78: 01078793 addi a5,a5,16 +8000fc7c: 00170713 addi a4,a4,1 +8000fc80: 0176a023 sw s7,0(a3) +8000fc84: 01b6a223 sw s11,4(a3) +8000fc88: 04f12423 sw a5,72(sp) +8000fc8c: 04e12223 sw a4,68(sp) +8000fc90: 00868693 addi a3,a3,8 +8000fc94: fce45ee3 bge s0,a4,8000fc70 <_svfiprintf_r+0xb38> +8000fc98: 04010613 addi a2,sp,64 +8000fc9c: 000a0593 mv a1,s4 +8000fca0: 000b0513 mv a0,s6 +8000fca4: ad8ff0ef jal ra,8000ef7c <__ssprint_r> +8000fca8: f4051c63 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000fcac: ff0c8c93 addi s9,s9,-16 +8000fcb0: 04812783 lw a5,72(sp) +8000fcb4: 04412703 lw a4,68(sp) +8000fcb8: 000a8693 mv a3,s5 +8000fcbc: fb9dcee3 blt s11,s9,8000fc78 <_svfiprintf_r+0xb40> +8000fcc0: 019787b3 add a5,a5,s9 +8000fcc4: 00170713 addi a4,a4,1 +8000fcc8: 0176a023 sw s7,0(a3) +8000fccc: 0196a223 sw s9,4(a3) +8000fcd0: 04f12423 sw a5,72(sp) +8000fcd4: 04e12223 sw a4,68(sp) +8000fcd8: 00700693 li a3,7 +8000fcdc: eee6d863 bge a3,a4,8000f3cc <_svfiprintf_r+0x294> +8000fce0: 04010613 addi a2,sp,64 +8000fce4: 000a0593 mv a1,s4 +8000fce8: 000b0513 mv a0,s6 +8000fcec: a90ff0ef jal ra,8000ef7c <__ssprint_r> +8000fcf0: f0051863 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000fcf4: 04812783 lw a5,72(sp) +8000fcf8: ed4ff06f j 8000f3cc <_svfiprintf_r+0x294> +8000fcfc: 88089ae3 bnez a7,8000f590 <_svfiprintf_r+0x458> +8000fd00: 000d8913 mv s2,s11 +8000fd04: 00000893 li a7,0 +8000fd08: 00000c93 li s9,0 +8000fd0c: 0f010413 addi s0,sp,240 +8000fd10: 895ff06f j 8000f5a4 <_svfiprintf_r+0x46c> +8000fd14: 00c12703 lw a4,12(sp) +8000fd18: 01097793 andi a5,s2,16 +8000fd1c: 00470693 addi a3,a4,4 +8000fd20: 18079263 bnez a5,8000fea4 <_svfiprintf_r+0xd6c> +8000fd24: 04097793 andi a5,s2,64 +8000fd28: 36078e63 beqz a5,800100a4 <_svfiprintf_r+0xf6c> +8000fd2c: 00c12783 lw a5,12(sp) +8000fd30: 00000c13 li s8,0 +8000fd34: 00d12623 sw a3,12(sp) +8000fd38: 0007dc83 lhu s9,0(a5) +8000fd3c: 8b1ff06f j 8000f5ec <_svfiprintf_r+0x4b4> +8000fd40: 00c12703 lw a4,12(sp) +8000fd44: 010df793 andi a5,s11,16 +8000fd48: 00470693 addi a3,a4,4 +8000fd4c: 10079a63 bnez a5,8000fe60 <_svfiprintf_r+0xd28> +8000fd50: 040df793 andi a5,s11,64 +8000fd54: 38078663 beqz a5,800100e0 <_svfiprintf_r+0xfa8> +8000fd58: 00c12783 lw a5,12(sp) +8000fd5c: 00000c13 li s8,0 +8000fd60: 00d12623 sw a3,12(sp) +8000fd64: 0007dc83 lhu s9,0(a5) +8000fd68: 00100693 li a3,1 +8000fd6c: 889ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> +8000fd70: 04010613 addi a2,sp,64 +8000fd74: 000a0593 mv a1,s4 +8000fd78: 000b0513 mv a0,s6 +8000fd7c: a00ff0ef jal ra,8000ef7c <__ssprint_r> +8000fd80: e8051063 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +8000fd84: 04412583 lw a1,68(sp) +8000fd88: 04812783 lw a5,72(sp) +8000fd8c: 05410693 addi a3,sp,84 +8000fd90: 00158593 addi a1,a1,1 +8000fd94: 000a8d13 mv s10,s5 +8000fd98: e04ff06f j 8000f39c <_svfiprintf_r+0x264> +8000fd9c: 400df793 andi a5,s11,1024 +8000fda0: 03412423 sw s4,40(sp) +8000fda4: 03312623 sw s3,44(sp) +8000fda8: 000c0a13 mv s4,s8 +8000fdac: 000c8993 mv s3,s9 +8000fdb0: 00000913 li s2,0 +8000fdb4: 01812c83 lw s9,24(sp) +8000fdb8: 0f010413 addi s0,sp,240 +8000fdbc: 03112223 sw a7,36(sp) +8000fdc0: 00078c13 mv s8,a5 +8000fdc4: 0240006f j 8000fde8 <_svfiprintf_r+0xcb0> +8000fdc8: 00a00613 li a2,10 +8000fdcc: 00000693 li a3,0 +8000fdd0: 00098513 mv a0,s3 +8000fdd4: 000a0593 mv a1,s4 +8000fdd8: 6ec000ef jal ra,800104c4 <__udivdi3> +8000fddc: 320a0663 beqz s4,80010108 <_svfiprintf_r+0xfd0> +8000fde0: 00050993 mv s3,a0 +8000fde4: 00058a13 mv s4,a1 +8000fde8: 00a00613 li a2,10 +8000fdec: 00000693 li a3,0 +8000fdf0: 00098513 mv a0,s3 +8000fdf4: 000a0593 mv a1,s4 +8000fdf8: 301000ef jal ra,800108f8 <__umoddi3> +8000fdfc: 03050513 addi a0,a0,48 +8000fe00: fea40fa3 sb a0,-1(s0) +8000fe04: 00190913 addi s2,s2,1 +8000fe08: fff40413 addi s0,s0,-1 +8000fe0c: fa0c0ee3 beqz s8,8000fdc8 <_svfiprintf_r+0xc90> +8000fe10: 000cc683 lbu a3,0(s9) +8000fe14: fb269ae3 bne a3,s2,8000fdc8 <_svfiprintf_r+0xc90> +8000fe18: 0ff00793 li a5,255 +8000fe1c: faf906e3 beq s2,a5,8000fdc8 <_svfiprintf_r+0xc90> +8000fe20: 160a1c63 bnez s4,8000ff98 <_svfiprintf_r+0xe60> +8000fe24: 00900793 li a5,9 +8000fe28: 1737e863 bltu a5,s3,8000ff98 <_svfiprintf_r+0xe60> +8000fe2c: 0f010793 addi a5,sp,240 +8000fe30: 01912c23 sw s9,24(sp) +8000fe34: 02412883 lw a7,36(sp) +8000fe38: 02812a03 lw s4,40(sp) +8000fe3c: 02c12983 lw s3,44(sp) +8000fe40: 40878cb3 sub s9,a5,s0 +8000fe44: 000d8913 mv s2,s11 +8000fe48: f5cff06f j 8000f5a4 <_svfiprintf_r+0x46c> +8000fe4c: 00812703 lw a4,8(sp) +8000fe50: 41f75793 srai a5,a4,0x1f +8000fe54: 00e6a023 sw a4,0(a3) +8000fe58: 00f6a223 sw a5,4(a3) +8000fe5c: b80ff06f j 8000f1dc <_svfiprintf_r+0xa4> +8000fe60: 00d12623 sw a3,12(sp) +8000fe64: 00072c83 lw s9,0(a4) +8000fe68: 00000c13 li s8,0 +8000fe6c: 00100693 li a3,1 +8000fe70: f84ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> +8000fe74: 01812783 lw a5,24(sp) +8000fe78: 0009c683 lbu a3,0(s3) +8000fe7c: be078863 beqz a5,8000f26c <_svfiprintf_r+0x134> +8000fe80: 0007c783 lbu a5,0(a5) +8000fe84: be078463 beqz a5,8000f26c <_svfiprintf_r+0x134> +8000fe88: 40096913 ori s2,s2,1024 +8000fe8c: be0ff06f j 8000f26c <_svfiprintf_r+0x134> +8000fe90: 00072c83 lw s9,0(a4) +8000fe94: 00d12623 sw a3,12(sp) +8000fe98: 41fcdc13 srai s8,s9,0x1f +8000fe9c: 000c0693 mv a3,s8 +8000fea0: ec8ff06f j 8000f568 <_svfiprintf_r+0x430> +8000fea4: 00072c83 lw s9,0(a4) +8000fea8: 00000c13 li s8,0 +8000feac: 00d12623 sw a3,12(sp) +8000feb0: f3cff06f j 8000f5ec <_svfiprintf_r+0x4b4> +8000feb4: 800157b7 lui a5,0x80015 +8000feb8: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> +8000febc: 00f12a23 sw a5,20(sp) +8000fec0: 02097793 andi a5,s2,32 +8000fec4: 00040893 mv a7,s0 +8000fec8: 06078c63 beqz a5,8000ff40 <_svfiprintf_r+0xe08> +8000fecc: 00c12783 lw a5,12(sp) +8000fed0: 00778793 addi a5,a5,7 +8000fed4: ff87f793 andi a5,a5,-8 +8000fed8: 0007ac83 lw s9,0(a5) +8000fedc: 0047ac03 lw s8,4(a5) +8000fee0: 00878793 addi a5,a5,8 +8000fee4: 00f12623 sw a5,12(sp) +8000fee8: 00197613 andi a2,s2,1 +8000feec: 00060e63 beqz a2,8000ff08 <_svfiprintf_r+0xdd0> +8000fef0: 018ce633 or a2,s9,s8 +8000fef4: 00060a63 beqz a2,8000ff08 <_svfiprintf_r+0xdd0> +8000fef8: 03000613 li a2,48 +8000fefc: 02c10e23 sb a2,60(sp) +8000ff00: 02d10ea3 sb a3,61(sp) +8000ff04: 00296913 ori s2,s2,2 +8000ff08: bff97d93 andi s11,s2,-1025 +8000ff0c: 00200693 li a3,2 +8000ff10: ee4ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> +8000ff14: 00040893 mv a7,s0 +8000ff18: 00090d93 mv s11,s2 +8000ff1c: ff0ff06f j 8000f70c <_svfiprintf_r+0x5d4> +8000ff20: 00040893 mv a7,s0 +8000ff24: ea4ff06f j 8000f5c8 <_svfiprintf_r+0x490> +8000ff28: 800157b7 lui a5,0x80015 +8000ff2c: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> +8000ff30: 00f12a23 sw a5,20(sp) +8000ff34: 02097793 andi a5,s2,32 +8000ff38: 00040893 mv a7,s0 +8000ff3c: f80798e3 bnez a5,8000fecc <_svfiprintf_r+0xd94> +8000ff40: 00c12703 lw a4,12(sp) +8000ff44: 01097793 andi a5,s2,16 +8000ff48: 00470613 addi a2,a4,4 +8000ff4c: 08078a63 beqz a5,8000ffe0 <_svfiprintf_r+0xea8> +8000ff50: 00072c83 lw s9,0(a4) +8000ff54: 00000c13 li s8,0 +8000ff58: 00c12623 sw a2,12(sp) +8000ff5c: f8dff06f j 8000fee8 <_svfiprintf_r+0xdb0> +8000ff60: 00040513 mv a0,s0 +8000ff64: 9fdf90ef jal ra,80009960 +8000ff68: 00050c93 mv s9,a0 +8000ff6c: 01b12623 sw s11,12(sp) +8000ff70: 00000893 li a7,0 +8000ff74: e30ff06f j 8000f5a4 <_svfiprintf_r+0x46c> +8000ff78: 04000593 li a1,64 +8000ff7c: c2df70ef jal ra,80007ba8 <_malloc_r> +8000ff80: 00aa2023 sw a0,0(s4) +8000ff84: 00aa2823 sw a0,16(s4) +8000ff88: 24050c63 beqz a0,800101e0 <_svfiprintf_r+0x10a8> +8000ff8c: 04000793 li a5,64 +8000ff90: 00fa2a23 sw a5,20(s4) +8000ff94: a00ff06f j 8000f194 <_svfiprintf_r+0x5c> +8000ff98: 02012783 lw a5,32(sp) +8000ff9c: 01c12583 lw a1,28(sp) +8000ffa0: 00000913 li s2,0 +8000ffa4: 40f40433 sub s0,s0,a5 +8000ffa8: 00078613 mv a2,a5 +8000ffac: 00040513 mv a0,s0 +8000ffb0: a3df90ef jal ra,800099ec +8000ffb4: 001cc583 lbu a1,1(s9) +8000ffb8: 00a00613 li a2,10 +8000ffbc: 00000693 li a3,0 +8000ffc0: 00b03833 snez a6,a1 +8000ffc4: 00098513 mv a0,s3 +8000ffc8: 000a0593 mv a1,s4 +8000ffcc: 010c8cb3 add s9,s9,a6 +8000ffd0: 4f4000ef jal ra,800104c4 <__udivdi3> +8000ffd4: e0dff06f j 8000fde0 <_svfiprintf_r+0xca8> +8000ffd8: 00090a13 mv s4,s2 +8000ffdc: c24ff06f j 8000f400 <_svfiprintf_r+0x2c8> +8000ffe0: 04097793 andi a5,s2,64 +8000ffe4: 0a078263 beqz a5,80010088 <_svfiprintf_r+0xf50> +8000ffe8: 00c12783 lw a5,12(sp) +8000ffec: 00000c13 li s8,0 +8000fff0: 00c12623 sw a2,12(sp) +8000fff4: 0007dc83 lhu s9,0(a5) +8000fff8: ef1ff06f j 8000fee8 <_svfiprintf_r+0xdb0> +8000fffc: 04010613 addi a2,sp,64 +80010000: 000a0593 mv a1,s4 +80010004: 000b0513 mv a0,s6 +80010008: 03112223 sw a7,36(sp) +8001000c: f71fe0ef jal ra,8000ef7c <__ssprint_r> +80010010: be051863 bnez a0,8000f400 <_svfiprintf_r+0x2c8> +80010014: 04412603 lw a2,68(sp) +80010018: 04812783 lw a5,72(sp) +8001001c: 02412883 lw a7,36(sp) +80010020: 05410693 addi a3,sp,84 +80010024: 00160593 addi a1,a2,1 +80010028: 000a8d13 mv s10,s5 +8001002c: b68ff06f j 8000f394 <_svfiprintf_r+0x25c> +80010030: 0019c683 lbu a3,1(s3) +80010034: 20096913 ori s2,s2,512 +80010038: 00198993 addi s3,s3,1 +8001003c: a30ff06f j 8000f26c <_svfiprintf_r+0x134> +80010040: 0019c683 lbu a3,1(s3) +80010044: 02096913 ori s2,s2,32 +80010048: 00198993 addi s3,s3,1 +8001004c: a20ff06f j 8000f26c <_svfiprintf_r+0x134> +80010050: 00040a13 mv s4,s0 +80010054: bacff06f j 8000f400 <_svfiprintf_r+0x2c8> +80010058: 00812783 lw a5,8(sp) +8001005c: 00f6a023 sw a5,0(a3) +80010060: 97cff06f j 8000f1dc <_svfiprintf_r+0xa4> +80010064: 00600793 li a5,6 +80010068: 00088c93 mv s9,a7 +8001006c: 0117f463 bgeu a5,a7,80010074 <_svfiprintf_r+0xf3c> +80010070: 00600c93 li s9,6 +80010074: 80015e37 lui t3,0x80015 +80010078: 000c8c13 mv s8,s9 +8001007c: 01b12623 sw s11,12(sp) +80010080: ca0e0413 addi s0,t3,-864 # 80014ca0 <__BSS_END__+0xffffe064> +80010084: a58ff06f j 8000f2dc <_svfiprintf_r+0x1a4> +80010088: 20097793 andi a5,s2,512 +8001008c: 0c078663 beqz a5,80010158 <_svfiprintf_r+0x1020> +80010090: 00c12783 lw a5,12(sp) +80010094: 00000c13 li s8,0 +80010098: 00c12623 sw a2,12(sp) +8001009c: 0007cc83 lbu s9,0(a5) +800100a0: e49ff06f j 8000fee8 <_svfiprintf_r+0xdb0> +800100a4: 20097793 andi a5,s2,512 +800100a8: 08078e63 beqz a5,80010144 <_svfiprintf_r+0x100c> +800100ac: 00c12783 lw a5,12(sp) +800100b0: 00000c13 li s8,0 +800100b4: 00d12623 sw a3,12(sp) +800100b8: 0007cc83 lbu s9,0(a5) +800100bc: d30ff06f j 8000f5ec <_svfiprintf_r+0x4b4> +800100c0: 20097793 andi a5,s2,512 +800100c4: 06078463 beqz a5,8001012c <_svfiprintf_r+0xff4> +800100c8: 00c12783 lw a5,12(sp) +800100cc: 00d12623 sw a3,12(sp) +800100d0: 00078c83 lb s9,0(a5) +800100d4: 41fcdc13 srai s8,s9,0x1f +800100d8: 000c0693 mv a3,s8 +800100dc: c8cff06f j 8000f568 <_svfiprintf_r+0x430> +800100e0: 200df793 andi a5,s11,512 +800100e4: 02078863 beqz a5,80010114 <_svfiprintf_r+0xfdc> +800100e8: 00c12783 lw a5,12(sp) +800100ec: 00000c13 li s8,0 +800100f0: 00d12623 sw a3,12(sp) +800100f4: 0007cc83 lbu s9,0(a5) +800100f8: 00100693 li a3,1 +800100fc: cf8ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> +80010100: 00068613 mv a2,a3 +80010104: 931ff06f j 8000fa34 <_svfiprintf_r+0x8fc> +80010108: 00900793 li a5,9 +8001010c: cd37eae3 bltu a5,s3,8000fde0 <_svfiprintf_r+0xca8> +80010110: d1dff06f j 8000fe2c <_svfiprintf_r+0xcf4> +80010114: 00c12783 lw a5,12(sp) +80010118: 00000c13 li s8,0 +8001011c: 00d12623 sw a3,12(sp) +80010120: 0007ac83 lw s9,0(a5) +80010124: 00100693 li a3,1 +80010128: cccff06f j 8000f5f4 <_svfiprintf_r+0x4bc> +8001012c: 00c12783 lw a5,12(sp) +80010130: 00d12623 sw a3,12(sp) +80010134: 0007ac83 lw s9,0(a5) +80010138: 41fcdc13 srai s8,s9,0x1f +8001013c: 000c0693 mv a3,s8 +80010140: c28ff06f j 8000f568 <_svfiprintf_r+0x430> +80010144: 00c12783 lw a5,12(sp) +80010148: 00000c13 li s8,0 +8001014c: 00d12623 sw a3,12(sp) +80010150: 0007ac83 lw s9,0(a5) +80010154: c98ff06f j 8000f5ec <_svfiprintf_r+0x4b4> +80010158: 00c12783 lw a5,12(sp) +8001015c: 00000c13 li s8,0 +80010160: 00c12623 sw a2,12(sp) +80010164: 0007ac83 lw s9,0(a5) +80010168: d81ff06f j 8000fee8 <_svfiprintf_r+0xdb0> +8001016c: 00812783 lw a5,8(sp) +80010170: 00f69023 sh a5,0(a3) +80010174: 868ff06f j 8000f1dc <_svfiprintf_r+0xa4> +80010178: 04010613 addi a2,sp,64 +8001017c: 000a0593 mv a1,s4 +80010180: 000b0513 mv a0,s6 +80010184: df9fe0ef jal ra,8000ef7c <__ssprint_r> +80010188: a78ff06f j 8000f400 <_svfiprintf_r+0x2c8> +8001018c: 00088c93 mv s9,a7 +80010190: 01b12623 sw s11,12(sp) +80010194: 00000893 li a7,0 +80010198: c0cff06f j 8000f5a4 <_svfiprintf_r+0x46c> +8001019c: 00090d93 mv s11,s2 +800101a0: bf0ff06f j 8000f590 <_svfiprintf_r+0x458> +800101a4: 00068513 mv a0,a3 +800101a8: 00058613 mv a2,a1 +800101ac: fe4ff06f j 8000f990 <_svfiprintf_r+0x858> +800101b0: fff00793 li a5,-1 +800101b4: 00f12423 sw a5,8(sp) +800101b8: a54ff06f j 8000f40c <_svfiprintf_r+0x2d4> +800101bc: 00c12783 lw a5,12(sp) +800101c0: 0007a403 lw s0,0(a5) +800101c4: 00478793 addi a5,a5,4 +800101c8: 00045463 bgez s0,800101d0 <_svfiprintf_r+0x1098> +800101cc: fff00413 li s0,-1 +800101d0: 0019c683 lbu a3,1(s3) +800101d4: 00f12623 sw a5,12(sp) +800101d8: 00070993 mv s3,a4 +800101dc: 890ff06f j 8000f26c <_svfiprintf_r+0x134> +800101e0: 00c00793 li a5,12 +800101e4: 00fb2023 sw a5,0(s6) +800101e8: fff00793 li a5,-1 +800101ec: 00f12423 sw a5,8(sp) +800101f0: a1cff06f j 8000f40c <_svfiprintf_r+0x2d4> -80010168 <__swbuf_r>: -80010168: fe010113 addi sp,sp,-32 -8001016c: 00812c23 sw s0,24(sp) -80010170: 00912a23 sw s1,20(sp) -80010174: 01212823 sw s2,16(sp) -80010178: 00112e23 sw ra,28(sp) -8001017c: 01312623 sw s3,12(sp) -80010180: 00050913 mv s2,a0 -80010184: 00058493 mv s1,a1 -80010188: 00060413 mv s0,a2 -8001018c: 00050663 beqz a0,80010198 <__swbuf_r+0x30> -80010190: 03852783 lw a5,56(a0) -80010194: 14078863 beqz a5,800102e4 <__swbuf_r+0x17c> -80010198: 00c41703 lh a4,12(s0) -8001019c: 01842683 lw a3,24(s0) -800101a0: 00877793 andi a5,a4,8 -800101a4: 00d42423 sw a3,8(s0) -800101a8: 01071693 slli a3,a4,0x10 -800101ac: 0106d693 srli a3,a3,0x10 -800101b0: 08078263 beqz a5,80010234 <__swbuf_r+0xcc> -800101b4: 01042783 lw a5,16(s0) -800101b8: 06078e63 beqz a5,80010234 <__swbuf_r+0xcc> -800101bc: 01269613 slli a2,a3,0x12 -800101c0: 0ff4f993 andi s3,s1,255 -800101c4: 0ff4f493 andi s1,s1,255 -800101c8: 08065e63 bgez a2,80010264 <__swbuf_r+0xfc> -800101cc: 00042703 lw a4,0(s0) -800101d0: 01442683 lw a3,20(s0) -800101d4: 40f707b3 sub a5,a4,a5 -800101d8: 0ad7de63 bge a5,a3,80010294 <__swbuf_r+0x12c> -800101dc: 00842683 lw a3,8(s0) -800101e0: 00170613 addi a2,a4,1 -800101e4: 00c42023 sw a2,0(s0) -800101e8: fff68693 addi a3,a3,-1 -800101ec: 00d42423 sw a3,8(s0) -800101f0: 01370023 sb s3,0(a4) -800101f4: 01442703 lw a4,20(s0) -800101f8: 00178793 addi a5,a5,1 -800101fc: 0cf70863 beq a4,a5,800102cc <__swbuf_r+0x164> -80010200: 00c45783 lhu a5,12(s0) -80010204: 0017f793 andi a5,a5,1 -80010208: 00078663 beqz a5,80010214 <__swbuf_r+0xac> -8001020c: 00a00793 li a5,10 -80010210: 0af48e63 beq s1,a5,800102cc <__swbuf_r+0x164> -80010214: 01c12083 lw ra,28(sp) -80010218: 01812403 lw s0,24(sp) -8001021c: 01012903 lw s2,16(sp) -80010220: 00c12983 lw s3,12(sp) -80010224: 00048513 mv a0,s1 -80010228: 01412483 lw s1,20(sp) -8001022c: 02010113 addi sp,sp,32 -80010230: 00008067 ret -80010234: 00040593 mv a1,s0 -80010238: 00090513 mv a0,s2 -8001023c: dcdf30ef jal ra,80004008 <__swsetup_r> -80010240: 08051e63 bnez a0,800102dc <__swbuf_r+0x174> -80010244: 00c41703 lh a4,12(s0) -80010248: 0ff4f993 andi s3,s1,255 -8001024c: 01042783 lw a5,16(s0) -80010250: 01071693 slli a3,a4,0x10 -80010254: 0106d693 srli a3,a3,0x10 -80010258: 01269613 slli a2,a3,0x12 -8001025c: 0ff4f493 andi s1,s1,255 -80010260: f60646e3 bltz a2,800101cc <__swbuf_r+0x64> -80010264: 06442683 lw a3,100(s0) -80010268: 00002637 lui a2,0x2 -8001026c: 00c76733 or a4,a4,a2 -80010270: ffffe637 lui a2,0xffffe -80010274: fff60613 addi a2,a2,-1 # ffffdfff <__BSS_END__+0x7ffe73cf> -80010278: 00c6f6b3 and a3,a3,a2 -8001027c: 00e41623 sh a4,12(s0) -80010280: 00042703 lw a4,0(s0) -80010284: 06d42223 sw a3,100(s0) -80010288: 01442683 lw a3,20(s0) -8001028c: 40f707b3 sub a5,a4,a5 -80010290: f4d7c6e3 blt a5,a3,800101dc <__swbuf_r+0x74> -80010294: 00040593 mv a1,s0 -80010298: 00090513 mv a0,s2 -8001029c: adcf40ef jal ra,80004578 <_fflush_r> -800102a0: 02051e63 bnez a0,800102dc <__swbuf_r+0x174> -800102a4: 00042703 lw a4,0(s0) -800102a8: 00842683 lw a3,8(s0) -800102ac: 00100793 li a5,1 -800102b0: 00170613 addi a2,a4,1 -800102b4: fff68693 addi a3,a3,-1 -800102b8: 00c42023 sw a2,0(s0) -800102bc: 00d42423 sw a3,8(s0) -800102c0: 01370023 sb s3,0(a4) -800102c4: 01442703 lw a4,20(s0) -800102c8: f2f71ce3 bne a4,a5,80010200 <__swbuf_r+0x98> -800102cc: 00040593 mv a1,s0 -800102d0: 00090513 mv a0,s2 -800102d4: aa4f40ef jal ra,80004578 <_fflush_r> -800102d8: f2050ee3 beqz a0,80010214 <__swbuf_r+0xac> -800102dc: fff00493 li s1,-1 -800102e0: f35ff06f j 80010214 <__swbuf_r+0xac> -800102e4: e30f40ef jal ra,80004914 <__sinit> -800102e8: eb1ff06f j 80010198 <__swbuf_r+0x30> +800101f4 <__swbuf_r>: +800101f4: fe010113 addi sp,sp,-32 +800101f8: 00812c23 sw s0,24(sp) +800101fc: 00912a23 sw s1,20(sp) +80010200: 01212823 sw s2,16(sp) +80010204: 00112e23 sw ra,28(sp) +80010208: 01312623 sw s3,12(sp) +8001020c: 00050913 mv s2,a0 +80010210: 00058493 mv s1,a1 +80010214: 00060413 mv s0,a2 +80010218: 00050663 beqz a0,80010224 <__swbuf_r+0x30> +8001021c: 03852783 lw a5,56(a0) +80010220: 14078863 beqz a5,80010370 <__swbuf_r+0x17c> +80010224: 00c41703 lh a4,12(s0) +80010228: 01842683 lw a3,24(s0) +8001022c: 00877793 andi a5,a4,8 +80010230: 00d42423 sw a3,8(s0) +80010234: 01071693 slli a3,a4,0x10 +80010238: 0106d693 srli a3,a3,0x10 +8001023c: 08078263 beqz a5,800102c0 <__swbuf_r+0xcc> +80010240: 01042783 lw a5,16(s0) +80010244: 06078e63 beqz a5,800102c0 <__swbuf_r+0xcc> +80010248: 01269613 slli a2,a3,0x12 +8001024c: 0ff4f993 andi s3,s1,255 +80010250: 0ff4f493 andi s1,s1,255 +80010254: 08065e63 bgez a2,800102f0 <__swbuf_r+0xfc> +80010258: 00042703 lw a4,0(s0) +8001025c: 01442683 lw a3,20(s0) +80010260: 40f707b3 sub a5,a4,a5 +80010264: 0ad7de63 bge a5,a3,80010320 <__swbuf_r+0x12c> +80010268: 00842683 lw a3,8(s0) +8001026c: 00170613 addi a2,a4,1 +80010270: 00c42023 sw a2,0(s0) +80010274: fff68693 addi a3,a3,-1 +80010278: 00d42423 sw a3,8(s0) +8001027c: 01370023 sb s3,0(a4) +80010280: 01442703 lw a4,20(s0) +80010284: 00178793 addi a5,a5,1 +80010288: 0cf70863 beq a4,a5,80010358 <__swbuf_r+0x164> +8001028c: 00c45783 lhu a5,12(s0) +80010290: 0017f793 andi a5,a5,1 +80010294: 00078663 beqz a5,800102a0 <__swbuf_r+0xac> +80010298: 00a00793 li a5,10 +8001029c: 0af48e63 beq s1,a5,80010358 <__swbuf_r+0x164> +800102a0: 01c12083 lw ra,28(sp) +800102a4: 01812403 lw s0,24(sp) +800102a8: 01012903 lw s2,16(sp) +800102ac: 00c12983 lw s3,12(sp) +800102b0: 00048513 mv a0,s1 +800102b4: 01412483 lw s1,20(sp) +800102b8: 02010113 addi sp,sp,32 +800102bc: 00008067 ret +800102c0: 00040593 mv a1,s0 +800102c4: 00090513 mv a0,s2 +800102c8: cb9f30ef jal ra,80003f80 <__swsetup_r> +800102cc: 08051e63 bnez a0,80010368 <__swbuf_r+0x174> +800102d0: 00c41703 lh a4,12(s0) +800102d4: 0ff4f993 andi s3,s1,255 +800102d8: 01042783 lw a5,16(s0) +800102dc: 01071693 slli a3,a4,0x10 +800102e0: 0106d693 srli a3,a3,0x10 +800102e4: 01269613 slli a2,a3,0x12 +800102e8: 0ff4f493 andi s1,s1,255 +800102ec: f60646e3 bltz a2,80010258 <__swbuf_r+0x64> +800102f0: 06442683 lw a3,100(s0) +800102f4: 00002637 lui a2,0x2 +800102f8: 00c76733 or a4,a4,a2 +800102fc: ffffe637 lui a2,0xffffe +80010300: fff60613 addi a2,a2,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> +80010304: 00c6f6b3 and a3,a3,a2 +80010308: 00e41623 sh a4,12(s0) +8001030c: 00042703 lw a4,0(s0) +80010310: 06d42223 sw a3,100(s0) +80010314: 01442683 lw a3,20(s0) +80010318: 40f707b3 sub a5,a4,a5 +8001031c: f4d7c6e3 blt a5,a3,80010268 <__swbuf_r+0x74> +80010320: 00040593 mv a1,s0 +80010324: 00090513 mv a0,s2 +80010328: 944f40ef jal ra,8000446c <_fflush_r> +8001032c: 02051e63 bnez a0,80010368 <__swbuf_r+0x174> +80010330: 00042703 lw a4,0(s0) +80010334: 00842683 lw a3,8(s0) +80010338: 00100793 li a5,1 +8001033c: 00170613 addi a2,a4,1 +80010340: fff68693 addi a3,a3,-1 +80010344: 00c42023 sw a2,0(s0) +80010348: 00d42423 sw a3,8(s0) +8001034c: 01370023 sb s3,0(a4) +80010350: 01442703 lw a4,20(s0) +80010354: f2f71ce3 bne a4,a5,8001028c <__swbuf_r+0x98> +80010358: 00040593 mv a1,s0 +8001035c: 00090513 mv a0,s2 +80010360: 90cf40ef jal ra,8000446c <_fflush_r> +80010364: f2050ee3 beqz a0,800102a0 <__swbuf_r+0xac> +80010368: fff00493 li s1,-1 +8001036c: f35ff06f j 800102a0 <__swbuf_r+0xac> +80010370: c98f40ef jal ra,80004808 <__sinit> +80010374: eb1ff06f j 80010224 <__swbuf_r+0x30> -800102ec <__swbuf>: -800102ec: 00050793 mv a5,a0 -800102f0: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -800102f4: 00058613 mv a2,a1 -800102f8: 00078593 mv a1,a5 -800102fc: e6dff06f j 80010168 <__swbuf_r> +80010378 <__swbuf>: +80010378: 00050793 mv a5,a0 +8001037c: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +80010380: 00058613 mv a2,a1 +80010384: 00078593 mv a1,a5 +80010388: e6dff06f j 800101f4 <__swbuf_r> -80010300 <_wcrtomb_r>: -80010300: fe010113 addi sp,sp,-32 -80010304: 00812c23 sw s0,24(sp) -80010308: 00912a23 sw s1,20(sp) -8001030c: 00112e23 sw ra,28(sp) -80010310: ea01a783 lw a5,-352(gp) # 800166a8 <__global_locale+0xe0> -80010314: 00050413 mv s0,a0 -80010318: 00068493 mv s1,a3 -8001031c: 02058263 beqz a1,80010340 <_wcrtomb_r+0x40> -80010320: 000780e7 jalr a5 -80010324: fff00793 li a5,-1 -80010328: 02f50663 beq a0,a5,80010354 <_wcrtomb_r+0x54> -8001032c: 01c12083 lw ra,28(sp) -80010330: 01812403 lw s0,24(sp) -80010334: 01412483 lw s1,20(sp) -80010338: 02010113 addi sp,sp,32 -8001033c: 00008067 ret -80010340: 00000613 li a2,0 -80010344: 00410593 addi a1,sp,4 -80010348: 000780e7 jalr a5 -8001034c: fff00793 li a5,-1 -80010350: fcf51ee3 bne a0,a5,8001032c <_wcrtomb_r+0x2c> -80010354: 0004a023 sw zero,0(s1) -80010358: 08a00793 li a5,138 -8001035c: 01c12083 lw ra,28(sp) -80010360: 00f42023 sw a5,0(s0) -80010364: 01812403 lw s0,24(sp) -80010368: 01412483 lw s1,20(sp) -8001036c: 02010113 addi sp,sp,32 -80010370: 00008067 ret - -80010374 : -80010374: fe010113 addi sp,sp,-32 -80010378: 00812c23 sw s0,24(sp) -8001037c: 00912a23 sw s1,20(sp) -80010380: 00112e23 sw ra,28(sp) -80010384: 3601a483 lw s1,864(gp) # 80016b68 <_impure_ptr> -80010388: ea01a783 lw a5,-352(gp) # 800166a8 <__global_locale+0xe0> -8001038c: 00060413 mv s0,a2 -80010390: 02050a63 beqz a0,800103c4 -80010394: 00058613 mv a2,a1 -80010398: 00040693 mv a3,s0 -8001039c: 00050593 mv a1,a0 -800103a0: 00048513 mv a0,s1 -800103a4: 000780e7 jalr a5 -800103a8: fff00793 li a5,-1 -800103ac: 02f50a63 beq a0,a5,800103e0 -800103b0: 01c12083 lw ra,28(sp) -800103b4: 01812403 lw s0,24(sp) -800103b8: 01412483 lw s1,20(sp) -800103bc: 02010113 addi sp,sp,32 -800103c0: 00008067 ret -800103c4: 00060693 mv a3,a2 -800103c8: 00410593 addi a1,sp,4 +8001038c <_wcrtomb_r>: +8001038c: fe010113 addi sp,sp,-32 +80010390: 00812c23 sw s0,24(sp) +80010394: 00912a23 sw s1,20(sp) +80010398: 00112e23 sw ra,28(sp) +8001039c: 2a81a783 lw a5,680(gp) # 80016ab0 <__global_locale+0xe0> +800103a0: 00050413 mv s0,a0 +800103a4: 00068493 mv s1,a3 +800103a8: 02058263 beqz a1,800103cc <_wcrtomb_r+0x40> +800103ac: 000780e7 jalr a5 +800103b0: fff00793 li a5,-1 +800103b4: 02f50663 beq a0,a5,800103e0 <_wcrtomb_r+0x54> +800103b8: 01c12083 lw ra,28(sp) +800103bc: 01812403 lw s0,24(sp) +800103c0: 01412483 lw s1,20(sp) +800103c4: 02010113 addi sp,sp,32 +800103c8: 00008067 ret 800103cc: 00000613 li a2,0 -800103d0: 00048513 mv a0,s1 +800103d0: 00410593 addi a1,sp,4 800103d4: 000780e7 jalr a5 800103d8: fff00793 li a5,-1 -800103dc: fcf51ae3 bne a0,a5,800103b0 -800103e0: 00042023 sw zero,0(s0) -800103e4: 01c12083 lw ra,28(sp) -800103e8: 01812403 lw s0,24(sp) -800103ec: 08a00793 li a5,138 -800103f0: 00f4a023 sw a5,0(s1) +800103dc: fcf51ee3 bne a0,a5,800103b8 <_wcrtomb_r+0x2c> +800103e0: 0004a023 sw zero,0(s1) +800103e4: 08a00793 li a5,138 +800103e8: 01c12083 lw ra,28(sp) +800103ec: 00f42023 sw a5,0(s0) +800103f0: 01812403 lw s0,24(sp) 800103f4: 01412483 lw s1,20(sp) 800103f8: 02010113 addi sp,sp,32 800103fc: 00008067 ret -80010400 <__udivdi3>: -80010400: 00050893 mv a7,a0 -80010404: 00058793 mv a5,a1 -80010408: 00060813 mv a6,a2 -8001040c: 00068513 mv a0,a3 -80010410: 00088313 mv t1,a7 -80010414: 28069463 bnez a3,8001069c <__udivdi3+0x29c> -80010418: 800156b7 lui a3,0x80015 -8001041c: 7fc68693 addi a3,a3,2044 # 800157fc <__BSS_END__+0xffffebcc> -80010420: 0ec5f663 bgeu a1,a2,8001050c <__udivdi3+0x10c> -80010424: 00010737 lui a4,0x10 -80010428: 0ce67863 bgeu a2,a4,800104f8 <__udivdi3+0xf8> -8001042c: 0ff00713 li a4,255 -80010430: 00c73733 sltu a4,a4,a2 -80010434: 00371713 slli a4,a4,0x3 -80010438: 00e65533 srl a0,a2,a4 -8001043c: 00a686b3 add a3,a3,a0 -80010440: 0006c683 lbu a3,0(a3) -80010444: 02000513 li a0,32 -80010448: 00e68733 add a4,a3,a4 -8001044c: 40e506b3 sub a3,a0,a4 -80010450: 00e50c63 beq a0,a4,80010468 <__udivdi3+0x68> -80010454: 00d797b3 sll a5,a5,a3 -80010458: 00e8d733 srl a4,a7,a4 -8001045c: 00d61833 sll a6,a2,a3 -80010460: 00f765b3 or a1,a4,a5 -80010464: 00d89333 sll t1,a7,a3 -80010468: 01085893 srli a7,a6,0x10 -8001046c: 0315d7b3 divu a5,a1,a7 -80010470: 01081613 slli a2,a6,0x10 -80010474: 01065613 srli a2,a2,0x10 -80010478: 01035713 srli a4,t1,0x10 -8001047c: 0315f6b3 remu a3,a1,a7 -80010480: 00078513 mv a0,a5 -80010484: 02f605b3 mul a1,a2,a5 -80010488: 01069693 slli a3,a3,0x10 -8001048c: 00e6e733 or a4,a3,a4 -80010490: 00b77e63 bgeu a4,a1,800104ac <__udivdi3+0xac> -80010494: 01070733 add a4,a4,a6 -80010498: fff78513 addi a0,a5,-1 -8001049c: 01076863 bltu a4,a6,800104ac <__udivdi3+0xac> -800104a0: 00b77663 bgeu a4,a1,800104ac <__udivdi3+0xac> -800104a4: ffe78513 addi a0,a5,-2 -800104a8: 01070733 add a4,a4,a6 -800104ac: 40b70733 sub a4,a4,a1 -800104b0: 031777b3 remu a5,a4,a7 -800104b4: 01031313 slli t1,t1,0x10 -800104b8: 01035313 srli t1,t1,0x10 -800104bc: 03175733 divu a4,a4,a7 -800104c0: 01079793 slli a5,a5,0x10 -800104c4: 0067e333 or t1,a5,t1 -800104c8: 02e606b3 mul a3,a2,a4 -800104cc: 00070613 mv a2,a4 -800104d0: 00d37c63 bgeu t1,a3,800104e8 <__udivdi3+0xe8> -800104d4: 00680333 add t1,a6,t1 -800104d8: fff70613 addi a2,a4,-1 # ffff <_start-0x7fff0001> -800104dc: 01036663 bltu t1,a6,800104e8 <__udivdi3+0xe8> -800104e0: 00d37463 bgeu t1,a3,800104e8 <__udivdi3+0xe8> -800104e4: ffe70613 addi a2,a4,-2 -800104e8: 01051513 slli a0,a0,0x10 -800104ec: 00c56533 or a0,a0,a2 -800104f0: 00000593 li a1,0 -800104f4: 0e40006f j 800105d8 <__udivdi3+0x1d8> -800104f8: 01000537 lui a0,0x1000 -800104fc: 01000713 li a4,16 -80010500: f2a66ce3 bltu a2,a0,80010438 <__udivdi3+0x38> -80010504: 01800713 li a4,24 -80010508: f31ff06f j 80010438 <__udivdi3+0x38> -8001050c: 00061663 bnez a2,80010518 <__udivdi3+0x118> -80010510: 00100713 li a4,1 -80010514: 02c75833 divu a6,a4,a2 -80010518: 00010737 lui a4,0x10 -8001051c: 0ce87063 bgeu a6,a4,800105dc <__udivdi3+0x1dc> -80010520: 0ff00713 li a4,255 -80010524: 01077463 bgeu a4,a6,8001052c <__udivdi3+0x12c> -80010528: 00800513 li a0,8 -8001052c: 00a85733 srl a4,a6,a0 -80010530: 00e686b3 add a3,a3,a4 -80010534: 0006c703 lbu a4,0(a3) -80010538: 02000613 li a2,32 -8001053c: 00a70733 add a4,a4,a0 -80010540: 40e606b3 sub a3,a2,a4 -80010544: 0ae61663 bne a2,a4,800105f0 <__udivdi3+0x1f0> -80010548: 410787b3 sub a5,a5,a6 -8001054c: 00100593 li a1,1 -80010550: 01085893 srli a7,a6,0x10 -80010554: 01081613 slli a2,a6,0x10 -80010558: 01065613 srli a2,a2,0x10 -8001055c: 01035713 srli a4,t1,0x10 -80010560: 0317f6b3 remu a3,a5,a7 -80010564: 0317d7b3 divu a5,a5,a7 -80010568: 01069693 slli a3,a3,0x10 -8001056c: 00e6e733 or a4,a3,a4 -80010570: 02f60e33 mul t3,a2,a5 -80010574: 00078513 mv a0,a5 -80010578: 01c77e63 bgeu a4,t3,80010594 <__udivdi3+0x194> -8001057c: 01070733 add a4,a4,a6 -80010580: fff78513 addi a0,a5,-1 -80010584: 01076863 bltu a4,a6,80010594 <__udivdi3+0x194> -80010588: 01c77663 bgeu a4,t3,80010594 <__udivdi3+0x194> -8001058c: ffe78513 addi a0,a5,-2 -80010590: 01070733 add a4,a4,a6 -80010594: 41c70733 sub a4,a4,t3 -80010598: 031777b3 remu a5,a4,a7 -8001059c: 01031313 slli t1,t1,0x10 -800105a0: 01035313 srli t1,t1,0x10 -800105a4: 03175733 divu a4,a4,a7 -800105a8: 01079793 slli a5,a5,0x10 -800105ac: 0067e333 or t1,a5,t1 -800105b0: 02e606b3 mul a3,a2,a4 -800105b4: 00070613 mv a2,a4 -800105b8: 00d37c63 bgeu t1,a3,800105d0 <__udivdi3+0x1d0> -800105bc: 00680333 add t1,a6,t1 -800105c0: fff70613 addi a2,a4,-1 # ffff <_start-0x7fff0001> -800105c4: 01036663 bltu t1,a6,800105d0 <__udivdi3+0x1d0> -800105c8: 00d37463 bgeu t1,a3,800105d0 <__udivdi3+0x1d0> -800105cc: ffe70613 addi a2,a4,-2 -800105d0: 01051513 slli a0,a0,0x10 -800105d4: 00c56533 or a0,a0,a2 -800105d8: 00008067 ret -800105dc: 01000737 lui a4,0x1000 -800105e0: 01000513 li a0,16 -800105e4: f4e864e3 bltu a6,a4,8001052c <__udivdi3+0x12c> -800105e8: 01800513 li a0,24 -800105ec: f41ff06f j 8001052c <__udivdi3+0x12c> -800105f0: 00d81833 sll a6,a6,a3 -800105f4: 00e7d5b3 srl a1,a5,a4 -800105f8: 00d89333 sll t1,a7,a3 -800105fc: 00d797b3 sll a5,a5,a3 -80010600: 00e8d733 srl a4,a7,a4 -80010604: 01085893 srli a7,a6,0x10 -80010608: 00f76633 or a2,a4,a5 -8001060c: 0315f733 remu a4,a1,a7 -80010610: 01081793 slli a5,a6,0x10 -80010614: 0107d793 srli a5,a5,0x10 -80010618: 01065513 srli a0,a2,0x10 -8001061c: 0315d5b3 divu a1,a1,a7 -80010620: 01071713 slli a4,a4,0x10 -80010624: 00a76733 or a4,a4,a0 -80010628: 02b786b3 mul a3,a5,a1 -8001062c: 00058513 mv a0,a1 -80010630: 00d77e63 bgeu a4,a3,8001064c <__udivdi3+0x24c> -80010634: 01070733 add a4,a4,a6 -80010638: fff58513 addi a0,a1,-1 -8001063c: 01076863 bltu a4,a6,8001064c <__udivdi3+0x24c> -80010640: 00d77663 bgeu a4,a3,8001064c <__udivdi3+0x24c> -80010644: ffe58513 addi a0,a1,-2 -80010648: 01070733 add a4,a4,a6 -8001064c: 40d706b3 sub a3,a4,a3 -80010650: 0316f733 remu a4,a3,a7 -80010654: 01061613 slli a2,a2,0x10 -80010658: 01065613 srli a2,a2,0x10 -8001065c: 0316d6b3 divu a3,a3,a7 -80010660: 01071713 slli a4,a4,0x10 -80010664: 02d788b3 mul a7,a5,a3 -80010668: 00c767b3 or a5,a4,a2 -8001066c: 00068713 mv a4,a3 -80010670: 0117fe63 bgeu a5,a7,8001068c <__udivdi3+0x28c> -80010674: 010787b3 add a5,a5,a6 -80010678: fff68713 addi a4,a3,-1 -8001067c: 0107e863 bltu a5,a6,8001068c <__udivdi3+0x28c> -80010680: 0117f663 bgeu a5,a7,8001068c <__udivdi3+0x28c> -80010684: ffe68713 addi a4,a3,-2 -80010688: 010787b3 add a5,a5,a6 -8001068c: 01051593 slli a1,a0,0x10 -80010690: 411787b3 sub a5,a5,a7 -80010694: 00e5e5b3 or a1,a1,a4 -80010698: eb9ff06f j 80010550 <__udivdi3+0x150> -8001069c: 18d5e663 bltu a1,a3,80010828 <__udivdi3+0x428> -800106a0: 00010737 lui a4,0x10 -800106a4: 04e6f463 bgeu a3,a4,800106ec <__udivdi3+0x2ec> -800106a8: 0ff00713 li a4,255 -800106ac: 00d735b3 sltu a1,a4,a3 -800106b0: 00359593 slli a1,a1,0x3 -800106b4: 80015737 lui a4,0x80015 -800106b8: 00b6d533 srl a0,a3,a1 -800106bc: 7fc70713 addi a4,a4,2044 # 800157fc <__BSS_END__+0xffffebcc> -800106c0: 00a70733 add a4,a4,a0 -800106c4: 00074703 lbu a4,0(a4) -800106c8: 02000513 li a0,32 -800106cc: 00b70733 add a4,a4,a1 -800106d0: 40e505b3 sub a1,a0,a4 -800106d4: 02e51663 bne a0,a4,80010700 <__udivdi3+0x300> -800106d8: 00100513 li a0,1 -800106dc: eef6eee3 bltu a3,a5,800105d8 <__udivdi3+0x1d8> -800106e0: 00c8b533 sltu a0,a7,a2 -800106e4: 00154513 xori a0,a0,1 -800106e8: ef1ff06f j 800105d8 <__udivdi3+0x1d8> -800106ec: 01000737 lui a4,0x1000 -800106f0: 01000593 li a1,16 -800106f4: fce6e0e3 bltu a3,a4,800106b4 <__udivdi3+0x2b4> -800106f8: 01800593 li a1,24 -800106fc: fb9ff06f j 800106b4 <__udivdi3+0x2b4> -80010700: 00e65333 srl t1,a2,a4 -80010704: 00b696b3 sll a3,a3,a1 -80010708: 00d36333 or t1,t1,a3 -8001070c: 01035513 srli a0,t1,0x10 -80010710: 00b61eb3 sll t4,a2,a1 -80010714: 00e7d633 srl a2,a5,a4 -80010718: 02a676b3 remu a3,a2,a0 -8001071c: 00b797b3 sll a5,a5,a1 -80010720: 00e8d733 srl a4,a7,a4 -80010724: 00f76833 or a6,a4,a5 -80010728: 01031793 slli a5,t1,0x10 -8001072c: 0107d793 srli a5,a5,0x10 -80010730: 01085713 srli a4,a6,0x10 -80010734: 02a65633 divu a2,a2,a0 -80010738: 01069693 slli a3,a3,0x10 -8001073c: 00e6e733 or a4,a3,a4 -80010740: 02c78f33 mul t5,a5,a2 -80010744: 00060e13 mv t3,a2 -80010748: 01e77e63 bgeu a4,t5,80010764 <__udivdi3+0x364> -8001074c: 00670733 add a4,a4,t1 -80010750: fff60e13 addi t3,a2,-1 -80010754: 00676863 bltu a4,t1,80010764 <__udivdi3+0x364> -80010758: 01e77663 bgeu a4,t5,80010764 <__udivdi3+0x364> -8001075c: ffe60e13 addi t3,a2,-2 -80010760: 00670733 add a4,a4,t1 -80010764: 41e70733 sub a4,a4,t5 -80010768: 02a776b3 remu a3,a4,a0 -8001076c: 02a75733 divu a4,a4,a0 -80010770: 01069693 slli a3,a3,0x10 -80010774: 02e78633 mul a2,a5,a4 -80010778: 01081793 slli a5,a6,0x10 -8001077c: 0107d793 srli a5,a5,0x10 -80010780: 00f6e7b3 or a5,a3,a5 -80010784: 00070693 mv a3,a4 -80010788: 00c7fe63 bgeu a5,a2,800107a4 <__udivdi3+0x3a4> -8001078c: 006787b3 add a5,a5,t1 -80010790: fff70693 addi a3,a4,-1 # ffffff <_start-0x7f000001> -80010794: 0067e863 bltu a5,t1,800107a4 <__udivdi3+0x3a4> -80010798: 00c7f663 bgeu a5,a2,800107a4 <__udivdi3+0x3a4> -8001079c: ffe70693 addi a3,a4,-2 -800107a0: 006787b3 add a5,a5,t1 -800107a4: 010e1513 slli a0,t3,0x10 -800107a8: 00010e37 lui t3,0x10 -800107ac: 00d56533 or a0,a0,a3 -800107b0: fffe0693 addi a3,t3,-1 # ffff <_start-0x7fff0001> -800107b4: 00d57833 and a6,a0,a3 -800107b8: 40c787b3 sub a5,a5,a2 -800107bc: 00def6b3 and a3,t4,a3 -800107c0: 01055613 srli a2,a0,0x10 -800107c4: 010ede93 srli t4,t4,0x10 -800107c8: 02d80333 mul t1,a6,a3 -800107cc: 02d606b3 mul a3,a2,a3 -800107d0: 01035713 srli a4,t1,0x10 -800107d4: 03d80833 mul a6,a6,t4 -800107d8: 00d80833 add a6,a6,a3 -800107dc: 01070733 add a4,a4,a6 -800107e0: 03d60633 mul a2,a2,t4 -800107e4: 00d77463 bgeu a4,a3,800107ec <__udivdi3+0x3ec> -800107e8: 01c60633 add a2,a2,t3 -800107ec: 01075693 srli a3,a4,0x10 -800107f0: 00c68633 add a2,a3,a2 -800107f4: 02c7e663 bltu a5,a2,80010820 <__udivdi3+0x420> -800107f8: cec79ce3 bne a5,a2,800104f0 <__udivdi3+0xf0> -800107fc: 000107b7 lui a5,0x10 -80010800: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -80010804: 00f77733 and a4,a4,a5 -80010808: 01071713 slli a4,a4,0x10 -8001080c: 00f37333 and t1,t1,a5 -80010810: 00b898b3 sll a7,a7,a1 -80010814: 00670733 add a4,a4,t1 -80010818: 00000593 li a1,0 -8001081c: dae8fee3 bgeu a7,a4,800105d8 <__udivdi3+0x1d8> -80010820: fff50513 addi a0,a0,-1 # ffffff <_start-0x7f000001> -80010824: ccdff06f j 800104f0 <__udivdi3+0xf0> -80010828: 00000593 li a1,0 -8001082c: 00000513 li a0,0 -80010830: da9ff06f j 800105d8 <__udivdi3+0x1d8> +80010400 : +80010400: fe010113 addi sp,sp,-32 +80010404: 00812c23 sw s0,24(sp) +80010408: 00912a23 sw s1,20(sp) +8001040c: 00112e23 sw ra,28(sp) +80010410: 3601a483 lw s1,864(gp) # 80016b68 <_impure_ptr> +80010414: 2a81a783 lw a5,680(gp) # 80016ab0 <__global_locale+0xe0> +80010418: 00060413 mv s0,a2 +8001041c: 02050a63 beqz a0,80010450 +80010420: 00058613 mv a2,a1 +80010424: 00040693 mv a3,s0 +80010428: 00050593 mv a1,a0 +8001042c: 00048513 mv a0,s1 +80010430: 000780e7 jalr a5 +80010434: fff00793 li a5,-1 +80010438: 02f50a63 beq a0,a5,8001046c +8001043c: 01c12083 lw ra,28(sp) +80010440: 01812403 lw s0,24(sp) +80010444: 01412483 lw s1,20(sp) +80010448: 02010113 addi sp,sp,32 +8001044c: 00008067 ret +80010450: 00060693 mv a3,a2 +80010454: 00410593 addi a1,sp,4 +80010458: 00000613 li a2,0 +8001045c: 00048513 mv a0,s1 +80010460: 000780e7 jalr a5 +80010464: fff00793 li a5,-1 +80010468: fcf51ae3 bne a0,a5,8001043c +8001046c: 00042023 sw zero,0(s0) +80010470: 01c12083 lw ra,28(sp) +80010474: 01812403 lw s0,24(sp) +80010478: 08a00793 li a5,138 +8001047c: 00f4a023 sw a5,0(s1) +80010480: 01412483 lw s1,20(sp) +80010484: 02010113 addi sp,sp,32 +80010488: 00008067 ret -80010834 <__umoddi3>: -80010834: 00060893 mv a7,a2 -80010838: 00068713 mv a4,a3 -8001083c: 00050793 mv a5,a0 -80010840: 00058813 mv a6,a1 -80010844: 22069c63 bnez a3,80010a7c <__umoddi3+0x248> -80010848: 800156b7 lui a3,0x80015 -8001084c: 7fc68693 addi a3,a3,2044 # 800157fc <__BSS_END__+0xffffebcc> -80010850: 0cc5fc63 bgeu a1,a2,80010928 <__umoddi3+0xf4> -80010854: 00010337 lui t1,0x10 -80010858: 0a667e63 bgeu a2,t1,80010914 <__umoddi3+0xe0> -8001085c: 0ff00313 li t1,255 -80010860: 00c37463 bgeu t1,a2,80010868 <__umoddi3+0x34> -80010864: 00800713 li a4,8 -80010868: 00e65333 srl t1,a2,a4 -8001086c: 006686b3 add a3,a3,t1 -80010870: 0006ce03 lbu t3,0(a3) -80010874: 00ee0e33 add t3,t3,a4 -80010878: 02000713 li a4,32 -8001087c: 41c70333 sub t1,a4,t3 -80010880: 01c70c63 beq a4,t3,80010898 <__umoddi3+0x64> -80010884: 006595b3 sll a1,a1,t1 -80010888: 01c55e33 srl t3,a0,t3 -8001088c: 006618b3 sll a7,a2,t1 -80010890: 00be6833 or a6,t3,a1 -80010894: 006517b3 sll a5,a0,t1 -80010898: 0108d613 srli a2,a7,0x10 -8001089c: 02c87733 remu a4,a6,a2 -800108a0: 01089513 slli a0,a7,0x10 -800108a4: 01055513 srli a0,a0,0x10 -800108a8: 0107d693 srli a3,a5,0x10 -800108ac: 02c85833 divu a6,a6,a2 -800108b0: 01071713 slli a4,a4,0x10 -800108b4: 00d766b3 or a3,a4,a3 -800108b8: 03050833 mul a6,a0,a6 -800108bc: 0106fa63 bgeu a3,a6,800108d0 <__umoddi3+0x9c> -800108c0: 011686b3 add a3,a3,a7 -800108c4: 0116e663 bltu a3,a7,800108d0 <__umoddi3+0x9c> -800108c8: 0106f463 bgeu a3,a6,800108d0 <__umoddi3+0x9c> -800108cc: 011686b3 add a3,a3,a7 -800108d0: 410686b3 sub a3,a3,a6 -800108d4: 02c6f733 remu a4,a3,a2 -800108d8: 01079793 slli a5,a5,0x10 -800108dc: 0107d793 srli a5,a5,0x10 -800108e0: 02c6d6b3 divu a3,a3,a2 -800108e4: 02d506b3 mul a3,a0,a3 -800108e8: 01071513 slli a0,a4,0x10 -800108ec: 00f567b3 or a5,a0,a5 -800108f0: 00d7fa63 bgeu a5,a3,80010904 <__umoddi3+0xd0> -800108f4: 011787b3 add a5,a5,a7 -800108f8: 0117e663 bltu a5,a7,80010904 <__umoddi3+0xd0> -800108fc: 00d7f463 bgeu a5,a3,80010904 <__umoddi3+0xd0> -80010900: 011787b3 add a5,a5,a7 -80010904: 40d787b3 sub a5,a5,a3 -80010908: 0067d533 srl a0,a5,t1 -8001090c: 00000593 li a1,0 -80010910: 00008067 ret -80010914: 01000337 lui t1,0x1000 -80010918: 01000713 li a4,16 -8001091c: f46666e3 bltu a2,t1,80010868 <__umoddi3+0x34> -80010920: 01800713 li a4,24 -80010924: f45ff06f j 80010868 <__umoddi3+0x34> -80010928: 00061663 bnez a2,80010934 <__umoddi3+0x100> -8001092c: 00100613 li a2,1 -80010930: 031658b3 divu a7,a2,a7 -80010934: 00010637 lui a2,0x10 -80010938: 0ac8f263 bgeu a7,a2,800109dc <__umoddi3+0x1a8> -8001093c: 0ff00613 li a2,255 -80010940: 01167463 bgeu a2,a7,80010948 <__umoddi3+0x114> -80010944: 00800713 li a4,8 -80010948: 00e8d633 srl a2,a7,a4 -8001094c: 00c686b3 add a3,a3,a2 -80010950: 0006ce03 lbu t3,0(a3) -80010954: 00ee0e33 add t3,t3,a4 -80010958: 02000713 li a4,32 -8001095c: 41c70333 sub t1,a4,t3 -80010960: 09c71863 bne a4,t3,800109f0 <__umoddi3+0x1bc> -80010964: 411585b3 sub a1,a1,a7 -80010968: 0108d713 srli a4,a7,0x10 -8001096c: 01089513 slli a0,a7,0x10 -80010970: 01055513 srli a0,a0,0x10 -80010974: 0107d613 srli a2,a5,0x10 -80010978: 02e5f6b3 remu a3,a1,a4 -8001097c: 02e5d5b3 divu a1,a1,a4 -80010980: 01069693 slli a3,a3,0x10 -80010984: 00c6e6b3 or a3,a3,a2 -80010988: 02b505b3 mul a1,a0,a1 -8001098c: 00b6fa63 bgeu a3,a1,800109a0 <__umoddi3+0x16c> +8001048c <_wctomb_r>: +8001048c: 2a81a303 lw t1,680(gp) # 80016ab0 <__global_locale+0xe0> +80010490: 00030067 jr t1 + +80010494 <__ascii_wctomb>: +80010494: 02058463 beqz a1,800104bc <__ascii_wctomb+0x28> +80010498: 0ff00793 li a5,255 +8001049c: 00c7e863 bltu a5,a2,800104ac <__ascii_wctomb+0x18> +800104a0: 00c58023 sb a2,0(a1) +800104a4: 00100513 li a0,1 +800104a8: 00008067 ret +800104ac: 08a00793 li a5,138 +800104b0: 00f52023 sw a5,0(a0) +800104b4: fff00513 li a0,-1 +800104b8: 00008067 ret +800104bc: 00000513 li a0,0 +800104c0: 00008067 ret + +800104c4 <__udivdi3>: +800104c4: 00050893 mv a7,a0 +800104c8: 00058793 mv a5,a1 +800104cc: 00060813 mv a6,a2 +800104d0: 00068513 mv a0,a3 +800104d4: 00088313 mv t1,a7 +800104d8: 28069463 bnez a3,80010760 <__udivdi3+0x29c> +800104dc: 800166b7 lui a3,0x80016 +800104e0: 84c68693 addi a3,a3,-1972 # 8001584c <__BSS_END__+0xffffec10> +800104e4: 0ec5f663 bgeu a1,a2,800105d0 <__udivdi3+0x10c> +800104e8: 00010737 lui a4,0x10 +800104ec: 0ce67863 bgeu a2,a4,800105bc <__udivdi3+0xf8> +800104f0: 0ff00713 li a4,255 +800104f4: 00c73733 sltu a4,a4,a2 +800104f8: 00371713 slli a4,a4,0x3 +800104fc: 00e65533 srl a0,a2,a4 +80010500: 00a686b3 add a3,a3,a0 +80010504: 0006c683 lbu a3,0(a3) +80010508: 02000513 li a0,32 +8001050c: 00e68733 add a4,a3,a4 +80010510: 40e506b3 sub a3,a0,a4 +80010514: 00e50c63 beq a0,a4,8001052c <__udivdi3+0x68> +80010518: 00d797b3 sll a5,a5,a3 +8001051c: 00e8d733 srl a4,a7,a4 +80010520: 00d61833 sll a6,a2,a3 +80010524: 00f765b3 or a1,a4,a5 +80010528: 00d89333 sll t1,a7,a3 +8001052c: 01085893 srli a7,a6,0x10 +80010530: 0315d7b3 divu a5,a1,a7 +80010534: 01081613 slli a2,a6,0x10 +80010538: 01065613 srli a2,a2,0x10 +8001053c: 01035713 srli a4,t1,0x10 +80010540: 0315f6b3 remu a3,a1,a7 +80010544: 00078513 mv a0,a5 +80010548: 02f605b3 mul a1,a2,a5 +8001054c: 01069693 slli a3,a3,0x10 +80010550: 00e6e733 or a4,a3,a4 +80010554: 00b77e63 bgeu a4,a1,80010570 <__udivdi3+0xac> +80010558: 01070733 add a4,a4,a6 +8001055c: fff78513 addi a0,a5,-1 +80010560: 01076863 bltu a4,a6,80010570 <__udivdi3+0xac> +80010564: 00b77663 bgeu a4,a1,80010570 <__udivdi3+0xac> +80010568: ffe78513 addi a0,a5,-2 +8001056c: 01070733 add a4,a4,a6 +80010570: 40b70733 sub a4,a4,a1 +80010574: 031777b3 remu a5,a4,a7 +80010578: 01031313 slli t1,t1,0x10 +8001057c: 01035313 srli t1,t1,0x10 +80010580: 03175733 divu a4,a4,a7 +80010584: 01079793 slli a5,a5,0x10 +80010588: 0067e333 or t1,a5,t1 +8001058c: 02e606b3 mul a3,a2,a4 +80010590: 00070613 mv a2,a4 +80010594: 00d37c63 bgeu t1,a3,800105ac <__udivdi3+0xe8> +80010598: 00680333 add t1,a6,t1 +8001059c: fff70613 addi a2,a4,-1 # ffff <_start-0x7fff0001> +800105a0: 01036663 bltu t1,a6,800105ac <__udivdi3+0xe8> +800105a4: 00d37463 bgeu t1,a3,800105ac <__udivdi3+0xe8> +800105a8: ffe70613 addi a2,a4,-2 +800105ac: 01051513 slli a0,a0,0x10 +800105b0: 00c56533 or a0,a0,a2 +800105b4: 00000593 li a1,0 +800105b8: 0e40006f j 8001069c <__udivdi3+0x1d8> +800105bc: 01000537 lui a0,0x1000 +800105c0: 01000713 li a4,16 +800105c4: f2a66ce3 bltu a2,a0,800104fc <__udivdi3+0x38> +800105c8: 01800713 li a4,24 +800105cc: f31ff06f j 800104fc <__udivdi3+0x38> +800105d0: 00061663 bnez a2,800105dc <__udivdi3+0x118> +800105d4: 00100713 li a4,1 +800105d8: 02c75833 divu a6,a4,a2 +800105dc: 00010737 lui a4,0x10 +800105e0: 0ce87063 bgeu a6,a4,800106a0 <__udivdi3+0x1dc> +800105e4: 0ff00713 li a4,255 +800105e8: 01077463 bgeu a4,a6,800105f0 <__udivdi3+0x12c> +800105ec: 00800513 li a0,8 +800105f0: 00a85733 srl a4,a6,a0 +800105f4: 00e686b3 add a3,a3,a4 +800105f8: 0006c703 lbu a4,0(a3) +800105fc: 02000613 li a2,32 +80010600: 00a70733 add a4,a4,a0 +80010604: 40e606b3 sub a3,a2,a4 +80010608: 0ae61663 bne a2,a4,800106b4 <__udivdi3+0x1f0> +8001060c: 410787b3 sub a5,a5,a6 +80010610: 00100593 li a1,1 +80010614: 01085893 srli a7,a6,0x10 +80010618: 01081613 slli a2,a6,0x10 +8001061c: 01065613 srli a2,a2,0x10 +80010620: 01035713 srli a4,t1,0x10 +80010624: 0317f6b3 remu a3,a5,a7 +80010628: 0317d7b3 divu a5,a5,a7 +8001062c: 01069693 slli a3,a3,0x10 +80010630: 00e6e733 or a4,a3,a4 +80010634: 02f60e33 mul t3,a2,a5 +80010638: 00078513 mv a0,a5 +8001063c: 01c77e63 bgeu a4,t3,80010658 <__udivdi3+0x194> +80010640: 01070733 add a4,a4,a6 +80010644: fff78513 addi a0,a5,-1 +80010648: 01076863 bltu a4,a6,80010658 <__udivdi3+0x194> +8001064c: 01c77663 bgeu a4,t3,80010658 <__udivdi3+0x194> +80010650: ffe78513 addi a0,a5,-2 +80010654: 01070733 add a4,a4,a6 +80010658: 41c70733 sub a4,a4,t3 +8001065c: 031777b3 remu a5,a4,a7 +80010660: 01031313 slli t1,t1,0x10 +80010664: 01035313 srli t1,t1,0x10 +80010668: 03175733 divu a4,a4,a7 +8001066c: 01079793 slli a5,a5,0x10 +80010670: 0067e333 or t1,a5,t1 +80010674: 02e606b3 mul a3,a2,a4 +80010678: 00070613 mv a2,a4 +8001067c: 00d37c63 bgeu t1,a3,80010694 <__udivdi3+0x1d0> +80010680: 00680333 add t1,a6,t1 +80010684: fff70613 addi a2,a4,-1 # ffff <_start-0x7fff0001> +80010688: 01036663 bltu t1,a6,80010694 <__udivdi3+0x1d0> +8001068c: 00d37463 bgeu t1,a3,80010694 <__udivdi3+0x1d0> +80010690: ffe70613 addi a2,a4,-2 +80010694: 01051513 slli a0,a0,0x10 +80010698: 00c56533 or a0,a0,a2 +8001069c: 00008067 ret +800106a0: 01000737 lui a4,0x1000 +800106a4: 01000513 li a0,16 +800106a8: f4e864e3 bltu a6,a4,800105f0 <__udivdi3+0x12c> +800106ac: 01800513 li a0,24 +800106b0: f41ff06f j 800105f0 <__udivdi3+0x12c> +800106b4: 00d81833 sll a6,a6,a3 +800106b8: 00e7d5b3 srl a1,a5,a4 +800106bc: 00d89333 sll t1,a7,a3 +800106c0: 00d797b3 sll a5,a5,a3 +800106c4: 00e8d733 srl a4,a7,a4 +800106c8: 01085893 srli a7,a6,0x10 +800106cc: 00f76633 or a2,a4,a5 +800106d0: 0315f733 remu a4,a1,a7 +800106d4: 01081793 slli a5,a6,0x10 +800106d8: 0107d793 srli a5,a5,0x10 +800106dc: 01065513 srli a0,a2,0x10 +800106e0: 0315d5b3 divu a1,a1,a7 +800106e4: 01071713 slli a4,a4,0x10 +800106e8: 00a76733 or a4,a4,a0 +800106ec: 02b786b3 mul a3,a5,a1 +800106f0: 00058513 mv a0,a1 +800106f4: 00d77e63 bgeu a4,a3,80010710 <__udivdi3+0x24c> +800106f8: 01070733 add a4,a4,a6 +800106fc: fff58513 addi a0,a1,-1 +80010700: 01076863 bltu a4,a6,80010710 <__udivdi3+0x24c> +80010704: 00d77663 bgeu a4,a3,80010710 <__udivdi3+0x24c> +80010708: ffe58513 addi a0,a1,-2 +8001070c: 01070733 add a4,a4,a6 +80010710: 40d706b3 sub a3,a4,a3 +80010714: 0316f733 remu a4,a3,a7 +80010718: 01061613 slli a2,a2,0x10 +8001071c: 01065613 srli a2,a2,0x10 +80010720: 0316d6b3 divu a3,a3,a7 +80010724: 01071713 slli a4,a4,0x10 +80010728: 02d788b3 mul a7,a5,a3 +8001072c: 00c767b3 or a5,a4,a2 +80010730: 00068713 mv a4,a3 +80010734: 0117fe63 bgeu a5,a7,80010750 <__udivdi3+0x28c> +80010738: 010787b3 add a5,a5,a6 +8001073c: fff68713 addi a4,a3,-1 +80010740: 0107e863 bltu a5,a6,80010750 <__udivdi3+0x28c> +80010744: 0117f663 bgeu a5,a7,80010750 <__udivdi3+0x28c> +80010748: ffe68713 addi a4,a3,-2 +8001074c: 010787b3 add a5,a5,a6 +80010750: 01051593 slli a1,a0,0x10 +80010754: 411787b3 sub a5,a5,a7 +80010758: 00e5e5b3 or a1,a1,a4 +8001075c: eb9ff06f j 80010614 <__udivdi3+0x150> +80010760: 18d5e663 bltu a1,a3,800108ec <__udivdi3+0x428> +80010764: 00010737 lui a4,0x10 +80010768: 04e6f463 bgeu a3,a4,800107b0 <__udivdi3+0x2ec> +8001076c: 0ff00713 li a4,255 +80010770: 00d735b3 sltu a1,a4,a3 +80010774: 00359593 slli a1,a1,0x3 +80010778: 80016737 lui a4,0x80016 +8001077c: 00b6d533 srl a0,a3,a1 +80010780: 84c70713 addi a4,a4,-1972 # 8001584c <__BSS_END__+0xffffec10> +80010784: 00a70733 add a4,a4,a0 +80010788: 00074703 lbu a4,0(a4) +8001078c: 02000513 li a0,32 +80010790: 00b70733 add a4,a4,a1 +80010794: 40e505b3 sub a1,a0,a4 +80010798: 02e51663 bne a0,a4,800107c4 <__udivdi3+0x300> +8001079c: 00100513 li a0,1 +800107a0: eef6eee3 bltu a3,a5,8001069c <__udivdi3+0x1d8> +800107a4: 00c8b533 sltu a0,a7,a2 +800107a8: 00154513 xori a0,a0,1 +800107ac: ef1ff06f j 8001069c <__udivdi3+0x1d8> +800107b0: 01000737 lui a4,0x1000 +800107b4: 01000593 li a1,16 +800107b8: fce6e0e3 bltu a3,a4,80010778 <__udivdi3+0x2b4> +800107bc: 01800593 li a1,24 +800107c0: fb9ff06f j 80010778 <__udivdi3+0x2b4> +800107c4: 00e65333 srl t1,a2,a4 +800107c8: 00b696b3 sll a3,a3,a1 +800107cc: 00d36333 or t1,t1,a3 +800107d0: 01035513 srli a0,t1,0x10 +800107d4: 00b61eb3 sll t4,a2,a1 +800107d8: 00e7d633 srl a2,a5,a4 +800107dc: 02a676b3 remu a3,a2,a0 +800107e0: 00b797b3 sll a5,a5,a1 +800107e4: 00e8d733 srl a4,a7,a4 +800107e8: 00f76833 or a6,a4,a5 +800107ec: 01031793 slli a5,t1,0x10 +800107f0: 0107d793 srli a5,a5,0x10 +800107f4: 01085713 srli a4,a6,0x10 +800107f8: 02a65633 divu a2,a2,a0 +800107fc: 01069693 slli a3,a3,0x10 +80010800: 00e6e733 or a4,a3,a4 +80010804: 02c78f33 mul t5,a5,a2 +80010808: 00060e13 mv t3,a2 +8001080c: 01e77e63 bgeu a4,t5,80010828 <__udivdi3+0x364> +80010810: 00670733 add a4,a4,t1 +80010814: fff60e13 addi t3,a2,-1 +80010818: 00676863 bltu a4,t1,80010828 <__udivdi3+0x364> +8001081c: 01e77663 bgeu a4,t5,80010828 <__udivdi3+0x364> +80010820: ffe60e13 addi t3,a2,-2 +80010824: 00670733 add a4,a4,t1 +80010828: 41e70733 sub a4,a4,t5 +8001082c: 02a776b3 remu a3,a4,a0 +80010830: 02a75733 divu a4,a4,a0 +80010834: 01069693 slli a3,a3,0x10 +80010838: 02e78633 mul a2,a5,a4 +8001083c: 01081793 slli a5,a6,0x10 +80010840: 0107d793 srli a5,a5,0x10 +80010844: 00f6e7b3 or a5,a3,a5 +80010848: 00070693 mv a3,a4 +8001084c: 00c7fe63 bgeu a5,a2,80010868 <__udivdi3+0x3a4> +80010850: 006787b3 add a5,a5,t1 +80010854: fff70693 addi a3,a4,-1 # ffffff <_start-0x7f000001> +80010858: 0067e863 bltu a5,t1,80010868 <__udivdi3+0x3a4> +8001085c: 00c7f663 bgeu a5,a2,80010868 <__udivdi3+0x3a4> +80010860: ffe70693 addi a3,a4,-2 +80010864: 006787b3 add a5,a5,t1 +80010868: 010e1513 slli a0,t3,0x10 +8001086c: 00010e37 lui t3,0x10 +80010870: 00d56533 or a0,a0,a3 +80010874: fffe0693 addi a3,t3,-1 # ffff <_start-0x7fff0001> +80010878: 00d57833 and a6,a0,a3 +8001087c: 40c787b3 sub a5,a5,a2 +80010880: 00def6b3 and a3,t4,a3 +80010884: 01055613 srli a2,a0,0x10 +80010888: 010ede93 srli t4,t4,0x10 +8001088c: 02d80333 mul t1,a6,a3 +80010890: 02d606b3 mul a3,a2,a3 +80010894: 01035713 srli a4,t1,0x10 +80010898: 03d80833 mul a6,a6,t4 +8001089c: 00d80833 add a6,a6,a3 +800108a0: 01070733 add a4,a4,a6 +800108a4: 03d60633 mul a2,a2,t4 +800108a8: 00d77463 bgeu a4,a3,800108b0 <__udivdi3+0x3ec> +800108ac: 01c60633 add a2,a2,t3 +800108b0: 01075693 srli a3,a4,0x10 +800108b4: 00c68633 add a2,a3,a2 +800108b8: 02c7e663 bltu a5,a2,800108e4 <__udivdi3+0x420> +800108bc: cec79ce3 bne a5,a2,800105b4 <__udivdi3+0xf0> +800108c0: 000107b7 lui a5,0x10 +800108c4: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +800108c8: 00f77733 and a4,a4,a5 +800108cc: 01071713 slli a4,a4,0x10 +800108d0: 00f37333 and t1,t1,a5 +800108d4: 00b898b3 sll a7,a7,a1 +800108d8: 00670733 add a4,a4,t1 +800108dc: 00000593 li a1,0 +800108e0: dae8fee3 bgeu a7,a4,8001069c <__udivdi3+0x1d8> +800108e4: fff50513 addi a0,a0,-1 # ffffff <_start-0x7f000001> +800108e8: ccdff06f j 800105b4 <__udivdi3+0xf0> +800108ec: 00000593 li a1,0 +800108f0: 00000513 li a0,0 +800108f4: da9ff06f j 8001069c <__udivdi3+0x1d8> + +800108f8 <__umoddi3>: +800108f8: 00060893 mv a7,a2 +800108fc: 00068713 mv a4,a3 +80010900: 00050793 mv a5,a0 +80010904: 00058813 mv a6,a1 +80010908: 22069c63 bnez a3,80010b40 <__umoddi3+0x248> +8001090c: 800166b7 lui a3,0x80016 +80010910: 84c68693 addi a3,a3,-1972 # 8001584c <__BSS_END__+0xffffec10> +80010914: 0cc5fc63 bgeu a1,a2,800109ec <__umoddi3+0xf4> +80010918: 00010337 lui t1,0x10 +8001091c: 0a667e63 bgeu a2,t1,800109d8 <__umoddi3+0xe0> +80010920: 0ff00313 li t1,255 +80010924: 00c37463 bgeu t1,a2,8001092c <__umoddi3+0x34> +80010928: 00800713 li a4,8 +8001092c: 00e65333 srl t1,a2,a4 +80010930: 006686b3 add a3,a3,t1 +80010934: 0006ce03 lbu t3,0(a3) +80010938: 00ee0e33 add t3,t3,a4 +8001093c: 02000713 li a4,32 +80010940: 41c70333 sub t1,a4,t3 +80010944: 01c70c63 beq a4,t3,8001095c <__umoddi3+0x64> +80010948: 006595b3 sll a1,a1,t1 +8001094c: 01c55e33 srl t3,a0,t3 +80010950: 006618b3 sll a7,a2,t1 +80010954: 00be6833 or a6,t3,a1 +80010958: 006517b3 sll a5,a0,t1 +8001095c: 0108d613 srli a2,a7,0x10 +80010960: 02c87733 remu a4,a6,a2 +80010964: 01089513 slli a0,a7,0x10 +80010968: 01055513 srli a0,a0,0x10 +8001096c: 0107d693 srli a3,a5,0x10 +80010970: 02c85833 divu a6,a6,a2 +80010974: 01071713 slli a4,a4,0x10 +80010978: 00d766b3 or a3,a4,a3 +8001097c: 03050833 mul a6,a0,a6 +80010980: 0106fa63 bgeu a3,a6,80010994 <__umoddi3+0x9c> +80010984: 011686b3 add a3,a3,a7 +80010988: 0116e663 bltu a3,a7,80010994 <__umoddi3+0x9c> +8001098c: 0106f463 bgeu a3,a6,80010994 <__umoddi3+0x9c> 80010990: 011686b3 add a3,a3,a7 -80010994: 0116e663 bltu a3,a7,800109a0 <__umoddi3+0x16c> -80010998: 00b6f463 bgeu a3,a1,800109a0 <__umoddi3+0x16c> -8001099c: 011686b3 add a3,a3,a7 -800109a0: 40b685b3 sub a1,a3,a1 -800109a4: 02e5f6b3 remu a3,a1,a4 -800109a8: 01079793 slli a5,a5,0x10 -800109ac: 0107d793 srli a5,a5,0x10 -800109b0: 02e5d5b3 divu a1,a1,a4 -800109b4: 02b505b3 mul a1,a0,a1 -800109b8: 01069513 slli a0,a3,0x10 -800109bc: 00f567b3 or a5,a0,a5 -800109c0: 00b7fa63 bgeu a5,a1,800109d4 <__umoddi3+0x1a0> +80010994: 410686b3 sub a3,a3,a6 +80010998: 02c6f733 remu a4,a3,a2 +8001099c: 01079793 slli a5,a5,0x10 +800109a0: 0107d793 srli a5,a5,0x10 +800109a4: 02c6d6b3 divu a3,a3,a2 +800109a8: 02d506b3 mul a3,a0,a3 +800109ac: 01071513 slli a0,a4,0x10 +800109b0: 00f567b3 or a5,a0,a5 +800109b4: 00d7fa63 bgeu a5,a3,800109c8 <__umoddi3+0xd0> +800109b8: 011787b3 add a5,a5,a7 +800109bc: 0117e663 bltu a5,a7,800109c8 <__umoddi3+0xd0> +800109c0: 00d7f463 bgeu a5,a3,800109c8 <__umoddi3+0xd0> 800109c4: 011787b3 add a5,a5,a7 -800109c8: 0117e663 bltu a5,a7,800109d4 <__umoddi3+0x1a0> -800109cc: 00b7f463 bgeu a5,a1,800109d4 <__umoddi3+0x1a0> -800109d0: 011787b3 add a5,a5,a7 -800109d4: 40b787b3 sub a5,a5,a1 -800109d8: f31ff06f j 80010908 <__umoddi3+0xd4> -800109dc: 01000637 lui a2,0x1000 -800109e0: 01000713 li a4,16 -800109e4: f6c8e2e3 bltu a7,a2,80010948 <__umoddi3+0x114> -800109e8: 01800713 li a4,24 -800109ec: f5dff06f j 80010948 <__umoddi3+0x114> -800109f0: 006898b3 sll a7,a7,t1 -800109f4: 01c5d733 srl a4,a1,t3 -800109f8: 006517b3 sll a5,a0,t1 -800109fc: 01c55e33 srl t3,a0,t3 -80010a00: 0108d513 srli a0,a7,0x10 -80010a04: 02a776b3 remu a3,a4,a0 -80010a08: 006595b3 sll a1,a1,t1 -80010a0c: 00be6e33 or t3,t3,a1 -80010a10: 01089593 slli a1,a7,0x10 -80010a14: 0105d593 srli a1,a1,0x10 -80010a18: 010e5613 srli a2,t3,0x10 -80010a1c: 02a75733 divu a4,a4,a0 -80010a20: 01069693 slli a3,a3,0x10 -80010a24: 00c6e6b3 or a3,a3,a2 -80010a28: 02e58733 mul a4,a1,a4 -80010a2c: 00e6fa63 bgeu a3,a4,80010a40 <__umoddi3+0x20c> -80010a30: 011686b3 add a3,a3,a7 -80010a34: 0116e663 bltu a3,a7,80010a40 <__umoddi3+0x20c> -80010a38: 00e6f463 bgeu a3,a4,80010a40 <__umoddi3+0x20c> -80010a3c: 011686b3 add a3,a3,a7 -80010a40: 40e68633 sub a2,a3,a4 -80010a44: 02a676b3 remu a3,a2,a0 -80010a48: 010e1e13 slli t3,t3,0x10 -80010a4c: 010e5e13 srli t3,t3,0x10 -80010a50: 02a65633 divu a2,a2,a0 -80010a54: 01069693 slli a3,a3,0x10 -80010a58: 02c58633 mul a2,a1,a2 -80010a5c: 01c6e5b3 or a1,a3,t3 -80010a60: 00c5fa63 bgeu a1,a2,80010a74 <__umoddi3+0x240> -80010a64: 011585b3 add a1,a1,a7 -80010a68: 0115e663 bltu a1,a7,80010a74 <__umoddi3+0x240> -80010a6c: 00c5f463 bgeu a1,a2,80010a74 <__umoddi3+0x240> -80010a70: 011585b3 add a1,a1,a7 -80010a74: 40c585b3 sub a1,a1,a2 -80010a78: ef1ff06f j 80010968 <__umoddi3+0x134> -80010a7c: e8d5eae3 bltu a1,a3,80010910 <__umoddi3+0xdc> -80010a80: 00010737 lui a4,0x10 -80010a84: 04e6fc63 bgeu a3,a4,80010adc <__umoddi3+0x2a8> -80010a88: 0ff00e13 li t3,255 -80010a8c: 00de3733 sltu a4,t3,a3 -80010a90: 00371713 slli a4,a4,0x3 -80010a94: 800158b7 lui a7,0x80015 -80010a98: 00e6d333 srl t1,a3,a4 -80010a9c: 7fc88893 addi a7,a7,2044 # 800157fc <__BSS_END__+0xffffebcc> -80010aa0: 006888b3 add a7,a7,t1 -80010aa4: 0008ce03 lbu t3,0(a7) -80010aa8: 00ee0e33 add t3,t3,a4 -80010aac: 02000713 li a4,32 -80010ab0: 41c70333 sub t1,a4,t3 -80010ab4: 03c71e63 bne a4,t3,80010af0 <__umoddi3+0x2bc> -80010ab8: 00b6e463 bltu a3,a1,80010ac0 <__umoddi3+0x28c> -80010abc: 00c56a63 bltu a0,a2,80010ad0 <__umoddi3+0x29c> -80010ac0: 40c507b3 sub a5,a0,a2 -80010ac4: 40d585b3 sub a1,a1,a3 -80010ac8: 00f53533 sltu a0,a0,a5 -80010acc: 40a58833 sub a6,a1,a0 -80010ad0: 00078513 mv a0,a5 -80010ad4: 00080593 mv a1,a6 -80010ad8: e39ff06f j 80010910 <__umoddi3+0xdc> -80010adc: 010008b7 lui a7,0x1000 -80010ae0: 01000713 li a4,16 -80010ae4: fb16e8e3 bltu a3,a7,80010a94 <__umoddi3+0x260> -80010ae8: 01800713 li a4,24 -80010aec: fa9ff06f j 80010a94 <__umoddi3+0x260> -80010af0: 01c65733 srl a4,a2,t3 -80010af4: 006696b3 sll a3,a3,t1 -80010af8: 00d76f33 or t5,a4,a3 -80010afc: 01c5d7b3 srl a5,a1,t3 -80010b00: 010f5713 srli a4,t5,0x10 -80010b04: 02e7f8b3 remu a7,a5,a4 -80010b08: 006595b3 sll a1,a1,t1 -80010b0c: 01c55833 srl a6,a0,t3 -80010b10: 00b86833 or a6,a6,a1 -80010b14: 010f1593 slli a1,t5,0x10 -80010b18: 0105d593 srli a1,a1,0x10 -80010b1c: 01085693 srli a3,a6,0x10 -80010b20: 00661633 sll a2,a2,t1 -80010b24: 00651533 sll a0,a0,t1 -80010b28: 02e7d7b3 divu a5,a5,a4 -80010b2c: 01089893 slli a7,a7,0x10 -80010b30: 00d8e6b3 or a3,a7,a3 -80010b34: 02f58eb3 mul t4,a1,a5 -80010b38: 00078893 mv a7,a5 -80010b3c: 01d6fe63 bgeu a3,t4,80010b58 <__umoddi3+0x324> -80010b40: 01e686b3 add a3,a3,t5 -80010b44: fff78893 addi a7,a5,-1 -80010b48: 01e6e863 bltu a3,t5,80010b58 <__umoddi3+0x324> -80010b4c: 01d6f663 bgeu a3,t4,80010b58 <__umoddi3+0x324> -80010b50: ffe78893 addi a7,a5,-2 -80010b54: 01e686b3 add a3,a3,t5 -80010b58: 41d686b3 sub a3,a3,t4 -80010b5c: 02e6feb3 remu t4,a3,a4 -80010b60: 01081813 slli a6,a6,0x10 -80010b64: 01085813 srli a6,a6,0x10 -80010b68: 02e6d6b3 divu a3,a3,a4 -80010b6c: 010e9e93 slli t4,t4,0x10 -80010b70: 010eeeb3 or t4,t4,a6 -80010b74: 02d585b3 mul a1,a1,a3 -80010b78: 00068793 mv a5,a3 -80010b7c: 00befe63 bgeu t4,a1,80010b98 <__umoddi3+0x364> -80010b80: 01ee8eb3 add t4,t4,t5 -80010b84: fff68793 addi a5,a3,-1 -80010b88: 01eee863 bltu t4,t5,80010b98 <__umoddi3+0x364> -80010b8c: 00bef663 bgeu t4,a1,80010b98 <__umoddi3+0x364> -80010b90: ffe68793 addi a5,a3,-2 -80010b94: 01ee8eb3 add t4,t4,t5 -80010b98: 40be85b3 sub a1,t4,a1 -80010b9c: 01089893 slli a7,a7,0x10 -80010ba0: 00010eb7 lui t4,0x10 -80010ba4: 00f8e8b3 or a7,a7,a5 -80010ba8: fffe8793 addi a5,t4,-1 # ffff <_start-0x7fff0001> -80010bac: 00f8f833 and a6,a7,a5 -80010bb0: 01065693 srli a3,a2,0x10 -80010bb4: 0108d893 srli a7,a7,0x10 -80010bb8: 00f677b3 and a5,a2,a5 -80010bbc: 02f80733 mul a4,a6,a5 -80010bc0: 02f887b3 mul a5,a7,a5 -80010bc4: 02d80833 mul a6,a6,a3 -80010bc8: 02d888b3 mul a7,a7,a3 -80010bcc: 00f80833 add a6,a6,a5 -80010bd0: 01075693 srli a3,a4,0x10 -80010bd4: 010686b3 add a3,a3,a6 -80010bd8: 00f6f463 bgeu a3,a5,80010be0 <__umoddi3+0x3ac> -80010bdc: 01d888b3 add a7,a7,t4 -80010be0: 000107b7 lui a5,0x10 -80010be4: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -80010be8: 0106d813 srli a6,a3,0x10 -80010bec: 00f6f6b3 and a3,a3,a5 -80010bf0: 01069693 slli a3,a3,0x10 -80010bf4: 00f77733 and a4,a4,a5 -80010bf8: 011808b3 add a7,a6,a7 -80010bfc: 00e68733 add a4,a3,a4 -80010c00: 0115e663 bltu a1,a7,80010c0c <__umoddi3+0x3d8> -80010c04: 01159e63 bne a1,a7,80010c20 <__umoddi3+0x3ec> -80010c08: 00e57c63 bgeu a0,a4,80010c20 <__umoddi3+0x3ec> -80010c0c: 40c70633 sub a2,a4,a2 -80010c10: 00c73733 sltu a4,a4,a2 -80010c14: 01e70733 add a4,a4,t5 -80010c18: 40e888b3 sub a7,a7,a4 -80010c1c: 00060713 mv a4,a2 -80010c20: 40e50733 sub a4,a0,a4 -80010c24: 00e53533 sltu a0,a0,a4 -80010c28: 411585b3 sub a1,a1,a7 -80010c2c: 40a585b3 sub a1,a1,a0 -80010c30: 01c597b3 sll a5,a1,t3 -80010c34: 00675733 srl a4,a4,t1 -80010c38: 00e7e533 or a0,a5,a4 -80010c3c: 0065d5b3 srl a1,a1,t1 -80010c40: cd1ff06f j 80010910 <__umoddi3+0xdc> +800109c8: 40d787b3 sub a5,a5,a3 +800109cc: 0067d533 srl a0,a5,t1 +800109d0: 00000593 li a1,0 +800109d4: 00008067 ret +800109d8: 01000337 lui t1,0x1000 +800109dc: 01000713 li a4,16 +800109e0: f46666e3 bltu a2,t1,8001092c <__umoddi3+0x34> +800109e4: 01800713 li a4,24 +800109e8: f45ff06f j 8001092c <__umoddi3+0x34> +800109ec: 00061663 bnez a2,800109f8 <__umoddi3+0x100> +800109f0: 00100613 li a2,1 +800109f4: 031658b3 divu a7,a2,a7 +800109f8: 00010637 lui a2,0x10 +800109fc: 0ac8f263 bgeu a7,a2,80010aa0 <__umoddi3+0x1a8> +80010a00: 0ff00613 li a2,255 +80010a04: 01167463 bgeu a2,a7,80010a0c <__umoddi3+0x114> +80010a08: 00800713 li a4,8 +80010a0c: 00e8d633 srl a2,a7,a4 +80010a10: 00c686b3 add a3,a3,a2 +80010a14: 0006ce03 lbu t3,0(a3) +80010a18: 00ee0e33 add t3,t3,a4 +80010a1c: 02000713 li a4,32 +80010a20: 41c70333 sub t1,a4,t3 +80010a24: 09c71863 bne a4,t3,80010ab4 <__umoddi3+0x1bc> +80010a28: 411585b3 sub a1,a1,a7 +80010a2c: 0108d713 srli a4,a7,0x10 +80010a30: 01089513 slli a0,a7,0x10 +80010a34: 01055513 srli a0,a0,0x10 +80010a38: 0107d613 srli a2,a5,0x10 +80010a3c: 02e5f6b3 remu a3,a1,a4 +80010a40: 02e5d5b3 divu a1,a1,a4 +80010a44: 01069693 slli a3,a3,0x10 +80010a48: 00c6e6b3 or a3,a3,a2 +80010a4c: 02b505b3 mul a1,a0,a1 +80010a50: 00b6fa63 bgeu a3,a1,80010a64 <__umoddi3+0x16c> +80010a54: 011686b3 add a3,a3,a7 +80010a58: 0116e663 bltu a3,a7,80010a64 <__umoddi3+0x16c> +80010a5c: 00b6f463 bgeu a3,a1,80010a64 <__umoddi3+0x16c> +80010a60: 011686b3 add a3,a3,a7 +80010a64: 40b685b3 sub a1,a3,a1 +80010a68: 02e5f6b3 remu a3,a1,a4 +80010a6c: 01079793 slli a5,a5,0x10 +80010a70: 0107d793 srli a5,a5,0x10 +80010a74: 02e5d5b3 divu a1,a1,a4 +80010a78: 02b505b3 mul a1,a0,a1 +80010a7c: 01069513 slli a0,a3,0x10 +80010a80: 00f567b3 or a5,a0,a5 +80010a84: 00b7fa63 bgeu a5,a1,80010a98 <__umoddi3+0x1a0> +80010a88: 011787b3 add a5,a5,a7 +80010a8c: 0117e663 bltu a5,a7,80010a98 <__umoddi3+0x1a0> +80010a90: 00b7f463 bgeu a5,a1,80010a98 <__umoddi3+0x1a0> +80010a94: 011787b3 add a5,a5,a7 +80010a98: 40b787b3 sub a5,a5,a1 +80010a9c: f31ff06f j 800109cc <__umoddi3+0xd4> +80010aa0: 01000637 lui a2,0x1000 +80010aa4: 01000713 li a4,16 +80010aa8: f6c8e2e3 bltu a7,a2,80010a0c <__umoddi3+0x114> +80010aac: 01800713 li a4,24 +80010ab0: f5dff06f j 80010a0c <__umoddi3+0x114> +80010ab4: 006898b3 sll a7,a7,t1 +80010ab8: 01c5d733 srl a4,a1,t3 +80010abc: 006517b3 sll a5,a0,t1 +80010ac0: 01c55e33 srl t3,a0,t3 +80010ac4: 0108d513 srli a0,a7,0x10 +80010ac8: 02a776b3 remu a3,a4,a0 +80010acc: 006595b3 sll a1,a1,t1 +80010ad0: 00be6e33 or t3,t3,a1 +80010ad4: 01089593 slli a1,a7,0x10 +80010ad8: 0105d593 srli a1,a1,0x10 +80010adc: 010e5613 srli a2,t3,0x10 +80010ae0: 02a75733 divu a4,a4,a0 +80010ae4: 01069693 slli a3,a3,0x10 +80010ae8: 00c6e6b3 or a3,a3,a2 +80010aec: 02e58733 mul a4,a1,a4 +80010af0: 00e6fa63 bgeu a3,a4,80010b04 <__umoddi3+0x20c> +80010af4: 011686b3 add a3,a3,a7 +80010af8: 0116e663 bltu a3,a7,80010b04 <__umoddi3+0x20c> +80010afc: 00e6f463 bgeu a3,a4,80010b04 <__umoddi3+0x20c> +80010b00: 011686b3 add a3,a3,a7 +80010b04: 40e68633 sub a2,a3,a4 +80010b08: 02a676b3 remu a3,a2,a0 +80010b0c: 010e1e13 slli t3,t3,0x10 +80010b10: 010e5e13 srli t3,t3,0x10 +80010b14: 02a65633 divu a2,a2,a0 +80010b18: 01069693 slli a3,a3,0x10 +80010b1c: 02c58633 mul a2,a1,a2 +80010b20: 01c6e5b3 or a1,a3,t3 +80010b24: 00c5fa63 bgeu a1,a2,80010b38 <__umoddi3+0x240> +80010b28: 011585b3 add a1,a1,a7 +80010b2c: 0115e663 bltu a1,a7,80010b38 <__umoddi3+0x240> +80010b30: 00c5f463 bgeu a1,a2,80010b38 <__umoddi3+0x240> +80010b34: 011585b3 add a1,a1,a7 +80010b38: 40c585b3 sub a1,a1,a2 +80010b3c: ef1ff06f j 80010a2c <__umoddi3+0x134> +80010b40: e8d5eae3 bltu a1,a3,800109d4 <__umoddi3+0xdc> +80010b44: 00010737 lui a4,0x10 +80010b48: 04e6fc63 bgeu a3,a4,80010ba0 <__umoddi3+0x2a8> +80010b4c: 0ff00e13 li t3,255 +80010b50: 00de3733 sltu a4,t3,a3 +80010b54: 00371713 slli a4,a4,0x3 +80010b58: 800168b7 lui a7,0x80016 +80010b5c: 00e6d333 srl t1,a3,a4 +80010b60: 84c88893 addi a7,a7,-1972 # 8001584c <__BSS_END__+0xffffec10> +80010b64: 006888b3 add a7,a7,t1 +80010b68: 0008ce03 lbu t3,0(a7) +80010b6c: 00ee0e33 add t3,t3,a4 +80010b70: 02000713 li a4,32 +80010b74: 41c70333 sub t1,a4,t3 +80010b78: 03c71e63 bne a4,t3,80010bb4 <__umoddi3+0x2bc> +80010b7c: 00b6e463 bltu a3,a1,80010b84 <__umoddi3+0x28c> +80010b80: 00c56a63 bltu a0,a2,80010b94 <__umoddi3+0x29c> +80010b84: 40c507b3 sub a5,a0,a2 +80010b88: 40d585b3 sub a1,a1,a3 +80010b8c: 00f53533 sltu a0,a0,a5 +80010b90: 40a58833 sub a6,a1,a0 +80010b94: 00078513 mv a0,a5 +80010b98: 00080593 mv a1,a6 +80010b9c: e39ff06f j 800109d4 <__umoddi3+0xdc> +80010ba0: 010008b7 lui a7,0x1000 +80010ba4: 01000713 li a4,16 +80010ba8: fb16e8e3 bltu a3,a7,80010b58 <__umoddi3+0x260> +80010bac: 01800713 li a4,24 +80010bb0: fa9ff06f j 80010b58 <__umoddi3+0x260> +80010bb4: 01c65733 srl a4,a2,t3 +80010bb8: 006696b3 sll a3,a3,t1 +80010bbc: 00d76f33 or t5,a4,a3 +80010bc0: 01c5d7b3 srl a5,a1,t3 +80010bc4: 010f5713 srli a4,t5,0x10 +80010bc8: 02e7f8b3 remu a7,a5,a4 +80010bcc: 006595b3 sll a1,a1,t1 +80010bd0: 01c55833 srl a6,a0,t3 +80010bd4: 00b86833 or a6,a6,a1 +80010bd8: 010f1593 slli a1,t5,0x10 +80010bdc: 0105d593 srli a1,a1,0x10 +80010be0: 01085693 srli a3,a6,0x10 +80010be4: 00661633 sll a2,a2,t1 +80010be8: 00651533 sll a0,a0,t1 +80010bec: 02e7d7b3 divu a5,a5,a4 +80010bf0: 01089893 slli a7,a7,0x10 +80010bf4: 00d8e6b3 or a3,a7,a3 +80010bf8: 02f58eb3 mul t4,a1,a5 +80010bfc: 00078893 mv a7,a5 +80010c00: 01d6fe63 bgeu a3,t4,80010c1c <__umoddi3+0x324> +80010c04: 01e686b3 add a3,a3,t5 +80010c08: fff78893 addi a7,a5,-1 +80010c0c: 01e6e863 bltu a3,t5,80010c1c <__umoddi3+0x324> +80010c10: 01d6f663 bgeu a3,t4,80010c1c <__umoddi3+0x324> +80010c14: ffe78893 addi a7,a5,-2 +80010c18: 01e686b3 add a3,a3,t5 +80010c1c: 41d686b3 sub a3,a3,t4 +80010c20: 02e6feb3 remu t4,a3,a4 +80010c24: 01081813 slli a6,a6,0x10 +80010c28: 01085813 srli a6,a6,0x10 +80010c2c: 02e6d6b3 divu a3,a3,a4 +80010c30: 010e9e93 slli t4,t4,0x10 +80010c34: 010eeeb3 or t4,t4,a6 +80010c38: 02d585b3 mul a1,a1,a3 +80010c3c: 00068793 mv a5,a3 +80010c40: 00befe63 bgeu t4,a1,80010c5c <__umoddi3+0x364> +80010c44: 01ee8eb3 add t4,t4,t5 +80010c48: fff68793 addi a5,a3,-1 +80010c4c: 01eee863 bltu t4,t5,80010c5c <__umoddi3+0x364> +80010c50: 00bef663 bgeu t4,a1,80010c5c <__umoddi3+0x364> +80010c54: ffe68793 addi a5,a3,-2 +80010c58: 01ee8eb3 add t4,t4,t5 +80010c5c: 40be85b3 sub a1,t4,a1 +80010c60: 01089893 slli a7,a7,0x10 +80010c64: 00010eb7 lui t4,0x10 +80010c68: 00f8e8b3 or a7,a7,a5 +80010c6c: fffe8793 addi a5,t4,-1 # ffff <_start-0x7fff0001> +80010c70: 00f8f833 and a6,a7,a5 +80010c74: 01065693 srli a3,a2,0x10 +80010c78: 0108d893 srli a7,a7,0x10 +80010c7c: 00f677b3 and a5,a2,a5 +80010c80: 02f80733 mul a4,a6,a5 +80010c84: 02f887b3 mul a5,a7,a5 +80010c88: 02d80833 mul a6,a6,a3 +80010c8c: 02d888b3 mul a7,a7,a3 +80010c90: 00f80833 add a6,a6,a5 +80010c94: 01075693 srli a3,a4,0x10 +80010c98: 010686b3 add a3,a3,a6 +80010c9c: 00f6f463 bgeu a3,a5,80010ca4 <__umoddi3+0x3ac> +80010ca0: 01d888b3 add a7,a7,t4 +80010ca4: 000107b7 lui a5,0x10 +80010ca8: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +80010cac: 0106d813 srli a6,a3,0x10 +80010cb0: 00f6f6b3 and a3,a3,a5 +80010cb4: 01069693 slli a3,a3,0x10 +80010cb8: 00f77733 and a4,a4,a5 +80010cbc: 011808b3 add a7,a6,a7 +80010cc0: 00e68733 add a4,a3,a4 +80010cc4: 0115e663 bltu a1,a7,80010cd0 <__umoddi3+0x3d8> +80010cc8: 01159e63 bne a1,a7,80010ce4 <__umoddi3+0x3ec> +80010ccc: 00e57c63 bgeu a0,a4,80010ce4 <__umoddi3+0x3ec> +80010cd0: 40c70633 sub a2,a4,a2 +80010cd4: 00c73733 sltu a4,a4,a2 +80010cd8: 01e70733 add a4,a4,t5 +80010cdc: 40e888b3 sub a7,a7,a4 +80010ce0: 00060713 mv a4,a2 +80010ce4: 40e50733 sub a4,a0,a4 +80010ce8: 00e53533 sltu a0,a0,a4 +80010cec: 411585b3 sub a1,a1,a7 +80010cf0: 40a585b3 sub a1,a1,a0 +80010cf4: 01c597b3 sll a5,a1,t3 +80010cf8: 00675733 srl a4,a4,t1 +80010cfc: 00e7e533 or a0,a5,a4 +80010d00: 0065d5b3 srl a1,a1,t1 +80010d04: cd1ff06f j 800109d4 <__umoddi3+0xdc> -80010c44 <__divdf3>: -80010c44: fd010113 addi sp,sp,-48 -80010c48: 0145d793 srli a5,a1,0x14 -80010c4c: 02912223 sw s1,36(sp) -80010c50: 03212023 sw s2,32(sp) -80010c54: 01412c23 sw s4,24(sp) -80010c58: 01612823 sw s6,16(sp) -80010c5c: 01812423 sw s8,8(sp) -80010c60: 00c59493 slli s1,a1,0xc -80010c64: 02112623 sw ra,44(sp) -80010c68: 02812423 sw s0,40(sp) -80010c6c: 01312e23 sw s3,28(sp) -80010c70: 01512a23 sw s5,20(sp) -80010c74: 01712623 sw s7,12(sp) -80010c78: 01579713 slli a4,a5,0x15 -80010c7c: 00050913 mv s2,a0 -80010c80: 00060b13 mv s6,a2 -80010c84: 00068c13 mv s8,a3 -80010c88: 00c4d493 srli s1,s1,0xc -80010c8c: 01f5da13 srli s4,a1,0x1f -80010c90: 0a070463 beqz a4,80010d38 <__divdf3+0xf4> -80010c94: 7ff7fa93 andi s5,a5,2047 -80010c98: 7ff00793 li a5,2047 -80010c9c: 10fa8063 beq s5,a5,80010d9c <__divdf3+0x158> -80010ca0: 01d55993 srli s3,a0,0x1d -80010ca4: 00349493 slli s1,s1,0x3 -80010ca8: 0099e4b3 or s1,s3,s1 -80010cac: 008009b7 lui s3,0x800 -80010cb0: 0134e9b3 or s3,s1,s3 -80010cb4: 00351413 slli s0,a0,0x3 -80010cb8: c01a8a93 addi s5,s5,-1023 -80010cbc: 00000b93 li s7,0 -80010cc0: 014c5793 srli a5,s8,0x14 -80010cc4: 00cc1513 slli a0,s8,0xc -80010cc8: 01579713 slli a4,a5,0x15 -80010ccc: 00c55493 srli s1,a0,0xc -80010cd0: 7ff7f593 andi a1,a5,2047 -80010cd4: 01fc5c13 srli s8,s8,0x1f -80010cd8: 10070063 beqz a4,80010dd8 <__divdf3+0x194> -80010cdc: 7ff00793 li a5,2047 -80010ce0: 16f58263 beq a1,a5,80010e44 <__divdf3+0x200> -80010ce4: 00349513 slli a0,s1,0x3 -80010ce8: 01db5793 srli a5,s6,0x1d -80010cec: 00a7e533 or a0,a5,a0 -80010cf0: 008004b7 lui s1,0x800 -80010cf4: 009564b3 or s1,a0,s1 -80010cf8: 003b1f93 slli t6,s6,0x3 -80010cfc: c0158513 addi a0,a1,-1023 -80010d00: 00000613 li a2,0 -80010d04: 002b9793 slli a5,s7,0x2 -80010d08: 00c7e7b3 or a5,a5,a2 -80010d0c: fff78793 addi a5,a5,-1 -80010d10: 00e00713 li a4,14 -80010d14: 018a46b3 xor a3,s4,s8 -80010d18: 40aa85b3 sub a1,s5,a0 -80010d1c: 16f76063 bltu a4,a5,80010e7c <__divdf3+0x238> -80010d20: 80015737 lui a4,0x80015 -80010d24: 00279793 slli a5,a5,0x2 -80010d28: 74870713 addi a4,a4,1864 # 80015748 <__BSS_END__+0xffffeb18> -80010d2c: 00e787b3 add a5,a5,a4 -80010d30: 0007a783 lw a5,0(a5) -80010d34: 00078067 jr a5 -80010d38: 00a4e9b3 or s3,s1,a0 -80010d3c: 06098e63 beqz s3,80010db8 <__divdf3+0x174> -80010d40: 04048063 beqz s1,80010d80 <__divdf3+0x13c> -80010d44: 00048513 mv a0,s1 -80010d48: 3bd030ef jal ra,80014904 <__clzsi2> -80010d4c: ff550793 addi a5,a0,-11 -80010d50: 01c00713 li a4,28 -80010d54: 02f74c63 blt a4,a5,80010d8c <__divdf3+0x148> -80010d58: 01d00993 li s3,29 -80010d5c: ff850413 addi s0,a0,-8 -80010d60: 40f989b3 sub s3,s3,a5 -80010d64: 008494b3 sll s1,s1,s0 -80010d68: 013959b3 srl s3,s2,s3 -80010d6c: 0099e9b3 or s3,s3,s1 -80010d70: 00891433 sll s0,s2,s0 -80010d74: c0d00593 li a1,-1011 -80010d78: 40a58ab3 sub s5,a1,a0 -80010d7c: f41ff06f j 80010cbc <__divdf3+0x78> -80010d80: 385030ef jal ra,80014904 <__clzsi2> -80010d84: 02050513 addi a0,a0,32 -80010d88: fc5ff06f j 80010d4c <__divdf3+0x108> -80010d8c: fd850493 addi s1,a0,-40 -80010d90: 009919b3 sll s3,s2,s1 -80010d94: 00000413 li s0,0 -80010d98: fddff06f j 80010d74 <__divdf3+0x130> -80010d9c: 00a4e9b3 or s3,s1,a0 -80010da0: 02098463 beqz s3,80010dc8 <__divdf3+0x184> -80010da4: 00050413 mv s0,a0 -80010da8: 00048993 mv s3,s1 -80010dac: 7ff00a93 li s5,2047 -80010db0: 00300b93 li s7,3 -80010db4: f0dff06f j 80010cc0 <__divdf3+0x7c> -80010db8: 00000413 li s0,0 -80010dbc: 00000a93 li s5,0 -80010dc0: 00100b93 li s7,1 -80010dc4: efdff06f j 80010cc0 <__divdf3+0x7c> -80010dc8: 00000413 li s0,0 -80010dcc: 7ff00a93 li s5,2047 -80010dd0: 00200b93 li s7,2 -80010dd4: eedff06f j 80010cc0 <__divdf3+0x7c> -80010dd8: 0164efb3 or t6,s1,s6 -80010ddc: 080f8063 beqz t6,80010e5c <__divdf3+0x218> -80010de0: 04048263 beqz s1,80010e24 <__divdf3+0x1e0> -80010de4: 00048513 mv a0,s1 -80010de8: 31d030ef jal ra,80014904 <__clzsi2> -80010dec: 00050593 mv a1,a0 -80010df0: ff558793 addi a5,a1,-11 -80010df4: 01c00713 li a4,28 -80010df8: 02f74e63 blt a4,a5,80010e34 <__divdf3+0x1f0> -80010dfc: 01d00693 li a3,29 -80010e00: ff858f93 addi t6,a1,-8 -80010e04: 40f686b3 sub a3,a3,a5 -80010e08: 01f49533 sll a0,s1,t6 -80010e0c: 00db56b3 srl a3,s6,a3 -80010e10: 00a6e4b3 or s1,a3,a0 -80010e14: 01fb1fb3 sll t6,s6,t6 -80010e18: c0d00713 li a4,-1011 -80010e1c: 40b70533 sub a0,a4,a1 -80010e20: ee1ff06f j 80010d00 <__divdf3+0xbc> -80010e24: 000b0513 mv a0,s6 -80010e28: 2dd030ef jal ra,80014904 <__clzsi2> -80010e2c: 02050593 addi a1,a0,32 -80010e30: fc1ff06f j 80010df0 <__divdf3+0x1ac> -80010e34: fd858513 addi a0,a1,-40 -80010e38: 00ab14b3 sll s1,s6,a0 -80010e3c: 00000f93 li t6,0 -80010e40: fd9ff06f j 80010e18 <__divdf3+0x1d4> -80010e44: 0164efb3 or t6,s1,s6 -80010e48: 020f8263 beqz t6,80010e6c <__divdf3+0x228> -80010e4c: 000b0f93 mv t6,s6 -80010e50: 7ff00513 li a0,2047 -80010e54: 00300613 li a2,3 -80010e58: eadff06f j 80010d04 <__divdf3+0xc0> -80010e5c: 00000493 li s1,0 -80010e60: 00000513 li a0,0 -80010e64: 00100613 li a2,1 -80010e68: e9dff06f j 80010d04 <__divdf3+0xc0> -80010e6c: 00000493 li s1,0 -80010e70: 7ff00513 li a0,2047 -80010e74: 00200613 li a2,2 -80010e78: e8dff06f j 80010d04 <__divdf3+0xc0> -80010e7c: 0134e663 bltu s1,s3,80010e88 <__divdf3+0x244> -80010e80: 34999c63 bne s3,s1,800111d8 <__divdf3+0x594> -80010e84: 35f46a63 bltu s0,t6,800111d8 <__divdf3+0x594> -80010e88: 01f99613 slli a2,s3,0x1f -80010e8c: 00145713 srli a4,s0,0x1 -80010e90: 01f41793 slli a5,s0,0x1f -80010e94: 0019d993 srli s3,s3,0x1 -80010e98: 00e66433 or s0,a2,a4 -80010e9c: 00849513 slli a0,s1,0x8 -80010ea0: 018fd893 srli a7,t6,0x18 -80010ea4: 00a8e8b3 or a7,a7,a0 -80010ea8: 01055513 srli a0,a0,0x10 -80010eac: 02a9d833 divu a6,s3,a0 -80010eb0: 01089e93 slli t4,a7,0x10 -80010eb4: 010ede93 srli t4,t4,0x10 -80010eb8: 01045713 srli a4,s0,0x10 -80010ebc: 008f9313 slli t1,t6,0x8 -80010ec0: 02a9f4b3 remu s1,s3,a0 -80010ec4: 00080f93 mv t6,a6 -80010ec8: 030e8633 mul a2,t4,a6 -80010ecc: 01049993 slli s3,s1,0x10 -80010ed0: 01376733 or a4,a4,s3 -80010ed4: 00c77e63 bgeu a4,a2,80010ef0 <__divdf3+0x2ac> -80010ed8: 01170733 add a4,a4,a7 -80010edc: fff80f93 addi t6,a6,-1 -80010ee0: 01176863 bltu a4,a7,80010ef0 <__divdf3+0x2ac> -80010ee4: 00c77663 bgeu a4,a2,80010ef0 <__divdf3+0x2ac> -80010ee8: ffe80f93 addi t6,a6,-2 -80010eec: 01170733 add a4,a4,a7 -80010ef0: 40c70733 sub a4,a4,a2 -80010ef4: 02a75e33 divu t3,a4,a0 -80010ef8: 01041413 slli s0,s0,0x10 -80010efc: 01045413 srli s0,s0,0x10 -80010f00: 02a77733 remu a4,a4,a0 -80010f04: 000e0613 mv a2,t3 -80010f08: 03ce8833 mul a6,t4,t3 -80010f0c: 01071713 slli a4,a4,0x10 -80010f10: 00e46733 or a4,s0,a4 -80010f14: 01077e63 bgeu a4,a6,80010f30 <__divdf3+0x2ec> -80010f18: 01170733 add a4,a4,a7 -80010f1c: fffe0613 addi a2,t3,-1 -80010f20: 01176863 bltu a4,a7,80010f30 <__divdf3+0x2ec> -80010f24: 01077663 bgeu a4,a6,80010f30 <__divdf3+0x2ec> -80010f28: ffee0613 addi a2,t3,-2 -80010f2c: 01170733 add a4,a4,a7 -80010f30: 41070433 sub s0,a4,a6 -80010f34: 010f9f93 slli t6,t6,0x10 -80010f38: 00010837 lui a6,0x10 -80010f3c: 00cfefb3 or t6,t6,a2 -80010f40: fff80e13 addi t3,a6,-1 # ffff <_start-0x7fff0001> -80010f44: 010fd613 srli a2,t6,0x10 -80010f48: 01cff733 and a4,t6,t3 -80010f4c: 01035f13 srli t5,t1,0x10 -80010f50: 01c37e33 and t3,t1,t3 -80010f54: 02ee03b3 mul t2,t3,a4 -80010f58: 03c604b3 mul s1,a2,t3 -80010f5c: 02ef0733 mul a4,t5,a4 -80010f60: 03e602b3 mul t0,a2,t5 -80010f64: 00970633 add a2,a4,s1 -80010f68: 0103d713 srli a4,t2,0x10 -80010f6c: 00c70733 add a4,a4,a2 -80010f70: 00977463 bgeu a4,s1,80010f78 <__divdf3+0x334> -80010f74: 010282b3 add t0,t0,a6 -80010f78: 01075613 srli a2,a4,0x10 -80010f7c: 00560633 add a2,a2,t0 -80010f80: 000102b7 lui t0,0x10 -80010f84: fff28293 addi t0,t0,-1 # ffff <_start-0x7fff0001> -80010f88: 00577833 and a6,a4,t0 -80010f8c: 01081813 slli a6,a6,0x10 -80010f90: 0053f3b3 and t2,t2,t0 -80010f94: 00780833 add a6,a6,t2 -80010f98: 00c46863 bltu s0,a2,80010fa8 <__divdf3+0x364> -80010f9c: 000f8493 mv s1,t6 -80010fa0: 04c41463 bne s0,a2,80010fe8 <__divdf3+0x3a4> -80010fa4: 0507f263 bgeu a5,a6,80010fe8 <__divdf3+0x3a4> -80010fa8: 006787b3 add a5,a5,t1 -80010fac: 0067b733 sltu a4,a5,t1 +80010d08 <__divdf3>: +80010d08: fd010113 addi sp,sp,-48 +80010d0c: 0145d793 srli a5,a1,0x14 +80010d10: 02912223 sw s1,36(sp) +80010d14: 03212023 sw s2,32(sp) +80010d18: 01412c23 sw s4,24(sp) +80010d1c: 01612823 sw s6,16(sp) +80010d20: 01812423 sw s8,8(sp) +80010d24: 00c59493 slli s1,a1,0xc +80010d28: 02112623 sw ra,44(sp) +80010d2c: 02812423 sw s0,40(sp) +80010d30: 01312e23 sw s3,28(sp) +80010d34: 01512a23 sw s5,20(sp) +80010d38: 01712623 sw s7,12(sp) +80010d3c: 01579713 slli a4,a5,0x15 +80010d40: 00050913 mv s2,a0 +80010d44: 00060b13 mv s6,a2 +80010d48: 00068c13 mv s8,a3 +80010d4c: 00c4d493 srli s1,s1,0xc +80010d50: 01f5da13 srli s4,a1,0x1f +80010d54: 0a070463 beqz a4,80010dfc <__divdf3+0xf4> +80010d58: 7ff7fa93 andi s5,a5,2047 +80010d5c: 7ff00793 li a5,2047 +80010d60: 10fa8063 beq s5,a5,80010e60 <__divdf3+0x158> +80010d64: 01d55993 srli s3,a0,0x1d +80010d68: 00349493 slli s1,s1,0x3 +80010d6c: 0099e4b3 or s1,s3,s1 +80010d70: 008009b7 lui s3,0x800 +80010d74: 0134e9b3 or s3,s1,s3 +80010d78: 00351413 slli s0,a0,0x3 +80010d7c: c01a8a93 addi s5,s5,-1023 +80010d80: 00000b93 li s7,0 +80010d84: 014c5793 srli a5,s8,0x14 +80010d88: 00cc1513 slli a0,s8,0xc +80010d8c: 01579713 slli a4,a5,0x15 +80010d90: 00c55493 srli s1,a0,0xc +80010d94: 7ff7f593 andi a1,a5,2047 +80010d98: 01fc5c13 srli s8,s8,0x1f +80010d9c: 10070063 beqz a4,80010e9c <__divdf3+0x194> +80010da0: 7ff00793 li a5,2047 +80010da4: 16f58263 beq a1,a5,80010f08 <__divdf3+0x200> +80010da8: 00349513 slli a0,s1,0x3 +80010dac: 01db5793 srli a5,s6,0x1d +80010db0: 00a7e533 or a0,a5,a0 +80010db4: 008004b7 lui s1,0x800 +80010db8: 009564b3 or s1,a0,s1 +80010dbc: 003b1f93 slli t6,s6,0x3 +80010dc0: c0158513 addi a0,a1,-1023 +80010dc4: 00000613 li a2,0 +80010dc8: 002b9793 slli a5,s7,0x2 +80010dcc: 00c7e7b3 or a5,a5,a2 +80010dd0: fff78793 addi a5,a5,-1 +80010dd4: 00e00713 li a4,14 +80010dd8: 018a46b3 xor a3,s4,s8 +80010ddc: 40aa85b3 sub a1,s5,a0 +80010de0: 16f76063 bltu a4,a5,80010f40 <__divdf3+0x238> +80010de4: 80015737 lui a4,0x80015 +80010de8: 00279793 slli a5,a5,0x2 +80010dec: 79870713 addi a4,a4,1944 # 80015798 <__BSS_END__+0xffffeb5c> +80010df0: 00e787b3 add a5,a5,a4 +80010df4: 0007a783 lw a5,0(a5) +80010df8: 00078067 jr a5 +80010dfc: 00a4e9b3 or s3,s1,a0 +80010e00: 06098e63 beqz s3,80010e7c <__divdf3+0x174> +80010e04: 04048063 beqz s1,80010e44 <__divdf3+0x13c> +80010e08: 00048513 mv a0,s1 +80010e0c: 3bd030ef jal ra,800149c8 <__clzsi2> +80010e10: ff550793 addi a5,a0,-11 +80010e14: 01c00713 li a4,28 +80010e18: 02f74c63 blt a4,a5,80010e50 <__divdf3+0x148> +80010e1c: 01d00993 li s3,29 +80010e20: ff850413 addi s0,a0,-8 +80010e24: 40f989b3 sub s3,s3,a5 +80010e28: 008494b3 sll s1,s1,s0 +80010e2c: 013959b3 srl s3,s2,s3 +80010e30: 0099e9b3 or s3,s3,s1 +80010e34: 00891433 sll s0,s2,s0 +80010e38: c0d00593 li a1,-1011 +80010e3c: 40a58ab3 sub s5,a1,a0 +80010e40: f41ff06f j 80010d80 <__divdf3+0x78> +80010e44: 385030ef jal ra,800149c8 <__clzsi2> +80010e48: 02050513 addi a0,a0,32 +80010e4c: fc5ff06f j 80010e10 <__divdf3+0x108> +80010e50: fd850493 addi s1,a0,-40 +80010e54: 009919b3 sll s3,s2,s1 +80010e58: 00000413 li s0,0 +80010e5c: fddff06f j 80010e38 <__divdf3+0x130> +80010e60: 00a4e9b3 or s3,s1,a0 +80010e64: 02098463 beqz s3,80010e8c <__divdf3+0x184> +80010e68: 00050413 mv s0,a0 +80010e6c: 00048993 mv s3,s1 +80010e70: 7ff00a93 li s5,2047 +80010e74: 00300b93 li s7,3 +80010e78: f0dff06f j 80010d84 <__divdf3+0x7c> +80010e7c: 00000413 li s0,0 +80010e80: 00000a93 li s5,0 +80010e84: 00100b93 li s7,1 +80010e88: efdff06f j 80010d84 <__divdf3+0x7c> +80010e8c: 00000413 li s0,0 +80010e90: 7ff00a93 li s5,2047 +80010e94: 00200b93 li s7,2 +80010e98: eedff06f j 80010d84 <__divdf3+0x7c> +80010e9c: 0164efb3 or t6,s1,s6 +80010ea0: 080f8063 beqz t6,80010f20 <__divdf3+0x218> +80010ea4: 04048263 beqz s1,80010ee8 <__divdf3+0x1e0> +80010ea8: 00048513 mv a0,s1 +80010eac: 31d030ef jal ra,800149c8 <__clzsi2> +80010eb0: 00050593 mv a1,a0 +80010eb4: ff558793 addi a5,a1,-11 +80010eb8: 01c00713 li a4,28 +80010ebc: 02f74e63 blt a4,a5,80010ef8 <__divdf3+0x1f0> +80010ec0: 01d00693 li a3,29 +80010ec4: ff858f93 addi t6,a1,-8 +80010ec8: 40f686b3 sub a3,a3,a5 +80010ecc: 01f49533 sll a0,s1,t6 +80010ed0: 00db56b3 srl a3,s6,a3 +80010ed4: 00a6e4b3 or s1,a3,a0 +80010ed8: 01fb1fb3 sll t6,s6,t6 +80010edc: c0d00713 li a4,-1011 +80010ee0: 40b70533 sub a0,a4,a1 +80010ee4: ee1ff06f j 80010dc4 <__divdf3+0xbc> +80010ee8: 000b0513 mv a0,s6 +80010eec: 2dd030ef jal ra,800149c8 <__clzsi2> +80010ef0: 02050593 addi a1,a0,32 +80010ef4: fc1ff06f j 80010eb4 <__divdf3+0x1ac> +80010ef8: fd858513 addi a0,a1,-40 +80010efc: 00ab14b3 sll s1,s6,a0 +80010f00: 00000f93 li t6,0 +80010f04: fd9ff06f j 80010edc <__divdf3+0x1d4> +80010f08: 0164efb3 or t6,s1,s6 +80010f0c: 020f8263 beqz t6,80010f30 <__divdf3+0x228> +80010f10: 000b0f93 mv t6,s6 +80010f14: 7ff00513 li a0,2047 +80010f18: 00300613 li a2,3 +80010f1c: eadff06f j 80010dc8 <__divdf3+0xc0> +80010f20: 00000493 li s1,0 +80010f24: 00000513 li a0,0 +80010f28: 00100613 li a2,1 +80010f2c: e9dff06f j 80010dc8 <__divdf3+0xc0> +80010f30: 00000493 li s1,0 +80010f34: 7ff00513 li a0,2047 +80010f38: 00200613 li a2,2 +80010f3c: e8dff06f j 80010dc8 <__divdf3+0xc0> +80010f40: 0134e663 bltu s1,s3,80010f4c <__divdf3+0x244> +80010f44: 34999c63 bne s3,s1,8001129c <__divdf3+0x594> +80010f48: 35f46a63 bltu s0,t6,8001129c <__divdf3+0x594> +80010f4c: 01f99613 slli a2,s3,0x1f +80010f50: 00145713 srli a4,s0,0x1 +80010f54: 01f41793 slli a5,s0,0x1f +80010f58: 0019d993 srli s3,s3,0x1 +80010f5c: 00e66433 or s0,a2,a4 +80010f60: 00849513 slli a0,s1,0x8 +80010f64: 018fd893 srli a7,t6,0x18 +80010f68: 00a8e8b3 or a7,a7,a0 +80010f6c: 01055513 srli a0,a0,0x10 +80010f70: 02a9d833 divu a6,s3,a0 +80010f74: 01089e93 slli t4,a7,0x10 +80010f78: 010ede93 srli t4,t4,0x10 +80010f7c: 01045713 srli a4,s0,0x10 +80010f80: 008f9313 slli t1,t6,0x8 +80010f84: 02a9f4b3 remu s1,s3,a0 +80010f88: 00080f93 mv t6,a6 +80010f8c: 030e8633 mul a2,t4,a6 +80010f90: 01049993 slli s3,s1,0x10 +80010f94: 01376733 or a4,a4,s3 +80010f98: 00c77e63 bgeu a4,a2,80010fb4 <__divdf3+0x2ac> +80010f9c: 01170733 add a4,a4,a7 +80010fa0: fff80f93 addi t6,a6,-1 +80010fa4: 01176863 bltu a4,a7,80010fb4 <__divdf3+0x2ac> +80010fa8: 00c77663 bgeu a4,a2,80010fb4 <__divdf3+0x2ac> +80010fac: ffe80f93 addi t6,a6,-2 80010fb0: 01170733 add a4,a4,a7 -80010fb4: 00e40433 add s0,s0,a4 -80010fb8: ffff8493 addi s1,t6,-1 -80010fbc: 0088e663 bltu a7,s0,80010fc8 <__divdf3+0x384> -80010fc0: 02889463 bne a7,s0,80010fe8 <__divdf3+0x3a4> -80010fc4: 0267e263 bltu a5,t1,80010fe8 <__divdf3+0x3a4> -80010fc8: 00c46663 bltu s0,a2,80010fd4 <__divdf3+0x390> -80010fcc: 00861e63 bne a2,s0,80010fe8 <__divdf3+0x3a4> -80010fd0: 0107fc63 bgeu a5,a6,80010fe8 <__divdf3+0x3a4> -80010fd4: 006787b3 add a5,a5,t1 -80010fd8: 0067b733 sltu a4,a5,t1 +80010fb4: 40c70733 sub a4,a4,a2 +80010fb8: 02a75e33 divu t3,a4,a0 +80010fbc: 01041413 slli s0,s0,0x10 +80010fc0: 01045413 srli s0,s0,0x10 +80010fc4: 02a77733 remu a4,a4,a0 +80010fc8: 000e0613 mv a2,t3 +80010fcc: 03ce8833 mul a6,t4,t3 +80010fd0: 01071713 slli a4,a4,0x10 +80010fd4: 00e46733 or a4,s0,a4 +80010fd8: 01077e63 bgeu a4,a6,80010ff4 <__divdf3+0x2ec> 80010fdc: 01170733 add a4,a4,a7 -80010fe0: ffef8493 addi s1,t6,-2 -80010fe4: 00e40433 add s0,s0,a4 -80010fe8: 41078833 sub a6,a5,a6 -80010fec: 40c40433 sub s0,s0,a2 -80010ff0: 0107b7b3 sltu a5,a5,a6 -80010ff4: 40f40433 sub s0,s0,a5 -80010ff8: fff00f93 li t6,-1 -80010ffc: 12888463 beq a7,s0,80011124 <__divdf3+0x4e0> -80011000: 02a45fb3 divu t6,s0,a0 -80011004: 01085713 srli a4,a6,0x10 -80011008: 02a47433 remu s0,s0,a0 -8001100c: 000f8613 mv a2,t6 -80011010: 03fe87b3 mul a5,t4,t6 -80011014: 01041413 slli s0,s0,0x10 -80011018: 00876433 or s0,a4,s0 -8001101c: 00f47e63 bgeu s0,a5,80011038 <__divdf3+0x3f4> -80011020: 01140433 add s0,s0,a7 -80011024: ffff8613 addi a2,t6,-1 -80011028: 01146863 bltu s0,a7,80011038 <__divdf3+0x3f4> -8001102c: 00f47663 bgeu s0,a5,80011038 <__divdf3+0x3f4> -80011030: ffef8613 addi a2,t6,-2 -80011034: 01140433 add s0,s0,a7 -80011038: 40f40433 sub s0,s0,a5 -8001103c: 02a45733 divu a4,s0,a0 -80011040: 01081813 slli a6,a6,0x10 -80011044: 01085813 srli a6,a6,0x10 -80011048: 02a47433 remu s0,s0,a0 -8001104c: 00070793 mv a5,a4 -80011050: 02ee8eb3 mul t4,t4,a4 -80011054: 01041413 slli s0,s0,0x10 -80011058: 00886433 or s0,a6,s0 -8001105c: 01d47e63 bgeu s0,t4,80011078 <__divdf3+0x434> -80011060: 01140433 add s0,s0,a7 -80011064: fff70793 addi a5,a4,-1 -80011068: 01146863 bltu s0,a7,80011078 <__divdf3+0x434> -8001106c: 01d47663 bgeu s0,t4,80011078 <__divdf3+0x434> -80011070: ffe70793 addi a5,a4,-2 -80011074: 01140433 add s0,s0,a7 -80011078: 01061613 slli a2,a2,0x10 -8001107c: 00f66633 or a2,a2,a5 -80011080: 01061793 slli a5,a2,0x10 -80011084: 0107d793 srli a5,a5,0x10 -80011088: 01065713 srli a4,a2,0x10 -8001108c: 02ef0833 mul a6,t5,a4 -80011090: 41d40433 sub s0,s0,t4 -80011094: 02ff0f33 mul t5,t5,a5 -80011098: 03c78eb3 mul t4,a5,t3 -8001109c: 03c70e33 mul t3,a4,t3 -800110a0: 010ed793 srli a5,t4,0x10 -800110a4: 01cf0f33 add t5,t5,t3 -800110a8: 01e787b3 add a5,a5,t5 -800110ac: 01c7f663 bgeu a5,t3,800110b8 <__divdf3+0x474> -800110b0: 00010737 lui a4,0x10 -800110b4: 00e80833 add a6,a6,a4 -800110b8: 0107d713 srli a4,a5,0x10 -800110bc: 01070733 add a4,a4,a6 -800110c0: 00010837 lui a6,0x10 -800110c4: fff80813 addi a6,a6,-1 # ffff <_start-0x7fff0001> -800110c8: 0107f533 and a0,a5,a6 -800110cc: 01051513 slli a0,a0,0x10 -800110d0: 010efeb3 and t4,t4,a6 -800110d4: 01d50533 add a0,a0,t4 -800110d8: 00e46863 bltu s0,a4,800110e8 <__divdf3+0x4a4> -800110dc: 24e41063 bne s0,a4,8001131c <__divdf3+0x6d8> -800110e0: 00060f93 mv t6,a2 -800110e4: 04050063 beqz a0,80011124 <__divdf3+0x4e0> -800110e8: 00888433 add s0,a7,s0 -800110ec: fff60f93 addi t6,a2,-1 # ffffff <_start-0x7f000001> -800110f0: 03146463 bltu s0,a7,80011118 <__divdf3+0x4d4> -800110f4: 00e46663 bltu s0,a4,80011100 <__divdf3+0x4bc> -800110f8: 22e41063 bne s0,a4,80011318 <__divdf3+0x6d4> -800110fc: 02a37063 bgeu t1,a0,8001111c <__divdf3+0x4d8> -80011100: 00131793 slli a5,t1,0x1 -80011104: 0067b333 sltu t1,a5,t1 -80011108: 011308b3 add a7,t1,a7 -8001110c: ffe60f93 addi t6,a2,-2 -80011110: 01140433 add s0,s0,a7 -80011114: 00078313 mv t1,a5 -80011118: 00e41463 bne s0,a4,80011120 <__divdf3+0x4dc> -8001111c: 00650463 beq a0,t1,80011124 <__divdf3+0x4e0> -80011120: 001fef93 ori t6,t6,1 -80011124: 3ff58793 addi a5,a1,1023 -80011128: 10f05863 blez a5,80011238 <__divdf3+0x5f4> -8001112c: 007ff713 andi a4,t6,7 -80011130: 02070063 beqz a4,80011150 <__divdf3+0x50c> -80011134: 00fff713 andi a4,t6,15 -80011138: 00400613 li a2,4 -8001113c: 00c70a63 beq a4,a2,80011150 <__divdf3+0x50c> -80011140: 004f8613 addi a2,t6,4 -80011144: 01f63fb3 sltu t6,a2,t6 -80011148: 01f484b3 add s1,s1,t6 -8001114c: 00060f93 mv t6,a2 -80011150: 00749713 slli a4,s1,0x7 -80011154: 00075a63 bgez a4,80011168 <__divdf3+0x524> -80011158: ff0007b7 lui a5,0xff000 -8001115c: fff78793 addi a5,a5,-1 # feffffff <__BSS_END__+0x7efe93cf> -80011160: 00f4f4b3 and s1,s1,a5 -80011164: 40058793 addi a5,a1,1024 -80011168: 7fe00713 li a4,2046 -8001116c: 0af74063 blt a4,a5,8001120c <__divdf3+0x5c8> -80011170: 003fdf93 srli t6,t6,0x3 -80011174: 01d49713 slli a4,s1,0x1d -80011178: 01f76733 or a4,a4,t6 -8001117c: 0034d513 srli a0,s1,0x3 -80011180: 01479793 slli a5,a5,0x14 -80011184: 7ff00637 lui a2,0x7ff00 -80011188: 00c51513 slli a0,a0,0xc -8001118c: 02c12083 lw ra,44(sp) -80011190: 02812403 lw s0,40(sp) -80011194: 00c7f7b3 and a5,a5,a2 -80011198: 00c55513 srli a0,a0,0xc -8001119c: 00a7e533 or a0,a5,a0 -800111a0: 01f69693 slli a3,a3,0x1f -800111a4: 00d567b3 or a5,a0,a3 -800111a8: 02412483 lw s1,36(sp) -800111ac: 02012903 lw s2,32(sp) -800111b0: 01c12983 lw s3,28(sp) -800111b4: 01812a03 lw s4,24(sp) -800111b8: 01412a83 lw s5,20(sp) -800111bc: 01012b03 lw s6,16(sp) -800111c0: 00c12b83 lw s7,12(sp) -800111c4: 00812c03 lw s8,8(sp) -800111c8: 00070513 mv a0,a4 -800111cc: 00078593 mv a1,a5 -800111d0: 03010113 addi sp,sp,48 -800111d4: 00008067 ret -800111d8: fff58593 addi a1,a1,-1 -800111dc: 00000793 li a5,0 -800111e0: cbdff06f j 80010e9c <__divdf3+0x258> -800111e4: 000a0693 mv a3,s4 -800111e8: 00098493 mv s1,s3 -800111ec: 00040f93 mv t6,s0 -800111f0: 000b8613 mv a2,s7 -800111f4: 00300793 li a5,3 -800111f8: 0ef60863 beq a2,a5,800112e8 <__divdf3+0x6a4> -800111fc: 00100793 li a5,1 -80011200: 0ef60e63 beq a2,a5,800112fc <__divdf3+0x6b8> -80011204: 00200793 li a5,2 -80011208: f0f61ee3 bne a2,a5,80011124 <__divdf3+0x4e0> -8001120c: 00000513 li a0,0 -80011210: 00000713 li a4,0 -80011214: 7ff00793 li a5,2047 -80011218: f69ff06f j 80011180 <__divdf3+0x53c> -8001121c: 000c0693 mv a3,s8 -80011220: fd5ff06f j 800111f4 <__divdf3+0x5b0> -80011224: 000804b7 lui s1,0x80 -80011228: 00000f93 li t6,0 -8001122c: 00000693 li a3,0 -80011230: 00300613 li a2,3 -80011234: fc1ff06f j 800111f4 <__divdf3+0x5b0> -80011238: 00100513 li a0,1 -8001123c: 40f50533 sub a0,a0,a5 -80011240: 03800713 li a4,56 -80011244: 0aa74c63 blt a4,a0,800112fc <__divdf3+0x6b8> -80011248: 01f00713 li a4,31 -8001124c: 06a74463 blt a4,a0,800112b4 <__divdf3+0x670> -80011250: 41e58593 addi a1,a1,1054 -80011254: 00b497b3 sll a5,s1,a1 -80011258: 00afd733 srl a4,t6,a0 -8001125c: 00bf95b3 sll a1,t6,a1 -80011260: 00e7e7b3 or a5,a5,a4 -80011264: 00b035b3 snez a1,a1 -80011268: 00b7e7b3 or a5,a5,a1 -8001126c: 00a4d533 srl a0,s1,a0 -80011270: 0077f713 andi a4,a5,7 -80011274: 02070063 beqz a4,80011294 <__divdf3+0x650> -80011278: 00f7f713 andi a4,a5,15 -8001127c: 00400613 li a2,4 -80011280: 00c70a63 beq a4,a2,80011294 <__divdf3+0x650> -80011284: 00478713 addi a4,a5,4 -80011288: 00f737b3 sltu a5,a4,a5 -8001128c: 00f50533 add a0,a0,a5 -80011290: 00070793 mv a5,a4 -80011294: 00851713 slli a4,a0,0x8 -80011298: 06074863 bltz a4,80011308 <__divdf3+0x6c4> -8001129c: 01d51713 slli a4,a0,0x1d -800112a0: 0037d793 srli a5,a5,0x3 -800112a4: 00f76733 or a4,a4,a5 -800112a8: 00355513 srli a0,a0,0x3 -800112ac: 00000793 li a5,0 -800112b0: ed1ff06f j 80011180 <__divdf3+0x53c> -800112b4: fe100713 li a4,-31 -800112b8: 40f707b3 sub a5,a4,a5 -800112bc: 02000613 li a2,32 -800112c0: 00f4d7b3 srl a5,s1,a5 -800112c4: 00000713 li a4,0 -800112c8: 00c50663 beq a0,a2,800112d4 <__divdf3+0x690> -800112cc: 43e58593 addi a1,a1,1086 -800112d0: 00b49733 sll a4,s1,a1 -800112d4: 01f76fb3 or t6,a4,t6 -800112d8: 01f03fb3 snez t6,t6 -800112dc: 01f7e7b3 or a5,a5,t6 -800112e0: 00000513 li a0,0 -800112e4: f8dff06f j 80011270 <__divdf3+0x62c> -800112e8: 00080537 lui a0,0x80 -800112ec: 00000713 li a4,0 -800112f0: 7ff00793 li a5,2047 -800112f4: 00000693 li a3,0 -800112f8: e89ff06f j 80011180 <__divdf3+0x53c> -800112fc: 00000513 li a0,0 -80011300: 00000713 li a4,0 -80011304: fa9ff06f j 800112ac <__divdf3+0x668> -80011308: 00000513 li a0,0 -8001130c: 00000713 li a4,0 -80011310: 00100793 li a5,1 -80011314: e6dff06f j 80011180 <__divdf3+0x53c> -80011318: 000f8613 mv a2,t6 -8001131c: 00060f93 mv t6,a2 -80011320: e01ff06f j 80011120 <__divdf3+0x4dc> +80010fe0: fffe0613 addi a2,t3,-1 +80010fe4: 01176863 bltu a4,a7,80010ff4 <__divdf3+0x2ec> +80010fe8: 01077663 bgeu a4,a6,80010ff4 <__divdf3+0x2ec> +80010fec: ffee0613 addi a2,t3,-2 +80010ff0: 01170733 add a4,a4,a7 +80010ff4: 41070433 sub s0,a4,a6 +80010ff8: 010f9f93 slli t6,t6,0x10 +80010ffc: 00010837 lui a6,0x10 +80011000: 00cfefb3 or t6,t6,a2 +80011004: fff80e13 addi t3,a6,-1 # ffff <_start-0x7fff0001> +80011008: 010fd613 srli a2,t6,0x10 +8001100c: 01cff733 and a4,t6,t3 +80011010: 01035f13 srli t5,t1,0x10 +80011014: 01c37e33 and t3,t1,t3 +80011018: 02ee03b3 mul t2,t3,a4 +8001101c: 03c604b3 mul s1,a2,t3 +80011020: 02ef0733 mul a4,t5,a4 +80011024: 03e602b3 mul t0,a2,t5 +80011028: 00970633 add a2,a4,s1 +8001102c: 0103d713 srli a4,t2,0x10 +80011030: 00c70733 add a4,a4,a2 +80011034: 00977463 bgeu a4,s1,8001103c <__divdf3+0x334> +80011038: 010282b3 add t0,t0,a6 +8001103c: 01075613 srli a2,a4,0x10 +80011040: 00560633 add a2,a2,t0 +80011044: 000102b7 lui t0,0x10 +80011048: fff28293 addi t0,t0,-1 # ffff <_start-0x7fff0001> +8001104c: 00577833 and a6,a4,t0 +80011050: 01081813 slli a6,a6,0x10 +80011054: 0053f3b3 and t2,t2,t0 +80011058: 00780833 add a6,a6,t2 +8001105c: 00c46863 bltu s0,a2,8001106c <__divdf3+0x364> +80011060: 000f8493 mv s1,t6 +80011064: 04c41463 bne s0,a2,800110ac <__divdf3+0x3a4> +80011068: 0507f263 bgeu a5,a6,800110ac <__divdf3+0x3a4> +8001106c: 006787b3 add a5,a5,t1 +80011070: 0067b733 sltu a4,a5,t1 +80011074: 01170733 add a4,a4,a7 +80011078: 00e40433 add s0,s0,a4 +8001107c: ffff8493 addi s1,t6,-1 +80011080: 0088e663 bltu a7,s0,8001108c <__divdf3+0x384> +80011084: 02889463 bne a7,s0,800110ac <__divdf3+0x3a4> +80011088: 0267e263 bltu a5,t1,800110ac <__divdf3+0x3a4> +8001108c: 00c46663 bltu s0,a2,80011098 <__divdf3+0x390> +80011090: 00861e63 bne a2,s0,800110ac <__divdf3+0x3a4> +80011094: 0107fc63 bgeu a5,a6,800110ac <__divdf3+0x3a4> +80011098: 006787b3 add a5,a5,t1 +8001109c: 0067b733 sltu a4,a5,t1 +800110a0: 01170733 add a4,a4,a7 +800110a4: ffef8493 addi s1,t6,-2 +800110a8: 00e40433 add s0,s0,a4 +800110ac: 41078833 sub a6,a5,a6 +800110b0: 40c40433 sub s0,s0,a2 +800110b4: 0107b7b3 sltu a5,a5,a6 +800110b8: 40f40433 sub s0,s0,a5 +800110bc: fff00f93 li t6,-1 +800110c0: 12888463 beq a7,s0,800111e8 <__divdf3+0x4e0> +800110c4: 02a45fb3 divu t6,s0,a0 +800110c8: 01085713 srli a4,a6,0x10 +800110cc: 02a47433 remu s0,s0,a0 +800110d0: 000f8613 mv a2,t6 +800110d4: 03fe87b3 mul a5,t4,t6 +800110d8: 01041413 slli s0,s0,0x10 +800110dc: 00876433 or s0,a4,s0 +800110e0: 00f47e63 bgeu s0,a5,800110fc <__divdf3+0x3f4> +800110e4: 01140433 add s0,s0,a7 +800110e8: ffff8613 addi a2,t6,-1 +800110ec: 01146863 bltu s0,a7,800110fc <__divdf3+0x3f4> +800110f0: 00f47663 bgeu s0,a5,800110fc <__divdf3+0x3f4> +800110f4: ffef8613 addi a2,t6,-2 +800110f8: 01140433 add s0,s0,a7 +800110fc: 40f40433 sub s0,s0,a5 +80011100: 02a45733 divu a4,s0,a0 +80011104: 01081813 slli a6,a6,0x10 +80011108: 01085813 srli a6,a6,0x10 +8001110c: 02a47433 remu s0,s0,a0 +80011110: 00070793 mv a5,a4 +80011114: 02ee8eb3 mul t4,t4,a4 +80011118: 01041413 slli s0,s0,0x10 +8001111c: 00886433 or s0,a6,s0 +80011120: 01d47e63 bgeu s0,t4,8001113c <__divdf3+0x434> +80011124: 01140433 add s0,s0,a7 +80011128: fff70793 addi a5,a4,-1 +8001112c: 01146863 bltu s0,a7,8001113c <__divdf3+0x434> +80011130: 01d47663 bgeu s0,t4,8001113c <__divdf3+0x434> +80011134: ffe70793 addi a5,a4,-2 +80011138: 01140433 add s0,s0,a7 +8001113c: 01061613 slli a2,a2,0x10 +80011140: 00f66633 or a2,a2,a5 +80011144: 01061793 slli a5,a2,0x10 +80011148: 0107d793 srli a5,a5,0x10 +8001114c: 01065713 srli a4,a2,0x10 +80011150: 02ef0833 mul a6,t5,a4 +80011154: 41d40433 sub s0,s0,t4 +80011158: 02ff0f33 mul t5,t5,a5 +8001115c: 03c78eb3 mul t4,a5,t3 +80011160: 03c70e33 mul t3,a4,t3 +80011164: 010ed793 srli a5,t4,0x10 +80011168: 01cf0f33 add t5,t5,t3 +8001116c: 01e787b3 add a5,a5,t5 +80011170: 01c7f663 bgeu a5,t3,8001117c <__divdf3+0x474> +80011174: 00010737 lui a4,0x10 +80011178: 00e80833 add a6,a6,a4 +8001117c: 0107d713 srli a4,a5,0x10 +80011180: 01070733 add a4,a4,a6 +80011184: 00010837 lui a6,0x10 +80011188: fff80813 addi a6,a6,-1 # ffff <_start-0x7fff0001> +8001118c: 0107f533 and a0,a5,a6 +80011190: 01051513 slli a0,a0,0x10 +80011194: 010efeb3 and t4,t4,a6 +80011198: 01d50533 add a0,a0,t4 +8001119c: 00e46863 bltu s0,a4,800111ac <__divdf3+0x4a4> +800111a0: 24e41063 bne s0,a4,800113e0 <__divdf3+0x6d8> +800111a4: 00060f93 mv t6,a2 +800111a8: 04050063 beqz a0,800111e8 <__divdf3+0x4e0> +800111ac: 00888433 add s0,a7,s0 +800111b0: fff60f93 addi t6,a2,-1 # ffffff <_start-0x7f000001> +800111b4: 03146463 bltu s0,a7,800111dc <__divdf3+0x4d4> +800111b8: 00e46663 bltu s0,a4,800111c4 <__divdf3+0x4bc> +800111bc: 22e41063 bne s0,a4,800113dc <__divdf3+0x6d4> +800111c0: 02a37063 bgeu t1,a0,800111e0 <__divdf3+0x4d8> +800111c4: 00131793 slli a5,t1,0x1 +800111c8: 0067b333 sltu t1,a5,t1 +800111cc: 011308b3 add a7,t1,a7 +800111d0: ffe60f93 addi t6,a2,-2 +800111d4: 01140433 add s0,s0,a7 +800111d8: 00078313 mv t1,a5 +800111dc: 00e41463 bne s0,a4,800111e4 <__divdf3+0x4dc> +800111e0: 00650463 beq a0,t1,800111e8 <__divdf3+0x4e0> +800111e4: 001fef93 ori t6,t6,1 +800111e8: 3ff58793 addi a5,a1,1023 +800111ec: 10f05863 blez a5,800112fc <__divdf3+0x5f4> +800111f0: 007ff713 andi a4,t6,7 +800111f4: 02070063 beqz a4,80011214 <__divdf3+0x50c> +800111f8: 00fff713 andi a4,t6,15 +800111fc: 00400613 li a2,4 +80011200: 00c70a63 beq a4,a2,80011214 <__divdf3+0x50c> +80011204: 004f8613 addi a2,t6,4 +80011208: 01f63fb3 sltu t6,a2,t6 +8001120c: 01f484b3 add s1,s1,t6 +80011210: 00060f93 mv t6,a2 +80011214: 00749713 slli a4,s1,0x7 +80011218: 00075a63 bgez a4,8001122c <__divdf3+0x524> +8001121c: ff0007b7 lui a5,0xff000 +80011220: fff78793 addi a5,a5,-1 # feffffff <__BSS_END__+0x7efe93c3> +80011224: 00f4f4b3 and s1,s1,a5 +80011228: 40058793 addi a5,a1,1024 +8001122c: 7fe00713 li a4,2046 +80011230: 0af74063 blt a4,a5,800112d0 <__divdf3+0x5c8> +80011234: 003fdf93 srli t6,t6,0x3 +80011238: 01d49713 slli a4,s1,0x1d +8001123c: 01f76733 or a4,a4,t6 +80011240: 0034d513 srli a0,s1,0x3 +80011244: 01479793 slli a5,a5,0x14 +80011248: 7ff00637 lui a2,0x7ff00 +8001124c: 00c51513 slli a0,a0,0xc +80011250: 02c12083 lw ra,44(sp) +80011254: 02812403 lw s0,40(sp) +80011258: 00c7f7b3 and a5,a5,a2 +8001125c: 00c55513 srli a0,a0,0xc +80011260: 00a7e533 or a0,a5,a0 +80011264: 01f69693 slli a3,a3,0x1f +80011268: 00d567b3 or a5,a0,a3 +8001126c: 02412483 lw s1,36(sp) +80011270: 02012903 lw s2,32(sp) +80011274: 01c12983 lw s3,28(sp) +80011278: 01812a03 lw s4,24(sp) +8001127c: 01412a83 lw s5,20(sp) +80011280: 01012b03 lw s6,16(sp) +80011284: 00c12b83 lw s7,12(sp) +80011288: 00812c03 lw s8,8(sp) +8001128c: 00070513 mv a0,a4 +80011290: 00078593 mv a1,a5 +80011294: 03010113 addi sp,sp,48 +80011298: 00008067 ret +8001129c: fff58593 addi a1,a1,-1 +800112a0: 00000793 li a5,0 +800112a4: cbdff06f j 80010f60 <__divdf3+0x258> +800112a8: 000a0693 mv a3,s4 +800112ac: 00098493 mv s1,s3 +800112b0: 00040f93 mv t6,s0 +800112b4: 000b8613 mv a2,s7 +800112b8: 00300793 li a5,3 +800112bc: 0ef60863 beq a2,a5,800113ac <__divdf3+0x6a4> +800112c0: 00100793 li a5,1 +800112c4: 0ef60e63 beq a2,a5,800113c0 <__divdf3+0x6b8> +800112c8: 00200793 li a5,2 +800112cc: f0f61ee3 bne a2,a5,800111e8 <__divdf3+0x4e0> +800112d0: 00000513 li a0,0 +800112d4: 00000713 li a4,0 +800112d8: 7ff00793 li a5,2047 +800112dc: f69ff06f j 80011244 <__divdf3+0x53c> +800112e0: 000c0693 mv a3,s8 +800112e4: fd5ff06f j 800112b8 <__divdf3+0x5b0> +800112e8: 000804b7 lui s1,0x80 +800112ec: 00000f93 li t6,0 +800112f0: 00000693 li a3,0 +800112f4: 00300613 li a2,3 +800112f8: fc1ff06f j 800112b8 <__divdf3+0x5b0> +800112fc: 00100513 li a0,1 +80011300: 40f50533 sub a0,a0,a5 +80011304: 03800713 li a4,56 +80011308: 0aa74c63 blt a4,a0,800113c0 <__divdf3+0x6b8> +8001130c: 01f00713 li a4,31 +80011310: 06a74463 blt a4,a0,80011378 <__divdf3+0x670> +80011314: 41e58593 addi a1,a1,1054 +80011318: 00b497b3 sll a5,s1,a1 +8001131c: 00afd733 srl a4,t6,a0 +80011320: 00bf95b3 sll a1,t6,a1 +80011324: 00e7e7b3 or a5,a5,a4 +80011328: 00b035b3 snez a1,a1 +8001132c: 00b7e7b3 or a5,a5,a1 +80011330: 00a4d533 srl a0,s1,a0 +80011334: 0077f713 andi a4,a5,7 +80011338: 02070063 beqz a4,80011358 <__divdf3+0x650> +8001133c: 00f7f713 andi a4,a5,15 +80011340: 00400613 li a2,4 +80011344: 00c70a63 beq a4,a2,80011358 <__divdf3+0x650> +80011348: 00478713 addi a4,a5,4 +8001134c: 00f737b3 sltu a5,a4,a5 +80011350: 00f50533 add a0,a0,a5 +80011354: 00070793 mv a5,a4 +80011358: 00851713 slli a4,a0,0x8 +8001135c: 06074863 bltz a4,800113cc <__divdf3+0x6c4> +80011360: 01d51713 slli a4,a0,0x1d +80011364: 0037d793 srli a5,a5,0x3 +80011368: 00f76733 or a4,a4,a5 +8001136c: 00355513 srli a0,a0,0x3 +80011370: 00000793 li a5,0 +80011374: ed1ff06f j 80011244 <__divdf3+0x53c> +80011378: fe100713 li a4,-31 +8001137c: 40f707b3 sub a5,a4,a5 +80011380: 02000613 li a2,32 +80011384: 00f4d7b3 srl a5,s1,a5 +80011388: 00000713 li a4,0 +8001138c: 00c50663 beq a0,a2,80011398 <__divdf3+0x690> +80011390: 43e58593 addi a1,a1,1086 +80011394: 00b49733 sll a4,s1,a1 +80011398: 01f76fb3 or t6,a4,t6 +8001139c: 01f03fb3 snez t6,t6 +800113a0: 01f7e7b3 or a5,a5,t6 +800113a4: 00000513 li a0,0 +800113a8: f8dff06f j 80011334 <__divdf3+0x62c> +800113ac: 00080537 lui a0,0x80 +800113b0: 00000713 li a4,0 +800113b4: 7ff00793 li a5,2047 +800113b8: 00000693 li a3,0 +800113bc: e89ff06f j 80011244 <__divdf3+0x53c> +800113c0: 00000513 li a0,0 +800113c4: 00000713 li a4,0 +800113c8: fa9ff06f j 80011370 <__divdf3+0x668> +800113cc: 00000513 li a0,0 +800113d0: 00000713 li a4,0 +800113d4: 00100793 li a5,1 +800113d8: e6dff06f j 80011244 <__divdf3+0x53c> +800113dc: 000f8613 mv a2,t6 +800113e0: 00060f93 mv t6,a2 +800113e4: e01ff06f j 800111e4 <__divdf3+0x4dc> -80011324 <__muldf3>: -80011324: fd010113 addi sp,sp,-48 -80011328: 0145d793 srli a5,a1,0x14 -8001132c: 02812423 sw s0,40(sp) -80011330: 02912223 sw s1,36(sp) -80011334: 01312e23 sw s3,28(sp) -80011338: 01412c23 sw s4,24(sp) -8001133c: 01512a23 sw s5,20(sp) -80011340: 00c59493 slli s1,a1,0xc -80011344: 02112623 sw ra,44(sp) -80011348: 03212023 sw s2,32(sp) -8001134c: 01612823 sw s6,16(sp) -80011350: 01712623 sw s7,12(sp) -80011354: 01579713 slli a4,a5,0x15 -80011358: 00050413 mv s0,a0 -8001135c: 00060993 mv s3,a2 -80011360: 00068a93 mv s5,a3 -80011364: 00c4d493 srli s1,s1,0xc -80011368: 01f5da13 srli s4,a1,0x1f -8001136c: 0a070663 beqz a4,80011418 <__muldf3+0xf4> -80011370: 7ff7fb13 andi s6,a5,2047 -80011374: 7ff00793 li a5,2047 -80011378: 10fb0263 beq s6,a5,8001147c <__muldf3+0x158> -8001137c: 01d55793 srli a5,a0,0x1d -80011380: 00349493 slli s1,s1,0x3 -80011384: 0097e4b3 or s1,a5,s1 -80011388: 008007b7 lui a5,0x800 -8001138c: 00f4e4b3 or s1,s1,a5 -80011390: 00351913 slli s2,a0,0x3 -80011394: c01b0b13 addi s6,s6,-1023 -80011398: 00000b93 li s7,0 -8001139c: 014ad793 srli a5,s5,0x14 -800113a0: 00ca9413 slli s0,s5,0xc -800113a4: 01579713 slli a4,a5,0x15 -800113a8: 00c45413 srli s0,s0,0xc -800113ac: 7ff7f513 andi a0,a5,2047 -800113b0: 01fada93 srli s5,s5,0x1f -800113b4: 10070063 beqz a4,800114b4 <__muldf3+0x190> -800113b8: 7ff00793 li a5,2047 -800113bc: 16f50063 beq a0,a5,8001151c <__muldf3+0x1f8> -800113c0: 01d9d793 srli a5,s3,0x1d -800113c4: 00341413 slli s0,s0,0x3 -800113c8: 0087e433 or s0,a5,s0 -800113cc: 008007b7 lui a5,0x800 -800113d0: 00f46433 or s0,s0,a5 -800113d4: c0150513 addi a0,a0,-1023 # 7fc01 <_start-0x7ff803ff> -800113d8: 00399793 slli a5,s3,0x3 -800113dc: 00000713 li a4,0 -800113e0: 002b9693 slli a3,s7,0x2 -800113e4: 00e6e6b3 or a3,a3,a4 -800113e8: 00ab0533 add a0,s6,a0 -800113ec: fff68693 addi a3,a3,-1 -800113f0: 00e00813 li a6,14 -800113f4: 015a4633 xor a2,s4,s5 -800113f8: 00150593 addi a1,a0,1 -800113fc: 14d86c63 bltu a6,a3,80011554 <__muldf3+0x230> -80011400: 80015537 lui a0,0x80015 -80011404: 00269693 slli a3,a3,0x2 -80011408: 78450513 addi a0,a0,1924 # 80015784 <__BSS_END__+0xffffeb54> -8001140c: 00a686b3 add a3,a3,a0 -80011410: 0006a683 lw a3,0(a3) -80011414: 00068067 jr a3 -80011418: 00a4e933 or s2,s1,a0 -8001141c: 06090c63 beqz s2,80011494 <__muldf3+0x170> -80011420: 04048063 beqz s1,80011460 <__muldf3+0x13c> -80011424: 00048513 mv a0,s1 -80011428: 4dc030ef jal ra,80014904 <__clzsi2> -8001142c: ff550713 addi a4,a0,-11 -80011430: 01c00793 li a5,28 -80011434: 02e7cc63 blt a5,a4,8001146c <__muldf3+0x148> -80011438: 01d00793 li a5,29 -8001143c: ff850913 addi s2,a0,-8 -80011440: 40e787b3 sub a5,a5,a4 -80011444: 012494b3 sll s1,s1,s2 -80011448: 00f457b3 srl a5,s0,a5 -8001144c: 0097e4b3 or s1,a5,s1 -80011450: 01241933 sll s2,s0,s2 -80011454: c0d00b13 li s6,-1011 -80011458: 40ab0b33 sub s6,s6,a0 -8001145c: f3dff06f j 80011398 <__muldf3+0x74> -80011460: 4a4030ef jal ra,80014904 <__clzsi2> -80011464: 02050513 addi a0,a0,32 -80011468: fc5ff06f j 8001142c <__muldf3+0x108> -8001146c: fd850493 addi s1,a0,-40 -80011470: 009414b3 sll s1,s0,s1 -80011474: 00000913 li s2,0 -80011478: fddff06f j 80011454 <__muldf3+0x130> -8001147c: 00a4e933 or s2,s1,a0 -80011480: 02090263 beqz s2,800114a4 <__muldf3+0x180> -80011484: 00050913 mv s2,a0 -80011488: 7ff00b13 li s6,2047 -8001148c: 00300b93 li s7,3 -80011490: f0dff06f j 8001139c <__muldf3+0x78> -80011494: 00000493 li s1,0 -80011498: 00000b13 li s6,0 -8001149c: 00100b93 li s7,1 -800114a0: efdff06f j 8001139c <__muldf3+0x78> -800114a4: 00000493 li s1,0 -800114a8: 7ff00b13 li s6,2047 -800114ac: 00200b93 li s7,2 -800114b0: eedff06f j 8001139c <__muldf3+0x78> -800114b4: 013467b3 or a5,s0,s3 -800114b8: 06078e63 beqz a5,80011534 <__muldf3+0x210> -800114bc: 04040063 beqz s0,800114fc <__muldf3+0x1d8> -800114c0: 00040513 mv a0,s0 -800114c4: 440030ef jal ra,80014904 <__clzsi2> -800114c8: ff550693 addi a3,a0,-11 -800114cc: 01c00793 li a5,28 -800114d0: 02d7ce63 blt a5,a3,8001150c <__muldf3+0x1e8> -800114d4: 01d00713 li a4,29 -800114d8: ff850793 addi a5,a0,-8 -800114dc: 40d70733 sub a4,a4,a3 -800114e0: 00f41433 sll s0,s0,a5 -800114e4: 00e9d733 srl a4,s3,a4 -800114e8: 00876433 or s0,a4,s0 -800114ec: 00f997b3 sll a5,s3,a5 -800114f0: c0d00713 li a4,-1011 -800114f4: 40a70533 sub a0,a4,a0 -800114f8: ee5ff06f j 800113dc <__muldf3+0xb8> -800114fc: 00098513 mv a0,s3 -80011500: 404030ef jal ra,80014904 <__clzsi2> -80011504: 02050513 addi a0,a0,32 -80011508: fc1ff06f j 800114c8 <__muldf3+0x1a4> -8001150c: fd850413 addi s0,a0,-40 -80011510: 00899433 sll s0,s3,s0 -80011514: 00000793 li a5,0 -80011518: fd9ff06f j 800114f0 <__muldf3+0x1cc> -8001151c: 013467b3 or a5,s0,s3 -80011520: 02078263 beqz a5,80011544 <__muldf3+0x220> -80011524: 00098793 mv a5,s3 -80011528: 7ff00513 li a0,2047 -8001152c: 00300713 li a4,3 -80011530: eb1ff06f j 800113e0 <__muldf3+0xbc> -80011534: 00000413 li s0,0 -80011538: 00000513 li a0,0 -8001153c: 00100713 li a4,1 -80011540: ea1ff06f j 800113e0 <__muldf3+0xbc> -80011544: 00000413 li s0,0 -80011548: 7ff00513 li a0,2047 -8001154c: 00200713 li a4,2 -80011550: e91ff06f j 800113e0 <__muldf3+0xbc> -80011554: 00010f37 lui t5,0x10 -80011558: ffff0713 addi a4,t5,-1 # ffff <_start-0x7fff0001> -8001155c: 01095693 srli a3,s2,0x10 -80011560: 0107d313 srli t1,a5,0x10 -80011564: 00e97933 and s2,s2,a4 -80011568: 00e7f7b3 and a5,a5,a4 -8001156c: 032308b3 mul a7,t1,s2 -80011570: 02f90833 mul a6,s2,a5 -80011574: 02f68fb3 mul t6,a3,a5 -80011578: 01f88eb3 add t4,a7,t6 -8001157c: 01085893 srli a7,a6,0x10 -80011580: 01d888b3 add a7,a7,t4 -80011584: 02668e33 mul t3,a3,t1 -80011588: 01f8f463 bgeu a7,t6,80011590 <__muldf3+0x26c> -8001158c: 01ee0e33 add t3,t3,t5 -80011590: 0108d293 srli t0,a7,0x10 -80011594: 00e8f8b3 and a7,a7,a4 -80011598: 00e87833 and a6,a6,a4 -8001159c: 01045f13 srli t5,s0,0x10 -800115a0: 01089893 slli a7,a7,0x10 -800115a4: 00e47433 and s0,s0,a4 -800115a8: 010888b3 add a7,a7,a6 -800115ac: 02868733 mul a4,a3,s0 -800115b0: 02890833 mul a6,s2,s0 -800115b4: 032f0933 mul s2,t5,s2 -800115b8: 00e90eb3 add t4,s2,a4 -800115bc: 01085913 srli s2,a6,0x10 -800115c0: 01d90933 add s2,s2,t4 -800115c4: 03e686b3 mul a3,a3,t5 -800115c8: 00e97663 bgeu s2,a4,800115d4 <__muldf3+0x2b0> -800115cc: 00010737 lui a4,0x10 -800115d0: 00e686b3 add a3,a3,a4 -800115d4: 01095e93 srli t4,s2,0x10 -800115d8: 00de8eb3 add t4,t4,a3 -800115dc: 000106b7 lui a3,0x10 -800115e0: fff68f93 addi t6,a3,-1 # ffff <_start-0x7fff0001> -800115e4: 01f97933 and s2,s2,t6 -800115e8: 01f87833 and a6,a6,t6 -800115ec: 0104d713 srli a4,s1,0x10 -800115f0: 01091913 slli s2,s2,0x10 -800115f4: 01f4f4b3 and s1,s1,t6 -800115f8: 029783b3 mul t2,a5,s1 -800115fc: 01090933 add s2,s2,a6 -80011600: 012282b3 add t0,t0,s2 -80011604: 02930833 mul a6,t1,s1 -80011608: 02f707b3 mul a5,a4,a5 -8001160c: 02e30fb3 mul t6,t1,a4 -80011610: 00f80333 add t1,a6,a5 -80011614: 0103d813 srli a6,t2,0x10 -80011618: 00680833 add a6,a6,t1 -8001161c: 00f87463 bgeu a6,a5,80011624 <__muldf3+0x300> -80011620: 00df8fb3 add t6,t6,a3 -80011624: 01085793 srli a5,a6,0x10 -80011628: 000106b7 lui a3,0x10 -8001162c: 01f78fb3 add t6,a5,t6 -80011630: fff68793 addi a5,a3,-1 # ffff <_start-0x7fff0001> -80011634: 00f87833 and a6,a6,a5 -80011638: 00f3f7b3 and a5,t2,a5 -8001163c: 029403b3 mul t2,s0,s1 -80011640: 01081813 slli a6,a6,0x10 -80011644: 00f80833 add a6,a6,a5 -80011648: 02870433 mul s0,a4,s0 -8001164c: 029f04b3 mul s1,t5,s1 -80011650: 02ef0333 mul t1,t5,a4 -80011654: 008484b3 add s1,s1,s0 -80011658: 0103d713 srli a4,t2,0x10 -8001165c: 009704b3 add s1,a4,s1 -80011660: 0084f463 bgeu s1,s0,80011668 <__muldf3+0x344> -80011664: 00d30333 add t1,t1,a3 -80011668: 000107b7 lui a5,0x10 -8001166c: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -80011670: 00f4f6b3 and a3,s1,a5 -80011674: 01069693 slli a3,a3,0x10 -80011678: 00f3f7b3 and a5,t2,a5 -8001167c: 005e0e33 add t3,t3,t0 -80011680: 00f686b3 add a3,a3,a5 -80011684: 012e3933 sltu s2,t3,s2 -80011688: 01d686b3 add a3,a3,t4 -8001168c: 01268733 add a4,a3,s2 -80011690: 010e0e33 add t3,t3,a6 -80011694: 010e3833 sltu a6,t3,a6 -80011698: 01f70f33 add t5,a4,t6 -8001169c: 010f02b3 add t0,t5,a6 -800116a0: 01d6b6b3 sltu a3,a3,t4 -800116a4: 01273733 sltu a4,a4,s2 -800116a8: 00e6e733 or a4,a3,a4 -800116ac: 0102b833 sltu a6,t0,a6 -800116b0: 0104d493 srli s1,s1,0x10 -800116b4: 01ff3fb3 sltu t6,t5,t6 -800116b8: 00970733 add a4,a4,s1 -800116bc: 010fe833 or a6,t6,a6 -800116c0: 009e1793 slli a5,t3,0x9 -800116c4: 01070733 add a4,a4,a6 -800116c8: 00670733 add a4,a4,t1 -800116cc: 0117e7b3 or a5,a5,a7 -800116d0: 00971713 slli a4,a4,0x9 -800116d4: 00f037b3 snez a5,a5 -800116d8: 017e5e13 srli t3,t3,0x17 -800116dc: 0172d413 srli s0,t0,0x17 -800116e0: 01c7e7b3 or a5,a5,t3 -800116e4: 00929293 slli t0,t0,0x9 -800116e8: 00771693 slli a3,a4,0x7 -800116ec: 00876433 or s0,a4,s0 -800116f0: 0057e7b3 or a5,a5,t0 -800116f4: 1006d463 bgez a3,800117fc <__muldf3+0x4d8> -800116f8: 0017d713 srli a4,a5,0x1 -800116fc: 0017f793 andi a5,a5,1 -80011700: 00f767b3 or a5,a4,a5 -80011704: 01f41713 slli a4,s0,0x1f -80011708: 00e7e7b3 or a5,a5,a4 -8001170c: 00145413 srli s0,s0,0x1 -80011710: 3ff58693 addi a3,a1,1023 -80011714: 0ed05863 blez a3,80011804 <__muldf3+0x4e0> -80011718: 0077f713 andi a4,a5,7 -8001171c: 02070063 beqz a4,8001173c <__muldf3+0x418> -80011720: 00f7f713 andi a4,a5,15 -80011724: 00400513 li a0,4 -80011728: 00a70a63 beq a4,a0,8001173c <__muldf3+0x418> -8001172c: 00478713 addi a4,a5,4 -80011730: 00f737b3 sltu a5,a4,a5 -80011734: 00f40433 add s0,s0,a5 -80011738: 00070793 mv a5,a4 -8001173c: 00741713 slli a4,s0,0x7 -80011740: 00075a63 bgez a4,80011754 <__muldf3+0x430> -80011744: ff000737 lui a4,0xff000 -80011748: fff70713 addi a4,a4,-1 # feffffff <__BSS_END__+0x7efe93cf> -8001174c: 00e47433 and s0,s0,a4 -80011750: 40058693 addi a3,a1,1024 -80011754: 7fe00713 li a4,2046 -80011758: 16d74863 blt a4,a3,800118c8 <__muldf3+0x5a4> -8001175c: 0037d713 srli a4,a5,0x3 -80011760: 01d41793 slli a5,s0,0x1d -80011764: 00e7e7b3 or a5,a5,a4 -80011768: 00345413 srli s0,s0,0x3 -8001176c: 01469713 slli a4,a3,0x14 -80011770: 00c41413 slli s0,s0,0xc -80011774: 7ff006b7 lui a3,0x7ff00 -80011778: 00d77733 and a4,a4,a3 -8001177c: 00c45413 srli s0,s0,0xc -80011780: 00876433 or s0,a4,s0 -80011784: 01f61613 slli a2,a2,0x1f -80011788: 02c12083 lw ra,44(sp) -8001178c: 00c46733 or a4,s0,a2 -80011790: 02812403 lw s0,40(sp) -80011794: 02412483 lw s1,36(sp) -80011798: 02012903 lw s2,32(sp) -8001179c: 01c12983 lw s3,28(sp) -800117a0: 01812a03 lw s4,24(sp) -800117a4: 01412a83 lw s5,20(sp) -800117a8: 01012b03 lw s6,16(sp) -800117ac: 00c12b83 lw s7,12(sp) -800117b0: 00078513 mv a0,a5 -800117b4: 00070593 mv a1,a4 -800117b8: 03010113 addi sp,sp,48 -800117bc: 00008067 ret -800117c0: 000a0613 mv a2,s4 -800117c4: 00048413 mv s0,s1 -800117c8: 00090793 mv a5,s2 -800117cc: 000b8713 mv a4,s7 -800117d0: 00200693 li a3,2 -800117d4: 0ed70a63 beq a4,a3,800118c8 <__muldf3+0x5a4> -800117d8: 00300693 li a3,3 -800117dc: 0cd70c63 beq a4,a3,800118b4 <__muldf3+0x590> -800117e0: 00100693 li a3,1 -800117e4: f2d716e3 bne a4,a3,80011710 <__muldf3+0x3ec> -800117e8: 00000413 li s0,0 -800117ec: 00000793 li a5,0 -800117f0: 0880006f j 80011878 <__muldf3+0x554> -800117f4: 000a8613 mv a2,s5 -800117f8: fd9ff06f j 800117d0 <__muldf3+0x4ac> -800117fc: 00050593 mv a1,a0 -80011800: f11ff06f j 80011710 <__muldf3+0x3ec> -80011804: 00100513 li a0,1 -80011808: 40d50533 sub a0,a0,a3 -8001180c: 03800713 li a4,56 -80011810: fca74ce3 blt a4,a0,800117e8 <__muldf3+0x4c4> -80011814: 01f00713 li a4,31 -80011818: 06a74463 blt a4,a0,80011880 <__muldf3+0x55c> -8001181c: 41e58593 addi a1,a1,1054 -80011820: 00b41733 sll a4,s0,a1 -80011824: 00a7d6b3 srl a3,a5,a0 -80011828: 00b797b3 sll a5,a5,a1 -8001182c: 00d76733 or a4,a4,a3 -80011830: 00f037b3 snez a5,a5 -80011834: 00f767b3 or a5,a4,a5 -80011838: 00a45433 srl s0,s0,a0 -8001183c: 0077f713 andi a4,a5,7 -80011840: 02070063 beqz a4,80011860 <__muldf3+0x53c> -80011844: 00f7f713 andi a4,a5,15 -80011848: 00400693 li a3,4 -8001184c: 00d70a63 beq a4,a3,80011860 <__muldf3+0x53c> -80011850: 00478713 addi a4,a5,4 -80011854: 00f737b3 sltu a5,a4,a5 -80011858: 00f40433 add s0,s0,a5 -8001185c: 00070793 mv a5,a4 -80011860: 00841713 slli a4,s0,0x8 -80011864: 06074a63 bltz a4,800118d8 <__muldf3+0x5b4> -80011868: 01d41713 slli a4,s0,0x1d -8001186c: 0037d793 srli a5,a5,0x3 -80011870: 00f767b3 or a5,a4,a5 -80011874: 00345413 srli s0,s0,0x3 -80011878: 00000693 li a3,0 -8001187c: ef1ff06f j 8001176c <__muldf3+0x448> -80011880: fe100713 li a4,-31 -80011884: 40d70733 sub a4,a4,a3 -80011888: 02000813 li a6,32 -8001188c: 00e45733 srl a4,s0,a4 -80011890: 00000693 li a3,0 -80011894: 01050663 beq a0,a6,800118a0 <__muldf3+0x57c> -80011898: 43e58593 addi a1,a1,1086 -8001189c: 00b416b3 sll a3,s0,a1 -800118a0: 00f6e7b3 or a5,a3,a5 -800118a4: 00f037b3 snez a5,a5 -800118a8: 00f767b3 or a5,a4,a5 +800113e8 <__muldf3>: +800113e8: fd010113 addi sp,sp,-48 +800113ec: 0145d793 srli a5,a1,0x14 +800113f0: 02812423 sw s0,40(sp) +800113f4: 02912223 sw s1,36(sp) +800113f8: 01312e23 sw s3,28(sp) +800113fc: 01412c23 sw s4,24(sp) +80011400: 01512a23 sw s5,20(sp) +80011404: 00c59493 slli s1,a1,0xc +80011408: 02112623 sw ra,44(sp) +8001140c: 03212023 sw s2,32(sp) +80011410: 01612823 sw s6,16(sp) +80011414: 01712623 sw s7,12(sp) +80011418: 01579713 slli a4,a5,0x15 +8001141c: 00050413 mv s0,a0 +80011420: 00060993 mv s3,a2 +80011424: 00068a93 mv s5,a3 +80011428: 00c4d493 srli s1,s1,0xc +8001142c: 01f5da13 srli s4,a1,0x1f +80011430: 0a070663 beqz a4,800114dc <__muldf3+0xf4> +80011434: 7ff7fb13 andi s6,a5,2047 +80011438: 7ff00793 li a5,2047 +8001143c: 10fb0263 beq s6,a5,80011540 <__muldf3+0x158> +80011440: 01d55793 srli a5,a0,0x1d +80011444: 00349493 slli s1,s1,0x3 +80011448: 0097e4b3 or s1,a5,s1 +8001144c: 008007b7 lui a5,0x800 +80011450: 00f4e4b3 or s1,s1,a5 +80011454: 00351913 slli s2,a0,0x3 +80011458: c01b0b13 addi s6,s6,-1023 +8001145c: 00000b93 li s7,0 +80011460: 014ad793 srli a5,s5,0x14 +80011464: 00ca9413 slli s0,s5,0xc +80011468: 01579713 slli a4,a5,0x15 +8001146c: 00c45413 srli s0,s0,0xc +80011470: 7ff7f513 andi a0,a5,2047 +80011474: 01fada93 srli s5,s5,0x1f +80011478: 10070063 beqz a4,80011578 <__muldf3+0x190> +8001147c: 7ff00793 li a5,2047 +80011480: 16f50063 beq a0,a5,800115e0 <__muldf3+0x1f8> +80011484: 01d9d793 srli a5,s3,0x1d +80011488: 00341413 slli s0,s0,0x3 +8001148c: 0087e433 or s0,a5,s0 +80011490: 008007b7 lui a5,0x800 +80011494: 00f46433 or s0,s0,a5 +80011498: c0150513 addi a0,a0,-1023 # 7fc01 <_start-0x7ff803ff> +8001149c: 00399793 slli a5,s3,0x3 +800114a0: 00000713 li a4,0 +800114a4: 002b9693 slli a3,s7,0x2 +800114a8: 00e6e6b3 or a3,a3,a4 +800114ac: 00ab0533 add a0,s6,a0 +800114b0: fff68693 addi a3,a3,-1 +800114b4: 00e00813 li a6,14 +800114b8: 015a4633 xor a2,s4,s5 +800114bc: 00150593 addi a1,a0,1 +800114c0: 14d86c63 bltu a6,a3,80011618 <__muldf3+0x230> +800114c4: 80015537 lui a0,0x80015 +800114c8: 00269693 slli a3,a3,0x2 +800114cc: 7d450513 addi a0,a0,2004 # 800157d4 <__BSS_END__+0xffffeb98> +800114d0: 00a686b3 add a3,a3,a0 +800114d4: 0006a683 lw a3,0(a3) +800114d8: 00068067 jr a3 +800114dc: 00a4e933 or s2,s1,a0 +800114e0: 06090c63 beqz s2,80011558 <__muldf3+0x170> +800114e4: 04048063 beqz s1,80011524 <__muldf3+0x13c> +800114e8: 00048513 mv a0,s1 +800114ec: 4dc030ef jal ra,800149c8 <__clzsi2> +800114f0: ff550713 addi a4,a0,-11 +800114f4: 01c00793 li a5,28 +800114f8: 02e7cc63 blt a5,a4,80011530 <__muldf3+0x148> +800114fc: 01d00793 li a5,29 +80011500: ff850913 addi s2,a0,-8 +80011504: 40e787b3 sub a5,a5,a4 +80011508: 012494b3 sll s1,s1,s2 +8001150c: 00f457b3 srl a5,s0,a5 +80011510: 0097e4b3 or s1,a5,s1 +80011514: 01241933 sll s2,s0,s2 +80011518: c0d00b13 li s6,-1011 +8001151c: 40ab0b33 sub s6,s6,a0 +80011520: f3dff06f j 8001145c <__muldf3+0x74> +80011524: 4a4030ef jal ra,800149c8 <__clzsi2> +80011528: 02050513 addi a0,a0,32 +8001152c: fc5ff06f j 800114f0 <__muldf3+0x108> +80011530: fd850493 addi s1,a0,-40 +80011534: 009414b3 sll s1,s0,s1 +80011538: 00000913 li s2,0 +8001153c: fddff06f j 80011518 <__muldf3+0x130> +80011540: 00a4e933 or s2,s1,a0 +80011544: 02090263 beqz s2,80011568 <__muldf3+0x180> +80011548: 00050913 mv s2,a0 +8001154c: 7ff00b13 li s6,2047 +80011550: 00300b93 li s7,3 +80011554: f0dff06f j 80011460 <__muldf3+0x78> +80011558: 00000493 li s1,0 +8001155c: 00000b13 li s6,0 +80011560: 00100b93 li s7,1 +80011564: efdff06f j 80011460 <__muldf3+0x78> +80011568: 00000493 li s1,0 +8001156c: 7ff00b13 li s6,2047 +80011570: 00200b93 li s7,2 +80011574: eedff06f j 80011460 <__muldf3+0x78> +80011578: 013467b3 or a5,s0,s3 +8001157c: 06078e63 beqz a5,800115f8 <__muldf3+0x210> +80011580: 04040063 beqz s0,800115c0 <__muldf3+0x1d8> +80011584: 00040513 mv a0,s0 +80011588: 440030ef jal ra,800149c8 <__clzsi2> +8001158c: ff550693 addi a3,a0,-11 +80011590: 01c00793 li a5,28 +80011594: 02d7ce63 blt a5,a3,800115d0 <__muldf3+0x1e8> +80011598: 01d00713 li a4,29 +8001159c: ff850793 addi a5,a0,-8 +800115a0: 40d70733 sub a4,a4,a3 +800115a4: 00f41433 sll s0,s0,a5 +800115a8: 00e9d733 srl a4,s3,a4 +800115ac: 00876433 or s0,a4,s0 +800115b0: 00f997b3 sll a5,s3,a5 +800115b4: c0d00713 li a4,-1011 +800115b8: 40a70533 sub a0,a4,a0 +800115bc: ee5ff06f j 800114a0 <__muldf3+0xb8> +800115c0: 00098513 mv a0,s3 +800115c4: 404030ef jal ra,800149c8 <__clzsi2> +800115c8: 02050513 addi a0,a0,32 +800115cc: fc1ff06f j 8001158c <__muldf3+0x1a4> +800115d0: fd850413 addi s0,a0,-40 +800115d4: 00899433 sll s0,s3,s0 +800115d8: 00000793 li a5,0 +800115dc: fd9ff06f j 800115b4 <__muldf3+0x1cc> +800115e0: 013467b3 or a5,s0,s3 +800115e4: 02078263 beqz a5,80011608 <__muldf3+0x220> +800115e8: 00098793 mv a5,s3 +800115ec: 7ff00513 li a0,2047 +800115f0: 00300713 li a4,3 +800115f4: eb1ff06f j 800114a4 <__muldf3+0xbc> +800115f8: 00000413 li s0,0 +800115fc: 00000513 li a0,0 +80011600: 00100713 li a4,1 +80011604: ea1ff06f j 800114a4 <__muldf3+0xbc> +80011608: 00000413 li s0,0 +8001160c: 7ff00513 li a0,2047 +80011610: 00200713 li a4,2 +80011614: e91ff06f j 800114a4 <__muldf3+0xbc> +80011618: 00010f37 lui t5,0x10 +8001161c: ffff0713 addi a4,t5,-1 # ffff <_start-0x7fff0001> +80011620: 01095693 srli a3,s2,0x10 +80011624: 0107d313 srli t1,a5,0x10 +80011628: 00e97933 and s2,s2,a4 +8001162c: 00e7f7b3 and a5,a5,a4 +80011630: 032308b3 mul a7,t1,s2 +80011634: 02f90833 mul a6,s2,a5 +80011638: 02f68fb3 mul t6,a3,a5 +8001163c: 01f88eb3 add t4,a7,t6 +80011640: 01085893 srli a7,a6,0x10 +80011644: 01d888b3 add a7,a7,t4 +80011648: 02668e33 mul t3,a3,t1 +8001164c: 01f8f463 bgeu a7,t6,80011654 <__muldf3+0x26c> +80011650: 01ee0e33 add t3,t3,t5 +80011654: 0108d293 srli t0,a7,0x10 +80011658: 00e8f8b3 and a7,a7,a4 +8001165c: 00e87833 and a6,a6,a4 +80011660: 01045f13 srli t5,s0,0x10 +80011664: 01089893 slli a7,a7,0x10 +80011668: 00e47433 and s0,s0,a4 +8001166c: 010888b3 add a7,a7,a6 +80011670: 02868733 mul a4,a3,s0 +80011674: 02890833 mul a6,s2,s0 +80011678: 032f0933 mul s2,t5,s2 +8001167c: 00e90eb3 add t4,s2,a4 +80011680: 01085913 srli s2,a6,0x10 +80011684: 01d90933 add s2,s2,t4 +80011688: 03e686b3 mul a3,a3,t5 +8001168c: 00e97663 bgeu s2,a4,80011698 <__muldf3+0x2b0> +80011690: 00010737 lui a4,0x10 +80011694: 00e686b3 add a3,a3,a4 +80011698: 01095e93 srli t4,s2,0x10 +8001169c: 00de8eb3 add t4,t4,a3 +800116a0: 000106b7 lui a3,0x10 +800116a4: fff68f93 addi t6,a3,-1 # ffff <_start-0x7fff0001> +800116a8: 01f97933 and s2,s2,t6 +800116ac: 01f87833 and a6,a6,t6 +800116b0: 0104d713 srli a4,s1,0x10 +800116b4: 01091913 slli s2,s2,0x10 +800116b8: 01f4f4b3 and s1,s1,t6 +800116bc: 029783b3 mul t2,a5,s1 +800116c0: 01090933 add s2,s2,a6 +800116c4: 012282b3 add t0,t0,s2 +800116c8: 02930833 mul a6,t1,s1 +800116cc: 02f707b3 mul a5,a4,a5 +800116d0: 02e30fb3 mul t6,t1,a4 +800116d4: 00f80333 add t1,a6,a5 +800116d8: 0103d813 srli a6,t2,0x10 +800116dc: 00680833 add a6,a6,t1 +800116e0: 00f87463 bgeu a6,a5,800116e8 <__muldf3+0x300> +800116e4: 00df8fb3 add t6,t6,a3 +800116e8: 01085793 srli a5,a6,0x10 +800116ec: 000106b7 lui a3,0x10 +800116f0: 01f78fb3 add t6,a5,t6 +800116f4: fff68793 addi a5,a3,-1 # ffff <_start-0x7fff0001> +800116f8: 00f87833 and a6,a6,a5 +800116fc: 00f3f7b3 and a5,t2,a5 +80011700: 029403b3 mul t2,s0,s1 +80011704: 01081813 slli a6,a6,0x10 +80011708: 00f80833 add a6,a6,a5 +8001170c: 02870433 mul s0,a4,s0 +80011710: 029f04b3 mul s1,t5,s1 +80011714: 02ef0333 mul t1,t5,a4 +80011718: 008484b3 add s1,s1,s0 +8001171c: 0103d713 srli a4,t2,0x10 +80011720: 009704b3 add s1,a4,s1 +80011724: 0084f463 bgeu s1,s0,8001172c <__muldf3+0x344> +80011728: 00d30333 add t1,t1,a3 +8001172c: 000107b7 lui a5,0x10 +80011730: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +80011734: 00f4f6b3 and a3,s1,a5 +80011738: 01069693 slli a3,a3,0x10 +8001173c: 00f3f7b3 and a5,t2,a5 +80011740: 005e0e33 add t3,t3,t0 +80011744: 00f686b3 add a3,a3,a5 +80011748: 012e3933 sltu s2,t3,s2 +8001174c: 01d686b3 add a3,a3,t4 +80011750: 01268733 add a4,a3,s2 +80011754: 010e0e33 add t3,t3,a6 +80011758: 010e3833 sltu a6,t3,a6 +8001175c: 01f70f33 add t5,a4,t6 +80011760: 010f02b3 add t0,t5,a6 +80011764: 01d6b6b3 sltu a3,a3,t4 +80011768: 01273733 sltu a4,a4,s2 +8001176c: 00e6e733 or a4,a3,a4 +80011770: 0102b833 sltu a6,t0,a6 +80011774: 0104d493 srli s1,s1,0x10 +80011778: 01ff3fb3 sltu t6,t5,t6 +8001177c: 00970733 add a4,a4,s1 +80011780: 010fe833 or a6,t6,a6 +80011784: 009e1793 slli a5,t3,0x9 +80011788: 01070733 add a4,a4,a6 +8001178c: 00670733 add a4,a4,t1 +80011790: 0117e7b3 or a5,a5,a7 +80011794: 00971713 slli a4,a4,0x9 +80011798: 00f037b3 snez a5,a5 +8001179c: 017e5e13 srli t3,t3,0x17 +800117a0: 0172d413 srli s0,t0,0x17 +800117a4: 01c7e7b3 or a5,a5,t3 +800117a8: 00929293 slli t0,t0,0x9 +800117ac: 00771693 slli a3,a4,0x7 +800117b0: 00876433 or s0,a4,s0 +800117b4: 0057e7b3 or a5,a5,t0 +800117b8: 1006d463 bgez a3,800118c0 <__muldf3+0x4d8> +800117bc: 0017d713 srli a4,a5,0x1 +800117c0: 0017f793 andi a5,a5,1 +800117c4: 00f767b3 or a5,a4,a5 +800117c8: 01f41713 slli a4,s0,0x1f +800117cc: 00e7e7b3 or a5,a5,a4 +800117d0: 00145413 srli s0,s0,0x1 +800117d4: 3ff58693 addi a3,a1,1023 +800117d8: 0ed05863 blez a3,800118c8 <__muldf3+0x4e0> +800117dc: 0077f713 andi a4,a5,7 +800117e0: 02070063 beqz a4,80011800 <__muldf3+0x418> +800117e4: 00f7f713 andi a4,a5,15 +800117e8: 00400513 li a0,4 +800117ec: 00a70a63 beq a4,a0,80011800 <__muldf3+0x418> +800117f0: 00478713 addi a4,a5,4 +800117f4: 00f737b3 sltu a5,a4,a5 +800117f8: 00f40433 add s0,s0,a5 +800117fc: 00070793 mv a5,a4 +80011800: 00741713 slli a4,s0,0x7 +80011804: 00075a63 bgez a4,80011818 <__muldf3+0x430> +80011808: ff000737 lui a4,0xff000 +8001180c: fff70713 addi a4,a4,-1 # feffffff <__BSS_END__+0x7efe93c3> +80011810: 00e47433 and s0,s0,a4 +80011814: 40058693 addi a3,a1,1024 +80011818: 7fe00713 li a4,2046 +8001181c: 16d74863 blt a4,a3,8001198c <__muldf3+0x5a4> +80011820: 0037d713 srli a4,a5,0x3 +80011824: 01d41793 slli a5,s0,0x1d +80011828: 00e7e7b3 or a5,a5,a4 +8001182c: 00345413 srli s0,s0,0x3 +80011830: 01469713 slli a4,a3,0x14 +80011834: 00c41413 slli s0,s0,0xc +80011838: 7ff006b7 lui a3,0x7ff00 +8001183c: 00d77733 and a4,a4,a3 +80011840: 00c45413 srli s0,s0,0xc +80011844: 00876433 or s0,a4,s0 +80011848: 01f61613 slli a2,a2,0x1f +8001184c: 02c12083 lw ra,44(sp) +80011850: 00c46733 or a4,s0,a2 +80011854: 02812403 lw s0,40(sp) +80011858: 02412483 lw s1,36(sp) +8001185c: 02012903 lw s2,32(sp) +80011860: 01c12983 lw s3,28(sp) +80011864: 01812a03 lw s4,24(sp) +80011868: 01412a83 lw s5,20(sp) +8001186c: 01012b03 lw s6,16(sp) +80011870: 00c12b83 lw s7,12(sp) +80011874: 00078513 mv a0,a5 +80011878: 00070593 mv a1,a4 +8001187c: 03010113 addi sp,sp,48 +80011880: 00008067 ret +80011884: 000a0613 mv a2,s4 +80011888: 00048413 mv s0,s1 +8001188c: 00090793 mv a5,s2 +80011890: 000b8713 mv a4,s7 +80011894: 00200693 li a3,2 +80011898: 0ed70a63 beq a4,a3,8001198c <__muldf3+0x5a4> +8001189c: 00300693 li a3,3 +800118a0: 0cd70c63 beq a4,a3,80011978 <__muldf3+0x590> +800118a4: 00100693 li a3,1 +800118a8: f2d716e3 bne a4,a3,800117d4 <__muldf3+0x3ec> 800118ac: 00000413 li s0,0 -800118b0: f8dff06f j 8001183c <__muldf3+0x518> -800118b4: 00080437 lui s0,0x80 -800118b8: 00000793 li a5,0 -800118bc: 7ff00693 li a3,2047 -800118c0: 00000613 li a2,0 -800118c4: ea9ff06f j 8001176c <__muldf3+0x448> -800118c8: 00000413 li s0,0 -800118cc: 00000793 li a5,0 -800118d0: 7ff00693 li a3,2047 -800118d4: e99ff06f j 8001176c <__muldf3+0x448> -800118d8: 00000413 li s0,0 -800118dc: 00000793 li a5,0 -800118e0: 00100693 li a3,1 -800118e4: e89ff06f j 8001176c <__muldf3+0x448> +800118b0: 00000793 li a5,0 +800118b4: 0880006f j 8001193c <__muldf3+0x554> +800118b8: 000a8613 mv a2,s5 +800118bc: fd9ff06f j 80011894 <__muldf3+0x4ac> +800118c0: 00050593 mv a1,a0 +800118c4: f11ff06f j 800117d4 <__muldf3+0x3ec> +800118c8: 00100513 li a0,1 +800118cc: 40d50533 sub a0,a0,a3 +800118d0: 03800713 li a4,56 +800118d4: fca74ce3 blt a4,a0,800118ac <__muldf3+0x4c4> +800118d8: 01f00713 li a4,31 +800118dc: 06a74463 blt a4,a0,80011944 <__muldf3+0x55c> +800118e0: 41e58593 addi a1,a1,1054 +800118e4: 00b41733 sll a4,s0,a1 +800118e8: 00a7d6b3 srl a3,a5,a0 +800118ec: 00b797b3 sll a5,a5,a1 +800118f0: 00d76733 or a4,a4,a3 +800118f4: 00f037b3 snez a5,a5 +800118f8: 00f767b3 or a5,a4,a5 +800118fc: 00a45433 srl s0,s0,a0 +80011900: 0077f713 andi a4,a5,7 +80011904: 02070063 beqz a4,80011924 <__muldf3+0x53c> +80011908: 00f7f713 andi a4,a5,15 +8001190c: 00400693 li a3,4 +80011910: 00d70a63 beq a4,a3,80011924 <__muldf3+0x53c> +80011914: 00478713 addi a4,a5,4 +80011918: 00f737b3 sltu a5,a4,a5 +8001191c: 00f40433 add s0,s0,a5 +80011920: 00070793 mv a5,a4 +80011924: 00841713 slli a4,s0,0x8 +80011928: 06074a63 bltz a4,8001199c <__muldf3+0x5b4> +8001192c: 01d41713 slli a4,s0,0x1d +80011930: 0037d793 srli a5,a5,0x3 +80011934: 00f767b3 or a5,a4,a5 +80011938: 00345413 srli s0,s0,0x3 +8001193c: 00000693 li a3,0 +80011940: ef1ff06f j 80011830 <__muldf3+0x448> +80011944: fe100713 li a4,-31 +80011948: 40d70733 sub a4,a4,a3 +8001194c: 02000813 li a6,32 +80011950: 00e45733 srl a4,s0,a4 +80011954: 00000693 li a3,0 +80011958: 01050663 beq a0,a6,80011964 <__muldf3+0x57c> +8001195c: 43e58593 addi a1,a1,1086 +80011960: 00b416b3 sll a3,s0,a1 +80011964: 00f6e7b3 or a5,a3,a5 +80011968: 00f037b3 snez a5,a5 +8001196c: 00f767b3 or a5,a4,a5 +80011970: 00000413 li s0,0 +80011974: f8dff06f j 80011900 <__muldf3+0x518> +80011978: 00080437 lui s0,0x80 +8001197c: 00000793 li a5,0 +80011980: 7ff00693 li a3,2047 +80011984: 00000613 li a2,0 +80011988: ea9ff06f j 80011830 <__muldf3+0x448> +8001198c: 00000413 li s0,0 +80011990: 00000793 li a5,0 +80011994: 7ff00693 li a3,2047 +80011998: e99ff06f j 80011830 <__muldf3+0x448> +8001199c: 00000413 li s0,0 +800119a0: 00000793 li a5,0 +800119a4: 00100693 li a3,1 +800119a8: e89ff06f j 80011830 <__muldf3+0x448> -800118e8 <__eqtf2>: -800118e8: 00c52783 lw a5,12(a0) -800118ec: 0005af03 lw t5,0(a1) -800118f0: 0045af83 lw t6,4(a1) -800118f4: 0085a283 lw t0,8(a1) -800118f8: 00c5a583 lw a1,12(a1) -800118fc: 00008737 lui a4,0x8 -80011900: 0107d693 srli a3,a5,0x10 -80011904: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80011908: 01079813 slli a6,a5,0x10 -8001190c: 01059e93 slli t4,a1,0x10 -80011910: 01f7d613 srli a2,a5,0x1f -80011914: 00e6f6b3 and a3,a3,a4 -80011918: 0105d793 srli a5,a1,0x10 -8001191c: 00052883 lw a7,0(a0) -80011920: 00452303 lw t1,4(a0) -80011924: 00852e03 lw t3,8(a0) -80011928: ff010113 addi sp,sp,-16 -8001192c: 01085813 srli a6,a6,0x10 -80011930: 010ede93 srli t4,t4,0x10 -80011934: 00e7f7b3 and a5,a5,a4 -80011938: 01f5d593 srli a1,a1,0x1f -8001193c: 02e69063 bne a3,a4,8001195c <__eqtf2+0x74> -80011940: 0068e733 or a4,a7,t1 -80011944: 01c76733 or a4,a4,t3 -80011948: 01076733 or a4,a4,a6 -8001194c: 00100513 li a0,1 -80011950: 04071a63 bnez a4,800119a4 <__eqtf2+0xbc> -80011954: 04d79863 bne a5,a3,800119a4 <__eqtf2+0xbc> -80011958: 0080006f j 80011960 <__eqtf2+0x78> -8001195c: 00e79c63 bne a5,a4,80011974 <__eqtf2+0x8c> -80011960: 01ff6733 or a4,t5,t6 -80011964: 00576733 or a4,a4,t0 -80011968: 01d76733 or a4,a4,t4 -8001196c: 00100513 li a0,1 -80011970: 02071a63 bnez a4,800119a4 <__eqtf2+0xbc> -80011974: 00100513 li a0,1 -80011978: 02d79663 bne a5,a3,800119a4 <__eqtf2+0xbc> -8001197c: 03e89463 bne a7,t5,800119a4 <__eqtf2+0xbc> -80011980: 03f31263 bne t1,t6,800119a4 <__eqtf2+0xbc> -80011984: 025e1063 bne t3,t0,800119a4 <__eqtf2+0xbc> -80011988: 01d81e63 bne a6,t4,800119a4 <__eqtf2+0xbc> -8001198c: 02b60063 beq a2,a1,800119ac <__eqtf2+0xc4> -80011990: 00079a63 bnez a5,800119a4 <__eqtf2+0xbc> -80011994: 0068e533 or a0,a7,t1 -80011998: 01c56533 or a0,a0,t3 -8001199c: 01056533 or a0,a0,a6 -800119a0: 00a03533 snez a0,a0 -800119a4: 01010113 addi sp,sp,16 -800119a8: 00008067 ret -800119ac: 00000513 li a0,0 -800119b0: ff5ff06f j 800119a4 <__eqtf2+0xbc> +800119ac <__eqtf2>: +800119ac: 00c52783 lw a5,12(a0) +800119b0: 0005af03 lw t5,0(a1) +800119b4: 0045af83 lw t6,4(a1) +800119b8: 0085a283 lw t0,8(a1) +800119bc: 00c5a583 lw a1,12(a1) +800119c0: 00008737 lui a4,0x8 +800119c4: 0107d693 srli a3,a5,0x10 +800119c8: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +800119cc: 01079813 slli a6,a5,0x10 +800119d0: 01059e93 slli t4,a1,0x10 +800119d4: 01f7d613 srli a2,a5,0x1f +800119d8: 00e6f6b3 and a3,a3,a4 +800119dc: 0105d793 srli a5,a1,0x10 +800119e0: 00052883 lw a7,0(a0) +800119e4: 00452303 lw t1,4(a0) +800119e8: 00852e03 lw t3,8(a0) +800119ec: ff010113 addi sp,sp,-16 +800119f0: 01085813 srli a6,a6,0x10 +800119f4: 010ede93 srli t4,t4,0x10 +800119f8: 00e7f7b3 and a5,a5,a4 +800119fc: 01f5d593 srli a1,a1,0x1f +80011a00: 02e69063 bne a3,a4,80011a20 <__eqtf2+0x74> +80011a04: 0068e733 or a4,a7,t1 +80011a08: 01c76733 or a4,a4,t3 +80011a0c: 01076733 or a4,a4,a6 +80011a10: 00100513 li a0,1 +80011a14: 04071a63 bnez a4,80011a68 <__eqtf2+0xbc> +80011a18: 04d79863 bne a5,a3,80011a68 <__eqtf2+0xbc> +80011a1c: 0080006f j 80011a24 <__eqtf2+0x78> +80011a20: 00e79c63 bne a5,a4,80011a38 <__eqtf2+0x8c> +80011a24: 01ff6733 or a4,t5,t6 +80011a28: 00576733 or a4,a4,t0 +80011a2c: 01d76733 or a4,a4,t4 +80011a30: 00100513 li a0,1 +80011a34: 02071a63 bnez a4,80011a68 <__eqtf2+0xbc> +80011a38: 00100513 li a0,1 +80011a3c: 02d79663 bne a5,a3,80011a68 <__eqtf2+0xbc> +80011a40: 03e89463 bne a7,t5,80011a68 <__eqtf2+0xbc> +80011a44: 03f31263 bne t1,t6,80011a68 <__eqtf2+0xbc> +80011a48: 025e1063 bne t3,t0,80011a68 <__eqtf2+0xbc> +80011a4c: 01d81e63 bne a6,t4,80011a68 <__eqtf2+0xbc> +80011a50: 02b60063 beq a2,a1,80011a70 <__eqtf2+0xc4> +80011a54: 00079a63 bnez a5,80011a68 <__eqtf2+0xbc> +80011a58: 0068e533 or a0,a7,t1 +80011a5c: 01c56533 or a0,a0,t3 +80011a60: 01056533 or a0,a0,a6 +80011a64: 00a03533 snez a0,a0 +80011a68: 01010113 addi sp,sp,16 +80011a6c: 00008067 ret +80011a70: 00000513 li a0,0 +80011a74: ff5ff06f j 80011a68 <__eqtf2+0xbc> -800119b4 <__getf2>: -800119b4: 00052f83 lw t6,0(a0) -800119b8: 00452803 lw a6,4(a0) -800119bc: 00852e03 lw t3,8(a0) -800119c0: 00c52503 lw a0,12(a0) -800119c4: 00c5a683 lw a3,12(a1) -800119c8: 000087b7 lui a5,0x8 -800119cc: 01055613 srli a2,a0,0x10 -800119d0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800119d4: 01069313 slli t1,a3,0x10 -800119d8: 0106d713 srli a4,a3,0x10 -800119dc: 0005a283 lw t0,0(a1) -800119e0: 0045a883 lw a7,4(a1) -800119e4: 0085ae83 lw t4,8(a1) -800119e8: 00f67633 and a2,a2,a5 -800119ec: 01051593 slli a1,a0,0x10 -800119f0: ff010113 addi sp,sp,-16 -800119f4: 0105d593 srli a1,a1,0x10 -800119f8: 01f55513 srli a0,a0,0x1f -800119fc: 01035313 srli t1,t1,0x10 -80011a00: 00f77733 and a4,a4,a5 -80011a04: 01f6d693 srli a3,a3,0x1f -80011a08: 00f61e63 bne a2,a5,80011a24 <__getf2+0x70> -80011a0c: 010fe7b3 or a5,t6,a6 -80011a10: 01c7e7b3 or a5,a5,t3 -80011a14: 00b7e7b3 or a5,a5,a1 -80011a18: 0c078863 beqz a5,80011ae8 <__getf2+0x134> -80011a1c: ffe00513 li a0,-2 -80011a20: 0640006f j 80011a84 <__getf2+0xd0> -80011a24: 00f71a63 bne a4,a5,80011a38 <__getf2+0x84> -80011a28: 0112e7b3 or a5,t0,a7 -80011a2c: 01d7e7b3 or a5,a5,t4 -80011a30: 0067e7b3 or a5,a5,t1 -80011a34: fe0794e3 bnez a5,80011a1c <__getf2+0x68> -80011a38: 0a061a63 bnez a2,80011aec <__getf2+0x138> -80011a3c: 010fe7b3 or a5,t6,a6 -80011a40: 01c7e7b3 or a5,a5,t3 -80011a44: 00b7e7b3 or a5,a5,a1 -80011a48: 0017b793 seqz a5,a5 -80011a4c: 00071a63 bnez a4,80011a60 <__getf2+0xac> -80011a50: 0112ef33 or t5,t0,a7 -80011a54: 01df6f33 or t5,t5,t4 -80011a58: 006f6f33 or t5,t5,t1 -80011a5c: 060f0a63 beqz t5,80011ad0 <__getf2+0x11c> -80011a60: 00079c63 bnez a5,80011a78 <__getf2+0xc4> -80011a64: 00a69463 bne a3,a0,80011a6c <__getf2+0xb8> -80011a68: 02c75263 bge a4,a2,80011a8c <__getf2+0xd8> -80011a6c: 04050e63 beqz a0,80011ac8 <__getf2+0x114> -80011a70: fff00513 li a0,-1 -80011a74: 0100006f j 80011a84 <__getf2+0xd0> -80011a78: fff00513 li a0,-1 -80011a7c: 00068463 beqz a3,80011a84 <__getf2+0xd0> -80011a80: 00068513 mv a0,a3 -80011a84: 01010113 addi sp,sp,16 -80011a88: 00008067 ret -80011a8c: 00e65663 bge a2,a4,80011a98 <__getf2+0xe4> -80011a90: fe051ae3 bnez a0,80011a84 <__getf2+0xd0> -80011a94: fddff06f j 80011a70 <__getf2+0xbc> -80011a98: fcb36ae3 bltu t1,a1,80011a6c <__getf2+0xb8> -80011a9c: 02659e63 bne a1,t1,80011ad8 <__getf2+0x124> -80011aa0: fdcee6e3 bltu t4,t3,80011a6c <__getf2+0xb8> -80011aa4: 03de1e63 bne t3,t4,80011ae0 <__getf2+0x12c> -80011aa8: fd08e2e3 bltu a7,a6,80011a6c <__getf2+0xb8> -80011aac: 01181463 bne a6,a7,80011ab4 <__getf2+0x100> -80011ab0: fbf2eee3 bltu t0,t6,80011a6c <__getf2+0xb8> -80011ab4: fd186ee3 bltu a6,a7,80011a90 <__getf2+0xdc> -80011ab8: 01181463 bne a6,a7,80011ac0 <__getf2+0x10c> -80011abc: fc5feae3 bltu t6,t0,80011a90 <__getf2+0xdc> -80011ac0: 00000513 li a0,0 -80011ac4: fc1ff06f j 80011a84 <__getf2+0xd0> -80011ac8: 00100513 li a0,1 -80011acc: fb9ff06f j 80011a84 <__getf2+0xd0> -80011ad0: fe0798e3 bnez a5,80011ac0 <__getf2+0x10c> -80011ad4: f99ff06f j 80011a6c <__getf2+0xb8> -80011ad8: fa65ece3 bltu a1,t1,80011a90 <__getf2+0xdc> -80011adc: fe5ff06f j 80011ac0 <__getf2+0x10c> -80011ae0: fbde68e3 bltu t3,t4,80011a90 <__getf2+0xdc> -80011ae4: fddff06f j 80011ac0 <__getf2+0x10c> -80011ae8: f4c700e3 beq a4,a2,80011a28 <__getf2+0x74> -80011aec: f6071ce3 bnez a4,80011a64 <__getf2+0xb0> -80011af0: 00000793 li a5,0 -80011af4: f5dff06f j 80011a50 <__getf2+0x9c> +80011a78 <__getf2>: +80011a78: 00052f83 lw t6,0(a0) +80011a7c: 00452803 lw a6,4(a0) +80011a80: 00852e03 lw t3,8(a0) +80011a84: 00c52503 lw a0,12(a0) +80011a88: 00c5a683 lw a3,12(a1) +80011a8c: 000087b7 lui a5,0x8 +80011a90: 01055613 srli a2,a0,0x10 +80011a94: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80011a98: 01069313 slli t1,a3,0x10 +80011a9c: 0106d713 srli a4,a3,0x10 +80011aa0: 0005a283 lw t0,0(a1) +80011aa4: 0045a883 lw a7,4(a1) +80011aa8: 0085ae83 lw t4,8(a1) +80011aac: 00f67633 and a2,a2,a5 +80011ab0: 01051593 slli a1,a0,0x10 +80011ab4: ff010113 addi sp,sp,-16 +80011ab8: 0105d593 srli a1,a1,0x10 +80011abc: 01f55513 srli a0,a0,0x1f +80011ac0: 01035313 srli t1,t1,0x10 +80011ac4: 00f77733 and a4,a4,a5 +80011ac8: 01f6d693 srli a3,a3,0x1f +80011acc: 00f61e63 bne a2,a5,80011ae8 <__getf2+0x70> +80011ad0: 010fe7b3 or a5,t6,a6 +80011ad4: 01c7e7b3 or a5,a5,t3 +80011ad8: 00b7e7b3 or a5,a5,a1 +80011adc: 0c078863 beqz a5,80011bac <__getf2+0x134> +80011ae0: ffe00513 li a0,-2 +80011ae4: 0640006f j 80011b48 <__getf2+0xd0> +80011ae8: 00f71a63 bne a4,a5,80011afc <__getf2+0x84> +80011aec: 0112e7b3 or a5,t0,a7 +80011af0: 01d7e7b3 or a5,a5,t4 +80011af4: 0067e7b3 or a5,a5,t1 +80011af8: fe0794e3 bnez a5,80011ae0 <__getf2+0x68> +80011afc: 0a061a63 bnez a2,80011bb0 <__getf2+0x138> +80011b00: 010fe7b3 or a5,t6,a6 +80011b04: 01c7e7b3 or a5,a5,t3 +80011b08: 00b7e7b3 or a5,a5,a1 +80011b0c: 0017b793 seqz a5,a5 +80011b10: 00071a63 bnez a4,80011b24 <__getf2+0xac> +80011b14: 0112ef33 or t5,t0,a7 +80011b18: 01df6f33 or t5,t5,t4 +80011b1c: 006f6f33 or t5,t5,t1 +80011b20: 060f0a63 beqz t5,80011b94 <__getf2+0x11c> +80011b24: 00079c63 bnez a5,80011b3c <__getf2+0xc4> +80011b28: 00a69463 bne a3,a0,80011b30 <__getf2+0xb8> +80011b2c: 02c75263 bge a4,a2,80011b50 <__getf2+0xd8> +80011b30: 04050e63 beqz a0,80011b8c <__getf2+0x114> +80011b34: fff00513 li a0,-1 +80011b38: 0100006f j 80011b48 <__getf2+0xd0> +80011b3c: fff00513 li a0,-1 +80011b40: 00068463 beqz a3,80011b48 <__getf2+0xd0> +80011b44: 00068513 mv a0,a3 +80011b48: 01010113 addi sp,sp,16 +80011b4c: 00008067 ret +80011b50: 00e65663 bge a2,a4,80011b5c <__getf2+0xe4> +80011b54: fe051ae3 bnez a0,80011b48 <__getf2+0xd0> +80011b58: fddff06f j 80011b34 <__getf2+0xbc> +80011b5c: fcb36ae3 bltu t1,a1,80011b30 <__getf2+0xb8> +80011b60: 02659e63 bne a1,t1,80011b9c <__getf2+0x124> +80011b64: fdcee6e3 bltu t4,t3,80011b30 <__getf2+0xb8> +80011b68: 03de1e63 bne t3,t4,80011ba4 <__getf2+0x12c> +80011b6c: fd08e2e3 bltu a7,a6,80011b30 <__getf2+0xb8> +80011b70: 01181463 bne a6,a7,80011b78 <__getf2+0x100> +80011b74: fbf2eee3 bltu t0,t6,80011b30 <__getf2+0xb8> +80011b78: fd186ee3 bltu a6,a7,80011b54 <__getf2+0xdc> +80011b7c: 01181463 bne a6,a7,80011b84 <__getf2+0x10c> +80011b80: fc5feae3 bltu t6,t0,80011b54 <__getf2+0xdc> +80011b84: 00000513 li a0,0 +80011b88: fc1ff06f j 80011b48 <__getf2+0xd0> +80011b8c: 00100513 li a0,1 +80011b90: fb9ff06f j 80011b48 <__getf2+0xd0> +80011b94: fe0798e3 bnez a5,80011b84 <__getf2+0x10c> +80011b98: f99ff06f j 80011b30 <__getf2+0xb8> +80011b9c: fa65ece3 bltu a1,t1,80011b54 <__getf2+0xdc> +80011ba0: fe5ff06f j 80011b84 <__getf2+0x10c> +80011ba4: fbde68e3 bltu t3,t4,80011b54 <__getf2+0xdc> +80011ba8: fddff06f j 80011b84 <__getf2+0x10c> +80011bac: f4c700e3 beq a4,a2,80011aec <__getf2+0x74> +80011bb0: f6071ce3 bnez a4,80011b28 <__getf2+0xb0> +80011bb4: 00000793 li a5,0 +80011bb8: f5dff06f j 80011b14 <__getf2+0x9c> -80011af8 <__letf2>: -80011af8: 00052f83 lw t6,0(a0) -80011afc: 00452803 lw a6,4(a0) -80011b00: 00852e03 lw t3,8(a0) -80011b04: 00c52503 lw a0,12(a0) -80011b08: 00c5a683 lw a3,12(a1) -80011b0c: 000087b7 lui a5,0x8 -80011b10: 01055613 srli a2,a0,0x10 -80011b14: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80011b18: 01069313 slli t1,a3,0x10 -80011b1c: 0106d713 srli a4,a3,0x10 -80011b20: 0005a283 lw t0,0(a1) -80011b24: 0045a883 lw a7,4(a1) -80011b28: 0085ae83 lw t4,8(a1) -80011b2c: 00f67633 and a2,a2,a5 -80011b30: 01051593 slli a1,a0,0x10 -80011b34: ff010113 addi sp,sp,-16 -80011b38: 0105d593 srli a1,a1,0x10 -80011b3c: 01f55513 srli a0,a0,0x1f -80011b40: 01035313 srli t1,t1,0x10 -80011b44: 00f77733 and a4,a4,a5 -80011b48: 01f6d693 srli a3,a3,0x1f -80011b4c: 00f61e63 bne a2,a5,80011b68 <__letf2+0x70> -80011b50: 010fe7b3 or a5,t6,a6 -80011b54: 01c7e7b3 or a5,a5,t3 -80011b58: 00b7e7b3 or a5,a5,a1 -80011b5c: 0c078863 beqz a5,80011c2c <__letf2+0x134> -80011b60: 00200513 li a0,2 -80011b64: 0640006f j 80011bc8 <__letf2+0xd0> -80011b68: 00f71a63 bne a4,a5,80011b7c <__letf2+0x84> -80011b6c: 0112e7b3 or a5,t0,a7 -80011b70: 01d7e7b3 or a5,a5,t4 -80011b74: 0067e7b3 or a5,a5,t1 -80011b78: fe0794e3 bnez a5,80011b60 <__letf2+0x68> -80011b7c: 0a061a63 bnez a2,80011c30 <__letf2+0x138> -80011b80: 010fe7b3 or a5,t6,a6 -80011b84: 01c7e7b3 or a5,a5,t3 -80011b88: 00b7e7b3 or a5,a5,a1 -80011b8c: 0017b793 seqz a5,a5 -80011b90: 00071a63 bnez a4,80011ba4 <__letf2+0xac> -80011b94: 0112ef33 or t5,t0,a7 -80011b98: 01df6f33 or t5,t5,t4 -80011b9c: 006f6f33 or t5,t5,t1 -80011ba0: 060f0a63 beqz t5,80011c14 <__letf2+0x11c> -80011ba4: 00079c63 bnez a5,80011bbc <__letf2+0xc4> -80011ba8: 00a69463 bne a3,a0,80011bb0 <__letf2+0xb8> -80011bac: 02c75263 bge a4,a2,80011bd0 <__letf2+0xd8> -80011bb0: 04050e63 beqz a0,80011c0c <__letf2+0x114> -80011bb4: fff00513 li a0,-1 -80011bb8: 0100006f j 80011bc8 <__letf2+0xd0> -80011bbc: fff00513 li a0,-1 -80011bc0: 00068463 beqz a3,80011bc8 <__letf2+0xd0> -80011bc4: 00068513 mv a0,a3 -80011bc8: 01010113 addi sp,sp,16 -80011bcc: 00008067 ret -80011bd0: 00e65663 bge a2,a4,80011bdc <__letf2+0xe4> -80011bd4: fe051ae3 bnez a0,80011bc8 <__letf2+0xd0> -80011bd8: fddff06f j 80011bb4 <__letf2+0xbc> -80011bdc: fcb36ae3 bltu t1,a1,80011bb0 <__letf2+0xb8> -80011be0: 02659e63 bne a1,t1,80011c1c <__letf2+0x124> -80011be4: fdcee6e3 bltu t4,t3,80011bb0 <__letf2+0xb8> -80011be8: 03de1e63 bne t3,t4,80011c24 <__letf2+0x12c> -80011bec: fd08e2e3 bltu a7,a6,80011bb0 <__letf2+0xb8> -80011bf0: 01181463 bne a6,a7,80011bf8 <__letf2+0x100> -80011bf4: fbf2eee3 bltu t0,t6,80011bb0 <__letf2+0xb8> -80011bf8: fd186ee3 bltu a6,a7,80011bd4 <__letf2+0xdc> -80011bfc: 01181463 bne a6,a7,80011c04 <__letf2+0x10c> -80011c00: fc5feae3 bltu t6,t0,80011bd4 <__letf2+0xdc> -80011c04: 00000513 li a0,0 -80011c08: fc1ff06f j 80011bc8 <__letf2+0xd0> -80011c0c: 00100513 li a0,1 -80011c10: fb9ff06f j 80011bc8 <__letf2+0xd0> -80011c14: fe0798e3 bnez a5,80011c04 <__letf2+0x10c> -80011c18: f99ff06f j 80011bb0 <__letf2+0xb8> -80011c1c: fa65ece3 bltu a1,t1,80011bd4 <__letf2+0xdc> -80011c20: fe5ff06f j 80011c04 <__letf2+0x10c> -80011c24: fbde68e3 bltu t3,t4,80011bd4 <__letf2+0xdc> -80011c28: fddff06f j 80011c04 <__letf2+0x10c> -80011c2c: f4c700e3 beq a4,a2,80011b6c <__letf2+0x74> -80011c30: f6071ce3 bnez a4,80011ba8 <__letf2+0xb0> -80011c34: 00000793 li a5,0 -80011c38: f5dff06f j 80011b94 <__letf2+0x9c> +80011bbc <__letf2>: +80011bbc: 00052f83 lw t6,0(a0) +80011bc0: 00452803 lw a6,4(a0) +80011bc4: 00852e03 lw t3,8(a0) +80011bc8: 00c52503 lw a0,12(a0) +80011bcc: 00c5a683 lw a3,12(a1) +80011bd0: 000087b7 lui a5,0x8 +80011bd4: 01055613 srli a2,a0,0x10 +80011bd8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80011bdc: 01069313 slli t1,a3,0x10 +80011be0: 0106d713 srli a4,a3,0x10 +80011be4: 0005a283 lw t0,0(a1) +80011be8: 0045a883 lw a7,4(a1) +80011bec: 0085ae83 lw t4,8(a1) +80011bf0: 00f67633 and a2,a2,a5 +80011bf4: 01051593 slli a1,a0,0x10 +80011bf8: ff010113 addi sp,sp,-16 +80011bfc: 0105d593 srli a1,a1,0x10 +80011c00: 01f55513 srli a0,a0,0x1f +80011c04: 01035313 srli t1,t1,0x10 +80011c08: 00f77733 and a4,a4,a5 +80011c0c: 01f6d693 srli a3,a3,0x1f +80011c10: 00f61e63 bne a2,a5,80011c2c <__letf2+0x70> +80011c14: 010fe7b3 or a5,t6,a6 +80011c18: 01c7e7b3 or a5,a5,t3 +80011c1c: 00b7e7b3 or a5,a5,a1 +80011c20: 0c078863 beqz a5,80011cf0 <__letf2+0x134> +80011c24: 00200513 li a0,2 +80011c28: 0640006f j 80011c8c <__letf2+0xd0> +80011c2c: 00f71a63 bne a4,a5,80011c40 <__letf2+0x84> +80011c30: 0112e7b3 or a5,t0,a7 +80011c34: 01d7e7b3 or a5,a5,t4 +80011c38: 0067e7b3 or a5,a5,t1 +80011c3c: fe0794e3 bnez a5,80011c24 <__letf2+0x68> +80011c40: 0a061a63 bnez a2,80011cf4 <__letf2+0x138> +80011c44: 010fe7b3 or a5,t6,a6 +80011c48: 01c7e7b3 or a5,a5,t3 +80011c4c: 00b7e7b3 or a5,a5,a1 +80011c50: 0017b793 seqz a5,a5 +80011c54: 00071a63 bnez a4,80011c68 <__letf2+0xac> +80011c58: 0112ef33 or t5,t0,a7 +80011c5c: 01df6f33 or t5,t5,t4 +80011c60: 006f6f33 or t5,t5,t1 +80011c64: 060f0a63 beqz t5,80011cd8 <__letf2+0x11c> +80011c68: 00079c63 bnez a5,80011c80 <__letf2+0xc4> +80011c6c: 00a69463 bne a3,a0,80011c74 <__letf2+0xb8> +80011c70: 02c75263 bge a4,a2,80011c94 <__letf2+0xd8> +80011c74: 04050e63 beqz a0,80011cd0 <__letf2+0x114> +80011c78: fff00513 li a0,-1 +80011c7c: 0100006f j 80011c8c <__letf2+0xd0> +80011c80: fff00513 li a0,-1 +80011c84: 00068463 beqz a3,80011c8c <__letf2+0xd0> +80011c88: 00068513 mv a0,a3 +80011c8c: 01010113 addi sp,sp,16 +80011c90: 00008067 ret +80011c94: 00e65663 bge a2,a4,80011ca0 <__letf2+0xe4> +80011c98: fe051ae3 bnez a0,80011c8c <__letf2+0xd0> +80011c9c: fddff06f j 80011c78 <__letf2+0xbc> +80011ca0: fcb36ae3 bltu t1,a1,80011c74 <__letf2+0xb8> +80011ca4: 02659e63 bne a1,t1,80011ce0 <__letf2+0x124> +80011ca8: fdcee6e3 bltu t4,t3,80011c74 <__letf2+0xb8> +80011cac: 03de1e63 bne t3,t4,80011ce8 <__letf2+0x12c> +80011cb0: fd08e2e3 bltu a7,a6,80011c74 <__letf2+0xb8> +80011cb4: 01181463 bne a6,a7,80011cbc <__letf2+0x100> +80011cb8: fbf2eee3 bltu t0,t6,80011c74 <__letf2+0xb8> +80011cbc: fd186ee3 bltu a6,a7,80011c98 <__letf2+0xdc> +80011cc0: 01181463 bne a6,a7,80011cc8 <__letf2+0x10c> +80011cc4: fc5feae3 bltu t6,t0,80011c98 <__letf2+0xdc> +80011cc8: 00000513 li a0,0 +80011ccc: fc1ff06f j 80011c8c <__letf2+0xd0> +80011cd0: 00100513 li a0,1 +80011cd4: fb9ff06f j 80011c8c <__letf2+0xd0> +80011cd8: fe0798e3 bnez a5,80011cc8 <__letf2+0x10c> +80011cdc: f99ff06f j 80011c74 <__letf2+0xb8> +80011ce0: fa65ece3 bltu a1,t1,80011c98 <__letf2+0xdc> +80011ce4: fe5ff06f j 80011cc8 <__letf2+0x10c> +80011ce8: fbde68e3 bltu t3,t4,80011c98 <__letf2+0xdc> +80011cec: fddff06f j 80011cc8 <__letf2+0x10c> +80011cf0: f4c700e3 beq a4,a2,80011c30 <__letf2+0x74> +80011cf4: f6071ce3 bnez a4,80011c6c <__letf2+0xb0> +80011cf8: 00000793 li a5,0 +80011cfc: f5dff06f j 80011c58 <__letf2+0x9c> -80011c3c <__multf3>: -80011c3c: f4010113 addi sp,sp,-192 -80011c40: 0a912a23 sw s1,180(sp) -80011c44: 00c5a483 lw s1,12(a1) -80011c48: 0005a683 lw a3,0(a1) -80011c4c: 0045a783 lw a5,4(a1) -80011c50: 00a12423 sw a0,8(sp) -80011c54: 0085a503 lw a0,8(a1) -80011c58: 01049713 slli a4,s1,0x10 -80011c5c: 0b212823 sw s2,176(sp) -80011c60: 0b312623 sw s3,172(sp) -80011c64: 00c62903 lw s2,12(a2) # 7ff0000c <_start-0xffff4> -80011c68: 00062983 lw s3,0(a2) -80011c6c: 0b412423 sw s4,168(sp) -80011c70: 0b512223 sw s5,164(sp) -80011c74: 00862a03 lw s4,8(a2) -80011c78: 00462a83 lw s5,4(a2) -80011c7c: 00008637 lui a2,0x8 -80011c80: 0a812c23 sw s0,184(sp) -80011c84: 01075713 srli a4,a4,0x10 -80011c88: 0104d413 srli s0,s1,0x10 -80011c8c: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> -80011c90: 06912623 sw s1,108(sp) -80011c94: 0a112e23 sw ra,188(sp) -80011c98: 0b612023 sw s6,160(sp) -80011c9c: 09712e23 sw s7,156(sp) -80011ca0: 09812c23 sw s8,152(sp) -80011ca4: 09912a23 sw s9,148(sp) -80011ca8: 09a12823 sw s10,144(sp) -80011cac: 09b12623 sw s11,140(sp) -80011cb0: 06d12023 sw a3,96(sp) -80011cb4: 06f12223 sw a5,100(sp) -80011cb8: 06a12423 sw a0,104(sp) -80011cbc: 02d12823 sw a3,48(sp) -80011cc0: 02f12a23 sw a5,52(sp) -80011cc4: 02a12c23 sw a0,56(sp) -80011cc8: 02e12e23 sw a4,60(sp) -80011ccc: 00c47433 and s0,s0,a2 -80011cd0: 01f4d493 srli s1,s1,0x1f -80011cd4: 12040863 beqz s0,80011e04 <__multf3+0x1c8> -80011cd8: 24c40663 beq s0,a2,80011f24 <__multf3+0x2e8> -80011cdc: 000107b7 lui a5,0x10 -80011ce0: 00f767b3 or a5,a4,a5 -80011ce4: 02f12e23 sw a5,60(sp) -80011ce8: 03010613 addi a2,sp,48 -80011cec: 03c10793 addi a5,sp,60 -80011cf0: 0007a703 lw a4,0(a5) # 10000 <_start-0x7fff0000> -80011cf4: ffc7a683 lw a3,-4(a5) -80011cf8: ffc78793 addi a5,a5,-4 -80011cfc: 00371713 slli a4,a4,0x3 -80011d00: 01d6d693 srli a3,a3,0x1d -80011d04: 00d76733 or a4,a4,a3 -80011d08: 00e7a223 sw a4,4(a5) -80011d0c: fef612e3 bne a2,a5,80011cf0 <__multf3+0xb4> -80011d10: 03012783 lw a5,48(sp) -80011d14: ffffc537 lui a0,0xffffc -80011d18: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe53d1> -80011d1c: 00379793 slli a5,a5,0x3 -80011d20: 02f12823 sw a5,48(sp) -80011d24: 00a40433 add s0,s0,a0 -80011d28: 00000b13 li s6,0 -80011d2c: 01091513 slli a0,s2,0x10 -80011d30: 00008737 lui a4,0x8 -80011d34: 01095793 srli a5,s2,0x10 -80011d38: 01055513 srli a0,a0,0x10 -80011d3c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80011d40: 07212623 sw s2,108(sp) -80011d44: 07312023 sw s3,96(sp) -80011d48: 07512223 sw s5,100(sp) -80011d4c: 07412423 sw s4,104(sp) -80011d50: 05312023 sw s3,64(sp) -80011d54: 05512223 sw s5,68(sp) -80011d58: 05412423 sw s4,72(sp) -80011d5c: 04a12623 sw a0,76(sp) -80011d60: 00e7f7b3 and a5,a5,a4 -80011d64: 01f95913 srli s2,s2,0x1f -80011d68: 1e078263 beqz a5,80011f4c <__multf3+0x310> -80011d6c: 30e78063 beq a5,a4,8001206c <__multf3+0x430> -80011d70: 00010a37 lui s4,0x10 -80011d74: 01456a33 or s4,a0,s4 -80011d78: 05412623 sw s4,76(sp) -80011d7c: 04010593 addi a1,sp,64 -80011d80: 04c10713 addi a4,sp,76 -80011d84: 00072683 lw a3,0(a4) -80011d88: ffc72603 lw a2,-4(a4) -80011d8c: ffc70713 addi a4,a4,-4 -80011d90: 00369693 slli a3,a3,0x3 -80011d94: 01d65613 srli a2,a2,0x1d -80011d98: 00c6e6b3 or a3,a3,a2 -80011d9c: 00d72223 sw a3,4(a4) -80011da0: fee592e3 bne a1,a4,80011d84 <__multf3+0x148> -80011da4: 04012703 lw a4,64(sp) -80011da8: ffffc537 lui a0,0xffffc -80011dac: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe53d1> -80011db0: 00371713 slli a4,a4,0x3 -80011db4: 04e12023 sw a4,64(sp) -80011db8: 00a787b3 add a5,a5,a0 -80011dbc: 00000713 li a4,0 -80011dc0: 008787b3 add a5,a5,s0 -80011dc4: 00f12e23 sw a5,28(sp) -80011dc8: 00178793 addi a5,a5,1 -80011dcc: 00f12c23 sw a5,24(sp) -80011dd0: 002b1793 slli a5,s6,0x2 -80011dd4: 0124c6b3 xor a3,s1,s2 -80011dd8: 00e7e7b3 or a5,a5,a4 -80011ddc: 00d12623 sw a3,12(sp) -80011de0: fff78793 addi a5,a5,-1 -80011de4: 00e00693 li a3,14 -80011de8: 2af6e663 bltu a3,a5,80012094 <__multf3+0x458> -80011dec: 800156b7 lui a3,0x80015 -80011df0: 00279793 slli a5,a5,0x2 -80011df4: 7c068693 addi a3,a3,1984 # 800157c0 <__BSS_END__+0xffffeb90> -80011df8: 00d787b3 add a5,a5,a3 -80011dfc: 0007a783 lw a5,0(a5) -80011e00: 00078067 jr a5 -80011e04: 00d7e633 or a2,a5,a3 -80011e08: 00a66633 or a2,a2,a0 -80011e0c: 00e66633 or a2,a2,a4 -80011e10: 12060863 beqz a2,80011f40 <__multf3+0x304> -80011e14: 06070063 beqz a4,80011e74 <__multf3+0x238> -80011e18: 00070513 mv a0,a4 -80011e1c: 2e9020ef jal ra,80014904 <__clzsi2> -80011e20: ff450693 addi a3,a0,-12 -80011e24: 4056d793 srai a5,a3,0x5 -80011e28: 01f6f693 andi a3,a3,31 -80011e2c: 06068e63 beqz a3,80011ea8 <__multf3+0x26c> -80011e30: ffc00713 li a4,-4 -80011e34: 02e78733 mul a4,a5,a4 -80011e38: 03010313 addi t1,sp,48 -80011e3c: 02000813 li a6,32 -80011e40: 00279593 slli a1,a5,0x2 -80011e44: 40d80833 sub a6,a6,a3 -80011e48: 00c70713 addi a4,a4,12 -80011e4c: 00e30733 add a4,t1,a4 -80011e50: 08e31463 bne t1,a4,80011ed8 <__multf3+0x29c> -80011e54: 08010713 addi a4,sp,128 -80011e58: 00b705b3 add a1,a4,a1 -80011e5c: 03012703 lw a4,48(sp) -80011e60: fff78793 addi a5,a5,-1 -80011e64: 00d716b3 sll a3,a4,a3 -80011e68: fad5a823 sw a3,-80(a1) -80011e6c: fff00693 li a3,-1 -80011e70: 0a00006f j 80011f10 <__multf3+0x2d4> -80011e74: 00050863 beqz a0,80011e84 <__multf3+0x248> -80011e78: 28d020ef jal ra,80014904 <__clzsi2> -80011e7c: 02050513 addi a0,a0,32 -80011e80: fa1ff06f j 80011e20 <__multf3+0x1e4> -80011e84: 00078a63 beqz a5,80011e98 <__multf3+0x25c> -80011e88: 00078513 mv a0,a5 -80011e8c: 279020ef jal ra,80014904 <__clzsi2> -80011e90: 04050513 addi a0,a0,64 -80011e94: f8dff06f j 80011e20 <__multf3+0x1e4> -80011e98: 00068513 mv a0,a3 -80011e9c: 269020ef jal ra,80014904 <__clzsi2> -80011ea0: 06050513 addi a0,a0,96 -80011ea4: f7dff06f j 80011e20 <__multf3+0x1e4> -80011ea8: ffc00613 li a2,-4 -80011eac: 02c78633 mul a2,a5,a2 -80011eb0: 03c10713 addi a4,sp,60 -80011eb4: 00300693 li a3,3 -80011eb8: 00c705b3 add a1,a4,a2 -80011ebc: 0005a583 lw a1,0(a1) -80011ec0: fff68693 addi a3,a3,-1 -80011ec4: ffc70713 addi a4,a4,-4 -80011ec8: 00b72223 sw a1,4(a4) -80011ecc: fef6d6e3 bge a3,a5,80011eb8 <__multf3+0x27c> -80011ed0: fff78793 addi a5,a5,-1 -80011ed4: f99ff06f j 80011e6c <__multf3+0x230> -80011ed8: ffc72603 lw a2,-4(a4) -80011edc: 00072883 lw a7,0(a4) -80011ee0: 00b70e33 add t3,a4,a1 -80011ee4: 01065633 srl a2,a2,a6 -80011ee8: 00d898b3 sll a7,a7,a3 -80011eec: 01166633 or a2,a2,a7 -80011ef0: 00ce2023 sw a2,0(t3) -80011ef4: ffc70713 addi a4,a4,-4 -80011ef8: f59ff06f j 80011e50 <__multf3+0x214> -80011efc: 00279713 slli a4,a5,0x2 -80011f00: 03010613 addi a2,sp,48 -80011f04: 00e60733 add a4,a2,a4 -80011f08: 00072023 sw zero,0(a4) -80011f0c: fff78793 addi a5,a5,-1 -80011f10: fed796e3 bne a5,a3,80011efc <__multf3+0x2c0> -80011f14: ffffc437 lui s0,0xffffc -80011f18: 01140413 addi s0,s0,17 # ffffc011 <__BSS_END__+0x7ffe53e1> -80011f1c: 40a40433 sub s0,s0,a0 -80011f20: e09ff06f j 80011d28 <__multf3+0xec> -80011f24: 00d7e7b3 or a5,a5,a3 -80011f28: 00a7e7b3 or a5,a5,a0 -80011f2c: 00e7e7b3 or a5,a5,a4 -80011f30: 00300b13 li s6,3 -80011f34: de079ce3 bnez a5,80011d2c <__multf3+0xf0> -80011f38: 00200b13 li s6,2 -80011f3c: df1ff06f j 80011d2c <__multf3+0xf0> -80011f40: 00000413 li s0,0 -80011f44: 00100b13 li s6,1 -80011f48: de5ff06f j 80011d2c <__multf3+0xf0> -80011f4c: 0159e7b3 or a5,s3,s5 -80011f50: 0147e7b3 or a5,a5,s4 -80011f54: 00a7e7b3 or a5,a5,a0 -80011f58: 12078863 beqz a5,80012088 <__multf3+0x44c> -80011f5c: 04050e63 beqz a0,80011fb8 <__multf3+0x37c> -80011f60: 1a5020ef jal ra,80014904 <__clzsi2> -80011f64: ff450693 addi a3,a0,-12 -80011f68: 4056d793 srai a5,a3,0x5 -80011f6c: 01f6f693 andi a3,a3,31 -80011f70: 08068063 beqz a3,80011ff0 <__multf3+0x3b4> -80011f74: ffc00713 li a4,-4 -80011f78: 02e78733 mul a4,a5,a4 -80011f7c: 04010313 addi t1,sp,64 -80011f80: 02000813 li a6,32 -80011f84: 00279593 slli a1,a5,0x2 -80011f88: 40d80833 sub a6,a6,a3 -80011f8c: 00c70713 addi a4,a4,12 -80011f90: 00e30733 add a4,t1,a4 -80011f94: 08e31663 bne t1,a4,80012020 <__multf3+0x3e4> -80011f98: 08010713 addi a4,sp,128 -80011f9c: 00b705b3 add a1,a4,a1 -80011fa0: 04012703 lw a4,64(sp) -80011fa4: fff78793 addi a5,a5,-1 -80011fa8: 00d716b3 sll a3,a4,a3 -80011fac: fcd5a023 sw a3,-64(a1) -80011fb0: fff00693 li a3,-1 -80011fb4: 0a40006f j 80012058 <__multf3+0x41c> -80011fb8: 000a0a63 beqz s4,80011fcc <__multf3+0x390> -80011fbc: 000a0513 mv a0,s4 -80011fc0: 145020ef jal ra,80014904 <__clzsi2> -80011fc4: 02050513 addi a0,a0,32 -80011fc8: f9dff06f j 80011f64 <__multf3+0x328> -80011fcc: 000a8a63 beqz s5,80011fe0 <__multf3+0x3a4> -80011fd0: 000a8513 mv a0,s5 -80011fd4: 131020ef jal ra,80014904 <__clzsi2> -80011fd8: 04050513 addi a0,a0,64 -80011fdc: f89ff06f j 80011f64 <__multf3+0x328> -80011fe0: 00098513 mv a0,s3 -80011fe4: 121020ef jal ra,80014904 <__clzsi2> -80011fe8: 06050513 addi a0,a0,96 -80011fec: f79ff06f j 80011f64 <__multf3+0x328> -80011ff0: ffc00613 li a2,-4 -80011ff4: 02c78633 mul a2,a5,a2 -80011ff8: 04c10713 addi a4,sp,76 -80011ffc: 00300693 li a3,3 -80012000: 00c705b3 add a1,a4,a2 -80012004: 0005a583 lw a1,0(a1) -80012008: fff68693 addi a3,a3,-1 -8001200c: ffc70713 addi a4,a4,-4 -80012010: 00b72223 sw a1,4(a4) -80012014: fef6d6e3 bge a3,a5,80012000 <__multf3+0x3c4> -80012018: fff78793 addi a5,a5,-1 -8001201c: f95ff06f j 80011fb0 <__multf3+0x374> -80012020: ffc72603 lw a2,-4(a4) -80012024: 00072883 lw a7,0(a4) -80012028: 00b70e33 add t3,a4,a1 -8001202c: 01065633 srl a2,a2,a6 -80012030: 00d898b3 sll a7,a7,a3 -80012034: 01166633 or a2,a2,a7 -80012038: 00ce2023 sw a2,0(t3) -8001203c: ffc70713 addi a4,a4,-4 -80012040: f55ff06f j 80011f94 <__multf3+0x358> -80012044: 00279713 slli a4,a5,0x2 -80012048: 04010613 addi a2,sp,64 -8001204c: 00e60733 add a4,a2,a4 -80012050: 00072023 sw zero,0(a4) -80012054: fff78793 addi a5,a5,-1 -80012058: fed796e3 bne a5,a3,80012044 <__multf3+0x408> -8001205c: ffffc7b7 lui a5,0xffffc -80012060: 01178793 addi a5,a5,17 # ffffc011 <__BSS_END__+0x7ffe53e1> -80012064: 40a787b3 sub a5,a5,a0 -80012068: d55ff06f j 80011dbc <__multf3+0x180> -8001206c: 0159e9b3 or s3,s3,s5 -80012070: 0149ea33 or s4,s3,s4 -80012074: 00aa6a33 or s4,s4,a0 -80012078: 00300713 li a4,3 -8001207c: d40a12e3 bnez s4,80011dc0 <__multf3+0x184> -80012080: 00200713 li a4,2 -80012084: d3dff06f j 80011dc0 <__multf3+0x184> -80012088: 00000793 li a5,0 -8001208c: 00100713 li a4,1 -80012090: d31ff06f j 80011dc0 <__multf3+0x184> -80012094: 03012703 lw a4,48(sp) -80012098: 04012e03 lw t3,64(sp) -8001209c: 00010537 lui a0,0x10 -800120a0: fff50693 addi a3,a0,-1 # ffff <_start-0x7fff0001> -800120a4: 01075f93 srli t6,a4,0x10 -800120a8: 010e5a93 srli s5,t3,0x10 -800120ac: 00d77733 and a4,a4,a3 -800120b0: 00de7e33 and t3,t3,a3 -800120b4: 02ea87b3 mul a5,s5,a4 -800120b8: 02ee0633 mul a2,t3,a4 -800120bc: 03cf8833 mul a6,t6,t3 -800120c0: 010785b3 add a1,a5,a6 -800120c4: 01065793 srli a5,a2,0x10 -800120c8: 00b787b3 add a5,a5,a1 -800120cc: 035f8bb3 mul s7,t6,s5 -800120d0: 0107f463 bgeu a5,a6,800120d8 <__multf3+0x49c> -800120d4: 00ab8bb3 add s7,s7,a0 -800120d8: 04412f03 lw t5,68(sp) -800120dc: 0107d993 srli s3,a5,0x10 -800120e0: 00d7f7b3 and a5,a5,a3 -800120e4: 00d67633 and a2,a2,a3 -800120e8: 01079793 slli a5,a5,0x10 -800120ec: 00c787b3 add a5,a5,a2 -800120f0: 010f5493 srli s1,t5,0x10 -800120f4: 00df7f33 and t5,t5,a3 -800120f8: 02ef06b3 mul a3,t5,a4 -800120fc: 02f12023 sw a5,32(sp) -80012100: 06f12023 sw a5,96(sp) -80012104: 03ef8633 mul a2,t6,t5 -80012108: 02e487b3 mul a5,s1,a4 -8001210c: 00c78533 add a0,a5,a2 -80012110: 0106d793 srli a5,a3,0x10 -80012114: 00a787b3 add a5,a5,a0 -80012118: 029f8b33 mul s6,t6,s1 -8001211c: 00c7f663 bgeu a5,a2,80012128 <__multf3+0x4ec> -80012120: 00010637 lui a2,0x10 -80012124: 00cb0b33 add s6,s6,a2 -80012128: 00010637 lui a2,0x10 -8001212c: fff60593 addi a1,a2,-1 # ffff <_start-0x7fff0001> -80012130: 00b7f533 and a0,a5,a1 -80012134: 0107d293 srli t0,a5,0x10 -80012138: 03412783 lw a5,52(sp) -8001213c: 00b6f6b3 and a3,a3,a1 -80012140: 01051513 slli a0,a0,0x10 -80012144: 0107d913 srli s2,a5,0x10 -80012148: 00b7f5b3 and a1,a5,a1 -8001214c: 02ba87b3 mul a5,s5,a1 -80012150: 00d50533 add a0,a0,a3 -80012154: 00a989b3 add s3,s3,a0 -80012158: 03c586b3 mul a3,a1,t3 -8001215c: 03c90333 mul t1,s2,t3 -80012160: 00678833 add a6,a5,t1 -80012164: 0106d793 srli a5,a3,0x10 -80012168: 010787b3 add a5,a5,a6 -8001216c: 032a88b3 mul a7,s5,s2 -80012170: 0067f463 bgeu a5,t1,80012178 <__multf3+0x53c> -80012174: 00c888b3 add a7,a7,a2 -80012178: 00010337 lui t1,0x10 -8001217c: fff30613 addi a2,t1,-1 # ffff <_start-0x7fff0001> -80012180: 0107da13 srli s4,a5,0x10 -80012184: 00c7f833 and a6,a5,a2 -80012188: 00c6f6b3 and a3,a3,a2 -8001218c: 011a0a33 add s4,s4,a7 -80012190: 01081813 slli a6,a6,0x10 -80012194: 03e588b3 mul a7,a1,t5 -80012198: 00d80833 add a6,a6,a3 -8001219c: 03e90633 mul a2,s2,t5 -800121a0: 0108d693 srli a3,a7,0x10 -800121a4: 02b487b3 mul a5,s1,a1 -800121a8: 00c787b3 add a5,a5,a2 -800121ac: 00f687b3 add a5,a3,a5 -800121b0: 03248eb3 mul t4,s1,s2 -800121b4: 00c7f463 bgeu a5,a2,800121bc <__multf3+0x580> -800121b8: 006e8eb3 add t4,t4,t1 -800121bc: 0107d693 srli a3,a5,0x10 -800121c0: 01d686b3 add a3,a3,t4 -800121c4: 00010437 lui s0,0x10 -800121c8: 04812e83 lw t4,72(sp) -800121cc: fff40613 addi a2,s0,-1 # ffff <_start-0x7fff0001> -800121d0: 02d12223 sw a3,36(sp) -800121d4: 00c7f6b3 and a3,a5,a2 -800121d8: 00c8f8b3 and a7,a7,a2 -800121dc: 010ed393 srli t2,t4,0x10 -800121e0: 01069693 slli a3,a3,0x10 -800121e4: 00cefeb3 and t4,t4,a2 -800121e8: 02ee8333 mul t1,t4,a4 -800121ec: 011686b3 add a3,a3,a7 -800121f0: 03df8c33 mul s8,t6,t4 -800121f4: 02e388b3 mul a7,t2,a4 -800121f8: 018887b3 add a5,a7,s8 -800121fc: 01035893 srli a7,t1,0x10 -80012200: 00f888b3 add a7,a7,a5 -80012204: 027f8633 mul a2,t6,t2 -80012208: 0188f463 bgeu a7,s8,80012210 <__multf3+0x5d4> -8001220c: 00860633 add a2,a2,s0 -80012210: 0108d793 srli a5,a7,0x10 -80012214: 00010cb7 lui s9,0x10 -80012218: 00c787b3 add a5,a5,a2 -8001221c: fffc8613 addi a2,s9,-1 # ffff <_start-0x7fff0001> -80012220: 02f12423 sw a5,40(sp) -80012224: 00c8f7b3 and a5,a7,a2 -80012228: 03812883 lw a7,56(sp) -8001222c: 00c37333 and t1,t1,a2 -80012230: 01079793 slli a5,a5,0x10 -80012234: 0108d413 srli s0,a7,0x10 -80012238: 00c8f633 and a2,a7,a2 -8001223c: 03c608b3 mul a7,a2,t3 -80012240: 006787b3 add a5,a5,t1 -80012244: 03c40d33 mul s10,s0,t3 -80012248: 0108dd93 srli s11,a7,0x10 -8001224c: 02ca8333 mul t1,s5,a2 -80012250: 01a30333 add t1,t1,s10 -80012254: 006d8333 add t1,s11,t1 -80012258: 028a8c33 mul s8,s5,s0 -8001225c: 01a37463 bgeu t1,s10,80012264 <__multf3+0x628> -80012260: 019c0c33 add s8,s8,s9 -80012264: 01035c93 srli s9,t1,0x10 -80012268: 018c8c33 add s8,s9,s8 -8001226c: 00010cb7 lui s9,0x10 -80012270: 013b89b3 add s3,s7,s3 -80012274: fffc8d13 addi s10,s9,-1 # ffff <_start-0x7fff0001> -80012278: 00a9b533 sltu a0,s3,a0 -8001227c: 01a37333 and t1,t1,s10 -80012280: 00a282b3 add t0,t0,a0 -80012284: 01031313 slli t1,t1,0x10 -80012288: 01a8f8b3 and a7,a7,s10 -8001228c: 01628b33 add s6,t0,s6 -80012290: 011308b3 add a7,t1,a7 -80012294: 01098333 add t1,s3,a6 -80012298: 01033833 sltu a6,t1,a6 -8001229c: 00612823 sw t1,16(sp) -800122a0: 06612223 sw t1,100(sp) -800122a4: 014b0333 add t1,s6,s4 -800122a8: 010302b3 add t0,t1,a6 -800122ac: 01433a33 sltu s4,t1,s4 -800122b0: 0102b833 sltu a6,t0,a6 -800122b4: 00d289b3 add s3,t0,a3 -800122b8: 010a6833 or a6,s4,a6 -800122bc: 00ab3533 sltu a0,s6,a0 -800122c0: 00d9b6b3 sltu a3,s3,a3 -800122c4: 00a80533 add a0,a6,a0 -800122c8: 00f989b3 add s3,s3,a5 -800122cc: 02412803 lw a6,36(sp) -800122d0: 01198333 add t1,s3,a7 -800122d4: 011338b3 sltu a7,t1,a7 -800122d8: 00612a23 sw t1,20(sp) -800122dc: 06612423 sw t1,104(sp) -800122e0: 02412303 lw t1,36(sp) -800122e4: 01050533 add a0,a0,a6 -800122e8: 02812803 lw a6,40(sp) -800122ec: 00d50db3 add s11,a0,a3 -800122f0: 00ddb6b3 sltu a3,s11,a3 -800122f4: 00653533 sltu a0,a0,t1 -800122f8: 00f9b7b3 sltu a5,s3,a5 -800122fc: 010d8bb3 add s7,s11,a6 -80012300: 00d566b3 or a3,a0,a3 -80012304: 02812503 lw a0,40(sp) -80012308: 00fb8833 add a6,s7,a5 -8001230c: 04c12303 lw t1,76(sp) -80012310: 018809b3 add s3,a6,s8 -80012314: 01198b33 add s6,s3,a7 -80012318: 00abbbb3 sltu s7,s7,a0 -8001231c: 00f837b3 sltu a5,a6,a5 -80012320: 00fbe7b3 or a5,s7,a5 -80012324: 011b38b3 sltu a7,s6,a7 -80012328: 0189bc33 sltu s8,s3,s8 -8001232c: 00f686b3 add a3,a3,a5 -80012330: 01035293 srli t0,t1,0x10 -80012334: 011c6a33 or s4,s8,a7 -80012338: 01a37333 and t1,t1,s10 -8001233c: 02e307b3 mul a5,t1,a4 -80012340: 01468a33 add s4,a3,s4 -80012344: 02e28733 mul a4,t0,a4 -80012348: 0107d893 srli a7,a5,0x10 -8001234c: 026f86b3 mul a3,t6,t1 -80012350: 00d70733 add a4,a4,a3 -80012354: 00e888b3 add a7,a7,a4 -80012358: 025f8fb3 mul t6,t6,t0 -8001235c: 00d8f463 bgeu a7,a3,80012364 <__multf3+0x728> -80012360: 019f8fb3 add t6,t6,s9 -80012364: 03c12983 lw s3,60(sp) -80012368: 000106b7 lui a3,0x10 -8001236c: fff68513 addi a0,a3,-1 # ffff <_start-0x7fff0001> -80012370: 0108dd13 srli s10,a7,0x10 -80012374: 00a8f8b3 and a7,a7,a0 -80012378: 00a7f7b3 and a5,a5,a0 -8001237c: 01fd0d33 add s10,s10,t6 -80012380: 01089893 slli a7,a7,0x10 -80012384: 0109df93 srli t6,s3,0x10 -80012388: 00a9f9b3 and s3,s3,a0 -8001238c: 03fa8cb3 mul s9,s5,t6 -80012390: 00f888b3 add a7,a7,a5 -80012394: 033a8ab3 mul s5,s5,s3 -80012398: 03c987b3 mul a5,s3,t3 -8001239c: 03cf8e33 mul t3,t6,t3 -800123a0: 0107d813 srli a6,a5,0x10 -800123a4: 01ca8ab3 add s5,s5,t3 -800123a8: 01580ab3 add s5,a6,s5 -800123ac: 01caf463 bgeu s5,t3,800123b4 <__multf3+0x778> -800123b0: 00dc8cb3 add s9,s9,a3 -800123b4: 00010bb7 lui s7,0x10 -800123b8: fffb8713 addi a4,s7,-1 # ffff <_start-0x7fff0001> -800123bc: 010ad813 srli a6,s5,0x10 -800123c0: 01980cb3 add s9,a6,s9 -800123c4: 00eaf833 and a6,s5,a4 -800123c8: 00e7f7b3 and a5,a5,a4 -800123cc: 01081813 slli a6,a6,0x10 -800123d0: 02be86b3 mul a3,t4,a1 -800123d4: 00f80833 add a6,a6,a5 -800123d8: 03d90e33 mul t3,s2,t4 -800123dc: 0106d513 srli a0,a3,0x10 -800123e0: 02b387b3 mul a5,t2,a1 -800123e4: 01c787b3 add a5,a5,t3 -800123e8: 00f507b3 add a5,a0,a5 -800123ec: 02790733 mul a4,s2,t2 -800123f0: 01c7f463 bgeu a5,t3,800123f8 <__multf3+0x7bc> -800123f4: 01770733 add a4,a4,s7 -800123f8: 0107d513 srli a0,a5,0x10 -800123fc: 00e50733 add a4,a0,a4 -80012400: 00010bb7 lui s7,0x10 -80012404: 02e12223 sw a4,36(sp) -80012408: fffb8713 addi a4,s7,-1 # ffff <_start-0x7fff0001> -8001240c: 00e7f533 and a0,a5,a4 -80012410: 00e6f6b3 and a3,a3,a4 -80012414: 03e40e33 mul t3,s0,t5 -80012418: 01051513 slli a0,a0,0x10 -8001241c: 00d50533 add a0,a0,a3 -80012420: 03e60733 mul a4,a2,t5 -80012424: 02c487b3 mul a5,s1,a2 -80012428: 01075693 srli a3,a4,0x10 -8001242c: 01c787b3 add a5,a5,t3 -80012430: 00f687b3 add a5,a3,a5 -80012434: 02848ab3 mul s5,s1,s0 -80012438: 01c7f463 bgeu a5,t3,80012440 <__multf3+0x804> -8001243c: 017a8ab3 add s5,s5,s7 -80012440: 00010db7 lui s11,0x10 -80012444: fffd8e13 addi t3,s11,-1 # ffff <_start-0x7fff0001> -80012448: 01c7f6b3 and a3,a5,t3 -8001244c: 0107db93 srli s7,a5,0x10 -80012450: 011b07b3 add a5,s6,a7 -80012454: 01c77733 and a4,a4,t3 -80012458: 0117b8b3 sltu a7,a5,a7 -8001245c: 01aa0a33 add s4,s4,s10 -80012460: 01069693 slli a3,a3,0x10 -80012464: 00e686b3 add a3,a3,a4 -80012468: 011a0733 add a4,s4,a7 -8001246c: 02e12423 sw a4,40(sp) -80012470: 010787b3 add a5,a5,a6 -80012474: 01aa3a33 sltu s4,s4,s10 -80012478: 02812d03 lw s10,40(sp) -8001247c: 0107b833 sltu a6,a5,a6 -80012480: 01970b33 add s6,a4,s9 -80012484: 010b0733 add a4,s6,a6 -80012488: 02e12623 sw a4,44(sp) -8001248c: 011d38b3 sltu a7,s10,a7 -80012490: 011a6a33 or s4,s4,a7 -80012494: 02c12883 lw a7,44(sp) -80012498: 02412e03 lw t3,36(sp) -8001249c: 00a787b3 add a5,a5,a0 -800124a0: 0108b833 sltu a6,a7,a6 -800124a4: 019b3b33 sltu s6,s6,s9 -800124a8: 00a7b533 sltu a0,a5,a0 -800124ac: 01c70733 add a4,a4,t3 -800124b0: 010b6b33 or s6,s6,a6 -800124b4: 02412803 lw a6,36(sp) -800124b8: 00a70c33 add s8,a4,a0 -800124bc: 015b8bb3 add s7,s7,s5 -800124c0: 00d787b3 add a5,a5,a3 -800124c4: 00d7b6b3 sltu a3,a5,a3 -800124c8: 017c0ab3 add s5,s8,s7 -800124cc: 00da8e33 add t3,s5,a3 -800124d0: 01073733 sltu a4,a4,a6 -800124d4: 00ac3533 sltu a0,s8,a0 -800124d8: 00a76733 or a4,a4,a0 -800124dc: 00de36b3 sltu a3,t3,a3 -800124e0: 016a0a33 add s4,s4,s6 -800124e4: 017abab3 sltu s5,s5,s7 -800124e8: 00ea0a33 add s4,s4,a4 -800124ec: 00daeab3 or s5,s5,a3 -800124f0: 02ce8833 mul a6,t4,a2 -800124f4: 015a06b3 add a3,s4,s5 -800124f8: 06f12623 sw a5,108(sp) -800124fc: 03d40a33 mul s4,s0,t4 -80012500: 01085513 srli a0,a6,0x10 -80012504: 02c38733 mul a4,t2,a2 -80012508: 01470733 add a4,a4,s4 -8001250c: 00e50733 add a4,a0,a4 -80012510: 028388b3 mul a7,t2,s0 -80012514: 01477463 bgeu a4,s4,8001251c <__multf3+0x8e0> -80012518: 01b888b3 add a7,a7,s11 -8001251c: 00010a37 lui s4,0x10 -80012520: 01075513 srli a0,a4,0x10 -80012524: fffa0a93 addi s5,s4,-1 # ffff <_start-0x7fff0001> -80012528: 011508b3 add a7,a0,a7 -8001252c: 01577533 and a0,a4,s5 -80012530: 01587833 and a6,a6,s5 -80012534: 01051513 slli a0,a0,0x10 -80012538: 02690ab3 mul s5,s2,t1 -8001253c: 01050533 add a0,a0,a6 -80012540: 02b30833 mul a6,t1,a1 -80012544: 02b285b3 mul a1,t0,a1 -80012548: 01085713 srli a4,a6,0x10 -8001254c: 015585b3 add a1,a1,s5 -80012550: 00b70733 add a4,a4,a1 -80012554: 02590933 mul s2,s2,t0 -80012558: 01577463 bgeu a4,s5,80012560 <__multf3+0x924> -8001255c: 01490933 add s2,s2,s4 -80012560: 00010ab7 lui s5,0x10 -80012564: 01075593 srli a1,a4,0x10 -80012568: fffa8a13 addi s4,s5,-1 # ffff <_start-0x7fff0001> -8001256c: 01487833 and a6,a6,s4 -80012570: 01258933 add s2,a1,s2 -80012574: 014775b3 and a1,a4,s4 -80012578: 01059593 slli a1,a1,0x10 -8001257c: 03e98733 mul a4,s3,t5 -80012580: 010585b3 add a1,a1,a6 -80012584: 03ef8f33 mul t5,t6,t5 -80012588: 01075813 srli a6,a4,0x10 -8001258c: 03f48a33 mul s4,s1,t6 -80012590: 033484b3 mul s1,s1,s3 -80012594: 01e484b3 add s1,s1,t5 -80012598: 009804b3 add s1,a6,s1 -8001259c: 01e4f463 bgeu s1,t5,800125a4 <__multf3+0x968> -800125a0: 015a0a33 add s4,s4,s5 -800125a4: 0104db13 srli s6,s1,0x10 -800125a8: 014b0b33 add s6,s6,s4 -800125ac: 00010a37 lui s4,0x10 -800125b0: fffa0f13 addi t5,s4,-1 # ffff <_start-0x7fff0001> -800125b4: 01e4f833 and a6,s1,t5 -800125b8: 01e77733 and a4,a4,t5 -800125bc: 026404b3 mul s1,s0,t1 -800125c0: 01081813 slli a6,a6,0x10 -800125c4: 00e80833 add a6,a6,a4 -800125c8: 02660f33 mul t5,a2,t1 -800125cc: 02c28633 mul a2,t0,a2 -800125d0: 010f5713 srli a4,t5,0x10 -800125d4: 00960633 add a2,a2,s1 -800125d8: 00c70633 add a2,a4,a2 -800125dc: 02540433 mul s0,s0,t0 -800125e0: 00967463 bgeu a2,s1,800125e8 <__multf3+0x9ac> -800125e4: 01440433 add s0,s0,s4 -800125e8: 00010a37 lui s4,0x10 -800125ec: 01065713 srli a4,a2,0x10 -800125f0: fffa0493 addi s1,s4,-1 # ffff <_start-0x7fff0001> -800125f4: 00870433 add s0,a4,s0 -800125f8: 00967733 and a4,a2,s1 -800125fc: 009f7f33 and t5,t5,s1 -80012600: 01071713 slli a4,a4,0x10 -80012604: 03f384b3 mul s1,t2,t6 -80012608: 01e70733 add a4,a4,t5 -8001260c: 033383b3 mul t2,t2,s3 -80012610: 03d98f33 mul t5,s3,t4 -80012614: 03df8eb3 mul t4,t6,t4 -80012618: 010f5613 srli a2,t5,0x10 -8001261c: 01d383b3 add t2,t2,t4 -80012620: 00760633 add a2,a2,t2 -80012624: 01d67463 bgeu a2,t4,8001262c <__multf3+0x9f0> -80012628: 014484b3 add s1,s1,s4 -8001262c: 01065c13 srli s8,a2,0x10 -80012630: 00010cb7 lui s9,0x10 -80012634: 009c0c33 add s8,s8,s1 -80012638: 00ae0e33 add t3,t3,a0 -8001263c: fffc8493 addi s1,s9,-1 # ffff <_start-0x7fff0001> -80012640: 00ae3533 sltu a0,t3,a0 -80012644: 011686b3 add a3,a3,a7 -80012648: 00967633 and a2,a2,s1 -8001264c: 00a68d33 add s10,a3,a0 -80012650: 009f7f33 and t5,t5,s1 -80012654: 00be0e33 add t3,t3,a1 -80012658: 01061613 slli a2,a2,0x10 -8001265c: 01e60633 add a2,a2,t5 -80012660: 00be35b3 sltu a1,t3,a1 -80012664: 012d0f33 add t5,s10,s2 -80012668: 010e0e33 add t3,t3,a6 -8001266c: 00bf03b3 add t2,t5,a1 -80012670: 01638eb3 add t4,t2,s6 -80012674: 07c12823 sw t3,112(sp) -80012678: 010e3e33 sltu t3,t3,a6 -8001267c: 01ce8db3 add s11,t4,t3 -80012680: 0116b6b3 sltu a3,a3,a7 -80012684: 00b3b5b3 sltu a1,t2,a1 -80012688: 00ad3533 sltu a0,s10,a0 -8001268c: 012f3933 sltu s2,t5,s2 -80012690: 00a6e533 or a0,a3,a0 -80012694: 00b96933 or s2,s2,a1 -80012698: 016ebeb3 sltu t4,t4,s6 -8001269c: 01cdbe33 sltu t3,s11,t3 -800126a0: 01250533 add a0,a0,s2 -800126a4: 01ceeeb3 or t4,t4,t3 -800126a8: 00ed8833 add a6,s11,a4 -800126ac: 01d50533 add a0,a0,t4 -800126b0: 00e83733 sltu a4,a6,a4 -800126b4: 00850533 add a0,a0,s0 -800126b8: 00e506b3 add a3,a0,a4 -800126bc: 00853433 sltu s0,a0,s0 -800126c0: 02698533 mul a0,s3,t1 -800126c4: 00c80833 add a6,a6,a2 -800126c8: 00e6b733 sltu a4,a3,a4 -800126cc: 00c83633 sltu a2,a6,a2 -800126d0: 018686b3 add a3,a3,s8 -800126d4: 00c685b3 add a1,a3,a2 -800126d8: 0186bc33 sltu s8,a3,s8 -800126dc: 00c5b633 sltu a2,a1,a2 -800126e0: 07012a23 sw a6,116(sp) -800126e4: 00e46733 or a4,s0,a4 -800126e8: 026f8333 mul t1,t6,t1 -800126ec: 01055693 srli a3,a0,0x10 -800126f0: 00cc6633 or a2,s8,a2 -800126f4: 033289b3 mul s3,t0,s3 -800126f8: 006989b3 add s3,s3,t1 -800126fc: 03f28fb3 mul t6,t0,t6 -80012700: 013682b3 add t0,a3,s3 -80012704: 0062f463 bgeu t0,t1,8001270c <__multf3+0xad0> -80012708: 019f8fb3 add t6,t6,s9 -8001270c: 0092f6b3 and a3,t0,s1 -80012710: 01069693 slli a3,a3,0x10 -80012714: 009574b3 and s1,a0,s1 -80012718: 0102d293 srli t0,t0,0x10 -8001271c: 009684b3 add s1,a3,s1 -80012720: 00e282b3 add t0,t0,a4 -80012724: 01012683 lw a3,16(sp) -80012728: 02012703 lw a4,32(sp) -8001272c: 009585b3 add a1,a1,s1 -80012730: 0095b4b3 sltu s1,a1,s1 -80012734: 00d769b3 or s3,a4,a3 -80012738: 01412703 lw a4,20(sp) -8001273c: 00c282b3 add t0,t0,a2 -80012740: 009282b3 add t0,t0,s1 -80012744: 013769b3 or s3,a4,s3 -80012748: 01f28fb3 add t6,t0,t6 -8001274c: 00d79793 slli a5,a5,0xd -80012750: 06b12c23 sw a1,120(sp) -80012754: 07f12e23 sw t6,124(sp) -80012758: 0137e7b3 or a5,a5,s3 -8001275c: 06010713 addi a4,sp,96 -80012760: 07010593 addi a1,sp,112 -80012764: 00c72683 lw a3,12(a4) -80012768: 01072603 lw a2,16(a4) -8001276c: 00470713 addi a4,a4,4 -80012770: 0136d693 srli a3,a3,0x13 -80012774: 00d61613 slli a2,a2,0xd -80012778: 00c6e6b3 or a3,a3,a2 -8001277c: fed72e23 sw a3,-4(a4) -80012780: fee592e3 bne a1,a4,80012764 <__multf3+0xb28> -80012784: 06012703 lw a4,96(sp) -80012788: 06812683 lw a3,104(sp) -8001278c: 00f037b3 snez a5,a5 -80012790: 00e7e7b3 or a5,a5,a4 -80012794: 04d12c23 sw a3,88(sp) -80012798: 06c12703 lw a4,108(sp) -8001279c: 06412683 lw a3,100(sp) -800127a0: 04f12823 sw a5,80(sp) -800127a4: 04e12e23 sw a4,92(sp) -800127a8: 04d12a23 sw a3,84(sp) -800127ac: 00b71693 slli a3,a4,0xb -800127b0: 2006dc63 bgez a3,800129c8 <__multf3+0xd8c> -800127b4: 01f79793 slli a5,a5,0x1f -800127b8: 05010713 addi a4,sp,80 -800127bc: 05c10593 addi a1,sp,92 -800127c0: 00072683 lw a3,0(a4) -800127c4: 00472603 lw a2,4(a4) -800127c8: 00470713 addi a4,a4,4 -800127cc: 0016d693 srli a3,a3,0x1 -800127d0: 01f61613 slli a2,a2,0x1f -800127d4: 00c6e6b3 or a3,a3,a2 -800127d8: fed72e23 sw a3,-4(a4) -800127dc: fee592e3 bne a1,a4,800127c0 <__multf3+0xb84> -800127e0: 05c12703 lw a4,92(sp) -800127e4: 00f037b3 snez a5,a5 -800127e8: 00175713 srli a4,a4,0x1 -800127ec: 04e12e23 sw a4,92(sp) -800127f0: 05012703 lw a4,80(sp) -800127f4: 00f767b3 or a5,a4,a5 -800127f8: 04f12823 sw a5,80(sp) -800127fc: 01812703 lw a4,24(sp) -80012800: 000047b7 lui a5,0x4 -80012804: fff78793 addi a5,a5,-1 # 3fff <_start-0x7fffc001> -80012808: 00f707b3 add a5,a4,a5 -8001280c: 1ef05063 blez a5,800129ec <__multf3+0xdb0> -80012810: 05012703 lw a4,80(sp) -80012814: 00777693 andi a3,a4,7 -80012818: 04068463 beqz a3,80012860 <__multf3+0xc24> -8001281c: 00f77693 andi a3,a4,15 -80012820: 00400613 li a2,4 -80012824: 02c68e63 beq a3,a2,80012860 <__multf3+0xc24> -80012828: 05412683 lw a3,84(sp) -8001282c: 00470713 addi a4,a4,4 -80012830: 04e12823 sw a4,80(sp) -80012834: 00473713 sltiu a4,a4,4 -80012838: 00d706b3 add a3,a4,a3 -8001283c: 00e6b733 sltu a4,a3,a4 -80012840: 04d12a23 sw a3,84(sp) -80012844: 05812683 lw a3,88(sp) -80012848: 00d706b3 add a3,a4,a3 -8001284c: 04d12c23 sw a3,88(sp) -80012850: 00e6b6b3 sltu a3,a3,a4 -80012854: 05c12703 lw a4,92(sp) -80012858: 00e686b3 add a3,a3,a4 -8001285c: 04d12e23 sw a3,92(sp) -80012860: 05c12703 lw a4,92(sp) -80012864: 00b71693 slli a3,a4,0xb -80012868: 0206d063 bgez a3,80012888 <__multf3+0xc4c> -8001286c: fff007b7 lui a5,0xfff00 -80012870: fff78793 addi a5,a5,-1 # ffefffff <__BSS_END__+0x7fee93cf> -80012874: 00f77733 and a4,a4,a5 -80012878: 04e12e23 sw a4,92(sp) -8001287c: 01812703 lw a4,24(sp) -80012880: 000047b7 lui a5,0x4 -80012884: 00f707b3 add a5,a4,a5 -80012888: 05010713 addi a4,sp,80 -8001288c: 05c10593 addi a1,sp,92 -80012890: 00072683 lw a3,0(a4) -80012894: 00472603 lw a2,4(a4) -80012898: 00470713 addi a4,a4,4 -8001289c: 0036d693 srli a3,a3,0x3 -800128a0: 01d61613 slli a2,a2,0x1d -800128a4: 00c6e6b3 or a3,a3,a2 -800128a8: fed72e23 sw a3,-4(a4) -800128ac: feb712e3 bne a4,a1,80012890 <__multf3+0xc54> -800128b0: 00008737 lui a4,0x8 -800128b4: ffe70693 addi a3,a4,-2 # 7ffe <_start-0x7fff8002> -800128b8: 10f6ce63 blt a3,a5,800129d4 <__multf3+0xd98> -800128bc: 05c12703 lw a4,92(sp) -800128c0: 00375713 srli a4,a4,0x3 -800128c4: 04e12e23 sw a4,92(sp) -800128c8: 05c12703 lw a4,92(sp) -800128cc: 01179793 slli a5,a5,0x11 -800128d0: 0117d793 srli a5,a5,0x11 -800128d4: 06e11623 sh a4,108(sp) -800128d8: 00c12703 lw a4,12(sp) -800128dc: 0bc12083 lw ra,188(sp) -800128e0: 0b812403 lw s0,184(sp) -800128e4: 00f71713 slli a4,a4,0xf -800128e8: 00f767b3 or a5,a4,a5 -800128ec: 06f11723 sh a5,110(sp) -800128f0: 00812703 lw a4,8(sp) -800128f4: 05012783 lw a5,80(sp) -800128f8: 0b412483 lw s1,180(sp) -800128fc: 0b012903 lw s2,176(sp) -80012900: 00f72023 sw a5,0(a4) -80012904: 05412783 lw a5,84(sp) -80012908: 0ac12983 lw s3,172(sp) -8001290c: 0a812a03 lw s4,168(sp) -80012910: 00f72223 sw a5,4(a4) -80012914: 05812783 lw a5,88(sp) -80012918: 0a412a83 lw s5,164(sp) -8001291c: 0a012b03 lw s6,160(sp) -80012920: 00f72423 sw a5,8(a4) -80012924: 06c12783 lw a5,108(sp) -80012928: 09c12b83 lw s7,156(sp) -8001292c: 09812c03 lw s8,152(sp) -80012930: 00f72623 sw a5,12(a4) -80012934: 09412c83 lw s9,148(sp) -80012938: 09012d03 lw s10,144(sp) -8001293c: 08c12d83 lw s11,140(sp) -80012940: 00070513 mv a0,a4 -80012944: 0c010113 addi sp,sp,192 -80012948: 00008067 ret -8001294c: 00912623 sw s1,12(sp) -80012950: 03012783 lw a5,48(sp) -80012954: 04f12823 sw a5,80(sp) -80012958: 03412783 lw a5,52(sp) -8001295c: 04f12a23 sw a5,84(sp) -80012960: 03812783 lw a5,56(sp) -80012964: 04f12c23 sw a5,88(sp) -80012968: 03c12783 lw a5,60(sp) -8001296c: 04f12e23 sw a5,92(sp) -80012970: 00200793 li a5,2 -80012974: 28fb0863 beq s6,a5,80012c04 <__multf3+0xfc8> -80012978: 00300793 li a5,3 -8001297c: 2afb0263 beq s6,a5,80012c20 <__multf3+0xfe4> -80012980: 00100793 li a5,1 -80012984: e6fb1ce3 bne s6,a5,800127fc <__multf3+0xbc0> -80012988: 04012e23 sw zero,92(sp) -8001298c: 04012c23 sw zero,88(sp) -80012990: 04012a23 sw zero,84(sp) -80012994: 04012823 sw zero,80(sp) -80012998: 22c0006f j 80012bc4 <__multf3+0xf88> -8001299c: 01212623 sw s2,12(sp) -800129a0: 04012783 lw a5,64(sp) -800129a4: 00070b13 mv s6,a4 -800129a8: 04f12823 sw a5,80(sp) -800129ac: 04412783 lw a5,68(sp) -800129b0: 04f12a23 sw a5,84(sp) -800129b4: 04812783 lw a5,72(sp) -800129b8: 04f12c23 sw a5,88(sp) -800129bc: 04c12783 lw a5,76(sp) -800129c0: 04f12e23 sw a5,92(sp) -800129c4: fadff06f j 80012970 <__multf3+0xd34> -800129c8: 01c12783 lw a5,28(sp) -800129cc: 00f12c23 sw a5,24(sp) -800129d0: e2dff06f j 800127fc <__multf3+0xbc0> -800129d4: 04012e23 sw zero,92(sp) -800129d8: 04012c23 sw zero,88(sp) -800129dc: 04012a23 sw zero,84(sp) -800129e0: 04012823 sw zero,80(sp) -800129e4: fff70793 addi a5,a4,-1 -800129e8: ee1ff06f j 800128c8 <__multf3+0xc8c> -800129ec: 00100693 li a3,1 -800129f0: 40f686b3 sub a3,a3,a5 -800129f4: 07400793 li a5,116 -800129f8: 1cd7ca63 blt a5,a3,80012bcc <__multf3+0xf90> -800129fc: 4056d513 srai a0,a3,0x5 -80012a00: 00000793 li a5,0 -80012a04: 00000713 li a4,0 -80012a08: 04a71663 bne a4,a0,80012a54 <__multf3+0xe18> -80012a0c: 01f6f693 andi a3,a3,31 -80012a10: 00251593 slli a1,a0,0x2 -80012a14: 04069e63 bnez a3,80012a70 <__multf3+0xe34> -80012a18: 00300613 li a2,3 -80012a1c: 05010713 addi a4,sp,80 -80012a20: 40a60633 sub a2,a2,a0 -80012a24: 00b70833 add a6,a4,a1 -80012a28: 00082803 lw a6,0(a6) -80012a2c: 00168693 addi a3,a3,1 -80012a30: 00470713 addi a4,a4,4 -80012a34: ff072e23 sw a6,-4(a4) -80012a38: fed656e3 bge a2,a3,80012a24 <__multf3+0xde8> -80012a3c: 00400713 li a4,4 -80012a40: 40a70533 sub a0,a4,a0 -80012a44: 00100713 li a4,1 -80012a48: 08a05063 blez a0,80012ac8 <__multf3+0xe8c> -80012a4c: 00050713 mv a4,a0 -80012a50: 0780006f j 80012ac8 <__multf3+0xe8c> -80012a54: 00271613 slli a2,a4,0x2 -80012a58: 05010593 addi a1,sp,80 -80012a5c: 00c58633 add a2,a1,a2 -80012a60: 00062603 lw a2,0(a2) -80012a64: 00170713 addi a4,a4,1 -80012a68: 00c7e7b3 or a5,a5,a2 -80012a6c: f9dff06f j 80012a08 <__multf3+0xdcc> -80012a70: 08010713 addi a4,sp,128 -80012a74: 00b70733 add a4,a4,a1 -80012a78: fd072703 lw a4,-48(a4) -80012a7c: 02000893 li a7,32 -80012a80: 40d888b3 sub a7,a7,a3 -80012a84: 01171733 sll a4,a4,a7 -80012a88: 00e7e7b3 or a5,a5,a4 -80012a8c: 00300613 li a2,3 -80012a90: 05010713 addi a4,sp,80 -80012a94: 00b705b3 add a1,a4,a1 -80012a98: 00000813 li a6,0 -80012a9c: 40a60633 sub a2,a2,a0 -80012aa0: 00458593 addi a1,a1,4 -80012aa4: 02c84663 blt a6,a2,80012ad0 <__multf3+0xe94> -80012aa8: 08010593 addi a1,sp,128 -80012aac: 00261613 slli a2,a2,0x2 -80012ab0: 00c58633 add a2,a1,a2 -80012ab4: 05c12583 lw a1,92(sp) -80012ab8: 00400713 li a4,4 -80012abc: 40a70733 sub a4,a4,a0 -80012ac0: 00d5d6b3 srl a3,a1,a3 -80012ac4: fcd62823 sw a3,-48(a2) -80012ac8: 00400613 li a2,4 -80012acc: 0440006f j 80012b10 <__multf3+0xed4> -80012ad0: 00281313 slli t1,a6,0x2 -80012ad4: 05010713 addi a4,sp,80 -80012ad8: 0005ae03 lw t3,0(a1) -80012adc: 00670333 add t1,a4,t1 -80012ae0: ffc5a703 lw a4,-4(a1) -80012ae4: 011e1e33 sll t3,t3,a7 -80012ae8: 00180813 addi a6,a6,1 -80012aec: 00d75733 srl a4,a4,a3 -80012af0: 01c76733 or a4,a4,t3 -80012af4: 00e32023 sw a4,0(t1) -80012af8: fa9ff06f j 80012aa0 <__multf3+0xe64> -80012afc: 00271693 slli a3,a4,0x2 -80012b00: 05010593 addi a1,sp,80 -80012b04: 00d586b3 add a3,a1,a3 -80012b08: 0006a023 sw zero,0(a3) -80012b0c: 00170713 addi a4,a4,1 -80012b10: fec716e3 bne a4,a2,80012afc <__multf3+0xec0> -80012b14: 05012683 lw a3,80(sp) -80012b18: 00f037b3 snez a5,a5 -80012b1c: 00d7e7b3 or a5,a5,a3 -80012b20: 04f12823 sw a5,80(sp) -80012b24: 0077f693 andi a3,a5,7 -80012b28: 04068263 beqz a3,80012b6c <__multf3+0xf30> -80012b2c: 00f7f693 andi a3,a5,15 -80012b30: 02e68e63 beq a3,a4,80012b6c <__multf3+0xf30> -80012b34: 05412703 lw a4,84(sp) -80012b38: 00478793 addi a5,a5,4 # 4004 <_start-0x7fffbffc> -80012b3c: 04f12823 sw a5,80(sp) -80012b40: 0047b793 sltiu a5,a5,4 -80012b44: 00e78733 add a4,a5,a4 -80012b48: 00f737b3 sltu a5,a4,a5 -80012b4c: 04e12a23 sw a4,84(sp) -80012b50: 05812703 lw a4,88(sp) -80012b54: 00e78733 add a4,a5,a4 -80012b58: 04e12c23 sw a4,88(sp) -80012b5c: 00f73733 sltu a4,a4,a5 -80012b60: 05c12783 lw a5,92(sp) -80012b64: 00f70733 add a4,a4,a5 -80012b68: 04e12e23 sw a4,92(sp) -80012b6c: 05c12783 lw a5,92(sp) -80012b70: 00c79713 slli a4,a5,0xc -80012b74: 00075e63 bgez a4,80012b90 <__multf3+0xf54> -80012b78: 04012e23 sw zero,92(sp) -80012b7c: 04012c23 sw zero,88(sp) -80012b80: 04012a23 sw zero,84(sp) -80012b84: 04012823 sw zero,80(sp) -80012b88: 00100793 li a5,1 -80012b8c: d3dff06f j 800128c8 <__multf3+0xc8c> -80012b90: 05010793 addi a5,sp,80 -80012b94: 05c10613 addi a2,sp,92 -80012b98: 0007a703 lw a4,0(a5) -80012b9c: 0047a683 lw a3,4(a5) -80012ba0: 00478793 addi a5,a5,4 -80012ba4: 00375713 srli a4,a4,0x3 -80012ba8: 01d69693 slli a3,a3,0x1d -80012bac: 00d76733 or a4,a4,a3 -80012bb0: fee7ae23 sw a4,-4(a5) -80012bb4: fef612e3 bne a2,a5,80012b98 <__multf3+0xf5c> -80012bb8: 05c12783 lw a5,92(sp) -80012bbc: 0037d793 srli a5,a5,0x3 -80012bc0: 04f12e23 sw a5,92(sp) -80012bc4: 00000793 li a5,0 -80012bc8: d01ff06f j 800128c8 <__multf3+0xc8c> -80012bcc: 05412783 lw a5,84(sp) -80012bd0: 05012703 lw a4,80(sp) -80012bd4: 00f76733 or a4,a4,a5 -80012bd8: 05812783 lw a5,88(sp) -80012bdc: 00f76733 or a4,a4,a5 -80012be0: 05c12783 lw a5,92(sp) -80012be4: 00f76733 or a4,a4,a5 -80012be8: 00000793 li a5,0 -80012bec: cc070ee3 beqz a4,800128c8 <__multf3+0xc8c> -80012bf0: 04012e23 sw zero,92(sp) -80012bf4: 04012c23 sw zero,88(sp) -80012bf8: 04012a23 sw zero,84(sp) -80012bfc: 04012823 sw zero,80(sp) -80012c00: cc9ff06f j 800128c8 <__multf3+0xc8c> -80012c04: 000087b7 lui a5,0x8 -80012c08: 04012e23 sw zero,92(sp) -80012c0c: 04012c23 sw zero,88(sp) -80012c10: 04012a23 sw zero,84(sp) -80012c14: 04012823 sw zero,80(sp) -80012c18: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012c1c: cadff06f j 800128c8 <__multf3+0xc8c> -80012c20: 000087b7 lui a5,0x8 -80012c24: 04f12e23 sw a5,92(sp) -80012c28: 04012c23 sw zero,88(sp) -80012c2c: 04012a23 sw zero,84(sp) -80012c30: 04012823 sw zero,80(sp) -80012c34: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012c38: 00012623 sw zero,12(sp) -80012c3c: c8dff06f j 800128c8 <__multf3+0xc8c> +80011d00 <__multf3>: +80011d00: f4010113 addi sp,sp,-192 +80011d04: 0a912a23 sw s1,180(sp) +80011d08: 00c5a483 lw s1,12(a1) +80011d0c: 0005a683 lw a3,0(a1) +80011d10: 0045a783 lw a5,4(a1) +80011d14: 00a12423 sw a0,8(sp) +80011d18: 0085a503 lw a0,8(a1) +80011d1c: 01049713 slli a4,s1,0x10 +80011d20: 0b212823 sw s2,176(sp) +80011d24: 0b312623 sw s3,172(sp) +80011d28: 00c62903 lw s2,12(a2) # 7ff0000c <_start-0xffff4> +80011d2c: 00062983 lw s3,0(a2) +80011d30: 0b412423 sw s4,168(sp) +80011d34: 0b512223 sw s5,164(sp) +80011d38: 00862a03 lw s4,8(a2) +80011d3c: 00462a83 lw s5,4(a2) +80011d40: 00008637 lui a2,0x8 +80011d44: 0a812c23 sw s0,184(sp) +80011d48: 01075713 srli a4,a4,0x10 +80011d4c: 0104d413 srli s0,s1,0x10 +80011d50: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +80011d54: 06912623 sw s1,108(sp) +80011d58: 0a112e23 sw ra,188(sp) +80011d5c: 0b612023 sw s6,160(sp) +80011d60: 09712e23 sw s7,156(sp) +80011d64: 09812c23 sw s8,152(sp) +80011d68: 09912a23 sw s9,148(sp) +80011d6c: 09a12823 sw s10,144(sp) +80011d70: 09b12623 sw s11,140(sp) +80011d74: 06d12023 sw a3,96(sp) +80011d78: 06f12223 sw a5,100(sp) +80011d7c: 06a12423 sw a0,104(sp) +80011d80: 02d12823 sw a3,48(sp) +80011d84: 02f12a23 sw a5,52(sp) +80011d88: 02a12c23 sw a0,56(sp) +80011d8c: 02e12e23 sw a4,60(sp) +80011d90: 00c47433 and s0,s0,a2 +80011d94: 01f4d493 srli s1,s1,0x1f +80011d98: 12040863 beqz s0,80011ec8 <__multf3+0x1c8> +80011d9c: 24c40663 beq s0,a2,80011fe8 <__multf3+0x2e8> +80011da0: 000107b7 lui a5,0x10 +80011da4: 00f767b3 or a5,a4,a5 +80011da8: 02f12e23 sw a5,60(sp) +80011dac: 03010613 addi a2,sp,48 +80011db0: 03c10793 addi a5,sp,60 +80011db4: 0007a703 lw a4,0(a5) # 10000 <_start-0x7fff0000> +80011db8: ffc7a683 lw a3,-4(a5) +80011dbc: ffc78793 addi a5,a5,-4 +80011dc0: 00371713 slli a4,a4,0x3 +80011dc4: 01d6d693 srli a3,a3,0x1d +80011dc8: 00d76733 or a4,a4,a3 +80011dcc: 00e7a223 sw a4,4(a5) +80011dd0: fef612e3 bne a2,a5,80011db4 <__multf3+0xb4> +80011dd4: 03012783 lw a5,48(sp) +80011dd8: ffffc537 lui a0,0xffffc +80011ddc: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe53c5> +80011de0: 00379793 slli a5,a5,0x3 +80011de4: 02f12823 sw a5,48(sp) +80011de8: 00a40433 add s0,s0,a0 +80011dec: 00000b13 li s6,0 +80011df0: 01091513 slli a0,s2,0x10 +80011df4: 00008737 lui a4,0x8 +80011df8: 01095793 srli a5,s2,0x10 +80011dfc: 01055513 srli a0,a0,0x10 +80011e00: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80011e04: 07212623 sw s2,108(sp) +80011e08: 07312023 sw s3,96(sp) +80011e0c: 07512223 sw s5,100(sp) +80011e10: 07412423 sw s4,104(sp) +80011e14: 05312023 sw s3,64(sp) +80011e18: 05512223 sw s5,68(sp) +80011e1c: 05412423 sw s4,72(sp) +80011e20: 04a12623 sw a0,76(sp) +80011e24: 00e7f7b3 and a5,a5,a4 +80011e28: 01f95913 srli s2,s2,0x1f +80011e2c: 1e078263 beqz a5,80012010 <__multf3+0x310> +80011e30: 30e78063 beq a5,a4,80012130 <__multf3+0x430> +80011e34: 00010a37 lui s4,0x10 +80011e38: 01456a33 or s4,a0,s4 +80011e3c: 05412623 sw s4,76(sp) +80011e40: 04010593 addi a1,sp,64 +80011e44: 04c10713 addi a4,sp,76 +80011e48: 00072683 lw a3,0(a4) +80011e4c: ffc72603 lw a2,-4(a4) +80011e50: ffc70713 addi a4,a4,-4 +80011e54: 00369693 slli a3,a3,0x3 +80011e58: 01d65613 srli a2,a2,0x1d +80011e5c: 00c6e6b3 or a3,a3,a2 +80011e60: 00d72223 sw a3,4(a4) +80011e64: fee592e3 bne a1,a4,80011e48 <__multf3+0x148> +80011e68: 04012703 lw a4,64(sp) +80011e6c: ffffc537 lui a0,0xffffc +80011e70: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe53c5> +80011e74: 00371713 slli a4,a4,0x3 +80011e78: 04e12023 sw a4,64(sp) +80011e7c: 00a787b3 add a5,a5,a0 +80011e80: 00000713 li a4,0 +80011e84: 008787b3 add a5,a5,s0 +80011e88: 00f12e23 sw a5,28(sp) +80011e8c: 00178793 addi a5,a5,1 +80011e90: 00f12c23 sw a5,24(sp) +80011e94: 002b1793 slli a5,s6,0x2 +80011e98: 0124c6b3 xor a3,s1,s2 +80011e9c: 00e7e7b3 or a5,a5,a4 +80011ea0: 00d12623 sw a3,12(sp) +80011ea4: fff78793 addi a5,a5,-1 +80011ea8: 00e00693 li a3,14 +80011eac: 2af6e663 bltu a3,a5,80012158 <__multf3+0x458> +80011eb0: 800166b7 lui a3,0x80016 +80011eb4: 00279793 slli a5,a5,0x2 +80011eb8: 81068693 addi a3,a3,-2032 # 80015810 <__BSS_END__+0xffffebd4> +80011ebc: 00d787b3 add a5,a5,a3 +80011ec0: 0007a783 lw a5,0(a5) +80011ec4: 00078067 jr a5 +80011ec8: 00d7e633 or a2,a5,a3 +80011ecc: 00a66633 or a2,a2,a0 +80011ed0: 00e66633 or a2,a2,a4 +80011ed4: 12060863 beqz a2,80012004 <__multf3+0x304> +80011ed8: 06070063 beqz a4,80011f38 <__multf3+0x238> +80011edc: 00070513 mv a0,a4 +80011ee0: 2e9020ef jal ra,800149c8 <__clzsi2> +80011ee4: ff450693 addi a3,a0,-12 +80011ee8: 4056d793 srai a5,a3,0x5 +80011eec: 01f6f693 andi a3,a3,31 +80011ef0: 06068e63 beqz a3,80011f6c <__multf3+0x26c> +80011ef4: ffc00713 li a4,-4 +80011ef8: 02e78733 mul a4,a5,a4 +80011efc: 03010313 addi t1,sp,48 +80011f00: 02000813 li a6,32 +80011f04: 00279593 slli a1,a5,0x2 +80011f08: 40d80833 sub a6,a6,a3 +80011f0c: 00c70713 addi a4,a4,12 +80011f10: 00e30733 add a4,t1,a4 +80011f14: 08e31463 bne t1,a4,80011f9c <__multf3+0x29c> +80011f18: 08010713 addi a4,sp,128 +80011f1c: 00b705b3 add a1,a4,a1 +80011f20: 03012703 lw a4,48(sp) +80011f24: fff78793 addi a5,a5,-1 +80011f28: 00d716b3 sll a3,a4,a3 +80011f2c: fad5a823 sw a3,-80(a1) +80011f30: fff00693 li a3,-1 +80011f34: 0a00006f j 80011fd4 <__multf3+0x2d4> +80011f38: 00050863 beqz a0,80011f48 <__multf3+0x248> +80011f3c: 28d020ef jal ra,800149c8 <__clzsi2> +80011f40: 02050513 addi a0,a0,32 +80011f44: fa1ff06f j 80011ee4 <__multf3+0x1e4> +80011f48: 00078a63 beqz a5,80011f5c <__multf3+0x25c> +80011f4c: 00078513 mv a0,a5 +80011f50: 279020ef jal ra,800149c8 <__clzsi2> +80011f54: 04050513 addi a0,a0,64 +80011f58: f8dff06f j 80011ee4 <__multf3+0x1e4> +80011f5c: 00068513 mv a0,a3 +80011f60: 269020ef jal ra,800149c8 <__clzsi2> +80011f64: 06050513 addi a0,a0,96 +80011f68: f7dff06f j 80011ee4 <__multf3+0x1e4> +80011f6c: ffc00613 li a2,-4 +80011f70: 02c78633 mul a2,a5,a2 +80011f74: 03c10713 addi a4,sp,60 +80011f78: 00300693 li a3,3 +80011f7c: 00c705b3 add a1,a4,a2 +80011f80: 0005a583 lw a1,0(a1) +80011f84: fff68693 addi a3,a3,-1 +80011f88: ffc70713 addi a4,a4,-4 +80011f8c: 00b72223 sw a1,4(a4) +80011f90: fef6d6e3 bge a3,a5,80011f7c <__multf3+0x27c> +80011f94: fff78793 addi a5,a5,-1 +80011f98: f99ff06f j 80011f30 <__multf3+0x230> +80011f9c: ffc72603 lw a2,-4(a4) +80011fa0: 00072883 lw a7,0(a4) +80011fa4: 00b70e33 add t3,a4,a1 +80011fa8: 01065633 srl a2,a2,a6 +80011fac: 00d898b3 sll a7,a7,a3 +80011fb0: 01166633 or a2,a2,a7 +80011fb4: 00ce2023 sw a2,0(t3) +80011fb8: ffc70713 addi a4,a4,-4 +80011fbc: f59ff06f j 80011f14 <__multf3+0x214> +80011fc0: 00279713 slli a4,a5,0x2 +80011fc4: 03010613 addi a2,sp,48 +80011fc8: 00e60733 add a4,a2,a4 +80011fcc: 00072023 sw zero,0(a4) +80011fd0: fff78793 addi a5,a5,-1 +80011fd4: fed796e3 bne a5,a3,80011fc0 <__multf3+0x2c0> +80011fd8: ffffc437 lui s0,0xffffc +80011fdc: 01140413 addi s0,s0,17 # ffffc011 <__BSS_END__+0x7ffe53d5> +80011fe0: 40a40433 sub s0,s0,a0 +80011fe4: e09ff06f j 80011dec <__multf3+0xec> +80011fe8: 00d7e7b3 or a5,a5,a3 +80011fec: 00a7e7b3 or a5,a5,a0 +80011ff0: 00e7e7b3 or a5,a5,a4 +80011ff4: 00300b13 li s6,3 +80011ff8: de079ce3 bnez a5,80011df0 <__multf3+0xf0> +80011ffc: 00200b13 li s6,2 +80012000: df1ff06f j 80011df0 <__multf3+0xf0> +80012004: 00000413 li s0,0 +80012008: 00100b13 li s6,1 +8001200c: de5ff06f j 80011df0 <__multf3+0xf0> +80012010: 0159e7b3 or a5,s3,s5 +80012014: 0147e7b3 or a5,a5,s4 +80012018: 00a7e7b3 or a5,a5,a0 +8001201c: 12078863 beqz a5,8001214c <__multf3+0x44c> +80012020: 04050e63 beqz a0,8001207c <__multf3+0x37c> +80012024: 1a5020ef jal ra,800149c8 <__clzsi2> +80012028: ff450693 addi a3,a0,-12 +8001202c: 4056d793 srai a5,a3,0x5 +80012030: 01f6f693 andi a3,a3,31 +80012034: 08068063 beqz a3,800120b4 <__multf3+0x3b4> +80012038: ffc00713 li a4,-4 +8001203c: 02e78733 mul a4,a5,a4 +80012040: 04010313 addi t1,sp,64 +80012044: 02000813 li a6,32 +80012048: 00279593 slli a1,a5,0x2 +8001204c: 40d80833 sub a6,a6,a3 +80012050: 00c70713 addi a4,a4,12 +80012054: 00e30733 add a4,t1,a4 +80012058: 08e31663 bne t1,a4,800120e4 <__multf3+0x3e4> +8001205c: 08010713 addi a4,sp,128 +80012060: 00b705b3 add a1,a4,a1 +80012064: 04012703 lw a4,64(sp) +80012068: fff78793 addi a5,a5,-1 +8001206c: 00d716b3 sll a3,a4,a3 +80012070: fcd5a023 sw a3,-64(a1) +80012074: fff00693 li a3,-1 +80012078: 0a40006f j 8001211c <__multf3+0x41c> +8001207c: 000a0a63 beqz s4,80012090 <__multf3+0x390> +80012080: 000a0513 mv a0,s4 +80012084: 145020ef jal ra,800149c8 <__clzsi2> +80012088: 02050513 addi a0,a0,32 +8001208c: f9dff06f j 80012028 <__multf3+0x328> +80012090: 000a8a63 beqz s5,800120a4 <__multf3+0x3a4> +80012094: 000a8513 mv a0,s5 +80012098: 131020ef jal ra,800149c8 <__clzsi2> +8001209c: 04050513 addi a0,a0,64 +800120a0: f89ff06f j 80012028 <__multf3+0x328> +800120a4: 00098513 mv a0,s3 +800120a8: 121020ef jal ra,800149c8 <__clzsi2> +800120ac: 06050513 addi a0,a0,96 +800120b0: f79ff06f j 80012028 <__multf3+0x328> +800120b4: ffc00613 li a2,-4 +800120b8: 02c78633 mul a2,a5,a2 +800120bc: 04c10713 addi a4,sp,76 +800120c0: 00300693 li a3,3 +800120c4: 00c705b3 add a1,a4,a2 +800120c8: 0005a583 lw a1,0(a1) +800120cc: fff68693 addi a3,a3,-1 +800120d0: ffc70713 addi a4,a4,-4 +800120d4: 00b72223 sw a1,4(a4) +800120d8: fef6d6e3 bge a3,a5,800120c4 <__multf3+0x3c4> +800120dc: fff78793 addi a5,a5,-1 +800120e0: f95ff06f j 80012074 <__multf3+0x374> +800120e4: ffc72603 lw a2,-4(a4) +800120e8: 00072883 lw a7,0(a4) +800120ec: 00b70e33 add t3,a4,a1 +800120f0: 01065633 srl a2,a2,a6 +800120f4: 00d898b3 sll a7,a7,a3 +800120f8: 01166633 or a2,a2,a7 +800120fc: 00ce2023 sw a2,0(t3) +80012100: ffc70713 addi a4,a4,-4 +80012104: f55ff06f j 80012058 <__multf3+0x358> +80012108: 00279713 slli a4,a5,0x2 +8001210c: 04010613 addi a2,sp,64 +80012110: 00e60733 add a4,a2,a4 +80012114: 00072023 sw zero,0(a4) +80012118: fff78793 addi a5,a5,-1 +8001211c: fed796e3 bne a5,a3,80012108 <__multf3+0x408> +80012120: ffffc7b7 lui a5,0xffffc +80012124: 01178793 addi a5,a5,17 # ffffc011 <__BSS_END__+0x7ffe53d5> +80012128: 40a787b3 sub a5,a5,a0 +8001212c: d55ff06f j 80011e80 <__multf3+0x180> +80012130: 0159e9b3 or s3,s3,s5 +80012134: 0149ea33 or s4,s3,s4 +80012138: 00aa6a33 or s4,s4,a0 +8001213c: 00300713 li a4,3 +80012140: d40a12e3 bnez s4,80011e84 <__multf3+0x184> +80012144: 00200713 li a4,2 +80012148: d3dff06f j 80011e84 <__multf3+0x184> +8001214c: 00000793 li a5,0 +80012150: 00100713 li a4,1 +80012154: d31ff06f j 80011e84 <__multf3+0x184> +80012158: 03012703 lw a4,48(sp) +8001215c: 04012e03 lw t3,64(sp) +80012160: 00010537 lui a0,0x10 +80012164: fff50693 addi a3,a0,-1 # ffff <_start-0x7fff0001> +80012168: 01075f93 srli t6,a4,0x10 +8001216c: 010e5a93 srli s5,t3,0x10 +80012170: 00d77733 and a4,a4,a3 +80012174: 00de7e33 and t3,t3,a3 +80012178: 02ea87b3 mul a5,s5,a4 +8001217c: 02ee0633 mul a2,t3,a4 +80012180: 03cf8833 mul a6,t6,t3 +80012184: 010785b3 add a1,a5,a6 +80012188: 01065793 srli a5,a2,0x10 +8001218c: 00b787b3 add a5,a5,a1 +80012190: 035f8bb3 mul s7,t6,s5 +80012194: 0107f463 bgeu a5,a6,8001219c <__multf3+0x49c> +80012198: 00ab8bb3 add s7,s7,a0 +8001219c: 04412f03 lw t5,68(sp) +800121a0: 0107d993 srli s3,a5,0x10 +800121a4: 00d7f7b3 and a5,a5,a3 +800121a8: 00d67633 and a2,a2,a3 +800121ac: 01079793 slli a5,a5,0x10 +800121b0: 00c787b3 add a5,a5,a2 +800121b4: 010f5493 srli s1,t5,0x10 +800121b8: 00df7f33 and t5,t5,a3 +800121bc: 02ef06b3 mul a3,t5,a4 +800121c0: 02f12023 sw a5,32(sp) +800121c4: 06f12023 sw a5,96(sp) +800121c8: 03ef8633 mul a2,t6,t5 +800121cc: 02e487b3 mul a5,s1,a4 +800121d0: 00c78533 add a0,a5,a2 +800121d4: 0106d793 srli a5,a3,0x10 +800121d8: 00a787b3 add a5,a5,a0 +800121dc: 029f8b33 mul s6,t6,s1 +800121e0: 00c7f663 bgeu a5,a2,800121ec <__multf3+0x4ec> +800121e4: 00010637 lui a2,0x10 +800121e8: 00cb0b33 add s6,s6,a2 +800121ec: 00010637 lui a2,0x10 +800121f0: fff60593 addi a1,a2,-1 # ffff <_start-0x7fff0001> +800121f4: 00b7f533 and a0,a5,a1 +800121f8: 0107d293 srli t0,a5,0x10 +800121fc: 03412783 lw a5,52(sp) +80012200: 00b6f6b3 and a3,a3,a1 +80012204: 01051513 slli a0,a0,0x10 +80012208: 0107d913 srli s2,a5,0x10 +8001220c: 00b7f5b3 and a1,a5,a1 +80012210: 02ba87b3 mul a5,s5,a1 +80012214: 00d50533 add a0,a0,a3 +80012218: 00a989b3 add s3,s3,a0 +8001221c: 03c586b3 mul a3,a1,t3 +80012220: 03c90333 mul t1,s2,t3 +80012224: 00678833 add a6,a5,t1 +80012228: 0106d793 srli a5,a3,0x10 +8001222c: 010787b3 add a5,a5,a6 +80012230: 032a88b3 mul a7,s5,s2 +80012234: 0067f463 bgeu a5,t1,8001223c <__multf3+0x53c> +80012238: 00c888b3 add a7,a7,a2 +8001223c: 00010337 lui t1,0x10 +80012240: fff30613 addi a2,t1,-1 # ffff <_start-0x7fff0001> +80012244: 0107da13 srli s4,a5,0x10 +80012248: 00c7f833 and a6,a5,a2 +8001224c: 00c6f6b3 and a3,a3,a2 +80012250: 011a0a33 add s4,s4,a7 +80012254: 01081813 slli a6,a6,0x10 +80012258: 03e588b3 mul a7,a1,t5 +8001225c: 00d80833 add a6,a6,a3 +80012260: 03e90633 mul a2,s2,t5 +80012264: 0108d693 srli a3,a7,0x10 +80012268: 02b487b3 mul a5,s1,a1 +8001226c: 00c787b3 add a5,a5,a2 +80012270: 00f687b3 add a5,a3,a5 +80012274: 03248eb3 mul t4,s1,s2 +80012278: 00c7f463 bgeu a5,a2,80012280 <__multf3+0x580> +8001227c: 006e8eb3 add t4,t4,t1 +80012280: 0107d693 srli a3,a5,0x10 +80012284: 01d686b3 add a3,a3,t4 +80012288: 00010437 lui s0,0x10 +8001228c: 04812e83 lw t4,72(sp) +80012290: fff40613 addi a2,s0,-1 # ffff <_start-0x7fff0001> +80012294: 02d12223 sw a3,36(sp) +80012298: 00c7f6b3 and a3,a5,a2 +8001229c: 00c8f8b3 and a7,a7,a2 +800122a0: 010ed393 srli t2,t4,0x10 +800122a4: 01069693 slli a3,a3,0x10 +800122a8: 00cefeb3 and t4,t4,a2 +800122ac: 02ee8333 mul t1,t4,a4 +800122b0: 011686b3 add a3,a3,a7 +800122b4: 03df8c33 mul s8,t6,t4 +800122b8: 02e388b3 mul a7,t2,a4 +800122bc: 018887b3 add a5,a7,s8 +800122c0: 01035893 srli a7,t1,0x10 +800122c4: 00f888b3 add a7,a7,a5 +800122c8: 027f8633 mul a2,t6,t2 +800122cc: 0188f463 bgeu a7,s8,800122d4 <__multf3+0x5d4> +800122d0: 00860633 add a2,a2,s0 +800122d4: 0108d793 srli a5,a7,0x10 +800122d8: 00010cb7 lui s9,0x10 +800122dc: 00c787b3 add a5,a5,a2 +800122e0: fffc8613 addi a2,s9,-1 # ffff <_start-0x7fff0001> +800122e4: 02f12423 sw a5,40(sp) +800122e8: 00c8f7b3 and a5,a7,a2 +800122ec: 03812883 lw a7,56(sp) +800122f0: 00c37333 and t1,t1,a2 +800122f4: 01079793 slli a5,a5,0x10 +800122f8: 0108d413 srli s0,a7,0x10 +800122fc: 00c8f633 and a2,a7,a2 +80012300: 03c608b3 mul a7,a2,t3 +80012304: 006787b3 add a5,a5,t1 +80012308: 03c40d33 mul s10,s0,t3 +8001230c: 0108dd93 srli s11,a7,0x10 +80012310: 02ca8333 mul t1,s5,a2 +80012314: 01a30333 add t1,t1,s10 +80012318: 006d8333 add t1,s11,t1 +8001231c: 028a8c33 mul s8,s5,s0 +80012320: 01a37463 bgeu t1,s10,80012328 <__multf3+0x628> +80012324: 019c0c33 add s8,s8,s9 +80012328: 01035c93 srli s9,t1,0x10 +8001232c: 018c8c33 add s8,s9,s8 +80012330: 00010cb7 lui s9,0x10 +80012334: 013b89b3 add s3,s7,s3 +80012338: fffc8d13 addi s10,s9,-1 # ffff <_start-0x7fff0001> +8001233c: 00a9b533 sltu a0,s3,a0 +80012340: 01a37333 and t1,t1,s10 +80012344: 00a282b3 add t0,t0,a0 +80012348: 01031313 slli t1,t1,0x10 +8001234c: 01a8f8b3 and a7,a7,s10 +80012350: 01628b33 add s6,t0,s6 +80012354: 011308b3 add a7,t1,a7 +80012358: 01098333 add t1,s3,a6 +8001235c: 01033833 sltu a6,t1,a6 +80012360: 00612823 sw t1,16(sp) +80012364: 06612223 sw t1,100(sp) +80012368: 014b0333 add t1,s6,s4 +8001236c: 010302b3 add t0,t1,a6 +80012370: 01433a33 sltu s4,t1,s4 +80012374: 0102b833 sltu a6,t0,a6 +80012378: 00d289b3 add s3,t0,a3 +8001237c: 010a6833 or a6,s4,a6 +80012380: 00ab3533 sltu a0,s6,a0 +80012384: 00d9b6b3 sltu a3,s3,a3 +80012388: 00a80533 add a0,a6,a0 +8001238c: 00f989b3 add s3,s3,a5 +80012390: 02412803 lw a6,36(sp) +80012394: 01198333 add t1,s3,a7 +80012398: 011338b3 sltu a7,t1,a7 +8001239c: 00612a23 sw t1,20(sp) +800123a0: 06612423 sw t1,104(sp) +800123a4: 02412303 lw t1,36(sp) +800123a8: 01050533 add a0,a0,a6 +800123ac: 02812803 lw a6,40(sp) +800123b0: 00d50db3 add s11,a0,a3 +800123b4: 00ddb6b3 sltu a3,s11,a3 +800123b8: 00653533 sltu a0,a0,t1 +800123bc: 00f9b7b3 sltu a5,s3,a5 +800123c0: 010d8bb3 add s7,s11,a6 +800123c4: 00d566b3 or a3,a0,a3 +800123c8: 02812503 lw a0,40(sp) +800123cc: 00fb8833 add a6,s7,a5 +800123d0: 04c12303 lw t1,76(sp) +800123d4: 018809b3 add s3,a6,s8 +800123d8: 01198b33 add s6,s3,a7 +800123dc: 00abbbb3 sltu s7,s7,a0 +800123e0: 00f837b3 sltu a5,a6,a5 +800123e4: 00fbe7b3 or a5,s7,a5 +800123e8: 011b38b3 sltu a7,s6,a7 +800123ec: 0189bc33 sltu s8,s3,s8 +800123f0: 00f686b3 add a3,a3,a5 +800123f4: 01035293 srli t0,t1,0x10 +800123f8: 011c6a33 or s4,s8,a7 +800123fc: 01a37333 and t1,t1,s10 +80012400: 02e307b3 mul a5,t1,a4 +80012404: 01468a33 add s4,a3,s4 +80012408: 02e28733 mul a4,t0,a4 +8001240c: 0107d893 srli a7,a5,0x10 +80012410: 026f86b3 mul a3,t6,t1 +80012414: 00d70733 add a4,a4,a3 +80012418: 00e888b3 add a7,a7,a4 +8001241c: 025f8fb3 mul t6,t6,t0 +80012420: 00d8f463 bgeu a7,a3,80012428 <__multf3+0x728> +80012424: 019f8fb3 add t6,t6,s9 +80012428: 03c12983 lw s3,60(sp) +8001242c: 000106b7 lui a3,0x10 +80012430: fff68513 addi a0,a3,-1 # ffff <_start-0x7fff0001> +80012434: 0108dd13 srli s10,a7,0x10 +80012438: 00a8f8b3 and a7,a7,a0 +8001243c: 00a7f7b3 and a5,a5,a0 +80012440: 01fd0d33 add s10,s10,t6 +80012444: 01089893 slli a7,a7,0x10 +80012448: 0109df93 srli t6,s3,0x10 +8001244c: 00a9f9b3 and s3,s3,a0 +80012450: 03fa8cb3 mul s9,s5,t6 +80012454: 00f888b3 add a7,a7,a5 +80012458: 033a8ab3 mul s5,s5,s3 +8001245c: 03c987b3 mul a5,s3,t3 +80012460: 03cf8e33 mul t3,t6,t3 +80012464: 0107d813 srli a6,a5,0x10 +80012468: 01ca8ab3 add s5,s5,t3 +8001246c: 01580ab3 add s5,a6,s5 +80012470: 01caf463 bgeu s5,t3,80012478 <__multf3+0x778> +80012474: 00dc8cb3 add s9,s9,a3 +80012478: 00010bb7 lui s7,0x10 +8001247c: fffb8713 addi a4,s7,-1 # ffff <_start-0x7fff0001> +80012480: 010ad813 srli a6,s5,0x10 +80012484: 01980cb3 add s9,a6,s9 +80012488: 00eaf833 and a6,s5,a4 +8001248c: 00e7f7b3 and a5,a5,a4 +80012490: 01081813 slli a6,a6,0x10 +80012494: 02be86b3 mul a3,t4,a1 +80012498: 00f80833 add a6,a6,a5 +8001249c: 03d90e33 mul t3,s2,t4 +800124a0: 0106d513 srli a0,a3,0x10 +800124a4: 02b387b3 mul a5,t2,a1 +800124a8: 01c787b3 add a5,a5,t3 +800124ac: 00f507b3 add a5,a0,a5 +800124b0: 02790733 mul a4,s2,t2 +800124b4: 01c7f463 bgeu a5,t3,800124bc <__multf3+0x7bc> +800124b8: 01770733 add a4,a4,s7 +800124bc: 0107d513 srli a0,a5,0x10 +800124c0: 00e50733 add a4,a0,a4 +800124c4: 00010bb7 lui s7,0x10 +800124c8: 02e12223 sw a4,36(sp) +800124cc: fffb8713 addi a4,s7,-1 # ffff <_start-0x7fff0001> +800124d0: 00e7f533 and a0,a5,a4 +800124d4: 00e6f6b3 and a3,a3,a4 +800124d8: 03e40e33 mul t3,s0,t5 +800124dc: 01051513 slli a0,a0,0x10 +800124e0: 00d50533 add a0,a0,a3 +800124e4: 03e60733 mul a4,a2,t5 +800124e8: 02c487b3 mul a5,s1,a2 +800124ec: 01075693 srli a3,a4,0x10 +800124f0: 01c787b3 add a5,a5,t3 +800124f4: 00f687b3 add a5,a3,a5 +800124f8: 02848ab3 mul s5,s1,s0 +800124fc: 01c7f463 bgeu a5,t3,80012504 <__multf3+0x804> +80012500: 017a8ab3 add s5,s5,s7 +80012504: 00010db7 lui s11,0x10 +80012508: fffd8e13 addi t3,s11,-1 # ffff <_start-0x7fff0001> +8001250c: 01c7f6b3 and a3,a5,t3 +80012510: 0107db93 srli s7,a5,0x10 +80012514: 011b07b3 add a5,s6,a7 +80012518: 01c77733 and a4,a4,t3 +8001251c: 0117b8b3 sltu a7,a5,a7 +80012520: 01aa0a33 add s4,s4,s10 +80012524: 01069693 slli a3,a3,0x10 +80012528: 00e686b3 add a3,a3,a4 +8001252c: 011a0733 add a4,s4,a7 +80012530: 02e12423 sw a4,40(sp) +80012534: 010787b3 add a5,a5,a6 +80012538: 01aa3a33 sltu s4,s4,s10 +8001253c: 02812d03 lw s10,40(sp) +80012540: 0107b833 sltu a6,a5,a6 +80012544: 01970b33 add s6,a4,s9 +80012548: 010b0733 add a4,s6,a6 +8001254c: 02e12623 sw a4,44(sp) +80012550: 011d38b3 sltu a7,s10,a7 +80012554: 011a6a33 or s4,s4,a7 +80012558: 02c12883 lw a7,44(sp) +8001255c: 02412e03 lw t3,36(sp) +80012560: 00a787b3 add a5,a5,a0 +80012564: 0108b833 sltu a6,a7,a6 +80012568: 019b3b33 sltu s6,s6,s9 +8001256c: 00a7b533 sltu a0,a5,a0 +80012570: 01c70733 add a4,a4,t3 +80012574: 010b6b33 or s6,s6,a6 +80012578: 02412803 lw a6,36(sp) +8001257c: 00a70c33 add s8,a4,a0 +80012580: 015b8bb3 add s7,s7,s5 +80012584: 00d787b3 add a5,a5,a3 +80012588: 00d7b6b3 sltu a3,a5,a3 +8001258c: 017c0ab3 add s5,s8,s7 +80012590: 00da8e33 add t3,s5,a3 +80012594: 01073733 sltu a4,a4,a6 +80012598: 00ac3533 sltu a0,s8,a0 +8001259c: 00a76733 or a4,a4,a0 +800125a0: 00de36b3 sltu a3,t3,a3 +800125a4: 016a0a33 add s4,s4,s6 +800125a8: 017abab3 sltu s5,s5,s7 +800125ac: 00ea0a33 add s4,s4,a4 +800125b0: 00daeab3 or s5,s5,a3 +800125b4: 02ce8833 mul a6,t4,a2 +800125b8: 015a06b3 add a3,s4,s5 +800125bc: 06f12623 sw a5,108(sp) +800125c0: 03d40a33 mul s4,s0,t4 +800125c4: 01085513 srli a0,a6,0x10 +800125c8: 02c38733 mul a4,t2,a2 +800125cc: 01470733 add a4,a4,s4 +800125d0: 00e50733 add a4,a0,a4 +800125d4: 028388b3 mul a7,t2,s0 +800125d8: 01477463 bgeu a4,s4,800125e0 <__multf3+0x8e0> +800125dc: 01b888b3 add a7,a7,s11 +800125e0: 00010a37 lui s4,0x10 +800125e4: 01075513 srli a0,a4,0x10 +800125e8: fffa0a93 addi s5,s4,-1 # ffff <_start-0x7fff0001> +800125ec: 011508b3 add a7,a0,a7 +800125f0: 01577533 and a0,a4,s5 +800125f4: 01587833 and a6,a6,s5 +800125f8: 01051513 slli a0,a0,0x10 +800125fc: 02690ab3 mul s5,s2,t1 +80012600: 01050533 add a0,a0,a6 +80012604: 02b30833 mul a6,t1,a1 +80012608: 02b285b3 mul a1,t0,a1 +8001260c: 01085713 srli a4,a6,0x10 +80012610: 015585b3 add a1,a1,s5 +80012614: 00b70733 add a4,a4,a1 +80012618: 02590933 mul s2,s2,t0 +8001261c: 01577463 bgeu a4,s5,80012624 <__multf3+0x924> +80012620: 01490933 add s2,s2,s4 +80012624: 00010ab7 lui s5,0x10 +80012628: 01075593 srli a1,a4,0x10 +8001262c: fffa8a13 addi s4,s5,-1 # ffff <_start-0x7fff0001> +80012630: 01487833 and a6,a6,s4 +80012634: 01258933 add s2,a1,s2 +80012638: 014775b3 and a1,a4,s4 +8001263c: 01059593 slli a1,a1,0x10 +80012640: 03e98733 mul a4,s3,t5 +80012644: 010585b3 add a1,a1,a6 +80012648: 03ef8f33 mul t5,t6,t5 +8001264c: 01075813 srli a6,a4,0x10 +80012650: 03f48a33 mul s4,s1,t6 +80012654: 033484b3 mul s1,s1,s3 +80012658: 01e484b3 add s1,s1,t5 +8001265c: 009804b3 add s1,a6,s1 +80012660: 01e4f463 bgeu s1,t5,80012668 <__multf3+0x968> +80012664: 015a0a33 add s4,s4,s5 +80012668: 0104db13 srli s6,s1,0x10 +8001266c: 014b0b33 add s6,s6,s4 +80012670: 00010a37 lui s4,0x10 +80012674: fffa0f13 addi t5,s4,-1 # ffff <_start-0x7fff0001> +80012678: 01e4f833 and a6,s1,t5 +8001267c: 01e77733 and a4,a4,t5 +80012680: 026404b3 mul s1,s0,t1 +80012684: 01081813 slli a6,a6,0x10 +80012688: 00e80833 add a6,a6,a4 +8001268c: 02660f33 mul t5,a2,t1 +80012690: 02c28633 mul a2,t0,a2 +80012694: 010f5713 srli a4,t5,0x10 +80012698: 00960633 add a2,a2,s1 +8001269c: 00c70633 add a2,a4,a2 +800126a0: 02540433 mul s0,s0,t0 +800126a4: 00967463 bgeu a2,s1,800126ac <__multf3+0x9ac> +800126a8: 01440433 add s0,s0,s4 +800126ac: 00010a37 lui s4,0x10 +800126b0: 01065713 srli a4,a2,0x10 +800126b4: fffa0493 addi s1,s4,-1 # ffff <_start-0x7fff0001> +800126b8: 00870433 add s0,a4,s0 +800126bc: 00967733 and a4,a2,s1 +800126c0: 009f7f33 and t5,t5,s1 +800126c4: 01071713 slli a4,a4,0x10 +800126c8: 03f384b3 mul s1,t2,t6 +800126cc: 01e70733 add a4,a4,t5 +800126d0: 033383b3 mul t2,t2,s3 +800126d4: 03d98f33 mul t5,s3,t4 +800126d8: 03df8eb3 mul t4,t6,t4 +800126dc: 010f5613 srli a2,t5,0x10 +800126e0: 01d383b3 add t2,t2,t4 +800126e4: 00760633 add a2,a2,t2 +800126e8: 01d67463 bgeu a2,t4,800126f0 <__multf3+0x9f0> +800126ec: 014484b3 add s1,s1,s4 +800126f0: 01065c13 srli s8,a2,0x10 +800126f4: 00010cb7 lui s9,0x10 +800126f8: 009c0c33 add s8,s8,s1 +800126fc: 00ae0e33 add t3,t3,a0 +80012700: fffc8493 addi s1,s9,-1 # ffff <_start-0x7fff0001> +80012704: 00ae3533 sltu a0,t3,a0 +80012708: 011686b3 add a3,a3,a7 +8001270c: 00967633 and a2,a2,s1 +80012710: 00a68d33 add s10,a3,a0 +80012714: 009f7f33 and t5,t5,s1 +80012718: 00be0e33 add t3,t3,a1 +8001271c: 01061613 slli a2,a2,0x10 +80012720: 01e60633 add a2,a2,t5 +80012724: 00be35b3 sltu a1,t3,a1 +80012728: 012d0f33 add t5,s10,s2 +8001272c: 010e0e33 add t3,t3,a6 +80012730: 00bf03b3 add t2,t5,a1 +80012734: 01638eb3 add t4,t2,s6 +80012738: 07c12823 sw t3,112(sp) +8001273c: 010e3e33 sltu t3,t3,a6 +80012740: 01ce8db3 add s11,t4,t3 +80012744: 0116b6b3 sltu a3,a3,a7 +80012748: 00b3b5b3 sltu a1,t2,a1 +8001274c: 00ad3533 sltu a0,s10,a0 +80012750: 012f3933 sltu s2,t5,s2 +80012754: 00a6e533 or a0,a3,a0 +80012758: 00b96933 or s2,s2,a1 +8001275c: 016ebeb3 sltu t4,t4,s6 +80012760: 01cdbe33 sltu t3,s11,t3 +80012764: 01250533 add a0,a0,s2 +80012768: 01ceeeb3 or t4,t4,t3 +8001276c: 00ed8833 add a6,s11,a4 +80012770: 01d50533 add a0,a0,t4 +80012774: 00e83733 sltu a4,a6,a4 +80012778: 00850533 add a0,a0,s0 +8001277c: 00e506b3 add a3,a0,a4 +80012780: 00853433 sltu s0,a0,s0 +80012784: 02698533 mul a0,s3,t1 +80012788: 00c80833 add a6,a6,a2 +8001278c: 00e6b733 sltu a4,a3,a4 +80012790: 00c83633 sltu a2,a6,a2 +80012794: 018686b3 add a3,a3,s8 +80012798: 00c685b3 add a1,a3,a2 +8001279c: 0186bc33 sltu s8,a3,s8 +800127a0: 00c5b633 sltu a2,a1,a2 +800127a4: 07012a23 sw a6,116(sp) +800127a8: 00e46733 or a4,s0,a4 +800127ac: 026f8333 mul t1,t6,t1 +800127b0: 01055693 srli a3,a0,0x10 +800127b4: 00cc6633 or a2,s8,a2 +800127b8: 033289b3 mul s3,t0,s3 +800127bc: 006989b3 add s3,s3,t1 +800127c0: 03f28fb3 mul t6,t0,t6 +800127c4: 013682b3 add t0,a3,s3 +800127c8: 0062f463 bgeu t0,t1,800127d0 <__multf3+0xad0> +800127cc: 019f8fb3 add t6,t6,s9 +800127d0: 0092f6b3 and a3,t0,s1 +800127d4: 01069693 slli a3,a3,0x10 +800127d8: 009574b3 and s1,a0,s1 +800127dc: 0102d293 srli t0,t0,0x10 +800127e0: 009684b3 add s1,a3,s1 +800127e4: 00e282b3 add t0,t0,a4 +800127e8: 01012683 lw a3,16(sp) +800127ec: 02012703 lw a4,32(sp) +800127f0: 009585b3 add a1,a1,s1 +800127f4: 0095b4b3 sltu s1,a1,s1 +800127f8: 00d769b3 or s3,a4,a3 +800127fc: 01412703 lw a4,20(sp) +80012800: 00c282b3 add t0,t0,a2 +80012804: 009282b3 add t0,t0,s1 +80012808: 013769b3 or s3,a4,s3 +8001280c: 01f28fb3 add t6,t0,t6 +80012810: 00d79793 slli a5,a5,0xd +80012814: 06b12c23 sw a1,120(sp) +80012818: 07f12e23 sw t6,124(sp) +8001281c: 0137e7b3 or a5,a5,s3 +80012820: 06010713 addi a4,sp,96 +80012824: 07010593 addi a1,sp,112 +80012828: 00c72683 lw a3,12(a4) +8001282c: 01072603 lw a2,16(a4) +80012830: 00470713 addi a4,a4,4 +80012834: 0136d693 srli a3,a3,0x13 +80012838: 00d61613 slli a2,a2,0xd +8001283c: 00c6e6b3 or a3,a3,a2 +80012840: fed72e23 sw a3,-4(a4) +80012844: fee592e3 bne a1,a4,80012828 <__multf3+0xb28> +80012848: 06012703 lw a4,96(sp) +8001284c: 06812683 lw a3,104(sp) +80012850: 00f037b3 snez a5,a5 +80012854: 00e7e7b3 or a5,a5,a4 +80012858: 04d12c23 sw a3,88(sp) +8001285c: 06c12703 lw a4,108(sp) +80012860: 06412683 lw a3,100(sp) +80012864: 04f12823 sw a5,80(sp) +80012868: 04e12e23 sw a4,92(sp) +8001286c: 04d12a23 sw a3,84(sp) +80012870: 00b71693 slli a3,a4,0xb +80012874: 2006dc63 bgez a3,80012a8c <__multf3+0xd8c> +80012878: 01f79793 slli a5,a5,0x1f +8001287c: 05010713 addi a4,sp,80 +80012880: 05c10593 addi a1,sp,92 +80012884: 00072683 lw a3,0(a4) +80012888: 00472603 lw a2,4(a4) +8001288c: 00470713 addi a4,a4,4 +80012890: 0016d693 srli a3,a3,0x1 +80012894: 01f61613 slli a2,a2,0x1f +80012898: 00c6e6b3 or a3,a3,a2 +8001289c: fed72e23 sw a3,-4(a4) +800128a0: fee592e3 bne a1,a4,80012884 <__multf3+0xb84> +800128a4: 05c12703 lw a4,92(sp) +800128a8: 00f037b3 snez a5,a5 +800128ac: 00175713 srli a4,a4,0x1 +800128b0: 04e12e23 sw a4,92(sp) +800128b4: 05012703 lw a4,80(sp) +800128b8: 00f767b3 or a5,a4,a5 +800128bc: 04f12823 sw a5,80(sp) +800128c0: 01812703 lw a4,24(sp) +800128c4: 000047b7 lui a5,0x4 +800128c8: fff78793 addi a5,a5,-1 # 3fff <_start-0x7fffc001> +800128cc: 00f707b3 add a5,a4,a5 +800128d0: 1ef05063 blez a5,80012ab0 <__multf3+0xdb0> +800128d4: 05012703 lw a4,80(sp) +800128d8: 00777693 andi a3,a4,7 +800128dc: 04068463 beqz a3,80012924 <__multf3+0xc24> +800128e0: 00f77693 andi a3,a4,15 +800128e4: 00400613 li a2,4 +800128e8: 02c68e63 beq a3,a2,80012924 <__multf3+0xc24> +800128ec: 05412683 lw a3,84(sp) +800128f0: 00470713 addi a4,a4,4 +800128f4: 04e12823 sw a4,80(sp) +800128f8: 00473713 sltiu a4,a4,4 +800128fc: 00d706b3 add a3,a4,a3 +80012900: 00e6b733 sltu a4,a3,a4 +80012904: 04d12a23 sw a3,84(sp) +80012908: 05812683 lw a3,88(sp) +8001290c: 00d706b3 add a3,a4,a3 +80012910: 04d12c23 sw a3,88(sp) +80012914: 00e6b6b3 sltu a3,a3,a4 +80012918: 05c12703 lw a4,92(sp) +8001291c: 00e686b3 add a3,a3,a4 +80012920: 04d12e23 sw a3,92(sp) +80012924: 05c12703 lw a4,92(sp) +80012928: 00b71693 slli a3,a4,0xb +8001292c: 0206d063 bgez a3,8001294c <__multf3+0xc4c> +80012930: fff007b7 lui a5,0xfff00 +80012934: fff78793 addi a5,a5,-1 # ffefffff <__BSS_END__+0x7fee93c3> +80012938: 00f77733 and a4,a4,a5 +8001293c: 04e12e23 sw a4,92(sp) +80012940: 01812703 lw a4,24(sp) +80012944: 000047b7 lui a5,0x4 +80012948: 00f707b3 add a5,a4,a5 +8001294c: 05010713 addi a4,sp,80 +80012950: 05c10593 addi a1,sp,92 +80012954: 00072683 lw a3,0(a4) +80012958: 00472603 lw a2,4(a4) +8001295c: 00470713 addi a4,a4,4 +80012960: 0036d693 srli a3,a3,0x3 +80012964: 01d61613 slli a2,a2,0x1d +80012968: 00c6e6b3 or a3,a3,a2 +8001296c: fed72e23 sw a3,-4(a4) +80012970: feb712e3 bne a4,a1,80012954 <__multf3+0xc54> +80012974: 00008737 lui a4,0x8 +80012978: ffe70693 addi a3,a4,-2 # 7ffe <_start-0x7fff8002> +8001297c: 10f6ce63 blt a3,a5,80012a98 <__multf3+0xd98> +80012980: 05c12703 lw a4,92(sp) +80012984: 00375713 srli a4,a4,0x3 +80012988: 04e12e23 sw a4,92(sp) +8001298c: 05c12703 lw a4,92(sp) +80012990: 01179793 slli a5,a5,0x11 +80012994: 0117d793 srli a5,a5,0x11 +80012998: 06e11623 sh a4,108(sp) +8001299c: 00c12703 lw a4,12(sp) +800129a0: 0bc12083 lw ra,188(sp) +800129a4: 0b812403 lw s0,184(sp) +800129a8: 00f71713 slli a4,a4,0xf +800129ac: 00f767b3 or a5,a4,a5 +800129b0: 06f11723 sh a5,110(sp) +800129b4: 00812703 lw a4,8(sp) +800129b8: 05012783 lw a5,80(sp) +800129bc: 0b412483 lw s1,180(sp) +800129c0: 0b012903 lw s2,176(sp) +800129c4: 00f72023 sw a5,0(a4) +800129c8: 05412783 lw a5,84(sp) +800129cc: 0ac12983 lw s3,172(sp) +800129d0: 0a812a03 lw s4,168(sp) +800129d4: 00f72223 sw a5,4(a4) +800129d8: 05812783 lw a5,88(sp) +800129dc: 0a412a83 lw s5,164(sp) +800129e0: 0a012b03 lw s6,160(sp) +800129e4: 00f72423 sw a5,8(a4) +800129e8: 06c12783 lw a5,108(sp) +800129ec: 09c12b83 lw s7,156(sp) +800129f0: 09812c03 lw s8,152(sp) +800129f4: 00f72623 sw a5,12(a4) +800129f8: 09412c83 lw s9,148(sp) +800129fc: 09012d03 lw s10,144(sp) +80012a00: 08c12d83 lw s11,140(sp) +80012a04: 00070513 mv a0,a4 +80012a08: 0c010113 addi sp,sp,192 +80012a0c: 00008067 ret +80012a10: 00912623 sw s1,12(sp) +80012a14: 03012783 lw a5,48(sp) +80012a18: 04f12823 sw a5,80(sp) +80012a1c: 03412783 lw a5,52(sp) +80012a20: 04f12a23 sw a5,84(sp) +80012a24: 03812783 lw a5,56(sp) +80012a28: 04f12c23 sw a5,88(sp) +80012a2c: 03c12783 lw a5,60(sp) +80012a30: 04f12e23 sw a5,92(sp) +80012a34: 00200793 li a5,2 +80012a38: 28fb0863 beq s6,a5,80012cc8 <__multf3+0xfc8> +80012a3c: 00300793 li a5,3 +80012a40: 2afb0263 beq s6,a5,80012ce4 <__multf3+0xfe4> +80012a44: 00100793 li a5,1 +80012a48: e6fb1ce3 bne s6,a5,800128c0 <__multf3+0xbc0> +80012a4c: 04012e23 sw zero,92(sp) +80012a50: 04012c23 sw zero,88(sp) +80012a54: 04012a23 sw zero,84(sp) +80012a58: 04012823 sw zero,80(sp) +80012a5c: 22c0006f j 80012c88 <__multf3+0xf88> +80012a60: 01212623 sw s2,12(sp) +80012a64: 04012783 lw a5,64(sp) +80012a68: 00070b13 mv s6,a4 +80012a6c: 04f12823 sw a5,80(sp) +80012a70: 04412783 lw a5,68(sp) +80012a74: 04f12a23 sw a5,84(sp) +80012a78: 04812783 lw a5,72(sp) +80012a7c: 04f12c23 sw a5,88(sp) +80012a80: 04c12783 lw a5,76(sp) +80012a84: 04f12e23 sw a5,92(sp) +80012a88: fadff06f j 80012a34 <__multf3+0xd34> +80012a8c: 01c12783 lw a5,28(sp) +80012a90: 00f12c23 sw a5,24(sp) +80012a94: e2dff06f j 800128c0 <__multf3+0xbc0> +80012a98: 04012e23 sw zero,92(sp) +80012a9c: 04012c23 sw zero,88(sp) +80012aa0: 04012a23 sw zero,84(sp) +80012aa4: 04012823 sw zero,80(sp) +80012aa8: fff70793 addi a5,a4,-1 +80012aac: ee1ff06f j 8001298c <__multf3+0xc8c> +80012ab0: 00100693 li a3,1 +80012ab4: 40f686b3 sub a3,a3,a5 +80012ab8: 07400793 li a5,116 +80012abc: 1cd7ca63 blt a5,a3,80012c90 <__multf3+0xf90> +80012ac0: 4056d513 srai a0,a3,0x5 +80012ac4: 00000793 li a5,0 +80012ac8: 00000713 li a4,0 +80012acc: 04a71663 bne a4,a0,80012b18 <__multf3+0xe18> +80012ad0: 01f6f693 andi a3,a3,31 +80012ad4: 00251593 slli a1,a0,0x2 +80012ad8: 04069e63 bnez a3,80012b34 <__multf3+0xe34> +80012adc: 00300613 li a2,3 +80012ae0: 05010713 addi a4,sp,80 +80012ae4: 40a60633 sub a2,a2,a0 +80012ae8: 00b70833 add a6,a4,a1 +80012aec: 00082803 lw a6,0(a6) +80012af0: 00168693 addi a3,a3,1 +80012af4: 00470713 addi a4,a4,4 +80012af8: ff072e23 sw a6,-4(a4) +80012afc: fed656e3 bge a2,a3,80012ae8 <__multf3+0xde8> +80012b00: 00400713 li a4,4 +80012b04: 40a70533 sub a0,a4,a0 +80012b08: 00100713 li a4,1 +80012b0c: 08a05063 blez a0,80012b8c <__multf3+0xe8c> +80012b10: 00050713 mv a4,a0 +80012b14: 0780006f j 80012b8c <__multf3+0xe8c> +80012b18: 00271613 slli a2,a4,0x2 +80012b1c: 05010593 addi a1,sp,80 +80012b20: 00c58633 add a2,a1,a2 +80012b24: 00062603 lw a2,0(a2) +80012b28: 00170713 addi a4,a4,1 +80012b2c: 00c7e7b3 or a5,a5,a2 +80012b30: f9dff06f j 80012acc <__multf3+0xdcc> +80012b34: 08010713 addi a4,sp,128 +80012b38: 00b70733 add a4,a4,a1 +80012b3c: fd072703 lw a4,-48(a4) +80012b40: 02000893 li a7,32 +80012b44: 40d888b3 sub a7,a7,a3 +80012b48: 01171733 sll a4,a4,a7 +80012b4c: 00e7e7b3 or a5,a5,a4 +80012b50: 00300613 li a2,3 +80012b54: 05010713 addi a4,sp,80 +80012b58: 00b705b3 add a1,a4,a1 +80012b5c: 00000813 li a6,0 +80012b60: 40a60633 sub a2,a2,a0 +80012b64: 00458593 addi a1,a1,4 +80012b68: 02c84663 blt a6,a2,80012b94 <__multf3+0xe94> +80012b6c: 08010593 addi a1,sp,128 +80012b70: 00261613 slli a2,a2,0x2 +80012b74: 00c58633 add a2,a1,a2 +80012b78: 05c12583 lw a1,92(sp) +80012b7c: 00400713 li a4,4 +80012b80: 40a70733 sub a4,a4,a0 +80012b84: 00d5d6b3 srl a3,a1,a3 +80012b88: fcd62823 sw a3,-48(a2) +80012b8c: 00400613 li a2,4 +80012b90: 0440006f j 80012bd4 <__multf3+0xed4> +80012b94: 00281313 slli t1,a6,0x2 +80012b98: 05010713 addi a4,sp,80 +80012b9c: 0005ae03 lw t3,0(a1) +80012ba0: 00670333 add t1,a4,t1 +80012ba4: ffc5a703 lw a4,-4(a1) +80012ba8: 011e1e33 sll t3,t3,a7 +80012bac: 00180813 addi a6,a6,1 +80012bb0: 00d75733 srl a4,a4,a3 +80012bb4: 01c76733 or a4,a4,t3 +80012bb8: 00e32023 sw a4,0(t1) +80012bbc: fa9ff06f j 80012b64 <__multf3+0xe64> +80012bc0: 00271693 slli a3,a4,0x2 +80012bc4: 05010593 addi a1,sp,80 +80012bc8: 00d586b3 add a3,a1,a3 +80012bcc: 0006a023 sw zero,0(a3) +80012bd0: 00170713 addi a4,a4,1 +80012bd4: fec716e3 bne a4,a2,80012bc0 <__multf3+0xec0> +80012bd8: 05012683 lw a3,80(sp) +80012bdc: 00f037b3 snez a5,a5 +80012be0: 00d7e7b3 or a5,a5,a3 +80012be4: 04f12823 sw a5,80(sp) +80012be8: 0077f693 andi a3,a5,7 +80012bec: 04068263 beqz a3,80012c30 <__multf3+0xf30> +80012bf0: 00f7f693 andi a3,a5,15 +80012bf4: 02e68e63 beq a3,a4,80012c30 <__multf3+0xf30> +80012bf8: 05412703 lw a4,84(sp) +80012bfc: 00478793 addi a5,a5,4 # 4004 <_start-0x7fffbffc> +80012c00: 04f12823 sw a5,80(sp) +80012c04: 0047b793 sltiu a5,a5,4 +80012c08: 00e78733 add a4,a5,a4 +80012c0c: 00f737b3 sltu a5,a4,a5 +80012c10: 04e12a23 sw a4,84(sp) +80012c14: 05812703 lw a4,88(sp) +80012c18: 00e78733 add a4,a5,a4 +80012c1c: 04e12c23 sw a4,88(sp) +80012c20: 00f73733 sltu a4,a4,a5 +80012c24: 05c12783 lw a5,92(sp) +80012c28: 00f70733 add a4,a4,a5 +80012c2c: 04e12e23 sw a4,92(sp) +80012c30: 05c12783 lw a5,92(sp) +80012c34: 00c79713 slli a4,a5,0xc +80012c38: 00075e63 bgez a4,80012c54 <__multf3+0xf54> +80012c3c: 04012e23 sw zero,92(sp) +80012c40: 04012c23 sw zero,88(sp) +80012c44: 04012a23 sw zero,84(sp) +80012c48: 04012823 sw zero,80(sp) +80012c4c: 00100793 li a5,1 +80012c50: d3dff06f j 8001298c <__multf3+0xc8c> +80012c54: 05010793 addi a5,sp,80 +80012c58: 05c10613 addi a2,sp,92 +80012c5c: 0007a703 lw a4,0(a5) +80012c60: 0047a683 lw a3,4(a5) +80012c64: 00478793 addi a5,a5,4 +80012c68: 00375713 srli a4,a4,0x3 +80012c6c: 01d69693 slli a3,a3,0x1d +80012c70: 00d76733 or a4,a4,a3 +80012c74: fee7ae23 sw a4,-4(a5) +80012c78: fef612e3 bne a2,a5,80012c5c <__multf3+0xf5c> +80012c7c: 05c12783 lw a5,92(sp) +80012c80: 0037d793 srli a5,a5,0x3 +80012c84: 04f12e23 sw a5,92(sp) +80012c88: 00000793 li a5,0 +80012c8c: d01ff06f j 8001298c <__multf3+0xc8c> +80012c90: 05412783 lw a5,84(sp) +80012c94: 05012703 lw a4,80(sp) +80012c98: 00f76733 or a4,a4,a5 +80012c9c: 05812783 lw a5,88(sp) +80012ca0: 00f76733 or a4,a4,a5 +80012ca4: 05c12783 lw a5,92(sp) +80012ca8: 00f76733 or a4,a4,a5 +80012cac: 00000793 li a5,0 +80012cb0: cc070ee3 beqz a4,8001298c <__multf3+0xc8c> +80012cb4: 04012e23 sw zero,92(sp) +80012cb8: 04012c23 sw zero,88(sp) +80012cbc: 04012a23 sw zero,84(sp) +80012cc0: 04012823 sw zero,80(sp) +80012cc4: cc9ff06f j 8001298c <__multf3+0xc8c> +80012cc8: 000087b7 lui a5,0x8 +80012ccc: 04012e23 sw zero,92(sp) +80012cd0: 04012c23 sw zero,88(sp) +80012cd4: 04012a23 sw zero,84(sp) +80012cd8: 04012823 sw zero,80(sp) +80012cdc: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80012ce0: cadff06f j 8001298c <__multf3+0xc8c> +80012ce4: 000087b7 lui a5,0x8 +80012ce8: 04f12e23 sw a5,92(sp) +80012cec: 04012c23 sw zero,88(sp) +80012cf0: 04012a23 sw zero,84(sp) +80012cf4: 04012823 sw zero,80(sp) +80012cf8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80012cfc: 00012623 sw zero,12(sp) +80012d00: c8dff06f j 8001298c <__multf3+0xc8c> -80012c40 <__subtf3>: -80012c40: fa010113 addi sp,sp,-96 -80012c44: 0085a783 lw a5,8(a1) -80012c48: 05212823 sw s2,80(sp) -80012c4c: 00c5a903 lw s2,12(a1) -80012c50: 0005a883 lw a7,0(a1) -80012c54: 0045a703 lw a4,4(a1) -80012c58: 04912a23 sw s1,84(sp) -80012c5c: 02f12c23 sw a5,56(sp) -80012c60: 00050493 mv s1,a0 -80012c64: 00f12c23 sw a5,24(sp) -80012c68: 00062803 lw a6,0(a2) -80012c6c: 01091793 slli a5,s2,0x10 -80012c70: 00462503 lw a0,4(a2) -80012c74: 00862683 lw a3,8(a2) -80012c78: 00c62e03 lw t3,12(a2) -80012c7c: 04812c23 sw s0,88(sp) -80012c80: 0107d793 srli a5,a5,0x10 -80012c84: 00191413 slli s0,s2,0x1 -80012c88: 03212e23 sw s2,60(sp) -80012c8c: 04112e23 sw ra,92(sp) -80012c90: 05312623 sw s3,76(sp) -80012c94: 05412423 sw s4,72(sp) -80012c98: 05512223 sw s5,68(sp) -80012c9c: 05612023 sw s6,64(sp) -80012ca0: 03112823 sw a7,48(sp) -80012ca4: 02e12a23 sw a4,52(sp) -80012ca8: 01112823 sw a7,16(sp) -80012cac: 00e12a23 sw a4,20(sp) -80012cb0: 00f12e23 sw a5,28(sp) -80012cb4: 01145413 srli s0,s0,0x11 -80012cb8: 01f95913 srli s2,s2,0x1f -80012cbc: 01010f13 addi t5,sp,16 -80012cc0: 01c10593 addi a1,sp,28 -80012cc4: 0005a783 lw a5,0(a1) -80012cc8: ffc5a703 lw a4,-4(a1) -80012ccc: ffc58593 addi a1,a1,-4 -80012cd0: 00379793 slli a5,a5,0x3 -80012cd4: 01d75713 srli a4,a4,0x1d -80012cd8: 00e7e7b3 or a5,a5,a4 -80012cdc: 00f5a223 sw a5,4(a1) -80012ce0: febf12e3 bne t5,a1,80012cc4 <__subtf3+0x84> -80012ce4: 01012703 lw a4,16(sp) -80012ce8: 010e1793 slli a5,t3,0x10 -80012cec: 001e1e93 slli t4,t3,0x1 -80012cf0: 00371713 slli a4,a4,0x3 -80012cf4: 0107d793 srli a5,a5,0x10 -80012cf8: 03012823 sw a6,48(sp) -80012cfc: 02d12c23 sw a3,56(sp) -80012d00: 03c12e23 sw t3,60(sp) -80012d04: 03012023 sw a6,32(sp) -80012d08: 02d12423 sw a3,40(sp) -80012d0c: 00e12823 sw a4,16(sp) -80012d10: 02a12a23 sw a0,52(sp) -80012d14: 02a12223 sw a0,36(sp) -80012d18: 02f12623 sw a5,44(sp) -80012d1c: 011ede93 srli t4,t4,0x11 -80012d20: 01fe5e13 srli t3,t3,0x1f -80012d24: 02010813 addi a6,sp,32 -80012d28: 02c10693 addi a3,sp,44 -80012d2c: 0006a783 lw a5,0(a3) -80012d30: ffc6a603 lw a2,-4(a3) -80012d34: ffc68693 addi a3,a3,-4 -80012d38: 00379793 slli a5,a5,0x3 -80012d3c: 01d65613 srli a2,a2,0x1d -80012d40: 00c7e7b3 or a5,a5,a2 -80012d44: 00f6a223 sw a5,4(a3) -80012d48: fed812e3 bne a6,a3,80012d2c <__subtf3+0xec> -80012d4c: 02012783 lw a5,32(sp) -80012d50: 00008637 lui a2,0x8 -80012d54: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> -80012d58: 00379793 slli a5,a5,0x3 -80012d5c: 02f12023 sw a5,32(sp) -80012d60: 02ce9063 bne t4,a2,80012d80 <__subtf3+0x140> -80012d64: 02812503 lw a0,40(sp) -80012d68: 02412603 lw a2,36(sp) -80012d6c: 00a66633 or a2,a2,a0 -80012d70: 02c12503 lw a0,44(sp) -80012d74: 00a66633 or a2,a2,a0 -80012d78: 00f66633 or a2,a2,a5 -80012d7c: 00061463 bnez a2,80012d84 <__subtf3+0x144> -80012d80: 001e4e13 xori t3,t3,1 -80012d84: 41d40333 sub t1,s0,t4 -80012d88: 0f2e1ee3 bne t3,s2,80013684 <__subtf3+0xa44> -80012d8c: 44605a63 blez t1,800131e0 <__subtf3+0x5a0> -80012d90: 01412f03 lw t5,20(sp) -80012d94: 01812e03 lw t3,24(sp) -80012d98: 01c12883 lw a7,28(sp) -80012d9c: 0a0e9c63 bnez t4,80012e54 <__subtf3+0x214> -80012da0: 02412503 lw a0,36(sp) -80012da4: 02812603 lw a2,40(sp) -80012da8: 02c12e83 lw t4,44(sp) -80012dac: 00c565b3 or a1,a0,a2 -80012db0: 01d5e5b3 or a1,a1,t4 -80012db4: 00f5e5b3 or a1,a1,a5 -80012db8: 00059e63 bnez a1,80012dd4 <__subtf3+0x194> -80012dbc: 02e12823 sw a4,48(sp) -80012dc0: 03e12a23 sw t5,52(sp) -80012dc4: 03c12c23 sw t3,56(sp) -80012dc8: 03112e23 sw a7,60(sp) -80012dcc: 00030413 mv s0,t1 -80012dd0: 0a00006f j 80012e70 <__subtf3+0x230> -80012dd4: fff30593 addi a1,t1,-1 -80012dd8: 04059a63 bnez a1,80012e2c <__subtf3+0x1ec> -80012ddc: 00f707b3 add a5,a4,a5 -80012de0: 00e7b733 sltu a4,a5,a4 -80012de4: 01e505b3 add a1,a0,t5 -80012de8: 02f12823 sw a5,48(sp) -80012dec: 00e587b3 add a5,a1,a4 -80012df0: 00e7b733 sltu a4,a5,a4 -80012df4: 01e5b5b3 sltu a1,a1,t5 -80012df8: 00e5e733 or a4,a1,a4 -80012dfc: 02f12a23 sw a5,52(sp) -80012e00: 01c607b3 add a5,a2,t3 -80012e04: 00e786b3 add a3,a5,a4 -80012e08: 00e6b733 sltu a4,a3,a4 -80012e0c: 01c7b7b3 sltu a5,a5,t3 -80012e10: 00e7e7b3 or a5,a5,a4 -80012e14: 011e88b3 add a7,t4,a7 -80012e18: 011787b3 add a5,a5,a7 -80012e1c: 02d12c23 sw a3,56(sp) -80012e20: 02f12e23 sw a5,60(sp) -80012e24: 00100413 li s0,1 -80012e28: 32c0006f j 80013154 <__subtf3+0x514> -80012e2c: 000087b7 lui a5,0x8 -80012e30: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012e34: f8f304e3 beq t1,a5,80012dbc <__subtf3+0x17c> -80012e38: 07400793 li a5,116 -80012e3c: 1ab7d463 bge a5,a1,80012fe4 <__subtf3+0x3a4> -80012e40: 02012623 sw zero,44(sp) -80012e44: 02012423 sw zero,40(sp) -80012e48: 02012223 sw zero,36(sp) -80012e4c: 00100793 li a5,1 -80012e50: 2a80006f j 800130f8 <__subtf3+0x4b8> -80012e54: 000087b7 lui a5,0x8 -80012e58: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012e5c: 16f41663 bne s0,a5,80012fc8 <__subtf3+0x388> -80012e60: 02e12823 sw a4,48(sp) -80012e64: 03e12a23 sw t5,52(sp) -80012e68: 03c12c23 sw t3,56(sp) -80012e6c: 03112e23 sw a7,60(sp) -80012e70: 03012783 lw a5,48(sp) -80012e74: 0077f713 andi a4,a5,7 -80012e78: 04070463 beqz a4,80012ec0 <__subtf3+0x280> -80012e7c: 00f7f713 andi a4,a5,15 -80012e80: 00400693 li a3,4 -80012e84: 02d70e63 beq a4,a3,80012ec0 <__subtf3+0x280> -80012e88: 03412703 lw a4,52(sp) -80012e8c: 00478793 addi a5,a5,4 -80012e90: 02f12823 sw a5,48(sp) -80012e94: 0047b793 sltiu a5,a5,4 -80012e98: 00e78733 add a4,a5,a4 -80012e9c: 00f737b3 sltu a5,a4,a5 -80012ea0: 02e12a23 sw a4,52(sp) -80012ea4: 03812703 lw a4,56(sp) -80012ea8: 00e78733 add a4,a5,a4 -80012eac: 02e12c23 sw a4,56(sp) -80012eb0: 00f73733 sltu a4,a4,a5 -80012eb4: 03c12783 lw a5,60(sp) -80012eb8: 00f70733 add a4,a4,a5 -80012ebc: 02e12e23 sw a4,60(sp) -80012ec0: 03c12783 lw a5,60(sp) -80012ec4: 00c79713 slli a4,a5,0xc -80012ec8: 02075463 bgez a4,80012ef0 <__subtf3+0x2b0> -80012ecc: 00008737 lui a4,0x8 -80012ed0: 00140413 addi s0,s0,1 -80012ed4: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80012ed8: 00e41463 bne s0,a4,80012ee0 <__subtf3+0x2a0> -80012edc: 2700106f j 8001414c <__subtf3+0x150c> -80012ee0: fff80737 lui a4,0xfff80 -80012ee4: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693cf> -80012ee8: 00e7f7b3 and a5,a5,a4 -80012eec: 02f12e23 sw a5,60(sp) -80012ef0: 03010793 addi a5,sp,48 -80012ef4: 03c10613 addi a2,sp,60 -80012ef8: 0007a703 lw a4,0(a5) -80012efc: 0047a683 lw a3,4(a5) -80012f00: 00478793 addi a5,a5,4 -80012f04: 00375713 srli a4,a4,0x3 -80012f08: 01d69693 slli a3,a3,0x1d -80012f0c: 00d76733 or a4,a4,a3 -80012f10: fee7ae23 sw a4,-4(a5) -80012f14: fef612e3 bne a2,a5,80012ef8 <__subtf3+0x2b8> -80012f18: 03c12783 lw a5,60(sp) -80012f1c: 000086b7 lui a3,0x8 -80012f20: 0037d713 srli a4,a5,0x3 -80012f24: 02e12e23 sw a4,60(sp) -80012f28: fff68793 addi a5,a3,-1 # 7fff <_start-0x7fff8001> -80012f2c: 02f41a63 bne s0,a5,80012f60 <__subtf3+0x320> -80012f30: 03412603 lw a2,52(sp) +80012d04 <__subtf3>: +80012d04: fa010113 addi sp,sp,-96 +80012d08: 0085a783 lw a5,8(a1) +80012d0c: 05212823 sw s2,80(sp) +80012d10: 00c5a903 lw s2,12(a1) +80012d14: 0005a883 lw a7,0(a1) +80012d18: 0045a703 lw a4,4(a1) +80012d1c: 04912a23 sw s1,84(sp) +80012d20: 02f12c23 sw a5,56(sp) +80012d24: 00050493 mv s1,a0 +80012d28: 00f12c23 sw a5,24(sp) +80012d2c: 00062803 lw a6,0(a2) +80012d30: 01091793 slli a5,s2,0x10 +80012d34: 00462503 lw a0,4(a2) +80012d38: 00862683 lw a3,8(a2) +80012d3c: 00c62e03 lw t3,12(a2) +80012d40: 04812c23 sw s0,88(sp) +80012d44: 0107d793 srli a5,a5,0x10 +80012d48: 00191413 slli s0,s2,0x1 +80012d4c: 03212e23 sw s2,60(sp) +80012d50: 04112e23 sw ra,92(sp) +80012d54: 05312623 sw s3,76(sp) +80012d58: 05412423 sw s4,72(sp) +80012d5c: 05512223 sw s5,68(sp) +80012d60: 05612023 sw s6,64(sp) +80012d64: 03112823 sw a7,48(sp) +80012d68: 02e12a23 sw a4,52(sp) +80012d6c: 01112823 sw a7,16(sp) +80012d70: 00e12a23 sw a4,20(sp) +80012d74: 00f12e23 sw a5,28(sp) +80012d78: 01145413 srli s0,s0,0x11 +80012d7c: 01f95913 srli s2,s2,0x1f +80012d80: 01010f13 addi t5,sp,16 +80012d84: 01c10593 addi a1,sp,28 +80012d88: 0005a783 lw a5,0(a1) +80012d8c: ffc5a703 lw a4,-4(a1) +80012d90: ffc58593 addi a1,a1,-4 +80012d94: 00379793 slli a5,a5,0x3 +80012d98: 01d75713 srli a4,a4,0x1d +80012d9c: 00e7e7b3 or a5,a5,a4 +80012da0: 00f5a223 sw a5,4(a1) +80012da4: febf12e3 bne t5,a1,80012d88 <__subtf3+0x84> +80012da8: 01012703 lw a4,16(sp) +80012dac: 010e1793 slli a5,t3,0x10 +80012db0: 001e1e93 slli t4,t3,0x1 +80012db4: 00371713 slli a4,a4,0x3 +80012db8: 0107d793 srli a5,a5,0x10 +80012dbc: 03012823 sw a6,48(sp) +80012dc0: 02d12c23 sw a3,56(sp) +80012dc4: 03c12e23 sw t3,60(sp) +80012dc8: 03012023 sw a6,32(sp) +80012dcc: 02d12423 sw a3,40(sp) +80012dd0: 00e12823 sw a4,16(sp) +80012dd4: 02a12a23 sw a0,52(sp) +80012dd8: 02a12223 sw a0,36(sp) +80012ddc: 02f12623 sw a5,44(sp) +80012de0: 011ede93 srli t4,t4,0x11 +80012de4: 01fe5e13 srli t3,t3,0x1f +80012de8: 02010813 addi a6,sp,32 +80012dec: 02c10693 addi a3,sp,44 +80012df0: 0006a783 lw a5,0(a3) +80012df4: ffc6a603 lw a2,-4(a3) +80012df8: ffc68693 addi a3,a3,-4 +80012dfc: 00379793 slli a5,a5,0x3 +80012e00: 01d65613 srli a2,a2,0x1d +80012e04: 00c7e7b3 or a5,a5,a2 +80012e08: 00f6a223 sw a5,4(a3) +80012e0c: fed812e3 bne a6,a3,80012df0 <__subtf3+0xec> +80012e10: 02012783 lw a5,32(sp) +80012e14: 00008637 lui a2,0x8 +80012e18: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +80012e1c: 00379793 slli a5,a5,0x3 +80012e20: 02f12023 sw a5,32(sp) +80012e24: 02ce9063 bne t4,a2,80012e44 <__subtf3+0x140> +80012e28: 02812503 lw a0,40(sp) +80012e2c: 02412603 lw a2,36(sp) +80012e30: 00a66633 or a2,a2,a0 +80012e34: 02c12503 lw a0,44(sp) +80012e38: 00a66633 or a2,a2,a0 +80012e3c: 00f66633 or a2,a2,a5 +80012e40: 00061463 bnez a2,80012e48 <__subtf3+0x144> +80012e44: 001e4e13 xori t3,t3,1 +80012e48: 41d40333 sub t1,s0,t4 +80012e4c: 0f2e1ee3 bne t3,s2,80013748 <__subtf3+0xa44> +80012e50: 44605a63 blez t1,800132a4 <__subtf3+0x5a0> +80012e54: 01412f03 lw t5,20(sp) +80012e58: 01812e03 lw t3,24(sp) +80012e5c: 01c12883 lw a7,28(sp) +80012e60: 0a0e9c63 bnez t4,80012f18 <__subtf3+0x214> +80012e64: 02412503 lw a0,36(sp) +80012e68: 02812603 lw a2,40(sp) +80012e6c: 02c12e83 lw t4,44(sp) +80012e70: 00c565b3 or a1,a0,a2 +80012e74: 01d5e5b3 or a1,a1,t4 +80012e78: 00f5e5b3 or a1,a1,a5 +80012e7c: 00059e63 bnez a1,80012e98 <__subtf3+0x194> +80012e80: 02e12823 sw a4,48(sp) +80012e84: 03e12a23 sw t5,52(sp) +80012e88: 03c12c23 sw t3,56(sp) +80012e8c: 03112e23 sw a7,60(sp) +80012e90: 00030413 mv s0,t1 +80012e94: 0a00006f j 80012f34 <__subtf3+0x230> +80012e98: fff30593 addi a1,t1,-1 +80012e9c: 04059a63 bnez a1,80012ef0 <__subtf3+0x1ec> +80012ea0: 00f707b3 add a5,a4,a5 +80012ea4: 00e7b733 sltu a4,a5,a4 +80012ea8: 01e505b3 add a1,a0,t5 +80012eac: 02f12823 sw a5,48(sp) +80012eb0: 00e587b3 add a5,a1,a4 +80012eb4: 00e7b733 sltu a4,a5,a4 +80012eb8: 01e5b5b3 sltu a1,a1,t5 +80012ebc: 00e5e733 or a4,a1,a4 +80012ec0: 02f12a23 sw a5,52(sp) +80012ec4: 01c607b3 add a5,a2,t3 +80012ec8: 00e786b3 add a3,a5,a4 +80012ecc: 00e6b733 sltu a4,a3,a4 +80012ed0: 01c7b7b3 sltu a5,a5,t3 +80012ed4: 00e7e7b3 or a5,a5,a4 +80012ed8: 011e88b3 add a7,t4,a7 +80012edc: 011787b3 add a5,a5,a7 +80012ee0: 02d12c23 sw a3,56(sp) +80012ee4: 02f12e23 sw a5,60(sp) +80012ee8: 00100413 li s0,1 +80012eec: 32c0006f j 80013218 <__subtf3+0x514> +80012ef0: 000087b7 lui a5,0x8 +80012ef4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80012ef8: f8f304e3 beq t1,a5,80012e80 <__subtf3+0x17c> +80012efc: 07400793 li a5,116 +80012f00: 1ab7d463 bge a5,a1,800130a8 <__subtf3+0x3a4> +80012f04: 02012623 sw zero,44(sp) +80012f08: 02012423 sw zero,40(sp) +80012f0c: 02012223 sw zero,36(sp) +80012f10: 00100793 li a5,1 +80012f14: 2a80006f j 800131bc <__subtf3+0x4b8> +80012f18: 000087b7 lui a5,0x8 +80012f1c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80012f20: 16f41663 bne s0,a5,8001308c <__subtf3+0x388> +80012f24: 02e12823 sw a4,48(sp) +80012f28: 03e12a23 sw t5,52(sp) +80012f2c: 03c12c23 sw t3,56(sp) +80012f30: 03112e23 sw a7,60(sp) 80012f34: 03012783 lw a5,48(sp) -80012f38: 00c7e7b3 or a5,a5,a2 -80012f3c: 03812603 lw a2,56(sp) -80012f40: 00c7e7b3 or a5,a5,a2 -80012f44: 00e7e7b3 or a5,a5,a4 -80012f48: 00078c63 beqz a5,80012f60 <__subtf3+0x320> -80012f4c: 02d12e23 sw a3,60(sp) -80012f50: 02012c23 sw zero,56(sp) -80012f54: 02012a23 sw zero,52(sp) -80012f58: 02012823 sw zero,48(sp) -80012f5c: 00000913 li s2,0 -80012f60: 03c12783 lw a5,60(sp) -80012f64: 01141413 slli s0,s0,0x11 -80012f68: 01145413 srli s0,s0,0x11 -80012f6c: 00f11623 sh a5,12(sp) -80012f70: 03012783 lw a5,48(sp) -80012f74: 00f91913 slli s2,s2,0xf -80012f78: 00896933 or s2,s2,s0 -80012f7c: 00f4a023 sw a5,0(s1) # 80000 <_start-0x7ff80000> -80012f80: 03412783 lw a5,52(sp) -80012f84: 01211723 sh s2,14(sp) -80012f88: 05c12083 lw ra,92(sp) -80012f8c: 00f4a223 sw a5,4(s1) -80012f90: 03812783 lw a5,56(sp) -80012f94: 05812403 lw s0,88(sp) -80012f98: 05012903 lw s2,80(sp) -80012f9c: 00f4a423 sw a5,8(s1) -80012fa0: 00c12783 lw a5,12(sp) -80012fa4: 04c12983 lw s3,76(sp) -80012fa8: 04812a03 lw s4,72(sp) -80012fac: 00f4a623 sw a5,12(s1) -80012fb0: 04412a83 lw s5,68(sp) -80012fb4: 04012b03 lw s6,64(sp) -80012fb8: 00048513 mv a0,s1 -80012fbc: 05412483 lw s1,84(sp) -80012fc0: 06010113 addi sp,sp,96 -80012fc4: 00008067 ret -80012fc8: 02c12783 lw a5,44(sp) -80012fcc: 00080637 lui a2,0x80 -80012fd0: 00c7e7b3 or a5,a5,a2 -80012fd4: 02f12623 sw a5,44(sp) -80012fd8: 07400793 li a5,116 -80012fdc: e667c2e3 blt a5,t1,80012e40 <__subtf3+0x200> -80012fe0: 00030593 mv a1,t1 -80012fe4: 4055de93 srai t4,a1,0x5 -80012fe8: 00000793 li a5,0 -80012fec: 00000613 li a2,0 -80012ff0: 05d61663 bne a2,t4,8001303c <__subtf3+0x3fc> -80012ff4: 01f5f593 andi a1,a1,31 -80012ff8: 002e9313 slli t1,t4,0x2 -80012ffc: 04059c63 bnez a1,80013054 <__subtf3+0x414> -80013000: 00300593 li a1,3 -80013004: 00000613 li a2,0 -80013008: 41d585b3 sub a1,a1,t4 -8001300c: 00668533 add a0,a3,t1 -80013010: 00052503 lw a0,0(a0) -80013014: 00160613 addi a2,a2,1 # 80001 <_start-0x7ff7ffff> -80013018: 00468693 addi a3,a3,4 -8001301c: fea6ae23 sw a0,-4(a3) -80013020: fec5d6e3 bge a1,a2,8001300c <__subtf3+0x3cc> -80013024: 00400613 li a2,4 -80013028: 41d60eb3 sub t4,a2,t4 -8001302c: 00100613 li a2,1 -80013030: 07d05c63 blez t4,800130a8 <__subtf3+0x468> -80013034: 000e8613 mv a2,t4 -80013038: 0700006f j 800130a8 <__subtf3+0x468> -8001303c: 00261513 slli a0,a2,0x2 -80013040: 00a80533 add a0,a6,a0 -80013044: 00052503 lw a0,0(a0) -80013048: 00160613 addi a2,a2,1 -8001304c: 00a7e7b3 or a5,a5,a0 -80013050: fa1ff06f j 80012ff0 <__subtf3+0x3b0> -80013054: 04010693 addi a3,sp,64 -80013058: 006686b3 add a3,a3,t1 -8001305c: fe06a683 lw a3,-32(a3) -80013060: 02000f93 li t6,32 -80013064: 40bf8fb3 sub t6,t6,a1 -80013068: 01f696b3 sll a3,a3,t6 -8001306c: 00300513 li a0,3 -80013070: 00d7e7b3 or a5,a5,a3 -80013074: 00680333 add t1,a6,t1 -80013078: 00000613 li a2,0 -8001307c: 41d50533 sub a0,a0,t4 -80013080: 00430313 addi t1,t1,4 -80013084: 02a64663 blt a2,a0,800130b0 <__subtf3+0x470> -80013088: 04010693 addi a3,sp,64 -8001308c: 00251513 slli a0,a0,0x2 -80013090: 00a68533 add a0,a3,a0 -80013094: 02c12683 lw a3,44(sp) -80013098: 00400613 li a2,4 -8001309c: 41d60633 sub a2,a2,t4 -800130a0: 00b6d5b3 srl a1,a3,a1 -800130a4: feb52023 sw a1,-32(a0) -800130a8: 00400593 li a1,4 -800130ac: 03c0006f j 800130e8 <__subtf3+0x4a8> -800130b0: ffc32683 lw a3,-4(t1) -800130b4: 00032383 lw t2,0(t1) -800130b8: 00261293 slli t0,a2,0x2 -800130bc: 00b6d6b3 srl a3,a3,a1 -800130c0: 01f393b3 sll t2,t2,t6 -800130c4: 005802b3 add t0,a6,t0 -800130c8: 0076e6b3 or a3,a3,t2 -800130cc: 00d2a023 sw a3,0(t0) -800130d0: 00160613 addi a2,a2,1 -800130d4: fadff06f j 80013080 <__subtf3+0x440> -800130d8: 00261693 slli a3,a2,0x2 -800130dc: 00d806b3 add a3,a6,a3 -800130e0: 0006a023 sw zero,0(a3) -800130e4: 00160613 addi a2,a2,1 -800130e8: feb618e3 bne a2,a1,800130d8 <__subtf3+0x498> -800130ec: 02012683 lw a3,32(sp) -800130f0: 00f037b3 snez a5,a5 -800130f4: 00f6e7b3 or a5,a3,a5 -800130f8: 02f12023 sw a5,32(sp) -800130fc: 02012583 lw a1,32(sp) -80013100: 02412603 lw a2,36(sp) -80013104: 00b705b3 add a1,a4,a1 -80013108: 00e5b733 sltu a4,a1,a4 -8001310c: 00cf0633 add a2,t5,a2 -80013110: 00e606b3 add a3,a2,a4 -80013114: 02b12823 sw a1,48(sp) -80013118: 01e635b3 sltu a1,a2,t5 -8001311c: 02812603 lw a2,40(sp) -80013120: 00e6b733 sltu a4,a3,a4 -80013124: 00e5e5b3 or a1,a1,a4 -80013128: 02d12a23 sw a3,52(sp) -8001312c: 00ce06b3 add a3,t3,a2 -80013130: 00b687b3 add a5,a3,a1 -80013134: 00b7b5b3 sltu a1,a5,a1 -80013138: 02f12c23 sw a5,56(sp) -8001313c: 02c12783 lw a5,44(sp) -80013140: 01c6b6b3 sltu a3,a3,t3 -80013144: 00b6e6b3 or a3,a3,a1 -80013148: 00f888b3 add a7,a7,a5 -8001314c: 011686b3 add a3,a3,a7 -80013150: 02d12e23 sw a3,60(sp) -80013154: 03c12783 lw a5,60(sp) -80013158: 00c79713 slli a4,a5,0xc -8001315c: d0075ae3 bgez a4,80012e70 <__subtf3+0x230> -80013160: fff80737 lui a4,0xfff80 -80013164: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693cf> -80013168: 00e7f7b3 and a5,a5,a4 -8001316c: 02f12e23 sw a5,60(sp) -80013170: 03012783 lw a5,48(sp) -80013174: 00140413 addi s0,s0,1 -80013178: 03c10593 addi a1,sp,60 -8001317c: 01f79713 slli a4,a5,0x1f -80013180: 03010793 addi a5,sp,48 -80013184: 0007a683 lw a3,0(a5) -80013188: 0047a603 lw a2,4(a5) -8001318c: 00478793 addi a5,a5,4 -80013190: 0016d693 srli a3,a3,0x1 -80013194: 01f61613 slli a2,a2,0x1f -80013198: 00c6e6b3 or a3,a3,a2 -8001319c: fed7ae23 sw a3,-4(a5) -800131a0: fef592e3 bne a1,a5,80013184 <__subtf3+0x544> -800131a4: 03c12783 lw a5,60(sp) -800131a8: 0017d793 srli a5,a5,0x1 -800131ac: 02f12e23 sw a5,60(sp) -800131b0: 00e037b3 snez a5,a4 -800131b4: 03012703 lw a4,48(sp) -800131b8: 00f767b3 or a5,a4,a5 -800131bc: 02f12823 sw a5,48(sp) -800131c0: 000087b7 lui a5,0x8 -800131c4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800131c8: caf414e3 bne s0,a5,80012e70 <__subtf3+0x230> -800131cc: 02012e23 sw zero,60(sp) -800131d0: 02012c23 sw zero,56(sp) -800131d4: 02012a23 sw zero,52(sp) -800131d8: 02012823 sw zero,48(sp) -800131dc: c95ff06f j 80012e70 <__subtf3+0x230> -800131e0: 02412683 lw a3,36(sp) -800131e4: 02812603 lw a2,40(sp) -800131e8: 02c12503 lw a0,44(sp) -800131ec: 28030463 beqz t1,80013474 <__subtf3+0x834> -800131f0: 408e8e33 sub t3,t4,s0 -800131f4: 0a041a63 bnez s0,800132a8 <__subtf3+0x668> -800131f8: 01412883 lw a7,20(sp) -800131fc: 01812803 lw a6,24(sp) -80013200: 01c12f83 lw t6,28(sp) -80013204: 0108e333 or t1,a7,a6 -80013208: 01f36333 or t1,t1,t6 -8001320c: 00e36333 or t1,t1,a4 -80013210: 00031e63 bnez t1,8001322c <__subtf3+0x5ec> -80013214: 02f12823 sw a5,48(sp) -80013218: 02d12a23 sw a3,52(sp) -8001321c: 02c12c23 sw a2,56(sp) -80013220: 02a12e23 sw a0,60(sp) -80013224: 000e0413 mv s0,t3 -80013228: c49ff06f j 80012e70 <__subtf3+0x230> -8001322c: fffe0313 addi t1,t3,-1 -80013230: 04031863 bnez t1,80013280 <__subtf3+0x640> -80013234: 00f70733 add a4,a4,a5 -80013238: 00f737b3 sltu a5,a4,a5 -8001323c: 00d885b3 add a1,a7,a3 -80013240: 02e12823 sw a4,48(sp) -80013244: 00f58733 add a4,a1,a5 -80013248: 00f737b3 sltu a5,a4,a5 -8001324c: 00d5b6b3 sltu a3,a1,a3 -80013250: 00f6e6b3 or a3,a3,a5 -80013254: 02e12a23 sw a4,52(sp) -80013258: 00c80733 add a4,a6,a2 -8001325c: 00d707b3 add a5,a4,a3 -80013260: 00d7b6b3 sltu a3,a5,a3 -80013264: 00c73733 sltu a4,a4,a2 -80013268: 00d76733 or a4,a4,a3 -8001326c: 00af8533 add a0,t6,a0 -80013270: 00a70533 add a0,a4,a0 -80013274: 02f12c23 sw a5,56(sp) -80013278: 02a12e23 sw a0,60(sp) -8001327c: ba9ff06f j 80012e24 <__subtf3+0x1e4> -80013280: 00008737 lui a4,0x8 -80013284: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80013288: f8ee06e3 beq t3,a4,80013214 <__subtf3+0x5d4> -8001328c: 07400713 li a4,116 -80013290: 04675c63 bge a4,t1,800132e8 <__subtf3+0x6a8> -80013294: 00012e23 sw zero,28(sp) -80013298: 00012c23 sw zero,24(sp) -8001329c: 00012a23 sw zero,20(sp) -800132a0: 00100713 li a4,1 -800132a4: 16c0006f j 80013410 <__subtf3+0x7d0> -800132a8: 00008737 lui a4,0x8 -800132ac: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -800132b0: 00ee9e63 bne t4,a4,800132cc <__subtf3+0x68c> -800132b4: 02f12823 sw a5,48(sp) -800132b8: 02d12a23 sw a3,52(sp) -800132bc: 02c12c23 sw a2,56(sp) -800132c0: 02a12e23 sw a0,60(sp) -800132c4: 000e8413 mv s0,t4 -800132c8: ba9ff06f j 80012e70 <__subtf3+0x230> -800132cc: 01c12703 lw a4,28(sp) -800132d0: 00080837 lui a6,0x80 -800132d4: 01076733 or a4,a4,a6 -800132d8: 00e12e23 sw a4,28(sp) -800132dc: 07400713 li a4,116 -800132e0: fbc74ae3 blt a4,t3,80013294 <__subtf3+0x654> -800132e4: 000e0313 mv t1,t3 -800132e8: 02000713 li a4,32 -800132ec: 02e34e33 div t3,t1,a4 -800132f0: 00000f93 li t6,0 -800132f4: 00000713 li a4,0 -800132f8: 05c74a63 blt a4,t3,8001334c <__subtf3+0x70c> -800132fc: 000e0893 mv a7,t3 -80013300: 000e5463 bgez t3,80013308 <__subtf3+0x6c8> -80013304: 00000893 li a7,0 -80013308: 01f37713 andi a4,t1,31 -8001330c: 002e1813 slli a6,t3,0x2 -80013310: 04071a63 bnez a4,80013364 <__subtf3+0x724> -80013314: 00300893 li a7,3 -80013318: 41c888b3 sub a7,a7,t3 -8001331c: 01058333 add t1,a1,a6 -80013320: 00032303 lw t1,0(t1) -80013324: 00170713 addi a4,a4,1 -80013328: 00458593 addi a1,a1,4 -8001332c: fe65ae23 sw t1,-4(a1) -80013330: fee8d6e3 bge a7,a4,8001331c <__subtf3+0x6dc> -80013334: 00400713 li a4,4 -80013338: 41c70e33 sub t3,a4,t3 -8001333c: 00100713 li a4,1 -80013340: 09c05063 blez t3,800133c0 <__subtf3+0x780> -80013344: 000e0713 mv a4,t3 -80013348: 0780006f j 800133c0 <__subtf3+0x780> -8001334c: 00271813 slli a6,a4,0x2 -80013350: 010f0833 add a6,t5,a6 -80013354: 00082803 lw a6,0(a6) # 80000 <_start-0x7ff80000> -80013358: 00170713 addi a4,a4,1 -8001335c: 010fefb3 or t6,t6,a6 -80013360: f99ff06f j 800132f8 <__subtf3+0x6b8> -80013364: 02000713 li a4,32 -80013368: 02e36333 rem t1,t1,a4 -8001336c: 04010593 addi a1,sp,64 -80013370: 00289893 slli a7,a7,0x2 -80013374: 011588b3 add a7,a1,a7 -80013378: fd08a583 lw a1,-48(a7) # ffffd0 <_start-0x7f000030> -8001337c: 010f0833 add a6,t5,a6 -80013380: 00000293 li t0,0 -80013384: 40670733 sub a4,a4,t1 -80013388: 00e595b3 sll a1,a1,a4 -8001338c: 00bfefb3 or t6,t6,a1 -80013390: 00300593 li a1,3 -80013394: 41c585b3 sub a1,a1,t3 -80013398: 00480813 addi a6,a6,4 -8001339c: 02b2c663 blt t0,a1,800133c8 <__subtf3+0x788> -800133a0: 04010813 addi a6,sp,64 -800133a4: 00259593 slli a1,a1,0x2 -800133a8: 00b805b3 add a1,a6,a1 -800133ac: 01c12803 lw a6,28(sp) -800133b0: 00400713 li a4,4 -800133b4: 41c70733 sub a4,a4,t3 -800133b8: 00685333 srl t1,a6,t1 -800133bc: fc65a823 sw t1,-48(a1) -800133c0: 00300813 li a6,3 -800133c4: 03c0006f j 80013400 <__subtf3+0x7c0> -800133c8: ffc82883 lw a7,-4(a6) -800133cc: 00082403 lw s0,0(a6) -800133d0: 00229393 slli t2,t0,0x2 -800133d4: 0068d8b3 srl a7,a7,t1 -800133d8: 00e41433 sll s0,s0,a4 -800133dc: 007f03b3 add t2,t5,t2 -800133e0: 0088e8b3 or a7,a7,s0 -800133e4: 0113a023 sw a7,0(t2) -800133e8: 00128293 addi t0,t0,1 -800133ec: fadff06f j 80013398 <__subtf3+0x758> -800133f0: 00271593 slli a1,a4,0x2 -800133f4: 00bf05b3 add a1,t5,a1 -800133f8: 0005a023 sw zero,0(a1) -800133fc: 00170713 addi a4,a4,1 -80013400: fee858e3 bge a6,a4,800133f0 <__subtf3+0x7b0> -80013404: 01012583 lw a1,16(sp) -80013408: 01f03733 snez a4,t6 -8001340c: 00e5e733 or a4,a1,a4 -80013410: 00e12823 sw a4,16(sp) -80013414: 01012703 lw a4,16(sp) -80013418: 01412583 lw a1,20(sp) -8001341c: 000e8413 mv s0,t4 -80013420: 00e78733 add a4,a5,a4 -80013424: 00f737b3 sltu a5,a4,a5 -80013428: 00b685b3 add a1,a3,a1 -8001342c: 02e12823 sw a4,48(sp) -80013430: 00f58733 add a4,a1,a5 -80013434: 00f737b3 sltu a5,a4,a5 -80013438: 02e12a23 sw a4,52(sp) -8001343c: 01812703 lw a4,24(sp) -80013440: 00d5b6b3 sltu a3,a1,a3 -80013444: 00f6e6b3 or a3,a3,a5 -80013448: 00e60733 add a4,a2,a4 -8001344c: 00d707b3 add a5,a4,a3 -80013450: 00c73733 sltu a4,a4,a2 -80013454: 01c12603 lw a2,28(sp) -80013458: 00d7b6b3 sltu a3,a5,a3 -8001345c: 00d76733 or a4,a4,a3 -80013460: 00c50533 add a0,a0,a2 -80013464: 00a70533 add a0,a4,a0 -80013468: 02f12c23 sw a5,56(sp) -8001346c: 02a12e23 sw a0,60(sp) -80013470: ce5ff06f j 80013154 <__subtf3+0x514> -80013474: 00008fb7 lui t6,0x8 -80013478: 00140593 addi a1,s0,1 -8001347c: ffef8813 addi a6,t6,-2 # 7ffe <_start-0x7fff8002> -80013480: 0105f833 and a6,a1,a6 -80013484: 01412f03 lw t5,20(sp) -80013488: 01812e83 lw t4,24(sp) -8001348c: 01c12e03 lw t3,28(sp) -80013490: 03010893 addi a7,sp,48 -80013494: 03c10313 addi t1,sp,60 -80013498: 14081663 bnez a6,800135e4 <__subtf3+0x9a4> -8001349c: 01df6833 or a6,t5,t4 -800134a0: 01c86833 or a6,a6,t3 -800134a4: 00e86833 or a6,a6,a4 -800134a8: 0a041663 bnez s0,80013554 <__subtf3+0x914> -800134ac: 00081c63 bnez a6,800134c4 <__subtf3+0x884> -800134b0: 02f12823 sw a5,48(sp) -800134b4: 02d12a23 sw a3,52(sp) -800134b8: 02c12c23 sw a2,56(sp) -800134bc: 02a12e23 sw a0,60(sp) -800134c0: 9b1ff06f j 80012e70 <__subtf3+0x230> -800134c4: 00c6e5b3 or a1,a3,a2 -800134c8: 00a5e5b3 or a1,a1,a0 -800134cc: 00f5e5b3 or a1,a1,a5 -800134d0: 00059c63 bnez a1,800134e8 <__subtf3+0x8a8> -800134d4: 02e12823 sw a4,48(sp) -800134d8: 03e12a23 sw t5,52(sp) -800134dc: 03d12c23 sw t4,56(sp) -800134e0: 03c12e23 sw t3,60(sp) -800134e4: 98dff06f j 80012e70 <__subtf3+0x230> -800134e8: 00f707b3 add a5,a4,a5 -800134ec: 00e7b733 sltu a4,a5,a4 -800134f0: 00df05b3 add a1,t5,a3 -800134f4: 02f12823 sw a5,48(sp) -800134f8: 00e587b3 add a5,a1,a4 -800134fc: 01e5b6b3 sltu a3,a1,t5 -80013500: 00e7b733 sltu a4,a5,a4 -80013504: 00e6e733 or a4,a3,a4 -80013508: 00ce8633 add a2,t4,a2 -8001350c: 00e606b3 add a3,a2,a4 -80013510: 00e6b733 sltu a4,a3,a4 -80013514: 01d63633 sltu a2,a2,t4 -80013518: 00e66633 or a2,a2,a4 -8001351c: 00ae0533 add a0,t3,a0 -80013520: 00a60633 add a2,a2,a0 -80013524: 02f12a23 sw a5,52(sp) -80013528: 02d12c23 sw a3,56(sp) -8001352c: 00c61793 slli a5,a2,0xc -80013530: 0007c663 bltz a5,8001353c <__subtf3+0x8fc> -80013534: 02c12e23 sw a2,60(sp) -80013538: 939ff06f j 80012e70 <__subtf3+0x230> -8001353c: fff807b7 lui a5,0xfff80 -80013540: fff78793 addi a5,a5,-1 # fff7ffff <__BSS_END__+0x7ff693cf> -80013544: 00f67633 and a2,a2,a5 -80013548: 02c12e23 sw a2,60(sp) -8001354c: 00100413 li s0,1 -80013550: 921ff06f j 80012e70 <__subtf3+0x230> -80013554: 00081e63 bnez a6,80013570 <__subtf3+0x930> -80013558: 02f12823 sw a5,48(sp) -8001355c: 02d12a23 sw a3,52(sp) -80013560: 02c12c23 sw a2,56(sp) -80013564: 02a12e23 sw a0,60(sp) -80013568: ffff8413 addi s0,t6,-1 -8001356c: 905ff06f j 80012e70 <__subtf3+0x230> -80013570: 00c6e6b3 or a3,a3,a2 -80013574: 00a6e533 or a0,a3,a0 -80013578: 00f567b3 or a5,a0,a5 -8001357c: 00079c63 bnez a5,80013594 <__subtf3+0x954> -80013580: 02e12823 sw a4,48(sp) -80013584: 03e12a23 sw t5,52(sp) -80013588: 03d12c23 sw t4,56(sp) -8001358c: 03c12e23 sw t3,60(sp) -80013590: fd9ff06f j 80013568 <__subtf3+0x928> -80013594: 03f12e23 sw t6,60(sp) -80013598: 02012c23 sw zero,56(sp) -8001359c: 02012a23 sw zero,52(sp) -800135a0: 02012823 sw zero,48(sp) -800135a4: 00030713 mv a4,t1 -800135a8: 00072783 lw a5,0(a4) -800135ac: ffc72683 lw a3,-4(a4) -800135b0: ffc70713 addi a4,a4,-4 -800135b4: 00379793 slli a5,a5,0x3 -800135b8: 01d6d693 srli a3,a3,0x1d -800135bc: 00d7e7b3 or a5,a5,a3 -800135c0: 00f72223 sw a5,4(a4) -800135c4: fee892e3 bne a7,a4,800135a8 <__subtf3+0x968> -800135c8: 03012783 lw a5,48(sp) -800135cc: 00008437 lui s0,0x8 -800135d0: 00000913 li s2,0 -800135d4: 00379793 slli a5,a5,0x3 -800135d8: 02f12823 sw a5,48(sp) -800135dc: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> -800135e0: 891ff06f j 80012e70 <__subtf3+0x230> -800135e4: 00f707b3 add a5,a4,a5 -800135e8: 00e7b733 sltu a4,a5,a4 -800135ec: 00df06b3 add a3,t5,a3 -800135f0: 02f12823 sw a5,48(sp) -800135f4: 00e687b3 add a5,a3,a4 -800135f8: 00e7b733 sltu a4,a5,a4 -800135fc: 01e6b6b3 sltu a3,a3,t5 -80013600: 00e6e733 or a4,a3,a4 -80013604: 00ce86b3 add a3,t4,a2 -80013608: 02f12a23 sw a5,52(sp) -8001360c: 00e687b3 add a5,a3,a4 -80013610: 01d6b633 sltu a2,a3,t4 -80013614: 00e7b6b3 sltu a3,a5,a4 -80013618: 00d666b3 or a3,a2,a3 -8001361c: 00ae0533 add a0,t3,a0 -80013620: 00a68533 add a0,a3,a0 -80013624: 02f12c23 sw a5,56(sp) +80012f38: 0077f713 andi a4,a5,7 +80012f3c: 04070463 beqz a4,80012f84 <__subtf3+0x280> +80012f40: 00f7f713 andi a4,a5,15 +80012f44: 00400693 li a3,4 +80012f48: 02d70e63 beq a4,a3,80012f84 <__subtf3+0x280> +80012f4c: 03412703 lw a4,52(sp) +80012f50: 00478793 addi a5,a5,4 +80012f54: 02f12823 sw a5,48(sp) +80012f58: 0047b793 sltiu a5,a5,4 +80012f5c: 00e78733 add a4,a5,a4 +80012f60: 00f737b3 sltu a5,a4,a5 +80012f64: 02e12a23 sw a4,52(sp) +80012f68: 03812703 lw a4,56(sp) +80012f6c: 00e78733 add a4,a5,a4 +80012f70: 02e12c23 sw a4,56(sp) +80012f74: 00f73733 sltu a4,a4,a5 +80012f78: 03c12783 lw a5,60(sp) +80012f7c: 00f70733 add a4,a4,a5 +80012f80: 02e12e23 sw a4,60(sp) +80012f84: 03c12783 lw a5,60(sp) +80012f88: 00c79713 slli a4,a5,0xc +80012f8c: 02075463 bgez a4,80012fb4 <__subtf3+0x2b0> +80012f90: 00008737 lui a4,0x8 +80012f94: 00140413 addi s0,s0,1 +80012f98: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80012f9c: 00e41463 bne s0,a4,80012fa4 <__subtf3+0x2a0> +80012fa0: 2700106f j 80014210 <__subtf3+0x150c> +80012fa4: fff80737 lui a4,0xfff80 +80012fa8: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> +80012fac: 00e7f7b3 and a5,a5,a4 +80012fb0: 02f12e23 sw a5,60(sp) +80012fb4: 03010793 addi a5,sp,48 +80012fb8: 03c10613 addi a2,sp,60 +80012fbc: 0007a703 lw a4,0(a5) +80012fc0: 0047a683 lw a3,4(a5) +80012fc4: 00478793 addi a5,a5,4 +80012fc8: 00375713 srli a4,a4,0x3 +80012fcc: 01d69693 slli a3,a3,0x1d +80012fd0: 00d76733 or a4,a4,a3 +80012fd4: fee7ae23 sw a4,-4(a5) +80012fd8: fef612e3 bne a2,a5,80012fbc <__subtf3+0x2b8> +80012fdc: 03c12783 lw a5,60(sp) +80012fe0: 000086b7 lui a3,0x8 +80012fe4: 0037d713 srli a4,a5,0x3 +80012fe8: 02e12e23 sw a4,60(sp) +80012fec: fff68793 addi a5,a3,-1 # 7fff <_start-0x7fff8001> +80012ff0: 02f41a63 bne s0,a5,80013024 <__subtf3+0x320> +80012ff4: 03412603 lw a2,52(sp) +80012ff8: 03012783 lw a5,48(sp) +80012ffc: 00c7e7b3 or a5,a5,a2 +80013000: 03812603 lw a2,56(sp) +80013004: 00c7e7b3 or a5,a5,a2 +80013008: 00e7e7b3 or a5,a5,a4 +8001300c: 00078c63 beqz a5,80013024 <__subtf3+0x320> +80013010: 02d12e23 sw a3,60(sp) +80013014: 02012c23 sw zero,56(sp) +80013018: 02012a23 sw zero,52(sp) +8001301c: 02012823 sw zero,48(sp) +80013020: 00000913 li s2,0 +80013024: 03c12783 lw a5,60(sp) +80013028: 01141413 slli s0,s0,0x11 +8001302c: 01145413 srli s0,s0,0x11 +80013030: 00f11623 sh a5,12(sp) +80013034: 03012783 lw a5,48(sp) +80013038: 00f91913 slli s2,s2,0xf +8001303c: 00896933 or s2,s2,s0 +80013040: 00f4a023 sw a5,0(s1) # 80000 <_start-0x7ff80000> +80013044: 03412783 lw a5,52(sp) +80013048: 01211723 sh s2,14(sp) +8001304c: 05c12083 lw ra,92(sp) +80013050: 00f4a223 sw a5,4(s1) +80013054: 03812783 lw a5,56(sp) +80013058: 05812403 lw s0,88(sp) +8001305c: 05012903 lw s2,80(sp) +80013060: 00f4a423 sw a5,8(s1) +80013064: 00c12783 lw a5,12(sp) +80013068: 04c12983 lw s3,76(sp) +8001306c: 04812a03 lw s4,72(sp) +80013070: 00f4a623 sw a5,12(s1) +80013074: 04412a83 lw s5,68(sp) +80013078: 04012b03 lw s6,64(sp) +8001307c: 00048513 mv a0,s1 +80013080: 05412483 lw s1,84(sp) +80013084: 06010113 addi sp,sp,96 +80013088: 00008067 ret +8001308c: 02c12783 lw a5,44(sp) +80013090: 00080637 lui a2,0x80 +80013094: 00c7e7b3 or a5,a5,a2 +80013098: 02f12623 sw a5,44(sp) +8001309c: 07400793 li a5,116 +800130a0: e667c2e3 blt a5,t1,80012f04 <__subtf3+0x200> +800130a4: 00030593 mv a1,t1 +800130a8: 4055de93 srai t4,a1,0x5 +800130ac: 00000793 li a5,0 +800130b0: 00000613 li a2,0 +800130b4: 05d61663 bne a2,t4,80013100 <__subtf3+0x3fc> +800130b8: 01f5f593 andi a1,a1,31 +800130bc: 002e9313 slli t1,t4,0x2 +800130c0: 04059c63 bnez a1,80013118 <__subtf3+0x414> +800130c4: 00300593 li a1,3 +800130c8: 00000613 li a2,0 +800130cc: 41d585b3 sub a1,a1,t4 +800130d0: 00668533 add a0,a3,t1 +800130d4: 00052503 lw a0,0(a0) +800130d8: 00160613 addi a2,a2,1 # 80001 <_start-0x7ff7ffff> +800130dc: 00468693 addi a3,a3,4 +800130e0: fea6ae23 sw a0,-4(a3) +800130e4: fec5d6e3 bge a1,a2,800130d0 <__subtf3+0x3cc> +800130e8: 00400613 li a2,4 +800130ec: 41d60eb3 sub t4,a2,t4 +800130f0: 00100613 li a2,1 +800130f4: 07d05c63 blez t4,8001316c <__subtf3+0x468> +800130f8: 000e8613 mv a2,t4 +800130fc: 0700006f j 8001316c <__subtf3+0x468> +80013100: 00261513 slli a0,a2,0x2 +80013104: 00a80533 add a0,a6,a0 +80013108: 00052503 lw a0,0(a0) +8001310c: 00160613 addi a2,a2,1 +80013110: 00a7e7b3 or a5,a5,a0 +80013114: fa1ff06f j 800130b4 <__subtf3+0x3b0> +80013118: 04010693 addi a3,sp,64 +8001311c: 006686b3 add a3,a3,t1 +80013120: fe06a683 lw a3,-32(a3) +80013124: 02000f93 li t6,32 +80013128: 40bf8fb3 sub t6,t6,a1 +8001312c: 01f696b3 sll a3,a3,t6 +80013130: 00300513 li a0,3 +80013134: 00d7e7b3 or a5,a5,a3 +80013138: 00680333 add t1,a6,t1 +8001313c: 00000613 li a2,0 +80013140: 41d50533 sub a0,a0,t4 +80013144: 00430313 addi t1,t1,4 +80013148: 02a64663 blt a2,a0,80013174 <__subtf3+0x470> +8001314c: 04010693 addi a3,sp,64 +80013150: 00251513 slli a0,a0,0x2 +80013154: 00a68533 add a0,a3,a0 +80013158: 02c12683 lw a3,44(sp) +8001315c: 00400613 li a2,4 +80013160: 41d60633 sub a2,a2,t4 +80013164: 00b6d5b3 srl a1,a3,a1 +80013168: feb52023 sw a1,-32(a0) +8001316c: 00400593 li a1,4 +80013170: 03c0006f j 800131ac <__subtf3+0x4a8> +80013174: ffc32683 lw a3,-4(t1) +80013178: 00032383 lw t2,0(t1) +8001317c: 00261293 slli t0,a2,0x2 +80013180: 00b6d6b3 srl a3,a3,a1 +80013184: 01f393b3 sll t2,t2,t6 +80013188: 005802b3 add t0,a6,t0 +8001318c: 0076e6b3 or a3,a3,t2 +80013190: 00d2a023 sw a3,0(t0) +80013194: 00160613 addi a2,a2,1 +80013198: fadff06f j 80013144 <__subtf3+0x440> +8001319c: 00261693 slli a3,a2,0x2 +800131a0: 00d806b3 add a3,a6,a3 +800131a4: 0006a023 sw zero,0(a3) +800131a8: 00160613 addi a2,a2,1 +800131ac: feb618e3 bne a2,a1,8001319c <__subtf3+0x498> +800131b0: 02012683 lw a3,32(sp) +800131b4: 00f037b3 snez a5,a5 +800131b8: 00f6e7b3 or a5,a3,a5 +800131bc: 02f12023 sw a5,32(sp) +800131c0: 02012583 lw a1,32(sp) +800131c4: 02412603 lw a2,36(sp) +800131c8: 00b705b3 add a1,a4,a1 +800131cc: 00e5b733 sltu a4,a1,a4 +800131d0: 00cf0633 add a2,t5,a2 +800131d4: 00e606b3 add a3,a2,a4 +800131d8: 02b12823 sw a1,48(sp) +800131dc: 01e635b3 sltu a1,a2,t5 +800131e0: 02812603 lw a2,40(sp) +800131e4: 00e6b733 sltu a4,a3,a4 +800131e8: 00e5e5b3 or a1,a1,a4 +800131ec: 02d12a23 sw a3,52(sp) +800131f0: 00ce06b3 add a3,t3,a2 +800131f4: 00b687b3 add a5,a3,a1 +800131f8: 00b7b5b3 sltu a1,a5,a1 +800131fc: 02f12c23 sw a5,56(sp) +80013200: 02c12783 lw a5,44(sp) +80013204: 01c6b6b3 sltu a3,a3,t3 +80013208: 00b6e6b3 or a3,a3,a1 +8001320c: 00f888b3 add a7,a7,a5 +80013210: 011686b3 add a3,a3,a7 +80013214: 02d12e23 sw a3,60(sp) +80013218: 03c12783 lw a5,60(sp) +8001321c: 00c79713 slli a4,a5,0xc +80013220: d0075ae3 bgez a4,80012f34 <__subtf3+0x230> +80013224: fff80737 lui a4,0xfff80 +80013228: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> +8001322c: 00e7f7b3 and a5,a5,a4 +80013230: 02f12e23 sw a5,60(sp) +80013234: 03012783 lw a5,48(sp) +80013238: 00140413 addi s0,s0,1 +8001323c: 03c10593 addi a1,sp,60 +80013240: 01f79713 slli a4,a5,0x1f +80013244: 03010793 addi a5,sp,48 +80013248: 0007a683 lw a3,0(a5) +8001324c: 0047a603 lw a2,4(a5) +80013250: 00478793 addi a5,a5,4 +80013254: 0016d693 srli a3,a3,0x1 +80013258: 01f61613 slli a2,a2,0x1f +8001325c: 00c6e6b3 or a3,a3,a2 +80013260: fed7ae23 sw a3,-4(a5) +80013264: fef592e3 bne a1,a5,80013248 <__subtf3+0x544> +80013268: 03c12783 lw a5,60(sp) +8001326c: 0017d793 srli a5,a5,0x1 +80013270: 02f12e23 sw a5,60(sp) +80013274: 00e037b3 snez a5,a4 +80013278: 03012703 lw a4,48(sp) +8001327c: 00f767b3 or a5,a4,a5 +80013280: 02f12823 sw a5,48(sp) +80013284: 000087b7 lui a5,0x8 +80013288: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +8001328c: caf414e3 bne s0,a5,80012f34 <__subtf3+0x230> +80013290: 02012e23 sw zero,60(sp) +80013294: 02012c23 sw zero,56(sp) +80013298: 02012a23 sw zero,52(sp) +8001329c: 02012823 sw zero,48(sp) +800132a0: c95ff06f j 80012f34 <__subtf3+0x230> +800132a4: 02412683 lw a3,36(sp) +800132a8: 02812603 lw a2,40(sp) +800132ac: 02c12503 lw a0,44(sp) +800132b0: 28030463 beqz t1,80013538 <__subtf3+0x834> +800132b4: 408e8e33 sub t3,t4,s0 +800132b8: 0a041a63 bnez s0,8001336c <__subtf3+0x668> +800132bc: 01412883 lw a7,20(sp) +800132c0: 01812803 lw a6,24(sp) +800132c4: 01c12f83 lw t6,28(sp) +800132c8: 0108e333 or t1,a7,a6 +800132cc: 01f36333 or t1,t1,t6 +800132d0: 00e36333 or t1,t1,a4 +800132d4: 00031e63 bnez t1,800132f0 <__subtf3+0x5ec> +800132d8: 02f12823 sw a5,48(sp) +800132dc: 02d12a23 sw a3,52(sp) +800132e0: 02c12c23 sw a2,56(sp) +800132e4: 02a12e23 sw a0,60(sp) +800132e8: 000e0413 mv s0,t3 +800132ec: c49ff06f j 80012f34 <__subtf3+0x230> +800132f0: fffe0313 addi t1,t3,-1 +800132f4: 04031863 bnez t1,80013344 <__subtf3+0x640> +800132f8: 00f70733 add a4,a4,a5 +800132fc: 00f737b3 sltu a5,a4,a5 +80013300: 00d885b3 add a1,a7,a3 +80013304: 02e12823 sw a4,48(sp) +80013308: 00f58733 add a4,a1,a5 +8001330c: 00f737b3 sltu a5,a4,a5 +80013310: 00d5b6b3 sltu a3,a1,a3 +80013314: 00f6e6b3 or a3,a3,a5 +80013318: 02e12a23 sw a4,52(sp) +8001331c: 00c80733 add a4,a6,a2 +80013320: 00d707b3 add a5,a4,a3 +80013324: 00d7b6b3 sltu a3,a5,a3 +80013328: 00c73733 sltu a4,a4,a2 +8001332c: 00d76733 or a4,a4,a3 +80013330: 00af8533 add a0,t6,a0 +80013334: 00a70533 add a0,a4,a0 +80013338: 02f12c23 sw a5,56(sp) +8001333c: 02a12e23 sw a0,60(sp) +80013340: ba9ff06f j 80012ee8 <__subtf3+0x1e4> +80013344: 00008737 lui a4,0x8 +80013348: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +8001334c: f8ee06e3 beq t3,a4,800132d8 <__subtf3+0x5d4> +80013350: 07400713 li a4,116 +80013354: 04675c63 bge a4,t1,800133ac <__subtf3+0x6a8> +80013358: 00012e23 sw zero,28(sp) +8001335c: 00012c23 sw zero,24(sp) +80013360: 00012a23 sw zero,20(sp) +80013364: 00100713 li a4,1 +80013368: 16c0006f j 800134d4 <__subtf3+0x7d0> +8001336c: 00008737 lui a4,0x8 +80013370: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80013374: 00ee9e63 bne t4,a4,80013390 <__subtf3+0x68c> +80013378: 02f12823 sw a5,48(sp) +8001337c: 02d12a23 sw a3,52(sp) +80013380: 02c12c23 sw a2,56(sp) +80013384: 02a12e23 sw a0,60(sp) +80013388: 000e8413 mv s0,t4 +8001338c: ba9ff06f j 80012f34 <__subtf3+0x230> +80013390: 01c12703 lw a4,28(sp) +80013394: 00080837 lui a6,0x80 +80013398: 01076733 or a4,a4,a6 +8001339c: 00e12e23 sw a4,28(sp) +800133a0: 07400713 li a4,116 +800133a4: fbc74ae3 blt a4,t3,80013358 <__subtf3+0x654> +800133a8: 000e0313 mv t1,t3 +800133ac: 02000713 li a4,32 +800133b0: 02e34e33 div t3,t1,a4 +800133b4: 00000f93 li t6,0 +800133b8: 00000713 li a4,0 +800133bc: 05c74a63 blt a4,t3,80013410 <__subtf3+0x70c> +800133c0: 000e0893 mv a7,t3 +800133c4: 000e5463 bgez t3,800133cc <__subtf3+0x6c8> +800133c8: 00000893 li a7,0 +800133cc: 01f37713 andi a4,t1,31 +800133d0: 002e1813 slli a6,t3,0x2 +800133d4: 04071a63 bnez a4,80013428 <__subtf3+0x724> +800133d8: 00300893 li a7,3 +800133dc: 41c888b3 sub a7,a7,t3 +800133e0: 01058333 add t1,a1,a6 +800133e4: 00032303 lw t1,0(t1) +800133e8: 00170713 addi a4,a4,1 +800133ec: 00458593 addi a1,a1,4 +800133f0: fe65ae23 sw t1,-4(a1) +800133f4: fee8d6e3 bge a7,a4,800133e0 <__subtf3+0x6dc> +800133f8: 00400713 li a4,4 +800133fc: 41c70e33 sub t3,a4,t3 +80013400: 00100713 li a4,1 +80013404: 09c05063 blez t3,80013484 <__subtf3+0x780> +80013408: 000e0713 mv a4,t3 +8001340c: 0780006f j 80013484 <__subtf3+0x780> +80013410: 00271813 slli a6,a4,0x2 +80013414: 010f0833 add a6,t5,a6 +80013418: 00082803 lw a6,0(a6) # 80000 <_start-0x7ff80000> +8001341c: 00170713 addi a4,a4,1 +80013420: 010fefb3 or t6,t6,a6 +80013424: f99ff06f j 800133bc <__subtf3+0x6b8> +80013428: 02000713 li a4,32 +8001342c: 02e36333 rem t1,t1,a4 +80013430: 04010593 addi a1,sp,64 +80013434: 00289893 slli a7,a7,0x2 +80013438: 011588b3 add a7,a1,a7 +8001343c: fd08a583 lw a1,-48(a7) # ffffd0 <_start-0x7f000030> +80013440: 010f0833 add a6,t5,a6 +80013444: 00000293 li t0,0 +80013448: 40670733 sub a4,a4,t1 +8001344c: 00e595b3 sll a1,a1,a4 +80013450: 00bfefb3 or t6,t6,a1 +80013454: 00300593 li a1,3 +80013458: 41c585b3 sub a1,a1,t3 +8001345c: 00480813 addi a6,a6,4 +80013460: 02b2c663 blt t0,a1,8001348c <__subtf3+0x788> +80013464: 04010813 addi a6,sp,64 +80013468: 00259593 slli a1,a1,0x2 +8001346c: 00b805b3 add a1,a6,a1 +80013470: 01c12803 lw a6,28(sp) +80013474: 00400713 li a4,4 +80013478: 41c70733 sub a4,a4,t3 +8001347c: 00685333 srl t1,a6,t1 +80013480: fc65a823 sw t1,-48(a1) +80013484: 00300813 li a6,3 +80013488: 03c0006f j 800134c4 <__subtf3+0x7c0> +8001348c: ffc82883 lw a7,-4(a6) +80013490: 00082403 lw s0,0(a6) +80013494: 00229393 slli t2,t0,0x2 +80013498: 0068d8b3 srl a7,a7,t1 +8001349c: 00e41433 sll s0,s0,a4 +800134a0: 007f03b3 add t2,t5,t2 +800134a4: 0088e8b3 or a7,a7,s0 +800134a8: 0113a023 sw a7,0(t2) +800134ac: 00128293 addi t0,t0,1 +800134b0: fadff06f j 8001345c <__subtf3+0x758> +800134b4: 00271593 slli a1,a4,0x2 +800134b8: 00bf05b3 add a1,t5,a1 +800134bc: 0005a023 sw zero,0(a1) +800134c0: 00170713 addi a4,a4,1 +800134c4: fee858e3 bge a6,a4,800134b4 <__subtf3+0x7b0> +800134c8: 01012583 lw a1,16(sp) +800134cc: 01f03733 snez a4,t6 +800134d0: 00e5e733 or a4,a1,a4 +800134d4: 00e12823 sw a4,16(sp) +800134d8: 01012703 lw a4,16(sp) +800134dc: 01412583 lw a1,20(sp) +800134e0: 000e8413 mv s0,t4 +800134e4: 00e78733 add a4,a5,a4 +800134e8: 00f737b3 sltu a5,a4,a5 +800134ec: 00b685b3 add a1,a3,a1 +800134f0: 02e12823 sw a4,48(sp) +800134f4: 00f58733 add a4,a1,a5 +800134f8: 00f737b3 sltu a5,a4,a5 +800134fc: 02e12a23 sw a4,52(sp) +80013500: 01812703 lw a4,24(sp) +80013504: 00d5b6b3 sltu a3,a1,a3 +80013508: 00f6e6b3 or a3,a3,a5 +8001350c: 00e60733 add a4,a2,a4 +80013510: 00d707b3 add a5,a4,a3 +80013514: 00c73733 sltu a4,a4,a2 +80013518: 01c12603 lw a2,28(sp) +8001351c: 00d7b6b3 sltu a3,a5,a3 +80013520: 00d76733 or a4,a4,a3 +80013524: 00c50533 add a0,a0,a2 +80013528: 00a70533 add a0,a4,a0 +8001352c: 02f12c23 sw a5,56(sp) +80013530: 02a12e23 sw a0,60(sp) +80013534: ce5ff06f j 80013218 <__subtf3+0x514> +80013538: 00008fb7 lui t6,0x8 +8001353c: 00140593 addi a1,s0,1 +80013540: ffef8813 addi a6,t6,-2 # 7ffe <_start-0x7fff8002> +80013544: 0105f833 and a6,a1,a6 +80013548: 01412f03 lw t5,20(sp) +8001354c: 01812e83 lw t4,24(sp) +80013550: 01c12e03 lw t3,28(sp) +80013554: 03010893 addi a7,sp,48 +80013558: 03c10313 addi t1,sp,60 +8001355c: 14081663 bnez a6,800136a8 <__subtf3+0x9a4> +80013560: 01df6833 or a6,t5,t4 +80013564: 01c86833 or a6,a6,t3 +80013568: 00e86833 or a6,a6,a4 +8001356c: 0a041663 bnez s0,80013618 <__subtf3+0x914> +80013570: 00081c63 bnez a6,80013588 <__subtf3+0x884> +80013574: 02f12823 sw a5,48(sp) +80013578: 02d12a23 sw a3,52(sp) +8001357c: 02c12c23 sw a2,56(sp) +80013580: 02a12e23 sw a0,60(sp) +80013584: 9b1ff06f j 80012f34 <__subtf3+0x230> +80013588: 00c6e5b3 or a1,a3,a2 +8001358c: 00a5e5b3 or a1,a1,a0 +80013590: 00f5e5b3 or a1,a1,a5 +80013594: 00059c63 bnez a1,800135ac <__subtf3+0x8a8> +80013598: 02e12823 sw a4,48(sp) +8001359c: 03e12a23 sw t5,52(sp) +800135a0: 03d12c23 sw t4,56(sp) +800135a4: 03c12e23 sw t3,60(sp) +800135a8: 98dff06f j 80012f34 <__subtf3+0x230> +800135ac: 00f707b3 add a5,a4,a5 +800135b0: 00e7b733 sltu a4,a5,a4 +800135b4: 00df05b3 add a1,t5,a3 +800135b8: 02f12823 sw a5,48(sp) +800135bc: 00e587b3 add a5,a1,a4 +800135c0: 01e5b6b3 sltu a3,a1,t5 +800135c4: 00e7b733 sltu a4,a5,a4 +800135c8: 00e6e733 or a4,a3,a4 +800135cc: 00ce8633 add a2,t4,a2 +800135d0: 00e606b3 add a3,a2,a4 +800135d4: 00e6b733 sltu a4,a3,a4 +800135d8: 01d63633 sltu a2,a2,t4 +800135dc: 00e66633 or a2,a2,a4 +800135e0: 00ae0533 add a0,t3,a0 +800135e4: 00a60633 add a2,a2,a0 +800135e8: 02f12a23 sw a5,52(sp) +800135ec: 02d12c23 sw a3,56(sp) +800135f0: 00c61793 slli a5,a2,0xc +800135f4: 0007c663 bltz a5,80013600 <__subtf3+0x8fc> +800135f8: 02c12e23 sw a2,60(sp) +800135fc: 939ff06f j 80012f34 <__subtf3+0x230> +80013600: fff807b7 lui a5,0xfff80 +80013604: fff78793 addi a5,a5,-1 # fff7ffff <__BSS_END__+0x7ff693c3> +80013608: 00f67633 and a2,a2,a5 +8001360c: 02c12e23 sw a2,60(sp) +80013610: 00100413 li s0,1 +80013614: 921ff06f j 80012f34 <__subtf3+0x230> +80013618: 00081e63 bnez a6,80013634 <__subtf3+0x930> +8001361c: 02f12823 sw a5,48(sp) +80013620: 02d12a23 sw a3,52(sp) +80013624: 02c12c23 sw a2,56(sp) 80013628: 02a12e23 sw a0,60(sp) -8001362c: 00088793 mv a5,a7 -80013630: 0007a703 lw a4,0(a5) -80013634: 0047a683 lw a3,4(a5) -80013638: 00478793 addi a5,a5,4 -8001363c: 00175713 srli a4,a4,0x1 -80013640: 01f69693 slli a3,a3,0x1f -80013644: 00d76733 or a4,a4,a3 -80013648: fee7ae23 sw a4,-4(a5) -8001364c: fef312e3 bne t1,a5,80013630 <__subtf3+0x9f0> -80013650: 000087b7 lui a5,0x8 -80013654: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80013658: 00f58c63 beq a1,a5,80013670 <__subtf3+0xa30> -8001365c: 03c12783 lw a5,60(sp) -80013660: 0017d793 srli a5,a5,0x1 -80013664: 02f12e23 sw a5,60(sp) -80013668: 00058413 mv s0,a1 -8001366c: 805ff06f j 80012e70 <__subtf3+0x230> -80013670: 02012e23 sw zero,60(sp) -80013674: 02012c23 sw zero,56(sp) -80013678: 02012a23 sw zero,52(sp) -8001367c: 02012823 sw zero,48(sp) -80013680: fe9ff06f j 80013668 <__subtf3+0xa28> -80013684: 2a605e63 blez t1,80013940 <__subtf3+0xd00> -80013688: 01412883 lw a7,20(sp) -8001368c: 01812e03 lw t3,24(sp) -80013690: 01c12f03 lw t5,28(sp) -80013694: 0c0e9463 bnez t4,8001375c <__subtf3+0xb1c> -80013698: 02412e83 lw t4,36(sp) -8001369c: 02812503 lw a0,40(sp) -800136a0: 02c12583 lw a1,44(sp) -800136a4: 00aee633 or a2,t4,a0 -800136a8: 00b66633 or a2,a2,a1 -800136ac: 00f66633 or a2,a2,a5 -800136b0: 00061c63 bnez a2,800136c8 <__subtf3+0xa88> -800136b4: 02e12823 sw a4,48(sp) -800136b8: 03112a23 sw a7,52(sp) -800136bc: 03c12c23 sw t3,56(sp) -800136c0: 03e12e23 sw t5,60(sp) -800136c4: f08ff06f j 80012dcc <__subtf3+0x18c> -800136c8: fff30613 addi a2,t1,-1 -800136cc: 06061463 bnez a2,80013734 <__subtf3+0xaf4> -800136d0: 40f707b3 sub a5,a4,a5 -800136d4: 41d886b3 sub a3,a7,t4 -800136d8: 00f73833 sltu a6,a4,a5 -800136dc: 00d8b333 sltu t1,a7,a3 -800136e0: 41068833 sub a6,a3,a6 -800136e4: 00000693 li a3,0 -800136e8: 00f77663 bgeu a4,a5,800136f4 <__subtf3+0xab4> -800136ec: 411e88b3 sub a7,t4,a7 -800136f0: 0018b693 seqz a3,a7 -800136f4: 0066e8b3 or a7,a3,t1 -800136f8: 40ae0733 sub a4,t3,a0 -800136fc: 00ee36b3 sltu a3,t3,a4 -80013700: 41170733 sub a4,a4,a7 -80013704: 00088663 beqz a7,80013710 <__subtf3+0xad0> -80013708: 41c50e33 sub t3,a0,t3 -8001370c: 001e3613 seqz a2,t3 -80013710: 40bf05b3 sub a1,t5,a1 -80013714: 00d66633 or a2,a2,a3 -80013718: 40c585b3 sub a1,a1,a2 -8001371c: 02b12e23 sw a1,60(sp) -80013720: 02e12c23 sw a4,56(sp) -80013724: 03012a23 sw a6,52(sp) -80013728: 02f12823 sw a5,48(sp) -8001372c: 00100413 li s0,1 -80013730: 1f00006f j 80013920 <__subtf3+0xce0> -80013734: 000087b7 lui a5,0x8 -80013738: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -8001373c: f6f30ce3 beq t1,a5,800136b4 <__subtf3+0xa74> -80013740: 07400793 li a5,116 -80013744: 04c7da63 bge a5,a2,80013798 <__subtf3+0xb58> -80013748: 02012623 sw zero,44(sp) -8001374c: 02012423 sw zero,40(sp) -80013750: 02012223 sw zero,36(sp) -80013754: 00100793 li a5,1 -80013758: 1540006f j 800138ac <__subtf3+0xc6c> -8001375c: 000087b7 lui a5,0x8 -80013760: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80013764: 00f41c63 bne s0,a5,8001377c <__subtf3+0xb3c> -80013768: 02e12823 sw a4,48(sp) -8001376c: 03112a23 sw a7,52(sp) -80013770: 03c12c23 sw t3,56(sp) -80013774: 03e12e23 sw t5,60(sp) -80013778: ef8ff06f j 80012e70 <__subtf3+0x230> -8001377c: 02c12783 lw a5,44(sp) -80013780: 00080637 lui a2,0x80 -80013784: 00c7e7b3 or a5,a5,a2 -80013788: 02f12623 sw a5,44(sp) -8001378c: 07400793 li a5,116 -80013790: fa67cce3 blt a5,t1,80013748 <__subtf3+0xb08> -80013794: 00030613 mv a2,t1 -80013798: 40565513 srai a0,a2,0x5 -8001379c: 00000313 li t1,0 -800137a0: 00000793 li a5,0 -800137a4: 04a79663 bne a5,a0,800137f0 <__subtf3+0xbb0> -800137a8: 01f67593 andi a1,a2,31 -800137ac: 00251613 slli a2,a0,0x2 -800137b0: 04059c63 bnez a1,80013808 <__subtf3+0xbc8> -800137b4: 00300593 li a1,3 -800137b8: 00000793 li a5,0 -800137bc: 40a585b3 sub a1,a1,a0 -800137c0: 00c68eb3 add t4,a3,a2 -800137c4: 000eae83 lw t4,0(t4) -800137c8: 00178793 addi a5,a5,1 -800137cc: 00468693 addi a3,a3,4 -800137d0: ffd6ae23 sw t4,-4(a3) -800137d4: fef5d6e3 bge a1,a5,800137c0 <__subtf3+0xb80> -800137d8: 00400793 li a5,4 -800137dc: 40a78533 sub a0,a5,a0 -800137e0: 00100793 li a5,1 -800137e4: 06a05c63 blez a0,8001385c <__subtf3+0xc1c> -800137e8: 00050793 mv a5,a0 -800137ec: 0700006f j 8001385c <__subtf3+0xc1c> -800137f0: 00279593 slli a1,a5,0x2 -800137f4: 00b805b3 add a1,a6,a1 -800137f8: 0005a583 lw a1,0(a1) -800137fc: 00178793 addi a5,a5,1 -80013800: 00b36333 or t1,t1,a1 -80013804: fa1ff06f j 800137a4 <__subtf3+0xb64> -80013808: 04010793 addi a5,sp,64 -8001380c: 00c787b3 add a5,a5,a2 -80013810: fe07a783 lw a5,-32(a5) -80013814: 02000f93 li t6,32 -80013818: 40bf8fb3 sub t6,t6,a1 -8001381c: 01f797b3 sll a5,a5,t6 -80013820: 00300693 li a3,3 -80013824: 00f36333 or t1,t1,a5 -80013828: 00c80633 add a2,a6,a2 -8001382c: 00000e93 li t4,0 -80013830: 40a686b3 sub a3,a3,a0 -80013834: 00460613 addi a2,a2,4 # 80004 <_start-0x7ff7fffc> -80013838: 02dec663 blt t4,a3,80013864 <__subtf3+0xc24> -8001383c: 04010613 addi a2,sp,64 -80013840: 00269693 slli a3,a3,0x2 -80013844: 00d606b3 add a3,a2,a3 -80013848: 02c12603 lw a2,44(sp) -8001384c: 00400793 li a5,4 -80013850: 40a787b3 sub a5,a5,a0 -80013854: 00b65633 srl a2,a2,a1 -80013858: fec6a023 sw a2,-32(a3) -8001385c: 00400613 li a2,4 -80013860: 03c0006f j 8001389c <__subtf3+0xc5c> -80013864: ffc62783 lw a5,-4(a2) -80013868: 00062383 lw t2,0(a2) -8001386c: 002e9293 slli t0,t4,0x2 -80013870: 00b7d7b3 srl a5,a5,a1 -80013874: 01f393b3 sll t2,t2,t6 -80013878: 005802b3 add t0,a6,t0 -8001387c: 0077e7b3 or a5,a5,t2 -80013880: 00f2a023 sw a5,0(t0) -80013884: 001e8e93 addi t4,t4,1 -80013888: fadff06f j 80013834 <__subtf3+0xbf4> -8001388c: 00279693 slli a3,a5,0x2 -80013890: 00d806b3 add a3,a6,a3 -80013894: 0006a023 sw zero,0(a3) -80013898: 00178793 addi a5,a5,1 -8001389c: fec798e3 bne a5,a2,8001388c <__subtf3+0xc4c> -800138a0: 02012683 lw a3,32(sp) -800138a4: 006037b3 snez a5,t1 -800138a8: 00f6e7b3 or a5,a3,a5 -800138ac: 02f12023 sw a5,32(sp) -800138b0: 02012783 lw a5,32(sp) -800138b4: 02412583 lw a1,36(sp) -800138b8: 40f707b3 sub a5,a4,a5 -800138bc: 40b88633 sub a2,a7,a1 -800138c0: 00f736b3 sltu a3,a4,a5 -800138c4: 00c8b533 sltu a0,a7,a2 -800138c8: 40d60633 sub a2,a2,a3 -800138cc: 00000693 li a3,0 -800138d0: 00f77663 bgeu a4,a5,800138dc <__subtf3+0xc9c> -800138d4: 411588b3 sub a7,a1,a7 -800138d8: 0018b693 seqz a3,a7 -800138dc: 00a6e8b3 or a7,a3,a0 -800138e0: 02812503 lw a0,40(sp) -800138e4: 00000693 li a3,0 -800138e8: 40ae0733 sub a4,t3,a0 -800138ec: 00ee3833 sltu a6,t3,a4 -800138f0: 41170733 sub a4,a4,a7 -800138f4: 00088663 beqz a7,80013900 <__subtf3+0xcc0> -800138f8: 41c50e33 sub t3,a0,t3 -800138fc: 001e3693 seqz a3,t3 -80013900: 02c12583 lw a1,44(sp) -80013904: 0106e6b3 or a3,a3,a6 -80013908: 02e12c23 sw a4,56(sp) -8001390c: 40bf05b3 sub a1,t5,a1 -80013910: 40d585b3 sub a1,a1,a3 -80013914: 02b12e23 sw a1,60(sp) -80013918: 02c12a23 sw a2,52(sp) -8001391c: 02f12823 sw a5,48(sp) -80013920: 03c12783 lw a5,60(sp) -80013924: 00c79713 slli a4,a5,0xc -80013928: d4075463 bgez a4,80012e70 <__subtf3+0x230> -8001392c: 00080737 lui a4,0x80 -80013930: fff70713 addi a4,a4,-1 # 7ffff <_start-0x7ff80001> -80013934: 00e7f7b3 and a5,a5,a4 -80013938: 02f12e23 sw a5,60(sp) -8001393c: 5800006f j 80013ebc <__subtf3+0x127c> -80013940: 02412803 lw a6,36(sp) -80013944: 02812883 lw a7,40(sp) -80013948: 02c12683 lw a3,44(sp) -8001394c: 2c030263 beqz t1,80013c10 <__subtf3+0xfd0> -80013950: 408e8333 sub t1,t4,s0 -80013954: 0c041263 bnez s0,80013a18 <__subtf3+0xdd8> -80013958: 01412283 lw t0,20(sp) -8001395c: 01812f83 lw t6,24(sp) -80013960: 01c12503 lw a0,28(sp) -80013964: 01f2e633 or a2,t0,t6 -80013968: 00a66633 or a2,a2,a0 -8001396c: 00e66633 or a2,a2,a4 -80013970: 02061063 bnez a2,80013990 <__subtf3+0xd50> -80013974: 02f12823 sw a5,48(sp) -80013978: 03012a23 sw a6,52(sp) -8001397c: 03112c23 sw a7,56(sp) -80013980: 02d12e23 sw a3,60(sp) -80013984: 00030413 mv s0,t1 -80013988: 000e0913 mv s2,t3 -8001398c: ce4ff06f j 80012e70 <__subtf3+0x230> -80013990: fff30613 addi a2,t1,-1 -80013994: 06061463 bnez a2,800139fc <__subtf3+0xdbc> -80013998: 40e78733 sub a4,a5,a4 -8001399c: 405805b3 sub a1,a6,t0 -800139a0: 00e7b333 sltu t1,a5,a4 -800139a4: 00b83eb3 sltu t4,a6,a1 -800139a8: 40658333 sub t1,a1,t1 -800139ac: 00000593 li a1,0 -800139b0: 00e7f663 bgeu a5,a4,800139bc <__subtf3+0xd7c> -800139b4: 41028833 sub a6,t0,a6 -800139b8: 00183593 seqz a1,a6 -800139bc: 01d5e833 or a6,a1,t4 -800139c0: 41f885b3 sub a1,a7,t6 -800139c4: 00b8b7b3 sltu a5,a7,a1 -800139c8: 410585b3 sub a1,a1,a6 -800139cc: 00080663 beqz a6,800139d8 <__subtf3+0xd98> -800139d0: 411f88b3 sub a7,t6,a7 -800139d4: 0018b613 seqz a2,a7 -800139d8: 40a68533 sub a0,a3,a0 -800139dc: 00f66633 or a2,a2,a5 -800139e0: 40c50533 sub a0,a0,a2 -800139e4: 02a12e23 sw a0,60(sp) -800139e8: 02b12c23 sw a1,56(sp) -800139ec: 02612a23 sw t1,52(sp) -800139f0: 02e12823 sw a4,48(sp) -800139f4: 000e0913 mv s2,t3 -800139f8: d35ff06f j 8001372c <__subtf3+0xaec> -800139fc: 00008737 lui a4,0x8 -80013a00: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80013a04: f6e308e3 beq t1,a4,80013974 <__subtf3+0xd34> -80013a08: 07400713 li a4,116 -80013a0c: 1ec74863 blt a4,a2,80013bfc <__subtf3+0xfbc> -80013a10: 00060313 mv t1,a2 -80013a14: 0400006f j 80013a54 <__subtf3+0xe14> -80013a18: 00008737 lui a4,0x8 -80013a1c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80013a20: 00ee9e63 bne t4,a4,80013a3c <__subtf3+0xdfc> -80013a24: 02f12823 sw a5,48(sp) -80013a28: 03012a23 sw a6,52(sp) -80013a2c: 03112c23 sw a7,56(sp) -80013a30: 02d12e23 sw a3,60(sp) -80013a34: 000e8413 mv s0,t4 -80013a38: f51ff06f j 80013988 <__subtf3+0xd48> -80013a3c: 01c12703 lw a4,28(sp) -80013a40: 00080637 lui a2,0x80 -80013a44: 00c76733 or a4,a4,a2 -80013a48: 00e12e23 sw a4,28(sp) -80013a4c: 07400713 li a4,116 -80013a50: 1a674663 blt a4,t1,80013bfc <__subtf3+0xfbc> -80013a54: 02000713 li a4,32 -80013a58: 02e34fb3 div t6,t1,a4 -80013a5c: 00000293 li t0,0 -80013a60: 00000713 li a4,0 -80013a64: 05f74a63 blt a4,t6,80013ab8 <__subtf3+0xe78> -80013a68: 000f8513 mv a0,t6 -80013a6c: 000fd463 bgez t6,80013a74 <__subtf3+0xe34> -80013a70: 00000513 li a0,0 -80013a74: 01f37713 andi a4,t1,31 -80013a78: 002f9613 slli a2,t6,0x2 -80013a7c: 04071a63 bnez a4,80013ad0 <__subtf3+0xe90> -80013a80: 00300513 li a0,3 -80013a84: 41f50533 sub a0,a0,t6 -80013a88: 00c58333 add t1,a1,a2 -80013a8c: 00032303 lw t1,0(t1) -80013a90: 00170713 addi a4,a4,1 -80013a94: 00458593 addi a1,a1,4 -80013a98: fe65ae23 sw t1,-4(a1) -80013a9c: fee556e3 bge a0,a4,80013a88 <__subtf3+0xe48> -80013aa0: 00400713 li a4,4 -80013aa4: 41f70fb3 sub t6,a4,t6 -80013aa8: 00100713 li a4,1 -80013aac: 09f05063 blez t6,80013b2c <__subtf3+0xeec> -80013ab0: 000f8713 mv a4,t6 -80013ab4: 0780006f j 80013b2c <__subtf3+0xeec> -80013ab8: 00271613 slli a2,a4,0x2 -80013abc: 00cf0633 add a2,t5,a2 -80013ac0: 00062603 lw a2,0(a2) # 80000 <_start-0x7ff80000> -80013ac4: 00170713 addi a4,a4,1 -80013ac8: 00c2e2b3 or t0,t0,a2 -80013acc: f99ff06f j 80013a64 <__subtf3+0xe24> -80013ad0: 02000713 li a4,32 -80013ad4: 02e36333 rem t1,t1,a4 -80013ad8: 04010593 addi a1,sp,64 -80013adc: 00251513 slli a0,a0,0x2 -80013ae0: 00a58533 add a0,a1,a0 -80013ae4: fd052583 lw a1,-48(a0) -80013ae8: 00000393 li t2,0 -80013aec: 40670733 sub a4,a4,t1 -80013af0: 00e595b3 sll a1,a1,a4 -80013af4: 00b2e2b3 or t0,t0,a1 -80013af8: 00cf05b3 add a1,t5,a2 -80013afc: 00300613 li a2,3 -80013b00: 41f60633 sub a2,a2,t6 -80013b04: 00458593 addi a1,a1,4 -80013b08: 02c3c663 blt t2,a2,80013b34 <__subtf3+0xef4> -80013b0c: 04010593 addi a1,sp,64 -80013b10: 00261613 slli a2,a2,0x2 -80013b14: 00c58633 add a2,a1,a2 -80013b18: 01c12583 lw a1,28(sp) -80013b1c: 00400713 li a4,4 -80013b20: 41f70733 sub a4,a4,t6 -80013b24: 0065d333 srl t1,a1,t1 -80013b28: fc662823 sw t1,-48(a2) -80013b2c: 00300593 li a1,3 -80013b30: 03c0006f j 80013b6c <__subtf3+0xf2c> -80013b34: ffc5a503 lw a0,-4(a1) -80013b38: 0005a903 lw s2,0(a1) -80013b3c: 00239413 slli s0,t2,0x2 -80013b40: 00655533 srl a0,a0,t1 -80013b44: 00e91933 sll s2,s2,a4 -80013b48: 008f0433 add s0,t5,s0 -80013b4c: 01256533 or a0,a0,s2 -80013b50: 00a42023 sw a0,0(s0) -80013b54: 00138393 addi t2,t2,1 -80013b58: fadff06f j 80013b04 <__subtf3+0xec4> -80013b5c: 00271613 slli a2,a4,0x2 -80013b60: 00cf0633 add a2,t5,a2 -80013b64: 00062023 sw zero,0(a2) -80013b68: 00170713 addi a4,a4,1 -80013b6c: fee5d8e3 bge a1,a4,80013b5c <__subtf3+0xf1c> -80013b70: 01012603 lw a2,16(sp) -80013b74: 00503733 snez a4,t0 -80013b78: 00e66733 or a4,a2,a4 -80013b7c: 00e12823 sw a4,16(sp) -80013b80: 01012703 lw a4,16(sp) -80013b84: 01412503 lw a0,20(sp) -80013b88: 40e78733 sub a4,a5,a4 -80013b8c: 40a805b3 sub a1,a6,a0 -80013b90: 00e7b633 sltu a2,a5,a4 -80013b94: 00b83333 sltu t1,a6,a1 -80013b98: 40c585b3 sub a1,a1,a2 -80013b9c: 00000613 li a2,0 -80013ba0: 00e7f663 bgeu a5,a4,80013bac <__subtf3+0xf6c> -80013ba4: 41050833 sub a6,a0,a6 -80013ba8: 00183613 seqz a2,a6 -80013bac: 01812503 lw a0,24(sp) -80013bb0: 00666833 or a6,a2,t1 -80013bb4: 00000613 li a2,0 -80013bb8: 40a887b3 sub a5,a7,a0 -80013bbc: 00f8b333 sltu t1,a7,a5 -80013bc0: 410787b3 sub a5,a5,a6 -80013bc4: 00080663 beqz a6,80013bd0 <__subtf3+0xf90> -80013bc8: 411508b3 sub a7,a0,a7 -80013bcc: 0018b613 seqz a2,a7 -80013bd0: 01c12503 lw a0,28(sp) -80013bd4: 00666633 or a2,a2,t1 -80013bd8: 02f12c23 sw a5,56(sp) -80013bdc: 40a686b3 sub a3,a3,a0 -80013be0: 40c686b3 sub a3,a3,a2 -80013be4: 02d12e23 sw a3,60(sp) -80013be8: 02b12a23 sw a1,52(sp) -80013bec: 02e12823 sw a4,48(sp) -80013bf0: 000e8413 mv s0,t4 -80013bf4: 000e0913 mv s2,t3 -80013bf8: d29ff06f j 80013920 <__subtf3+0xce0> -80013bfc: 00012e23 sw zero,28(sp) -80013c00: 00012c23 sw zero,24(sp) -80013c04: 00012a23 sw zero,20(sp) -80013c08: 00100713 li a4,1 -80013c0c: f71ff06f j 80013b7c <__subtf3+0xf3c> -80013c10: 00008f37 lui t5,0x8 -80013c14: ffef0613 addi a2,t5,-2 # 7ffe <_start-0x7fff8002> -80013c18: 00140e93 addi t4,s0,1 -80013c1c: 00cefeb3 and t4,t4,a2 -80013c20: 01812583 lw a1,24(sp) -80013c24: 01412603 lw a2,20(sp) -80013c28: 01c12503 lw a0,28(sp) -80013c2c: 1c0e9c63 bnez t4,80013e04 <__subtf3+0x11c4> -80013c30: 01186333 or t1,a6,a7 -80013c34: 00b66eb3 or t4,a2,a1 -80013c38: 00d36333 or t1,t1,a3 -80013c3c: 00aeeeb3 or t4,t4,a0 -80013c40: 00f36333 or t1,t1,a5 -80013c44: 00eeeeb3 or t4,t4,a4 -80013c48: 10041663 bnez s0,80013d54 <__subtf3+0x1114> -80013c4c: 020e9463 bnez t4,80013c74 <__subtf3+0x1034> -80013c50: 02f12823 sw a5,48(sp) -80013c54: 03012a23 sw a6,52(sp) -80013c58: 03112c23 sw a7,56(sp) -80013c5c: 02d12e23 sw a3,60(sp) -80013c60: 000e0913 mv s2,t3 -80013c64: a0031663 bnez t1,80012e70 <__subtf3+0x230> -80013c68: 00000413 li s0,0 -80013c6c: 00000913 li s2,0 -80013c70: a00ff06f j 80012e70 <__subtf3+0x230> -80013c74: 00031a63 bnez t1,80013c88 <__subtf3+0x1048> -80013c78: 02e12823 sw a4,48(sp) -80013c7c: 02c12a23 sw a2,52(sp) -80013c80: 02b12c23 sw a1,56(sp) -80013c84: 839ff06f j 800134bc <__subtf3+0x87c> -80013c88: 40f70333 sub t1,a4,a5 -80013c8c: 410603b3 sub t2,a2,a6 -80013c90: 00673fb3 sltu t6,a4,t1 -80013c94: 00763eb3 sltu t4,a2,t2 -80013c98: 41f38fb3 sub t6,t2,t6 -80013c9c: 00000f13 li t5,0 -80013ca0: 00677463 bgeu a4,t1,80013ca8 <__subtf3+0x1068> -80013ca4: 0013bf13 seqz t5,t2 -80013ca8: 411582b3 sub t0,a1,a7 -80013cac: 01df6f33 or t5,t5,t4 -80013cb0: 0055bab3 sltu s5,a1,t0 -80013cb4: 41e28a33 sub s4,t0,t5 -80013cb8: 00000993 li s3,0 -80013cbc: 000f0463 beqz t5,80013cc4 <__subtf3+0x1084> -80013cc0: 0012b993 seqz s3,t0 -80013cc4: 40d50eb3 sub t4,a0,a3 -80013cc8: 0159e9b3 or s3,s3,s5 -80013ccc: 413e8eb3 sub t4,t4,s3 -80013cd0: 03d12e23 sw t4,60(sp) -80013cd4: 03412c23 sw s4,56(sp) -80013cd8: 03f12a23 sw t6,52(sp) -80013cdc: 02612823 sw t1,48(sp) -80013ce0: 00ce9f13 slli t5,t4,0xc -80013ce4: 060f5063 bgez t5,80013d44 <__subtf3+0x1104> -80013ce8: 40c80633 sub a2,a6,a2 -80013cec: 40e78733 sub a4,a5,a4 -80013cf0: 00c83333 sltu t1,a6,a2 -80013cf4: 00e7b833 sltu a6,a5,a4 -80013cf8: 41060633 sub a2,a2,a6 -80013cfc: 00000813 li a6,0 -80013d00: 00e7f463 bgeu a5,a4,80013d08 <__subtf3+0x10c8> -80013d04: 0013b813 seqz a6,t2 -80013d08: 00686833 or a6,a6,t1 -80013d0c: 40b885b3 sub a1,a7,a1 -80013d10: 00b8b8b3 sltu a7,a7,a1 -80013d14: 00000313 li t1,0 -80013d18: 410585b3 sub a1,a1,a6 -80013d1c: 00080463 beqz a6,80013d24 <__subtf3+0x10e4> -80013d20: 0012b313 seqz t1,t0 -80013d24: 40a68533 sub a0,a3,a0 -80013d28: 01136333 or t1,t1,a7 -80013d2c: 40650333 sub t1,a0,t1 -80013d30: 02612e23 sw t1,60(sp) -80013d34: 02b12c23 sw a1,56(sp) -80013d38: 02c12a23 sw a2,52(sp) +8001362c: ffff8413 addi s0,t6,-1 +80013630: 905ff06f j 80012f34 <__subtf3+0x230> +80013634: 00c6e6b3 or a3,a3,a2 +80013638: 00a6e533 or a0,a3,a0 +8001363c: 00f567b3 or a5,a0,a5 +80013640: 00079c63 bnez a5,80013658 <__subtf3+0x954> +80013644: 02e12823 sw a4,48(sp) +80013648: 03e12a23 sw t5,52(sp) +8001364c: 03d12c23 sw t4,56(sp) +80013650: 03c12e23 sw t3,60(sp) +80013654: fd9ff06f j 8001362c <__subtf3+0x928> +80013658: 03f12e23 sw t6,60(sp) +8001365c: 02012c23 sw zero,56(sp) +80013660: 02012a23 sw zero,52(sp) +80013664: 02012823 sw zero,48(sp) +80013668: 00030713 mv a4,t1 +8001366c: 00072783 lw a5,0(a4) +80013670: ffc72683 lw a3,-4(a4) +80013674: ffc70713 addi a4,a4,-4 +80013678: 00379793 slli a5,a5,0x3 +8001367c: 01d6d693 srli a3,a3,0x1d +80013680: 00d7e7b3 or a5,a5,a3 +80013684: 00f72223 sw a5,4(a4) +80013688: fee892e3 bne a7,a4,8001366c <__subtf3+0x968> +8001368c: 03012783 lw a5,48(sp) +80013690: 00008437 lui s0,0x8 +80013694: 00000913 li s2,0 +80013698: 00379793 slli a5,a5,0x3 +8001369c: 02f12823 sw a5,48(sp) +800136a0: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +800136a4: 891ff06f j 80012f34 <__subtf3+0x230> +800136a8: 00f707b3 add a5,a4,a5 +800136ac: 00e7b733 sltu a4,a5,a4 +800136b0: 00df06b3 add a3,t5,a3 +800136b4: 02f12823 sw a5,48(sp) +800136b8: 00e687b3 add a5,a3,a4 +800136bc: 00e7b733 sltu a4,a5,a4 +800136c0: 01e6b6b3 sltu a3,a3,t5 +800136c4: 00e6e733 or a4,a3,a4 +800136c8: 00ce86b3 add a3,t4,a2 +800136cc: 02f12a23 sw a5,52(sp) +800136d0: 00e687b3 add a5,a3,a4 +800136d4: 01d6b633 sltu a2,a3,t4 +800136d8: 00e7b6b3 sltu a3,a5,a4 +800136dc: 00d666b3 or a3,a2,a3 +800136e0: 00ae0533 add a0,t3,a0 +800136e4: 00a68533 add a0,a3,a0 +800136e8: 02f12c23 sw a5,56(sp) +800136ec: 02a12e23 sw a0,60(sp) +800136f0: 00088793 mv a5,a7 +800136f4: 0007a703 lw a4,0(a5) +800136f8: 0047a683 lw a3,4(a5) +800136fc: 00478793 addi a5,a5,4 +80013700: 00175713 srli a4,a4,0x1 +80013704: 01f69693 slli a3,a3,0x1f +80013708: 00d76733 or a4,a4,a3 +8001370c: fee7ae23 sw a4,-4(a5) +80013710: fef312e3 bne t1,a5,800136f4 <__subtf3+0x9f0> +80013714: 000087b7 lui a5,0x8 +80013718: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +8001371c: 00f58c63 beq a1,a5,80013734 <__subtf3+0xa30> +80013720: 03c12783 lw a5,60(sp) +80013724: 0017d793 srli a5,a5,0x1 +80013728: 02f12e23 sw a5,60(sp) +8001372c: 00058413 mv s0,a1 +80013730: 805ff06f j 80012f34 <__subtf3+0x230> +80013734: 02012e23 sw zero,60(sp) +80013738: 02012c23 sw zero,56(sp) +8001373c: 02012a23 sw zero,52(sp) +80013740: 02012823 sw zero,48(sp) +80013744: fe9ff06f j 8001372c <__subtf3+0xa28> +80013748: 2a605e63 blez t1,80013a04 <__subtf3+0xd00> +8001374c: 01412883 lw a7,20(sp) +80013750: 01812e03 lw t3,24(sp) +80013754: 01c12f03 lw t5,28(sp) +80013758: 0c0e9463 bnez t4,80013820 <__subtf3+0xb1c> +8001375c: 02412e83 lw t4,36(sp) +80013760: 02812503 lw a0,40(sp) +80013764: 02c12583 lw a1,44(sp) +80013768: 00aee633 or a2,t4,a0 +8001376c: 00b66633 or a2,a2,a1 +80013770: 00f66633 or a2,a2,a5 +80013774: 00061c63 bnez a2,8001378c <__subtf3+0xa88> +80013778: 02e12823 sw a4,48(sp) +8001377c: 03112a23 sw a7,52(sp) +80013780: 03c12c23 sw t3,56(sp) +80013784: 03e12e23 sw t5,60(sp) +80013788: f08ff06f j 80012e90 <__subtf3+0x18c> +8001378c: fff30613 addi a2,t1,-1 +80013790: 06061463 bnez a2,800137f8 <__subtf3+0xaf4> +80013794: 40f707b3 sub a5,a4,a5 +80013798: 41d886b3 sub a3,a7,t4 +8001379c: 00f73833 sltu a6,a4,a5 +800137a0: 00d8b333 sltu t1,a7,a3 +800137a4: 41068833 sub a6,a3,a6 +800137a8: 00000693 li a3,0 +800137ac: 00f77663 bgeu a4,a5,800137b8 <__subtf3+0xab4> +800137b0: 411e88b3 sub a7,t4,a7 +800137b4: 0018b693 seqz a3,a7 +800137b8: 0066e8b3 or a7,a3,t1 +800137bc: 40ae0733 sub a4,t3,a0 +800137c0: 00ee36b3 sltu a3,t3,a4 +800137c4: 41170733 sub a4,a4,a7 +800137c8: 00088663 beqz a7,800137d4 <__subtf3+0xad0> +800137cc: 41c50e33 sub t3,a0,t3 +800137d0: 001e3613 seqz a2,t3 +800137d4: 40bf05b3 sub a1,t5,a1 +800137d8: 00d66633 or a2,a2,a3 +800137dc: 40c585b3 sub a1,a1,a2 +800137e0: 02b12e23 sw a1,60(sp) +800137e4: 02e12c23 sw a4,56(sp) +800137e8: 03012a23 sw a6,52(sp) +800137ec: 02f12823 sw a5,48(sp) +800137f0: 00100413 li s0,1 +800137f4: 1f00006f j 800139e4 <__subtf3+0xce0> +800137f8: 000087b7 lui a5,0x8 +800137fc: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80013800: f6f30ce3 beq t1,a5,80013778 <__subtf3+0xa74> +80013804: 07400793 li a5,116 +80013808: 04c7da63 bge a5,a2,8001385c <__subtf3+0xb58> +8001380c: 02012623 sw zero,44(sp) +80013810: 02012423 sw zero,40(sp) +80013814: 02012223 sw zero,36(sp) +80013818: 00100793 li a5,1 +8001381c: 1540006f j 80013970 <__subtf3+0xc6c> +80013820: 000087b7 lui a5,0x8 +80013824: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80013828: 00f41c63 bne s0,a5,80013840 <__subtf3+0xb3c> +8001382c: 02e12823 sw a4,48(sp) +80013830: 03112a23 sw a7,52(sp) +80013834: 03c12c23 sw t3,56(sp) +80013838: 03e12e23 sw t5,60(sp) +8001383c: ef8ff06f j 80012f34 <__subtf3+0x230> +80013840: 02c12783 lw a5,44(sp) +80013844: 00080637 lui a2,0x80 +80013848: 00c7e7b3 or a5,a5,a2 +8001384c: 02f12623 sw a5,44(sp) +80013850: 07400793 li a5,116 +80013854: fa67cce3 blt a5,t1,8001380c <__subtf3+0xb08> +80013858: 00030613 mv a2,t1 +8001385c: 40565513 srai a0,a2,0x5 +80013860: 00000313 li t1,0 +80013864: 00000793 li a5,0 +80013868: 04a79663 bne a5,a0,800138b4 <__subtf3+0xbb0> +8001386c: 01f67593 andi a1,a2,31 +80013870: 00251613 slli a2,a0,0x2 +80013874: 04059c63 bnez a1,800138cc <__subtf3+0xbc8> +80013878: 00300593 li a1,3 +8001387c: 00000793 li a5,0 +80013880: 40a585b3 sub a1,a1,a0 +80013884: 00c68eb3 add t4,a3,a2 +80013888: 000eae83 lw t4,0(t4) +8001388c: 00178793 addi a5,a5,1 +80013890: 00468693 addi a3,a3,4 +80013894: ffd6ae23 sw t4,-4(a3) +80013898: fef5d6e3 bge a1,a5,80013884 <__subtf3+0xb80> +8001389c: 00400793 li a5,4 +800138a0: 40a78533 sub a0,a5,a0 +800138a4: 00100793 li a5,1 +800138a8: 06a05c63 blez a0,80013920 <__subtf3+0xc1c> +800138ac: 00050793 mv a5,a0 +800138b0: 0700006f j 80013920 <__subtf3+0xc1c> +800138b4: 00279593 slli a1,a5,0x2 +800138b8: 00b805b3 add a1,a6,a1 +800138bc: 0005a583 lw a1,0(a1) +800138c0: 00178793 addi a5,a5,1 +800138c4: 00b36333 or t1,t1,a1 +800138c8: fa1ff06f j 80013868 <__subtf3+0xb64> +800138cc: 04010793 addi a5,sp,64 +800138d0: 00c787b3 add a5,a5,a2 +800138d4: fe07a783 lw a5,-32(a5) +800138d8: 02000f93 li t6,32 +800138dc: 40bf8fb3 sub t6,t6,a1 +800138e0: 01f797b3 sll a5,a5,t6 +800138e4: 00300693 li a3,3 +800138e8: 00f36333 or t1,t1,a5 +800138ec: 00c80633 add a2,a6,a2 +800138f0: 00000e93 li t4,0 +800138f4: 40a686b3 sub a3,a3,a0 +800138f8: 00460613 addi a2,a2,4 # 80004 <_start-0x7ff7fffc> +800138fc: 02dec663 blt t4,a3,80013928 <__subtf3+0xc24> +80013900: 04010613 addi a2,sp,64 +80013904: 00269693 slli a3,a3,0x2 +80013908: 00d606b3 add a3,a2,a3 +8001390c: 02c12603 lw a2,44(sp) +80013910: 00400793 li a5,4 +80013914: 40a787b3 sub a5,a5,a0 +80013918: 00b65633 srl a2,a2,a1 +8001391c: fec6a023 sw a2,-32(a3) +80013920: 00400613 li a2,4 +80013924: 03c0006f j 80013960 <__subtf3+0xc5c> +80013928: ffc62783 lw a5,-4(a2) +8001392c: 00062383 lw t2,0(a2) +80013930: 002e9293 slli t0,t4,0x2 +80013934: 00b7d7b3 srl a5,a5,a1 +80013938: 01f393b3 sll t2,t2,t6 +8001393c: 005802b3 add t0,a6,t0 +80013940: 0077e7b3 or a5,a5,t2 +80013944: 00f2a023 sw a5,0(t0) +80013948: 001e8e93 addi t4,t4,1 +8001394c: fadff06f j 800138f8 <__subtf3+0xbf4> +80013950: 00279693 slli a3,a5,0x2 +80013954: 00d806b3 add a3,a6,a3 +80013958: 0006a023 sw zero,0(a3) +8001395c: 00178793 addi a5,a5,1 +80013960: fec798e3 bne a5,a2,80013950 <__subtf3+0xc4c> +80013964: 02012683 lw a3,32(sp) +80013968: 006037b3 snez a5,t1 +8001396c: 00f6e7b3 or a5,a3,a5 +80013970: 02f12023 sw a5,32(sp) +80013974: 02012783 lw a5,32(sp) +80013978: 02412583 lw a1,36(sp) +8001397c: 40f707b3 sub a5,a4,a5 +80013980: 40b88633 sub a2,a7,a1 +80013984: 00f736b3 sltu a3,a4,a5 +80013988: 00c8b533 sltu a0,a7,a2 +8001398c: 40d60633 sub a2,a2,a3 +80013990: 00000693 li a3,0 +80013994: 00f77663 bgeu a4,a5,800139a0 <__subtf3+0xc9c> +80013998: 411588b3 sub a7,a1,a7 +8001399c: 0018b693 seqz a3,a7 +800139a0: 00a6e8b3 or a7,a3,a0 +800139a4: 02812503 lw a0,40(sp) +800139a8: 00000693 li a3,0 +800139ac: 40ae0733 sub a4,t3,a0 +800139b0: 00ee3833 sltu a6,t3,a4 +800139b4: 41170733 sub a4,a4,a7 +800139b8: 00088663 beqz a7,800139c4 <__subtf3+0xcc0> +800139bc: 41c50e33 sub t3,a0,t3 +800139c0: 001e3693 seqz a3,t3 +800139c4: 02c12583 lw a1,44(sp) +800139c8: 0106e6b3 or a3,a3,a6 +800139cc: 02e12c23 sw a4,56(sp) +800139d0: 40bf05b3 sub a1,t5,a1 +800139d4: 40d585b3 sub a1,a1,a3 +800139d8: 02b12e23 sw a1,60(sp) +800139dc: 02c12a23 sw a2,52(sp) +800139e0: 02f12823 sw a5,48(sp) +800139e4: 03c12783 lw a5,60(sp) +800139e8: 00c79713 slli a4,a5,0xc +800139ec: d4075463 bgez a4,80012f34 <__subtf3+0x230> +800139f0: 00080737 lui a4,0x80 +800139f4: fff70713 addi a4,a4,-1 # 7ffff <_start-0x7ff80001> +800139f8: 00e7f7b3 and a5,a5,a4 +800139fc: 02f12e23 sw a5,60(sp) +80013a00: 5800006f j 80013f80 <__subtf3+0x127c> +80013a04: 02412803 lw a6,36(sp) +80013a08: 02812883 lw a7,40(sp) +80013a0c: 02c12683 lw a3,44(sp) +80013a10: 2c030263 beqz t1,80013cd4 <__subtf3+0xfd0> +80013a14: 408e8333 sub t1,t4,s0 +80013a18: 0c041263 bnez s0,80013adc <__subtf3+0xdd8> +80013a1c: 01412283 lw t0,20(sp) +80013a20: 01812f83 lw t6,24(sp) +80013a24: 01c12503 lw a0,28(sp) +80013a28: 01f2e633 or a2,t0,t6 +80013a2c: 00a66633 or a2,a2,a0 +80013a30: 00e66633 or a2,a2,a4 +80013a34: 02061063 bnez a2,80013a54 <__subtf3+0xd50> +80013a38: 02f12823 sw a5,48(sp) +80013a3c: 03012a23 sw a6,52(sp) +80013a40: 03112c23 sw a7,56(sp) +80013a44: 02d12e23 sw a3,60(sp) +80013a48: 00030413 mv s0,t1 +80013a4c: 000e0913 mv s2,t3 +80013a50: ce4ff06f j 80012f34 <__subtf3+0x230> +80013a54: fff30613 addi a2,t1,-1 +80013a58: 06061463 bnez a2,80013ac0 <__subtf3+0xdbc> +80013a5c: 40e78733 sub a4,a5,a4 +80013a60: 405805b3 sub a1,a6,t0 +80013a64: 00e7b333 sltu t1,a5,a4 +80013a68: 00b83eb3 sltu t4,a6,a1 +80013a6c: 40658333 sub t1,a1,t1 +80013a70: 00000593 li a1,0 +80013a74: 00e7f663 bgeu a5,a4,80013a80 <__subtf3+0xd7c> +80013a78: 41028833 sub a6,t0,a6 +80013a7c: 00183593 seqz a1,a6 +80013a80: 01d5e833 or a6,a1,t4 +80013a84: 41f885b3 sub a1,a7,t6 +80013a88: 00b8b7b3 sltu a5,a7,a1 +80013a8c: 410585b3 sub a1,a1,a6 +80013a90: 00080663 beqz a6,80013a9c <__subtf3+0xd98> +80013a94: 411f88b3 sub a7,t6,a7 +80013a98: 0018b613 seqz a2,a7 +80013a9c: 40a68533 sub a0,a3,a0 +80013aa0: 00f66633 or a2,a2,a5 +80013aa4: 40c50533 sub a0,a0,a2 +80013aa8: 02a12e23 sw a0,60(sp) +80013aac: 02b12c23 sw a1,56(sp) +80013ab0: 02612a23 sw t1,52(sp) +80013ab4: 02e12823 sw a4,48(sp) +80013ab8: 000e0913 mv s2,t3 +80013abc: d35ff06f j 800137f0 <__subtf3+0xaec> +80013ac0: 00008737 lui a4,0x8 +80013ac4: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80013ac8: f6e308e3 beq t1,a4,80013a38 <__subtf3+0xd34> +80013acc: 07400713 li a4,116 +80013ad0: 1ec74863 blt a4,a2,80013cc0 <__subtf3+0xfbc> +80013ad4: 00060313 mv t1,a2 +80013ad8: 0400006f j 80013b18 <__subtf3+0xe14> +80013adc: 00008737 lui a4,0x8 +80013ae0: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80013ae4: 00ee9e63 bne t4,a4,80013b00 <__subtf3+0xdfc> +80013ae8: 02f12823 sw a5,48(sp) +80013aec: 03012a23 sw a6,52(sp) +80013af0: 03112c23 sw a7,56(sp) +80013af4: 02d12e23 sw a3,60(sp) +80013af8: 000e8413 mv s0,t4 +80013afc: f51ff06f j 80013a4c <__subtf3+0xd48> +80013b00: 01c12703 lw a4,28(sp) +80013b04: 00080637 lui a2,0x80 +80013b08: 00c76733 or a4,a4,a2 +80013b0c: 00e12e23 sw a4,28(sp) +80013b10: 07400713 li a4,116 +80013b14: 1a674663 blt a4,t1,80013cc0 <__subtf3+0xfbc> +80013b18: 02000713 li a4,32 +80013b1c: 02e34fb3 div t6,t1,a4 +80013b20: 00000293 li t0,0 +80013b24: 00000713 li a4,0 +80013b28: 05f74a63 blt a4,t6,80013b7c <__subtf3+0xe78> +80013b2c: 000f8513 mv a0,t6 +80013b30: 000fd463 bgez t6,80013b38 <__subtf3+0xe34> +80013b34: 00000513 li a0,0 +80013b38: 01f37713 andi a4,t1,31 +80013b3c: 002f9613 slli a2,t6,0x2 +80013b40: 04071a63 bnez a4,80013b94 <__subtf3+0xe90> +80013b44: 00300513 li a0,3 +80013b48: 41f50533 sub a0,a0,t6 +80013b4c: 00c58333 add t1,a1,a2 +80013b50: 00032303 lw t1,0(t1) +80013b54: 00170713 addi a4,a4,1 +80013b58: 00458593 addi a1,a1,4 +80013b5c: fe65ae23 sw t1,-4(a1) +80013b60: fee556e3 bge a0,a4,80013b4c <__subtf3+0xe48> +80013b64: 00400713 li a4,4 +80013b68: 41f70fb3 sub t6,a4,t6 +80013b6c: 00100713 li a4,1 +80013b70: 09f05063 blez t6,80013bf0 <__subtf3+0xeec> +80013b74: 000f8713 mv a4,t6 +80013b78: 0780006f j 80013bf0 <__subtf3+0xeec> +80013b7c: 00271613 slli a2,a4,0x2 +80013b80: 00cf0633 add a2,t5,a2 +80013b84: 00062603 lw a2,0(a2) # 80000 <_start-0x7ff80000> +80013b88: 00170713 addi a4,a4,1 +80013b8c: 00c2e2b3 or t0,t0,a2 +80013b90: f99ff06f j 80013b28 <__subtf3+0xe24> +80013b94: 02000713 li a4,32 +80013b98: 02e36333 rem t1,t1,a4 +80013b9c: 04010593 addi a1,sp,64 +80013ba0: 00251513 slli a0,a0,0x2 +80013ba4: 00a58533 add a0,a1,a0 +80013ba8: fd052583 lw a1,-48(a0) +80013bac: 00000393 li t2,0 +80013bb0: 40670733 sub a4,a4,t1 +80013bb4: 00e595b3 sll a1,a1,a4 +80013bb8: 00b2e2b3 or t0,t0,a1 +80013bbc: 00cf05b3 add a1,t5,a2 +80013bc0: 00300613 li a2,3 +80013bc4: 41f60633 sub a2,a2,t6 +80013bc8: 00458593 addi a1,a1,4 +80013bcc: 02c3c663 blt t2,a2,80013bf8 <__subtf3+0xef4> +80013bd0: 04010593 addi a1,sp,64 +80013bd4: 00261613 slli a2,a2,0x2 +80013bd8: 00c58633 add a2,a1,a2 +80013bdc: 01c12583 lw a1,28(sp) +80013be0: 00400713 li a4,4 +80013be4: 41f70733 sub a4,a4,t6 +80013be8: 0065d333 srl t1,a1,t1 +80013bec: fc662823 sw t1,-48(a2) +80013bf0: 00300593 li a1,3 +80013bf4: 03c0006f j 80013c30 <__subtf3+0xf2c> +80013bf8: ffc5a503 lw a0,-4(a1) +80013bfc: 0005a903 lw s2,0(a1) +80013c00: 00239413 slli s0,t2,0x2 +80013c04: 00655533 srl a0,a0,t1 +80013c08: 00e91933 sll s2,s2,a4 +80013c0c: 008f0433 add s0,t5,s0 +80013c10: 01256533 or a0,a0,s2 +80013c14: 00a42023 sw a0,0(s0) +80013c18: 00138393 addi t2,t2,1 +80013c1c: fadff06f j 80013bc8 <__subtf3+0xec4> +80013c20: 00271613 slli a2,a4,0x2 +80013c24: 00cf0633 add a2,t5,a2 +80013c28: 00062023 sw zero,0(a2) +80013c2c: 00170713 addi a4,a4,1 +80013c30: fee5d8e3 bge a1,a4,80013c20 <__subtf3+0xf1c> +80013c34: 01012603 lw a2,16(sp) +80013c38: 00503733 snez a4,t0 +80013c3c: 00e66733 or a4,a2,a4 +80013c40: 00e12823 sw a4,16(sp) +80013c44: 01012703 lw a4,16(sp) +80013c48: 01412503 lw a0,20(sp) +80013c4c: 40e78733 sub a4,a5,a4 +80013c50: 40a805b3 sub a1,a6,a0 +80013c54: 00e7b633 sltu a2,a5,a4 +80013c58: 00b83333 sltu t1,a6,a1 +80013c5c: 40c585b3 sub a1,a1,a2 +80013c60: 00000613 li a2,0 +80013c64: 00e7f663 bgeu a5,a4,80013c70 <__subtf3+0xf6c> +80013c68: 41050833 sub a6,a0,a6 +80013c6c: 00183613 seqz a2,a6 +80013c70: 01812503 lw a0,24(sp) +80013c74: 00666833 or a6,a2,t1 +80013c78: 00000613 li a2,0 +80013c7c: 40a887b3 sub a5,a7,a0 +80013c80: 00f8b333 sltu t1,a7,a5 +80013c84: 410787b3 sub a5,a5,a6 +80013c88: 00080663 beqz a6,80013c94 <__subtf3+0xf90> +80013c8c: 411508b3 sub a7,a0,a7 +80013c90: 0018b613 seqz a2,a7 +80013c94: 01c12503 lw a0,28(sp) +80013c98: 00666633 or a2,a2,t1 +80013c9c: 02f12c23 sw a5,56(sp) +80013ca0: 40a686b3 sub a3,a3,a0 +80013ca4: 40c686b3 sub a3,a3,a2 +80013ca8: 02d12e23 sw a3,60(sp) +80013cac: 02b12a23 sw a1,52(sp) +80013cb0: 02e12823 sw a4,48(sp) +80013cb4: 000e8413 mv s0,t4 +80013cb8: 000e0913 mv s2,t3 +80013cbc: d29ff06f j 800139e4 <__subtf3+0xce0> +80013cc0: 00012e23 sw zero,28(sp) +80013cc4: 00012c23 sw zero,24(sp) +80013cc8: 00012a23 sw zero,20(sp) +80013ccc: 00100713 li a4,1 +80013cd0: f71ff06f j 80013c40 <__subtf3+0xf3c> +80013cd4: 00008f37 lui t5,0x8 +80013cd8: ffef0613 addi a2,t5,-2 # 7ffe <_start-0x7fff8002> +80013cdc: 00140e93 addi t4,s0,1 +80013ce0: 00cefeb3 and t4,t4,a2 +80013ce4: 01812583 lw a1,24(sp) +80013ce8: 01412603 lw a2,20(sp) +80013cec: 01c12503 lw a0,28(sp) +80013cf0: 1c0e9c63 bnez t4,80013ec8 <__subtf3+0x11c4> +80013cf4: 01186333 or t1,a6,a7 +80013cf8: 00b66eb3 or t4,a2,a1 +80013cfc: 00d36333 or t1,t1,a3 +80013d00: 00aeeeb3 or t4,t4,a0 +80013d04: 00f36333 or t1,t1,a5 +80013d08: 00eeeeb3 or t4,t4,a4 +80013d0c: 10041663 bnez s0,80013e18 <__subtf3+0x1114> +80013d10: 020e9463 bnez t4,80013d38 <__subtf3+0x1034> +80013d14: 02f12823 sw a5,48(sp) +80013d18: 03012a23 sw a6,52(sp) +80013d1c: 03112c23 sw a7,56(sp) +80013d20: 02d12e23 sw a3,60(sp) +80013d24: 000e0913 mv s2,t3 +80013d28: a0031663 bnez t1,80012f34 <__subtf3+0x230> +80013d2c: 00000413 li s0,0 +80013d30: 00000913 li s2,0 +80013d34: a00ff06f j 80012f34 <__subtf3+0x230> +80013d38: 00031a63 bnez t1,80013d4c <__subtf3+0x1048> 80013d3c: 02e12823 sw a4,48(sp) -80013d40: c49ff06f j 80013988 <__subtf3+0xd48> -80013d44: 01f36333 or t1,t1,t6 -80013d48: 01436333 or t1,t1,s4 -80013d4c: 01d36333 or t1,t1,t4 -80013d50: f15ff06f j 80013c64 <__subtf3+0x1024> -80013d54: 03010f93 addi t6,sp,48 -80013d58: 040e9e63 bnez t4,80013db4 <__subtf3+0x1174> -80013d5c: 02031e63 bnez t1,80013d98 <__subtf3+0x1158> -80013d60: 03e12e23 sw t5,60(sp) -80013d64: 02012c23 sw zero,56(sp) -80013d68: 02012a23 sw zero,52(sp) -80013d6c: 02012823 sw zero,48(sp) -80013d70: 03c10793 addi a5,sp,60 -80013d74: 0007a703 lw a4,0(a5) -80013d78: ffc7a683 lw a3,-4(a5) -80013d7c: ffc78793 addi a5,a5,-4 -80013d80: 00371713 slli a4,a4,0x3 -80013d84: 01d6d693 srli a3,a3,0x1d -80013d88: 00d76733 or a4,a4,a3 -80013d8c: 00e7a223 sw a4,4(a5) -80013d90: feff92e3 bne t6,a5,80013d74 <__subtf3+0x1134> -80013d94: 835ff06f j 800135c8 <__subtf3+0x988> -80013d98: 02f12823 sw a5,48(sp) -80013d9c: 03012a23 sw a6,52(sp) -80013da0: 03112c23 sw a7,56(sp) -80013da4: 02d12e23 sw a3,60(sp) -80013da8: 000e0913 mv s2,t3 -80013dac: ffff0413 addi s0,t5,-1 -80013db0: 8c0ff06f j 80012e70 <__subtf3+0x230> -80013db4: 00031c63 bnez t1,80013dcc <__subtf3+0x118c> -80013db8: 02e12823 sw a4,48(sp) -80013dbc: 02c12a23 sw a2,52(sp) -80013dc0: 02b12c23 sw a1,56(sp) -80013dc4: 02a12e23 sw a0,60(sp) -80013dc8: fe5ff06f j 80013dac <__subtf3+0x116c> -80013dcc: 03e12e23 sw t5,60(sp) -80013dd0: 02012c23 sw zero,56(sp) -80013dd4: 02012a23 sw zero,52(sp) -80013dd8: 02012823 sw zero,48(sp) -80013ddc: 03c10793 addi a5,sp,60 -80013de0: 0007a703 lw a4,0(a5) -80013de4: ffc7a683 lw a3,-4(a5) -80013de8: ffc78793 addi a5,a5,-4 -80013dec: 00371713 slli a4,a4,0x3 -80013df0: 01d6d693 srli a3,a3,0x1d -80013df4: 00d76733 or a4,a4,a3 -80013df8: 00e7a223 sw a4,4(a5) -80013dfc: feff92e3 bne t6,a5,80013de0 <__subtf3+0x11a0> -80013e00: fc8ff06f j 800135c8 <__subtf3+0x988> -80013e04: 40f70eb3 sub t4,a4,a5 -80013e08: 410609b3 sub s3,a2,a6 -80013e0c: 01d732b3 sltu t0,a4,t4 -80013e10: 01363f33 sltu t5,a2,s3 -80013e14: 405982b3 sub t0,s3,t0 -80013e18: 00000f93 li t6,0 -80013e1c: 01d77463 bgeu a4,t4,80013e24 <__subtf3+0x11e4> -80013e20: 0019bf93 seqz t6,s3 -80013e24: 411583b3 sub t2,a1,a7 -80013e28: 01efefb3 or t6,t6,t5 -80013e2c: 0075bb33 sltu s6,a1,t2 -80013e30: 41f38ab3 sub s5,t2,t6 -80013e34: 00000a13 li s4,0 -80013e38: 000f8463 beqz t6,80013e40 <__subtf3+0x1200> -80013e3c: 0013ba13 seqz s4,t2 -80013e40: 40d50f33 sub t5,a0,a3 -80013e44: 016a6a33 or s4,s4,s6 -80013e48: 414f0f33 sub t5,t5,s4 -80013e4c: 03e12e23 sw t5,60(sp) -80013e50: 03512c23 sw s5,56(sp) -80013e54: 02512a23 sw t0,52(sp) -80013e58: 03d12823 sw t4,48(sp) -80013e5c: 00cf1f93 slli t6,t5,0xc -80013e60: 0c0fd063 bgez t6,80013f20 <__subtf3+0x12e0> -80013e64: 40c80633 sub a2,a6,a2 -80013e68: 40e78733 sub a4,a5,a4 -80013e6c: 00c83eb3 sltu t4,a6,a2 -80013e70: 00e7b833 sltu a6,a5,a4 -80013e74: 41060633 sub a2,a2,a6 -80013e78: 00000813 li a6,0 -80013e7c: 00e7f463 bgeu a5,a4,80013e84 <__subtf3+0x1244> -80013e80: 0019b813 seqz a6,s3 -80013e84: 40b885b3 sub a1,a7,a1 -80013e88: 01d86833 or a6,a6,t4 -80013e8c: 00b8b8b3 sltu a7,a7,a1 -80013e90: 410585b3 sub a1,a1,a6 -80013e94: 00080463 beqz a6,80013e9c <__subtf3+0x125c> -80013e98: 0013b313 seqz t1,t2 -80013e9c: 40a68533 sub a0,a3,a0 -80013ea0: 011366b3 or a3,t1,a7 -80013ea4: 40d506b3 sub a3,a0,a3 -80013ea8: 02d12e23 sw a3,60(sp) -80013eac: 02b12c23 sw a1,56(sp) -80013eb0: 02c12a23 sw a2,52(sp) -80013eb4: 02e12823 sw a4,48(sp) -80013eb8: 000e0913 mv s2,t3 -80013ebc: 03c12503 lw a0,60(sp) -80013ec0: 06050a63 beqz a0,80013f34 <__subtf3+0x12f4> -80013ec4: 241000ef jal ra,80014904 <__clzsi2> -80013ec8: ff450793 addi a5,a0,-12 -80013ecc: 02000613 li a2,32 -80013ed0: 01f7f693 andi a3,a5,31 -80013ed4: 02c7c733 div a4,a5,a2 -80013ed8: 08068a63 beqz a3,80013f6c <__subtf3+0x132c> -80013edc: ffc00693 li a3,-4 -80013ee0: 03010313 addi t1,sp,48 -80013ee4: 00271513 slli a0,a4,0x2 -80013ee8: 02c7e833 rem a6,a5,a2 -80013eec: 02d706b3 mul a3,a4,a3 -80013ef0: 41060633 sub a2,a2,a6 -80013ef4: 00c68693 addi a3,a3,12 -80013ef8: 00d306b3 add a3,t1,a3 -80013efc: 0ad31063 bne t1,a3,80013f9c <__subtf3+0x135c> -80013f00: 04010693 addi a3,sp,64 -80013f04: 00a68533 add a0,a3,a0 -80013f08: 03012683 lw a3,48(sp) -80013f0c: fff70713 addi a4,a4,-1 -80013f10: 010696b3 sll a3,a3,a6 -80013f14: fed52823 sw a3,-16(a0) -80013f18: fff00613 li a2,-1 -80013f1c: 0b80006f j 80013fd4 <__subtf3+0x1394> -80013f20: 005eeeb3 or t4,t4,t0 -80013f24: 015eeeb3 or t4,t4,s5 -80013f28: 01eeeeb3 or t4,t4,t5 -80013f2c: d20e8ee3 beqz t4,80013c68 <__subtf3+0x1028> -80013f30: f8dff06f j 80013ebc <__subtf3+0x127c> -80013f34: 03812503 lw a0,56(sp) -80013f38: 00050863 beqz a0,80013f48 <__subtf3+0x1308> -80013f3c: 1c9000ef jal ra,80014904 <__clzsi2> -80013f40: 02050513 addi a0,a0,32 -80013f44: f85ff06f j 80013ec8 <__subtf3+0x1288> -80013f48: 03412503 lw a0,52(sp) -80013f4c: 00050863 beqz a0,80013f5c <__subtf3+0x131c> -80013f50: 1b5000ef jal ra,80014904 <__clzsi2> -80013f54: 04050513 addi a0,a0,64 -80013f58: f71ff06f j 80013ec8 <__subtf3+0x1288> -80013f5c: 03012503 lw a0,48(sp) -80013f60: 1a5000ef jal ra,80014904 <__clzsi2> -80013f64: 06050513 addi a0,a0,96 -80013f68: f61ff06f j 80013ec8 <__subtf3+0x1288> -80013f6c: ffc00593 li a1,-4 -80013f70: 02b705b3 mul a1,a4,a1 -80013f74: 03c10693 addi a3,sp,60 -80013f78: 00300613 li a2,3 -80013f7c: 00b68533 add a0,a3,a1 -80013f80: 00052503 lw a0,0(a0) -80013f84: fff60613 addi a2,a2,-1 -80013f88: ffc68693 addi a3,a3,-4 -80013f8c: 00a6a223 sw a0,4(a3) -80013f90: fee656e3 bge a2,a4,80013f7c <__subtf3+0x133c> -80013f94: fff70713 addi a4,a4,-1 -80013f98: f81ff06f j 80013f18 <__subtf3+0x12d8> -80013f9c: ffc6a583 lw a1,-4(a3) -80013fa0: 0006a883 lw a7,0(a3) -80013fa4: 00a68e33 add t3,a3,a0 -80013fa8: 00c5d5b3 srl a1,a1,a2 -80013fac: 010898b3 sll a7,a7,a6 -80013fb0: 0115e5b3 or a1,a1,a7 -80013fb4: 00be2023 sw a1,0(t3) -80013fb8: ffc68693 addi a3,a3,-4 -80013fbc: f41ff06f j 80013efc <__subtf3+0x12bc> -80013fc0: 00271693 slli a3,a4,0x2 -80013fc4: 03010593 addi a1,sp,48 -80013fc8: 00d586b3 add a3,a1,a3 -80013fcc: 0006a023 sw zero,0(a3) +80013d40: 02c12a23 sw a2,52(sp) +80013d44: 02b12c23 sw a1,56(sp) +80013d48: 839ff06f j 80013580 <__subtf3+0x87c> +80013d4c: 40f70333 sub t1,a4,a5 +80013d50: 410603b3 sub t2,a2,a6 +80013d54: 00673fb3 sltu t6,a4,t1 +80013d58: 00763eb3 sltu t4,a2,t2 +80013d5c: 41f38fb3 sub t6,t2,t6 +80013d60: 00000f13 li t5,0 +80013d64: 00677463 bgeu a4,t1,80013d6c <__subtf3+0x1068> +80013d68: 0013bf13 seqz t5,t2 +80013d6c: 411582b3 sub t0,a1,a7 +80013d70: 01df6f33 or t5,t5,t4 +80013d74: 0055bab3 sltu s5,a1,t0 +80013d78: 41e28a33 sub s4,t0,t5 +80013d7c: 00000993 li s3,0 +80013d80: 000f0463 beqz t5,80013d88 <__subtf3+0x1084> +80013d84: 0012b993 seqz s3,t0 +80013d88: 40d50eb3 sub t4,a0,a3 +80013d8c: 0159e9b3 or s3,s3,s5 +80013d90: 413e8eb3 sub t4,t4,s3 +80013d94: 03d12e23 sw t4,60(sp) +80013d98: 03412c23 sw s4,56(sp) +80013d9c: 03f12a23 sw t6,52(sp) +80013da0: 02612823 sw t1,48(sp) +80013da4: 00ce9f13 slli t5,t4,0xc +80013da8: 060f5063 bgez t5,80013e08 <__subtf3+0x1104> +80013dac: 40c80633 sub a2,a6,a2 +80013db0: 40e78733 sub a4,a5,a4 +80013db4: 00c83333 sltu t1,a6,a2 +80013db8: 00e7b833 sltu a6,a5,a4 +80013dbc: 41060633 sub a2,a2,a6 +80013dc0: 00000813 li a6,0 +80013dc4: 00e7f463 bgeu a5,a4,80013dcc <__subtf3+0x10c8> +80013dc8: 0013b813 seqz a6,t2 +80013dcc: 00686833 or a6,a6,t1 +80013dd0: 40b885b3 sub a1,a7,a1 +80013dd4: 00b8b8b3 sltu a7,a7,a1 +80013dd8: 00000313 li t1,0 +80013ddc: 410585b3 sub a1,a1,a6 +80013de0: 00080463 beqz a6,80013de8 <__subtf3+0x10e4> +80013de4: 0012b313 seqz t1,t0 +80013de8: 40a68533 sub a0,a3,a0 +80013dec: 01136333 or t1,t1,a7 +80013df0: 40650333 sub t1,a0,t1 +80013df4: 02612e23 sw t1,60(sp) +80013df8: 02b12c23 sw a1,56(sp) +80013dfc: 02c12a23 sw a2,52(sp) +80013e00: 02e12823 sw a4,48(sp) +80013e04: c49ff06f j 80013a4c <__subtf3+0xd48> +80013e08: 01f36333 or t1,t1,t6 +80013e0c: 01436333 or t1,t1,s4 +80013e10: 01d36333 or t1,t1,t4 +80013e14: f15ff06f j 80013d28 <__subtf3+0x1024> +80013e18: 03010f93 addi t6,sp,48 +80013e1c: 040e9e63 bnez t4,80013e78 <__subtf3+0x1174> +80013e20: 02031e63 bnez t1,80013e5c <__subtf3+0x1158> +80013e24: 03e12e23 sw t5,60(sp) +80013e28: 02012c23 sw zero,56(sp) +80013e2c: 02012a23 sw zero,52(sp) +80013e30: 02012823 sw zero,48(sp) +80013e34: 03c10793 addi a5,sp,60 +80013e38: 0007a703 lw a4,0(a5) +80013e3c: ffc7a683 lw a3,-4(a5) +80013e40: ffc78793 addi a5,a5,-4 +80013e44: 00371713 slli a4,a4,0x3 +80013e48: 01d6d693 srli a3,a3,0x1d +80013e4c: 00d76733 or a4,a4,a3 +80013e50: 00e7a223 sw a4,4(a5) +80013e54: feff92e3 bne t6,a5,80013e38 <__subtf3+0x1134> +80013e58: 835ff06f j 8001368c <__subtf3+0x988> +80013e5c: 02f12823 sw a5,48(sp) +80013e60: 03012a23 sw a6,52(sp) +80013e64: 03112c23 sw a7,56(sp) +80013e68: 02d12e23 sw a3,60(sp) +80013e6c: 000e0913 mv s2,t3 +80013e70: ffff0413 addi s0,t5,-1 +80013e74: 8c0ff06f j 80012f34 <__subtf3+0x230> +80013e78: 00031c63 bnez t1,80013e90 <__subtf3+0x118c> +80013e7c: 02e12823 sw a4,48(sp) +80013e80: 02c12a23 sw a2,52(sp) +80013e84: 02b12c23 sw a1,56(sp) +80013e88: 02a12e23 sw a0,60(sp) +80013e8c: fe5ff06f j 80013e70 <__subtf3+0x116c> +80013e90: 03e12e23 sw t5,60(sp) +80013e94: 02012c23 sw zero,56(sp) +80013e98: 02012a23 sw zero,52(sp) +80013e9c: 02012823 sw zero,48(sp) +80013ea0: 03c10793 addi a5,sp,60 +80013ea4: 0007a703 lw a4,0(a5) +80013ea8: ffc7a683 lw a3,-4(a5) +80013eac: ffc78793 addi a5,a5,-4 +80013eb0: 00371713 slli a4,a4,0x3 +80013eb4: 01d6d693 srli a3,a3,0x1d +80013eb8: 00d76733 or a4,a4,a3 +80013ebc: 00e7a223 sw a4,4(a5) +80013ec0: feff92e3 bne t6,a5,80013ea4 <__subtf3+0x11a0> +80013ec4: fc8ff06f j 8001368c <__subtf3+0x988> +80013ec8: 40f70eb3 sub t4,a4,a5 +80013ecc: 410609b3 sub s3,a2,a6 +80013ed0: 01d732b3 sltu t0,a4,t4 +80013ed4: 01363f33 sltu t5,a2,s3 +80013ed8: 405982b3 sub t0,s3,t0 +80013edc: 00000f93 li t6,0 +80013ee0: 01d77463 bgeu a4,t4,80013ee8 <__subtf3+0x11e4> +80013ee4: 0019bf93 seqz t6,s3 +80013ee8: 411583b3 sub t2,a1,a7 +80013eec: 01efefb3 or t6,t6,t5 +80013ef0: 0075bb33 sltu s6,a1,t2 +80013ef4: 41f38ab3 sub s5,t2,t6 +80013ef8: 00000a13 li s4,0 +80013efc: 000f8463 beqz t6,80013f04 <__subtf3+0x1200> +80013f00: 0013ba13 seqz s4,t2 +80013f04: 40d50f33 sub t5,a0,a3 +80013f08: 016a6a33 or s4,s4,s6 +80013f0c: 414f0f33 sub t5,t5,s4 +80013f10: 03e12e23 sw t5,60(sp) +80013f14: 03512c23 sw s5,56(sp) +80013f18: 02512a23 sw t0,52(sp) +80013f1c: 03d12823 sw t4,48(sp) +80013f20: 00cf1f93 slli t6,t5,0xc +80013f24: 0c0fd063 bgez t6,80013fe4 <__subtf3+0x12e0> +80013f28: 40c80633 sub a2,a6,a2 +80013f2c: 40e78733 sub a4,a5,a4 +80013f30: 00c83eb3 sltu t4,a6,a2 +80013f34: 00e7b833 sltu a6,a5,a4 +80013f38: 41060633 sub a2,a2,a6 +80013f3c: 00000813 li a6,0 +80013f40: 00e7f463 bgeu a5,a4,80013f48 <__subtf3+0x1244> +80013f44: 0019b813 seqz a6,s3 +80013f48: 40b885b3 sub a1,a7,a1 +80013f4c: 01d86833 or a6,a6,t4 +80013f50: 00b8b8b3 sltu a7,a7,a1 +80013f54: 410585b3 sub a1,a1,a6 +80013f58: 00080463 beqz a6,80013f60 <__subtf3+0x125c> +80013f5c: 0013b313 seqz t1,t2 +80013f60: 40a68533 sub a0,a3,a0 +80013f64: 011366b3 or a3,t1,a7 +80013f68: 40d506b3 sub a3,a0,a3 +80013f6c: 02d12e23 sw a3,60(sp) +80013f70: 02b12c23 sw a1,56(sp) +80013f74: 02c12a23 sw a2,52(sp) +80013f78: 02e12823 sw a4,48(sp) +80013f7c: 000e0913 mv s2,t3 +80013f80: 03c12503 lw a0,60(sp) +80013f84: 06050a63 beqz a0,80013ff8 <__subtf3+0x12f4> +80013f88: 241000ef jal ra,800149c8 <__clzsi2> +80013f8c: ff450793 addi a5,a0,-12 +80013f90: 02000613 li a2,32 +80013f94: 01f7f693 andi a3,a5,31 +80013f98: 02c7c733 div a4,a5,a2 +80013f9c: 08068a63 beqz a3,80014030 <__subtf3+0x132c> +80013fa0: ffc00693 li a3,-4 +80013fa4: 03010313 addi t1,sp,48 +80013fa8: 00271513 slli a0,a4,0x2 +80013fac: 02c7e833 rem a6,a5,a2 +80013fb0: 02d706b3 mul a3,a4,a3 +80013fb4: 41060633 sub a2,a2,a6 +80013fb8: 00c68693 addi a3,a3,12 +80013fbc: 00d306b3 add a3,t1,a3 +80013fc0: 0ad31063 bne t1,a3,80014060 <__subtf3+0x135c> +80013fc4: 04010693 addi a3,sp,64 +80013fc8: 00a68533 add a0,a3,a0 +80013fcc: 03012683 lw a3,48(sp) 80013fd0: fff70713 addi a4,a4,-1 -80013fd4: fec716e3 bne a4,a2,80013fc0 <__subtf3+0x1380> -80013fd8: 1487cc63 blt a5,s0,80014130 <__subtf3+0x14f0> -80013fdc: 40878433 sub s0,a5,s0 -80013fe0: 00140413 addi s0,s0,1 -80013fe4: 02000713 li a4,32 -80013fe8: 02e44533 div a0,s0,a4 -80013fec: 00000813 li a6,0 -80013ff0: 00000793 li a5,0 -80013ff4: 04a7ce63 blt a5,a0,80014050 <__subtf3+0x1410> -80013ff8: 00050613 mv a2,a0 -80013ffc: 00055463 bgez a0,80014004 <__subtf3+0x13c4> -80014000: 00000613 li a2,0 -80014004: 01f47793 andi a5,s0,31 -80014008: 00251693 slli a3,a0,0x2 -8001400c: 06079063 bnez a5,8001406c <__subtf3+0x142c> -80014010: 00300613 li a2,3 -80014014: 03010793 addi a5,sp,48 -80014018: 00000713 li a4,0 -8001401c: 40a60633 sub a2,a2,a0 -80014020: 00d785b3 add a1,a5,a3 -80014024: 0005a583 lw a1,0(a1) -80014028: 00170713 addi a4,a4,1 -8001402c: 00478793 addi a5,a5,4 -80014030: feb7ae23 sw a1,-4(a5) -80014034: fee656e3 bge a2,a4,80014020 <__subtf3+0x13e0> -80014038: 00400713 li a4,4 -8001403c: 40a70533 sub a0,a4,a0 -80014040: 00100713 li a4,1 -80014044: 08a05463 blez a0,800140cc <__subtf3+0x148c> -80014048: 00050713 mv a4,a0 -8001404c: 0800006f j 800140cc <__subtf3+0x148c> -80014050: 00279713 slli a4,a5,0x2 -80014054: 03010693 addi a3,sp,48 -80014058: 00e68733 add a4,a3,a4 -8001405c: 00072703 lw a4,0(a4) -80014060: 00178793 addi a5,a5,1 -80014064: 00e86833 or a6,a6,a4 -80014068: f8dff06f j 80013ff4 <__subtf3+0x13b4> -8001406c: 02000593 li a1,32 -80014070: 02b46433 rem s0,s0,a1 -80014074: 04010793 addi a5,sp,64 -80014078: 00261613 slli a2,a2,0x2 -8001407c: 00c78633 add a2,a5,a2 -80014080: ff062783 lw a5,-16(a2) -80014084: 00000713 li a4,0 -80014088: 408585b3 sub a1,a1,s0 -8001408c: 00b797b3 sll a5,a5,a1 -80014090: 00f86833 or a6,a6,a5 -80014094: 03010793 addi a5,sp,48 -80014098: 00d786b3 add a3,a5,a3 -8001409c: 00300793 li a5,3 -800140a0: 40a787b3 sub a5,a5,a0 -800140a4: 00468693 addi a3,a3,4 -800140a8: 02f74663 blt a4,a5,800140d4 <__subtf3+0x1494> -800140ac: 04010693 addi a3,sp,64 -800140b0: 00279793 slli a5,a5,0x2 -800140b4: 00f687b3 add a5,a3,a5 -800140b8: 03c12683 lw a3,60(sp) -800140bc: 00400713 li a4,4 -800140c0: 40a70733 sub a4,a4,a0 -800140c4: 0086d433 srl s0,a3,s0 -800140c8: fe87a823 sw s0,-16(a5) -800140cc: 00300693 li a3,3 -800140d0: 0440006f j 80014114 <__subtf3+0x14d4> -800140d4: 00271893 slli a7,a4,0x2 -800140d8: 03010613 addi a2,sp,48 -800140dc: 0006a303 lw t1,0(a3) -800140e0: 011608b3 add a7,a2,a7 -800140e4: ffc6a603 lw a2,-4(a3) -800140e8: 00b31333 sll t1,t1,a1 +80013fd4: 010696b3 sll a3,a3,a6 +80013fd8: fed52823 sw a3,-16(a0) +80013fdc: fff00613 li a2,-1 +80013fe0: 0b80006f j 80014098 <__subtf3+0x1394> +80013fe4: 005eeeb3 or t4,t4,t0 +80013fe8: 015eeeb3 or t4,t4,s5 +80013fec: 01eeeeb3 or t4,t4,t5 +80013ff0: d20e8ee3 beqz t4,80013d2c <__subtf3+0x1028> +80013ff4: f8dff06f j 80013f80 <__subtf3+0x127c> +80013ff8: 03812503 lw a0,56(sp) +80013ffc: 00050863 beqz a0,8001400c <__subtf3+0x1308> +80014000: 1c9000ef jal ra,800149c8 <__clzsi2> +80014004: 02050513 addi a0,a0,32 +80014008: f85ff06f j 80013f8c <__subtf3+0x1288> +8001400c: 03412503 lw a0,52(sp) +80014010: 00050863 beqz a0,80014020 <__subtf3+0x131c> +80014014: 1b5000ef jal ra,800149c8 <__clzsi2> +80014018: 04050513 addi a0,a0,64 +8001401c: f71ff06f j 80013f8c <__subtf3+0x1288> +80014020: 03012503 lw a0,48(sp) +80014024: 1a5000ef jal ra,800149c8 <__clzsi2> +80014028: 06050513 addi a0,a0,96 +8001402c: f61ff06f j 80013f8c <__subtf3+0x1288> +80014030: ffc00593 li a1,-4 +80014034: 02b705b3 mul a1,a4,a1 +80014038: 03c10693 addi a3,sp,60 +8001403c: 00300613 li a2,3 +80014040: 00b68533 add a0,a3,a1 +80014044: 00052503 lw a0,0(a0) +80014048: fff60613 addi a2,a2,-1 +8001404c: ffc68693 addi a3,a3,-4 +80014050: 00a6a223 sw a0,4(a3) +80014054: fee656e3 bge a2,a4,80014040 <__subtf3+0x133c> +80014058: fff70713 addi a4,a4,-1 +8001405c: f81ff06f j 80013fdc <__subtf3+0x12d8> +80014060: ffc6a583 lw a1,-4(a3) +80014064: 0006a883 lw a7,0(a3) +80014068: 00a68e33 add t3,a3,a0 +8001406c: 00c5d5b3 srl a1,a1,a2 +80014070: 010898b3 sll a7,a7,a6 +80014074: 0115e5b3 or a1,a1,a7 +80014078: 00be2023 sw a1,0(t3) +8001407c: ffc68693 addi a3,a3,-4 +80014080: f41ff06f j 80013fc0 <__subtf3+0x12bc> +80014084: 00271693 slli a3,a4,0x2 +80014088: 03010593 addi a1,sp,48 +8001408c: 00d586b3 add a3,a1,a3 +80014090: 0006a023 sw zero,0(a3) +80014094: fff70713 addi a4,a4,-1 +80014098: fec716e3 bne a4,a2,80014084 <__subtf3+0x1380> +8001409c: 1487cc63 blt a5,s0,800141f4 <__subtf3+0x14f0> +800140a0: 40878433 sub s0,a5,s0 +800140a4: 00140413 addi s0,s0,1 +800140a8: 02000713 li a4,32 +800140ac: 02e44533 div a0,s0,a4 +800140b0: 00000813 li a6,0 +800140b4: 00000793 li a5,0 +800140b8: 04a7ce63 blt a5,a0,80014114 <__subtf3+0x1410> +800140bc: 00050613 mv a2,a0 +800140c0: 00055463 bgez a0,800140c8 <__subtf3+0x13c4> +800140c4: 00000613 li a2,0 +800140c8: 01f47793 andi a5,s0,31 +800140cc: 00251693 slli a3,a0,0x2 +800140d0: 06079063 bnez a5,80014130 <__subtf3+0x142c> +800140d4: 00300613 li a2,3 +800140d8: 03010793 addi a5,sp,48 +800140dc: 00000713 li a4,0 +800140e0: 40a60633 sub a2,a2,a0 +800140e4: 00d785b3 add a1,a5,a3 +800140e8: 0005a583 lw a1,0(a1) 800140ec: 00170713 addi a4,a4,1 -800140f0: 00865633 srl a2,a2,s0 -800140f4: 00666633 or a2,a2,t1 -800140f8: 00c8a023 sw a2,0(a7) -800140fc: fa9ff06f j 800140a4 <__subtf3+0x1464> -80014100: 00271793 slli a5,a4,0x2 -80014104: 03010613 addi a2,sp,48 -80014108: 00f607b3 add a5,a2,a5 -8001410c: 0007a023 sw zero,0(a5) -80014110: 00170713 addi a4,a4,1 -80014114: fee6d6e3 bge a3,a4,80014100 <__subtf3+0x14c0> -80014118: 03012703 lw a4,48(sp) -8001411c: 010037b3 snez a5,a6 -80014120: 00000413 li s0,0 -80014124: 00f767b3 or a5,a4,a5 -80014128: 02f12823 sw a5,48(sp) -8001412c: d45fe06f j 80012e70 <__subtf3+0x230> -80014130: 40f40433 sub s0,s0,a5 -80014134: 03c12783 lw a5,60(sp) -80014138: fff80737 lui a4,0xfff80 -8001413c: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693cf> -80014140: 00e7f7b3 and a5,a5,a4 -80014144: 02f12e23 sw a5,60(sp) -80014148: d29fe06f j 80012e70 <__subtf3+0x230> -8001414c: 02012e23 sw zero,60(sp) -80014150: 02012c23 sw zero,56(sp) -80014154: 02012a23 sw zero,52(sp) -80014158: 02012823 sw zero,48(sp) -8001415c: d95fe06f j 80012ef0 <__subtf3+0x2b0> +800140f0: 00478793 addi a5,a5,4 +800140f4: feb7ae23 sw a1,-4(a5) +800140f8: fee656e3 bge a2,a4,800140e4 <__subtf3+0x13e0> +800140fc: 00400713 li a4,4 +80014100: 40a70533 sub a0,a4,a0 +80014104: 00100713 li a4,1 +80014108: 08a05463 blez a0,80014190 <__subtf3+0x148c> +8001410c: 00050713 mv a4,a0 +80014110: 0800006f j 80014190 <__subtf3+0x148c> +80014114: 00279713 slli a4,a5,0x2 +80014118: 03010693 addi a3,sp,48 +8001411c: 00e68733 add a4,a3,a4 +80014120: 00072703 lw a4,0(a4) +80014124: 00178793 addi a5,a5,1 +80014128: 00e86833 or a6,a6,a4 +8001412c: f8dff06f j 800140b8 <__subtf3+0x13b4> +80014130: 02000593 li a1,32 +80014134: 02b46433 rem s0,s0,a1 +80014138: 04010793 addi a5,sp,64 +8001413c: 00261613 slli a2,a2,0x2 +80014140: 00c78633 add a2,a5,a2 +80014144: ff062783 lw a5,-16(a2) +80014148: 00000713 li a4,0 +8001414c: 408585b3 sub a1,a1,s0 +80014150: 00b797b3 sll a5,a5,a1 +80014154: 00f86833 or a6,a6,a5 +80014158: 03010793 addi a5,sp,48 +8001415c: 00d786b3 add a3,a5,a3 +80014160: 00300793 li a5,3 +80014164: 40a787b3 sub a5,a5,a0 +80014168: 00468693 addi a3,a3,4 +8001416c: 02f74663 blt a4,a5,80014198 <__subtf3+0x1494> +80014170: 04010693 addi a3,sp,64 +80014174: 00279793 slli a5,a5,0x2 +80014178: 00f687b3 add a5,a3,a5 +8001417c: 03c12683 lw a3,60(sp) +80014180: 00400713 li a4,4 +80014184: 40a70733 sub a4,a4,a0 +80014188: 0086d433 srl s0,a3,s0 +8001418c: fe87a823 sw s0,-16(a5) +80014190: 00300693 li a3,3 +80014194: 0440006f j 800141d8 <__subtf3+0x14d4> +80014198: 00271893 slli a7,a4,0x2 +8001419c: 03010613 addi a2,sp,48 +800141a0: 0006a303 lw t1,0(a3) +800141a4: 011608b3 add a7,a2,a7 +800141a8: ffc6a603 lw a2,-4(a3) +800141ac: 00b31333 sll t1,t1,a1 +800141b0: 00170713 addi a4,a4,1 +800141b4: 00865633 srl a2,a2,s0 +800141b8: 00666633 or a2,a2,t1 +800141bc: 00c8a023 sw a2,0(a7) +800141c0: fa9ff06f j 80014168 <__subtf3+0x1464> +800141c4: 00271793 slli a5,a4,0x2 +800141c8: 03010613 addi a2,sp,48 +800141cc: 00f607b3 add a5,a2,a5 +800141d0: 0007a023 sw zero,0(a5) +800141d4: 00170713 addi a4,a4,1 +800141d8: fee6d6e3 bge a3,a4,800141c4 <__subtf3+0x14c0> +800141dc: 03012703 lw a4,48(sp) +800141e0: 010037b3 snez a5,a6 +800141e4: 00000413 li s0,0 +800141e8: 00f767b3 or a5,a4,a5 +800141ec: 02f12823 sw a5,48(sp) +800141f0: d45fe06f j 80012f34 <__subtf3+0x230> +800141f4: 40f40433 sub s0,s0,a5 +800141f8: 03c12783 lw a5,60(sp) +800141fc: fff80737 lui a4,0xfff80 +80014200: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> +80014204: 00e7f7b3 and a5,a5,a4 +80014208: 02f12e23 sw a5,60(sp) +8001420c: d29fe06f j 80012f34 <__subtf3+0x230> +80014210: 02012e23 sw zero,60(sp) +80014214: 02012c23 sw zero,56(sp) +80014218: 02012a23 sw zero,52(sp) +8001421c: 02012823 sw zero,48(sp) +80014220: d95fe06f j 80012fb4 <__subtf3+0x2b0> -80014160 <__fixtfsi>: -80014160: 00852783 lw a5,8(a0) -80014164: 00452703 lw a4,4(a0) -80014168: 00c52683 lw a3,12(a0) -8001416c: 00052603 lw a2,0(a0) -80014170: fe010113 addi sp,sp,-32 -80014174: 00e12223 sw a4,4(sp) -80014178: 00f12423 sw a5,8(sp) -8001417c: 00f12c23 sw a5,24(sp) -80014180: 00004737 lui a4,0x4 -80014184: 00169793 slli a5,a3,0x1 -80014188: 0117d593 srli a1,a5,0x11 -8001418c: 00c12023 sw a2,0(sp) -80014190: 00d12623 sw a3,12(sp) -80014194: 00c12823 sw a2,16(sp) -80014198: ffe70793 addi a5,a4,-2 # 3ffe <_start-0x7fffc002> -8001419c: 00000513 li a0,0 -800141a0: 00b7de63 bge a5,a1,800141bc <__fixtfsi+0x5c> -800141a4: 01d70793 addi a5,a4,29 -800141a8: 01f6d813 srli a6,a3,0x1f -800141ac: 00b7dc63 bge a5,a1,800141c4 <__fixtfsi+0x64> -800141b0: 80000537 lui a0,0x80000 -800141b4: fff54513 not a0,a0 -800141b8: 00a80533 add a0,a6,a0 -800141bc: 02010113 addi sp,sp,32 -800141c0: 00008067 ret -800141c4: 01069693 slli a3,a3,0x10 -800141c8: 000107b7 lui a5,0x10 -800141cc: 0106d693 srli a3,a3,0x10 -800141d0: 00f6e6b3 or a3,a3,a5 -800141d4: 06f70793 addi a5,a4,111 -800141d8: 40b787b3 sub a5,a5,a1 -800141dc: 4057d713 srai a4,a5,0x5 -800141e0: 00d12e23 sw a3,28(sp) -800141e4: 01f7f793 andi a5,a5,31 -800141e8: 04078863 beqz a5,80014238 <__fixtfsi+0xd8> -800141ec: 02000513 li a0,32 -800141f0: ffe70893 addi a7,a4,-2 -800141f4: 40f50533 sub a0,a0,a5 -800141f8: 00271713 slli a4,a4,0x2 -800141fc: 02010e13 addi t3,sp,32 -80014200: 00a69533 sll a0,a3,a0 -80014204: 00000313 li t1,0 -80014208: 00000593 li a1,0 -8001420c: 0018b893 seqz a7,a7 -80014210: 00ee0733 add a4,t3,a4 -80014214: 0515c463 blt a1,a7,8001425c <__fixtfsi+0xfc> -80014218: 00030463 beqz t1,80014220 <__fixtfsi+0xc0> -8001421c: 00c12823 sw a2,16(sp) -80014220: 00259593 slli a1,a1,0x2 -80014224: 02010713 addi a4,sp,32 -80014228: 00b705b3 add a1,a4,a1 -8001422c: 00f6d6b3 srl a3,a3,a5 -80014230: fed5a823 sw a3,-16(a1) -80014234: 0180006f j 8001424c <__fixtfsi+0xec> -80014238: 02010793 addi a5,sp,32 -8001423c: 00271713 slli a4,a4,0x2 -80014240: 00e78733 add a4,a5,a4 -80014244: ff072783 lw a5,-16(a4) -80014248: 00f12823 sw a5,16(sp) -8001424c: 01012503 lw a0,16(sp) -80014250: f60806e3 beqz a6,800141bc <__fixtfsi+0x5c> -80014254: 40a00533 neg a0,a0 -80014258: f65ff06f j 800141bc <__fixtfsi+0x5c> -8001425c: ff072603 lw a2,-16(a4) -80014260: 00100313 li t1,1 -80014264: 00100593 li a1,1 -80014268: 00f65633 srl a2,a2,a5 -8001426c: 00a66633 or a2,a2,a0 -80014270: fa5ff06f j 80014214 <__fixtfsi+0xb4> +80014224 <__fixtfsi>: +80014224: 00852783 lw a5,8(a0) +80014228: 00452703 lw a4,4(a0) +8001422c: 00c52683 lw a3,12(a0) +80014230: 00052603 lw a2,0(a0) +80014234: fe010113 addi sp,sp,-32 +80014238: 00e12223 sw a4,4(sp) +8001423c: 00f12423 sw a5,8(sp) +80014240: 00f12c23 sw a5,24(sp) +80014244: 00004737 lui a4,0x4 +80014248: 00169793 slli a5,a3,0x1 +8001424c: 0117d593 srli a1,a5,0x11 +80014250: 00c12023 sw a2,0(sp) +80014254: 00d12623 sw a3,12(sp) +80014258: 00c12823 sw a2,16(sp) +8001425c: ffe70793 addi a5,a4,-2 # 3ffe <_start-0x7fffc002> +80014260: 00000513 li a0,0 +80014264: 00b7de63 bge a5,a1,80014280 <__fixtfsi+0x5c> +80014268: 01d70793 addi a5,a4,29 +8001426c: 01f6d813 srli a6,a3,0x1f +80014270: 00b7dc63 bge a5,a1,80014288 <__fixtfsi+0x64> +80014274: 80000537 lui a0,0x80000 +80014278: fff54513 not a0,a0 +8001427c: 00a80533 add a0,a6,a0 +80014280: 02010113 addi sp,sp,32 +80014284: 00008067 ret +80014288: 01069693 slli a3,a3,0x10 +8001428c: 000107b7 lui a5,0x10 +80014290: 0106d693 srli a3,a3,0x10 +80014294: 00f6e6b3 or a3,a3,a5 +80014298: 06f70793 addi a5,a4,111 +8001429c: 40b787b3 sub a5,a5,a1 +800142a0: 4057d713 srai a4,a5,0x5 +800142a4: 00d12e23 sw a3,28(sp) +800142a8: 01f7f793 andi a5,a5,31 +800142ac: 04078863 beqz a5,800142fc <__fixtfsi+0xd8> +800142b0: 02000513 li a0,32 +800142b4: ffe70893 addi a7,a4,-2 +800142b8: 40f50533 sub a0,a0,a5 +800142bc: 00271713 slli a4,a4,0x2 +800142c0: 02010e13 addi t3,sp,32 +800142c4: 00a69533 sll a0,a3,a0 +800142c8: 00000313 li t1,0 +800142cc: 00000593 li a1,0 +800142d0: 0018b893 seqz a7,a7 +800142d4: 00ee0733 add a4,t3,a4 +800142d8: 0515c463 blt a1,a7,80014320 <__fixtfsi+0xfc> +800142dc: 00030463 beqz t1,800142e4 <__fixtfsi+0xc0> +800142e0: 00c12823 sw a2,16(sp) +800142e4: 00259593 slli a1,a1,0x2 +800142e8: 02010713 addi a4,sp,32 +800142ec: 00b705b3 add a1,a4,a1 +800142f0: 00f6d6b3 srl a3,a3,a5 +800142f4: fed5a823 sw a3,-16(a1) +800142f8: 0180006f j 80014310 <__fixtfsi+0xec> +800142fc: 02010793 addi a5,sp,32 +80014300: 00271713 slli a4,a4,0x2 +80014304: 00e78733 add a4,a5,a4 +80014308: ff072783 lw a5,-16(a4) +8001430c: 00f12823 sw a5,16(sp) +80014310: 01012503 lw a0,16(sp) +80014314: f60806e3 beqz a6,80014280 <__fixtfsi+0x5c> +80014318: 40a00533 neg a0,a0 +8001431c: f65ff06f j 80014280 <__fixtfsi+0x5c> +80014320: ff072603 lw a2,-16(a4) +80014324: 00100313 li t1,1 +80014328: 00100593 li a1,1 +8001432c: 00f65633 srl a2,a2,a5 +80014330: 00a66633 or a2,a2,a0 +80014334: fa5ff06f j 800142d8 <__fixtfsi+0xb4> -80014274 <__floatsitf>: -80014274: fd010113 addi sp,sp,-48 -80014278: 02912223 sw s1,36(sp) -8001427c: 02112623 sw ra,44(sp) -80014280: 02812423 sw s0,40(sp) -80014284: 03212023 sw s2,32(sp) -80014288: 00050493 mv s1,a0 -8001428c: 12058063 beqz a1,800143ac <__floatsitf+0x138> -80014290: 41f5d793 srai a5,a1,0x1f -80014294: 00b7c433 xor s0,a5,a1 -80014298: 40f40433 sub s0,s0,a5 -8001429c: 00040513 mv a0,s0 -800142a0: 01f5d913 srli s2,a1,0x1f -800142a4: 660000ef jal ra,80014904 <__clzsi2> -800142a8: 00004737 lui a4,0x4 -800142ac: 01e70713 addi a4,a4,30 # 401e <_start-0x7fffbfe2> -800142b0: 05150793 addi a5,a0,81 # 80000051 <__BSS_END__+0xfffe9421> -800142b4: 40a705b3 sub a1,a4,a0 -800142b8: 00812823 sw s0,16(sp) -800142bc: 4057d713 srai a4,a5,0x5 -800142c0: 00012a23 sw zero,20(sp) -800142c4: 00012c23 sw zero,24(sp) -800142c8: 00012e23 sw zero,28(sp) -800142cc: 01f7f793 andi a5,a5,31 -800142d0: 02078c63 beqz a5,80014308 <__floatsitf+0x94> -800142d4: 00200693 li a3,2 -800142d8: 0cd71663 bne a4,a3,800143a4 <__floatsitf+0x130> -800142dc: 02000693 li a3,32 -800142e0: 40f686b3 sub a3,a3,a5 -800142e4: 00d456b3 srl a3,s0,a3 -800142e8: 00d12e23 sw a3,28(sp) -800142ec: fff70693 addi a3,a4,-1 -800142f0: 02010613 addi a2,sp,32 -800142f4: 00271713 slli a4,a4,0x2 -800142f8: 00e60733 add a4,a2,a4 -800142fc: 00f417b3 sll a5,s0,a5 -80014300: fef72823 sw a5,-16(a4) -80014304: 0340006f j 80014338 <__floatsitf+0xc4> -80014308: 00300793 li a5,3 -8001430c: 40e787b3 sub a5,a5,a4 -80014310: 02010693 addi a3,sp,32 -80014314: 00279793 slli a5,a5,0x2 -80014318: 00f687b3 add a5,a3,a5 -8001431c: ff07a783 lw a5,-16(a5) # fff0 <_start-0x7fff0010> -80014320: 00200693 li a3,2 -80014324: 00f12e23 sw a5,28(sp) -80014328: 00200793 li a5,2 -8001432c: 00f71663 bne a4,a5,80014338 <__floatsitf+0xc4> -80014330: 00812c23 sw s0,24(sp) -80014334: 00100693 li a3,1 -80014338: fff00793 li a5,-1 -8001433c: 00269713 slli a4,a3,0x2 -80014340: 01010613 addi a2,sp,16 -80014344: 00e60733 add a4,a2,a4 -80014348: 00072023 sw zero,0(a4) -8001434c: fff68693 addi a3,a3,-1 -80014350: fef696e3 bne a3,a5,8001433c <__floatsitf+0xc8> -80014354: 01c12783 lw a5,28(sp) -80014358: 02c12083 lw ra,44(sp) -8001435c: 02812403 lw s0,40(sp) -80014360: 00f11623 sh a5,12(sp) -80014364: 00f91793 slli a5,s2,0xf -80014368: 00b7e5b3 or a1,a5,a1 -8001436c: 01012783 lw a5,16(sp) -80014370: 00b11723 sh a1,14(sp) -80014374: 02012903 lw s2,32(sp) -80014378: 00f4a023 sw a5,0(s1) -8001437c: 01412783 lw a5,20(sp) -80014380: 00048513 mv a0,s1 -80014384: 00f4a223 sw a5,4(s1) -80014388: 01812783 lw a5,24(sp) -8001438c: 00f4a423 sw a5,8(s1) -80014390: 00c12783 lw a5,12(sp) -80014394: 00f4a623 sw a5,12(s1) -80014398: 02412483 lw s1,36(sp) -8001439c: 03010113 addi sp,sp,48 -800143a0: 00008067 ret -800143a4: 00300713 li a4,3 -800143a8: f45ff06f j 800142ec <__floatsitf+0x78> -800143ac: 00012e23 sw zero,28(sp) -800143b0: 00012c23 sw zero,24(sp) -800143b4: 00012a23 sw zero,20(sp) -800143b8: 00012823 sw zero,16(sp) -800143bc: 00000913 li s2,0 -800143c0: f95ff06f j 80014354 <__floatsitf+0xe0> +80014338 <__floatsitf>: +80014338: fd010113 addi sp,sp,-48 +8001433c: 02912223 sw s1,36(sp) +80014340: 02112623 sw ra,44(sp) +80014344: 02812423 sw s0,40(sp) +80014348: 03212023 sw s2,32(sp) +8001434c: 00050493 mv s1,a0 +80014350: 12058063 beqz a1,80014470 <__floatsitf+0x138> +80014354: 41f5d793 srai a5,a1,0x1f +80014358: 00b7c433 xor s0,a5,a1 +8001435c: 40f40433 sub s0,s0,a5 +80014360: 00040513 mv a0,s0 +80014364: 01f5d913 srli s2,a1,0x1f +80014368: 660000ef jal ra,800149c8 <__clzsi2> +8001436c: 00004737 lui a4,0x4 +80014370: 01e70713 addi a4,a4,30 # 401e <_start-0x7fffbfe2> +80014374: 05150793 addi a5,a0,81 # 80000051 <__BSS_END__+0xfffe9415> +80014378: 40a705b3 sub a1,a4,a0 +8001437c: 00812823 sw s0,16(sp) +80014380: 4057d713 srai a4,a5,0x5 +80014384: 00012a23 sw zero,20(sp) +80014388: 00012c23 sw zero,24(sp) +8001438c: 00012e23 sw zero,28(sp) +80014390: 01f7f793 andi a5,a5,31 +80014394: 02078c63 beqz a5,800143cc <__floatsitf+0x94> +80014398: 00200693 li a3,2 +8001439c: 0cd71663 bne a4,a3,80014468 <__floatsitf+0x130> +800143a0: 02000693 li a3,32 +800143a4: 40f686b3 sub a3,a3,a5 +800143a8: 00d456b3 srl a3,s0,a3 +800143ac: 00d12e23 sw a3,28(sp) +800143b0: fff70693 addi a3,a4,-1 +800143b4: 02010613 addi a2,sp,32 +800143b8: 00271713 slli a4,a4,0x2 +800143bc: 00e60733 add a4,a2,a4 +800143c0: 00f417b3 sll a5,s0,a5 +800143c4: fef72823 sw a5,-16(a4) +800143c8: 0340006f j 800143fc <__floatsitf+0xc4> +800143cc: 00300793 li a5,3 +800143d0: 40e787b3 sub a5,a5,a4 +800143d4: 02010693 addi a3,sp,32 +800143d8: 00279793 slli a5,a5,0x2 +800143dc: 00f687b3 add a5,a3,a5 +800143e0: ff07a783 lw a5,-16(a5) # fff0 <_start-0x7fff0010> +800143e4: 00200693 li a3,2 +800143e8: 00f12e23 sw a5,28(sp) +800143ec: 00200793 li a5,2 +800143f0: 00f71663 bne a4,a5,800143fc <__floatsitf+0xc4> +800143f4: 00812c23 sw s0,24(sp) +800143f8: 00100693 li a3,1 +800143fc: fff00793 li a5,-1 +80014400: 00269713 slli a4,a3,0x2 +80014404: 01010613 addi a2,sp,16 +80014408: 00e60733 add a4,a2,a4 +8001440c: 00072023 sw zero,0(a4) +80014410: fff68693 addi a3,a3,-1 +80014414: fef696e3 bne a3,a5,80014400 <__floatsitf+0xc8> +80014418: 01c12783 lw a5,28(sp) +8001441c: 02c12083 lw ra,44(sp) +80014420: 02812403 lw s0,40(sp) +80014424: 00f11623 sh a5,12(sp) +80014428: 00f91793 slli a5,s2,0xf +8001442c: 00b7e5b3 or a1,a5,a1 +80014430: 01012783 lw a5,16(sp) +80014434: 00b11723 sh a1,14(sp) +80014438: 02012903 lw s2,32(sp) +8001443c: 00f4a023 sw a5,0(s1) +80014440: 01412783 lw a5,20(sp) +80014444: 00048513 mv a0,s1 +80014448: 00f4a223 sw a5,4(s1) +8001444c: 01812783 lw a5,24(sp) +80014450: 00f4a423 sw a5,8(s1) +80014454: 00c12783 lw a5,12(sp) +80014458: 00f4a623 sw a5,12(s1) +8001445c: 02412483 lw s1,36(sp) +80014460: 03010113 addi sp,sp,48 +80014464: 00008067 ret +80014468: 00300713 li a4,3 +8001446c: f45ff06f j 800143b0 <__floatsitf+0x78> +80014470: 00012e23 sw zero,28(sp) +80014474: 00012c23 sw zero,24(sp) +80014478: 00012a23 sw zero,20(sp) +8001447c: 00012823 sw zero,16(sp) +80014480: 00000913 li s2,0 +80014484: f95ff06f j 80014418 <__floatsitf+0xe0> -800143c4 <__extenddftf2>: -800143c4: 01465793 srli a5,a2,0x14 -800143c8: 00c61713 slli a4,a2,0xc -800143cc: 7ff7f793 andi a5,a5,2047 -800143d0: fd010113 addi sp,sp,-48 -800143d4: 00c75713 srli a4,a4,0xc -800143d8: 00178693 addi a3,a5,1 -800143dc: 02812423 sw s0,40(sp) -800143e0: 02912223 sw s1,36(sp) -800143e4: 03212023 sw s2,32(sp) -800143e8: 02112623 sw ra,44(sp) -800143ec: 00b12823 sw a1,16(sp) -800143f0: 00e12a23 sw a4,20(sp) -800143f4: 00012e23 sw zero,28(sp) -800143f8: 00012c23 sw zero,24(sp) -800143fc: 7fe6f693 andi a3,a3,2046 -80014400: 00050913 mv s2,a0 -80014404: 00058413 mv s0,a1 -80014408: 01f65493 srli s1,a2,0x1f -8001440c: 08068263 beqz a3,80014490 <__extenddftf2+0xcc> -80014410: 000046b7 lui a3,0x4 -80014414: c0068693 addi a3,a3,-1024 # 3c00 <_start-0x7fffc400> -80014418: 00d787b3 add a5,a5,a3 -8001441c: 0045d513 srli a0,a1,0x4 -80014420: 00475693 srli a3,a4,0x4 -80014424: 01c71713 slli a4,a4,0x1c -80014428: 00a76733 or a4,a4,a0 -8001442c: 01c59413 slli s0,a1,0x1c -80014430: 00d12e23 sw a3,28(sp) -80014434: 00e12c23 sw a4,24(sp) -80014438: 00812a23 sw s0,20(sp) -8001443c: 00012823 sw zero,16(sp) -80014440: 00f49493 slli s1,s1,0xf -80014444: 00f4e7b3 or a5,s1,a5 -80014448: 00f11723 sh a5,14(sp) -8001444c: 01012783 lw a5,16(sp) -80014450: 01c12703 lw a4,28(sp) -80014454: 02c12083 lw ra,44(sp) -80014458: 00f92023 sw a5,0(s2) -8001445c: 01412783 lw a5,20(sp) -80014460: 00e11623 sh a4,12(sp) -80014464: 02812403 lw s0,40(sp) -80014468: 00f92223 sw a5,4(s2) -8001446c: 01812783 lw a5,24(sp) -80014470: 02412483 lw s1,36(sp) -80014474: 00090513 mv a0,s2 -80014478: 00f92423 sw a5,8(s2) -8001447c: 00c12783 lw a5,12(sp) -80014480: 00f92623 sw a5,12(s2) -80014484: 02012903 lw s2,32(sp) -80014488: 03010113 addi sp,sp,48 -8001448c: 00008067 ret -80014490: 00b76533 or a0,a4,a1 -80014494: 0e079463 bnez a5,8001457c <__extenddftf2+0x1b8> -80014498: fa0504e3 beqz a0,80014440 <__extenddftf2+0x7c> -8001449c: 04070c63 beqz a4,800144f4 <__extenddftf2+0x130> -800144a0: 00070513 mv a0,a4 -800144a4: 460000ef jal ra,80014904 <__clzsi2> -800144a8: 03150593 addi a1,a0,49 -800144ac: 4055d713 srai a4,a1,0x5 -800144b0: 01f5f593 andi a1,a1,31 -800144b4: 04058663 beqz a1,80014500 <__extenddftf2+0x13c> -800144b8: ffc00693 li a3,-4 -800144bc: 02d706b3 mul a3,a4,a3 -800144c0: 01010313 addi t1,sp,16 -800144c4: 02000813 li a6,32 -800144c8: 00271613 slli a2,a4,0x2 -800144cc: 40b80833 sub a6,a6,a1 -800144d0: 00c68693 addi a3,a3,12 -800144d4: 00d306b3 add a3,t1,a3 -800144d8: 08d31063 bne t1,a3,80014558 <__extenddftf2+0x194> -800144dc: 02010793 addi a5,sp,32 -800144e0: 00c78633 add a2,a5,a2 -800144e4: 00b415b3 sll a1,s0,a1 -800144e8: fff70713 addi a4,a4,-1 -800144ec: feb62823 sw a1,-16(a2) -800144f0: 03c0006f j 8001452c <__extenddftf2+0x168> -800144f4: 410000ef jal ra,80014904 <__clzsi2> -800144f8: 02050513 addi a0,a0,32 -800144fc: fadff06f j 800144a8 <__extenddftf2+0xe4> -80014500: ffc00613 li a2,-4 -80014504: 02c70633 mul a2,a4,a2 -80014508: 01c10793 addi a5,sp,28 -8001450c: 00300693 li a3,3 -80014510: 00c785b3 add a1,a5,a2 -80014514: 0005a583 lw a1,0(a1) -80014518: fff68693 addi a3,a3,-1 -8001451c: ffc78793 addi a5,a5,-4 -80014520: 00b7a223 sw a1,4(a5) -80014524: fee6d6e3 bge a3,a4,80014510 <__extenddftf2+0x14c> -80014528: fff70713 addi a4,a4,-1 -8001452c: fff00693 li a3,-1 -80014530: 00271793 slli a5,a4,0x2 -80014534: 01010613 addi a2,sp,16 -80014538: 00f607b3 add a5,a2,a5 -8001453c: 0007a023 sw zero,0(a5) -80014540: fff70713 addi a4,a4,-1 -80014544: fed716e3 bne a4,a3,80014530 <__extenddftf2+0x16c> -80014548: 000047b7 lui a5,0x4 -8001454c: c0c78793 addi a5,a5,-1012 # 3c0c <_start-0x7fffc3f4> -80014550: 40a787b3 sub a5,a5,a0 -80014554: eedff06f j 80014440 <__extenddftf2+0x7c> -80014558: ffc6a783 lw a5,-4(a3) -8001455c: 0006a883 lw a7,0(a3) -80014560: 00c68e33 add t3,a3,a2 -80014564: 0107d7b3 srl a5,a5,a6 -80014568: 00b898b3 sll a7,a7,a1 -8001456c: 0117e7b3 or a5,a5,a7 -80014570: 00fe2023 sw a5,0(t3) -80014574: ffc68693 addi a3,a3,-4 -80014578: f61ff06f j 800144d8 <__extenddftf2+0x114> -8001457c: 000087b7 lui a5,0x8 -80014580: 02050863 beqz a0,800145b0 <__extenddftf2+0x1ec> -80014584: 01c71793 slli a5,a4,0x1c -80014588: 0045d693 srli a3,a1,0x4 -8001458c: 00d7e7b3 or a5,a5,a3 -80014590: 00f12c23 sw a5,24(sp) -80014594: 00475713 srli a4,a4,0x4 -80014598: 000087b7 lui a5,0x8 -8001459c: 01c59413 slli s0,a1,0x1c -800145a0: 00f76733 or a4,a4,a5 -800145a4: 00812a23 sw s0,20(sp) -800145a8: 00012823 sw zero,16(sp) -800145ac: 00e12e23 sw a4,28(sp) -800145b0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800145b4: e8dff06f j 80014440 <__extenddftf2+0x7c> +80014488 <__extenddftf2>: +80014488: 01465793 srli a5,a2,0x14 +8001448c: 00c61713 slli a4,a2,0xc +80014490: 7ff7f793 andi a5,a5,2047 +80014494: fd010113 addi sp,sp,-48 +80014498: 00c75713 srli a4,a4,0xc +8001449c: 00178693 addi a3,a5,1 +800144a0: 02812423 sw s0,40(sp) +800144a4: 02912223 sw s1,36(sp) +800144a8: 03212023 sw s2,32(sp) +800144ac: 02112623 sw ra,44(sp) +800144b0: 00b12823 sw a1,16(sp) +800144b4: 00e12a23 sw a4,20(sp) +800144b8: 00012e23 sw zero,28(sp) +800144bc: 00012c23 sw zero,24(sp) +800144c0: 7fe6f693 andi a3,a3,2046 +800144c4: 00050913 mv s2,a0 +800144c8: 00058413 mv s0,a1 +800144cc: 01f65493 srli s1,a2,0x1f +800144d0: 08068263 beqz a3,80014554 <__extenddftf2+0xcc> +800144d4: 000046b7 lui a3,0x4 +800144d8: c0068693 addi a3,a3,-1024 # 3c00 <_start-0x7fffc400> +800144dc: 00d787b3 add a5,a5,a3 +800144e0: 0045d513 srli a0,a1,0x4 +800144e4: 00475693 srli a3,a4,0x4 +800144e8: 01c71713 slli a4,a4,0x1c +800144ec: 00a76733 or a4,a4,a0 +800144f0: 01c59413 slli s0,a1,0x1c +800144f4: 00d12e23 sw a3,28(sp) +800144f8: 00e12c23 sw a4,24(sp) +800144fc: 00812a23 sw s0,20(sp) +80014500: 00012823 sw zero,16(sp) +80014504: 00f49493 slli s1,s1,0xf +80014508: 00f4e7b3 or a5,s1,a5 +8001450c: 00f11723 sh a5,14(sp) +80014510: 01012783 lw a5,16(sp) +80014514: 01c12703 lw a4,28(sp) +80014518: 02c12083 lw ra,44(sp) +8001451c: 00f92023 sw a5,0(s2) +80014520: 01412783 lw a5,20(sp) +80014524: 00e11623 sh a4,12(sp) +80014528: 02812403 lw s0,40(sp) +8001452c: 00f92223 sw a5,4(s2) +80014530: 01812783 lw a5,24(sp) +80014534: 02412483 lw s1,36(sp) +80014538: 00090513 mv a0,s2 +8001453c: 00f92423 sw a5,8(s2) +80014540: 00c12783 lw a5,12(sp) +80014544: 00f92623 sw a5,12(s2) +80014548: 02012903 lw s2,32(sp) +8001454c: 03010113 addi sp,sp,48 +80014550: 00008067 ret +80014554: 00b76533 or a0,a4,a1 +80014558: 0e079463 bnez a5,80014640 <__extenddftf2+0x1b8> +8001455c: fa0504e3 beqz a0,80014504 <__extenddftf2+0x7c> +80014560: 04070c63 beqz a4,800145b8 <__extenddftf2+0x130> +80014564: 00070513 mv a0,a4 +80014568: 460000ef jal ra,800149c8 <__clzsi2> +8001456c: 03150593 addi a1,a0,49 +80014570: 4055d713 srai a4,a1,0x5 +80014574: 01f5f593 andi a1,a1,31 +80014578: 04058663 beqz a1,800145c4 <__extenddftf2+0x13c> +8001457c: ffc00693 li a3,-4 +80014580: 02d706b3 mul a3,a4,a3 +80014584: 01010313 addi t1,sp,16 +80014588: 02000813 li a6,32 +8001458c: 00271613 slli a2,a4,0x2 +80014590: 40b80833 sub a6,a6,a1 +80014594: 00c68693 addi a3,a3,12 +80014598: 00d306b3 add a3,t1,a3 +8001459c: 08d31063 bne t1,a3,8001461c <__extenddftf2+0x194> +800145a0: 02010793 addi a5,sp,32 +800145a4: 00c78633 add a2,a5,a2 +800145a8: 00b415b3 sll a1,s0,a1 +800145ac: fff70713 addi a4,a4,-1 +800145b0: feb62823 sw a1,-16(a2) +800145b4: 03c0006f j 800145f0 <__extenddftf2+0x168> +800145b8: 410000ef jal ra,800149c8 <__clzsi2> +800145bc: 02050513 addi a0,a0,32 +800145c0: fadff06f j 8001456c <__extenddftf2+0xe4> +800145c4: ffc00613 li a2,-4 +800145c8: 02c70633 mul a2,a4,a2 +800145cc: 01c10793 addi a5,sp,28 +800145d0: 00300693 li a3,3 +800145d4: 00c785b3 add a1,a5,a2 +800145d8: 0005a583 lw a1,0(a1) +800145dc: fff68693 addi a3,a3,-1 +800145e0: ffc78793 addi a5,a5,-4 +800145e4: 00b7a223 sw a1,4(a5) +800145e8: fee6d6e3 bge a3,a4,800145d4 <__extenddftf2+0x14c> +800145ec: fff70713 addi a4,a4,-1 +800145f0: fff00693 li a3,-1 +800145f4: 00271793 slli a5,a4,0x2 +800145f8: 01010613 addi a2,sp,16 +800145fc: 00f607b3 add a5,a2,a5 +80014600: 0007a023 sw zero,0(a5) +80014604: fff70713 addi a4,a4,-1 +80014608: fed716e3 bne a4,a3,800145f4 <__extenddftf2+0x16c> +8001460c: 000047b7 lui a5,0x4 +80014610: c0c78793 addi a5,a5,-1012 # 3c0c <_start-0x7fffc3f4> +80014614: 40a787b3 sub a5,a5,a0 +80014618: eedff06f j 80014504 <__extenddftf2+0x7c> +8001461c: ffc6a783 lw a5,-4(a3) +80014620: 0006a883 lw a7,0(a3) +80014624: 00c68e33 add t3,a3,a2 +80014628: 0107d7b3 srl a5,a5,a6 +8001462c: 00b898b3 sll a7,a7,a1 +80014630: 0117e7b3 or a5,a5,a7 +80014634: 00fe2023 sw a5,0(t3) +80014638: ffc68693 addi a3,a3,-4 +8001463c: f61ff06f j 8001459c <__extenddftf2+0x114> +80014640: 000087b7 lui a5,0x8 +80014644: 02050863 beqz a0,80014674 <__extenddftf2+0x1ec> +80014648: 01c71793 slli a5,a4,0x1c +8001464c: 0045d693 srli a3,a1,0x4 +80014650: 00d7e7b3 or a5,a5,a3 +80014654: 00f12c23 sw a5,24(sp) +80014658: 00475713 srli a4,a4,0x4 +8001465c: 000087b7 lui a5,0x8 +80014660: 01c59413 slli s0,a1,0x1c +80014664: 00f76733 or a4,a4,a5 +80014668: 00812a23 sw s0,20(sp) +8001466c: 00012823 sw zero,16(sp) +80014670: 00e12e23 sw a4,28(sp) +80014674: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80014678: e8dff06f j 80014504 <__extenddftf2+0x7c> -800145b8 <__trunctfdf2>: -800145b8: 00c52583 lw a1,12(a0) -800145bc: 00852783 lw a5,8(a0) -800145c0: 00452703 lw a4,4(a0) -800145c4: fe010113 addi sp,sp,-32 -800145c8: 00052683 lw a3,0(a0) -800145cc: 00f12423 sw a5,8(sp) -800145d0: 00f12c23 sw a5,24(sp) -800145d4: 01059793 slli a5,a1,0x10 -800145d8: 00e12223 sw a4,4(sp) -800145dc: 00e12a23 sw a4,20(sp) -800145e0: 0107d793 srli a5,a5,0x10 -800145e4: 00159713 slli a4,a1,0x1 -800145e8: 00b12623 sw a1,12(sp) -800145ec: 00d12023 sw a3,0(sp) -800145f0: 00d12823 sw a3,16(sp) -800145f4: 00f12e23 sw a5,28(sp) -800145f8: 01175713 srli a4,a4,0x11 -800145fc: 01f5d593 srli a1,a1,0x1f -80014600: 01010813 addi a6,sp,16 -80014604: 01c10613 addi a2,sp,28 -80014608: 00062783 lw a5,0(a2) -8001460c: ffc62683 lw a3,-4(a2) -80014610: ffc60613 addi a2,a2,-4 -80014614: 00379793 slli a5,a5,0x3 -80014618: 01d6d693 srli a3,a3,0x1d -8001461c: 00d7e7b3 or a5,a5,a3 -80014620: 00f62223 sw a5,4(a2) -80014624: fec812e3 bne a6,a2,80014608 <__trunctfdf2+0x50> -80014628: 01012683 lw a3,16(sp) -8001462c: 00170793 addi a5,a4,1 -80014630: 00369513 slli a0,a3,0x3 -80014634: 000086b7 lui a3,0x8 -80014638: ffe68693 addi a3,a3,-2 # 7ffe <_start-0x7fff8002> -8001463c: 00a12823 sw a0,16(sp) -80014640: 00d7f7b3 and a5,a5,a3 -80014644: 1c078463 beqz a5,8001480c <__trunctfdf2+0x254> -80014648: ffffc7b7 lui a5,0xffffc -8001464c: 40078793 addi a5,a5,1024 # ffffc400 <__BSS_END__+0x7ffe57d0> -80014650: 00f70733 add a4,a4,a5 -80014654: 7fe00793 li a5,2046 -80014658: 20e7c663 blt a5,a4,80014864 <__trunctfdf2+0x2ac> -8001465c: 06e05863 blez a4,800146cc <__trunctfdf2+0x114> -80014660: 01812803 lw a6,24(sp) -80014664: 01c12603 lw a2,28(sp) -80014668: 01412783 lw a5,20(sp) -8001466c: 01c85693 srli a3,a6,0x1c -80014670: 00461613 slli a2,a2,0x4 -80014674: 00d66633 or a2,a2,a3 -80014678: 00479693 slli a3,a5,0x4 -8001467c: 00a6e6b3 or a3,a3,a0 -80014680: 01c7d793 srli a5,a5,0x1c -80014684: 00481813 slli a6,a6,0x4 -80014688: 00d036b3 snez a3,a3 -8001468c: 0107e7b3 or a5,a5,a6 -80014690: 00f6e6b3 or a3,a3,a5 -80014694: 00c12a23 sw a2,20(sp) -80014698: 00d12823 sw a3,16(sp) -8001469c: 01012683 lw a3,16(sp) -800146a0: 01412783 lw a5,20(sp) -800146a4: 0076f613 andi a2,a3,7 -800146a8: 1c060463 beqz a2,80014870 <__trunctfdf2+0x2b8> -800146ac: 00f6f613 andi a2,a3,15 -800146b0: 00400513 li a0,4 -800146b4: 1aa60e63 beq a2,a0,80014870 <__trunctfdf2+0x2b8> -800146b8: 00468613 addi a2,a3,4 -800146bc: 00d636b3 sltu a3,a2,a3 -800146c0: 00d787b3 add a5,a5,a3 -800146c4: 00060693 mv a3,a2 -800146c8: 1a80006f j 80014870 <__trunctfdf2+0x2b8> -800146cc: fcc00793 li a5,-52 -800146d0: 00f75c63 bge a4,a5,800146e8 <__trunctfdf2+0x130> -800146d4: 00012a23 sw zero,20(sp) -800146d8: 00100793 li a5,1 -800146dc: 00f12823 sw a5,16(sp) -800146e0: 00000713 li a4,0 -800146e4: fb9ff06f j 8001469c <__trunctfdf2+0xe4> -800146e8: 01c12783 lw a5,28(sp) -800146ec: 00080f37 lui t5,0x80 -800146f0: 03d00693 li a3,61 -800146f4: 00ff6f33 or t5,t5,a5 -800146f8: 40e686b3 sub a3,a3,a4 -800146fc: 01e12e23 sw t5,28(sp) -80014700: 4056de93 srai t4,a3,0x5 -80014704: 00080713 mv a4,a6 -80014708: 00000793 li a5,0 -8001470c: 00000e13 li t3,0 -80014710: 00072503 lw a0,0(a4) -80014714: 00178793 addi a5,a5,1 -80014718: 00470713 addi a4,a4,4 -8001471c: 00ae6e33 or t3,t3,a0 -80014720: fefe98e3 bne t4,a5,80014710 <__trunctfdf2+0x158> -80014724: 01f6f713 andi a4,a3,31 -80014728: 002e9693 slli a3,t4,0x2 -8001472c: 04071063 bnez a4,8001476c <__trunctfdf2+0x1b4> -80014730: 00300713 li a4,3 -80014734: 00000793 li a5,0 -80014738: 41d70733 sub a4,a4,t4 -8001473c: 00d60533 add a0,a2,a3 -80014740: 00052503 lw a0,0(a0) -80014744: 00178793 addi a5,a5,1 -80014748: 00460613 addi a2,a2,4 -8001474c: fea62e23 sw a0,-4(a2) -80014750: fef756e3 bge a4,a5,8001473c <__trunctfdf2+0x184> -80014754: 00400713 li a4,4 -80014758: 41d70733 sub a4,a4,t4 -8001475c: 00100793 li a5,1 -80014760: 04e05e63 blez a4,800147bc <__trunctfdf2+0x204> -80014764: 00070793 mv a5,a4 -80014768: 0540006f j 800147bc <__trunctfdf2+0x204> -8001476c: 02010793 addi a5,sp,32 -80014770: 00d787b3 add a5,a5,a3 -80014774: ff07a783 lw a5,-16(a5) -80014778: 02000313 li t1,32 -8001477c: 40e30333 sub t1,t1,a4 -80014780: 006797b3 sll a5,a5,t1 -80014784: 00d80633 add a2,a6,a3 -80014788: 00300693 li a3,3 -8001478c: 00fe6e33 or t3,t3,a5 -80014790: 00000893 li a7,0 -80014794: 41d686b3 sub a3,a3,t4 -80014798: 00460613 addi a2,a2,4 -8001479c: 04d8c463 blt a7,a3,800147e4 <__trunctfdf2+0x22c> -800147a0: 00269693 slli a3,a3,0x2 -800147a4: 02010613 addi a2,sp,32 -800147a8: 00400793 li a5,4 -800147ac: 00d606b3 add a3,a2,a3 -800147b0: 00ef5733 srl a4,t5,a4 -800147b4: 41d787b3 sub a5,a5,t4 -800147b8: fee6a823 sw a4,-16(a3) -800147bc: 00400693 li a3,4 -800147c0: 00279713 slli a4,a5,0x2 -800147c4: 00e80733 add a4,a6,a4 -800147c8: 00072023 sw zero,0(a4) -800147cc: 00178793 addi a5,a5,1 -800147d0: fed798e3 bne a5,a3,800147c0 <__trunctfdf2+0x208> -800147d4: 01012703 lw a4,16(sp) -800147d8: 01c037b3 snez a5,t3 -800147dc: 00f767b3 or a5,a4,a5 -800147e0: efdff06f j 800146dc <__trunctfdf2+0x124> -800147e4: ffc62503 lw a0,-4(a2) -800147e8: 00062f83 lw t6,0(a2) -800147ec: 00289793 slli a5,a7,0x2 -800147f0: 00e55533 srl a0,a0,a4 -800147f4: 006f9fb3 sll t6,t6,t1 -800147f8: 00f807b3 add a5,a6,a5 -800147fc: 01f56533 or a0,a0,t6 -80014800: 00a7a023 sw a0,0(a5) -80014804: 00188893 addi a7,a7,1 -80014808: f91ff06f j 80014798 <__trunctfdf2+0x1e0> -8001480c: 01412603 lw a2,20(sp) -80014810: 01812783 lw a5,24(sp) -80014814: 01c12803 lw a6,28(sp) -80014818: 00f666b3 or a3,a2,a5 -8001481c: 0106e6b3 or a3,a3,a6 -80014820: 00a6e6b3 or a3,a3,a0 -80014824: 00071863 bnez a4,80014834 <__trunctfdf2+0x27c> -80014828: 00d036b3 snez a3,a3 -8001482c: 00000793 li a5,0 -80014830: e75ff06f j 800146a4 <__trunctfdf2+0xec> -80014834: 0a068e63 beqz a3,800148f0 <__trunctfdf2+0x338> -80014838: 01c65693 srli a3,a2,0x1c -8001483c: 00481813 slli a6,a6,0x4 -80014840: 00479613 slli a2,a5,0x4 -80014844: 01c7d793 srli a5,a5,0x1c -80014848: 00400737 lui a4,0x400 -8001484c: 00c6e6b3 or a3,a3,a2 -80014850: 0107e7b3 or a5,a5,a6 -80014854: 00e7e7b3 or a5,a5,a4 -80014858: ff86f693 andi a3,a3,-8 -8001485c: 7ff00713 li a4,2047 -80014860: e45ff06f j 800146a4 <__trunctfdf2+0xec> -80014864: 00000793 li a5,0 -80014868: 00000693 li a3,0 -8001486c: 7ff00713 li a4,2047 -80014870: 00879613 slli a2,a5,0x8 -80014874: 00065e63 bgez a2,80014890 <__trunctfdf2+0x2d8> -80014878: 00170713 addi a4,a4,1 # 400001 <_start-0x7fbfffff> -8001487c: 7ff00613 li a2,2047 -80014880: 06c70c63 beq a4,a2,800148f8 <__trunctfdf2+0x340> -80014884: ff800637 lui a2,0xff800 -80014888: fff60613 addi a2,a2,-1 # ff7fffff <__BSS_END__+0x7f7e93cf> -8001488c: 00c7f7b3 and a5,a5,a2 -80014890: 01d79613 slli a2,a5,0x1d -80014894: 0036d693 srli a3,a3,0x3 -80014898: 00d666b3 or a3,a2,a3 -8001489c: 7ff00613 li a2,2047 -800148a0: 0037d793 srli a5,a5,0x3 -800148a4: 00c71e63 bne a4,a2,800148c0 <__trunctfdf2+0x308> -800148a8: 00f6e6b3 or a3,a3,a5 -800148ac: 00000793 li a5,0 -800148b0: 00068863 beqz a3,800148c0 <__trunctfdf2+0x308> -800148b4: 000807b7 lui a5,0x80 -800148b8: 00000693 li a3,0 -800148bc: 00000593 li a1,0 -800148c0: 01471713 slli a4,a4,0x14 -800148c4: 7ff00637 lui a2,0x7ff00 -800148c8: 00c79793 slli a5,a5,0xc -800148cc: 00c77733 and a4,a4,a2 -800148d0: 00c7d793 srli a5,a5,0xc -800148d4: 01f59593 slli a1,a1,0x1f -800148d8: 00f767b3 or a5,a4,a5 -800148dc: 00b7e733 or a4,a5,a1 -800148e0: 00068513 mv a0,a3 -800148e4: 00070593 mv a1,a4 -800148e8: 02010113 addi sp,sp,32 -800148ec: 00008067 ret +8001467c <__trunctfdf2>: +8001467c: 00c52583 lw a1,12(a0) +80014680: 00852783 lw a5,8(a0) +80014684: 00452703 lw a4,4(a0) +80014688: fe010113 addi sp,sp,-32 +8001468c: 00052683 lw a3,0(a0) +80014690: 00f12423 sw a5,8(sp) +80014694: 00f12c23 sw a5,24(sp) +80014698: 01059793 slli a5,a1,0x10 +8001469c: 00e12223 sw a4,4(sp) +800146a0: 00e12a23 sw a4,20(sp) +800146a4: 0107d793 srli a5,a5,0x10 +800146a8: 00159713 slli a4,a1,0x1 +800146ac: 00b12623 sw a1,12(sp) +800146b0: 00d12023 sw a3,0(sp) +800146b4: 00d12823 sw a3,16(sp) +800146b8: 00f12e23 sw a5,28(sp) +800146bc: 01175713 srli a4,a4,0x11 +800146c0: 01f5d593 srli a1,a1,0x1f +800146c4: 01010813 addi a6,sp,16 +800146c8: 01c10613 addi a2,sp,28 +800146cc: 00062783 lw a5,0(a2) +800146d0: ffc62683 lw a3,-4(a2) +800146d4: ffc60613 addi a2,a2,-4 +800146d8: 00379793 slli a5,a5,0x3 +800146dc: 01d6d693 srli a3,a3,0x1d +800146e0: 00d7e7b3 or a5,a5,a3 +800146e4: 00f62223 sw a5,4(a2) +800146e8: fec812e3 bne a6,a2,800146cc <__trunctfdf2+0x50> +800146ec: 01012683 lw a3,16(sp) +800146f0: 00170793 addi a5,a4,1 +800146f4: 00369513 slli a0,a3,0x3 +800146f8: 000086b7 lui a3,0x8 +800146fc: ffe68693 addi a3,a3,-2 # 7ffe <_start-0x7fff8002> +80014700: 00a12823 sw a0,16(sp) +80014704: 00d7f7b3 and a5,a5,a3 +80014708: 1c078463 beqz a5,800148d0 <__trunctfdf2+0x254> +8001470c: ffffc7b7 lui a5,0xffffc +80014710: 40078793 addi a5,a5,1024 # ffffc400 <__BSS_END__+0x7ffe57c4> +80014714: 00f70733 add a4,a4,a5 +80014718: 7fe00793 li a5,2046 +8001471c: 20e7c663 blt a5,a4,80014928 <__trunctfdf2+0x2ac> +80014720: 06e05863 blez a4,80014790 <__trunctfdf2+0x114> +80014724: 01812803 lw a6,24(sp) +80014728: 01c12603 lw a2,28(sp) +8001472c: 01412783 lw a5,20(sp) +80014730: 01c85693 srli a3,a6,0x1c +80014734: 00461613 slli a2,a2,0x4 +80014738: 00d66633 or a2,a2,a3 +8001473c: 00479693 slli a3,a5,0x4 +80014740: 00a6e6b3 or a3,a3,a0 +80014744: 01c7d793 srli a5,a5,0x1c +80014748: 00481813 slli a6,a6,0x4 +8001474c: 00d036b3 snez a3,a3 +80014750: 0107e7b3 or a5,a5,a6 +80014754: 00f6e6b3 or a3,a3,a5 +80014758: 00c12a23 sw a2,20(sp) +8001475c: 00d12823 sw a3,16(sp) +80014760: 01012683 lw a3,16(sp) +80014764: 01412783 lw a5,20(sp) +80014768: 0076f613 andi a2,a3,7 +8001476c: 1c060463 beqz a2,80014934 <__trunctfdf2+0x2b8> +80014770: 00f6f613 andi a2,a3,15 +80014774: 00400513 li a0,4 +80014778: 1aa60e63 beq a2,a0,80014934 <__trunctfdf2+0x2b8> +8001477c: 00468613 addi a2,a3,4 +80014780: 00d636b3 sltu a3,a2,a3 +80014784: 00d787b3 add a5,a5,a3 +80014788: 00060693 mv a3,a2 +8001478c: 1a80006f j 80014934 <__trunctfdf2+0x2b8> +80014790: fcc00793 li a5,-52 +80014794: 00f75c63 bge a4,a5,800147ac <__trunctfdf2+0x130> +80014798: 00012a23 sw zero,20(sp) +8001479c: 00100793 li a5,1 +800147a0: 00f12823 sw a5,16(sp) +800147a4: 00000713 li a4,0 +800147a8: fb9ff06f j 80014760 <__trunctfdf2+0xe4> +800147ac: 01c12783 lw a5,28(sp) +800147b0: 00080f37 lui t5,0x80 +800147b4: 03d00693 li a3,61 +800147b8: 00ff6f33 or t5,t5,a5 +800147bc: 40e686b3 sub a3,a3,a4 +800147c0: 01e12e23 sw t5,28(sp) +800147c4: 4056de93 srai t4,a3,0x5 +800147c8: 00080713 mv a4,a6 +800147cc: 00000793 li a5,0 +800147d0: 00000e13 li t3,0 +800147d4: 00072503 lw a0,0(a4) +800147d8: 00178793 addi a5,a5,1 +800147dc: 00470713 addi a4,a4,4 +800147e0: 00ae6e33 or t3,t3,a0 +800147e4: fefe98e3 bne t4,a5,800147d4 <__trunctfdf2+0x158> +800147e8: 01f6f713 andi a4,a3,31 +800147ec: 002e9693 slli a3,t4,0x2 +800147f0: 04071063 bnez a4,80014830 <__trunctfdf2+0x1b4> +800147f4: 00300713 li a4,3 +800147f8: 00000793 li a5,0 +800147fc: 41d70733 sub a4,a4,t4 +80014800: 00d60533 add a0,a2,a3 +80014804: 00052503 lw a0,0(a0) +80014808: 00178793 addi a5,a5,1 +8001480c: 00460613 addi a2,a2,4 +80014810: fea62e23 sw a0,-4(a2) +80014814: fef756e3 bge a4,a5,80014800 <__trunctfdf2+0x184> +80014818: 00400713 li a4,4 +8001481c: 41d70733 sub a4,a4,t4 +80014820: 00100793 li a5,1 +80014824: 04e05e63 blez a4,80014880 <__trunctfdf2+0x204> +80014828: 00070793 mv a5,a4 +8001482c: 0540006f j 80014880 <__trunctfdf2+0x204> +80014830: 02010793 addi a5,sp,32 +80014834: 00d787b3 add a5,a5,a3 +80014838: ff07a783 lw a5,-16(a5) +8001483c: 02000313 li t1,32 +80014840: 40e30333 sub t1,t1,a4 +80014844: 006797b3 sll a5,a5,t1 +80014848: 00d80633 add a2,a6,a3 +8001484c: 00300693 li a3,3 +80014850: 00fe6e33 or t3,t3,a5 +80014854: 00000893 li a7,0 +80014858: 41d686b3 sub a3,a3,t4 +8001485c: 00460613 addi a2,a2,4 +80014860: 04d8c463 blt a7,a3,800148a8 <__trunctfdf2+0x22c> +80014864: 00269693 slli a3,a3,0x2 +80014868: 02010613 addi a2,sp,32 +8001486c: 00400793 li a5,4 +80014870: 00d606b3 add a3,a2,a3 +80014874: 00ef5733 srl a4,t5,a4 +80014878: 41d787b3 sub a5,a5,t4 +8001487c: fee6a823 sw a4,-16(a3) +80014880: 00400693 li a3,4 +80014884: 00279713 slli a4,a5,0x2 +80014888: 00e80733 add a4,a6,a4 +8001488c: 00072023 sw zero,0(a4) +80014890: 00178793 addi a5,a5,1 +80014894: fed798e3 bne a5,a3,80014884 <__trunctfdf2+0x208> +80014898: 01012703 lw a4,16(sp) +8001489c: 01c037b3 snez a5,t3 +800148a0: 00f767b3 or a5,a4,a5 +800148a4: efdff06f j 800147a0 <__trunctfdf2+0x124> +800148a8: ffc62503 lw a0,-4(a2) +800148ac: 00062f83 lw t6,0(a2) +800148b0: 00289793 slli a5,a7,0x2 +800148b4: 00e55533 srl a0,a0,a4 +800148b8: 006f9fb3 sll t6,t6,t1 +800148bc: 00f807b3 add a5,a6,a5 +800148c0: 01f56533 or a0,a0,t6 +800148c4: 00a7a023 sw a0,0(a5) +800148c8: 00188893 addi a7,a7,1 +800148cc: f91ff06f j 8001485c <__trunctfdf2+0x1e0> +800148d0: 01412603 lw a2,20(sp) +800148d4: 01812783 lw a5,24(sp) +800148d8: 01c12803 lw a6,28(sp) +800148dc: 00f666b3 or a3,a2,a5 +800148e0: 0106e6b3 or a3,a3,a6 +800148e4: 00a6e6b3 or a3,a3,a0 +800148e8: 00071863 bnez a4,800148f8 <__trunctfdf2+0x27c> +800148ec: 00d036b3 snez a3,a3 800148f0: 00000793 li a5,0 -800148f4: f79ff06f j 8001486c <__trunctfdf2+0x2b4> -800148f8: 00000793 li a5,0 -800148fc: 00000693 li a3,0 -80014900: f91ff06f j 80014890 <__trunctfdf2+0x2d8> +800148f4: e75ff06f j 80014768 <__trunctfdf2+0xec> +800148f8: 0a068e63 beqz a3,800149b4 <__trunctfdf2+0x338> +800148fc: 01c65693 srli a3,a2,0x1c +80014900: 00481813 slli a6,a6,0x4 +80014904: 00479613 slli a2,a5,0x4 +80014908: 01c7d793 srli a5,a5,0x1c +8001490c: 00400737 lui a4,0x400 +80014910: 00c6e6b3 or a3,a3,a2 +80014914: 0107e7b3 or a5,a5,a6 +80014918: 00e7e7b3 or a5,a5,a4 +8001491c: ff86f693 andi a3,a3,-8 +80014920: 7ff00713 li a4,2047 +80014924: e45ff06f j 80014768 <__trunctfdf2+0xec> +80014928: 00000793 li a5,0 +8001492c: 00000693 li a3,0 +80014930: 7ff00713 li a4,2047 +80014934: 00879613 slli a2,a5,0x8 +80014938: 00065e63 bgez a2,80014954 <__trunctfdf2+0x2d8> +8001493c: 00170713 addi a4,a4,1 # 400001 <_start-0x7fbfffff> +80014940: 7ff00613 li a2,2047 +80014944: 06c70c63 beq a4,a2,800149bc <__trunctfdf2+0x340> +80014948: ff800637 lui a2,0xff800 +8001494c: fff60613 addi a2,a2,-1 # ff7fffff <__BSS_END__+0x7f7e93c3> +80014950: 00c7f7b3 and a5,a5,a2 +80014954: 01d79613 slli a2,a5,0x1d +80014958: 0036d693 srli a3,a3,0x3 +8001495c: 00d666b3 or a3,a2,a3 +80014960: 7ff00613 li a2,2047 +80014964: 0037d793 srli a5,a5,0x3 +80014968: 00c71e63 bne a4,a2,80014984 <__trunctfdf2+0x308> +8001496c: 00f6e6b3 or a3,a3,a5 +80014970: 00000793 li a5,0 +80014974: 00068863 beqz a3,80014984 <__trunctfdf2+0x308> +80014978: 000807b7 lui a5,0x80 +8001497c: 00000693 li a3,0 +80014980: 00000593 li a1,0 +80014984: 01471713 slli a4,a4,0x14 +80014988: 7ff00637 lui a2,0x7ff00 +8001498c: 00c79793 slli a5,a5,0xc +80014990: 00c77733 and a4,a4,a2 +80014994: 00c7d793 srli a5,a5,0xc +80014998: 01f59593 slli a1,a1,0x1f +8001499c: 00f767b3 or a5,a4,a5 +800149a0: 00b7e733 or a4,a5,a1 +800149a4: 00068513 mv a0,a3 +800149a8: 00070593 mv a1,a4 +800149ac: 02010113 addi sp,sp,32 +800149b0: 00008067 ret +800149b4: 00000793 li a5,0 +800149b8: f79ff06f j 80014930 <__trunctfdf2+0x2b4> +800149bc: 00000793 li a5,0 +800149c0: 00000693 li a3,0 +800149c4: f91ff06f j 80014954 <__trunctfdf2+0x2d8> -80014904 <__clzsi2>: -80014904: 000107b7 lui a5,0x10 -80014908: 02f57a63 bgeu a0,a5,8001493c <__clzsi2+0x38> -8001490c: 0ff00793 li a5,255 -80014910: 00a7b7b3 sltu a5,a5,a0 -80014914: 00379793 slli a5,a5,0x3 -80014918: 80015737 lui a4,0x80015 -8001491c: 02000693 li a3,32 -80014920: 40f686b3 sub a3,a3,a5 -80014924: 00f55533 srl a0,a0,a5 -80014928: 7fc70793 addi a5,a4,2044 # 800157fc <__BSS_END__+0xffffebcc> -8001492c: 00a78533 add a0,a5,a0 -80014930: 00054503 lbu a0,0(a0) -80014934: 40a68533 sub a0,a3,a0 -80014938: 00008067 ret -8001493c: 01000737 lui a4,0x1000 -80014940: 01000793 li a5,16 -80014944: fce56ae3 bltu a0,a4,80014918 <__clzsi2+0x14> -80014948: 01800793 li a5,24 -8001494c: fcdff06f j 80014918 <__clzsi2+0x14> +800149c8 <__clzsi2>: +800149c8: 000107b7 lui a5,0x10 +800149cc: 02f57a63 bgeu a0,a5,80014a00 <__clzsi2+0x38> +800149d0: 0ff00793 li a5,255 +800149d4: 00a7b7b3 sltu a5,a5,a0 +800149d8: 00379793 slli a5,a5,0x3 +800149dc: 80016737 lui a4,0x80016 +800149e0: 02000693 li a3,32 +800149e4: 40f686b3 sub a3,a3,a5 +800149e8: 00f55533 srl a0,a0,a5 +800149ec: 84c70793 addi a5,a4,-1972 # 8001584c <__BSS_END__+0xffffec10> +800149f0: 00a78533 add a0,a5,a0 +800149f4: 00054503 lbu a0,0(a0) +800149f8: 40a68533 sub a0,a3,a0 +800149fc: 00008067 ret +80014a00: 01000737 lui a4,0x1000 +80014a04: 01000793 li a5,16 +80014a08: fce56ae3 bltu a0,a4,800149dc <__clzsi2+0x14> +80014a0c: 01800793 li a5,24 +80014a10: fcdff06f j 800149dc <__clzsi2+0x14> Disassembly of section .rodata: -80014950 : -80014950: 0030 addi a2,sp,8 -80014952: 0000 unimp -80014954: 0031 c.nop 12 -80014956: 0000 unimp -80014958: 0032 c.slli zero,0xc -8001495a: 0000 unimp -8001495c: 00000033 add zero,zero,zero -80014960: 0034 addi a3,sp,8 -80014962: 0000 unimp -80014964: 0035 c.nop 13 -80014966: 0000 unimp -80014968: 0036 c.slli zero,0xd -8001496a: 0000 unimp -8001496c: 00000037 lui zero,0x0 -80014970: 0038 addi a4,sp,8 -80014972: 0000 unimp -80014974: 0039 c.nop 14 -80014976: 0000 unimp -80014978: 0061 c.nop 24 -8001497a: 0000 unimp -8001497c: 0062 c.slli zero,0x18 -8001497e: 0000 unimp -80014980: 00000063 beqz zero,80014980 <__clzsi2+0x7c> -80014984: 0064 addi s1,sp,12 -80014986: 0000 unimp -80014988: 0065 c.nop 25 -8001498a: 0000 unimp -8001498c: 0066 c.slli zero,0x19 -8001498e: 0000 unimp -80014990: 6548 flw fa0,12(a0) -80014992: 6c6c flw fa1,92(s0) -80014994: 7266206f j 800770ba <__BSS_END__+0x6048a> -80014998: 5f206d6f jal s10,8001af8a <__BSS_END__+0x435a> -8001499c: 7369 lui t1,0xffffa -8001499e: 7461 lui s0,0xffff8 -800149a0: 7974 flw fa3,116(a0) -800149a2: 000a c.slli zero,0x2 -800149a4: 5245 li tp,-15 -800149a6: 4f52 lw t5,20(sp) -800149a8: 3a52 fld fs4,304(sp) -800149aa: 5f20 lw s0,120(a4) -800149ac: 6c6c696b 0x6c6c696b -800149b0: 6e20 flw fs0,88(a2) -800149b2: 7920746f jal s0,8001c144 <__BSS_END__+0x5514> -800149b6: 7465 lui s0,0xffff9 -800149b8: 6920 flw fs0,80(a0) -800149ba: 706d c.lui zero,0xffffb -800149bc: 656c flw fa1,76(a0) -800149be: 656d lui a0,0x1b -800149c0: 746e flw fs0,248(sp) -800149c2: 6465 lui s0,0x19 -800149c4: 000a c.slli zero,0x2 -800149c6: 0000 unimp -800149c8: 5245 li tp,-15 -800149ca: 4f52 lw t5,20(sp) -800149cc: 3a52 fld fs4,304(sp) -800149ce: 5f20 lw s0,120(a4) -800149d0: 6e75 lui t3,0x1d -800149d2: 696c flw fa1,84(a0) -800149d4: 6b6e flw fs6,216(sp) -800149d6: 6e20 flw fs0,88(a2) -800149d8: 7920746f jal s0,8001c16a <__BSS_END__+0x553a> -800149dc: 7465 lui s0,0xffff9 -800149de: 6920 flw fs0,80(a0) -800149e0: 706d c.lui zero,0xffffb -800149e2: 656c flw fa1,76(a0) -800149e4: 656d lui a0,0x1b -800149e6: 746e flw fs0,248(sp) -800149e8: 6465 lui s0,0x19 -800149ea: 000a c.slli zero,0x2 -800149ec: 5245 li tp,-15 -800149ee: 4f52 lw t5,20(sp) -800149f0: 3a52 fld fs4,304(sp) -800149f2: 5f20 lw s0,120(a4) -800149f4: 74746567 0x74746567 -800149f8: 6d69 lui s10,0x1a -800149fa: 6f65 lui t5,0x19 -800149fc: 6466 flw fs0,88(sp) -800149fe: 7961 lui s2,0xffff8 -80014a00: 6e20 flw fs0,88(a2) -80014a02: 7920746f jal s0,8001c194 <__BSS_END__+0x5564> -80014a06: 7465 lui s0,0xffff9 -80014a08: 6920 flw fs0,80(a0) -80014a0a: 706d c.lui zero,0xffffb -80014a0c: 656c flw fa1,76(a0) -80014a0e: 656d lui a0,0x1b -80014a10: 746e flw fs0,248(sp) -80014a12: 6465 lui s0,0x19 -80014a14: 000a c.slli zero,0x2 -80014a16: 0000 unimp -80014a18: 5245 li tp,-15 -80014a1a: 4f52 lw t5,20(sp) -80014a1c: 3a52 fld fs4,304(sp) -80014a1e: 5f20 lw s0,120(a4) -80014a20: 696c flw fa1,84(a0) -80014a22: 6b6e flw fs6,216(sp) -80014a24: 6e20 flw fs0,88(a2) -80014a26: 7920746f jal s0,8001c1b8 <__BSS_END__+0x5588> -80014a2a: 7465 lui s0,0xffff9 -80014a2c: 6920 flw fs0,80(a0) -80014a2e: 706d c.lui zero,0xffffb -80014a30: 656c flw fa1,76(a0) -80014a32: 656d lui a0,0x1b -80014a34: 746e flw fs0,248(sp) -80014a36: 6465 lui s0,0x19 -80014a38: 000a c.slli zero,0x2 +80014a18 : +80014a18: 0030 addi a2,sp,8 +80014a1a: 0000 unimp +80014a1c: 0031 c.nop 12 +80014a1e: 0000 unimp +80014a20: 0032 c.slli zero,0xc +80014a22: 0000 unimp +80014a24: 00000033 add zero,zero,zero +80014a28: 0034 addi a3,sp,8 +80014a2a: 0000 unimp +80014a2c: 0035 c.nop 13 +80014a2e: 0000 unimp +80014a30: 0036 c.slli zero,0xd +80014a32: 0000 unimp +80014a34: 00000037 lui zero,0x0 +80014a38: 0038 addi a4,sp,8 80014a3a: 0000 unimp -80014a3c: 0030 addi a2,sp,8 +80014a3c: 0039 c.nop 14 80014a3e: 0000 unimp -80014a40: 0031 c.nop 12 +80014a40: 0061 c.nop 24 80014a42: 0000 unimp -80014a44: 0032 c.slli zero,0xc +80014a44: 0062 c.slli zero,0x18 80014a46: 0000 unimp -80014a48: 00000033 add zero,zero,zero -80014a4c: 0034 addi a3,sp,8 +80014a48: 00000063 beqz zero,80014a48 <__clzsi2+0x80> +80014a4c: 0064 addi s1,sp,12 80014a4e: 0000 unimp -80014a50: 0035 c.nop 13 +80014a50: 0065 c.nop 25 80014a52: 0000 unimp -80014a54: 0036 c.slli zero,0xd +80014a54: 0066 c.slli zero,0x19 80014a56: 0000 unimp -80014a58: 00000037 lui zero,0x0 -80014a5c: 0038 addi a4,sp,8 -80014a5e: 0000 unimp -80014a60: 0039 c.nop 14 -80014a62: 0000 unimp -80014a64: 0061 c.nop 24 -80014a66: 0000 unimp -80014a68: 0062 c.slli zero,0x18 -80014a6a: 0000 unimp -80014a6c: 00000063 beqz zero,80014a6c <__clzsi2+0x168> -80014a70: 0064 addi s1,sp,12 -80014a72: 0000 unimp -80014a74: 0065 c.nop 25 -80014a76: 0000 unimp -80014a78: 0066 c.slli zero,0x19 -80014a7a: 0000 unimp -80014a7c: 000a c.slli zero,0x2 -80014a7e: 0000 unimp -80014a80: 5245 li tp,-15 -80014a82: 4f52 lw t5,20(sp) -80014a84: 3a52 fld fs4,304(sp) -80014a86: 7020 flw fs0,96(s0) -80014a88: 5f6c636f jal t1,800db07e <__BSS_END__+0xc444e> -80014a8c: 77617073 csrci 0x776,2 -80014a90: 206e fld ft0,216(sp) -80014a92: 6f64 flw fs1,92(a4) -80014a94: 7365 lui t1,0xffff9 -80014a96: 276e fld fa4,216(sp) -80014a98: 2074 fld fa3,192(s0) -80014a9a: 70707573 csrrci a0,0x707,0 -80014a9e: 2074726f jal tp,8005c4a4 <__BSS_END__+0x45874> -80014aa2: 205a fld ft0,400(sp) -80014aa4: 6964 flw fs1,84(a0) -80014aa6: 656d lui a0,0x1b -80014aa8: 736e flw ft6,248(sp) -80014aaa: 6f69 lui t5,0x1a -80014aac: 206e fld ft0,216(sp) -80014aae: 6579 lui a0,0x1e -80014ab0: 2174 fld fa3,192(a0) -80014ab2: 000a c.slli zero,0x2 -80014ab4: 0030 addi a2,sp,8 +80014a58: 5245 li tp,-15 +80014a5a: 4f52 lw t5,20(sp) +80014a5c: 3a52 fld fs4,304(sp) +80014a5e: 5f20 lw s0,120(a4) +80014a60: 6e75 lui t3,0x1d +80014a62: 696c flw fa1,84(a0) +80014a64: 6b6e flw fs6,216(sp) +80014a66: 6e20 flw fs0,88(a2) +80014a68: 7920746f jal s0,8001c1fa <__BSS_END__+0x55be> +80014a6c: 7465 lui s0,0xffff9 +80014a6e: 6920 flw fs0,80(a0) +80014a70: 706d c.lui zero,0xffffb +80014a72: 656c flw fa1,76(a0) +80014a74: 656d lui a0,0x1b +80014a76: 746e flw fs0,248(sp) +80014a78: 6465 lui s0,0x19 +80014a7a: 000a c.slli zero,0x2 +80014a7c: 5245 li tp,-15 +80014a7e: 4f52 lw t5,20(sp) +80014a80: 3a52 fld fs4,304(sp) +80014a82: 5f20 lw s0,120(a4) +80014a84: 696c flw fa1,84(a0) +80014a86: 6b6e flw fs6,216(sp) +80014a88: 6e20 flw fs0,88(a2) +80014a8a: 7920746f jal s0,8001c21c <__BSS_END__+0x55e0> +80014a8e: 7465 lui s0,0xffff9 +80014a90: 6920 flw fs0,80(a0) +80014a92: 706d c.lui zero,0xffffb +80014a94: 656c flw fa1,76(a0) +80014a96: 656d lui a0,0x1b +80014a98: 746e flw fs0,248(sp) +80014a9a: 6465 lui s0,0x19 +80014a9c: 000a c.slli zero,0x2 +80014a9e: 0000 unimp +80014aa0: 0030 addi a2,sp,8 +80014aa2: 0000 unimp +80014aa4: 0031 c.nop 12 +80014aa6: 0000 unimp +80014aa8: 0032 c.slli zero,0xc +80014aaa: 0000 unimp +80014aac: 00000033 add zero,zero,zero +80014ab0: 0034 addi a3,sp,8 +80014ab2: 0000 unimp +80014ab4: 0035 c.nop 13 80014ab6: 0000 unimp -80014ab8: 0031 c.nop 12 +80014ab8: 0036 c.slli zero,0xd 80014aba: 0000 unimp -80014abc: 0032 c.slli zero,0xc -80014abe: 0000 unimp -80014ac0: 00000033 add zero,zero,zero -80014ac4: 0034 addi a3,sp,8 +80014abc: 00000037 lui zero,0x0 +80014ac0: 0038 addi a4,sp,8 +80014ac2: 0000 unimp +80014ac4: 0039 c.nop 14 80014ac6: 0000 unimp -80014ac8: 0035 c.nop 13 +80014ac8: 0061 c.nop 24 80014aca: 0000 unimp -80014acc: 0036 c.slli zero,0xd +80014acc: 0062 c.slli zero,0x18 80014ace: 0000 unimp -80014ad0: 00000037 lui zero,0x0 -80014ad4: 0038 addi a4,sp,8 +80014ad0: 00000063 beqz zero,80014ad0 <__clzsi2+0x108> +80014ad4: 0064 addi s1,sp,12 80014ad6: 0000 unimp -80014ad8: 0039 c.nop 14 +80014ad8: 0065 c.nop 25 80014ada: 0000 unimp -80014adc: 0061 c.nop 24 +80014adc: 0066 c.slli zero,0x19 80014ade: 0000 unimp -80014ae0: 0062 c.slli zero,0x18 +80014ae0: 000a c.slli zero,0x2 80014ae2: 0000 unimp -80014ae4: 00000063 beqz zero,80014ae4 <__clzsi2+0x1e0> -80014ae8: 0064 addi s1,sp,12 +80014ae4: 6425 lui s0,0x9 +80014ae6: 000a c.slli zero,0x2 +80014ae8: 0030 addi a2,sp,8 80014aea: 0000 unimp -80014aec: 0065 c.nop 25 +80014aec: 0031 c.nop 12 80014aee: 0000 unimp -80014af0: 0066 c.slli zero,0x19 +80014af0: 0032 c.slli zero,0xc 80014af2: 0000 unimp -80014af4: 6574 flw fa3,76(a0) -80014af6: 6e697473 csrrci s0,0x6e6,18 -80014afa: 6d745f67 0x6d745f67 -80014afe: 00000a63 beqz zero,80014b12 <__clzsi2+0x20e> +80014af4: 00000033 add zero,zero,zero +80014af8: 0034 addi a3,sp,8 +80014afa: 0000 unimp +80014afc: 0035 c.nop 13 +80014afe: 0000 unimp +80014b00: 0036 c.slli zero,0xd 80014b02: 0000 unimp -80014b04: 000a c.slli zero,0x2 -80014b06: 0000 unimp -80014b08: 6574 flw fa3,76(a0) -80014b0a: 645f7473 csrrci s0,0x645,30 -80014b0e: 7669 lui a2,0xffffa -80014b10: 7265 lui tp,0xffff9 -80014b12: 636e6567 0x636e6567 -80014b16: 0a65 addi s4,s4,25 -80014b18: 0000 unimp -80014b1a: 0000 unimp -80014b1c: 6574 flw fa3,76(a0) -80014b1e: 735f7473 csrrci s0,0x735,30 -80014b22: 6170 flw fa2,68(a0) -80014b24: 000a6e77 0xa6e77 -80014b28: 0030 addi a2,sp,8 -80014b2a: 0000 unimp -80014b2c: 0031 c.nop 12 -80014b2e: 0000 unimp -80014b30: 0032 c.slli zero,0xc -80014b32: 0000 unimp -80014b34: 00000033 add zero,zero,zero -80014b38: 0034 addi a3,sp,8 +80014b04: 00000037 lui zero,0x0 +80014b08: 0038 addi a4,sp,8 +80014b0a: 0000 unimp +80014b0c: 0039 c.nop 14 +80014b0e: 0000 unimp +80014b10: 0061 c.nop 24 +80014b12: 0000 unimp +80014b14: 0062 c.slli zero,0x18 +80014b16: 0000 unimp +80014b18: 00000063 beqz zero,80014b18 <__clzsi2+0x150> +80014b1c: 0064 addi s1,sp,12 +80014b1e: 0000 unimp +80014b20: 0065 c.nop 25 +80014b22: 0000 unimp +80014b24: 0066 c.slli zero,0x19 +80014b26: 0000 unimp +80014b28: 6574 flw fa3,76(a0) +80014b2a: 6e697473 csrrci s0,0x6e6,18 +80014b2e: 6d745f67 0x6d745f67 +80014b32: 00000a63 beqz zero,80014b46 <__clzsi2+0x17e> +80014b36: 0000 unimp +80014b38: 000a c.slli zero,0x2 80014b3a: 0000 unimp -80014b3c: 0035 c.nop 13 -80014b3e: 0000 unimp -80014b40: 0036 c.slli zero,0xd -80014b42: 0000 unimp -80014b44: 00000037 lui zero,0x0 -80014b48: 0038 addi a4,sp,8 -80014b4a: 0000 unimp -80014b4c: 0039 c.nop 14 +80014b3c: 6574 flw fa3,76(a0) +80014b3e: 645f7473 csrrci s0,0x645,30 +80014b42: 7669 lui a2,0xffffa +80014b44: 7265 lui tp,0xffff9 +80014b46: 636e6567 0x636e6567 +80014b4a: 0a65 addi s4,s4,25 +80014b4c: 0000 unimp 80014b4e: 0000 unimp -80014b50: 0061 c.nop 24 -80014b52: 0000 unimp -80014b54: 0062 c.slli zero,0x18 -80014b56: 0000 unimp -80014b58: 00000063 beqz zero,80014b58 <__clzsi2+0x254> -80014b5c: 0064 addi s1,sp,12 +80014b50: 6574 flw fa3,76(a0) +80014b52: 735f7473 csrrci s0,0x735,30 +80014b56: 6170 flw fa2,68(a0) +80014b58: 000a6e77 0xa6e77 +80014b5c: 0030 addi a2,sp,8 80014b5e: 0000 unimp -80014b60: 0065 c.nop 25 +80014b60: 0031 c.nop 12 80014b62: 0000 unimp -80014b64: 0066 c.slli zero,0x19 +80014b64: 0032 c.slli zero,0xc 80014b66: 0000 unimp -80014b68: 706d6953 0x706d6953 -80014b6c: 656c flw fa1,76(a0) -80014b6e: 4d20 lw s0,88(a0) -80014b70: 6961 lui s2,0x18 -80014b72: 0a6e slli s4,s4,0x1b -80014b74: 0000 unimp +80014b68: 00000033 add zero,zero,zero +80014b6c: 0034 addi a3,sp,8 +80014b6e: 0000 unimp +80014b70: 0035 c.nop 13 +80014b72: 0000 unimp +80014b74: 0036 c.slli zero,0xd 80014b76: 0000 unimp -80014b78: 6574 flw fa3,76(a0) -80014b7a: 645f7473 csrrci s0,0x645,30 -80014b7e: 7669 lui a2,0xffffa -80014b80: 7265 lui tp,0xffff9 -80014b82: 636e6567 0x636e6567 -80014b86: 0a65 addi s4,s4,25 -80014b88: 0000 unimp +80014b78: 00000037 lui zero,0x0 +80014b7c: 0038 addi a4,sp,8 +80014b7e: 0000 unimp +80014b80: 0039 c.nop 14 +80014b82: 0000 unimp +80014b84: 0061 c.nop 24 +80014b86: 0000 unimp +80014b88: 0062 c.slli zero,0x18 80014b8a: 0000 unimp -80014b8c: 6574 flw fa3,76(a0) -80014b8e: 775f7473 csrrci s0,0x775,30 -80014b92: 77617073 csrci 0x776,2 -80014b96: 0a6e slli s4,s4,0x1b -80014b98: 0000 unimp +80014b8c: 00000063 beqz zero,80014b8c <__clzsi2+0x1c4> +80014b90: 0064 addi s1,sp,12 +80014b92: 0000 unimp +80014b94: 0065 c.nop 25 +80014b96: 0000 unimp +80014b98: 0066 c.slli zero,0x19 80014b9a: 0000 unimp -80014b9c: 72616853 0x72616853 -80014ba0: 6465 lui s0,0x19 -80014ba2: 4d20 lw s0,88(a0) -80014ba4: 6d65 lui s10,0x19 -80014ba6: 2079726f jal tp,800ac5ac <__BSS_END__+0x9597c> -80014baa: 6574 flw fa3,76(a0) -80014bac: 000a7473 csrrci s0,ustatus,20 -80014bb0: 7470 flw fa2,108(s0) -80014bb2: 3a72 fld fs4,312(sp) -80014bb4: 0020 addi s0,sp,8 -80014bb6: 0000 unimp -80014bb8: 6769724f fnmadd.q ft4,fs2,fs6,fa2 -80014bbc: 6e69 lui t3,0x1a -80014bbe: 6c61 lui s8,0x18 -80014bc0: 5620 lw s0,104(a2) -80014bc2: 6c61 lui s8,0x18 -80014bc4: 6575 lui a0,0x1d -80014bc6: 203a fld ft0,392(sp) -80014bc8: 0000 unimp -80014bca: 0000 unimp -80014bcc: 6552 flw fa0,20(sp) -80014bce: 6461 lui s0,0x18 -80014bd0: 5620 lw s0,104(a2) -80014bd2: 6c61 lui s8,0x18 -80014bd4: 6575 lui a0,0x1d -80014bd6: 203a fld ft0,392(sp) -80014bd8: 0000 unimp -80014bda: 0000 unimp -80014bdc: 2d2d jal 80015216 <__mprec_bigtens+0x9e> -80014bde: 2d2d jal 80015218 <__mprec_bigtens+0xa0> -80014be0: 2d2d jal 8001521a <__mprec_bigtens+0xa2> -80014be2: 2d2d jal 8001521c <__mprec_bigtens+0xa4> -80014be4: 2d2d jal 8001521e <__mprec_bigtens+0xa6> -80014be6: 2d2d jal 80015220 <__mprec_bigtens+0xa8> -80014be8: 2d2d jal 80015222 <__mprec_bigtens+0xaa> -80014bea: 2d2d jal 80015224 <__mprec_bigtens+0xac> -80014bec: 2d2d jal 80015226 <__mprec_bigtens+0xae> -80014bee: 0a2d addi s4,s4,11 -80014bf0: 0000 unimp -80014bf2: 0000 unimp -80014bf4: 7876 flw fa6,124(sp) -80014bf6: 735f 6170 6e77 0x6e776170735f -80014bfc: 70726157 0x70726157 -80014c00: 616d2073 csrs 0x616,s10 -80014c04: 5f74 lw a3,124(a4) -80014c06: 6461 lui s0,0x18 -80014c08: 5f64 lw s1,124(a4) -80014c0a: 6e72656b 0x6e72656b -80014c0e: 6c65 lui s8,0x19 -80014c10: 000a c.slli zero,0x2 -80014c12: 0000 unimp -80014c14: 0020 addi s0,sp,8 +80014b9c: 654c flw fa1,12(a0) +80014b9e: 2774 fld fa3,200(a4) +80014ba0: 74732073 csrs 0x747,t1 +80014ba4: 7261 lui tp,0xffff8 +80014ba6: 2e74 fld fa3,216(a2) +80014ba8: 2e2e fld ft8,200(sp) +80014baa: 000a c.slli zero,0x2 +80014bac: 6156 flw ft2,84(sp) +80014bae: 756c flw fa1,108(a0) +80014bb0: 3a65 jal 80014568 <__extenddftf2+0xe0> +80014bb2: 0020 addi s0,sp,8 +80014bb4: 706d6953 0x706d6953 +80014bb8: 656c flw fa1,76(a0) +80014bba: 4d20 lw s0,88(a0) +80014bbc: 6961 lui s2,0x18 +80014bbe: 0a6e slli s4,s4,0x1b +80014bc0: 0000 unimp +80014bc2: 0000 unimp +80014bc4: 6574 flw fa3,76(a0) +80014bc6: 645f7473 csrrci s0,0x645,30 +80014bca: 7669 lui a2,0xffffa +80014bcc: 7265 lui tp,0xffff9 +80014bce: 636e6567 0x636e6567 +80014bd2: 0a65 addi s4,s4,25 +80014bd4: 0000 unimp +80014bd6: 0000 unimp +80014bd8: 6574 flw fa3,76(a0) +80014bda: 775f7473 csrrci s0,0x775,30 +80014bde: 77617073 csrci 0x776,2 +80014be2: 0a6e slli s4,s4,0x1b +80014be4: 0000 unimp +80014be6: 0000 unimp +80014be8: 72616853 0x72616853 +80014bec: 6465 lui s0,0x19 +80014bee: 4d20 lw s0,88(a0) +80014bf0: 6d65 lui s10,0x19 +80014bf2: 2079726f jal tp,800ac5f8 <__BSS_END__+0x959bc> +80014bf6: 6574 flw fa3,76(a0) +80014bf8: 000a7473 csrrci s0,ustatus,20 +80014bfc: 7470 flw fa2,108(s0) +80014bfe: 3a72 fld fs4,312(sp) +80014c00: 0020 addi s0,sp,8 +80014c02: 0000 unimp +80014c04: 6769724f fnmadd.q ft4,fs2,fs6,fa2 +80014c08: 6e69 lui t3,0x1a +80014c0a: 6c61 lui s8,0x18 +80014c0c: 5620 lw s0,104(a2) +80014c0e: 6c61 lui s8,0x18 +80014c10: 6575 lui a0,0x1d +80014c12: 203a fld ft0,392(sp) +80014c14: 0000 unimp 80014c16: 0000 unimp -80014c18: 000a c.slli zero,0x2 -80014c1a: 0000 unimp -80014c1c: 4e49 li t3,18 -80014c1e: 0046 c.slli zero,0x11 -80014c20: 6e69 lui t3,0x1a -80014c22: 0066 c.slli zero,0x19 -80014c24: 414e lw sp,208(sp) -80014c26: 004e c.slli zero,0x13 -80014c28: 616e flw ft2,216(sp) -80014c2a: 006e c.slli zero,0x1b -80014c2c: 3130 fld fa2,96(a0) -80014c2e: 3332 fld ft6,296(sp) -80014c30: 3534 fld fa3,104(a0) -80014c32: 3736 fld fa4,360(sp) -80014c34: 3938 fld fa4,112(a0) -80014c36: 6261 lui tp,0x18 -80014c38: 66656463 bltu a0,t1,800152a0 <__mprec_bigtens+0x128> +80014c18: 6552 flw fa0,20(sp) +80014c1a: 6461 lui s0,0x18 +80014c1c: 5620 lw s0,104(a2) +80014c1e: 6c61 lui s8,0x18 +80014c20: 6575 lui a0,0x1d +80014c22: 203a fld ft0,392(sp) +80014c24: 0000 unimp +80014c26: 0000 unimp +80014c28: 2d2d jal 80015262 <__mprec_bigtens+0xaa> +80014c2a: 2d2d jal 80015264 <__mprec_bigtens+0xac> +80014c2c: 2d2d jal 80015266 <__mprec_bigtens+0xae> +80014c2e: 2d2d jal 80015268 <__mprec_bigtens+0xb0> +80014c30: 2d2d jal 8001526a <__mprec_bigtens+0xb2> +80014c32: 2d2d jal 8001526c <__mprec_bigtens+0xb4> +80014c34: 2d2d jal 8001526e <__mprec_bigtens+0xb6> +80014c36: 2d2d jal 80015270 <__mprec_bigtens+0xb8> +80014c38: 2d2d jal 80015272 <__mprec_bigtens+0xba> +80014c3a: 0a2d addi s4,s4,11 80014c3c: 0000 unimp 80014c3e: 0000 unimp -80014c40: 3130 fld fa2,96(a0) -80014c42: 3332 fld ft6,296(sp) -80014c44: 3534 fld fa3,104(a0) -80014c46: 3736 fld fa4,360(sp) -80014c48: 3938 fld fa4,112(a0) -80014c4a: 4241 li tp,16 -80014c4c: 46454443 fmadd.q fs0,fa0,ft4,fs0,rmm -80014c50: 0000 unimp -80014c52: 0000 unimp -80014c54: 6e28 flw fa0,88(a2) -80014c56: 6c75 lui s8,0x1d -80014c58: 296c fld fa1,208(a0) -80014c5a: 0000 unimp -80014c5c: 0030 addi a2,sp,8 +80014c40: 7876 flw fa6,124(sp) +80014c42: 735f 6170 6e77 0x6e776170735f +80014c48: 70726157 0x70726157 +80014c4c: 616d2073 csrs 0x616,s10 +80014c50: 5f74 lw a3,124(a4) +80014c52: 6461 lui s0,0x18 +80014c54: 5f64 lw s1,124(a4) +80014c56: 6e72656b 0x6e72656b +80014c5a: 6c65 lui s8,0x19 +80014c5c: 000a c.slli zero,0x2 80014c5e: 0000 unimp -80014c60: 2028 fld fa0,64(s0) -80014c62: 8000 0x8000 -80014c64: 16a8 addi a0,sp,872 -80014c66: 8000 0x8000 -80014c68: 16a8 addi a0,sp,872 -80014c6a: 8000 0x8000 -80014c6c: 201c fld fa5,0(s0) -80014c6e: 8000 0x8000 -80014c70: 16a8 addi a0,sp,872 -80014c72: 8000 0x8000 -80014c74: 16a8 addi a0,sp,872 -80014c76: 8000 0x8000 -80014c78: 16a8 addi a0,sp,872 -80014c7a: 8000 0x8000 -80014c7c: 189c addi a5,sp,112 -80014c7e: 8000 0x8000 -80014c80: 16a8 addi a0,sp,872 -80014c82: 8000 0x8000 -80014c84: 16a8 addi a0,sp,872 -80014c86: 8000 0x8000 -80014c88: 1ff8 addi a4,sp,1020 -80014c8a: 8000 0x8000 -80014c8c: 1f98 addi a4,sp,1008 -80014c8e: 8000 0x8000 -80014c90: 16a8 addi a0,sp,872 -80014c92: 8000 0x8000 -80014c94: 1e84 addi s1,sp,880 -80014c96: 8000 0x8000 -80014c98: 1fb4 addi a3,sp,1016 -80014c9a: 8000 0x8000 -80014c9c: 16a8 addi a0,sp,872 -80014c9e: 8000 0x8000 -80014ca0: 1fa8 addi a0,sp,1016 -80014ca2: 8000 0x8000 -80014ca4: 1678 addi a4,sp,812 -80014ca6: 8000 0x8000 -80014ca8: 1678 addi a4,sp,812 -80014caa: 8000 0x8000 -80014cac: 1678 addi a4,sp,812 +80014c60: 0020 addi s0,sp,8 +80014c62: 0000 unimp +80014c64: 000a c.slli zero,0x2 +80014c66: 0000 unimp +80014c68: 4e49 li t3,18 +80014c6a: 0046 c.slli zero,0x11 +80014c6c: 6e69 lui t3,0x1a +80014c6e: 0066 c.slli zero,0x19 +80014c70: 414e lw sp,208(sp) +80014c72: 004e c.slli zero,0x13 +80014c74: 616e flw ft2,216(sp) +80014c76: 006e c.slli zero,0x1b +80014c78: 3130 fld fa2,96(a0) +80014c7a: 3332 fld ft6,296(sp) +80014c7c: 3534 fld fa3,104(a0) +80014c7e: 3736 fld fa4,360(sp) +80014c80: 3938 fld fa4,112(a0) +80014c82: 6261 lui tp,0x18 +80014c84: 66656463 bltu a0,t1,800152ec <__mprec_bigtens+0x134> +80014c88: 0000 unimp +80014c8a: 0000 unimp +80014c8c: 3130 fld fa2,96(a0) +80014c8e: 3332 fld ft6,296(sp) +80014c90: 3534 fld fa3,104(a0) +80014c92: 3736 fld fa4,360(sp) +80014c94: 3938 fld fa4,112(a0) +80014c96: 4241 li tp,16 +80014c98: 46454443 fmadd.q fs0,fa0,ft4,fs0,rmm +80014c9c: 0000 unimp +80014c9e: 0000 unimp +80014ca0: 6e28 flw fa0,88(a2) +80014ca2: 6c75 lui s8,0x1d +80014ca4: 296c fld fa1,208(a0) +80014ca6: 0000 unimp +80014ca8: 0030 addi a2,sp,8 +80014caa: 0000 unimp +80014cac: 1fa0 addi s0,sp,1016 80014cae: 8000 0x8000 -80014cb0: 1678 addi a4,sp,812 +80014cb0: 1620 addi s0,sp,808 80014cb2: 8000 0x8000 -80014cb4: 1678 addi a4,sp,812 +80014cb4: 1620 addi s0,sp,808 80014cb6: 8000 0x8000 -80014cb8: 1678 addi a4,sp,812 +80014cb8: 1f94 addi a3,sp,1008 80014cba: 8000 0x8000 -80014cbc: 1678 addi a4,sp,812 +80014cbc: 1620 addi s0,sp,808 80014cbe: 8000 0x8000 -80014cc0: 1678 addi a4,sp,812 +80014cc0: 1620 addi s0,sp,808 80014cc2: 8000 0x8000 -80014cc4: 1678 addi a4,sp,812 +80014cc4: 1620 addi s0,sp,808 80014cc6: 8000 0x8000 -80014cc8: 16a8 addi a0,sp,872 +80014cc8: 1814 addi a3,sp,48 80014cca: 8000 0x8000 -80014ccc: 16a8 addi a0,sp,872 +80014ccc: 1620 addi s0,sp,808 80014cce: 8000 0x8000 -80014cd0: 16a8 addi a0,sp,872 +80014cd0: 1620 addi s0,sp,808 80014cd2: 8000 0x8000 -80014cd4: 16a8 addi a0,sp,872 +80014cd4: 1f70 addi a2,sp,956 80014cd6: 8000 0x8000 -80014cd8: 16a8 addi a0,sp,872 +80014cd8: 1f10 addi a2,sp,944 80014cda: 8000 0x8000 -80014cdc: 16a8 addi a0,sp,872 +80014cdc: 1620 addi s0,sp,808 80014cde: 8000 0x8000 -80014ce0: 16a8 addi a0,sp,872 +80014ce0: 1dfc addi a5,sp,764 80014ce2: 8000 0x8000 -80014ce4: 1918 addi a4,sp,176 +80014ce4: 1f2c addi a1,sp,952 80014ce6: 8000 0x8000 -80014ce8: 16a8 addi a0,sp,872 +80014ce8: 1620 addi s0,sp,808 80014cea: 8000 0x8000 -80014cec: 1dd4 addi a3,sp,756 +80014cec: 1f20 addi s0,sp,952 80014cee: 8000 0x8000 -80014cf0: 20b8 fld fa4,64(s1) +80014cf0: 15f0 addi a2,sp,748 80014cf2: 8000 0x8000 -80014cf4: 1918 addi a4,sp,176 +80014cf4: 15f0 addi a2,sp,748 80014cf6: 8000 0x8000 -80014cf8: 1918 addi a4,sp,176 +80014cf8: 15f0 addi a2,sp,748 80014cfa: 8000 0x8000 -80014cfc: 1918 addi a4,sp,176 +80014cfc: 15f0 addi a2,sp,748 80014cfe: 8000 0x8000 -80014d00: 16a8 addi a0,sp,872 +80014d00: 15f0 addi a2,sp,748 80014d02: 8000 0x8000 -80014d04: 16a8 addi a0,sp,872 +80014d04: 15f0 addi a2,sp,748 80014d06: 8000 0x8000 -80014d08: 16a8 addi a0,sp,872 +80014d08: 15f0 addi a2,sp,748 80014d0a: 8000 0x8000 -80014d0c: 16a8 addi a0,sp,872 +80014d0c: 15f0 addi a2,sp,748 80014d0e: 8000 0x8000 -80014d10: 20ac fld fa1,64(s1) +80014d10: 15f0 addi a2,sp,748 80014d12: 8000 0x8000 -80014d14: 16a8 addi a0,sp,872 +80014d14: 1620 addi s0,sp,808 80014d16: 8000 0x8000 -80014d18: 16a8 addi a0,sp,872 +80014d18: 1620 addi s0,sp,808 80014d1a: 8000 0x8000 -80014d1c: 2040 fld fs0,128(s0) +80014d1c: 1620 addi s0,sp,808 80014d1e: 8000 0x8000 -80014d20: 16a8 addi a0,sp,872 +80014d20: 1620 addi s0,sp,808 80014d22: 8000 0x8000 -80014d24: 16a8 addi a0,sp,872 +80014d24: 1620 addi s0,sp,808 80014d26: 8000 0x8000 -80014d28: 16a8 addi a0,sp,872 +80014d28: 1620 addi s0,sp,808 80014d2a: 8000 0x8000 -80014d2c: 1e00 addi s0,sp,816 +80014d2c: 1620 addi s0,sp,808 80014d2e: 8000 0x8000 -80014d30: 16a8 addi a0,sp,872 +80014d30: 1890 addi a2,sp,112 80014d32: 8000 0x8000 -80014d34: 2078 fld fa4,192(s0) +80014d34: 1620 addi s0,sp,808 80014d36: 8000 0x8000 -80014d38: 16a8 addi a0,sp,872 +80014d38: 1d4c addi a1,sp,692 80014d3a: 8000 0x8000 -80014d3c: 16a8 addi a0,sp,872 +80014d3c: 2030 fld fa2,64(s0) 80014d3e: 8000 0x8000 -80014d40: 2b74 fld fa3,208(a4) +80014d40: 1890 addi a2,sp,112 80014d42: 8000 0x8000 -80014d44: 16a8 addi a0,sp,872 +80014d44: 1890 addi a2,sp,112 80014d46: 8000 0x8000 -80014d48: 16a8 addi a0,sp,872 +80014d48: 1890 addi a2,sp,112 80014d4a: 8000 0x8000 -80014d4c: 16a8 addi a0,sp,872 +80014d4c: 1620 addi s0,sp,808 80014d4e: 8000 0x8000 -80014d50: 16a8 addi a0,sp,872 +80014d50: 1620 addi s0,sp,808 80014d52: 8000 0x8000 -80014d54: 16a8 addi a0,sp,872 +80014d54: 1620 addi s0,sp,808 80014d56: 8000 0x8000 -80014d58: 16a8 addi a0,sp,872 +80014d58: 1620 addi s0,sp,808 80014d5a: 8000 0x8000 -80014d5c: 16a8 addi a0,sp,872 +80014d5c: 2024 fld fs1,64(s0) 80014d5e: 8000 0x8000 -80014d60: 16a8 addi a0,sp,872 +80014d60: 1620 addi s0,sp,808 80014d62: 8000 0x8000 -80014d64: 1918 addi a4,sp,176 +80014d64: 1620 addi s0,sp,808 80014d66: 8000 0x8000 -80014d68: 16a8 addi a0,sp,872 +80014d68: 1fb8 addi a4,sp,1016 80014d6a: 8000 0x8000 -80014d6c: 1dd4 addi a3,sp,756 +80014d6c: 1620 addi s0,sp,808 80014d6e: 8000 0x8000 -80014d70: 29e8 fld fa0,208(a1) +80014d70: 1620 addi s0,sp,808 80014d72: 8000 0x8000 -80014d74: 1918 addi a4,sp,176 +80014d74: 1620 addi s0,sp,808 80014d76: 8000 0x8000 -80014d78: 1918 addi a4,sp,176 +80014d78: 1d78 addi a4,sp,700 80014d7a: 8000 0x8000 -80014d7c: 1918 addi a4,sp,176 +80014d7c: 1620 addi s0,sp,808 80014d7e: 8000 0x8000 -80014d80: 1f84 addi s1,sp,1008 +80014d80: 1ff0 addi a2,sp,1020 80014d82: 8000 0x8000 -80014d84: 29e8 fld fa0,208(a1) +80014d84: 1620 addi s0,sp,808 80014d86: 8000 0x8000 -80014d88: 18e0 addi s0,sp,124 +80014d88: 1620 addi s0,sp,808 80014d8a: 8000 0x8000 -80014d8c: 16a8 addi a0,sp,872 +80014d8c: 2aec fld fa1,208(a3) 80014d8e: 8000 0x8000 -80014d90: 1ee0 addi s0,sp,892 +80014d90: 1620 addi s0,sp,808 80014d92: 8000 0x8000 -80014d94: 16a8 addi a0,sp,872 +80014d94: 1620 addi s0,sp,808 80014d96: 8000 0x8000 -80014d98: 1e90 addi a2,sp,880 +80014d98: 1620 addi s0,sp,808 80014d9a: 8000 0x8000 -80014d9c: 2b88 fld fa0,16(a5) +80014d9c: 1620 addi s0,sp,808 80014d9e: 8000 0x8000 -80014da0: 1ef4 addi a3,sp,892 +80014da0: 1620 addi s0,sp,808 80014da2: 8000 0x8000 -80014da4: 18e0 addi s0,sp,124 +80014da4: 1620 addi s0,sp,808 80014da6: 8000 0x8000 -80014da8: 16a8 addi a0,sp,872 +80014da8: 1620 addi s0,sp,808 80014daa: 8000 0x8000 -80014dac: 1e00 addi s0,sp,816 +80014dac: 1620 addi s0,sp,808 80014dae: 8000 0x8000 -80014db0: 18d8 addi a4,sp,116 +80014db0: 1890 addi a2,sp,112 80014db2: 8000 0x8000 -80014db4: 2b08 fld fa0,16(a4) +80014db4: 1620 addi s0,sp,808 80014db6: 8000 0x8000 -80014db8: 16a8 addi a0,sp,872 +80014db8: 1d4c addi a1,sp,692 80014dba: 8000 0x8000 -80014dbc: 16a8 addi a0,sp,872 +80014dbc: 2960 fld fs0,208(a0) 80014dbe: 8000 0x8000 -80014dc0: 2b14 fld fa3,16(a4) +80014dc0: 1890 addi a2,sp,112 80014dc2: 8000 0x8000 -80014dc4: 16a8 addi a0,sp,872 +80014dc4: 1890 addi a2,sp,112 80014dc6: 8000 0x8000 -80014dc8: 18d8 addi a4,sp,116 +80014dc8: 1890 addi a2,sp,112 80014dca: 8000 0x8000 +80014dcc: 1efc addi a5,sp,892 +80014dce: 8000 0x8000 +80014dd0: 2960 fld fs0,208(a0) +80014dd2: 8000 0x8000 +80014dd4: 1858 addi a4,sp,52 +80014dd6: 8000 0x8000 +80014dd8: 1620 addi s0,sp,808 +80014dda: 8000 0x8000 +80014ddc: 1e58 addi a4,sp,820 +80014dde: 8000 0x8000 +80014de0: 1620 addi s0,sp,808 +80014de2: 8000 0x8000 +80014de4: 1e08 addi a0,sp,816 +80014de6: 8000 0x8000 +80014de8: 2b00 fld fs0,16(a4) +80014dea: 8000 0x8000 +80014dec: 1e6c addi a1,sp,828 +80014dee: 8000 0x8000 +80014df0: 1858 addi a4,sp,52 +80014df2: 8000 0x8000 +80014df4: 1620 addi s0,sp,808 +80014df6: 8000 0x8000 +80014df8: 1d78 addi a4,sp,700 +80014dfa: 8000 0x8000 +80014dfc: 1850 addi a2,sp,52 +80014dfe: 8000 0x8000 +80014e00: 2a80 fld fs0,16(a3) +80014e02: 8000 0x8000 +80014e04: 1620 addi s0,sp,808 +80014e06: 8000 0x8000 +80014e08: 1620 addi s0,sp,808 +80014e0a: 8000 0x8000 +80014e0c: 2a8c fld fa1,16(a3) +80014e0e: 8000 0x8000 +80014e10: 1620 addi s0,sp,808 +80014e12: 8000 0x8000 +80014e14: 1850 addi a2,sp,52 +80014e16: 8000 0x8000 -80014dcc : -80014dcc: 2020 fld fs0,64(s0) -80014dce: 2020 fld fs0,64(s0) -80014dd0: 2020 fld fs0,64(s0) -80014dd2: 2020 fld fs0,64(s0) -80014dd4: 2020 fld fs0,64(s0) -80014dd6: 2020 fld fs0,64(s0) -80014dd8: 2020 fld fs0,64(s0) -80014dda: 2020 fld fs0,64(s0) +80014e18 : +80014e18: 2020 fld fs0,64(s0) +80014e1a: 2020 fld fs0,64(s0) +80014e1c: 2020 fld fs0,64(s0) +80014e1e: 2020 fld fs0,64(s0) +80014e20: 2020 fld fs0,64(s0) +80014e22: 2020 fld fs0,64(s0) +80014e24: 2020 fld fs0,64(s0) +80014e26: 2020 fld fs0,64(s0) -80014ddc : -80014ddc: 3030 fld fa2,96(s0) -80014dde: 3030 fld fa2,96(s0) -80014de0: 3030 fld fa2,96(s0) -80014de2: 3030 fld fa2,96(s0) -80014de4: 3030 fld fa2,96(s0) -80014de6: 3030 fld fa2,96(s0) -80014de8: 3030 fld fa2,96(s0) -80014dea: 3030 fld fa2,96(s0) -80014dec: 4e20 lw s0,88(a2) -80014dee: 4e61 li t3,24 -80014df0: 0020 addi s0,sp,8 -80014df2: 0000 unimp -80014df4: 2d20 fld fs0,88(a0) -80014df6: 6e49 lui t3,0x12 -80014df8: 6966 flw fs2,88(sp) -80014dfa: 696e flw fs2,216(sp) -80014dfc: 7974 flw fa3,116(a0) -80014dfe: 0020 addi s0,sp,8 -80014e00: 4920 lw s0,80(a0) -80014e02: 666e flw fa2,216(sp) -80014e04: 6e69 lui t3,0x1a -80014e06: 7469 lui s0,0xffffa -80014e08: 2079 jal 80014e96 -80014e0a: 0000 unimp -80014e0c: 614e flw ft2,208(sp) -80014e0e: 004e c.slli zero,0x13 -80014e10: 2545 jal 800154b0 -80014e12: 0064 addi s1,sp,12 +80014e28 : +80014e28: 3030 fld fa2,96(s0) +80014e2a: 3030 fld fa2,96(s0) +80014e2c: 3030 fld fa2,96(s0) +80014e2e: 3030 fld fa2,96(s0) +80014e30: 3030 fld fa2,96(s0) +80014e32: 3030 fld fa2,96(s0) +80014e34: 3030 fld fa2,96(s0) +80014e36: 3030 fld fa2,96(s0) +80014e38: 4e20 lw s0,88(a2) +80014e3a: 4e61 li t3,24 +80014e3c: 0020 addi s0,sp,8 +80014e3e: 0000 unimp +80014e40: 2d20 fld fs0,88(a0) +80014e42: 6e49 lui t3,0x12 +80014e44: 6966 flw fs2,88(sp) +80014e46: 696e flw fs2,216(sp) +80014e48: 7974 flw fa3,116(a0) +80014e4a: 0020 addi s0,sp,8 +80014e4c: 4920 lw s0,80(a0) +80014e4e: 666e flw fa2,216(sp) +80014e50: 6e69 lui t3,0x1a +80014e52: 7469 lui s0,0xffffa +80014e54: 2079 jal 80014ee2 +80014e56: 0000 unimp +80014e58: 614e flw ft2,208(sp) +80014e5a: 004e c.slli zero,0x13 +80014e5c: 2545 jal 800154fc +80014e5e: 0064 addi s1,sp,12 -80014e14 : +80014e60 : ... -80014e28 : +80014e74 : ... -80014e38: 8000 0x8000 -80014e3a: 3fff 0x3fff +80014e84: 8000 0x8000 +80014e86: 3fff 0x3fff -80014e3c : -80014e3c: 6576 flw fa0,92(sp) -80014e3e: 4a92 lw s5,4(sp) -80014e40: 804a c.mv zero,s2 -80014e42: c94c153f 8a20979a 0x8a20979ac94c153f -80014e4a: 5202 lw tp,32(sp) -80014e4c: c460 sw s0,76(s0) -80014e4e: 7525 lui a0,0xfffe9 -80014e50: 6a32 flw fs4,12(sp) -80014e52: ce52 sw s4,28(sp) -80014e54: 329a fld ft5,416(sp) -80014e56: 28ce fld fa7,208(sp) -80014e58: a74d j 800155fa <_ctype_+0x142> -80014e5a: 5de4 lw s1,124(a1) -80014e5c: c53d beqz a0,80014eca -80014e5e: 3b5d jal 80014c14 <__clzsi2+0x310> -80014e60: 5a929e8b 0x5a929e8b -80014e64: 526c lw a1,100(a2) -80014e66: 50ce lw ra,240(sp) -80014e68: 3d28f18b 0x3d28f18b -80014e6c: 650d lui a0,0x3 -80014e6e: 81750c17 auipc s8,0x81750 -80014e72: 7586 flw fa1,96(sp) -80014e74: c976 sw t4,144(sp) -80014e76: 4d48 lw a0,28(a0) -80014e78: 9c66 add s8,s8,s9 -80014e7a: 58f8 lw a4,116(s1) -80014e7c: bc50 fsd fa2,184(s0) -80014e7e: 5c54 lw a3,60(s0) -80014e80: cc65 beqz s0,80014f78 -80014e82: 91c6 add gp,gp,a7 -80014e84: a60e fsd ft3,264(sp) -80014e86: a0ae fsd fa1,64(sp) -80014e88: e319 bnez a4,80014e8e -80014e8a: 851e46a3 0x851e46a3 -80014e8e: 98feeab7 lui s5,0x98fee -80014e92: ddbb901b 0xddbb901b -80014e96: de8d beqz a3,80014dd0 -80014e98: 9df9 0x9df9 -80014e9a: aa7eebfb 0xaa7eebfb -80014e9e: 4351 li t1,20 -80014ea0: 0235 addi tp,tp,13 -80014ea2: 36b10137 lui sp,0x36b10 -80014ea6: 336c fld fa1,224(a4) -80014ea8: 8cdfc66f jal a2,80011774 <__muldf3+0x450> -80014eac: 80e9 srli s1,s1,0x1a -80014eae: 47c9 li a5,18 -80014eb0: 93ba add t2,t2,a4 -80014eb2: 41a8 lw a0,64(a1) -80014eb4: 50f8 lw a4,100(s1) -80014eb6: c76b25fb 0xc76b25fb -80014eba: 6b71 lui s6,0x1c -80014ebc: a6d53cbf 1f49ffcf 0x1f49ffcfa6d53cbf -80014ec4: c278 sw a4,68(a2) -80014ec6: 000040d3 fadd.s ft1,ft0,ft0,rmm -80014eca: 0000 unimp -80014ecc: 0000 unimp -80014ece: 0000 unimp -80014ed0: f020 fsw fs0,96(s0) -80014ed2: b59d j 80014d38 <__clzsi2+0x434> -80014ed4: 2b70 fld fa2,208(a4) -80014ed6: ada8 fsd fa0,88(a1) -80014ed8: 9dc5 0x9dc5 -80014eda: 4069 c.li zero,26 +80014e88 : +80014e88: 6576 flw fa0,92(sp) +80014e8a: 4a92 lw s5,4(sp) +80014e8c: 804a c.mv zero,s2 +80014e8e: c94c153f 8a20979a 0x8a20979ac94c153f +80014e96: 5202 lw tp,32(sp) +80014e98: c460 sw s0,76(s0) +80014e9a: 7525 lui a0,0xfffe9 +80014e9c: 6a32 flw fs4,12(sp) +80014e9e: ce52 sw s4,28(sp) +80014ea0: 329a fld ft5,416(sp) +80014ea2: 28ce fld fa7,208(sp) +80014ea4: a74d j 80015646 +80014ea6: 5de4 lw s1,124(a1) +80014ea8: c53d beqz a0,80014f16 +80014eaa: 3b5d jal 80014c60 <__clzsi2+0x298> +80014eac: 5a929e8b 0x5a929e8b +80014eb0: 526c lw a1,100(a2) +80014eb2: 50ce lw ra,240(sp) +80014eb4: 3d28f18b 0x3d28f18b +80014eb8: 650d lui a0,0x3 +80014eba: 81750c17 auipc s8,0x81750 +80014ebe: 7586 flw fa1,96(sp) +80014ec0: c976 sw t4,144(sp) +80014ec2: 4d48 lw a0,28(a0) +80014ec4: 9c66 add s8,s8,s9 +80014ec6: 58f8 lw a4,116(s1) +80014ec8: bc50 fsd fa2,184(s0) +80014eca: 5c54 lw a3,60(s0) +80014ecc: cc65 beqz s0,80014fc4 +80014ece: 91c6 add gp,gp,a7 +80014ed0: a60e fsd ft3,264(sp) +80014ed2: a0ae fsd fa1,64(sp) +80014ed4: e319 bnez a4,80014eda +80014ed6: 851e46a3 0x851e46a3 +80014eda: 98feeab7 lui s5,0x98fee +80014ede: ddbb901b 0xddbb901b +80014ee2: de8d beqz a3,80014e1c +80014ee4: 9df9 0x9df9 +80014ee6: aa7eebfb 0xaa7eebfb +80014eea: 4351 li t1,20 +80014eec: 0235 addi tp,tp,13 +80014eee: 36b10137 lui sp,0x36b10 +80014ef2: 336c fld fa1,224(a4) +80014ef4: 8cdfc66f jal a2,800117c0 <__muldf3+0x3d8> +80014ef8: 80e9 srli s1,s1,0x1a +80014efa: 47c9 li a5,18 +80014efc: 93ba add t2,t2,a4 +80014efe: 41a8 lw a0,64(a1) +80014f00: 50f8 lw a4,100(s1) +80014f02: c76b25fb 0xc76b25fb +80014f06: 6b71 lui s6,0x1c +80014f08: a6d53cbf 1f49ffcf 0x1f49ffcfa6d53cbf +80014f10: c278 sw a4,68(a2) +80014f12: 000040d3 fadd.s ft1,ft0,ft0,rmm +80014f16: 0000 unimp +80014f18: 0000 unimp +80014f1a: 0000 unimp +80014f1c: f020 fsw fs0,96(s0) +80014f1e: b59d j 80014d84 <__clzsi2+0x3bc> +80014f20: 2b70 fld fa2,208(a4) +80014f22: ada8 fsd fa0,88(a1) +80014f24: 9dc5 0x9dc5 +80014f26: 4069 c.li zero,26 ... -80014ee8: 0400 addi s0,sp,512 -80014eea: 8e1bc9bf 00004034 0x40348e1bc9bf +80014f34: 0400 addi s0,sp,512 +80014f36: 8e1bc9bf 00004034 0x40348e1bc9bf ... -80014efe: 2000 fld fs0,0(s0) -80014f00: bebc fsd fa5,120(a3) -80014f02: 4019 c.li zero,6 +80014f4a: 2000 fld fs0,0(s0) +80014f4c: bebc fsd fa5,120(a3) +80014f4e: 4019 c.li zero,6 ... -80014f14: 9c40 0x9c40 -80014f16: 400c lw a1,0(s0) +80014f60: 9c40 0x9c40 +80014f62: 400c lw a1,0(s0) ... -80014f28: c800 sw s0,16(s0) -80014f2a: 4005 c.li zero,1 +80014f74: c800 sw s0,16(s0) +80014f76: 4005 c.li zero,1 ... -80014f3c: a000 fsd fs0,0(s0) -80014f3e: 4002 0x4002 +80014f88: a000 fsd fs0,0(s0) +80014f8a: 4002 0x4002 -80014f40 : -80014f40: 2030 fld fa2,64(s0) -80014f42: cffc sw a5,92(a5) -80014f44: 8123a1c3 fmadd.s ft3,ft7,fs2,fa6,rdn -80014f48: 9fde2de3 0x9fde2de3 -80014f4c: d2ce sw s3,100(sp) -80014f4e: 04c8 addi a0,sp,580 -80014f50: a6dd j 80015336 -80014f52: 0ad8 addi a4,sp,340 -80014f54: 8264 0x8264 -80014f56: f2ead2cb fnmsub.d ft5,fs5,fa4,ft10,unknown -80014f5a: 12d4 addi a3,sp,356 -80014f5c: 4925 li s2,9 -80014f5e: 2de4 fld fs1,216(a1) -80014f60: 3436 fld fs0,360(sp) -80014f62: ceae534f fnmadd.q ft6,ft8,fa0,fs9,unknown -80014f66: f53f256b 0xf53f256b -80014f6a: f698 fsw fa4,40(a3) -80014f6c: 01586bd3 fadd.s fs7,fa6,fs5,unknown -80014f70: 87a6 mv a5,s1 -80014f72: c0bd beqz s1,80014fd8 -80014f74: 82a5da57 0x82a5da57 -80014f78: a2a6 fsd fs1,320(sp) -80014f7a: 32b5 jal 800148e6 <__trunctfdf2+0x32e> -80014f7c: e731 bnez a4,80014fc8 -80014f7e: 04d4 addi a3,sp,580 -80014f80: e3f2 fsw ft8,196(sp) -80014f82: d332 sw a2,164(sp) -80014f84: 7132 flw ft2,44(sp) -80014f86: d21c sw a5,32(a2) -80014f88: ee32db23 0xee32db23 -80014f8c: 9049 srli s0,s0,0x32 -80014f8e: 395a fld fs2,432(sp) -80014f90: a23e fsd fa5,256(sp) -80014f92: 5308 lw a0,32(a4) -80014f94: 1155fefb 0x1155fefb -80014f98: fa91 bnez a3,80014eac -80014f9a: 1939 addi s2,s2,-18 -80014f9c: 637a flw ft6,156(sp) -80014f9e: 4325 li t1,9 -80014fa0: c031 beqz s0,80014fe4 -80014fa2: 3cac fld fa1,120(s1) -80014fa4: e26d bnez a2,80015086 -80014fa6: dbde sw s7,244(sp) -80014fa8: d05d beqz s0,80014f4e -80014faa: b3f6 fsd ft9,480(sp) -80014fac: ac7c fsd fa5,216(s0) -80014fae: e4a0 fsw fs0,72(s1) -80014fb0: 64bc flw fa5,72(s1) -80014fb2: 467c lw a5,76(a2) -80014fb4: ddd0 sw a2,60(a1) -80014fb6: 3e55 jal 80014b6a <__clzsi2+0x266> -80014fb8: 2a20 fld fs0,80(a2) -80014fba: 6224 flw fs1,64(a2) -80014fbc: 98d747b3 0x98d747b3 -80014fc0: e9a53f23 0xe9a53f23 -80014fc4: a539 j 800155d2 <_ctype_+0x11a> -80014fc6: a87fea27 0xa87fea27 -80014fca: 3f2a fld ft10,168(sp) -80014fcc: 4af20b5b 0x4af20b5b -80014fd0: a581 j 80015610 <_ctype_+0x158> -80014fd2: 18ed addi a7,a7,-5 -80014fd4: 67de flw fa5,212(sp) -80014fd6: 94ba add s1,s1,a4 -80014fd8: 4539 li a0,14 -80014fda: 1ead addi t4,t4,-21 -80014fdc: cfb1 beqz a5,80015038 -80014fde: 3f94 fld fa3,56(a5) -80014fe0: bf71 j 80014f7c -80014fe2: 7989a9b3 0x7989a9b3 -80014fe6: be68 fsd fa0,248(a2) -80014fe8: 4c2e lw s8,200(sp) -80014fea: c44de15b 0xc44de15b -80014fee: 94be add s1,s1,a5 -80014ff0: e695 bnez a3,8001501c -80014ff2: 3fc9 jal 80014fc4 -80014ff4: 3d4d jal 80014ea6 -80014ff6: 7c3d lui s8,0xfffef -80014ff8: 36ba fld fa3,424(sp) -80014ffa: fdc20d2b 0xfdc20d2b -80014ffe: cefc sw a5,92(a3) -80015000: 8461 srai s0,s0,0x18 -80015002: 7711 lui a4,0xfffe4 -80015004: abcc fsd fa1,144(a5) -80015006: 3fe4 fld fs1,248(a5) -80015008: c155 beqz a0,800150ac <__mprec_tens+0x24> -8001500a: a4a8 fsd fa0,72(s1) -8001500c: 404e 0x404e -8001500e: d3c36113 ori sp,t1,-708 -80015012: e219652b 0xe219652b -80015016: 1758 addi a4,sp,932 -80015018: 3ff1d1b7 lui gp,0x3ff1d -8001501c: d70a sw sp,172(sp) -8001501e: 0a3d70a3 0xa3d70a3 -80015022: 3d70a3d7 0x3d70a3d7 -80015026: d70a sw sp,172(sp) -80015028: 0a3d70a3 0xa3d70a3 -8001502c: 3ff8a3d7 0x3ff8a3d7 -80015030: cccd beqz s1,800150ea <__mprec_tens+0x62> -80015032: cccc sw a1,28(s1) -80015034: cccc sw a1,28(s1) -80015036: cccc sw a1,28(s1) -80015038: cccc sw a1,28(s1) -8001503a: cccc sw a1,28(s1) -8001503c: cccc sw a1,28(s1) -8001503e: cccc sw a1,28(s1) -80015040: cccc sw a1,28(s1) -80015042: 0xffff3ffb +80014f8c : +80014f8c: 2030 fld fa2,64(s0) +80014f8e: cffc sw a5,92(a5) +80014f90: 8123a1c3 fmadd.s ft3,ft7,fs2,fa6,rdn +80014f94: 9fde2de3 0x9fde2de3 +80014f98: d2ce sw s3,100(sp) +80014f9a: 04c8 addi a0,sp,580 +80014f9c: a6dd j 80015382 +80014f9e: 0ad8 addi a4,sp,340 +80014fa0: 8264 0x8264 +80014fa2: f2ead2cb fnmsub.d ft5,fs5,fa4,ft10,unknown +80014fa6: 12d4 addi a3,sp,356 +80014fa8: 4925 li s2,9 +80014faa: 2de4 fld fs1,216(a1) +80014fac: 3436 fld fs0,360(sp) +80014fae: ceae534f fnmadd.q ft6,ft8,fa0,fs9,unknown +80014fb2: f53f256b 0xf53f256b +80014fb6: f698 fsw fa4,40(a3) +80014fb8: 01586bd3 fadd.s fs7,fa6,fs5,unknown +80014fbc: 87a6 mv a5,s1 +80014fbe: c0bd beqz s1,80015024 +80014fc0: 82a5da57 0x82a5da57 +80014fc4: a2a6 fsd fs1,320(sp) +80014fc6: 32b5 jal 80014932 <__trunctfdf2+0x2b6> +80014fc8: e731 bnez a4,80015014 +80014fca: 04d4 addi a3,sp,580 +80014fcc: e3f2 fsw ft8,196(sp) +80014fce: d332 sw a2,164(sp) +80014fd0: 7132 flw ft2,44(sp) +80014fd2: d21c sw a5,32(a2) +80014fd4: ee32db23 0xee32db23 +80014fd8: 9049 srli s0,s0,0x32 +80014fda: 395a fld fs2,432(sp) +80014fdc: a23e fsd fa5,256(sp) +80014fde: 5308 lw a0,32(a4) +80014fe0: 1155fefb 0x1155fefb +80014fe4: fa91 bnez a3,80014ef8 +80014fe6: 1939 addi s2,s2,-18 +80014fe8: 637a flw ft6,156(sp) +80014fea: 4325 li t1,9 +80014fec: c031 beqz s0,80015030 +80014fee: 3cac fld fa1,120(s1) +80014ff0: e26d bnez a2,800150d2 <__mprec_tens+0xa> +80014ff2: dbde sw s7,244(sp) +80014ff4: d05d beqz s0,80014f9a +80014ff6: b3f6 fsd ft9,480(sp) +80014ff8: ac7c fsd fa5,216(s0) +80014ffa: e4a0 fsw fs0,72(s1) +80014ffc: 64bc flw fa5,72(s1) +80014ffe: 467c lw a5,76(a2) +80015000: ddd0 sw a2,60(a1) +80015002: 3e55 jal 80014bb6 <__clzsi2+0x1ee> +80015004: 2a20 fld fs0,80(a2) +80015006: 6224 flw fs1,64(a2) +80015008: 98d747b3 0x98d747b3 +8001500c: e9a53f23 0xe9a53f23 +80015010: a539 j 8001561e +80015012: a87fea27 0xa87fea27 +80015016: 3f2a fld ft10,168(sp) +80015018: 4af20b5b 0x4af20b5b +8001501c: a581 j 8001565c +8001501e: 18ed addi a7,a7,-5 +80015020: 67de flw fa5,212(sp) +80015022: 94ba add s1,s1,a4 +80015024: 4539 li a0,14 +80015026: 1ead addi t4,t4,-21 +80015028: cfb1 beqz a5,80015084 +8001502a: 3f94 fld fa3,56(a5) +8001502c: bf71 j 80014fc8 +8001502e: 7989a9b3 0x7989a9b3 +80015032: be68 fsd fa0,248(a2) +80015034: 4c2e lw s8,200(sp) +80015036: c44de15b 0xc44de15b +8001503a: 94be add s1,s1,a5 +8001503c: e695 bnez a3,80015068 +8001503e: 3fc9 jal 80015010 +80015040: 3d4d jal 80014ef2 +80015042: 7c3d lui s8,0xfffef +80015044: 36ba fld fa3,424(sp) +80015046: fdc20d2b 0xfdc20d2b +8001504a: cefc sw a5,92(a3) +8001504c: 8461 srai s0,s0,0x18 +8001504e: 7711 lui a4,0xfffe4 +80015050: abcc fsd fa1,144(a5) +80015052: 3fe4 fld fs1,248(a5) +80015054: c155 beqz a0,800150f8 <__mprec_tens+0x30> +80015056: a4a8 fsd fa0,72(s1) +80015058: 404e 0x404e +8001505a: d3c36113 ori sp,t1,-708 +8001505e: e219652b 0xe219652b +80015062: 1758 addi a4,sp,932 +80015064: 3ff1d1b7 lui gp,0x3ff1d +80015068: d70a sw sp,172(sp) +8001506a: 0a3d70a3 0xa3d70a3 +8001506e: 3d70a3d7 0x3d70a3d7 +80015072: d70a sw sp,172(sp) +80015074: 0a3d70a3 0xa3d70a3 +80015078: 3ff8a3d7 0x3ff8a3d7 +8001507c: cccd beqz s1,80015136 <__mprec_tens+0x6e> +8001507e: cccc sw a1,28(s1) +80015080: cccc sw a1,28(s1) +80015082: cccc sw a1,28(s1) +80015084: cccc sw a1,28(s1) +80015086: cccc sw a1,28(s1) +80015088: cccc sw a1,28(s1) +8001508a: cccc sw a1,28(s1) +8001508c: cccc sw a1,28(s1) +8001508e: 0xffff3ffb -80015044 : -80015044: ffff 0xffff -80015046: fffe fsw ft11,252(sp) -80015048: fffc fsw fa5,124(a5) -8001504a: fff8 fsw fa4,124(a5) -8001504c: fff0 fsw fa2,124(a5) -8001504e: ffe0 fsw fs0,124(a5) -80015050: ffc0 fsw fs0,60(a5) -80015052: ff80 fsw fs0,56(a5) -80015054: ff00 fsw fs0,56(a4) -80015056: fe00 fsw fs0,56(a2) -80015058: fc00 fsw fs0,56(s0) -8001505a: f800 fsw fs0,48(s0) -8001505c: f000 fsw fs0,32(s0) -8001505e: e000 fsw fs0,0(s0) -80015060: c000 sw s0,0(s0) -80015062: 8000 0x8000 -80015064: 0000 unimp -80015066: 0000 unimp -80015068: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne -8001506c: 4f50 lw a2,28(a4) -8001506e: 00584953 fadd.s fs2,fa6,ft5,rmm -80015072: 0000 unimp -80015074: 002e c.slli zero,0xb +80015090 : +80015090: ffff 0xffff +80015092: fffe fsw ft11,252(sp) +80015094: fffc fsw fa5,124(a5) +80015096: fff8 fsw fa4,124(a5) +80015098: fff0 fsw fa2,124(a5) +8001509a: ffe0 fsw fs0,124(a5) +8001509c: ffc0 fsw fs0,60(a5) +8001509e: ff80 fsw fs0,56(a5) +800150a0: ff00 fsw fs0,56(a4) +800150a2: fe00 fsw fs0,56(a2) +800150a4: fc00 fsw fs0,56(s0) +800150a6: f800 fsw fs0,48(s0) +800150a8: f000 fsw fs0,32(s0) +800150aa: e000 fsw fs0,0(s0) +800150ac: c000 sw s0,0(s0) +800150ae: 8000 0x8000 ... -80015078 : -80015078: 0005 c.nop 1 -8001507a: 0000 unimp -8001507c: 0019 c.nop 6 -8001507e: 0000 unimp -80015080: 007d c.nop 31 -80015082: 0000 unimp -80015084: 0000 unimp - ... - -80015088 <__mprec_tens>: -80015088: 0000 unimp -8001508a: 0000 unimp -8001508c: 0000 unimp -8001508e: 3ff0 fld fa2,248(a5) -80015090: 0000 unimp -80015092: 0000 unimp -80015094: 0000 unimp -80015096: 4024 lw s1,64(s0) -80015098: 0000 unimp -8001509a: 0000 unimp -8001509c: 0000 unimp -8001509e: 4059 c.li zero,22 -800150a0: 0000 unimp -800150a2: 0000 unimp -800150a4: 4000 lw s0,0(s0) -800150a6: 0000408f 0x408f -800150aa: 0000 unimp -800150ac: 8800 0x8800 -800150ae: 000040c3 fmadd.s ft1,ft0,ft0,ft0,rmm -800150b2: 0000 unimp -800150b4: 6a00 flw fs0,16(a2) -800150b6: 40f8 lw a4,68(s1) -800150b8: 0000 unimp +800150b8 : +800150b8: 0005 c.nop 1 800150ba: 0000 unimp -800150bc: 8480 0x8480 -800150be: 412e lw sp,200(sp) -800150c0: 0000 unimp +800150bc: 0019 c.nop 6 +800150be: 0000 unimp +800150c0: 007d c.nop 31 800150c2: 0000 unimp -800150c4: 12d0 addi a2,sp,356 -800150c6: 00004163 bltz zero,800150c8 <__mprec_tens+0x40> -800150ca: 0000 unimp -800150cc: d784 sw s1,40(a5) -800150ce: 00004197 auipc gp,0x4 -800150d2: 0000 unimp -800150d4: cd65 beqz a0,800151cc <__mprec_bigtens+0x54> -800150d6: 41cd li gp,19 -800150d8: 0000 unimp -800150da: 2000 fld fs0,0(s0) -800150dc: a05f 4202 0000 0x4202a05f -800150e2: e800 fsw fs0,16(s0) -800150e4: 4876 lw a6,92(sp) -800150e6: 00004237 lui tp,0x4 -800150ea: a200 fsd fs0,0(a2) -800150ec: 1a94 addi a3,sp,368 -800150ee: 426d li tp,27 -800150f0: 0000 unimp -800150f2: e540 fsw fs0,12(a0) -800150f4: 309c fld fa5,32(s1) -800150f6: 42a2 lw t0,8(sp) -800150f8: 0000 unimp -800150fa: 1e90 addi a2,sp,880 -800150fc: bcc4 fsd fs1,184(s1) -800150fe: 42d6 lw t0,84(sp) -80015100: 0000 unimp -80015102: 2634 fld fa3,72(a2) -80015104: 6bf5 lui s7,0x1d -80015106: 430c lw a1,0(a4) -80015108: 8000 0x8000 -8001510a: 37e0 fld fs0,232(a5) -8001510c: c379 beqz a4,800151d2 <__mprec_bigtens+0x5a> -8001510e: 4341 li t1,16 -80015110: a000 fsd fs0,0(s0) -80015112: 85d8 0x85d8 -80015114: 43763457 0x43763457 -80015118: c800 sw s0,16(s0) -8001511a: 674e flw fa4,208(sp) -8001511c: c16d beqz a0,800151fe <__mprec_bigtens+0x86> -8001511e: 3d0043ab 0x3d0043ab -80015122: 6091 lui ra,0x4 -80015124: 58e4 lw s1,116(s1) -80015126: 43e1 li t2,24 -80015128: 8c40 0x8c40 -8001512a: 78b5 lui a7,0xfffed -8001512c: af1d j 80015862 <__clz_tab+0x66> -8001512e: 4415 li s0,5 -80015130: ef50 fsw fa2,28(a4) -80015132: d6e2 sw s8,108(sp) -80015134: 1ae4 addi s1,sp,380 -80015136: d592444b 0xd592444b -8001513a: 064d addi a2,a2,19 -8001513c: 4480f0cf 0x4480f0cf -80015140: 4af6 lw s5,92(sp) -80015142: c7e1 beqz a5,8001520a <__mprec_bigtens+0x92> -80015144: 2d02 fld fs10,0(sp) -80015146: 44b5 li s1,13 -80015148: 9db4 0x9db4 -8001514a: 79d9 lui s3,0xffff6 -8001514c: 44ea7843 0x44ea7843 - -80015150 <__mprec_tinytens>: -80015150: 89bc 0x89bc -80015152: 97d8 0x97d8 -80015154: d2b2 sw a2,100(sp) -80015156: 3c9c fld fa5,56(s1) -80015158: d5a8a733 0xd5a8a733 -8001515c: 3949f623 0x3949f623 -80015160: a73d j 8001588e <__clz_tab+0x92> -80015162: 44f4 lw a3,76(s1) -80015164: 0ffd addi t6,t6,31 -80015166: 32a5 jal 80014ace <__clzsi2+0x1ca> -80015168: 979d srai a5,a5,0x27 -8001516a: cf8c sw a1,24(a5) -8001516c: ba08 fsd fa0,48(a2) -8001516e: 6f43255b 0x6f43255b -80015172: 64ac flw fa1,72(s1) -80015174: 0628 addi a0,sp,776 -80015176: 0ac8 addi a0,sp,340 - -80015178 <__mprec_bigtens>: -80015178: 8000 0x8000 -8001517a: 37e0 fld fs0,232(a5) -8001517c: c379 beqz a4,80015242 <__mprec_bigtens+0xca> -8001517e: 4341 li t1,16 -80015180: b5056e17 auipc t3,0xb5056 -80015184: b8b5 j 80014a00 <__clzsi2+0xfc> -80015186: f9f54693 xori a3,a0,-97 -8001518a: 4f03e93f 1d324d38 0x1d324d384f03e93f -80015192: f930 fsw fa2,112(a0) -80015194: 7748 flw fa0,44(a4) -80015196: 5a82 lw s5,32(sp) -80015198: bf3c fsd fa5,120(a4) -8001519a: 4fdd7f73 csrrci t5,0x4fd,26 -8001519e: 7515 lui a0,0xfffe5 -800151a0: a878 fsd fa4,208(s0) -800151a2: 8000 0x8000 -800151a4: 9ea0 0x9ea0 -800151a6: 8000 0x8000 -800151a8: 9ea0 0x9ea0 -800151aa: 8000 0x8000 -800151ac: a86c fsd fa1,208(s0) -800151ae: 8000 0x8000 -800151b0: 9ea0 0x9ea0 -800151b2: 8000 0x8000 -800151b4: 9ea0 0x9ea0 -800151b6: 8000 0x8000 -800151b8: 9ea0 0x9ea0 -800151ba: 8000 0x8000 -800151bc: a048 fsd fa0,128(s0) -800151be: 8000 0x8000 -800151c0: 9ea0 0x9ea0 -800151c2: 8000 0x8000 -800151c4: 9ea0 0x9ea0 -800151c6: 8000 0x8000 -800151c8: a848 fsd fa0,144(s0) -800151ca: 8000 0x8000 -800151cc: a8e0 fsd fs0,208(s1) -800151ce: 8000 0x8000 -800151d0: 9ea0 0x9ea0 -800151d2: 8000 0x8000 -800151d4: a6bc fsd fa5,72(a3) -800151d6: 8000 0x8000 -800151d8: a89c fsd fa5,16(s1) -800151da: 8000 0x8000 -800151dc: 9ea0 0x9ea0 -800151de: 8000 0x8000 -800151e0: a890 fsd fa2,16(s1) -800151e2: 8000 0x8000 -800151e4: 9e70 0x9e70 -800151e6: 8000 0x8000 -800151e8: 9e70 0x9e70 -800151ea: 8000 0x8000 -800151ec: 9e70 0x9e70 -800151ee: 8000 0x8000 -800151f0: 9e70 0x9e70 -800151f2: 8000 0x8000 -800151f4: 9e70 0x9e70 -800151f6: 8000 0x8000 -800151f8: 9e70 0x9e70 -800151fa: 8000 0x8000 -800151fc: 9e70 0x9e70 -800151fe: 8000 0x8000 -80015200: 9e70 0x9e70 -80015202: 8000 0x8000 -80015204: 9e70 0x9e70 -80015206: 8000 0x8000 -80015208: 9ea0 0x9ea0 -8001520a: 8000 0x8000 -8001520c: 9ea0 0x9ea0 -8001520e: 8000 0x8000 -80015210: 9ea0 0x9ea0 -80015212: 8000 0x8000 -80015214: 9ea0 0x9ea0 -80015216: 8000 0x8000 -80015218: 9ea0 0x9ea0 -8001521a: 8000 0x8000 -8001521c: 9ea0 0x9ea0 -8001521e: 8000 0x8000 -80015220: 9ea0 0x9ea0 -80015222: 8000 0x8000 -80015224: a0c4 fsd fs1,128(s1) -80015226: 8000 0x8000 -80015228: 9ea0 0x9ea0 -8001522a: 8000 0x8000 -8001522c: a690 fsd fa2,8(a3) -8001522e: 8000 0x8000 -80015230: a8f0 fsd fa2,208(s1) -80015232: 8000 0x8000 -80015234: a0c4 fsd fs1,128(s1) -80015236: 8000 0x8000 -80015238: a0c4 fsd fs1,128(s1) -8001523a: 8000 0x8000 -8001523c: a0c4 fsd fs1,128(s1) -8001523e: 8000 0x8000 -80015240: 9ea0 0x9ea0 -80015242: 8000 0x8000 -80015244: 9ea0 0x9ea0 -80015246: 8000 0x8000 -80015248: 9ea0 0x9ea0 -8001524a: 8000 0x8000 -8001524c: 9ea0 0x9ea0 -8001524e: 8000 0x8000 -80015250: a83c fsd fa5,80(s0) -80015252: 8000 0x8000 -80015254: 9ea0 0x9ea0 -80015256: 8000 0x8000 -80015258: 9ea0 0x9ea0 -8001525a: 8000 0x8000 -8001525c: a7bc fsd fa5,72(a5) -8001525e: 8000 0x8000 -80015260: 9ea0 0x9ea0 -80015262: 8000 0x8000 -80015264: 9ea0 0x9ea0 -80015266: 8000 0x8000 -80015268: 9ea0 0x9ea0 -8001526a: 8000 0x8000 -8001526c: a60c fsd fa1,8(a2) -8001526e: 8000 0x8000 -80015270: 9ea0 0x9ea0 -80015272: 8000 0x8000 -80015274: a808 fsd fa0,16(s0) -80015276: 8000 0x8000 -80015278: 9ea0 0x9ea0 -8001527a: 8000 0x8000 -8001527c: 9ea0 0x9ea0 -8001527e: 8000 0x8000 -80015280: b2a0 fsd fs0,96(a3) -80015282: 8000 0x8000 -80015284: 9ea0 0x9ea0 -80015286: 8000 0x8000 -80015288: 9ea0 0x9ea0 -8001528a: 8000 0x8000 -8001528c: 9ea0 0x9ea0 -8001528e: 8000 0x8000 -80015290: 9ea0 0x9ea0 -80015292: 8000 0x8000 -80015294: 9ea0 0x9ea0 -80015296: 8000 0x8000 -80015298: 9ea0 0x9ea0 -8001529a: 8000 0x8000 -8001529c: 9ea0 0x9ea0 -8001529e: 8000 0x8000 -800152a0: 9ea0 0x9ea0 -800152a2: 8000 0x8000 -800152a4: a0c4 fsd fs1,128(s1) -800152a6: 8000 0x8000 -800152a8: 9ea0 0x9ea0 -800152aa: 8000 0x8000 -800152ac: a690 fsd fa2,8(a3) -800152ae: 8000 0x8000 -800152b0: b148 fsd fa0,160(a0) -800152b2: 8000 0x8000 -800152b4: a0c4 fsd fs1,128(s1) -800152b6: 8000 0x8000 -800152b8: a0c4 fsd fs1,128(s1) -800152ba: 8000 0x8000 -800152bc: a0c4 fsd fs1,128(s1) -800152be: 8000 0x8000 -800152c0: a7f4 fsd fa3,200(a5) -800152c2: 8000 0x8000 -800152c4: b148 fsd fa0,160(a0) -800152c6: 8000 0x8000 -800152c8: a08c fsd fa1,0(s1) -800152ca: 8000 0x8000 -800152cc: 9ea0 0x9ea0 -800152ce: 8000 0x8000 -800152d0: a718 fsd fa4,8(a4) -800152d2: 8000 0x8000 -800152d4: 9ea0 0x9ea0 -800152d6: 8000 0x8000 -800152d8: a6c8 fsd fa0,136(a3) -800152da: 8000 0x8000 -800152dc: b2b4 fsd fa3,96(a3) -800152de: 8000 0x8000 -800152e0: a72c fsd fa1,72(a4) -800152e2: 8000 0x8000 -800152e4: a08c fsd fa1,0(s1) -800152e6: 8000 0x8000 -800152e8: 9ea0 0x9ea0 -800152ea: 8000 0x8000 -800152ec: a60c fsd fa1,8(a2) -800152ee: 8000 0x8000 -800152f0: a084 fsd fs1,0(s1) -800152f2: 8000 0x8000 -800152f4: b214 fsd fa3,32(a2) -800152f6: 8000 0x8000 -800152f8: 9ea0 0x9ea0 -800152fa: 8000 0x8000 -800152fc: 9ea0 0x9ea0 -800152fe: 8000 0x8000 -80015300: b220 fsd fs0,96(a2) -80015302: 8000 0x8000 -80015304: 9ea0 0x9ea0 -80015306: 8000 0x8000 -80015308: a084 fsd fs1,0(s1) -8001530a: 8000 0x8000 - -8001530c : -8001530c: 2020 fld fs0,64(s0) -8001530e: 2020 fld fs0,64(s0) -80015310: 2020 fld fs0,64(s0) -80015312: 2020 fld fs0,64(s0) -80015314: 2020 fld fs0,64(s0) -80015316: 2020 fld fs0,64(s0) -80015318: 2020 fld fs0,64(s0) -8001531a: 2020 fld fs0,64(s0) - -8001531c : -8001531c: 3030 fld fa2,96(s0) -8001531e: 3030 fld fa2,96(s0) -80015320: 3030 fld fa2,96(s0) -80015322: 3030 fld fa2,96(s0) -80015324: 3030 fld fa2,96(s0) -80015326: 3030 fld fa2,96(s0) -80015328: 3030 fld fa2,96(s0) -8001532a: 3030 fld fa2,96(s0) -8001532c: cf98 sw a4,24(a5) -8001532e: 8000 0x8000 -80015330: ca08 sw a0,16(a2) -80015332: 8000 0x8000 -80015334: ca08 sw a0,16(a2) -80015336: 8000 0x8000 -80015338: cf8c sw a1,24(a5) -8001533a: 8000 0x8000 -8001533c: ca08 sw a0,16(a2) -8001533e: 8000 0x8000 -80015340: ca08 sw a0,16(a2) -80015342: 8000 0x8000 -80015344: ca08 sw a0,16(a2) -80015346: 8000 0x8000 -80015348: cbd0 sw a2,20(a5) -8001534a: 8000 0x8000 -8001534c: ca08 sw a0,16(a2) -8001534e: 8000 0x8000 -80015350: ca08 sw a0,16(a2) -80015352: 8000 0x8000 -80015354: cf60 sw s0,92(a4) -80015356: 8000 0x8000 -80015358: cfbc sw a5,88(a5) -8001535a: 8000 0x8000 -8001535c: ca08 sw a0,16(a2) -8001535e: 8000 0x8000 -80015360: cfb0 sw a2,88(a5) -80015362: 8000 0x8000 -80015364: cfcc sw a1,28(a5) -80015366: 8000 0x8000 -80015368: ca08 sw a0,16(a2) -8001536a: 8000 0x8000 -8001536c: cf54 sw a3,28(a4) -8001536e: 8000 0x8000 -80015370: c9d0 sw a2,20(a1) -80015372: 8000 0x8000 -80015374: c9d0 sw a2,20(a1) -80015376: 8000 0x8000 -80015378: c9d0 sw a2,20(a1) -8001537a: 8000 0x8000 -8001537c: c9d0 sw a2,20(a1) -8001537e: 8000 0x8000 -80015380: c9d0 sw a2,20(a1) -80015382: 8000 0x8000 -80015384: c9d0 sw a2,20(a1) -80015386: 8000 0x8000 -80015388: c9d0 sw a2,20(a1) -8001538a: 8000 0x8000 -8001538c: c9d0 sw a2,20(a1) -8001538e: 8000 0x8000 -80015390: c9d0 sw a2,20(a1) -80015392: 8000 0x8000 -80015394: ca08 sw a0,16(a2) -80015396: 8000 0x8000 -80015398: ca08 sw a0,16(a2) -8001539a: 8000 0x8000 -8001539c: ca08 sw a0,16(a2) -8001539e: 8000 0x8000 -800153a0: ca08 sw a0,16(a2) -800153a2: 8000 0x8000 -800153a4: ca08 sw a0,16(a2) -800153a6: 8000 0x8000 -800153a8: ca08 sw a0,16(a2) -800153aa: 8000 0x8000 -800153ac: ca08 sw a0,16(a2) -800153ae: 8000 0x8000 -800153b0: ca08 sw a0,16(a2) -800153b2: 8000 0x8000 -800153b4: ca08 sw a0,16(a2) -800153b6: 8000 0x8000 -800153b8: ce9c sw a5,24(a3) -800153ba: 8000 0x8000 -800153bc: cc20 sw s0,88(s0) -800153be: 8000 0x8000 -800153c0: ca08 sw a0,16(a2) -800153c2: 8000 0x8000 -800153c4: ca08 sw a0,16(a2) -800153c6: 8000 0x8000 -800153c8: ca08 sw a0,16(a2) -800153ca: 8000 0x8000 -800153cc: ca08 sw a0,16(a2) -800153ce: 8000 0x8000 -800153d0: ca08 sw a0,16(a2) -800153d2: 8000 0x8000 -800153d4: ca08 sw a0,16(a2) -800153d6: 8000 0x8000 -800153d8: ca08 sw a0,16(a2) -800153da: 8000 0x8000 -800153dc: ca08 sw a0,16(a2) -800153de: 8000 0x8000 -800153e0: ca08 sw a0,16(a2) -800153e2: 8000 0x8000 -800153e4: ca08 sw a0,16(a2) -800153e6: 8000 0x8000 -800153e8: cce8 sw a0,92(s1) -800153ea: 8000 0x8000 -800153ec: ca08 sw a0,16(a2) -800153ee: 8000 0x8000 -800153f0: ca08 sw a0,16(a2) -800153f2: 8000 0x8000 -800153f4: ca08 sw a0,16(a2) -800153f6: 8000 0x8000 -800153f8: ce5c sw a5,28(a2) -800153fa: 8000 0x8000 -800153fc: ca08 sw a0,16(a2) -800153fe: 8000 0x8000 -80015400: cf24 sw s1,88(a4) -80015402: 8000 0x8000 -80015404: ca08 sw a0,16(a2) -80015406: 8000 0x8000 -80015408: ca08 sw a0,16(a2) -8001540a: 8000 0x8000 -8001540c: d714 sw a3,40(a4) -8001540e: 8000 0x8000 -80015410: ca08 sw a0,16(a2) -80015412: 8000 0x8000 -80015414: ca08 sw a0,16(a2) -80015416: 8000 0x8000 -80015418: ca08 sw a0,16(a2) -8001541a: 8000 0x8000 -8001541c: ca08 sw a0,16(a2) -8001541e: 8000 0x8000 -80015420: ca08 sw a0,16(a2) -80015422: 8000 0x8000 -80015424: ca08 sw a0,16(a2) -80015426: 8000 0x8000 -80015428: ca08 sw a0,16(a2) -8001542a: 8000 0x8000 -8001542c: ca08 sw a0,16(a2) -8001542e: 8000 0x8000 -80015430: ca08 sw a0,16(a2) -80015432: 8000 0x8000 -80015434: ca08 sw a0,16(a2) -80015436: 8000 0x8000 -80015438: ce9c sw a5,24(a3) -8001543a: 8000 0x8000 -8001543c: cc24 sw s1,88(s0) -8001543e: 8000 0x8000 -80015440: ca08 sw a0,16(a2) -80015442: 8000 0x8000 -80015444: ca08 sw a0,16(a2) -80015446: 8000 0x8000 -80015448: ca08 sw a0,16(a2) -8001544a: 8000 0x8000 -8001544c: cf10 sw a2,24(a4) -8001544e: 8000 0x8000 -80015450: cc24 sw s1,88(s0) -80015452: 8000 0x8000 -80015454: cc14 sw a3,24(s0) -80015456: 8000 0x8000 -80015458: ca08 sw a0,16(a2) -8001545a: 8000 0x8000 -8001545c: cefc sw a5,92(a3) -8001545e: 8000 0x8000 -80015460: ca08 sw a0,16(a2) -80015462: 8000 0x8000 -80015464: d00c sw a1,32(s0) -80015466: 8000 0x8000 -80015468: ccec sw a1,92(s1) -8001546a: 8000 0x8000 -8001546c: cec4 sw s1,28(a3) -8001546e: 8000 0x8000 -80015470: cc14 sw a3,24(s0) -80015472: 8000 0x8000 -80015474: ca08 sw a0,16(a2) -80015476: 8000 0x8000 -80015478: ce5c sw a5,28(a2) -8001547a: 8000 0x8000 -8001547c: cc0c sw a1,24(s0) -8001547e: 8000 0x8000 -80015480: d70c sw a1,40(a4) -80015482: 8000 0x8000 -80015484: ca08 sw a0,16(a2) -80015486: 8000 0x8000 -80015488: ca08 sw a0,16(a2) -8001548a: 8000 0x8000 -8001548c: d770 sw a2,108(a4) -8001548e: 8000 0x8000 -80015490: ca08 sw a0,16(a2) -80015492: 8000 0x8000 -80015494: cc0c sw a1,24(s0) -80015496: 8000 0x8000 - -80015498 : -80015498: 2020 fld fs0,64(s0) -8001549a: 2020 fld fs0,64(s0) -8001549c: 2020 fld fs0,64(s0) -8001549e: 2020 fld fs0,64(s0) -800154a0: 2020 fld fs0,64(s0) -800154a2: 2020 fld fs0,64(s0) -800154a4: 2020 fld fs0,64(s0) -800154a6: 2020 fld fs0,64(s0) - -800154a8 : -800154a8: 3030 fld fa2,96(s0) -800154aa: 3030 fld fa2,96(s0) -800154ac: 3030 fld fa2,96(s0) -800154ae: 3030 fld fa2,96(s0) -800154b0: 3030 fld fa2,96(s0) -800154b2: 3030 fld fa2,96(s0) -800154b4: 3030 fld fa2,96(s0) -800154b6: 3030 fld fa2,96(s0) - -800154b8 <_ctype_>: -800154b8: 2000 fld fs0,0(s0) -800154ba: 2020 fld fs0,64(s0) -800154bc: 2020 fld fs0,64(s0) -800154be: 2020 fld fs0,64(s0) -800154c0: 2020 fld fs0,64(s0) -800154c2: 2828 fld fa0,80(s0) -800154c4: 2828 fld fa0,80(s0) -800154c6: 2028 fld fa0,64(s0) -800154c8: 2020 fld fs0,64(s0) -800154ca: 2020 fld fs0,64(s0) -800154cc: 2020 fld fs0,64(s0) -800154ce: 2020 fld fs0,64(s0) -800154d0: 2020 fld fs0,64(s0) -800154d2: 2020 fld fs0,64(s0) -800154d4: 2020 fld fs0,64(s0) -800154d6: 2020 fld fs0,64(s0) -800154d8: 8820 0x8820 -800154da: 1010 addi a2,sp,32 -800154dc: 1010 addi a2,sp,32 -800154de: 1010 addi a2,sp,32 -800154e0: 1010 addi a2,sp,32 -800154e2: 1010 addi a2,sp,32 -800154e4: 1010 addi a2,sp,32 -800154e6: 1010 addi a2,sp,32 -800154e8: 0410 addi a2,sp,512 -800154ea: 0404 addi s1,sp,512 -800154ec: 0404 addi s1,sp,512 -800154ee: 0404 addi s1,sp,512 -800154f0: 0404 addi s1,sp,512 -800154f2: 1004 addi s1,sp,32 -800154f4: 1010 addi a2,sp,32 -800154f6: 1010 addi a2,sp,32 -800154f8: 1010 addi a2,sp,32 -800154fa: 4141 li sp,16 -800154fc: 4141 li sp,16 -800154fe: 4141 li sp,16 -80015500: 0101 addi sp,sp,0 -80015502: 0101 addi sp,sp,0 -80015504: 0101 addi sp,sp,0 -80015506: 0101 addi sp,sp,0 -80015508: 0101 addi sp,sp,0 -8001550a: 0101 addi sp,sp,0 -8001550c: 0101 addi sp,sp,0 -8001550e: 0101 addi sp,sp,0 -80015510: 0101 addi sp,sp,0 -80015512: 0101 addi sp,sp,0 -80015514: 1010 addi a2,sp,32 -80015516: 1010 addi a2,sp,32 -80015518: 1010 addi a2,sp,32 -8001551a: 4242 lw tp,16(sp) -8001551c: 4242 lw tp,16(sp) -8001551e: 4242 lw tp,16(sp) -80015520: 0202 c.slli64 tp -80015522: 0202 c.slli64 tp -80015524: 0202 c.slli64 tp -80015526: 0202 c.slli64 tp -80015528: 0202 c.slli64 tp -8001552a: 0202 c.slli64 tp -8001552c: 0202 c.slli64 tp -8001552e: 0202 c.slli64 tp -80015530: 0202 c.slli64 tp -80015532: 0202 c.slli64 tp -80015534: 1010 addi a2,sp,32 -80015536: 1010 addi a2,sp,32 -80015538: 0020 addi s0,sp,8 +800150c4: 0000 unimp ... -800155ba: 0000 unimp -800155bc: f788 fsw fa0,40(a5) + +800150c8 <__mprec_tens>: +800150c8: 0000 unimp +800150ca: 0000 unimp +800150cc: 0000 unimp +800150ce: 3ff0 fld fa2,248(a5) +800150d0: 0000 unimp +800150d2: 0000 unimp +800150d4: 0000 unimp +800150d6: 4024 lw s1,64(s0) +800150d8: 0000 unimp +800150da: 0000 unimp +800150dc: 0000 unimp +800150de: 4059 c.li zero,22 +800150e0: 0000 unimp +800150e2: 0000 unimp +800150e4: 4000 lw s0,0(s0) +800150e6: 0000408f 0x408f +800150ea: 0000 unimp +800150ec: 8800 0x8800 +800150ee: 000040c3 fmadd.s ft1,ft0,ft0,ft0,rmm +800150f2: 0000 unimp +800150f4: 6a00 flw fs0,16(a2) +800150f6: 40f8 lw a4,68(s1) +800150f8: 0000 unimp +800150fa: 0000 unimp +800150fc: 8480 0x8480 +800150fe: 412e lw sp,200(sp) +80015100: 0000 unimp +80015102: 0000 unimp +80015104: 12d0 addi a2,sp,356 +80015106: 00004163 bltz zero,80015108 <__mprec_tens+0x40> +8001510a: 0000 unimp +8001510c: d784 sw s1,40(a5) +8001510e: 00004197 auipc gp,0x4 +80015112: 0000 unimp +80015114: cd65 beqz a0,8001520c <__mprec_bigtens+0x54> +80015116: 41cd li gp,19 +80015118: 0000 unimp +8001511a: 2000 fld fs0,0(s0) +8001511c: a05f 4202 0000 0x4202a05f +80015122: e800 fsw fs0,16(s0) +80015124: 4876 lw a6,92(sp) +80015126: 00004237 lui tp,0x4 +8001512a: a200 fsd fs0,0(a2) +8001512c: 1a94 addi a3,sp,368 +8001512e: 426d li tp,27 +80015130: 0000 unimp +80015132: e540 fsw fs0,12(a0) +80015134: 309c fld fa5,32(s1) +80015136: 42a2 lw t0,8(sp) +80015138: 0000 unimp +8001513a: 1e90 addi a2,sp,880 +8001513c: bcc4 fsd fs1,184(s1) +8001513e: 42d6 lw t0,84(sp) +80015140: 0000 unimp +80015142: 2634 fld fa3,72(a2) +80015144: 6bf5 lui s7,0x1d +80015146: 430c lw a1,0(a4) +80015148: 8000 0x8000 +8001514a: 37e0 fld fs0,232(a5) +8001514c: c379 beqz a4,80015212 <__mprec_bigtens+0x5a> +8001514e: 4341 li t1,16 +80015150: a000 fsd fs0,0(s0) +80015152: 85d8 0x85d8 +80015154: 43763457 0x43763457 +80015158: c800 sw s0,16(s0) +8001515a: 674e flw fa4,208(sp) +8001515c: c16d beqz a0,8001523e <__mprec_bigtens+0x86> +8001515e: 3d0043ab 0x3d0043ab +80015162: 6091 lui ra,0x4 +80015164: 58e4 lw s1,116(s1) +80015166: 43e1 li t2,24 +80015168: 8c40 0x8c40 +8001516a: 78b5 lui a7,0xfffed +8001516c: af1d j 800158a2 <__clz_tab+0x56> +8001516e: 4415 li s0,5 +80015170: ef50 fsw fa2,28(a4) +80015172: d6e2 sw s8,108(sp) +80015174: 1ae4 addi s1,sp,380 +80015176: d592444b 0xd592444b +8001517a: 064d addi a2,a2,19 +8001517c: 4480f0cf 0x4480f0cf +80015180: 4af6 lw s5,92(sp) +80015182: c7e1 beqz a5,8001524a <__mprec_bigtens+0x92> +80015184: 2d02 fld fs10,0(sp) +80015186: 44b5 li s1,13 +80015188: 9db4 0x9db4 +8001518a: 79d9 lui s3,0xffff6 +8001518c: 44ea7843 0x44ea7843 + +80015190 <__mprec_tinytens>: +80015190: 89bc 0x89bc +80015192: 97d8 0x97d8 +80015194: d2b2 sw a2,100(sp) +80015196: 3c9c fld fa5,56(s1) +80015198: d5a8a733 0xd5a8a733 +8001519c: 3949f623 0x3949f623 +800151a0: a73d j 800158ce <__clz_tab+0x82> +800151a2: 44f4 lw a3,76(s1) +800151a4: 0ffd addi t6,t6,31 +800151a6: 32a5 jal 80014b0e <__clzsi2+0x146> +800151a8: 979d srai a5,a5,0x27 +800151aa: cf8c sw a1,24(a5) +800151ac: ba08 fsd fa0,48(a2) +800151ae: 6f43255b 0x6f43255b +800151b2: 64ac flw fa1,72(s1) +800151b4: 0628 addi a0,sp,776 +800151b6: 0ac8 addi a0,sp,340 + +800151b8 <__mprec_bigtens>: +800151b8: 8000 0x8000 +800151ba: 37e0 fld fs0,232(a5) +800151bc: c379 beqz a4,80015282 <__mprec_bigtens+0xca> +800151be: 4341 li t1,16 +800151c0: b5056e17 auipc t3,0xb5056 +800151c4: b8b5 j 80014a40 <__clzsi2+0x78> +800151c6: f9f54693 xori a3,a0,-97 +800151ca: 4f03e93f 1d324d38 0x1d324d384f03e93f +800151d2: f930 fsw fa2,112(a0) +800151d4: 7748 flw fa0,44(a4) +800151d6: 5a82 lw s5,32(sp) +800151d8: bf3c fsd fa5,120(a4) +800151da: 4fdd7f73 csrrci t5,0x4fd,26 +800151de: 7515 lui a0,0xfffe5 +800151e0: a620 fsd fs0,72(a2) +800151e2: 8000 0x8000 +800151e4: 9c48 0x9c48 +800151e6: 8000 0x8000 +800151e8: 9c48 0x9c48 +800151ea: 8000 0x8000 +800151ec: a614 fsd fa3,8(a2) +800151ee: 8000 0x8000 +800151f0: 9c48 0x9c48 +800151f2: 8000 0x8000 +800151f4: 9c48 0x9c48 +800151f6: 8000 0x8000 +800151f8: 9c48 0x9c48 +800151fa: 8000 0x8000 +800151fc: 9df0 0x9df0 +800151fe: 8000 0x8000 +80015200: 9c48 0x9c48 +80015202: 8000 0x8000 +80015204: 9c48 0x9c48 +80015206: 8000 0x8000 +80015208: a5f0 fsd fa2,200(a1) +8001520a: 8000 0x8000 +8001520c: a688 fsd fa0,8(a3) +8001520e: 8000 0x8000 +80015210: 9c48 0x9c48 +80015212: 8000 0x8000 +80015214: a464 fsd fs1,200(s0) +80015216: 8000 0x8000 +80015218: a644 fsd fs1,136(a2) +8001521a: 8000 0x8000 +8001521c: 9c48 0x9c48 +8001521e: 8000 0x8000 +80015220: a638 fsd fa4,72(a2) +80015222: 8000 0x8000 +80015224: 9c18 0x9c18 +80015226: 8000 0x8000 +80015228: 9c18 0x9c18 +8001522a: 8000 0x8000 +8001522c: 9c18 0x9c18 +8001522e: 8000 0x8000 +80015230: 9c18 0x9c18 +80015232: 8000 0x8000 +80015234: 9c18 0x9c18 +80015236: 8000 0x8000 +80015238: 9c18 0x9c18 +8001523a: 8000 0x8000 +8001523c: 9c18 0x9c18 +8001523e: 8000 0x8000 +80015240: 9c18 0x9c18 +80015242: 8000 0x8000 +80015244: 9c18 0x9c18 +80015246: 8000 0x8000 +80015248: 9c48 0x9c48 +8001524a: 8000 0x8000 +8001524c: 9c48 0x9c48 +8001524e: 8000 0x8000 +80015250: 9c48 0x9c48 +80015252: 8000 0x8000 +80015254: 9c48 0x9c48 +80015256: 8000 0x8000 +80015258: 9c48 0x9c48 +8001525a: 8000 0x8000 +8001525c: 9c48 0x9c48 +8001525e: 8000 0x8000 +80015260: 9c48 0x9c48 +80015262: 8000 0x8000 +80015264: 9e6c 0x9e6c +80015266: 8000 0x8000 +80015268: 9c48 0x9c48 +8001526a: 8000 0x8000 +8001526c: a438 fsd fa4,72(s0) +8001526e: 8000 0x8000 +80015270: a698 fsd fa4,8(a3) +80015272: 8000 0x8000 +80015274: 9e6c 0x9e6c +80015276: 8000 0x8000 +80015278: 9e6c 0x9e6c +8001527a: 8000 0x8000 +8001527c: 9e6c 0x9e6c +8001527e: 8000 0x8000 +80015280: 9c48 0x9c48 +80015282: 8000 0x8000 +80015284: 9c48 0x9c48 +80015286: 8000 0x8000 +80015288: 9c48 0x9c48 +8001528a: 8000 0x8000 +8001528c: 9c48 0x9c48 +8001528e: 8000 0x8000 +80015290: a5e4 fsd fs1,200(a1) +80015292: 8000 0x8000 +80015294: 9c48 0x9c48 +80015296: 8000 0x8000 +80015298: 9c48 0x9c48 +8001529a: 8000 0x8000 +8001529c: a564 fsd fs1,200(a0) +8001529e: 8000 0x8000 +800152a0: 9c48 0x9c48 +800152a2: 8000 0x8000 +800152a4: 9c48 0x9c48 +800152a6: 8000 0x8000 +800152a8: 9c48 0x9c48 +800152aa: 8000 0x8000 +800152ac: a3b4 fsd fa3,64(a5) +800152ae: 8000 0x8000 +800152b0: 9c48 0x9c48 +800152b2: 8000 0x8000 +800152b4: a5b0 fsd fa2,72(a1) +800152b6: 8000 0x8000 +800152b8: 9c48 0x9c48 +800152ba: 8000 0x8000 +800152bc: 9c48 0x9c48 +800152be: 8000 0x8000 +800152c0: b048 fsd fa0,160(s0) +800152c2: 8000 0x8000 +800152c4: 9c48 0x9c48 +800152c6: 8000 0x8000 +800152c8: 9c48 0x9c48 +800152ca: 8000 0x8000 +800152cc: 9c48 0x9c48 +800152ce: 8000 0x8000 +800152d0: 9c48 0x9c48 +800152d2: 8000 0x8000 +800152d4: 9c48 0x9c48 +800152d6: 8000 0x8000 +800152d8: 9c48 0x9c48 +800152da: 8000 0x8000 +800152dc: 9c48 0x9c48 +800152de: 8000 0x8000 +800152e0: 9c48 0x9c48 +800152e2: 8000 0x8000 +800152e4: 9e6c 0x9e6c +800152e6: 8000 0x8000 +800152e8: 9c48 0x9c48 +800152ea: 8000 0x8000 +800152ec: a438 fsd fa4,72(s0) +800152ee: 8000 0x8000 +800152f0: aef0 fsd fa2,216(a3) +800152f2: 8000 0x8000 +800152f4: 9e6c 0x9e6c +800152f6: 8000 0x8000 +800152f8: 9e6c 0x9e6c +800152fa: 8000 0x8000 +800152fc: 9e6c 0x9e6c +800152fe: 8000 0x8000 +80015300: a59c fsd fa5,8(a1) +80015302: 8000 0x8000 +80015304: aef0 fsd fa2,216(a3) +80015306: 8000 0x8000 +80015308: 9e34 0x9e34 +8001530a: 8000 0x8000 +8001530c: 9c48 0x9c48 +8001530e: 8000 0x8000 +80015310: a4c0 fsd fs0,136(s1) +80015312: 8000 0x8000 +80015314: 9c48 0x9c48 +80015316: 8000 0x8000 +80015318: a470 fsd fa2,200(s0) +8001531a: 8000 0x8000 +8001531c: b05c fsd fa5,160(s0) +8001531e: 8000 0x8000 +80015320: a4d4 fsd fa3,136(s1) +80015322: 8000 0x8000 +80015324: 9e34 0x9e34 +80015326: 8000 0x8000 +80015328: 9c48 0x9c48 +8001532a: 8000 0x8000 +8001532c: a3b4 fsd fa3,64(a5) +8001532e: 8000 0x8000 +80015330: 9e2c 0x9e2c +80015332: 8000 0x8000 +80015334: afbc fsd fa5,88(a5) +80015336: 8000 0x8000 +80015338: 9c48 0x9c48 +8001533a: 8000 0x8000 +8001533c: 9c48 0x9c48 +8001533e: 8000 0x8000 +80015340: afc8 fsd fa0,152(a5) +80015342: 8000 0x8000 +80015344: 9c48 0x9c48 +80015346: 8000 0x8000 +80015348: 9e2c 0x9e2c +8001534a: 8000 0x8000 + +8001534c : +8001534c: 2020 fld fs0,64(s0) +8001534e: 2020 fld fs0,64(s0) +80015350: 2020 fld fs0,64(s0) +80015352: 2020 fld fs0,64(s0) +80015354: 2020 fld fs0,64(s0) +80015356: 2020 fld fs0,64(s0) +80015358: 2020 fld fs0,64(s0) +8001535a: 2020 fld fs0,64(s0) + +8001535c : +8001535c: 3030 fld fa2,96(s0) +8001535e: 3030 fld fa2,96(s0) +80015360: 3030 fld fa2,96(s0) +80015362: 3030 fld fa2,96(s0) +80015364: 3030 fld fa2,96(s0) +80015366: 3030 fld fa2,96(s0) +80015368: 3030 fld fa2,96(s0) +8001536a: 3030 fld fa2,96(s0) +8001536c: cd40 sw s0,28(a0) +8001536e: 8000 0x8000 +80015370: c7b0 sw a2,72(a5) +80015372: 8000 0x8000 +80015374: c7b0 sw a2,72(a5) +80015376: 8000 0x8000 +80015378: cd34 sw a3,88(a0) +8001537a: 8000 0x8000 +8001537c: c7b0 sw a2,72(a5) +8001537e: 8000 0x8000 +80015380: c7b0 sw a2,72(a5) +80015382: 8000 0x8000 +80015384: c7b0 sw a2,72(a5) +80015386: 8000 0x8000 +80015388: c978 sw a4,84(a0) +8001538a: 8000 0x8000 +8001538c: c7b0 sw a2,72(a5) +8001538e: 8000 0x8000 +80015390: c7b0 sw a2,72(a5) +80015392: 8000 0x8000 +80015394: cd08 sw a0,24(a0) +80015396: 8000 0x8000 +80015398: cd64 sw s1,92(a0) +8001539a: 8000 0x8000 +8001539c: c7b0 sw a2,72(a5) +8001539e: 8000 0x8000 +800153a0: cd58 sw a4,28(a0) +800153a2: 8000 0x8000 +800153a4: cd74 sw a3,92(a0) +800153a6: 8000 0x8000 +800153a8: c7b0 sw a2,72(a5) +800153aa: 8000 0x8000 +800153ac: ccfc sw a5,92(s1) +800153ae: 8000 0x8000 +800153b0: c778 sw a4,76(a4) +800153b2: 8000 0x8000 +800153b4: c778 sw a4,76(a4) +800153b6: 8000 0x8000 +800153b8: c778 sw a4,76(a4) +800153ba: 8000 0x8000 +800153bc: c778 sw a4,76(a4) +800153be: 8000 0x8000 +800153c0: c778 sw a4,76(a4) +800153c2: 8000 0x8000 +800153c4: c778 sw a4,76(a4) +800153c6: 8000 0x8000 +800153c8: c778 sw a4,76(a4) +800153ca: 8000 0x8000 +800153cc: c778 sw a4,76(a4) +800153ce: 8000 0x8000 +800153d0: c778 sw a4,76(a4) +800153d2: 8000 0x8000 +800153d4: c7b0 sw a2,72(a5) +800153d6: 8000 0x8000 +800153d8: c7b0 sw a2,72(a5) +800153da: 8000 0x8000 +800153dc: c7b0 sw a2,72(a5) +800153de: 8000 0x8000 +800153e0: c7b0 sw a2,72(a5) +800153e2: 8000 0x8000 +800153e4: c7b0 sw a2,72(a5) +800153e6: 8000 0x8000 +800153e8: c7b0 sw a2,72(a5) +800153ea: 8000 0x8000 +800153ec: c7b0 sw a2,72(a5) +800153ee: 8000 0x8000 +800153f0: c7b0 sw a2,72(a5) +800153f2: 8000 0x8000 +800153f4: c7b0 sw a2,72(a5) +800153f6: 8000 0x8000 +800153f8: cc44 sw s1,28(s0) +800153fa: 8000 0x8000 +800153fc: c9c8 sw a0,20(a1) +800153fe: 8000 0x8000 +80015400: c7b0 sw a2,72(a5) +80015402: 8000 0x8000 +80015404: c7b0 sw a2,72(a5) +80015406: 8000 0x8000 +80015408: c7b0 sw a2,72(a5) +8001540a: 8000 0x8000 +8001540c: c7b0 sw a2,72(a5) +8001540e: 8000 0x8000 +80015410: c7b0 sw a2,72(a5) +80015412: 8000 0x8000 +80015414: c7b0 sw a2,72(a5) +80015416: 8000 0x8000 +80015418: c7b0 sw a2,72(a5) +8001541a: 8000 0x8000 +8001541c: c7b0 sw a2,72(a5) +8001541e: 8000 0x8000 +80015420: c7b0 sw a2,72(a5) +80015422: 8000 0x8000 +80015424: c7b0 sw a2,72(a5) +80015426: 8000 0x8000 +80015428: ca90 sw a2,16(a3) +8001542a: 8000 0x8000 +8001542c: c7b0 sw a2,72(a5) +8001542e: 8000 0x8000 +80015430: c7b0 sw a2,72(a5) +80015432: 8000 0x8000 +80015434: c7b0 sw a2,72(a5) +80015436: 8000 0x8000 +80015438: cc04 sw s1,24(s0) +8001543a: 8000 0x8000 +8001543c: c7b0 sw a2,72(a5) +8001543e: 8000 0x8000 +80015440: cccc sw a1,28(s1) +80015442: 8000 0x8000 +80015444: c7b0 sw a2,72(a5) +80015446: 8000 0x8000 +80015448: c7b0 sw a2,72(a5) +8001544a: 8000 0x8000 +8001544c: d4bc sw a5,104(s1) +8001544e: 8000 0x8000 +80015450: c7b0 sw a2,72(a5) +80015452: 8000 0x8000 +80015454: c7b0 sw a2,72(a5) +80015456: 8000 0x8000 +80015458: c7b0 sw a2,72(a5) +8001545a: 8000 0x8000 +8001545c: c7b0 sw a2,72(a5) +8001545e: 8000 0x8000 +80015460: c7b0 sw a2,72(a5) +80015462: 8000 0x8000 +80015464: c7b0 sw a2,72(a5) +80015466: 8000 0x8000 +80015468: c7b0 sw a2,72(a5) +8001546a: 8000 0x8000 +8001546c: c7b0 sw a2,72(a5) +8001546e: 8000 0x8000 +80015470: c7b0 sw a2,72(a5) +80015472: 8000 0x8000 +80015474: c7b0 sw a2,72(a5) +80015476: 8000 0x8000 +80015478: cc44 sw s1,28(s0) +8001547a: 8000 0x8000 +8001547c: c9cc sw a1,20(a1) +8001547e: 8000 0x8000 +80015480: c7b0 sw a2,72(a5) +80015482: 8000 0x8000 +80015484: c7b0 sw a2,72(a5) +80015486: 8000 0x8000 +80015488: c7b0 sw a2,72(a5) +8001548a: 8000 0x8000 +8001548c: ccb8 sw a4,88(s1) +8001548e: 8000 0x8000 +80015490: c9cc sw a1,20(a1) +80015492: 8000 0x8000 +80015494: c9bc sw a5,80(a1) +80015496: 8000 0x8000 +80015498: c7b0 sw a2,72(a5) +8001549a: 8000 0x8000 +8001549c: cca4 sw s1,88(s1) +8001549e: 8000 0x8000 +800154a0: c7b0 sw a2,72(a5) +800154a2: 8000 0x8000 +800154a4: cdb4 sw a3,88(a1) +800154a6: 8000 0x8000 +800154a8: ca94 sw a3,16(a3) +800154aa: 8000 0x8000 +800154ac: cc6c sw a1,92(s0) +800154ae: 8000 0x8000 +800154b0: c9bc sw a5,80(a1) +800154b2: 8000 0x8000 +800154b4: c7b0 sw a2,72(a5) +800154b6: 8000 0x8000 +800154b8: cc04 sw s1,24(s0) +800154ba: 8000 0x8000 +800154bc: c9b4 sw a3,80(a1) +800154be: 8000 0x8000 +800154c0: d4b4 sw a3,104(s1) +800154c2: 8000 0x8000 +800154c4: c7b0 sw a2,72(a5) +800154c6: 8000 0x8000 +800154c8: c7b0 sw a2,72(a5) +800154ca: 8000 0x8000 +800154cc: d518 sw a4,40(a0) +800154ce: 8000 0x8000 +800154d0: c7b0 sw a2,72(a5) +800154d2: 8000 0x8000 +800154d4: c9b4 sw a3,80(a1) +800154d6: 8000 0x8000 + +800154d8 : +800154d8: 2020 fld fs0,64(s0) +800154da: 2020 fld fs0,64(s0) +800154dc: 2020 fld fs0,64(s0) +800154de: 2020 fld fs0,64(s0) +800154e0: 2020 fld fs0,64(s0) +800154e2: 2020 fld fs0,64(s0) +800154e4: 2020 fld fs0,64(s0) +800154e6: 2020 fld fs0,64(s0) + +800154e8 : +800154e8: 3030 fld fa2,96(s0) +800154ea: 3030 fld fa2,96(s0) +800154ec: 3030 fld fa2,96(s0) +800154ee: 3030 fld fa2,96(s0) +800154f0: 3030 fld fa2,96(s0) +800154f2: 3030 fld fa2,96(s0) +800154f4: 3030 fld fa2,96(s0) +800154f6: 3030 fld fa2,96(s0) +800154f8: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne +800154fc: 4f50 lw a2,28(a4) +800154fe: 00584953 fadd.s fs2,fa6,ft5,rmm +80015502: 0000 unimp +80015504: 002e c.slli zero,0xb +80015506: 0000 unimp +80015508: f814 fsw fa3,48(s0) +8001550a: 8000 0x8000 +8001550c: f2c4 fsw fs1,36(a3) +8001550e: 8000 0x8000 +80015510: f2c4 fsw fs1,36(a3) +80015512: 8000 0x8000 +80015514: f808 fsw fa0,48(s0) +80015516: 8000 0x8000 +80015518: f2c4 fsw fs1,36(a3) +8001551a: 8000 0x8000 +8001551c: f2c4 fsw fs1,36(a3) +8001551e: 8000 0x8000 +80015520: f2c4 fsw fs1,36(a3) +80015522: 8000 0x8000 +80015524: f44c fsw fa1,44(s0) +80015526: 8000 0x8000 +80015528: f2c4 fsw fs1,36(a3) +8001552a: 8000 0x8000 +8001552c: f2c4 fsw fs1,36(a3) +8001552e: 8000 0x8000 +80015530: f7dc fsw fa5,44(a5) +80015532: 8000 0x8000 +80015534: f7cc fsw fa1,44(a5) +80015536: 8000 0x8000 +80015538: f2c4 fsw fs1,36(a3) +8001553a: 8000 0x8000 +8001553c: f7c0 fsw fs0,44(a5) +8001553e: 8000 0x8000 +80015540: f780 fsw fs0,40(a5) +80015542: 8000 0x8000 +80015544: f2c4 fsw fs1,36(a3) +80015546: 8000 0x8000 +80015548: f774 fsw fa3,108(a4) +8001554a: 8000 0x8000 +8001554c: f28c fsw fa1,32(a3) +8001554e: 8000 0x8000 +80015550: f28c fsw fa1,32(a3) +80015552: 8000 0x8000 +80015554: f28c fsw fa1,32(a3) +80015556: 8000 0x8000 +80015558: f28c fsw fa1,32(a3) +8001555a: 8000 0x8000 +8001555c: f28c fsw fa1,32(a3) +8001555e: 8000 0x8000 +80015560: f28c fsw fa1,32(a3) +80015562: 8000 0x8000 +80015564: f28c fsw fa1,32(a3) +80015566: 8000 0x8000 +80015568: f28c fsw fa1,32(a3) +8001556a: 8000 0x8000 +8001556c: f28c fsw fa1,32(a3) +8001556e: 8000 0x8000 +80015570: f2c4 fsw fs1,36(a3) +80015572: 8000 0x8000 +80015574: f2c4 fsw fs1,36(a3) +80015576: 8000 0x8000 +80015578: f2c4 fsw fs1,36(a3) +8001557a: 8000 0x8000 +8001557c: f2c4 fsw fs1,36(a3) +8001557e: 8000 0x8000 +80015580: f2c4 fsw fs1,36(a3) +80015582: 8000 0x8000 +80015584: f2c4 fsw fs1,36(a3) +80015586: 8000 0x8000 +80015588: f2c4 fsw fs1,36(a3) +8001558a: 8000 0x8000 +8001558c: f2c4 fsw fs1,36(a3) +8001558e: 8000 0x8000 +80015590: f2c4 fsw fs1,36(a3) +80015592: 8000 0x8000 +80015594: f514 fsw fa3,40(a0) +80015596: 8000 0x8000 +80015598: f630 fsw fa2,104(a2) +8001559a: 8000 0x8000 +8001559c: f2c4 fsw fs1,36(a3) +8001559e: 8000 0x8000 +800155a0: f2c4 fsw fs1,36(a3) +800155a2: 8000 0x8000 +800155a4: f2c4 fsw fs1,36(a3) +800155a6: 8000 0x8000 +800155a8: f2c4 fsw fs1,36(a3) +800155aa: 8000 0x8000 +800155ac: f2c4 fsw fs1,36(a3) +800155ae: 8000 0x8000 +800155b0: f2c4 fsw fs1,36(a3) +800155b2: 8000 0x8000 +800155b4: f2c4 fsw fs1,36(a3) +800155b6: 8000 0x8000 +800155b8: f2c4 fsw fs1,36(a3) +800155ba: 8000 0x8000 +800155bc: f2c4 fsw fs1,36(a3) 800155be: 8000 0x8000 -800155c0: f238 fsw fa4,96(a2) +800155c0: f2c4 fsw fs1,36(a3) 800155c2: 8000 0x8000 -800155c4: f238 fsw fa4,96(a2) +800155c4: f5c0 fsw fs0,44(a1) 800155c6: 8000 0x8000 -800155c8: f77c fsw fa5,108(a4) +800155c8: f2c4 fsw fs1,36(a3) 800155ca: 8000 0x8000 -800155cc: f238 fsw fa4,96(a2) +800155cc: f2c4 fsw fs1,36(a3) 800155ce: 8000 0x8000 -800155d0: f238 fsw fa4,96(a2) +800155d0: f2c4 fsw fs1,36(a3) 800155d2: 8000 0x8000 -800155d4: f238 fsw fa4,96(a2) +800155d4: f4c8 fsw fa0,44(s1) 800155d6: 8000 0x8000 -800155d8: f3c0 fsw fs0,36(a5) +800155d8: f2c4 fsw fs1,36(a3) 800155da: 8000 0x8000 -800155dc: f238 fsw fa4,96(a2) +800155dc: f704 fsw fs1,40(a4) 800155de: 8000 0x8000 -800155e0: f238 fsw fa4,96(a2) +800155e0: f2c4 fsw fs1,36(a3) 800155e2: 8000 0x8000 -800155e4: f750 fsw fa2,44(a4) +800155e4: f2c4 fsw fs1,36(a3) 800155e6: 8000 0x8000 -800155e8: f740 fsw fs0,44(a4) +800155e8: feb4 fsw fa3,120(a3) 800155ea: 8000 0x8000 -800155ec: f238 fsw fa4,96(a2) +800155ec: f2c4 fsw fs1,36(a3) 800155ee: 8000 0x8000 -800155f0: f734 fsw fa3,104(a4) +800155f0: f2c4 fsw fs1,36(a3) 800155f2: 8000 0x8000 -800155f4: f6f4 fsw fa3,108(a3) +800155f4: f2c4 fsw fs1,36(a3) 800155f6: 8000 0x8000 -800155f8: f238 fsw fa4,96(a2) +800155f8: f2c4 fsw fs1,36(a3) 800155fa: 8000 0x8000 -800155fc: f6e8 fsw fa0,108(a3) +800155fc: f2c4 fsw fs1,36(a3) 800155fe: 8000 0x8000 -80015600: f200 fsw fs0,32(a2) +80015600: f2c4 fsw fs1,36(a3) 80015602: 8000 0x8000 -80015604: f200 fsw fs0,32(a2) +80015604: f2c4 fsw fs1,36(a3) 80015606: 8000 0x8000 -80015608: f200 fsw fs0,32(a2) +80015608: f2c4 fsw fs1,36(a3) 8001560a: 8000 0x8000 -8001560c: f200 fsw fs0,32(a2) +8001560c: f2c4 fsw fs1,36(a3) 8001560e: 8000 0x8000 -80015610: f200 fsw fs0,32(a2) +80015610: f2c4 fsw fs1,36(a3) 80015612: 8000 0x8000 -80015614: f200 fsw fs0,32(a2) +80015614: f514 fsw fa3,40(a0) 80015616: 8000 0x8000 -80015618: f200 fsw fs0,32(a2) +80015618: f53c fsw fa5,104(a0) 8001561a: 8000 0x8000 -8001561c: f200 fsw fs0,32(a2) +8001561c: f2c4 fsw fs1,36(a3) 8001561e: 8000 0x8000 -80015620: f200 fsw fs0,32(a2) +80015620: f2c4 fsw fs1,36(a3) 80015622: 8000 0x8000 -80015624: f238 fsw fa4,96(a2) +80015624: f2c4 fsw fs1,36(a3) 80015626: 8000 0x8000 -80015628: f238 fsw fa4,96(a2) +80015628: f82c fsw fa1,112(s0) 8001562a: 8000 0x8000 -8001562c: f238 fsw fa4,96(a2) +8001562c: f53c fsw fa5,104(a0) 8001562e: 8000 0x8000 -80015630: f238 fsw fa4,96(a2) +80015630: f490 fsw fa2,40(s1) 80015632: 8000 0x8000 -80015634: f238 fsw fa4,96(a2) +80015634: f2c4 fsw fs1,36(a3) 80015636: 8000 0x8000 -80015638: f238 fsw fa4,96(a2) +80015638: f87c fsw fa5,116(s0) 8001563a: 8000 0x8000 -8001563c: f238 fsw fa4,96(a2) +8001563c: f2c4 fsw fs1,36(a3) 8001563e: 8000 0x8000 -80015640: f238 fsw fa4,96(a2) +80015640: f840 fsw fs0,52(s0) 80015642: 8000 0x8000 -80015644: f238 fsw fa4,96(a2) +80015644: ff20 fsw fs0,120(a4) 80015646: 8000 0x8000 -80015648: f488 fsw fa0,40(s1) +80015648: f738 fsw fa4,104(a4) 8001564a: 8000 0x8000 -8001564c: f5a4 fsw fs1,104(a1) +8001564c: f490 fsw fa2,40(s1) 8001564e: 8000 0x8000 -80015650: f238 fsw fa4,96(a2) +80015650: f2c4 fsw fs1,36(a3) 80015652: 8000 0x8000 -80015654: f238 fsw fa4,96(a2) +80015654: f4c8 fsw fa0,44(s1) 80015656: 8000 0x8000 -80015658: f238 fsw fa4,96(a2) +80015658: f488 fsw fa0,40(s1) 8001565a: 8000 0x8000 -8001565c: f238 fsw fa4,96(a2) +8001565c: ff14 fsw fa3,56(a4) 8001565e: 8000 0x8000 -80015660: f238 fsw fa4,96(a2) +80015660: f2c4 fsw fs1,36(a3) 80015662: 8000 0x8000 -80015664: f238 fsw fa4,96(a2) +80015664: f2c4 fsw fs1,36(a3) 80015666: 8000 0x8000 -80015668: f238 fsw fa4,96(a2) +80015668: ff28 fsw fa0,120(a4) 8001566a: 8000 0x8000 -8001566c: f238 fsw fa4,96(a2) +8001566c: f2c4 fsw fs1,36(a3) 8001566e: 8000 0x8000 -80015670: f238 fsw fa4,96(a2) +80015670: f488 fsw fa0,40(s1) 80015672: 8000 0x8000 -80015674: f238 fsw fa4,96(a2) -80015676: 8000 0x8000 -80015678: f534 fsw fa3,104(a0) -8001567a: 8000 0x8000 -8001567c: f238 fsw fa4,96(a2) -8001567e: 8000 0x8000 -80015680: f238 fsw fa4,96(a2) -80015682: 8000 0x8000 -80015684: f238 fsw fa4,96(a2) -80015686: 8000 0x8000 -80015688: f43c fsw fa5,104(s0) -8001568a: 8000 0x8000 -8001568c: f238 fsw fa4,96(a2) -8001568e: 8000 0x8000 -80015690: f678 fsw fa4,108(a2) -80015692: 8000 0x8000 -80015694: f238 fsw fa4,96(a2) -80015696: 8000 0x8000 -80015698: f238 fsw fa4,96(a2) -8001569a: 8000 0x8000 -8001569c: fe28 fsw fa0,120(a2) -8001569e: 8000 0x8000 -800156a0: f238 fsw fa4,96(a2) -800156a2: 8000 0x8000 -800156a4: f238 fsw fa4,96(a2) -800156a6: 8000 0x8000 -800156a8: f238 fsw fa4,96(a2) -800156aa: 8000 0x8000 -800156ac: f238 fsw fa4,96(a2) -800156ae: 8000 0x8000 -800156b0: f238 fsw fa4,96(a2) -800156b2: 8000 0x8000 -800156b4: f238 fsw fa4,96(a2) -800156b6: 8000 0x8000 -800156b8: f238 fsw fa4,96(a2) -800156ba: 8000 0x8000 -800156bc: f238 fsw fa4,96(a2) -800156be: 8000 0x8000 -800156c0: f238 fsw fa4,96(a2) -800156c2: 8000 0x8000 -800156c4: f238 fsw fa4,96(a2) -800156c6: 8000 0x8000 -800156c8: f488 fsw fa0,40(s1) -800156ca: 8000 0x8000 -800156cc: f4b0 fsw fa2,104(s1) -800156ce: 8000 0x8000 -800156d0: f238 fsw fa4,96(a2) -800156d2: 8000 0x8000 -800156d4: f238 fsw fa4,96(a2) -800156d6: 8000 0x8000 -800156d8: f238 fsw fa4,96(a2) -800156da: 8000 0x8000 -800156dc: f7a0 fsw fs0,104(a5) -800156de: 8000 0x8000 -800156e0: f4b0 fsw fa2,104(s1) -800156e2: 8000 0x8000 -800156e4: f404 fsw fs1,40(s0) -800156e6: 8000 0x8000 -800156e8: f238 fsw fa4,96(a2) -800156ea: 8000 0x8000 -800156ec: f7f0 fsw fa2,108(a5) -800156ee: 8000 0x8000 -800156f0: f238 fsw fa4,96(a2) -800156f2: 8000 0x8000 -800156f4: f7b4 fsw fa3,104(a5) -800156f6: 8000 0x8000 -800156f8: fe94 fsw fa3,56(a3) -800156fa: 8000 0x8000 -800156fc: f6ac fsw fa1,104(a3) -800156fe: 8000 0x8000 -80015700: f404 fsw fs1,40(s0) -80015702: 8000 0x8000 -80015704: f238 fsw fa4,96(a2) -80015706: 8000 0x8000 -80015708: f43c fsw fa5,104(s0) -8001570a: 8000 0x8000 -8001570c: f3fc fsw fa5,100(a5) -8001570e: 8000 0x8000 -80015710: fe88 fsw fa0,56(a3) -80015712: 8000 0x8000 -80015714: f238 fsw fa4,96(a2) -80015716: 8000 0x8000 -80015718: f238 fsw fa4,96(a2) -8001571a: 8000 0x8000 -8001571c: fe9c fsw fa5,56(a3) -8001571e: 8000 0x8000 -80015720: f238 fsw fa4,96(a2) -80015722: 8000 0x8000 -80015724: f3fc fsw fa5,100(a5) -80015726: 8000 0x8000 -80015728 : -80015728: 2020 fld fs0,64(s0) -8001572a: 2020 fld fs0,64(s0) -8001572c: 2020 fld fs0,64(s0) -8001572e: 2020 fld fs0,64(s0) -80015730: 2020 fld fs0,64(s0) -80015732: 2020 fld fs0,64(s0) -80015734: 2020 fld fs0,64(s0) -80015736: 2020 fld fs0,64(s0) +80015674 : +80015674: 2020 fld fs0,64(s0) +80015676: 2020 fld fs0,64(s0) +80015678: 2020 fld fs0,64(s0) +8001567a: 2020 fld fs0,64(s0) +8001567c: 2020 fld fs0,64(s0) +8001567e: 2020 fld fs0,64(s0) +80015680: 2020 fld fs0,64(s0) +80015682: 2020 fld fs0,64(s0) -80015738 : -80015738: 3030 fld fa2,96(s0) -8001573a: 3030 fld fa2,96(s0) -8001573c: 3030 fld fa2,96(s0) -8001573e: 3030 fld fa2,96(s0) -80015740: 3030 fld fa2,96(s0) -80015742: 3030 fld fa2,96(s0) -80015744: 3030 fld fa2,96(s0) -80015746: 3030 fld fa2,96(s0) -80015748: 120c addi a1,sp,288 -8001574a: 8001 c.srli64 s0 -8001574c: 12fc addi a5,sp,364 -8001574e: 8001 c.srli64 s0 -80015750: 121c addi a5,sp,288 -80015752: 8001 c.srli64 s0 -80015754: 12fc addi a5,sp,364 -80015756: 8001 c.srli64 s0 -80015758: 12e8 addi a0,sp,364 -8001575a: 8001 c.srli64 s0 -8001575c: 12fc addi a5,sp,364 -8001575e: 8001 c.srli64 s0 -80015760: 121c addi a5,sp,288 -80015762: 8001 c.srli64 s0 -80015764: 120c addi a1,sp,288 -80015766: 8001 c.srli64 s0 -80015768: 120c addi a1,sp,288 -8001576a: 8001 c.srli64 s0 -8001576c: 12e8 addi a0,sp,364 -8001576e: 8001 c.srli64 s0 -80015770: 121c addi a5,sp,288 -80015772: 8001 c.srli64 s0 -80015774: 11e4 addi s1,sp,236 -80015776: 8001 c.srli64 s0 -80015778: 11e4 addi s1,sp,236 -8001577a: 8001 c.srli64 s0 -8001577c: 11e4 addi s1,sp,236 -8001577e: 8001 c.srli64 s0 -80015780: 1224 addi s1,sp,296 -80015782: 8001 c.srli64 s0 -80015784: 17d0 addi a2,sp,996 -80015786: 8001 c.srli64 s0 -80015788: 17d0 addi a2,sp,996 -8001578a: 8001 c.srli64 s0 -8001578c: 17f4 addi a3,sp,1004 -8001578e: 8001 c.srli64 s0 -80015790: 17c4 addi s1,sp,996 -80015792: 8001 c.srli64 s0 -80015794: 17c4 addi s1,sp,996 -80015796: 8001 c.srli64 s0 -80015798: 18b4 addi a3,sp,120 +80015684 : +80015684: 3030 fld fa2,96(s0) +80015686: 3030 fld fa2,96(s0) +80015688: 3030 fld fa2,96(s0) +8001568a: 3030 fld fa2,96(s0) +8001568c: 3030 fld fa2,96(s0) +8001568e: 3030 fld fa2,96(s0) +80015690: 3030 fld fa2,96(s0) +80015692: 3030 fld fa2,96(s0) + +80015694 <_ctype_>: +80015694: 2000 fld fs0,0(s0) +80015696: 2020 fld fs0,64(s0) +80015698: 2020 fld fs0,64(s0) +8001569a: 2020 fld fs0,64(s0) +8001569c: 2020 fld fs0,64(s0) +8001569e: 2828 fld fa0,80(s0) +800156a0: 2828 fld fa0,80(s0) +800156a2: 2028 fld fa0,64(s0) +800156a4: 2020 fld fs0,64(s0) +800156a6: 2020 fld fs0,64(s0) +800156a8: 2020 fld fs0,64(s0) +800156aa: 2020 fld fs0,64(s0) +800156ac: 2020 fld fs0,64(s0) +800156ae: 2020 fld fs0,64(s0) +800156b0: 2020 fld fs0,64(s0) +800156b2: 2020 fld fs0,64(s0) +800156b4: 8820 0x8820 +800156b6: 1010 addi a2,sp,32 +800156b8: 1010 addi a2,sp,32 +800156ba: 1010 addi a2,sp,32 +800156bc: 1010 addi a2,sp,32 +800156be: 1010 addi a2,sp,32 +800156c0: 1010 addi a2,sp,32 +800156c2: 1010 addi a2,sp,32 +800156c4: 0410 addi a2,sp,512 +800156c6: 0404 addi s1,sp,512 +800156c8: 0404 addi s1,sp,512 +800156ca: 0404 addi s1,sp,512 +800156cc: 0404 addi s1,sp,512 +800156ce: 1004 addi s1,sp,32 +800156d0: 1010 addi a2,sp,32 +800156d2: 1010 addi a2,sp,32 +800156d4: 1010 addi a2,sp,32 +800156d6: 4141 li sp,16 +800156d8: 4141 li sp,16 +800156da: 4141 li sp,16 +800156dc: 0101 addi sp,sp,0 +800156de: 0101 addi sp,sp,0 +800156e0: 0101 addi sp,sp,0 +800156e2: 0101 addi sp,sp,0 +800156e4: 0101 addi sp,sp,0 +800156e6: 0101 addi sp,sp,0 +800156e8: 0101 addi sp,sp,0 +800156ea: 0101 addi sp,sp,0 +800156ec: 0101 addi sp,sp,0 +800156ee: 0101 addi sp,sp,0 +800156f0: 1010 addi a2,sp,32 +800156f2: 1010 addi a2,sp,32 +800156f4: 1010 addi a2,sp,32 +800156f6: 4242 lw tp,16(sp) +800156f8: 4242 lw tp,16(sp) +800156fa: 4242 lw tp,16(sp) +800156fc: 0202 c.slli64 tp +800156fe: 0202 c.slli64 tp +80015700: 0202 c.slli64 tp +80015702: 0202 c.slli64 tp +80015704: 0202 c.slli64 tp +80015706: 0202 c.slli64 tp +80015708: 0202 c.slli64 tp +8001570a: 0202 c.slli64 tp +8001570c: 0202 c.slli64 tp +8001570e: 0202 c.slli64 tp +80015710: 1010 addi a2,sp,32 +80015712: 1010 addi a2,sp,32 +80015714: 0020 addi s0,sp,8 + ... +80015796: 0000 unimp +80015798: 12d0 addi a2,sp,356 8001579a: 8001 c.srli64 s0 -8001579c: 17f4 addi a3,sp,1004 +8001579c: 13c0 addi s0,sp,484 8001579e: 8001 c.srli64 s0 -800157a0: 17c4 addi s1,sp,996 +800157a0: 12e0 addi s0,sp,364 800157a2: 8001 c.srli64 s0 -800157a4: 18b4 addi a3,sp,120 +800157a4: 13c0 addi s0,sp,484 800157a6: 8001 c.srli64 s0 -800157a8: 17c4 addi s1,sp,996 +800157a8: 13ac addi a1,sp,488 800157aa: 8001 c.srli64 s0 -800157ac: 17f4 addi a3,sp,1004 +800157ac: 13c0 addi s0,sp,484 800157ae: 8001 c.srli64 s0 -800157b0: 17c0 addi s0,sp,996 +800157b0: 12e0 addi s0,sp,364 800157b2: 8001 c.srli64 s0 -800157b4: 17c0 addi s0,sp,996 +800157b4: 12d0 addi a2,sp,356 800157b6: 8001 c.srli64 s0 -800157b8: 17c0 addi s0,sp,996 +800157b8: 12d0 addi a2,sp,356 800157ba: 8001 c.srli64 s0 -800157bc: 18b4 addi a3,sp,120 +800157bc: 13ac addi a1,sp,488 800157be: 8001 c.srli64 s0 -800157c0: 29a0 fld fs0,80(a1) +800157c0: 12e0 addi s0,sp,364 800157c2: 8001 c.srli64 s0 -800157c4: 29a0 fld fs0,80(a1) +800157c4: 12a8 addi a0,sp,360 800157c6: 8001 c.srli64 s0 -800157c8: 299c fld fa5,16(a1) +800157c8: 12a8 addi a0,sp,360 800157ca: 8001 c.srli64 s0 -800157cc: 2950 fld fa2,144(a0) +800157cc: 12a8 addi a0,sp,360 800157ce: 8001 c.srli64 s0 -800157d0: 2950 fld fa2,144(a0) +800157d0: 12e8 addi a0,sp,364 800157d2: 8001 c.srli64 s0 -800157d4: 2c20 fld fs0,88(s0) +800157d4: 1894 addi a3,sp,112 800157d6: 8001 c.srli64 s0 -800157d8: 299c fld fa5,16(a1) +800157d8: 1894 addi a3,sp,112 800157da: 8001 c.srli64 s0 -800157dc: 2950 fld fa2,144(a0) +800157dc: 18b8 addi a4,sp,120 800157de: 8001 c.srli64 s0 -800157e0: 2c20 fld fs0,88(s0) +800157e0: 1888 addi a0,sp,112 800157e2: 8001 c.srli64 s0 -800157e4: 2950 fld fa2,144(a0) +800157e4: 1888 addi a0,sp,112 800157e6: 8001 c.srli64 s0 -800157e8: 299c fld fa5,16(a1) +800157e8: 1978 addi a4,sp,188 800157ea: 8001 c.srli64 s0 -800157ec: 294c fld fa1,144(a0) +800157ec: 18b8 addi a4,sp,120 800157ee: 8001 c.srli64 s0 -800157f0: 294c fld fa1,144(a0) +800157f0: 1888 addi a0,sp,112 800157f2: 8001 c.srli64 s0 -800157f4: 294c fld fa1,144(a0) +800157f4: 1978 addi a4,sp,188 800157f6: 8001 c.srli64 s0 -800157f8: 2c20 fld fs0,88(s0) +800157f8: 1888 addi a0,sp,112 800157fa: 8001 c.srli64 s0 +800157fc: 18b8 addi a4,sp,120 +800157fe: 8001 c.srli64 s0 +80015800: 1884 addi s1,sp,112 +80015802: 8001 c.srli64 s0 +80015804: 1884 addi s1,sp,112 +80015806: 8001 c.srli64 s0 +80015808: 1884 addi s1,sp,112 +8001580a: 8001 c.srli64 s0 +8001580c: 1978 addi a4,sp,188 +8001580e: 8001 c.srli64 s0 +80015810: 2a64 fld fs1,208(a2) +80015812: 8001 c.srli64 s0 +80015814: 2a64 fld fs1,208(a2) +80015816: 8001 c.srli64 s0 +80015818: 2a60 fld fs0,208(a2) +8001581a: 8001 c.srli64 s0 +8001581c: 2a14 fld fa3,16(a2) +8001581e: 8001 c.srli64 s0 +80015820: 2a14 fld fa3,16(a2) +80015822: 8001 c.srli64 s0 +80015824: 2ce4 fld fs1,216(s1) +80015826: 8001 c.srli64 s0 +80015828: 2a60 fld fs0,208(a2) +8001582a: 8001 c.srli64 s0 +8001582c: 2a14 fld fa3,16(a2) +8001582e: 8001 c.srli64 s0 +80015830: 2ce4 fld fs1,216(s1) +80015832: 8001 c.srli64 s0 +80015834: 2a14 fld fa3,16(a2) +80015836: 8001 c.srli64 s0 +80015838: 2a60 fld fs0,208(a2) +8001583a: 8001 c.srli64 s0 +8001583c: 2a10 fld fa2,16(a2) +8001583e: 8001 c.srli64 s0 +80015840: 2a10 fld fa2,16(a2) +80015842: 8001 c.srli64 s0 +80015844: 2a10 fld fa2,16(a2) +80015846: 8001 c.srli64 s0 +80015848: 2ce4 fld fs1,216(s1) +8001584a: 8001 c.srli64 s0 -800157fc <__clz_tab>: -800157fc: 0100 addi s0,sp,128 -800157fe: 0202 c.slli64 tp -80015800: 03030303 lb t1,48(t1) # ffff9030 <__BSS_END__+0x7ffe2400> -80015804: 0404 addi s1,sp,512 -80015806: 0404 addi s1,sp,512 -80015808: 0404 addi s1,sp,512 -8001580a: 0404 addi s1,sp,512 -8001580c: 0505 addi a0,a0,1 -8001580e: 0505 addi a0,a0,1 -80015810: 0505 addi a0,a0,1 -80015812: 0505 addi a0,a0,1 -80015814: 0505 addi a0,a0,1 -80015816: 0505 addi a0,a0,1 -80015818: 0505 addi a0,a0,1 -8001581a: 0505 addi a0,a0,1 -8001581c: 0606 slli a2,a2,0x1 -8001581e: 0606 slli a2,a2,0x1 -80015820: 0606 slli a2,a2,0x1 -80015822: 0606 slli a2,a2,0x1 -80015824: 0606 slli a2,a2,0x1 -80015826: 0606 slli a2,a2,0x1 -80015828: 0606 slli a2,a2,0x1 -8001582a: 0606 slli a2,a2,0x1 -8001582c: 0606 slli a2,a2,0x1 -8001582e: 0606 slli a2,a2,0x1 -80015830: 0606 slli a2,a2,0x1 -80015832: 0606 slli a2,a2,0x1 -80015834: 0606 slli a2,a2,0x1 -80015836: 0606 slli a2,a2,0x1 -80015838: 0606 slli a2,a2,0x1 -8001583a: 0606 slli a2,a2,0x1 -8001583c: 07070707 0x7070707 -80015840: 07070707 0x7070707 -80015844: 07070707 0x7070707 -80015848: 07070707 0x7070707 -8001584c: 07070707 0x7070707 -80015850: 07070707 0x7070707 -80015854: 07070707 0x7070707 -80015858: 07070707 0x7070707 -8001585c: 07070707 0x7070707 -80015860: 07070707 0x7070707 -80015864: 07070707 0x7070707 -80015868: 07070707 0x7070707 -8001586c: 07070707 0x7070707 -80015870: 07070707 0x7070707 -80015874: 07070707 0x7070707 -80015878: 07070707 0x7070707 -8001587c: 0808 addi a0,sp,16 -8001587e: 0808 addi a0,sp,16 -80015880: 0808 addi a0,sp,16 -80015882: 0808 addi a0,sp,16 -80015884: 0808 addi a0,sp,16 -80015886: 0808 addi a0,sp,16 -80015888: 0808 addi a0,sp,16 -8001588a: 0808 addi a0,sp,16 -8001588c: 0808 addi a0,sp,16 -8001588e: 0808 addi a0,sp,16 -80015890: 0808 addi a0,sp,16 -80015892: 0808 addi a0,sp,16 -80015894: 0808 addi a0,sp,16 -80015896: 0808 addi a0,sp,16 -80015898: 0808 addi a0,sp,16 -8001589a: 0808 addi a0,sp,16 -8001589c: 0808 addi a0,sp,16 -8001589e: 0808 addi a0,sp,16 -800158a0: 0808 addi a0,sp,16 -800158a2: 0808 addi a0,sp,16 -800158a4: 0808 addi a0,sp,16 -800158a6: 0808 addi a0,sp,16 -800158a8: 0808 addi a0,sp,16 -800158aa: 0808 addi a0,sp,16 -800158ac: 0808 addi a0,sp,16 -800158ae: 0808 addi a0,sp,16 -800158b0: 0808 addi a0,sp,16 -800158b2: 0808 addi a0,sp,16 -800158b4: 0808 addi a0,sp,16 -800158b6: 0808 addi a0,sp,16 -800158b8: 0808 addi a0,sp,16 -800158ba: 0808 addi a0,sp,16 -800158bc: 0808 addi a0,sp,16 -800158be: 0808 addi a0,sp,16 -800158c0: 0808 addi a0,sp,16 -800158c2: 0808 addi a0,sp,16 -800158c4: 0808 addi a0,sp,16 -800158c6: 0808 addi a0,sp,16 -800158c8: 0808 addi a0,sp,16 -800158ca: 0808 addi a0,sp,16 +8001584c <__clz_tab>: +8001584c: 0100 addi s0,sp,128 +8001584e: 0202 c.slli64 tp +80015850: 03030303 lb t1,48(t1) +80015854: 0404 addi s1,sp,512 +80015856: 0404 addi s1,sp,512 +80015858: 0404 addi s1,sp,512 +8001585a: 0404 addi s1,sp,512 +8001585c: 0505 addi a0,a0,1 +8001585e: 0505 addi a0,a0,1 +80015860: 0505 addi a0,a0,1 +80015862: 0505 addi a0,a0,1 +80015864: 0505 addi a0,a0,1 +80015866: 0505 addi a0,a0,1 +80015868: 0505 addi a0,a0,1 +8001586a: 0505 addi a0,a0,1 +8001586c: 0606 slli a2,a2,0x1 +8001586e: 0606 slli a2,a2,0x1 +80015870: 0606 slli a2,a2,0x1 +80015872: 0606 slli a2,a2,0x1 +80015874: 0606 slli a2,a2,0x1 +80015876: 0606 slli a2,a2,0x1 +80015878: 0606 slli a2,a2,0x1 +8001587a: 0606 slli a2,a2,0x1 +8001587c: 0606 slli a2,a2,0x1 +8001587e: 0606 slli a2,a2,0x1 +80015880: 0606 slli a2,a2,0x1 +80015882: 0606 slli a2,a2,0x1 +80015884: 0606 slli a2,a2,0x1 +80015886: 0606 slli a2,a2,0x1 +80015888: 0606 slli a2,a2,0x1 +8001588a: 0606 slli a2,a2,0x1 +8001588c: 07070707 0x7070707 +80015890: 07070707 0x7070707 +80015894: 07070707 0x7070707 +80015898: 07070707 0x7070707 +8001589c: 07070707 0x7070707 +800158a0: 07070707 0x7070707 +800158a4: 07070707 0x7070707 +800158a8: 07070707 0x7070707 +800158ac: 07070707 0x7070707 +800158b0: 07070707 0x7070707 +800158b4: 07070707 0x7070707 +800158b8: 07070707 0x7070707 +800158bc: 07070707 0x7070707 +800158c0: 07070707 0x7070707 +800158c4: 07070707 0x7070707 +800158c8: 07070707 0x7070707 800158cc: 0808 addi a0,sp,16 800158ce: 0808 addi a0,sp,16 800158d0: 0808 addi a0,sp,16 @@ -23271,44 +23230,84 @@ Disassembly of section .rodata: 800158f6: 0808 addi a0,sp,16 800158f8: 0808 addi a0,sp,16 800158fa: 0808 addi a0,sp,16 +800158fc: 0808 addi a0,sp,16 +800158fe: 0808 addi a0,sp,16 +80015900: 0808 addi a0,sp,16 +80015902: 0808 addi a0,sp,16 +80015904: 0808 addi a0,sp,16 +80015906: 0808 addi a0,sp,16 +80015908: 0808 addi a0,sp,16 +8001590a: 0808 addi a0,sp,16 +8001590c: 0808 addi a0,sp,16 +8001590e: 0808 addi a0,sp,16 +80015910: 0808 addi a0,sp,16 +80015912: 0808 addi a0,sp,16 +80015914: 0808 addi a0,sp,16 +80015916: 0808 addi a0,sp,16 +80015918: 0808 addi a0,sp,16 +8001591a: 0808 addi a0,sp,16 +8001591c: 0808 addi a0,sp,16 +8001591e: 0808 addi a0,sp,16 +80015920: 0808 addi a0,sp,16 +80015922: 0808 addi a0,sp,16 +80015924: 0808 addi a0,sp,16 +80015926: 0808 addi a0,sp,16 +80015928: 0808 addi a0,sp,16 +8001592a: 0808 addi a0,sp,16 +8001592c: 0808 addi a0,sp,16 +8001592e: 0808 addi a0,sp,16 +80015930: 0808 addi a0,sp,16 +80015932: 0808 addi a0,sp,16 +80015934: 0808 addi a0,sp,16 +80015936: 0808 addi a0,sp,16 +80015938: 0808 addi a0,sp,16 +8001593a: 0808 addi a0,sp,16 +8001593c: 0808 addi a0,sp,16 +8001593e: 0808 addi a0,sp,16 +80015940: 0808 addi a0,sp,16 +80015942: 0808 addi a0,sp,16 +80015944: 0808 addi a0,sp,16 +80015946: 0808 addi a0,sp,16 +80015948: 0808 addi a0,sp,16 +8001594a: 0808 addi a0,sp,16 Disassembly of section .eh_frame: -800158fc <.eh_frame>: -800158fc: 0010 0x10 -800158fe: 0000 unimp -80015900: 0000 unimp -80015902: 0000 unimp -80015904: 7a01 lui s4,0xfffe0 -80015906: 0052 c.slli zero,0x14 -80015908: 7c01 lui s8,0xfffe0 -8001590a: 0101 addi sp,sp,0 -8001590c: 00020d1b 0x20d1b -80015910: 0010 0x10 -80015912: 0000 unimp -80015914: 0018 0x18 -80015916: 0000 unimp -80015918: aae8 fsd fa0,208(a3) -8001591a: ffff 0xffff -8001591c: 0434 addi a3,sp,520 -8001591e: 0000 unimp -80015920: 0000 unimp -80015922: 0000 unimp -80015924: 0010 0x10 -80015926: 0000 unimp -80015928: 002c addi a1,sp,8 -8001592a: 0000 unimp -8001592c: af08 fsd fa0,24(a4) -8001592e: ffff 0xffff -80015930: 0410 addi a2,sp,512 -80015932: 0000 unimp -80015934: 0000 unimp +8001594c <.eh_frame>: +8001594c: 0010 0x10 +8001594e: 0000 unimp +80015950: 0000 unimp +80015952: 0000 unimp +80015954: 7a01 lui s4,0xfffe0 +80015956: 0052 c.slli zero,0x14 +80015958: 7c01 lui s8,0xfffe0 +8001595a: 0101 addi sp,sp,0 +8001595c: 00020d1b 0x20d1b +80015960: 0010 0x10 +80015962: 0000 unimp +80015964: 0018 0x18 +80015966: 0000 unimp +80015968: ab5c fsd fa5,144(a4) +8001596a: ffff 0xffff +8001596c: 0434 addi a3,sp,520 +8001596e: 0000 unimp +80015970: 0000 unimp +80015972: 0000 unimp +80015974: 0010 0x10 +80015976: 0000 unimp +80015978: 002c addi a1,sp,8 +8001597a: 0000 unimp +8001597c: af7c fsd fa5,216(a4) +8001597e: ffff 0xffff +80015980: 0410 addi a2,sp,512 +80015982: 0000 unimp +80015984: 0000 unimp ... Disassembly of section .init_array: -80016000 <__init_array_start>: -80016000: 0050 addi a2,sp,4 +80016000 <__fini_array_end-0x4>: +80016000: 001c 0x1c 80016002: 8000 0x8000 Disassembly of section .data: @@ -23318,105 +23317,105 @@ Disassembly of section .data: ... 8001600c : -8001600c: 4950 lw a2,20(a0) +8001600c: 4a18 lw a4,16(a2) 8001600e: 8001 c.srli64 s0 -80016010: 4954 lw a3,20(a0) +80016010: 4a1c lw a5,16(a2) 80016012: 8001 c.srli64 s0 -80016014: 4958 lw a4,20(a0) +80016014: 4a20 lw s0,80(a2) 80016016: 8001 c.srli64 s0 -80016018: 495c lw a5,20(a0) +80016018: 4a24 lw s1,80(a2) 8001601a: 8001 c.srli64 s0 -8001601c: 4960 lw s0,84(a0) +8001601c: 4a28 lw a0,80(a2) 8001601e: 8001 c.srli64 s0 -80016020: 4964 lw s1,84(a0) +80016020: 4a2c lw a1,80(a2) 80016022: 8001 c.srli64 s0 -80016024: 4968 lw a0,84(a0) +80016024: 4a30 lw a2,80(a2) 80016026: 8001 c.srli64 s0 -80016028: 496c lw a1,84(a0) +80016028: 4a34 lw a3,80(a2) 8001602a: 8001 c.srli64 s0 -8001602c: 4970 lw a2,84(a0) +8001602c: 4a38 lw a4,80(a2) 8001602e: 8001 c.srli64 s0 -80016030: 4974 lw a3,84(a0) +80016030: 4a3c lw a5,80(a2) 80016032: 8001 c.srli64 s0 -80016034: 4978 lw a4,84(a0) +80016034: 4a40 lw s0,20(a2) 80016036: 8001 c.srli64 s0 -80016038: 497c lw a5,84(a0) +80016038: 4a44 lw s1,20(a2) 8001603a: 8001 c.srli64 s0 -8001603c: 4980 lw s0,16(a1) +8001603c: 4a48 lw a0,20(a2) 8001603e: 8001 c.srli64 s0 -80016040: 4984 lw s1,16(a1) +80016040: 4a4c lw a1,20(a2) 80016042: 8001 c.srli64 s0 -80016044: 4988 lw a0,16(a1) +80016044: 4a50 lw a2,20(a2) 80016046: 8001 c.srli64 s0 -80016048: 498c lw a1,16(a1) +80016048: 4a54 lw a3,20(a2) 8001604a: 8001 c.srli64 s0 8001604c : -8001604c: 4a3c lw a5,80(a2) +8001604c: 4aa0 lw s0,80(a3) 8001604e: 8001 c.srli64 s0 -80016050: 4a40 lw s0,20(a2) +80016050: 4aa4 lw s1,80(a3) 80016052: 8001 c.srli64 s0 -80016054: 4a44 lw s1,20(a2) +80016054: 4aa8 lw a0,80(a3) 80016056: 8001 c.srli64 s0 -80016058: 4a48 lw a0,20(a2) +80016058: 4aac lw a1,80(a3) 8001605a: 8001 c.srli64 s0 -8001605c: 4a4c lw a1,20(a2) +8001605c: 4ab0 lw a2,80(a3) 8001605e: 8001 c.srli64 s0 -80016060: 4a50 lw a2,20(a2) +80016060: 4ab4 lw a3,80(a3) 80016062: 8001 c.srli64 s0 -80016064: 4a54 lw a3,20(a2) +80016064: 4ab8 lw a4,80(a3) 80016066: 8001 c.srli64 s0 -80016068: 4a58 lw a4,20(a2) +80016068: 4abc lw a5,80(a3) 8001606a: 8001 c.srli64 s0 -8001606c: 4a5c lw a5,20(a2) +8001606c: 4ac0 lw s0,20(a3) 8001606e: 8001 c.srli64 s0 -80016070: 4a60 lw s0,84(a2) +80016070: 4ac4 lw s1,20(a3) 80016072: 8001 c.srli64 s0 -80016074: 4a64 lw s1,84(a2) +80016074: 4ac8 lw a0,20(a3) 80016076: 8001 c.srli64 s0 -80016078: 4a68 lw a0,84(a2) +80016078: 4acc lw a1,20(a3) 8001607a: 8001 c.srli64 s0 -8001607c: 4a6c lw a1,84(a2) +8001607c: 4ad0 lw a2,20(a3) 8001607e: 8001 c.srli64 s0 -80016080: 4a70 lw a2,84(a2) +80016080: 4ad4 lw a3,20(a3) 80016082: 8001 c.srli64 s0 -80016084: 4a74 lw a3,84(a2) +80016084: 4ad8 lw a4,20(a3) 80016086: 8001 c.srli64 s0 -80016088: 4a78 lw a4,84(a2) +80016088: 4adc lw a5,20(a3) 8001608a: 8001 c.srli64 s0 8001608c : -8001608c: 4ab4 lw a3,80(a3) +8001608c: 4ae8 lw a0,84(a3) 8001608e: 8001 c.srli64 s0 -80016090: 4ab8 lw a4,80(a3) +80016090: 4aec lw a1,84(a3) 80016092: 8001 c.srli64 s0 -80016094: 4abc lw a5,80(a3) +80016094: 4af0 lw a2,84(a3) 80016096: 8001 c.srli64 s0 -80016098: 4ac0 lw s0,20(a3) +80016098: 4af4 lw a3,84(a3) 8001609a: 8001 c.srli64 s0 -8001609c: 4ac4 lw s1,20(a3) +8001609c: 4af8 lw a4,84(a3) 8001609e: 8001 c.srli64 s0 -800160a0: 4ac8 lw a0,20(a3) +800160a0: 4afc lw a5,84(a3) 800160a2: 8001 c.srli64 s0 -800160a4: 4acc lw a1,20(a3) +800160a4: 4b00 lw s0,16(a4) 800160a6: 8001 c.srli64 s0 -800160a8: 4ad0 lw a2,20(a3) +800160a8: 4b04 lw s1,16(a4) 800160aa: 8001 c.srli64 s0 -800160ac: 4ad4 lw a3,20(a3) +800160ac: 4b08 lw a0,16(a4) 800160ae: 8001 c.srli64 s0 -800160b0: 4ad8 lw a4,20(a3) +800160b0: 4b0c lw a1,16(a4) 800160b2: 8001 c.srli64 s0 -800160b4: 4adc lw a5,20(a3) +800160b4: 4b10 lw a2,16(a4) 800160b6: 8001 c.srli64 s0 -800160b8: 4ae0 lw s0,84(a3) +800160b8: 4b14 lw a3,16(a4) 800160ba: 8001 c.srli64 s0 -800160bc: 4ae4 lw s1,84(a3) +800160bc: 4b18 lw a4,16(a4) 800160be: 8001 c.srli64 s0 -800160c0: 4ae8 lw a0,84(a3) +800160c0: 4b1c lw a5,16(a4) 800160c2: 8001 c.srli64 s0 -800160c4: 4aec lw a1,84(a3) +800160c4: 4b20 lw s0,80(a4) 800160c6: 8001 c.srli64 s0 -800160c8: 4af0 lw a2,84(a3) +800160c8: 4b24 lw s1,80(a4) 800160ca: 8001 c.srli64 s0 800160cc : @@ -23430,37 +23429,37 @@ Disassembly of section .data: ... 800160dc : -800160dc: 4b28 lw a0,80(a4) +800160dc: 4b5c lw a5,20(a4) 800160de: 8001 c.srli64 s0 -800160e0: 4b2c lw a1,80(a4) +800160e0: 4b60 lw s0,84(a4) 800160e2: 8001 c.srli64 s0 -800160e4: 4b30 lw a2,80(a4) +800160e4: 4b64 lw s1,84(a4) 800160e6: 8001 c.srli64 s0 -800160e8: 4b34 lw a3,80(a4) +800160e8: 4b68 lw a0,84(a4) 800160ea: 8001 c.srli64 s0 -800160ec: 4b38 lw a4,80(a4) +800160ec: 4b6c lw a1,84(a4) 800160ee: 8001 c.srli64 s0 -800160f0: 4b3c lw a5,80(a4) +800160f0: 4b70 lw a2,84(a4) 800160f2: 8001 c.srli64 s0 -800160f4: 4b40 lw s0,20(a4) +800160f4: 4b74 lw a3,84(a4) 800160f6: 8001 c.srli64 s0 -800160f8: 4b44 lw s1,20(a4) +800160f8: 4b78 lw a4,84(a4) 800160fa: 8001 c.srli64 s0 -800160fc: 4b48 lw a0,20(a4) +800160fc: 4b7c lw a5,84(a4) 800160fe: 8001 c.srli64 s0 -80016100: 4b4c lw a1,20(a4) +80016100: 4b80 lw s0,16(a5) 80016102: 8001 c.srli64 s0 -80016104: 4b50 lw a2,20(a4) +80016104: 4b84 lw s1,16(a5) 80016106: 8001 c.srli64 s0 -80016108: 4b54 lw a3,20(a4) +80016108: 4b88 lw a0,16(a5) 8001610a: 8001 c.srli64 s0 -8001610c: 4b58 lw a4,20(a4) +8001610c: 4b8c lw a1,16(a5) 8001610e: 8001 c.srli64 s0 -80016110: 4b5c lw a5,20(a4) +80016110: 4b90 lw a2,16(a5) 80016112: 8001 c.srli64 s0 -80016114: 4b60 lw s0,84(a4) +80016114: 4b94 lw a3,16(a5) 80016116: 8001 c.srli64 s0 -80016118: 4b64 lw s1,84(a4) +80016118: 4b98 lw a4,16(a5) 8001611a: 8001 c.srli64 s0 8001611c : @@ -23552,580 +23551,580 @@ Disassembly of section .data: 8001625c: 0000000b 0xb ... -800165c8 <__global_locale>: -800165c8: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne +800165c8 <__malloc_av_>: ... -800165e8: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016608: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016628: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016648: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016668: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -80016688: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne - ... -800166a8: db2c sw a1,112(a4) -800166aa: 8000 0x8000 -800166ac: 8490 0x8490 -800166ae: 8000 0x8000 -800166b0: 0000 unimp -800166b2: 0000 unimp -800166b4: 54b8 lw a4,104(s1) +800165d0: 65c8 flw fa0,12(a1) +800165d2: 8001 c.srli64 s0 +800165d4: 65c8 flw fa0,12(a1) +800165d6: 8001 c.srli64 s0 +800165d8: 65d0 flw fa2,12(a1) +800165da: 8001 c.srli64 s0 +800165dc: 65d0 flw fa2,12(a1) +800165de: 8001 c.srli64 s0 +800165e0: 65d8 flw fa4,12(a1) +800165e2: 8001 c.srli64 s0 +800165e4: 65d8 flw fa4,12(a1) +800165e6: 8001 c.srli64 s0 +800165e8: 65e0 flw fs0,76(a1) +800165ea: 8001 c.srli64 s0 +800165ec: 65e0 flw fs0,76(a1) +800165ee: 8001 c.srli64 s0 +800165f0: 65e8 flw fa0,76(a1) +800165f2: 8001 c.srli64 s0 +800165f4: 65e8 flw fa0,76(a1) +800165f6: 8001 c.srli64 s0 +800165f8: 65f0 flw fa2,76(a1) +800165fa: 8001 c.srli64 s0 +800165fc: 65f0 flw fa2,76(a1) +800165fe: 8001 c.srli64 s0 +80016600: 65f8 flw fa4,76(a1) +80016602: 8001 c.srli64 s0 +80016604: 65f8 flw fa4,76(a1) +80016606: 8001 c.srli64 s0 +80016608: 6600 flw fs0,8(a2) +8001660a: 8001 c.srli64 s0 +8001660c: 6600 flw fs0,8(a2) +8001660e: 8001 c.srli64 s0 +80016610: 6608 flw fa0,8(a2) +80016612: 8001 c.srli64 s0 +80016614: 6608 flw fa0,8(a2) +80016616: 8001 c.srli64 s0 +80016618: 6610 flw fa2,8(a2) +8001661a: 8001 c.srli64 s0 +8001661c: 6610 flw fa2,8(a2) +8001661e: 8001 c.srli64 s0 +80016620: 6618 flw fa4,8(a2) +80016622: 8001 c.srli64 s0 +80016624: 6618 flw fa4,8(a2) +80016626: 8001 c.srli64 s0 +80016628: 6620 flw fs0,72(a2) +8001662a: 8001 c.srli64 s0 +8001662c: 6620 flw fs0,72(a2) +8001662e: 8001 c.srli64 s0 +80016630: 6628 flw fa0,72(a2) +80016632: 8001 c.srli64 s0 +80016634: 6628 flw fa0,72(a2) +80016636: 8001 c.srli64 s0 +80016638: 6630 flw fa2,72(a2) +8001663a: 8001 c.srli64 s0 +8001663c: 6630 flw fa2,72(a2) +8001663e: 8001 c.srli64 s0 +80016640: 6638 flw fa4,72(a2) +80016642: 8001 c.srli64 s0 +80016644: 6638 flw fa4,72(a2) +80016646: 8001 c.srli64 s0 +80016648: 6640 flw fs0,12(a2) +8001664a: 8001 c.srli64 s0 +8001664c: 6640 flw fs0,12(a2) +8001664e: 8001 c.srli64 s0 +80016650: 6648 flw fa0,12(a2) +80016652: 8001 c.srli64 s0 +80016654: 6648 flw fa0,12(a2) +80016656: 8001 c.srli64 s0 +80016658: 6650 flw fa2,12(a2) +8001665a: 8001 c.srli64 s0 +8001665c: 6650 flw fa2,12(a2) +8001665e: 8001 c.srli64 s0 +80016660: 6658 flw fa4,12(a2) +80016662: 8001 c.srli64 s0 +80016664: 6658 flw fa4,12(a2) +80016666: 8001 c.srli64 s0 +80016668: 6660 flw fs0,76(a2) +8001666a: 8001 c.srli64 s0 +8001666c: 6660 flw fs0,76(a2) +8001666e: 8001 c.srli64 s0 +80016670: 6668 flw fa0,76(a2) +80016672: 8001 c.srli64 s0 +80016674: 6668 flw fa0,76(a2) +80016676: 8001 c.srli64 s0 +80016678: 6670 flw fa2,76(a2) +8001667a: 8001 c.srli64 s0 +8001667c: 6670 flw fa2,76(a2) +8001667e: 8001 c.srli64 s0 +80016680: 6678 flw fa4,76(a2) +80016682: 8001 c.srli64 s0 +80016684: 6678 flw fa4,76(a2) +80016686: 8001 c.srli64 s0 +80016688: 6680 flw fs0,8(a3) +8001668a: 8001 c.srli64 s0 +8001668c: 6680 flw fs0,8(a3) +8001668e: 8001 c.srli64 s0 +80016690: 6688 flw fa0,8(a3) +80016692: 8001 c.srli64 s0 +80016694: 6688 flw fa0,8(a3) +80016696: 8001 c.srli64 s0 +80016698: 6690 flw fa2,8(a3) +8001669a: 8001 c.srli64 s0 +8001669c: 6690 flw fa2,8(a3) +8001669e: 8001 c.srli64 s0 +800166a0: 6698 flw fa4,8(a3) +800166a2: 8001 c.srli64 s0 +800166a4: 6698 flw fa4,8(a3) +800166a6: 8001 c.srli64 s0 +800166a8: 66a0 flw fs0,72(a3) +800166aa: 8001 c.srli64 s0 +800166ac: 66a0 flw fs0,72(a3) +800166ae: 8001 c.srli64 s0 +800166b0: 66a8 flw fa0,72(a3) +800166b2: 8001 c.srli64 s0 +800166b4: 66a8 flw fa0,72(a3) 800166b6: 8001 c.srli64 s0 -800166b8: 5074 lw a3,100(s0) +800166b8: 66b0 flw fa2,72(a3) 800166ba: 8001 c.srli64 s0 -800166bc: 4c50 lw a2,28(s0) +800166bc: 66b0 flw fa2,72(a3) 800166be: 8001 c.srli64 s0 -800166c0: 4c50 lw a2,28(s0) +800166c0: 66b8 flw fa4,72(a3) 800166c2: 8001 c.srli64 s0 -800166c4: 4c50 lw a2,28(s0) +800166c4: 66b8 flw fa4,72(a3) 800166c6: 8001 c.srli64 s0 -800166c8: 4c50 lw a2,28(s0) +800166c8: 66c0 flw fs0,12(a3) 800166ca: 8001 c.srli64 s0 -800166cc: 4c50 lw a2,28(s0) +800166cc: 66c0 flw fs0,12(a3) 800166ce: 8001 c.srli64 s0 -800166d0: 4c50 lw a2,28(s0) +800166d0: 66c8 flw fa0,12(a3) 800166d2: 8001 c.srli64 s0 -800166d4: 4c50 lw a2,28(s0) +800166d4: 66c8 flw fa0,12(a3) 800166d6: 8001 c.srli64 s0 -800166d8: 4c50 lw a2,28(s0) +800166d8: 66d0 flw fa2,12(a3) 800166da: 8001 c.srli64 s0 -800166dc: 4c50 lw a2,28(s0) +800166dc: 66d0 flw fa2,12(a3) 800166de: 8001 c.srli64 s0 -800166e0: ffff 0xffff -800166e2: ffff 0xffff -800166e4: ffff 0xffff -800166e6: ffff 0xffff -800166e8: ffff 0xffff -800166ea: ffff 0xffff -800166ec: ffff 0xffff -800166ee: 0000 unimp -800166f0: 0001 nop -800166f2: 5341 li t1,-16 -800166f4: 00494943 fmadd.s fs2,fs2,ft4,ft0,rmm - ... -80016710: 0000 unimp -80016712: 5341 li t1,-16 -80016714: 00494943 fmadd.s fs2,fs2,ft4,ft0,rmm - ... - -80016734 <__malloc_av_>: - ... -8001673c: 6734 flw fa3,72(a4) +800166e0: 66d8 flw fa4,12(a3) +800166e2: 8001 c.srli64 s0 +800166e4: 66d8 flw fa4,12(a3) +800166e6: 8001 c.srli64 s0 +800166e8: 66e0 flw fs0,76(a3) +800166ea: 8001 c.srli64 s0 +800166ec: 66e0 flw fs0,76(a3) +800166ee: 8001 c.srli64 s0 +800166f0: 66e8 flw fa0,76(a3) +800166f2: 8001 c.srli64 s0 +800166f4: 66e8 flw fa0,76(a3) +800166f6: 8001 c.srli64 s0 +800166f8: 66f0 flw fa2,76(a3) +800166fa: 8001 c.srli64 s0 +800166fc: 66f0 flw fa2,76(a3) +800166fe: 8001 c.srli64 s0 +80016700: 66f8 flw fa4,76(a3) +80016702: 8001 c.srli64 s0 +80016704: 66f8 flw fa4,76(a3) +80016706: 8001 c.srli64 s0 +80016708: 6700 flw fs0,8(a4) +8001670a: 8001 c.srli64 s0 +8001670c: 6700 flw fs0,8(a4) +8001670e: 8001 c.srli64 s0 +80016710: 6708 flw fa0,8(a4) +80016712: 8001 c.srli64 s0 +80016714: 6708 flw fa0,8(a4) +80016716: 8001 c.srli64 s0 +80016718: 6710 flw fa2,8(a4) +8001671a: 8001 c.srli64 s0 +8001671c: 6710 flw fa2,8(a4) +8001671e: 8001 c.srli64 s0 +80016720: 6718 flw fa4,8(a4) +80016722: 8001 c.srli64 s0 +80016724: 6718 flw fa4,8(a4) +80016726: 8001 c.srli64 s0 +80016728: 6720 flw fs0,72(a4) +8001672a: 8001 c.srli64 s0 +8001672c: 6720 flw fs0,72(a4) +8001672e: 8001 c.srli64 s0 +80016730: 6728 flw fa0,72(a4) +80016732: 8001 c.srli64 s0 +80016734: 6728 flw fa0,72(a4) +80016736: 8001 c.srli64 s0 +80016738: 6730 flw fa2,72(a4) +8001673a: 8001 c.srli64 s0 +8001673c: 6730 flw fa2,72(a4) 8001673e: 8001 c.srli64 s0 -80016740: 6734 flw fa3,72(a4) +80016740: 6738 flw fa4,72(a4) 80016742: 8001 c.srli64 s0 -80016744: 673c flw fa5,72(a4) +80016744: 6738 flw fa4,72(a4) 80016746: 8001 c.srli64 s0 -80016748: 673c flw fa5,72(a4) +80016748: 6740 flw fs0,12(a4) 8001674a: 8001 c.srli64 s0 -8001674c: 6744 flw fs1,12(a4) +8001674c: 6740 flw fs0,12(a4) 8001674e: 8001 c.srli64 s0 -80016750: 6744 flw fs1,12(a4) +80016750: 6748 flw fa0,12(a4) 80016752: 8001 c.srli64 s0 -80016754: 674c flw fa1,12(a4) +80016754: 6748 flw fa0,12(a4) 80016756: 8001 c.srli64 s0 -80016758: 674c flw fa1,12(a4) +80016758: 6750 flw fa2,12(a4) 8001675a: 8001 c.srli64 s0 -8001675c: 6754 flw fa3,12(a4) +8001675c: 6750 flw fa2,12(a4) 8001675e: 8001 c.srli64 s0 -80016760: 6754 flw fa3,12(a4) +80016760: 6758 flw fa4,12(a4) 80016762: 8001 c.srli64 s0 -80016764: 675c flw fa5,12(a4) +80016764: 6758 flw fa4,12(a4) 80016766: 8001 c.srli64 s0 -80016768: 675c flw fa5,12(a4) +80016768: 6760 flw fs0,76(a4) 8001676a: 8001 c.srli64 s0 -8001676c: 6764 flw fs1,76(a4) +8001676c: 6760 flw fs0,76(a4) 8001676e: 8001 c.srli64 s0 -80016770: 6764 flw fs1,76(a4) +80016770: 6768 flw fa0,76(a4) 80016772: 8001 c.srli64 s0 -80016774: 676c flw fa1,76(a4) +80016774: 6768 flw fa0,76(a4) 80016776: 8001 c.srli64 s0 -80016778: 676c flw fa1,76(a4) +80016778: 6770 flw fa2,76(a4) 8001677a: 8001 c.srli64 s0 -8001677c: 6774 flw fa3,76(a4) +8001677c: 6770 flw fa2,76(a4) 8001677e: 8001 c.srli64 s0 -80016780: 6774 flw fa3,76(a4) +80016780: 6778 flw fa4,76(a4) 80016782: 8001 c.srli64 s0 -80016784: 677c flw fa5,76(a4) +80016784: 6778 flw fa4,76(a4) 80016786: 8001 c.srli64 s0 -80016788: 677c flw fa5,76(a4) +80016788: 6780 flw fs0,8(a5) 8001678a: 8001 c.srli64 s0 -8001678c: 6784 flw fs1,8(a5) +8001678c: 6780 flw fs0,8(a5) 8001678e: 8001 c.srli64 s0 -80016790: 6784 flw fs1,8(a5) +80016790: 6788 flw fa0,8(a5) 80016792: 8001 c.srli64 s0 -80016794: 678c flw fa1,8(a5) +80016794: 6788 flw fa0,8(a5) 80016796: 8001 c.srli64 s0 -80016798: 678c flw fa1,8(a5) +80016798: 6790 flw fa2,8(a5) 8001679a: 8001 c.srli64 s0 -8001679c: 6794 flw fa3,8(a5) +8001679c: 6790 flw fa2,8(a5) 8001679e: 8001 c.srli64 s0 -800167a0: 6794 flw fa3,8(a5) +800167a0: 6798 flw fa4,8(a5) 800167a2: 8001 c.srli64 s0 -800167a4: 679c flw fa5,8(a5) +800167a4: 6798 flw fa4,8(a5) 800167a6: 8001 c.srli64 s0 -800167a8: 679c flw fa5,8(a5) +800167a8: 67a0 flw fs0,72(a5) 800167aa: 8001 c.srli64 s0 -800167ac: 67a4 flw fs1,72(a5) +800167ac: 67a0 flw fs0,72(a5) 800167ae: 8001 c.srli64 s0 -800167b0: 67a4 flw fs1,72(a5) +800167b0: 67a8 flw fa0,72(a5) 800167b2: 8001 c.srli64 s0 -800167b4: 67ac flw fa1,72(a5) +800167b4: 67a8 flw fa0,72(a5) 800167b6: 8001 c.srli64 s0 -800167b8: 67ac flw fa1,72(a5) +800167b8: 67b0 flw fa2,72(a5) 800167ba: 8001 c.srli64 s0 -800167bc: 67b4 flw fa3,72(a5) +800167bc: 67b0 flw fa2,72(a5) 800167be: 8001 c.srli64 s0 -800167c0: 67b4 flw fa3,72(a5) +800167c0: 67b8 flw fa4,72(a5) 800167c2: 8001 c.srli64 s0 -800167c4: 67bc flw fa5,72(a5) +800167c4: 67b8 flw fa4,72(a5) 800167c6: 8001 c.srli64 s0 -800167c8: 67bc flw fa5,72(a5) +800167c8: 67c0 flw fs0,12(a5) 800167ca: 8001 c.srli64 s0 -800167cc: 67c4 flw fs1,12(a5) +800167cc: 67c0 flw fs0,12(a5) 800167ce: 8001 c.srli64 s0 -800167d0: 67c4 flw fs1,12(a5) +800167d0: 67c8 flw fa0,12(a5) 800167d2: 8001 c.srli64 s0 -800167d4: 67cc flw fa1,12(a5) +800167d4: 67c8 flw fa0,12(a5) 800167d6: 8001 c.srli64 s0 -800167d8: 67cc flw fa1,12(a5) +800167d8: 67d0 flw fa2,12(a5) 800167da: 8001 c.srli64 s0 -800167dc: 67d4 flw fa3,12(a5) +800167dc: 67d0 flw fa2,12(a5) 800167de: 8001 c.srli64 s0 -800167e0: 67d4 flw fa3,12(a5) +800167e0: 67d8 flw fa4,12(a5) 800167e2: 8001 c.srli64 s0 -800167e4: 67dc flw fa5,12(a5) +800167e4: 67d8 flw fa4,12(a5) 800167e6: 8001 c.srli64 s0 -800167e8: 67dc flw fa5,12(a5) +800167e8: 67e0 flw fs0,76(a5) 800167ea: 8001 c.srli64 s0 -800167ec: 67e4 flw fs1,76(a5) +800167ec: 67e0 flw fs0,76(a5) 800167ee: 8001 c.srli64 s0 -800167f0: 67e4 flw fs1,76(a5) +800167f0: 67e8 flw fa0,76(a5) 800167f2: 8001 c.srli64 s0 -800167f4: 67ec flw fa1,76(a5) +800167f4: 67e8 flw fa0,76(a5) 800167f6: 8001 c.srli64 s0 -800167f8: 67ec flw fa1,76(a5) +800167f8: 67f0 flw fa2,76(a5) 800167fa: 8001 c.srli64 s0 -800167fc: 67f4 flw fa3,76(a5) +800167fc: 67f0 flw fa2,76(a5) 800167fe: 8001 c.srli64 s0 -80016800: 67f4 flw fa3,76(a5) +80016800: 67f8 flw fa4,76(a5) 80016802: 8001 c.srli64 s0 -80016804: 67fc flw fa5,76(a5) +80016804: 67f8 flw fa4,76(a5) 80016806: 8001 c.srli64 s0 -80016808: 67fc flw fa5,76(a5) +80016808: 6800 flw fs0,16(s0) 8001680a: 8001 c.srli64 s0 -8001680c: 6804 flw fs1,16(s0) +8001680c: 6800 flw fs0,16(s0) 8001680e: 8001 c.srli64 s0 -80016810: 6804 flw fs1,16(s0) +80016810: 6808 flw fa0,16(s0) 80016812: 8001 c.srli64 s0 -80016814: 680c flw fa1,16(s0) +80016814: 6808 flw fa0,16(s0) 80016816: 8001 c.srli64 s0 -80016818: 680c flw fa1,16(s0) +80016818: 6810 flw fa2,16(s0) 8001681a: 8001 c.srli64 s0 -8001681c: 6814 flw fa3,16(s0) +8001681c: 6810 flw fa2,16(s0) 8001681e: 8001 c.srli64 s0 -80016820: 6814 flw fa3,16(s0) +80016820: 6818 flw fa4,16(s0) 80016822: 8001 c.srli64 s0 -80016824: 681c flw fa5,16(s0) +80016824: 6818 flw fa4,16(s0) 80016826: 8001 c.srli64 s0 -80016828: 681c flw fa5,16(s0) +80016828: 6820 flw fs0,80(s0) 8001682a: 8001 c.srli64 s0 -8001682c: 6824 flw fs1,80(s0) +8001682c: 6820 flw fs0,80(s0) 8001682e: 8001 c.srli64 s0 -80016830: 6824 flw fs1,80(s0) +80016830: 6828 flw fa0,80(s0) 80016832: 8001 c.srli64 s0 -80016834: 682c flw fa1,80(s0) +80016834: 6828 flw fa0,80(s0) 80016836: 8001 c.srli64 s0 -80016838: 682c flw fa1,80(s0) +80016838: 6830 flw fa2,80(s0) 8001683a: 8001 c.srli64 s0 -8001683c: 6834 flw fa3,80(s0) +8001683c: 6830 flw fa2,80(s0) 8001683e: 8001 c.srli64 s0 -80016840: 6834 flw fa3,80(s0) +80016840: 6838 flw fa4,80(s0) 80016842: 8001 c.srli64 s0 -80016844: 683c flw fa5,80(s0) +80016844: 6838 flw fa4,80(s0) 80016846: 8001 c.srli64 s0 -80016848: 683c flw fa5,80(s0) +80016848: 6840 flw fs0,20(s0) 8001684a: 8001 c.srli64 s0 -8001684c: 6844 flw fs1,20(s0) +8001684c: 6840 flw fs0,20(s0) 8001684e: 8001 c.srli64 s0 -80016850: 6844 flw fs1,20(s0) +80016850: 6848 flw fa0,20(s0) 80016852: 8001 c.srli64 s0 -80016854: 684c flw fa1,20(s0) +80016854: 6848 flw fa0,20(s0) 80016856: 8001 c.srli64 s0 -80016858: 684c flw fa1,20(s0) +80016858: 6850 flw fa2,20(s0) 8001685a: 8001 c.srli64 s0 -8001685c: 6854 flw fa3,20(s0) +8001685c: 6850 flw fa2,20(s0) 8001685e: 8001 c.srli64 s0 -80016860: 6854 flw fa3,20(s0) +80016860: 6858 flw fa4,20(s0) 80016862: 8001 c.srli64 s0 -80016864: 685c flw fa5,20(s0) +80016864: 6858 flw fa4,20(s0) 80016866: 8001 c.srli64 s0 -80016868: 685c flw fa5,20(s0) +80016868: 6860 flw fs0,84(s0) 8001686a: 8001 c.srli64 s0 -8001686c: 6864 flw fs1,84(s0) +8001686c: 6860 flw fs0,84(s0) 8001686e: 8001 c.srli64 s0 -80016870: 6864 flw fs1,84(s0) +80016870: 6868 flw fa0,84(s0) 80016872: 8001 c.srli64 s0 -80016874: 686c flw fa1,84(s0) +80016874: 6868 flw fa0,84(s0) 80016876: 8001 c.srli64 s0 -80016878: 686c flw fa1,84(s0) +80016878: 6870 flw fa2,84(s0) 8001687a: 8001 c.srli64 s0 -8001687c: 6874 flw fa3,84(s0) +8001687c: 6870 flw fa2,84(s0) 8001687e: 8001 c.srli64 s0 -80016880: 6874 flw fa3,84(s0) +80016880: 6878 flw fa4,84(s0) 80016882: 8001 c.srli64 s0 -80016884: 687c flw fa5,84(s0) +80016884: 6878 flw fa4,84(s0) 80016886: 8001 c.srli64 s0 -80016888: 687c flw fa5,84(s0) +80016888: 6880 flw fs0,16(s1) 8001688a: 8001 c.srli64 s0 -8001688c: 6884 flw fs1,16(s1) +8001688c: 6880 flw fs0,16(s1) 8001688e: 8001 c.srli64 s0 -80016890: 6884 flw fs1,16(s1) +80016890: 6888 flw fa0,16(s1) 80016892: 8001 c.srli64 s0 -80016894: 688c flw fa1,16(s1) +80016894: 6888 flw fa0,16(s1) 80016896: 8001 c.srli64 s0 -80016898: 688c flw fa1,16(s1) +80016898: 6890 flw fa2,16(s1) 8001689a: 8001 c.srli64 s0 -8001689c: 6894 flw fa3,16(s1) +8001689c: 6890 flw fa2,16(s1) 8001689e: 8001 c.srli64 s0 -800168a0: 6894 flw fa3,16(s1) +800168a0: 6898 flw fa4,16(s1) 800168a2: 8001 c.srli64 s0 -800168a4: 689c flw fa5,16(s1) +800168a4: 6898 flw fa4,16(s1) 800168a6: 8001 c.srli64 s0 -800168a8: 689c flw fa5,16(s1) +800168a8: 68a0 flw fs0,80(s1) 800168aa: 8001 c.srli64 s0 -800168ac: 68a4 flw fs1,80(s1) +800168ac: 68a0 flw fs0,80(s1) 800168ae: 8001 c.srli64 s0 -800168b0: 68a4 flw fs1,80(s1) +800168b0: 68a8 flw fa0,80(s1) 800168b2: 8001 c.srli64 s0 -800168b4: 68ac flw fa1,80(s1) +800168b4: 68a8 flw fa0,80(s1) 800168b6: 8001 c.srli64 s0 -800168b8: 68ac flw fa1,80(s1) +800168b8: 68b0 flw fa2,80(s1) 800168ba: 8001 c.srli64 s0 -800168bc: 68b4 flw fa3,80(s1) +800168bc: 68b0 flw fa2,80(s1) 800168be: 8001 c.srli64 s0 -800168c0: 68b4 flw fa3,80(s1) +800168c0: 68b8 flw fa4,80(s1) 800168c2: 8001 c.srli64 s0 -800168c4: 68bc flw fa5,80(s1) +800168c4: 68b8 flw fa4,80(s1) 800168c6: 8001 c.srli64 s0 -800168c8: 68bc flw fa5,80(s1) +800168c8: 68c0 flw fs0,20(s1) 800168ca: 8001 c.srli64 s0 -800168cc: 68c4 flw fs1,20(s1) +800168cc: 68c0 flw fs0,20(s1) 800168ce: 8001 c.srli64 s0 -800168d0: 68c4 flw fs1,20(s1) +800168d0: 68c8 flw fa0,20(s1) 800168d2: 8001 c.srli64 s0 -800168d4: 68cc flw fa1,20(s1) +800168d4: 68c8 flw fa0,20(s1) 800168d6: 8001 c.srli64 s0 -800168d8: 68cc flw fa1,20(s1) +800168d8: 68d0 flw fa2,20(s1) 800168da: 8001 c.srli64 s0 -800168dc: 68d4 flw fa3,20(s1) +800168dc: 68d0 flw fa2,20(s1) 800168de: 8001 c.srli64 s0 -800168e0: 68d4 flw fa3,20(s1) +800168e0: 68d8 flw fa4,20(s1) 800168e2: 8001 c.srli64 s0 -800168e4: 68dc flw fa5,20(s1) +800168e4: 68d8 flw fa4,20(s1) 800168e6: 8001 c.srli64 s0 -800168e8: 68dc flw fa5,20(s1) +800168e8: 68e0 flw fs0,84(s1) 800168ea: 8001 c.srli64 s0 -800168ec: 68e4 flw fs1,84(s1) +800168ec: 68e0 flw fs0,84(s1) 800168ee: 8001 c.srli64 s0 -800168f0: 68e4 flw fs1,84(s1) +800168f0: 68e8 flw fa0,84(s1) 800168f2: 8001 c.srli64 s0 -800168f4: 68ec flw fa1,84(s1) +800168f4: 68e8 flw fa0,84(s1) 800168f6: 8001 c.srli64 s0 -800168f8: 68ec flw fa1,84(s1) +800168f8: 68f0 flw fa2,84(s1) 800168fa: 8001 c.srli64 s0 -800168fc: 68f4 flw fa3,84(s1) +800168fc: 68f0 flw fa2,84(s1) 800168fe: 8001 c.srli64 s0 -80016900: 68f4 flw fa3,84(s1) +80016900: 68f8 flw fa4,84(s1) 80016902: 8001 c.srli64 s0 -80016904: 68fc flw fa5,84(s1) +80016904: 68f8 flw fa4,84(s1) 80016906: 8001 c.srli64 s0 -80016908: 68fc flw fa5,84(s1) +80016908: 6900 flw fs0,16(a0) 8001690a: 8001 c.srli64 s0 -8001690c: 6904 flw fs1,16(a0) +8001690c: 6900 flw fs0,16(a0) 8001690e: 8001 c.srli64 s0 -80016910: 6904 flw fs1,16(a0) +80016910: 6908 flw fa0,16(a0) 80016912: 8001 c.srli64 s0 -80016914: 690c flw fa1,16(a0) +80016914: 6908 flw fa0,16(a0) 80016916: 8001 c.srli64 s0 -80016918: 690c flw fa1,16(a0) +80016918: 6910 flw fa2,16(a0) 8001691a: 8001 c.srli64 s0 -8001691c: 6914 flw fa3,16(a0) +8001691c: 6910 flw fa2,16(a0) 8001691e: 8001 c.srli64 s0 -80016920: 6914 flw fa3,16(a0) +80016920: 6918 flw fa4,16(a0) 80016922: 8001 c.srli64 s0 -80016924: 691c flw fa5,16(a0) +80016924: 6918 flw fa4,16(a0) 80016926: 8001 c.srli64 s0 -80016928: 691c flw fa5,16(a0) +80016928: 6920 flw fs0,80(a0) 8001692a: 8001 c.srli64 s0 -8001692c: 6924 flw fs1,80(a0) +8001692c: 6920 flw fs0,80(a0) 8001692e: 8001 c.srli64 s0 -80016930: 6924 flw fs1,80(a0) +80016930: 6928 flw fa0,80(a0) 80016932: 8001 c.srli64 s0 -80016934: 692c flw fa1,80(a0) +80016934: 6928 flw fa0,80(a0) 80016936: 8001 c.srli64 s0 -80016938: 692c flw fa1,80(a0) +80016938: 6930 flw fa2,80(a0) 8001693a: 8001 c.srli64 s0 -8001693c: 6934 flw fa3,80(a0) +8001693c: 6930 flw fa2,80(a0) 8001693e: 8001 c.srli64 s0 -80016940: 6934 flw fa3,80(a0) +80016940: 6938 flw fa4,80(a0) 80016942: 8001 c.srli64 s0 -80016944: 693c flw fa5,80(a0) +80016944: 6938 flw fa4,80(a0) 80016946: 8001 c.srli64 s0 -80016948: 693c flw fa5,80(a0) +80016948: 6940 flw fs0,20(a0) 8001694a: 8001 c.srli64 s0 -8001694c: 6944 flw fs1,20(a0) +8001694c: 6940 flw fs0,20(a0) 8001694e: 8001 c.srli64 s0 -80016950: 6944 flw fs1,20(a0) +80016950: 6948 flw fa0,20(a0) 80016952: 8001 c.srli64 s0 -80016954: 694c flw fa1,20(a0) +80016954: 6948 flw fa0,20(a0) 80016956: 8001 c.srli64 s0 -80016958: 694c flw fa1,20(a0) +80016958: 6950 flw fa2,20(a0) 8001695a: 8001 c.srli64 s0 -8001695c: 6954 flw fa3,20(a0) +8001695c: 6950 flw fa2,20(a0) 8001695e: 8001 c.srli64 s0 -80016960: 6954 flw fa3,20(a0) +80016960: 6958 flw fa4,20(a0) 80016962: 8001 c.srli64 s0 -80016964: 695c flw fa5,20(a0) +80016964: 6958 flw fa4,20(a0) 80016966: 8001 c.srli64 s0 -80016968: 695c flw fa5,20(a0) +80016968: 6960 flw fs0,84(a0) 8001696a: 8001 c.srli64 s0 -8001696c: 6964 flw fs1,84(a0) +8001696c: 6960 flw fs0,84(a0) 8001696e: 8001 c.srli64 s0 -80016970: 6964 flw fs1,84(a0) +80016970: 6968 flw fa0,84(a0) 80016972: 8001 c.srli64 s0 -80016974: 696c flw fa1,84(a0) +80016974: 6968 flw fa0,84(a0) 80016976: 8001 c.srli64 s0 -80016978: 696c flw fa1,84(a0) +80016978: 6970 flw fa2,84(a0) 8001697a: 8001 c.srli64 s0 -8001697c: 6974 flw fa3,84(a0) +8001697c: 6970 flw fa2,84(a0) 8001697e: 8001 c.srli64 s0 -80016980: 6974 flw fa3,84(a0) +80016980: 6978 flw fa4,84(a0) 80016982: 8001 c.srli64 s0 -80016984: 697c flw fa5,84(a0) +80016984: 6978 flw fa4,84(a0) 80016986: 8001 c.srli64 s0 -80016988: 697c flw fa5,84(a0) +80016988: 6980 flw fs0,16(a1) 8001698a: 8001 c.srli64 s0 -8001698c: 6984 flw fs1,16(a1) +8001698c: 6980 flw fs0,16(a1) 8001698e: 8001 c.srli64 s0 -80016990: 6984 flw fs1,16(a1) +80016990: 6988 flw fa0,16(a1) 80016992: 8001 c.srli64 s0 -80016994: 698c flw fa1,16(a1) +80016994: 6988 flw fa0,16(a1) 80016996: 8001 c.srli64 s0 -80016998: 698c flw fa1,16(a1) +80016998: 6990 flw fa2,16(a1) 8001699a: 8001 c.srli64 s0 -8001699c: 6994 flw fa3,16(a1) +8001699c: 6990 flw fa2,16(a1) 8001699e: 8001 c.srli64 s0 -800169a0: 6994 flw fa3,16(a1) +800169a0: 6998 flw fa4,16(a1) 800169a2: 8001 c.srli64 s0 -800169a4: 699c flw fa5,16(a1) +800169a4: 6998 flw fa4,16(a1) 800169a6: 8001 c.srli64 s0 -800169a8: 699c flw fa5,16(a1) +800169a8: 69a0 flw fs0,80(a1) 800169aa: 8001 c.srli64 s0 -800169ac: 69a4 flw fs1,80(a1) +800169ac: 69a0 flw fs0,80(a1) 800169ae: 8001 c.srli64 s0 -800169b0: 69a4 flw fs1,80(a1) +800169b0: 69a8 flw fa0,80(a1) 800169b2: 8001 c.srli64 s0 -800169b4: 69ac flw fa1,80(a1) +800169b4: 69a8 flw fa0,80(a1) 800169b6: 8001 c.srli64 s0 -800169b8: 69ac flw fa1,80(a1) +800169b8: 69b0 flw fa2,80(a1) 800169ba: 8001 c.srli64 s0 -800169bc: 69b4 flw fa3,80(a1) +800169bc: 69b0 flw fa2,80(a1) 800169be: 8001 c.srli64 s0 -800169c0: 69b4 flw fa3,80(a1) +800169c0: 69b8 flw fa4,80(a1) 800169c2: 8001 c.srli64 s0 -800169c4: 69bc flw fa5,80(a1) +800169c4: 69b8 flw fa4,80(a1) 800169c6: 8001 c.srli64 s0 -800169c8: 69bc flw fa5,80(a1) +800169c8: 69c0 flw fs0,20(a1) 800169ca: 8001 c.srli64 s0 -800169cc: 69c4 flw fs1,20(a1) +800169cc: 69c0 flw fs0,20(a1) 800169ce: 8001 c.srli64 s0 -800169d0: 69c4 flw fs1,20(a1) -800169d2: 8001 c.srli64 s0 -800169d4: 69cc flw fa1,20(a1) -800169d6: 8001 c.srli64 s0 -800169d8: 69cc flw fa1,20(a1) -800169da: 8001 c.srli64 s0 -800169dc: 69d4 flw fa3,20(a1) -800169de: 8001 c.srli64 s0 -800169e0: 69d4 flw fa3,20(a1) -800169e2: 8001 c.srli64 s0 -800169e4: 69dc flw fa5,20(a1) -800169e6: 8001 c.srli64 s0 -800169e8: 69dc flw fa5,20(a1) -800169ea: 8001 c.srli64 s0 -800169ec: 69e4 flw fs1,84(a1) -800169ee: 8001 c.srli64 s0 -800169f0: 69e4 flw fs1,84(a1) -800169f2: 8001 c.srli64 s0 -800169f4: 69ec flw fa1,84(a1) -800169f6: 8001 c.srli64 s0 -800169f8: 69ec flw fa1,84(a1) -800169fa: 8001 c.srli64 s0 -800169fc: 69f4 flw fa3,84(a1) -800169fe: 8001 c.srli64 s0 -80016a00: 69f4 flw fa3,84(a1) -80016a02: 8001 c.srli64 s0 -80016a04: 69fc flw fa5,84(a1) -80016a06: 8001 c.srli64 s0 -80016a08: 69fc flw fa5,84(a1) -80016a0a: 8001 c.srli64 s0 -80016a0c: 6a04 flw fs1,16(a2) -80016a0e: 8001 c.srli64 s0 -80016a10: 6a04 flw fs1,16(a2) -80016a12: 8001 c.srli64 s0 -80016a14: 6a0c flw fa1,16(a2) -80016a16: 8001 c.srli64 s0 -80016a18: 6a0c flw fa1,16(a2) -80016a1a: 8001 c.srli64 s0 -80016a1c: 6a14 flw fa3,16(a2) -80016a1e: 8001 c.srli64 s0 -80016a20: 6a14 flw fa3,16(a2) -80016a22: 8001 c.srli64 s0 -80016a24: 6a1c flw fa5,16(a2) -80016a26: 8001 c.srli64 s0 -80016a28: 6a1c flw fa5,16(a2) -80016a2a: 8001 c.srli64 s0 -80016a2c: 6a24 flw fs1,80(a2) -80016a2e: 8001 c.srli64 s0 -80016a30: 6a24 flw fs1,80(a2) -80016a32: 8001 c.srli64 s0 -80016a34: 6a2c flw fa1,80(a2) -80016a36: 8001 c.srli64 s0 -80016a38: 6a2c flw fa1,80(a2) -80016a3a: 8001 c.srli64 s0 -80016a3c: 6a34 flw fa3,80(a2) -80016a3e: 8001 c.srli64 s0 -80016a40: 6a34 flw fa3,80(a2) -80016a42: 8001 c.srli64 s0 -80016a44: 6a3c flw fa5,80(a2) -80016a46: 8001 c.srli64 s0 -80016a48: 6a3c flw fa5,80(a2) -80016a4a: 8001 c.srli64 s0 -80016a4c: 6a44 flw fs1,20(a2) -80016a4e: 8001 c.srli64 s0 -80016a50: 6a44 flw fs1,20(a2) -80016a52: 8001 c.srli64 s0 -80016a54: 6a4c flw fa1,20(a2) -80016a56: 8001 c.srli64 s0 -80016a58: 6a4c flw fa1,20(a2) -80016a5a: 8001 c.srli64 s0 -80016a5c: 6a54 flw fa3,20(a2) -80016a5e: 8001 c.srli64 s0 -80016a60: 6a54 flw fa3,20(a2) -80016a62: 8001 c.srli64 s0 -80016a64: 6a5c flw fa5,20(a2) -80016a66: 8001 c.srli64 s0 -80016a68: 6a5c flw fa5,20(a2) -80016a6a: 8001 c.srli64 s0 -80016a6c: 6a64 flw fs1,84(a2) -80016a6e: 8001 c.srli64 s0 -80016a70: 6a64 flw fs1,84(a2) -80016a72: 8001 c.srli64 s0 -80016a74: 6a6c flw fa1,84(a2) -80016a76: 8001 c.srli64 s0 -80016a78: 6a6c flw fa1,84(a2) -80016a7a: 8001 c.srli64 s0 -80016a7c: 6a74 flw fa3,84(a2) -80016a7e: 8001 c.srli64 s0 -80016a80: 6a74 flw fa3,84(a2) -80016a82: 8001 c.srli64 s0 -80016a84: 6a7c flw fa5,84(a2) -80016a86: 8001 c.srli64 s0 -80016a88: 6a7c flw fa5,84(a2) -80016a8a: 8001 c.srli64 s0 -80016a8c: 6a84 flw fs1,16(a3) -80016a8e: 8001 c.srli64 s0 -80016a90: 6a84 flw fs1,16(a3) -80016a92: 8001 c.srli64 s0 -80016a94: 6a8c flw fa1,16(a3) -80016a96: 8001 c.srli64 s0 -80016a98: 6a8c flw fa1,16(a3) -80016a9a: 8001 c.srli64 s0 -80016a9c: 6a94 flw fa3,16(a3) -80016a9e: 8001 c.srli64 s0 -80016aa0: 6a94 flw fa3,16(a3) -80016aa2: 8001 c.srli64 s0 -80016aa4: 6a9c flw fa5,16(a3) -80016aa6: 8001 c.srli64 s0 -80016aa8: 6a9c flw fa5,16(a3) -80016aaa: 8001 c.srli64 s0 -80016aac: 6aa4 flw fs1,80(a3) -80016aae: 8001 c.srli64 s0 -80016ab0: 6aa4 flw fs1,80(a3) + +800169d0 <__global_locale>: +800169d0: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne + ... +800169f0: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne + ... +80016a10: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne + ... +80016a30: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne + ... +80016a50: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne + ... +80016a70: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne + ... +80016a90: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne + ... +80016ab0: 0494 addi a3,sp,576 80016ab2: 8001 c.srli64 s0 -80016ab4: 6aac flw fa1,80(a3) -80016ab6: 8001 c.srli64 s0 -80016ab8: 6aac flw fa1,80(a3) -80016aba: 8001 c.srli64 s0 -80016abc: 6ab4 flw fa3,80(a3) +80016ab4: e438 fsw fa4,72(s0) +80016ab6: 8000 0x8000 +80016ab8: 0000 unimp +80016aba: 0000 unimp +80016abc: 5694 lw a3,40(a3) 80016abe: 8001 c.srli64 s0 -80016ac0: 6ab4 flw fa3,80(a3) +80016ac0: 5504 lw s1,40(a0) 80016ac2: 8001 c.srli64 s0 -80016ac4: 6abc flw fa5,80(a3) +80016ac4: 4c9c lw a5,24(s1) 80016ac6: 8001 c.srli64 s0 -80016ac8: 6abc flw fa5,80(a3) +80016ac8: 4c9c lw a5,24(s1) 80016aca: 8001 c.srli64 s0 -80016acc: 6ac4 flw fs1,20(a3) +80016acc: 4c9c lw a5,24(s1) 80016ace: 8001 c.srli64 s0 -80016ad0: 6ac4 flw fs1,20(a3) +80016ad0: 4c9c lw a5,24(s1) 80016ad2: 8001 c.srli64 s0 -80016ad4: 6acc flw fa1,20(a3) +80016ad4: 4c9c lw a5,24(s1) 80016ad6: 8001 c.srli64 s0 -80016ad8: 6acc flw fa1,20(a3) +80016ad8: 4c9c lw a5,24(s1) 80016ada: 8001 c.srli64 s0 -80016adc: 6ad4 flw fa3,20(a3) +80016adc: 4c9c lw a5,24(s1) 80016ade: 8001 c.srli64 s0 -80016ae0: 6ad4 flw fa3,20(a3) +80016ae0: 4c9c lw a5,24(s1) 80016ae2: 8001 c.srli64 s0 -80016ae4: 6adc flw fa5,20(a3) +80016ae4: 4c9c lw a5,24(s1) 80016ae6: 8001 c.srli64 s0 -80016ae8: 6adc flw fa5,20(a3) -80016aea: 8001 c.srli64 s0 -80016aec: 6ae4 flw fs1,84(a3) -80016aee: 8001 c.srli64 s0 -80016af0: 6ae4 flw fs1,84(a3) -80016af2: 8001 c.srli64 s0 -80016af4: 6aec flw fa1,84(a3) -80016af6: 8001 c.srli64 s0 -80016af8: 6aec flw fa1,84(a3) -80016afa: 8001 c.srli64 s0 -80016afc: 6af4 flw fa3,84(a3) -80016afe: 8001 c.srli64 s0 -80016b00: 6af4 flw fa3,84(a3) -80016b02: 8001 c.srli64 s0 -80016b04: 6afc flw fa5,84(a3) -80016b06: 8001 c.srli64 s0 -80016b08: 6afc flw fa5,84(a3) -80016b0a: 8001 c.srli64 s0 -80016b0c: 6b04 flw fs1,16(a4) -80016b0e: 8001 c.srli64 s0 -80016b10: 6b04 flw fs1,16(a4) -80016b12: 8001 c.srli64 s0 -80016b14: 6b0c flw fa1,16(a4) -80016b16: 8001 c.srli64 s0 -80016b18: 6b0c flw fa1,16(a4) -80016b1a: 8001 c.srli64 s0 -80016b1c: 6b14 flw fa3,16(a4) -80016b1e: 8001 c.srli64 s0 -80016b20: 6b14 flw fa3,16(a4) -80016b22: 8001 c.srli64 s0 -80016b24: 6b1c flw fa5,16(a4) -80016b26: 8001 c.srli64 s0 -80016b28: 6b1c flw fa5,16(a4) -80016b2a: 8001 c.srli64 s0 -80016b2c: 6b24 flw fs1,80(a4) -80016b2e: 8001 c.srli64 s0 -80016b30: 6b24 flw fs1,80(a4) -80016b32: 8001 c.srli64 s0 -80016b34: 6b2c flw fa1,80(a4) -80016b36: 8001 c.srli64 s0 -80016b38: 6b2c flw fa1,80(a4) -80016b3a: 8001 c.srli64 s0 +80016ae8: ffff 0xffff +80016aea: ffff 0xffff +80016aec: ffff 0xffff +80016aee: ffff 0xffff +80016af0: ffff 0xffff +80016af2: ffff 0xffff +80016af4: ffff 0xffff +80016af6: 0000 unimp +80016af8: 0001 nop +80016afa: 5341 li t1,-16 +80016afc: 00494943 fmadd.s fs2,fs2,ft4,ft0,rmm + ... +80016b18: 0000 unimp +80016b1a: 5341 li t1,-16 +80016b1c: 00494943 fmadd.s fs2,fs2,ft4,ft0,rmm + ... Disassembly of section .sdata: @@ -24173,19 +24172,19 @@ Disassembly of section .sdata: Disassembly of section .sbss: -80016b74 <_PathLocale>: +80016b74 <__malloc_max_total_mem>: 80016b74: 0000 unimp ... -80016b78 <__malloc_max_total_mem>: +80016b78 <__malloc_max_sbrked_mem>: 80016b78: 0000 unimp ... -80016b7c <__malloc_max_sbrked_mem>: +80016b7c <__malloc_top_pad>: 80016b7c: 0000 unimp ... -80016b80 <__malloc_top_pad>: +80016b80 <_PathLocale>: 80016b80: 0000 unimp ... @@ -24209,34 +24208,46 @@ Disassembly of section .bss: 80016bf4: 0000 unimp ... -80016bf8 : +80016bf8 : 80016bf8: 0000 unimp ... -80016bfc : +80016bfc : 80016bfc: 0000 unimp ... -80016c00 : +80016c00 : 80016c00: 0000 unimp ... -80016c04 : +80016c04 : 80016c04: 0000 unimp ... -80016c08 : +80016c08 : 80016c08: 0000 unimp ... -80016c0c : +80016c0c : +80016c0c: 0000 unimp ... -80016c1c : +80016c10 : +80016c10: 0000 unimp ... -80016c2c : -80016c2c: 0000 unimp +80016c14 : +80016c14: 0000 unimp + ... + +80016c18 : + ... + +80016c28 : + ... + +80016c38 : +80016c38: 0000 unimp ... Disassembly of section .comment: @@ -24266,7 +24277,7 @@ Disassembly of section .riscv.attributes: 16: 6932 flw fs2,12(sp) 18: 7032 flw ft0,44(sp) 1a: 5f30 lw a2,120(a4) - 1c: 326d jal fffff9c6 <__BSS_END__+0x7ffe8d96> + 1c: 326d jal fffff9c6 <__BSS_END__+0x7ffe8d8a> 1e: 3070 fld fa2,224(s0) ... @@ -24281,7 +24292,7 @@ Disassembly of section .debug_aranges: a: 0004 0x4 c: 0000 unimp e: 0000 unimp - 10: 0400 addi s0,sp,512 + 10: 04c4 addi s1,sp,580 12: 8001 c.srli64 s0 14: 0434 addi a3,sp,520 ... @@ -24294,7 +24305,7 @@ Disassembly of section .debug_aranges: 2a: 0004 0x4 2c: 0000 unimp 2e: 0000 unimp - 30: 0834 addi a3,sp,24 + 30: 08f8 addi a4,sp,92 32: 8001 c.srli64 s0 34: 0410 addi a2,sp,512 ... @@ -24307,7 +24318,7 @@ Disassembly of section .debug_aranges: 4a: 0004 0x4 4c: 0000 unimp 4e: 0000 unimp - 50: 0c44 addi s1,sp,532 + 50: 0d08 addi a0,sp,656 52: 8001 c.srli64 s0 54: 06e0 addi s0,sp,844 ... @@ -24320,7 +24331,7 @@ Disassembly of section .debug_aranges: 6a: 0004 0x4 6c: 0000 unimp 6e: 0000 unimp - 70: 1324 addi s1,sp,424 + 70: 13e8 addi a0,sp,492 72: 8001 c.srli64 s0 74: 05c4 addi s1,sp,708 ... @@ -24333,7 +24344,7 @@ Disassembly of section .debug_aranges: 8a: 0004 0x4 8c: 0000 unimp 8e: 0000 unimp - 90: 18e8 addi a0,sp,124 + 90: 19ac addi a1,sp,248 92: 8001 c.srli64 s0 94: 00cc addi a1,sp,68 ... @@ -24346,7 +24357,7 @@ Disassembly of section .debug_aranges: aa: 0004 0x4 ac: 0000 unimp ae: 0000 unimp - b0: 19b4 addi a3,sp,248 + b0: 1a78 addi a4,sp,316 b2: 8001 c.srli64 s0 b4: 0144 addi s1,sp,132 ... @@ -24359,7 +24370,7 @@ Disassembly of section .debug_aranges: ca: 0004 0x4 cc: 0000 unimp ce: 0000 unimp - d0: 1af8 addi a4,sp,380 + d0: 1bbc addi a5,sp,504 d2: 8001 c.srli64 s0 d4: 0144 addi s1,sp,132 ... @@ -24372,7 +24383,7 @@ Disassembly of section .debug_aranges: ea: 0004 0x4 ec: 0000 unimp ee: 0000 unimp - f0: 1c3c addi a5,sp,568 + f0: 1d00 addi s0,sp,688 f2: 8001 c.srli64 s0 f4: 1004 addi s1,sp,32 ... @@ -24385,7 +24396,7 @@ Disassembly of section .debug_aranges: 10a: 0004 0x4 10c: 0000 unimp 10e: 0000 unimp - 110: 2c40 fld fs0,152(s0) + 110: 2d04 fld fs1,24(a0) 112: 8001 c.srli64 s0 114: 1520 addi s0,sp,680 ... @@ -24398,7 +24409,7 @@ Disassembly of section .debug_aranges: 12a: 0004 0x4 12c: 0000 unimp 12e: 0000 unimp - 130: 4160 lw s0,68(a0) + 130: 4224 lw s1,64(a2) 132: 8001 c.srli64 s0 134: 0114 addi a3,sp,128 ... @@ -24411,7 +24422,7 @@ Disassembly of section .debug_aranges: 14a: 0004 0x4 14c: 0000 unimp 14e: 0000 unimp - 150: 4274 lw a3,68(a2) + 150: 4338 lw a4,64(a4) 152: 8001 c.srli64 s0 154: 0150 addi a2,sp,132 ... @@ -24424,7 +24435,7 @@ Disassembly of section .debug_aranges: 16a: 0004 0x4 16c: 0000 unimp 16e: 0000 unimp - 170: 43c4 lw s1,4(a5) + 170: 4488 lw a0,8(s1) 172: 8001 c.srli64 s0 174: 01f4 addi a3,sp,204 ... @@ -24437,7 +24448,7 @@ Disassembly of section .debug_aranges: 18a: 0004 0x4 18c: 0000 unimp 18e: 0000 unimp - 190: 45b8 lw a4,72(a1) + 190: 467c lw a5,76(a2) 192: 8001 c.srli64 s0 194: 034c addi a1,sp,388 ... @@ -24456,7 +24467,7 @@ Disassembly of section .debug_aranges: 1c2: 0004 0x4 1c4: 0000 unimp 1c6: 0000 unimp - 1c8: 4904 lw s1,16(a0) + 1c8: 49c8 lw a0,20(a1) 1ca: 8001 c.srli64 s0 1cc: 004c addi a1,sp,4 ... @@ -24470,13 +24481,13 @@ Disassembly of section .debug_info: 6: 0000 unimp 8: 0000 unimp a: 0104 addi s1,sp,128 - c: 03e6 slli t2,t2,0x19 + c: 037a slli t1,t1,0x1e e: 0000 unimp - 10: 3e0c fld fa1,56(a2) - 12: 0005 c.nop 1 - 14: 9400 0x9400 - 16: 0001 nop - 18: 0000 unimp + 10: d20c sw a1,32(a2) + 12: 0004 0x4 + 14: ed00 fsw fs0,24(a0) + 16: 0005 c.nop 1 + 18: c400 sw s0,8(s0) 1a: 0104 addi s1,sp,128 1c: 3480 fld fs0,40(s1) 1e: 0004 0x4 @@ -24484,16 +24495,16 @@ Disassembly of section .debug_info: 22: 0000 unimp 24: 0200 addi s0,sp,256 26: 0708 addi a0,sp,896 - 28: 02d8 addi a4,sp,324 + 28: 026c addi a1,sp,268 2a: 0000 unimp 2c: 0402 c.slli64 s0 - 2e: 0002e207 0x2e207 + 2e: 00027607 0x27607 32: 0300 addi s0,sp,384 34: 0504 addi s1,sp,640 36: 6e69 lui t3,0x1a 38: 0074 addi a3,sp,12 3a: 0802 c.slli64 a6 - 3c: c205 beqz a2,5c <_start-0x7fffffa4> + 3c: 5605 li a2,-31 3e: 0004 0x4 40: 0200 addi s0,sp,256 42: 0410 addi a2,sp,512 @@ -24510,26 +24521,28 @@ Disassembly of section .debug_info: 5a: 0000 unimp 5c: 0200 addi s0,sp,256 5e: 0702 c.slli64 a4 - 60: 02f8 addi a4,sp,332 + 60: 028c addi a1,sp,320 62: 0000 unimp 64: 0402 c.slli64 s0 - 66: c705 beqz a4,8e <_start-0x7fffff72> + 66: 5b05 li s6,-31 68: 0004 0x4 6a: 0200 addi s0,sp,256 6c: 0704 addi s1,sp,896 - 6e: 02dd addi t0,t0,23 + 6e: 0271 addi tp,tp,28 70: 0000 unimp - 72: 5404 lw s1,40(s0) - 74: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> + 72: e804 fsw fs1,16(s0) + 74: 0002 c.slli64 zero + 76: 0200 addi s0,sp,256 78: 015e slli sp,sp,0x17 7a: 00002c17 auipc s8,0x2 7e: 0500 addi s0,sp,640 - 80: 04f6 slli s1,s1,0x1d + 80: 048a slli s1,s1,0x2 82: 0000 unimp 84: 640e2e03 lw t3,1600(t3) # 1a640 <_start-0x7ffe59c0> 88: 0000 unimp 8a: 0500 addi s0,sp,640 - 8c: 0000063f 640e7403 0x640e74030000063f + 8c: 000005d3 fadd.s fa1,ft0,ft0,rne + 90: 640e7403 0x640e7403 94: 0000 unimp 96: 0500 addi s0,sp,640 98: 0721 addi a4,a4,8 @@ -24541,11 +24554,11 @@ Disassembly of section .debug_info: a6: 03a5 addi t2,t2,9 a8: 00c5 addi ra,ra,17 aa: 0000 unimp - ac: 00033f07 fld ft10,0(t1) # ffffa000 <__BSS_END__+0x7ffe33d0> + ac: 0002d307 0x2d307 b0: 0300 addi s0,sp,384 b2: 00720ca7 0x720ca7 b6: 0000 unimp - b8: 0002aa07 flw fs4,0(t0) + b8: 00023e07 fld ft8,0(tp) # fffe1000 <__BSS_END__+0x7ffca3c4> bc: 0300 addi s0,sp,384 be: 13a8 addi a0,sp,488 c0: 00c5 addi ra,ra,17 @@ -24562,18 +24575,18 @@ Disassembly of section .debug_info: d8: 09a2 slli s3,s3,0x8 da: 00f9 addi ra,ra,30 dc: 0000 unimp - de: 0003a50b 0x3a50b + de: 0003390b 0x3390b e2: 0300 addi s0,sp,384 e4: 07a4 addi s1,sp,968 e6: 00000033 add zero,zero,zero ea: 0b00 addi s0,sp,400 - ec: 0631 addi a2,a2,12 + ec: 05c5 addi a1,a1,17 ee: 0000 unimp f0: a305a903 lw s2,-1488(a1) f4: 0000 unimp f6: 0400 addi s0,sp,512 f8: 0500 addi s0,sp,640 - fa: 0000051b 0x51b + fa: 000004af 0x4af fe: d503aa03 lw s4,-688(t2) 102: 0000 unimp 104: 0c00 addi s0,sp,528 @@ -24584,18 +24597,18 @@ Disassembly of section .debug_info: 10e: 6b19 lui s6,0x6 110: 0000 unimp 112: 0500 addi s0,sp,640 - 114: 0526 slli a0,a0,0x9 + 114: 04ba slli s1,s1,0xe 116: 0000 unimp 118: 0c05 addi s8,s8,1 - 11a: 330d jal fffffe3c <__BSS_END__+0x7ffe920c> + 11a: 330d jal fffffe3c <__BSS_END__+0x7ffe9200> 11c: 0000 unimp 11e: 0500 addi s0,sp,640 - 120: 059c addi a5,sp,704 + 120: 0530 addi a2,sp,648 122: 0000 unimp 124: 2304 fld fs1,0(a4) 126: 0001131b 0x1131b 12a: 0d00 addi s0,sp,656 - 12c: 03de slli t2,t2,0x17 + 12c: 0372 slli t1,t1,0x1c 12e: 0000 unimp 130: 0418 addi a4,sp,512 132: 0834 addi a3,sp,24 @@ -24610,12 +24623,12 @@ Disassembly of section .debug_info: 146: 6b5f 0400 0737 0x73704006b5f 14c: 00000033 add zero,zero,zero 150: 0b04 addi s1,sp,400 - 152: 060e slli a2,a2,0x3 + 152: 05a2 slli a1,a1,0x8 154: 0000 unimp 156: 3704 fld fs1,40(a4) 158: 0000330b 0x330b 15c: 0800 addi s0,sp,16 - 15e: 00024e0b 0x24e0b + 15e: 0001e20b 0x1e20b 162: 0400 addi s0,sp,512 164: 00331437 lui s0,0x331 168: 0000 unimp @@ -24640,7 +24653,7 @@ Disassembly of section .debug_info: 196: 0000 unimp 198: 0000 unimp 19a: 0d00 addi s0,sp,656 - 19c: 028d addi t0,t0,3 + 19c: 0221 addi tp,tp,8 19e: 0000 unimp 1a0: 0424 addi s1,sp,520 1a2: 083c addi a5,sp,24 @@ -24654,7 +24667,7 @@ Disassembly of section .debug_info: 1b6: 077f 0x77f 1b8: 0000 unimp 1ba: 3f04 fld fs1,56(a4) - 1bc: 3309 jal fffffebe <__BSS_END__+0x7ffe928e> + 1bc: 3309 jal fffffebe <__BSS_END__+0x7ffe9282> 1be: 0000 unimp 1c0: 0400 addi s0,sp,512 1c2: 0001140b 0x1140b @@ -24665,17 +24678,17 @@ Disassembly of section .debug_info: 1d0: 07d2 slli a5,a5,0x14 1d2: 0000 unimp 1d4: 4104 lw s1,0(a0) - 1d6: 3309 jal fffffed8 <__BSS_END__+0x7ffe92a8> + 1d6: 3309 jal fffffed8 <__BSS_END__+0x7ffe929c> 1d8: 0000 unimp 1da: 0c00 addi s0,sp,528 - 1dc: 0004d00b 0x4d00b + 1dc: 0004640b 0x4640b 1e0: 0400 addi s0,sp,512 1e2: 0942 slli s2,s2,0x10 1e4: 00000033 add zero,zero,zero 1e8: 0b10 addi a2,sp,400 - 1ea: 0000039b 0x39b + 1ea: 0000032f 0x32f 1ee: 4304 lw s1,0(a4) - 1f0: 3309 jal fffffef2 <__BSS_END__+0x7ffe92c2> + 1f0: 3309 jal fffffef2 <__BSS_END__+0x7ffe92b6> 1f2: 0000 unimp 1f4: 1400 addi s0,sp,544 1f6: 00070a0b 0x70a0b @@ -24683,10 +24696,10 @@ Disassembly of section .debug_info: 1fc: 0944 addi s1,sp,148 1fe: 00000033 add zero,zero,zero 202: 0b18 addi a4,sp,400 - 204: 05a5 addi a1,a1,9 + 204: 0539 addi a0,a0,14 206: 0000 unimp 208: 4504 lw s1,8(a0) - 20a: 3309 jal ffffff0c <__BSS_END__+0x7ffe92dc> + 20a: 3309 jal ffffff0c <__BSS_END__+0x7ffe92d0> 20c: 0000 unimp 20e: 1c00 addi s0,sp,560 210: 0007650b 0x7650b @@ -24700,12 +24713,12 @@ Disassembly of section .debug_info: 224: 0401 addi s0,s0,0 226: 0263084f fnmadd.d fa6,ft6,ft6,ft0,rne 22a: 0000 unimp - 22c: 0002410b 0x2410b + 22c: 0001d50b 0x1d50b 230: 0400 addi s0,sp,512 232: 0a50 addi a2,sp,276 234: 00000263 beqz zero,238 <_start-0x7ffffdc8> 238: 0b00 addi s0,sp,400 - 23a: 0578 addi a4,sp,652 + 23a: 050c addi a1,sp,640 23c: 0000 unimp 23e: 5104 lw s1,32(a0) 240: 6309 lui t1,0x2 @@ -24731,7 +24744,7 @@ Disassembly of section .debug_info: 26e: 0000 unimp 270: 1f00 addi s0,sp,944 272: 1000 addi s0,sp,32 - 274: 04d9 addi s1,s1,22 + 274: 046d addi s0,s0,27 276: 0000 unimp 278: 0190 addi a2,sp,192 27a: 6204 flw fs1,0(a2) @@ -24744,15 +24757,15 @@ Disassembly of section .debug_info: 288: b612 fsd ft4,296(sp) 28a: 0002 c.slli64 zero 28c: 0000 unimp - 28e: 0005f50b 0x5f50b + 28e: 0005890b 0x5890b 292: 0400 addi s0,sp,512 294: 0664 addi s1,sp,780 296: 00000033 add zero,zero,zero 29a: 0b04 addi s1,sp,400 - 29c: 0249 addi tp,tp,18 + 29c: 01dd addi gp,gp,23 29e: 0000 unimp 2a0: 6604 flw fs1,8(a2) - 2a2: bc09 j fffffcb4 <__BSS_END__+0x7ffe9084> + 2a2: bc09 j fffffcb4 <__BSS_END__+0x7ffe9078> 2a4: 0002 c.slli64 zero 2a6: 0800 addi s0,sp,16 2a8: 0001310b 0x1310b @@ -24791,7 +24804,7 @@ Disassembly of section .debug_info: 2fc: 4f04 lw s1,24(a4) 2fe: 0000 unimp 300: 0d00 addi s0,sp,656 - 302: 05d1 addi a1,a1,20 + 302: 0565 addi a0,a0,25 304: 0000 unimp 306: 0468 addi a0,sp,524 308: 08ba slli a7,a7,0xe @@ -24818,7 +24831,7 @@ Disassembly of section .debug_info: 33a: 0056 c.slli zero,0x15 33c: 0000 unimp 33e: 0b0c addi a1,sp,400 - 340: 02b9 addi t0,t0,14 + 340: 024d addi tp,tp,19 342: 0000 unimp 344: bf04 fsd fs1,56(a4) 346: 5609 li a2,-30 @@ -24841,18 +24854,18 @@ Disassembly of section .debug_info: 36e: 0105 addi sp,sp,1 370: 0000 unimp 372: 0b1c addi a5,sp,400 - 374: 0538 addi a4,sp,648 + 374: 04cc addi a1,sp,580 376: 0000 unimp 378: ca04 sw s1,16(a2) 37a: c81d beqz s0,3b0 <_start-0x7ffffc50> 37c: 0005 c.nop 1 37e: 2000 fld fs0,0(s0) - 380: 0003940b 0x3940b + 380: 0003280b 0x3280b 384: 0400 addi s0,sp,512 386: 1dcc addi a1,sp,756 388: 000005f7 0x5f7 38c: 0b24 addi s1,sp,408 - 38e: 0639 addi a2,a2,14 + 38e: 05cd addi a1,a1,19 390: 0000 unimp 392: cf04 sw s1,24(a4) 394: 1b0d addi s6,s6,-29 @@ -24894,12 +24907,12 @@ Disassembly of section .debug_info: 3ee: 11dc addi a5,sp,228 3f0: 000002d3 fadd.s ft5,ft0,ft0,rne 3f4: 0b44 addi s1,sp,404 - 3f6: 0650 addi a2,sp,772 + 3f6: 05e4 addi s1,sp,716 3f8: 0000 unimp 3fa: df04 sw s1,56(a4) 3fc: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> 400: 4c00 lw s0,24(s0) - 402: 0003d60b 0x3d60b + 402: 00036a0b 0x36a0b 406: 0400 addi s0,sp,512 408: 0ae0 addi s0,sp,348 40a: 007f 0x7f @@ -24910,18 +24923,18 @@ Disassembly of section .debug_info: 416: 6212 flw ft4,4(sp) 418: 0004 0x4 41a: 5400 lw s0,40(s0) - 41c: 00035b0b 0x35b0b + 41c: 0002ef0b 0x2ef0b 420: 0400 addi s0,sp,512 - 422: 011f0ce7 jalr s9,17(t5) # 1a011 <_start-0x7ffe5fef> + 422: 011f0ce7 jalr s9,17(t5) # 80011 <_start-0x7ff7ffef> 426: 0000 unimp 428: 0b58 addi a4,sp,404 - 42a: 02a1 addi t0,t0,8 + 42a: 0235 addi tp,tp,13 42c: 0000 unimp 42e: e904 fsw fs1,16(a0) 430: f90e fsw ft3,176(sp) 432: 0000 unimp 434: 5c00 lw s0,56(s0) - 436: 0005af0b 0x5af0b + 436: 0005430b 0x5430b 43a: 0400 addi s0,sp,512 43c: 09ea slli s3,s3,0x1a 43e: 00000033 add zero,zero,zero @@ -24945,16 +24958,16 @@ Disassembly of section .debug_info: 468: 6215 lui tp,0x5 46a: 0004 0x4 46c: 1600 addi s0,sp,800 - 46e: 0616 slli a2,a2,0x5 + 46e: 05aa slli a1,a1,0xa 470: 0000 unimp 472: 0428 addi a0,sp,520 474: 6504 flw fs1,8(a0) 476: 0802 c.slli64 a6 478: 05b6 slli a1,a1,0xd 47a: 0000 unimp - 47c: 00059517 auipc a0,0x59 + 47c: 00052917 auipc s2,0x52 480: 0400 addi s0,sp,512 - 482: 33070267 jalr tp,816(a4) # fffe4330 <__BSS_END__+0x7ffcd700> + 482: 33070267 jalr tp,816(a4) # fffe4330 <__BSS_END__+0x7ffcd6f4> 486: 0000 unimp 488: 0000 unimp 48a: 00071a17 auipc s4,0x71 @@ -24968,13 +24981,13 @@ Disassembly of section .debug_info: 4a0: a714 fsd fa3,8(a4) 4a2: 0006 c.slli zero,0x1 4a4: 0800 addi s0,sp,16 - 4a6: 00025417 auipc s0,0x25 + 4a6: 0001e817 auipc a6,0x1e 4aa: 0400 addi s0,sp,512 4ac: 026c addi a1,sp,268 4ae: a71e fsd ft7,392(sp) 4b0: 0006 c.slli zero,0x1 4b2: 0c00 addi s0,sp,528 - 4b4: 0005f017 auipc zero,0x5f + 4b4: 00058417 auipc s0,0x58 4b8: 0400 addi s0,sp,512 4ba: 026e slli tp,tp,0x1b 4bc: 3308 fld fa0,32(a4) @@ -24982,10 +24995,10 @@ Disassembly of section .debug_info: 4c0: 1000 addi s0,sp,32 4c2: 00002a17 auipc s4,0x2 4c6: 0400 addi s0,sp,512 - 4c8: a708026f jal tp,fff80738 <__BSS_END__+0x7ff69b08> + 4c8: a708026f jal tp,fff80738 <__BSS_END__+0x7ff69afc> 4cc: 0008 0x8 4ce: 1400 addi s0,sp,544 - 4d0: 00027417 auipc s0,0x27 + 4d0: 00020817 auipc a6,0x20 4d4: 0400 addi s0,sp,512 4d6: 0272 slli tp,tp,0x1c 4d8: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> @@ -24995,17 +25008,17 @@ Disassembly of section .debug_info: 4e4: bc160273 0xbc160273 4e8: 0008 0x8 4ea: 3400 fld fs0,40(s0) - 4ec: 0004eb17 auipc s6,0x4e + 4ec: 00047f17 auipc t5,0x47 4f0: 0400 addi s0,sp,512 4f2: 0275 addi tp,tp,29 4f4: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> 4f8: 3800 fld fs0,48(s0) - 4fa: 00060417 auipc s0,0x60 + 4fa: 00059817 auipc a6,0x59 4fe: 0400 addi s0,sp,512 500: cd0a0277 0xcd0a0277 504: 0008 0x8 506: 3c00 fld fs0,56(s0) - 508: 00033717 auipc a4,0x33 + 508: 0002cb17 auipc s6,0x2c 50c: 0400 addi s0,sp,512 50e: 027a slli tp,tp,0x1e 510: 00018513 mv a0,gp @@ -25020,36 +25033,36 @@ Disassembly of section .debug_info: 52a: 027c addi a5,sp,268 52c: 00018513 mv a0,gp 530: 4800 lw s0,16(s0) - 532: 00050717 auipc a4,0x50 + 532: 00049b17 auipc s6,0x49 536: 0400 addi s0,sp,512 538: 027d addi tp,tp,31 53a: d314 sw a3,32(a4) 53c: 0008 0x8 53e: 4c00 lw s0,24(s0) - 540: 0002b117 auipc sp,0x2b + 540: 00024517 auipc a0,0x24 544: 0400 addi s0,sp,512 546: 0280 addi s0,sp,320 548: 00003307 fld ft6,0(zero) # 0 <_start-0x80000000> 54c: 5000 lw s0,32(s0) - 54e: 00020d17 auipc s10,0x20 + 54e: 0001a117 auipc sp,0x1a 552: 0400 addi s0,sp,512 554: 0281 addi t0,t0,0 556: b609 j 58 <_start-0x7fffffa8> 558: 0005 c.nop 1 55a: 5400 lw s0,40(s0) - 55c: 00058e17 auipc t3,0x58 + 55c: 00052217 auipc tp,0x52 560: 0400 addi s0,sp,512 562: 02a4 addi s1,sp,328 564: 00088207 0x88207 568: 5800 lw s0,48(s0) - 56a: d918 sw a4,48(a0) + 56a: 6d18 flw fa4,24(a0) 56c: 0004 0x4 56e: 0400 addi s0,sp,512 570: 02a8 addi a0,sp,328 572: 0002b613 sltiu a2,t0,0 576: 4800 lw s0,16(s0) 578: 1801 addi a6,a6,-32 - 57a: 0315 addi t1,t1,5 + 57a: 02a9 addi t0,t0,10 57c: 0000 unimp 57e: a904 fsd fs1,16(a0) 580: 1202 slli tp,tp,0x20 @@ -25164,12 +25177,12 @@ Disassembly of section .debug_info: 67e: a111 j a82 <_start-0x7ffff57e> 680: 0006 c.slli zero,0x1 682: 0000 unimp - 684: 0002d117 auipc sp,0x2d + 684: 00026517 auipc a0,0x26 688: 0400 addi s0,sp,512 68a: 3307012b 0x3307012b 68e: 0000 unimp 690: 0400 addi s0,sp,512 - 692: 0005b717 auipc a4,0x5b + 692: 00054b17 auipc s6,0x54 696: 0400 addi s0,sp,512 698: 012c addi a1,sp,136 69a: 0006a70b 0x6a70b @@ -25195,7 +25208,7 @@ Disassembly of section .debug_info: 6c4: 06e6 slli a3,a3,0x19 6c6: 0000 unimp 6c8: 1700 addi s0,sp,928 - 6ca: 0371 addi t1,t1,28 + 6ca: 0305 addi t1,t1,1 6cc: 0000 unimp 6ce: 4604 lw s1,8(a2) 6d0: 1201 addi tp,tp,-32 @@ -25221,7 +25234,7 @@ Disassembly of section .debug_info: 6f8: 8504 0x8504 6fa: 0702 c.slli64 a4 6fc: 0000080b 0x80b - 700: 0003ad17 auipc s10,0x3a + 700: 00034117 auipc sp,0x34 704: 0400 addi s0,sp,512 706: 2c180287 0x2c180287 70a: 0000 unimp @@ -25232,7 +25245,7 @@ Disassembly of section .debug_info: 716: b612 fsd ft4,296(sp) 718: 0005 c.nop 1 71a: 0400 addi s0,sp,512 - 71c: 00032a17 auipc s4,0x32 + 71c: 0002be17 auipc t3,0x2b 720: 0400 addi s0,sp,512 722: 0289 addi t0,t0,2 724: 0b10 addi a2,sp,400 @@ -25243,7 +25256,7 @@ Disassembly of section .debug_info: 730: 028a slli t0,t0,0x2 732: 00019b17 auipc s6,0x19 736: 2400 fld fs0,8(s0) - 738: 00025c17 auipc s8,0x25 + 738: 0001f017 auipc zero,0x1f 73c: 0400 addi s0,sp,512 73e: 330f028b 0x330f028b 742: 0000 unimp @@ -25260,7 +25273,7 @@ Disassembly of section .debug_info: 75c: ad1a fsd ft6,152(sp) 75e: 0006 c.slli zero,0x1 760: 5800 lw s0,48(s0) - 762: 0005e317 auipc t1,0x5e + 762: 00057717 auipc a4,0x57 766: 0400 addi s0,sp,512 768: 028e slli t0,t0,0x3 76a: f916 fsw ft5,176(sp) @@ -25283,7 +25296,7 @@ Disassembly of section .debug_info: 794: 1b10 addi a2,sp,432 796: 0008 0x8 798: 8000 0x8000 - 79a: 00031e17 auipc t3,0x31 + 79a: 0002b217 auipc tp,0x2b 79e: 0400 addi s0,sp,512 7a0: 0292 slli t0,t0,0x4 7a2: 2b10 fld fa2,16(a4) @@ -25291,10 +25304,10 @@ Disassembly of section .debug_info: 7a6: 8800 0x8800 7a8: 00004e17 auipc t3,0x4 7ac: 0400 addi s0,sp,512 - 7ae: 330f0293 addi t0,t5,816 + 7ae: 330f0293 addi t0,t5,816 # 4781c <_start-0x7ffb87e4> 7b2: 0000 unimp 7b4: a000 fsd fs0,0(s0) - 7b6: 00022617 auipc a2,0x22 + 7b6: 0001ba17 auipc s4,0x1b 7ba: 0400 addi s0,sp,512 7bc: 0294 addi a3,sp,320 7be: f916 fsw ft5,176(sp) @@ -25306,7 +25319,7 @@ Disassembly of section .debug_info: 7cc: f916 fsw ft5,176(sp) 7ce: 0000 unimp 7d0: ac00 fsd fs0,24(s0) - 7d2: 00021517 auipc a0,0x21 + 7d2: 0001a917 auipc s2,0x1a 7d6: 0400 addi s0,sp,512 7d8: 0296 slli t0,t0,0x5 7da: f916 fsw ft5,176(sp) @@ -25323,7 +25336,7 @@ Disassembly of section .debug_info: 7f6: f916 fsw ft5,176(sp) 7f8: 0000 unimp 7fa: c400 sw s0,8(s0) - 7fc: 00059317 auipc t1,0x59 + 7fc: 00052717 auipc a4,0x52 800: 0400 addi s0,sp,512 802: 0299 addi t0,t0,6 804: 3308 fld fa0,32(a4) @@ -25355,14 +25368,15 @@ Disassembly of section .debug_info: 83e: 029e slli t0,t0,0x7 840: 00086207 0x86207 844: 1700 addi s0,sp,928 - 846: 0345 addi t1,t1,17 + 846: 02d9 addi t0,t0,22 848: 0000 unimp 84a: a104 fsd fs1,0(a0) 84c: 1b02 slli s6,s6,0x20 84e: 0862 slli a6,a6,0x18 850: 0000 unimp 852: 1700 addi s0,sp,928 - 854: 0000026b 0x26b + 854: 01ff 0x1ff + 856: 0000 unimp 858: a204 fsd fs1,0(a2) 85a: 1802 slli a6,a6,0x20 85c: 0872 slli a6,a6,0x1c @@ -25387,8 +25401,8 @@ Disassembly of section .debug_info: 882: 8304f01b 0x8304f01b 886: 0302 c.slli64 t1 888: 000008a7 0x8a7 - 88c: 161c addi a5,sp,800 - 88e: 0006 c.slli zero,0x1 + 88c: aa1c fsd fa5,16(a2) + 88e: 0005 c.nop 1 890: 0400 addi s0,sp,512 892: 029a slli t0,t0,0x6 894: 0006f60b 0x6f60b @@ -25454,13 +25468,13 @@ Disassembly of section .debug_info: 924: 1500 addi s0,sp,672 926: 091a slli s2,s2,0x6 928: 0000 unimp - 92a: 0021 c.nop 8 - 92c: 0002 c.slli64 zero + 92a: 9421 srai s0,s0,0x28 + 92c: 0001 nop 92e: 0600 addi s0,sp,768 930: 2414 fld fa3,8(s0) 932: 0925 addi s2,s2,9 934: 0000 unimp - 936: d921 beqz a0,886 <_start-0x7ffff77a> + 936: 6d21 lui s10,0x8 938: 0005 c.nop 1 93a: 0600 addi s0,sp,768 93c: 1515 addi a0,a0,-27 @@ -25479,12 +25493,12 @@ Disassembly of section .debug_info: 95c: 0962040f 0x962040f 960: 0000 unimp 962: 2122 fld ft2,8(sp) - 964: 04e1 addi s1,s1,24 + 964: 0475 addi s0,s0,29 966: 0000 unimp 968: b60e6707 0xb60e6707 96c: 0005 c.nop 1 96e: 2100 fld fs0,0(a0) - 970: 034c addi a1,sp,388 + 970: 02e0 addi s0,sp,332 972: 0000 unimp 974: 1008 addi a0,sp,32 976: 00097b0f 0x97b0f @@ -25492,7 +25506,7 @@ Disassembly of section .debug_info: 97c: b604 fsd fs1,40(a2) 97e: 0005 c.nop 1 980: 2100 fld fs0,0(a0) - 982: 04e4 addi s1,sp,588 + 982: 0478 addi a4,sp,524 984: 0000 unimp 986: fc08 fsw fa0,56(s0) 988: b60e fsd ft3,296(sp) @@ -25515,12 +25529,11 @@ Disassembly of section .debug_info: 9ac: 331c fld fa5,32(a4) 9ae: 0000 unimp 9b0: 2100 fld fs0,0(a0) - 9b2: 0000038b 0x38b - 9b6: ff08 fsw fa0,56(a4) + 9b2: 031f 0000 ff08 0xff080000031f 9b8: 330c fld fa1,32(a4) 9ba: 0000 unimp 9bc: 2100 fld fs0,0(a0) - 9be: 0511 addi a0,a0,4 + 9be: 04a5 addi s1,s1,9 9c0: 0000 unimp 9c2: 9a09 andi a2,a2,-30 9c4: 6416 flw fs0,68(sp) @@ -25545,10 +25558,12 @@ Disassembly of section .debug_info: 9ea: 9e09 0x9e09 9ec: 0009d517 auipc a0,0x9d 9f0: 0500 addi s0,sp,640 - 9f2: 000002bf 2c162a0a 0x2c162a0a000002bf + 9f2: 00000253 fadd.s ft4,ft0,ft0,rne + 9f6: 2a0a fld fs4,128(sp) + 9f8: 2c16 fld fs8,320(sp) 9fa: 0000 unimp 9fc: 0500 addi s0,sp,640 - 9fe: 000005c7 fmsub.s fa1,ft0,ft0,ft0,rne + 9fe: 0000055b 0x55b a02: 2f0a fld ft10,128(sp) a04: 0915 addi s2,s2,5 a06: 000a c.slli zero,0x2 @@ -25579,7 +25594,7 @@ Disassembly of section .debug_info: a3c: 10be slli ra,ra,0x2f a3e: 0a1e slli s4,s4,0x7 a40: 0000 unimp - a42: 00029223 sh zero,4(t0) # f91607ea <__BSS_END__+0x79149bba> + a42: 00022623 sw zero,12(tp) # 2b7a6 <_start-0x7ffd485a> a46: 0700 addi s0,sp,896 a48: 2c04 fld fs1,24(s0) a4a: 0000 unimp @@ -25587,18 +25602,19 @@ Disassembly of section .debug_info: a4e: 0618 addi a4,sp,768 a50: 0a7f 0xa7f a52: 0000 unimp - a54: 6e24 flw fs1,88(a2) + a54: 0224 addi s1,sp,264 a56: 0005 c.nop 1 a58: 0000 unimp - a5a: 6624 flw fs1,72(a2) - a5c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> - a60: a924 fsd fs1,80(a0) + a5a: fa24 fsw fs1,112(a2) + a5c: 0002 c.slli64 zero + a5e: 0100 addi s0,sp,128 + a60: 3d24 fld fs1,120(a0) a62: 0004 0x4 a64: 0200 addi s0,sp,256 - a66: ba24 fsd fs1,112(a2) + a66: 4e24 lw s1,88(a2) a68: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - a6c: 6524 flw fs1,72(a0) - a6e: 0005 c.nop 1 + a6c: f924 fsw fs1,112(a0) + a6e: 0004 0x4 a70: 0400 addi s0,sp,512 a72: 9e24 0x9e24 a74: 05000007 0x5000007 @@ -25610,23 +25626,23 @@ Disassembly of section .debug_info: a84: 421c210b 0x421c210b a88: 000a c.slli zero,0x2 a8a: 2300 fld fs0,0(a4) - a8c: 03c5 addi t2,t2,17 + a8c: 0359 addi t1,t1,22 a8e: 0000 unimp a90: 002c0407 0x2c0407 a94: 0000 unimp a96: b006230b 0xb006230b a9a: 000a c.slli zero,0x2 a9c: 2400 fld fs0,8(s0) - a9e: 05bd addi a1,a1,15 + a9e: 0551 addi a0,a0,20 aa0: 0000 unimp aa2: 2400 fld fs0,8(s0) - aa4: 0584 addi s1,sp,704 + aa4: 0518 addi a4,sp,640 aa6: 0000 unimp aa8: 2401 jal ca8 <_start-0x7ffff358> aaa: 000006a7 0x6a7 aae: 0002 c.slli64 zero - ab0: 3421 jal 4b8 <_start-0x7ffffb48> - ab2: 0002 c.slli64 zero + ab0: c821 beqz s0,b00 <_start-0x7ffff500> + ab2: 0001 nop ab4: 0b00 addi s0,sp,400 ab6: 1e28 addi a0,sp,824 ab8: 00000a8b 0xa8b @@ -25640,8 +25656,8 @@ Disassembly of section .debug_info: ace: 5924 lw s1,112(a0) ad0: 0006 c.slli zero,0x1 ad2: 0000 unimp - ad4: 4724 lw s1,72(a4) - ad6: 0006 c.slli zero,0x1 + ad4: db24 sw s1,112(a4) + ad6: 0005 c.nop 1 ad8: 0100 addi s0,sp,128 ada: 2100 fld fs0,0(a0) adc: 017c addi a5,sp,140 @@ -25649,7 +25665,7 @@ Disassembly of section .debug_info: ae0: bc2a2f0b 0xbc2a2f0b ae4: 000a c.slli zero,0x2 ae6: 2100 fld fs0,0(a0) - ae8: 037c addi a5,sp,396 + ae8: 0310 addi a2,sp,384 aea: 0000 unimp aec: 290c fld fa1,16(a0) aee: 251a fld fa0,384(sp) @@ -25692,11 +25708,11 @@ Disassembly of section .debug_info: b3c: 0025 c.nop 9 b3e: 0000 unimp b40: 0402 c.slli64 s0 - b42: bc04 fsd fs1,56(s0) + b42: 5004 lw s1,32(s0) b44: 0004 0x4 b46: 0200 addi s0,sp,256 b48: 0308 addi a0,sp,384 - b4a: 04b4 addi a3,sp,584 + b4a: 0448 addi a0,sp,516 b4c: 0000 unimp b4e: 0802 c.slli64 a6 b50: c504 sw s1,8(a0) @@ -25706,7 +25722,7 @@ Disassembly of section .debug_info: b58: 0000003f b8032002 0xb80320020000003f b60: 0000 unimp b62: 1900 addi s0,sp,176 - b64: 000002ef jal t0,b64 <_start-0x7ffff49c> + b64: 00000283 lb t0,0(zero) # 0 <_start-0x80000000> b68: 0d08 addi a0,sp,656 b6a: 01ed addi gp,gp,27 b6c: 8e0a mv t3,sp @@ -25736,7 +25752,7 @@ Disassembly of section .debug_info: ba6: 0d00 addi s0,sp,656 ba8: 280a01f7 0x280a01f7 bac: 0000000b 0xb - bb0: c904 sw s1,16(a0) + bb0: 5d04 lw s1,56(a0) bb2: 0002 c.slli64 zero bb4: 0d00 addi s0,sp,656 bb6: 01f8 addi a4,sp,204 @@ -25758,17 +25774,17 @@ Disassembly of section .debug_info: bde: 1601 addi a2,a2,-32 be0: 0bd2 slli s7,s7,0x14 be2: 0000 unimp - be4: 0b1f 0003 0d00 0xd0000030b1f + be4: 9f1f 0002 0d00 0xd0000029f1f bea: 0202 c.slli64 tp bec: d216 sw t0,36(sp) bee: 2700000b 0x2700000b - bf2: 05fa slli a1,a1,0x1e + bf2: 058e slli a1,a1,0x3 bf4: 0000 unimp bf6: 2601 jal ef6 <_start-0x7ffff10a> bf8: 0105 addi sp,sp,1 bfa: 0b34 addi a3,sp,408 bfc: 0000 unimp - bfe: 0400 addi s0,sp,512 + bfe: 04c4 addi s1,sp,580 c00: 8001 c.srli64 s0 c02: 0434 addi a3,sp,520 c04: 0000 unimp @@ -25791,7 +25807,7 @@ Disassembly of section .debug_info: c28: 0000 unimp c2a: cd29 beqz a0,c84 <_start-0x7ffff37c> c2c: 000e c.slli zero,0x3 - c2e: 0400 addi s0,sp,512 + c2e: c800 sw s0,16(s0) c30: 0104 addi s1,sp,128 c32: 0080 addi s0,sp,64 c34: 0000 unimp @@ -25869,8 +25885,8 @@ Disassembly of section .debug_info: cdc: 0005 c.nop 1 cde: 0000 unimp ce0: 000fbc2f 0xfbc2f - ce4: 6800 flw fs0,16(s0) - ce6: 0104 addi s1,sp,128 + ce4: 2c00 fld fs0,24(s0) + ce6: 0105 addi sp,sp,1 ce8: 8880 0x8880 cea: 0000 unimp cec: 3100 fld fs0,32(a0) @@ -26009,8 +26025,8 @@ Disassembly of section .debug_info: e0c: 0009 c.nop 2 e0e: 0000 unimp e10: 00109e2f 0x109e2f - e14: 5000 lw s0,32(s0) - e16: 0105 addi sp,sp,1 + e14: 1400 addi s0,sp,544 + e16: 0106 slli sp,sp,0x1 e18: 8880 0x8880 e1a: 0000 unimp e1c: 6100 flw fs0,0(a0) @@ -26094,7 +26110,7 @@ Disassembly of section .debug_info: ece: 0661 addi a2,a2,24 ed0: 0000 unimp ed2: f701 bnez a4,dda <_start-0x7ffff226> - ed4: 0b340103 lb sp,179(s0) # fffe10b3 <__BSS_END__+0x7ffca483> + ed4: 0b340103 lb sp,179(s0) # fffe10b3 <__BSS_END__+0x7ffca477> ed8: 0000 unimp eda: 00123e03 0x123e03 ede: 3200 fld fs0,32(a2) @@ -26392,47 +26408,47 @@ Disassembly of section .debug_info: 11ac: 1a34 addi a3,sp,312 11ae: 0012 c.slli zero,0x4 11b0: 3500 fld fs0,40(a0) - 11b2: 061d addi a2,a2,7 + 11b2: 05b1 addi a1,a1,12 11b4: 0000 unimp 11b6: b101 j db6 <_start-0x7ffff24a> 11b8: 0804 addi s1,sp,16 11ba: 0b1c addi a5,sp,400 11bc: 0000 unimp - 11be: 2235 jal 12ea <_start-0x7fffed16> - 11c0: 0006 c.slli zero,0x1 + 11be: b635 j cea <_start-0x7ffff316> + 11c0: 0005 c.nop 1 11c2: 0100 addi s0,sp,128 11c4: 04b1 addi s1,s1,12 11c6: 1c08 addi a0,sp,560 11c8: 3500000b 0x3500000b - 11cc: 00000627 0x627 + 11cc: 000005bb 0x5bb 11d0: b101 j dd0 <_start-0x7ffff230> 11d2: 0804 addi s1,sp,16 11d4: 0b1c addi a5,sp,400 11d6: 0000 unimp - 11d8: 2c35 jal 1414 <_start-0x7fffebec> - 11da: 0006 c.slli zero,0x1 + 11d8: c035 beqz s0,123c <_start-0x7fffedc4> + 11da: 0005 c.nop 1 11dc: 0100 addi s0,sp,128 11de: 04b1 addi s1,s1,12 11e0: 1c08 addi a0,sp,560 11e2: 3500000b 0x3500000b - 11e6: 00000377 0x377 + 11e6: 0000030b 0x30b 11ea: b101 j dea <_start-0x7ffff216> 11ec: 0804 addi s1,sp,16 11ee: 0b1c addi a5,sp,400 11f0: 0000 unimp - 11f2: 0235 addi tp,tp,13 - 11f4: 0005 c.nop 1 + 11f2: 9635 srai a2,a2,0x2d + 11f4: 0004 0x4 11f6: 0100 addi s0,sp,128 11f8: 04b1 addi s1,s1,12 11fa: 1c08 addi a0,sp,560 11fc: 3500000b 0x3500000b - 1200: 0361 addi t1,t1,24 + 1200: 02f5 addi t0,t0,29 1202: 0000 unimp 1204: b101 j e04 <_start-0x7ffff1fc> 1206: 0804 addi s1,sp,16 1208: 0b1c addi a5,sp,400 120a: 0000 unimp - 120c: fd35 bnez a0,1188 <_start-0x7fffee78> + 120c: 9135 srli a0,a0,0x2d 120e: 0004 0x4 1210: 0100 addi s0,sp,128 1212: 04b1 addi s1,s1,12 @@ -26460,28 +26476,29 @@ Disassembly of section .debug_info: 124a: cc00 sw s0,24(s0) 124c: 0002 c.slli64 zero 124e: 0400 addi s0,sp,512 - 1250: e601 bnez a2,1258 <_start-0x7fffeda8> + 1250: 7a01 lui s4,0xfffe0 1252: 0c000003 lb zero,192(zero) # c0 <_start-0x7fffff40> - 1256: 053e slli a0,a0,0xf + 1256: 04d2 slli s1,s1,0x14 1258: 0000 unimp - 125a: 0194 addi a3,sp,192 + 125a: 05ed addi a1,a1,27 125c: 0000 unimp - 125e: 0834 addi a3,sp,24 + 125e: 08f8 addi a4,sp,92 1260: 8001 c.srli64 s0 1262: 0410 addi a2,sp,512 1264: 0000 unimp - 1266: 0000092f 0x92f + 1266: 0905 addi s2,s2,1 + 1268: 0000 unimp 126a: 0802 c.slli64 a6 - 126c: 0002d807 0x2d807 + 126c: 00026c07 0x26c07 1270: 0300 addi s0,sp,384 1272: 0504 addi s1,sp,640 1274: 6e69 lui t3,0x1a 1276: 0074 addi a3,sp,12 1278: 0402 c.slli64 s0 - 127a: 0002e207 0x2e207 + 127a: 00027607 0x27607 127e: 0200 addi s0,sp,256 1280: 0508 addi a0,sp,640 - 1282: 04c2 slli s1,s1,0x10 + 1282: 0456 slli s0,s0,0x15 1284: 0000 unimp 1286: 1002 c.slli zero,0x20 1288: c004 sw s1,0(s0) @@ -26498,26 +26515,26 @@ Disassembly of section .debug_info: 129e: 0000 unimp 12a0: 0000 unimp 12a2: 0202 c.slli64 tp - 12a4: 0002f807 0x2f807 + 12a4: 00028c07 0x28c07 12a8: 0200 addi s0,sp,256 12aa: 0504 addi s1,sp,640 - 12ac: 000004c7 fmsub.s fs1,ft0,ft0,ft0,rne + 12ac: 0000045b 0x45b 12b0: 0402 c.slli64 s0 - 12b2: 0002dd07 0x2dd07 + 12b2: 00027107 0x27107 12b6: 0400 addi s0,sp,512 - 12b8: 0354 addi a3,sp,388 + 12b8: 02e8 addi a0,sp,332 12ba: 0000 unimp 12bc: 5e02 lw t3,32(sp) 12be: 1701 addi a4,a4,-32 12c0: 00000033 add zero,zero,zero - 12c4: f605 bnez a2,11ec <_start-0x7fffee14> + 12c4: 8a05 andi a2,a2,1 12c6: 0004 0x4 12c8: 0300 addi s0,sp,384 12ca: 0e2e slli t3,t3,0xb 12cc: 0064 addi s1,sp,12 12ce: 0000 unimp - 12d0: 3f05 jal 1200 <_start-0x7fffee00> - 12d2: 0006 c.slli zero,0x1 + 12d0: d305 beqz a4,11f0 <_start-0x7fffee10> + 12d2: 0005 c.nop 1 12d4: 0300 addi s0,sp,384 12d6: 0e74 addi a3,sp,796 12d8: 0064 addi s1,sp,12 @@ -26530,10 +26547,11 @@ Disassembly of section .debug_info: 12ea: c503a503 lw a0,-944(t2) 12ee: 0000 unimp 12f0: 0700 addi s0,sp,896 - 12f2: 0000033f 720ca703 0x720ca7030000033f + 12f2: 000002d3 fadd.s ft5,ft0,ft0,rne + 12f6: 720ca703 lw a4,1824(s9) 12fa: 0000 unimp 12fc: 0700 addi s0,sp,896 - 12fe: 02aa slli t0,t0,0xa + 12fe: 023e slli tp,tp,0xf 1300: 0000 unimp 1302: c513a803 lw a6,-943(t2) 1306: 0000 unimp @@ -26544,22 +26562,22 @@ Disassembly of section .debug_info: 1310: 0000 unimp 1312: 0900 addi s0,sp,144 1314: 00000033 add zero,zero,zero - 1318: 080a0003 lb zero,128(s4) # 7280c <_start-0x7ff8d7f4> - 131c: f909a203 lw tp,-112(s3) # ffffff90 <__BSS_END__+0x7ffe9360> + 1318: 080a0003 lb zero,128(s4) # fffe0080 <__BSS_END__+0x7ffc9444> + 131c: f909a203 lw tp,-112(s3) # ffffff90 <__BSS_END__+0x7ffe9354> 1320: 0000 unimp 1322: 0b00 addi s0,sp,400 - 1324: 03a5 addi t2,t2,9 + 1324: 0339 addi t1,t1,14 1326: 0000 unimp 1328: 2c07a403 lw s0,704(a5) # c66 <_start-0x7ffff39a> 132c: 0000 unimp 132e: 0000 unimp - 1330: 0006310b 0x6310b + 1330: 0005c50b 0x5c50b 1334: 0300 addi s0,sp,384 1336: 05a9 addi a1,a1,10 1338: 000000a3 sb zero,1(zero) # 1 <_start-0x7fffffff> 133c: 0004 0x4 - 133e: 1b05 addi s6,s6,-31 - 1340: 0005 c.nop 1 + 133e: af05 j 1a6e <_start-0x7fffe592> + 1340: 0004 0x4 1342: 0300 addi s0,sp,384 1344: 03aa slli t2,t2,0xa 1346: 00d5 addi ra,ra,21 @@ -26570,18 +26588,18 @@ Disassembly of section .debug_info: 1350: 0400 addi s0,sp,512 1352: 1916 slli s2,s2,0x25 1354: 0000006b 0x6b - 1358: 2605 jal 1678 <_start-0x7fffe988> - 135a: 0005 c.nop 1 + 1358: ba05 j c88 <_start-0x7ffff378> + 135a: 0004 0x4 135c: 0500 addi s0,sp,640 135e: 0d0c addi a1,sp,656 1360: 002c addi a1,sp,8 1362: 0000 unimp - 1364: 9c05 0x9c05 + 1364: 3005 jal b84 <_start-0x7ffff47c> 1366: 0005 c.nop 1 1368: 0400 addi s0,sp,512 - 136a: 01131b23 sh a7,22(t1) # 59812 <_start-0x7ffa67ee> + 136a: 01131b23 sh a7,22(t1) # 2016 <_start-0x7fffdfea> 136e: 0000 unimp - 1370: de0d beqz a2,12aa <_start-0x7fffed56> + 1370: 720d lui tp,0xfffe3 1372: 18000003 lb zero,384(zero) # 180 <_start-0x7ffffe80> 1376: 3404 fld fs1,40(s0) 1378: 8508 0x8508 @@ -26596,12 +26614,12 @@ Disassembly of section .debug_info: 138c: 3704006b 0x3704006b 1390: 00002c07 flw fs8,0(zero) # 0 <_start-0x80000000> 1394: 0400 addi s0,sp,512 - 1396: 00060e0b 0x60e0b + 1396: 0005a20b 0x5a20b 139a: 0400 addi s0,sp,512 139c: 002c0b37 lui s6,0x2c0 13a0: 0000 unimp 13a2: 0b08 addi a0,sp,400 - 13a4: 024e slli tp,tp,0x13 + 13a4: 01e2 slli gp,gp,0x18 13a6: 0000 unimp 13a8: 3704 fld fs1,40(a4) 13aa: 2c14 fld fa3,24(s0) @@ -26624,7 +26642,7 @@ Disassembly of section .debug_info: 13d8: 0900 addi s0,sp,144 13da: 00000033 add zero,zero,zero 13de: 0000 unimp - 13e0: 8d0d sub a0,a0,a1 + 13e0: 210d jal 1802 <_start-0x7fffe7fe> 13e2: 0002 c.slli64 zero 13e4: 2400 fld fs0,8(s0) 13e6: 3c04 fld fs1,56(s0) @@ -26652,13 +26670,13 @@ Disassembly of section .debug_info: 141c: 002c addi a1,sp,8 141e: 0000 unimp 1420: 0b0c addi a1,sp,400 - 1422: 04d0 addi a2,sp,580 + 1422: 0464 addi s1,sp,524 1424: 0000 unimp 1426: 4204 lw s1,0(a2) 1428: 2c09 jal 163a <_start-0x7fffe9c6> 142a: 0000 unimp 142c: 1000 addi s0,sp,32 - 142e: 00039b0b 0x39b0b + 142e: 00032f0b 0x32f0b 1432: 0400 addi s0,sp,512 1434: 002c0943 fmadd.s fs2,fs8,ft2,ft0,rne 1438: 0000 unimp @@ -26669,7 +26687,7 @@ Disassembly of section .debug_info: 1442: 2c09 jal 1654 <_start-0x7fffe9ac> 1444: 0000 unimp 1446: 1800 addi s0,sp,48 - 1448: 0005a50b 0x5a50b + 1448: 0005390b 0x5390b 144c: 0400 addi s0,sp,512 144e: 0945 addi s2,s2,17 1450: 002c addi a1,sp,8 @@ -26689,13 +26707,13 @@ Disassembly of section .debug_info: 146c: 6308 flw fa0,0(a4) 146e: 0002 c.slli64 zero 1470: 0b00 addi s0,sp,400 - 1472: 0241 addi tp,tp,16 + 1472: 01d5 addi gp,gp,21 1474: 0000 unimp 1476: 5004 lw s1,32(s0) 1478: 630a flw ft6,128(sp) 147a: 0002 c.slli64 zero 147c: 0000 unimp - 147e: 0005780b 0x5780b + 147e: 00050c0b 0x50c0b 1482: 0400 addi s0,sp,512 1484: 0951 addi s2,s2,20 1486: 00000263 beqz zero,148a <_start-0x7fffeb76> @@ -26720,7 +26738,7 @@ Disassembly of section .debug_info: 14ae: 0002 c.slli64 zero 14b0: 0900 addi s0,sp,144 14b2: 00000033 add zero,zero,zero - 14b6: 001f d910 0004 0x4d910001f + 14b6: 001f 6d10 0004 0x46d10001f 14bc: 9000 0x9000 14be: 0401 addi s0,s0,0 14c0: 0862 slli a6,a6,0x18 @@ -26731,13 +26749,13 @@ Disassembly of section .debug_info: 14cc: 02b61263 bne a2,a1,14f0 <_start-0x7fffeb10> 14d0: 0000 unimp 14d2: 0b00 addi s0,sp,400 - 14d4: 05f5 addi a1,a1,29 + 14d4: 0589 addi a1,a1,2 14d6: 0000 unimp 14d8: 6404 flw fs1,8(s0) 14da: 2c06 fld fs8,64(sp) 14dc: 0000 unimp 14de: 0400 addi s0,sp,512 - 14e0: 0002490b 0x2490b + 14e0: 0001dd0b 0x1dd0b 14e4: 0400 addi s0,sp,512 14e6: 0966 slli s2,s2,0x19 14e8: 02bc addi a5,sp,328 @@ -26784,7 +26802,7 @@ Disassembly of section .debug_info: 153e: 0004 0x4 1540: 004f040f 0x4f040f 1544: 0000 unimp - 1546: d10d beqz a0,1468 <_start-0x7fffeb98> + 1546: 650d lui a0,0x3 1548: 0005 c.nop 1 154a: 6800 flw fs0,16(s0) 154c: ba04 fsd fs1,48(a2) @@ -26807,7 +26825,7 @@ Disassembly of section .debug_info: 157e: 5609 li a2,-30 1580: 0000 unimp 1582: 0c00 addi s0,sp,528 - 1584: 0002b90b 0x2b90b + 1584: 00024d0b 0x24d0b 1588: 0400 addi s0,sp,512 158a: 005609bf 0e0e0000 0xe0e0000005609bf 1592: 625f 0066 c004 0xc0040066625f @@ -26823,19 +26841,19 @@ Disassembly of section .debug_info: 15ac: 0000013f 050ac804 0x50ac8040000013f 15b4: 0001 nop 15b6: 1c00 addi s0,sp,560 - 15b8: 0005380b 0x5380b + 15b8: 0004cc0b 0x4cc0b 15bc: 0400 addi s0,sp,512 15be: 1dca slli s11,s11,0x32 15c0: 05c8 addi a0,sp,708 15c2: 0000 unimp 15c4: 0b20 addi s0,sp,408 - 15c6: 0394 addi a3,sp,448 + 15c6: 0328 addi a0,sp,392 15c8: 0000 unimp 15ca: cc04 sw s1,24(s0) 15cc: f71d bnez a4,14fa <_start-0x7fffeb06> 15ce: 0005 c.nop 1 15d0: 2400 fld fs0,8(s0) - 15d2: 0006390b 0x6390b + 15d2: 0005cd0b 0x5cd0b 15d6: 0400 addi s0,sp,512 15d8: 061b0dcf fnmadd.q fs11,fs6,ft1,ft0,rne 15dc: 0000 unimp @@ -26879,11 +26897,11 @@ Disassembly of section .debug_info: 1634: d311 beqz a4,1538 <_start-0x7fffeac8> 1636: 0002 c.slli64 zero 1638: 4400 lw s0,8(s0) - 163a: 0006500b 0x6500b + 163a: 0005e40b 0x5e40b 163e: 0400 addi s0,sp,512 1640: 07df 002c 0000 0x2c07df 1646: 0b4c addi a1,sp,404 - 1648: 03d6 slli t2,t2,0x15 + 1648: 036a slli t1,t1,0x1a 164a: 0000 unimp 164c: e004 fsw fs1,0(s0) 164e: 7f0a flw ft10,160(sp) @@ -26894,18 +26912,18 @@ Disassembly of section .debug_info: 165a: 046212e3 bne tp,t1,1e9e <_start-0x7fffe162> 165e: 0000 unimp 1660: 0b54 addi a3,sp,404 - 1662: 0000035b 0x35b + 1662: 000002ef jal t0,1662 <_start-0x7fffe99e> 1666: e704 fsw fs1,8(a4) 1668: 1f0c addi a1,sp,944 166a: 0001 nop 166c: 5800 lw s0,48(s0) - 166e: 0002a10b 0x2a10b + 166e: 0002350b 0x2350b 1672: 0400 addi s0,sp,512 1674: 0ee9 addi t4,t4,26 1676: 00f9 addi ra,ra,30 1678: 0000 unimp 167a: 0b5c addi a5,sp,404 - 167c: 000005af 0x5af + 167c: 00000543 fmadd.s fa0,ft0,ft0,ft0,rne 1680: ea04 fsw fs1,16(a2) 1682: 2c09 jal 1894 <_start-0x7fffe76c> 1684: 0000 unimp @@ -26930,15 +26948,15 @@ Disassembly of section .debug_info: 16ac: 1500 addi s0,sp,672 16ae: 0462 slli s0,s0,0x18 16b0: 0000 unimp - 16b2: 1616 slli a2,a2,0x25 - 16b4: 0006 c.slli zero,0x1 + 16b2: aa16 fsd ft5,272(sp) + 16b4: 0005 c.nop 1 16b6: 2800 fld fs0,16(s0) 16b8: 0404 addi s1,sp,512 16ba: 0265 addi tp,tp,25 16bc: b608 fsd fa0,40(a2) 16be: 0005 c.nop 1 16c0: 1700 addi s0,sp,928 - 16c2: 0595 addi a1,a1,5 + 16c2: 0529 addi a0,a0,10 16c4: 0000 unimp 16c6: 6704 flw fs1,8(a4) 16c8: 0702 c.slli64 a4 @@ -26957,13 +26975,13 @@ Disassembly of section .debug_info: 16e4: 1402 slli s0,s0,0x20 16e6: 000006a7 0x6a7 16ea: 1708 addi a0,sp,928 - 16ec: 0254 addi a3,sp,260 + 16ec: 01e8 addi a0,sp,204 16ee: 0000 unimp 16f0: 6c04 flw fs1,24(s0) 16f2: 1e02 slli t3,t3,0x20 16f4: 000006a7 0x6a7 16f8: 170c addi a1,sp,928 - 16fa: 05f0 addi a2,sp,716 + 16fa: 0584 addi s1,sp,704 16fc: 0000 unimp 16fe: 6e04 flw fs1,24(a2) 1700: 0802 c.slli64 a6 @@ -26976,7 +26994,7 @@ Disassembly of section .debug_info: 170e: 0802 c.slli64 a6 1710: 000008a7 0x8a7 1714: 1714 addi a3,sp,928 - 1716: 0274 addi a3,sp,268 + 1716: 0208 addi a0,sp,256 1718: 0000 unimp 171a: 7204 flw fs1,32(a2) 171c: 0702 c.slli64 a4 @@ -26989,20 +27007,21 @@ Disassembly of section .debug_info: 172c: 08bc addi a5,sp,88 172e: 0000 unimp 1730: 1734 addi a3,sp,936 - 1732: 000004eb 0x4eb + 1732: 047f 0x47f + 1734: 0000 unimp 1736: 7504 flw fs1,40(a0) 1738: 0702 c.slli64 a4 173a: 002c addi a1,sp,8 173c: 0000 unimp 173e: 1738 addi a4,sp,936 - 1740: 0604 addi s1,sp,768 + 1740: 0598 addi a4,sp,704 1742: 0000 unimp 1744: 7704 flw fs1,40(a4) 1746: 0a02 c.slli64 s4 1748: 08cd addi a7,a7,19 174a: 0000 unimp 174c: 173c addi a5,sp,936 - 174e: 00000337 lui t1,0x0 + 174e: 000002cb fnmsub.s ft5,ft0,ft0,ft0,rne 1752: 7a04 flw fs1,48(a2) 1754: 1302 slli t1,t1,0x20 1756: 0185 addi gp,gp,1 @@ -27022,41 +27041,42 @@ Disassembly of section .debug_info: 1772: 0185 addi gp,gp,1 1774: 0000 unimp 1776: 1748 addi a0,sp,932 - 1778: 00000507 0x507 + 1778: 0000049b 0x49b 177c: 7d04 flw fs1,56(a0) 177e: 1402 slli s0,s0,0x20 1780: 000008d3 fadd.s fa7,ft0,ft0,rne 1784: 174c addi a1,sp,932 - 1786: 02b1 addi t0,t0,12 + 1786: 0245 addi tp,tp,17 1788: 0000 unimp 178a: 8004 0x8004 178c: 0702 c.slli64 a4 178e: 002c addi a1,sp,8 1790: 0000 unimp 1792: 1750 addi a2,sp,932 - 1794: 020d addi tp,tp,3 + 1794: 01a1 addi gp,gp,8 1796: 0000 unimp 1798: 8104 0x8104 179a: 0902 c.slli64 s2 179c: 05b6 slli a1,a1,0xd 179e: 0000 unimp 17a0: 1754 addi a3,sp,932 - 17a2: 058e slli a1,a1,0x3 + 17a2: 0522 slli a0,a0,0x8 17a4: 0000 unimp 17a6: a404 fsd fs1,8(s0) 17a8: 0702 c.slli64 a4 17aa: 0882 c.slli64 a7 17ac: 0000 unimp 17ae: 1858 addi a4,sp,52 - 17b0: 04d9 addi s1,s1,22 + 17b0: 046d addi s0,s0,27 17b2: 0000 unimp 17b4: a804 fsd fs1,16(s0) 17b6: 1302 slli t1,t1,0x20 17b8: 02b6 slli t0,t0,0xd 17ba: 0000 unimp 17bc: 0148 addi a0,sp,132 - 17be: 1518 addi a4,sp,672 - 17c0: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> + 17be: a918 fsd fa4,16(a0) + 17c0: 0002 c.slli64 zero + 17c2: 0400 addi s0,sp,512 17c4: 02a9 addi t0,t0,10 17c6: 7312 flw ft6,36(sp) 17c8: 0002 c.slli64 zero @@ -27178,14 +27198,14 @@ Disassembly of section .debug_info: 18c4: 06a1 addi a3,a3,8 18c6: 0000 unimp 18c8: 1700 addi s0,sp,928 - 18ca: 02d1 addi t0,t0,20 + 18ca: 0265 addi tp,tp,25 18cc: 0000 unimp 18ce: 2b04 fld fs1,16(a4) 18d0: 0701 addi a4,a4,0 18d2: 002c addi a1,sp,8 18d4: 0000 unimp 18d6: 1704 addi s1,sp,928 - 18d8: 000005b7 lui a1,0x0 + 18d8: 0000054b fnmsub.s fa0,ft0,ft0,ft0,rne 18dc: 2c04 fld fs1,24(s0) 18de: 0b01 addi s6,s6,0 18e0: 000006a7 0x6a7 @@ -27207,7 +27227,7 @@ Disassembly of section .debug_info: 1908: e612 fsw ft4,12(sp) 190a: 0006 c.slli zero,0x1 190c: 0000 unimp - 190e: 00037117 auipc sp,0x37 + 190e: 00030517 auipc a0,0x30 1912: 0400 addi s0,sp,512 1914: 0146 slli sp,sp,0x11 1916: e612 fsw ft4,12(sp) @@ -27231,7 +27251,7 @@ Disassembly of section .debug_info: 193e: 0285 addi t0,t0,1 1940: 00080b07 0x80b07 1944: 1700 addi s0,sp,928 - 1946: 03ad addi t2,t2,11 + 1946: 0341 addi t1,t1,16 1948: 0000 unimp 194a: 8704 0x8704 194c: 1802 slli a6,a6,0x20 @@ -27244,7 +27264,7 @@ Disassembly of section .debug_info: 195c: 05b6 slli a1,a1,0xd 195e: 0000 unimp 1960: 1704 addi s1,sp,928 - 1962: 032a slli t1,t1,0xa + 1962: 02be slli t0,t0,0xf 1964: 0000 unimp 1966: 8904 0x8904 1968: 1002 c.slli zero,0x20 @@ -27256,7 +27276,7 @@ Disassembly of section .debug_info: 1976: 1702 slli a4,a4,0x20 1978: 0000019b 0x19b 197c: 1724 addi s1,sp,936 - 197e: 025c addi a5,sp,260 + 197e: 01f0 addi a2,sp,204 1980: 0000 unimp 1982: 8b04 0x8b04 1984: 0f02 c.slli64 t5 @@ -27277,7 +27297,7 @@ Disassembly of section .debug_info: 19a2: 06ad addi a3,a3,11 19a4: 0000 unimp 19a6: 1758 addi a4,sp,932 - 19a8: 000005e3 beqz zero,21b2 <_start-0x7fffde4e> + 19a8: 00000577 0x577 19ac: 8e04 0x8e04 19ae: 1602 slli a2,a2,0x20 19b0: 00f9 addi ra,ra,30 @@ -27303,7 +27323,7 @@ Disassembly of section .debug_info: 19d8: 1002 c.slli zero,0x20 19da: 0000081b 0x81b 19de: 1780 addi s0,sp,992 - 19e0: 031e slli t1,t1,0x7 + 19e0: 02b2 slli t0,t0,0xc 19e2: 0000 unimp 19e4: 9204 0x9204 19e6: 1002 c.slli zero,0x20 @@ -27316,7 +27336,7 @@ Disassembly of section .debug_info: 19f6: 002c addi a1,sp,8 19f8: 0000 unimp 19fa: 17a0 addi s0,sp,1000 - 19fc: 0226 slli tp,tp,0x9 + 19fc: 01ba slli gp,gp,0xe 19fe: 0000 unimp 1a00: 9404 0x9404 1a02: 1602 slli a2,a2,0x20 @@ -27330,7 +27350,7 @@ Disassembly of section .debug_info: 1a12: 00f9 addi ra,ra,30 1a14: 0000 unimp 1a16: 17ac addi a1,sp,1000 - 1a18: 0215 addi tp,tp,5 + 1a18: 01a9 addi gp,gp,10 1a1a: 0000 unimp 1a1c: 9604 0x9604 1a1e: 1602 slli a2,a2,0x20 @@ -27351,7 +27371,7 @@ Disassembly of section .debug_info: 1a3c: 00f9 addi ra,ra,30 1a3e: 0000 unimp 1a40: 17c4 addi s1,sp,996 - 1a42: 00000593 li a1,0 + 1a42: 00000527 0x527 1a46: 9904 0x9904 1a48: 0802 c.slli64 a6 1a4a: 002c addi a1,sp,8 @@ -27381,12 +27401,12 @@ Disassembly of section .debug_info: 1a84: 0702 c.slli64 a4 1a86: 0862 slli a6,a6,0x18 1a88: 0000 unimp - 1a8a: 00034517 auipc a0,0x34 + 1a8a: 0002d917 auipc s2,0x2d 1a8e: 0400 addi s0,sp,512 1a90: 02a1 addi t0,t0,8 1a92: 0008621b 0x8621b 1a96: 0000 unimp - 1a98: 00026b17 auipc s6,0x26 + 1a98: 0001ff17 auipc t5,0x1f 1a9c: 0400 addi s0,sp,512 1a9e: 02a2 slli t0,t0,0x8 1aa0: 7218 flw fa4,32(a2) @@ -27408,10 +27428,10 @@ Disassembly of section .debug_info: 1ac4: 1d00 addi s0,sp,688 1ac6: 1b00 addi s0,sp,432 1ac8: 04f0 addi a2,sp,588 - 1aca: a7030283 lb t0,-1424(t1) # fffffa70 <__BSS_END__+0x7ffe8e40> + 1aca: a7030283 lb t0,-1424(t1) 1ace: 0008 0x8 1ad0: 1c00 addi s0,sp,560 - 1ad2: 0616 slli a2,a2,0x5 + 1ad2: 05aa slli a1,a1,0xa 1ad4: 0000 unimp 1ad6: 9a04 0x9a04 1ad8: 0b02 c.slli64 s6 @@ -27419,7 +27439,7 @@ Disassembly of section .debug_info: 1adc: 0000 unimp 1ade: 531c lw a5,32(a4) 1ae0: 04000007 0x4000007 - 1ae4: 3b0b02a3 sb a6,933(s6) # 27e3d <_start-0x7ffd81c3> + 1ae4: 3b0b02a3 sb a6,933(s6) # 2c13a5 <_start-0x7fd3ec5b> 1ae8: 0008 0x8 1aea: 0000 unimp 1aec: bc08 fsd fa0,56(s0) @@ -27466,7 +27486,7 @@ Disassembly of section .debug_info: 1b46: 06ee slli a3,a3,0x1b 1b48: 0000 unimp 1b4a: 3304 fld fs1,32(a4) - 1b4c: 04621703 lh a4,70(tp) # ffffd046 <__BSS_END__+0x7ffe6416> + 1b4c: 04621703 lh a4,70(tp) # ffffd046 <__BSS_END__+0x7ffe640a> 1b50: 0000 unimp 1b52: e71f 0006 0400 0x4000006e71f 1b58: 0334 addi a3,sp,392 @@ -27481,13 +27501,13 @@ Disassembly of section .debug_info: 1b6a: 1a15 addi s4,s4,-27 1b6c: 0009 c.nop 2 1b6e: 2100 fld fs0,0(a0) - 1b70: 0200 addi s0,sp,256 + 1b70: 0194 addi a3,sp,192 1b72: 0000 unimp 1b74: 1406 slli s0,s0,0x21 1b76: 2524 fld fs1,72(a0) 1b78: 0009 c.nop 2 1b7a: 2100 fld fs0,0(a0) - 1b7c: 05d9 addi a1,a1,22 + 1b7c: 056d addi a0,a0,27 1b7e: 0000 unimp 1b80: 1506 slli a0,a0,0x21 1b82: 2c15 jal 1db6 <_start-0x7fffe24a> @@ -27509,18 +27529,19 @@ Disassembly of section .debug_info: 1ba2: 6204 flw fs1,0(a2) 1ba4: 0009 c.nop 2 1ba6: 2200 fld fs0,0(a2) - 1ba8: e121 bnez a0,1be8 <_start-0x7fffe418> + 1ba8: 7521 lui a0,0xfffe8 1baa: 0004 0x4 1bac: 0700 addi s0,sp,896 - 1bae: 05b60e67 jalr t3,91(a2) # fffeb05b <__BSS_END__+0x7ffd442b> + 1bae: 05b60e67 jalr t3,91(a2) # fffeb05b <__BSS_END__+0x7ffd441f> 1bb2: 0000 unimp - 1bb4: 4c21 li s8,8 - 1bb6: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> + 1bb4: e021 bnez s0,1bf4 <_start-0x7fffe40c> + 1bb6: 0002 c.slli64 zero + 1bb8: 0800 addi s0,sp,16 1bba: 0f10 addi a2,sp,912 1bbc: 0000097b 0x97b 1bc0: 05b6040f 0x5b6040f 1bc4: 0000 unimp - 1bc6: e421 bnez s0,1c0e <_start-0x7fffe3f2> + 1bc6: 7821 lui a6,0xfffe8 1bc8: 0004 0x4 1bca: 0800 addi s0,sp,16 1bcc: 0efc addi a5,sp,860 @@ -27543,13 +27564,13 @@ Disassembly of section .debug_info: 1bf0: 1cfd addi s9,s9,-1 1bf2: 002c addi a1,sp,8 1bf4: 0000 unimp - 1bf6: 8b21 andi a4,a4,8 + 1bf6: 1f21 addi t5,t5,-24 1bf8: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> 1bfc: 0cff 0xcff 1bfe: 002c addi a1,sp,8 1c00: 0000 unimp - 1c02: 1121 addi sp,sp,-24 - 1c04: 0005 c.nop 1 + 1c02: a521 j 220a <_start-0x7fffddf6> + 1c04: 0004 0x4 1c06: 0900 addi s0,sp,144 1c08: 169a slli a3,a3,0x26 1c0a: 0064 addi s1,sp,12 @@ -27572,12 +27593,12 @@ Disassembly of section .debug_info: 1c30: 179e slli a5,a5,0x27 1c32: 09d5 addi s3,s3,21 1c34: 0000 unimp - 1c36: bf05 j 1b66 <_start-0x7fffe49a> + 1c36: 5305 li t1,-31 1c38: 0002 c.slli64 zero 1c3a: 0a00 addi s0,sp,272 1c3c: 162a slli a2,a2,0x2a 1c3e: 00000033 add zero,zero,zero - 1c42: c705 beqz a4,1c6a <_start-0x7fffe396> + 1c42: 5b05 li s6,-31 1c44: 0005 c.nop 1 1c46: 0a00 addi s0,sp,272 1c48: 0a09152f 0xa09152f @@ -27607,25 +27628,25 @@ Disassembly of section .debug_info: 1c82: 1e10 addi a2,sp,816 1c84: 000a c.slli zero,0x2 1c86: 2300 fld fs0,0(a4) - 1c88: 0292 slli t0,t0,0x4 + 1c88: 0226 slli tp,tp,0x9 1c8a: 0000 unimp 1c8c: 00330407 0x330407 1c90: 0000 unimp 1c92: 7f06180b 0x7f06180b 1c96: 000a c.slli zero,0x2 1c98: 2400 fld fs0,8(s0) - 1c9a: 056e slli a0,a0,0x1b + 1c9a: 0502 c.slli64 a0 1c9c: 0000 unimp 1c9e: 2400 fld fs0,8(s0) - 1ca0: 0366 slli t1,t1,0x19 + 1ca0: 02fa slli t0,t0,0x1e 1ca2: 0000 unimp 1ca4: 2401 jal 1ea4 <_start-0x7fffe15c> - 1ca6: 04a9 addi s1,s1,10 + 1ca6: 043d addi s0,s0,15 1ca8: 0000 unimp 1caa: 2402 fld fs0,0(sp) - 1cac: 03ba slli t2,t2,0xe + 1cac: 034e slli t1,t1,0x13 1cae: 0000 unimp - 1cb0: 05652403 lw s0,86(a0) # 35ae0 <_start-0x7ffca520> + 1cb0: 04f92403 lw s0,79(s2) # 2ead9 <_start-0x7ffd1527> 1cb4: 0000 unimp 1cb6: 2404 fld fs1,8(s0) 1cb8: 079e slli a5,a5,0x7 @@ -27640,24 +27661,24 @@ Disassembly of section .debug_info: 1cca: 1c21 addi s8,s8,-24 1ccc: 0a42 slli s4,s4,0x10 1cce: 0000 unimp - 1cd0: 0003c523 0x3c523 + 1cd0: 00035923 0x35923 1cd4: 0700 addi s0,sp,896 1cd6: 3304 fld fs1,32(a4) 1cd8: 0000 unimp 1cda: 0b00 addi s0,sp,400 1cdc: 0ab00623 sb a1,172(zero) # ac <_start-0x7fffff54> 1ce0: 0000 unimp - 1ce2: bd24 fsd fs1,120(a0) + 1ce2: 5124 lw s1,96(a0) 1ce4: 0005 c.nop 1 1ce6: 0000 unimp - 1ce8: 8424 0x8424 + 1ce8: 1824 addi s1,sp,56 1cea: 0005 c.nop 1 1cec: 0100 addi s0,sp,128 1cee: a724 fsd fs1,72(a4) 1cf0: 0006 c.slli zero,0x1 1cf2: 0200 addi s0,sp,256 1cf4: 2100 fld fs0,0(a0) - 1cf6: 0234 addi a3,sp,264 + 1cf6: 01c8 addi a0,sp,196 1cf8: 0000 unimp 1cfa: 8b1e280b 0x8b1e280b 1cfe: 000a c.slli zero,0x2 @@ -27672,14 +27693,14 @@ Disassembly of section .debug_info: 1d14: 0659 addi a2,a2,22 1d16: 0000 unimp 1d18: 2400 fld fs0,8(s0) - 1d1a: 00000647 fmsub.s fa2,ft0,ft0,ft0,rne + 1d1a: 000005db 0x5db 1d1e: 0001 nop 1d20: 7c21 lui s8,0xfffe8 1d22: 0001 nop 1d24: 0b00 addi s0,sp,400 1d26: 0abc2a2f amoswap.w.rl s4,a1,(s8) 1d2a: 0000 unimp - 1d2c: 7c21 lui s8,0xfffe8 + 1d2c: 1021 c.nop -24 1d2e: 0c000003 lb zero,192(zero) # c0 <_start-0x7fffff40> 1d32: 1a29 addi s4,s4,-22 1d34: 0925 addi s2,s2,9 @@ -27719,10 +27740,10 @@ Disassembly of section .debug_info: 1d82: 0000 unimp 1d84: 0200 addi s0,sp,256 1d86: 0404 addi s1,sp,512 - 1d88: 04bc addi a5,sp,584 + 1d88: 0450 addi a2,sp,516 1d8a: 0000 unimp 1d8c: 0802 c.slli64 a6 - 1d8e: 0004b403 0x4b403 + 1d8e: 00044803 lbu a6,0(s0) 1d92: 0200 addi s0,sp,256 1d94: 0408 addi a0,sp,512 1d96: 00c5 addi ra,ra,17 @@ -27733,7 +27754,7 @@ Disassembly of section .debug_info: 1da2: 0320 addi s0,sp,392 1da4: 00b8 addi a4,sp,72 1da6: 0000 unimp - 1da8: ef19 bnez a4,1dc6 <_start-0x7fffe23a> + 1da8: 8319 srli a4,a4,0x6 1daa: 0002 c.slli64 zero 1dac: 0800 addi s0,sp,16 1dae: ed0d bnez a0,1de8 <_start-0x7fffe218> @@ -27764,7 +27785,7 @@ Disassembly of section .debug_info: 1df0: 0b28 addi a0,sp,408 1df2: 0000 unimp 1df4: 0400 addi s0,sp,512 - 1df6: 02c9 addi t0,t0,18 + 1df6: 025d addi tp,tp,23 1df8: 0000 unimp 1dfa: f80d bnez s0,1d2c <_start-0x7fffe2d4> 1dfc: 0301 addi t1,t1,0 @@ -27785,8 +27806,7 @@ Disassembly of section .debug_info: 1e22: 01fc addi a5,sp,204 1e24: d216 sw t0,36(sp) 1e26: 1f00000b 0x1f00000b - 1e2a: 0000030b 0x30b - 1e2e: 020d addi tp,tp,3 + 1e2a: 029f 0000 020d 0x20d0000029f 1e30: 1602 slli a2,a2,0x20 1e32: 0bd2 slli s7,s7,0x14 1e34: 0000 unimp @@ -27794,7 +27814,7 @@ Disassembly of section .debug_info: 1e3a: 0100 addi s0,sp,128 1e3c: 051a slli a0,a0,0x6 1e3e: 3401 jal 183e <_start-0x7fffe7c2> - 1e40: 3400000b 0x3400000b + 1e40: f800000b 0xf800000b 1e44: 0108 addi a0,sp,128 1e46: 1080 addi s0,sp,96 1e48: 0004 0x4 @@ -27821,7 +27841,7 @@ Disassembly of section .debug_info: 1e7a: 0d05 addi s10,s10,1 1e7c: 0000 unimp 1e7e: 292a fld fs2,136(sp) - 1e80: 3400000f 0x3400000f + 1e80: f800000f 0xf800000f 1e84: 0108 addi a0,sp,128 1e86: 0080 addi s0,sp,64 1e88: 0001 nop @@ -27900,8 +27920,8 @@ Disassembly of section .debug_info: 1f32: 0000 unimp 1f34: 1830 addi a2,sp,56 1f36: 0010 0x10 - 1f38: 9800 0x9800 - 1f3a: 0108 addi a0,sp,128 + 1f38: 5c00 lw s0,56(s0) + 1f3a: 0109 addi sp,sp,2 1f3c: 7080 flw fs0,32(s1) 1f3e: 0000 unimp 1f40: 3c00 fld fs0,56(s0) @@ -27949,7 +27969,7 @@ Disassembly of section .debug_info: 1fa0: 3000 fld fs0,32(s0) 1fa2: 10fa slli ra,ra,0x3e 1fa4: 0000 unimp - 1fa6: 0968 addi a0,sp,156 + 1fa6: 0a2c addi a1,sp,280 1fa8: 8001 c.srli64 s0 1faa: 0074 addi a3,sp,12 1fac: 0000 unimp @@ -28038,7 +28058,7 @@ Disassembly of section .debug_info: 205c: 0000 unimp 205e: 3000 fld fs0,32(s0) 2060: 0000117b 0x117b - 2064: 0ac0 addi s0,sp,340 + 2064: 0b84 addi s1,sp,464 2066: 8001 c.srli64 s0 2068: 0010 0x10 206a: 0000 unimp @@ -28050,9 +28070,8 @@ Disassembly of section .debug_info: 2076: 00000013 nop 207a: 8e31 xor a2,a2,a2 207c: 0011 c.nop 4 - 207e: f000 fsw fs0,32(s0) - 2080: 010a slli sp,sp,0x2 - 2082: 5480 lw s0,40(s1) + 207e: b400 fsd fs0,40(s0) + 2080: 5480010b 0x5480010b 2084: 0001 nop 2086: 3200 fld fs0,32(a2) 2088: 0000118f 0x118f @@ -28129,7 +28148,7 @@ Disassembly of section .debug_info: 2136: 005d c.nop 23 2138: 7630 flw fa2,104(a2) 213a: 0012 c.slli zero,0x4 - 213c: 0c00 addi s0,sp,528 + 213c: d000 sw s0,32(s0) 213e: 010c addi a1,sp,128 2140: 1480 addi s0,sp,608 2142: 0000 unimp @@ -28141,7 +28160,7 @@ Disassembly of section .debug_info: 2152: 3100 fld fs0,32(a0) 2154: 1289 addi t0,t0,-30 2156: 0000 unimp - 2158: 0c20 addi s0,sp,536 + 2158: 0ce4 addi s1,sp,604 215a: 8001 c.srli64 s0 215c: 0010 0x10 215e: 0000 unimp @@ -28446,45 +28465,45 @@ Disassembly of section .debug_info: 244c: 3600 fld fs0,40(a2) 244e: 1276 slli tp,tp,0x3d 2450: 0000 unimp - 2452: 00061d37 lui s10,0x61 + 2452: 0005b137 lui sp,0x5b 2456: 0100 addi s0,sp,128 2458: 04b1 addi s1,s1,12 245a: 1c08 addi a0,sp,560 245c: 3700000b 0x3700000b - 2460: 0622 slli a2,a2,0x8 + 2460: 05b6 slli a1,a1,0xd 2462: 0000 unimp 2464: b101 j 2064 <_start-0x7fffdf9c> 2466: 0804 addi s1,sp,16 2468: 0b1c addi a5,sp,400 246a: 0000 unimp - 246c: 00062737 lui a4,0x62 + 246c: 0005bb37 lui s6,0x5b 2470: 0100 addi s0,sp,128 2472: 04b1 addi s1,s1,12 2474: 1c08 addi a0,sp,560 2476: 3700000b 0x3700000b - 247a: 062c addi a1,sp,776 + 247a: 05c0 addi s0,sp,708 247c: 0000 unimp 247e: b101 j 207e <_start-0x7fffdf82> 2480: 0804 addi s1,sp,16 2482: 0b1c addi a5,sp,400 2484: 0000 unimp - 2486: 00037737 lui a4,0x37 + 2486: 00030b37 lui s6,0x30 248a: 0100 addi s0,sp,128 248c: 04b1 addi s1,s1,12 248e: 1c08 addi a0,sp,560 2490: 3700000b 0x3700000b - 2494: 0502 c.slli64 a0 + 2494: 0496 slli s1,s1,0x5 2496: 0000 unimp 2498: b101 j 2098 <_start-0x7fffdf68> 249a: 0804 addi s1,sp,16 249c: 0b1c addi a5,sp,400 249e: 0000 unimp - 24a0: 00036137 lui sp,0x36 + 24a0: 0002f537 lui a0,0x2f 24a4: 0100 addi s0,sp,128 24a6: 04b1 addi s1,s1,12 24a8: 1c08 addi a0,sp,560 24aa: 3700000b 0x3700000b - 24ae: 04fd addi s1,s1,31 + 24ae: 0491 addi s1,s1,4 24b0: 0000 unimp 24b2: b101 j 20b2 <_start-0x7fffdf4e> 24b4: 0804 addi s1,sp,16 @@ -28514,28 +28533,28 @@ Disassembly of section .debug_info: 24f0: 0104 addi s1,sp,128 24f2: 09d4 addi a3,sp,212 24f4: 0000 unimp - 24f6: a60c fsd fa1,8(a2) + 24f6: a10c fsd fa1,0(a0) 24f8: 0009 c.nop 2 - 24fa: 9400 0x9400 - 24fc: 0001 nop - 24fe: 4400 lw s0,8(s0) - 2500: 010c addi a1,sp,128 + 24fa: ed00 fsw fs0,24(a0) + 24fc: 0005 c.nop 1 + 24fe: 0800 addi s0,sp,16 + 2500: 010d addi sp,sp,3 2502: e080 fsw fs0,0(s1) 2504: 0006 c.slli zero,0x1 - 2506: fc00 fsw fs0,56(s0) + 2506: a800 fsd fs0,16(s0) 2508: 0012 c.slli zero,0x4 250a: 0200 addi s0,sp,256 250c: 0408 addi a0,sp,512 250e: 00c5 addi ra,ra,17 2510: 0000 unimp - 2512: 69050403 lb s0,1680(a0) # 69690 <_start-0x7ff96970> + 2512: 69050403 lb s0,1680(a0) # 2f690 <_start-0x7ffd0970> 2516: 746e flw fs0,248(sp) 2518: 0200 addi s0,sp,256 251a: 0601 addi a2,a2,0 251c: 06b9 addi a3,a3,14 251e: 0000 unimp 2520: 0802 c.slli64 a6 - 2522: c205 beqz a2,2542 <_start-0x7fffdabe> + 2522: 5605 li a2,-31 2524: 0004 0x4 2526: 0400 addi s0,sp,512 2528: 000007c3 fmadd.s fa5,ft0,ft0,ft0,rne @@ -28548,10 +28567,10 @@ Disassembly of section .debug_info: 253a: 0801 addi a6,a6,0 253c: 000006b7 lui a3,0x0 2540: 0402 c.slli64 s0 - 2542: 0002e207 0x2e207 + 2542: 00027607 0x27607 2546: 0200 addi s0,sp,256 2548: 0708 addi a0,sp,896 - 254a: 02d8 addi a4,sp,324 + 254a: 026c addi a1,sp,268 254c: 0000 unimp 254e: 4b04 lw s1,16(a4) 2550: 0008 0x8 @@ -28561,7 +28580,7 @@ Disassembly of section .debug_info: 2558: 0000 unimp 255a: 0200 addi s0,sp,256 255c: 0702 c.slli64 a4 - 255e: 02f8 addi a4,sp,332 + 255e: 028c addi a1,sp,320 2560: 0000 unimp 2562: 4e06 lw t3,64(sp) 2564: 0000 unimp @@ -28574,13 +28593,12 @@ Disassembly of section .debug_info: 2572: 7c05 lui s8,0xfffe1 2574: 0000 unimp 2576: 0800 addi s0,sp,16 - 2578: 0000030b 0x30b - 257c: 3c04 fld fs1,56(s0) + 2578: 029f 0000 3c04 0x3c040000029f 257e: 8c16 mv s8,t0 2580: 0000 unimp 2582: 0900 addi s0,sp,144 2584: 0000088b 0x88b - 2588: 250f4803 lbu a6,592(t5) + 2588: 250f4803 lbu a6,592(t5) # 20ce8 <_start-0x7ffdf318> 258c: 0000 unimp 258e: 0a00 addi s0,sp,272 2590: 0308 addi a0,sp,384 @@ -28607,7 +28625,7 @@ Disassembly of section .debug_info: 25c2: 0000 unimp 25c4: 0b04 addi s1,sp,400 25c6: 0401 addi s0,s0,0 - 25c8: 00024f0b 0x24f0b + 25c8: 0001e30b 0x1e30b 25cc: 0300 addi s0,sp,384 25ce: 0e5a slli t3,t3,0x16 25d0: 005a c.slli zero,0x16 @@ -28638,8 +28656,8 @@ Disassembly of section .debug_info: 2604: 2301 jal 2b04 <_start-0x7fffd4fc> 2606: 9d01 0x9d01 2608: 0000 unimp - 260a: 4400 lw s0,8(s0) - 260c: 010c addi a1,sp,128 + 260a: 0800 addi s0,sp,16 + 260c: 010d addi sp,sp,3 260e: e080 fsw fs0,0(s1) 2610: 0006 c.slli zero,0x1 2612: 0100 addi s0,sp,128 @@ -28659,7 +28677,8 @@ Disassembly of section .debug_info: 2630: 0000 unimp 2632: 0016 c.slli zero,0x5 2634: 1200 addi s0,sp,288 - 2636: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> + 2636: 08fe slli a7,a7,0x1f + 2638: 0000 unimp 263a: 2501 jal 2c3a <_start-0x7fffd3c6> 263c: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> 2640: 8800 0x8800 @@ -28688,14 +28707,14 @@ Disassembly of section .debug_info: 267c: 0000 unimp 267e: 1705 addi a4,a4,-31 2680: 0000 unimp - 2682: 9c12 add s8,s8,tp + 2682: 9712 add a4,a4,tp 2684: 0009 c.nop 2 2686: 0100 addi s0,sp,128 2688: 0326 slli t1,t1,0x9 268a: 0728 addi a0,sp,904 268c: 0000 unimp 268e: 000017ab 0x17ab - 2692: fe12 fsw ft4,60(sp) + 2692: f912 fsw ft4,176(sp) 2694: 0008 0x8 2696: 0100 addi s0,sp,128 2698: 0326 slli t1,t1,0x9 @@ -28720,7 +28739,7 @@ Disassembly of section .debug_info: 26cc: 0000 unimp 26ce: 1962 slli s2,s2,0x38 26d0: 0000 unimp - 26d2: a112 fsd ft4,128(sp) + 26d2: 9c12 add s8,s8,tp 26d4: 0009 c.nop 2 26d6: 0100 addi s0,sp,128 26d8: 07280327 0x7280327 @@ -28752,8 +28771,8 @@ Disassembly of section .debug_info: 271c: 0000 unimp 271e: 1bde slli s7,s7,0x37 2720: 0000 unimp - 2722: e412 fsw ft4,8(sp) - 2724: 0008 0x8 + 2722: cf12 sw tp,156(sp) + 2724: 0009 c.nop 2 2726: 0100 addi s0,sp,128 2728: 0328 addi a0,sp,392 272a: 0728 addi a0,sp,904 @@ -28778,7 +28797,7 @@ Disassembly of section .debug_info: 2750: 7c00 flw fs0,56(s0) 2752: 0002 c.slli64 zero 2754: 1700 addi s0,sp,928 - 2756: 08e9 addi a7,a7,26 + 2756: 08e4 addi s1,sp,92 2758: 0000 unimp 275a: 2c01 jal 296a <_start-0x7fffd696> 275c: 0000f303 0xf303 @@ -28790,7 +28809,7 @@ Disassembly of section .debug_info: 276a: 1200 addi s0,sp,288 276c: 00000897 auipc a7,0x0 2770: 2c01 jal 2980 <_start-0x7fffd680> - 2772: 00072103 lw sp,0(a4) # 37000 <_start-0x7ffc9000> + 2772: 00072103 lw sp,0(a4) # fffeb000 <__BSS_END__+0x7ffd43c4> 2776: 5b00 lw s0,48(a4) 2778: 001e c.slli zero,0x7 277a: 0000 unimp @@ -28799,7 +28818,7 @@ Disassembly of section .debug_info: 2780: ac00 fsd fs0,24(s0) 2782: 0002 c.slli64 zero 2784: 1700 addi s0,sp,928 - 2786: 08e9 addi a7,a7,26 + 2786: 08e4 addi s1,sp,92 2788: 0000 unimp 278a: 2d01 jal 2d9a <_start-0x7fffd266> 278c: 0000f303 0xf303 @@ -28820,22 +28839,21 @@ Disassembly of section .debug_info: 27b0: ce00 sw s0,24(a2) 27b2: 0005 c.nop 1 27b4: 1200 addi s0,sp,288 - 27b6: 093a slli s2,s2,0xe + 27b6: 0935 addi s2,s2,13 27b8: 0000 unimp 27ba: 2e01 jal 2aca <_start-0x7fffd536> 27bc: 00072803 lw a6,0(a4) 27c0: ce00 sw s0,24(a2) 27c2: 001e c.slli zero,0x7 27c4: 1200 addi s0,sp,288 - 27c6: 0921 addi s2,s2,8 + 27c6: 091c addi a5,sp,144 27c8: 0000 unimp 27ca: 2e01 jal 2ada <_start-0x7fffd526> 27cc: 00072803 lw a6,0(a4) 27d0: fb00 fsw fs0,48(a4) 27d2: 001e c.slli zero,0x7 27d4: 1200 addi s0,sp,288 - 27d6: 0908 addi a0,sp,144 - 27d8: 0000 unimp + 27d6: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> 27da: 2e01 jal 2aea <_start-0x7fffd516> 27dc: 00072803 lw a6,0(a4) 27e0: 2900 fld fs0,16(a0) @@ -28919,64 +28937,65 @@ Disassembly of section .debug_info: 289a: 219c fld fa5,0(a1) 289c: 0000 unimp 289e: 1800 addi s0,sp,48 - 28a0: 0f40 addi s0,sp,916 + 28a0: 1004 addi s1,sp,32 28a2: 8001 c.srli64 s0 28a4: 0058 addi a4,sp,4 28a6: 0000 unimp 28a8: 00000447 fmsub.s fs0,ft0,ft0,ft0,rne - 28ac: 1d12 slli s10,s10,0x24 - 28ae: 0006 c.slli zero,0x1 + 28ac: b112 fsd ft4,160(sp) + 28ae: 0005 c.nop 1 28b0: 0100 addi s0,sp,128 28b2: 032e slli t1,t1,0xb 28b4: 0728 addi a0,sp,904 28b6: 0000 unimp 28b8: 21da fld ft3,400(sp) 28ba: 0000 unimp - 28bc: 2212 fld ft4,256(sp) - 28be: 0006 c.slli zero,0x1 + 28bc: b612 fsd ft4,296(sp) + 28be: 0005 c.nop 1 28c0: 0100 addi s0,sp,128 28c2: 032e slli t1,t1,0xb 28c4: 0728 addi a0,sp,904 28c6: 0000 unimp 28c8: 2226 fld ft4,72(sp) 28ca: 0000 unimp - 28cc: 2712 fld fa4,256(sp) - 28ce: 0006 c.slli zero,0x1 + 28cc: bb12 fsd ft4,432(sp) + 28ce: 0005 c.nop 1 28d0: 0100 addi s0,sp,128 28d2: 032e slli t1,t1,0xb 28d4: 0728 addi a0,sp,904 28d6: 0000 unimp 28d8: 227a fld ft4,408(sp) 28da: 0000 unimp - 28dc: 2c12 fld fs8,256(sp) - 28de: 0006 c.slli zero,0x1 + 28dc: c012 sw tp,0(sp) + 28de: 0005 c.nop 1 28e0: 0100 addi s0,sp,128 28e2: 032e slli t1,t1,0xb 28e4: 0728 addi a0,sp,904 28e6: 0000 unimp 28e8: 000022c3 fmadd.s ft5,ft0,ft0,ft0,rdn - 28ec: 7712 flw fa4,36(sp) + 28ec: 0b12 slli s6,s6,0x4 28ee: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 28f2: 032e slli t1,t1,0xb 28f4: 0068 addi a0,sp,12 28f6: 0000 unimp 28f8: 22d6 fld ft5,336(sp) 28fa: 0000 unimp - 28fc: 0212 slli tp,tp,0x4 - 28fe: 0005 c.nop 1 + 28fc: 9612 add a2,a2,tp + 28fe: 0004 0x4 2900: 0100 addi s0,sp,128 2902: 032e slli t1,t1,0xb 2904: 0068 addi a0,sp,12 2906: 0000 unimp 2908: 22e9 jal 2ad2 <_start-0x7fffd52e> 290a: 0000 unimp - 290c: 6112 flw ft2,4(sp) - 290e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 290c: f512 fsw ft4,168(sp) + 290e: 0002 c.slli64 zero + 2910: 0100 addi s0,sp,128 2912: 032e slli t1,t1,0xb 2914: 0068 addi a0,sp,12 2916: 0000 unimp 2918: 00002307 flw ft6,0(zero) # 0 <_start-0x80000000> - 291c: fd12 fsw ft4,184(sp) + 291c: 9112 add sp,sp,tp 291e: 0004 0x4 2920: 0100 addi s0,sp,128 2922: 032e slli t1,t1,0xb @@ -29004,7 +29023,7 @@ Disassembly of section .debug_info: 295a: 0000 unimp 295c: 0000238b 0x238b 2960: 1800 addi s0,sp,48 - 2962: 0fe8 addi a0,sp,988 + 2962: 10ac addi a1,sp,104 2964: 8001 c.srli64 s0 2966: 0010 0x10 2968: 0000 unimp @@ -29075,59 +29094,60 @@ Disassembly of section .debug_info: 29fc: 0000 unimp 29fe: 059d addi a1,a1,7 2a00: 0000 unimp - 2a02: 1d12 slli s10,s10,0x24 - 2a04: 0006 c.slli zero,0x1 + 2a02: b112 fsd ft4,160(sp) + 2a04: 0005 c.nop 1 2a06: 0100 addi s0,sp,128 2a08: 032e slli t1,t1,0xb 2a0a: 0728 addi a0,sp,904 2a0c: 0000 unimp 2a0e: 24d5 jal 2cf2 <_start-0x7fffd30e> 2a10: 0000 unimp - 2a12: 2212 fld ft4,256(sp) - 2a14: 0006 c.slli zero,0x1 + 2a12: b612 fsd ft4,296(sp) + 2a14: 0005 c.nop 1 2a16: 0100 addi s0,sp,128 2a18: 032e slli t1,t1,0xb 2a1a: 0728 addi a0,sp,904 2a1c: 0000 unimp 2a1e: 2516 fld fa0,320(sp) 2a20: 0000 unimp - 2a22: 2712 fld fa4,256(sp) - 2a24: 0006 c.slli zero,0x1 + 2a22: bb12 fsd ft4,432(sp) + 2a24: 0005 c.nop 1 2a26: 0100 addi s0,sp,128 2a28: 032e slli t1,t1,0xb 2a2a: 0728 addi a0,sp,904 2a2c: 0000 unimp 2a2e: 2550 fld fa2,136(a0) 2a30: 0000 unimp - 2a32: 2c12 fld fs8,256(sp) - 2a34: 0006 c.slli zero,0x1 + 2a32: c012 sw tp,0(sp) + 2a34: 0005 c.nop 1 2a36: 0100 addi s0,sp,128 2a38: 032e slli t1,t1,0xb 2a3a: 0728 addi a0,sp,904 2a3c: 0000 unimp 2a3e: 256e fld fa0,216(sp) 2a40: 0000 unimp - 2a42: 7712 flw fa4,36(sp) + 2a42: 0b12 slli s6,s6,0x4 2a44: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 2a48: 032e slli t1,t1,0xb 2a4a: 0068 addi a0,sp,12 2a4c: 0000 unimp 2a4e: 2581 jal 308e <_start-0x7fffcf72> 2a50: 0000 unimp - 2a52: 0212 slli tp,tp,0x4 - 2a54: 0005 c.nop 1 + 2a52: 9612 add a2,a2,tp + 2a54: 0004 0x4 2a56: 0100 addi s0,sp,128 2a58: 032e slli t1,t1,0xb 2a5a: 0068 addi a0,sp,12 2a5c: 0000 unimp - 2a5e: 259f 0000 6112 0x61120000259f - 2a64: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 2a5e: 259f 0000 f512 0xf5120000259f + 2a64: 0002 c.slli64 zero + 2a66: 0100 addi s0,sp,128 2a68: 032e slli t1,t1,0xb 2a6a: 0068 addi a0,sp,12 2a6c: 0000 unimp 2a6e: 25bd jal 30dc <_start-0x7fffcf24> 2a70: 0000 unimp - 2a72: fd12 fsw ft4,184(sp) + 2a72: 9112 add sp,sp,tp 2a74: 0004 0x4 2a76: 0100 addi s0,sp,128 2a78: 032e slli t1,t1,0xb @@ -29153,8 +29173,8 @@ Disassembly of section .debug_info: 2aae: 263d jal 2ddc <_start-0x7fffd224> 2ab0: 0000 unimp 2ab2: 0000 unimp - 2ab4: 4018 lw a4,0(s0) - 2ab6: 0111 addi sp,sp,4 + 2ab4: 0418 addi a4,sp,512 + 2ab6: 0112 slli sp,sp,0x4 2ab8: 1080 addi s0,sp,96 2aba: 0000 unimp 2abc: ec00 fsw fs0,24(s0) @@ -29180,18 +29200,18 @@ Disassembly of section .debug_info: 2af6: 3816 fld fa6,352(sp) 2af8: 0e000003 lb zero,224(zero) # e0 <_start-0x7fffff20> 2afc: 17000007 0x17000007 - 2b00: 096a slli s2,s2,0x1a + 2b00: 0965 addi s2,s2,25 2b02: 0000 unimp 2b04: 2f01 jal 3214 <_start-0x7fffcdec> 2b06: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> 2b0a: 1a00 addi s0,sp,304 2b0c: 0699 addi a3,a3,6 2b0e: 0000 unimp - 2b10: 00098517 auipc a0,0x98 + 2b10: 00098017 auipc zero,0x98 2b14: 0100 addi s0,sp,128 2b16: 0721032f 0x721032f 2b1a: 0000 unimp - 2b1c: 00095317 auipc t1,0x95 + 2b1c: 00094e17 auipc t3,0x94 2b20: 0100 addi s0,sp,128 2b22: 0721032f 0x721032f 2b26: 0000 unimp @@ -29225,7 +29245,7 @@ Disassembly of section .debug_info: 2b78: 00072803 lw a6,0(a4) 2b7c: 0000 unimp 2b7e: 1800 addi s0,sp,48 - 2b80: 1284 addi s1,sp,352 + 2b80: 1348 addi a0,sp,420 2b82: 8001 c.srli64 s0 2b84: 0010 0x10 2b86: 0000 unimp @@ -29277,9 +29297,9 @@ Disassembly of section .debug_info: 2c04: 0000 unimp 2c06: 0200 addi s0,sp,256 2c08: 0504 addi s1,sp,640 - 2c0a: 000004c7 fmsub.s fs1,ft0,ft0,ft0,rne + 2c0a: 0000045b 0x45b 2c0e: 0402 c.slli64 s0 - 2c10: 0002dd07 0x2dd07 + 2c10: 00027107 0x27107 2c14: 0000 unimp 2c16: 0758 addi a4,sp,900 2c18: 0000 unimp @@ -29289,25 +29309,25 @@ Disassembly of section .debug_info: 2c22: 09d4 addi a3,sp,212 2c24: 0000 unimp 2c26: 800c 0x800c - 2c28: 9400000b 0x9400000b - 2c2c: 0001 nop - 2c2e: 2400 fld fs0,8(s0) + 2c28: ed00000b 0xed00000b + 2c2c: 0005 c.nop 1 + 2c2e: e800 fsw fs0,16(s0) 2c30: c4800113 li sp,-952 2c34: 0005 c.nop 1 - 2c36: 9700 0x9700 + 2c36: 4300 lw s0,0(a4) 2c38: 0022 c.slli zero,0x8 2c3a: 0200 addi s0,sp,256 2c3c: 0408 addi a0,sp,512 2c3e: 00c5 addi ra,ra,17 2c40: 0000 unimp - 2c42: 69050403 lb s0,1680(a0) # 9b1a0 <_start-0x7ff64e60> + 2c42: 69050403 lb s0,1680(a0) 2c46: 746e flw fs0,248(sp) 2c48: 0200 addi s0,sp,256 2c4a: 0601 addi a2,a2,0 2c4c: 06b9 addi a3,a3,14 2c4e: 0000 unimp 2c50: 0802 c.slli64 a6 - 2c52: c205 beqz a2,2c72 <_start-0x7fffd38e> + 2c52: 5605 li a2,-31 2c54: 0004 0x4 2c56: 0400 addi s0,sp,512 2c58: 000007c3 fmadd.s fa5,ft0,ft0,ft0,rne @@ -29320,10 +29340,10 @@ Disassembly of section .debug_info: 2c6a: 0801 addi a6,a6,0 2c6c: 000006b7 lui a3,0x0 2c70: 0402 c.slli64 s0 - 2c72: 0002e207 0x2e207 + 2c72: 00027607 0x27607 2c76: 0200 addi s0,sp,256 2c78: 0708 addi a0,sp,896 - 2c7a: 02d8 addi a4,sp,324 + 2c7a: 026c addi a1,sp,268 2c7c: 0000 unimp 2c7e: 4b04 lw s1,16(a4) 2c80: 0008 0x8 @@ -29333,7 +29353,7 @@ Disassembly of section .debug_info: 2c88: 0000 unimp 2c8a: 0200 addi s0,sp,256 2c8c: 0702 c.slli64 a4 - 2c8e: 02f8 addi a4,sp,332 + 2c8e: 028c addi a1,sp,320 2c90: 0000 unimp 2c92: 4e06 lw t3,64(sp) 2c94: 0000 unimp @@ -29346,8 +29366,7 @@ Disassembly of section .debug_info: 2ca2: 7c05 lui s8,0xfffe1 2ca4: 0000 unimp 2ca6: 0800 addi s0,sp,16 - 2ca8: 0000030b 0x30b - 2cac: 3c04 fld fs1,56(s0) + 2ca8: 029f 0000 3c04 0x3c040000029f 2cae: 8c16 mv s8,t0 2cb0: 0000 unimp 2cb2: 0900 addi s0,sp,144 @@ -29379,7 +29398,7 @@ Disassembly of section .debug_info: 2cf2: 0000 unimp 2cf4: 0b04 addi s1,sp,400 2cf6: 0401 addi s0,s0,0 - 2cf8: 00024f0b 0x24f0b + 2cf8: 0001e30b 0x1e30b 2cfc: 0300 addi s0,sp,384 2cfe: 0e5a slli t3,t3,0x16 2d00: 005a c.slli zero,0x16 @@ -29410,7 +29429,7 @@ Disassembly of section .debug_info: 2d34: 2301 jal 3234 <_start-0x7fffcdcc> 2d36: 9d01 0x9d01 2d38: 0000 unimp - 2d3a: 2400 fld fs0,8(s0) + 2d3a: e800 fsw fs0,16(s0) 2d3c: c4800113 li sp,-952 2d40: 0005 c.nop 1 2d42: 0100 addi s0,sp,128 @@ -29430,7 +29449,8 @@ Disassembly of section .debug_info: 2d60: fe00 fsw fs0,56(a2) 2d62: 0026 c.slli zero,0x9 2d64: 1200 addi s0,sp,288 - 2d66: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> + 2d66: 08fe slli a7,a7,0x1f + 2d68: 0000 unimp 2d6a: 2501 jal 336a <_start-0x7fffcc96> 2d6c: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> 2d70: 8600 0x8600 @@ -29456,7 +29476,7 @@ Disassembly of section .debug_info: 2daa: 0741 addi a4,a4,16 2dac: 0000 unimp 2dae: 00002803 lw a6,0(zero) # 0 <_start-0x80000000> - 2db2: 9c12 add s8,s8,tp + 2db2: 9712 add a4,a4,tp 2db4: 0009 c.nop 2 2db6: 0100 addi s0,sp,128 2db8: 0326 slli t1,t1,0x9 @@ -29464,7 +29484,7 @@ Disassembly of section .debug_info: 2dbc: 0000 unimp 2dbe: 28a9 jal 2e18 <_start-0x7fffd1e8> 2dc0: 0000 unimp - 2dc2: fe12 fsw ft4,60(sp) + 2dc2: f912 fsw ft4,176(sp) 2dc4: 0008 0x8 2dc6: 0100 addi s0,sp,128 2dc8: 0326 slli t1,t1,0x9 @@ -29489,7 +29509,7 @@ Disassembly of section .debug_info: 2dfc: 0000 unimp 2dfe: 2a56 fld fs4,336(sp) 2e00: 0000 unimp - 2e02: a112 fsd ft4,128(sp) + 2e02: 9c12 add s8,s8,tp 2e04: 0009 c.nop 2 2e06: 0100 addi s0,sp,128 2e08: 07480327 0x7480327 @@ -29521,8 +29541,8 @@ Disassembly of section .debug_info: 2e4c: 0000 unimp 2e4e: 2c69 jal 30e8 <_start-0x7fffcf18> 2e50: 0000 unimp - 2e52: e412 fsw ft4,8(sp) - 2e54: 0008 0x8 + 2e52: cf12 sw tp,156(sp) + 2e54: 0009 c.nop 2 2e56: 0100 addi s0,sp,128 2e58: 0328 addi a0,sp,392 2e5a: 0748 addi a0,sp,900 @@ -29546,13 +29566,13 @@ Disassembly of section .debug_info: 2e7e: 7c000003 lb zero,1984(zero) # 7c0 <_start-0x7ffff840> 2e82: 0002 c.slli64 zero 2e84: 1700 addi s0,sp,928 - 2e86: 08e9 addi a7,a7,26 + 2e86: 08e4 addi s1,sp,92 2e88: 0000 unimp 2e8a: 2c01 jal 309a <_start-0x7fffcf66> 2e8c: 0000f303 0xf303 2e90: 0000 unimp 2e92: 8016 c.mv zero,t0 - 2e94: 96000003 lb zero,-1696(zero) # fffff960 <__BSS_END__+0x7ffe8d30> + 2e94: 96000003 lb zero,-1696(zero) # fffff960 <__BSS_END__+0x7ffe8d24> 2e98: 0002 c.slli64 zero 2e9a: 1200 addi s0,sp,288 2e9c: 00000897 auipc a7,0x0 @@ -29562,16 +29582,16 @@ Disassembly of section .debug_info: 2ea8: 002e c.slli zero,0xb 2eaa: 0000 unimp 2eac: 9816 add a6,a6,t0 - 2eae: ac000003 lb zero,-1344(zero) # fffffac0 <__BSS_END__+0x7ffe8e90> + 2eae: ac000003 lb zero,-1344(zero) # fffffac0 <__BSS_END__+0x7ffe8e84> 2eb2: 0002 c.slli64 zero 2eb4: 1700 addi s0,sp,928 - 2eb6: 08e9 addi a7,a7,26 + 2eb6: 08e4 addi s1,sp,92 2eb8: 0000 unimp 2eba: 2d01 jal 34ca <_start-0x7fffcb36> 2ebc: 0000f303 0xf303 2ec0: 0000 unimp 2ec2: b816 fsd ft5,48(sp) - 2ec4: c6000003 lb zero,-928(zero) # fffffc60 <__BSS_END__+0x7ffe9030> + 2ec4: c6000003 lb zero,-928(zero) # fffffc60 <__BSS_END__+0x7ffe9024> 2ec8: 0002 c.slli64 zero 2eca: 1200 addi s0,sp,288 2ecc: 00000897 auipc a7,0x0 @@ -29581,7 +29601,7 @@ Disassembly of section .debug_info: 2ed8: 002e c.slli zero,0xb 2eda: 0000 unimp 2edc: d016 sw t0,32(sp) - 2ede: ee000003 lb zero,-288(zero) # fffffee0 <__BSS_END__+0x7ffe92b0> + 2ede: ee000003 lb zero,-288(zero) # fffffee0 <__BSS_END__+0x7ffe92a4> 2ee2: 0005 c.nop 1 2ee4: 1700 addi s0,sp,928 2ee6: 0b68 addi a0,sp,412 @@ -29625,47 +29645,47 @@ Disassembly of section .debug_info: 2f3c: 0004 0x4 2f3e: ae00 fsd fs0,24(a2) 2f40: 12000003 lb zero,288(zero) # 120 <_start-0x7ffffee0> - 2f44: 061d addi a2,a2,7 + 2f44: 05b1 addi a1,a1,12 2f46: 0000 unimp 2f48: 2e01 jal 3258 <_start-0x7fffcda8> 2f4a: 00074803 lbu a6,0(a4) 2f4e: 2000 fld fs0,0(s0) 2f50: 1200002f 0x1200002f - 2f54: 0622 slli a2,a2,0x8 + 2f54: 05b6 slli a1,a1,0xd 2f56: 0000 unimp 2f58: 2e01 jal 3268 <_start-0x7fffcd98> 2f5a: 00074803 lbu a6,0(a4) 2f5e: 4300 lw s0,0(a4) 2f60: 1200002f 0x1200002f - 2f64: 00000627 0x627 + 2f64: 000005bb 0x5bb 2f68: 2e01 jal 3278 <_start-0x7fffcd88> 2f6a: 00074803 lbu a6,0(a4) 2f6e: 9800 0x9800 2f70: 1200002f 0x1200002f - 2f74: 062c addi a1,sp,776 + 2f74: 05c0 addi s0,sp,708 2f76: 0000 unimp 2f78: 2e01 jal 3288 <_start-0x7fffcd78> 2f7a: 00074803 lbu a6,0(a4) 2f7e: ab00 fsd fs0,16(a4) 2f80: 1200002f 0x1200002f - 2f84: 00000377 0x377 + 2f84: 0000030b 0x30b 2f88: 2e01 jal 3298 <_start-0x7fffcd68> 2f8a: 00006803 0x6803 2f8e: be00 fsd fs0,56(a2) 2f90: 1200002f 0x1200002f - 2f94: 0502 c.slli64 a0 + 2f94: 0496 slli s1,s1,0x5 2f96: 0000 unimp 2f98: 2e01 jal 32a8 <_start-0x7fffcd58> 2f9a: 00006803 0x6803 2f9e: d100 sw s0,32(a0) 2fa0: 1200002f 0x1200002f - 2fa4: 0361 addi t1,t1,24 + 2fa4: 02f5 addi t0,t0,29 2fa6: 0000 unimp 2fa8: 2e01 jal 32b8 <_start-0x7fffcd48> 2faa: 00006803 0x6803 2fae: e400 fsw fs0,8(s0) 2fb0: 1200002f 0x1200002f - 2fb4: 04fd addi s1,s1,31 + 2fb4: 0491 addi s1,s1,4 2fb6: 0000 unimp 2fb8: 2e01 jal 32c8 <_start-0x7fffcd38> 2fba: 00006803 0x6803 @@ -29676,50 +29696,50 @@ Disassembly of section .debug_info: 2fc8: 3000 fld fs0,32(s0) 2fca: 0004 0x4 2fcc: 1200 addi s0,sp,288 - 2fce: 061d addi a2,a2,7 + 2fce: 05b1 addi a1,a1,12 2fd0: 0000 unimp 2fd2: 2e01 jal 32e2 <_start-0x7fffcd1e> 2fd4: 00074803 lbu a6,0(a4) 2fd8: 0a00 addi s0,sp,272 2fda: 0030 addi a2,sp,8 2fdc: 1200 addi s0,sp,288 - 2fde: 0622 slli a2,a2,0x8 + 2fde: 05b6 slli a1,a1,0xd 2fe0: 0000 unimp 2fe2: 2e01 jal 32f2 <_start-0x7fffcd0e> 2fe4: 00074803 lbu a6,0(a4) 2fe8: 1d00 addi s0,sp,688 2fea: 0030 addi a2,sp,8 2fec: 1200 addi s0,sp,288 - 2fee: 00000627 0x627 + 2fee: 000005bb 0x5bb 2ff2: 2e01 jal 3302 <_start-0x7fffccfe> 2ff4: 00074803 lbu a6,0(a4) 2ff8: 4b00 lw s0,16(a4) 2ffa: 0030 addi a2,sp,8 2ffc: 1200 addi s0,sp,288 - 2ffe: 062c addi a1,sp,776 + 2ffe: 05c0 addi s0,sp,708 3000: 0000 unimp 3002: 2e01 jal 3312 <_start-0x7fffccee> 3004: 00074803 lbu a6,0(a4) 3008: 5e00 lw s0,56(a2) 300a: 0030 addi a2,sp,8 300c: 1700 addi s0,sp,928 - 300e: 00000377 0x377 + 300e: 0000030b 0x30b 3012: 2e01 jal 3322 <_start-0x7fffccde> 3014: 00006803 0x6803 3018: 1700 addi s0,sp,928 - 301a: 0502 c.slli64 a0 + 301a: 0496 slli s1,s1,0x5 301c: 0000 unimp 301e: 2e01 jal 332e <_start-0x7fffccd2> 3020: 00006803 0x6803 3024: 1200 addi s0,sp,288 - 3026: 0361 addi t1,t1,24 + 3026: 02f5 addi t0,t0,29 3028: 0000 unimp 302a: 2e01 jal 333a <_start-0x7fffccc6> 302c: 00006803 0x6803 3030: 7100 flw fs0,32(a0) 3032: 0030 addi a2,sp,8 3034: 1200 addi s0,sp,288 - 3036: 04fd addi s1,s1,31 + 3036: 0491 addi s1,s1,4 3038: 0000 unimp 303a: 2e01 jal 334a <_start-0x7fffccb6> 303c: 00006803 0x6803 @@ -29731,50 +29751,50 @@ Disassembly of section .debug_info: 304a: b200 fsd fs0,32(a2) 304c: 0004 0x4 304e: 1200 addi s0,sp,288 - 3050: 061d addi a2,a2,7 + 3050: 05b1 addi a1,a1,12 3052: 0000 unimp 3054: 2e01 jal 3364 <_start-0x7fffcc9c> 3056: 00074803 lbu a6,0(a4) 305a: 9700 0x9700 305c: 0030 addi a2,sp,8 305e: 1200 addi s0,sp,288 - 3060: 0622 slli a2,a2,0x8 + 3060: 05b6 slli a1,a1,0xd 3062: 0000 unimp 3064: 2e01 jal 3374 <_start-0x7fffcc8c> 3066: 00074803 lbu a6,0(a4) 306a: aa00 fsd fs0,16(a2) 306c: 0030 addi a2,sp,8 306e: 1200 addi s0,sp,288 - 3070: 00000627 0x627 + 3070: 000005bb 0x5bb 3074: 2e01 jal 3384 <_start-0x7fffcc7c> 3076: 00074803 lbu a6,0(a4) 307a: fc00 fsw fs0,56(s0) 307c: 0030 addi a2,sp,8 307e: 1200 addi s0,sp,288 - 3080: 062c addi a1,sp,776 + 3080: 05c0 addi s0,sp,708 3082: 0000 unimp 3084: 2e01 jal 3394 <_start-0x7fffcc6c> 3086: 00074803 lbu a6,0(a4) 308a: 0f00 addi s0,sp,912 308c: 0031 c.nop 12 308e: 1700 addi s0,sp,928 - 3090: 00000377 0x377 + 3090: 0000030b 0x30b 3094: 2e01 jal 33a4 <_start-0x7fffcc5c> 3096: 00006803 0x6803 309a: 1700 addi s0,sp,928 - 309c: 0502 c.slli64 a0 + 309c: 0496 slli s1,s1,0x5 309e: 0000 unimp 30a0: 2e01 jal 33b0 <_start-0x7fffcc50> 30a2: 00006803 0x6803 30a6: 1200 addi s0,sp,288 - 30a8: 0361 addi t1,t1,24 + 30a8: 02f5 addi t0,t0,29 30aa: 0000 unimp 30ac: 2e01 jal 33bc <_start-0x7fffcc44> 30ae: 00006803 0x6803 30b2: 2200 fld fs0,0(a2) 30b4: 0031 c.nop 12 30b6: 1200 addi s0,sp,288 - 30b8: 04fd addi s1,s1,31 + 30b8: 0491 addi s1,s1,4 30ba: 0000 unimp 30bc: 2e01 jal 33cc <_start-0x7fffcc34> 30be: 00006803 0x6803 @@ -29786,50 +29806,50 @@ Disassembly of section .debug_info: 30cc: 3400 fld fs0,40(s0) 30ce: 0005 c.nop 1 30d0: 1200 addi s0,sp,288 - 30d2: 061d addi a2,a2,7 + 30d2: 05b1 addi a1,a1,12 30d4: 0000 unimp 30d6: 2e01 jal 33e6 <_start-0x7fffcc1a> 30d8: 00074803 lbu a6,0(a4) 30dc: 4800 lw s0,16(s0) 30de: 0031 c.nop 12 30e0: 1200 addi s0,sp,288 - 30e2: 0622 slli a2,a2,0x8 + 30e2: 05b6 slli a1,a1,0xd 30e4: 0000 unimp 30e6: 2e01 jal 33f6 <_start-0x7fffcc0a> 30e8: 00074803 lbu a6,0(a4) 30ec: 6600 flw fs0,8(a2) 30ee: 0031 c.nop 12 30f0: 1200 addi s0,sp,288 - 30f2: 00000627 0x627 + 30f2: 000005bb 0x5bb 30f6: 2e01 jal 3406 <_start-0x7fffcbfa> 30f8: 00074803 lbu a6,0(a4) 30fc: 9400 0x9400 30fe: 0031 c.nop 12 3100: 1200 addi s0,sp,288 - 3102: 062c addi a1,sp,776 + 3102: 05c0 addi s0,sp,708 3104: 0000 unimp 3106: 2e01 jal 3416 <_start-0x7fffcbea> 3108: 00074803 lbu a6,0(a4) 310c: a700 fsd fs0,8(a4) 310e: 0031 c.nop 12 3110: 1700 addi s0,sp,928 - 3112: 00000377 0x377 + 3112: 0000030b 0x30b 3116: 2e01 jal 3426 <_start-0x7fffcbda> 3118: 00006803 0x6803 311c: 1700 addi s0,sp,928 - 311e: 0502 c.slli64 a0 + 311e: 0496 slli s1,s1,0x5 3120: 0000 unimp 3122: 2e01 jal 3432 <_start-0x7fffcbce> 3124: 00006803 0x6803 3128: 1200 addi s0,sp,288 - 312a: 0361 addi t1,t1,24 + 312a: 02f5 addi t0,t0,29 312c: 0000 unimp 312e: 2e01 jal 343e <_start-0x7fffcbc2> 3130: 00006803 0x6803 3134: c500 sw s0,8(a0) 3136: 0031 c.nop 12 3138: 1200 addi s0,sp,288 - 313a: 04fd addi s1,s1,31 + 313a: 0491 addi s1,s1,4 313c: 0000 unimp 313e: 2e01 jal 344e <_start-0x7fffcbb2> 3140: 00006803 0x6803 @@ -29913,7 +29933,7 @@ Disassembly of section .debug_info: 31fc: b300 fsd fs0,32(a4) 31fe: 00000033 add zero,zero,zero 3202: 0000 unimp - 3204: 2c19 jal 341a <_start-0x7fffcbe6> + 3204: f019 bnez s0,310a <_start-0x7fffcef6> 3206: 10800117 auipc sp,0x10800 320a: 0000 unimp 320c: 0c00 addi s0,sp,528 @@ -29939,18 +29959,18 @@ Disassembly of section .debug_info: 3248: 0005 c.nop 1 324a: 2e00 fld fs0,24(a2) 324c: 17000007 0x17000007 - 3250: 096a slli s2,s2,0x1a + 3250: 0965 addi s2,s2,25 3252: 0000 unimp 3254: 2f01 jal 3964 <_start-0x7fffc69c> 3256: 00002c03 lw s8,0(zero) # 0 <_start-0x80000000> 325a: 1a00 addi s0,sp,304 325c: 06b9 addi a3,a3,14 325e: 0000 unimp - 3260: 00098517 auipc a0,0x98 + 3260: 00098017 auipc zero,0x98 3264: 0100 addi s0,sp,128 3266: 0741032f 0x741032f 326a: 0000 unimp - 326c: 00095317 auipc t1,0x95 + 326c: 00094e17 auipc t3,0x94 3270: 0100 addi s0,sp,128 3272: 0741032f 0x741032f 3276: 0000 unimp @@ -29984,7 +30004,7 @@ Disassembly of section .debug_info: 32c8: 00074803 lbu a6,0(a4) 32cc: 0000 unimp 32ce: 1900 addi s0,sp,176 - 32d0: 1850 addi a2,sp,52 + 32d0: 1914 addi a3,sp,176 32d2: 8001 c.srli64 s0 32d4: 0010 0x10 32d6: 0000 unimp @@ -30036,9 +30056,9 @@ Disassembly of section .debug_info: 3354: 0000 unimp 3356: 0200 addi s0,sp,256 3358: 0504 addi s1,sp,640 - 335a: 000004c7 fmsub.s fs1,ft0,ft0,ft0,rne + 335a: 0000045b 0x45b 335e: 0402 c.slli64 s0 - 3360: 0002dd07 0x2dd07 + 3360: 00027107 0x27107 3364: 1c00 addi s0,sp,560 3366: 0748 addi a0,sp,900 3368: 0000 unimp @@ -30055,13 +30075,13 @@ Disassembly of section .debug_info: 3380: 0000 unimp 3382: 170c addi a1,sp,928 3384: 000c 0xc - 3386: 9400 0x9400 - 3388: 0001 nop - 338a: e800 fsw fs0,16(s0) - 338c: 0118 addi a4,sp,128 + 3386: ed00 fsw fs0,24(a0) + 3388: 0005 c.nop 1 + 338a: ac00 fsd fs0,24(s0) + 338c: 0119 addi sp,sp,6 338e: cc80 sw s0,24(s1) 3390: 0000 unimp - 3392: 6d00 flw fs0,24(a0) + 3392: 1900 addi s0,sp,176 3394: 0030 addi a2,sp,8 3396: 0200 addi s0,sp,256 3398: 00000c57 0xc57 @@ -30077,7 +30097,7 @@ Disassembly of section .debug_info: 33ae: 0006 c.slli zero,0x1 33b0: 0400 addi s0,sp,512 33b2: 0508 addi a0,sp,640 - 33b4: 04c2 slli s1,s1,0x10 + 33b4: 0456 slli s0,s0,0x15 33b6: 0000 unimp 33b8: c305 beqz a4,33d8 <_start-0x7fffcc28> 33ba: 03000007 0x3000007 @@ -30092,13 +30112,13 @@ Disassembly of section .debug_info: 33ce: 0006 c.slli zero,0x1 33d0: 0400 addi s0,sp,512 33d2: 0704 addi s1,sp,896 - 33d4: 02e2 slli t0,t0,0x18 + 33d4: 0276 slli tp,tp,0x1d 33d6: 0000 unimp 33d8: 0804 addi s1,sp,16 - 33da: 0002d807 0x2d807 + 33da: 00026c07 0x26c07 33de: 0400 addi s0,sp,512 33e0: 0702 c.slli64 a4 - 33e2: 02f8 addi a4,sp,332 + 33e2: 028c addi a1,sp,320 33e4: 0000 unimp 33e6: 00005307 0x5307 33ea: 8400 0x8400 @@ -30108,8 +30128,7 @@ Disassembly of section .debug_info: 33f6: 7406 flw fs0,96(sp) 33f8: 0000 unimp 33fa: 0900 addi s0,sp,144 - 33fc: 0000030b 0x30b - 3400: 3c05 jal 2e30 <_start-0x7fffd1d0> + 33fc: 029f 0000 3c05 0x3c050000029f 3402: 8416 mv s0,t0 3404: 0000 unimp 3406: 0200 addi s0,sp,256 @@ -30160,7 +30179,7 @@ Disassembly of section .debug_info: 346c: 0000 unimp 346e: 0400 addi s0,sp,512 3470: 0b0c010f 0xb0c010f - 3474: 0000024f fnmadd.s ft4,ft0,ft0,ft0,rne + 3474: 000001e3 beqz zero,3c76 <_start-0x7fffc38a> 3478: 5e04 lw s1,56(a2) 347a: 5f0e lw t5,224(sp) 347c: 0000 unimp @@ -30168,7 +30187,7 @@ Disassembly of section .debug_info: 3480: 0001 nop 3482: 000c 0xc 3484: 0404 addi s1,sp,512 - 3486: 0002dd07 0x2dd07 + 3486: 00027107 0x27107 348a: 0d00 addi s0,sp,656 348c: 0c7e slli s8,s8,0x1f 348e: 0000 unimp @@ -30190,8 +30209,8 @@ Disassembly of section .debug_info: 34b6: 2301 jal 39b6 <_start-0x7fffc64a> 34b8: 2501 jal 3ab8 <_start-0x7fffc548> 34ba: 0000 unimp - 34bc: e800 fsw fs0,16(s0) - 34be: 0118 addi a4,sp,128 + 34bc: ac00 fsd fs0,24(s0) + 34be: 0119 addi sp,sp,6 34c0: cc80 sw s0,24(s1) 34c2: 0000 unimp 34c4: 0100 addi s0,sp,128 @@ -30207,7 +30226,8 @@ Disassembly of section .debug_info: 34d8: 2301 jal 39d8 <_start-0x7fffc628> 34da: 0000951b 0x951b 34de: 1200 addi s0,sp,288 - 34e0: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> + 34e0: 08fe slli a7,a7,0x1f + 34e2: 0000 unimp 34e4: 2501 jal 3ae4 <_start-0x7fffc51c> 34e6: 00003103 0x3103 34ea: 0000 unimp @@ -30220,7 +30240,7 @@ Disassembly of section .debug_info: 34f8: 1300 addi s0,sp,416 34fa: 5f41 li t5,-16 34fc: 26010063 beqz sp,375c <_start-0x7fffc8a4> - 3500: 00028403 lb s0,0(t0) + 3500: 00028403 lb s0,0(t0) # f91607e6 <__BSS_END__+0x79149baa> 3504: 1400 addi s0,sp,544 3506: 5f41 li t5,-16 3508: 26010073 0x26010073 @@ -30321,7 +30341,7 @@ Disassembly of section .debug_info: 35f2: 0000 unimp 35f4: 0000 unimp 35f6: 0404 addi s1,sp,512 - 35f8: c705 beqz a4,3620 <_start-0x7fffc9e0> + 35f8: 5b05 li s6,-31 35fa: 0004 0x4 35fc: 1b00 addi s0,sp,432 35fe: 0112 slli sp,sp,0x4 @@ -30340,14 +30360,15 @@ Disassembly of section .debug_info: 3618: 0000 unimp 361a: 920c 0x920c 361c: 000c 0xc - 361e: 9400 0x9400 - 3620: 0001 nop - 3622: b400 fsd fs0,40(s0) - 3624: 0119 addi sp,sp,6 + 361e: ed00 fsw fs0,24(a0) + 3620: 0005 c.nop 1 + 3622: 7800 flw fs0,48(s0) + 3624: 011a slli sp,sp,0x6 3626: 4480 lw s0,8(s1) 3628: 0001 nop - 362a: 4f00 lw s0,24(a4) - 362c: 02000033 mul zero,zero,zero + 362a: fb00 fsw fs0,48(a4) + 362c: 0032 c.slli zero,0xc + 362e: 0200 addi s0,sp,256 3630: 00000c57 0xc57 3634: 5002 0x5002 3636: 310d jal 3258 <_start-0x7fffcda8> @@ -30361,7 +30382,7 @@ Disassembly of section .debug_info: 3646: 0006 c.slli zero,0x1 3648: 0400 addi s0,sp,512 364a: 0508 addi a0,sp,640 - 364c: 04c2 slli s1,s1,0x10 + 364c: 0456 slli s0,s0,0x15 364e: 0000 unimp 3650: c305 beqz a4,3670 <_start-0x7fffc990> 3652: 03000007 0x3000007 @@ -30376,13 +30397,13 @@ Disassembly of section .debug_info: 3666: 0006 c.slli zero,0x1 3668: 0400 addi s0,sp,512 366a: 0704 addi s1,sp,896 - 366c: 02e2 slli t0,t0,0x18 + 366c: 0276 slli tp,tp,0x1d 366e: 0000 unimp 3670: 0804 addi s1,sp,16 - 3672: 0002d807 0x2d807 + 3672: 00026c07 0x26c07 3676: 0400 addi s0,sp,512 3678: 0702 c.slli64 a4 - 367a: 02f8 addi a4,sp,332 + 367a: 028c addi a1,sp,320 367c: 0000 unimp 367e: 00005307 0x5307 3682: 8400 0x8400 @@ -30392,8 +30413,7 @@ Disassembly of section .debug_info: 368e: 7406 flw fs0,96(sp) 3690: 0000 unimp 3692: 0900 addi s0,sp,144 - 3694: 0000030b 0x30b - 3698: 3c05 jal 30c8 <_start-0x7fffcf38> + 3694: 029f 0000 3c05 0x3c050000029f 369a: 8416 mv s0,t0 369c: 0000 unimp 369e: 0200 addi s0,sp,256 @@ -30444,7 +30464,7 @@ Disassembly of section .debug_info: 3704: 0000 unimp 3706: 0400 addi s0,sp,512 3708: 0b0c010f 0xb0c010f - 370c: 0000024f fnmadd.s ft4,ft0,ft0,ft0,rne + 370c: 000001e3 beqz zero,3f0e <_start-0x7fffc0f2> 3710: 5e04 lw s1,56(a2) 3712: 5f0e lw t5,224(sp) 3714: 0000 unimp @@ -30452,7 +30472,7 @@ Disassembly of section .debug_info: 3718: 0001 nop 371a: 000c 0xc 371c: 0404 addi s1,sp,512 - 371e: 0002dd07 0x2dd07 + 371e: 00027107 0x27107 3722: 0d00 addi s0,sp,656 3724: 0c7e slli s8,s8,0x1f 3726: 0000 unimp @@ -30474,8 +30494,8 @@ Disassembly of section .debug_info: 374e: 2301 jal 3c4e <_start-0x7fffc3b2> 3750: 2501 jal 3d50 <_start-0x7fffc2b0> 3752: 0000 unimp - 3754: b400 fsd fs0,40(s0) - 3756: 0119 addi sp,sp,6 + 3754: 7800 flw fs0,48(s0) + 3756: 011a slli sp,sp,0x6 3758: 4480 lw s0,8(s1) 375a: 0001 nop 375c: 0100 addi s0,sp,128 @@ -30491,7 +30511,8 @@ Disassembly of section .debug_info: 3770: 2301 jal 3c70 <_start-0x7fffc390> 3772: 0000951b 0x951b 3776: 1200 addi s0,sp,288 - 3778: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> + 3778: 08fe slli a7,a7,0x1f + 377a: 0000 unimp 377c: 2501 jal 3d7c <_start-0x7fffc284> 377e: 00003103 0x3103 3782: 0000 unimp @@ -30608,7 +30629,7 @@ Disassembly of section .debug_info: 3886: 00003587 fld fa1,0(zero) # 0 <_start-0x80000000> 388a: 0000 unimp 388c: 0404 addi s1,sp,512 - 388e: c705 beqz a4,38b6 <_start-0x7fffc74a> + 388e: 5b05 li s6,-31 3890: 0004 0x4 3892: 1c00 addi s0,sp,560 3894: 0112 slli sp,sp,0x4 @@ -30627,14 +30648,14 @@ Disassembly of section .debug_info: 38ae: 0000 unimp 38b0: eb0c fsw fa1,16(a4) 38b2: 000c 0xc - 38b4: 9400 0x9400 - 38b6: 0001 nop - 38b8: f800 fsw fs0,48(s0) - 38ba: 011a slli sp,sp,0x6 - 38bc: 4480 lw s0,8(s1) + 38b4: ed00 fsw fs0,24(a0) + 38b6: 0005 c.nop 1 + 38b8: bc00 fsd fs0,56(s0) + 38ba: 4480011b 0x4480011b 38be: 0001 nop - 38c0: 0c00 addi s0,sp,528 - 38c2: 02000037 lui zero,0x2000 + 38c0: b800 fsd fs0,48(s0) + 38c2: 0036 c.slli zero,0xd + 38c4: 0200 addi s0,sp,256 38c6: 00000c57 0xc57 38ca: 5002 0x5002 38cc: 310d jal 34ee <_start-0x7fffcb12> @@ -30648,7 +30669,7 @@ Disassembly of section .debug_info: 38dc: 0006 c.slli zero,0x1 38de: 0400 addi s0,sp,512 38e0: 0508 addi a0,sp,640 - 38e2: 04c2 slli s1,s1,0x10 + 38e2: 0456 slli s0,s0,0x15 38e4: 0000 unimp 38e6: c305 beqz a4,3906 <_start-0x7fffc6fa> 38e8: 03000007 0x3000007 @@ -30663,13 +30684,13 @@ Disassembly of section .debug_info: 38fc: 0006 c.slli zero,0x1 38fe: 0400 addi s0,sp,512 3900: 0704 addi s1,sp,896 - 3902: 02e2 slli t0,t0,0x18 + 3902: 0276 slli tp,tp,0x1d 3904: 0000 unimp 3906: 0804 addi s1,sp,16 - 3908: 0002d807 0x2d807 + 3908: 00026c07 0x26c07 390c: 0400 addi s0,sp,512 390e: 0702 c.slli64 a4 - 3910: 02f8 addi a4,sp,332 + 3910: 028c addi a1,sp,320 3912: 0000 unimp 3914: 00005307 0x5307 3918: 8400 0x8400 @@ -30679,8 +30700,7 @@ Disassembly of section .debug_info: 3924: 7406 flw fs0,96(sp) 3926: 0000 unimp 3928: 0900 addi s0,sp,144 - 392a: 0000030b 0x30b - 392e: 3c05 jal 335e <_start-0x7fffcca2> + 392a: 029f 0000 3c05 0x3c050000029f 3930: 8416 mv s0,t0 3932: 0000 unimp 3934: 0200 addi s0,sp,256 @@ -30731,7 +30751,7 @@ Disassembly of section .debug_info: 399a: 0000 unimp 399c: 0400 addi s0,sp,512 399e: 0b0c010f 0xb0c010f - 39a2: 0000024f fnmadd.s ft4,ft0,ft0,ft0,rne + 39a2: 000001e3 beqz zero,41a4 <_start-0x7fffbe5c> 39a6: 5e04 lw s1,56(a2) 39a8: 5f0e lw t5,224(sp) 39aa: 0000 unimp @@ -30739,7 +30759,7 @@ Disassembly of section .debug_info: 39ae: 0001 nop 39b0: 000c 0xc 39b2: 0404 addi s1,sp,512 - 39b4: 0002dd07 0x2dd07 + 39b4: 00027107 0x27107 39b8: 0d00 addi s0,sp,656 39ba: 0c7e slli s8,s8,0x1f 39bc: 0000 unimp @@ -30760,9 +30780,8 @@ Disassembly of section .debug_info: 39e4: 2301 jal 3ee4 <_start-0x7fffc11c> 39e6: 2501 jal 3fe6 <_start-0x7fffc01a> 39e8: 0000 unimp - 39ea: f800 fsw fs0,48(s0) - 39ec: 011a slli sp,sp,0x6 - 39ee: 4480 lw s0,8(s1) + 39ea: bc00 fsd fs0,56(s0) + 39ec: 4480011b 0x4480011b 39f0: 0001 nop 39f2: 0100 addi s0,sp,128 39f4: 829c 0x829c @@ -30777,7 +30796,8 @@ Disassembly of section .debug_info: 3a06: 2301 jal 3f06 <_start-0x7fffc0fa> 3a08: 0000951b 0x951b 3a0c: 1200 addi s0,sp,288 - 3a0e: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> + 3a0e: 08fe slli a7,a7,0x1f + 3a10: 0000 unimp 3a12: 2501 jal 4012 <_start-0x7fffbfee> 3a14: 00003103 0x3103 3a18: 0000 unimp @@ -30894,7 +30914,7 @@ Disassembly of section .debug_info: 3b1c: 000036bb 0x36bb 3b20: 0000 unimp 3b22: 0404 addi s1,sp,512 - 3b24: c705 beqz a4,3b4c <_start-0x7fffc4b4> + 3b24: 5b05 li s6,-31 3b26: 0004 0x4 3b28: 1c00 addi s0,sp,560 3b2a: 0112 slli sp,sp,0x4 @@ -30912,13 +30932,13 @@ Disassembly of section .debug_info: 3b42: 09d4 addi a3,sp,212 3b44: 0000 unimp 3b46: 120c addi a1,sp,288 - 3b48: 9400000f 0x9400000f - 3b4c: 0001 nop - 3b4e: 3c00 fld fs0,56(s0) - 3b50: 011c addi a5,sp,128 + 3b48: ed00000f 0xed00000f + 3b4c: 0005 c.nop 1 + 3b4e: 0000 unimp + 3b50: 011d addi sp,sp,7 3b52: 0480 addi s0,sp,576 3b54: 0010 0x10 - 3b56: c900 sw s0,16(a0) + 3b56: 7500 flw fs0,40(a0) 3b58: 003a c.slli zero,0xe 3b5a: 0200 addi s0,sp,256 3b5c: 0504 addi s1,sp,640 @@ -30928,7 +30948,7 @@ Disassembly of section .debug_info: 3b66: 0006 c.slli zero,0x1 3b68: 0300 addi s0,sp,384 3b6a: 0508 addi a0,sp,640 - 3b6c: 04c2 slli s1,s1,0x10 + 3b6c: 0456 slli s0,s0,0x15 3b6e: 0000 unimp 3b70: c304 sw s1,0(a4) 3b72: 02000007 0x2000007 @@ -30938,13 +30958,13 @@ Disassembly of section .debug_info: 3b7c: 0500 addi s0,sp,640 3b7e: 003a c.slli zero,0xe 3b80: 0000 unimp - 3b82: b7080103 lb sp,-1168(a6) # ffff8b70 <__BSS_END__+0x7ffe1f40> + 3b82: b7080103 lb sp,-1168(a6) # ffff8b70 <__BSS_END__+0x7ffe1f34> 3b86: 0006 c.slli zero,0x1 3b88: 0300 addi s0,sp,384 3b8a: 0704 addi s1,sp,896 - 3b8c: 02e2 slli t0,t0,0x18 + 3b8c: 0276 slli tp,tp,0x1d 3b8e: 0000 unimp - 3b90: d8070803 lb a6,-640(a4) + 3b90: 6c070803 lb a6,1728(a4) 3b94: 0002 c.slli64 zero 3b96: 0400 addi s0,sp,512 3b98: 0000084b fnmsub.s fa6,ft0,ft0,ft0,rne @@ -30952,7 +30972,7 @@ Disassembly of section .debug_info: 3b9e: 1601 addi a2,a2,-32 3ba0: 006e c.slli zero,0x1b 3ba2: 0000 unimp - 3ba4: f8070203 lb tp,-128(a4) + 3ba4: 8c070203 lb tp,-1856(a4) 3ba8: 0002 c.slli64 zero 3baa: 0600 addi s0,sp,768 3bac: 00000047 fmsub.s ft0,ft0,ft0,ft0,rne @@ -30963,8 +30983,9 @@ Disassembly of section .debug_info: 3bba: 0500 addi s0,sp,640 3bbc: 0075 c.nop 29 3bbe: 0000 unimp - 3bc0: 0b08 addi a0,sp,400 - 3bc2: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> + 3bc0: 9f08 0x9f08 + 3bc2: 0002 c.slli64 zero + 3bc4: 0400 addi s0,sp,512 3bc6: 163c addi a5,sp,808 3bc8: 0085 addi ra,ra,1 3bca: 0000 unimp @@ -31011,7 +31032,7 @@ Disassembly of section .debug_info: 3c30: 00000053 fadd.s ft0,ft0,ft0,rne 3c34: 0f04 addi s1,sp,912 3c36: 0c01 addi s8,s8,0 - 3c38: 00024f0b 0x24f0b + 3c38: 0001e30b 0x1e30b 3c3c: 0300 addi s0,sp,384 3c3e: 0e5e slli t3,t3,0x17 3c40: 00000053 fadd.s ft0,ft0,ft0,rne @@ -31019,7 +31040,7 @@ Disassembly of section .debug_info: 3c46: 0c00 addi s0,sp,528 3c48: 0300 addi s0,sp,384 3c4a: 0704 addi s1,sp,896 - 3c4c: 02dd addi t0,t0,23 + 3c4c: 0271 addi tp,tp,28 3c4e: 0000 unimp 3c50: 7e0d lui t3,0xfffe3 3c52: 000c 0xc @@ -31041,7 +31062,7 @@ Disassembly of section .debug_info: 3c7a: 0100 addi s0,sp,128 3c7c: 00960123 sb s1,2(a2) 3c80: 0000 unimp - 3c82: 1c3c addi a5,sp,568 + 3c82: 1d00 addi s0,sp,688 3c84: 8001 c.srli64 s0 3c86: 1004 addi s1,sp,32 3c88: 0000 unimp @@ -31056,8 +31077,8 @@ Disassembly of section .debug_info: 3c9c: 0100 addi s0,sp,128 3c9e: 00961c23 sh s1,24(a2) 3ca2: 0000 unimp - 3ca4: 0312 slli t1,t1,0x4 - 3ca6: 0009 c.nop 2 + 3ca4: fe12 fsw ft4,60(sp) + 3ca6: 0008 0x8 3ca8: 0100 addi s0,sp,128 3caa: 0325 addi t1,t1,9 3cac: 0025 c.nop 9 @@ -31159,7 +31180,7 @@ Disassembly of section .debug_info: 3d9e: 032c addi a1,sp,392 3da0: 011a slli sp,sp,0x6 3da2: 0000 unimp - 3da4: 7fa09103 lh sp,2042(ra) # fffe47fa <__BSS_END__+0x7ffcdbca> + 3da4: 7fa09103 lh sp,2042(ra) # fffe47fa <__BSS_END__+0x7ffcdbbe> 3da8: 1600 addi s0,sp,800 3daa: 0700 addi s0,sp,896 3dac: 0000 unimp @@ -31402,56 +31423,57 @@ Disassembly of section .debug_info: 3fdc: 0000 unimp 3fde: 052d addi a0,a0,11 3fe0: 0000 unimp - 3fe2: 1d12 slli s10,s10,0x24 - 3fe4: 0006 c.slli zero,0x1 + 3fe2: b112 fsd ft4,160(sp) + 3fe4: 0005 c.nop 1 3fe6: 0100 addi s0,sp,128 3fe8: 032e slli t1,t1,0xb 3fea: 00000113 li sp,0 3fee: 00005343 fmadd.s ft6,ft0,ft0,ft0,unknown - 3ff2: 2212 fld ft4,256(sp) - 3ff4: 0006 c.slli zero,0x1 + 3ff2: b612 fsd ft4,296(sp) + 3ff4: 0005 c.nop 1 3ff6: 0100 addi s0,sp,128 3ff8: 032e slli t1,t1,0xb 3ffa: 00000113 li sp,0 3ffe: 5460 lw s0,108(s0) 4000: 0000 unimp - 4002: 2712 fld fa4,256(sp) - 4004: 0006 c.slli zero,0x1 + 4002: bb12 fsd ft4,432(sp) + 4004: 0005 c.nop 1 4006: 0100 addi s0,sp,128 4008: 032e slli t1,t1,0xb 400a: 00000113 li sp,0 400e: 576e lw a4,248(sp) 4010: 0000 unimp - 4012: 2c12 fld fs8,256(sp) - 4014: 0006 c.slli zero,0x1 + 4012: c012 sw tp,0(sp) + 4014: 0005 c.nop 1 4016: 0100 addi s0,sp,128 4018: 032e slli t1,t1,0xb 401a: 00000113 li sp,0 401e: 586d li a6,-5 4020: 0000 unimp - 4022: 7712 flw fa4,36(sp) + 4022: 0b12 slli s6,s6,0x4 4024: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 4028: 032e slli t1,t1,0xb 402a: 0061 c.nop 24 402c: 0000 unimp 402e: 5880 lw s0,48(s1) 4030: 0000 unimp - 4032: 0212 slli tp,tp,0x4 - 4034: 0005 c.nop 1 + 4032: 9612 add a2,a2,tp + 4034: 0004 0x4 4036: 0100 addi s0,sp,128 4038: 032e slli t1,t1,0xb 403a: 0061 c.nop 24 403c: 0000 unimp 403e: 58ad li a7,-21 4040: 0000 unimp - 4042: 6112 flw ft2,4(sp) - 4044: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 4042: f512 fsw ft4,168(sp) + 4044: 0002 c.slli64 zero + 4046: 0100 addi s0,sp,128 4048: 032e slli t1,t1,0xb 404a: 0061 c.nop 24 404c: 0000 unimp 404e: 58da lw a7,180(sp) 4050: 0000 unimp - 4052: fd12 fsw ft4,184(sp) + 4052: 9112 add sp,sp,tp 4054: 0004 0x4 4056: 0100 addi s0,sp,128 4058: 032e slli t1,t1,0xb @@ -31462,55 +31484,56 @@ Disassembly of section .debug_info: 4064: 0810 addi a2,sp,16 4066: 0000 unimp 4068: 000005b3 add a1,zero,zero - 406c: 1d12 slli s10,s10,0x24 - 406e: 0006 c.slli zero,0x1 + 406c: b112 fsd ft4,160(sp) + 406e: 0005 c.nop 1 4070: 0100 addi s0,sp,128 4072: 032e slli t1,t1,0xb 4074: 00000113 li sp,0 4078: 5934 lw a3,112(a0) 407a: 0000 unimp - 407c: 2212 fld ft4,256(sp) - 407e: 0006 c.slli zero,0x1 + 407c: b612 fsd ft4,296(sp) + 407e: 0005 c.nop 1 4080: 0100 addi s0,sp,128 4082: 032e slli t1,t1,0xb 4084: 00000113 li sp,0 4088: 5a3d li s4,-17 408a: 0000 unimp - 408c: 2712 fld fa4,256(sp) - 408e: 0006 c.slli zero,0x1 + 408c: bb12 fsd ft4,432(sp) + 408e: 0005 c.nop 1 4090: 0100 addi s0,sp,128 4092: 032e slli t1,t1,0xb 4094: 00000113 li sp,0 4098: 5d02 lw s10,32(sp) 409a: 0000 unimp - 409c: 2c12 fld fs8,256(sp) - 409e: 0006 c.slli zero,0x1 + 409c: c012 sw tp,0(sp) + 409e: 0005 c.nop 1 40a0: 0100 addi s0,sp,128 40a2: 032e slli t1,t1,0xb 40a4: 00000113 li sp,0 40a8: 5d9d li s11,-25 40aa: 0000 unimp - 40ac: 7712 flw fa4,36(sp) + 40ac: 0b12 slli s6,s6,0x4 40ae: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 40b2: 032e slli t1,t1,0xb 40b4: 0061 c.nop 24 40b6: 0000 unimp 40b8: 5db0 lw a2,120(a1) 40ba: 0000 unimp - 40bc: 0219 addi tp,tp,6 - 40be: 0005 c.nop 1 + 40bc: 9619 srai a2,a2,0x26 + 40be: 0004 0x4 40c0: 0100 addi s0,sp,128 40c2: 032e slli t1,t1,0xb 40c4: 0061 c.nop 24 40c6: 0000 unimp - 40c8: 6112 flw ft2,4(sp) - 40ca: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 40c8: f512 fsw ft4,168(sp) + 40ca: 0002 c.slli64 zero + 40cc: 0100 addi s0,sp,128 40ce: 032e slli t1,t1,0xb 40d0: 0061 c.nop 24 40d2: 0000 unimp 40d4: 5dd2 lw s11,52(sp) 40d6: 0000 unimp - 40d8: fd12 fsw ft4,184(sp) + 40d8: 9112 add sp,sp,tp 40da: 0004 0x4 40dc: 0100 addi s0,sp,128 40de: 032e slli t1,t1,0xb @@ -31523,54 +31546,55 @@ Disassembly of section .debug_info: 40ec: 0000 unimp 40ee: 0639 addi a2,a2,14 40f0: 0000 unimp - 40f2: 1d12 slli s10,s10,0x24 - 40f4: 0006 c.slli zero,0x1 + 40f2: b112 fsd ft4,160(sp) + 40f4: 0005 c.nop 1 40f6: 0100 addi s0,sp,128 40f8: 032e slli t1,t1,0xb 40fa: 00000113 li sp,0 40fe: 5e2c lw a1,120(a2) 4100: 0000 unimp - 4102: 2212 fld ft4,256(sp) - 4104: 0006 c.slli zero,0x1 + 4102: b612 fsd ft4,296(sp) + 4104: 0005 c.nop 1 4106: 0100 addi s0,sp,128 4108: 032e slli t1,t1,0xb 410a: 00000113 li sp,0 410e: 5f20 lw s0,120(a4) 4110: 0000 unimp - 4112: 2712 fld fa4,256(sp) - 4114: 0006 c.slli zero,0x1 + 4112: bb12 fsd ft4,432(sp) + 4114: 0005 c.nop 1 4116: 0100 addi s0,sp,128 4118: 032e slli t1,t1,0xb 411a: 00000113 li sp,0 411e: 6188 flw fa0,0(a1) 4120: 0000 unimp - 4122: 2c12 fld fs8,256(sp) - 4124: 0006 c.slli zero,0x1 + 4122: c012 sw tp,0(sp) + 4124: 0005 c.nop 1 4126: 0100 addi s0,sp,128 4128: 032e slli t1,t1,0xb 412a: 00000113 li sp,0 412e: 6278 flw fa4,68(a2) 4130: 0000 unimp - 4132: 7719 lui a4,0xfffe6 + 4132: 0b19 addi s6,s6,6 4134: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 4138: 032e slli t1,t1,0xb 413a: 0061 c.nop 24 413c: 0000 unimp - 413e: 0212 slli tp,tp,0x4 - 4140: 0005 c.nop 1 + 413e: 9612 add a2,a2,tp + 4140: 0004 0x4 4142: 0100 addi s0,sp,128 4144: 032e slli t1,t1,0xb 4146: 0061 c.nop 24 4148: 0000 unimp 414a: 0000628b 0x628b - 414e: 6112 flw ft2,4(sp) - 4150: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 414e: f512 fsw ft4,168(sp) + 4150: 0002 c.slli64 zero + 4152: 0100 addi s0,sp,128 4154: 032e slli t1,t1,0xb 4156: 0061 c.nop 24 4158: 0000 unimp 415a: 62ad lui t0,0xb 415c: 0000 unimp - 415e: fd12 fsw ft4,184(sp) + 415e: 9112 add sp,sp,tp 4160: 0004 0x4 4162: 0100 addi s0,sp,128 4164: 032e slli t1,t1,0xb @@ -31583,49 +31607,50 @@ Disassembly of section .debug_info: 4172: 0000 unimp 4174: 06b9 addi a3,a3,14 4176: 0000 unimp - 4178: 1d12 slli s10,s10,0x24 - 417a: 0006 c.slli zero,0x1 + 4178: b112 fsd ft4,160(sp) + 417a: 0005 c.nop 1 417c: 0100 addi s0,sp,128 417e: 032e slli t1,t1,0xb 4180: 00000113 li sp,0 4184: 00006307 0x6307 - 4188: 2212 fld ft4,256(sp) - 418a: 0006 c.slli zero,0x1 + 4188: b612 fsd ft4,296(sp) + 418a: 0005 c.nop 1 418c: 0100 addi s0,sp,128 418e: 032e slli t1,t1,0xb 4190: 00000113 li sp,0 4194: 000063a7 0x63a7 - 4198: 00062717 auipc a4,0x62 + 4198: 0005bb17 auipc s6,0x5b 419c: 0100 addi s0,sp,128 419e: 032e slli t1,t1,0xb 41a0: 00000113 li sp,0 41a4: 5c01 li s8,-32 - 41a6: 2c12 fld fs8,256(sp) - 41a8: 0006 c.slli zero,0x1 + 41a6: c012 sw tp,0(sp) + 41a8: 0005 c.nop 1 41aa: 0100 addi s0,sp,128 41ac: 032e slli t1,t1,0xb 41ae: 00000113 li sp,0 41b2: 6575 lui a0,0x1d 41b4: 0000 unimp - 41b6: 7719 lui a4,0xfffe6 + 41b6: 0b19 addi s6,s6,6 41b8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 41bc: 032e slli t1,t1,0xb 41be: 0061 c.nop 24 41c0: 0000 unimp - 41c2: 0219 addi tp,tp,6 - 41c4: 0005 c.nop 1 + 41c2: 9619 srai a2,a2,0x26 + 41c4: 0004 0x4 41c6: 0100 addi s0,sp,128 41c8: 032e slli t1,t1,0xb 41ca: 0061 c.nop 24 41cc: 0000 unimp - 41ce: 6112 flw ft2,4(sp) - 41d0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 41ce: f512 fsw ft4,168(sp) + 41d0: 0002 c.slli64 zero + 41d2: 0100 addi s0,sp,128 41d4: 032e slli t1,t1,0xb 41d6: 0061 c.nop 24 41d8: 0000 unimp 41da: 6588 flw fa0,8(a1) 41dc: 0000 unimp - 41de: fd12 fsw ft4,184(sp) + 41de: 9112 add sp,sp,tp 41e0: 0004 0x4 41e2: 0100 addi s0,sp,128 41e4: 032e slli t1,t1,0xb @@ -31636,53 +31661,54 @@ Disassembly of section .debug_info: 41ee: 1600 addi s0,sp,800 41f0: 0898 addi a4,sp,80 41f2: 0000 unimp - 41f4: 0000073f 00061d12 0x61d120000073f + 41f4: 0000073f 0005b112 0x5b1120000073f 41fc: 0100 addi s0,sp,128 41fe: 032e slli t1,t1,0xb 4200: 00000113 li sp,0 4204: 65e2 flw fa1,24(sp) 4206: 0000 unimp - 4208: 2212 fld ft4,256(sp) - 420a: 0006 c.slli zero,0x1 + 4208: b612 fsd ft4,296(sp) + 420a: 0005 c.nop 1 420c: 0100 addi s0,sp,128 420e: 032e slli t1,t1,0xb 4210: 00000113 li sp,0 4214: 000066eb 0x66eb - 4218: 2712 fld fa4,256(sp) - 421a: 0006 c.slli zero,0x1 + 4218: bb12 fsd ft4,432(sp) + 421a: 0005 c.nop 1 421c: 0100 addi s0,sp,128 421e: 032e slli t1,t1,0xb 4220: 00000113 li sp,0 4224: 69c2 flw fs3,16(sp) 4226: 0000 unimp - 4228: 2c12 fld fs8,256(sp) - 422a: 0006 c.slli zero,0x1 + 4228: c012 sw tp,0(sp) + 422a: 0005 c.nop 1 422c: 0100 addi s0,sp,128 422e: 032e slli t1,t1,0xb 4230: 00000113 li sp,0 4234: 6a5d lui s4,0x17 4236: 0000 unimp - 4238: 7712 flw fa4,36(sp) + 4238: 0b12 slli s6,s6,0x4 423a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 423e: 032e slli t1,t1,0xb 4240: 0061 c.nop 24 4242: 0000 unimp 4244: 6a70 flw fa2,84(a2) 4246: 0000 unimp - 4248: 0219 addi tp,tp,6 - 424a: 0005 c.nop 1 + 4248: 9619 srai a2,a2,0x26 + 424a: 0004 0x4 424c: 0100 addi s0,sp,128 424e: 032e slli t1,t1,0xb 4250: 0061 c.nop 24 4252: 0000 unimp - 4254: 6112 flw ft2,4(sp) - 4256: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 4254: f512 fsw ft4,168(sp) + 4256: 0002 c.slli64 zero + 4258: 0100 addi s0,sp,128 425a: 032e slli t1,t1,0xb 425c: 0061 c.nop 24 425e: 0000 unimp 4260: 6a92 flw fs5,4(sp) 4262: 0000 unimp - 4264: fd12 fsw ft4,184(sp) + 4264: 9112 add sp,sp,tp 4266: 0004 0x4 4268: 0100 addi s0,sp,128 426a: 032e slli t1,t1,0xb @@ -31692,55 +31718,56 @@ Disassembly of section .debug_info: 4278: 0000 unimp 427a: 07c5 addi a5,a5,17 427c: 0000 unimp - 427e: 1d12 slli s10,s10,0x24 - 4280: 0006 c.slli zero,0x1 + 427e: b112 fsd ft4,160(sp) + 4280: 0005 c.nop 1 4282: 0100 addi s0,sp,128 4284: 032e slli t1,t1,0xb 4286: 00000113 li sp,0 428a: 6aec flw fa1,84(a3) 428c: 0000 unimp - 428e: 2212 fld ft4,256(sp) - 4290: 0006 c.slli zero,0x1 + 428e: b612 fsd ft4,296(sp) + 4290: 0005 c.nop 1 4292: 0100 addi s0,sp,128 4294: 032e slli t1,t1,0xb 4296: 00000113 li sp,0 429a: 6be0 flw fs0,84(a5) 429c: 0000 unimp - 429e: 2712 fld fa4,256(sp) - 42a0: 0006 c.slli zero,0x1 + 429e: bb12 fsd ft4,432(sp) + 42a0: 0005 c.nop 1 42a2: 0100 addi s0,sp,128 42a4: 032e slli t1,t1,0xb 42a6: 00000113 li sp,0 42aa: 6e71 lui t3,0x1c 42ac: 0000 unimp - 42ae: 2c12 fld fs8,256(sp) - 42b0: 0006 c.slli zero,0x1 + 42ae: c012 sw tp,0(sp) + 42b0: 0005 c.nop 1 42b2: 0100 addi s0,sp,128 42b4: 032e slli t1,t1,0xb 42b6: 00000113 li sp,0 42ba: 6f61 lui t5,0x18 42bc: 0000 unimp - 42be: 7719 lui a4,0xfffe6 + 42be: 0b19 addi s6,s6,6 42c0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 42c4: 032e slli t1,t1,0xb 42c6: 0061 c.nop 24 42c8: 0000 unimp - 42ca: 0212 slli tp,tp,0x4 - 42cc: 0005 c.nop 1 + 42ca: 9612 add a2,a2,tp + 42cc: 0004 0x4 42ce: 0100 addi s0,sp,128 42d0: 032e slli t1,t1,0xb 42d2: 0061 c.nop 24 42d4: 0000 unimp 42d6: 6f74 flw fa3,92(a4) 42d8: 0000 unimp - 42da: 6112 flw ft2,4(sp) - 42dc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 42da: f512 fsw ft4,168(sp) + 42dc: 0002 c.slli64 zero + 42de: 0100 addi s0,sp,128 42e0: 032e slli t1,t1,0xb 42e2: 0061 c.nop 24 42e4: 0000 unimp 42e6: 6f96 flw ft11,68(sp) 42e8: 0000 unimp - 42ea: fd12 fsw ft4,184(sp) + 42ea: 9112 add sp,sp,tp 42ec: 0004 0x4 42ee: 0100 addi s0,sp,128 42f0: 032e slli t1,t1,0xb @@ -31831,53 +31858,54 @@ Disassembly of section .debug_info: 43d0: 0000 unimp 43d2: 091d addi s2,s2,7 43d4: 0000 unimp - 43d6: 1d12 slli s10,s10,0x24 - 43d8: 0006 c.slli zero,0x1 + 43d6: b112 fsd ft4,160(sp) + 43d8: 0005 c.nop 1 43da: 0100 addi s0,sp,128 43dc: 032e slli t1,t1,0xb 43de: 00000113 li sp,0 43e2: 7db4 flw fa3,120(a1) 43e4: 0000 unimp - 43e6: 2212 fld ft4,256(sp) - 43e8: 0006 c.slli zero,0x1 + 43e6: b612 fsd ft4,296(sp) + 43e8: 0005 c.nop 1 43ea: 0100 addi s0,sp,128 43ec: 032e slli t1,t1,0xb 43ee: 00000113 li sp,0 43f2: 00007e93 andi t4,zero,0 - 43f6: 2712 fld fa4,256(sp) - 43f8: 0006 c.slli zero,0x1 + 43f6: bb12 fsd ft4,432(sp) + 43f8: 0005 c.nop 1 43fa: 0100 addi s0,sp,128 43fc: 032e slli t1,t1,0xb 43fe: 00000113 li sp,0 4402: 80ee mv ra,s11 4404: 0000 unimp - 4406: 2c12 fld fs8,256(sp) - 4408: 0006 c.slli zero,0x1 + 4406: c012 sw tp,0(sp) + 4408: 0005 c.nop 1 440a: 0100 addi s0,sp,128 440c: 032e slli t1,t1,0xb 440e: 00000113 li sp,0 4412: 8160 0x8160 4414: 0000 unimp - 4416: 7712 flw fa4,36(sp) + 4416: 0b12 slli s6,s6,0x4 4418: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 441c: 032e slli t1,t1,0xb 441e: 0061 c.nop 24 4420: 0000 unimp 4422: 00008173 0x8173 - 4426: 0219 addi tp,tp,6 - 4428: 0005 c.nop 1 + 4426: 9619 srai a2,a2,0x26 + 4428: 0004 0x4 442a: 0100 addi s0,sp,128 442c: 032e slli t1,t1,0xb 442e: 0061 c.nop 24 4430: 0000 unimp - 4432: 6112 flw ft2,4(sp) - 4434: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 4432: f512 fsw ft4,168(sp) + 4434: 0002 c.slli64 zero + 4436: 0100 addi s0,sp,128 4438: 032e slli t1,t1,0xb 443a: 0061 c.nop 24 443c: 0000 unimp 443e: 8195 srli a1,a1,0x5 4440: 0000 unimp - 4442: fd12 fsw ft4,184(sp) + 4442: 9112 add sp,sp,tp 4444: 0004 0x4 4446: 0100 addi s0,sp,128 4448: 032e slli t1,t1,0xb @@ -31889,54 +31917,55 @@ Disassembly of section .debug_info: 4454: 0a68 addi a0,sp,284 4456: 0000 unimp 4458: 000009a3 sb zero,19(zero) # 13 <_start-0x7fffffed> - 445c: 1d12 slli s10,s10,0x24 - 445e: 0006 c.slli zero,0x1 + 445c: b112 fsd ft4,160(sp) + 445e: 0005 c.nop 1 4460: 0100 addi s0,sp,128 4462: 032e slli t1,t1,0xb 4464: 00000113 li sp,0 4468: 000081ef jal gp,c468 <_start-0x7fff3b98> - 446c: 2212 fld ft4,256(sp) - 446e: 0006 c.slli zero,0x1 + 446c: b612 fsd ft4,296(sp) + 446e: 0005 c.nop 1 4470: 0100 addi s0,sp,128 4472: 032e slli t1,t1,0xb 4474: 00000113 li sp,0 4478: 82ce mv t0,s3 447a: 0000 unimp - 447c: 2712 fld fa4,256(sp) - 447e: 0006 c.slli zero,0x1 + 447c: bb12 fsd ft4,432(sp) + 447e: 0005 c.nop 1 4480: 0100 addi s0,sp,128 4482: 032e slli t1,t1,0xb 4484: 00000113 li sp,0 4488: 8475 srai s0,s0,0x1d 448a: 0000 unimp - 448c: 2c12 fld fs8,256(sp) - 448e: 0006 c.slli zero,0x1 + 448c: c012 sw tp,0(sp) + 448e: 0005 c.nop 1 4490: 0100 addi s0,sp,128 4492: 032e slli t1,t1,0xb 4494: 00000113 li sp,0 4498: 8551 srai a0,a0,0x14 449a: 0000 unimp - 449c: 7719 lui a4,0xfffe6 + 449c: 0b19 addi s6,s6,6 449e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 44a2: 032e slli t1,t1,0xb 44a4: 0061 c.nop 24 44a6: 0000 unimp - 44a8: 0212 slli tp,tp,0x4 - 44aa: 0005 c.nop 1 + 44a8: 9612 add a2,a2,tp + 44aa: 0004 0x4 44ac: 0100 addi s0,sp,128 44ae: 032e slli t1,t1,0xb 44b0: 0061 c.nop 24 44b2: 0000 unimp 44b4: 8564 0x8564 44b6: 0000 unimp - 44b8: 6112 flw ft2,4(sp) - 44ba: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 44b8: f512 fsw ft4,168(sp) + 44ba: 0002 c.slli64 zero + 44bc: 0100 addi s0,sp,128 44be: 032e slli t1,t1,0xb 44c0: 0061 c.nop 24 44c2: 0000 unimp 44c4: 8586 mv a1,ra 44c6: 0000 unimp - 44c8: fd12 fsw ft4,184(sp) + 44c8: 9112 add sp,sp,tp 44ca: 0004 0x4 44cc: 0100 addi s0,sp,128 44ce: 032e slli t1,t1,0xb @@ -31947,50 +31976,51 @@ Disassembly of section .debug_info: 44da: 0a90 addi a2,sp,336 44dc: 0000 unimp 44de: 00000a23 sb zero,20(zero) # 14 <_start-0x7fffffec> - 44e2: 1d12 slli s10,s10,0x24 - 44e4: 0006 c.slli zero,0x1 + 44e2: b112 fsd ft4,160(sp) + 44e4: 0005 c.nop 1 44e6: 0100 addi s0,sp,128 44e8: 032e slli t1,t1,0xb 44ea: 00000113 li sp,0 44ee: 85e0 0x85e0 44f0: 0000 unimp - 44f2: 2212 fld ft4,256(sp) - 44f4: 0006 c.slli zero,0x1 + 44f2: b612 fsd ft4,296(sp) + 44f4: 0005 c.nop 1 44f6: 0100 addi s0,sp,128 44f8: 032e slli t1,t1,0xb 44fa: 00000113 li sp,0 44fe: 8680 0x8680 4500: 0000 unimp - 4502: 00062717 auipc a4,0x62 + 4502: 0005bb17 auipc s6,0x5b 4506: 0100 addi s0,sp,128 4508: 032e slli t1,t1,0xb 450a: 00000113 li sp,0 450e: 6c01 0x6c01 - 4510: 2c12 fld fs8,256(sp) - 4512: 0006 c.slli zero,0x1 + 4510: c012 sw tp,0(sp) + 4512: 0005 c.nop 1 4514: 0100 addi s0,sp,128 4516: 032e slli t1,t1,0xb 4518: 00000113 li sp,0 451c: 8848 0x8848 451e: 0000 unimp - 4520: 7719 lui a4,0xfffe6 + 4520: 0b19 addi s6,s6,6 4522: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 4526: 032e slli t1,t1,0xb 4528: 0061 c.nop 24 452a: 0000 unimp - 452c: 0219 addi tp,tp,6 - 452e: 0005 c.nop 1 + 452c: 9619 srai a2,a2,0x26 + 452e: 0004 0x4 4530: 0100 addi s0,sp,128 4532: 032e slli t1,t1,0xb 4534: 0061 c.nop 24 4536: 0000 unimp - 4538: 6112 flw ft2,4(sp) - 453a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 4538: f512 fsw ft4,168(sp) + 453a: 0002 c.slli64 zero + 453c: 0100 addi s0,sp,128 453e: 032e slli t1,t1,0xb 4540: 0061 c.nop 24 4542: 0000 unimp 4544: 0000885b 0x885b - 4548: fd12 fsw ft4,184(sp) + 4548: 9112 add sp,sp,tp 454a: 0004 0x4 454c: 0100 addi s0,sp,128 454e: 032e slli t1,t1,0xb @@ -32002,51 +32032,52 @@ Disassembly of section .debug_info: 455a: 0ab0 addi a2,sp,344 455c: 0000 unimp 455e: 00000aa3 sb zero,21(zero) # 15 <_start-0x7fffffeb> - 4562: 1d12 slli s10,s10,0x24 - 4564: 0006 c.slli zero,0x1 + 4562: b112 fsd ft4,160(sp) + 4564: 0005 c.nop 1 4566: 0100 addi s0,sp,128 4568: 032e slli t1,t1,0xb 456a: 00000113 li sp,0 456e: 88b5 andi s1,s1,13 4570: 0000 unimp - 4572: 2212 fld ft4,256(sp) - 4574: 0006 c.slli zero,0x1 + 4572: b612 fsd ft4,296(sp) + 4574: 0005 c.nop 1 4576: 0100 addi s0,sp,128 4578: 032e slli t1,t1,0xb 457a: 00000113 li sp,0 457e: 8955 andi a0,a0,21 4580: 0000 unimp - 4582: 00062717 auipc a4,0x62 + 4582: 0005bb17 auipc s6,0x5b 4586: 0100 addi s0,sp,128 4588: 032e slli t1,t1,0xb 458a: 00000113 li sp,0 458e: 6c01 0x6c01 - 4590: 2c12 fld fs8,256(sp) - 4592: 0006 c.slli zero,0x1 + 4590: c012 sw tp,0(sp) + 4592: 0005 c.nop 1 4594: 0100 addi s0,sp,128 4596: 032e slli t1,t1,0xb 4598: 00000113 li sp,0 459c: 8b3e mv s6,a5 459e: 0000 unimp - 45a0: 7719 lui a4,0xfffe6 + 45a0: 0b19 addi s6,s6,6 45a2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 45a6: 032e slli t1,t1,0xb 45a8: 0061 c.nop 24 45aa: 0000 unimp - 45ac: 0219 addi tp,tp,6 - 45ae: 0005 c.nop 1 + 45ac: 9619 srai a2,a2,0x26 + 45ae: 0004 0x4 45b0: 0100 addi s0,sp,128 45b2: 032e slli t1,t1,0xb 45b4: 0061 c.nop 24 45b6: 0000 unimp - 45b8: 6112 flw ft2,4(sp) - 45ba: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 45b8: f512 fsw ft4,168(sp) + 45ba: 0002 c.slli64 zero + 45bc: 0100 addi s0,sp,128 45be: 032e slli t1,t1,0xb 45c0: 0061 c.nop 24 45c2: 0000 unimp 45c4: 8b51 andi a4,a4,20 45c6: 0000 unimp - 45c8: fd12 fsw ft4,184(sp) + 45c8: 9112 add sp,sp,tp 45ca: 0004 0x4 45cc: 0100 addi s0,sp,128 45ce: 032e slli t1,t1,0xb @@ -32111,48 +32142,49 @@ Disassembly of section .debug_info: 466a: 0bc0 addi s0,sp,468 466c: 0000 unimp 466e: 00000bb3 add s7,zero,zero - 4672: 1d12 slli s10,s10,0x24 - 4674: 0006 c.slli zero,0x1 + 4672: b112 fsd ft4,160(sp) + 4674: 0005 c.nop 1 4676: 0100 addi s0,sp,128 4678: 032e slli t1,t1,0xb 467a: 00000113 li sp,0 467e: 00008c1b 0x8c1b - 4682: 2212 fld ft4,256(sp) - 4684: 0006 c.slli zero,0x1 + 4682: b612 fsd ft4,296(sp) + 4684: 0005 c.nop 1 4686: 0100 addi s0,sp,128 4688: 032e slli t1,t1,0xb 468a: 00000113 li sp,0 468e: 00008cbb 0x8cbb - 4692: 00062717 auipc a4,0x62 + 4692: 0005bb17 auipc s6,0x5b 4696: 0100 addi s0,sp,128 4698: 032e slli t1,t1,0xb 469a: 00000113 li sp,0 469e: 6401 0x6401 - 46a0: 2c12 fld fs8,256(sp) - 46a2: 0006 c.slli zero,0x1 + 46a0: c012 sw tp,0(sp) + 46a2: 0005 c.nop 1 46a4: 0100 addi s0,sp,128 46a6: 032e slli t1,t1,0xb 46a8: 00000113 li sp,0 46ac: 00008e83 lb t4,0(ra) - 46b0: 7719 lui a4,0xfffe6 + 46b0: 0b19 addi s6,s6,6 46b2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 46b6: 032e slli t1,t1,0xb 46b8: 0061 c.nop 24 46ba: 0000 unimp - 46bc: 0219 addi tp,tp,6 - 46be: 0005 c.nop 1 + 46bc: 9619 srai a2,a2,0x26 + 46be: 0004 0x4 46c0: 0100 addi s0,sp,128 46c2: 032e slli t1,t1,0xb 46c4: 0061 c.nop 24 46c6: 0000 unimp - 46c8: 6112 flw ft2,4(sp) - 46ca: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 46c8: f512 fsw ft4,168(sp) + 46ca: 0002 c.slli64 zero + 46cc: 0100 addi s0,sp,128 46ce: 032e slli t1,t1,0xb 46d0: 0061 c.nop 24 46d2: 0000 unimp 46d4: 8e96 mv t4,t0 46d6: 0000 unimp - 46d8: fd12 fsw ft4,184(sp) + 46d8: 9112 add sp,sp,tp 46da: 0004 0x4 46dc: 0100 addi s0,sp,128 46de: 032e slli t1,t1,0xb @@ -32164,52 +32196,53 @@ Disassembly of section .debug_info: 46ec: 0000 unimp 46ee: 0c35 addi s8,s8,13 46f0: 0000 unimp - 46f2: 1d12 slli s10,s10,0x24 - 46f4: 0006 c.slli zero,0x1 + 46f2: b112 fsd ft4,160(sp) + 46f4: 0005 c.nop 1 46f6: 0100 addi s0,sp,128 46f8: 032e slli t1,t1,0xb 46fa: 00000113 li sp,0 46fe: 8ef0 0x8ef0 4700: 0000 unimp - 4702: 2212 fld ft4,256(sp) - 4704: 0006 c.slli zero,0x1 + 4702: b612 fsd ft4,296(sp) + 4704: 0005 c.nop 1 4706: 0100 addi s0,sp,128 4708: 032e slli t1,t1,0xb 470a: 00000113 li sp,0 470e: 00008f7b 0x8f7b - 4712: 2712 fld fa4,256(sp) - 4714: 0006 c.slli zero,0x1 + 4712: bb12 fsd ft4,432(sp) + 4714: 0005 c.nop 1 4716: 0100 addi s0,sp,128 4718: 032e slli t1,t1,0xb 471a: 00000113 li sp,0 471e: 90fa add ra,ra,t5 4720: 0000 unimp - 4722: 2c12 fld fs8,256(sp) - 4724: 0006 c.slli zero,0x1 + 4722: c012 sw tp,0(sp) + 4724: 0005 c.nop 1 4726: 0100 addi s0,sp,128 4728: 032e slli t1,t1,0xb 472a: 00000113 li sp,0 472e: 916c 0x916c 4730: 0000 unimp - 4732: 7719 lui a4,0xfffe6 + 4732: 0b19 addi s6,s6,6 4734: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 4738: 032e slli t1,t1,0xb 473a: 0061 c.nop 24 473c: 0000 unimp - 473e: 0219 addi tp,tp,6 - 4740: 0005 c.nop 1 + 473e: 9619 srai a2,a2,0x26 + 4740: 0004 0x4 4742: 0100 addi s0,sp,128 4744: 032e slli t1,t1,0xb 4746: 0061 c.nop 24 4748: 0000 unimp - 474a: 6112 flw ft2,4(sp) - 474c: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 474a: f512 fsw ft4,168(sp) + 474c: 0002 c.slli64 zero + 474e: 0100 addi s0,sp,128 4750: 032e slli t1,t1,0xb 4752: 0061 c.nop 24 4754: 0000 unimp 4756: 917f 0x917f 4758: 0000 unimp - 475a: fd12 fsw ft4,184(sp) + 475a: 9112 add sp,sp,tp 475c: 0004 0x4 475e: 0100 addi s0,sp,128 4760: 032e slli t1,t1,0xb @@ -32221,51 +32254,52 @@ Disassembly of section .debug_info: 476c: 0c00 addi s0,sp,528 476e: 0000 unimp 4770: 00000cb7 lui s9,0x0 - 4774: 1d12 slli s10,s10,0x24 - 4776: 0006 c.slli zero,0x1 + 4774: b112 fsd ft4,160(sp) + 4776: 0005 c.nop 1 4778: 0100 addi s0,sp,128 477a: 032e slli t1,t1,0xb 477c: 00000113 li sp,0 4780: 91d9 srli a1,a1,0x36 4782: 0000 unimp - 4784: 2212 fld ft4,256(sp) - 4786: 0006 c.slli zero,0x1 + 4784: b612 fsd ft4,296(sp) + 4786: 0005 c.nop 1 4788: 0100 addi s0,sp,128 478a: 032e slli t1,t1,0xb 478c: 00000113 li sp,0 4790: 9264 0x9264 4792: 0000 unimp - 4794: 2712 fld fa4,256(sp) - 4796: 0006 c.slli zero,0x1 + 4794: bb12 fsd ft4,432(sp) + 4796: 0005 c.nop 1 4798: 0100 addi s0,sp,128 479a: 032e slli t1,t1,0xb 479c: 00000113 li sp,0 47a0: 000093e7 0x93e7 - 47a4: 2c12 fld fs8,256(sp) - 47a6: 0006 c.slli zero,0x1 + 47a4: c012 sw tp,0(sp) + 47a6: 0005 c.nop 1 47a8: 0100 addi s0,sp,128 47aa: 032e slli t1,t1,0xb 47ac: 00000113 li sp,0 47b0: 0000946f jal s0,d7b0 <_start-0x7fff2850> - 47b4: 7719 lui a4,0xfffe6 + 47b4: 0b19 addi s6,s6,6 47b6: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 47ba: 032e slli t1,t1,0xb 47bc: 0061 c.nop 24 47be: 0000 unimp - 47c0: 0219 addi tp,tp,6 - 47c2: 0005 c.nop 1 + 47c0: 9619 srai a2,a2,0x26 + 47c2: 0004 0x4 47c4: 0100 addi s0,sp,128 47c6: 032e slli t1,t1,0xb 47c8: 0061 c.nop 24 47ca: 0000 unimp - 47cc: 6112 flw ft2,4(sp) - 47ce: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 47cc: f512 fsw ft4,168(sp) + 47ce: 0002 c.slli64 zero + 47d0: 0100 addi s0,sp,128 47d2: 032e slli t1,t1,0xb 47d4: 0061 c.nop 24 47d6: 0000 unimp 47d8: 9482 jalr s1 47da: 0000 unimp - 47dc: fd12 fsw ft4,184(sp) + 47dc: 9112 add sp,sp,tp 47de: 0004 0x4 47e0: 0100 addi s0,sp,128 47e2: 032e slli t1,t1,0xb @@ -32277,51 +32311,52 @@ Disassembly of section .debug_info: 47f0: 0000 unimp 47f2: 0d39 addi s10,s10,14 47f4: 0000 unimp - 47f6: 1d12 slli s10,s10,0x24 - 47f8: 0006 c.slli zero,0x1 + 47f6: b112 fsd ft4,160(sp) + 47f8: 0005 c.nop 1 47fa: 0100 addi s0,sp,128 47fc: 032e slli t1,t1,0xb 47fe: 00000113 li sp,0 4802: 94dc 0x94dc 4804: 0000 unimp - 4806: 2212 fld ft4,256(sp) - 4808: 0006 c.slli zero,0x1 + 4806: b612 fsd ft4,296(sp) + 4808: 0005 c.nop 1 480a: 0100 addi s0,sp,128 480c: 032e slli t1,t1,0xb 480e: 00000113 li sp,0 4812: 00009567 0x9567 - 4816: 2712 fld fa4,256(sp) - 4818: 0006 c.slli zero,0x1 + 4816: bb12 fsd ft4,432(sp) + 4818: 0005 c.nop 1 481a: 0100 addi s0,sp,128 481c: 032e slli t1,t1,0xb 481e: 00000113 li sp,0 4822: 96e6 add a3,a3,s9 4824: 0000 unimp - 4826: 2c12 fld fs8,256(sp) - 4828: 0006 c.slli zero,0x1 + 4826: c012 sw tp,0(sp) + 4828: 0005 c.nop 1 482a: 0100 addi s0,sp,128 482c: 032e slli t1,t1,0xb 482e: 00000113 li sp,0 4832: 9758 0x9758 4834: 0000 unimp - 4836: 7719 lui a4,0xfffe6 + 4836: 0b19 addi s6,s6,6 4838: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 483c: 032e slli t1,t1,0xb 483e: 0061 c.nop 24 4840: 0000 unimp - 4842: 0219 addi tp,tp,6 - 4844: 0005 c.nop 1 + 4842: 9619 srai a2,a2,0x26 + 4844: 0004 0x4 4846: 0100 addi s0,sp,128 4848: 032e slli t1,t1,0xb 484a: 0061 c.nop 24 484c: 0000 unimp - 484e: 6112 flw ft2,4(sp) - 4850: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 484e: f512 fsw ft4,168(sp) + 4850: 0002 c.slli64 zero + 4852: 0100 addi s0,sp,128 4854: 032e slli t1,t1,0xb 4856: 0061 c.nop 24 4858: 0000 unimp 485a: 0000976b 0x976b - 485e: fd12 fsw ft4,184(sp) + 485e: 9112 add sp,sp,tp 4860: 0004 0x4 4862: 0100 addi s0,sp,128 4864: 032e slli t1,t1,0xb @@ -32333,51 +32368,52 @@ Disassembly of section .debug_info: 4870: 0c40 addi s0,sp,532 4872: 0000 unimp 4874: 00000dbb 0xdbb - 4878: 1d12 slli s10,s10,0x24 - 487a: 0006 c.slli zero,0x1 + 4878: b112 fsd ft4,160(sp) + 487a: 0005 c.nop 1 487c: 0100 addi s0,sp,128 487e: 032e slli t1,t1,0xb 4880: 00000113 li sp,0 4884: 97c5 srai a5,a5,0x31 4886: 0000 unimp - 4888: 2212 fld ft4,256(sp) - 488a: 0006 c.slli zero,0x1 + 4888: b612 fsd ft4,296(sp) + 488a: 0005 c.nop 1 488c: 0100 addi s0,sp,128 488e: 032e slli t1,t1,0xb 4890: 00000113 li sp,0 4894: 9850 0x9850 4896: 0000 unimp - 4898: 2712 fld fa4,256(sp) - 489a: 0006 c.slli zero,0x1 + 4898: bb12 fsd ft4,432(sp) + 489a: 0005 c.nop 1 489c: 0100 addi s0,sp,128 489e: 032e slli t1,t1,0xb 48a0: 00000113 li sp,0 48a4: 000099ef jal s3,d8a4 <_start-0x7fff275c> - 48a8: 2c12 fld fs8,256(sp) - 48aa: 0006 c.slli zero,0x1 + 48a8: c012 sw tp,0(sp) + 48aa: 0005 c.nop 1 48ac: 0100 addi s0,sp,128 48ae: 032e slli t1,t1,0xb 48b0: 00000113 li sp,0 48b4: 00009a77 0x9a77 - 48b8: 7719 lui a4,0xfffe6 + 48b8: 0b19 addi s6,s6,6 48ba: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 48be: 032e slli t1,t1,0xb 48c0: 0061 c.nop 24 48c2: 0000 unimp - 48c4: 0219 addi tp,tp,6 - 48c6: 0005 c.nop 1 + 48c4: 9619 srai a2,a2,0x26 + 48c6: 0004 0x4 48c8: 0100 addi s0,sp,128 48ca: 032e slli t1,t1,0xb 48cc: 0061 c.nop 24 48ce: 0000 unimp - 48d0: 6112 flw ft2,4(sp) - 48d2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 48d0: f512 fsw ft4,168(sp) + 48d2: 0002 c.slli64 zero + 48d4: 0100 addi s0,sp,128 48d6: 032e slli t1,t1,0xb 48d8: 0061 c.nop 24 48da: 0000 unimp 48dc: 9a8a add s5,s5,sp 48de: 0000 unimp - 48e0: fd12 fsw ft4,184(sp) + 48e0: 9112 add sp,sp,tp 48e2: 0004 0x4 48e4: 0100 addi s0,sp,128 48e6: 032e slli t1,t1,0xb @@ -32464,50 +32500,51 @@ Disassembly of section .debug_info: 49c0: 0d58 addi a4,sp,660 49c2: 0000 unimp 49c4: 00000f0b 0xf0b - 49c8: 1d12 slli s10,s10,0x24 - 49ca: 0006 c.slli zero,0x1 + 49c8: b112 fsd ft4,160(sp) + 49ca: 0005 c.nop 1 49cc: 0100 addi s0,sp,128 49ce: 032e slli t1,t1,0xb 49d0: 00000113 li sp,0 49d4: a30a fsd ft2,384(sp) 49d6: 0000 unimp - 49d8: 2212 fld ft4,256(sp) - 49da: 0006 c.slli zero,0x1 + 49d8: b612 fsd ft4,296(sp) + 49da: 0005 c.nop 1 49dc: 0100 addi s0,sp,128 49de: 032e slli t1,t1,0xb 49e0: 00000113 li sp,0 49e4: a328 fsd fa0,64(a4) 49e6: 0000 unimp - 49e8: 2712 fld fa4,256(sp) - 49ea: 0006 c.slli zero,0x1 + 49e8: bb12 fsd ft4,432(sp) + 49ea: 0005 c.nop 1 49ec: 0100 addi s0,sp,128 49ee: 032e slli t1,t1,0xb 49f0: 00000113 li sp,0 - 49f4: 0000a3bf 00062c12 0x62c120000a3bf + 49f4: 0000a3bf 0005c012 0x5c0120000a3bf 49fc: 0100 addi s0,sp,128 49fe: 032e slli t1,t1,0xb 4a00: 00000113 li sp,0 4a04: a3dd j 4fea <_start-0x7fffb016> 4a06: 0000 unimp - 4a08: 7719 lui a4,0xfffe6 + 4a08: 0b19 addi s6,s6,6 4a0a: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 4a0e: 032e slli t1,t1,0xb 4a10: 0061 c.nop 24 4a12: 0000 unimp - 4a14: 0219 addi tp,tp,6 - 4a16: 0005 c.nop 1 + 4a14: 9619 srai a2,a2,0x26 + 4a16: 0004 0x4 4a18: 0100 addi s0,sp,128 4a1a: 032e slli t1,t1,0xb 4a1c: 0061 c.nop 24 4a1e: 0000 unimp - 4a20: 6112 flw ft2,4(sp) - 4a22: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> + 4a20: f512 fsw ft4,168(sp) + 4a22: 0002 c.slli64 zero + 4a24: 0100 addi s0,sp,128 4a26: 032e slli t1,t1,0xb 4a28: 0061 c.nop 24 4a2a: 0000 unimp 4a2c: a3f0 fsd fa2,192(a5) 4a2e: 0000 unimp - 4a30: fd12 fsw ft4,184(sp) + 4a30: 9112 add sp,sp,tp 4a32: 0004 0x4 4a34: 0100 addi s0,sp,128 4a36: 032e slli t1,t1,0xb @@ -32561,7 +32598,7 @@ Disassembly of section .debug_info: 4aaa: 00a4 addi s1,sp,72 4aac: 0000 unimp 4aae: 1a00 addi s0,sp,304 - 4ab0: 27b4 fld fa3,72(a5) + 4ab0: 2878 fld fa4,208(s0) 4ab2: 8001 c.srli64 s0 4ab4: 0048 addi a0,sp,4 4ab6: 0000 unimp @@ -32573,7 +32610,7 @@ Disassembly of section .debug_info: 4ac2: 032e slli t1,t1,0xb 4ac4: 0025 c.nop 9 4ac6: 0000 unimp - 4ac8: 0127b41b 0x127b41b + 4ac8: 0128781b 0x128781b 4acc: 3c80 fld fs0,56(s1) 4ace: 0000 unimp 4ad0: 1200 addi s0,sp,288 @@ -32612,7 +32649,7 @@ Disassembly of section .debug_info: 4b1e: 00a5 addi ra,ra,9 4b20: 0000 unimp 4b22: 1a00 addi s0,sp,304 - 4b24: 2828 fld fa0,80(s0) + 4b24: 28ec fld fa1,208(s1) 4b26: 8001 c.srli64 s0 4b28: 0038 addi a4,sp,8 4b2a: 0000 unimp @@ -32674,7 +32711,7 @@ Disassembly of section .debug_info: 4bb2: 0000 unimp 4bb4: 1221 addi tp,tp,-24 4bb6: 0000 unimp - 4bb8: 6a19 lui s4,0x6 + 4bb8: 6519 lui a0,0x6 4bba: 0009 c.nop 2 4bbc: 0100 addi s0,sp,128 4bbe: 0025032f 0x25032f @@ -32682,12 +32719,13 @@ Disassembly of section .debug_info: 4bc4: f61c fsw fa5,40(a2) 4bc6: 0010 0x10 4bc8: 1900 addi s0,sp,176 - 4bca: 0985 addi s3,s3,1 + 4bca: 0980 addi s0,sp,208 4bcc: 0000 unimp 4bce: 2f01 jal 52de <_start-0x7fffad22> 4bd0: 00123803 0x123803 4bd4: 1900 addi s0,sp,176 - 4bd6: 00000953 fadd.s fs2,ft0,ft0,rne + 4bd6: 094e slli s2,s2,0x13 + 4bd8: 0000 unimp 4bda: 2f01 jal 52ea <_start-0x7fffad16> 4bdc: 00123803 0x123803 4be0: 1900 addi s0,sp,176 @@ -32718,8 +32756,8 @@ Disassembly of section .debug_info: 4c24: 0113032f 0x113032f 4c28: 0000 unimp 4c2a: 0000 unimp - 4c2c: fc1a fsw ft6,56(sp) - 4c2e: 0129 addi sp,sp,10 + 4c2c: c01a sw t1,0(sp) + 4c2e: 012a slli sp,sp,0xa 4c30: 2880 fld fs0,16(s1) 4c32: 0001 nop 4c34: 6a00 flw fs0,16(a2) @@ -32769,7 +32807,7 @@ Disassembly of section .debug_info: 4c9a: a96e fsd fs11,144(sp) 4c9c: 0000 unimp 4c9e: 0000 unimp - 4ca0: 341a fld fs0,416(sp) + 4ca0: f81a fsw ft6,48(sp) 4ca2: 3880012b 0x3880012b 4ca6: 0000 unimp 4ca8: 8800 0x8800 @@ -32798,8 +32836,9 @@ Disassembly of section .debug_info: 4cda: 2f01 jal 53ea <_start-0x7fffac16> 4cdc: 00011303 lh t1,0(sp) 4ce0: 0000 unimp - 4ce2: 981a add a6,a6,t1 - 4ce4: 2c80012b 0x2c80012b + 4ce2: 5c1a lw s8,164(sp) + 4ce4: 012c addi a1,sp,136 + 4ce6: 2c80 fld fs0,24(s1) 4ce8: 0000 unimp 4cea: ee00 fsw fs0,24(a2) 4cec: 0011 c.nop 4 @@ -32857,7 +32896,7 @@ Disassembly of section .debug_info: 4d66: 0000 unimp 4d68: 7fa09103 lh sp,2042(ra) 4d6c: 0000 unimp - 4d6e: c7050403 lb s0,-912(a0) # 1cc70 <_start-0x7ffe3390> + 4d6e: 5b050403 lb s0,1456(a0) # 65b0 <_start-0x7fff9a50> 4d72: 0004 0x4 4d74: 0600 addi s0,sp,768 4d76: 00000113 li sp,0 @@ -32878,13 +32917,13 @@ Disassembly of section .debug_info: 4da0: 0000 unimp 4da2: 0b0c addi a1,sp,400 4da4: 0010 0x10 - 4da6: 9400 0x9400 - 4da8: 0001 nop - 4daa: 4000 lw s0,0(s0) - 4dac: 012c addi a1,sp,136 + 4da6: ed00 fsw fs0,24(a0) + 4da8: 0005 c.nop 1 + 4daa: 0400 addi s0,sp,512 + 4dac: 012d addi sp,sp,11 4dae: 2080 fld fs0,0(s1) 4db0: 0015 c.nop 5 - 4db2: f000 fsw fs0,32(s0) + 4db2: 9c00 0x9c00 4db4: 005d c.nop 23 4db6: 0200 addi s0,sp,256 4db8: 0504 addi s1,sp,640 @@ -32894,7 +32933,7 @@ Disassembly of section .debug_info: 4dc2: 0006 c.slli zero,0x1 4dc4: 0300 addi s0,sp,384 4dc6: 0508 addi a0,sp,640 - 4dc8: 04c2 slli s1,s1,0x10 + 4dc8: 0456 slli s0,s0,0x15 4dca: 0000 unimp 4dcc: c304 sw s1,0(a4) 4dce: 02000007 0x2000007 @@ -32904,17 +32943,17 @@ Disassembly of section .debug_info: 4dd8: 0500 addi s0,sp,640 4dda: 003a c.slli zero,0xe 4ddc: 0000 unimp - 4dde: b7080103 lb sp,-1168(a6) # fffe5b70 <__BSS_END__+0x7ffcef40> + 4dde: b7080103 lb sp,-1168(a6) # fffe5b70 <__BSS_END__+0x7ffcef34> 4de2: 0006 c.slli zero,0x1 4de4: 0300 addi s0,sp,384 4de6: 0704 addi s1,sp,896 - 4de8: 02e2 slli t0,t0,0x18 + 4de8: 0276 slli tp,tp,0x1d 4dea: 0000 unimp - 4dec: d8070803 lb a6,-640(a4) # fffe5d80 <__BSS_END__+0x7ffcf150> + 4dec: 6c070803 lb a6,1728(a4) 4df0: 0002 c.slli64 zero 4df2: 0300 addi s0,sp,384 4df4: 0702 c.slli64 a4 - 4df6: 02f8 addi a4,sp,332 + 4df6: 028c addi a1,sp,320 4df8: 0000 unimp 4dfa: 4706 lw a4,64(sp) 4dfc: 0000 unimp @@ -32926,8 +32965,7 @@ Disassembly of section .debug_info: 4e0a: 6805 lui a6,0x1 4e0c: 0000 unimp 4e0e: 0800 addi s0,sp,16 - 4e10: 0000030b 0x30b - 4e14: 3c04 fld fs1,56(s0) + 4e10: 029f 0000 3c04 0x3c040000029f 4e16: 7816 flw fa6,100(sp) 4e18: 0000 unimp 4e1a: 0900 addi s0,sp,144 @@ -32977,13 +33015,13 @@ Disassembly of section .debug_info: 4e80: 0000 unimp 4e82: 0400 addi s0,sp,512 4e84: 0b0c010f 0xb0c010f - 4e88: 0000024f fnmadd.s ft4,ft0,ft0,ft0,rne + 4e88: 000001e3 beqz zero,568a <_start-0x7fffa976> 4e8c: 530e5e03 lhu t3,1328(t3) 4e90: 0000 unimp 4e92: 0400 addi s0,sp,512 4e94: 0001 nop 4e96: 000c 0xc - 4e98: dd070403 lb s0,-560(a4) + 4e98: 71070403 lb s0,1808(a4) 4e9c: 0002 c.slli64 zero 4e9e: 0d00 addi s0,sp,656 4ea0: 0c7e slli s8,s8,0x1f @@ -33008,8 +33046,8 @@ Disassembly of section .debug_info: 4eca: 2301 jal 53ca <_start-0x7fffac36> 4ecc: 8901 andi a0,a0,0 4ece: 0000 unimp - 4ed0: 4000 lw s0,0(s0) - 4ed2: 012c addi a1,sp,136 + 4ed0: 0400 addi s0,sp,512 + 4ed2: 012d addi sp,sp,11 4ed4: 2080 fld fs0,0(s1) 4ed6: 0015 c.nop 5 4ed8: 0100 addi s0,sp,128 @@ -33026,7 +33064,8 @@ Disassembly of section .debug_info: 4eee: 891c 0x891c 4ef0: 0000 unimp 4ef2: 1200 addi s0,sp,288 - 4ef4: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> + 4ef4: 08fe slli a7,a7,0x1f + 4ef6: 0000 unimp 4ef8: 2501 jal 54f8 <_start-0x7fffab08> 4efa: 00002503 lw a0,0(zero) # 0 <_start-0x80000000> 4efe: 1b00 addi s0,sp,432 @@ -33181,21 +33220,21 @@ Disassembly of section .debug_info: 5092: 1118 addi a4,sp,160 5094: 0000 unimp 5096: 2e01 jal 53a6 <_start-0x7fffac5a> - 5098: 012fd803 lhu a6,18(t6) + 5098: 01309c03 lh s8,19(ra) 509c: 1980 addi s0,sp,240 509e: 0fde slli t6,t6,0x17 50a0: 0000 unimp 50a2: 2e01 jal 53b2 <_start-0x7fffac4e> - 50a4: 0132dc03 lhu s8,19(t0) # b013 <_start-0x7fff4fed> + 50a4: 0133a003 lw zero,19(t2) 50a8: 1980 addi s0,sp,240 50aa: 111d addi sp,sp,-25 50ac: 0000 unimp 50ae: 2e01 jal 53be <_start-0x7fffac42> - 50b0: 01315403 lhu s0,19(sp) + 50b0: 01321803 lh a6,19(tp) # fffe5013 <__BSS_END__+0x7ffce3d7> 50b4: 1980 addi s0,sp,240 50b6: 00000fe3 beqz zero,58d4 <_start-0x7fffa72c> 50ba: 2e01 jal 53ca <_start-0x7fffac36> - 50bc: 012e7003 0x12e7003 + 50bc: 012f3403 0x12f3403 50c0: 1280 addi s0,sp,352 50c2: 10e5 addi ra,ra,-7 50c4: 0000 unimp @@ -33204,7 +33243,7 @@ Disassembly of section .debug_info: 50cc: a400 fsd fs0,8(s0) 50ce: 00b1 addi ra,ra,12 50d0: 1a00 addi s0,sp,304 - 50d2: 2ddc fld fa5,152(a1) + 50d2: 2ea0 fld fs0,88(a3) 50d4: 8001 c.srli64 s0 50d6: 0048 addi a0,sp,4 50d8: 0000 unimp @@ -33235,7 +33274,7 @@ Disassembly of section .debug_info: 510a: b3be fsd fa5,480(sp) 510c: 0000 unimp 510e: 1a00 addi s0,sp,304 - 5110: 2fe4 fld fs1,216(a5) + 5110: 30a8 fld fa0,96(s1) 5112: 8001 c.srli64 s0 5114: 0114 addi a3,sp,128 5116: 0000 unimp @@ -33286,7 +33325,7 @@ Disassembly of section .debug_info: 517e: 00b5 addi ra,ra,13 5180: 0000 unimp 5182: 1a00 addi s0,sp,304 - 5184: 30fc fld fa5,224(s1) + 5184: 31c0 fld fs0,160(a1) 5186: 8001 c.srli64 s0 5188: 0058 addi a4,sp,4 518a: 0000 unimp @@ -33316,7 +33355,7 @@ Disassembly of section .debug_info: 51bc: b5ec fsd fa1,232(a1) 51be: 0000 unimp 51c0: 1a00 addi s0,sp,304 - 51c2: 3234 fld fa3,96(a2) + 51c2: 32f8 fld fa4,224(a3) 51c4: 8001 c.srli64 s0 51c6: 004c addi a1,sp,4 51c8: 0000 unimp @@ -33345,7 +33384,7 @@ Disassembly of section .debug_info: 51f8: 0000 unimp 51fa: 0000b6bb 0xb6bb 51fe: 1a00 addi s0,sp,304 - 5200: 32e8 fld fa0,224(a3) + 5200: 33ac fld fa1,96(a5) 5202: 8001 c.srli64 s0 5204: 0128 addi a0,sp,136 5206: 0000 unimp @@ -33491,7 +33530,7 @@ Disassembly of section .debug_info: 5348: 032e slli t1,t1,0xb 534a: 00000df7 0xdf7 534e: 1a00 addi s0,sp,304 - 5350: 35a4 fld fs1,104(a1) + 5350: 3668 fld fa0,232(a2) 5352: 8001 c.srli64 s0 5354: 0024 addi s1,sp,8 5356: 0000 unimp @@ -33524,7 +33563,7 @@ Disassembly of section .debug_info: 5398: ba22 fsd fs0,304(sp) 539a: 0000 unimp 539c: 1a00 addi s0,sp,304 - 539e: 35e4 fld fs1,232(a1) + 539e: 36a8 fld fa0,104(a3) 53a0: 8001 c.srli64 s0 53a2: 0048 addi a0,sp,4 53a4: 0000 unimp @@ -33652,27 +33691,27 @@ Disassembly of section .debug_info: 54c2: 1006 c.slli zero,0x21 54c4: 0000 unimp 54c6: 2e01 jal 57d6 <_start-0x7fffa82a> - 54c8: 01378c03 lb s8,19(a5) # fffe3013 <__BSS_END__+0x7ffcc3e3> + 54c8: 01385003 lhu zero,19(a6) # 1064cb <_start-0x7fef9b35> 54cc: 1980 addi s0,sp,240 54ce: 0fec addi a1,sp,988 54d0: 0000 unimp 54d2: 2e01 jal 57e2 <_start-0x7fffa81e> - 54d4: 013a4c03 lbu s8,19(s4) # 6013 <_start-0x7fff9fed> + 54d4: 013b1003 lh zero,19(s6) # 5f6a5 <_start-0x7ffa095b> 54d8: 1980 addi s0,sp,240 54da: 10e0 addi s0,sp,108 54dc: 0000 unimp 54de: 2e01 jal 57ee <_start-0x7fffa812> - 54e0: 01392003 lw zero,19(s2) # 82297 <_start-0x7ff7dd69> + 54e0: 0139e403 0x139e403 54e4: 1980 addi s0,sp,240 54e6: 1122 slli sp,sp,0x28 54e8: 0000 unimp 54ea: 2e01 jal 57fa <_start-0x7fffa806> - 54ec: 013ebc03 0x13ebc03 + 54ec: 013f8003 lb zero,19(t6) 54f0: 1980 addi s0,sp,240 54f2: 10fc addi a5,sp,108 54f4: 0000 unimp 54f6: 2e01 jal 5806 <_start-0x7fffa7fa> - 54f8: 012e7003 0x12e7003 + 54f8: 012f3403 0x12f3403 54fc: 1280 addi s0,sp,352 54fe: 10e5 addi ra,ra,-7 5500: 0000 unimp @@ -33681,7 +33720,7 @@ Disassembly of section .debug_info: 5508: 6f00 flw fs0,24(a4) 550a: 00bc addi a5,sp,72 550c: 1a00 addi s0,sp,304 - 550e: 36d0 fld fa2,168(a3) + 550e: 3794 fld fa3,40(a5) 5510: 8001 c.srli64 s0 5512: 005c addi a5,sp,4 5514: 0000 unimp @@ -33717,7 +33756,7 @@ Disassembly of section .debug_info: 5554: 0000 unimp 5556: 0000bec3 fmadd.s ft9,ft1,ft0,ft0,rup 555a: 1a00 addi s0,sp,304 - 555c: 3798 fld fa4,40(a5) + 555c: 385c fld fa5,176(s0) 555e: 8001 c.srli64 s0 5560: 0114 addi a3,sp,128 5562: 0000 unimp @@ -33757,7 +33796,7 @@ Disassembly of section .debug_info: 55ca: 00c0 addi s0,sp,68 55cc: 0000 unimp 55ce: 1a00 addi s0,sp,304 - 55d0: 38b0 fld fa2,112(s1) + 55d0: 3974 fld fa3,240(a0) 55d2: 8001 c.srli64 s0 55d4: 0070 addi a2,sp,12 55d6: 0000 unimp @@ -33792,7 +33831,7 @@ Disassembly of section .debug_info: 5618: c11a sw t1,128(sp) 561a: 0000 unimp 561c: 1a00 addi s0,sp,304 - 561e: 3998 fld fa4,48(a1) + 561e: 3a5c fld fa5,176(a2) 5620: 8001 c.srli64 s0 5622: 005c addi a5,sp,4 5624: 0000 unimp @@ -33829,7 +33868,7 @@ Disassembly of section .debug_info: 5666: c212 sw tp,4(sp) 5668: 0000 unimp 566a: 1a00 addi s0,sp,304 - 566c: 3a54 fld fa3,176(a2) + 566c: 3b18 fld fa4,48(a4) 566e: 8001 c.srli64 s0 5670: 0128 addi a0,sp,136 5672: 0000 unimp @@ -33879,7 +33918,7 @@ Disassembly of section .debug_info: 56d8: a900 fsd fs0,16(a0) 56da: 000000c3 fmadd.s ft1,ft0,ft0,ft0,rne 56de: 1a00 addi s0,sp,304 - 56e0: 3b80 fld fs0,48(a5) + 56e0: 3c44 fld fs1,184(s0) 56e2: 8001 c.srli64 s0 56e4: 0070 addi a2,sp,12 56e6: 0000 unimp @@ -33915,7 +33954,7 @@ Disassembly of section .debug_info: 5728: c492 sw tp,72(sp) 572a: 0000 unimp 572c: 1a00 addi s0,sp,304 - 572e: 3c88 fld fa0,56(s1) + 572e: 3d4c fld fa1,184(a0) 5730: 8001 c.srli64 s0 5732: 0058 addi a4,sp,4 5734: 0000 unimp @@ -33951,7 +33990,7 @@ Disassembly of section .debug_info: 5774: 0000 unimp 5776: 0000c657 0xc657 577a: 1a00 addi s0,sp,304 - 577c: 3ce8 fld fa0,248(s1) + 577c: 3dac fld fa1,120(a1) 577e: 8001 c.srli64 s0 5780: 005c addi a5,sp,4 5782: 0000 unimp @@ -33986,7 +34025,7 @@ Disassembly of section .debug_info: 57c4: c724 sw s1,72(a4) 57c6: 0000 unimp 57c8: 1a00 addi s0,sp,304 - 57ca: 3d70 fld fa2,248(a0) + 57ca: 3e34 fld fa3,120(a2) 57cc: 8001 c.srli64 s0 57ce: 0028 addi a0,sp,8 57d0: 0000 unimp @@ -34096,7 +34135,7 @@ Disassembly of section .debug_info: 58c8: c7de sw s7,204(sp) 58ca: 0000 unimp 58cc: 1a00 addi s0,sp,304 - 58ce: 3e04 fld fs1,56(a2) + 58ce: 3ec8 fld fa0,184(a3) 58d0: 8001 c.srli64 s0 58d2: 0058 addi a4,sp,4 58d4: 0000 unimp @@ -34133,7 +34172,7 @@ Disassembly of section .debug_info: 5916: c996 sw t0,208(sp) 5918: 0000 unimp 591a: 1a00 addi s0,sp,304 - 591c: 3e64 fld fs1,248(a2) + 591c: 3f28 fld fa0,120(a4) 591e: 8001 c.srli64 s0 5920: 0054 addi a3,sp,4 5922: 0000 unimp @@ -34329,7 +34368,7 @@ Disassembly of section .debug_info: 5ae2: 00010603 lb a2,0(sp) 5ae6: 0000 unimp 5ae8: 1a00 addi s0,sp,304 - 5aea: 2e88 fld fa0,24(a3) + 5aea: 2f4c fld fa1,152(a4) 5aec: 8001 c.srli64 s0 5aee: 0038 addi a4,sp,8 5af0: 0000 unimp @@ -34397,7 +34436,7 @@ Disassembly of section .debug_info: 5b86: 007f 0x7f 5b88: 0300 addi s0,sp,384 5b8a: 0504 addi s1,sp,640 - 5b8c: 000004c7 fmsub.s fs1,ft0,ft0,ft0,rne + 5b8c: 0000045b 0x45b 5b90: 0606 slli a2,a2,0x1 5b92: 0001 nop 5b94: 0e00 addi s0,sp,784 @@ -34420,13 +34459,13 @@ Disassembly of section .debug_info: 5bbc: 0c00 addi s0,sp,528 5bbe: 114d addi sp,sp,-13 5bc0: 0000 unimp - 5bc2: 0194 addi a3,sp,192 + 5bc2: 05ed addi a1,a1,27 5bc4: 0000 unimp - 5bc6: 4160 lw s0,68(a0) + 5bc6: 4224 lw s1,64(a2) 5bc8: 8001 c.srli64 s0 5bca: 0114 addi a3,sp,128 5bcc: 0000 unimp - 5bce: 8619 srai a2,a2,0x6 + 5bce: 85c5 srai a1,a1,0x11 5bd0: 0000 unimp 5bd2: 0402 c.slli64 s0 5bd4: 6905 lui s2,0x1 @@ -34443,7 +34482,7 @@ Disassembly of section .debug_info: 5bea: 0000 unimp 5bec: 0300 addi s0,sp,384 5bee: 0508 addi a0,sp,640 - 5bf0: 04c2 slli s1,s1,0x10 + 5bf0: 0456 slli s0,s0,0x15 5bf2: 0000 unimp 5bf4: c304 sw s1,0(a4) 5bf6: 02000007 0x2000007 @@ -34452,7 +34491,7 @@ Disassembly of section .debug_info: 5bfe: 0000 unimp 5c00: 0500 addi s0,sp,640 5c02: 00000047 fmsub.s ft0,ft0,ft0,ft0,rne - 5c06: b7080103 lb sp,-1168(a6) # 106028 <_start-0x7fef9fd8> + 5c06: b7080103 lb sp,-1168(a6) 5c0a: 0006 c.slli zero,0x1 5c0c: 0400 addi s0,sp,512 5c0e: 0174 addi a3,sp,140 @@ -34461,13 +34500,13 @@ Disassembly of section .debug_info: 5c14: 1601 addi a2,a2,-32 5c16: 006d c.nop 27 5c18: 0000 unimp - 5c1a: e2070403 lb s0,-480(a4) + 5c1a: 76070403 lb s0,1888(a4) 5c1e: 0002 c.slli64 zero 5c20: 0300 addi s0,sp,384 5c22: 0708 addi a0,sp,896 - 5c24: 02d8 addi a4,sp,324 + 5c24: 026c addi a1,sp,268 5c26: 0000 unimp - 5c28: f8070203 lb tp,-128(a4) + 5c28: 8c070203 lb tp,-1856(a4) 5c2c: 0002 c.slli64 zero 5c2e: 0600 addi s0,sp,768 5c30: 0054 addi a3,sp,4 @@ -34479,8 +34518,9 @@ Disassembly of section .debug_info: 5c3e: 0500 addi s0,sp,640 5c40: 0082 c.slli64 ra 5c42: 0000 unimp - 5c44: 0b08 addi a0,sp,400 - 5c46: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> + 5c44: 9f08 0x9f08 + 5c46: 0002 c.slli64 zero + 5c48: 0400 addi s0,sp,512 5c4a: 163c addi a5,sp,808 5c4c: 0092 slli ra,ra,0x4 5c4e: 0000 unimp @@ -34530,7 +34570,7 @@ Disassembly of section .debug_info: 5cb6: 0000 unimp 5cb8: 0f04 addi s1,sp,912 5cba: 0c01 addi s8,s8,0 - 5cbc: 00024f0b 0x24f0b + 5cbc: 0001e30b 0x1e30b 5cc0: 0300 addi s0,sp,384 5cc2: 0e5e slli t3,t3,0x17 5cc4: 006d c.nop 27 @@ -34539,7 +34579,7 @@ Disassembly of section .debug_info: 5cca: 0c00 addi s0,sp,528 5ccc: 0300 addi s0,sp,384 5cce: 0704 addi s1,sp,896 - 5cd0: 02dd addi t0,t0,23 + 5cd0: 0271 addi tp,tp,28 5cd2: 0000 unimp 5cd4: 7e0d lui t3,0xfffe3 5cd6: 000c 0xc @@ -34549,7 +34589,7 @@ Disassembly of section .debug_info: 5ce0: 0e00 addi s0,sp,784 5ce2: 6c66 flw fs8,88(sp) 5ce4: 0074 addi a3,sp,12 - 5ce6: a30a4e03 lbu t3,-1488(s4) # fffffa30 <__BSS_END__+0x7ffe8e00> + 5ce6: a30a4e03 lbu t3,-1488(s4) # fffffa30 <__BSS_END__+0x7ffe8df4> 5cea: 0000 unimp 5cec: 0f00 addi s0,sp,912 5cee: 00000a97 auipc s5,0x0 @@ -34561,7 +34601,7 @@ Disassembly of section .debug_info: 5cfe: 0100 addi s0,sp,128 5d00: 00330123 sb gp,2(t1) 5d04: 0000 unimp - 5d06: 4160 lw s0,68(a0) + 5d06: 4224 lw s1,64(a2) 5d08: 8001 c.srli64 s0 5d0a: 0114 addi a3,sp,128 5d0c: 0000 unimp @@ -34572,8 +34612,8 @@ Disassembly of section .debug_info: 5d16: 0100 addi s0,sp,128 5d18: 00a31323 sh a0,6(t1) 5d1c: 0000 unimp - 5d1e: 0312 slli t1,t1,0x4 - 5d20: 0009 c.nop 2 + 5d1e: fe12 fsw ft4,60(sp) + 5d20: 0008 0x8 5d22: 0100 addi s0,sp,128 5d24: 0325 addi t1,t1,9 5d26: 0025 c.nop 9 @@ -34588,7 +34628,7 @@ Disassembly of section .debug_info: 5d3a: 1400 addi s0,sp,544 5d3c: 5f41 li t5,-16 5d3e: 26010063 beqz sp,5f9e <_start-0x7fffa062> - 5d42: 0002a903 lw s2,0(t0) + 5d42: 0002a903 lw s2,0(t0) # b000 <_start-0x7fff5000> 5d46: 1500 addi s0,sp,672 5d48: 5f41 li t5,-16 5d4a: 26010073 0x26010073 @@ -34700,7 +34740,7 @@ Disassembly of section .debug_info: 5e4e: 00012003 lw zero,0(sp) 5e52: 0000 unimp 5e54: 0000 unimp - 5e56: c7050403 lb s0,-912(a0) + 5e56: 5b050403 lb s0,1456(a0) 5e5a: 0004 0x4 5e5c: 1d00 addi s0,sp,688 5e5e: 0120 addi s0,sp,136 @@ -34718,13 +34758,12 @@ Disassembly of section .debug_info: 5e78: 0000 unimp 5e7a: 860c 0x860c 5e7c: 0011 c.nop 4 - 5e7e: 9400 0x9400 - 5e80: 0001 nop - 5e82: 7400 flw fs0,40(s0) - 5e84: 0142 slli sp,sp,0x10 - 5e86: 5080 lw s0,32(s1) + 5e7e: ed00 fsw fs0,24(a0) + 5e80: 0005 c.nop 1 + 5e82: 3800 fld fs0,48(s0) + 5e84: 50800143 fmadd.s ft2,ft0,fs0,fa0,rne 5e88: 0001 nop - 5e8a: 5900 lw s0,48(a0) + 5e8a: 0500 addi s0,sp,640 5e8c: 0089 addi ra,ra,2 5e8e: 0200 addi s0,sp,256 5e90: 0504 addi s1,sp,640 @@ -34739,7 +34778,7 @@ Disassembly of section .debug_info: 5ea4: 0d01 addi s10,s10,0 5ea6: 0025 c.nop 9 5ea8: 0000 unimp - 5eaa: c2050803 lb a6,-992(a0) + 5eaa: 56050803 lb a6,1376(a0) 5eae: 0004 0x4 5eb0: 0400 addi s0,sp,512 5eb2: 000007c3 fmadd.s fa5,ft0,ft0,ft0,rne @@ -34759,13 +34798,13 @@ Disassembly of section .debug_info: 5ed4: 0000 unimp 5ed6: 0300 addi s0,sp,384 5ed8: 0704 addi s1,sp,896 - 5eda: 02e2 slli t0,t0,0x18 + 5eda: 0276 slli tp,tp,0x1d 5edc: 0000 unimp - 5ede: d8070803 lb a6,-640(a4) + 5ede: 6c070803 lb a6,1728(a4) 5ee2: 0002 c.slli64 zero 5ee4: 0300 addi s0,sp,384 5ee6: 0702 c.slli64 a4 - 5ee8: 02f8 addi a4,sp,332 + 5ee8: 028c addi a1,sp,320 5eea: 0000 unimp 5eec: 5406 lw s0,96(sp) 5eee: 0000 unimp @@ -34778,8 +34817,7 @@ Disassembly of section .debug_info: 5efc: 8205 srli a2,a2,0x1 5efe: 0000 unimp 5f00: 0800 addi s0,sp,16 - 5f02: 0000030b 0x30b - 5f06: 3c04 fld fs1,56(s0) + 5f02: 029f 0000 3c04 0x3c040000029f 5f08: 9216 add tp,tp,t0 5f0a: 0000 unimp 5f0c: 0900 addi s0,sp,144 @@ -34829,13 +34867,13 @@ Disassembly of section .debug_info: 5f72: 0000 unimp 5f74: 0400 addi s0,sp,512 5f76: 0b0c010f 0xb0c010f - 5f7a: 0000024f fnmadd.s ft4,ft0,ft0,ft0,rne + 5f7a: 000001e3 beqz zero,677c <_start-0x7fff9884> 5f7e: 6d0e5e03 lhu t3,1744(t3) 5f82: 0000 unimp 5f84: 0400 addi s0,sp,512 5f86: 0001 nop 5f88: 000c 0xc - 5f8a: dd070403 lb s0,-560(a4) + 5f8a: 71070403 lb s0,1808(a4) 5f8e: 0002 c.slli64 zero 5f90: 0d00 addi s0,sp,656 5f92: 0c7e slli s8,s8,0x1f @@ -34860,9 +34898,8 @@ Disassembly of section .debug_info: 5fbc: 2401 jal 61bc <_start-0x7fff9e44> 5fbe: a301 j 64be <_start-0x7fff9b42> 5fc0: 0000 unimp - 5fc2: 7400 flw fs0,40(s0) - 5fc4: 0142 slli sp,sp,0x10 - 5fc6: 5080 lw s0,32(s1) + 5fc2: 3800 fld fs0,48(s0) + 5fc4: 50800143 fmadd.s ft2,ft0,fs0,fa0,rne 5fc8: 0001 nop 5fca: 0100 addi s0,sp,128 5fcc: aa9c fsd fa5,16(a3) @@ -35109,7 +35146,7 @@ Disassembly of section .debug_info: 620e: 0200 addi s0,sp,256 6210: 5091 li ra,-28 6212: 0000 unimp - 6214: c7050403 lb s0,-912(a0) + 6214: 5b050403 lb s0,1456(a0) 6218: 0004 0x4 621a: 1d00 addi s0,sp,688 621c: 0120 addi s0,sp,136 @@ -35127,12 +35164,13 @@ Disassembly of section .debug_info: 6236: 0000 unimp 6238: fd0c fsw fa1,56(a0) 623a: 0011 c.nop 4 - 623c: 9400 0x9400 - 623e: 0001 nop - 6240: c400 sw s0,8(s0) - 6242: f4800143 0xf4800143 + 623c: ed00 fsw fs0,24(a0) + 623e: 0005 c.nop 1 + 6240: 8800 0x8800 + 6242: 0144 addi s1,sp,132 + 6244: f480 fsw fs0,40(s1) 6246: 0001 nop - 6248: f600 fsw fs0,40(a2) + 6248: a200 fsd fs0,0(a2) 624a: 008c addi a1,sp,64 624c: 0200 addi s0,sp,256 624e: 0408 addi a0,sp,512 @@ -35145,7 +35183,7 @@ Disassembly of section .debug_info: 625e: 06b9 addi a3,a3,14 6260: 0000 unimp 6262: 0802 c.slli64 a6 - 6264: c205 beqz a2,6284 <_start-0x7fff9d7c> + 6264: 5605 li a2,-31 6266: 0004 0x4 6268: 0400 addi s0,sp,512 626a: 000007c3 fmadd.s fa5,ft0,ft0,ft0,rne @@ -35158,13 +35196,13 @@ Disassembly of section .debug_info: 627c: 0801 addi a6,a6,0 627e: 000006b7 lui a3,0x0 6282: 0402 c.slli64 s0 - 6284: 0002e207 0x2e207 + 6284: 00027607 0x27607 6288: 0200 addi s0,sp,256 628a: 0708 addi a0,sp,896 - 628c: 02d8 addi a4,sp,324 + 628c: 026c addi a1,sp,268 628e: 0000 unimp 6290: 0202 c.slli64 tp - 6292: 0002f807 0x2f807 + 6292: 00028c07 0x28c07 6296: 0600 addi s0,sp,768 6298: 004e c.slli zero,0x13 629a: 0000 unimp @@ -35174,8 +35212,9 @@ Disassembly of section .debug_info: 62a4: ff00 fsw fs0,56(a4) 62a6: 0500 addi s0,sp,640 62a8: 0000006f j 62a8 <_start-0x7fff9d58> - 62ac: 0b08 addi a0,sp,400 - 62ae: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> + 62ac: 9f08 0x9f08 + 62ae: 0002 c.slli64 zero + 62b0: 0500 addi s0,sp,640 62b2: 163c addi a5,sp,808 62b4: 007f 0x7f 62b6: 0000 unimp @@ -35191,7 +35230,7 @@ Disassembly of section .debug_info: 62cc: 0b00 addi s0,sp,400 62ce: 086c addi a1,sp,28 62d0: 0000 unimp - 62d2: 5a0e5703 lhu a4,1440(t3) # fffe65a0 <__BSS_END__+0x7ffcf970> + 62d2: 5a0e5703 lhu a4,1440(t3) # fffe65a0 <__BSS_END__+0x7ffcf964> 62d6: 0000 unimp 62d8: 0400 addi s0,sp,512 62da: 0020 addi s0,sp,8 @@ -35209,7 +35248,7 @@ Disassembly of section .debug_info: 62f6: 0000 unimp 62f8: 0400 addi s0,sp,512 62fa: 0b04010b 0xb04010b - 62fe: 0000024f fnmadd.s ft4,ft0,ft0,ft0,rne + 62fe: 000001e3 beqz zero,6b00 <_start-0x7fff9500> 6302: 5a0e5a03 lhu s4,1440(t3) 6306: 0000 unimp 6308: 0400 addi s0,sp,512 @@ -35278,7 +35317,7 @@ Disassembly of section .debug_info: 639a: 0000 unimp 639c: 0f04 addi s1,sp,912 639e: 0c01 addi s8,s8,0 - 63a0: 00024f0b 0x24f0b + 63a0: 0001e30b 0x1e30b 63a4: 0400 addi s0,sp,512 63a6: 0e5e slli t3,t3,0x17 63a8: 005a c.slli zero,0x16 @@ -35287,7 +35326,7 @@ Disassembly of section .debug_info: 63ae: 0c00 addi s0,sp,528 63b0: 0200 addi s0,sp,256 63b2: 0704 addi s1,sp,896 - 63b4: 02dd addi t0,t0,23 + 63b4: 0271 addi tp,tp,28 63b6: 0000 unimp 63b8: 7e0d lui t3,0xfffe3 63ba: 000c 0xc @@ -35312,7 +35351,7 @@ Disassembly of section .debug_info: 63e4: 0125 addi sp,sp,9 63e6: 010c addi a1,sp,128 63e8: 0000 unimp - 63ea: 43c4 lw s1,4(a5) + 63ea: 4488 lw a0,8(s1) 63ec: 8001 c.srli64 s0 63ee: 01f4 addi a3,sp,204 63f0: 0000 unimp @@ -35326,8 +35365,8 @@ Disassembly of section .debug_info: 6400: 0000 unimp 6402: d4ce sw s3,104(sp) 6404: 0000 unimp - 6406: 0312 slli t1,t1,0x4 - 6408: 0009 c.nop 2 + 6406: fe12 fsw ft4,60(sp) + 6408: 0008 0x8 640a: 0100 addi s0,sp,128 640c: 002c0327 0x2c0327 6410: 0000 unimp @@ -35355,14 +35394,13 @@ Disassembly of section .debug_info: 644a: 8e00 0x8e00 644c: 00d5 addi ra,ra,21 644e: 1200 addi s0,sp,288 - 6450: 099c addi a5,sp,208 - 6452: 0000 unimp + 6450: 00000997 auipc s3,0x0 6454: 2801 jal 6464 <_start-0x7fff9b9c> 6456: 00018903 lb s2,0(gp) # 80016808 <__global_pointer$> 645a: e400 fsw fs0,8(s0) 645c: 00d5 addi ra,ra,21 645e: 1200 addi s0,sp,288 - 6460: 08fe slli a7,a7,0x1f + 6460: 08f9 addi a7,a7,30 6462: 0000 unimp 6464: 2801 jal 6474 <_start-0x7fff9b8c> 6466: 00018903 lb s2,0(gp) # 80016808 <__global_pointer$> @@ -35402,12 +35440,12 @@ Disassembly of section .debug_info: 64bc: a600 fsd fs0,8(a2) 64be: 0002 c.slli64 zero 64c0: 1800 addi s0,sp,48 - 64c2: 08e9 addi a7,a7,26 + 64c2: 08e4 addi s1,sp,92 64c4: 0000 unimp 64c6: 2d01 jal 6ad6 <_start-0x7fff952a> 64c8: 0000e603 0xe603 64cc: 0000 unimp - 64ce: 1c19 addi s8,s8,-26 + 64ce: e019 bnez s0,64d4 <_start-0x7fff9b2c> 64d0: 0144 addi s1,sp,132 64d2: 2480 fld fs0,8(s1) 64d4: 0000 unimp @@ -35459,8 +35497,8 @@ Disassembly of section .debug_info: 654a: 2f01 jal 6c5a <_start-0x7fff93a6> 654c: 0003e203 0x3e203 6550: 0000 unimp - 6552: 9c19 0x9c19 - 6554: 0144 addi s1,sp,132 + 6552: 6019 c.lui zero,0x6 + 6554: 0145 addi sp,sp,17 6556: e080 fsw fs0,0(s1) 6558: 0000 unimp 655a: 8e00 0x8e00 @@ -35534,7 +35572,7 @@ Disassembly of section .debug_info: 6606: 5091 li ra,-28 6608: 0000 unimp 660a: 0402 c.slli64 s0 - 660c: c705 beqz a4,6634 <_start-0x7fff99cc> + 660c: 5b05 li s6,-31 660e: 0004 0x4 6610: 1d00 addi s0,sp,688 6612: 0189 addi gp,gp,2 @@ -35551,12 +35589,12 @@ Disassembly of section .debug_info: 662c: 0000 unimp 662e: 3e0c fld fa1,56(a2) 6630: 0012 c.slli zero,0x4 - 6632: 9400 0x9400 - 6634: 0001 nop - 6636: b800 fsd fs0,48(s0) - 6638: 0145 addi sp,sp,17 + 6632: ed00 fsw fs0,24(a0) + 6634: 0005 c.nop 1 + 6636: 7c00 flw fs0,56(s0) + 6638: 0146 slli sp,sp,0x11 663a: 4c80 lw s0,24(s1) - 663c: e0000003 lb zero,-512(zero) # fffffe00 <__BSS_END__+0x7ffe91d0> + 663c: 8c000003 lb zero,-1856(zero) # fffff8c0 <__BSS_END__+0x7ffe8c84> 6640: 0092 slli ra,ra,0x4 6642: 0200 addi s0,sp,256 6644: 0504 addi s1,sp,640 @@ -35566,7 +35604,7 @@ Disassembly of section .debug_info: 664e: 0006 c.slli zero,0x1 6650: 0300 addi s0,sp,384 6652: 0508 addi a0,sp,640 - 6654: 04c2 slli s1,s1,0x10 + 6654: 0456 slli s0,s0,0x15 6656: 0000 unimp 6658: c304 sw s1,0(a4) 665a: 02000007 0x2000007 @@ -35580,13 +35618,13 @@ Disassembly of section .debug_info: 666e: 0006 c.slli zero,0x1 6670: 0300 addi s0,sp,384 6672: 0704 addi s1,sp,896 - 6674: 02e2 slli t0,t0,0x18 + 6674: 0276 slli tp,tp,0x1d 6676: 0000 unimp - 6678: d8070803 lb a6,-640(a4) + 6678: 6c070803 lb a6,1728(a4) 667c: 0002 c.slli64 zero 667e: 0300 addi s0,sp,384 6680: 0702 c.slli64 a4 - 6682: 02f8 addi a4,sp,332 + 6682: 028c addi a1,sp,320 6684: 0000 unimp 6686: 4706 lw a4,64(sp) 6688: 0000 unimp @@ -35598,8 +35636,7 @@ Disassembly of section .debug_info: 6696: 6805 lui a6,0x1 6698: 0000 unimp 669a: 0800 addi s0,sp,16 - 669c: 0000030b 0x30b - 66a0: 3c05 jal 60d0 <_start-0x7fff9f30> + 669c: 029f 0000 3c05 0x3c050000029f 66a2: 7816 flw fa6,100(sp) 66a4: 0000 unimp 66a6: 0900 addi s0,sp,144 @@ -35634,7 +35671,7 @@ Disassembly of section .debug_info: 66ec: 0000 unimp 66ee: 0400 addi s0,sp,512 66f0: 0b04010b 0xb04010b - 66f4: 0000024f fnmadd.s ft4,ft0,ft0,ft0,rne + 66f4: 000001e3 beqz zero,6ef6 <_start-0x7fff910a> 66f8: 530e5a03 lhu s4,1328(t3) 66fc: 0000 unimp 66fe: 0400 addi s0,sp,512 @@ -35661,7 +35698,7 @@ Disassembly of section .debug_info: 6730: 0f48 addi a0,sp,916 6732: 0118 addi a4,sp,128 6734: 0000 unimp - 6736: c0041003 lh zero,-1024(s0) # fffe2c00 <__BSS_END__+0x7ffcbfd0> + 6736: c0041003 lh zero,-1024(s0) # fffe2c00 <__BSS_END__+0x7ffcbfc4> 673a: 0000 unimp 673c: 0a00 addi s0,sp,272 673e: 0410 addi a2,sp,512 @@ -35701,7 +35738,7 @@ Disassembly of section .debug_info: 678e: 00000053 fadd.s ft0,ft0,ft0,rne 6792: 0f04 addi s1,sp,912 6794: 0c01 addi s8,s8,0 - 6796: 00024f0b 0x24f0b + 6796: 0001e30b 0x1e30b 679a: 0400 addi s0,sp,512 679c: 0e5e slli t3,t3,0x17 679e: 00000053 fadd.s ft0,ft0,ft0,rne @@ -35709,7 +35746,7 @@ Disassembly of section .debug_info: 67a4: 0c00 addi s0,sp,528 67a6: 0300 addi s0,sp,384 67a8: 0704 addi s1,sp,896 - 67aa: 02dd addi t0,t0,23 + 67aa: 0271 addi tp,tp,28 67ac: 0000 unimp 67ae: 7e0d lui t3,0xfffe3 67b0: 000c 0xc @@ -35734,7 +35771,7 @@ Disassembly of section .debug_info: 67da: 0124 addi s1,sp,136 67dc: 0089 addi ra,ra,2 67de: 0000 unimp - 67e0: 45b8 lw a4,72(a1) + 67e0: 467c lw a5,76(a2) 67e2: 8001 c.srli64 s0 67e4: 034c addi a1,sp,388 67e6: 0000 unimp @@ -35744,8 +35781,8 @@ Disassembly of section .debug_info: 67f2: 1624 addi s1,sp,808 67f4: 010c addi a1,sp,128 67f6: 0000 unimp - 67f8: 0312 slli t1,t1,0x4 - 67fa: 0009 c.nop 2 + 67f8: fe12 fsw ft4,60(sp) + 67fa: 0008 0x8 67fc: 0100 addi s0,sp,128 67fe: 0326 slli t1,t1,0x9 6800: 0025 c.nop 9 @@ -35791,8 +35828,8 @@ Disassembly of section .debug_info: 686e: 655f 0100 0328 0x3280100655f 6874: 051f 0000 da54 0xda540000051f 687a: 0000 unimp - 687c: e412 fsw ft4,8(sp) - 687e: 0008 0x8 + 687c: cf12 sw tp,156(sp) + 687e: 0009 c.nop 2 6880: 0100 addi s0,sp,128 6882: 0328 addi a0,sp,392 6884: 0189 addi gp,gp,2 @@ -35890,9 +35927,8 @@ Disassembly of section .debug_info: 6968: 0000 unimp 696a: 0000dedb 0xdedb 696e: 0000 unimp - 6970: 601a flw ft0,132(sp) - 6972: 0146 slli sp,sp,0x11 - 6974: 3c80 fld fs0,56(s1) + 6970: 241a fld fs0,384(sp) + 6972: 3c800147 0x3c800147 6976: 0000 unimp 6978: b600 fsd fs0,40(a2) 697a: 1b000003 lb zero,432(zero) # 1b0 <_start-0x7ffffe50> @@ -36033,7 +36069,7 @@ Disassembly of section .debug_info: 6ae0: 00018903 lb s2,0(gp) # 80016808 <__global_pointer$> 6ae4: 0000 unimp 6ae6: 1a00 addi s0,sp,304 - 6ae8: 46b8 lw a4,72(a3) + 6ae8: 477c lw a5,76(a4) 6aea: 8001 c.srli64 s0 6aec: 0014 0x14 6aee: 0000 unimp @@ -36057,8 +36093,8 @@ Disassembly of section .debug_info: 6b20: 0189 addi gp,gp,2 6b22: 0000 unimp 6b24: 0000 unimp - 6b26: c01e sw t2,0(sp) - 6b28: 0148 addi a0,sp,132 + 6b26: 841e mv s0,t2 + 6b28: 0149 addi sp,sp,18 6b2a: 2080 fld fs0,0(s1) 6b2c: 0000 unimp 6b2e: 1b00 addi s0,sp,432 @@ -36069,7 +36105,7 @@ Disassembly of section .debug_info: 6b3a: 0000 unimp 6b3c: 0300 addi s0,sp,384 6b3e: 0504 addi s1,sp,640 - 6b40: 000004c7 fmsub.s fs1,ft0,ft0,ft0,rne + 6b40: 0000045b 0x45b 6b44: 891f 0001 0700 0x7000001891f 6b4a: 00000053 fadd.s ft0,ft0,ft0,rne 6b4e: 66000003 lb zero,1632(zero) # 660 <_start-0x7ffff9a0> @@ -36079,20 +36115,20 @@ Disassembly of section .debug_info: 6b5c: d401 beqz s0,6a64 <_start-0x7fff959c> 6b5e: 0009 c.nop 2 6b60: 0c00 addi s0,sp,528 - 6b62: 053e slli a0,a0,0xf + 6b62: 04d2 slli s1,s1,0x14 6b64: 0000 unimp - 6b66: 0194 addi a3,sp,192 + 6b66: 05ed addi a1,a1,27 6b68: 0000 unimp - 6b6a: 99ec 0x99ec + 6b6a: 9998 0x9998 6b6c: 0000 unimp 6b6e: 0402 c.slli64 s0 6b70: 6905 lui s2,0x1 6b72: 746e flw fs0,248(sp) 6b74: 0300 addi s0,sp,384 6b76: 0704 addi s1,sp,896 - 6b78: 02e2 slli t0,t0,0x18 + 6b78: 0276 slli tp,tp,0x1d 6b7a: 0000 unimp - 6b7c: c2050803 lb a6,-992(a0) + 6b7c: 56050803 lb a6,1376(a0) 6b80: 0004 0x4 6b82: 0300 addi s0,sp,384 6b84: 0410 addi a2,sp,512 @@ -36107,31 +36143,31 @@ Disassembly of section .debug_info: 6b9c: 0000 unimp 6b9e: 0300 addi s0,sp,384 6ba0: 0702 c.slli64 a4 - 6ba2: 02f8 addi a4,sp,332 + 6ba2: 028c addi a1,sp,320 6ba4: 0000 unimp - 6ba6: c7050403 lb s0,-912(a0) + 6ba6: 5b050403 lb s0,1456(a0) 6baa: 0004 0x4 6bac: 0300 addi s0,sp,384 6bae: 0704 addi s1,sp,896 - 6bb0: 02dd addi t0,t0,23 + 6bb0: 0271 addi tp,tp,28 6bb2: 0000 unimp - 6bb4: d8070803 lb a6,-640(a4) + 6bb4: 6c070803 lb a6,1728(a4) 6bb8: 0002 c.slli64 zero 6bba: 0400 addi s0,sp,512 - 6bbc: 0354 addi a3,sp,388 + 6bbc: 02e8 addi a0,sp,332 6bbe: 0000 unimp 6bc0: 5e01 li t3,-32 6bc2: 1701 addi a4,a4,-32 6bc4: 0024 addi s1,sp,8 6bc6: 0000 unimp - 6bc8: f605 bnez a2,6af0 <_start-0x7fff9510> + 6bc8: 8a05 andi a2,a2,1 6bca: 0004 0x4 6bcc: 0200 addi s0,sp,256 6bce: 0e2e slli t3,t3,0xb 6bd0: 0055 c.nop 21 6bd2: 0000 unimp - 6bd4: 3f05 jal 6b04 <_start-0x7fff94fc> - 6bd6: 0006 c.slli zero,0x1 + 6bd4: d305 beqz a4,6af4 <_start-0x7fff950c> + 6bd6: 0005 c.nop 1 6bd8: 0200 addi s0,sp,256 6bda: 0e74 addi a3,sp,796 6bdc: 0055 c.nop 21 @@ -36144,10 +36180,12 @@ Disassembly of section .debug_info: 6bee: a502 fsd ft0,136(sp) 6bf0: 0000bd03 0xbd03 6bf4: 0700 addi s0,sp,896 - 6bf6: 0000033f 6a0ca702 0x6a0ca7020000033f + 6bf6: 000002d3 fadd.s ft5,ft0,ft0,rne + 6bfa: a702 fsd ft0,392(sp) + 6bfc: 6a0c flw fa1,16(a2) 6bfe: 0000 unimp 6c00: 0700 addi s0,sp,896 - 6c02: 02aa slli t0,t0,0xa + 6c02: 023e slli tp,tp,0xf 6c04: 0000 unimp 6c06: a802 fsd ft0,16(sp) 6c08: 0000bd13 sltiu s10,ra,0 @@ -36164,18 +36202,18 @@ Disassembly of section .debug_info: 6c22: f109 bnez a0,6b24 <_start-0x7fff94dc> 6c24: 0000 unimp 6c26: 0b00 addi s0,sp,400 - 6c28: 03a5 addi t2,t2,9 + 6c28: 0339 addi t1,t1,14 6c2a: 0000 unimp 6c2c: a402 fsd ft0,8(sp) 6c2e: 00001d07 0x1d07 6c32: 0000 unimp - 6c34: 0006310b 0x6310b + 6c34: 0005c50b 0x5c50b 6c38: 0200 addi s0,sp,256 6c3a: 05a9 addi a1,a1,10 6c3c: 0000009b 0x9b 6c40: 0004 0x4 - 6c42: 1b05 addi s6,s6,-31 - 6c44: 0005 c.nop 1 + 6c42: af05 j 7372 <_start-0x7fff8c8e> + 6c44: 0004 0x4 6c46: 0200 addi s0,sp,256 6c48: 03aa slli t2,t2,0xa 6c4a: 00cd addi ra,ra,19 @@ -36187,18 +36225,18 @@ Disassembly of section .debug_info: 6c56: 1916 slli s2,s2,0x25 6c58: 005c addi a5,sp,4 6c5a: 0000 unimp - 6c5c: 2605 jal 6f7c <_start-0x7fff9084> - 6c5e: 0005 c.nop 1 + 6c5c: ba05 j 658c <_start-0x7fff9a74> + 6c5e: 0004 0x4 6c60: 0400 addi s0,sp,512 6c62: 0d0c addi a1,sp,656 6c64: 001d c.nop 7 6c66: 0000 unimp - 6c68: 9c05 0x9c05 + 6c68: 3005 jal 6488 <_start-0x7fff9b78> 6c6a: 0005 c.nop 1 6c6c: 0300 addi s0,sp,384 - 6c6e: 010b1b23 sh a6,22(s6) # 75016 <_start-0x7ff8afea> + 6c6e: 010b1b23 sh a6,22(s6) 6c72: 0000 unimp - 6c74: de0d beqz a2,6bae <_start-0x7fff9452> + 6c74: 720d lui tp,0xfffe3 6c76: 18000003 lb zero,384(zero) # 180 <_start-0x7ffffe80> 6c7a: 7d083403 0x7d083403 6c7e: 0001 nop @@ -36212,12 +36250,12 @@ Disassembly of section .debug_info: 6c90: 3703006b 0x3703006b 6c94: 00001d07 0x1d07 6c98: 0400 addi s0,sp,512 - 6c9a: 00060e0b 0x60e0b + 6c9a: 0005a20b 0x5a20b 6c9e: 0300 addi s0,sp,384 6ca0: 001d0b37 lui s6,0x1d0 6ca4: 0000 unimp 6ca6: 0b08 addi a0,sp,400 - 6ca8: 024e slli tp,tp,0x13 + 6ca8: 01e2 slli gp,gp,0x18 6caa: 0000 unimp 6cac: 1d143703 0x1d143703 6cb0: 0000 unimp @@ -36240,7 +36278,7 @@ Disassembly of section .debug_info: 6cde: 0024 addi s1,sp,8 6ce0: 0000 unimp 6ce2: 0000 unimp - 6ce4: 8d0d sub a0,a0,a1 + 6ce4: 210d jal 7106 <_start-0x7fff8efa> 6ce6: 0002 c.slli64 zero 6ce8: 2400 fld fs0,8(s0) 6cea: 16083c03 0x16083c03 @@ -36265,12 +36303,12 @@ Disassembly of section .debug_info: 6d20: 001d c.nop 7 6d22: 0000 unimp 6d24: 0b0c addi a1,sp,400 - 6d26: 04d0 addi a2,sp,580 + 6d26: 0464 addi s1,sp,524 6d28: 0000 unimp 6d2a: 1d094203 lbu tp,464(s2) 6d2e: 0000 unimp 6d30: 1000 addi s0,sp,32 - 6d32: 00039b0b 0x39b0b + 6d32: 00032f0b 0x32f0b 6d36: 0300 addi s0,sp,384 6d38: 001d0943 fmadd.s fs2,fs10,ft1,ft0,rne 6d3c: 0000 unimp @@ -36280,7 +36318,7 @@ Disassembly of section .debug_info: 6d44: 1d094403 lbu s0,464(s2) 6d48: 0000 unimp 6d4a: 1800 addi s0,sp,48 - 6d4c: 0005a50b 0x5a50b + 6d4c: 0005390b 0x5390b 6d50: 0300 addi s0,sp,384 6d52: 0945 addi s2,s2,17 6d54: 001d c.nop 7 @@ -36298,12 +36336,12 @@ Disassembly of section .debug_info: 6d6e: 5b084f03 lbu t5,1456(a6) # 13b00e <_start-0x7fec4ff2> 6d72: 0002 c.slli64 zero 6d74: 0b00 addi s0,sp,400 - 6d76: 0241 addi tp,tp,16 + 6d76: 01d5 addi gp,gp,21 6d78: 0000 unimp 6d7a: 5b0a5003 lhu zero,1456(s4) 6d7e: 0002 c.slli64 zero 6d80: 0000 unimp - 6d82: 0005780b 0x5780b + 6d82: 00050c0b 0x50c0b 6d86: 0300 addi s0,sp,384 6d88: 0951 addi s2,s2,20 6d8a: 0000025b 0x25b @@ -36327,7 +36365,7 @@ Disassembly of section .debug_info: 6db4: 0900 addi s0,sp,144 6db6: 0024 addi s1,sp,8 6db8: 0000 unimp - 6dba: 001f d910 0004 0x4d910001f + 6dba: 001f 6d10 0004 0x46d10001f 6dc0: 9000 0x9000 6dc2: 0301 addi t1,t1,0 6dc4: 0862 slli a6,a6,0x18 @@ -36338,12 +36376,12 @@ Disassembly of section .debug_info: 6dd0: 02ae1263 bne t3,a0,6df4 <_start-0x7fff920c> 6dd4: 0000 unimp 6dd6: 0b00 addi s0,sp,400 - 6dd8: 05f5 addi a1,a1,29 + 6dd8: 0589 addi a1,a1,2 6dda: 0000 unimp 6ddc: 1d066403 0x1d066403 6de0: 0000 unimp 6de2: 0400 addi s0,sp,512 - 6de4: 0002490b 0x2490b + 6de4: 0001dd0b 0x1dd0b 6de8: 0300 addi s0,sp,384 6dea: 0966 slli s2,s2,0x19 6dec: 02b4 addi a3,sp,328 @@ -36387,7 +36425,7 @@ Disassembly of section .debug_info: 6e42: 0004 0x4 6e44: 0040040f 0x40040f 6e48: 0000 unimp - 6e4a: d10d beqz a0,6d6c <_start-0x7fff9294> + 6e4a: 650d lui a0,0x3 6e4c: 0005 c.nop 1 6e4e: 6800 flw fs0,16(s0) 6e50: 3c08ba03 0x3c08ba03 @@ -36408,7 +36446,7 @@ Disassembly of section .debug_info: 6e80: 4709be03 0x4709be03 6e84: 0000 unimp 6e86: 0c00 addi s0,sp,528 - 6e88: 0002b90b 0x2b90b + 6e88: 00024d0b 0x24d0b 6e8c: 0300 addi s0,sp,384 6e8e: 004709bf 0e0e0000 0xe0e0000004709bf 6e96: 625f 0066 c003 0xc0030066625f @@ -36424,25 +36462,25 @@ Disassembly of section .debug_info: 6eb0: 0000013f fd0ac803 0xfd0ac8030000013f 6eb8: 0000 unimp 6eba: 1c00 addi s0,sp,560 - 6ebc: 0005380b 0x5380b + 6ebc: 0004cc0b 0x4cc0b 6ec0: 0300 addi s0,sp,384 6ec2: 1dca slli s11,s11,0x32 6ec4: 05c0 addi s0,sp,708 6ec6: 0000 unimp 6ec8: 0b20 addi s0,sp,408 - 6eca: 0394 addi a3,sp,448 + 6eca: 0328 addi a0,sp,392 6ecc: 0000 unimp 6ece: ef1dcc03 lbu s8,-271(s11) 6ed2: 0005 c.nop 1 6ed4: 2400 fld fs0,8(s0) - 6ed6: 0006390b 0x6390b + 6ed6: 0005cd0b 0x5cd0b 6eda: 0300 addi s0,sp,384 6edc: 06130dcf fnmadd.q fs11,ft6,ft1,ft0,rne 6ee0: 0000 unimp 6ee2: 0b28 addi a0,sp,408 6ee4: 0101 addi sp,sp,0 6ee6: 0000 unimp - 6ee8: 2d09d003 lhu zero,720(s3) + 6ee8: 2d09d003 lhu zero,720(s3) # 6720 <_start-0x7fff98e0> 6eec: 0006 c.slli zero,0x1 6eee: 2c00 fld fs0,24(s0) 6ef0: 5f0e lw t5,224(sp) @@ -36464,7 +36502,7 @@ Disassembly of section .debug_info: 6f16: 0b3c addi a5,sp,408 6f18: 0108 addi a0,sp,128 6f1a: 0000 unimp - 6f1c: 3311d803 lhu a6,817(gp) # 80016b39 <__global_pointer$+0x331> + 6f1c: 3311d803 lhu a6,817(gp) # 80016b39 <__global_locale+0x169> 6f20: 0006 c.slli zero,0x1 6f22: 4000 lw s0,0(s0) 6f24: 00074d0b 0x74d0b @@ -36476,11 +36514,11 @@ Disassembly of section .debug_info: 6f36: cb11dc03 lhu s8,-847(gp) # 800164b9 6f3a: 0002 c.slli64 zero 6f3c: 4400 lw s0,8(s0) - 6f3e: 0006500b 0x6500b + 6f3e: 0005e40b 0x5e40b 6f42: 0300 addi s0,sp,384 6f44: 07df 001d 0000 0x1d07df 6f4a: 0b4c addi a1,sp,404 - 6f4c: 03d6 slli t2,t2,0x15 + 6f4c: 036a slli t1,t1,0x1a 6f4e: 0000 unimp 6f50: 770ae003 0x770ae003 6f54: 0000 unimp @@ -36490,17 +36528,17 @@ Disassembly of section .debug_info: 6f5e: 045a12e3 bne s4,t0,77a2 <_start-0x7fff885e> 6f62: 0000 unimp 6f64: 0b54 addi a3,sp,404 - 6f66: 0000035b 0x35b + 6f66: 000002ef jal t0,6f66 <_start-0x7fff909a> 6f6a: 170ce703 0x170ce703 6f6e: 0001 nop 6f70: 5800 lw s0,48(s0) - 6f72: 0002a10b 0x2a10b + 6f72: 0002350b 0x2350b 6f76: 0300 addi s0,sp,384 6f78: 0ee9 addi t4,t4,26 6f7a: 00f1 addi ra,ra,28 6f7c: 0000 unimp 6f7e: 0b5c addi a5,sp,404 - 6f80: 000005af 0x5af + 6f80: 00000543 fmadd.s fa0,ft0,ft0,ft0,rne 6f84: 1d09ea03 0x1d09ea03 6f88: 0000 unimp 6f8a: 6400 flw fs0,8(s0) @@ -36524,15 +36562,15 @@ Disassembly of section .debug_info: 6fb0: 1500 addi s0,sp,672 6fb2: 045a slli s0,s0,0x16 6fb4: 0000 unimp - 6fb6: 1616 slli a2,a2,0x25 - 6fb8: 0006 c.slli zero,0x1 + 6fb6: aa16 fsd ft5,272(sp) + 6fb8: 0005 c.nop 1 6fba: 2800 fld fs0,16(s0) 6fbc: 0304 addi s1,sp,384 6fbe: 0265 addi tp,tp,25 6fc0: ae08 fsd fa0,24(a2) 6fc2: 0005 c.nop 1 6fc4: 1700 addi s0,sp,928 - 6fc6: 0595 addi a1,a1,5 + 6fc6: 0529 addi a0,a0,10 6fc8: 0000 unimp 6fca: 07026703 0x7026703 6fce: 001d c.nop 7 @@ -36546,11 +36584,11 @@ Disassembly of section .debug_info: 6fe4: 0000 unimp 6fe6: 14026c03 0x14026c03 6fea: 069f 0000 1708 0x17080000069f - 6ff0: 0254 addi a3,sp,260 + 6ff0: 01e8 addi a0,sp,204 6ff2: 0000 unimp 6ff4: 1e026c03 0x1e026c03 6ff8: 069f 0000 170c 0x170c0000069f - 6ffe: 05f0 addi a2,sp,716 + 6ffe: 0584 addi s1,sp,704 7000: 0000 unimp 7002: 08026e03 0x8026e03 7006: 001d c.nop 7 @@ -36560,7 +36598,7 @@ Disassembly of section .debug_info: 700e: 0000 unimp 7010: 08026f03 0x8026f03 7014: 089f 0000 1714 0x17140000089f - 701a: 0274 addi a3,sp,268 + 701a: 0208 addi a0,sp,256 701c: 0000 unimp 701e: 07027203 0x7027203 7022: 001d c.nop 7 @@ -36571,18 +36609,19 @@ Disassembly of section .debug_info: 7030: 08b4 addi a3,sp,88 7032: 0000 unimp 7034: 1734 addi a3,sp,936 - 7036: 000004eb 0x4eb + 7036: 047f 0x47f + 7038: 0000 unimp 703a: 07027503 0x7027503 703e: 001d c.nop 7 7040: 0000 unimp 7042: 1738 addi a4,sp,936 - 7044: 0604 addi s1,sp,768 + 7044: 0598 addi a4,sp,704 7046: 0000 unimp 7048: 0a027703 0xa027703 704c: 08c5 addi a7,a7,17 704e: 0000 unimp 7050: 173c addi a5,sp,936 - 7052: 00000337 lui t1,0x0 + 7052: 000002cb fnmsub.s ft5,ft0,ft0,ft0,rne 7056: 13027a03 0x13027a03 705a: 017d addi sp,sp,31 705c: 0000 unimp @@ -36599,36 +36638,37 @@ Disassembly of section .debug_info: 7076: 017d addi sp,sp,31 7078: 0000 unimp 707a: 1748 addi a0,sp,932 - 707c: 00000507 0x507 + 707c: 0000049b 0x49b 7080: 14027d03 0x14027d03 7084: 000008cb fnmsub.s fa7,ft0,ft0,ft0,rne 7088: 174c addi a1,sp,932 - 708a: 02b1 addi t0,t0,12 + 708a: 0245 addi tp,tp,17 708c: 0000 unimp 708e: 07028003 lb zero,112(t0) 7092: 001d c.nop 7 7094: 0000 unimp 7096: 1750 addi a2,sp,932 - 7098: 020d addi tp,tp,3 + 7098: 01a1 addi gp,gp,8 709a: 0000 unimp 709c: 09028103 lb sp,144(t0) 70a0: 05ae slli a1,a1,0xb 70a2: 0000 unimp 70a4: 1754 addi a3,sp,932 - 70a6: 058e slli a1,a1,0x3 + 70a6: 0522 slli a0,a0,0x8 70a8: 0000 unimp 70aa: 0702a403 lw s0,112(t0) 70ae: 087a slli a6,a6,0x1e 70b0: 0000 unimp 70b2: 1858 addi a4,sp,52 - 70b4: 04d9 addi s1,s1,22 + 70b4: 046d addi s0,s0,27 70b6: 0000 unimp 70b8: 1302a803 lw a6,304(t0) 70bc: 02ae slli t0,t0,0xb 70be: 0000 unimp 70c0: 0148 addi a0,sp,132 - 70c2: 1518 addi a4,sp,672 - 70c4: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> + 70c2: a918 fsd fa4,16(a0) + 70c4: 0002 c.slli64 zero + 70c6: 0300 addi s0,sp,384 70c8: 02a9 addi t0,t0,10 70ca: 6b12 flw fs6,4(sp) 70cc: 0002 c.slli64 zero @@ -36750,13 +36790,13 @@ Disassembly of section .debug_info: 71c8: 0699 addi a3,a3,6 71ca: 0000 unimp 71cc: 1700 addi s0,sp,928 - 71ce: 02d1 addi t0,t0,20 + 71ce: 0265 addi tp,tp,25 71d0: 0000 unimp 71d2: 07012b03 lw s6,112(sp) 71d6: 001d c.nop 7 71d8: 0000 unimp 71da: 1704 addi s1,sp,928 - 71dc: 000005b7 lui a1,0x0 + 71dc: 0000054b fnmsub.s fa0,ft0,ft0,ft0,rne 71e0: 0b012c03 lw s8,176(sp) 71e4: 069f 0000 0008 0x80000069f 71ea: 0660040f 0x660040f @@ -36775,7 +36815,7 @@ Disassembly of section .debug_info: 720c: de12 sw tp,60(sp) 720e: 0006 c.slli zero,0x1 7210: 0000 unimp - 7212: 00037117 auipc sp,0x37 + 7212: 00030517 auipc a0,0x30 7216: 0300 addi s0,sp,384 7218: 0146 slli sp,sp,0x11 721a: de12 sw tp,60(sp) @@ -36799,7 +36839,7 @@ Disassembly of section .debug_info: 7242: 0285 addi t0,t0,1 7244: 00080307 0x80307 7248: 1700 addi s0,sp,928 - 724a: 03ad addi t2,t2,11 + 724a: 0341 addi t1,t1,16 724c: 0000 unimp 724e: 18028703 lb a4,384(t0) 7252: 0024 addi s1,sp,8 @@ -36811,7 +36851,7 @@ Disassembly of section .debug_info: 7260: 05ae slli a1,a1,0xb 7262: 0000 unimp 7264: 1704 addi s1,sp,928 - 7266: 032a slli t1,t1,0xa + 7266: 02be slli t0,t0,0xf 7268: 0000 unimp 726a: 10028903 lb s2,256(t0) 726e: 00000803 lb a6,0(zero) # 0 <_start-0x80000000> @@ -36821,7 +36861,7 @@ Disassembly of section .debug_info: 7278: 17028a03 lb s4,368(t0) 727c: 00000193 li gp,0 7280: 1724 addi s1,sp,936 - 7282: 025c addi a5,sp,260 + 7282: 01f0 addi a2,sp,204 7284: 0000 unimp 7286: 0f028b03 lb s6,240(t0) 728a: 001d c.nop 7 @@ -36838,7 +36878,7 @@ Disassembly of section .debug_info: 72a6: 06a5 addi a3,a3,9 72a8: 0000 unimp 72aa: 1758 addi a4,sp,932 - 72ac: 000005e3 beqz zero,7ab6 <_start-0x7fff854a> + 72ac: 00000577 0x577 72b0: 16028e03 lb t3,352(t0) 72b4: 00f1 addi ra,ra,28 72b6: 0000 unimp @@ -36860,7 +36900,7 @@ Disassembly of section .debug_info: 72da: 10029103 lh sp,256(t0) 72de: 00000813 li a6,0 72e2: 1780 addi s0,sp,992 - 72e4: 031e slli t1,t1,0x7 + 72e4: 02b2 slli t0,t0,0xc 72e6: 0000 unimp 72e8: 10029203 lh tp,256(t0) 72ec: 00000823 sb zero,16(zero) # 10 <_start-0x7ffffff0> @@ -36871,7 +36911,7 @@ Disassembly of section .debug_info: 72fa: 001d c.nop 7 72fc: 0000 unimp 72fe: 17a0 addi s0,sp,1000 - 7300: 0226 slli tp,tp,0x9 + 7300: 01ba slli gp,gp,0xe 7302: 0000 unimp 7304: 16029403 lh s0,352(t0) 7308: 00f1 addi ra,ra,28 @@ -36883,7 +36923,7 @@ Disassembly of section .debug_info: 7316: 00f1 addi ra,ra,28 7318: 0000 unimp 731a: 17ac addi a1,sp,1000 - 731c: 0215 addi tp,tp,5 + 731c: 01a9 addi gp,gp,10 731e: 0000 unimp 7320: 16029603 lh a2,352(t0) 7324: 00f1 addi ra,ra,28 @@ -36901,7 +36941,7 @@ Disassembly of section .debug_info: 7340: 00f1 addi ra,ra,28 7342: 0000 unimp 7344: 17c4 addi s1,sp,996 - 7346: 00000593 li a1,0 + 7346: 00000527 0x527 734a: 08029903 lh s2,128(t0) 734e: 001d c.nop 7 7350: 0000 unimp @@ -36932,12 +36972,12 @@ Disassembly of section .debug_info: 7386: 07029e03 lh t3,112(t0) 738a: 085a slli a6,a6,0x16 738c: 0000 unimp - 738e: 00034517 auipc a0,0x34 + 738e: 0002d917 auipc s2,0x2d 7392: 0300 addi s0,sp,384 7394: 02a1 addi t0,t0,8 7396: 00085a1b 0x85a1b 739a: 0000 unimp - 739c: 00026b17 auipc s6,0x26 + 739c: 0001ff17 auipc t5,0x1f 73a0: 0300 addi s0,sp,384 73a2: 02a2 slli t0,t0,0x8 73a4: 6a18 flw fa4,16(a2) @@ -36960,17 +37000,17 @@ Disassembly of section .debug_info: 73c8: 1d00 addi s0,sp,688 73ca: 1b00 addi s0,sp,432 73cc: 03f0 addi a2,sp,460 - 73ce: 9f030283 lb t0,-1552(t1) # fffff9f0 <__BSS_END__+0x7ffe8dc0> + 73ce: 9f030283 lb t0,-1552(t1) 73d2: 0008 0x8 73d4: 1c00 addi s0,sp,560 - 73d6: 0616 slli a2,a2,0x5 + 73d6: 05aa slli a1,a1,0xa 73d8: 0000 unimp 73da: 0b029a03 lh s4,176(t0) 73de: 06ee slli a3,a3,0x1b 73e0: 0000 unimp 73e2: 531c lw a5,32(a4) 73e4: 03000007 0x3000007 - 73e8: 330b02a3 sb a6,805(s6) # 2d6c1 <_start-0x7ffd293f> + 73e8: 330b02a3 sb a6,805(s6) # 1d1325 <_start-0x7fe2ecdb> 73ec: 0008 0x8 73ee: 0000 unimp 73f0: b408 fsd fa0,40(s0) @@ -37033,13 +37073,13 @@ Disassembly of section .debug_info: 746e: 1215 addi tp,tp,-27 7470: 0009 c.nop 2 7472: 2100 fld fs0,0(a0) - 7474: 0200 addi s0,sp,256 + 7474: 0194 addi a3,sp,192 7476: 0000 unimp 7478: 1405 addi s0,s0,-31 747a: 1d24 addi s1,sp,696 747c: 0009 c.nop 2 747e: 2100 fld fs0,0(a0) - 7480: 05d9 addi a1,a1,22 + 7480: 056d addi a0,a0,27 7482: 0000 unimp 7484: 1505 addi a0,a0,-31 7486: 1d15 addi s10,s10,-27 @@ -37061,18 +37101,19 @@ Disassembly of section .debug_info: 74a6: 5a04 lw s1,48(a2) 74a8: 0009 c.nop 2 74aa: 2200 fld fs0,0(a2) - 74ac: e121 bnez a0,74ec <_start-0x7fff8b14> + 74ac: 7521 lui a0,0xfffe8 74ae: 0004 0x4 74b0: 0600 addi s0,sp,768 74b2: 05ae0e67 jalr t3,90(t3) # 6e25e <_start-0x7ff91da2> 74b6: 0000 unimp - 74b8: 4c21 li s8,8 - 74ba: 07000003 lb zero,112(zero) # 70 <_start-0x7fffff90> + 74b8: e021 bnez s0,74f8 <_start-0x7fff8b08> + 74ba: 0002 c.slli64 zero + 74bc: 0700 addi s0,sp,896 74be: 0f10 addi a2,sp,912 74c0: 00000973 0x973 74c4: 05ae040f 0x5ae040f 74c8: 0000 unimp - 74ca: e421 bnez s0,7512 <_start-0x7fff8aee> + 74ca: 7821 lui a6,0xfffe8 74cc: 0004 0x4 74ce: 0700 addi s0,sp,896 74d0: 0efc addi a5,sp,860 @@ -37095,13 +37136,13 @@ Disassembly of section .debug_info: 74f4: 1cfd addi s9,s9,-1 74f6: 001d c.nop 7 74f8: 0000 unimp - 74fa: 8b21 andi a4,a4,8 + 74fa: 1f21 addi t5,t5,-24 74fc: 07000003 lb zero,112(zero) # 70 <_start-0x7fffff90> 7500: 0cff 0xcff 7502: 001d c.nop 7 7504: 0000 unimp - 7506: 1121 addi sp,sp,-24 - 7508: 0005 c.nop 1 + 7506: a521 j 7b0e <_start-0x7fff84f2> + 7508: 0004 0x4 750a: 0800 addi s0,sp,16 750c: 169a slli a3,a3,0x26 750e: 0055 c.nop 21 @@ -37125,13 +37166,13 @@ Disassembly of section .debug_info: 7534: 179e slli a5,a5,0x27 7536: 09cd addi s3,s3,19 7538: 0000 unimp - 753a: bf05 j 746a <_start-0x7fff8b96> + 753a: 5305 li t1,-31 753c: 0002 c.slli64 zero 753e: 0900 addi s0,sp,144 7540: 162a slli a2,a2,0x2a 7542: 0024 addi s1,sp,8 7544: 0000 unimp - 7546: c705 beqz a4,756e <_start-0x7fff8a92> + 7546: 5b05 li s6,-31 7548: 0005 c.nop 1 754a: 0900 addi s0,sp,144 754c: 0a01152f 0xa01152f @@ -37161,7 +37202,7 @@ Disassembly of section .debug_info: 7586: 1610 addi a2,sp,800 7588: 000a c.slli zero,0x2 758a: 2300 fld fs0,0(a4) - 758c: 0292 slli t0,t0,0x4 + 758c: 0226 slli tp,tp,0x9 758e: 0000 unimp 7590: 00240407 0x240407 7594: 0000 unimp @@ -37169,18 +37210,18 @@ Disassembly of section .debug_info: 7598: 7706 flw fa4,96(sp) 759a: 000a c.slli zero,0x2 759c: 2400 fld fs0,8(s0) - 759e: 056e slli a0,a0,0x1b + 759e: 0502 c.slli64 a0 75a0: 0000 unimp 75a2: 2400 fld fs0,8(s0) - 75a4: 0366 slli t1,t1,0x19 + 75a4: 02fa slli t0,t0,0x1e 75a6: 0000 unimp 75a8: 2401 jal 77a8 <_start-0x7fff8858> - 75aa: 04a9 addi s1,s1,10 + 75aa: 043d addi s0,s0,15 75ac: 0000 unimp 75ae: 2402 fld fs0,0(sp) - 75b0: 03ba slli t2,t2,0xe + 75b0: 034e slli t1,t1,0x13 75b2: 0000 unimp - 75b4: 05652403 lw s0,86(a0) # 3b3e4 <_start-0x7ffc4c1c> + 75b4: 04f92403 lw s0,79(s2) # 343dd <_start-0x7ffcbc23> 75b8: 0000 unimp 75ba: 2404 fld fs1,8(s0) 75bc: 079e slli a5,a5,0x7 @@ -37195,24 +37236,24 @@ Disassembly of section .debug_info: 75ce: 1c21 addi s8,s8,-24 75d0: 0a3a slli s4,s4,0xe 75d2: 0000 unimp - 75d4: 0003c523 0x3c523 + 75d4: 00035923 0x35923 75d8: 0700 addi s0,sp,896 75da: 2404 fld fs1,8(s0) 75dc: 0000 unimp 75de: 0a00 addi s0,sp,272 - 75e0: 0aa80623 sb a0,172(a6) + 75e0: 0aa80623 sb a0,172(a6) # fffe80ac <__BSS_END__+0x7ffd1470> 75e4: 0000 unimp - 75e6: bd24 fsd fs1,120(a0) + 75e6: 5124 lw s1,96(a0) 75e8: 0005 c.nop 1 75ea: 0000 unimp - 75ec: 8424 0x8424 + 75ec: 1824 addi s1,sp,56 75ee: 0005 c.nop 1 75f0: 0100 addi s0,sp,128 75f2: a724 fsd fs1,72(a4) 75f4: 0006 c.slli zero,0x1 75f6: 0200 addi s0,sp,256 75f8: 2100 fld fs0,0(a0) - 75fa: 0234 addi a3,sp,264 + 75fa: 01c8 addi a0,sp,196 75fc: 0000 unimp 75fe: 280a fld fa6,128(sp) 7600: 831e mv t1,t2 @@ -37229,14 +37270,14 @@ Disassembly of section .debug_info: 7618: 0659 addi a2,a2,22 761a: 0000 unimp 761c: 2400 fld fs0,8(s0) - 761e: 00000647 fmsub.s fa2,ft0,ft0,ft0,rne + 761e: 000005db 0x5db 7622: 0001 nop 7624: 7c21 lui s8,0xfffe8 7626: 0001 nop 7628: 0a00 addi s0,sp,272 762a: 0ab42a2f amoswap.w.rl s4,a1,(s0) 762e: 0000 unimp - 7630: 7c21 lui s8,0xfffe8 + 7630: 1021 c.nop -24 7632: 0b000003 lb zero,176(zero) # b0 <_start-0x7fffff50> 7636: 1a29 addi s4,s4,-22 7638: 091d addi s2,s2,7 @@ -37255,9 +37296,9 @@ Disassembly of section .debug_info: 7656: 000a c.slli zero,0x2 7658: 0300 addi s0,sp,384 765a: 0404 addi s1,sp,512 - 765c: 04bc addi a5,sp,584 + 765c: 0450 addi a2,sp,516 765e: 0000 unimp - 7660: b4030803 lb a6,-1216(t1) + 7660: 48030803 lb a6,1152(t1) 7664: 0004 0x4 7666: 0300 addi s0,sp,384 7668: 0408 addi a0,sp,512 @@ -37282,7 +37323,7 @@ Disassembly of section .debug_info: 7696: fc0c fsw fa1,56(s0) 7698: 1601 addi a2,a2,-32 769a: 00000b3b 0xb3b - 769e: 0b1f 0003 0c00 0xc0000030b1f + 769e: 9f1f 0002 0c00 0xc0000029f1f 76a4: 0202 c.slli64 tp 76a6: 3b16 fld fs6,352(sp) 76a8: 2500000b 0x2500000b @@ -37291,7 +37332,7 @@ Disassembly of section .debug_info: 76b0: b20d j 6fd2 <_start-0x7fff902e> 76b2: 0f02 c.slli64 t5 76b4: 0305 addi t1,t1,1 - 76b6: 57fc lw a5,108(a5) + 76b6: 584c lw a1,52(s0) 76b8: 8001 c.srli64 s0 76ba: d300 sw s0,32(a4) 76bc: 0400000b 0x400000b @@ -37301,24 +37342,22 @@ Disassembly of section .debug_info: 76c6: d401 beqz s0,75ce <_start-0x7fff8a32> 76c8: 0009 c.nop 2 76ca: 0c00 addi s0,sp,528 - 76cc: 053e slli a0,a0,0xf + 76cc: 04d2 slli s1,s1,0x14 76ce: 0000 unimp - 76d0: 0194 addi a3,sp,192 + 76d0: 05ed addi a1,a1,27 76d2: 0000 unimp - 76d4: 4904 lw s1,16(a0) + 76d4: 49c8 lw a0,20(a1) 76d6: 8001 c.srli64 s0 76d8: 004c addi a1,sp,4 76da: 0000 unimp - 76dc: 9c1d 0x9c1d - 76de: 0000 unimp - 76e0: 0402 c.slli64 s0 + 76dc: 9b9f 0000 0402 0x40200009b9f 76e2: 6905 lui s2,0x1 76e4: 746e flw fs0,248(sp) 76e6: 0300 addi s0,sp,384 76e8: 0704 addi s1,sp,896 - 76ea: 02e2 slli t0,t0,0x18 + 76ea: 0276 slli tp,tp,0x1d 76ec: 0000 unimp - 76ee: c2050803 lb a6,-992(a0) + 76ee: 56050803 lb a6,1376(a0) # fffe8560 <__BSS_END__+0x7ffd1924> 76f2: 0004 0x4 76f4: 0300 addi s0,sp,384 76f6: 0410 addi a2,sp,512 @@ -37333,31 +37372,31 @@ Disassembly of section .debug_info: 770e: 0000 unimp 7710: 0300 addi s0,sp,384 7712: 0702 c.slli64 a4 - 7714: 02f8 addi a4,sp,332 + 7714: 028c addi a1,sp,320 7716: 0000 unimp - 7718: c7050403 lb s0,-912(a0) + 7718: 5b050403 lb s0,1456(a0) 771c: 0004 0x4 771e: 0300 addi s0,sp,384 7720: 0704 addi s1,sp,896 - 7722: 02dd addi t0,t0,23 + 7722: 0271 addi tp,tp,28 7724: 0000 unimp - 7726: d8070803 lb a6,-640(a4) + 7726: 6c070803 lb a6,1728(a4) 772a: 0002 c.slli64 zero 772c: 0400 addi s0,sp,512 - 772e: 0354 addi a3,sp,388 + 772e: 02e8 addi a0,sp,332 7730: 0000 unimp 7732: 5e02 lw t3,32(sp) 7734: 1701 addi a4,a4,-32 7736: 002c addi a1,sp,8 7738: 0000 unimp - 773a: f605 bnez a2,7662 <_start-0x7fff899e> + 773a: 8a05 andi a2,a2,1 773c: 0004 0x4 773e: 0300 addi s0,sp,384 7740: 0e2e slli t3,t3,0xb 7742: 005d c.nop 23 7744: 0000 unimp - 7746: 3f05 jal 7676 <_start-0x7fff898a> - 7748: 0006 c.slli zero,0x1 + 7746: d305 beqz a4,7666 <_start-0x7fff899a> + 7748: 0005 c.nop 1 774a: 0300 addi s0,sp,384 774c: 0e74 addi a3,sp,796 774e: 005d c.nop 23 @@ -37370,10 +37409,11 @@ Disassembly of section .debug_info: 7760: c503a503 lw a0,-944(t2) 7764: 0000 unimp 7766: 0700 addi s0,sp,896 - 7768: 0000033f 720ca703 0x720ca7030000033f + 7768: 000002d3 fadd.s ft5,ft0,ft0,rne + 776c: 720ca703 lw a4,1824(s9) # 720 <_start-0x7ffff8e0> 7770: 0000 unimp 7772: 0700 addi s0,sp,896 - 7774: 02aa slli t0,t0,0xa + 7774: 023e slli tp,tp,0xf 7776: 0000 unimp 7778: c513a803 lw a6,-943(t2) 777c: 0000 unimp @@ -37389,18 +37429,18 @@ Disassembly of section .debug_info: 7792: f909a203 lw tp,-112(s3) 7796: 0000 unimp 7798: 0b00 addi s0,sp,400 - 779a: 03a5 addi t2,t2,9 + 779a: 0339 addi t1,t1,14 779c: 0000 unimp - 779e: 2507a403 lw s0,592(a5) + 779e: 2507a403 lw s0,592(a5) # fffe3250 <__BSS_END__+0x7ffcc614> 77a2: 0000 unimp 77a4: 0000 unimp - 77a6: 0006310b 0x6310b + 77a6: 0005c50b 0x5c50b 77aa: 0300 addi s0,sp,384 77ac: 05a9 addi a1,a1,10 77ae: 000000a3 sb zero,1(zero) # 1 <_start-0x7fffffff> 77b2: 0004 0x4 - 77b4: 1b05 addi s6,s6,-31 - 77b6: 0005 c.nop 1 + 77b4: af05 j 7ee4 <_start-0x7fff811c> + 77b6: 0004 0x4 77b8: 0300 addi s0,sp,384 77ba: 03aa slli t2,t2,0xa 77bc: 00d5 addi ra,ra,21 @@ -37412,18 +37452,18 @@ Disassembly of section .debug_info: 77c8: 1916 slli s2,s2,0x25 77ca: 0064 addi s1,sp,12 77cc: 0000 unimp - 77ce: 2605 jal 7aee <_start-0x7fff8512> - 77d0: 0005 c.nop 1 + 77ce: ba05 j 70fe <_start-0x7fff8f02> + 77d0: 0004 0x4 77d2: 0500 addi s0,sp,640 77d4: 0d0c addi a1,sp,656 77d6: 0025 c.nop 9 77d8: 0000 unimp - 77da: 9c05 0x9c05 + 77da: 3005 jal 6ffa <_start-0x7fff9006> 77dc: 0005 c.nop 1 77de: 0400 addi s0,sp,512 77e0: 01131b23 sh a7,22(t1) 77e4: 0000 unimp - 77e6: de0d beqz a2,7720 <_start-0x7fff88e0> + 77e6: 720d lui tp,0xfffe3 77e8: 18000003 lb zero,384(zero) # 180 <_start-0x7ffffe80> 77ec: 3404 fld fs1,40(s0) 77ee: 8508 0x8508 @@ -37438,12 +37478,12 @@ Disassembly of section .debug_info: 7802: 3704006b 0x3704006b 7806: 00002507 flw fa0,0(zero) # 0 <_start-0x80000000> 780a: 0400 addi s0,sp,512 - 780c: 00060e0b 0x60e0b + 780c: 0005a20b 0x5a20b 7810: 0400 addi s0,sp,512 7812: 00250b37 lui s6,0x250 7816: 0000 unimp 7818: 0b08 addi a0,sp,400 - 781a: 024e slli tp,tp,0x13 + 781a: 01e2 slli gp,gp,0x18 781c: 0000 unimp 781e: 3704 fld fs1,40(a4) 7820: 2514 fld fa3,8(a0) @@ -37467,7 +37507,7 @@ Disassembly of section .debug_info: 7850: 002c addi a1,sp,8 7852: 0000 unimp 7854: 0000 unimp - 7856: 8d0d sub a0,a0,a1 + 7856: 210d jal 7c78 <_start-0x7fff8388> 7858: 0002 c.slli64 zero 785a: 2400 fld fs0,8(s0) 785c: 3c04 fld fs1,56(s0) @@ -37495,13 +37535,13 @@ Disassembly of section .debug_info: 7892: 0025 c.nop 9 7894: 0000 unimp 7896: 0b0c addi a1,sp,400 - 7898: 04d0 addi a2,sp,580 + 7898: 0464 addi s1,sp,524 789a: 0000 unimp 789c: 4204 lw s1,0(a2) 789e: 2509 jal 7ea0 <_start-0x7fff8160> 78a0: 0000 unimp 78a2: 1000 addi s0,sp,32 - 78a4: 00039b0b 0x39b0b + 78a4: 00032f0b 0x32f0b 78a8: 0400 addi s0,sp,512 78aa: 00250943 fmadd.s fs2,fa0,ft2,ft0,rne 78ae: 0000 unimp @@ -37512,7 +37552,7 @@ Disassembly of section .debug_info: 78b8: 2509 jal 7eba <_start-0x7fff8146> 78ba: 0000 unimp 78bc: 1800 addi s0,sp,48 - 78be: 0005a50b 0x5a50b + 78be: 0005390b 0x5390b 78c2: 0400 addi s0,sp,512 78c4: 0945 addi s2,s2,17 78c6: 0025 c.nop 9 @@ -37532,13 +37572,13 @@ Disassembly of section .debug_info: 78e2: 6308 flw fa0,0(a4) 78e4: 0002 c.slli64 zero 78e6: 0b00 addi s0,sp,400 - 78e8: 0241 addi tp,tp,16 + 78e8: 01d5 addi gp,gp,21 78ea: 0000 unimp 78ec: 5004 lw s1,32(s0) 78ee: 630a flw ft6,128(sp) 78f0: 0002 c.slli64 zero 78f2: 0000 unimp - 78f4: 0005780b 0x5780b + 78f4: 00050c0b 0x50c0b 78f8: 0400 addi s0,sp,512 78fa: 0951 addi s2,s2,20 78fc: 00000263 beqz zero,7900 <_start-0x7fff8700> @@ -37564,7 +37604,7 @@ Disassembly of section .debug_info: 7926: 0900 addi s0,sp,144 7928: 002c addi a1,sp,8 792a: 0000 unimp - 792c: 001f d910 0004 0x4d910001f + 792c: 001f 6d10 0004 0x46d10001f 7932: 9000 0x9000 7934: 0401 addi s0,s0,0 7936: 0862 slli a6,a6,0x18 @@ -37575,13 +37615,13 @@ Disassembly of section .debug_info: 7942: 02b61263 bne a2,a1,7966 <_start-0x7fff869a> 7946: 0000 unimp 7948: 0b00 addi s0,sp,400 - 794a: 05f5 addi a1,a1,29 + 794a: 0589 addi a1,a1,2 794c: 0000 unimp 794e: 6404 flw fs1,8(s0) 7950: 2506 fld fa0,64(sp) 7952: 0000 unimp 7954: 0400 addi s0,sp,512 - 7956: 0002490b 0x2490b + 7956: 0001dd0b 0x1dd0b 795a: 0400 addi s0,sp,512 795c: 0966 slli s2,s2,0x19 795e: 02bc addi a5,sp,328 @@ -37628,7 +37668,7 @@ Disassembly of section .debug_info: 79b4: 0004 0x4 79b6: 0048040f 0x48040f 79ba: 0000 unimp - 79bc: d10d beqz a0,78de <_start-0x7fff8722> + 79bc: 650d lui a0,0x3 79be: 0005 c.nop 1 79c0: 6800 flw fs0,16(s0) 79c2: ba04 fsd fs1,48(a2) @@ -37651,7 +37691,7 @@ Disassembly of section .debug_info: 79f4: 4f09 li t5,2 79f6: 0000 unimp 79f8: 0c00 addi s0,sp,528 - 79fa: 0002b90b 0x2b90b + 79fa: 00024d0b 0x24d0b 79fe: 0400 addi s0,sp,512 7a00: 004f09bf 0e0e0000 0xe0e0000004f09bf 7a08: 625f 0066 c004 0xc0040066625f @@ -37667,19 +37707,19 @@ Disassembly of section .debug_info: 7a22: 0000013f 050ac804 0x50ac8040000013f 7a2a: 0001 nop 7a2c: 1c00 addi s0,sp,560 - 7a2e: 0005380b 0x5380b + 7a2e: 0004cc0b 0x4cc0b 7a32: 0400 addi s0,sp,512 7a34: 1dca slli s11,s11,0x32 7a36: 05c8 addi a0,sp,708 7a38: 0000 unimp 7a3a: 0b20 addi s0,sp,408 - 7a3c: 0394 addi a3,sp,448 + 7a3c: 0328 addi a0,sp,392 7a3e: 0000 unimp 7a40: cc04 sw s1,24(s0) 7a42: f71d bnez a4,7970 <_start-0x7fff8690> 7a44: 0005 c.nop 1 7a46: 2400 fld fs0,8(s0) - 7a48: 0006390b 0x6390b + 7a48: 0005cd0b 0x5cd0b 7a4c: 0400 addi s0,sp,512 7a4e: 061b0dcf fnmadd.q fs11,fs6,ft1,ft0,rne 7a52: 0000 unimp @@ -37723,11 +37763,11 @@ Disassembly of section .debug_info: 7aaa: d311 beqz a4,79ae <_start-0x7fff8652> 7aac: 0002 c.slli64 zero 7aae: 4400 lw s0,8(s0) - 7ab0: 0006500b 0x6500b + 7ab0: 0005e40b 0x5e40b 7ab4: 0400 addi s0,sp,512 7ab6: 07df 0025 0000 0x2507df 7abc: 0b4c addi a1,sp,404 - 7abe: 03d6 slli t2,t2,0x15 + 7abe: 036a slli t1,t1,0x1a 7ac0: 0000 unimp 7ac2: e004 fsw fs1,0(s0) 7ac4: 7f0a flw ft10,160(sp) @@ -37738,18 +37778,18 @@ Disassembly of section .debug_info: 7ad0: 046212e3 bne tp,t1,8314 <_start-0x7fff7cec> 7ad4: 0000 unimp 7ad6: 0b54 addi a3,sp,404 - 7ad8: 0000035b 0x35b + 7ad8: 000002ef jal t0,7ad8 <_start-0x7fff8528> 7adc: e704 fsw fs1,8(a4) 7ade: 1f0c addi a1,sp,944 7ae0: 0001 nop 7ae2: 5800 lw s0,48(s0) - 7ae4: 0002a10b 0x2a10b + 7ae4: 0002350b 0x2350b 7ae8: 0400 addi s0,sp,512 7aea: 0ee9 addi t4,t4,26 7aec: 00f9 addi ra,ra,30 7aee: 0000 unimp 7af0: 0b5c addi a5,sp,404 - 7af2: 000005af 0x5af + 7af2: 00000543 fmadd.s fa0,ft0,ft0,ft0,rne 7af6: ea04 fsw fs1,16(a2) 7af8: 2509 jal 80fa <_start-0x7fff7f06> 7afa: 0000 unimp @@ -37774,15 +37814,15 @@ Disassembly of section .debug_info: 7b22: 1500 addi s0,sp,672 7b24: 0462 slli s0,s0,0x18 7b26: 0000 unimp - 7b28: 1616 slli a2,a2,0x25 - 7b2a: 0006 c.slli zero,0x1 + 7b28: aa16 fsd ft5,272(sp) + 7b2a: 0005 c.nop 1 7b2c: 2800 fld fs0,16(s0) 7b2e: 0404 addi s1,sp,512 7b30: 0265 addi tp,tp,25 7b32: b608 fsd fa0,40(a2) 7b34: 0005 c.nop 1 7b36: 1700 addi s0,sp,928 - 7b38: 0595 addi a1,a1,5 + 7b38: 0529 addi a0,a0,10 7b3a: 0000 unimp 7b3c: 6704 flw fs1,8(a4) 7b3e: 0702 c.slli64 a4 @@ -37801,13 +37841,13 @@ Disassembly of section .debug_info: 7b5a: 1402 slli s0,s0,0x20 7b5c: 000006a7 0x6a7 7b60: 1708 addi a0,sp,928 - 7b62: 0254 addi a3,sp,260 + 7b62: 01e8 addi a0,sp,204 7b64: 0000 unimp 7b66: 6c04 flw fs1,24(s0) 7b68: 1e02 slli t3,t3,0x20 7b6a: 000006a7 0x6a7 7b6e: 170c addi a1,sp,928 - 7b70: 05f0 addi a2,sp,716 + 7b70: 0584 addi s1,sp,704 7b72: 0000 unimp 7b74: 6e04 flw fs1,24(a2) 7b76: 0802 c.slli64 a6 @@ -37820,7 +37860,7 @@ Disassembly of section .debug_info: 7b84: 0802 c.slli64 a6 7b86: 000008a7 0x8a7 7b8a: 1714 addi a3,sp,928 - 7b8c: 0274 addi a3,sp,268 + 7b8c: 0208 addi a0,sp,256 7b8e: 0000 unimp 7b90: 7204 flw fs1,32(a2) 7b92: 0702 c.slli64 a4 @@ -37833,20 +37873,21 @@ Disassembly of section .debug_info: 7ba2: 08bc addi a5,sp,88 7ba4: 0000 unimp 7ba6: 1734 addi a3,sp,936 - 7ba8: 000004eb 0x4eb + 7ba8: 047f 0x47f + 7baa: 0000 unimp 7bac: 7504 flw fs1,40(a0) 7bae: 0702 c.slli64 a4 7bb0: 0025 c.nop 9 7bb2: 0000 unimp 7bb4: 1738 addi a4,sp,936 - 7bb6: 0604 addi s1,sp,768 + 7bb6: 0598 addi a4,sp,704 7bb8: 0000 unimp 7bba: 7704 flw fs1,40(a4) 7bbc: 0a02 c.slli64 s4 7bbe: 08cd addi a7,a7,19 7bc0: 0000 unimp 7bc2: 173c addi a5,sp,936 - 7bc4: 00000337 lui t1,0x0 + 7bc4: 000002cb fnmsub.s ft5,ft0,ft0,ft0,rne 7bc8: 7a04 flw fs1,48(a2) 7bca: 1302 slli t1,t1,0x20 7bcc: 0185 addi gp,gp,1 @@ -37866,41 +37907,42 @@ Disassembly of section .debug_info: 7be8: 0185 addi gp,gp,1 7bea: 0000 unimp 7bec: 1748 addi a0,sp,932 - 7bee: 00000507 0x507 + 7bee: 0000049b 0x49b 7bf2: 7d04 flw fs1,56(a0) 7bf4: 1402 slli s0,s0,0x20 7bf6: 000008d3 fadd.s fa7,ft0,ft0,rne 7bfa: 174c addi a1,sp,932 - 7bfc: 02b1 addi t0,t0,12 + 7bfc: 0245 addi tp,tp,17 7bfe: 0000 unimp 7c00: 8004 0x8004 7c02: 0702 c.slli64 a4 7c04: 0025 c.nop 9 7c06: 0000 unimp 7c08: 1750 addi a2,sp,932 - 7c0a: 020d addi tp,tp,3 + 7c0a: 01a1 addi gp,gp,8 7c0c: 0000 unimp 7c0e: 8104 0x8104 7c10: 0902 c.slli64 s2 7c12: 05b6 slli a1,a1,0xd 7c14: 0000 unimp 7c16: 1754 addi a3,sp,932 - 7c18: 058e slli a1,a1,0x3 + 7c18: 0522 slli a0,a0,0x8 7c1a: 0000 unimp 7c1c: a404 fsd fs1,8(s0) 7c1e: 0702 c.slli64 a4 7c20: 0882 c.slli64 a7 7c22: 0000 unimp 7c24: 1858 addi a4,sp,52 - 7c26: 04d9 addi s1,s1,22 + 7c26: 046d addi s0,s0,27 7c28: 0000 unimp 7c2a: a804 fsd fs1,16(s0) 7c2c: 1302 slli t1,t1,0x20 7c2e: 02b6 slli t0,t0,0xd 7c30: 0000 unimp 7c32: 0148 addi a0,sp,132 - 7c34: 1518 addi a4,sp,672 - 7c36: 04000003 lb zero,64(zero) # 40 <_start-0x7fffffc0> + 7c34: a918 fsd fa4,16(a0) + 7c36: 0002 c.slli64 zero + 7c38: 0400 addi s0,sp,512 7c3a: 02a9 addi t0,t0,10 7c3c: 7312 flw ft6,36(sp) 7c3e: 0002 c.slli64 zero @@ -38024,14 +38066,14 @@ Disassembly of section .debug_info: 7d3a: 06a1 addi a3,a3,8 7d3c: 0000 unimp 7d3e: 1700 addi s0,sp,928 - 7d40: 02d1 addi t0,t0,20 + 7d40: 0265 addi tp,tp,25 7d42: 0000 unimp 7d44: 2b04 fld fs1,16(a4) 7d46: 0701 addi a4,a4,0 7d48: 0025 c.nop 9 7d4a: 0000 unimp 7d4c: 1704 addi s1,sp,928 - 7d4e: 000005b7 lui a1,0x0 + 7d4e: 0000054b fnmsub.s fa0,ft0,ft0,ft0,rne 7d52: 2c04 fld fs1,24(s0) 7d54: 0b01 addi s6,s6,0 7d56: 000006a7 0x6a7 @@ -38053,7 +38095,7 @@ Disassembly of section .debug_info: 7d7e: e612 fsw ft4,12(sp) 7d80: 0006 c.slli zero,0x1 7d82: 0000 unimp - 7d84: 00037117 auipc sp,0x37 + 7d84: 00030517 auipc a0,0x30 7d88: 0400 addi s0,sp,512 7d8a: 0146 slli sp,sp,0x11 7d8c: e612 fsw ft4,12(sp) @@ -38077,7 +38119,7 @@ Disassembly of section .debug_info: 7db4: 0285 addi t0,t0,1 7db6: 00080b07 0x80b07 7dba: 1700 addi s0,sp,928 - 7dbc: 03ad addi t2,t2,11 + 7dbc: 0341 addi t1,t1,16 7dbe: 0000 unimp 7dc0: 8704 0x8704 7dc2: 1802 slli a6,a6,0x20 @@ -38091,7 +38133,7 @@ Disassembly of section .debug_info: 7dd2: 05b6 slli a1,a1,0xd 7dd4: 0000 unimp 7dd6: 1704 addi s1,sp,928 - 7dd8: 032a slli t1,t1,0xa + 7dd8: 02be slli t0,t0,0xf 7dda: 0000 unimp 7ddc: 8904 0x8904 7dde: 1002 c.slli zero,0x20 @@ -38103,7 +38145,7 @@ Disassembly of section .debug_info: 7dec: 1702 slli a4,a4,0x20 7dee: 0000019b 0x19b 7df2: 1724 addi s1,sp,936 - 7df4: 025c addi a5,sp,260 + 7df4: 01f0 addi a2,sp,204 7df6: 0000 unimp 7df8: 8b04 0x8b04 7dfa: 0f02 c.slli64 t5 @@ -38123,7 +38165,7 @@ Disassembly of section .debug_info: 7e18: 06ad addi a3,a3,11 7e1a: 0000 unimp 7e1c: 1758 addi a4,sp,932 - 7e1e: 000005e3 beqz zero,8628 <_start-0x7fff79d8> + 7e1e: 00000577 0x577 7e22: 8e04 0x8e04 7e24: 1602 slli a2,a2,0x20 7e26: 00f9 addi ra,ra,30 @@ -38149,7 +38191,7 @@ Disassembly of section .debug_info: 7e4e: 1002 c.slli zero,0x20 7e50: 0000081b 0x81b 7e54: 1780 addi s0,sp,992 - 7e56: 031e slli t1,t1,0x7 + 7e56: 02b2 slli t0,t0,0xc 7e58: 0000 unimp 7e5a: 9204 0x9204 7e5c: 1002 c.slli zero,0x20 @@ -38162,7 +38204,7 @@ Disassembly of section .debug_info: 7e6c: 0025 c.nop 9 7e6e: 0000 unimp 7e70: 17a0 addi s0,sp,1000 - 7e72: 0226 slli tp,tp,0x9 + 7e72: 01ba slli gp,gp,0xe 7e74: 0000 unimp 7e76: 9404 0x9404 7e78: 1602 slli a2,a2,0x20 @@ -38176,7 +38218,7 @@ Disassembly of section .debug_info: 7e88: 00f9 addi ra,ra,30 7e8a: 0000 unimp 7e8c: 17ac addi a1,sp,1000 - 7e8e: 0215 addi tp,tp,5 + 7e8e: 01a9 addi gp,gp,10 7e90: 0000 unimp 7e92: 9604 0x9604 7e94: 1602 slli a2,a2,0x20 @@ -38197,7 +38239,7 @@ Disassembly of section .debug_info: 7eb2: 00f9 addi ra,ra,30 7eb4: 0000 unimp 7eb6: 17c4 addi s1,sp,996 - 7eb8: 00000593 li a1,0 + 7eb8: 00000527 0x527 7ebc: 9904 0x9904 7ebe: 0802 c.slli64 a6 7ec0: 0025 c.nop 9 @@ -38230,12 +38272,12 @@ Disassembly of section .debug_info: 7efa: 0702 c.slli64 a4 7efc: 0862 slli a6,a6,0x18 7efe: 0000 unimp - 7f00: 00034517 auipc a0,0x34 + 7f00: 0002d917 auipc s2,0x2d 7f04: 0400 addi s0,sp,512 7f06: 02a1 addi t0,t0,8 7f08: 0008621b 0x8621b 7f0c: 0000 unimp - 7f0e: 00026b17 auipc s6,0x26 + 7f0e: 0001ff17 auipc t5,0x1f 7f12: 0400 addi s0,sp,512 7f14: 02a2 slli t0,t0,0x8 7f16: 7218 flw fa4,32(a2) @@ -38258,10 +38300,10 @@ Disassembly of section .debug_info: 7f3a: 1d00 addi s0,sp,688 7f3c: 1b00 addi s0,sp,432 7f3e: 04f0 addi a2,sp,588 - 7f40: a7030283 lb t0,-1424(t1) # fffffa70 <__BSS_END__+0x7ffe8e40> + 7f40: a7030283 lb t0,-1424(t1) 7f44: 0008 0x8 7f46: 1c00 addi s0,sp,560 - 7f48: 0616 slli a2,a2,0x5 + 7f48: 05aa slli a1,a1,0xa 7f4a: 0000 unimp 7f4c: 9a04 0x9a04 7f4e: 0b02 c.slli64 s6 @@ -38269,7 +38311,7 @@ Disassembly of section .debug_info: 7f52: 0000 unimp 7f54: 531c lw a5,32(a4) 7f56: 04000007 0x4000007 - 7f5a: 3b0b02a3 sb a6,933(s6) # 2e2b3 <_start-0x7ffd1d4d> + 7f5a: 3b0b02a3 sb a6,933(s6) # 2513a5 <_start-0x7fdaec5b> 7f5e: 0008 0x8 7f60: 0000 unimp 7f62: bc08 fsd fa0,56(s0) @@ -38317,7 +38359,7 @@ Disassembly of section .debug_info: 7fbc: 06ee slli a3,a3,0x1b 7fbe: 0000 unimp 7fc0: 3304 fld fs1,32(a4) - 7fc2: 04621703 lh a4,70(tp) # ffffd046 <__BSS_END__+0x7ffe6416> + 7fc2: 04621703 lh a4,70(tp) # ffffd046 <__BSS_END__+0x7ffe640a> 7fc6: 0000 unimp 7fc8: e71f 0006 0400 0x4000006e71f 7fce: 0334 addi a3,sp,392 @@ -38332,13 +38374,13 @@ Disassembly of section .debug_info: 7fe0: 1a15 addi s4,s4,-27 7fe2: 0009 c.nop 2 7fe4: 2100 fld fs0,0(a0) - 7fe6: 0200 addi s0,sp,256 + 7fe6: 0194 addi a3,sp,192 7fe8: 0000 unimp 7fea: 1406 slli s0,s0,0x21 7fec: 2524 fld fs1,72(a0) 7fee: 0009 c.nop 2 7ff0: 2100 fld fs0,0(a0) - 7ff2: 05d9 addi a1,a1,22 + 7ff2: 056d addi a0,a0,27 7ff4: 0000 unimp 7ff6: 1506 slli a0,a0,0x21 7ff8: 2515 jal 861c <_start-0x7fff79e4> @@ -38360,18 +38402,19 @@ Disassembly of section .debug_info: 8018: 6204 flw fs1,0(a2) 801a: 0009 c.nop 2 801c: 2200 fld fs0,0(a2) - 801e: e121 bnez a0,805e <_start-0x7fff7fa2> + 801e: 7521 lui a0,0xfffe8 8020: 0004 0x4 8022: 0700 addi s0,sp,896 8024: 05b60e67 jalr t3,91(a2) 8028: 0000 unimp - 802a: 4c21 li s8,8 - 802c: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> + 802a: e021 bnez s0,806a <_start-0x7fff7f96> + 802c: 0002 c.slli64 zero + 802e: 0800 addi s0,sp,16 8030: 0f10 addi a2,sp,912 8032: 0000097b 0x97b 8036: 05b6040f 0x5b6040f 803a: 0000 unimp - 803c: e421 bnez s0,8084 <_start-0x7fff7f7c> + 803c: 7821 lui a6,0xfffe8 803e: 0004 0x4 8040: 0800 addi s0,sp,16 8042: 0efc addi a5,sp,860 @@ -38394,13 +38437,13 @@ Disassembly of section .debug_info: 8066: 1cfd addi s9,s9,-1 8068: 0025 c.nop 9 806a: 0000 unimp - 806c: 8b21 andi a4,a4,8 + 806c: 1f21 addi t5,t5,-24 806e: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> 8072: 0cff 0xcff 8074: 0025 c.nop 9 8076: 0000 unimp - 8078: 1121 addi sp,sp,-24 - 807a: 0005 c.nop 1 + 8078: a521 j 8680 <_start-0x7fff7980> + 807a: 0004 0x4 807c: 0900 addi s0,sp,144 807e: 169a slli a3,a3,0x26 8080: 005d c.nop 23 @@ -38424,13 +38467,13 @@ Disassembly of section .debug_info: 80a6: 179e slli a5,a5,0x27 80a8: 09d5 addi s3,s3,21 80aa: 0000 unimp - 80ac: bf05 j 7fdc <_start-0x7fff8024> + 80ac: 5305 li t1,-31 80ae: 0002 c.slli64 zero 80b0: 0a00 addi s0,sp,272 80b2: 162a slli a2,a2,0x2a 80b4: 002c addi a1,sp,8 80b6: 0000 unimp - 80b8: c705 beqz a4,80e0 <_start-0x7fff7f20> + 80b8: 5b05 li s6,-31 80ba: 0005 c.nop 1 80bc: 0a00 addi s0,sp,272 80be: 0a09152f 0xa09152f @@ -38460,25 +38503,25 @@ Disassembly of section .debug_info: 80f8: 1e10 addi a2,sp,816 80fa: 000a c.slli zero,0x2 80fc: 2300 fld fs0,0(a4) - 80fe: 0292 slli t0,t0,0x4 + 80fe: 0226 slli tp,tp,0x9 8100: 0000 unimp 8102: 002c0407 0x2c0407 8106: 0000 unimp 8108: 7f06180b 0x7f06180b 810c: 000a c.slli zero,0x2 810e: 2400 fld fs0,8(s0) - 8110: 056e slli a0,a0,0x1b + 8110: 0502 c.slli64 a0 8112: 0000 unimp 8114: 2400 fld fs0,8(s0) - 8116: 0366 slli t1,t1,0x19 + 8116: 02fa slli t0,t0,0x1e 8118: 0000 unimp 811a: 2401 jal 831a <_start-0x7fff7ce6> - 811c: 04a9 addi s1,s1,10 + 811c: 043d addi s0,s0,15 811e: 0000 unimp 8120: 2402 fld fs0,0(sp) - 8122: 03ba slli t2,t2,0xe + 8122: 034e slli t1,t1,0x13 8124: 0000 unimp - 8126: 05652403 lw s0,86(a0) # 3bf56 <_start-0x7ffc40aa> + 8126: 04f92403 lw s0,79(s2) # 34f4f <_start-0x7ffcb0b1> 812a: 0000 unimp 812c: 2404 fld fs1,8(s0) 812e: 079e slli a5,a5,0x7 @@ -38493,24 +38536,24 @@ Disassembly of section .debug_info: 8140: 1c21 addi s8,s8,-24 8142: 0a42 slli s4,s4,0x10 8144: 0000 unimp - 8146: 0003c523 0x3c523 + 8146: 00035923 0x35923 814a: 0700 addi s0,sp,896 814c: 2c04 fld fs1,24(s0) 814e: 0000 unimp 8150: 0b00 addi s0,sp,400 8152: 0ab00623 sb a1,172(zero) # ac <_start-0x7fffff54> 8156: 0000 unimp - 8158: bd24 fsd fs1,120(a0) + 8158: 5124 lw s1,96(a0) 815a: 0005 c.nop 1 815c: 0000 unimp - 815e: 8424 0x8424 + 815e: 1824 addi s1,sp,56 8160: 0005 c.nop 1 8162: 0100 addi s0,sp,128 8164: a724 fsd fs1,72(a4) 8166: 0006 c.slli zero,0x1 8168: 0200 addi s0,sp,256 816a: 2100 fld fs0,0(a0) - 816c: 0234 addi a3,sp,264 + 816c: 01c8 addi a0,sp,196 816e: 0000 unimp 8170: 8b1e280b 0x8b1e280b 8174: 000a c.slli zero,0x2 @@ -38525,14 +38568,14 @@ Disassembly of section .debug_info: 818a: 0659 addi a2,a2,22 818c: 0000 unimp 818e: 2400 fld fs0,8(s0) - 8190: 00000647 fmsub.s fa2,ft0,ft0,ft0,rne + 8190: 000005db 0x5db 8194: 0001 nop 8196: 7c21 lui s8,0xfffe8 8198: 0001 nop 819a: 0b00 addi s0,sp,400 819c: 0abc2a2f amoswap.w.rl s4,a1,(s8) 81a0: 0000 unimp - 81a2: 7c21 lui s8,0xfffe8 + 81a2: 1021 c.nop -24 81a4: 0c000003 lb zero,192(zero) # c0 <_start-0x7fffff40> 81a8: 1a29 addi s4,s4,-22 81aa: 0925 addi s2,s2,9 @@ -38562,9 +38605,9 @@ Disassembly of section .debug_info: 81e0: 0000 unimp 81e2: 0300 addi s0,sp,384 81e4: 0404 addi s1,sp,512 - 81e6: 04bc addi a5,sp,584 + 81e6: 0450 addi a2,sp,516 81e8: 0000 unimp - 81ea: b4030803 lb a6,-1216(t1) + 81ea: 48030803 lb a6,1152(t1) 81ee: 0004 0x4 81f0: 0300 addi s0,sp,384 81f2: 0408 addi a0,sp,512 @@ -38589,7 +38632,7 @@ Disassembly of section .debug_info: 8220: fc0d bnez s0,815a <_start-0x7fff7ea6> 8222: 1601 addi a2,a2,-32 8224: 00000b5b 0xb5b - 8228: 0b1f 0003 0d00 0xd0000030b1f + 8228: 9f1f 0002 0d00 0xd0000029f1f 822e: 0202 c.slli64 tp 8230: 5b16 lw s6,100(sp) 8232: 2500000b 0x2500000b @@ -38599,7 +38642,7 @@ Disassembly of section .debug_info: 823c: 0102 c.slli64 sp 823e: 0025 c.nop 9 8240: 0000 unimp - 8242: 4904 lw s1,16(a0) + 8242: 49c8 lw a0,20(a1) 8244: 8001 c.srli64 s0 8246: 004c addi a1,sp,4 8248: 0000 unimp @@ -38749,7 +38792,7 @@ Disassembly of section .debug_abbrev: 140: 0301 addi t1,t1,0 142: 0b0e slli s6,s6,0x3 144: 3b0b3a0b 0x3b0b3a0b - 148: 3905 jal fffffd78 <__BSS_END__+0x7ffe9148> + 148: 3905 jal fffffd78 <__BSS_END__+0x7ffe913c> 14a: 0013010b 0x13010b 14e: 1a00 addi s0,sp,304 150: 0b0b0113 addi sp,s6,176 @@ -38759,7 +38802,7 @@ Disassembly of section .debug_abbrev: 15c: 0000 unimp 15e: 0b01171b 0xb01171b 162: 3b0b3a0b 0x3b0b3a0b - 166: 3905 jal fffffd96 <__BSS_END__+0x7ffe9166> + 166: 3905 jal fffffd96 <__BSS_END__+0x7ffe915a> 168: 0013010b 0x13010b 16c: 1c00 addi s0,sp,560 16e: 000d c.nop 3 @@ -38778,17 +38821,17 @@ Disassembly of section .debug_abbrev: 18e: 341f 0300 3a0e 0x3a0e0300341f 194: 39053b0b 0x39053b0b 198: 3f13490b 0x3f13490b - 19c: 3c19 jal fffffbb2 <__BSS_END__+0x7ffe8f82> + 19c: 3c19 jal fffffbb2 <__BSS_END__+0x7ffe8f76> 19e: 0019 c.nop 6 1a0: 2000 fld fs0,0(s0) 1a2: 0021 c.nop 8 1a4: 0000 unimp - 1a6: 3421 jal fffffbae <__BSS_END__+0x7ffe8f7e> + 1a6: 3421 jal fffffbae <__BSS_END__+0x7ffe8f72> 1a8: 0300 addi s0,sp,384 1aa: 3a0e fld fs4,224(sp) 1ac: 390b3b0b 0x390b3b0b 1b0: 3f13490b 0x3f13490b - 1b4: 3c19 jal fffffbca <__BSS_END__+0x7ffe8f9a> + 1b4: 3c19 jal fffffbca <__BSS_END__+0x7ffe8f8e> 1b6: 0019 c.nop 6 1b8: 2200 fld fs0,0(a2) 1ba: 0026 c.slli zero,0x9 @@ -38800,7 +38843,7 @@ Disassembly of section .debug_abbrev: 1cc: 010b390b 0x10b390b 1d0: 24000013 li zero,576 1d4: 0028 addi a0,sp,8 - 1d6: 0b1c0e03 lb t3,177(s8) # fffe80b1 <__BSS_END__+0x7ffd1481> + 1d6: 0b1c0e03 lb t3,177(s8) # fffe80b1 <__BSS_END__+0x7ffd1475> 1da: 0000 unimp 1dc: 0d25 addi s10,s10,9 1de: 0300 addi s0,sp,384 @@ -38851,7 +38894,7 @@ Disassembly of section .debug_abbrev: 258: 1702 slli a4,a4,0x20 25a: 0000 unimp 25c: 0b2e slli s6,s6,0xb - 25e: 3101 jal fffffe5e <__BSS_END__+0x7ffe922e> + 25e: 3101 jal fffffe5e <__BSS_END__+0x7ffe9222> 260: 01175513 srli a0,a4,0x11 264: 2f000013 li zero,752 268: 1331010b 0x1331010b @@ -38860,7 +38903,7 @@ Disassembly of section .debug_abbrev: 270: 1301 addi t1,t1,-32 272: 0000 unimp 274: 0b30 addi a2,sp,408 - 276: 3101 jal fffffe76 <__BSS_END__+0x7ffe9246> + 276: 3101 jal fffffe76 <__BSS_END__+0x7ffe923a> 278: 00175513 srli a0,a4,0x1 27c: 3100 fld fs0,32(a0) 27e: 012e slli sp,sp,0xb @@ -39036,17 +39079,17 @@ Disassembly of section .debug_abbrev: 45a: 341f 0300 3a0e 0x3a0e0300341f 460: 39053b0b 0x39053b0b 464: 3f13490b 0x3f13490b - 468: 3c19 jal fffffe7e <__BSS_END__+0x7ffe924e> + 468: 3c19 jal fffffe7e <__BSS_END__+0x7ffe9242> 46a: 0019 c.nop 6 46c: 2000 fld fs0,0(s0) 46e: 0021 c.nop 8 470: 0000 unimp - 472: 3421 jal fffffe7a <__BSS_END__+0x7ffe924a> + 472: 3421 jal fffffe7a <__BSS_END__+0x7ffe923e> 474: 0300 addi s0,sp,384 476: 3a0e fld fs4,224(sp) 478: 390b3b0b 0x390b3b0b 47c: 3f13490b 0x3f13490b - 480: 3c19 jal fffffe96 <__BSS_END__+0x7ffe9266> + 480: 3c19 jal fffffe96 <__BSS_END__+0x7ffe925a> 482: 0019 c.nop 6 484: 2200 fld fs0,0(a2) 486: 0026 c.slli zero,0x9 @@ -41173,8 +41216,9 @@ Disassembly of section .debug_abbrev: Disassembly of section .debug_line: 00000000 <.debug_line>: - 0: 0000092b 0x92b - 4: 02270003 lb zero,34(a4) + 0: 0901 addi s2,s2,0 + 2: 0000 unimp + 4: 01fd0003 lb zero,31(s10) # 3000407 <_start-0x7cfffbf9> 8: 0000 unimp a: 0101 addi sp,sp,0 c: 000d0efb 0xd0efb @@ -41193,16 +41237,15 @@ Disassembly of section .debug_line: 2e: 6c2f6363 bltu t5,sp,6f4 <_start-0x7ffff90c> 32: 6269 lui tp,0x1a 34: 00636367 0x636367 - 38: 6d6f682f 0x6d6f682f - 3c: 2f65 jal 7f4 <_start-0x7ffff80c> - 3e: 6166 flw ft2,88(sp) - 40: 6572 flw fa0,28(sp) - 42: 6f442f73 csrrs t5,0x6f4,s0 + 38: 6573552f 0x6573552f + 3c: 7372 flw ft6,60(sp) + 3e: 6d65642f 0x6d65642f + 42: 6f442f6f jal t5,42736 <_start-0x7ffbd8ca> 46: 656d7563 bgeu s10,s6,690 <_start-0x7ffff970> 4a: 746e flw fs0,248(sp) - 4c: 6f702f73 csrr t5,0x6f7 - 50: 645f6c63 bltu t5,t0,6a8 <_start-0x7ffff958> - 54: 7065 c.lui zero,0xffff9 + 4c: 656e2f73 csrrs t5,0x656,t3 + 50: 636f7077 0x636f7077 + 54: 766c flw fa1,108(a2) 56: 7369722f 0x7369722f 5a: 672d7663 bgeu s10,s2,6c6 <_start-0x7ffff93a> 5e: 756e flw fa0,248(sp) @@ -41220,344 +41263,349 @@ Disassembly of section .debug_line: 7e: 696c flw fa1,84(a0) 80: 2d62 fld fs10,24(sp) 82: 67617473 csrrci s0,0x676,2 - 86: 3265 jal fffffa2e <__BSS_END__+0x7ffe8dfe> + 86: 3265 jal fffffa2e <__BSS_END__+0x7ffe8df2> 88: 6363672f 0x6363672f 8c: 636e692f 0x636e692f 90: 756c flw fa1,108(a0) 92: 6564 flw fs1,76(a0) 94: 2f00 fld fs0,24(a4) - 96: 6f68 flw fa0,92(a4) - 98: 656d lui a0,0x1b - 9a: 7261662f 0x7261662f - 9e: 7365 lui t1,0xffff9 - a0: 7665642f 0x7665642f - a4: 7369722f 0x7369722f - a8: 672d7663 bgeu s10,s2,714 <_start-0x7ffff8ec> - ac: 756e flw fa0,248(sp) - ae: 742d lui s0,0xfffeb - b0: 636c6f6f jal t5,c66e6 <_start-0x7ff3991a> - b4: 6168 flw fa0,68(a0) - b6: 6e69 lui t3,0x1a - b8: 6f72642f 0x6f72642f - bc: 7370 flw fa2,100(a4) - be: 7369722f 0x7369722f - c2: 32337663 bgeu t1,gp,3ee <_start-0x7ffffc12> - c6: 752d lui a0,0xfffeb - c8: 6b6e flw fs6,216(sp) - ca: 6f6e flw ft10,216(sp) - cc: 652d6e77 0x652d6e77 - d0: 666c flw fa1,76(a2) - d2: 636e692f 0x636e692f - d6: 756c flw fa1,108(a0) - d8: 6564 flw fs1,76(a0) - da: 7379732f 0x7379732f - de: 2f00 fld fs0,24(a4) - e0: 6f68 flw fa0,92(a4) - e2: 656d lui a0,0x1b - e4: 7261662f 0x7261662f - e8: 7365 lui t1,0xffff9 - ea: 7665642f 0x7665642f - ee: 7369722f 0x7369722f - f2: 672d7663 bgeu s10,s2,75e <_start-0x7ffff8a2> - f6: 756e flw fa0,248(sp) - f8: 742d lui s0,0xfffeb - fa: 636c6f6f jal t5,c6730 <_start-0x7ff398d0> - fe: 6168 flw fa0,68(a0) - 100: 6e69 lui t3,0x1a - 102: 6f72642f 0x6f72642f - 106: 7370 flw fa2,100(a4) - 108: 7369722f 0x7369722f - 10c: 32337663 bgeu t1,gp,438 <_start-0x7ffffbc8> - 110: 752d lui a0,0xfffeb - 112: 6b6e flw fs6,216(sp) - 114: 6f6e flw ft10,216(sp) - 116: 652d6e77 0x652d6e77 - 11a: 666c flw fa1,76(a2) - 11c: 636e692f 0x636e692f - 120: 756c flw fa1,108(a0) - 122: 6564 flw fs1,76(a0) - 124: 2e00 fld fs0,24(a2) - 126: 2f2e fld ft10,200(sp) - 128: 2e2e fld ft8,200(sp) - 12a: 2f2e2e2f 0x2f2e2e2f - 12e: 2e2e fld ft8,200(sp) - 130: 7369722f 0x7369722f - 134: 672d7663 bgeu s10,s2,7a0 <_start-0x7ffff860> - 138: 6c2f6363 bltu t5,sp,7fe <_start-0x7ffff802> - 13c: 6269 lui tp,0x1a - 13e: 2f636367 0x2f636367 - 142: 2e2e fld ft8,200(sp) - 144: 636e692f 0x636e692f - 148: 756c flw fa1,108(a0) - 14a: 6564 flw fs1,76(a0) - 14c: 2e00 fld fs0,24(a2) - 14e: 2f2e fld ft10,200(sp) - 150: 2e2e fld ft8,200(sp) - 152: 2f2e2e2f 0x2f2e2e2f - 156: 2e2e fld ft8,200(sp) - 158: 7369722f 0x7369722f - 15c: 672d7663 bgeu s10,s2,7c8 <_start-0x7ffff838> - 160: 6c2f6363 bltu t5,sp,826 <_start-0x7ffff7da> - 164: 6269 lui tp,0x1a - 166: 2f636367 0x2f636367 - 16a: 2e2e fld ft8,200(sp) - 16c: 6363672f 0x6363672f - 170: 6e6f632f 0x6e6f632f - 174: 6966 flw fs2,88(sp) - 176: 69722f67 0x69722f67 - 17a: 00766373 csrrsi t1,0x7,12 - 17e: 2e2e fld ft8,200(sp) - 180: 2f2e2e2f 0x2f2e2e2f - 184: 2f2e fld ft10,200(sp) - 186: 00636367 0x636367 - 18a: 6c00 flw fs0,24(s0) - 18c: 6269 lui tp,0x1a - 18e: 32636367 0x32636367 - 192: 632e flw ft6,200(sp) - 194: 0100 addi s0,sp,128 - 196: 0000 unimp - 198: 64647473 csrrci s0,0x646,8 - 19c: 6665 lui a2,0x19 - 19e: 682e flw fa6,200(sp) - 1a0: 0200 addi s0,sp,256 - 1a2: 0000 unimp - 1a4: 745f 7079 7365 0x73657079745f - 1aa: 682e flw fa6,200(sp) - 1ac: 0300 addi s0,sp,384 - 1ae: 0000 unimp - 1b0: 6572 flw fa0,28(sp) - 1b2: 6e65 lui t3,0x19 - 1b4: 2e74 fld fa3,216(a2) - 1b6: 0068 addi a0,sp,12 - 1b8: 6c000003 lb zero,1728(zero) # 6c0 <_start-0x7ffff940> - 1bc: 2e6b636f jal t1,b64a2 <_start-0x7ff49b5e> - 1c0: 0068 addi a0,sp,12 - 1c2: 65000003 lb zero,1616(zero) # 650 <_start-0x7ffff9b0> - 1c6: 7272 flw ft4,60(sp) - 1c8: 6f6e flw ft10,216(sp) - 1ca: 682e flw fa6,200(sp) - 1cc: 0300 addi s0,sp,384 - 1ce: 0000 unimp - 1d0: 6c647473 csrrci s0,0x6c6,8 - 1d4: 6269 lui tp,0x1a - 1d6: 682e flw fa6,200(sp) - 1d8: 0400 addi s0,sp,512 - 1da: 0000 unimp - 1dc: 6e75 lui t3,0x1d - 1de: 7369 lui t1,0xffffa - 1e0: 6474 flw fa3,76(s0) - 1e2: 682e flw fa6,200(sp) - 1e4: 0300 addi s0,sp,384 - 1e6: 0000 unimp - 1e8: 6974 flw fa3,84(a0) - 1ea: 656d lui a0,0x1b - 1ec: 682e flw fa6,200(sp) - 1ee: 0400 addi s0,sp,512 - 1f0: 0000 unimp - 1f2: 6168 flw fa0,68(a0) - 1f4: 61746873 csrrsi a6,0x617,8 - 1f8: 2e62 fld ft8,24(sp) - 1fa: 0068 addi a0,sp,12 - 1fc: 0005 c.nop 1 - 1fe: 7200 flw fs0,32(a2) - 200: 7369 lui t1,0xffffa - 202: 6f2d7663 bgeu s10,s2,8ee <_start-0x7ffff712> - 206: 7470 flw fa2,108(s0) - 208: 00682e73 csrrs t3,0x6,a6 - 20c: 0006 c.slli zero,0x1 - 20e: 6900 flw fs0,16(a0) - 210: 736e flw ft6,248(sp) - 212: 2d6e fld fs10,216(sp) - 214: 736e6f63 bltu t3,s6,952 <_start-0x7ffff6ae> - 218: 6174 flw fa3,68(a0) - 21a: 746e flw fs0,248(sp) - 21c: 00682e73 csrrs t3,0x6,a6 - 220: 6c000007 0x6c000007 - 224: 6269 lui tp,0x1a - 226: 32636367 0x32636367 - 22a: 682e flw fa6,200(sp) - 22c: 0100 addi s0,sp,128 - 22e: 0000 unimp - 230: 0500 addi s0,sp,640 - 232: 0001 nop - 234: 0205 addi tp,tp,1 - 236: 0400 addi s0,sp,512 - 238: 8001 c.srli64 s0 - 23a: 010aa603 lw a2,16(s5) # 67d8 <_start-0x7fff9828> - 23e: 0305 addi t1,t1,1 - 240: 00090103 lb sp,0(s2) # 1000 <_start-0x7ffff000> - 244: 0100 addi s0,sp,128 - 246: 0105 addi sp,sp,1 - 248: 0306 slli t1,t1,0x1 - 24a: 097f 0x97f - 24c: 0000 unimp - 24e: 0501 addi a0,a0,0 - 250: d2030603 lb a2,-736(t1) # ffff9d20 <__BSS_END__+0x7ffe30f0> - 254: 097d addi s2,s2,31 - 256: 0004 0x4 - 258: 0301 addi t1,t1,0 - 25a: 0901 addi s2,s2,0 - 25c: 0000 unimp - 25e: 0301 addi t1,t1,0 - 260: 0901 addi s2,s2,0 - 262: 0000 unimp - 264: 0301 addi t1,t1,0 - 266: 0901 addi s2,s2,0 - 268: 0000 unimp - 26a: 0301 addi t1,t1,0 - 26c: 0901 addi s2,s2,0 - 26e: 0000 unimp - 270: 0301 addi t1,t1,0 - 272: 0901 addi s2,s2,0 - 274: 0000 unimp - 276: 0301 addi t1,t1,0 - 278: 0902 c.slli64 s2 - 27a: 0000 unimp - 27c: 0501 addi a0,a0,0 - 27e: 0601 addi a2,a2,0 - 280: 0902a703 lw a4,144(t0) # 195c06 <_start-0x7fe6a3fa> - 284: 0000 unimp - 286: 0501 addi a0,a0,0 - 288: 0306 slli t1,t1,0x1 - 28a: 7dd9 lui s11,0xffff6 - 28c: 0409 addi s0,s0,2 - 28e: 0100 addi s0,sp,128 - 290: 0305 addi t1,t1,1 - 292: 0306 slli t1,t1,0x1 - 294: 0901 addi s2,s2,0 - 296: 0004 0x4 + 96: 2f74706f j 47b8c <_start-0x7ffb8474> + 9a: 6972 flw fs2,28(sp) + 9c: 2d766373 csrrsi t1,0x2d7,12 + a0: 656e flw fa0,216(sp) + a2: 72642f77 0x72642f77 + a6: 2f73706f j 37b9c <_start-0x7ffc8464> + aa: 6972 flw fs2,28(sp) + ac: 33766373 csrrsi t1,mhpmevent23,12 + b0: 2d32 fld fs10,264(sp) + b2: 6e75 lui t3,0x1d + b4: 776f6e6b 0x776f6e6b + b8: 2d6e fld fs10,216(sp) + ba: 6c65 lui s8,0x19 + bc: 2f66 fld ft10,88(sp) + be: 6e69 lui t3,0x1a + c0: 64756c63 bltu a0,t2,718 <_start-0x7ffff8e8> + c4: 2f65 jal 87c <_start-0x7ffff784> + c6: 00737973 csrrci s2,0x7,6 + ca: 74706f2f 0x74706f2f + ce: 7369722f 0x7369722f + d2: 6e2d7663 bgeu s10,sp,7be <_start-0x7ffff842> + d6: 7765 lui a4,0xffff9 + d8: 6f72642f 0x6f72642f + dc: 7370 flw fa2,100(a4) + de: 7369722f 0x7369722f + e2: 32337663 bgeu t1,gp,40e <_start-0x7ffffbf2> + e6: 752d lui a0,0xfffeb + e8: 6b6e flw fs6,216(sp) + ea: 6f6e flw ft10,216(sp) + ec: 652d6e77 0x652d6e77 + f0: 666c flw fa1,76(a2) + f2: 636e692f 0x636e692f + f6: 756c flw fa1,108(a0) + f8: 6564 flw fs1,76(a0) + fa: 2e00 fld fs0,24(a2) + fc: 2f2e fld ft10,200(sp) + fe: 2e2e fld ft8,200(sp) + 100: 2f2e2e2f 0x2f2e2e2f + 104: 2e2e fld ft8,200(sp) + 106: 7369722f 0x7369722f + 10a: 672d7663 bgeu s10,s2,776 <_start-0x7ffff88a> + 10e: 6c2f6363 bltu t5,sp,7d4 <_start-0x7ffff82c> + 112: 6269 lui tp,0x1a + 114: 2f636367 0x2f636367 + 118: 2e2e fld ft8,200(sp) + 11a: 636e692f 0x636e692f + 11e: 756c flw fa1,108(a0) + 120: 6564 flw fs1,76(a0) + 122: 2e00 fld fs0,24(a2) + 124: 2f2e fld ft10,200(sp) + 126: 2e2e fld ft8,200(sp) + 128: 2f2e2e2f 0x2f2e2e2f + 12c: 2e2e fld ft8,200(sp) + 12e: 7369722f 0x7369722f + 132: 672d7663 bgeu s10,s2,79e <_start-0x7ffff862> + 136: 6c2f6363 bltu t5,sp,7fc <_start-0x7ffff804> + 13a: 6269 lui tp,0x1a + 13c: 2f636367 0x2f636367 + 140: 2e2e fld ft8,200(sp) + 142: 6363672f 0x6363672f + 146: 6e6f632f 0x6e6f632f + 14a: 6966 flw fs2,88(sp) + 14c: 69722f67 0x69722f67 + 150: 00766373 csrrsi t1,0x7,12 + 154: 2e2e fld ft8,200(sp) + 156: 2f2e2e2f 0x2f2e2e2f + 15a: 2f2e fld ft10,200(sp) + 15c: 00636367 0x636367 + 160: 6c00 flw fs0,24(s0) + 162: 6269 lui tp,0x1a + 164: 32636367 0x32636367 + 168: 632e flw ft6,200(sp) + 16a: 0100 addi s0,sp,128 + 16c: 0000 unimp + 16e: 64647473 csrrci s0,0x646,8 + 172: 6665 lui a2,0x19 + 174: 682e flw fa6,200(sp) + 176: 0200 addi s0,sp,256 + 178: 0000 unimp + 17a: 745f 7079 7365 0x73657079745f + 180: 682e flw fa6,200(sp) + 182: 0300 addi s0,sp,384 + 184: 0000 unimp + 186: 6572 flw fa0,28(sp) + 188: 6e65 lui t3,0x19 + 18a: 2e74 fld fa3,216(a2) + 18c: 0068 addi a0,sp,12 + 18e: 6c000003 lb zero,1728(zero) # 6c0 <_start-0x7ffff940> + 192: 2e6b636f jal t1,b6478 <_start-0x7ff49b88> + 196: 0068 addi a0,sp,12 + 198: 65000003 lb zero,1616(zero) # 650 <_start-0x7ffff9b0> + 19c: 7272 flw ft4,60(sp) + 19e: 6f6e flw ft10,216(sp) + 1a0: 682e flw fa6,200(sp) + 1a2: 0300 addi s0,sp,384 + 1a4: 0000 unimp + 1a6: 6c647473 csrrci s0,0x6c6,8 + 1aa: 6269 lui tp,0x1a + 1ac: 682e flw fa6,200(sp) + 1ae: 0400 addi s0,sp,512 + 1b0: 0000 unimp + 1b2: 6e75 lui t3,0x1d + 1b4: 7369 lui t1,0xffffa + 1b6: 6474 flw fa3,76(s0) + 1b8: 682e flw fa6,200(sp) + 1ba: 0300 addi s0,sp,384 + 1bc: 0000 unimp + 1be: 6974 flw fa3,84(a0) + 1c0: 656d lui a0,0x1b + 1c2: 682e flw fa6,200(sp) + 1c4: 0400 addi s0,sp,512 + 1c6: 0000 unimp + 1c8: 6168 flw fa0,68(a0) + 1ca: 61746873 csrrsi a6,0x617,8 + 1ce: 2e62 fld ft8,24(sp) + 1d0: 0068 addi a0,sp,12 + 1d2: 0005 c.nop 1 + 1d4: 7200 flw fs0,32(a2) + 1d6: 7369 lui t1,0xffffa + 1d8: 6f2d7663 bgeu s10,s2,8c4 <_start-0x7ffff73c> + 1dc: 7470 flw fa2,108(s0) + 1de: 00682e73 csrrs t3,0x6,a6 + 1e2: 0006 c.slli zero,0x1 + 1e4: 6900 flw fs0,16(a0) + 1e6: 736e flw ft6,248(sp) + 1e8: 2d6e fld fs10,216(sp) + 1ea: 736e6f63 bltu t3,s6,928 <_start-0x7ffff6d8> + 1ee: 6174 flw fa3,68(a0) + 1f0: 746e flw fs0,248(sp) + 1f2: 00682e73 csrrs t3,0x6,a6 + 1f6: 6c000007 0x6c000007 + 1fa: 6269 lui tp,0x1a + 1fc: 32636367 0x32636367 + 200: 682e flw fa6,200(sp) + 202: 0100 addi s0,sp,128 + 204: 0000 unimp + 206: 0500 addi s0,sp,640 + 208: 0001 nop + 20a: 0205 addi tp,tp,1 + 20c: 04c4 addi s1,sp,580 + 20e: 8001 c.srli64 s0 + 210: 010aa603 lw a2,16(s5) # 67d8 <_start-0x7fff9828> + 214: 0305 addi t1,t1,1 + 216: 00090103 lb sp,0(s2) + 21a: 0100 addi s0,sp,128 + 21c: 0105 addi sp,sp,1 + 21e: 0306 slli t1,t1,0x1 + 220: 097f 0x97f + 222: 0000 unimp + 224: 0501 addi a0,a0,0 + 226: d2030603 lb a2,-736(t1) # ffff9d20 <__BSS_END__+0x7ffe30e4> + 22a: 097d addi s2,s2,31 + 22c: 0004 0x4 + 22e: 0301 addi t1,t1,0 + 230: 0901 addi s2,s2,0 + 232: 0000 unimp + 234: 0301 addi t1,t1,0 + 236: 0901 addi s2,s2,0 + 238: 0000 unimp + 23a: 0301 addi t1,t1,0 + 23c: 0901 addi s2,s2,0 + 23e: 0000 unimp + 240: 0301 addi t1,t1,0 + 242: 0901 addi s2,s2,0 + 244: 0000 unimp + 246: 0301 addi t1,t1,0 + 248: 0901 addi s2,s2,0 + 24a: 0000 unimp + 24c: 0301 addi t1,t1,0 + 24e: 0902 c.slli64 s2 + 250: 0000 unimp + 252: 0501 addi a0,a0,0 + 254: 0601 addi a2,a2,0 + 256: 0902a703 lw a4,144(t0) # 195c06 <_start-0x7fe6a3fa> + 25a: 0000 unimp + 25c: 0501 addi a0,a0,0 + 25e: 0306 slli t1,t1,0x1 + 260: 7dd9 lui s11,0xffff6 + 262: 0409 addi s0,s0,2 + 264: 0100 addi s0,sp,128 + 266: 0305 addi t1,t1,1 + 268: 0306 slli t1,t1,0x1 + 26a: 0901 addi s2,s2,0 + 26c: 0004 0x4 + 26e: 0501 addi a0,a0,0 + 270: 0606 slli a2,a2,0x1 + 272: 00090003 lb zero,0(s2) + 276: 0100 addi s0,sp,128 + 278: 0305 addi t1,t1,1 + 27a: 0306 slli t1,t1,0x1 + 27c: 0901 addi s2,s2,0 + 27e: 0004 0x4 + 280: 0501 addi a0,a0,0 + 282: 0606 slli a2,a2,0x1 + 284: 00090003 lb zero,0(s2) + 288: 0100 addi s0,sp,128 + 28a: 0305 addi t1,t1,1 + 28c: 0306 slli t1,t1,0x1 + 28e: 0901 addi s2,s2,0 + 290: 0004 0x4 + 292: 0301 addi t1,t1,0 + 294: 0925 addi s2,s2,9 + 296: 0000 unimp 298: 0501 addi a0,a0,0 29a: 0606 slli a2,a2,0x1 29c: 00090003 lb zero,0(s2) 2a0: 0100 addi s0,sp,128 - 2a2: 0305 addi t1,t1,1 + 2a2: 0705 addi a4,a4,1 2a4: 0306 slli t1,t1,0x1 - 2a6: 0901 addi s2,s2,0 + 2a6: 0902 c.slli64 s2 2a8: 0004 0x4 2aa: 0501 addi a0,a0,0 - 2ac: 0606 slli a2,a2,0x1 - 2ae: 00090003 lb zero,0(s2) + 2ac: 060a slli a2,a2,0x2 + 2ae: 08090003 lb zero,128(s2) 2b2: 0100 addi s0,sp,128 - 2b4: 0305 addi t1,t1,1 + 2b4: 0405 addi s0,s0,1 2b6: 0306 slli t1,t1,0x1 - 2b8: 0901 addi s2,s2,0 + 2b8: 0904 addi s1,sp,144 2ba: 0004 0x4 2bc: 0301 addi t1,t1,0 - 2be: 0925 addi s2,s2,9 + 2be: 0900 addi s0,sp,144 2c0: 0000 unimp - 2c2: 0501 addi a0,a0,0 - 2c4: 0606 slli a2,a2,0x1 - 2c6: 00090003 lb zero,0(s2) - 2ca: 0100 addi s0,sp,128 - 2cc: 0705 addi a4,a4,1 - 2ce: 0306 slli t1,t1,0x1 - 2d0: 0902 c.slli64 s2 - 2d2: 0004 0x4 - 2d4: 0501 addi a0,a0,0 - 2d6: 060a slli a2,a2,0x2 - 2d8: 08090003 lb zero,128(s2) - 2dc: 0100 addi s0,sp,128 - 2de: 0405 addi s0,s0,1 - 2e0: 0306 slli t1,t1,0x1 - 2e2: 0904 addi s1,sp,144 - 2e4: 0004 0x4 - 2e6: 0301 addi t1,t1,0 - 2e8: 0900 addi s0,sp,144 - 2ea: 0000 unimp - 2ec: 0301 addi t1,t1,0 - 2ee: 0900 addi s0,sp,144 - 2f0: 0000 unimp - 2f2: 0301 addi t1,t1,0 - 2f4: 0900 addi s0,sp,144 - 2f6: 0000 unimp - 2f8: 0301 addi t1,t1,0 - 2fa: 0900 addi s0,sp,144 - 2fc: 0000 unimp - 2fe: 0301 addi t1,t1,0 - 300: 0900 addi s0,sp,144 - 302: 0014 0x14 - 304: 0301 addi t1,t1,0 - 306: 0900 addi s0,sp,144 - 308: 0018 0x18 - 30a: 0301 addi t1,t1,0 - 30c: 0902 c.slli64 s2 - 30e: 0000 unimp - 310: 0501 addi a0,a0,0 - 312: 00030607 0x30607 - 316: 0009 c.nop 2 - 318: 0100 addi s0,sp,128 - 31a: 0805 addi a6,a6,1 - 31c: 0306 slli t1,t1,0x1 - 31e: 0905 addi s2,s2,1 - 320: 0004 0x4 - 322: 0501 addi a0,a0,0 - 324: 0611 addi a2,a2,4 - 326: 00090103 lb sp,0(s2) - 32a: 0100 addi s0,sp,128 - 32c: 1e05 addi t3,t3,-31 - 32e: 04090003 lb zero,64(s2) - 332: 0100 addi s0,sp,128 - 334: 0b05 addi s6,s6,1 - 336: 04097f03 0x4097f03 - 33a: 0100 addi s0,sp,128 - 33c: 0805 addi a6,a6,1 - 33e: 0306 slli t1,t1,0x1 - 340: 0901 addi s2,s2,0 - 342: 0004 0x4 - 344: 0501 addi a0,a0,0 - 346: 0003060b 0x3060b - 34a: 0009 c.nop 2 - 34c: 0100 addi s0,sp,128 - 34e: 0805 addi a6,a6,1 - 350: 0306 slli t1,t1,0x1 - 352: 0901 addi s2,s2,0 + 2c2: 0301 addi t1,t1,0 + 2c4: 0900 addi s0,sp,144 + 2c6: 0000 unimp + 2c8: 0301 addi t1,t1,0 + 2ca: 0900 addi s0,sp,144 + 2cc: 0000 unimp + 2ce: 0301 addi t1,t1,0 + 2d0: 0900 addi s0,sp,144 + 2d2: 0000 unimp + 2d4: 0301 addi t1,t1,0 + 2d6: 0900 addi s0,sp,144 + 2d8: 0014 0x14 + 2da: 0301 addi t1,t1,0 + 2dc: 0900 addi s0,sp,144 + 2de: 0018 0x18 + 2e0: 0301 addi t1,t1,0 + 2e2: 0902 c.slli64 s2 + 2e4: 0000 unimp + 2e6: 0501 addi a0,a0,0 + 2e8: 00030607 0x30607 + 2ec: 0009 c.nop 2 + 2ee: 0100 addi s0,sp,128 + 2f0: 0805 addi a6,a6,1 + 2f2: 0306 slli t1,t1,0x1 + 2f4: 0905 addi s2,s2,1 + 2f6: 0004 0x4 + 2f8: 0501 addi a0,a0,0 + 2fa: 0611 addi a2,a2,4 + 2fc: 00090103 lb sp,0(s2) + 300: 0100 addi s0,sp,128 + 302: 1e05 addi t3,t3,-31 + 304: 04090003 lb zero,64(s2) + 308: 0100 addi s0,sp,128 + 30a: 0b05 addi s6,s6,1 + 30c: 04097f03 0x4097f03 + 310: 0100 addi s0,sp,128 + 312: 0805 addi a6,a6,1 + 314: 0306 slli t1,t1,0x1 + 316: 0901 addi s2,s2,0 + 318: 0004 0x4 + 31a: 0501 addi a0,a0,0 + 31c: 0003060b 0x3060b + 320: 0009 c.nop 2 + 322: 0100 addi s0,sp,128 + 324: 0805 addi a6,a6,1 + 326: 0306 slli t1,t1,0x1 + 328: 0901 addi s2,s2,0 + 32a: 0004 0x4 + 32c: 0501 addi a0,a0,0 + 32e: 0003060b 0x3060b + 332: 0009 c.nop 2 + 334: 0100 addi s0,sp,128 + 336: 0405 addi s0,s0,1 + 338: 0306 slli t1,t1,0x1 + 33a: 00040903 lb s2,0(s0) # fffeb000 <__BSS_END__+0x7ffd43c4> + 33e: 0301 addi t1,t1,0 + 340: 0900 addi s0,sp,144 + 342: 0000 unimp + 344: 0301 addi t1,t1,0 + 346: 0900 addi s0,sp,144 + 348: 0000 unimp + 34a: 0301 addi t1,t1,0 + 34c: 0900 addi s0,sp,144 + 34e: 0000 unimp + 350: 0301 addi t1,t1,0 + 352: 0900 addi s0,sp,144 354: 0004 0x4 - 356: 0501 addi a0,a0,0 - 358: 0003060b 0x3060b - 35c: 0009 c.nop 2 - 35e: 0100 addi s0,sp,128 - 360: 0405 addi s0,s0,1 - 362: 0306 slli t1,t1,0x1 - 364: 00040903 lb s2,0(s0) # fffeb000 <__BSS_END__+0x7ffd43d0> + 356: 0301 addi t1,t1,0 + 358: 0900 addi s0,sp,144 + 35a: 000c 0xc + 35c: 0301 addi t1,t1,0 + 35e: 0900 addi s0,sp,144 + 360: 0008 0x8 + 362: 0301 addi t1,t1,0 + 364: 0900 addi s0,sp,144 + 366: 0000 unimp 368: 0301 addi t1,t1,0 36a: 0900 addi s0,sp,144 - 36c: 0000 unimp + 36c: 0008 0x8 36e: 0301 addi t1,t1,0 370: 0900 addi s0,sp,144 - 372: 0000 unimp + 372: 0008 0x8 374: 0301 addi t1,t1,0 376: 0900 addi s0,sp,144 - 378: 0000 unimp + 378: 0004 0x4 37a: 0301 addi t1,t1,0 37c: 0900 addi s0,sp,144 - 37e: 0004 0x4 + 37e: 0008 0x8 380: 0301 addi t1,t1,0 382: 0900 addi s0,sp,144 - 384: 000c 0xc + 384: 0004 0x4 386: 0301 addi t1,t1,0 388: 0900 addi s0,sp,144 - 38a: 0008 0x8 + 38a: 0004 0x4 38c: 0301 addi t1,t1,0 38e: 0900 addi s0,sp,144 - 390: 0000 unimp + 390: 0008 0x8 392: 0301 addi t1,t1,0 394: 0900 addi s0,sp,144 - 396: 0008 0x8 + 396: 0004 0x4 398: 0301 addi t1,t1,0 39a: 0900 addi s0,sp,144 - 39c: 0008 0x8 + 39c: 0004 0x4 39e: 0301 addi t1,t1,0 3a0: 0900 addi s0,sp,144 - 3a2: 0004 0x4 + 3a2: 000c 0xc 3a4: 0301 addi t1,t1,0 3a6: 0900 addi s0,sp,144 - 3a8: 0008 0x8 + 3a8: 000c 0xc 3aa: 0301 addi t1,t1,0 3ac: 0900 addi s0,sp,144 - 3ae: 0004 0x4 + 3ae: 0000 unimp 3b0: 0301 addi t1,t1,0 3b2: 0900 addi s0,sp,144 - 3b4: 0004 0x4 + 3b4: 0008 0x8 3b6: 0301 addi t1,t1,0 3b8: 0900 addi s0,sp,144 3ba: 0008 0x8 @@ -41569,156 +41617,156 @@ Disassembly of section .debug_line: 3c6: 0004 0x4 3c8: 0301 addi t1,t1,0 3ca: 0900 addi s0,sp,144 - 3cc: 000c 0xc + 3cc: 0004 0x4 3ce: 0301 addi t1,t1,0 3d0: 0900 addi s0,sp,144 - 3d2: 000c 0xc + 3d2: 0000 unimp 3d4: 0301 addi t1,t1,0 3d6: 0900 addi s0,sp,144 - 3d8: 0000 unimp + 3d8: 0008 0x8 3da: 0301 addi t1,t1,0 3dc: 0900 addi s0,sp,144 - 3de: 0008 0x8 + 3de: 0000 unimp 3e0: 0301 addi t1,t1,0 - 3e2: 0900 addi s0,sp,144 - 3e4: 0008 0x8 - 3e6: 0301 addi t1,t1,0 - 3e8: 0900 addi s0,sp,144 - 3ea: 0004 0x4 - 3ec: 0301 addi t1,t1,0 - 3ee: 0900 addi s0,sp,144 - 3f0: 0004 0x4 - 3f2: 0301 addi t1,t1,0 - 3f4: 0900 addi s0,sp,144 - 3f6: 0004 0x4 - 3f8: 0301 addi t1,t1,0 - 3fa: 0900 addi s0,sp,144 - 3fc: 0000 unimp - 3fe: 0301 addi t1,t1,0 - 400: 0900 addi s0,sp,144 - 402: 0008 0x8 - 404: 0301 addi t1,t1,0 - 406: 0900 addi s0,sp,144 - 408: 0000 unimp - 40a: 0301 addi t1,t1,0 - 40c: 0901 addi s2,s2,0 - 40e: 0000 unimp - 410: 0501 addi a0,a0,0 - 412: fe03060b 0xfe03060b - 416: 0900 addi s0,sp,144 - 418: 0000 unimp - 41a: 0501 addi a0,a0,0 - 41c: 0304 addi s1,sp,384 - 41e: 7ef5 lui t4,0xffffd - 420: 0809 addi a6,a6,2 - 422: 0100 addi s0,sp,128 - 424: 0306 slli t1,t1,0x1 - 426: 0915 addi s2,s2,5 - 428: 0014 0x14 - 42a: 0501 addi a0,a0,0 - 42c: 00030607 0x30607 - 430: 0009 c.nop 2 - 432: 0100 addi s0,sp,128 - 434: 0605 addi a2,a2,1 - 436: 0306 slli t1,t1,0x1 - 438: 0901 addi s2,s2,0 - 43a: 0004 0x4 - 43c: 0501 addi a0,a0,0 - 43e: 0609 addi a2,a2,2 - 440: 00090003 lb zero,0(s2) - 444: 0100 addi s0,sp,128 - 446: 0405 addi s0,s0,1 - 448: 0306 slli t1,t1,0x1 + 3e2: 0901 addi s2,s2,0 + 3e4: 0000 unimp + 3e6: 0501 addi a0,a0,0 + 3e8: fe03060b 0xfe03060b + 3ec: 0900 addi s0,sp,144 + 3ee: 0000 unimp + 3f0: 0501 addi a0,a0,0 + 3f2: 0304 addi s1,sp,384 + 3f4: 7ef5 lui t4,0xffffd + 3f6: 0809 addi a6,a6,2 + 3f8: 0100 addi s0,sp,128 + 3fa: 0306 slli t1,t1,0x1 + 3fc: 0915 addi s2,s2,5 + 3fe: 0014 0x14 + 400: 0501 addi a0,a0,0 + 402: 00030607 0x30607 + 406: 0009 c.nop 2 + 408: 0100 addi s0,sp,128 + 40a: 0605 addi a2,a2,1 + 40c: 0306 slli t1,t1,0x1 + 40e: 0901 addi s2,s2,0 + 410: 0004 0x4 + 412: 0501 addi a0,a0,0 + 414: 0609 addi a2,a2,2 + 416: 00090003 lb zero,0(s2) + 41a: 0100 addi s0,sp,128 + 41c: 0405 addi s0,s0,1 + 41e: 0306 slli t1,t1,0x1 + 420: 0902 c.slli64 s2 + 422: 0008 0x8 + 424: 0301 addi t1,t1,0 + 426: 0900 addi s0,sp,144 + 428: 0000 unimp + 42a: 0301 addi t1,t1,0 + 42c: 0900 addi s0,sp,144 + 42e: 0000 unimp + 430: 0301 addi t1,t1,0 + 432: 0900 addi s0,sp,144 + 434: 0000 unimp + 436: 0301 addi t1,t1,0 + 438: 0900 addi s0,sp,144 + 43a: 0000 unimp + 43c: 0301 addi t1,t1,0 + 43e: 0900 addi s0,sp,144 + 440: 0014 0x14 + 442: 0301 addi t1,t1,0 + 444: 0900 addi s0,sp,144 + 446: 0018 0x18 + 448: 0301 addi t1,t1,0 44a: 0902 c.slli64 s2 - 44c: 0008 0x8 - 44e: 0301 addi t1,t1,0 - 450: 0900 addi s0,sp,144 - 452: 0000 unimp - 454: 0301 addi t1,t1,0 - 456: 0900 addi s0,sp,144 - 458: 0000 unimp - 45a: 0301 addi t1,t1,0 - 45c: 0900 addi s0,sp,144 - 45e: 0000 unimp - 460: 0301 addi t1,t1,0 - 462: 0900 addi s0,sp,144 - 464: 0000 unimp - 466: 0301 addi t1,t1,0 - 468: 0900 addi s0,sp,144 - 46a: 0014 0x14 - 46c: 0301 addi t1,t1,0 - 46e: 0900 addi s0,sp,144 - 470: 0018 0x18 - 472: 0301 addi t1,t1,0 - 474: 0902 c.slli64 s2 - 476: 0000 unimp - 478: 0501 addi a0,a0,0 - 47a: 00030607 0x30607 - 47e: 0009 c.nop 2 - 480: 0100 addi s0,sp,128 - 482: 0805 addi a6,a6,1 - 484: 0306 slli t1,t1,0x1 - 486: 0909 addi s2,s2,2 - 488: 0004 0x4 - 48a: 0501 addi a0,a0,0 - 48c: 0003060b 0x3060b - 490: 0009 c.nop 2 - 492: 0100 addi s0,sp,128 - 494: 0805 addi a6,a6,1 - 496: 0306 slli t1,t1,0x1 - 498: 0901 addi s2,s2,0 - 49a: 0004 0x4 - 49c: 0501 addi a0,a0,0 - 49e: 0003060b 0x3060b - 4a2: 0009 c.nop 2 - 4a4: 0100 addi s0,sp,128 - 4a6: 0805 addi a6,a6,1 - 4a8: 0306 slli t1,t1,0x1 - 4aa: 090d addi s2,s2,3 - 4ac: 0004 0x4 - 4ae: 0501 addi a0,a0,0 - 4b0: 0304 addi s1,sp,384 - 4b2: 0905 addi s2,s2,1 - 4b4: 0000 unimp + 44c: 0000 unimp + 44e: 0501 addi a0,a0,0 + 450: 00030607 0x30607 + 454: 0009 c.nop 2 + 456: 0100 addi s0,sp,128 + 458: 0805 addi a6,a6,1 + 45a: 0306 slli t1,t1,0x1 + 45c: 0909 addi s2,s2,2 + 45e: 0004 0x4 + 460: 0501 addi a0,a0,0 + 462: 0003060b 0x3060b + 466: 0009 c.nop 2 + 468: 0100 addi s0,sp,128 + 46a: 0805 addi a6,a6,1 + 46c: 0306 slli t1,t1,0x1 + 46e: 0901 addi s2,s2,0 + 470: 0004 0x4 + 472: 0501 addi a0,a0,0 + 474: 0003060b 0x3060b + 478: 0009 c.nop 2 + 47a: 0100 addi s0,sp,128 + 47c: 0805 addi a6,a6,1 + 47e: 0306 slli t1,t1,0x1 + 480: 090d addi s2,s2,3 + 482: 0004 0x4 + 484: 0501 addi a0,a0,0 + 486: 0304 addi s1,sp,384 + 488: 0905 addi s2,s2,1 + 48a: 0000 unimp + 48c: 0301 addi t1,t1,0 + 48e: 0900 addi s0,sp,144 + 490: 0000 unimp + 492: 0301 addi t1,t1,0 + 494: 0900 addi s0,sp,144 + 496: 0000 unimp + 498: 0301 addi t1,t1,0 + 49a: 0900 addi s0,sp,144 + 49c: 0000 unimp + 49e: 0301 addi t1,t1,0 + 4a0: 0900 addi s0,sp,144 + 4a2: 0004 0x4 + 4a4: 0301 addi t1,t1,0 + 4a6: 0900 addi s0,sp,144 + 4a8: 0008 0x8 + 4aa: 0301 addi t1,t1,0 + 4ac: 0900 addi s0,sp,144 + 4ae: 0008 0x8 + 4b0: 0301 addi t1,t1,0 + 4b2: 0900 addi s0,sp,144 + 4b4: 0004 0x4 4b6: 0301 addi t1,t1,0 4b8: 0900 addi s0,sp,144 - 4ba: 0000 unimp + 4ba: 000c 0xc 4bc: 0301 addi t1,t1,0 4be: 0900 addi s0,sp,144 4c0: 0000 unimp 4c2: 0301 addi t1,t1,0 4c4: 0900 addi s0,sp,144 - 4c6: 0000 unimp + 4c6: 0008 0x8 4c8: 0301 addi t1,t1,0 4ca: 0900 addi s0,sp,144 - 4cc: 0004 0x4 + 4cc: 0008 0x8 4ce: 0301 addi t1,t1,0 4d0: 0900 addi s0,sp,144 - 4d2: 0008 0x8 + 4d2: 0004 0x4 4d4: 0301 addi t1,t1,0 4d6: 0900 addi s0,sp,144 - 4d8: 0008 0x8 + 4d8: 0004 0x4 4da: 0301 addi t1,t1,0 4dc: 0900 addi s0,sp,144 - 4de: 0004 0x4 + 4de: 0008 0x8 4e0: 0301 addi t1,t1,0 4e2: 0900 addi s0,sp,144 - 4e4: 000c 0xc + 4e4: 0004 0x4 4e6: 0301 addi t1,t1,0 4e8: 0900 addi s0,sp,144 - 4ea: 0000 unimp + 4ea: 0004 0x4 4ec: 0301 addi t1,t1,0 4ee: 0900 addi s0,sp,144 - 4f0: 0008 0x8 + 4f0: 000c 0xc 4f2: 0301 addi t1,t1,0 4f4: 0900 addi s0,sp,144 - 4f6: 0008 0x8 + 4f6: 000c 0xc 4f8: 0301 addi t1,t1,0 4fa: 0900 addi s0,sp,144 - 4fc: 0004 0x4 + 4fc: 0000 unimp 4fe: 0301 addi t1,t1,0 500: 0900 addi s0,sp,144 - 502: 0004 0x4 + 502: 0008 0x8 504: 0301 addi t1,t1,0 506: 0900 addi s0,sp,144 508: 0008 0x8 @@ -41730,119 +41778,112 @@ Disassembly of section .debug_line: 514: 0004 0x4 516: 0301 addi t1,t1,0 518: 0900 addi s0,sp,144 - 51a: 000c 0xc + 51a: 0004 0x4 51c: 0301 addi t1,t1,0 51e: 0900 addi s0,sp,144 - 520: 000c 0xc + 520: 0000 unimp 522: 0301 addi t1,t1,0 524: 0900 addi s0,sp,144 - 526: 0000 unimp - 528: 0301 addi t1,t1,0 - 52a: 0900 addi s0,sp,144 - 52c: 0008 0x8 - 52e: 0301 addi t1,t1,0 - 530: 0900 addi s0,sp,144 - 532: 0008 0x8 - 534: 0301 addi t1,t1,0 - 536: 0900 addi s0,sp,144 - 538: 0004 0x4 - 53a: 0301 addi t1,t1,0 - 53c: 0900 addi s0,sp,144 - 53e: 0004 0x4 - 540: 0301 addi t1,t1,0 - 542: 0900 addi s0,sp,144 - 544: 0004 0x4 - 546: 0301 addi t1,t1,0 - 548: 0900 addi s0,sp,144 - 54a: 0000 unimp - 54c: 0301 addi t1,t1,0 - 54e: 0900 addi s0,sp,144 - 550: 0008 0x8 - 552: 0501 addi a0,a0,0 - 554: 00e30303 lb t1,14(t1) - 558: 0009 c.nop 2 - 55a: 0100 addi s0,sp,128 - 55c: 00090103 lb sp,0(s2) - 560: 0100 addi s0,sp,128 - 562: 0105 addi sp,sp,1 - 564: 0306 slli t1,t1,0x1 - 566: 00e1 addi ra,ra,24 - 568: 0009 c.nop 2 + 526: 0008 0x8 + 528: 0501 addi a0,a0,0 + 52a: 00e30303 lb t1,14(t1) + 52e: 0009 c.nop 2 + 530: 0100 addi s0,sp,128 + 532: 00090103 lb sp,0(s2) + 536: 0100 addi s0,sp,128 + 538: 0105 addi sp,sp,1 + 53a: 0306 slli t1,t1,0x1 + 53c: 00e1 addi ra,ra,24 + 53e: 0009 c.nop 2 + 540: 0100 addi s0,sp,128 + 542: 0405 addi s0,s0,1 + 544: 097e9d03 lh s10,151(t4) # ffffd097 <__BSS_END__+0x7ffe645b> + 548: 0004 0x4 + 54a: 0501 addi a0,a0,0 + 54c: 0608 addi a0,sp,768 + 54e: 14091203 lh tp,320(s2) + 552: 0100 addi s0,sp,128 + 554: 00090203 lb tp,0(s2) + 558: 0100 addi s0,sp,128 + 55a: 0b05 addi s6,s6,1 + 55c: 0306 slli t1,t1,0x1 + 55e: 0900 addi s0,sp,144 + 560: 0000 unimp + 562: 0501 addi a0,a0,0 + 564: 0608 addi a0,sp,768 + 566: 04090103 lb sp,64(s2) 56a: 0100 addi s0,sp,128 - 56c: 0405 addi s0,s0,1 - 56e: 097e9d03 lh s10,151(t4) # ffffd097 <__BSS_END__+0x7ffe6467> - 572: 0004 0x4 + 56c: 0b05 addi s6,s6,1 + 56e: 0306 slli t1,t1,0x1 + 570: 0900 addi s0,sp,144 + 572: 0000 unimp 574: 0501 addi a0,a0,0 576: 0608 addi a0,sp,768 - 578: 14091203 lh tp,320(s2) + 578: 04090103 lb sp,64(s2) 57c: 0100 addi s0,sp,128 - 57e: 00090203 lb tp,0(s2) - 582: 0100 addi s0,sp,128 - 584: 0b05 addi s6,s6,1 - 586: 0306 slli t1,t1,0x1 - 588: 0900 addi s0,sp,144 - 58a: 0000 unimp - 58c: 0501 addi a0,a0,0 - 58e: 0608 addi a0,sp,768 - 590: 04090103 lb sp,64(s2) - 594: 0100 addi s0,sp,128 - 596: 0b05 addi s6,s6,1 - 598: 0306 slli t1,t1,0x1 - 59a: 0900 addi s0,sp,144 - 59c: 0000 unimp + 57e: 0b05 addi s6,s6,1 + 580: 0306 slli t1,t1,0x1 + 582: 0901 addi s2,s2,0 + 584: 0000 unimp + 586: 0501 addi a0,a0,0 + 588: 0311 addi t1,t1,4 + 58a: 097f 0x97f + 58c: 0004 0x4 + 58e: 0501 addi a0,a0,0 + 590: 031e slli t1,t1,0x7 + 592: 0900 addi s0,sp,144 + 594: 0004 0x4 + 596: 0501 addi a0,a0,0 + 598: 0308 addi a0,sp,384 + 59a: 00040903 lb s2,0(s0) 59e: 0501 addi a0,a0,0 - 5a0: 0608 addi a0,sp,768 - 5a2: 04090103 lb sp,64(s2) - 5a6: 0100 addi s0,sp,128 - 5a8: 0b05 addi s6,s6,1 - 5aa: 0306 slli t1,t1,0x1 - 5ac: 0901 addi s2,s2,0 - 5ae: 0000 unimp - 5b0: 0501 addi a0,a0,0 - 5b2: 0311 addi t1,t1,4 - 5b4: 097f 0x97f - 5b6: 0004 0x4 - 5b8: 0501 addi a0,a0,0 - 5ba: 031e slli t1,t1,0x7 - 5bc: 0900 addi s0,sp,144 - 5be: 0004 0x4 - 5c0: 0501 addi a0,a0,0 - 5c2: 0308 addi a0,sp,384 - 5c4: 00040903 lb s2,0(s0) - 5c8: 0501 addi a0,a0,0 - 5ca: 097d030b 0x97d030b - 5ce: 0004 0x4 - 5d0: 0501 addi a0,a0,0 - 5d2: 0608 addi a0,sp,768 - 5d4: 04090103 lb sp,64(s2) + 5a0: 097d030b 0x97d030b + 5a4: 0004 0x4 + 5a6: 0501 addi a0,a0,0 + 5a8: 0608 addi a0,sp,768 + 5aa: 04090103 lb sp,64(s2) + 5ae: 0100 addi s0,sp,128 + 5b0: 00090203 lb tp,0(s2) + 5b4: 0100 addi s0,sp,128 + 5b6: 00090003 lb zero,0(s2) + 5ba: 0100 addi s0,sp,128 + 5bc: 00090003 lb zero,0(s2) + 5c0: 0100 addi s0,sp,128 + 5c2: 00090003 lb zero,0(s2) + 5c6: 0100 addi s0,sp,128 + 5c8: 00090003 lb zero,0(s2) + 5cc: 0100 addi s0,sp,128 + 5ce: 0c090003 lb zero,192(s2) + 5d2: 0100 addi s0,sp,128 + 5d4: 00090003 lb zero,0(s2) 5d8: 0100 addi s0,sp,128 - 5da: 00090203 lb tp,0(s2) + 5da: 08090003 lb zero,128(s2) 5de: 0100 addi s0,sp,128 - 5e0: 00090003 lb zero,0(s2) + 5e0: 0c090003 lb zero,192(s2) 5e4: 0100 addi s0,sp,128 5e6: 00090003 lb zero,0(s2) 5ea: 0100 addi s0,sp,128 - 5ec: 00090003 lb zero,0(s2) + 5ec: 08090003 lb zero,128(s2) 5f0: 0100 addi s0,sp,128 - 5f2: 00090003 lb zero,0(s2) + 5f2: 08090003 lb zero,128(s2) 5f6: 0100 addi s0,sp,128 - 5f8: 0c090003 lb zero,192(s2) + 5f8: 04090003 lb zero,64(s2) 5fc: 0100 addi s0,sp,128 - 5fe: 00090003 lb zero,0(s2) + 5fe: 04090003 lb zero,64(s2) 602: 0100 addi s0,sp,128 604: 08090003 lb zero,128(s2) 608: 0100 addi s0,sp,128 - 60a: 0c090003 lb zero,192(s2) + 60a: 04090003 lb zero,64(s2) 60e: 0100 addi s0,sp,128 - 610: 00090003 lb zero,0(s2) + 610: 04090003 lb zero,64(s2) 614: 0100 addi s0,sp,128 - 616: 08090003 lb zero,128(s2) + 616: 0c090003 lb zero,192(s2) 61a: 0100 addi s0,sp,128 61c: 08090003 lb zero,128(s2) 620: 0100 addi s0,sp,128 622: 04090003 lb zero,64(s2) 626: 0100 addi s0,sp,128 - 628: 04090003 lb zero,64(s2) + 628: 08090003 lb zero,128(s2) 62c: 0100 addi s0,sp,128 62e: 08090003 lb zero,128(s2) 632: 0100 addi s0,sp,128 @@ -41850,158 +41891,158 @@ Disassembly of section .debug_line: 638: 0100 addi s0,sp,128 63a: 04090003 lb zero,64(s2) 63e: 0100 addi s0,sp,128 - 640: 0c090003 lb zero,192(s2) + 640: 08090003 lb zero,128(s2) 644: 0100 addi s0,sp,128 646: 08090003 lb zero,128(s2) 64a: 0100 addi s0,sp,128 64c: 04090003 lb zero,64(s2) 650: 0100 addi s0,sp,128 - 652: 08090003 lb zero,128(s2) - 656: 0100 addi s0,sp,128 - 658: 08090003 lb zero,128(s2) - 65c: 0100 addi s0,sp,128 - 65e: 04090003 lb zero,64(s2) - 662: 0100 addi s0,sp,128 - 664: 04090003 lb zero,64(s2) - 668: 0100 addi s0,sp,128 - 66a: 08090003 lb zero,128(s2) - 66e: 0100 addi s0,sp,128 - 670: 08090003 lb zero,128(s2) - 674: 0100 addi s0,sp,128 - 676: 04090003 lb zero,64(s2) - 67a: 0100 addi s0,sp,128 - 67c: 0705 addi a4,a4,1 - 67e: 04091503 lh a0,64(s2) + 652: 0705 addi a4,a4,1 + 654: 04091503 lh a0,64(s2) + 658: 0100 addi s0,sp,128 + 65a: 0a05 addi s4,s4,1 + 65c: 0306 slli t1,t1,0x1 + 65e: 0900 addi s0,sp,144 + 660: 0000 unimp + 662: 0501 addi a0,a0,0 + 664: 0604 addi s1,sp,768 + 666: 04091303 lh t1,64(s2) + 66a: 0100 addi s0,sp,128 + 66c: 00090003 lb zero,0(s2) + 670: 0100 addi s0,sp,128 + 672: 00090003 lb zero,0(s2) + 676: 0100 addi s0,sp,128 + 678: 00090003 lb zero,0(s2) + 67c: 0100 addi s0,sp,128 + 67e: 00090003 lb zero,0(s2) 682: 0100 addi s0,sp,128 - 684: 0a05 addi s4,s4,1 - 686: 0306 slli t1,t1,0x1 - 688: 0900 addi s0,sp,144 - 68a: 0000 unimp - 68c: 0501 addi a0,a0,0 - 68e: 0604 addi s1,sp,768 - 690: 04091303 lh t1,64(s2) + 684: 14090003 lb zero,320(s2) + 688: 0100 addi s0,sp,128 + 68a: 20090003 lb zero,512(s2) + 68e: 0100 addi s0,sp,128 + 690: 00090103 lb sp,0(s2) 694: 0100 addi s0,sp,128 - 696: 00090003 lb zero,0(s2) - 69a: 0100 addi s0,sp,128 - 69c: 00090003 lb zero,0(s2) - 6a0: 0100 addi s0,sp,128 - 6a2: 00090003 lb zero,0(s2) + 696: 0705 addi a4,a4,1 + 698: 0306 slli t1,t1,0x1 + 69a: 0900 addi s0,sp,144 + 69c: 0000 unimp + 69e: 0501 addi a0,a0,0 + 6a0: 0608 addi a0,sp,768 + 6a2: 04090a03 lb s4,64(s2) 6a6: 0100 addi s0,sp,128 - 6a8: 00090003 lb zero,0(s2) - 6ac: 0100 addi s0,sp,128 - 6ae: 14090003 lb zero,320(s2) - 6b2: 0100 addi s0,sp,128 - 6b4: 20090003 lb zero,512(s2) - 6b8: 0100 addi s0,sp,128 - 6ba: 00090103 lb sp,0(s2) - 6be: 0100 addi s0,sp,128 - 6c0: 0705 addi a4,a4,1 - 6c2: 0306 slli t1,t1,0x1 - 6c4: 0900 addi s0,sp,144 - 6c6: 0000 unimp - 6c8: 0501 addi a0,a0,0 - 6ca: 0608 addi a0,sp,768 - 6cc: 04090a03 lb s4,64(s2) - 6d0: 0100 addi s0,sp,128 - 6d2: 0306 slli t1,t1,0x1 - 6d4: 0902 c.slli64 s2 - 6d6: 0000 unimp - 6d8: 0501 addi a0,a0,0 - 6da: 097e030b 0x97e030b - 6de: 0004 0x4 - 6e0: 0501 addi a0,a0,0 - 6e2: 0314 addi a3,sp,384 - 6e4: 0900 addi s0,sp,144 - 6e6: 0004 0x4 - 6e8: 0501 addi a0,a0,0 - 6ea: 0304 addi s1,sp,384 - 6ec: 0975 addi s2,s2,29 - 6ee: 000c 0xc - 6f0: 0501 addi a0,a0,0 - 6f2: 0608 addi a0,sp,768 - 6f4: 14091e03 lh t3,320(s2) - 6f8: 0100 addi s0,sp,128 - 6fa: 00090303 lb t1,0(s2) - 6fe: 0100 addi s0,sp,128 - 700: 00090203 lb tp,0(s2) - 704: 0100 addi s0,sp,128 - 706: 1e05 addi t3,t3,-31 - 708: 0306 slli t1,t1,0x1 - 70a: 0900 addi s0,sp,144 - 70c: 0000 unimp - 70e: 0501 addi a0,a0,0 - 710: 0311 addi t1,t1,4 - 712: 0900 addi s0,sp,144 - 714: 0004 0x4 - 716: 0501 addi a0,a0,0 - 718: 0900030b 0x900030b - 71c: 0004 0x4 + 6a8: 0306 slli t1,t1,0x1 + 6aa: 0902 c.slli64 s2 + 6ac: 0000 unimp + 6ae: 0501 addi a0,a0,0 + 6b0: 097e030b 0x97e030b + 6b4: 0004 0x4 + 6b6: 0501 addi a0,a0,0 + 6b8: 0314 addi a3,sp,384 + 6ba: 0900 addi s0,sp,144 + 6bc: 0004 0x4 + 6be: 0501 addi a0,a0,0 + 6c0: 0304 addi s1,sp,384 + 6c2: 0975 addi s2,s2,29 + 6c4: 000c 0xc + 6c6: 0501 addi a0,a0,0 + 6c8: 0608 addi a0,sp,768 + 6ca: 14091e03 lh t3,320(s2) + 6ce: 0100 addi s0,sp,128 + 6d0: 00090303 lb t1,0(s2) + 6d4: 0100 addi s0,sp,128 + 6d6: 00090203 lb tp,0(s2) + 6da: 0100 addi s0,sp,128 + 6dc: 1e05 addi t3,t3,-31 + 6de: 0306 slli t1,t1,0x1 + 6e0: 0900 addi s0,sp,144 + 6e2: 0000 unimp + 6e4: 0501 addi a0,a0,0 + 6e6: 0311 addi t1,t1,4 + 6e8: 0900 addi s0,sp,144 + 6ea: 0004 0x4 + 6ec: 0501 addi a0,a0,0 + 6ee: 0900030b 0x900030b + 6f2: 0004 0x4 + 6f4: 0501 addi a0,a0,0 + 6f6: 0608 addi a0,sp,768 + 6f8: 04090103 lb sp,64(s2) + 6fc: 0100 addi s0,sp,128 + 6fe: 0306 slli t1,t1,0x1 + 700: 0905 addi s2,s2,1 + 702: 0000 unimp + 704: 0501 addi a0,a0,0 + 706: 097b030b 0x97b030b + 70a: 0004 0x4 + 70c: 0501 addi a0,a0,0 + 70e: 0608 addi a0,sp,768 + 710: 04090103 lb sp,64(s2) + 714: 0100 addi s0,sp,128 + 716: 0b05 addi s6,s6,1 + 718: 0306 slli t1,t1,0x1 + 71a: 0900 addi s0,sp,144 + 71c: 0000 unimp 71e: 0501 addi a0,a0,0 720: 0608 addi a0,sp,768 722: 04090103 lb sp,64(s2) 726: 0100 addi s0,sp,128 728: 0306 slli t1,t1,0x1 - 72a: 0905 addi s2,s2,1 - 72c: 0000 unimp + 72a: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> 72e: 0501 addi a0,a0,0 - 730: 097b030b 0x97b030b + 730: 0311 addi t1,t1,4 + 732: 097d addi s2,s2,31 734: 0004 0x4 736: 0501 addi a0,a0,0 - 738: 0608 addi a0,sp,768 - 73a: 04090103 lb sp,64(s2) - 73e: 0100 addi s0,sp,128 - 740: 0b05 addi s6,s6,1 - 742: 0306 slli t1,t1,0x1 - 744: 0900 addi s0,sp,144 - 746: 0000 unimp - 748: 0501 addi a0,a0,0 - 74a: 0608 addi a0,sp,768 - 74c: 04090103 lb sp,64(s2) - 750: 0100 addi s0,sp,128 - 752: 0306 slli t1,t1,0x1 - 754: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> - 758: 0501 addi a0,a0,0 - 75a: 0311 addi t1,t1,4 - 75c: 097d addi s2,s2,31 - 75e: 0004 0x4 - 760: 0501 addi a0,a0,0 - 762: 031e slli t1,t1,0x7 - 764: 0900 addi s0,sp,144 - 766: 0004 0x4 - 768: 0501 addi a0,a0,0 - 76a: 0900030b 0x900030b - 76e: 0004 0x4 - 770: 0501 addi a0,a0,0 - 772: 0608 addi a0,sp,768 - 774: 04090103 lb sp,64(s2) + 738: 031e slli t1,t1,0x7 + 73a: 0900 addi s0,sp,144 + 73c: 0004 0x4 + 73e: 0501 addi a0,a0,0 + 740: 0900030b 0x900030b + 744: 0004 0x4 + 746: 0501 addi a0,a0,0 + 748: 0608 addi a0,sp,768 + 74a: 04090103 lb sp,64(s2) + 74e: 0100 addi s0,sp,128 + 750: 00090203 lb tp,0(s2) + 754: 0100 addi s0,sp,128 + 756: 00090003 lb zero,0(s2) + 75a: 0100 addi s0,sp,128 + 75c: 00090003 lb zero,0(s2) + 760: 0100 addi s0,sp,128 + 762: 00090003 lb zero,0(s2) + 766: 0100 addi s0,sp,128 + 768: 00090003 lb zero,0(s2) + 76c: 0100 addi s0,sp,128 + 76e: 08090003 lb zero,128(s2) + 772: 0100 addi s0,sp,128 + 774: 00090003 lb zero,0(s2) 778: 0100 addi s0,sp,128 - 77a: 00090203 lb tp,0(s2) + 77a: 08090003 lb zero,128(s2) 77e: 0100 addi s0,sp,128 - 780: 00090003 lb zero,0(s2) + 780: 0c090003 lb zero,192(s2) 784: 0100 addi s0,sp,128 786: 00090003 lb zero,0(s2) 78a: 0100 addi s0,sp,128 - 78c: 00090003 lb zero,0(s2) + 78c: 08090003 lb zero,128(s2) 790: 0100 addi s0,sp,128 - 792: 00090003 lb zero,0(s2) + 792: 08090003 lb zero,128(s2) 796: 0100 addi s0,sp,128 - 798: 08090003 lb zero,128(s2) + 798: 04090003 lb zero,64(s2) 79c: 0100 addi s0,sp,128 - 79e: 00090003 lb zero,0(s2) + 79e: 04090003 lb zero,64(s2) 7a2: 0100 addi s0,sp,128 7a4: 08090003 lb zero,128(s2) 7a8: 0100 addi s0,sp,128 - 7aa: 0c090003 lb zero,192(s2) + 7aa: 04090003 lb zero,64(s2) 7ae: 0100 addi s0,sp,128 - 7b0: 00090003 lb zero,0(s2) + 7b0: 04090003 lb zero,64(s2) 7b4: 0100 addi s0,sp,128 - 7b6: 08090003 lb zero,128(s2) + 7b6: 04090003 lb zero,64(s2) 7ba: 0100 addi s0,sp,128 7bc: 08090003 lb zero,128(s2) 7c0: 0100 addi s0,sp,128 - 7c2: 04090003 lb zero,64(s2) + 7c2: 0c090003 lb zero,192(s2) 7c6: 0100 addi s0,sp,128 - 7c8: 04090003 lb zero,64(s2) + 7c8: 08090003 lb zero,128(s2) 7cc: 0100 addi s0,sp,128 7ce: 08090003 lb zero,128(s2) 7d2: 0100 addi s0,sp,128 @@ -42009,52 +42050,52 @@ Disassembly of section .debug_line: 7d8: 0100 addi s0,sp,128 7da: 04090003 lb zero,64(s2) 7de: 0100 addi s0,sp,128 - 7e0: 04090003 lb zero,64(s2) + 7e0: 08090003 lb zero,128(s2) 7e4: 0100 addi s0,sp,128 - 7e6: 08090003 lb zero,128(s2) - 7ea: 0100 addi s0,sp,128 - 7ec: 0c090003 lb zero,192(s2) - 7f0: 0100 addi s0,sp,128 - 7f2: 08090003 lb zero,128(s2) - 7f6: 0100 addi s0,sp,128 - 7f8: 08090003 lb zero,128(s2) - 7fc: 0100 addi s0,sp,128 - 7fe: 04090003 lb zero,64(s2) - 802: 0100 addi s0,sp,128 - 804: 04090003 lb zero,64(s2) - 808: 0100 addi s0,sp,128 - 80a: 08090003 lb zero,128(s2) - 80e: 0100 addi s0,sp,128 - 810: 0306 slli t1,t1,0x1 - 812: 0901 addi s2,s2,0 - 814: 0004 0x4 - 816: 0301 addi t1,t1,0 - 818: 097f 0x97f - 81a: 0004 0x4 - 81c: 0301 addi t1,t1,0 - 81e: 0901 addi s2,s2,0 - 820: 0004 0x4 - 822: 0301 addi t1,t1,0 - 824: 097f 0x97f - 826: 0008 0x8 - 828: 0601 addi a2,a2,0 - 82a: 04090003 lb zero,64(s2) + 7e6: 0306 slli t1,t1,0x1 + 7e8: 0901 addi s2,s2,0 + 7ea: 0004 0x4 + 7ec: 0301 addi t1,t1,0 + 7ee: 097f 0x97f + 7f0: 0004 0x4 + 7f2: 0301 addi t1,t1,0 + 7f4: 0901 addi s2,s2,0 + 7f6: 0004 0x4 + 7f8: 0301 addi t1,t1,0 + 7fa: 097f 0x97f + 7fc: 0008 0x8 + 7fe: 0601 addi a2,a2,0 + 800: 04090003 lb zero,64(s2) + 804: 0100 addi s0,sp,128 + 806: 00090003 lb zero,0(s2) + 80a: 0100 addi s0,sp,128 + 80c: 00090003 lb zero,0(s2) + 810: 0100 addi s0,sp,128 + 812: 00090103 lb sp,0(s2) + 816: 0100 addi s0,sp,128 + 818: 00090003 lb zero,0(s2) + 81c: 0100 addi s0,sp,128 + 81e: 00090003 lb zero,0(s2) + 822: 0100 addi s0,sp,128 + 824: 00090003 lb zero,0(s2) + 828: 0100 addi s0,sp,128 + 82a: 00090003 lb zero,0(s2) 82e: 0100 addi s0,sp,128 - 830: 00090003 lb zero,0(s2) + 830: 08090003 lb zero,128(s2) 834: 0100 addi s0,sp,128 836: 00090003 lb zero,0(s2) 83a: 0100 addi s0,sp,128 - 83c: 00090103 lb sp,0(s2) + 83c: 04090003 lb zero,64(s2) 840: 0100 addi s0,sp,128 - 842: 00090003 lb zero,0(s2) + 842: 04090003 lb zero,64(s2) 846: 0100 addi s0,sp,128 848: 00090003 lb zero,0(s2) 84c: 0100 addi s0,sp,128 - 84e: 00090003 lb zero,0(s2) + 84e: 04090003 lb zero,64(s2) 852: 0100 addi s0,sp,128 - 854: 00090003 lb zero,0(s2) + 854: 14090003 lb zero,320(s2) 858: 0100 addi s0,sp,128 - 85a: 08090003 lb zero,128(s2) + 85a: 00090003 lb zero,0(s2) 85e: 0100 addi s0,sp,128 860: 00090003 lb zero,0(s2) 864: 0100 addi s0,sp,128 @@ -42062,593 +42103,602 @@ Disassembly of section .debug_line: 86a: 0100 addi s0,sp,128 86c: 04090003 lb zero,64(s2) 870: 0100 addi s0,sp,128 - 872: 00090003 lb zero,0(s2) + 872: 08090003 lb zero,128(s2) 876: 0100 addi s0,sp,128 - 878: 04090003 lb zero,64(s2) + 878: 00090003 lb zero,0(s2) 87c: 0100 addi s0,sp,128 - 87e: 14090003 lb zero,320(s2) + 87e: 00090203 lb tp,0(s2) 882: 0100 addi s0,sp,128 - 884: 00090003 lb zero,0(s2) - 888: 0100 addi s0,sp,128 - 88a: 00090003 lb zero,0(s2) - 88e: 0100 addi s0,sp,128 - 890: 04090003 lb zero,64(s2) - 894: 0100 addi s0,sp,128 - 896: 04090003 lb zero,64(s2) - 89a: 0100 addi s0,sp,128 - 89c: 08090003 lb zero,128(s2) - 8a0: 0100 addi s0,sp,128 - 8a2: 00090003 lb zero,0(s2) - 8a6: 0100 addi s0,sp,128 - 8a8: 00090203 lb tp,0(s2) - 8ac: 0100 addi s0,sp,128 - 8ae: 0b05 addi s6,s6,1 - 8b0: 0306 slli t1,t1,0x1 - 8b2: 0900 addi s0,sp,144 - 8b4: 0000 unimp - 8b6: 0501 addi a0,a0,0 - 8b8: 0314 addi a3,sp,384 - 8ba: 0900 addi s0,sp,144 - 8bc: 0004 0x4 - 8be: 0501 addi a0,a0,0 - 8c0: 0308 addi a0,sp,384 - 8c2: 097e slli s2,s2,0x1f - 8c4: 0004 0x4 - 8c6: 0501 addi a0,a0,0 - 8c8: 097d030b 0x97d030b - 8cc: 0014 0x14 + 884: 0b05 addi s6,s6,1 + 886: 0306 slli t1,t1,0x1 + 888: 0900 addi s0,sp,144 + 88a: 0000 unimp + 88c: 0501 addi a0,a0,0 + 88e: 0314 addi a3,sp,384 + 890: 0900 addi s0,sp,144 + 892: 0004 0x4 + 894: 0501 addi a0,a0,0 + 896: 0308 addi a0,sp,384 + 898: 097e slli s2,s2,0x1f + 89a: 0004 0x4 + 89c: 0501 addi a0,a0,0 + 89e: 097d030b 0x97d030b + 8a2: 0014 0x14 + 8a4: 0501 addi a0,a0,0 + 8a6: 0308 addi a0,sp,384 + 8a8: 00040903 lb s2,0(s0) + 8ac: 0501 addi a0,a0,0 + 8ae: 0908030b 0x908030b + 8b2: 0004 0x4 + 8b4: 0501 addi a0,a0,0 + 8b6: 0321 addi t1,t1,8 + 8b8: 097a slli s2,s2,0x1e + 8ba: 0004 0x4 + 8bc: 0501 addi a0,a0,0 + 8be: 0605 addi a2,a2,1 + 8c0: 04090203 lb tp,64(s2) + 8c4: 0100 addi s0,sp,128 + 8c6: 0705 addi a4,a4,1 + 8c8: 0306 slli t1,t1,0x1 + 8ca: 0900 addi s0,sp,144 + 8cc: 0000 unimp 8ce: 0501 addi a0,a0,0 - 8d0: 0308 addi a0,sp,384 - 8d2: 00040903 lb s2,0(s0) - 8d6: 0501 addi a0,a0,0 - 8d8: 0908030b 0x908030b - 8dc: 0004 0x4 - 8de: 0501 addi a0,a0,0 - 8e0: 0321 addi t1,t1,8 - 8e2: 097a slli s2,s2,0x1e - 8e4: 0004 0x4 - 8e6: 0501 addi a0,a0,0 - 8e8: 0605 addi a2,a2,1 - 8ea: 04090203 lb tp,64(s2) + 8d0: 0605 addi a2,a2,1 + 8d2: 04090103 lb sp,64(s2) + 8d6: 0100 addi s0,sp,128 + 8d8: 00090003 lb zero,0(s2) + 8dc: 0100 addi s0,sp,128 + 8de: 00090003 lb zero,0(s2) + 8e2: 0100 addi s0,sp,128 + 8e4: 00090003 lb zero,0(s2) + 8e8: 0100 addi s0,sp,128 + 8ea: 00090003 lb zero,0(s2) 8ee: 0100 addi s0,sp,128 8f0: 0705 addi a4,a4,1 8f2: 0306 slli t1,t1,0x1 - 8f4: 0900 addi s0,sp,144 - 8f6: 0000 unimp - 8f8: 0501 addi a0,a0,0 - 8fa: 0605 addi a2,a2,1 - 8fc: 04090103 lb sp,64(s2) - 900: 0100 addi s0,sp,128 - 902: 00090003 lb zero,0(s2) - 906: 0100 addi s0,sp,128 - 908: 00090003 lb zero,0(s2) - 90c: 0100 addi s0,sp,128 - 90e: 00090003 lb zero,0(s2) - 912: 0100 addi s0,sp,128 - 914: 00090003 lb zero,0(s2) - 918: 0100 addi s0,sp,128 - 91a: 0705 addi a4,a4,1 - 91c: 0306 slli t1,t1,0x1 - 91e: 00040943 fmadd.s fs2,fs0,ft0,ft0,rne - 922: 0301 addi t1,t1,0 - 924: 097f 0x97f - 926: 0004 0x4 - 928: 0901 addi s2,s2,0 - 92a: 0008 0x8 - 92c: 0100 addi s0,sp,128 - 92e: c901 beqz a0,93e <_start-0x7ffff6c2> - 930: 0009 c.nop 2 - 932: 0300 addi s0,sp,384 - 934: 2700 fld fs0,8(a4) - 936: 0002 c.slli64 zero - 938: 0100 addi s0,sp,128 - 93a: fb01 bnez a4,84a <_start-0x7ffff7b6> - 93c: 0d0e slli s10,s10,0x3 - 93e: 0100 addi s0,sp,128 - 940: 0101 addi sp,sp,0 - 942: 0001 nop - 944: 0000 unimp - 946: 0001 nop - 948: 0100 addi s0,sp,128 - 94a: 2e2e fld ft8,200(sp) - 94c: 2f2e2e2f 0x2f2e2e2f - 950: 2e2e fld ft8,200(sp) - 952: 2f2e2e2f 0x2f2e2e2f - 956: 6972 flw fs2,28(sp) - 958: 2d766373 csrrsi t1,0x2d7,12 - 95c: 2f636367 0x2f636367 - 960: 696c flw fa1,84(a0) - 962: 6762 flw fa4,24(sp) - 964: 2f006363 bltu zero,a6,c4a <_start-0x7ffff3b6> - 968: 6f68 flw fa0,92(a4) - 96a: 656d lui a0,0x1b - 96c: 7261662f 0x7261662f - 970: 7365 lui t1,0xffff9 - 972: 636f442f 0x636f442f - 976: 6d75 lui s10,0x1d - 978: 6e65 lui t3,0x19 - 97a: 7374 flw fa3,100(a4) - 97c: 636f702f 0x636f702f - 980: 5f6c lw a1,124(a4) - 982: 6564 flw fs1,76(a0) - 984: 2f70 fld fa2,216(a4) - 986: 6972 flw fs2,28(sp) - 988: 2d766373 csrrsi t1,0x2d7,12 - 98c: 2d756e67 0x2d756e67 - 990: 6f74 flw fa3,92(a4) - 992: 68636c6f jal s8,37018 <_start-0x7ffc8fe8> - 996: 6961 lui s2,0x18 - 998: 2f6e fld ft10,216(sp) - 99a: 7562 flw fa0,56(sp) - 99c: 6c69 lui s8,0x1a - 99e: 2f64 fld fs1,216(a4) - 9a0: 7562 flw fa0,56(sp) - 9a2: 6c69 lui s8,0x1a - 9a4: 2d64 fld fs1,216(a0) - 9a6: 2d636367 0x2d636367 - 9aa: 656e flw fa0,216(sp) - 9ac: 62696c77 0x62696c77 - 9b0: 732d lui t1,0xfffeb - 9b2: 6174 flw fa3,68(a0) - 9b4: 2f326567 0x2f326567 - 9b8: 2f636367 0x2f636367 - 9bc: 6e69 lui t3,0x1a - 9be: 64756c63 bltu a0,t2,1016 <_start-0x7fffefea> - 9c2: 0065 c.nop 25 - 9c4: 6d6f682f 0x6d6f682f - 9c8: 2f65 jal 1180 <_start-0x7fffee80> - 9ca: 6166 flw ft2,88(sp) - 9cc: 6572 flw fa0,28(sp) - 9ce: 65642f73 csrrs t5,0x656,s0 - 9d2: 2f76 fld ft10,344(sp) + 8f4: 00040943 fmadd.s fs2,fs0,ft0,ft0,rne + 8f8: 0301 addi t1,t1,0 + 8fa: 097f 0x97f + 8fc: 0004 0x4 + 8fe: 0901 addi s2,s2,0 + 900: 0008 0x8 + 902: 0100 addi s0,sp,128 + 904: 9f01 0x9f01 + 906: 0009 c.nop 2 + 908: 0300 addi s0,sp,384 + 90a: fd00 fsw fs0,56(a0) + 90c: 0001 nop + 90e: 0100 addi s0,sp,128 + 910: fb01 bnez a4,820 <_start-0x7ffff7e0> + 912: 0d0e slli s10,s10,0x3 + 914: 0100 addi s0,sp,128 + 916: 0101 addi sp,sp,0 + 918: 0001 nop + 91a: 0000 unimp + 91c: 0001 nop + 91e: 0100 addi s0,sp,128 + 920: 2e2e fld ft8,200(sp) + 922: 2f2e2e2f 0x2f2e2e2f + 926: 2e2e fld ft8,200(sp) + 928: 2f2e2e2f 0x2f2e2e2f + 92c: 6972 flw fs2,28(sp) + 92e: 2d766373 csrrsi t1,0x2d7,12 + 932: 2f636367 0x2f636367 + 936: 696c flw fa1,84(a0) + 938: 6762 flw fa4,24(sp) + 93a: 2f006363 bltu zero,a6,c20 <_start-0x7ffff3e0> + 93e: 7355 lui t1,0xffff5 + 940: 7265 lui tp,0xffff9 + 942: 65642f73 csrrs t5,0x656,s0 + 946: 6f6d lui t5,0x1b + 948: 636f442f 0x636f442f + 94c: 6d75 lui s10,0x1d + 94e: 6e65 lui t3,0x19 + 950: 7374 flw fa3,100(a4) + 952: 77656e2f 0x77656e2f + 956: 6f70 flw fa2,92(a4) + 958: 2f766c63 bltu a2,s7,c50 <_start-0x7ffff3b0> + 95c: 6972 flw fs2,28(sp) + 95e: 2d766373 csrrsi t1,0x2d7,12 + 962: 2d756e67 0x2d756e67 + 966: 6f74 flw fa3,92(a4) + 968: 68636c6f jal s8,36fee <_start-0x7ffc9012> + 96c: 6961 lui s2,0x18 + 96e: 2f6e fld ft10,216(sp) + 970: 7562 flw fa0,56(sp) + 972: 6c69 lui s8,0x1a + 974: 2f64 fld fs1,216(a4) + 976: 7562 flw fa0,56(sp) + 978: 6c69 lui s8,0x1a + 97a: 2d64 fld fs1,216(a0) + 97c: 2d636367 0x2d636367 + 980: 656e flw fa0,216(sp) + 982: 62696c77 0x62696c77 + 986: 732d lui t1,0xfffeb + 988: 6174 flw fa3,68(a0) + 98a: 2f326567 0x2f326567 + 98e: 2f636367 0x2f636367 + 992: 6e69 lui t3,0x1a + 994: 64756c63 bltu a0,t2,fec <_start-0x7ffff014> + 998: 0065 c.nop 25 + 99a: 74706f2f 0x74706f2f + 99e: 7369722f 0x7369722f + 9a2: 6e2d7663 bgeu s10,sp,108e <_start-0x7fffef72> + 9a6: 7765 lui a4,0xffff9 + 9a8: 6f72642f 0x6f72642f + 9ac: 7370 flw fa2,100(a4) + 9ae: 7369722f 0x7369722f + 9b2: 32337663 bgeu t1,gp,cde <_start-0x7ffff322> + 9b6: 752d lui a0,0xfffeb + 9b8: 6b6e flw fs6,216(sp) + 9ba: 6f6e flw ft10,216(sp) + 9bc: 652d6e77 0x652d6e77 + 9c0: 666c flw fa1,76(a2) + 9c2: 636e692f 0x636e692f + 9c6: 756c flw fa1,108(a0) + 9c8: 6564 flw fs1,76(a0) + 9ca: 7379732f 0x7379732f + 9ce: 2f00 fld fs0,24(a4) + 9d0: 2f74706f j 484c6 <_start-0x7ffb7b3a> 9d4: 6972 flw fs2,28(sp) 9d6: 2d766373 csrrsi t1,0x2d7,12 - 9da: 2d756e67 0x2d756e67 - 9de: 6f74 flw fa3,92(a4) - 9e0: 68636c6f jal s8,37066 <_start-0x7ffc8f9a> - 9e4: 6961 lui s2,0x18 - 9e6: 2f6e fld ft10,216(sp) - 9e8: 7264 flw fs1,100(a2) - 9ea: 2f73706f j 384e0 <_start-0x7ffc7b20> - 9ee: 6972 flw fs2,28(sp) - 9f0: 33766373 csrrsi t1,mhpmevent23,12 - 9f4: 2d32 fld fs10,264(sp) - 9f6: 6e75 lui t3,0x1d - 9f8: 776f6e6b 0x776f6e6b - 9fc: 2d6e fld fs10,216(sp) - 9fe: 6c65 lui s8,0x19 - a00: 2f66 fld ft10,88(sp) - a02: 6e69 lui t3,0x1a - a04: 64756c63 bltu a0,t2,105c <_start-0x7fffefa4> - a08: 2f65 jal 11c0 <_start-0x7fffee40> - a0a: 00737973 csrrci s2,0x7,6 - a0e: 6d6f682f 0x6d6f682f - a12: 2f65 jal 11ca <_start-0x7fffee36> - a14: 6166 flw ft2,88(sp) - a16: 6572 flw fa0,28(sp) - a18: 65642f73 csrrs t5,0x656,s0 - a1c: 2f76 fld ft10,344(sp) - a1e: 6972 flw fs2,28(sp) - a20: 2d766373 csrrsi t1,0x2d7,12 - a24: 2d756e67 0x2d756e67 - a28: 6f74 flw fa3,92(a4) - a2a: 68636c6f jal s8,370b0 <_start-0x7ffc8f50> - a2e: 6961 lui s2,0x18 - a30: 2f6e fld ft10,216(sp) - a32: 7264 flw fs1,100(a2) - a34: 2f73706f j 3852a <_start-0x7ffc7ad6> - a38: 6972 flw fs2,28(sp) - a3a: 33766373 csrrsi t1,mhpmevent23,12 - a3e: 2d32 fld fs10,264(sp) - a40: 6e75 lui t3,0x1d - a42: 776f6e6b 0x776f6e6b - a46: 2d6e fld fs10,216(sp) - a48: 6c65 lui s8,0x19 - a4a: 2f66 fld ft10,88(sp) - a4c: 6e69 lui t3,0x1a - a4e: 64756c63 bltu a0,t2,10a6 <_start-0x7fffef5a> - a52: 0065 c.nop 25 - a54: 2e2e fld ft8,200(sp) - a56: 2f2e2e2f 0x2f2e2e2f - a5a: 2e2e fld ft8,200(sp) - a5c: 2f2e2e2f 0x2f2e2e2f - a60: 6972 flw fs2,28(sp) - a62: 2d766373 csrrsi t1,0x2d7,12 - a66: 2f636367 0x2f636367 - a6a: 696c flw fa1,84(a0) - a6c: 6762 flw fa4,24(sp) - a6e: 2e2f6363 bltu t5,sp,d54 <_start-0x7ffff2ac> - a72: 2f2e fld ft10,200(sp) - a74: 6e69 lui t3,0x1a - a76: 64756c63 bltu a0,t2,10ce <_start-0x7fffef32> - a7a: 0065 c.nop 25 - a7c: 2e2e fld ft8,200(sp) - a7e: 2f2e2e2f 0x2f2e2e2f - a82: 2e2e fld ft8,200(sp) - a84: 2f2e2e2f 0x2f2e2e2f - a88: 6972 flw fs2,28(sp) - a8a: 2d766373 csrrsi t1,0x2d7,12 - a8e: 2f636367 0x2f636367 - a92: 696c flw fa1,84(a0) - a94: 6762 flw fa4,24(sp) - a96: 2e2f6363 bltu t5,sp,d7c <_start-0x7ffff284> - a9a: 2f2e fld ft10,200(sp) - a9c: 2f636367 0x2f636367 - aa0: 666e6f63 bltu t3,t1,111e <_start-0x7fffeee2> - aa4: 6769 lui a4,0x1a - aa6: 7369722f 0x7369722f - aaa: 2e007663 bgeu zero,zero,d96 <_start-0x7ffff26a> - aae: 2f2e fld ft10,200(sp) - ab0: 2e2e fld ft8,200(sp) - ab2: 672f2e2f amoand.w.aqrl t3,s2,(t5) - ab6: 00006363 bltu zero,zero,abc <_start-0x7ffff544> - aba: 696c flw fa1,84(a0) - abc: 6762 flw fa4,24(sp) - abe: 2e326363 bltu tp,gp,da4 <_start-0x7ffff25c> - ac2: 00010063 beqz sp,ac2 <_start-0x7ffff53e> - ac6: 7300 flw fs0,32(a4) - ac8: 6474 flw fa3,76(s0) - aca: 6564 flw fs1,76(a0) - acc: 2e66 fld ft8,88(sp) - ace: 0068 addi a0,sp,12 - ad0: 0002 c.slli64 zero - ad2: 5f00 lw s0,56(a4) - ad4: 7974 flw fa3,116(a0) - ad6: 6570 flw fa2,76(a0) - ad8: 00682e73 csrrs t3,0x6,a6 - adc: 72000003 lb zero,1824(zero) # 720 <_start-0x7ffff8e0> - ae0: 6565 lui a0,0x19 - ae2: 746e flw fs0,248(sp) + 9da: 656e flw fa0,216(sp) + 9dc: 72642f77 0x72642f77 + 9e0: 2f73706f j 384d6 <_start-0x7ffc7b2a> + 9e4: 6972 flw fs2,28(sp) + 9e6: 33766373 csrrsi t1,mhpmevent23,12 + 9ea: 2d32 fld fs10,264(sp) + 9ec: 6e75 lui t3,0x1d + 9ee: 776f6e6b 0x776f6e6b + 9f2: 2d6e fld fs10,216(sp) + 9f4: 6c65 lui s8,0x19 + 9f6: 2f66 fld ft10,88(sp) + 9f8: 6e69 lui t3,0x1a + 9fa: 64756c63 bltu a0,t2,1052 <_start-0x7fffefae> + 9fe: 0065 c.nop 25 + a00: 2e2e fld ft8,200(sp) + a02: 2f2e2e2f 0x2f2e2e2f + a06: 2e2e fld ft8,200(sp) + a08: 2f2e2e2f 0x2f2e2e2f + a0c: 6972 flw fs2,28(sp) + a0e: 2d766373 csrrsi t1,0x2d7,12 + a12: 2f636367 0x2f636367 + a16: 696c flw fa1,84(a0) + a18: 6762 flw fa4,24(sp) + a1a: 2e2f6363 bltu t5,sp,d00 <_start-0x7ffff300> + a1e: 2f2e fld ft10,200(sp) + a20: 6e69 lui t3,0x1a + a22: 64756c63 bltu a0,t2,107a <_start-0x7fffef86> + a26: 0065 c.nop 25 + a28: 2e2e fld ft8,200(sp) + a2a: 2f2e2e2f 0x2f2e2e2f + a2e: 2e2e fld ft8,200(sp) + a30: 2f2e2e2f 0x2f2e2e2f + a34: 6972 flw fs2,28(sp) + a36: 2d766373 csrrsi t1,0x2d7,12 + a3a: 2f636367 0x2f636367 + a3e: 696c flw fa1,84(a0) + a40: 6762 flw fa4,24(sp) + a42: 2e2f6363 bltu t5,sp,d28 <_start-0x7ffff2d8> + a46: 2f2e fld ft10,200(sp) + a48: 2f636367 0x2f636367 + a4c: 666e6f63 bltu t3,t1,10ca <_start-0x7fffef36> + a50: 6769 lui a4,0x1a + a52: 7369722f 0x7369722f + a56: 2e007663 bgeu zero,zero,d42 <_start-0x7ffff2be> + a5a: 2f2e fld ft10,200(sp) + a5c: 2e2e fld ft8,200(sp) + a5e: 672f2e2f amoand.w.aqrl t3,s2,(t5) + a62: 00006363 bltu zero,zero,a68 <_start-0x7ffff598> + a66: 696c flw fa1,84(a0) + a68: 6762 flw fa4,24(sp) + a6a: 2e326363 bltu tp,gp,d50 <_start-0x7ffff2b0> + a6e: 00010063 beqz sp,a6e <_start-0x7ffff592> + a72: 7300 flw fs0,32(a4) + a74: 6474 flw fa3,76(s0) + a76: 6564 flw fs1,76(a0) + a78: 2e66 fld ft8,88(sp) + a7a: 0068 addi a0,sp,12 + a7c: 0002 c.slli64 zero + a7e: 5f00 lw s0,56(a4) + a80: 7974 flw fa3,116(a0) + a82: 6570 flw fa2,76(a0) + a84: 00682e73 csrrs t3,0x6,a6 + a88: 72000003 lb zero,1824(zero) # 720 <_start-0x7ffff8e0> + a8c: 6565 lui a0,0x19 + a8e: 746e flw fs0,248(sp) + a90: 682e flw fa6,200(sp) + a92: 0300 addi s0,sp,384 + a94: 0000 unimp + a96: 6f6c flw fa1,92(a4) + a98: 682e6b63 bltu t3,sp,112e <_start-0x7fffeed2> + a9c: 0300 addi s0,sp,384 + a9e: 0000 unimp + aa0: 7265 lui tp,0xffff9 + aa2: 6e72 flw ft8,28(sp) + aa4: 00682e6f jal t3,82aaa <_start-0x7ff7d556> + aa8: 73000003 lb zero,1840(zero) # 730 <_start-0x7ffff8d0> + aac: 6474 flw fa3,76(s0) + aae: 696c flw fa1,84(a0) + ab0: 2e62 fld ft8,24(sp) + ab2: 0068 addi a0,sp,12 + ab4: 0004 0x4 + ab6: 7500 flw fs0,40(a0) + ab8: 696e flw fs2,216(sp) + aba: 2e647473 csrrci s0,0x2e6,8 + abe: 0068 addi a0,sp,12 + ac0: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> + ac4: 6d69 lui s10,0x1a + ac6: 2e65 jal e7e <_start-0x7ffff182> + ac8: 0068 addi a0,sp,12 + aca: 0004 0x4 + acc: 6800 flw fs0,16(s0) + ace: 7361 lui t1,0xffff8 + ad0: 7468 flw fa0,108(s0) + ad2: 6261 lui tp,0x18 + ad4: 682e flw fa6,200(sp) + ad6: 0500 addi s0,sp,640 + ad8: 0000 unimp + ada: 6972 flw fs2,28(sp) + adc: 2d766373 csrrsi t1,0x2d7,12 + ae0: 7374706f j 48a16 <_start-0x7ffb75ea> ae4: 682e flw fa6,200(sp) - ae6: 0300 addi s0,sp,384 + ae6: 0600 addi s0,sp,768 ae8: 0000 unimp - aea: 6f6c flw fa1,92(a4) - aec: 682e6b63 bltu t3,sp,1182 <_start-0x7fffee7e> - af0: 0300 addi s0,sp,384 - af2: 0000 unimp - af4: 7265 lui tp,0xffff9 - af6: 6e72 flw ft8,28(sp) - af8: 00682e6f jal t3,82afe <_start-0x7ff7d502> - afc: 73000003 lb zero,1840(zero) # 730 <_start-0x7ffff8d0> - b00: 6474 flw fa3,76(s0) - b02: 696c flw fa1,84(a0) - b04: 2e62 fld ft8,24(sp) + aea: 6e69 lui t3,0x1a + aec: 632d6e73 csrrsi t3,0x632,26 + af0: 74736e6f jal t3,37a36 <_start-0x7ffc85ca> + af4: 6e61 lui t3,0x18 + af6: 7374 flw fa3,100(a4) + af8: 682e flw fa6,200(sp) + afa: 0700 addi s0,sp,896 + afc: 0000 unimp + afe: 696c flw fa1,84(a0) + b00: 6762 flw fa4,24(sp) + b02: 2e326363 bltu tp,gp,de8 <_start-0x7ffff218> b06: 0068 addi a0,sp,12 - b08: 0004 0x4 - b0a: 7500 flw fs0,40(a0) - b0c: 696e flw fs2,216(sp) - b0e: 2e647473 csrrci s0,0x2e6,8 - b12: 0068 addi a0,sp,12 - b14: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> - b18: 6d69 lui s10,0x1a - b1a: 2e65 jal ed2 <_start-0x7ffff12e> - b1c: 0068 addi a0,sp,12 - b1e: 0004 0x4 - b20: 6800 flw fs0,16(s0) - b22: 7361 lui t1,0xffff8 - b24: 7468 flw fa0,108(s0) - b26: 6261 lui tp,0x18 - b28: 682e flw fa6,200(sp) - b2a: 0500 addi s0,sp,640 - b2c: 0000 unimp - b2e: 6972 flw fs2,28(sp) - b30: 2d766373 csrrsi t1,0x2d7,12 - b34: 7374706f j 48a6a <_start-0x7ffb7596> - b38: 682e flw fa6,200(sp) - b3a: 0600 addi s0,sp,768 - b3c: 0000 unimp - b3e: 6e69 lui t3,0x1a - b40: 632d6e73 csrrsi t3,0x632,26 - b44: 74736e6f jal t3,37a8a <_start-0x7ffc8576> - b48: 6e61 lui t3,0x18 - b4a: 7374 flw fa3,100(a4) - b4c: 682e flw fa6,200(sp) - b4e: 0700 addi s0,sp,896 - b50: 0000 unimp - b52: 696c flw fa1,84(a0) - b54: 6762 flw fa4,24(sp) - b56: 2e326363 bltu tp,gp,e3c <_start-0x7ffff1c4> - b5a: 0068 addi a0,sp,12 - b5c: 0001 nop - b5e: 0000 unimp - b60: 0105 addi sp,sp,1 - b62: 0500 addi s0,sp,640 - b64: 3402 fld fs0,32(sp) - b66: 0108 addi a0,sp,128 - b68: 0380 addi s0,sp,448 - b6a: 0a9a slli s5,s5,0x6 + b08: 0001 nop + b0a: 0000 unimp + b0c: 0105 addi sp,sp,1 + b0e: 0500 addi s0,sp,640 + b10: f802 fsw ft0,48(sp) + b12: 0108 addi a0,sp,128 + b14: 0380 addi s0,sp,448 + b16: 0a9a slli s5,s5,0x6 + b18: 0501 addi a0,a0,0 + b1a: 09010303 lb t1,144(sp) # b0b1b72 <_start-0x74f4e48e> + b1e: 0000 unimp + b20: 0301 addi t1,t1,0 + b22: 0902 c.slli64 s2 + b24: 0000 unimp + b26: 0301 addi t1,t1,0 + b28: 00097ddb 0x97ddb + b2c: 0100 addi s0,sp,128 + b2e: 00090103 lb sp,0(s2) # 18000 <_start-0x7ffe8000> + b32: 0100 addi s0,sp,128 + b34: 00090103 lb sp,0(s2) + b38: 0100 addi s0,sp,128 + b3a: 00090103 lb sp,0(s2) + b3e: 0100 addi s0,sp,128 + b40: 00090103 lb sp,0(s2) + b44: 0100 addi s0,sp,128 + b46: 00090103 lb sp,0(s2) + b4a: 0100 addi s0,sp,128 + b4c: 00090203 lb tp,0(s2) + b50: 0100 addi s0,sp,128 + b52: 0605 addi a2,a2,1 + b54: 0306 slli t1,t1,0x1 + b56: 0900 addi s0,sp,144 + b58: 0000 unimp + b5a: 0501 addi a0,a0,0 + b5c: 01030603 lb a2,16(t1) # ffff8010 <__BSS_END__+0x7ffe13d4> + b60: 0409 addi s0,s0,2 + b62: 0100 addi s0,sp,128 + b64: 0605 addi a2,a2,1 + b66: 0306 slli t1,t1,0x1 + b68: 0900 addi s0,sp,144 + b6a: 0000 unimp b6c: 0501 addi a0,a0,0 - b6e: 09010303 lb t1,144(sp) # b0b1b72 <_start-0x74f4e48e> - b72: 0000 unimp - b74: 0301 addi t1,t1,0 - b76: 0902 c.slli64 s2 - b78: 0000 unimp - b7a: 0301 addi t1,t1,0 - b7c: 00097ddb 0x97ddb - b80: 0100 addi s0,sp,128 - b82: 00090103 lb sp,0(s2) # 18000 <_start-0x7ffe8000> + b6e: 01030603 lb a2,16(t1) + b72: 0409 addi s0,s0,2 + b74: 0100 addi s0,sp,128 + b76: 0605 addi a2,a2,1 + b78: 0306 slli t1,t1,0x1 + b7a: 0900 addi s0,sp,144 + b7c: 0000 unimp + b7e: 0501 addi a0,a0,0 + b80: 01030603 lb a2,16(t1) + b84: 0409 addi s0,s0,2 b86: 0100 addi s0,sp,128 - b88: 00090103 lb sp,0(s2) - b8c: 0100 addi s0,sp,128 - b8e: 00090103 lb sp,0(s2) - b92: 0100 addi s0,sp,128 - b94: 00090103 lb sp,0(s2) + b88: 0605 addi a2,a2,1 + b8a: 0306 slli t1,t1,0x1 + b8c: 0900 addi s0,sp,144 + b8e: 0000 unimp + b90: 0501 addi a0,a0,0 + b92: 25030603 lb a2,592(t1) + b96: 0409 addi s0,s0,2 b98: 0100 addi s0,sp,128 - b9a: 00090103 lb sp,0(s2) - b9e: 0100 addi s0,sp,128 - ba0: 00090203 lb tp,0(s2) - ba4: 0100 addi s0,sp,128 - ba6: 0605 addi a2,a2,1 - ba8: 0306 slli t1,t1,0x1 - baa: 0900 addi s0,sp,144 - bac: 0000 unimp - bae: 0501 addi a0,a0,0 - bb0: 01030603 lb a2,16(t1) # ffff8010 <__BSS_END__+0x7ffe13e0> - bb4: 0409 addi s0,s0,2 - bb6: 0100 addi s0,sp,128 - bb8: 0605 addi a2,a2,1 - bba: 0306 slli t1,t1,0x1 - bbc: 0900 addi s0,sp,144 - bbe: 0000 unimp - bc0: 0501 addi a0,a0,0 - bc2: 01030603 lb a2,16(t1) - bc6: 0409 addi s0,s0,2 + b9a: 0605 addi a2,a2,1 + b9c: 0306 slli t1,t1,0x1 + b9e: 0900 addi s0,sp,144 + ba0: 0000 unimp + ba2: 0501 addi a0,a0,0 + ba4: 02030607 0x2030607 + ba8: 0409 addi s0,s0,2 + baa: 0100 addi s0,sp,128 + bac: 0a05 addi s4,s4,1 + bae: 0306 slli t1,t1,0x1 + bb0: 0900 addi s0,sp,144 + bb2: 0008 0x8 + bb4: 0501 addi a0,a0,0 + bb6: 0604 addi s1,sp,768 + bb8: 04090403 lb s0,64(s2) + bbc: 0100 addi s0,sp,128 + bbe: 00090003 lb zero,0(s2) + bc2: 0100 addi s0,sp,128 + bc4: 00090003 lb zero,0(s2) bc8: 0100 addi s0,sp,128 - bca: 0605 addi a2,a2,1 - bcc: 0306 slli t1,t1,0x1 - bce: 0900 addi s0,sp,144 - bd0: 0000 unimp - bd2: 0501 addi a0,a0,0 - bd4: 01030603 lb a2,16(t1) - bd8: 0409 addi s0,s0,2 + bca: 00090003 lb zero,0(s2) + bce: 0100 addi s0,sp,128 + bd0: 00090003 lb zero,0(s2) + bd4: 0100 addi s0,sp,128 + bd6: 14090003 lb zero,320(s2) bda: 0100 addi s0,sp,128 - bdc: 0605 addi a2,a2,1 - bde: 0306 slli t1,t1,0x1 - be0: 0900 addi s0,sp,144 - be2: 0000 unimp - be4: 0501 addi a0,a0,0 - be6: 25030603 lb a2,592(t1) - bea: 0409 addi s0,s0,2 - bec: 0100 addi s0,sp,128 - bee: 0605 addi a2,a2,1 - bf0: 0306 slli t1,t1,0x1 - bf2: 0900 addi s0,sp,144 - bf4: 0000 unimp - bf6: 0501 addi a0,a0,0 - bf8: 02030607 0x2030607 - bfc: 0409 addi s0,s0,2 - bfe: 0100 addi s0,sp,128 - c00: 0a05 addi s4,s4,1 - c02: 0306 slli t1,t1,0x1 - c04: 0900 addi s0,sp,144 - c06: 0008 0x8 - c08: 0501 addi a0,a0,0 - c0a: 0604 addi s1,sp,768 - c0c: 04090403 lb s0,64(s2) - c10: 0100 addi s0,sp,128 - c12: 00090003 lb zero,0(s2) - c16: 0100 addi s0,sp,128 - c18: 00090003 lb zero,0(s2) - c1c: 0100 addi s0,sp,128 - c1e: 00090003 lb zero,0(s2) - c22: 0100 addi s0,sp,128 - c24: 00090003 lb zero,0(s2) - c28: 0100 addi s0,sp,128 - c2a: 14090003 lb zero,320(s2) - c2e: 0100 addi s0,sp,128 - c30: 18090003 lb zero,384(s2) - c34: 0100 addi s0,sp,128 - c36: 00090203 lb tp,0(s2) - c3a: 0100 addi s0,sp,128 - c3c: 0705 addi a4,a4,1 - c3e: 0306 slli t1,t1,0x1 - c40: 0900 addi s0,sp,144 - c42: 0000 unimp - c44: 0501 addi a0,a0,0 - c46: 0608 addi a0,sp,768 - c48: 04090503 lb a0,64(s2) - c4c: 0100 addi s0,sp,128 - c4e: 1105 addi sp,sp,-31 - c50: 0306 slli t1,t1,0x1 - c52: 0901 addi s2,s2,0 - c54: 0000 unimp - c56: 0501 addi a0,a0,0 - c58: 031e slli t1,t1,0x7 - c5a: 0900 addi s0,sp,144 - c5c: 0004 0x4 - c5e: 0501 addi a0,a0,0 - c60: 097f030b 0x97f030b - c64: 0004 0x4 - c66: 0501 addi a0,a0,0 - c68: 0608 addi a0,sp,768 - c6a: 04090103 lb sp,64(s2) + bdc: 18090003 lb zero,384(s2) + be0: 0100 addi s0,sp,128 + be2: 00090203 lb tp,0(s2) + be6: 0100 addi s0,sp,128 + be8: 0705 addi a4,a4,1 + bea: 0306 slli t1,t1,0x1 + bec: 0900 addi s0,sp,144 + bee: 0000 unimp + bf0: 0501 addi a0,a0,0 + bf2: 0608 addi a0,sp,768 + bf4: 04090503 lb a0,64(s2) + bf8: 0100 addi s0,sp,128 + bfa: 1105 addi sp,sp,-31 + bfc: 0306 slli t1,t1,0x1 + bfe: 0901 addi s2,s2,0 + c00: 0000 unimp + c02: 0501 addi a0,a0,0 + c04: 031e slli t1,t1,0x7 + c06: 0900 addi s0,sp,144 + c08: 0004 0x4 + c0a: 0501 addi a0,a0,0 + c0c: 097f030b 0x97f030b + c10: 0004 0x4 + c12: 0501 addi a0,a0,0 + c14: 0608 addi a0,sp,768 + c16: 04090103 lb sp,64(s2) + c1a: 0100 addi s0,sp,128 + c1c: 0b05 addi s6,s6,1 + c1e: 0306 slli t1,t1,0x1 + c20: 0900 addi s0,sp,144 + c22: 0000 unimp + c24: 0501 addi a0,a0,0 + c26: 0608 addi a0,sp,768 + c28: 04090103 lb sp,64(s2) + c2c: 0100 addi s0,sp,128 + c2e: 0b05 addi s6,s6,1 + c30: 0306 slli t1,t1,0x1 + c32: 0900 addi s0,sp,144 + c34: 0000 unimp + c36: 0501 addi a0,a0,0 + c38: 0604 addi s1,sp,768 + c3a: 04090303 lb t1,64(s2) + c3e: 0100 addi s0,sp,128 + c40: 00090003 lb zero,0(s2) + c44: 0100 addi s0,sp,128 + c46: 00090003 lb zero,0(s2) + c4a: 0100 addi s0,sp,128 + c4c: 00090003 lb zero,0(s2) + c50: 0100 addi s0,sp,128 + c52: 04090003 lb zero,64(s2) + c56: 0100 addi s0,sp,128 + c58: 0c090003 lb zero,192(s2) + c5c: 0100 addi s0,sp,128 + c5e: 00090003 lb zero,0(s2) + c62: 0100 addi s0,sp,128 + c64: 08090003 lb zero,128(s2) + c68: 0100 addi s0,sp,128 + c6a: 0c090003 lb zero,192(s2) c6e: 0100 addi s0,sp,128 - c70: 0b05 addi s6,s6,1 - c72: 0306 slli t1,t1,0x1 - c74: 0900 addi s0,sp,144 - c76: 0000 unimp - c78: 0501 addi a0,a0,0 - c7a: 0608 addi a0,sp,768 - c7c: 04090103 lb sp,64(s2) + c70: 00090003 lb zero,0(s2) + c74: 0100 addi s0,sp,128 + c76: 04090003 lb zero,64(s2) + c7a: 0100 addi s0,sp,128 + c7c: 04090003 lb zero,64(s2) c80: 0100 addi s0,sp,128 - c82: 0b05 addi s6,s6,1 - c84: 0306 slli t1,t1,0x1 - c86: 0900 addi s0,sp,144 - c88: 0000 unimp - c8a: 0501 addi a0,a0,0 - c8c: 0604 addi s1,sp,768 - c8e: 04090303 lb t1,64(s2) + c82: 04090003 lb zero,64(s2) + c86: 0100 addi s0,sp,128 + c88: 04090003 lb zero,64(s2) + c8c: 0100 addi s0,sp,128 + c8e: 04090003 lb zero,64(s2) c92: 0100 addi s0,sp,128 - c94: 00090003 lb zero,0(s2) + c94: 04090003 lb zero,64(s2) c98: 0100 addi s0,sp,128 - c9a: 00090003 lb zero,0(s2) + c9a: 04090003 lb zero,64(s2) c9e: 0100 addi s0,sp,128 - ca0: 00090003 lb zero,0(s2) + ca0: 0c090003 lb zero,192(s2) ca4: 0100 addi s0,sp,128 ca6: 04090003 lb zero,64(s2) caa: 0100 addi s0,sp,128 - cac: 0c090003 lb zero,192(s2) + cac: 08090003 lb zero,128(s2) cb0: 0100 addi s0,sp,128 - cb2: 00090003 lb zero,0(s2) + cb2: 04090003 lb zero,64(s2) cb6: 0100 addi s0,sp,128 - cb8: 08090003 lb zero,128(s2) + cb8: 04090003 lb zero,64(s2) cbc: 0100 addi s0,sp,128 - cbe: 0c090003 lb zero,192(s2) + cbe: 04090003 lb zero,64(s2) cc2: 0100 addi s0,sp,128 - cc4: 00090003 lb zero,0(s2) + cc4: 04090003 lb zero,64(s2) cc8: 0100 addi s0,sp,128 cca: 04090003 lb zero,64(s2) cce: 0100 addi s0,sp,128 cd0: 04090003 lb zero,64(s2) cd4: 0100 addi s0,sp,128 - cd6: 04090003 lb zero,64(s2) + cd6: 00090003 lb zero,0(s2) cda: 0100 addi s0,sp,128 - cdc: 04090003 lb zero,64(s2) + cdc: 00090003 lb zero,0(s2) ce0: 0100 addi s0,sp,128 - ce2: 04090003 lb zero,64(s2) + ce2: 00090103 lb sp,0(s2) ce6: 0100 addi s0,sp,128 - ce8: 04090003 lb zero,64(s2) + ce8: 00092903 lw s2,0(s2) cec: 0100 addi s0,sp,128 - cee: 04090003 lb zero,64(s2) - cf2: 0100 addi s0,sp,128 - cf4: 0c090003 lb zero,192(s2) - cf8: 0100 addi s0,sp,128 - cfa: 04090003 lb zero,64(s2) - cfe: 0100 addi s0,sp,128 - d00: 08090003 lb zero,128(s2) - d04: 0100 addi s0,sp,128 - d06: 04090003 lb zero,64(s2) - d0a: 0100 addi s0,sp,128 - d0c: 04090003 lb zero,64(s2) - d10: 0100 addi s0,sp,128 - d12: 04090003 lb zero,64(s2) - d16: 0100 addi s0,sp,128 - d18: 04090003 lb zero,64(s2) - d1c: 0100 addi s0,sp,128 - d1e: 04090003 lb zero,64(s2) - d22: 0100 addi s0,sp,128 - d24: 04090003 lb zero,64(s2) - d28: 0100 addi s0,sp,128 - d2a: 00090003 lb zero,0(s2) - d2e: 0100 addi s0,sp,128 - d30: 00090003 lb zero,0(s2) + cee: 0705 addi a4,a4,1 + cf0: 00090503 lb a0,0(s2) + cf4: 0100 addi s0,sp,128 + cf6: 0405 addi s0,s0,1 + cf8: 00090203 lb tp,0(s2) + cfc: 0100 addi s0,sp,128 + cfe: 1205 addi tp,tp,-31 + d00: 0306 slli t1,t1,0x1 + d02: 0900 addi s0,sp,144 + d04: 0000 unimp + d06: 0501 addi a0,a0,0 + d08: 0604 addi s1,sp,768 + d0a: 04090103 lb sp,64(s2) + d0e: 0100 addi s0,sp,128 + d10: 00090103 lb sp,0(s2) + d14: 0100 addi s0,sp,128 + d16: 0c05 addi s8,s8,1 + d18: 0306 slli t1,t1,0x1 + d1a: 0900 addi s0,sp,144 + d1c: 0000 unimp + d1e: 0501 addi a0,a0,0 + d20: da030603 lb a2,-608(t1) + d24: 0900 addi s0,sp,144 + d26: 0004 0x4 + d28: 0301 addi t1,t1,0 + d2a: 0901 addi s2,s2,0 + d2c: 0000 unimp + d2e: 0301 addi t1,t1,0 + d30: 00d8 addi a4,sp,68 + d32: 0009 c.nop 2 d34: 0100 addi s0,sp,128 - d36: 00090103 lb sp,0(s2) - d3a: 0100 addi s0,sp,128 - d3c: 00092903 lw s2,0(s2) - d40: 0100 addi s0,sp,128 - d42: 0705 addi a4,a4,1 - d44: 00090503 lb a0,0(s2) - d48: 0100 addi s0,sp,128 - d4a: 0405 addi s0,s0,1 - d4c: 00090203 lb tp,0(s2) - d50: 0100 addi s0,sp,128 - d52: 1205 addi tp,tp,-31 - d54: 0306 slli t1,t1,0x1 - d56: 0900 addi s0,sp,144 - d58: 0000 unimp - d5a: 0501 addi a0,a0,0 - d5c: 0604 addi s1,sp,768 - d5e: 04090103 lb sp,64(s2) - d62: 0100 addi s0,sp,128 - d64: 00090103 lb sp,0(s2) + d36: 0105 addi sp,sp,1 + d38: 0306 slli t1,t1,0x1 + d3a: 0901 addi s2,s2,0 + d3c: 0000 unimp + d3e: 0501 addi a0,a0,0 + d40: 0304 addi s1,sp,384 + d42: 7e8d lui t4,0xfffe3 + d44: 0409 addi s0,s0,2 + d46: 0100 addi s0,sp,128 + d48: 0306 slli t1,t1,0x1 + d4a: 0915 addi s2,s2,5 + d4c: 0014 0x14 + d4e: 0501 addi a0,a0,0 + d50: 00030607 0x30607 + d54: 0009 c.nop 2 + d56: 0100 addi s0,sp,128 + d58: 0605 addi a2,a2,1 + d5a: 0306 slli t1,t1,0x1 + d5c: 0901 addi s2,s2,0 + d5e: 0004 0x4 + d60: 0501 addi a0,a0,0 + d62: 0609 addi a2,a2,2 + d64: 00090003 lb zero,0(s2) d68: 0100 addi s0,sp,128 - d6a: 0c05 addi s8,s8,1 + d6a: 0405 addi s0,s0,1 d6c: 0306 slli t1,t1,0x1 - d6e: 0900 addi s0,sp,144 - d70: 0000 unimp - d72: 0501 addi a0,a0,0 - d74: da030603 lb a2,-608(t1) - d78: 0900 addi s0,sp,144 - d7a: 0004 0x4 - d7c: 0301 addi t1,t1,0 - d7e: 0901 addi s2,s2,0 - d80: 0000 unimp - d82: 0301 addi t1,t1,0 - d84: 00d8 addi a4,sp,68 - d86: 0009 c.nop 2 - d88: 0100 addi s0,sp,128 - d8a: 0105 addi sp,sp,1 - d8c: 0306 slli t1,t1,0x1 - d8e: 0901 addi s2,s2,0 - d90: 0000 unimp - d92: 0501 addi a0,a0,0 - d94: 0304 addi s1,sp,384 - d96: 7e8d lui t4,0xfffe3 - d98: 0409 addi s0,s0,2 - d9a: 0100 addi s0,sp,128 - d9c: 0306 slli t1,t1,0x1 - d9e: 0915 addi s2,s2,5 - da0: 0014 0x14 - da2: 0501 addi a0,a0,0 - da4: 00030607 0x30607 - da8: 0009 c.nop 2 - daa: 0100 addi s0,sp,128 - dac: 0605 addi a2,a2,1 - dae: 0306 slli t1,t1,0x1 - db0: 0901 addi s2,s2,0 - db2: 0004 0x4 - db4: 0501 addi a0,a0,0 - db6: 0609 addi a2,a2,2 - db8: 00090003 lb zero,0(s2) - dbc: 0100 addi s0,sp,128 - dbe: 0405 addi s0,s0,1 - dc0: 0306 slli t1,t1,0x1 - dc2: 0902 c.slli64 s2 - dc4: 0008 0x8 - dc6: 0301 addi t1,t1,0 - dc8: 0900 addi s0,sp,144 - dca: 0000 unimp - dcc: 0301 addi t1,t1,0 - dce: 0900 addi s0,sp,144 - dd0: 0000 unimp - dd2: 0301 addi t1,t1,0 - dd4: 0900 addi s0,sp,144 - dd6: 0000 unimp - dd8: 0301 addi t1,t1,0 - dda: 0900 addi s0,sp,144 - ddc: 0000 unimp - dde: 0301 addi t1,t1,0 - de0: 0900 addi s0,sp,144 - de2: 0014 0x14 - de4: 0301 addi t1,t1,0 - de6: 0900 addi s0,sp,144 - de8: 0018 0x18 - dea: 0301 addi t1,t1,0 - dec: 0902 c.slli64 s2 - dee: 0000 unimp - df0: 0501 addi a0,a0,0 - df2: 00030607 0x30607 - df6: 0009 c.nop 2 - df8: 0100 addi s0,sp,128 - dfa: 0805 addi a6,a6,1 - dfc: 0306 slli t1,t1,0x1 - dfe: 0909 addi s2,s2,2 - e00: 0004 0x4 - e02: 0501 addi a0,a0,0 - e04: 0003060b 0x3060b - e08: 0009 c.nop 2 - e0a: 0100 addi s0,sp,128 - e0c: 0805 addi a6,a6,1 - e0e: 0306 slli t1,t1,0x1 - e10: 0901 addi s2,s2,0 - e12: 0004 0x4 - e14: 0301 addi t1,t1,0 - e16: 090d addi s2,s2,3 - e18: 0000 unimp - e1a: 0501 addi a0,a0,0 - e1c: 0304 addi s1,sp,384 - e1e: 0905 addi s2,s2,1 - e20: 0000 unimp + d6e: 0902 c.slli64 s2 + d70: 0008 0x8 + d72: 0301 addi t1,t1,0 + d74: 0900 addi s0,sp,144 + d76: 0000 unimp + d78: 0301 addi t1,t1,0 + d7a: 0900 addi s0,sp,144 + d7c: 0000 unimp + d7e: 0301 addi t1,t1,0 + d80: 0900 addi s0,sp,144 + d82: 0000 unimp + d84: 0301 addi t1,t1,0 + d86: 0900 addi s0,sp,144 + d88: 0000 unimp + d8a: 0301 addi t1,t1,0 + d8c: 0900 addi s0,sp,144 + d8e: 0014 0x14 + d90: 0301 addi t1,t1,0 + d92: 0900 addi s0,sp,144 + d94: 0018 0x18 + d96: 0301 addi t1,t1,0 + d98: 0902 c.slli64 s2 + d9a: 0000 unimp + d9c: 0501 addi a0,a0,0 + d9e: 00030607 0x30607 + da2: 0009 c.nop 2 + da4: 0100 addi s0,sp,128 + da6: 0805 addi a6,a6,1 + da8: 0306 slli t1,t1,0x1 + daa: 0909 addi s2,s2,2 + dac: 0004 0x4 + dae: 0501 addi a0,a0,0 + db0: 0003060b 0x3060b + db4: 0009 c.nop 2 + db6: 0100 addi s0,sp,128 + db8: 0805 addi a6,a6,1 + dba: 0306 slli t1,t1,0x1 + dbc: 0901 addi s2,s2,0 + dbe: 0004 0x4 + dc0: 0301 addi t1,t1,0 + dc2: 090d addi s2,s2,3 + dc4: 0000 unimp + dc6: 0501 addi a0,a0,0 + dc8: 0304 addi s1,sp,384 + dca: 0905 addi s2,s2,1 + dcc: 0000 unimp + dce: 0301 addi t1,t1,0 + dd0: 0900 addi s0,sp,144 + dd2: 0000 unimp + dd4: 0301 addi t1,t1,0 + dd6: 0900 addi s0,sp,144 + dd8: 0000 unimp + dda: 0301 addi t1,t1,0 + ddc: 0900 addi s0,sp,144 + dde: 0000 unimp + de0: 0301 addi t1,t1,0 + de2: 0900 addi s0,sp,144 + de4: 0004 0x4 + de6: 0301 addi t1,t1,0 + de8: 0900 addi s0,sp,144 + dea: 0008 0x8 + dec: 0301 addi t1,t1,0 + dee: 0900 addi s0,sp,144 + df0: 0008 0x8 + df2: 0301 addi t1,t1,0 + df4: 0900 addi s0,sp,144 + df6: 0004 0x4 + df8: 0301 addi t1,t1,0 + dfa: 0900 addi s0,sp,144 + dfc: 000c 0xc + dfe: 0301 addi t1,t1,0 + e00: 0900 addi s0,sp,144 + e02: 0000 unimp + e04: 0301 addi t1,t1,0 + e06: 0900 addi s0,sp,144 + e08: 0004 0x4 + e0a: 0301 addi t1,t1,0 + e0c: 0900 addi s0,sp,144 + e0e: 0004 0x4 + e10: 0301 addi t1,t1,0 + e12: 0900 addi s0,sp,144 + e14: 0004 0x4 + e16: 0301 addi t1,t1,0 + e18: 0900 addi s0,sp,144 + e1a: 0004 0x4 + e1c: 0301 addi t1,t1,0 + e1e: 0900 addi s0,sp,144 + e20: 0004 0x4 e22: 0301 addi t1,t1,0 e24: 0900 addi s0,sp,144 - e26: 0000 unimp + e26: 0004 0x4 e28: 0301 addi t1,t1,0 e2a: 0900 addi s0,sp,144 - e2c: 0000 unimp + e2c: 0004 0x4 e2e: 0301 addi t1,t1,0 e30: 0900 addi s0,sp,144 - e32: 0000 unimp + e32: 000c 0xc e34: 0301 addi t1,t1,0 e36: 0900 addi s0,sp,144 e38: 0004 0x4 @@ -42657,16 +42707,16 @@ Disassembly of section .debug_line: e3e: 0008 0x8 e40: 0301 addi t1,t1,0 e42: 0900 addi s0,sp,144 - e44: 0008 0x8 + e44: 0004 0x4 e46: 0301 addi t1,t1,0 e48: 0900 addi s0,sp,144 e4a: 0004 0x4 e4c: 0301 addi t1,t1,0 e4e: 0900 addi s0,sp,144 - e50: 000c 0xc + e50: 0004 0x4 e52: 0301 addi t1,t1,0 e54: 0900 addi s0,sp,144 - e56: 0000 unimp + e56: 0004 0x4 e58: 0301 addi t1,t1,0 e5a: 0900 addi s0,sp,144 e5c: 0004 0x4 @@ -42675,125 +42725,125 @@ Disassembly of section .debug_line: e62: 0004 0x4 e64: 0301 addi t1,t1,0 e66: 0900 addi s0,sp,144 - e68: 0004 0x4 - e6a: 0301 addi t1,t1,0 - e6c: 0900 addi s0,sp,144 - e6e: 0004 0x4 - e70: 0301 addi t1,t1,0 - e72: 0900 addi s0,sp,144 - e74: 0004 0x4 - e76: 0301 addi t1,t1,0 - e78: 0900 addi s0,sp,144 - e7a: 0004 0x4 - e7c: 0301 addi t1,t1,0 - e7e: 0900 addi s0,sp,144 - e80: 0004 0x4 - e82: 0301 addi t1,t1,0 - e84: 0900 addi s0,sp,144 - e86: 000c 0xc - e88: 0301 addi t1,t1,0 - e8a: 0900 addi s0,sp,144 - e8c: 0004 0x4 - e8e: 0301 addi t1,t1,0 - e90: 0900 addi s0,sp,144 - e92: 0008 0x8 - e94: 0301 addi t1,t1,0 - e96: 0900 addi s0,sp,144 - e98: 0004 0x4 - e9a: 0301 addi t1,t1,0 - e9c: 0900 addi s0,sp,144 - e9e: 0004 0x4 - ea0: 0301 addi t1,t1,0 - ea2: 0900 addi s0,sp,144 - ea4: 0004 0x4 - ea6: 0301 addi t1,t1,0 - ea8: 0900 addi s0,sp,144 - eaa: 0004 0x4 - eac: 0301 addi t1,t1,0 - eae: 0900 addi s0,sp,144 - eb0: 0004 0x4 - eb2: 0301 addi t1,t1,0 - eb4: 0900 addi s0,sp,144 - eb6: 0004 0x4 - eb8: 0301 addi t1,t1,0 - eba: 0900 addi s0,sp,144 - ebc: 0000 unimp - ebe: 0601 addi a2,a2,0 - ec0: 04096203 0x4096203 + e68: 0000 unimp + e6a: 0601 addi a2,a2,0 + e6c: 04096203 0x4096203 + e70: 0100 addi s0,sp,128 + e72: 0805 addi a6,a6,1 + e74: 0306 slli t1,t1,0x1 + e76: 0912 slli s2,s2,0x4 + e78: 0014 0x14 + e7a: 0301 addi t1,t1,0 + e7c: 0902 c.slli64 s2 + e7e: 0000 unimp + e80: 0501 addi a0,a0,0 + e82: 0003060b 0x3060b + e86: 0009 c.nop 2 + e88: 0100 addi s0,sp,128 + e8a: 0805 addi a6,a6,1 + e8c: 0306 slli t1,t1,0x1 + e8e: 0901 addi s2,s2,0 + e90: 0004 0x4 + e92: 0501 addi a0,a0,0 + e94: 0003060b 0x3060b + e98: 0009 c.nop 2 + e9a: 0100 addi s0,sp,128 + e9c: 0805 addi a6,a6,1 + e9e: 0306 slli t1,t1,0x1 + ea0: 0901 addi s2,s2,0 + ea2: 0004 0x4 + ea4: 0501 addi a0,a0,0 + ea6: 0103060b 0x103060b + eaa: 0009 c.nop 2 + eac: 0100 addi s0,sp,128 + eae: 1e05 addi t3,t3,-31 + eb0: 04097f03 0x4097f03 + eb4: 0100 addi s0,sp,128 + eb6: 0805 addi a6,a6,1 + eb8: 04090303 lb t1,64(s2) + ebc: 0100 addi s0,sp,128 + ebe: 1105 addi sp,sp,-31 + ec0: 08097d03 0x8097d03 ec4: 0100 addi s0,sp,128 - ec6: 0805 addi a6,a6,1 - ec8: 0306 slli t1,t1,0x1 - eca: 0912 slli s2,s2,0x4 - ecc: 0014 0x14 - ece: 0301 addi t1,t1,0 - ed0: 0902 c.slli64 s2 - ed2: 0000 unimp - ed4: 0501 addi a0,a0,0 - ed6: 0003060b 0x3060b - eda: 0009 c.nop 2 - edc: 0100 addi s0,sp,128 - ede: 0805 addi a6,a6,1 - ee0: 0306 slli t1,t1,0x1 - ee2: 0901 addi s2,s2,0 - ee4: 0004 0x4 - ee6: 0501 addi a0,a0,0 - ee8: 0003060b 0x3060b - eec: 0009 c.nop 2 - eee: 0100 addi s0,sp,128 - ef0: 0805 addi a6,a6,1 - ef2: 0306 slli t1,t1,0x1 - ef4: 0901 addi s2,s2,0 - ef6: 0004 0x4 - ef8: 0501 addi a0,a0,0 - efa: 0103060b 0x103060b - efe: 0009 c.nop 2 - f00: 0100 addi s0,sp,128 - f02: 1e05 addi t3,t3,-31 - f04: 04097f03 0x4097f03 - f08: 0100 addi s0,sp,128 - f0a: 0805 addi a6,a6,1 - f0c: 04090303 lb t1,64(s2) - f10: 0100 addi s0,sp,128 - f12: 1105 addi sp,sp,-31 - f14: 08097d03 0x8097d03 - f18: 0100 addi s0,sp,128 - f1a: 0b05 addi s6,s6,1 - f1c: 04090003 lb zero,64(s2) - f20: 0100 addi s0,sp,128 - f22: 0805 addi a6,a6,1 - f24: 0306 slli t1,t1,0x1 - f26: 0901 addi s2,s2,0 + ec6: 0b05 addi s6,s6,1 + ec8: 04090003 lb zero,64(s2) + ecc: 0100 addi s0,sp,128 + ece: 0805 addi a6,a6,1 + ed0: 0306 slli t1,t1,0x1 + ed2: 0901 addi s2,s2,0 + ed4: 0004 0x4 + ed6: 0301 addi t1,t1,0 + ed8: 0902 c.slli64 s2 + eda: 0000 unimp + edc: 0301 addi t1,t1,0 + ede: 0900 addi s0,sp,144 + ee0: 0000 unimp + ee2: 0301 addi t1,t1,0 + ee4: 0900 addi s0,sp,144 + ee6: 0000 unimp + ee8: 0301 addi t1,t1,0 + eea: 0900 addi s0,sp,144 + eec: 0000 unimp + eee: 0301 addi t1,t1,0 + ef0: 0900 addi s0,sp,144 + ef2: 0000 unimp + ef4: 0301 addi t1,t1,0 + ef6: 0900 addi s0,sp,144 + ef8: 0008 0x8 + efa: 0301 addi t1,t1,0 + efc: 0900 addi s0,sp,144 + efe: 0000 unimp + f00: 0301 addi t1,t1,0 + f02: 0900 addi s0,sp,144 + f04: 0008 0x8 + f06: 0301 addi t1,t1,0 + f08: 0900 addi s0,sp,144 + f0a: 000c 0xc + f0c: 0301 addi t1,t1,0 + f0e: 0900 addi s0,sp,144 + f10: 0000 unimp + f12: 0301 addi t1,t1,0 + f14: 0900 addi s0,sp,144 + f16: 0004 0x4 + f18: 0301 addi t1,t1,0 + f1a: 0900 addi s0,sp,144 + f1c: 0004 0x4 + f1e: 0301 addi t1,t1,0 + f20: 0900 addi s0,sp,144 + f22: 0004 0x4 + f24: 0301 addi t1,t1,0 + f26: 0900 addi s0,sp,144 f28: 0004 0x4 f2a: 0301 addi t1,t1,0 - f2c: 0902 c.slli64 s2 - f2e: 0000 unimp + f2c: 0900 addi s0,sp,144 + f2e: 0004 0x4 f30: 0301 addi t1,t1,0 f32: 0900 addi s0,sp,144 - f34: 0000 unimp + f34: 0004 0x4 f36: 0301 addi t1,t1,0 f38: 0900 addi s0,sp,144 - f3a: 0000 unimp + f3a: 0004 0x4 f3c: 0301 addi t1,t1,0 f3e: 0900 addi s0,sp,144 - f40: 0000 unimp + f40: 000c 0xc f42: 0301 addi t1,t1,0 f44: 0900 addi s0,sp,144 - f46: 0000 unimp + f46: 0008 0x8 f48: 0301 addi t1,t1,0 f4a: 0900 addi s0,sp,144 - f4c: 0008 0x8 + f4c: 0004 0x4 f4e: 0301 addi t1,t1,0 f50: 0900 addi s0,sp,144 - f52: 0000 unimp + f52: 0004 0x4 f54: 0301 addi t1,t1,0 f56: 0900 addi s0,sp,144 - f58: 0008 0x8 + f58: 0004 0x4 f5a: 0301 addi t1,t1,0 f5c: 0900 addi s0,sp,144 - f5e: 000c 0xc + f5e: 0004 0x4 f60: 0301 addi t1,t1,0 f62: 0900 addi s0,sp,144 - f64: 0000 unimp + f64: 0004 0x4 f66: 0301 addi t1,t1,0 f68: 0900 addi s0,sp,144 f6a: 0004 0x4 @@ -42802,505 +42852,505 @@ Disassembly of section .debug_line: f70: 0004 0x4 f72: 0301 addi t1,t1,0 f74: 0900 addi s0,sp,144 - f76: 0004 0x4 - f78: 0301 addi t1,t1,0 - f7a: 0900 addi s0,sp,144 - f7c: 0004 0x4 - f7e: 0301 addi t1,t1,0 - f80: 0900 addi s0,sp,144 - f82: 0004 0x4 - f84: 0301 addi t1,t1,0 - f86: 0900 addi s0,sp,144 - f88: 0004 0x4 - f8a: 0301 addi t1,t1,0 - f8c: 0900 addi s0,sp,144 - f8e: 0004 0x4 - f90: 0301 addi t1,t1,0 - f92: 0900 addi s0,sp,144 - f94: 000c 0xc - f96: 0301 addi t1,t1,0 - f98: 0900 addi s0,sp,144 - f9a: 0008 0x8 - f9c: 0301 addi t1,t1,0 - f9e: 0900 addi s0,sp,144 - fa0: 0004 0x4 - fa2: 0301 addi t1,t1,0 - fa4: 0900 addi s0,sp,144 - fa6: 0004 0x4 - fa8: 0301 addi t1,t1,0 - faa: 0900 addi s0,sp,144 - fac: 0004 0x4 - fae: 0301 addi t1,t1,0 - fb0: 0900 addi s0,sp,144 - fb2: 0004 0x4 - fb4: 0301 addi t1,t1,0 - fb6: 0900 addi s0,sp,144 - fb8: 0004 0x4 - fba: 0301 addi t1,t1,0 - fbc: 0900 addi s0,sp,144 - fbe: 0004 0x4 - fc0: 0301 addi t1,t1,0 - fc2: 0900 addi s0,sp,144 - fc4: 0004 0x4 - fc6: 0301 addi t1,t1,0 - fc8: 0900 addi s0,sp,144 - fca: 0000 unimp - fcc: 0501 addi a0,a0,0 - fce: 09150307 0x9150307 - fd2: 0004 0x4 - fd4: 0501 addi a0,a0,0 - fd6: 060a slli a2,a2,0x2 - fd8: 00090003 lb zero,0(s2) - fdc: 0100 addi s0,sp,128 - fde: 0405 addi s0,s0,1 - fe0: 0306 slli t1,t1,0x1 - fe2: 00040913 mv s2,s0 - fe6: 0301 addi t1,t1,0 - fe8: 0900 addi s0,sp,144 - fea: 0000 unimp - fec: 0301 addi t1,t1,0 - fee: 0900 addi s0,sp,144 - ff0: 0000 unimp - ff2: 0301 addi t1,t1,0 - ff4: 0900 addi s0,sp,144 - ff6: 0000 unimp - ff8: 0301 addi t1,t1,0 - ffa: 0900 addi s0,sp,144 - ffc: 0000 unimp - ffe: 0301 addi t1,t1,0 - 1000: 0900 addi s0,sp,144 - 1002: 0014 0x14 - 1004: 0301 addi t1,t1,0 - 1006: 0900 addi s0,sp,144 - 1008: 0020 addi s0,sp,8 - 100a: 0301 addi t1,t1,0 - 100c: 0901 addi s2,s2,0 - 100e: 0000 unimp - 1010: 0501 addi a0,a0,0 - 1012: 00030607 0x30607 - 1016: 0009 c.nop 2 - 1018: 0100 addi s0,sp,128 - 101a: 0805 addi a6,a6,1 - 101c: 0306 slli t1,t1,0x1 - 101e: 090a slli s2,s2,0x2 - 1020: 0004 0x4 - 1022: 0501 addi a0,a0,0 - 1024: 0003060b 0x3060b - 1028: 0009 c.nop 2 - 102a: 0100 addi s0,sp,128 - 102c: 1405 addi s0,s0,-31 - 102e: 04090003 lb zero,64(s2) - 1032: 0100 addi s0,sp,128 - 1034: 0505 addi a0,a0,1 - 1036: 0306 slli t1,t1,0x1 - 1038: 0902 c.slli64 s2 - 103a: 0004 0x4 - 103c: 0301 addi t1,t1,0 - 103e: 0901 addi s2,s2,0 - 1040: 0000 unimp - 1042: 0301 addi t1,t1,0 - 1044: 0900 addi s0,sp,144 - 1046: 0000 unimp + f76: 0000 unimp + f78: 0501 addi a0,a0,0 + f7a: 09150307 0x9150307 + f7e: 0004 0x4 + f80: 0501 addi a0,a0,0 + f82: 060a slli a2,a2,0x2 + f84: 00090003 lb zero,0(s2) + f88: 0100 addi s0,sp,128 + f8a: 0405 addi s0,s0,1 + f8c: 0306 slli t1,t1,0x1 + f8e: 00040913 mv s2,s0 + f92: 0301 addi t1,t1,0 + f94: 0900 addi s0,sp,144 + f96: 0000 unimp + f98: 0301 addi t1,t1,0 + f9a: 0900 addi s0,sp,144 + f9c: 0000 unimp + f9e: 0301 addi t1,t1,0 + fa0: 0900 addi s0,sp,144 + fa2: 0000 unimp + fa4: 0301 addi t1,t1,0 + fa6: 0900 addi s0,sp,144 + fa8: 0000 unimp + faa: 0301 addi t1,t1,0 + fac: 0900 addi s0,sp,144 + fae: 0014 0x14 + fb0: 0301 addi t1,t1,0 + fb2: 0900 addi s0,sp,144 + fb4: 0020 addi s0,sp,8 + fb6: 0301 addi t1,t1,0 + fb8: 0901 addi s2,s2,0 + fba: 0000 unimp + fbc: 0501 addi a0,a0,0 + fbe: 00030607 0x30607 + fc2: 0009 c.nop 2 + fc4: 0100 addi s0,sp,128 + fc6: 0805 addi a6,a6,1 + fc8: 0306 slli t1,t1,0x1 + fca: 090a slli s2,s2,0x2 + fcc: 0004 0x4 + fce: 0501 addi a0,a0,0 + fd0: 0003060b 0x3060b + fd4: 0009 c.nop 2 + fd6: 0100 addi s0,sp,128 + fd8: 1405 addi s0,s0,-31 + fda: 04090003 lb zero,64(s2) + fde: 0100 addi s0,sp,128 + fe0: 0505 addi a0,a0,1 + fe2: 0306 slli t1,t1,0x1 + fe4: 0902 c.slli64 s2 + fe6: 0004 0x4 + fe8: 0301 addi t1,t1,0 + fea: 0901 addi s2,s2,0 + fec: 0000 unimp + fee: 0301 addi t1,t1,0 + ff0: 0900 addi s0,sp,144 + ff2: 0000 unimp + ff4: 0301 addi t1,t1,0 + ff6: 0900 addi s0,sp,144 + ff8: 0000 unimp + ffa: 0301 addi t1,t1,0 + ffc: 0900 addi s0,sp,144 + ffe: 0004 0x4 + 1000: 0301 addi t1,t1,0 + 1002: 0900 addi s0,sp,144 + 1004: 000c 0xc + 1006: 0301 addi t1,t1,0 + 1008: 0900 addi s0,sp,144 + 100a: 0000 unimp + 100c: 0501 addi a0,a0,0 + 100e: 0308 addi a0,sp,384 + 1010: 0905 addi s2,s2,1 + 1012: 0000 unimp + 1014: 0301 addi t1,t1,0 + 1016: 0902 c.slli64 s2 + 1018: 0000 unimp + 101a: 0501 addi a0,a0,0 + 101c: 0305 addi t1,t1,1 + 101e: 0902 c.slli64 s2 + 1020: 0000 unimp + 1022: 0301 addi t1,t1,0 + 1024: 0901 addi s2,s2,0 + 1026: 0000 unimp + 1028: 0301 addi t1,t1,0 + 102a: 0901 addi s2,s2,0 + 102c: 0000 unimp + 102e: 0501 addi a0,a0,0 + 1030: 060d addi a2,a2,3 + 1032: 00090003 lb zero,0(s2) + 1036: 0100 addi s0,sp,128 + 1038: 0405 addi s0,s0,1 + 103a: 0c096703 0xc096703 + 103e: 0100 addi s0,sp,128 + 1040: 0805 addi a6,a6,1 + 1042: 0306 slli t1,t1,0x1 + 1044: 091e slli s2,s2,0x7 + 1046: 0014 0x14 1048: 0301 addi t1,t1,0 - 104a: 0900 addi s0,sp,144 - 104c: 0000 unimp + 104a: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> 104e: 0301 addi t1,t1,0 - 1050: 0900 addi s0,sp,144 - 1052: 0004 0x4 - 1054: 0301 addi t1,t1,0 - 1056: 0900 addi s0,sp,144 - 1058: 000c 0xc - 105a: 0301 addi t1,t1,0 - 105c: 0900 addi s0,sp,144 - 105e: 0000 unimp - 1060: 0501 addi a0,a0,0 - 1062: 0308 addi a0,sp,384 - 1064: 0905 addi s2,s2,1 - 1066: 0000 unimp - 1068: 0301 addi t1,t1,0 - 106a: 0902 c.slli64 s2 - 106c: 0000 unimp - 106e: 0501 addi a0,a0,0 - 1070: 0305 addi t1,t1,1 - 1072: 0902 c.slli64 s2 - 1074: 0000 unimp - 1076: 0301 addi t1,t1,0 - 1078: 0901 addi s2,s2,0 - 107a: 0000 unimp - 107c: 0301 addi t1,t1,0 - 107e: 0901 addi s2,s2,0 - 1080: 0000 unimp - 1082: 0501 addi a0,a0,0 - 1084: 060d addi a2,a2,3 - 1086: 00090003 lb zero,0(s2) - 108a: 0100 addi s0,sp,128 - 108c: 0405 addi s0,s0,1 - 108e: 0c096703 0xc096703 - 1092: 0100 addi s0,sp,128 - 1094: 0805 addi a6,a6,1 - 1096: 0306 slli t1,t1,0x1 - 1098: 091e slli s2,s2,0x7 - 109a: 0014 0x14 - 109c: 0301 addi t1,t1,0 - 109e: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> - 10a2: 0301 addi t1,t1,0 - 10a4: 0902 c.slli64 s2 - 10a6: 0000 unimp - 10a8: 0501 addi a0,a0,0 - 10aa: 061e slli a2,a2,0x7 - 10ac: 00090003 lb zero,0(s2) - 10b0: 0100 addi s0,sp,128 - 10b2: 1105 addi sp,sp,-31 - 10b4: 04090003 lb zero,64(s2) - 10b8: 0100 addi s0,sp,128 - 10ba: 0b05 addi s6,s6,1 - 10bc: 04090003 lb zero,64(s2) - 10c0: 0100 addi s0,sp,128 - 10c2: 0805 addi a6,a6,1 - 10c4: 0306 slli t1,t1,0x1 - 10c6: 0901 addi s2,s2,0 - 10c8: 0004 0x4 - 10ca: 0501 addi a0,a0,0 - 10cc: 0103060b 0x103060b - 10d0: 0009 c.nop 2 - 10d2: 0100 addi s0,sp,128 - 10d4: 0805 addi a6,a6,1 - 10d6: 04090403 lb s0,64(s2) - 10da: 0100 addi s0,sp,128 - 10dc: 1105 addi sp,sp,-31 - 10de: 08097d03 0x8097d03 - 10e2: 0100 addi s0,sp,128 - 10e4: 1e05 addi t3,t3,-31 - 10e6: 04090003 lb zero,64(s2) - 10ea: 0100 addi s0,sp,128 - 10ec: 0b05 addi s6,s6,1 - 10ee: 04090003 lb zero,64(s2) - 10f2: 0100 addi s0,sp,128 - 10f4: 0805 addi a6,a6,1 - 10f6: 04090303 lb t1,64(s2) - 10fa: 0100 addi s0,sp,128 - 10fc: 0b05 addi s6,s6,1 - 10fe: 0c097b03 0xc097b03 - 1102: 0100 addi s0,sp,128 - 1104: 0805 addi a6,a6,1 - 1106: 0306 slli t1,t1,0x1 - 1108: 0901 addi s2,s2,0 - 110a: 0004 0x4 + 1050: 0902 c.slli64 s2 + 1052: 0000 unimp + 1054: 0501 addi a0,a0,0 + 1056: 061e slli a2,a2,0x7 + 1058: 00090003 lb zero,0(s2) + 105c: 0100 addi s0,sp,128 + 105e: 1105 addi sp,sp,-31 + 1060: 04090003 lb zero,64(s2) + 1064: 0100 addi s0,sp,128 + 1066: 0b05 addi s6,s6,1 + 1068: 04090003 lb zero,64(s2) + 106c: 0100 addi s0,sp,128 + 106e: 0805 addi a6,a6,1 + 1070: 0306 slli t1,t1,0x1 + 1072: 0901 addi s2,s2,0 + 1074: 0004 0x4 + 1076: 0501 addi a0,a0,0 + 1078: 0103060b 0x103060b + 107c: 0009 c.nop 2 + 107e: 0100 addi s0,sp,128 + 1080: 0805 addi a6,a6,1 + 1082: 04090403 lb s0,64(s2) + 1086: 0100 addi s0,sp,128 + 1088: 1105 addi sp,sp,-31 + 108a: 08097d03 0x8097d03 + 108e: 0100 addi s0,sp,128 + 1090: 1e05 addi t3,t3,-31 + 1092: 04090003 lb zero,64(s2) + 1096: 0100 addi s0,sp,128 + 1098: 0b05 addi s6,s6,1 + 109a: 04090003 lb zero,64(s2) + 109e: 0100 addi s0,sp,128 + 10a0: 0805 addi a6,a6,1 + 10a2: 04090303 lb t1,64(s2) + 10a6: 0100 addi s0,sp,128 + 10a8: 0b05 addi s6,s6,1 + 10aa: 0c097b03 0xc097b03 + 10ae: 0100 addi s0,sp,128 + 10b0: 0805 addi a6,a6,1 + 10b2: 0306 slli t1,t1,0x1 + 10b4: 0901 addi s2,s2,0 + 10b6: 0004 0x4 + 10b8: 0301 addi t1,t1,0 + 10ba: 0901 addi s2,s2,0 + 10bc: 0000 unimp + 10be: 0301 addi t1,t1,0 + 10c0: 0901 addi s2,s2,0 + 10c2: 0000 unimp + 10c4: 0501 addi a0,a0,0 + 10c6: 0003060b 0x3060b + 10ca: 0009 c.nop 2 + 10cc: 0100 addi s0,sp,128 + 10ce: 0805 addi a6,a6,1 + 10d0: 0306 slli t1,t1,0x1 + 10d2: 0902 c.slli64 s2 + 10d4: 0004 0x4 + 10d6: 0301 addi t1,t1,0 + 10d8: 0900 addi s0,sp,144 + 10da: 0000 unimp + 10dc: 0301 addi t1,t1,0 + 10de: 0900 addi s0,sp,144 + 10e0: 0000 unimp + 10e2: 0301 addi t1,t1,0 + 10e4: 0900 addi s0,sp,144 + 10e6: 0000 unimp + 10e8: 0301 addi t1,t1,0 + 10ea: 0900 addi s0,sp,144 + 10ec: 0000 unimp + 10ee: 0301 addi t1,t1,0 + 10f0: 0900 addi s0,sp,144 + 10f2: 0000 unimp + 10f4: 0301 addi t1,t1,0 + 10f6: 0900 addi s0,sp,144 + 10f8: 0000 unimp + 10fa: 0301 addi t1,t1,0 + 10fc: 0900 addi s0,sp,144 + 10fe: 0004 0x4 + 1100: 0301 addi t1,t1,0 + 1102: 0900 addi s0,sp,144 + 1104: 000c 0xc + 1106: 0301 addi t1,t1,0 + 1108: 0900 addi s0,sp,144 + 110a: 0000 unimp 110c: 0301 addi t1,t1,0 - 110e: 0901 addi s2,s2,0 - 1110: 0000 unimp + 110e: 0900 addi s0,sp,144 + 1110: 0008 0x8 1112: 0301 addi t1,t1,0 - 1114: 0901 addi s2,s2,0 - 1116: 0000 unimp - 1118: 0501 addi a0,a0,0 - 111a: 0003060b 0x3060b - 111e: 0009 c.nop 2 - 1120: 0100 addi s0,sp,128 - 1122: 0805 addi a6,a6,1 - 1124: 0306 slli t1,t1,0x1 - 1126: 0902 c.slli64 s2 - 1128: 0004 0x4 + 1114: 0900 addi s0,sp,144 + 1116: 0008 0x8 + 1118: 0301 addi t1,t1,0 + 111a: 0900 addi s0,sp,144 + 111c: 0004 0x4 + 111e: 0301 addi t1,t1,0 + 1120: 0900 addi s0,sp,144 + 1122: 0004 0x4 + 1124: 0301 addi t1,t1,0 + 1126: 0900 addi s0,sp,144 + 1128: 0008 0x8 112a: 0301 addi t1,t1,0 112c: 0900 addi s0,sp,144 - 112e: 0000 unimp + 112e: 0004 0x4 1130: 0301 addi t1,t1,0 1132: 0900 addi s0,sp,144 - 1134: 0000 unimp + 1134: 0004 0x4 1136: 0301 addi t1,t1,0 1138: 0900 addi s0,sp,144 - 113a: 0000 unimp + 113a: 000c 0xc 113c: 0301 addi t1,t1,0 113e: 0900 addi s0,sp,144 - 1140: 0000 unimp + 1140: 000c 0xc 1142: 0301 addi t1,t1,0 1144: 0900 addi s0,sp,144 1146: 0000 unimp 1148: 0301 addi t1,t1,0 114a: 0900 addi s0,sp,144 - 114c: 0000 unimp + 114c: 0008 0x8 114e: 0301 addi t1,t1,0 1150: 0900 addi s0,sp,144 - 1152: 0004 0x4 + 1152: 0008 0x8 1154: 0301 addi t1,t1,0 1156: 0900 addi s0,sp,144 - 1158: 000c 0xc + 1158: 0004 0x4 115a: 0301 addi t1,t1,0 115c: 0900 addi s0,sp,144 - 115e: 0000 unimp + 115e: 0004 0x4 1160: 0301 addi t1,t1,0 1162: 0900 addi s0,sp,144 1164: 0008 0x8 1166: 0301 addi t1,t1,0 1168: 0900 addi s0,sp,144 - 116a: 0008 0x8 - 116c: 0301 addi t1,t1,0 - 116e: 0900 addi s0,sp,144 - 1170: 0004 0x4 - 1172: 0301 addi t1,t1,0 - 1174: 0900 addi s0,sp,144 - 1176: 0004 0x4 - 1178: 0301 addi t1,t1,0 - 117a: 0900 addi s0,sp,144 - 117c: 0008 0x8 - 117e: 0301 addi t1,t1,0 - 1180: 0900 addi s0,sp,144 - 1182: 0004 0x4 - 1184: 0301 addi t1,t1,0 - 1186: 0900 addi s0,sp,144 - 1188: 0004 0x4 - 118a: 0301 addi t1,t1,0 - 118c: 0900 addi s0,sp,144 - 118e: 000c 0xc - 1190: 0301 addi t1,t1,0 - 1192: 0900 addi s0,sp,144 - 1194: 000c 0xc - 1196: 0301 addi t1,t1,0 - 1198: 0900 addi s0,sp,144 - 119a: 0000 unimp - 119c: 0301 addi t1,t1,0 - 119e: 0900 addi s0,sp,144 - 11a0: 0008 0x8 - 11a2: 0301 addi t1,t1,0 - 11a4: 0900 addi s0,sp,144 - 11a6: 0008 0x8 - 11a8: 0301 addi t1,t1,0 - 11aa: 0900 addi s0,sp,144 - 11ac: 0004 0x4 - 11ae: 0301 addi t1,t1,0 - 11b0: 0900 addi s0,sp,144 - 11b2: 0004 0x4 - 11b4: 0301 addi t1,t1,0 - 11b6: 0900 addi s0,sp,144 - 11b8: 0008 0x8 - 11ba: 0301 addi t1,t1,0 - 11bc: 0900 addi s0,sp,144 - 11be: 0004 0x4 - 11c0: 0601 addi a2,a2,0 - 11c2: 04090103 lb sp,64(s2) - 11c6: 0100 addi s0,sp,128 - 11c8: 04097f03 0x4097f03 - 11cc: 0100 addi s0,sp,128 - 11ce: 0306 slli t1,t1,0x1 + 116a: 0004 0x4 + 116c: 0601 addi a2,a2,0 + 116e: 04090103 lb sp,64(s2) + 1172: 0100 addi s0,sp,128 + 1174: 04097f03 0x4097f03 + 1178: 0100 addi s0,sp,128 + 117a: 0306 slli t1,t1,0x1 + 117c: 0900 addi s0,sp,144 + 117e: 0004 0x4 + 1180: 0301 addi t1,t1,0 + 1182: 0900 addi s0,sp,144 + 1184: 0000 unimp + 1186: 0301 addi t1,t1,0 + 1188: 0901 addi s2,s2,0 + 118a: 0000 unimp + 118c: 0301 addi t1,t1,0 + 118e: 0900 addi s0,sp,144 + 1190: 0000 unimp + 1192: 0301 addi t1,t1,0 + 1194: 0900 addi s0,sp,144 + 1196: 0000 unimp + 1198: 0301 addi t1,t1,0 + 119a: 0900 addi s0,sp,144 + 119c: 0000 unimp + 119e: 0301 addi t1,t1,0 + 11a0: 0900 addi s0,sp,144 + 11a2: 0008 0x8 + 11a4: 0301 addi t1,t1,0 + 11a6: 0900 addi s0,sp,144 + 11a8: 0008 0x8 + 11aa: 0301 addi t1,t1,0 + 11ac: 0900 addi s0,sp,144 + 11ae: 0004 0x4 + 11b0: 0301 addi t1,t1,0 + 11b2: 0900 addi s0,sp,144 + 11b4: 0000 unimp + 11b6: 0301 addi t1,t1,0 + 11b8: 0900 addi s0,sp,144 + 11ba: 0004 0x4 + 11bc: 0301 addi t1,t1,0 + 11be: 0900 addi s0,sp,144 + 11c0: 0000 unimp + 11c2: 0301 addi t1,t1,0 + 11c4: 0900 addi s0,sp,144 + 11c6: 0004 0x4 + 11c8: 0301 addi t1,t1,0 + 11ca: 0900 addi s0,sp,144 + 11cc: 0008 0x8 + 11ce: 0301 addi t1,t1,0 11d0: 0900 addi s0,sp,144 11d2: 0004 0x4 11d4: 0301 addi t1,t1,0 11d6: 0900 addi s0,sp,144 - 11d8: 0000 unimp + 11d8: 0008 0x8 11da: 0301 addi t1,t1,0 - 11dc: 0901 addi s2,s2,0 - 11de: 0000 unimp + 11dc: 0900 addi s0,sp,144 + 11de: 0004 0x4 11e0: 0301 addi t1,t1,0 11e2: 0900 addi s0,sp,144 - 11e4: 0000 unimp + 11e4: 0004 0x4 11e6: 0301 addi t1,t1,0 11e8: 0900 addi s0,sp,144 - 11ea: 0000 unimp + 11ea: 001c 0x1c 11ec: 0301 addi t1,t1,0 11ee: 0900 addi s0,sp,144 - 11f0: 0000 unimp + 11f0: 0004 0x4 11f2: 0301 addi t1,t1,0 - 11f4: 0900 addi s0,sp,144 - 11f6: 0008 0x8 - 11f8: 0301 addi t1,t1,0 - 11fa: 0900 addi s0,sp,144 - 11fc: 0008 0x8 - 11fe: 0301 addi t1,t1,0 - 1200: 0900 addi s0,sp,144 - 1202: 0004 0x4 - 1204: 0301 addi t1,t1,0 - 1206: 0900 addi s0,sp,144 - 1208: 0000 unimp - 120a: 0301 addi t1,t1,0 - 120c: 0900 addi s0,sp,144 - 120e: 0004 0x4 - 1210: 0301 addi t1,t1,0 - 1212: 0900 addi s0,sp,144 - 1214: 0000 unimp - 1216: 0301 addi t1,t1,0 - 1218: 0900 addi s0,sp,144 - 121a: 0004 0x4 - 121c: 0301 addi t1,t1,0 - 121e: 0900 addi s0,sp,144 - 1220: 0008 0x8 - 1222: 0301 addi t1,t1,0 - 1224: 0900 addi s0,sp,144 - 1226: 0004 0x4 - 1228: 0301 addi t1,t1,0 - 122a: 0900 addi s0,sp,144 - 122c: 0008 0x8 - 122e: 0301 addi t1,t1,0 - 1230: 0900 addi s0,sp,144 - 1232: 0004 0x4 - 1234: 0301 addi t1,t1,0 - 1236: 0900 addi s0,sp,144 - 1238: 0004 0x4 - 123a: 0301 addi t1,t1,0 - 123c: 0900 addi s0,sp,144 - 123e: 001c 0x1c - 1240: 0301 addi t1,t1,0 - 1242: 0900 addi s0,sp,144 - 1244: 0004 0x4 + 11f4: 0902 c.slli64 s2 + 11f6: 0000 unimp + 11f8: 0501 addi a0,a0,0 + 11fa: 0003060b 0x3060b + 11fe: 0009 c.nop 2 + 1200: 0100 addi s0,sp,128 + 1202: 1405 addi s0,s0,-31 + 1204: 04090003 lb zero,64(s2) + 1208: 0100 addi s0,sp,128 + 120a: 2105 jal 162a <_start-0x7fffe9d6> + 120c: 04090003 lb zero,64(s2) + 1210: 0100 addi s0,sp,128 + 1212: 0505 addi a0,a0,1 + 1214: 0306 slli t1,t1,0x1 + 1216: 0902 c.slli64 s2 + 1218: 0004 0x4 + 121a: 0301 addi t1,t1,0 + 121c: 0901 addi s2,s2,0 + 121e: 0000 unimp + 1220: 0301 addi t1,t1,0 + 1222: 0900 addi s0,sp,144 + 1224: 0000 unimp + 1226: 0301 addi t1,t1,0 + 1228: 0900 addi s0,sp,144 + 122a: 0000 unimp + 122c: 0301 addi t1,t1,0 + 122e: 0900 addi s0,sp,144 + 1230: 0004 0x4 + 1232: 0301 addi t1,t1,0 + 1234: 0900 addi s0,sp,144 + 1236: 000c 0xc + 1238: 0301 addi t1,t1,0 + 123a: 0900 addi s0,sp,144 + 123c: 0004 0x4 + 123e: 0501 addi a0,a0,0 + 1240: 0308 addi a0,sp,384 + 1242: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> 1246: 0301 addi t1,t1,0 - 1248: 0902 c.slli64 s2 - 124a: 0000 unimp + 1248: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> 124c: 0501 addi a0,a0,0 - 124e: 0003060b 0x3060b - 1252: 0009 c.nop 2 - 1254: 0100 addi s0,sp,128 - 1256: 1405 addi s0,s0,-31 - 1258: 04090003 lb zero,64(s2) - 125c: 0100 addi s0,sp,128 - 125e: 2105 jal 167e <_start-0x7fffe982> - 1260: 04090003 lb zero,64(s2) - 1264: 0100 addi s0,sp,128 - 1266: 0505 addi a0,a0,1 - 1268: 0306 slli t1,t1,0x1 - 126a: 0902 c.slli64 s2 - 126c: 0004 0x4 - 126e: 0301 addi t1,t1,0 - 1270: 0901 addi s2,s2,0 - 1272: 0000 unimp - 1274: 0301 addi t1,t1,0 - 1276: 0900 addi s0,sp,144 - 1278: 0000 unimp - 127a: 0301 addi t1,t1,0 - 127c: 0900 addi s0,sp,144 - 127e: 0000 unimp - 1280: 0301 addi t1,t1,0 - 1282: 0900 addi s0,sp,144 - 1284: 0004 0x4 - 1286: 0301 addi t1,t1,0 - 1288: 0900 addi s0,sp,144 - 128a: 000c 0xc - 128c: 0301 addi t1,t1,0 - 128e: 0900 addi s0,sp,144 + 124e: 0305 addi t1,t1,1 + 1250: 0902 c.slli64 s2 + 1252: 0000 unimp + 1254: 0301 addi t1,t1,0 + 1256: 0900 addi s0,sp,144 + 1258: 0000 unimp + 125a: 0301 addi t1,t1,0 + 125c: 0900 addi s0,sp,144 + 125e: 0000 unimp + 1260: 0301 addi t1,t1,0 + 1262: 0900 addi s0,sp,144 + 1264: 0004 0x4 + 1266: 0301 addi t1,t1,0 + 1268: 0900 addi s0,sp,144 + 126a: 000c 0xc + 126c: 0301 addi t1,t1,0 + 126e: 0900 addi s0,sp,144 + 1270: 0000 unimp + 1272: 0301 addi t1,t1,0 + 1274: 0901 addi s2,s2,0 + 1276: 0000 unimp + 1278: 0501 addi a0,a0,0 + 127a: 0614 addi a3,sp,768 + 127c: 00090003 lb zero,0(s2) + 1280: 0100 addi s0,sp,128 + 1282: 2005 jal 12a2 <_start-0x7fffed5e> + 1284: 04090003 lb zero,64(s2) + 1288: 0100 addi s0,sp,128 + 128a: 0505 addi a0,a0,1 + 128c: 0306 slli t1,t1,0x1 + 128e: 0901 addi s2,s2,0 1290: 0004 0x4 - 1292: 0501 addi a0,a0,0 - 1294: 0308 addi a0,sp,384 - 1296: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> - 129a: 0301 addi t1,t1,0 - 129c: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> - 12a0: 0501 addi a0,a0,0 - 12a2: 0305 addi t1,t1,1 - 12a4: 0902 c.slli64 s2 - 12a6: 0000 unimp - 12a8: 0301 addi t1,t1,0 - 12aa: 0900 addi s0,sp,144 - 12ac: 0000 unimp - 12ae: 0301 addi t1,t1,0 - 12b0: 0900 addi s0,sp,144 - 12b2: 0000 unimp - 12b4: 0301 addi t1,t1,0 - 12b6: 0900 addi s0,sp,144 - 12b8: 0004 0x4 - 12ba: 0301 addi t1,t1,0 - 12bc: 0900 addi s0,sp,144 - 12be: 000c 0xc - 12c0: 0301 addi t1,t1,0 - 12c2: 0900 addi s0,sp,144 - 12c4: 0000 unimp - 12c6: 0301 addi t1,t1,0 - 12c8: 0901 addi s2,s2,0 - 12ca: 0000 unimp - 12cc: 0501 addi a0,a0,0 - 12ce: 0614 addi a3,sp,768 - 12d0: 00090003 lb zero,0(s2) - 12d4: 0100 addi s0,sp,128 - 12d6: 2005 jal 12f6 <_start-0x7fffed0a> - 12d8: 04090003 lb zero,64(s2) - 12dc: 0100 addi s0,sp,128 - 12de: 0505 addi a0,a0,1 - 12e0: 0306 slli t1,t1,0x1 - 12e2: 0901 addi s2,s2,0 - 12e4: 0004 0x4 - 12e6: 0301 addi t1,t1,0 - 12e8: 0901 addi s2,s2,0 - 12ea: 0000 unimp - 12ec: 0501 addi a0,a0,0 - 12ee: 060d addi a2,a2,3 - 12f0: 00090003 lb zero,0(s2) - 12f4: 0100 addi s0,sp,128 - 12f6: 0c09 addi s8,s8,2 - 12f8: 0000 unimp - 12fa: 0101 addi sp,sp,0 - 12fc: 00000f97 auipc t6,0x0 - 1300: 00930003 lb zero,9(t1) - 1304: 0000 unimp - 1306: 0101 addi sp,sp,0 - 1308: 000d0efb 0xd0efb - 130c: 0101 addi sp,sp,0 - 130e: 0101 addi sp,sp,0 - 1310: 0000 unimp - 1312: 0100 addi s0,sp,128 - 1314: 0000 unimp - 1316: 2e01 jal 1626 <_start-0x7fffe9da> - 1318: 2f2e fld ft10,200(sp) - 131a: 2e2e fld ft8,200(sp) - 131c: 2f2e2e2f 0x2f2e2e2f - 1320: 2e2e fld ft8,200(sp) - 1322: 7369722f 0x7369722f - 1326: 672d7663 bgeu s10,s2,1992 <_start-0x7fffe66e> - 132a: 6c2f6363 bltu t5,sp,19f0 <_start-0x7fffe610> - 132e: 6269 lui tp,0x1a - 1330: 2f636367 0x2f636367 - 1334: 74666f73 csrrsi t5,0x746,12 - 1338: 662d lui a2,0xb - 133a: 0070 addi a2,sp,12 - 133c: 2e2e fld ft8,200(sp) - 133e: 2f2e2e2f 0x2f2e2e2f - 1342: 2e2e fld ft8,200(sp) - 1344: 2f2e2e2f 0x2f2e2e2f - 1348: 6972 flw fs2,28(sp) - 134a: 2d766373 csrrsi t1,0x2d7,12 - 134e: 2f636367 0x2f636367 - 1352: 696c flw fa1,84(a0) - 1354: 6762 flw fa4,24(sp) - 1356: 2e2f6363 bltu t5,sp,163c <_start-0x7fffe9c4> - 135a: 2f2e fld ft10,200(sp) - 135c: 6e69 lui t3,0x1a - 135e: 64756c63 bltu a0,t2,19b6 <_start-0x7fffe64a> - 1362: 0065 c.nop 25 - 1364: 6400 flw fs0,8(s0) - 1366: 7669 lui a2,0xffffa - 1368: 6664 flw fs1,76(a2) - 136a: 00632e33 slt t3,t1,t1 - 136e: 0001 nop - 1370: 7300 flw fs0,32(a4) - 1372: 2d74666f jal a2,47e48 <_start-0x7ffb81b8> - 1376: 7066 flw ft0,120(sp) - 1378: 682e flw fa6,200(sp) - 137a: 0100 addi s0,sp,128 - 137c: 0000 unimp - 137e: 6f64 flw fs1,92(a4) - 1380: 6275 lui tp,0x1d - 1382: 656c flw fa1,76(a0) - 1384: 682e flw fa6,200(sp) - 1386: 0100 addi s0,sp,128 - 1388: 0000 unimp - 138a: 6f6c flw fa1,92(a4) - 138c: 676e flw fa4,216(sp) - 138e: 6f6c flw fa1,92(a4) - 1390: 676e flw fa4,216(sp) - 1392: 682e flw fa6,200(sp) - 1394: 0200 addi s0,sp,256 + 1292: 0301 addi t1,t1,0 + 1294: 0901 addi s2,s2,0 + 1296: 0000 unimp + 1298: 0501 addi a0,a0,0 + 129a: 060d addi a2,a2,3 + 129c: 00090003 lb zero,0(s2) + 12a0: 0100 addi s0,sp,128 + 12a2: 0c09 addi s8,s8,2 + 12a4: 0000 unimp + 12a6: 0101 addi sp,sp,0 + 12a8: 00000f97 auipc t6,0x0 + 12ac: 00930003 lb zero,9(t1) + 12b0: 0000 unimp + 12b2: 0101 addi sp,sp,0 + 12b4: 000d0efb 0xd0efb + 12b8: 0101 addi sp,sp,0 + 12ba: 0101 addi sp,sp,0 + 12bc: 0000 unimp + 12be: 0100 addi s0,sp,128 + 12c0: 0000 unimp + 12c2: 2e01 jal 15d2 <_start-0x7fffea2e> + 12c4: 2f2e fld ft10,200(sp) + 12c6: 2e2e fld ft8,200(sp) + 12c8: 2f2e2e2f 0x2f2e2e2f + 12cc: 2e2e fld ft8,200(sp) + 12ce: 7369722f 0x7369722f + 12d2: 672d7663 bgeu s10,s2,193e <_start-0x7fffe6c2> + 12d6: 6c2f6363 bltu t5,sp,199c <_start-0x7fffe664> + 12da: 6269 lui tp,0x1a + 12dc: 2f636367 0x2f636367 + 12e0: 74666f73 csrrsi t5,0x746,12 + 12e4: 662d lui a2,0xb + 12e6: 0070 addi a2,sp,12 + 12e8: 2e2e fld ft8,200(sp) + 12ea: 2f2e2e2f 0x2f2e2e2f + 12ee: 2e2e fld ft8,200(sp) + 12f0: 2f2e2e2f 0x2f2e2e2f + 12f4: 6972 flw fs2,28(sp) + 12f6: 2d766373 csrrsi t1,0x2d7,12 + 12fa: 2f636367 0x2f636367 + 12fe: 696c flw fa1,84(a0) + 1300: 6762 flw fa4,24(sp) + 1302: 2e2f6363 bltu t5,sp,15e8 <_start-0x7fffea18> + 1306: 2f2e fld ft10,200(sp) + 1308: 6e69 lui t3,0x1a + 130a: 64756c63 bltu a0,t2,1962 <_start-0x7fffe69e> + 130e: 0065 c.nop 25 + 1310: 6400 flw fs0,8(s0) + 1312: 7669 lui a2,0xffffa + 1314: 6664 flw fs1,76(a2) + 1316: 00632e33 slt t3,t1,t1 + 131a: 0001 nop + 131c: 7300 flw fs0,32(a4) + 131e: 2d74666f jal a2,47df4 <_start-0x7ffb820c> + 1322: 7066 flw ft0,120(sp) + 1324: 682e flw fa6,200(sp) + 1326: 0100 addi s0,sp,128 + 1328: 0000 unimp + 132a: 6f64 flw fs1,92(a4) + 132c: 6275 lui tp,0x1d + 132e: 656c flw fa1,76(a0) + 1330: 682e flw fa6,200(sp) + 1332: 0100 addi s0,sp,128 + 1334: 0000 unimp + 1336: 6f6c flw fa1,92(a4) + 1338: 676e flw fa4,216(sp) + 133a: 6f6c flw fa1,92(a4) + 133c: 676e flw fa4,216(sp) + 133e: 682e flw fa6,200(sp) + 1340: 0200 addi s0,sp,256 + 1342: 0000 unimp + 1344: 0500 addi s0,sp,640 + 1346: 0001 nop + 1348: 0205 addi tp,tp,1 + 134a: 0d08 addi a0,sp,656 + 134c: 8001 c.srli64 s0 + 134e: 05012303 lw t1,80(sp) + 1352: 09010303 lb t1,144(sp) + 1356: 0000 unimp + 1358: 0301 addi t1,t1,0 + 135a: 0900 addi s0,sp,144 + 135c: 0000 unimp + 135e: 0501 addi a0,a0,0 + 1360: 030d addi t1,t1,3 + 1362: 0900 addi s0,sp,144 + 1364: 0000 unimp + 1366: 0501 addi a0,a0,0 + 1368: 09010303 lb t1,144(sp) + 136c: 0000 unimp + 136e: 0301 addi t1,t1,0 + 1370: 0900 addi s0,sp,144 + 1372: 0000 unimp + 1374: 0301 addi t1,t1,0 + 1376: 0900 addi s0,sp,144 + 1378: 0000 unimp + 137a: 0301 addi t1,t1,0 + 137c: 0900 addi s0,sp,144 + 137e: 0000 unimp + 1380: 0301 addi t1,t1,0 + 1382: 0901 addi s2,s2,0 + 1384: 0000 unimp + 1386: 0301 addi t1,t1,0 + 1388: 0900 addi s0,sp,144 + 138a: 0000 unimp + 138c: 0301 addi t1,t1,0 + 138e: 0900 addi s0,sp,144 + 1390: 0000 unimp + 1392: 0301 addi t1,t1,0 + 1394: 0900 addi s0,sp,144 1396: 0000 unimp - 1398: 0500 addi s0,sp,640 - 139a: 0001 nop - 139c: 0205 addi tp,tp,1 - 139e: 0c44 addi s1,sp,532 - 13a0: 8001 c.srli64 s0 - 13a2: 05012303 lw t1,80(sp) - 13a6: 09010303 lb t1,144(sp) - 13aa: 0000 unimp - 13ac: 0301 addi t1,t1,0 - 13ae: 0900 addi s0,sp,144 - 13b0: 0000 unimp - 13b2: 0501 addi a0,a0,0 - 13b4: 030d addi t1,t1,3 - 13b6: 0900 addi s0,sp,144 - 13b8: 0000 unimp - 13ba: 0501 addi a0,a0,0 - 13bc: 09010303 lb t1,144(sp) + 1398: 0301 addi t1,t1,0 + 139a: 0901 addi s2,s2,0 + 139c: 0000 unimp + 139e: 0301 addi t1,t1,0 + 13a0: 0900 addi s0,sp,144 + 13a2: 0000 unimp + 13a4: 0301 addi t1,t1,0 + 13a6: 0900 addi s0,sp,144 + 13a8: 0000 unimp + 13aa: 0301 addi t1,t1,0 + 13ac: 0900 addi s0,sp,144 + 13ae: 0000 unimp + 13b0: 0301 addi t1,t1,0 + 13b2: 0901 addi s2,s2,0 + 13b4: 0000 unimp + 13b6: 0301 addi t1,t1,0 + 13b8: 0902 c.slli64 s2 + 13ba: 0000 unimp + 13bc: 0301 addi t1,t1,0 + 13be: 0901 addi s2,s2,0 13c0: 0000 unimp 13c2: 0301 addi t1,t1,0 13c4: 0900 addi s0,sp,144 @@ -43312,1829 +43362,1815 @@ Disassembly of section .debug_line: 13d0: 0900 addi s0,sp,144 13d2: 0000 unimp 13d4: 0301 addi t1,t1,0 - 13d6: 0901 addi s2,s2,0 + 13d6: 0900 addi s0,sp,144 13d8: 0000 unimp 13da: 0301 addi t1,t1,0 13dc: 0900 addi s0,sp,144 13de: 0000 unimp - 13e0: 0301 addi t1,t1,0 - 13e2: 0900 addi s0,sp,144 - 13e4: 0000 unimp - 13e6: 0301 addi t1,t1,0 - 13e8: 0900 addi s0,sp,144 - 13ea: 0000 unimp - 13ec: 0301 addi t1,t1,0 - 13ee: 0901 addi s2,s2,0 - 13f0: 0000 unimp - 13f2: 0301 addi t1,t1,0 - 13f4: 0900 addi s0,sp,144 - 13f6: 0000 unimp - 13f8: 0301 addi t1,t1,0 - 13fa: 0900 addi s0,sp,144 - 13fc: 0000 unimp - 13fe: 0301 addi t1,t1,0 - 1400: 0900 addi s0,sp,144 - 1402: 0000 unimp - 1404: 0301 addi t1,t1,0 - 1406: 0901 addi s2,s2,0 - 1408: 0000 unimp - 140a: 0301 addi t1,t1,0 - 140c: 0902 c.slli64 s2 - 140e: 0000 unimp - 1410: 0301 addi t1,t1,0 - 1412: 0901 addi s2,s2,0 - 1414: 0000 unimp - 1416: 0301 addi t1,t1,0 - 1418: 0900 addi s0,sp,144 - 141a: 0000 unimp - 141c: 0301 addi t1,t1,0 - 141e: 0900 addi s0,sp,144 - 1420: 0000 unimp - 1422: 0301 addi t1,t1,0 + 13e0: 0501 addi a0,a0,0 + 13e2: 0601 addi a2,a2,0 + 13e4: 00097803 0x97803 + 13e8: 0100 addi s0,sp,128 + 13ea: 0305 addi t1,t1,1 + 13ec: 04090803 lb a6,64(s2) + 13f0: 0100 addi s0,sp,128 + 13f2: 0105 addi sp,sp,1 + 13f4: 04097803 0x4097803 + 13f8: 0100 addi s0,sp,128 + 13fa: 0305 addi t1,t1,1 + 13fc: 14090803 lb a6,320(s2) + 1400: 0100 addi s0,sp,128 + 1402: 0105 addi sp,sp,1 + 1404: 04097803 0x4097803 + 1408: 0100 addi s0,sp,128 + 140a: 0305 addi t1,t1,1 + 140c: 14090803 lb a6,320(s2) + 1410: 0100 addi s0,sp,128 + 1412: 0105 addi sp,sp,1 + 1414: 04097803 0x4097803 + 1418: 0100 addi s0,sp,128 + 141a: 0305 addi t1,t1,1 + 141c: 0c090803 lb a6,192(s2) + 1420: 0100 addi s0,sp,128 + 1422: 0306 slli t1,t1,0x1 1424: 0900 addi s0,sp,144 - 1426: 0000 unimp + 1426: 0004 0x4 1428: 0301 addi t1,t1,0 142a: 0900 addi s0,sp,144 142c: 0000 unimp 142e: 0301 addi t1,t1,0 1430: 0900 addi s0,sp,144 - 1432: 0000 unimp - 1434: 0501 addi a0,a0,0 - 1436: 0601 addi a2,a2,0 - 1438: 00097803 0x97803 - 143c: 0100 addi s0,sp,128 - 143e: 0305 addi t1,t1,1 - 1440: 04090803 lb a6,64(s2) - 1444: 0100 addi s0,sp,128 - 1446: 0105 addi sp,sp,1 - 1448: 04097803 0x4097803 - 144c: 0100 addi s0,sp,128 - 144e: 0305 addi t1,t1,1 - 1450: 14090803 lb a6,320(s2) - 1454: 0100 addi s0,sp,128 - 1456: 0105 addi sp,sp,1 - 1458: 04097803 0x4097803 - 145c: 0100 addi s0,sp,128 - 145e: 0305 addi t1,t1,1 - 1460: 14090803 lb a6,320(s2) - 1464: 0100 addi s0,sp,128 - 1466: 0105 addi sp,sp,1 - 1468: 04097803 0x4097803 - 146c: 0100 addi s0,sp,128 - 146e: 0305 addi t1,t1,1 - 1470: 0c090803 lb a6,192(s2) - 1474: 0100 addi s0,sp,128 - 1476: 0306 slli t1,t1,0x1 + 1432: 0004 0x4 + 1434: 0301 addi t1,t1,0 + 1436: 0900 addi s0,sp,144 + 1438: 0000 unimp + 143a: 0301 addi t1,t1,0 + 143c: 0900 addi s0,sp,144 + 143e: 0000 unimp + 1440: 0001 nop + 1442: 0402 c.slli64 s0 + 1444: 0301 addi t1,t1,0 + 1446: 0900 addi s0,sp,144 + 1448: 0010 0x10 + 144a: 0001 nop + 144c: 0402 c.slli64 s0 + 144e: 0301 addi t1,t1,0 + 1450: 0900 addi s0,sp,144 + 1452: 0000 unimp + 1454: 0001 nop + 1456: 0402 c.slli64 s0 + 1458: 0301 addi t1,t1,0 + 145a: 0900 addi s0,sp,144 + 145c: 0000 unimp + 145e: 0001 nop + 1460: 0402 c.slli64 s0 + 1462: 0301 addi t1,t1,0 + 1464: 0900 addi s0,sp,144 + 1466: 0000 unimp + 1468: 0001 nop + 146a: 0402 c.slli64 s0 + 146c: 0301 addi t1,t1,0 + 146e: 0900 addi s0,sp,144 + 1470: 0014 0x14 + 1472: 0001 nop + 1474: 0402 c.slli64 s0 + 1476: 0301 addi t1,t1,0 1478: 0900 addi s0,sp,144 147a: 0004 0x4 - 147c: 0301 addi t1,t1,0 - 147e: 0900 addi s0,sp,144 - 1480: 0000 unimp - 1482: 0301 addi t1,t1,0 - 1484: 0900 addi s0,sp,144 - 1486: 0004 0x4 - 1488: 0301 addi t1,t1,0 - 148a: 0900 addi s0,sp,144 - 148c: 0000 unimp - 148e: 0301 addi t1,t1,0 - 1490: 0900 addi s0,sp,144 - 1492: 0000 unimp - 1494: 0001 nop - 1496: 0402 c.slli64 s0 - 1498: 0301 addi t1,t1,0 - 149a: 0900 addi s0,sp,144 - 149c: 0010 0x10 - 149e: 0001 nop - 14a0: 0402 c.slli64 s0 - 14a2: 0301 addi t1,t1,0 - 14a4: 0900 addi s0,sp,144 - 14a6: 0000 unimp - 14a8: 0001 nop - 14aa: 0402 c.slli64 s0 - 14ac: 0301 addi t1,t1,0 - 14ae: 0900 addi s0,sp,144 - 14b0: 0000 unimp - 14b2: 0001 nop - 14b4: 0402 c.slli64 s0 - 14b6: 0301 addi t1,t1,0 - 14b8: 0900 addi s0,sp,144 - 14ba: 0000 unimp - 14bc: 0001 nop - 14be: 0402 c.slli64 s0 - 14c0: 0301 addi t1,t1,0 - 14c2: 0900 addi s0,sp,144 - 14c4: 0014 0x14 - 14c6: 0001 nop - 14c8: 0402 c.slli64 s0 - 14ca: 0301 addi t1,t1,0 - 14cc: 0900 addi s0,sp,144 - 14ce: 0004 0x4 - 14d0: 0001 nop - 14d2: 0402 c.slli64 s0 - 14d4: 0301 addi t1,t1,0 - 14d6: 0900 addi s0,sp,144 - 14d8: 0000 unimp - 14da: 0001 nop - 14dc: 0402 c.slli64 s0 - 14de: 0301 addi t1,t1,0 - 14e0: 0900 addi s0,sp,144 - 14e2: 0004 0x4 - 14e4: 0001 nop - 14e6: 0402 c.slli64 s0 - 14e8: 0301 addi t1,t1,0 - 14ea: 0900 addi s0,sp,144 - 14ec: 0000 unimp - 14ee: 0001 nop - 14f0: 0402 c.slli64 s0 - 14f2: 0329 addi t1,t1,10 - 14f4: 0900 addi s0,sp,144 - 14f6: 0000 unimp - 14f8: 0001 nop - 14fa: 0402 c.slli64 s0 - 14fc: 0329 addi t1,t1,10 - 14fe: 0900 addi s0,sp,144 - 1500: 0000 unimp - 1502: 0001 nop - 1504: 0402 c.slli64 s0 - 1506: 0308 addi a0,sp,384 - 1508: 0900 addi s0,sp,144 - 150a: 0004 0x4 - 150c: 0001 nop - 150e: 0402 c.slli64 s0 - 1510: 0308 addi a0,sp,384 - 1512: 0900 addi s0,sp,144 - 1514: 0000 unimp - 1516: 0001 nop - 1518: 0402 c.slli64 s0 - 151a: 0308 addi a0,sp,384 - 151c: 0901 addi s2,s2,0 - 151e: 0000 unimp - 1520: 0001 nop - 1522: 0402 c.slli64 s0 - 1524: 0308 addi a0,sp,384 - 1526: 0900 addi s0,sp,144 - 1528: 0000 unimp - 152a: 0001 nop - 152c: 0402 c.slli64 s0 - 152e: 0308 addi a0,sp,384 - 1530: 0900 addi s0,sp,144 - 1532: 0000 unimp - 1534: 0001 nop - 1536: 0402 c.slli64 s0 - 1538: 0308 addi a0,sp,384 - 153a: 0900 addi s0,sp,144 - 153c: 0000 unimp - 153e: 0001 nop - 1540: 0402 c.slli64 s0 - 1542: 0308 addi a0,sp,384 - 1544: 0900 addi s0,sp,144 - 1546: 0000 unimp - 1548: 0001 nop - 154a: 0402 c.slli64 s0 - 154c: 0308 addi a0,sp,384 - 154e: 0900 addi s0,sp,144 - 1550: 0000 unimp - 1552: 0001 nop - 1554: 0402 c.slli64 s0 - 1556: 0308 addi a0,sp,384 - 1558: 0900 addi s0,sp,144 - 155a: 0010 0x10 - 155c: 0001 nop - 155e: 0402 c.slli64 s0 - 1560: 0308 addi a0,sp,384 - 1562: 0900 addi s0,sp,144 - 1564: 0004 0x4 - 1566: 0001 nop - 1568: 0402 c.slli64 s0 - 156a: 0308 addi a0,sp,384 - 156c: 0900 addi s0,sp,144 - 156e: 0004 0x4 - 1570: 0001 nop - 1572: 0402 c.slli64 s0 - 1574: 0308 addi a0,sp,384 - 1576: 0900 addi s0,sp,144 - 1578: 0000 unimp - 157a: 0001 nop - 157c: 0402 c.slli64 s0 - 157e: 0308 addi a0,sp,384 - 1580: 0900 addi s0,sp,144 - 1582: 0000 unimp - 1584: 0601 addi a2,a2,0 - 1586: 04090003 lb zero,64(s2) - 158a: 0100 addi s0,sp,128 - 158c: 0200 addi s0,sp,256 - 158e: 0104 addi s1,sp,128 - 1590: 0306 slli t1,t1,0x1 - 1592: 0900 addi s0,sp,144 - 1594: 0008 0x8 - 1596: 0001 nop - 1598: 0402 c.slli64 s0 - 159a: 0301 addi t1,t1,0 - 159c: 0900 addi s0,sp,144 - 159e: 0000 unimp - 15a0: 0001 nop - 15a2: 0402 c.slli64 s0 - 15a4: 0301 addi t1,t1,0 - 15a6: 0900 addi s0,sp,144 - 15a8: 0000 unimp - 15aa: 0001 nop - 15ac: 0402 c.slli64 s0 - 15ae: 0301 addi t1,t1,0 - 15b0: 0900 addi s0,sp,144 - 15b2: 0000 unimp - 15b4: 0001 nop - 15b6: 0402 c.slli64 s0 - 15b8: 0301 addi t1,t1,0 - 15ba: 0900 addi s0,sp,144 - 15bc: 0014 0x14 - 15be: 0001 nop - 15c0: 0402 c.slli64 s0 - 15c2: 0301 addi t1,t1,0 - 15c4: 0900 addi s0,sp,144 - 15c6: 0004 0x4 - 15c8: 0001 nop - 15ca: 0402 c.slli64 s0 - 15cc: 0301 addi t1,t1,0 - 15ce: 0900 addi s0,sp,144 - 15d0: 0000 unimp - 15d2: 0001 nop - 15d4: 0402 c.slli64 s0 - 15d6: 0301 addi t1,t1,0 - 15d8: 0900 addi s0,sp,144 - 15da: 0004 0x4 - 15dc: 0001 nop - 15de: 0402 c.slli64 s0 - 15e0: 0301 addi t1,t1,0 - 15e2: 0900 addi s0,sp,144 - 15e4: 0000 unimp - 15e6: 0001 nop - 15e8: 0402 c.slli64 s0 - 15ea: 0329 addi t1,t1,10 - 15ec: 0900 addi s0,sp,144 - 15ee: 0000 unimp - 15f0: 0001 nop - 15f2: 0402 c.slli64 s0 - 15f4: 0329 addi t1,t1,10 - 15f6: 0900 addi s0,sp,144 - 15f8: 0000 unimp - 15fa: 0001 nop - 15fc: 0402 c.slli64 s0 - 15fe: 0308 addi a0,sp,384 - 1600: 0900 addi s0,sp,144 - 1602: 0004 0x4 - 1604: 0001 nop - 1606: 0402 c.slli64 s0 - 1608: 0308 addi a0,sp,384 - 160a: 0900 addi s0,sp,144 - 160c: 0000 unimp - 160e: 0001 nop - 1610: 0402 c.slli64 s0 - 1612: 0308 addi a0,sp,384 - 1614: 0901 addi s2,s2,0 - 1616: 0000 unimp - 1618: 0001 nop - 161a: 0402 c.slli64 s0 - 161c: 0308 addi a0,sp,384 - 161e: 0900 addi s0,sp,144 - 1620: 0000 unimp - 1622: 0001 nop - 1624: 0402 c.slli64 s0 - 1626: 0308 addi a0,sp,384 - 1628: 0900 addi s0,sp,144 - 162a: 0014 0x14 - 162c: 0001 nop - 162e: 0402 c.slli64 s0 - 1630: 0308 addi a0,sp,384 - 1632: 0900 addi s0,sp,144 - 1634: 0004 0x4 - 1636: 0001 nop - 1638: 0402 c.slli64 s0 - 163a: 0302 c.slli64 t1 - 163c: 097e slli s2,s2,0x1f - 163e: 001c 0x1c - 1640: 0001 nop - 1642: 0402 c.slli64 s0 - 1644: 030d addi t1,t1,3 - 1646: 0900 addi s0,sp,144 - 1648: 0008 0x8 - 164a: 0001 nop - 164c: 0402 c.slli64 s0 - 164e: 030d addi t1,t1,3 - 1650: 0900 addi s0,sp,144 - 1652: 0000 unimp - 1654: 0001 nop - 1656: 0402 c.slli64 s0 - 1658: 030d addi t1,t1,3 - 165a: 0900 addi s0,sp,144 - 165c: 0000 unimp - 165e: 0001 nop - 1660: 0402 c.slli64 s0 - 1662: 030d addi t1,t1,3 - 1664: 0900 addi s0,sp,144 - 1666: 0000 unimp - 1668: 0001 nop - 166a: 0402 c.slli64 s0 - 166c: 0311 addi t1,t1,4 - 166e: 0900 addi s0,sp,144 - 1670: 0004 0x4 - 1672: 0001 nop - 1674: 0402 c.slli64 s0 - 1676: 0311 addi t1,t1,4 - 1678: 0900 addi s0,sp,144 - 167a: 0000 unimp - 167c: 0001 nop - 167e: 0402 c.slli64 s0 - 1680: 0311 addi t1,t1,4 - 1682: 0900 addi s0,sp,144 - 1684: 0000 unimp - 1686: 0001 nop - 1688: 0402 c.slli64 s0 - 168a: 0311 addi t1,t1,4 - 168c: 0900 addi s0,sp,144 - 168e: 0000 unimp - 1690: 0001 nop - 1692: 0402 c.slli64 s0 - 1694: 0311 addi t1,t1,4 - 1696: 0900 addi s0,sp,144 - 1698: 0008 0x8 - 169a: 0001 nop - 169c: 0402 c.slli64 s0 - 169e: 031f 0900 0000 0x900031f - 16a4: 0001 nop - 16a6: 0402 c.slli64 s0 - 16a8: 031f 0900 0000 0x900031f - 16ae: 0001 nop - 16b0: 0402 c.slli64 s0 - 16b2: 031f 0900 0004 0x40900031f - 16b8: 0001 nop - 16ba: 0402 c.slli64 s0 - 16bc: 0320 addi s0,sp,392 - 16be: 0900 addi s0,sp,144 - 16c0: 0008 0x8 - 16c2: 0001 nop - 16c4: 0402 c.slli64 s0 - 16c6: 0320 addi s0,sp,392 - 16c8: 0900 addi s0,sp,144 - 16ca: 0008 0x8 - 16cc: 0001 nop - 16ce: 0402 c.slli64 s0 - 16d0: 0320 addi s0,sp,392 - 16d2: 0900 addi s0,sp,144 - 16d4: 0010 0x10 - 16d6: 0001 nop - 16d8: 0402 c.slli64 s0 - 16da: 0320 addi s0,sp,392 - 16dc: 0900 addi s0,sp,144 - 16de: 0004 0x4 - 16e0: 0001 nop - 16e2: 0402 c.slli64 s0 - 16e4: 0329 addi t1,t1,10 - 16e6: 0900 addi s0,sp,144 - 16e8: 0000 unimp - 16ea: 0001 nop - 16ec: 0402 c.slli64 s0 - 16ee: 0318 addi a4,sp,384 - 16f0: 0900 addi s0,sp,144 - 16f2: 000c 0xc - 16f4: 0001 nop - 16f6: 0402 c.slli64 s0 - 16f8: 0318 addi a4,sp,384 - 16fa: 0900 addi s0,sp,144 - 16fc: 0000 unimp - 16fe: 0001 nop - 1700: 0402 c.slli64 s0 - 1702: 0318 addi a4,sp,384 - 1704: 0900 addi s0,sp,144 - 1706: 0000 unimp - 1708: 0001 nop - 170a: 0402 c.slli64 s0 - 170c: 0318 addi a4,sp,384 - 170e: 0900 addi s0,sp,144 - 1710: 0000 unimp - 1712: 0001 nop - 1714: 0402 c.slli64 s0 - 1716: 0318 addi a4,sp,384 - 1718: 0900 addi s0,sp,144 - 171a: 0004 0x4 - 171c: 0001 nop - 171e: 0402 c.slli64 s0 - 1720: 0318 addi a4,sp,384 - 1722: 0900 addi s0,sp,144 - 1724: 0000 unimp - 1726: 0001 nop - 1728: 0402 c.slli64 s0 - 172a: 0321 addi t1,t1,8 - 172c: 0900 addi s0,sp,144 - 172e: 0008 0x8 - 1730: 0001 nop - 1732: 0402 c.slli64 s0 - 1734: 0321 addi t1,t1,8 - 1736: 0900 addi s0,sp,144 - 1738: 0008 0x8 - 173a: 0001 nop - 173c: 0402 c.slli64 s0 - 173e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 1742: 0008 0x8 - 1744: 0601 addi a2,a2,0 - 1746: 0c090003 lb zero,192(s2) - 174a: 0100 addi s0,sp,128 - 174c: 0200 addi s0,sp,256 - 174e: 0204 addi s1,sp,256 - 1750: 0306 slli t1,t1,0x1 - 1752: 0901 addi s2,s2,0 - 1754: 0030 addi a2,sp,8 - 1756: 0001 nop - 1758: 0402 c.slli64 s0 - 175a: 030d addi t1,t1,3 - 175c: 0900 addi s0,sp,144 - 175e: 0008 0x8 - 1760: 0001 nop - 1762: 0402 c.slli64 s0 - 1764: 030d addi t1,t1,3 - 1766: 0900 addi s0,sp,144 - 1768: 0000 unimp - 176a: 0001 nop - 176c: 0402 c.slli64 s0 - 176e: 030d addi t1,t1,3 - 1770: 0900 addi s0,sp,144 - 1772: 0000 unimp - 1774: 0001 nop - 1776: 0402 c.slli64 s0 - 1778: 030d addi t1,t1,3 - 177a: 0900 addi s0,sp,144 - 177c: 0000 unimp - 177e: 0001 nop - 1780: 0402 c.slli64 s0 - 1782: 0311 addi t1,t1,4 - 1784: 0900 addi s0,sp,144 - 1786: 0004 0x4 - 1788: 0001 nop - 178a: 0402 c.slli64 s0 - 178c: 0311 addi t1,t1,4 - 178e: 0900 addi s0,sp,144 - 1790: 0000 unimp - 1792: 0001 nop - 1794: 0402 c.slli64 s0 - 1796: 0311 addi t1,t1,4 - 1798: 0900 addi s0,sp,144 - 179a: 0000 unimp - 179c: 0001 nop - 179e: 0402 c.slli64 s0 - 17a0: 0311 addi t1,t1,4 - 17a2: 0900 addi s0,sp,144 - 17a4: 0000 unimp - 17a6: 0001 nop - 17a8: 0402 c.slli64 s0 - 17aa: 0311 addi t1,t1,4 - 17ac: 0900 addi s0,sp,144 - 17ae: 000c 0xc - 17b0: 0001 nop - 17b2: 0402 c.slli64 s0 - 17b4: 031f 0900 0000 0x900031f - 17ba: 0001 nop - 17bc: 0402 c.slli64 s0 - 17be: 031f 0900 0000 0x900031f - 17c4: 0001 nop - 17c6: 0402 c.slli64 s0 - 17c8: 031f 0900 0004 0x40900031f - 17ce: 0001 nop - 17d0: 0402 c.slli64 s0 - 17d2: 0320 addi s0,sp,392 - 17d4: 0900 addi s0,sp,144 - 17d6: 0008 0x8 - 17d8: 0001 nop - 17da: 0402 c.slli64 s0 - 17dc: 0320 addi s0,sp,392 - 17de: 0900 addi s0,sp,144 - 17e0: 0008 0x8 - 17e2: 0001 nop - 17e4: 0402 c.slli64 s0 - 17e6: 0320 addi s0,sp,392 - 17e8: 0900 addi s0,sp,144 - 17ea: 0010 0x10 - 17ec: 0001 nop - 17ee: 0402 c.slli64 s0 - 17f0: 0320 addi s0,sp,392 - 17f2: 0900 addi s0,sp,144 - 17f4: 0004 0x4 - 17f6: 0001 nop - 17f8: 0402 c.slli64 s0 - 17fa: 0329 addi t1,t1,10 - 17fc: 0900 addi s0,sp,144 - 17fe: 0000 unimp - 1800: 0001 nop - 1802: 0402 c.slli64 s0 - 1804: 0318 addi a4,sp,384 - 1806: 0900 addi s0,sp,144 - 1808: 000c 0xc - 180a: 0001 nop - 180c: 0402 c.slli64 s0 - 180e: 0318 addi a4,sp,384 - 1810: 0900 addi s0,sp,144 - 1812: 0000 unimp - 1814: 0001 nop - 1816: 0402 c.slli64 s0 - 1818: 0318 addi a4,sp,384 - 181a: 0900 addi s0,sp,144 - 181c: 0000 unimp - 181e: 0001 nop - 1820: 0402 c.slli64 s0 - 1822: 0318 addi a4,sp,384 - 1824: 0900 addi s0,sp,144 - 1826: 0000 unimp - 1828: 0001 nop - 182a: 0402 c.slli64 s0 - 182c: 0318 addi a4,sp,384 - 182e: 0900 addi s0,sp,144 - 1830: 0008 0x8 - 1832: 0001 nop - 1834: 0402 c.slli64 s0 - 1836: 0318 addi a4,sp,384 - 1838: 0900 addi s0,sp,144 - 183a: 0000 unimp - 183c: 0001 nop - 183e: 0402 c.slli64 s0 - 1840: 0321 addi t1,t1,8 - 1842: 0900 addi s0,sp,144 - 1844: 0008 0x8 - 1846: 0001 nop - 1848: 0402 c.slli64 s0 - 184a: 0321 addi t1,t1,8 - 184c: 0900 addi s0,sp,144 - 184e: 0008 0x8 - 1850: 0001 nop - 1852: 0402 c.slli64 s0 - 1854: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 1858: 0008 0x8 - 185a: 0601 addi a2,a2,0 - 185c: 08090003 lb zero,128(s2) - 1860: 0100 addi s0,sp,128 - 1862: 0200 addi s0,sp,256 - 1864: 0204 addi s1,sp,256 - 1866: 0306 slli t1,t1,0x1 - 1868: 0901 addi s2,s2,0 - 186a: 0030 addi a2,sp,8 - 186c: 0001 nop - 186e: 0402 c.slli64 s0 - 1870: 0302 c.slli64 t1 - 1872: 0900 addi s0,sp,144 - 1874: 0000 unimp - 1876: 0001 nop - 1878: 0402 c.slli64 s0 - 187a: 0302 c.slli64 t1 - 187c: 0900 addi s0,sp,144 - 187e: 0000 unimp - 1880: 0001 nop - 1882: 0402 c.slli64 s0 - 1884: 0302 c.slli64 t1 - 1886: 0900 addi s0,sp,144 - 1888: 0000 unimp - 188a: 0001 nop - 188c: 0402 c.slli64 s0 - 188e: 0302 c.slli64 t1 - 1890: 0900 addi s0,sp,144 - 1892: 0000 unimp - 1894: 0001 nop - 1896: 0402 c.slli64 s0 - 1898: 0302 c.slli64 t1 - 189a: 0900 addi s0,sp,144 - 189c: 0000 unimp - 189e: 0001 nop - 18a0: 0402 c.slli64 s0 - 18a2: 0302 c.slli64 t1 - 18a4: 0900 addi s0,sp,144 - 18a6: 0000 unimp - 18a8: 0001 nop - 18aa: 0402 c.slli64 s0 - 18ac: 0302 c.slli64 t1 - 18ae: 0900 addi s0,sp,144 - 18b0: 0000 unimp - 18b2: 0001 nop - 18b4: 0402 c.slli64 s0 - 18b6: 0302 c.slli64 t1 - 18b8: 0900 addi s0,sp,144 - 18ba: 0000 unimp - 18bc: 0001 nop - 18be: 0402 c.slli64 s0 - 18c0: 0302 c.slli64 t1 - 18c2: 0900 addi s0,sp,144 - 18c4: 0000 unimp - 18c6: 0001 nop - 18c8: 0402 c.slli64 s0 - 18ca: 0003060b 0x3060b - 18ce: 0409 addi s0,s0,2 - 18d0: 0100 addi s0,sp,128 - 18d2: 0200 addi s0,sp,256 - 18d4: 0c04 addi s1,sp,528 - 18d6: 04090003 lb zero,64(s2) - 18da: 0100 addi s0,sp,128 - 18dc: 0200 addi s0,sp,256 - 18de: 0e04 addi s1,sp,784 - 18e0: 0306 slli t1,t1,0x1 - 18e2: 0900 addi s0,sp,144 - 18e4: 0004 0x4 - 18e6: 0001 nop - 18e8: 0402 c.slli64 s0 - 18ea: 030e slli t1,t1,0x3 - 18ec: 0900 addi s0,sp,144 - 18ee: 0000 unimp - 18f0: 0001 nop - 18f2: 0402 c.slli64 s0 - 18f4: 030e slli t1,t1,0x3 - 18f6: 0900 addi s0,sp,144 - 18f8: 0008 0x8 - 18fa: 0001 nop - 18fc: 0402 c.slli64 s0 - 18fe: 09000313 li t1,144 - 1902: 000c 0xc - 1904: 0001 nop - 1906: 0402 c.slli64 s0 - 1908: 09000313 li t1,144 - 190c: 0000 unimp - 190e: 0001 nop - 1910: 0402 c.slli64 s0 - 1912: 09000313 li t1,144 - 1916: 0000 unimp - 1918: 0001 nop - 191a: 0402 c.slli64 s0 - 191c: 09000313 li t1,144 - 1920: 000c 0xc - 1922: 0001 nop - 1924: 0402 c.slli64 s0 - 1926: 09000313 li t1,144 - 192a: 0018 0x18 - 192c: 0001 nop - 192e: 0402 c.slli64 s0 - 1930: 09000313 li t1,144 - 1934: 0000 unimp - 1936: 0001 nop - 1938: 0402 c.slli64 s0 - 193a: 09000313 li t1,144 - 193e: 0000 unimp - 1940: 0001 nop - 1942: 0402 c.slli64 s0 - 1944: 09000313 li t1,144 - 1948: 0000 unimp - 194a: 0001 nop - 194c: 0402 c.slli64 s0 - 194e: 09000313 li t1,144 - 1952: 0000 unimp - 1954: 0001 nop - 1956: 0402 c.slli64 s0 - 1958: 09000313 li t1,144 - 195c: 0000 unimp - 195e: 0001 nop - 1960: 0402 c.slli64 s0 - 1962: 09000313 li t1,144 - 1966: 0000 unimp - 1968: 0001 nop - 196a: 0402 c.slli64 s0 - 196c: 09000313 li t1,144 - 1970: 0000 unimp - 1972: 0001 nop - 1974: 0402 c.slli64 s0 - 1976: 09000313 li t1,144 - 197a: 0000 unimp - 197c: 0001 nop - 197e: 0402 c.slli64 s0 - 1980: 09000313 li t1,144 - 1984: 000c 0xc - 1986: 0001 nop - 1988: 0402 c.slli64 s0 - 198a: 09000313 li t1,144 - 198e: 0008 0x8 - 1990: 0001 nop - 1992: 0402 c.slli64 s0 - 1994: 0316 slli t1,t1,0x5 - 1996: 0900 addi s0,sp,144 - 1998: 0004 0x4 - 199a: 0001 nop - 199c: 0402 c.slli64 s0 - 199e: 0316 slli t1,t1,0x5 - 19a0: 0900 addi s0,sp,144 - 19a2: 0008 0x8 - 19a4: 0001 nop - 19a6: 0402 c.slli64 s0 - 19a8: 0318 addi a4,sp,384 - 19aa: 0900 addi s0,sp,144 - 19ac: 0004 0x4 - 19ae: 0001 nop - 19b0: 0402 c.slli64 s0 - 19b2: 031a slli t1,t1,0x6 - 19b4: 0900 addi s0,sp,144 - 19b6: 0004 0x4 - 19b8: 0001 nop - 19ba: 0402 c.slli64 s0 - 19bc: 031c addi a5,sp,384 - 19be: 0900 addi s0,sp,144 - 19c0: 0008 0x8 - 19c2: 0001 nop - 19c4: 0402 c.slli64 s0 - 19c6: 031c addi a5,sp,384 - 19c8: 0900 addi s0,sp,144 - 19ca: 0004 0x4 - 19cc: 0001 nop - 19ce: 0402 c.slli64 s0 - 19d0: 031c addi a5,sp,384 - 19d2: 0900 addi s0,sp,144 - 19d4: 0000 unimp - 19d6: 0001 nop - 19d8: 0402 c.slli64 s0 - 19da: 031c addi a5,sp,384 - 19dc: 0900 addi s0,sp,144 - 19de: 0004 0x4 - 19e0: 0001 nop - 19e2: 0402 c.slli64 s0 - 19e4: 031c addi a5,sp,384 - 19e6: 0900 addi s0,sp,144 - 19e8: 0014 0x14 - 19ea: 0001 nop - 19ec: 0402 c.slli64 s0 - 19ee: 031c addi a5,sp,384 - 19f0: 0900 addi s0,sp,144 - 19f2: 0008 0x8 - 19f4: 0001 nop - 19f6: 0402 c.slli64 s0 - 19f8: 031d addi t1,t1,7 - 19fa: 0900 addi s0,sp,144 - 19fc: 0004 0x4 - 19fe: 0001 nop - 1a00: 0402 c.slli64 s0 - 1a02: 031d addi t1,t1,7 - 1a04: 0900 addi s0,sp,144 - 1a06: 0008 0x8 - 1a08: 0001 nop - 1a0a: 0402 c.slli64 s0 - 1a0c: 031f 0900 0004 0x40900031f - 1a12: 0001 nop - 1a14: 0402 c.slli64 s0 - 1a16: 0321 addi t1,t1,8 - 1a18: 0900 addi s0,sp,144 - 1a1a: 0004 0x4 - 1a1c: 0001 nop - 1a1e: 0402 c.slli64 s0 - 1a20: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a24: 0008 0x8 - 1a26: 0001 nop - 1a28: 0402 c.slli64 s0 - 1a2a: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a2e: 0004 0x4 - 1a30: 0001 nop - 1a32: 0402 c.slli64 s0 - 1a34: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a38: 000c 0xc - 1a3a: 0001 nop - 1a3c: 0402 c.slli64 s0 - 1a3e: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a42: 0000 unimp - 1a44: 0001 nop - 1a46: 0402 c.slli64 s0 - 1a48: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a4c: 0000 unimp - 1a4e: 0001 nop - 1a50: 0402 c.slli64 s0 - 1a52: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a56: 0000 unimp - 1a58: 0001 nop - 1a5a: 0402 c.slli64 s0 - 1a5c: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a60: 0000 unimp - 1a62: 0001 nop - 1a64: 0402 c.slli64 s0 - 1a66: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a6a: 0000 unimp - 1a6c: 0001 nop - 1a6e: 0402 c.slli64 s0 - 1a70: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a74: 0000 unimp - 1a76: 0001 nop - 1a78: 0402 c.slli64 s0 - 1a7a: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a7e: 0008 0x8 - 1a80: 0001 nop - 1a82: 0402 c.slli64 s0 - 1a84: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a88: 0000 unimp - 1a8a: 0001 nop - 1a8c: 0402 c.slli64 s0 - 1a8e: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a92: 0008 0x8 - 1a94: 0001 nop - 1a96: 0402 c.slli64 s0 - 1a98: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1a9c: 0008 0x8 - 1a9e: 0001 nop - 1aa0: 0402 c.slli64 s0 - 1aa2: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1aa6: 0000 unimp - 1aa8: 0001 nop - 1aaa: 0402 c.slli64 s0 - 1aac: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1ab0: 0004 0x4 - 1ab2: 0001 nop - 1ab4: 0402 c.slli64 s0 - 1ab6: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1aba: 0008 0x8 - 1abc: 0001 nop - 1abe: 0402 c.slli64 s0 - 1ac0: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1ac4: 0004 0x4 - 1ac6: 0001 nop - 1ac8: 0402 c.slli64 s0 - 1aca: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 1ace: 0008 0x8 - 1ad0: 0001 nop - 1ad2: 0402 c.slli64 s0 - 1ad4: 0324 addi s1,sp,392 - 1ad6: 0900 addi s0,sp,144 - 1ad8: 0004 0x4 - 1ada: 0001 nop - 1adc: 0402 c.slli64 s0 - 1ade: 0326 slli t1,t1,0x9 - 1ae0: 0900 addi s0,sp,144 - 1ae2: 0004 0x4 - 1ae4: 0001 nop - 1ae6: 0402 c.slli64 s0 - 1ae8: 0326 slli t1,t1,0x9 - 1aea: 0900 addi s0,sp,144 - 1aec: 0008 0x8 - 1aee: 0001 nop - 1af0: 0402 c.slli64 s0 - 1af2: 0326 slli t1,t1,0x9 - 1af4: 0900 addi s0,sp,144 - 1af6: 0018 0x18 - 1af8: 0001 nop - 1afa: 0402 c.slli64 s0 - 1afc: 0326 slli t1,t1,0x9 - 1afe: 0900 addi s0,sp,144 - 1b00: 0000 unimp - 1b02: 0001 nop - 1b04: 0402 c.slli64 s0 - 1b06: 0326 slli t1,t1,0x9 - 1b08: 0900 addi s0,sp,144 - 1b0a: 0000 unimp - 1b0c: 0001 nop - 1b0e: 0402 c.slli64 s0 - 1b10: 0628 addi a0,sp,776 - 1b12: 04090003 lb zero,64(s2) - 1b16: 0100 addi s0,sp,128 - 1b18: 0200 addi s0,sp,256 - 1b1a: 2904 fld fs1,16(a0) - 1b1c: 08090003 lb zero,128(s2) - 1b20: 0100 addi s0,sp,128 - 1b22: 0200 addi s0,sp,256 - 1b24: 2b04 fld fs1,16(a4) - 1b26: 0306 slli t1,t1,0x1 - 1b28: 0900 addi s0,sp,144 - 1b2a: 0004 0x4 - 1b2c: 0001 nop - 1b2e: 0402 c.slli64 s0 - 1b30: 0900032b 0x900032b - 1b34: 0014 0x14 - 1b36: 0001 nop - 1b38: 0402 c.slli64 s0 - 1b3a: 0900032b 0x900032b - 1b3e: 0000 unimp - 1b40: 0001 nop - 1b42: 0402 c.slli64 s0 - 1b44: 0900032b 0x900032b - 1b48: 0000 unimp - 1b4a: 0001 nop - 1b4c: 0402 c.slli64 s0 - 1b4e: 0900032b 0x900032b - 1b52: 0000 unimp - 1b54: 0001 nop - 1b56: 0402 c.slli64 s0 - 1b58: 0900032b 0x900032b - 1b5c: 0000 unimp - 1b5e: 0001 nop - 1b60: 0402 c.slli64 s0 - 1b62: 0900032b 0x900032b - 1b66: 0000 unimp - 1b68: 0001 nop - 1b6a: 0402 c.slli64 s0 - 1b6c: 0900032b 0x900032b - 1b70: 0000 unimp - 1b72: 0001 nop - 1b74: 0402 c.slli64 s0 - 1b76: 062e slli a2,a2,0xb - 1b78: 04090003 lb zero,64(s2) - 1b7c: 0100 addi s0,sp,128 - 1b7e: 0200 addi s0,sp,256 - 1b80: 2f04 fld fs1,24(a4) - 1b82: 04090003 lb zero,64(s2) - 1b86: 0100 addi s0,sp,128 - 1b88: 0200 addi s0,sp,256 - 1b8a: 3104 fld fs1,32(a0) - 1b8c: 04090003 lb zero,64(s2) - 1b90: 0100 addi s0,sp,128 - 1b92: 0200 addi s0,sp,256 - 1b94: 3404 fld fs1,40(s0) - 1b96: 04090003 lb zero,64(s2) - 1b9a: 0100 addi s0,sp,128 - 1b9c: 0200 addi s0,sp,256 - 1b9e: 3504 fld fs1,40(a0) - 1ba0: 04090003 lb zero,64(s2) - 1ba4: 0100 addi s0,sp,128 - 1ba6: 0200 addi s0,sp,256 - 1ba8: 3704 fld fs1,40(a4) - 1baa: 0306 slli t1,t1,0x1 - 1bac: 0900 addi s0,sp,144 - 1bae: 0004 0x4 - 1bb0: 0001 nop - 1bb2: 0402 c.slli64 s0 - 1bb4: 09000337 lui t1,0x9000 - 1bb8: 0010 0x10 - 1bba: 0001 nop - 1bbc: 0402 c.slli64 s0 - 1bbe: 09000337 lui t1,0x9000 - 1bc2: 0000 unimp - 1bc4: 0001 nop - 1bc6: 0402 c.slli64 s0 - 1bc8: 09000337 lui t1,0x9000 - 1bcc: 0000 unimp - 1bce: 0001 nop - 1bd0: 0402 c.slli64 s0 - 1bd2: 09000337 lui t1,0x9000 - 1bd6: 0000 unimp - 1bd8: 0001 nop - 1bda: 0402 c.slli64 s0 - 1bdc: 09000337 lui t1,0x9000 - 1be0: 0004 0x4 - 1be2: 0001 nop - 1be4: 0402 c.slli64 s0 - 1be6: 0339 addi t1,t1,14 - 1be8: 0900 addi s0,sp,144 - 1bea: 0000 unimp - 1bec: 0001 nop - 1bee: 0402 c.slli64 s0 - 1bf0: 0339 addi t1,t1,14 - 1bf2: 0900 addi s0,sp,144 - 1bf4: 0000 unimp - 1bf6: 0001 nop - 1bf8: 0402 c.slli64 s0 - 1bfa: 0339 addi t1,t1,14 - 1bfc: 0900 addi s0,sp,144 - 1bfe: 0000 unimp - 1c00: 0001 nop - 1c02: 0402 c.slli64 s0 - 1c04: 0339 addi t1,t1,14 - 1c06: 0900 addi s0,sp,144 - 1c08: 0000 unimp - 1c0a: 0001 nop - 1c0c: 0402 c.slli64 s0 - 1c0e: 0339 addi t1,t1,14 - 1c10: 0900 addi s0,sp,144 - 1c12: 0004 0x4 - 1c14: 0001 nop - 1c16: 0402 c.slli64 s0 - 1c18: 0339 addi t1,t1,14 - 1c1a: 0900 addi s0,sp,144 - 1c1c: 000c 0xc - 1c1e: 0001 nop - 1c20: 0402 c.slli64 s0 - 1c22: 0339 addi t1,t1,14 - 1c24: 0900 addi s0,sp,144 - 1c26: 0000 unimp - 1c28: 0001 nop - 1c2a: 0402 c.slli64 s0 - 1c2c: 0339 addi t1,t1,14 - 1c2e: 0900 addi s0,sp,144 - 1c30: 0000 unimp - 1c32: 0001 nop - 1c34: 0402 c.slli64 s0 - 1c36: 0900033b 0x900033b - 1c3a: 0008 0x8 - 1c3c: 0001 nop - 1c3e: 0402 c.slli64 s0 - 1c40: 0900033b 0x900033b - 1c44: 0000 unimp - 1c46: 0001 nop - 1c48: 0402 c.slli64 s0 - 1c4a: 0900033b 0x900033b - 1c4e: 0000 unimp - 1c50: 0001 nop - 1c52: 0402 c.slli64 s0 - 1c54: 0900033b 0x900033b - 1c58: 0000 unimp - 1c5a: 0001 nop - 1c5c: 0402 c.slli64 s0 - 1c5e: 0900033b 0x900033b - 1c62: 0000 unimp - 1c64: 0001 nop - 1c66: 0402 c.slli64 s0 - 1c68: 0900033b 0x900033b - 1c6c: 0000 unimp - 1c6e: 0001 nop - 1c70: 0402 c.slli64 s0 - 1c72: 0900033b 0x900033b - 1c76: 0000 unimp - 1c78: 0001 nop - 1c7a: 0402 c.slli64 s0 - 1c7c: 0900033b 0x900033b - 1c80: 0004 0x4 - 1c82: 0001 nop - 1c84: 0402 c.slli64 s0 - 1c86: 0900033b 0x900033b - 1c8a: 0010 0x10 - 1c8c: 0001 nop - 1c8e: 0402 c.slli64 s0 - 1c90: 0900033b 0x900033b - 1c94: 0008 0x8 - 1c96: 0001 nop - 1c98: 0402 c.slli64 s0 - 1c9a: 033d addi t1,t1,15 - 1c9c: 0900 addi s0,sp,144 - 1c9e: 0004 0x4 - 1ca0: 0001 nop - 1ca2: 0402 c.slli64 s0 - 1ca4: 033d addi t1,t1,15 - 1ca6: 0900 addi s0,sp,144 - 1ca8: 0008 0x8 - 1caa: 0001 nop - 1cac: 0402 c.slli64 s0 - 1cae: 0900033f 00010004 0x100040900033f - 1cb6: 0402 c.slli64 s0 - 1cb8: 0341 addi t1,t1,16 - 1cba: 0900 addi s0,sp,144 - 1cbc: 0004 0x4 - 1cbe: 0001 nop - 1cc0: 0402 c.slli64 s0 - 1cc2: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1cc6: 0008 0x8 - 1cc8: 0001 nop - 1cca: 0402 c.slli64 s0 - 1ccc: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1cd0: 0004 0x4 - 1cd2: 0001 nop - 1cd4: 0402 c.slli64 s0 - 1cd6: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1cda: 0000 unimp - 1cdc: 0001 nop - 1cde: 0402 c.slli64 s0 - 1ce0: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1ce4: 0004 0x4 - 1ce6: 0001 nop - 1ce8: 0402 c.slli64 s0 - 1cea: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1cee: 0014 0x14 - 1cf0: 0001 nop - 1cf2: 0402 c.slli64 s0 - 1cf4: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne - 1cf8: 0008 0x8 - 1cfa: 0001 nop - 1cfc: 0402 c.slli64 s0 - 1cfe: 0344 addi s1,sp,388 - 1d00: 0900 addi s0,sp,144 - 1d02: 0004 0x4 - 1d04: 0001 nop - 1d06: 0402 c.slli64 s0 - 1d08: 0344 addi s1,sp,388 - 1d0a: 0900 addi s0,sp,144 - 1d0c: 0008 0x8 - 1d0e: 0001 nop - 1d10: 0402 c.slli64 s0 - 1d12: 0346 slli t1,t1,0x11 - 1d14: 0900 addi s0,sp,144 - 1d16: 0004 0x4 - 1d18: 0001 nop - 1d1a: 0402 c.slli64 s0 - 1d1c: 0348 addi a0,sp,388 - 1d1e: 0900 addi s0,sp,144 - 1d20: 0004 0x4 - 1d22: 0001 nop - 1d24: 0402 c.slli64 s0 - 1d26: 034a slli t1,t1,0x12 - 1d28: 0900 addi s0,sp,144 - 1d2a: 0008 0x8 - 1d2c: 0001 nop - 1d2e: 0402 c.slli64 s0 - 1d30: 034a slli t1,t1,0x12 - 1d32: 0900 addi s0,sp,144 - 1d34: 001c 0x1c - 1d36: 0001 nop - 1d38: 0402 c.slli64 s0 - 1d3a: 034a slli t1,t1,0x12 - 1d3c: 0900 addi s0,sp,144 - 1d3e: 0000 unimp - 1d40: 0001 nop - 1d42: 0402 c.slli64 s0 - 1d44: 034a slli t1,t1,0x12 - 1d46: 0900 addi s0,sp,144 - 1d48: 0000 unimp - 1d4a: 0001 nop - 1d4c: 0402 c.slli64 s0 - 1d4e: 034a slli t1,t1,0x12 - 1d50: 0900 addi s0,sp,144 - 1d52: 0000 unimp - 1d54: 0001 nop - 1d56: 0402 c.slli64 s0 - 1d58: 034a slli t1,t1,0x12 - 1d5a: 0900 addi s0,sp,144 - 1d5c: 0000 unimp - 1d5e: 0001 nop - 1d60: 0402 c.slli64 s0 - 1d62: 034a slli t1,t1,0x12 - 1d64: 0900 addi s0,sp,144 - 1d66: 0000 unimp - 1d68: 0001 nop - 1d6a: 0402 c.slli64 s0 - 1d6c: 034a slli t1,t1,0x12 - 1d6e: 0900 addi s0,sp,144 - 1d70: 0000 unimp - 1d72: 0001 nop - 1d74: 0402 c.slli64 s0 - 1d76: 034a slli t1,t1,0x12 - 1d78: 0900 addi s0,sp,144 - 1d7a: 0000 unimp - 1d7c: 0001 nop - 1d7e: 0402 c.slli64 s0 - 1d80: 034a slli t1,t1,0x12 - 1d82: 0900 addi s0,sp,144 - 1d84: 0000 unimp - 1d86: 0001 nop - 1d88: 0402 c.slli64 s0 - 1d8a: 034a slli t1,t1,0x12 - 1d8c: 0900 addi s0,sp,144 - 1d8e: 0000 unimp - 1d90: 0001 nop - 1d92: 0402 c.slli64 s0 - 1d94: 034a slli t1,t1,0x12 - 1d96: 0900 addi s0,sp,144 - 1d98: 0000 unimp - 1d9a: 0001 nop - 1d9c: 0402 c.slli64 s0 - 1d9e: 034a slli t1,t1,0x12 - 1da0: 0900 addi s0,sp,144 - 1da2: 0008 0x8 - 1da4: 0001 nop - 1da6: 0402 c.slli64 s0 - 1da8: 034a slli t1,t1,0x12 - 1daa: 0900 addi s0,sp,144 - 1dac: 0000 unimp - 1dae: 0001 nop - 1db0: 0402 c.slli64 s0 - 1db2: 034a slli t1,t1,0x12 - 1db4: 0900 addi s0,sp,144 - 1db6: 0004 0x4 - 1db8: 0001 nop - 1dba: 0402 c.slli64 s0 - 1dbc: 034a slli t1,t1,0x12 - 1dbe: 0900 addi s0,sp,144 - 1dc0: 0000 unimp - 1dc2: 0001 nop - 1dc4: 0402 c.slli64 s0 - 1dc6: 034a slli t1,t1,0x12 - 1dc8: 0900 addi s0,sp,144 - 1dca: 0008 0x8 - 1dcc: 0001 nop - 1dce: 0402 c.slli64 s0 - 1dd0: 034a slli t1,t1,0x12 - 1dd2: 0900 addi s0,sp,144 - 1dd4: 0004 0x4 - 1dd6: 0001 nop - 1dd8: 0402 c.slli64 s0 - 1dda: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne - 1dde: 0004 0x4 - 1de0: 0001 nop - 1de2: 0402 c.slli64 s0 - 1de4: 034d addi t1,t1,19 - 1de6: 0900 addi s0,sp,144 - 1de8: 0008 0x8 - 1dea: 0001 nop - 1dec: 0402 c.slli64 s0 - 1dee: 034d addi t1,t1,19 - 1df0: 0900 addi s0,sp,144 - 1df2: 0008 0x8 - 1df4: 0001 nop - 1df6: 0402 c.slli64 s0 - 1df8: 034d addi t1,t1,19 - 1dfa: 0900 addi s0,sp,144 - 1dfc: 0018 0x18 - 1dfe: 0001 nop - 1e00: 0402 c.slli64 s0 - 1e02: 034d addi t1,t1,19 - 1e04: 0900 addi s0,sp,144 - 1e06: 0000 unimp - 1e08: 0001 nop - 1e0a: 0402 c.slli64 s0 - 1e0c: 034d addi t1,t1,19 - 1e0e: 0900 addi s0,sp,144 - 1e10: 0000 unimp - 1e12: 0001 nop - 1e14: 0402 c.slli64 s0 - 1e16: 0003064f fnmadd.s fa2,ft6,ft0,ft0,rne - 1e1a: 0409 addi s0,s0,2 - 1e1c: 0100 addi s0,sp,128 - 1e1e: 0200 addi s0,sp,256 - 1e20: 5004 lw s1,32(s0) - 1e22: 04090003 lb zero,64(s2) - 1e26: 0100 addi s0,sp,128 - 1e28: 0200 addi s0,sp,256 - 1e2a: 5204 lw s1,32(a2) - 1e2c: 0306 slli t1,t1,0x1 - 1e2e: 0900 addi s0,sp,144 - 1e30: 0008 0x8 - 1e32: 0001 nop - 1e34: 0402 c.slli64 s0 - 1e36: 0352 slli t1,t1,0x14 - 1e38: 0900 addi s0,sp,144 - 1e3a: 0008 0x8 - 1e3c: 0001 nop - 1e3e: 0402 c.slli64 s0 - 1e40: 0352 slli t1,t1,0x14 - 1e42: 0900 addi s0,sp,144 - 1e44: 0000 unimp - 1e46: 0001 nop - 1e48: 0402 c.slli64 s0 - 1e4a: 0352 slli t1,t1,0x14 - 1e4c: 0900 addi s0,sp,144 - 1e4e: 0000 unimp - 1e50: 0001 nop - 1e52: 0402 c.slli64 s0 - 1e54: 0352 slli t1,t1,0x14 - 1e56: 0900 addi s0,sp,144 - 1e58: 0000 unimp - 1e5a: 0001 nop - 1e5c: 0402 c.slli64 s0 - 1e5e: 0352 slli t1,t1,0x14 - 1e60: 0900 addi s0,sp,144 - 1e62: 0000 unimp - 1e64: 0001 nop - 1e66: 0402 c.slli64 s0 - 1e68: 0352 slli t1,t1,0x14 - 1e6a: 0900 addi s0,sp,144 - 1e6c: 0000 unimp - 1e6e: 0001 nop - 1e70: 0402 c.slli64 s0 - 1e72: 0352 slli t1,t1,0x14 - 1e74: 0900 addi s0,sp,144 - 1e76: 0000 unimp - 1e78: 0001 nop - 1e7a: 0402 c.slli64 s0 - 1e7c: 0658 addi a4,sp,772 - 1e7e: 04090003 lb zero,64(s2) - 1e82: 0100 addi s0,sp,128 - 1e84: 0200 addi s0,sp,256 - 1e86: 5b04 lw s1,48(a4) - 1e88: 04090003 lb zero,64(s2) - 1e8c: 0100 addi s0,sp,128 - 1e8e: 0200 addi s0,sp,256 - 1e90: 5c04 lw s1,56(s0) - 1e92: 04090003 lb zero,64(s2) - 1e96: 0100 addi s0,sp,128 - 1e98: 0200 addi s0,sp,256 - 1e9a: 5e04 lw s1,56(a2) - 1e9c: 0306 slli t1,t1,0x1 - 1e9e: 0900 addi s0,sp,144 - 1ea0: 0004 0x4 - 1ea2: 0001 nop - 1ea4: 0402 c.slli64 s0 - 1ea6: 035e slli t1,t1,0x17 - 1ea8: 0900 addi s0,sp,144 - 1eaa: 0010 0x10 - 1eac: 0001 nop - 1eae: 0402 c.slli64 s0 - 1eb0: 035e slli t1,t1,0x17 - 1eb2: 0900 addi s0,sp,144 - 1eb4: 0000 unimp - 1eb6: 0001 nop - 1eb8: 0402 c.slli64 s0 - 1eba: 035e slli t1,t1,0x17 - 1ebc: 0900 addi s0,sp,144 - 1ebe: 0000 unimp - 1ec0: 0001 nop - 1ec2: 0402 c.slli64 s0 - 1ec4: 035e slli t1,t1,0x17 - 1ec6: 0900 addi s0,sp,144 - 1ec8: 0000 unimp - 1eca: 0001 nop - 1ecc: 0402 c.slli64 s0 - 1ece: 035e slli t1,t1,0x17 - 1ed0: 0900 addi s0,sp,144 - 1ed2: 0004 0x4 - 1ed4: 0001 nop - 1ed6: 0402 c.slli64 s0 - 1ed8: 0360 addi s0,sp,396 - 1eda: 0900 addi s0,sp,144 - 1edc: 0004 0x4 - 1ede: 0001 nop - 1ee0: 0402 c.slli64 s0 - 1ee2: 0360 addi s0,sp,396 - 1ee4: 0900 addi s0,sp,144 - 1ee6: 0000 unimp - 1ee8: 0001 nop - 1eea: 0402 c.slli64 s0 - 1eec: 0662 slli a2,a2,0x18 - 1eee: 04090003 lb zero,64(s2) - 1ef2: 0100 addi s0,sp,128 - 1ef4: 0200 addi s0,sp,256 - 1ef6: 6304 flw fs1,0(a4) - 1ef8: 0306 slli t1,t1,0x1 - 1efa: 0900 addi s0,sp,144 - 1efc: 0004 0x4 - 1efe: 0001 nop - 1f00: 0402 c.slli64 s0 - 1f02: 0302 c.slli64 t1 - 1f04: 0901 addi s2,s2,0 - 1f06: 0004 0x4 - 1f08: 0001 nop - 1f0a: 0402 c.slli64 s0 - 1f0c: 0302 c.slli64 t1 - 1f0e: 0900 addi s0,sp,144 - 1f10: 0004 0x4 - 1f12: 0001 nop - 1f14: 0402 c.slli64 s0 - 1f16: 0306 slli t1,t1,0x1 - 1f18: 0900 addi s0,sp,144 - 1f1a: 0004 0x4 - 1f1c: 0001 nop - 1f1e: 0402 c.slli64 s0 - 1f20: 0306 slli t1,t1,0x1 - 1f22: 0900 addi s0,sp,144 - 1f24: 0000 unimp - 1f26: 0001 nop - 1f28: 0402 c.slli64 s0 - 1f2a: 0308 addi a0,sp,384 - 1f2c: 0900 addi s0,sp,144 - 1f2e: 0008 0x8 - 1f30: 0001 nop - 1f32: 0402 c.slli64 s0 - 1f34: 0308 addi a0,sp,384 - 1f36: 0900 addi s0,sp,144 - 1f38: 0000 unimp - 1f3a: 0001 nop - 1f3c: 0402 c.slli64 s0 - 1f3e: 0308 addi a0,sp,384 - 1f40: 0900 addi s0,sp,144 - 1f42: 0000 unimp - 1f44: 0001 nop - 1f46: 0402 c.slli64 s0 - 1f48: 0308 addi a0,sp,384 - 1f4a: 0900 addi s0,sp,144 - 1f4c: 0000 unimp - 1f4e: 0001 nop - 1f50: 0402 c.slli64 s0 - 1f52: 030a slli t1,t1,0x2 - 1f54: 0900 addi s0,sp,144 - 1f56: 000c 0xc - 1f58: 0001 nop - 1f5a: 0402 c.slli64 s0 - 1f5c: 030a slli t1,t1,0x2 - 1f5e: 0900 addi s0,sp,144 - 1f60: 0000 unimp - 1f62: 0001 nop - 1f64: 0402 c.slli64 s0 - 1f66: 030a slli t1,t1,0x2 - 1f68: 0900 addi s0,sp,144 - 1f6a: 0000 unimp - 1f6c: 0001 nop - 1f6e: 0402 c.slli64 s0 - 1f70: 030a slli t1,t1,0x2 - 1f72: 0900 addi s0,sp,144 - 1f74: 0004 0x4 - 1f76: 0001 nop - 1f78: 0402 c.slli64 s0 - 1f7a: 030a slli t1,t1,0x2 - 1f7c: 0900 addi s0,sp,144 - 1f7e: 0008 0x8 - 1f80: 0001 nop - 1f82: 0402 c.slli64 s0 - 1f84: 0309 addi t1,t1,2 - 1f86: 0900 addi s0,sp,144 - 1f88: 0004 0x4 - 1f8a: 0001 nop - 1f8c: 0402 c.slli64 s0 - 1f8e: 0309 addi t1,t1,2 - 1f90: 0900 addi s0,sp,144 - 1f92: 0000 unimp - 1f94: 0001 nop - 1f96: 0402 c.slli64 s0 - 1f98: 0318 addi a4,sp,384 - 1f9a: 0900 addi s0,sp,144 - 1f9c: 0008 0x8 - 1f9e: 0001 nop - 1fa0: 0402 c.slli64 s0 - 1fa2: 0318 addi a4,sp,384 - 1fa4: 0900 addi s0,sp,144 - 1fa6: 000c 0xc - 1fa8: 0001 nop - 1faa: 0402 c.slli64 s0 - 1fac: 031a slli t1,t1,0x6 - 1fae: 0900 addi s0,sp,144 - 1fb0: 0004 0x4 - 1fb2: 0001 nop - 1fb4: 0402 c.slli64 s0 - 1fb6: 031a slli t1,t1,0x6 - 1fb8: 0900 addi s0,sp,144 - 1fba: 0000 unimp - 1fbc: 0001 nop - 1fbe: 0402 c.slli64 s0 - 1fc0: 031a slli t1,t1,0x6 - 1fc2: 0900 addi s0,sp,144 - 1fc4: 0000 unimp - 1fc6: 0001 nop - 1fc8: 0402 c.slli64 s0 - 1fca: 031a slli t1,t1,0x6 - 1fcc: 0900 addi s0,sp,144 - 1fce: 0000 unimp - 1fd0: 0601 addi a2,a2,0 - 1fd2: 08090003 lb zero,128(s2) - 1fd6: 0100 addi s0,sp,128 - 1fd8: 0200 addi s0,sp,256 - 1fda: 7704 flw fs1,40(a4) - 1fdc: 0306 slli t1,t1,0x1 - 1fde: 0900 addi s0,sp,144 - 1fe0: 0010 0x10 - 1fe2: 0001 nop - 1fe4: 0402 c.slli64 s0 - 1fe6: 09000377 0x9000377 - 1fea: 0000 unimp - 1fec: 0001 nop - 1fee: 0402 c.slli64 s0 - 1ff0: 09000377 0x9000377 - 1ff4: 0000 unimp - 1ff6: 0001 nop - 1ff8: 0402 c.slli64 s0 - 1ffa: 09000377 0x9000377 - 1ffe: 0000 unimp - 2000: 0001 nop - 2002: 0402 c.slli64 s0 - 2004: 09000377 0x9000377 - 2008: 0000 unimp - 200a: 0001 nop - 200c: 0402 c.slli64 s0 - 200e: 09000377 0x9000377 - 2012: 0000 unimp - 2014: 0001 nop - 2016: 0402 c.slli64 s0 - 2018: 09000377 0x9000377 - 201c: 0000 unimp - 201e: 0001 nop - 2020: 0402 c.slli64 s0 - 2022: 09000377 0x9000377 - 2026: 0000 unimp - 2028: 0501 addi a0,a0,0 - 202a: 0001 nop - 202c: 0402 c.slli64 s0 - 202e: 04030677 0x4030677 - 2032: 0c09 addi s8,s8,2 - 2034: 0100 addi s0,sp,128 - 2036: 0305 addi t1,t1,1 - 2038: 0200 addi s0,sp,256 - 203a: 7704 flw fs1,40(a4) - 203c: 08097c03 0x8097c03 - 2040: 0100 addi s0,sp,128 - 2042: 0200 addi s0,sp,256 - 2044: 7704 flw fs1,40(a4) - 2046: 0306 slli t1,t1,0x1 - 2048: 0900 addi s0,sp,144 - 204a: 0014 0x14 - 204c: 0001 nop - 204e: 0402 c.slli64 s0 - 2050: 09000377 0x9000377 - 2054: 0000 unimp - 2056: 0001 nop - 2058: 0402 c.slli64 s0 - 205a: 09010377 0x9010377 - 205e: 0000 unimp - 2060: 0001 nop - 2062: 0402 c.slli64 s0 - 2064: 09000377 0x9000377 - 2068: 0000 unimp - 206a: 0001 nop - 206c: 0402 c.slli64 s0 - 206e: 09000377 0x9000377 - 2072: 0000 unimp - 2074: 0001 nop - 2076: 0402 c.slli64 s0 - 2078: 09020377 0x9020377 - 207c: 0000 unimp - 207e: 0501 addi a0,a0,0 - 2080: 0001 nop - 2082: 0402 c.slli64 s0 - 2084: 01030677 0x1030677 - 2088: 0009 c.nop 2 - 208a: 0100 addi s0,sp,128 - 208c: 0305 addi t1,t1,1 - 208e: 0200 addi s0,sp,256 - 2090: 0f04 addi s1,sp,912 - 2092: 0306 slli t1,t1,0x1 - 2094: 0030097b 0x30097b - 2098: 0001 nop - 209a: 0402 c.slli64 s0 - 209c: 0900030f 0x900030f - 20a0: 0004 0x4 - 20a2: 0001 nop - 20a4: 0402 c.slli64 s0 - 20a6: 0900030f 0x900030f - 20aa: 0000 unimp - 20ac: 0001 nop - 20ae: 0402 c.slli64 s0 - 20b0: 0900030f 0x900030f - 20b4: 0000 unimp - 20b6: 0001 nop - 20b8: 0402 c.slli64 s0 - 20ba: 0608 addi a0,sp,768 - 20bc: 08097e03 0x8097e03 - 20c0: 0100 addi s0,sp,128 - 20c2: 0200 addi s0,sp,256 - 20c4: 0804 addi s1,sp,16 - 20c6: 0306 slli t1,t1,0x1 - 20c8: 0902 c.slli64 s2 - 20ca: 0004 0x4 - 20cc: 0001 nop - 20ce: 0402 c.slli64 s0 - 20d0: 0308 addi a0,sp,384 - 20d2: 0900 addi s0,sp,144 - 20d4: 0000 unimp - 20d6: 0001 nop - 20d8: 0402 c.slli64 s0 - 20da: 0308 addi a0,sp,384 - 20dc: 0900 addi s0,sp,144 - 20de: 0000 unimp - 20e0: 0001 nop - 20e2: 0402 c.slli64 s0 - 20e4: 0308 addi a0,sp,384 - 20e6: 0900 addi s0,sp,144 - 20e8: 0000 unimp - 20ea: 0001 nop - 20ec: 0402 c.slli64 s0 - 20ee: 036c addi a1,sp,396 - 20f0: 0900 addi s0,sp,144 - 20f2: 000c 0xc - 20f4: 0001 nop - 20f6: 0402 c.slli64 s0 - 20f8: 036c addi a1,sp,396 - 20fa: 0901 addi s2,s2,0 - 20fc: 0000 unimp - 20fe: 0001 nop - 2100: 0402 c.slli64 s0 - 2102: 036c addi a1,sp,396 - 2104: 0900 addi s0,sp,144 - 2106: 0000 unimp - 2108: 0001 nop - 210a: 0402 c.slli64 s0 - 210c: 036c addi a1,sp,396 - 210e: 0900 addi s0,sp,144 - 2110: 0000 unimp - 2112: 0601 addi a2,a2,0 - 2114: 08090003 lb zero,128(s2) - 2118: 0100 addi s0,sp,128 - 211a: 0200 addi s0,sp,256 - 211c: 0504 addi s1,sp,640 - 211e: 20097e03 0x20097e03 - 2122: 0100 addi s0,sp,128 - 2124: 0200 addi s0,sp,256 - 2126: 0504 addi s1,sp,640 - 2128: 0306 slli t1,t1,0x1 - 212a: 0901 addi s2,s2,0 - 212c: 0004 0x4 - 212e: 0001 nop - 2130: 0402 c.slli64 s0 - 2132: 0305 addi t1,t1,1 - 2134: 0900 addi s0,sp,144 - 2136: 0000 unimp - 2138: 0001 nop - 213a: 0402 c.slli64 s0 - 213c: 0305 addi t1,t1,1 - 213e: 0900 addi s0,sp,144 - 2140: 0000 unimp - 2142: 0001 nop - 2144: 0402 c.slli64 s0 - 2146: 0305 addi t1,t1,1 - 2148: 0900 addi s0,sp,144 - 214a: 0000 unimp - 214c: 0601 addi a2,a2,0 - 214e: 04090003 lb zero,64(s2) - 2152: 0100 addi s0,sp,128 - 2154: 0200 addi s0,sp,256 - 2156: 3b04 fld fs1,48(a4) - 2158: 0306 slli t1,t1,0x1 - 215a: 0901 addi s2,s2,0 - 215c: 0014 0x14 - 215e: 0001 nop - 2160: 0402 c.slli64 s0 - 2162: 0900033b 0x900033b - 2166: 0000 unimp - 2168: 0001 nop - 216a: 0402 c.slli64 s0 - 216c: 0900033b 0x900033b - 2170: 0000 unimp - 2172: 0001 nop - 2174: 0402 c.slli64 s0 - 2176: 0900033b 0x900033b - 217a: 0008 0x8 - 217c: 0001 nop - 217e: 0402 c.slli64 s0 - 2180: 033c addi a5,sp,392 - 2182: 0900 addi s0,sp,144 - 2184: 0008 0x8 - 2186: 0001 nop - 2188: 0402 c.slli64 s0 - 218a: 033e slli t1,t1,0xf - 218c: 0900 addi s0,sp,144 - 218e: 0008 0x8 - 2190: 0001 nop - 2192: 0402 c.slli64 s0 - 2194: 033e slli t1,t1,0xf - 2196: 0900 addi s0,sp,144 - 2198: 001c 0x1c - 219a: 0001 nop - 219c: 0402 c.slli64 s0 - 219e: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne - 21a2: 0004 0x4 - 21a4: 0001 nop - 21a6: 0402 c.slli64 s0 - 21a8: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne - 21ac: 0000 unimp - 21ae: 0001 nop - 21b0: 0402 c.slli64 s0 - 21b2: 034c addi a1,sp,388 - 21b4: 0900 addi s0,sp,144 - 21b6: 0008 0x8 - 21b8: 0001 nop - 21ba: 0402 c.slli64 s0 - 21bc: 034c addi a1,sp,388 - 21be: 0900 addi s0,sp,144 - 21c0: 0000 unimp - 21c2: 0001 nop - 21c4: 0402 c.slli64 s0 - 21c6: 034c addi a1,sp,388 - 21c8: 0900 addi s0,sp,144 - 21ca: 0000 unimp - 21cc: 0001 nop - 21ce: 0402 c.slli64 s0 - 21d0: 034c addi a1,sp,388 - 21d2: 0900 addi s0,sp,144 - 21d4: 0000 unimp - 21d6: 0001 nop - 21d8: 0402 c.slli64 s0 - 21da: 034e slli t1,t1,0x13 - 21dc: 0900 addi s0,sp,144 - 21de: 000c 0xc - 21e0: 0001 nop - 21e2: 0402 c.slli64 s0 - 21e4: 034e slli t1,t1,0x13 - 21e6: 0900 addi s0,sp,144 - 21e8: 0000 unimp - 21ea: 0001 nop - 21ec: 0402 c.slli64 s0 - 21ee: 034e slli t1,t1,0x13 - 21f0: 0900 addi s0,sp,144 - 21f2: 0000 unimp - 21f4: 0001 nop - 21f6: 0402 c.slli64 s0 - 21f8: 034e slli t1,t1,0x13 - 21fa: 0900 addi s0,sp,144 - 21fc: 0004 0x4 - 21fe: 0001 nop - 2200: 0402 c.slli64 s0 - 2202: 034e slli t1,t1,0x13 - 2204: 0900 addi s0,sp,144 - 2206: 0008 0x8 - 2208: 0001 nop - 220a: 0402 c.slli64 s0 - 220c: 034d addi t1,t1,19 - 220e: 0900 addi s0,sp,144 - 2210: 0004 0x4 - 2212: 0001 nop - 2214: 0402 c.slli64 s0 - 2216: 034d addi t1,t1,19 - 2218: 0900 addi s0,sp,144 - 221a: 0000 unimp - 221c: 0001 nop - 221e: 0402 c.slli64 s0 - 2220: 035d addi t1,t1,23 - 2222: 0900 addi s0,sp,144 - 2224: 0008 0x8 - 2226: 0001 nop - 2228: 0402 c.slli64 s0 - 222a: 035d addi t1,t1,23 - 222c: 0900 addi s0,sp,144 - 222e: 0000 unimp - 2230: 0001 nop - 2232: 0402 c.slli64 s0 - 2234: 035d addi t1,t1,23 - 2236: 0900 addi s0,sp,144 - 2238: 0000 unimp - 223a: 0001 nop - 223c: 0402 c.slli64 s0 - 223e: 035d addi t1,t1,23 - 2240: 0900 addi s0,sp,144 - 2242: 000c 0xc - 2244: 0601 addi a2,a2,0 - 2246: 04090003 lb zero,64(s2) - 224a: 0100 addi s0,sp,128 - 224c: 0200 addi s0,sp,256 - 224e: 3f04 fld fs1,56(a4) - 2250: 0306 slli t1,t1,0x1 - 2252: 0900 addi s0,sp,144 - 2254: 0008 0x8 + 147c: 0001 nop + 147e: 0402 c.slli64 s0 + 1480: 0301 addi t1,t1,0 + 1482: 0900 addi s0,sp,144 + 1484: 0000 unimp + 1486: 0001 nop + 1488: 0402 c.slli64 s0 + 148a: 0301 addi t1,t1,0 + 148c: 0900 addi s0,sp,144 + 148e: 0004 0x4 + 1490: 0001 nop + 1492: 0402 c.slli64 s0 + 1494: 0301 addi t1,t1,0 + 1496: 0900 addi s0,sp,144 + 1498: 0000 unimp + 149a: 0001 nop + 149c: 0402 c.slli64 s0 + 149e: 0329 addi t1,t1,10 + 14a0: 0900 addi s0,sp,144 + 14a2: 0000 unimp + 14a4: 0001 nop + 14a6: 0402 c.slli64 s0 + 14a8: 0329 addi t1,t1,10 + 14aa: 0900 addi s0,sp,144 + 14ac: 0000 unimp + 14ae: 0001 nop + 14b0: 0402 c.slli64 s0 + 14b2: 0308 addi a0,sp,384 + 14b4: 0900 addi s0,sp,144 + 14b6: 0004 0x4 + 14b8: 0001 nop + 14ba: 0402 c.slli64 s0 + 14bc: 0308 addi a0,sp,384 + 14be: 0900 addi s0,sp,144 + 14c0: 0000 unimp + 14c2: 0001 nop + 14c4: 0402 c.slli64 s0 + 14c6: 0308 addi a0,sp,384 + 14c8: 0901 addi s2,s2,0 + 14ca: 0000 unimp + 14cc: 0001 nop + 14ce: 0402 c.slli64 s0 + 14d0: 0308 addi a0,sp,384 + 14d2: 0900 addi s0,sp,144 + 14d4: 0000 unimp + 14d6: 0001 nop + 14d8: 0402 c.slli64 s0 + 14da: 0308 addi a0,sp,384 + 14dc: 0900 addi s0,sp,144 + 14de: 0000 unimp + 14e0: 0001 nop + 14e2: 0402 c.slli64 s0 + 14e4: 0308 addi a0,sp,384 + 14e6: 0900 addi s0,sp,144 + 14e8: 0000 unimp + 14ea: 0001 nop + 14ec: 0402 c.slli64 s0 + 14ee: 0308 addi a0,sp,384 + 14f0: 0900 addi s0,sp,144 + 14f2: 0000 unimp + 14f4: 0001 nop + 14f6: 0402 c.slli64 s0 + 14f8: 0308 addi a0,sp,384 + 14fa: 0900 addi s0,sp,144 + 14fc: 0000 unimp + 14fe: 0001 nop + 1500: 0402 c.slli64 s0 + 1502: 0308 addi a0,sp,384 + 1504: 0900 addi s0,sp,144 + 1506: 0010 0x10 + 1508: 0001 nop + 150a: 0402 c.slli64 s0 + 150c: 0308 addi a0,sp,384 + 150e: 0900 addi s0,sp,144 + 1510: 0004 0x4 + 1512: 0001 nop + 1514: 0402 c.slli64 s0 + 1516: 0308 addi a0,sp,384 + 1518: 0900 addi s0,sp,144 + 151a: 0004 0x4 + 151c: 0001 nop + 151e: 0402 c.slli64 s0 + 1520: 0308 addi a0,sp,384 + 1522: 0900 addi s0,sp,144 + 1524: 0000 unimp + 1526: 0001 nop + 1528: 0402 c.slli64 s0 + 152a: 0308 addi a0,sp,384 + 152c: 0900 addi s0,sp,144 + 152e: 0000 unimp + 1530: 0601 addi a2,a2,0 + 1532: 04090003 lb zero,64(s2) + 1536: 0100 addi s0,sp,128 + 1538: 0200 addi s0,sp,256 + 153a: 0104 addi s1,sp,128 + 153c: 0306 slli t1,t1,0x1 + 153e: 0900 addi s0,sp,144 + 1540: 0008 0x8 + 1542: 0001 nop + 1544: 0402 c.slli64 s0 + 1546: 0301 addi t1,t1,0 + 1548: 0900 addi s0,sp,144 + 154a: 0000 unimp + 154c: 0001 nop + 154e: 0402 c.slli64 s0 + 1550: 0301 addi t1,t1,0 + 1552: 0900 addi s0,sp,144 + 1554: 0000 unimp + 1556: 0001 nop + 1558: 0402 c.slli64 s0 + 155a: 0301 addi t1,t1,0 + 155c: 0900 addi s0,sp,144 + 155e: 0000 unimp + 1560: 0001 nop + 1562: 0402 c.slli64 s0 + 1564: 0301 addi t1,t1,0 + 1566: 0900 addi s0,sp,144 + 1568: 0014 0x14 + 156a: 0001 nop + 156c: 0402 c.slli64 s0 + 156e: 0301 addi t1,t1,0 + 1570: 0900 addi s0,sp,144 + 1572: 0004 0x4 + 1574: 0001 nop + 1576: 0402 c.slli64 s0 + 1578: 0301 addi t1,t1,0 + 157a: 0900 addi s0,sp,144 + 157c: 0000 unimp + 157e: 0001 nop + 1580: 0402 c.slli64 s0 + 1582: 0301 addi t1,t1,0 + 1584: 0900 addi s0,sp,144 + 1586: 0004 0x4 + 1588: 0001 nop + 158a: 0402 c.slli64 s0 + 158c: 0301 addi t1,t1,0 + 158e: 0900 addi s0,sp,144 + 1590: 0000 unimp + 1592: 0001 nop + 1594: 0402 c.slli64 s0 + 1596: 0329 addi t1,t1,10 + 1598: 0900 addi s0,sp,144 + 159a: 0000 unimp + 159c: 0001 nop + 159e: 0402 c.slli64 s0 + 15a0: 0329 addi t1,t1,10 + 15a2: 0900 addi s0,sp,144 + 15a4: 0000 unimp + 15a6: 0001 nop + 15a8: 0402 c.slli64 s0 + 15aa: 0308 addi a0,sp,384 + 15ac: 0900 addi s0,sp,144 + 15ae: 0004 0x4 + 15b0: 0001 nop + 15b2: 0402 c.slli64 s0 + 15b4: 0308 addi a0,sp,384 + 15b6: 0900 addi s0,sp,144 + 15b8: 0000 unimp + 15ba: 0001 nop + 15bc: 0402 c.slli64 s0 + 15be: 0308 addi a0,sp,384 + 15c0: 0901 addi s2,s2,0 + 15c2: 0000 unimp + 15c4: 0001 nop + 15c6: 0402 c.slli64 s0 + 15c8: 0308 addi a0,sp,384 + 15ca: 0900 addi s0,sp,144 + 15cc: 0000 unimp + 15ce: 0001 nop + 15d0: 0402 c.slli64 s0 + 15d2: 0308 addi a0,sp,384 + 15d4: 0900 addi s0,sp,144 + 15d6: 0014 0x14 + 15d8: 0001 nop + 15da: 0402 c.slli64 s0 + 15dc: 0308 addi a0,sp,384 + 15de: 0900 addi s0,sp,144 + 15e0: 0004 0x4 + 15e2: 0001 nop + 15e4: 0402 c.slli64 s0 + 15e6: 0302 c.slli64 t1 + 15e8: 097e slli s2,s2,0x1f + 15ea: 001c 0x1c + 15ec: 0001 nop + 15ee: 0402 c.slli64 s0 + 15f0: 030d addi t1,t1,3 + 15f2: 0900 addi s0,sp,144 + 15f4: 0008 0x8 + 15f6: 0001 nop + 15f8: 0402 c.slli64 s0 + 15fa: 030d addi t1,t1,3 + 15fc: 0900 addi s0,sp,144 + 15fe: 0000 unimp + 1600: 0001 nop + 1602: 0402 c.slli64 s0 + 1604: 030d addi t1,t1,3 + 1606: 0900 addi s0,sp,144 + 1608: 0000 unimp + 160a: 0001 nop + 160c: 0402 c.slli64 s0 + 160e: 030d addi t1,t1,3 + 1610: 0900 addi s0,sp,144 + 1612: 0000 unimp + 1614: 0001 nop + 1616: 0402 c.slli64 s0 + 1618: 0311 addi t1,t1,4 + 161a: 0900 addi s0,sp,144 + 161c: 0004 0x4 + 161e: 0001 nop + 1620: 0402 c.slli64 s0 + 1622: 0311 addi t1,t1,4 + 1624: 0900 addi s0,sp,144 + 1626: 0000 unimp + 1628: 0001 nop + 162a: 0402 c.slli64 s0 + 162c: 0311 addi t1,t1,4 + 162e: 0900 addi s0,sp,144 + 1630: 0000 unimp + 1632: 0001 nop + 1634: 0402 c.slli64 s0 + 1636: 0311 addi t1,t1,4 + 1638: 0900 addi s0,sp,144 + 163a: 0000 unimp + 163c: 0001 nop + 163e: 0402 c.slli64 s0 + 1640: 0311 addi t1,t1,4 + 1642: 0900 addi s0,sp,144 + 1644: 0008 0x8 + 1646: 0001 nop + 1648: 0402 c.slli64 s0 + 164a: 031f 0900 0000 0x900031f + 1650: 0001 nop + 1652: 0402 c.slli64 s0 + 1654: 031f 0900 0000 0x900031f + 165a: 0001 nop + 165c: 0402 c.slli64 s0 + 165e: 031f 0900 0004 0x40900031f + 1664: 0001 nop + 1666: 0402 c.slli64 s0 + 1668: 0320 addi s0,sp,392 + 166a: 0900 addi s0,sp,144 + 166c: 0008 0x8 + 166e: 0001 nop + 1670: 0402 c.slli64 s0 + 1672: 0320 addi s0,sp,392 + 1674: 0900 addi s0,sp,144 + 1676: 0008 0x8 + 1678: 0001 nop + 167a: 0402 c.slli64 s0 + 167c: 0320 addi s0,sp,392 + 167e: 0900 addi s0,sp,144 + 1680: 0010 0x10 + 1682: 0001 nop + 1684: 0402 c.slli64 s0 + 1686: 0320 addi s0,sp,392 + 1688: 0900 addi s0,sp,144 + 168a: 0004 0x4 + 168c: 0001 nop + 168e: 0402 c.slli64 s0 + 1690: 0329 addi t1,t1,10 + 1692: 0900 addi s0,sp,144 + 1694: 0000 unimp + 1696: 0001 nop + 1698: 0402 c.slli64 s0 + 169a: 0318 addi a4,sp,384 + 169c: 0900 addi s0,sp,144 + 169e: 000c 0xc + 16a0: 0001 nop + 16a2: 0402 c.slli64 s0 + 16a4: 0318 addi a4,sp,384 + 16a6: 0900 addi s0,sp,144 + 16a8: 0000 unimp + 16aa: 0001 nop + 16ac: 0402 c.slli64 s0 + 16ae: 0318 addi a4,sp,384 + 16b0: 0900 addi s0,sp,144 + 16b2: 0000 unimp + 16b4: 0001 nop + 16b6: 0402 c.slli64 s0 + 16b8: 0318 addi a4,sp,384 + 16ba: 0900 addi s0,sp,144 + 16bc: 0000 unimp + 16be: 0001 nop + 16c0: 0402 c.slli64 s0 + 16c2: 0318 addi a4,sp,384 + 16c4: 0900 addi s0,sp,144 + 16c6: 0004 0x4 + 16c8: 0001 nop + 16ca: 0402 c.slli64 s0 + 16cc: 0318 addi a4,sp,384 + 16ce: 0900 addi s0,sp,144 + 16d0: 0000 unimp + 16d2: 0001 nop + 16d4: 0402 c.slli64 s0 + 16d6: 0321 addi t1,t1,8 + 16d8: 0900 addi s0,sp,144 + 16da: 0008 0x8 + 16dc: 0001 nop + 16de: 0402 c.slli64 s0 + 16e0: 0321 addi t1,t1,8 + 16e2: 0900 addi s0,sp,144 + 16e4: 0008 0x8 + 16e6: 0001 nop + 16e8: 0402 c.slli64 s0 + 16ea: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 16ee: 0008 0x8 + 16f0: 0601 addi a2,a2,0 + 16f2: 0c090003 lb zero,192(s2) + 16f6: 0100 addi s0,sp,128 + 16f8: 0200 addi s0,sp,256 + 16fa: 0204 addi s1,sp,256 + 16fc: 0306 slli t1,t1,0x1 + 16fe: 0901 addi s2,s2,0 + 1700: 0030 addi a2,sp,8 + 1702: 0001 nop + 1704: 0402 c.slli64 s0 + 1706: 030d addi t1,t1,3 + 1708: 0900 addi s0,sp,144 + 170a: 0008 0x8 + 170c: 0001 nop + 170e: 0402 c.slli64 s0 + 1710: 030d addi t1,t1,3 + 1712: 0900 addi s0,sp,144 + 1714: 0000 unimp + 1716: 0001 nop + 1718: 0402 c.slli64 s0 + 171a: 030d addi t1,t1,3 + 171c: 0900 addi s0,sp,144 + 171e: 0000 unimp + 1720: 0001 nop + 1722: 0402 c.slli64 s0 + 1724: 030d addi t1,t1,3 + 1726: 0900 addi s0,sp,144 + 1728: 0000 unimp + 172a: 0001 nop + 172c: 0402 c.slli64 s0 + 172e: 0311 addi t1,t1,4 + 1730: 0900 addi s0,sp,144 + 1732: 0004 0x4 + 1734: 0001 nop + 1736: 0402 c.slli64 s0 + 1738: 0311 addi t1,t1,4 + 173a: 0900 addi s0,sp,144 + 173c: 0000 unimp + 173e: 0001 nop + 1740: 0402 c.slli64 s0 + 1742: 0311 addi t1,t1,4 + 1744: 0900 addi s0,sp,144 + 1746: 0000 unimp + 1748: 0001 nop + 174a: 0402 c.slli64 s0 + 174c: 0311 addi t1,t1,4 + 174e: 0900 addi s0,sp,144 + 1750: 0000 unimp + 1752: 0001 nop + 1754: 0402 c.slli64 s0 + 1756: 0311 addi t1,t1,4 + 1758: 0900 addi s0,sp,144 + 175a: 000c 0xc + 175c: 0001 nop + 175e: 0402 c.slli64 s0 + 1760: 031f 0900 0000 0x900031f + 1766: 0001 nop + 1768: 0402 c.slli64 s0 + 176a: 031f 0900 0000 0x900031f + 1770: 0001 nop + 1772: 0402 c.slli64 s0 + 1774: 031f 0900 0004 0x40900031f + 177a: 0001 nop + 177c: 0402 c.slli64 s0 + 177e: 0320 addi s0,sp,392 + 1780: 0900 addi s0,sp,144 + 1782: 0008 0x8 + 1784: 0001 nop + 1786: 0402 c.slli64 s0 + 1788: 0320 addi s0,sp,392 + 178a: 0900 addi s0,sp,144 + 178c: 0008 0x8 + 178e: 0001 nop + 1790: 0402 c.slli64 s0 + 1792: 0320 addi s0,sp,392 + 1794: 0900 addi s0,sp,144 + 1796: 0010 0x10 + 1798: 0001 nop + 179a: 0402 c.slli64 s0 + 179c: 0320 addi s0,sp,392 + 179e: 0900 addi s0,sp,144 + 17a0: 0004 0x4 + 17a2: 0001 nop + 17a4: 0402 c.slli64 s0 + 17a6: 0329 addi t1,t1,10 + 17a8: 0900 addi s0,sp,144 + 17aa: 0000 unimp + 17ac: 0001 nop + 17ae: 0402 c.slli64 s0 + 17b0: 0318 addi a4,sp,384 + 17b2: 0900 addi s0,sp,144 + 17b4: 000c 0xc + 17b6: 0001 nop + 17b8: 0402 c.slli64 s0 + 17ba: 0318 addi a4,sp,384 + 17bc: 0900 addi s0,sp,144 + 17be: 0000 unimp + 17c0: 0001 nop + 17c2: 0402 c.slli64 s0 + 17c4: 0318 addi a4,sp,384 + 17c6: 0900 addi s0,sp,144 + 17c8: 0000 unimp + 17ca: 0001 nop + 17cc: 0402 c.slli64 s0 + 17ce: 0318 addi a4,sp,384 + 17d0: 0900 addi s0,sp,144 + 17d2: 0000 unimp + 17d4: 0001 nop + 17d6: 0402 c.slli64 s0 + 17d8: 0318 addi a4,sp,384 + 17da: 0900 addi s0,sp,144 + 17dc: 0008 0x8 + 17de: 0001 nop + 17e0: 0402 c.slli64 s0 + 17e2: 0318 addi a4,sp,384 + 17e4: 0900 addi s0,sp,144 + 17e6: 0000 unimp + 17e8: 0001 nop + 17ea: 0402 c.slli64 s0 + 17ec: 0321 addi t1,t1,8 + 17ee: 0900 addi s0,sp,144 + 17f0: 0008 0x8 + 17f2: 0001 nop + 17f4: 0402 c.slli64 s0 + 17f6: 0321 addi t1,t1,8 + 17f8: 0900 addi s0,sp,144 + 17fa: 0008 0x8 + 17fc: 0001 nop + 17fe: 0402 c.slli64 s0 + 1800: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 1804: 0008 0x8 + 1806: 0601 addi a2,a2,0 + 1808: 08090003 lb zero,128(s2) + 180c: 0100 addi s0,sp,128 + 180e: 0200 addi s0,sp,256 + 1810: 0204 addi s1,sp,256 + 1812: 0306 slli t1,t1,0x1 + 1814: 0901 addi s2,s2,0 + 1816: 0030 addi a2,sp,8 + 1818: 0001 nop + 181a: 0402 c.slli64 s0 + 181c: 0302 c.slli64 t1 + 181e: 0900 addi s0,sp,144 + 1820: 0000 unimp + 1822: 0001 nop + 1824: 0402 c.slli64 s0 + 1826: 0302 c.slli64 t1 + 1828: 0900 addi s0,sp,144 + 182a: 0000 unimp + 182c: 0001 nop + 182e: 0402 c.slli64 s0 + 1830: 0302 c.slli64 t1 + 1832: 0900 addi s0,sp,144 + 1834: 0000 unimp + 1836: 0001 nop + 1838: 0402 c.slli64 s0 + 183a: 0302 c.slli64 t1 + 183c: 0900 addi s0,sp,144 + 183e: 0000 unimp + 1840: 0001 nop + 1842: 0402 c.slli64 s0 + 1844: 0302 c.slli64 t1 + 1846: 0900 addi s0,sp,144 + 1848: 0000 unimp + 184a: 0001 nop + 184c: 0402 c.slli64 s0 + 184e: 0302 c.slli64 t1 + 1850: 0900 addi s0,sp,144 + 1852: 0000 unimp + 1854: 0001 nop + 1856: 0402 c.slli64 s0 + 1858: 0302 c.slli64 t1 + 185a: 0900 addi s0,sp,144 + 185c: 0000 unimp + 185e: 0001 nop + 1860: 0402 c.slli64 s0 + 1862: 0302 c.slli64 t1 + 1864: 0900 addi s0,sp,144 + 1866: 0000 unimp + 1868: 0001 nop + 186a: 0402 c.slli64 s0 + 186c: 0302 c.slli64 t1 + 186e: 0900 addi s0,sp,144 + 1870: 0000 unimp + 1872: 0001 nop + 1874: 0402 c.slli64 s0 + 1876: 0003060b 0x3060b + 187a: 0409 addi s0,s0,2 + 187c: 0100 addi s0,sp,128 + 187e: 0200 addi s0,sp,256 + 1880: 0c04 addi s1,sp,528 + 1882: 04090003 lb zero,64(s2) + 1886: 0100 addi s0,sp,128 + 1888: 0200 addi s0,sp,256 + 188a: 0e04 addi s1,sp,784 + 188c: 0306 slli t1,t1,0x1 + 188e: 0900 addi s0,sp,144 + 1890: 0004 0x4 + 1892: 0001 nop + 1894: 0402 c.slli64 s0 + 1896: 030e slli t1,t1,0x3 + 1898: 0900 addi s0,sp,144 + 189a: 0000 unimp + 189c: 0001 nop + 189e: 0402 c.slli64 s0 + 18a0: 030e slli t1,t1,0x3 + 18a2: 0900 addi s0,sp,144 + 18a4: 0008 0x8 + 18a6: 0001 nop + 18a8: 0402 c.slli64 s0 + 18aa: 09000313 li t1,144 + 18ae: 000c 0xc + 18b0: 0001 nop + 18b2: 0402 c.slli64 s0 + 18b4: 09000313 li t1,144 + 18b8: 0000 unimp + 18ba: 0001 nop + 18bc: 0402 c.slli64 s0 + 18be: 09000313 li t1,144 + 18c2: 0000 unimp + 18c4: 0001 nop + 18c6: 0402 c.slli64 s0 + 18c8: 09000313 li t1,144 + 18cc: 000c 0xc + 18ce: 0001 nop + 18d0: 0402 c.slli64 s0 + 18d2: 09000313 li t1,144 + 18d6: 0018 0x18 + 18d8: 0001 nop + 18da: 0402 c.slli64 s0 + 18dc: 09000313 li t1,144 + 18e0: 0000 unimp + 18e2: 0001 nop + 18e4: 0402 c.slli64 s0 + 18e6: 09000313 li t1,144 + 18ea: 0000 unimp + 18ec: 0001 nop + 18ee: 0402 c.slli64 s0 + 18f0: 09000313 li t1,144 + 18f4: 0000 unimp + 18f6: 0001 nop + 18f8: 0402 c.slli64 s0 + 18fa: 09000313 li t1,144 + 18fe: 0000 unimp + 1900: 0001 nop + 1902: 0402 c.slli64 s0 + 1904: 09000313 li t1,144 + 1908: 0000 unimp + 190a: 0001 nop + 190c: 0402 c.slli64 s0 + 190e: 09000313 li t1,144 + 1912: 0000 unimp + 1914: 0001 nop + 1916: 0402 c.slli64 s0 + 1918: 09000313 li t1,144 + 191c: 0000 unimp + 191e: 0001 nop + 1920: 0402 c.slli64 s0 + 1922: 09000313 li t1,144 + 1926: 0000 unimp + 1928: 0001 nop + 192a: 0402 c.slli64 s0 + 192c: 09000313 li t1,144 + 1930: 000c 0xc + 1932: 0001 nop + 1934: 0402 c.slli64 s0 + 1936: 09000313 li t1,144 + 193a: 0008 0x8 + 193c: 0001 nop + 193e: 0402 c.slli64 s0 + 1940: 0316 slli t1,t1,0x5 + 1942: 0900 addi s0,sp,144 + 1944: 0004 0x4 + 1946: 0001 nop + 1948: 0402 c.slli64 s0 + 194a: 0316 slli t1,t1,0x5 + 194c: 0900 addi s0,sp,144 + 194e: 0008 0x8 + 1950: 0001 nop + 1952: 0402 c.slli64 s0 + 1954: 0318 addi a4,sp,384 + 1956: 0900 addi s0,sp,144 + 1958: 0004 0x4 + 195a: 0001 nop + 195c: 0402 c.slli64 s0 + 195e: 031a slli t1,t1,0x6 + 1960: 0900 addi s0,sp,144 + 1962: 0004 0x4 + 1964: 0001 nop + 1966: 0402 c.slli64 s0 + 1968: 031c addi a5,sp,384 + 196a: 0900 addi s0,sp,144 + 196c: 0008 0x8 + 196e: 0001 nop + 1970: 0402 c.slli64 s0 + 1972: 031c addi a5,sp,384 + 1974: 0900 addi s0,sp,144 + 1976: 0004 0x4 + 1978: 0001 nop + 197a: 0402 c.slli64 s0 + 197c: 031c addi a5,sp,384 + 197e: 0900 addi s0,sp,144 + 1980: 0000 unimp + 1982: 0001 nop + 1984: 0402 c.slli64 s0 + 1986: 031c addi a5,sp,384 + 1988: 0900 addi s0,sp,144 + 198a: 0004 0x4 + 198c: 0001 nop + 198e: 0402 c.slli64 s0 + 1990: 031c addi a5,sp,384 + 1992: 0900 addi s0,sp,144 + 1994: 0014 0x14 + 1996: 0001 nop + 1998: 0402 c.slli64 s0 + 199a: 031c addi a5,sp,384 + 199c: 0900 addi s0,sp,144 + 199e: 0008 0x8 + 19a0: 0001 nop + 19a2: 0402 c.slli64 s0 + 19a4: 031d addi t1,t1,7 + 19a6: 0900 addi s0,sp,144 + 19a8: 0004 0x4 + 19aa: 0001 nop + 19ac: 0402 c.slli64 s0 + 19ae: 031d addi t1,t1,7 + 19b0: 0900 addi s0,sp,144 + 19b2: 0008 0x8 + 19b4: 0001 nop + 19b6: 0402 c.slli64 s0 + 19b8: 031f 0900 0004 0x40900031f + 19be: 0001 nop + 19c0: 0402 c.slli64 s0 + 19c2: 0321 addi t1,t1,8 + 19c4: 0900 addi s0,sp,144 + 19c6: 0004 0x4 + 19c8: 0001 nop + 19ca: 0402 c.slli64 s0 + 19cc: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 19d0: 0008 0x8 + 19d2: 0001 nop + 19d4: 0402 c.slli64 s0 + 19d6: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 19da: 0004 0x4 + 19dc: 0001 nop + 19de: 0402 c.slli64 s0 + 19e0: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 19e4: 000c 0xc + 19e6: 0001 nop + 19e8: 0402 c.slli64 s0 + 19ea: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 19ee: 0000 unimp + 19f0: 0001 nop + 19f2: 0402 c.slli64 s0 + 19f4: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 19f8: 0000 unimp + 19fa: 0001 nop + 19fc: 0402 c.slli64 s0 + 19fe: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a02: 0000 unimp + 1a04: 0001 nop + 1a06: 0402 c.slli64 s0 + 1a08: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a0c: 0000 unimp + 1a0e: 0001 nop + 1a10: 0402 c.slli64 s0 + 1a12: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a16: 0000 unimp + 1a18: 0001 nop + 1a1a: 0402 c.slli64 s0 + 1a1c: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a20: 0000 unimp + 1a22: 0001 nop + 1a24: 0402 c.slli64 s0 + 1a26: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a2a: 0008 0x8 + 1a2c: 0001 nop + 1a2e: 0402 c.slli64 s0 + 1a30: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a34: 0000 unimp + 1a36: 0001 nop + 1a38: 0402 c.slli64 s0 + 1a3a: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a3e: 0008 0x8 + 1a40: 0001 nop + 1a42: 0402 c.slli64 s0 + 1a44: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a48: 0008 0x8 + 1a4a: 0001 nop + 1a4c: 0402 c.slli64 s0 + 1a4e: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a52: 0000 unimp + 1a54: 0001 nop + 1a56: 0402 c.slli64 s0 + 1a58: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a5c: 0004 0x4 + 1a5e: 0001 nop + 1a60: 0402 c.slli64 s0 + 1a62: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a66: 0008 0x8 + 1a68: 0001 nop + 1a6a: 0402 c.slli64 s0 + 1a6c: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a70: 0004 0x4 + 1a72: 0001 nop + 1a74: 0402 c.slli64 s0 + 1a76: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 1a7a: 0008 0x8 + 1a7c: 0001 nop + 1a7e: 0402 c.slli64 s0 + 1a80: 0324 addi s1,sp,392 + 1a82: 0900 addi s0,sp,144 + 1a84: 0004 0x4 + 1a86: 0001 nop + 1a88: 0402 c.slli64 s0 + 1a8a: 0326 slli t1,t1,0x9 + 1a8c: 0900 addi s0,sp,144 + 1a8e: 0004 0x4 + 1a90: 0001 nop + 1a92: 0402 c.slli64 s0 + 1a94: 0326 slli t1,t1,0x9 + 1a96: 0900 addi s0,sp,144 + 1a98: 0008 0x8 + 1a9a: 0001 nop + 1a9c: 0402 c.slli64 s0 + 1a9e: 0326 slli t1,t1,0x9 + 1aa0: 0900 addi s0,sp,144 + 1aa2: 0018 0x18 + 1aa4: 0001 nop + 1aa6: 0402 c.slli64 s0 + 1aa8: 0326 slli t1,t1,0x9 + 1aaa: 0900 addi s0,sp,144 + 1aac: 0000 unimp + 1aae: 0001 nop + 1ab0: 0402 c.slli64 s0 + 1ab2: 0326 slli t1,t1,0x9 + 1ab4: 0900 addi s0,sp,144 + 1ab6: 0000 unimp + 1ab8: 0001 nop + 1aba: 0402 c.slli64 s0 + 1abc: 0628 addi a0,sp,776 + 1abe: 04090003 lb zero,64(s2) + 1ac2: 0100 addi s0,sp,128 + 1ac4: 0200 addi s0,sp,256 + 1ac6: 2904 fld fs1,16(a0) + 1ac8: 08090003 lb zero,128(s2) + 1acc: 0100 addi s0,sp,128 + 1ace: 0200 addi s0,sp,256 + 1ad0: 2b04 fld fs1,16(a4) + 1ad2: 0306 slli t1,t1,0x1 + 1ad4: 0900 addi s0,sp,144 + 1ad6: 0004 0x4 + 1ad8: 0001 nop + 1ada: 0402 c.slli64 s0 + 1adc: 0900032b 0x900032b + 1ae0: 0014 0x14 + 1ae2: 0001 nop + 1ae4: 0402 c.slli64 s0 + 1ae6: 0900032b 0x900032b + 1aea: 0000 unimp + 1aec: 0001 nop + 1aee: 0402 c.slli64 s0 + 1af0: 0900032b 0x900032b + 1af4: 0000 unimp + 1af6: 0001 nop + 1af8: 0402 c.slli64 s0 + 1afa: 0900032b 0x900032b + 1afe: 0000 unimp + 1b00: 0001 nop + 1b02: 0402 c.slli64 s0 + 1b04: 0900032b 0x900032b + 1b08: 0000 unimp + 1b0a: 0001 nop + 1b0c: 0402 c.slli64 s0 + 1b0e: 0900032b 0x900032b + 1b12: 0000 unimp + 1b14: 0001 nop + 1b16: 0402 c.slli64 s0 + 1b18: 0900032b 0x900032b + 1b1c: 0000 unimp + 1b1e: 0001 nop + 1b20: 0402 c.slli64 s0 + 1b22: 062e slli a2,a2,0xb + 1b24: 04090003 lb zero,64(s2) + 1b28: 0100 addi s0,sp,128 + 1b2a: 0200 addi s0,sp,256 + 1b2c: 2f04 fld fs1,24(a4) + 1b2e: 04090003 lb zero,64(s2) + 1b32: 0100 addi s0,sp,128 + 1b34: 0200 addi s0,sp,256 + 1b36: 3104 fld fs1,32(a0) + 1b38: 04090003 lb zero,64(s2) + 1b3c: 0100 addi s0,sp,128 + 1b3e: 0200 addi s0,sp,256 + 1b40: 3404 fld fs1,40(s0) + 1b42: 04090003 lb zero,64(s2) + 1b46: 0100 addi s0,sp,128 + 1b48: 0200 addi s0,sp,256 + 1b4a: 3504 fld fs1,40(a0) + 1b4c: 04090003 lb zero,64(s2) + 1b50: 0100 addi s0,sp,128 + 1b52: 0200 addi s0,sp,256 + 1b54: 3704 fld fs1,40(a4) + 1b56: 0306 slli t1,t1,0x1 + 1b58: 0900 addi s0,sp,144 + 1b5a: 0004 0x4 + 1b5c: 0001 nop + 1b5e: 0402 c.slli64 s0 + 1b60: 09000337 lui t1,0x9000 + 1b64: 0010 0x10 + 1b66: 0001 nop + 1b68: 0402 c.slli64 s0 + 1b6a: 09000337 lui t1,0x9000 + 1b6e: 0000 unimp + 1b70: 0001 nop + 1b72: 0402 c.slli64 s0 + 1b74: 09000337 lui t1,0x9000 + 1b78: 0000 unimp + 1b7a: 0001 nop + 1b7c: 0402 c.slli64 s0 + 1b7e: 09000337 lui t1,0x9000 + 1b82: 0000 unimp + 1b84: 0001 nop + 1b86: 0402 c.slli64 s0 + 1b88: 09000337 lui t1,0x9000 + 1b8c: 0004 0x4 + 1b8e: 0001 nop + 1b90: 0402 c.slli64 s0 + 1b92: 0339 addi t1,t1,14 + 1b94: 0900 addi s0,sp,144 + 1b96: 0000 unimp + 1b98: 0001 nop + 1b9a: 0402 c.slli64 s0 + 1b9c: 0339 addi t1,t1,14 + 1b9e: 0900 addi s0,sp,144 + 1ba0: 0000 unimp + 1ba2: 0001 nop + 1ba4: 0402 c.slli64 s0 + 1ba6: 0339 addi t1,t1,14 + 1ba8: 0900 addi s0,sp,144 + 1baa: 0000 unimp + 1bac: 0001 nop + 1bae: 0402 c.slli64 s0 + 1bb0: 0339 addi t1,t1,14 + 1bb2: 0900 addi s0,sp,144 + 1bb4: 0000 unimp + 1bb6: 0001 nop + 1bb8: 0402 c.slli64 s0 + 1bba: 0339 addi t1,t1,14 + 1bbc: 0900 addi s0,sp,144 + 1bbe: 0004 0x4 + 1bc0: 0001 nop + 1bc2: 0402 c.slli64 s0 + 1bc4: 0339 addi t1,t1,14 + 1bc6: 0900 addi s0,sp,144 + 1bc8: 000c 0xc + 1bca: 0001 nop + 1bcc: 0402 c.slli64 s0 + 1bce: 0339 addi t1,t1,14 + 1bd0: 0900 addi s0,sp,144 + 1bd2: 0000 unimp + 1bd4: 0001 nop + 1bd6: 0402 c.slli64 s0 + 1bd8: 0339 addi t1,t1,14 + 1bda: 0900 addi s0,sp,144 + 1bdc: 0000 unimp + 1bde: 0001 nop + 1be0: 0402 c.slli64 s0 + 1be2: 0900033b 0x900033b + 1be6: 0008 0x8 + 1be8: 0001 nop + 1bea: 0402 c.slli64 s0 + 1bec: 0900033b 0x900033b + 1bf0: 0000 unimp + 1bf2: 0001 nop + 1bf4: 0402 c.slli64 s0 + 1bf6: 0900033b 0x900033b + 1bfa: 0000 unimp + 1bfc: 0001 nop + 1bfe: 0402 c.slli64 s0 + 1c00: 0900033b 0x900033b + 1c04: 0000 unimp + 1c06: 0001 nop + 1c08: 0402 c.slli64 s0 + 1c0a: 0900033b 0x900033b + 1c0e: 0000 unimp + 1c10: 0001 nop + 1c12: 0402 c.slli64 s0 + 1c14: 0900033b 0x900033b + 1c18: 0000 unimp + 1c1a: 0001 nop + 1c1c: 0402 c.slli64 s0 + 1c1e: 0900033b 0x900033b + 1c22: 0000 unimp + 1c24: 0001 nop + 1c26: 0402 c.slli64 s0 + 1c28: 0900033b 0x900033b + 1c2c: 0004 0x4 + 1c2e: 0001 nop + 1c30: 0402 c.slli64 s0 + 1c32: 0900033b 0x900033b + 1c36: 0010 0x10 + 1c38: 0001 nop + 1c3a: 0402 c.slli64 s0 + 1c3c: 0900033b 0x900033b + 1c40: 0008 0x8 + 1c42: 0001 nop + 1c44: 0402 c.slli64 s0 + 1c46: 033d addi t1,t1,15 + 1c48: 0900 addi s0,sp,144 + 1c4a: 0004 0x4 + 1c4c: 0001 nop + 1c4e: 0402 c.slli64 s0 + 1c50: 033d addi t1,t1,15 + 1c52: 0900 addi s0,sp,144 + 1c54: 0008 0x8 + 1c56: 0001 nop + 1c58: 0402 c.slli64 s0 + 1c5a: 0900033f 00010004 0x100040900033f + 1c62: 0402 c.slli64 s0 + 1c64: 0341 addi t1,t1,16 + 1c66: 0900 addi s0,sp,144 + 1c68: 0004 0x4 + 1c6a: 0001 nop + 1c6c: 0402 c.slli64 s0 + 1c6e: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne + 1c72: 0008 0x8 + 1c74: 0001 nop + 1c76: 0402 c.slli64 s0 + 1c78: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne + 1c7c: 0004 0x4 + 1c7e: 0001 nop + 1c80: 0402 c.slli64 s0 + 1c82: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne + 1c86: 0000 unimp + 1c88: 0001 nop + 1c8a: 0402 c.slli64 s0 + 1c8c: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne + 1c90: 0004 0x4 + 1c92: 0001 nop + 1c94: 0402 c.slli64 s0 + 1c96: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne + 1c9a: 0014 0x14 + 1c9c: 0001 nop + 1c9e: 0402 c.slli64 s0 + 1ca0: 09000343 fmadd.s ft6,ft0,fa6,ft1,rne + 1ca4: 0008 0x8 + 1ca6: 0001 nop + 1ca8: 0402 c.slli64 s0 + 1caa: 0344 addi s1,sp,388 + 1cac: 0900 addi s0,sp,144 + 1cae: 0004 0x4 + 1cb0: 0001 nop + 1cb2: 0402 c.slli64 s0 + 1cb4: 0344 addi s1,sp,388 + 1cb6: 0900 addi s0,sp,144 + 1cb8: 0008 0x8 + 1cba: 0001 nop + 1cbc: 0402 c.slli64 s0 + 1cbe: 0346 slli t1,t1,0x11 + 1cc0: 0900 addi s0,sp,144 + 1cc2: 0004 0x4 + 1cc4: 0001 nop + 1cc6: 0402 c.slli64 s0 + 1cc8: 0348 addi a0,sp,388 + 1cca: 0900 addi s0,sp,144 + 1ccc: 0004 0x4 + 1cce: 0001 nop + 1cd0: 0402 c.slli64 s0 + 1cd2: 034a slli t1,t1,0x12 + 1cd4: 0900 addi s0,sp,144 + 1cd6: 0008 0x8 + 1cd8: 0001 nop + 1cda: 0402 c.slli64 s0 + 1cdc: 034a slli t1,t1,0x12 + 1cde: 0900 addi s0,sp,144 + 1ce0: 001c 0x1c + 1ce2: 0001 nop + 1ce4: 0402 c.slli64 s0 + 1ce6: 034a slli t1,t1,0x12 + 1ce8: 0900 addi s0,sp,144 + 1cea: 0000 unimp + 1cec: 0001 nop + 1cee: 0402 c.slli64 s0 + 1cf0: 034a slli t1,t1,0x12 + 1cf2: 0900 addi s0,sp,144 + 1cf4: 0000 unimp + 1cf6: 0001 nop + 1cf8: 0402 c.slli64 s0 + 1cfa: 034a slli t1,t1,0x12 + 1cfc: 0900 addi s0,sp,144 + 1cfe: 0000 unimp + 1d00: 0001 nop + 1d02: 0402 c.slli64 s0 + 1d04: 034a slli t1,t1,0x12 + 1d06: 0900 addi s0,sp,144 + 1d08: 0000 unimp + 1d0a: 0001 nop + 1d0c: 0402 c.slli64 s0 + 1d0e: 034a slli t1,t1,0x12 + 1d10: 0900 addi s0,sp,144 + 1d12: 0000 unimp + 1d14: 0001 nop + 1d16: 0402 c.slli64 s0 + 1d18: 034a slli t1,t1,0x12 + 1d1a: 0900 addi s0,sp,144 + 1d1c: 0000 unimp + 1d1e: 0001 nop + 1d20: 0402 c.slli64 s0 + 1d22: 034a slli t1,t1,0x12 + 1d24: 0900 addi s0,sp,144 + 1d26: 0000 unimp + 1d28: 0001 nop + 1d2a: 0402 c.slli64 s0 + 1d2c: 034a slli t1,t1,0x12 + 1d2e: 0900 addi s0,sp,144 + 1d30: 0000 unimp + 1d32: 0001 nop + 1d34: 0402 c.slli64 s0 + 1d36: 034a slli t1,t1,0x12 + 1d38: 0900 addi s0,sp,144 + 1d3a: 0000 unimp + 1d3c: 0001 nop + 1d3e: 0402 c.slli64 s0 + 1d40: 034a slli t1,t1,0x12 + 1d42: 0900 addi s0,sp,144 + 1d44: 0000 unimp + 1d46: 0001 nop + 1d48: 0402 c.slli64 s0 + 1d4a: 034a slli t1,t1,0x12 + 1d4c: 0900 addi s0,sp,144 + 1d4e: 0008 0x8 + 1d50: 0001 nop + 1d52: 0402 c.slli64 s0 + 1d54: 034a slli t1,t1,0x12 + 1d56: 0900 addi s0,sp,144 + 1d58: 0000 unimp + 1d5a: 0001 nop + 1d5c: 0402 c.slli64 s0 + 1d5e: 034a slli t1,t1,0x12 + 1d60: 0900 addi s0,sp,144 + 1d62: 0004 0x4 + 1d64: 0001 nop + 1d66: 0402 c.slli64 s0 + 1d68: 034a slli t1,t1,0x12 + 1d6a: 0900 addi s0,sp,144 + 1d6c: 0000 unimp + 1d6e: 0001 nop + 1d70: 0402 c.slli64 s0 + 1d72: 034a slli t1,t1,0x12 + 1d74: 0900 addi s0,sp,144 + 1d76: 0008 0x8 + 1d78: 0001 nop + 1d7a: 0402 c.slli64 s0 + 1d7c: 034a slli t1,t1,0x12 + 1d7e: 0900 addi s0,sp,144 + 1d80: 0004 0x4 + 1d82: 0001 nop + 1d84: 0402 c.slli64 s0 + 1d86: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne + 1d8a: 0004 0x4 + 1d8c: 0001 nop + 1d8e: 0402 c.slli64 s0 + 1d90: 034d addi t1,t1,19 + 1d92: 0900 addi s0,sp,144 + 1d94: 0008 0x8 + 1d96: 0001 nop + 1d98: 0402 c.slli64 s0 + 1d9a: 034d addi t1,t1,19 + 1d9c: 0900 addi s0,sp,144 + 1d9e: 0008 0x8 + 1da0: 0001 nop + 1da2: 0402 c.slli64 s0 + 1da4: 034d addi t1,t1,19 + 1da6: 0900 addi s0,sp,144 + 1da8: 0018 0x18 + 1daa: 0001 nop + 1dac: 0402 c.slli64 s0 + 1dae: 034d addi t1,t1,19 + 1db0: 0900 addi s0,sp,144 + 1db2: 0000 unimp + 1db4: 0001 nop + 1db6: 0402 c.slli64 s0 + 1db8: 034d addi t1,t1,19 + 1dba: 0900 addi s0,sp,144 + 1dbc: 0000 unimp + 1dbe: 0001 nop + 1dc0: 0402 c.slli64 s0 + 1dc2: 0003064f fnmadd.s fa2,ft6,ft0,ft0,rne + 1dc6: 0409 addi s0,s0,2 + 1dc8: 0100 addi s0,sp,128 + 1dca: 0200 addi s0,sp,256 + 1dcc: 5004 lw s1,32(s0) + 1dce: 04090003 lb zero,64(s2) + 1dd2: 0100 addi s0,sp,128 + 1dd4: 0200 addi s0,sp,256 + 1dd6: 5204 lw s1,32(a2) + 1dd8: 0306 slli t1,t1,0x1 + 1dda: 0900 addi s0,sp,144 + 1ddc: 0008 0x8 + 1dde: 0001 nop + 1de0: 0402 c.slli64 s0 + 1de2: 0352 slli t1,t1,0x14 + 1de4: 0900 addi s0,sp,144 + 1de6: 0008 0x8 + 1de8: 0001 nop + 1dea: 0402 c.slli64 s0 + 1dec: 0352 slli t1,t1,0x14 + 1dee: 0900 addi s0,sp,144 + 1df0: 0000 unimp + 1df2: 0001 nop + 1df4: 0402 c.slli64 s0 + 1df6: 0352 slli t1,t1,0x14 + 1df8: 0900 addi s0,sp,144 + 1dfa: 0000 unimp + 1dfc: 0001 nop + 1dfe: 0402 c.slli64 s0 + 1e00: 0352 slli t1,t1,0x14 + 1e02: 0900 addi s0,sp,144 + 1e04: 0000 unimp + 1e06: 0001 nop + 1e08: 0402 c.slli64 s0 + 1e0a: 0352 slli t1,t1,0x14 + 1e0c: 0900 addi s0,sp,144 + 1e0e: 0000 unimp + 1e10: 0001 nop + 1e12: 0402 c.slli64 s0 + 1e14: 0352 slli t1,t1,0x14 + 1e16: 0900 addi s0,sp,144 + 1e18: 0000 unimp + 1e1a: 0001 nop + 1e1c: 0402 c.slli64 s0 + 1e1e: 0352 slli t1,t1,0x14 + 1e20: 0900 addi s0,sp,144 + 1e22: 0000 unimp + 1e24: 0001 nop + 1e26: 0402 c.slli64 s0 + 1e28: 0658 addi a4,sp,772 + 1e2a: 04090003 lb zero,64(s2) + 1e2e: 0100 addi s0,sp,128 + 1e30: 0200 addi s0,sp,256 + 1e32: 5b04 lw s1,48(a4) + 1e34: 04090003 lb zero,64(s2) + 1e38: 0100 addi s0,sp,128 + 1e3a: 0200 addi s0,sp,256 + 1e3c: 5c04 lw s1,56(s0) + 1e3e: 04090003 lb zero,64(s2) + 1e42: 0100 addi s0,sp,128 + 1e44: 0200 addi s0,sp,256 + 1e46: 5e04 lw s1,56(a2) + 1e48: 0306 slli t1,t1,0x1 + 1e4a: 0900 addi s0,sp,144 + 1e4c: 0004 0x4 + 1e4e: 0001 nop + 1e50: 0402 c.slli64 s0 + 1e52: 035e slli t1,t1,0x17 + 1e54: 0900 addi s0,sp,144 + 1e56: 0010 0x10 + 1e58: 0001 nop + 1e5a: 0402 c.slli64 s0 + 1e5c: 035e slli t1,t1,0x17 + 1e5e: 0900 addi s0,sp,144 + 1e60: 0000 unimp + 1e62: 0001 nop + 1e64: 0402 c.slli64 s0 + 1e66: 035e slli t1,t1,0x17 + 1e68: 0900 addi s0,sp,144 + 1e6a: 0000 unimp + 1e6c: 0001 nop + 1e6e: 0402 c.slli64 s0 + 1e70: 035e slli t1,t1,0x17 + 1e72: 0900 addi s0,sp,144 + 1e74: 0000 unimp + 1e76: 0001 nop + 1e78: 0402 c.slli64 s0 + 1e7a: 035e slli t1,t1,0x17 + 1e7c: 0900 addi s0,sp,144 + 1e7e: 0004 0x4 + 1e80: 0001 nop + 1e82: 0402 c.slli64 s0 + 1e84: 0360 addi s0,sp,396 + 1e86: 0900 addi s0,sp,144 + 1e88: 0004 0x4 + 1e8a: 0001 nop + 1e8c: 0402 c.slli64 s0 + 1e8e: 0360 addi s0,sp,396 + 1e90: 0900 addi s0,sp,144 + 1e92: 0000 unimp + 1e94: 0001 nop + 1e96: 0402 c.slli64 s0 + 1e98: 0662 slli a2,a2,0x18 + 1e9a: 04090003 lb zero,64(s2) + 1e9e: 0100 addi s0,sp,128 + 1ea0: 0200 addi s0,sp,256 + 1ea2: 6304 flw fs1,0(a4) + 1ea4: 0306 slli t1,t1,0x1 + 1ea6: 0900 addi s0,sp,144 + 1ea8: 0004 0x4 + 1eaa: 0001 nop + 1eac: 0402 c.slli64 s0 + 1eae: 0302 c.slli64 t1 + 1eb0: 0901 addi s2,s2,0 + 1eb2: 0004 0x4 + 1eb4: 0001 nop + 1eb6: 0402 c.slli64 s0 + 1eb8: 0302 c.slli64 t1 + 1eba: 0900 addi s0,sp,144 + 1ebc: 0004 0x4 + 1ebe: 0001 nop + 1ec0: 0402 c.slli64 s0 + 1ec2: 0306 slli t1,t1,0x1 + 1ec4: 0900 addi s0,sp,144 + 1ec6: 0004 0x4 + 1ec8: 0001 nop + 1eca: 0402 c.slli64 s0 + 1ecc: 0306 slli t1,t1,0x1 + 1ece: 0900 addi s0,sp,144 + 1ed0: 0000 unimp + 1ed2: 0001 nop + 1ed4: 0402 c.slli64 s0 + 1ed6: 0308 addi a0,sp,384 + 1ed8: 0900 addi s0,sp,144 + 1eda: 0008 0x8 + 1edc: 0001 nop + 1ede: 0402 c.slli64 s0 + 1ee0: 0308 addi a0,sp,384 + 1ee2: 0900 addi s0,sp,144 + 1ee4: 0000 unimp + 1ee6: 0001 nop + 1ee8: 0402 c.slli64 s0 + 1eea: 0308 addi a0,sp,384 + 1eec: 0900 addi s0,sp,144 + 1eee: 0000 unimp + 1ef0: 0001 nop + 1ef2: 0402 c.slli64 s0 + 1ef4: 0308 addi a0,sp,384 + 1ef6: 0900 addi s0,sp,144 + 1ef8: 0000 unimp + 1efa: 0001 nop + 1efc: 0402 c.slli64 s0 + 1efe: 030a slli t1,t1,0x2 + 1f00: 0900 addi s0,sp,144 + 1f02: 000c 0xc + 1f04: 0001 nop + 1f06: 0402 c.slli64 s0 + 1f08: 030a slli t1,t1,0x2 + 1f0a: 0900 addi s0,sp,144 + 1f0c: 0000 unimp + 1f0e: 0001 nop + 1f10: 0402 c.slli64 s0 + 1f12: 030a slli t1,t1,0x2 + 1f14: 0900 addi s0,sp,144 + 1f16: 0000 unimp + 1f18: 0001 nop + 1f1a: 0402 c.slli64 s0 + 1f1c: 030a slli t1,t1,0x2 + 1f1e: 0900 addi s0,sp,144 + 1f20: 0004 0x4 + 1f22: 0001 nop + 1f24: 0402 c.slli64 s0 + 1f26: 030a slli t1,t1,0x2 + 1f28: 0900 addi s0,sp,144 + 1f2a: 0008 0x8 + 1f2c: 0001 nop + 1f2e: 0402 c.slli64 s0 + 1f30: 0309 addi t1,t1,2 + 1f32: 0900 addi s0,sp,144 + 1f34: 0004 0x4 + 1f36: 0001 nop + 1f38: 0402 c.slli64 s0 + 1f3a: 0309 addi t1,t1,2 + 1f3c: 0900 addi s0,sp,144 + 1f3e: 0000 unimp + 1f40: 0001 nop + 1f42: 0402 c.slli64 s0 + 1f44: 0318 addi a4,sp,384 + 1f46: 0900 addi s0,sp,144 + 1f48: 0008 0x8 + 1f4a: 0001 nop + 1f4c: 0402 c.slli64 s0 + 1f4e: 0318 addi a4,sp,384 + 1f50: 0900 addi s0,sp,144 + 1f52: 000c 0xc + 1f54: 0001 nop + 1f56: 0402 c.slli64 s0 + 1f58: 031a slli t1,t1,0x6 + 1f5a: 0900 addi s0,sp,144 + 1f5c: 0004 0x4 + 1f5e: 0001 nop + 1f60: 0402 c.slli64 s0 + 1f62: 031a slli t1,t1,0x6 + 1f64: 0900 addi s0,sp,144 + 1f66: 0000 unimp + 1f68: 0001 nop + 1f6a: 0402 c.slli64 s0 + 1f6c: 031a slli t1,t1,0x6 + 1f6e: 0900 addi s0,sp,144 + 1f70: 0000 unimp + 1f72: 0001 nop + 1f74: 0402 c.slli64 s0 + 1f76: 031a slli t1,t1,0x6 + 1f78: 0900 addi s0,sp,144 + 1f7a: 0000 unimp + 1f7c: 0601 addi a2,a2,0 + 1f7e: 08090003 lb zero,128(s2) + 1f82: 0100 addi s0,sp,128 + 1f84: 0200 addi s0,sp,256 + 1f86: 7704 flw fs1,40(a4) + 1f88: 0306 slli t1,t1,0x1 + 1f8a: 0900 addi s0,sp,144 + 1f8c: 0010 0x10 + 1f8e: 0001 nop + 1f90: 0402 c.slli64 s0 + 1f92: 09000377 0x9000377 + 1f96: 0000 unimp + 1f98: 0001 nop + 1f9a: 0402 c.slli64 s0 + 1f9c: 09000377 0x9000377 + 1fa0: 0000 unimp + 1fa2: 0001 nop + 1fa4: 0402 c.slli64 s0 + 1fa6: 09000377 0x9000377 + 1faa: 0000 unimp + 1fac: 0001 nop + 1fae: 0402 c.slli64 s0 + 1fb0: 09000377 0x9000377 + 1fb4: 0000 unimp + 1fb6: 0001 nop + 1fb8: 0402 c.slli64 s0 + 1fba: 09000377 0x9000377 + 1fbe: 0000 unimp + 1fc0: 0001 nop + 1fc2: 0402 c.slli64 s0 + 1fc4: 09000377 0x9000377 + 1fc8: 0000 unimp + 1fca: 0001 nop + 1fcc: 0402 c.slli64 s0 + 1fce: 09000377 0x9000377 + 1fd2: 0000 unimp + 1fd4: 0501 addi a0,a0,0 + 1fd6: 0001 nop + 1fd8: 0402 c.slli64 s0 + 1fda: 04030677 0x4030677 + 1fde: 0c09 addi s8,s8,2 + 1fe0: 0100 addi s0,sp,128 + 1fe2: 0305 addi t1,t1,1 + 1fe4: 0200 addi s0,sp,256 + 1fe6: 7704 flw fs1,40(a4) + 1fe8: 08097c03 0x8097c03 + 1fec: 0100 addi s0,sp,128 + 1fee: 0200 addi s0,sp,256 + 1ff0: 7704 flw fs1,40(a4) + 1ff2: 0306 slli t1,t1,0x1 + 1ff4: 0900 addi s0,sp,144 + 1ff6: 0014 0x14 + 1ff8: 0001 nop + 1ffa: 0402 c.slli64 s0 + 1ffc: 09000377 0x9000377 + 2000: 0000 unimp + 2002: 0001 nop + 2004: 0402 c.slli64 s0 + 2006: 09010377 0x9010377 + 200a: 0000 unimp + 200c: 0001 nop + 200e: 0402 c.slli64 s0 + 2010: 09000377 0x9000377 + 2014: 0000 unimp + 2016: 0001 nop + 2018: 0402 c.slli64 s0 + 201a: 09000377 0x9000377 + 201e: 0000 unimp + 2020: 0001 nop + 2022: 0402 c.slli64 s0 + 2024: 09020377 0x9020377 + 2028: 0000 unimp + 202a: 0501 addi a0,a0,0 + 202c: 0001 nop + 202e: 0402 c.slli64 s0 + 2030: 01030677 0x1030677 + 2034: 0009 c.nop 2 + 2036: 0100 addi s0,sp,128 + 2038: 0305 addi t1,t1,1 + 203a: 0200 addi s0,sp,256 + 203c: 0f04 addi s1,sp,912 + 203e: 0306 slli t1,t1,0x1 + 2040: 0030097b 0x30097b + 2044: 0001 nop + 2046: 0402 c.slli64 s0 + 2048: 0900030f 0x900030f + 204c: 0004 0x4 + 204e: 0001 nop + 2050: 0402 c.slli64 s0 + 2052: 0900030f 0x900030f + 2056: 0000 unimp + 2058: 0001 nop + 205a: 0402 c.slli64 s0 + 205c: 0900030f 0x900030f + 2060: 0000 unimp + 2062: 0001 nop + 2064: 0402 c.slli64 s0 + 2066: 0608 addi a0,sp,768 + 2068: 08097e03 0x8097e03 + 206c: 0100 addi s0,sp,128 + 206e: 0200 addi s0,sp,256 + 2070: 0804 addi s1,sp,16 + 2072: 0306 slli t1,t1,0x1 + 2074: 0902 c.slli64 s2 + 2076: 0004 0x4 + 2078: 0001 nop + 207a: 0402 c.slli64 s0 + 207c: 0308 addi a0,sp,384 + 207e: 0900 addi s0,sp,144 + 2080: 0000 unimp + 2082: 0001 nop + 2084: 0402 c.slli64 s0 + 2086: 0308 addi a0,sp,384 + 2088: 0900 addi s0,sp,144 + 208a: 0000 unimp + 208c: 0001 nop + 208e: 0402 c.slli64 s0 + 2090: 0308 addi a0,sp,384 + 2092: 0900 addi s0,sp,144 + 2094: 0000 unimp + 2096: 0001 nop + 2098: 0402 c.slli64 s0 + 209a: 036c addi a1,sp,396 + 209c: 0900 addi s0,sp,144 + 209e: 000c 0xc + 20a0: 0001 nop + 20a2: 0402 c.slli64 s0 + 20a4: 036c addi a1,sp,396 + 20a6: 0901 addi s2,s2,0 + 20a8: 0000 unimp + 20aa: 0001 nop + 20ac: 0402 c.slli64 s0 + 20ae: 036c addi a1,sp,396 + 20b0: 0900 addi s0,sp,144 + 20b2: 0000 unimp + 20b4: 0001 nop + 20b6: 0402 c.slli64 s0 + 20b8: 036c addi a1,sp,396 + 20ba: 0900 addi s0,sp,144 + 20bc: 0000 unimp + 20be: 0601 addi a2,a2,0 + 20c0: 08090003 lb zero,128(s2) + 20c4: 0100 addi s0,sp,128 + 20c6: 0200 addi s0,sp,256 + 20c8: 0504 addi s1,sp,640 + 20ca: 20097e03 0x20097e03 + 20ce: 0100 addi s0,sp,128 + 20d0: 0200 addi s0,sp,256 + 20d2: 0504 addi s1,sp,640 + 20d4: 0306 slli t1,t1,0x1 + 20d6: 0901 addi s2,s2,0 + 20d8: 0004 0x4 + 20da: 0001 nop + 20dc: 0402 c.slli64 s0 + 20de: 0305 addi t1,t1,1 + 20e0: 0900 addi s0,sp,144 + 20e2: 0000 unimp + 20e4: 0001 nop + 20e6: 0402 c.slli64 s0 + 20e8: 0305 addi t1,t1,1 + 20ea: 0900 addi s0,sp,144 + 20ec: 0000 unimp + 20ee: 0001 nop + 20f0: 0402 c.slli64 s0 + 20f2: 0305 addi t1,t1,1 + 20f4: 0900 addi s0,sp,144 + 20f6: 0000 unimp + 20f8: 0601 addi a2,a2,0 + 20fa: 04090003 lb zero,64(s2) + 20fe: 0100 addi s0,sp,128 + 2100: 0200 addi s0,sp,256 + 2102: 3b04 fld fs1,48(a4) + 2104: 0306 slli t1,t1,0x1 + 2106: 0901 addi s2,s2,0 + 2108: 0014 0x14 + 210a: 0001 nop + 210c: 0402 c.slli64 s0 + 210e: 0900033b 0x900033b + 2112: 0000 unimp + 2114: 0001 nop + 2116: 0402 c.slli64 s0 + 2118: 0900033b 0x900033b + 211c: 0000 unimp + 211e: 0001 nop + 2120: 0402 c.slli64 s0 + 2122: 0900033b 0x900033b + 2126: 0008 0x8 + 2128: 0001 nop + 212a: 0402 c.slli64 s0 + 212c: 033c addi a5,sp,392 + 212e: 0900 addi s0,sp,144 + 2130: 0008 0x8 + 2132: 0001 nop + 2134: 0402 c.slli64 s0 + 2136: 033e slli t1,t1,0xf + 2138: 0900 addi s0,sp,144 + 213a: 0008 0x8 + 213c: 0001 nop + 213e: 0402 c.slli64 s0 + 2140: 033e slli t1,t1,0xf + 2142: 0900 addi s0,sp,144 + 2144: 001c 0x1c + 2146: 0001 nop + 2148: 0402 c.slli64 s0 + 214a: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne + 214e: 0004 0x4 + 2150: 0001 nop + 2152: 0402 c.slli64 s0 + 2154: 0900034b fnmsub.s ft6,ft0,fa6,ft1,rne + 2158: 0000 unimp + 215a: 0001 nop + 215c: 0402 c.slli64 s0 + 215e: 034c addi a1,sp,388 + 2160: 0900 addi s0,sp,144 + 2162: 0008 0x8 + 2164: 0001 nop + 2166: 0402 c.slli64 s0 + 2168: 034c addi a1,sp,388 + 216a: 0900 addi s0,sp,144 + 216c: 0000 unimp + 216e: 0001 nop + 2170: 0402 c.slli64 s0 + 2172: 034c addi a1,sp,388 + 2174: 0900 addi s0,sp,144 + 2176: 0000 unimp + 2178: 0001 nop + 217a: 0402 c.slli64 s0 + 217c: 034c addi a1,sp,388 + 217e: 0900 addi s0,sp,144 + 2180: 0000 unimp + 2182: 0001 nop + 2184: 0402 c.slli64 s0 + 2186: 034e slli t1,t1,0x13 + 2188: 0900 addi s0,sp,144 + 218a: 000c 0xc + 218c: 0001 nop + 218e: 0402 c.slli64 s0 + 2190: 034e slli t1,t1,0x13 + 2192: 0900 addi s0,sp,144 + 2194: 0000 unimp + 2196: 0001 nop + 2198: 0402 c.slli64 s0 + 219a: 034e slli t1,t1,0x13 + 219c: 0900 addi s0,sp,144 + 219e: 0000 unimp + 21a0: 0001 nop + 21a2: 0402 c.slli64 s0 + 21a4: 034e slli t1,t1,0x13 + 21a6: 0900 addi s0,sp,144 + 21a8: 0004 0x4 + 21aa: 0001 nop + 21ac: 0402 c.slli64 s0 + 21ae: 034e slli t1,t1,0x13 + 21b0: 0900 addi s0,sp,144 + 21b2: 0008 0x8 + 21b4: 0001 nop + 21b6: 0402 c.slli64 s0 + 21b8: 034d addi t1,t1,19 + 21ba: 0900 addi s0,sp,144 + 21bc: 0004 0x4 + 21be: 0001 nop + 21c0: 0402 c.slli64 s0 + 21c2: 034d addi t1,t1,19 + 21c4: 0900 addi s0,sp,144 + 21c6: 0000 unimp + 21c8: 0001 nop + 21ca: 0402 c.slli64 s0 + 21cc: 035d addi t1,t1,23 + 21ce: 0900 addi s0,sp,144 + 21d0: 0008 0x8 + 21d2: 0001 nop + 21d4: 0402 c.slli64 s0 + 21d6: 035d addi t1,t1,23 + 21d8: 0900 addi s0,sp,144 + 21da: 0000 unimp + 21dc: 0001 nop + 21de: 0402 c.slli64 s0 + 21e0: 035d addi t1,t1,23 + 21e2: 0900 addi s0,sp,144 + 21e4: 0000 unimp + 21e6: 0001 nop + 21e8: 0402 c.slli64 s0 + 21ea: 035d addi t1,t1,23 + 21ec: 0900 addi s0,sp,144 + 21ee: 000c 0xc + 21f0: 0601 addi a2,a2,0 + 21f2: 04090003 lb zero,64(s2) + 21f6: 0100 addi s0,sp,128 + 21f8: 0200 addi s0,sp,256 + 21fa: 3f04 fld fs1,56(a4) + 21fc: 0306 slli t1,t1,0x1 + 21fe: 0900 addi s0,sp,144 + 2200: 0008 0x8 + 2202: 0001 nop + 2204: 0402 c.slli64 s0 + 2206: 00030647 fmsub.s fa2,ft6,ft0,ft0,rne + 220a: 1809 addi a6,a6,-30 + 220c: 0100 addi s0,sp,128 + 220e: 0200 addi s0,sp,256 + 2210: 4a04 lw s1,16(a2) + 2212: 08090003 lb zero,128(s2) + 2216: 0100 addi s0,sp,128 + 2218: 0200 addi s0,sp,256 + 221a: 4a04 lw s1,16(a2) + 221c: 0306 slli t1,t1,0x1 + 221e: 0900 addi s0,sp,144 + 2220: 000c 0xc + 2222: 0601 addi a2,a2,0 + 2224: 08090003 lb zero,128(s2) + 2228: 0100 addi s0,sp,128 + 222a: 30097f03 0x30097f03 + 222e: 0100 addi s0,sp,128 + 2230: 0306 slli t1,t1,0x1 + 2232: 0900 addi s0,sp,144 + 2234: 0004 0x4 + 2236: 0301 addi t1,t1,0 + 2238: 0900 addi s0,sp,144 + 223a: 0000 unimp + 223c: 0901 addi s2,s2,0 + 223e: 0008 0x8 + 2240: 0100 addi s0,sp,128 + 2242: d201 beqz a2,2142 <_start-0x7fffdebe> + 2244: 000d c.nop 3 + 2246: 0300 addi s0,sp,384 + 2248: 9300 0x9300 + 224a: 0000 unimp + 224c: 0100 addi s0,sp,128 + 224e: fb01 bnez a4,215e <_start-0x7fffdea2> + 2250: 0d0e slli s10,s10,0x3 + 2252: 0100 addi s0,sp,128 + 2254: 0101 addi sp,sp,0 2256: 0001 nop - 2258: 0402 c.slli64 s0 - 225a: 00030647 fmsub.s fa2,ft6,ft0,ft0,rne - 225e: 1809 addi a6,a6,-30 - 2260: 0100 addi s0,sp,128 - 2262: 0200 addi s0,sp,256 - 2264: 4a04 lw s1,16(a2) - 2266: 08090003 lb zero,128(s2) - 226a: 0100 addi s0,sp,128 - 226c: 0200 addi s0,sp,256 - 226e: 4a04 lw s1,16(a2) - 2270: 0306 slli t1,t1,0x1 - 2272: 0900 addi s0,sp,144 - 2274: 000c 0xc - 2276: 0601 addi a2,a2,0 - 2278: 08090003 lb zero,128(s2) - 227c: 0100 addi s0,sp,128 - 227e: 30097f03 0x30097f03 - 2282: 0100 addi s0,sp,128 - 2284: 0306 slli t1,t1,0x1 - 2286: 0900 addi s0,sp,144 - 2288: 0004 0x4 - 228a: 0301 addi t1,t1,0 - 228c: 0900 addi s0,sp,144 - 228e: 0000 unimp - 2290: 0901 addi s2,s2,0 - 2292: 0008 0x8 - 2294: 0100 addi s0,sp,128 - 2296: d201 beqz a2,2196 <_start-0x7fffde6a> - 2298: 000d c.nop 3 - 229a: 0300 addi s0,sp,384 - 229c: 9300 0x9300 - 229e: 0000 unimp - 22a0: 0100 addi s0,sp,128 - 22a2: fb01 bnez a4,21b2 <_start-0x7fffde4e> - 22a4: 0d0e slli s10,s10,0x3 - 22a6: 0100 addi s0,sp,128 - 22a8: 0101 addi sp,sp,0 - 22aa: 0001 nop - 22ac: 0000 unimp - 22ae: 0001 nop - 22b0: 0100 addi s0,sp,128 - 22b2: 2e2e fld ft8,200(sp) - 22b4: 2f2e2e2f 0x2f2e2e2f - 22b8: 2e2e fld ft8,200(sp) - 22ba: 2f2e2e2f 0x2f2e2e2f - 22be: 6972 flw fs2,28(sp) - 22c0: 2d766373 csrrsi t1,0x2d7,12 - 22c4: 2f636367 0x2f636367 - 22c8: 696c flw fa1,84(a0) - 22ca: 6762 flw fa4,24(sp) - 22cc: 732f6363 bltu t5,s2,29f2 <_start-0x7fffd60e> - 22d0: 2d74666f jal a2,48da6 <_start-0x7ffb725a> - 22d4: 7066 flw ft0,120(sp) - 22d6: 2e00 fld fs0,24(a2) - 22d8: 2f2e fld ft10,200(sp) - 22da: 2e2e fld ft8,200(sp) - 22dc: 2f2e2e2f 0x2f2e2e2f - 22e0: 2e2e fld ft8,200(sp) - 22e2: 7369722f 0x7369722f - 22e6: 672d7663 bgeu s10,s2,2952 <_start-0x7fffd6ae> - 22ea: 6c2f6363 bltu t5,sp,29b0 <_start-0x7fffd650> - 22ee: 6269 lui tp,0x1a - 22f0: 2f636367 0x2f636367 - 22f4: 2e2e fld ft8,200(sp) - 22f6: 636e692f 0x636e692f - 22fa: 756c flw fa1,108(a0) - 22fc: 6564 flw fs1,76(a0) - 22fe: 0000 unimp - 2300: 756d lui a0,0xffffb - 2302: 646c flw fa1,76(s0) - 2304: 3366 fld ft6,120(sp) - 2306: 632e flw ft6,200(sp) + 2258: 0000 unimp + 225a: 0001 nop + 225c: 0100 addi s0,sp,128 + 225e: 2e2e fld ft8,200(sp) + 2260: 2f2e2e2f 0x2f2e2e2f + 2264: 2e2e fld ft8,200(sp) + 2266: 2f2e2e2f 0x2f2e2e2f + 226a: 6972 flw fs2,28(sp) + 226c: 2d766373 csrrsi t1,0x2d7,12 + 2270: 2f636367 0x2f636367 + 2274: 696c flw fa1,84(a0) + 2276: 6762 flw fa4,24(sp) + 2278: 732f6363 bltu t5,s2,299e <_start-0x7fffd662> + 227c: 2d74666f jal a2,48d52 <_start-0x7ffb72ae> + 2280: 7066 flw ft0,120(sp) + 2282: 2e00 fld fs0,24(a2) + 2284: 2f2e fld ft10,200(sp) + 2286: 2e2e fld ft8,200(sp) + 2288: 2f2e2e2f 0x2f2e2e2f + 228c: 2e2e fld ft8,200(sp) + 228e: 7369722f 0x7369722f + 2292: 672d7663 bgeu s10,s2,28fe <_start-0x7fffd702> + 2296: 6c2f6363 bltu t5,sp,295c <_start-0x7fffd6a4> + 229a: 6269 lui tp,0x1a + 229c: 2f636367 0x2f636367 + 22a0: 2e2e fld ft8,200(sp) + 22a2: 636e692f 0x636e692f + 22a6: 756c flw fa1,108(a0) + 22a8: 6564 flw fs1,76(a0) + 22aa: 0000 unimp + 22ac: 756d lui a0,0xffffb + 22ae: 646c flw fa1,76(s0) + 22b0: 3366 fld ft6,120(sp) + 22b2: 632e flw ft6,200(sp) + 22b4: 0100 addi s0,sp,128 + 22b6: 0000 unimp + 22b8: 74666f73 csrrsi t5,0x746,12 + 22bc: 662d lui a2,0xb + 22be: 2e70 fld fa2,216(a2) + 22c0: 0068 addi a0,sp,12 + 22c2: 0001 nop + 22c4: 6400 flw fs0,8(s0) + 22c6: 6c62756f jal a0,2998c <_start-0x7ffd6674> + 22ca: 2e65 jal 2682 <_start-0x7fffd97e> + 22cc: 0068 addi a0,sp,12 + 22ce: 0001 nop + 22d0: 6c00 flw fs0,24(s0) + 22d2: 6c676e6f jal t3,78998 <_start-0x7ff87668> + 22d6: 2e676e6f jal t3,785bc <_start-0x7ff87a44> + 22da: 0068 addi a0,sp,12 + 22dc: 0002 c.slli64 zero + 22de: 0000 unimp + 22e0: 0105 addi sp,sp,1 + 22e2: 0500 addi s0,sp,640 + 22e4: e802 fsw ft0,16(sp) + 22e6: 03800113 li sp,56 + 22ea: 03050123 sb a6,34(a0) # ffffb022 <__BSS_END__+0x7ffe43e6> + 22ee: 00090103 lb sp,0(s2) + 22f2: 0100 addi s0,sp,128 + 22f4: 00090003 lb zero,0(s2) + 22f8: 0100 addi s0,sp,128 + 22fa: 0d05 addi s10,s10,1 + 22fc: 00090003 lb zero,0(s2) + 2300: 0100 addi s0,sp,128 + 2302: 0305 addi t1,t1,1 + 2304: 00090103 lb sp,0(s2) 2308: 0100 addi s0,sp,128 - 230a: 0000 unimp - 230c: 74666f73 csrrsi t5,0x746,12 - 2310: 662d lui a2,0xb - 2312: 2e70 fld fa2,216(a2) - 2314: 0068 addi a0,sp,12 - 2316: 0001 nop - 2318: 6400 flw fs0,8(s0) - 231a: 6c62756f jal a0,299e0 <_start-0x7ffd6620> - 231e: 2e65 jal 26d6 <_start-0x7fffd92a> - 2320: 0068 addi a0,sp,12 - 2322: 0001 nop - 2324: 6c00 flw fs0,24(s0) - 2326: 6c676e6f jal t3,789ec <_start-0x7ff87614> - 232a: 2e676e6f jal t3,78610 <_start-0x7ff879f0> - 232e: 0068 addi a0,sp,12 - 2330: 0002 c.slli64 zero - 2332: 0000 unimp - 2334: 0105 addi sp,sp,1 - 2336: 0500 addi s0,sp,640 - 2338: 2402 fld fs0,0(sp) - 233a: 03800113 li sp,56 - 233e: 03050123 sb a6,34(a0) # ffffb022 <__BSS_END__+0x7ffe43f2> - 2342: 00090103 lb sp,0(s2) - 2346: 0100 addi s0,sp,128 - 2348: 00090003 lb zero,0(s2) - 234c: 0100 addi s0,sp,128 - 234e: 0d05 addi s10,s10,1 - 2350: 00090003 lb zero,0(s2) - 2354: 0100 addi s0,sp,128 - 2356: 0305 addi t1,t1,1 + 230a: 00090003 lb zero,0(s2) + 230e: 0100 addi s0,sp,128 + 2310: 00090003 lb zero,0(s2) + 2314: 0100 addi s0,sp,128 + 2316: 00090003 lb zero,0(s2) + 231a: 0100 addi s0,sp,128 + 231c: 00090103 lb sp,0(s2) + 2320: 0100 addi s0,sp,128 + 2322: 00090003 lb zero,0(s2) + 2326: 0100 addi s0,sp,128 + 2328: 00090003 lb zero,0(s2) + 232c: 0100 addi s0,sp,128 + 232e: 00090003 lb zero,0(s2) + 2332: 0100 addi s0,sp,128 + 2334: 00090103 lb sp,0(s2) + 2338: 0100 addi s0,sp,128 + 233a: 00090003 lb zero,0(s2) + 233e: 0100 addi s0,sp,128 + 2340: 00090003 lb zero,0(s2) + 2344: 0100 addi s0,sp,128 + 2346: 00090003 lb zero,0(s2) + 234a: 0100 addi s0,sp,128 + 234c: 00090103 lb sp,0(s2) + 2350: 0100 addi s0,sp,128 + 2352: 00090203 lb tp,0(s2) + 2356: 0100 addi s0,sp,128 2358: 00090103 lb sp,0(s2) 235c: 0100 addi s0,sp,128 235e: 00090003 lb zero,0(s2) @@ -45143,2518 +45179,2518 @@ Disassembly of section .debug_line: 2368: 0100 addi s0,sp,128 236a: 00090003 lb zero,0(s2) 236e: 0100 addi s0,sp,128 - 2370: 00090103 lb sp,0(s2) + 2370: 00090003 lb zero,0(s2) 2374: 0100 addi s0,sp,128 2376: 00090003 lb zero,0(s2) 237a: 0100 addi s0,sp,128 - 237c: 00090003 lb zero,0(s2) - 2380: 0100 addi s0,sp,128 - 2382: 00090003 lb zero,0(s2) - 2386: 0100 addi s0,sp,128 - 2388: 00090103 lb sp,0(s2) - 238c: 0100 addi s0,sp,128 - 238e: 00090003 lb zero,0(s2) - 2392: 0100 addi s0,sp,128 - 2394: 00090003 lb zero,0(s2) - 2398: 0100 addi s0,sp,128 - 239a: 00090003 lb zero,0(s2) - 239e: 0100 addi s0,sp,128 - 23a0: 00090103 lb sp,0(s2) - 23a4: 0100 addi s0,sp,128 - 23a6: 00090203 lb tp,0(s2) - 23aa: 0100 addi s0,sp,128 - 23ac: 00090103 lb sp,0(s2) - 23b0: 0100 addi s0,sp,128 - 23b2: 00090003 lb zero,0(s2) - 23b6: 0100 addi s0,sp,128 - 23b8: 00090003 lb zero,0(s2) - 23bc: 0100 addi s0,sp,128 - 23be: 00090003 lb zero,0(s2) + 237c: 0105 addi sp,sp,1 + 237e: 0306 slli t1,t1,0x1 + 2380: 0978 addi a4,sp,156 + 2382: 0000 unimp + 2384: 0501 addi a0,a0,0 + 2386: 09080303 lb t1,144(a6) + 238a: 0004 0x4 + 238c: 0501 addi a0,a0,0 + 238e: 0301 addi t1,t1,0 + 2390: 0978 addi a4,sp,156 + 2392: 0004 0x4 + 2394: 0501 addi a0,a0,0 + 2396: 09080303 lb t1,144(a6) + 239a: 0014 0x14 + 239c: 0501 addi a0,a0,0 + 239e: 0301 addi t1,t1,0 + 23a0: 0978 addi a4,sp,156 + 23a2: 0004 0x4 + 23a4: 0501 addi a0,a0,0 + 23a6: 09080303 lb t1,144(a6) + 23aa: 0010 0x10 + 23ac: 0501 addi a0,a0,0 + 23ae: 0301 addi t1,t1,0 + 23b0: 0978 addi a4,sp,156 + 23b2: 0004 0x4 + 23b4: 0501 addi a0,a0,0 + 23b6: 09080303 lb t1,144(a6) + 23ba: 000c 0xc + 23bc: 0601 addi a2,a2,0 + 23be: 04090003 lb zero,64(s2) 23c2: 0100 addi s0,sp,128 23c4: 00090003 lb zero,0(s2) 23c8: 0100 addi s0,sp,128 - 23ca: 00090003 lb zero,0(s2) + 23ca: 04090003 lb zero,64(s2) 23ce: 0100 addi s0,sp,128 - 23d0: 0105 addi sp,sp,1 - 23d2: 0306 slli t1,t1,0x1 - 23d4: 0978 addi a4,sp,156 - 23d6: 0000 unimp - 23d8: 0501 addi a0,a0,0 - 23da: 09080303 lb t1,144(a6) - 23de: 0004 0x4 - 23e0: 0501 addi a0,a0,0 - 23e2: 0301 addi t1,t1,0 - 23e4: 0978 addi a4,sp,156 - 23e6: 0004 0x4 - 23e8: 0501 addi a0,a0,0 - 23ea: 09080303 lb t1,144(a6) - 23ee: 0014 0x14 - 23f0: 0501 addi a0,a0,0 - 23f2: 0301 addi t1,t1,0 - 23f4: 0978 addi a4,sp,156 - 23f6: 0004 0x4 - 23f8: 0501 addi a0,a0,0 - 23fa: 09080303 lb t1,144(a6) - 23fe: 0010 0x10 - 2400: 0501 addi a0,a0,0 - 2402: 0301 addi t1,t1,0 - 2404: 0978 addi a4,sp,156 - 2406: 0004 0x4 - 2408: 0501 addi a0,a0,0 - 240a: 09080303 lb t1,144(a6) - 240e: 000c 0xc - 2410: 0601 addi a2,a2,0 + 23d0: 00090003 lb zero,0(s2) + 23d4: 0100 addi s0,sp,128 + 23d6: 00090003 lb zero,0(s2) + 23da: 0100 addi s0,sp,128 + 23dc: 0200 addi s0,sp,256 + 23de: 0104 addi s1,sp,128 + 23e0: 10090003 lb zero,256(s2) + 23e4: 0100 addi s0,sp,128 + 23e6: 0200 addi s0,sp,256 + 23e8: 0104 addi s1,sp,128 + 23ea: 00090003 lb zero,0(s2) + 23ee: 0100 addi s0,sp,128 + 23f0: 0200 addi s0,sp,256 + 23f2: 0104 addi s1,sp,128 + 23f4: 00090003 lb zero,0(s2) + 23f8: 0100 addi s0,sp,128 + 23fa: 0200 addi s0,sp,256 + 23fc: 0104 addi s1,sp,128 + 23fe: 00090003 lb zero,0(s2) + 2402: 0100 addi s0,sp,128 + 2404: 0200 addi s0,sp,256 + 2406: 0104 addi s1,sp,128 + 2408: 14090003 lb zero,320(s2) + 240c: 0100 addi s0,sp,128 + 240e: 0200 addi s0,sp,256 + 2410: 0104 addi s1,sp,128 2412: 04090003 lb zero,64(s2) 2416: 0100 addi s0,sp,128 - 2418: 00090003 lb zero,0(s2) - 241c: 0100 addi s0,sp,128 - 241e: 04090003 lb zero,64(s2) - 2422: 0100 addi s0,sp,128 - 2424: 00090003 lb zero,0(s2) - 2428: 0100 addi s0,sp,128 - 242a: 00090003 lb zero,0(s2) - 242e: 0100 addi s0,sp,128 - 2430: 0200 addi s0,sp,256 - 2432: 0104 addi s1,sp,128 - 2434: 10090003 lb zero,256(s2) - 2438: 0100 addi s0,sp,128 - 243a: 0200 addi s0,sp,256 - 243c: 0104 addi s1,sp,128 - 243e: 00090003 lb zero,0(s2) - 2442: 0100 addi s0,sp,128 - 2444: 0200 addi s0,sp,256 - 2446: 0104 addi s1,sp,128 - 2448: 00090003 lb zero,0(s2) - 244c: 0100 addi s0,sp,128 - 244e: 0200 addi s0,sp,256 - 2450: 0104 addi s1,sp,128 - 2452: 00090003 lb zero,0(s2) - 2456: 0100 addi s0,sp,128 - 2458: 0200 addi s0,sp,256 - 245a: 0104 addi s1,sp,128 - 245c: 14090003 lb zero,320(s2) - 2460: 0100 addi s0,sp,128 - 2462: 0200 addi s0,sp,256 - 2464: 0104 addi s1,sp,128 - 2466: 04090003 lb zero,64(s2) - 246a: 0100 addi s0,sp,128 - 246c: 0200 addi s0,sp,256 - 246e: 0104 addi s1,sp,128 - 2470: 00090003 lb zero,0(s2) - 2474: 0100 addi s0,sp,128 - 2476: 0200 addi s0,sp,256 - 2478: 0104 addi s1,sp,128 - 247a: 04090003 lb zero,64(s2) - 247e: 0100 addi s0,sp,128 - 2480: 0200 addi s0,sp,256 - 2482: 0104 addi s1,sp,128 - 2484: 00090003 lb zero,0(s2) - 2488: 0100 addi s0,sp,128 - 248a: 0200 addi s0,sp,256 - 248c: 2904 fld fs1,16(a0) - 248e: 00090003 lb zero,0(s2) - 2492: 0100 addi s0,sp,128 - 2494: 0200 addi s0,sp,256 - 2496: 2904 fld fs1,16(a0) - 2498: 00090003 lb zero,0(s2) - 249c: 0100 addi s0,sp,128 - 249e: 0200 addi s0,sp,256 - 24a0: 0804 addi s1,sp,16 - 24a2: 04090003 lb zero,64(s2) - 24a6: 0100 addi s0,sp,128 - 24a8: 0200 addi s0,sp,256 - 24aa: 0804 addi s1,sp,16 - 24ac: 00090003 lb zero,0(s2) - 24b0: 0100 addi s0,sp,128 - 24b2: 0200 addi s0,sp,256 - 24b4: 0804 addi s1,sp,16 - 24b6: 00090103 lb sp,0(s2) - 24ba: 0100 addi s0,sp,128 - 24bc: 0200 addi s0,sp,256 - 24be: 0804 addi s1,sp,16 - 24c0: 00090003 lb zero,0(s2) - 24c4: 0100 addi s0,sp,128 - 24c6: 0200 addi s0,sp,256 - 24c8: 0804 addi s1,sp,16 - 24ca: 00090003 lb zero,0(s2) - 24ce: 0100 addi s0,sp,128 - 24d0: 0200 addi s0,sp,256 - 24d2: 0804 addi s1,sp,16 - 24d4: 00090003 lb zero,0(s2) - 24d8: 0100 addi s0,sp,128 - 24da: 0200 addi s0,sp,256 - 24dc: 0804 addi s1,sp,16 - 24de: 00090003 lb zero,0(s2) - 24e2: 0100 addi s0,sp,128 - 24e4: 0200 addi s0,sp,256 - 24e6: 0804 addi s1,sp,16 - 24e8: 00090003 lb zero,0(s2) - 24ec: 0100 addi s0,sp,128 - 24ee: 0200 addi s0,sp,256 - 24f0: 0804 addi s1,sp,16 - 24f2: 10090003 lb zero,256(s2) - 24f6: 0100 addi s0,sp,128 - 24f8: 0200 addi s0,sp,256 - 24fa: 0804 addi s1,sp,16 - 24fc: 04090003 lb zero,64(s2) - 2500: 0100 addi s0,sp,128 - 2502: 0200 addi s0,sp,256 - 2504: 0804 addi s1,sp,16 - 2506: 04090003 lb zero,64(s2) - 250a: 0100 addi s0,sp,128 - 250c: 0200 addi s0,sp,256 - 250e: 0804 addi s1,sp,16 - 2510: 00090003 lb zero,0(s2) - 2514: 0100 addi s0,sp,128 - 2516: 0200 addi s0,sp,256 - 2518: 0804 addi s1,sp,16 - 251a: 00090003 lb zero,0(s2) - 251e: 0100 addi s0,sp,128 - 2520: 0306 slli t1,t1,0x1 - 2522: 0900 addi s0,sp,144 - 2524: 0004 0x4 - 2526: 0001 nop - 2528: 0402 c.slli64 s0 - 252a: 0601 addi a2,a2,0 - 252c: 08090003 lb zero,128(s2) - 2530: 0100 addi s0,sp,128 - 2532: 0200 addi s0,sp,256 - 2534: 0104 addi s1,sp,128 - 2536: 00090003 lb zero,0(s2) - 253a: 0100 addi s0,sp,128 - 253c: 0200 addi s0,sp,256 - 253e: 0104 addi s1,sp,128 - 2540: 00090003 lb zero,0(s2) - 2544: 0100 addi s0,sp,128 - 2546: 0200 addi s0,sp,256 - 2548: 0104 addi s1,sp,128 - 254a: 00090003 lb zero,0(s2) - 254e: 0100 addi s0,sp,128 - 2550: 0200 addi s0,sp,256 - 2552: 0104 addi s1,sp,128 - 2554: 14090003 lb zero,320(s2) - 2558: 0100 addi s0,sp,128 - 255a: 0200 addi s0,sp,256 - 255c: 0104 addi s1,sp,128 - 255e: 08090003 lb zero,128(s2) - 2562: 0100 addi s0,sp,128 - 2564: 0200 addi s0,sp,256 - 2566: 0104 addi s1,sp,128 - 2568: 00090003 lb zero,0(s2) - 256c: 0100 addi s0,sp,128 - 256e: 0200 addi s0,sp,256 - 2570: 0104 addi s1,sp,128 - 2572: 00090003 lb zero,0(s2) - 2576: 0100 addi s0,sp,128 - 2578: 0200 addi s0,sp,256 - 257a: 0104 addi s1,sp,128 - 257c: 00090003 lb zero,0(s2) - 2580: 0100 addi s0,sp,128 - 2582: 0200 addi s0,sp,256 - 2584: 2904 fld fs1,16(a0) - 2586: 00090003 lb zero,0(s2) - 258a: 0100 addi s0,sp,128 - 258c: 0200 addi s0,sp,256 - 258e: 2904 fld fs1,16(a0) - 2590: 00090003 lb zero,0(s2) - 2594: 0100 addi s0,sp,128 - 2596: 0200 addi s0,sp,256 - 2598: 0804 addi s1,sp,16 - 259a: 04090003 lb zero,64(s2) - 259e: 0100 addi s0,sp,128 - 25a0: 0200 addi s0,sp,256 - 25a2: 0804 addi s1,sp,16 - 25a4: 00090003 lb zero,0(s2) - 25a8: 0100 addi s0,sp,128 - 25aa: 0200 addi s0,sp,256 - 25ac: 0804 addi s1,sp,16 - 25ae: 00090103 lb sp,0(s2) - 25b2: 0100 addi s0,sp,128 - 25b4: 0200 addi s0,sp,256 - 25b6: 0804 addi s1,sp,16 - 25b8: 00090003 lb zero,0(s2) - 25bc: 0100 addi s0,sp,128 - 25be: 0200 addi s0,sp,256 - 25c0: 0804 addi s1,sp,16 - 25c2: 18090003 lb zero,384(s2) - 25c6: 0100 addi s0,sp,128 - 25c8: 0200 addi s0,sp,256 - 25ca: 0804 addi s1,sp,16 - 25cc: 04090003 lb zero,64(s2) - 25d0: 0100 addi s0,sp,128 - 25d2: 0200 addi s0,sp,256 - 25d4: 0204 addi s1,sp,256 - 25d6: 1c097e03 0x1c097e03 - 25da: 0100 addi s0,sp,128 - 25dc: 0200 addi s0,sp,256 - 25de: 0d04 addi s1,sp,656 - 25e0: 08090003 lb zero,128(s2) - 25e4: 0100 addi s0,sp,128 - 25e6: 0200 addi s0,sp,256 - 25e8: 0d04 addi s1,sp,656 - 25ea: 00090003 lb zero,0(s2) - 25ee: 0100 addi s0,sp,128 - 25f0: 0200 addi s0,sp,256 - 25f2: 0d04 addi s1,sp,656 - 25f4: 00090003 lb zero,0(s2) - 25f8: 0100 addi s0,sp,128 - 25fa: 0200 addi s0,sp,256 - 25fc: 0d04 addi s1,sp,656 - 25fe: 00090003 lb zero,0(s2) - 2602: 0100 addi s0,sp,128 - 2604: 0200 addi s0,sp,256 - 2606: 1104 addi s1,sp,160 - 2608: 04090003 lb zero,64(s2) - 260c: 0100 addi s0,sp,128 - 260e: 0200 addi s0,sp,256 - 2610: 1104 addi s1,sp,160 - 2612: 00090003 lb zero,0(s2) - 2616: 0100 addi s0,sp,128 - 2618: 0200 addi s0,sp,256 - 261a: 1104 addi s1,sp,160 - 261c: 00090003 lb zero,0(s2) - 2620: 0100 addi s0,sp,128 - 2622: 0200 addi s0,sp,256 - 2624: 1104 addi s1,sp,160 - 2626: 00090003 lb zero,0(s2) - 262a: 0100 addi s0,sp,128 - 262c: 0200 addi s0,sp,256 - 262e: 1104 addi s1,sp,160 - 2630: 08090003 lb zero,128(s2) - 2634: 0100 addi s0,sp,128 - 2636: 0200 addi s0,sp,256 - 2638: 1f04 addi s1,sp,944 - 263a: 00090003 lb zero,0(s2) - 263e: 0100 addi s0,sp,128 - 2640: 0200 addi s0,sp,256 - 2642: 1f04 addi s1,sp,944 - 2644: 00090003 lb zero,0(s2) - 2648: 0100 addi s0,sp,128 - 264a: 0200 addi s0,sp,256 - 264c: 1f04 addi s1,sp,944 - 264e: 04090003 lb zero,64(s2) - 2652: 0100 addi s0,sp,128 - 2654: 0200 addi s0,sp,256 - 2656: 2004 fld fs1,0(s0) - 2658: 08090003 lb zero,128(s2) - 265c: 0100 addi s0,sp,128 - 265e: 0200 addi s0,sp,256 - 2660: 2004 fld fs1,0(s0) - 2662: 08090003 lb zero,128(s2) - 2666: 0100 addi s0,sp,128 - 2668: 0200 addi s0,sp,256 - 266a: 2004 fld fs1,0(s0) - 266c: 10090003 lb zero,256(s2) - 2670: 0100 addi s0,sp,128 - 2672: 0200 addi s0,sp,256 - 2674: 2004 fld fs1,0(s0) - 2676: 04090003 lb zero,64(s2) - 267a: 0100 addi s0,sp,128 - 267c: 0200 addi s0,sp,256 - 267e: 2904 fld fs1,16(a0) - 2680: 00090003 lb zero,0(s2) - 2684: 0100 addi s0,sp,128 - 2686: 0200 addi s0,sp,256 - 2688: 1804 addi s1,sp,48 - 268a: 0c090003 lb zero,192(s2) - 268e: 0100 addi s0,sp,128 - 2690: 0200 addi s0,sp,256 - 2692: 1804 addi s1,sp,48 - 2694: 00090003 lb zero,0(s2) - 2698: 0100 addi s0,sp,128 - 269a: 0200 addi s0,sp,256 - 269c: 1804 addi s1,sp,48 - 269e: 00090003 lb zero,0(s2) - 26a2: 0100 addi s0,sp,128 - 26a4: 0200 addi s0,sp,256 - 26a6: 1804 addi s1,sp,48 - 26a8: 00090003 lb zero,0(s2) - 26ac: 0100 addi s0,sp,128 - 26ae: 0200 addi s0,sp,256 - 26b0: 1804 addi s1,sp,48 - 26b2: 04090003 lb zero,64(s2) - 26b6: 0100 addi s0,sp,128 - 26b8: 0200 addi s0,sp,256 - 26ba: 1804 addi s1,sp,48 - 26bc: 00090003 lb zero,0(s2) - 26c0: 0100 addi s0,sp,128 - 26c2: 0200 addi s0,sp,256 - 26c4: 2104 fld fs1,0(a0) - 26c6: 08090003 lb zero,128(s2) - 26ca: 0100 addi s0,sp,128 - 26cc: 0200 addi s0,sp,256 - 26ce: 2104 fld fs1,0(a0) - 26d0: 08090003 lb zero,128(s2) - 26d4: 0100 addi s0,sp,128 - 26d6: 0200 addi s0,sp,256 - 26d8: 0304 addi s1,sp,384 - 26da: 08090003 lb zero,128(s2) - 26de: 0100 addi s0,sp,128 - 26e0: 0306 slli t1,t1,0x1 - 26e2: 0900 addi s0,sp,144 - 26e4: 0008 0x8 - 26e6: 0001 nop - 26e8: 0402 c.slli64 s0 - 26ea: 0602 c.slli64 a2 - 26ec: 30090103 lb sp,768(s2) - 26f0: 0100 addi s0,sp,128 - 26f2: 0200 addi s0,sp,256 - 26f4: 0d04 addi s1,sp,656 - 26f6: 08090003 lb zero,128(s2) - 26fa: 0100 addi s0,sp,128 - 26fc: 0200 addi s0,sp,256 - 26fe: 0d04 addi s1,sp,656 - 2700: 00090003 lb zero,0(s2) - 2704: 0100 addi s0,sp,128 - 2706: 0200 addi s0,sp,256 - 2708: 0d04 addi s1,sp,656 - 270a: 00090003 lb zero,0(s2) - 270e: 0100 addi s0,sp,128 - 2710: 0200 addi s0,sp,256 - 2712: 0d04 addi s1,sp,656 - 2714: 00090003 lb zero,0(s2) - 2718: 0100 addi s0,sp,128 - 271a: 0200 addi s0,sp,256 - 271c: 1104 addi s1,sp,160 - 271e: 04090003 lb zero,64(s2) - 2722: 0100 addi s0,sp,128 - 2724: 0200 addi s0,sp,256 - 2726: 1104 addi s1,sp,160 - 2728: 00090003 lb zero,0(s2) - 272c: 0100 addi s0,sp,128 - 272e: 0200 addi s0,sp,256 - 2730: 1104 addi s1,sp,160 - 2732: 00090003 lb zero,0(s2) - 2736: 0100 addi s0,sp,128 - 2738: 0200 addi s0,sp,256 - 273a: 1104 addi s1,sp,160 - 273c: 00090003 lb zero,0(s2) - 2740: 0100 addi s0,sp,128 - 2742: 0200 addi s0,sp,256 - 2744: 1104 addi s1,sp,160 - 2746: 08090003 lb zero,128(s2) - 274a: 0100 addi s0,sp,128 - 274c: 0200 addi s0,sp,256 - 274e: 1f04 addi s1,sp,944 - 2750: 00090003 lb zero,0(s2) - 2754: 0100 addi s0,sp,128 - 2756: 0200 addi s0,sp,256 - 2758: 1f04 addi s1,sp,944 - 275a: 00090003 lb zero,0(s2) - 275e: 0100 addi s0,sp,128 - 2760: 0200 addi s0,sp,256 - 2762: 1f04 addi s1,sp,944 - 2764: 04090003 lb zero,64(s2) - 2768: 0100 addi s0,sp,128 - 276a: 0200 addi s0,sp,256 - 276c: 2004 fld fs1,0(s0) - 276e: 08090003 lb zero,128(s2) - 2772: 0100 addi s0,sp,128 - 2774: 0200 addi s0,sp,256 - 2776: 2004 fld fs1,0(s0) - 2778: 08090003 lb zero,128(s2) - 277c: 0100 addi s0,sp,128 - 277e: 0200 addi s0,sp,256 - 2780: 2004 fld fs1,0(s0) - 2782: 10090003 lb zero,256(s2) - 2786: 0100 addi s0,sp,128 - 2788: 0200 addi s0,sp,256 - 278a: 2004 fld fs1,0(s0) - 278c: 04090003 lb zero,64(s2) - 2790: 0100 addi s0,sp,128 - 2792: 0200 addi s0,sp,256 - 2794: 2904 fld fs1,16(a0) - 2796: 00090003 lb zero,0(s2) - 279a: 0100 addi s0,sp,128 - 279c: 0200 addi s0,sp,256 - 279e: 1804 addi s1,sp,48 - 27a0: 0c090003 lb zero,192(s2) - 27a4: 0100 addi s0,sp,128 - 27a6: 0200 addi s0,sp,256 - 27a8: 1804 addi s1,sp,48 - 27aa: 00090003 lb zero,0(s2) - 27ae: 0100 addi s0,sp,128 - 27b0: 0200 addi s0,sp,256 - 27b2: 1804 addi s1,sp,48 - 27b4: 00090003 lb zero,0(s2) - 27b8: 0100 addi s0,sp,128 - 27ba: 0200 addi s0,sp,256 - 27bc: 1804 addi s1,sp,48 - 27be: 00090003 lb zero,0(s2) - 27c2: 0100 addi s0,sp,128 - 27c4: 0200 addi s0,sp,256 - 27c6: 1804 addi s1,sp,48 - 27c8: 08090003 lb zero,128(s2) - 27cc: 0100 addi s0,sp,128 - 27ce: 0200 addi s0,sp,256 - 27d0: 1804 addi s1,sp,48 - 27d2: 00090003 lb zero,0(s2) - 27d6: 0100 addi s0,sp,128 - 27d8: 0200 addi s0,sp,256 - 27da: 2104 fld fs1,0(a0) - 27dc: 08090003 lb zero,128(s2) - 27e0: 0100 addi s0,sp,128 - 27e2: 0200 addi s0,sp,256 - 27e4: 2104 fld fs1,0(a0) - 27e6: 08090003 lb zero,128(s2) - 27ea: 0100 addi s0,sp,128 - 27ec: 0200 addi s0,sp,256 - 27ee: 0304 addi s1,sp,384 - 27f0: 08090003 lb zero,128(s2) - 27f4: 0100 addi s0,sp,128 - 27f6: 0306 slli t1,t1,0x1 - 27f8: 0900 addi s0,sp,144 - 27fa: 0008 0x8 - 27fc: 0001 nop - 27fe: 0402 c.slli64 s0 - 2800: 0602 c.slli64 a2 - 2802: 30090103 lb sp,768(s2) - 2806: 0100 addi s0,sp,128 - 2808: 0200 addi s0,sp,256 - 280a: 0204 addi s1,sp,256 - 280c: 00090003 lb zero,0(s2) - 2810: 0100 addi s0,sp,128 - 2812: 0200 addi s0,sp,256 - 2814: 0204 addi s1,sp,256 - 2816: 00090003 lb zero,0(s2) - 281a: 0100 addi s0,sp,128 - 281c: 0200 addi s0,sp,256 - 281e: 0204 addi s1,sp,256 - 2820: 00090003 lb zero,0(s2) - 2824: 0100 addi s0,sp,128 - 2826: 0200 addi s0,sp,256 - 2828: 0204 addi s1,sp,256 - 282a: 00090003 lb zero,0(s2) - 282e: 0100 addi s0,sp,128 - 2830: 0200 addi s0,sp,256 - 2832: 0204 addi s1,sp,256 - 2834: 00090003 lb zero,0(s2) - 2838: 0100 addi s0,sp,128 - 283a: 0200 addi s0,sp,256 - 283c: 0204 addi s1,sp,256 - 283e: 00090003 lb zero,0(s2) - 2842: 0100 addi s0,sp,128 - 2844: 0200 addi s0,sp,256 - 2846: 0204 addi s1,sp,256 - 2848: 00090003 lb zero,0(s2) - 284c: 0100 addi s0,sp,128 - 284e: 0200 addi s0,sp,256 - 2850: 0204 addi s1,sp,256 - 2852: 00090003 lb zero,0(s2) - 2856: 0100 addi s0,sp,128 - 2858: 0200 addi s0,sp,256 - 285a: 0204 addi s1,sp,256 - 285c: 00090003 lb zero,0(s2) - 2860: 0100 addi s0,sp,128 - 2862: 0200 addi s0,sp,256 - 2864: 0204 addi s1,sp,256 - 2866: 00090003 lb zero,0(s2) - 286a: 0100 addi s0,sp,128 - 286c: 0200 addi s0,sp,256 - 286e: 0204 addi s1,sp,256 - 2870: 0c090003 lb zero,192(s2) - 2874: 0100 addi s0,sp,128 - 2876: 0200 addi s0,sp,256 - 2878: 0204 addi s1,sp,256 - 287a: 00090003 lb zero,0(s2) - 287e: 0100 addi s0,sp,128 - 2880: 0200 addi s0,sp,256 - 2882: 0204 addi s1,sp,256 - 2884: 04090003 lb zero,64(s2) - 2888: 0100 addi s0,sp,128 - 288a: 0200 addi s0,sp,256 - 288c: 0204 addi s1,sp,256 - 288e: 10090003 lb zero,256(s2) - 2892: 0100 addi s0,sp,128 - 2894: 0200 addi s0,sp,256 - 2896: 0204 addi s1,sp,256 - 2898: 00090003 lb zero,0(s2) - 289c: 0100 addi s0,sp,128 - 289e: 0200 addi s0,sp,256 - 28a0: 0204 addi s1,sp,256 - 28a2: 04090003 lb zero,64(s2) - 28a6: 0100 addi s0,sp,128 - 28a8: 0200 addi s0,sp,256 - 28aa: 0204 addi s1,sp,256 - 28ac: 10090003 lb zero,256(s2) - 28b0: 0100 addi s0,sp,128 - 28b2: 0200 addi s0,sp,256 - 28b4: 0204 addi s1,sp,256 - 28b6: 00090003 lb zero,0(s2) - 28ba: 0100 addi s0,sp,128 - 28bc: 0200 addi s0,sp,256 - 28be: 0204 addi s1,sp,256 - 28c0: 00090003 lb zero,0(s2) - 28c4: 0100 addi s0,sp,128 - 28c6: 0200 addi s0,sp,256 - 28c8: 0904 addi s1,sp,144 - 28ca: 04090003 lb zero,64(s2) - 28ce: 0100 addi s0,sp,128 - 28d0: 0200 addi s0,sp,256 - 28d2: 0b04 addi s1,sp,400 - 28d4: 04090003 lb zero,64(s2) - 28d8: 0100 addi s0,sp,128 - 28da: 0200 addi s0,sp,256 - 28dc: 0b04 addi s1,sp,400 - 28de: 04090003 lb zero,64(s2) - 28e2: 0100 addi s0,sp,128 - 28e4: 0200 addi s0,sp,256 - 28e6: 0b04 addi s1,sp,400 - 28e8: 18090003 lb zero,384(s2) - 28ec: 0100 addi s0,sp,128 - 28ee: 0200 addi s0,sp,256 - 28f0: 0b04 addi s1,sp,400 - 28f2: 00090003 lb zero,0(s2) - 28f6: 0100 addi s0,sp,128 - 28f8: 0200 addi s0,sp,256 - 28fa: 0b04 addi s1,sp,400 - 28fc: 00090003 lb zero,0(s2) - 2900: 0100 addi s0,sp,128 - 2902: 0200 addi s0,sp,256 - 2904: 0b04 addi s1,sp,400 - 2906: 00090003 lb zero,0(s2) - 290a: 0100 addi s0,sp,128 - 290c: 0200 addi s0,sp,256 - 290e: 0b04 addi s1,sp,400 - 2910: 00090003 lb zero,0(s2) - 2914: 0100 addi s0,sp,128 - 2916: 0200 addi s0,sp,256 - 2918: 0b04 addi s1,sp,400 - 291a: 00090003 lb zero,0(s2) - 291e: 0100 addi s0,sp,128 - 2920: 0200 addi s0,sp,256 - 2922: 0b04 addi s1,sp,400 - 2924: 00090003 lb zero,0(s2) - 2928: 0100 addi s0,sp,128 - 292a: 0200 addi s0,sp,256 - 292c: 0b04 addi s1,sp,400 - 292e: 00090003 lb zero,0(s2) - 2932: 0100 addi s0,sp,128 - 2934: 0200 addi s0,sp,256 - 2936: 0b04 addi s1,sp,400 - 2938: 00090003 lb zero,0(s2) - 293c: 0100 addi s0,sp,128 - 293e: 0200 addi s0,sp,256 - 2940: 0b04 addi s1,sp,400 - 2942: 08090003 lb zero,128(s2) - 2946: 0100 addi s0,sp,128 - 2948: 0200 addi s0,sp,256 - 294a: 0b04 addi s1,sp,400 - 294c: 00090003 lb zero,0(s2) - 2950: 0100 addi s0,sp,128 - 2952: 0200 addi s0,sp,256 - 2954: 0b04 addi s1,sp,400 - 2956: 00090003 lb zero,0(s2) - 295a: 0100 addi s0,sp,128 - 295c: 0200 addi s0,sp,256 - 295e: 0b04 addi s1,sp,400 - 2960: 14090003 lb zero,320(s2) - 2964: 0100 addi s0,sp,128 - 2966: 0200 addi s0,sp,256 - 2968: 0b04 addi s1,sp,400 - 296a: 00090003 lb zero,0(s2) - 296e: 0100 addi s0,sp,128 - 2970: 0200 addi s0,sp,256 - 2972: 0b04 addi s1,sp,400 - 2974: 00090003 lb zero,0(s2) - 2978: 0100 addi s0,sp,128 - 297a: 0200 addi s0,sp,256 - 297c: 0c04 addi s1,sp,528 - 297e: 04090003 lb zero,64(s2) - 2982: 0100 addi s0,sp,128 - 2984: 0200 addi s0,sp,256 - 2986: 0e04 addi s1,sp,784 - 2988: 08090003 lb zero,128(s2) - 298c: 0100 addi s0,sp,128 - 298e: 0200 addi s0,sp,256 - 2990: 0e04 addi s1,sp,784 - 2992: 08090003 lb zero,128(s2) - 2996: 0100 addi s0,sp,128 - 2998: 0200 addi s0,sp,256 - 299a: 0e04 addi s1,sp,784 - 299c: 28090003 lb zero,640(s2) - 29a0: 0100 addi s0,sp,128 - 29a2: 0200 addi s0,sp,256 - 29a4: 0e04 addi s1,sp,784 - 29a6: 00090003 lb zero,0(s2) - 29aa: 0100 addi s0,sp,128 - 29ac: 0200 addi s0,sp,256 - 29ae: 0e04 addi s1,sp,784 - 29b0: 00090003 lb zero,0(s2) - 29b4: 0100 addi s0,sp,128 - 29b6: 0200 addi s0,sp,256 - 29b8: 0e04 addi s1,sp,784 - 29ba: 00090003 lb zero,0(s2) - 29be: 0100 addi s0,sp,128 - 29c0: 0200 addi s0,sp,256 - 29c2: 0e04 addi s1,sp,784 - 29c4: 00090003 lb zero,0(s2) - 29c8: 0100 addi s0,sp,128 - 29ca: 0200 addi s0,sp,256 - 29cc: 0e04 addi s1,sp,784 - 29ce: 00090003 lb zero,0(s2) - 29d2: 0100 addi s0,sp,128 - 29d4: 0200 addi s0,sp,256 - 29d6: 0e04 addi s1,sp,784 - 29d8: 00090003 lb zero,0(s2) - 29dc: 0100 addi s0,sp,128 - 29de: 0200 addi s0,sp,256 - 29e0: 0e04 addi s1,sp,784 - 29e2: 00090003 lb zero,0(s2) - 29e6: 0100 addi s0,sp,128 - 29e8: 0200 addi s0,sp,256 - 29ea: 0e04 addi s1,sp,784 - 29ec: 00090003 lb zero,0(s2) - 29f0: 0100 addi s0,sp,128 - 29f2: 0200 addi s0,sp,256 - 29f4: 0e04 addi s1,sp,784 - 29f6: 00090003 lb zero,0(s2) - 29fa: 0100 addi s0,sp,128 - 29fc: 0200 addi s0,sp,256 - 29fe: 0e04 addi s1,sp,784 - 2a00: 00090003 lb zero,0(s2) - 2a04: 0100 addi s0,sp,128 - 2a06: 0200 addi s0,sp,256 - 2a08: 0e04 addi s1,sp,784 - 2a0a: 08090003 lb zero,128(s2) - 2a0e: 0100 addi s0,sp,128 - 2a10: 0200 addi s0,sp,256 - 2a12: 0e04 addi s1,sp,784 - 2a14: 04090003 lb zero,64(s2) - 2a18: 0100 addi s0,sp,128 - 2a1a: 0200 addi s0,sp,256 - 2a1c: 0e04 addi s1,sp,784 - 2a1e: 04090003 lb zero,64(s2) - 2a22: 0100 addi s0,sp,128 - 2a24: 0200 addi s0,sp,256 - 2a26: 0e04 addi s1,sp,784 - 2a28: 08090003 lb zero,128(s2) - 2a2c: 0100 addi s0,sp,128 - 2a2e: 0200 addi s0,sp,256 - 2a30: 0f04 addi s1,sp,912 - 2a32: 04090003 lb zero,64(s2) - 2a36: 0100 addi s0,sp,128 - 2a38: 0200 addi s0,sp,256 - 2a3a: 1104 addi s1,sp,160 - 2a3c: 04090003 lb zero,64(s2) - 2a40: 0100 addi s0,sp,128 - 2a42: 0200 addi s0,sp,256 - 2a44: 1104 addi s1,sp,160 - 2a46: 0c090003 lb zero,192(s2) - 2a4a: 0100 addi s0,sp,128 - 2a4c: 0200 addi s0,sp,256 - 2a4e: 1104 addi s1,sp,160 - 2a50: 18090003 lb zero,384(s2) - 2a54: 0100 addi s0,sp,128 - 2a56: 0200 addi s0,sp,256 - 2a58: 1104 addi s1,sp,160 - 2a5a: 00090003 lb zero,0(s2) - 2a5e: 0100 addi s0,sp,128 - 2a60: 0200 addi s0,sp,256 - 2a62: 1104 addi s1,sp,160 - 2a64: 00090003 lb zero,0(s2) - 2a68: 0100 addi s0,sp,128 - 2a6a: 0200 addi s0,sp,256 - 2a6c: 1104 addi s1,sp,160 - 2a6e: 00090003 lb zero,0(s2) - 2a72: 0100 addi s0,sp,128 - 2a74: 0200 addi s0,sp,256 - 2a76: 1104 addi s1,sp,160 - 2a78: 00090003 lb zero,0(s2) - 2a7c: 0100 addi s0,sp,128 - 2a7e: 0200 addi s0,sp,256 - 2a80: 1104 addi s1,sp,160 - 2a82: 00090003 lb zero,0(s2) - 2a86: 0100 addi s0,sp,128 - 2a88: 0200 addi s0,sp,256 - 2a8a: 1104 addi s1,sp,160 - 2a8c: 00090003 lb zero,0(s2) - 2a90: 0100 addi s0,sp,128 - 2a92: 0200 addi s0,sp,256 - 2a94: 1104 addi s1,sp,160 - 2a96: 00090003 lb zero,0(s2) - 2a9a: 0100 addi s0,sp,128 - 2a9c: 0200 addi s0,sp,256 - 2a9e: 1104 addi s1,sp,160 - 2aa0: 00090003 lb zero,0(s2) - 2aa4: 0100 addi s0,sp,128 - 2aa6: 0200 addi s0,sp,256 - 2aa8: 1104 addi s1,sp,160 - 2aaa: 00090003 lb zero,0(s2) - 2aae: 0100 addi s0,sp,128 - 2ab0: 0200 addi s0,sp,256 - 2ab2: 1104 addi s1,sp,160 - 2ab4: 00090003 lb zero,0(s2) - 2ab8: 0100 addi s0,sp,128 - 2aba: 0200 addi s0,sp,256 - 2abc: 1104 addi s1,sp,160 - 2abe: 04090003 lb zero,64(s2) - 2ac2: 0100 addi s0,sp,128 - 2ac4: 0200 addi s0,sp,256 - 2ac6: 1104 addi s1,sp,160 - 2ac8: 08090003 lb zero,128(s2) - 2acc: 0100 addi s0,sp,128 - 2ace: 0200 addi s0,sp,256 - 2ad0: 1104 addi s1,sp,160 - 2ad2: 04090003 lb zero,64(s2) - 2ad6: 0100 addi s0,sp,128 - 2ad8: 0200 addi s0,sp,256 - 2ada: 1104 addi s1,sp,160 - 2adc: 08090003 lb zero,128(s2) - 2ae0: 0100 addi s0,sp,128 - 2ae2: 0200 addi s0,sp,256 - 2ae4: 1204 addi s1,sp,288 - 2ae6: 04090003 lb zero,64(s2) - 2aea: 0100 addi s0,sp,128 - 2aec: 0200 addi s0,sp,256 - 2aee: 1404 addi s1,sp,544 - 2af0: 04090003 lb zero,64(s2) - 2af4: 0100 addi s0,sp,128 - 2af6: 0200 addi s0,sp,256 - 2af8: 1404 addi s1,sp,544 - 2afa: 00090003 lb zero,0(s2) - 2afe: 0100 addi s0,sp,128 - 2b00: 0200 addi s0,sp,256 - 2b02: 1404 addi s1,sp,544 - 2b04: 00090003 lb zero,0(s2) - 2b08: 0100 addi s0,sp,128 - 2b0a: 0200 addi s0,sp,256 - 2b0c: 1404 addi s1,sp,544 - 2b0e: 00090003 lb zero,0(s2) - 2b12: 0100 addi s0,sp,128 - 2b14: 0200 addi s0,sp,256 - 2b16: 1404 addi s1,sp,544 - 2b18: 00090003 lb zero,0(s2) - 2b1c: 0100 addi s0,sp,128 - 2b1e: 0200 addi s0,sp,256 - 2b20: 1404 addi s1,sp,544 - 2b22: 00090003 lb zero,0(s2) - 2b26: 0100 addi s0,sp,128 - 2b28: 0200 addi s0,sp,256 - 2b2a: 1404 addi s1,sp,544 - 2b2c: 18090003 lb zero,384(s2) - 2b30: 0100 addi s0,sp,128 - 2b32: 0200 addi s0,sp,256 - 2b34: 1404 addi s1,sp,544 - 2b36: 08090003 lb zero,128(s2) - 2b3a: 0100 addi s0,sp,128 - 2b3c: 0200 addi s0,sp,256 - 2b3e: 1404 addi s1,sp,544 - 2b40: 04090003 lb zero,64(s2) - 2b44: 0100 addi s0,sp,128 - 2b46: 0200 addi s0,sp,256 - 2b48: 1404 addi s1,sp,544 - 2b4a: 00090003 lb zero,0(s2) - 2b4e: 0100 addi s0,sp,128 - 2b50: 0200 addi s0,sp,256 - 2b52: 1404 addi s1,sp,544 - 2b54: 04090003 lb zero,64(s2) - 2b58: 0100 addi s0,sp,128 - 2b5a: 0200 addi s0,sp,256 - 2b5c: 1404 addi s1,sp,544 - 2b5e: 00090003 lb zero,0(s2) - 2b62: 0100 addi s0,sp,128 - 2b64: 0200 addi s0,sp,256 - 2b66: 1404 addi s1,sp,544 - 2b68: 00090003 lb zero,0(s2) - 2b6c: 0100 addi s0,sp,128 - 2b6e: 0200 addi s0,sp,256 - 2b70: 1404 addi s1,sp,544 - 2b72: 00090003 lb zero,0(s2) - 2b76: 0100 addi s0,sp,128 - 2b78: 0200 addi s0,sp,256 - 2b7a: 1404 addi s1,sp,544 - 2b7c: 00090003 lb zero,0(s2) - 2b80: 0100 addi s0,sp,128 - 2b82: 0200 addi s0,sp,256 - 2b84: 1404 addi s1,sp,544 - 2b86: 00090003 lb zero,0(s2) - 2b8a: 0100 addi s0,sp,128 - 2b8c: 0200 addi s0,sp,256 - 2b8e: 1404 addi s1,sp,544 - 2b90: 04090003 lb zero,64(s2) - 2b94: 0100 addi s0,sp,128 - 2b96: 0200 addi s0,sp,256 - 2b98: 1404 addi s1,sp,544 - 2b9a: 04090003 lb zero,64(s2) - 2b9e: 0100 addi s0,sp,128 - 2ba0: 0200 addi s0,sp,256 - 2ba2: 1404 addi s1,sp,544 - 2ba4: 04090003 lb zero,64(s2) - 2ba8: 0100 addi s0,sp,128 - 2baa: 0200 addi s0,sp,256 - 2bac: 1404 addi s1,sp,544 - 2bae: 00090003 lb zero,0(s2) - 2bb2: 0100 addi s0,sp,128 - 2bb4: 0200 addi s0,sp,256 - 2bb6: 1404 addi s1,sp,544 - 2bb8: 04090003 lb zero,64(s2) - 2bbc: 0100 addi s0,sp,128 - 2bbe: 0200 addi s0,sp,256 - 2bc0: 1404 addi s1,sp,544 - 2bc2: 00090003 lb zero,0(s2) - 2bc6: 0100 addi s0,sp,128 - 2bc8: 0200 addi s0,sp,256 - 2bca: 1404 addi s1,sp,544 - 2bcc: 00090003 lb zero,0(s2) - 2bd0: 0100 addi s0,sp,128 - 2bd2: 0200 addi s0,sp,256 - 2bd4: 1404 addi s1,sp,544 - 2bd6: 00090003 lb zero,0(s2) - 2bda: 0100 addi s0,sp,128 - 2bdc: 0200 addi s0,sp,256 - 2bde: 1404 addi s1,sp,544 - 2be0: 00090003 lb zero,0(s2) - 2be4: 0100 addi s0,sp,128 - 2be6: 0200 addi s0,sp,256 - 2be8: 1404 addi s1,sp,544 - 2bea: 00090003 lb zero,0(s2) - 2bee: 0100 addi s0,sp,128 - 2bf0: 0200 addi s0,sp,256 - 2bf2: 1404 addi s1,sp,544 - 2bf4: 00090003 lb zero,0(s2) - 2bf8: 0100 addi s0,sp,128 - 2bfa: 0200 addi s0,sp,256 - 2bfc: 1404 addi s1,sp,544 - 2bfe: 00090003 lb zero,0(s2) - 2c02: 0100 addi s0,sp,128 - 2c04: 0200 addi s0,sp,256 - 2c06: 1404 addi s1,sp,544 - 2c08: 00090003 lb zero,0(s2) - 2c0c: 0100 addi s0,sp,128 - 2c0e: 0200 addi s0,sp,256 - 2c10: 1404 addi s1,sp,544 - 2c12: 00090003 lb zero,0(s2) - 2c16: 0100 addi s0,sp,128 - 2c18: 0200 addi s0,sp,256 - 2c1a: 1404 addi s1,sp,544 - 2c1c: 00090003 lb zero,0(s2) - 2c20: 0100 addi s0,sp,128 - 2c22: 0200 addi s0,sp,256 - 2c24: 1404 addi s1,sp,544 - 2c26: 00090003 lb zero,0(s2) - 2c2a: 0100 addi s0,sp,128 - 2c2c: 0200 addi s0,sp,256 - 2c2e: 1404 addi s1,sp,544 - 2c30: 00090003 lb zero,0(s2) - 2c34: 0100 addi s0,sp,128 - 2c36: 0200 addi s0,sp,256 - 2c38: 1404 addi s1,sp,544 - 2c3a: 00090003 lb zero,0(s2) - 2c3e: 0100 addi s0,sp,128 - 2c40: 0200 addi s0,sp,256 - 2c42: 1404 addi s1,sp,544 - 2c44: 00090003 lb zero,0(s2) - 2c48: 0100 addi s0,sp,128 - 2c4a: 0200 addi s0,sp,256 - 2c4c: 1404 addi s1,sp,544 - 2c4e: 00090003 lb zero,0(s2) - 2c52: 0100 addi s0,sp,128 - 2c54: 0200 addi s0,sp,256 - 2c56: 1404 addi s1,sp,544 - 2c58: 00090003 lb zero,0(s2) - 2c5c: 0100 addi s0,sp,128 - 2c5e: 0200 addi s0,sp,256 - 2c60: 1404 addi s1,sp,544 - 2c62: 00090003 lb zero,0(s2) - 2c66: 0100 addi s0,sp,128 - 2c68: 0200 addi s0,sp,256 - 2c6a: 1404 addi s1,sp,544 - 2c6c: 00090003 lb zero,0(s2) - 2c70: 0100 addi s0,sp,128 - 2c72: 0200 addi s0,sp,256 - 2c74: 1404 addi s1,sp,544 - 2c76: 00090003 lb zero,0(s2) - 2c7a: 0100 addi s0,sp,128 - 2c7c: 0200 addi s0,sp,256 - 2c7e: 1404 addi s1,sp,544 - 2c80: 00090003 lb zero,0(s2) - 2c84: 0100 addi s0,sp,128 - 2c86: 0200 addi s0,sp,256 - 2c88: 1404 addi s1,sp,544 - 2c8a: 00090003 lb zero,0(s2) - 2c8e: 0100 addi s0,sp,128 - 2c90: 0200 addi s0,sp,256 - 2c92: 1404 addi s1,sp,544 - 2c94: 00090003 lb zero,0(s2) - 2c98: 0100 addi s0,sp,128 - 2c9a: 0200 addi s0,sp,256 - 2c9c: 1404 addi s1,sp,544 - 2c9e: 00090003 lb zero,0(s2) - 2ca2: 0100 addi s0,sp,128 - 2ca4: 0200 addi s0,sp,256 - 2ca6: 1404 addi s1,sp,544 - 2ca8: 00090003 lb zero,0(s2) - 2cac: 0100 addi s0,sp,128 - 2cae: 0200 addi s0,sp,256 - 2cb0: 1404 addi s1,sp,544 - 2cb2: 00090003 lb zero,0(s2) - 2cb6: 0100 addi s0,sp,128 - 2cb8: 0200 addi s0,sp,256 - 2cba: 1404 addi s1,sp,544 - 2cbc: 50090003 lb zero,1280(s2) - 2cc0: 0100 addi s0,sp,128 - 2cc2: 0200 addi s0,sp,256 - 2cc4: 1404 addi s1,sp,544 - 2cc6: 00090003 lb zero,0(s2) - 2cca: 0100 addi s0,sp,128 - 2ccc: 0200 addi s0,sp,256 - 2cce: 1404 addi s1,sp,544 - 2cd0: 00090003 lb zero,0(s2) - 2cd4: 0100 addi s0,sp,128 - 2cd6: 0200 addi s0,sp,256 - 2cd8: 1404 addi s1,sp,544 - 2cda: 00090003 lb zero,0(s2) - 2cde: 0100 addi s0,sp,128 - 2ce0: 0200 addi s0,sp,256 - 2ce2: 1404 addi s1,sp,544 - 2ce4: 00090003 lb zero,0(s2) - 2ce8: 0100 addi s0,sp,128 - 2cea: 0200 addi s0,sp,256 - 2cec: 1404 addi s1,sp,544 - 2cee: 00090003 lb zero,0(s2) - 2cf2: 0100 addi s0,sp,128 - 2cf4: 0200 addi s0,sp,256 - 2cf6: 1404 addi s1,sp,544 - 2cf8: 00090003 lb zero,0(s2) - 2cfc: 0100 addi s0,sp,128 - 2cfe: 0200 addi s0,sp,256 - 2d00: 1404 addi s1,sp,544 - 2d02: 04090003 lb zero,64(s2) - 2d06: 0100 addi s0,sp,128 - 2d08: 0200 addi s0,sp,256 - 2d0a: 1404 addi s1,sp,544 - 2d0c: 00090003 lb zero,0(s2) - 2d10: 0100 addi s0,sp,128 - 2d12: 0200 addi s0,sp,256 - 2d14: 1404 addi s1,sp,544 - 2d16: 00090003 lb zero,0(s2) - 2d1a: 0100 addi s0,sp,128 - 2d1c: 0200 addi s0,sp,256 - 2d1e: 1404 addi s1,sp,544 - 2d20: 00090003 lb zero,0(s2) - 2d24: 0100 addi s0,sp,128 - 2d26: 0200 addi s0,sp,256 - 2d28: 1404 addi s1,sp,544 - 2d2a: 00090003 lb zero,0(s2) - 2d2e: 0100 addi s0,sp,128 - 2d30: 0200 addi s0,sp,256 - 2d32: 2604 fld fs1,8(a2) - 2d34: 04090003 lb zero,64(s2) - 2d38: 0100 addi s0,sp,128 - 2d3a: 0200 addi s0,sp,256 - 2d3c: 2604 fld fs1,8(a2) - 2d3e: 00090003 lb zero,0(s2) - 2d42: 0100 addi s0,sp,128 - 2d44: 0200 addi s0,sp,256 - 2d46: 2604 fld fs1,8(a2) - 2d48: 14090003 lb zero,320(s2) - 2d4c: 0100 addi s0,sp,128 - 2d4e: 0200 addi s0,sp,256 - 2d50: 0204 addi s1,sp,256 - 2d52: 04090103 lb sp,64(s2) - 2d56: 0100 addi s0,sp,128 - 2d58: 0200 addi s0,sp,256 - 2d5a: 0204 addi s1,sp,256 - 2d5c: 04090003 lb zero,64(s2) - 2d60: 0100 addi s0,sp,128 - 2d62: 0200 addi s0,sp,256 - 2d64: 0604 addi s1,sp,768 - 2d66: 04090003 lb zero,64(s2) - 2d6a: 0100 addi s0,sp,128 - 2d6c: 0200 addi s0,sp,256 - 2d6e: 0604 addi s1,sp,768 - 2d70: 00090003 lb zero,0(s2) - 2d74: 0100 addi s0,sp,128 - 2d76: 0200 addi s0,sp,256 - 2d78: 0804 addi s1,sp,16 - 2d7a: 08090003 lb zero,128(s2) - 2d7e: 0100 addi s0,sp,128 - 2d80: 0200 addi s0,sp,256 - 2d82: 0804 addi s1,sp,16 - 2d84: 00090003 lb zero,0(s2) - 2d88: 0100 addi s0,sp,128 - 2d8a: 0200 addi s0,sp,256 - 2d8c: 0804 addi s1,sp,16 - 2d8e: 00090003 lb zero,0(s2) - 2d92: 0100 addi s0,sp,128 - 2d94: 0200 addi s0,sp,256 - 2d96: 0804 addi s1,sp,16 - 2d98: 00090003 lb zero,0(s2) - 2d9c: 0100 addi s0,sp,128 - 2d9e: 0200 addi s0,sp,256 - 2da0: 0a04 addi s1,sp,272 - 2da2: 0c090003 lb zero,192(s2) - 2da6: 0100 addi s0,sp,128 - 2da8: 0200 addi s0,sp,256 - 2daa: 0a04 addi s1,sp,272 - 2dac: 00090003 lb zero,0(s2) - 2db0: 0100 addi s0,sp,128 - 2db2: 0200 addi s0,sp,256 - 2db4: 0a04 addi s1,sp,272 - 2db6: 00090003 lb zero,0(s2) - 2dba: 0100 addi s0,sp,128 - 2dbc: 0200 addi s0,sp,256 - 2dbe: 0a04 addi s1,sp,272 - 2dc0: 04090003 lb zero,64(s2) - 2dc4: 0100 addi s0,sp,128 - 2dc6: 0200 addi s0,sp,256 - 2dc8: 0a04 addi s1,sp,272 - 2dca: 08090003 lb zero,128(s2) - 2dce: 0100 addi s0,sp,128 - 2dd0: 0200 addi s0,sp,256 - 2dd2: 0904 addi s1,sp,144 - 2dd4: 04090003 lb zero,64(s2) - 2dd8: 0100 addi s0,sp,128 - 2dda: 0200 addi s0,sp,256 - 2ddc: 0904 addi s1,sp,144 - 2dde: 00090003 lb zero,0(s2) - 2de2: 0100 addi s0,sp,128 - 2de4: 0200 addi s0,sp,256 - 2de6: 1804 addi s1,sp,48 - 2de8: 08090003 lb zero,128(s2) - 2dec: 0100 addi s0,sp,128 - 2dee: 0200 addi s0,sp,256 - 2df0: 1804 addi s1,sp,48 - 2df2: 0c090003 lb zero,192(s2) - 2df6: 0100 addi s0,sp,128 - 2df8: 0200 addi s0,sp,256 - 2dfa: 1a04 addi s1,sp,304 - 2dfc: 04090003 lb zero,64(s2) - 2e00: 0100 addi s0,sp,128 - 2e02: 0200 addi s0,sp,256 - 2e04: 1a04 addi s1,sp,304 - 2e06: 00090003 lb zero,0(s2) - 2e0a: 0100 addi s0,sp,128 - 2e0c: 0200 addi s0,sp,256 - 2e0e: 1a04 addi s1,sp,304 - 2e10: 00090003 lb zero,0(s2) - 2e14: 0100 addi s0,sp,128 - 2e16: 0200 addi s0,sp,256 - 2e18: 1a04 addi s1,sp,304 - 2e1a: 00090003 lb zero,0(s2) - 2e1e: 0100 addi s0,sp,128 - 2e20: 0306 slli t1,t1,0x1 - 2e22: 0900 addi s0,sp,144 - 2e24: 0008 0x8 - 2e26: 0001 nop - 2e28: 0402 c.slli64 s0 - 2e2a: 00030677 0x30677 - 2e2e: 1009 c.nop -30 - 2e30: 0100 addi s0,sp,128 - 2e32: 0200 addi s0,sp,256 - 2e34: 7704 flw fs1,40(a4) - 2e36: 00090003 lb zero,0(s2) - 2e3a: 0100 addi s0,sp,128 - 2e3c: 0200 addi s0,sp,256 - 2e3e: 7704 flw fs1,40(a4) - 2e40: 00090003 lb zero,0(s2) - 2e44: 0100 addi s0,sp,128 - 2e46: 0200 addi s0,sp,256 - 2e48: 7704 flw fs1,40(a4) - 2e4a: 00090003 lb zero,0(s2) - 2e4e: 0100 addi s0,sp,128 - 2e50: 0200 addi s0,sp,256 - 2e52: 7704 flw fs1,40(a4) - 2e54: 00090003 lb zero,0(s2) - 2e58: 0100 addi s0,sp,128 - 2e5a: 0200 addi s0,sp,256 - 2e5c: 7704 flw fs1,40(a4) - 2e5e: 00090003 lb zero,0(s2) - 2e62: 0100 addi s0,sp,128 - 2e64: 0200 addi s0,sp,256 - 2e66: 7704 flw fs1,40(a4) - 2e68: 00090003 lb zero,0(s2) - 2e6c: 0100 addi s0,sp,128 - 2e6e: 0200 addi s0,sp,256 - 2e70: 7704 flw fs1,40(a4) - 2e72: 00090003 lb zero,0(s2) - 2e76: 0100 addi s0,sp,128 - 2e78: 0105 addi sp,sp,1 - 2e7a: 0200 addi s0,sp,256 - 2e7c: 7704 flw fs1,40(a4) - 2e7e: 0306 slli t1,t1,0x1 - 2e80: 0904 addi s1,sp,144 - 2e82: 001c 0x1c - 2e84: 0501 addi a0,a0,0 - 2e86: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> - 2e8a: 097c0377 0x97c0377 - 2e8e: 0004 0x4 - 2e90: 0001 nop - 2e92: 0402 c.slli64 s0 - 2e94: 00030677 0x30677 - 2e98: 0409 addi s0,s0,2 - 2e9a: 0100 addi s0,sp,128 - 2e9c: 0200 addi s0,sp,256 - 2e9e: 7704 flw fs1,40(a4) - 2ea0: 00090003 lb zero,0(s2) - 2ea4: 0100 addi s0,sp,128 - 2ea6: 0200 addi s0,sp,256 - 2ea8: 7704 flw fs1,40(a4) - 2eaa: 00090103 lb sp,0(s2) - 2eae: 0100 addi s0,sp,128 - 2eb0: 0200 addi s0,sp,256 - 2eb2: 7704 flw fs1,40(a4) - 2eb4: 00090003 lb zero,0(s2) - 2eb8: 0100 addi s0,sp,128 - 2eba: 0200 addi s0,sp,256 - 2ebc: 7704 flw fs1,40(a4) - 2ebe: 00090003 lb zero,0(s2) - 2ec2: 0100 addi s0,sp,128 - 2ec4: 0200 addi s0,sp,256 - 2ec6: 7704 flw fs1,40(a4) - 2ec8: 00090203 lb tp,0(s2) - 2ecc: 0100 addi s0,sp,128 - 2ece: 0105 addi sp,sp,1 - 2ed0: 0200 addi s0,sp,256 - 2ed2: 7704 flw fs1,40(a4) - 2ed4: 0306 slli t1,t1,0x1 - 2ed6: 0901 addi s2,s2,0 - 2ed8: 0000 unimp - 2eda: 0501 addi a0,a0,0 - 2edc: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> - 2ee0: 09790307 0x9790307 - 2ee4: 0030 addi a2,sp,8 - 2ee6: 0001 nop - 2ee8: 0402 c.slli64 s0 - 2eea: 02030607 0x2030607 - 2eee: 0409 addi s0,s0,2 - 2ef0: 0100 addi s0,sp,128 - 2ef2: 0200 addi s0,sp,256 - 2ef4: 2f04 fld fs1,24(a4) - 2ef6: 0c090003 lb zero,192(s2) - 2efa: 0100 addi s0,sp,128 - 2efc: 0200 addi s0,sp,256 - 2efe: 2f04 fld fs1,24(a4) - 2f00: 00090103 lb sp,0(s2) - 2f04: 0100 addi s0,sp,128 - 2f06: 0200 addi s0,sp,256 - 2f08: 2f04 fld fs1,24(a4) - 2f0a: 00090003 lb zero,0(s2) - 2f0e: 0100 addi s0,sp,128 - 2f10: 0200 addi s0,sp,256 - 2f12: 2f04 fld fs1,24(a4) - 2f14: 00090003 lb zero,0(s2) - 2f18: 0100 addi s0,sp,128 - 2f1a: 0306 slli t1,t1,0x1 - 2f1c: 0900 addi s0,sp,144 - 2f1e: 0008 0x8 - 2f20: 0001 nop - 2f22: 0402 c.slli64 s0 - 2f24: 0304 addi s1,sp,384 - 2f26: 097e slli s2,s2,0x1f - 2f28: 001c 0x1c - 2f2a: 0001 nop - 2f2c: 0402 c.slli64 s0 - 2f2e: 0604 addi s1,sp,768 - 2f30: 04090103 lb sp,64(s2) - 2f34: 0100 addi s0,sp,128 - 2f36: 0306 slli t1,t1,0x1 - 2f38: 0900 addi s0,sp,144 - 2f3a: 0004 0x4 - 2f3c: 0001 nop - 2f3e: 0402 c.slli64 s0 - 2f40: 0103063b 0x103063b - 2f44: 0809 addi a6,a6,2 - 2f46: 0100 addi s0,sp,128 - 2f48: 0200 addi s0,sp,256 - 2f4a: 3b04 fld fs1,48(a4) - 2f4c: 00090003 lb zero,0(s2) - 2f50: 0100 addi s0,sp,128 - 2f52: 0200 addi s0,sp,256 - 2f54: 3b04 fld fs1,48(a4) - 2f56: 00090003 lb zero,0(s2) - 2f5a: 0100 addi s0,sp,128 - 2f5c: 0200 addi s0,sp,256 - 2f5e: 3b04 fld fs1,48(a4) - 2f60: 08090003 lb zero,128(s2) - 2f64: 0100 addi s0,sp,128 - 2f66: 0200 addi s0,sp,256 - 2f68: 3c04 fld fs1,56(s0) - 2f6a: 08090003 lb zero,128(s2) - 2f6e: 0100 addi s0,sp,128 - 2f70: 0200 addi s0,sp,256 - 2f72: 3e04 fld fs1,56(a2) - 2f74: 08090003 lb zero,128(s2) - 2f78: 0100 addi s0,sp,128 - 2f7a: 0200 addi s0,sp,256 - 2f7c: 3e04 fld fs1,56(a2) - 2f7e: 1c090003 lb zero,448(s2) - 2f82: 0100 addi s0,sp,128 - 2f84: 0200 addi s0,sp,256 - 2f86: 4b04 lw s1,16(a4) - 2f88: 04090003 lb zero,64(s2) - 2f8c: 0100 addi s0,sp,128 - 2f8e: 0200 addi s0,sp,256 - 2f90: 4b04 lw s1,16(a4) - 2f92: 00090003 lb zero,0(s2) - 2f96: 0100 addi s0,sp,128 - 2f98: 0200 addi s0,sp,256 - 2f9a: 4c04 lw s1,24(s0) - 2f9c: 08090003 lb zero,128(s2) - 2fa0: 0100 addi s0,sp,128 - 2fa2: 0200 addi s0,sp,256 - 2fa4: 4c04 lw s1,24(s0) - 2fa6: 00090003 lb zero,0(s2) - 2faa: 0100 addi s0,sp,128 - 2fac: 0200 addi s0,sp,256 - 2fae: 4c04 lw s1,24(s0) - 2fb0: 00090003 lb zero,0(s2) - 2fb4: 0100 addi s0,sp,128 - 2fb6: 0200 addi s0,sp,256 - 2fb8: 4c04 lw s1,24(s0) - 2fba: 00090003 lb zero,0(s2) - 2fbe: 0100 addi s0,sp,128 - 2fc0: 0200 addi s0,sp,256 - 2fc2: 4e04 lw s1,24(a2) - 2fc4: 0c090003 lb zero,192(s2) - 2fc8: 0100 addi s0,sp,128 - 2fca: 0200 addi s0,sp,256 - 2fcc: 4e04 lw s1,24(a2) - 2fce: 00090003 lb zero,0(s2) - 2fd2: 0100 addi s0,sp,128 - 2fd4: 0200 addi s0,sp,256 - 2fd6: 4e04 lw s1,24(a2) - 2fd8: 00090003 lb zero,0(s2) - 2fdc: 0100 addi s0,sp,128 - 2fde: 0200 addi s0,sp,256 - 2fe0: 4e04 lw s1,24(a2) - 2fe2: 04090003 lb zero,64(s2) - 2fe6: 0100 addi s0,sp,128 - 2fe8: 0200 addi s0,sp,256 - 2fea: 4e04 lw s1,24(a2) - 2fec: 08090003 lb zero,128(s2) - 2ff0: 0100 addi s0,sp,128 - 2ff2: 0200 addi s0,sp,256 - 2ff4: 4d04 lw s1,24(a0) - 2ff6: 04090003 lb zero,64(s2) - 2ffa: 0100 addi s0,sp,128 - 2ffc: 0200 addi s0,sp,256 - 2ffe: 4d04 lw s1,24(a0) - 3000: 00090003 lb zero,0(s2) - 3004: 0100 addi s0,sp,128 - 3006: 0200 addi s0,sp,256 - 3008: 5d04 lw s1,56(a0) - 300a: 08090003 lb zero,128(s2) - 300e: 0100 addi s0,sp,128 - 3010: 0200 addi s0,sp,256 - 3012: 5d04 lw s1,56(a0) - 3014: 00090003 lb zero,0(s2) - 3018: 0100 addi s0,sp,128 - 301a: 0200 addi s0,sp,256 - 301c: 5d04 lw s1,56(a0) - 301e: 00090003 lb zero,0(s2) + 2418: 0200 addi s0,sp,256 + 241a: 0104 addi s1,sp,128 + 241c: 00090003 lb zero,0(s2) + 2420: 0100 addi s0,sp,128 + 2422: 0200 addi s0,sp,256 + 2424: 0104 addi s1,sp,128 + 2426: 04090003 lb zero,64(s2) + 242a: 0100 addi s0,sp,128 + 242c: 0200 addi s0,sp,256 + 242e: 0104 addi s1,sp,128 + 2430: 00090003 lb zero,0(s2) + 2434: 0100 addi s0,sp,128 + 2436: 0200 addi s0,sp,256 + 2438: 2904 fld fs1,16(a0) + 243a: 00090003 lb zero,0(s2) + 243e: 0100 addi s0,sp,128 + 2440: 0200 addi s0,sp,256 + 2442: 2904 fld fs1,16(a0) + 2444: 00090003 lb zero,0(s2) + 2448: 0100 addi s0,sp,128 + 244a: 0200 addi s0,sp,256 + 244c: 0804 addi s1,sp,16 + 244e: 04090003 lb zero,64(s2) + 2452: 0100 addi s0,sp,128 + 2454: 0200 addi s0,sp,256 + 2456: 0804 addi s1,sp,16 + 2458: 00090003 lb zero,0(s2) + 245c: 0100 addi s0,sp,128 + 245e: 0200 addi s0,sp,256 + 2460: 0804 addi s1,sp,16 + 2462: 00090103 lb sp,0(s2) + 2466: 0100 addi s0,sp,128 + 2468: 0200 addi s0,sp,256 + 246a: 0804 addi s1,sp,16 + 246c: 00090003 lb zero,0(s2) + 2470: 0100 addi s0,sp,128 + 2472: 0200 addi s0,sp,256 + 2474: 0804 addi s1,sp,16 + 2476: 00090003 lb zero,0(s2) + 247a: 0100 addi s0,sp,128 + 247c: 0200 addi s0,sp,256 + 247e: 0804 addi s1,sp,16 + 2480: 00090003 lb zero,0(s2) + 2484: 0100 addi s0,sp,128 + 2486: 0200 addi s0,sp,256 + 2488: 0804 addi s1,sp,16 + 248a: 00090003 lb zero,0(s2) + 248e: 0100 addi s0,sp,128 + 2490: 0200 addi s0,sp,256 + 2492: 0804 addi s1,sp,16 + 2494: 00090003 lb zero,0(s2) + 2498: 0100 addi s0,sp,128 + 249a: 0200 addi s0,sp,256 + 249c: 0804 addi s1,sp,16 + 249e: 10090003 lb zero,256(s2) + 24a2: 0100 addi s0,sp,128 + 24a4: 0200 addi s0,sp,256 + 24a6: 0804 addi s1,sp,16 + 24a8: 04090003 lb zero,64(s2) + 24ac: 0100 addi s0,sp,128 + 24ae: 0200 addi s0,sp,256 + 24b0: 0804 addi s1,sp,16 + 24b2: 04090003 lb zero,64(s2) + 24b6: 0100 addi s0,sp,128 + 24b8: 0200 addi s0,sp,256 + 24ba: 0804 addi s1,sp,16 + 24bc: 00090003 lb zero,0(s2) + 24c0: 0100 addi s0,sp,128 + 24c2: 0200 addi s0,sp,256 + 24c4: 0804 addi s1,sp,16 + 24c6: 00090003 lb zero,0(s2) + 24ca: 0100 addi s0,sp,128 + 24cc: 0306 slli t1,t1,0x1 + 24ce: 0900 addi s0,sp,144 + 24d0: 0004 0x4 + 24d2: 0001 nop + 24d4: 0402 c.slli64 s0 + 24d6: 0601 addi a2,a2,0 + 24d8: 08090003 lb zero,128(s2) + 24dc: 0100 addi s0,sp,128 + 24de: 0200 addi s0,sp,256 + 24e0: 0104 addi s1,sp,128 + 24e2: 00090003 lb zero,0(s2) + 24e6: 0100 addi s0,sp,128 + 24e8: 0200 addi s0,sp,256 + 24ea: 0104 addi s1,sp,128 + 24ec: 00090003 lb zero,0(s2) + 24f0: 0100 addi s0,sp,128 + 24f2: 0200 addi s0,sp,256 + 24f4: 0104 addi s1,sp,128 + 24f6: 00090003 lb zero,0(s2) + 24fa: 0100 addi s0,sp,128 + 24fc: 0200 addi s0,sp,256 + 24fe: 0104 addi s1,sp,128 + 2500: 14090003 lb zero,320(s2) + 2504: 0100 addi s0,sp,128 + 2506: 0200 addi s0,sp,256 + 2508: 0104 addi s1,sp,128 + 250a: 08090003 lb zero,128(s2) + 250e: 0100 addi s0,sp,128 + 2510: 0200 addi s0,sp,256 + 2512: 0104 addi s1,sp,128 + 2514: 00090003 lb zero,0(s2) + 2518: 0100 addi s0,sp,128 + 251a: 0200 addi s0,sp,256 + 251c: 0104 addi s1,sp,128 + 251e: 00090003 lb zero,0(s2) + 2522: 0100 addi s0,sp,128 + 2524: 0200 addi s0,sp,256 + 2526: 0104 addi s1,sp,128 + 2528: 00090003 lb zero,0(s2) + 252c: 0100 addi s0,sp,128 + 252e: 0200 addi s0,sp,256 + 2530: 2904 fld fs1,16(a0) + 2532: 00090003 lb zero,0(s2) + 2536: 0100 addi s0,sp,128 + 2538: 0200 addi s0,sp,256 + 253a: 2904 fld fs1,16(a0) + 253c: 00090003 lb zero,0(s2) + 2540: 0100 addi s0,sp,128 + 2542: 0200 addi s0,sp,256 + 2544: 0804 addi s1,sp,16 + 2546: 04090003 lb zero,64(s2) + 254a: 0100 addi s0,sp,128 + 254c: 0200 addi s0,sp,256 + 254e: 0804 addi s1,sp,16 + 2550: 00090003 lb zero,0(s2) + 2554: 0100 addi s0,sp,128 + 2556: 0200 addi s0,sp,256 + 2558: 0804 addi s1,sp,16 + 255a: 00090103 lb sp,0(s2) + 255e: 0100 addi s0,sp,128 + 2560: 0200 addi s0,sp,256 + 2562: 0804 addi s1,sp,16 + 2564: 00090003 lb zero,0(s2) + 2568: 0100 addi s0,sp,128 + 256a: 0200 addi s0,sp,256 + 256c: 0804 addi s1,sp,16 + 256e: 18090003 lb zero,384(s2) + 2572: 0100 addi s0,sp,128 + 2574: 0200 addi s0,sp,256 + 2576: 0804 addi s1,sp,16 + 2578: 04090003 lb zero,64(s2) + 257c: 0100 addi s0,sp,128 + 257e: 0200 addi s0,sp,256 + 2580: 0204 addi s1,sp,256 + 2582: 1c097e03 0x1c097e03 + 2586: 0100 addi s0,sp,128 + 2588: 0200 addi s0,sp,256 + 258a: 0d04 addi s1,sp,656 + 258c: 08090003 lb zero,128(s2) + 2590: 0100 addi s0,sp,128 + 2592: 0200 addi s0,sp,256 + 2594: 0d04 addi s1,sp,656 + 2596: 00090003 lb zero,0(s2) + 259a: 0100 addi s0,sp,128 + 259c: 0200 addi s0,sp,256 + 259e: 0d04 addi s1,sp,656 + 25a0: 00090003 lb zero,0(s2) + 25a4: 0100 addi s0,sp,128 + 25a6: 0200 addi s0,sp,256 + 25a8: 0d04 addi s1,sp,656 + 25aa: 00090003 lb zero,0(s2) + 25ae: 0100 addi s0,sp,128 + 25b0: 0200 addi s0,sp,256 + 25b2: 1104 addi s1,sp,160 + 25b4: 04090003 lb zero,64(s2) + 25b8: 0100 addi s0,sp,128 + 25ba: 0200 addi s0,sp,256 + 25bc: 1104 addi s1,sp,160 + 25be: 00090003 lb zero,0(s2) + 25c2: 0100 addi s0,sp,128 + 25c4: 0200 addi s0,sp,256 + 25c6: 1104 addi s1,sp,160 + 25c8: 00090003 lb zero,0(s2) + 25cc: 0100 addi s0,sp,128 + 25ce: 0200 addi s0,sp,256 + 25d0: 1104 addi s1,sp,160 + 25d2: 00090003 lb zero,0(s2) + 25d6: 0100 addi s0,sp,128 + 25d8: 0200 addi s0,sp,256 + 25da: 1104 addi s1,sp,160 + 25dc: 08090003 lb zero,128(s2) + 25e0: 0100 addi s0,sp,128 + 25e2: 0200 addi s0,sp,256 + 25e4: 1f04 addi s1,sp,944 + 25e6: 00090003 lb zero,0(s2) + 25ea: 0100 addi s0,sp,128 + 25ec: 0200 addi s0,sp,256 + 25ee: 1f04 addi s1,sp,944 + 25f0: 00090003 lb zero,0(s2) + 25f4: 0100 addi s0,sp,128 + 25f6: 0200 addi s0,sp,256 + 25f8: 1f04 addi s1,sp,944 + 25fa: 04090003 lb zero,64(s2) + 25fe: 0100 addi s0,sp,128 + 2600: 0200 addi s0,sp,256 + 2602: 2004 fld fs1,0(s0) + 2604: 08090003 lb zero,128(s2) + 2608: 0100 addi s0,sp,128 + 260a: 0200 addi s0,sp,256 + 260c: 2004 fld fs1,0(s0) + 260e: 08090003 lb zero,128(s2) + 2612: 0100 addi s0,sp,128 + 2614: 0200 addi s0,sp,256 + 2616: 2004 fld fs1,0(s0) + 2618: 10090003 lb zero,256(s2) + 261c: 0100 addi s0,sp,128 + 261e: 0200 addi s0,sp,256 + 2620: 2004 fld fs1,0(s0) + 2622: 04090003 lb zero,64(s2) + 2626: 0100 addi s0,sp,128 + 2628: 0200 addi s0,sp,256 + 262a: 2904 fld fs1,16(a0) + 262c: 00090003 lb zero,0(s2) + 2630: 0100 addi s0,sp,128 + 2632: 0200 addi s0,sp,256 + 2634: 1804 addi s1,sp,48 + 2636: 0c090003 lb zero,192(s2) + 263a: 0100 addi s0,sp,128 + 263c: 0200 addi s0,sp,256 + 263e: 1804 addi s1,sp,48 + 2640: 00090003 lb zero,0(s2) + 2644: 0100 addi s0,sp,128 + 2646: 0200 addi s0,sp,256 + 2648: 1804 addi s1,sp,48 + 264a: 00090003 lb zero,0(s2) + 264e: 0100 addi s0,sp,128 + 2650: 0200 addi s0,sp,256 + 2652: 1804 addi s1,sp,48 + 2654: 00090003 lb zero,0(s2) + 2658: 0100 addi s0,sp,128 + 265a: 0200 addi s0,sp,256 + 265c: 1804 addi s1,sp,48 + 265e: 04090003 lb zero,64(s2) + 2662: 0100 addi s0,sp,128 + 2664: 0200 addi s0,sp,256 + 2666: 1804 addi s1,sp,48 + 2668: 00090003 lb zero,0(s2) + 266c: 0100 addi s0,sp,128 + 266e: 0200 addi s0,sp,256 + 2670: 2104 fld fs1,0(a0) + 2672: 08090003 lb zero,128(s2) + 2676: 0100 addi s0,sp,128 + 2678: 0200 addi s0,sp,256 + 267a: 2104 fld fs1,0(a0) + 267c: 08090003 lb zero,128(s2) + 2680: 0100 addi s0,sp,128 + 2682: 0200 addi s0,sp,256 + 2684: 0304 addi s1,sp,384 + 2686: 08090003 lb zero,128(s2) + 268a: 0100 addi s0,sp,128 + 268c: 0306 slli t1,t1,0x1 + 268e: 0900 addi s0,sp,144 + 2690: 0008 0x8 + 2692: 0001 nop + 2694: 0402 c.slli64 s0 + 2696: 0602 c.slli64 a2 + 2698: 30090103 lb sp,768(s2) + 269c: 0100 addi s0,sp,128 + 269e: 0200 addi s0,sp,256 + 26a0: 0d04 addi s1,sp,656 + 26a2: 08090003 lb zero,128(s2) + 26a6: 0100 addi s0,sp,128 + 26a8: 0200 addi s0,sp,256 + 26aa: 0d04 addi s1,sp,656 + 26ac: 00090003 lb zero,0(s2) + 26b0: 0100 addi s0,sp,128 + 26b2: 0200 addi s0,sp,256 + 26b4: 0d04 addi s1,sp,656 + 26b6: 00090003 lb zero,0(s2) + 26ba: 0100 addi s0,sp,128 + 26bc: 0200 addi s0,sp,256 + 26be: 0d04 addi s1,sp,656 + 26c0: 00090003 lb zero,0(s2) + 26c4: 0100 addi s0,sp,128 + 26c6: 0200 addi s0,sp,256 + 26c8: 1104 addi s1,sp,160 + 26ca: 04090003 lb zero,64(s2) + 26ce: 0100 addi s0,sp,128 + 26d0: 0200 addi s0,sp,256 + 26d2: 1104 addi s1,sp,160 + 26d4: 00090003 lb zero,0(s2) + 26d8: 0100 addi s0,sp,128 + 26da: 0200 addi s0,sp,256 + 26dc: 1104 addi s1,sp,160 + 26de: 00090003 lb zero,0(s2) + 26e2: 0100 addi s0,sp,128 + 26e4: 0200 addi s0,sp,256 + 26e6: 1104 addi s1,sp,160 + 26e8: 00090003 lb zero,0(s2) + 26ec: 0100 addi s0,sp,128 + 26ee: 0200 addi s0,sp,256 + 26f0: 1104 addi s1,sp,160 + 26f2: 08090003 lb zero,128(s2) + 26f6: 0100 addi s0,sp,128 + 26f8: 0200 addi s0,sp,256 + 26fa: 1f04 addi s1,sp,944 + 26fc: 00090003 lb zero,0(s2) + 2700: 0100 addi s0,sp,128 + 2702: 0200 addi s0,sp,256 + 2704: 1f04 addi s1,sp,944 + 2706: 00090003 lb zero,0(s2) + 270a: 0100 addi s0,sp,128 + 270c: 0200 addi s0,sp,256 + 270e: 1f04 addi s1,sp,944 + 2710: 04090003 lb zero,64(s2) + 2714: 0100 addi s0,sp,128 + 2716: 0200 addi s0,sp,256 + 2718: 2004 fld fs1,0(s0) + 271a: 08090003 lb zero,128(s2) + 271e: 0100 addi s0,sp,128 + 2720: 0200 addi s0,sp,256 + 2722: 2004 fld fs1,0(s0) + 2724: 08090003 lb zero,128(s2) + 2728: 0100 addi s0,sp,128 + 272a: 0200 addi s0,sp,256 + 272c: 2004 fld fs1,0(s0) + 272e: 10090003 lb zero,256(s2) + 2732: 0100 addi s0,sp,128 + 2734: 0200 addi s0,sp,256 + 2736: 2004 fld fs1,0(s0) + 2738: 04090003 lb zero,64(s2) + 273c: 0100 addi s0,sp,128 + 273e: 0200 addi s0,sp,256 + 2740: 2904 fld fs1,16(a0) + 2742: 00090003 lb zero,0(s2) + 2746: 0100 addi s0,sp,128 + 2748: 0200 addi s0,sp,256 + 274a: 1804 addi s1,sp,48 + 274c: 0c090003 lb zero,192(s2) + 2750: 0100 addi s0,sp,128 + 2752: 0200 addi s0,sp,256 + 2754: 1804 addi s1,sp,48 + 2756: 00090003 lb zero,0(s2) + 275a: 0100 addi s0,sp,128 + 275c: 0200 addi s0,sp,256 + 275e: 1804 addi s1,sp,48 + 2760: 00090003 lb zero,0(s2) + 2764: 0100 addi s0,sp,128 + 2766: 0200 addi s0,sp,256 + 2768: 1804 addi s1,sp,48 + 276a: 00090003 lb zero,0(s2) + 276e: 0100 addi s0,sp,128 + 2770: 0200 addi s0,sp,256 + 2772: 1804 addi s1,sp,48 + 2774: 08090003 lb zero,128(s2) + 2778: 0100 addi s0,sp,128 + 277a: 0200 addi s0,sp,256 + 277c: 1804 addi s1,sp,48 + 277e: 00090003 lb zero,0(s2) + 2782: 0100 addi s0,sp,128 + 2784: 0200 addi s0,sp,256 + 2786: 2104 fld fs1,0(a0) + 2788: 08090003 lb zero,128(s2) + 278c: 0100 addi s0,sp,128 + 278e: 0200 addi s0,sp,256 + 2790: 2104 fld fs1,0(a0) + 2792: 08090003 lb zero,128(s2) + 2796: 0100 addi s0,sp,128 + 2798: 0200 addi s0,sp,256 + 279a: 0304 addi s1,sp,384 + 279c: 08090003 lb zero,128(s2) + 27a0: 0100 addi s0,sp,128 + 27a2: 0306 slli t1,t1,0x1 + 27a4: 0900 addi s0,sp,144 + 27a6: 0008 0x8 + 27a8: 0001 nop + 27aa: 0402 c.slli64 s0 + 27ac: 0602 c.slli64 a2 + 27ae: 30090103 lb sp,768(s2) + 27b2: 0100 addi s0,sp,128 + 27b4: 0200 addi s0,sp,256 + 27b6: 0204 addi s1,sp,256 + 27b8: 00090003 lb zero,0(s2) + 27bc: 0100 addi s0,sp,128 + 27be: 0200 addi s0,sp,256 + 27c0: 0204 addi s1,sp,256 + 27c2: 00090003 lb zero,0(s2) + 27c6: 0100 addi s0,sp,128 + 27c8: 0200 addi s0,sp,256 + 27ca: 0204 addi s1,sp,256 + 27cc: 00090003 lb zero,0(s2) + 27d0: 0100 addi s0,sp,128 + 27d2: 0200 addi s0,sp,256 + 27d4: 0204 addi s1,sp,256 + 27d6: 00090003 lb zero,0(s2) + 27da: 0100 addi s0,sp,128 + 27dc: 0200 addi s0,sp,256 + 27de: 0204 addi s1,sp,256 + 27e0: 00090003 lb zero,0(s2) + 27e4: 0100 addi s0,sp,128 + 27e6: 0200 addi s0,sp,256 + 27e8: 0204 addi s1,sp,256 + 27ea: 00090003 lb zero,0(s2) + 27ee: 0100 addi s0,sp,128 + 27f0: 0200 addi s0,sp,256 + 27f2: 0204 addi s1,sp,256 + 27f4: 00090003 lb zero,0(s2) + 27f8: 0100 addi s0,sp,128 + 27fa: 0200 addi s0,sp,256 + 27fc: 0204 addi s1,sp,256 + 27fe: 00090003 lb zero,0(s2) + 2802: 0100 addi s0,sp,128 + 2804: 0200 addi s0,sp,256 + 2806: 0204 addi s1,sp,256 + 2808: 00090003 lb zero,0(s2) + 280c: 0100 addi s0,sp,128 + 280e: 0200 addi s0,sp,256 + 2810: 0204 addi s1,sp,256 + 2812: 00090003 lb zero,0(s2) + 2816: 0100 addi s0,sp,128 + 2818: 0200 addi s0,sp,256 + 281a: 0204 addi s1,sp,256 + 281c: 0c090003 lb zero,192(s2) + 2820: 0100 addi s0,sp,128 + 2822: 0200 addi s0,sp,256 + 2824: 0204 addi s1,sp,256 + 2826: 00090003 lb zero,0(s2) + 282a: 0100 addi s0,sp,128 + 282c: 0200 addi s0,sp,256 + 282e: 0204 addi s1,sp,256 + 2830: 04090003 lb zero,64(s2) + 2834: 0100 addi s0,sp,128 + 2836: 0200 addi s0,sp,256 + 2838: 0204 addi s1,sp,256 + 283a: 10090003 lb zero,256(s2) + 283e: 0100 addi s0,sp,128 + 2840: 0200 addi s0,sp,256 + 2842: 0204 addi s1,sp,256 + 2844: 00090003 lb zero,0(s2) + 2848: 0100 addi s0,sp,128 + 284a: 0200 addi s0,sp,256 + 284c: 0204 addi s1,sp,256 + 284e: 04090003 lb zero,64(s2) + 2852: 0100 addi s0,sp,128 + 2854: 0200 addi s0,sp,256 + 2856: 0204 addi s1,sp,256 + 2858: 10090003 lb zero,256(s2) + 285c: 0100 addi s0,sp,128 + 285e: 0200 addi s0,sp,256 + 2860: 0204 addi s1,sp,256 + 2862: 00090003 lb zero,0(s2) + 2866: 0100 addi s0,sp,128 + 2868: 0200 addi s0,sp,256 + 286a: 0204 addi s1,sp,256 + 286c: 00090003 lb zero,0(s2) + 2870: 0100 addi s0,sp,128 + 2872: 0200 addi s0,sp,256 + 2874: 0904 addi s1,sp,144 + 2876: 04090003 lb zero,64(s2) + 287a: 0100 addi s0,sp,128 + 287c: 0200 addi s0,sp,256 + 287e: 0b04 addi s1,sp,400 + 2880: 04090003 lb zero,64(s2) + 2884: 0100 addi s0,sp,128 + 2886: 0200 addi s0,sp,256 + 2888: 0b04 addi s1,sp,400 + 288a: 04090003 lb zero,64(s2) + 288e: 0100 addi s0,sp,128 + 2890: 0200 addi s0,sp,256 + 2892: 0b04 addi s1,sp,400 + 2894: 18090003 lb zero,384(s2) + 2898: 0100 addi s0,sp,128 + 289a: 0200 addi s0,sp,256 + 289c: 0b04 addi s1,sp,400 + 289e: 00090003 lb zero,0(s2) + 28a2: 0100 addi s0,sp,128 + 28a4: 0200 addi s0,sp,256 + 28a6: 0b04 addi s1,sp,400 + 28a8: 00090003 lb zero,0(s2) + 28ac: 0100 addi s0,sp,128 + 28ae: 0200 addi s0,sp,256 + 28b0: 0b04 addi s1,sp,400 + 28b2: 00090003 lb zero,0(s2) + 28b6: 0100 addi s0,sp,128 + 28b8: 0200 addi s0,sp,256 + 28ba: 0b04 addi s1,sp,400 + 28bc: 00090003 lb zero,0(s2) + 28c0: 0100 addi s0,sp,128 + 28c2: 0200 addi s0,sp,256 + 28c4: 0b04 addi s1,sp,400 + 28c6: 00090003 lb zero,0(s2) + 28ca: 0100 addi s0,sp,128 + 28cc: 0200 addi s0,sp,256 + 28ce: 0b04 addi s1,sp,400 + 28d0: 00090003 lb zero,0(s2) + 28d4: 0100 addi s0,sp,128 + 28d6: 0200 addi s0,sp,256 + 28d8: 0b04 addi s1,sp,400 + 28da: 00090003 lb zero,0(s2) + 28de: 0100 addi s0,sp,128 + 28e0: 0200 addi s0,sp,256 + 28e2: 0b04 addi s1,sp,400 + 28e4: 00090003 lb zero,0(s2) + 28e8: 0100 addi s0,sp,128 + 28ea: 0200 addi s0,sp,256 + 28ec: 0b04 addi s1,sp,400 + 28ee: 08090003 lb zero,128(s2) + 28f2: 0100 addi s0,sp,128 + 28f4: 0200 addi s0,sp,256 + 28f6: 0b04 addi s1,sp,400 + 28f8: 00090003 lb zero,0(s2) + 28fc: 0100 addi s0,sp,128 + 28fe: 0200 addi s0,sp,256 + 2900: 0b04 addi s1,sp,400 + 2902: 00090003 lb zero,0(s2) + 2906: 0100 addi s0,sp,128 + 2908: 0200 addi s0,sp,256 + 290a: 0b04 addi s1,sp,400 + 290c: 14090003 lb zero,320(s2) + 2910: 0100 addi s0,sp,128 + 2912: 0200 addi s0,sp,256 + 2914: 0b04 addi s1,sp,400 + 2916: 00090003 lb zero,0(s2) + 291a: 0100 addi s0,sp,128 + 291c: 0200 addi s0,sp,256 + 291e: 0b04 addi s1,sp,400 + 2920: 00090003 lb zero,0(s2) + 2924: 0100 addi s0,sp,128 + 2926: 0200 addi s0,sp,256 + 2928: 0c04 addi s1,sp,528 + 292a: 04090003 lb zero,64(s2) + 292e: 0100 addi s0,sp,128 + 2930: 0200 addi s0,sp,256 + 2932: 0e04 addi s1,sp,784 + 2934: 08090003 lb zero,128(s2) + 2938: 0100 addi s0,sp,128 + 293a: 0200 addi s0,sp,256 + 293c: 0e04 addi s1,sp,784 + 293e: 08090003 lb zero,128(s2) + 2942: 0100 addi s0,sp,128 + 2944: 0200 addi s0,sp,256 + 2946: 0e04 addi s1,sp,784 + 2948: 28090003 lb zero,640(s2) + 294c: 0100 addi s0,sp,128 + 294e: 0200 addi s0,sp,256 + 2950: 0e04 addi s1,sp,784 + 2952: 00090003 lb zero,0(s2) + 2956: 0100 addi s0,sp,128 + 2958: 0200 addi s0,sp,256 + 295a: 0e04 addi s1,sp,784 + 295c: 00090003 lb zero,0(s2) + 2960: 0100 addi s0,sp,128 + 2962: 0200 addi s0,sp,256 + 2964: 0e04 addi s1,sp,784 + 2966: 00090003 lb zero,0(s2) + 296a: 0100 addi s0,sp,128 + 296c: 0200 addi s0,sp,256 + 296e: 0e04 addi s1,sp,784 + 2970: 00090003 lb zero,0(s2) + 2974: 0100 addi s0,sp,128 + 2976: 0200 addi s0,sp,256 + 2978: 0e04 addi s1,sp,784 + 297a: 00090003 lb zero,0(s2) + 297e: 0100 addi s0,sp,128 + 2980: 0200 addi s0,sp,256 + 2982: 0e04 addi s1,sp,784 + 2984: 00090003 lb zero,0(s2) + 2988: 0100 addi s0,sp,128 + 298a: 0200 addi s0,sp,256 + 298c: 0e04 addi s1,sp,784 + 298e: 00090003 lb zero,0(s2) + 2992: 0100 addi s0,sp,128 + 2994: 0200 addi s0,sp,256 + 2996: 0e04 addi s1,sp,784 + 2998: 00090003 lb zero,0(s2) + 299c: 0100 addi s0,sp,128 + 299e: 0200 addi s0,sp,256 + 29a0: 0e04 addi s1,sp,784 + 29a2: 00090003 lb zero,0(s2) + 29a6: 0100 addi s0,sp,128 + 29a8: 0200 addi s0,sp,256 + 29aa: 0e04 addi s1,sp,784 + 29ac: 00090003 lb zero,0(s2) + 29b0: 0100 addi s0,sp,128 + 29b2: 0200 addi s0,sp,256 + 29b4: 0e04 addi s1,sp,784 + 29b6: 08090003 lb zero,128(s2) + 29ba: 0100 addi s0,sp,128 + 29bc: 0200 addi s0,sp,256 + 29be: 0e04 addi s1,sp,784 + 29c0: 04090003 lb zero,64(s2) + 29c4: 0100 addi s0,sp,128 + 29c6: 0200 addi s0,sp,256 + 29c8: 0e04 addi s1,sp,784 + 29ca: 04090003 lb zero,64(s2) + 29ce: 0100 addi s0,sp,128 + 29d0: 0200 addi s0,sp,256 + 29d2: 0e04 addi s1,sp,784 + 29d4: 08090003 lb zero,128(s2) + 29d8: 0100 addi s0,sp,128 + 29da: 0200 addi s0,sp,256 + 29dc: 0f04 addi s1,sp,912 + 29de: 04090003 lb zero,64(s2) + 29e2: 0100 addi s0,sp,128 + 29e4: 0200 addi s0,sp,256 + 29e6: 1104 addi s1,sp,160 + 29e8: 04090003 lb zero,64(s2) + 29ec: 0100 addi s0,sp,128 + 29ee: 0200 addi s0,sp,256 + 29f0: 1104 addi s1,sp,160 + 29f2: 0c090003 lb zero,192(s2) + 29f6: 0100 addi s0,sp,128 + 29f8: 0200 addi s0,sp,256 + 29fa: 1104 addi s1,sp,160 + 29fc: 18090003 lb zero,384(s2) + 2a00: 0100 addi s0,sp,128 + 2a02: 0200 addi s0,sp,256 + 2a04: 1104 addi s1,sp,160 + 2a06: 00090003 lb zero,0(s2) + 2a0a: 0100 addi s0,sp,128 + 2a0c: 0200 addi s0,sp,256 + 2a0e: 1104 addi s1,sp,160 + 2a10: 00090003 lb zero,0(s2) + 2a14: 0100 addi s0,sp,128 + 2a16: 0200 addi s0,sp,256 + 2a18: 1104 addi s1,sp,160 + 2a1a: 00090003 lb zero,0(s2) + 2a1e: 0100 addi s0,sp,128 + 2a20: 0200 addi s0,sp,256 + 2a22: 1104 addi s1,sp,160 + 2a24: 00090003 lb zero,0(s2) + 2a28: 0100 addi s0,sp,128 + 2a2a: 0200 addi s0,sp,256 + 2a2c: 1104 addi s1,sp,160 + 2a2e: 00090003 lb zero,0(s2) + 2a32: 0100 addi s0,sp,128 + 2a34: 0200 addi s0,sp,256 + 2a36: 1104 addi s1,sp,160 + 2a38: 00090003 lb zero,0(s2) + 2a3c: 0100 addi s0,sp,128 + 2a3e: 0200 addi s0,sp,256 + 2a40: 1104 addi s1,sp,160 + 2a42: 00090003 lb zero,0(s2) + 2a46: 0100 addi s0,sp,128 + 2a48: 0200 addi s0,sp,256 + 2a4a: 1104 addi s1,sp,160 + 2a4c: 00090003 lb zero,0(s2) + 2a50: 0100 addi s0,sp,128 + 2a52: 0200 addi s0,sp,256 + 2a54: 1104 addi s1,sp,160 + 2a56: 00090003 lb zero,0(s2) + 2a5a: 0100 addi s0,sp,128 + 2a5c: 0200 addi s0,sp,256 + 2a5e: 1104 addi s1,sp,160 + 2a60: 00090003 lb zero,0(s2) + 2a64: 0100 addi s0,sp,128 + 2a66: 0200 addi s0,sp,256 + 2a68: 1104 addi s1,sp,160 + 2a6a: 04090003 lb zero,64(s2) + 2a6e: 0100 addi s0,sp,128 + 2a70: 0200 addi s0,sp,256 + 2a72: 1104 addi s1,sp,160 + 2a74: 08090003 lb zero,128(s2) + 2a78: 0100 addi s0,sp,128 + 2a7a: 0200 addi s0,sp,256 + 2a7c: 1104 addi s1,sp,160 + 2a7e: 04090003 lb zero,64(s2) + 2a82: 0100 addi s0,sp,128 + 2a84: 0200 addi s0,sp,256 + 2a86: 1104 addi s1,sp,160 + 2a88: 08090003 lb zero,128(s2) + 2a8c: 0100 addi s0,sp,128 + 2a8e: 0200 addi s0,sp,256 + 2a90: 1204 addi s1,sp,288 + 2a92: 04090003 lb zero,64(s2) + 2a96: 0100 addi s0,sp,128 + 2a98: 0200 addi s0,sp,256 + 2a9a: 1404 addi s1,sp,544 + 2a9c: 04090003 lb zero,64(s2) + 2aa0: 0100 addi s0,sp,128 + 2aa2: 0200 addi s0,sp,256 + 2aa4: 1404 addi s1,sp,544 + 2aa6: 00090003 lb zero,0(s2) + 2aaa: 0100 addi s0,sp,128 + 2aac: 0200 addi s0,sp,256 + 2aae: 1404 addi s1,sp,544 + 2ab0: 00090003 lb zero,0(s2) + 2ab4: 0100 addi s0,sp,128 + 2ab6: 0200 addi s0,sp,256 + 2ab8: 1404 addi s1,sp,544 + 2aba: 00090003 lb zero,0(s2) + 2abe: 0100 addi s0,sp,128 + 2ac0: 0200 addi s0,sp,256 + 2ac2: 1404 addi s1,sp,544 + 2ac4: 00090003 lb zero,0(s2) + 2ac8: 0100 addi s0,sp,128 + 2aca: 0200 addi s0,sp,256 + 2acc: 1404 addi s1,sp,544 + 2ace: 00090003 lb zero,0(s2) + 2ad2: 0100 addi s0,sp,128 + 2ad4: 0200 addi s0,sp,256 + 2ad6: 1404 addi s1,sp,544 + 2ad8: 18090003 lb zero,384(s2) + 2adc: 0100 addi s0,sp,128 + 2ade: 0200 addi s0,sp,256 + 2ae0: 1404 addi s1,sp,544 + 2ae2: 08090003 lb zero,128(s2) + 2ae6: 0100 addi s0,sp,128 + 2ae8: 0200 addi s0,sp,256 + 2aea: 1404 addi s1,sp,544 + 2aec: 04090003 lb zero,64(s2) + 2af0: 0100 addi s0,sp,128 + 2af2: 0200 addi s0,sp,256 + 2af4: 1404 addi s1,sp,544 + 2af6: 00090003 lb zero,0(s2) + 2afa: 0100 addi s0,sp,128 + 2afc: 0200 addi s0,sp,256 + 2afe: 1404 addi s1,sp,544 + 2b00: 04090003 lb zero,64(s2) + 2b04: 0100 addi s0,sp,128 + 2b06: 0200 addi s0,sp,256 + 2b08: 1404 addi s1,sp,544 + 2b0a: 00090003 lb zero,0(s2) + 2b0e: 0100 addi s0,sp,128 + 2b10: 0200 addi s0,sp,256 + 2b12: 1404 addi s1,sp,544 + 2b14: 00090003 lb zero,0(s2) + 2b18: 0100 addi s0,sp,128 + 2b1a: 0200 addi s0,sp,256 + 2b1c: 1404 addi s1,sp,544 + 2b1e: 00090003 lb zero,0(s2) + 2b22: 0100 addi s0,sp,128 + 2b24: 0200 addi s0,sp,256 + 2b26: 1404 addi s1,sp,544 + 2b28: 00090003 lb zero,0(s2) + 2b2c: 0100 addi s0,sp,128 + 2b2e: 0200 addi s0,sp,256 + 2b30: 1404 addi s1,sp,544 + 2b32: 00090003 lb zero,0(s2) + 2b36: 0100 addi s0,sp,128 + 2b38: 0200 addi s0,sp,256 + 2b3a: 1404 addi s1,sp,544 + 2b3c: 04090003 lb zero,64(s2) + 2b40: 0100 addi s0,sp,128 + 2b42: 0200 addi s0,sp,256 + 2b44: 1404 addi s1,sp,544 + 2b46: 04090003 lb zero,64(s2) + 2b4a: 0100 addi s0,sp,128 + 2b4c: 0200 addi s0,sp,256 + 2b4e: 1404 addi s1,sp,544 + 2b50: 04090003 lb zero,64(s2) + 2b54: 0100 addi s0,sp,128 + 2b56: 0200 addi s0,sp,256 + 2b58: 1404 addi s1,sp,544 + 2b5a: 00090003 lb zero,0(s2) + 2b5e: 0100 addi s0,sp,128 + 2b60: 0200 addi s0,sp,256 + 2b62: 1404 addi s1,sp,544 + 2b64: 04090003 lb zero,64(s2) + 2b68: 0100 addi s0,sp,128 + 2b6a: 0200 addi s0,sp,256 + 2b6c: 1404 addi s1,sp,544 + 2b6e: 00090003 lb zero,0(s2) + 2b72: 0100 addi s0,sp,128 + 2b74: 0200 addi s0,sp,256 + 2b76: 1404 addi s1,sp,544 + 2b78: 00090003 lb zero,0(s2) + 2b7c: 0100 addi s0,sp,128 + 2b7e: 0200 addi s0,sp,256 + 2b80: 1404 addi s1,sp,544 + 2b82: 00090003 lb zero,0(s2) + 2b86: 0100 addi s0,sp,128 + 2b88: 0200 addi s0,sp,256 + 2b8a: 1404 addi s1,sp,544 + 2b8c: 00090003 lb zero,0(s2) + 2b90: 0100 addi s0,sp,128 + 2b92: 0200 addi s0,sp,256 + 2b94: 1404 addi s1,sp,544 + 2b96: 00090003 lb zero,0(s2) + 2b9a: 0100 addi s0,sp,128 + 2b9c: 0200 addi s0,sp,256 + 2b9e: 1404 addi s1,sp,544 + 2ba0: 00090003 lb zero,0(s2) + 2ba4: 0100 addi s0,sp,128 + 2ba6: 0200 addi s0,sp,256 + 2ba8: 1404 addi s1,sp,544 + 2baa: 00090003 lb zero,0(s2) + 2bae: 0100 addi s0,sp,128 + 2bb0: 0200 addi s0,sp,256 + 2bb2: 1404 addi s1,sp,544 + 2bb4: 00090003 lb zero,0(s2) + 2bb8: 0100 addi s0,sp,128 + 2bba: 0200 addi s0,sp,256 + 2bbc: 1404 addi s1,sp,544 + 2bbe: 00090003 lb zero,0(s2) + 2bc2: 0100 addi s0,sp,128 + 2bc4: 0200 addi s0,sp,256 + 2bc6: 1404 addi s1,sp,544 + 2bc8: 00090003 lb zero,0(s2) + 2bcc: 0100 addi s0,sp,128 + 2bce: 0200 addi s0,sp,256 + 2bd0: 1404 addi s1,sp,544 + 2bd2: 00090003 lb zero,0(s2) + 2bd6: 0100 addi s0,sp,128 + 2bd8: 0200 addi s0,sp,256 + 2bda: 1404 addi s1,sp,544 + 2bdc: 00090003 lb zero,0(s2) + 2be0: 0100 addi s0,sp,128 + 2be2: 0200 addi s0,sp,256 + 2be4: 1404 addi s1,sp,544 + 2be6: 00090003 lb zero,0(s2) + 2bea: 0100 addi s0,sp,128 + 2bec: 0200 addi s0,sp,256 + 2bee: 1404 addi s1,sp,544 + 2bf0: 00090003 lb zero,0(s2) + 2bf4: 0100 addi s0,sp,128 + 2bf6: 0200 addi s0,sp,256 + 2bf8: 1404 addi s1,sp,544 + 2bfa: 00090003 lb zero,0(s2) + 2bfe: 0100 addi s0,sp,128 + 2c00: 0200 addi s0,sp,256 + 2c02: 1404 addi s1,sp,544 + 2c04: 00090003 lb zero,0(s2) + 2c08: 0100 addi s0,sp,128 + 2c0a: 0200 addi s0,sp,256 + 2c0c: 1404 addi s1,sp,544 + 2c0e: 00090003 lb zero,0(s2) + 2c12: 0100 addi s0,sp,128 + 2c14: 0200 addi s0,sp,256 + 2c16: 1404 addi s1,sp,544 + 2c18: 00090003 lb zero,0(s2) + 2c1c: 0100 addi s0,sp,128 + 2c1e: 0200 addi s0,sp,256 + 2c20: 1404 addi s1,sp,544 + 2c22: 00090003 lb zero,0(s2) + 2c26: 0100 addi s0,sp,128 + 2c28: 0200 addi s0,sp,256 + 2c2a: 1404 addi s1,sp,544 + 2c2c: 00090003 lb zero,0(s2) + 2c30: 0100 addi s0,sp,128 + 2c32: 0200 addi s0,sp,256 + 2c34: 1404 addi s1,sp,544 + 2c36: 00090003 lb zero,0(s2) + 2c3a: 0100 addi s0,sp,128 + 2c3c: 0200 addi s0,sp,256 + 2c3e: 1404 addi s1,sp,544 + 2c40: 00090003 lb zero,0(s2) + 2c44: 0100 addi s0,sp,128 + 2c46: 0200 addi s0,sp,256 + 2c48: 1404 addi s1,sp,544 + 2c4a: 00090003 lb zero,0(s2) + 2c4e: 0100 addi s0,sp,128 + 2c50: 0200 addi s0,sp,256 + 2c52: 1404 addi s1,sp,544 + 2c54: 00090003 lb zero,0(s2) + 2c58: 0100 addi s0,sp,128 + 2c5a: 0200 addi s0,sp,256 + 2c5c: 1404 addi s1,sp,544 + 2c5e: 00090003 lb zero,0(s2) + 2c62: 0100 addi s0,sp,128 + 2c64: 0200 addi s0,sp,256 + 2c66: 1404 addi s1,sp,544 + 2c68: 50090003 lb zero,1280(s2) + 2c6c: 0100 addi s0,sp,128 + 2c6e: 0200 addi s0,sp,256 + 2c70: 1404 addi s1,sp,544 + 2c72: 00090003 lb zero,0(s2) + 2c76: 0100 addi s0,sp,128 + 2c78: 0200 addi s0,sp,256 + 2c7a: 1404 addi s1,sp,544 + 2c7c: 00090003 lb zero,0(s2) + 2c80: 0100 addi s0,sp,128 + 2c82: 0200 addi s0,sp,256 + 2c84: 1404 addi s1,sp,544 + 2c86: 00090003 lb zero,0(s2) + 2c8a: 0100 addi s0,sp,128 + 2c8c: 0200 addi s0,sp,256 + 2c8e: 1404 addi s1,sp,544 + 2c90: 00090003 lb zero,0(s2) + 2c94: 0100 addi s0,sp,128 + 2c96: 0200 addi s0,sp,256 + 2c98: 1404 addi s1,sp,544 + 2c9a: 00090003 lb zero,0(s2) + 2c9e: 0100 addi s0,sp,128 + 2ca0: 0200 addi s0,sp,256 + 2ca2: 1404 addi s1,sp,544 + 2ca4: 00090003 lb zero,0(s2) + 2ca8: 0100 addi s0,sp,128 + 2caa: 0200 addi s0,sp,256 + 2cac: 1404 addi s1,sp,544 + 2cae: 04090003 lb zero,64(s2) + 2cb2: 0100 addi s0,sp,128 + 2cb4: 0200 addi s0,sp,256 + 2cb6: 1404 addi s1,sp,544 + 2cb8: 00090003 lb zero,0(s2) + 2cbc: 0100 addi s0,sp,128 + 2cbe: 0200 addi s0,sp,256 + 2cc0: 1404 addi s1,sp,544 + 2cc2: 00090003 lb zero,0(s2) + 2cc6: 0100 addi s0,sp,128 + 2cc8: 0200 addi s0,sp,256 + 2cca: 1404 addi s1,sp,544 + 2ccc: 00090003 lb zero,0(s2) + 2cd0: 0100 addi s0,sp,128 + 2cd2: 0200 addi s0,sp,256 + 2cd4: 1404 addi s1,sp,544 + 2cd6: 00090003 lb zero,0(s2) + 2cda: 0100 addi s0,sp,128 + 2cdc: 0200 addi s0,sp,256 + 2cde: 2604 fld fs1,8(a2) + 2ce0: 04090003 lb zero,64(s2) + 2ce4: 0100 addi s0,sp,128 + 2ce6: 0200 addi s0,sp,256 + 2ce8: 2604 fld fs1,8(a2) + 2cea: 00090003 lb zero,0(s2) + 2cee: 0100 addi s0,sp,128 + 2cf0: 0200 addi s0,sp,256 + 2cf2: 2604 fld fs1,8(a2) + 2cf4: 14090003 lb zero,320(s2) + 2cf8: 0100 addi s0,sp,128 + 2cfa: 0200 addi s0,sp,256 + 2cfc: 0204 addi s1,sp,256 + 2cfe: 04090103 lb sp,64(s2) + 2d02: 0100 addi s0,sp,128 + 2d04: 0200 addi s0,sp,256 + 2d06: 0204 addi s1,sp,256 + 2d08: 04090003 lb zero,64(s2) + 2d0c: 0100 addi s0,sp,128 + 2d0e: 0200 addi s0,sp,256 + 2d10: 0604 addi s1,sp,768 + 2d12: 04090003 lb zero,64(s2) + 2d16: 0100 addi s0,sp,128 + 2d18: 0200 addi s0,sp,256 + 2d1a: 0604 addi s1,sp,768 + 2d1c: 00090003 lb zero,0(s2) + 2d20: 0100 addi s0,sp,128 + 2d22: 0200 addi s0,sp,256 + 2d24: 0804 addi s1,sp,16 + 2d26: 08090003 lb zero,128(s2) + 2d2a: 0100 addi s0,sp,128 + 2d2c: 0200 addi s0,sp,256 + 2d2e: 0804 addi s1,sp,16 + 2d30: 00090003 lb zero,0(s2) + 2d34: 0100 addi s0,sp,128 + 2d36: 0200 addi s0,sp,256 + 2d38: 0804 addi s1,sp,16 + 2d3a: 00090003 lb zero,0(s2) + 2d3e: 0100 addi s0,sp,128 + 2d40: 0200 addi s0,sp,256 + 2d42: 0804 addi s1,sp,16 + 2d44: 00090003 lb zero,0(s2) + 2d48: 0100 addi s0,sp,128 + 2d4a: 0200 addi s0,sp,256 + 2d4c: 0a04 addi s1,sp,272 + 2d4e: 0c090003 lb zero,192(s2) + 2d52: 0100 addi s0,sp,128 + 2d54: 0200 addi s0,sp,256 + 2d56: 0a04 addi s1,sp,272 + 2d58: 00090003 lb zero,0(s2) + 2d5c: 0100 addi s0,sp,128 + 2d5e: 0200 addi s0,sp,256 + 2d60: 0a04 addi s1,sp,272 + 2d62: 00090003 lb zero,0(s2) + 2d66: 0100 addi s0,sp,128 + 2d68: 0200 addi s0,sp,256 + 2d6a: 0a04 addi s1,sp,272 + 2d6c: 04090003 lb zero,64(s2) + 2d70: 0100 addi s0,sp,128 + 2d72: 0200 addi s0,sp,256 + 2d74: 0a04 addi s1,sp,272 + 2d76: 08090003 lb zero,128(s2) + 2d7a: 0100 addi s0,sp,128 + 2d7c: 0200 addi s0,sp,256 + 2d7e: 0904 addi s1,sp,144 + 2d80: 04090003 lb zero,64(s2) + 2d84: 0100 addi s0,sp,128 + 2d86: 0200 addi s0,sp,256 + 2d88: 0904 addi s1,sp,144 + 2d8a: 00090003 lb zero,0(s2) + 2d8e: 0100 addi s0,sp,128 + 2d90: 0200 addi s0,sp,256 + 2d92: 1804 addi s1,sp,48 + 2d94: 08090003 lb zero,128(s2) + 2d98: 0100 addi s0,sp,128 + 2d9a: 0200 addi s0,sp,256 + 2d9c: 1804 addi s1,sp,48 + 2d9e: 0c090003 lb zero,192(s2) + 2da2: 0100 addi s0,sp,128 + 2da4: 0200 addi s0,sp,256 + 2da6: 1a04 addi s1,sp,304 + 2da8: 04090003 lb zero,64(s2) + 2dac: 0100 addi s0,sp,128 + 2dae: 0200 addi s0,sp,256 + 2db0: 1a04 addi s1,sp,304 + 2db2: 00090003 lb zero,0(s2) + 2db6: 0100 addi s0,sp,128 + 2db8: 0200 addi s0,sp,256 + 2dba: 1a04 addi s1,sp,304 + 2dbc: 00090003 lb zero,0(s2) + 2dc0: 0100 addi s0,sp,128 + 2dc2: 0200 addi s0,sp,256 + 2dc4: 1a04 addi s1,sp,304 + 2dc6: 00090003 lb zero,0(s2) + 2dca: 0100 addi s0,sp,128 + 2dcc: 0306 slli t1,t1,0x1 + 2dce: 0900 addi s0,sp,144 + 2dd0: 0008 0x8 + 2dd2: 0001 nop + 2dd4: 0402 c.slli64 s0 + 2dd6: 00030677 0x30677 + 2dda: 1009 c.nop -30 + 2ddc: 0100 addi s0,sp,128 + 2dde: 0200 addi s0,sp,256 + 2de0: 7704 flw fs1,40(a4) + 2de2: 00090003 lb zero,0(s2) + 2de6: 0100 addi s0,sp,128 + 2de8: 0200 addi s0,sp,256 + 2dea: 7704 flw fs1,40(a4) + 2dec: 00090003 lb zero,0(s2) + 2df0: 0100 addi s0,sp,128 + 2df2: 0200 addi s0,sp,256 + 2df4: 7704 flw fs1,40(a4) + 2df6: 00090003 lb zero,0(s2) + 2dfa: 0100 addi s0,sp,128 + 2dfc: 0200 addi s0,sp,256 + 2dfe: 7704 flw fs1,40(a4) + 2e00: 00090003 lb zero,0(s2) + 2e04: 0100 addi s0,sp,128 + 2e06: 0200 addi s0,sp,256 + 2e08: 7704 flw fs1,40(a4) + 2e0a: 00090003 lb zero,0(s2) + 2e0e: 0100 addi s0,sp,128 + 2e10: 0200 addi s0,sp,256 + 2e12: 7704 flw fs1,40(a4) + 2e14: 00090003 lb zero,0(s2) + 2e18: 0100 addi s0,sp,128 + 2e1a: 0200 addi s0,sp,256 + 2e1c: 7704 flw fs1,40(a4) + 2e1e: 00090003 lb zero,0(s2) + 2e22: 0100 addi s0,sp,128 + 2e24: 0105 addi sp,sp,1 + 2e26: 0200 addi s0,sp,256 + 2e28: 7704 flw fs1,40(a4) + 2e2a: 0306 slli t1,t1,0x1 + 2e2c: 0904 addi s1,sp,144 + 2e2e: 001c 0x1c + 2e30: 0501 addi a0,a0,0 + 2e32: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> + 2e36: 097c0377 0x97c0377 + 2e3a: 0004 0x4 + 2e3c: 0001 nop + 2e3e: 0402 c.slli64 s0 + 2e40: 00030677 0x30677 + 2e44: 0409 addi s0,s0,2 + 2e46: 0100 addi s0,sp,128 + 2e48: 0200 addi s0,sp,256 + 2e4a: 7704 flw fs1,40(a4) + 2e4c: 00090003 lb zero,0(s2) + 2e50: 0100 addi s0,sp,128 + 2e52: 0200 addi s0,sp,256 + 2e54: 7704 flw fs1,40(a4) + 2e56: 00090103 lb sp,0(s2) + 2e5a: 0100 addi s0,sp,128 + 2e5c: 0200 addi s0,sp,256 + 2e5e: 7704 flw fs1,40(a4) + 2e60: 00090003 lb zero,0(s2) + 2e64: 0100 addi s0,sp,128 + 2e66: 0200 addi s0,sp,256 + 2e68: 7704 flw fs1,40(a4) + 2e6a: 00090003 lb zero,0(s2) + 2e6e: 0100 addi s0,sp,128 + 2e70: 0200 addi s0,sp,256 + 2e72: 7704 flw fs1,40(a4) + 2e74: 00090203 lb tp,0(s2) + 2e78: 0100 addi s0,sp,128 + 2e7a: 0105 addi sp,sp,1 + 2e7c: 0200 addi s0,sp,256 + 2e7e: 7704 flw fs1,40(a4) + 2e80: 0306 slli t1,t1,0x1 + 2e82: 0901 addi s2,s2,0 + 2e84: 0000 unimp + 2e86: 0501 addi a0,a0,0 + 2e88: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> + 2e8c: 09790307 0x9790307 + 2e90: 0030 addi a2,sp,8 + 2e92: 0001 nop + 2e94: 0402 c.slli64 s0 + 2e96: 02030607 0x2030607 + 2e9a: 0409 addi s0,s0,2 + 2e9c: 0100 addi s0,sp,128 + 2e9e: 0200 addi s0,sp,256 + 2ea0: 2f04 fld fs1,24(a4) + 2ea2: 0c090003 lb zero,192(s2) + 2ea6: 0100 addi s0,sp,128 + 2ea8: 0200 addi s0,sp,256 + 2eaa: 2f04 fld fs1,24(a4) + 2eac: 00090103 lb sp,0(s2) + 2eb0: 0100 addi s0,sp,128 + 2eb2: 0200 addi s0,sp,256 + 2eb4: 2f04 fld fs1,24(a4) + 2eb6: 00090003 lb zero,0(s2) + 2eba: 0100 addi s0,sp,128 + 2ebc: 0200 addi s0,sp,256 + 2ebe: 2f04 fld fs1,24(a4) + 2ec0: 00090003 lb zero,0(s2) + 2ec4: 0100 addi s0,sp,128 + 2ec6: 0306 slli t1,t1,0x1 + 2ec8: 0900 addi s0,sp,144 + 2eca: 0008 0x8 + 2ecc: 0001 nop + 2ece: 0402 c.slli64 s0 + 2ed0: 0304 addi s1,sp,384 + 2ed2: 097e slli s2,s2,0x1f + 2ed4: 001c 0x1c + 2ed6: 0001 nop + 2ed8: 0402 c.slli64 s0 + 2eda: 0604 addi s1,sp,768 + 2edc: 04090103 lb sp,64(s2) + 2ee0: 0100 addi s0,sp,128 + 2ee2: 0306 slli t1,t1,0x1 + 2ee4: 0900 addi s0,sp,144 + 2ee6: 0004 0x4 + 2ee8: 0001 nop + 2eea: 0402 c.slli64 s0 + 2eec: 0103063b 0x103063b + 2ef0: 0809 addi a6,a6,2 + 2ef2: 0100 addi s0,sp,128 + 2ef4: 0200 addi s0,sp,256 + 2ef6: 3b04 fld fs1,48(a4) + 2ef8: 00090003 lb zero,0(s2) + 2efc: 0100 addi s0,sp,128 + 2efe: 0200 addi s0,sp,256 + 2f00: 3b04 fld fs1,48(a4) + 2f02: 00090003 lb zero,0(s2) + 2f06: 0100 addi s0,sp,128 + 2f08: 0200 addi s0,sp,256 + 2f0a: 3b04 fld fs1,48(a4) + 2f0c: 08090003 lb zero,128(s2) + 2f10: 0100 addi s0,sp,128 + 2f12: 0200 addi s0,sp,256 + 2f14: 3c04 fld fs1,56(s0) + 2f16: 08090003 lb zero,128(s2) + 2f1a: 0100 addi s0,sp,128 + 2f1c: 0200 addi s0,sp,256 + 2f1e: 3e04 fld fs1,56(a2) + 2f20: 08090003 lb zero,128(s2) + 2f24: 0100 addi s0,sp,128 + 2f26: 0200 addi s0,sp,256 + 2f28: 3e04 fld fs1,56(a2) + 2f2a: 1c090003 lb zero,448(s2) + 2f2e: 0100 addi s0,sp,128 + 2f30: 0200 addi s0,sp,256 + 2f32: 4b04 lw s1,16(a4) + 2f34: 04090003 lb zero,64(s2) + 2f38: 0100 addi s0,sp,128 + 2f3a: 0200 addi s0,sp,256 + 2f3c: 4b04 lw s1,16(a4) + 2f3e: 00090003 lb zero,0(s2) + 2f42: 0100 addi s0,sp,128 + 2f44: 0200 addi s0,sp,256 + 2f46: 4c04 lw s1,24(s0) + 2f48: 08090003 lb zero,128(s2) + 2f4c: 0100 addi s0,sp,128 + 2f4e: 0200 addi s0,sp,256 + 2f50: 4c04 lw s1,24(s0) + 2f52: 00090003 lb zero,0(s2) + 2f56: 0100 addi s0,sp,128 + 2f58: 0200 addi s0,sp,256 + 2f5a: 4c04 lw s1,24(s0) + 2f5c: 00090003 lb zero,0(s2) + 2f60: 0100 addi s0,sp,128 + 2f62: 0200 addi s0,sp,256 + 2f64: 4c04 lw s1,24(s0) + 2f66: 00090003 lb zero,0(s2) + 2f6a: 0100 addi s0,sp,128 + 2f6c: 0200 addi s0,sp,256 + 2f6e: 4e04 lw s1,24(a2) + 2f70: 0c090003 lb zero,192(s2) + 2f74: 0100 addi s0,sp,128 + 2f76: 0200 addi s0,sp,256 + 2f78: 4e04 lw s1,24(a2) + 2f7a: 00090003 lb zero,0(s2) + 2f7e: 0100 addi s0,sp,128 + 2f80: 0200 addi s0,sp,256 + 2f82: 4e04 lw s1,24(a2) + 2f84: 00090003 lb zero,0(s2) + 2f88: 0100 addi s0,sp,128 + 2f8a: 0200 addi s0,sp,256 + 2f8c: 4e04 lw s1,24(a2) + 2f8e: 04090003 lb zero,64(s2) + 2f92: 0100 addi s0,sp,128 + 2f94: 0200 addi s0,sp,256 + 2f96: 4e04 lw s1,24(a2) + 2f98: 08090003 lb zero,128(s2) + 2f9c: 0100 addi s0,sp,128 + 2f9e: 0200 addi s0,sp,256 + 2fa0: 4d04 lw s1,24(a0) + 2fa2: 04090003 lb zero,64(s2) + 2fa6: 0100 addi s0,sp,128 + 2fa8: 0200 addi s0,sp,256 + 2faa: 4d04 lw s1,24(a0) + 2fac: 00090003 lb zero,0(s2) + 2fb0: 0100 addi s0,sp,128 + 2fb2: 0200 addi s0,sp,256 + 2fb4: 5d04 lw s1,56(a0) + 2fb6: 08090003 lb zero,128(s2) + 2fba: 0100 addi s0,sp,128 + 2fbc: 0200 addi s0,sp,256 + 2fbe: 5d04 lw s1,56(a0) + 2fc0: 00090003 lb zero,0(s2) + 2fc4: 0100 addi s0,sp,128 + 2fc6: 0200 addi s0,sp,256 + 2fc8: 5d04 lw s1,56(a0) + 2fca: 00090003 lb zero,0(s2) + 2fce: 0100 addi s0,sp,128 + 2fd0: 0200 addi s0,sp,256 + 2fd2: 5d04 lw s1,56(a0) + 2fd4: 0c090003 lb zero,192(s2) + 2fd8: 0100 addi s0,sp,128 + 2fda: 0306 slli t1,t1,0x1 + 2fdc: 0900 addi s0,sp,144 + 2fde: 0004 0x4 + 2fe0: 0001 nop + 2fe2: 0402 c.slli64 s0 + 2fe4: 0003063f 01000809 0x10008090003063f + 2fec: 0200 addi s0,sp,256 + 2fee: 4704 lw s1,8(a4) + 2ff0: 0306 slli t1,t1,0x1 + 2ff2: 0900 addi s0,sp,144 + 2ff4: 0018 0x18 + 2ff6: 0001 nop + 2ff8: 0402 c.slli64 s0 + 2ffa: 034a slli t1,t1,0x12 + 2ffc: 0900 addi s0,sp,144 + 2ffe: 0008 0x8 + 3000: 0001 nop + 3002: 0402 c.slli64 s0 + 3004: 064a slli a2,a2,0x12 + 3006: 0c090003 lb zero,192(s2) + 300a: 0100 addi s0,sp,128 + 300c: 0306 slli t1,t1,0x1 + 300e: 0900 addi s0,sp,144 + 3010: 0008 0x8 + 3012: 0901 addi s2,s2,0 + 3014: 0034 addi a3,sp,8 + 3016: 0100 addi s0,sp,128 + 3018: de01 beqz a2,2f30 <_start-0x7fffd0d0> + 301a: 0002 c.slli64 zero + 301c: 0300 addi s0,sp,384 + 301e: a300 fsd fs0,0(a4) + 3020: 0000 unimp 3022: 0100 addi s0,sp,128 - 3024: 0200 addi s0,sp,256 - 3026: 5d04 lw s1,56(a0) - 3028: 0c090003 lb zero,192(s2) - 302c: 0100 addi s0,sp,128 - 302e: 0306 slli t1,t1,0x1 - 3030: 0900 addi s0,sp,144 - 3032: 0004 0x4 - 3034: 0001 nop - 3036: 0402 c.slli64 s0 - 3038: 0003063f 01000809 0x10008090003063f - 3040: 0200 addi s0,sp,256 - 3042: 4704 lw s1,8(a4) - 3044: 0306 slli t1,t1,0x1 - 3046: 0900 addi s0,sp,144 - 3048: 0018 0x18 - 304a: 0001 nop - 304c: 0402 c.slli64 s0 - 304e: 034a slli t1,t1,0x12 - 3050: 0900 addi s0,sp,144 - 3052: 0008 0x8 - 3054: 0001 nop - 3056: 0402 c.slli64 s0 - 3058: 064a slli a2,a2,0x12 - 305a: 0c090003 lb zero,192(s2) - 305e: 0100 addi s0,sp,128 - 3060: 0306 slli t1,t1,0x1 - 3062: 0900 addi s0,sp,144 - 3064: 0008 0x8 - 3066: 0901 addi s2,s2,0 - 3068: 0034 addi a3,sp,8 - 306a: 0100 addi s0,sp,128 - 306c: de01 beqz a2,2f84 <_start-0x7fffd07c> - 306e: 0002 c.slli64 zero - 3070: 0300 addi s0,sp,384 - 3072: a300 fsd fs0,0(a4) - 3074: 0000 unimp - 3076: 0100 addi s0,sp,128 - 3078: fb01 bnez a4,2f88 <_start-0x7fffd078> - 307a: 0d0e slli s10,s10,0x3 - 307c: 0100 addi s0,sp,128 - 307e: 0101 addi sp,sp,0 - 3080: 0001 nop + 3024: fb01 bnez a4,2f34 <_start-0x7fffd0cc> + 3026: 0d0e slli s10,s10,0x3 + 3028: 0100 addi s0,sp,128 + 302a: 0101 addi sp,sp,0 + 302c: 0001 nop + 302e: 0000 unimp + 3030: 0001 nop + 3032: 0100 addi s0,sp,128 + 3034: 2e2e fld ft8,200(sp) + 3036: 2f2e2e2f 0x2f2e2e2f + 303a: 2e2e fld ft8,200(sp) + 303c: 2f2e2e2f 0x2f2e2e2f + 3040: 6972 flw fs2,28(sp) + 3042: 2d766373 csrrsi t1,0x2d7,12 + 3046: 2f636367 0x2f636367 + 304a: 696c flw fa1,84(a0) + 304c: 6762 flw fa4,24(sp) + 304e: 732f6363 bltu t5,s2,3774 <_start-0x7fffc88c> + 3052: 2d74666f jal a2,49b28 <_start-0x7ffb64d8> + 3056: 7066 flw ft0,120(sp) + 3058: 2e00 fld fs0,24(a2) + 305a: 2e00 fld fs0,24(a2) + 305c: 2f2e fld ft10,200(sp) + 305e: 2e2e fld ft8,200(sp) + 3060: 2f2e2e2f 0x2f2e2e2f + 3064: 2e2e fld ft8,200(sp) + 3066: 7369722f 0x7369722f + 306a: 672d7663 bgeu s10,s2,36d6 <_start-0x7fffc92a> + 306e: 6c2f6363 bltu t5,sp,3734 <_start-0x7fffc8cc> + 3072: 6269 lui tp,0x1a + 3074: 2f636367 0x2f636367 + 3078: 2e2e fld ft8,200(sp) + 307a: 636e692f 0x636e692f + 307e: 756c flw fa1,108(a0) + 3080: 6564 flw fs1,76(a0) 3082: 0000 unimp - 3084: 0001 nop - 3086: 0100 addi s0,sp,128 - 3088: 2e2e fld ft8,200(sp) - 308a: 2f2e2e2f 0x2f2e2e2f - 308e: 2e2e fld ft8,200(sp) - 3090: 2f2e2e2f 0x2f2e2e2f - 3094: 6972 flw fs2,28(sp) - 3096: 2d766373 csrrsi t1,0x2d7,12 - 309a: 2f636367 0x2f636367 - 309e: 696c flw fa1,84(a0) - 30a0: 6762 flw fa4,24(sp) - 30a2: 732f6363 bltu t5,s2,37c8 <_start-0x7fffc838> - 30a6: 2d74666f jal a2,49b7c <_start-0x7ffb6484> - 30aa: 7066 flw ft0,120(sp) - 30ac: 2e00 fld fs0,24(a2) - 30ae: 2e00 fld fs0,24(a2) - 30b0: 2f2e fld ft10,200(sp) - 30b2: 2e2e fld ft8,200(sp) - 30b4: 2f2e2e2f 0x2f2e2e2f - 30b8: 2e2e fld ft8,200(sp) - 30ba: 7369722f 0x7369722f - 30be: 672d7663 bgeu s10,s2,372a <_start-0x7fffc8d6> - 30c2: 6c2f6363 bltu t5,sp,3788 <_start-0x7fffc878> - 30c6: 6269 lui tp,0x1a - 30c8: 2f636367 0x2f636367 - 30cc: 2e2e fld ft8,200(sp) - 30ce: 636e692f 0x636e692f - 30d2: 756c flw fa1,108(a0) - 30d4: 6564 flw fs1,76(a0) - 30d6: 0000 unimp - 30d8: 7165 addi sp,sp,-400 - 30da: 6674 flw fa3,76(a2) - 30dc: 2e32 fld ft8,264(sp) - 30de: 00010063 beqz sp,30de <_start-0x7fffcf22> - 30e2: 7300 flw fs0,32(a4) - 30e4: 7066 flw ft0,120(sp) - 30e6: 6d2d lui s10,0xb - 30e8: 6361 lui t1,0x18 - 30ea: 6968 flw fa0,84(a0) - 30ec: 656e flw fa0,216(sp) - 30ee: 682e flw fa6,200(sp) - 30f0: 0200 addi s0,sp,256 - 30f2: 0000 unimp - 30f4: 74666f73 csrrsi t5,0x746,12 - 30f8: 662d lui a2,0xb - 30fa: 2e70 fld fa2,216(a2) - 30fc: 0068 addi a0,sp,12 - 30fe: 0001 nop - 3100: 7100 flw fs0,32(a0) - 3102: 6175 addi sp,sp,368 - 3104: 2e64 fld fs1,216(a2) - 3106: 0068 addi a0,sp,12 - 3108: 0001 nop - 310a: 6c00 flw fs0,24(s0) - 310c: 6c676e6f jal t3,797d2 <_start-0x7ff8682e> - 3110: 2e676e6f jal t3,793f6 <_start-0x7ff86c0a> - 3114: 0068 addi a0,sp,12 - 3116: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> - 311a: 0105 addi sp,sp,1 - 311c: 0500 addi s0,sp,640 - 311e: e802 fsw ft0,16(sp) - 3120: 0118 addi a4,sp,128 - 3122: 0380 addi s0,sp,448 - 3124: 03050123 sb a6,34(a0) - 3128: 00090103 lb sp,0(s2) - 312c: 0100 addi s0,sp,128 - 312e: 00090003 lb zero,0(s2) - 3132: 0100 addi s0,sp,128 - 3134: 0d05 addi s10,s10,1 - 3136: 00090003 lb zero,0(s2) - 313a: 0100 addi s0,sp,128 - 313c: 0305 addi t1,t1,1 - 313e: 00090103 lb sp,0(s2) - 3142: 0100 addi s0,sp,128 - 3144: 00090003 lb zero,0(s2) - 3148: 0100 addi s0,sp,128 - 314a: 00090003 lb zero,0(s2) - 314e: 0100 addi s0,sp,128 - 3150: 00090003 lb zero,0(s2) - 3154: 0100 addi s0,sp,128 - 3156: 00090103 lb sp,0(s2) - 315a: 0100 addi s0,sp,128 - 315c: 00090003 lb zero,0(s2) - 3160: 0100 addi s0,sp,128 - 3162: 00090003 lb zero,0(s2) - 3166: 0100 addi s0,sp,128 - 3168: 00090003 lb zero,0(s2) - 316c: 0100 addi s0,sp,128 - 316e: 00090103 lb sp,0(s2) - 3172: 0100 addi s0,sp,128 - 3174: 00090203 lb tp,0(s2) - 3178: 0100 addi s0,sp,128 - 317a: 00090103 lb sp,0(s2) - 317e: 0100 addi s0,sp,128 - 3180: 00090003 lb zero,0(s2) - 3184: 0100 addi s0,sp,128 - 3186: 00090003 lb zero,0(s2) - 318a: 0100 addi s0,sp,128 - 318c: 00090003 lb zero,0(s2) - 3190: 0100 addi s0,sp,128 - 3192: 0105 addi sp,sp,1 - 3194: 0306 slli t1,t1,0x1 - 3196: 0979 addi s2,s2,30 - 3198: 0000 unimp - 319a: 0501 addi a0,a0,0 - 319c: 09070303 lb t1,144(a4) # 1a090 <_start-0x7ffe5f70> - 31a0: 0014 0x14 - 31a2: 0301 addi t1,t1,0 - 31a4: 0901 addi s2,s2,0 - 31a6: 0010 0x10 - 31a8: 0301 addi t1,t1,0 - 31aa: 097f 0x97f - 31ac: 0004 0x4 - 31ae: 0301 addi t1,t1,0 - 31b0: 0901 addi s2,s2,0 - 31b2: 0008 0x8 - 31b4: 0501 addi a0,a0,0 - 31b6: 0301 addi t1,t1,0 - 31b8: 0978 addi a4,sp,156 - 31ba: 0004 0x4 - 31bc: 0501 addi a0,a0,0 - 31be: 07030603 lb a2,112(t1) # 18070 <_start-0x7ffe7f90> - 31c2: 0409 addi s0,s0,2 + 3084: 7165 addi sp,sp,-400 + 3086: 6674 flw fa3,76(a2) + 3088: 2e32 fld ft8,264(sp) + 308a: 00010063 beqz sp,308a <_start-0x7fffcf76> + 308e: 7300 flw fs0,32(a4) + 3090: 7066 flw ft0,120(sp) + 3092: 6d2d lui s10,0xb + 3094: 6361 lui t1,0x18 + 3096: 6968 flw fa0,84(a0) + 3098: 656e flw fa0,216(sp) + 309a: 682e flw fa6,200(sp) + 309c: 0200 addi s0,sp,256 + 309e: 0000 unimp + 30a0: 74666f73 csrrsi t5,0x746,12 + 30a4: 662d lui a2,0xb + 30a6: 2e70 fld fa2,216(a2) + 30a8: 0068 addi a0,sp,12 + 30aa: 0001 nop + 30ac: 7100 flw fs0,32(a0) + 30ae: 6175 addi sp,sp,368 + 30b0: 2e64 fld fs1,216(a2) + 30b2: 0068 addi a0,sp,12 + 30b4: 0001 nop + 30b6: 6c00 flw fs0,24(s0) + 30b8: 6c676e6f jal t3,7977e <_start-0x7ff86882> + 30bc: 2e676e6f jal t3,793a2 <_start-0x7ff86c5e> + 30c0: 0068 addi a0,sp,12 + 30c2: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> + 30c6: 0105 addi sp,sp,1 + 30c8: 0500 addi s0,sp,640 + 30ca: ac02 fsd ft0,24(sp) + 30cc: 0119 addi sp,sp,6 + 30ce: 0380 addi s0,sp,448 + 30d0: 03050123 sb a6,34(a0) + 30d4: 00090103 lb sp,0(s2) + 30d8: 0100 addi s0,sp,128 + 30da: 00090003 lb zero,0(s2) + 30de: 0100 addi s0,sp,128 + 30e0: 0d05 addi s10,s10,1 + 30e2: 00090003 lb zero,0(s2) + 30e6: 0100 addi s0,sp,128 + 30e8: 0305 addi t1,t1,1 + 30ea: 00090103 lb sp,0(s2) + 30ee: 0100 addi s0,sp,128 + 30f0: 00090003 lb zero,0(s2) + 30f4: 0100 addi s0,sp,128 + 30f6: 00090003 lb zero,0(s2) + 30fa: 0100 addi s0,sp,128 + 30fc: 00090003 lb zero,0(s2) + 3100: 0100 addi s0,sp,128 + 3102: 00090103 lb sp,0(s2) + 3106: 0100 addi s0,sp,128 + 3108: 00090003 lb zero,0(s2) + 310c: 0100 addi s0,sp,128 + 310e: 00090003 lb zero,0(s2) + 3112: 0100 addi s0,sp,128 + 3114: 00090003 lb zero,0(s2) + 3118: 0100 addi s0,sp,128 + 311a: 00090103 lb sp,0(s2) + 311e: 0100 addi s0,sp,128 + 3120: 00090203 lb tp,0(s2) + 3124: 0100 addi s0,sp,128 + 3126: 00090103 lb sp,0(s2) + 312a: 0100 addi s0,sp,128 + 312c: 00090003 lb zero,0(s2) + 3130: 0100 addi s0,sp,128 + 3132: 00090003 lb zero,0(s2) + 3136: 0100 addi s0,sp,128 + 3138: 00090003 lb zero,0(s2) + 313c: 0100 addi s0,sp,128 + 313e: 0105 addi sp,sp,1 + 3140: 0306 slli t1,t1,0x1 + 3142: 0979 addi s2,s2,30 + 3144: 0000 unimp + 3146: 0501 addi a0,a0,0 + 3148: 09070303 lb t1,144(a4) # 1a090 <_start-0x7ffe5f70> + 314c: 0014 0x14 + 314e: 0301 addi t1,t1,0 + 3150: 0901 addi s2,s2,0 + 3152: 0010 0x10 + 3154: 0301 addi t1,t1,0 + 3156: 097f 0x97f + 3158: 0004 0x4 + 315a: 0301 addi t1,t1,0 + 315c: 0901 addi s2,s2,0 + 315e: 0008 0x8 + 3160: 0501 addi a0,a0,0 + 3162: 0301 addi t1,t1,0 + 3164: 0978 addi a4,sp,156 + 3166: 0004 0x4 + 3168: 0501 addi a0,a0,0 + 316a: 07030603 lb a2,112(t1) # 18070 <_start-0x7ffe7f90> + 316e: 0409 addi s0,s0,2 + 3170: 0100 addi s0,sp,128 + 3172: 0105 addi sp,sp,1 + 3174: 0306 slli t1,t1,0x1 + 3176: 0979 addi s2,s2,30 + 3178: 0000 unimp + 317a: 0501 addi a0,a0,0 + 317c: 07030603 lb a2,112(t1) + 3180: 0409 addi s0,s0,2 + 3182: 0100 addi s0,sp,128 + 3184: 0105 addi sp,sp,1 + 3186: 0306 slli t1,t1,0x1 + 3188: 0979 addi s2,s2,30 + 318a: 0000 unimp + 318c: 0501 addi a0,a0,0 + 318e: 07030603 lb a2,112(t1) + 3192: 0409 addi s0,s0,2 + 3194: 0100 addi s0,sp,128 + 3196: 0105 addi sp,sp,1 + 3198: 0306 slli t1,t1,0x1 + 319a: 0979 addi s2,s2,30 + 319c: 0000 unimp + 319e: 0501 addi a0,a0,0 + 31a0: 09070303 lb t1,144(a4) + 31a4: 0004 0x4 + 31a6: 0601 addi a2,a2,0 + 31a8: 04090003 lb zero,64(s2) + 31ac: 0100 addi s0,sp,128 + 31ae: 00090003 lb zero,0(s2) + 31b2: 0100 addi s0,sp,128 + 31b4: 00090003 lb zero,0(s2) + 31b8: 0100 addi s0,sp,128 + 31ba: 00090103 lb sp,0(s2) + 31be: 0100 addi s0,sp,128 + 31c0: 00090003 lb zero,0(s2) 31c4: 0100 addi s0,sp,128 - 31c6: 0105 addi sp,sp,1 - 31c8: 0306 slli t1,t1,0x1 - 31ca: 0979 addi s2,s2,30 - 31cc: 0000 unimp - 31ce: 0501 addi a0,a0,0 - 31d0: 07030603 lb a2,112(t1) - 31d4: 0409 addi s0,s0,2 + 31c6: 00090003 lb zero,0(s2) + 31ca: 0100 addi s0,sp,128 + 31cc: 00090003 lb zero,0(s2) + 31d0: 0100 addi s0,sp,128 + 31d2: 00090003 lb zero,0(s2) 31d6: 0100 addi s0,sp,128 - 31d8: 0105 addi sp,sp,1 - 31da: 0306 slli t1,t1,0x1 - 31dc: 0979 addi s2,s2,30 - 31de: 0000 unimp - 31e0: 0501 addi a0,a0,0 - 31e2: 07030603 lb a2,112(t1) - 31e6: 0409 addi s0,s0,2 + 31d8: 00090003 lb zero,0(s2) + 31dc: 0100 addi s0,sp,128 + 31de: 00090003 lb zero,0(s2) + 31e2: 0100 addi s0,sp,128 + 31e4: 04090003 lb zero,64(s2) 31e8: 0100 addi s0,sp,128 - 31ea: 0105 addi sp,sp,1 - 31ec: 0306 slli t1,t1,0x1 - 31ee: 0979 addi s2,s2,30 - 31f0: 0000 unimp - 31f2: 0501 addi a0,a0,0 - 31f4: 09070303 lb t1,144(a4) - 31f8: 0004 0x4 - 31fa: 0601 addi a2,a2,0 - 31fc: 04090003 lb zero,64(s2) + 31ea: 04090003 lb zero,64(s2) + 31ee: 0100 addi s0,sp,128 + 31f0: 04090003 lb zero,64(s2) + 31f4: 0100 addi s0,sp,128 + 31f6: 00090103 lb sp,0(s2) + 31fa: 0100 addi s0,sp,128 + 31fc: 00090003 lb zero,0(s2) 3200: 0100 addi s0,sp,128 3202: 00090003 lb zero,0(s2) 3206: 0100 addi s0,sp,128 3208: 00090003 lb zero,0(s2) 320c: 0100 addi s0,sp,128 - 320e: 00090103 lb sp,0(s2) + 320e: 00090003 lb zero,0(s2) 3212: 0100 addi s0,sp,128 - 3214: 00090003 lb zero,0(s2) - 3218: 0100 addi s0,sp,128 - 321a: 00090003 lb zero,0(s2) - 321e: 0100 addi s0,sp,128 - 3220: 00090003 lb zero,0(s2) - 3224: 0100 addi s0,sp,128 - 3226: 00090003 lb zero,0(s2) - 322a: 0100 addi s0,sp,128 - 322c: 00090003 lb zero,0(s2) - 3230: 0100 addi s0,sp,128 - 3232: 00090003 lb zero,0(s2) - 3236: 0100 addi s0,sp,128 - 3238: 04090003 lb zero,64(s2) - 323c: 0100 addi s0,sp,128 - 323e: 04090003 lb zero,64(s2) + 3214: 0200 addi s0,sp,256 + 3216: 1404 addi s1,sp,544 + 3218: 0306 slli t1,t1,0x1 + 321a: 0900 addi s0,sp,144 + 321c: 0004 0x4 + 321e: 0301 addi t1,t1,0 + 3220: 0900 addi s0,sp,144 + 3222: 0014 0x14 + 3224: 0001 nop + 3226: 0402 c.slli64 s0 + 3228: 09000317 auipc t1,0x9000 + 322c: 0008 0x8 + 322e: 0001 nop + 3230: 0402 c.slli64 s0 + 3232: 0318 addi a4,sp,384 + 3234: 0900 addi s0,sp,144 + 3236: 0004 0x4 + 3238: 0001 nop + 323a: 0402 c.slli64 s0 + 323c: 064e slli a2,a2,0x13 + 323e: 14090003 lb zero,320(s2) 3242: 0100 addi s0,sp,128 - 3244: 04090003 lb zero,64(s2) - 3248: 0100 addi s0,sp,128 - 324a: 00090103 lb sp,0(s2) - 324e: 0100 addi s0,sp,128 - 3250: 00090003 lb zero,0(s2) - 3254: 0100 addi s0,sp,128 - 3256: 00090003 lb zero,0(s2) - 325a: 0100 addi s0,sp,128 + 3244: 0200 addi s0,sp,256 + 3246: 4e04 lw s1,24(a2) + 3248: 00090003 lb zero,0(s2) + 324c: 0100 addi s0,sp,128 + 324e: 0200 addi s0,sp,256 + 3250: 4e04 lw s1,24(a2) + 3252: 00090003 lb zero,0(s2) + 3256: 0100 addi s0,sp,128 + 3258: 0200 addi s0,sp,256 + 325a: 4e04 lw s1,24(a2) 325c: 00090003 lb zero,0(s2) 3260: 0100 addi s0,sp,128 - 3262: 00090003 lb zero,0(s2) - 3266: 0100 addi s0,sp,128 - 3268: 0200 addi s0,sp,256 - 326a: 1404 addi s1,sp,544 - 326c: 0306 slli t1,t1,0x1 - 326e: 0900 addi s0,sp,144 - 3270: 0004 0x4 - 3272: 0301 addi t1,t1,0 - 3274: 0900 addi s0,sp,144 - 3276: 0014 0x14 - 3278: 0001 nop - 327a: 0402 c.slli64 s0 - 327c: 09000317 auipc t1,0x9000 - 3280: 0008 0x8 - 3282: 0001 nop - 3284: 0402 c.slli64 s0 - 3286: 0318 addi a4,sp,384 - 3288: 0900 addi s0,sp,144 - 328a: 0004 0x4 - 328c: 0001 nop - 328e: 0402 c.slli64 s0 - 3290: 064e slli a2,a2,0x13 - 3292: 14090003 lb zero,320(s2) - 3296: 0100 addi s0,sp,128 - 3298: 0200 addi s0,sp,256 - 329a: 4e04 lw s1,24(a2) - 329c: 00090003 lb zero,0(s2) - 32a0: 0100 addi s0,sp,128 - 32a2: 0200 addi s0,sp,256 - 32a4: 4e04 lw s1,24(a2) - 32a6: 00090003 lb zero,0(s2) - 32aa: 0100 addi s0,sp,128 - 32ac: 0200 addi s0,sp,256 - 32ae: 4e04 lw s1,24(a2) - 32b0: 00090003 lb zero,0(s2) - 32b4: 0100 addi s0,sp,128 - 32b6: 0200 addi s0,sp,256 - 32b8: 4e04 lw s1,24(a2) - 32ba: 00090003 lb zero,0(s2) - 32be: 0100 addi s0,sp,128 - 32c0: 0200 addi s0,sp,256 - 32c2: 4e04 lw s1,24(a2) - 32c4: 00090003 lb zero,0(s2) - 32c8: 0100 addi s0,sp,128 - 32ca: 0200 addi s0,sp,256 - 32cc: 4e04 lw s1,24(a2) - 32ce: 00090003 lb zero,0(s2) - 32d2: 0100 addi s0,sp,128 - 32d4: 0200 addi s0,sp,256 - 32d6: 4e04 lw s1,24(a2) - 32d8: 00090003 lb zero,0(s2) - 32dc: 0100 addi s0,sp,128 - 32de: 0200 addi s0,sp,256 - 32e0: 4e04 lw s1,24(a2) - 32e2: 00090003 lb zero,0(s2) - 32e6: 0100 addi s0,sp,128 - 32e8: 0200 addi s0,sp,256 - 32ea: 4e04 lw s1,24(a2) - 32ec: 00090003 lb zero,0(s2) - 32f0: 0100 addi s0,sp,128 - 32f2: 0200 addi s0,sp,256 - 32f4: 5004 lw s1,32(s0) - 32f6: 0306 slli t1,t1,0x1 - 32f8: 0900 addi s0,sp,144 - 32fa: 0008 0x8 - 32fc: 0001 nop - 32fe: 0402 c.slli64 s0 - 3300: 0352 slli t1,t1,0x14 - 3302: 0900 addi s0,sp,144 - 3304: 0004 0x4 - 3306: 0001 nop - 3308: 0402 c.slli64 s0 - 330a: 0354 addi a3,sp,388 - 330c: 0900 addi s0,sp,144 - 330e: 0004 0x4 - 3310: 0001 nop - 3312: 0402 c.slli64 s0 - 3314: 0356 slli t1,t1,0x15 - 3316: 0900 addi s0,sp,144 - 3318: 0004 0x4 - 331a: 0001 nop - 331c: 0402 c.slli64 s0 - 331e: 0358 addi a4,sp,388 - 3320: 0900 addi s0,sp,144 - 3322: 0004 0x4 - 3324: 0001 nop - 3326: 0402 c.slli64 s0 - 3328: 0359 addi t1,t1,22 - 332a: 0900 addi s0,sp,144 - 332c: 0004 0x4 - 332e: 0001 nop - 3330: 0402 c.slli64 s0 - 3332: 035c addi a5,sp,388 - 3334: 0900 addi s0,sp,144 - 3336: 0004 0x4 - 3338: 0501 addi a0,a0,0 - 333a: 0301 addi t1,t1,0 - 333c: 0904 addi s1,sp,144 - 333e: 0010 0x10 - 3340: 0501 addi a0,a0,0 - 3342: 097c0303 lb t1,151(s8) # 19097 <_start-0x7ffe6f69> - 3346: 0008 0x8 - 3348: 0901 addi s2,s2,0 - 334a: 0008 0x8 - 334c: 0100 addi s0,sp,128 - 334e: b901 j 2f5e <_start-0x7fffd0a2> - 3350: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 3354: a300 fsd fs0,0(a4) - 3356: 0000 unimp - 3358: 0100 addi s0,sp,128 - 335a: fb01 bnez a4,326a <_start-0x7fffcd96> - 335c: 0d0e slli s10,s10,0x3 - 335e: 0100 addi s0,sp,128 - 3360: 0101 addi sp,sp,0 - 3362: 0001 nop + 3262: 0200 addi s0,sp,256 + 3264: 4e04 lw s1,24(a2) + 3266: 00090003 lb zero,0(s2) + 326a: 0100 addi s0,sp,128 + 326c: 0200 addi s0,sp,256 + 326e: 4e04 lw s1,24(a2) + 3270: 00090003 lb zero,0(s2) + 3274: 0100 addi s0,sp,128 + 3276: 0200 addi s0,sp,256 + 3278: 4e04 lw s1,24(a2) + 327a: 00090003 lb zero,0(s2) + 327e: 0100 addi s0,sp,128 + 3280: 0200 addi s0,sp,256 + 3282: 4e04 lw s1,24(a2) + 3284: 00090003 lb zero,0(s2) + 3288: 0100 addi s0,sp,128 + 328a: 0200 addi s0,sp,256 + 328c: 4e04 lw s1,24(a2) + 328e: 00090003 lb zero,0(s2) + 3292: 0100 addi s0,sp,128 + 3294: 0200 addi s0,sp,256 + 3296: 4e04 lw s1,24(a2) + 3298: 00090003 lb zero,0(s2) + 329c: 0100 addi s0,sp,128 + 329e: 0200 addi s0,sp,256 + 32a0: 5004 lw s1,32(s0) + 32a2: 0306 slli t1,t1,0x1 + 32a4: 0900 addi s0,sp,144 + 32a6: 0008 0x8 + 32a8: 0001 nop + 32aa: 0402 c.slli64 s0 + 32ac: 0352 slli t1,t1,0x14 + 32ae: 0900 addi s0,sp,144 + 32b0: 0004 0x4 + 32b2: 0001 nop + 32b4: 0402 c.slli64 s0 + 32b6: 0354 addi a3,sp,388 + 32b8: 0900 addi s0,sp,144 + 32ba: 0004 0x4 + 32bc: 0001 nop + 32be: 0402 c.slli64 s0 + 32c0: 0356 slli t1,t1,0x15 + 32c2: 0900 addi s0,sp,144 + 32c4: 0004 0x4 + 32c6: 0001 nop + 32c8: 0402 c.slli64 s0 + 32ca: 0358 addi a4,sp,388 + 32cc: 0900 addi s0,sp,144 + 32ce: 0004 0x4 + 32d0: 0001 nop + 32d2: 0402 c.slli64 s0 + 32d4: 0359 addi t1,t1,22 + 32d6: 0900 addi s0,sp,144 + 32d8: 0004 0x4 + 32da: 0001 nop + 32dc: 0402 c.slli64 s0 + 32de: 035c addi a5,sp,388 + 32e0: 0900 addi s0,sp,144 + 32e2: 0004 0x4 + 32e4: 0501 addi a0,a0,0 + 32e6: 0301 addi t1,t1,0 + 32e8: 0904 addi s1,sp,144 + 32ea: 0010 0x10 + 32ec: 0501 addi a0,a0,0 + 32ee: 097c0303 lb t1,151(s8) # 19097 <_start-0x7ffe6f69> + 32f2: 0008 0x8 + 32f4: 0901 addi s2,s2,0 + 32f6: 0008 0x8 + 32f8: 0100 addi s0,sp,128 + 32fa: b901 j 2f0a <_start-0x7fffd0f6> + 32fc: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> + 3300: a300 fsd fs0,0(a4) + 3302: 0000 unimp + 3304: 0100 addi s0,sp,128 + 3306: fb01 bnez a4,3216 <_start-0x7fffcdea> + 3308: 0d0e slli s10,s10,0x3 + 330a: 0100 addi s0,sp,128 + 330c: 0101 addi sp,sp,0 + 330e: 0001 nop + 3310: 0000 unimp + 3312: 0001 nop + 3314: 0100 addi s0,sp,128 + 3316: 2e2e fld ft8,200(sp) + 3318: 2f2e2e2f 0x2f2e2e2f + 331c: 2e2e fld ft8,200(sp) + 331e: 2f2e2e2f 0x2f2e2e2f + 3322: 6972 flw fs2,28(sp) + 3324: 2d766373 csrrsi t1,0x2d7,12 + 3328: 2f636367 0x2f636367 + 332c: 696c flw fa1,84(a0) + 332e: 6762 flw fa4,24(sp) + 3330: 732f6363 bltu t5,s2,3a56 <_start-0x7fffc5aa> + 3334: 2d74666f jal a2,49e0a <_start-0x7ffb61f6> + 3338: 7066 flw ft0,120(sp) + 333a: 2e00 fld fs0,24(a2) + 333c: 2e00 fld fs0,24(a2) + 333e: 2f2e fld ft10,200(sp) + 3340: 2e2e fld ft8,200(sp) + 3342: 2f2e2e2f 0x2f2e2e2f + 3346: 2e2e fld ft8,200(sp) + 3348: 7369722f 0x7369722f + 334c: 672d7663 bgeu s10,s2,39b8 <_start-0x7fffc648> + 3350: 6c2f6363 bltu t5,sp,3a16 <_start-0x7fffc5ea> + 3354: 6269 lui tp,0x1a + 3356: 2f636367 0x2f636367 + 335a: 2e2e fld ft8,200(sp) + 335c: 636e692f 0x636e692f + 3360: 756c flw fa1,108(a0) + 3362: 6564 flw fs1,76(a0) 3364: 0000 unimp - 3366: 0001 nop - 3368: 0100 addi s0,sp,128 - 336a: 2e2e fld ft8,200(sp) - 336c: 2f2e2e2f 0x2f2e2e2f - 3370: 2e2e fld ft8,200(sp) - 3372: 2f2e2e2f 0x2f2e2e2f - 3376: 6972 flw fs2,28(sp) - 3378: 2d766373 csrrsi t1,0x2d7,12 - 337c: 2f636367 0x2f636367 - 3380: 696c flw fa1,84(a0) - 3382: 6762 flw fa4,24(sp) - 3384: 732f6363 bltu t5,s2,3aaa <_start-0x7fffc556> - 3388: 2d74666f jal a2,49e5e <_start-0x7ffb61a2> - 338c: 7066 flw ft0,120(sp) - 338e: 2e00 fld fs0,24(a2) - 3390: 2e00 fld fs0,24(a2) - 3392: 2f2e fld ft10,200(sp) - 3394: 2e2e fld ft8,200(sp) - 3396: 2f2e2e2f 0x2f2e2e2f - 339a: 2e2e fld ft8,200(sp) - 339c: 7369722f 0x7369722f - 33a0: 672d7663 bgeu s10,s2,3a0c <_start-0x7fffc5f4> - 33a4: 6c2f6363 bltu t5,sp,3a6a <_start-0x7fffc596> - 33a8: 6269 lui tp,0x1a - 33aa: 2f636367 0x2f636367 - 33ae: 2e2e fld ft8,200(sp) - 33b0: 636e692f 0x636e692f - 33b4: 756c flw fa1,108(a0) - 33b6: 6564 flw fs1,76(a0) - 33b8: 0000 unimp - 33ba: 66746567 0x66746567 - 33be: 2e32 fld ft8,264(sp) - 33c0: 00010063 beqz sp,33c0 <_start-0x7fffcc40> - 33c4: 7300 flw fs0,32(a4) - 33c6: 7066 flw ft0,120(sp) - 33c8: 6d2d lui s10,0xb - 33ca: 6361 lui t1,0x18 - 33cc: 6968 flw fa0,84(a0) - 33ce: 656e flw fa0,216(sp) - 33d0: 682e flw fa6,200(sp) - 33d2: 0200 addi s0,sp,256 - 33d4: 0000 unimp - 33d6: 74666f73 csrrsi t5,0x746,12 - 33da: 662d lui a2,0xb - 33dc: 2e70 fld fa2,216(a2) - 33de: 0068 addi a0,sp,12 - 33e0: 0001 nop - 33e2: 7100 flw fs0,32(a0) - 33e4: 6175 addi sp,sp,368 - 33e6: 2e64 fld fs1,216(a2) - 33e8: 0068 addi a0,sp,12 - 33ea: 0001 nop - 33ec: 6c00 flw fs0,24(s0) - 33ee: 6c676e6f jal t3,79ab4 <_start-0x7ff8654c> - 33f2: 2e676e6f jal t3,796d8 <_start-0x7ff86928> - 33f6: 0068 addi a0,sp,12 - 33f8: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> - 33fc: 0105 addi sp,sp,1 - 33fe: 0500 addi s0,sp,640 - 3400: b402 fsd ft0,40(sp) - 3402: 0119 addi sp,sp,6 - 3404: 0380 addi s0,sp,448 - 3406: 03050123 sb a6,34(a0) - 340a: 00090103 lb sp,0(s2) - 340e: 0100 addi s0,sp,128 - 3410: 00090003 lb zero,0(s2) - 3414: 0100 addi s0,sp,128 - 3416: 0d05 addi s10,s10,1 - 3418: 00090003 lb zero,0(s2) - 341c: 0100 addi s0,sp,128 - 341e: 0305 addi t1,t1,1 - 3420: 00090103 lb sp,0(s2) - 3424: 0100 addi s0,sp,128 - 3426: 00090003 lb zero,0(s2) - 342a: 0100 addi s0,sp,128 - 342c: 00090003 lb zero,0(s2) + 3366: 66746567 0x66746567 + 336a: 2e32 fld ft8,264(sp) + 336c: 00010063 beqz sp,336c <_start-0x7fffcc94> + 3370: 7300 flw fs0,32(a4) + 3372: 7066 flw ft0,120(sp) + 3374: 6d2d lui s10,0xb + 3376: 6361 lui t1,0x18 + 3378: 6968 flw fa0,84(a0) + 337a: 656e flw fa0,216(sp) + 337c: 682e flw fa6,200(sp) + 337e: 0200 addi s0,sp,256 + 3380: 0000 unimp + 3382: 74666f73 csrrsi t5,0x746,12 + 3386: 662d lui a2,0xb + 3388: 2e70 fld fa2,216(a2) + 338a: 0068 addi a0,sp,12 + 338c: 0001 nop + 338e: 7100 flw fs0,32(a0) + 3390: 6175 addi sp,sp,368 + 3392: 2e64 fld fs1,216(a2) + 3394: 0068 addi a0,sp,12 + 3396: 0001 nop + 3398: 6c00 flw fs0,24(s0) + 339a: 6c676e6f jal t3,79a60 <_start-0x7ff865a0> + 339e: 2e676e6f jal t3,79684 <_start-0x7ff8697c> + 33a2: 0068 addi a0,sp,12 + 33a4: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> + 33a8: 0105 addi sp,sp,1 + 33aa: 0500 addi s0,sp,640 + 33ac: 7802 flw fa6,32(sp) + 33ae: 011a slli sp,sp,0x6 + 33b0: 0380 addi s0,sp,448 + 33b2: 03050123 sb a6,34(a0) + 33b6: 00090103 lb sp,0(s2) + 33ba: 0100 addi s0,sp,128 + 33bc: 00090003 lb zero,0(s2) + 33c0: 0100 addi s0,sp,128 + 33c2: 0d05 addi s10,s10,1 + 33c4: 00090003 lb zero,0(s2) + 33c8: 0100 addi s0,sp,128 + 33ca: 0305 addi t1,t1,1 + 33cc: 00090103 lb sp,0(s2) + 33d0: 0100 addi s0,sp,128 + 33d2: 00090003 lb zero,0(s2) + 33d6: 0100 addi s0,sp,128 + 33d8: 00090003 lb zero,0(s2) + 33dc: 0100 addi s0,sp,128 + 33de: 00090003 lb zero,0(s2) + 33e2: 0100 addi s0,sp,128 + 33e4: 00090103 lb sp,0(s2) + 33e8: 0100 addi s0,sp,128 + 33ea: 00090003 lb zero,0(s2) + 33ee: 0100 addi s0,sp,128 + 33f0: 00090003 lb zero,0(s2) + 33f4: 0100 addi s0,sp,128 + 33f6: 00090003 lb zero,0(s2) + 33fa: 0100 addi s0,sp,128 + 33fc: 00090103 lb sp,0(s2) + 3400: 0100 addi s0,sp,128 + 3402: 00090203 lb tp,0(s2) + 3406: 0100 addi s0,sp,128 + 3408: 00090103 lb sp,0(s2) + 340c: 0100 addi s0,sp,128 + 340e: 00090003 lb zero,0(s2) + 3412: 0100 addi s0,sp,128 + 3414: 00090003 lb zero,0(s2) + 3418: 0100 addi s0,sp,128 + 341a: 00090003 lb zero,0(s2) + 341e: 0100 addi s0,sp,128 + 3420: 0105 addi sp,sp,1 + 3422: 0306 slli t1,t1,0x1 + 3424: 0979 addi s2,s2,30 + 3426: 0000 unimp + 3428: 0501 addi a0,a0,0 + 342a: 07030603 lb a2,112(t1) # 18070 <_start-0x7ffe7f90> + 342e: 0409 addi s0,s0,2 3430: 0100 addi s0,sp,128 - 3432: 00090003 lb zero,0(s2) - 3436: 0100 addi s0,sp,128 - 3438: 00090103 lb sp,0(s2) - 343c: 0100 addi s0,sp,128 - 343e: 00090003 lb zero,0(s2) + 3432: 0105 addi sp,sp,1 + 3434: 0306 slli t1,t1,0x1 + 3436: 0979 addi s2,s2,30 + 3438: 0000 unimp + 343a: 0501 addi a0,a0,0 + 343c: 07030603 lb a2,112(t1) + 3440: 0409 addi s0,s0,2 3442: 0100 addi s0,sp,128 - 3444: 00090003 lb zero,0(s2) - 3448: 0100 addi s0,sp,128 - 344a: 00090003 lb zero,0(s2) - 344e: 0100 addi s0,sp,128 - 3450: 00090103 lb sp,0(s2) + 3444: 0105 addi sp,sp,1 + 3446: 0306 slli t1,t1,0x1 + 3448: 0979 addi s2,s2,30 + 344a: 0000 unimp + 344c: 0501 addi a0,a0,0 + 344e: 07030603 lb a2,112(t1) + 3452: 0409 addi s0,s0,2 3454: 0100 addi s0,sp,128 - 3456: 00090203 lb tp,0(s2) - 345a: 0100 addi s0,sp,128 - 345c: 00090103 lb sp,0(s2) - 3460: 0100 addi s0,sp,128 - 3462: 00090003 lb zero,0(s2) - 3466: 0100 addi s0,sp,128 - 3468: 00090003 lb zero,0(s2) - 346c: 0100 addi s0,sp,128 - 346e: 00090003 lb zero,0(s2) - 3472: 0100 addi s0,sp,128 - 3474: 0105 addi sp,sp,1 - 3476: 0306 slli t1,t1,0x1 - 3478: 0979 addi s2,s2,30 - 347a: 0000 unimp + 3456: 0105 addi sp,sp,1 + 3458: 0306 slli t1,t1,0x1 + 345a: 0979 addi s2,s2,30 + 345c: 0000 unimp + 345e: 0501 addi a0,a0,0 + 3460: 09070303 lb t1,144(a4) + 3464: 0008 0x8 + 3466: 0301 addi t1,t1,0 + 3468: 0901 addi s2,s2,0 + 346a: 000c 0xc + 346c: 0501 addi a0,a0,0 + 346e: 0301 addi t1,t1,0 + 3470: 0978 addi a4,sp,156 + 3472: 0008 0x8 + 3474: 0501 addi a0,a0,0 + 3476: 09070303 lb t1,144(a4) + 347a: 000c 0xc 347c: 0501 addi a0,a0,0 - 347e: 07030603 lb a2,112(t1) # 18070 <_start-0x7ffe7f90> - 3482: 0409 addi s0,s0,2 - 3484: 0100 addi s0,sp,128 - 3486: 0105 addi sp,sp,1 - 3488: 0306 slli t1,t1,0x1 - 348a: 0979 addi s2,s2,30 - 348c: 0000 unimp - 348e: 0501 addi a0,a0,0 - 3490: 07030603 lb a2,112(t1) - 3494: 0409 addi s0,s0,2 - 3496: 0100 addi s0,sp,128 - 3498: 0105 addi sp,sp,1 - 349a: 0306 slli t1,t1,0x1 - 349c: 0979 addi s2,s2,30 - 349e: 0000 unimp - 34a0: 0501 addi a0,a0,0 - 34a2: 07030603 lb a2,112(t1) - 34a6: 0409 addi s0,s0,2 - 34a8: 0100 addi s0,sp,128 - 34aa: 0105 addi sp,sp,1 - 34ac: 0306 slli t1,t1,0x1 - 34ae: 0979 addi s2,s2,30 - 34b0: 0000 unimp - 34b2: 0501 addi a0,a0,0 - 34b4: 09070303 lb t1,144(a4) - 34b8: 0008 0x8 - 34ba: 0301 addi t1,t1,0 - 34bc: 0901 addi s2,s2,0 - 34be: 000c 0xc - 34c0: 0501 addi a0,a0,0 - 34c2: 0301 addi t1,t1,0 - 34c4: 0978 addi a4,sp,156 - 34c6: 0008 0x8 - 34c8: 0501 addi a0,a0,0 - 34ca: 09070303 lb t1,144(a4) - 34ce: 000c 0xc - 34d0: 0501 addi a0,a0,0 - 34d2: 0301 addi t1,t1,0 - 34d4: 0979 addi s2,s2,30 - 34d6: 0008 0x8 - 34d8: 0501 addi a0,a0,0 - 34da: 09070303 lb t1,144(a4) - 34de: 0004 0x4 - 34e0: 0601 addi a2,a2,0 - 34e2: 04090003 lb zero,64(s2) + 347e: 0301 addi t1,t1,0 + 3480: 0979 addi s2,s2,30 + 3482: 0008 0x8 + 3484: 0501 addi a0,a0,0 + 3486: 09070303 lb t1,144(a4) + 348a: 0004 0x4 + 348c: 0601 addi a2,a2,0 + 348e: 04090003 lb zero,64(s2) + 3492: 0100 addi s0,sp,128 + 3494: 00090003 lb zero,0(s2) + 3498: 0100 addi s0,sp,128 + 349a: 04090003 lb zero,64(s2) + 349e: 0100 addi s0,sp,128 + 34a0: 00090103 lb sp,0(s2) + 34a4: 0100 addi s0,sp,128 + 34a6: 00090003 lb zero,0(s2) + 34aa: 0100 addi s0,sp,128 + 34ac: 00090003 lb zero,0(s2) + 34b0: 0100 addi s0,sp,128 + 34b2: 00090003 lb zero,0(s2) + 34b6: 0100 addi s0,sp,128 + 34b8: 00090003 lb zero,0(s2) + 34bc: 0100 addi s0,sp,128 + 34be: 00090003 lb zero,0(s2) + 34c2: 0100 addi s0,sp,128 + 34c4: 00090003 lb zero,0(s2) + 34c8: 0100 addi s0,sp,128 + 34ca: 04090003 lb zero,64(s2) + 34ce: 0100 addi s0,sp,128 + 34d0: 04090003 lb zero,64(s2) + 34d4: 0100 addi s0,sp,128 + 34d6: 04090003 lb zero,64(s2) + 34da: 0100 addi s0,sp,128 + 34dc: 00090103 lb sp,0(s2) + 34e0: 0100 addi s0,sp,128 + 34e2: 00090003 lb zero,0(s2) 34e6: 0100 addi s0,sp,128 34e8: 00090003 lb zero,0(s2) 34ec: 0100 addi s0,sp,128 - 34ee: 04090003 lb zero,64(s2) + 34ee: 00090003 lb zero,0(s2) 34f2: 0100 addi s0,sp,128 - 34f4: 00090103 lb sp,0(s2) + 34f4: 00090003 lb zero,0(s2) 34f8: 0100 addi s0,sp,128 - 34fa: 00090003 lb zero,0(s2) - 34fe: 0100 addi s0,sp,128 - 3500: 00090003 lb zero,0(s2) - 3504: 0100 addi s0,sp,128 - 3506: 00090003 lb zero,0(s2) - 350a: 0100 addi s0,sp,128 - 350c: 00090003 lb zero,0(s2) - 3510: 0100 addi s0,sp,128 - 3512: 00090003 lb zero,0(s2) - 3516: 0100 addi s0,sp,128 - 3518: 00090003 lb zero,0(s2) - 351c: 0100 addi s0,sp,128 - 351e: 04090003 lb zero,64(s2) - 3522: 0100 addi s0,sp,128 - 3524: 04090003 lb zero,64(s2) + 34fa: 0200 addi s0,sp,256 + 34fc: 1404 addi s1,sp,544 + 34fe: 0306 slli t1,t1,0x1 + 3500: 0900 addi s0,sp,144 + 3502: 0004 0x4 + 3504: 0301 addi t1,t1,0 + 3506: 0900 addi s0,sp,144 + 3508: 0010 0x10 + 350a: 0001 nop + 350c: 0402 c.slli64 s0 + 350e: 09000317 auipc t1,0x9000 + 3512: 0008 0x8 + 3514: 0001 nop + 3516: 0402 c.slli64 s0 + 3518: 0318 addi a4,sp,384 + 351a: 0900 addi s0,sp,144 + 351c: 0004 0x4 + 351e: 0001 nop + 3520: 0402 c.slli64 s0 + 3522: 063e slli a2,a2,0xf + 3524: 10090003 lb zero,256(s2) 3528: 0100 addi s0,sp,128 - 352a: 04090003 lb zero,64(s2) - 352e: 0100 addi s0,sp,128 - 3530: 00090103 lb sp,0(s2) - 3534: 0100 addi s0,sp,128 - 3536: 00090003 lb zero,0(s2) - 353a: 0100 addi s0,sp,128 - 353c: 00090003 lb zero,0(s2) - 3540: 0100 addi s0,sp,128 + 352a: 0200 addi s0,sp,256 + 352c: 3e04 fld fs1,56(a2) + 352e: 00090003 lb zero,0(s2) + 3532: 0100 addi s0,sp,128 + 3534: 0200 addi s0,sp,256 + 3536: 3e04 fld fs1,56(a2) + 3538: 00090003 lb zero,0(s2) + 353c: 0100 addi s0,sp,128 + 353e: 0200 addi s0,sp,256 + 3540: 3e04 fld fs1,56(a2) 3542: 00090003 lb zero,0(s2) 3546: 0100 addi s0,sp,128 - 3548: 00090003 lb zero,0(s2) - 354c: 0100 addi s0,sp,128 - 354e: 0200 addi s0,sp,256 - 3550: 1404 addi s1,sp,544 - 3552: 0306 slli t1,t1,0x1 - 3554: 0900 addi s0,sp,144 - 3556: 0004 0x4 - 3558: 0301 addi t1,t1,0 - 355a: 0900 addi s0,sp,144 - 355c: 0010 0x10 - 355e: 0001 nop - 3560: 0402 c.slli64 s0 - 3562: 09000317 auipc t1,0x9000 - 3566: 0008 0x8 - 3568: 0001 nop - 356a: 0402 c.slli64 s0 - 356c: 0318 addi a4,sp,384 - 356e: 0900 addi s0,sp,144 - 3570: 0004 0x4 - 3572: 0001 nop - 3574: 0402 c.slli64 s0 - 3576: 063e slli a2,a2,0xf - 3578: 10090003 lb zero,256(s2) - 357c: 0100 addi s0,sp,128 - 357e: 0200 addi s0,sp,256 - 3580: 3e04 fld fs1,56(a2) - 3582: 00090003 lb zero,0(s2) - 3586: 0100 addi s0,sp,128 - 3588: 0200 addi s0,sp,256 - 358a: 3e04 fld fs1,56(a2) - 358c: 00090003 lb zero,0(s2) - 3590: 0100 addi s0,sp,128 - 3592: 0200 addi s0,sp,256 - 3594: 3e04 fld fs1,56(a2) - 3596: 00090003 lb zero,0(s2) - 359a: 0100 addi s0,sp,128 - 359c: 0200 addi s0,sp,256 - 359e: 3e04 fld fs1,56(a2) - 35a0: 00090003 lb zero,0(s2) - 35a4: 0100 addi s0,sp,128 - 35a6: 0200 addi s0,sp,256 - 35a8: 3e04 fld fs1,56(a2) - 35aa: 00090003 lb zero,0(s2) - 35ae: 0100 addi s0,sp,128 - 35b0: 0200 addi s0,sp,256 - 35b2: 3e04 fld fs1,56(a2) - 35b4: 00090003 lb zero,0(s2) - 35b8: 0100 addi s0,sp,128 - 35ba: 0200 addi s0,sp,256 - 35bc: 3e04 fld fs1,56(a2) - 35be: 00090003 lb zero,0(s2) - 35c2: 0100 addi s0,sp,128 - 35c4: 0200 addi s0,sp,256 - 35c6: 3e04 fld fs1,56(a2) - 35c8: 00090003 lb zero,0(s2) - 35cc: 0100 addi s0,sp,128 - 35ce: 0200 addi s0,sp,256 - 35d0: 3e04 fld fs1,56(a2) - 35d2: 00090003 lb zero,0(s2) - 35d6: 0100 addi s0,sp,128 - 35d8: 0200 addi s0,sp,256 - 35da: 3e04 fld fs1,56(a2) - 35dc: 00090003 lb zero,0(s2) - 35e0: 0100 addi s0,sp,128 - 35e2: 0200 addi s0,sp,256 - 35e4: 3e04 fld fs1,56(a2) - 35e6: 00090003 lb zero,0(s2) - 35ea: 0100 addi s0,sp,128 - 35ec: 0200 addi s0,sp,256 - 35ee: 3f04 fld fs1,56(a4) - 35f0: 0306 slli t1,t1,0x1 - 35f2: 0900 addi s0,sp,144 - 35f4: 0004 0x4 - 35f6: 0001 nop - 35f8: 0402 c.slli64 s0 - 35fa: 0003063f 01001009 0x10010090003063f - 3602: 0200 addi s0,sp,256 - 3604: 4504 lw s1,8(a0) - 3606: 0306 slli t1,t1,0x1 - 3608: 0900 addi s0,sp,144 - 360a: 0004 0x4 - 360c: 0601 addi a2,a2,0 - 360e: 10090003 lb zero,256(s2) - 3612: 0100 addi s0,sp,128 - 3614: 04090003 lb zero,64(s2) - 3618: 0100 addi s0,sp,128 - 361a: 00090003 lb zero,0(s2) - 361e: 0100 addi s0,sp,128 - 3620: 00090003 lb zero,0(s2) - 3624: 0100 addi s0,sp,128 - 3626: 0200 addi s0,sp,256 - 3628: 5f04 lw s1,56(a4) - 362a: 04090003 lb zero,64(s2) - 362e: 0100 addi s0,sp,128 - 3630: 0200 addi s0,sp,256 - 3632: 7f04 flw fs1,56(a4) - 3634: 04090003 lb zero,64(s2) - 3638: 0100 addi s0,sp,128 - 363a: 0306 slli t1,t1,0x1 - 363c: 0900 addi s0,sp,144 - 363e: 0004 0x4 - 3640: 0001 nop - 3642: 0402 c.slli64 s0 - 3644: 0650 addi a2,sp,772 - 3646: 08090003 lb zero,128(s2) - 364a: 0100 addi s0,sp,128 - 364c: 0200 addi s0,sp,256 - 364e: 5004 lw s1,32(s0) - 3650: 00090003 lb zero,0(s2) - 3654: 0100 addi s0,sp,128 - 3656: 0306 slli t1,t1,0x1 - 3658: 0900 addi s0,sp,144 - 365a: 0008 0x8 - 365c: 0501 addi a0,a0,0 - 365e: 0301 addi t1,t1,0 - 3660: 0904 addi s1,sp,144 - 3662: 0004 0x4 - 3664: 0501 addi a0,a0,0 - 3666: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> - 366a: 0666 slli a2,a2,0x19 - 366c: 08097c03 0x8097c03 - 3670: 0100 addi s0,sp,128 - 3672: 0300 addi s0,sp,384 - 3674: 9204 0x9204 - 3676: 0301 addi t1,t1,0 - 3678: 0900 addi s0,sp,144 - 367a: 0004 0x4 - 367c: 0001 nop - 367e: 0402 c.slli64 s0 - 3680: 036d addi t1,t1,27 - 3682: 0900 addi s0,sp,144 - 3684: 0008 0x8 - 3686: 0001 nop - 3688: 0402 c.slli64 s0 - 368a: 0674 addi a3,sp,780 - 368c: 04090003 lb zero,64(s2) - 3690: 0100 addi s0,sp,128 - 3692: 0200 addi s0,sp,256 - 3694: 7504 flw fs1,40(a0) - 3696: 04090003 lb zero,64(s2) - 369a: 0100 addi s0,sp,128 - 369c: 0200 addi s0,sp,256 - 369e: 7804 flw fs1,48(s0) - 36a0: 04090003 lb zero,64(s2) + 3548: 0200 addi s0,sp,256 + 354a: 3e04 fld fs1,56(a2) + 354c: 00090003 lb zero,0(s2) + 3550: 0100 addi s0,sp,128 + 3552: 0200 addi s0,sp,256 + 3554: 3e04 fld fs1,56(a2) + 3556: 00090003 lb zero,0(s2) + 355a: 0100 addi s0,sp,128 + 355c: 0200 addi s0,sp,256 + 355e: 3e04 fld fs1,56(a2) + 3560: 00090003 lb zero,0(s2) + 3564: 0100 addi s0,sp,128 + 3566: 0200 addi s0,sp,256 + 3568: 3e04 fld fs1,56(a2) + 356a: 00090003 lb zero,0(s2) + 356e: 0100 addi s0,sp,128 + 3570: 0200 addi s0,sp,256 + 3572: 3e04 fld fs1,56(a2) + 3574: 00090003 lb zero,0(s2) + 3578: 0100 addi s0,sp,128 + 357a: 0200 addi s0,sp,256 + 357c: 3e04 fld fs1,56(a2) + 357e: 00090003 lb zero,0(s2) + 3582: 0100 addi s0,sp,128 + 3584: 0200 addi s0,sp,256 + 3586: 3e04 fld fs1,56(a2) + 3588: 00090003 lb zero,0(s2) + 358c: 0100 addi s0,sp,128 + 358e: 0200 addi s0,sp,256 + 3590: 3e04 fld fs1,56(a2) + 3592: 00090003 lb zero,0(s2) + 3596: 0100 addi s0,sp,128 + 3598: 0200 addi s0,sp,256 + 359a: 3f04 fld fs1,56(a4) + 359c: 0306 slli t1,t1,0x1 + 359e: 0900 addi s0,sp,144 + 35a0: 0004 0x4 + 35a2: 0001 nop + 35a4: 0402 c.slli64 s0 + 35a6: 0003063f 01001009 0x10010090003063f + 35ae: 0200 addi s0,sp,256 + 35b0: 4504 lw s1,8(a0) + 35b2: 0306 slli t1,t1,0x1 + 35b4: 0900 addi s0,sp,144 + 35b6: 0004 0x4 + 35b8: 0601 addi a2,a2,0 + 35ba: 10090003 lb zero,256(s2) + 35be: 0100 addi s0,sp,128 + 35c0: 04090003 lb zero,64(s2) + 35c4: 0100 addi s0,sp,128 + 35c6: 00090003 lb zero,0(s2) + 35ca: 0100 addi s0,sp,128 + 35cc: 00090003 lb zero,0(s2) + 35d0: 0100 addi s0,sp,128 + 35d2: 0200 addi s0,sp,256 + 35d4: 5f04 lw s1,56(a4) + 35d6: 04090003 lb zero,64(s2) + 35da: 0100 addi s0,sp,128 + 35dc: 0200 addi s0,sp,256 + 35de: 7f04 flw fs1,56(a4) + 35e0: 04090003 lb zero,64(s2) + 35e4: 0100 addi s0,sp,128 + 35e6: 0306 slli t1,t1,0x1 + 35e8: 0900 addi s0,sp,144 + 35ea: 0004 0x4 + 35ec: 0001 nop + 35ee: 0402 c.slli64 s0 + 35f0: 0650 addi a2,sp,772 + 35f2: 08090003 lb zero,128(s2) + 35f6: 0100 addi s0,sp,128 + 35f8: 0200 addi s0,sp,256 + 35fa: 5004 lw s1,32(s0) + 35fc: 00090003 lb zero,0(s2) + 3600: 0100 addi s0,sp,128 + 3602: 0306 slli t1,t1,0x1 + 3604: 0900 addi s0,sp,144 + 3606: 0008 0x8 + 3608: 0501 addi a0,a0,0 + 360a: 0301 addi t1,t1,0 + 360c: 0904 addi s1,sp,144 + 360e: 0004 0x4 + 3610: 0501 addi a0,a0,0 + 3612: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> + 3616: 0666 slli a2,a2,0x19 + 3618: 08097c03 0x8097c03 + 361c: 0100 addi s0,sp,128 + 361e: 0300 addi s0,sp,384 + 3620: 9204 0x9204 + 3622: 0301 addi t1,t1,0 + 3624: 0900 addi s0,sp,144 + 3626: 0004 0x4 + 3628: 0001 nop + 362a: 0402 c.slli64 s0 + 362c: 036d addi t1,t1,27 + 362e: 0900 addi s0,sp,144 + 3630: 0008 0x8 + 3632: 0001 nop + 3634: 0402 c.slli64 s0 + 3636: 0674 addi a3,sp,780 + 3638: 04090003 lb zero,64(s2) + 363c: 0100 addi s0,sp,128 + 363e: 0200 addi s0,sp,256 + 3640: 7504 flw fs1,40(a0) + 3642: 04090003 lb zero,64(s2) + 3646: 0100 addi s0,sp,128 + 3648: 0200 addi s0,sp,256 + 364a: 7804 flw fs1,48(s0) + 364c: 04090003 lb zero,64(s2) + 3650: 0100 addi s0,sp,128 + 3652: 0200 addi s0,sp,256 + 3654: 7904 flw fs1,48(a0) + 3656: 04090003 lb zero,64(s2) + 365a: 0100 addi s0,sp,128 + 365c: 0200 addi s0,sp,256 + 365e: 7c04 flw fs1,56(s0) + 3660: 04090003 lb zero,64(s2) + 3664: 0100 addi s0,sp,128 + 3666: 0200 addi s0,sp,256 + 3668: 7d04 flw fs1,56(a0) + 366a: 04090003 lb zero,64(s2) + 366e: 0100 addi s0,sp,128 + 3670: 0300 addi s0,sp,384 + 3672: 8c04 0x8c04 + 3674: 0601 addi a2,a2,0 + 3676: 04090003 lb zero,64(s2) + 367a: 0100 addi s0,sp,128 + 367c: 0300 addi s0,sp,384 + 367e: 8f04 0x8f04 + 3680: 0601 addi a2,a2,0 + 3682: 04090003 lb zero,64(s2) + 3686: 0100 addi s0,sp,128 + 3688: 0300 addi s0,sp,384 + 368a: 9004 0x9004 + 368c: 0301 addi t1,t1,0 + 368e: 0900 addi s0,sp,144 + 3690: 0004 0x4 + 3692: 0301 addi t1,t1,0 + 3694: 0900 addi s0,sp,144 + 3696: 0004 0x4 + 3698: 0601 addi a2,a2,0 + 369a: 10090003 lb zero,256(s2) + 369e: 0100 addi s0,sp,128 + 36a0: 08090003 lb zero,128(s2) 36a4: 0100 addi s0,sp,128 - 36a6: 0200 addi s0,sp,256 - 36a8: 7904 flw fs1,48(a0) - 36aa: 04090003 lb zero,64(s2) - 36ae: 0100 addi s0,sp,128 - 36b0: 0200 addi s0,sp,256 - 36b2: 7c04 flw fs1,56(s0) - 36b4: 04090003 lb zero,64(s2) - 36b8: 0100 addi s0,sp,128 - 36ba: 0200 addi s0,sp,256 - 36bc: 7d04 flw fs1,56(a0) - 36be: 04090003 lb zero,64(s2) - 36c2: 0100 addi s0,sp,128 - 36c4: 0300 addi s0,sp,384 - 36c6: 8c04 0x8c04 - 36c8: 0601 addi a2,a2,0 - 36ca: 04090003 lb zero,64(s2) + 36a6: 08090003 lb zero,128(s2) + 36aa: 0100 addi s0,sp,128 + 36ac: 0c090003 lb zero,192(s2) + 36b0: 0100 addi s0,sp,128 + 36b2: 0c09 addi s8,s8,2 + 36b4: 0000 unimp + 36b6: 0101 addi sp,sp,0 + 36b8: 03b9 addi t2,t2,14 + 36ba: 0000 unimp + 36bc: 00a30003 lb zero,10(t1) # 9003518 <_start-0x76ffcae8> + 36c0: 0000 unimp + 36c2: 0101 addi sp,sp,0 + 36c4: 000d0efb 0xd0efb + 36c8: 0101 addi sp,sp,0 + 36ca: 0101 addi sp,sp,0 + 36cc: 0000 unimp 36ce: 0100 addi s0,sp,128 - 36d0: 0300 addi s0,sp,384 - 36d2: 8f04 0x8f04 - 36d4: 0601 addi a2,a2,0 - 36d6: 04090003 lb zero,64(s2) - 36da: 0100 addi s0,sp,128 - 36dc: 0300 addi s0,sp,384 - 36de: 9004 0x9004 - 36e0: 0301 addi t1,t1,0 - 36e2: 0900 addi s0,sp,144 - 36e4: 0004 0x4 - 36e6: 0301 addi t1,t1,0 - 36e8: 0900 addi s0,sp,144 - 36ea: 0004 0x4 - 36ec: 0601 addi a2,a2,0 - 36ee: 10090003 lb zero,256(s2) - 36f2: 0100 addi s0,sp,128 - 36f4: 08090003 lb zero,128(s2) - 36f8: 0100 addi s0,sp,128 - 36fa: 08090003 lb zero,128(s2) - 36fe: 0100 addi s0,sp,128 - 3700: 0c090003 lb zero,192(s2) - 3704: 0100 addi s0,sp,128 - 3706: 0c09 addi s8,s8,2 - 3708: 0000 unimp - 370a: 0101 addi sp,sp,0 - 370c: 03b9 addi t2,t2,14 - 370e: 0000 unimp - 3710: 00a30003 lb zero,10(t1) # 900356c <_start-0x76ffca94> - 3714: 0000 unimp - 3716: 0101 addi sp,sp,0 - 3718: 000d0efb 0xd0efb - 371c: 0101 addi sp,sp,0 - 371e: 0101 addi sp,sp,0 - 3720: 0000 unimp - 3722: 0100 addi s0,sp,128 - 3724: 0000 unimp - 3726: 2e01 jal 3a36 <_start-0x7fffc5ca> - 3728: 2f2e fld ft10,200(sp) - 372a: 2e2e fld ft8,200(sp) - 372c: 2f2e2e2f 0x2f2e2e2f - 3730: 2e2e fld ft8,200(sp) - 3732: 7369722f 0x7369722f - 3736: 672d7663 bgeu s10,s2,3da2 <_start-0x7fffc25e> - 373a: 6c2f6363 bltu t5,sp,3e00 <_start-0x7fffc200> - 373e: 6269 lui tp,0x1a - 3740: 2f636367 0x2f636367 - 3744: 74666f73 csrrsi t5,0x746,12 - 3748: 662d lui a2,0xb - 374a: 0070 addi a2,sp,12 - 374c: 002e c.slli zero,0xb - 374e: 2e2e fld ft8,200(sp) - 3750: 2f2e2e2f 0x2f2e2e2f - 3754: 2e2e fld ft8,200(sp) - 3756: 2f2e2e2f 0x2f2e2e2f - 375a: 6972 flw fs2,28(sp) - 375c: 2d766373 csrrsi t1,0x2d7,12 - 3760: 2f636367 0x2f636367 - 3764: 696c flw fa1,84(a0) - 3766: 6762 flw fa4,24(sp) - 3768: 2e2f6363 bltu t5,sp,3a4e <_start-0x7fffc5b2> - 376c: 2f2e fld ft10,200(sp) - 376e: 6e69 lui t3,0x1a - 3770: 64756c63 bltu a0,t2,3dc8 <_start-0x7fffc238> - 3774: 0065 c.nop 25 - 3776: 6c00 flw fs0,24(s0) - 3778: 7465 lui s0,0xffff9 - 377a: 3266 fld ft4,120(sp) - 377c: 632e flw ft6,200(sp) - 377e: 0100 addi s0,sp,128 - 3780: 0000 unimp - 3782: 2d706673 csrrsi a2,0x2d7,0 - 3786: 616d addi sp,sp,240 - 3788: 6e696863 bltu s2,t1,3e78 <_start-0x7fffc188> - 378c: 2e65 jal 3b44 <_start-0x7fffc4bc> - 378e: 0068 addi a0,sp,12 - 3790: 0002 c.slli64 zero - 3792: 7300 flw fs0,32(a4) - 3794: 2d74666f jal a2,4a26a <_start-0x7ffb5d96> - 3798: 7066 flw ft0,120(sp) - 379a: 682e flw fa6,200(sp) - 379c: 0100 addi s0,sp,128 + 36d0: 0000 unimp + 36d2: 2e01 jal 39e2 <_start-0x7fffc61e> + 36d4: 2f2e fld ft10,200(sp) + 36d6: 2e2e fld ft8,200(sp) + 36d8: 2f2e2e2f 0x2f2e2e2f + 36dc: 2e2e fld ft8,200(sp) + 36de: 7369722f 0x7369722f + 36e2: 672d7663 bgeu s10,s2,3d4e <_start-0x7fffc2b2> + 36e6: 6c2f6363 bltu t5,sp,3dac <_start-0x7fffc254> + 36ea: 6269 lui tp,0x1a + 36ec: 2f636367 0x2f636367 + 36f0: 74666f73 csrrsi t5,0x746,12 + 36f4: 662d lui a2,0xb + 36f6: 0070 addi a2,sp,12 + 36f8: 002e c.slli zero,0xb + 36fa: 2e2e fld ft8,200(sp) + 36fc: 2f2e2e2f 0x2f2e2e2f + 3700: 2e2e fld ft8,200(sp) + 3702: 2f2e2e2f 0x2f2e2e2f + 3706: 6972 flw fs2,28(sp) + 3708: 2d766373 csrrsi t1,0x2d7,12 + 370c: 2f636367 0x2f636367 + 3710: 696c flw fa1,84(a0) + 3712: 6762 flw fa4,24(sp) + 3714: 2e2f6363 bltu t5,sp,39fa <_start-0x7fffc606> + 3718: 2f2e fld ft10,200(sp) + 371a: 6e69 lui t3,0x1a + 371c: 64756c63 bltu a0,t2,3d74 <_start-0x7fffc28c> + 3720: 0065 c.nop 25 + 3722: 6c00 flw fs0,24(s0) + 3724: 7465 lui s0,0xffff9 + 3726: 3266 fld ft4,120(sp) + 3728: 632e flw ft6,200(sp) + 372a: 0100 addi s0,sp,128 + 372c: 0000 unimp + 372e: 2d706673 csrrsi a2,0x2d7,0 + 3732: 616d addi sp,sp,240 + 3734: 6e696863 bltu s2,t1,3e24 <_start-0x7fffc1dc> + 3738: 2e65 jal 3af0 <_start-0x7fffc510> + 373a: 0068 addi a0,sp,12 + 373c: 0002 c.slli64 zero + 373e: 7300 flw fs0,32(a4) + 3740: 2d74666f jal a2,4a216 <_start-0x7ffb5dea> + 3744: 7066 flw ft0,120(sp) + 3746: 682e flw fa6,200(sp) + 3748: 0100 addi s0,sp,128 + 374a: 0000 unimp + 374c: 7571 lui a0,0xffffc + 374e: 6461 lui s0,0x18 + 3750: 682e flw fa6,200(sp) + 3752: 0100 addi s0,sp,128 + 3754: 0000 unimp + 3756: 6f6c flw fa1,92(a4) + 3758: 676e flw fa4,216(sp) + 375a: 6f6c flw fa1,92(a4) + 375c: 676e flw fa4,216(sp) + 375e: 682e flw fa6,200(sp) + 3760: 0300 addi s0,sp,384 + 3762: 0000 unimp + 3764: 0500 addi s0,sp,640 + 3766: 0001 nop + 3768: 0205 addi tp,tp,1 + 376a: 1bbc addi a5,sp,504 + 376c: 8001 c.srli64 s0 + 376e: 05012303 lw t1,80(sp) + 3772: 09010303 lb t1,144(sp) + 3776: 0000 unimp + 3778: 0301 addi t1,t1,0 + 377a: 0900 addi s0,sp,144 + 377c: 0000 unimp + 377e: 0501 addi a0,a0,0 + 3780: 030d addi t1,t1,3 + 3782: 0900 addi s0,sp,144 + 3784: 0000 unimp + 3786: 0501 addi a0,a0,0 + 3788: 09010303 lb t1,144(sp) + 378c: 0000 unimp + 378e: 0301 addi t1,t1,0 + 3790: 0900 addi s0,sp,144 + 3792: 0000 unimp + 3794: 0301 addi t1,t1,0 + 3796: 0900 addi s0,sp,144 + 3798: 0000 unimp + 379a: 0301 addi t1,t1,0 + 379c: 0900 addi s0,sp,144 379e: 0000 unimp - 37a0: 7571 lui a0,0xffffc - 37a2: 6461 lui s0,0x18 - 37a4: 682e flw fa6,200(sp) - 37a6: 0100 addi s0,sp,128 - 37a8: 0000 unimp - 37aa: 6f6c flw fa1,92(a4) - 37ac: 676e flw fa4,216(sp) - 37ae: 6f6c flw fa1,92(a4) - 37b0: 676e flw fa4,216(sp) - 37b2: 682e flw fa6,200(sp) - 37b4: 0300 addi s0,sp,384 + 37a0: 0301 addi t1,t1,0 + 37a2: 0901 addi s2,s2,0 + 37a4: 0000 unimp + 37a6: 0301 addi t1,t1,0 + 37a8: 0900 addi s0,sp,144 + 37aa: 0000 unimp + 37ac: 0301 addi t1,t1,0 + 37ae: 0900 addi s0,sp,144 + 37b0: 0000 unimp + 37b2: 0301 addi t1,t1,0 + 37b4: 0900 addi s0,sp,144 37b6: 0000 unimp - 37b8: 0500 addi s0,sp,640 - 37ba: 0001 nop - 37bc: 0205 addi tp,tp,1 - 37be: 1af8 addi a4,sp,380 - 37c0: 8001 c.srli64 s0 - 37c2: 05012303 lw t1,80(sp) - 37c6: 09010303 lb t1,144(sp) - 37ca: 0000 unimp - 37cc: 0301 addi t1,t1,0 - 37ce: 0900 addi s0,sp,144 - 37d0: 0000 unimp - 37d2: 0501 addi a0,a0,0 - 37d4: 030d addi t1,t1,3 - 37d6: 0900 addi s0,sp,144 - 37d8: 0000 unimp - 37da: 0501 addi a0,a0,0 - 37dc: 09010303 lb t1,144(sp) - 37e0: 0000 unimp - 37e2: 0301 addi t1,t1,0 - 37e4: 0900 addi s0,sp,144 - 37e6: 0000 unimp - 37e8: 0301 addi t1,t1,0 - 37ea: 0900 addi s0,sp,144 - 37ec: 0000 unimp - 37ee: 0301 addi t1,t1,0 - 37f0: 0900 addi s0,sp,144 - 37f2: 0000 unimp - 37f4: 0301 addi t1,t1,0 - 37f6: 0901 addi s2,s2,0 - 37f8: 0000 unimp - 37fa: 0301 addi t1,t1,0 - 37fc: 0900 addi s0,sp,144 - 37fe: 0000 unimp - 3800: 0301 addi t1,t1,0 - 3802: 0900 addi s0,sp,144 - 3804: 0000 unimp - 3806: 0301 addi t1,t1,0 - 3808: 0900 addi s0,sp,144 - 380a: 0000 unimp - 380c: 0301 addi t1,t1,0 - 380e: 0901 addi s2,s2,0 - 3810: 0000 unimp - 3812: 0301 addi t1,t1,0 - 3814: 0902 c.slli64 s2 - 3816: 0000 unimp - 3818: 0301 addi t1,t1,0 - 381a: 0901 addi s2,s2,0 - 381c: 0000 unimp - 381e: 0301 addi t1,t1,0 - 3820: 0900 addi s0,sp,144 - 3822: 0000 unimp - 3824: 0301 addi t1,t1,0 - 3826: 0900 addi s0,sp,144 - 3828: 0000 unimp - 382a: 0301 addi t1,t1,0 - 382c: 0900 addi s0,sp,144 - 382e: 0000 unimp - 3830: 0501 addi a0,a0,0 - 3832: 0601 addi a2,a2,0 - 3834: 00097903 0x97903 + 37b8: 0301 addi t1,t1,0 + 37ba: 0901 addi s2,s2,0 + 37bc: 0000 unimp + 37be: 0301 addi t1,t1,0 + 37c0: 0902 c.slli64 s2 + 37c2: 0000 unimp + 37c4: 0301 addi t1,t1,0 + 37c6: 0901 addi s2,s2,0 + 37c8: 0000 unimp + 37ca: 0301 addi t1,t1,0 + 37cc: 0900 addi s0,sp,144 + 37ce: 0000 unimp + 37d0: 0301 addi t1,t1,0 + 37d2: 0900 addi s0,sp,144 + 37d4: 0000 unimp + 37d6: 0301 addi t1,t1,0 + 37d8: 0900 addi s0,sp,144 + 37da: 0000 unimp + 37dc: 0501 addi a0,a0,0 + 37de: 0601 addi a2,a2,0 + 37e0: 00097903 0x97903 + 37e4: 0100 addi s0,sp,128 + 37e6: 0305 addi t1,t1,1 + 37e8: 0306 slli t1,t1,0x1 + 37ea: 00040907 0x40907 + 37ee: 0501 addi a0,a0,0 + 37f0: 0601 addi a2,a2,0 + 37f2: 00097903 0x97903 + 37f6: 0100 addi s0,sp,128 + 37f8: 0305 addi t1,t1,1 + 37fa: 0306 slli t1,t1,0x1 + 37fc: 00040907 0x40907 + 3800: 0501 addi a0,a0,0 + 3802: 0601 addi a2,a2,0 + 3804: 00097903 0x97903 + 3808: 0100 addi s0,sp,128 + 380a: 0305 addi t1,t1,1 + 380c: 0306 slli t1,t1,0x1 + 380e: 00040907 0x40907 + 3812: 0501 addi a0,a0,0 + 3814: 0601 addi a2,a2,0 + 3816: 00097903 0x97903 + 381a: 0100 addi s0,sp,128 + 381c: 0305 addi t1,t1,1 + 381e: 08090703 lb a4,128(s2) + 3822: 0100 addi s0,sp,128 + 3824: 0c090103 lb sp,192(s2) + 3828: 0100 addi s0,sp,128 + 382a: 0105 addi sp,sp,1 + 382c: 08097803 0x8097803 + 3830: 0100 addi s0,sp,128 + 3832: 0305 addi t1,t1,1 + 3834: 0c090703 lb a4,192(s2) 3838: 0100 addi s0,sp,128 - 383a: 0305 addi t1,t1,1 - 383c: 0306 slli t1,t1,0x1 - 383e: 00040907 0x40907 - 3842: 0501 addi a0,a0,0 - 3844: 0601 addi a2,a2,0 - 3846: 00097903 0x97903 - 384a: 0100 addi s0,sp,128 - 384c: 0305 addi t1,t1,1 - 384e: 0306 slli t1,t1,0x1 - 3850: 00040907 0x40907 - 3854: 0501 addi a0,a0,0 - 3856: 0601 addi a2,a2,0 - 3858: 00097903 0x97903 - 385c: 0100 addi s0,sp,128 - 385e: 0305 addi t1,t1,1 - 3860: 0306 slli t1,t1,0x1 - 3862: 00040907 0x40907 - 3866: 0501 addi a0,a0,0 - 3868: 0601 addi a2,a2,0 - 386a: 00097903 0x97903 - 386e: 0100 addi s0,sp,128 - 3870: 0305 addi t1,t1,1 - 3872: 08090703 lb a4,128(s2) - 3876: 0100 addi s0,sp,128 - 3878: 0c090103 lb sp,192(s2) - 387c: 0100 addi s0,sp,128 - 387e: 0105 addi sp,sp,1 - 3880: 08097803 0x8097803 - 3884: 0100 addi s0,sp,128 - 3886: 0305 addi t1,t1,1 - 3888: 0c090703 lb a4,192(s2) - 388c: 0100 addi s0,sp,128 - 388e: 0105 addi sp,sp,1 - 3890: 08097903 0x8097903 - 3894: 0100 addi s0,sp,128 - 3896: 0305 addi t1,t1,1 - 3898: 04090703 lb a4,64(s2) - 389c: 0100 addi s0,sp,128 - 389e: 0306 slli t1,t1,0x1 + 383a: 0105 addi sp,sp,1 + 383c: 08097903 0x8097903 + 3840: 0100 addi s0,sp,128 + 3842: 0305 addi t1,t1,1 + 3844: 04090703 lb a4,64(s2) + 3848: 0100 addi s0,sp,128 + 384a: 0306 slli t1,t1,0x1 + 384c: 0900 addi s0,sp,144 + 384e: 0004 0x4 + 3850: 0301 addi t1,t1,0 + 3852: 0900 addi s0,sp,144 + 3854: 0000 unimp + 3856: 0301 addi t1,t1,0 + 3858: 0900 addi s0,sp,144 + 385a: 0004 0x4 + 385c: 0301 addi t1,t1,0 + 385e: 0901 addi s2,s2,0 + 3860: 0000 unimp + 3862: 0301 addi t1,t1,0 + 3864: 0900 addi s0,sp,144 + 3866: 0000 unimp + 3868: 0301 addi t1,t1,0 + 386a: 0900 addi s0,sp,144 + 386c: 0000 unimp + 386e: 0301 addi t1,t1,0 + 3870: 0900 addi s0,sp,144 + 3872: 0000 unimp + 3874: 0301 addi t1,t1,0 + 3876: 0900 addi s0,sp,144 + 3878: 0000 unimp + 387a: 0301 addi t1,t1,0 + 387c: 0900 addi s0,sp,144 + 387e: 0000 unimp + 3880: 0301 addi t1,t1,0 + 3882: 0900 addi s0,sp,144 + 3884: 0000 unimp + 3886: 0301 addi t1,t1,0 + 3888: 0900 addi s0,sp,144 + 388a: 0004 0x4 + 388c: 0301 addi t1,t1,0 + 388e: 0900 addi s0,sp,144 + 3890: 0004 0x4 + 3892: 0301 addi t1,t1,0 + 3894: 0900 addi s0,sp,144 + 3896: 0004 0x4 + 3898: 0301 addi t1,t1,0 + 389a: 0901 addi s2,s2,0 + 389c: 0000 unimp + 389e: 0301 addi t1,t1,0 38a0: 0900 addi s0,sp,144 - 38a2: 0004 0x4 + 38a2: 0000 unimp 38a4: 0301 addi t1,t1,0 38a6: 0900 addi s0,sp,144 38a8: 0000 unimp 38aa: 0301 addi t1,t1,0 38ac: 0900 addi s0,sp,144 - 38ae: 0004 0x4 + 38ae: 0000 unimp 38b0: 0301 addi t1,t1,0 - 38b2: 0901 addi s2,s2,0 + 38b2: 0900 addi s0,sp,144 38b4: 0000 unimp - 38b6: 0301 addi t1,t1,0 - 38b8: 0900 addi s0,sp,144 - 38ba: 0000 unimp - 38bc: 0301 addi t1,t1,0 - 38be: 0900 addi s0,sp,144 - 38c0: 0000 unimp - 38c2: 0301 addi t1,t1,0 - 38c4: 0900 addi s0,sp,144 - 38c6: 0000 unimp - 38c8: 0301 addi t1,t1,0 - 38ca: 0900 addi s0,sp,144 - 38cc: 0000 unimp - 38ce: 0301 addi t1,t1,0 - 38d0: 0900 addi s0,sp,144 - 38d2: 0000 unimp - 38d4: 0301 addi t1,t1,0 - 38d6: 0900 addi s0,sp,144 - 38d8: 0000 unimp - 38da: 0301 addi t1,t1,0 - 38dc: 0900 addi s0,sp,144 - 38de: 0004 0x4 - 38e0: 0301 addi t1,t1,0 + 38b6: 0001 nop + 38b8: 0402 c.slli64 s0 + 38ba: 0614 addi a3,sp,768 + 38bc: 04090003 lb zero,64(s2) + 38c0: 0100 addi s0,sp,128 + 38c2: 10090003 lb zero,256(s2) + 38c6: 0100 addi s0,sp,128 + 38c8: 0200 addi s0,sp,256 + 38ca: 1704 addi s1,sp,928 + 38cc: 08090003 lb zero,128(s2) + 38d0: 0100 addi s0,sp,128 + 38d2: 0200 addi s0,sp,256 + 38d4: 1804 addi s1,sp,48 + 38d6: 04090003 lb zero,64(s2) + 38da: 0100 addi s0,sp,128 + 38dc: 0200 addi s0,sp,256 + 38de: 3e04 fld fs1,56(a2) + 38e0: 0306 slli t1,t1,0x1 38e2: 0900 addi s0,sp,144 - 38e4: 0004 0x4 - 38e6: 0301 addi t1,t1,0 - 38e8: 0900 addi s0,sp,144 - 38ea: 0004 0x4 - 38ec: 0301 addi t1,t1,0 - 38ee: 0901 addi s2,s2,0 - 38f0: 0000 unimp - 38f2: 0301 addi t1,t1,0 - 38f4: 0900 addi s0,sp,144 - 38f6: 0000 unimp - 38f8: 0301 addi t1,t1,0 - 38fa: 0900 addi s0,sp,144 - 38fc: 0000 unimp - 38fe: 0301 addi t1,t1,0 + 38e4: 0010 0x10 + 38e6: 0001 nop + 38e8: 0402 c.slli64 s0 + 38ea: 033e slli t1,t1,0xf + 38ec: 0900 addi s0,sp,144 + 38ee: 0000 unimp + 38f0: 0001 nop + 38f2: 0402 c.slli64 s0 + 38f4: 033e slli t1,t1,0xf + 38f6: 0900 addi s0,sp,144 + 38f8: 0000 unimp + 38fa: 0001 nop + 38fc: 0402 c.slli64 s0 + 38fe: 033e slli t1,t1,0xf 3900: 0900 addi s0,sp,144 3902: 0000 unimp - 3904: 0301 addi t1,t1,0 - 3906: 0900 addi s0,sp,144 - 3908: 0000 unimp - 390a: 0001 nop - 390c: 0402 c.slli64 s0 - 390e: 0614 addi a3,sp,768 - 3910: 04090003 lb zero,64(s2) - 3914: 0100 addi s0,sp,128 - 3916: 10090003 lb zero,256(s2) - 391a: 0100 addi s0,sp,128 - 391c: 0200 addi s0,sp,256 - 391e: 1704 addi s1,sp,928 - 3920: 08090003 lb zero,128(s2) - 3924: 0100 addi s0,sp,128 - 3926: 0200 addi s0,sp,256 - 3928: 1804 addi s1,sp,48 - 392a: 04090003 lb zero,64(s2) - 392e: 0100 addi s0,sp,128 - 3930: 0200 addi s0,sp,256 - 3932: 3e04 fld fs1,56(a2) - 3934: 0306 slli t1,t1,0x1 - 3936: 0900 addi s0,sp,144 - 3938: 0010 0x10 - 393a: 0001 nop - 393c: 0402 c.slli64 s0 - 393e: 033e slli t1,t1,0xf - 3940: 0900 addi s0,sp,144 - 3942: 0000 unimp - 3944: 0001 nop - 3946: 0402 c.slli64 s0 - 3948: 033e slli t1,t1,0xf - 394a: 0900 addi s0,sp,144 - 394c: 0000 unimp - 394e: 0001 nop - 3950: 0402 c.slli64 s0 - 3952: 033e slli t1,t1,0xf - 3954: 0900 addi s0,sp,144 - 3956: 0000 unimp - 3958: 0001 nop - 395a: 0402 c.slli64 s0 - 395c: 033e slli t1,t1,0xf - 395e: 0900 addi s0,sp,144 - 3960: 0000 unimp - 3962: 0001 nop - 3964: 0402 c.slli64 s0 - 3966: 033e slli t1,t1,0xf - 3968: 0900 addi s0,sp,144 - 396a: 0000 unimp - 396c: 0001 nop - 396e: 0402 c.slli64 s0 - 3970: 033e slli t1,t1,0xf - 3972: 0900 addi s0,sp,144 - 3974: 0000 unimp - 3976: 0001 nop - 3978: 0402 c.slli64 s0 - 397a: 033e slli t1,t1,0xf - 397c: 0900 addi s0,sp,144 - 397e: 0000 unimp - 3980: 0001 nop - 3982: 0402 c.slli64 s0 - 3984: 033e slli t1,t1,0xf - 3986: 0900 addi s0,sp,144 - 3988: 0000 unimp - 398a: 0001 nop - 398c: 0402 c.slli64 s0 - 398e: 033e slli t1,t1,0xf - 3990: 0900 addi s0,sp,144 - 3992: 0000 unimp - 3994: 0001 nop - 3996: 0402 c.slli64 s0 - 3998: 033e slli t1,t1,0xf - 399a: 0900 addi s0,sp,144 - 399c: 0000 unimp - 399e: 0001 nop - 39a0: 0402 c.slli64 s0 - 39a2: 033e slli t1,t1,0xf - 39a4: 0900 addi s0,sp,144 - 39a6: 0000 unimp - 39a8: 0001 nop - 39aa: 0402 c.slli64 s0 - 39ac: 0003063f 01000409 0x10004090003063f - 39b4: 0200 addi s0,sp,256 - 39b6: 3f04 fld fs1,56(a4) - 39b8: 0306 slli t1,t1,0x1 + 3904: 0001 nop + 3906: 0402 c.slli64 s0 + 3908: 033e slli t1,t1,0xf + 390a: 0900 addi s0,sp,144 + 390c: 0000 unimp + 390e: 0001 nop + 3910: 0402 c.slli64 s0 + 3912: 033e slli t1,t1,0xf + 3914: 0900 addi s0,sp,144 + 3916: 0000 unimp + 3918: 0001 nop + 391a: 0402 c.slli64 s0 + 391c: 033e slli t1,t1,0xf + 391e: 0900 addi s0,sp,144 + 3920: 0000 unimp + 3922: 0001 nop + 3924: 0402 c.slli64 s0 + 3926: 033e slli t1,t1,0xf + 3928: 0900 addi s0,sp,144 + 392a: 0000 unimp + 392c: 0001 nop + 392e: 0402 c.slli64 s0 + 3930: 033e slli t1,t1,0xf + 3932: 0900 addi s0,sp,144 + 3934: 0000 unimp + 3936: 0001 nop + 3938: 0402 c.slli64 s0 + 393a: 033e slli t1,t1,0xf + 393c: 0900 addi s0,sp,144 + 393e: 0000 unimp + 3940: 0001 nop + 3942: 0402 c.slli64 s0 + 3944: 033e slli t1,t1,0xf + 3946: 0900 addi s0,sp,144 + 3948: 0000 unimp + 394a: 0001 nop + 394c: 0402 c.slli64 s0 + 394e: 033e slli t1,t1,0xf + 3950: 0900 addi s0,sp,144 + 3952: 0000 unimp + 3954: 0001 nop + 3956: 0402 c.slli64 s0 + 3958: 0003063f 01000409 0x10004090003063f + 3960: 0200 addi s0,sp,256 + 3962: 3f04 fld fs1,56(a4) + 3964: 0306 slli t1,t1,0x1 + 3966: 0900 addi s0,sp,144 + 3968: 0010 0x10 + 396a: 0001 nop + 396c: 0402 c.slli64 s0 + 396e: 0645 addi a2,a2,17 + 3970: 04090003 lb zero,64(s2) + 3974: 0100 addi s0,sp,128 + 3976: 0306 slli t1,t1,0x1 + 3978: 0900 addi s0,sp,144 + 397a: 0010 0x10 + 397c: 0301 addi t1,t1,0 + 397e: 0900 addi s0,sp,144 + 3980: 0004 0x4 + 3982: 0301 addi t1,t1,0 + 3984: 0900 addi s0,sp,144 + 3986: 0000 unimp + 3988: 0301 addi t1,t1,0 + 398a: 0900 addi s0,sp,144 + 398c: 0000 unimp + 398e: 0001 nop + 3990: 0402 c.slli64 s0 + 3992: 035f 0900 0004 0x40900035f + 3998: 0001 nop + 399a: 0402 c.slli64 s0 + 399c: 037f 0x37f + 399e: 0900 addi s0,sp,144 + 39a0: 0004 0x4 + 39a2: 0601 addi a2,a2,0 + 39a4: 04090003 lb zero,64(s2) + 39a8: 0100 addi s0,sp,128 + 39aa: 0200 addi s0,sp,256 + 39ac: 5004 lw s1,32(s0) + 39ae: 0306 slli t1,t1,0x1 + 39b0: 0900 addi s0,sp,144 + 39b2: 0008 0x8 + 39b4: 0001 nop + 39b6: 0402 c.slli64 s0 + 39b8: 0350 addi a2,sp,388 39ba: 0900 addi s0,sp,144 - 39bc: 0010 0x10 - 39be: 0001 nop - 39c0: 0402 c.slli64 s0 - 39c2: 0645 addi a2,a2,17 - 39c4: 04090003 lb zero,64(s2) - 39c8: 0100 addi s0,sp,128 - 39ca: 0306 slli t1,t1,0x1 - 39cc: 0900 addi s0,sp,144 - 39ce: 0010 0x10 - 39d0: 0301 addi t1,t1,0 - 39d2: 0900 addi s0,sp,144 - 39d4: 0004 0x4 - 39d6: 0301 addi t1,t1,0 - 39d8: 0900 addi s0,sp,144 - 39da: 0000 unimp - 39dc: 0301 addi t1,t1,0 - 39de: 0900 addi s0,sp,144 - 39e0: 0000 unimp - 39e2: 0001 nop - 39e4: 0402 c.slli64 s0 - 39e6: 035f 0900 0004 0x40900035f - 39ec: 0001 nop - 39ee: 0402 c.slli64 s0 - 39f0: 037f 0x37f - 39f2: 0900 addi s0,sp,144 - 39f4: 0004 0x4 - 39f6: 0601 addi a2,a2,0 - 39f8: 04090003 lb zero,64(s2) - 39fc: 0100 addi s0,sp,128 - 39fe: 0200 addi s0,sp,256 - 3a00: 5004 lw s1,32(s0) - 3a02: 0306 slli t1,t1,0x1 - 3a04: 0900 addi s0,sp,144 - 3a06: 0008 0x8 - 3a08: 0001 nop - 3a0a: 0402 c.slli64 s0 - 3a0c: 0350 addi a2,sp,388 - 3a0e: 0900 addi s0,sp,144 - 3a10: 0000 unimp - 3a12: 0601 addi a2,a2,0 - 3a14: 08090003 lb zero,128(s2) - 3a18: 0100 addi s0,sp,128 - 3a1a: 0105 addi sp,sp,1 - 3a1c: 04090403 lb s0,64(s2) - 3a20: 0100 addi s0,sp,128 - 3a22: 0305 addi t1,t1,1 - 3a24: 0200 addi s0,sp,256 - 3a26: 6604 flw fs1,8(a2) - 3a28: 0306 slli t1,t1,0x1 - 3a2a: 097c addi a5,sp,156 - 3a2c: 0008 0x8 - 3a2e: 0001 nop - 3a30: 01920403 lb s0,25(tp) # 1a019 <_start-0x7ffe5fe7> - 3a34: 04090003 lb zero,64(s2) - 3a38: 0100 addi s0,sp,128 - 3a3a: 0200 addi s0,sp,256 - 3a3c: 6d04 flw fs1,24(a0) - 3a3e: 08090003 lb zero,128(s2) - 3a42: 0100 addi s0,sp,128 - 3a44: 0200 addi s0,sp,256 - 3a46: 7404 flw fs1,40(s0) - 3a48: 0306 slli t1,t1,0x1 - 3a4a: 0900 addi s0,sp,144 - 3a4c: 0004 0x4 - 3a4e: 0001 nop - 3a50: 0402 c.slli64 s0 - 3a52: 0375 addi t1,t1,29 - 3a54: 0900 addi s0,sp,144 - 3a56: 0004 0x4 - 3a58: 0001 nop - 3a5a: 0402 c.slli64 s0 - 3a5c: 0378 addi a4,sp,396 + 39bc: 0000 unimp + 39be: 0601 addi a2,a2,0 + 39c0: 08090003 lb zero,128(s2) + 39c4: 0100 addi s0,sp,128 + 39c6: 0105 addi sp,sp,1 + 39c8: 04090403 lb s0,64(s2) + 39cc: 0100 addi s0,sp,128 + 39ce: 0305 addi t1,t1,1 + 39d0: 0200 addi s0,sp,256 + 39d2: 6604 flw fs1,8(a2) + 39d4: 0306 slli t1,t1,0x1 + 39d6: 097c addi a5,sp,156 + 39d8: 0008 0x8 + 39da: 0001 nop + 39dc: 01920403 lb s0,25(tp) # 1a019 <_start-0x7ffe5fe7> + 39e0: 04090003 lb zero,64(s2) + 39e4: 0100 addi s0,sp,128 + 39e6: 0200 addi s0,sp,256 + 39e8: 6d04 flw fs1,24(a0) + 39ea: 08090003 lb zero,128(s2) + 39ee: 0100 addi s0,sp,128 + 39f0: 0200 addi s0,sp,256 + 39f2: 7404 flw fs1,40(s0) + 39f4: 0306 slli t1,t1,0x1 + 39f6: 0900 addi s0,sp,144 + 39f8: 0004 0x4 + 39fa: 0001 nop + 39fc: 0402 c.slli64 s0 + 39fe: 0375 addi t1,t1,29 + 3a00: 0900 addi s0,sp,144 + 3a02: 0004 0x4 + 3a04: 0001 nop + 3a06: 0402 c.slli64 s0 + 3a08: 0378 addi a4,sp,396 + 3a0a: 0900 addi s0,sp,144 + 3a0c: 0004 0x4 + 3a0e: 0001 nop + 3a10: 0402 c.slli64 s0 + 3a12: 0379 addi t1,t1,30 + 3a14: 0900 addi s0,sp,144 + 3a16: 0004 0x4 + 3a18: 0001 nop + 3a1a: 0402 c.slli64 s0 + 3a1c: 037c addi a5,sp,396 + 3a1e: 0900 addi s0,sp,144 + 3a20: 0004 0x4 + 3a22: 0001 nop + 3a24: 0402 c.slli64 s0 + 3a26: 037d addi t1,t1,31 + 3a28: 0900 addi s0,sp,144 + 3a2a: 0004 0x4 + 3a2c: 0001 nop + 3a2e: 018c0403 lb s0,24(s8) + 3a32: 0306 slli t1,t1,0x1 + 3a34: 0900 addi s0,sp,144 + 3a36: 0004 0x4 + 3a38: 0001 nop + 3a3a: 018f0403 lb s0,24(t5) # 1b018 <_start-0x7ffe4fe8> + 3a3e: 0306 slli t1,t1,0x1 + 3a40: 0900 addi s0,sp,144 + 3a42: 0004 0x4 + 3a44: 0001 nop + 3a46: 01900403 lb s0,25(zero) # 19 <_start-0x7fffffe7> + 3a4a: 04090003 lb zero,64(s2) + 3a4e: 0100 addi s0,sp,128 + 3a50: 04090003 lb zero,64(s2) + 3a54: 0100 addi s0,sp,128 + 3a56: 0306 slli t1,t1,0x1 + 3a58: 0900 addi s0,sp,144 + 3a5a: 0010 0x10 + 3a5c: 0301 addi t1,t1,0 3a5e: 0900 addi s0,sp,144 - 3a60: 0004 0x4 - 3a62: 0001 nop - 3a64: 0402 c.slli64 s0 - 3a66: 0379 addi t1,t1,30 - 3a68: 0900 addi s0,sp,144 - 3a6a: 0004 0x4 - 3a6c: 0001 nop - 3a6e: 0402 c.slli64 s0 - 3a70: 037c addi a5,sp,396 - 3a72: 0900 addi s0,sp,144 - 3a74: 0004 0x4 - 3a76: 0001 nop - 3a78: 0402 c.slli64 s0 - 3a7a: 037d addi t1,t1,31 - 3a7c: 0900 addi s0,sp,144 - 3a7e: 0004 0x4 - 3a80: 0001 nop - 3a82: 018c0403 lb s0,24(s8) - 3a86: 0306 slli t1,t1,0x1 - 3a88: 0900 addi s0,sp,144 - 3a8a: 0004 0x4 + 3a60: 0008 0x8 + 3a62: 0301 addi t1,t1,0 + 3a64: 0900 addi s0,sp,144 + 3a66: 0008 0x8 + 3a68: 0301 addi t1,t1,0 + 3a6a: 0900 addi s0,sp,144 + 3a6c: 000c 0xc + 3a6e: 0901 addi s2,s2,0 + 3a70: 000c 0xc + 3a72: 0100 addi s0,sp,128 + 3a74: 2301 jal 3f74 <_start-0x7fffc08c> + 3a76: 03000023 sb a6,32(zero) # 20 <_start-0x7fffffe0> + 3a7a: 9100 0x9100 + 3a7c: 0000 unimp + 3a7e: 0100 addi s0,sp,128 + 3a80: fb01 bnez a4,3990 <_start-0x7fffc670> + 3a82: 0d0e slli s10,s10,0x3 + 3a84: 0100 addi s0,sp,128 + 3a86: 0101 addi sp,sp,0 + 3a88: 0001 nop + 3a8a: 0000 unimp 3a8c: 0001 nop - 3a8e: 018f0403 lb s0,24(t5) - 3a92: 0306 slli t1,t1,0x1 - 3a94: 0900 addi s0,sp,144 - 3a96: 0004 0x4 - 3a98: 0001 nop - 3a9a: 01900403 lb s0,25(zero) # 19 <_start-0x7fffffe7> - 3a9e: 04090003 lb zero,64(s2) - 3aa2: 0100 addi s0,sp,128 - 3aa4: 04090003 lb zero,64(s2) - 3aa8: 0100 addi s0,sp,128 - 3aaa: 0306 slli t1,t1,0x1 - 3aac: 0900 addi s0,sp,144 - 3aae: 0010 0x10 - 3ab0: 0301 addi t1,t1,0 - 3ab2: 0900 addi s0,sp,144 - 3ab4: 0008 0x8 - 3ab6: 0301 addi t1,t1,0 - 3ab8: 0900 addi s0,sp,144 - 3aba: 0008 0x8 - 3abc: 0301 addi t1,t1,0 - 3abe: 0900 addi s0,sp,144 - 3ac0: 000c 0xc - 3ac2: 0901 addi s2,s2,0 - 3ac4: 000c 0xc - 3ac6: 0100 addi s0,sp,128 - 3ac8: 2301 jal 3fc8 <_start-0x7fffc038> - 3aca: 03000023 sb a6,32(zero) # 20 <_start-0x7fffffe0> - 3ace: 9100 0x9100 - 3ad0: 0000 unimp - 3ad2: 0100 addi s0,sp,128 - 3ad4: fb01 bnez a4,39e4 <_start-0x7fffc61c> - 3ad6: 0d0e slli s10,s10,0x3 - 3ad8: 0100 addi s0,sp,128 - 3ada: 0101 addi sp,sp,0 - 3adc: 0001 nop - 3ade: 0000 unimp - 3ae0: 0001 nop - 3ae2: 0100 addi s0,sp,128 - 3ae4: 2e2e fld ft8,200(sp) - 3ae6: 2f2e2e2f 0x2f2e2e2f - 3aea: 2e2e fld ft8,200(sp) - 3aec: 2f2e2e2f 0x2f2e2e2f - 3af0: 6972 flw fs2,28(sp) - 3af2: 2d766373 csrrsi t1,0x2d7,12 - 3af6: 2f636367 0x2f636367 - 3afa: 696c flw fa1,84(a0) - 3afc: 6762 flw fa4,24(sp) - 3afe: 732f6363 bltu t5,s2,4224 <_start-0x7fffbddc> - 3b02: 2d74666f jal a2,4a5d8 <_start-0x7ffb5a28> - 3b06: 7066 flw ft0,120(sp) - 3b08: 2e00 fld fs0,24(a2) - 3b0a: 2f2e fld ft10,200(sp) - 3b0c: 2e2e fld ft8,200(sp) - 3b0e: 2f2e2e2f 0x2f2e2e2f - 3b12: 2e2e fld ft8,200(sp) - 3b14: 7369722f 0x7369722f - 3b18: 672d7663 bgeu s10,s2,4184 <_start-0x7fffbe7c> - 3b1c: 6c2f6363 bltu t5,sp,41e2 <_start-0x7fffbe1e> - 3b20: 6269 lui tp,0x1a - 3b22: 2f636367 0x2f636367 - 3b26: 2e2e fld ft8,200(sp) - 3b28: 636e692f 0x636e692f - 3b2c: 756c flw fa1,108(a0) - 3b2e: 6564 flw fs1,76(a0) - 3b30: 0000 unimp - 3b32: 756d lui a0,0xffffb - 3b34: 746c flw fa1,108(s0) - 3b36: 3366 fld ft6,120(sp) - 3b38: 632e flw ft6,200(sp) - 3b3a: 0100 addi s0,sp,128 - 3b3c: 0000 unimp - 3b3e: 74666f73 csrrsi t5,0x746,12 - 3b42: 662d lui a2,0xb - 3b44: 2e70 fld fa2,216(a2) - 3b46: 0068 addi a0,sp,12 - 3b48: 0001 nop - 3b4a: 7100 flw fs0,32(a0) - 3b4c: 6175 addi sp,sp,368 - 3b4e: 2e64 fld fs1,216(a2) - 3b50: 0068 addi a0,sp,12 - 3b52: 0001 nop - 3b54: 6c00 flw fs0,24(s0) - 3b56: 6c676e6f jal t3,7a21c <_start-0x7ff85de4> - 3b5a: 2e676e6f jal t3,79e40 <_start-0x7ff861c0> - 3b5e: 0068 addi a0,sp,12 - 3b60: 0002 c.slli64 zero - 3b62: 0000 unimp - 3b64: 0105 addi sp,sp,1 - 3b66: 0500 addi s0,sp,640 - 3b68: 3c02 fld fs8,32(sp) - 3b6a: 011c addi a5,sp,128 - 3b6c: 0380 addi s0,sp,448 - 3b6e: 03050123 sb a6,34(a0) # ffffb022 <__BSS_END__+0x7ffe43f2> - 3b72: 00090103 lb sp,0(s2) - 3b76: 0100 addi s0,sp,128 - 3b78: 00090003 lb zero,0(s2) - 3b7c: 0100 addi s0,sp,128 - 3b7e: 0d05 addi s10,s10,1 - 3b80: 00090003 lb zero,0(s2) - 3b84: 0100 addi s0,sp,128 - 3b86: 0305 addi t1,t1,1 + 3a8e: 0100 addi s0,sp,128 + 3a90: 2e2e fld ft8,200(sp) + 3a92: 2f2e2e2f 0x2f2e2e2f + 3a96: 2e2e fld ft8,200(sp) + 3a98: 2f2e2e2f 0x2f2e2e2f + 3a9c: 6972 flw fs2,28(sp) + 3a9e: 2d766373 csrrsi t1,0x2d7,12 + 3aa2: 2f636367 0x2f636367 + 3aa6: 696c flw fa1,84(a0) + 3aa8: 6762 flw fa4,24(sp) + 3aaa: 732f6363 bltu t5,s2,41d0 <_start-0x7fffbe30> + 3aae: 2d74666f jal a2,4a584 <_start-0x7ffb5a7c> + 3ab2: 7066 flw ft0,120(sp) + 3ab4: 2e00 fld fs0,24(a2) + 3ab6: 2f2e fld ft10,200(sp) + 3ab8: 2e2e fld ft8,200(sp) + 3aba: 2f2e2e2f 0x2f2e2e2f + 3abe: 2e2e fld ft8,200(sp) + 3ac0: 7369722f 0x7369722f + 3ac4: 672d7663 bgeu s10,s2,4130 <_start-0x7fffbed0> + 3ac8: 6c2f6363 bltu t5,sp,418e <_start-0x7fffbe72> + 3acc: 6269 lui tp,0x1a + 3ace: 2f636367 0x2f636367 + 3ad2: 2e2e fld ft8,200(sp) + 3ad4: 636e692f 0x636e692f + 3ad8: 756c flw fa1,108(a0) + 3ada: 6564 flw fs1,76(a0) + 3adc: 0000 unimp + 3ade: 756d lui a0,0xffffb + 3ae0: 746c flw fa1,108(s0) + 3ae2: 3366 fld ft6,120(sp) + 3ae4: 632e flw ft6,200(sp) + 3ae6: 0100 addi s0,sp,128 + 3ae8: 0000 unimp + 3aea: 74666f73 csrrsi t5,0x746,12 + 3aee: 662d lui a2,0xb + 3af0: 2e70 fld fa2,216(a2) + 3af2: 0068 addi a0,sp,12 + 3af4: 0001 nop + 3af6: 7100 flw fs0,32(a0) + 3af8: 6175 addi sp,sp,368 + 3afa: 2e64 fld fs1,216(a2) + 3afc: 0068 addi a0,sp,12 + 3afe: 0001 nop + 3b00: 6c00 flw fs0,24(s0) + 3b02: 6c676e6f jal t3,7a1c8 <_start-0x7ff85e38> + 3b06: 2e676e6f jal t3,79dec <_start-0x7ff86214> + 3b0a: 0068 addi a0,sp,12 + 3b0c: 0002 c.slli64 zero + 3b0e: 0000 unimp + 3b10: 0105 addi sp,sp,1 + 3b12: 0500 addi s0,sp,640 + 3b14: 0002 c.slli64 zero + 3b16: 011d addi sp,sp,7 + 3b18: 0380 addi s0,sp,448 + 3b1a: 03050123 sb a6,34(a0) # ffffb022 <__BSS_END__+0x7ffe43e6> + 3b1e: 00090103 lb sp,0(s2) + 3b22: 0100 addi s0,sp,128 + 3b24: 00090003 lb zero,0(s2) + 3b28: 0100 addi s0,sp,128 + 3b2a: 0d05 addi s10,s10,1 + 3b2c: 00090003 lb zero,0(s2) + 3b30: 0100 addi s0,sp,128 + 3b32: 0305 addi t1,t1,1 + 3b34: 00090103 lb sp,0(s2) + 3b38: 0100 addi s0,sp,128 + 3b3a: 00090003 lb zero,0(s2) + 3b3e: 0100 addi s0,sp,128 + 3b40: 00090003 lb zero,0(s2) + 3b44: 0100 addi s0,sp,128 + 3b46: 00090003 lb zero,0(s2) + 3b4a: 0100 addi s0,sp,128 + 3b4c: 00090103 lb sp,0(s2) + 3b50: 0100 addi s0,sp,128 + 3b52: 00090003 lb zero,0(s2) + 3b56: 0100 addi s0,sp,128 + 3b58: 00090003 lb zero,0(s2) + 3b5c: 0100 addi s0,sp,128 + 3b5e: 00090003 lb zero,0(s2) + 3b62: 0100 addi s0,sp,128 + 3b64: 00090103 lb sp,0(s2) + 3b68: 0100 addi s0,sp,128 + 3b6a: 00090003 lb zero,0(s2) + 3b6e: 0100 addi s0,sp,128 + 3b70: 00090003 lb zero,0(s2) + 3b74: 0100 addi s0,sp,128 + 3b76: 00090003 lb zero,0(s2) + 3b7a: 0100 addi s0,sp,128 + 3b7c: 00090103 lb sp,0(s2) + 3b80: 0100 addi s0,sp,128 + 3b82: 00090203 lb tp,0(s2) + 3b86: 0100 addi s0,sp,128 3b88: 00090103 lb sp,0(s2) 3b8c: 0100 addi s0,sp,128 3b8e: 00090003 lb zero,0(s2) @@ -47663,3613 +47699,3627 @@ Disassembly of section .debug_line: 3b98: 0100 addi s0,sp,128 3b9a: 00090003 lb zero,0(s2) 3b9e: 0100 addi s0,sp,128 - 3ba0: 00090103 lb sp,0(s2) - 3ba4: 0100 addi s0,sp,128 - 3ba6: 00090003 lb zero,0(s2) - 3baa: 0100 addi s0,sp,128 - 3bac: 00090003 lb zero,0(s2) - 3bb0: 0100 addi s0,sp,128 - 3bb2: 00090003 lb zero,0(s2) - 3bb6: 0100 addi s0,sp,128 - 3bb8: 00090103 lb sp,0(s2) - 3bbc: 0100 addi s0,sp,128 - 3bbe: 00090003 lb zero,0(s2) - 3bc2: 0100 addi s0,sp,128 - 3bc4: 00090003 lb zero,0(s2) - 3bc8: 0100 addi s0,sp,128 - 3bca: 00090003 lb zero,0(s2) - 3bce: 0100 addi s0,sp,128 - 3bd0: 00090103 lb sp,0(s2) - 3bd4: 0100 addi s0,sp,128 - 3bd6: 00090203 lb tp,0(s2) - 3bda: 0100 addi s0,sp,128 - 3bdc: 00090103 lb sp,0(s2) - 3be0: 0100 addi s0,sp,128 - 3be2: 00090003 lb zero,0(s2) - 3be6: 0100 addi s0,sp,128 - 3be8: 00090003 lb zero,0(s2) - 3bec: 0100 addi s0,sp,128 - 3bee: 00090003 lb zero,0(s2) - 3bf2: 0100 addi s0,sp,128 - 3bf4: 0105 addi sp,sp,1 - 3bf6: 0306 slli t1,t1,0x1 - 3bf8: 0978 addi a4,sp,156 - 3bfa: 0000 unimp - 3bfc: 0501 addi a0,a0,0 - 3bfe: 09080303 lb t1,144(a6) - 3c02: 0040 addi s0,sp,4 - 3c04: 0501 addi a0,a0,0 - 3c06: 0301 addi t1,t1,0 - 3c08: 0978 addi a4,sp,156 - 3c0a: 0004 0x4 - 3c0c: 0501 addi a0,a0,0 - 3c0e: 09080303 lb t1,144(a6) - 3c12: 0008 0x8 - 3c14: 0601 addi a2,a2,0 - 3c16: 0c090003 lb zero,192(s2) - 3c1a: 0100 addi s0,sp,128 - 3c1c: 0105 addi sp,sp,1 - 3c1e: 0306 slli t1,t1,0x1 - 3c20: 0978 addi a4,sp,156 - 3c22: 0000 unimp - 3c24: 0501 addi a0,a0,0 - 3c26: 09080303 lb t1,144(a6) - 3c2a: 001c 0x1c - 3c2c: 0601 addi a2,a2,0 - 3c2e: 10090003 lb zero,256(s2) - 3c32: 0100 addi s0,sp,128 - 3c34: 04090003 lb zero,64(s2) - 3c38: 0100 addi s0,sp,128 - 3c3a: 04090003 lb zero,64(s2) - 3c3e: 0100 addi s0,sp,128 - 3c40: 04090003 lb zero,64(s2) + 3ba0: 0105 addi sp,sp,1 + 3ba2: 0306 slli t1,t1,0x1 + 3ba4: 0978 addi a4,sp,156 + 3ba6: 0000 unimp + 3ba8: 0501 addi a0,a0,0 + 3baa: 09080303 lb t1,144(a6) + 3bae: 0040 addi s0,sp,4 + 3bb0: 0501 addi a0,a0,0 + 3bb2: 0301 addi t1,t1,0 + 3bb4: 0978 addi a4,sp,156 + 3bb6: 0004 0x4 + 3bb8: 0501 addi a0,a0,0 + 3bba: 09080303 lb t1,144(a6) + 3bbe: 0008 0x8 + 3bc0: 0601 addi a2,a2,0 + 3bc2: 0c090003 lb zero,192(s2) + 3bc6: 0100 addi s0,sp,128 + 3bc8: 0105 addi sp,sp,1 + 3bca: 0306 slli t1,t1,0x1 + 3bcc: 0978 addi a4,sp,156 + 3bce: 0000 unimp + 3bd0: 0501 addi a0,a0,0 + 3bd2: 09080303 lb t1,144(a6) + 3bd6: 001c 0x1c + 3bd8: 0601 addi a2,a2,0 + 3bda: 10090003 lb zero,256(s2) + 3bde: 0100 addi s0,sp,128 + 3be0: 04090003 lb zero,64(s2) + 3be4: 0100 addi s0,sp,128 + 3be6: 04090003 lb zero,64(s2) + 3bea: 0100 addi s0,sp,128 + 3bec: 04090003 lb zero,64(s2) + 3bf0: 0100 addi s0,sp,128 + 3bf2: 04090003 lb zero,64(s2) + 3bf6: 0100 addi s0,sp,128 + 3bf8: 04090003 lb zero,64(s2) + 3bfc: 0100 addi s0,sp,128 + 3bfe: 00090003 lb zero,0(s2) + 3c02: 0100 addi s0,sp,128 + 3c04: 00090003 lb zero,0(s2) + 3c08: 0100 addi s0,sp,128 + 3c0a: 0200 addi s0,sp,256 + 3c0c: 0104 addi s1,sp,128 + 3c0e: 08090003 lb zero,128(s2) + 3c12: 0100 addi s0,sp,128 + 3c14: 0200 addi s0,sp,256 + 3c16: 0104 addi s1,sp,128 + 3c18: 0c090003 lb zero,192(s2) + 3c1c: 0100 addi s0,sp,128 + 3c1e: 0200 addi s0,sp,256 + 3c20: 0104 addi s1,sp,128 + 3c22: 00090003 lb zero,0(s2) + 3c26: 0100 addi s0,sp,128 + 3c28: 0200 addi s0,sp,256 + 3c2a: 0104 addi s1,sp,128 + 3c2c: 00090003 lb zero,0(s2) + 3c30: 0100 addi s0,sp,128 + 3c32: 0200 addi s0,sp,256 + 3c34: 0104 addi s1,sp,128 + 3c36: 00090003 lb zero,0(s2) + 3c3a: 0100 addi s0,sp,128 + 3c3c: 0200 addi s0,sp,256 + 3c3e: 0104 addi s1,sp,128 + 3c40: 00090003 lb zero,0(s2) 3c44: 0100 addi s0,sp,128 - 3c46: 04090003 lb zero,64(s2) - 3c4a: 0100 addi s0,sp,128 - 3c4c: 04090003 lb zero,64(s2) - 3c50: 0100 addi s0,sp,128 - 3c52: 00090003 lb zero,0(s2) - 3c56: 0100 addi s0,sp,128 - 3c58: 00090003 lb zero,0(s2) - 3c5c: 0100 addi s0,sp,128 - 3c5e: 0200 addi s0,sp,256 - 3c60: 0104 addi s1,sp,128 - 3c62: 08090003 lb zero,128(s2) - 3c66: 0100 addi s0,sp,128 - 3c68: 0200 addi s0,sp,256 - 3c6a: 0104 addi s1,sp,128 - 3c6c: 0c090003 lb zero,192(s2) - 3c70: 0100 addi s0,sp,128 - 3c72: 0200 addi s0,sp,256 - 3c74: 0104 addi s1,sp,128 - 3c76: 00090003 lb zero,0(s2) - 3c7a: 0100 addi s0,sp,128 - 3c7c: 0200 addi s0,sp,256 - 3c7e: 0104 addi s1,sp,128 - 3c80: 00090003 lb zero,0(s2) - 3c84: 0100 addi s0,sp,128 - 3c86: 0200 addi s0,sp,256 - 3c88: 0104 addi s1,sp,128 - 3c8a: 00090003 lb zero,0(s2) - 3c8e: 0100 addi s0,sp,128 - 3c90: 0200 addi s0,sp,256 - 3c92: 0104 addi s1,sp,128 - 3c94: 00090003 lb zero,0(s2) - 3c98: 0100 addi s0,sp,128 - 3c9a: 0200 addi s0,sp,256 - 3c9c: 0104 addi s1,sp,128 - 3c9e: 00090003 lb zero,0(s2) - 3ca2: 0100 addi s0,sp,128 - 3ca4: 0200 addi s0,sp,256 - 3ca6: 0104 addi s1,sp,128 - 3ca8: 00090003 lb zero,0(s2) - 3cac: 0100 addi s0,sp,128 - 3cae: 0200 addi s0,sp,256 - 3cb0: 0104 addi s1,sp,128 - 3cb2: 00090003 lb zero,0(s2) - 3cb6: 0100 addi s0,sp,128 - 3cb8: 0200 addi s0,sp,256 - 3cba: 0104 addi s1,sp,128 - 3cbc: 00090003 lb zero,0(s2) - 3cc0: 0100 addi s0,sp,128 - 3cc2: 0200 addi s0,sp,256 - 3cc4: 0b04 addi s1,sp,400 - 3cc6: 08090003 lb zero,128(s2) - 3cca: 0100 addi s0,sp,128 - 3ccc: 0200 addi s0,sp,256 - 3cce: 0b04 addi s1,sp,400 - 3cd0: 1c090003 lb zero,448(s2) - 3cd4: 0100 addi s0,sp,128 - 3cd6: 0200 addi s0,sp,256 - 3cd8: 0b04 addi s1,sp,400 - 3cda: 00090003 lb zero,0(s2) - 3cde: 0100 addi s0,sp,128 - 3ce0: 0200 addi s0,sp,256 - 3ce2: 0c04 addi s1,sp,528 - 3ce4: 04090003 lb zero,64(s2) - 3ce8: 0100 addi s0,sp,128 - 3cea: 0200 addi s0,sp,256 - 3cec: 0c04 addi s1,sp,528 - 3cee: 14090003 lb zero,320(s2) - 3cf2: 0100 addi s0,sp,128 - 3cf4: 0200 addi s0,sp,256 - 3cf6: 0c04 addi s1,sp,528 - 3cf8: 00090003 lb zero,0(s2) - 3cfc: 0100 addi s0,sp,128 - 3cfe: 0200 addi s0,sp,256 - 3d00: 0c04 addi s1,sp,528 - 3d02: 00090003 lb zero,0(s2) - 3d06: 0100 addi s0,sp,128 - 3d08: 0200 addi s0,sp,256 - 3d0a: 0c04 addi s1,sp,528 - 3d0c: 04090003 lb zero,64(s2) - 3d10: 0100 addi s0,sp,128 - 3d12: 0200 addi s0,sp,256 - 3d14: 0c04 addi s1,sp,528 - 3d16: 00090003 lb zero,0(s2) - 3d1a: 0100 addi s0,sp,128 - 3d1c: 0200 addi s0,sp,256 - 3d1e: 4904 lw s1,16(a0) - 3d20: 00090003 lb zero,0(s2) - 3d24: 0100 addi s0,sp,128 - 3d26: 0200 addi s0,sp,256 - 3d28: 4904 lw s1,16(a0) - 3d2a: 00090003 lb zero,0(s2) - 3d2e: 0100 addi s0,sp,128 - 3d30: 0200 addi s0,sp,256 - 3d32: 1104 addi s1,sp,160 - 3d34: 04090003 lb zero,64(s2) - 3d38: 0100 addi s0,sp,128 - 3d3a: 0200 addi s0,sp,256 - 3d3c: 1104 addi s1,sp,160 - 3d3e: 00090003 lb zero,0(s2) - 3d42: 0100 addi s0,sp,128 - 3d44: 0200 addi s0,sp,256 - 3d46: 1104 addi s1,sp,160 - 3d48: 00090103 lb sp,0(s2) - 3d4c: 0100 addi s0,sp,128 - 3d4e: 0200 addi s0,sp,256 - 3d50: 1104 addi s1,sp,160 - 3d52: 00090003 lb zero,0(s2) - 3d56: 0100 addi s0,sp,128 - 3d58: 0200 addi s0,sp,256 - 3d5a: 1104 addi s1,sp,160 - 3d5c: 00090003 lb zero,0(s2) - 3d60: 0100 addi s0,sp,128 - 3d62: 0200 addi s0,sp,256 - 3d64: 1104 addi s1,sp,160 - 3d66: 00090003 lb zero,0(s2) - 3d6a: 0100 addi s0,sp,128 - 3d6c: 0200 addi s0,sp,256 - 3d6e: 1104 addi s1,sp,160 - 3d70: 18090003 lb zero,384(s2) - 3d74: 0100 addi s0,sp,128 - 3d76: 0200 addi s0,sp,256 - 3d78: 1104 addi s1,sp,160 - 3d7a: 10090003 lb zero,256(s2) - 3d7e: 0100 addi s0,sp,128 - 3d80: 0200 addi s0,sp,256 - 3d82: 1104 addi s1,sp,160 - 3d84: 04090003 lb zero,64(s2) - 3d88: 0100 addi s0,sp,128 - 3d8a: 0200 addi s0,sp,256 - 3d8c: 1104 addi s1,sp,160 - 3d8e: 04090003 lb zero,64(s2) - 3d92: 0100 addi s0,sp,128 - 3d94: 0200 addi s0,sp,256 - 3d96: 1104 addi s1,sp,160 - 3d98: 04090003 lb zero,64(s2) - 3d9c: 0100 addi s0,sp,128 - 3d9e: 0200 addi s0,sp,256 - 3da0: 1104 addi s1,sp,160 - 3da2: 04090003 lb zero,64(s2) - 3da6: 0100 addi s0,sp,128 - 3da8: 0200 addi s0,sp,256 - 3daa: 1104 addi s1,sp,160 - 3dac: 04090003 lb zero,64(s2) - 3db0: 0100 addi s0,sp,128 - 3db2: 0200 addi s0,sp,256 - 3db4: 1104 addi s1,sp,160 - 3db6: 00090003 lb zero,0(s2) - 3dba: 0100 addi s0,sp,128 - 3dbc: 0200 addi s0,sp,256 - 3dbe: 1104 addi s1,sp,160 - 3dc0: 00090003 lb zero,0(s2) - 3dc4: 0100 addi s0,sp,128 - 3dc6: 0306 slli t1,t1,0x1 - 3dc8: 0900 addi s0,sp,144 - 3dca: 0004 0x4 - 3dcc: 0001 nop - 3dce: 0402 c.slli64 s0 - 3dd0: 0601 addi a2,a2,0 - 3dd2: 04090003 lb zero,64(s2) - 3dd6: 0100 addi s0,sp,128 - 3dd8: 0200 addi s0,sp,256 - 3dda: 0104 addi s1,sp,128 - 3ddc: 0c090003 lb zero,192(s2) - 3de0: 0100 addi s0,sp,128 - 3de2: 0200 addi s0,sp,256 - 3de4: 0104 addi s1,sp,128 - 3de6: 00090003 lb zero,0(s2) - 3dea: 0100 addi s0,sp,128 - 3dec: 0200 addi s0,sp,256 - 3dee: 0104 addi s1,sp,128 - 3df0: 00090003 lb zero,0(s2) - 3df4: 0100 addi s0,sp,128 - 3df6: 0200 addi s0,sp,256 - 3df8: 0104 addi s1,sp,128 - 3dfa: 00090003 lb zero,0(s2) - 3dfe: 0100 addi s0,sp,128 - 3e00: 0200 addi s0,sp,256 - 3e02: 0104 addi s1,sp,128 - 3e04: 00090003 lb zero,0(s2) - 3e08: 0100 addi s0,sp,128 - 3e0a: 0200 addi s0,sp,256 - 3e0c: 0104 addi s1,sp,128 - 3e0e: 00090003 lb zero,0(s2) - 3e12: 0100 addi s0,sp,128 - 3e14: 0200 addi s0,sp,256 - 3e16: 0104 addi s1,sp,128 - 3e18: 00090003 lb zero,0(s2) - 3e1c: 0100 addi s0,sp,128 - 3e1e: 0200 addi s0,sp,256 - 3e20: 0104 addi s1,sp,128 - 3e22: 00090003 lb zero,0(s2) - 3e26: 0100 addi s0,sp,128 - 3e28: 0200 addi s0,sp,256 - 3e2a: 0104 addi s1,sp,128 - 3e2c: 00090003 lb zero,0(s2) - 3e30: 0100 addi s0,sp,128 - 3e32: 0200 addi s0,sp,256 - 3e34: 0b04 addi s1,sp,400 - 3e36: 08090003 lb zero,128(s2) - 3e3a: 0100 addi s0,sp,128 - 3e3c: 0200 addi s0,sp,256 - 3e3e: 0b04 addi s1,sp,400 - 3e40: 1c090003 lb zero,448(s2) - 3e44: 0100 addi s0,sp,128 - 3e46: 0200 addi s0,sp,256 - 3e48: 0b04 addi s1,sp,400 - 3e4a: 00090003 lb zero,0(s2) - 3e4e: 0100 addi s0,sp,128 - 3e50: 0200 addi s0,sp,256 - 3e52: 0c04 addi s1,sp,528 - 3e54: 04090003 lb zero,64(s2) - 3e58: 0100 addi s0,sp,128 - 3e5a: 0200 addi s0,sp,256 - 3e5c: 0c04 addi s1,sp,528 - 3e5e: 14090003 lb zero,320(s2) - 3e62: 0100 addi s0,sp,128 - 3e64: 0200 addi s0,sp,256 - 3e66: 0c04 addi s1,sp,528 - 3e68: 00090003 lb zero,0(s2) - 3e6c: 0100 addi s0,sp,128 - 3e6e: 0200 addi s0,sp,256 - 3e70: 0c04 addi s1,sp,528 - 3e72: 00090003 lb zero,0(s2) - 3e76: 0100 addi s0,sp,128 - 3e78: 0200 addi s0,sp,256 - 3e7a: 0c04 addi s1,sp,528 - 3e7c: 04090003 lb zero,64(s2) - 3e80: 0100 addi s0,sp,128 - 3e82: 0200 addi s0,sp,256 - 3e84: 0c04 addi s1,sp,528 - 3e86: 00090003 lb zero,0(s2) - 3e8a: 0100 addi s0,sp,128 - 3e8c: 0200 addi s0,sp,256 - 3e8e: 4904 lw s1,16(a0) - 3e90: 00090003 lb zero,0(s2) - 3e94: 0100 addi s0,sp,128 - 3e96: 0200 addi s0,sp,256 - 3e98: 4904 lw s1,16(a0) - 3e9a: 00090003 lb zero,0(s2) - 3e9e: 0100 addi s0,sp,128 - 3ea0: 0200 addi s0,sp,256 - 3ea2: 1104 addi s1,sp,160 - 3ea4: 04090003 lb zero,64(s2) - 3ea8: 0100 addi s0,sp,128 - 3eaa: 0200 addi s0,sp,256 - 3eac: 1104 addi s1,sp,160 - 3eae: 00090003 lb zero,0(s2) - 3eb2: 0100 addi s0,sp,128 - 3eb4: 0200 addi s0,sp,256 - 3eb6: 1104 addi s1,sp,160 - 3eb8: 00090103 lb sp,0(s2) - 3ebc: 0100 addi s0,sp,128 - 3ebe: 0200 addi s0,sp,256 - 3ec0: 1104 addi s1,sp,160 - 3ec2: 00090003 lb zero,0(s2) - 3ec6: 0100 addi s0,sp,128 - 3ec8: 0200 addi s0,sp,256 - 3eca: 1104 addi s1,sp,160 - 3ecc: 20090003 lb zero,512(s2) - 3ed0: 0100 addi s0,sp,128 - 3ed2: 0200 addi s0,sp,256 - 3ed4: 1104 addi s1,sp,160 - 3ed6: 00090003 lb zero,0(s2) - 3eda: 0100 addi s0,sp,128 - 3edc: 0200 addi s0,sp,256 - 3ede: 0204 addi s1,sp,256 - 3ee0: 24097e03 0x24097e03 - 3ee4: 0100 addi s0,sp,128 - 3ee6: 0200 addi s0,sp,256 - 3ee8: 1604 addi s1,sp,800 - 3eea: 10090003 lb zero,256(s2) - 3eee: 0100 addi s0,sp,128 - 3ef0: 0200 addi s0,sp,256 - 3ef2: 1604 addi s1,sp,800 - 3ef4: 00090003 lb zero,0(s2) - 3ef8: 0100 addi s0,sp,128 - 3efa: 0200 addi s0,sp,256 - 3efc: 1604 addi s1,sp,800 - 3efe: 00090003 lb zero,0(s2) - 3f02: 0100 addi s0,sp,128 - 3f04: 0200 addi s0,sp,256 - 3f06: 1604 addi s1,sp,800 - 3f08: 00090003 lb zero,0(s2) - 3f0c: 0100 addi s0,sp,128 - 3f0e: 0200 addi s0,sp,256 - 3f10: 1a04 addi s1,sp,304 - 3f12: 04090003 lb zero,64(s2) - 3f16: 0100 addi s0,sp,128 - 3f18: 0200 addi s0,sp,256 - 3f1a: 1a04 addi s1,sp,304 - 3f1c: 00090003 lb zero,0(s2) - 3f20: 0100 addi s0,sp,128 - 3f22: 0200 addi s0,sp,256 - 3f24: 1a04 addi s1,sp,304 - 3f26: 00090003 lb zero,0(s2) - 3f2a: 0100 addi s0,sp,128 - 3f2c: 0200 addi s0,sp,256 - 3f2e: 1a04 addi s1,sp,304 - 3f30: 00090003 lb zero,0(s2) - 3f34: 0100 addi s0,sp,128 - 3f36: 0200 addi s0,sp,256 - 3f38: 1a04 addi s1,sp,304 - 3f3a: 08090003 lb zero,128(s2) - 3f3e: 0100 addi s0,sp,128 - 3f40: 0200 addi s0,sp,256 - 3f42: 3c04 fld fs1,56(s0) - 3f44: 00090003 lb zero,0(s2) - 3f48: 0100 addi s0,sp,128 - 3f4a: 0200 addi s0,sp,256 - 3f4c: 3c04 fld fs1,56(s0) - 3f4e: 00090003 lb zero,0(s2) - 3f52: 0100 addi s0,sp,128 - 3f54: 0200 addi s0,sp,256 - 3f56: 3c04 fld fs1,56(s0) - 3f58: 00090003 lb zero,0(s2) - 3f5c: 0100 addi s0,sp,128 - 3f5e: 0200 addi s0,sp,256 - 3f60: 3c04 fld fs1,56(s0) - 3f62: 00090003 lb zero,0(s2) - 3f66: 0100 addi s0,sp,128 - 3f68: 0200 addi s0,sp,256 - 3f6a: 3c04 fld fs1,56(s0) - 3f6c: 00090003 lb zero,0(s2) - 3f70: 0100 addi s0,sp,128 - 3f72: 0200 addi s0,sp,256 - 3f74: 3c04 fld fs1,56(s0) - 3f76: 00090003 lb zero,0(s2) - 3f7a: 0100 addi s0,sp,128 - 3f7c: 0200 addi s0,sp,256 - 3f7e: 3c04 fld fs1,56(s0) - 3f80: 08090003 lb zero,128(s2) - 3f84: 0100 addi s0,sp,128 - 3f86: 0200 addi s0,sp,256 - 3f88: 3c04 fld fs1,56(s0) - 3f8a: 00090003 lb zero,0(s2) - 3f8e: 0100 addi s0,sp,128 - 3f90: 0200 addi s0,sp,256 - 3f92: 3c04 fld fs1,56(s0) - 3f94: 00090003 lb zero,0(s2) - 3f98: 0100 addi s0,sp,128 - 3f9a: 0306 slli t1,t1,0x1 - 3f9c: 0900 addi s0,sp,144 - 3f9e: 0014 0x14 - 3fa0: 0001 nop - 3fa2: 0402 c.slli64 s0 - 3fa4: 0642 slli a2,a2,0x10 - 3fa6: 14090003 lb zero,320(s2) + 3c46: 0200 addi s0,sp,256 + 3c48: 0104 addi s1,sp,128 + 3c4a: 00090003 lb zero,0(s2) + 3c4e: 0100 addi s0,sp,128 + 3c50: 0200 addi s0,sp,256 + 3c52: 0104 addi s1,sp,128 + 3c54: 00090003 lb zero,0(s2) + 3c58: 0100 addi s0,sp,128 + 3c5a: 0200 addi s0,sp,256 + 3c5c: 0104 addi s1,sp,128 + 3c5e: 00090003 lb zero,0(s2) + 3c62: 0100 addi s0,sp,128 + 3c64: 0200 addi s0,sp,256 + 3c66: 0104 addi s1,sp,128 + 3c68: 00090003 lb zero,0(s2) + 3c6c: 0100 addi s0,sp,128 + 3c6e: 0200 addi s0,sp,256 + 3c70: 0b04 addi s1,sp,400 + 3c72: 08090003 lb zero,128(s2) + 3c76: 0100 addi s0,sp,128 + 3c78: 0200 addi s0,sp,256 + 3c7a: 0b04 addi s1,sp,400 + 3c7c: 1c090003 lb zero,448(s2) + 3c80: 0100 addi s0,sp,128 + 3c82: 0200 addi s0,sp,256 + 3c84: 0b04 addi s1,sp,400 + 3c86: 00090003 lb zero,0(s2) + 3c8a: 0100 addi s0,sp,128 + 3c8c: 0200 addi s0,sp,256 + 3c8e: 0c04 addi s1,sp,528 + 3c90: 04090003 lb zero,64(s2) + 3c94: 0100 addi s0,sp,128 + 3c96: 0200 addi s0,sp,256 + 3c98: 0c04 addi s1,sp,528 + 3c9a: 14090003 lb zero,320(s2) + 3c9e: 0100 addi s0,sp,128 + 3ca0: 0200 addi s0,sp,256 + 3ca2: 0c04 addi s1,sp,528 + 3ca4: 00090003 lb zero,0(s2) + 3ca8: 0100 addi s0,sp,128 + 3caa: 0200 addi s0,sp,256 + 3cac: 0c04 addi s1,sp,528 + 3cae: 00090003 lb zero,0(s2) + 3cb2: 0100 addi s0,sp,128 + 3cb4: 0200 addi s0,sp,256 + 3cb6: 0c04 addi s1,sp,528 + 3cb8: 04090003 lb zero,64(s2) + 3cbc: 0100 addi s0,sp,128 + 3cbe: 0200 addi s0,sp,256 + 3cc0: 0c04 addi s1,sp,528 + 3cc2: 00090003 lb zero,0(s2) + 3cc6: 0100 addi s0,sp,128 + 3cc8: 0200 addi s0,sp,256 + 3cca: 4904 lw s1,16(a0) + 3ccc: 00090003 lb zero,0(s2) + 3cd0: 0100 addi s0,sp,128 + 3cd2: 0200 addi s0,sp,256 + 3cd4: 4904 lw s1,16(a0) + 3cd6: 00090003 lb zero,0(s2) + 3cda: 0100 addi s0,sp,128 + 3cdc: 0200 addi s0,sp,256 + 3cde: 1104 addi s1,sp,160 + 3ce0: 04090003 lb zero,64(s2) + 3ce4: 0100 addi s0,sp,128 + 3ce6: 0200 addi s0,sp,256 + 3ce8: 1104 addi s1,sp,160 + 3cea: 00090003 lb zero,0(s2) + 3cee: 0100 addi s0,sp,128 + 3cf0: 0200 addi s0,sp,256 + 3cf2: 1104 addi s1,sp,160 + 3cf4: 00090103 lb sp,0(s2) + 3cf8: 0100 addi s0,sp,128 + 3cfa: 0200 addi s0,sp,256 + 3cfc: 1104 addi s1,sp,160 + 3cfe: 00090003 lb zero,0(s2) + 3d02: 0100 addi s0,sp,128 + 3d04: 0200 addi s0,sp,256 + 3d06: 1104 addi s1,sp,160 + 3d08: 00090003 lb zero,0(s2) + 3d0c: 0100 addi s0,sp,128 + 3d0e: 0200 addi s0,sp,256 + 3d10: 1104 addi s1,sp,160 + 3d12: 00090003 lb zero,0(s2) + 3d16: 0100 addi s0,sp,128 + 3d18: 0200 addi s0,sp,256 + 3d1a: 1104 addi s1,sp,160 + 3d1c: 18090003 lb zero,384(s2) + 3d20: 0100 addi s0,sp,128 + 3d22: 0200 addi s0,sp,256 + 3d24: 1104 addi s1,sp,160 + 3d26: 10090003 lb zero,256(s2) + 3d2a: 0100 addi s0,sp,128 + 3d2c: 0200 addi s0,sp,256 + 3d2e: 1104 addi s1,sp,160 + 3d30: 04090003 lb zero,64(s2) + 3d34: 0100 addi s0,sp,128 + 3d36: 0200 addi s0,sp,256 + 3d38: 1104 addi s1,sp,160 + 3d3a: 04090003 lb zero,64(s2) + 3d3e: 0100 addi s0,sp,128 + 3d40: 0200 addi s0,sp,256 + 3d42: 1104 addi s1,sp,160 + 3d44: 04090003 lb zero,64(s2) + 3d48: 0100 addi s0,sp,128 + 3d4a: 0200 addi s0,sp,256 + 3d4c: 1104 addi s1,sp,160 + 3d4e: 04090003 lb zero,64(s2) + 3d52: 0100 addi s0,sp,128 + 3d54: 0200 addi s0,sp,256 + 3d56: 1104 addi s1,sp,160 + 3d58: 04090003 lb zero,64(s2) + 3d5c: 0100 addi s0,sp,128 + 3d5e: 0200 addi s0,sp,256 + 3d60: 1104 addi s1,sp,160 + 3d62: 00090003 lb zero,0(s2) + 3d66: 0100 addi s0,sp,128 + 3d68: 0200 addi s0,sp,256 + 3d6a: 1104 addi s1,sp,160 + 3d6c: 00090003 lb zero,0(s2) + 3d70: 0100 addi s0,sp,128 + 3d72: 0306 slli t1,t1,0x1 + 3d74: 0900 addi s0,sp,144 + 3d76: 0004 0x4 + 3d78: 0001 nop + 3d7a: 0402 c.slli64 s0 + 3d7c: 0601 addi a2,a2,0 + 3d7e: 04090003 lb zero,64(s2) + 3d82: 0100 addi s0,sp,128 + 3d84: 0200 addi s0,sp,256 + 3d86: 0104 addi s1,sp,128 + 3d88: 0c090003 lb zero,192(s2) + 3d8c: 0100 addi s0,sp,128 + 3d8e: 0200 addi s0,sp,256 + 3d90: 0104 addi s1,sp,128 + 3d92: 00090003 lb zero,0(s2) + 3d96: 0100 addi s0,sp,128 + 3d98: 0200 addi s0,sp,256 + 3d9a: 0104 addi s1,sp,128 + 3d9c: 00090003 lb zero,0(s2) + 3da0: 0100 addi s0,sp,128 + 3da2: 0200 addi s0,sp,256 + 3da4: 0104 addi s1,sp,128 + 3da6: 00090003 lb zero,0(s2) + 3daa: 0100 addi s0,sp,128 + 3dac: 0200 addi s0,sp,256 + 3dae: 0104 addi s1,sp,128 + 3db0: 00090003 lb zero,0(s2) + 3db4: 0100 addi s0,sp,128 + 3db6: 0200 addi s0,sp,256 + 3db8: 0104 addi s1,sp,128 + 3dba: 00090003 lb zero,0(s2) + 3dbe: 0100 addi s0,sp,128 + 3dc0: 0200 addi s0,sp,256 + 3dc2: 0104 addi s1,sp,128 + 3dc4: 00090003 lb zero,0(s2) + 3dc8: 0100 addi s0,sp,128 + 3dca: 0200 addi s0,sp,256 + 3dcc: 0104 addi s1,sp,128 + 3dce: 00090003 lb zero,0(s2) + 3dd2: 0100 addi s0,sp,128 + 3dd4: 0200 addi s0,sp,256 + 3dd6: 0104 addi s1,sp,128 + 3dd8: 00090003 lb zero,0(s2) + 3ddc: 0100 addi s0,sp,128 + 3dde: 0200 addi s0,sp,256 + 3de0: 0b04 addi s1,sp,400 + 3de2: 08090003 lb zero,128(s2) + 3de6: 0100 addi s0,sp,128 + 3de8: 0200 addi s0,sp,256 + 3dea: 0b04 addi s1,sp,400 + 3dec: 1c090003 lb zero,448(s2) + 3df0: 0100 addi s0,sp,128 + 3df2: 0200 addi s0,sp,256 + 3df4: 0b04 addi s1,sp,400 + 3df6: 00090003 lb zero,0(s2) + 3dfa: 0100 addi s0,sp,128 + 3dfc: 0200 addi s0,sp,256 + 3dfe: 0c04 addi s1,sp,528 + 3e00: 04090003 lb zero,64(s2) + 3e04: 0100 addi s0,sp,128 + 3e06: 0200 addi s0,sp,256 + 3e08: 0c04 addi s1,sp,528 + 3e0a: 14090003 lb zero,320(s2) + 3e0e: 0100 addi s0,sp,128 + 3e10: 0200 addi s0,sp,256 + 3e12: 0c04 addi s1,sp,528 + 3e14: 00090003 lb zero,0(s2) + 3e18: 0100 addi s0,sp,128 + 3e1a: 0200 addi s0,sp,256 + 3e1c: 0c04 addi s1,sp,528 + 3e1e: 00090003 lb zero,0(s2) + 3e22: 0100 addi s0,sp,128 + 3e24: 0200 addi s0,sp,256 + 3e26: 0c04 addi s1,sp,528 + 3e28: 04090003 lb zero,64(s2) + 3e2c: 0100 addi s0,sp,128 + 3e2e: 0200 addi s0,sp,256 + 3e30: 0c04 addi s1,sp,528 + 3e32: 00090003 lb zero,0(s2) + 3e36: 0100 addi s0,sp,128 + 3e38: 0200 addi s0,sp,256 + 3e3a: 4904 lw s1,16(a0) + 3e3c: 00090003 lb zero,0(s2) + 3e40: 0100 addi s0,sp,128 + 3e42: 0200 addi s0,sp,256 + 3e44: 4904 lw s1,16(a0) + 3e46: 00090003 lb zero,0(s2) + 3e4a: 0100 addi s0,sp,128 + 3e4c: 0200 addi s0,sp,256 + 3e4e: 1104 addi s1,sp,160 + 3e50: 04090003 lb zero,64(s2) + 3e54: 0100 addi s0,sp,128 + 3e56: 0200 addi s0,sp,256 + 3e58: 1104 addi s1,sp,160 + 3e5a: 00090003 lb zero,0(s2) + 3e5e: 0100 addi s0,sp,128 + 3e60: 0200 addi s0,sp,256 + 3e62: 1104 addi s1,sp,160 + 3e64: 00090103 lb sp,0(s2) + 3e68: 0100 addi s0,sp,128 + 3e6a: 0200 addi s0,sp,256 + 3e6c: 1104 addi s1,sp,160 + 3e6e: 00090003 lb zero,0(s2) + 3e72: 0100 addi s0,sp,128 + 3e74: 0200 addi s0,sp,256 + 3e76: 1104 addi s1,sp,160 + 3e78: 20090003 lb zero,512(s2) + 3e7c: 0100 addi s0,sp,128 + 3e7e: 0200 addi s0,sp,256 + 3e80: 1104 addi s1,sp,160 + 3e82: 00090003 lb zero,0(s2) + 3e86: 0100 addi s0,sp,128 + 3e88: 0200 addi s0,sp,256 + 3e8a: 0204 addi s1,sp,256 + 3e8c: 24097e03 0x24097e03 + 3e90: 0100 addi s0,sp,128 + 3e92: 0200 addi s0,sp,256 + 3e94: 1604 addi s1,sp,800 + 3e96: 10090003 lb zero,256(s2) + 3e9a: 0100 addi s0,sp,128 + 3e9c: 0200 addi s0,sp,256 + 3e9e: 1604 addi s1,sp,800 + 3ea0: 00090003 lb zero,0(s2) + 3ea4: 0100 addi s0,sp,128 + 3ea6: 0200 addi s0,sp,256 + 3ea8: 1604 addi s1,sp,800 + 3eaa: 00090003 lb zero,0(s2) + 3eae: 0100 addi s0,sp,128 + 3eb0: 0200 addi s0,sp,256 + 3eb2: 1604 addi s1,sp,800 + 3eb4: 00090003 lb zero,0(s2) + 3eb8: 0100 addi s0,sp,128 + 3eba: 0200 addi s0,sp,256 + 3ebc: 1a04 addi s1,sp,304 + 3ebe: 04090003 lb zero,64(s2) + 3ec2: 0100 addi s0,sp,128 + 3ec4: 0200 addi s0,sp,256 + 3ec6: 1a04 addi s1,sp,304 + 3ec8: 00090003 lb zero,0(s2) + 3ecc: 0100 addi s0,sp,128 + 3ece: 0200 addi s0,sp,256 + 3ed0: 1a04 addi s1,sp,304 + 3ed2: 00090003 lb zero,0(s2) + 3ed6: 0100 addi s0,sp,128 + 3ed8: 0200 addi s0,sp,256 + 3eda: 1a04 addi s1,sp,304 + 3edc: 00090003 lb zero,0(s2) + 3ee0: 0100 addi s0,sp,128 + 3ee2: 0200 addi s0,sp,256 + 3ee4: 1a04 addi s1,sp,304 + 3ee6: 08090003 lb zero,128(s2) + 3eea: 0100 addi s0,sp,128 + 3eec: 0200 addi s0,sp,256 + 3eee: 3c04 fld fs1,56(s0) + 3ef0: 00090003 lb zero,0(s2) + 3ef4: 0100 addi s0,sp,128 + 3ef6: 0200 addi s0,sp,256 + 3ef8: 3c04 fld fs1,56(s0) + 3efa: 00090003 lb zero,0(s2) + 3efe: 0100 addi s0,sp,128 + 3f00: 0200 addi s0,sp,256 + 3f02: 3c04 fld fs1,56(s0) + 3f04: 00090003 lb zero,0(s2) + 3f08: 0100 addi s0,sp,128 + 3f0a: 0200 addi s0,sp,256 + 3f0c: 3c04 fld fs1,56(s0) + 3f0e: 00090003 lb zero,0(s2) + 3f12: 0100 addi s0,sp,128 + 3f14: 0200 addi s0,sp,256 + 3f16: 3c04 fld fs1,56(s0) + 3f18: 00090003 lb zero,0(s2) + 3f1c: 0100 addi s0,sp,128 + 3f1e: 0200 addi s0,sp,256 + 3f20: 3c04 fld fs1,56(s0) + 3f22: 00090003 lb zero,0(s2) + 3f26: 0100 addi s0,sp,128 + 3f28: 0200 addi s0,sp,256 + 3f2a: 3c04 fld fs1,56(s0) + 3f2c: 08090003 lb zero,128(s2) + 3f30: 0100 addi s0,sp,128 + 3f32: 0200 addi s0,sp,256 + 3f34: 3c04 fld fs1,56(s0) + 3f36: 00090003 lb zero,0(s2) + 3f3a: 0100 addi s0,sp,128 + 3f3c: 0200 addi s0,sp,256 + 3f3e: 3c04 fld fs1,56(s0) + 3f40: 00090003 lb zero,0(s2) + 3f44: 0100 addi s0,sp,128 + 3f46: 0306 slli t1,t1,0x1 + 3f48: 0900 addi s0,sp,144 + 3f4a: 0014 0x14 + 3f4c: 0001 nop + 3f4e: 0402 c.slli64 s0 + 3f50: 0642 slli a2,a2,0x10 + 3f52: 14090003 lb zero,320(s2) + 3f56: 0100 addi s0,sp,128 + 3f58: 0200 addi s0,sp,256 + 3f5a: 4504 lw s1,8(a0) + 3f5c: 0306 slli t1,t1,0x1 + 3f5e: 0900 addi s0,sp,144 + 3f60: 0004 0x4 + 3f62: 0001 nop + 3f64: 0402 c.slli64 s0 + 3f66: 0645 addi a2,a2,17 + 3f68: 10090003 lb zero,256(s2) + 3f6c: 0100 addi s0,sp,128 + 3f6e: 0200 addi s0,sp,256 + 3f70: 4704 lw s1,8(a4) + 3f72: 0306 slli t1,t1,0x1 + 3f74: 0900 addi s0,sp,144 + 3f76: 0008 0x8 + 3f78: 0001 nop + 3f7a: 0402 c.slli64 s0 + 3f7c: 0619 addi a2,a2,6 + 3f7e: 08090003 lb zero,128(s2) + 3f82: 0100 addi s0,sp,128 + 3f84: 0200 addi s0,sp,256 + 3f86: 2304 fld fs1,0(a4) + 3f88: 04090003 lb zero,64(s2) + 3f8c: 0100 addi s0,sp,128 + 3f8e: 0200 addi s0,sp,256 + 3f90: 2304 fld fs1,0(a4) + 3f92: 00090003 lb zero,0(s2) + 3f96: 0100 addi s0,sp,128 + 3f98: 0200 addi s0,sp,256 + 3f9a: 2304 fld fs1,0(a4) + 3f9c: 00090003 lb zero,0(s2) + 3fa0: 0100 addi s0,sp,128 + 3fa2: 0200 addi s0,sp,256 + 3fa4: 2304 fld fs1,0(a4) + 3fa6: 00090003 lb zero,0(s2) 3faa: 0100 addi s0,sp,128 3fac: 0200 addi s0,sp,256 - 3fae: 4504 lw s1,8(a0) - 3fb0: 0306 slli t1,t1,0x1 - 3fb2: 0900 addi s0,sp,144 - 3fb4: 0004 0x4 - 3fb6: 0001 nop - 3fb8: 0402 c.slli64 s0 - 3fba: 0645 addi a2,a2,17 - 3fbc: 10090003 lb zero,256(s2) - 3fc0: 0100 addi s0,sp,128 - 3fc2: 0200 addi s0,sp,256 - 3fc4: 4704 lw s1,8(a4) - 3fc6: 0306 slli t1,t1,0x1 - 3fc8: 0900 addi s0,sp,144 - 3fca: 0008 0x8 - 3fcc: 0001 nop - 3fce: 0402 c.slli64 s0 - 3fd0: 0619 addi a2,a2,6 - 3fd2: 08090003 lb zero,128(s2) - 3fd6: 0100 addi s0,sp,128 - 3fd8: 0200 addi s0,sp,256 - 3fda: 2304 fld fs1,0(a4) - 3fdc: 04090003 lb zero,64(s2) - 3fe0: 0100 addi s0,sp,128 - 3fe2: 0200 addi s0,sp,256 - 3fe4: 2304 fld fs1,0(a4) - 3fe6: 00090003 lb zero,0(s2) - 3fea: 0100 addi s0,sp,128 - 3fec: 0200 addi s0,sp,256 - 3fee: 2304 fld fs1,0(a4) - 3ff0: 00090003 lb zero,0(s2) - 3ff4: 0100 addi s0,sp,128 - 3ff6: 0200 addi s0,sp,256 - 3ff8: 2304 fld fs1,0(a4) - 3ffa: 00090003 lb zero,0(s2) - 3ffe: 0100 addi s0,sp,128 - 4000: 0200 addi s0,sp,256 - 4002: 2304 fld fs1,0(a4) - 4004: 04090003 lb zero,64(s2) - 4008: 0100 addi s0,sp,128 - 400a: 0200 addi s0,sp,256 - 400c: 2304 fld fs1,0(a4) - 400e: 00090003 lb zero,0(s2) - 4012: 0100 addi s0,sp,128 - 4014: 0200 addi s0,sp,256 - 4016: 2204 fld fs1,0(a2) - 4018: 08090003 lb zero,128(s2) - 401c: 0100 addi s0,sp,128 - 401e: 0200 addi s0,sp,256 - 4020: 2d04 fld fs1,24(a0) - 4022: 04090003 lb zero,64(s2) - 4026: 0100 addi s0,sp,128 - 4028: 0200 addi s0,sp,256 - 402a: 2d04 fld fs1,24(a0) - 402c: 00090003 lb zero,0(s2) - 4030: 0100 addi s0,sp,128 - 4032: 0200 addi s0,sp,256 - 4034: 2d04 fld fs1,24(a0) - 4036: 00090003 lb zero,0(s2) - 403a: 0100 addi s0,sp,128 - 403c: 0200 addi s0,sp,256 - 403e: 2d04 fld fs1,24(a0) - 4040: 00090003 lb zero,0(s2) - 4044: 0100 addi s0,sp,128 - 4046: 0200 addi s0,sp,256 - 4048: 2d04 fld fs1,24(a0) - 404a: 08090003 lb zero,128(s2) - 404e: 0100 addi s0,sp,128 - 4050: 0200 addi s0,sp,256 - 4052: 2d04 fld fs1,24(a0) - 4054: 00090003 lb zero,0(s2) - 4058: 0100 addi s0,sp,128 - 405a: 0200 addi s0,sp,256 - 405c: 3504 fld fs1,40(a0) - 405e: 08090003 lb zero,128(s2) - 4062: 0100 addi s0,sp,128 - 4064: 0200 addi s0,sp,256 - 4066: 3504 fld fs1,40(a0) - 4068: 00090003 lb zero,0(s2) - 406c: 0100 addi s0,sp,128 - 406e: 0200 addi s0,sp,256 - 4070: 3504 fld fs1,40(a0) - 4072: 00090003 lb zero,0(s2) - 4076: 0100 addi s0,sp,128 - 4078: 0200 addi s0,sp,256 - 407a: 3504 fld fs1,40(a0) - 407c: 00090003 lb zero,0(s2) - 4080: 0100 addi s0,sp,128 - 4082: 0200 addi s0,sp,256 - 4084: 3504 fld fs1,40(a0) - 4086: 08090003 lb zero,128(s2) - 408a: 0100 addi s0,sp,128 - 408c: 0200 addi s0,sp,256 - 408e: 3504 fld fs1,40(a0) - 4090: 00090003 lb zero,0(s2) - 4094: 0100 addi s0,sp,128 - 4096: 0306 slli t1,t1,0x1 - 4098: 0900 addi s0,sp,144 - 409a: 0014 0x14 - 409c: 0001 nop - 409e: 0402 c.slli64 s0 - 40a0: 0641 addi a2,a2,16 - 40a2: 04090003 lb zero,64(s2) - 40a6: 0100 addi s0,sp,128 - 40a8: 0200 addi s0,sp,256 - 40aa: 4104 lw s1,0(a0) - 40ac: 14090003 lb zero,320(s2) - 40b0: 0100 addi s0,sp,128 - 40b2: 0200 addi s0,sp,256 - 40b4: 4104 lw s1,0(a0) - 40b6: 00090003 lb zero,0(s2) - 40ba: 0100 addi s0,sp,128 - 40bc: 0200 addi s0,sp,256 - 40be: 4404 lw s1,8(s0) - 40c0: 0c090003 lb zero,192(s2) - 40c4: 0100 addi s0,sp,128 - 40c6: 0200 addi s0,sp,256 - 40c8: 4404 lw s1,8(s0) - 40ca: 1c090003 lb zero,448(s2) - 40ce: 0100 addi s0,sp,128 - 40d0: 0200 addi s0,sp,256 - 40d2: 4804 lw s1,16(s0) - 40d4: 08090003 lb zero,128(s2) - 40d8: 0100 addi s0,sp,128 - 40da: 0200 addi s0,sp,256 - 40dc: 4804 lw s1,16(s0) - 40de: 10090003 lb zero,256(s2) - 40e2: 0100 addi s0,sp,128 - 40e4: 0200 addi s0,sp,256 - 40e6: 4704 lw s1,8(a4) - 40e8: 04090003 lb zero,64(s2) - 40ec: 0100 addi s0,sp,128 - 40ee: 0200 addi s0,sp,256 - 40f0: 4904 lw s1,16(a0) - 40f2: 04090003 lb zero,64(s2) - 40f6: 0100 addi s0,sp,128 - 40f8: 0200 addi s0,sp,256 - 40fa: 4904 lw s1,16(a0) - 40fc: 00090003 lb zero,0(s2) - 4100: 0100 addi s0,sp,128 - 4102: 0200 addi s0,sp,256 - 4104: 0304 addi s1,sp,384 - 4106: 10090003 lb zero,256(s2) - 410a: 0100 addi s0,sp,128 - 410c: 0306 slli t1,t1,0x1 - 410e: 0900 addi s0,sp,144 - 4110: 0014 0x14 - 4112: 0001 nop - 4114: 0402 c.slli64 s0 - 4116: 0602 c.slli64 a2 - 4118: 14090103 lb sp,320(s2) - 411c: 0100 addi s0,sp,128 - 411e: 0200 addi s0,sp,256 - 4120: 1604 addi s1,sp,800 - 4122: 10090003 lb zero,256(s2) - 4126: 0100 addi s0,sp,128 - 4128: 0200 addi s0,sp,256 - 412a: 1604 addi s1,sp,800 - 412c: 00090003 lb zero,0(s2) - 4130: 0100 addi s0,sp,128 - 4132: 0200 addi s0,sp,256 - 4134: 1604 addi s1,sp,800 - 4136: 00090003 lb zero,0(s2) - 413a: 0100 addi s0,sp,128 - 413c: 0200 addi s0,sp,256 - 413e: 1604 addi s1,sp,800 - 4140: 00090003 lb zero,0(s2) - 4144: 0100 addi s0,sp,128 - 4146: 0200 addi s0,sp,256 - 4148: 1a04 addi s1,sp,304 - 414a: 04090003 lb zero,64(s2) - 414e: 0100 addi s0,sp,128 - 4150: 0200 addi s0,sp,256 - 4152: 1a04 addi s1,sp,304 - 4154: 00090003 lb zero,0(s2) - 4158: 0100 addi s0,sp,128 - 415a: 0200 addi s0,sp,256 - 415c: 1a04 addi s1,sp,304 - 415e: 00090003 lb zero,0(s2) - 4162: 0100 addi s0,sp,128 - 4164: 0200 addi s0,sp,256 - 4166: 1a04 addi s1,sp,304 - 4168: 00090003 lb zero,0(s2) - 416c: 0100 addi s0,sp,128 - 416e: 0200 addi s0,sp,256 - 4170: 1a04 addi s1,sp,304 - 4172: 04090003 lb zero,64(s2) - 4176: 0100 addi s0,sp,128 - 4178: 0200 addi s0,sp,256 - 417a: 3c04 fld fs1,56(s0) - 417c: 00090003 lb zero,0(s2) - 4180: 0100 addi s0,sp,128 - 4182: 0200 addi s0,sp,256 - 4184: 3c04 fld fs1,56(s0) - 4186: 00090003 lb zero,0(s2) - 418a: 0100 addi s0,sp,128 - 418c: 0200 addi s0,sp,256 - 418e: 3c04 fld fs1,56(s0) - 4190: 00090003 lb zero,0(s2) - 4194: 0100 addi s0,sp,128 - 4196: 0200 addi s0,sp,256 - 4198: 3c04 fld fs1,56(s0) - 419a: 00090003 lb zero,0(s2) - 419e: 0100 addi s0,sp,128 - 41a0: 0200 addi s0,sp,256 - 41a2: 3c04 fld fs1,56(s0) - 41a4: 00090003 lb zero,0(s2) - 41a8: 0100 addi s0,sp,128 - 41aa: 0200 addi s0,sp,256 - 41ac: 3c04 fld fs1,56(s0) - 41ae: 00090003 lb zero,0(s2) - 41b2: 0100 addi s0,sp,128 - 41b4: 0200 addi s0,sp,256 - 41b6: 3c04 fld fs1,56(s0) - 41b8: 08090003 lb zero,128(s2) - 41bc: 0100 addi s0,sp,128 - 41be: 0200 addi s0,sp,256 - 41c0: 3c04 fld fs1,56(s0) - 41c2: 00090003 lb zero,0(s2) - 41c6: 0100 addi s0,sp,128 - 41c8: 0200 addi s0,sp,256 - 41ca: 3c04 fld fs1,56(s0) - 41cc: 00090003 lb zero,0(s2) - 41d0: 0100 addi s0,sp,128 - 41d2: 0306 slli t1,t1,0x1 - 41d4: 0900 addi s0,sp,144 - 41d6: 0014 0x14 - 41d8: 0001 nop - 41da: 0402 c.slli64 s0 - 41dc: 0642 slli a2,a2,0x10 - 41de: 14090003 lb zero,320(s2) + 3fae: 2304 fld fs1,0(a4) + 3fb0: 04090003 lb zero,64(s2) + 3fb4: 0100 addi s0,sp,128 + 3fb6: 0200 addi s0,sp,256 + 3fb8: 2304 fld fs1,0(a4) + 3fba: 00090003 lb zero,0(s2) + 3fbe: 0100 addi s0,sp,128 + 3fc0: 0200 addi s0,sp,256 + 3fc2: 2204 fld fs1,0(a2) + 3fc4: 08090003 lb zero,128(s2) + 3fc8: 0100 addi s0,sp,128 + 3fca: 0200 addi s0,sp,256 + 3fcc: 2d04 fld fs1,24(a0) + 3fce: 04090003 lb zero,64(s2) + 3fd2: 0100 addi s0,sp,128 + 3fd4: 0200 addi s0,sp,256 + 3fd6: 2d04 fld fs1,24(a0) + 3fd8: 00090003 lb zero,0(s2) + 3fdc: 0100 addi s0,sp,128 + 3fde: 0200 addi s0,sp,256 + 3fe0: 2d04 fld fs1,24(a0) + 3fe2: 00090003 lb zero,0(s2) + 3fe6: 0100 addi s0,sp,128 + 3fe8: 0200 addi s0,sp,256 + 3fea: 2d04 fld fs1,24(a0) + 3fec: 00090003 lb zero,0(s2) + 3ff0: 0100 addi s0,sp,128 + 3ff2: 0200 addi s0,sp,256 + 3ff4: 2d04 fld fs1,24(a0) + 3ff6: 08090003 lb zero,128(s2) + 3ffa: 0100 addi s0,sp,128 + 3ffc: 0200 addi s0,sp,256 + 3ffe: 2d04 fld fs1,24(a0) + 4000: 00090003 lb zero,0(s2) + 4004: 0100 addi s0,sp,128 + 4006: 0200 addi s0,sp,256 + 4008: 3504 fld fs1,40(a0) + 400a: 08090003 lb zero,128(s2) + 400e: 0100 addi s0,sp,128 + 4010: 0200 addi s0,sp,256 + 4012: 3504 fld fs1,40(a0) + 4014: 00090003 lb zero,0(s2) + 4018: 0100 addi s0,sp,128 + 401a: 0200 addi s0,sp,256 + 401c: 3504 fld fs1,40(a0) + 401e: 00090003 lb zero,0(s2) + 4022: 0100 addi s0,sp,128 + 4024: 0200 addi s0,sp,256 + 4026: 3504 fld fs1,40(a0) + 4028: 00090003 lb zero,0(s2) + 402c: 0100 addi s0,sp,128 + 402e: 0200 addi s0,sp,256 + 4030: 3504 fld fs1,40(a0) + 4032: 08090003 lb zero,128(s2) + 4036: 0100 addi s0,sp,128 + 4038: 0200 addi s0,sp,256 + 403a: 3504 fld fs1,40(a0) + 403c: 00090003 lb zero,0(s2) + 4040: 0100 addi s0,sp,128 + 4042: 0306 slli t1,t1,0x1 + 4044: 0900 addi s0,sp,144 + 4046: 0014 0x14 + 4048: 0001 nop + 404a: 0402 c.slli64 s0 + 404c: 0641 addi a2,a2,16 + 404e: 04090003 lb zero,64(s2) + 4052: 0100 addi s0,sp,128 + 4054: 0200 addi s0,sp,256 + 4056: 4104 lw s1,0(a0) + 4058: 14090003 lb zero,320(s2) + 405c: 0100 addi s0,sp,128 + 405e: 0200 addi s0,sp,256 + 4060: 4104 lw s1,0(a0) + 4062: 00090003 lb zero,0(s2) + 4066: 0100 addi s0,sp,128 + 4068: 0200 addi s0,sp,256 + 406a: 4404 lw s1,8(s0) + 406c: 0c090003 lb zero,192(s2) + 4070: 0100 addi s0,sp,128 + 4072: 0200 addi s0,sp,256 + 4074: 4404 lw s1,8(s0) + 4076: 1c090003 lb zero,448(s2) + 407a: 0100 addi s0,sp,128 + 407c: 0200 addi s0,sp,256 + 407e: 4804 lw s1,16(s0) + 4080: 08090003 lb zero,128(s2) + 4084: 0100 addi s0,sp,128 + 4086: 0200 addi s0,sp,256 + 4088: 4804 lw s1,16(s0) + 408a: 10090003 lb zero,256(s2) + 408e: 0100 addi s0,sp,128 + 4090: 0200 addi s0,sp,256 + 4092: 4704 lw s1,8(a4) + 4094: 04090003 lb zero,64(s2) + 4098: 0100 addi s0,sp,128 + 409a: 0200 addi s0,sp,256 + 409c: 4904 lw s1,16(a0) + 409e: 04090003 lb zero,64(s2) + 40a2: 0100 addi s0,sp,128 + 40a4: 0200 addi s0,sp,256 + 40a6: 4904 lw s1,16(a0) + 40a8: 00090003 lb zero,0(s2) + 40ac: 0100 addi s0,sp,128 + 40ae: 0200 addi s0,sp,256 + 40b0: 0304 addi s1,sp,384 + 40b2: 10090003 lb zero,256(s2) + 40b6: 0100 addi s0,sp,128 + 40b8: 0306 slli t1,t1,0x1 + 40ba: 0900 addi s0,sp,144 + 40bc: 0014 0x14 + 40be: 0001 nop + 40c0: 0402 c.slli64 s0 + 40c2: 0602 c.slli64 a2 + 40c4: 14090103 lb sp,320(s2) + 40c8: 0100 addi s0,sp,128 + 40ca: 0200 addi s0,sp,256 + 40cc: 1604 addi s1,sp,800 + 40ce: 10090003 lb zero,256(s2) + 40d2: 0100 addi s0,sp,128 + 40d4: 0200 addi s0,sp,256 + 40d6: 1604 addi s1,sp,800 + 40d8: 00090003 lb zero,0(s2) + 40dc: 0100 addi s0,sp,128 + 40de: 0200 addi s0,sp,256 + 40e0: 1604 addi s1,sp,800 + 40e2: 00090003 lb zero,0(s2) + 40e6: 0100 addi s0,sp,128 + 40e8: 0200 addi s0,sp,256 + 40ea: 1604 addi s1,sp,800 + 40ec: 00090003 lb zero,0(s2) + 40f0: 0100 addi s0,sp,128 + 40f2: 0200 addi s0,sp,256 + 40f4: 1a04 addi s1,sp,304 + 40f6: 04090003 lb zero,64(s2) + 40fa: 0100 addi s0,sp,128 + 40fc: 0200 addi s0,sp,256 + 40fe: 1a04 addi s1,sp,304 + 4100: 00090003 lb zero,0(s2) + 4104: 0100 addi s0,sp,128 + 4106: 0200 addi s0,sp,256 + 4108: 1a04 addi s1,sp,304 + 410a: 00090003 lb zero,0(s2) + 410e: 0100 addi s0,sp,128 + 4110: 0200 addi s0,sp,256 + 4112: 1a04 addi s1,sp,304 + 4114: 00090003 lb zero,0(s2) + 4118: 0100 addi s0,sp,128 + 411a: 0200 addi s0,sp,256 + 411c: 1a04 addi s1,sp,304 + 411e: 04090003 lb zero,64(s2) + 4122: 0100 addi s0,sp,128 + 4124: 0200 addi s0,sp,256 + 4126: 3c04 fld fs1,56(s0) + 4128: 00090003 lb zero,0(s2) + 412c: 0100 addi s0,sp,128 + 412e: 0200 addi s0,sp,256 + 4130: 3c04 fld fs1,56(s0) + 4132: 00090003 lb zero,0(s2) + 4136: 0100 addi s0,sp,128 + 4138: 0200 addi s0,sp,256 + 413a: 3c04 fld fs1,56(s0) + 413c: 00090003 lb zero,0(s2) + 4140: 0100 addi s0,sp,128 + 4142: 0200 addi s0,sp,256 + 4144: 3c04 fld fs1,56(s0) + 4146: 00090003 lb zero,0(s2) + 414a: 0100 addi s0,sp,128 + 414c: 0200 addi s0,sp,256 + 414e: 3c04 fld fs1,56(s0) + 4150: 00090003 lb zero,0(s2) + 4154: 0100 addi s0,sp,128 + 4156: 0200 addi s0,sp,256 + 4158: 3c04 fld fs1,56(s0) + 415a: 00090003 lb zero,0(s2) + 415e: 0100 addi s0,sp,128 + 4160: 0200 addi s0,sp,256 + 4162: 3c04 fld fs1,56(s0) + 4164: 08090003 lb zero,128(s2) + 4168: 0100 addi s0,sp,128 + 416a: 0200 addi s0,sp,256 + 416c: 3c04 fld fs1,56(s0) + 416e: 00090003 lb zero,0(s2) + 4172: 0100 addi s0,sp,128 + 4174: 0200 addi s0,sp,256 + 4176: 3c04 fld fs1,56(s0) + 4178: 00090003 lb zero,0(s2) + 417c: 0100 addi s0,sp,128 + 417e: 0306 slli t1,t1,0x1 + 4180: 0900 addi s0,sp,144 + 4182: 0014 0x14 + 4184: 0001 nop + 4186: 0402 c.slli64 s0 + 4188: 0642 slli a2,a2,0x10 + 418a: 14090003 lb zero,320(s2) + 418e: 0100 addi s0,sp,128 + 4190: 0200 addi s0,sp,256 + 4192: 4504 lw s1,8(a0) + 4194: 0306 slli t1,t1,0x1 + 4196: 0900 addi s0,sp,144 + 4198: 0004 0x4 + 419a: 0001 nop + 419c: 0402 c.slli64 s0 + 419e: 0645 addi a2,a2,17 + 41a0: 10090003 lb zero,256(s2) + 41a4: 0100 addi s0,sp,128 + 41a6: 0200 addi s0,sp,256 + 41a8: 4704 lw s1,8(a4) + 41aa: 0306 slli t1,t1,0x1 + 41ac: 0900 addi s0,sp,144 + 41ae: 0008 0x8 + 41b0: 0001 nop + 41b2: 0402 c.slli64 s0 + 41b4: 0619 addi a2,a2,6 + 41b6: 08090003 lb zero,128(s2) + 41ba: 0100 addi s0,sp,128 + 41bc: 0200 addi s0,sp,256 + 41be: 2304 fld fs1,0(a4) + 41c0: 04090003 lb zero,64(s2) + 41c4: 0100 addi s0,sp,128 + 41c6: 0200 addi s0,sp,256 + 41c8: 2304 fld fs1,0(a4) + 41ca: 00090003 lb zero,0(s2) + 41ce: 0100 addi s0,sp,128 + 41d0: 0200 addi s0,sp,256 + 41d2: 2304 fld fs1,0(a4) + 41d4: 00090003 lb zero,0(s2) + 41d8: 0100 addi s0,sp,128 + 41da: 0200 addi s0,sp,256 + 41dc: 2304 fld fs1,0(a4) + 41de: 00090003 lb zero,0(s2) 41e2: 0100 addi s0,sp,128 41e4: 0200 addi s0,sp,256 - 41e6: 4504 lw s1,8(a0) - 41e8: 0306 slli t1,t1,0x1 - 41ea: 0900 addi s0,sp,144 - 41ec: 0004 0x4 - 41ee: 0001 nop - 41f0: 0402 c.slli64 s0 - 41f2: 0645 addi a2,a2,17 - 41f4: 10090003 lb zero,256(s2) - 41f8: 0100 addi s0,sp,128 - 41fa: 0200 addi s0,sp,256 - 41fc: 4704 lw s1,8(a4) - 41fe: 0306 slli t1,t1,0x1 - 4200: 0900 addi s0,sp,144 - 4202: 0008 0x8 - 4204: 0001 nop - 4206: 0402 c.slli64 s0 - 4208: 0619 addi a2,a2,6 - 420a: 08090003 lb zero,128(s2) - 420e: 0100 addi s0,sp,128 - 4210: 0200 addi s0,sp,256 - 4212: 2304 fld fs1,0(a4) - 4214: 04090003 lb zero,64(s2) - 4218: 0100 addi s0,sp,128 - 421a: 0200 addi s0,sp,256 - 421c: 2304 fld fs1,0(a4) - 421e: 00090003 lb zero,0(s2) - 4222: 0100 addi s0,sp,128 - 4224: 0200 addi s0,sp,256 - 4226: 2304 fld fs1,0(a4) - 4228: 00090003 lb zero,0(s2) - 422c: 0100 addi s0,sp,128 - 422e: 0200 addi s0,sp,256 - 4230: 2304 fld fs1,0(a4) - 4232: 00090003 lb zero,0(s2) - 4236: 0100 addi s0,sp,128 - 4238: 0200 addi s0,sp,256 - 423a: 2304 fld fs1,0(a4) - 423c: 08090003 lb zero,128(s2) - 4240: 0100 addi s0,sp,128 - 4242: 0200 addi s0,sp,256 - 4244: 2304 fld fs1,0(a4) - 4246: 00090003 lb zero,0(s2) - 424a: 0100 addi s0,sp,128 - 424c: 0200 addi s0,sp,256 - 424e: 2204 fld fs1,0(a2) - 4250: 08090003 lb zero,128(s2) - 4254: 0100 addi s0,sp,128 - 4256: 0200 addi s0,sp,256 - 4258: 2d04 fld fs1,24(a0) - 425a: 04090003 lb zero,64(s2) - 425e: 0100 addi s0,sp,128 - 4260: 0200 addi s0,sp,256 - 4262: 2d04 fld fs1,24(a0) - 4264: 00090003 lb zero,0(s2) - 4268: 0100 addi s0,sp,128 - 426a: 0200 addi s0,sp,256 - 426c: 2d04 fld fs1,24(a0) - 426e: 00090003 lb zero,0(s2) - 4272: 0100 addi s0,sp,128 - 4274: 0200 addi s0,sp,256 - 4276: 2d04 fld fs1,24(a0) - 4278: 00090003 lb zero,0(s2) - 427c: 0100 addi s0,sp,128 - 427e: 0200 addi s0,sp,256 - 4280: 2d04 fld fs1,24(a0) - 4282: 08090003 lb zero,128(s2) - 4286: 0100 addi s0,sp,128 - 4288: 0200 addi s0,sp,256 - 428a: 2d04 fld fs1,24(a0) - 428c: 00090003 lb zero,0(s2) - 4290: 0100 addi s0,sp,128 - 4292: 0200 addi s0,sp,256 - 4294: 3504 fld fs1,40(a0) - 4296: 08090003 lb zero,128(s2) - 429a: 0100 addi s0,sp,128 - 429c: 0200 addi s0,sp,256 - 429e: 3504 fld fs1,40(a0) - 42a0: 00090003 lb zero,0(s2) - 42a4: 0100 addi s0,sp,128 - 42a6: 0200 addi s0,sp,256 - 42a8: 3504 fld fs1,40(a0) - 42aa: 00090003 lb zero,0(s2) - 42ae: 0100 addi s0,sp,128 - 42b0: 0200 addi s0,sp,256 - 42b2: 3504 fld fs1,40(a0) - 42b4: 00090003 lb zero,0(s2) - 42b8: 0100 addi s0,sp,128 - 42ba: 0200 addi s0,sp,256 - 42bc: 3504 fld fs1,40(a0) - 42be: 08090003 lb zero,128(s2) - 42c2: 0100 addi s0,sp,128 - 42c4: 0200 addi s0,sp,256 - 42c6: 3504 fld fs1,40(a0) - 42c8: 00090003 lb zero,0(s2) - 42cc: 0100 addi s0,sp,128 - 42ce: 0306 slli t1,t1,0x1 - 42d0: 0900 addi s0,sp,144 - 42d2: 0014 0x14 - 42d4: 0001 nop - 42d6: 0402 c.slli64 s0 - 42d8: 0641 addi a2,a2,16 - 42da: 04090003 lb zero,64(s2) - 42de: 0100 addi s0,sp,128 - 42e0: 0200 addi s0,sp,256 - 42e2: 4104 lw s1,0(a0) - 42e4: 14090003 lb zero,320(s2) - 42e8: 0100 addi s0,sp,128 - 42ea: 0200 addi s0,sp,256 - 42ec: 4104 lw s1,0(a0) - 42ee: 00090003 lb zero,0(s2) - 42f2: 0100 addi s0,sp,128 - 42f4: 0200 addi s0,sp,256 - 42f6: 4404 lw s1,8(s0) - 42f8: 0c090003 lb zero,192(s2) - 42fc: 0100 addi s0,sp,128 - 42fe: 0200 addi s0,sp,256 - 4300: 4404 lw s1,8(s0) - 4302: 1c090003 lb zero,448(s2) - 4306: 0100 addi s0,sp,128 - 4308: 0200 addi s0,sp,256 - 430a: 4804 lw s1,16(s0) - 430c: 08090003 lb zero,128(s2) - 4310: 0100 addi s0,sp,128 - 4312: 0200 addi s0,sp,256 - 4314: 4804 lw s1,16(s0) - 4316: 10090003 lb zero,256(s2) - 431a: 0100 addi s0,sp,128 - 431c: 0200 addi s0,sp,256 - 431e: 4704 lw s1,8(a4) - 4320: 04090003 lb zero,64(s2) - 4324: 0100 addi s0,sp,128 - 4326: 0200 addi s0,sp,256 - 4328: 4904 lw s1,16(a0) - 432a: 04090003 lb zero,64(s2) - 432e: 0100 addi s0,sp,128 - 4330: 0200 addi s0,sp,256 - 4332: 4904 lw s1,16(a0) - 4334: 00090003 lb zero,0(s2) - 4338: 0100 addi s0,sp,128 - 433a: 0200 addi s0,sp,256 - 433c: 0304 addi s1,sp,384 - 433e: 10090003 lb zero,256(s2) - 4342: 0100 addi s0,sp,128 - 4344: 0306 slli t1,t1,0x1 - 4346: 0900 addi s0,sp,144 - 4348: 0014 0x14 - 434a: 0001 nop - 434c: 0402 c.slli64 s0 - 434e: 0602 c.slli64 a2 - 4350: 14090103 lb sp,320(s2) - 4354: 0100 addi s0,sp,128 - 4356: 0200 addi s0,sp,256 - 4358: 0204 addi s1,sp,256 - 435a: 00090003 lb zero,0(s2) - 435e: 0100 addi s0,sp,128 - 4360: 0200 addi s0,sp,256 - 4362: 0204 addi s1,sp,256 - 4364: 00090003 lb zero,0(s2) - 4368: 0100 addi s0,sp,128 - 436a: 0200 addi s0,sp,256 - 436c: 0204 addi s1,sp,256 - 436e: 00090003 lb zero,0(s2) - 4372: 0100 addi s0,sp,128 - 4374: 0200 addi s0,sp,256 - 4376: 0204 addi s1,sp,256 - 4378: 00090003 lb zero,0(s2) - 437c: 0100 addi s0,sp,128 - 437e: 0200 addi s0,sp,256 - 4380: 0204 addi s1,sp,256 - 4382: 00090003 lb zero,0(s2) - 4386: 0100 addi s0,sp,128 - 4388: 0200 addi s0,sp,256 - 438a: 0204 addi s1,sp,256 - 438c: 00090003 lb zero,0(s2) - 4390: 0100 addi s0,sp,128 - 4392: 0200 addi s0,sp,256 - 4394: 0204 addi s1,sp,256 - 4396: 00090003 lb zero,0(s2) - 439a: 0100 addi s0,sp,128 - 439c: 0200 addi s0,sp,256 - 439e: 0204 addi s1,sp,256 - 43a0: 00090003 lb zero,0(s2) - 43a4: 0100 addi s0,sp,128 - 43a6: 0200 addi s0,sp,256 - 43a8: 0204 addi s1,sp,256 - 43aa: 00090003 lb zero,0(s2) - 43ae: 0100 addi s0,sp,128 - 43b0: 0200 addi s0,sp,256 - 43b2: 0204 addi s1,sp,256 - 43b4: 00090003 lb zero,0(s2) - 43b8: 0100 addi s0,sp,128 - 43ba: 0200 addi s0,sp,256 - 43bc: 0204 addi s1,sp,256 - 43be: 00090003 lb zero,0(s2) - 43c2: 0100 addi s0,sp,128 - 43c4: 0200 addi s0,sp,256 - 43c6: 0204 addi s1,sp,256 - 43c8: 00090003 lb zero,0(s2) - 43cc: 0100 addi s0,sp,128 - 43ce: 0200 addi s0,sp,256 - 43d0: 0204 addi s1,sp,256 - 43d2: 04090003 lb zero,64(s2) - 43d6: 0100 addi s0,sp,128 - 43d8: 0200 addi s0,sp,256 - 43da: 0204 addi s1,sp,256 - 43dc: 10090003 lb zero,256(s2) - 43e0: 0100 addi s0,sp,128 - 43e2: 0200 addi s0,sp,256 - 43e4: 0204 addi s1,sp,256 - 43e6: 00090003 lb zero,0(s2) - 43ea: 0100 addi s0,sp,128 - 43ec: 0200 addi s0,sp,256 - 43ee: 0204 addi s1,sp,256 - 43f0: 04090003 lb zero,64(s2) - 43f4: 0100 addi s0,sp,128 - 43f6: 0200 addi s0,sp,256 - 43f8: 0204 addi s1,sp,256 - 43fa: 10090003 lb zero,256(s2) - 43fe: 0100 addi s0,sp,128 - 4400: 0200 addi s0,sp,256 - 4402: 0204 addi s1,sp,256 - 4404: 00090003 lb zero,0(s2) - 4408: 0100 addi s0,sp,128 - 440a: 0200 addi s0,sp,256 - 440c: 0204 addi s1,sp,256 - 440e: 04090003 lb zero,64(s2) - 4412: 0100 addi s0,sp,128 - 4414: 0200 addi s0,sp,256 - 4416: 0204 addi s1,sp,256 - 4418: 10090003 lb zero,256(s2) - 441c: 0100 addi s0,sp,128 - 441e: 0200 addi s0,sp,256 - 4420: 0204 addi s1,sp,256 - 4422: 00090003 lb zero,0(s2) - 4426: 0100 addi s0,sp,128 - 4428: 0200 addi s0,sp,256 - 442a: 0204 addi s1,sp,256 - 442c: 00090003 lb zero,0(s2) - 4430: 0100 addi s0,sp,128 - 4432: 0200 addi s0,sp,256 - 4434: 0904 addi s1,sp,144 - 4436: 04090003 lb zero,64(s2) - 443a: 0100 addi s0,sp,128 - 443c: 0200 addi s0,sp,256 - 443e: 0b04 addi s1,sp,400 - 4440: 04090003 lb zero,64(s2) - 4444: 0100 addi s0,sp,128 - 4446: 0200 addi s0,sp,256 - 4448: 0b04 addi s1,sp,400 - 444a: 08090003 lb zero,128(s2) - 444e: 0100 addi s0,sp,128 - 4450: 0200 addi s0,sp,256 - 4452: 0b04 addi s1,sp,400 - 4454: 24090003 lb zero,576(s2) - 4458: 0100 addi s0,sp,128 - 445a: 0200 addi s0,sp,256 - 445c: 0b04 addi s1,sp,400 - 445e: 00090003 lb zero,0(s2) - 4462: 0100 addi s0,sp,128 - 4464: 0200 addi s0,sp,256 - 4466: 0b04 addi s1,sp,400 - 4468: 00090003 lb zero,0(s2) - 446c: 0100 addi s0,sp,128 - 446e: 0200 addi s0,sp,256 - 4470: 0b04 addi s1,sp,400 - 4472: 00090003 lb zero,0(s2) - 4476: 0100 addi s0,sp,128 - 4478: 0200 addi s0,sp,256 - 447a: 0b04 addi s1,sp,400 - 447c: 00090003 lb zero,0(s2) - 4480: 0100 addi s0,sp,128 - 4482: 0200 addi s0,sp,256 - 4484: 0b04 addi s1,sp,400 - 4486: 00090003 lb zero,0(s2) - 448a: 0100 addi s0,sp,128 - 448c: 0200 addi s0,sp,256 - 448e: 0b04 addi s1,sp,400 - 4490: 00090003 lb zero,0(s2) - 4494: 0100 addi s0,sp,128 - 4496: 0200 addi s0,sp,256 - 4498: 0b04 addi s1,sp,400 - 449a: 00090003 lb zero,0(s2) - 449e: 0100 addi s0,sp,128 - 44a0: 0200 addi s0,sp,256 - 44a2: 0b04 addi s1,sp,400 - 44a4: 00090003 lb zero,0(s2) - 44a8: 0100 addi s0,sp,128 - 44aa: 0200 addi s0,sp,256 - 44ac: 0b04 addi s1,sp,400 - 44ae: 00090003 lb zero,0(s2) - 44b2: 0100 addi s0,sp,128 - 44b4: 0200 addi s0,sp,256 - 44b6: 0b04 addi s1,sp,400 - 44b8: 00090003 lb zero,0(s2) - 44bc: 0100 addi s0,sp,128 - 44be: 0200 addi s0,sp,256 - 44c0: 0b04 addi s1,sp,400 - 44c2: 04090003 lb zero,64(s2) - 44c6: 0100 addi s0,sp,128 - 44c8: 0200 addi s0,sp,256 - 44ca: 0b04 addi s1,sp,400 - 44cc: 14090003 lb zero,320(s2) - 44d0: 0100 addi s0,sp,128 - 44d2: 0200 addi s0,sp,256 - 44d4: 0b04 addi s1,sp,400 - 44d6: 00090003 lb zero,0(s2) - 44da: 0100 addi s0,sp,128 - 44dc: 0200 addi s0,sp,256 - 44de: 0b04 addi s1,sp,400 - 44e0: 00090003 lb zero,0(s2) - 44e4: 0100 addi s0,sp,128 - 44e6: 0200 addi s0,sp,256 - 44e8: 0c04 addi s1,sp,528 - 44ea: 04090003 lb zero,64(s2) - 44ee: 0100 addi s0,sp,128 - 44f0: 0200 addi s0,sp,256 - 44f2: 0e04 addi s1,sp,784 - 44f4: 08090003 lb zero,128(s2) - 44f8: 0100 addi s0,sp,128 - 44fa: 0200 addi s0,sp,256 - 44fc: 0e04 addi s1,sp,784 - 44fe: 10090003 lb zero,256(s2) - 4502: 0100 addi s0,sp,128 - 4504: 0200 addi s0,sp,256 - 4506: 0e04 addi s1,sp,784 - 4508: 20090003 lb zero,512(s2) - 450c: 0100 addi s0,sp,128 - 450e: 0200 addi s0,sp,256 - 4510: 0e04 addi s1,sp,784 - 4512: 00090003 lb zero,0(s2) - 4516: 0100 addi s0,sp,128 - 4518: 0200 addi s0,sp,256 - 451a: 0e04 addi s1,sp,784 - 451c: 00090003 lb zero,0(s2) - 4520: 0100 addi s0,sp,128 - 4522: 0200 addi s0,sp,256 - 4524: 0e04 addi s1,sp,784 - 4526: 00090003 lb zero,0(s2) - 452a: 0100 addi s0,sp,128 - 452c: 0200 addi s0,sp,256 - 452e: 0e04 addi s1,sp,784 - 4530: 00090003 lb zero,0(s2) - 4534: 0100 addi s0,sp,128 - 4536: 0200 addi s0,sp,256 - 4538: 0e04 addi s1,sp,784 - 453a: 00090003 lb zero,0(s2) - 453e: 0100 addi s0,sp,128 - 4540: 0200 addi s0,sp,256 - 4542: 0e04 addi s1,sp,784 - 4544: 00090003 lb zero,0(s2) - 4548: 0100 addi s0,sp,128 - 454a: 0200 addi s0,sp,256 - 454c: 0e04 addi s1,sp,784 - 454e: 00090003 lb zero,0(s2) - 4552: 0100 addi s0,sp,128 - 4554: 0200 addi s0,sp,256 - 4556: 0e04 addi s1,sp,784 - 4558: 00090003 lb zero,0(s2) - 455c: 0100 addi s0,sp,128 - 455e: 0200 addi s0,sp,256 - 4560: 0e04 addi s1,sp,784 - 4562: 04090003 lb zero,64(s2) - 4566: 0100 addi s0,sp,128 - 4568: 0200 addi s0,sp,256 - 456a: 0e04 addi s1,sp,784 - 456c: 00090003 lb zero,0(s2) - 4570: 0100 addi s0,sp,128 - 4572: 0200 addi s0,sp,256 - 4574: 0e04 addi s1,sp,784 - 4576: 04090003 lb zero,64(s2) - 457a: 0100 addi s0,sp,128 - 457c: 0200 addi s0,sp,256 - 457e: 0e04 addi s1,sp,784 - 4580: 10090003 lb zero,256(s2) - 4584: 0100 addi s0,sp,128 - 4586: 0200 addi s0,sp,256 - 4588: 0e04 addi s1,sp,784 - 458a: 00090003 lb zero,0(s2) - 458e: 0100 addi s0,sp,128 - 4590: 0200 addi s0,sp,256 - 4592: 0e04 addi s1,sp,784 - 4594: 00090003 lb zero,0(s2) - 4598: 0100 addi s0,sp,128 - 459a: 0200 addi s0,sp,256 - 459c: 0f04 addi s1,sp,912 - 459e: 04090003 lb zero,64(s2) - 45a2: 0100 addi s0,sp,128 - 45a4: 0200 addi s0,sp,256 - 45a6: 1104 addi s1,sp,160 - 45a8: 04090003 lb zero,64(s2) - 45ac: 0100 addi s0,sp,128 - 45ae: 0200 addi s0,sp,256 - 45b0: 1104 addi s1,sp,160 - 45b2: 18090003 lb zero,384(s2) - 45b6: 0100 addi s0,sp,128 - 45b8: 0200 addi s0,sp,256 - 45ba: 1104 addi s1,sp,160 - 45bc: 0c090003 lb zero,192(s2) - 45c0: 0100 addi s0,sp,128 - 45c2: 0200 addi s0,sp,256 - 45c4: 1104 addi s1,sp,160 - 45c6: 00090003 lb zero,0(s2) - 45ca: 0100 addi s0,sp,128 - 45cc: 0200 addi s0,sp,256 - 45ce: 1104 addi s1,sp,160 - 45d0: 00090003 lb zero,0(s2) - 45d4: 0100 addi s0,sp,128 - 45d6: 0200 addi s0,sp,256 - 45d8: 1104 addi s1,sp,160 - 45da: 00090003 lb zero,0(s2) - 45de: 0100 addi s0,sp,128 - 45e0: 0200 addi s0,sp,256 - 45e2: 1104 addi s1,sp,160 - 45e4: 00090003 lb zero,0(s2) - 45e8: 0100 addi s0,sp,128 - 45ea: 0200 addi s0,sp,256 - 45ec: 1104 addi s1,sp,160 - 45ee: 00090003 lb zero,0(s2) - 45f2: 0100 addi s0,sp,128 - 45f4: 0200 addi s0,sp,256 - 45f6: 1104 addi s1,sp,160 - 45f8: 00090003 lb zero,0(s2) - 45fc: 0100 addi s0,sp,128 - 45fe: 0200 addi s0,sp,256 - 4600: 1104 addi s1,sp,160 - 4602: 00090003 lb zero,0(s2) - 4606: 0100 addi s0,sp,128 - 4608: 0200 addi s0,sp,256 - 460a: 1104 addi s1,sp,160 - 460c: 00090003 lb zero,0(s2) - 4610: 0100 addi s0,sp,128 - 4612: 0200 addi s0,sp,256 - 4614: 1104 addi s1,sp,160 - 4616: 00090003 lb zero,0(s2) - 461a: 0100 addi s0,sp,128 - 461c: 0200 addi s0,sp,256 - 461e: 1104 addi s1,sp,160 - 4620: 00090003 lb zero,0(s2) - 4624: 0100 addi s0,sp,128 - 4626: 0200 addi s0,sp,256 - 4628: 1104 addi s1,sp,160 - 462a: 04090003 lb zero,64(s2) - 462e: 0100 addi s0,sp,128 - 4630: 0200 addi s0,sp,256 - 4632: 1104 addi s1,sp,160 - 4634: 14090003 lb zero,320(s2) - 4638: 0100 addi s0,sp,128 - 463a: 0200 addi s0,sp,256 - 463c: 1104 addi s1,sp,160 - 463e: 00090003 lb zero,0(s2) - 4642: 0100 addi s0,sp,128 - 4644: 0200 addi s0,sp,256 - 4646: 1104 addi s1,sp,160 - 4648: 00090003 lb zero,0(s2) - 464c: 0100 addi s0,sp,128 - 464e: 0200 addi s0,sp,256 - 4650: 1204 addi s1,sp,288 - 4652: 04090003 lb zero,64(s2) - 4656: 0100 addi s0,sp,128 - 4658: 0200 addi s0,sp,256 - 465a: 1404 addi s1,sp,544 - 465c: 04090003 lb zero,64(s2) - 4660: 0100 addi s0,sp,128 - 4662: 0200 addi s0,sp,256 - 4664: 1404 addi s1,sp,544 - 4666: 18090003 lb zero,384(s2) - 466a: 0100 addi s0,sp,128 - 466c: 0200 addi s0,sp,256 - 466e: 1404 addi s1,sp,544 - 4670: 1c090003 lb zero,448(s2) - 4674: 0100 addi s0,sp,128 - 4676: 0200 addi s0,sp,256 - 4678: 1404 addi s1,sp,544 - 467a: 00090003 lb zero,0(s2) - 467e: 0100 addi s0,sp,128 - 4680: 0200 addi s0,sp,256 - 4682: 1404 addi s1,sp,544 - 4684: 00090003 lb zero,0(s2) - 4688: 0100 addi s0,sp,128 - 468a: 0200 addi s0,sp,256 - 468c: 1404 addi s1,sp,544 - 468e: 00090003 lb zero,0(s2) - 4692: 0100 addi s0,sp,128 - 4694: 0200 addi s0,sp,256 - 4696: 1404 addi s1,sp,544 - 4698: 00090003 lb zero,0(s2) - 469c: 0100 addi s0,sp,128 - 469e: 0200 addi s0,sp,256 - 46a0: 1404 addi s1,sp,544 - 46a2: 00090003 lb zero,0(s2) - 46a6: 0100 addi s0,sp,128 - 46a8: 0200 addi s0,sp,256 - 46aa: 1404 addi s1,sp,544 - 46ac: 00090003 lb zero,0(s2) - 46b0: 0100 addi s0,sp,128 - 46b2: 0200 addi s0,sp,256 - 46b4: 1404 addi s1,sp,544 - 46b6: 00090003 lb zero,0(s2) - 46ba: 0100 addi s0,sp,128 - 46bc: 0200 addi s0,sp,256 - 46be: 1404 addi s1,sp,544 - 46c0: 00090003 lb zero,0(s2) - 46c4: 0100 addi s0,sp,128 - 46c6: 0200 addi s0,sp,256 - 46c8: 1404 addi s1,sp,544 - 46ca: 00090003 lb zero,0(s2) - 46ce: 0100 addi s0,sp,128 - 46d0: 0200 addi s0,sp,256 - 46d2: 1404 addi s1,sp,544 - 46d4: 00090003 lb zero,0(s2) - 46d8: 0100 addi s0,sp,128 - 46da: 0200 addi s0,sp,256 - 46dc: 1404 addi s1,sp,544 - 46de: 04090003 lb zero,64(s2) - 46e2: 0100 addi s0,sp,128 - 46e4: 0200 addi s0,sp,256 - 46e6: 1404 addi s1,sp,544 - 46e8: 14090003 lb zero,320(s2) - 46ec: 0100 addi s0,sp,128 - 46ee: 0200 addi s0,sp,256 - 46f0: 1404 addi s1,sp,544 - 46f2: 00090003 lb zero,0(s2) - 46f6: 0100 addi s0,sp,128 - 46f8: 0200 addi s0,sp,256 - 46fa: 1404 addi s1,sp,544 - 46fc: 00090003 lb zero,0(s2) - 4700: 0100 addi s0,sp,128 - 4702: 0200 addi s0,sp,256 - 4704: 1504 addi s1,sp,672 - 4706: 04090003 lb zero,64(s2) - 470a: 0100 addi s0,sp,128 - 470c: 0200 addi s0,sp,256 - 470e: 1704 addi s1,sp,928 - 4710: 04090003 lb zero,64(s2) - 4714: 0100 addi s0,sp,128 - 4716: 0200 addi s0,sp,256 - 4718: 1704 addi s1,sp,928 - 471a: 14090003 lb zero,320(s2) - 471e: 0100 addi s0,sp,128 - 4720: 0200 addi s0,sp,256 - 4722: 1704 addi s1,sp,928 - 4724: 20090003 lb zero,512(s2) - 4728: 0100 addi s0,sp,128 - 472a: 0200 addi s0,sp,256 - 472c: 1704 addi s1,sp,928 - 472e: 00090003 lb zero,0(s2) - 4732: 0100 addi s0,sp,128 - 4734: 0200 addi s0,sp,256 - 4736: 1704 addi s1,sp,928 - 4738: 00090003 lb zero,0(s2) - 473c: 0100 addi s0,sp,128 - 473e: 0200 addi s0,sp,256 - 4740: 1704 addi s1,sp,928 - 4742: 00090003 lb zero,0(s2) - 4746: 0100 addi s0,sp,128 - 4748: 0200 addi s0,sp,256 - 474a: 1704 addi s1,sp,928 - 474c: 00090003 lb zero,0(s2) - 4750: 0100 addi s0,sp,128 - 4752: 0200 addi s0,sp,256 - 4754: 1704 addi s1,sp,928 - 4756: 00090003 lb zero,0(s2) - 475a: 0100 addi s0,sp,128 - 475c: 0200 addi s0,sp,256 - 475e: 1704 addi s1,sp,928 - 4760: 00090003 lb zero,0(s2) - 4764: 0100 addi s0,sp,128 - 4766: 0200 addi s0,sp,256 - 4768: 1704 addi s1,sp,928 - 476a: 00090003 lb zero,0(s2) - 476e: 0100 addi s0,sp,128 - 4770: 0200 addi s0,sp,256 - 4772: 1704 addi s1,sp,928 - 4774: 00090003 lb zero,0(s2) - 4778: 0100 addi s0,sp,128 - 477a: 0200 addi s0,sp,256 - 477c: 1704 addi s1,sp,928 - 477e: 00090003 lb zero,0(s2) - 4782: 0100 addi s0,sp,128 - 4784: 0200 addi s0,sp,256 - 4786: 1704 addi s1,sp,928 - 4788: 00090003 lb zero,0(s2) - 478c: 0100 addi s0,sp,128 - 478e: 0200 addi s0,sp,256 - 4790: 1704 addi s1,sp,928 - 4792: 04090003 lb zero,64(s2) - 4796: 0100 addi s0,sp,128 - 4798: 0200 addi s0,sp,256 - 479a: 1704 addi s1,sp,928 - 479c: 14090003 lb zero,320(s2) - 47a0: 0100 addi s0,sp,128 - 47a2: 0200 addi s0,sp,256 - 47a4: 1704 addi s1,sp,928 - 47a6: 00090003 lb zero,0(s2) - 47aa: 0100 addi s0,sp,128 - 47ac: 0200 addi s0,sp,256 - 47ae: 1704 addi s1,sp,928 - 47b0: 00090003 lb zero,0(s2) - 47b4: 0100 addi s0,sp,128 - 47b6: 0200 addi s0,sp,256 - 47b8: 1804 addi s1,sp,48 - 47ba: 04090003 lb zero,64(s2) - 47be: 0100 addi s0,sp,128 - 47c0: 0200 addi s0,sp,256 - 47c2: 1a04 addi s1,sp,304 - 47c4: 04090003 lb zero,64(s2) - 47c8: 0100 addi s0,sp,128 - 47ca: 0200 addi s0,sp,256 - 47cc: 1a04 addi s1,sp,304 - 47ce: 08090003 lb zero,128(s2) - 47d2: 0100 addi s0,sp,128 - 47d4: 0200 addi s0,sp,256 - 47d6: 1a04 addi s1,sp,304 - 47d8: 28090003 lb zero,640(s2) - 47dc: 0100 addi s0,sp,128 - 47de: 0200 addi s0,sp,256 - 47e0: 1a04 addi s1,sp,304 - 47e2: 00090003 lb zero,0(s2) - 47e6: 0100 addi s0,sp,128 - 47e8: 0200 addi s0,sp,256 - 47ea: 1a04 addi s1,sp,304 - 47ec: 00090003 lb zero,0(s2) - 47f0: 0100 addi s0,sp,128 - 47f2: 0200 addi s0,sp,256 - 47f4: 1a04 addi s1,sp,304 - 47f6: 00090003 lb zero,0(s2) - 47fa: 0100 addi s0,sp,128 - 47fc: 0200 addi s0,sp,256 - 47fe: 1a04 addi s1,sp,304 - 4800: 00090003 lb zero,0(s2) - 4804: 0100 addi s0,sp,128 - 4806: 0200 addi s0,sp,256 - 4808: 1a04 addi s1,sp,304 - 480a: 00090003 lb zero,0(s2) - 480e: 0100 addi s0,sp,128 - 4810: 0200 addi s0,sp,256 - 4812: 1a04 addi s1,sp,304 - 4814: 00090003 lb zero,0(s2) - 4818: 0100 addi s0,sp,128 - 481a: 0200 addi s0,sp,256 - 481c: 1a04 addi s1,sp,304 - 481e: 00090003 lb zero,0(s2) - 4822: 0100 addi s0,sp,128 - 4824: 0200 addi s0,sp,256 - 4826: 1a04 addi s1,sp,304 - 4828: 00090003 lb zero,0(s2) - 482c: 0100 addi s0,sp,128 - 482e: 0200 addi s0,sp,256 - 4830: 1a04 addi s1,sp,304 - 4832: 00090003 lb zero,0(s2) - 4836: 0100 addi s0,sp,128 - 4838: 0200 addi s0,sp,256 - 483a: 1a04 addi s1,sp,304 - 483c: 00090003 lb zero,0(s2) - 4840: 0100 addi s0,sp,128 - 4842: 0200 addi s0,sp,256 - 4844: 1a04 addi s1,sp,304 - 4846: 00090003 lb zero,0(s2) - 484a: 0100 addi s0,sp,128 - 484c: 0200 addi s0,sp,256 - 484e: 1a04 addi s1,sp,304 - 4850: 00090003 lb zero,0(s2) - 4854: 0100 addi s0,sp,128 - 4856: 0200 addi s0,sp,256 - 4858: 1a04 addi s1,sp,304 - 485a: 00090003 lb zero,0(s2) - 485e: 0100 addi s0,sp,128 - 4860: 0200 addi s0,sp,256 - 4862: 1a04 addi s1,sp,304 - 4864: 10090003 lb zero,256(s2) - 4868: 0100 addi s0,sp,128 - 486a: 0200 addi s0,sp,256 - 486c: 1a04 addi s1,sp,304 - 486e: 00090003 lb zero,0(s2) - 4872: 0100 addi s0,sp,128 - 4874: 0200 addi s0,sp,256 - 4876: 1a04 addi s1,sp,304 - 4878: 04090003 lb zero,64(s2) - 487c: 0100 addi s0,sp,128 - 487e: 0200 addi s0,sp,256 - 4880: 1a04 addi s1,sp,304 - 4882: 00090003 lb zero,0(s2) - 4886: 0100 addi s0,sp,128 - 4888: 0200 addi s0,sp,256 - 488a: 1a04 addi s1,sp,304 - 488c: 04090003 lb zero,64(s2) - 4890: 0100 addi s0,sp,128 - 4892: 0200 addi s0,sp,256 - 4894: 1a04 addi s1,sp,304 - 4896: 00090003 lb zero,0(s2) - 489a: 0100 addi s0,sp,128 - 489c: 0200 addi s0,sp,256 - 489e: 1a04 addi s1,sp,304 - 48a0: 00090003 lb zero,0(s2) - 48a4: 0100 addi s0,sp,128 - 48a6: 0200 addi s0,sp,256 - 48a8: 1a04 addi s1,sp,304 - 48aa: 00090003 lb zero,0(s2) - 48ae: 0100 addi s0,sp,128 - 48b0: 0200 addi s0,sp,256 - 48b2: 1a04 addi s1,sp,304 - 48b4: 00090003 lb zero,0(s2) - 48b8: 0100 addi s0,sp,128 - 48ba: 0200 addi s0,sp,256 - 48bc: 1a04 addi s1,sp,304 - 48be: 00090003 lb zero,0(s2) - 48c2: 0100 addi s0,sp,128 - 48c4: 0200 addi s0,sp,256 - 48c6: 1a04 addi s1,sp,304 - 48c8: 0c090003 lb zero,192(s2) - 48cc: 0100 addi s0,sp,128 - 48ce: 0200 addi s0,sp,256 - 48d0: 1a04 addi s1,sp,304 - 48d2: 0c090003 lb zero,192(s2) - 48d6: 0100 addi s0,sp,128 - 48d8: 0200 addi s0,sp,256 - 48da: 1a04 addi s1,sp,304 - 48dc: 24090003 lb zero,576(s2) - 48e0: 0100 addi s0,sp,128 - 48e2: 0200 addi s0,sp,256 - 48e4: 1a04 addi s1,sp,304 - 48e6: 00090003 lb zero,0(s2) - 48ea: 0100 addi s0,sp,128 - 48ec: 0200 addi s0,sp,256 - 48ee: 1a04 addi s1,sp,304 - 48f0: 08090003 lb zero,128(s2) - 48f4: 0100 addi s0,sp,128 - 48f6: 0200 addi s0,sp,256 - 48f8: 1a04 addi s1,sp,304 - 48fa: 00090003 lb zero,0(s2) - 48fe: 0100 addi s0,sp,128 - 4900: 0200 addi s0,sp,256 - 4902: 1a04 addi s1,sp,304 - 4904: 00090003 lb zero,0(s2) - 4908: 0100 addi s0,sp,128 - 490a: 0200 addi s0,sp,256 - 490c: 1a04 addi s1,sp,304 - 490e: 00090003 lb zero,0(s2) - 4912: 0100 addi s0,sp,128 - 4914: 0200 addi s0,sp,256 - 4916: 1a04 addi s1,sp,304 - 4918: 00090003 lb zero,0(s2) - 491c: 0100 addi s0,sp,128 - 491e: 0200 addi s0,sp,256 - 4920: 1a04 addi s1,sp,304 - 4922: 00090003 lb zero,0(s2) - 4926: 0100 addi s0,sp,128 - 4928: 0200 addi s0,sp,256 - 492a: 1a04 addi s1,sp,304 - 492c: 00090003 lb zero,0(s2) - 4930: 0100 addi s0,sp,128 - 4932: 0200 addi s0,sp,256 - 4934: 1a04 addi s1,sp,304 - 4936: 0c090003 lb zero,192(s2) - 493a: 0100 addi s0,sp,128 - 493c: 0200 addi s0,sp,256 - 493e: 1a04 addi s1,sp,304 - 4940: 04090003 lb zero,64(s2) - 4944: 0100 addi s0,sp,128 - 4946: 0200 addi s0,sp,256 - 4948: 1a04 addi s1,sp,304 - 494a: 00090003 lb zero,0(s2) - 494e: 0100 addi s0,sp,128 - 4950: 0200 addi s0,sp,256 - 4952: 1a04 addi s1,sp,304 - 4954: 0c090003 lb zero,192(s2) - 4958: 0100 addi s0,sp,128 - 495a: 0200 addi s0,sp,256 - 495c: 1a04 addi s1,sp,304 - 495e: 00090003 lb zero,0(s2) - 4962: 0100 addi s0,sp,128 - 4964: 0200 addi s0,sp,256 - 4966: 1a04 addi s1,sp,304 - 4968: 00090003 lb zero,0(s2) - 496c: 0100 addi s0,sp,128 - 496e: 0200 addi s0,sp,256 - 4970: 1a04 addi s1,sp,304 - 4972: 00090003 lb zero,0(s2) - 4976: 0100 addi s0,sp,128 - 4978: 0200 addi s0,sp,256 - 497a: 1a04 addi s1,sp,304 - 497c: 00090003 lb zero,0(s2) - 4980: 0100 addi s0,sp,128 - 4982: 0200 addi s0,sp,256 - 4984: 1a04 addi s1,sp,304 - 4986: 00090003 lb zero,0(s2) - 498a: 0100 addi s0,sp,128 - 498c: 0200 addi s0,sp,256 - 498e: 1a04 addi s1,sp,304 - 4990: 00090003 lb zero,0(s2) - 4994: 0100 addi s0,sp,128 - 4996: 0200 addi s0,sp,256 - 4998: 1a04 addi s1,sp,304 - 499a: 00090003 lb zero,0(s2) - 499e: 0100 addi s0,sp,128 - 49a0: 0200 addi s0,sp,256 - 49a2: 1a04 addi s1,sp,304 - 49a4: 08090003 lb zero,128(s2) - 49a8: 0100 addi s0,sp,128 - 49aa: 0200 addi s0,sp,256 - 49ac: 1a04 addi s1,sp,304 - 49ae: 00090003 lb zero,0(s2) - 49b2: 0100 addi s0,sp,128 - 49b4: 0200 addi s0,sp,256 - 49b6: 1a04 addi s1,sp,304 - 49b8: 04090003 lb zero,64(s2) - 49bc: 0100 addi s0,sp,128 - 49be: 0200 addi s0,sp,256 - 49c0: 1a04 addi s1,sp,304 - 49c2: 00090003 lb zero,0(s2) - 49c6: 0100 addi s0,sp,128 - 49c8: 0200 addi s0,sp,256 - 49ca: 1a04 addi s1,sp,304 - 49cc: 2c090003 lb zero,704(s2) - 49d0: 0100 addi s0,sp,128 - 49d2: 0200 addi s0,sp,256 - 49d4: 1a04 addi s1,sp,304 - 49d6: 00090003 lb zero,0(s2) - 49da: 0100 addi s0,sp,128 - 49dc: 0200 addi s0,sp,256 - 49de: 1a04 addi s1,sp,304 - 49e0: 00090003 lb zero,0(s2) - 49e4: 0100 addi s0,sp,128 - 49e6: 0200 addi s0,sp,256 - 49e8: 1a04 addi s1,sp,304 - 49ea: 00090003 lb zero,0(s2) - 49ee: 0100 addi s0,sp,128 - 49f0: 0200 addi s0,sp,256 - 49f2: 1a04 addi s1,sp,304 - 49f4: 00090003 lb zero,0(s2) - 49f8: 0100 addi s0,sp,128 - 49fa: 0200 addi s0,sp,256 - 49fc: 1a04 addi s1,sp,304 - 49fe: 00090003 lb zero,0(s2) - 4a02: 0100 addi s0,sp,128 - 4a04: 0200 addi s0,sp,256 - 4a06: 1a04 addi s1,sp,304 - 4a08: 00090003 lb zero,0(s2) - 4a0c: 0100 addi s0,sp,128 - 4a0e: 0200 addi s0,sp,256 - 4a10: 1a04 addi s1,sp,304 - 4a12: 00090003 lb zero,0(s2) - 4a16: 0100 addi s0,sp,128 - 4a18: 0200 addi s0,sp,256 - 4a1a: 1a04 addi s1,sp,304 - 4a1c: 00090003 lb zero,0(s2) - 4a20: 0100 addi s0,sp,128 - 4a22: 0200 addi s0,sp,256 - 4a24: 1a04 addi s1,sp,304 - 4a26: 00090003 lb zero,0(s2) - 4a2a: 0100 addi s0,sp,128 - 4a2c: 0200 addi s0,sp,256 - 4a2e: 1a04 addi s1,sp,304 - 4a30: 00090003 lb zero,0(s2) - 4a34: 0100 addi s0,sp,128 - 4a36: 0200 addi s0,sp,256 - 4a38: 1a04 addi s1,sp,304 - 4a3a: 0c090003 lb zero,192(s2) - 4a3e: 0100 addi s0,sp,128 - 4a40: 0200 addi s0,sp,256 - 4a42: 1a04 addi s1,sp,304 - 4a44: 0c090003 lb zero,192(s2) - 4a48: 0100 addi s0,sp,128 - 4a4a: 0200 addi s0,sp,256 - 4a4c: 1a04 addi s1,sp,304 - 4a4e: 00090003 lb zero,0(s2) - 4a52: 0100 addi s0,sp,128 - 4a54: 0200 addi s0,sp,256 - 4a56: 1a04 addi s1,sp,304 - 4a58: 00090003 lb zero,0(s2) - 4a5c: 0100 addi s0,sp,128 - 4a5e: 0200 addi s0,sp,256 - 4a60: 1b04 addi s1,sp,432 - 4a62: 04090003 lb zero,64(s2) - 4a66: 0100 addi s0,sp,128 - 4a68: 0200 addi s0,sp,256 - 4a6a: 1d04 addi s1,sp,688 - 4a6c: 04090003 lb zero,64(s2) - 4a70: 0100 addi s0,sp,128 - 4a72: 0200 addi s0,sp,256 - 4a74: 1d04 addi s1,sp,688 - 4a76: 1c090003 lb zero,448(s2) - 4a7a: 0100 addi s0,sp,128 - 4a7c: 0200 addi s0,sp,256 - 4a7e: 1d04 addi s1,sp,688 - 4a80: 14090003 lb zero,320(s2) - 4a84: 0100 addi s0,sp,128 - 4a86: 0200 addi s0,sp,256 - 4a88: 1d04 addi s1,sp,688 - 4a8a: 00090003 lb zero,0(s2) - 4a8e: 0100 addi s0,sp,128 - 4a90: 0200 addi s0,sp,256 - 4a92: 1d04 addi s1,sp,688 - 4a94: 00090003 lb zero,0(s2) - 4a98: 0100 addi s0,sp,128 - 4a9a: 0200 addi s0,sp,256 - 4a9c: 1d04 addi s1,sp,688 - 4a9e: 00090003 lb zero,0(s2) - 4aa2: 0100 addi s0,sp,128 - 4aa4: 0200 addi s0,sp,256 - 4aa6: 1d04 addi s1,sp,688 - 4aa8: 00090003 lb zero,0(s2) - 4aac: 0100 addi s0,sp,128 - 4aae: 0200 addi s0,sp,256 - 4ab0: 1d04 addi s1,sp,688 - 4ab2: 00090003 lb zero,0(s2) - 4ab6: 0100 addi s0,sp,128 - 4ab8: 0200 addi s0,sp,256 - 4aba: 1d04 addi s1,sp,688 - 4abc: 00090003 lb zero,0(s2) - 4ac0: 0100 addi s0,sp,128 - 4ac2: 0200 addi s0,sp,256 - 4ac4: 1d04 addi s1,sp,688 - 4ac6: 00090003 lb zero,0(s2) - 4aca: 0100 addi s0,sp,128 - 4acc: 0200 addi s0,sp,256 - 4ace: 1d04 addi s1,sp,688 - 4ad0: 00090003 lb zero,0(s2) - 4ad4: 0100 addi s0,sp,128 - 4ad6: 0200 addi s0,sp,256 - 4ad8: 1d04 addi s1,sp,688 - 4ada: 08090003 lb zero,128(s2) - 4ade: 0100 addi s0,sp,128 - 4ae0: 0200 addi s0,sp,256 - 4ae2: 1d04 addi s1,sp,688 - 4ae4: 00090003 lb zero,0(s2) - 4ae8: 0100 addi s0,sp,128 - 4aea: 0200 addi s0,sp,256 - 4aec: 1d04 addi s1,sp,688 - 4aee: 04090003 lb zero,64(s2) - 4af2: 0100 addi s0,sp,128 - 4af4: 0200 addi s0,sp,256 - 4af6: 1d04 addi s1,sp,688 - 4af8: 00090003 lb zero,0(s2) - 4afc: 0100 addi s0,sp,128 - 4afe: 0200 addi s0,sp,256 - 4b00: 1d04 addi s1,sp,688 - 4b02: 08090003 lb zero,128(s2) - 4b06: 0100 addi s0,sp,128 - 4b08: 0200 addi s0,sp,256 - 4b0a: 1d04 addi s1,sp,688 - 4b0c: 04090003 lb zero,64(s2) - 4b10: 0100 addi s0,sp,128 - 4b12: 0200 addi s0,sp,256 - 4b14: 1e04 addi s1,sp,816 - 4b16: 04090003 lb zero,64(s2) - 4b1a: 0100 addi s0,sp,128 - 4b1c: 0200 addi s0,sp,256 - 4b1e: 2004 fld fs1,0(s0) - 4b20: 04090003 lb zero,64(s2) - 4b24: 0100 addi s0,sp,128 - 4b26: 0200 addi s0,sp,256 - 4b28: 2004 fld fs1,0(s0) - 4b2a: 10090003 lb zero,256(s2) - 4b2e: 0100 addi s0,sp,128 - 4b30: 0200 addi s0,sp,256 - 4b32: 2004 fld fs1,0(s0) - 4b34: 14090003 lb zero,320(s2) - 4b38: 0100 addi s0,sp,128 - 4b3a: 0200 addi s0,sp,256 - 4b3c: 2004 fld fs1,0(s0) - 4b3e: 00090003 lb zero,0(s2) - 4b42: 0100 addi s0,sp,128 - 4b44: 0200 addi s0,sp,256 - 4b46: 2004 fld fs1,0(s0) - 4b48: 00090003 lb zero,0(s2) - 4b4c: 0100 addi s0,sp,128 - 4b4e: 0200 addi s0,sp,256 - 4b50: 2004 fld fs1,0(s0) - 4b52: 00090003 lb zero,0(s2) - 4b56: 0100 addi s0,sp,128 - 4b58: 0200 addi s0,sp,256 - 4b5a: 2004 fld fs1,0(s0) - 4b5c: 00090003 lb zero,0(s2) - 4b60: 0100 addi s0,sp,128 - 4b62: 0200 addi s0,sp,256 - 4b64: 2004 fld fs1,0(s0) - 4b66: 00090003 lb zero,0(s2) - 4b6a: 0100 addi s0,sp,128 - 4b6c: 0200 addi s0,sp,256 - 4b6e: 2004 fld fs1,0(s0) - 4b70: 00090003 lb zero,0(s2) - 4b74: 0100 addi s0,sp,128 - 4b76: 0200 addi s0,sp,256 - 4b78: 2004 fld fs1,0(s0) - 4b7a: 00090003 lb zero,0(s2) - 4b7e: 0100 addi s0,sp,128 - 4b80: 0200 addi s0,sp,256 - 4b82: 2004 fld fs1,0(s0) - 4b84: 00090003 lb zero,0(s2) - 4b88: 0100 addi s0,sp,128 - 4b8a: 0200 addi s0,sp,256 - 4b8c: 2004 fld fs1,0(s0) - 4b8e: 00090003 lb zero,0(s2) - 4b92: 0100 addi s0,sp,128 - 4b94: 0200 addi s0,sp,256 - 4b96: 2004 fld fs1,0(s0) - 4b98: 00090003 lb zero,0(s2) - 4b9c: 0100 addi s0,sp,128 - 4b9e: 0200 addi s0,sp,256 - 4ba0: 2004 fld fs1,0(s0) - 4ba2: 04090003 lb zero,64(s2) - 4ba6: 0100 addi s0,sp,128 - 4ba8: 0200 addi s0,sp,256 - 4baa: 2004 fld fs1,0(s0) - 4bac: 14090003 lb zero,320(s2) - 4bb0: 0100 addi s0,sp,128 - 4bb2: 0200 addi s0,sp,256 - 4bb4: 2004 fld fs1,0(s0) - 4bb6: 00090003 lb zero,0(s2) - 4bba: 0100 addi s0,sp,128 - 4bbc: 0200 addi s0,sp,256 - 4bbe: 2004 fld fs1,0(s0) - 4bc0: 00090003 lb zero,0(s2) - 4bc4: 0100 addi s0,sp,128 - 4bc6: 0200 addi s0,sp,256 - 4bc8: 2104 fld fs1,0(a0) - 4bca: 04090003 lb zero,64(s2) - 4bce: 0100 addi s0,sp,128 - 4bd0: 0200 addi s0,sp,256 - 4bd2: 2304 fld fs1,0(a4) - 4bd4: 04090003 lb zero,64(s2) - 4bd8: 0100 addi s0,sp,128 - 4bda: 0200 addi s0,sp,256 - 4bdc: 2304 fld fs1,0(a4) - 4bde: 10090003 lb zero,256(s2) - 4be2: 0100 addi s0,sp,128 - 4be4: 0200 addi s0,sp,256 - 4be6: 2304 fld fs1,0(a4) - 4be8: 18090003 lb zero,384(s2) - 4bec: 0100 addi s0,sp,128 - 4bee: 0200 addi s0,sp,256 - 4bf0: 2304 fld fs1,0(a4) - 4bf2: 00090003 lb zero,0(s2) - 4bf6: 0100 addi s0,sp,128 - 4bf8: 0200 addi s0,sp,256 - 4bfa: 2304 fld fs1,0(a4) - 4bfc: 00090003 lb zero,0(s2) - 4c00: 0100 addi s0,sp,128 - 4c02: 0200 addi s0,sp,256 - 4c04: 2304 fld fs1,0(a4) - 4c06: 00090003 lb zero,0(s2) - 4c0a: 0100 addi s0,sp,128 - 4c0c: 0200 addi s0,sp,256 - 4c0e: 2304 fld fs1,0(a4) - 4c10: 00090003 lb zero,0(s2) - 4c14: 0100 addi s0,sp,128 - 4c16: 0200 addi s0,sp,256 - 4c18: 2304 fld fs1,0(a4) - 4c1a: 00090003 lb zero,0(s2) - 4c1e: 0100 addi s0,sp,128 - 4c20: 0200 addi s0,sp,256 - 4c22: 2304 fld fs1,0(a4) - 4c24: 00090003 lb zero,0(s2) - 4c28: 0100 addi s0,sp,128 - 4c2a: 0200 addi s0,sp,256 - 4c2c: 2304 fld fs1,0(a4) - 4c2e: 00090003 lb zero,0(s2) - 4c32: 0100 addi s0,sp,128 - 4c34: 0200 addi s0,sp,256 - 4c36: 2304 fld fs1,0(a4) - 4c38: 00090003 lb zero,0(s2) - 4c3c: 0100 addi s0,sp,128 - 4c3e: 0200 addi s0,sp,256 - 4c40: 2304 fld fs1,0(a4) - 4c42: 04090003 lb zero,64(s2) - 4c46: 0100 addi s0,sp,128 - 4c48: 0200 addi s0,sp,256 - 4c4a: 2304 fld fs1,0(a4) - 4c4c: 00090003 lb zero,0(s2) - 4c50: 0100 addi s0,sp,128 - 4c52: 0200 addi s0,sp,256 - 4c54: 2304 fld fs1,0(a4) - 4c56: 00090003 lb zero,0(s2) - 4c5a: 0100 addi s0,sp,128 - 4c5c: 0200 addi s0,sp,256 - 4c5e: 2304 fld fs1,0(a4) - 4c60: 14090003 lb zero,320(s2) - 4c64: 0100 addi s0,sp,128 - 4c66: 0200 addi s0,sp,256 - 4c68: 2304 fld fs1,0(a4) - 4c6a: 00090003 lb zero,0(s2) - 4c6e: 0100 addi s0,sp,128 - 4c70: 0200 addi s0,sp,256 - 4c72: 2304 fld fs1,0(a4) - 4c74: 00090003 lb zero,0(s2) - 4c78: 0100 addi s0,sp,128 - 4c7a: 0200 addi s0,sp,256 - 4c7c: 2404 fld fs1,8(s0) - 4c7e: 04090003 lb zero,64(s2) - 4c82: 0100 addi s0,sp,128 - 4c84: 0200 addi s0,sp,256 - 4c86: 2604 fld fs1,8(a2) - 4c88: 04090003 lb zero,64(s2) - 4c8c: 0100 addi s0,sp,128 - 4c8e: 0200 addi s0,sp,256 - 4c90: 2604 fld fs1,8(a2) - 4c92: 80090003 lb zero,-2048(s2) - 4c96: 0100 addi s0,sp,128 - 4c98: 0200 addi s0,sp,256 - 4c9a: 2604 fld fs1,8(a2) - 4c9c: 00090003 lb zero,0(s2) - 4ca0: 0100 addi s0,sp,128 - 4ca2: 0200 addi s0,sp,256 - 4ca4: 2604 fld fs1,8(a2) - 4ca6: 00090003 lb zero,0(s2) - 4caa: 0100 addi s0,sp,128 - 4cac: 0200 addi s0,sp,256 - 4cae: 2604 fld fs1,8(a2) - 4cb0: 00090003 lb zero,0(s2) - 4cb4: 0100 addi s0,sp,128 - 4cb6: 0200 addi s0,sp,256 - 4cb8: 2604 fld fs1,8(a2) - 4cba: 00090003 lb zero,0(s2) - 4cbe: 0100 addi s0,sp,128 - 4cc0: 0200 addi s0,sp,256 - 4cc2: 2604 fld fs1,8(a2) - 4cc4: 00090003 lb zero,0(s2) - 4cc8: 0100 addi s0,sp,128 - 4cca: 0200 addi s0,sp,256 - 4ccc: 2604 fld fs1,8(a2) - 4cce: 00090003 lb zero,0(s2) - 4cd2: 0100 addi s0,sp,128 - 4cd4: 0200 addi s0,sp,256 - 4cd6: 2604 fld fs1,8(a2) - 4cd8: 00090003 lb zero,0(s2) - 4cdc: 0100 addi s0,sp,128 - 4cde: 0200 addi s0,sp,256 - 4ce0: 2604 fld fs1,8(a2) - 4ce2: 00090003 lb zero,0(s2) - 4ce6: 0100 addi s0,sp,128 - 4ce8: 0200 addi s0,sp,256 - 4cea: 2604 fld fs1,8(a2) - 4cec: 00090003 lb zero,0(s2) - 4cf0: 0100 addi s0,sp,128 - 4cf2: 0200 addi s0,sp,256 - 4cf4: 2604 fld fs1,8(a2) - 4cf6: 00090003 lb zero,0(s2) - 4cfa: 0100 addi s0,sp,128 - 4cfc: 0200 addi s0,sp,256 - 4cfe: 2604 fld fs1,8(a2) - 4d00: 00090003 lb zero,0(s2) - 4d04: 0100 addi s0,sp,128 - 4d06: 0200 addi s0,sp,256 - 4d08: 2604 fld fs1,8(a2) - 4d0a: 00090003 lb zero,0(s2) - 4d0e: 0100 addi s0,sp,128 - 4d10: 0200 addi s0,sp,256 - 4d12: 2604 fld fs1,8(a2) - 4d14: 00090003 lb zero,0(s2) - 4d18: 0100 addi s0,sp,128 - 4d1a: 0200 addi s0,sp,256 - 4d1c: 2604 fld fs1,8(a2) - 4d1e: 00090003 lb zero,0(s2) - 4d22: 0100 addi s0,sp,128 - 4d24: 0200 addi s0,sp,256 - 4d26: 2604 fld fs1,8(a2) - 4d28: 00090003 lb zero,0(s2) - 4d2c: 0100 addi s0,sp,128 - 4d2e: 0200 addi s0,sp,256 - 4d30: 2604 fld fs1,8(a2) - 4d32: 00090003 lb zero,0(s2) - 4d36: 0100 addi s0,sp,128 - 4d38: 0200 addi s0,sp,256 - 4d3a: 2604 fld fs1,8(a2) - 4d3c: 00090003 lb zero,0(s2) - 4d40: 0100 addi s0,sp,128 - 4d42: 0200 addi s0,sp,256 - 4d44: 2604 fld fs1,8(a2) - 4d46: 00090003 lb zero,0(s2) - 4d4a: 0100 addi s0,sp,128 - 4d4c: 0200 addi s0,sp,256 - 4d4e: 2604 fld fs1,8(a2) - 4d50: 00090003 lb zero,0(s2) - 4d54: 0100 addi s0,sp,128 - 4d56: 0200 addi s0,sp,256 - 4d58: 2604 fld fs1,8(a2) - 4d5a: 00090003 lb zero,0(s2) - 4d5e: 0100 addi s0,sp,128 - 4d60: 0200 addi s0,sp,256 - 4d62: 2604 fld fs1,8(a2) - 4d64: 00090003 lb zero,0(s2) - 4d68: 0100 addi s0,sp,128 - 4d6a: 0200 addi s0,sp,256 - 4d6c: 2604 fld fs1,8(a2) - 4d6e: 00090003 lb zero,0(s2) - 4d72: 0100 addi s0,sp,128 - 4d74: 0200 addi s0,sp,256 - 4d76: 2604 fld fs1,8(a2) - 4d78: 00090003 lb zero,0(s2) - 4d7c: 0100 addi s0,sp,128 - 4d7e: 0200 addi s0,sp,256 - 4d80: 2604 fld fs1,8(a2) - 4d82: 00090003 lb zero,0(s2) - 4d86: 0100 addi s0,sp,128 - 4d88: 0200 addi s0,sp,256 - 4d8a: 2604 fld fs1,8(a2) - 4d8c: 00090003 lb zero,0(s2) - 4d90: 0100 addi s0,sp,128 - 4d92: 0200 addi s0,sp,256 - 4d94: 2604 fld fs1,8(a2) - 4d96: 00090003 lb zero,0(s2) - 4d9a: 0100 addi s0,sp,128 - 4d9c: 0200 addi s0,sp,256 - 4d9e: 2604 fld fs1,8(a2) - 4da0: 00090003 lb zero,0(s2) - 4da4: 0100 addi s0,sp,128 - 4da6: 0200 addi s0,sp,256 - 4da8: 2604 fld fs1,8(a2) - 4daa: 00090003 lb zero,0(s2) - 4dae: 0100 addi s0,sp,128 - 4db0: 0200 addi s0,sp,256 - 4db2: 2604 fld fs1,8(a2) - 4db4: 00090003 lb zero,0(s2) - 4db8: 0100 addi s0,sp,128 - 4dba: 0200 addi s0,sp,256 - 4dbc: 2604 fld fs1,8(a2) - 4dbe: 00090003 lb zero,0(s2) - 4dc2: 0100 addi s0,sp,128 - 4dc4: 0200 addi s0,sp,256 - 4dc6: 2604 fld fs1,8(a2) - 4dc8: 00090003 lb zero,0(s2) - 4dcc: 0100 addi s0,sp,128 - 4dce: 0200 addi s0,sp,256 - 4dd0: 2604 fld fs1,8(a2) - 4dd2: 00090003 lb zero,0(s2) - 4dd6: 0100 addi s0,sp,128 - 4dd8: 0200 addi s0,sp,256 - 4dda: 2604 fld fs1,8(a2) - 4ddc: 00090003 lb zero,0(s2) - 4de0: 0100 addi s0,sp,128 - 4de2: 0200 addi s0,sp,256 - 4de4: 2604 fld fs1,8(a2) - 4de6: 00090003 lb zero,0(s2) - 4dea: 0100 addi s0,sp,128 - 4dec: 0200 addi s0,sp,256 - 4dee: 2604 fld fs1,8(a2) - 4df0: 3c090003 lb zero,960(s2) - 4df4: 0100 addi s0,sp,128 - 4df6: 0200 addi s0,sp,256 - 4df8: 2604 fld fs1,8(a2) - 4dfa: 00090003 lb zero,0(s2) - 4dfe: 0100 addi s0,sp,128 - 4e00: 0200 addi s0,sp,256 - 4e02: 2604 fld fs1,8(a2) - 4e04: 00090003 lb zero,0(s2) - 4e08: 0100 addi s0,sp,128 - 4e0a: 0200 addi s0,sp,256 - 4e0c: 2604 fld fs1,8(a2) - 4e0e: 00090003 lb zero,0(s2) - 4e12: 0100 addi s0,sp,128 - 4e14: 0200 addi s0,sp,256 - 4e16: 2604 fld fs1,8(a2) - 4e18: 00090003 lb zero,0(s2) - 4e1c: 0100 addi s0,sp,128 - 4e1e: 0200 addi s0,sp,256 - 4e20: 2604 fld fs1,8(a2) - 4e22: 00090003 lb zero,0(s2) - 4e26: 0100 addi s0,sp,128 - 4e28: 0200 addi s0,sp,256 - 4e2a: 2604 fld fs1,8(a2) - 4e2c: 00090003 lb zero,0(s2) - 4e30: 0100 addi s0,sp,128 - 4e32: 0200 addi s0,sp,256 - 4e34: 2604 fld fs1,8(a2) - 4e36: 00090003 lb zero,0(s2) - 4e3a: 0100 addi s0,sp,128 - 4e3c: 0200 addi s0,sp,256 - 4e3e: 2604 fld fs1,8(a2) - 4e40: 00090003 lb zero,0(s2) - 4e44: 0100 addi s0,sp,128 - 4e46: 0200 addi s0,sp,256 - 4e48: 2604 fld fs1,8(a2) - 4e4a: 00090003 lb zero,0(s2) - 4e4e: 0100 addi s0,sp,128 - 4e50: 0200 addi s0,sp,256 - 4e52: 2604 fld fs1,8(a2) - 4e54: 00090003 lb zero,0(s2) - 4e58: 0100 addi s0,sp,128 - 4e5a: 0200 addi s0,sp,256 - 4e5c: 2604 fld fs1,8(a2) - 4e5e: 00090003 lb zero,0(s2) - 4e62: 0100 addi s0,sp,128 - 4e64: 0200 addi s0,sp,256 - 4e66: 2604 fld fs1,8(a2) - 4e68: 00090003 lb zero,0(s2) - 4e6c: 0100 addi s0,sp,128 - 4e6e: 0200 addi s0,sp,256 - 4e70: 2604 fld fs1,8(a2) - 4e72: 00090003 lb zero,0(s2) - 4e76: 0100 addi s0,sp,128 - 4e78: 0200 addi s0,sp,256 - 4e7a: 2604 fld fs1,8(a2) - 4e7c: 00090003 lb zero,0(s2) - 4e80: 0100 addi s0,sp,128 - 4e82: 0200 addi s0,sp,256 - 4e84: 2604 fld fs1,8(a2) - 4e86: 00090003 lb zero,0(s2) - 4e8a: 0100 addi s0,sp,128 - 4e8c: 0200 addi s0,sp,256 - 4e8e: 2604 fld fs1,8(a2) - 4e90: 00090003 lb zero,0(s2) - 4e94: 0100 addi s0,sp,128 - 4e96: 0200 addi s0,sp,256 - 4e98: 2604 fld fs1,8(a2) - 4e9a: 04090003 lb zero,64(s2) - 4e9e: 0100 addi s0,sp,128 - 4ea0: 0200 addi s0,sp,256 - 4ea2: 2604 fld fs1,8(a2) - 4ea4: 14090003 lb zero,320(s2) - 4ea8: 0100 addi s0,sp,128 - 4eaa: 0200 addi s0,sp,256 - 4eac: 2604 fld fs1,8(a2) - 4eae: 00090003 lb zero,0(s2) - 4eb2: 0100 addi s0,sp,128 - 4eb4: 0200 addi s0,sp,256 - 4eb6: 2604 fld fs1,8(a2) - 4eb8: 00090003 lb zero,0(s2) - 4ebc: 0100 addi s0,sp,128 - 4ebe: 0200 addi s0,sp,256 - 4ec0: 2704 fld fs1,8(a4) - 4ec2: 04090003 lb zero,64(s2) - 4ec6: 0100 addi s0,sp,128 - 4ec8: 0200 addi s0,sp,256 - 4eca: 2904 fld fs1,16(a0) - 4ecc: 04090003 lb zero,64(s2) - 4ed0: 0100 addi s0,sp,128 - 4ed2: 0200 addi s0,sp,256 - 4ed4: 2904 fld fs1,16(a0) - 4ed6: 10090003 lb zero,256(s2) - 4eda: 0100 addi s0,sp,128 - 4edc: 0200 addi s0,sp,256 - 4ede: 2904 fld fs1,16(a0) - 4ee0: 14090003 lb zero,320(s2) - 4ee4: 0100 addi s0,sp,128 - 4ee6: 0200 addi s0,sp,256 - 4ee8: 2904 fld fs1,16(a0) - 4eea: 00090003 lb zero,0(s2) - 4eee: 0100 addi s0,sp,128 - 4ef0: 0200 addi s0,sp,256 - 4ef2: 2904 fld fs1,16(a0) - 4ef4: 00090003 lb zero,0(s2) - 4ef8: 0100 addi s0,sp,128 - 4efa: 0200 addi s0,sp,256 - 4efc: 2904 fld fs1,16(a0) - 4efe: 00090003 lb zero,0(s2) - 4f02: 0100 addi s0,sp,128 - 4f04: 0200 addi s0,sp,256 - 4f06: 2904 fld fs1,16(a0) - 4f08: 00090003 lb zero,0(s2) - 4f0c: 0100 addi s0,sp,128 - 4f0e: 0200 addi s0,sp,256 - 4f10: 2904 fld fs1,16(a0) - 4f12: 00090003 lb zero,0(s2) - 4f16: 0100 addi s0,sp,128 - 4f18: 0200 addi s0,sp,256 - 4f1a: 2904 fld fs1,16(a0) - 4f1c: 00090003 lb zero,0(s2) - 4f20: 0100 addi s0,sp,128 - 4f22: 0200 addi s0,sp,256 - 4f24: 2904 fld fs1,16(a0) - 4f26: 00090003 lb zero,0(s2) - 4f2a: 0100 addi s0,sp,128 - 4f2c: 0200 addi s0,sp,256 - 4f2e: 2904 fld fs1,16(a0) - 4f30: 00090003 lb zero,0(s2) - 4f34: 0100 addi s0,sp,128 - 4f36: 0200 addi s0,sp,256 - 4f38: 2904 fld fs1,16(a0) - 4f3a: 04090003 lb zero,64(s2) - 4f3e: 0100 addi s0,sp,128 - 4f40: 0200 addi s0,sp,256 - 4f42: 2904 fld fs1,16(a0) - 4f44: 00090003 lb zero,0(s2) - 4f48: 0100 addi s0,sp,128 - 4f4a: 0200 addi s0,sp,256 - 4f4c: 2904 fld fs1,16(a0) - 4f4e: 00090003 lb zero,0(s2) - 4f52: 0100 addi s0,sp,128 - 4f54: 0200 addi s0,sp,256 - 4f56: 2904 fld fs1,16(a0) - 4f58: 14090003 lb zero,320(s2) - 4f5c: 0100 addi s0,sp,128 - 4f5e: 0200 addi s0,sp,256 - 4f60: 2904 fld fs1,16(a0) - 4f62: 00090003 lb zero,0(s2) - 4f66: 0100 addi s0,sp,128 - 4f68: 0200 addi s0,sp,256 - 4f6a: 2904 fld fs1,16(a0) - 4f6c: 00090003 lb zero,0(s2) - 4f70: 0100 addi s0,sp,128 - 4f72: 0200 addi s0,sp,256 - 4f74: 2a04 fld fs1,16(a2) - 4f76: 04090003 lb zero,64(s2) - 4f7a: 0100 addi s0,sp,128 - 4f7c: 0200 addi s0,sp,256 - 4f7e: 2c04 fld fs1,24(s0) - 4f80: 04090003 lb zero,64(s2) - 4f84: 0100 addi s0,sp,128 - 4f86: 0200 addi s0,sp,256 - 4f88: 2c04 fld fs1,24(s0) - 4f8a: 14090003 lb zero,320(s2) - 4f8e: 0100 addi s0,sp,128 - 4f90: 0200 addi s0,sp,256 - 4f92: 2c04 fld fs1,24(s0) - 4f94: 10090003 lb zero,256(s2) - 4f98: 0100 addi s0,sp,128 - 4f9a: 0200 addi s0,sp,256 - 4f9c: 2c04 fld fs1,24(s0) - 4f9e: 00090003 lb zero,0(s2) - 4fa2: 0100 addi s0,sp,128 - 4fa4: 0200 addi s0,sp,256 - 4fa6: 2c04 fld fs1,24(s0) - 4fa8: 00090003 lb zero,0(s2) - 4fac: 0100 addi s0,sp,128 - 4fae: 0200 addi s0,sp,256 - 4fb0: 2c04 fld fs1,24(s0) - 4fb2: 00090003 lb zero,0(s2) - 4fb6: 0100 addi s0,sp,128 - 4fb8: 0200 addi s0,sp,256 - 4fba: 2c04 fld fs1,24(s0) - 4fbc: 00090003 lb zero,0(s2) - 4fc0: 0100 addi s0,sp,128 - 4fc2: 0200 addi s0,sp,256 - 4fc4: 2c04 fld fs1,24(s0) - 4fc6: 00090003 lb zero,0(s2) - 4fca: 0100 addi s0,sp,128 - 4fcc: 0200 addi s0,sp,256 - 4fce: 2c04 fld fs1,24(s0) - 4fd0: 00090003 lb zero,0(s2) - 4fd4: 0100 addi s0,sp,128 - 4fd6: 0200 addi s0,sp,256 - 4fd8: 2c04 fld fs1,24(s0) - 4fda: 00090003 lb zero,0(s2) - 4fde: 0100 addi s0,sp,128 - 4fe0: 0200 addi s0,sp,256 - 4fe2: 2c04 fld fs1,24(s0) - 4fe4: 00090003 lb zero,0(s2) - 4fe8: 0100 addi s0,sp,128 - 4fea: 0200 addi s0,sp,256 - 4fec: 2c04 fld fs1,24(s0) - 4fee: 00090003 lb zero,0(s2) - 4ff2: 0100 addi s0,sp,128 - 4ff4: 0200 addi s0,sp,256 - 4ff6: 2c04 fld fs1,24(s0) - 4ff8: 00090003 lb zero,0(s2) - 4ffc: 0100 addi s0,sp,128 - 4ffe: 0200 addi s0,sp,256 - 5000: 2c04 fld fs1,24(s0) - 5002: 04090003 lb zero,64(s2) - 5006: 0100 addi s0,sp,128 - 5008: 0200 addi s0,sp,256 - 500a: 2c04 fld fs1,24(s0) - 500c: 08090003 lb zero,128(s2) - 5010: 0100 addi s0,sp,128 - 5012: 0200 addi s0,sp,256 - 5014: 2c04 fld fs1,24(s0) - 5016: 08090003 lb zero,128(s2) - 501a: 0100 addi s0,sp,128 - 501c: 0200 addi s0,sp,256 - 501e: 2c04 fld fs1,24(s0) - 5020: 04090003 lb zero,64(s2) - 5024: 0100 addi s0,sp,128 - 5026: 0200 addi s0,sp,256 - 5028: 2d04 fld fs1,24(a0) - 502a: 04090003 lb zero,64(s2) - 502e: 0100 addi s0,sp,128 - 5030: 0200 addi s0,sp,256 - 5032: 2f04 fld fs1,24(a4) - 5034: 04090003 lb zero,64(s2) - 5038: 0100 addi s0,sp,128 - 503a: 0200 addi s0,sp,256 - 503c: 2f04 fld fs1,24(a4) - 503e: 08090003 lb zero,128(s2) - 5042: 0100 addi s0,sp,128 - 5044: 0200 addi s0,sp,256 - 5046: 2f04 fld fs1,24(a4) - 5048: 1c090003 lb zero,448(s2) - 504c: 0100 addi s0,sp,128 - 504e: 0200 addi s0,sp,256 - 5050: 2f04 fld fs1,24(a4) - 5052: 00090003 lb zero,0(s2) - 5056: 0100 addi s0,sp,128 - 5058: 0200 addi s0,sp,256 - 505a: 2f04 fld fs1,24(a4) - 505c: 00090003 lb zero,0(s2) - 5060: 0100 addi s0,sp,128 - 5062: 0200 addi s0,sp,256 - 5064: 2f04 fld fs1,24(a4) - 5066: 00090003 lb zero,0(s2) - 506a: 0100 addi s0,sp,128 - 506c: 0200 addi s0,sp,256 - 506e: 2f04 fld fs1,24(a4) - 5070: 00090003 lb zero,0(s2) - 5074: 0100 addi s0,sp,128 - 5076: 0200 addi s0,sp,256 - 5078: 2f04 fld fs1,24(a4) - 507a: 00090003 lb zero,0(s2) - 507e: 0100 addi s0,sp,128 - 5080: 0200 addi s0,sp,256 - 5082: 2f04 fld fs1,24(a4) - 5084: 00090003 lb zero,0(s2) - 5088: 0100 addi s0,sp,128 - 508a: 0200 addi s0,sp,256 - 508c: 2f04 fld fs1,24(a4) - 508e: 00090003 lb zero,0(s2) - 5092: 0100 addi s0,sp,128 - 5094: 0200 addi s0,sp,256 - 5096: 2f04 fld fs1,24(a4) - 5098: 00090003 lb zero,0(s2) - 509c: 0100 addi s0,sp,128 - 509e: 0200 addi s0,sp,256 - 50a0: 2f04 fld fs1,24(a4) - 50a2: 04090003 lb zero,64(s2) - 50a6: 0100 addi s0,sp,128 - 50a8: 0200 addi s0,sp,256 - 50aa: 2f04 fld fs1,24(a4) - 50ac: 00090003 lb zero,0(s2) - 50b0: 0100 addi s0,sp,128 - 50b2: 0200 addi s0,sp,256 - 50b4: 2f04 fld fs1,24(a4) - 50b6: 00090003 lb zero,0(s2) - 50ba: 0100 addi s0,sp,128 - 50bc: 0200 addi s0,sp,256 - 50be: 2f04 fld fs1,24(a4) - 50c0: 14090003 lb zero,320(s2) - 50c4: 0100 addi s0,sp,128 - 50c6: 0200 addi s0,sp,256 - 50c8: 2f04 fld fs1,24(a4) - 50ca: 00090003 lb zero,0(s2) - 50ce: 0100 addi s0,sp,128 - 50d0: 0200 addi s0,sp,256 - 50d2: 2f04 fld fs1,24(a4) - 50d4: 00090003 lb zero,0(s2) - 50d8: 0100 addi s0,sp,128 - 50da: 0200 addi s0,sp,256 - 50dc: 3004 fld fs1,32(s0) - 50de: 04090003 lb zero,64(s2) - 50e2: 0100 addi s0,sp,128 - 50e4: 0200 addi s0,sp,256 - 50e6: 3204 fld fs1,32(a2) - 50e8: 04090003 lb zero,64(s2) - 50ec: 0100 addi s0,sp,128 - 50ee: 0200 addi s0,sp,256 - 50f0: 3204 fld fs1,32(a2) - 50f2: 10090003 lb zero,256(s2) - 50f6: 0100 addi s0,sp,128 - 50f8: 0200 addi s0,sp,256 - 50fa: 3204 fld fs1,32(a2) - 50fc: 14090003 lb zero,320(s2) - 5100: 0100 addi s0,sp,128 - 5102: 0200 addi s0,sp,256 - 5104: 3204 fld fs1,32(a2) - 5106: 00090003 lb zero,0(s2) - 510a: 0100 addi s0,sp,128 - 510c: 0200 addi s0,sp,256 - 510e: 3204 fld fs1,32(a2) - 5110: 00090003 lb zero,0(s2) - 5114: 0100 addi s0,sp,128 - 5116: 0200 addi s0,sp,256 - 5118: 3204 fld fs1,32(a2) - 511a: 00090003 lb zero,0(s2) - 511e: 0100 addi s0,sp,128 - 5120: 0200 addi s0,sp,256 - 5122: 3204 fld fs1,32(a2) - 5124: 00090003 lb zero,0(s2) - 5128: 0100 addi s0,sp,128 - 512a: 0200 addi s0,sp,256 - 512c: 3204 fld fs1,32(a2) - 512e: 00090003 lb zero,0(s2) - 5132: 0100 addi s0,sp,128 - 5134: 0200 addi s0,sp,256 - 5136: 3204 fld fs1,32(a2) - 5138: 00090003 lb zero,0(s2) - 513c: 0100 addi s0,sp,128 - 513e: 0200 addi s0,sp,256 - 5140: 3204 fld fs1,32(a2) - 5142: 00090003 lb zero,0(s2) - 5146: 0100 addi s0,sp,128 - 5148: 0200 addi s0,sp,256 - 514a: 3204 fld fs1,32(a2) - 514c: 00090003 lb zero,0(s2) - 5150: 0100 addi s0,sp,128 - 5152: 0200 addi s0,sp,256 - 5154: 3204 fld fs1,32(a2) - 5156: 08090003 lb zero,128(s2) - 515a: 0100 addi s0,sp,128 - 515c: 0200 addi s0,sp,256 - 515e: 3204 fld fs1,32(a2) - 5160: 00090003 lb zero,0(s2) - 5164: 0100 addi s0,sp,128 - 5166: 0200 addi s0,sp,256 - 5168: 3204 fld fs1,32(a2) - 516a: 04090003 lb zero,64(s2) - 516e: 0100 addi s0,sp,128 - 5170: 0200 addi s0,sp,256 - 5172: 3204 fld fs1,32(a2) - 5174: 00090003 lb zero,0(s2) - 5178: 0100 addi s0,sp,128 - 517a: 0200 addi s0,sp,256 - 517c: 3204 fld fs1,32(a2) - 517e: 08090003 lb zero,128(s2) - 5182: 0100 addi s0,sp,128 - 5184: 0200 addi s0,sp,256 - 5186: 3204 fld fs1,32(a2) - 5188: 04090003 lb zero,64(s2) - 518c: 0100 addi s0,sp,128 - 518e: 0200 addi s0,sp,256 - 5190: 3304 fld fs1,32(a4) - 5192: 04090003 lb zero,64(s2) - 5196: 0100 addi s0,sp,128 - 5198: 0200 addi s0,sp,256 - 519a: 3504 fld fs1,40(a0) - 519c: 04090003 lb zero,64(s2) - 51a0: 0100 addi s0,sp,128 - 51a2: 0200 addi s0,sp,256 - 51a4: 3504 fld fs1,40(a0) - 51a6: 0c090003 lb zero,192(s2) - 51aa: 0100 addi s0,sp,128 - 51ac: 0200 addi s0,sp,256 - 51ae: 3504 fld fs1,40(a0) - 51b0: 28090003 lb zero,640(s2) - 51b4: 0100 addi s0,sp,128 - 51b6: 0200 addi s0,sp,256 - 51b8: 3504 fld fs1,40(a0) - 51ba: 00090003 lb zero,0(s2) - 51be: 0100 addi s0,sp,128 - 51c0: 0200 addi s0,sp,256 - 51c2: 3504 fld fs1,40(a0) - 51c4: 00090003 lb zero,0(s2) - 51c8: 0100 addi s0,sp,128 - 51ca: 0200 addi s0,sp,256 - 51cc: 3504 fld fs1,40(a0) - 51ce: 00090003 lb zero,0(s2) - 51d2: 0100 addi s0,sp,128 - 51d4: 0200 addi s0,sp,256 - 51d6: 3504 fld fs1,40(a0) - 51d8: 00090003 lb zero,0(s2) - 51dc: 0100 addi s0,sp,128 - 51de: 0200 addi s0,sp,256 - 51e0: 3504 fld fs1,40(a0) - 51e2: 00090003 lb zero,0(s2) - 51e6: 0100 addi s0,sp,128 - 51e8: 0200 addi s0,sp,256 - 51ea: 3504 fld fs1,40(a0) - 51ec: 00090003 lb zero,0(s2) - 51f0: 0100 addi s0,sp,128 - 51f2: 0200 addi s0,sp,256 - 51f4: 3504 fld fs1,40(a0) - 51f6: 00090003 lb zero,0(s2) - 51fa: 0100 addi s0,sp,128 - 51fc: 0200 addi s0,sp,256 - 51fe: 3504 fld fs1,40(a0) - 5200: 00090003 lb zero,0(s2) - 5204: 0100 addi s0,sp,128 - 5206: 0200 addi s0,sp,256 - 5208: 3504 fld fs1,40(a0) - 520a: 00090003 lb zero,0(s2) - 520e: 0100 addi s0,sp,128 - 5210: 0200 addi s0,sp,256 - 5212: 3504 fld fs1,40(a0) - 5214: 00090003 lb zero,0(s2) - 5218: 0100 addi s0,sp,128 - 521a: 0200 addi s0,sp,256 - 521c: 3504 fld fs1,40(a0) - 521e: 00090003 lb zero,0(s2) - 5222: 0100 addi s0,sp,128 - 5224: 0200 addi s0,sp,256 - 5226: 3504 fld fs1,40(a0) - 5228: 00090003 lb zero,0(s2) - 522c: 0100 addi s0,sp,128 - 522e: 0200 addi s0,sp,256 - 5230: 3504 fld fs1,40(a0) - 5232: 00090003 lb zero,0(s2) - 5236: 0100 addi s0,sp,128 - 5238: 0200 addi s0,sp,256 - 523a: 3504 fld fs1,40(a0) - 523c: 00090003 lb zero,0(s2) - 5240: 0100 addi s0,sp,128 - 5242: 0200 addi s0,sp,256 - 5244: 3504 fld fs1,40(a0) - 5246: 04090003 lb zero,64(s2) - 524a: 0100 addi s0,sp,128 - 524c: 0200 addi s0,sp,256 - 524e: 3504 fld fs1,40(a0) - 5250: 04090003 lb zero,64(s2) - 5254: 0100 addi s0,sp,128 - 5256: 0200 addi s0,sp,256 - 5258: 3504 fld fs1,40(a0) - 525a: 00090003 lb zero,0(s2) - 525e: 0100 addi s0,sp,128 - 5260: 0200 addi s0,sp,256 - 5262: 3504 fld fs1,40(a0) - 5264: 08090003 lb zero,128(s2) - 5268: 0100 addi s0,sp,128 - 526a: 0200 addi s0,sp,256 - 526c: 3504 fld fs1,40(a0) - 526e: 00090003 lb zero,0(s2) - 5272: 0100 addi s0,sp,128 - 5274: 0200 addi s0,sp,256 - 5276: 3504 fld fs1,40(a0) - 5278: 00090003 lb zero,0(s2) - 527c: 0100 addi s0,sp,128 - 527e: 0200 addi s0,sp,256 - 5280: 3504 fld fs1,40(a0) - 5282: 00090003 lb zero,0(s2) - 5286: 0100 addi s0,sp,128 - 5288: 0200 addi s0,sp,256 - 528a: 3504 fld fs1,40(a0) - 528c: 00090003 lb zero,0(s2) - 5290: 0100 addi s0,sp,128 - 5292: 0200 addi s0,sp,256 - 5294: 3504 fld fs1,40(a0) - 5296: 00090003 lb zero,0(s2) - 529a: 0100 addi s0,sp,128 - 529c: 0200 addi s0,sp,256 - 529e: 3504 fld fs1,40(a0) - 52a0: 08090003 lb zero,128(s2) - 52a4: 0100 addi s0,sp,128 - 52a6: 0200 addi s0,sp,256 - 52a8: 3504 fld fs1,40(a0) - 52aa: 04090003 lb zero,64(s2) - 52ae: 0100 addi s0,sp,128 - 52b0: 0200 addi s0,sp,256 - 52b2: 3504 fld fs1,40(a0) - 52b4: 00090003 lb zero,0(s2) - 52b8: 0100 addi s0,sp,128 - 52ba: 0200 addi s0,sp,256 - 52bc: 3504 fld fs1,40(a0) - 52be: 00090003 lb zero,0(s2) - 52c2: 0100 addi s0,sp,128 - 52c4: 0200 addi s0,sp,256 - 52c6: 3504 fld fs1,40(a0) - 52c8: 04090003 lb zero,64(s2) - 52cc: 0100 addi s0,sp,128 - 52ce: 0200 addi s0,sp,256 - 52d0: 3504 fld fs1,40(a0) - 52d2: 00090003 lb zero,0(s2) - 52d6: 0100 addi s0,sp,128 - 52d8: 0200 addi s0,sp,256 - 52da: 3504 fld fs1,40(a0) - 52dc: 00090003 lb zero,0(s2) - 52e0: 0100 addi s0,sp,128 - 52e2: 0200 addi s0,sp,256 - 52e4: 3504 fld fs1,40(a0) - 52e6: 00090003 lb zero,0(s2) - 52ea: 0100 addi s0,sp,128 - 52ec: 0200 addi s0,sp,256 - 52ee: 3504 fld fs1,40(a0) - 52f0: 00090003 lb zero,0(s2) - 52f4: 0100 addi s0,sp,128 - 52f6: 0200 addi s0,sp,256 - 52f8: 3504 fld fs1,40(a0) - 52fa: 00090003 lb zero,0(s2) - 52fe: 0100 addi s0,sp,128 - 5300: 0200 addi s0,sp,256 - 5302: 3504 fld fs1,40(a0) - 5304: 2c090003 lb zero,704(s2) - 5308: 0100 addi s0,sp,128 - 530a: 0200 addi s0,sp,256 - 530c: 3504 fld fs1,40(a0) - 530e: 08090003 lb zero,128(s2) - 5312: 0100 addi s0,sp,128 - 5314: 0200 addi s0,sp,256 - 5316: 3504 fld fs1,40(a0) - 5318: 04090003 lb zero,64(s2) - 531c: 0100 addi s0,sp,128 - 531e: 0200 addi s0,sp,256 - 5320: 3504 fld fs1,40(a0) - 5322: 00090003 lb zero,0(s2) - 5326: 0100 addi s0,sp,128 - 5328: 0200 addi s0,sp,256 - 532a: 3504 fld fs1,40(a0) - 532c: 04090003 lb zero,64(s2) - 5330: 0100 addi s0,sp,128 - 5332: 0200 addi s0,sp,256 - 5334: 3504 fld fs1,40(a0) - 5336: 2c090003 lb zero,704(s2) - 533a: 0100 addi s0,sp,128 - 533c: 0200 addi s0,sp,256 - 533e: 3504 fld fs1,40(a0) - 5340: 00090003 lb zero,0(s2) - 5344: 0100 addi s0,sp,128 - 5346: 0200 addi s0,sp,256 - 5348: 3504 fld fs1,40(a0) - 534a: 00090003 lb zero,0(s2) - 534e: 0100 addi s0,sp,128 - 5350: 0200 addi s0,sp,256 - 5352: 3504 fld fs1,40(a0) - 5354: 00090003 lb zero,0(s2) - 5358: 0100 addi s0,sp,128 - 535a: 0200 addi s0,sp,256 - 535c: 3504 fld fs1,40(a0) - 535e: 00090003 lb zero,0(s2) - 5362: 0100 addi s0,sp,128 - 5364: 0200 addi s0,sp,256 - 5366: 3504 fld fs1,40(a0) - 5368: 00090003 lb zero,0(s2) - 536c: 0100 addi s0,sp,128 - 536e: 0200 addi s0,sp,256 - 5370: 3504 fld fs1,40(a0) - 5372: 00090003 lb zero,0(s2) - 5376: 0100 addi s0,sp,128 - 5378: 0200 addi s0,sp,256 - 537a: 3504 fld fs1,40(a0) - 537c: 00090003 lb zero,0(s2) - 5380: 0100 addi s0,sp,128 - 5382: 0200 addi s0,sp,256 - 5384: 3504 fld fs1,40(a0) - 5386: 00090003 lb zero,0(s2) - 538a: 0100 addi s0,sp,128 - 538c: 0200 addi s0,sp,256 - 538e: 3504 fld fs1,40(a0) - 5390: 00090003 lb zero,0(s2) - 5394: 0100 addi s0,sp,128 - 5396: 0200 addi s0,sp,256 - 5398: 3504 fld fs1,40(a0) - 539a: 0c090003 lb zero,192(s2) - 539e: 0100 addi s0,sp,128 - 53a0: 0200 addi s0,sp,256 - 53a2: 3504 fld fs1,40(a0) - 53a4: 00090003 lb zero,0(s2) - 53a8: 0100 addi s0,sp,128 - 53aa: 0200 addi s0,sp,256 - 53ac: 3504 fld fs1,40(a0) - 53ae: 00090003 lb zero,0(s2) - 53b2: 0100 addi s0,sp,128 - 53b4: 0200 addi s0,sp,256 - 53b6: 3504 fld fs1,40(a0) - 53b8: 00090003 lb zero,0(s2) - 53bc: 0100 addi s0,sp,128 - 53be: 0200 addi s0,sp,256 - 53c0: 3504 fld fs1,40(a0) - 53c2: 00090003 lb zero,0(s2) - 53c6: 0100 addi s0,sp,128 - 53c8: 0200 addi s0,sp,256 - 53ca: 3504 fld fs1,40(a0) - 53cc: 00090003 lb zero,0(s2) - 53d0: 0100 addi s0,sp,128 - 53d2: 0200 addi s0,sp,256 - 53d4: 3504 fld fs1,40(a0) - 53d6: 00090003 lb zero,0(s2) - 53da: 0100 addi s0,sp,128 - 53dc: 0200 addi s0,sp,256 - 53de: 3504 fld fs1,40(a0) - 53e0: 00090003 lb zero,0(s2) - 53e4: 0100 addi s0,sp,128 - 53e6: 0200 addi s0,sp,256 - 53e8: 3504 fld fs1,40(a0) - 53ea: 00090003 lb zero,0(s2) - 53ee: 0100 addi s0,sp,128 - 53f0: 0200 addi s0,sp,256 - 53f2: 3504 fld fs1,40(a0) - 53f4: 00090003 lb zero,0(s2) - 53f8: 0100 addi s0,sp,128 - 53fa: 0200 addi s0,sp,256 - 53fc: 3504 fld fs1,40(a0) - 53fe: 00090003 lb zero,0(s2) - 5402: 0100 addi s0,sp,128 - 5404: 0200 addi s0,sp,256 - 5406: 3504 fld fs1,40(a0) - 5408: 00090003 lb zero,0(s2) - 540c: 0100 addi s0,sp,128 - 540e: 0200 addi s0,sp,256 - 5410: 3504 fld fs1,40(a0) - 5412: 00090003 lb zero,0(s2) - 5416: 0100 addi s0,sp,128 - 5418: 0200 addi s0,sp,256 - 541a: 3504 fld fs1,40(a0) - 541c: 0c090003 lb zero,192(s2) - 5420: 0100 addi s0,sp,128 - 5422: 0200 addi s0,sp,256 - 5424: 3504 fld fs1,40(a0) - 5426: 00090003 lb zero,0(s2) - 542a: 0100 addi s0,sp,128 - 542c: 0200 addi s0,sp,256 - 542e: 3504 fld fs1,40(a0) - 5430: 04090003 lb zero,64(s2) - 5434: 0100 addi s0,sp,128 - 5436: 0200 addi s0,sp,256 - 5438: 3604 fld fs1,40(a2) - 543a: 04090003 lb zero,64(s2) - 543e: 0100 addi s0,sp,128 - 5440: 0200 addi s0,sp,256 - 5442: 3804 fld fs1,48(s0) - 5444: 04090003 lb zero,64(s2) - 5448: 0100 addi s0,sp,128 - 544a: 0200 addi s0,sp,256 - 544c: 3804 fld fs1,48(s0) - 544e: 00090003 lb zero,0(s2) - 5452: 0100 addi s0,sp,128 - 5454: 0200 addi s0,sp,256 - 5456: 3804 fld fs1,48(s0) - 5458: 14090003 lb zero,320(s2) - 545c: 0100 addi s0,sp,128 - 545e: 0200 addi s0,sp,256 - 5460: 3804 fld fs1,48(s0) - 5462: 00090003 lb zero,0(s2) - 5466: 0100 addi s0,sp,128 - 5468: 0200 addi s0,sp,256 - 546a: 3804 fld fs1,48(s0) - 546c: 00090003 lb zero,0(s2) - 5470: 0100 addi s0,sp,128 - 5472: 0200 addi s0,sp,256 - 5474: 3804 fld fs1,48(s0) - 5476: 00090003 lb zero,0(s2) - 547a: 0100 addi s0,sp,128 - 547c: 0200 addi s0,sp,256 - 547e: 3804 fld fs1,48(s0) - 5480: 10090003 lb zero,256(s2) - 5484: 0100 addi s0,sp,128 - 5486: 0200 addi s0,sp,256 - 5488: 3804 fld fs1,48(s0) - 548a: 28090003 lb zero,640(s2) - 548e: 0100 addi s0,sp,128 - 5490: 0200 addi s0,sp,256 - 5492: 3804 fld fs1,48(s0) - 5494: 00090003 lb zero,0(s2) - 5498: 0100 addi s0,sp,128 - 549a: 0200 addi s0,sp,256 - 549c: 3804 fld fs1,48(s0) - 549e: 00090003 lb zero,0(s2) - 54a2: 0100 addi s0,sp,128 - 54a4: 0200 addi s0,sp,256 - 54a6: 3804 fld fs1,48(s0) - 54a8: 00090003 lb zero,0(s2) - 54ac: 0100 addi s0,sp,128 - 54ae: 0200 addi s0,sp,256 - 54b0: 3804 fld fs1,48(s0) - 54b2: 00090003 lb zero,0(s2) - 54b6: 0100 addi s0,sp,128 - 54b8: 0200 addi s0,sp,256 - 54ba: 3804 fld fs1,48(s0) - 54bc: 00090003 lb zero,0(s2) - 54c0: 0100 addi s0,sp,128 - 54c2: 0200 addi s0,sp,256 - 54c4: 3804 fld fs1,48(s0) - 54c6: 00090003 lb zero,0(s2) - 54ca: 0100 addi s0,sp,128 - 54cc: 0200 addi s0,sp,256 - 54ce: 3804 fld fs1,48(s0) - 54d0: 00090003 lb zero,0(s2) - 54d4: 0100 addi s0,sp,128 - 54d6: 0200 addi s0,sp,256 - 54d8: 3804 fld fs1,48(s0) - 54da: 00090003 lb zero,0(s2) - 54de: 0100 addi s0,sp,128 - 54e0: 0200 addi s0,sp,256 - 54e2: 3804 fld fs1,48(s0) - 54e4: 00090003 lb zero,0(s2) - 54e8: 0100 addi s0,sp,128 - 54ea: 0200 addi s0,sp,256 - 54ec: 3804 fld fs1,48(s0) - 54ee: 00090003 lb zero,0(s2) - 54f2: 0100 addi s0,sp,128 - 54f4: 0200 addi s0,sp,256 - 54f6: 3804 fld fs1,48(s0) - 54f8: 00090003 lb zero,0(s2) - 54fc: 0100 addi s0,sp,128 - 54fe: 0200 addi s0,sp,256 - 5500: 3804 fld fs1,48(s0) - 5502: 00090003 lb zero,0(s2) - 5506: 0100 addi s0,sp,128 - 5508: 0200 addi s0,sp,256 - 550a: 3804 fld fs1,48(s0) - 550c: 00090003 lb zero,0(s2) - 5510: 0100 addi s0,sp,128 - 5512: 0200 addi s0,sp,256 - 5514: 3804 fld fs1,48(s0) - 5516: 00090003 lb zero,0(s2) - 551a: 0100 addi s0,sp,128 - 551c: 0200 addi s0,sp,256 - 551e: 3804 fld fs1,48(s0) - 5520: 00090003 lb zero,0(s2) - 5524: 0100 addi s0,sp,128 - 5526: 0200 addi s0,sp,256 - 5528: 3804 fld fs1,48(s0) - 552a: 00090003 lb zero,0(s2) - 552e: 0100 addi s0,sp,128 - 5530: 0200 addi s0,sp,256 - 5532: 3804 fld fs1,48(s0) - 5534: 00090003 lb zero,0(s2) - 5538: 0100 addi s0,sp,128 - 553a: 0200 addi s0,sp,256 - 553c: 3804 fld fs1,48(s0) - 553e: 00090003 lb zero,0(s2) - 5542: 0100 addi s0,sp,128 - 5544: 0200 addi s0,sp,256 - 5546: 3804 fld fs1,48(s0) - 5548: 00090003 lb zero,0(s2) - 554c: 0100 addi s0,sp,128 - 554e: 0200 addi s0,sp,256 - 5550: 3804 fld fs1,48(s0) - 5552: 00090003 lb zero,0(s2) - 5556: 0100 addi s0,sp,128 - 5558: 0200 addi s0,sp,256 - 555a: 3804 fld fs1,48(s0) - 555c: 00090003 lb zero,0(s2) - 5560: 0100 addi s0,sp,128 - 5562: 0200 addi s0,sp,256 - 5564: 3804 fld fs1,48(s0) - 5566: 00090003 lb zero,0(s2) - 556a: 0100 addi s0,sp,128 - 556c: 0200 addi s0,sp,256 - 556e: 3804 fld fs1,48(s0) - 5570: 04090003 lb zero,64(s2) - 5574: 0100 addi s0,sp,128 - 5576: 0200 addi s0,sp,256 - 5578: 3804 fld fs1,48(s0) - 557a: 00090003 lb zero,0(s2) - 557e: 0100 addi s0,sp,128 - 5580: 0200 addi s0,sp,256 - 5582: 4404 lw s1,8(s0) - 5584: 08090003 lb zero,128(s2) - 5588: 0100 addi s0,sp,128 - 558a: 0200 addi s0,sp,256 - 558c: 4404 lw s1,8(s0) - 558e: 1c090003 lb zero,448(s2) - 5592: 0100 addi s0,sp,128 - 5594: 0200 addi s0,sp,256 - 5596: 4404 lw s1,8(s0) - 5598: 00090003 lb zero,0(s2) - 559c: 0100 addi s0,sp,128 - 559e: 0200 addi s0,sp,256 - 55a0: 4704 lw s1,8(a4) - 55a2: 04090003 lb zero,64(s2) - 55a6: 0100 addi s0,sp,128 - 55a8: 0200 addi s0,sp,256 - 55aa: 4704 lw s1,8(a4) - 55ac: 00090003 lb zero,0(s2) - 55b0: 0100 addi s0,sp,128 - 55b2: 0200 addi s0,sp,256 - 55b4: 4704 lw s1,8(a4) - 55b6: 00090003 lb zero,0(s2) - 55ba: 0100 addi s0,sp,128 - 55bc: 0200 addi s0,sp,256 - 55be: 4704 lw s1,8(a4) - 55c0: 10090003 lb zero,256(s2) - 55c4: 0100 addi s0,sp,128 - 55c6: 0200 addi s0,sp,256 - 55c8: 4704 lw s1,8(a4) - 55ca: 00090003 lb zero,0(s2) - 55ce: 0100 addi s0,sp,128 - 55d0: 0200 addi s0,sp,256 - 55d2: 4704 lw s1,8(a4) - 55d4: 10090003 lb zero,256(s2) - 55d8: 0100 addi s0,sp,128 - 55da: 0200 addi s0,sp,256 - 55dc: 4704 lw s1,8(a4) - 55de: 00090003 lb zero,0(s2) - 55e2: 0100 addi s0,sp,128 - 55e4: 0200 addi s0,sp,256 - 55e6: 5104 lw s1,32(a0) - 55e8: 10090003 lb zero,256(s2) - 55ec: 0100 addi s0,sp,128 - 55ee: 0200 addi s0,sp,256 - 55f0: 5104 lw s1,32(a0) - 55f2: 00090003 lb zero,0(s2) - 55f6: 0100 addi s0,sp,128 - 55f8: 0200 addi s0,sp,256 - 55fa: 5104 lw s1,32(a0) - 55fc: 00090003 lb zero,0(s2) - 5600: 0100 addi s0,sp,128 - 5602: 0200 addi s0,sp,256 - 5604: 5104 lw s1,32(a0) - 5606: 00090003 lb zero,0(s2) - 560a: 0100 addi s0,sp,128 - 560c: 0200 addi s0,sp,256 - 560e: 5104 lw s1,32(a0) - 5610: 00090003 lb zero,0(s2) - 5614: 0100 addi s0,sp,128 - 5616: 0200 addi s0,sp,256 - 5618: 5104 lw s1,32(a0) - 561a: 00090003 lb zero,0(s2) - 561e: 0100 addi s0,sp,128 - 5620: 0200 addi s0,sp,256 - 5622: 5104 lw s1,32(a0) - 5624: 00090003 lb zero,0(s2) - 5628: 0100 addi s0,sp,128 - 562a: 0200 addi s0,sp,256 - 562c: 5104 lw s1,32(a0) - 562e: 00090003 lb zero,0(s2) - 5632: 0100 addi s0,sp,128 - 5634: 0200 addi s0,sp,256 - 5636: 5104 lw s1,32(a0) - 5638: 00090003 lb zero,0(s2) - 563c: 0100 addi s0,sp,128 - 563e: 0200 addi s0,sp,256 - 5640: 5104 lw s1,32(a0) - 5642: 00090003 lb zero,0(s2) - 5646: 0100 addi s0,sp,128 - 5648: 0200 addi s0,sp,256 - 564a: 5104 lw s1,32(a0) - 564c: 00090003 lb zero,0(s2) - 5650: 0100 addi s0,sp,128 - 5652: 0200 addi s0,sp,256 - 5654: 5104 lw s1,32(a0) - 5656: 00090003 lb zero,0(s2) - 565a: 0100 addi s0,sp,128 - 565c: 0200 addi s0,sp,256 - 565e: 5104 lw s1,32(a0) - 5660: 00090003 lb zero,0(s2) - 5664: 0100 addi s0,sp,128 - 5666: 0200 addi s0,sp,256 - 5668: 5104 lw s1,32(a0) - 566a: 04090003 lb zero,64(s2) - 566e: 0100 addi s0,sp,128 - 5670: 0200 addi s0,sp,256 - 5672: 5104 lw s1,32(a0) - 5674: 00090003 lb zero,0(s2) - 5678: 0100 addi s0,sp,128 - 567a: 0200 addi s0,sp,256 - 567c: 5704 lw s1,40(a4) - 567e: 08090003 lb zero,128(s2) - 5682: 0100 addi s0,sp,128 - 5684: 0200 addi s0,sp,256 - 5686: 5704 lw s1,40(a4) - 5688: 1c090003 lb zero,448(s2) - 568c: 0100 addi s0,sp,128 - 568e: 0200 addi s0,sp,256 - 5690: 5704 lw s1,40(a4) - 5692: 00090003 lb zero,0(s2) - 5696: 0100 addi s0,sp,128 - 5698: 0200 addi s0,sp,256 - 569a: 5804 lw s1,48(s0) - 569c: 04090003 lb zero,64(s2) - 56a0: 0100 addi s0,sp,128 - 56a2: 0200 addi s0,sp,256 - 56a4: 5804 lw s1,48(s0) - 56a6: 10090003 lb zero,256(s2) - 56aa: 0100 addi s0,sp,128 - 56ac: 0200 addi s0,sp,256 - 56ae: 5804 lw s1,48(s0) - 56b0: 00090003 lb zero,0(s2) - 56b4: 0100 addi s0,sp,128 - 56b6: 0200 addi s0,sp,256 - 56b8: 5804 lw s1,48(s0) - 56ba: 00090003 lb zero,0(s2) - 56be: 0100 addi s0,sp,128 - 56c0: 0200 addi s0,sp,256 - 56c2: 5804 lw s1,48(s0) - 56c4: 00090003 lb zero,0(s2) - 56c8: 0100 addi s0,sp,128 - 56ca: 0200 addi s0,sp,256 - 56cc: 5804 lw s1,48(s0) - 56ce: 0c090003 lb zero,192(s2) - 56d2: 0100 addi s0,sp,128 - 56d4: 0200 addi s0,sp,256 - 56d6: 0204 addi s1,sp,256 - 56d8: 00090103 lb sp,0(s2) - 56dc: 0100 addi s0,sp,128 - 56de: 0200 addi s0,sp,256 - 56e0: 0204 addi s1,sp,256 - 56e2: 10090003 lb zero,256(s2) - 56e6: 0100 addi s0,sp,128 - 56e8: 0200 addi s0,sp,256 - 56ea: 0604 addi s1,sp,768 - 56ec: 04090003 lb zero,64(s2) - 56f0: 0100 addi s0,sp,128 - 56f2: 0200 addi s0,sp,256 - 56f4: 0604 addi s1,sp,768 - 56f6: 00090003 lb zero,0(s2) - 56fa: 0100 addi s0,sp,128 - 56fc: 0200 addi s0,sp,256 - 56fe: 0804 addi s1,sp,16 - 5700: 0c090003 lb zero,192(s2) - 5704: 0100 addi s0,sp,128 - 5706: 0200 addi s0,sp,256 - 5708: 0804 addi s1,sp,16 - 570a: 00090003 lb zero,0(s2) - 570e: 0100 addi s0,sp,128 - 5710: 0200 addi s0,sp,256 - 5712: 0804 addi s1,sp,16 - 5714: 00090003 lb zero,0(s2) - 5718: 0100 addi s0,sp,128 - 571a: 0200 addi s0,sp,256 - 571c: 0804 addi s1,sp,16 - 571e: 00090003 lb zero,0(s2) - 5722: 0100 addi s0,sp,128 - 5724: 0200 addi s0,sp,256 - 5726: 0a04 addi s1,sp,272 - 5728: 0c090003 lb zero,192(s2) - 572c: 0100 addi s0,sp,128 - 572e: 0200 addi s0,sp,256 - 5730: 0a04 addi s1,sp,272 - 5732: 00090003 lb zero,0(s2) - 5736: 0100 addi s0,sp,128 - 5738: 0200 addi s0,sp,256 - 573a: 0a04 addi s1,sp,272 - 573c: 00090003 lb zero,0(s2) - 5740: 0100 addi s0,sp,128 - 5742: 0200 addi s0,sp,256 - 5744: 0a04 addi s1,sp,272 - 5746: 10090003 lb zero,256(s2) - 574a: 0100 addi s0,sp,128 - 574c: 0200 addi s0,sp,256 - 574e: 0a04 addi s1,sp,272 - 5750: 0c090003 lb zero,192(s2) - 5754: 0100 addi s0,sp,128 - 5756: 0200 addi s0,sp,256 - 5758: 0a04 addi s1,sp,272 - 575a: 00090003 lb zero,0(s2) - 575e: 0100 addi s0,sp,128 - 5760: 0200 addi s0,sp,256 - 5762: 0a04 addi s1,sp,272 - 5764: 0c090003 lb zero,192(s2) - 5768: 0100 addi s0,sp,128 - 576a: 0200 addi s0,sp,256 - 576c: 0a04 addi s1,sp,272 - 576e: 04090003 lb zero,64(s2) - 5772: 0100 addi s0,sp,128 - 5774: 0200 addi s0,sp,256 - 5776: 0904 addi s1,sp,144 - 5778: 0c090003 lb zero,192(s2) - 577c: 0100 addi s0,sp,128 - 577e: 0200 addi s0,sp,256 - 5780: 0904 addi s1,sp,144 - 5782: 00090003 lb zero,0(s2) - 5786: 0100 addi s0,sp,128 - 5788: 0200 addi s0,sp,256 - 578a: 1804 addi s1,sp,48 - 578c: 0c090003 lb zero,192(s2) - 5790: 0100 addi s0,sp,128 - 5792: 0200 addi s0,sp,256 - 5794: 1804 addi s1,sp,48 - 5796: 10090003 lb zero,256(s2) - 579a: 0100 addi s0,sp,128 - 579c: 0200 addi s0,sp,256 - 579e: 1a04 addi s1,sp,304 - 57a0: 0c090003 lb zero,192(s2) - 57a4: 0100 addi s0,sp,128 - 57a6: 0200 addi s0,sp,256 - 57a8: 1a04 addi s1,sp,304 - 57aa: 00090003 lb zero,0(s2) - 57ae: 0100 addi s0,sp,128 - 57b0: 0200 addi s0,sp,256 - 57b2: 1a04 addi s1,sp,304 - 57b4: 00090003 lb zero,0(s2) - 57b8: 0100 addi s0,sp,128 - 57ba: 0200 addi s0,sp,256 - 57bc: 1a04 addi s1,sp,304 - 57be: 00090003 lb zero,0(s2) - 57c2: 0100 addi s0,sp,128 - 57c4: 0200 addi s0,sp,256 - 57c6: 1a04 addi s1,sp,304 - 57c8: 00090003 lb zero,0(s2) - 57cc: 0100 addi s0,sp,128 - 57ce: 0200 addi s0,sp,256 - 57d0: 1a04 addi s1,sp,304 - 57d2: 00090003 lb zero,0(s2) - 57d6: 0100 addi s0,sp,128 - 57d8: 0200 addi s0,sp,256 - 57da: 1a04 addi s1,sp,304 - 57dc: 00090003 lb zero,0(s2) - 57e0: 0100 addi s0,sp,128 - 57e2: 0200 addi s0,sp,256 - 57e4: 1a04 addi s1,sp,304 - 57e6: 00090003 lb zero,0(s2) - 57ea: 0100 addi s0,sp,128 - 57ec: 0200 addi s0,sp,256 - 57ee: 1a04 addi s1,sp,304 - 57f0: 00090003 lb zero,0(s2) - 57f4: 0100 addi s0,sp,128 - 57f6: 0200 addi s0,sp,256 - 57f8: 2204 fld fs1,0(a2) - 57fa: 08090003 lb zero,128(s2) - 57fe: 0100 addi s0,sp,128 - 5800: 0200 addi s0,sp,256 - 5802: 2204 fld fs1,0(a2) - 5804: 1c090003 lb zero,448(s2) - 5808: 0100 addi s0,sp,128 - 580a: 0200 addi s0,sp,256 - 580c: 2204 fld fs1,0(a2) - 580e: 00090003 lb zero,0(s2) - 5812: 0100 addi s0,sp,128 - 5814: 0200 addi s0,sp,256 - 5816: 2304 fld fs1,0(a4) - 5818: 04090003 lb zero,64(s2) - 581c: 0100 addi s0,sp,128 - 581e: 0200 addi s0,sp,256 - 5820: 2304 fld fs1,0(a4) - 5822: 00090003 lb zero,0(s2) - 5826: 0100 addi s0,sp,128 - 5828: 0200 addi s0,sp,256 - 582a: 2304 fld fs1,0(a4) + 41e6: 2304 fld fs1,0(a4) + 41e8: 08090003 lb zero,128(s2) + 41ec: 0100 addi s0,sp,128 + 41ee: 0200 addi s0,sp,256 + 41f0: 2304 fld fs1,0(a4) + 41f2: 00090003 lb zero,0(s2) + 41f6: 0100 addi s0,sp,128 + 41f8: 0200 addi s0,sp,256 + 41fa: 2204 fld fs1,0(a2) + 41fc: 08090003 lb zero,128(s2) + 4200: 0100 addi s0,sp,128 + 4202: 0200 addi s0,sp,256 + 4204: 2d04 fld fs1,24(a0) + 4206: 04090003 lb zero,64(s2) + 420a: 0100 addi s0,sp,128 + 420c: 0200 addi s0,sp,256 + 420e: 2d04 fld fs1,24(a0) + 4210: 00090003 lb zero,0(s2) + 4214: 0100 addi s0,sp,128 + 4216: 0200 addi s0,sp,256 + 4218: 2d04 fld fs1,24(a0) + 421a: 00090003 lb zero,0(s2) + 421e: 0100 addi s0,sp,128 + 4220: 0200 addi s0,sp,256 + 4222: 2d04 fld fs1,24(a0) + 4224: 00090003 lb zero,0(s2) + 4228: 0100 addi s0,sp,128 + 422a: 0200 addi s0,sp,256 + 422c: 2d04 fld fs1,24(a0) + 422e: 08090003 lb zero,128(s2) + 4232: 0100 addi s0,sp,128 + 4234: 0200 addi s0,sp,256 + 4236: 2d04 fld fs1,24(a0) + 4238: 00090003 lb zero,0(s2) + 423c: 0100 addi s0,sp,128 + 423e: 0200 addi s0,sp,256 + 4240: 3504 fld fs1,40(a0) + 4242: 08090003 lb zero,128(s2) + 4246: 0100 addi s0,sp,128 + 4248: 0200 addi s0,sp,256 + 424a: 3504 fld fs1,40(a0) + 424c: 00090003 lb zero,0(s2) + 4250: 0100 addi s0,sp,128 + 4252: 0200 addi s0,sp,256 + 4254: 3504 fld fs1,40(a0) + 4256: 00090003 lb zero,0(s2) + 425a: 0100 addi s0,sp,128 + 425c: 0200 addi s0,sp,256 + 425e: 3504 fld fs1,40(a0) + 4260: 00090003 lb zero,0(s2) + 4264: 0100 addi s0,sp,128 + 4266: 0200 addi s0,sp,256 + 4268: 3504 fld fs1,40(a0) + 426a: 08090003 lb zero,128(s2) + 426e: 0100 addi s0,sp,128 + 4270: 0200 addi s0,sp,256 + 4272: 3504 fld fs1,40(a0) + 4274: 00090003 lb zero,0(s2) + 4278: 0100 addi s0,sp,128 + 427a: 0306 slli t1,t1,0x1 + 427c: 0900 addi s0,sp,144 + 427e: 0014 0x14 + 4280: 0001 nop + 4282: 0402 c.slli64 s0 + 4284: 0641 addi a2,a2,16 + 4286: 04090003 lb zero,64(s2) + 428a: 0100 addi s0,sp,128 + 428c: 0200 addi s0,sp,256 + 428e: 4104 lw s1,0(a0) + 4290: 14090003 lb zero,320(s2) + 4294: 0100 addi s0,sp,128 + 4296: 0200 addi s0,sp,256 + 4298: 4104 lw s1,0(a0) + 429a: 00090003 lb zero,0(s2) + 429e: 0100 addi s0,sp,128 + 42a0: 0200 addi s0,sp,256 + 42a2: 4404 lw s1,8(s0) + 42a4: 0c090003 lb zero,192(s2) + 42a8: 0100 addi s0,sp,128 + 42aa: 0200 addi s0,sp,256 + 42ac: 4404 lw s1,8(s0) + 42ae: 1c090003 lb zero,448(s2) + 42b2: 0100 addi s0,sp,128 + 42b4: 0200 addi s0,sp,256 + 42b6: 4804 lw s1,16(s0) + 42b8: 08090003 lb zero,128(s2) + 42bc: 0100 addi s0,sp,128 + 42be: 0200 addi s0,sp,256 + 42c0: 4804 lw s1,16(s0) + 42c2: 10090003 lb zero,256(s2) + 42c6: 0100 addi s0,sp,128 + 42c8: 0200 addi s0,sp,256 + 42ca: 4704 lw s1,8(a4) + 42cc: 04090003 lb zero,64(s2) + 42d0: 0100 addi s0,sp,128 + 42d2: 0200 addi s0,sp,256 + 42d4: 4904 lw s1,16(a0) + 42d6: 04090003 lb zero,64(s2) + 42da: 0100 addi s0,sp,128 + 42dc: 0200 addi s0,sp,256 + 42de: 4904 lw s1,16(a0) + 42e0: 00090003 lb zero,0(s2) + 42e4: 0100 addi s0,sp,128 + 42e6: 0200 addi s0,sp,256 + 42e8: 0304 addi s1,sp,384 + 42ea: 10090003 lb zero,256(s2) + 42ee: 0100 addi s0,sp,128 + 42f0: 0306 slli t1,t1,0x1 + 42f2: 0900 addi s0,sp,144 + 42f4: 0014 0x14 + 42f6: 0001 nop + 42f8: 0402 c.slli64 s0 + 42fa: 0602 c.slli64 a2 + 42fc: 14090103 lb sp,320(s2) + 4300: 0100 addi s0,sp,128 + 4302: 0200 addi s0,sp,256 + 4304: 0204 addi s1,sp,256 + 4306: 00090003 lb zero,0(s2) + 430a: 0100 addi s0,sp,128 + 430c: 0200 addi s0,sp,256 + 430e: 0204 addi s1,sp,256 + 4310: 00090003 lb zero,0(s2) + 4314: 0100 addi s0,sp,128 + 4316: 0200 addi s0,sp,256 + 4318: 0204 addi s1,sp,256 + 431a: 00090003 lb zero,0(s2) + 431e: 0100 addi s0,sp,128 + 4320: 0200 addi s0,sp,256 + 4322: 0204 addi s1,sp,256 + 4324: 00090003 lb zero,0(s2) + 4328: 0100 addi s0,sp,128 + 432a: 0200 addi s0,sp,256 + 432c: 0204 addi s1,sp,256 + 432e: 00090003 lb zero,0(s2) + 4332: 0100 addi s0,sp,128 + 4334: 0200 addi s0,sp,256 + 4336: 0204 addi s1,sp,256 + 4338: 00090003 lb zero,0(s2) + 433c: 0100 addi s0,sp,128 + 433e: 0200 addi s0,sp,256 + 4340: 0204 addi s1,sp,256 + 4342: 00090003 lb zero,0(s2) + 4346: 0100 addi s0,sp,128 + 4348: 0200 addi s0,sp,256 + 434a: 0204 addi s1,sp,256 + 434c: 00090003 lb zero,0(s2) + 4350: 0100 addi s0,sp,128 + 4352: 0200 addi s0,sp,256 + 4354: 0204 addi s1,sp,256 + 4356: 00090003 lb zero,0(s2) + 435a: 0100 addi s0,sp,128 + 435c: 0200 addi s0,sp,256 + 435e: 0204 addi s1,sp,256 + 4360: 00090003 lb zero,0(s2) + 4364: 0100 addi s0,sp,128 + 4366: 0200 addi s0,sp,256 + 4368: 0204 addi s1,sp,256 + 436a: 00090003 lb zero,0(s2) + 436e: 0100 addi s0,sp,128 + 4370: 0200 addi s0,sp,256 + 4372: 0204 addi s1,sp,256 + 4374: 00090003 lb zero,0(s2) + 4378: 0100 addi s0,sp,128 + 437a: 0200 addi s0,sp,256 + 437c: 0204 addi s1,sp,256 + 437e: 04090003 lb zero,64(s2) + 4382: 0100 addi s0,sp,128 + 4384: 0200 addi s0,sp,256 + 4386: 0204 addi s1,sp,256 + 4388: 10090003 lb zero,256(s2) + 438c: 0100 addi s0,sp,128 + 438e: 0200 addi s0,sp,256 + 4390: 0204 addi s1,sp,256 + 4392: 00090003 lb zero,0(s2) + 4396: 0100 addi s0,sp,128 + 4398: 0200 addi s0,sp,256 + 439a: 0204 addi s1,sp,256 + 439c: 04090003 lb zero,64(s2) + 43a0: 0100 addi s0,sp,128 + 43a2: 0200 addi s0,sp,256 + 43a4: 0204 addi s1,sp,256 + 43a6: 10090003 lb zero,256(s2) + 43aa: 0100 addi s0,sp,128 + 43ac: 0200 addi s0,sp,256 + 43ae: 0204 addi s1,sp,256 + 43b0: 00090003 lb zero,0(s2) + 43b4: 0100 addi s0,sp,128 + 43b6: 0200 addi s0,sp,256 + 43b8: 0204 addi s1,sp,256 + 43ba: 04090003 lb zero,64(s2) + 43be: 0100 addi s0,sp,128 + 43c0: 0200 addi s0,sp,256 + 43c2: 0204 addi s1,sp,256 + 43c4: 10090003 lb zero,256(s2) + 43c8: 0100 addi s0,sp,128 + 43ca: 0200 addi s0,sp,256 + 43cc: 0204 addi s1,sp,256 + 43ce: 00090003 lb zero,0(s2) + 43d2: 0100 addi s0,sp,128 + 43d4: 0200 addi s0,sp,256 + 43d6: 0204 addi s1,sp,256 + 43d8: 00090003 lb zero,0(s2) + 43dc: 0100 addi s0,sp,128 + 43de: 0200 addi s0,sp,256 + 43e0: 0904 addi s1,sp,144 + 43e2: 04090003 lb zero,64(s2) + 43e6: 0100 addi s0,sp,128 + 43e8: 0200 addi s0,sp,256 + 43ea: 0b04 addi s1,sp,400 + 43ec: 04090003 lb zero,64(s2) + 43f0: 0100 addi s0,sp,128 + 43f2: 0200 addi s0,sp,256 + 43f4: 0b04 addi s1,sp,400 + 43f6: 08090003 lb zero,128(s2) + 43fa: 0100 addi s0,sp,128 + 43fc: 0200 addi s0,sp,256 + 43fe: 0b04 addi s1,sp,400 + 4400: 24090003 lb zero,576(s2) + 4404: 0100 addi s0,sp,128 + 4406: 0200 addi s0,sp,256 + 4408: 0b04 addi s1,sp,400 + 440a: 00090003 lb zero,0(s2) + 440e: 0100 addi s0,sp,128 + 4410: 0200 addi s0,sp,256 + 4412: 0b04 addi s1,sp,400 + 4414: 00090003 lb zero,0(s2) + 4418: 0100 addi s0,sp,128 + 441a: 0200 addi s0,sp,256 + 441c: 0b04 addi s1,sp,400 + 441e: 00090003 lb zero,0(s2) + 4422: 0100 addi s0,sp,128 + 4424: 0200 addi s0,sp,256 + 4426: 0b04 addi s1,sp,400 + 4428: 00090003 lb zero,0(s2) + 442c: 0100 addi s0,sp,128 + 442e: 0200 addi s0,sp,256 + 4430: 0b04 addi s1,sp,400 + 4432: 00090003 lb zero,0(s2) + 4436: 0100 addi s0,sp,128 + 4438: 0200 addi s0,sp,256 + 443a: 0b04 addi s1,sp,400 + 443c: 00090003 lb zero,0(s2) + 4440: 0100 addi s0,sp,128 + 4442: 0200 addi s0,sp,256 + 4444: 0b04 addi s1,sp,400 + 4446: 00090003 lb zero,0(s2) + 444a: 0100 addi s0,sp,128 + 444c: 0200 addi s0,sp,256 + 444e: 0b04 addi s1,sp,400 + 4450: 00090003 lb zero,0(s2) + 4454: 0100 addi s0,sp,128 + 4456: 0200 addi s0,sp,256 + 4458: 0b04 addi s1,sp,400 + 445a: 00090003 lb zero,0(s2) + 445e: 0100 addi s0,sp,128 + 4460: 0200 addi s0,sp,256 + 4462: 0b04 addi s1,sp,400 + 4464: 00090003 lb zero,0(s2) + 4468: 0100 addi s0,sp,128 + 446a: 0200 addi s0,sp,256 + 446c: 0b04 addi s1,sp,400 + 446e: 04090003 lb zero,64(s2) + 4472: 0100 addi s0,sp,128 + 4474: 0200 addi s0,sp,256 + 4476: 0b04 addi s1,sp,400 + 4478: 14090003 lb zero,320(s2) + 447c: 0100 addi s0,sp,128 + 447e: 0200 addi s0,sp,256 + 4480: 0b04 addi s1,sp,400 + 4482: 00090003 lb zero,0(s2) + 4486: 0100 addi s0,sp,128 + 4488: 0200 addi s0,sp,256 + 448a: 0b04 addi s1,sp,400 + 448c: 00090003 lb zero,0(s2) + 4490: 0100 addi s0,sp,128 + 4492: 0200 addi s0,sp,256 + 4494: 0c04 addi s1,sp,528 + 4496: 04090003 lb zero,64(s2) + 449a: 0100 addi s0,sp,128 + 449c: 0200 addi s0,sp,256 + 449e: 0e04 addi s1,sp,784 + 44a0: 08090003 lb zero,128(s2) + 44a4: 0100 addi s0,sp,128 + 44a6: 0200 addi s0,sp,256 + 44a8: 0e04 addi s1,sp,784 + 44aa: 10090003 lb zero,256(s2) + 44ae: 0100 addi s0,sp,128 + 44b0: 0200 addi s0,sp,256 + 44b2: 0e04 addi s1,sp,784 + 44b4: 20090003 lb zero,512(s2) + 44b8: 0100 addi s0,sp,128 + 44ba: 0200 addi s0,sp,256 + 44bc: 0e04 addi s1,sp,784 + 44be: 00090003 lb zero,0(s2) + 44c2: 0100 addi s0,sp,128 + 44c4: 0200 addi s0,sp,256 + 44c6: 0e04 addi s1,sp,784 + 44c8: 00090003 lb zero,0(s2) + 44cc: 0100 addi s0,sp,128 + 44ce: 0200 addi s0,sp,256 + 44d0: 0e04 addi s1,sp,784 + 44d2: 00090003 lb zero,0(s2) + 44d6: 0100 addi s0,sp,128 + 44d8: 0200 addi s0,sp,256 + 44da: 0e04 addi s1,sp,784 + 44dc: 00090003 lb zero,0(s2) + 44e0: 0100 addi s0,sp,128 + 44e2: 0200 addi s0,sp,256 + 44e4: 0e04 addi s1,sp,784 + 44e6: 00090003 lb zero,0(s2) + 44ea: 0100 addi s0,sp,128 + 44ec: 0200 addi s0,sp,256 + 44ee: 0e04 addi s1,sp,784 + 44f0: 00090003 lb zero,0(s2) + 44f4: 0100 addi s0,sp,128 + 44f6: 0200 addi s0,sp,256 + 44f8: 0e04 addi s1,sp,784 + 44fa: 00090003 lb zero,0(s2) + 44fe: 0100 addi s0,sp,128 + 4500: 0200 addi s0,sp,256 + 4502: 0e04 addi s1,sp,784 + 4504: 00090003 lb zero,0(s2) + 4508: 0100 addi s0,sp,128 + 450a: 0200 addi s0,sp,256 + 450c: 0e04 addi s1,sp,784 + 450e: 04090003 lb zero,64(s2) + 4512: 0100 addi s0,sp,128 + 4514: 0200 addi s0,sp,256 + 4516: 0e04 addi s1,sp,784 + 4518: 00090003 lb zero,0(s2) + 451c: 0100 addi s0,sp,128 + 451e: 0200 addi s0,sp,256 + 4520: 0e04 addi s1,sp,784 + 4522: 04090003 lb zero,64(s2) + 4526: 0100 addi s0,sp,128 + 4528: 0200 addi s0,sp,256 + 452a: 0e04 addi s1,sp,784 + 452c: 10090003 lb zero,256(s2) + 4530: 0100 addi s0,sp,128 + 4532: 0200 addi s0,sp,256 + 4534: 0e04 addi s1,sp,784 + 4536: 00090003 lb zero,0(s2) + 453a: 0100 addi s0,sp,128 + 453c: 0200 addi s0,sp,256 + 453e: 0e04 addi s1,sp,784 + 4540: 00090003 lb zero,0(s2) + 4544: 0100 addi s0,sp,128 + 4546: 0200 addi s0,sp,256 + 4548: 0f04 addi s1,sp,912 + 454a: 04090003 lb zero,64(s2) + 454e: 0100 addi s0,sp,128 + 4550: 0200 addi s0,sp,256 + 4552: 1104 addi s1,sp,160 + 4554: 04090003 lb zero,64(s2) + 4558: 0100 addi s0,sp,128 + 455a: 0200 addi s0,sp,256 + 455c: 1104 addi s1,sp,160 + 455e: 18090003 lb zero,384(s2) + 4562: 0100 addi s0,sp,128 + 4564: 0200 addi s0,sp,256 + 4566: 1104 addi s1,sp,160 + 4568: 0c090003 lb zero,192(s2) + 456c: 0100 addi s0,sp,128 + 456e: 0200 addi s0,sp,256 + 4570: 1104 addi s1,sp,160 + 4572: 00090003 lb zero,0(s2) + 4576: 0100 addi s0,sp,128 + 4578: 0200 addi s0,sp,256 + 457a: 1104 addi s1,sp,160 + 457c: 00090003 lb zero,0(s2) + 4580: 0100 addi s0,sp,128 + 4582: 0200 addi s0,sp,256 + 4584: 1104 addi s1,sp,160 + 4586: 00090003 lb zero,0(s2) + 458a: 0100 addi s0,sp,128 + 458c: 0200 addi s0,sp,256 + 458e: 1104 addi s1,sp,160 + 4590: 00090003 lb zero,0(s2) + 4594: 0100 addi s0,sp,128 + 4596: 0200 addi s0,sp,256 + 4598: 1104 addi s1,sp,160 + 459a: 00090003 lb zero,0(s2) + 459e: 0100 addi s0,sp,128 + 45a0: 0200 addi s0,sp,256 + 45a2: 1104 addi s1,sp,160 + 45a4: 00090003 lb zero,0(s2) + 45a8: 0100 addi s0,sp,128 + 45aa: 0200 addi s0,sp,256 + 45ac: 1104 addi s1,sp,160 + 45ae: 00090003 lb zero,0(s2) + 45b2: 0100 addi s0,sp,128 + 45b4: 0200 addi s0,sp,256 + 45b6: 1104 addi s1,sp,160 + 45b8: 00090003 lb zero,0(s2) + 45bc: 0100 addi s0,sp,128 + 45be: 0200 addi s0,sp,256 + 45c0: 1104 addi s1,sp,160 + 45c2: 00090003 lb zero,0(s2) + 45c6: 0100 addi s0,sp,128 + 45c8: 0200 addi s0,sp,256 + 45ca: 1104 addi s1,sp,160 + 45cc: 00090003 lb zero,0(s2) + 45d0: 0100 addi s0,sp,128 + 45d2: 0200 addi s0,sp,256 + 45d4: 1104 addi s1,sp,160 + 45d6: 04090003 lb zero,64(s2) + 45da: 0100 addi s0,sp,128 + 45dc: 0200 addi s0,sp,256 + 45de: 1104 addi s1,sp,160 + 45e0: 14090003 lb zero,320(s2) + 45e4: 0100 addi s0,sp,128 + 45e6: 0200 addi s0,sp,256 + 45e8: 1104 addi s1,sp,160 + 45ea: 00090003 lb zero,0(s2) + 45ee: 0100 addi s0,sp,128 + 45f0: 0200 addi s0,sp,256 + 45f2: 1104 addi s1,sp,160 + 45f4: 00090003 lb zero,0(s2) + 45f8: 0100 addi s0,sp,128 + 45fa: 0200 addi s0,sp,256 + 45fc: 1204 addi s1,sp,288 + 45fe: 04090003 lb zero,64(s2) + 4602: 0100 addi s0,sp,128 + 4604: 0200 addi s0,sp,256 + 4606: 1404 addi s1,sp,544 + 4608: 04090003 lb zero,64(s2) + 460c: 0100 addi s0,sp,128 + 460e: 0200 addi s0,sp,256 + 4610: 1404 addi s1,sp,544 + 4612: 18090003 lb zero,384(s2) + 4616: 0100 addi s0,sp,128 + 4618: 0200 addi s0,sp,256 + 461a: 1404 addi s1,sp,544 + 461c: 1c090003 lb zero,448(s2) + 4620: 0100 addi s0,sp,128 + 4622: 0200 addi s0,sp,256 + 4624: 1404 addi s1,sp,544 + 4626: 00090003 lb zero,0(s2) + 462a: 0100 addi s0,sp,128 + 462c: 0200 addi s0,sp,256 + 462e: 1404 addi s1,sp,544 + 4630: 00090003 lb zero,0(s2) + 4634: 0100 addi s0,sp,128 + 4636: 0200 addi s0,sp,256 + 4638: 1404 addi s1,sp,544 + 463a: 00090003 lb zero,0(s2) + 463e: 0100 addi s0,sp,128 + 4640: 0200 addi s0,sp,256 + 4642: 1404 addi s1,sp,544 + 4644: 00090003 lb zero,0(s2) + 4648: 0100 addi s0,sp,128 + 464a: 0200 addi s0,sp,256 + 464c: 1404 addi s1,sp,544 + 464e: 00090003 lb zero,0(s2) + 4652: 0100 addi s0,sp,128 + 4654: 0200 addi s0,sp,256 + 4656: 1404 addi s1,sp,544 + 4658: 00090003 lb zero,0(s2) + 465c: 0100 addi s0,sp,128 + 465e: 0200 addi s0,sp,256 + 4660: 1404 addi s1,sp,544 + 4662: 00090003 lb zero,0(s2) + 4666: 0100 addi s0,sp,128 + 4668: 0200 addi s0,sp,256 + 466a: 1404 addi s1,sp,544 + 466c: 00090003 lb zero,0(s2) + 4670: 0100 addi s0,sp,128 + 4672: 0200 addi s0,sp,256 + 4674: 1404 addi s1,sp,544 + 4676: 00090003 lb zero,0(s2) + 467a: 0100 addi s0,sp,128 + 467c: 0200 addi s0,sp,256 + 467e: 1404 addi s1,sp,544 + 4680: 00090003 lb zero,0(s2) + 4684: 0100 addi s0,sp,128 + 4686: 0200 addi s0,sp,256 + 4688: 1404 addi s1,sp,544 + 468a: 04090003 lb zero,64(s2) + 468e: 0100 addi s0,sp,128 + 4690: 0200 addi s0,sp,256 + 4692: 1404 addi s1,sp,544 + 4694: 14090003 lb zero,320(s2) + 4698: 0100 addi s0,sp,128 + 469a: 0200 addi s0,sp,256 + 469c: 1404 addi s1,sp,544 + 469e: 00090003 lb zero,0(s2) + 46a2: 0100 addi s0,sp,128 + 46a4: 0200 addi s0,sp,256 + 46a6: 1404 addi s1,sp,544 + 46a8: 00090003 lb zero,0(s2) + 46ac: 0100 addi s0,sp,128 + 46ae: 0200 addi s0,sp,256 + 46b0: 1504 addi s1,sp,672 + 46b2: 04090003 lb zero,64(s2) + 46b6: 0100 addi s0,sp,128 + 46b8: 0200 addi s0,sp,256 + 46ba: 1704 addi s1,sp,928 + 46bc: 04090003 lb zero,64(s2) + 46c0: 0100 addi s0,sp,128 + 46c2: 0200 addi s0,sp,256 + 46c4: 1704 addi s1,sp,928 + 46c6: 14090003 lb zero,320(s2) + 46ca: 0100 addi s0,sp,128 + 46cc: 0200 addi s0,sp,256 + 46ce: 1704 addi s1,sp,928 + 46d0: 20090003 lb zero,512(s2) + 46d4: 0100 addi s0,sp,128 + 46d6: 0200 addi s0,sp,256 + 46d8: 1704 addi s1,sp,928 + 46da: 00090003 lb zero,0(s2) + 46de: 0100 addi s0,sp,128 + 46e0: 0200 addi s0,sp,256 + 46e2: 1704 addi s1,sp,928 + 46e4: 00090003 lb zero,0(s2) + 46e8: 0100 addi s0,sp,128 + 46ea: 0200 addi s0,sp,256 + 46ec: 1704 addi s1,sp,928 + 46ee: 00090003 lb zero,0(s2) + 46f2: 0100 addi s0,sp,128 + 46f4: 0200 addi s0,sp,256 + 46f6: 1704 addi s1,sp,928 + 46f8: 00090003 lb zero,0(s2) + 46fc: 0100 addi s0,sp,128 + 46fe: 0200 addi s0,sp,256 + 4700: 1704 addi s1,sp,928 + 4702: 00090003 lb zero,0(s2) + 4706: 0100 addi s0,sp,128 + 4708: 0200 addi s0,sp,256 + 470a: 1704 addi s1,sp,928 + 470c: 00090003 lb zero,0(s2) + 4710: 0100 addi s0,sp,128 + 4712: 0200 addi s0,sp,256 + 4714: 1704 addi s1,sp,928 + 4716: 00090003 lb zero,0(s2) + 471a: 0100 addi s0,sp,128 + 471c: 0200 addi s0,sp,256 + 471e: 1704 addi s1,sp,928 + 4720: 00090003 lb zero,0(s2) + 4724: 0100 addi s0,sp,128 + 4726: 0200 addi s0,sp,256 + 4728: 1704 addi s1,sp,928 + 472a: 00090003 lb zero,0(s2) + 472e: 0100 addi s0,sp,128 + 4730: 0200 addi s0,sp,256 + 4732: 1704 addi s1,sp,928 + 4734: 00090003 lb zero,0(s2) + 4738: 0100 addi s0,sp,128 + 473a: 0200 addi s0,sp,256 + 473c: 1704 addi s1,sp,928 + 473e: 04090003 lb zero,64(s2) + 4742: 0100 addi s0,sp,128 + 4744: 0200 addi s0,sp,256 + 4746: 1704 addi s1,sp,928 + 4748: 14090003 lb zero,320(s2) + 474c: 0100 addi s0,sp,128 + 474e: 0200 addi s0,sp,256 + 4750: 1704 addi s1,sp,928 + 4752: 00090003 lb zero,0(s2) + 4756: 0100 addi s0,sp,128 + 4758: 0200 addi s0,sp,256 + 475a: 1704 addi s1,sp,928 + 475c: 00090003 lb zero,0(s2) + 4760: 0100 addi s0,sp,128 + 4762: 0200 addi s0,sp,256 + 4764: 1804 addi s1,sp,48 + 4766: 04090003 lb zero,64(s2) + 476a: 0100 addi s0,sp,128 + 476c: 0200 addi s0,sp,256 + 476e: 1a04 addi s1,sp,304 + 4770: 04090003 lb zero,64(s2) + 4774: 0100 addi s0,sp,128 + 4776: 0200 addi s0,sp,256 + 4778: 1a04 addi s1,sp,304 + 477a: 08090003 lb zero,128(s2) + 477e: 0100 addi s0,sp,128 + 4780: 0200 addi s0,sp,256 + 4782: 1a04 addi s1,sp,304 + 4784: 28090003 lb zero,640(s2) + 4788: 0100 addi s0,sp,128 + 478a: 0200 addi s0,sp,256 + 478c: 1a04 addi s1,sp,304 + 478e: 00090003 lb zero,0(s2) + 4792: 0100 addi s0,sp,128 + 4794: 0200 addi s0,sp,256 + 4796: 1a04 addi s1,sp,304 + 4798: 00090003 lb zero,0(s2) + 479c: 0100 addi s0,sp,128 + 479e: 0200 addi s0,sp,256 + 47a0: 1a04 addi s1,sp,304 + 47a2: 00090003 lb zero,0(s2) + 47a6: 0100 addi s0,sp,128 + 47a8: 0200 addi s0,sp,256 + 47aa: 1a04 addi s1,sp,304 + 47ac: 00090003 lb zero,0(s2) + 47b0: 0100 addi s0,sp,128 + 47b2: 0200 addi s0,sp,256 + 47b4: 1a04 addi s1,sp,304 + 47b6: 00090003 lb zero,0(s2) + 47ba: 0100 addi s0,sp,128 + 47bc: 0200 addi s0,sp,256 + 47be: 1a04 addi s1,sp,304 + 47c0: 00090003 lb zero,0(s2) + 47c4: 0100 addi s0,sp,128 + 47c6: 0200 addi s0,sp,256 + 47c8: 1a04 addi s1,sp,304 + 47ca: 00090003 lb zero,0(s2) + 47ce: 0100 addi s0,sp,128 + 47d0: 0200 addi s0,sp,256 + 47d2: 1a04 addi s1,sp,304 + 47d4: 00090003 lb zero,0(s2) + 47d8: 0100 addi s0,sp,128 + 47da: 0200 addi s0,sp,256 + 47dc: 1a04 addi s1,sp,304 + 47de: 00090003 lb zero,0(s2) + 47e2: 0100 addi s0,sp,128 + 47e4: 0200 addi s0,sp,256 + 47e6: 1a04 addi s1,sp,304 + 47e8: 00090003 lb zero,0(s2) + 47ec: 0100 addi s0,sp,128 + 47ee: 0200 addi s0,sp,256 + 47f0: 1a04 addi s1,sp,304 + 47f2: 00090003 lb zero,0(s2) + 47f6: 0100 addi s0,sp,128 + 47f8: 0200 addi s0,sp,256 + 47fa: 1a04 addi s1,sp,304 + 47fc: 00090003 lb zero,0(s2) + 4800: 0100 addi s0,sp,128 + 4802: 0200 addi s0,sp,256 + 4804: 1a04 addi s1,sp,304 + 4806: 00090003 lb zero,0(s2) + 480a: 0100 addi s0,sp,128 + 480c: 0200 addi s0,sp,256 + 480e: 1a04 addi s1,sp,304 + 4810: 10090003 lb zero,256(s2) + 4814: 0100 addi s0,sp,128 + 4816: 0200 addi s0,sp,256 + 4818: 1a04 addi s1,sp,304 + 481a: 00090003 lb zero,0(s2) + 481e: 0100 addi s0,sp,128 + 4820: 0200 addi s0,sp,256 + 4822: 1a04 addi s1,sp,304 + 4824: 04090003 lb zero,64(s2) + 4828: 0100 addi s0,sp,128 + 482a: 0200 addi s0,sp,256 + 482c: 1a04 addi s1,sp,304 + 482e: 00090003 lb zero,0(s2) + 4832: 0100 addi s0,sp,128 + 4834: 0200 addi s0,sp,256 + 4836: 1a04 addi s1,sp,304 + 4838: 04090003 lb zero,64(s2) + 483c: 0100 addi s0,sp,128 + 483e: 0200 addi s0,sp,256 + 4840: 1a04 addi s1,sp,304 + 4842: 00090003 lb zero,0(s2) + 4846: 0100 addi s0,sp,128 + 4848: 0200 addi s0,sp,256 + 484a: 1a04 addi s1,sp,304 + 484c: 00090003 lb zero,0(s2) + 4850: 0100 addi s0,sp,128 + 4852: 0200 addi s0,sp,256 + 4854: 1a04 addi s1,sp,304 + 4856: 00090003 lb zero,0(s2) + 485a: 0100 addi s0,sp,128 + 485c: 0200 addi s0,sp,256 + 485e: 1a04 addi s1,sp,304 + 4860: 00090003 lb zero,0(s2) + 4864: 0100 addi s0,sp,128 + 4866: 0200 addi s0,sp,256 + 4868: 1a04 addi s1,sp,304 + 486a: 00090003 lb zero,0(s2) + 486e: 0100 addi s0,sp,128 + 4870: 0200 addi s0,sp,256 + 4872: 1a04 addi s1,sp,304 + 4874: 0c090003 lb zero,192(s2) + 4878: 0100 addi s0,sp,128 + 487a: 0200 addi s0,sp,256 + 487c: 1a04 addi s1,sp,304 + 487e: 0c090003 lb zero,192(s2) + 4882: 0100 addi s0,sp,128 + 4884: 0200 addi s0,sp,256 + 4886: 1a04 addi s1,sp,304 + 4888: 24090003 lb zero,576(s2) + 488c: 0100 addi s0,sp,128 + 488e: 0200 addi s0,sp,256 + 4890: 1a04 addi s1,sp,304 + 4892: 00090003 lb zero,0(s2) + 4896: 0100 addi s0,sp,128 + 4898: 0200 addi s0,sp,256 + 489a: 1a04 addi s1,sp,304 + 489c: 08090003 lb zero,128(s2) + 48a0: 0100 addi s0,sp,128 + 48a2: 0200 addi s0,sp,256 + 48a4: 1a04 addi s1,sp,304 + 48a6: 00090003 lb zero,0(s2) + 48aa: 0100 addi s0,sp,128 + 48ac: 0200 addi s0,sp,256 + 48ae: 1a04 addi s1,sp,304 + 48b0: 00090003 lb zero,0(s2) + 48b4: 0100 addi s0,sp,128 + 48b6: 0200 addi s0,sp,256 + 48b8: 1a04 addi s1,sp,304 + 48ba: 00090003 lb zero,0(s2) + 48be: 0100 addi s0,sp,128 + 48c0: 0200 addi s0,sp,256 + 48c2: 1a04 addi s1,sp,304 + 48c4: 00090003 lb zero,0(s2) + 48c8: 0100 addi s0,sp,128 + 48ca: 0200 addi s0,sp,256 + 48cc: 1a04 addi s1,sp,304 + 48ce: 00090003 lb zero,0(s2) + 48d2: 0100 addi s0,sp,128 + 48d4: 0200 addi s0,sp,256 + 48d6: 1a04 addi s1,sp,304 + 48d8: 00090003 lb zero,0(s2) + 48dc: 0100 addi s0,sp,128 + 48de: 0200 addi s0,sp,256 + 48e0: 1a04 addi s1,sp,304 + 48e2: 0c090003 lb zero,192(s2) + 48e6: 0100 addi s0,sp,128 + 48e8: 0200 addi s0,sp,256 + 48ea: 1a04 addi s1,sp,304 + 48ec: 04090003 lb zero,64(s2) + 48f0: 0100 addi s0,sp,128 + 48f2: 0200 addi s0,sp,256 + 48f4: 1a04 addi s1,sp,304 + 48f6: 00090003 lb zero,0(s2) + 48fa: 0100 addi s0,sp,128 + 48fc: 0200 addi s0,sp,256 + 48fe: 1a04 addi s1,sp,304 + 4900: 0c090003 lb zero,192(s2) + 4904: 0100 addi s0,sp,128 + 4906: 0200 addi s0,sp,256 + 4908: 1a04 addi s1,sp,304 + 490a: 00090003 lb zero,0(s2) + 490e: 0100 addi s0,sp,128 + 4910: 0200 addi s0,sp,256 + 4912: 1a04 addi s1,sp,304 + 4914: 00090003 lb zero,0(s2) + 4918: 0100 addi s0,sp,128 + 491a: 0200 addi s0,sp,256 + 491c: 1a04 addi s1,sp,304 + 491e: 00090003 lb zero,0(s2) + 4922: 0100 addi s0,sp,128 + 4924: 0200 addi s0,sp,256 + 4926: 1a04 addi s1,sp,304 + 4928: 00090003 lb zero,0(s2) + 492c: 0100 addi s0,sp,128 + 492e: 0200 addi s0,sp,256 + 4930: 1a04 addi s1,sp,304 + 4932: 00090003 lb zero,0(s2) + 4936: 0100 addi s0,sp,128 + 4938: 0200 addi s0,sp,256 + 493a: 1a04 addi s1,sp,304 + 493c: 00090003 lb zero,0(s2) + 4940: 0100 addi s0,sp,128 + 4942: 0200 addi s0,sp,256 + 4944: 1a04 addi s1,sp,304 + 4946: 00090003 lb zero,0(s2) + 494a: 0100 addi s0,sp,128 + 494c: 0200 addi s0,sp,256 + 494e: 1a04 addi s1,sp,304 + 4950: 08090003 lb zero,128(s2) + 4954: 0100 addi s0,sp,128 + 4956: 0200 addi s0,sp,256 + 4958: 1a04 addi s1,sp,304 + 495a: 00090003 lb zero,0(s2) + 495e: 0100 addi s0,sp,128 + 4960: 0200 addi s0,sp,256 + 4962: 1a04 addi s1,sp,304 + 4964: 04090003 lb zero,64(s2) + 4968: 0100 addi s0,sp,128 + 496a: 0200 addi s0,sp,256 + 496c: 1a04 addi s1,sp,304 + 496e: 00090003 lb zero,0(s2) + 4972: 0100 addi s0,sp,128 + 4974: 0200 addi s0,sp,256 + 4976: 1a04 addi s1,sp,304 + 4978: 2c090003 lb zero,704(s2) + 497c: 0100 addi s0,sp,128 + 497e: 0200 addi s0,sp,256 + 4980: 1a04 addi s1,sp,304 + 4982: 00090003 lb zero,0(s2) + 4986: 0100 addi s0,sp,128 + 4988: 0200 addi s0,sp,256 + 498a: 1a04 addi s1,sp,304 + 498c: 00090003 lb zero,0(s2) + 4990: 0100 addi s0,sp,128 + 4992: 0200 addi s0,sp,256 + 4994: 1a04 addi s1,sp,304 + 4996: 00090003 lb zero,0(s2) + 499a: 0100 addi s0,sp,128 + 499c: 0200 addi s0,sp,256 + 499e: 1a04 addi s1,sp,304 + 49a0: 00090003 lb zero,0(s2) + 49a4: 0100 addi s0,sp,128 + 49a6: 0200 addi s0,sp,256 + 49a8: 1a04 addi s1,sp,304 + 49aa: 00090003 lb zero,0(s2) + 49ae: 0100 addi s0,sp,128 + 49b0: 0200 addi s0,sp,256 + 49b2: 1a04 addi s1,sp,304 + 49b4: 00090003 lb zero,0(s2) + 49b8: 0100 addi s0,sp,128 + 49ba: 0200 addi s0,sp,256 + 49bc: 1a04 addi s1,sp,304 + 49be: 00090003 lb zero,0(s2) + 49c2: 0100 addi s0,sp,128 + 49c4: 0200 addi s0,sp,256 + 49c6: 1a04 addi s1,sp,304 + 49c8: 00090003 lb zero,0(s2) + 49cc: 0100 addi s0,sp,128 + 49ce: 0200 addi s0,sp,256 + 49d0: 1a04 addi s1,sp,304 + 49d2: 00090003 lb zero,0(s2) + 49d6: 0100 addi s0,sp,128 + 49d8: 0200 addi s0,sp,256 + 49da: 1a04 addi s1,sp,304 + 49dc: 00090003 lb zero,0(s2) + 49e0: 0100 addi s0,sp,128 + 49e2: 0200 addi s0,sp,256 + 49e4: 1a04 addi s1,sp,304 + 49e6: 0c090003 lb zero,192(s2) + 49ea: 0100 addi s0,sp,128 + 49ec: 0200 addi s0,sp,256 + 49ee: 1a04 addi s1,sp,304 + 49f0: 0c090003 lb zero,192(s2) + 49f4: 0100 addi s0,sp,128 + 49f6: 0200 addi s0,sp,256 + 49f8: 1a04 addi s1,sp,304 + 49fa: 00090003 lb zero,0(s2) + 49fe: 0100 addi s0,sp,128 + 4a00: 0200 addi s0,sp,256 + 4a02: 1a04 addi s1,sp,304 + 4a04: 00090003 lb zero,0(s2) + 4a08: 0100 addi s0,sp,128 + 4a0a: 0200 addi s0,sp,256 + 4a0c: 1b04 addi s1,sp,432 + 4a0e: 04090003 lb zero,64(s2) + 4a12: 0100 addi s0,sp,128 + 4a14: 0200 addi s0,sp,256 + 4a16: 1d04 addi s1,sp,688 + 4a18: 04090003 lb zero,64(s2) + 4a1c: 0100 addi s0,sp,128 + 4a1e: 0200 addi s0,sp,256 + 4a20: 1d04 addi s1,sp,688 + 4a22: 1c090003 lb zero,448(s2) + 4a26: 0100 addi s0,sp,128 + 4a28: 0200 addi s0,sp,256 + 4a2a: 1d04 addi s1,sp,688 + 4a2c: 14090003 lb zero,320(s2) + 4a30: 0100 addi s0,sp,128 + 4a32: 0200 addi s0,sp,256 + 4a34: 1d04 addi s1,sp,688 + 4a36: 00090003 lb zero,0(s2) + 4a3a: 0100 addi s0,sp,128 + 4a3c: 0200 addi s0,sp,256 + 4a3e: 1d04 addi s1,sp,688 + 4a40: 00090003 lb zero,0(s2) + 4a44: 0100 addi s0,sp,128 + 4a46: 0200 addi s0,sp,256 + 4a48: 1d04 addi s1,sp,688 + 4a4a: 00090003 lb zero,0(s2) + 4a4e: 0100 addi s0,sp,128 + 4a50: 0200 addi s0,sp,256 + 4a52: 1d04 addi s1,sp,688 + 4a54: 00090003 lb zero,0(s2) + 4a58: 0100 addi s0,sp,128 + 4a5a: 0200 addi s0,sp,256 + 4a5c: 1d04 addi s1,sp,688 + 4a5e: 00090003 lb zero,0(s2) + 4a62: 0100 addi s0,sp,128 + 4a64: 0200 addi s0,sp,256 + 4a66: 1d04 addi s1,sp,688 + 4a68: 00090003 lb zero,0(s2) + 4a6c: 0100 addi s0,sp,128 + 4a6e: 0200 addi s0,sp,256 + 4a70: 1d04 addi s1,sp,688 + 4a72: 00090003 lb zero,0(s2) + 4a76: 0100 addi s0,sp,128 + 4a78: 0200 addi s0,sp,256 + 4a7a: 1d04 addi s1,sp,688 + 4a7c: 00090003 lb zero,0(s2) + 4a80: 0100 addi s0,sp,128 + 4a82: 0200 addi s0,sp,256 + 4a84: 1d04 addi s1,sp,688 + 4a86: 08090003 lb zero,128(s2) + 4a8a: 0100 addi s0,sp,128 + 4a8c: 0200 addi s0,sp,256 + 4a8e: 1d04 addi s1,sp,688 + 4a90: 00090003 lb zero,0(s2) + 4a94: 0100 addi s0,sp,128 + 4a96: 0200 addi s0,sp,256 + 4a98: 1d04 addi s1,sp,688 + 4a9a: 04090003 lb zero,64(s2) + 4a9e: 0100 addi s0,sp,128 + 4aa0: 0200 addi s0,sp,256 + 4aa2: 1d04 addi s1,sp,688 + 4aa4: 00090003 lb zero,0(s2) + 4aa8: 0100 addi s0,sp,128 + 4aaa: 0200 addi s0,sp,256 + 4aac: 1d04 addi s1,sp,688 + 4aae: 08090003 lb zero,128(s2) + 4ab2: 0100 addi s0,sp,128 + 4ab4: 0200 addi s0,sp,256 + 4ab6: 1d04 addi s1,sp,688 + 4ab8: 04090003 lb zero,64(s2) + 4abc: 0100 addi s0,sp,128 + 4abe: 0200 addi s0,sp,256 + 4ac0: 1e04 addi s1,sp,816 + 4ac2: 04090003 lb zero,64(s2) + 4ac6: 0100 addi s0,sp,128 + 4ac8: 0200 addi s0,sp,256 + 4aca: 2004 fld fs1,0(s0) + 4acc: 04090003 lb zero,64(s2) + 4ad0: 0100 addi s0,sp,128 + 4ad2: 0200 addi s0,sp,256 + 4ad4: 2004 fld fs1,0(s0) + 4ad6: 10090003 lb zero,256(s2) + 4ada: 0100 addi s0,sp,128 + 4adc: 0200 addi s0,sp,256 + 4ade: 2004 fld fs1,0(s0) + 4ae0: 14090003 lb zero,320(s2) + 4ae4: 0100 addi s0,sp,128 + 4ae6: 0200 addi s0,sp,256 + 4ae8: 2004 fld fs1,0(s0) + 4aea: 00090003 lb zero,0(s2) + 4aee: 0100 addi s0,sp,128 + 4af0: 0200 addi s0,sp,256 + 4af2: 2004 fld fs1,0(s0) + 4af4: 00090003 lb zero,0(s2) + 4af8: 0100 addi s0,sp,128 + 4afa: 0200 addi s0,sp,256 + 4afc: 2004 fld fs1,0(s0) + 4afe: 00090003 lb zero,0(s2) + 4b02: 0100 addi s0,sp,128 + 4b04: 0200 addi s0,sp,256 + 4b06: 2004 fld fs1,0(s0) + 4b08: 00090003 lb zero,0(s2) + 4b0c: 0100 addi s0,sp,128 + 4b0e: 0200 addi s0,sp,256 + 4b10: 2004 fld fs1,0(s0) + 4b12: 00090003 lb zero,0(s2) + 4b16: 0100 addi s0,sp,128 + 4b18: 0200 addi s0,sp,256 + 4b1a: 2004 fld fs1,0(s0) + 4b1c: 00090003 lb zero,0(s2) + 4b20: 0100 addi s0,sp,128 + 4b22: 0200 addi s0,sp,256 + 4b24: 2004 fld fs1,0(s0) + 4b26: 00090003 lb zero,0(s2) + 4b2a: 0100 addi s0,sp,128 + 4b2c: 0200 addi s0,sp,256 + 4b2e: 2004 fld fs1,0(s0) + 4b30: 00090003 lb zero,0(s2) + 4b34: 0100 addi s0,sp,128 + 4b36: 0200 addi s0,sp,256 + 4b38: 2004 fld fs1,0(s0) + 4b3a: 00090003 lb zero,0(s2) + 4b3e: 0100 addi s0,sp,128 + 4b40: 0200 addi s0,sp,256 + 4b42: 2004 fld fs1,0(s0) + 4b44: 00090003 lb zero,0(s2) + 4b48: 0100 addi s0,sp,128 + 4b4a: 0200 addi s0,sp,256 + 4b4c: 2004 fld fs1,0(s0) + 4b4e: 04090003 lb zero,64(s2) + 4b52: 0100 addi s0,sp,128 + 4b54: 0200 addi s0,sp,256 + 4b56: 2004 fld fs1,0(s0) + 4b58: 14090003 lb zero,320(s2) + 4b5c: 0100 addi s0,sp,128 + 4b5e: 0200 addi s0,sp,256 + 4b60: 2004 fld fs1,0(s0) + 4b62: 00090003 lb zero,0(s2) + 4b66: 0100 addi s0,sp,128 + 4b68: 0200 addi s0,sp,256 + 4b6a: 2004 fld fs1,0(s0) + 4b6c: 00090003 lb zero,0(s2) + 4b70: 0100 addi s0,sp,128 + 4b72: 0200 addi s0,sp,256 + 4b74: 2104 fld fs1,0(a0) + 4b76: 04090003 lb zero,64(s2) + 4b7a: 0100 addi s0,sp,128 + 4b7c: 0200 addi s0,sp,256 + 4b7e: 2304 fld fs1,0(a4) + 4b80: 04090003 lb zero,64(s2) + 4b84: 0100 addi s0,sp,128 + 4b86: 0200 addi s0,sp,256 + 4b88: 2304 fld fs1,0(a4) + 4b8a: 10090003 lb zero,256(s2) + 4b8e: 0100 addi s0,sp,128 + 4b90: 0200 addi s0,sp,256 + 4b92: 2304 fld fs1,0(a4) + 4b94: 18090003 lb zero,384(s2) + 4b98: 0100 addi s0,sp,128 + 4b9a: 0200 addi s0,sp,256 + 4b9c: 2304 fld fs1,0(a4) + 4b9e: 00090003 lb zero,0(s2) + 4ba2: 0100 addi s0,sp,128 + 4ba4: 0200 addi s0,sp,256 + 4ba6: 2304 fld fs1,0(a4) + 4ba8: 00090003 lb zero,0(s2) + 4bac: 0100 addi s0,sp,128 + 4bae: 0200 addi s0,sp,256 + 4bb0: 2304 fld fs1,0(a4) + 4bb2: 00090003 lb zero,0(s2) + 4bb6: 0100 addi s0,sp,128 + 4bb8: 0200 addi s0,sp,256 + 4bba: 2304 fld fs1,0(a4) + 4bbc: 00090003 lb zero,0(s2) + 4bc0: 0100 addi s0,sp,128 + 4bc2: 0200 addi s0,sp,256 + 4bc4: 2304 fld fs1,0(a4) + 4bc6: 00090003 lb zero,0(s2) + 4bca: 0100 addi s0,sp,128 + 4bcc: 0200 addi s0,sp,256 + 4bce: 2304 fld fs1,0(a4) + 4bd0: 00090003 lb zero,0(s2) + 4bd4: 0100 addi s0,sp,128 + 4bd6: 0200 addi s0,sp,256 + 4bd8: 2304 fld fs1,0(a4) + 4bda: 00090003 lb zero,0(s2) + 4bde: 0100 addi s0,sp,128 + 4be0: 0200 addi s0,sp,256 + 4be2: 2304 fld fs1,0(a4) + 4be4: 00090003 lb zero,0(s2) + 4be8: 0100 addi s0,sp,128 + 4bea: 0200 addi s0,sp,256 + 4bec: 2304 fld fs1,0(a4) + 4bee: 04090003 lb zero,64(s2) + 4bf2: 0100 addi s0,sp,128 + 4bf4: 0200 addi s0,sp,256 + 4bf6: 2304 fld fs1,0(a4) + 4bf8: 00090003 lb zero,0(s2) + 4bfc: 0100 addi s0,sp,128 + 4bfe: 0200 addi s0,sp,256 + 4c00: 2304 fld fs1,0(a4) + 4c02: 00090003 lb zero,0(s2) + 4c06: 0100 addi s0,sp,128 + 4c08: 0200 addi s0,sp,256 + 4c0a: 2304 fld fs1,0(a4) + 4c0c: 14090003 lb zero,320(s2) + 4c10: 0100 addi s0,sp,128 + 4c12: 0200 addi s0,sp,256 + 4c14: 2304 fld fs1,0(a4) + 4c16: 00090003 lb zero,0(s2) + 4c1a: 0100 addi s0,sp,128 + 4c1c: 0200 addi s0,sp,256 + 4c1e: 2304 fld fs1,0(a4) + 4c20: 00090003 lb zero,0(s2) + 4c24: 0100 addi s0,sp,128 + 4c26: 0200 addi s0,sp,256 + 4c28: 2404 fld fs1,8(s0) + 4c2a: 04090003 lb zero,64(s2) + 4c2e: 0100 addi s0,sp,128 + 4c30: 0200 addi s0,sp,256 + 4c32: 2604 fld fs1,8(a2) + 4c34: 04090003 lb zero,64(s2) + 4c38: 0100 addi s0,sp,128 + 4c3a: 0200 addi s0,sp,256 + 4c3c: 2604 fld fs1,8(a2) + 4c3e: 80090003 lb zero,-2048(s2) + 4c42: 0100 addi s0,sp,128 + 4c44: 0200 addi s0,sp,256 + 4c46: 2604 fld fs1,8(a2) + 4c48: 00090003 lb zero,0(s2) + 4c4c: 0100 addi s0,sp,128 + 4c4e: 0200 addi s0,sp,256 + 4c50: 2604 fld fs1,8(a2) + 4c52: 00090003 lb zero,0(s2) + 4c56: 0100 addi s0,sp,128 + 4c58: 0200 addi s0,sp,256 + 4c5a: 2604 fld fs1,8(a2) + 4c5c: 00090003 lb zero,0(s2) + 4c60: 0100 addi s0,sp,128 + 4c62: 0200 addi s0,sp,256 + 4c64: 2604 fld fs1,8(a2) + 4c66: 00090003 lb zero,0(s2) + 4c6a: 0100 addi s0,sp,128 + 4c6c: 0200 addi s0,sp,256 + 4c6e: 2604 fld fs1,8(a2) + 4c70: 00090003 lb zero,0(s2) + 4c74: 0100 addi s0,sp,128 + 4c76: 0200 addi s0,sp,256 + 4c78: 2604 fld fs1,8(a2) + 4c7a: 00090003 lb zero,0(s2) + 4c7e: 0100 addi s0,sp,128 + 4c80: 0200 addi s0,sp,256 + 4c82: 2604 fld fs1,8(a2) + 4c84: 00090003 lb zero,0(s2) + 4c88: 0100 addi s0,sp,128 + 4c8a: 0200 addi s0,sp,256 + 4c8c: 2604 fld fs1,8(a2) + 4c8e: 00090003 lb zero,0(s2) + 4c92: 0100 addi s0,sp,128 + 4c94: 0200 addi s0,sp,256 + 4c96: 2604 fld fs1,8(a2) + 4c98: 00090003 lb zero,0(s2) + 4c9c: 0100 addi s0,sp,128 + 4c9e: 0200 addi s0,sp,256 + 4ca0: 2604 fld fs1,8(a2) + 4ca2: 00090003 lb zero,0(s2) + 4ca6: 0100 addi s0,sp,128 + 4ca8: 0200 addi s0,sp,256 + 4caa: 2604 fld fs1,8(a2) + 4cac: 00090003 lb zero,0(s2) + 4cb0: 0100 addi s0,sp,128 + 4cb2: 0200 addi s0,sp,256 + 4cb4: 2604 fld fs1,8(a2) + 4cb6: 00090003 lb zero,0(s2) + 4cba: 0100 addi s0,sp,128 + 4cbc: 0200 addi s0,sp,256 + 4cbe: 2604 fld fs1,8(a2) + 4cc0: 00090003 lb zero,0(s2) + 4cc4: 0100 addi s0,sp,128 + 4cc6: 0200 addi s0,sp,256 + 4cc8: 2604 fld fs1,8(a2) + 4cca: 00090003 lb zero,0(s2) + 4cce: 0100 addi s0,sp,128 + 4cd0: 0200 addi s0,sp,256 + 4cd2: 2604 fld fs1,8(a2) + 4cd4: 00090003 lb zero,0(s2) + 4cd8: 0100 addi s0,sp,128 + 4cda: 0200 addi s0,sp,256 + 4cdc: 2604 fld fs1,8(a2) + 4cde: 00090003 lb zero,0(s2) + 4ce2: 0100 addi s0,sp,128 + 4ce4: 0200 addi s0,sp,256 + 4ce6: 2604 fld fs1,8(a2) + 4ce8: 00090003 lb zero,0(s2) + 4cec: 0100 addi s0,sp,128 + 4cee: 0200 addi s0,sp,256 + 4cf0: 2604 fld fs1,8(a2) + 4cf2: 00090003 lb zero,0(s2) + 4cf6: 0100 addi s0,sp,128 + 4cf8: 0200 addi s0,sp,256 + 4cfa: 2604 fld fs1,8(a2) + 4cfc: 00090003 lb zero,0(s2) + 4d00: 0100 addi s0,sp,128 + 4d02: 0200 addi s0,sp,256 + 4d04: 2604 fld fs1,8(a2) + 4d06: 00090003 lb zero,0(s2) + 4d0a: 0100 addi s0,sp,128 + 4d0c: 0200 addi s0,sp,256 + 4d0e: 2604 fld fs1,8(a2) + 4d10: 00090003 lb zero,0(s2) + 4d14: 0100 addi s0,sp,128 + 4d16: 0200 addi s0,sp,256 + 4d18: 2604 fld fs1,8(a2) + 4d1a: 00090003 lb zero,0(s2) + 4d1e: 0100 addi s0,sp,128 + 4d20: 0200 addi s0,sp,256 + 4d22: 2604 fld fs1,8(a2) + 4d24: 00090003 lb zero,0(s2) + 4d28: 0100 addi s0,sp,128 + 4d2a: 0200 addi s0,sp,256 + 4d2c: 2604 fld fs1,8(a2) + 4d2e: 00090003 lb zero,0(s2) + 4d32: 0100 addi s0,sp,128 + 4d34: 0200 addi s0,sp,256 + 4d36: 2604 fld fs1,8(a2) + 4d38: 00090003 lb zero,0(s2) + 4d3c: 0100 addi s0,sp,128 + 4d3e: 0200 addi s0,sp,256 + 4d40: 2604 fld fs1,8(a2) + 4d42: 00090003 lb zero,0(s2) + 4d46: 0100 addi s0,sp,128 + 4d48: 0200 addi s0,sp,256 + 4d4a: 2604 fld fs1,8(a2) + 4d4c: 00090003 lb zero,0(s2) + 4d50: 0100 addi s0,sp,128 + 4d52: 0200 addi s0,sp,256 + 4d54: 2604 fld fs1,8(a2) + 4d56: 00090003 lb zero,0(s2) + 4d5a: 0100 addi s0,sp,128 + 4d5c: 0200 addi s0,sp,256 + 4d5e: 2604 fld fs1,8(a2) + 4d60: 00090003 lb zero,0(s2) + 4d64: 0100 addi s0,sp,128 + 4d66: 0200 addi s0,sp,256 + 4d68: 2604 fld fs1,8(a2) + 4d6a: 00090003 lb zero,0(s2) + 4d6e: 0100 addi s0,sp,128 + 4d70: 0200 addi s0,sp,256 + 4d72: 2604 fld fs1,8(a2) + 4d74: 00090003 lb zero,0(s2) + 4d78: 0100 addi s0,sp,128 + 4d7a: 0200 addi s0,sp,256 + 4d7c: 2604 fld fs1,8(a2) + 4d7e: 00090003 lb zero,0(s2) + 4d82: 0100 addi s0,sp,128 + 4d84: 0200 addi s0,sp,256 + 4d86: 2604 fld fs1,8(a2) + 4d88: 00090003 lb zero,0(s2) + 4d8c: 0100 addi s0,sp,128 + 4d8e: 0200 addi s0,sp,256 + 4d90: 2604 fld fs1,8(a2) + 4d92: 00090003 lb zero,0(s2) + 4d96: 0100 addi s0,sp,128 + 4d98: 0200 addi s0,sp,256 + 4d9a: 2604 fld fs1,8(a2) + 4d9c: 3c090003 lb zero,960(s2) + 4da0: 0100 addi s0,sp,128 + 4da2: 0200 addi s0,sp,256 + 4da4: 2604 fld fs1,8(a2) + 4da6: 00090003 lb zero,0(s2) + 4daa: 0100 addi s0,sp,128 + 4dac: 0200 addi s0,sp,256 + 4dae: 2604 fld fs1,8(a2) + 4db0: 00090003 lb zero,0(s2) + 4db4: 0100 addi s0,sp,128 + 4db6: 0200 addi s0,sp,256 + 4db8: 2604 fld fs1,8(a2) + 4dba: 00090003 lb zero,0(s2) + 4dbe: 0100 addi s0,sp,128 + 4dc0: 0200 addi s0,sp,256 + 4dc2: 2604 fld fs1,8(a2) + 4dc4: 00090003 lb zero,0(s2) + 4dc8: 0100 addi s0,sp,128 + 4dca: 0200 addi s0,sp,256 + 4dcc: 2604 fld fs1,8(a2) + 4dce: 00090003 lb zero,0(s2) + 4dd2: 0100 addi s0,sp,128 + 4dd4: 0200 addi s0,sp,256 + 4dd6: 2604 fld fs1,8(a2) + 4dd8: 00090003 lb zero,0(s2) + 4ddc: 0100 addi s0,sp,128 + 4dde: 0200 addi s0,sp,256 + 4de0: 2604 fld fs1,8(a2) + 4de2: 00090003 lb zero,0(s2) + 4de6: 0100 addi s0,sp,128 + 4de8: 0200 addi s0,sp,256 + 4dea: 2604 fld fs1,8(a2) + 4dec: 00090003 lb zero,0(s2) + 4df0: 0100 addi s0,sp,128 + 4df2: 0200 addi s0,sp,256 + 4df4: 2604 fld fs1,8(a2) + 4df6: 00090003 lb zero,0(s2) + 4dfa: 0100 addi s0,sp,128 + 4dfc: 0200 addi s0,sp,256 + 4dfe: 2604 fld fs1,8(a2) + 4e00: 00090003 lb zero,0(s2) + 4e04: 0100 addi s0,sp,128 + 4e06: 0200 addi s0,sp,256 + 4e08: 2604 fld fs1,8(a2) + 4e0a: 00090003 lb zero,0(s2) + 4e0e: 0100 addi s0,sp,128 + 4e10: 0200 addi s0,sp,256 + 4e12: 2604 fld fs1,8(a2) + 4e14: 00090003 lb zero,0(s2) + 4e18: 0100 addi s0,sp,128 + 4e1a: 0200 addi s0,sp,256 + 4e1c: 2604 fld fs1,8(a2) + 4e1e: 00090003 lb zero,0(s2) + 4e22: 0100 addi s0,sp,128 + 4e24: 0200 addi s0,sp,256 + 4e26: 2604 fld fs1,8(a2) + 4e28: 00090003 lb zero,0(s2) + 4e2c: 0100 addi s0,sp,128 + 4e2e: 0200 addi s0,sp,256 + 4e30: 2604 fld fs1,8(a2) + 4e32: 00090003 lb zero,0(s2) + 4e36: 0100 addi s0,sp,128 + 4e38: 0200 addi s0,sp,256 + 4e3a: 2604 fld fs1,8(a2) + 4e3c: 00090003 lb zero,0(s2) + 4e40: 0100 addi s0,sp,128 + 4e42: 0200 addi s0,sp,256 + 4e44: 2604 fld fs1,8(a2) + 4e46: 04090003 lb zero,64(s2) + 4e4a: 0100 addi s0,sp,128 + 4e4c: 0200 addi s0,sp,256 + 4e4e: 2604 fld fs1,8(a2) + 4e50: 14090003 lb zero,320(s2) + 4e54: 0100 addi s0,sp,128 + 4e56: 0200 addi s0,sp,256 + 4e58: 2604 fld fs1,8(a2) + 4e5a: 00090003 lb zero,0(s2) + 4e5e: 0100 addi s0,sp,128 + 4e60: 0200 addi s0,sp,256 + 4e62: 2604 fld fs1,8(a2) + 4e64: 00090003 lb zero,0(s2) + 4e68: 0100 addi s0,sp,128 + 4e6a: 0200 addi s0,sp,256 + 4e6c: 2704 fld fs1,8(a4) + 4e6e: 04090003 lb zero,64(s2) + 4e72: 0100 addi s0,sp,128 + 4e74: 0200 addi s0,sp,256 + 4e76: 2904 fld fs1,16(a0) + 4e78: 04090003 lb zero,64(s2) + 4e7c: 0100 addi s0,sp,128 + 4e7e: 0200 addi s0,sp,256 + 4e80: 2904 fld fs1,16(a0) + 4e82: 10090003 lb zero,256(s2) + 4e86: 0100 addi s0,sp,128 + 4e88: 0200 addi s0,sp,256 + 4e8a: 2904 fld fs1,16(a0) + 4e8c: 14090003 lb zero,320(s2) + 4e90: 0100 addi s0,sp,128 + 4e92: 0200 addi s0,sp,256 + 4e94: 2904 fld fs1,16(a0) + 4e96: 00090003 lb zero,0(s2) + 4e9a: 0100 addi s0,sp,128 + 4e9c: 0200 addi s0,sp,256 + 4e9e: 2904 fld fs1,16(a0) + 4ea0: 00090003 lb zero,0(s2) + 4ea4: 0100 addi s0,sp,128 + 4ea6: 0200 addi s0,sp,256 + 4ea8: 2904 fld fs1,16(a0) + 4eaa: 00090003 lb zero,0(s2) + 4eae: 0100 addi s0,sp,128 + 4eb0: 0200 addi s0,sp,256 + 4eb2: 2904 fld fs1,16(a0) + 4eb4: 00090003 lb zero,0(s2) + 4eb8: 0100 addi s0,sp,128 + 4eba: 0200 addi s0,sp,256 + 4ebc: 2904 fld fs1,16(a0) + 4ebe: 00090003 lb zero,0(s2) + 4ec2: 0100 addi s0,sp,128 + 4ec4: 0200 addi s0,sp,256 + 4ec6: 2904 fld fs1,16(a0) + 4ec8: 00090003 lb zero,0(s2) + 4ecc: 0100 addi s0,sp,128 + 4ece: 0200 addi s0,sp,256 + 4ed0: 2904 fld fs1,16(a0) + 4ed2: 00090003 lb zero,0(s2) + 4ed6: 0100 addi s0,sp,128 + 4ed8: 0200 addi s0,sp,256 + 4eda: 2904 fld fs1,16(a0) + 4edc: 00090003 lb zero,0(s2) + 4ee0: 0100 addi s0,sp,128 + 4ee2: 0200 addi s0,sp,256 + 4ee4: 2904 fld fs1,16(a0) + 4ee6: 04090003 lb zero,64(s2) + 4eea: 0100 addi s0,sp,128 + 4eec: 0200 addi s0,sp,256 + 4eee: 2904 fld fs1,16(a0) + 4ef0: 00090003 lb zero,0(s2) + 4ef4: 0100 addi s0,sp,128 + 4ef6: 0200 addi s0,sp,256 + 4ef8: 2904 fld fs1,16(a0) + 4efa: 00090003 lb zero,0(s2) + 4efe: 0100 addi s0,sp,128 + 4f00: 0200 addi s0,sp,256 + 4f02: 2904 fld fs1,16(a0) + 4f04: 14090003 lb zero,320(s2) + 4f08: 0100 addi s0,sp,128 + 4f0a: 0200 addi s0,sp,256 + 4f0c: 2904 fld fs1,16(a0) + 4f0e: 00090003 lb zero,0(s2) + 4f12: 0100 addi s0,sp,128 + 4f14: 0200 addi s0,sp,256 + 4f16: 2904 fld fs1,16(a0) + 4f18: 00090003 lb zero,0(s2) + 4f1c: 0100 addi s0,sp,128 + 4f1e: 0200 addi s0,sp,256 + 4f20: 2a04 fld fs1,16(a2) + 4f22: 04090003 lb zero,64(s2) + 4f26: 0100 addi s0,sp,128 + 4f28: 0200 addi s0,sp,256 + 4f2a: 2c04 fld fs1,24(s0) + 4f2c: 04090003 lb zero,64(s2) + 4f30: 0100 addi s0,sp,128 + 4f32: 0200 addi s0,sp,256 + 4f34: 2c04 fld fs1,24(s0) + 4f36: 14090003 lb zero,320(s2) + 4f3a: 0100 addi s0,sp,128 + 4f3c: 0200 addi s0,sp,256 + 4f3e: 2c04 fld fs1,24(s0) + 4f40: 10090003 lb zero,256(s2) + 4f44: 0100 addi s0,sp,128 + 4f46: 0200 addi s0,sp,256 + 4f48: 2c04 fld fs1,24(s0) + 4f4a: 00090003 lb zero,0(s2) + 4f4e: 0100 addi s0,sp,128 + 4f50: 0200 addi s0,sp,256 + 4f52: 2c04 fld fs1,24(s0) + 4f54: 00090003 lb zero,0(s2) + 4f58: 0100 addi s0,sp,128 + 4f5a: 0200 addi s0,sp,256 + 4f5c: 2c04 fld fs1,24(s0) + 4f5e: 00090003 lb zero,0(s2) + 4f62: 0100 addi s0,sp,128 + 4f64: 0200 addi s0,sp,256 + 4f66: 2c04 fld fs1,24(s0) + 4f68: 00090003 lb zero,0(s2) + 4f6c: 0100 addi s0,sp,128 + 4f6e: 0200 addi s0,sp,256 + 4f70: 2c04 fld fs1,24(s0) + 4f72: 00090003 lb zero,0(s2) + 4f76: 0100 addi s0,sp,128 + 4f78: 0200 addi s0,sp,256 + 4f7a: 2c04 fld fs1,24(s0) + 4f7c: 00090003 lb zero,0(s2) + 4f80: 0100 addi s0,sp,128 + 4f82: 0200 addi s0,sp,256 + 4f84: 2c04 fld fs1,24(s0) + 4f86: 00090003 lb zero,0(s2) + 4f8a: 0100 addi s0,sp,128 + 4f8c: 0200 addi s0,sp,256 + 4f8e: 2c04 fld fs1,24(s0) + 4f90: 00090003 lb zero,0(s2) + 4f94: 0100 addi s0,sp,128 + 4f96: 0200 addi s0,sp,256 + 4f98: 2c04 fld fs1,24(s0) + 4f9a: 00090003 lb zero,0(s2) + 4f9e: 0100 addi s0,sp,128 + 4fa0: 0200 addi s0,sp,256 + 4fa2: 2c04 fld fs1,24(s0) + 4fa4: 00090003 lb zero,0(s2) + 4fa8: 0100 addi s0,sp,128 + 4faa: 0200 addi s0,sp,256 + 4fac: 2c04 fld fs1,24(s0) + 4fae: 04090003 lb zero,64(s2) + 4fb2: 0100 addi s0,sp,128 + 4fb4: 0200 addi s0,sp,256 + 4fb6: 2c04 fld fs1,24(s0) + 4fb8: 08090003 lb zero,128(s2) + 4fbc: 0100 addi s0,sp,128 + 4fbe: 0200 addi s0,sp,256 + 4fc0: 2c04 fld fs1,24(s0) + 4fc2: 08090003 lb zero,128(s2) + 4fc6: 0100 addi s0,sp,128 + 4fc8: 0200 addi s0,sp,256 + 4fca: 2c04 fld fs1,24(s0) + 4fcc: 04090003 lb zero,64(s2) + 4fd0: 0100 addi s0,sp,128 + 4fd2: 0200 addi s0,sp,256 + 4fd4: 2d04 fld fs1,24(a0) + 4fd6: 04090003 lb zero,64(s2) + 4fda: 0100 addi s0,sp,128 + 4fdc: 0200 addi s0,sp,256 + 4fde: 2f04 fld fs1,24(a4) + 4fe0: 04090003 lb zero,64(s2) + 4fe4: 0100 addi s0,sp,128 + 4fe6: 0200 addi s0,sp,256 + 4fe8: 2f04 fld fs1,24(a4) + 4fea: 08090003 lb zero,128(s2) + 4fee: 0100 addi s0,sp,128 + 4ff0: 0200 addi s0,sp,256 + 4ff2: 2f04 fld fs1,24(a4) + 4ff4: 1c090003 lb zero,448(s2) + 4ff8: 0100 addi s0,sp,128 + 4ffa: 0200 addi s0,sp,256 + 4ffc: 2f04 fld fs1,24(a4) + 4ffe: 00090003 lb zero,0(s2) + 5002: 0100 addi s0,sp,128 + 5004: 0200 addi s0,sp,256 + 5006: 2f04 fld fs1,24(a4) + 5008: 00090003 lb zero,0(s2) + 500c: 0100 addi s0,sp,128 + 500e: 0200 addi s0,sp,256 + 5010: 2f04 fld fs1,24(a4) + 5012: 00090003 lb zero,0(s2) + 5016: 0100 addi s0,sp,128 + 5018: 0200 addi s0,sp,256 + 501a: 2f04 fld fs1,24(a4) + 501c: 00090003 lb zero,0(s2) + 5020: 0100 addi s0,sp,128 + 5022: 0200 addi s0,sp,256 + 5024: 2f04 fld fs1,24(a4) + 5026: 00090003 lb zero,0(s2) + 502a: 0100 addi s0,sp,128 + 502c: 0200 addi s0,sp,256 + 502e: 2f04 fld fs1,24(a4) + 5030: 00090003 lb zero,0(s2) + 5034: 0100 addi s0,sp,128 + 5036: 0200 addi s0,sp,256 + 5038: 2f04 fld fs1,24(a4) + 503a: 00090003 lb zero,0(s2) + 503e: 0100 addi s0,sp,128 + 5040: 0200 addi s0,sp,256 + 5042: 2f04 fld fs1,24(a4) + 5044: 00090003 lb zero,0(s2) + 5048: 0100 addi s0,sp,128 + 504a: 0200 addi s0,sp,256 + 504c: 2f04 fld fs1,24(a4) + 504e: 04090003 lb zero,64(s2) + 5052: 0100 addi s0,sp,128 + 5054: 0200 addi s0,sp,256 + 5056: 2f04 fld fs1,24(a4) + 5058: 00090003 lb zero,0(s2) + 505c: 0100 addi s0,sp,128 + 505e: 0200 addi s0,sp,256 + 5060: 2f04 fld fs1,24(a4) + 5062: 00090003 lb zero,0(s2) + 5066: 0100 addi s0,sp,128 + 5068: 0200 addi s0,sp,256 + 506a: 2f04 fld fs1,24(a4) + 506c: 14090003 lb zero,320(s2) + 5070: 0100 addi s0,sp,128 + 5072: 0200 addi s0,sp,256 + 5074: 2f04 fld fs1,24(a4) + 5076: 00090003 lb zero,0(s2) + 507a: 0100 addi s0,sp,128 + 507c: 0200 addi s0,sp,256 + 507e: 2f04 fld fs1,24(a4) + 5080: 00090003 lb zero,0(s2) + 5084: 0100 addi s0,sp,128 + 5086: 0200 addi s0,sp,256 + 5088: 3004 fld fs1,32(s0) + 508a: 04090003 lb zero,64(s2) + 508e: 0100 addi s0,sp,128 + 5090: 0200 addi s0,sp,256 + 5092: 3204 fld fs1,32(a2) + 5094: 04090003 lb zero,64(s2) + 5098: 0100 addi s0,sp,128 + 509a: 0200 addi s0,sp,256 + 509c: 3204 fld fs1,32(a2) + 509e: 10090003 lb zero,256(s2) + 50a2: 0100 addi s0,sp,128 + 50a4: 0200 addi s0,sp,256 + 50a6: 3204 fld fs1,32(a2) + 50a8: 14090003 lb zero,320(s2) + 50ac: 0100 addi s0,sp,128 + 50ae: 0200 addi s0,sp,256 + 50b0: 3204 fld fs1,32(a2) + 50b2: 00090003 lb zero,0(s2) + 50b6: 0100 addi s0,sp,128 + 50b8: 0200 addi s0,sp,256 + 50ba: 3204 fld fs1,32(a2) + 50bc: 00090003 lb zero,0(s2) + 50c0: 0100 addi s0,sp,128 + 50c2: 0200 addi s0,sp,256 + 50c4: 3204 fld fs1,32(a2) + 50c6: 00090003 lb zero,0(s2) + 50ca: 0100 addi s0,sp,128 + 50cc: 0200 addi s0,sp,256 + 50ce: 3204 fld fs1,32(a2) + 50d0: 00090003 lb zero,0(s2) + 50d4: 0100 addi s0,sp,128 + 50d6: 0200 addi s0,sp,256 + 50d8: 3204 fld fs1,32(a2) + 50da: 00090003 lb zero,0(s2) + 50de: 0100 addi s0,sp,128 + 50e0: 0200 addi s0,sp,256 + 50e2: 3204 fld fs1,32(a2) + 50e4: 00090003 lb zero,0(s2) + 50e8: 0100 addi s0,sp,128 + 50ea: 0200 addi s0,sp,256 + 50ec: 3204 fld fs1,32(a2) + 50ee: 00090003 lb zero,0(s2) + 50f2: 0100 addi s0,sp,128 + 50f4: 0200 addi s0,sp,256 + 50f6: 3204 fld fs1,32(a2) + 50f8: 00090003 lb zero,0(s2) + 50fc: 0100 addi s0,sp,128 + 50fe: 0200 addi s0,sp,256 + 5100: 3204 fld fs1,32(a2) + 5102: 08090003 lb zero,128(s2) + 5106: 0100 addi s0,sp,128 + 5108: 0200 addi s0,sp,256 + 510a: 3204 fld fs1,32(a2) + 510c: 00090003 lb zero,0(s2) + 5110: 0100 addi s0,sp,128 + 5112: 0200 addi s0,sp,256 + 5114: 3204 fld fs1,32(a2) + 5116: 04090003 lb zero,64(s2) + 511a: 0100 addi s0,sp,128 + 511c: 0200 addi s0,sp,256 + 511e: 3204 fld fs1,32(a2) + 5120: 00090003 lb zero,0(s2) + 5124: 0100 addi s0,sp,128 + 5126: 0200 addi s0,sp,256 + 5128: 3204 fld fs1,32(a2) + 512a: 08090003 lb zero,128(s2) + 512e: 0100 addi s0,sp,128 + 5130: 0200 addi s0,sp,256 + 5132: 3204 fld fs1,32(a2) + 5134: 04090003 lb zero,64(s2) + 5138: 0100 addi s0,sp,128 + 513a: 0200 addi s0,sp,256 + 513c: 3304 fld fs1,32(a4) + 513e: 04090003 lb zero,64(s2) + 5142: 0100 addi s0,sp,128 + 5144: 0200 addi s0,sp,256 + 5146: 3504 fld fs1,40(a0) + 5148: 04090003 lb zero,64(s2) + 514c: 0100 addi s0,sp,128 + 514e: 0200 addi s0,sp,256 + 5150: 3504 fld fs1,40(a0) + 5152: 0c090003 lb zero,192(s2) + 5156: 0100 addi s0,sp,128 + 5158: 0200 addi s0,sp,256 + 515a: 3504 fld fs1,40(a0) + 515c: 28090003 lb zero,640(s2) + 5160: 0100 addi s0,sp,128 + 5162: 0200 addi s0,sp,256 + 5164: 3504 fld fs1,40(a0) + 5166: 00090003 lb zero,0(s2) + 516a: 0100 addi s0,sp,128 + 516c: 0200 addi s0,sp,256 + 516e: 3504 fld fs1,40(a0) + 5170: 00090003 lb zero,0(s2) + 5174: 0100 addi s0,sp,128 + 5176: 0200 addi s0,sp,256 + 5178: 3504 fld fs1,40(a0) + 517a: 00090003 lb zero,0(s2) + 517e: 0100 addi s0,sp,128 + 5180: 0200 addi s0,sp,256 + 5182: 3504 fld fs1,40(a0) + 5184: 00090003 lb zero,0(s2) + 5188: 0100 addi s0,sp,128 + 518a: 0200 addi s0,sp,256 + 518c: 3504 fld fs1,40(a0) + 518e: 00090003 lb zero,0(s2) + 5192: 0100 addi s0,sp,128 + 5194: 0200 addi s0,sp,256 + 5196: 3504 fld fs1,40(a0) + 5198: 00090003 lb zero,0(s2) + 519c: 0100 addi s0,sp,128 + 519e: 0200 addi s0,sp,256 + 51a0: 3504 fld fs1,40(a0) + 51a2: 00090003 lb zero,0(s2) + 51a6: 0100 addi s0,sp,128 + 51a8: 0200 addi s0,sp,256 + 51aa: 3504 fld fs1,40(a0) + 51ac: 00090003 lb zero,0(s2) + 51b0: 0100 addi s0,sp,128 + 51b2: 0200 addi s0,sp,256 + 51b4: 3504 fld fs1,40(a0) + 51b6: 00090003 lb zero,0(s2) + 51ba: 0100 addi s0,sp,128 + 51bc: 0200 addi s0,sp,256 + 51be: 3504 fld fs1,40(a0) + 51c0: 00090003 lb zero,0(s2) + 51c4: 0100 addi s0,sp,128 + 51c6: 0200 addi s0,sp,256 + 51c8: 3504 fld fs1,40(a0) + 51ca: 00090003 lb zero,0(s2) + 51ce: 0100 addi s0,sp,128 + 51d0: 0200 addi s0,sp,256 + 51d2: 3504 fld fs1,40(a0) + 51d4: 00090003 lb zero,0(s2) + 51d8: 0100 addi s0,sp,128 + 51da: 0200 addi s0,sp,256 + 51dc: 3504 fld fs1,40(a0) + 51de: 00090003 lb zero,0(s2) + 51e2: 0100 addi s0,sp,128 + 51e4: 0200 addi s0,sp,256 + 51e6: 3504 fld fs1,40(a0) + 51e8: 00090003 lb zero,0(s2) + 51ec: 0100 addi s0,sp,128 + 51ee: 0200 addi s0,sp,256 + 51f0: 3504 fld fs1,40(a0) + 51f2: 04090003 lb zero,64(s2) + 51f6: 0100 addi s0,sp,128 + 51f8: 0200 addi s0,sp,256 + 51fa: 3504 fld fs1,40(a0) + 51fc: 04090003 lb zero,64(s2) + 5200: 0100 addi s0,sp,128 + 5202: 0200 addi s0,sp,256 + 5204: 3504 fld fs1,40(a0) + 5206: 00090003 lb zero,0(s2) + 520a: 0100 addi s0,sp,128 + 520c: 0200 addi s0,sp,256 + 520e: 3504 fld fs1,40(a0) + 5210: 08090003 lb zero,128(s2) + 5214: 0100 addi s0,sp,128 + 5216: 0200 addi s0,sp,256 + 5218: 3504 fld fs1,40(a0) + 521a: 00090003 lb zero,0(s2) + 521e: 0100 addi s0,sp,128 + 5220: 0200 addi s0,sp,256 + 5222: 3504 fld fs1,40(a0) + 5224: 00090003 lb zero,0(s2) + 5228: 0100 addi s0,sp,128 + 522a: 0200 addi s0,sp,256 + 522c: 3504 fld fs1,40(a0) + 522e: 00090003 lb zero,0(s2) + 5232: 0100 addi s0,sp,128 + 5234: 0200 addi s0,sp,256 + 5236: 3504 fld fs1,40(a0) + 5238: 00090003 lb zero,0(s2) + 523c: 0100 addi s0,sp,128 + 523e: 0200 addi s0,sp,256 + 5240: 3504 fld fs1,40(a0) + 5242: 00090003 lb zero,0(s2) + 5246: 0100 addi s0,sp,128 + 5248: 0200 addi s0,sp,256 + 524a: 3504 fld fs1,40(a0) + 524c: 08090003 lb zero,128(s2) + 5250: 0100 addi s0,sp,128 + 5252: 0200 addi s0,sp,256 + 5254: 3504 fld fs1,40(a0) + 5256: 04090003 lb zero,64(s2) + 525a: 0100 addi s0,sp,128 + 525c: 0200 addi s0,sp,256 + 525e: 3504 fld fs1,40(a0) + 5260: 00090003 lb zero,0(s2) + 5264: 0100 addi s0,sp,128 + 5266: 0200 addi s0,sp,256 + 5268: 3504 fld fs1,40(a0) + 526a: 00090003 lb zero,0(s2) + 526e: 0100 addi s0,sp,128 + 5270: 0200 addi s0,sp,256 + 5272: 3504 fld fs1,40(a0) + 5274: 04090003 lb zero,64(s2) + 5278: 0100 addi s0,sp,128 + 527a: 0200 addi s0,sp,256 + 527c: 3504 fld fs1,40(a0) + 527e: 00090003 lb zero,0(s2) + 5282: 0100 addi s0,sp,128 + 5284: 0200 addi s0,sp,256 + 5286: 3504 fld fs1,40(a0) + 5288: 00090003 lb zero,0(s2) + 528c: 0100 addi s0,sp,128 + 528e: 0200 addi s0,sp,256 + 5290: 3504 fld fs1,40(a0) + 5292: 00090003 lb zero,0(s2) + 5296: 0100 addi s0,sp,128 + 5298: 0200 addi s0,sp,256 + 529a: 3504 fld fs1,40(a0) + 529c: 00090003 lb zero,0(s2) + 52a0: 0100 addi s0,sp,128 + 52a2: 0200 addi s0,sp,256 + 52a4: 3504 fld fs1,40(a0) + 52a6: 00090003 lb zero,0(s2) + 52aa: 0100 addi s0,sp,128 + 52ac: 0200 addi s0,sp,256 + 52ae: 3504 fld fs1,40(a0) + 52b0: 2c090003 lb zero,704(s2) + 52b4: 0100 addi s0,sp,128 + 52b6: 0200 addi s0,sp,256 + 52b8: 3504 fld fs1,40(a0) + 52ba: 08090003 lb zero,128(s2) + 52be: 0100 addi s0,sp,128 + 52c0: 0200 addi s0,sp,256 + 52c2: 3504 fld fs1,40(a0) + 52c4: 04090003 lb zero,64(s2) + 52c8: 0100 addi s0,sp,128 + 52ca: 0200 addi s0,sp,256 + 52cc: 3504 fld fs1,40(a0) + 52ce: 00090003 lb zero,0(s2) + 52d2: 0100 addi s0,sp,128 + 52d4: 0200 addi s0,sp,256 + 52d6: 3504 fld fs1,40(a0) + 52d8: 04090003 lb zero,64(s2) + 52dc: 0100 addi s0,sp,128 + 52de: 0200 addi s0,sp,256 + 52e0: 3504 fld fs1,40(a0) + 52e2: 2c090003 lb zero,704(s2) + 52e6: 0100 addi s0,sp,128 + 52e8: 0200 addi s0,sp,256 + 52ea: 3504 fld fs1,40(a0) + 52ec: 00090003 lb zero,0(s2) + 52f0: 0100 addi s0,sp,128 + 52f2: 0200 addi s0,sp,256 + 52f4: 3504 fld fs1,40(a0) + 52f6: 00090003 lb zero,0(s2) + 52fa: 0100 addi s0,sp,128 + 52fc: 0200 addi s0,sp,256 + 52fe: 3504 fld fs1,40(a0) + 5300: 00090003 lb zero,0(s2) + 5304: 0100 addi s0,sp,128 + 5306: 0200 addi s0,sp,256 + 5308: 3504 fld fs1,40(a0) + 530a: 00090003 lb zero,0(s2) + 530e: 0100 addi s0,sp,128 + 5310: 0200 addi s0,sp,256 + 5312: 3504 fld fs1,40(a0) + 5314: 00090003 lb zero,0(s2) + 5318: 0100 addi s0,sp,128 + 531a: 0200 addi s0,sp,256 + 531c: 3504 fld fs1,40(a0) + 531e: 00090003 lb zero,0(s2) + 5322: 0100 addi s0,sp,128 + 5324: 0200 addi s0,sp,256 + 5326: 3504 fld fs1,40(a0) + 5328: 00090003 lb zero,0(s2) + 532c: 0100 addi s0,sp,128 + 532e: 0200 addi s0,sp,256 + 5330: 3504 fld fs1,40(a0) + 5332: 00090003 lb zero,0(s2) + 5336: 0100 addi s0,sp,128 + 5338: 0200 addi s0,sp,256 + 533a: 3504 fld fs1,40(a0) + 533c: 00090003 lb zero,0(s2) + 5340: 0100 addi s0,sp,128 + 5342: 0200 addi s0,sp,256 + 5344: 3504 fld fs1,40(a0) + 5346: 0c090003 lb zero,192(s2) + 534a: 0100 addi s0,sp,128 + 534c: 0200 addi s0,sp,256 + 534e: 3504 fld fs1,40(a0) + 5350: 00090003 lb zero,0(s2) + 5354: 0100 addi s0,sp,128 + 5356: 0200 addi s0,sp,256 + 5358: 3504 fld fs1,40(a0) + 535a: 00090003 lb zero,0(s2) + 535e: 0100 addi s0,sp,128 + 5360: 0200 addi s0,sp,256 + 5362: 3504 fld fs1,40(a0) + 5364: 00090003 lb zero,0(s2) + 5368: 0100 addi s0,sp,128 + 536a: 0200 addi s0,sp,256 + 536c: 3504 fld fs1,40(a0) + 536e: 00090003 lb zero,0(s2) + 5372: 0100 addi s0,sp,128 + 5374: 0200 addi s0,sp,256 + 5376: 3504 fld fs1,40(a0) + 5378: 00090003 lb zero,0(s2) + 537c: 0100 addi s0,sp,128 + 537e: 0200 addi s0,sp,256 + 5380: 3504 fld fs1,40(a0) + 5382: 00090003 lb zero,0(s2) + 5386: 0100 addi s0,sp,128 + 5388: 0200 addi s0,sp,256 + 538a: 3504 fld fs1,40(a0) + 538c: 00090003 lb zero,0(s2) + 5390: 0100 addi s0,sp,128 + 5392: 0200 addi s0,sp,256 + 5394: 3504 fld fs1,40(a0) + 5396: 00090003 lb zero,0(s2) + 539a: 0100 addi s0,sp,128 + 539c: 0200 addi s0,sp,256 + 539e: 3504 fld fs1,40(a0) + 53a0: 00090003 lb zero,0(s2) + 53a4: 0100 addi s0,sp,128 + 53a6: 0200 addi s0,sp,256 + 53a8: 3504 fld fs1,40(a0) + 53aa: 00090003 lb zero,0(s2) + 53ae: 0100 addi s0,sp,128 + 53b0: 0200 addi s0,sp,256 + 53b2: 3504 fld fs1,40(a0) + 53b4: 00090003 lb zero,0(s2) + 53b8: 0100 addi s0,sp,128 + 53ba: 0200 addi s0,sp,256 + 53bc: 3504 fld fs1,40(a0) + 53be: 00090003 lb zero,0(s2) + 53c2: 0100 addi s0,sp,128 + 53c4: 0200 addi s0,sp,256 + 53c6: 3504 fld fs1,40(a0) + 53c8: 0c090003 lb zero,192(s2) + 53cc: 0100 addi s0,sp,128 + 53ce: 0200 addi s0,sp,256 + 53d0: 3504 fld fs1,40(a0) + 53d2: 00090003 lb zero,0(s2) + 53d6: 0100 addi s0,sp,128 + 53d8: 0200 addi s0,sp,256 + 53da: 3504 fld fs1,40(a0) + 53dc: 04090003 lb zero,64(s2) + 53e0: 0100 addi s0,sp,128 + 53e2: 0200 addi s0,sp,256 + 53e4: 3604 fld fs1,40(a2) + 53e6: 04090003 lb zero,64(s2) + 53ea: 0100 addi s0,sp,128 + 53ec: 0200 addi s0,sp,256 + 53ee: 3804 fld fs1,48(s0) + 53f0: 04090003 lb zero,64(s2) + 53f4: 0100 addi s0,sp,128 + 53f6: 0200 addi s0,sp,256 + 53f8: 3804 fld fs1,48(s0) + 53fa: 00090003 lb zero,0(s2) + 53fe: 0100 addi s0,sp,128 + 5400: 0200 addi s0,sp,256 + 5402: 3804 fld fs1,48(s0) + 5404: 14090003 lb zero,320(s2) + 5408: 0100 addi s0,sp,128 + 540a: 0200 addi s0,sp,256 + 540c: 3804 fld fs1,48(s0) + 540e: 00090003 lb zero,0(s2) + 5412: 0100 addi s0,sp,128 + 5414: 0200 addi s0,sp,256 + 5416: 3804 fld fs1,48(s0) + 5418: 00090003 lb zero,0(s2) + 541c: 0100 addi s0,sp,128 + 541e: 0200 addi s0,sp,256 + 5420: 3804 fld fs1,48(s0) + 5422: 00090003 lb zero,0(s2) + 5426: 0100 addi s0,sp,128 + 5428: 0200 addi s0,sp,256 + 542a: 3804 fld fs1,48(s0) + 542c: 10090003 lb zero,256(s2) + 5430: 0100 addi s0,sp,128 + 5432: 0200 addi s0,sp,256 + 5434: 3804 fld fs1,48(s0) + 5436: 28090003 lb zero,640(s2) + 543a: 0100 addi s0,sp,128 + 543c: 0200 addi s0,sp,256 + 543e: 3804 fld fs1,48(s0) + 5440: 00090003 lb zero,0(s2) + 5444: 0100 addi s0,sp,128 + 5446: 0200 addi s0,sp,256 + 5448: 3804 fld fs1,48(s0) + 544a: 00090003 lb zero,0(s2) + 544e: 0100 addi s0,sp,128 + 5450: 0200 addi s0,sp,256 + 5452: 3804 fld fs1,48(s0) + 5454: 00090003 lb zero,0(s2) + 5458: 0100 addi s0,sp,128 + 545a: 0200 addi s0,sp,256 + 545c: 3804 fld fs1,48(s0) + 545e: 00090003 lb zero,0(s2) + 5462: 0100 addi s0,sp,128 + 5464: 0200 addi s0,sp,256 + 5466: 3804 fld fs1,48(s0) + 5468: 00090003 lb zero,0(s2) + 546c: 0100 addi s0,sp,128 + 546e: 0200 addi s0,sp,256 + 5470: 3804 fld fs1,48(s0) + 5472: 00090003 lb zero,0(s2) + 5476: 0100 addi s0,sp,128 + 5478: 0200 addi s0,sp,256 + 547a: 3804 fld fs1,48(s0) + 547c: 00090003 lb zero,0(s2) + 5480: 0100 addi s0,sp,128 + 5482: 0200 addi s0,sp,256 + 5484: 3804 fld fs1,48(s0) + 5486: 00090003 lb zero,0(s2) + 548a: 0100 addi s0,sp,128 + 548c: 0200 addi s0,sp,256 + 548e: 3804 fld fs1,48(s0) + 5490: 00090003 lb zero,0(s2) + 5494: 0100 addi s0,sp,128 + 5496: 0200 addi s0,sp,256 + 5498: 3804 fld fs1,48(s0) + 549a: 00090003 lb zero,0(s2) + 549e: 0100 addi s0,sp,128 + 54a0: 0200 addi s0,sp,256 + 54a2: 3804 fld fs1,48(s0) + 54a4: 00090003 lb zero,0(s2) + 54a8: 0100 addi s0,sp,128 + 54aa: 0200 addi s0,sp,256 + 54ac: 3804 fld fs1,48(s0) + 54ae: 00090003 lb zero,0(s2) + 54b2: 0100 addi s0,sp,128 + 54b4: 0200 addi s0,sp,256 + 54b6: 3804 fld fs1,48(s0) + 54b8: 00090003 lb zero,0(s2) + 54bc: 0100 addi s0,sp,128 + 54be: 0200 addi s0,sp,256 + 54c0: 3804 fld fs1,48(s0) + 54c2: 00090003 lb zero,0(s2) + 54c6: 0100 addi s0,sp,128 + 54c8: 0200 addi s0,sp,256 + 54ca: 3804 fld fs1,48(s0) + 54cc: 00090003 lb zero,0(s2) + 54d0: 0100 addi s0,sp,128 + 54d2: 0200 addi s0,sp,256 + 54d4: 3804 fld fs1,48(s0) + 54d6: 00090003 lb zero,0(s2) + 54da: 0100 addi s0,sp,128 + 54dc: 0200 addi s0,sp,256 + 54de: 3804 fld fs1,48(s0) + 54e0: 00090003 lb zero,0(s2) + 54e4: 0100 addi s0,sp,128 + 54e6: 0200 addi s0,sp,256 + 54e8: 3804 fld fs1,48(s0) + 54ea: 00090003 lb zero,0(s2) + 54ee: 0100 addi s0,sp,128 + 54f0: 0200 addi s0,sp,256 + 54f2: 3804 fld fs1,48(s0) + 54f4: 00090003 lb zero,0(s2) + 54f8: 0100 addi s0,sp,128 + 54fa: 0200 addi s0,sp,256 + 54fc: 3804 fld fs1,48(s0) + 54fe: 00090003 lb zero,0(s2) + 5502: 0100 addi s0,sp,128 + 5504: 0200 addi s0,sp,256 + 5506: 3804 fld fs1,48(s0) + 5508: 00090003 lb zero,0(s2) + 550c: 0100 addi s0,sp,128 + 550e: 0200 addi s0,sp,256 + 5510: 3804 fld fs1,48(s0) + 5512: 00090003 lb zero,0(s2) + 5516: 0100 addi s0,sp,128 + 5518: 0200 addi s0,sp,256 + 551a: 3804 fld fs1,48(s0) + 551c: 04090003 lb zero,64(s2) + 5520: 0100 addi s0,sp,128 + 5522: 0200 addi s0,sp,256 + 5524: 3804 fld fs1,48(s0) + 5526: 00090003 lb zero,0(s2) + 552a: 0100 addi s0,sp,128 + 552c: 0200 addi s0,sp,256 + 552e: 4404 lw s1,8(s0) + 5530: 08090003 lb zero,128(s2) + 5534: 0100 addi s0,sp,128 + 5536: 0200 addi s0,sp,256 + 5538: 4404 lw s1,8(s0) + 553a: 1c090003 lb zero,448(s2) + 553e: 0100 addi s0,sp,128 + 5540: 0200 addi s0,sp,256 + 5542: 4404 lw s1,8(s0) + 5544: 00090003 lb zero,0(s2) + 5548: 0100 addi s0,sp,128 + 554a: 0200 addi s0,sp,256 + 554c: 4704 lw s1,8(a4) + 554e: 04090003 lb zero,64(s2) + 5552: 0100 addi s0,sp,128 + 5554: 0200 addi s0,sp,256 + 5556: 4704 lw s1,8(a4) + 5558: 00090003 lb zero,0(s2) + 555c: 0100 addi s0,sp,128 + 555e: 0200 addi s0,sp,256 + 5560: 4704 lw s1,8(a4) + 5562: 00090003 lb zero,0(s2) + 5566: 0100 addi s0,sp,128 + 5568: 0200 addi s0,sp,256 + 556a: 4704 lw s1,8(a4) + 556c: 10090003 lb zero,256(s2) + 5570: 0100 addi s0,sp,128 + 5572: 0200 addi s0,sp,256 + 5574: 4704 lw s1,8(a4) + 5576: 00090003 lb zero,0(s2) + 557a: 0100 addi s0,sp,128 + 557c: 0200 addi s0,sp,256 + 557e: 4704 lw s1,8(a4) + 5580: 10090003 lb zero,256(s2) + 5584: 0100 addi s0,sp,128 + 5586: 0200 addi s0,sp,256 + 5588: 4704 lw s1,8(a4) + 558a: 00090003 lb zero,0(s2) + 558e: 0100 addi s0,sp,128 + 5590: 0200 addi s0,sp,256 + 5592: 5104 lw s1,32(a0) + 5594: 10090003 lb zero,256(s2) + 5598: 0100 addi s0,sp,128 + 559a: 0200 addi s0,sp,256 + 559c: 5104 lw s1,32(a0) + 559e: 00090003 lb zero,0(s2) + 55a2: 0100 addi s0,sp,128 + 55a4: 0200 addi s0,sp,256 + 55a6: 5104 lw s1,32(a0) + 55a8: 00090003 lb zero,0(s2) + 55ac: 0100 addi s0,sp,128 + 55ae: 0200 addi s0,sp,256 + 55b0: 5104 lw s1,32(a0) + 55b2: 00090003 lb zero,0(s2) + 55b6: 0100 addi s0,sp,128 + 55b8: 0200 addi s0,sp,256 + 55ba: 5104 lw s1,32(a0) + 55bc: 00090003 lb zero,0(s2) + 55c0: 0100 addi s0,sp,128 + 55c2: 0200 addi s0,sp,256 + 55c4: 5104 lw s1,32(a0) + 55c6: 00090003 lb zero,0(s2) + 55ca: 0100 addi s0,sp,128 + 55cc: 0200 addi s0,sp,256 + 55ce: 5104 lw s1,32(a0) + 55d0: 00090003 lb zero,0(s2) + 55d4: 0100 addi s0,sp,128 + 55d6: 0200 addi s0,sp,256 + 55d8: 5104 lw s1,32(a0) + 55da: 00090003 lb zero,0(s2) + 55de: 0100 addi s0,sp,128 + 55e0: 0200 addi s0,sp,256 + 55e2: 5104 lw s1,32(a0) + 55e4: 00090003 lb zero,0(s2) + 55e8: 0100 addi s0,sp,128 + 55ea: 0200 addi s0,sp,256 + 55ec: 5104 lw s1,32(a0) + 55ee: 00090003 lb zero,0(s2) + 55f2: 0100 addi s0,sp,128 + 55f4: 0200 addi s0,sp,256 + 55f6: 5104 lw s1,32(a0) + 55f8: 00090003 lb zero,0(s2) + 55fc: 0100 addi s0,sp,128 + 55fe: 0200 addi s0,sp,256 + 5600: 5104 lw s1,32(a0) + 5602: 00090003 lb zero,0(s2) + 5606: 0100 addi s0,sp,128 + 5608: 0200 addi s0,sp,256 + 560a: 5104 lw s1,32(a0) + 560c: 00090003 lb zero,0(s2) + 5610: 0100 addi s0,sp,128 + 5612: 0200 addi s0,sp,256 + 5614: 5104 lw s1,32(a0) + 5616: 04090003 lb zero,64(s2) + 561a: 0100 addi s0,sp,128 + 561c: 0200 addi s0,sp,256 + 561e: 5104 lw s1,32(a0) + 5620: 00090003 lb zero,0(s2) + 5624: 0100 addi s0,sp,128 + 5626: 0200 addi s0,sp,256 + 5628: 5704 lw s1,40(a4) + 562a: 08090003 lb zero,128(s2) + 562e: 0100 addi s0,sp,128 + 5630: 0200 addi s0,sp,256 + 5632: 5704 lw s1,40(a4) + 5634: 1c090003 lb zero,448(s2) + 5638: 0100 addi s0,sp,128 + 563a: 0200 addi s0,sp,256 + 563c: 5704 lw s1,40(a4) + 563e: 00090003 lb zero,0(s2) + 5642: 0100 addi s0,sp,128 + 5644: 0200 addi s0,sp,256 + 5646: 5804 lw s1,48(s0) + 5648: 04090003 lb zero,64(s2) + 564c: 0100 addi s0,sp,128 + 564e: 0200 addi s0,sp,256 + 5650: 5804 lw s1,48(s0) + 5652: 10090003 lb zero,256(s2) + 5656: 0100 addi s0,sp,128 + 5658: 0200 addi s0,sp,256 + 565a: 5804 lw s1,48(s0) + 565c: 00090003 lb zero,0(s2) + 5660: 0100 addi s0,sp,128 + 5662: 0200 addi s0,sp,256 + 5664: 5804 lw s1,48(s0) + 5666: 00090003 lb zero,0(s2) + 566a: 0100 addi s0,sp,128 + 566c: 0200 addi s0,sp,256 + 566e: 5804 lw s1,48(s0) + 5670: 00090003 lb zero,0(s2) + 5674: 0100 addi s0,sp,128 + 5676: 0200 addi s0,sp,256 + 5678: 5804 lw s1,48(s0) + 567a: 0c090003 lb zero,192(s2) + 567e: 0100 addi s0,sp,128 + 5680: 0200 addi s0,sp,256 + 5682: 0204 addi s1,sp,256 + 5684: 00090103 lb sp,0(s2) + 5688: 0100 addi s0,sp,128 + 568a: 0200 addi s0,sp,256 + 568c: 0204 addi s1,sp,256 + 568e: 10090003 lb zero,256(s2) + 5692: 0100 addi s0,sp,128 + 5694: 0200 addi s0,sp,256 + 5696: 0604 addi s1,sp,768 + 5698: 04090003 lb zero,64(s2) + 569c: 0100 addi s0,sp,128 + 569e: 0200 addi s0,sp,256 + 56a0: 0604 addi s1,sp,768 + 56a2: 00090003 lb zero,0(s2) + 56a6: 0100 addi s0,sp,128 + 56a8: 0200 addi s0,sp,256 + 56aa: 0804 addi s1,sp,16 + 56ac: 0c090003 lb zero,192(s2) + 56b0: 0100 addi s0,sp,128 + 56b2: 0200 addi s0,sp,256 + 56b4: 0804 addi s1,sp,16 + 56b6: 00090003 lb zero,0(s2) + 56ba: 0100 addi s0,sp,128 + 56bc: 0200 addi s0,sp,256 + 56be: 0804 addi s1,sp,16 + 56c0: 00090003 lb zero,0(s2) + 56c4: 0100 addi s0,sp,128 + 56c6: 0200 addi s0,sp,256 + 56c8: 0804 addi s1,sp,16 + 56ca: 00090003 lb zero,0(s2) + 56ce: 0100 addi s0,sp,128 + 56d0: 0200 addi s0,sp,256 + 56d2: 0a04 addi s1,sp,272 + 56d4: 0c090003 lb zero,192(s2) + 56d8: 0100 addi s0,sp,128 + 56da: 0200 addi s0,sp,256 + 56dc: 0a04 addi s1,sp,272 + 56de: 00090003 lb zero,0(s2) + 56e2: 0100 addi s0,sp,128 + 56e4: 0200 addi s0,sp,256 + 56e6: 0a04 addi s1,sp,272 + 56e8: 00090003 lb zero,0(s2) + 56ec: 0100 addi s0,sp,128 + 56ee: 0200 addi s0,sp,256 + 56f0: 0a04 addi s1,sp,272 + 56f2: 10090003 lb zero,256(s2) + 56f6: 0100 addi s0,sp,128 + 56f8: 0200 addi s0,sp,256 + 56fa: 0a04 addi s1,sp,272 + 56fc: 0c090003 lb zero,192(s2) + 5700: 0100 addi s0,sp,128 + 5702: 0200 addi s0,sp,256 + 5704: 0a04 addi s1,sp,272 + 5706: 00090003 lb zero,0(s2) + 570a: 0100 addi s0,sp,128 + 570c: 0200 addi s0,sp,256 + 570e: 0a04 addi s1,sp,272 + 5710: 0c090003 lb zero,192(s2) + 5714: 0100 addi s0,sp,128 + 5716: 0200 addi s0,sp,256 + 5718: 0a04 addi s1,sp,272 + 571a: 04090003 lb zero,64(s2) + 571e: 0100 addi s0,sp,128 + 5720: 0200 addi s0,sp,256 + 5722: 0904 addi s1,sp,144 + 5724: 0c090003 lb zero,192(s2) + 5728: 0100 addi s0,sp,128 + 572a: 0200 addi s0,sp,256 + 572c: 0904 addi s1,sp,144 + 572e: 00090003 lb zero,0(s2) + 5732: 0100 addi s0,sp,128 + 5734: 0200 addi s0,sp,256 + 5736: 1804 addi s1,sp,48 + 5738: 0c090003 lb zero,192(s2) + 573c: 0100 addi s0,sp,128 + 573e: 0200 addi s0,sp,256 + 5740: 1804 addi s1,sp,48 + 5742: 10090003 lb zero,256(s2) + 5746: 0100 addi s0,sp,128 + 5748: 0200 addi s0,sp,256 + 574a: 1a04 addi s1,sp,304 + 574c: 0c090003 lb zero,192(s2) + 5750: 0100 addi s0,sp,128 + 5752: 0200 addi s0,sp,256 + 5754: 1a04 addi s1,sp,304 + 5756: 00090003 lb zero,0(s2) + 575a: 0100 addi s0,sp,128 + 575c: 0200 addi s0,sp,256 + 575e: 1a04 addi s1,sp,304 + 5760: 00090003 lb zero,0(s2) + 5764: 0100 addi s0,sp,128 + 5766: 0200 addi s0,sp,256 + 5768: 1a04 addi s1,sp,304 + 576a: 00090003 lb zero,0(s2) + 576e: 0100 addi s0,sp,128 + 5770: 0200 addi s0,sp,256 + 5772: 1a04 addi s1,sp,304 + 5774: 00090003 lb zero,0(s2) + 5778: 0100 addi s0,sp,128 + 577a: 0200 addi s0,sp,256 + 577c: 1a04 addi s1,sp,304 + 577e: 00090003 lb zero,0(s2) + 5782: 0100 addi s0,sp,128 + 5784: 0200 addi s0,sp,256 + 5786: 1a04 addi s1,sp,304 + 5788: 00090003 lb zero,0(s2) + 578c: 0100 addi s0,sp,128 + 578e: 0200 addi s0,sp,256 + 5790: 1a04 addi s1,sp,304 + 5792: 00090003 lb zero,0(s2) + 5796: 0100 addi s0,sp,128 + 5798: 0200 addi s0,sp,256 + 579a: 1a04 addi s1,sp,304 + 579c: 00090003 lb zero,0(s2) + 57a0: 0100 addi s0,sp,128 + 57a2: 0200 addi s0,sp,256 + 57a4: 2204 fld fs1,0(a2) + 57a6: 08090003 lb zero,128(s2) + 57aa: 0100 addi s0,sp,128 + 57ac: 0200 addi s0,sp,256 + 57ae: 2204 fld fs1,0(a2) + 57b0: 1c090003 lb zero,448(s2) + 57b4: 0100 addi s0,sp,128 + 57b6: 0200 addi s0,sp,256 + 57b8: 2204 fld fs1,0(a2) + 57ba: 00090003 lb zero,0(s2) + 57be: 0100 addi s0,sp,128 + 57c0: 0200 addi s0,sp,256 + 57c2: 2304 fld fs1,0(a4) + 57c4: 04090003 lb zero,64(s2) + 57c8: 0100 addi s0,sp,128 + 57ca: 0200 addi s0,sp,256 + 57cc: 2304 fld fs1,0(a4) + 57ce: 00090003 lb zero,0(s2) + 57d2: 0100 addi s0,sp,128 + 57d4: 0200 addi s0,sp,256 + 57d6: 2304 fld fs1,0(a4) + 57d8: 00090003 lb zero,0(s2) + 57dc: 0100 addi s0,sp,128 + 57de: 0200 addi s0,sp,256 + 57e0: 2304 fld fs1,0(a4) + 57e2: 00090003 lb zero,0(s2) + 57e6: 0100 addi s0,sp,128 + 57e8: 0306 slli t1,t1,0x1 + 57ea: 0900 addi s0,sp,144 + 57ec: 000c 0xc + 57ee: 0001 nop + 57f0: 01910403 lb s0,25(sp) + 57f4: 0306 slli t1,t1,0x1 + 57f6: 0900 addi s0,sp,144 + 57f8: 000c 0xc + 57fa: 0001 nop + 57fc: 01910403 lb s0,25(sp) + 5800: 00090003 lb zero,0(s2) + 5804: 0100 addi s0,sp,128 + 5806: 0300 addi s0,sp,384 + 5808: 9104 0x9104 + 580a: 0301 addi t1,t1,0 + 580c: 0900 addi s0,sp,144 + 580e: 0000 unimp + 5810: 0001 nop + 5812: 01910403 lb s0,25(sp) + 5816: 00090003 lb zero,0(s2) + 581a: 0100 addi s0,sp,128 + 581c: 0300 addi s0,sp,384 + 581e: 9104 0x9104 + 5820: 0301 addi t1,t1,0 + 5822: 0900 addi s0,sp,144 + 5824: 0000 unimp + 5826: 0001 nop + 5828: 01910403 lb s0,25(sp) 582c: 00090003 lb zero,0(s2) 5830: 0100 addi s0,sp,128 - 5832: 0200 addi s0,sp,256 - 5834: 2304 fld fs1,0(a4) - 5836: 00090003 lb zero,0(s2) - 583a: 0100 addi s0,sp,128 - 583c: 0306 slli t1,t1,0x1 - 583e: 0900 addi s0,sp,144 - 5840: 000c 0xc - 5842: 0001 nop - 5844: 01910403 lb s0,25(sp) - 5848: 0306 slli t1,t1,0x1 - 584a: 0900 addi s0,sp,144 - 584c: 000c 0xc - 584e: 0001 nop - 5850: 01910403 lb s0,25(sp) - 5854: 00090003 lb zero,0(s2) - 5858: 0100 addi s0,sp,128 - 585a: 0300 addi s0,sp,384 - 585c: 9104 0x9104 - 585e: 0301 addi t1,t1,0 - 5860: 0900 addi s0,sp,144 - 5862: 0000 unimp - 5864: 0001 nop - 5866: 01910403 lb s0,25(sp) - 586a: 00090003 lb zero,0(s2) - 586e: 0100 addi s0,sp,128 - 5870: 0300 addi s0,sp,384 - 5872: 9104 0x9104 - 5874: 0301 addi t1,t1,0 - 5876: 0900 addi s0,sp,144 - 5878: 0000 unimp - 587a: 0001 nop - 587c: 01910403 lb s0,25(sp) - 5880: 00090003 lb zero,0(s2) - 5884: 0100 addi s0,sp,128 - 5886: 0300 addi s0,sp,384 - 5888: 9104 0x9104 - 588a: 0301 addi t1,t1,0 - 588c: 0900 addi s0,sp,144 - 588e: 0000 unimp - 5890: 0001 nop - 5892: 01910403 lb s0,25(sp) - 5896: 10090003 lb zero,256(s2) - 589a: 0100 addi s0,sp,128 - 589c: 0300 addi s0,sp,384 - 589e: 9104 0x9104 - 58a0: 0301 addi t1,t1,0 - 58a2: 0900 addi s0,sp,144 - 58a4: 0000 unimp - 58a6: 0501 addi a0,a0,0 - 58a8: 0001 nop - 58aa: 01910403 lb s0,25(sp) - 58ae: 0306 slli t1,t1,0x1 - 58b0: 0904 addi s1,sp,144 - 58b2: 0004 0x4 - 58b4: 0501 addi a0,a0,0 - 58b6: 04030003 lb zero,64(t1) - 58ba: 0191 addi gp,gp,4 - 58bc: 08097c03 0x8097c03 - 58c0: 0100 addi s0,sp,128 - 58c2: 0300 addi s0,sp,384 - 58c4: 9104 0x9104 - 58c6: 0601 addi a2,a2,0 - 58c8: 0c090003 lb zero,192(s2) - 58cc: 0100 addi s0,sp,128 - 58ce: 0300 addi s0,sp,384 - 58d0: 9104 0x9104 - 58d2: 0301 addi t1,t1,0 - 58d4: 0900 addi s0,sp,144 - 58d6: 0000 unimp - 58d8: 0001 nop + 5832: 0300 addi s0,sp,384 + 5834: 9104 0x9104 + 5836: 0301 addi t1,t1,0 + 5838: 0900 addi s0,sp,144 + 583a: 0000 unimp + 583c: 0001 nop + 583e: 01910403 lb s0,25(sp) + 5842: 10090003 lb zero,256(s2) + 5846: 0100 addi s0,sp,128 + 5848: 0300 addi s0,sp,384 + 584a: 9104 0x9104 + 584c: 0301 addi t1,t1,0 + 584e: 0900 addi s0,sp,144 + 5850: 0000 unimp + 5852: 0501 addi a0,a0,0 + 5854: 0001 nop + 5856: 01910403 lb s0,25(sp) + 585a: 0306 slli t1,t1,0x1 + 585c: 0904 addi s1,sp,144 + 585e: 0004 0x4 + 5860: 0501 addi a0,a0,0 + 5862: 04030003 lb zero,64(t1) + 5866: 0191 addi gp,gp,4 + 5868: 08097c03 0x8097c03 + 586c: 0100 addi s0,sp,128 + 586e: 0300 addi s0,sp,384 + 5870: 9104 0x9104 + 5872: 0601 addi a2,a2,0 + 5874: 0c090003 lb zero,192(s2) + 5878: 0100 addi s0,sp,128 + 587a: 0300 addi s0,sp,384 + 587c: 9104 0x9104 + 587e: 0301 addi t1,t1,0 + 5880: 0900 addi s0,sp,144 + 5882: 0000 unimp + 5884: 0001 nop + 5886: 01910403 lb s0,25(sp) + 588a: 00090003 lb zero,0(s2) + 588e: 0100 addi s0,sp,128 + 5890: 0300 addi s0,sp,384 + 5892: 9104 0x9104 + 5894: 0301 addi t1,t1,0 + 5896: 0901 addi s2,s2,0 + 5898: 0000 unimp + 589a: 0001 nop + 589c: 01910403 lb s0,25(sp) + 58a0: 00090003 lb zero,0(s2) + 58a4: 0100 addi s0,sp,128 + 58a6: 0300 addi s0,sp,384 + 58a8: 9104 0x9104 + 58aa: 0301 addi t1,t1,0 + 58ac: 0900 addi s0,sp,144 + 58ae: 0000 unimp + 58b0: 0001 nop + 58b2: 01910403 lb s0,25(sp) + 58b6: 00090203 lb tp,0(s2) + 58ba: 0100 addi s0,sp,128 + 58bc: 0a05 addi s4,s4,1 + 58be: 0300 addi s0,sp,384 + 58c0: 9104 0x9104 + 58c2: 0601 addi a2,a2,0 + 58c4: 00090003 lb zero,0(s2) + 58c8: 0100 addi s0,sp,128 + 58ca: 0105 addi sp,sp,1 + 58cc: 0300 addi s0,sp,384 + 58ce: 9104 0x9104 + 58d0: 0301 addi t1,t1,0 + 58d2: 0901 addi s2,s2,0 + 58d4: 0008 0x8 + 58d6: 0501 addi a0,a0,0 + 58d8: 000a c.slli zero,0x2 58da: 01910403 lb s0,25(sp) - 58de: 00090003 lb zero,0(s2) + 58de: 08097f03 0x8097f03 58e2: 0100 addi s0,sp,128 - 58e4: 0300 addi s0,sp,384 - 58e6: 9104 0x9104 - 58e8: 0301 addi t1,t1,0 - 58ea: 0901 addi s2,s2,0 - 58ec: 0000 unimp - 58ee: 0001 nop - 58f0: 01910403 lb s0,25(sp) - 58f4: 00090003 lb zero,0(s2) - 58f8: 0100 addi s0,sp,128 - 58fa: 0300 addi s0,sp,384 - 58fc: 9104 0x9104 - 58fe: 0301 addi t1,t1,0 - 5900: 0900 addi s0,sp,144 - 5902: 0000 unimp - 5904: 0001 nop - 5906: 01910403 lb s0,25(sp) - 590a: 00090203 lb tp,0(s2) - 590e: 0100 addi s0,sp,128 - 5910: 0a05 addi s4,s4,1 - 5912: 0300 addi s0,sp,384 - 5914: 9104 0x9104 - 5916: 0601 addi a2,a2,0 - 5918: 00090003 lb zero,0(s2) - 591c: 0100 addi s0,sp,128 - 591e: 0105 addi sp,sp,1 - 5920: 0300 addi s0,sp,384 - 5922: 9104 0x9104 - 5924: 0301 addi t1,t1,0 - 5926: 0901 addi s2,s2,0 - 5928: 0008 0x8 - 592a: 0501 addi a0,a0,0 - 592c: 000a c.slli zero,0x2 - 592e: 01910403 lb s0,25(sp) - 5932: 08097f03 0x8097f03 - 5936: 0100 addi s0,sp,128 - 5938: 0105 addi sp,sp,1 - 593a: 0300 addi s0,sp,384 - 593c: 9104 0x9104 - 593e: 0301 addi t1,t1,0 - 5940: 0901 addi s2,s2,0 - 5942: 0008 0x8 - 5944: 0501 addi a0,a0,0 - 5946: 000a c.slli zero,0x2 - 5948: 01910403 lb s0,25(sp) - 594c: 08097f03 0x8097f03 + 58e4: 0105 addi sp,sp,1 + 58e6: 0300 addi s0,sp,384 + 58e8: 9104 0x9104 + 58ea: 0301 addi t1,t1,0 + 58ec: 0901 addi s2,s2,0 + 58ee: 0008 0x8 + 58f0: 0501 addi a0,a0,0 + 58f2: 000a c.slli zero,0x2 + 58f4: 01910403 lb s0,25(sp) + 58f8: 08097f03 0x8097f03 + 58fc: 0100 addi s0,sp,128 + 58fe: 0105 addi sp,sp,1 + 5900: 0300 addi s0,sp,384 + 5902: 9104 0x9104 + 5904: 0301 addi t1,t1,0 + 5906: 0901 addi s2,s2,0 + 5908: 0008 0x8 + 590a: 0501 addi a0,a0,0 + 590c: 000a c.slli zero,0x2 + 590e: 01910403 lb s0,25(sp) + 5912: 08097f03 0x8097f03 + 5916: 0100 addi s0,sp,128 + 5918: 0105 addi sp,sp,1 + 591a: 0300 addi s0,sp,384 + 591c: 9104 0x9104 + 591e: 0301 addi t1,t1,0 + 5920: 0901 addi s2,s2,0 + 5922: 0008 0x8 + 5924: 0501 addi a0,a0,0 + 5926: 000a c.slli zero,0x2 + 5928: 01910403 lb s0,25(sp) + 592c: 08097f03 0x8097f03 + 5930: 0100 addi s0,sp,128 + 5932: 0105 addi sp,sp,1 + 5934: 0300 addi s0,sp,384 + 5936: 9104 0x9104 + 5938: 0301 addi t1,t1,0 + 593a: 0901 addi s2,s2,0 + 593c: 0004 0x4 + 593e: 0501 addi a0,a0,0 + 5940: 09790303 lb t1,151(s2) + 5944: 0018 0x18 + 5946: 0001 nop + 5948: 0402 c.slli64 s0 + 594a: 0660 addi s0,sp,780 + 594c: 04090203 lb tp,64(s2) 5950: 0100 addi s0,sp,128 - 5952: 0105 addi sp,sp,1 - 5954: 0300 addi s0,sp,384 - 5956: 9104 0x9104 - 5958: 0301 addi t1,t1,0 - 595a: 0901 addi s2,s2,0 - 595c: 0008 0x8 - 595e: 0501 addi a0,a0,0 - 5960: 000a c.slli zero,0x2 - 5962: 01910403 lb s0,25(sp) - 5966: 08097f03 0x8097f03 - 596a: 0100 addi s0,sp,128 - 596c: 0105 addi sp,sp,1 - 596e: 0300 addi s0,sp,384 - 5970: 9104 0x9104 - 5972: 0301 addi t1,t1,0 - 5974: 0901 addi s2,s2,0 - 5976: 0008 0x8 - 5978: 0501 addi a0,a0,0 - 597a: 000a c.slli zero,0x2 - 597c: 01910403 lb s0,25(sp) - 5980: 08097f03 0x8097f03 - 5984: 0100 addi s0,sp,128 - 5986: 0105 addi sp,sp,1 - 5988: 0300 addi s0,sp,384 - 598a: 9104 0x9104 - 598c: 0301 addi t1,t1,0 - 598e: 0901 addi s2,s2,0 - 5990: 0004 0x4 - 5992: 0501 addi a0,a0,0 - 5994: 09790303 lb t1,151(s2) - 5998: 0018 0x18 - 599a: 0001 nop - 599c: 0402 c.slli64 s0 - 599e: 0660 addi s0,sp,780 - 59a0: 04090203 lb tp,64(s2) - 59a4: 0100 addi s0,sp,128 - 59a6: 0200 addi s0,sp,256 - 59a8: 6004 flw fs1,0(s0) - 59aa: 20090003 lb zero,512(s2) - 59ae: 0100 addi s0,sp,128 - 59b0: 0200 addi s0,sp,256 - 59b2: 6004 flw fs1,0(s0) - 59b4: 00090003 lb zero,0(s2) - 59b8: 0100 addi s0,sp,128 - 59ba: 0200 addi s0,sp,256 - 59bc: 6404 flw fs1,8(s0) - 59be: 00090003 lb zero,0(s2) - 59c2: 0100 addi s0,sp,128 - 59c4: 0200 addi s0,sp,256 - 59c6: 6404 flw fs1,8(s0) - 59c8: 00090103 lb sp,0(s2) - 59cc: 0100 addi s0,sp,128 - 59ce: 0200 addi s0,sp,256 - 59d0: 6404 flw fs1,8(s0) - 59d2: 00090003 lb zero,0(s2) - 59d6: 0100 addi s0,sp,128 - 59d8: 0200 addi s0,sp,256 - 59da: 6404 flw fs1,8(s0) - 59dc: 00090003 lb zero,0(s2) + 5952: 0200 addi s0,sp,256 + 5954: 6004 flw fs1,0(s0) + 5956: 20090003 lb zero,512(s2) + 595a: 0100 addi s0,sp,128 + 595c: 0200 addi s0,sp,256 + 595e: 6004 flw fs1,0(s0) + 5960: 00090003 lb zero,0(s2) + 5964: 0100 addi s0,sp,128 + 5966: 0200 addi s0,sp,256 + 5968: 6404 flw fs1,8(s0) + 596a: 00090003 lb zero,0(s2) + 596e: 0100 addi s0,sp,128 + 5970: 0200 addi s0,sp,256 + 5972: 6404 flw fs1,8(s0) + 5974: 00090103 lb sp,0(s2) + 5978: 0100 addi s0,sp,128 + 597a: 0200 addi s0,sp,256 + 597c: 6404 flw fs1,8(s0) + 597e: 00090003 lb zero,0(s2) + 5982: 0100 addi s0,sp,128 + 5984: 0200 addi s0,sp,256 + 5986: 6404 flw fs1,8(s0) + 5988: 00090003 lb zero,0(s2) + 598c: 0100 addi s0,sp,128 + 598e: 0306 slli t1,t1,0x1 + 5990: 0900 addi s0,sp,144 + 5992: 0008 0x8 + 5994: 0001 nop + 5996: 0402 c.slli64 s0 + 5998: 00030603 lb a2,0(t1) + 599c: 1009 c.nop -30 + 599e: 0100 addi s0,sp,128 + 59a0: 0200 addi s0,sp,256 + 59a2: 0304 addi s1,sp,384 + 59a4: 00090003 lb zero,0(s2) + 59a8: 0100 addi s0,sp,128 + 59aa: 0306 slli t1,t1,0x1 + 59ac: 097e slli s2,s2,0x1f + 59ae: 0014 0x14 + 59b0: 0001 nop + 59b2: 0402 c.slli64 s0 + 59b4: 0662 slli a2,a2,0x18 + 59b6: 04090103 lb sp,64(s2) + 59ba: 0100 addi s0,sp,128 + 59bc: 0200 addi s0,sp,256 + 59be: 6204 flw fs1,0(a2) + 59c0: 24090003 lb zero,576(s2) + 59c4: 0100 addi s0,sp,128 + 59c6: 0200 addi s0,sp,256 + 59c8: 6204 flw fs1,0(a2) + 59ca: 00090003 lb zero,0(s2) + 59ce: 0100 addi s0,sp,128 + 59d0: 0306 slli t1,t1,0x1 + 59d2: 0900 addi s0,sp,144 + 59d4: 0004 0x4 + 59d6: 0001 nop + 59d8: 0402 c.slli64 s0 + 59da: 0630 addi a2,sp,776 + 59dc: 0c090103 lb sp,192(s2) 59e0: 0100 addi s0,sp,128 - 59e2: 0306 slli t1,t1,0x1 - 59e4: 0900 addi s0,sp,144 - 59e6: 0008 0x8 - 59e8: 0001 nop - 59ea: 0402 c.slli64 s0 - 59ec: 00030603 lb a2,0(t1) - 59f0: 1009 c.nop -30 - 59f2: 0100 addi s0,sp,128 - 59f4: 0200 addi s0,sp,256 - 59f6: 0304 addi s1,sp,384 - 59f8: 00090003 lb zero,0(s2) - 59fc: 0100 addi s0,sp,128 - 59fe: 0306 slli t1,t1,0x1 - 5a00: 097e slli s2,s2,0x1f - 5a02: 0014 0x14 - 5a04: 0001 nop - 5a06: 0402 c.slli64 s0 - 5a08: 0662 slli a2,a2,0x18 - 5a0a: 04090103 lb sp,64(s2) - 5a0e: 0100 addi s0,sp,128 - 5a10: 0200 addi s0,sp,256 - 5a12: 6204 flw fs1,0(a2) - 5a14: 24090003 lb zero,576(s2) - 5a18: 0100 addi s0,sp,128 - 5a1a: 0200 addi s0,sp,256 - 5a1c: 6204 flw fs1,0(a2) - 5a1e: 00090003 lb zero,0(s2) - 5a22: 0100 addi s0,sp,128 - 5a24: 0306 slli t1,t1,0x1 - 5a26: 0900 addi s0,sp,144 - 5a28: 0004 0x4 - 5a2a: 0001 nop - 5a2c: 0402 c.slli64 s0 - 5a2e: 0630 addi a2,sp,776 - 5a30: 0c090103 lb sp,192(s2) - 5a34: 0100 addi s0,sp,128 - 5a36: 0200 addi s0,sp,256 - 5a38: 3004 fld fs1,32(s0) - 5a3a: 00090003 lb zero,0(s2) - 5a3e: 0100 addi s0,sp,128 - 5a40: 0200 addi s0,sp,256 - 5a42: 3004 fld fs1,32(s0) - 5a44: 00090003 lb zero,0(s2) - 5a48: 0100 addi s0,sp,128 - 5a4a: 0200 addi s0,sp,256 - 5a4c: 3004 fld fs1,32(s0) - 5a4e: 00090003 lb zero,0(s2) - 5a52: 0100 addi s0,sp,128 - 5a54: 0200 addi s0,sp,256 - 5a56: 3004 fld fs1,32(s0) - 5a58: 00090003 lb zero,0(s2) - 5a5c: 0100 addi s0,sp,128 - 5a5e: 0200 addi s0,sp,256 - 5a60: 3004 fld fs1,32(s0) - 5a62: 00090003 lb zero,0(s2) - 5a66: 0100 addi s0,sp,128 - 5a68: 0200 addi s0,sp,256 - 5a6a: 3004 fld fs1,32(s0) - 5a6c: 10090003 lb zero,256(s2) - 5a70: 0100 addi s0,sp,128 - 5a72: 0200 addi s0,sp,256 - 5a74: 3004 fld fs1,32(s0) - 5a76: 00090003 lb zero,0(s2) - 5a7a: 0100 addi s0,sp,128 - 5a7c: 0200 addi s0,sp,256 - 5a7e: 3504 fld fs1,40(a0) - 5a80: 08090003 lb zero,128(s2) - 5a84: 0100 addi s0,sp,128 - 5a86: 0200 addi s0,sp,256 - 5a88: 3504 fld fs1,40(a0) - 5a8a: 00090003 lb zero,0(s2) - 5a8e: 0100 addi s0,sp,128 - 5a90: 0200 addi s0,sp,256 - 5a92: 3504 fld fs1,40(a0) - 5a94: 00090003 lb zero,0(s2) - 5a98: 0100 addi s0,sp,128 - 5a9a: 0200 addi s0,sp,256 - 5a9c: 3504 fld fs1,40(a0) - 5a9e: 08090003 lb zero,128(s2) - 5aa2: 0100 addi s0,sp,128 - 5aa4: 0200 addi s0,sp,256 - 5aa6: 4704 lw s1,8(a4) - 5aa8: 08090003 lb zero,128(s2) - 5aac: 0100 addi s0,sp,128 - 5aae: 0200 addi s0,sp,256 - 5ab0: 4704 lw s1,8(a4) - 5ab2: 00090003 lb zero,0(s2) - 5ab6: 0100 addi s0,sp,128 - 5ab8: 0200 addi s0,sp,256 - 5aba: 4704 lw s1,8(a4) - 5abc: 00090003 lb zero,0(s2) - 5ac0: 0100 addi s0,sp,128 - 5ac2: 0200 addi s0,sp,256 - 5ac4: 4704 lw s1,8(a4) - 5ac6: 00090003 lb zero,0(s2) - 5aca: 0100 addi s0,sp,128 - 5acc: 0200 addi s0,sp,256 - 5ace: 4704 lw s1,8(a4) - 5ad0: 00090003 lb zero,0(s2) - 5ad4: 0100 addi s0,sp,128 - 5ad6: 0200 addi s0,sp,256 - 5ad8: 4704 lw s1,8(a4) - 5ada: 00090003 lb zero,0(s2) - 5ade: 0100 addi s0,sp,128 - 5ae0: 0200 addi s0,sp,256 - 5ae2: 4704 lw s1,8(a4) - 5ae4: 00090003 lb zero,0(s2) - 5ae8: 0100 addi s0,sp,128 - 5aea: 0200 addi s0,sp,256 - 5aec: 4704 lw s1,8(a4) - 5aee: 04090003 lb zero,64(s2) - 5af2: 0100 addi s0,sp,128 - 5af4: 0200 addi s0,sp,256 - 5af6: 4704 lw s1,8(a4) - 5af8: 00090003 lb zero,0(s2) - 5afc: 0100 addi s0,sp,128 - 5afe: 0200 addi s0,sp,256 - 5b00: 4704 lw s1,8(a4) - 5b02: 00090003 lb zero,0(s2) - 5b06: 0100 addi s0,sp,128 - 5b08: 0200 addi s0,sp,256 - 5b0a: 4904 lw s1,16(a0) - 5b0c: 08090003 lb zero,128(s2) - 5b10: 0100 addi s0,sp,128 - 5b12: 0200 addi s0,sp,256 - 5b14: 4c04 lw s1,24(s0) - 5b16: 04090003 lb zero,64(s2) - 5b1a: 0100 addi s0,sp,128 - 5b1c: 0306 slli t1,t1,0x1 - 5b1e: 0900 addi s0,sp,144 - 5b20: 000c 0xc - 5b22: 0001 nop - 5b24: 0402 c.slli64 s0 - 5b26: 0651 addi a2,a2,20 - 5b28: 0c090003 lb zero,192(s2) - 5b2c: 0100 addi s0,sp,128 - 5b2e: 0200 addi s0,sp,256 - 5b30: 5104 lw s1,32(a0) - 5b32: 14090003 lb zero,320(s2) - 5b36: 0100 addi s0,sp,128 - 5b38: 0200 addi s0,sp,256 - 5b3a: 5104 lw s1,32(a0) - 5b3c: 00090003 lb zero,0(s2) + 59e2: 0200 addi s0,sp,256 + 59e4: 3004 fld fs1,32(s0) + 59e6: 00090003 lb zero,0(s2) + 59ea: 0100 addi s0,sp,128 + 59ec: 0200 addi s0,sp,256 + 59ee: 3004 fld fs1,32(s0) + 59f0: 00090003 lb zero,0(s2) + 59f4: 0100 addi s0,sp,128 + 59f6: 0200 addi s0,sp,256 + 59f8: 3004 fld fs1,32(s0) + 59fa: 00090003 lb zero,0(s2) + 59fe: 0100 addi s0,sp,128 + 5a00: 0200 addi s0,sp,256 + 5a02: 3004 fld fs1,32(s0) + 5a04: 00090003 lb zero,0(s2) + 5a08: 0100 addi s0,sp,128 + 5a0a: 0200 addi s0,sp,256 + 5a0c: 3004 fld fs1,32(s0) + 5a0e: 00090003 lb zero,0(s2) + 5a12: 0100 addi s0,sp,128 + 5a14: 0200 addi s0,sp,256 + 5a16: 3004 fld fs1,32(s0) + 5a18: 10090003 lb zero,256(s2) + 5a1c: 0100 addi s0,sp,128 + 5a1e: 0200 addi s0,sp,256 + 5a20: 3004 fld fs1,32(s0) + 5a22: 00090003 lb zero,0(s2) + 5a26: 0100 addi s0,sp,128 + 5a28: 0200 addi s0,sp,256 + 5a2a: 3504 fld fs1,40(a0) + 5a2c: 08090003 lb zero,128(s2) + 5a30: 0100 addi s0,sp,128 + 5a32: 0200 addi s0,sp,256 + 5a34: 3504 fld fs1,40(a0) + 5a36: 00090003 lb zero,0(s2) + 5a3a: 0100 addi s0,sp,128 + 5a3c: 0200 addi s0,sp,256 + 5a3e: 3504 fld fs1,40(a0) + 5a40: 00090003 lb zero,0(s2) + 5a44: 0100 addi s0,sp,128 + 5a46: 0200 addi s0,sp,256 + 5a48: 3504 fld fs1,40(a0) + 5a4a: 08090003 lb zero,128(s2) + 5a4e: 0100 addi s0,sp,128 + 5a50: 0200 addi s0,sp,256 + 5a52: 4704 lw s1,8(a4) + 5a54: 08090003 lb zero,128(s2) + 5a58: 0100 addi s0,sp,128 + 5a5a: 0200 addi s0,sp,256 + 5a5c: 4704 lw s1,8(a4) + 5a5e: 00090003 lb zero,0(s2) + 5a62: 0100 addi s0,sp,128 + 5a64: 0200 addi s0,sp,256 + 5a66: 4704 lw s1,8(a4) + 5a68: 00090003 lb zero,0(s2) + 5a6c: 0100 addi s0,sp,128 + 5a6e: 0200 addi s0,sp,256 + 5a70: 4704 lw s1,8(a4) + 5a72: 00090003 lb zero,0(s2) + 5a76: 0100 addi s0,sp,128 + 5a78: 0200 addi s0,sp,256 + 5a7a: 4704 lw s1,8(a4) + 5a7c: 00090003 lb zero,0(s2) + 5a80: 0100 addi s0,sp,128 + 5a82: 0200 addi s0,sp,256 + 5a84: 4704 lw s1,8(a4) + 5a86: 00090003 lb zero,0(s2) + 5a8a: 0100 addi s0,sp,128 + 5a8c: 0200 addi s0,sp,256 + 5a8e: 4704 lw s1,8(a4) + 5a90: 00090003 lb zero,0(s2) + 5a94: 0100 addi s0,sp,128 + 5a96: 0200 addi s0,sp,256 + 5a98: 4704 lw s1,8(a4) + 5a9a: 04090003 lb zero,64(s2) + 5a9e: 0100 addi s0,sp,128 + 5aa0: 0200 addi s0,sp,256 + 5aa2: 4704 lw s1,8(a4) + 5aa4: 00090003 lb zero,0(s2) + 5aa8: 0100 addi s0,sp,128 + 5aaa: 0200 addi s0,sp,256 + 5aac: 4704 lw s1,8(a4) + 5aae: 00090003 lb zero,0(s2) + 5ab2: 0100 addi s0,sp,128 + 5ab4: 0200 addi s0,sp,256 + 5ab6: 4904 lw s1,16(a0) + 5ab8: 08090003 lb zero,128(s2) + 5abc: 0100 addi s0,sp,128 + 5abe: 0200 addi s0,sp,256 + 5ac0: 4c04 lw s1,24(s0) + 5ac2: 04090003 lb zero,64(s2) + 5ac6: 0100 addi s0,sp,128 + 5ac8: 0306 slli t1,t1,0x1 + 5aca: 0900 addi s0,sp,144 + 5acc: 000c 0xc + 5ace: 0001 nop + 5ad0: 0402 c.slli64 s0 + 5ad2: 0651 addi a2,a2,20 + 5ad4: 0c090003 lb zero,192(s2) + 5ad8: 0100 addi s0,sp,128 + 5ada: 0200 addi s0,sp,256 + 5adc: 5104 lw s1,32(a0) + 5ade: 14090003 lb zero,320(s2) + 5ae2: 0100 addi s0,sp,128 + 5ae4: 0200 addi s0,sp,256 + 5ae6: 5104 lw s1,32(a0) + 5ae8: 00090003 lb zero,0(s2) + 5aec: 0100 addi s0,sp,128 + 5aee: 0200 addi s0,sp,256 + 5af0: 4b04 lw s1,16(a4) + 5af2: 1c090003 lb zero,448(s2) + 5af6: 0100 addi s0,sp,128 + 5af8: 0200 addi s0,sp,256 + 5afa: 4b04 lw s1,16(a4) + 5afc: 18090003 lb zero,384(s2) + 5b00: 0100 addi s0,sp,128 + 5b02: 0200 addi s0,sp,256 + 5b04: 4e04 lw s1,24(a2) + 5b06: 0306 slli t1,t1,0x1 + 5b08: 0900 addi s0,sp,144 + 5b0a: 0004 0x4 + 5b0c: 0001 nop + 5b0e: 0402 c.slli64 s0 + 5b10: 064e slli a2,a2,0x13 + 5b12: 14090003 lb zero,320(s2) + 5b16: 0100 addi s0,sp,128 + 5b18: 0200 addi s0,sp,256 + 5b1a: 4e04 lw s1,24(a2) + 5b1c: 08090003 lb zero,128(s2) + 5b20: 0100 addi s0,sp,128 + 5b22: 0200 addi s0,sp,256 + 5b24: 5204 lw s1,32(a2) + 5b26: 14090003 lb zero,320(s2) + 5b2a: 0100 addi s0,sp,128 + 5b2c: 0200 addi s0,sp,256 + 5b2e: 5504 lw s1,40(a0) + 5b30: 0306 slli t1,t1,0x1 + 5b32: 0900 addi s0,sp,144 + 5b34: 0008 0x8 + 5b36: 0001 nop + 5b38: 0402 c.slli64 s0 + 5b3a: 0655 addi a2,a2,21 + 5b3c: 18090003 lb zero,384(s2) 5b40: 0100 addi s0,sp,128 5b42: 0200 addi s0,sp,256 - 5b44: 4b04 lw s1,16(a4) - 5b46: 1c090003 lb zero,448(s2) - 5b4a: 0100 addi s0,sp,128 - 5b4c: 0200 addi s0,sp,256 - 5b4e: 4b04 lw s1,16(a4) - 5b50: 18090003 lb zero,384(s2) - 5b54: 0100 addi s0,sp,128 - 5b56: 0200 addi s0,sp,256 - 5b58: 4e04 lw s1,24(a2) - 5b5a: 0306 slli t1,t1,0x1 - 5b5c: 0900 addi s0,sp,144 - 5b5e: 0004 0x4 - 5b60: 0001 nop - 5b62: 0402 c.slli64 s0 - 5b64: 064e slli a2,a2,0x13 - 5b66: 14090003 lb zero,320(s2) + 5b44: 5704 lw s1,40(a4) + 5b46: 0306 slli t1,t1,0x1 + 5b48: 0900 addi s0,sp,144 + 5b4a: 0008 0x8 + 5b4c: 0001 nop + 5b4e: 0402 c.slli64 s0 + 5b50: 0654 addi a3,sp,772 + 5b52: 08090003 lb zero,128(s2) + 5b56: 0100 addi s0,sp,128 + 5b58: 0200 addi s0,sp,256 + 5b5a: 5404 lw s1,40(s0) + 5b5c: 28090003 lb zero,640(s2) + 5b60: 0100 addi s0,sp,128 + 5b62: 0200 addi s0,sp,256 + 5b64: 5804 lw s1,48(s0) + 5b66: 04090003 lb zero,64(s2) 5b6a: 0100 addi s0,sp,128 5b6c: 0200 addi s0,sp,256 - 5b6e: 4e04 lw s1,24(a2) - 5b70: 08090003 lb zero,128(s2) + 5b6e: 5804 lw s1,48(s0) + 5b70: 10090003 lb zero,256(s2) 5b74: 0100 addi s0,sp,128 5b76: 0200 addi s0,sp,256 - 5b78: 5204 lw s1,32(a2) - 5b7a: 14090003 lb zero,320(s2) + 5b78: 5704 lw s1,40(a4) + 5b7a: 04090003 lb zero,64(s2) 5b7e: 0100 addi s0,sp,128 5b80: 0200 addi s0,sp,256 - 5b82: 5504 lw s1,40(a0) - 5b84: 0306 slli t1,t1,0x1 - 5b86: 0900 addi s0,sp,144 - 5b88: 0008 0x8 - 5b8a: 0001 nop - 5b8c: 0402 c.slli64 s0 - 5b8e: 0655 addi a2,a2,21 - 5b90: 18090003 lb zero,384(s2) - 5b94: 0100 addi s0,sp,128 - 5b96: 0200 addi s0,sp,256 - 5b98: 5704 lw s1,40(a4) - 5b9a: 0306 slli t1,t1,0x1 - 5b9c: 0900 addi s0,sp,144 - 5b9e: 0008 0x8 - 5ba0: 0001 nop - 5ba2: 0402 c.slli64 s0 - 5ba4: 0654 addi a3,sp,772 - 5ba6: 08090003 lb zero,128(s2) - 5baa: 0100 addi s0,sp,128 - 5bac: 0200 addi s0,sp,256 - 5bae: 5404 lw s1,40(s0) - 5bb0: 28090003 lb zero,640(s2) - 5bb4: 0100 addi s0,sp,128 - 5bb6: 0200 addi s0,sp,256 - 5bb8: 5804 lw s1,48(s0) - 5bba: 04090003 lb zero,64(s2) - 5bbe: 0100 addi s0,sp,128 - 5bc0: 0200 addi s0,sp,256 - 5bc2: 5804 lw s1,48(s0) - 5bc4: 10090003 lb zero,256(s2) - 5bc8: 0100 addi s0,sp,128 - 5bca: 0200 addi s0,sp,256 - 5bcc: 5704 lw s1,40(a4) - 5bce: 04090003 lb zero,64(s2) - 5bd2: 0100 addi s0,sp,128 - 5bd4: 0200 addi s0,sp,256 - 5bd6: 5904 lw s1,48(a0) - 5bd8: 04090003 lb zero,64(s2) - 5bdc: 0100 addi s0,sp,128 - 5bde: 0200 addi s0,sp,256 - 5be0: 5904 lw s1,48(a0) - 5be2: 00090003 lb zero,0(s2) - 5be6: 0100 addi s0,sp,128 - 5be8: 0200 addi s0,sp,256 - 5bea: 5904 lw s1,48(a0) - 5bec: 00090003 lb zero,0(s2) - 5bf0: 0100 addi s0,sp,128 - 5bf2: 0200 addi s0,sp,256 - 5bf4: 5904 lw s1,48(a0) - 5bf6: 10090003 lb zero,256(s2) - 5bfa: 0100 addi s0,sp,128 - 5bfc: 0200 addi s0,sp,256 - 5bfe: 5904 lw s1,48(a0) - 5c00: 00090003 lb zero,0(s2) - 5c04: 0100 addi s0,sp,128 - 5c06: 0200 addi s0,sp,256 - 5c08: 5904 lw s1,48(a0) - 5c0a: 00090003 lb zero,0(s2) - 5c0e: 0100 addi s0,sp,128 - 5c10: 0200 addi s0,sp,256 - 5c12: 5a04 lw s1,48(a2) - 5c14: 08090003 lb zero,128(s2) - 5c18: 0100 addi s0,sp,128 - 5c1a: 0200 addi s0,sp,256 - 5c1c: 5a04 lw s1,48(a2) - 5c1e: 00090003 lb zero,0(s2) - 5c22: 0100 addi s0,sp,128 - 5c24: 0200 addi s0,sp,256 - 5c26: 5a04 lw s1,48(a2) - 5c28: 00090003 lb zero,0(s2) - 5c2c: 0100 addi s0,sp,128 - 5c2e: 0200 addi s0,sp,256 - 5c30: 5a04 lw s1,48(a2) - 5c32: 00090003 lb zero,0(s2) - 5c36: 0100 addi s0,sp,128 - 5c38: 0200 addi s0,sp,256 - 5c3a: 5c04 lw s1,56(s0) - 5c3c: 08090003 lb zero,128(s2) - 5c40: 0100 addi s0,sp,128 - 5c42: 0200 addi s0,sp,256 - 5c44: 5c04 lw s1,56(s0) - 5c46: 00090003 lb zero,0(s2) - 5c4a: 0100 addi s0,sp,128 - 5c4c: 0200 addi s0,sp,256 - 5c4e: 5c04 lw s1,56(s0) - 5c50: 00090003 lb zero,0(s2) - 5c54: 0100 addi s0,sp,128 - 5c56: 0200 addi s0,sp,256 - 5c58: 5c04 lw s1,56(s0) - 5c5a: 10090003 lb zero,256(s2) - 5c5e: 0100 addi s0,sp,128 - 5c60: 0200 addi s0,sp,256 - 5c62: 5c04 lw s1,56(s0) - 5c64: 0c090003 lb zero,192(s2) - 5c68: 0100 addi s0,sp,128 - 5c6a: 0200 addi s0,sp,256 - 5c6c: 5c04 lw s1,56(s0) - 5c6e: 00090003 lb zero,0(s2) - 5c72: 0100 addi s0,sp,128 - 5c74: 0200 addi s0,sp,256 - 5c76: 5c04 lw s1,56(s0) - 5c78: 0c090003 lb zero,192(s2) - 5c7c: 0100 addi s0,sp,128 - 5c7e: 0200 addi s0,sp,256 - 5c80: 5c04 lw s1,56(s0) - 5c82: 04090003 lb zero,64(s2) - 5c86: 0100 addi s0,sp,128 - 5c88: 0200 addi s0,sp,256 - 5c8a: 5b04 lw s1,48(a4) - 5c8c: 0c090003 lb zero,192(s2) - 5c90: 0100 addi s0,sp,128 - 5c92: 0200 addi s0,sp,256 - 5c94: 5b04 lw s1,48(a4) - 5c96: 00090003 lb zero,0(s2) - 5c9a: 0100 addi s0,sp,128 - 5c9c: 0200 addi s0,sp,256 - 5c9e: 6a04 flw fs1,16(a2) - 5ca0: 0c090003 lb zero,192(s2) - 5ca4: 0100 addi s0,sp,128 - 5ca6: 0200 addi s0,sp,256 - 5ca8: 6a04 flw fs1,16(a2) - 5caa: 00090003 lb zero,0(s2) - 5cae: 0100 addi s0,sp,128 - 5cb0: 0200 addi s0,sp,256 - 5cb2: 6a04 flw fs1,16(a2) - 5cb4: 10090003 lb zero,256(s2) - 5cb8: 0100 addi s0,sp,128 - 5cba: 0200 addi s0,sp,256 - 5cbc: 7404 flw fs1,40(s0) - 5cbe: 10090003 lb zero,256(s2) - 5cc2: 0100 addi s0,sp,128 - 5cc4: 0200 addi s0,sp,256 - 5cc6: 7404 flw fs1,40(s0) - 5cc8: 1c090003 lb zero,448(s2) - 5ccc: 0100 addi s0,sp,128 - 5cce: 0200 addi s0,sp,256 - 5cd0: 7404 flw fs1,40(s0) - 5cd2: 00090003 lb zero,0(s2) - 5cd6: 0100 addi s0,sp,128 - 5cd8: 0200 addi s0,sp,256 - 5cda: 7504 flw fs1,40(a0) - 5cdc: 04090003 lb zero,64(s2) - 5ce0: 0100 addi s0,sp,128 - 5ce2: 0200 addi s0,sp,256 - 5ce4: 7504 flw fs1,40(a0) - 5ce6: 0c090003 lb zero,192(s2) - 5cea: 0100 addi s0,sp,128 - 5cec: 0200 addi s0,sp,256 - 5cee: 0304 addi s1,sp,384 - 5cf0: 00090003 lb zero,0(s2) - 5cf4: 0100 addi s0,sp,128 - 5cf6: 0200 addi s0,sp,256 - 5cf8: 4804 lw s1,16(s0) - 5cfa: 08090003 lb zero,128(s2) - 5cfe: 0100 addi s0,sp,128 - 5d00: 0200 addi s0,sp,256 - 5d02: 4804 lw s1,16(s0) - 5d04: 00090003 lb zero,0(s2) - 5d08: 0100 addi s0,sp,128 - 5d0a: 0200 addi s0,sp,256 - 5d0c: 7c04 flw fs1,56(s0) - 5d0e: 24090003 lb zero,576(s2) - 5d12: 0100 addi s0,sp,128 - 5d14: 0200 addi s0,sp,256 - 5d16: 7c04 flw fs1,56(s0) - 5d18: 0c090003 lb zero,192(s2) - 5d1c: 0100 addi s0,sp,128 - 5d1e: 0200 addi s0,sp,256 - 5d20: 7c04 flw fs1,56(s0) - 5d22: 00090003 lb zero,0(s2) - 5d26: 0100 addi s0,sp,128 - 5d28: 0200 addi s0,sp,256 - 5d2a: 7c04 flw fs1,56(s0) - 5d2c: 00090003 lb zero,0(s2) - 5d30: 0100 addi s0,sp,128 - 5d32: 0200 addi s0,sp,256 - 5d34: 7c04 flw fs1,56(s0) - 5d36: 00090003 lb zero,0(s2) - 5d3a: 0100 addi s0,sp,128 - 5d3c: 0200 addi s0,sp,256 - 5d3e: 7c04 flw fs1,56(s0) - 5d40: 00090003 lb zero,0(s2) - 5d44: 0100 addi s0,sp,128 - 5d46: 0200 addi s0,sp,256 - 5d48: 7c04 flw fs1,56(s0) - 5d4a: 00090003 lb zero,0(s2) - 5d4e: 0100 addi s0,sp,128 - 5d50: 0200 addi s0,sp,256 - 5d52: 7c04 flw fs1,56(s0) - 5d54: 00090003 lb zero,0(s2) - 5d58: 0100 addi s0,sp,128 - 5d5a: 0200 addi s0,sp,256 - 5d5c: 7c04 flw fs1,56(s0) - 5d5e: 00090003 lb zero,0(s2) - 5d62: 0100 addi s0,sp,128 - 5d64: 0200 addi s0,sp,256 - 5d66: 7c04 flw fs1,56(s0) - 5d68: 00090003 lb zero,0(s2) - 5d6c: 0100 addi s0,sp,128 - 5d6e: 0200 addi s0,sp,256 - 5d70: 7c04 flw fs1,56(s0) - 5d72: 00090003 lb zero,0(s2) - 5d76: 0100 addi s0,sp,128 - 5d78: 0200 addi s0,sp,256 - 5d7a: 7c04 flw fs1,56(s0) - 5d7c: 00090003 lb zero,0(s2) - 5d80: 0100 addi s0,sp,128 - 5d82: 0200 addi s0,sp,256 - 5d84: 7c04 flw fs1,56(s0) - 5d86: 00090003 lb zero,0(s2) - 5d8a: 0100 addi s0,sp,128 - 5d8c: 0200 addi s0,sp,256 - 5d8e: 7c04 flw fs1,56(s0) - 5d90: 00090003 lb zero,0(s2) + 5b82: 5904 lw s1,48(a0) + 5b84: 04090003 lb zero,64(s2) + 5b88: 0100 addi s0,sp,128 + 5b8a: 0200 addi s0,sp,256 + 5b8c: 5904 lw s1,48(a0) + 5b8e: 00090003 lb zero,0(s2) + 5b92: 0100 addi s0,sp,128 + 5b94: 0200 addi s0,sp,256 + 5b96: 5904 lw s1,48(a0) + 5b98: 00090003 lb zero,0(s2) + 5b9c: 0100 addi s0,sp,128 + 5b9e: 0200 addi s0,sp,256 + 5ba0: 5904 lw s1,48(a0) + 5ba2: 10090003 lb zero,256(s2) + 5ba6: 0100 addi s0,sp,128 + 5ba8: 0200 addi s0,sp,256 + 5baa: 5904 lw s1,48(a0) + 5bac: 00090003 lb zero,0(s2) + 5bb0: 0100 addi s0,sp,128 + 5bb2: 0200 addi s0,sp,256 + 5bb4: 5904 lw s1,48(a0) + 5bb6: 00090003 lb zero,0(s2) + 5bba: 0100 addi s0,sp,128 + 5bbc: 0200 addi s0,sp,256 + 5bbe: 5a04 lw s1,48(a2) + 5bc0: 08090003 lb zero,128(s2) + 5bc4: 0100 addi s0,sp,128 + 5bc6: 0200 addi s0,sp,256 + 5bc8: 5a04 lw s1,48(a2) + 5bca: 00090003 lb zero,0(s2) + 5bce: 0100 addi s0,sp,128 + 5bd0: 0200 addi s0,sp,256 + 5bd2: 5a04 lw s1,48(a2) + 5bd4: 00090003 lb zero,0(s2) + 5bd8: 0100 addi s0,sp,128 + 5bda: 0200 addi s0,sp,256 + 5bdc: 5a04 lw s1,48(a2) + 5bde: 00090003 lb zero,0(s2) + 5be2: 0100 addi s0,sp,128 + 5be4: 0200 addi s0,sp,256 + 5be6: 5c04 lw s1,56(s0) + 5be8: 08090003 lb zero,128(s2) + 5bec: 0100 addi s0,sp,128 + 5bee: 0200 addi s0,sp,256 + 5bf0: 5c04 lw s1,56(s0) + 5bf2: 00090003 lb zero,0(s2) + 5bf6: 0100 addi s0,sp,128 + 5bf8: 0200 addi s0,sp,256 + 5bfa: 5c04 lw s1,56(s0) + 5bfc: 00090003 lb zero,0(s2) + 5c00: 0100 addi s0,sp,128 + 5c02: 0200 addi s0,sp,256 + 5c04: 5c04 lw s1,56(s0) + 5c06: 10090003 lb zero,256(s2) + 5c0a: 0100 addi s0,sp,128 + 5c0c: 0200 addi s0,sp,256 + 5c0e: 5c04 lw s1,56(s0) + 5c10: 0c090003 lb zero,192(s2) + 5c14: 0100 addi s0,sp,128 + 5c16: 0200 addi s0,sp,256 + 5c18: 5c04 lw s1,56(s0) + 5c1a: 00090003 lb zero,0(s2) + 5c1e: 0100 addi s0,sp,128 + 5c20: 0200 addi s0,sp,256 + 5c22: 5c04 lw s1,56(s0) + 5c24: 0c090003 lb zero,192(s2) + 5c28: 0100 addi s0,sp,128 + 5c2a: 0200 addi s0,sp,256 + 5c2c: 5c04 lw s1,56(s0) + 5c2e: 04090003 lb zero,64(s2) + 5c32: 0100 addi s0,sp,128 + 5c34: 0200 addi s0,sp,256 + 5c36: 5b04 lw s1,48(a4) + 5c38: 0c090003 lb zero,192(s2) + 5c3c: 0100 addi s0,sp,128 + 5c3e: 0200 addi s0,sp,256 + 5c40: 5b04 lw s1,48(a4) + 5c42: 00090003 lb zero,0(s2) + 5c46: 0100 addi s0,sp,128 + 5c48: 0200 addi s0,sp,256 + 5c4a: 6a04 flw fs1,16(a2) + 5c4c: 0c090003 lb zero,192(s2) + 5c50: 0100 addi s0,sp,128 + 5c52: 0200 addi s0,sp,256 + 5c54: 6a04 flw fs1,16(a2) + 5c56: 00090003 lb zero,0(s2) + 5c5a: 0100 addi s0,sp,128 + 5c5c: 0200 addi s0,sp,256 + 5c5e: 6a04 flw fs1,16(a2) + 5c60: 10090003 lb zero,256(s2) + 5c64: 0100 addi s0,sp,128 + 5c66: 0200 addi s0,sp,256 + 5c68: 7404 flw fs1,40(s0) + 5c6a: 10090003 lb zero,256(s2) + 5c6e: 0100 addi s0,sp,128 + 5c70: 0200 addi s0,sp,256 + 5c72: 7404 flw fs1,40(s0) + 5c74: 1c090003 lb zero,448(s2) + 5c78: 0100 addi s0,sp,128 + 5c7a: 0200 addi s0,sp,256 + 5c7c: 7404 flw fs1,40(s0) + 5c7e: 00090003 lb zero,0(s2) + 5c82: 0100 addi s0,sp,128 + 5c84: 0200 addi s0,sp,256 + 5c86: 7504 flw fs1,40(a0) + 5c88: 04090003 lb zero,64(s2) + 5c8c: 0100 addi s0,sp,128 + 5c8e: 0200 addi s0,sp,256 + 5c90: 7504 flw fs1,40(a0) + 5c92: 0c090003 lb zero,192(s2) + 5c96: 0100 addi s0,sp,128 + 5c98: 0200 addi s0,sp,256 + 5c9a: 0304 addi s1,sp,384 + 5c9c: 00090003 lb zero,0(s2) + 5ca0: 0100 addi s0,sp,128 + 5ca2: 0200 addi s0,sp,256 + 5ca4: 4804 lw s1,16(s0) + 5ca6: 08090003 lb zero,128(s2) + 5caa: 0100 addi s0,sp,128 + 5cac: 0200 addi s0,sp,256 + 5cae: 4804 lw s1,16(s0) + 5cb0: 00090003 lb zero,0(s2) + 5cb4: 0100 addi s0,sp,128 + 5cb6: 0200 addi s0,sp,256 + 5cb8: 7c04 flw fs1,56(s0) + 5cba: 24090003 lb zero,576(s2) + 5cbe: 0100 addi s0,sp,128 + 5cc0: 0200 addi s0,sp,256 + 5cc2: 7c04 flw fs1,56(s0) + 5cc4: 0c090003 lb zero,192(s2) + 5cc8: 0100 addi s0,sp,128 + 5cca: 0200 addi s0,sp,256 + 5ccc: 7c04 flw fs1,56(s0) + 5cce: 00090003 lb zero,0(s2) + 5cd2: 0100 addi s0,sp,128 + 5cd4: 0200 addi s0,sp,256 + 5cd6: 7c04 flw fs1,56(s0) + 5cd8: 00090003 lb zero,0(s2) + 5cdc: 0100 addi s0,sp,128 + 5cde: 0200 addi s0,sp,256 + 5ce0: 7c04 flw fs1,56(s0) + 5ce2: 00090003 lb zero,0(s2) + 5ce6: 0100 addi s0,sp,128 + 5ce8: 0200 addi s0,sp,256 + 5cea: 7c04 flw fs1,56(s0) + 5cec: 00090003 lb zero,0(s2) + 5cf0: 0100 addi s0,sp,128 + 5cf2: 0200 addi s0,sp,256 + 5cf4: 7c04 flw fs1,56(s0) + 5cf6: 00090003 lb zero,0(s2) + 5cfa: 0100 addi s0,sp,128 + 5cfc: 0200 addi s0,sp,256 + 5cfe: 7c04 flw fs1,56(s0) + 5d00: 00090003 lb zero,0(s2) + 5d04: 0100 addi s0,sp,128 + 5d06: 0200 addi s0,sp,256 + 5d08: 7c04 flw fs1,56(s0) + 5d0a: 00090003 lb zero,0(s2) + 5d0e: 0100 addi s0,sp,128 + 5d10: 0200 addi s0,sp,256 + 5d12: 7c04 flw fs1,56(s0) + 5d14: 00090003 lb zero,0(s2) + 5d18: 0100 addi s0,sp,128 + 5d1a: 0200 addi s0,sp,256 + 5d1c: 7c04 flw fs1,56(s0) + 5d1e: 00090003 lb zero,0(s2) + 5d22: 0100 addi s0,sp,128 + 5d24: 0200 addi s0,sp,256 + 5d26: 7c04 flw fs1,56(s0) + 5d28: 00090003 lb zero,0(s2) + 5d2c: 0100 addi s0,sp,128 + 5d2e: 0200 addi s0,sp,256 + 5d30: 7c04 flw fs1,56(s0) + 5d32: 00090003 lb zero,0(s2) + 5d36: 0100 addi s0,sp,128 + 5d38: 0200 addi s0,sp,256 + 5d3a: 7c04 flw fs1,56(s0) + 5d3c: 00090003 lb zero,0(s2) + 5d40: 0100 addi s0,sp,128 + 5d42: 0200 addi s0,sp,256 + 5d44: 7c04 flw fs1,56(s0) + 5d46: 00090003 lb zero,0(s2) + 5d4a: 0100 addi s0,sp,128 + 5d4c: 0200 addi s0,sp,256 + 5d4e: 7c04 flw fs1,56(s0) + 5d50: 00090003 lb zero,0(s2) + 5d54: 0100 addi s0,sp,128 + 5d56: 0200 addi s0,sp,256 + 5d58: 7c04 flw fs1,56(s0) + 5d5a: 00090003 lb zero,0(s2) + 5d5e: 0100 addi s0,sp,128 + 5d60: 0200 addi s0,sp,256 + 5d62: 0404 addi s1,sp,512 + 5d64: 08090003 lb zero,128(s2) + 5d68: 0100 addi s0,sp,128 + 5d6a: 0200 addi s0,sp,256 + 5d6c: 0404 addi s1,sp,512 + 5d6e: 00090003 lb zero,0(s2) + 5d72: 0100 addi s0,sp,128 + 5d74: 0200 addi s0,sp,256 + 5d76: 0404 addi s1,sp,512 + 5d78: 14090003 lb zero,320(s2) + 5d7c: 0100 addi s0,sp,128 + 5d7e: 08090003 lb zero,128(s2) + 5d82: 0100 addi s0,sp,128 + 5d84: 00090003 lb zero,0(s2) + 5d88: 0100 addi s0,sp,128 + 5d8a: 00090003 lb zero,0(s2) + 5d8e: 0100 addi s0,sp,128 + 5d90: 14090003 lb zero,320(s2) 5d94: 0100 addi s0,sp,128 - 5d96: 0200 addi s0,sp,256 - 5d98: 7c04 flw fs1,56(s0) - 5d9a: 00090003 lb zero,0(s2) - 5d9e: 0100 addi s0,sp,128 - 5da0: 0200 addi s0,sp,256 - 5da2: 7c04 flw fs1,56(s0) - 5da4: 00090003 lb zero,0(s2) - 5da8: 0100 addi s0,sp,128 - 5daa: 0200 addi s0,sp,256 - 5dac: 7c04 flw fs1,56(s0) - 5dae: 00090003 lb zero,0(s2) + 5d96: 0c09 addi s8,s8,2 + 5d98: 0000 unimp + 5d9a: 0101 addi sp,sp,0 + 5d9c: 2825 jal 5dd4 <_start-0x7fffa22c> + 5d9e: 0000 unimp + 5da0: 00910003 lb zero,9(sp) + 5da4: 0000 unimp + 5da6: 0101 addi sp,sp,0 + 5da8: 000d0efb 0xd0efb + 5dac: 0101 addi sp,sp,0 + 5dae: 0101 addi sp,sp,0 + 5db0: 0000 unimp 5db2: 0100 addi s0,sp,128 - 5db4: 0200 addi s0,sp,256 - 5db6: 0404 addi s1,sp,512 - 5db8: 08090003 lb zero,128(s2) - 5dbc: 0100 addi s0,sp,128 - 5dbe: 0200 addi s0,sp,256 - 5dc0: 0404 addi s1,sp,512 - 5dc2: 00090003 lb zero,0(s2) - 5dc6: 0100 addi s0,sp,128 - 5dc8: 0200 addi s0,sp,256 - 5dca: 0404 addi s1,sp,512 - 5dcc: 14090003 lb zero,320(s2) - 5dd0: 0100 addi s0,sp,128 - 5dd2: 08090003 lb zero,128(s2) - 5dd6: 0100 addi s0,sp,128 - 5dd8: 00090003 lb zero,0(s2) - 5ddc: 0100 addi s0,sp,128 - 5dde: 00090003 lb zero,0(s2) - 5de2: 0100 addi s0,sp,128 - 5de4: 14090003 lb zero,320(s2) - 5de8: 0100 addi s0,sp,128 - 5dea: 0c09 addi s8,s8,2 - 5dec: 0000 unimp - 5dee: 0101 addi sp,sp,0 - 5df0: 2825 jal 5e28 <_start-0x7fffa1d8> - 5df2: 0000 unimp - 5df4: 00910003 lb zero,9(sp) - 5df8: 0000 unimp - 5dfa: 0101 addi sp,sp,0 - 5dfc: 000d0efb 0xd0efb - 5e00: 0101 addi sp,sp,0 - 5e02: 0101 addi sp,sp,0 - 5e04: 0000 unimp - 5e06: 0100 addi s0,sp,128 - 5e08: 0000 unimp - 5e0a: 2e01 jal 611a <_start-0x7fff9ee6> - 5e0c: 2f2e fld ft10,200(sp) - 5e0e: 2e2e fld ft8,200(sp) - 5e10: 2f2e2e2f 0x2f2e2e2f - 5e14: 2e2e fld ft8,200(sp) - 5e16: 7369722f 0x7369722f - 5e1a: 672d7663 bgeu s10,s2,6486 <_start-0x7fff9b7a> - 5e1e: 6c2f6363 bltu t5,sp,64e4 <_start-0x7fff9b1c> - 5e22: 6269 lui tp,0x1a - 5e24: 2f636367 0x2f636367 - 5e28: 74666f73 csrrsi t5,0x746,12 - 5e2c: 662d lui a2,0xb - 5e2e: 0070 addi a2,sp,12 - 5e30: 2e2e fld ft8,200(sp) - 5e32: 2f2e2e2f 0x2f2e2e2f - 5e36: 2e2e fld ft8,200(sp) - 5e38: 2f2e2e2f 0x2f2e2e2f - 5e3c: 6972 flw fs2,28(sp) - 5e3e: 2d766373 csrrsi t1,0x2d7,12 - 5e42: 2f636367 0x2f636367 - 5e46: 696c flw fa1,84(a0) - 5e48: 6762 flw fa4,24(sp) - 5e4a: 2e2f6363 bltu t5,sp,6130 <_start-0x7fff9ed0> - 5e4e: 2f2e fld ft10,200(sp) - 5e50: 6e69 lui t3,0x1a - 5e52: 64756c63 bltu a0,t2,64aa <_start-0x7fff9b56> - 5e56: 0065 c.nop 25 - 5e58: 7300 flw fs0,32(a4) - 5e5a: 6275 lui tp,0x1d - 5e5c: 6674 flw fa3,76(a2) - 5e5e: 00632e33 slt t3,t1,t1 - 5e62: 0001 nop - 5e64: 7300 flw fs0,32(a4) - 5e66: 2d74666f jal a2,4c93c <_start-0x7ffb36c4> - 5e6a: 7066 flw ft0,120(sp) - 5e6c: 682e flw fa6,200(sp) - 5e6e: 0100 addi s0,sp,128 + 5db4: 0000 unimp + 5db6: 2e01 jal 60c6 <_start-0x7fff9f3a> + 5db8: 2f2e fld ft10,200(sp) + 5dba: 2e2e fld ft8,200(sp) + 5dbc: 2f2e2e2f 0x2f2e2e2f + 5dc0: 2e2e fld ft8,200(sp) + 5dc2: 7369722f 0x7369722f + 5dc6: 672d7663 bgeu s10,s2,6432 <_start-0x7fff9bce> + 5dca: 6c2f6363 bltu t5,sp,6490 <_start-0x7fff9b70> + 5dce: 6269 lui tp,0x1a + 5dd0: 2f636367 0x2f636367 + 5dd4: 74666f73 csrrsi t5,0x746,12 + 5dd8: 662d lui a2,0xb + 5dda: 0070 addi a2,sp,12 + 5ddc: 2e2e fld ft8,200(sp) + 5dde: 2f2e2e2f 0x2f2e2e2f + 5de2: 2e2e fld ft8,200(sp) + 5de4: 2f2e2e2f 0x2f2e2e2f + 5de8: 6972 flw fs2,28(sp) + 5dea: 2d766373 csrrsi t1,0x2d7,12 + 5dee: 2f636367 0x2f636367 + 5df2: 696c flw fa1,84(a0) + 5df4: 6762 flw fa4,24(sp) + 5df6: 2e2f6363 bltu t5,sp,60dc <_start-0x7fff9f24> + 5dfa: 2f2e fld ft10,200(sp) + 5dfc: 6e69 lui t3,0x1a + 5dfe: 64756c63 bltu a0,t2,6456 <_start-0x7fff9baa> + 5e02: 0065 c.nop 25 + 5e04: 7300 flw fs0,32(a4) + 5e06: 6275 lui tp,0x1d + 5e08: 6674 flw fa3,76(a2) + 5e0a: 00632e33 slt t3,t1,t1 + 5e0e: 0001 nop + 5e10: 7300 flw fs0,32(a4) + 5e12: 2d74666f jal a2,4c8e8 <_start-0x7ffb3718> + 5e16: 7066 flw ft0,120(sp) + 5e18: 682e flw fa6,200(sp) + 5e1a: 0100 addi s0,sp,128 + 5e1c: 0000 unimp + 5e1e: 7571 lui a0,0xffffc + 5e20: 6461 lui s0,0x18 + 5e22: 682e flw fa6,200(sp) + 5e24: 0100 addi s0,sp,128 + 5e26: 0000 unimp + 5e28: 6f6c flw fa1,92(a4) + 5e2a: 676e flw fa4,216(sp) + 5e2c: 6f6c flw fa1,92(a4) + 5e2e: 676e flw fa4,216(sp) + 5e30: 682e flw fa6,200(sp) + 5e32: 0200 addi s0,sp,256 + 5e34: 0000 unimp + 5e36: 0500 addi s0,sp,640 + 5e38: 0001 nop + 5e3a: 0205 addi tp,tp,1 + 5e3c: 2d04 fld fs1,24(a0) + 5e3e: 8001 c.srli64 s0 + 5e40: 05012303 lw t1,80(sp) + 5e44: 09010303 lb t1,144(sp) + 5e48: 0000 unimp + 5e4a: 0301 addi t1,t1,0 + 5e4c: 0900 addi s0,sp,144 + 5e4e: 0000 unimp + 5e50: 0501 addi a0,a0,0 + 5e52: 030d addi t1,t1,3 + 5e54: 0900 addi s0,sp,144 + 5e56: 0000 unimp + 5e58: 0501 addi a0,a0,0 + 5e5a: 09010303 lb t1,144(sp) + 5e5e: 0000 unimp + 5e60: 0301 addi t1,t1,0 + 5e62: 0900 addi s0,sp,144 + 5e64: 0000 unimp + 5e66: 0301 addi t1,t1,0 + 5e68: 0900 addi s0,sp,144 + 5e6a: 0000 unimp + 5e6c: 0301 addi t1,t1,0 + 5e6e: 0900 addi s0,sp,144 5e70: 0000 unimp - 5e72: 7571 lui a0,0xffffc - 5e74: 6461 lui s0,0x18 - 5e76: 682e flw fa6,200(sp) - 5e78: 0100 addi s0,sp,128 - 5e7a: 0000 unimp - 5e7c: 6f6c flw fa1,92(a4) - 5e7e: 676e flw fa4,216(sp) - 5e80: 6f6c flw fa1,92(a4) - 5e82: 676e flw fa4,216(sp) - 5e84: 682e flw fa6,200(sp) - 5e86: 0200 addi s0,sp,256 + 5e72: 0301 addi t1,t1,0 + 5e74: 0901 addi s2,s2,0 + 5e76: 0000 unimp + 5e78: 0301 addi t1,t1,0 + 5e7a: 0900 addi s0,sp,144 + 5e7c: 0000 unimp + 5e7e: 0301 addi t1,t1,0 + 5e80: 0900 addi s0,sp,144 + 5e82: 0000 unimp + 5e84: 0301 addi t1,t1,0 + 5e86: 0900 addi s0,sp,144 5e88: 0000 unimp - 5e8a: 0500 addi s0,sp,640 - 5e8c: 0001 nop - 5e8e: 0205 addi tp,tp,1 - 5e90: 2c40 fld fs0,152(s0) - 5e92: 8001 c.srli64 s0 - 5e94: 05012303 lw t1,80(sp) - 5e98: 09010303 lb t1,144(sp) - 5e9c: 0000 unimp - 5e9e: 0301 addi t1,t1,0 - 5ea0: 0900 addi s0,sp,144 - 5ea2: 0000 unimp - 5ea4: 0501 addi a0,a0,0 - 5ea6: 030d addi t1,t1,3 - 5ea8: 0900 addi s0,sp,144 - 5eaa: 0000 unimp - 5eac: 0501 addi a0,a0,0 - 5eae: 09010303 lb t1,144(sp) + 5e8a: 0301 addi t1,t1,0 + 5e8c: 0901 addi s2,s2,0 + 5e8e: 0000 unimp + 5e90: 0301 addi t1,t1,0 + 5e92: 0900 addi s0,sp,144 + 5e94: 0000 unimp + 5e96: 0301 addi t1,t1,0 + 5e98: 0900 addi s0,sp,144 + 5e9a: 0000 unimp + 5e9c: 0301 addi t1,t1,0 + 5e9e: 0900 addi s0,sp,144 + 5ea0: 0000 unimp + 5ea2: 0301 addi t1,t1,0 + 5ea4: 0901 addi s2,s2,0 + 5ea6: 0000 unimp + 5ea8: 0301 addi t1,t1,0 + 5eaa: 0902 c.slli64 s2 + 5eac: 0000 unimp + 5eae: 0301 addi t1,t1,0 + 5eb0: 0901 addi s2,s2,0 5eb2: 0000 unimp 5eb4: 0301 addi t1,t1,0 5eb6: 0900 addi s0,sp,144 @@ -51280,4213 +51330,4209 @@ Disassembly of section .debug_line: 5ec0: 0301 addi t1,t1,0 5ec2: 0900 addi s0,sp,144 5ec4: 0000 unimp - 5ec6: 0301 addi t1,t1,0 - 5ec8: 0901 addi s2,s2,0 - 5eca: 0000 unimp - 5ecc: 0301 addi t1,t1,0 - 5ece: 0900 addi s0,sp,144 - 5ed0: 0000 unimp - 5ed2: 0301 addi t1,t1,0 - 5ed4: 0900 addi s0,sp,144 - 5ed6: 0000 unimp - 5ed8: 0301 addi t1,t1,0 - 5eda: 0900 addi s0,sp,144 - 5edc: 0000 unimp - 5ede: 0301 addi t1,t1,0 - 5ee0: 0901 addi s2,s2,0 - 5ee2: 0000 unimp - 5ee4: 0301 addi t1,t1,0 - 5ee6: 0900 addi s0,sp,144 - 5ee8: 0000 unimp - 5eea: 0301 addi t1,t1,0 - 5eec: 0900 addi s0,sp,144 - 5eee: 0000 unimp - 5ef0: 0301 addi t1,t1,0 - 5ef2: 0900 addi s0,sp,144 - 5ef4: 0000 unimp - 5ef6: 0301 addi t1,t1,0 - 5ef8: 0901 addi s2,s2,0 - 5efa: 0000 unimp - 5efc: 0301 addi t1,t1,0 - 5efe: 0902 c.slli64 s2 - 5f00: 0000 unimp - 5f02: 0301 addi t1,t1,0 - 5f04: 0901 addi s2,s2,0 - 5f06: 0000 unimp - 5f08: 0301 addi t1,t1,0 + 5ec6: 0501 addi a0,a0,0 + 5ec8: 0601 addi a2,a2,0 + 5eca: 00097803 0x97803 + 5ece: 0100 addi s0,sp,128 + 5ed0: 0305 addi t1,t1,1 + 5ed2: 1c090803 lb a6,448(s2) + 5ed6: 0100 addi s0,sp,128 + 5ed8: 0105 addi sp,sp,1 + 5eda: 04097803 0x4097803 + 5ede: 0100 addi s0,sp,128 + 5ee0: 0305 addi t1,t1,1 + 5ee2: 04090803 lb a6,64(s2) + 5ee6: 0100 addi s0,sp,128 + 5ee8: 0105 addi sp,sp,1 + 5eea: 04097803 0x4097803 + 5eee: 0100 addi s0,sp,128 + 5ef0: 0305 addi t1,t1,1 + 5ef2: 04090803 lb a6,64(s2) + 5ef6: 0100 addi s0,sp,128 + 5ef8: 0105 addi sp,sp,1 + 5efa: 04097803 0x4097803 + 5efe: 0100 addi s0,sp,128 + 5f00: 0305 addi t1,t1,1 + 5f02: 10090803 lb a6,256(s2) + 5f06: 0100 addi s0,sp,128 + 5f08: 0306 slli t1,t1,0x1 5f0a: 0900 addi s0,sp,144 - 5f0c: 0000 unimp - 5f0e: 0301 addi t1,t1,0 - 5f10: 0900 addi s0,sp,144 - 5f12: 0000 unimp - 5f14: 0301 addi t1,t1,0 - 5f16: 0900 addi s0,sp,144 - 5f18: 0000 unimp - 5f1a: 0501 addi a0,a0,0 - 5f1c: 0601 addi a2,a2,0 - 5f1e: 00097803 0x97803 - 5f22: 0100 addi s0,sp,128 - 5f24: 0305 addi t1,t1,1 - 5f26: 1c090803 lb a6,448(s2) - 5f2a: 0100 addi s0,sp,128 - 5f2c: 0105 addi sp,sp,1 - 5f2e: 04097803 0x4097803 - 5f32: 0100 addi s0,sp,128 - 5f34: 0305 addi t1,t1,1 - 5f36: 04090803 lb a6,64(s2) - 5f3a: 0100 addi s0,sp,128 - 5f3c: 0105 addi sp,sp,1 - 5f3e: 04097803 0x4097803 - 5f42: 0100 addi s0,sp,128 - 5f44: 0305 addi t1,t1,1 - 5f46: 04090803 lb a6,64(s2) - 5f4a: 0100 addi s0,sp,128 - 5f4c: 0105 addi sp,sp,1 - 5f4e: 04097803 0x4097803 - 5f52: 0100 addi s0,sp,128 - 5f54: 0305 addi t1,t1,1 - 5f56: 10090803 lb a6,256(s2) - 5f5a: 0100 addi s0,sp,128 - 5f5c: 0306 slli t1,t1,0x1 + 5f0c: 000c 0xc + 5f0e: 0501 addi a0,a0,0 + 5f10: 0601 addi a2,a2,0 + 5f12: 00097803 0x97803 + 5f16: 0100 addi s0,sp,128 + 5f18: 0305 addi t1,t1,1 + 5f1a: 14090803 lb a6,320(s2) + 5f1e: 0100 addi s0,sp,128 + 5f20: 0306 slli t1,t1,0x1 + 5f22: 0900 addi s0,sp,144 + 5f24: 000c 0xc + 5f26: 0301 addi t1,t1,0 + 5f28: 0900 addi s0,sp,144 + 5f2a: 0004 0x4 + 5f2c: 0301 addi t1,t1,0 + 5f2e: 0900 addi s0,sp,144 + 5f30: 0000 unimp + 5f32: 0301 addi t1,t1,0 + 5f34: 0900 addi s0,sp,144 + 5f36: 0004 0x4 + 5f38: 0301 addi t1,t1,0 + 5f3a: 0900 addi s0,sp,144 + 5f3c: 0004 0x4 + 5f3e: 0301 addi t1,t1,0 + 5f40: 0900 addi s0,sp,144 + 5f42: 0004 0x4 + 5f44: 0301 addi t1,t1,0 + 5f46: 0900 addi s0,sp,144 + 5f48: 0000 unimp + 5f4a: 0301 addi t1,t1,0 + 5f4c: 0900 addi s0,sp,144 + 5f4e: 0000 unimp + 5f50: 0301 addi t1,t1,0 + 5f52: 0900 addi s0,sp,144 + 5f54: 0000 unimp + 5f56: 0301 addi t1,t1,0 + 5f58: 0900 addi s0,sp,144 + 5f5a: 0000 unimp + 5f5c: 0301 addi t1,t1,0 5f5e: 0900 addi s0,sp,144 - 5f60: 000c 0xc - 5f62: 0501 addi a0,a0,0 - 5f64: 0601 addi a2,a2,0 - 5f66: 00097803 0x97803 - 5f6a: 0100 addi s0,sp,128 - 5f6c: 0305 addi t1,t1,1 - 5f6e: 14090803 lb a6,320(s2) - 5f72: 0100 addi s0,sp,128 - 5f74: 0306 slli t1,t1,0x1 + 5f60: 0000 unimp + 5f62: 0301 addi t1,t1,0 + 5f64: 0900 addi s0,sp,144 + 5f66: 0000 unimp + 5f68: 0301 addi t1,t1,0 + 5f6a: 0900 addi s0,sp,144 + 5f6c: 0000 unimp + 5f6e: 0301 addi t1,t1,0 + 5f70: 0900 addi s0,sp,144 + 5f72: 0000 unimp + 5f74: 0301 addi t1,t1,0 5f76: 0900 addi s0,sp,144 - 5f78: 000c 0xc - 5f7a: 0301 addi t1,t1,0 - 5f7c: 0900 addi s0,sp,144 - 5f7e: 0004 0x4 - 5f80: 0301 addi t1,t1,0 - 5f82: 0900 addi s0,sp,144 - 5f84: 0000 unimp - 5f86: 0301 addi t1,t1,0 - 5f88: 0900 addi s0,sp,144 - 5f8a: 0004 0x4 - 5f8c: 0301 addi t1,t1,0 - 5f8e: 0900 addi s0,sp,144 - 5f90: 0004 0x4 - 5f92: 0301 addi t1,t1,0 + 5f78: 0000 unimp + 5f7a: 0001 nop + 5f7c: 0402 c.slli64 s0 + 5f7e: 0308 addi a0,sp,384 + 5f80: 0900 addi s0,sp,144 + 5f82: 0008 0x8 + 5f84: 0001 nop + 5f86: 0402 c.slli64 s0 + 5f88: 0308 addi a0,sp,384 + 5f8a: 0900 addi s0,sp,144 + 5f8c: 001c 0x1c + 5f8e: 0001 nop + 5f90: 0402 c.slli64 s0 + 5f92: 0308 addi a0,sp,384 5f94: 0900 addi s0,sp,144 - 5f96: 0004 0x4 - 5f98: 0301 addi t1,t1,0 - 5f9a: 0900 addi s0,sp,144 - 5f9c: 0000 unimp - 5f9e: 0301 addi t1,t1,0 - 5fa0: 0900 addi s0,sp,144 - 5fa2: 0000 unimp - 5fa4: 0301 addi t1,t1,0 - 5fa6: 0900 addi s0,sp,144 - 5fa8: 0000 unimp - 5faa: 0301 addi t1,t1,0 - 5fac: 0900 addi s0,sp,144 - 5fae: 0000 unimp - 5fb0: 0301 addi t1,t1,0 - 5fb2: 0900 addi s0,sp,144 - 5fb4: 0000 unimp - 5fb6: 0301 addi t1,t1,0 - 5fb8: 0900 addi s0,sp,144 - 5fba: 0000 unimp - 5fbc: 0301 addi t1,t1,0 - 5fbe: 0900 addi s0,sp,144 - 5fc0: 0000 unimp - 5fc2: 0301 addi t1,t1,0 - 5fc4: 0900 addi s0,sp,144 - 5fc6: 0000 unimp - 5fc8: 0301 addi t1,t1,0 - 5fca: 0900 addi s0,sp,144 - 5fcc: 0000 unimp - 5fce: 0001 nop - 5fd0: 0402 c.slli64 s0 - 5fd2: 0308 addi a0,sp,384 - 5fd4: 0900 addi s0,sp,144 - 5fd6: 0008 0x8 - 5fd8: 0001 nop - 5fda: 0402 c.slli64 s0 - 5fdc: 0308 addi a0,sp,384 - 5fde: 0900 addi s0,sp,144 - 5fe0: 001c 0x1c - 5fe2: 0001 nop - 5fe4: 0402 c.slli64 s0 - 5fe6: 0308 addi a0,sp,384 - 5fe8: 0900 addi s0,sp,144 - 5fea: 0000 unimp - 5fec: 0001 nop - 5fee: 0402 c.slli64 s0 - 5ff0: 0309 addi t1,t1,2 - 5ff2: 0900 addi s0,sp,144 - 5ff4: 0004 0x4 - 5ff6: 0001 nop - 5ff8: 0402 c.slli64 s0 - 5ffa: 0609 addi a2,a2,2 - 5ffc: 04090103 lb sp,64(s2) - 6000: 0100 addi s0,sp,128 - 6002: 0200 addi s0,sp,256 - 6004: 0904 addi s1,sp,144 - 6006: 08097f03 0x8097f03 - 600a: 0100 addi s0,sp,128 - 600c: 0200 addi s0,sp,256 - 600e: 0904 addi s1,sp,144 - 6010: 04090103 lb sp,64(s2) - 6014: 0100 addi s0,sp,128 - 6016: 0200 addi s0,sp,256 - 6018: 0904 addi s1,sp,144 - 601a: 18097f03 0x18097f03 - 601e: 0100 addi s0,sp,128 - 6020: 0200 addi s0,sp,256 - 6022: 0904 addi s1,sp,144 - 6024: 0306 slli t1,t1,0x1 - 6026: 0900 addi s0,sp,144 - 6028: 0004 0x4 - 602a: 0001 nop - 602c: 0402 c.slli64 s0 - 602e: 0309 addi t1,t1,2 - 6030: 0900 addi s0,sp,144 - 6032: 0000 unimp - 6034: 0001 nop - 6036: 0402 c.slli64 s0 - 6038: 0309 addi t1,t1,2 - 603a: 0900 addi s0,sp,144 - 603c: 0000 unimp - 603e: 0001 nop - 6040: 0402 c.slli64 s0 - 6042: 0309 addi t1,t1,2 - 6044: 0901 addi s2,s2,0 - 6046: 0000 unimp - 6048: 0001 nop - 604a: 0402 c.slli64 s0 - 604c: 0309 addi t1,t1,2 - 604e: 0900 addi s0,sp,144 - 6050: 0000 unimp - 6052: 0001 nop - 6054: 0402 c.slli64 s0 - 6056: 0309 addi t1,t1,2 - 6058: 0900 addi s0,sp,144 - 605a: 0000 unimp - 605c: 0001 nop - 605e: 0402 c.slli64 s0 - 6060: 0309 addi t1,t1,2 - 6062: 0900 addi s0,sp,144 - 6064: 0000 unimp - 6066: 0001 nop - 6068: 0402 c.slli64 s0 - 606a: 0309 addi t1,t1,2 - 606c: 0900 addi s0,sp,144 - 606e: 0000 unimp - 6070: 0001 nop - 6072: 0402 c.slli64 s0 - 6074: 0309 addi t1,t1,2 - 6076: 0900 addi s0,sp,144 - 6078: 0000 unimp - 607a: 0001 nop - 607c: 0402 c.slli64 s0 - 607e: 0309 addi t1,t1,2 - 6080: 0900 addi s0,sp,144 - 6082: 0008 0x8 - 6084: 0001 nop - 6086: 0402 c.slli64 s0 - 6088: 0309 addi t1,t1,2 - 608a: 0900 addi s0,sp,144 - 608c: 0000 unimp - 608e: 0001 nop - 6090: 0402 c.slli64 s0 - 6092: 0309 addi t1,t1,2 - 6094: 0900 addi s0,sp,144 - 6096: 0004 0x4 - 6098: 0001 nop - 609a: 0402 c.slli64 s0 - 609c: 0309 addi t1,t1,2 - 609e: 0900 addi s0,sp,144 - 60a0: 0004 0x4 - 60a2: 0001 nop - 60a4: 0402 c.slli64 s0 - 60a6: 0309 addi t1,t1,2 - 60a8: 0900 addi s0,sp,144 - 60aa: 0004 0x4 - 60ac: 0001 nop - 60ae: 0402 c.slli64 s0 - 60b0: 0309 addi t1,t1,2 - 60b2: 0900 addi s0,sp,144 - 60b4: 0000 unimp - 60b6: 0001 nop - 60b8: 0402 c.slli64 s0 - 60ba: 0309 addi t1,t1,2 - 60bc: 0900 addi s0,sp,144 - 60be: 0000 unimp - 60c0: 0001 nop - 60c2: 0402 c.slli64 s0 - 60c4: 0309 addi t1,t1,2 - 60c6: 0900 addi s0,sp,144 - 60c8: 0000 unimp - 60ca: 0001 nop - 60cc: 0402 c.slli64 s0 - 60ce: 0309 addi t1,t1,2 - 60d0: 0900 addi s0,sp,144 - 60d2: 0000 unimp - 60d4: 0001 nop - 60d6: 0402 c.slli64 s0 - 60d8: 0309 addi t1,t1,2 - 60da: 0900 addi s0,sp,144 - 60dc: 0000 unimp - 60de: 0001 nop - 60e0: 0402 c.slli64 s0 - 60e2: 0309 addi t1,t1,2 - 60e4: 0900 addi s0,sp,144 - 60e6: 0000 unimp - 60e8: 0001 nop - 60ea: 0402 c.slli64 s0 - 60ec: 0309 addi t1,t1,2 - 60ee: 0900 addi s0,sp,144 - 60f0: 0000 unimp - 60f2: 0001 nop - 60f4: 0402 c.slli64 s0 - 60f6: 0309 addi t1,t1,2 - 60f8: 0900 addi s0,sp,144 - 60fa: 0000 unimp - 60fc: 0001 nop - 60fe: 0402 c.slli64 s0 - 6100: 0309 addi t1,t1,2 - 6102: 0900 addi s0,sp,144 - 6104: 0000 unimp - 6106: 0001 nop - 6108: 0402 c.slli64 s0 - 610a: 0308 addi a0,sp,384 - 610c: 0900 addi s0,sp,144 - 610e: 0008 0x8 - 6110: 0001 nop - 6112: 0402 c.slli64 s0 - 6114: 0308 addi a0,sp,384 - 6116: 0900 addi s0,sp,144 - 6118: 001c 0x1c - 611a: 0001 nop - 611c: 0402 c.slli64 s0 - 611e: 0308 addi a0,sp,384 - 6120: 0900 addi s0,sp,144 - 6122: 0000 unimp - 6124: 0001 nop - 6126: 0402 c.slli64 s0 - 6128: 0309 addi t1,t1,2 - 612a: 0900 addi s0,sp,144 - 612c: 0004 0x4 - 612e: 0001 nop - 6130: 0402 c.slli64 s0 - 6132: 0609 addi a2,a2,2 - 6134: 04090103 lb sp,64(s2) - 6138: 0100 addi s0,sp,128 - 613a: 0200 addi s0,sp,256 - 613c: 0904 addi s1,sp,144 - 613e: 08097f03 0x8097f03 - 6142: 0100 addi s0,sp,128 - 6144: 0200 addi s0,sp,256 - 6146: 0904 addi s1,sp,144 - 6148: 0306 slli t1,t1,0x1 - 614a: 0900 addi s0,sp,144 - 614c: 0008 0x8 - 614e: 0001 nop - 6150: 0402 c.slli64 s0 - 6152: 0309 addi t1,t1,2 - 6154: 0900 addi s0,sp,144 - 6156: 0000 unimp - 6158: 0001 nop - 615a: 0402 c.slli64 s0 - 615c: 0309 addi t1,t1,2 - 615e: 0900 addi s0,sp,144 - 6160: 0000 unimp - 6162: 0001 nop - 6164: 0402 c.slli64 s0 - 6166: 0309 addi t1,t1,2 - 6168: 0901 addi s2,s2,0 - 616a: 0000 unimp - 616c: 0001 nop - 616e: 0402 c.slli64 s0 - 6170: 0309 addi t1,t1,2 - 6172: 0900 addi s0,sp,144 - 6174: 0000 unimp - 6176: 0001 nop - 6178: 0402 c.slli64 s0 - 617a: 0602 c.slli64 a2 - 617c: 04090003 lb zero,64(s2) - 6180: 0100 addi s0,sp,128 - 6182: 0200 addi s0,sp,256 - 6184: 0304 addi s1,sp,384 - 6186: 0306 slli t1,t1,0x1 - 6188: 0900 addi s0,sp,144 - 618a: 001c 0x1c - 618c: 0001 nop - 618e: 0402 c.slli64 s0 - 6190: 0900030b 0x900030b - 6194: 0004 0x4 - 6196: 0001 nop - 6198: 0402 c.slli64 s0 - 619a: 0900030b 0x900030b - 619e: 0000 unimp - 61a0: 0001 nop - 61a2: 0402 c.slli64 s0 - 61a4: 0900030b 0x900030b - 61a8: 0000 unimp - 61aa: 0001 nop - 61ac: 0402 c.slli64 s0 - 61ae: 0900030b 0x900030b - 61b2: 0000 unimp - 61b4: 0001 nop - 61b6: 0402 c.slli64 s0 - 61b8: 0900030b 0x900030b - 61bc: 0000 unimp - 61be: 0001 nop - 61c0: 0402 c.slli64 s0 - 61c2: 0900030b 0x900030b - 61c6: 0000 unimp - 61c8: 0001 nop - 61ca: 0402 c.slli64 s0 - 61cc: 0900030b 0x900030b - 61d0: 0000 unimp - 61d2: 0001 nop - 61d4: 0402 c.slli64 s0 - 61d6: 0900030b 0x900030b - 61da: 0000 unimp - 61dc: 0001 nop - 61de: 0402 c.slli64 s0 - 61e0: 030c addi a1,sp,384 - 61e2: 0900 addi s0,sp,144 - 61e4: 0008 0x8 - 61e6: 0001 nop - 61e8: 0402 c.slli64 s0 - 61ea: 030c addi a1,sp,384 - 61ec: 0900 addi s0,sp,144 - 61ee: 0000 unimp - 61f0: 0001 nop - 61f2: 0402 c.slli64 s0 - 61f4: 030c addi a1,sp,384 - 61f6: 0900 addi s0,sp,144 - 61f8: 0000 unimp - 61fa: 0001 nop - 61fc: 0402 c.slli64 s0 - 61fe: 030e slli t1,t1,0x3 - 6200: 0900 addi s0,sp,144 - 6202: 0004 0x4 - 6204: 0001 nop - 6206: 0402 c.slli64 s0 - 6208: 030e slli t1,t1,0x3 - 620a: 0900 addi s0,sp,144 - 620c: 0000 unimp - 620e: 0001 nop - 6210: 0402 c.slli64 s0 - 6212: 0310 addi a2,sp,384 - 6214: 0900 addi s0,sp,144 - 6216: 0010 0x10 - 6218: 0001 nop - 621a: 0402 c.slli64 s0 - 621c: 09000327 0x9000327 - 6220: 001c 0x1c - 6222: 0001 nop - 6224: 0402 c.slli64 s0 - 6226: 09000327 0x9000327 - 622a: 0000 unimp - 622c: 0001 nop - 622e: 0402 c.slli64 s0 - 6230: 09000327 0x9000327 - 6234: 0000 unimp - 6236: 0001 nop - 6238: 0402 c.slli64 s0 - 623a: 09000327 0x9000327 - 623e: 0000 unimp - 6240: 0001 nop - 6242: 0402 c.slli64 s0 - 6244: 09000327 0x9000327 - 6248: 0010 0x10 - 624a: 0001 nop - 624c: 02a90403 lb s0,42(s2) - 6250: 00090003 lb zero,0(s2) - 6254: 0100 addi s0,sp,128 - 6256: 0200 addi s0,sp,256 - 6258: 1304 addi s1,sp,416 - 625a: 08090003 lb zero,128(s2) - 625e: 0100 addi s0,sp,128 - 6260: 0200 addi s0,sp,256 - 6262: 1304 addi s1,sp,416 - 6264: 00090003 lb zero,0(s2) - 6268: 0100 addi s0,sp,128 - 626a: 0200 addi s0,sp,256 - 626c: 1304 addi s1,sp,416 - 626e: 04090003 lb zero,64(s2) - 6272: 0100 addi s0,sp,128 - 6274: 0200 addi s0,sp,256 - 6276: 1c04 addi s1,sp,560 - 6278: 04090003 lb zero,64(s2) - 627c: 0100 addi s0,sp,128 - 627e: 0200 addi s0,sp,256 - 6280: 1c04 addi s1,sp,560 - 6282: 00090003 lb zero,0(s2) - 6286: 0100 addi s0,sp,128 - 6288: 0200 addi s0,sp,256 - 628a: 1c04 addi s1,sp,560 - 628c: 00090003 lb zero,0(s2) - 6290: 0100 addi s0,sp,128 - 6292: 0200 addi s0,sp,256 - 6294: 1c04 addi s1,sp,560 - 6296: 00090003 lb zero,0(s2) - 629a: 0100 addi s0,sp,128 - 629c: 0200 addi s0,sp,256 - 629e: 1c04 addi s1,sp,560 - 62a0: 10090003 lb zero,256(s2) - 62a4: 0100 addi s0,sp,128 - 62a6: 0200 addi s0,sp,256 - 62a8: 1c04 addi s1,sp,560 - 62aa: 00090003 lb zero,0(s2) - 62ae: 0100 addi s0,sp,128 - 62b0: 0200 addi s0,sp,256 - 62b2: 1c04 addi s1,sp,560 - 62b4: 00090003 lb zero,0(s2) - 62b8: 0100 addi s0,sp,128 - 62ba: 0200 addi s0,sp,256 - 62bc: 1c04 addi s1,sp,560 - 62be: 00090003 lb zero,0(s2) - 62c2: 0100 addi s0,sp,128 - 62c4: 0200 addi s0,sp,256 - 62c6: 1c04 addi s1,sp,560 - 62c8: 14090003 lb zero,320(s2) - 62cc: 0100 addi s0,sp,128 - 62ce: 0200 addi s0,sp,256 - 62d0: 1c04 addi s1,sp,560 - 62d2: 00090003 lb zero,0(s2) - 62d6: 0100 addi s0,sp,128 - 62d8: 0200 addi s0,sp,256 - 62da: 1c04 addi s1,sp,560 - 62dc: 04090003 lb zero,64(s2) - 62e0: 0100 addi s0,sp,128 - 62e2: 0200 addi s0,sp,256 - 62e4: 1c04 addi s1,sp,560 - 62e6: 00090003 lb zero,0(s2) - 62ea: 0100 addi s0,sp,128 - 62ec: 0200 addi s0,sp,256 - 62ee: 1c04 addi s1,sp,560 - 62f0: 1c090003 lb zero,448(s2) - 62f4: 0100 addi s0,sp,128 - 62f6: 0200 addi s0,sp,256 - 62f8: 1c04 addi s1,sp,560 - 62fa: 00090003 lb zero,0(s2) + 5f96: 0000 unimp + 5f98: 0001 nop + 5f9a: 0402 c.slli64 s0 + 5f9c: 0309 addi t1,t1,2 + 5f9e: 0900 addi s0,sp,144 + 5fa0: 0004 0x4 + 5fa2: 0001 nop + 5fa4: 0402 c.slli64 s0 + 5fa6: 0609 addi a2,a2,2 + 5fa8: 04090103 lb sp,64(s2) + 5fac: 0100 addi s0,sp,128 + 5fae: 0200 addi s0,sp,256 + 5fb0: 0904 addi s1,sp,144 + 5fb2: 08097f03 0x8097f03 + 5fb6: 0100 addi s0,sp,128 + 5fb8: 0200 addi s0,sp,256 + 5fba: 0904 addi s1,sp,144 + 5fbc: 04090103 lb sp,64(s2) + 5fc0: 0100 addi s0,sp,128 + 5fc2: 0200 addi s0,sp,256 + 5fc4: 0904 addi s1,sp,144 + 5fc6: 18097f03 0x18097f03 + 5fca: 0100 addi s0,sp,128 + 5fcc: 0200 addi s0,sp,256 + 5fce: 0904 addi s1,sp,144 + 5fd0: 0306 slli t1,t1,0x1 + 5fd2: 0900 addi s0,sp,144 + 5fd4: 0004 0x4 + 5fd6: 0001 nop + 5fd8: 0402 c.slli64 s0 + 5fda: 0309 addi t1,t1,2 + 5fdc: 0900 addi s0,sp,144 + 5fde: 0000 unimp + 5fe0: 0001 nop + 5fe2: 0402 c.slli64 s0 + 5fe4: 0309 addi t1,t1,2 + 5fe6: 0900 addi s0,sp,144 + 5fe8: 0000 unimp + 5fea: 0001 nop + 5fec: 0402 c.slli64 s0 + 5fee: 0309 addi t1,t1,2 + 5ff0: 0901 addi s2,s2,0 + 5ff2: 0000 unimp + 5ff4: 0001 nop + 5ff6: 0402 c.slli64 s0 + 5ff8: 0309 addi t1,t1,2 + 5ffa: 0900 addi s0,sp,144 + 5ffc: 0000 unimp + 5ffe: 0001 nop + 6000: 0402 c.slli64 s0 + 6002: 0309 addi t1,t1,2 + 6004: 0900 addi s0,sp,144 + 6006: 0000 unimp + 6008: 0001 nop + 600a: 0402 c.slli64 s0 + 600c: 0309 addi t1,t1,2 + 600e: 0900 addi s0,sp,144 + 6010: 0000 unimp + 6012: 0001 nop + 6014: 0402 c.slli64 s0 + 6016: 0309 addi t1,t1,2 + 6018: 0900 addi s0,sp,144 + 601a: 0000 unimp + 601c: 0001 nop + 601e: 0402 c.slli64 s0 + 6020: 0309 addi t1,t1,2 + 6022: 0900 addi s0,sp,144 + 6024: 0000 unimp + 6026: 0001 nop + 6028: 0402 c.slli64 s0 + 602a: 0309 addi t1,t1,2 + 602c: 0900 addi s0,sp,144 + 602e: 0008 0x8 + 6030: 0001 nop + 6032: 0402 c.slli64 s0 + 6034: 0309 addi t1,t1,2 + 6036: 0900 addi s0,sp,144 + 6038: 0000 unimp + 603a: 0001 nop + 603c: 0402 c.slli64 s0 + 603e: 0309 addi t1,t1,2 + 6040: 0900 addi s0,sp,144 + 6042: 0004 0x4 + 6044: 0001 nop + 6046: 0402 c.slli64 s0 + 6048: 0309 addi t1,t1,2 + 604a: 0900 addi s0,sp,144 + 604c: 0004 0x4 + 604e: 0001 nop + 6050: 0402 c.slli64 s0 + 6052: 0309 addi t1,t1,2 + 6054: 0900 addi s0,sp,144 + 6056: 0004 0x4 + 6058: 0001 nop + 605a: 0402 c.slli64 s0 + 605c: 0309 addi t1,t1,2 + 605e: 0900 addi s0,sp,144 + 6060: 0000 unimp + 6062: 0001 nop + 6064: 0402 c.slli64 s0 + 6066: 0309 addi t1,t1,2 + 6068: 0900 addi s0,sp,144 + 606a: 0000 unimp + 606c: 0001 nop + 606e: 0402 c.slli64 s0 + 6070: 0309 addi t1,t1,2 + 6072: 0900 addi s0,sp,144 + 6074: 0000 unimp + 6076: 0001 nop + 6078: 0402 c.slli64 s0 + 607a: 0309 addi t1,t1,2 + 607c: 0900 addi s0,sp,144 + 607e: 0000 unimp + 6080: 0001 nop + 6082: 0402 c.slli64 s0 + 6084: 0309 addi t1,t1,2 + 6086: 0900 addi s0,sp,144 + 6088: 0000 unimp + 608a: 0001 nop + 608c: 0402 c.slli64 s0 + 608e: 0309 addi t1,t1,2 + 6090: 0900 addi s0,sp,144 + 6092: 0000 unimp + 6094: 0001 nop + 6096: 0402 c.slli64 s0 + 6098: 0309 addi t1,t1,2 + 609a: 0900 addi s0,sp,144 + 609c: 0000 unimp + 609e: 0001 nop + 60a0: 0402 c.slli64 s0 + 60a2: 0309 addi t1,t1,2 + 60a4: 0900 addi s0,sp,144 + 60a6: 0000 unimp + 60a8: 0001 nop + 60aa: 0402 c.slli64 s0 + 60ac: 0309 addi t1,t1,2 + 60ae: 0900 addi s0,sp,144 + 60b0: 0000 unimp + 60b2: 0001 nop + 60b4: 0402 c.slli64 s0 + 60b6: 0308 addi a0,sp,384 + 60b8: 0900 addi s0,sp,144 + 60ba: 0008 0x8 + 60bc: 0001 nop + 60be: 0402 c.slli64 s0 + 60c0: 0308 addi a0,sp,384 + 60c2: 0900 addi s0,sp,144 + 60c4: 001c 0x1c + 60c6: 0001 nop + 60c8: 0402 c.slli64 s0 + 60ca: 0308 addi a0,sp,384 + 60cc: 0900 addi s0,sp,144 + 60ce: 0000 unimp + 60d0: 0001 nop + 60d2: 0402 c.slli64 s0 + 60d4: 0309 addi t1,t1,2 + 60d6: 0900 addi s0,sp,144 + 60d8: 0004 0x4 + 60da: 0001 nop + 60dc: 0402 c.slli64 s0 + 60de: 0609 addi a2,a2,2 + 60e0: 04090103 lb sp,64(s2) + 60e4: 0100 addi s0,sp,128 + 60e6: 0200 addi s0,sp,256 + 60e8: 0904 addi s1,sp,144 + 60ea: 08097f03 0x8097f03 + 60ee: 0100 addi s0,sp,128 + 60f0: 0200 addi s0,sp,256 + 60f2: 0904 addi s1,sp,144 + 60f4: 0306 slli t1,t1,0x1 + 60f6: 0900 addi s0,sp,144 + 60f8: 0008 0x8 + 60fa: 0001 nop + 60fc: 0402 c.slli64 s0 + 60fe: 0309 addi t1,t1,2 + 6100: 0900 addi s0,sp,144 + 6102: 0000 unimp + 6104: 0001 nop + 6106: 0402 c.slli64 s0 + 6108: 0309 addi t1,t1,2 + 610a: 0900 addi s0,sp,144 + 610c: 0000 unimp + 610e: 0001 nop + 6110: 0402 c.slli64 s0 + 6112: 0309 addi t1,t1,2 + 6114: 0901 addi s2,s2,0 + 6116: 0000 unimp + 6118: 0001 nop + 611a: 0402 c.slli64 s0 + 611c: 0309 addi t1,t1,2 + 611e: 0900 addi s0,sp,144 + 6120: 0000 unimp + 6122: 0001 nop + 6124: 0402 c.slli64 s0 + 6126: 0602 c.slli64 a2 + 6128: 04090003 lb zero,64(s2) + 612c: 0100 addi s0,sp,128 + 612e: 0200 addi s0,sp,256 + 6130: 0304 addi s1,sp,384 + 6132: 0306 slli t1,t1,0x1 + 6134: 0900 addi s0,sp,144 + 6136: 001c 0x1c + 6138: 0001 nop + 613a: 0402 c.slli64 s0 + 613c: 0900030b 0x900030b + 6140: 0004 0x4 + 6142: 0001 nop + 6144: 0402 c.slli64 s0 + 6146: 0900030b 0x900030b + 614a: 0000 unimp + 614c: 0001 nop + 614e: 0402 c.slli64 s0 + 6150: 0900030b 0x900030b + 6154: 0000 unimp + 6156: 0001 nop + 6158: 0402 c.slli64 s0 + 615a: 0900030b 0x900030b + 615e: 0000 unimp + 6160: 0001 nop + 6162: 0402 c.slli64 s0 + 6164: 0900030b 0x900030b + 6168: 0000 unimp + 616a: 0001 nop + 616c: 0402 c.slli64 s0 + 616e: 0900030b 0x900030b + 6172: 0000 unimp + 6174: 0001 nop + 6176: 0402 c.slli64 s0 + 6178: 0900030b 0x900030b + 617c: 0000 unimp + 617e: 0001 nop + 6180: 0402 c.slli64 s0 + 6182: 0900030b 0x900030b + 6186: 0000 unimp + 6188: 0001 nop + 618a: 0402 c.slli64 s0 + 618c: 030c addi a1,sp,384 + 618e: 0900 addi s0,sp,144 + 6190: 0008 0x8 + 6192: 0001 nop + 6194: 0402 c.slli64 s0 + 6196: 030c addi a1,sp,384 + 6198: 0900 addi s0,sp,144 + 619a: 0000 unimp + 619c: 0001 nop + 619e: 0402 c.slli64 s0 + 61a0: 030c addi a1,sp,384 + 61a2: 0900 addi s0,sp,144 + 61a4: 0000 unimp + 61a6: 0001 nop + 61a8: 0402 c.slli64 s0 + 61aa: 030e slli t1,t1,0x3 + 61ac: 0900 addi s0,sp,144 + 61ae: 0004 0x4 + 61b0: 0001 nop + 61b2: 0402 c.slli64 s0 + 61b4: 030e slli t1,t1,0x3 + 61b6: 0900 addi s0,sp,144 + 61b8: 0000 unimp + 61ba: 0001 nop + 61bc: 0402 c.slli64 s0 + 61be: 0310 addi a2,sp,384 + 61c0: 0900 addi s0,sp,144 + 61c2: 0010 0x10 + 61c4: 0001 nop + 61c6: 0402 c.slli64 s0 + 61c8: 09000327 0x9000327 + 61cc: 001c 0x1c + 61ce: 0001 nop + 61d0: 0402 c.slli64 s0 + 61d2: 09000327 0x9000327 + 61d6: 0000 unimp + 61d8: 0001 nop + 61da: 0402 c.slli64 s0 + 61dc: 09000327 0x9000327 + 61e0: 0000 unimp + 61e2: 0001 nop + 61e4: 0402 c.slli64 s0 + 61e6: 09000327 0x9000327 + 61ea: 0000 unimp + 61ec: 0001 nop + 61ee: 0402 c.slli64 s0 + 61f0: 09000327 0x9000327 + 61f4: 0010 0x10 + 61f6: 0001 nop + 61f8: 02a90403 lb s0,42(s2) + 61fc: 00090003 lb zero,0(s2) + 6200: 0100 addi s0,sp,128 + 6202: 0200 addi s0,sp,256 + 6204: 1304 addi s1,sp,416 + 6206: 08090003 lb zero,128(s2) + 620a: 0100 addi s0,sp,128 + 620c: 0200 addi s0,sp,256 + 620e: 1304 addi s1,sp,416 + 6210: 00090003 lb zero,0(s2) + 6214: 0100 addi s0,sp,128 + 6216: 0200 addi s0,sp,256 + 6218: 1304 addi s1,sp,416 + 621a: 04090003 lb zero,64(s2) + 621e: 0100 addi s0,sp,128 + 6220: 0200 addi s0,sp,256 + 6222: 1c04 addi s1,sp,560 + 6224: 04090003 lb zero,64(s2) + 6228: 0100 addi s0,sp,128 + 622a: 0200 addi s0,sp,256 + 622c: 1c04 addi s1,sp,560 + 622e: 00090003 lb zero,0(s2) + 6232: 0100 addi s0,sp,128 + 6234: 0200 addi s0,sp,256 + 6236: 1c04 addi s1,sp,560 + 6238: 00090003 lb zero,0(s2) + 623c: 0100 addi s0,sp,128 + 623e: 0200 addi s0,sp,256 + 6240: 1c04 addi s1,sp,560 + 6242: 00090003 lb zero,0(s2) + 6246: 0100 addi s0,sp,128 + 6248: 0200 addi s0,sp,256 + 624a: 1c04 addi s1,sp,560 + 624c: 10090003 lb zero,256(s2) + 6250: 0100 addi s0,sp,128 + 6252: 0200 addi s0,sp,256 + 6254: 1c04 addi s1,sp,560 + 6256: 00090003 lb zero,0(s2) + 625a: 0100 addi s0,sp,128 + 625c: 0200 addi s0,sp,256 + 625e: 1c04 addi s1,sp,560 + 6260: 00090003 lb zero,0(s2) + 6264: 0100 addi s0,sp,128 + 6266: 0200 addi s0,sp,256 + 6268: 1c04 addi s1,sp,560 + 626a: 00090003 lb zero,0(s2) + 626e: 0100 addi s0,sp,128 + 6270: 0200 addi s0,sp,256 + 6272: 1c04 addi s1,sp,560 + 6274: 14090003 lb zero,320(s2) + 6278: 0100 addi s0,sp,128 + 627a: 0200 addi s0,sp,256 + 627c: 1c04 addi s1,sp,560 + 627e: 00090003 lb zero,0(s2) + 6282: 0100 addi s0,sp,128 + 6284: 0200 addi s0,sp,256 + 6286: 1c04 addi s1,sp,560 + 6288: 04090003 lb zero,64(s2) + 628c: 0100 addi s0,sp,128 + 628e: 0200 addi s0,sp,256 + 6290: 1c04 addi s1,sp,560 + 6292: 00090003 lb zero,0(s2) + 6296: 0100 addi s0,sp,128 + 6298: 0200 addi s0,sp,256 + 629a: 1c04 addi s1,sp,560 + 629c: 1c090003 lb zero,448(s2) + 62a0: 0100 addi s0,sp,128 + 62a2: 0200 addi s0,sp,256 + 62a4: 1c04 addi s1,sp,560 + 62a6: 00090003 lb zero,0(s2) + 62aa: 0100 addi s0,sp,128 + 62ac: 0200 addi s0,sp,256 + 62ae: 1c04 addi s1,sp,560 + 62b0: 04090003 lb zero,64(s2) + 62b4: 0100 addi s0,sp,128 + 62b6: 0200 addi s0,sp,256 + 62b8: 1c04 addi s1,sp,560 + 62ba: 00090003 lb zero,0(s2) + 62be: 0100 addi s0,sp,128 + 62c0: 0200 addi s0,sp,256 + 62c2: 5b04 lw s1,48(a4) + 62c4: 00090003 lb zero,0(s2) + 62c8: 0100 addi s0,sp,128 + 62ca: 0200 addi s0,sp,256 + 62cc: 5b04 lw s1,48(a4) + 62ce: 00090003 lb zero,0(s2) + 62d2: 0100 addi s0,sp,128 + 62d4: 0200 addi s0,sp,256 + 62d6: 5b04 lw s1,48(a4) + 62d8: 0306 slli t1,t1,0x1 + 62da: 097f 0x97f + 62dc: 0000 unimp + 62de: 0001 nop + 62e0: 0402 c.slli64 s0 + 62e2: 0901035b 0x901035b + 62e6: 0004 0x4 + 62e8: 0001 nop + 62ea: 0402 c.slli64 s0 + 62ec: 061d addi a2,a2,7 + 62ee: 04090003 lb zero,64(s2) + 62f2: 0100 addi s0,sp,128 + 62f4: 0c090003 lb zero,192(s2) + 62f8: 0100 addi s0,sp,128 + 62fa: 08090003 lb zero,128(s2) 62fe: 0100 addi s0,sp,128 6300: 0200 addi s0,sp,256 - 6302: 1c04 addi s1,sp,560 - 6304: 04090003 lb zero,64(s2) + 6302: 1104 addi s1,sp,160 + 6304: 14090003 lb zero,320(s2) 6308: 0100 addi s0,sp,128 630a: 0200 addi s0,sp,256 - 630c: 1c04 addi s1,sp,560 - 630e: 00090003 lb zero,0(s2) + 630c: 3204 fld fs1,32(a2) + 630e: 0c090003 lb zero,192(s2) 6312: 0100 addi s0,sp,128 6314: 0200 addi s0,sp,256 - 6316: 5b04 lw s1,48(a4) + 6316: 3204 fld fs1,32(a2) 6318: 00090003 lb zero,0(s2) 631c: 0100 addi s0,sp,128 631e: 0200 addi s0,sp,256 - 6320: 5b04 lw s1,48(a4) + 6320: 3204 fld fs1,32(a2) 6322: 00090003 lb zero,0(s2) 6326: 0100 addi s0,sp,128 6328: 0200 addi s0,sp,256 - 632a: 5b04 lw s1,48(a4) - 632c: 0306 slli t1,t1,0x1 - 632e: 097f 0x97f - 6330: 0000 unimp - 6332: 0001 nop - 6334: 0402 c.slli64 s0 - 6336: 0901035b 0x901035b - 633a: 0004 0x4 - 633c: 0001 nop - 633e: 0402 c.slli64 s0 - 6340: 061d addi a2,a2,7 - 6342: 04090003 lb zero,64(s2) - 6346: 0100 addi s0,sp,128 - 6348: 0c090003 lb zero,192(s2) - 634c: 0100 addi s0,sp,128 - 634e: 08090003 lb zero,128(s2) - 6352: 0100 addi s0,sp,128 - 6354: 0200 addi s0,sp,256 - 6356: 1104 addi s1,sp,160 - 6358: 14090003 lb zero,320(s2) - 635c: 0100 addi s0,sp,128 - 635e: 0200 addi s0,sp,256 - 6360: 3204 fld fs1,32(a2) - 6362: 0c090003 lb zero,192(s2) + 632a: 3204 fld fs1,32(a2) + 632c: 00090003 lb zero,0(s2) + 6330: 0100 addi s0,sp,128 + 6332: 0200 addi s0,sp,256 + 6334: 3204 fld fs1,32(a2) + 6336: 10090003 lb zero,256(s2) + 633a: 0100 addi s0,sp,128 + 633c: 0300 addi s0,sp,384 + 633e: a804 fsd fs1,16(s0) + 6340: 0305 addi t1,t1,1 + 6342: 0900 addi s0,sp,144 + 6344: 0000 unimp + 6346: 0001 nop + 6348: 05a80403 lb s0,90(a6) + 634c: 00090003 lb zero,0(s2) + 6350: 0100 addi s0,sp,128 + 6352: 0300 addi s0,sp,384 + 6354: a804 fsd fs1,16(s0) + 6356: 0305 addi t1,t1,1 + 6358: 0900 addi s0,sp,144 + 635a: 0000 unimp + 635c: 0001 nop + 635e: 05a80403 lb s0,90(a6) + 6362: 00090103 lb sp,0(s2) 6366: 0100 addi s0,sp,128 - 6368: 0200 addi s0,sp,256 - 636a: 3204 fld fs1,32(a2) - 636c: 00090003 lb zero,0(s2) - 6370: 0100 addi s0,sp,128 - 6372: 0200 addi s0,sp,256 - 6374: 3204 fld fs1,32(a2) - 6376: 00090003 lb zero,0(s2) - 637a: 0100 addi s0,sp,128 - 637c: 0200 addi s0,sp,256 - 637e: 3204 fld fs1,32(a2) - 6380: 00090003 lb zero,0(s2) - 6384: 0100 addi s0,sp,128 - 6386: 0200 addi s0,sp,256 - 6388: 3204 fld fs1,32(a2) - 638a: 10090003 lb zero,256(s2) - 638e: 0100 addi s0,sp,128 - 6390: 0300 addi s0,sp,384 - 6392: a804 fsd fs1,16(s0) - 6394: 0305 addi t1,t1,1 - 6396: 0900 addi s0,sp,144 - 6398: 0000 unimp - 639a: 0001 nop - 639c: 05a80403 lb s0,90(a6) - 63a0: 00090003 lb zero,0(s2) - 63a4: 0100 addi s0,sp,128 - 63a6: 0300 addi s0,sp,384 - 63a8: a804 fsd fs1,16(s0) - 63aa: 0305 addi t1,t1,1 - 63ac: 0900 addi s0,sp,144 - 63ae: 0000 unimp - 63b0: 0001 nop - 63b2: 05a80403 lb s0,90(a6) - 63b6: 00090103 lb sp,0(s2) + 6368: 0300 addi s0,sp,384 + 636a: a804 fsd fs1,16(s0) + 636c: 0305 addi t1,t1,1 + 636e: 0900 addi s0,sp,144 + 6370: 0000 unimp + 6372: 0001 nop + 6374: 05a80403 lb s0,90(a6) + 6378: 00090003 lb zero,0(s2) + 637c: 0100 addi s0,sp,128 + 637e: 0300 addi s0,sp,384 + 6380: a804 fsd fs1,16(s0) + 6382: 0305 addi t1,t1,1 + 6384: 0900 addi s0,sp,144 + 6386: 0000 unimp + 6388: 0001 nop + 638a: 05a80403 lb s0,90(a6) + 638e: 00090003 lb zero,0(s2) + 6392: 0100 addi s0,sp,128 + 6394: 0200 addi s0,sp,256 + 6396: 2c04 fld fs1,24(s0) + 6398: 0c090003 lb zero,192(s2) + 639c: 0100 addi s0,sp,128 + 639e: 0200 addi s0,sp,256 + 63a0: 2c04 fld fs1,24(s0) + 63a2: 00090003 lb zero,0(s2) + 63a6: 0100 addi s0,sp,128 + 63a8: 0200 addi s0,sp,256 + 63aa: 2c04 fld fs1,24(s0) + 63ac: 00090003 lb zero,0(s2) + 63b0: 0100 addi s0,sp,128 + 63b2: 0200 addi s0,sp,256 + 63b4: 2c04 fld fs1,24(s0) + 63b6: 00090003 lb zero,0(s2) 63ba: 0100 addi s0,sp,128 - 63bc: 0300 addi s0,sp,384 - 63be: a804 fsd fs1,16(s0) - 63c0: 0305 addi t1,t1,1 - 63c2: 0900 addi s0,sp,144 - 63c4: 0000 unimp - 63c6: 0001 nop - 63c8: 05a80403 lb s0,90(a6) - 63cc: 00090003 lb zero,0(s2) - 63d0: 0100 addi s0,sp,128 - 63d2: 0300 addi s0,sp,384 - 63d4: a804 fsd fs1,16(s0) - 63d6: 0305 addi t1,t1,1 - 63d8: 0900 addi s0,sp,144 - 63da: 0000 unimp - 63dc: 0001 nop - 63de: 05a80403 lb s0,90(a6) - 63e2: 00090003 lb zero,0(s2) - 63e6: 0100 addi s0,sp,128 - 63e8: 0200 addi s0,sp,256 - 63ea: 2c04 fld fs1,24(s0) - 63ec: 0c090003 lb zero,192(s2) - 63f0: 0100 addi s0,sp,128 - 63f2: 0200 addi s0,sp,256 - 63f4: 2c04 fld fs1,24(s0) - 63f6: 00090003 lb zero,0(s2) - 63fa: 0100 addi s0,sp,128 - 63fc: 0200 addi s0,sp,256 - 63fe: 2c04 fld fs1,24(s0) - 6400: 00090003 lb zero,0(s2) - 6404: 0100 addi s0,sp,128 - 6406: 0200 addi s0,sp,256 - 6408: 2c04 fld fs1,24(s0) - 640a: 00090003 lb zero,0(s2) - 640e: 0100 addi s0,sp,128 - 6410: 0200 addi s0,sp,256 - 6412: 3304 fld fs1,32(a4) - 6414: 0c090003 lb zero,192(s2) - 6418: 0100 addi s0,sp,128 - 641a: 0200 addi s0,sp,256 - 641c: 3304 fld fs1,32(a4) - 641e: 00090003 lb zero,0(s2) - 6422: 0100 addi s0,sp,128 - 6424: 0200 addi s0,sp,256 - 6426: 3304 fld fs1,32(a4) - 6428: 00090003 lb zero,0(s2) - 642c: 0100 addi s0,sp,128 - 642e: 0200 addi s0,sp,256 - 6430: 3304 fld fs1,32(a4) - 6432: 10090003 lb zero,256(s2) - 6436: 0100 addi s0,sp,128 - 6438: 0200 addi s0,sp,256 - 643a: 3304 fld fs1,32(a4) - 643c: 0c090003 lb zero,192(s2) - 6440: 0100 addi s0,sp,128 - 6442: 0200 addi s0,sp,256 - 6444: 3304 fld fs1,32(a4) - 6446: 00090003 lb zero,0(s2) - 644a: 0100 addi s0,sp,128 - 644c: 0200 addi s0,sp,256 - 644e: 3304 fld fs1,32(a4) - 6450: 0c090003 lb zero,192(s2) - 6454: 0100 addi s0,sp,128 - 6456: 0200 addi s0,sp,256 - 6458: 3304 fld fs1,32(a4) - 645a: 04090003 lb zero,64(s2) - 645e: 0100 addi s0,sp,128 - 6460: 0200 addi s0,sp,256 - 6462: 3604 fld fs1,40(a2) - 6464: 0c090003 lb zero,192(s2) - 6468: 0100 addi s0,sp,128 - 646a: 0200 addi s0,sp,256 - 646c: 3604 fld fs1,40(a2) - 646e: 00090003 lb zero,0(s2) - 6472: 0100 addi s0,sp,128 - 6474: 0200 addi s0,sp,256 - 6476: 3604 fld fs1,40(a2) - 6478: 00090003 lb zero,0(s2) - 647c: 0100 addi s0,sp,128 - 647e: 0200 addi s0,sp,256 - 6480: 4604 lw s1,8(a2) - 6482: 0c090003 lb zero,192(s2) - 6486: 0100 addi s0,sp,128 - 6488: 0200 addi s0,sp,256 - 648a: 4604 lw s1,8(a2) - 648c: 00090003 lb zero,0(s2) - 6490: 0100 addi s0,sp,128 - 6492: 0200 addi s0,sp,256 - 6494: 4604 lw s1,8(a2) - 6496: 08090003 lb zero,128(s2) - 649a: 0100 addi s0,sp,128 - 649c: 0306 slli t1,t1,0x1 - 649e: 0900 addi s0,sp,144 - 64a0: 000c 0xc - 64a2: 0001 nop - 64a4: 0402 c.slli64 s0 - 64a6: 0656 slli a2,a2,0x15 - 64a8: 10090003 lb zero,256(s2) - 64ac: 0100 addi s0,sp,128 - 64ae: 0200 addi s0,sp,256 - 64b0: 5604 lw s1,40(a2) - 64b2: 00090003 lb zero,0(s2) - 64b6: 0100 addi s0,sp,128 - 64b8: 0200 addi s0,sp,256 - 64ba: 5604 lw s1,40(a2) - 64bc: 00090003 lb zero,0(s2) - 64c0: 0100 addi s0,sp,128 - 64c2: 0200 addi s0,sp,256 - 64c4: 5604 lw s1,40(a2) - 64c6: 00090003 lb zero,0(s2) - 64ca: 0100 addi s0,sp,128 - 64cc: 0200 addi s0,sp,256 - 64ce: 5604 lw s1,40(a2) - 64d0: 00090003 lb zero,0(s2) - 64d4: 0100 addi s0,sp,128 - 64d6: 0200 addi s0,sp,256 - 64d8: 5604 lw s1,40(a2) - 64da: 00090003 lb zero,0(s2) - 64de: 0100 addi s0,sp,128 - 64e0: 0200 addi s0,sp,256 - 64e2: 5604 lw s1,40(a2) - 64e4: 00090003 lb zero,0(s2) - 64e8: 0100 addi s0,sp,128 - 64ea: 0200 addi s0,sp,256 - 64ec: 5604 lw s1,40(a2) - 64ee: 00090003 lb zero,0(s2) - 64f2: 0100 addi s0,sp,128 - 64f4: 0200 addi s0,sp,256 - 64f6: 5604 lw s1,40(a2) - 64f8: 00090003 lb zero,0(s2) - 64fc: 0100 addi s0,sp,128 - 64fe: 0200 addi s0,sp,256 - 6500: 5604 lw s1,40(a2) - 6502: 00090003 lb zero,0(s2) - 6506: 0100 addi s0,sp,128 - 6508: 0200 addi s0,sp,256 - 650a: 5e04 lw s1,56(a2) - 650c: 08090003 lb zero,128(s2) - 6510: 0100 addi s0,sp,128 - 6512: 0200 addi s0,sp,256 - 6514: 5e04 lw s1,56(a2) - 6516: 1c090003 lb zero,448(s2) - 651a: 0100 addi s0,sp,128 - 651c: 0200 addi s0,sp,256 - 651e: 5e04 lw s1,56(a2) - 6520: 00090003 lb zero,0(s2) - 6524: 0100 addi s0,sp,128 - 6526: 0200 addi s0,sp,256 - 6528: 5f04 lw s1,56(a4) - 652a: 04090003 lb zero,64(s2) - 652e: 0100 addi s0,sp,128 - 6530: 0200 addi s0,sp,256 - 6532: 5f04 lw s1,56(a4) - 6534: 10090003 lb zero,256(s2) - 6538: 0100 addi s0,sp,128 - 653a: 0200 addi s0,sp,256 - 653c: 5f04 lw s1,56(a4) - 653e: 00090003 lb zero,0(s2) - 6542: 0100 addi s0,sp,128 - 6544: 0200 addi s0,sp,256 - 6546: 5f04 lw s1,56(a4) - 6548: 00090003 lb zero,0(s2) - 654c: 0100 addi s0,sp,128 - 654e: 0200 addi s0,sp,256 - 6550: 6404 flw fs1,8(s0) - 6552: 0306 slli t1,t1,0x1 - 6554: 0900 addi s0,sp,144 - 6556: 0008 0x8 - 6558: 0001 nop - 655a: 0402 c.slli64 s0 - 655c: 0668 addi a0,sp,780 - 655e: 1c090003 lb zero,448(s2) - 6562: 0100 addi s0,sp,128 - 6564: 0200 addi s0,sp,256 - 6566: 6804 flw fs1,16(s0) - 6568: 00090003 lb zero,0(s2) - 656c: 0100 addi s0,sp,128 - 656e: 0200 addi s0,sp,256 - 6570: 6804 flw fs1,16(s0) - 6572: 10090003 lb zero,256(s2) - 6576: 0100 addi s0,sp,128 - 6578: 0200 addi s0,sp,256 - 657a: 6e04 flw fs1,24(a2) - 657c: 04090003 lb zero,64(s2) - 6580: 0100 addi s0,sp,128 - 6582: 0200 addi s0,sp,256 - 6584: 6e04 flw fs1,24(a2) - 6586: 00090003 lb zero,0(s2) - 658a: 0100 addi s0,sp,128 - 658c: 0200 addi s0,sp,256 - 658e: 6e04 flw fs1,24(a2) - 6590: 00090003 lb zero,0(s2) - 6594: 0100 addi s0,sp,128 - 6596: 0200 addi s0,sp,256 - 6598: 6e04 flw fs1,24(a2) - 659a: 00090003 lb zero,0(s2) - 659e: 0100 addi s0,sp,128 - 65a0: 0200 addi s0,sp,256 - 65a2: 6e04 flw fs1,24(a2) - 65a4: 00090003 lb zero,0(s2) - 65a8: 0100 addi s0,sp,128 - 65aa: 0200 addi s0,sp,256 - 65ac: 6e04 flw fs1,24(a2) - 65ae: 00090003 lb zero,0(s2) - 65b2: 0100 addi s0,sp,128 - 65b4: 0200 addi s0,sp,256 - 65b6: 6e04 flw fs1,24(a2) - 65b8: 00090003 lb zero,0(s2) - 65bc: 0100 addi s0,sp,128 - 65be: 0200 addi s0,sp,256 - 65c0: 6e04 flw fs1,24(a2) - 65c2: 00090003 lb zero,0(s2) - 65c6: 0100 addi s0,sp,128 - 65c8: 0200 addi s0,sp,256 - 65ca: 6e04 flw fs1,24(a2) - 65cc: 10090003 lb zero,256(s2) - 65d0: 0100 addi s0,sp,128 - 65d2: 0200 addi s0,sp,256 - 65d4: 6e04 flw fs1,24(a2) - 65d6: 00090003 lb zero,0(s2) - 65da: 0100 addi s0,sp,128 - 65dc: 0a05 addi s4,s4,1 - 65de: 0200 addi s0,sp,256 - 65e0: 6e04 flw fs1,24(a2) - 65e2: 0306 slli t1,t1,0x1 - 65e4: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> - 65e8: 0501 addi a0,a0,0 - 65ea: 04020003 lb zero,64(tp) # 1d040 <_start-0x7ffe2fc0> - 65ee: 036e slli t1,t1,0x1b - 65f0: 097d addi s2,s2,31 - 65f2: 0004 0x4 - 65f4: 0501 addi a0,a0,0 - 65f6: 000a c.slli zero,0x2 - 65f8: 0402 c.slli64 s0 - 65fa: 036e slli t1,t1,0x1b - 65fc: 00080903 lb s2,0(a6) - 6600: 0501 addi a0,a0,0 - 6602: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> - 6606: 036e slli t1,t1,0x1b - 6608: 097d addi s2,s2,31 - 660a: 0008 0x8 - 660c: 0001 nop - 660e: 0402 c.slli64 s0 - 6610: 066e slli a2,a2,0x1b - 6612: 04090003 lb zero,64(s2) - 6616: 0100 addi s0,sp,128 - 6618: 0200 addi s0,sp,256 - 661a: 6e04 flw fs1,24(a2) - 661c: 00090003 lb zero,0(s2) - 6620: 0100 addi s0,sp,128 - 6622: 0200 addi s0,sp,256 - 6624: 6e04 flw fs1,24(a2) - 6626: 00090003 lb zero,0(s2) - 662a: 0100 addi s0,sp,128 - 662c: 0200 addi s0,sp,256 - 662e: 6e04 flw fs1,24(a2) - 6630: 00090103 lb sp,0(s2) - 6634: 0100 addi s0,sp,128 - 6636: 0200 addi s0,sp,256 - 6638: 6e04 flw fs1,24(a2) - 663a: 00090003 lb zero,0(s2) - 663e: 0100 addi s0,sp,128 - 6640: 0200 addi s0,sp,256 - 6642: 6e04 flw fs1,24(a2) - 6644: 00090003 lb zero,0(s2) - 6648: 0100 addi s0,sp,128 - 664a: 0200 addi s0,sp,256 - 664c: 6e04 flw fs1,24(a2) - 664e: 00090203 lb tp,0(s2) - 6652: 0100 addi s0,sp,128 - 6654: 0105 addi sp,sp,1 - 6656: 0200 addi s0,sp,256 - 6658: 6e04 flw fs1,24(a2) - 665a: 0306 slli t1,t1,0x1 - 665c: 0901 addi s2,s2,0 - 665e: 0000 unimp - 6660: 0501 addi a0,a0,0 - 6662: 000a c.slli zero,0x2 - 6664: 0402 c.slli64 s0 - 6666: 036e slli t1,t1,0x1b - 6668: 097f 0x97f - 666a: 0004 0x4 - 666c: 0501 addi a0,a0,0 - 666e: 0001 nop - 6670: 0402 c.slli64 s0 - 6672: 036e slli t1,t1,0x1b - 6674: 0901 addi s2,s2,0 - 6676: 0008 0x8 - 6678: 0501 addi a0,a0,0 - 667a: 000a c.slli zero,0x2 - 667c: 0402 c.slli64 s0 - 667e: 036e slli t1,t1,0x1b - 6680: 097f 0x97f - 6682: 0008 0x8 - 6684: 0501 addi a0,a0,0 - 6686: 0001 nop - 6688: 0402 c.slli64 s0 - 668a: 036e slli t1,t1,0x1b - 668c: 0901 addi s2,s2,0 - 668e: 0008 0x8 - 6690: 0501 addi a0,a0,0 - 6692: 000a c.slli zero,0x2 - 6694: 0402 c.slli64 s0 - 6696: 036e slli t1,t1,0x1b - 6698: 097f 0x97f - 669a: 0008 0x8 - 669c: 0501 addi a0,a0,0 - 669e: 0001 nop - 66a0: 0402 c.slli64 s0 - 66a2: 036e slli t1,t1,0x1b - 66a4: 0901 addi s2,s2,0 - 66a6: 0004 0x4 - 66a8: 0501 addi a0,a0,0 - 66aa: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> - 66ae: 7b03062b 0x7b03062b - 66b2: 1809 addi a6,a6,-30 - 66b4: 0100 addi s0,sp,128 - 66b6: 0200 addi s0,sp,256 - 66b8: 2b04 fld fs1,16(a4) - 66ba: 10090003 lb zero,256(s2) - 66be: 0100 addi s0,sp,128 - 66c0: 0200 addi s0,sp,256 - 66c2: 3504 fld fs1,40(a0) - 66c4: 0c090003 lb zero,192(s2) - 66c8: 0100 addi s0,sp,128 - 66ca: 0200 addi s0,sp,256 - 66cc: 3504 fld fs1,40(a0) - 66ce: 00090003 lb zero,0(s2) - 66d2: 0100 addi s0,sp,128 - 66d4: 0200 addi s0,sp,256 - 66d6: 3504 fld fs1,40(a0) - 66d8: 00090003 lb zero,0(s2) - 66dc: 0100 addi s0,sp,128 - 66de: 0200 addi s0,sp,256 - 66e0: 3504 fld fs1,40(a0) - 66e2: 00090003 lb zero,0(s2) - 66e6: 0100 addi s0,sp,128 - 66e8: 0200 addi s0,sp,256 - 66ea: 3504 fld fs1,40(a0) - 66ec: 00090003 lb zero,0(s2) - 66f0: 0100 addi s0,sp,128 - 66f2: 0200 addi s0,sp,256 - 66f4: 3504 fld fs1,40(a0) - 66f6: 00090003 lb zero,0(s2) - 66fa: 0100 addi s0,sp,128 - 66fc: 0200 addi s0,sp,256 - 66fe: 3504 fld fs1,40(a0) - 6700: 00090003 lb zero,0(s2) - 6704: 0100 addi s0,sp,128 - 6706: 0200 addi s0,sp,256 - 6708: 3504 fld fs1,40(a0) - 670a: 04090003 lb zero,64(s2) - 670e: 0100 addi s0,sp,128 - 6710: 0200 addi s0,sp,256 - 6712: 3504 fld fs1,40(a0) - 6714: 00090003 lb zero,0(s2) - 6718: 0100 addi s0,sp,128 - 671a: 0200 addi s0,sp,256 - 671c: 3504 fld fs1,40(a0) - 671e: 00090003 lb zero,0(s2) - 6722: 0100 addi s0,sp,128 - 6724: 0200 addi s0,sp,256 - 6726: 3704 fld fs1,40(a4) - 6728: 08090003 lb zero,128(s2) - 672c: 0100 addi s0,sp,128 - 672e: 0200 addi s0,sp,256 - 6730: 3a04 fld fs1,48(a2) - 6732: 04090003 lb zero,64(s2) - 6736: 0100 addi s0,sp,128 - 6738: 0306 slli t1,t1,0x1 - 673a: 0900 addi s0,sp,144 - 673c: 000c 0xc - 673e: 0001 nop - 6740: 0402 c.slli64 s0 - 6742: 0003063f 01000c09 0x1000c090003063f - 674a: 0200 addi s0,sp,256 - 674c: 3f04 fld fs1,56(a4) - 674e: 14090003 lb zero,320(s2) - 6752: 0100 addi s0,sp,128 - 6754: 0200 addi s0,sp,256 - 6756: 3f04 fld fs1,56(a4) - 6758: 00090003 lb zero,0(s2) + 63bc: 0200 addi s0,sp,256 + 63be: 3304 fld fs1,32(a4) + 63c0: 0c090003 lb zero,192(s2) + 63c4: 0100 addi s0,sp,128 + 63c6: 0200 addi s0,sp,256 + 63c8: 3304 fld fs1,32(a4) + 63ca: 00090003 lb zero,0(s2) + 63ce: 0100 addi s0,sp,128 + 63d0: 0200 addi s0,sp,256 + 63d2: 3304 fld fs1,32(a4) + 63d4: 00090003 lb zero,0(s2) + 63d8: 0100 addi s0,sp,128 + 63da: 0200 addi s0,sp,256 + 63dc: 3304 fld fs1,32(a4) + 63de: 10090003 lb zero,256(s2) + 63e2: 0100 addi s0,sp,128 + 63e4: 0200 addi s0,sp,256 + 63e6: 3304 fld fs1,32(a4) + 63e8: 0c090003 lb zero,192(s2) + 63ec: 0100 addi s0,sp,128 + 63ee: 0200 addi s0,sp,256 + 63f0: 3304 fld fs1,32(a4) + 63f2: 00090003 lb zero,0(s2) + 63f6: 0100 addi s0,sp,128 + 63f8: 0200 addi s0,sp,256 + 63fa: 3304 fld fs1,32(a4) + 63fc: 0c090003 lb zero,192(s2) + 6400: 0100 addi s0,sp,128 + 6402: 0200 addi s0,sp,256 + 6404: 3304 fld fs1,32(a4) + 6406: 04090003 lb zero,64(s2) + 640a: 0100 addi s0,sp,128 + 640c: 0200 addi s0,sp,256 + 640e: 3604 fld fs1,40(a2) + 6410: 0c090003 lb zero,192(s2) + 6414: 0100 addi s0,sp,128 + 6416: 0200 addi s0,sp,256 + 6418: 3604 fld fs1,40(a2) + 641a: 00090003 lb zero,0(s2) + 641e: 0100 addi s0,sp,128 + 6420: 0200 addi s0,sp,256 + 6422: 3604 fld fs1,40(a2) + 6424: 00090003 lb zero,0(s2) + 6428: 0100 addi s0,sp,128 + 642a: 0200 addi s0,sp,256 + 642c: 4604 lw s1,8(a2) + 642e: 0c090003 lb zero,192(s2) + 6432: 0100 addi s0,sp,128 + 6434: 0200 addi s0,sp,256 + 6436: 4604 lw s1,8(a2) + 6438: 00090003 lb zero,0(s2) + 643c: 0100 addi s0,sp,128 + 643e: 0200 addi s0,sp,256 + 6440: 4604 lw s1,8(a2) + 6442: 08090003 lb zero,128(s2) + 6446: 0100 addi s0,sp,128 + 6448: 0306 slli t1,t1,0x1 + 644a: 0900 addi s0,sp,144 + 644c: 000c 0xc + 644e: 0001 nop + 6450: 0402 c.slli64 s0 + 6452: 0656 slli a2,a2,0x15 + 6454: 10090003 lb zero,256(s2) + 6458: 0100 addi s0,sp,128 + 645a: 0200 addi s0,sp,256 + 645c: 5604 lw s1,40(a2) + 645e: 00090003 lb zero,0(s2) + 6462: 0100 addi s0,sp,128 + 6464: 0200 addi s0,sp,256 + 6466: 5604 lw s1,40(a2) + 6468: 00090003 lb zero,0(s2) + 646c: 0100 addi s0,sp,128 + 646e: 0200 addi s0,sp,256 + 6470: 5604 lw s1,40(a2) + 6472: 00090003 lb zero,0(s2) + 6476: 0100 addi s0,sp,128 + 6478: 0200 addi s0,sp,256 + 647a: 5604 lw s1,40(a2) + 647c: 00090003 lb zero,0(s2) + 6480: 0100 addi s0,sp,128 + 6482: 0200 addi s0,sp,256 + 6484: 5604 lw s1,40(a2) + 6486: 00090003 lb zero,0(s2) + 648a: 0100 addi s0,sp,128 + 648c: 0200 addi s0,sp,256 + 648e: 5604 lw s1,40(a2) + 6490: 00090003 lb zero,0(s2) + 6494: 0100 addi s0,sp,128 + 6496: 0200 addi s0,sp,256 + 6498: 5604 lw s1,40(a2) + 649a: 00090003 lb zero,0(s2) + 649e: 0100 addi s0,sp,128 + 64a0: 0200 addi s0,sp,256 + 64a2: 5604 lw s1,40(a2) + 64a4: 00090003 lb zero,0(s2) + 64a8: 0100 addi s0,sp,128 + 64aa: 0200 addi s0,sp,256 + 64ac: 5604 lw s1,40(a2) + 64ae: 00090003 lb zero,0(s2) + 64b2: 0100 addi s0,sp,128 + 64b4: 0200 addi s0,sp,256 + 64b6: 5e04 lw s1,56(a2) + 64b8: 08090003 lb zero,128(s2) + 64bc: 0100 addi s0,sp,128 + 64be: 0200 addi s0,sp,256 + 64c0: 5e04 lw s1,56(a2) + 64c2: 1c090003 lb zero,448(s2) + 64c6: 0100 addi s0,sp,128 + 64c8: 0200 addi s0,sp,256 + 64ca: 5e04 lw s1,56(a2) + 64cc: 00090003 lb zero,0(s2) + 64d0: 0100 addi s0,sp,128 + 64d2: 0200 addi s0,sp,256 + 64d4: 5f04 lw s1,56(a4) + 64d6: 04090003 lb zero,64(s2) + 64da: 0100 addi s0,sp,128 + 64dc: 0200 addi s0,sp,256 + 64de: 5f04 lw s1,56(a4) + 64e0: 10090003 lb zero,256(s2) + 64e4: 0100 addi s0,sp,128 + 64e6: 0200 addi s0,sp,256 + 64e8: 5f04 lw s1,56(a4) + 64ea: 00090003 lb zero,0(s2) + 64ee: 0100 addi s0,sp,128 + 64f0: 0200 addi s0,sp,256 + 64f2: 5f04 lw s1,56(a4) + 64f4: 00090003 lb zero,0(s2) + 64f8: 0100 addi s0,sp,128 + 64fa: 0200 addi s0,sp,256 + 64fc: 6404 flw fs1,8(s0) + 64fe: 0306 slli t1,t1,0x1 + 6500: 0900 addi s0,sp,144 + 6502: 0008 0x8 + 6504: 0001 nop + 6506: 0402 c.slli64 s0 + 6508: 0668 addi a0,sp,780 + 650a: 1c090003 lb zero,448(s2) + 650e: 0100 addi s0,sp,128 + 6510: 0200 addi s0,sp,256 + 6512: 6804 flw fs1,16(s0) + 6514: 00090003 lb zero,0(s2) + 6518: 0100 addi s0,sp,128 + 651a: 0200 addi s0,sp,256 + 651c: 6804 flw fs1,16(s0) + 651e: 10090003 lb zero,256(s2) + 6522: 0100 addi s0,sp,128 + 6524: 0200 addi s0,sp,256 + 6526: 6e04 flw fs1,24(a2) + 6528: 04090003 lb zero,64(s2) + 652c: 0100 addi s0,sp,128 + 652e: 0200 addi s0,sp,256 + 6530: 6e04 flw fs1,24(a2) + 6532: 00090003 lb zero,0(s2) + 6536: 0100 addi s0,sp,128 + 6538: 0200 addi s0,sp,256 + 653a: 6e04 flw fs1,24(a2) + 653c: 00090003 lb zero,0(s2) + 6540: 0100 addi s0,sp,128 + 6542: 0200 addi s0,sp,256 + 6544: 6e04 flw fs1,24(a2) + 6546: 00090003 lb zero,0(s2) + 654a: 0100 addi s0,sp,128 + 654c: 0200 addi s0,sp,256 + 654e: 6e04 flw fs1,24(a2) + 6550: 00090003 lb zero,0(s2) + 6554: 0100 addi s0,sp,128 + 6556: 0200 addi s0,sp,256 + 6558: 6e04 flw fs1,24(a2) + 655a: 00090003 lb zero,0(s2) + 655e: 0100 addi s0,sp,128 + 6560: 0200 addi s0,sp,256 + 6562: 6e04 flw fs1,24(a2) + 6564: 00090003 lb zero,0(s2) + 6568: 0100 addi s0,sp,128 + 656a: 0200 addi s0,sp,256 + 656c: 6e04 flw fs1,24(a2) + 656e: 00090003 lb zero,0(s2) + 6572: 0100 addi s0,sp,128 + 6574: 0200 addi s0,sp,256 + 6576: 6e04 flw fs1,24(a2) + 6578: 10090003 lb zero,256(s2) + 657c: 0100 addi s0,sp,128 + 657e: 0200 addi s0,sp,256 + 6580: 6e04 flw fs1,24(a2) + 6582: 00090003 lb zero,0(s2) + 6586: 0100 addi s0,sp,128 + 6588: 0a05 addi s4,s4,1 + 658a: 0200 addi s0,sp,256 + 658c: 6e04 flw fs1,24(a2) + 658e: 0306 slli t1,t1,0x1 + 6590: 00000903 lb s2,0(zero) # 0 <_start-0x80000000> + 6594: 0501 addi a0,a0,0 + 6596: 04020003 lb zero,64(tp) # 1d040 <_start-0x7ffe2fc0> + 659a: 036e slli t1,t1,0x1b + 659c: 097d addi s2,s2,31 + 659e: 0004 0x4 + 65a0: 0501 addi a0,a0,0 + 65a2: 000a c.slli zero,0x2 + 65a4: 0402 c.slli64 s0 + 65a6: 036e slli t1,t1,0x1b + 65a8: 00080903 lb s2,0(a6) + 65ac: 0501 addi a0,a0,0 + 65ae: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> + 65b2: 036e slli t1,t1,0x1b + 65b4: 097d addi s2,s2,31 + 65b6: 0008 0x8 + 65b8: 0001 nop + 65ba: 0402 c.slli64 s0 + 65bc: 066e slli a2,a2,0x1b + 65be: 04090003 lb zero,64(s2) + 65c2: 0100 addi s0,sp,128 + 65c4: 0200 addi s0,sp,256 + 65c6: 6e04 flw fs1,24(a2) + 65c8: 00090003 lb zero,0(s2) + 65cc: 0100 addi s0,sp,128 + 65ce: 0200 addi s0,sp,256 + 65d0: 6e04 flw fs1,24(a2) + 65d2: 00090003 lb zero,0(s2) + 65d6: 0100 addi s0,sp,128 + 65d8: 0200 addi s0,sp,256 + 65da: 6e04 flw fs1,24(a2) + 65dc: 00090103 lb sp,0(s2) + 65e0: 0100 addi s0,sp,128 + 65e2: 0200 addi s0,sp,256 + 65e4: 6e04 flw fs1,24(a2) + 65e6: 00090003 lb zero,0(s2) + 65ea: 0100 addi s0,sp,128 + 65ec: 0200 addi s0,sp,256 + 65ee: 6e04 flw fs1,24(a2) + 65f0: 00090003 lb zero,0(s2) + 65f4: 0100 addi s0,sp,128 + 65f6: 0200 addi s0,sp,256 + 65f8: 6e04 flw fs1,24(a2) + 65fa: 00090203 lb tp,0(s2) + 65fe: 0100 addi s0,sp,128 + 6600: 0105 addi sp,sp,1 + 6602: 0200 addi s0,sp,256 + 6604: 6e04 flw fs1,24(a2) + 6606: 0306 slli t1,t1,0x1 + 6608: 0901 addi s2,s2,0 + 660a: 0000 unimp + 660c: 0501 addi a0,a0,0 + 660e: 000a c.slli zero,0x2 + 6610: 0402 c.slli64 s0 + 6612: 036e slli t1,t1,0x1b + 6614: 097f 0x97f + 6616: 0004 0x4 + 6618: 0501 addi a0,a0,0 + 661a: 0001 nop + 661c: 0402 c.slli64 s0 + 661e: 036e slli t1,t1,0x1b + 6620: 0901 addi s2,s2,0 + 6622: 0008 0x8 + 6624: 0501 addi a0,a0,0 + 6626: 000a c.slli zero,0x2 + 6628: 0402 c.slli64 s0 + 662a: 036e slli t1,t1,0x1b + 662c: 097f 0x97f + 662e: 0008 0x8 + 6630: 0501 addi a0,a0,0 + 6632: 0001 nop + 6634: 0402 c.slli64 s0 + 6636: 036e slli t1,t1,0x1b + 6638: 0901 addi s2,s2,0 + 663a: 0008 0x8 + 663c: 0501 addi a0,a0,0 + 663e: 000a c.slli zero,0x2 + 6640: 0402 c.slli64 s0 + 6642: 036e slli t1,t1,0x1b + 6644: 097f 0x97f + 6646: 0008 0x8 + 6648: 0501 addi a0,a0,0 + 664a: 0001 nop + 664c: 0402 c.slli64 s0 + 664e: 036e slli t1,t1,0x1b + 6650: 0901 addi s2,s2,0 + 6652: 0004 0x4 + 6654: 0501 addi a0,a0,0 + 6656: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> + 665a: 7b03062b 0x7b03062b + 665e: 1809 addi a6,a6,-30 + 6660: 0100 addi s0,sp,128 + 6662: 0200 addi s0,sp,256 + 6664: 2b04 fld fs1,16(a4) + 6666: 10090003 lb zero,256(s2) + 666a: 0100 addi s0,sp,128 + 666c: 0200 addi s0,sp,256 + 666e: 3504 fld fs1,40(a0) + 6670: 0c090003 lb zero,192(s2) + 6674: 0100 addi s0,sp,128 + 6676: 0200 addi s0,sp,256 + 6678: 3504 fld fs1,40(a0) + 667a: 00090003 lb zero,0(s2) + 667e: 0100 addi s0,sp,128 + 6680: 0200 addi s0,sp,256 + 6682: 3504 fld fs1,40(a0) + 6684: 00090003 lb zero,0(s2) + 6688: 0100 addi s0,sp,128 + 668a: 0200 addi s0,sp,256 + 668c: 3504 fld fs1,40(a0) + 668e: 00090003 lb zero,0(s2) + 6692: 0100 addi s0,sp,128 + 6694: 0200 addi s0,sp,256 + 6696: 3504 fld fs1,40(a0) + 6698: 00090003 lb zero,0(s2) + 669c: 0100 addi s0,sp,128 + 669e: 0200 addi s0,sp,256 + 66a0: 3504 fld fs1,40(a0) + 66a2: 00090003 lb zero,0(s2) + 66a6: 0100 addi s0,sp,128 + 66a8: 0200 addi s0,sp,256 + 66aa: 3504 fld fs1,40(a0) + 66ac: 00090003 lb zero,0(s2) + 66b0: 0100 addi s0,sp,128 + 66b2: 0200 addi s0,sp,256 + 66b4: 3504 fld fs1,40(a0) + 66b6: 04090003 lb zero,64(s2) + 66ba: 0100 addi s0,sp,128 + 66bc: 0200 addi s0,sp,256 + 66be: 3504 fld fs1,40(a0) + 66c0: 00090003 lb zero,0(s2) + 66c4: 0100 addi s0,sp,128 + 66c6: 0200 addi s0,sp,256 + 66c8: 3504 fld fs1,40(a0) + 66ca: 00090003 lb zero,0(s2) + 66ce: 0100 addi s0,sp,128 + 66d0: 0200 addi s0,sp,256 + 66d2: 3704 fld fs1,40(a4) + 66d4: 08090003 lb zero,128(s2) + 66d8: 0100 addi s0,sp,128 + 66da: 0200 addi s0,sp,256 + 66dc: 3a04 fld fs1,48(a2) + 66de: 04090003 lb zero,64(s2) + 66e2: 0100 addi s0,sp,128 + 66e4: 0306 slli t1,t1,0x1 + 66e6: 0900 addi s0,sp,144 + 66e8: 000c 0xc + 66ea: 0001 nop + 66ec: 0402 c.slli64 s0 + 66ee: 0003063f 01000c09 0x1000c090003063f + 66f6: 0200 addi s0,sp,256 + 66f8: 3f04 fld fs1,56(a4) + 66fa: 14090003 lb zero,320(s2) + 66fe: 0100 addi s0,sp,128 + 6700: 0200 addi s0,sp,256 + 6702: 3f04 fld fs1,56(a4) + 6704: 00090003 lb zero,0(s2) + 6708: 0100 addi s0,sp,128 + 670a: 0200 addi s0,sp,256 + 670c: 3904 fld fs1,48(a0) + 670e: 1c090003 lb zero,448(s2) + 6712: 0100 addi s0,sp,128 + 6714: 0200 addi s0,sp,256 + 6716: 3904 fld fs1,48(a0) + 6718: 14090003 lb zero,320(s2) + 671c: 0100 addi s0,sp,128 + 671e: 0200 addi s0,sp,256 + 6720: 3c04 fld fs1,56(s0) + 6722: 0306 slli t1,t1,0x1 + 6724: 0900 addi s0,sp,144 + 6726: 0004 0x4 + 6728: 0001 nop + 672a: 0402 c.slli64 s0 + 672c: 063c addi a5,sp,776 + 672e: 14090003 lb zero,320(s2) + 6732: 0100 addi s0,sp,128 + 6734: 0200 addi s0,sp,256 + 6736: 3c04 fld fs1,56(s0) + 6738: 0c090003 lb zero,192(s2) + 673c: 0100 addi s0,sp,128 + 673e: 0200 addi s0,sp,256 + 6740: 4004 lw s1,0(s0) + 6742: 0c090003 lb zero,192(s2) + 6746: 0100 addi s0,sp,128 + 6748: 0200 addi s0,sp,256 + 674a: 4304 lw s1,0(a4) + 674c: 0306 slli t1,t1,0x1 + 674e: 0900 addi s0,sp,144 + 6750: 0008 0x8 + 6752: 0001 nop + 6754: 0402 c.slli64 s0 + 6756: 00030643 fmadd.s fa2,ft6,ft0,ft0,rne + 675a: 1809 addi a6,a6,-30 675c: 0100 addi s0,sp,128 675e: 0200 addi s0,sp,256 - 6760: 3904 fld fs1,48(a0) - 6762: 1c090003 lb zero,448(s2) - 6766: 0100 addi s0,sp,128 - 6768: 0200 addi s0,sp,256 - 676a: 3904 fld fs1,48(a0) - 676c: 14090003 lb zero,320(s2) - 6770: 0100 addi s0,sp,128 - 6772: 0200 addi s0,sp,256 - 6774: 3c04 fld fs1,56(s0) - 6776: 0306 slli t1,t1,0x1 - 6778: 0900 addi s0,sp,144 - 677a: 0004 0x4 - 677c: 0001 nop - 677e: 0402 c.slli64 s0 - 6780: 063c addi a5,sp,776 - 6782: 14090003 lb zero,320(s2) + 6760: 4504 lw s1,8(a0) + 6762: 0306 slli t1,t1,0x1 + 6764: 0900 addi s0,sp,144 + 6766: 0008 0x8 + 6768: 0001 nop + 676a: 0402 c.slli64 s0 + 676c: 0642 slli a2,a2,0x10 + 676e: 08090003 lb zero,128(s2) + 6772: 0100 addi s0,sp,128 + 6774: 0200 addi s0,sp,256 + 6776: 4204 lw s1,0(a2) + 6778: 20090003 lb zero,512(s2) + 677c: 0100 addi s0,sp,128 + 677e: 0200 addi s0,sp,256 + 6780: 4604 lw s1,8(a2) + 6782: 08090003 lb zero,128(s2) 6786: 0100 addi s0,sp,128 6788: 0200 addi s0,sp,256 - 678a: 3c04 fld fs1,56(s0) + 678a: 4604 lw s1,8(a2) 678c: 0c090003 lb zero,192(s2) 6790: 0100 addi s0,sp,128 6792: 0200 addi s0,sp,256 - 6794: 4004 lw s1,0(s0) - 6796: 0c090003 lb zero,192(s2) + 6794: 4504 lw s1,8(a0) + 6796: 04090003 lb zero,64(s2) 679a: 0100 addi s0,sp,128 679c: 0200 addi s0,sp,256 - 679e: 4304 lw s1,0(a4) - 67a0: 0306 slli t1,t1,0x1 - 67a2: 0900 addi s0,sp,144 - 67a4: 0008 0x8 - 67a6: 0001 nop - 67a8: 0402 c.slli64 s0 - 67aa: 00030643 fmadd.s fa2,ft6,ft0,ft0,rne - 67ae: 1809 addi a6,a6,-30 - 67b0: 0100 addi s0,sp,128 - 67b2: 0200 addi s0,sp,256 - 67b4: 4504 lw s1,8(a0) - 67b6: 0306 slli t1,t1,0x1 - 67b8: 0900 addi s0,sp,144 - 67ba: 0008 0x8 - 67bc: 0001 nop - 67be: 0402 c.slli64 s0 - 67c0: 0642 slli a2,a2,0x10 - 67c2: 08090003 lb zero,128(s2) + 679e: 4704 lw s1,8(a4) + 67a0: 04090003 lb zero,64(s2) + 67a4: 0100 addi s0,sp,128 + 67a6: 0200 addi s0,sp,256 + 67a8: 4704 lw s1,8(a4) + 67aa: 00090003 lb zero,0(s2) + 67ae: 0100 addi s0,sp,128 + 67b0: 0200 addi s0,sp,256 + 67b2: 4704 lw s1,8(a4) + 67b4: 00090003 lb zero,0(s2) + 67b8: 0100 addi s0,sp,128 + 67ba: 0306 slli t1,t1,0x1 + 67bc: 0900 addi s0,sp,144 + 67be: 000c 0xc + 67c0: 0601 addi a2,a2,0 + 67c2: 04090003 lb zero,64(s2) 67c6: 0100 addi s0,sp,128 - 67c8: 0200 addi s0,sp,256 - 67ca: 4204 lw s1,0(a2) - 67cc: 20090003 lb zero,512(s2) - 67d0: 0100 addi s0,sp,128 - 67d2: 0200 addi s0,sp,256 - 67d4: 4604 lw s1,8(a2) - 67d6: 08090003 lb zero,128(s2) - 67da: 0100 addi s0,sp,128 - 67dc: 0200 addi s0,sp,256 - 67de: 4604 lw s1,8(a2) - 67e0: 0c090003 lb zero,192(s2) + 67c8: 00090003 lb zero,0(s2) + 67cc: 0100 addi s0,sp,128 + 67ce: 00090003 lb zero,0(s2) + 67d2: 0100 addi s0,sp,128 + 67d4: 00090003 lb zero,0(s2) + 67d8: 0100 addi s0,sp,128 + 67da: 1c090003 lb zero,448(s2) + 67de: 0100 addi s0,sp,128 + 67e0: 00090003 lb zero,0(s2) 67e4: 0100 addi s0,sp,128 - 67e6: 0200 addi s0,sp,256 - 67e8: 4504 lw s1,8(a0) - 67ea: 04090003 lb zero,64(s2) - 67ee: 0100 addi s0,sp,128 - 67f0: 0200 addi s0,sp,256 - 67f2: 4704 lw s1,8(a4) - 67f4: 04090003 lb zero,64(s2) - 67f8: 0100 addi s0,sp,128 - 67fa: 0200 addi s0,sp,256 - 67fc: 4704 lw s1,8(a4) - 67fe: 00090003 lb zero,0(s2) + 67e6: 00090003 lb zero,0(s2) + 67ea: 0100 addi s0,sp,128 + 67ec: 00090003 lb zero,0(s2) + 67f0: 0100 addi s0,sp,128 + 67f2: 14090003 lb zero,320(s2) + 67f6: 0100 addi s0,sp,128 + 67f8: 00090003 lb zero,0(s2) + 67fc: 0100 addi s0,sp,128 + 67fe: 04090003 lb zero,64(s2) 6802: 0100 addi s0,sp,128 - 6804: 0200 addi s0,sp,256 - 6806: 4704 lw s1,8(a4) - 6808: 00090003 lb zero,0(s2) - 680c: 0100 addi s0,sp,128 - 680e: 0306 slli t1,t1,0x1 - 6810: 0900 addi s0,sp,144 - 6812: 000c 0xc - 6814: 0601 addi a2,a2,0 - 6816: 04090003 lb zero,64(s2) + 6804: 00090003 lb zero,0(s2) + 6808: 0100 addi s0,sp,128 + 680a: 0c090003 lb zero,192(s2) + 680e: 0100 addi s0,sp,128 + 6810: 00090003 lb zero,0(s2) + 6814: 0100 addi s0,sp,128 + 6816: 18090003 lb zero,384(s2) 681a: 0100 addi s0,sp,128 - 681c: 00090003 lb zero,0(s2) - 6820: 0100 addi s0,sp,128 - 6822: 00090003 lb zero,0(s2) - 6826: 0100 addi s0,sp,128 - 6828: 00090003 lb zero,0(s2) - 682c: 0100 addi s0,sp,128 - 682e: 1c090003 lb zero,448(s2) - 6832: 0100 addi s0,sp,128 - 6834: 00090003 lb zero,0(s2) - 6838: 0100 addi s0,sp,128 - 683a: 00090003 lb zero,0(s2) - 683e: 0100 addi s0,sp,128 - 6840: 00090003 lb zero,0(s2) - 6844: 0100 addi s0,sp,128 - 6846: 14090003 lb zero,320(s2) - 684a: 0100 addi s0,sp,128 - 684c: 00090003 lb zero,0(s2) - 6850: 0100 addi s0,sp,128 - 6852: 04090003 lb zero,64(s2) - 6856: 0100 addi s0,sp,128 + 681c: 0300 addi s0,sp,384 + 681e: 8b04 0x8b04 + 6820: 0301 addi t1,t1,0 + 6822: 0900 addi s0,sp,144 + 6824: 0000 unimp + 6826: 0001 nop + 6828: 01fa0403 lb s0,31(s4) + 682c: 0c090003 lb zero,192(s2) + 6830: 0100 addi s0,sp,128 + 6832: 0300 addi s0,sp,384 + 6834: fa04 fsw fs1,48(a2) + 6836: 0301 addi t1,t1,0 + 6838: 0900 addi s0,sp,144 + 683a: 0010 0x10 + 683c: 0001 nop + 683e: 01fa0403 lb s0,31(s4) + 6842: 08090003 lb zero,128(s2) + 6846: 0100 addi s0,sp,128 + 6848: 0300 addi s0,sp,384 + 684a: fa04 fsw fs1,48(a2) + 684c: 0301 addi t1,t1,0 + 684e: 0900 addi s0,sp,144 + 6850: 0000 unimp + 6852: 0001 nop + 6854: 01fa0403 lb s0,31(s4) 6858: 00090003 lb zero,0(s2) 685c: 0100 addi s0,sp,128 - 685e: 0c090003 lb zero,192(s2) - 6862: 0100 addi s0,sp,128 - 6864: 00090003 lb zero,0(s2) - 6868: 0100 addi s0,sp,128 - 686a: 18090003 lb zero,384(s2) - 686e: 0100 addi s0,sp,128 - 6870: 0300 addi s0,sp,384 - 6872: 8b04 0x8b04 - 6874: 0301 addi t1,t1,0 - 6876: 0900 addi s0,sp,144 - 6878: 0000 unimp - 687a: 0001 nop - 687c: 01fa0403 lb s0,31(s4) - 6880: 0c090003 lb zero,192(s2) - 6884: 0100 addi s0,sp,128 - 6886: 0300 addi s0,sp,384 - 6888: fa04 fsw fs1,48(a2) - 688a: 0301 addi t1,t1,0 - 688c: 0900 addi s0,sp,144 - 688e: 0010 0x10 - 6890: 0001 nop - 6892: 01fa0403 lb s0,31(s4) - 6896: 08090003 lb zero,128(s2) - 689a: 0100 addi s0,sp,128 - 689c: 0300 addi s0,sp,384 - 689e: fa04 fsw fs1,48(a2) - 68a0: 0301 addi t1,t1,0 - 68a2: 0900 addi s0,sp,144 - 68a4: 0000 unimp - 68a6: 0001 nop - 68a8: 01fa0403 lb s0,31(s4) - 68ac: 00090003 lb zero,0(s2) - 68b0: 0100 addi s0,sp,128 - 68b2: 0300 addi s0,sp,384 - 68b4: fa04 fsw fs1,48(a2) - 68b6: 0301 addi t1,t1,0 - 68b8: 0900 addi s0,sp,144 - 68ba: 0000 unimp - 68bc: 0001 nop - 68be: 01fa0403 lb s0,31(s4) - 68c2: 00090003 lb zero,0(s2) - 68c6: 0100 addi s0,sp,128 - 68c8: 0300 addi s0,sp,384 - 68ca: fa04 fsw fs1,48(a2) - 68cc: 0301 addi t1,t1,0 - 68ce: 0900 addi s0,sp,144 - 68d0: 0000 unimp - 68d2: 0001 nop - 68d4: 01fa0403 lb s0,31(s4) - 68d8: 00090003 lb zero,0(s2) - 68dc: 0100 addi s0,sp,128 - 68de: 0300 addi s0,sp,384 - 68e0: fa04 fsw fs1,48(a2) - 68e2: 0301 addi t1,t1,0 - 68e4: 0900 addi s0,sp,144 - 68e6: 0000 unimp - 68e8: 0001 nop - 68ea: 01fa0403 lb s0,31(s4) - 68ee: 00090003 lb zero,0(s2) - 68f2: 0100 addi s0,sp,128 - 68f4: 0300 addi s0,sp,384 - 68f6: fa04 fsw fs1,48(a2) - 68f8: 0301 addi t1,t1,0 - 68fa: 0900 addi s0,sp,144 - 68fc: 0000 unimp - 68fe: 0001 nop - 6900: 01fa0403 lb s0,31(s4) - 6904: 00090003 lb zero,0(s2) - 6908: 0100 addi s0,sp,128 - 690a: 0300 addi s0,sp,384 - 690c: fa04 fsw fs1,48(a2) - 690e: 0301 addi t1,t1,0 - 6910: 0900 addi s0,sp,144 - 6912: 0000 unimp - 6914: 0001 nop - 6916: 01fa0403 lb s0,31(s4) - 691a: 00090003 lb zero,0(s2) - 691e: 0100 addi s0,sp,128 - 6920: 0300 addi s0,sp,384 - 6922: fa04 fsw fs1,48(a2) - 6924: 0301 addi t1,t1,0 - 6926: 0900 addi s0,sp,144 - 6928: 0008 0x8 - 692a: 0001 nop - 692c: 01fa0403 lb s0,31(s4) - 6930: 00090003 lb zero,0(s2) - 6934: 0100 addi s0,sp,128 - 6936: 0300 addi s0,sp,384 - 6938: 8704 0x8704 - 693a: 0302 c.slli64 t1 - 693c: 0900 addi s0,sp,144 - 693e: 0004 0x4 - 6940: 0001 nop - 6942: 02870403 lb s0,40(a4) - 6946: 1c090003 lb zero,448(s2) - 694a: 0100 addi s0,sp,128 - 694c: 0300 addi s0,sp,384 - 694e: 8704 0x8704 - 6950: 0302 c.slli64 t1 - 6952: 0900 addi s0,sp,144 - 6954: 0000 unimp - 6956: 0001 nop - 6958: 02880403 lb s0,40(a6) - 695c: 04090003 lb zero,64(s2) - 6960: 0100 addi s0,sp,128 - 6962: 0300 addi s0,sp,384 - 6964: 8804 0x8804 - 6966: 0302 c.slli64 t1 - 6968: 0900 addi s0,sp,144 - 696a: 000c 0xc - 696c: 0001 nop - 696e: 02880403 lb s0,40(a6) - 6972: 00090003 lb zero,0(s2) - 6976: 0100 addi s0,sp,128 - 6978: 0300 addi s0,sp,384 - 697a: 8804 0x8804 - 697c: 0302 c.slli64 t1 - 697e: 0900 addi s0,sp,144 - 6980: 0000 unimp - 6982: 0001 nop - 6984: 02880403 lb s0,40(a6) - 6988: 00090003 lb zero,0(s2) - 698c: 0100 addi s0,sp,128 - 698e: 0300 addi s0,sp,384 - 6990: 8804 0x8804 - 6992: 0302 c.slli64 t1 - 6994: 0900 addi s0,sp,144 - 6996: 0010 0x10 - 6998: 0001 nop - 699a: 02880403 lb s0,40(a6) - 699e: 00090003 lb zero,0(s2) - 69a2: 0100 addi s0,sp,128 - 69a4: 0300 addi s0,sp,384 - 69a6: 9704 0x9704 - 69a8: 0302 c.slli64 t1 - 69aa: 0900 addi s0,sp,144 - 69ac: 000c 0xc - 69ae: 0001 nop - 69b0: 02970403 lb s0,41(a4) + 685e: 0300 addi s0,sp,384 + 6860: fa04 fsw fs1,48(a2) + 6862: 0301 addi t1,t1,0 + 6864: 0900 addi s0,sp,144 + 6866: 0000 unimp + 6868: 0001 nop + 686a: 01fa0403 lb s0,31(s4) + 686e: 00090003 lb zero,0(s2) + 6872: 0100 addi s0,sp,128 + 6874: 0300 addi s0,sp,384 + 6876: fa04 fsw fs1,48(a2) + 6878: 0301 addi t1,t1,0 + 687a: 0900 addi s0,sp,144 + 687c: 0000 unimp + 687e: 0001 nop + 6880: 01fa0403 lb s0,31(s4) + 6884: 00090003 lb zero,0(s2) + 6888: 0100 addi s0,sp,128 + 688a: 0300 addi s0,sp,384 + 688c: fa04 fsw fs1,48(a2) + 688e: 0301 addi t1,t1,0 + 6890: 0900 addi s0,sp,144 + 6892: 0000 unimp + 6894: 0001 nop + 6896: 01fa0403 lb s0,31(s4) + 689a: 00090003 lb zero,0(s2) + 689e: 0100 addi s0,sp,128 + 68a0: 0300 addi s0,sp,384 + 68a2: fa04 fsw fs1,48(a2) + 68a4: 0301 addi t1,t1,0 + 68a6: 0900 addi s0,sp,144 + 68a8: 0000 unimp + 68aa: 0001 nop + 68ac: 01fa0403 lb s0,31(s4) + 68b0: 00090003 lb zero,0(s2) + 68b4: 0100 addi s0,sp,128 + 68b6: 0300 addi s0,sp,384 + 68b8: fa04 fsw fs1,48(a2) + 68ba: 0301 addi t1,t1,0 + 68bc: 0900 addi s0,sp,144 + 68be: 0000 unimp + 68c0: 0001 nop + 68c2: 01fa0403 lb s0,31(s4) + 68c6: 00090003 lb zero,0(s2) + 68ca: 0100 addi s0,sp,128 + 68cc: 0300 addi s0,sp,384 + 68ce: fa04 fsw fs1,48(a2) + 68d0: 0301 addi t1,t1,0 + 68d2: 0900 addi s0,sp,144 + 68d4: 0008 0x8 + 68d6: 0001 nop + 68d8: 01fa0403 lb s0,31(s4) + 68dc: 00090003 lb zero,0(s2) + 68e0: 0100 addi s0,sp,128 + 68e2: 0300 addi s0,sp,384 + 68e4: 8704 0x8704 + 68e6: 0302 c.slli64 t1 + 68e8: 0900 addi s0,sp,144 + 68ea: 0004 0x4 + 68ec: 0001 nop + 68ee: 02870403 lb s0,40(a4) + 68f2: 1c090003 lb zero,448(s2) + 68f6: 0100 addi s0,sp,128 + 68f8: 0300 addi s0,sp,384 + 68fa: 8704 0x8704 + 68fc: 0302 c.slli64 t1 + 68fe: 0900 addi s0,sp,144 + 6900: 0000 unimp + 6902: 0001 nop + 6904: 02880403 lb s0,40(a6) + 6908: 04090003 lb zero,64(s2) + 690c: 0100 addi s0,sp,128 + 690e: 0300 addi s0,sp,384 + 6910: 8804 0x8804 + 6912: 0302 c.slli64 t1 + 6914: 0900 addi s0,sp,144 + 6916: 000c 0xc + 6918: 0001 nop + 691a: 02880403 lb s0,40(a6) + 691e: 00090003 lb zero,0(s2) + 6922: 0100 addi s0,sp,128 + 6924: 0300 addi s0,sp,384 + 6926: 8804 0x8804 + 6928: 0302 c.slli64 t1 + 692a: 0900 addi s0,sp,144 + 692c: 0000 unimp + 692e: 0001 nop + 6930: 02880403 lb s0,40(a6) + 6934: 00090003 lb zero,0(s2) + 6938: 0100 addi s0,sp,128 + 693a: 0300 addi s0,sp,384 + 693c: 8804 0x8804 + 693e: 0302 c.slli64 t1 + 6940: 0900 addi s0,sp,144 + 6942: 0010 0x10 + 6944: 0001 nop + 6946: 02880403 lb s0,40(a6) + 694a: 00090003 lb zero,0(s2) + 694e: 0100 addi s0,sp,128 + 6950: 0300 addi s0,sp,384 + 6952: 9704 0x9704 + 6954: 0302 c.slli64 t1 + 6956: 0900 addi s0,sp,144 + 6958: 000c 0xc + 695a: 0001 nop + 695c: 02970403 lb s0,41(a4) + 6960: 00090003 lb zero,0(s2) + 6964: 0100 addi s0,sp,128 + 6966: 0300 addi s0,sp,384 + 6968: 9704 0x9704 + 696a: 0302 c.slli64 t1 + 696c: 0900 addi s0,sp,144 + 696e: 0000 unimp + 6970: 0001 nop + 6972: 02970403 lb s0,41(a4) + 6976: 00090003 lb zero,0(s2) + 697a: 0100 addi s0,sp,128 + 697c: 0300 addi s0,sp,384 + 697e: 9704 0x9704 + 6980: 0302 c.slli64 t1 + 6982: 0900 addi s0,sp,144 + 6984: 0010 0x10 + 6986: 0001 nop + 6988: 02970403 lb s0,41(a4) + 698c: 00090003 lb zero,0(s2) + 6990: 0100 addi s0,sp,128 + 6992: 0200 addi s0,sp,256 + 6994: 0f04 addi s1,sp,912 + 6996: 04090003 lb zero,64(s2) + 699a: 0100 addi s0,sp,128 + 699c: 0200 addi s0,sp,256 + 699e: 4d04 lw s1,24(a0) + 69a0: 10090003 lb zero,256(s2) + 69a4: 0100 addi s0,sp,128 + 69a6: 0200 addi s0,sp,256 + 69a8: 4d04 lw s1,24(a0) + 69aa: 04090003 lb zero,64(s2) + 69ae: 0100 addi s0,sp,128 + 69b0: 0200 addi s0,sp,256 + 69b2: 4d04 lw s1,24(a0) 69b4: 00090003 lb zero,0(s2) 69b8: 0100 addi s0,sp,128 - 69ba: 0300 addi s0,sp,384 - 69bc: 9704 0x9704 - 69be: 0302 c.slli64 t1 - 69c0: 0900 addi s0,sp,144 - 69c2: 0000 unimp - 69c4: 0001 nop - 69c6: 02970403 lb s0,41(a4) - 69ca: 00090003 lb zero,0(s2) - 69ce: 0100 addi s0,sp,128 - 69d0: 0300 addi s0,sp,384 - 69d2: 9704 0x9704 - 69d4: 0302 c.slli64 t1 - 69d6: 0900 addi s0,sp,144 - 69d8: 0010 0x10 - 69da: 0001 nop - 69dc: 02970403 lb s0,41(a4) - 69e0: 00090003 lb zero,0(s2) - 69e4: 0100 addi s0,sp,128 - 69e6: 0200 addi s0,sp,256 - 69e8: 0f04 addi s1,sp,912 - 69ea: 04090003 lb zero,64(s2) - 69ee: 0100 addi s0,sp,128 - 69f0: 0200 addi s0,sp,256 - 69f2: 4d04 lw s1,24(a0) - 69f4: 10090003 lb zero,256(s2) - 69f8: 0100 addi s0,sp,128 - 69fa: 0200 addi s0,sp,256 - 69fc: 4d04 lw s1,24(a0) - 69fe: 04090003 lb zero,64(s2) - 6a02: 0100 addi s0,sp,128 - 6a04: 0200 addi s0,sp,256 - 6a06: 4d04 lw s1,24(a0) - 6a08: 00090003 lb zero,0(s2) - 6a0c: 0100 addi s0,sp,128 - 6a0e: 0200 addi s0,sp,256 - 6a10: 4f04 lw s1,24(a4) - 6a12: 04090003 lb zero,64(s2) - 6a16: 0100 addi s0,sp,128 - 6a18: 0200 addi s0,sp,256 - 6a1a: 6604 flw fs1,8(a2) - 6a1c: 1c090003 lb zero,448(s2) - 6a20: 0100 addi s0,sp,128 - 6a22: 0200 addi s0,sp,256 - 6a24: 6604 flw fs1,8(a2) - 6a26: 00090003 lb zero,0(s2) - 6a2a: 0100 addi s0,sp,128 - 6a2c: 0200 addi s0,sp,256 - 6a2e: 6604 flw fs1,8(a2) - 6a30: 00090003 lb zero,0(s2) - 6a34: 0100 addi s0,sp,128 - 6a36: 0200 addi s0,sp,256 - 6a38: 6604 flw fs1,8(a2) - 6a3a: 00090003 lb zero,0(s2) - 6a3e: 0100 addi s0,sp,128 - 6a40: 0200 addi s0,sp,256 - 6a42: 6604 flw fs1,8(a2) - 6a44: 10090003 lb zero,256(s2) - 6a48: 0100 addi s0,sp,128 - 6a4a: 0200 addi s0,sp,256 - 6a4c: 5204 lw s1,32(a2) - 6a4e: 08090003 lb zero,128(s2) - 6a52: 0100 addi s0,sp,128 - 6a54: 0200 addi s0,sp,256 - 6a56: 5204 lw s1,32(a2) - 6a58: 00090003 lb zero,0(s2) - 6a5c: 0100 addi s0,sp,128 - 6a5e: 0200 addi s0,sp,256 - 6a60: 5204 lw s1,32(a2) - 6a62: 04090003 lb zero,64(s2) - 6a66: 0100 addi s0,sp,128 - 6a68: 0200 addi s0,sp,256 - 6a6a: 5b04 lw s1,48(a4) - 6a6c: 04090003 lb zero,64(s2) - 6a70: 0100 addi s0,sp,128 - 6a72: 0200 addi s0,sp,256 - 6a74: 5b04 lw s1,48(a4) - 6a76: 00090003 lb zero,0(s2) - 6a7a: 0100 addi s0,sp,128 - 6a7c: 0200 addi s0,sp,256 - 6a7e: 5b04 lw s1,48(a4) - 6a80: 00090003 lb zero,0(s2) - 6a84: 0100 addi s0,sp,128 - 6a86: 0200 addi s0,sp,256 - 6a88: 5b04 lw s1,48(a4) - 6a8a: 00090003 lb zero,0(s2) - 6a8e: 0100 addi s0,sp,128 - 6a90: 0200 addi s0,sp,256 - 6a92: 5b04 lw s1,48(a4) - 6a94: 10090003 lb zero,256(s2) - 6a98: 0100 addi s0,sp,128 - 6a9a: 0200 addi s0,sp,256 - 6a9c: 5b04 lw s1,48(a4) - 6a9e: 00090003 lb zero,0(s2) - 6aa2: 0100 addi s0,sp,128 - 6aa4: 0200 addi s0,sp,256 - 6aa6: 5b04 lw s1,48(a4) - 6aa8: 00090003 lb zero,0(s2) - 6aac: 0100 addi s0,sp,128 - 6aae: 0200 addi s0,sp,256 - 6ab0: 5b04 lw s1,48(a4) - 6ab2: 00090003 lb zero,0(s2) - 6ab6: 0100 addi s0,sp,128 - 6ab8: 0200 addi s0,sp,256 - 6aba: 5b04 lw s1,48(a4) - 6abc: 14090003 lb zero,320(s2) - 6ac0: 0100 addi s0,sp,128 - 6ac2: 0200 addi s0,sp,256 - 6ac4: 5b04 lw s1,48(a4) - 6ac6: 00090003 lb zero,0(s2) - 6aca: 0100 addi s0,sp,128 - 6acc: 0200 addi s0,sp,256 - 6ace: 5b04 lw s1,48(a4) - 6ad0: 04090003 lb zero,64(s2) - 6ad4: 0100 addi s0,sp,128 - 6ad6: 0200 addi s0,sp,256 - 6ad8: 5b04 lw s1,48(a4) - 6ada: 00090003 lb zero,0(s2) - 6ade: 0100 addi s0,sp,128 - 6ae0: 0200 addi s0,sp,256 - 6ae2: 5b04 lw s1,48(a4) - 6ae4: 1c090003 lb zero,448(s2) - 6ae8: 0100 addi s0,sp,128 - 6aea: 0200 addi s0,sp,256 - 6aec: 5b04 lw s1,48(a4) - 6aee: 00090003 lb zero,0(s2) - 6af2: 0100 addi s0,sp,128 - 6af4: 0200 addi s0,sp,256 - 6af6: 5c04 lw s1,56(s0) - 6af8: 08090003 lb zero,128(s2) - 6afc: 0100 addi s0,sp,128 - 6afe: 0c090003 lb zero,192(s2) - 6b02: 0100 addi s0,sp,128 - 6b04: 08090003 lb zero,128(s2) - 6b08: 0100 addi s0,sp,128 - 6b0a: 0200 addi s0,sp,256 - 6b0c: 5004 lw s1,32(s0) - 6b0e: 14090003 lb zero,320(s2) - 6b12: 0100 addi s0,sp,128 - 6b14: 0200 addi s0,sp,256 - 6b16: 7104 flw fs1,32(a0) - 6b18: 0c090003 lb zero,192(s2) - 6b1c: 0100 addi s0,sp,128 - 6b1e: 0200 addi s0,sp,256 - 6b20: 7104 flw fs1,32(a0) - 6b22: 00090003 lb zero,0(s2) - 6b26: 0100 addi s0,sp,128 - 6b28: 0200 addi s0,sp,256 - 6b2a: 7104 flw fs1,32(a0) - 6b2c: 00090003 lb zero,0(s2) - 6b30: 0100 addi s0,sp,128 - 6b32: 0200 addi s0,sp,256 - 6b34: 7104 flw fs1,32(a0) - 6b36: 00090003 lb zero,0(s2) - 6b3a: 0100 addi s0,sp,128 - 6b3c: 0200 addi s0,sp,256 - 6b3e: 7104 flw fs1,32(a0) - 6b40: 10090003 lb zero,256(s2) - 6b44: 0100 addi s0,sp,128 - 6b46: 0200 addi s0,sp,256 - 6b48: 6a04 flw fs1,16(a2) - 6b4a: 08090003 lb zero,128(s2) - 6b4e: 0100 addi s0,sp,128 - 6b50: 0200 addi s0,sp,256 - 6b52: 6a04 flw fs1,16(a2) - 6b54: 10090003 lb zero,256(s2) - 6b58: 0100 addi s0,sp,128 - 6b5a: 0200 addi s0,sp,256 - 6b5c: 7404 flw fs1,40(s0) - 6b5e: 0c090003 lb zero,192(s2) - 6b62: 0100 addi s0,sp,128 - 6b64: 0200 addi s0,sp,256 - 6b66: 7404 flw fs1,40(s0) - 6b68: 00090003 lb zero,0(s2) - 6b6c: 0100 addi s0,sp,128 - 6b6e: 0200 addi s0,sp,256 - 6b70: 7404 flw fs1,40(s0) - 6b72: 00090003 lb zero,0(s2) - 6b76: 0100 addi s0,sp,128 - 6b78: 0200 addi s0,sp,256 - 6b7a: 7404 flw fs1,40(s0) - 6b7c: 00090003 lb zero,0(s2) - 6b80: 0100 addi s0,sp,128 - 6b82: 0200 addi s0,sp,256 - 6b84: 7404 flw fs1,40(s0) - 6b86: 00090003 lb zero,0(s2) - 6b8a: 0100 addi s0,sp,128 - 6b8c: 0200 addi s0,sp,256 - 6b8e: 7404 flw fs1,40(s0) - 6b90: 00090003 lb zero,0(s2) - 6b94: 0100 addi s0,sp,128 - 6b96: 0200 addi s0,sp,256 - 6b98: 7404 flw fs1,40(s0) - 6b9a: 00090003 lb zero,0(s2) - 6b9e: 0100 addi s0,sp,128 - 6ba0: 0200 addi s0,sp,256 - 6ba2: 7404 flw fs1,40(s0) - 6ba4: 08090003 lb zero,128(s2) - 6ba8: 0100 addi s0,sp,128 - 6baa: 0200 addi s0,sp,256 - 6bac: 7404 flw fs1,40(s0) - 6bae: 00090003 lb zero,0(s2) - 6bb2: 0100 addi s0,sp,128 - 6bb4: 0200 addi s0,sp,256 - 6bb6: 7404 flw fs1,40(s0) - 6bb8: 00090003 lb zero,0(s2) - 6bbc: 0100 addi s0,sp,128 - 6bbe: 0200 addi s0,sp,256 - 6bc0: 7604 flw fs1,40(a2) - 6bc2: 08090003 lb zero,128(s2) - 6bc6: 0100 addi s0,sp,128 - 6bc8: 0200 addi s0,sp,256 - 6bca: 7904 flw fs1,48(a0) - 6bcc: 10090003 lb zero,256(s2) - 6bd0: 0100 addi s0,sp,128 - 6bd2: 0306 slli t1,t1,0x1 - 6bd4: 0900 addi s0,sp,144 - 6bd6: 000c 0xc - 6bd8: 0001 nop - 6bda: 0402 c.slli64 s0 - 6bdc: 067e slli a2,a2,0x1f - 6bde: 08090003 lb zero,128(s2) - 6be2: 0100 addi s0,sp,128 - 6be4: 0200 addi s0,sp,256 - 6be6: 7e04 flw fs1,56(a2) - 6be8: 14090003 lb zero,320(s2) + 69ba: 0200 addi s0,sp,256 + 69bc: 4f04 lw s1,24(a4) + 69be: 04090003 lb zero,64(s2) + 69c2: 0100 addi s0,sp,128 + 69c4: 0200 addi s0,sp,256 + 69c6: 6604 flw fs1,8(a2) + 69c8: 1c090003 lb zero,448(s2) + 69cc: 0100 addi s0,sp,128 + 69ce: 0200 addi s0,sp,256 + 69d0: 6604 flw fs1,8(a2) + 69d2: 00090003 lb zero,0(s2) + 69d6: 0100 addi s0,sp,128 + 69d8: 0200 addi s0,sp,256 + 69da: 6604 flw fs1,8(a2) + 69dc: 00090003 lb zero,0(s2) + 69e0: 0100 addi s0,sp,128 + 69e2: 0200 addi s0,sp,256 + 69e4: 6604 flw fs1,8(a2) + 69e6: 00090003 lb zero,0(s2) + 69ea: 0100 addi s0,sp,128 + 69ec: 0200 addi s0,sp,256 + 69ee: 6604 flw fs1,8(a2) + 69f0: 10090003 lb zero,256(s2) + 69f4: 0100 addi s0,sp,128 + 69f6: 0200 addi s0,sp,256 + 69f8: 5204 lw s1,32(a2) + 69fa: 08090003 lb zero,128(s2) + 69fe: 0100 addi s0,sp,128 + 6a00: 0200 addi s0,sp,256 + 6a02: 5204 lw s1,32(a2) + 6a04: 00090003 lb zero,0(s2) + 6a08: 0100 addi s0,sp,128 + 6a0a: 0200 addi s0,sp,256 + 6a0c: 5204 lw s1,32(a2) + 6a0e: 04090003 lb zero,64(s2) + 6a12: 0100 addi s0,sp,128 + 6a14: 0200 addi s0,sp,256 + 6a16: 5b04 lw s1,48(a4) + 6a18: 04090003 lb zero,64(s2) + 6a1c: 0100 addi s0,sp,128 + 6a1e: 0200 addi s0,sp,256 + 6a20: 5b04 lw s1,48(a4) + 6a22: 00090003 lb zero,0(s2) + 6a26: 0100 addi s0,sp,128 + 6a28: 0200 addi s0,sp,256 + 6a2a: 5b04 lw s1,48(a4) + 6a2c: 00090003 lb zero,0(s2) + 6a30: 0100 addi s0,sp,128 + 6a32: 0200 addi s0,sp,256 + 6a34: 5b04 lw s1,48(a4) + 6a36: 00090003 lb zero,0(s2) + 6a3a: 0100 addi s0,sp,128 + 6a3c: 0200 addi s0,sp,256 + 6a3e: 5b04 lw s1,48(a4) + 6a40: 10090003 lb zero,256(s2) + 6a44: 0100 addi s0,sp,128 + 6a46: 0200 addi s0,sp,256 + 6a48: 5b04 lw s1,48(a4) + 6a4a: 00090003 lb zero,0(s2) + 6a4e: 0100 addi s0,sp,128 + 6a50: 0200 addi s0,sp,256 + 6a52: 5b04 lw s1,48(a4) + 6a54: 00090003 lb zero,0(s2) + 6a58: 0100 addi s0,sp,128 + 6a5a: 0200 addi s0,sp,256 + 6a5c: 5b04 lw s1,48(a4) + 6a5e: 00090003 lb zero,0(s2) + 6a62: 0100 addi s0,sp,128 + 6a64: 0200 addi s0,sp,256 + 6a66: 5b04 lw s1,48(a4) + 6a68: 14090003 lb zero,320(s2) + 6a6c: 0100 addi s0,sp,128 + 6a6e: 0200 addi s0,sp,256 + 6a70: 5b04 lw s1,48(a4) + 6a72: 00090003 lb zero,0(s2) + 6a76: 0100 addi s0,sp,128 + 6a78: 0200 addi s0,sp,256 + 6a7a: 5b04 lw s1,48(a4) + 6a7c: 04090003 lb zero,64(s2) + 6a80: 0100 addi s0,sp,128 + 6a82: 0200 addi s0,sp,256 + 6a84: 5b04 lw s1,48(a4) + 6a86: 00090003 lb zero,0(s2) + 6a8a: 0100 addi s0,sp,128 + 6a8c: 0200 addi s0,sp,256 + 6a8e: 5b04 lw s1,48(a4) + 6a90: 1c090003 lb zero,448(s2) + 6a94: 0100 addi s0,sp,128 + 6a96: 0200 addi s0,sp,256 + 6a98: 5b04 lw s1,48(a4) + 6a9a: 00090003 lb zero,0(s2) + 6a9e: 0100 addi s0,sp,128 + 6aa0: 0200 addi s0,sp,256 + 6aa2: 5c04 lw s1,56(s0) + 6aa4: 08090003 lb zero,128(s2) + 6aa8: 0100 addi s0,sp,128 + 6aaa: 0c090003 lb zero,192(s2) + 6aae: 0100 addi s0,sp,128 + 6ab0: 08090003 lb zero,128(s2) + 6ab4: 0100 addi s0,sp,128 + 6ab6: 0200 addi s0,sp,256 + 6ab8: 5004 lw s1,32(s0) + 6aba: 14090003 lb zero,320(s2) + 6abe: 0100 addi s0,sp,128 + 6ac0: 0200 addi s0,sp,256 + 6ac2: 7104 flw fs1,32(a0) + 6ac4: 0c090003 lb zero,192(s2) + 6ac8: 0100 addi s0,sp,128 + 6aca: 0200 addi s0,sp,256 + 6acc: 7104 flw fs1,32(a0) + 6ace: 00090003 lb zero,0(s2) + 6ad2: 0100 addi s0,sp,128 + 6ad4: 0200 addi s0,sp,256 + 6ad6: 7104 flw fs1,32(a0) + 6ad8: 00090003 lb zero,0(s2) + 6adc: 0100 addi s0,sp,128 + 6ade: 0200 addi s0,sp,256 + 6ae0: 7104 flw fs1,32(a0) + 6ae2: 00090003 lb zero,0(s2) + 6ae6: 0100 addi s0,sp,128 + 6ae8: 0200 addi s0,sp,256 + 6aea: 7104 flw fs1,32(a0) + 6aec: 10090003 lb zero,256(s2) + 6af0: 0100 addi s0,sp,128 + 6af2: 0200 addi s0,sp,256 + 6af4: 6a04 flw fs1,16(a2) + 6af6: 08090003 lb zero,128(s2) + 6afa: 0100 addi s0,sp,128 + 6afc: 0200 addi s0,sp,256 + 6afe: 6a04 flw fs1,16(a2) + 6b00: 10090003 lb zero,256(s2) + 6b04: 0100 addi s0,sp,128 + 6b06: 0200 addi s0,sp,256 + 6b08: 7404 flw fs1,40(s0) + 6b0a: 0c090003 lb zero,192(s2) + 6b0e: 0100 addi s0,sp,128 + 6b10: 0200 addi s0,sp,256 + 6b12: 7404 flw fs1,40(s0) + 6b14: 00090003 lb zero,0(s2) + 6b18: 0100 addi s0,sp,128 + 6b1a: 0200 addi s0,sp,256 + 6b1c: 7404 flw fs1,40(s0) + 6b1e: 00090003 lb zero,0(s2) + 6b22: 0100 addi s0,sp,128 + 6b24: 0200 addi s0,sp,256 + 6b26: 7404 flw fs1,40(s0) + 6b28: 00090003 lb zero,0(s2) + 6b2c: 0100 addi s0,sp,128 + 6b2e: 0200 addi s0,sp,256 + 6b30: 7404 flw fs1,40(s0) + 6b32: 00090003 lb zero,0(s2) + 6b36: 0100 addi s0,sp,128 + 6b38: 0200 addi s0,sp,256 + 6b3a: 7404 flw fs1,40(s0) + 6b3c: 00090003 lb zero,0(s2) + 6b40: 0100 addi s0,sp,128 + 6b42: 0200 addi s0,sp,256 + 6b44: 7404 flw fs1,40(s0) + 6b46: 00090003 lb zero,0(s2) + 6b4a: 0100 addi s0,sp,128 + 6b4c: 0200 addi s0,sp,256 + 6b4e: 7404 flw fs1,40(s0) + 6b50: 08090003 lb zero,128(s2) + 6b54: 0100 addi s0,sp,128 + 6b56: 0200 addi s0,sp,256 + 6b58: 7404 flw fs1,40(s0) + 6b5a: 00090003 lb zero,0(s2) + 6b5e: 0100 addi s0,sp,128 + 6b60: 0200 addi s0,sp,256 + 6b62: 7404 flw fs1,40(s0) + 6b64: 00090003 lb zero,0(s2) + 6b68: 0100 addi s0,sp,128 + 6b6a: 0200 addi s0,sp,256 + 6b6c: 7604 flw fs1,40(a2) + 6b6e: 08090003 lb zero,128(s2) + 6b72: 0100 addi s0,sp,128 + 6b74: 0200 addi s0,sp,256 + 6b76: 7904 flw fs1,48(a0) + 6b78: 10090003 lb zero,256(s2) + 6b7c: 0100 addi s0,sp,128 + 6b7e: 0306 slli t1,t1,0x1 + 6b80: 0900 addi s0,sp,144 + 6b82: 000c 0xc + 6b84: 0001 nop + 6b86: 0402 c.slli64 s0 + 6b88: 067e slli a2,a2,0x1f + 6b8a: 08090003 lb zero,128(s2) + 6b8e: 0100 addi s0,sp,128 + 6b90: 0200 addi s0,sp,256 + 6b92: 7e04 flw fs1,56(a2) + 6b94: 14090003 lb zero,320(s2) + 6b98: 0100 addi s0,sp,128 + 6b9a: 0200 addi s0,sp,256 + 6b9c: 7e04 flw fs1,56(a2) + 6b9e: 00090003 lb zero,0(s2) + 6ba2: 0100 addi s0,sp,128 + 6ba4: 0200 addi s0,sp,256 + 6ba6: 7804 flw fs1,48(s0) + 6ba8: 1c090003 lb zero,448(s2) + 6bac: 0100 addi s0,sp,128 + 6bae: 0200 addi s0,sp,256 + 6bb0: 7804 flw fs1,48(s0) + 6bb2: 14090003 lb zero,320(s2) + 6bb6: 0100 addi s0,sp,128 + 6bb8: 0200 addi s0,sp,256 + 6bba: 7b04 flw fs1,48(a4) + 6bbc: 0306 slli t1,t1,0x1 + 6bbe: 0900 addi s0,sp,144 + 6bc0: 0004 0x4 + 6bc2: 0001 nop + 6bc4: 0402 c.slli64 s0 + 6bc6: 0003067b 0x3067b + 6bca: 2409 jal 6dcc <_start-0x7fff9234> + 6bcc: 0100 addi s0,sp,128 + 6bce: 0200 addi s0,sp,256 + 6bd0: 7b04 flw fs1,48(a4) + 6bd2: 08090003 lb zero,128(s2) + 6bd6: 0100 addi s0,sp,128 + 6bd8: 0200 addi s0,sp,256 + 6bda: 7f04 flw fs1,56(a4) + 6bdc: 08090003 lb zero,128(s2) + 6be0: 0100 addi s0,sp,128 + 6be2: 0300 addi s0,sp,384 + 6be4: 8204 0x8204 + 6be6: 0601 addi a2,a2,0 + 6be8: 08090003 lb zero,128(s2) 6bec: 0100 addi s0,sp,128 - 6bee: 0200 addi s0,sp,256 - 6bf0: 7e04 flw fs1,56(a2) - 6bf2: 00090003 lb zero,0(s2) - 6bf6: 0100 addi s0,sp,128 - 6bf8: 0200 addi s0,sp,256 - 6bfa: 7804 flw fs1,48(s0) - 6bfc: 1c090003 lb zero,448(s2) - 6c00: 0100 addi s0,sp,128 - 6c02: 0200 addi s0,sp,256 - 6c04: 7804 flw fs1,48(s0) - 6c06: 14090003 lb zero,320(s2) - 6c0a: 0100 addi s0,sp,128 - 6c0c: 0200 addi s0,sp,256 - 6c0e: 7b04 flw fs1,48(a4) - 6c10: 0306 slli t1,t1,0x1 - 6c12: 0900 addi s0,sp,144 - 6c14: 0004 0x4 - 6c16: 0001 nop - 6c18: 0402 c.slli64 s0 - 6c1a: 0003067b 0x3067b - 6c1e: 2409 jal 6e20 <_start-0x7fff91e0> - 6c20: 0100 addi s0,sp,128 - 6c22: 0200 addi s0,sp,256 - 6c24: 7b04 flw fs1,48(a4) - 6c26: 08090003 lb zero,128(s2) - 6c2a: 0100 addi s0,sp,128 - 6c2c: 0200 addi s0,sp,256 - 6c2e: 7f04 flw fs1,56(a4) - 6c30: 08090003 lb zero,128(s2) - 6c34: 0100 addi s0,sp,128 - 6c36: 0300 addi s0,sp,384 - 6c38: 8204 0x8204 - 6c3a: 0601 addi a2,a2,0 - 6c3c: 08090003 lb zero,128(s2) - 6c40: 0100 addi s0,sp,128 - 6c42: 0300 addi s0,sp,384 - 6c44: 8204 0x8204 - 6c46: 0601 addi a2,a2,0 - 6c48: 18090003 lb zero,384(s2) - 6c4c: 0100 addi s0,sp,128 - 6c4e: 0300 addi s0,sp,384 - 6c50: 8404 0x8404 - 6c52: 0601 addi a2,a2,0 - 6c54: 08090003 lb zero,128(s2) - 6c58: 0100 addi s0,sp,128 - 6c5a: 0300 addi s0,sp,384 - 6c5c: 8104 0x8104 + 6bee: 0300 addi s0,sp,384 + 6bf0: 8204 0x8204 + 6bf2: 0601 addi a2,a2,0 + 6bf4: 18090003 lb zero,384(s2) + 6bf8: 0100 addi s0,sp,128 + 6bfa: 0300 addi s0,sp,384 + 6bfc: 8404 0x8404 + 6bfe: 0601 addi a2,a2,0 + 6c00: 08090003 lb zero,128(s2) + 6c04: 0100 addi s0,sp,128 + 6c06: 0300 addi s0,sp,384 + 6c08: 8104 0x8104 + 6c0a: 0601 addi a2,a2,0 + 6c0c: 08090003 lb zero,128(s2) + 6c10: 0100 addi s0,sp,128 + 6c12: 0300 addi s0,sp,384 + 6c14: 8104 0x8104 + 6c16: 0301 addi t1,t1,0 + 6c18: 0900 addi s0,sp,144 + 6c1a: 0020 addi s0,sp,8 + 6c1c: 0001 nop + 6c1e: 01850403 lb s0,24(a0) # ffffc018 <__BSS_END__+0x7ffe53dc> + 6c22: 08090003 lb zero,128(s2) + 6c26: 0100 addi s0,sp,128 + 6c28: 0300 addi s0,sp,384 + 6c2a: 8504 0x8504 + 6c2c: 0301 addi t1,t1,0 + 6c2e: 0900 addi s0,sp,144 + 6c30: 000c 0xc + 6c32: 0001 nop + 6c34: 01840403 lb s0,24(s0) # 18018 <_start-0x7ffe7fe8> + 6c38: 04090003 lb zero,64(s2) + 6c3c: 0100 addi s0,sp,128 + 6c3e: 0300 addi s0,sp,384 + 6c40: 8604 0x8604 + 6c42: 0301 addi t1,t1,0 + 6c44: 0900 addi s0,sp,144 + 6c46: 0004 0x4 + 6c48: 0001 nop + 6c4a: 01860403 lb s0,24(a2) # b018 <_start-0x7fff4fe8> + 6c4e: 00090003 lb zero,0(s2) + 6c52: 0100 addi s0,sp,128 + 6c54: 0300 addi s0,sp,384 + 6c56: 8604 0x8604 + 6c58: 0301 addi t1,t1,0 + 6c5a: 0900 addi s0,sp,144 + 6c5c: 0000 unimp 6c5e: 0601 addi a2,a2,0 - 6c60: 08090003 lb zero,128(s2) + 6c60: 0c090003 lb zero,192(s2) 6c64: 0100 addi s0,sp,128 - 6c66: 0300 addi s0,sp,384 - 6c68: 8104 0x8104 - 6c6a: 0301 addi t1,t1,0 - 6c6c: 0900 addi s0,sp,144 - 6c6e: 0020 addi s0,sp,8 - 6c70: 0001 nop - 6c72: 01850403 lb s0,24(a0) # ffffc018 <__BSS_END__+0x7ffe53e8> - 6c76: 08090003 lb zero,128(s2) - 6c7a: 0100 addi s0,sp,128 - 6c7c: 0300 addi s0,sp,384 - 6c7e: 8504 0x8504 - 6c80: 0301 addi t1,t1,0 - 6c82: 0900 addi s0,sp,144 - 6c84: 000c 0xc - 6c86: 0001 nop - 6c88: 01840403 lb s0,24(s0) # 18018 <_start-0x7ffe7fe8> - 6c8c: 04090003 lb zero,64(s2) - 6c90: 0100 addi s0,sp,128 - 6c92: 0300 addi s0,sp,384 - 6c94: 8604 0x8604 - 6c96: 0301 addi t1,t1,0 - 6c98: 0900 addi s0,sp,144 - 6c9a: 0004 0x4 - 6c9c: 0001 nop - 6c9e: 01860403 lb s0,24(a2) # b018 <_start-0x7fff4fe8> - 6ca2: 00090003 lb zero,0(s2) - 6ca6: 0100 addi s0,sp,128 - 6ca8: 0300 addi s0,sp,384 - 6caa: 8604 0x8604 - 6cac: 0301 addi t1,t1,0 - 6cae: 0900 addi s0,sp,144 - 6cb0: 0000 unimp - 6cb2: 0601 addi a2,a2,0 - 6cb4: 0c090003 lb zero,192(s2) - 6cb8: 0100 addi s0,sp,128 - 6cba: 0306 slli t1,t1,0x1 - 6cbc: 0900 addi s0,sp,144 - 6cbe: 0004 0x4 - 6cc0: 0301 addi t1,t1,0 - 6cc2: 0900 addi s0,sp,144 - 6cc4: 0000 unimp - 6cc6: 0301 addi t1,t1,0 - 6cc8: 0900 addi s0,sp,144 - 6cca: 0000 unimp - 6ccc: 0301 addi t1,t1,0 - 6cce: 0900 addi s0,sp,144 - 6cd0: 0000 unimp - 6cd2: 0601 addi a2,a2,0 - 6cd4: 08097f03 0x8097f03 - 6cd8: 0100 addi s0,sp,128 - 6cda: 04090103 lb sp,64(s2) - 6cde: 0100 addi s0,sp,128 - 6ce0: 0306 slli t1,t1,0x1 - 6ce2: 0900 addi s0,sp,144 - 6ce4: 0010 0x10 - 6ce6: 0301 addi t1,t1,0 - 6ce8: 0900 addi s0,sp,144 - 6cea: 0000 unimp - 6cec: 0301 addi t1,t1,0 - 6cee: 0900 addi s0,sp,144 - 6cf0: 0000 unimp - 6cf2: 0301 addi t1,t1,0 - 6cf4: 0900 addi s0,sp,144 - 6cf6: 0000 unimp - 6cf8: 0301 addi t1,t1,0 - 6cfa: 0900 addi s0,sp,144 - 6cfc: 000c 0xc + 6c66: 0306 slli t1,t1,0x1 + 6c68: 0900 addi s0,sp,144 + 6c6a: 0004 0x4 + 6c6c: 0301 addi t1,t1,0 + 6c6e: 0900 addi s0,sp,144 + 6c70: 0000 unimp + 6c72: 0301 addi t1,t1,0 + 6c74: 0900 addi s0,sp,144 + 6c76: 0000 unimp + 6c78: 0301 addi t1,t1,0 + 6c7a: 0900 addi s0,sp,144 + 6c7c: 0000 unimp + 6c7e: 0601 addi a2,a2,0 + 6c80: 08097f03 0x8097f03 + 6c84: 0100 addi s0,sp,128 + 6c86: 04090103 lb sp,64(s2) + 6c8a: 0100 addi s0,sp,128 + 6c8c: 0306 slli t1,t1,0x1 + 6c8e: 0900 addi s0,sp,144 + 6c90: 0010 0x10 + 6c92: 0301 addi t1,t1,0 + 6c94: 0900 addi s0,sp,144 + 6c96: 0000 unimp + 6c98: 0301 addi t1,t1,0 + 6c9a: 0900 addi s0,sp,144 + 6c9c: 0000 unimp + 6c9e: 0301 addi t1,t1,0 + 6ca0: 0900 addi s0,sp,144 + 6ca2: 0000 unimp + 6ca4: 0301 addi t1,t1,0 + 6ca6: 0900 addi s0,sp,144 + 6ca8: 000c 0xc + 6caa: 0301 addi t1,t1,0 + 6cac: 0900 addi s0,sp,144 + 6cae: 000c 0xc + 6cb0: 0301 addi t1,t1,0 + 6cb2: 0900 addi s0,sp,144 + 6cb4: 0004 0x4 + 6cb6: 0301 addi t1,t1,0 + 6cb8: 0900 addi s0,sp,144 + 6cba: 0000 unimp + 6cbc: 0301 addi t1,t1,0 + 6cbe: 0900 addi s0,sp,144 + 6cc0: 0020 addi s0,sp,8 + 6cc2: 0301 addi t1,t1,0 + 6cc4: 0900 addi s0,sp,144 + 6cc6: 0000 unimp + 6cc8: 0301 addi t1,t1,0 + 6cca: 0900 addi s0,sp,144 + 6ccc: 0004 0x4 + 6cce: 0001 nop + 6cd0: 0402 c.slli64 s0 + 6cd2: 034e slli t1,t1,0x13 + 6cd4: 0900 addi s0,sp,144 + 6cd6: 0004 0x4 + 6cd8: 0001 nop + 6cda: 018c0403 lb s0,24(s8) + 6cde: 28090003 lb zero,640(s2) + 6ce2: 0100 addi s0,sp,128 + 6ce4: 0300 addi s0,sp,384 + 6ce6: 8e04 0x8e04 + 6ce8: 0301 addi t1,t1,0 + 6cea: 0900 addi s0,sp,144 + 6cec: 0010 0x10 + 6cee: 0001 nop + 6cf0: 018e0403 lb s0,24(t3) # 1a018 <_start-0x7ffe5fe8> + 6cf4: 00090003 lb zero,0(s2) + 6cf8: 0100 addi s0,sp,128 + 6cfa: 0300 addi s0,sp,384 + 6cfc: 9004 0x9004 6cfe: 0301 addi t1,t1,0 6d00: 0900 addi s0,sp,144 - 6d02: 000c 0xc - 6d04: 0301 addi t1,t1,0 - 6d06: 0900 addi s0,sp,144 - 6d08: 0004 0x4 - 6d0a: 0301 addi t1,t1,0 - 6d0c: 0900 addi s0,sp,144 - 6d0e: 0000 unimp - 6d10: 0301 addi t1,t1,0 - 6d12: 0900 addi s0,sp,144 - 6d14: 0020 addi s0,sp,8 - 6d16: 0301 addi t1,t1,0 - 6d18: 0900 addi s0,sp,144 - 6d1a: 0000 unimp - 6d1c: 0301 addi t1,t1,0 - 6d1e: 0900 addi s0,sp,144 - 6d20: 0004 0x4 - 6d22: 0001 nop - 6d24: 0402 c.slli64 s0 - 6d26: 034e slli t1,t1,0x13 - 6d28: 0900 addi s0,sp,144 - 6d2a: 0004 0x4 - 6d2c: 0001 nop - 6d2e: 018c0403 lb s0,24(s8) - 6d32: 28090003 lb zero,640(s2) - 6d36: 0100 addi s0,sp,128 - 6d38: 0300 addi s0,sp,384 - 6d3a: 8e04 0x8e04 - 6d3c: 0301 addi t1,t1,0 - 6d3e: 0900 addi s0,sp,144 - 6d40: 0010 0x10 - 6d42: 0001 nop - 6d44: 018e0403 lb s0,24(t3) # 1a018 <_start-0x7ffe5fe8> - 6d48: 00090003 lb zero,0(s2) - 6d4c: 0100 addi s0,sp,128 - 6d4e: 0300 addi s0,sp,384 - 6d50: 9004 0x9004 - 6d52: 0301 addi t1,t1,0 - 6d54: 0900 addi s0,sp,144 - 6d56: 0004 0x4 - 6d58: 0001 nop - 6d5a: 01900403 lb s0,25(zero) # 19 <_start-0x7fffffe7> - 6d5e: 00090003 lb zero,0(s2) - 6d62: 0100 addi s0,sp,128 - 6d64: 0300 addi s0,sp,384 - 6d66: d404 sw s1,40(s0) - 6d68: 00030603 lb a2,0(t1) - 6d6c: 0c09 addi s8,s8,2 - 6d6e: 0100 addi s0,sp,128 - 6d70: 0300 addi s0,sp,384 - 6d72: d404 sw s1,40(s0) - 6d74: 00030603 lb a2,0(t1) - 6d78: 0409 addi s0,s0,2 - 6d7a: 0100 addi s0,sp,128 - 6d7c: 0300 addi s0,sp,384 - 6d7e: d404 sw s1,40(s0) - 6d80: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 6d84: 0000 unimp - 6d86: 0001 nop - 6d88: 01910403 lb s0,25(sp) - 6d8c: 04090003 lb zero,64(s2) - 6d90: 0100 addi s0,sp,128 - 6d92: 0300 addi s0,sp,384 - 6d94: 9604 0x9604 - 6d96: 0301 addi t1,t1,0 - 6d98: 0900 addi s0,sp,144 - 6d9a: 0010 0x10 - 6d9c: 0001 nop - 6d9e: 01960403 lb s0,25(a2) - 6da2: 00090003 lb zero,0(s2) - 6da6: 0100 addi s0,sp,128 - 6da8: 0300 addi s0,sp,384 - 6daa: 9604 0x9604 - 6dac: 0301 addi t1,t1,0 - 6dae: 0900 addi s0,sp,144 - 6db0: 0010 0x10 - 6db2: 0001 nop - 6db4: 01970403 lb s0,25(a4) - 6db8: 04090003 lb zero,64(s2) - 6dbc: 0100 addi s0,sp,128 - 6dbe: 0300 addi s0,sp,384 - 6dc0: 9704 0x9704 - 6dc2: 0301 addi t1,t1,0 - 6dc4: 0900 addi s0,sp,144 - 6dc6: 0000 unimp - 6dc8: 0001 nop - 6dca: 01970403 lb s0,25(a4) - 6dce: 00090003 lb zero,0(s2) - 6dd2: 0100 addi s0,sp,128 - 6dd4: 0300 addi s0,sp,384 - 6dd6: 9704 0x9704 - 6dd8: 0301 addi t1,t1,0 - 6dda: 0900 addi s0,sp,144 - 6ddc: 0000 unimp - 6dde: 0001 nop - 6de0: 01970403 lb s0,25(a4) - 6de4: 00090003 lb zero,0(s2) - 6de8: 0100 addi s0,sp,128 - 6dea: 0300 addi s0,sp,384 - 6dec: 9704 0x9704 - 6dee: 0301 addi t1,t1,0 - 6df0: 0900 addi s0,sp,144 - 6df2: 0010 0x10 - 6df4: 0001 nop - 6df6: 01970403 lb s0,25(a4) - 6dfa: 00090003 lb zero,0(s2) - 6dfe: 0100 addi s0,sp,128 - 6e00: 0300 addi s0,sp,384 - 6e02: 9704 0x9704 - 6e04: 0301 addi t1,t1,0 - 6e06: 0900 addi s0,sp,144 - 6e08: 0000 unimp - 6e0a: 0001 nop - 6e0c: 01970403 lb s0,25(a4) - 6e10: 00090003 lb zero,0(s2) - 6e14: 0100 addi s0,sp,128 - 6e16: 0300 addi s0,sp,384 - 6e18: 9704 0x9704 - 6e1a: 0301 addi t1,t1,0 + 6d02: 0004 0x4 + 6d04: 0001 nop + 6d06: 01900403 lb s0,25(zero) # 19 <_start-0x7fffffe7> + 6d0a: 00090003 lb zero,0(s2) + 6d0e: 0100 addi s0,sp,128 + 6d10: 0300 addi s0,sp,384 + 6d12: d404 sw s1,40(s0) + 6d14: 00030603 lb a2,0(t1) + 6d18: 0c09 addi s8,s8,2 + 6d1a: 0100 addi s0,sp,128 + 6d1c: 0300 addi s0,sp,384 + 6d1e: d404 sw s1,40(s0) + 6d20: 00030603 lb a2,0(t1) + 6d24: 0409 addi s0,s0,2 + 6d26: 0100 addi s0,sp,128 + 6d28: 0300 addi s0,sp,384 + 6d2a: d404 sw s1,40(s0) + 6d2c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 6d30: 0000 unimp + 6d32: 0001 nop + 6d34: 01910403 lb s0,25(sp) + 6d38: 04090003 lb zero,64(s2) + 6d3c: 0100 addi s0,sp,128 + 6d3e: 0300 addi s0,sp,384 + 6d40: 9604 0x9604 + 6d42: 0301 addi t1,t1,0 + 6d44: 0900 addi s0,sp,144 + 6d46: 0010 0x10 + 6d48: 0001 nop + 6d4a: 01960403 lb s0,25(a2) + 6d4e: 00090003 lb zero,0(s2) + 6d52: 0100 addi s0,sp,128 + 6d54: 0300 addi s0,sp,384 + 6d56: 9604 0x9604 + 6d58: 0301 addi t1,t1,0 + 6d5a: 0900 addi s0,sp,144 + 6d5c: 0010 0x10 + 6d5e: 0001 nop + 6d60: 01970403 lb s0,25(a4) + 6d64: 04090003 lb zero,64(s2) + 6d68: 0100 addi s0,sp,128 + 6d6a: 0300 addi s0,sp,384 + 6d6c: 9704 0x9704 + 6d6e: 0301 addi t1,t1,0 + 6d70: 0900 addi s0,sp,144 + 6d72: 0000 unimp + 6d74: 0001 nop + 6d76: 01970403 lb s0,25(a4) + 6d7a: 00090003 lb zero,0(s2) + 6d7e: 0100 addi s0,sp,128 + 6d80: 0300 addi s0,sp,384 + 6d82: 9704 0x9704 + 6d84: 0301 addi t1,t1,0 + 6d86: 0900 addi s0,sp,144 + 6d88: 0000 unimp + 6d8a: 0001 nop + 6d8c: 01970403 lb s0,25(a4) + 6d90: 00090003 lb zero,0(s2) + 6d94: 0100 addi s0,sp,128 + 6d96: 0300 addi s0,sp,384 + 6d98: 9704 0x9704 + 6d9a: 0301 addi t1,t1,0 + 6d9c: 0900 addi s0,sp,144 + 6d9e: 0010 0x10 + 6da0: 0001 nop + 6da2: 01970403 lb s0,25(a4) + 6da6: 00090003 lb zero,0(s2) + 6daa: 0100 addi s0,sp,128 + 6dac: 0300 addi s0,sp,384 + 6dae: 9704 0x9704 + 6db0: 0301 addi t1,t1,0 + 6db2: 0900 addi s0,sp,144 + 6db4: 0000 unimp + 6db6: 0001 nop + 6db8: 01970403 lb s0,25(a4) + 6dbc: 00090003 lb zero,0(s2) + 6dc0: 0100 addi s0,sp,128 + 6dc2: 0300 addi s0,sp,384 + 6dc4: 9704 0x9704 + 6dc6: 0301 addi t1,t1,0 + 6dc8: 0900 addi s0,sp,144 + 6dca: 0030 addi a2,sp,8 + 6dcc: 0001 nop + 6dce: 01970403 lb s0,25(a4) + 6dd2: 00090003 lb zero,0(s2) + 6dd6: 0100 addi s0,sp,128 + 6dd8: 0300 addi s0,sp,384 + 6dda: 9704 0x9704 + 6ddc: 0301 addi t1,t1,0 + 6dde: 0900 addi s0,sp,144 + 6de0: 0000 unimp + 6de2: 0001 nop + 6de4: 01970403 lb s0,25(a4) + 6de8: 00090003 lb zero,0(s2) + 6dec: 0100 addi s0,sp,128 + 6dee: 0300 addi s0,sp,384 + 6df0: 9704 0x9704 + 6df2: 0301 addi t1,t1,0 + 6df4: 0900 addi s0,sp,144 + 6df6: 0004 0x4 + 6df8: 0001 nop + 6dfa: 01970403 lb s0,25(a4) + 6dfe: 00090003 lb zero,0(s2) + 6e02: 0100 addi s0,sp,128 + 6e04: 0300 addi s0,sp,384 + 6e06: 9704 0x9704 + 6e08: 0301 addi t1,t1,0 + 6e0a: 0900 addi s0,sp,144 + 6e0c: 0000 unimp + 6e0e: 0001 nop + 6e10: 01970403 lb s0,25(a4) + 6e14: 00090003 lb zero,0(s2) + 6e18: 0100 addi s0,sp,128 + 6e1a: 0306 slli t1,t1,0x1 6e1c: 0900 addi s0,sp,144 - 6e1e: 0030 addi a2,sp,8 + 6e1e: 0008 0x8 6e20: 0001 nop - 6e22: 01970403 lb s0,25(a4) - 6e26: 00090003 lb zero,0(s2) - 6e2a: 0100 addi s0,sp,128 - 6e2c: 0300 addi s0,sp,384 - 6e2e: 9704 0x9704 - 6e30: 0301 addi t1,t1,0 - 6e32: 0900 addi s0,sp,144 - 6e34: 0000 unimp - 6e36: 0001 nop - 6e38: 01970403 lb s0,25(a4) - 6e3c: 00090003 lb zero,0(s2) - 6e40: 0100 addi s0,sp,128 - 6e42: 0300 addi s0,sp,384 - 6e44: 9704 0x9704 - 6e46: 0301 addi t1,t1,0 - 6e48: 0900 addi s0,sp,144 - 6e4a: 0004 0x4 - 6e4c: 0001 nop - 6e4e: 01970403 lb s0,25(a4) - 6e52: 00090003 lb zero,0(s2) - 6e56: 0100 addi s0,sp,128 - 6e58: 0300 addi s0,sp,384 - 6e5a: 9704 0x9704 - 6e5c: 0301 addi t1,t1,0 - 6e5e: 0900 addi s0,sp,144 - 6e60: 0000 unimp - 6e62: 0001 nop - 6e64: 01970403 lb s0,25(a4) - 6e68: 00090003 lb zero,0(s2) - 6e6c: 0100 addi s0,sp,128 - 6e6e: 0306 slli t1,t1,0x1 - 6e70: 0900 addi s0,sp,144 - 6e72: 0008 0x8 - 6e74: 0001 nop - 6e76: 01990403 lb s0,25(s2) - 6e7a: 0306 slli t1,t1,0x1 - 6e7c: 0900 addi s0,sp,144 - 6e7e: 0008 0x8 - 6e80: 0001 nop - 6e82: 01990403 lb s0,25(s2) - 6e86: 10090003 lb zero,256(s2) - 6e8a: 0100 addi s0,sp,128 - 6e8c: 0300 addi s0,sp,384 - 6e8e: aa04 fsd fs1,16(a2) - 6e90: 0301 addi t1,t1,0 - 6e92: 0900 addi s0,sp,144 - 6e94: 0008 0x8 - 6e96: 0001 nop - 6e98: 01aa0403 lb s0,26(s4) - 6e9c: 00090003 lb zero,0(s2) - 6ea0: 0100 addi s0,sp,128 - 6ea2: 0300 addi s0,sp,384 - 6ea4: aa04 fsd fs1,16(a2) - 6ea6: 0301 addi t1,t1,0 - 6ea8: 0900 addi s0,sp,144 - 6eaa: 0000 unimp - 6eac: 0001 nop - 6eae: 01aa0403 lb s0,26(s4) - 6eb2: 00090003 lb zero,0(s2) - 6eb6: 0100 addi s0,sp,128 - 6eb8: 0300 addi s0,sp,384 - 6eba: aa04 fsd fs1,16(a2) - 6ebc: 0301 addi t1,t1,0 - 6ebe: 0900 addi s0,sp,144 - 6ec0: 0000 unimp - 6ec2: 0001 nop - 6ec4: 01aa0403 lb s0,26(s4) - 6ec8: 00090003 lb zero,0(s2) - 6ecc: 0100 addi s0,sp,128 - 6ece: 0300 addi s0,sp,384 - 6ed0: aa04 fsd fs1,16(a2) - 6ed2: 0301 addi t1,t1,0 - 6ed4: 0900 addi s0,sp,144 - 6ed6: 0000 unimp - 6ed8: 0001 nop - 6eda: 01aa0403 lb s0,26(s4) - 6ede: 00090003 lb zero,0(s2) - 6ee2: 0100 addi s0,sp,128 - 6ee4: 0300 addi s0,sp,384 - 6ee6: ab04 fsd fs1,16(a4) - 6ee8: 0301 addi t1,t1,0 - 6eea: 0900 addi s0,sp,144 - 6eec: 0004 0x4 - 6eee: 0001 nop - 6ef0: 01ae0403 lb s0,26(t3) - 6ef4: 0306 slli t1,t1,0x1 - 6ef6: 0900 addi s0,sp,144 - 6ef8: 0010 0x10 - 6efa: 0001 nop - 6efc: 01ac0403 lb s0,26(s8) - 6f00: 0306 slli t1,t1,0x1 - 6f02: 0900 addi s0,sp,144 - 6f04: 0008 0x8 - 6f06: 0001 nop - 6f08: 01ae0403 lb s0,26(t3) - 6f0c: 10090003 lb zero,256(s2) - 6f10: 0100 addi s0,sp,128 - 6f12: 0300 addi s0,sp,384 - 6f14: b604 fsd fs1,40(a2) - 6f16: 0301 addi t1,t1,0 - 6f18: 0900 addi s0,sp,144 - 6f1a: 0014 0x14 - 6f1c: 0001 nop - 6f1e: 01b60403 lb s0,27(a2) - 6f22: 00090003 lb zero,0(s2) - 6f26: 0100 addi s0,sp,128 - 6f28: 0300 addi s0,sp,384 - 6f2a: b604 fsd fs1,40(a2) - 6f2c: 0301 addi t1,t1,0 - 6f2e: 0900 addi s0,sp,144 - 6f30: 0000 unimp - 6f32: 0001 nop - 6f34: 01b60403 lb s0,27(a2) - 6f38: 00090003 lb zero,0(s2) - 6f3c: 0100 addi s0,sp,128 - 6f3e: 0300 addi s0,sp,384 - 6f40: b604 fsd fs1,40(a2) - 6f42: 0301 addi t1,t1,0 - 6f44: 0900 addi s0,sp,144 - 6f46: 0000 unimp - 6f48: 0001 nop - 6f4a: 01b60403 lb s0,27(a2) - 6f4e: 00090003 lb zero,0(s2) - 6f52: 0100 addi s0,sp,128 - 6f54: 0300 addi s0,sp,384 - 6f56: b604 fsd fs1,40(a2) - 6f58: 0301 addi t1,t1,0 - 6f5a: 0900 addi s0,sp,144 - 6f5c: 0000 unimp - 6f5e: 0001 nop - 6f60: 01b60403 lb s0,27(a2) - 6f64: 00090003 lb zero,0(s2) - 6f68: 0100 addi s0,sp,128 - 6f6a: 0300 addi s0,sp,384 - 6f6c: b604 fsd fs1,40(a2) - 6f6e: 0301 addi t1,t1,0 - 6f70: 0900 addi s0,sp,144 - 6f72: 0000 unimp - 6f74: 0001 nop - 6f76: 01b60403 lb s0,27(a2) - 6f7a: 00090003 lb zero,0(s2) - 6f7e: 0100 addi s0,sp,128 - 6f80: 0300 addi s0,sp,384 - 6f82: b604 fsd fs1,40(a2) - 6f84: 0301 addi t1,t1,0 - 6f86: 0900 addi s0,sp,144 - 6f88: 0010 0x10 - 6f8a: 0001 nop - 6f8c: 01b60403 lb s0,27(a2) - 6f90: 00090003 lb zero,0(s2) - 6f94: 0100 addi s0,sp,128 - 6f96: 0300 addi s0,sp,384 - 6f98: b604 fsd fs1,40(a2) - 6f9a: 0301 addi t1,t1,0 - 6f9c: 0900 addi s0,sp,144 - 6f9e: 0000 unimp - 6fa0: 0001 nop - 6fa2: 01b60403 lb s0,27(a2) - 6fa6: 00090003 lb zero,0(s2) - 6faa: 0100 addi s0,sp,128 - 6fac: 0300 addi s0,sp,384 - 6fae: b604 fsd fs1,40(a2) - 6fb0: 0301 addi t1,t1,0 - 6fb2: 0900 addi s0,sp,144 - 6fb4: 0000 unimp - 6fb6: 0001 nop - 6fb8: 01b60403 lb s0,27(a2) - 6fbc: 00090003 lb zero,0(s2) - 6fc0: 0100 addi s0,sp,128 - 6fc2: 0300 addi s0,sp,384 - 6fc4: b604 fsd fs1,40(a2) - 6fc6: 0301 addi t1,t1,0 - 6fc8: 0900 addi s0,sp,144 - 6fca: 0000 unimp - 6fcc: 0001 nop - 6fce: 01b60403 lb s0,27(a2) - 6fd2: 00090003 lb zero,0(s2) - 6fd6: 0100 addi s0,sp,128 - 6fd8: 0300 addi s0,sp,384 - 6fda: b604 fsd fs1,40(a2) - 6fdc: 0301 addi t1,t1,0 - 6fde: 0900 addi s0,sp,144 - 6fe0: 0000 unimp - 6fe2: 0001 nop - 6fe4: 01b60403 lb s0,27(a2) - 6fe8: 00090003 lb zero,0(s2) - 6fec: 0100 addi s0,sp,128 - 6fee: 0300 addi s0,sp,384 - 6ff0: b604 fsd fs1,40(a2) - 6ff2: 0301 addi t1,t1,0 - 6ff4: 0900 addi s0,sp,144 - 6ff6: 0000 unimp - 6ff8: 0001 nop - 6ffa: 01d20403 lb s0,29(tp) # 1d <_start-0x7fffffe3> - 6ffe: 04090003 lb zero,64(s2) - 7002: 0100 addi s0,sp,128 - 7004: 0300 addi s0,sp,384 - 7006: d204 sw s1,32(a2) - 7008: 0301 addi t1,t1,0 - 700a: 0900 addi s0,sp,144 - 700c: 001c 0x1c - 700e: 0001 nop - 7010: 01d20403 lb s0,29(tp) # 1d <_start-0x7fffffe3> - 7014: 00090003 lb zero,0(s2) - 7018: 0100 addi s0,sp,128 - 701a: 0300 addi s0,sp,384 - 701c: ba04 fsd fs1,48(a2) - 701e: 0304 addi s1,sp,384 - 7020: 0900 addi s0,sp,144 - 7022: 0004 0x4 - 7024: 0001 nop - 7026: 04ba0403 lb s0,75(s4) - 702a: 14090003 lb zero,320(s2) - 702e: 0100 addi s0,sp,128 - 7030: 0300 addi s0,sp,384 - 7032: 8d04 0x8d04 - 7034: 0301 addi t1,t1,0 - 7036: 0900 addi s0,sp,144 - 7038: 0008 0x8 - 703a: 0001 nop - 703c: 018d0403 lb s0,24(s10) # b018 <_start-0x7fff4fe8> - 7040: 00090003 lb zero,0(s2) - 7044: 0100 addi s0,sp,128 - 7046: 0300 addi s0,sp,384 - 7048: 8d04 0x8d04 - 704a: 0301 addi t1,t1,0 - 704c: 0900 addi s0,sp,144 - 704e: 0000 unimp - 7050: 0001 nop - 7052: 018d0403 lb s0,24(s10) - 7056: 00090003 lb zero,0(s2) - 705a: 0100 addi s0,sp,128 - 705c: 0300 addi s0,sp,384 - 705e: 8d04 0x8d04 - 7060: 0301 addi t1,t1,0 - 7062: 0900 addi s0,sp,144 - 7064: 0010 0x10 - 7066: 0001 nop - 7068: 018d0403 lb s0,24(s10) - 706c: 00090003 lb zero,0(s2) - 7070: 0100 addi s0,sp,128 - 7072: 0300 addi s0,sp,384 - 7074: 8d04 0x8d04 - 7076: 0301 addi t1,t1,0 - 7078: 0900 addi s0,sp,144 - 707a: 0000 unimp - 707c: 0001 nop - 707e: 018d0403 lb s0,24(s10) - 7082: 00090003 lb zero,0(s2) - 7086: 0100 addi s0,sp,128 - 7088: 0300 addi s0,sp,384 - 708a: 8d04 0x8d04 - 708c: 0301 addi t1,t1,0 - 708e: 0900 addi s0,sp,144 - 7090: 0018 0x18 - 7092: 0001 nop - 7094: 018d0403 lb s0,24(s10) - 7098: 00090003 lb zero,0(s2) - 709c: 0100 addi s0,sp,128 - 709e: 0300 addi s0,sp,384 - 70a0: 8d04 0x8d04 - 70a2: 0301 addi t1,t1,0 - 70a4: 0900 addi s0,sp,144 - 70a6: 0000 unimp - 70a8: 0001 nop - 70aa: 018d0403 lb s0,24(s10) - 70ae: 00090003 lb zero,0(s2) - 70b2: 0100 addi s0,sp,128 - 70b4: 0300 addi s0,sp,384 - 70b6: 8d04 0x8d04 - 70b8: 0301 addi t1,t1,0 - 70ba: 0900 addi s0,sp,144 - 70bc: 001c 0x1c - 70be: 0001 nop - 70c0: 018d0403 lb s0,24(s10) - 70c4: 00090003 lb zero,0(s2) - 70c8: 0100 addi s0,sp,128 - 70ca: 0300 addi s0,sp,384 - 70cc: 8d04 0x8d04 - 70ce: 0301 addi t1,t1,0 - 70d0: 0900 addi s0,sp,144 - 70d2: 0004 0x4 - 70d4: 0001 nop - 70d6: 018d0403 lb s0,24(s10) - 70da: 00090003 lb zero,0(s2) - 70de: 0100 addi s0,sp,128 - 70e0: 0300 addi s0,sp,384 - 70e2: 8d04 0x8d04 - 70e4: 0301 addi t1,t1,0 - 70e6: 0900 addi s0,sp,144 - 70e8: 0000 unimp - 70ea: 0001 nop - 70ec: 018d0403 lb s0,24(s10) - 70f0: 00090003 lb zero,0(s2) - 70f4: 0100 addi s0,sp,128 - 70f6: 0300 addi s0,sp,384 - 70f8: 8d04 0x8d04 - 70fa: 0301 addi t1,t1,0 - 70fc: 0900 addi s0,sp,144 - 70fe: 0000 unimp - 7100: 0001 nop - 7102: 018d0403 lb s0,24(s10) - 7106: 00090003 lb zero,0(s2) - 710a: 0100 addi s0,sp,128 - 710c: 0300 addi s0,sp,384 - 710e: 8d04 0x8d04 - 7110: 0301 addi t1,t1,0 - 7112: 0900 addi s0,sp,144 - 7114: 0000 unimp - 7116: 0001 nop - 7118: 018d0403 lb s0,24(s10) - 711c: 00090003 lb zero,0(s2) - 7120: 0100 addi s0,sp,128 - 7122: 0300 addi s0,sp,384 - 7124: 8d04 0x8d04 - 7126: 0301 addi t1,t1,0 - 7128: 0900 addi s0,sp,144 - 712a: 0000 unimp - 712c: 0001 nop - 712e: 018d0403 lb s0,24(s10) - 7132: 00090003 lb zero,0(s2) - 7136: 0100 addi s0,sp,128 - 7138: 0300 addi s0,sp,384 - 713a: 8d04 0x8d04 - 713c: 0301 addi t1,t1,0 - 713e: 0900 addi s0,sp,144 - 7140: 0000 unimp - 7142: 0001 nop - 7144: 018d0403 lb s0,24(s10) - 7148: 00090003 lb zero,0(s2) - 714c: 0100 addi s0,sp,128 - 714e: 0300 addi s0,sp,384 - 7150: 8d04 0x8d04 - 7152: 0301 addi t1,t1,0 - 7154: 0900 addi s0,sp,144 - 7156: 0000 unimp - 7158: 0001 nop - 715a: 018d0403 lb s0,24(s10) - 715e: 00090003 lb zero,0(s2) - 7162: 0100 addi s0,sp,128 - 7164: 0300 addi s0,sp,384 - 7166: 8d04 0x8d04 - 7168: 0301 addi t1,t1,0 - 716a: 0900 addi s0,sp,144 - 716c: 0000 unimp - 716e: 0001 nop - 7170: 018d0403 lb s0,24(s10) - 7174: 00090003 lb zero,0(s2) - 7178: 0100 addi s0,sp,128 - 717a: 0300 addi s0,sp,384 - 717c: 8d04 0x8d04 - 717e: 0301 addi t1,t1,0 - 7180: 0900 addi s0,sp,144 - 7182: 0000 unimp - 7184: 0001 nop - 7186: 01e40403 lb s0,30(s0) - 718a: 04090003 lb zero,64(s2) - 718e: 0100 addi s0,sp,128 - 7190: 0300 addi s0,sp,384 - 7192: e404 fsw fs1,8(s0) - 7194: 0301 addi t1,t1,0 - 7196: 0900 addi s0,sp,144 - 7198: 001c 0x1c - 719a: 0001 nop - 719c: 01e40403 lb s0,30(s0) - 71a0: 00090003 lb zero,0(s2) + 6e22: 01990403 lb s0,25(s2) + 6e26: 0306 slli t1,t1,0x1 + 6e28: 0900 addi s0,sp,144 + 6e2a: 0008 0x8 + 6e2c: 0001 nop + 6e2e: 01990403 lb s0,25(s2) + 6e32: 10090003 lb zero,256(s2) + 6e36: 0100 addi s0,sp,128 + 6e38: 0300 addi s0,sp,384 + 6e3a: aa04 fsd fs1,16(a2) + 6e3c: 0301 addi t1,t1,0 + 6e3e: 0900 addi s0,sp,144 + 6e40: 0008 0x8 + 6e42: 0001 nop + 6e44: 01aa0403 lb s0,26(s4) + 6e48: 00090003 lb zero,0(s2) + 6e4c: 0100 addi s0,sp,128 + 6e4e: 0300 addi s0,sp,384 + 6e50: aa04 fsd fs1,16(a2) + 6e52: 0301 addi t1,t1,0 + 6e54: 0900 addi s0,sp,144 + 6e56: 0000 unimp + 6e58: 0001 nop + 6e5a: 01aa0403 lb s0,26(s4) + 6e5e: 00090003 lb zero,0(s2) + 6e62: 0100 addi s0,sp,128 + 6e64: 0300 addi s0,sp,384 + 6e66: aa04 fsd fs1,16(a2) + 6e68: 0301 addi t1,t1,0 + 6e6a: 0900 addi s0,sp,144 + 6e6c: 0000 unimp + 6e6e: 0001 nop + 6e70: 01aa0403 lb s0,26(s4) + 6e74: 00090003 lb zero,0(s2) + 6e78: 0100 addi s0,sp,128 + 6e7a: 0300 addi s0,sp,384 + 6e7c: aa04 fsd fs1,16(a2) + 6e7e: 0301 addi t1,t1,0 + 6e80: 0900 addi s0,sp,144 + 6e82: 0000 unimp + 6e84: 0001 nop + 6e86: 01aa0403 lb s0,26(s4) + 6e8a: 00090003 lb zero,0(s2) + 6e8e: 0100 addi s0,sp,128 + 6e90: 0300 addi s0,sp,384 + 6e92: ab04 fsd fs1,16(a4) + 6e94: 0301 addi t1,t1,0 + 6e96: 0900 addi s0,sp,144 + 6e98: 0004 0x4 + 6e9a: 0001 nop + 6e9c: 01ae0403 lb s0,26(t3) + 6ea0: 0306 slli t1,t1,0x1 + 6ea2: 0900 addi s0,sp,144 + 6ea4: 0010 0x10 + 6ea6: 0001 nop + 6ea8: 01ac0403 lb s0,26(s8) + 6eac: 0306 slli t1,t1,0x1 + 6eae: 0900 addi s0,sp,144 + 6eb0: 0008 0x8 + 6eb2: 0001 nop + 6eb4: 01ae0403 lb s0,26(t3) + 6eb8: 10090003 lb zero,256(s2) + 6ebc: 0100 addi s0,sp,128 + 6ebe: 0300 addi s0,sp,384 + 6ec0: b604 fsd fs1,40(a2) + 6ec2: 0301 addi t1,t1,0 + 6ec4: 0900 addi s0,sp,144 + 6ec6: 0014 0x14 + 6ec8: 0001 nop + 6eca: 01b60403 lb s0,27(a2) + 6ece: 00090003 lb zero,0(s2) + 6ed2: 0100 addi s0,sp,128 + 6ed4: 0300 addi s0,sp,384 + 6ed6: b604 fsd fs1,40(a2) + 6ed8: 0301 addi t1,t1,0 + 6eda: 0900 addi s0,sp,144 + 6edc: 0000 unimp + 6ede: 0001 nop + 6ee0: 01b60403 lb s0,27(a2) + 6ee4: 00090003 lb zero,0(s2) + 6ee8: 0100 addi s0,sp,128 + 6eea: 0300 addi s0,sp,384 + 6eec: b604 fsd fs1,40(a2) + 6eee: 0301 addi t1,t1,0 + 6ef0: 0900 addi s0,sp,144 + 6ef2: 0000 unimp + 6ef4: 0001 nop + 6ef6: 01b60403 lb s0,27(a2) + 6efa: 00090003 lb zero,0(s2) + 6efe: 0100 addi s0,sp,128 + 6f00: 0300 addi s0,sp,384 + 6f02: b604 fsd fs1,40(a2) + 6f04: 0301 addi t1,t1,0 + 6f06: 0900 addi s0,sp,144 + 6f08: 0000 unimp + 6f0a: 0001 nop + 6f0c: 01b60403 lb s0,27(a2) + 6f10: 00090003 lb zero,0(s2) + 6f14: 0100 addi s0,sp,128 + 6f16: 0300 addi s0,sp,384 + 6f18: b604 fsd fs1,40(a2) + 6f1a: 0301 addi t1,t1,0 + 6f1c: 0900 addi s0,sp,144 + 6f1e: 0000 unimp + 6f20: 0001 nop + 6f22: 01b60403 lb s0,27(a2) + 6f26: 00090003 lb zero,0(s2) + 6f2a: 0100 addi s0,sp,128 + 6f2c: 0300 addi s0,sp,384 + 6f2e: b604 fsd fs1,40(a2) + 6f30: 0301 addi t1,t1,0 + 6f32: 0900 addi s0,sp,144 + 6f34: 0010 0x10 + 6f36: 0001 nop + 6f38: 01b60403 lb s0,27(a2) + 6f3c: 00090003 lb zero,0(s2) + 6f40: 0100 addi s0,sp,128 + 6f42: 0300 addi s0,sp,384 + 6f44: b604 fsd fs1,40(a2) + 6f46: 0301 addi t1,t1,0 + 6f48: 0900 addi s0,sp,144 + 6f4a: 0000 unimp + 6f4c: 0001 nop + 6f4e: 01b60403 lb s0,27(a2) + 6f52: 00090003 lb zero,0(s2) + 6f56: 0100 addi s0,sp,128 + 6f58: 0300 addi s0,sp,384 + 6f5a: b604 fsd fs1,40(a2) + 6f5c: 0301 addi t1,t1,0 + 6f5e: 0900 addi s0,sp,144 + 6f60: 0000 unimp + 6f62: 0001 nop + 6f64: 01b60403 lb s0,27(a2) + 6f68: 00090003 lb zero,0(s2) + 6f6c: 0100 addi s0,sp,128 + 6f6e: 0300 addi s0,sp,384 + 6f70: b604 fsd fs1,40(a2) + 6f72: 0301 addi t1,t1,0 + 6f74: 0900 addi s0,sp,144 + 6f76: 0000 unimp + 6f78: 0001 nop + 6f7a: 01b60403 lb s0,27(a2) + 6f7e: 00090003 lb zero,0(s2) + 6f82: 0100 addi s0,sp,128 + 6f84: 0300 addi s0,sp,384 + 6f86: b604 fsd fs1,40(a2) + 6f88: 0301 addi t1,t1,0 + 6f8a: 0900 addi s0,sp,144 + 6f8c: 0000 unimp + 6f8e: 0001 nop + 6f90: 01b60403 lb s0,27(a2) + 6f94: 00090003 lb zero,0(s2) + 6f98: 0100 addi s0,sp,128 + 6f9a: 0300 addi s0,sp,384 + 6f9c: b604 fsd fs1,40(a2) + 6f9e: 0301 addi t1,t1,0 + 6fa0: 0900 addi s0,sp,144 + 6fa2: 0000 unimp + 6fa4: 0001 nop + 6fa6: 01d20403 lb s0,29(tp) # 1d <_start-0x7fffffe3> + 6faa: 04090003 lb zero,64(s2) + 6fae: 0100 addi s0,sp,128 + 6fb0: 0300 addi s0,sp,384 + 6fb2: d204 sw s1,32(a2) + 6fb4: 0301 addi t1,t1,0 + 6fb6: 0900 addi s0,sp,144 + 6fb8: 001c 0x1c + 6fba: 0001 nop + 6fbc: 01d20403 lb s0,29(tp) # 1d <_start-0x7fffffe3> + 6fc0: 00090003 lb zero,0(s2) + 6fc4: 0100 addi s0,sp,128 + 6fc6: 0300 addi s0,sp,384 + 6fc8: ba04 fsd fs1,48(a2) + 6fca: 0304 addi s1,sp,384 + 6fcc: 0900 addi s0,sp,144 + 6fce: 0004 0x4 + 6fd0: 0001 nop + 6fd2: 04ba0403 lb s0,75(s4) + 6fd6: 14090003 lb zero,320(s2) + 6fda: 0100 addi s0,sp,128 + 6fdc: 0300 addi s0,sp,384 + 6fde: 8d04 0x8d04 + 6fe0: 0301 addi t1,t1,0 + 6fe2: 0900 addi s0,sp,144 + 6fe4: 0008 0x8 + 6fe6: 0001 nop + 6fe8: 018d0403 lb s0,24(s10) # b018 <_start-0x7fff4fe8> + 6fec: 00090003 lb zero,0(s2) + 6ff0: 0100 addi s0,sp,128 + 6ff2: 0300 addi s0,sp,384 + 6ff4: 8d04 0x8d04 + 6ff6: 0301 addi t1,t1,0 + 6ff8: 0900 addi s0,sp,144 + 6ffa: 0000 unimp + 6ffc: 0001 nop + 6ffe: 018d0403 lb s0,24(s10) + 7002: 00090003 lb zero,0(s2) + 7006: 0100 addi s0,sp,128 + 7008: 0300 addi s0,sp,384 + 700a: 8d04 0x8d04 + 700c: 0301 addi t1,t1,0 + 700e: 0900 addi s0,sp,144 + 7010: 0010 0x10 + 7012: 0001 nop + 7014: 018d0403 lb s0,24(s10) + 7018: 00090003 lb zero,0(s2) + 701c: 0100 addi s0,sp,128 + 701e: 0300 addi s0,sp,384 + 7020: 8d04 0x8d04 + 7022: 0301 addi t1,t1,0 + 7024: 0900 addi s0,sp,144 + 7026: 0000 unimp + 7028: 0001 nop + 702a: 018d0403 lb s0,24(s10) + 702e: 00090003 lb zero,0(s2) + 7032: 0100 addi s0,sp,128 + 7034: 0300 addi s0,sp,384 + 7036: 8d04 0x8d04 + 7038: 0301 addi t1,t1,0 + 703a: 0900 addi s0,sp,144 + 703c: 0018 0x18 + 703e: 0001 nop + 7040: 018d0403 lb s0,24(s10) + 7044: 00090003 lb zero,0(s2) + 7048: 0100 addi s0,sp,128 + 704a: 0300 addi s0,sp,384 + 704c: 8d04 0x8d04 + 704e: 0301 addi t1,t1,0 + 7050: 0900 addi s0,sp,144 + 7052: 0000 unimp + 7054: 0001 nop + 7056: 018d0403 lb s0,24(s10) + 705a: 00090003 lb zero,0(s2) + 705e: 0100 addi s0,sp,128 + 7060: 0300 addi s0,sp,384 + 7062: 8d04 0x8d04 + 7064: 0301 addi t1,t1,0 + 7066: 0900 addi s0,sp,144 + 7068: 001c 0x1c + 706a: 0001 nop + 706c: 018d0403 lb s0,24(s10) + 7070: 00090003 lb zero,0(s2) + 7074: 0100 addi s0,sp,128 + 7076: 0300 addi s0,sp,384 + 7078: 8d04 0x8d04 + 707a: 0301 addi t1,t1,0 + 707c: 0900 addi s0,sp,144 + 707e: 0004 0x4 + 7080: 0001 nop + 7082: 018d0403 lb s0,24(s10) + 7086: 00090003 lb zero,0(s2) + 708a: 0100 addi s0,sp,128 + 708c: 0300 addi s0,sp,384 + 708e: 8d04 0x8d04 + 7090: 0301 addi t1,t1,0 + 7092: 0900 addi s0,sp,144 + 7094: 0000 unimp + 7096: 0001 nop + 7098: 018d0403 lb s0,24(s10) + 709c: 00090003 lb zero,0(s2) + 70a0: 0100 addi s0,sp,128 + 70a2: 0300 addi s0,sp,384 + 70a4: 8d04 0x8d04 + 70a6: 0301 addi t1,t1,0 + 70a8: 0900 addi s0,sp,144 + 70aa: 0000 unimp + 70ac: 0001 nop + 70ae: 018d0403 lb s0,24(s10) + 70b2: 00090003 lb zero,0(s2) + 70b6: 0100 addi s0,sp,128 + 70b8: 0300 addi s0,sp,384 + 70ba: 8d04 0x8d04 + 70bc: 0301 addi t1,t1,0 + 70be: 0900 addi s0,sp,144 + 70c0: 0000 unimp + 70c2: 0001 nop + 70c4: 018d0403 lb s0,24(s10) + 70c8: 00090003 lb zero,0(s2) + 70cc: 0100 addi s0,sp,128 + 70ce: 0300 addi s0,sp,384 + 70d0: 8d04 0x8d04 + 70d2: 0301 addi t1,t1,0 + 70d4: 0900 addi s0,sp,144 + 70d6: 0000 unimp + 70d8: 0001 nop + 70da: 018d0403 lb s0,24(s10) + 70de: 00090003 lb zero,0(s2) + 70e2: 0100 addi s0,sp,128 + 70e4: 0300 addi s0,sp,384 + 70e6: 8d04 0x8d04 + 70e8: 0301 addi t1,t1,0 + 70ea: 0900 addi s0,sp,144 + 70ec: 0000 unimp + 70ee: 0001 nop + 70f0: 018d0403 lb s0,24(s10) + 70f4: 00090003 lb zero,0(s2) + 70f8: 0100 addi s0,sp,128 + 70fa: 0300 addi s0,sp,384 + 70fc: 8d04 0x8d04 + 70fe: 0301 addi t1,t1,0 + 7100: 0900 addi s0,sp,144 + 7102: 0000 unimp + 7104: 0001 nop + 7106: 018d0403 lb s0,24(s10) + 710a: 00090003 lb zero,0(s2) + 710e: 0100 addi s0,sp,128 + 7110: 0300 addi s0,sp,384 + 7112: 8d04 0x8d04 + 7114: 0301 addi t1,t1,0 + 7116: 0900 addi s0,sp,144 + 7118: 0000 unimp + 711a: 0001 nop + 711c: 018d0403 lb s0,24(s10) + 7120: 00090003 lb zero,0(s2) + 7124: 0100 addi s0,sp,128 + 7126: 0300 addi s0,sp,384 + 7128: 8d04 0x8d04 + 712a: 0301 addi t1,t1,0 + 712c: 0900 addi s0,sp,144 + 712e: 0000 unimp + 7130: 0001 nop + 7132: 01e40403 lb s0,30(s0) + 7136: 04090003 lb zero,64(s2) + 713a: 0100 addi s0,sp,128 + 713c: 0300 addi s0,sp,384 + 713e: e404 fsw fs1,8(s0) + 7140: 0301 addi t1,t1,0 + 7142: 0900 addi s0,sp,144 + 7144: 001c 0x1c + 7146: 0001 nop + 7148: 01e40403 lb s0,30(s0) + 714c: 00090003 lb zero,0(s2) + 7150: 0100 addi s0,sp,128 + 7152: 0300 addi s0,sp,384 + 7154: e504 fsw fs1,8(a0) + 7156: 0301 addi t1,t1,0 + 7158: 0900 addi s0,sp,144 + 715a: 0004 0x4 + 715c: 0001 nop + 715e: 01e50403 lb s0,30(a0) + 7162: 00090003 lb zero,0(s2) + 7166: 0100 addi s0,sp,128 + 7168: 0300 addi s0,sp,384 + 716a: e504 fsw fs1,8(a0) + 716c: 0301 addi t1,t1,0 + 716e: 0900 addi s0,sp,144 + 7170: 0000 unimp + 7172: 0001 nop + 7174: 01e50403 lb s0,30(a0) + 7178: 00090003 lb zero,0(s2) + 717c: 0100 addi s0,sp,128 + 717e: 0300 addi s0,sp,384 + 7180: e504 fsw fs1,8(a0) + 7182: 0301 addi t1,t1,0 + 7184: 0900 addi s0,sp,144 + 7186: 0000 unimp + 7188: 0001 nop + 718a: 01e50403 lb s0,30(a0) + 718e: 00090003 lb zero,0(s2) + 7192: 0100 addi s0,sp,128 + 7194: 0300 addi s0,sp,384 + 7196: e504 fsw fs1,8(a0) + 7198: 0301 addi t1,t1,0 + 719a: 0900 addi s0,sp,144 + 719c: 0000 unimp + 719e: 0601 addi a2,a2,0 + 71a0: 0c090003 lb zero,192(s2) 71a4: 0100 addi s0,sp,128 71a6: 0300 addi s0,sp,384 - 71a8: e504 fsw fs1,8(a0) - 71aa: 0301 addi t1,t1,0 - 71ac: 0900 addi s0,sp,144 - 71ae: 0004 0x4 - 71b0: 0001 nop - 71b2: 01e50403 lb s0,30(a0) - 71b6: 00090003 lb zero,0(s2) - 71ba: 0100 addi s0,sp,128 - 71bc: 0300 addi s0,sp,384 - 71be: e504 fsw fs1,8(a0) - 71c0: 0301 addi t1,t1,0 - 71c2: 0900 addi s0,sp,144 - 71c4: 0000 unimp - 71c6: 0001 nop - 71c8: 01e50403 lb s0,30(a0) - 71cc: 00090003 lb zero,0(s2) - 71d0: 0100 addi s0,sp,128 - 71d2: 0300 addi s0,sp,384 - 71d4: e504 fsw fs1,8(a0) - 71d6: 0301 addi t1,t1,0 - 71d8: 0900 addi s0,sp,144 - 71da: 0000 unimp - 71dc: 0001 nop - 71de: 01e50403 lb s0,30(a0) - 71e2: 00090003 lb zero,0(s2) - 71e6: 0100 addi s0,sp,128 - 71e8: 0300 addi s0,sp,384 - 71ea: e504 fsw fs1,8(a0) - 71ec: 0301 addi t1,t1,0 + 71a8: f404 fsw fs1,40(s0) + 71aa: 0601 addi a2,a2,0 + 71ac: 0c090003 lb zero,192(s2) + 71b0: 0100 addi s0,sp,128 + 71b2: 0300 addi s0,sp,384 + 71b4: f404 fsw fs1,40(s0) + 71b6: 0301 addi t1,t1,0 + 71b8: 0900 addi s0,sp,144 + 71ba: 0000 unimp + 71bc: 0001 nop + 71be: 01f40403 lb s0,31(s0) + 71c2: 08090003 lb zero,128(s2) + 71c6: 0100 addi s0,sp,128 + 71c8: 0300 addi s0,sp,384 + 71ca: f404 fsw fs1,40(s0) + 71cc: 0301 addi t1,t1,0 + 71ce: 0900 addi s0,sp,144 + 71d0: 0000 unimp + 71d2: 0001 nop + 71d4: 01f40403 lb s0,31(s0) + 71d8: 00090003 lb zero,0(s2) + 71dc: 0100 addi s0,sp,128 + 71de: 0300 addi s0,sp,384 + 71e0: f404 fsw fs1,40(s0) + 71e2: 0301 addi t1,t1,0 + 71e4: 0900 addi s0,sp,144 + 71e6: 0000 unimp + 71e8: 0001 nop + 71ea: 0402 c.slli64 s0 + 71ec: 030d addi t1,t1,3 71ee: 0900 addi s0,sp,144 - 71f0: 0000 unimp - 71f2: 0601 addi a2,a2,0 - 71f4: 0c090003 lb zero,192(s2) - 71f8: 0100 addi s0,sp,128 - 71fa: 0300 addi s0,sp,384 - 71fc: f404 fsw fs1,40(s0) - 71fe: 0601 addi a2,a2,0 - 7200: 0c090003 lb zero,192(s2) - 7204: 0100 addi s0,sp,128 - 7206: 0300 addi s0,sp,384 - 7208: f404 fsw fs1,40(s0) - 720a: 0301 addi t1,t1,0 - 720c: 0900 addi s0,sp,144 - 720e: 0000 unimp - 7210: 0001 nop - 7212: 01f40403 lb s0,31(s0) - 7216: 08090003 lb zero,128(s2) - 721a: 0100 addi s0,sp,128 - 721c: 0300 addi s0,sp,384 - 721e: f404 fsw fs1,40(s0) - 7220: 0301 addi t1,t1,0 - 7222: 0900 addi s0,sp,144 - 7224: 0000 unimp - 7226: 0001 nop - 7228: 01f40403 lb s0,31(s0) - 722c: 00090003 lb zero,0(s2) - 7230: 0100 addi s0,sp,128 - 7232: 0300 addi s0,sp,384 - 7234: f404 fsw fs1,40(s0) - 7236: 0301 addi t1,t1,0 - 7238: 0900 addi s0,sp,144 - 723a: 0000 unimp - 723c: 0001 nop - 723e: 0402 c.slli64 s0 - 7240: 030d addi t1,t1,3 - 7242: 0900 addi s0,sp,144 - 7244: 0014 0x14 - 7246: 0001 nop - 7248: 0402 c.slli64 s0 - 724a: 030d addi t1,t1,3 - 724c: 0900 addi s0,sp,144 - 724e: 0000 unimp - 7250: 0001 nop - 7252: 029d0403 lb s0,41(s10) - 7256: 04090003 lb zero,64(s2) - 725a: 0100 addi s0,sp,128 - 725c: 0300 addi s0,sp,384 - 725e: 9d04 0x9d04 - 7260: 0302 c.slli64 t1 - 7262: 0900 addi s0,sp,144 - 7264: 0000 unimp - 7266: 0001 nop - 7268: 029d0403 lb s0,41(s10) - 726c: 00090003 lb zero,0(s2) - 7270: 0100 addi s0,sp,128 - 7272: 0300 addi s0,sp,384 - 7274: 9f04 0x9f04 - 7276: 0302 c.slli64 t1 - 7278: 0900 addi s0,sp,144 - 727a: 0010 0x10 - 727c: 0001 nop - 727e: 02a90403 lb s0,42(s2) - 7282: 1c090003 lb zero,448(s2) - 7286: 0100 addi s0,sp,128 - 7288: 0300 addi s0,sp,384 - 728a: a904 fsd fs1,16(a0) - 728c: 0302 c.slli64 t1 - 728e: 0900 addi s0,sp,144 - 7290: 0000 unimp - 7292: 0001 nop - 7294: 02a90403 lb s0,42(s2) - 7298: 00090003 lb zero,0(s2) - 729c: 0100 addi s0,sp,128 - 729e: 0300 addi s0,sp,384 - 72a0: a904 fsd fs1,16(a0) - 72a2: 0302 c.slli64 t1 - 72a4: 0900 addi s0,sp,144 - 72a6: 0000 unimp - 72a8: 0001 nop - 72aa: 02a20403 lb s0,42(tp) # 2a <_start-0x7fffffd6> - 72ae: 14090003 lb zero,320(s2) - 72b2: 0100 addi s0,sp,128 - 72b4: 0300 addi s0,sp,384 - 72b6: a204 fsd fs1,0(a2) - 72b8: 0302 c.slli64 t1 - 72ba: 0900 addi s0,sp,144 - 72bc: 0000 unimp - 72be: 0001 nop - 72c0: 02a20403 lb s0,42(tp) # 2a <_start-0x7fffffd6> - 72c4: 04090003 lb zero,64(s2) - 72c8: 0100 addi s0,sp,128 - 72ca: 0300 addi s0,sp,384 - 72cc: ab04 fsd fs1,16(a4) - 72ce: 0302 c.slli64 t1 - 72d0: 0900 addi s0,sp,144 - 72d2: 0004 0x4 - 72d4: 0001 nop - 72d6: 02ab0403 lb s0,42(s6) - 72da: 00090003 lb zero,0(s2) - 72de: 0100 addi s0,sp,128 - 72e0: 0300 addi s0,sp,384 - 72e2: ab04 fsd fs1,16(a4) - 72e4: 0302 c.slli64 t1 - 72e6: 0900 addi s0,sp,144 - 72e8: 0000 unimp - 72ea: 0001 nop - 72ec: 02ab0403 lb s0,42(s6) - 72f0: 00090003 lb zero,0(s2) - 72f4: 0100 addi s0,sp,128 - 72f6: 0300 addi s0,sp,384 - 72f8: ab04 fsd fs1,16(a4) - 72fa: 0302 c.slli64 t1 - 72fc: 0900 addi s0,sp,144 - 72fe: 0000 unimp - 7300: 0001 nop - 7302: 02ab0403 lb s0,42(s6) - 7306: 04090003 lb zero,64(s2) - 730a: 0100 addi s0,sp,128 - 730c: 0300 addi s0,sp,384 - 730e: ab04 fsd fs1,16(a4) - 7310: 0302 c.slli64 t1 - 7312: 0900 addi s0,sp,144 - 7314: 0000 unimp - 7316: 0001 nop - 7318: 02ab0403 lb s0,42(s6) - 731c: 04090003 lb zero,64(s2) - 7320: 0100 addi s0,sp,128 - 7322: 0300 addi s0,sp,384 - 7324: ab04 fsd fs1,16(a4) - 7326: 0302 c.slli64 t1 - 7328: 0900 addi s0,sp,144 - 732a: 0008 0x8 - 732c: 0001 nop - 732e: 02ab0403 lb s0,42(s6) - 7332: 04090003 lb zero,64(s2) - 7336: 0100 addi s0,sp,128 - 7338: 0300 addi s0,sp,384 - 733a: ad04 fsd fs1,24(a0) - 733c: 0602 c.slli64 a2 - 733e: 08090003 lb zero,128(s2) - 7342: 0100 addi s0,sp,128 - 7344: 0300 addi s0,sp,384 - 7346: b204 fsd fs1,32(a2) - 7348: 0302 c.slli64 t1 - 734a: 0900 addi s0,sp,144 - 734c: 0008 0x8 - 734e: 0001 nop - 7350: 02b20403 lb s0,43(tp) # 2b <_start-0x7fffffd5> - 7354: 0306 slli t1,t1,0x1 - 7356: 0900 addi s0,sp,144 - 7358: 0004 0x4 - 735a: 0001 nop - 735c: 02b20403 lb s0,43(tp) # 2b <_start-0x7fffffd5> - 7360: 04090003 lb zero,64(s2) - 7364: 0100 addi s0,sp,128 - 7366: 0300 addi s0,sp,384 - 7368: b204 fsd fs1,32(a2) - 736a: 0302 c.slli64 t1 - 736c: 0900 addi s0,sp,144 - 736e: 0004 0x4 - 7370: 0001 nop - 7372: 02b20403 lb s0,43(tp) # 2b <_start-0x7fffffd5> - 7376: 04090003 lb zero,64(s2) - 737a: 0100 addi s0,sp,128 - 737c: 0300 addi s0,sp,384 - 737e: b304 fsd fs1,32(a4) - 7380: 0602 c.slli64 a2 - 7382: 04090003 lb zero,64(s2) - 7386: 0100 addi s0,sp,128 - 7388: 0300 addi s0,sp,384 - 738a: b804 fsd fs1,48(s0) - 738c: 0602 c.slli64 a2 - 738e: 08090003 lb zero,128(s2) - 7392: 0100 addi s0,sp,128 - 7394: 0300 addi s0,sp,384 - 7396: b804 fsd fs1,48(s0) - 7398: 0302 c.slli64 t1 - 739a: 0900 addi s0,sp,144 - 739c: 0010 0x10 - 739e: 0001 nop - 73a0: 02b80403 lb s0,43(a6) - 73a4: 04090003 lb zero,64(s2) - 73a8: 0100 addi s0,sp,128 - 73aa: 0300 addi s0,sp,384 - 73ac: b804 fsd fs1,48(s0) - 73ae: 0302 c.slli64 t1 - 73b0: 0900 addi s0,sp,144 - 73b2: 0004 0x4 - 73b4: 0001 nop - 73b6: 02b80403 lb s0,43(a6) - 73ba: 04090003 lb zero,64(s2) - 73be: 0100 addi s0,sp,128 - 73c0: 0300 addi s0,sp,384 - 73c2: b804 fsd fs1,48(s0) - 73c4: 0302 c.slli64 t1 - 73c6: 0900 addi s0,sp,144 - 73c8: 0000 unimp - 73ca: 0001 nop - 73cc: 038e0403 lb s0,56(t3) - 73d0: 0306 slli t1,t1,0x1 - 73d2: 097f 0x97f - 73d4: 0000 unimp - 73d6: 0001 nop - 73d8: 038e0403 lb s0,56(t3) - 73dc: 04090103 lb sp,64(s2) - 73e0: 0100 addi s0,sp,128 - 73e2: 0300 addi s0,sp,384 - 73e4: ac04 fsd fs1,24(s0) - 73e6: 0602 c.slli64 a2 - 73e8: 04090003 lb zero,64(s2) - 73ec: 0100 addi s0,sp,128 - 73ee: 0c090003 lb zero,192(s2) - 73f2: 0100 addi s0,sp,128 - 73f4: 08090003 lb zero,128(s2) - 73f8: 0100 addi s0,sp,128 - 73fa: 0300 addi s0,sp,384 - 73fc: a004 fsd fs1,0(s0) - 73fe: 0302 c.slli64 t1 - 7400: 0900 addi s0,sp,144 - 7402: 0014 0x14 - 7404: 0001 nop - 7406: 02cd0403 lb s0,44(s10) - 740a: 0c090003 lb zero,192(s2) - 740e: 0100 addi s0,sp,128 - 7410: 0300 addi s0,sp,384 - 7412: cd04 sw s1,24(a0) - 7414: 0302 c.slli64 t1 - 7416: 0900 addi s0,sp,144 - 7418: 0000 unimp - 741a: 0001 nop - 741c: 02cd0403 lb s0,44(s10) - 7420: 00090003 lb zero,0(s2) - 7424: 0100 addi s0,sp,128 - 7426: 0300 addi s0,sp,384 - 7428: cd04 sw s1,24(a0) - 742a: 0302 c.slli64 t1 - 742c: 0900 addi s0,sp,144 - 742e: 0000 unimp - 7430: 0001 nop - 7432: 02cd0403 lb s0,44(s10) - 7436: 10090003 lb zero,256(s2) - 743a: 0100 addi s0,sp,128 - 743c: 0300 addi s0,sp,384 - 743e: c604 sw s1,8(a2) - 7440: 0302 c.slli64 t1 - 7442: 0900 addi s0,sp,144 - 7444: 0004 0x4 - 7446: 0001 nop - 7448: 02c60403 lb s0,44(a2) - 744c: 10090003 lb zero,256(s2) - 7450: 0100 addi s0,sp,128 - 7452: 0300 addi s0,sp,384 - 7454: d004 sw s1,32(s0) - 7456: 0302 c.slli64 t1 - 7458: 0900 addi s0,sp,144 - 745a: 000c 0xc - 745c: 0001 nop - 745e: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 7462: 00090003 lb zero,0(s2) - 7466: 0100 addi s0,sp,128 - 7468: 0300 addi s0,sp,384 - 746a: d004 sw s1,32(s0) - 746c: 0302 c.slli64 t1 - 746e: 0900 addi s0,sp,144 - 7470: 0000 unimp - 7472: 0001 nop - 7474: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 7478: 00090003 lb zero,0(s2) - 747c: 0100 addi s0,sp,128 - 747e: 0300 addi s0,sp,384 - 7480: d004 sw s1,32(s0) - 7482: 0302 c.slli64 t1 + 71f0: 0014 0x14 + 71f2: 0001 nop + 71f4: 0402 c.slli64 s0 + 71f6: 030d addi t1,t1,3 + 71f8: 0900 addi s0,sp,144 + 71fa: 0000 unimp + 71fc: 0001 nop + 71fe: 029d0403 lb s0,41(s10) + 7202: 04090003 lb zero,64(s2) + 7206: 0100 addi s0,sp,128 + 7208: 0300 addi s0,sp,384 + 720a: 9d04 0x9d04 + 720c: 0302 c.slli64 t1 + 720e: 0900 addi s0,sp,144 + 7210: 0000 unimp + 7212: 0001 nop + 7214: 029d0403 lb s0,41(s10) + 7218: 00090003 lb zero,0(s2) + 721c: 0100 addi s0,sp,128 + 721e: 0300 addi s0,sp,384 + 7220: 9f04 0x9f04 + 7222: 0302 c.slli64 t1 + 7224: 0900 addi s0,sp,144 + 7226: 0010 0x10 + 7228: 0001 nop + 722a: 02a90403 lb s0,42(s2) + 722e: 1c090003 lb zero,448(s2) + 7232: 0100 addi s0,sp,128 + 7234: 0300 addi s0,sp,384 + 7236: a904 fsd fs1,16(a0) + 7238: 0302 c.slli64 t1 + 723a: 0900 addi s0,sp,144 + 723c: 0000 unimp + 723e: 0001 nop + 7240: 02a90403 lb s0,42(s2) + 7244: 00090003 lb zero,0(s2) + 7248: 0100 addi s0,sp,128 + 724a: 0300 addi s0,sp,384 + 724c: a904 fsd fs1,16(a0) + 724e: 0302 c.slli64 t1 + 7250: 0900 addi s0,sp,144 + 7252: 0000 unimp + 7254: 0001 nop + 7256: 02a20403 lb s0,42(tp) # 2a <_start-0x7fffffd6> + 725a: 14090003 lb zero,320(s2) + 725e: 0100 addi s0,sp,128 + 7260: 0300 addi s0,sp,384 + 7262: a204 fsd fs1,0(a2) + 7264: 0302 c.slli64 t1 + 7266: 0900 addi s0,sp,144 + 7268: 0000 unimp + 726a: 0001 nop + 726c: 02a20403 lb s0,42(tp) # 2a <_start-0x7fffffd6> + 7270: 04090003 lb zero,64(s2) + 7274: 0100 addi s0,sp,128 + 7276: 0300 addi s0,sp,384 + 7278: ab04 fsd fs1,16(a4) + 727a: 0302 c.slli64 t1 + 727c: 0900 addi s0,sp,144 + 727e: 0004 0x4 + 7280: 0001 nop + 7282: 02ab0403 lb s0,42(s6) + 7286: 00090003 lb zero,0(s2) + 728a: 0100 addi s0,sp,128 + 728c: 0300 addi s0,sp,384 + 728e: ab04 fsd fs1,16(a4) + 7290: 0302 c.slli64 t1 + 7292: 0900 addi s0,sp,144 + 7294: 0000 unimp + 7296: 0001 nop + 7298: 02ab0403 lb s0,42(s6) + 729c: 00090003 lb zero,0(s2) + 72a0: 0100 addi s0,sp,128 + 72a2: 0300 addi s0,sp,384 + 72a4: ab04 fsd fs1,16(a4) + 72a6: 0302 c.slli64 t1 + 72a8: 0900 addi s0,sp,144 + 72aa: 0000 unimp + 72ac: 0001 nop + 72ae: 02ab0403 lb s0,42(s6) + 72b2: 04090003 lb zero,64(s2) + 72b6: 0100 addi s0,sp,128 + 72b8: 0300 addi s0,sp,384 + 72ba: ab04 fsd fs1,16(a4) + 72bc: 0302 c.slli64 t1 + 72be: 0900 addi s0,sp,144 + 72c0: 0000 unimp + 72c2: 0001 nop + 72c4: 02ab0403 lb s0,42(s6) + 72c8: 04090003 lb zero,64(s2) + 72cc: 0100 addi s0,sp,128 + 72ce: 0300 addi s0,sp,384 + 72d0: ab04 fsd fs1,16(a4) + 72d2: 0302 c.slli64 t1 + 72d4: 0900 addi s0,sp,144 + 72d6: 0008 0x8 + 72d8: 0001 nop + 72da: 02ab0403 lb s0,42(s6) + 72de: 04090003 lb zero,64(s2) + 72e2: 0100 addi s0,sp,128 + 72e4: 0300 addi s0,sp,384 + 72e6: ad04 fsd fs1,24(a0) + 72e8: 0602 c.slli64 a2 + 72ea: 08090003 lb zero,128(s2) + 72ee: 0100 addi s0,sp,128 + 72f0: 0300 addi s0,sp,384 + 72f2: b204 fsd fs1,32(a2) + 72f4: 0302 c.slli64 t1 + 72f6: 0900 addi s0,sp,144 + 72f8: 0008 0x8 + 72fa: 0001 nop + 72fc: 02b20403 lb s0,43(tp) # 2b <_start-0x7fffffd5> + 7300: 0306 slli t1,t1,0x1 + 7302: 0900 addi s0,sp,144 + 7304: 0004 0x4 + 7306: 0001 nop + 7308: 02b20403 lb s0,43(tp) # 2b <_start-0x7fffffd5> + 730c: 04090003 lb zero,64(s2) + 7310: 0100 addi s0,sp,128 + 7312: 0300 addi s0,sp,384 + 7314: b204 fsd fs1,32(a2) + 7316: 0302 c.slli64 t1 + 7318: 0900 addi s0,sp,144 + 731a: 0004 0x4 + 731c: 0001 nop + 731e: 02b20403 lb s0,43(tp) # 2b <_start-0x7fffffd5> + 7322: 04090003 lb zero,64(s2) + 7326: 0100 addi s0,sp,128 + 7328: 0300 addi s0,sp,384 + 732a: b304 fsd fs1,32(a4) + 732c: 0602 c.slli64 a2 + 732e: 04090003 lb zero,64(s2) + 7332: 0100 addi s0,sp,128 + 7334: 0300 addi s0,sp,384 + 7336: b804 fsd fs1,48(s0) + 7338: 0602 c.slli64 a2 + 733a: 08090003 lb zero,128(s2) + 733e: 0100 addi s0,sp,128 + 7340: 0300 addi s0,sp,384 + 7342: b804 fsd fs1,48(s0) + 7344: 0302 c.slli64 t1 + 7346: 0900 addi s0,sp,144 + 7348: 0010 0x10 + 734a: 0001 nop + 734c: 02b80403 lb s0,43(a6) + 7350: 04090003 lb zero,64(s2) + 7354: 0100 addi s0,sp,128 + 7356: 0300 addi s0,sp,384 + 7358: b804 fsd fs1,48(s0) + 735a: 0302 c.slli64 t1 + 735c: 0900 addi s0,sp,144 + 735e: 0004 0x4 + 7360: 0001 nop + 7362: 02b80403 lb s0,43(a6) + 7366: 04090003 lb zero,64(s2) + 736a: 0100 addi s0,sp,128 + 736c: 0300 addi s0,sp,384 + 736e: b804 fsd fs1,48(s0) + 7370: 0302 c.slli64 t1 + 7372: 0900 addi s0,sp,144 + 7374: 0000 unimp + 7376: 0001 nop + 7378: 038e0403 lb s0,56(t3) + 737c: 0306 slli t1,t1,0x1 + 737e: 097f 0x97f + 7380: 0000 unimp + 7382: 0001 nop + 7384: 038e0403 lb s0,56(t3) + 7388: 04090103 lb sp,64(s2) + 738c: 0100 addi s0,sp,128 + 738e: 0300 addi s0,sp,384 + 7390: ac04 fsd fs1,24(s0) + 7392: 0602 c.slli64 a2 + 7394: 04090003 lb zero,64(s2) + 7398: 0100 addi s0,sp,128 + 739a: 0c090003 lb zero,192(s2) + 739e: 0100 addi s0,sp,128 + 73a0: 08090003 lb zero,128(s2) + 73a4: 0100 addi s0,sp,128 + 73a6: 0300 addi s0,sp,384 + 73a8: a004 fsd fs1,0(s0) + 73aa: 0302 c.slli64 t1 + 73ac: 0900 addi s0,sp,144 + 73ae: 0014 0x14 + 73b0: 0001 nop + 73b2: 02cd0403 lb s0,44(s10) + 73b6: 0c090003 lb zero,192(s2) + 73ba: 0100 addi s0,sp,128 + 73bc: 0300 addi s0,sp,384 + 73be: cd04 sw s1,24(a0) + 73c0: 0302 c.slli64 t1 + 73c2: 0900 addi s0,sp,144 + 73c4: 0000 unimp + 73c6: 0001 nop + 73c8: 02cd0403 lb s0,44(s10) + 73cc: 00090003 lb zero,0(s2) + 73d0: 0100 addi s0,sp,128 + 73d2: 0300 addi s0,sp,384 + 73d4: cd04 sw s1,24(a0) + 73d6: 0302 c.slli64 t1 + 73d8: 0900 addi s0,sp,144 + 73da: 0000 unimp + 73dc: 0001 nop + 73de: 02cd0403 lb s0,44(s10) + 73e2: 10090003 lb zero,256(s2) + 73e6: 0100 addi s0,sp,128 + 73e8: 0300 addi s0,sp,384 + 73ea: c604 sw s1,8(a2) + 73ec: 0302 c.slli64 t1 + 73ee: 0900 addi s0,sp,144 + 73f0: 0004 0x4 + 73f2: 0001 nop + 73f4: 02c60403 lb s0,44(a2) + 73f8: 10090003 lb zero,256(s2) + 73fc: 0100 addi s0,sp,128 + 73fe: 0300 addi s0,sp,384 + 7400: d004 sw s1,32(s0) + 7402: 0302 c.slli64 t1 + 7404: 0900 addi s0,sp,144 + 7406: 000c 0xc + 7408: 0001 nop + 740a: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> + 740e: 00090003 lb zero,0(s2) + 7412: 0100 addi s0,sp,128 + 7414: 0300 addi s0,sp,384 + 7416: d004 sw s1,32(s0) + 7418: 0302 c.slli64 t1 + 741a: 0900 addi s0,sp,144 + 741c: 0000 unimp + 741e: 0001 nop + 7420: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> + 7424: 00090003 lb zero,0(s2) + 7428: 0100 addi s0,sp,128 + 742a: 0300 addi s0,sp,384 + 742c: d004 sw s1,32(s0) + 742e: 0302 c.slli64 t1 + 7430: 0900 addi s0,sp,144 + 7432: 0000 unimp + 7434: 0001 nop + 7436: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> + 743a: 00090003 lb zero,0(s2) + 743e: 0100 addi s0,sp,128 + 7440: 0300 addi s0,sp,384 + 7442: d004 sw s1,32(s0) + 7444: 0302 c.slli64 t1 + 7446: 0900 addi s0,sp,144 + 7448: 0000 unimp + 744a: 0001 nop + 744c: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> + 7450: 04090003 lb zero,64(s2) + 7454: 0100 addi s0,sp,128 + 7456: 0300 addi s0,sp,384 + 7458: d004 sw s1,32(s0) + 745a: 0302 c.slli64 t1 + 745c: 0900 addi s0,sp,144 + 745e: 0000 unimp + 7460: 0001 nop + 7462: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> + 7466: 00090003 lb zero,0(s2) + 746a: 0100 addi s0,sp,128 + 746c: 0300 addi s0,sp,384 + 746e: d204 sw s1,32(a2) + 7470: 0302 c.slli64 t1 + 7472: 0900 addi s0,sp,144 + 7474: 0008 0x8 + 7476: 0001 nop + 7478: 02d50403 lb s0,45(a0) + 747c: 04090003 lb zero,64(s2) + 7480: 0100 addi s0,sp,128 + 7482: 0306 slli t1,t1,0x1 7484: 0900 addi s0,sp,144 - 7486: 0000 unimp + 7486: 000c 0xc 7488: 0001 nop - 748a: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 748e: 00090003 lb zero,0(s2) - 7492: 0100 addi s0,sp,128 - 7494: 0300 addi s0,sp,384 - 7496: d004 sw s1,32(s0) - 7498: 0302 c.slli64 t1 - 749a: 0900 addi s0,sp,144 - 749c: 0000 unimp - 749e: 0001 nop - 74a0: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 74a4: 04090003 lb zero,64(s2) - 74a8: 0100 addi s0,sp,128 - 74aa: 0300 addi s0,sp,384 - 74ac: d004 sw s1,32(s0) - 74ae: 0302 c.slli64 t1 - 74b0: 0900 addi s0,sp,144 - 74b2: 0000 unimp - 74b4: 0001 nop - 74b6: 02d00403 lb s0,45(zero) # 2d <_start-0x7fffffd3> - 74ba: 00090003 lb zero,0(s2) - 74be: 0100 addi s0,sp,128 - 74c0: 0300 addi s0,sp,384 - 74c2: d204 sw s1,32(a2) - 74c4: 0302 c.slli64 t1 - 74c6: 0900 addi s0,sp,144 - 74c8: 0008 0x8 - 74ca: 0001 nop - 74cc: 02d50403 lb s0,45(a0) - 74d0: 04090003 lb zero,64(s2) - 74d4: 0100 addi s0,sp,128 - 74d6: 0306 slli t1,t1,0x1 - 74d8: 0900 addi s0,sp,144 - 74da: 000c 0xc - 74dc: 0001 nop - 74de: 02da0403 lb s0,45(s4) - 74e2: 0306 slli t1,t1,0x1 - 74e4: 0900 addi s0,sp,144 - 74e6: 000c 0xc - 74e8: 0001 nop - 74ea: 02da0403 lb s0,45(s4) - 74ee: 14090003 lb zero,320(s2) - 74f2: 0100 addi s0,sp,128 - 74f4: 0300 addi s0,sp,384 - 74f6: da04 sw s1,48(a2) - 74f8: 0302 c.slli64 t1 - 74fa: 0900 addi s0,sp,144 - 74fc: 0000 unimp - 74fe: 0001 nop - 7500: 02d40403 lb s0,45(s0) - 7504: 1c090003 lb zero,448(s2) - 7508: 0100 addi s0,sp,128 - 750a: 0300 addi s0,sp,384 - 750c: d404 sw s1,40(s0) - 750e: 0302 c.slli64 t1 - 7510: 0900 addi s0,sp,144 - 7512: 0014 0x14 - 7514: 0001 nop - 7516: 02d70403 lb s0,45(a4) - 751a: 0306 slli t1,t1,0x1 - 751c: 0900 addi s0,sp,144 - 751e: 0004 0x4 - 7520: 0001 nop - 7522: 02d70403 lb s0,45(a4) - 7526: 0306 slli t1,t1,0x1 - 7528: 0900 addi s0,sp,144 - 752a: 0014 0x14 - 752c: 0001 nop - 752e: 02d70403 lb s0,45(a4) - 7532: 0c090003 lb zero,192(s2) - 7536: 0100 addi s0,sp,128 - 7538: 0300 addi s0,sp,384 - 753a: db04 sw s1,48(a4) - 753c: 0302 c.slli64 t1 - 753e: 0900 addi s0,sp,144 - 7540: 000c 0xc - 7542: 0001 nop - 7544: 02de0403 lb s0,45(t3) - 7548: 0306 slli t1,t1,0x1 - 754a: 0900 addi s0,sp,144 - 754c: 0008 0x8 - 754e: 0001 nop - 7550: 02de0403 lb s0,45(t3) - 7554: 0306 slli t1,t1,0x1 - 7556: 0900 addi s0,sp,144 - 7558: 0018 0x18 - 755a: 0001 nop - 755c: 02e00403 lb s0,46(zero) # 2e <_start-0x7fffffd2> - 7560: 0306 slli t1,t1,0x1 - 7562: 0900 addi s0,sp,144 - 7564: 0008 0x8 - 7566: 0001 nop - 7568: 02dd0403 lb s0,45(s10) + 748a: 02da0403 lb s0,45(s4) + 748e: 0306 slli t1,t1,0x1 + 7490: 0900 addi s0,sp,144 + 7492: 000c 0xc + 7494: 0001 nop + 7496: 02da0403 lb s0,45(s4) + 749a: 14090003 lb zero,320(s2) + 749e: 0100 addi s0,sp,128 + 74a0: 0300 addi s0,sp,384 + 74a2: da04 sw s1,48(a2) + 74a4: 0302 c.slli64 t1 + 74a6: 0900 addi s0,sp,144 + 74a8: 0000 unimp + 74aa: 0001 nop + 74ac: 02d40403 lb s0,45(s0) + 74b0: 1c090003 lb zero,448(s2) + 74b4: 0100 addi s0,sp,128 + 74b6: 0300 addi s0,sp,384 + 74b8: d404 sw s1,40(s0) + 74ba: 0302 c.slli64 t1 + 74bc: 0900 addi s0,sp,144 + 74be: 0014 0x14 + 74c0: 0001 nop + 74c2: 02d70403 lb s0,45(a4) + 74c6: 0306 slli t1,t1,0x1 + 74c8: 0900 addi s0,sp,144 + 74ca: 0004 0x4 + 74cc: 0001 nop + 74ce: 02d70403 lb s0,45(a4) + 74d2: 0306 slli t1,t1,0x1 + 74d4: 0900 addi s0,sp,144 + 74d6: 0014 0x14 + 74d8: 0001 nop + 74da: 02d70403 lb s0,45(a4) + 74de: 0c090003 lb zero,192(s2) + 74e2: 0100 addi s0,sp,128 + 74e4: 0300 addi s0,sp,384 + 74e6: db04 sw s1,48(a4) + 74e8: 0302 c.slli64 t1 + 74ea: 0900 addi s0,sp,144 + 74ec: 000c 0xc + 74ee: 0001 nop + 74f0: 02de0403 lb s0,45(t3) + 74f4: 0306 slli t1,t1,0x1 + 74f6: 0900 addi s0,sp,144 + 74f8: 0008 0x8 + 74fa: 0001 nop + 74fc: 02de0403 lb s0,45(t3) + 7500: 0306 slli t1,t1,0x1 + 7502: 0900 addi s0,sp,144 + 7504: 0018 0x18 + 7506: 0001 nop + 7508: 02e00403 lb s0,46(zero) # 2e <_start-0x7fffffd2> + 750c: 0306 slli t1,t1,0x1 + 750e: 0900 addi s0,sp,144 + 7510: 0008 0x8 + 7512: 0001 nop + 7514: 02dd0403 lb s0,45(s10) + 7518: 0306 slli t1,t1,0x1 + 751a: 0900 addi s0,sp,144 + 751c: 0008 0x8 + 751e: 0001 nop + 7520: 02dd0403 lb s0,45(s10) + 7524: 20090003 lb zero,512(s2) + 7528: 0100 addi s0,sp,128 + 752a: 0300 addi s0,sp,384 + 752c: e104 fsw fs1,0(a0) + 752e: 0302 c.slli64 t1 + 7530: 0900 addi s0,sp,144 + 7532: 0008 0x8 + 7534: 0001 nop + 7536: 02e10403 lb s0,46(sp) + 753a: 0c090003 lb zero,192(s2) + 753e: 0100 addi s0,sp,128 + 7540: 0300 addi s0,sp,384 + 7542: e004 fsw fs1,0(s0) + 7544: 0302 c.slli64 t1 + 7546: 0900 addi s0,sp,144 + 7548: 0004 0x4 + 754a: 0001 nop + 754c: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> + 7550: 04090003 lb zero,64(s2) + 7554: 0100 addi s0,sp,128 + 7556: 0300 addi s0,sp,384 + 7558: e204 fsw fs1,0(a2) + 755a: 0302 c.slli64 t1 + 755c: 0900 addi s0,sp,144 + 755e: 0000 unimp + 7560: 0001 nop + 7562: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> + 7566: 00090003 lb zero,0(s2) + 756a: 0100 addi s0,sp,128 756c: 0306 slli t1,t1,0x1 756e: 0900 addi s0,sp,144 - 7570: 0008 0x8 - 7572: 0001 nop - 7574: 02dd0403 lb s0,45(s10) - 7578: 20090003 lb zero,512(s2) - 757c: 0100 addi s0,sp,128 - 757e: 0300 addi s0,sp,384 - 7580: e104 fsw fs1,0(a0) - 7582: 0302 c.slli64 t1 - 7584: 0900 addi s0,sp,144 - 7586: 0008 0x8 - 7588: 0001 nop - 758a: 02e10403 lb s0,46(sp) - 758e: 0c090003 lb zero,192(s2) - 7592: 0100 addi s0,sp,128 - 7594: 0300 addi s0,sp,384 - 7596: e004 fsw fs1,0(s0) - 7598: 0302 c.slli64 t1 - 759a: 0900 addi s0,sp,144 - 759c: 0004 0x4 - 759e: 0001 nop - 75a0: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> - 75a4: 04090003 lb zero,64(s2) + 7570: 000c 0xc + 7572: 0601 addi a2,a2,0 + 7574: 04090003 lb zero,64(s2) + 7578: 0100 addi s0,sp,128 + 757a: 00090003 lb zero,0(s2) + 757e: 0100 addi s0,sp,128 + 7580: 00090003 lb zero,0(s2) + 7584: 0100 addi s0,sp,128 + 7586: 00090003 lb zero,0(s2) + 758a: 0100 addi s0,sp,128 + 758c: 00090003 lb zero,0(s2) + 7590: 0100 addi s0,sp,128 + 7592: 0c090003 lb zero,192(s2) + 7596: 0100 addi s0,sp,128 + 7598: 00090003 lb zero,0(s2) + 759c: 0100 addi s0,sp,128 + 759e: 04090003 lb zero,64(s2) + 75a2: 0100 addi s0,sp,128 + 75a4: 08090003 lb zero,128(s2) 75a8: 0100 addi s0,sp,128 - 75aa: 0300 addi s0,sp,384 - 75ac: e204 fsw fs1,0(a2) - 75ae: 0302 c.slli64 t1 - 75b0: 0900 addi s0,sp,144 - 75b2: 0000 unimp - 75b4: 0001 nop - 75b6: 02e20403 lb s0,46(tp) # 2e <_start-0x7fffffd2> - 75ba: 00090003 lb zero,0(s2) - 75be: 0100 addi s0,sp,128 - 75c0: 0306 slli t1,t1,0x1 + 75aa: 04090003 lb zero,64(s2) + 75ae: 0100 addi s0,sp,128 + 75b0: 0300 addi s0,sp,384 + 75b2: e704 fsw fs1,8(a4) + 75b4: 0602 c.slli64 a2 + 75b6: 08090003 lb zero,128(s2) + 75ba: 0100 addi s0,sp,128 + 75bc: 0300 addi s0,sp,384 + 75be: ec04 fsw fs1,24(s0) + 75c0: 0302 c.slli64 t1 75c2: 0900 addi s0,sp,144 - 75c4: 000c 0xc - 75c6: 0601 addi a2,a2,0 - 75c8: 04090003 lb zero,64(s2) - 75cc: 0100 addi s0,sp,128 - 75ce: 00090003 lb zero,0(s2) - 75d2: 0100 addi s0,sp,128 - 75d4: 00090003 lb zero,0(s2) - 75d8: 0100 addi s0,sp,128 - 75da: 00090003 lb zero,0(s2) - 75de: 0100 addi s0,sp,128 - 75e0: 00090003 lb zero,0(s2) - 75e4: 0100 addi s0,sp,128 - 75e6: 0c090003 lb zero,192(s2) - 75ea: 0100 addi s0,sp,128 - 75ec: 00090003 lb zero,0(s2) - 75f0: 0100 addi s0,sp,128 - 75f2: 04090003 lb zero,64(s2) - 75f6: 0100 addi s0,sp,128 - 75f8: 08090003 lb zero,128(s2) - 75fc: 0100 addi s0,sp,128 - 75fe: 04090003 lb zero,64(s2) - 7602: 0100 addi s0,sp,128 - 7604: 0300 addi s0,sp,384 - 7606: e704 fsw fs1,8(a4) - 7608: 0602 c.slli64 a2 - 760a: 08090003 lb zero,128(s2) - 760e: 0100 addi s0,sp,128 - 7610: 0300 addi s0,sp,384 - 7612: ec04 fsw fs1,24(s0) - 7614: 0302 c.slli64 t1 - 7616: 0900 addi s0,sp,144 - 7618: 0008 0x8 - 761a: 0001 nop - 761c: 02ec0403 lb s0,46(s8) - 7620: 0306 slli t1,t1,0x1 - 7622: 0900 addi s0,sp,144 - 7624: 0004 0x4 - 7626: 0001 nop - 7628: 02ec0403 lb s0,46(s8) - 762c: 0c090003 lb zero,192(s2) - 7630: 0100 addi s0,sp,128 - 7632: 0300 addi s0,sp,384 - 7634: ec04 fsw fs1,24(s0) - 7636: 0302 c.slli64 t1 - 7638: 0900 addi s0,sp,144 - 763a: 0004 0x4 - 763c: 0001 nop - 763e: 02ec0403 lb s0,46(s8) - 7642: 04090003 lb zero,64(s2) - 7646: 0100 addi s0,sp,128 - 7648: 0300 addi s0,sp,384 - 764a: ed04 fsw fs1,24(a0) - 764c: 0602 c.slli64 a2 - 764e: 04090003 lb zero,64(s2) - 7652: 0100 addi s0,sp,128 - 7654: 0300 addi s0,sp,384 - 7656: f204 fsw fs1,32(a2) - 7658: 0602 c.slli64 a2 - 765a: 08090003 lb zero,128(s2) - 765e: 0100 addi s0,sp,128 - 7660: 0300 addi s0,sp,384 - 7662: f204 fsw fs1,32(a2) - 7664: 0302 c.slli64 t1 - 7666: 0900 addi s0,sp,144 - 7668: 0018 0x18 - 766a: 0001 nop - 766c: 02f20403 lb s0,47(tp) # 2f <_start-0x7fffffd1> - 7670: 00090003 lb zero,0(s2) - 7674: 0100 addi s0,sp,128 - 7676: 0300 addi s0,sp,384 - 7678: f204 fsw fs1,32(a2) - 767a: 0302 c.slli64 t1 - 767c: 0900 addi s0,sp,144 - 767e: 0004 0x4 - 7680: 0001 nop - 7682: 02f20403 lb s0,47(tp) # 2f <_start-0x7fffffd1> - 7686: 04090003 lb zero,64(s2) - 768a: 0100 addi s0,sp,128 - 768c: 0300 addi s0,sp,384 - 768e: 8f04 0x8f04 - 7690: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7694: 0000 unimp - 7696: 0001 nop - 7698: 04df0403 lb s0,77(t5) - 769c: 0c090003 lb zero,192(s2) - 76a0: 0100 addi s0,sp,128 - 76a2: 0300 addi s0,sp,384 - 76a4: df04 sw s1,56(a4) - 76a6: 0304 addi s1,sp,384 - 76a8: 0900 addi s0,sp,144 - 76aa: 0000 unimp - 76ac: 0001 nop - 76ae: 029e0403 lb s0,41(t3) - 76b2: 14090003 lb zero,320(s2) - 76b6: 0100 addi s0,sp,128 - 76b8: 0300 addi s0,sp,384 - 76ba: f304 fsw fs1,32(a4) - 76bc: 0302 c.slli64 t1 - 76be: 0900 addi s0,sp,144 - 76c0: 0010 0x10 - 76c2: 0001 nop - 76c4: 02f30403 lb s0,47(t1) - 76c8: 04090003 lb zero,64(s2) - 76cc: 0100 addi s0,sp,128 - 76ce: 0300 addi s0,sp,384 - 76d0: f304 fsw fs1,32(a4) - 76d2: 0302 c.slli64 t1 - 76d4: 0900 addi s0,sp,144 - 76d6: 0000 unimp - 76d8: 0001 nop - 76da: 02f30403 lb s0,47(t1) - 76de: 00090003 lb zero,0(s2) - 76e2: 0100 addi s0,sp,128 - 76e4: 0300 addi s0,sp,384 - 76e6: f504 fsw fs1,40(a0) - 76e8: 0302 c.slli64 t1 - 76ea: 0900 addi s0,sp,144 - 76ec: 0004 0x4 - 76ee: 0001 nop - 76f0: 03980403 lb s0,57(a6) - 76f4: 1c090003 lb zero,448(s2) - 76f8: 0100 addi s0,sp,128 - 76fa: 0300 addi s0,sp,384 - 76fc: 9804 0x9804 - 76fe: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7702: 0000 unimp - 7704: 0001 nop - 7706: 03980403 lb s0,57(a6) - 770a: 00090003 lb zero,0(s2) - 770e: 0100 addi s0,sp,128 - 7710: 0300 addi s0,sp,384 - 7712: 9804 0x9804 - 7714: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7718: 0000 unimp - 771a: 0001 nop - 771c: 03980403 lb s0,57(a6) - 7720: 10090003 lb zero,256(s2) - 7724: 0100 addi s0,sp,128 - 7726: 0300 addi s0,sp,384 - 7728: f004 fsw fs1,32(s0) - 772a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 772e: 0004 0x4 - 7730: 0001 nop - 7732: 03f00403 lb s0,63(zero) # 3f <_start-0x7fffffc1> - 7736: 00090003 lb zero,0(s2) - 773a: 0100 addi s0,sp,128 - 773c: 0300 addi s0,sp,384 - 773e: f804 fsw fs1,48(s0) - 7740: 0302 c.slli64 t1 - 7742: 0900 addi s0,sp,144 - 7744: 0008 0x8 - 7746: 0001 nop - 7748: 02f80403 lb s0,47(a6) - 774c: 00090003 lb zero,0(s2) - 7750: 0100 addi s0,sp,128 - 7752: 0300 addi s0,sp,384 - 7754: f804 fsw fs1,48(s0) - 7756: 0302 c.slli64 t1 - 7758: 0900 addi s0,sp,144 - 775a: 0004 0x4 - 775c: 0001 nop - 775e: 03810403 lb s0,56(sp) - 7762: 04090003 lb zero,64(s2) - 7766: 0100 addi s0,sp,128 - 7768: 0300 addi s0,sp,384 - 776a: 8104 0x8104 - 776c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7770: 0000 unimp - 7772: 0001 nop - 7774: 03810403 lb s0,56(sp) - 7778: 00090003 lb zero,0(s2) - 777c: 0100 addi s0,sp,128 - 777e: 0300 addi s0,sp,384 - 7780: 8104 0x8104 - 7782: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7786: 0000 unimp - 7788: 0001 nop - 778a: 03810403 lb s0,56(sp) - 778e: 00090003 lb zero,0(s2) - 7792: 0100 addi s0,sp,128 - 7794: 0300 addi s0,sp,384 - 7796: 8104 0x8104 - 7798: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 779c: 0004 0x4 - 779e: 0001 nop - 77a0: 03810403 lb s0,56(sp) - 77a4: 00090003 lb zero,0(s2) - 77a8: 0100 addi s0,sp,128 - 77aa: 0300 addi s0,sp,384 - 77ac: 8104 0x8104 - 77ae: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 77b2: 0004 0x4 - 77b4: 0001 nop - 77b6: 03810403 lb s0,56(sp) - 77ba: 08090003 lb zero,128(s2) - 77be: 0100 addi s0,sp,128 - 77c0: 0300 addi s0,sp,384 - 77c2: 8104 0x8104 - 77c4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 77c8: 0004 0x4 - 77ca: 0001 nop - 77cc: 03830403 lb s0,56(t1) - 77d0: 0306 slli t1,t1,0x1 - 77d2: 0900 addi s0,sp,144 - 77d4: 0008 0x8 - 77d6: 0001 nop - 77d8: 03880403 lb s0,56(a6) - 77dc: 08090003 lb zero,128(s2) - 77e0: 0100 addi s0,sp,128 - 77e2: 0300 addi s0,sp,384 - 77e4: 8804 0x8804 - 77e6: 00030603 lb a2,0(t1) - 77ea: 0409 addi s0,s0,2 - 77ec: 0100 addi s0,sp,128 - 77ee: 0300 addi s0,sp,384 - 77f0: 8804 0x8804 - 77f2: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 77f6: 0004 0x4 - 77f8: 0001 nop - 77fa: 03880403 lb s0,56(a6) - 77fe: 04090003 lb zero,64(s2) - 7802: 0100 addi s0,sp,128 - 7804: 0300 addi s0,sp,384 - 7806: 8804 0x8804 - 7808: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 780c: 0004 0x4 - 780e: 0001 nop - 7810: 03890403 lb s0,56(s2) - 7814: 0306 slli t1,t1,0x1 + 75c4: 0008 0x8 + 75c6: 0001 nop + 75c8: 02ec0403 lb s0,46(s8) + 75cc: 0306 slli t1,t1,0x1 + 75ce: 0900 addi s0,sp,144 + 75d0: 0004 0x4 + 75d2: 0001 nop + 75d4: 02ec0403 lb s0,46(s8) + 75d8: 0c090003 lb zero,192(s2) + 75dc: 0100 addi s0,sp,128 + 75de: 0300 addi s0,sp,384 + 75e0: ec04 fsw fs1,24(s0) + 75e2: 0302 c.slli64 t1 + 75e4: 0900 addi s0,sp,144 + 75e6: 0004 0x4 + 75e8: 0001 nop + 75ea: 02ec0403 lb s0,46(s8) + 75ee: 04090003 lb zero,64(s2) + 75f2: 0100 addi s0,sp,128 + 75f4: 0300 addi s0,sp,384 + 75f6: ed04 fsw fs1,24(a0) + 75f8: 0602 c.slli64 a2 + 75fa: 04090003 lb zero,64(s2) + 75fe: 0100 addi s0,sp,128 + 7600: 0300 addi s0,sp,384 + 7602: f204 fsw fs1,32(a2) + 7604: 0602 c.slli64 a2 + 7606: 08090003 lb zero,128(s2) + 760a: 0100 addi s0,sp,128 + 760c: 0300 addi s0,sp,384 + 760e: f204 fsw fs1,32(a2) + 7610: 0302 c.slli64 t1 + 7612: 0900 addi s0,sp,144 + 7614: 0018 0x18 + 7616: 0001 nop + 7618: 02f20403 lb s0,47(tp) # 2f <_start-0x7fffffd1> + 761c: 00090003 lb zero,0(s2) + 7620: 0100 addi s0,sp,128 + 7622: 0300 addi s0,sp,384 + 7624: f204 fsw fs1,32(a2) + 7626: 0302 c.slli64 t1 + 7628: 0900 addi s0,sp,144 + 762a: 0004 0x4 + 762c: 0001 nop + 762e: 02f20403 lb s0,47(tp) # 2f <_start-0x7fffffd1> + 7632: 04090003 lb zero,64(s2) + 7636: 0100 addi s0,sp,128 + 7638: 0300 addi s0,sp,384 + 763a: 8f04 0x8f04 + 763c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7640: 0000 unimp + 7642: 0001 nop + 7644: 04df0403 lb s0,77(t5) + 7648: 0c090003 lb zero,192(s2) + 764c: 0100 addi s0,sp,128 + 764e: 0300 addi s0,sp,384 + 7650: df04 sw s1,56(a4) + 7652: 0304 addi s1,sp,384 + 7654: 0900 addi s0,sp,144 + 7656: 0000 unimp + 7658: 0001 nop + 765a: 029e0403 lb s0,41(t3) + 765e: 14090003 lb zero,320(s2) + 7662: 0100 addi s0,sp,128 + 7664: 0300 addi s0,sp,384 + 7666: f304 fsw fs1,32(a4) + 7668: 0302 c.slli64 t1 + 766a: 0900 addi s0,sp,144 + 766c: 0010 0x10 + 766e: 0001 nop + 7670: 02f30403 lb s0,47(t1) + 7674: 04090003 lb zero,64(s2) + 7678: 0100 addi s0,sp,128 + 767a: 0300 addi s0,sp,384 + 767c: f304 fsw fs1,32(a4) + 767e: 0302 c.slli64 t1 + 7680: 0900 addi s0,sp,144 + 7682: 0000 unimp + 7684: 0001 nop + 7686: 02f30403 lb s0,47(t1) + 768a: 00090003 lb zero,0(s2) + 768e: 0100 addi s0,sp,128 + 7690: 0300 addi s0,sp,384 + 7692: f504 fsw fs1,40(a0) + 7694: 0302 c.slli64 t1 + 7696: 0900 addi s0,sp,144 + 7698: 0004 0x4 + 769a: 0001 nop + 769c: 03980403 lb s0,57(a6) + 76a0: 1c090003 lb zero,448(s2) + 76a4: 0100 addi s0,sp,128 + 76a6: 0300 addi s0,sp,384 + 76a8: 9804 0x9804 + 76aa: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 76ae: 0000 unimp + 76b0: 0001 nop + 76b2: 03980403 lb s0,57(a6) + 76b6: 00090003 lb zero,0(s2) + 76ba: 0100 addi s0,sp,128 + 76bc: 0300 addi s0,sp,384 + 76be: 9804 0x9804 + 76c0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 76c4: 0000 unimp + 76c6: 0001 nop + 76c8: 03980403 lb s0,57(a6) + 76cc: 10090003 lb zero,256(s2) + 76d0: 0100 addi s0,sp,128 + 76d2: 0300 addi s0,sp,384 + 76d4: f004 fsw fs1,32(s0) + 76d6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 76da: 0004 0x4 + 76dc: 0001 nop + 76de: 03f00403 lb s0,63(zero) # 3f <_start-0x7fffffc1> + 76e2: 00090003 lb zero,0(s2) + 76e6: 0100 addi s0,sp,128 + 76e8: 0300 addi s0,sp,384 + 76ea: f804 fsw fs1,48(s0) + 76ec: 0302 c.slli64 t1 + 76ee: 0900 addi s0,sp,144 + 76f0: 0008 0x8 + 76f2: 0001 nop + 76f4: 02f80403 lb s0,47(a6) + 76f8: 00090003 lb zero,0(s2) + 76fc: 0100 addi s0,sp,128 + 76fe: 0300 addi s0,sp,384 + 7700: f804 fsw fs1,48(s0) + 7702: 0302 c.slli64 t1 + 7704: 0900 addi s0,sp,144 + 7706: 0004 0x4 + 7708: 0001 nop + 770a: 03810403 lb s0,56(sp) + 770e: 04090003 lb zero,64(s2) + 7712: 0100 addi s0,sp,128 + 7714: 0300 addi s0,sp,384 + 7716: 8104 0x8104 + 7718: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 771c: 0000 unimp + 771e: 0001 nop + 7720: 03810403 lb s0,56(sp) + 7724: 00090003 lb zero,0(s2) + 7728: 0100 addi s0,sp,128 + 772a: 0300 addi s0,sp,384 + 772c: 8104 0x8104 + 772e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7732: 0000 unimp + 7734: 0001 nop + 7736: 03810403 lb s0,56(sp) + 773a: 00090003 lb zero,0(s2) + 773e: 0100 addi s0,sp,128 + 7740: 0300 addi s0,sp,384 + 7742: 8104 0x8104 + 7744: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7748: 0004 0x4 + 774a: 0001 nop + 774c: 03810403 lb s0,56(sp) + 7750: 00090003 lb zero,0(s2) + 7754: 0100 addi s0,sp,128 + 7756: 0300 addi s0,sp,384 + 7758: 8104 0x8104 + 775a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 775e: 0004 0x4 + 7760: 0001 nop + 7762: 03810403 lb s0,56(sp) + 7766: 08090003 lb zero,128(s2) + 776a: 0100 addi s0,sp,128 + 776c: 0300 addi s0,sp,384 + 776e: 8104 0x8104 + 7770: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7774: 0004 0x4 + 7776: 0001 nop + 7778: 03830403 lb s0,56(t1) + 777c: 0306 slli t1,t1,0x1 + 777e: 0900 addi s0,sp,144 + 7780: 0008 0x8 + 7782: 0001 nop + 7784: 03880403 lb s0,56(a6) + 7788: 08090003 lb zero,128(s2) + 778c: 0100 addi s0,sp,128 + 778e: 0300 addi s0,sp,384 + 7790: 8804 0x8804 + 7792: 00030603 lb a2,0(t1) + 7796: 0409 addi s0,s0,2 + 7798: 0100 addi s0,sp,128 + 779a: 0300 addi s0,sp,384 + 779c: 8804 0x8804 + 779e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 77a2: 0004 0x4 + 77a4: 0001 nop + 77a6: 03880403 lb s0,56(a6) + 77aa: 04090003 lb zero,64(s2) + 77ae: 0100 addi s0,sp,128 + 77b0: 0300 addi s0,sp,384 + 77b2: 8804 0x8804 + 77b4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 77b8: 0004 0x4 + 77ba: 0001 nop + 77bc: 03890403 lb s0,56(s2) + 77c0: 0306 slli t1,t1,0x1 + 77c2: 0900 addi s0,sp,144 + 77c4: 0004 0x4 + 77c6: 0001 nop + 77c8: 038e0403 lb s0,56(t3) + 77cc: 0306 slli t1,t1,0x1 + 77ce: 0900 addi s0,sp,144 + 77d0: 0008 0x8 + 77d2: 0001 nop + 77d4: 038e0403 lb s0,56(t3) + 77d8: 10090003 lb zero,256(s2) + 77dc: 0100 addi s0,sp,128 + 77de: 0300 addi s0,sp,384 + 77e0: 8e04 0x8e04 + 77e2: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 77e6: 0004 0x4 + 77e8: 0001 nop + 77ea: 038e0403 lb s0,56(t3) + 77ee: 04090003 lb zero,64(s2) + 77f2: 0100 addi s0,sp,128 + 77f4: 0300 addi s0,sp,384 + 77f6: 8e04 0x8e04 + 77f8: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 77fc: 0004 0x4 + 77fe: 0001 nop + 7800: 038e0403 lb s0,56(t3) + 7804: 00090003 lb zero,0(s2) + 7808: 0100 addi s0,sp,128 + 780a: 0300 addi s0,sp,384 + 780c: 8204 0x8204 + 780e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7812: 0008 0x8 + 7814: 0301 addi t1,t1,0 7816: 0900 addi s0,sp,144 - 7818: 0004 0x4 + 7818: 000c 0xc 781a: 0001 nop - 781c: 038e0403 lb s0,56(t3) - 7820: 0306 slli t1,t1,0x1 - 7822: 0900 addi s0,sp,144 - 7824: 0008 0x8 - 7826: 0001 nop - 7828: 038e0403 lb s0,56(t3) - 782c: 10090003 lb zero,256(s2) - 7830: 0100 addi s0,sp,128 - 7832: 0300 addi s0,sp,384 - 7834: 8e04 0x8e04 - 7836: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 783a: 0004 0x4 - 783c: 0001 nop - 783e: 038e0403 lb s0,56(t3) - 7842: 04090003 lb zero,64(s2) - 7846: 0100 addi s0,sp,128 - 7848: 0300 addi s0,sp,384 - 784a: 8e04 0x8e04 - 784c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7850: 0004 0x4 - 7852: 0001 nop - 7854: 038e0403 lb s0,56(t3) - 7858: 00090003 lb zero,0(s2) - 785c: 0100 addi s0,sp,128 - 785e: 0300 addi s0,sp,384 - 7860: 8204 0x8204 - 7862: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7866: 0008 0x8 - 7868: 0301 addi t1,t1,0 - 786a: 0900 addi s0,sp,144 - 786c: 000c 0xc - 786e: 0001 nop - 7870: 02f60403 lb s0,47(a2) - 7874: 10090003 lb zero,256(s2) - 7878: 0100 addi s0,sp,128 - 787a: 0300 addi s0,sp,384 - 787c: a304 fsd fs1,0(a4) - 787e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7882: 000c 0xc - 7884: 0001 nop - 7886: 03a30403 lb s0,58(t1) - 788a: 00090003 lb zero,0(s2) - 788e: 0100 addi s0,sp,128 - 7890: 0300 addi s0,sp,384 - 7892: a304 fsd fs1,0(a4) - 7894: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7898: 0000 unimp - 789a: 0001 nop - 789c: 03a30403 lb s0,58(t1) - 78a0: 00090003 lb zero,0(s2) - 78a4: 0100 addi s0,sp,128 - 78a6: 0300 addi s0,sp,384 - 78a8: a304 fsd fs1,0(a4) - 78aa: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 78ae: 0010 0x10 - 78b0: 0001 nop - 78b2: 039c0403 lb s0,57(s8) - 78b6: 08090003 lb zero,128(s2) - 78ba: 0100 addi s0,sp,128 - 78bc: 0300 addi s0,sp,384 - 78be: 9c04 0x9c04 - 78c0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 78c4: 0010 0x10 - 78c6: 0001 nop - 78c8: 03a60403 lb s0,58(a2) - 78cc: 08090003 lb zero,128(s2) - 78d0: 0100 addi s0,sp,128 - 78d2: 0300 addi s0,sp,384 - 78d4: a604 fsd fs1,8(a2) - 78d6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 78da: 0000 unimp - 78dc: 0001 nop - 78de: 03a60403 lb s0,58(a2) - 78e2: 00090003 lb zero,0(s2) - 78e6: 0100 addi s0,sp,128 - 78e8: 0300 addi s0,sp,384 - 78ea: a604 fsd fs1,8(a2) - 78ec: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 78f0: 0000 unimp - 78f2: 0001 nop - 78f4: 03a60403 lb s0,58(a2) - 78f8: 00090003 lb zero,0(s2) + 781c: 02f60403 lb s0,47(a2) + 7820: 10090003 lb zero,256(s2) + 7824: 0100 addi s0,sp,128 + 7826: 0300 addi s0,sp,384 + 7828: a304 fsd fs1,0(a4) + 782a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 782e: 000c 0xc + 7830: 0001 nop + 7832: 03a30403 lb s0,58(t1) + 7836: 00090003 lb zero,0(s2) + 783a: 0100 addi s0,sp,128 + 783c: 0300 addi s0,sp,384 + 783e: a304 fsd fs1,0(a4) + 7840: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7844: 0000 unimp + 7846: 0001 nop + 7848: 03a30403 lb s0,58(t1) + 784c: 00090003 lb zero,0(s2) + 7850: 0100 addi s0,sp,128 + 7852: 0300 addi s0,sp,384 + 7854: a304 fsd fs1,0(a4) + 7856: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 785a: 0010 0x10 + 785c: 0001 nop + 785e: 039c0403 lb s0,57(s8) + 7862: 08090003 lb zero,128(s2) + 7866: 0100 addi s0,sp,128 + 7868: 0300 addi s0,sp,384 + 786a: 9c04 0x9c04 + 786c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7870: 0010 0x10 + 7872: 0001 nop + 7874: 03a60403 lb s0,58(a2) + 7878: 08090003 lb zero,128(s2) + 787c: 0100 addi s0,sp,128 + 787e: 0300 addi s0,sp,384 + 7880: a604 fsd fs1,8(a2) + 7882: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7886: 0000 unimp + 7888: 0001 nop + 788a: 03a60403 lb s0,58(a2) + 788e: 00090003 lb zero,0(s2) + 7892: 0100 addi s0,sp,128 + 7894: 0300 addi s0,sp,384 + 7896: a604 fsd fs1,8(a2) + 7898: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 789c: 0000 unimp + 789e: 0001 nop + 78a0: 03a60403 lb s0,58(a2) + 78a4: 00090003 lb zero,0(s2) + 78a8: 0100 addi s0,sp,128 + 78aa: 0300 addi s0,sp,384 + 78ac: a604 fsd fs1,8(a2) + 78ae: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 78b2: 0000 unimp + 78b4: 0001 nop + 78b6: 03a60403 lb s0,58(a2) + 78ba: 00090003 lb zero,0(s2) + 78be: 0100 addi s0,sp,128 + 78c0: 0300 addi s0,sp,384 + 78c2: a604 fsd fs1,8(a2) + 78c4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 78c8: 0008 0x8 + 78ca: 0001 nop + 78cc: 03a60403 lb s0,58(a2) + 78d0: 00090003 lb zero,0(s2) + 78d4: 0100 addi s0,sp,128 + 78d6: 0300 addi s0,sp,384 + 78d8: a604 fsd fs1,8(a2) + 78da: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 78de: 0000 unimp + 78e0: 0001 nop + 78e2: 03a80403 lb s0,58(a6) + 78e6: 08090003 lb zero,128(s2) + 78ea: 0100 addi s0,sp,128 + 78ec: 0300 addi s0,sp,384 + 78ee: ab04 fsd fs1,16(a4) + 78f0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 78f4: 0010 0x10 + 78f6: 0601 addi a2,a2,0 + 78f8: 0c090003 lb zero,192(s2) 78fc: 0100 addi s0,sp,128 78fe: 0300 addi s0,sp,384 - 7900: a604 fsd fs1,8(a2) - 7902: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7906: 0000 unimp - 7908: 0001 nop - 790a: 03a60403 lb s0,58(a2) - 790e: 00090003 lb zero,0(s2) - 7912: 0100 addi s0,sp,128 - 7914: 0300 addi s0,sp,384 - 7916: a604 fsd fs1,8(a2) - 7918: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 791c: 0008 0x8 - 791e: 0001 nop - 7920: 03a60403 lb s0,58(a2) - 7924: 00090003 lb zero,0(s2) - 7928: 0100 addi s0,sp,128 - 792a: 0300 addi s0,sp,384 - 792c: a604 fsd fs1,8(a2) - 792e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7932: 0000 unimp - 7934: 0001 nop - 7936: 03a80403 lb s0,58(a6) - 793a: 08090003 lb zero,128(s2) - 793e: 0100 addi s0,sp,128 - 7940: 0300 addi s0,sp,384 - 7942: ab04 fsd fs1,16(a4) - 7944: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7948: 0010 0x10 - 794a: 0601 addi a2,a2,0 - 794c: 0c090003 lb zero,192(s2) - 7950: 0100 addi s0,sp,128 - 7952: 0300 addi s0,sp,384 - 7954: b004 fsd fs1,32(s0) - 7956: 00030603 lb a2,0(t1) - 795a: 0809 addi a6,a6,2 - 795c: 0100 addi s0,sp,128 - 795e: 0300 addi s0,sp,384 - 7960: b004 fsd fs1,32(s0) - 7962: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7966: 0014 0x14 - 7968: 0001 nop - 796a: 03b00403 lb s0,59(zero) # 3b <_start-0x7fffffc5> - 796e: 00090003 lb zero,0(s2) - 7972: 0100 addi s0,sp,128 - 7974: 0300 addi s0,sp,384 - 7976: aa04 fsd fs1,16(a2) - 7978: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 797c: 001c 0x1c - 797e: 0001 nop - 7980: 03aa0403 lb s0,58(s4) - 7984: 14090003 lb zero,320(s2) - 7988: 0100 addi s0,sp,128 - 798a: 0300 addi s0,sp,384 - 798c: ad04 fsd fs1,24(a0) - 798e: 00030603 lb a2,0(t1) - 7992: 0409 addi s0,s0,2 - 7994: 0100 addi s0,sp,128 - 7996: 0300 addi s0,sp,384 - 7998: ad04 fsd fs1,24(a0) - 799a: 00030603 lb a2,0(t1) - 799e: 2009 jal 79a0 <_start-0x7fff8660> - 79a0: 0100 addi s0,sp,128 - 79a2: 0300 addi s0,sp,384 - 79a4: ad04 fsd fs1,24(a0) - 79a6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 79aa: 0008 0x8 - 79ac: 0001 nop - 79ae: 03b10403 lb s0,59(sp) - 79b2: 0c090003 lb zero,192(s2) - 79b6: 0100 addi s0,sp,128 - 79b8: 0300 addi s0,sp,384 - 79ba: b404 fsd fs1,40(s0) - 79bc: 00030603 lb a2,0(t1) - 79c0: 0809 addi a6,a6,2 - 79c2: 0100 addi s0,sp,128 - 79c4: 0300 addi s0,sp,384 - 79c6: b404 fsd fs1,40(s0) - 79c8: 00030603 lb a2,0(t1) - 79cc: 1809 addi a6,a6,-30 - 79ce: 0100 addi s0,sp,128 - 79d0: 0300 addi s0,sp,384 - 79d2: b604 fsd fs1,40(a2) - 79d4: 00030603 lb a2,0(t1) - 79d8: 0809 addi a6,a6,2 - 79da: 0100 addi s0,sp,128 - 79dc: 0300 addi s0,sp,384 - 79de: b304 fsd fs1,32(a4) - 79e0: 00030603 lb a2,0(t1) - 79e4: 0809 addi a6,a6,2 + 7900: b004 fsd fs1,32(s0) + 7902: 00030603 lb a2,0(t1) + 7906: 0809 addi a6,a6,2 + 7908: 0100 addi s0,sp,128 + 790a: 0300 addi s0,sp,384 + 790c: b004 fsd fs1,32(s0) + 790e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7912: 0014 0x14 + 7914: 0001 nop + 7916: 03b00403 lb s0,59(zero) # 3b <_start-0x7fffffc5> + 791a: 00090003 lb zero,0(s2) + 791e: 0100 addi s0,sp,128 + 7920: 0300 addi s0,sp,384 + 7922: aa04 fsd fs1,16(a2) + 7924: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7928: 001c 0x1c + 792a: 0001 nop + 792c: 03aa0403 lb s0,58(s4) + 7930: 14090003 lb zero,320(s2) + 7934: 0100 addi s0,sp,128 + 7936: 0300 addi s0,sp,384 + 7938: ad04 fsd fs1,24(a0) + 793a: 00030603 lb a2,0(t1) + 793e: 0409 addi s0,s0,2 + 7940: 0100 addi s0,sp,128 + 7942: 0300 addi s0,sp,384 + 7944: ad04 fsd fs1,24(a0) + 7946: 00030603 lb a2,0(t1) + 794a: 2009 jal 794c <_start-0x7fff86b4> + 794c: 0100 addi s0,sp,128 + 794e: 0300 addi s0,sp,384 + 7950: ad04 fsd fs1,24(a0) + 7952: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7956: 0008 0x8 + 7958: 0001 nop + 795a: 03b10403 lb s0,59(sp) + 795e: 0c090003 lb zero,192(s2) + 7962: 0100 addi s0,sp,128 + 7964: 0300 addi s0,sp,384 + 7966: b404 fsd fs1,40(s0) + 7968: 00030603 lb a2,0(t1) + 796c: 0809 addi a6,a6,2 + 796e: 0100 addi s0,sp,128 + 7970: 0300 addi s0,sp,384 + 7972: b404 fsd fs1,40(s0) + 7974: 00030603 lb a2,0(t1) + 7978: 1809 addi a6,a6,-30 + 797a: 0100 addi s0,sp,128 + 797c: 0300 addi s0,sp,384 + 797e: b604 fsd fs1,40(a2) + 7980: 00030603 lb a2,0(t1) + 7984: 0809 addi a6,a6,2 + 7986: 0100 addi s0,sp,128 + 7988: 0300 addi s0,sp,384 + 798a: b304 fsd fs1,32(a4) + 798c: 00030603 lb a2,0(t1) + 7990: 0809 addi a6,a6,2 + 7992: 0100 addi s0,sp,128 + 7994: 0300 addi s0,sp,384 + 7996: b304 fsd fs1,32(a4) + 7998: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 799c: 0020 addi s0,sp,8 + 799e: 0001 nop + 79a0: 03b70403 lb s0,59(a4) + 79a4: 08090003 lb zero,128(s2) + 79a8: 0100 addi s0,sp,128 + 79aa: 0300 addi s0,sp,384 + 79ac: b704 fsd fs1,40(a4) + 79ae: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 79b2: 000c 0xc + 79b4: 0001 nop + 79b6: 03b60403 lb s0,59(a2) + 79ba: 04090003 lb zero,64(s2) + 79be: 0100 addi s0,sp,128 + 79c0: 0300 addi s0,sp,384 + 79c2: b804 fsd fs1,48(s0) + 79c4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 79c8: 0004 0x4 + 79ca: 0001 nop + 79cc: 03b80403 lb s0,59(a6) + 79d0: 00090003 lb zero,0(s2) + 79d4: 0100 addi s0,sp,128 + 79d6: 0300 addi s0,sp,384 + 79d8: b804 fsd fs1,48(s0) + 79da: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 79de: 0000 unimp + 79e0: 0601 addi a2,a2,0 + 79e2: 0c090003 lb zero,192(s2) 79e6: 0100 addi s0,sp,128 - 79e8: 0300 addi s0,sp,384 - 79ea: b304 fsd fs1,32(a4) - 79ec: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 79f0: 0020 addi s0,sp,8 - 79f2: 0001 nop - 79f4: 03b70403 lb s0,59(a4) - 79f8: 08090003 lb zero,128(s2) - 79fc: 0100 addi s0,sp,128 - 79fe: 0300 addi s0,sp,384 - 7a00: b704 fsd fs1,40(a4) - 7a02: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7a06: 000c 0xc - 7a08: 0001 nop - 7a0a: 03b60403 lb s0,59(a2) - 7a0e: 04090003 lb zero,64(s2) - 7a12: 0100 addi s0,sp,128 - 7a14: 0300 addi s0,sp,384 - 7a16: b804 fsd fs1,48(s0) - 7a18: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7a1c: 0004 0x4 - 7a1e: 0001 nop - 7a20: 03b80403 lb s0,59(a6) - 7a24: 00090003 lb zero,0(s2) - 7a28: 0100 addi s0,sp,128 - 7a2a: 0300 addi s0,sp,384 - 7a2c: b804 fsd fs1,48(s0) - 7a2e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7a32: 0000 unimp - 7a34: 0601 addi a2,a2,0 - 7a36: 0c090003 lb zero,192(s2) + 79e8: 0306 slli t1,t1,0x1 + 79ea: 0900 addi s0,sp,144 + 79ec: 0004 0x4 + 79ee: 0301 addi t1,t1,0 + 79f0: 0900 addi s0,sp,144 + 79f2: 0000 unimp + 79f4: 0301 addi t1,t1,0 + 79f6: 0900 addi s0,sp,144 + 79f8: 0000 unimp + 79fa: 0301 addi t1,t1,0 + 79fc: 0900 addi s0,sp,144 + 79fe: 0000 unimp + 7a00: 0301 addi t1,t1,0 + 7a02: 0900 addi s0,sp,144 + 7a04: 0000 unimp + 7a06: 0301 addi t1,t1,0 + 7a08: 0900 addi s0,sp,144 + 7a0a: 000c 0xc + 7a0c: 0301 addi t1,t1,0 + 7a0e: 0900 addi s0,sp,144 + 7a10: 0000 unimp + 7a12: 0301 addi t1,t1,0 + 7a14: 0900 addi s0,sp,144 + 7a16: 0004 0x4 + 7a18: 0301 addi t1,t1,0 + 7a1a: 0900 addi s0,sp,144 + 7a1c: 0008 0x8 + 7a1e: 0301 addi t1,t1,0 + 7a20: 0900 addi s0,sp,144 + 7a22: 0004 0x4 + 7a24: 0001 nop + 7a26: 03bd0403 lb s0,59(s10) + 7a2a: 0306 slli t1,t1,0x1 + 7a2c: 0900 addi s0,sp,144 + 7a2e: 0008 0x8 + 7a30: 0001 nop + 7a32: 03c20403 lb s0,60(tp) # 3c <_start-0x7fffffc4> + 7a36: 08090003 lb zero,128(s2) 7a3a: 0100 addi s0,sp,128 - 7a3c: 0306 slli t1,t1,0x1 - 7a3e: 0900 addi s0,sp,144 - 7a40: 0004 0x4 - 7a42: 0301 addi t1,t1,0 - 7a44: 0900 addi s0,sp,144 - 7a46: 0000 unimp - 7a48: 0301 addi t1,t1,0 - 7a4a: 0900 addi s0,sp,144 - 7a4c: 0000 unimp - 7a4e: 0301 addi t1,t1,0 - 7a50: 0900 addi s0,sp,144 - 7a52: 0000 unimp - 7a54: 0301 addi t1,t1,0 - 7a56: 0900 addi s0,sp,144 - 7a58: 0000 unimp - 7a5a: 0301 addi t1,t1,0 - 7a5c: 0900 addi s0,sp,144 - 7a5e: 000c 0xc - 7a60: 0301 addi t1,t1,0 - 7a62: 0900 addi s0,sp,144 - 7a64: 0000 unimp - 7a66: 0301 addi t1,t1,0 - 7a68: 0900 addi s0,sp,144 - 7a6a: 0004 0x4 - 7a6c: 0301 addi t1,t1,0 - 7a6e: 0900 addi s0,sp,144 - 7a70: 0008 0x8 - 7a72: 0301 addi t1,t1,0 - 7a74: 0900 addi s0,sp,144 - 7a76: 0004 0x4 - 7a78: 0001 nop - 7a7a: 03bd0403 lb s0,59(s10) - 7a7e: 0306 slli t1,t1,0x1 - 7a80: 0900 addi s0,sp,144 - 7a82: 0008 0x8 - 7a84: 0001 nop - 7a86: 03c20403 lb s0,60(tp) # 3c <_start-0x7fffffc4> - 7a8a: 08090003 lb zero,128(s2) - 7a8e: 0100 addi s0,sp,128 - 7a90: 0300 addi s0,sp,384 - 7a92: c204 sw s1,0(a2) - 7a94: 00030603 lb a2,0(t1) - 7a98: 0809 addi a6,a6,2 - 7a9a: 0100 addi s0,sp,128 - 7a9c: 0300 addi s0,sp,384 - 7a9e: c204 sw s1,0(a2) - 7aa0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7aa4: 0008 0x8 - 7aa6: 0001 nop - 7aa8: 03c20403 lb s0,60(tp) # 3c <_start-0x7fffffc4> - 7aac: 04090003 lb zero,64(s2) - 7ab0: 0100 addi s0,sp,128 - 7ab2: 0300 addi s0,sp,384 - 7ab4: c204 sw s1,0(a2) - 7ab6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7aba: 0004 0x4 - 7abc: 0001 nop - 7abe: 03c30403 lb s0,60(t1) - 7ac2: 0306 slli t1,t1,0x1 - 7ac4: 0900 addi s0,sp,144 - 7ac6: 0004 0x4 - 7ac8: 0001 nop - 7aca: 03c80403 lb s0,60(a6) - 7ace: 0306 slli t1,t1,0x1 - 7ad0: 0900 addi s0,sp,144 - 7ad2: 0008 0x8 - 7ad4: 0001 nop - 7ad6: 03c80403 lb s0,60(a6) - 7ada: 18090003 lb zero,384(s2) - 7ade: 0100 addi s0,sp,128 - 7ae0: 0300 addi s0,sp,384 - 7ae2: c804 sw s1,16(s0) - 7ae4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7ae8: 0000 unimp - 7aea: 0001 nop - 7aec: 03c80403 lb s0,60(a6) - 7af0: 04090003 lb zero,64(s2) - 7af4: 0100 addi s0,sp,128 - 7af6: 0300 addi s0,sp,384 - 7af8: c804 sw s1,16(s0) - 7afa: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7afe: 0004 0x4 - 7b00: 0001 nop - 7b02: 03c80403 lb s0,60(a6) - 7b06: 0306 slli t1,t1,0x1 - 7b08: 097f 0x97f - 7b0a: 0000 unimp - 7b0c: 0601 addi a2,a2,0 - 7b0e: 0c090103 lb sp,192(s2) - 7b12: 0100 addi s0,sp,128 - 7b14: 0300 addi s0,sp,384 - 7b16: f404 fsw fs1,40(s0) - 7b18: 0302 c.slli64 t1 - 7b1a: 0900 addi s0,sp,144 - 7b1c: 0014 0x14 - 7b1e: 0001 nop - 7b20: 03c90403 lb s0,60(s2) - 7b24: 20090003 lb zero,512(s2) - 7b28: 0100 addi s0,sp,128 - 7b2a: 0300 addi s0,sp,384 - 7b2c: cb04 sw s1,16(a4) - 7b2e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7b32: 001c 0x1c - 7b34: 0001 nop - 7b36: 03cb0403 lb s0,60(s6) - 7b3a: 00090003 lb zero,0(s2) - 7b3e: 0100 addi s0,sp,128 - 7b40: 0300 addi s0,sp,384 - 7b42: cd04 sw s1,24(a0) - 7b44: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7b48: 0004 0x4 - 7b4a: 0001 nop - 7b4c: 03cd0403 lb s0,60(s10) - 7b50: 10090003 lb zero,256(s2) - 7b54: 0100 addi s0,sp,128 - 7b56: 0306 slli t1,t1,0x1 - 7b58: 0900 addi s0,sp,144 - 7b5a: 0008 0x8 - 7b5c: 0001 nop - 7b5e: 03ce0403 lb s0,60(t3) - 7b62: 0306 slli t1,t1,0x1 - 7b64: 0900 addi s0,sp,144 - 7b66: 000c 0xc - 7b68: 0001 nop - 7b6a: 03d40403 lb s0,61(s0) - 7b6e: 04090003 lb zero,64(s2) - 7b72: 0100 addi s0,sp,128 - 7b74: 0300 addi s0,sp,384 - 7b76: d404 sw s1,40(s0) - 7b78: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7b7c: 0000 unimp - 7b7e: 0001 nop - 7b80: 03d50403 lb s0,61(a0) - 7b84: 10090003 lb zero,256(s2) - 7b88: 0100 addi s0,sp,128 - 7b8a: 0300 addi s0,sp,384 - 7b8c: d504 sw s1,40(a0) - 7b8e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7b92: 0000 unimp - 7b94: 0001 nop - 7b96: 03d50403 lb s0,61(a0) - 7b9a: 00090003 lb zero,0(s2) - 7b9e: 0100 addi s0,sp,128 - 7ba0: 0300 addi s0,sp,384 - 7ba2: d504 sw s1,40(a0) - 7ba4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7ba8: 0000 unimp - 7baa: 0001 nop - 7bac: 03d50403 lb s0,61(a0) - 7bb0: 00090003 lb zero,0(s2) - 7bb4: 0100 addi s0,sp,128 - 7bb6: 0300 addi s0,sp,384 - 7bb8: d504 sw s1,40(a0) - 7bba: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7bbe: 0000 unimp - 7bc0: 0001 nop - 7bc2: 03d50403 lb s0,61(a0) - 7bc6: 04090003 lb zero,64(s2) - 7bca: 0100 addi s0,sp,128 - 7bcc: 0300 addi s0,sp,384 - 7bce: d504 sw s1,40(a0) - 7bd0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7bd4: 0000 unimp - 7bd6: 0001 nop - 7bd8: 03d50403 lb s0,61(a0) - 7bdc: 04090003 lb zero,64(s2) - 7be0: 0100 addi s0,sp,128 - 7be2: 0300 addi s0,sp,384 - 7be4: d504 sw s1,40(a0) - 7be6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7bea: 0008 0x8 - 7bec: 0001 nop - 7bee: 03d50403 lb s0,61(a0) - 7bf2: 04090003 lb zero,64(s2) - 7bf6: 0100 addi s0,sp,128 - 7bf8: 0300 addi s0,sp,384 - 7bfa: d704 sw s1,40(a4) - 7bfc: 00030603 lb a2,0(t1) - 7c00: 0809 addi a6,a6,2 - 7c02: 0100 addi s0,sp,128 - 7c04: 0300 addi s0,sp,384 - 7c06: dc04 sw s1,56(s0) - 7c08: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7c0c: 0004 0x4 - 7c0e: 0001 nop - 7c10: 03dc0403 lb s0,61(s8) - 7c14: 0306 slli t1,t1,0x1 - 7c16: 0900 addi s0,sp,144 - 7c18: 0008 0x8 - 7c1a: 0001 nop - 7c1c: 03dc0403 lb s0,61(s8) - 7c20: 00090003 lb zero,0(s2) - 7c24: 0100 addi s0,sp,128 - 7c26: 0300 addi s0,sp,384 - 7c28: dc04 sw s1,56(s0) - 7c2a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7c2e: 0004 0x4 - 7c30: 0001 nop - 7c32: 03dc0403 lb s0,61(s8) - 7c36: 04090003 lb zero,64(s2) - 7c3a: 0100 addi s0,sp,128 - 7c3c: 0300 addi s0,sp,384 - 7c3e: dd04 sw s1,56(a0) - 7c40: 00030603 lb a2,0(t1) - 7c44: 0809 addi a6,a6,2 - 7c46: 0100 addi s0,sp,128 - 7c48: 0300 addi s0,sp,384 - 7c4a: e204 fsw fs1,0(a2) - 7c4c: 00030603 lb a2,0(t1) - 7c50: 0409 addi s0,s0,2 - 7c52: 0100 addi s0,sp,128 - 7c54: 0300 addi s0,sp,384 - 7c56: e204 fsw fs1,0(a2) - 7c58: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7c5c: 0010 0x10 - 7c5e: 0001 nop - 7c60: 03e20403 lb s0,62(tp) # 3e <_start-0x7fffffc2> - 7c64: 04090003 lb zero,64(s2) - 7c68: 0100 addi s0,sp,128 - 7c6a: 0300 addi s0,sp,384 - 7c6c: e204 fsw fs1,0(a2) - 7c6e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7c72: 0004 0x4 - 7c74: 0001 nop - 7c76: 03e20403 lb s0,62(tp) # 3e <_start-0x7fffffc2> - 7c7a: 04090003 lb zero,64(s2) - 7c7e: 0100 addi s0,sp,128 - 7c80: 0300 addi s0,sp,384 - 7c82: e204 fsw fs1,0(a2) - 7c84: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7c88: 0000 unimp - 7c8a: 0001 nop - 7c8c: 03e20403 lb s0,62(tp) # 3e <_start-0x7fffffc2> - 7c90: 00090003 lb zero,0(s2) - 7c94: 0100 addi s0,sp,128 - 7c96: 0300 addi s0,sp,384 - 7c98: e304 fsw fs1,0(a4) - 7c9a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7c9e: 0008 0x8 - 7ca0: 0001 nop - 7ca2: 03e30403 lb s0,62(t1) - 7ca6: 00090003 lb zero,0(s2) - 7caa: 0100 addi s0,sp,128 - 7cac: 0300 addi s0,sp,384 - 7cae: e304 fsw fs1,0(a4) - 7cb0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7cb4: 0000 unimp - 7cb6: 0001 nop - 7cb8: 03e30403 lb s0,62(t1) - 7cbc: 00090003 lb zero,0(s2) - 7cc0: 0100 addi s0,sp,128 - 7cc2: 0300 addi s0,sp,384 - 7cc4: e304 fsw fs1,0(a4) - 7cc6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7cca: 0000 unimp - 7ccc: 0001 nop - 7cce: 03e30403 lb s0,62(t1) - 7cd2: 08090003 lb zero,128(s2) - 7cd6: 0100 addi s0,sp,128 - 7cd8: 0300 addi s0,sp,384 - 7cda: e304 fsw fs1,0(a4) - 7cdc: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7ce0: 0000 unimp - 7ce2: 0001 nop - 7ce4: 03e30403 lb s0,62(t1) - 7ce8: 00090003 lb zero,0(s2) - 7cec: 0100 addi s0,sp,128 - 7cee: 0300 addi s0,sp,384 - 7cf0: e304 fsw fs1,0(a4) - 7cf2: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7cf6: 0004 0x4 - 7cf8: 0001 nop - 7cfa: 03e30403 lb s0,62(t1) - 7cfe: 08090003 lb zero,128(s2) - 7d02: 0100 addi s0,sp,128 - 7d04: 0300 addi s0,sp,384 - 7d06: e504 fsw fs1,8(a0) - 7d08: 00030603 lb a2,0(t1) - 7d0c: 0809 addi a6,a6,2 - 7d0e: 0100 addi s0,sp,128 - 7d10: 0300 addi s0,sp,384 - 7d12: ea04 fsw fs1,16(a2) - 7d14: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7d18: 0004 0x4 - 7d1a: 0001 nop - 7d1c: 03ea0403 lb s0,62(s4) - 7d20: 0306 slli t1,t1,0x1 - 7d22: 0900 addi s0,sp,144 - 7d24: 0004 0x4 - 7d26: 0001 nop - 7d28: 03ea0403 lb s0,62(s4) - 7d2c: 04090003 lb zero,64(s2) - 7d30: 0100 addi s0,sp,128 - 7d32: 0300 addi s0,sp,384 - 7d34: ea04 fsw fs1,16(a2) - 7d36: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7d3a: 0004 0x4 - 7d3c: 0001 nop - 7d3e: 03ea0403 lb s0,62(s4) - 7d42: 08090003 lb zero,128(s2) - 7d46: 0100 addi s0,sp,128 - 7d48: 0300 addi s0,sp,384 - 7d4a: eb04 fsw fs1,16(a4) - 7d4c: 00030603 lb a2,0(t1) - 7d50: 0409 addi s0,s0,2 - 7d52: 0100 addi s0,sp,128 - 7d54: 0300 addi s0,sp,384 - 7d56: f004 fsw fs1,32(s0) - 7d58: 00030603 lb a2,0(t1) - 7d5c: 0409 addi s0,s0,2 - 7d5e: 0100 addi s0,sp,128 - 7d60: 0300 addi s0,sp,384 - 7d62: f004 fsw fs1,32(s0) - 7d64: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7d68: 0010 0x10 - 7d6a: 0001 nop - 7d6c: 03f00403 lb s0,63(zero) # 3f <_start-0x7fffffc1> - 7d70: 04090003 lb zero,64(s2) - 7d74: 0100 addi s0,sp,128 - 7d76: 0300 addi s0,sp,384 - 7d78: f004 fsw fs1,32(s0) - 7d7a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7d7e: 0004 0x4 - 7d80: 0001 nop - 7d82: 03e40403 lb s0,62(s0) - 7d86: 08090003 lb zero,128(s2) - 7d8a: 0100 addi s0,sp,128 - 7d8c: 0300 addi s0,sp,384 - 7d8e: 8304 0x8304 - 7d90: 0304 addi s1,sp,384 - 7d92: 0900 addi s0,sp,144 - 7d94: 0010 0x10 - 7d96: 0001 nop - 7d98: 04830403 lb s0,72(t1) - 7d9c: 00090003 lb zero,0(s2) - 7da0: 0100 addi s0,sp,128 - 7da2: 0300 addi s0,sp,384 - 7da4: 8304 0x8304 - 7da6: 0304 addi s1,sp,384 - 7da8: 0900 addi s0,sp,144 - 7daa: 0000 unimp - 7dac: 0001 nop - 7dae: 04830403 lb s0,72(t1) - 7db2: 00090003 lb zero,0(s2) - 7db6: 0100 addi s0,sp,128 - 7db8: 0300 addi s0,sp,384 - 7dba: 8304 0x8304 - 7dbc: 0304 addi s1,sp,384 - 7dbe: 0900 addi s0,sp,144 - 7dc0: 0000 unimp - 7dc2: 0001 nop - 7dc4: 04830403 lb s0,72(t1) - 7dc8: 00090003 lb zero,0(s2) - 7dcc: 0100 addi s0,sp,128 - 7dce: 0300 addi s0,sp,384 - 7dd0: 8304 0x8304 - 7dd2: 0304 addi s1,sp,384 - 7dd4: 0900 addi s0,sp,144 - 7dd6: 0000 unimp - 7dd8: 0001 nop - 7dda: 04830403 lb s0,72(t1) - 7dde: 00090003 lb zero,0(s2) - 7de2: 0100 addi s0,sp,128 - 7de4: 0300 addi s0,sp,384 - 7de6: 8404 0x8404 - 7de8: 0304 addi s1,sp,384 - 7dea: 0900 addi s0,sp,144 - 7dec: 0008 0x8 - 7dee: 0001 nop - 7df0: 04860403 lb s0,72(a2) - 7df4: 04090003 lb zero,64(s2) - 7df8: 0100 addi s0,sp,128 - 7dfa: 0300 addi s0,sp,384 - 7dfc: 8604 0x8604 - 7dfe: 0304 addi s1,sp,384 - 7e00: 0900 addi s0,sp,144 - 7e02: 0000 unimp - 7e04: 0001 nop - 7e06: 04860403 lb s0,72(a2) - 7e0a: 10090003 lb zero,256(s2) - 7e0e: 0100 addi s0,sp,128 - 7e10: 0300 addi s0,sp,384 - 7e12: 8604 0x8604 - 7e14: 0304 addi s1,sp,384 - 7e16: 0900 addi s0,sp,144 - 7e18: 0000 unimp - 7e1a: 0001 nop - 7e1c: 04860403 lb s0,72(a2) - 7e20: 00090003 lb zero,0(s2) - 7e24: 0100 addi s0,sp,128 - 7e26: 0300 addi s0,sp,384 - 7e28: 8604 0x8604 - 7e2a: 0304 addi s1,sp,384 - 7e2c: 0900 addi s0,sp,144 - 7e2e: 0000 unimp - 7e30: 0001 nop - 7e32: 04860403 lb s0,72(a2) - 7e36: 00090003 lb zero,0(s2) - 7e3a: 0100 addi s0,sp,128 - 7e3c: 0300 addi s0,sp,384 - 7e3e: 8604 0x8604 - 7e40: 0304 addi s1,sp,384 - 7e42: 0900 addi s0,sp,144 - 7e44: 0000 unimp - 7e46: 0001 nop - 7e48: 04860403 lb s0,72(a2) - 7e4c: 00090003 lb zero,0(s2) - 7e50: 0100 addi s0,sp,128 - 7e52: 0300 addi s0,sp,384 - 7e54: 8604 0x8604 - 7e56: 0304 addi s1,sp,384 - 7e58: 0900 addi s0,sp,144 - 7e5a: 0000 unimp - 7e5c: 0001 nop - 7e5e: 04860403 lb s0,72(a2) - 7e62: 00090003 lb zero,0(s2) - 7e66: 0100 addi s0,sp,128 - 7e68: 0300 addi s0,sp,384 - 7e6a: 8f04 0x8f04 - 7e6c: 0304 addi s1,sp,384 - 7e6e: 0900 addi s0,sp,144 - 7e70: 0004 0x4 - 7e72: 0001 nop - 7e74: 048f0403 lb s0,72(t5) - 7e78: 1c090003 lb zero,448(s2) - 7e7c: 0100 addi s0,sp,128 - 7e7e: 0300 addi s0,sp,384 - 7e80: 8f04 0x8f04 - 7e82: 0304 addi s1,sp,384 - 7e84: 0900 addi s0,sp,144 - 7e86: 0000 unimp - 7e88: 0001 nop - 7e8a: 04870403 lb s0,72(a4) - 7e8e: 08090003 lb zero,128(s2) - 7e92: 0100 addi s0,sp,128 - 7e94: 0300 addi s0,sp,384 - 7e96: 8704 0x8704 - 7e98: 0304 addi s1,sp,384 - 7e9a: 0900 addi s0,sp,144 - 7e9c: 0000 unimp - 7e9e: 0001 nop - 7ea0: 04950403 lb s0,73(a0) - 7ea4: 0306 slli t1,t1,0x1 - 7ea6: 0900 addi s0,sp,144 - 7ea8: 0014 0x14 - 7eaa: 0001 nop - 7eac: 04850403 lb s0,72(a0) - 7eb0: 0306 slli t1,t1,0x1 - 7eb2: 0900 addi s0,sp,144 - 7eb4: 0008 0x8 - 7eb6: 0001 nop - 7eb8: 04950403 lb s0,73(a0) - 7ebc: 04090003 lb zero,64(s2) - 7ec0: 0100 addi s0,sp,128 - 7ec2: 0300 addi s0,sp,384 - 7ec4: 9504 0x9504 - 7ec6: 0304 addi s1,sp,384 - 7ec8: 0900 addi s0,sp,144 - 7eca: 0000 unimp - 7ecc: 0001 nop - 7ece: 049d0403 lb s0,73(s10) - 7ed2: 14090003 lb zero,320(s2) - 7ed6: 0100 addi s0,sp,128 - 7ed8: 0300 addi s0,sp,384 - 7eda: 9d04 0x9d04 - 7edc: 0304 addi s1,sp,384 - 7ede: 0900 addi s0,sp,144 - 7ee0: 0000 unimp - 7ee2: 0001 nop - 7ee4: 049d0403 lb s0,73(s10) - 7ee8: 00090003 lb zero,0(s2) - 7eec: 0100 addi s0,sp,128 - 7eee: 0300 addi s0,sp,384 - 7ef0: 9d04 0x9d04 - 7ef2: 0304 addi s1,sp,384 - 7ef4: 0900 addi s0,sp,144 - 7ef6: 0000 unimp - 7ef8: 0001 nop - 7efa: 049d0403 lb s0,73(s10) - 7efe: 00090003 lb zero,0(s2) - 7f02: 0100 addi s0,sp,128 - 7f04: 0300 addi s0,sp,384 - 7f06: 9d04 0x9d04 - 7f08: 0304 addi s1,sp,384 - 7f0a: 0900 addi s0,sp,144 - 7f0c: 0000 unimp - 7f0e: 0001 nop - 7f10: 049d0403 lb s0,73(s10) - 7f14: 00090003 lb zero,0(s2) - 7f18: 0100 addi s0,sp,128 - 7f1a: 0300 addi s0,sp,384 - 7f1c: 9d04 0x9d04 - 7f1e: 0304 addi s1,sp,384 - 7f20: 0900 addi s0,sp,144 - 7f22: 0000 unimp - 7f24: 0001 nop - 7f26: 049d0403 lb s0,73(s10) - 7f2a: 00090003 lb zero,0(s2) - 7f2e: 0100 addi s0,sp,128 - 7f30: 0300 addi s0,sp,384 - 7f32: 9d04 0x9d04 - 7f34: 0304 addi s1,sp,384 - 7f36: 0900 addi s0,sp,144 - 7f38: 0000 unimp - 7f3a: 0001 nop - 7f3c: 049d0403 lb s0,73(s10) - 7f40: 10090003 lb zero,256(s2) - 7f44: 0100 addi s0,sp,128 - 7f46: 0300 addi s0,sp,384 - 7f48: 9d04 0x9d04 - 7f4a: 0304 addi s1,sp,384 - 7f4c: 0900 addi s0,sp,144 - 7f4e: 0000 unimp - 7f50: 0001 nop - 7f52: 049d0403 lb s0,73(s10) - 7f56: 00090003 lb zero,0(s2) - 7f5a: 0100 addi s0,sp,128 - 7f5c: 0300 addi s0,sp,384 - 7f5e: 9d04 0x9d04 - 7f60: 0304 addi s1,sp,384 - 7f62: 0900 addi s0,sp,144 - 7f64: 0000 unimp - 7f66: 0001 nop - 7f68: 049d0403 lb s0,73(s10) - 7f6c: 00090003 lb zero,0(s2) - 7f70: 0100 addi s0,sp,128 - 7f72: 0300 addi s0,sp,384 - 7f74: 9d04 0x9d04 - 7f76: 0304 addi s1,sp,384 - 7f78: 0900 addi s0,sp,144 - 7f7a: 0000 unimp - 7f7c: 0001 nop - 7f7e: 049d0403 lb s0,73(s10) - 7f82: 00090003 lb zero,0(s2) - 7f86: 0100 addi s0,sp,128 - 7f88: 0300 addi s0,sp,384 - 7f8a: 9d04 0x9d04 - 7f8c: 0304 addi s1,sp,384 - 7f8e: 0900 addi s0,sp,144 - 7f90: 0000 unimp - 7f92: 0001 nop - 7f94: 049d0403 lb s0,73(s10) - 7f98: 00090003 lb zero,0(s2) - 7f9c: 0100 addi s0,sp,128 - 7f9e: 0300 addi s0,sp,384 - 7fa0: 9d04 0x9d04 - 7fa2: 0304 addi s1,sp,384 - 7fa4: 0900 addi s0,sp,144 - 7fa6: 0000 unimp - 7fa8: 0001 nop - 7faa: 049d0403 lb s0,73(s10) - 7fae: 00090003 lb zero,0(s2) - 7fb2: 0100 addi s0,sp,128 - 7fb4: 0300 addi s0,sp,384 - 7fb6: b904 fsd fs1,48(a0) - 7fb8: 0304 addi s1,sp,384 - 7fba: 0900 addi s0,sp,144 - 7fbc: 0004 0x4 - 7fbe: 0001 nop - 7fc0: 04b90403 lb s0,75(s2) - 7fc4: 1c090003 lb zero,448(s2) - 7fc8: 0100 addi s0,sp,128 - 7fca: 0300 addi s0,sp,384 - 7fcc: b904 fsd fs1,48(a0) - 7fce: 0304 addi s1,sp,384 - 7fd0: 0900 addi s0,sp,144 - 7fd2: 0000 unimp - 7fd4: 0001 nop - 7fd6: 03ca0403 lb s0,60(s4) - 7fda: 08090003 lb zero,128(s2) - 7fde: 0100 addi s0,sp,128 - 7fe0: 0300 addi s0,sp,384 - 7fe2: ca04 sw s1,16(a2) - 7fe4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7fe8: 0000 unimp - 7fea: 0001 nop - 7fec: 03ca0403 lb s0,60(s4) - 7ff0: 00090003 lb zero,0(s2) - 7ff4: 0100 addi s0,sp,128 - 7ff6: 0300 addi s0,sp,384 - 7ff8: ca04 sw s1,16(a2) - 7ffa: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 7ffe: 0000 unimp - 8000: 0001 nop - 8002: 03ca0403 lb s0,60(s4) - 8006: 00090003 lb zero,0(s2) - 800a: 0100 addi s0,sp,128 - 800c: 0300 addi s0,sp,384 - 800e: ca04 sw s1,16(a2) - 8010: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 8014: 0000 unimp - 8016: 0001 nop - 8018: 03ca0403 lb s0,60(s4) - 801c: 04090003 lb zero,64(s2) - 8020: 0100 addi s0,sp,128 - 8022: 0300 addi s0,sp,384 - 8024: ca04 sw s1,16(a2) - 8026: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 802a: 0000 unimp - 802c: 0001 nop - 802e: 03ca0403 lb s0,60(s4) - 8032: 04090003 lb zero,64(s2) - 8036: 0100 addi s0,sp,128 - 8038: 0300 addi s0,sp,384 - 803a: ca04 sw s1,16(a2) - 803c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> - 8040: 0008 0x8 - 8042: 0001 nop - 8044: 03ca0403 lb s0,60(s4) - 8048: 04090003 lb zero,64(s2) - 804c: 0100 addi s0,sp,128 - 804e: 0300 addi s0,sp,384 - 8050: c004 sw s1,0(s0) - 8052: 0604 addi s1,sp,768 - 8054: 08090003 lb zero,128(s2) - 8058: 0100 addi s0,sp,128 - 805a: 0300 addi s0,sp,384 - 805c: c504 sw s1,8(a0) - 805e: 0304 addi s1,sp,384 - 8060: 0900 addi s0,sp,144 - 8062: 0004 0x4 - 8064: 0001 nop - 8066: 04c50403 lb s0,76(a0) - 806a: 0306 slli t1,t1,0x1 - 806c: 0900 addi s0,sp,144 - 806e: 0008 0x8 - 8070: 0001 nop - 8072: 04c50403 lb s0,76(a0) - 8076: 00090003 lb zero,0(s2) - 807a: 0100 addi s0,sp,128 - 807c: 0300 addi s0,sp,384 - 807e: c504 sw s1,8(a0) - 8080: 0304 addi s1,sp,384 - 8082: 0900 addi s0,sp,144 - 8084: 0004 0x4 - 8086: 0001 nop - 8088: 04c50403 lb s0,76(a0) - 808c: 04090003 lb zero,64(s2) - 8090: 0100 addi s0,sp,128 - 8092: 0300 addi s0,sp,384 - 8094: c604 sw s1,8(a2) - 8096: 0604 addi s1,sp,768 - 8098: 08090003 lb zero,128(s2) - 809c: 0100 addi s0,sp,128 - 809e: 0300 addi s0,sp,384 - 80a0: cb04 sw s1,16(a4) - 80a2: 0604 addi s1,sp,768 - 80a4: 04090003 lb zero,64(s2) - 80a8: 0100 addi s0,sp,128 - 80aa: 0300 addi s0,sp,384 - 80ac: cb04 sw s1,16(a4) - 80ae: 0304 addi s1,sp,384 - 80b0: 0900 addi s0,sp,144 - 80b2: 0010 0x10 - 80b4: 0001 nop - 80b6: 04cb0403 lb s0,76(s6) - 80ba: 04090003 lb zero,64(s2) - 80be: 0100 addi s0,sp,128 - 80c0: 0300 addi s0,sp,384 - 80c2: cb04 sw s1,16(a4) - 80c4: 0304 addi s1,sp,384 - 80c6: 0900 addi s0,sp,144 - 80c8: 0004 0x4 - 80ca: 0001 nop - 80cc: 04cb0403 lb s0,76(s6) - 80d0: 04090003 lb zero,64(s2) - 80d4: 0100 addi s0,sp,128 - 80d6: 0300 addi s0,sp,384 - 80d8: cb04 sw s1,16(a4) - 80da: 0304 addi s1,sp,384 - 80dc: 0900 addi s0,sp,144 - 80de: 0000 unimp - 80e0: 0001 nop - 80e2: 04cb0403 lb s0,76(s6) - 80e6: 00090003 lb zero,0(s2) - 80ea: 0100 addi s0,sp,128 - 80ec: 0300 addi s0,sp,384 - 80ee: cc04 sw s1,24(s0) - 80f0: 0304 addi s1,sp,384 - 80f2: 0900 addi s0,sp,144 - 80f4: 0008 0x8 - 80f6: 0001 nop - 80f8: 04cc0403 lb s0,76(s8) - 80fc: 00090003 lb zero,0(s2) - 8100: 0100 addi s0,sp,128 - 8102: 0300 addi s0,sp,384 - 8104: cc04 sw s1,24(s0) - 8106: 0304 addi s1,sp,384 - 8108: 0900 addi s0,sp,144 - 810a: 0000 unimp - 810c: 0001 nop - 810e: 04cc0403 lb s0,76(s8) - 8112: 00090003 lb zero,0(s2) - 8116: 0100 addi s0,sp,128 - 8118: 0300 addi s0,sp,384 - 811a: cc04 sw s1,24(s0) - 811c: 0304 addi s1,sp,384 - 811e: 0900 addi s0,sp,144 - 8120: 0000 unimp - 8122: 0001 nop - 8124: 04cc0403 lb s0,76(s8) - 8128: 08090003 lb zero,128(s2) - 812c: 0100 addi s0,sp,128 - 812e: 0300 addi s0,sp,384 - 8130: cc04 sw s1,24(s0) - 8132: 0304 addi s1,sp,384 - 8134: 0900 addi s0,sp,144 - 8136: 0000 unimp - 8138: 0001 nop - 813a: 04cc0403 lb s0,76(s8) - 813e: 00090003 lb zero,0(s2) - 8142: 0100 addi s0,sp,128 - 8144: 0300 addi s0,sp,384 - 8146: cc04 sw s1,24(s0) - 8148: 0304 addi s1,sp,384 - 814a: 0900 addi s0,sp,144 - 814c: 0004 0x4 - 814e: 0001 nop - 8150: 04cc0403 lb s0,76(s8) - 8154: 08090003 lb zero,128(s2) - 8158: 0100 addi s0,sp,128 - 815a: 0300 addi s0,sp,384 - 815c: ce04 sw s1,24(a2) - 815e: 0604 addi s1,sp,768 - 8160: 08090003 lb zero,128(s2) - 8164: 0100 addi s0,sp,128 - 8166: 0300 addi s0,sp,384 - 8168: d304 sw s1,32(a4) - 816a: 0304 addi s1,sp,384 - 816c: 0900 addi s0,sp,144 - 816e: 0004 0x4 - 8170: 0001 nop - 8172: 04d30403 lb s0,77(t1) - 8176: 0306 slli t1,t1,0x1 - 8178: 0900 addi s0,sp,144 - 817a: 0008 0x8 - 817c: 0001 nop - 817e: 04d30403 lb s0,77(t1) - 8182: 00090003 lb zero,0(s2) - 8186: 0100 addi s0,sp,128 - 8188: 0300 addi s0,sp,384 - 818a: d304 sw s1,32(a4) - 818c: 0304 addi s1,sp,384 - 818e: 0900 addi s0,sp,144 - 8190: 0004 0x4 - 8192: 0001 nop - 8194: 04d30403 lb s0,77(t1) - 8198: 04090003 lb zero,64(s2) - 819c: 0100 addi s0,sp,128 - 819e: 0300 addi s0,sp,384 - 81a0: d404 sw s1,40(s0) - 81a2: 0604 addi s1,sp,768 - 81a4: 04090003 lb zero,64(s2) - 81a8: 0100 addi s0,sp,128 - 81aa: 0300 addi s0,sp,384 - 81ac: d904 sw s1,48(a0) - 81ae: 0604 addi s1,sp,768 - 81b0: 04090003 lb zero,64(s2) - 81b4: 0100 addi s0,sp,128 - 81b6: 0300 addi s0,sp,384 - 81b8: d904 sw s1,48(a0) - 81ba: 0304 addi s1,sp,384 - 81bc: 0900 addi s0,sp,144 - 81be: 0010 0x10 - 81c0: 0001 nop - 81c2: 04d90403 lb s0,77(s2) - 81c6: 04090003 lb zero,64(s2) - 81ca: 0100 addi s0,sp,128 - 81cc: 0300 addi s0,sp,384 - 81ce: d904 sw s1,48(a0) - 81d0: 0304 addi s1,sp,384 - 81d2: 0900 addi s0,sp,144 - 81d4: 0004 0x4 - 81d6: 0001 nop - 81d8: 04d90403 lb s0,77(s2) - 81dc: 04090003 lb zero,64(s2) - 81e0: 0100 addi s0,sp,128 - 81e2: 0300 addi s0,sp,384 - 81e4: d904 sw s1,48(a0) - 81e6: 0304 addi s1,sp,384 - 81e8: 0900 addi s0,sp,144 - 81ea: 0000 unimp - 81ec: 0001 nop - 81ee: 04e10403 lb s0,78(sp) - 81f2: 04090003 lb zero,64(s2) - 81f6: 0100 addi s0,sp,128 - 81f8: 0300 addi s0,sp,384 - 81fa: e104 fsw fs1,0(a0) - 81fc: 0304 addi s1,sp,384 - 81fe: 0900 addi s0,sp,144 - 8200: 0000 unimp - 8202: 0001 nop - 8204: 04e40403 lb s0,78(s0) - 8208: 08090003 lb zero,128(s2) - 820c: 0100 addi s0,sp,128 - 820e: 0300 addi s0,sp,384 - 8210: e404 fsw fs1,8(s0) - 8212: 0304 addi s1,sp,384 - 8214: 0900 addi s0,sp,144 - 8216: 0000 unimp - 8218: 0001 nop - 821a: 04e40403 lb s0,78(s0) - 821e: 00090003 lb zero,0(s2) - 8222: 0100 addi s0,sp,128 - 8224: 0300 addi s0,sp,384 - 8226: e404 fsw fs1,8(s0) - 8228: 0304 addi s1,sp,384 - 822a: 0900 addi s0,sp,144 - 822c: 0000 unimp - 822e: 0001 nop - 8230: 04e40403 lb s0,78(s0) - 8234: 04090003 lb zero,64(s2) - 8238: 0100 addi s0,sp,128 - 823a: 0300 addi s0,sp,384 - 823c: 8604 0x8604 - 823e: 0305 addi t1,t1,1 - 8240: 0900 addi s0,sp,144 - 8242: 0000 unimp - 8244: 0001 nop - 8246: 05860403 lb s0,88(a2) - 824a: 00090003 lb zero,0(s2) + 7a3c: 0300 addi s0,sp,384 + 7a3e: c204 sw s1,0(a2) + 7a40: 00030603 lb a2,0(t1) + 7a44: 0809 addi a6,a6,2 + 7a46: 0100 addi s0,sp,128 + 7a48: 0300 addi s0,sp,384 + 7a4a: c204 sw s1,0(a2) + 7a4c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7a50: 0008 0x8 + 7a52: 0001 nop + 7a54: 03c20403 lb s0,60(tp) # 3c <_start-0x7fffffc4> + 7a58: 04090003 lb zero,64(s2) + 7a5c: 0100 addi s0,sp,128 + 7a5e: 0300 addi s0,sp,384 + 7a60: c204 sw s1,0(a2) + 7a62: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7a66: 0004 0x4 + 7a68: 0001 nop + 7a6a: 03c30403 lb s0,60(t1) + 7a6e: 0306 slli t1,t1,0x1 + 7a70: 0900 addi s0,sp,144 + 7a72: 0004 0x4 + 7a74: 0001 nop + 7a76: 03c80403 lb s0,60(a6) + 7a7a: 0306 slli t1,t1,0x1 + 7a7c: 0900 addi s0,sp,144 + 7a7e: 0008 0x8 + 7a80: 0001 nop + 7a82: 03c80403 lb s0,60(a6) + 7a86: 18090003 lb zero,384(s2) + 7a8a: 0100 addi s0,sp,128 + 7a8c: 0300 addi s0,sp,384 + 7a8e: c804 sw s1,16(s0) + 7a90: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7a94: 0000 unimp + 7a96: 0001 nop + 7a98: 03c80403 lb s0,60(a6) + 7a9c: 04090003 lb zero,64(s2) + 7aa0: 0100 addi s0,sp,128 + 7aa2: 0300 addi s0,sp,384 + 7aa4: c804 sw s1,16(s0) + 7aa6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7aaa: 0004 0x4 + 7aac: 0001 nop + 7aae: 03c80403 lb s0,60(a6) + 7ab2: 0306 slli t1,t1,0x1 + 7ab4: 097f 0x97f + 7ab6: 0000 unimp + 7ab8: 0601 addi a2,a2,0 + 7aba: 0c090103 lb sp,192(s2) + 7abe: 0100 addi s0,sp,128 + 7ac0: 0300 addi s0,sp,384 + 7ac2: f404 fsw fs1,40(s0) + 7ac4: 0302 c.slli64 t1 + 7ac6: 0900 addi s0,sp,144 + 7ac8: 0014 0x14 + 7aca: 0001 nop + 7acc: 03c90403 lb s0,60(s2) + 7ad0: 20090003 lb zero,512(s2) + 7ad4: 0100 addi s0,sp,128 + 7ad6: 0300 addi s0,sp,384 + 7ad8: cb04 sw s1,16(a4) + 7ada: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7ade: 001c 0x1c + 7ae0: 0001 nop + 7ae2: 03cb0403 lb s0,60(s6) + 7ae6: 00090003 lb zero,0(s2) + 7aea: 0100 addi s0,sp,128 + 7aec: 0300 addi s0,sp,384 + 7aee: cd04 sw s1,24(a0) + 7af0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7af4: 0004 0x4 + 7af6: 0001 nop + 7af8: 03cd0403 lb s0,60(s10) + 7afc: 10090003 lb zero,256(s2) + 7b00: 0100 addi s0,sp,128 + 7b02: 0306 slli t1,t1,0x1 + 7b04: 0900 addi s0,sp,144 + 7b06: 0008 0x8 + 7b08: 0001 nop + 7b0a: 03ce0403 lb s0,60(t3) + 7b0e: 0306 slli t1,t1,0x1 + 7b10: 0900 addi s0,sp,144 + 7b12: 000c 0xc + 7b14: 0001 nop + 7b16: 03d40403 lb s0,61(s0) + 7b1a: 04090003 lb zero,64(s2) + 7b1e: 0100 addi s0,sp,128 + 7b20: 0300 addi s0,sp,384 + 7b22: d404 sw s1,40(s0) + 7b24: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7b28: 0000 unimp + 7b2a: 0001 nop + 7b2c: 03d50403 lb s0,61(a0) + 7b30: 10090003 lb zero,256(s2) + 7b34: 0100 addi s0,sp,128 + 7b36: 0300 addi s0,sp,384 + 7b38: d504 sw s1,40(a0) + 7b3a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7b3e: 0000 unimp + 7b40: 0001 nop + 7b42: 03d50403 lb s0,61(a0) + 7b46: 00090003 lb zero,0(s2) + 7b4a: 0100 addi s0,sp,128 + 7b4c: 0300 addi s0,sp,384 + 7b4e: d504 sw s1,40(a0) + 7b50: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7b54: 0000 unimp + 7b56: 0001 nop + 7b58: 03d50403 lb s0,61(a0) + 7b5c: 00090003 lb zero,0(s2) + 7b60: 0100 addi s0,sp,128 + 7b62: 0300 addi s0,sp,384 + 7b64: d504 sw s1,40(a0) + 7b66: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7b6a: 0000 unimp + 7b6c: 0001 nop + 7b6e: 03d50403 lb s0,61(a0) + 7b72: 04090003 lb zero,64(s2) + 7b76: 0100 addi s0,sp,128 + 7b78: 0300 addi s0,sp,384 + 7b7a: d504 sw s1,40(a0) + 7b7c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7b80: 0000 unimp + 7b82: 0001 nop + 7b84: 03d50403 lb s0,61(a0) + 7b88: 04090003 lb zero,64(s2) + 7b8c: 0100 addi s0,sp,128 + 7b8e: 0300 addi s0,sp,384 + 7b90: d504 sw s1,40(a0) + 7b92: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7b96: 0008 0x8 + 7b98: 0001 nop + 7b9a: 03d50403 lb s0,61(a0) + 7b9e: 04090003 lb zero,64(s2) + 7ba2: 0100 addi s0,sp,128 + 7ba4: 0300 addi s0,sp,384 + 7ba6: d704 sw s1,40(a4) + 7ba8: 00030603 lb a2,0(t1) + 7bac: 0809 addi a6,a6,2 + 7bae: 0100 addi s0,sp,128 + 7bb0: 0300 addi s0,sp,384 + 7bb2: dc04 sw s1,56(s0) + 7bb4: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7bb8: 0004 0x4 + 7bba: 0001 nop + 7bbc: 03dc0403 lb s0,61(s8) + 7bc0: 0306 slli t1,t1,0x1 + 7bc2: 0900 addi s0,sp,144 + 7bc4: 0008 0x8 + 7bc6: 0001 nop + 7bc8: 03dc0403 lb s0,61(s8) + 7bcc: 00090003 lb zero,0(s2) + 7bd0: 0100 addi s0,sp,128 + 7bd2: 0300 addi s0,sp,384 + 7bd4: dc04 sw s1,56(s0) + 7bd6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7bda: 0004 0x4 + 7bdc: 0001 nop + 7bde: 03dc0403 lb s0,61(s8) + 7be2: 04090003 lb zero,64(s2) + 7be6: 0100 addi s0,sp,128 + 7be8: 0300 addi s0,sp,384 + 7bea: dd04 sw s1,56(a0) + 7bec: 00030603 lb a2,0(t1) + 7bf0: 0809 addi a6,a6,2 + 7bf2: 0100 addi s0,sp,128 + 7bf4: 0300 addi s0,sp,384 + 7bf6: e204 fsw fs1,0(a2) + 7bf8: 00030603 lb a2,0(t1) + 7bfc: 0409 addi s0,s0,2 + 7bfe: 0100 addi s0,sp,128 + 7c00: 0300 addi s0,sp,384 + 7c02: e204 fsw fs1,0(a2) + 7c04: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7c08: 0010 0x10 + 7c0a: 0001 nop + 7c0c: 03e20403 lb s0,62(tp) # 3e <_start-0x7fffffc2> + 7c10: 04090003 lb zero,64(s2) + 7c14: 0100 addi s0,sp,128 + 7c16: 0300 addi s0,sp,384 + 7c18: e204 fsw fs1,0(a2) + 7c1a: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7c1e: 0004 0x4 + 7c20: 0001 nop + 7c22: 03e20403 lb s0,62(tp) # 3e <_start-0x7fffffc2> + 7c26: 04090003 lb zero,64(s2) + 7c2a: 0100 addi s0,sp,128 + 7c2c: 0300 addi s0,sp,384 + 7c2e: e204 fsw fs1,0(a2) + 7c30: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7c34: 0000 unimp + 7c36: 0001 nop + 7c38: 03e20403 lb s0,62(tp) # 3e <_start-0x7fffffc2> + 7c3c: 00090003 lb zero,0(s2) + 7c40: 0100 addi s0,sp,128 + 7c42: 0300 addi s0,sp,384 + 7c44: e304 fsw fs1,0(a4) + 7c46: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7c4a: 0008 0x8 + 7c4c: 0001 nop + 7c4e: 03e30403 lb s0,62(t1) + 7c52: 00090003 lb zero,0(s2) + 7c56: 0100 addi s0,sp,128 + 7c58: 0300 addi s0,sp,384 + 7c5a: e304 fsw fs1,0(a4) + 7c5c: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7c60: 0000 unimp + 7c62: 0001 nop + 7c64: 03e30403 lb s0,62(t1) + 7c68: 00090003 lb zero,0(s2) + 7c6c: 0100 addi s0,sp,128 + 7c6e: 0300 addi s0,sp,384 + 7c70: e304 fsw fs1,0(a4) + 7c72: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7c76: 0000 unimp + 7c78: 0001 nop + 7c7a: 03e30403 lb s0,62(t1) + 7c7e: 08090003 lb zero,128(s2) + 7c82: 0100 addi s0,sp,128 + 7c84: 0300 addi s0,sp,384 + 7c86: e304 fsw fs1,0(a4) + 7c88: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7c8c: 0000 unimp + 7c8e: 0001 nop + 7c90: 03e30403 lb s0,62(t1) + 7c94: 00090003 lb zero,0(s2) + 7c98: 0100 addi s0,sp,128 + 7c9a: 0300 addi s0,sp,384 + 7c9c: e304 fsw fs1,0(a4) + 7c9e: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7ca2: 0004 0x4 + 7ca4: 0001 nop + 7ca6: 03e30403 lb s0,62(t1) + 7caa: 08090003 lb zero,128(s2) + 7cae: 0100 addi s0,sp,128 + 7cb0: 0300 addi s0,sp,384 + 7cb2: e504 fsw fs1,8(a0) + 7cb4: 00030603 lb a2,0(t1) + 7cb8: 0809 addi a6,a6,2 + 7cba: 0100 addi s0,sp,128 + 7cbc: 0300 addi s0,sp,384 + 7cbe: ea04 fsw fs1,16(a2) + 7cc0: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7cc4: 0004 0x4 + 7cc6: 0001 nop + 7cc8: 03ea0403 lb s0,62(s4) + 7ccc: 0306 slli t1,t1,0x1 + 7cce: 0900 addi s0,sp,144 + 7cd0: 0004 0x4 + 7cd2: 0001 nop + 7cd4: 03ea0403 lb s0,62(s4) + 7cd8: 04090003 lb zero,64(s2) + 7cdc: 0100 addi s0,sp,128 + 7cde: 0300 addi s0,sp,384 + 7ce0: ea04 fsw fs1,16(a2) + 7ce2: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7ce6: 0004 0x4 + 7ce8: 0001 nop + 7cea: 03ea0403 lb s0,62(s4) + 7cee: 08090003 lb zero,128(s2) + 7cf2: 0100 addi s0,sp,128 + 7cf4: 0300 addi s0,sp,384 + 7cf6: eb04 fsw fs1,16(a4) + 7cf8: 00030603 lb a2,0(t1) + 7cfc: 0409 addi s0,s0,2 + 7cfe: 0100 addi s0,sp,128 + 7d00: 0300 addi s0,sp,384 + 7d02: f004 fsw fs1,32(s0) + 7d04: 00030603 lb a2,0(t1) + 7d08: 0409 addi s0,s0,2 + 7d0a: 0100 addi s0,sp,128 + 7d0c: 0300 addi s0,sp,384 + 7d0e: f004 fsw fs1,32(s0) + 7d10: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7d14: 0010 0x10 + 7d16: 0001 nop + 7d18: 03f00403 lb s0,63(zero) # 3f <_start-0x7fffffc1> + 7d1c: 04090003 lb zero,64(s2) + 7d20: 0100 addi s0,sp,128 + 7d22: 0300 addi s0,sp,384 + 7d24: f004 fsw fs1,32(s0) + 7d26: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7d2a: 0004 0x4 + 7d2c: 0001 nop + 7d2e: 03e40403 lb s0,62(s0) + 7d32: 08090003 lb zero,128(s2) + 7d36: 0100 addi s0,sp,128 + 7d38: 0300 addi s0,sp,384 + 7d3a: 8304 0x8304 + 7d3c: 0304 addi s1,sp,384 + 7d3e: 0900 addi s0,sp,144 + 7d40: 0010 0x10 + 7d42: 0001 nop + 7d44: 04830403 lb s0,72(t1) + 7d48: 00090003 lb zero,0(s2) + 7d4c: 0100 addi s0,sp,128 + 7d4e: 0300 addi s0,sp,384 + 7d50: 8304 0x8304 + 7d52: 0304 addi s1,sp,384 + 7d54: 0900 addi s0,sp,144 + 7d56: 0000 unimp + 7d58: 0001 nop + 7d5a: 04830403 lb s0,72(t1) + 7d5e: 00090003 lb zero,0(s2) + 7d62: 0100 addi s0,sp,128 + 7d64: 0300 addi s0,sp,384 + 7d66: 8304 0x8304 + 7d68: 0304 addi s1,sp,384 + 7d6a: 0900 addi s0,sp,144 + 7d6c: 0000 unimp + 7d6e: 0001 nop + 7d70: 04830403 lb s0,72(t1) + 7d74: 00090003 lb zero,0(s2) + 7d78: 0100 addi s0,sp,128 + 7d7a: 0300 addi s0,sp,384 + 7d7c: 8304 0x8304 + 7d7e: 0304 addi s1,sp,384 + 7d80: 0900 addi s0,sp,144 + 7d82: 0000 unimp + 7d84: 0001 nop + 7d86: 04830403 lb s0,72(t1) + 7d8a: 00090003 lb zero,0(s2) + 7d8e: 0100 addi s0,sp,128 + 7d90: 0300 addi s0,sp,384 + 7d92: 8404 0x8404 + 7d94: 0304 addi s1,sp,384 + 7d96: 0900 addi s0,sp,144 + 7d98: 0008 0x8 + 7d9a: 0001 nop + 7d9c: 04860403 lb s0,72(a2) + 7da0: 04090003 lb zero,64(s2) + 7da4: 0100 addi s0,sp,128 + 7da6: 0300 addi s0,sp,384 + 7da8: 8604 0x8604 + 7daa: 0304 addi s1,sp,384 + 7dac: 0900 addi s0,sp,144 + 7dae: 0000 unimp + 7db0: 0001 nop + 7db2: 04860403 lb s0,72(a2) + 7db6: 10090003 lb zero,256(s2) + 7dba: 0100 addi s0,sp,128 + 7dbc: 0300 addi s0,sp,384 + 7dbe: 8604 0x8604 + 7dc0: 0304 addi s1,sp,384 + 7dc2: 0900 addi s0,sp,144 + 7dc4: 0000 unimp + 7dc6: 0001 nop + 7dc8: 04860403 lb s0,72(a2) + 7dcc: 00090003 lb zero,0(s2) + 7dd0: 0100 addi s0,sp,128 + 7dd2: 0300 addi s0,sp,384 + 7dd4: 8604 0x8604 + 7dd6: 0304 addi s1,sp,384 + 7dd8: 0900 addi s0,sp,144 + 7dda: 0000 unimp + 7ddc: 0001 nop + 7dde: 04860403 lb s0,72(a2) + 7de2: 00090003 lb zero,0(s2) + 7de6: 0100 addi s0,sp,128 + 7de8: 0300 addi s0,sp,384 + 7dea: 8604 0x8604 + 7dec: 0304 addi s1,sp,384 + 7dee: 0900 addi s0,sp,144 + 7df0: 0000 unimp + 7df2: 0001 nop + 7df4: 04860403 lb s0,72(a2) + 7df8: 00090003 lb zero,0(s2) + 7dfc: 0100 addi s0,sp,128 + 7dfe: 0300 addi s0,sp,384 + 7e00: 8604 0x8604 + 7e02: 0304 addi s1,sp,384 + 7e04: 0900 addi s0,sp,144 + 7e06: 0000 unimp + 7e08: 0001 nop + 7e0a: 04860403 lb s0,72(a2) + 7e0e: 00090003 lb zero,0(s2) + 7e12: 0100 addi s0,sp,128 + 7e14: 0300 addi s0,sp,384 + 7e16: 8f04 0x8f04 + 7e18: 0304 addi s1,sp,384 + 7e1a: 0900 addi s0,sp,144 + 7e1c: 0004 0x4 + 7e1e: 0001 nop + 7e20: 048f0403 lb s0,72(t5) + 7e24: 1c090003 lb zero,448(s2) + 7e28: 0100 addi s0,sp,128 + 7e2a: 0300 addi s0,sp,384 + 7e2c: 8f04 0x8f04 + 7e2e: 0304 addi s1,sp,384 + 7e30: 0900 addi s0,sp,144 + 7e32: 0000 unimp + 7e34: 0001 nop + 7e36: 04870403 lb s0,72(a4) + 7e3a: 08090003 lb zero,128(s2) + 7e3e: 0100 addi s0,sp,128 + 7e40: 0300 addi s0,sp,384 + 7e42: 8704 0x8704 + 7e44: 0304 addi s1,sp,384 + 7e46: 0900 addi s0,sp,144 + 7e48: 0000 unimp + 7e4a: 0001 nop + 7e4c: 04950403 lb s0,73(a0) + 7e50: 0306 slli t1,t1,0x1 + 7e52: 0900 addi s0,sp,144 + 7e54: 0014 0x14 + 7e56: 0001 nop + 7e58: 04850403 lb s0,72(a0) + 7e5c: 0306 slli t1,t1,0x1 + 7e5e: 0900 addi s0,sp,144 + 7e60: 0008 0x8 + 7e62: 0001 nop + 7e64: 04950403 lb s0,73(a0) + 7e68: 04090003 lb zero,64(s2) + 7e6c: 0100 addi s0,sp,128 + 7e6e: 0300 addi s0,sp,384 + 7e70: 9504 0x9504 + 7e72: 0304 addi s1,sp,384 + 7e74: 0900 addi s0,sp,144 + 7e76: 0000 unimp + 7e78: 0001 nop + 7e7a: 049d0403 lb s0,73(s10) + 7e7e: 14090003 lb zero,320(s2) + 7e82: 0100 addi s0,sp,128 + 7e84: 0300 addi s0,sp,384 + 7e86: 9d04 0x9d04 + 7e88: 0304 addi s1,sp,384 + 7e8a: 0900 addi s0,sp,144 + 7e8c: 0000 unimp + 7e8e: 0001 nop + 7e90: 049d0403 lb s0,73(s10) + 7e94: 00090003 lb zero,0(s2) + 7e98: 0100 addi s0,sp,128 + 7e9a: 0300 addi s0,sp,384 + 7e9c: 9d04 0x9d04 + 7e9e: 0304 addi s1,sp,384 + 7ea0: 0900 addi s0,sp,144 + 7ea2: 0000 unimp + 7ea4: 0001 nop + 7ea6: 049d0403 lb s0,73(s10) + 7eaa: 00090003 lb zero,0(s2) + 7eae: 0100 addi s0,sp,128 + 7eb0: 0300 addi s0,sp,384 + 7eb2: 9d04 0x9d04 + 7eb4: 0304 addi s1,sp,384 + 7eb6: 0900 addi s0,sp,144 + 7eb8: 0000 unimp + 7eba: 0001 nop + 7ebc: 049d0403 lb s0,73(s10) + 7ec0: 00090003 lb zero,0(s2) + 7ec4: 0100 addi s0,sp,128 + 7ec6: 0300 addi s0,sp,384 + 7ec8: 9d04 0x9d04 + 7eca: 0304 addi s1,sp,384 + 7ecc: 0900 addi s0,sp,144 + 7ece: 0000 unimp + 7ed0: 0001 nop + 7ed2: 049d0403 lb s0,73(s10) + 7ed6: 00090003 lb zero,0(s2) + 7eda: 0100 addi s0,sp,128 + 7edc: 0300 addi s0,sp,384 + 7ede: 9d04 0x9d04 + 7ee0: 0304 addi s1,sp,384 + 7ee2: 0900 addi s0,sp,144 + 7ee4: 0000 unimp + 7ee6: 0001 nop + 7ee8: 049d0403 lb s0,73(s10) + 7eec: 10090003 lb zero,256(s2) + 7ef0: 0100 addi s0,sp,128 + 7ef2: 0300 addi s0,sp,384 + 7ef4: 9d04 0x9d04 + 7ef6: 0304 addi s1,sp,384 + 7ef8: 0900 addi s0,sp,144 + 7efa: 0000 unimp + 7efc: 0001 nop + 7efe: 049d0403 lb s0,73(s10) + 7f02: 00090003 lb zero,0(s2) + 7f06: 0100 addi s0,sp,128 + 7f08: 0300 addi s0,sp,384 + 7f0a: 9d04 0x9d04 + 7f0c: 0304 addi s1,sp,384 + 7f0e: 0900 addi s0,sp,144 + 7f10: 0000 unimp + 7f12: 0001 nop + 7f14: 049d0403 lb s0,73(s10) + 7f18: 00090003 lb zero,0(s2) + 7f1c: 0100 addi s0,sp,128 + 7f1e: 0300 addi s0,sp,384 + 7f20: 9d04 0x9d04 + 7f22: 0304 addi s1,sp,384 + 7f24: 0900 addi s0,sp,144 + 7f26: 0000 unimp + 7f28: 0001 nop + 7f2a: 049d0403 lb s0,73(s10) + 7f2e: 00090003 lb zero,0(s2) + 7f32: 0100 addi s0,sp,128 + 7f34: 0300 addi s0,sp,384 + 7f36: 9d04 0x9d04 + 7f38: 0304 addi s1,sp,384 + 7f3a: 0900 addi s0,sp,144 + 7f3c: 0000 unimp + 7f3e: 0001 nop + 7f40: 049d0403 lb s0,73(s10) + 7f44: 00090003 lb zero,0(s2) + 7f48: 0100 addi s0,sp,128 + 7f4a: 0300 addi s0,sp,384 + 7f4c: 9d04 0x9d04 + 7f4e: 0304 addi s1,sp,384 + 7f50: 0900 addi s0,sp,144 + 7f52: 0000 unimp + 7f54: 0001 nop + 7f56: 049d0403 lb s0,73(s10) + 7f5a: 00090003 lb zero,0(s2) + 7f5e: 0100 addi s0,sp,128 + 7f60: 0300 addi s0,sp,384 + 7f62: b904 fsd fs1,48(a0) + 7f64: 0304 addi s1,sp,384 + 7f66: 0900 addi s0,sp,144 + 7f68: 0004 0x4 + 7f6a: 0001 nop + 7f6c: 04b90403 lb s0,75(s2) + 7f70: 1c090003 lb zero,448(s2) + 7f74: 0100 addi s0,sp,128 + 7f76: 0300 addi s0,sp,384 + 7f78: b904 fsd fs1,48(a0) + 7f7a: 0304 addi s1,sp,384 + 7f7c: 0900 addi s0,sp,144 + 7f7e: 0000 unimp + 7f80: 0001 nop + 7f82: 03ca0403 lb s0,60(s4) + 7f86: 08090003 lb zero,128(s2) + 7f8a: 0100 addi s0,sp,128 + 7f8c: 0300 addi s0,sp,384 + 7f8e: ca04 sw s1,16(a2) + 7f90: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7f94: 0000 unimp + 7f96: 0001 nop + 7f98: 03ca0403 lb s0,60(s4) + 7f9c: 00090003 lb zero,0(s2) + 7fa0: 0100 addi s0,sp,128 + 7fa2: 0300 addi s0,sp,384 + 7fa4: ca04 sw s1,16(a2) + 7fa6: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7faa: 0000 unimp + 7fac: 0001 nop + 7fae: 03ca0403 lb s0,60(s4) + 7fb2: 00090003 lb zero,0(s2) + 7fb6: 0100 addi s0,sp,128 + 7fb8: 0300 addi s0,sp,384 + 7fba: ca04 sw s1,16(a2) + 7fbc: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7fc0: 0000 unimp + 7fc2: 0001 nop + 7fc4: 03ca0403 lb s0,60(s4) + 7fc8: 04090003 lb zero,64(s2) + 7fcc: 0100 addi s0,sp,128 + 7fce: 0300 addi s0,sp,384 + 7fd0: ca04 sw s1,16(a2) + 7fd2: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7fd6: 0000 unimp + 7fd8: 0001 nop + 7fda: 03ca0403 lb s0,60(s4) + 7fde: 04090003 lb zero,64(s2) + 7fe2: 0100 addi s0,sp,128 + 7fe4: 0300 addi s0,sp,384 + 7fe6: ca04 sw s1,16(a2) + 7fe8: 09000303 lb t1,144(zero) # 90 <_start-0x7fffff70> + 7fec: 0008 0x8 + 7fee: 0001 nop + 7ff0: 03ca0403 lb s0,60(s4) + 7ff4: 04090003 lb zero,64(s2) + 7ff8: 0100 addi s0,sp,128 + 7ffa: 0300 addi s0,sp,384 + 7ffc: c004 sw s1,0(s0) + 7ffe: 0604 addi s1,sp,768 + 8000: 08090003 lb zero,128(s2) + 8004: 0100 addi s0,sp,128 + 8006: 0300 addi s0,sp,384 + 8008: c504 sw s1,8(a0) + 800a: 0304 addi s1,sp,384 + 800c: 0900 addi s0,sp,144 + 800e: 0004 0x4 + 8010: 0001 nop + 8012: 04c50403 lb s0,76(a0) + 8016: 0306 slli t1,t1,0x1 + 8018: 0900 addi s0,sp,144 + 801a: 0008 0x8 + 801c: 0001 nop + 801e: 04c50403 lb s0,76(a0) + 8022: 00090003 lb zero,0(s2) + 8026: 0100 addi s0,sp,128 + 8028: 0300 addi s0,sp,384 + 802a: c504 sw s1,8(a0) + 802c: 0304 addi s1,sp,384 + 802e: 0900 addi s0,sp,144 + 8030: 0004 0x4 + 8032: 0001 nop + 8034: 04c50403 lb s0,76(a0) + 8038: 04090003 lb zero,64(s2) + 803c: 0100 addi s0,sp,128 + 803e: 0300 addi s0,sp,384 + 8040: c604 sw s1,8(a2) + 8042: 0604 addi s1,sp,768 + 8044: 08090003 lb zero,128(s2) + 8048: 0100 addi s0,sp,128 + 804a: 0300 addi s0,sp,384 + 804c: cb04 sw s1,16(a4) + 804e: 0604 addi s1,sp,768 + 8050: 04090003 lb zero,64(s2) + 8054: 0100 addi s0,sp,128 + 8056: 0300 addi s0,sp,384 + 8058: cb04 sw s1,16(a4) + 805a: 0304 addi s1,sp,384 + 805c: 0900 addi s0,sp,144 + 805e: 0010 0x10 + 8060: 0001 nop + 8062: 04cb0403 lb s0,76(s6) + 8066: 04090003 lb zero,64(s2) + 806a: 0100 addi s0,sp,128 + 806c: 0300 addi s0,sp,384 + 806e: cb04 sw s1,16(a4) + 8070: 0304 addi s1,sp,384 + 8072: 0900 addi s0,sp,144 + 8074: 0004 0x4 + 8076: 0001 nop + 8078: 04cb0403 lb s0,76(s6) + 807c: 04090003 lb zero,64(s2) + 8080: 0100 addi s0,sp,128 + 8082: 0300 addi s0,sp,384 + 8084: cb04 sw s1,16(a4) + 8086: 0304 addi s1,sp,384 + 8088: 0900 addi s0,sp,144 + 808a: 0000 unimp + 808c: 0001 nop + 808e: 04cb0403 lb s0,76(s6) + 8092: 00090003 lb zero,0(s2) + 8096: 0100 addi s0,sp,128 + 8098: 0300 addi s0,sp,384 + 809a: cc04 sw s1,24(s0) + 809c: 0304 addi s1,sp,384 + 809e: 0900 addi s0,sp,144 + 80a0: 0008 0x8 + 80a2: 0001 nop + 80a4: 04cc0403 lb s0,76(s8) + 80a8: 00090003 lb zero,0(s2) + 80ac: 0100 addi s0,sp,128 + 80ae: 0300 addi s0,sp,384 + 80b0: cc04 sw s1,24(s0) + 80b2: 0304 addi s1,sp,384 + 80b4: 0900 addi s0,sp,144 + 80b6: 0000 unimp + 80b8: 0001 nop + 80ba: 04cc0403 lb s0,76(s8) + 80be: 00090003 lb zero,0(s2) + 80c2: 0100 addi s0,sp,128 + 80c4: 0300 addi s0,sp,384 + 80c6: cc04 sw s1,24(s0) + 80c8: 0304 addi s1,sp,384 + 80ca: 0900 addi s0,sp,144 + 80cc: 0000 unimp + 80ce: 0001 nop + 80d0: 04cc0403 lb s0,76(s8) + 80d4: 08090003 lb zero,128(s2) + 80d8: 0100 addi s0,sp,128 + 80da: 0300 addi s0,sp,384 + 80dc: cc04 sw s1,24(s0) + 80de: 0304 addi s1,sp,384 + 80e0: 0900 addi s0,sp,144 + 80e2: 0000 unimp + 80e4: 0001 nop + 80e6: 04cc0403 lb s0,76(s8) + 80ea: 00090003 lb zero,0(s2) + 80ee: 0100 addi s0,sp,128 + 80f0: 0300 addi s0,sp,384 + 80f2: cc04 sw s1,24(s0) + 80f4: 0304 addi s1,sp,384 + 80f6: 0900 addi s0,sp,144 + 80f8: 0004 0x4 + 80fa: 0001 nop + 80fc: 04cc0403 lb s0,76(s8) + 8100: 08090003 lb zero,128(s2) + 8104: 0100 addi s0,sp,128 + 8106: 0300 addi s0,sp,384 + 8108: ce04 sw s1,24(a2) + 810a: 0604 addi s1,sp,768 + 810c: 08090003 lb zero,128(s2) + 8110: 0100 addi s0,sp,128 + 8112: 0300 addi s0,sp,384 + 8114: d304 sw s1,32(a4) + 8116: 0304 addi s1,sp,384 + 8118: 0900 addi s0,sp,144 + 811a: 0004 0x4 + 811c: 0001 nop + 811e: 04d30403 lb s0,77(t1) + 8122: 0306 slli t1,t1,0x1 + 8124: 0900 addi s0,sp,144 + 8126: 0008 0x8 + 8128: 0001 nop + 812a: 04d30403 lb s0,77(t1) + 812e: 00090003 lb zero,0(s2) + 8132: 0100 addi s0,sp,128 + 8134: 0300 addi s0,sp,384 + 8136: d304 sw s1,32(a4) + 8138: 0304 addi s1,sp,384 + 813a: 0900 addi s0,sp,144 + 813c: 0004 0x4 + 813e: 0001 nop + 8140: 04d30403 lb s0,77(t1) + 8144: 04090003 lb zero,64(s2) + 8148: 0100 addi s0,sp,128 + 814a: 0300 addi s0,sp,384 + 814c: d404 sw s1,40(s0) + 814e: 0604 addi s1,sp,768 + 8150: 04090003 lb zero,64(s2) + 8154: 0100 addi s0,sp,128 + 8156: 0300 addi s0,sp,384 + 8158: d904 sw s1,48(a0) + 815a: 0604 addi s1,sp,768 + 815c: 04090003 lb zero,64(s2) + 8160: 0100 addi s0,sp,128 + 8162: 0300 addi s0,sp,384 + 8164: d904 sw s1,48(a0) + 8166: 0304 addi s1,sp,384 + 8168: 0900 addi s0,sp,144 + 816a: 0010 0x10 + 816c: 0001 nop + 816e: 04d90403 lb s0,77(s2) + 8172: 04090003 lb zero,64(s2) + 8176: 0100 addi s0,sp,128 + 8178: 0300 addi s0,sp,384 + 817a: d904 sw s1,48(a0) + 817c: 0304 addi s1,sp,384 + 817e: 0900 addi s0,sp,144 + 8180: 0004 0x4 + 8182: 0001 nop + 8184: 04d90403 lb s0,77(s2) + 8188: 04090003 lb zero,64(s2) + 818c: 0100 addi s0,sp,128 + 818e: 0300 addi s0,sp,384 + 8190: d904 sw s1,48(a0) + 8192: 0304 addi s1,sp,384 + 8194: 0900 addi s0,sp,144 + 8196: 0000 unimp + 8198: 0001 nop + 819a: 04e10403 lb s0,78(sp) + 819e: 04090003 lb zero,64(s2) + 81a2: 0100 addi s0,sp,128 + 81a4: 0300 addi s0,sp,384 + 81a6: e104 fsw fs1,0(a0) + 81a8: 0304 addi s1,sp,384 + 81aa: 0900 addi s0,sp,144 + 81ac: 0000 unimp + 81ae: 0001 nop + 81b0: 04e40403 lb s0,78(s0) + 81b4: 08090003 lb zero,128(s2) + 81b8: 0100 addi s0,sp,128 + 81ba: 0300 addi s0,sp,384 + 81bc: e404 fsw fs1,8(s0) + 81be: 0304 addi s1,sp,384 + 81c0: 0900 addi s0,sp,144 + 81c2: 0000 unimp + 81c4: 0001 nop + 81c6: 04e40403 lb s0,78(s0) + 81ca: 00090003 lb zero,0(s2) + 81ce: 0100 addi s0,sp,128 + 81d0: 0300 addi s0,sp,384 + 81d2: e404 fsw fs1,8(s0) + 81d4: 0304 addi s1,sp,384 + 81d6: 0900 addi s0,sp,144 + 81d8: 0000 unimp + 81da: 0001 nop + 81dc: 04e40403 lb s0,78(s0) + 81e0: 04090003 lb zero,64(s2) + 81e4: 0100 addi s0,sp,128 + 81e6: 0300 addi s0,sp,384 + 81e8: 8604 0x8604 + 81ea: 0305 addi t1,t1,1 + 81ec: 0900 addi s0,sp,144 + 81ee: 0000 unimp + 81f0: 0001 nop + 81f2: 05860403 lb s0,88(a2) + 81f6: 00090003 lb zero,0(s2) + 81fa: 0100 addi s0,sp,128 + 81fc: 0300 addi s0,sp,384 + 81fe: 8604 0x8604 + 8200: 0305 addi t1,t1,1 + 8202: 0900 addi s0,sp,144 + 8204: 0004 0x4 + 8206: 0001 nop + 8208: 05860403 lb s0,88(a2) + 820c: 00090003 lb zero,0(s2) + 8210: 0100 addi s0,sp,128 + 8212: 0300 addi s0,sp,384 + 8214: 8604 0x8604 + 8216: 0305 addi t1,t1,1 + 8218: 0900 addi s0,sp,144 + 821a: 0000 unimp + 821c: 0001 nop + 821e: 05860403 lb s0,88(a2) + 8222: 00090003 lb zero,0(s2) + 8226: 0100 addi s0,sp,128 + 8228: 0300 addi s0,sp,384 + 822a: 8604 0x8604 + 822c: 0305 addi t1,t1,1 + 822e: 0900 addi s0,sp,144 + 8230: 000c 0xc + 8232: 0001 nop + 8234: 05860403 lb s0,88(a2) + 8238: 00090003 lb zero,0(s2) + 823c: 0100 addi s0,sp,128 + 823e: 0300 addi s0,sp,384 + 8240: 8604 0x8604 + 8242: 0305 addi t1,t1,1 + 8244: 0900 addi s0,sp,144 + 8246: 0000 unimp + 8248: 0601 addi a2,a2,0 + 824a: 10090003 lb zero,256(s2) 824e: 0100 addi s0,sp,128 8250: 0300 addi s0,sp,384 - 8252: 8604 0x8604 - 8254: 0305 addi t1,t1,1 - 8256: 0900 addi s0,sp,144 - 8258: 0004 0x4 - 825a: 0001 nop - 825c: 05860403 lb s0,88(a2) - 8260: 00090003 lb zero,0(s2) - 8264: 0100 addi s0,sp,128 - 8266: 0300 addi s0,sp,384 - 8268: 8604 0x8604 - 826a: 0305 addi t1,t1,1 - 826c: 0900 addi s0,sp,144 - 826e: 0000 unimp - 8270: 0001 nop - 8272: 05860403 lb s0,88(a2) - 8276: 00090003 lb zero,0(s2) - 827a: 0100 addi s0,sp,128 - 827c: 0300 addi s0,sp,384 - 827e: 8604 0x8604 - 8280: 0305 addi t1,t1,1 - 8282: 0900 addi s0,sp,144 - 8284: 000c 0xc - 8286: 0001 nop - 8288: 05860403 lb s0,88(a2) - 828c: 00090003 lb zero,0(s2) - 8290: 0100 addi s0,sp,128 - 8292: 0300 addi s0,sp,384 - 8294: 8604 0x8604 - 8296: 0305 addi t1,t1,1 - 8298: 0900 addi s0,sp,144 - 829a: 0000 unimp - 829c: 0601 addi a2,a2,0 - 829e: 10090003 lb zero,256(s2) - 82a2: 0100 addi s0,sp,128 - 82a4: 0300 addi s0,sp,384 - 82a6: 8c04 0x8c04 - 82a8: 0605 addi a2,a2,1 - 82aa: 14090003 lb zero,320(s2) - 82ae: 0100 addi s0,sp,128 - 82b0: 0300 addi s0,sp,384 - 82b2: 8f04 0x8f04 - 82b4: 0605 addi a2,a2,1 - 82b6: 04090003 lb zero,64(s2) - 82ba: 0100 addi s0,sp,128 - 82bc: 0300 addi s0,sp,384 - 82be: 8f04 0x8f04 - 82c0: 0605 addi a2,a2,1 - 82c2: 10090003 lb zero,256(s2) - 82c6: 0100 addi s0,sp,128 - 82c8: 0300 addi s0,sp,384 - 82ca: 9104 0x9104 - 82cc: 0605 addi a2,a2,1 - 82ce: 08090003 lb zero,128(s2) - 82d2: 0100 addi s0,sp,128 - 82d4: 0300 addi s0,sp,384 - 82d6: cd04 sw s1,24(a0) - 82d8: 0604 addi s1,sp,768 - 82da: 08090003 lb zero,128(s2) - 82de: 0100 addi s0,sp,128 - 82e0: 0300 addi s0,sp,384 - 82e2: e304 fsw fs1,0(a4) - 82e4: 0304 addi s1,sp,384 - 82e6: 0900 addi s0,sp,144 - 82e8: 0014 0x14 - 82ea: 0001 nop - 82ec: 04ed0403 lb s0,78(s10) - 82f0: 08090003 lb zero,128(s2) - 82f4: 0100 addi s0,sp,128 - 82f6: 0300 addi s0,sp,384 - 82f8: ed04 fsw fs1,24(a0) - 82fa: 0304 addi s1,sp,384 - 82fc: 0900 addi s0,sp,144 - 82fe: 0000 unimp - 8300: 0001 nop - 8302: 04ed0403 lb s0,78(s10) - 8306: 00090003 lb zero,0(s2) - 830a: 0100 addi s0,sp,128 - 830c: 0300 addi s0,sp,384 - 830e: ed04 fsw fs1,24(a0) - 8310: 0304 addi s1,sp,384 - 8312: 0900 addi s0,sp,144 - 8314: 0000 unimp - 8316: 0001 nop - 8318: 04ed0403 lb s0,78(s10) - 831c: 04090003 lb zero,64(s2) - 8320: 0100 addi s0,sp,128 - 8322: 0300 addi s0,sp,384 - 8324: ed04 fsw fs1,24(a0) - 8326: 0304 addi s1,sp,384 - 8328: 0900 addi s0,sp,144 - 832a: 0000 unimp - 832c: 0001 nop - 832e: 04ec0403 lb s0,78(s8) - 8332: 08090003 lb zero,128(s2) - 8336: 0100 addi s0,sp,128 - 8338: 0300 addi s0,sp,384 - 833a: f704 fsw fs1,40(a4) - 833c: 0304 addi s1,sp,384 - 833e: 0900 addi s0,sp,144 - 8340: 0008 0x8 - 8342: 0001 nop - 8344: 04f70403 lb s0,79(a4) - 8348: 00090003 lb zero,0(s2) - 834c: 0100 addi s0,sp,128 - 834e: 0300 addi s0,sp,384 - 8350: f704 fsw fs1,40(a4) - 8352: 0304 addi s1,sp,384 - 8354: 0900 addi s0,sp,144 - 8356: 0000 unimp - 8358: 0001 nop - 835a: 04f70403 lb s0,79(a4) - 835e: 00090003 lb zero,0(s2) - 8362: 0100 addi s0,sp,128 - 8364: 0300 addi s0,sp,384 - 8366: f704 fsw fs1,40(a4) - 8368: 0304 addi s1,sp,384 + 8252: 8c04 0x8c04 + 8254: 0605 addi a2,a2,1 + 8256: 14090003 lb zero,320(s2) + 825a: 0100 addi s0,sp,128 + 825c: 0300 addi s0,sp,384 + 825e: 8f04 0x8f04 + 8260: 0605 addi a2,a2,1 + 8262: 04090003 lb zero,64(s2) + 8266: 0100 addi s0,sp,128 + 8268: 0300 addi s0,sp,384 + 826a: 8f04 0x8f04 + 826c: 0605 addi a2,a2,1 + 826e: 10090003 lb zero,256(s2) + 8272: 0100 addi s0,sp,128 + 8274: 0300 addi s0,sp,384 + 8276: 9104 0x9104 + 8278: 0605 addi a2,a2,1 + 827a: 08090003 lb zero,128(s2) + 827e: 0100 addi s0,sp,128 + 8280: 0300 addi s0,sp,384 + 8282: cd04 sw s1,24(a0) + 8284: 0604 addi s1,sp,768 + 8286: 08090003 lb zero,128(s2) + 828a: 0100 addi s0,sp,128 + 828c: 0300 addi s0,sp,384 + 828e: e304 fsw fs1,0(a4) + 8290: 0304 addi s1,sp,384 + 8292: 0900 addi s0,sp,144 + 8294: 0014 0x14 + 8296: 0001 nop + 8298: 04ed0403 lb s0,78(s10) + 829c: 08090003 lb zero,128(s2) + 82a0: 0100 addi s0,sp,128 + 82a2: 0300 addi s0,sp,384 + 82a4: ed04 fsw fs1,24(a0) + 82a6: 0304 addi s1,sp,384 + 82a8: 0900 addi s0,sp,144 + 82aa: 0000 unimp + 82ac: 0001 nop + 82ae: 04ed0403 lb s0,78(s10) + 82b2: 00090003 lb zero,0(s2) + 82b6: 0100 addi s0,sp,128 + 82b8: 0300 addi s0,sp,384 + 82ba: ed04 fsw fs1,24(a0) + 82bc: 0304 addi s1,sp,384 + 82be: 0900 addi s0,sp,144 + 82c0: 0000 unimp + 82c2: 0001 nop + 82c4: 04ed0403 lb s0,78(s10) + 82c8: 04090003 lb zero,64(s2) + 82cc: 0100 addi s0,sp,128 + 82ce: 0300 addi s0,sp,384 + 82d0: ed04 fsw fs1,24(a0) + 82d2: 0304 addi s1,sp,384 + 82d4: 0900 addi s0,sp,144 + 82d6: 0000 unimp + 82d8: 0001 nop + 82da: 04ec0403 lb s0,78(s8) + 82de: 08090003 lb zero,128(s2) + 82e2: 0100 addi s0,sp,128 + 82e4: 0300 addi s0,sp,384 + 82e6: f704 fsw fs1,40(a4) + 82e8: 0304 addi s1,sp,384 + 82ea: 0900 addi s0,sp,144 + 82ec: 0008 0x8 + 82ee: 0001 nop + 82f0: 04f70403 lb s0,79(a4) + 82f4: 00090003 lb zero,0(s2) + 82f8: 0100 addi s0,sp,128 + 82fa: 0300 addi s0,sp,384 + 82fc: f704 fsw fs1,40(a4) + 82fe: 0304 addi s1,sp,384 + 8300: 0900 addi s0,sp,144 + 8302: 0000 unimp + 8304: 0001 nop + 8306: 04f70403 lb s0,79(a4) + 830a: 00090003 lb zero,0(s2) + 830e: 0100 addi s0,sp,128 + 8310: 0300 addi s0,sp,384 + 8312: f704 fsw fs1,40(a4) + 8314: 0304 addi s1,sp,384 + 8316: 0900 addi s0,sp,144 + 8318: 0004 0x4 + 831a: 0001 nop + 831c: 04f70403 lb s0,79(a4) + 8320: 00090003 lb zero,0(s2) + 8324: 0100 addi s0,sp,128 + 8326: 0300 addi s0,sp,384 + 8328: ff04 fsw fs1,56(a4) + 832a: 0304 addi s1,sp,384 + 832c: 0900 addi s0,sp,144 + 832e: 0008 0x8 + 8330: 0001 nop + 8332: 04ff0403 lb s0,79(t5) + 8336: 00090003 lb zero,0(s2) + 833a: 0100 addi s0,sp,128 + 833c: 0300 addi s0,sp,384 + 833e: ff04 fsw fs1,56(a4) + 8340: 0304 addi s1,sp,384 + 8342: 0900 addi s0,sp,144 + 8344: 0000 unimp + 8346: 0001 nop + 8348: 04ff0403 lb s0,79(t5) + 834c: 00090003 lb zero,0(s2) + 8350: 0100 addi s0,sp,128 + 8352: 0300 addi s0,sp,384 + 8354: ff04 fsw fs1,56(a4) + 8356: 0304 addi s1,sp,384 + 8358: 0900 addi s0,sp,144 + 835a: 0008 0x8 + 835c: 0001 nop + 835e: 04ff0403 lb s0,79(t5) + 8362: 00090003 lb zero,0(s2) + 8366: 0100 addi s0,sp,128 + 8368: 0306 slli t1,t1,0x1 836a: 0900 addi s0,sp,144 - 836c: 0004 0x4 + 836c: 0014 0x14 836e: 0001 nop - 8370: 04f70403 lb s0,79(a4) - 8374: 00090003 lb zero,0(s2) - 8378: 0100 addi s0,sp,128 - 837a: 0300 addi s0,sp,384 - 837c: ff04 fsw fs1,56(a4) - 837e: 0304 addi s1,sp,384 - 8380: 0900 addi s0,sp,144 - 8382: 0008 0x8 - 8384: 0001 nop - 8386: 04ff0403 lb s0,79(t5) - 838a: 00090003 lb zero,0(s2) - 838e: 0100 addi s0,sp,128 - 8390: 0300 addi s0,sp,384 - 8392: ff04 fsw fs1,56(a4) - 8394: 0304 addi s1,sp,384 - 8396: 0900 addi s0,sp,144 - 8398: 0000 unimp - 839a: 0001 nop - 839c: 04ff0403 lb s0,79(t5) - 83a0: 00090003 lb zero,0(s2) - 83a4: 0100 addi s0,sp,128 - 83a6: 0300 addi s0,sp,384 - 83a8: ff04 fsw fs1,56(a4) - 83aa: 0304 addi s1,sp,384 - 83ac: 0900 addi s0,sp,144 - 83ae: 0008 0x8 - 83b0: 0001 nop - 83b2: 04ff0403 lb s0,79(t5) - 83b6: 00090003 lb zero,0(s2) - 83ba: 0100 addi s0,sp,128 - 83bc: 0306 slli t1,t1,0x1 - 83be: 0900 addi s0,sp,144 - 83c0: 0014 0x14 - 83c2: 0001 nop - 83c4: 058b0403 lb s0,88(s6) - 83c8: 0306 slli t1,t1,0x1 - 83ca: 0900 addi s0,sp,144 - 83cc: 0004 0x4 - 83ce: 0001 nop - 83d0: 058b0403 lb s0,88(s6) - 83d4: 14090003 lb zero,320(s2) - 83d8: 0100 addi s0,sp,128 - 83da: 0300 addi s0,sp,384 - 83dc: 8b04 0x8b04 - 83de: 0305 addi t1,t1,1 - 83e0: 0900 addi s0,sp,144 - 83e2: 0000 unimp - 83e4: 0001 nop - 83e6: 058e0403 lb s0,88(t3) - 83ea: 0c090003 lb zero,192(s2) - 83ee: 0100 addi s0,sp,128 - 83f0: 0300 addi s0,sp,384 - 83f2: 8e04 0x8e04 - 83f4: 0305 addi t1,t1,1 - 83f6: 0900 addi s0,sp,144 - 83f8: 001c 0x1c - 83fa: 0001 nop - 83fc: 05920403 lb s0,89(tp) # 59 <_start-0x7fffffa7> - 8400: 08090003 lb zero,128(s2) - 8404: 0100 addi s0,sp,128 - 8406: 0300 addi s0,sp,384 - 8408: 9204 0x9204 - 840a: 0305 addi t1,t1,1 - 840c: 0900 addi s0,sp,144 - 840e: 0010 0x10 - 8410: 0001 nop - 8412: 05910403 lb s0,89(sp) - 8416: 04090003 lb zero,64(s2) - 841a: 0100 addi s0,sp,128 - 841c: 0300 addi s0,sp,384 - 841e: 9304 0x9304 - 8420: 0305 addi t1,t1,1 - 8422: 0900 addi s0,sp,144 - 8424: 0004 0x4 - 8426: 0001 nop - 8428: 05930403 lb s0,89(t1) - 842c: 00090003 lb zero,0(s2) - 8430: 0100 addi s0,sp,128 - 8432: 0300 addi s0,sp,384 - 8434: 9404 0x9404 - 8436: 0305 addi t1,t1,1 - 8438: 0900 addi s0,sp,144 - 843a: 0004 0x4 - 843c: 0001 nop - 843e: 05940403 lb s0,89(s0) - 8442: 08090003 lb zero,128(s2) - 8446: 0100 addi s0,sp,128 - 8448: 0300 addi s0,sp,384 - 844a: 9404 0x9404 - 844c: 0305 addi t1,t1,1 - 844e: 0900 addi s0,sp,144 - 8450: 0000 unimp - 8452: 0001 nop - 8454: 05940403 lb s0,89(s0) - 8458: 00090003 lb zero,0(s2) - 845c: 0100 addi s0,sp,128 - 845e: 0300 addi s0,sp,384 - 8460: 9404 0x9404 - 8462: 0305 addi t1,t1,1 - 8464: 0900 addi s0,sp,144 - 8466: 0000 unimp - 8468: 0001 nop - 846a: 05940403 lb s0,89(s0) - 846e: 00090003 lb zero,0(s2) + 8370: 058b0403 lb s0,88(s6) + 8374: 0306 slli t1,t1,0x1 + 8376: 0900 addi s0,sp,144 + 8378: 0004 0x4 + 837a: 0001 nop + 837c: 058b0403 lb s0,88(s6) + 8380: 14090003 lb zero,320(s2) + 8384: 0100 addi s0,sp,128 + 8386: 0300 addi s0,sp,384 + 8388: 8b04 0x8b04 + 838a: 0305 addi t1,t1,1 + 838c: 0900 addi s0,sp,144 + 838e: 0000 unimp + 8390: 0001 nop + 8392: 058e0403 lb s0,88(t3) + 8396: 0c090003 lb zero,192(s2) + 839a: 0100 addi s0,sp,128 + 839c: 0300 addi s0,sp,384 + 839e: 8e04 0x8e04 + 83a0: 0305 addi t1,t1,1 + 83a2: 0900 addi s0,sp,144 + 83a4: 001c 0x1c + 83a6: 0001 nop + 83a8: 05920403 lb s0,89(tp) # 59 <_start-0x7fffffa7> + 83ac: 08090003 lb zero,128(s2) + 83b0: 0100 addi s0,sp,128 + 83b2: 0300 addi s0,sp,384 + 83b4: 9204 0x9204 + 83b6: 0305 addi t1,t1,1 + 83b8: 0900 addi s0,sp,144 + 83ba: 0010 0x10 + 83bc: 0001 nop + 83be: 05910403 lb s0,89(sp) + 83c2: 04090003 lb zero,64(s2) + 83c6: 0100 addi s0,sp,128 + 83c8: 0300 addi s0,sp,384 + 83ca: 9304 0x9304 + 83cc: 0305 addi t1,t1,1 + 83ce: 0900 addi s0,sp,144 + 83d0: 0004 0x4 + 83d2: 0001 nop + 83d4: 05930403 lb s0,89(t1) + 83d8: 00090003 lb zero,0(s2) + 83dc: 0100 addi s0,sp,128 + 83de: 0300 addi s0,sp,384 + 83e0: 9404 0x9404 + 83e2: 0305 addi t1,t1,1 + 83e4: 0900 addi s0,sp,144 + 83e6: 0004 0x4 + 83e8: 0001 nop + 83ea: 05940403 lb s0,89(s0) + 83ee: 08090003 lb zero,128(s2) + 83f2: 0100 addi s0,sp,128 + 83f4: 0300 addi s0,sp,384 + 83f6: 9404 0x9404 + 83f8: 0305 addi t1,t1,1 + 83fa: 0900 addi s0,sp,144 + 83fc: 0000 unimp + 83fe: 0001 nop + 8400: 05940403 lb s0,89(s0) + 8404: 00090003 lb zero,0(s2) + 8408: 0100 addi s0,sp,128 + 840a: 0300 addi s0,sp,384 + 840c: 9404 0x9404 + 840e: 0305 addi t1,t1,1 + 8410: 0900 addi s0,sp,144 + 8412: 0000 unimp + 8414: 0001 nop + 8416: 05940403 lb s0,89(s0) + 841a: 00090003 lb zero,0(s2) + 841e: 0100 addi s0,sp,128 + 8420: 0300 addi s0,sp,384 + 8422: 9404 0x9404 + 8424: 0305 addi t1,t1,1 + 8426: 0900 addi s0,sp,144 + 8428: 0000 unimp + 842a: 0001 nop + 842c: 05940403 lb s0,89(s0) + 8430: 00090003 lb zero,0(s2) + 8434: 0100 addi s0,sp,128 + 8436: 0300 addi s0,sp,384 + 8438: 9404 0x9404 + 843a: 0305 addi t1,t1,1 + 843c: 0900 addi s0,sp,144 + 843e: 0008 0x8 + 8440: 0001 nop + 8442: 05940403 lb s0,89(s0) + 8446: 00090003 lb zero,0(s2) + 844a: 0100 addi s0,sp,128 + 844c: 0300 addi s0,sp,384 + 844e: 9404 0x9404 + 8450: 0305 addi t1,t1,1 + 8452: 0900 addi s0,sp,144 + 8454: 0000 unimp + 8456: 0001 nop + 8458: 05960403 lb s0,89(a2) + 845c: 08090003 lb zero,128(s2) + 8460: 0100 addi s0,sp,128 + 8462: 0300 addi s0,sp,384 + 8464: 9904 0x9904 + 8466: 0305 addi t1,t1,1 + 8468: 0900 addi s0,sp,144 + 846a: 0010 0x10 + 846c: 0601 addi a2,a2,0 + 846e: 0c090003 lb zero,192(s2) 8472: 0100 addi s0,sp,128 8474: 0300 addi s0,sp,384 - 8476: 9404 0x9404 - 8478: 0305 addi t1,t1,1 - 847a: 0900 addi s0,sp,144 - 847c: 0000 unimp - 847e: 0001 nop - 8480: 05940403 lb s0,89(s0) - 8484: 00090003 lb zero,0(s2) - 8488: 0100 addi s0,sp,128 - 848a: 0300 addi s0,sp,384 - 848c: 9404 0x9404 - 848e: 0305 addi t1,t1,1 - 8490: 0900 addi s0,sp,144 - 8492: 0008 0x8 - 8494: 0001 nop - 8496: 05940403 lb s0,89(s0) - 849a: 00090003 lb zero,0(s2) - 849e: 0100 addi s0,sp,128 - 84a0: 0300 addi s0,sp,384 - 84a2: 9404 0x9404 - 84a4: 0305 addi t1,t1,1 - 84a6: 0900 addi s0,sp,144 - 84a8: 0000 unimp - 84aa: 0001 nop - 84ac: 05960403 lb s0,89(a2) - 84b0: 08090003 lb zero,128(s2) - 84b4: 0100 addi s0,sp,128 - 84b6: 0300 addi s0,sp,384 - 84b8: 9904 0x9904 - 84ba: 0305 addi t1,t1,1 - 84bc: 0900 addi s0,sp,144 - 84be: 0010 0x10 - 84c0: 0601 addi a2,a2,0 - 84c2: 0c090003 lb zero,192(s2) - 84c6: 0100 addi s0,sp,128 - 84c8: 0300 addi s0,sp,384 - 84ca: 9e04 0x9e04 - 84cc: 0605 addi a2,a2,1 - 84ce: 10090003 lb zero,256(s2) - 84d2: 0100 addi s0,sp,128 - 84d4: 0300 addi s0,sp,384 - 84d6: 9e04 0x9e04 - 84d8: 0305 addi t1,t1,1 - 84da: 0900 addi s0,sp,144 - 84dc: 0014 0x14 - 84de: 0001 nop - 84e0: 059e0403 lb s0,89(t3) - 84e4: 00090003 lb zero,0(s2) - 84e8: 0100 addi s0,sp,128 - 84ea: 0300 addi s0,sp,384 - 84ec: 9804 0x9804 - 84ee: 0305 addi t1,t1,1 - 84f0: 0900 addi s0,sp,144 - 84f2: 001c 0x1c - 84f4: 0001 nop - 84f6: 05980403 lb s0,89(a6) - 84fa: 18090003 lb zero,384(s2) - 84fe: 0100 addi s0,sp,128 - 8500: 0300 addi s0,sp,384 - 8502: 9b04 0x9b04 - 8504: 0605 addi a2,a2,1 - 8506: 04090003 lb zero,64(s2) - 850a: 0100 addi s0,sp,128 - 850c: 0300 addi s0,sp,384 - 850e: 9b04 0x9b04 - 8510: 0605 addi a2,a2,1 - 8512: 20090003 lb zero,512(s2) - 8516: 0100 addi s0,sp,128 - 8518: 0300 addi s0,sp,384 - 851a: 9b04 0x9b04 - 851c: 0305 addi t1,t1,1 - 851e: 0900 addi s0,sp,144 - 8520: 0008 0x8 - 8522: 0001 nop - 8524: 059f0403 lb s0,89(t5) - 8528: 10090003 lb zero,256(s2) - 852c: 0100 addi s0,sp,128 - 852e: 0300 addi s0,sp,384 - 8530: a204 fsd fs1,0(a2) - 8532: 0605 addi a2,a2,1 - 8534: 08090003 lb zero,128(s2) - 8538: 0100 addi s0,sp,128 - 853a: 0300 addi s0,sp,384 - 853c: a204 fsd fs1,0(a2) - 853e: 0605 addi a2,a2,1 - 8540: 18090003 lb zero,384(s2) - 8544: 0100 addi s0,sp,128 - 8546: 0300 addi s0,sp,384 - 8548: a404 fsd fs1,8(s0) - 854a: 0605 addi a2,a2,1 - 854c: 08090003 lb zero,128(s2) - 8550: 0100 addi s0,sp,128 - 8552: 0300 addi s0,sp,384 - 8554: a104 fsd fs1,0(a0) - 8556: 0605 addi a2,a2,1 - 8558: 08090003 lb zero,128(s2) - 855c: 0100 addi s0,sp,128 - 855e: 0300 addi s0,sp,384 - 8560: a104 fsd fs1,0(a0) - 8562: 0305 addi t1,t1,1 - 8564: 0900 addi s0,sp,144 - 8566: 0028 addi a0,sp,8 - 8568: 0001 nop - 856a: 05a50403 lb s0,90(a0) - 856e: 04090003 lb zero,64(s2) - 8572: 0100 addi s0,sp,128 - 8574: 0300 addi s0,sp,384 - 8576: a504 fsd fs1,8(a0) - 8578: 0305 addi t1,t1,1 - 857a: 0900 addi s0,sp,144 - 857c: 0010 0x10 - 857e: 0001 nop - 8580: 05a40403 lb s0,90(s0) - 8584: 04090003 lb zero,64(s2) - 8588: 0100 addi s0,sp,128 - 858a: 0300 addi s0,sp,384 - 858c: a604 fsd fs1,8(a2) - 858e: 0305 addi t1,t1,1 - 8590: 0900 addi s0,sp,144 - 8592: 0004 0x4 - 8594: 0001 nop - 8596: 05a60403 lb s0,90(a2) - 859a: 00090003 lb zero,0(s2) - 859e: 0100 addi s0,sp,128 - 85a0: 0300 addi s0,sp,384 - 85a2: a604 fsd fs1,8(a2) - 85a4: 0305 addi t1,t1,1 + 8476: 9e04 0x9e04 + 8478: 0605 addi a2,a2,1 + 847a: 10090003 lb zero,256(s2) + 847e: 0100 addi s0,sp,128 + 8480: 0300 addi s0,sp,384 + 8482: 9e04 0x9e04 + 8484: 0305 addi t1,t1,1 + 8486: 0900 addi s0,sp,144 + 8488: 0014 0x14 + 848a: 0001 nop + 848c: 059e0403 lb s0,89(t3) + 8490: 00090003 lb zero,0(s2) + 8494: 0100 addi s0,sp,128 + 8496: 0300 addi s0,sp,384 + 8498: 9804 0x9804 + 849a: 0305 addi t1,t1,1 + 849c: 0900 addi s0,sp,144 + 849e: 001c 0x1c + 84a0: 0001 nop + 84a2: 05980403 lb s0,89(a6) + 84a6: 18090003 lb zero,384(s2) + 84aa: 0100 addi s0,sp,128 + 84ac: 0300 addi s0,sp,384 + 84ae: 9b04 0x9b04 + 84b0: 0605 addi a2,a2,1 + 84b2: 04090003 lb zero,64(s2) + 84b6: 0100 addi s0,sp,128 + 84b8: 0300 addi s0,sp,384 + 84ba: 9b04 0x9b04 + 84bc: 0605 addi a2,a2,1 + 84be: 20090003 lb zero,512(s2) + 84c2: 0100 addi s0,sp,128 + 84c4: 0300 addi s0,sp,384 + 84c6: 9b04 0x9b04 + 84c8: 0305 addi t1,t1,1 + 84ca: 0900 addi s0,sp,144 + 84cc: 0008 0x8 + 84ce: 0001 nop + 84d0: 059f0403 lb s0,89(t5) + 84d4: 10090003 lb zero,256(s2) + 84d8: 0100 addi s0,sp,128 + 84da: 0300 addi s0,sp,384 + 84dc: a204 fsd fs1,0(a2) + 84de: 0605 addi a2,a2,1 + 84e0: 08090003 lb zero,128(s2) + 84e4: 0100 addi s0,sp,128 + 84e6: 0300 addi s0,sp,384 + 84e8: a204 fsd fs1,0(a2) + 84ea: 0605 addi a2,a2,1 + 84ec: 18090003 lb zero,384(s2) + 84f0: 0100 addi s0,sp,128 + 84f2: 0300 addi s0,sp,384 + 84f4: a404 fsd fs1,8(s0) + 84f6: 0605 addi a2,a2,1 + 84f8: 08090003 lb zero,128(s2) + 84fc: 0100 addi s0,sp,128 + 84fe: 0300 addi s0,sp,384 + 8500: a104 fsd fs1,0(a0) + 8502: 0605 addi a2,a2,1 + 8504: 08090003 lb zero,128(s2) + 8508: 0100 addi s0,sp,128 + 850a: 0300 addi s0,sp,384 + 850c: a104 fsd fs1,0(a0) + 850e: 0305 addi t1,t1,1 + 8510: 0900 addi s0,sp,144 + 8512: 0028 addi a0,sp,8 + 8514: 0001 nop + 8516: 05a50403 lb s0,90(a0) + 851a: 04090003 lb zero,64(s2) + 851e: 0100 addi s0,sp,128 + 8520: 0300 addi s0,sp,384 + 8522: a504 fsd fs1,8(a0) + 8524: 0305 addi t1,t1,1 + 8526: 0900 addi s0,sp,144 + 8528: 0010 0x10 + 852a: 0001 nop + 852c: 05a40403 lb s0,90(s0) + 8530: 04090003 lb zero,64(s2) + 8534: 0100 addi s0,sp,128 + 8536: 0300 addi s0,sp,384 + 8538: a604 fsd fs1,8(a2) + 853a: 0305 addi t1,t1,1 + 853c: 0900 addi s0,sp,144 + 853e: 0004 0x4 + 8540: 0001 nop + 8542: 05a60403 lb s0,90(a2) + 8546: 00090003 lb zero,0(s2) + 854a: 0100 addi s0,sp,128 + 854c: 0300 addi s0,sp,384 + 854e: a604 fsd fs1,8(a2) + 8550: 0305 addi t1,t1,1 + 8552: 0900 addi s0,sp,144 + 8554: 0000 unimp + 8556: 0001 nop + 8558: 05a60403 lb s0,90(a2) + 855c: 14090003 lb zero,320(s2) + 8560: 0100 addi s0,sp,128 + 8562: 0300 addi s0,sp,384 + 8564: a604 fsd fs1,8(a2) + 8566: 0305 addi t1,t1,1 + 8568: 0900 addi s0,sp,144 + 856a: 0000 unimp + 856c: 0001 nop + 856e: 05950403 lb s0,89(a0) + 8572: 04090003 lb zero,64(s2) + 8576: 0100 addi s0,sp,128 + 8578: 0300 addi s0,sp,384 + 857a: 9504 0x9504 + 857c: 0305 addi t1,t1,1 + 857e: 0900 addi s0,sp,144 + 8580: 0004 0x4 + 8582: 0001 nop + 8584: 0402 c.slli64 s0 + 8586: 0352 slli t1,t1,0x14 + 8588: 0901 addi s2,s2,0 + 858a: 0018 0x18 + 858c: 0001 nop + 858e: 0402 c.slli64 s0 + 8590: 0352 slli t1,t1,0x14 + 8592: 0900 addi s0,sp,144 + 8594: 0000 unimp + 8596: 0001 nop + 8598: 0402 c.slli64 s0 + 859a: 0352 slli t1,t1,0x14 + 859c: 0900 addi s0,sp,144 + 859e: 0000 unimp + 85a0: 0001 nop + 85a2: 0402 c.slli64 s0 + 85a4: 0352 slli t1,t1,0x14 85a6: 0900 addi s0,sp,144 85a8: 0000 unimp 85aa: 0001 nop - 85ac: 05a60403 lb s0,90(a2) - 85b0: 14090003 lb zero,320(s2) - 85b4: 0100 addi s0,sp,128 - 85b6: 0300 addi s0,sp,384 - 85b8: a604 fsd fs1,8(a2) - 85ba: 0305 addi t1,t1,1 - 85bc: 0900 addi s0,sp,144 - 85be: 0000 unimp - 85c0: 0001 nop - 85c2: 05950403 lb s0,89(a0) - 85c6: 04090003 lb zero,64(s2) - 85ca: 0100 addi s0,sp,128 - 85cc: 0300 addi s0,sp,384 - 85ce: 9504 0x9504 - 85d0: 0305 addi t1,t1,1 - 85d2: 0900 addi s0,sp,144 - 85d4: 0004 0x4 - 85d6: 0001 nop - 85d8: 0402 c.slli64 s0 - 85da: 0352 slli t1,t1,0x14 - 85dc: 0901 addi s2,s2,0 - 85de: 0018 0x18 - 85e0: 0001 nop - 85e2: 0402 c.slli64 s0 - 85e4: 0352 slli t1,t1,0x14 - 85e6: 0900 addi s0,sp,144 - 85e8: 0000 unimp - 85ea: 0001 nop - 85ec: 0402 c.slli64 s0 - 85ee: 0352 slli t1,t1,0x14 - 85f0: 0900 addi s0,sp,144 - 85f2: 0000 unimp - 85f4: 0001 nop - 85f6: 0402 c.slli64 s0 - 85f8: 0352 slli t1,t1,0x14 - 85fa: 0900 addi s0,sp,144 - 85fc: 0000 unimp - 85fe: 0001 nop - 8600: 0402 c.slli64 s0 - 8602: 0352 slli t1,t1,0x14 - 8604: 0900 addi s0,sp,144 - 8606: 0010 0x10 - 8608: 0001 nop - 860a: 0402 c.slli64 s0 - 860c: 0352 slli t1,t1,0x14 - 860e: 0900 addi s0,sp,144 - 8610: 0000 unimp - 8612: 0901 addi s2,s2,0 - 8614: 0004 0x4 - 8616: 0100 addi s0,sp,128 - 8618: 3c01 jal 8028 <_start-0x7fff7fd8> - 861a: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 861e: 9200 0x9200 - 8620: 0000 unimp - 8622: 0100 addi s0,sp,128 - 8624: fb01 bnez a4,8534 <_start-0x7fff7acc> - 8626: 0d0e slli s10,s10,0x3 - 8628: 0100 addi s0,sp,128 - 862a: 0101 addi sp,sp,0 - 862c: 0001 nop - 862e: 0000 unimp - 8630: 0001 nop - 8632: 0100 addi s0,sp,128 - 8634: 2e2e fld ft8,200(sp) - 8636: 2f2e2e2f 0x2f2e2e2f - 863a: 2e2e fld ft8,200(sp) - 863c: 2f2e2e2f 0x2f2e2e2f - 8640: 6972 flw fs2,28(sp) - 8642: 2d766373 csrrsi t1,0x2d7,12 - 8646: 2f636367 0x2f636367 - 864a: 696c flw fa1,84(a0) - 864c: 6762 flw fa4,24(sp) - 864e: 732f6363 bltu t5,s2,8d74 <_start-0x7fff728c> - 8652: 2d74666f jal a2,4f128 <_start-0x7ffb0ed8> - 8656: 7066 flw ft0,120(sp) - 8658: 2e00 fld fs0,24(a2) - 865a: 2f2e fld ft10,200(sp) - 865c: 2e2e fld ft8,200(sp) - 865e: 2f2e2e2f 0x2f2e2e2f - 8662: 2e2e fld ft8,200(sp) - 8664: 7369722f 0x7369722f - 8668: 672d7663 bgeu s10,s2,8cd4 <_start-0x7fff732c> - 866c: 6c2f6363 bltu t5,sp,8d32 <_start-0x7fff72ce> - 8670: 6269 lui tp,0x1a - 8672: 2f636367 0x2f636367 - 8676: 2e2e fld ft8,200(sp) - 8678: 636e692f 0x636e692f - 867c: 756c flw fa1,108(a0) - 867e: 6564 flw fs1,76(a0) + 85ac: 0402 c.slli64 s0 + 85ae: 0352 slli t1,t1,0x14 + 85b0: 0900 addi s0,sp,144 + 85b2: 0010 0x10 + 85b4: 0001 nop + 85b6: 0402 c.slli64 s0 + 85b8: 0352 slli t1,t1,0x14 + 85ba: 0900 addi s0,sp,144 + 85bc: 0000 unimp + 85be: 0901 addi s2,s2,0 + 85c0: 0004 0x4 + 85c2: 0100 addi s0,sp,128 + 85c4: 3c01 jal 7fd4 <_start-0x7fff802c> + 85c6: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> + 85ca: 9200 0x9200 + 85cc: 0000 unimp + 85ce: 0100 addi s0,sp,128 + 85d0: fb01 bnez a4,84e0 <_start-0x7fff7b20> + 85d2: 0d0e slli s10,s10,0x3 + 85d4: 0100 addi s0,sp,128 + 85d6: 0101 addi sp,sp,0 + 85d8: 0001 nop + 85da: 0000 unimp + 85dc: 0001 nop + 85de: 0100 addi s0,sp,128 + 85e0: 2e2e fld ft8,200(sp) + 85e2: 2f2e2e2f 0x2f2e2e2f + 85e6: 2e2e fld ft8,200(sp) + 85e8: 2f2e2e2f 0x2f2e2e2f + 85ec: 6972 flw fs2,28(sp) + 85ee: 2d766373 csrrsi t1,0x2d7,12 + 85f2: 2f636367 0x2f636367 + 85f6: 696c flw fa1,84(a0) + 85f8: 6762 flw fa4,24(sp) + 85fa: 732f6363 bltu t5,s2,8d20 <_start-0x7fff72e0> + 85fe: 2d74666f jal a2,4f0d4 <_start-0x7ffb0f2c> + 8602: 7066 flw ft0,120(sp) + 8604: 2e00 fld fs0,24(a2) + 8606: 2f2e fld ft10,200(sp) + 8608: 2e2e fld ft8,200(sp) + 860a: 2f2e2e2f 0x2f2e2e2f + 860e: 2e2e fld ft8,200(sp) + 8610: 7369722f 0x7369722f + 8614: 672d7663 bgeu s10,s2,8c80 <_start-0x7fff7380> + 8618: 6c2f6363 bltu t5,sp,8cde <_start-0x7fff7322> + 861c: 6269 lui tp,0x1a + 861e: 2f636367 0x2f636367 + 8622: 2e2e fld ft8,200(sp) + 8624: 636e692f 0x636e692f + 8628: 756c flw fa1,108(a0) + 862a: 6564 flw fs1,76(a0) + 862c: 0000 unimp + 862e: 6966 flw fs2,88(sp) + 8630: 7478 flw fa4,108(s0) + 8632: 7366 flw ft6,120(sp) + 8634: 2e69 jal 89ce <_start-0x7fff7632> + 8636: 00010063 beqz sp,8636 <_start-0x7fff79ca> + 863a: 7300 flw fs0,32(a4) + 863c: 2d74666f jal a2,4f112 <_start-0x7ffb0eee> + 8640: 7066 flw ft0,120(sp) + 8642: 682e flw fa6,200(sp) + 8644: 0100 addi s0,sp,128 + 8646: 0000 unimp + 8648: 7571 lui a0,0xffffc + 864a: 6461 lui s0,0x18 + 864c: 682e flw fa6,200(sp) + 864e: 0100 addi s0,sp,128 + 8650: 0000 unimp + 8652: 6f6c flw fa1,92(a4) + 8654: 676e flw fa4,216(sp) + 8656: 6f6c flw fa1,92(a4) + 8658: 676e flw fa4,216(sp) + 865a: 682e flw fa6,200(sp) + 865c: 0200 addi s0,sp,256 + 865e: 0000 unimp + 8660: 0500 addi s0,sp,640 + 8662: 0001 nop + 8664: 0205 addi tp,tp,1 + 8666: 4224 lw s1,64(a2) + 8668: 8001 c.srli64 s0 + 866a: 05012303 lw t1,80(sp) + 866e: 09010303 lb t1,144(sp) + 8672: 0000 unimp + 8674: 0301 addi t1,t1,0 + 8676: 0900 addi s0,sp,144 + 8678: 0000 unimp + 867a: 0501 addi a0,a0,0 + 867c: 030d addi t1,t1,3 + 867e: 0900 addi s0,sp,144 8680: 0000 unimp - 8682: 6966 flw fs2,88(sp) - 8684: 7478 flw fa4,108(s0) - 8686: 7366 flw ft6,120(sp) - 8688: 2e69 jal 8a22 <_start-0x7fff75de> - 868a: 00010063 beqz sp,868a <_start-0x7fff7976> - 868e: 7300 flw fs0,32(a4) - 8690: 2d74666f jal a2,4f166 <_start-0x7ffb0e9a> - 8694: 7066 flw ft0,120(sp) - 8696: 682e flw fa6,200(sp) - 8698: 0100 addi s0,sp,128 + 8682: 0501 addi a0,a0,0 + 8684: 09010303 lb t1,144(sp) + 8688: 0000 unimp + 868a: 0301 addi t1,t1,0 + 868c: 0900 addi s0,sp,144 + 868e: 0000 unimp + 8690: 0301 addi t1,t1,0 + 8692: 0900 addi s0,sp,144 + 8694: 0000 unimp + 8696: 0301 addi t1,t1,0 + 8698: 0900 addi s0,sp,144 869a: 0000 unimp - 869c: 7571 lui a0,0xffffc - 869e: 6461 lui s0,0x18 - 86a0: 682e flw fa6,200(sp) - 86a2: 0100 addi s0,sp,128 - 86a4: 0000 unimp - 86a6: 6f6c flw fa1,92(a4) - 86a8: 676e flw fa4,216(sp) - 86aa: 6f6c flw fa1,92(a4) - 86ac: 676e flw fa4,216(sp) - 86ae: 682e flw fa6,200(sp) - 86b0: 0200 addi s0,sp,256 + 869c: 0301 addi t1,t1,0 + 869e: 0901 addi s2,s2,0 + 86a0: 0000 unimp + 86a2: 0301 addi t1,t1,0 + 86a4: 0902 c.slli64 s2 + 86a6: 0000 unimp + 86a8: 0301 addi t1,t1,0 + 86aa: 0901 addi s2,s2,0 + 86ac: 0000 unimp + 86ae: 0301 addi t1,t1,0 + 86b0: 0900 addi s0,sp,144 86b2: 0000 unimp - 86b4: 0500 addi s0,sp,640 - 86b6: 0001 nop - 86b8: 0205 addi tp,tp,1 - 86ba: 4160 lw s0,68(a0) - 86bc: 8001 c.srli64 s0 - 86be: 05012303 lw t1,80(sp) - 86c2: 09010303 lb t1,144(sp) - 86c6: 0000 unimp - 86c8: 0301 addi t1,t1,0 - 86ca: 0900 addi s0,sp,144 - 86cc: 0000 unimp - 86ce: 0501 addi a0,a0,0 - 86d0: 030d addi t1,t1,3 - 86d2: 0900 addi s0,sp,144 - 86d4: 0000 unimp - 86d6: 0501 addi a0,a0,0 - 86d8: 09010303 lb t1,144(sp) - 86dc: 0000 unimp + 86b4: 0301 addi t1,t1,0 + 86b6: 0900 addi s0,sp,144 + 86b8: 0000 unimp + 86ba: 0501 addi a0,a0,0 + 86bc: 0601 addi a2,a2,0 + 86be: 00097a03 0x97a03 + 86c2: 0100 addi s0,sp,128 + 86c4: 0305 addi t1,t1,1 + 86c6: 14090603 lb a2,320(s2) + 86ca: 0100 addi s0,sp,128 + 86cc: 0c090103 lb sp,192(s2) + 86d0: 0100 addi s0,sp,128 + 86d2: 04097f03 0x4097f03 + 86d6: 0100 addi s0,sp,128 + 86d8: 0306 slli t1,t1,0x1 + 86da: 0900 addi s0,sp,144 + 86dc: 0010 0x10 86de: 0301 addi t1,t1,0 86e0: 0900 addi s0,sp,144 - 86e2: 0000 unimp + 86e2: 0004 0x4 86e4: 0301 addi t1,t1,0 86e6: 0900 addi s0,sp,144 86e8: 0000 unimp @@ -55494,1418 +55540,1420 @@ Disassembly of section .debug_line: 86ec: 0900 addi s0,sp,144 86ee: 0000 unimp 86f0: 0301 addi t1,t1,0 - 86f2: 0901 addi s2,s2,0 + 86f2: 0900 addi s0,sp,144 86f4: 0000 unimp 86f6: 0301 addi t1,t1,0 - 86f8: 0902 c.slli64 s2 + 86f8: 0900 addi s0,sp,144 86fa: 0000 unimp 86fc: 0301 addi t1,t1,0 - 86fe: 0901 addi s2,s2,0 + 86fe: 0900 addi s0,sp,144 8700: 0000 unimp 8702: 0301 addi t1,t1,0 - 8704: 0900 addi s0,sp,144 + 8704: 0901 addi s2,s2,0 8706: 0000 unimp 8708: 0301 addi t1,t1,0 870a: 0900 addi s0,sp,144 870c: 0000 unimp - 870e: 0501 addi a0,a0,0 - 8710: 0601 addi a2,a2,0 - 8712: 00097a03 0x97a03 - 8716: 0100 addi s0,sp,128 - 8718: 0305 addi t1,t1,1 - 871a: 14090603 lb a2,320(s2) - 871e: 0100 addi s0,sp,128 - 8720: 0c090103 lb sp,192(s2) - 8724: 0100 addi s0,sp,128 - 8726: 04097f03 0x4097f03 - 872a: 0100 addi s0,sp,128 - 872c: 0306 slli t1,t1,0x1 - 872e: 0900 addi s0,sp,144 - 8730: 0010 0x10 - 8732: 0301 addi t1,t1,0 + 870e: 0001 nop + 8710: 0402 c.slli64 s0 + 8712: 060a slli a2,a2,0x2 + 8714: 0c090003 lb zero,192(s2) + 8718: 0100 addi s0,sp,128 + 871a: 0200 addi s0,sp,256 + 871c: 0a04 addi s1,sp,272 + 871e: 0306 slli t1,t1,0x1 + 8720: 0900 addi s0,sp,144 + 8722: 0008 0x8 + 8724: 0001 nop + 8726: 0402 c.slli64 s0 + 8728: 030a slli t1,t1,0x2 + 872a: 0900 addi s0,sp,144 + 872c: 0000 unimp + 872e: 0001 nop + 8730: 0402 c.slli64 s0 + 8732: 030e slli t1,t1,0x3 8734: 0900 addi s0,sp,144 8736: 0004 0x4 - 8738: 0301 addi t1,t1,0 - 873a: 0900 addi s0,sp,144 - 873c: 0000 unimp - 873e: 0301 addi t1,t1,0 - 8740: 0900 addi s0,sp,144 - 8742: 0000 unimp - 8744: 0301 addi t1,t1,0 - 8746: 0900 addi s0,sp,144 - 8748: 0000 unimp - 874a: 0301 addi t1,t1,0 - 874c: 0900 addi s0,sp,144 - 874e: 0000 unimp - 8750: 0301 addi t1,t1,0 + 8738: 0001 nop + 873a: 0402 c.slli64 s0 + 873c: 030e slli t1,t1,0x3 + 873e: 0900 addi s0,sp,144 + 8740: 0000 unimp + 8742: 0001 nop + 8744: 0402 c.slli64 s0 + 8746: 030e slli t1,t1,0x3 + 8748: 0900 addi s0,sp,144 + 874a: 0000 unimp + 874c: 0001 nop + 874e: 0402 c.slli64 s0 + 8750: 030e slli t1,t1,0x3 8752: 0900 addi s0,sp,144 8754: 0000 unimp - 8756: 0301 addi t1,t1,0 - 8758: 0901 addi s2,s2,0 - 875a: 0000 unimp - 875c: 0301 addi t1,t1,0 - 875e: 0900 addi s0,sp,144 - 8760: 0000 unimp - 8762: 0001 nop - 8764: 0402 c.slli64 s0 - 8766: 060a slli a2,a2,0x2 - 8768: 0c090003 lb zero,192(s2) - 876c: 0100 addi s0,sp,128 - 876e: 0200 addi s0,sp,256 - 8770: 0a04 addi s1,sp,272 - 8772: 0306 slli t1,t1,0x1 - 8774: 0900 addi s0,sp,144 - 8776: 0008 0x8 - 8778: 0001 nop - 877a: 0402 c.slli64 s0 - 877c: 030a slli t1,t1,0x2 - 877e: 0900 addi s0,sp,144 - 8780: 0000 unimp - 8782: 0001 nop - 8784: 0402 c.slli64 s0 - 8786: 030e slli t1,t1,0x3 - 8788: 0900 addi s0,sp,144 - 878a: 0004 0x4 - 878c: 0001 nop - 878e: 0402 c.slli64 s0 - 8790: 030e slli t1,t1,0x3 - 8792: 0900 addi s0,sp,144 - 8794: 0000 unimp - 8796: 0001 nop - 8798: 0402 c.slli64 s0 - 879a: 030e slli t1,t1,0x3 - 879c: 0900 addi s0,sp,144 - 879e: 0000 unimp - 87a0: 0001 nop - 87a2: 0402 c.slli64 s0 - 87a4: 030e slli t1,t1,0x3 - 87a6: 0900 addi s0,sp,144 - 87a8: 0000 unimp - 87aa: 0001 nop - 87ac: 0402 c.slli64 s0 - 87ae: 030e slli t1,t1,0x3 - 87b0: 0900 addi s0,sp,144 - 87b2: 000c 0xc - 87b4: 0001 nop - 87b6: 0402 c.slli64 s0 - 87b8: 035c addi a5,sp,388 - 87ba: 0900 addi s0,sp,144 - 87bc: 0000 unimp - 87be: 0001 nop - 87c0: 0402 c.slli64 s0 - 87c2: 035c addi a5,sp,388 - 87c4: 0901 addi s2,s2,0 - 87c6: 0000 unimp - 87c8: 0001 nop - 87ca: 0402 c.slli64 s0 - 87cc: 035c addi a5,sp,388 - 87ce: 0900 addi s0,sp,144 - 87d0: 0000 unimp - 87d2: 0001 nop - 87d4: 0402 c.slli64 s0 - 87d6: 035c addi a5,sp,388 - 87d8: 0900 addi s0,sp,144 - 87da: 0000 unimp - 87dc: 0001 nop - 87de: 0402 c.slli64 s0 - 87e0: 035c addi a5,sp,388 - 87e2: 0902 c.slli64 s2 - 87e4: 0000 unimp - 87e6: 0501 addi a0,a0,0 - 87e8: 0001 nop - 87ea: 0402 c.slli64 s0 - 87ec: 065c addi a5,sp,772 - 87ee: 00090103 lb sp,0(s2) - 87f2: 0100 addi s0,sp,128 - 87f4: 0305 addi t1,t1,1 - 87f6: 0200 addi s0,sp,256 - 87f8: 0d04 addi s1,sp,656 - 87fa: 0306 slli t1,t1,0x1 - 87fc: 097c addi a5,sp,156 - 87fe: 0008 0x8 - 8800: 0001 nop - 8802: 0402 c.slli64 s0 - 8804: 030d addi t1,t1,3 - 8806: 0900 addi s0,sp,144 - 8808: 0000 unimp - 880a: 0001 nop - 880c: 0402 c.slli64 s0 - 880e: 060d addi a2,a2,3 - 8810: 00097f03 0x97f03 - 8814: 0100 addi s0,sp,128 - 8816: 0200 addi s0,sp,256 - 8818: 0d04 addi s1,sp,656 - 881a: 04090103 lb sp,64(s2) - 881e: 0100 addi s0,sp,128 - 8820: 0200 addi s0,sp,256 - 8822: 0d04 addi s1,sp,656 - 8824: 04097f03 0x4097f03 - 8828: 0100 addi s0,sp,128 - 882a: 0200 addi s0,sp,256 - 882c: 0d04 addi s1,sp,656 - 882e: 04090103 lb sp,64(s2) - 8832: 0100 addi s0,sp,128 - 8834: 0200 addi s0,sp,256 - 8836: 0d04 addi s1,sp,656 - 8838: 0306 slli t1,t1,0x1 - 883a: 0900 addi s0,sp,144 - 883c: 0014 0x14 - 883e: 0001 nop - 8840: 0402 c.slli64 s0 - 8842: 030d addi t1,t1,3 - 8844: 0900 addi s0,sp,144 - 8846: 0000 unimp - 8848: 0001 nop - 884a: 0402 c.slli64 s0 - 884c: 030d addi t1,t1,3 - 884e: 0900 addi s0,sp,144 - 8850: 0000 unimp - 8852: 0001 nop - 8854: 0402 c.slli64 s0 - 8856: 030d addi t1,t1,3 - 8858: 0900 addi s0,sp,144 - 885a: 0000 unimp - 885c: 0001 nop - 885e: 0402 c.slli64 s0 - 8860: 030d addi t1,t1,3 - 8862: 0900 addi s0,sp,144 - 8864: 0000 unimp - 8866: 0001 nop - 8868: 0402 c.slli64 s0 - 886a: 030d addi t1,t1,3 + 8756: 0001 nop + 8758: 0402 c.slli64 s0 + 875a: 030e slli t1,t1,0x3 + 875c: 0900 addi s0,sp,144 + 875e: 000c 0xc + 8760: 0001 nop + 8762: 0402 c.slli64 s0 + 8764: 035c addi a5,sp,388 + 8766: 0900 addi s0,sp,144 + 8768: 0000 unimp + 876a: 0001 nop + 876c: 0402 c.slli64 s0 + 876e: 035c addi a5,sp,388 + 8770: 0901 addi s2,s2,0 + 8772: 0000 unimp + 8774: 0001 nop + 8776: 0402 c.slli64 s0 + 8778: 035c addi a5,sp,388 + 877a: 0900 addi s0,sp,144 + 877c: 0000 unimp + 877e: 0001 nop + 8780: 0402 c.slli64 s0 + 8782: 035c addi a5,sp,388 + 8784: 0900 addi s0,sp,144 + 8786: 0000 unimp + 8788: 0001 nop + 878a: 0402 c.slli64 s0 + 878c: 035c addi a5,sp,388 + 878e: 0902 c.slli64 s2 + 8790: 0000 unimp + 8792: 0501 addi a0,a0,0 + 8794: 0001 nop + 8796: 0402 c.slli64 s0 + 8798: 065c addi a5,sp,772 + 879a: 00090103 lb sp,0(s2) + 879e: 0100 addi s0,sp,128 + 87a0: 0305 addi t1,t1,1 + 87a2: 0200 addi s0,sp,256 + 87a4: 0d04 addi s1,sp,656 + 87a6: 0306 slli t1,t1,0x1 + 87a8: 097c addi a5,sp,156 + 87aa: 0008 0x8 + 87ac: 0001 nop + 87ae: 0402 c.slli64 s0 + 87b0: 030d addi t1,t1,3 + 87b2: 0900 addi s0,sp,144 + 87b4: 0000 unimp + 87b6: 0001 nop + 87b8: 0402 c.slli64 s0 + 87ba: 060d addi a2,a2,3 + 87bc: 00097f03 0x97f03 + 87c0: 0100 addi s0,sp,128 + 87c2: 0200 addi s0,sp,256 + 87c4: 0d04 addi s1,sp,656 + 87c6: 04090103 lb sp,64(s2) + 87ca: 0100 addi s0,sp,128 + 87cc: 0200 addi s0,sp,256 + 87ce: 0d04 addi s1,sp,656 + 87d0: 04097f03 0x4097f03 + 87d4: 0100 addi s0,sp,128 + 87d6: 0200 addi s0,sp,256 + 87d8: 0d04 addi s1,sp,656 + 87da: 04090103 lb sp,64(s2) + 87de: 0100 addi s0,sp,128 + 87e0: 0200 addi s0,sp,256 + 87e2: 0d04 addi s1,sp,656 + 87e4: 0306 slli t1,t1,0x1 + 87e6: 0900 addi s0,sp,144 + 87e8: 0014 0x14 + 87ea: 0001 nop + 87ec: 0402 c.slli64 s0 + 87ee: 030d addi t1,t1,3 + 87f0: 0900 addi s0,sp,144 + 87f2: 0000 unimp + 87f4: 0001 nop + 87f6: 0402 c.slli64 s0 + 87f8: 030d addi t1,t1,3 + 87fa: 0900 addi s0,sp,144 + 87fc: 0000 unimp + 87fe: 0001 nop + 8800: 0402 c.slli64 s0 + 8802: 030d addi t1,t1,3 + 8804: 0900 addi s0,sp,144 + 8806: 0000 unimp + 8808: 0001 nop + 880a: 0402 c.slli64 s0 + 880c: 030d addi t1,t1,3 + 880e: 0900 addi s0,sp,144 + 8810: 0000 unimp + 8812: 0001 nop + 8814: 0402 c.slli64 s0 + 8816: 030d addi t1,t1,3 + 8818: 0900 addi s0,sp,144 + 881a: 0000 unimp + 881c: 0001 nop + 881e: 0402 c.slli64 s0 + 8820: 030d addi t1,t1,3 + 8822: 0900 addi s0,sp,144 + 8824: 0000 unimp + 8826: 0001 nop + 8828: 0402 c.slli64 s0 + 882a: 030d addi t1,t1,3 + 882c: 0900 addi s0,sp,144 + 882e: 0000 unimp + 8830: 0001 nop + 8832: 0402 c.slli64 s0 + 8834: 030d addi t1,t1,3 + 8836: 0900 addi s0,sp,144 + 8838: 0000 unimp + 883a: 0001 nop + 883c: 0402 c.slli64 s0 + 883e: 030d addi t1,t1,3 + 8840: 0900 addi s0,sp,144 + 8842: 0000 unimp + 8844: 0001 nop + 8846: 0402 c.slli64 s0 + 8848: 030d addi t1,t1,3 + 884a: 0900 addi s0,sp,144 + 884c: 0000 unimp + 884e: 0601 addi a2,a2,0 + 8850: 08090003 lb zero,128(s2) + 8854: 0100 addi s0,sp,128 + 8856: 0200 addi s0,sp,256 + 8858: 3f04 fld fs1,56(a4) + 885a: 0306 slli t1,t1,0x1 + 885c: 0900 addi s0,sp,144 + 885e: 0028 addi a0,sp,8 + 8860: 0001 nop + 8862: 0402 c.slli64 s0 + 8864: 0342 slli t1,t1,0x10 + 8866: 0900 addi s0,sp,144 + 8868: 000c 0xc + 886a: 0301 addi t1,t1,0 886c: 0900 addi s0,sp,144 - 886e: 0000 unimp - 8870: 0001 nop - 8872: 0402 c.slli64 s0 - 8874: 030d addi t1,t1,3 - 8876: 0900 addi s0,sp,144 - 8878: 0000 unimp - 887a: 0001 nop - 887c: 0402 c.slli64 s0 - 887e: 030d addi t1,t1,3 - 8880: 0900 addi s0,sp,144 - 8882: 0000 unimp - 8884: 0001 nop - 8886: 0402 c.slli64 s0 - 8888: 030d addi t1,t1,3 - 888a: 0900 addi s0,sp,144 - 888c: 0000 unimp - 888e: 0001 nop - 8890: 0402 c.slli64 s0 - 8892: 030d addi t1,t1,3 - 8894: 0900 addi s0,sp,144 - 8896: 0000 unimp - 8898: 0001 nop - 889a: 0402 c.slli64 s0 - 889c: 030d addi t1,t1,3 - 889e: 0900 addi s0,sp,144 - 88a0: 0000 unimp - 88a2: 0601 addi a2,a2,0 - 88a4: 08090003 lb zero,128(s2) - 88a8: 0100 addi s0,sp,128 - 88aa: 0200 addi s0,sp,256 - 88ac: 3f04 fld fs1,56(a4) - 88ae: 0306 slli t1,t1,0x1 - 88b0: 0900 addi s0,sp,144 - 88b2: 0028 addi a0,sp,8 - 88b4: 0001 nop - 88b6: 0402 c.slli64 s0 - 88b8: 0342 slli t1,t1,0x10 - 88ba: 0900 addi s0,sp,144 - 88bc: 000c 0xc - 88be: 0301 addi t1,t1,0 - 88c0: 0900 addi s0,sp,144 - 88c2: 0018 0x18 - 88c4: 0301 addi t1,t1,0 - 88c6: 0900 addi s0,sp,144 - 88c8: 0014 0x14 - 88ca: 0301 addi t1,t1,0 - 88cc: 0900 addi s0,sp,144 - 88ce: 0000 unimp - 88d0: 0001 nop - 88d2: 0402 c.slli64 s0 - 88d4: 0345 addi t1,t1,17 - 88d6: 0900 addi s0,sp,144 - 88d8: 0000 unimp - 88da: 0001 nop - 88dc: 0402 c.slli64 s0 - 88de: 0345 addi t1,t1,17 - 88e0: 0900 addi s0,sp,144 - 88e2: 0000 unimp - 88e4: 0001 nop - 88e6: 0402 c.slli64 s0 - 88e8: 0345 addi t1,t1,17 - 88ea: 0900 addi s0,sp,144 - 88ec: 0000 unimp - 88ee: 0001 nop - 88f0: 0402 c.slli64 s0 - 88f2: 0345 addi t1,t1,17 - 88f4: 0900 addi s0,sp,144 - 88f6: 0000 unimp - 88f8: 0001 nop - 88fa: 0402 c.slli64 s0 - 88fc: 0345 addi t1,t1,17 - 88fe: 0900 addi s0,sp,144 - 8900: 0000 unimp - 8902: 0001 nop - 8904: 0402 c.slli64 s0 - 8906: 0345 addi t1,t1,17 - 8908: 0900 addi s0,sp,144 - 890a: 0000 unimp - 890c: 0001 nop - 890e: 0402 c.slli64 s0 - 8910: 0345 addi t1,t1,17 - 8912: 0900 addi s0,sp,144 - 8914: 0000 unimp - 8916: 0001 nop - 8918: 0402 c.slli64 s0 - 891a: 0345 addi t1,t1,17 - 891c: 0900 addi s0,sp,144 - 891e: 0000 unimp - 8920: 0001 nop - 8922: 0402 c.slli64 s0 - 8924: 0345 addi t1,t1,17 - 8926: 0900 addi s0,sp,144 - 8928: 0004 0x4 - 892a: 0001 nop - 892c: 0402 c.slli64 s0 - 892e: 0345 addi t1,t1,17 - 8930: 0900 addi s0,sp,144 - 8932: 0000 unimp - 8934: 0001 nop - 8936: 0402 c.slli64 s0 - 8938: 034e slli t1,t1,0x13 - 893a: 0900 addi s0,sp,144 - 893c: 0004 0x4 - 893e: 0001 nop - 8940: 0402 c.slli64 s0 - 8942: 0341 addi t1,t1,16 - 8944: 0900 addi s0,sp,144 - 8946: 0008 0x8 - 8948: 0001 nop - 894a: 0402 c.slli64 s0 - 894c: 0341 addi t1,t1,16 - 894e: 0900 addi s0,sp,144 - 8950: 0014 0x14 - 8952: 0901 addi s2,s2,0 - 8954: 0004 0x4 - 8956: 0100 addi s0,sp,128 - 8958: 9901 andi a0,a0,-32 - 895a: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> - 895e: 9400 0x9400 - 8960: 0000 unimp - 8962: 0100 addi s0,sp,128 - 8964: fb01 bnez a4,8874 <_start-0x7fff778c> - 8966: 0d0e slli s10,s10,0x3 - 8968: 0100 addi s0,sp,128 - 896a: 0101 addi sp,sp,0 - 896c: 0001 nop - 896e: 0000 unimp - 8970: 0001 nop - 8972: 0100 addi s0,sp,128 - 8974: 2e2e fld ft8,200(sp) - 8976: 2f2e2e2f 0x2f2e2e2f - 897a: 2e2e fld ft8,200(sp) - 897c: 2f2e2e2f 0x2f2e2e2f - 8980: 6972 flw fs2,28(sp) - 8982: 2d766373 csrrsi t1,0x2d7,12 - 8986: 2f636367 0x2f636367 - 898a: 696c flw fa1,84(a0) - 898c: 6762 flw fa4,24(sp) - 898e: 732f6363 bltu t5,s2,90b4 <_start-0x7fff6f4c> - 8992: 2d74666f jal a2,4f468 <_start-0x7ffb0b98> - 8996: 7066 flw ft0,120(sp) - 8998: 2e00 fld fs0,24(a2) - 899a: 2f2e fld ft10,200(sp) - 899c: 2e2e fld ft8,200(sp) - 899e: 2f2e2e2f 0x2f2e2e2f - 89a2: 2e2e fld ft8,200(sp) - 89a4: 7369722f 0x7369722f - 89a8: 672d7663 bgeu s10,s2,9014 <_start-0x7fff6fec> - 89ac: 6c2f6363 bltu t5,sp,9072 <_start-0x7fff6f8e> - 89b0: 6269 lui tp,0x1a - 89b2: 2f636367 0x2f636367 - 89b6: 2e2e fld ft8,200(sp) - 89b8: 636e692f 0x636e692f - 89bc: 756c flw fa1,108(a0) - 89be: 6564 flw fs1,76(a0) + 886e: 0018 0x18 + 8870: 0301 addi t1,t1,0 + 8872: 0900 addi s0,sp,144 + 8874: 0014 0x14 + 8876: 0301 addi t1,t1,0 + 8878: 0900 addi s0,sp,144 + 887a: 0000 unimp + 887c: 0001 nop + 887e: 0402 c.slli64 s0 + 8880: 0345 addi t1,t1,17 + 8882: 0900 addi s0,sp,144 + 8884: 0000 unimp + 8886: 0001 nop + 8888: 0402 c.slli64 s0 + 888a: 0345 addi t1,t1,17 + 888c: 0900 addi s0,sp,144 + 888e: 0000 unimp + 8890: 0001 nop + 8892: 0402 c.slli64 s0 + 8894: 0345 addi t1,t1,17 + 8896: 0900 addi s0,sp,144 + 8898: 0000 unimp + 889a: 0001 nop + 889c: 0402 c.slli64 s0 + 889e: 0345 addi t1,t1,17 + 88a0: 0900 addi s0,sp,144 + 88a2: 0000 unimp + 88a4: 0001 nop + 88a6: 0402 c.slli64 s0 + 88a8: 0345 addi t1,t1,17 + 88aa: 0900 addi s0,sp,144 + 88ac: 0000 unimp + 88ae: 0001 nop + 88b0: 0402 c.slli64 s0 + 88b2: 0345 addi t1,t1,17 + 88b4: 0900 addi s0,sp,144 + 88b6: 0000 unimp + 88b8: 0001 nop + 88ba: 0402 c.slli64 s0 + 88bc: 0345 addi t1,t1,17 + 88be: 0900 addi s0,sp,144 + 88c0: 0000 unimp + 88c2: 0001 nop + 88c4: 0402 c.slli64 s0 + 88c6: 0345 addi t1,t1,17 + 88c8: 0900 addi s0,sp,144 + 88ca: 0000 unimp + 88cc: 0001 nop + 88ce: 0402 c.slli64 s0 + 88d0: 0345 addi t1,t1,17 + 88d2: 0900 addi s0,sp,144 + 88d4: 0004 0x4 + 88d6: 0001 nop + 88d8: 0402 c.slli64 s0 + 88da: 0345 addi t1,t1,17 + 88dc: 0900 addi s0,sp,144 + 88de: 0000 unimp + 88e0: 0001 nop + 88e2: 0402 c.slli64 s0 + 88e4: 034e slli t1,t1,0x13 + 88e6: 0900 addi s0,sp,144 + 88e8: 0004 0x4 + 88ea: 0001 nop + 88ec: 0402 c.slli64 s0 + 88ee: 0341 addi t1,t1,16 + 88f0: 0900 addi s0,sp,144 + 88f2: 0008 0x8 + 88f4: 0001 nop + 88f6: 0402 c.slli64 s0 + 88f8: 0341 addi t1,t1,16 + 88fa: 0900 addi s0,sp,144 + 88fc: 0014 0x14 + 88fe: 0901 addi s2,s2,0 + 8900: 0004 0x4 + 8902: 0100 addi s0,sp,128 + 8904: 9901 andi a0,a0,-32 + 8906: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> + 890a: 9400 0x9400 + 890c: 0000 unimp + 890e: 0100 addi s0,sp,128 + 8910: fb01 bnez a4,8820 <_start-0x7fff77e0> + 8912: 0d0e slli s10,s10,0x3 + 8914: 0100 addi s0,sp,128 + 8916: 0101 addi sp,sp,0 + 8918: 0001 nop + 891a: 0000 unimp + 891c: 0001 nop + 891e: 0100 addi s0,sp,128 + 8920: 2e2e fld ft8,200(sp) + 8922: 2f2e2e2f 0x2f2e2e2f + 8926: 2e2e fld ft8,200(sp) + 8928: 2f2e2e2f 0x2f2e2e2f + 892c: 6972 flw fs2,28(sp) + 892e: 2d766373 csrrsi t1,0x2d7,12 + 8932: 2f636367 0x2f636367 + 8936: 696c flw fa1,84(a0) + 8938: 6762 flw fa4,24(sp) + 893a: 732f6363 bltu t5,s2,9060 <_start-0x7fff6fa0> + 893e: 2d74666f jal a2,4f414 <_start-0x7ffb0bec> + 8942: 7066 flw ft0,120(sp) + 8944: 2e00 fld fs0,24(a2) + 8946: 2f2e fld ft10,200(sp) + 8948: 2e2e fld ft8,200(sp) + 894a: 2f2e2e2f 0x2f2e2e2f + 894e: 2e2e fld ft8,200(sp) + 8950: 7369722f 0x7369722f + 8954: 672d7663 bgeu s10,s2,8fc0 <_start-0x7fff7040> + 8958: 6c2f6363 bltu t5,sp,901e <_start-0x7fff6fe2> + 895c: 6269 lui tp,0x1a + 895e: 2f636367 0x2f636367 + 8962: 2e2e fld ft8,200(sp) + 8964: 636e692f 0x636e692f + 8968: 756c flw fa1,108(a0) + 896a: 6564 flw fs1,76(a0) + 896c: 0000 unimp + 896e: 6c66 flw fs8,88(sp) + 8970: 7374616f jal sp,4f8a6 <_start-0x7ffb075a> + 8974: 7469 lui s0,0xffffa + 8976: 2e66 fld ft8,88(sp) + 8978: 00010063 beqz sp,8978 <_start-0x7fff7688> + 897c: 7300 flw fs0,32(a4) + 897e: 2d74666f jal a2,4f454 <_start-0x7ffb0bac> + 8982: 7066 flw ft0,120(sp) + 8984: 682e flw fa6,200(sp) + 8986: 0100 addi s0,sp,128 + 8988: 0000 unimp + 898a: 7571 lui a0,0xffffc + 898c: 6461 lui s0,0x18 + 898e: 682e flw fa6,200(sp) + 8990: 0100 addi s0,sp,128 + 8992: 0000 unimp + 8994: 6f6c flw fa1,92(a4) + 8996: 676e flw fa4,216(sp) + 8998: 6f6c flw fa1,92(a4) + 899a: 676e flw fa4,216(sp) + 899c: 682e flw fa6,200(sp) + 899e: 0200 addi s0,sp,256 + 89a0: 0000 unimp + 89a2: 0500 addi s0,sp,640 + 89a4: 0001 nop + 89a6: 0205 addi tp,tp,1 + 89a8: 4338 lw a4,64(a4) + 89aa: 8001 c.srli64 s0 + 89ac: 05012403 lw s0,80(sp) + 89b0: 09010303 lb t1,144(sp) + 89b4: 0000 unimp + 89b6: 0301 addi t1,t1,0 + 89b8: 0900 addi s0,sp,144 + 89ba: 0000 unimp + 89bc: 0301 addi t1,t1,0 + 89be: 0900 addi s0,sp,144 89c0: 0000 unimp - 89c2: 6c66 flw fs8,88(sp) - 89c4: 7374616f jal sp,4f8fa <_start-0x7ffb0706> - 89c8: 7469 lui s0,0xffffa - 89ca: 2e66 fld ft8,88(sp) - 89cc: 00010063 beqz sp,89cc <_start-0x7fff7634> - 89d0: 7300 flw fs0,32(a4) - 89d2: 2d74666f jal a2,4f4a8 <_start-0x7ffb0b58> - 89d6: 7066 flw ft0,120(sp) - 89d8: 682e flw fa6,200(sp) - 89da: 0100 addi s0,sp,128 - 89dc: 0000 unimp - 89de: 7571 lui a0,0xffffc - 89e0: 6461 lui s0,0x18 - 89e2: 682e flw fa6,200(sp) - 89e4: 0100 addi s0,sp,128 - 89e6: 0000 unimp - 89e8: 6f6c flw fa1,92(a4) - 89ea: 676e flw fa4,216(sp) - 89ec: 6f6c flw fa1,92(a4) - 89ee: 676e flw fa4,216(sp) - 89f0: 682e flw fa6,200(sp) + 89c2: 0301 addi t1,t1,0 + 89c4: 0900 addi s0,sp,144 + 89c6: 0000 unimp + 89c8: 0301 addi t1,t1,0 + 89ca: 0901 addi s2,s2,0 + 89cc: 0000 unimp + 89ce: 0301 addi t1,t1,0 + 89d0: 0902 c.slli64 s2 + 89d2: 0000 unimp + 89d4: 0301 addi t1,t1,0 + 89d6: 0900 addi s0,sp,144 + 89d8: 0000 unimp + 89da: 0501 addi a0,a0,0 + 89dc: 0601 addi a2,a2,0 + 89de: 00097c03 0x97c03 + 89e2: 0100 addi s0,sp,128 + 89e4: 14090003 lb zero,320(s2) + 89e8: 0100 addi s0,sp,128 + 89ea: 0305 addi t1,t1,1 + 89ec: 04090403 lb s0,64(s2) + 89f0: 0100 addi s0,sp,128 89f2: 0200 addi s0,sp,256 - 89f4: 0000 unimp - 89f6: 0500 addi s0,sp,640 - 89f8: 0001 nop - 89fa: 0205 addi tp,tp,1 - 89fc: 4274 lw a3,68(a2) - 89fe: 8001 c.srli64 s0 - 8a00: 05012403 lw s0,80(sp) - 8a04: 09010303 lb t1,144(sp) - 8a08: 0000 unimp + 89f4: 0104 addi s1,sp,128 + 89f6: 0306 slli t1,t1,0x1 + 89f8: 0900 addi s0,sp,144 + 89fa: 0004 0x4 + 89fc: 0001 nop + 89fe: 0402 c.slli64 s0 + 8a00: 0301 addi t1,t1,0 + 8a02: 0900 addi s0,sp,144 + 8a04: 0000 unimp + 8a06: 0001 nop + 8a08: 0402 c.slli64 s0 8a0a: 0301 addi t1,t1,0 8a0c: 0900 addi s0,sp,144 - 8a0e: 0000 unimp - 8a10: 0301 addi t1,t1,0 - 8a12: 0900 addi s0,sp,144 - 8a14: 0000 unimp - 8a16: 0301 addi t1,t1,0 - 8a18: 0900 addi s0,sp,144 - 8a1a: 0000 unimp - 8a1c: 0301 addi t1,t1,0 - 8a1e: 0901 addi s2,s2,0 - 8a20: 0000 unimp - 8a22: 0301 addi t1,t1,0 - 8a24: 0902 c.slli64 s2 - 8a26: 0000 unimp + 8a0e: 0014 0x14 + 8a10: 0001 nop + 8a12: 0402 c.slli64 s0 + 8a14: 0301 addi t1,t1,0 + 8a16: 0900 addi s0,sp,144 + 8a18: 0000 unimp + 8a1a: 0001 nop + 8a1c: 0402 c.slli64 s0 + 8a1e: 0301 addi t1,t1,0 + 8a20: 0900 addi s0,sp,144 + 8a22: 0000 unimp + 8a24: 0001 nop + 8a26: 0402 c.slli64 s0 8a28: 0301 addi t1,t1,0 8a2a: 0900 addi s0,sp,144 8a2c: 0000 unimp - 8a2e: 0501 addi a0,a0,0 - 8a30: 0601 addi a2,a2,0 - 8a32: 00097c03 0x97c03 - 8a36: 0100 addi s0,sp,128 - 8a38: 14090003 lb zero,320(s2) - 8a3c: 0100 addi s0,sp,128 - 8a3e: 0305 addi t1,t1,1 - 8a40: 04090403 lb s0,64(s2) - 8a44: 0100 addi s0,sp,128 - 8a46: 0200 addi s0,sp,256 - 8a48: 0104 addi s1,sp,128 - 8a4a: 0306 slli t1,t1,0x1 - 8a4c: 0900 addi s0,sp,144 - 8a4e: 0004 0x4 - 8a50: 0001 nop - 8a52: 0402 c.slli64 s0 - 8a54: 0301 addi t1,t1,0 - 8a56: 0900 addi s0,sp,144 - 8a58: 0000 unimp - 8a5a: 0001 nop - 8a5c: 0402 c.slli64 s0 - 8a5e: 0301 addi t1,t1,0 - 8a60: 0900 addi s0,sp,144 - 8a62: 0014 0x14 - 8a64: 0001 nop - 8a66: 0402 c.slli64 s0 - 8a68: 0301 addi t1,t1,0 - 8a6a: 0900 addi s0,sp,144 - 8a6c: 0000 unimp - 8a6e: 0001 nop - 8a70: 0402 c.slli64 s0 - 8a72: 0301 addi t1,t1,0 - 8a74: 0900 addi s0,sp,144 - 8a76: 0000 unimp - 8a78: 0001 nop - 8a7a: 0402 c.slli64 s0 - 8a7c: 0301 addi t1,t1,0 - 8a7e: 0900 addi s0,sp,144 - 8a80: 0000 unimp - 8a82: 0001 nop - 8a84: 0402 c.slli64 s0 - 8a86: 0301 addi t1,t1,0 - 8a88: 0900 addi s0,sp,144 - 8a8a: 0000 unimp - 8a8c: 0001 nop - 8a8e: 0402 c.slli64 s0 - 8a90: 0301 addi t1,t1,0 - 8a92: 0900 addi s0,sp,144 - 8a94: 0000 unimp - 8a96: 0001 nop - 8a98: 0402 c.slli64 s0 - 8a9a: 0301 addi t1,t1,0 - 8a9c: 0900 addi s0,sp,144 - 8a9e: 0000 unimp - 8aa0: 0001 nop - 8aa2: 0402 c.slli64 s0 - 8aa4: 0301 addi t1,t1,0 - 8aa6: 0900 addi s0,sp,144 - 8aa8: 0004 0x4 - 8aaa: 0001 nop - 8aac: 0402 c.slli64 s0 - 8aae: 0301 addi t1,t1,0 - 8ab0: 0900 addi s0,sp,144 - 8ab2: 0000 unimp - 8ab4: 0001 nop - 8ab6: 0402 c.slli64 s0 - 8ab8: 0301 addi t1,t1,0 - 8aba: 0900 addi s0,sp,144 - 8abc: 0010 0x10 - 8abe: 0001 nop - 8ac0: 0402 c.slli64 s0 - 8ac2: 0301 addi t1,t1,0 - 8ac4: 0900 addi s0,sp,144 - 8ac6: 0000 unimp - 8ac8: 0001 nop - 8aca: 0402 c.slli64 s0 - 8acc: 0301 addi t1,t1,0 - 8ace: 0900 addi s0,sp,144 - 8ad0: 0000 unimp - 8ad2: 0001 nop - 8ad4: 0402 c.slli64 s0 - 8ad6: 0301 addi t1,t1,0 - 8ad8: 0900 addi s0,sp,144 - 8ada: 0000 unimp - 8adc: 0001 nop - 8ade: 0402 c.slli64 s0 - 8ae0: 0301 addi t1,t1,0 - 8ae2: 0900 addi s0,sp,144 - 8ae4: 0004 0x4 - 8ae6: 0001 nop - 8ae8: 0402 c.slli64 s0 - 8aea: 0301 addi t1,t1,0 - 8aec: 0900 addi s0,sp,144 - 8aee: 0008 0x8 - 8af0: 0001 nop - 8af2: 0402 c.slli64 s0 - 8af4: 0301 addi t1,t1,0 - 8af6: 0900 addi s0,sp,144 - 8af8: 0004 0x4 - 8afa: 0001 nop - 8afc: 0402 c.slli64 s0 - 8afe: 0301 addi t1,t1,0 - 8b00: 0900 addi s0,sp,144 - 8b02: 0004 0x4 - 8b04: 0001 nop - 8b06: 0402 c.slli64 s0 - 8b08: 0301 addi t1,t1,0 - 8b0a: 0900 addi s0,sp,144 - 8b0c: 0000 unimp - 8b0e: 0001 nop - 8b10: 0402 c.slli64 s0 + 8a2e: 0001 nop + 8a30: 0402 c.slli64 s0 + 8a32: 0301 addi t1,t1,0 + 8a34: 0900 addi s0,sp,144 + 8a36: 0000 unimp + 8a38: 0001 nop + 8a3a: 0402 c.slli64 s0 + 8a3c: 0301 addi t1,t1,0 + 8a3e: 0900 addi s0,sp,144 + 8a40: 0000 unimp + 8a42: 0001 nop + 8a44: 0402 c.slli64 s0 + 8a46: 0301 addi t1,t1,0 + 8a48: 0900 addi s0,sp,144 + 8a4a: 0000 unimp + 8a4c: 0001 nop + 8a4e: 0402 c.slli64 s0 + 8a50: 0301 addi t1,t1,0 + 8a52: 0900 addi s0,sp,144 + 8a54: 0004 0x4 + 8a56: 0001 nop + 8a58: 0402 c.slli64 s0 + 8a5a: 0301 addi t1,t1,0 + 8a5c: 0900 addi s0,sp,144 + 8a5e: 0000 unimp + 8a60: 0001 nop + 8a62: 0402 c.slli64 s0 + 8a64: 0301 addi t1,t1,0 + 8a66: 0900 addi s0,sp,144 + 8a68: 0010 0x10 + 8a6a: 0001 nop + 8a6c: 0402 c.slli64 s0 + 8a6e: 0301 addi t1,t1,0 + 8a70: 0900 addi s0,sp,144 + 8a72: 0000 unimp + 8a74: 0001 nop + 8a76: 0402 c.slli64 s0 + 8a78: 0301 addi t1,t1,0 + 8a7a: 0900 addi s0,sp,144 + 8a7c: 0000 unimp + 8a7e: 0001 nop + 8a80: 0402 c.slli64 s0 + 8a82: 0301 addi t1,t1,0 + 8a84: 0900 addi s0,sp,144 + 8a86: 0000 unimp + 8a88: 0001 nop + 8a8a: 0402 c.slli64 s0 + 8a8c: 0301 addi t1,t1,0 + 8a8e: 0900 addi s0,sp,144 + 8a90: 0004 0x4 + 8a92: 0001 nop + 8a94: 0402 c.slli64 s0 + 8a96: 0301 addi t1,t1,0 + 8a98: 0900 addi s0,sp,144 + 8a9a: 0008 0x8 + 8a9c: 0001 nop + 8a9e: 0402 c.slli64 s0 + 8aa0: 0301 addi t1,t1,0 + 8aa2: 0900 addi s0,sp,144 + 8aa4: 0004 0x4 + 8aa6: 0001 nop + 8aa8: 0402 c.slli64 s0 + 8aaa: 0301 addi t1,t1,0 + 8aac: 0900 addi s0,sp,144 + 8aae: 0004 0x4 + 8ab0: 0001 nop + 8ab2: 0402 c.slli64 s0 + 8ab4: 0301 addi t1,t1,0 + 8ab6: 0900 addi s0,sp,144 + 8ab8: 0000 unimp + 8aba: 0001 nop + 8abc: 0402 c.slli64 s0 + 8abe: 0301 addi t1,t1,0 + 8ac0: 0900 addi s0,sp,144 + 8ac2: 0000 unimp + 8ac4: 0001 nop + 8ac6: 0402 c.slli64 s0 + 8ac8: 0301 addi t1,t1,0 + 8aca: 0900 addi s0,sp,144 + 8acc: 0000 unimp + 8ace: 0001 nop + 8ad0: 0402 c.slli64 s0 + 8ad2: 0301 addi t1,t1,0 + 8ad4: 0900 addi s0,sp,144 + 8ad6: 0000 unimp + 8ad8: 0001 nop + 8ada: 0402 c.slli64 s0 + 8adc: 0301 addi t1,t1,0 + 8ade: 0900 addi s0,sp,144 + 8ae0: 0000 unimp + 8ae2: 0001 nop + 8ae4: 0402 c.slli64 s0 + 8ae6: 0301 addi t1,t1,0 + 8ae8: 0900 addi s0,sp,144 + 8aea: 0000 unimp + 8aec: 0001 nop + 8aee: 0402 c.slli64 s0 + 8af0: 0301 addi t1,t1,0 + 8af2: 0900 addi s0,sp,144 + 8af4: 0000 unimp + 8af6: 0001 nop + 8af8: 0402 c.slli64 s0 + 8afa: 0301 addi t1,t1,0 + 8afc: 0900 addi s0,sp,144 + 8afe: 0000 unimp + 8b00: 0301 addi t1,t1,0 + 8b02: 0900 addi s0,sp,144 + 8b04: 0008 0x8 + 8b06: 0301 addi t1,t1,0 + 8b08: 0900 addi s0,sp,144 + 8b0a: 0008 0x8 + 8b0c: 0301 addi t1,t1,0 + 8b0e: 0900 addi s0,sp,144 + 8b10: 0010 0x10 8b12: 0301 addi t1,t1,0 8b14: 0900 addi s0,sp,144 8b16: 0000 unimp 8b18: 0001 nop 8b1a: 0402 c.slli64 s0 - 8b1c: 0301 addi t1,t1,0 + 8b1c: 0320 addi s0,sp,392 8b1e: 0900 addi s0,sp,144 8b20: 0000 unimp - 8b22: 0001 nop - 8b24: 0402 c.slli64 s0 - 8b26: 0301 addi t1,t1,0 - 8b28: 0900 addi s0,sp,144 - 8b2a: 0000 unimp - 8b2c: 0001 nop - 8b2e: 0402 c.slli64 s0 - 8b30: 0301 addi t1,t1,0 - 8b32: 0900 addi s0,sp,144 - 8b34: 0000 unimp - 8b36: 0001 nop - 8b38: 0402 c.slli64 s0 + 8b22: 0301 addi t1,t1,0 + 8b24: 0900 addi s0,sp,144 + 8b26: 001c 0x1c + 8b28: 0301 addi t1,t1,0 + 8b2a: 0900 addi s0,sp,144 + 8b2c: 0000 unimp + 8b2e: 0301 addi t1,t1,0 + 8b30: 0900 addi s0,sp,144 + 8b32: 0020 addi s0,sp,8 + 8b34: 0301 addi t1,t1,0 + 8b36: 0900 addi s0,sp,144 + 8b38: 0000 unimp 8b3a: 0301 addi t1,t1,0 8b3c: 0900 addi s0,sp,144 - 8b3e: 0000 unimp - 8b40: 0001 nop - 8b42: 0402 c.slli64 s0 - 8b44: 0301 addi t1,t1,0 - 8b46: 0900 addi s0,sp,144 - 8b48: 0000 unimp - 8b4a: 0001 nop - 8b4c: 0402 c.slli64 s0 - 8b4e: 0301 addi t1,t1,0 - 8b50: 0900 addi s0,sp,144 - 8b52: 0000 unimp - 8b54: 0301 addi t1,t1,0 - 8b56: 0900 addi s0,sp,144 - 8b58: 0008 0x8 - 8b5a: 0301 addi t1,t1,0 - 8b5c: 0900 addi s0,sp,144 - 8b5e: 0008 0x8 - 8b60: 0301 addi t1,t1,0 - 8b62: 0900 addi s0,sp,144 - 8b64: 0010 0x10 - 8b66: 0301 addi t1,t1,0 - 8b68: 0900 addi s0,sp,144 - 8b6a: 0000 unimp + 8b3e: 0008 0x8 + 8b40: 0301 addi t1,t1,0 + 8b42: 0900 addi s0,sp,144 + 8b44: 0004 0x4 + 8b46: 0301 addi t1,t1,0 + 8b48: 0900 addi s0,sp,144 + 8b4a: 0000 unimp + 8b4c: 0001 nop + 8b4e: 0402 c.slli64 s0 + 8b50: 00030623 sb zero,12(t1) + 8b54: 0409 addi s0,s0,2 + 8b56: 0100 addi s0,sp,128 + 8b58: 0200 addi s0,sp,256 + 8b5a: 2304 fld fs1,0(a4) + 8b5c: 0306 slli t1,t1,0x1 + 8b5e: 0900 addi s0,sp,144 + 8b60: 0004 0x4 + 8b62: 0001 nop + 8b64: 0402 c.slli64 s0 + 8b66: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 8b6a: 0010 0x10 8b6c: 0001 nop 8b6e: 0402 c.slli64 s0 - 8b70: 0320 addi s0,sp,392 - 8b72: 0900 addi s0,sp,144 - 8b74: 0000 unimp - 8b76: 0301 addi t1,t1,0 - 8b78: 0900 addi s0,sp,144 - 8b7a: 001c 0x1c - 8b7c: 0301 addi t1,t1,0 - 8b7e: 0900 addi s0,sp,144 - 8b80: 0000 unimp - 8b82: 0301 addi t1,t1,0 - 8b84: 0900 addi s0,sp,144 - 8b86: 0020 addi s0,sp,8 - 8b88: 0301 addi t1,t1,0 - 8b8a: 0900 addi s0,sp,144 - 8b8c: 0000 unimp - 8b8e: 0301 addi t1,t1,0 - 8b90: 0900 addi s0,sp,144 - 8b92: 0008 0x8 - 8b94: 0301 addi t1,t1,0 - 8b96: 0900 addi s0,sp,144 - 8b98: 0004 0x4 - 8b9a: 0301 addi t1,t1,0 - 8b9c: 0900 addi s0,sp,144 - 8b9e: 0000 unimp - 8ba0: 0001 nop - 8ba2: 0402 c.slli64 s0 - 8ba4: 00030623 sb zero,12(t1) - 8ba8: 0409 addi s0,s0,2 - 8baa: 0100 addi s0,sp,128 - 8bac: 0200 addi s0,sp,256 - 8bae: 2304 fld fs1,0(a4) - 8bb0: 0306 slli t1,t1,0x1 - 8bb2: 0900 addi s0,sp,144 - 8bb4: 0004 0x4 - 8bb6: 0001 nop - 8bb8: 0402 c.slli64 s0 - 8bba: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 8bbe: 0010 0x10 - 8bc0: 0001 nop - 8bc2: 0402 c.slli64 s0 - 8bc4: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> - 8bc8: 0004 0x4 - 8bca: 0001 nop - 8bcc: 019b0403 lb s0,25(s6) - 8bd0: 04090003 lb zero,64(s2) - 8bd4: 0100 addi s0,sp,128 - 8bd6: 0300 addi s0,sp,384 - 8bd8: 9b04 0x9b04 - 8bda: 0301 addi t1,t1,0 - 8bdc: 0901 addi s2,s2,0 - 8bde: 0000 unimp - 8be0: 0001 nop - 8be2: 019b0403 lb s0,25(s6) - 8be6: 00090003 lb zero,0(s2) - 8bea: 0100 addi s0,sp,128 - 8bec: 0300 addi s0,sp,384 - 8bee: 9b04 0x9b04 - 8bf0: 0301 addi t1,t1,0 - 8bf2: 0900 addi s0,sp,144 - 8bf4: 0000 unimp - 8bf6: 0001 nop - 8bf8: 019b0403 lb s0,25(s6) - 8bfc: 00090003 lb zero,0(s2) - 8c00: 0100 addi s0,sp,128 - 8c02: 0300 addi s0,sp,384 - 8c04: 9b04 0x9b04 - 8c06: 0301 addi t1,t1,0 - 8c08: 0900 addi s0,sp,144 - 8c0a: 0000 unimp - 8c0c: 0001 nop - 8c0e: 019b0403 lb s0,25(s6) - 8c12: 00090003 lb zero,0(s2) - 8c16: 0100 addi s0,sp,128 - 8c18: 0105 addi sp,sp,1 - 8c1a: 0300 addi s0,sp,384 - 8c1c: 9b04 0x9b04 - 8c1e: 0601 addi a2,a2,0 - 8c20: 04090303 lb t1,64(s2) - 8c24: 0100 addi s0,sp,128 - 8c26: 0305 addi t1,t1,1 + 8b70: 09000323 sb a6,134(zero) # 86 <_start-0x7fffff7a> + 8b74: 0004 0x4 + 8b76: 0001 nop + 8b78: 019b0403 lb s0,25(s6) + 8b7c: 04090003 lb zero,64(s2) + 8b80: 0100 addi s0,sp,128 + 8b82: 0300 addi s0,sp,384 + 8b84: 9b04 0x9b04 + 8b86: 0301 addi t1,t1,0 + 8b88: 0901 addi s2,s2,0 + 8b8a: 0000 unimp + 8b8c: 0001 nop + 8b8e: 019b0403 lb s0,25(s6) + 8b92: 00090003 lb zero,0(s2) + 8b96: 0100 addi s0,sp,128 + 8b98: 0300 addi s0,sp,384 + 8b9a: 9b04 0x9b04 + 8b9c: 0301 addi t1,t1,0 + 8b9e: 0900 addi s0,sp,144 + 8ba0: 0000 unimp + 8ba2: 0001 nop + 8ba4: 019b0403 lb s0,25(s6) + 8ba8: 00090003 lb zero,0(s2) + 8bac: 0100 addi s0,sp,128 + 8bae: 0300 addi s0,sp,384 + 8bb0: 9b04 0x9b04 + 8bb2: 0301 addi t1,t1,0 + 8bb4: 0900 addi s0,sp,144 + 8bb6: 0000 unimp + 8bb8: 0001 nop + 8bba: 019b0403 lb s0,25(s6) + 8bbe: 00090003 lb zero,0(s2) + 8bc2: 0100 addi s0,sp,128 + 8bc4: 0105 addi sp,sp,1 + 8bc6: 0300 addi s0,sp,384 + 8bc8: 9b04 0x9b04 + 8bca: 0601 addi a2,a2,0 + 8bcc: 04090303 lb t1,64(s2) + 8bd0: 0100 addi s0,sp,128 + 8bd2: 0305 addi t1,t1,1 + 8bd4: 0300 addi s0,sp,384 + 8bd6: 9b04 0x9b04 + 8bd8: 0301 addi t1,t1,0 + 8bda: 097d addi s2,s2,31 + 8bdc: 0008 0x8 + 8bde: 0001 nop + 8be0: 019b0403 lb s0,25(s6) + 8be4: 0306 slli t1,t1,0x1 + 8be6: 0900 addi s0,sp,144 + 8be8: 0004 0x4 + 8bea: 0001 nop + 8bec: 019b0403 lb s0,25(s6) + 8bf0: 00090003 lb zero,0(s2) + 8bf4: 0100 addi s0,sp,128 + 8bf6: 0a05 addi s4,s4,1 + 8bf8: 0300 addi s0,sp,384 + 8bfa: 9b04 0x9b04 + 8bfc: 0601 addi a2,a2,0 + 8bfe: 08090203 lb tp,128(s2) + 8c02: 0100 addi s0,sp,128 + 8c04: 0305 addi t1,t1,1 + 8c06: 0300 addi s0,sp,384 + 8c08: 9b04 0x9b04 + 8c0a: 0301 addi t1,t1,0 + 8c0c: 097e slli s2,s2,0x1f + 8c0e: 0004 0x4 + 8c10: 0001 nop + 8c12: 019b0403 lb s0,25(s6) + 8c16: 0306 slli t1,t1,0x1 + 8c18: 0900 addi s0,sp,144 + 8c1a: 0004 0x4 + 8c1c: 0001 nop + 8c1e: 019b0403 lb s0,25(s6) + 8c22: 00090003 lb zero,0(s2) + 8c26: 0100 addi s0,sp,128 8c28: 0300 addi s0,sp,384 8c2a: 9b04 0x9b04 8c2c: 0301 addi t1,t1,0 - 8c2e: 097d addi s2,s2,31 - 8c30: 0008 0x8 - 8c32: 0001 nop - 8c34: 019b0403 lb s0,25(s6) - 8c38: 0306 slli t1,t1,0x1 - 8c3a: 0900 addi s0,sp,144 - 8c3c: 0004 0x4 - 8c3e: 0001 nop - 8c40: 019b0403 lb s0,25(s6) - 8c44: 00090003 lb zero,0(s2) - 8c48: 0100 addi s0,sp,128 - 8c4a: 0a05 addi s4,s4,1 - 8c4c: 0300 addi s0,sp,384 - 8c4e: 9b04 0x9b04 - 8c50: 0601 addi a2,a2,0 - 8c52: 08090203 lb tp,128(s2) - 8c56: 0100 addi s0,sp,128 - 8c58: 0305 addi t1,t1,1 - 8c5a: 0300 addi s0,sp,384 - 8c5c: 9b04 0x9b04 - 8c5e: 0301 addi t1,t1,0 - 8c60: 097e slli s2,s2,0x1f - 8c62: 0004 0x4 - 8c64: 0001 nop - 8c66: 019b0403 lb s0,25(s6) - 8c6a: 0306 slli t1,t1,0x1 - 8c6c: 0900 addi s0,sp,144 - 8c6e: 0004 0x4 - 8c70: 0001 nop - 8c72: 019b0403 lb s0,25(s6) - 8c76: 00090003 lb zero,0(s2) - 8c7a: 0100 addi s0,sp,128 - 8c7c: 0300 addi s0,sp,384 - 8c7e: 9b04 0x9b04 - 8c80: 0301 addi t1,t1,0 - 8c82: 0902 c.slli64 s2 - 8c84: 0000 unimp - 8c86: 0501 addi a0,a0,0 - 8c88: 0001 nop - 8c8a: 019b0403 lb s0,25(s6) - 8c8e: 0306 slli t1,t1,0x1 - 8c90: 0901 addi s2,s2,0 - 8c92: 0000 unimp - 8c94: 0501 addi a0,a0,0 - 8c96: 000a c.slli zero,0x2 - 8c98: 019b0403 lb s0,25(s6) - 8c9c: 04097f03 0x4097f03 - 8ca0: 0100 addi s0,sp,128 - 8ca2: 0105 addi sp,sp,1 - 8ca4: 0300 addi s0,sp,384 - 8ca6: 9b04 0x9b04 - 8ca8: 0301 addi t1,t1,0 - 8caa: 0901 addi s2,s2,0 - 8cac: 0008 0x8 - 8cae: 0501 addi a0,a0,0 - 8cb0: 000a c.slli zero,0x2 - 8cb2: 019b0403 lb s0,25(s6) - 8cb6: 04097f03 0x4097f03 - 8cba: 0100 addi s0,sp,128 - 8cbc: 0105 addi sp,sp,1 - 8cbe: 0300 addi s0,sp,384 - 8cc0: 9b04 0x9b04 - 8cc2: 0301 addi t1,t1,0 - 8cc4: 0901 addi s2,s2,0 - 8cc6: 0014 0x14 - 8cc8: 0501 addi a0,a0,0 - 8cca: 097c0303 lb t1,151(s8) - 8cce: 000c 0xc - 8cd0: 0001 nop - 8cd2: 0402 c.slli64 s0 - 8cd4: 0602 c.slli64 a2 - 8cd6: 08090003 lb zero,128(s2) - 8cda: 0100 addi s0,sp,128 - 8cdc: 0200 addi s0,sp,256 - 8cde: 0204 addi s1,sp,256 - 8ce0: 00090003 lb zero,0(s2) - 8ce4: 0100 addi s0,sp,128 - 8ce6: 0200 addi s0,sp,256 - 8ce8: 0204 addi s1,sp,256 - 8cea: 00090003 lb zero,0(s2) - 8cee: 0100 addi s0,sp,128 - 8cf0: 1809 addi a6,a6,-30 - 8cf2: 0000 unimp - 8cf4: 0101 addi sp,sp,0 - 8cf6: 05e6 slli a1,a1,0x19 - 8cf8: 0000 unimp - 8cfa: 00a20003 lb zero,10(tp) # 1a00a <_start-0x7ffe5ff6> - 8cfe: 0000 unimp - 8d00: 0101 addi sp,sp,0 - 8d02: 000d0efb 0xd0efb - 8d06: 0101 addi sp,sp,0 - 8d08: 0101 addi sp,sp,0 - 8d0a: 0000 unimp - 8d0c: 0100 addi s0,sp,128 - 8d0e: 0000 unimp - 8d10: 2e01 jal 9020 <_start-0x7fff6fe0> - 8d12: 2f2e fld ft10,200(sp) - 8d14: 2e2e fld ft8,200(sp) - 8d16: 2f2e2e2f 0x2f2e2e2f - 8d1a: 2e2e fld ft8,200(sp) - 8d1c: 7369722f 0x7369722f - 8d20: 672d7663 bgeu s10,s2,938c <_start-0x7fff6c74> - 8d24: 6c2f6363 bltu t5,sp,93ea <_start-0x7fff6c16> - 8d28: 6269 lui tp,0x1a - 8d2a: 2f636367 0x2f636367 - 8d2e: 74666f73 csrrsi t5,0x746,12 - 8d32: 662d lui a2,0xb - 8d34: 0070 addi a2,sp,12 - 8d36: 2e2e fld ft8,200(sp) - 8d38: 2f2e2e2f 0x2f2e2e2f - 8d3c: 2e2e fld ft8,200(sp) - 8d3e: 2f2e2e2f 0x2f2e2e2f - 8d42: 6972 flw fs2,28(sp) - 8d44: 2d766373 csrrsi t1,0x2d7,12 - 8d48: 2f636367 0x2f636367 - 8d4c: 696c flw fa1,84(a0) - 8d4e: 6762 flw fa4,24(sp) - 8d50: 2e2f6363 bltu t5,sp,9036 <_start-0x7fff6fca> - 8d54: 2f2e fld ft10,200(sp) - 8d56: 6e69 lui t3,0x1a - 8d58: 64756c63 bltu a0,t2,93b0 <_start-0x7fff6c50> - 8d5c: 0065 c.nop 25 - 8d5e: 6500 flw fs0,8(a0) - 8d60: 7478 flw fa4,108(s0) - 8d62: 6e65 lui t3,0x19 - 8d64: 6464 flw fs1,76(s0) - 8d66: 7466 flw fs0,120(sp) - 8d68: 3266 fld ft4,120(sp) - 8d6a: 632e flw ft6,200(sp) - 8d6c: 0100 addi s0,sp,128 - 8d6e: 0000 unimp - 8d70: 74666f73 csrrsi t5,0x746,12 - 8d74: 662d lui a2,0xb - 8d76: 2e70 fld fa2,216(a2) - 8d78: 0068 addi a0,sp,12 - 8d7a: 0001 nop - 8d7c: 6400 flw fs0,8(s0) - 8d7e: 6c62756f jal a0,30444 <_start-0x7ffcfbbc> - 8d82: 2e65 jal 913a <_start-0x7fff6ec6> - 8d84: 0068 addi a0,sp,12 - 8d86: 0001 nop - 8d88: 7100 flw fs0,32(a0) - 8d8a: 6175 addi sp,sp,368 - 8d8c: 2e64 fld fs1,216(a2) - 8d8e: 0068 addi a0,sp,12 - 8d90: 0001 nop - 8d92: 6c00 flw fs0,24(s0) - 8d94: 6c676e6f jal t3,7f45a <_start-0x7ff80ba6> - 8d98: 2e676e6f jal t3,7f07e <_start-0x7ff80f82> - 8d9c: 0068 addi a0,sp,12 - 8d9e: 0002 c.slli64 zero - 8da0: 0000 unimp - 8da2: 0105 addi sp,sp,1 - 8da4: 0500 addi s0,sp,640 - 8da6: c402 sw zero,8(sp) - 8da8: 03800143 fmadd.d ft2,ft0,fs8,ft0,rne - 8dac: 0125 addi sp,sp,9 - 8dae: 0305 addi t1,t1,1 - 8db0: 00090103 lb sp,0(s2) - 8db4: 0100 addi s0,sp,128 - 8db6: 00090003 lb zero,0(s2) - 8dba: 0100 addi s0,sp,128 - 8dbc: 0d05 addi s10,s10,1 - 8dbe: 00090003 lb zero,0(s2) - 8dc2: 0100 addi s0,sp,128 - 8dc4: 0305 addi t1,t1,1 - 8dc6: 00090103 lb sp,0(s2) + 8c2e: 0902 c.slli64 s2 + 8c30: 0000 unimp + 8c32: 0501 addi a0,a0,0 + 8c34: 0001 nop + 8c36: 019b0403 lb s0,25(s6) + 8c3a: 0306 slli t1,t1,0x1 + 8c3c: 0901 addi s2,s2,0 + 8c3e: 0000 unimp + 8c40: 0501 addi a0,a0,0 + 8c42: 000a c.slli zero,0x2 + 8c44: 019b0403 lb s0,25(s6) + 8c48: 04097f03 0x4097f03 + 8c4c: 0100 addi s0,sp,128 + 8c4e: 0105 addi sp,sp,1 + 8c50: 0300 addi s0,sp,384 + 8c52: 9b04 0x9b04 + 8c54: 0301 addi t1,t1,0 + 8c56: 0901 addi s2,s2,0 + 8c58: 0008 0x8 + 8c5a: 0501 addi a0,a0,0 + 8c5c: 000a c.slli zero,0x2 + 8c5e: 019b0403 lb s0,25(s6) + 8c62: 04097f03 0x4097f03 + 8c66: 0100 addi s0,sp,128 + 8c68: 0105 addi sp,sp,1 + 8c6a: 0300 addi s0,sp,384 + 8c6c: 9b04 0x9b04 + 8c6e: 0301 addi t1,t1,0 + 8c70: 0901 addi s2,s2,0 + 8c72: 0014 0x14 + 8c74: 0501 addi a0,a0,0 + 8c76: 097c0303 lb t1,151(s8) + 8c7a: 000c 0xc + 8c7c: 0001 nop + 8c7e: 0402 c.slli64 s0 + 8c80: 0602 c.slli64 a2 + 8c82: 08090003 lb zero,128(s2) + 8c86: 0100 addi s0,sp,128 + 8c88: 0200 addi s0,sp,256 + 8c8a: 0204 addi s1,sp,256 + 8c8c: 00090003 lb zero,0(s2) + 8c90: 0100 addi s0,sp,128 + 8c92: 0200 addi s0,sp,256 + 8c94: 0204 addi s1,sp,256 + 8c96: 00090003 lb zero,0(s2) + 8c9a: 0100 addi s0,sp,128 + 8c9c: 1809 addi a6,a6,-30 + 8c9e: 0000 unimp + 8ca0: 0101 addi sp,sp,0 + 8ca2: 05e6 slli a1,a1,0x19 + 8ca4: 0000 unimp + 8ca6: 00a20003 lb zero,10(tp) # 1a00a <_start-0x7ffe5ff6> + 8caa: 0000 unimp + 8cac: 0101 addi sp,sp,0 + 8cae: 000d0efb 0xd0efb + 8cb2: 0101 addi sp,sp,0 + 8cb4: 0101 addi sp,sp,0 + 8cb6: 0000 unimp + 8cb8: 0100 addi s0,sp,128 + 8cba: 0000 unimp + 8cbc: 2e01 jal 8fcc <_start-0x7fff7034> + 8cbe: 2f2e fld ft10,200(sp) + 8cc0: 2e2e fld ft8,200(sp) + 8cc2: 2f2e2e2f 0x2f2e2e2f + 8cc6: 2e2e fld ft8,200(sp) + 8cc8: 7369722f 0x7369722f + 8ccc: 672d7663 bgeu s10,s2,9338 <_start-0x7fff6cc8> + 8cd0: 6c2f6363 bltu t5,sp,9396 <_start-0x7fff6c6a> + 8cd4: 6269 lui tp,0x1a + 8cd6: 2f636367 0x2f636367 + 8cda: 74666f73 csrrsi t5,0x746,12 + 8cde: 662d lui a2,0xb + 8ce0: 0070 addi a2,sp,12 + 8ce2: 2e2e fld ft8,200(sp) + 8ce4: 2f2e2e2f 0x2f2e2e2f + 8ce8: 2e2e fld ft8,200(sp) + 8cea: 2f2e2e2f 0x2f2e2e2f + 8cee: 6972 flw fs2,28(sp) + 8cf0: 2d766373 csrrsi t1,0x2d7,12 + 8cf4: 2f636367 0x2f636367 + 8cf8: 696c flw fa1,84(a0) + 8cfa: 6762 flw fa4,24(sp) + 8cfc: 2e2f6363 bltu t5,sp,8fe2 <_start-0x7fff701e> + 8d00: 2f2e fld ft10,200(sp) + 8d02: 6e69 lui t3,0x1a + 8d04: 64756c63 bltu a0,t2,935c <_start-0x7fff6ca4> + 8d08: 0065 c.nop 25 + 8d0a: 6500 flw fs0,8(a0) + 8d0c: 7478 flw fa4,108(s0) + 8d0e: 6e65 lui t3,0x19 + 8d10: 6464 flw fs1,76(s0) + 8d12: 7466 flw fs0,120(sp) + 8d14: 3266 fld ft4,120(sp) + 8d16: 632e flw ft6,200(sp) + 8d18: 0100 addi s0,sp,128 + 8d1a: 0000 unimp + 8d1c: 74666f73 csrrsi t5,0x746,12 + 8d20: 662d lui a2,0xb + 8d22: 2e70 fld fa2,216(a2) + 8d24: 0068 addi a0,sp,12 + 8d26: 0001 nop + 8d28: 6400 flw fs0,8(s0) + 8d2a: 6c62756f jal a0,303f0 <_start-0x7ffcfc10> + 8d2e: 2e65 jal 90e6 <_start-0x7fff6f1a> + 8d30: 0068 addi a0,sp,12 + 8d32: 0001 nop + 8d34: 7100 flw fs0,32(a0) + 8d36: 6175 addi sp,sp,368 + 8d38: 2e64 fld fs1,216(a2) + 8d3a: 0068 addi a0,sp,12 + 8d3c: 0001 nop + 8d3e: 6c00 flw fs0,24(s0) + 8d40: 6c676e6f jal t3,7f406 <_start-0x7ff80bfa> + 8d44: 2e676e6f jal t3,7f02a <_start-0x7ff80fd6> + 8d48: 0068 addi a0,sp,12 + 8d4a: 0002 c.slli64 zero + 8d4c: 0000 unimp + 8d4e: 0105 addi sp,sp,1 + 8d50: 0500 addi s0,sp,640 + 8d52: 8802 jr a6 + 8d54: 0144 addi s1,sp,132 + 8d56: 0380 addi s0,sp,448 + 8d58: 0125 addi sp,sp,9 + 8d5a: 0305 addi t1,t1,1 + 8d5c: 00090103 lb sp,0(s2) + 8d60: 0100 addi s0,sp,128 + 8d62: 00090003 lb zero,0(s2) + 8d66: 0100 addi s0,sp,128 + 8d68: 0d05 addi s10,s10,1 + 8d6a: 00090003 lb zero,0(s2) + 8d6e: 0100 addi s0,sp,128 + 8d70: 0305 addi t1,t1,1 + 8d72: 00090103 lb sp,0(s2) + 8d76: 0100 addi s0,sp,128 + 8d78: 00090003 lb zero,0(s2) + 8d7c: 0100 addi s0,sp,128 + 8d7e: 00090003 lb zero,0(s2) + 8d82: 0100 addi s0,sp,128 + 8d84: 00090003 lb zero,0(s2) + 8d88: 0100 addi s0,sp,128 + 8d8a: 00090103 lb sp,0(s2) + 8d8e: 0100 addi s0,sp,128 + 8d90: 00090003 lb zero,0(s2) + 8d94: 0100 addi s0,sp,128 + 8d96: 00090003 lb zero,0(s2) + 8d9a: 0100 addi s0,sp,128 + 8d9c: 00090003 lb zero,0(s2) + 8da0: 0100 addi s0,sp,128 + 8da2: 00090103 lb sp,0(s2) + 8da6: 0100 addi s0,sp,128 + 8da8: 00090203 lb tp,0(s2) + 8dac: 0100 addi s0,sp,128 + 8dae: 00090103 lb sp,0(s2) + 8db2: 0100 addi s0,sp,128 + 8db4: 00090003 lb zero,0(s2) + 8db8: 0100 addi s0,sp,128 + 8dba: 00090003 lb zero,0(s2) + 8dbe: 0100 addi s0,sp,128 + 8dc0: 00090003 lb zero,0(s2) + 8dc4: 0100 addi s0,sp,128 + 8dc6: 00090003 lb zero,0(s2) 8dca: 0100 addi s0,sp,128 - 8dcc: 00090003 lb zero,0(s2) - 8dd0: 0100 addi s0,sp,128 - 8dd2: 00090003 lb zero,0(s2) - 8dd6: 0100 addi s0,sp,128 - 8dd8: 00090003 lb zero,0(s2) - 8ddc: 0100 addi s0,sp,128 - 8dde: 00090103 lb sp,0(s2) + 8dcc: 0105 addi sp,sp,1 + 8dce: 0306 slli t1,t1,0x1 + 8dd0: 0979 addi s2,s2,30 + 8dd2: 000c 0xc + 8dd4: 0501 addi a0,a0,0 + 8dd6: 09070303 lb t1,144(a4) + 8dda: 0004 0x4 + 8ddc: 0601 addi a2,a2,0 + 8dde: 04090003 lb zero,64(s2) 8de2: 0100 addi s0,sp,128 8de4: 00090003 lb zero,0(s2) 8de8: 0100 addi s0,sp,128 - 8dea: 00090003 lb zero,0(s2) - 8dee: 0100 addi s0,sp,128 - 8df0: 00090003 lb zero,0(s2) - 8df4: 0100 addi s0,sp,128 - 8df6: 00090103 lb sp,0(s2) - 8dfa: 0100 addi s0,sp,128 - 8dfc: 00090203 lb tp,0(s2) - 8e00: 0100 addi s0,sp,128 - 8e02: 00090103 lb sp,0(s2) - 8e06: 0100 addi s0,sp,128 - 8e08: 00090003 lb zero,0(s2) - 8e0c: 0100 addi s0,sp,128 - 8e0e: 00090003 lb zero,0(s2) - 8e12: 0100 addi s0,sp,128 - 8e14: 00090003 lb zero,0(s2) - 8e18: 0100 addi s0,sp,128 - 8e1a: 00090003 lb zero,0(s2) - 8e1e: 0100 addi s0,sp,128 - 8e20: 0105 addi sp,sp,1 - 8e22: 0306 slli t1,t1,0x1 - 8e24: 0979 addi s2,s2,30 - 8e26: 000c 0xc - 8e28: 0501 addi a0,a0,0 - 8e2a: 09070303 lb t1,144(a4) - 8e2e: 0004 0x4 - 8e30: 0601 addi a2,a2,0 - 8e32: 04090003 lb zero,64(s2) - 8e36: 0100 addi s0,sp,128 - 8e38: 00090003 lb zero,0(s2) - 8e3c: 0100 addi s0,sp,128 - 8e3e: 0306 slli t1,t1,0x1 - 8e40: 0902 c.slli64 s2 - 8e42: 0000 unimp - 8e44: 0501 addi a0,a0,0 - 8e46: 0301 addi t1,t1,0 - 8e48: 00040977 0x40977 - 8e4c: 0501 addi a0,a0,0 - 8e4e: 09090303 lb t1,144(s2) - 8e52: 0010 0x10 - 8e54: 0501 addi a0,a0,0 - 8e56: 0301 addi t1,t1,0 - 8e58: 00140977 0x140977 - 8e5c: 0501 addi a0,a0,0 - 8e5e: 09070303 lb t1,144(a4) - 8e62: 0008 0x8 - 8e64: 0601 addi a2,a2,0 - 8e66: 04090003 lb zero,64(s2) - 8e6a: 0100 addi s0,sp,128 - 8e6c: 00090203 lb tp,0(s2) - 8e70: 0100 addi s0,sp,128 + 8dea: 0306 slli t1,t1,0x1 + 8dec: 0902 c.slli64 s2 + 8dee: 0000 unimp + 8df0: 0501 addi a0,a0,0 + 8df2: 0301 addi t1,t1,0 + 8df4: 00040977 0x40977 + 8df8: 0501 addi a0,a0,0 + 8dfa: 09090303 lb t1,144(s2) + 8dfe: 0010 0x10 + 8e00: 0501 addi a0,a0,0 + 8e02: 0301 addi t1,t1,0 + 8e04: 00140977 0x140977 + 8e08: 0501 addi a0,a0,0 + 8e0a: 09070303 lb t1,144(a4) + 8e0e: 0008 0x8 + 8e10: 0601 addi a2,a2,0 + 8e12: 04090003 lb zero,64(s2) + 8e16: 0100 addi s0,sp,128 + 8e18: 00090203 lb tp,0(s2) + 8e1c: 0100 addi s0,sp,128 + 8e1e: 00090003 lb zero,0(s2) + 8e22: 0100 addi s0,sp,128 + 8e24: 00090003 lb zero,0(s2) + 8e28: 0100 addi s0,sp,128 + 8e2a: 00090003 lb zero,0(s2) + 8e2e: 0100 addi s0,sp,128 + 8e30: 00090003 lb zero,0(s2) + 8e34: 0100 addi s0,sp,128 + 8e36: 00090003 lb zero,0(s2) + 8e3a: 0100 addi s0,sp,128 + 8e3c: 00090003 lb zero,0(s2) + 8e40: 0100 addi s0,sp,128 + 8e42: 00090003 lb zero,0(s2) + 8e46: 0100 addi s0,sp,128 + 8e48: 00090003 lb zero,0(s2) + 8e4c: 0100 addi s0,sp,128 + 8e4e: 00090003 lb zero,0(s2) + 8e52: 0100 addi s0,sp,128 + 8e54: 00090003 lb zero,0(s2) + 8e58: 0100 addi s0,sp,128 + 8e5a: 0200 addi s0,sp,256 + 8e5c: 0104 addi s1,sp,128 + 8e5e: 04090003 lb zero,64(s2) + 8e62: 0100 addi s0,sp,128 + 8e64: 0200 addi s0,sp,256 + 8e66: 0104 addi s1,sp,128 + 8e68: 0c090003 lb zero,192(s2) + 8e6c: 0100 addi s0,sp,128 + 8e6e: 0200 addi s0,sp,256 + 8e70: 0104 addi s1,sp,128 8e72: 00090003 lb zero,0(s2) 8e76: 0100 addi s0,sp,128 - 8e78: 00090003 lb zero,0(s2) - 8e7c: 0100 addi s0,sp,128 - 8e7e: 00090003 lb zero,0(s2) - 8e82: 0100 addi s0,sp,128 - 8e84: 00090003 lb zero,0(s2) - 8e88: 0100 addi s0,sp,128 - 8e8a: 00090003 lb zero,0(s2) - 8e8e: 0100 addi s0,sp,128 + 8e78: 0200 addi s0,sp,256 + 8e7a: 0104 addi s1,sp,128 + 8e7c: 00090003 lb zero,0(s2) + 8e80: 0100 addi s0,sp,128 + 8e82: 0200 addi s0,sp,256 + 8e84: 0104 addi s1,sp,128 + 8e86: 00090003 lb zero,0(s2) + 8e8a: 0100 addi s0,sp,128 + 8e8c: 0200 addi s0,sp,256 + 8e8e: 0104 addi s1,sp,128 8e90: 00090003 lb zero,0(s2) 8e94: 0100 addi s0,sp,128 - 8e96: 00090003 lb zero,0(s2) - 8e9a: 0100 addi s0,sp,128 - 8e9c: 00090003 lb zero,0(s2) - 8ea0: 0100 addi s0,sp,128 - 8ea2: 00090003 lb zero,0(s2) - 8ea6: 0100 addi s0,sp,128 - 8ea8: 00090003 lb zero,0(s2) - 8eac: 0100 addi s0,sp,128 - 8eae: 0200 addi s0,sp,256 - 8eb0: 0104 addi s1,sp,128 - 8eb2: 04090003 lb zero,64(s2) - 8eb6: 0100 addi s0,sp,128 - 8eb8: 0200 addi s0,sp,256 - 8eba: 0104 addi s1,sp,128 - 8ebc: 0c090003 lb zero,192(s2) - 8ec0: 0100 addi s0,sp,128 - 8ec2: 0200 addi s0,sp,256 - 8ec4: 0104 addi s1,sp,128 - 8ec6: 00090003 lb zero,0(s2) - 8eca: 0100 addi s0,sp,128 - 8ecc: 0200 addi s0,sp,256 - 8ece: 0104 addi s1,sp,128 - 8ed0: 00090003 lb zero,0(s2) - 8ed4: 0100 addi s0,sp,128 - 8ed6: 0200 addi s0,sp,256 - 8ed8: 0104 addi s1,sp,128 - 8eda: 00090003 lb zero,0(s2) - 8ede: 0100 addi s0,sp,128 - 8ee0: 0200 addi s0,sp,256 - 8ee2: 0104 addi s1,sp,128 - 8ee4: 00090003 lb zero,0(s2) - 8ee8: 0100 addi s0,sp,128 - 8eea: 0200 addi s0,sp,256 - 8eec: 0104 addi s1,sp,128 - 8eee: 00090003 lb zero,0(s2) - 8ef2: 0100 addi s0,sp,128 - 8ef4: 0200 addi s0,sp,256 - 8ef6: 0104 addi s1,sp,128 - 8ef8: 00090003 lb zero,0(s2) - 8efc: 0100 addi s0,sp,128 - 8efe: 0200 addi s0,sp,256 - 8f00: 0104 addi s1,sp,128 - 8f02: 00090003 lb zero,0(s2) - 8f06: 0100 addi s0,sp,128 - 8f08: 0200 addi s0,sp,256 - 8f0a: 0104 addi s1,sp,128 - 8f0c: 00090003 lb zero,0(s2) - 8f10: 0100 addi s0,sp,128 - 8f12: 0200 addi s0,sp,256 - 8f14: 0104 addi s1,sp,128 - 8f16: 00090003 lb zero,0(s2) - 8f1a: 0100 addi s0,sp,128 - 8f1c: 0200 addi s0,sp,256 - 8f1e: 0104 addi s1,sp,128 - 8f20: 18090003 lb zero,384(s2) - 8f24: 0100 addi s0,sp,128 - 8f26: 0200 addi s0,sp,256 - 8f28: 0104 addi s1,sp,128 - 8f2a: 00090003 lb zero,0(s2) - 8f2e: 0100 addi s0,sp,128 - 8f30: 0200 addi s0,sp,256 - 8f32: 0104 addi s1,sp,128 - 8f34: 00090003 lb zero,0(s2) - 8f38: 0100 addi s0,sp,128 - 8f3a: 0200 addi s0,sp,256 - 8f3c: 0104 addi s1,sp,128 - 8f3e: 04090003 lb zero,64(s2) - 8f42: 0100 addi s0,sp,128 - 8f44: 0200 addi s0,sp,256 - 8f46: 0104 addi s1,sp,128 - 8f48: 00090003 lb zero,0(s2) - 8f4c: 0100 addi s0,sp,128 - 8f4e: 0200 addi s0,sp,256 - 8f50: 0104 addi s1,sp,128 - 8f52: 00090003 lb zero,0(s2) - 8f56: 0100 addi s0,sp,128 - 8f58: 0200 addi s0,sp,256 - 8f5a: 0104 addi s1,sp,128 - 8f5c: 04090003 lb zero,64(s2) - 8f60: 0100 addi s0,sp,128 - 8f62: 0200 addi s0,sp,256 - 8f64: 0104 addi s1,sp,128 - 8f66: 00090003 lb zero,0(s2) - 8f6a: 0100 addi s0,sp,128 - 8f6c: 0200 addi s0,sp,256 - 8f6e: 0104 addi s1,sp,128 - 8f70: 04090003 lb zero,64(s2) - 8f74: 0100 addi s0,sp,128 - 8f76: 0200 addi s0,sp,256 - 8f78: 0104 addi s1,sp,128 - 8f7a: 00090003 lb zero,0(s2) - 8f7e: 0100 addi s0,sp,128 - 8f80: 0200 addi s0,sp,256 - 8f82: 5c04 lw s1,56(s0) - 8f84: 00090003 lb zero,0(s2) - 8f88: 0100 addi s0,sp,128 - 8f8a: 0200 addi s0,sp,256 - 8f8c: 5c04 lw s1,56(s0) - 8f8e: 00090003 lb zero,0(s2) - 8f92: 0100 addi s0,sp,128 - 8f94: 0200 addi s0,sp,256 - 8f96: 5c04 lw s1,56(s0) - 8f98: 00090403 lb s0,0(s2) - 8f9c: 0100 addi s0,sp,128 - 8f9e: 0200 addi s0,sp,256 - 8fa0: 5c04 lw s1,56(s0) - 8fa2: 00090003 lb zero,0(s2) - 8fa6: 0100 addi s0,sp,128 - 8fa8: 0200 addi s0,sp,256 - 8faa: 5c04 lw s1,56(s0) - 8fac: 00090003 lb zero,0(s2) - 8fb0: 0100 addi s0,sp,128 - 8fb2: 0200 addi s0,sp,256 - 8fb4: 5c04 lw s1,56(s0) - 8fb6: 00090003 lb zero,0(s2) - 8fba: 0100 addi s0,sp,128 - 8fbc: 0200 addi s0,sp,256 - 8fbe: 5c04 lw s1,56(s0) - 8fc0: 00090003 lb zero,0(s2) - 8fc4: 0100 addi s0,sp,128 - 8fc6: 0200 addi s0,sp,256 - 8fc8: 5c04 lw s1,56(s0) - 8fca: 00090003 lb zero,0(s2) - 8fce: 0100 addi s0,sp,128 - 8fd0: 0a05 addi s4,s4,1 - 8fd2: 0200 addi s0,sp,256 - 8fd4: 5c04 lw s1,56(s0) - 8fd6: 0306 slli t1,t1,0x1 - 8fd8: 000c0903 lb s2,0(s8) - 8fdc: 0501 addi a0,a0,0 - 8fde: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> - 8fe2: 035c addi a5,sp,388 - 8fe4: 097d addi s2,s2,31 - 8fe6: 0004 0x4 - 8fe8: 0501 addi a0,a0,0 - 8fea: 0001 nop - 8fec: 0402 c.slli64 s0 - 8fee: 035c addi a5,sp,388 - 8ff0: 0904 addi s1,sp,144 - 8ff2: 0004 0x4 - 8ff4: 0501 addi a0,a0,0 - 8ff6: 000a c.slli zero,0x2 - 8ff8: 0402 c.slli64 s0 - 8ffa: 035c addi a5,sp,388 - 8ffc: 097f 0x97f - 8ffe: 0004 0x4 - 9000: 0501 addi a0,a0,0 - 9002: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> - 9006: 035c addi a5,sp,388 - 9008: 097d addi s2,s2,31 - 900a: 0008 0x8 - 900c: 0001 nop - 900e: 0402 c.slli64 s0 - 9010: 065c addi a5,sp,772 - 9012: 04090003 lb zero,64(s2) - 9016: 0100 addi s0,sp,128 - 9018: 0200 addi s0,sp,256 - 901a: 5c04 lw s1,56(s0) - 901c: 00090003 lb zero,0(s2) - 9020: 0100 addi s0,sp,128 - 9022: 0200 addi s0,sp,256 - 9024: 5c04 lw s1,56(s0) - 9026: 00090003 lb zero,0(s2) - 902a: 0100 addi s0,sp,128 - 902c: 0200 addi s0,sp,256 - 902e: 5c04 lw s1,56(s0) - 9030: 00090003 lb zero,0(s2) - 9034: 0100 addi s0,sp,128 - 9036: 0200 addi s0,sp,256 - 9038: 5c04 lw s1,56(s0) - 903a: 00090103 lb sp,0(s2) - 903e: 0100 addi s0,sp,128 - 9040: 0200 addi s0,sp,256 - 9042: 5c04 lw s1,56(s0) - 9044: 00090003 lb zero,0(s2) - 9048: 0100 addi s0,sp,128 - 904a: 0200 addi s0,sp,256 - 904c: 5c04 lw s1,56(s0) - 904e: 00090003 lb zero,0(s2) + 8e96: 0200 addi s0,sp,256 + 8e98: 0104 addi s1,sp,128 + 8e9a: 00090003 lb zero,0(s2) + 8e9e: 0100 addi s0,sp,128 + 8ea0: 0200 addi s0,sp,256 + 8ea2: 0104 addi s1,sp,128 + 8ea4: 00090003 lb zero,0(s2) + 8ea8: 0100 addi s0,sp,128 + 8eaa: 0200 addi s0,sp,256 + 8eac: 0104 addi s1,sp,128 + 8eae: 00090003 lb zero,0(s2) + 8eb2: 0100 addi s0,sp,128 + 8eb4: 0200 addi s0,sp,256 + 8eb6: 0104 addi s1,sp,128 + 8eb8: 00090003 lb zero,0(s2) + 8ebc: 0100 addi s0,sp,128 + 8ebe: 0200 addi s0,sp,256 + 8ec0: 0104 addi s1,sp,128 + 8ec2: 00090003 lb zero,0(s2) + 8ec6: 0100 addi s0,sp,128 + 8ec8: 0200 addi s0,sp,256 + 8eca: 0104 addi s1,sp,128 + 8ecc: 18090003 lb zero,384(s2) + 8ed0: 0100 addi s0,sp,128 + 8ed2: 0200 addi s0,sp,256 + 8ed4: 0104 addi s1,sp,128 + 8ed6: 00090003 lb zero,0(s2) + 8eda: 0100 addi s0,sp,128 + 8edc: 0200 addi s0,sp,256 + 8ede: 0104 addi s1,sp,128 + 8ee0: 00090003 lb zero,0(s2) + 8ee4: 0100 addi s0,sp,128 + 8ee6: 0200 addi s0,sp,256 + 8ee8: 0104 addi s1,sp,128 + 8eea: 04090003 lb zero,64(s2) + 8eee: 0100 addi s0,sp,128 + 8ef0: 0200 addi s0,sp,256 + 8ef2: 0104 addi s1,sp,128 + 8ef4: 00090003 lb zero,0(s2) + 8ef8: 0100 addi s0,sp,128 + 8efa: 0200 addi s0,sp,256 + 8efc: 0104 addi s1,sp,128 + 8efe: 00090003 lb zero,0(s2) + 8f02: 0100 addi s0,sp,128 + 8f04: 0200 addi s0,sp,256 + 8f06: 0104 addi s1,sp,128 + 8f08: 04090003 lb zero,64(s2) + 8f0c: 0100 addi s0,sp,128 + 8f0e: 0200 addi s0,sp,256 + 8f10: 0104 addi s1,sp,128 + 8f12: 00090003 lb zero,0(s2) + 8f16: 0100 addi s0,sp,128 + 8f18: 0200 addi s0,sp,256 + 8f1a: 0104 addi s1,sp,128 + 8f1c: 04090003 lb zero,64(s2) + 8f20: 0100 addi s0,sp,128 + 8f22: 0200 addi s0,sp,256 + 8f24: 0104 addi s1,sp,128 + 8f26: 00090003 lb zero,0(s2) + 8f2a: 0100 addi s0,sp,128 + 8f2c: 0200 addi s0,sp,256 + 8f2e: 5c04 lw s1,56(s0) + 8f30: 00090003 lb zero,0(s2) + 8f34: 0100 addi s0,sp,128 + 8f36: 0200 addi s0,sp,256 + 8f38: 5c04 lw s1,56(s0) + 8f3a: 00090003 lb zero,0(s2) + 8f3e: 0100 addi s0,sp,128 + 8f40: 0200 addi s0,sp,256 + 8f42: 5c04 lw s1,56(s0) + 8f44: 00090403 lb s0,0(s2) + 8f48: 0100 addi s0,sp,128 + 8f4a: 0200 addi s0,sp,256 + 8f4c: 5c04 lw s1,56(s0) + 8f4e: 00090003 lb zero,0(s2) + 8f52: 0100 addi s0,sp,128 + 8f54: 0200 addi s0,sp,256 + 8f56: 5c04 lw s1,56(s0) + 8f58: 00090003 lb zero,0(s2) + 8f5c: 0100 addi s0,sp,128 + 8f5e: 0200 addi s0,sp,256 + 8f60: 5c04 lw s1,56(s0) + 8f62: 00090003 lb zero,0(s2) + 8f66: 0100 addi s0,sp,128 + 8f68: 0200 addi s0,sp,256 + 8f6a: 5c04 lw s1,56(s0) + 8f6c: 00090003 lb zero,0(s2) + 8f70: 0100 addi s0,sp,128 + 8f72: 0200 addi s0,sp,256 + 8f74: 5c04 lw s1,56(s0) + 8f76: 00090003 lb zero,0(s2) + 8f7a: 0100 addi s0,sp,128 + 8f7c: 0a05 addi s4,s4,1 + 8f7e: 0200 addi s0,sp,256 + 8f80: 5c04 lw s1,56(s0) + 8f82: 0306 slli t1,t1,0x1 + 8f84: 000c0903 lb s2,0(s8) + 8f88: 0501 addi a0,a0,0 + 8f8a: 04020003 lb zero,64(tp) # 1a040 <_start-0x7ffe5fc0> + 8f8e: 035c addi a5,sp,388 + 8f90: 097d addi s2,s2,31 + 8f92: 0004 0x4 + 8f94: 0501 addi a0,a0,0 + 8f96: 0001 nop + 8f98: 0402 c.slli64 s0 + 8f9a: 035c addi a5,sp,388 + 8f9c: 0904 addi s1,sp,144 + 8f9e: 0004 0x4 + 8fa0: 0501 addi a0,a0,0 + 8fa2: 000a c.slli zero,0x2 + 8fa4: 0402 c.slli64 s0 + 8fa6: 035c addi a5,sp,388 + 8fa8: 097f 0x97f + 8faa: 0004 0x4 + 8fac: 0501 addi a0,a0,0 + 8fae: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> + 8fb2: 035c addi a5,sp,388 + 8fb4: 097d addi s2,s2,31 + 8fb6: 0008 0x8 + 8fb8: 0001 nop + 8fba: 0402 c.slli64 s0 + 8fbc: 065c addi a5,sp,772 + 8fbe: 04090003 lb zero,64(s2) + 8fc2: 0100 addi s0,sp,128 + 8fc4: 0200 addi s0,sp,256 + 8fc6: 5c04 lw s1,56(s0) + 8fc8: 00090003 lb zero,0(s2) + 8fcc: 0100 addi s0,sp,128 + 8fce: 0200 addi s0,sp,256 + 8fd0: 5c04 lw s1,56(s0) + 8fd2: 00090003 lb zero,0(s2) + 8fd6: 0100 addi s0,sp,128 + 8fd8: 0200 addi s0,sp,256 + 8fda: 5c04 lw s1,56(s0) + 8fdc: 00090003 lb zero,0(s2) + 8fe0: 0100 addi s0,sp,128 + 8fe2: 0200 addi s0,sp,256 + 8fe4: 5c04 lw s1,56(s0) + 8fe6: 00090103 lb sp,0(s2) + 8fea: 0100 addi s0,sp,128 + 8fec: 0200 addi s0,sp,256 + 8fee: 5c04 lw s1,56(s0) + 8ff0: 00090003 lb zero,0(s2) + 8ff4: 0100 addi s0,sp,128 + 8ff6: 0200 addi s0,sp,256 + 8ff8: 5c04 lw s1,56(s0) + 8ffa: 00090003 lb zero,0(s2) + 8ffe: 0100 addi s0,sp,128 + 9000: 0200 addi s0,sp,256 + 9002: 5c04 lw s1,56(s0) + 9004: 00090203 lb tp,0(s2) + 9008: 0100 addi s0,sp,128 + 900a: 0105 addi sp,sp,1 + 900c: 0200 addi s0,sp,256 + 900e: 5c04 lw s1,56(s0) + 9010: 0306 slli t1,t1,0x1 + 9012: 0901 addi s2,s2,0 + 9014: 0000 unimp + 9016: 0501 addi a0,a0,0 + 9018: 000a c.slli zero,0x2 + 901a: 0402 c.slli64 s0 + 901c: 035c addi a5,sp,388 + 901e: 097f 0x97f + 9020: 0004 0x4 + 9022: 0501 addi a0,a0,0 + 9024: 0001 nop + 9026: 0402 c.slli64 s0 + 9028: 035c addi a5,sp,388 + 902a: 0901 addi s2,s2,0 + 902c: 0008 0x8 + 902e: 0501 addi a0,a0,0 + 9030: 000a c.slli zero,0x2 + 9032: 0402 c.slli64 s0 + 9034: 035c addi a5,sp,388 + 9036: 097f 0x97f + 9038: 0008 0x8 + 903a: 0501 addi a0,a0,0 + 903c: 0001 nop + 903e: 0402 c.slli64 s0 + 9040: 035c addi a5,sp,388 + 9042: 0901 addi s2,s2,0 + 9044: 000c 0xc + 9046: 0501 addi a0,a0,0 + 9048: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> + 904c: 0602 c.slli64 a2 + 904e: 0c097803 0xc097803 9052: 0100 addi s0,sp,128 9054: 0200 addi s0,sp,256 - 9056: 5c04 lw s1,56(s0) - 9058: 00090203 lb tp,0(s2) + 9056: 1404 addi s1,sp,544 + 9058: 08090003 lb zero,128(s2) 905c: 0100 addi s0,sp,128 - 905e: 0105 addi sp,sp,1 - 9060: 0200 addi s0,sp,256 - 9062: 5c04 lw s1,56(s0) - 9064: 0306 slli t1,t1,0x1 - 9066: 0901 addi s2,s2,0 - 9068: 0000 unimp - 906a: 0501 addi a0,a0,0 - 906c: 000a c.slli zero,0x2 - 906e: 0402 c.slli64 s0 - 9070: 035c addi a5,sp,388 - 9072: 097f 0x97f - 9074: 0004 0x4 - 9076: 0501 addi a0,a0,0 - 9078: 0001 nop - 907a: 0402 c.slli64 s0 - 907c: 035c addi a5,sp,388 - 907e: 0901 addi s2,s2,0 - 9080: 0008 0x8 - 9082: 0501 addi a0,a0,0 - 9084: 000a c.slli zero,0x2 - 9086: 0402 c.slli64 s0 - 9088: 035c addi a5,sp,388 - 908a: 097f 0x97f - 908c: 0008 0x8 - 908e: 0501 addi a0,a0,0 - 9090: 0001 nop - 9092: 0402 c.slli64 s0 - 9094: 035c addi a5,sp,388 - 9096: 0901 addi s2,s2,0 - 9098: 000c 0xc - 909a: 0501 addi a0,a0,0 - 909c: 04020003 lb zero,64(tp) # 40 <_start-0x7fffffc0> - 90a0: 0602 c.slli64 a2 - 90a2: 0c097803 0xc097803 - 90a6: 0100 addi s0,sp,128 - 90a8: 0200 addi s0,sp,256 - 90aa: 1404 addi s1,sp,544 - 90ac: 08090003 lb zero,128(s2) - 90b0: 0100 addi s0,sp,128 - 90b2: 0200 addi s0,sp,256 - 90b4: 1404 addi s1,sp,544 - 90b6: 00090003 lb zero,0(s2) - 90ba: 0100 addi s0,sp,128 - 90bc: 0200 addi s0,sp,256 - 90be: 1404 addi s1,sp,544 - 90c0: 00090003 lb zero,0(s2) - 90c4: 0100 addi s0,sp,128 - 90c6: 0200 addi s0,sp,256 - 90c8: 1404 addi s1,sp,544 - 90ca: 00090003 lb zero,0(s2) - 90ce: 0100 addi s0,sp,128 - 90d0: 0200 addi s0,sp,256 - 90d2: 1804 addi s1,sp,48 - 90d4: 04090003 lb zero,64(s2) - 90d8: 0100 addi s0,sp,128 - 90da: 0200 addi s0,sp,256 - 90dc: 1804 addi s1,sp,48 - 90de: 00090003 lb zero,0(s2) - 90e2: 0100 addi s0,sp,128 - 90e4: 0200 addi s0,sp,256 - 90e6: 1804 addi s1,sp,48 - 90e8: 00090003 lb zero,0(s2) - 90ec: 0100 addi s0,sp,128 - 90ee: 0200 addi s0,sp,256 - 90f0: 1804 addi s1,sp,48 - 90f2: 00090003 lb zero,0(s2) - 90f6: 0100 addi s0,sp,128 - 90f8: 0200 addi s0,sp,256 - 90fa: 1804 addi s1,sp,48 - 90fc: 00090003 lb zero,0(s2) - 9100: 0100 addi s0,sp,128 - 9102: 0200 addi s0,sp,256 - 9104: 2904 fld fs1,16(a0) - 9106: 04090003 lb zero,64(s2) - 910a: 0100 addi s0,sp,128 - 910c: 0200 addi s0,sp,256 - 910e: 2904 fld fs1,16(a0) - 9110: 00090003 lb zero,0(s2) - 9114: 0100 addi s0,sp,128 - 9116: 0200 addi s0,sp,256 - 9118: 2904 fld fs1,16(a0) - 911a: 00090003 lb zero,0(s2) - 911e: 0100 addi s0,sp,128 - 9120: 0200 addi s0,sp,256 - 9122: 2904 fld fs1,16(a0) - 9124: 00090003 lb zero,0(s2) - 9128: 0100 addi s0,sp,128 - 912a: 0200 addi s0,sp,256 - 912c: 2904 fld fs1,16(a0) - 912e: 08090003 lb zero,128(s2) - 9132: 0100 addi s0,sp,128 - 9134: 0200 addi s0,sp,256 - 9136: 3704 fld fs1,40(a4) - 9138: 00090003 lb zero,0(s2) - 913c: 0100 addi s0,sp,128 - 913e: 0200 addi s0,sp,256 - 9140: 3704 fld fs1,40(a4) - 9142: 00090003 lb zero,0(s2) - 9146: 0100 addi s0,sp,128 - 9148: 0200 addi s0,sp,256 - 914a: 3704 fld fs1,40(a4) - 914c: 00090003 lb zero,0(s2) - 9150: 0100 addi s0,sp,128 - 9152: 0200 addi s0,sp,256 - 9154: 3704 fld fs1,40(a4) - 9156: 00090003 lb zero,0(s2) - 915a: 0100 addi s0,sp,128 - 915c: 0200 addi s0,sp,256 - 915e: 3704 fld fs1,40(a4) - 9160: 00090003 lb zero,0(s2) - 9164: 0100 addi s0,sp,128 - 9166: 0200 addi s0,sp,256 - 9168: 3704 fld fs1,40(a4) - 916a: 08090003 lb zero,128(s2) - 916e: 0100 addi s0,sp,128 - 9170: 0200 addi s0,sp,256 - 9172: 3704 fld fs1,40(a4) - 9174: 00090003 lb zero,0(s2) - 9178: 0100 addi s0,sp,128 - 917a: 0200 addi s0,sp,256 - 917c: 3704 fld fs1,40(a4) - 917e: 00090003 lb zero,0(s2) - 9182: 0100 addi s0,sp,128 - 9184: 0306 slli t1,t1,0x1 - 9186: 0900 addi s0,sp,144 - 9188: 0014 0x14 - 918a: 0001 nop - 918c: 0402 c.slli64 s0 - 918e: 063d addi a2,a2,15 - 9190: 14090003 lb zero,320(s2) - 9194: 0100 addi s0,sp,128 - 9196: 0200 addi s0,sp,256 - 9198: 4004 lw s1,0(s0) - 919a: 0306 slli t1,t1,0x1 - 919c: 0900 addi s0,sp,144 - 919e: 0004 0x4 - 91a0: 0001 nop - 91a2: 0402 c.slli64 s0 - 91a4: 0640 addi s0,sp,772 - 91a6: 10090003 lb zero,256(s2) - 91aa: 0100 addi s0,sp,128 - 91ac: 0200 addi s0,sp,256 - 91ae: 3004 fld fs1,32(s0) - 91b0: 08090003 lb zero,128(s2) - 91b4: 0100 addi s0,sp,128 - 91b6: 0200 addi s0,sp,256 - 91b8: 3004 fld fs1,32(s0) - 91ba: 00090003 lb zero,0(s2) - 91be: 0100 addi s0,sp,128 - 91c0: 0200 addi s0,sp,256 - 91c2: 3004 fld fs1,32(s0) - 91c4: 00090003 lb zero,0(s2) - 91c8: 0100 addi s0,sp,128 - 91ca: 0200 addi s0,sp,256 - 91cc: 3004 fld fs1,32(s0) - 91ce: 00090003 lb zero,0(s2) - 91d2: 0100 addi s0,sp,128 - 91d4: 0200 addi s0,sp,256 - 91d6: 3004 fld fs1,32(s0) - 91d8: 04090003 lb zero,64(s2) - 91dc: 0100 addi s0,sp,128 - 91de: 0200 addi s0,sp,256 - 91e0: 3004 fld fs1,32(s0) - 91e2: 00090003 lb zero,0(s2) - 91e6: 0100 addi s0,sp,128 - 91e8: 0306 slli t1,t1,0x1 - 91ea: 0900 addi s0,sp,144 - 91ec: 0014 0x14 - 91ee: 0001 nop - 91f0: 0402 c.slli64 s0 - 91f2: 063c addi a5,sp,776 - 91f4: 04090003 lb zero,64(s2) - 91f8: 0100 addi s0,sp,128 - 91fa: 0200 addi s0,sp,256 - 91fc: 3c04 fld fs1,56(s0) - 91fe: 14090003 lb zero,320(s2) - 9202: 0100 addi s0,sp,128 - 9204: 0200 addi s0,sp,256 - 9206: 3c04 fld fs1,56(s0) - 9208: 00090003 lb zero,0(s2) - 920c: 0100 addi s0,sp,128 - 920e: 0200 addi s0,sp,256 - 9210: 4304 lw s1,0(a4) - 9212: 0306 slli t1,t1,0x1 - 9214: 0900 addi s0,sp,144 - 9216: 0008 0x8 - 9218: 0001 nop - 921a: 0402 c.slli64 s0 - 921c: 00030643 fmadd.s fa2,ft6,ft0,ft0,rne - 9220: 0409 addi s0,s0,2 - 9222: 0100 addi s0,sp,128 - 9224: 0200 addi s0,sp,256 - 9226: 4304 lw s1,0(a4) - 9228: 10090003 lb zero,256(s2) - 922c: 0100 addi s0,sp,128 - 922e: 0200 addi s0,sp,256 - 9230: 4304 lw s1,0(a4) - 9232: 04090003 lb zero,64(s2) + 905e: 0200 addi s0,sp,256 + 9060: 1404 addi s1,sp,544 + 9062: 00090003 lb zero,0(s2) + 9066: 0100 addi s0,sp,128 + 9068: 0200 addi s0,sp,256 + 906a: 1404 addi s1,sp,544 + 906c: 00090003 lb zero,0(s2) + 9070: 0100 addi s0,sp,128 + 9072: 0200 addi s0,sp,256 + 9074: 1404 addi s1,sp,544 + 9076: 00090003 lb zero,0(s2) + 907a: 0100 addi s0,sp,128 + 907c: 0200 addi s0,sp,256 + 907e: 1804 addi s1,sp,48 + 9080: 04090003 lb zero,64(s2) + 9084: 0100 addi s0,sp,128 + 9086: 0200 addi s0,sp,256 + 9088: 1804 addi s1,sp,48 + 908a: 00090003 lb zero,0(s2) + 908e: 0100 addi s0,sp,128 + 9090: 0200 addi s0,sp,256 + 9092: 1804 addi s1,sp,48 + 9094: 00090003 lb zero,0(s2) + 9098: 0100 addi s0,sp,128 + 909a: 0200 addi s0,sp,256 + 909c: 1804 addi s1,sp,48 + 909e: 00090003 lb zero,0(s2) + 90a2: 0100 addi s0,sp,128 + 90a4: 0200 addi s0,sp,256 + 90a6: 1804 addi s1,sp,48 + 90a8: 00090003 lb zero,0(s2) + 90ac: 0100 addi s0,sp,128 + 90ae: 0200 addi s0,sp,256 + 90b0: 2904 fld fs1,16(a0) + 90b2: 04090003 lb zero,64(s2) + 90b6: 0100 addi s0,sp,128 + 90b8: 0200 addi s0,sp,256 + 90ba: 2904 fld fs1,16(a0) + 90bc: 00090003 lb zero,0(s2) + 90c0: 0100 addi s0,sp,128 + 90c2: 0200 addi s0,sp,256 + 90c4: 2904 fld fs1,16(a0) + 90c6: 00090003 lb zero,0(s2) + 90ca: 0100 addi s0,sp,128 + 90cc: 0200 addi s0,sp,256 + 90ce: 2904 fld fs1,16(a0) + 90d0: 00090003 lb zero,0(s2) + 90d4: 0100 addi s0,sp,128 + 90d6: 0200 addi s0,sp,256 + 90d8: 2904 fld fs1,16(a0) + 90da: 08090003 lb zero,128(s2) + 90de: 0100 addi s0,sp,128 + 90e0: 0200 addi s0,sp,256 + 90e2: 3704 fld fs1,40(a4) + 90e4: 00090003 lb zero,0(s2) + 90e8: 0100 addi s0,sp,128 + 90ea: 0200 addi s0,sp,256 + 90ec: 3704 fld fs1,40(a4) + 90ee: 00090003 lb zero,0(s2) + 90f2: 0100 addi s0,sp,128 + 90f4: 0200 addi s0,sp,256 + 90f6: 3704 fld fs1,40(a4) + 90f8: 00090003 lb zero,0(s2) + 90fc: 0100 addi s0,sp,128 + 90fe: 0200 addi s0,sp,256 + 9100: 3704 fld fs1,40(a4) + 9102: 00090003 lb zero,0(s2) + 9106: 0100 addi s0,sp,128 + 9108: 0200 addi s0,sp,256 + 910a: 3704 fld fs1,40(a4) + 910c: 00090003 lb zero,0(s2) + 9110: 0100 addi s0,sp,128 + 9112: 0200 addi s0,sp,256 + 9114: 3704 fld fs1,40(a4) + 9116: 08090003 lb zero,128(s2) + 911a: 0100 addi s0,sp,128 + 911c: 0200 addi s0,sp,256 + 911e: 3704 fld fs1,40(a4) + 9120: 00090003 lb zero,0(s2) + 9124: 0100 addi s0,sp,128 + 9126: 0200 addi s0,sp,256 + 9128: 3704 fld fs1,40(a4) + 912a: 00090003 lb zero,0(s2) + 912e: 0100 addi s0,sp,128 + 9130: 0306 slli t1,t1,0x1 + 9132: 0900 addi s0,sp,144 + 9134: 0014 0x14 + 9136: 0001 nop + 9138: 0402 c.slli64 s0 + 913a: 063d addi a2,a2,15 + 913c: 14090003 lb zero,320(s2) + 9140: 0100 addi s0,sp,128 + 9142: 0200 addi s0,sp,256 + 9144: 4004 lw s1,0(s0) + 9146: 0306 slli t1,t1,0x1 + 9148: 0900 addi s0,sp,144 + 914a: 0004 0x4 + 914c: 0001 nop + 914e: 0402 c.slli64 s0 + 9150: 0640 addi s0,sp,772 + 9152: 10090003 lb zero,256(s2) + 9156: 0100 addi s0,sp,128 + 9158: 0200 addi s0,sp,256 + 915a: 3004 fld fs1,32(s0) + 915c: 08090003 lb zero,128(s2) + 9160: 0100 addi s0,sp,128 + 9162: 0200 addi s0,sp,256 + 9164: 3004 fld fs1,32(s0) + 9166: 00090003 lb zero,0(s2) + 916a: 0100 addi s0,sp,128 + 916c: 0200 addi s0,sp,256 + 916e: 3004 fld fs1,32(s0) + 9170: 00090003 lb zero,0(s2) + 9174: 0100 addi s0,sp,128 + 9176: 0200 addi s0,sp,256 + 9178: 3004 fld fs1,32(s0) + 917a: 00090003 lb zero,0(s2) + 917e: 0100 addi s0,sp,128 + 9180: 0200 addi s0,sp,256 + 9182: 3004 fld fs1,32(s0) + 9184: 04090003 lb zero,64(s2) + 9188: 0100 addi s0,sp,128 + 918a: 0200 addi s0,sp,256 + 918c: 3004 fld fs1,32(s0) + 918e: 00090003 lb zero,0(s2) + 9192: 0100 addi s0,sp,128 + 9194: 0306 slli t1,t1,0x1 + 9196: 0900 addi s0,sp,144 + 9198: 0014 0x14 + 919a: 0001 nop + 919c: 0402 c.slli64 s0 + 919e: 063c addi a5,sp,776 + 91a0: 04090003 lb zero,64(s2) + 91a4: 0100 addi s0,sp,128 + 91a6: 0200 addi s0,sp,256 + 91a8: 3c04 fld fs1,56(s0) + 91aa: 14090003 lb zero,320(s2) + 91ae: 0100 addi s0,sp,128 + 91b0: 0200 addi s0,sp,256 + 91b2: 3c04 fld fs1,56(s0) + 91b4: 00090003 lb zero,0(s2) + 91b8: 0100 addi s0,sp,128 + 91ba: 0200 addi s0,sp,256 + 91bc: 4304 lw s1,0(a4) + 91be: 0306 slli t1,t1,0x1 + 91c0: 0900 addi s0,sp,144 + 91c2: 0008 0x8 + 91c4: 0001 nop + 91c6: 0402 c.slli64 s0 + 91c8: 00030643 fmadd.s fa2,ft6,ft0,ft0,rne + 91cc: 0409 addi s0,s0,2 + 91ce: 0100 addi s0,sp,128 + 91d0: 0200 addi s0,sp,256 + 91d2: 4304 lw s1,0(a4) + 91d4: 10090003 lb zero,256(s2) + 91d8: 0100 addi s0,sp,128 + 91da: 0200 addi s0,sp,256 + 91dc: 4304 lw s1,0(a4) + 91de: 04090003 lb zero,64(s2) + 91e2: 0100 addi s0,sp,128 + 91e4: 0200 addi s0,sp,256 + 91e6: 4404 lw s1,8(s0) + 91e8: 04090003 lb zero,64(s2) + 91ec: 0100 addi s0,sp,128 + 91ee: 0200 addi s0,sp,256 + 91f0: 4404 lw s1,8(s0) + 91f2: 00090003 lb zero,0(s2) + 91f6: 0100 addi s0,sp,128 + 91f8: 0200 addi s0,sp,256 + 91fa: 3f04 fld fs1,56(a4) + 91fc: 10090003 lb zero,256(s2) + 9200: 0100 addi s0,sp,128 + 9202: 0200 addi s0,sp,256 + 9204: 3f04 fld fs1,56(a4) + 9206: 1c090003 lb zero,448(s2) + 920a: 0100 addi s0,sp,128 + 920c: 0200 addi s0,sp,256 + 920e: 1104 addi s1,sp,160 + 9210: 08090003 lb zero,128(s2) + 9214: 0100 addi s0,sp,128 + 9216: 0200 addi s0,sp,256 + 9218: 1104 addi s1,sp,160 + 921a: 00090003 lb zero,0(s2) + 921e: 0100 addi s0,sp,128 + 9220: 08090003 lb zero,128(s2) + 9224: 0100 addi s0,sp,128 + 9226: 00090003 lb zero,0(s2) + 922a: 0100 addi s0,sp,128 + 922c: 00090003 lb zero,0(s2) + 9230: 0100 addi s0,sp,128 + 9232: 00090003 lb zero,0(s2) 9236: 0100 addi s0,sp,128 - 9238: 0200 addi s0,sp,256 - 923a: 4404 lw s1,8(s0) - 923c: 04090003 lb zero,64(s2) - 9240: 0100 addi s0,sp,128 - 9242: 0200 addi s0,sp,256 - 9244: 4404 lw s1,8(s0) - 9246: 00090003 lb zero,0(s2) - 924a: 0100 addi s0,sp,128 - 924c: 0200 addi s0,sp,256 - 924e: 3f04 fld fs1,56(a4) - 9250: 10090003 lb zero,256(s2) + 9238: 00090003 lb zero,0(s2) + 923c: 0100 addi s0,sp,128 + 923e: 10090003 lb zero,256(s2) + 9242: 0100 addi s0,sp,128 + 9244: 00090003 lb zero,0(s2) + 9248: 0100 addi s0,sp,128 + 924a: 00090003 lb zero,0(s2) + 924e: 0100 addi s0,sp,128 + 9250: 14090003 lb zero,320(s2) 9254: 0100 addi s0,sp,128 - 9256: 0200 addi s0,sp,256 - 9258: 3f04 fld fs1,56(a4) - 925a: 1c090003 lb zero,448(s2) - 925e: 0100 addi s0,sp,128 - 9260: 0200 addi s0,sp,256 - 9262: 1104 addi s1,sp,160 - 9264: 08090003 lb zero,128(s2) - 9268: 0100 addi s0,sp,128 - 926a: 0200 addi s0,sp,256 - 926c: 1104 addi s1,sp,160 + 9256: 00090003 lb zero,0(s2) + 925a: 0100 addi s0,sp,128 + 925c: 04090003 lb zero,64(s2) + 9260: 0100 addi s0,sp,128 + 9262: 00090003 lb zero,0(s2) + 9266: 0100 addi s0,sp,128 + 9268: 00090003 lb zero,0(s2) + 926c: 0100 addi s0,sp,128 926e: 00090003 lb zero,0(s2) 9272: 0100 addi s0,sp,128 - 9274: 08090003 lb zero,128(s2) + 9274: 00090003 lb zero,0(s2) 9278: 0100 addi s0,sp,128 927a: 00090003 lb zero,0(s2) 927e: 0100 addi s0,sp,128 9280: 00090003 lb zero,0(s2) 9284: 0100 addi s0,sp,128 - 9286: 00090003 lb zero,0(s2) - 928a: 0100 addi s0,sp,128 - 928c: 00090003 lb zero,0(s2) - 9290: 0100 addi s0,sp,128 - 9292: 10090003 lb zero,256(s2) - 9296: 0100 addi s0,sp,128 - 9298: 00090003 lb zero,0(s2) - 929c: 0100 addi s0,sp,128 - 929e: 00090003 lb zero,0(s2) + 9286: 0c09 addi s8,s8,2 + 9288: 0000 unimp + 928a: 0101 addi sp,sp,0 + 928c: 0708 addi a0,sp,896 + 928e: 0000 unimp + 9290: 00a10003 lb zero,10(sp) + 9294: 0000 unimp + 9296: 0101 addi sp,sp,0 + 9298: 000d0efb 0xd0efb + 929c: 0101 addi sp,sp,0 + 929e: 0101 addi sp,sp,0 + 92a0: 0000 unimp 92a2: 0100 addi s0,sp,128 - 92a4: 14090003 lb zero,320(s2) - 92a8: 0100 addi s0,sp,128 - 92aa: 00090003 lb zero,0(s2) - 92ae: 0100 addi s0,sp,128 - 92b0: 04090003 lb zero,64(s2) - 92b4: 0100 addi s0,sp,128 - 92b6: 00090003 lb zero,0(s2) - 92ba: 0100 addi s0,sp,128 - 92bc: 00090003 lb zero,0(s2) - 92c0: 0100 addi s0,sp,128 - 92c2: 00090003 lb zero,0(s2) - 92c6: 0100 addi s0,sp,128 - 92c8: 00090003 lb zero,0(s2) - 92cc: 0100 addi s0,sp,128 - 92ce: 00090003 lb zero,0(s2) - 92d2: 0100 addi s0,sp,128 - 92d4: 00090003 lb zero,0(s2) - 92d8: 0100 addi s0,sp,128 - 92da: 0c09 addi s8,s8,2 - 92dc: 0000 unimp - 92de: 0101 addi sp,sp,0 - 92e0: 0708 addi a0,sp,896 - 92e2: 0000 unimp - 92e4: 00a10003 lb zero,10(sp) - 92e8: 0000 unimp - 92ea: 0101 addi sp,sp,0 - 92ec: 000d0efb 0xd0efb - 92f0: 0101 addi sp,sp,0 - 92f2: 0101 addi sp,sp,0 - 92f4: 0000 unimp - 92f6: 0100 addi s0,sp,128 - 92f8: 0000 unimp - 92fa: 2e01 jal 960a <_start-0x7fff69f6> - 92fc: 2f2e fld ft10,200(sp) - 92fe: 2e2e fld ft8,200(sp) - 9300: 2f2e2e2f 0x2f2e2e2f - 9304: 2e2e fld ft8,200(sp) - 9306: 7369722f 0x7369722f - 930a: 672d7663 bgeu s10,s2,9976 <_start-0x7fff668a> - 930e: 6c2f6363 bltu t5,sp,99d4 <_start-0x7fff662c> - 9312: 6269 lui tp,0x1a - 9314: 2f636367 0x2f636367 - 9318: 74666f73 csrrsi t5,0x746,12 - 931c: 662d lui a2,0xb - 931e: 0070 addi a2,sp,12 - 9320: 2e2e fld ft8,200(sp) - 9322: 2f2e2e2f 0x2f2e2e2f - 9326: 2e2e fld ft8,200(sp) - 9328: 2f2e2e2f 0x2f2e2e2f - 932c: 6972 flw fs2,28(sp) - 932e: 2d766373 csrrsi t1,0x2d7,12 - 9332: 2f636367 0x2f636367 - 9336: 696c flw fa1,84(a0) - 9338: 6762 flw fa4,24(sp) - 933a: 2e2f6363 bltu t5,sp,9620 <_start-0x7fff69e0> - 933e: 2f2e fld ft10,200(sp) - 9340: 6e69 lui t3,0x1a - 9342: 64756c63 bltu a0,t2,999a <_start-0x7fff6666> - 9346: 0065 c.nop 25 - 9348: 7400 flw fs0,40(s0) - 934a: 7572 flw fa0,60(sp) - 934c: 636e flw ft6,216(sp) - 934e: 6674 flw fa3,76(a2) - 9350: 6664 flw fs1,76(a2) - 9352: 2e32 fld ft8,264(sp) - 9354: 00010063 beqz sp,9354 <_start-0x7fff6cac> - 9358: 7300 flw fs0,32(a4) - 935a: 2d74666f jal a2,4fe30 <_start-0x7ffb01d0> - 935e: 7066 flw ft0,120(sp) - 9360: 682e flw fa6,200(sp) - 9362: 0100 addi s0,sp,128 + 92a4: 0000 unimp + 92a6: 2e01 jal 95b6 <_start-0x7fff6a4a> + 92a8: 2f2e fld ft10,200(sp) + 92aa: 2e2e fld ft8,200(sp) + 92ac: 2f2e2e2f 0x2f2e2e2f + 92b0: 2e2e fld ft8,200(sp) + 92b2: 7369722f 0x7369722f + 92b6: 672d7663 bgeu s10,s2,9922 <_start-0x7fff66de> + 92ba: 6c2f6363 bltu t5,sp,9980 <_start-0x7fff6680> + 92be: 6269 lui tp,0x1a + 92c0: 2f636367 0x2f636367 + 92c4: 74666f73 csrrsi t5,0x746,12 + 92c8: 662d lui a2,0xb + 92ca: 0070 addi a2,sp,12 + 92cc: 2e2e fld ft8,200(sp) + 92ce: 2f2e2e2f 0x2f2e2e2f + 92d2: 2e2e fld ft8,200(sp) + 92d4: 2f2e2e2f 0x2f2e2e2f + 92d8: 6972 flw fs2,28(sp) + 92da: 2d766373 csrrsi t1,0x2d7,12 + 92de: 2f636367 0x2f636367 + 92e2: 696c flw fa1,84(a0) + 92e4: 6762 flw fa4,24(sp) + 92e6: 2e2f6363 bltu t5,sp,95cc <_start-0x7fff6a34> + 92ea: 2f2e fld ft10,200(sp) + 92ec: 6e69 lui t3,0x1a + 92ee: 64756c63 bltu a0,t2,9946 <_start-0x7fff66ba> + 92f2: 0065 c.nop 25 + 92f4: 7400 flw fs0,40(s0) + 92f6: 7572 flw fa0,60(sp) + 92f8: 636e flw ft6,216(sp) + 92fa: 6674 flw fa3,76(a2) + 92fc: 6664 flw fs1,76(a2) + 92fe: 2e32 fld ft8,264(sp) + 9300: 00010063 beqz sp,9300 <_start-0x7fff6d00> + 9304: 7300 flw fs0,32(a4) + 9306: 2d74666f jal a2,4fddc <_start-0x7ffb0224> + 930a: 7066 flw ft0,120(sp) + 930c: 682e flw fa6,200(sp) + 930e: 0100 addi s0,sp,128 + 9310: 0000 unimp + 9312: 6f64 flw fs1,92(a4) + 9314: 6275 lui tp,0x1d + 9316: 656c flw fa1,76(a0) + 9318: 682e flw fa6,200(sp) + 931a: 0100 addi s0,sp,128 + 931c: 0000 unimp + 931e: 7571 lui a0,0xffffc + 9320: 6461 lui s0,0x18 + 9322: 682e flw fa6,200(sp) + 9324: 0100 addi s0,sp,128 + 9326: 0000 unimp + 9328: 6f6c flw fa1,92(a4) + 932a: 676e flw fa4,216(sp) + 932c: 6f6c flw fa1,92(a4) + 932e: 676e flw fa4,216(sp) + 9330: 682e flw fa6,200(sp) + 9332: 0200 addi s0,sp,256 + 9334: 0000 unimp + 9336: 0500 addi s0,sp,640 + 9338: 0001 nop + 933a: 0205 addi tp,tp,1 + 933c: 467c lw a5,76(a2) + 933e: 8001 c.srli64 s0 + 9340: 05012403 lw s0,80(sp) + 9344: 09010303 lb t1,144(sp) + 9348: 0000 unimp + 934a: 0301 addi t1,t1,0 + 934c: 0900 addi s0,sp,144 + 934e: 0000 unimp + 9350: 0501 addi a0,a0,0 + 9352: 030d addi t1,t1,3 + 9354: 0900 addi s0,sp,144 + 9356: 0000 unimp + 9358: 0501 addi a0,a0,0 + 935a: 09010303 lb t1,144(sp) + 935e: 0000 unimp + 9360: 0301 addi t1,t1,0 + 9362: 0900 addi s0,sp,144 9364: 0000 unimp - 9366: 6f64 flw fs1,92(a4) - 9368: 6275 lui tp,0x1d - 936a: 656c flw fa1,76(a0) - 936c: 682e flw fa6,200(sp) - 936e: 0100 addi s0,sp,128 + 9366: 0301 addi t1,t1,0 + 9368: 0900 addi s0,sp,144 + 936a: 0000 unimp + 936c: 0301 addi t1,t1,0 + 936e: 0900 addi s0,sp,144 9370: 0000 unimp - 9372: 7571 lui a0,0xffffc - 9374: 6461 lui s0,0x18 - 9376: 682e flw fa6,200(sp) - 9378: 0100 addi s0,sp,128 - 937a: 0000 unimp - 937c: 6f6c flw fa1,92(a4) - 937e: 676e flw fa4,216(sp) - 9380: 6f6c flw fa1,92(a4) - 9382: 676e flw fa4,216(sp) - 9384: 682e flw fa6,200(sp) - 9386: 0200 addi s0,sp,256 + 9372: 0301 addi t1,t1,0 + 9374: 0901 addi s2,s2,0 + 9376: 0000 unimp + 9378: 0301 addi t1,t1,0 + 937a: 0900 addi s0,sp,144 + 937c: 0000 unimp + 937e: 0301 addi t1,t1,0 + 9380: 0900 addi s0,sp,144 + 9382: 0000 unimp + 9384: 0301 addi t1,t1,0 + 9386: 0900 addi s0,sp,144 9388: 0000 unimp - 938a: 0500 addi s0,sp,640 - 938c: 0001 nop - 938e: 0205 addi tp,tp,1 - 9390: 45b8 lw a4,72(a1) - 9392: 8001 c.srli64 s0 - 9394: 05012403 lw s0,80(sp) - 9398: 09010303 lb t1,144(sp) - 939c: 0000 unimp - 939e: 0301 addi t1,t1,0 - 93a0: 0900 addi s0,sp,144 - 93a2: 0000 unimp - 93a4: 0501 addi a0,a0,0 - 93a6: 030d addi t1,t1,3 - 93a8: 0900 addi s0,sp,144 - 93aa: 0000 unimp - 93ac: 0501 addi a0,a0,0 - 93ae: 09010303 lb t1,144(sp) - 93b2: 0000 unimp - 93b4: 0301 addi t1,t1,0 - 93b6: 0900 addi s0,sp,144 - 93b8: 0000 unimp - 93ba: 0301 addi t1,t1,0 - 93bc: 0900 addi s0,sp,144 - 93be: 0000 unimp - 93c0: 0301 addi t1,t1,0 - 93c2: 0900 addi s0,sp,144 - 93c4: 0000 unimp - 93c6: 0301 addi t1,t1,0 - 93c8: 0901 addi s2,s2,0 - 93ca: 0000 unimp + 938a: 0301 addi t1,t1,0 + 938c: 0901 addi s2,s2,0 + 938e: 0000 unimp + 9390: 0301 addi t1,t1,0 + 9392: 0902 c.slli64 s2 + 9394: 0000 unimp + 9396: 0301 addi t1,t1,0 + 9398: 0901 addi s2,s2,0 + 939a: 0000 unimp + 939c: 0301 addi t1,t1,0 + 939e: 0900 addi s0,sp,144 + 93a0: 0000 unimp + 93a2: 0301 addi t1,t1,0 + 93a4: 0900 addi s0,sp,144 + 93a6: 0000 unimp + 93a8: 0301 addi t1,t1,0 + 93aa: 0900 addi s0,sp,144 + 93ac: 0000 unimp + 93ae: 0501 addi a0,a0,0 + 93b0: 0601 addi a2,a2,0 + 93b2: 00097903 0x97903 + 93b6: 0100 addi s0,sp,128 + 93b8: 10090003 lb zero,256(s2) + 93bc: 0100 addi s0,sp,128 + 93be: 0305 addi t1,t1,1 + 93c0: 04090703 lb a4,64(s2) + 93c4: 0100 addi s0,sp,128 + 93c6: 0306 slli t1,t1,0x1 + 93c8: 0900 addi s0,sp,144 + 93ca: 0020 addi s0,sp,8 93cc: 0301 addi t1,t1,0 93ce: 0900 addi s0,sp,144 - 93d0: 0000 unimp + 93d0: 0008 0x8 93d2: 0301 addi t1,t1,0 93d4: 0900 addi s0,sp,144 93d6: 0000 unimp @@ -56913,14 +56961,14 @@ Disassembly of section .debug_line: 93da: 0900 addi s0,sp,144 93dc: 0000 unimp 93de: 0301 addi t1,t1,0 - 93e0: 0901 addi s2,s2,0 - 93e2: 0000 unimp + 93e0: 0900 addi s0,sp,144 + 93e2: 0004 0x4 93e4: 0301 addi t1,t1,0 - 93e6: 0902 c.slli64 s2 - 93e8: 0000 unimp + 93e6: 0900 addi s0,sp,144 + 93e8: 0004 0x4 93ea: 0301 addi t1,t1,0 - 93ec: 0901 addi s2,s2,0 - 93ee: 0000 unimp + 93ec: 0900 addi s0,sp,144 + 93ee: 0004 0x4 93f0: 0301 addi t1,t1,0 93f2: 0900 addi s0,sp,144 93f4: 0000 unimp @@ -56930,158 +56978,161 @@ Disassembly of section .debug_line: 93fc: 0301 addi t1,t1,0 93fe: 0900 addi s0,sp,144 9400: 0000 unimp - 9402: 0501 addi a0,a0,0 - 9404: 0601 addi a2,a2,0 - 9406: 00097903 0x97903 - 940a: 0100 addi s0,sp,128 - 940c: 10090003 lb zero,256(s2) - 9410: 0100 addi s0,sp,128 - 9412: 0305 addi t1,t1,1 - 9414: 04090703 lb a4,64(s2) - 9418: 0100 addi s0,sp,128 - 941a: 0306 slli t1,t1,0x1 + 9402: 0301 addi t1,t1,0 + 9404: 0900 addi s0,sp,144 + 9406: 0000 unimp + 9408: 0301 addi t1,t1,0 + 940a: 0900 addi s0,sp,144 + 940c: 0000 unimp + 940e: 0301 addi t1,t1,0 + 9410: 0900 addi s0,sp,144 + 9412: 0000 unimp + 9414: 0301 addi t1,t1,0 + 9416: 0900 addi s0,sp,144 + 9418: 0000 unimp + 941a: 0301 addi t1,t1,0 941c: 0900 addi s0,sp,144 - 941e: 0020 addi s0,sp,8 + 941e: 0000 unimp 9420: 0301 addi t1,t1,0 9422: 0900 addi s0,sp,144 - 9424: 0008 0x8 - 9426: 0301 addi t1,t1,0 - 9428: 0900 addi s0,sp,144 - 942a: 0000 unimp - 942c: 0301 addi t1,t1,0 - 942e: 0900 addi s0,sp,144 - 9430: 0000 unimp - 9432: 0301 addi t1,t1,0 - 9434: 0900 addi s0,sp,144 - 9436: 0004 0x4 - 9438: 0301 addi t1,t1,0 - 943a: 0900 addi s0,sp,144 - 943c: 0004 0x4 - 943e: 0301 addi t1,t1,0 + 9424: 0000 unimp + 9426: 0001 nop + 9428: 0402 c.slli64 s0 + 942a: 0308 addi a0,sp,384 + 942c: 0900 addi s0,sp,144 + 942e: 0008 0x8 + 9430: 0001 nop + 9432: 0402 c.slli64 s0 + 9434: 0308 addi a0,sp,384 + 9436: 0900 addi s0,sp,144 + 9438: 001c 0x1c + 943a: 0001 nop + 943c: 0402 c.slli64 s0 + 943e: 0308 addi a0,sp,384 9440: 0900 addi s0,sp,144 - 9442: 0004 0x4 - 9444: 0301 addi t1,t1,0 - 9446: 0900 addi s0,sp,144 - 9448: 0000 unimp - 944a: 0301 addi t1,t1,0 - 944c: 0900 addi s0,sp,144 - 944e: 0000 unimp - 9450: 0301 addi t1,t1,0 - 9452: 0900 addi s0,sp,144 - 9454: 0000 unimp - 9456: 0301 addi t1,t1,0 - 9458: 0900 addi s0,sp,144 - 945a: 0000 unimp - 945c: 0301 addi t1,t1,0 - 945e: 0900 addi s0,sp,144 - 9460: 0000 unimp - 9462: 0301 addi t1,t1,0 - 9464: 0900 addi s0,sp,144 - 9466: 0000 unimp - 9468: 0301 addi t1,t1,0 - 946a: 0900 addi s0,sp,144 - 946c: 0000 unimp - 946e: 0301 addi t1,t1,0 - 9470: 0900 addi s0,sp,144 - 9472: 0000 unimp - 9474: 0301 addi t1,t1,0 - 9476: 0900 addi s0,sp,144 - 9478: 0000 unimp - 947a: 0001 nop - 947c: 0402 c.slli64 s0 - 947e: 0308 addi a0,sp,384 - 9480: 0900 addi s0,sp,144 - 9482: 0008 0x8 - 9484: 0001 nop - 9486: 0402 c.slli64 s0 - 9488: 0308 addi a0,sp,384 - 948a: 0900 addi s0,sp,144 - 948c: 001c 0x1c - 948e: 0001 nop - 9490: 0402 c.slli64 s0 - 9492: 0308 addi a0,sp,384 - 9494: 0900 addi s0,sp,144 - 9496: 0000 unimp - 9498: 0001 nop - 949a: 0402 c.slli64 s0 - 949c: 0309 addi t1,t1,2 - 949e: 0900 addi s0,sp,144 - 94a0: 0004 0x4 - 94a2: 0001 nop - 94a4: 0402 c.slli64 s0 - 94a6: 0609 addi a2,a2,2 - 94a8: 04090203 lb tp,64(s2) - 94ac: 0100 addi s0,sp,128 - 94ae: 0200 addi s0,sp,256 - 94b0: 0904 addi s1,sp,144 - 94b2: 04097e03 0x4097e03 - 94b6: 0100 addi s0,sp,128 - 94b8: 0200 addi s0,sp,256 - 94ba: 0904 addi s1,sp,144 - 94bc: 04090203 lb tp,64(s2) - 94c0: 0100 addi s0,sp,128 - 94c2: 0200 addi s0,sp,256 - 94c4: 0904 addi s1,sp,144 - 94c6: 08097e03 0x8097e03 - 94ca: 0100 addi s0,sp,128 - 94cc: 0200 addi s0,sp,256 - 94ce: 0904 addi s1,sp,144 - 94d0: 0306 slli t1,t1,0x1 - 94d2: 0900 addi s0,sp,144 - 94d4: 0004 0x4 - 94d6: 0001 nop - 94d8: 0402 c.slli64 s0 - 94da: 0309 addi t1,t1,2 - 94dc: 0900 addi s0,sp,144 - 94de: 0000 unimp - 94e0: 0001 nop - 94e2: 0402 c.slli64 s0 - 94e4: 0309 addi t1,t1,2 - 94e6: 0900 addi s0,sp,144 - 94e8: 0000 unimp - 94ea: 0001 nop - 94ec: 0402 c.slli64 s0 - 94ee: 0309 addi t1,t1,2 - 94f0: 0902 c.slli64 s2 - 94f2: 0000 unimp - 94f4: 0001 nop - 94f6: 0402 c.slli64 s0 - 94f8: 0309 addi t1,t1,2 + 9442: 0000 unimp + 9444: 0001 nop + 9446: 0402 c.slli64 s0 + 9448: 0309 addi t1,t1,2 + 944a: 0900 addi s0,sp,144 + 944c: 0004 0x4 + 944e: 0001 nop + 9450: 0402 c.slli64 s0 + 9452: 0609 addi a2,a2,2 + 9454: 04090203 lb tp,64(s2) + 9458: 0100 addi s0,sp,128 + 945a: 0200 addi s0,sp,256 + 945c: 0904 addi s1,sp,144 + 945e: 04097e03 0x4097e03 + 9462: 0100 addi s0,sp,128 + 9464: 0200 addi s0,sp,256 + 9466: 0904 addi s1,sp,144 + 9468: 04090203 lb tp,64(s2) + 946c: 0100 addi s0,sp,128 + 946e: 0200 addi s0,sp,256 + 9470: 0904 addi s1,sp,144 + 9472: 08097e03 0x8097e03 + 9476: 0100 addi s0,sp,128 + 9478: 0200 addi s0,sp,256 + 947a: 0904 addi s1,sp,144 + 947c: 0306 slli t1,t1,0x1 + 947e: 0900 addi s0,sp,144 + 9480: 0004 0x4 + 9482: 0001 nop + 9484: 0402 c.slli64 s0 + 9486: 0309 addi t1,t1,2 + 9488: 0900 addi s0,sp,144 + 948a: 0000 unimp + 948c: 0001 nop + 948e: 0402 c.slli64 s0 + 9490: 0309 addi t1,t1,2 + 9492: 0900 addi s0,sp,144 + 9494: 0000 unimp + 9496: 0001 nop + 9498: 0402 c.slli64 s0 + 949a: 0309 addi t1,t1,2 + 949c: 0902 c.slli64 s2 + 949e: 0000 unimp + 94a0: 0001 nop + 94a2: 0402 c.slli64 s0 + 94a4: 0309 addi t1,t1,2 + 94a6: 0900 addi s0,sp,144 + 94a8: 0000 unimp + 94aa: 0001 nop + 94ac: 0402 c.slli64 s0 + 94ae: 0309 addi t1,t1,2 + 94b0: 0900 addi s0,sp,144 + 94b2: 0000 unimp + 94b4: 0001 nop + 94b6: 0402 c.slli64 s0 + 94b8: 0309 addi t1,t1,2 + 94ba: 0900 addi s0,sp,144 + 94bc: 0000 unimp + 94be: 0001 nop + 94c0: 0402 c.slli64 s0 + 94c2: 0309 addi t1,t1,2 + 94c4: 0900 addi s0,sp,144 + 94c6: 0000 unimp + 94c8: 0001 nop + 94ca: 0402 c.slli64 s0 + 94cc: 0301 addi t1,t1,0 + 94ce: 0900 addi s0,sp,144 + 94d0: 0008 0x8 + 94d2: 0001 nop + 94d4: 0402 c.slli64 s0 + 94d6: 0301 addi t1,t1,0 + 94d8: 0900 addi s0,sp,144 + 94da: 000c 0xc + 94dc: 0001 nop + 94de: 0402 c.slli64 s0 + 94e0: 0304 addi s1,sp,384 + 94e2: 0900 addi s0,sp,144 + 94e4: 0008 0x8 + 94e6: 0301 addi t1,t1,0 + 94e8: 0900 addi s0,sp,144 + 94ea: 0004 0x4 + 94ec: 0301 addi t1,t1,0 + 94ee: 0900 addi s0,sp,144 + 94f0: 0000 unimp + 94f2: 0301 addi t1,t1,0 + 94f4: 0900 addi s0,sp,144 + 94f6: 0000 unimp + 94f8: 0301 addi t1,t1,0 94fa: 0900 addi s0,sp,144 94fc: 0000 unimp - 94fe: 0001 nop - 9500: 0402 c.slli64 s0 - 9502: 0309 addi t1,t1,2 - 9504: 0900 addi s0,sp,144 - 9506: 0000 unimp - 9508: 0001 nop - 950a: 0402 c.slli64 s0 - 950c: 0309 addi t1,t1,2 - 950e: 0900 addi s0,sp,144 - 9510: 0000 unimp - 9512: 0001 nop - 9514: 0402 c.slli64 s0 - 9516: 0309 addi t1,t1,2 + 94fe: 0301 addi t1,t1,0 + 9500: 0900 addi s0,sp,144 + 9502: 0000 unimp + 9504: 0301 addi t1,t1,0 + 9506: 0900 addi s0,sp,144 + 9508: 0000 unimp + 950a: 0301 addi t1,t1,0 + 950c: 0900 addi s0,sp,144 + 950e: 000c 0xc + 9510: 0301 addi t1,t1,0 + 9512: 0900 addi s0,sp,144 + 9514: 0000 unimp + 9516: 0301 addi t1,t1,0 9518: 0900 addi s0,sp,144 951a: 0000 unimp - 951c: 0001 nop - 951e: 0402 c.slli64 s0 - 9520: 0301 addi t1,t1,0 - 9522: 0900 addi s0,sp,144 - 9524: 0008 0x8 - 9526: 0001 nop - 9528: 0402 c.slli64 s0 - 952a: 0301 addi t1,t1,0 - 952c: 0900 addi s0,sp,144 - 952e: 000c 0xc - 9530: 0001 nop - 9532: 0402 c.slli64 s0 - 9534: 0304 addi s1,sp,384 + 951c: 0301 addi t1,t1,0 + 951e: 0900 addi s0,sp,144 + 9520: 0000 unimp + 9522: 0301 addi t1,t1,0 + 9524: 0900 addi s0,sp,144 + 9526: 0000 unimp + 9528: 0301 addi t1,t1,0 + 952a: 0900 addi s0,sp,144 + 952c: 0000 unimp + 952e: 0301 addi t1,t1,0 + 9530: 0900 addi s0,sp,144 + 9532: 002c addi a1,sp,8 + 9534: 0301 addi t1,t1,0 9536: 0900 addi s0,sp,144 - 9538: 0008 0x8 + 9538: 0000 unimp 953a: 0301 addi t1,t1,0 953c: 0900 addi s0,sp,144 - 953e: 0004 0x4 + 953e: 0000 unimp 9540: 0301 addi t1,t1,0 9542: 0900 addi s0,sp,144 9544: 0000 unimp @@ -57094,1049 +57145,968 @@ Disassembly of section .debug_line: 9552: 0301 addi t1,t1,0 9554: 0900 addi s0,sp,144 9556: 0000 unimp - 9558: 0301 addi t1,t1,0 - 955a: 0900 addi s0,sp,144 - 955c: 0000 unimp - 955e: 0301 addi t1,t1,0 - 9560: 0900 addi s0,sp,144 - 9562: 000c 0xc - 9564: 0301 addi t1,t1,0 - 9566: 0900 addi s0,sp,144 - 9568: 0000 unimp - 956a: 0301 addi t1,t1,0 - 956c: 0900 addi s0,sp,144 - 956e: 0000 unimp - 9570: 0301 addi t1,t1,0 - 9572: 0900 addi s0,sp,144 + 9558: 0001 nop + 955a: 0402 c.slli64 s0 + 955c: 0900033b 0x900033b + 9560: 0004 0x4 + 9562: 0001 nop + 9564: 0402 c.slli64 s0 + 9566: 0900033b 0x900033b + 956a: 0000 unimp + 956c: 0001 nop + 956e: 0402 c.slli64 s0 + 9570: 0900033b 0x900033b 9574: 0000 unimp - 9576: 0301 addi t1,t1,0 - 9578: 0900 addi s0,sp,144 - 957a: 0000 unimp - 957c: 0301 addi t1,t1,0 - 957e: 0900 addi s0,sp,144 - 9580: 0000 unimp - 9582: 0301 addi t1,t1,0 - 9584: 0900 addi s0,sp,144 - 9586: 002c addi a1,sp,8 - 9588: 0301 addi t1,t1,0 - 958a: 0900 addi s0,sp,144 - 958c: 0000 unimp - 958e: 0301 addi t1,t1,0 + 9576: 0001 nop + 9578: 0402 c.slli64 s0 + 957a: 0900033b 0x900033b + 957e: 0004 0x4 + 9580: 0001 nop + 9582: 0402 c.slli64 s0 + 9584: 0375 addi t1,t1,29 + 9586: 0900 addi s0,sp,144 + 9588: 0004 0x4 + 958a: 0001 nop + 958c: 0402 c.slli64 s0 + 958e: 0375 addi t1,t1,29 9590: 0900 addi s0,sp,144 9592: 0000 unimp - 9594: 0301 addi t1,t1,0 - 9596: 0900 addi s0,sp,144 - 9598: 0000 unimp - 959a: 0301 addi t1,t1,0 - 959c: 0900 addi s0,sp,144 - 959e: 0000 unimp - 95a0: 0301 addi t1,t1,0 - 95a2: 0900 addi s0,sp,144 - 95a4: 0000 unimp - 95a6: 0301 addi t1,t1,0 - 95a8: 0900 addi s0,sp,144 - 95aa: 0000 unimp - 95ac: 0001 nop - 95ae: 0402 c.slli64 s0 - 95b0: 0900033b 0x900033b - 95b4: 0004 0x4 - 95b6: 0001 nop - 95b8: 0402 c.slli64 s0 - 95ba: 0900033b 0x900033b - 95be: 0000 unimp - 95c0: 0001 nop - 95c2: 0402 c.slli64 s0 - 95c4: 0900033b 0x900033b - 95c8: 0000 unimp - 95ca: 0001 nop - 95cc: 0402 c.slli64 s0 - 95ce: 0900033b 0x900033b - 95d2: 0004 0x4 - 95d4: 0001 nop - 95d6: 0402 c.slli64 s0 - 95d8: 0375 addi t1,t1,29 - 95da: 0900 addi s0,sp,144 - 95dc: 0004 0x4 - 95de: 0001 nop - 95e0: 0402 c.slli64 s0 - 95e2: 0375 addi t1,t1,29 - 95e4: 0900 addi s0,sp,144 - 95e6: 0000 unimp - 95e8: 0001 nop - 95ea: 0402 c.slli64 s0 - 95ec: 0375 addi t1,t1,29 - 95ee: 0904 addi s1,sp,144 - 95f0: 0000 unimp - 95f2: 0001 nop - 95f4: 0402 c.slli64 s0 - 95f6: 0375 addi t1,t1,29 - 95f8: 0900 addi s0,sp,144 - 95fa: 0000 unimp - 95fc: 0001 nop - 95fe: 0402 c.slli64 s0 - 9600: 0375 addi t1,t1,29 - 9602: 0900 addi s0,sp,144 - 9604: 0000 unimp - 9606: 0001 nop - 9608: 0402 c.slli64 s0 - 960a: 0375 addi t1,t1,29 - 960c: 0900 addi s0,sp,144 - 960e: 0000 unimp - 9610: 0001 nop - 9612: 0402 c.slli64 s0 - 9614: 0375 addi t1,t1,29 - 9616: 0900 addi s0,sp,144 - 9618: 0000 unimp - 961a: 0001 nop - 961c: 0402 c.slli64 s0 - 961e: 0325 addi t1,t1,9 - 9620: 0900 addi s0,sp,144 - 9622: 0008 0x8 - 9624: 0001 nop - 9626: 0402 c.slli64 s0 - 9628: 0325 addi t1,t1,9 - 962a: 0900 addi s0,sp,144 - 962c: 0000 unimp - 962e: 0001 nop - 9630: 0402 c.slli64 s0 - 9632: 0325 addi t1,t1,9 - 9634: 0900 addi s0,sp,144 - 9636: 0000 unimp - 9638: 0001 nop - 963a: 0402 c.slli64 s0 - 963c: 0325 addi t1,t1,9 - 963e: 0900 addi s0,sp,144 - 9640: 0000 unimp - 9642: 0001 nop - 9644: 0402 c.slli64 s0 - 9646: 032c addi a1,sp,392 - 9648: 0900 addi s0,sp,144 - 964a: 000c 0xc - 964c: 0001 nop - 964e: 0402 c.slli64 s0 - 9650: 032c addi a1,sp,392 - 9652: 0900 addi s0,sp,144 - 9654: 0000 unimp - 9656: 0001 nop - 9658: 0402 c.slli64 s0 - 965a: 032c addi a1,sp,392 - 965c: 0900 addi s0,sp,144 - 965e: 0000 unimp - 9660: 0001 nop - 9662: 0402 c.slli64 s0 - 9664: 032c addi a1,sp,392 - 9666: 0900 addi s0,sp,144 - 9668: 0004 0x4 - 966a: 0001 nop - 966c: 0402 c.slli64 s0 - 966e: 032c addi a1,sp,392 - 9670: 0900 addi s0,sp,144 - 9672: 0008 0x8 - 9674: 0001 nop - 9676: 0402 c.slli64 s0 - 9678: 0312 slli t1,t1,0x4 - 967a: 097c addi a5,sp,156 - 967c: 0008 0x8 - 967e: 0001 nop - 9680: 0402 c.slli64 s0 - 9682: 0314 addi a3,sp,384 - 9684: 0900 addi s0,sp,144 - 9686: 0008 0x8 - 9688: 0001 nop - 968a: 0402 c.slli64 s0 - 968c: 0314 addi a3,sp,384 - 968e: 0900 addi s0,sp,144 - 9690: 0004 0x4 - 9692: 0001 nop - 9694: 0402 c.slli64 s0 - 9696: 00030627 0x30627 - 969a: 0409 addi s0,s0,2 - 969c: 0100 addi s0,sp,128 - 969e: 0200 addi s0,sp,256 - 96a0: 1504 addi s1,sp,672 - 96a2: 0306 slli t1,t1,0x1 - 96a4: 0900 addi s0,sp,144 - 96a6: 000c 0xc - 96a8: 0001 nop - 96aa: 0402 c.slli64 s0 - 96ac: 0315 addi t1,t1,5 - 96ae: 0900 addi s0,sp,144 - 96b0: 0018 0x18 - 96b2: 0001 nop - 96b4: 0402 c.slli64 s0 - 96b6: 0315 addi t1,t1,5 - 96b8: 0900 addi s0,sp,144 - 96ba: 0000 unimp - 96bc: 0001 nop - 96be: 0402 c.slli64 s0 - 96c0: 0315 addi t1,t1,5 - 96c2: 0900 addi s0,sp,144 - 96c4: 0000 unimp - 96c6: 0001 nop - 96c8: 0402 c.slli64 s0 - 96ca: 0315 addi t1,t1,5 - 96cc: 0900 addi s0,sp,144 - 96ce: 0000 unimp - 96d0: 0001 nop - 96d2: 0402 c.slli64 s0 - 96d4: 0315 addi t1,t1,5 - 96d6: 0900 addi s0,sp,144 - 96d8: 0000 unimp - 96da: 0001 nop - 96dc: 0402 c.slli64 s0 - 96de: 0315 addi t1,t1,5 - 96e0: 0900 addi s0,sp,144 - 96e2: 0000 unimp - 96e4: 0001 nop - 96e6: 0402 c.slli64 s0 - 96e8: 0315 addi t1,t1,5 - 96ea: 0900 addi s0,sp,144 - 96ec: 0000 unimp - 96ee: 0001 nop - 96f0: 0402 c.slli64 s0 - 96f2: 0315 addi t1,t1,5 - 96f4: 0900 addi s0,sp,144 - 96f6: 0004 0x4 - 96f8: 0001 nop - 96fa: 0402 c.slli64 s0 - 96fc: 0315 addi t1,t1,5 - 96fe: 0900 addi s0,sp,144 - 9700: 0000 unimp - 9702: 0001 nop - 9704: 0402 c.slli64 s0 - 9706: 0315 addi t1,t1,5 - 9708: 0900 addi s0,sp,144 - 970a: 0000 unimp - 970c: 0001 nop - 970e: 0402 c.slli64 s0 - 9710: 0315 addi t1,t1,5 - 9712: 0900 addi s0,sp,144 - 9714: 0000 unimp - 9716: 0001 nop - 9718: 0402 c.slli64 s0 - 971a: 0319 addi t1,t1,6 - 971c: 0900 addi s0,sp,144 - 971e: 000c 0xc - 9720: 0001 nop - 9722: 0402 c.slli64 s0 - 9724: 0319 addi t1,t1,6 - 9726: 0900 addi s0,sp,144 - 9728: 0010 0x10 - 972a: 0001 nop - 972c: 0402 c.slli64 s0 - 972e: 0319 addi t1,t1,6 - 9730: 0900 addi s0,sp,144 - 9732: 0000 unimp - 9734: 0001 nop - 9736: 0402 c.slli64 s0 - 9738: 031a slli t1,t1,0x6 - 973a: 0900 addi s0,sp,144 - 973c: 0004 0x4 - 973e: 0601 addi a2,a2,0 - 9740: 0c090003 lb zero,192(s2) + 9594: 0001 nop + 9596: 0402 c.slli64 s0 + 9598: 0375 addi t1,t1,29 + 959a: 0904 addi s1,sp,144 + 959c: 0000 unimp + 959e: 0001 nop + 95a0: 0402 c.slli64 s0 + 95a2: 0375 addi t1,t1,29 + 95a4: 0900 addi s0,sp,144 + 95a6: 0000 unimp + 95a8: 0001 nop + 95aa: 0402 c.slli64 s0 + 95ac: 0375 addi t1,t1,29 + 95ae: 0900 addi s0,sp,144 + 95b0: 0000 unimp + 95b2: 0001 nop + 95b4: 0402 c.slli64 s0 + 95b6: 0375 addi t1,t1,29 + 95b8: 0900 addi s0,sp,144 + 95ba: 0000 unimp + 95bc: 0001 nop + 95be: 0402 c.slli64 s0 + 95c0: 0375 addi t1,t1,29 + 95c2: 0900 addi s0,sp,144 + 95c4: 0000 unimp + 95c6: 0001 nop + 95c8: 0402 c.slli64 s0 + 95ca: 0325 addi t1,t1,9 + 95cc: 0900 addi s0,sp,144 + 95ce: 0008 0x8 + 95d0: 0001 nop + 95d2: 0402 c.slli64 s0 + 95d4: 0325 addi t1,t1,9 + 95d6: 0900 addi s0,sp,144 + 95d8: 0000 unimp + 95da: 0001 nop + 95dc: 0402 c.slli64 s0 + 95de: 0325 addi t1,t1,9 + 95e0: 0900 addi s0,sp,144 + 95e2: 0000 unimp + 95e4: 0001 nop + 95e6: 0402 c.slli64 s0 + 95e8: 0325 addi t1,t1,9 + 95ea: 0900 addi s0,sp,144 + 95ec: 0000 unimp + 95ee: 0001 nop + 95f0: 0402 c.slli64 s0 + 95f2: 032c addi a1,sp,392 + 95f4: 0900 addi s0,sp,144 + 95f6: 000c 0xc + 95f8: 0001 nop + 95fa: 0402 c.slli64 s0 + 95fc: 032c addi a1,sp,392 + 95fe: 0900 addi s0,sp,144 + 9600: 0000 unimp + 9602: 0001 nop + 9604: 0402 c.slli64 s0 + 9606: 032c addi a1,sp,392 + 9608: 0900 addi s0,sp,144 + 960a: 0000 unimp + 960c: 0001 nop + 960e: 0402 c.slli64 s0 + 9610: 032c addi a1,sp,392 + 9612: 0900 addi s0,sp,144 + 9614: 0004 0x4 + 9616: 0001 nop + 9618: 0402 c.slli64 s0 + 961a: 032c addi a1,sp,392 + 961c: 0900 addi s0,sp,144 + 961e: 0008 0x8 + 9620: 0001 nop + 9622: 0402 c.slli64 s0 + 9624: 0312 slli t1,t1,0x4 + 9626: 097c addi a5,sp,156 + 9628: 0008 0x8 + 962a: 0001 nop + 962c: 0402 c.slli64 s0 + 962e: 0314 addi a3,sp,384 + 9630: 0900 addi s0,sp,144 + 9632: 0008 0x8 + 9634: 0001 nop + 9636: 0402 c.slli64 s0 + 9638: 0314 addi a3,sp,384 + 963a: 0900 addi s0,sp,144 + 963c: 0004 0x4 + 963e: 0001 nop + 9640: 0402 c.slli64 s0 + 9642: 00030627 0x30627 + 9646: 0409 addi s0,s0,2 + 9648: 0100 addi s0,sp,128 + 964a: 0200 addi s0,sp,256 + 964c: 1504 addi s1,sp,672 + 964e: 0306 slli t1,t1,0x1 + 9650: 0900 addi s0,sp,144 + 9652: 000c 0xc + 9654: 0001 nop + 9656: 0402 c.slli64 s0 + 9658: 0315 addi t1,t1,5 + 965a: 0900 addi s0,sp,144 + 965c: 0018 0x18 + 965e: 0001 nop + 9660: 0402 c.slli64 s0 + 9662: 0315 addi t1,t1,5 + 9664: 0900 addi s0,sp,144 + 9666: 0000 unimp + 9668: 0001 nop + 966a: 0402 c.slli64 s0 + 966c: 0315 addi t1,t1,5 + 966e: 0900 addi s0,sp,144 + 9670: 0000 unimp + 9672: 0001 nop + 9674: 0402 c.slli64 s0 + 9676: 0315 addi t1,t1,5 + 9678: 0900 addi s0,sp,144 + 967a: 0000 unimp + 967c: 0001 nop + 967e: 0402 c.slli64 s0 + 9680: 0315 addi t1,t1,5 + 9682: 0900 addi s0,sp,144 + 9684: 0000 unimp + 9686: 0001 nop + 9688: 0402 c.slli64 s0 + 968a: 0315 addi t1,t1,5 + 968c: 0900 addi s0,sp,144 + 968e: 0000 unimp + 9690: 0001 nop + 9692: 0402 c.slli64 s0 + 9694: 0315 addi t1,t1,5 + 9696: 0900 addi s0,sp,144 + 9698: 0000 unimp + 969a: 0001 nop + 969c: 0402 c.slli64 s0 + 969e: 0315 addi t1,t1,5 + 96a0: 0900 addi s0,sp,144 + 96a2: 0004 0x4 + 96a4: 0001 nop + 96a6: 0402 c.slli64 s0 + 96a8: 0315 addi t1,t1,5 + 96aa: 0900 addi s0,sp,144 + 96ac: 0000 unimp + 96ae: 0001 nop + 96b0: 0402 c.slli64 s0 + 96b2: 0315 addi t1,t1,5 + 96b4: 0900 addi s0,sp,144 + 96b6: 0000 unimp + 96b8: 0001 nop + 96ba: 0402 c.slli64 s0 + 96bc: 0315 addi t1,t1,5 + 96be: 0900 addi s0,sp,144 + 96c0: 0000 unimp + 96c2: 0001 nop + 96c4: 0402 c.slli64 s0 + 96c6: 0319 addi t1,t1,6 + 96c8: 0900 addi s0,sp,144 + 96ca: 000c 0xc + 96cc: 0001 nop + 96ce: 0402 c.slli64 s0 + 96d0: 0319 addi t1,t1,6 + 96d2: 0900 addi s0,sp,144 + 96d4: 0010 0x10 + 96d6: 0001 nop + 96d8: 0402 c.slli64 s0 + 96da: 0319 addi t1,t1,6 + 96dc: 0900 addi s0,sp,144 + 96de: 0000 unimp + 96e0: 0001 nop + 96e2: 0402 c.slli64 s0 + 96e4: 031a slli t1,t1,0x6 + 96e6: 0900 addi s0,sp,144 + 96e8: 0004 0x4 + 96ea: 0601 addi a2,a2,0 + 96ec: 0c090003 lb zero,192(s2) + 96f0: 0100 addi s0,sp,128 + 96f2: 0200 addi s0,sp,256 + 96f4: 1f04 addi s1,sp,944 + 96f6: 0306 slli t1,t1,0x1 + 96f8: 0900 addi s0,sp,144 + 96fa: 000c 0xc + 96fc: 0001 nop + 96fe: 0402 c.slli64 s0 + 9700: 031f 0900 0014 0x140900031f + 9706: 0001 nop + 9708: 0402 c.slli64 s0 + 970a: 031f 0900 0000 0x900031f + 9710: 0001 nop + 9712: 0402 c.slli64 s0 + 9714: 061c addi a5,sp,768 + 9716: 1c090003 lb zero,448(s2) + 971a: 0100 addi s0,sp,128 + 971c: 0200 addi s0,sp,256 + 971e: 1c04 addi s1,sp,560 + 9720: 0306 slli t1,t1,0x1 + 9722: 0900 addi s0,sp,144 + 9724: 0014 0x14 + 9726: 0001 nop + 9728: 0402 c.slli64 s0 + 972a: 031c addi a5,sp,384 + 972c: 0900 addi s0,sp,144 + 972e: 0010 0x10 + 9730: 0001 nop + 9732: 0402 c.slli64 s0 + 9734: 0320 addi s0,sp,392 + 9736: 0900 addi s0,sp,144 + 9738: 0008 0x8 + 973a: 0001 nop + 973c: 0402 c.slli64 s0 + 973e: 00030623 sb zero,12(t1) + 9742: 0809 addi a6,a6,2 9744: 0100 addi s0,sp,128 9746: 0200 addi s0,sp,256 - 9748: 1f04 addi s1,sp,944 + 9748: 2304 fld fs1,0(a4) 974a: 0306 slli t1,t1,0x1 974c: 0900 addi s0,sp,144 - 974e: 000c 0xc + 974e: 0018 0x18 9750: 0001 nop 9752: 0402 c.slli64 s0 - 9754: 031f 0900 0014 0x140900031f + 9754: 0325 addi t1,t1,9 + 9756: 0900 addi s0,sp,144 + 9758: 0004 0x4 975a: 0001 nop 975c: 0402 c.slli64 s0 - 975e: 031f 0900 0000 0x900031f + 975e: 0326 slli t1,t1,0x9 + 9760: 0900 addi s0,sp,144 + 9762: 0004 0x4 9764: 0001 nop 9766: 0402 c.slli64 s0 - 9768: 061c addi a5,sp,768 - 976a: 1c090003 lb zero,448(s2) - 976e: 0100 addi s0,sp,128 - 9770: 0200 addi s0,sp,256 - 9772: 1c04 addi s1,sp,560 - 9774: 0306 slli t1,t1,0x1 - 9776: 0900 addi s0,sp,144 - 9778: 0014 0x14 - 977a: 0001 nop - 977c: 0402 c.slli64 s0 - 977e: 031c addi a5,sp,384 - 9780: 0900 addi s0,sp,144 - 9782: 0010 0x10 - 9784: 0001 nop - 9786: 0402 c.slli64 s0 - 9788: 0320 addi s0,sp,392 - 978a: 0900 addi s0,sp,144 - 978c: 0008 0x8 - 978e: 0001 nop - 9790: 0402 c.slli64 s0 - 9792: 00030623 sb zero,12(t1) - 9796: 0809 addi a6,a6,2 - 9798: 0100 addi s0,sp,128 - 979a: 0200 addi s0,sp,256 - 979c: 2304 fld fs1,0(a4) - 979e: 0306 slli t1,t1,0x1 - 97a0: 0900 addi s0,sp,144 - 97a2: 0018 0x18 - 97a4: 0001 nop - 97a6: 0402 c.slli64 s0 - 97a8: 0325 addi t1,t1,9 - 97aa: 0900 addi s0,sp,144 - 97ac: 0004 0x4 - 97ae: 0001 nop - 97b0: 0402 c.slli64 s0 - 97b2: 0326 slli t1,t1,0x9 - 97b4: 0900 addi s0,sp,144 - 97b6: 0004 0x4 - 97b8: 0001 nop - 97ba: 0402 c.slli64 s0 - 97bc: 0326 slli t1,t1,0x9 - 97be: 0900 addi s0,sp,144 - 97c0: 000c 0xc - 97c2: 0001 nop - 97c4: 0402 c.slli64 s0 - 97c6: 0326 slli t1,t1,0x9 - 97c8: 0900 addi s0,sp,144 - 97ca: 0004 0x4 - 97cc: 0001 nop - 97ce: 0402 c.slli64 s0 - 97d0: 09000327 0x9000327 - 97d4: 0004 0x4 - 97d6: 0001 nop - 97d8: 0402 c.slli64 s0 - 97da: 09000327 0x9000327 - 97de: 0000 unimp - 97e0: 0001 nop - 97e2: 0402 c.slli64 s0 - 97e4: 09000327 0x9000327 - 97e8: 0000 unimp - 97ea: 0001 nop - 97ec: 0402 c.slli64 s0 - 97ee: 0322 slli t1,t1,0x8 - 97f0: 0900 addi s0,sp,144 - 97f2: 0010 0x10 - 97f4: 0001 nop - 97f6: 0402 c.slli64 s0 - 97f8: 0322 slli t1,t1,0x8 - 97fa: 0900 addi s0,sp,144 - 97fc: 0020 addi s0,sp,8 - 97fe: 0001 nop - 9800: 0402 c.slli64 s0 - 9802: 0302 c.slli64 t1 - 9804: 0900 addi s0,sp,144 - 9806: 0008 0x8 - 9808: 0001 nop - 980a: 0402 c.slli64 s0 - 980c: 0341 addi t1,t1,16 + 9768: 0326 slli t1,t1,0x9 + 976a: 0900 addi s0,sp,144 + 976c: 000c 0xc + 976e: 0001 nop + 9770: 0402 c.slli64 s0 + 9772: 0326 slli t1,t1,0x9 + 9774: 0900 addi s0,sp,144 + 9776: 0004 0x4 + 9778: 0001 nop + 977a: 0402 c.slli64 s0 + 977c: 09000327 0x9000327 + 9780: 0004 0x4 + 9782: 0001 nop + 9784: 0402 c.slli64 s0 + 9786: 09000327 0x9000327 + 978a: 0000 unimp + 978c: 0001 nop + 978e: 0402 c.slli64 s0 + 9790: 09000327 0x9000327 + 9794: 0000 unimp + 9796: 0001 nop + 9798: 0402 c.slli64 s0 + 979a: 0322 slli t1,t1,0x8 + 979c: 0900 addi s0,sp,144 + 979e: 0010 0x10 + 97a0: 0001 nop + 97a2: 0402 c.slli64 s0 + 97a4: 0322 slli t1,t1,0x8 + 97a6: 0900 addi s0,sp,144 + 97a8: 0020 addi s0,sp,8 + 97aa: 0001 nop + 97ac: 0402 c.slli64 s0 + 97ae: 0302 c.slli64 t1 + 97b0: 0900 addi s0,sp,144 + 97b2: 0008 0x8 + 97b4: 0001 nop + 97b6: 0402 c.slli64 s0 + 97b8: 0341 addi t1,t1,16 + 97ba: 0900 addi s0,sp,144 + 97bc: 001c 0x1c + 97be: 0001 nop + 97c0: 0402 c.slli64 s0 + 97c2: 0341 addi t1,t1,16 + 97c4: 0900 addi s0,sp,144 + 97c6: 0000 unimp + 97c8: 0001 nop + 97ca: 0402 c.slli64 s0 + 97cc: 0341 addi t1,t1,16 + 97ce: 0900 addi s0,sp,144 + 97d0: 0000 unimp + 97d2: 0001 nop + 97d4: 0402 c.slli64 s0 + 97d6: 0341 addi t1,t1,16 + 97d8: 0900 addi s0,sp,144 + 97da: 0000 unimp + 97dc: 0001 nop + 97de: 0402 c.slli64 s0 + 97e0: 0341 addi t1,t1,16 + 97e2: 0900 addi s0,sp,144 + 97e4: 0000 unimp + 97e6: 0001 nop + 97e8: 0402 c.slli64 s0 + 97ea: 033e slli t1,t1,0xf + 97ec: 0900 addi s0,sp,144 + 97ee: 000c 0xc + 97f0: 0001 nop + 97f2: 0402 c.slli64 s0 + 97f4: 033e slli t1,t1,0xf + 97f6: 0900 addi s0,sp,144 + 97f8: 0000 unimp + 97fa: 0301 addi t1,t1,0 + 97fc: 0900 addi s0,sp,144 + 97fe: 0004 0x4 + 9800: 0301 addi t1,t1,0 + 9802: 0900 addi s0,sp,144 + 9804: 0000 unimp + 9806: 0301 addi t1,t1,0 + 9808: 0900 addi s0,sp,144 + 980a: 0000 unimp + 980c: 0301 addi t1,t1,0 980e: 0900 addi s0,sp,144 - 9810: 001c 0x1c - 9812: 0001 nop - 9814: 0402 c.slli64 s0 - 9816: 0341 addi t1,t1,16 - 9818: 0900 addi s0,sp,144 - 981a: 0000 unimp - 981c: 0001 nop - 981e: 0402 c.slli64 s0 - 9820: 0341 addi t1,t1,16 - 9822: 0900 addi s0,sp,144 - 9824: 0000 unimp - 9826: 0001 nop - 9828: 0402 c.slli64 s0 - 982a: 0341 addi t1,t1,16 + 9810: 0000 unimp + 9812: 0301 addi t1,t1,0 + 9814: 0900 addi s0,sp,144 + 9816: 0000 unimp + 9818: 0301 addi t1,t1,0 + 981a: 0900 addi s0,sp,144 + 981c: 0000 unimp + 981e: 0301 addi t1,t1,0 + 9820: 0900 addi s0,sp,144 + 9822: 0000 unimp + 9824: 0301 addi t1,t1,0 + 9826: 0900 addi s0,sp,144 + 9828: 0000 unimp + 982a: 0301 addi t1,t1,0 982c: 0900 addi s0,sp,144 982e: 0000 unimp - 9830: 0001 nop - 9832: 0402 c.slli64 s0 - 9834: 0341 addi t1,t1,16 - 9836: 0900 addi s0,sp,144 - 9838: 0000 unimp - 983a: 0001 nop - 983c: 0402 c.slli64 s0 - 983e: 033e slli t1,t1,0xf - 9840: 0900 addi s0,sp,144 - 9842: 000c 0xc - 9844: 0001 nop - 9846: 0402 c.slli64 s0 - 9848: 033e slli t1,t1,0xf + 9830: 0301 addi t1,t1,0 + 9832: 0900 addi s0,sp,144 + 9834: 0000 unimp + 9836: 0301 addi t1,t1,0 + 9838: 0900 addi s0,sp,144 + 983a: 0000 unimp + 983c: 0301 addi t1,t1,0 + 983e: 0900 addi s0,sp,144 + 9840: 0000 unimp + 9842: 0301 addi t1,t1,0 + 9844: 0900 addi s0,sp,144 + 9846: 0000 unimp + 9848: 0301 addi t1,t1,0 984a: 0900 addi s0,sp,144 984c: 0000 unimp 984e: 0301 addi t1,t1,0 9850: 0900 addi s0,sp,144 - 9852: 0004 0x4 + 9852: 0000 unimp 9854: 0301 addi t1,t1,0 9856: 0900 addi s0,sp,144 - 9858: 0000 unimp + 9858: 0024 addi s1,sp,8 985a: 0301 addi t1,t1,0 985c: 0900 addi s0,sp,144 985e: 0000 unimp 9860: 0301 addi t1,t1,0 9862: 0900 addi s0,sp,144 9864: 0000 unimp - 9866: 0301 addi t1,t1,0 - 9868: 0900 addi s0,sp,144 - 986a: 0000 unimp - 986c: 0301 addi t1,t1,0 - 986e: 0900 addi s0,sp,144 - 9870: 0000 unimp - 9872: 0301 addi t1,t1,0 - 9874: 0900 addi s0,sp,144 - 9876: 0000 unimp - 9878: 0301 addi t1,t1,0 - 987a: 0900 addi s0,sp,144 - 987c: 0000 unimp - 987e: 0301 addi t1,t1,0 - 9880: 0900 addi s0,sp,144 + 9866: 0001 nop + 9868: 0402 c.slli64 s0 + 986a: 0904032f 0x904032f + 986e: 0014 0x14 + 9870: 0001 nop + 9872: 0402 c.slli64 s0 + 9874: 0900032f 0x900032f + 9878: 0000 unimp + 987a: 0001 nop + 987c: 0402 c.slli64 s0 + 987e: 0900032f 0x900032f 9882: 0000 unimp - 9884: 0301 addi t1,t1,0 - 9886: 0900 addi s0,sp,144 - 9888: 0000 unimp - 988a: 0301 addi t1,t1,0 - 988c: 0900 addi s0,sp,144 - 988e: 0000 unimp - 9890: 0301 addi t1,t1,0 - 9892: 0900 addi s0,sp,144 - 9894: 0000 unimp - 9896: 0301 addi t1,t1,0 - 9898: 0900 addi s0,sp,144 - 989a: 0000 unimp - 989c: 0301 addi t1,t1,0 - 989e: 0900 addi s0,sp,144 - 98a0: 0000 unimp - 98a2: 0301 addi t1,t1,0 - 98a4: 0900 addi s0,sp,144 - 98a6: 0000 unimp - 98a8: 0301 addi t1,t1,0 - 98aa: 0900 addi s0,sp,144 - 98ac: 0024 addi s1,sp,8 - 98ae: 0301 addi t1,t1,0 + 9884: 0001 nop + 9886: 0402 c.slli64 s0 + 9888: 0900033f 00010008 0x100080900033f + 9890: 0402 c.slli64 s0 + 9892: 0900033f 00010000 0x100000900033f + 989a: 0402 c.slli64 s0 + 989c: 0900033f 06010004 0x60100040900033f + 98a4: 08090003 lb zero,128(s2) + 98a8: 0100 addi s0,sp,128 + 98aa: 0200 addi s0,sp,256 + 98ac: 4f04 lw s1,24(a4) + 98ae: 0306 slli t1,t1,0x1 98b0: 0900 addi s0,sp,144 - 98b2: 0000 unimp - 98b4: 0301 addi t1,t1,0 - 98b6: 0900 addi s0,sp,144 - 98b8: 0000 unimp - 98ba: 0001 nop - 98bc: 0402 c.slli64 s0 - 98be: 0904032f 0x904032f - 98c2: 0014 0x14 - 98c4: 0001 nop - 98c6: 0402 c.slli64 s0 - 98c8: 0900032f 0x900032f - 98cc: 0000 unimp - 98ce: 0001 nop - 98d0: 0402 c.slli64 s0 - 98d2: 0900032f 0x900032f - 98d6: 0000 unimp - 98d8: 0001 nop - 98da: 0402 c.slli64 s0 - 98dc: 0900033f 00010008 0x100080900033f - 98e4: 0402 c.slli64 s0 - 98e6: 0900033f 00010000 0x100000900033f - 98ee: 0402 c.slli64 s0 - 98f0: 0900033f 06010004 0x60100040900033f - 98f8: 08090003 lb zero,128(s2) - 98fc: 0100 addi s0,sp,128 - 98fe: 0200 addi s0,sp,256 - 9900: 4f04 lw s1,24(a4) - 9902: 0306 slli t1,t1,0x1 - 9904: 0900 addi s0,sp,144 - 9906: 000c 0xc - 9908: 0001 nop - 990a: 0402 c.slli64 s0 - 990c: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 9910: 0000 unimp - 9912: 0001 nop - 9914: 0402 c.slli64 s0 - 9916: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 991a: 0000 unimp - 991c: 0001 nop - 991e: 0402 c.slli64 s0 - 9920: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 9924: 000c 0xc - 9926: 0001 nop - 9928: 0402 c.slli64 s0 - 992a: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne - 992e: 0008 0x8 - 9930: 0001 nop - 9932: 0402 c.slli64 s0 - 9934: 0650 addi a2,sp,772 - 9936: 04090003 lb zero,64(s2) - 993a: 0100 addi s0,sp,128 - 993c: 0c090003 lb zero,192(s2) - 9940: 0100 addi s0,sp,128 - 9942: 0200 addi s0,sp,256 - 9944: 5a04 lw s1,48(a2) - 9946: 0306 slli t1,t1,0x1 - 9948: 0900 addi s0,sp,144 - 994a: 000c 0xc - 994c: 0001 nop - 994e: 0402 c.slli64 s0 - 9950: 035a slli t1,t1,0x16 - 9952: 0900 addi s0,sp,144 - 9954: 0000 unimp - 9956: 0001 nop - 9958: 0402 c.slli64 s0 - 995a: 035a slli t1,t1,0x16 - 995c: 0900 addi s0,sp,144 - 995e: 0000 unimp - 9960: 0001 nop - 9962: 0402 c.slli64 s0 - 9964: 035a slli t1,t1,0x16 - 9966: 0900 addi s0,sp,144 - 9968: 0000 unimp - 996a: 0001 nop - 996c: 0402 c.slli64 s0 - 996e: 035a slli t1,t1,0x16 - 9970: 0900 addi s0,sp,144 - 9972: 0000 unimp - 9974: 0001 nop - 9976: 0402 c.slli64 s0 - 9978: 035a slli t1,t1,0x16 - 997a: 0900 addi s0,sp,144 - 997c: 0000 unimp - 997e: 0001 nop - 9980: 0402 c.slli64 s0 - 9982: 035a slli t1,t1,0x16 - 9984: 0900 addi s0,sp,144 - 9986: 0000 unimp - 9988: 0001 nop - 998a: 0402 c.slli64 s0 - 998c: 035a slli t1,t1,0x16 - 998e: 0900 addi s0,sp,144 - 9990: 0000 unimp - 9992: 0001 nop - 9994: 0402 c.slli64 s0 - 9996: 035a slli t1,t1,0x16 - 9998: 0900 addi s0,sp,144 - 999a: 0000 unimp - 999c: 0001 nop - 999e: 0402 c.slli64 s0 - 99a0: 035a slli t1,t1,0x16 - 99a2: 0900 addi s0,sp,144 - 99a4: 0020 addi s0,sp,8 - 99a6: 0001 nop - 99a8: 0402 c.slli64 s0 - 99aa: 035a slli t1,t1,0x16 - 99ac: 0900 addi s0,sp,144 - 99ae: 0000 unimp - 99b0: 0001 nop - 99b2: 0402 c.slli64 s0 - 99b4: 035a slli t1,t1,0x16 - 99b6: 0901 addi s2,s2,0 - 99b8: 0000 unimp - 99ba: 0001 nop - 99bc: 0402 c.slli64 s0 - 99be: 035a slli t1,t1,0x16 - 99c0: 0900 addi s0,sp,144 - 99c2: 0000 unimp - 99c4: 0001 nop - 99c6: 0402 c.slli64 s0 - 99c8: 035a slli t1,t1,0x16 - 99ca: 0900 addi s0,sp,144 - 99cc: 0000 unimp - 99ce: 0001 nop - 99d0: 0402 c.slli64 s0 - 99d2: 035a slli t1,t1,0x16 - 99d4: 0902 c.slli64 s2 - 99d6: 0000 unimp - 99d8: 0501 addi a0,a0,0 - 99da: 0001 nop - 99dc: 0402 c.slli64 s0 - 99de: 065a slli a2,a2,0x16 - 99e0: 00090103 lb sp,0(s2) - 99e4: 0100 addi s0,sp,128 - 99e6: 2409 jal 9be8 <_start-0x7fff6418> - 99e8: 0000 unimp - 99ea: 0101 addi sp,sp,0 - 99ec: 022d addi tp,tp,11 - 99ee: 0000 unimp - 99f0: 02270003 lb zero,34(a4) - 99f4: 0000 unimp - 99f6: 0101 addi sp,sp,0 - 99f8: 000d0efb 0xd0efb - 99fc: 0101 addi sp,sp,0 - 99fe: 0101 addi sp,sp,0 - 9a00: 0000 unimp - 9a02: 0100 addi s0,sp,128 - 9a04: 0000 unimp - 9a06: 2f01 jal a116 <_start-0x7fff5eea> - 9a08: 6f68 flw fa0,92(a4) - 9a0a: 656d lui a0,0x1b - 9a0c: 7261662f 0x7261662f - 9a10: 7365 lui t1,0xffff9 - 9a12: 636f442f 0x636f442f - 9a16: 6d75 lui s10,0x1d - 9a18: 6e65 lui t3,0x19 - 9a1a: 7374 flw fa3,100(a4) - 9a1c: 636f702f 0x636f702f - 9a20: 5f6c lw a1,124(a4) - 9a22: 6564 flw fs1,76(a0) - 9a24: 2f70 fld fa2,216(a4) - 9a26: 6972 flw fs2,28(sp) - 9a28: 2d766373 csrrsi t1,0x2d7,12 - 9a2c: 2d756e67 0x2d756e67 - 9a30: 6f74 flw fa3,92(a4) - 9a32: 68636c6f jal s8,400b8 <_start-0x7ffbff48> - 9a36: 6961 lui s2,0x18 - 9a38: 2f6e fld ft10,216(sp) - 9a3a: 7562 flw fa0,56(sp) - 9a3c: 6c69 lui s8,0x1a - 9a3e: 2f64 fld fs1,216(a4) - 9a40: 7562 flw fa0,56(sp) - 9a42: 6c69 lui s8,0x1a - 9a44: 2d64 fld fs1,216(a0) - 9a46: 2d636367 0x2d636367 - 9a4a: 656e flw fa0,216(sp) - 9a4c: 62696c77 0x62696c77 - 9a50: 732d lui t1,0xfffeb - 9a52: 6174 flw fa3,68(a0) - 9a54: 2f326567 0x2f326567 - 9a58: 2f636367 0x2f636367 - 9a5c: 6e69 lui t3,0x1a - 9a5e: 64756c63 bltu a0,t2,a0b6 <_start-0x7fff5f4a> - 9a62: 0065 c.nop 25 - 9a64: 6d6f682f 0x6d6f682f - 9a68: 2f65 jal a220 <_start-0x7fff5de0> - 9a6a: 6166 flw ft2,88(sp) - 9a6c: 6572 flw fa0,28(sp) - 9a6e: 65642f73 csrrs t5,0x656,s0 - 9a72: 2f76 fld ft10,344(sp) - 9a74: 6972 flw fs2,28(sp) - 9a76: 2d766373 csrrsi t1,0x2d7,12 - 9a7a: 2d756e67 0x2d756e67 - 9a7e: 6f74 flw fa3,92(a4) - 9a80: 68636c6f jal s8,40106 <_start-0x7ffbfefa> - 9a84: 6961 lui s2,0x18 - 9a86: 2f6e fld ft10,216(sp) - 9a88: 7264 flw fs1,100(a2) - 9a8a: 2f73706f j 41580 <_start-0x7ffbea80> - 9a8e: 6972 flw fs2,28(sp) - 9a90: 33766373 csrrsi t1,mhpmevent23,12 - 9a94: 2d32 fld fs10,264(sp) - 9a96: 6e75 lui t3,0x1d - 9a98: 776f6e6b 0x776f6e6b - 9a9c: 2d6e fld fs10,216(sp) - 9a9e: 6c65 lui s8,0x19 - 9aa0: 2f66 fld ft10,88(sp) - 9aa2: 6e69 lui t3,0x1a - 9aa4: 64756c63 bltu a0,t2,a0fc <_start-0x7fff5f04> - 9aa8: 2f65 jal a260 <_start-0x7fff5da0> - 9aaa: 00737973 csrrci s2,0x7,6 - 9aae: 6d6f682f 0x6d6f682f - 9ab2: 2f65 jal a26a <_start-0x7fff5d96> - 9ab4: 6166 flw ft2,88(sp) - 9ab6: 6572 flw fa0,28(sp) - 9ab8: 65642f73 csrrs t5,0x656,s0 - 9abc: 2f76 fld ft10,344(sp) - 9abe: 6972 flw fs2,28(sp) - 9ac0: 2d766373 csrrsi t1,0x2d7,12 - 9ac4: 2d756e67 0x2d756e67 - 9ac8: 6f74 flw fa3,92(a4) - 9aca: 68636c6f jal s8,40150 <_start-0x7ffbfeb0> - 9ace: 6961 lui s2,0x18 - 9ad0: 2f6e fld ft10,216(sp) - 9ad2: 7264 flw fs1,100(a2) - 9ad4: 2f73706f j 415ca <_start-0x7ffbea36> - 9ad8: 6972 flw fs2,28(sp) - 9ada: 33766373 csrrsi t1,mhpmevent23,12 - 9ade: 2d32 fld fs10,264(sp) - 9ae0: 6e75 lui t3,0x1d - 9ae2: 776f6e6b 0x776f6e6b - 9ae6: 2d6e fld fs10,216(sp) - 9ae8: 6c65 lui s8,0x19 - 9aea: 2f66 fld ft10,88(sp) - 9aec: 6e69 lui t3,0x1a - 9aee: 64756c63 bltu a0,t2,a146 <_start-0x7fff5eba> - 9af2: 0065 c.nop 25 - 9af4: 2e2e fld ft8,200(sp) - 9af6: 2f2e2e2f 0x2f2e2e2f - 9afa: 2e2e fld ft8,200(sp) - 9afc: 2f2e2e2f 0x2f2e2e2f - 9b00: 6972 flw fs2,28(sp) - 9b02: 2d766373 csrrsi t1,0x2d7,12 - 9b06: 2f636367 0x2f636367 - 9b0a: 696c flw fa1,84(a0) - 9b0c: 6762 flw fa4,24(sp) - 9b0e: 2e2f6363 bltu t5,sp,9df4 <_start-0x7fff620c> - 9b12: 2f2e fld ft10,200(sp) - 9b14: 6e69 lui t3,0x1a - 9b16: 64756c63 bltu a0,t2,a16e <_start-0x7fff5e92> - 9b1a: 0065 c.nop 25 - 9b1c: 2e2e fld ft8,200(sp) - 9b1e: 2f2e2e2f 0x2f2e2e2f - 9b22: 2e2e fld ft8,200(sp) - 9b24: 2f2e2e2f 0x2f2e2e2f - 9b28: 6972 flw fs2,28(sp) - 9b2a: 2d766373 csrrsi t1,0x2d7,12 - 9b2e: 2f636367 0x2f636367 - 9b32: 696c flw fa1,84(a0) - 9b34: 6762 flw fa4,24(sp) - 9b36: 2e2f6363 bltu t5,sp,9e1c <_start-0x7fff61e4> - 9b3a: 2f2e fld ft10,200(sp) - 9b3c: 2f636367 0x2f636367 - 9b40: 666e6f63 bltu t3,t1,a1be <_start-0x7fff5e42> - 9b44: 6769 lui a4,0x1a - 9b46: 7369722f 0x7369722f - 9b4a: 2e007663 bgeu zero,zero,9e36 <_start-0x7fff61ca> - 9b4e: 2f2e fld ft10,200(sp) - 9b50: 2e2e fld ft8,200(sp) - 9b52: 672f2e2f amoand.w.aqrl t3,s2,(t5) - 9b56: 2e006363 bltu zero,zero,9e3c <_start-0x7fff61c4> - 9b5a: 2f2e fld ft10,200(sp) - 9b5c: 2e2e fld ft8,200(sp) - 9b5e: 2f2e2e2f 0x2f2e2e2f - 9b62: 2e2e fld ft8,200(sp) - 9b64: 7369722f 0x7369722f - 9b68: 672d7663 bgeu s10,s2,a1d4 <_start-0x7fff5e2c> - 9b6c: 6c2f6363 bltu t5,sp,a232 <_start-0x7fff5dce> - 9b70: 6269 lui tp,0x1a - 9b72: 00636367 0x636367 - 9b76: 7300 flw fs0,32(a4) - 9b78: 6474 flw fa3,76(s0) - 9b7a: 6564 flw fs1,76(a0) - 9b7c: 2e66 fld ft8,88(sp) - 9b7e: 0068 addi a0,sp,12 - 9b80: 0001 nop - 9b82: 5f00 lw s0,56(a4) - 9b84: 7974 flw fa3,116(a0) - 9b86: 6570 flw fa2,76(a0) - 9b88: 00682e73 csrrs t3,0x6,a6 - 9b8c: 0002 c.slli64 zero - 9b8e: 7200 flw fs0,32(a2) - 9b90: 6565 lui a0,0x19 - 9b92: 746e flw fs0,248(sp) - 9b94: 682e flw fa6,200(sp) - 9b96: 0200 addi s0,sp,256 - 9b98: 0000 unimp - 9b9a: 6f6c flw fa1,92(a4) - 9b9c: 682e6b63 bltu t3,sp,a232 <_start-0x7fff5dce> - 9ba0: 0200 addi s0,sp,256 - 9ba2: 0000 unimp - 9ba4: 7265 lui tp,0xffff9 - 9ba6: 6e72 flw ft8,28(sp) - 9ba8: 00682e6f jal t3,8bbae <_start-0x7ff74452> - 9bac: 0002 c.slli64 zero - 9bae: 7300 flw fs0,32(a4) - 9bb0: 6474 flw fa3,76(s0) - 9bb2: 696c flw fa1,84(a0) - 9bb4: 2e62 fld ft8,24(sp) - 9bb6: 0068 addi a0,sp,12 - 9bb8: 75000003 lb zero,1872(zero) # 750 <_start-0x7ffff8b0> - 9bbc: 696e flw fs2,216(sp) - 9bbe: 2e647473 csrrci s0,0x2e6,8 - 9bc2: 0068 addi a0,sp,12 - 9bc4: 0002 c.slli64 zero - 9bc6: 7400 flw fs0,40(s0) - 9bc8: 6d69 lui s10,0x1a - 9bca: 2e65 jal 9f82 <_start-0x7fff607e> - 9bcc: 0068 addi a0,sp,12 - 9bce: 68000003 lb zero,1664(zero) # 680 <_start-0x7ffff980> - 9bd2: 7361 lui t1,0xffff8 - 9bd4: 7468 flw fa0,108(s0) - 9bd6: 6261 lui tp,0x18 - 9bd8: 682e flw fa6,200(sp) - 9bda: 0400 addi s0,sp,512 - 9bdc: 0000 unimp - 9bde: 6972 flw fs2,28(sp) - 9be0: 2d766373 csrrsi t1,0x2d7,12 - 9be4: 7374706f j 51b1a <_start-0x7ffae4e6> - 9be8: 682e flw fa6,200(sp) - 9bea: 0500 addi s0,sp,640 - 9bec: 0000 unimp - 9bee: 6e69 lui t3,0x1a - 9bf0: 632d6e73 csrrsi t3,0x632,26 - 9bf4: 74736e6f jal t3,40b3a <_start-0x7ffbf4c6> - 9bf8: 6e61 lui t3,0x18 - 9bfa: 7374 flw fa3,100(a4) - 9bfc: 682e flw fa6,200(sp) - 9bfe: 0600 addi s0,sp,768 - 9c00: 0000 unimp - 9c02: 696c flw fa1,84(a0) - 9c04: 6762 flw fa4,24(sp) - 9c06: 2e326363 bltu tp,gp,9eec <_start-0x7fff6114> - 9c0a: 0068 addi a0,sp,12 - 9c0c: 6c000007 0x6c000007 - 9c10: 6269 lui tp,0x1a - 9c12: 32636367 0x32636367 - 9c16: 632e flw ft6,200(sp) - 9c18: 0700 addi s0,sp,896 - 9c1a: 0000 unimp - 9c1c: b900 fsd fs0,48(a0) - 9c1e: 0002 c.slli64 zero - 9c20: 0300 addi s0,sp,384 - 9c22: 2700 fld fs0,8(a4) - 9c24: 0002 c.slli64 zero - 9c26: 0100 addi s0,sp,128 - 9c28: fb01 bnez a4,9b38 <_start-0x7fff64c8> - 9c2a: 0d0e slli s10,s10,0x3 - 9c2c: 0100 addi s0,sp,128 - 9c2e: 0101 addi sp,sp,0 - 9c30: 0001 nop - 9c32: 0000 unimp - 9c34: 0001 nop - 9c36: 0100 addi s0,sp,128 - 9c38: 2e2e fld ft8,200(sp) - 9c3a: 2f2e2e2f 0x2f2e2e2f - 9c3e: 2e2e fld ft8,200(sp) - 9c40: 2f2e2e2f 0x2f2e2e2f - 9c44: 6972 flw fs2,28(sp) - 9c46: 2d766373 csrrsi t1,0x2d7,12 - 9c4a: 2f636367 0x2f636367 - 9c4e: 696c flw fa1,84(a0) - 9c50: 6762 flw fa4,24(sp) - 9c52: 2f006363 bltu zero,a6,9f38 <_start-0x7fff60c8> - 9c56: 6f68 flw fa0,92(a4) - 9c58: 656d lui a0,0x1b - 9c5a: 7261662f 0x7261662f - 9c5e: 7365 lui t1,0xffff9 - 9c60: 636f442f 0x636f442f - 9c64: 6d75 lui s10,0x1d - 9c66: 6e65 lui t3,0x19 - 9c68: 7374 flw fa3,100(a4) - 9c6a: 636f702f 0x636f702f - 9c6e: 5f6c lw a1,124(a4) - 9c70: 6564 flw fs1,76(a0) - 9c72: 2f70 fld fa2,216(a4) - 9c74: 6972 flw fs2,28(sp) - 9c76: 2d766373 csrrsi t1,0x2d7,12 - 9c7a: 2d756e67 0x2d756e67 - 9c7e: 6f74 flw fa3,92(a4) - 9c80: 68636c6f jal s8,40306 <_start-0x7ffbfcfa> - 9c84: 6961 lui s2,0x18 - 9c86: 2f6e fld ft10,216(sp) - 9c88: 7562 flw fa0,56(sp) - 9c8a: 6c69 lui s8,0x1a - 9c8c: 2f64 fld fs1,216(a4) - 9c8e: 7562 flw fa0,56(sp) - 9c90: 6c69 lui s8,0x1a - 9c92: 2d64 fld fs1,216(a0) - 9c94: 2d636367 0x2d636367 - 9c98: 656e flw fa0,216(sp) - 9c9a: 62696c77 0x62696c77 - 9c9e: 732d lui t1,0xfffeb - 9ca0: 6174 flw fa3,68(a0) - 9ca2: 2f326567 0x2f326567 - 9ca6: 2f636367 0x2f636367 - 9caa: 6e69 lui t3,0x1a - 9cac: 64756c63 bltu a0,t2,a304 <_start-0x7fff5cfc> - 9cb0: 0065 c.nop 25 - 9cb2: 6d6f682f 0x6d6f682f - 9cb6: 2f65 jal a46e <_start-0x7fff5b92> - 9cb8: 6166 flw ft2,88(sp) - 9cba: 6572 flw fa0,28(sp) - 9cbc: 65642f73 csrrs t5,0x656,s0 - 9cc0: 2f76 fld ft10,344(sp) - 9cc2: 6972 flw fs2,28(sp) - 9cc4: 2d766373 csrrsi t1,0x2d7,12 - 9cc8: 2d756e67 0x2d756e67 - 9ccc: 6f74 flw fa3,92(a4) - 9cce: 68636c6f jal s8,40354 <_start-0x7ffbfcac> - 9cd2: 6961 lui s2,0x18 - 9cd4: 2f6e fld ft10,216(sp) - 9cd6: 7264 flw fs1,100(a2) - 9cd8: 2f73706f j 417ce <_start-0x7ffbe832> - 9cdc: 6972 flw fs2,28(sp) - 9cde: 33766373 csrrsi t1,mhpmevent23,12 - 9ce2: 2d32 fld fs10,264(sp) - 9ce4: 6e75 lui t3,0x1d - 9ce6: 776f6e6b 0x776f6e6b - 9cea: 2d6e fld fs10,216(sp) - 9cec: 6c65 lui s8,0x19 - 9cee: 2f66 fld ft10,88(sp) - 9cf0: 6e69 lui t3,0x1a - 9cf2: 64756c63 bltu a0,t2,a34a <_start-0x7fff5cb6> - 9cf6: 2f65 jal a4ae <_start-0x7fff5b52> - 9cf8: 00737973 csrrci s2,0x7,6 - 9cfc: 6d6f682f 0x6d6f682f - 9d00: 2f65 jal a4b8 <_start-0x7fff5b48> - 9d02: 6166 flw ft2,88(sp) - 9d04: 6572 flw fa0,28(sp) - 9d06: 65642f73 csrrs t5,0x656,s0 - 9d0a: 2f76 fld ft10,344(sp) - 9d0c: 6972 flw fs2,28(sp) - 9d0e: 2d766373 csrrsi t1,0x2d7,12 - 9d12: 2d756e67 0x2d756e67 - 9d16: 6f74 flw fa3,92(a4) - 9d18: 68636c6f jal s8,4039e <_start-0x7ffbfc62> - 9d1c: 6961 lui s2,0x18 - 9d1e: 2f6e fld ft10,216(sp) - 9d20: 7264 flw fs1,100(a2) - 9d22: 2f73706f j 41818 <_start-0x7ffbe7e8> - 9d26: 6972 flw fs2,28(sp) - 9d28: 33766373 csrrsi t1,mhpmevent23,12 - 9d2c: 2d32 fld fs10,264(sp) - 9d2e: 6e75 lui t3,0x1d - 9d30: 776f6e6b 0x776f6e6b - 9d34: 2d6e fld fs10,216(sp) - 9d36: 6c65 lui s8,0x19 - 9d38: 2f66 fld ft10,88(sp) - 9d3a: 6e69 lui t3,0x1a - 9d3c: 64756c63 bltu a0,t2,a394 <_start-0x7fff5c6c> - 9d40: 0065 c.nop 25 - 9d42: 2e2e fld ft8,200(sp) - 9d44: 2f2e2e2f 0x2f2e2e2f - 9d48: 2e2e fld ft8,200(sp) - 9d4a: 2f2e2e2f 0x2f2e2e2f - 9d4e: 6972 flw fs2,28(sp) - 9d50: 2d766373 csrrsi t1,0x2d7,12 - 9d54: 2f636367 0x2f636367 - 9d58: 696c flw fa1,84(a0) - 9d5a: 6762 flw fa4,24(sp) - 9d5c: 2e2f6363 bltu t5,sp,a042 <_start-0x7fff5fbe> - 9d60: 2f2e fld ft10,200(sp) - 9d62: 6e69 lui t3,0x1a - 9d64: 64756c63 bltu a0,t2,a3bc <_start-0x7fff5c44> - 9d68: 0065 c.nop 25 - 9d6a: 2e2e fld ft8,200(sp) - 9d6c: 2f2e2e2f 0x2f2e2e2f - 9d70: 2e2e fld ft8,200(sp) - 9d72: 2f2e2e2f 0x2f2e2e2f - 9d76: 6972 flw fs2,28(sp) - 9d78: 2d766373 csrrsi t1,0x2d7,12 - 9d7c: 2f636367 0x2f636367 - 9d80: 696c flw fa1,84(a0) - 9d82: 6762 flw fa4,24(sp) - 9d84: 2e2f6363 bltu t5,sp,a06a <_start-0x7fff5f96> - 9d88: 2f2e fld ft10,200(sp) - 9d8a: 2f636367 0x2f636367 - 9d8e: 666e6f63 bltu t3,t1,a40c <_start-0x7fff5bf4> - 9d92: 6769 lui a4,0x1a - 9d94: 7369722f 0x7369722f - 9d98: 2e007663 bgeu zero,zero,a084 <_start-0x7fff5f7c> - 9d9c: 2f2e fld ft10,200(sp) - 9d9e: 2e2e fld ft8,200(sp) - 9da0: 672f2e2f amoand.w.aqrl t3,s2,(t5) - 9da4: 00006363 bltu zero,zero,9daa <_start-0x7fff6256> - 9da8: 696c flw fa1,84(a0) - 9daa: 6762 flw fa4,24(sp) - 9dac: 2e326363 bltu tp,gp,a092 <_start-0x7fff5f6e> - 9db0: 00010063 beqz sp,9db0 <_start-0x7fff6250> - 9db4: 7300 flw fs0,32(a4) - 9db6: 6474 flw fa3,76(s0) - 9db8: 6564 flw fs1,76(a0) - 9dba: 2e66 fld ft8,88(sp) - 9dbc: 0068 addi a0,sp,12 - 9dbe: 0002 c.slli64 zero - 9dc0: 5f00 lw s0,56(a4) - 9dc2: 7974 flw fa3,116(a0) - 9dc4: 6570 flw fa2,76(a0) - 9dc6: 00682e73 csrrs t3,0x6,a6 - 9dca: 72000003 lb zero,1824(zero) # 720 <_start-0x7ffff8e0> - 9dce: 6565 lui a0,0x19 - 9dd0: 746e flw fs0,248(sp) - 9dd2: 682e flw fa6,200(sp) - 9dd4: 0300 addi s0,sp,384 + 98b2: 000c 0xc + 98b4: 0001 nop + 98b6: 0402 c.slli64 s0 + 98b8: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne + 98bc: 0000 unimp + 98be: 0001 nop + 98c0: 0402 c.slli64 s0 + 98c2: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne + 98c6: 0000 unimp + 98c8: 0001 nop + 98ca: 0402 c.slli64 s0 + 98cc: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne + 98d0: 000c 0xc + 98d2: 0001 nop + 98d4: 0402 c.slli64 s0 + 98d6: 0900034f fnmadd.s ft6,ft0,fa6,ft1,rne + 98da: 0008 0x8 + 98dc: 0001 nop + 98de: 0402 c.slli64 s0 + 98e0: 0650 addi a2,sp,772 + 98e2: 04090003 lb zero,64(s2) + 98e6: 0100 addi s0,sp,128 + 98e8: 0c090003 lb zero,192(s2) + 98ec: 0100 addi s0,sp,128 + 98ee: 0200 addi s0,sp,256 + 98f0: 5a04 lw s1,48(a2) + 98f2: 0306 slli t1,t1,0x1 + 98f4: 0900 addi s0,sp,144 + 98f6: 000c 0xc + 98f8: 0001 nop + 98fa: 0402 c.slli64 s0 + 98fc: 035a slli t1,t1,0x16 + 98fe: 0900 addi s0,sp,144 + 9900: 0000 unimp + 9902: 0001 nop + 9904: 0402 c.slli64 s0 + 9906: 035a slli t1,t1,0x16 + 9908: 0900 addi s0,sp,144 + 990a: 0000 unimp + 990c: 0001 nop + 990e: 0402 c.slli64 s0 + 9910: 035a slli t1,t1,0x16 + 9912: 0900 addi s0,sp,144 + 9914: 0000 unimp + 9916: 0001 nop + 9918: 0402 c.slli64 s0 + 991a: 035a slli t1,t1,0x16 + 991c: 0900 addi s0,sp,144 + 991e: 0000 unimp + 9920: 0001 nop + 9922: 0402 c.slli64 s0 + 9924: 035a slli t1,t1,0x16 + 9926: 0900 addi s0,sp,144 + 9928: 0000 unimp + 992a: 0001 nop + 992c: 0402 c.slli64 s0 + 992e: 035a slli t1,t1,0x16 + 9930: 0900 addi s0,sp,144 + 9932: 0000 unimp + 9934: 0001 nop + 9936: 0402 c.slli64 s0 + 9938: 035a slli t1,t1,0x16 + 993a: 0900 addi s0,sp,144 + 993c: 0000 unimp + 993e: 0001 nop + 9940: 0402 c.slli64 s0 + 9942: 035a slli t1,t1,0x16 + 9944: 0900 addi s0,sp,144 + 9946: 0000 unimp + 9948: 0001 nop + 994a: 0402 c.slli64 s0 + 994c: 035a slli t1,t1,0x16 + 994e: 0900 addi s0,sp,144 + 9950: 0020 addi s0,sp,8 + 9952: 0001 nop + 9954: 0402 c.slli64 s0 + 9956: 035a slli t1,t1,0x16 + 9958: 0900 addi s0,sp,144 + 995a: 0000 unimp + 995c: 0001 nop + 995e: 0402 c.slli64 s0 + 9960: 035a slli t1,t1,0x16 + 9962: 0901 addi s2,s2,0 + 9964: 0000 unimp + 9966: 0001 nop + 9968: 0402 c.slli64 s0 + 996a: 035a slli t1,t1,0x16 + 996c: 0900 addi s0,sp,144 + 996e: 0000 unimp + 9970: 0001 nop + 9972: 0402 c.slli64 s0 + 9974: 035a slli t1,t1,0x16 + 9976: 0900 addi s0,sp,144 + 9978: 0000 unimp + 997a: 0001 nop + 997c: 0402 c.slli64 s0 + 997e: 035a slli t1,t1,0x16 + 9980: 0902 c.slli64 s2 + 9982: 0000 unimp + 9984: 0501 addi a0,a0,0 + 9986: 0001 nop + 9988: 0402 c.slli64 s0 + 998a: 065a slli a2,a2,0x16 + 998c: 00090103 lb sp,0(s2) + 9990: 0100 addi s0,sp,128 + 9992: 2409 jal 9b94 <_start-0x7fff646c> + 9994: 0000 unimp + 9996: 0101 addi sp,sp,0 + 9998: 00000203 lb tp,0(zero) # 0 <_start-0x80000000> + 999c: 01fd0003 lb zero,31(s10) + 99a0: 0000 unimp + 99a2: 0101 addi sp,sp,0 + 99a4: 000d0efb 0xd0efb + 99a8: 0101 addi sp,sp,0 + 99aa: 0101 addi sp,sp,0 + 99ac: 0000 unimp + 99ae: 0100 addi s0,sp,128 + 99b0: 0000 unimp + 99b2: 2f01 jal a0c2 <_start-0x7fff5f3e> + 99b4: 7355 lui t1,0xffff5 + 99b6: 7265 lui tp,0xffff9 + 99b8: 65642f73 csrrs t5,0x656,s0 + 99bc: 6f6d lui t5,0x1b + 99be: 636f442f 0x636f442f + 99c2: 6d75 lui s10,0x1d + 99c4: 6e65 lui t3,0x19 + 99c6: 7374 flw fa3,100(a4) + 99c8: 77656e2f 0x77656e2f + 99cc: 6f70 flw fa2,92(a4) + 99ce: 2f766c63 bltu a2,s7,9cc6 <_start-0x7fff633a> + 99d2: 6972 flw fs2,28(sp) + 99d4: 2d766373 csrrsi t1,0x2d7,12 + 99d8: 2d756e67 0x2d756e67 + 99dc: 6f74 flw fa3,92(a4) + 99de: 68636c6f jal s8,40064 <_start-0x7ffbff9c> + 99e2: 6961 lui s2,0x18 + 99e4: 2f6e fld ft10,216(sp) + 99e6: 7562 flw fa0,56(sp) + 99e8: 6c69 lui s8,0x1a + 99ea: 2f64 fld fs1,216(a4) + 99ec: 7562 flw fa0,56(sp) + 99ee: 6c69 lui s8,0x1a + 99f0: 2d64 fld fs1,216(a0) + 99f2: 2d636367 0x2d636367 + 99f6: 656e flw fa0,216(sp) + 99f8: 62696c77 0x62696c77 + 99fc: 732d lui t1,0xfffeb + 99fe: 6174 flw fa3,68(a0) + 9a00: 2f326567 0x2f326567 + 9a04: 2f636367 0x2f636367 + 9a08: 6e69 lui t3,0x1a + 9a0a: 64756c63 bltu a0,t2,a062 <_start-0x7fff5f9e> + 9a0e: 0065 c.nop 25 + 9a10: 74706f2f 0x74706f2f + 9a14: 7369722f 0x7369722f + 9a18: 6e2d7663 bgeu s10,sp,a104 <_start-0x7fff5efc> + 9a1c: 7765 lui a4,0xffff9 + 9a1e: 6f72642f 0x6f72642f + 9a22: 7370 flw fa2,100(a4) + 9a24: 7369722f 0x7369722f + 9a28: 32337663 bgeu t1,gp,9d54 <_start-0x7fff62ac> + 9a2c: 752d lui a0,0xfffeb + 9a2e: 6b6e flw fs6,216(sp) + 9a30: 6f6e flw ft10,216(sp) + 9a32: 652d6e77 0x652d6e77 + 9a36: 666c flw fa1,76(a2) + 9a38: 636e692f 0x636e692f + 9a3c: 756c flw fa1,108(a0) + 9a3e: 6564 flw fs1,76(a0) + 9a40: 7379732f 0x7379732f + 9a44: 2f00 fld fs0,24(a4) + 9a46: 2f74706f j 5153c <_start-0x7ffaeac4> + 9a4a: 6972 flw fs2,28(sp) + 9a4c: 2d766373 csrrsi t1,0x2d7,12 + 9a50: 656e flw fa0,216(sp) + 9a52: 72642f77 0x72642f77 + 9a56: 2f73706f j 4154c <_start-0x7ffbeab4> + 9a5a: 6972 flw fs2,28(sp) + 9a5c: 33766373 csrrsi t1,mhpmevent23,12 + 9a60: 2d32 fld fs10,264(sp) + 9a62: 6e75 lui t3,0x1d + 9a64: 776f6e6b 0x776f6e6b + 9a68: 2d6e fld fs10,216(sp) + 9a6a: 6c65 lui s8,0x19 + 9a6c: 2f66 fld ft10,88(sp) + 9a6e: 6e69 lui t3,0x1a + 9a70: 64756c63 bltu a0,t2,a0c8 <_start-0x7fff5f38> + 9a74: 0065 c.nop 25 + 9a76: 2e2e fld ft8,200(sp) + 9a78: 2f2e2e2f 0x2f2e2e2f + 9a7c: 2e2e fld ft8,200(sp) + 9a7e: 2f2e2e2f 0x2f2e2e2f + 9a82: 6972 flw fs2,28(sp) + 9a84: 2d766373 csrrsi t1,0x2d7,12 + 9a88: 2f636367 0x2f636367 + 9a8c: 696c flw fa1,84(a0) + 9a8e: 6762 flw fa4,24(sp) + 9a90: 2e2f6363 bltu t5,sp,9d76 <_start-0x7fff628a> + 9a94: 2f2e fld ft10,200(sp) + 9a96: 6e69 lui t3,0x1a + 9a98: 64756c63 bltu a0,t2,a0f0 <_start-0x7fff5f10> + 9a9c: 0065 c.nop 25 + 9a9e: 2e2e fld ft8,200(sp) + 9aa0: 2f2e2e2f 0x2f2e2e2f + 9aa4: 2e2e fld ft8,200(sp) + 9aa6: 2f2e2e2f 0x2f2e2e2f + 9aaa: 6972 flw fs2,28(sp) + 9aac: 2d766373 csrrsi t1,0x2d7,12 + 9ab0: 2f636367 0x2f636367 + 9ab4: 696c flw fa1,84(a0) + 9ab6: 6762 flw fa4,24(sp) + 9ab8: 2e2f6363 bltu t5,sp,9d9e <_start-0x7fff6262> + 9abc: 2f2e fld ft10,200(sp) + 9abe: 2f636367 0x2f636367 + 9ac2: 666e6f63 bltu t3,t1,a140 <_start-0x7fff5ec0> + 9ac6: 6769 lui a4,0x1a + 9ac8: 7369722f 0x7369722f + 9acc: 2e007663 bgeu zero,zero,9db8 <_start-0x7fff6248> + 9ad0: 2f2e fld ft10,200(sp) + 9ad2: 2e2e fld ft8,200(sp) + 9ad4: 672f2e2f amoand.w.aqrl t3,s2,(t5) + 9ad8: 2e006363 bltu zero,zero,9dbe <_start-0x7fff6242> + 9adc: 2f2e fld ft10,200(sp) + 9ade: 2e2e fld ft8,200(sp) + 9ae0: 2f2e2e2f 0x2f2e2e2f + 9ae4: 2e2e fld ft8,200(sp) + 9ae6: 7369722f 0x7369722f + 9aea: 672d7663 bgeu s10,s2,a156 <_start-0x7fff5eaa> + 9aee: 6c2f6363 bltu t5,sp,a1b4 <_start-0x7fff5e4c> + 9af2: 6269 lui tp,0x1a + 9af4: 00636367 0x636367 + 9af8: 7300 flw fs0,32(a4) + 9afa: 6474 flw fa3,76(s0) + 9afc: 6564 flw fs1,76(a0) + 9afe: 2e66 fld ft8,88(sp) + 9b00: 0068 addi a0,sp,12 + 9b02: 0001 nop + 9b04: 5f00 lw s0,56(a4) + 9b06: 7974 flw fa3,116(a0) + 9b08: 6570 flw fa2,76(a0) + 9b0a: 00682e73 csrrs t3,0x6,a6 + 9b0e: 0002 c.slli64 zero + 9b10: 7200 flw fs0,32(a2) + 9b12: 6565 lui a0,0x19 + 9b14: 746e flw fs0,248(sp) + 9b16: 682e flw fa6,200(sp) + 9b18: 0200 addi s0,sp,256 + 9b1a: 0000 unimp + 9b1c: 6f6c flw fa1,92(a4) + 9b1e: 682e6b63 bltu t3,sp,a1b4 <_start-0x7fff5e4c> + 9b22: 0200 addi s0,sp,256 + 9b24: 0000 unimp + 9b26: 7265 lui tp,0xffff9 + 9b28: 6e72 flw ft8,28(sp) + 9b2a: 00682e6f jal t3,8bb30 <_start-0x7ff744d0> + 9b2e: 0002 c.slli64 zero + 9b30: 7300 flw fs0,32(a4) + 9b32: 6474 flw fa3,76(s0) + 9b34: 696c flw fa1,84(a0) + 9b36: 2e62 fld ft8,24(sp) + 9b38: 0068 addi a0,sp,12 + 9b3a: 75000003 lb zero,1872(zero) # 750 <_start-0x7ffff8b0> + 9b3e: 696e flw fs2,216(sp) + 9b40: 2e647473 csrrci s0,0x2e6,8 + 9b44: 0068 addi a0,sp,12 + 9b46: 0002 c.slli64 zero + 9b48: 7400 flw fs0,40(s0) + 9b4a: 6d69 lui s10,0x1a + 9b4c: 2e65 jal 9f04 <_start-0x7fff60fc> + 9b4e: 0068 addi a0,sp,12 + 9b50: 68000003 lb zero,1664(zero) # 680 <_start-0x7ffff980> + 9b54: 7361 lui t1,0xffff8 + 9b56: 7468 flw fa0,108(s0) + 9b58: 6261 lui tp,0x18 + 9b5a: 682e flw fa6,200(sp) + 9b5c: 0400 addi s0,sp,512 + 9b5e: 0000 unimp + 9b60: 6972 flw fs2,28(sp) + 9b62: 2d766373 csrrsi t1,0x2d7,12 + 9b66: 7374706f j 51a9c <_start-0x7ffae564> + 9b6a: 682e flw fa6,200(sp) + 9b6c: 0500 addi s0,sp,640 + 9b6e: 0000 unimp + 9b70: 6e69 lui t3,0x1a + 9b72: 632d6e73 csrrsi t3,0x632,26 + 9b76: 74736e6f jal t3,40abc <_start-0x7ffbf544> + 9b7a: 6e61 lui t3,0x18 + 9b7c: 7374 flw fa3,100(a4) + 9b7e: 682e flw fa6,200(sp) + 9b80: 0600 addi s0,sp,768 + 9b82: 0000 unimp + 9b84: 696c flw fa1,84(a0) + 9b86: 6762 flw fa4,24(sp) + 9b88: 2e326363 bltu tp,gp,9e6e <_start-0x7fff6192> + 9b8c: 0068 addi a0,sp,12 + 9b8e: 6c000007 0x6c000007 + 9b92: 6269 lui tp,0x1a + 9b94: 32636367 0x32636367 + 9b98: 632e flw ft6,200(sp) + 9b9a: 0700 addi s0,sp,896 + 9b9c: 0000 unimp + 9b9e: 8f00 0x8f00 + 9ba0: 0002 c.slli64 zero + 9ba2: 0300 addi s0,sp,384 + 9ba4: fd00 fsw fs0,56(a0) + 9ba6: 0001 nop + 9ba8: 0100 addi s0,sp,128 + 9baa: fb01 bnez a4,9aba <_start-0x7fff6546> + 9bac: 0d0e slli s10,s10,0x3 + 9bae: 0100 addi s0,sp,128 + 9bb0: 0101 addi sp,sp,0 + 9bb2: 0001 nop + 9bb4: 0000 unimp + 9bb6: 0001 nop + 9bb8: 0100 addi s0,sp,128 + 9bba: 2e2e fld ft8,200(sp) + 9bbc: 2f2e2e2f 0x2f2e2e2f + 9bc0: 2e2e fld ft8,200(sp) + 9bc2: 2f2e2e2f 0x2f2e2e2f + 9bc6: 6972 flw fs2,28(sp) + 9bc8: 2d766373 csrrsi t1,0x2d7,12 + 9bcc: 2f636367 0x2f636367 + 9bd0: 696c flw fa1,84(a0) + 9bd2: 6762 flw fa4,24(sp) + 9bd4: 2f006363 bltu zero,a6,9eba <_start-0x7fff6146> + 9bd8: 7355 lui t1,0xffff5 + 9bda: 7265 lui tp,0xffff9 + 9bdc: 65642f73 csrrs t5,0x656,s0 + 9be0: 6f6d lui t5,0x1b + 9be2: 636f442f 0x636f442f + 9be6: 6d75 lui s10,0x1d + 9be8: 6e65 lui t3,0x19 + 9bea: 7374 flw fa3,100(a4) + 9bec: 77656e2f 0x77656e2f + 9bf0: 6f70 flw fa2,92(a4) + 9bf2: 2f766c63 bltu a2,s7,9eea <_start-0x7fff6116> + 9bf6: 6972 flw fs2,28(sp) + 9bf8: 2d766373 csrrsi t1,0x2d7,12 + 9bfc: 2d756e67 0x2d756e67 + 9c00: 6f74 flw fa3,92(a4) + 9c02: 68636c6f jal s8,40288 <_start-0x7ffbfd78> + 9c06: 6961 lui s2,0x18 + 9c08: 2f6e fld ft10,216(sp) + 9c0a: 7562 flw fa0,56(sp) + 9c0c: 6c69 lui s8,0x1a + 9c0e: 2f64 fld fs1,216(a4) + 9c10: 7562 flw fa0,56(sp) + 9c12: 6c69 lui s8,0x1a + 9c14: 2d64 fld fs1,216(a0) + 9c16: 2d636367 0x2d636367 + 9c1a: 656e flw fa0,216(sp) + 9c1c: 62696c77 0x62696c77 + 9c20: 732d lui t1,0xfffeb + 9c22: 6174 flw fa3,68(a0) + 9c24: 2f326567 0x2f326567 + 9c28: 2f636367 0x2f636367 + 9c2c: 6e69 lui t3,0x1a + 9c2e: 64756c63 bltu a0,t2,a286 <_start-0x7fff5d7a> + 9c32: 0065 c.nop 25 + 9c34: 74706f2f 0x74706f2f + 9c38: 7369722f 0x7369722f + 9c3c: 6e2d7663 bgeu s10,sp,a328 <_start-0x7fff5cd8> + 9c40: 7765 lui a4,0xffff9 + 9c42: 6f72642f 0x6f72642f + 9c46: 7370 flw fa2,100(a4) + 9c48: 7369722f 0x7369722f + 9c4c: 32337663 bgeu t1,gp,9f78 <_start-0x7fff6088> + 9c50: 752d lui a0,0xfffeb + 9c52: 6b6e flw fs6,216(sp) + 9c54: 6f6e flw ft10,216(sp) + 9c56: 652d6e77 0x652d6e77 + 9c5a: 666c flw fa1,76(a2) + 9c5c: 636e692f 0x636e692f + 9c60: 756c flw fa1,108(a0) + 9c62: 6564 flw fs1,76(a0) + 9c64: 7379732f 0x7379732f + 9c68: 2f00 fld fs0,24(a4) + 9c6a: 2f74706f j 51760 <_start-0x7ffae8a0> + 9c6e: 6972 flw fs2,28(sp) + 9c70: 2d766373 csrrsi t1,0x2d7,12 + 9c74: 656e flw fa0,216(sp) + 9c76: 72642f77 0x72642f77 + 9c7a: 2f73706f j 41770 <_start-0x7ffbe890> + 9c7e: 6972 flw fs2,28(sp) + 9c80: 33766373 csrrsi t1,mhpmevent23,12 + 9c84: 2d32 fld fs10,264(sp) + 9c86: 6e75 lui t3,0x1d + 9c88: 776f6e6b 0x776f6e6b + 9c8c: 2d6e fld fs10,216(sp) + 9c8e: 6c65 lui s8,0x19 + 9c90: 2f66 fld ft10,88(sp) + 9c92: 6e69 lui t3,0x1a + 9c94: 64756c63 bltu a0,t2,a2ec <_start-0x7fff5d14> + 9c98: 0065 c.nop 25 + 9c9a: 2e2e fld ft8,200(sp) + 9c9c: 2f2e2e2f 0x2f2e2e2f + 9ca0: 2e2e fld ft8,200(sp) + 9ca2: 2f2e2e2f 0x2f2e2e2f + 9ca6: 6972 flw fs2,28(sp) + 9ca8: 2d766373 csrrsi t1,0x2d7,12 + 9cac: 2f636367 0x2f636367 + 9cb0: 696c flw fa1,84(a0) + 9cb2: 6762 flw fa4,24(sp) + 9cb4: 2e2f6363 bltu t5,sp,9f9a <_start-0x7fff6066> + 9cb8: 2f2e fld ft10,200(sp) + 9cba: 6e69 lui t3,0x1a + 9cbc: 64756c63 bltu a0,t2,a314 <_start-0x7fff5cec> + 9cc0: 0065 c.nop 25 + 9cc2: 2e2e fld ft8,200(sp) + 9cc4: 2f2e2e2f 0x2f2e2e2f + 9cc8: 2e2e fld ft8,200(sp) + 9cca: 2f2e2e2f 0x2f2e2e2f + 9cce: 6972 flw fs2,28(sp) + 9cd0: 2d766373 csrrsi t1,0x2d7,12 + 9cd4: 2f636367 0x2f636367 + 9cd8: 696c flw fa1,84(a0) + 9cda: 6762 flw fa4,24(sp) + 9cdc: 2e2f6363 bltu t5,sp,9fc2 <_start-0x7fff603e> + 9ce0: 2f2e fld ft10,200(sp) + 9ce2: 2f636367 0x2f636367 + 9ce6: 666e6f63 bltu t3,t1,a364 <_start-0x7fff5c9c> + 9cea: 6769 lui a4,0x1a + 9cec: 7369722f 0x7369722f + 9cf0: 2e007663 bgeu zero,zero,9fdc <_start-0x7fff6024> + 9cf4: 2f2e fld ft10,200(sp) + 9cf6: 2e2e fld ft8,200(sp) + 9cf8: 672f2e2f amoand.w.aqrl t3,s2,(t5) + 9cfc: 00006363 bltu zero,zero,9d02 <_start-0x7fff62fe> + 9d00: 696c flw fa1,84(a0) + 9d02: 6762 flw fa4,24(sp) + 9d04: 2e326363 bltu tp,gp,9fea <_start-0x7fff6016> + 9d08: 00010063 beqz sp,9d08 <_start-0x7fff62f8> + 9d0c: 7300 flw fs0,32(a4) + 9d0e: 6474 flw fa3,76(s0) + 9d10: 6564 flw fs1,76(a0) + 9d12: 2e66 fld ft8,88(sp) + 9d14: 0068 addi a0,sp,12 + 9d16: 0002 c.slli64 zero + 9d18: 5f00 lw s0,56(a4) + 9d1a: 7974 flw fa3,116(a0) + 9d1c: 6570 flw fa2,76(a0) + 9d1e: 00682e73 csrrs t3,0x6,a6 + 9d22: 72000003 lb zero,1824(zero) # 720 <_start-0x7ffff8e0> + 9d26: 6565 lui a0,0x19 + 9d28: 746e flw fs0,248(sp) + 9d2a: 682e flw fa6,200(sp) + 9d2c: 0300 addi s0,sp,384 + 9d2e: 0000 unimp + 9d30: 6f6c flw fa1,92(a4) + 9d32: 682e6b63 bltu t3,sp,a3c8 <_start-0x7fff5c38> + 9d36: 0300 addi s0,sp,384 + 9d38: 0000 unimp + 9d3a: 7265 lui tp,0xffff9 + 9d3c: 6e72 flw ft8,28(sp) + 9d3e: 00682e6f jal t3,8bd44 <_start-0x7ff742bc> + 9d42: 73000003 lb zero,1840(zero) # 730 <_start-0x7ffff8d0> + 9d46: 6474 flw fa3,76(s0) + 9d48: 696c flw fa1,84(a0) + 9d4a: 2e62 fld ft8,24(sp) + 9d4c: 0068 addi a0,sp,12 + 9d4e: 0004 0x4 + 9d50: 7500 flw fs0,40(a0) + 9d52: 696e flw fs2,216(sp) + 9d54: 2e647473 csrrci s0,0x2e6,8 + 9d58: 0068 addi a0,sp,12 + 9d5a: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> + 9d5e: 6d69 lui s10,0x1a + 9d60: 2e65 jal a118 <_start-0x7fff5ee8> + 9d62: 0068 addi a0,sp,12 + 9d64: 0004 0x4 + 9d66: 6800 flw fs0,16(s0) + 9d68: 7361 lui t1,0xffff8 + 9d6a: 7468 flw fa0,108(s0) + 9d6c: 6261 lui tp,0x18 + 9d6e: 682e flw fa6,200(sp) + 9d70: 0500 addi s0,sp,640 + 9d72: 0000 unimp + 9d74: 6972 flw fs2,28(sp) + 9d76: 2d766373 csrrsi t1,0x2d7,12 + 9d7a: 7374706f j 51cb0 <_start-0x7ffae350> + 9d7e: 682e flw fa6,200(sp) + 9d80: 0600 addi s0,sp,768 + 9d82: 0000 unimp + 9d84: 6e69 lui t3,0x1a + 9d86: 632d6e73 csrrsi t3,0x632,26 + 9d8a: 74736e6f jal t3,40cd0 <_start-0x7ffbf330> + 9d8e: 6e61 lui t3,0x18 + 9d90: 7374 flw fa3,100(a4) + 9d92: 682e flw fa6,200(sp) + 9d94: 0700 addi s0,sp,896 + 9d96: 0000 unimp + 9d98: 696c flw fa1,84(a0) + 9d9a: 6762 flw fa4,24(sp) + 9d9c: 2e326363 bltu tp,gp,a082 <_start-0x7fff5f7e> + 9da0: 0068 addi a0,sp,12 + 9da2: 0001 nop + 9da4: 0000 unimp + 9da6: 0105 addi sp,sp,1 + 9da8: 0500 addi s0,sp,640 + 9daa: c802 sw zero,16(sp) + 9dac: 0149 addi sp,sp,18 + 9dae: 0380 addi s0,sp,448 + 9db0: 05c2 slli a1,a1,0x10 + 9db2: 0501 addi a0,a0,0 + 9db4: 09010303 lb t1,144(sp) + 9db8: 0000 unimp + 9dba: 0301 addi t1,t1,0 + 9dbc: 0902 c.slli64 s2 + 9dbe: 0000 unimp + 9dc0: 0301 addi t1,t1,0 + 9dc2: 0900 addi s0,sp,144 + 9dc4: 0000 unimp + 9dc6: 0301 addi t1,t1,0 + 9dc8: 0900 addi s0,sp,144 + 9dca: 0000 unimp + 9dcc: 0301 addi t1,t1,0 + 9dce: 0900 addi s0,sp,144 + 9dd0: 0000 unimp + 9dd2: 0301 addi t1,t1,0 + 9dd4: 0900 addi s0,sp,144 9dd6: 0000 unimp - 9dd8: 6f6c flw fa1,92(a4) - 9dda: 682e6b63 bltu t3,sp,a470 <_start-0x7fff5b90> - 9dde: 0300 addi s0,sp,384 - 9de0: 0000 unimp - 9de2: 7265 lui tp,0xffff9 - 9de4: 6e72 flw ft8,28(sp) - 9de6: 00682e6f jal t3,8bdec <_start-0x7ff74214> - 9dea: 73000003 lb zero,1840(zero) # 730 <_start-0x7ffff8d0> - 9dee: 6474 flw fa3,76(s0) - 9df0: 696c flw fa1,84(a0) - 9df2: 2e62 fld ft8,24(sp) - 9df4: 0068 addi a0,sp,12 - 9df6: 0004 0x4 - 9df8: 7500 flw fs0,40(a0) - 9dfa: 696e flw fs2,216(sp) - 9dfc: 2e647473 csrrci s0,0x2e6,8 - 9e00: 0068 addi a0,sp,12 - 9e02: 74000003 lb zero,1856(zero) # 740 <_start-0x7ffff8c0> - 9e06: 6d69 lui s10,0x1a - 9e08: 2e65 jal a1c0 <_start-0x7fff5e40> - 9e0a: 0068 addi a0,sp,12 - 9e0c: 0004 0x4 - 9e0e: 6800 flw fs0,16(s0) - 9e10: 7361 lui t1,0xffff8 - 9e12: 7468 flw fa0,108(s0) - 9e14: 6261 lui tp,0x18 - 9e16: 682e flw fa6,200(sp) - 9e18: 0500 addi s0,sp,640 - 9e1a: 0000 unimp - 9e1c: 6972 flw fs2,28(sp) - 9e1e: 2d766373 csrrsi t1,0x2d7,12 - 9e22: 7374706f j 51d58 <_start-0x7ffae2a8> - 9e26: 682e flw fa6,200(sp) - 9e28: 0600 addi s0,sp,768 - 9e2a: 0000 unimp - 9e2c: 6e69 lui t3,0x1a - 9e2e: 632d6e73 csrrsi t3,0x632,26 - 9e32: 74736e6f jal t3,40d78 <_start-0x7ffbf288> - 9e36: 6e61 lui t3,0x18 - 9e38: 7374 flw fa3,100(a4) - 9e3a: 682e flw fa6,200(sp) - 9e3c: 0700 addi s0,sp,896 - 9e3e: 0000 unimp - 9e40: 696c flw fa1,84(a0) - 9e42: 6762 flw fa4,24(sp) - 9e44: 2e326363 bltu tp,gp,a12a <_start-0x7fff5ed6> - 9e48: 0068 addi a0,sp,12 - 9e4a: 0001 nop - 9e4c: 0000 unimp - 9e4e: 0105 addi sp,sp,1 - 9e50: 0500 addi s0,sp,640 - 9e52: 0402 c.slli64 s0 - 9e54: 0149 addi sp,sp,18 - 9e56: 0380 addi s0,sp,448 - 9e58: 05c2 slli a1,a1,0x10 - 9e5a: 0501 addi a0,a0,0 - 9e5c: 09010303 lb t1,144(sp) - 9e60: 0000 unimp - 9e62: 0301 addi t1,t1,0 - 9e64: 0902 c.slli64 s2 - 9e66: 0000 unimp - 9e68: 0301 addi t1,t1,0 - 9e6a: 0900 addi s0,sp,144 - 9e6c: 0000 unimp - 9e6e: 0301 addi t1,t1,0 - 9e70: 0900 addi s0,sp,144 - 9e72: 0000 unimp - 9e74: 0301 addi t1,t1,0 - 9e76: 0900 addi s0,sp,144 - 9e78: 0000 unimp - 9e7a: 0301 addi t1,t1,0 - 9e7c: 0900 addi s0,sp,144 - 9e7e: 0000 unimp - 9e80: 0001 nop - 9e82: 0402 c.slli64 s0 - 9e84: 00030603 lb a2,0(t1) # ffff8000 <__BSS_END__+0x7ffe13d0> - 9e88: 0809 addi a6,a6,2 - 9e8a: 0100 addi s0,sp,128 - 9e8c: 0200 addi s0,sp,256 - 9e8e: 0e04 addi s1,sp,784 - 9e90: 0306 slli t1,t1,0x1 - 9e92: 0900 addi s0,sp,144 - 9e94: 000c 0xc - 9e96: 0001 nop - 9e98: 0402 c.slli64 s0 - 9e9a: 030e slli t1,t1,0x3 - 9e9c: 0900 addi s0,sp,144 - 9e9e: 0000 unimp - 9ea0: 0001 nop - 9ea2: 0402 c.slli64 s0 - 9ea4: 030e slli t1,t1,0x3 - 9ea6: 0902 c.slli64 s2 - 9ea8: 0000 unimp - 9eaa: 0001 nop - 9eac: 0402 c.slli64 s0 - 9eae: 060e slli a2,a2,0x3 - 9eb0: 00097e03 0x97e03 - 9eb4: 0100 addi s0,sp,128 - 9eb6: 0105 addi sp,sp,1 - 9eb8: 0200 addi s0,sp,256 - 9eba: 0e04 addi s1,sp,784 - 9ebc: 1c090303 lb t1,448(s2) # 181c0 <_start-0x7ffe7e40> - 9ec0: 0100 addi s0,sp,128 - 9ec2: 0305 addi t1,t1,1 - 9ec4: 0200 addi s0,sp,256 - 9ec6: 0404 addi s1,sp,512 - 9ec8: 08097d03 0x8097d03 - 9ecc: 0100 addi s0,sp,128 - 9ece: 0c090003 lb zero,192(s2) - 9ed2: 0100 addi s0,sp,128 - 9ed4: 0809 addi a6,a6,2 - 9ed6: 0000 unimp - 9ed8: 0101 addi sp,sp,0 + 9dd8: 0001 nop + 9dda: 0402 c.slli64 s0 + 9ddc: 00030603 lb a2,0(t1) # ffff8000 <__BSS_END__+0x7ffe13c4> + 9de0: 0809 addi a6,a6,2 + 9de2: 0100 addi s0,sp,128 + 9de4: 0200 addi s0,sp,256 + 9de6: 0e04 addi s1,sp,784 + 9de8: 0306 slli t1,t1,0x1 + 9dea: 0900 addi s0,sp,144 + 9dec: 000c 0xc + 9dee: 0001 nop + 9df0: 0402 c.slli64 s0 + 9df2: 030e slli t1,t1,0x3 + 9df4: 0900 addi s0,sp,144 + 9df6: 0000 unimp + 9df8: 0001 nop + 9dfa: 0402 c.slli64 s0 + 9dfc: 030e slli t1,t1,0x3 + 9dfe: 0902 c.slli64 s2 + 9e00: 0000 unimp + 9e02: 0001 nop + 9e04: 0402 c.slli64 s0 + 9e06: 060e slli a2,a2,0x3 + 9e08: 00097e03 0x97e03 + 9e0c: 0100 addi s0,sp,128 + 9e0e: 0105 addi sp,sp,1 + 9e10: 0200 addi s0,sp,256 + 9e12: 0e04 addi s1,sp,784 + 9e14: 1c090303 lb t1,448(s2) # 181c0 <_start-0x7ffe7e40> + 9e18: 0100 addi s0,sp,128 + 9e1a: 0305 addi t1,t1,1 + 9e1c: 0200 addi s0,sp,256 + 9e1e: 0404 addi s1,sp,512 + 9e20: 08097d03 0x8097d03 + 9e24: 0100 addi s0,sp,128 + 9e26: 0c090003 lb zero,192(s2) + 9e2a: 0100 addi s0,sp,128 + 9e2c: 0809 addi a6,a6,2 + 9e2e: 0000 unimp + 9e30: 0101 addi sp,sp,0 Disassembly of section .debug_frame: @@ -58153,7 +58123,7 @@ Disassembly of section .debug_frame: 12: 0000 unimp 14: 0000 unimp 16: 0000 unimp - 18: 0c44 addi s1,sp,532 + 18: 0d08 addi a0,sp,656 1a: 8001 c.srli64 s0 1c: 06e0 addi s0,sp,844 1e: 0000 unimp @@ -58195,7 +58165,7 @@ Disassembly of section .debug_frame: 6a: 0000 unimp 6c: 0058 addi a4,sp,4 6e: 0000 unimp - 70: 1324 addi s1,sp,424 + 70: 13e8 addi a0,sp,492 72: 8001 c.srli64 s0 74: 05c4 addi s1,sp,708 76: 0000 unimp @@ -58235,7 +58205,7 @@ Disassembly of section .debug_frame: be: 0000 unimp c0: 00ac addi a1,sp,72 c2: 0000 unimp - c4: 18e8 addi a0,sp,124 + c4: 19ac addi a1,sp,248 c6: 8001 c.srli64 s0 c8: 00cc addi a1,sp,68 ca: 0000 unimp @@ -58256,7 +58226,7 @@ Disassembly of section .debug_frame: ea: 0000 unimp ec: 00d8 addi a4,sp,68 ee: 0000 unimp - f0: 19b4 addi a3,sp,248 + f0: 1a78 addi a4,sp,316 f2: 8001 c.srli64 s0 f4: 0144 addi s1,sp,132 f6: 0000 unimp @@ -58277,7 +58247,7 @@ Disassembly of section .debug_frame: 116: 0000 unimp 118: 0104 addi s1,sp,128 11a: 0000 unimp - 11c: 1af8 addi a4,sp,380 + 11c: 1bbc addi a5,sp,504 11e: 8001 c.srli64 s0 120: 0144 addi s1,sp,132 122: 0000 unimp @@ -58298,7 +58268,7 @@ Disassembly of section .debug_frame: 142: 0000 unimp 144: 0130 addi a2,sp,136 146: 0000 unimp - 148: 1c3c addi a5,sp,568 + 148: 1d00 addi s0,sp,688 14a: 8001 c.srli64 s0 14c: 1004 addi s1,sp,32 14e: 0000 unimp @@ -58345,7 +58315,7 @@ Disassembly of section .debug_frame: 1aa: 0000 unimp 1ac: 0198 addi a4,sp,192 1ae: 0000 unimp - 1b0: 2c40 fld fs0,152(s0) + 1b0: 2d04 fld fs1,24(a0) 1b2: 8001 c.srli64 s0 1b4: 1520 addi s0,sp,680 1b6: 0000 unimp @@ -58382,7 +58352,7 @@ Disassembly of section .debug_frame: 1fa: 0000 unimp 1fc: 01e8 addi a0,sp,204 1fe: 0000 unimp - 200: 4160 lw s0,68(a0) + 200: 4224 lw s1,64(a2) 202: 8001 c.srli64 s0 204: 0114 addi a3,sp,128 206: 0000 unimp @@ -58404,7 +58374,7 @@ Disassembly of section .debug_frame: 226: 0000 unimp 228: 0214 addi a3,sp,256 22a: 0000 unimp - 22c: 4274 lw a3,68(a2) + 22c: 4338 lw a4,64(a4) 22e: 8001 c.srli64 s0 230: 0150 addi a2,sp,132 232: 0000 unimp @@ -58433,7 +58403,7 @@ Disassembly of section .debug_frame: 262: 0000 unimp 264: 0250 addi a2,sp,260 266: 0000 unimp - 268: 43c4 lw s1,4(a5) + 268: 4488 lw a0,8(s1) 26a: 8001 c.srli64 s0 26c: 01f4 addi a3,sp,204 26e: 0000 unimp @@ -58462,7 +58432,7 @@ Disassembly of section .debug_frame: 29e: 0000 unimp 2a0: 028c addi a1,sp,320 2a2: 0000 unimp - 2a4: 45b8 lw a4,72(a1) + 2a4: 467c lw a5,76(a2) 2a6: 8001 c.srli64 s0 2a8: 034c addi a1,sp,388 2aa: 0000 unimp @@ -58483,7 +58453,7 @@ Disassembly of section .debug_frame: 2ca: 0000 unimp 2cc: 02b8 addi a4,sp,328 2ce: 0000 unimp - 2d0: 4904 lw s1,16(a0) + 2d0: 49c8 lw a0,20(a1) 2d2: 8001 c.srli64 s0 2d4: 004c addi a1,sp,4 ... @@ -58621,438 +58591,442 @@ Disassembly of section .debug_str: 18c: 6574 flw fa3,76(a0) 18e: 72757463 bgeu a0,t2,8b6 <_start-0x7ffff74a> 192: 0065 c.nop 25 - 194: 6d6f682f 0x6d6f682f - 198: 2f65 jal 950 <_start-0x7ffff6b0> - 19a: 6166 flw ft2,88(sp) - 19c: 6572 flw fa0,28(sp) - 19e: 6f442f73 csrrs t5,0x6f4,s0 - 1a2: 656d7563 bgeu s10,s6,7ec <_start-0x7ffff814> - 1a6: 746e flw fs0,248(sp) - 1a8: 6f702f73 csrr t5,0x6f7 - 1ac: 645f6c63 bltu t5,t0,804 <_start-0x7ffff7fc> - 1b0: 7065 c.lui zero,0xffff9 - 1b2: 7369722f 0x7369722f - 1b6: 672d7663 bgeu s10,s2,822 <_start-0x7ffff7de> - 1ba: 756e flw fa0,248(sp) - 1bc: 742d lui s0,0xfffeb - 1be: 636c6f6f jal t5,c67f4 <_start-0x7ff3980c> - 1c2: 6168 flw fa0,68(a0) - 1c4: 6e69 lui t3,0x1a - 1c6: 6975622f 0x6975622f - 1ca: 646c flw fa1,76(s0) - 1cc: 6975622f 0x6975622f - 1d0: 646c flw fa1,76(s0) - 1d2: 672d lui a4,0xb - 1d4: 6e2d6363 bltu s10,sp,8ba <_start-0x7ffff746> - 1d8: 7765 lui a4,0xffff9 - 1da: 696c flw fa1,84(a0) - 1dc: 2d62 fld fs10,24(sp) - 1de: 67617473 csrrci s0,0x676,2 - 1e2: 3265 jal fffffb8a <__BSS_END__+0x7ffe8f5a> - 1e4: 7369722f 0x7369722f - 1e8: 32337663 bgeu t1,gp,514 <_start-0x7ffffaec> - 1ec: 752d lui a0,0xfffeb - 1ee: 6b6e flw fs6,216(sp) - 1f0: 6f6e flw ft10,216(sp) - 1f2: 652d6e77 0x652d6e77 - 1f6: 666c flw fa1,76(a2) - 1f8: 62696c2f 0x62696c2f - 1fc: 00636367 0x636367 - 200: 735f 7379 655f 0x655f7379735f - 206: 7272 flw ft4,60(sp) - 208: 696c flw fa1,84(a0) - 20a: 5f007473 csrrci s0,0x5f0,0 - 20e: 62747663 bgeu s0,t2,83a <_start-0x7ffff7c6> - 212: 6675 lui a2,0x1d - 214: 5f00 lw s0,56(a4) - 216: 626d lui tp,0x1b - 218: 6f747273 csrrci tp,0x6f7,8 - 21c: 5f736377 0x5f736377 - 220: 74617473 csrrci s0,0x746,2 - 224: 0065 c.nop 25 - 226: 6d5f 7262 656c 0x656c72626d5f - 22c: 5f6e lw t5,248(sp) - 22e: 74617473 csrrci s0,0x746,2 - 232: 0065 c.nop 25 - 234: 6972 flw fs2,28(sp) - 236: 5f766373 csrrsi t1,0x5f7,12 - 23a: 646f6d63 bltu t5,t1,894 <_start-0x7ffff76c> - 23e: 6c65 lui s8,0x19 - 240: 5f00 lw s0,56(a4) - 242: 6e66 flw ft8,88(sp) - 244: 7261 lui tp,0xffff8 - 246: 5f007367 0x5f007367 - 24a: 6e66 flw ft8,88(sp) - 24c: 735f0073 0x735f0073 - 250: 6769 lui a4,0x1a - 252: 006e c.slli zero,0x1b - 254: 735f 6474 7265 0x72656474735f - 25a: 0072 c.slli zero,0x1c - 25c: 675f 6d61 616d 0x616d6d61675f - 262: 735f 6769 676e 0x676e6769735f - 268: 6d61 lui s10,0x18 - 26a: 5f00 lw s0,56(a4) - 26c: 6d6e flw fs10,216(sp) - 26e: 6c61 lui s8,0x18 - 270: 6f6c flw fa1,92(a4) - 272: 755f0063 beq t5,s5,9b2 <_start-0x7ffff64e> - 276: 736e flw ft6,248(sp) - 278: 6570 flw fa2,76(a0) - 27a: 69666963 bltu a2,s6,90c <_start-0x7ffff6f4> - 27e: 6465 lui s0,0x19 - 280: 6c5f 636f 6c61 0x6c61636f6c5f - 286: 5f65 li t5,-7 - 288: 6e69 lui t3,0x1a - 28a: 6f66 flw ft10,88(sp) - 28c: 5f00 lw s0,56(a4) - 28e: 745f 006d 6972 0x6972006d745f - 294: 5f766373 csrrsi t1,0x5f7,12 - 298: 6261 lui tp,0x18 - 29a: 5f69 li t5,-6 - 29c: 7974 flw fa3,116(a0) - 29e: 6570 flw fa2,76(a0) - 2a0: 5f00 lw s0,56(a4) - 2a2: 626d lui tp,0x1b - 2a4: 74617473 csrrci s0,0x746,2 - 2a8: 0065 c.nop 25 - 2aa: 5f5f 6377 6268 0x626863775f5f - 2b0: 5f00 lw s0,56(a4) - 2b2: 6c747663 bgeu s0,t2,97e <_start-0x7ffff682> - 2b6: 6e65 lui t3,0x19 - 2b8: 5f00 lw s0,56(a4) - 2ba: 6966 flw fs2,88(sp) - 2bc: 656c flw fa1,76(a0) - 2be: 6800 flw fs0,16(s0) - 2c0: 7361 lui t1,0xffff8 - 2c2: 7668 flw fa0,108(a2) - 2c4: 6c61 lui s8,0x18 - 2c6: 745f 4400 7557 0x75574400745f - 2cc: 696e flw fs2,216(sp) - 2ce: 5f006e6f jal t3,68be <_start-0x7fff9742> - 2d2: 696e flw fs2,216(sp) - 2d4: 0073626f jal tp,36ada <_start-0x7ffc9526> - 2d8: 6f6c flw fa1,92(a4) - 2da: 676e flw fa4,216(sp) - 2dc: 6c20 flw fs0,88(s0) - 2de: 20676e6f jal t3,764e4 <_start-0x7ff89b1c> - 2e2: 6e75 lui t3,0x1d - 2e4: 6e676973 csrrsi s2,0x6e6,14 - 2e8: 6465 lui s0,0x19 - 2ea: 6920 flw fs0,80(a0) - 2ec: 746e flw fs0,248(sp) - 2ee: 4400 lw s0,8(s0) - 2f0: 72747357 0x72747357 - 2f4: 6375 lui t1,0x1d - 2f6: 0074 addi a3,sp,12 - 2f8: 726f6873 csrrsi a6,0x726,30 - 2fc: 2074 fld fa3,192(s0) - 2fe: 6e75 lui t3,0x1d - 300: 6e676973 csrrsi s2,0x6e6,14 - 304: 6465 lui s0,0x19 - 306: 6920 flw fs0,80(a0) - 308: 746e flw fs0,248(sp) + 194: 735f 7379 655f 0x655f7379735f + 19a: 7272 flw ft4,60(sp) + 19c: 696c flw fa1,84(a0) + 19e: 5f007473 csrrci s0,0x5f0,0 + 1a2: 62747663 bgeu s0,t2,7ce <_start-0x7ffff832> + 1a6: 6675 lui a2,0x1d + 1a8: 5f00 lw s0,56(a4) + 1aa: 626d lui tp,0x1b + 1ac: 6f747273 csrrci tp,0x6f7,8 + 1b0: 5f736377 0x5f736377 + 1b4: 74617473 csrrci s0,0x746,2 + 1b8: 0065 c.nop 25 + 1ba: 6d5f 7262 656c 0x656c72626d5f + 1c0: 5f6e lw t5,248(sp) + 1c2: 74617473 csrrci s0,0x746,2 + 1c6: 0065 c.nop 25 + 1c8: 6972 flw fs2,28(sp) + 1ca: 5f766373 csrrsi t1,0x5f7,12 + 1ce: 646f6d63 bltu t5,t1,828 <_start-0x7ffff7d8> + 1d2: 6c65 lui s8,0x19 + 1d4: 5f00 lw s0,56(a4) + 1d6: 6e66 flw ft8,88(sp) + 1d8: 7261 lui tp,0xffff8 + 1da: 5f007367 0x5f007367 + 1de: 6e66 flw ft8,88(sp) + 1e0: 735f0073 0x735f0073 + 1e4: 6769 lui a4,0x1a + 1e6: 006e c.slli zero,0x1b + 1e8: 735f 6474 7265 0x72656474735f + 1ee: 0072 c.slli zero,0x1c + 1f0: 675f 6d61 616d 0x616d6d61675f + 1f6: 735f 6769 676e 0x676e6769735f + 1fc: 6d61 lui s10,0x18 + 1fe: 5f00 lw s0,56(a4) + 200: 6d6e flw fs10,216(sp) + 202: 6c61 lui s8,0x18 + 204: 6f6c flw fa1,92(a4) + 206: 755f0063 beq t5,s5,946 <_start-0x7ffff6ba> + 20a: 736e flw ft6,248(sp) + 20c: 6570 flw fa2,76(a0) + 20e: 69666963 bltu a2,s6,8a0 <_start-0x7ffff760> + 212: 6465 lui s0,0x19 + 214: 6c5f 636f 6c61 0x6c61636f6c5f + 21a: 5f65 li t5,-7 + 21c: 6e69 lui t3,0x1a + 21e: 6f66 flw ft10,88(sp) + 220: 5f00 lw s0,56(a4) + 222: 745f 006d 6972 0x6972006d745f + 228: 5f766373 csrrsi t1,0x5f7,12 + 22c: 6261 lui tp,0x18 + 22e: 5f69 li t5,-6 + 230: 7974 flw fa3,116(a0) + 232: 6570 flw fa2,76(a0) + 234: 5f00 lw s0,56(a4) + 236: 626d lui tp,0x1b + 238: 74617473 csrrci s0,0x746,2 + 23c: 0065 c.nop 25 + 23e: 5f5f 6377 6268 0x626863775f5f + 244: 5f00 lw s0,56(a4) + 246: 6c747663 bgeu s0,t2,912 <_start-0x7ffff6ee> + 24a: 6e65 lui t3,0x19 + 24c: 5f00 lw s0,56(a4) + 24e: 6966 flw fs2,88(sp) + 250: 656c flw fa1,76(a0) + 252: 6800 flw fs0,16(s0) + 254: 7361 lui t1,0xffff8 + 256: 7668 flw fa0,108(a2) + 258: 6c61 lui s8,0x18 + 25a: 745f 4400 7557 0x75574400745f + 260: 696e flw fs2,216(sp) + 262: 5f006e6f jal t3,6852 <_start-0x7fff97ae> + 266: 696e flw fs2,216(sp) + 268: 0073626f jal tp,36a6e <_start-0x7ffc9592> + 26c: 6f6c flw fa1,92(a4) + 26e: 676e flw fa4,216(sp) + 270: 6c20 flw fs0,88(s0) + 272: 20676e6f jal t3,76478 <_start-0x7ff89b88> + 276: 6e75 lui t3,0x1d + 278: 6e676973 csrrsi s2,0x6e6,14 + 27c: 6465 lui s0,0x19 + 27e: 6920 flw fs0,80(a0) + 280: 746e flw fs0,248(sp) + 282: 4400 lw s0,8(s0) + 284: 72747357 0x72747357 + 288: 6375 lui t1,0x1d + 28a: 0074 addi a3,sp,12 + 28c: 726f6873 csrrsi a6,0x726,30 + 290: 2074 fld fa3,192(s0) + 292: 6e75 lui t3,0x1d + 294: 6e676973 csrrsi s2,0x6e6,14 + 298: 6465 lui s0,0x19 + 29a: 6920 flw fs0,80(a0) + 29c: 746e flw fs0,248(sp) + 29e: 5f00 lw s0,56(a4) + 2a0: 635f 7a6c 745f 0x745f7a6c635f + 2a6: 6261 lui tp,0x18 + 2a8: 5f00 lw s0,56(a4) + 2aa: 7461 lui s0,0xffff8 + 2ac: 7865 lui a6,0xffff9 + 2ae: 7469 lui s0,0xffffa + 2b0: 0030 addi a2,sp,8 + 2b2: 735f 6769 616e 0x616e6769735f + 2b8: 5f6c lw a1,124(a4) + 2ba: 7562 flw fa0,56(sp) + 2bc: 0066 c.slli zero,0x19 + 2be: 615f 6373 6974 0x69746373615f + 2c4: 656d lui a0,0x1b + 2c6: 625f 6675 5f00 0x5f006675625f + 2cc: 6572 flw fa0,28(sp) + 2ce: 746c7573 csrrci a0,0x746,24 + 2d2: 5f00 lw s0,56(a4) + 2d4: 775f 6863 5f00 0x5f006863775f + 2da: 656e flw fa0,216(sp) + 2dc: 7478 flw fa4,108(s0) + 2de: 0066 c.slli zero,0x19 + 2e0: 6e65 lui t3,0x19 + 2e2: 6976 flw fs2,92(sp) + 2e4: 6f72 flw ft10,28(sp) + 2e6: 006e c.slli zero,0x1b + 2e8: 746e6977 0x746e6977 + 2ec: 745f 5f00 6f6c 0x6f6c5f00745f + 2f2: 5f006b63 bltu zero,a6,8e8 <_start-0x7ffff718> + 2f6: 755f 0068 4241 0x42410068755f + 2fc: 5f49 li t5,-14 + 2fe: 4c49 li s8,18 + 300: 3350 fld fa2,160(a4) + 302: 4532 lw a0,12(sp) + 304: 5f00 lw s0,56(a4) + 306: 756d lui a0,0xffffb + 308: 746c flw fa1,108(s0) 30a: 5f00 lw s0,56(a4) - 30c: 635f 7a6c 745f 0x745f7a6c635f - 312: 6261 lui tp,0x18 - 314: 5f00 lw s0,56(a4) - 316: 7461 lui s0,0xffff8 - 318: 7865 lui a6,0xffff9 - 31a: 7469 lui s0,0xffffa - 31c: 0030 addi a2,sp,8 - 31e: 735f 6769 616e 0x616e6769735f - 324: 5f6c lw a1,124(a4) - 326: 7562 flw fa0,56(sp) - 328: 0066 c.slli zero,0x19 - 32a: 615f 6373 6974 0x69746373615f - 330: 656d lui a0,0x1b - 332: 625f 6675 5f00 0x5f006675625f - 338: 6572 flw fa0,28(sp) - 33a: 746c7573 csrrci a0,0x746,24 - 33e: 5f00 lw s0,56(a4) - 340: 775f 6863 5f00 0x5f006863775f - 346: 656e flw fa0,216(sp) - 348: 7478 flw fa4,108(s0) - 34a: 0066 c.slli zero,0x19 - 34c: 6e65 lui t3,0x19 - 34e: 6976 flw fs2,92(sp) - 350: 6f72 flw ft10,28(sp) - 352: 006e c.slli zero,0x1b - 354: 746e6977 0x746e6977 - 358: 745f 5f00 6f6c 0x6f6c5f00745f - 35e: 5f006b63 bltu zero,a6,954 <_start-0x7ffff6ac> - 362: 755f 0068 4241 0x42410068755f - 368: 5f49 li t5,-14 - 36a: 4c49 li s8,18 - 36c: 3350 fld fa2,160(a4) - 36e: 4532 lw a0,12(sp) - 370: 5f00 lw s0,56(a4) - 372: 756d lui a0,0xffffb - 374: 746c flw fa1,108(s0) - 376: 5f00 lw s0,56(a4) - 378: 755f 006c 6e75 0x6e75006c755f - 37e: 63657073 csrci 0x636,10 - 382: 735f 7274 6e69 0x6e697274735f - 388: 6f007367 0x6f007367 - 38c: 7470 flw fa2,108(s0) - 38e: 6572 flw fa0,28(sp) - 390: 00746573 csrrsi a0,0x7,8 - 394: 775f 6972 6574 0x65746972775f - 39a: 5f00 lw s0,56(a4) - 39c: 745f 5f6d 6579 0x65795f6d745f - 3a2: 7261 lui tp,0xffff8 - 3a4: 5f00 lw s0,56(a4) - 3a6: 635f 756f 746e 0x746e756f635f - 3ac: 5f00 lw s0,56(a4) - 3ae: 6e75 lui t3,0x1d - 3b0: 7375 lui t1,0xffffd - 3b2: 6465 lui s0,0x19 - 3b4: 725f 6e61 0064 0x646e61725f - 3ba: 4241 li tp,16 - 3bc: 5f49 li t5,-14 - 3be: 4c49 li s8,18 - 3c0: 3350 fld fa2,160(a4) - 3c2: 4432 lw s0,12(sp) - 3c4: 7200 flw fs0,32(a2) - 3c6: 7369 lui t1,0xffffa - 3c8: 635f7663 bgeu t5,s5,9f4 <_start-0x7ffff60c> - 3cc: 5f65646f jal s0,569c2 <_start-0x7ffa963e> - 3d0: 6f6d lui t5,0x1b - 3d2: 6564 flw fs1,76(a0) - 3d4: 006c addi a1,sp,12 - 3d6: 6f5f 6666 6573 0x657366666f5f - 3dc: 0074 addi a3,sp,12 - 3de: 425f 6769 6e69 0x6e696769425f - 3e4: 0074 addi a3,sp,12 - 3e6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm - 3ea: 20373143 fmadd.s ft2,fa4,ft3,ft4,rup - 3ee: 2e39 jal 70c <_start-0x7ffff8f4> - 3f0: 2e32 fld ft8,264(sp) - 3f2: 2030 fld fa2,64(s0) - 3f4: 6d2d lui s10,0xb - 3f6: 646f6d63 bltu t5,t1,a50 <_start-0x7ffff5b0> - 3fa: 6c65 lui s8,0x19 - 3fc: 6d3d lui s10,0xf - 3fe: 6465 lui s0,0x19 - 400: 6f6c flw fa1,92(a4) - 402: 6d2d2077 0x6d2d2077 - 406: 646f6d63 bltu t5,t1,a60 <_start-0x7ffff5a0> - 40a: 6c65 lui s8,0x19 - 40c: 6d3d lui s10,0xf - 40e: 6465 lui s0,0x19 - 410: 6f6c flw fa1,92(a4) - 412: 6d2d2077 0x6d2d2077 - 416: 7574 flw fa3,108(a0) - 418: 656e flw fa0,216(sp) - 41a: 723d lui tp,0xfffef - 41c: 656b636f jal t1,b6a72 <_start-0x7ff4958e> - 420: 2074 fld fa3,192(s0) - 422: 6d2d lui s10,0xb - 424: 7261 lui tp,0xffff8 - 426: 723d6863 bltu s10,gp,b56 <_start-0x7ffff4aa> - 42a: 3376 fld ft6,376(sp) - 42c: 6932 flw fs2,12(sp) - 42e: 206d jal 4d8 <_start-0x7ffffb28> - 430: 6d2d lui s10,0xb - 432: 6261 lui tp,0x18 - 434: 3d69 jal 2ce <_start-0x7ffffd32> - 436: 6c69 lui s8,0x1a - 438: 3370 fld fa2,224(a4) - 43a: 2032 fld ft0,264(sp) - 43c: 672d lui a4,0xb - 43e: 2d20 fld fs0,88(a0) - 440: 2d20734f 0x2d20734f - 444: 2d20324f 0x2d20324f - 448: 2d20734f 0x2d20734f - 44c: 6266 flw ft4,88(sp) - 44e: 6975 lui s2,0x1d - 450: 646c flw fa1,76(s0) - 452: 6e69 lui t3,0x1a - 454: 696c2d67 0x696c2d67 - 458: 6762 flw fa4,24(sp) - 45a: 2d206363 bltu zero,s2,720 <_start-0x7ffff8e0> - 45e: 6e66 flw ft8,88(sp) - 460: 74732d6f jal s10,333a6 <_start-0x7ffccc5a> - 464: 6361 lui t1,0x18 - 466: 72702d6b 0x72702d6b - 46a: 6365746f jal s0,57aa0 <_start-0x7ffa8560> - 46e: 6f74 flw fa3,92(a4) - 470: 2072 fld ft0,280(sp) - 472: 662d lui a2,0xb - 474: 7865 lui a6,0xffff9 - 476: 74706563 bltu zero,t2,bc0 <_start-0x7ffff440> - 47a: 6f69 lui t5,0x1a - 47c: 736e flw ft6,248(sp) - 47e: 2d20 fld fs0,88(a0) - 480: 6e66 flw ft8,88(sp) - 482: 632d6e6f jal t3,d6ab4 <_start-0x7ff2954c> - 486: 6c61 lui s8,0x18 - 488: 2d6c fld fa1,216(a0) - 48a: 7865 lui a6,0xffff9 - 48c: 74706563 bltu zero,t2,bd6 <_start-0x7ffff42a> - 490: 6f69 lui t5,0x1a - 492: 736e flw ft6,248(sp) - 494: 2d20 fld fs0,88(a0) - 496: 7666 flw fa2,120(sp) - 498: 7369 lui t1,0xffffa - 49a: 6269 lui tp,0x1a - 49c: 6c69 lui s8,0x1a - 49e: 7469 lui s0,0xffffa - 4a0: 3d79 jal 33e <_start-0x7ffffcc2> - 4a2: 6968 flw fa0,84(a0) - 4a4: 6464 flw fs1,76(s0) - 4a6: 6e65 lui t3,0x19 - 4a8: 4100 lw s0,0(a0) - 4aa: 4942 lw s2,16(sp) - 4ac: 495f 504c 3233 0x3233504c495f - 4b2: 0046 c.slli zero,0x11 - 4b4: 706d6f63 bltu s10,t1,bd2 <_start-0x7ffff42e> - 4b8: 656c flw fa1,76(a0) - 4ba: 2078 fld fa4,192(s0) - 4bc: 6c66 flw fs8,88(sp) - 4be: 0074616f jal sp,46cc4 <_start-0x7ffb933c> - 4c2: 6f6c flw fa1,92(a4) - 4c4: 676e flw fa4,216(sp) - 4c6: 6c20 flw fs0,88(s0) - 4c8: 20676e6f jal t3,766ce <_start-0x7ff89932> - 4cc: 6e69 lui t3,0x1a - 4ce: 0074 addi a3,sp,12 - 4d0: 5f5f 6d74 6d5f 0x6d5f6d745f5f - 4d6: 5f006e6f jal t3,6ac6 <_start-0x7fff953a> - 4da: 7461 lui s0,0xffff8 - 4dc: 7865 lui a6,0xffff9 - 4de: 7469 lui s0,0xffffa - 4e0: 7300 flw fs0,32(a4) - 4e2: 6275 lui tp,0x1d - 4e4: 6174706f j 482fa <_start-0x7ffb7d06> - 4e8: 6772 flw fa4,28(sp) - 4ea: 5f00 lw s0,56(a4) - 4ec: 735f 6964 6964 0x69646964735f - 4f2: 696e flw fs2,216(sp) - 4f4: 0074 addi a3,sp,12 - 4f6: 6f5f 6666 745f 0x745f66666f5f - 4fc: 5f00 lw s0,56(a4) - 4fe: 765f 0068 5f5f 0x5f5f0068765f - 504: 6c76 flw fs8,92(sp) - 506: 5f00 lw s0,56(a4) - 508: 7266 flw ft4,120(sp) - 50a: 6565 lui a0,0x19 - 50c: 696c flw fa1,84(a0) - 50e: 5f007473 csrrci s0,0x5f0,0 - 512: 6974 flw fa3,84(a0) - 514: 656d lui a0,0x1b - 516: 6f7a flw ft10,156(sp) - 518: 656e flw fa0,216(sp) - 51a: 5f00 lw s0,56(a4) - 51c: 626d lui tp,0x1b - 51e: 74617473 csrrci s0,0x746,2 - 522: 5f65 li t5,-7 - 524: 0074 addi a3,sp,12 - 526: 4c5f 434f 5f4b 0x5f4b434f4c5f - 52c: 4552 lw a0,20(sp) - 52e: 53525543 fmadd.d fa0,ft4,fs5,fa0,unknown - 532: 5649 li a2,-14 - 534: 5f45 li t5,-15 - 536: 0054 addi a3,sp,4 - 538: 725f 6165 0064 0x646165725f - 53e: 2e2e fld ft8,200(sp) - 540: 2f2e2e2f 0x2f2e2e2f - 544: 2e2e fld ft8,200(sp) - 546: 2f2e2e2f 0x2f2e2e2f - 54a: 6972 flw fs2,28(sp) - 54c: 2d766373 csrrsi t1,0x2d7,12 - 550: 2f636367 0x2f636367 - 554: 696c flw fa1,84(a0) - 556: 6762 flw fa4,24(sp) - 558: 6c2f6363 bltu t5,sp,c1e <_start-0x7ffff3e2> - 55c: 6269 lui tp,0x1a - 55e: 32636367 0x32636367 - 562: 632e flw ft6,200(sp) - 564: 4100 lw s0,0(a0) - 566: 4942 lw s2,16(sp) - 568: 4c5f 3650 0034 0x3436504c5f - 56e: 4241 li tp,16 - 570: 5f49 li t5,-14 - 572: 4c49 li s8,18 - 574: 3350 fld fa2,160(a4) - 576: 0032 c.slli zero,0xc - 578: 645f 6f73 685f 0x685f6f73645f - 57e: 6e61 lui t3,0x18 - 580: 6c64 flw fs1,92(s0) + 30c: 755f 006c 6e75 0x6e75006c755f + 312: 63657073 csrci 0x636,10 + 316: 735f 7274 6e69 0x6e697274735f + 31c: 6f007367 0x6f007367 + 320: 7470 flw fa2,108(s0) + 322: 6572 flw fa0,28(sp) + 324: 00746573 csrrsi a0,0x7,8 + 328: 775f 6972 6574 0x65746972775f + 32e: 5f00 lw s0,56(a4) + 330: 745f 5f6d 6579 0x65795f6d745f + 336: 7261 lui tp,0xffff8 + 338: 5f00 lw s0,56(a4) + 33a: 635f 756f 746e 0x746e756f635f + 340: 5f00 lw s0,56(a4) + 342: 6e75 lui t3,0x1d + 344: 7375 lui t1,0xffffd + 346: 6465 lui s0,0x19 + 348: 725f 6e61 0064 0x646e61725f + 34e: 4241 li tp,16 + 350: 5f49 li t5,-14 + 352: 4c49 li s8,18 + 354: 3350 fld fa2,160(a4) + 356: 4432 lw s0,12(sp) + 358: 7200 flw fs0,32(a2) + 35a: 7369 lui t1,0xffffa + 35c: 635f7663 bgeu t5,s5,988 <_start-0x7ffff678> + 360: 5f65646f jal s0,56956 <_start-0x7ffa96aa> + 364: 6f6d lui t5,0x1b + 366: 6564 flw fs1,76(a0) + 368: 006c addi a1,sp,12 + 36a: 6f5f 6666 6573 0x657366666f5f + 370: 0074 addi a3,sp,12 + 372: 425f 6769 6e69 0x6e696769425f + 378: 0074 addi a3,sp,12 + 37a: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm + 37e: 20373143 fmadd.s ft2,fa4,ft3,ft4,rup + 382: 2e39 jal 6a0 <_start-0x7ffff960> + 384: 2e32 fld ft8,264(sp) + 386: 2030 fld fa2,64(s0) + 388: 6d2d lui s10,0xb + 38a: 646f6d63 bltu t5,t1,9e4 <_start-0x7ffff61c> + 38e: 6c65 lui s8,0x19 + 390: 6d3d lui s10,0xf + 392: 6465 lui s0,0x19 + 394: 6f6c flw fa1,92(a4) + 396: 6d2d2077 0x6d2d2077 + 39a: 646f6d63 bltu t5,t1,9f4 <_start-0x7ffff60c> + 39e: 6c65 lui s8,0x19 + 3a0: 6d3d lui s10,0xf + 3a2: 6465 lui s0,0x19 + 3a4: 6f6c flw fa1,92(a4) + 3a6: 6d2d2077 0x6d2d2077 + 3aa: 7574 flw fa3,108(a0) + 3ac: 656e flw fa0,216(sp) + 3ae: 723d lui tp,0xfffef + 3b0: 656b636f jal t1,b6a06 <_start-0x7ff495fa> + 3b4: 2074 fld fa3,192(s0) + 3b6: 6d2d lui s10,0xb + 3b8: 7261 lui tp,0xffff8 + 3ba: 723d6863 bltu s10,gp,aea <_start-0x7ffff516> + 3be: 3376 fld ft6,376(sp) + 3c0: 6932 flw fs2,12(sp) + 3c2: 206d jal 46c <_start-0x7ffffb94> + 3c4: 6d2d lui s10,0xb + 3c6: 6261 lui tp,0x18 + 3c8: 3d69 jal 262 <_start-0x7ffffd9e> + 3ca: 6c69 lui s8,0x1a + 3cc: 3370 fld fa2,224(a4) + 3ce: 2032 fld ft0,264(sp) + 3d0: 672d lui a4,0xb + 3d2: 2d20 fld fs0,88(a0) + 3d4: 2d20734f 0x2d20734f + 3d8: 2d20324f 0x2d20324f + 3dc: 2d20734f 0x2d20734f + 3e0: 6266 flw ft4,88(sp) + 3e2: 6975 lui s2,0x1d + 3e4: 646c flw fa1,76(s0) + 3e6: 6e69 lui t3,0x1a + 3e8: 696c2d67 0x696c2d67 + 3ec: 6762 flw fa4,24(sp) + 3ee: 2d206363 bltu zero,s2,6b4 <_start-0x7ffff94c> + 3f2: 6e66 flw ft8,88(sp) + 3f4: 74732d6f jal s10,3333a <_start-0x7ffcccc6> + 3f8: 6361 lui t1,0x18 + 3fa: 72702d6b 0x72702d6b + 3fe: 6365746f jal s0,57a34 <_start-0x7ffa85cc> + 402: 6f74 flw fa3,92(a4) + 404: 2072 fld ft0,280(sp) + 406: 662d lui a2,0xb + 408: 7865 lui a6,0xffff9 + 40a: 74706563 bltu zero,t2,b54 <_start-0x7ffff4ac> + 40e: 6f69 lui t5,0x1a + 410: 736e flw ft6,248(sp) + 412: 2d20 fld fs0,88(a0) + 414: 6e66 flw ft8,88(sp) + 416: 632d6e6f jal t3,d6a48 <_start-0x7ff295b8> + 41a: 6c61 lui s8,0x18 + 41c: 2d6c fld fa1,216(a0) + 41e: 7865 lui a6,0xffff9 + 420: 74706563 bltu zero,t2,b6a <_start-0x7ffff496> + 424: 6f69 lui t5,0x1a + 426: 736e flw ft6,248(sp) + 428: 2d20 fld fs0,88(a0) + 42a: 7666 flw fa2,120(sp) + 42c: 7369 lui t1,0xffffa + 42e: 6269 lui tp,0x1a + 430: 6c69 lui s8,0x1a + 432: 7469 lui s0,0xffffa + 434: 3d79 jal 2d2 <_start-0x7ffffd2e> + 436: 6968 flw fa0,84(a0) + 438: 6464 flw fs1,76(s0) + 43a: 6e65 lui t3,0x19 + 43c: 4100 lw s0,0(a0) + 43e: 4942 lw s2,16(sp) + 440: 495f 504c 3233 0x3233504c495f + 446: 0046 c.slli zero,0x11 + 448: 706d6f63 bltu s10,t1,b66 <_start-0x7ffff49a> + 44c: 656c flw fa1,76(a0) + 44e: 2078 fld fa4,192(s0) + 450: 6c66 flw fs8,88(sp) + 452: 0074616f jal sp,46c58 <_start-0x7ffb93a8> + 456: 6f6c flw fa1,92(a4) + 458: 676e flw fa4,216(sp) + 45a: 6c20 flw fs0,88(s0) + 45c: 20676e6f jal t3,76662 <_start-0x7ff8999e> + 460: 6e69 lui t3,0x1a + 462: 0074 addi a3,sp,12 + 464: 5f5f 6d74 6d5f 0x6d5f6d745f5f + 46a: 5f006e6f jal t3,6a5a <_start-0x7fff95a6> + 46e: 7461 lui s0,0xffff8 + 470: 7865 lui a6,0xffff9 + 472: 7469 lui s0,0xffffa + 474: 7300 flw fs0,32(a4) + 476: 6275 lui tp,0x1d + 478: 6174706f j 4828e <_start-0x7ffb7d72> + 47c: 6772 flw fa4,28(sp) + 47e: 5f00 lw s0,56(a4) + 480: 735f 6964 6964 0x69646964735f + 486: 696e flw fs2,216(sp) + 488: 0074 addi a3,sp,12 + 48a: 6f5f 6666 745f 0x745f66666f5f + 490: 5f00 lw s0,56(a4) + 492: 765f 0068 5f5f 0x5f5f0068765f + 498: 6c76 flw fs8,92(sp) + 49a: 5f00 lw s0,56(a4) + 49c: 7266 flw ft4,120(sp) + 49e: 6565 lui a0,0x19 + 4a0: 696c flw fa1,84(a0) + 4a2: 5f007473 csrrci s0,0x5f0,0 + 4a6: 6974 flw fa3,84(a0) + 4a8: 656d lui a0,0x1b + 4aa: 6f7a flw ft10,156(sp) + 4ac: 656e flw fa0,216(sp) + 4ae: 5f00 lw s0,56(a4) + 4b0: 626d lui tp,0x1b + 4b2: 74617473 csrrci s0,0x746,2 + 4b6: 5f65 li t5,-7 + 4b8: 0074 addi a3,sp,12 + 4ba: 4c5f 434f 5f4b 0x5f4b434f4c5f + 4c0: 4552 lw a0,20(sp) + 4c2: 53525543 fmadd.d fa0,ft4,fs5,fa0,unknown + 4c6: 5649 li a2,-14 + 4c8: 5f45 li t5,-15 + 4ca: 0054 addi a3,sp,4 + 4cc: 725f 6165 0064 0x646165725f + 4d2: 2e2e fld ft8,200(sp) + 4d4: 2f2e2e2f 0x2f2e2e2f + 4d8: 2e2e fld ft8,200(sp) + 4da: 2f2e2e2f 0x2f2e2e2f + 4de: 6972 flw fs2,28(sp) + 4e0: 2d766373 csrrsi t1,0x2d7,12 + 4e4: 2f636367 0x2f636367 + 4e8: 696c flw fa1,84(a0) + 4ea: 6762 flw fa4,24(sp) + 4ec: 6c2f6363 bltu t5,sp,bb2 <_start-0x7ffff44e> + 4f0: 6269 lui tp,0x1a + 4f2: 32636367 0x32636367 + 4f6: 632e flw ft6,200(sp) + 4f8: 4100 lw s0,0(a0) + 4fa: 4942 lw s2,16(sp) + 4fc: 4c5f 3650 0034 0x3436504c5f + 502: 4241 li tp,16 + 504: 5f49 li t5,-14 + 506: 4c49 li s8,18 + 508: 3350 fld fa2,160(a4) + 50a: 0032 c.slli zero,0xc + 50c: 645f 6f73 685f 0x685f6f73645f + 512: 6e61 lui t3,0x18 + 514: 6c64 flw fs1,92(s0) + 516: 0065 c.nop 25 + 518: 4d5f4d43 0x4d5f4d43 + 51c: 4445 li s0,17 + 51e: 4e41 li t3,16 + 520: 0059 c.nop 22 + 522: 6e5f 7765 5f00 0x5f0077656e5f + 528: 5f68 lw a0,124(a4) + 52a: 7265 lui tp,0xffff9 + 52c: 6e72 flw ft8,28(sp) + 52e: 665f006f j f1392 <_start-0x7ff0ec6e> + 532: 6f6c flw fa1,92(a4) + 534: 745f6b63 bltu t5,t0,c8a <_start-0x7ffff376> + 538: 5f00 lw s0,56(a4) + 53a: 745f 5f6d 6479 0x64795f6d745f + 540: 7961 lui s2,0xffff8 + 542: 5f00 lw s0,56(a4) + 544: 6c66 flw fs8,88(sp) + 546: 6761 lui a4,0x18 + 548: 5f003273 csrrc tp,0x5f0,zero + 54c: 6f69 lui t5,0x1a + 54e: 7362 flw ft6,56(sp) + 550: 4300 lw s0,0(a4) + 552: 5f4d li t5,-13 + 554: 454d li a0,19 + 556: 4c44 lw s1,28(s0) + 558: 6800574f fnmadd.s fa4,ft0,ft0,fa3,unknown + 55c: 6174 flw fa3,68(a0) + 55e: 5f62 lw t5,56(sp) + 560: 6168 flw fa0,68(a0) + 562: 5f006873 csrrsi a6,0x5f0,0 + 566: 735f 4946 454c 0x454c4946735f + 56c: 5f00 lw s0,56(a4) + 56e: 5f737973 csrrci s2,0x5f7,6 + 572: 656e flw fa0,216(sp) + 574: 7272 flw ft4,60(sp) + 576: 5f00 lw s0,56(a4) + 578: 626d lui tp,0x1b + 57a: 656c flw fa1,76(a0) + 57c: 5f6e lw t5,248(sp) + 57e: 74617473 csrrci s0,0x746,2 582: 0065 c.nop 25 - 584: 4d5f4d43 0x4d5f4d43 - 588: 4445 li s0,17 - 58a: 4e41 li t3,16 - 58c: 0059 c.nop 22 - 58e: 6e5f 7765 5f00 0x5f0077656e5f - 594: 5f68 lw a0,124(a4) - 596: 7265 lui tp,0xffff9 - 598: 6e72 flw ft8,28(sp) - 59a: 665f006f j f13fe <_start-0x7ff0ec02> - 59e: 6f6c flw fa1,92(a4) - 5a0: 745f6b63 bltu t5,t0,cf6 <_start-0x7ffff30a> - 5a4: 5f00 lw s0,56(a4) - 5a6: 745f 5f6d 6479 0x64795f6d745f - 5ac: 7961 lui s2,0xffff8 - 5ae: 5f00 lw s0,56(a4) - 5b0: 6c66 flw fs8,88(sp) - 5b2: 6761 lui a4,0x18 - 5b4: 5f003273 csrrc tp,0x5f0,zero - 5b8: 6f69 lui t5,0x1a - 5ba: 7362 flw ft6,56(sp) - 5bc: 4300 lw s0,0(a4) - 5be: 5f4d li t5,-13 - 5c0: 454d li a0,19 - 5c2: 4c44 lw s1,28(s0) - 5c4: 6800574f fnmadd.s fa4,ft0,ft0,fa3,unknown - 5c8: 6174 flw fa3,68(a0) - 5ca: 5f62 lw t5,56(sp) - 5cc: 6168 flw fa0,68(a0) - 5ce: 5f006873 csrrsi a6,0x5f0,0 - 5d2: 735f 4946 454c 0x454c4946735f - 5d8: 5f00 lw s0,56(a4) - 5da: 5f737973 csrrci s2,0x5f7,6 - 5de: 656e flw fa0,216(sp) - 5e0: 7272 flw ft4,60(sp) - 5e2: 5f00 lw s0,56(a4) - 5e4: 626d lui tp,0x1b - 5e6: 656c flw fa1,76(a0) - 5e8: 5f6e lw t5,248(sp) - 5ea: 74617473 csrrci s0,0x746,2 - 5ee: 0065 c.nop 25 - 5f0: 695f 636e 5f00 0x5f00636e695f - 5f6: 6e69 lui t3,0x1a - 5f8: 0064 addi s1,sp,12 - 5fa: 5f5f 6475 7669 0x766964755f5f - 600: 6964 flw fs1,84(a0) - 602: 5f5f0033 0x5f5f0033 - 606: 61656c63 bltu a0,s6,c1e <_start-0x7ffff3e2> - 60a: 756e flw fa0,248(sp) - 60c: 0070 addi a2,sp,12 - 60e: 6d5f 7861 6477 0x647778616d5f - 614: 725f0073 0x725f0073 - 618: 6565 lui a0,0x19 - 61a: 746e flw fs0,248(sp) - 61c: 5f00 lw s0,56(a4) - 61e: 785f 0030 5f5f 0x5f5f0030785f - 624: 3178 fld fa4,224(a0) - 626: 5f00 lw s0,56(a4) - 628: 785f 0032 5f5f 0x5f5f0032785f - 62e: 3378 fld fa4,224(a4) - 630: 5f00 lw s0,56(a4) - 632: 765f 6c61 6575 0x65756c61765f - 638: 5f00 lw s0,56(a4) - 63a: 6b656573 csrrsi a0,0x6b6,10 - 63e: 5f00 lw s0,56(a4) - 640: 7066 flw ft0,120(sp) - 642: 745f736f jal t1,f8586 <_start-0x7ff07a7a> - 646: 7300 flw fs0,32(a4) - 648: 6669 lui a2,0x1a - 64a: 7669 lui a2,0xffffa - 64c: 5f65 li t5,-7 - 64e: 625f0037 lui zero,0x625f0 - 652: 6b6c flw fa1,84(a4) - 654: 657a6973 csrrsi s2,0x657,20 - 658: 6700 flw fs0,8(a4) + 584: 695f 636e 5f00 0x5f00636e695f + 58a: 6e69 lui t3,0x1a + 58c: 0064 addi s1,sp,12 + 58e: 5f5f 6475 7669 0x766964755f5f + 594: 6964 flw fs1,84(a0) + 596: 5f5f0033 0x5f5f0033 + 59a: 61656c63 bltu a0,s6,bb2 <_start-0x7ffff44e> + 59e: 756e flw fa0,248(sp) + 5a0: 0070 addi a2,sp,12 + 5a2: 6d5f 7861 6477 0x647778616d5f + 5a8: 725f0073 0x725f0073 + 5ac: 6565 lui a0,0x19 + 5ae: 746e flw fs0,248(sp) + 5b0: 5f00 lw s0,56(a4) + 5b2: 785f 0030 5f5f 0x5f5f0030785f + 5b8: 3178 fld fa4,224(a0) + 5ba: 5f00 lw s0,56(a4) + 5bc: 785f 0032 5f5f 0x5f5f0032785f + 5c2: 3378 fld fa4,224(a4) + 5c4: 5f00 lw s0,56(a4) + 5c6: 765f 6c61 6575 0x65756c61765f + 5cc: 5f00 lw s0,56(a4) + 5ce: 6b656573 csrrsi a0,0x6b6,10 + 5d2: 5f00 lw s0,56(a4) + 5d4: 7066 flw ft0,120(sp) + 5d6: 745f736f jal t1,f851a <_start-0x7ff07ae6> + 5da: 7300 flw fs0,32(a4) + 5dc: 6669 lui a2,0x1a + 5de: 7669 lui a2,0xffffa + 5e0: 5f65 li t5,-7 + 5e2: 625f0037 lui zero,0x625f0 + 5e6: 6b6c flw fa1,84(a4) + 5e8: 657a6973 csrrsi s2,0x657,20 + 5ec: 2f00 fld fs0,24(a4) + 5ee: 7355 lui t1,0xffff5 + 5f0: 7265 lui tp,0xffff9 + 5f2: 65642f73 csrrs t5,0x656,s0 + 5f6: 6f6d lui t5,0x1b + 5f8: 636f442f 0x636f442f + 5fc: 6d75 lui s10,0x1d + 5fe: 6e65 lui t3,0x19 + 600: 7374 flw fa3,100(a4) + 602: 77656e2f 0x77656e2f + 606: 6f70 flw fa2,92(a4) + 608: 2f766c63 bltu a2,s7,900 <_start-0x7ffff700> + 60c: 6972 flw fs2,28(sp) + 60e: 2d766373 csrrsi t1,0x2d7,12 + 612: 2d756e67 0x2d756e67 + 616: 6f74 flw fa3,92(a4) + 618: 68636c6f jal s8,36c9e <_start-0x7ffc9362> + 61c: 6961 lui s2,0x18 + 61e: 2f6e fld ft10,216(sp) + 620: 7562 flw fa0,56(sp) + 622: 6c69 lui s8,0x1a + 624: 2f64 fld fs1,216(a4) + 626: 7562 flw fa0,56(sp) + 628: 6c69 lui s8,0x1a + 62a: 2d64 fld fs1,216(a0) + 62c: 2d636367 0x2d636367 + 630: 656e flw fa0,216(sp) + 632: 62696c77 0x62696c77 + 636: 732d lui t1,0xfffeb + 638: 6174 flw fa3,68(a0) + 63a: 2f326567 0x2f326567 + 63e: 6972 flw fs2,28(sp) + 640: 33766373 csrrsi t1,mhpmevent23,12 + 644: 2d32 fld fs10,264(sp) + 646: 6e75 lui t3,0x1d + 648: 776f6e6b 0x776f6e6b + 64c: 2d6e fld fs10,216(sp) + 64e: 6c65 lui s8,0x19 + 650: 2f66 fld ft10,88(sp) + 652: 696c flw fa1,84(a0) + 654: 6762 flw fa4,24(sp) + 656: 67006363 bltu zero,a6,cbc <_start-0x7ffff344> 65a: 6e65 lui t3,0x19 65c: 7265 lui tp,0xffff9 65e: 6369 lui t1,0x1a @@ -59095,7 +59069,7 @@ Disassembly of section .debug_str: 6c6: 6461 lui s0,0x18 6c8: 0064 addi s1,sp,12 6ca: 5f5f 4c55 6e6f 0x6e6f4c555f5f - 6d0: 74680067 jr 1862(a6) # ffff9746 <__BSS_END__+0x7ffe2b16> + 6d0: 74680067 jr 1862(a6) # ffff9746 <__BSS_END__+0x7ffe2b0a> 6d4: 6261 lui tp,0x18 6d6: 655f 5f71 6f70 0x6f705f71655f 6dc: 6e69 lui t3,0x1a @@ -59271,86 +59245,81 @@ Disassembly of section .debug_str: 8da: 6475 lui s0,0x1d 8dc: 7669 lui a2,0xffffa 8de: 725f 665f 0031 0x31665f725f - 8e4: 5f52 lw t5,52(sp) - 8e6: 3066 fld ft0,120(sp) - 8e8: 5f00 lw s0,56(a4) - 8ea: 5046 0x5046 - 8ec: 555f 504e 4341 0x4341504e555f - 8f2: 41525f4b fnmsub.s ft10,ft4,fs5,fs0,unknown - 8f6: 5f325f57 0x5f325f57 - 8fa: 6c66 flw fs8,88(sp) - 8fc: 5f41006f j 10ef0 <_start-0x7ffef110> - 900: 3166 fld ft2,120(sp) + 8e4: 465f 5f50 4e55 0x4e555f50465f + 8ea: 4150 lw a2,4(a0) + 8ec: 525f4b43 fmadd.d fs6,ft10,ft5,fa0,rmm + 8f0: 5741 li a4,-16 + 8f2: 325f 665f 6f6c 0x6f6c665f325f + 8f8: 4100 lw s0,0(a0) + 8fa: 665f 0031 665f 0x665f0031665f + 900: 7865 lui a6,0xffff9 902: 5f00 lw s0,56(a4) - 904: 6566 flw fa0,88(sp) - 906: 0078 addi a4,sp,12 - 908: 465f 5f50 4944 0x49445f50465f - 90e: 5f56 lw t5,116(sp) - 910: 454d li a0,19 - 912: 5441 li s0,-16 - 914: 325f 755f 6964 0x6964755f325f - 91a: 5f76 lw t5,124(sp) - 91c: 5f6e lw t5,248(sp) - 91e: 3066 fld ft0,120(sp) - 920: 5f00 lw s0,56(a4) - 922: 5046 0x5046 - 924: 445f 5649 4d5f 0x4d5f5649445f - 92a: 4145 li sp,17 - 92c: 5f54 lw a3,60(a4) - 92e: 5f32 lw t5,44(sp) - 930: 6475 lui s0,0x1d - 932: 7669 lui a2,0xffffa - 934: 6e5f 665f 0031 0x31665f6e5f - 93a: 465f 5f50 4944 0x49445f50465f - 940: 5f56 lw t5,116(sp) - 942: 454d li a0,19 - 944: 5441 li s0,-16 - 946: 325f 755f 6964 0x6964755f325f - 94c: 5f76 lw t5,124(sp) - 94e: 5f6e lw t5,248(sp) - 950: 3266 fld ft4,120(sp) - 952: 5f00 lw s0,56(a4) - 954: 5046 0x5046 - 956: 505f 4341 5f4b 0x5f4b4341505f - 95c: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm - 960: 494e lw s2,208(sp) - 962: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm - 966: 5f54 lw a3,60(a4) - 968: 465f0073 0x465f0073 - 96c: 5f50 lw a2,60(a4) - 96e: 4150 lw a2,4(a0) - 970: 435f4b43 fmadd.d fs6,ft10,fs5,fs0,rmm - 974: 4e41 li t3,16 - 976: 43494e4f fnmadd.d ft8,fs2,fs4,fs0,rmm - 97a: 4c41 li s8,16 - 97c: 695f 5f73 6974 0x69745f73695f - 982: 796e flw fs2,248(sp) - 984: 5f00 lw s0,56(a4) - 986: 5046 0x5046 - 988: 505f 4341 5f4b 0x5f4b4341505f - 98e: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm - 992: 494e lw s2,208(sp) - 994: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm - 998: 5f54 lw a3,60(a4) - 99a: 5f410063 beq sp,s4,f7a <_start-0x7ffff086> + 904: 5046 0x5046 + 906: 445f 5649 4d5f 0x4d5f5649445f + 90c: 4145 li sp,17 + 90e: 5f54 lw a3,60(a4) + 910: 5f32 lw t5,44(sp) + 912: 6475 lui s0,0x1d + 914: 7669 lui a2,0xffffa + 916: 6e5f 665f 0030 0x30665f6e5f + 91c: 465f 5f50 4944 0x49445f50465f + 922: 5f56 lw t5,116(sp) + 924: 454d li a0,19 + 926: 5441 li s0,-16 + 928: 325f 755f 6964 0x6964755f325f + 92e: 5f76 lw t5,124(sp) + 930: 5f6e lw t5,248(sp) + 932: 3166 fld ft2,120(sp) + 934: 5f00 lw s0,56(a4) + 936: 5046 0x5046 + 938: 445f 5649 4d5f 0x4d5f5649445f + 93e: 4145 li sp,17 + 940: 5f54 lw a3,60(a4) + 942: 5f32 lw t5,44(sp) + 944: 6475 lui s0,0x1d + 946: 7669 lui a2,0xffffa + 948: 6e5f 665f 0032 0x32665f6e5f + 94e: 465f 5f50 4150 0x41505f50465f + 954: 435f4b43 fmadd.d fs6,ft10,fs5,fs0,rmm + 958: 4e41 li t3,16 + 95a: 43494e4f fnmadd.d ft8,fs2,fs4,fs0,rmm + 95e: 4c41 li s8,16 + 960: 545f 735f 5f00 0x5f00735f545f + 966: 5046 0x5046 + 968: 505f 4341 5f4b 0x5f4b4341505f + 96e: 4f4e4143 fmadd.q ft2,ft8,fs4,fs1,rmm + 972: 494e lw s2,208(sp) + 974: 5f4c4143 fmadd.q ft2,fs8,fs4,fa1,rmm + 978: 7369 lui t1,0xffffa + 97a: 745f 6e69 0079 0x796e69745f + 980: 465f 5f50 4150 0x41505f50465f + 986: 435f4b43 fmadd.d fs6,ft10,fs5,fs0,rmm + 98a: 4e41 li t3,16 + 98c: 43494e4f fnmadd.d ft8,fs2,fs4,fs0,rmm + 990: 4c41 li s8,16 + 992: 545f 635f 4100 0x4100635f545f + 998: 665f 0030 5f42 0x5f420030665f 99e: 3066 fld ft0,120(sp) - 9a0: 4200 lw s0,0(a2) - 9a2: 665f 0030 2e2e 0x2e2e0030665f - 9a8: 2f2e2e2f 0x2f2e2e2f - 9ac: 2e2e fld ft8,200(sp) - 9ae: 2f2e2e2f 0x2f2e2e2f - 9b2: 6972 flw fs2,28(sp) - 9b4: 2d766373 csrrsi t1,0x2d7,12 - 9b8: 2f636367 0x2f636367 - 9bc: 696c flw fa1,84(a0) - 9be: 6762 flw fa4,24(sp) - 9c0: 732f6363 bltu t5,s2,10e6 <_start-0x7fffef1a> - 9c4: 2d74666f jal a2,4749a <_start-0x7ffb8b66> - 9c8: 7066 flw ft0,120(sp) - 9ca: 7669642f 0x7669642f - 9ce: 6664 flw fs1,76(a2) - 9d0: 00632e33 slt t3,t1,t1 - 9d4: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm + 9a0: 2e00 fld fs0,24(a2) + 9a2: 2f2e fld ft10,200(sp) + 9a4: 2e2e fld ft8,200(sp) + 9a6: 2f2e2e2f 0x2f2e2e2f + 9aa: 2e2e fld ft8,200(sp) + 9ac: 7369722f 0x7369722f + 9b0: 672d7663 bgeu s10,s2,101c <_start-0x7fffefe4> + 9b4: 6c2f6363 bltu t5,sp,107a <_start-0x7fffef86> + 9b8: 6269 lui tp,0x1a + 9ba: 2f636367 0x2f636367 + 9be: 74666f73 csrrsi t5,0x746,12 + 9c2: 662d lui a2,0xb + 9c4: 2f70 fld fa2,216(a4) + 9c6: 6964 flw fs1,84(a0) + 9c8: 6476 flw fs0,92(sp) + 9ca: 3366 fld ft6,120(sp) + 9cc: 632e flw ft6,200(sp) + 9ce: 5200 lw s0,32(a2) + 9d0: 665f 0030 4e47 0x4e470030665f + 9d6: 2055 jal a7a <_start-0x7ffff586> 9d8: 20373143 fmadd.s ft2,fa4,ft3,ft4,rup 9dc: 2e39 jal cfa <_start-0x7ffff306> 9de: 2e32 fld ft8,264(sp) @@ -60097,7 +60066,7 @@ Disassembly of section .debug_loc: 30: 0006 c.slli zero,0x1 32: 935c 0x935c 34: 5d04 lw s1,56(a0) - 36: 00740493 addi s1,s0,7 # ffffa007 <__BSS_END__+0x7ffe33d7> + 36: 00740493 addi s1,s0,7 # ffffa007 <__BSS_END__+0x7ffe33cb> 3a: 0000 unimp 3c: 00f8 addi a4,sp,76 3e: 0000 unimp @@ -60139,7 +60108,7 @@ Disassembly of section .debug_loc: 90: 0006 c.slli zero,0x1 92: 935c 0x935c 94: 5d04 lw s1,56(a0) - 96: 03180493 addi s1,a6,49 # ffff9031 <__BSS_END__+0x7ffe2401> + 96: 03180493 addi s1,a6,49 # ffff9031 <__BSS_END__+0x7ffe23f5> 9a: 0000 unimp 9c: 0428 addi a0,sp,520 9e: 0000 unimp @@ -60472,7 +60441,7 @@ Disassembly of section .debug_loc: 374: 0000 unimp 376: 0001 nop 378: 0c5d addi s8,s8,23 - 37a: cc000003 lb zero,-832(zero) # fffffcc0 <__BSS_END__+0x7ffe9090> + 37a: cc000003 lb zero,-832(zero) # fffffcc0 <__BSS_END__+0x7ffe9084> 37e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 382: 5600 lw s0,40(a2) 384: 0428 addi a0,sp,520 @@ -60873,7 +60842,7 @@ Disassembly of section .debug_loc: 706: 009f 0000 0000 0x9f 70c: 0000 unimp 70e: 2800 fld fs0,16(s0) - 710: a8000003 lb zero,-1408(zero) # fffffa80 <__BSS_END__+0x7ffe8e50> + 710: a8000003 lb zero,-1408(zero) # fffffa80 <__BSS_END__+0x7ffe8e44> 714: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 718: 5a00 lw s0,48(a2) 71a: 03a8 addi a0,sp,456 @@ -60912,7 +60881,7 @@ Disassembly of section .debug_loc: 76e: 0000 unimp 770: 0000 unimp 772: 7000 flw fs0,32(s0) - 774: 94000003 lb zero,-1728(zero) # fffff940 <__BSS_END__+0x7ffe8d10> + 774: 94000003 lb zero,-1728(zero) # fffff940 <__BSS_END__+0x7ffe8d04> 778: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 77c: 5e00 lw s0,56(a2) 77e: 0394 addi a3,sp,448 @@ -60950,7 +60919,7 @@ Disassembly of section .debug_loc: 7d2: 0000 unimp 7d4: 0001 nop 7d6: 845d srai s0,s0,0x17 - 7d8: 90000003 lb zero,-1792(zero) # fffff900 <__BSS_END__+0x7ffe8cd0> + 7d8: 90000003 lb zero,-1792(zero) # fffff900 <__BSS_END__+0x7ffe8cc4> 7dc: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 7e0: 5f00 lw s0,56(a4) 7e2: 0394 addi a3,sp,448 @@ -60970,7 +60939,7 @@ Disassembly of section .debug_loc: 806: 0000 unimp 808: 0001 nop 80a: c45c sw a5,12(s0) - 80c: cc000003 lb zero,-832(zero) # fffffcc0 <__BSS_END__+0x7ffe9090> + 80c: cc000003 lb zero,-832(zero) # fffffcc0 <__BSS_END__+0x7ffe9084> 810: 0a000003 lb zero,160(zero) # a0 <_start-0x7fffff60> 814: 7600 flw fs0,40(a2) 816: 4000 lw s0,0(s0) @@ -60999,7 +60968,7 @@ Disassembly of section .debug_loc: 850: 0000 unimp 852: 0001 nop 854: dc60 sw s0,124(s0) - 856: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe9210> + 856: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe9204> 85a: 09000003 lb zero,144(zero) # 90 <_start-0x7fffff70> 85e: 8c00 0x8c00 860: 7a7f 0x7a7f @@ -61023,7 +60992,7 @@ Disassembly of section .debug_loc: 884: 009f 0000 0000 0x9f 88a: 0000 unimp 88c: d000 sw s0,32(s0) - 88e: f0000003 lb zero,-256(zero) # ffffff00 <__BSS_END__+0x7ffe92d0> + 88e: f0000003 lb zero,-256(zero) # ffffff00 <__BSS_END__+0x7ffe92c4> 892: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 896: 5d00 lw s0,56(a0) ... @@ -61037,7 +61006,7 @@ Disassembly of section .debug_loc: 8ae: 0000 unimp 8b0: 0000 unimp 8b2: bc00 fsd fs0,56(s0) - 8b4: d8000003 lb zero,-640(zero) # fffffd80 <__BSS_END__+0x7ffe9150> + 8b4: d8000003 lb zero,-640(zero) # fffffd80 <__BSS_END__+0x7ffe9144> 8b8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 8bc: 6000 flw fs0,0(s0) 8be: 03d8 addi a4,sp,452 @@ -61083,7 +61052,7 @@ Disassembly of section .debug_loc: 914: 0000 unimp 916: 0000 unimp 918: c400 sw s0,8(s0) - 91a: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe9210> + 91a: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe9204> 91e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 922: 5c00 lw s0,56(s0) 924: 03e4 addi s1,sp,460 @@ -61473,7 +61442,7 @@ Disassembly of section .debug_loc: ca2: 0000 unimp ca4: 0600 addi s0,sp,768 ca6: 5c00 lw s0,56(s0) - ca8: 935d0493 addi s1,s10,-1739 # fffe8935 <__BSS_END__+0x7ffd1d05> + ca8: 935d0493 addi s1,s10,-1739 # fffe8935 <__BSS_END__+0x7ffd1cf9> cac: 6804 flw fs1,16(s0) cae: 0000 unimp cb0: e000 fsw fs0,0(s0) @@ -61548,7 +61517,7 @@ Disassembly of section .debug_loc: d6a: 0000 unimp d6c: 0600 addi s0,sp,768 d6e: 5c00 lw s0,56(s0) - d70: 935e0493 addi s1,t3,-1739 # fffe8935 <__BSS_END__+0x7ffd1d05> + d70: 935e0493 addi s1,t3,-1739 # fffe8935 <__BSS_END__+0x7ffd1cf9> d74: e004 fsw fs1,0(s0) d76: 0000 unimp d78: e800 fsw fs0,16(s0) @@ -62215,7 +62184,7 @@ Disassembly of section .debug_loc: 135a: 005f 0000 0000 0x5f 1360: 0000 unimp 1362: cc00 sw s0,24(s0) - 1364: e0000003 lb zero,-512(zero) # fffffe00 <__BSS_END__+0x7ffe91d0> + 1364: e0000003 lb zero,-512(zero) # fffffe00 <__BSS_END__+0x7ffe91c4> 1368: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 136c: 5e00 lw s0,56(a2) 136e: 03e8 addi a0,sp,460 @@ -62224,7 +62193,7 @@ Disassembly of section .debug_loc: 1374: 0000 unimp 1376: 0001 nop 1378: ec5c fsw fa5,28(s0) - 137a: f0000003 lb zero,-256(zero) # ffffff00 <__BSS_END__+0x7ffe92d0> + 137a: f0000003 lb zero,-256(zero) # ffffff00 <__BSS_END__+0x7ffe92c4> 137e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 1382: 5e00 lw s0,56(a2) ... @@ -62340,7 +62309,7 @@ Disassembly of section .debug_loc: 14a4: 009f 0000 0000 0x9f 14aa: 0000 unimp 14ac: 8c00 0x8c00 - 14ae: c4000003 lb zero,-960(zero) # fffffc40 <__BSS_END__+0x7ffe9010> + 14ae: c4000003 lb zero,-960(zero) # fffffc40 <__BSS_END__+0x7ffe9004> 14b2: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 14b6: 5e00 lw s0,56(a2) ... @@ -62354,7 +62323,7 @@ Disassembly of section .debug_loc: 14ce: 0000 unimp 14d0: 0000 unimp 14d2: 9000 0x9000 - 14d4: b0000003 lb zero,-1280(zero) # fffffb00 <__BSS_END__+0x7ffe8ed0> + 14d4: b0000003 lb zero,-1280(zero) # fffffb00 <__BSS_END__+0x7ffe8ec4> 14d8: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 14dc: 5f00 lw s0,56(a4) ... @@ -62368,7 +62337,7 @@ Disassembly of section .debug_loc: 14f4: 0000 unimp 14f6: 0000 unimp 14f8: 7c00 flw fs0,56(s0) - 14fa: 94000003 lb zero,-1728(zero) # fffff940 <__BSS_END__+0x7ffe8d10> + 14fa: 94000003 lb zero,-1728(zero) # fffff940 <__BSS_END__+0x7ffe8d04> 14fe: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 1502: 6000 flw fs0,0(s0) ... @@ -62390,7 +62359,7 @@ Disassembly of section .debug_loc: 1536: 009f 0000 0000 0x9f 153c: 0000 unimp 153e: 8400 0x8400 - 1540: 98000003 lb zero,-1664(zero) # fffff980 <__BSS_END__+0x7ffe8d50> + 1540: 98000003 lb zero,-1664(zero) # fffff980 <__BSS_END__+0x7ffe8d44> 1544: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 1548: 6100 flw fs0,0(a0) ... @@ -62428,7 +62397,7 @@ Disassembly of section .debug_loc: 15a0: 0006 c.slli zero,0x1 15a2: 935a add t1,t1,s6 15a4: 5b04 lw s1,48(a4) - 15a6: 01040493 addi s1,s0,16 # ffff7010 <__BSS_END__+0x7ffe03e0> + 15a6: 01040493 addi s1,s0,16 # ffff7010 <__BSS_END__+0x7ffe03d4> 15aa: 0000 unimp 15ac: 013c addi a5,sp,136 15ae: 0000 unimp @@ -62439,7 +62408,7 @@ Disassembly of section .debug_loc: 15ba: 0000 unimp 15bc: 0000013f 935a0006 0x935a00060000013f 15c4: 5b04 lw s1,48(a4) - 15c6: 013f0493 addi s1,t5,19 # 1a013 <_start-0x7ffe5fed> + 15c6: 013f0493 addi s1,t5,19 # 1b013 <_start-0x7ffe4fed> 15ca: 0000 unimp 15cc: 0158 addi a4,sp,132 15ce: 0000 unimp @@ -63514,7 +63483,7 @@ Disassembly of section .debug_loc: 1f4e: 0000 unimp 1f50: 0001 nop 1f52: 7858 flw fa4,52(s0) - 1f54: ac000003 lb zero,-1344(zero) # fffffac0 <__BSS_END__+0x7ffe8e90> + 1f54: ac000003 lb zero,-1344(zero) # fffffac0 <__BSS_END__+0x7ffe8e84> 1f58: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 1f5c: 5800 lw s0,48(s0) 1f5e: 03b4 addi a3,sp,456 @@ -63594,7 +63563,7 @@ Disassembly of section .debug_loc: 2004: 0000 unimp 2006: 0000 unimp 2008: 3c00 fld fs0,56(s0) - 200a: cc000003 lb zero,-832(zero) # fffffcc0 <__BSS_END__+0x7ffe9090> + 200a: cc000003 lb zero,-832(zero) # fffffcc0 <__BSS_END__+0x7ffe9084> 200e: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 2012: 5c00 lw s0,56(s0) 2014: 047c addi a5,sp,524 @@ -63615,7 +63584,7 @@ Disassembly of section .debug_loc: 2038: 0000 unimp 203a: 0001 nop 203c: a860 fsd fs0,208(s0) - 203e: b8000003 lb zero,-1152(zero) # fffffb80 <__BSS_END__+0x7ffe8f50> + 203e: b8000003 lb zero,-1152(zero) # fffffb80 <__BSS_END__+0x7ffe8f44> 2042: 24000003 lb zero,576(zero) # 240 <_start-0x7ffffdc0> 2046: 8f00 0x8f00 2048: 7500 flw fs0,40(a0) @@ -63898,7 +63867,7 @@ Disassembly of section .debug_loc: 22e4: 0000 unimp 22e6: 0000 unimp 22e8: 0400 addi s0,sp,512 - 22ea: c4000003 lb zero,-960(zero) # fffffc40 <__BSS_END__+0x7ffe9010> + 22ea: c4000003 lb zero,-960(zero) # fffffc40 <__BSS_END__+0x7ffe9004> 22ee: 0004 0x4 22f0: 0100 addi s0,sp,128 22f2: 5600 lw s0,40(a2) @@ -63961,7 +63930,7 @@ Disassembly of section .debug_loc: 2382: 005f 0000 0000 0x5f 2388: 0000 unimp 238a: a000 fsd fs0,0(s0) - 238c: a4000003 lb zero,-1472(zero) # fffffa40 <__BSS_END__+0x7ffe8e10> + 238c: a4000003 lb zero,-1472(zero) # fffffa40 <__BSS_END__+0x7ffe8e04> 2390: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 2394: 5f00 lw s0,56(a4) ... @@ -63975,7 +63944,7 @@ Disassembly of section .debug_loc: 23ac: 0000 unimp 23ae: 0000 unimp 23b0: bc00 fsd fs0,56(s0) - 23b2: 88000003 lb zero,-1920(zero) # fffff880 <__BSS_END__+0x7ffe8c50> + 23b2: 88000003 lb zero,-1920(zero) # fffff880 <__BSS_END__+0x7ffe8c44> 23b6: 0004 0x4 23b8: 0100 addi s0,sp,128 23ba: 5a00 lw s0,48(a2) @@ -64004,7 +63973,7 @@ Disassembly of section .debug_loc: 23f0: 009f 0000 0000 0x9f 23f6: 0000 unimp 23f8: c000 sw s0,0(s0) - 23fa: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe9210> + 23fa: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe9204> 23fe: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 2402: 6f00 flw fs0,24(a4) 2404: 03e4 addi s1,sp,460 @@ -64029,7 +63998,7 @@ Disassembly of section .debug_loc: 242c: 005f 0000 0000 0x5f 2432: 0000 unimp 2434: bc00 fsd fs0,56(s0) - 2436: c8000003 lb zero,-896(zero) # fffffc80 <__BSS_END__+0x7ffe9050> + 2436: c8000003 lb zero,-896(zero) # fffffc80 <__BSS_END__+0x7ffe9044> 243a: 06000003 lb zero,96(zero) # 60 <_start-0x7fffffa0> 243e: 7800 flw fs0,48(s0) 2440: 7a00 flw fs0,48(a2) @@ -65235,7 +65204,7 @@ Disassembly of section .debug_loc: 2f08: 0000 unimp 2f0a: 0000 unimp 2f0c: 0c00 addi s0,sp,528 - 2f0e: 94000003 lb zero,-1728(zero) # fffff940 <__BSS_END__+0x7ffe8d10> + 2f0e: 94000003 lb zero,-1728(zero) # fffff940 <__BSS_END__+0x7ffe8d04> 2f12: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 2f16: 6f00 flw fs0,24(a4) ... @@ -65494,7 +65463,7 @@ Disassembly of section .debug_loc: 317c: 0000 unimp 317e: 0001 nop 3180: 3c59 jal 2c16 <_start-0x7fffd3ea> - 3182: 90000003 lb zero,-1792(zero) # fffff900 <__BSS_END__+0x7ffe8cd0> + 3182: 90000003 lb zero,-1792(zero) # fffff900 <__BSS_END__+0x7ffe8cc4> 3186: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 318a: 5900 lw s0,48(a0) ... @@ -65508,7 +65477,7 @@ Disassembly of section .debug_loc: 31a2: 0000 unimp 31a4: 0000 unimp 31a6: 3000 fld fs0,32(s0) - 31a8: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9290> + 31a8: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9284> 31ac: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 31b0: 5600 lw s0,40(a2) 31b2: 04d8 addi a4,sp,580 @@ -65535,7 +65504,7 @@ Disassembly of section .debug_loc: 31e6: 0000 unimp 31e8: 0000 unimp 31ea: 6400 flw fs0,8(s0) - 31ec: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9290> + 31ec: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9284> 31f0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 31f4: 6200 flw fs0,0(a2) 31f6: 04d8 addi a4,sp,580 @@ -65671,7 +65640,7 @@ Disassembly of section .debug_loc: 3336: 009f 0000 0000 0x9f 333c: 0000 unimp 333e: 7c00 flw fs0,56(s0) - 3340: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9290> + 3340: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9284> 3344: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> 3348: 3900 fld fs0,48(a0) 334a: d89f 0004 e000 0xe0000004d89f @@ -65681,7 +65650,7 @@ Disassembly of section .debug_loc: 3356: 009f 0000 0000 0x9f 335c: 0000 unimp 335e: 7c00 flw fs0,56(s0) - 3360: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9290> + 3360: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9284> 3364: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> 3368: 4700 lw s0,8(a4) 336a: d89f 0004 e000 0xe0000004d89f @@ -65691,7 +65660,7 @@ Disassembly of section .debug_loc: 3376: 009f 0000 0000 0x9f 337c: 0000 unimp 337e: 7c00 flw fs0,56(s0) - 3380: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9290> + 3380: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9284> 3384: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> 3388: 3100 fld fs0,32(a0) 338a: d89f 0004 e000 0xe0000004d89f @@ -65701,13 +65670,13 @@ Disassembly of section .debug_loc: 3396: 009f 0000 0000 0x9f 339c: 0000 unimp 339e: 7c00 flw fs0,56(s0) - 33a0: cc000003 lb zero,-832(zero) # fffffcc0 <__BSS_END__+0x7ffe9090> + 33a0: cc000003 lb zero,-832(zero) # fffffcc0 <__BSS_END__+0x7ffe9084> 33a4: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> 33a8: 3100 fld fs0,32(a0) 33aa: 009f 0000 0000 0x9f 33b0: 0000 unimp 33b2: 7c00 flw fs0,56(s0) - 33b4: ac000003 lb zero,-1344(zero) # fffffac0 <__BSS_END__+0x7ffe8e90> + 33b4: ac000003 lb zero,-1344(zero) # fffffac0 <__BSS_END__+0x7ffe8e84> 33b8: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> 33bc: 8c00 0x8c00 33be: 3900 fld fs0,48(a0) @@ -65785,7 +65754,7 @@ Disassembly of section .debug_loc: 346a: 0000 unimp 346c: 936e000b 0x936e000b 3470: 6f04 flw fs1,24(a4) - 3472: 93550493 addi s1,a0,-1739 # fffea935 <__BSS_END__+0x7ffd3d05> + 3472: 93550493 addi s1,a0,-1739 # fffea935 <__BSS_END__+0x7ffd3cf9> 3476: 9304 0x9304 3478: 4c04 lw s1,24(s0) 347a: 0000 unimp @@ -65795,7 +65764,7 @@ Disassembly of section .debug_loc: 3482: 6e00 flw fs0,24(a2) 3484: 936f0493 addi s1,t5,-1738 3488: 5504 lw s1,40(a0) - 348a: 936d0493 addi s1,s10,-1738 # fffe8936 <__BSS_END__+0x7ffd1d06> + 348a: 936d0493 addi s1,s10,-1738 # fffe8936 <__BSS_END__+0x7ffd1cfa> 348e: 0004 0x4 3490: 0000 unimp 3492: 0000 unimp @@ -66593,7 +66562,7 @@ Disassembly of section .debug_loc: 3bea: 937f 0x937f 3bec: 7204 flw fs1,32(a2) 3bee: 7f94 flw fa3,56(a5) - 3bf0: 98720493 addi s1,tp,-1657 # fffff987 <__BSS_END__+0x7ffe8d57> + 3bf0: 98720493 addi s1,tp,-1657 # fffff987 <__BSS_END__+0x7ffe8d4b> 3bf4: 937f 0x937f 3bf6: 5f04 lw s1,56(a4) 3bf8: 00000493 li s1,0 @@ -66632,7 +66601,7 @@ Disassembly of section .debug_loc: 3c4c: 0000 unimp 3c4e: 00ec addi a1,sp,76 3c50: 0000 unimp - 3c52: ff090003 lb zero,-16(s2) # fffeaff0 <__BSS_END__+0x7ffd43c0> + 3c52: ff090003 lb zero,-16(s2) # fffeaff0 <__BSS_END__+0x7ffd43b4> 3c56: 009f 0000 0000 0x9f 3c5c: 0000 unimp 3c5e: e400 fsw fs0,8(s0) @@ -66840,7 +66809,7 @@ Disassembly of section .debug_loc: 3e3c: 0000 unimp 3e3e: 0001 nop 3e40: 9c5a add s8,s8,s6 - 3e42: a4000003 lb zero,-1472(zero) # fffffa40 <__BSS_END__+0x7ffe8e10> + 3e42: a4000003 lb zero,-1472(zero) # fffffa40 <__BSS_END__+0x7ffe8e04> 3e46: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> 3e4a: 5a00 lw s0,48(a2) 3e4c: 03ac addi a1,sp,456 @@ -66871,7 +66840,7 @@ Disassembly of section .debug_loc: 3e8c: 0000 unimp 3e8e: 0001 nop 3e90: c45d beqz s0,3f3e <_start-0x7fffc0c2> - 3e92: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe9210> + 3e92: e4000003 lb zero,-448(zero) # fffffe40 <__BSS_END__+0x7ffe9204> 3e96: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> 3e9a: 7a00 flw fs0,48(a2) 3e9c: 4f74 lw a3,92(a4) @@ -66957,7 +66926,7 @@ Disassembly of section .debug_loc: 3f66: 0000 unimp 3f68: 0001 nop 3f6a: d05d beqz s0,3f10 <_start-0x7fffc0f0> - 3f6c: d8000003 lb zero,-640(zero) # fffffd80 <__BSS_END__+0x7ffe9150> + 3f6c: d8000003 lb zero,-640(zero) # fffffd80 <__BSS_END__+0x7ffe9144> 3f70: 03000003 lb zero,48(zero) # 30 <_start-0x7fffffd0> 3f74: 7d00 flw fs0,56(a0) 3f76: 9f01 0x9f01 @@ -67287,7 +67256,7 @@ Disassembly of section .debug_loc: 4228: 1a00 addi s0,sp,304 422a: 007a c.slli zero,0x1e 422c: 2540 fld fs0,136(a0) - 422e: 84220083 lb ra,-1982(tp) # fffff842 <__BSS_END__+0x7ffe8c12> + 422e: 84220083 lb ra,-1982(tp) # fffff842 <__BSS_END__+0x7ffe8c06> 4232: 1a7f 0x1a7f 4234: 2440 fld fs0,136(s0) 4236: 9f22 add t5,t5,s0 @@ -67517,7 +67486,7 @@ Disassembly of section .debug_loc: 4430: 7f80 flw fs0,56(a5) 4432: 8c06 mv s8,ra 4434: 1a00 addi s0,sp,304 - 4436: 8c1e0083 lb ra,-1855(t3) # fffe88c1 <__BSS_END__+0x7ffd1c91> + 4436: 8c1e0083 lb ra,-1855(t3) # fffe88c1 <__BSS_END__+0x7ffd1c85> 443a: 1a00 addi s0,sp,304 443c: 8091 srli s1,s1,0x4 443e: 067f 0x67f @@ -78635,7 +78604,7 @@ Disassembly of section .debug_loc: a58c: 7f90 flw fa2,56(a5) a58e: 4006 0x4006 a590: 0c22244b 0xc22244b - a594: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8bd0> + a594: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8bc4> a598: 9f2c 0x9f2c a59a: 0c08 addi a0,sp,528 a59c: 0000 unimp @@ -78663,7 +78632,7 @@ Disassembly of section .debug_loc: a5d0: 7f90 flw fa2,56(a5) a5d2: 4006 0x4006 a5d4: 0c22244b 0xc22244b - a5d8: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8bd0> + a5d8: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8bc4> a5dc: 402c lw a1,64(s0) a5de: 2d22244b 0x2d22244b a5e2: 4b40 lw s0,20(a4) @@ -79309,7 +79278,7 @@ Disassembly of section .debug_loc: abe0: 0000 unimp abe2: 0a30 addi a2,sp,280 abe4: 0000 unimp - abe6: 7f7b0003 lb zero,2039(s6) # fffe97f7 <__BSS_END__+0x7ffd2bc7> + abe6: 7f7b0003 lb zero,2039(s6) # fffe97f7 <__BSS_END__+0x7ffd2bbb> abea: 309f 000a f000 0xf000000a309f abf0: 000a c.slli zero,0x2 abf2: 0100 addi s0,sp,128 @@ -79913,7 +79882,7 @@ Disassembly of section .debug_loc: b11e: 9358 0x9358 b120: 9104 0x9104 b122: 7fac flw fa1,120(a5) - b124: 03540493 addi s1,s0,53 # ffff8035 <__BSS_END__+0x7ffe1405> + b124: 03540493 addi s1,s0,53 # ffff8035 <__BSS_END__+0x7ffe13f9> b128: 0000 unimp b12a: 0384 addi s1,sp,448 b12c: 0000 unimp @@ -79924,7 +79893,7 @@ Disassembly of section .debug_loc: b13a: ac910493 addi s1,sp,-1335 b13e: 937f 0x937f b140: 8404 0x8404 - b142: 88000003 lb zero,-1920(zero) # fffff880 <__BSS_END__+0x7ffe8c50> + b142: 88000003 lb zero,-1920(zero) # fffff880 <__BSS_END__+0x7ffe8c44> b146: 0f000003 lb zero,240(zero) # f0 <_start-0x7fffff10> b14a: 7200 flw fs0,32(a2) b14c: 9350 0x9350 @@ -80235,7 +80204,7 @@ Disassembly of section .debug_loc: b410: 009f 0000 0000 0x9f b416: 0000 unimp b418: a800 fsd fs0,16(s0) - b41a: b8000003 lb zero,-1152(zero) # fffffb80 <__BSS_END__+0x7ffe8f50> + b41a: b8000003 lb zero,-1152(zero) # fffffb80 <__BSS_END__+0x7ffe8f44> b41e: 08000003 lb zero,128(zero) # 80 <_start-0x7fffff80> b422: 0800 addi s0,sp,16 b424: 7b20 flw fs0,112(a4) @@ -80251,7 +80220,7 @@ Disassembly of section .debug_loc: b43c: 009f 0000 0000 0x9f b442: 0000 unimp b444: a800 fsd fs0,16(s0) - b446: b8000003 lb zero,-1152(zero) # fffffb80 <__BSS_END__+0x7ffe8f50> + b446: b8000003 lb zero,-1152(zero) # fffffb80 <__BSS_END__+0x7ffe8f44> b44a: 05000003 lb zero,80(zero) # 50 <_start-0x7fffffb0> b44e: 7b00 flw fs0,48(a4) b450: 4f00 lw s0,24(a4) @@ -80265,7 +80234,7 @@ Disassembly of section .debug_loc: b462: 009f 0000 0000 0x9f b468: 0000 unimp b46a: a800 fsd fs0,16(s0) - b46c: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9290> + b46c: ec000003 lb zero,-320(zero) # fffffec0 <__BSS_END__+0x7ffe9284> b470: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> b474: 6d00 flw fs0,24(a0) b476: 03fc addi a5,sp,460 @@ -80292,7 +80261,7 @@ Disassembly of section .debug_loc: b4a6: 0000 unimp b4a8: 0001 nop b4aa: cc5c sw a5,28(s0) - b4ac: d8000003 lb zero,-640(zero) # fffffd80 <__BSS_END__+0x7ffe9150> + b4ac: d8000003 lb zero,-640(zero) # fffffd80 <__BSS_END__+0x7ffe9144> b4b0: 01000003 lb zero,16(zero) # 10 <_start-0x7ffffff0> b4b4: 5c00 lw s0,56(s0) b4b6: 03d8 addi a4,sp,452 @@ -80352,7 +80321,7 @@ Disassembly of section .debug_loc: b52e: 0000 unimp b530: 0000 unimp b532: a800 fsd fs0,16(s0) - b534: b0000003 lb zero,-1280(zero) # fffffb00 <__BSS_END__+0x7ffe8ed0> + b534: b0000003 lb zero,-1280(zero) # fffffb00 <__BSS_END__+0x7ffe8ec4> b538: 02000003 lb zero,32(zero) # 20 <_start-0x7fffffe0> b53c: 3000 fld fs0,32(s0) b53e: b09f 0003 b400 0xb4000003b09f @@ -81650,7 +81619,7 @@ Disassembly of section .debug_loc: c16e: 000d c.nop 3 c170: 0800 addi s0,sp,16 c172: 5e00 lw s0,56(a2) - c174: 93560493 addi s1,a2,-1739 # fffe8935 <__BSS_END__+0x7ffd1d05> + c174: 93560493 addi s1,a2,-1739 # fffe8935 <__BSS_END__+0x7ffd1cf9> c178: 9304 0x9304 c17a: 8404 0x8404 c17c: 000d c.nop 3 @@ -81870,7 +81839,7 @@ Disassembly of section .debug_loc: c380: 0000 unimp c382: 0f18 addi a4,sp,912 c384: 0000 unimp - c386: 01770003 lb zero,23(a4) # fffeb017 <__BSS_END__+0x7ffd43e7> + c386: 01770003 lb zero,23(a4) # fffeb017 <__BSS_END__+0x7ffd43db> c38a: 189f 000f 1c00 0x1c00000f189f c390: 0100000f fence w,unknown c394: 5700 lw s0,40(a4) @@ -82015,7 +81984,7 @@ Disassembly of section .debug_loc: c4fc: 5600 lw s0,40(a2) c4fe: 936f0493 addi s1,t5,-1738 c502: 5504 lw s1,40(a0) - c504: 10780493 addi s1,a6,263 # fffe9107 <__BSS_END__+0x7ffd24d7> + c504: 10780493 addi s1,a6,263 # fffe9107 <__BSS_END__+0x7ffd24cb> c508: 0000 unimp c50a: 10b4 addi a3,sp,104 c50c: 0000 unimp @@ -83036,7 +83005,7 @@ Disassembly of section .debug_loc: ce9a: 5091 li ra,-28 ce9c: 4006 0x4006 ce9e: 0c22244b 0xc22244b - cea2: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8bd0> + cea2: 80000003 lb zero,-2048(zero) # fffff800 <__BSS_END__+0x7ffe8bc4> cea6: 402c lw a1,64(s0) cea8: 2d22244b 0x2d22244b ceac: 4b40 lw s0,20(a4) @@ -84729,7 +84698,7 @@ Disassembly of section .debug_loc: de4a: 0000 unimp de4c: 0168 addi a0,sp,140 de4e: 0000 unimp - de50: 7f7f0003 lb zero,2039(t5) # fffe97f7 <__BSS_END__+0x7ffd2bc7> + de50: 7f7f0003 lb zero,2039(t5) # fffe97f7 <__BSS_END__+0x7ffd2bbb> de54: 689f 0001 8000 0x80000001689f de5a: 0001 nop de5c: 0100 addi s0,sp,128 diff --git a/runtime/mains/simple/vx_simple_main.elf b/runtime/mains/simple/vx_simple_main.elf index fb94b489f1e52aa8862bfa19c7071301a91628ed..1406072ac36a079fc97818cc32ef91066032f42d 100644 GIT binary patch delta 26106 zcmc(H3qVxW*8kc2%rFQDBOoskkcSeXkWb3jsQAc8vCMoGDELYgQZzDahCspcCc4dI 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+:106AD8009C4C01809C4C01809C4C01809C4C01800A +:106AE800FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000AC +:106AF8000100415343494900000000000000000024 +:106B0800000000000000000000000000000000007D +:106B18000000415343494900000000000000000004 +:106B2800000000000000000000000000000000005D +:046B38000000000059 :106B4000000000000000F03F0000000000002440B2 :106B50000000000000005043A061018000000070B0 :106B60000000001000000020A0610180FFFFFFFF77 diff --git a/runtime/startup/vx_start.s b/runtime/startup/vx_start.s index 3cd421df..22f4d4af 100644 --- a/runtime/startup/vx_start.s +++ b/runtime/startup/vx_start.s @@ -20,22 +20,22 @@ _start: # Initialize SP # la sp, __stack_top la a1, vx_set_sp - li a0, 32 + li a0, 4 .word 0x00b5106b # wspawn a0(numWarps), a1(PC SPAWN) jal vx_set_sp - li a0, 1 - .word 0x0005006b # tmc 1 + # li a0, 1 + # .word 0x0005006b # tmc 1 # Initialize global pointerp # call __cxx_global_var_init # Clear the bss segment - la a0, _edata - la a2, _end - sub a2, a2, a0 - li a1, 0 - call memset - la a0, __libc_fini_array # Register global termination functions - call atexit # to be called upon exit - call __libc_init_array # Run global initialization functions + # la a0, _edata + # la a2, _end + # sub a2, a2, a0 + # li a1, 0 + # call memset + # la a0, __libc_fini_array # Register global termination functions + # call atexit # to be called upon exit + # call __libc_init_array # Run global initialization functions # li a0, 4 # .word 0x0005006b # tmc 4 call main @@ -46,7 +46,7 @@ _start: .type vx_set_sp, @function .global vx_set_sp vx_set_sp: - li a0, 32 + li a0, 4 .word 0x0005006b # tmc 4 .option push @@ -55,7 +55,7 @@ vx_set_sp: addi gp, gp, %pcrel_lo(1b) .option pop - csrr a3, 0x21 # get wid + csrr a3, 0x22 # get wid slli a3, a3, 0x1a # shift by wid csrr a2, 0x20 # get tid slli a1, a2, 10 # multiply tid by 1024 diff --git a/runtime/tests/tests.c b/runtime/tests/tests.c index 825bdd83..d78814ef 100644 --- a/runtime/tests/tests.c +++ b/runtime/tests/tests.c @@ -13,6 +13,7 @@ void test_tmc() vx_tmc(4); unsigned tid = vx_threadID(); // Get TID + tmc_array[tid] = tid; vx_tmc(1); @@ -85,6 +86,7 @@ void simple_kernel() wsapwn_arr[wid] = wid; + wid = vx_warpID(); if (wid != 0) { vx_tmc(0); From 4e6de0dc3822a3264b023e7b9c2b8dc009c3adf8 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 22 Mar 2020 15:59:45 -0700 Subject: [PATCH 48/66] Fixed most of the cache issues, mat_add left --- rtl/VX_cache/VX_cache_miss_resrv.v | 11 +- rtl/VX_cache/VX_tag_data_access.v | 6 +- rtl/simulate/test_bench.cpp | 6 +- runtime/mains/simple/Makefile | 2 +- runtime/mains/simple/vx_simple_main.c | 42 +- runtime/mains/simple/vx_simple_main.dump | 46574 +++++++++++---------- runtime/mains/simple/vx_simple_main.elf | Bin 256904 -> 256952 bytes runtime/mains/simple/vx_simple_main.hex | 11166 ++--- runtime/startup/vx_start.s | 37 +- 9 files changed, 29220 insertions(+), 28624 deletions(-) diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v index 3da09745..4bd1225d 100644 --- a/rtl/VX_cache/VX_cache_miss_resrv.v +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -71,7 +71,7 @@ module VX_cache_miss_resrv output wire miss_resrv_valid_st0, output wire[31:0] miss_resrv_addr_st0, output wire[`WORD_SIZE_RNG] miss_resrv_data_st0, - output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, + output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0, output wire[4:0] miss_resrv_rd_st0, output wire[1:0] miss_resrv_wb_st0, output wire[`NW_M1:0] miss_resrv_warp_num_st0, @@ -90,8 +90,11 @@ module VX_cache_miss_resrv reg[`vx_clog2(MRVQ_SIZE)-1:0] head_ptr; reg[`vx_clog2(MRVQ_SIZE)-1:0] tail_ptr; + reg[31:0] size; - assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr; + + // assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr; + assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE); wire enqueue_possible = !miss_resrv_full; @@ -108,7 +111,7 @@ module VX_cache_miss_resrv wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr]; - wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; + wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr; assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible; assign miss_resrv_pc_st0 = pc_table[dequeue_index]; @@ -126,6 +129,7 @@ module VX_cache_miss_resrv pc_table <= 0; end else begin if (miss_add && enqueue_possible && (MRVQ_SIZE != 2)) begin + size <= size + 1; valid_table[enqueue_index] <= 1; ready_table[enqueue_index] <= 0; pc_table[enqueue_index] <= miss_add_pc; @@ -139,6 +143,7 @@ module VX_cache_miss_resrv end if (miss_resrv_pop && dequeue_possible) begin + size <= size - 1; valid_table[dequeue_index] <= 0; ready_table[dequeue_index] <= 0; addr_table[dequeue_index] <= 0; diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 2c75745b..2d3672b8 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -94,7 +94,7 @@ module VX_tag_data_access wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data; - wire real_writefill = writefill_st1e && miss_st1e; + wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e))); wire fill_sent; @@ -238,14 +238,14 @@ module VX_tag_data_access wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e; - wire force_write = writefill_st1e && valid_req_st1e && miss_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e)); + wire force_write = real_writefill && valid_req_st1e && miss_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e)); wire[`DBANK_LINE_SIZE_RNG][3:0] we; wire[`DBANK_LINE_SIZE_RNG][31:0] data_write; genvar g; generate for (g = 0; g < `DBANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables - wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !writefill_st1e; + wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !real_writefill; assign we[g] = (force_write) ? 4'b1111 : (normal_write && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 : diff --git a/rtl/simulate/test_bench.cpp b/rtl/simulate/test_bench.cpp index 0d03f4bf..66c0b617 100644 --- a/rtl/simulate/test_bench.cpp +++ b/rtl/simulate/test_bench.cpp @@ -12,7 +12,7 @@ int main(int argc, char **argv) Verilated::traceEverOn(true); -#define ALL_TESTS +// #define ALL_TESTS #ifdef ALL_TESTS bool passed = true; @@ -88,9 +88,9 @@ int main(int argc, char **argv) #else - // char testing[] = "../../runtime/mains/simple/vx_simple_main.hex"; + char testing[] = "../../runtime/mains/simple/vx_simple_main.hex"; // char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex"; - char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; + // char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; Vortex v; // const char *testing; diff --git a/runtime/mains/simple/Makefile b/runtime/mains/simple/Makefile index d1823e85..4f878ec0 100644 --- a/runtime/mains/simple/Makefile +++ b/runtime/mains/simple/Makefile @@ -1,5 +1,5 @@ -COMP = /opt/riscv-new/drops/bin/riscv32-unknown-elf-gcc +COMP = /opt/riscv-new/drops/bin/riscv32-unknown-elf-g++ CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,../vortex_link.ld -ffreestanding -nostdlib DMP = /opt/riscv-new/drops/bin/riscv32-unknown-elf-objdump diff --git a/runtime/mains/simple/vx_simple_main.c b/runtime/mains/simple/vx_simple_main.c index 05bfea84..1d53458d 100644 --- a/runtime/mains/simple/vx_simple_main.c +++ b/runtime/mains/simple/vx_simple_main.c @@ -52,7 +52,7 @@ int main() // Main is called with all threads active of warp 0 vx_tmc(1); - vx_print_str("Let's start...\n"); + vx_print_str("Let's start... (This might take a while)\n"); unsigned what[36]; for (int i = 0; i < 36; i++) { @@ -98,31 +98,31 @@ int main() } - vx_print_str("vx_spawnWarps mat_add_kernel\n"); + // vx_print_str("vx_spawnWarps mat_add_kernel\n"); - mat_add_args_t arguments; - arguments.x = x; - arguments.y = y; - arguments.z = z; - arguments.numColums = 4; - arguments.numRows = 4; + // mat_add_args_t arguments; + // arguments.x = x; + // arguments.y = y; + // arguments.z = z; + // arguments.numColums = 4; + // arguments.numRows = 4; - int numWarps = 4; - int numThreads = 4; + // int numWarps = 4; + // int numThreads = 4; - vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments); + // vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments); - for (int i = 0; i < arguments.numRows; i++) - { - for (int j = 0; j < arguments.numColums; j++) - { - unsigned index = (i * arguments.numColums) + j; - vx_print_hex(z[index]); - vx_print_str(" "); - } - vx_print_str("\n"); - } + // for (int i = 0; i < arguments.numRows; i++) + // { + // for (int j = 0; j < arguments.numColums; j++) + // { + // unsigned index = (i * arguments.numColums) + j; + // vx_print_hex(z[index]); + // vx_print_str(" "); + // } + // vx_print_str("\n"); + // } return 0; } \ No newline at end of file diff --git a/runtime/mains/simple/vx_simple_main.dump b/runtime/mains/simple/vx_simple_main.dump index c1e051f4..13107406 100644 --- a/runtime/mains/simple/vx_simple_main.dump +++ b/runtime/mains/simple/vx_simple_main.dump @@ -6,23308 +6,23831 @@ Disassembly of section .init: 80000000 <_start>: 80000000: 00000597 auipc a1,0x0 -80000004: 03858593 addi a1,a1,56 # 80000038 +80000004: 04058593 addi a1,a1,64 # 80000040 80000008: 00400513 li a0,4 8000000c: 00b5106b 0xb5106b -80000010: 028000ef jal ra,80000038 -80000014: 0b8010ef jal ra,800010cc
-80000018: 3440106f j 8000135c +80000010: 030000ef jal ra,80000040 +80000014: 00400513 li a0,4 +80000018: 0005006b 0x5006b +8000001c: 0dc010ef jal ra,800010f8
+80000020: 2780106f j 80001298 Disassembly of section .text: -8000001c : -8000001c: 000007b7 lui a5,0x0 -80000020: 00078793 mv a5,a5 -80000024: 00078863 beqz a5,80000034 -80000028: 80005537 lui a0,0x80005 -8000002c: 84850513 addi a0,a0,-1976 # 80004848 <__BSS_END__+0xfffedc0c> -80000030: 1cc0406f j 800041fc -80000034: 00008067 ret +80000024 : +80000024: 000007b7 lui a5,0x0 +80000028: 00078793 mv a5,a5 +8000002c: 00078863 beqz a5,8000003c +80000030: 80004537 lui a0,0x80004 +80000034: 78450513 addi a0,a0,1924 # 80004784 <__BSS_END__+0xfffedb48> +80000038: 1000406f j 80004138 +8000003c: 00008067 ret -80000038 : -80000038: 00400513 li a0,4 -8000003c: 0005006b 0x5006b -80000040: 00016197 auipc gp,0x16 -80000044: 7c818193 addi gp,gp,1992 # 80016808 <__global_pointer$> -80000048: 022026f3 csrr a3,0x22 -8000004c: 01a69693 slli a3,a3,0x1a -80000050: 02002673 csrr a2,0x20 -80000054: 00a61593 slli a1,a2,0xa -80000058: 00261613 slli a2,a2,0x2 -8000005c: 6ffff137 lui sp,0x6ffff -80000060: 40b10133 sub sp,sp,a1 -80000064: 40d10133 sub sp,sp,a3 -80000068: 00c10133 add sp,sp,a2 -8000006c: 021026f3 csrr a3,0x21 -80000070: 00068663 beqz a3,8000007c -80000074: 00000513 li a0,0 -80000078: 0005006b 0x5006b +80000040 : +80000040: 00400513 li a0,4 +80000044: 0005006b 0x5006b +80000048: 00016197 auipc gp,0x16 +8000004c: 7c018193 addi gp,gp,1984 # 80016808 <__global_pointer$> +80000050: 022026f3 csrr a3,0x22 +80000054: 01a69693 slli a3,a3,0x1a +80000058: 02002673 csrr a2,0x20 +8000005c: 00a61593 slli a1,a2,0xa +80000060: 00261613 slli a2,a2,0x2 +80000064: 6ffff137 lui sp,0x6ffff +80000068: 40b10133 sub sp,sp,a1 +8000006c: 40d10133 sub sp,sp,a3 +80000070: 00c10133 add sp,sp,a2 +80000074: 021026f3 csrr a3,0x21 +80000078: 00068663 beqz a3,80000084 +8000007c: 00000513 li a0,0 +80000080: 0005006b 0x5006b -8000007c : -8000007c: 00008067 ret +80000084 : +80000084: 00008067 ret -80000080 : -80000080: fd010113 addi sp,sp,-48 # 6fffefd0 <_start-0x10001030> -80000084: 02812623 sw s0,44(sp) -80000088: 03010413 addi s0,sp,48 -8000008c: fca42e23 sw a0,-36(s0) -80000090: fcb42c23 sw a1,-40(s0) -80000094: fcc42a23 sw a2,-44(s0) -80000098: fdc42783 lw a5,-36(s0) -8000009c: 0007a783 lw a5,0(a5) # 0 <_start-0x80000000> -800000a0: fef42623 sw a5,-20(s0) -800000a4: fd440793 addi a5,s0,-44 -800000a8: fef42223 sw a5,-28(s0) -800000ac: fe442783 lw a5,-28(s0) -800000b0: 0007c703 lbu a4,0(a5) -800000b4: fec42783 lw a5,-20(s0) -800000b8: 00e78023 sb a4,0(a5) +80000088 : +80000088: fd010113 addi sp,sp,-48 # 6fffefd0 <_start-0x10001030> +8000008c: 02812623 sw s0,44(sp) +80000090: 03010413 addi s0,sp,48 +80000094: fca42e23 sw a0,-36(s0) +80000098: fcb42c23 sw a1,-40(s0) +8000009c: fcc42a23 sw a2,-44(s0) +800000a0: fdc42783 lw a5,-36(s0) +800000a4: 0007a783 lw a5,0(a5) # 0 <_start-0x80000000> +800000a8: fef42623 sw a5,-20(s0) +800000ac: fd440793 addi a5,s0,-44 +800000b0: fef42223 sw a5,-28(s0) +800000b4: fe442783 lw a5,-28(s0) +800000b8: 0007c703 lbu a4,0(a5) 800000bc: fec42783 lw a5,-20(s0) -800000c0: 00178793 addi a5,a5,1 -800000c4: fe442703 lw a4,-28(s0) -800000c8: 00174703 lbu a4,1(a4) -800000cc: 00e78023 sb a4,0(a5) -800000d0: fec42783 lw a5,-20(s0) -800000d4: 00278793 addi a5,a5,2 -800000d8: fe442703 lw a4,-28(s0) -800000dc: 00274703 lbu a4,2(a4) -800000e0: 00e78023 sb a4,0(a5) -800000e4: fec42783 lw a5,-20(s0) -800000e8: 00378793 addi a5,a5,3 -800000ec: fe442703 lw a4,-28(s0) -800000f0: 00374703 lbu a4,3(a4) -800000f4: 00e78023 sb a4,0(a5) -800000f8: fec42783 lw a5,-20(s0) -800000fc: 00478793 addi a5,a5,4 -80000100: fef42623 sw a5,-20(s0) -80000104: fe042423 sw zero,-24(s0) -80000108: 0340006f j 8000013c -8000010c: fe842783 lw a5,-24(s0) -80000110: fd842703 lw a4,-40(s0) -80000114: 00f707b3 add a5,a4,a5 -80000118: 0007c703 lbu a4,0(a5) -8000011c: fec42783 lw a5,-20(s0) -80000120: 00e78023 sb a4,0(a5) -80000124: fec42783 lw a5,-20(s0) -80000128: 00178793 addi a5,a5,1 -8000012c: fef42623 sw a5,-20(s0) -80000130: fe842783 lw a5,-24(s0) -80000134: 00178793 addi a5,a5,1 -80000138: fef42423 sw a5,-24(s0) -8000013c: fd442783 lw a5,-44(s0) -80000140: fe842703 lw a4,-24(s0) -80000144: fcf744e3 blt a4,a5,8000010c -80000148: fec42783 lw a5,-20(s0) -8000014c: fef42023 sw a5,-32(s0) -80000150: fe042783 lw a5,-32(s0) -80000154: 0037f793 andi a5,a5,3 -80000158: fe042703 lw a4,-32(s0) -8000015c: 00f707b3 add a5,a4,a5 -80000160: fef42023 sw a5,-32(s0) -80000164: fe042783 lw a5,-32(s0) -80000168: fef42623 sw a5,-20(s0) -8000016c: fdc42783 lw a5,-36(s0) -80000170: fec42703 lw a4,-20(s0) -80000174: 00e7a023 sw a4,0(a5) -80000178: 00000013 nop -8000017c: 02c12403 lw s0,44(sp) -80000180: 03010113 addi sp,sp,48 -80000184: 00008067 ret +800000c0: 00e78023 sb a4,0(a5) +800000c4: fec42783 lw a5,-20(s0) +800000c8: 00178793 addi a5,a5,1 +800000cc: fe442703 lw a4,-28(s0) +800000d0: 00174703 lbu a4,1(a4) +800000d4: 00e78023 sb a4,0(a5) +800000d8: fec42783 lw a5,-20(s0) +800000dc: 00278793 addi a5,a5,2 +800000e0: fe442703 lw a4,-28(s0) +800000e4: 00274703 lbu a4,2(a4) +800000e8: 00e78023 sb a4,0(a5) +800000ec: fec42783 lw a5,-20(s0) +800000f0: 00378793 addi a5,a5,3 +800000f4: fe442703 lw a4,-28(s0) +800000f8: 00374703 lbu a4,3(a4) +800000fc: 00e78023 sb a4,0(a5) +80000100: fec42783 lw a5,-20(s0) +80000104: 00478793 addi a5,a5,4 +80000108: fef42623 sw a5,-20(s0) +8000010c: fe042423 sw zero,-24(s0) +80000110: fd442783 lw a5,-44(s0) +80000114: fe842703 lw a4,-24(s0) +80000118: 02f75c63 bge a4,a5,80000150 +8000011c: fe842783 lw a5,-24(s0) +80000120: fd842703 lw a4,-40(s0) +80000124: 00f707b3 add a5,a4,a5 +80000128: 0007c703 lbu a4,0(a5) +8000012c: fec42783 lw a5,-20(s0) +80000130: 00e78023 sb a4,0(a5) +80000134: fec42783 lw a5,-20(s0) +80000138: 00178793 addi a5,a5,1 +8000013c: fef42623 sw a5,-20(s0) +80000140: fe842783 lw a5,-24(s0) +80000144: 00178793 addi a5,a5,1 +80000148: fef42423 sw a5,-24(s0) +8000014c: fc5ff06f j 80000110 +80000150: fec42783 lw a5,-20(s0) +80000154: fef42023 sw a5,-32(s0) +80000158: fe042783 lw a5,-32(s0) +8000015c: 0037f793 andi a5,a5,3 +80000160: fe042703 lw a4,-32(s0) +80000164: 00f707b3 add a5,a4,a5 +80000168: fef42023 sw a5,-32(s0) +8000016c: fe042783 lw a5,-32(s0) +80000170: fef42623 sw a5,-20(s0) +80000174: fdc42783 lw a5,-36(s0) +80000178: fec42703 lw a4,-20(s0) +8000017c: 00e7a023 sw a4,0(a5) +80000180: 00000013 nop +80000184: 02c12403 lw s0,44(sp) +80000188: 03010113 addi sp,sp,48 +8000018c: 00008067 ret -80000188 : -80000188: fc010113 addi sp,sp,-64 -8000018c: 02812e23 sw s0,60(sp) -80000190: 04010413 addi s0,sp,64 -80000194: fca42623 sw a0,-52(s0) -80000198: fcb42423 sw a1,-56(s0) -8000019c: fcc42783 lw a5,-52(s0) -800001a0: 0007a783 lw a5,0(a5) -800001a4: fef42623 sw a5,-20(s0) -800001a8: fdc40793 addi a5,s0,-36 -800001ac: fef42223 sw a5,-28(s0) -800001b0: fec42783 lw a5,-20(s0) -800001b4: 0007c703 lbu a4,0(a5) -800001b8: fe442783 lw a5,-28(s0) -800001bc: 00e78023 sb a4,0(a5) +80000190 : +80000190: fc010113 addi sp,sp,-64 +80000194: 02812e23 sw s0,60(sp) +80000198: 04010413 addi s0,sp,64 +8000019c: fca42623 sw a0,-52(s0) +800001a0: fcb42423 sw a1,-56(s0) +800001a4: fcc42783 lw a5,-52(s0) +800001a8: 0007a783 lw a5,0(a5) +800001ac: fef42623 sw a5,-20(s0) +800001b0: fdc40793 addi a5,s0,-36 +800001b4: fef42223 sw a5,-28(s0) +800001b8: fec42783 lw a5,-20(s0) +800001bc: 0007c703 lbu a4,0(a5) 800001c0: fe442783 lw a5,-28(s0) -800001c4: 00178793 addi a5,a5,1 -800001c8: fec42703 lw a4,-20(s0) -800001cc: 00174703 lbu a4,1(a4) -800001d0: 00e78023 sb a4,0(a5) -800001d4: fe442783 lw a5,-28(s0) -800001d8: 00278793 addi a5,a5,2 -800001dc: fec42703 lw a4,-20(s0) -800001e0: 00274703 lbu a4,2(a4) -800001e4: 00e78023 sb a4,0(a5) -800001e8: fe442783 lw a5,-28(s0) -800001ec: 00378793 addi a5,a5,3 -800001f0: fec42703 lw a4,-20(s0) -800001f4: 00374703 lbu a4,3(a4) -800001f8: 00e78023 sb a4,0(a5) -800001fc: fec42783 lw a5,-20(s0) -80000200: 00478793 addi a5,a5,4 -80000204: fef42623 sw a5,-20(s0) -80000208: fe042423 sw zero,-24(s0) -8000020c: 0340006f j 80000240 -80000210: fe842783 lw a5,-24(s0) -80000214: fc842703 lw a4,-56(s0) -80000218: 00f707b3 add a5,a4,a5 -8000021c: fec42703 lw a4,-20(s0) -80000220: 00074703 lbu a4,0(a4) -80000224: 00e78023 sb a4,0(a5) -80000228: fec42783 lw a5,-20(s0) -8000022c: 00178793 addi a5,a5,1 -80000230: fef42623 sw a5,-20(s0) -80000234: fe842783 lw a5,-24(s0) -80000238: 00178793 addi a5,a5,1 -8000023c: fef42423 sw a5,-24(s0) -80000240: fdc42783 lw a5,-36(s0) -80000244: fe842703 lw a4,-24(s0) -80000248: fcf744e3 blt a4,a5,80000210 -8000024c: fec42783 lw a5,-20(s0) -80000250: fef42023 sw a5,-32(s0) -80000254: fe042783 lw a5,-32(s0) -80000258: 0037f793 andi a5,a5,3 -8000025c: fe042703 lw a4,-32(s0) -80000260: 00f707b3 add a5,a4,a5 -80000264: fef42023 sw a5,-32(s0) -80000268: fe042783 lw a5,-32(s0) -8000026c: fef42623 sw a5,-20(s0) -80000270: fcc42783 lw a5,-52(s0) -80000274: fec42703 lw a4,-20(s0) -80000278: 00e7a023 sw a4,0(a5) -8000027c: 00000013 nop -80000280: 03c12403 lw s0,60(sp) -80000284: 04010113 addi sp,sp,64 -80000288: 00008067 ret +800001c4: 00e78023 sb a4,0(a5) +800001c8: fe442783 lw a5,-28(s0) +800001cc: 00178793 addi a5,a5,1 +800001d0: fec42703 lw a4,-20(s0) +800001d4: 00174703 lbu a4,1(a4) +800001d8: 00e78023 sb a4,0(a5) +800001dc: fe442783 lw a5,-28(s0) +800001e0: 00278793 addi a5,a5,2 +800001e4: fec42703 lw a4,-20(s0) +800001e8: 00274703 lbu a4,2(a4) +800001ec: 00e78023 sb a4,0(a5) +800001f0: fe442783 lw a5,-28(s0) +800001f4: 00378793 addi a5,a5,3 +800001f8: fec42703 lw a4,-20(s0) +800001fc: 00374703 lbu a4,3(a4) +80000200: 00e78023 sb a4,0(a5) +80000204: fec42783 lw a5,-20(s0) +80000208: 00478793 addi a5,a5,4 +8000020c: fef42623 sw a5,-20(s0) +80000210: fe042423 sw zero,-24(s0) +80000214: fdc42783 lw a5,-36(s0) +80000218: fe842703 lw a4,-24(s0) +8000021c: 02f75c63 bge a4,a5,80000254 +80000220: fe842783 lw a5,-24(s0) +80000224: fc842703 lw a4,-56(s0) +80000228: 00f707b3 add a5,a4,a5 +8000022c: fec42703 lw a4,-20(s0) +80000230: 00074703 lbu a4,0(a4) +80000234: 00e78023 sb a4,0(a5) +80000238: fec42783 lw a5,-20(s0) +8000023c: 00178793 addi a5,a5,1 +80000240: fef42623 sw a5,-20(s0) +80000244: fe842783 lw a5,-24(s0) +80000248: 00178793 addi a5,a5,1 +8000024c: fef42423 sw a5,-24(s0) +80000250: fc5ff06f j 80000214 +80000254: fec42783 lw a5,-20(s0) +80000258: fef42023 sw a5,-32(s0) +8000025c: fe042783 lw a5,-32(s0) +80000260: 0037f793 andi a5,a5,3 +80000264: fe042703 lw a4,-32(s0) +80000268: 00f707b3 add a5,a4,a5 +8000026c: fef42023 sw a5,-32(s0) +80000270: fe042783 lw a5,-32(s0) +80000274: fef42623 sw a5,-20(s0) +80000278: fcc42783 lw a5,-52(s0) +8000027c: fec42703 lw a4,-20(s0) +80000280: 00e7a023 sw a4,0(a5) +80000284: 00000013 nop +80000288: 03c12403 lw s0,60(sp) +8000028c: 04010113 addi sp,sp,64 +80000290: 00008067 ret -8000028c <_close>: -8000028c: ff010113 addi sp,sp,-16 -80000290: 00812623 sw s0,12(sp) -80000294: 01010413 addi s0,sp,16 -80000298: 00000013 nop -8000029c: 00c12403 lw s0,12(sp) -800002a0: 01010113 addi sp,sp,16 -800002a4: 00008067 ret +80000294 <_close>: +80000294: ff010113 addi sp,sp,-16 +80000298: 00812623 sw s0,12(sp) +8000029c: 01010413 addi s0,sp,16 +800002a0: 00000013 nop +800002a4: 00c12403 lw s0,12(sp) +800002a8: 01010113 addi sp,sp,16 +800002ac: 00008067 ret -800002a8 <_fstat>: -800002a8: fe010113 addi sp,sp,-32 -800002ac: 00812e23 sw s0,28(sp) -800002b0: 02010413 addi s0,sp,32 -800002b4: fea42623 sw a0,-20(s0) -800002b8: feb42423 sw a1,-24(s0) -800002bc: fe842783 lw a5,-24(s0) -800002c0: 00002737 lui a4,0x2 -800002c4: 00e7a223 sw a4,4(a5) -800002c8: 00000793 li a5,0 -800002cc: 00078513 mv a0,a5 -800002d0: 01c12403 lw s0,28(sp) -800002d4: 02010113 addi sp,sp,32 -800002d8: 00008067 ret +800002b0 <_fstat>: +800002b0: fe010113 addi sp,sp,-32 +800002b4: 00812e23 sw s0,28(sp) +800002b8: 02010413 addi s0,sp,32 +800002bc: fea42623 sw a0,-20(s0) +800002c0: feb42423 sw a1,-24(s0) +800002c4: fe842783 lw a5,-24(s0) +800002c8: 00002737 lui a4,0x2 +800002cc: 00e7a223 sw a4,4(a5) +800002d0: 00000793 li a5,0 +800002d4: 00078513 mv a0,a5 +800002d8: 01c12403 lw s0,28(sp) +800002dc: 02010113 addi sp,sp,32 +800002e0: 00008067 ret -800002dc <_isatty>: -800002dc: fe010113 addi sp,sp,-32 -800002e0: 00812e23 sw s0,28(sp) -800002e4: 02010413 addi s0,sp,32 -800002e8: fea42623 sw a0,-20(s0) -800002ec: 00100793 li a5,1 -800002f0: 00078513 mv a0,a5 -800002f4: 01c12403 lw s0,28(sp) -800002f8: 02010113 addi sp,sp,32 -800002fc: 00008067 ret +800002e4 <_isatty>: +800002e4: fe010113 addi sp,sp,-32 +800002e8: 00812e23 sw s0,28(sp) +800002ec: 02010413 addi s0,sp,32 +800002f0: fea42623 sw a0,-20(s0) +800002f4: 00100793 li a5,1 +800002f8: 00078513 mv a0,a5 +800002fc: 01c12403 lw s0,28(sp) +80000300: 02010113 addi sp,sp,32 +80000304: 00008067 ret -80000300 <_lseek>: -80000300: fd010113 addi sp,sp,-48 -80000304: 02112623 sw ra,44(sp) -80000308: 02812423 sw s0,40(sp) -8000030c: 03010413 addi s0,sp,48 -80000310: fca42e23 sw a0,-36(s0) -80000314: fcb42c23 sw a1,-40(s0) -80000318: fcc42a23 sw a2,-44(s0) -8000031c: 710007b7 lui a5,0x71000 -80000320: fef42623 sw a5,-20(s0) -80000324: 720007b7 lui a5,0x72000 -80000328: fef42423 sw a5,-24(s0) -8000032c: 00300793 li a5,3 -80000330: fef42223 sw a5,-28(s0) -80000334: fe440713 addi a4,s0,-28 -80000338: fec40793 addi a5,s0,-20 -8000033c: 00400613 li a2,4 -80000340: 00070593 mv a1,a4 -80000344: 00078513 mv a0,a5 -80000348: d39ff0ef jal ra,80000080 -8000034c: fdc40713 addi a4,s0,-36 -80000350: fec40793 addi a5,s0,-20 -80000354: 00400613 li a2,4 -80000358: 00070593 mv a1,a4 -8000035c: 00078513 mv a0,a5 -80000360: d21ff0ef jal ra,80000080 -80000364: fd840713 addi a4,s0,-40 -80000368: fec40793 addi a5,s0,-20 -8000036c: 00400613 li a2,4 -80000370: 00070593 mv a1,a4 -80000374: 00078513 mv a0,a5 -80000378: d09ff0ef jal ra,80000080 -8000037c: fd440713 addi a4,s0,-44 -80000380: fec40793 addi a5,s0,-20 -80000384: 00400613 li a2,4 -80000388: 00070593 mv a1,a4 -8000038c: 00078513 mv a0,a5 -80000390: cf1ff0ef jal ra,80000080 -80000394: 3541a783 lw a5,852(gp) # 80016b5c -80000398: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -8000039c: fe040713 addi a4,s0,-32 -800003a0: fe840793 addi a5,s0,-24 -800003a4: 00070593 mv a1,a4 -800003a8: 00078513 mv a0,a5 -800003ac: dddff0ef jal ra,80000188 -800003b0: fe042783 lw a5,-32(s0) -800003b4: 00078513 mv a0,a5 -800003b8: 02c12083 lw ra,44(sp) -800003bc: 02812403 lw s0,40(sp) -800003c0: 03010113 addi sp,sp,48 -800003c4: 00008067 ret +80000308 <_lseek>: +80000308: fd010113 addi sp,sp,-48 +8000030c: 02112623 sw ra,44(sp) +80000310: 02812423 sw s0,40(sp) +80000314: 03010413 addi s0,sp,48 +80000318: fca42e23 sw a0,-36(s0) +8000031c: fcb42c23 sw a1,-40(s0) +80000320: fcc42a23 sw a2,-44(s0) +80000324: 710007b7 lui a5,0x71000 +80000328: fef42623 sw a5,-20(s0) +8000032c: 720007b7 lui a5,0x72000 +80000330: fef42423 sw a5,-24(s0) +80000334: 00300793 li a5,3 +80000338: fef42223 sw a5,-28(s0) +8000033c: fe440713 addi a4,s0,-28 +80000340: fec40793 addi a5,s0,-20 +80000344: 00400613 li a2,4 +80000348: 00070593 mv a1,a4 +8000034c: 00078513 mv a0,a5 +80000350: d39ff0ef jal ra,80000088 +80000354: fdc40713 addi a4,s0,-36 +80000358: fec40793 addi a5,s0,-20 +8000035c: 00400613 li a2,4 +80000360: 00070593 mv a1,a4 +80000364: 00078513 mv a0,a5 +80000368: d21ff0ef jal ra,80000088 +8000036c: fd840713 addi a4,s0,-40 +80000370: fec40793 addi a5,s0,-20 +80000374: 00400613 li a2,4 +80000378: 00070593 mv a1,a4 +8000037c: 00078513 mv a0,a5 +80000380: d09ff0ef jal ra,80000088 +80000384: fd440713 addi a4,s0,-44 +80000388: fec40793 addi a5,s0,-20 +8000038c: 00400613 li a2,4 +80000390: 00070593 mv a1,a4 +80000394: 00078513 mv a0,a5 +80000398: cf1ff0ef jal ra,80000088 +8000039c: 3541a783 lw a5,852(gp) # 80016b5c +800003a0: 000780e7 jalr a5 # 72000000 <_start-0xe000000> +800003a4: fe040713 addi a4,s0,-32 +800003a8: fe840793 addi a5,s0,-24 +800003ac: 00070593 mv a1,a4 +800003b0: 00078513 mv a0,a5 +800003b4: dddff0ef jal ra,80000190 +800003b8: fe042783 lw a5,-32(s0) +800003bc: 00078513 mv a0,a5 +800003c0: 02c12083 lw ra,44(sp) +800003c4: 02812403 lw s0,40(sp) +800003c8: 03010113 addi sp,sp,48 +800003cc: 00008067 ret -800003c8 <_read>: -800003c8: fd010113 addi sp,sp,-48 -800003cc: 02112623 sw ra,44(sp) -800003d0: 02812423 sw s0,40(sp) -800003d4: 03010413 addi s0,sp,48 -800003d8: fca42e23 sw a0,-36(s0) -800003dc: fcb42c23 sw a1,-40(s0) -800003e0: fcc42a23 sw a2,-44(s0) -800003e4: 710007b7 lui a5,0x71000 -800003e8: fef42423 sw a5,-24(s0) -800003ec: 720007b7 lui a5,0x72000 -800003f0: fef42623 sw a5,-20(s0) -800003f4: 00400793 li a5,4 -800003f8: fef42223 sw a5,-28(s0) -800003fc: fe440713 addi a4,s0,-28 -80000400: fe840793 addi a5,s0,-24 -80000404: 00400613 li a2,4 -80000408: 00070593 mv a1,a4 -8000040c: 00078513 mv a0,a5 -80000410: c71ff0ef jal ra,80000080 -80000414: fdc40713 addi a4,s0,-36 -80000418: fe840793 addi a5,s0,-24 -8000041c: 00400613 li a2,4 -80000420: 00070593 mv a1,a4 -80000424: 00078513 mv a0,a5 -80000428: c59ff0ef jal ra,80000080 -8000042c: fd840713 addi a4,s0,-40 -80000430: fe840793 addi a5,s0,-24 -80000434: 00400613 li a2,4 -80000438: 00070593 mv a1,a4 -8000043c: 00078513 mv a0,a5 -80000440: c41ff0ef jal ra,80000080 -80000444: fd440713 addi a4,s0,-44 -80000448: fe840793 addi a5,s0,-24 -8000044c: 00400613 li a2,4 -80000450: 00070593 mv a1,a4 -80000454: 00078513 mv a0,a5 -80000458: c29ff0ef jal ra,80000080 -8000045c: 3541a783 lw a5,852(gp) # 80016b5c -80000460: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -80000464: fd442783 lw a5,-44(s0) -80000468: 00078513 mv a0,a5 -8000046c: 02c12083 lw ra,44(sp) -80000470: 02812403 lw s0,40(sp) -80000474: 03010113 addi sp,sp,48 -80000478: 00008067 ret +800003d0 <_read>: +800003d0: fd010113 addi sp,sp,-48 +800003d4: 02112623 sw ra,44(sp) +800003d8: 02812423 sw s0,40(sp) +800003dc: 03010413 addi s0,sp,48 +800003e0: fca42e23 sw a0,-36(s0) +800003e4: fcb42c23 sw a1,-40(s0) +800003e8: fcc42a23 sw a2,-44(s0) +800003ec: 710007b7 lui a5,0x71000 +800003f0: fef42423 sw a5,-24(s0) +800003f4: 720007b7 lui a5,0x72000 +800003f8: fef42623 sw a5,-20(s0) +800003fc: 00400793 li a5,4 +80000400: fef42223 sw a5,-28(s0) +80000404: fe440713 addi a4,s0,-28 +80000408: fe840793 addi a5,s0,-24 +8000040c: 00400613 li a2,4 +80000410: 00070593 mv a1,a4 +80000414: 00078513 mv a0,a5 +80000418: c71ff0ef jal ra,80000088 +8000041c: fdc40713 addi a4,s0,-36 +80000420: fe840793 addi a5,s0,-24 +80000424: 00400613 li a2,4 +80000428: 00070593 mv a1,a4 +8000042c: 00078513 mv a0,a5 +80000430: c59ff0ef jal ra,80000088 +80000434: fd840713 addi a4,s0,-40 +80000438: fe840793 addi a5,s0,-24 +8000043c: 00400613 li a2,4 +80000440: 00070593 mv a1,a4 +80000444: 00078513 mv a0,a5 +80000448: c41ff0ef jal ra,80000088 +8000044c: fd440713 addi a4,s0,-44 +80000450: fe840793 addi a5,s0,-24 +80000454: 00400613 li a2,4 +80000458: 00070593 mv a1,a4 +8000045c: 00078513 mv a0,a5 +80000460: c29ff0ef jal ra,80000088 +80000464: 3541a783 lw a5,852(gp) # 80016b5c +80000468: 000780e7 jalr a5 # 72000000 <_start-0xe000000> +8000046c: fd442783 lw a5,-44(s0) +80000470: 00078513 mv a0,a5 +80000474: 02c12083 lw ra,44(sp) +80000478: 02812403 lw s0,40(sp) +8000047c: 03010113 addi sp,sp,48 +80000480: 00008067 ret -8000047c <_write>: -8000047c: fd010113 addi sp,sp,-48 -80000480: 02112623 sw ra,44(sp) -80000484: 02812423 sw s0,40(sp) -80000488: 03010413 addi s0,sp,48 -8000048c: fca42e23 sw a0,-36(s0) -80000490: fcb42c23 sw a1,-40(s0) -80000494: fcc42a23 sw a2,-44(s0) -80000498: 710007b7 lui a5,0x71000 -8000049c: fef42623 sw a5,-20(s0) -800004a0: 00500793 li a5,5 -800004a4: fef42423 sw a5,-24(s0) -800004a8: fe840713 addi a4,s0,-24 -800004ac: fec40793 addi a5,s0,-20 -800004b0: 00400613 li a2,4 -800004b4: 00070593 mv a1,a4 -800004b8: 00078513 mv a0,a5 -800004bc: bc5ff0ef jal ra,80000080 -800004c0: fdc40713 addi a4,s0,-36 -800004c4: fec40793 addi a5,s0,-20 -800004c8: 00400613 li a2,4 -800004cc: 00070593 mv a1,a4 -800004d0: 00078513 mv a0,a5 -800004d4: badff0ef jal ra,80000080 -800004d8: fec40793 addi a5,s0,-20 -800004dc: fd442603 lw a2,-44(s0) -800004e0: fd842583 lw a1,-40(s0) -800004e4: 00078513 mv a0,a5 -800004e8: b99ff0ef jal ra,80000080 -800004ec: 3541a783 lw a5,852(gp) # 80016b5c -800004f0: 000780e7 jalr a5 # 71000000 <_start-0xf000000> -800004f4: fd442783 lw a5,-44(s0) -800004f8: 00078513 mv a0,a5 -800004fc: 02c12083 lw ra,44(sp) -80000500: 02812403 lw s0,40(sp) -80000504: 03010113 addi sp,sp,48 -80000508: 00008067 ret +80000484 <_write>: +80000484: fd010113 addi sp,sp,-48 +80000488: 02112623 sw ra,44(sp) +8000048c: 02812423 sw s0,40(sp) +80000490: 03010413 addi s0,sp,48 +80000494: fca42e23 sw a0,-36(s0) +80000498: fcb42c23 sw a1,-40(s0) +8000049c: fcc42a23 sw a2,-44(s0) +800004a0: 710007b7 lui a5,0x71000 +800004a4: fef42623 sw a5,-20(s0) +800004a8: 00500793 li a5,5 +800004ac: fef42423 sw a5,-24(s0) +800004b0: fe840713 addi a4,s0,-24 +800004b4: fec40793 addi a5,s0,-20 +800004b8: 00400613 li a2,4 +800004bc: 00070593 mv a1,a4 +800004c0: 00078513 mv a0,a5 +800004c4: bc5ff0ef jal ra,80000088 +800004c8: fdc40713 addi a4,s0,-36 +800004cc: fec40793 addi a5,s0,-20 +800004d0: 00400613 li a2,4 +800004d4: 00070593 mv a1,a4 +800004d8: 00078513 mv a0,a5 +800004dc: badff0ef jal ra,80000088 +800004e0: fec40793 addi a5,s0,-20 +800004e4: fd442603 lw a2,-44(s0) +800004e8: fd842583 lw a1,-40(s0) +800004ec: 00078513 mv a0,a5 +800004f0: b99ff0ef jal ra,80000088 +800004f4: 3541a783 lw a5,852(gp) # 80016b5c +800004f8: 000780e7 jalr a5 # 71000000 <_start-0xf000000> +800004fc: fd442783 lw a5,-44(s0) +80000500: 00078513 mv a0,a5 +80000504: 02c12083 lw ra,44(sp) +80000508: 02812403 lw s0,40(sp) +8000050c: 03010113 addi sp,sp,48 +80000510: 00008067 ret -8000050c <_sbrk>: -8000050c: fd010113 addi sp,sp,-48 -80000510: 02812623 sw s0,44(sp) -80000514: 03010413 addi s0,sp,48 -80000518: fca42e23 sw a0,-36(s0) -8000051c: fdc42783 lw a5,-36(s0) -80000520: 0007d863 bgez a5,80000530 <_sbrk+0x24> +80000514 <_sbrk>: +80000514: fd010113 addi sp,sp,-48 +80000518: 02812623 sw s0,44(sp) +8000051c: 03010413 addi s0,sp,48 +80000520: fca42e23 sw a0,-36(s0) 80000524: fdc42783 lw a5,-36(s0) -80000528: 40f007b3 neg a5,a5 -8000052c: fcf42e23 sw a5,-36(s0) -80000530: 3581a783 lw a5,856(gp) # 80016b60 -80000534: fef42623 sw a5,-20(s0) -80000538: 3581a703 lw a4,856(gp) # 80016b60 -8000053c: fdc42783 lw a5,-36(s0) -80000540: 00f70733 add a4,a4,a5 -80000544: 34e1ac23 sw a4,856(gp) # 80016b60 -80000548: fec42783 lw a5,-20(s0) -8000054c: 00078513 mv a0,a5 -80000550: 02c12403 lw s0,44(sp) -80000554: 03010113 addi sp,sp,48 -80000558: 00008067 ret +80000528: 0007d863 bgez a5,80000538 <_sbrk+0x24> +8000052c: fdc42783 lw a5,-36(s0) +80000530: 40f007b3 neg a5,a5 +80000534: fcf42e23 sw a5,-36(s0) +80000538: 3581a783 lw a5,856(gp) # 80016b60 <_ZL10heap_start> +8000053c: fef42623 sw a5,-20(s0) +80000540: 3581a703 lw a4,856(gp) # 80016b60 <_ZL10heap_start> +80000544: fdc42783 lw a5,-36(s0) +80000548: 00f70733 add a4,a4,a5 +8000054c: 34e1ac23 sw a4,856(gp) # 80016b60 <_ZL10heap_start> +80000550: fec42783 lw a5,-20(s0) +80000554: 00078513 mv a0,a5 +80000558: 02c12403 lw s0,44(sp) +8000055c: 03010113 addi sp,sp,48 +80000560: 00008067 ret -8000055c <_exit>: -8000055c: fe010113 addi sp,sp,-32 -80000560: 00112e23 sw ra,28(sp) -80000564: 00812c23 sw s0,24(sp) -80000568: 02010413 addi s0,sp,32 -8000056c: fea42623 sw a0,-20(s0) -80000570: 00000513 li a0,0 -80000574: 1c8000ef jal ra,8000073c -80000578: 00000013 nop -8000057c: 01c12083 lw ra,28(sp) -80000580: 01812403 lw s0,24(sp) -80000584: 02010113 addi sp,sp,32 -80000588: 00008067 ret +80000564 <_exit>: +80000564: fe010113 addi sp,sp,-32 +80000568: 00112e23 sw ra,28(sp) +8000056c: 00812c23 sw s0,24(sp) +80000570: 02010413 addi s0,sp,32 +80000574: fea42623 sw a0,-20(s0) +80000578: 00000513 li a0,0 +8000057c: 1c8000ef jal ra,80000744 +80000580: 00000013 nop +80000584: 01c12083 lw ra,28(sp) +80000588: 01812403 lw s0,24(sp) +8000058c: 02010113 addi sp,sp,32 +80000590: 00008067 ret -8000058c <_open>: -8000058c: fd010113 addi sp,sp,-48 -80000590: 02112623 sw ra,44(sp) -80000594: 02812423 sw s0,40(sp) -80000598: 03010413 addi s0,sp,48 -8000059c: fca42e23 sw a0,-36(s0) -800005a0: fcb42c23 sw a1,-40(s0) -800005a4: fcc42a23 sw a2,-44(s0) -800005a8: 710007b7 lui a5,0x71000 -800005ac: fef42623 sw a5,-20(s0) -800005b0: 720007b7 lui a5,0x72000 -800005b4: fef42423 sw a5,-24(s0) -800005b8: 00700793 li a5,7 -800005bc: fef42223 sw a5,-28(s0) -800005c0: fe440713 addi a4,s0,-28 -800005c4: fec40793 addi a5,s0,-20 -800005c8: 00400613 li a2,4 -800005cc: 00070593 mv a1,a4 -800005d0: 00078513 mv a0,a5 -800005d4: aadff0ef jal ra,80000080 -800005d8: fdc40713 addi a4,s0,-36 -800005dc: fec40793 addi a5,s0,-20 -800005e0: 00400613 li a2,4 -800005e4: 00070593 mv a1,a4 -800005e8: 00078513 mv a0,a5 -800005ec: a95ff0ef jal ra,80000080 -800005f0: fd840713 addi a4,s0,-40 -800005f4: fec40793 addi a5,s0,-20 -800005f8: 00400613 li a2,4 -800005fc: 00070593 mv a1,a4 -80000600: 00078513 mv a0,a5 -80000604: a7dff0ef jal ra,80000080 -80000608: fd440713 addi a4,s0,-44 -8000060c: fec40793 addi a5,s0,-20 -80000610: 00400613 li a2,4 -80000614: 00070593 mv a1,a4 -80000618: 00078513 mv a0,a5 -8000061c: a65ff0ef jal ra,80000080 -80000620: 3541a783 lw a5,852(gp) # 80016b5c -80000624: 000780e7 jalr a5 # 72000000 <_start-0xe000000> -80000628: fe040713 addi a4,s0,-32 -8000062c: fe840793 addi a5,s0,-24 -80000630: 00070593 mv a1,a4 -80000634: 00078513 mv a0,a5 -80000638: b51ff0ef jal ra,80000188 -8000063c: fe042783 lw a5,-32(s0) -80000640: 00078513 mv a0,a5 -80000644: 02c12083 lw ra,44(sp) -80000648: 02812403 lw s0,40(sp) -8000064c: 03010113 addi sp,sp,48 -80000650: 00008067 ret +80000594 <_open>: +80000594: fd010113 addi sp,sp,-48 +80000598: 02112623 sw ra,44(sp) +8000059c: 02812423 sw s0,40(sp) +800005a0: 03010413 addi s0,sp,48 +800005a4: fca42e23 sw a0,-36(s0) +800005a8: fcb42c23 sw a1,-40(s0) +800005ac: fcc42a23 sw a2,-44(s0) +800005b0: 710007b7 lui a5,0x71000 +800005b4: fef42623 sw a5,-20(s0) +800005b8: 720007b7 lui a5,0x72000 +800005bc: fef42423 sw a5,-24(s0) +800005c0: 00700793 li a5,7 +800005c4: fef42223 sw a5,-28(s0) +800005c8: fe440713 addi a4,s0,-28 +800005cc: fec40793 addi a5,s0,-20 +800005d0: 00400613 li a2,4 +800005d4: 00070593 mv a1,a4 +800005d8: 00078513 mv a0,a5 +800005dc: aadff0ef jal ra,80000088 +800005e0: fdc40713 addi a4,s0,-36 +800005e4: fec40793 addi a5,s0,-20 +800005e8: 00400613 li a2,4 +800005ec: 00070593 mv a1,a4 +800005f0: 00078513 mv a0,a5 +800005f4: a95ff0ef jal ra,80000088 +800005f8: fd840713 addi a4,s0,-40 +800005fc: fec40793 addi a5,s0,-20 +80000600: 00400613 li a2,4 +80000604: 00070593 mv a1,a4 +80000608: 00078513 mv a0,a5 +8000060c: a7dff0ef jal ra,80000088 +80000610: fd440713 addi a4,s0,-44 +80000614: fec40793 addi a5,s0,-20 +80000618: 00400613 li a2,4 +8000061c: 00070593 mv a1,a4 +80000620: 00078513 mv a0,a5 +80000624: a65ff0ef jal ra,80000088 +80000628: 3541a783 lw a5,852(gp) # 80016b5c +8000062c: 000780e7 jalr a5 # 72000000 <_start-0xe000000> +80000630: fe040713 addi a4,s0,-32 +80000634: fe840793 addi a5,s0,-24 +80000638: 00070593 mv a1,a4 +8000063c: 00078513 mv a0,a5 +80000640: b51ff0ef jal ra,80000190 +80000644: fe042783 lw a5,-32(s0) +80000648: 00078513 mv a0,a5 +8000064c: 02c12083 lw ra,44(sp) +80000650: 02812403 lw s0,40(sp) +80000654: 03010113 addi sp,sp,48 +80000658: 00008067 ret -80000654 <_kill>: -80000654: ff010113 addi sp,sp,-16 -80000658: 00112623 sw ra,12(sp) -8000065c: 00812423 sw s0,8(sp) -80000660: 01010413 addi s0,sp,16 -80000664: 00000513 li a0,0 -80000668: 0d4000ef jal ra,8000073c -8000066c: 00000013 nop -80000670: 00c12083 lw ra,12(sp) -80000674: 00812403 lw s0,8(sp) -80000678: 01010113 addi sp,sp,16 -8000067c: 00008067 ret +8000065c <_kill>: +8000065c: ff010113 addi sp,sp,-16 +80000660: 00112623 sw ra,12(sp) +80000664: 00812423 sw s0,8(sp) +80000668: 01010413 addi s0,sp,16 +8000066c: 00000513 li a0,0 +80000670: 0d4000ef jal ra,80000744 +80000674: 00000013 nop +80000678: 00c12083 lw ra,12(sp) +8000067c: 00812403 lw s0,8(sp) +80000680: 01010113 addi sp,sp,16 +80000684: 00008067 ret -80000680 <_getpid>: -80000680: ff010113 addi sp,sp,-16 -80000684: 00112623 sw ra,12(sp) -80000688: 00812423 sw s0,8(sp) -8000068c: 01010413 addi s0,sp,16 -80000690: 0dc000ef jal ra,8000076c -80000694: 00050793 mv a5,a0 -80000698: 00078513 mv a0,a5 -8000069c: 00c12083 lw ra,12(sp) -800006a0: 00812403 lw s0,8(sp) -800006a4: 01010113 addi sp,sp,16 -800006a8: 00008067 ret +80000688 <_getpid>: +80000688: ff010113 addi sp,sp,-16 +8000068c: 00112623 sw ra,12(sp) +80000690: 00812423 sw s0,8(sp) +80000694: 01010413 addi s0,sp,16 +80000698: 0dc000ef jal ra,80000774 +8000069c: 00050793 mv a5,a0 +800006a0: 00078513 mv a0,a5 +800006a4: 00c12083 lw ra,12(sp) +800006a8: 00812403 lw s0,8(sp) +800006ac: 01010113 addi sp,sp,16 +800006b0: 00008067 ret -800006ac <_unlink>: -800006ac: ff010113 addi sp,sp,-16 -800006b0: 00112623 sw ra,12(sp) -800006b4: 00812423 sw s0,8(sp) -800006b8: 01010413 addi s0,sp,16 -800006bc: 800157b7 lui a5,0x80015 -800006c0: a5878513 addi a0,a5,-1448 # 80014a58 <__BSS_END__+0xffffde1c> -800006c4: 100000ef jal ra,800007c4 -800006c8: 00000013 nop -800006cc: 00c12083 lw ra,12(sp) -800006d0: 00812403 lw s0,8(sp) -800006d4: 01010113 addi sp,sp,16 -800006d8: 00008067 ret +800006b4 <_unlink>: +800006b4: ff010113 addi sp,sp,-16 +800006b8: 00112623 sw ra,12(sp) +800006bc: 00812423 sw s0,8(sp) +800006c0: 01010413 addi s0,sp,16 +800006c4: 800157b7 lui a5,0x80015 +800006c8: 99078513 addi a0,a5,-1648 # 80014990 <__BSS_END__+0xffffdd54> +800006cc: 100000ef jal ra,800007cc +800006d0: 00000013 nop +800006d4: 00c12083 lw ra,12(sp) +800006d8: 00812403 lw s0,8(sp) +800006dc: 01010113 addi sp,sp,16 +800006e0: 00008067 ret -800006dc <_gettimeofday>: -800006dc: ff010113 addi sp,sp,-16 -800006e0: 00812623 sw s0,12(sp) -800006e4: 01010413 addi s0,sp,16 -800006e8: 37c1a783 lw a5,892(gp) # 80016b84 -800006ec: 00178693 addi a3,a5,1 -800006f0: 36d1ae23 sw a3,892(gp) # 80016b84 -800006f4: 00078513 mv a0,a5 -800006f8: 00c12403 lw s0,12(sp) -800006fc: 01010113 addi sp,sp,16 -80000700: 00008067 ret +800006e4 <_gettimeofday>: +800006e4: ff010113 addi sp,sp,-16 +800006e8: 00812623 sw s0,12(sp) +800006ec: 01010413 addi s0,sp,16 +800006f0: 3a41a783 lw a5,932(gp) # 80016bac <_ZL9curr_time> +800006f4: 00178693 addi a3,a5,1 +800006f8: 3ad1a223 sw a3,932(gp) # 80016bac <_ZL9curr_time> +800006fc: 00078513 mv a0,a5 +80000700: 00c12403 lw s0,12(sp) +80000704: 01010113 addi sp,sp,16 +80000708: 00008067 ret -80000704 <_link>: -80000704: ff010113 addi sp,sp,-16 -80000708: 00112623 sw ra,12(sp) -8000070c: 00812423 sw s0,8(sp) -80000710: 01010413 addi s0,sp,16 -80000714: 800157b7 lui a5,0x80015 -80000718: a7c78513 addi a0,a5,-1412 # 80014a7c <__BSS_END__+0xffffde40> -8000071c: 0a8000ef jal ra,800007c4 -80000720: 00000013 nop -80000724: 00c12083 lw ra,12(sp) -80000728: 00812403 lw s0,8(sp) -8000072c: 01010113 addi sp,sp,16 -80000730: 00008067 ret - -80000734 : -80000734: 00b5106b 0xb5106b +8000070c <_link>: +8000070c: ff010113 addi sp,sp,-16 +80000710: 00112623 sw ra,12(sp) +80000714: 00812423 sw s0,8(sp) +80000718: 01010413 addi s0,sp,16 +8000071c: 800157b7 lui a5,0x80015 +80000720: 9b478513 addi a0,a5,-1612 # 800149b4 <__BSS_END__+0xffffdd78> +80000724: 0a8000ef jal ra,800007cc +80000728: 00000013 nop +8000072c: 00c12083 lw ra,12(sp) +80000730: 00812403 lw s0,8(sp) +80000734: 01010113 addi sp,sp,16 80000738: 00008067 ret -8000073c : -8000073c: 0005006b 0x5006b +8000073c : +8000073c: 00b5106b 0xb5106b 80000740: 00008067 ret -80000744 : -80000744: 00b5406b 0xb5406b +80000744 : +80000744: 0005006b 0x5006b 80000748: 00008067 ret -8000074c : -8000074c: 0005206b 0x5206b +8000074c : +8000074c: 00b5406b 0xb5406b 80000750: 00008067 ret -80000754 : -80000754: 0000306b 0x306b +80000754 : +80000754: 0005206b 0x5206b 80000758: 00008067 ret -8000075c : -8000075c: 02102573 csrr a0,0x21 +8000075c : +8000075c: 0000306b 0x306b 80000760: 00008067 ret -80000764 : -80000764: 02202573 csrr a0,0x22 +80000764 : +80000764: 02102573 csrr a0,0x21 80000768: 00008067 ret -8000076c : -8000076c: 02002573 csrr a0,0x20 +8000076c : +8000076c: 02202573 csrr a0,0x22 80000770: 00008067 ret -80000774 : -80000774: 02602573 csrr a0,0x26 +80000774 : +80000774: 02002573 csrr a0,0x20 80000778: 00008067 ret -8000077c : -8000077c: 02502573 csrr a0,0x25 +8000077c : +8000077c: 02602573 csrr a0,0x26 80000780: 00008067 ret -80000784 : -80000784: 00400513 li a0,4 -80000788: 0005006b 0x5006b -8000078c: 021026f3 csrr a3,0x21 -80000790: 00f69693 slli a3,a3,0xf -80000794: 02002673 csrr a2,0x20 -80000798: 00a61593 slli a1,a2,0xa -8000079c: 00261613 slli a2,a2,0x2 -800007a0: 6ffff137 lui sp,0x6ffff -800007a4: 40b10133 sub sp,sp,a1 -800007a8: 40d10133 sub sp,sp,a3 -800007ac: 00c10133 add sp,sp,a2 -800007b0: 021026f3 csrr a3,0x21 -800007b4: 00068663 beqz a3,800007c0 -800007b8: 00000513 li a0,0 -800007bc: 0005006b 0x5006b +80000784 : +80000784: 02502573 csrr a0,0x25 +80000788: 00008067 ret -800007c0 : -800007c0: 00008067 ret +8000078c : +8000078c: 00400513 li a0,4 +80000790: 0005006b 0x5006b +80000794: 021026f3 csrr a3,0x21 +80000798: 00f69693 slli a3,a3,0xf +8000079c: 02002673 csrr a2,0x20 +800007a0: 00a61593 slli a1,a2,0xa +800007a4: 00261613 slli a2,a2,0x2 +800007a8: 6ffff137 lui sp,0x6ffff +800007ac: 40b10133 sub sp,sp,a1 +800007b0: 40d10133 sub sp,sp,a3 +800007b4: 00c10133 add sp,sp,a2 +800007b8: 021026f3 csrr a3,0x21 +800007bc: 00068663 beqz a3,800007c8 +800007c0: 00000513 li a0,0 +800007c4: 0005006b 0x5006b -800007c4 : -800007c4: ff410113 addi sp,sp,-12 # 6fffeff4 <_start-0x1000100c> -800007c8: 00112023 sw ra,0(sp) -800007cc: 00b12223 sw a1,4(sp) +800007c8 : +800007c8: 00008067 ret -800007d0 : -800007d0: 00054583 lbu a1,0(a0) -800007d4: 00058863 beqz a1,800007e4 -800007d8: 01c000ef jal ra,800007f4 -800007dc: 00150513 addi a0,a0,1 -800007e0: ff1ff06f j 800007d0 +800007cc : +800007cc: ff410113 addi sp,sp,-12 # 6fffeff4 <_start-0x1000100c> +800007d0: 00112023 sw ra,0(sp) +800007d4: 00b12223 sw a1,4(sp) -800007e4 : -800007e4: 00012083 lw ra,0(sp) -800007e8: 00412583 lw a1,4(sp) -800007ec: 00c10113 addi sp,sp,12 -800007f0: 00008067 ret +800007d8 : +800007d8: 00054583 lbu a1,0(a0) +800007dc: 00058863 beqz a1,800007ec +800007e0: 01c000ef jal ra,800007fc +800007e4: 00150513 addi a0,a0,1 +800007e8: ff1ff06f j 800007d8 -800007f4 : -800007f4: 000102b7 lui t0,0x10 -800007f8: 00b2a023 sw a1,0(t0) # 10000 <_start-0x7fff0000> -800007fc: 00008067 ret +800007ec : +800007ec: 00012083 lw ra,0(sp) +800007f0: 00412583 lw a1,4(sp) +800007f4: 00c10113 addi sp,sp,12 +800007f8: 00008067 ret -80000800 : -80000800: fd010113 addi sp,sp,-48 -80000804: 02112623 sw ra,44(sp) -80000808: 02812423 sw s0,40(sp) -8000080c: 03010413 addi s0,sp,48 -80000810: fca42e23 sw a0,-36(s0) -80000814: fdc42703 lw a4,-36(s0) -80000818: 00f00793 li a5,15 -8000081c: 02e7e463 bltu a5,a4,80000844 -80000820: 800167b7 lui a5,0x80016 -80000824: 04c78713 addi a4,a5,76 # 8001604c <__BSS_END__+0xfffff410> -80000828: fdc42783 lw a5,-36(s0) -8000082c: 00279793 slli a5,a5,0x2 -80000830: 00f707b3 add a5,a4,a5 -80000834: 0007a783 lw a5,0(a5) -80000838: 00078513 mv a0,a5 -8000083c: f89ff0ef jal ra,800007c4 -80000840: 0740006f j 800008b4 -80000844: 02000793 li a5,32 -80000848: fef42623 sw a5,-20(s0) -8000084c: fe0405a3 sb zero,-21(s0) -80000850: fec42783 lw a5,-20(s0) -80000854: ffc78793 addi a5,a5,-4 -80000858: fdc42703 lw a4,-36(s0) -8000085c: 00f757b3 srl a5,a4,a5 -80000860: 00f7f793 andi a5,a5,15 -80000864: fef42223 sw a5,-28(s0) -80000868: fe442783 lw a5,-28(s0) -8000086c: 00078663 beqz a5,80000878 -80000870: 00100793 li a5,1 -80000874: fef405a3 sb a5,-21(s0) -80000878: feb44783 lbu a5,-21(s0) -8000087c: 02078263 beqz a5,800008a0 -80000880: 800167b7 lui a5,0x80016 -80000884: 04c78713 addi a4,a5,76 # 8001604c <__BSS_END__+0xfffff410> -80000888: fe442783 lw a5,-28(s0) -8000088c: 00279793 slli a5,a5,0x2 -80000890: 00f707b3 add a5,a4,a5 -80000894: 0007a783 lw a5,0(a5) -80000898: 00078513 mv a0,a5 -8000089c: f29ff0ef jal ra,800007c4 -800008a0: fec42783 lw a5,-20(s0) -800008a4: ffc78793 addi a5,a5,-4 -800008a8: fef42623 sw a5,-20(s0) -800008ac: fec42783 lw a5,-20(s0) -800008b0: faf040e3 bgtz a5,80000850 -800008b4: 02c12083 lw ra,44(sp) -800008b8: 02812403 lw s0,40(sp) -800008bc: 03010113 addi sp,sp,48 -800008c0: 00008067 ret +800007fc : +800007fc: 000102b7 lui t0,0x10 +80000800: 00b2a023 sw a1,0(t0) # 10000 <_start-0x7fff0000> +80000804: 00008067 ret -800008c4 : -800008c4: fe010113 addi sp,sp,-32 -800008c8: 00112e23 sw ra,28(sp) -800008cc: 00812c23 sw s0,24(sp) -800008d0: 02010413 addi s0,sp,32 -800008d4: fea42623 sw a0,-20(s0) -800008d8: feb42423 sw a1,-24(s0) -800008dc: fec42503 lw a0,-20(s0) -800008e0: ee5ff0ef jal ra,800007c4 -800008e4: fe842503 lw a0,-24(s0) -800008e8: f19ff0ef jal ra,80000800 -800008ec: 800157b7 lui a5,0x80015 -800008f0: ae078513 addi a0,a5,-1312 # 80014ae0 <__BSS_END__+0xffffdea4> -800008f4: ed1ff0ef jal ra,800007c4 -800008f8: 00000013 nop -800008fc: 01c12083 lw ra,28(sp) -80000900: 01812403 lw s0,24(sp) -80000904: 02010113 addi sp,sp,32 -80000908: 00008067 ret +80000808 : +80000808: fd010113 addi sp,sp,-48 +8000080c: 02112623 sw ra,44(sp) +80000810: 02812423 sw s0,40(sp) +80000814: 03010413 addi s0,sp,48 +80000818: fca42e23 sw a0,-36(s0) +8000081c: fdc42703 lw a4,-36(s0) +80000820: 00f00793 li a5,15 +80000824: 02e7e463 bltu a5,a4,8000084c +80000828: 800167b7 lui a5,0x80016 +8000082c: 04c78713 addi a4,a5,76 # 8001604c <__BSS_END__+0xfffff410> +80000830: fdc42783 lw a5,-36(s0) +80000834: 00279793 slli a5,a5,0x2 +80000838: 00f707b3 add a5,a4,a5 +8000083c: 0007a783 lw a5,0(a5) +80000840: 00078513 mv a0,a5 +80000844: f89ff0ef jal ra,800007cc +80000848: 0780006f j 800008c0 +8000084c: 02000793 li a5,32 +80000850: fef42623 sw a5,-20(s0) +80000854: fe0405a3 sb zero,-21(s0) +80000858: fec42783 lw a5,-20(s0) +8000085c: ffc78793 addi a5,a5,-4 +80000860: fdc42703 lw a4,-36(s0) +80000864: 00f757b3 srl a5,a4,a5 +80000868: 00f7f793 andi a5,a5,15 +8000086c: fef42223 sw a5,-28(s0) +80000870: fe442783 lw a5,-28(s0) +80000874: 00078663 beqz a5,80000880 +80000878: 00100793 li a5,1 +8000087c: fef405a3 sb a5,-21(s0) +80000880: feb44783 lbu a5,-21(s0) +80000884: 02078263 beqz a5,800008a8 +80000888: 800167b7 lui a5,0x80016 +8000088c: 04c78713 addi a4,a5,76 # 8001604c <__BSS_END__+0xfffff410> +80000890: fe442783 lw a5,-28(s0) +80000894: 00279793 slli a5,a5,0x2 +80000898: 00f707b3 add a5,a4,a5 +8000089c: 0007a783 lw a5,0(a5) +800008a0: 00078513 mv a0,a5 +800008a4: f29ff0ef jal ra,800007cc +800008a8: fec42783 lw a5,-20(s0) +800008ac: ffc78793 addi a5,a5,-4 +800008b0: fef42623 sw a5,-20(s0) +800008b4: fec42783 lw a5,-20(s0) +800008b8: 00f05463 blez a5,800008c0 +800008bc: f9dff06f j 80000858 +800008c0: 02c12083 lw ra,44(sp) +800008c4: 02812403 lw s0,40(sp) +800008c8: 03010113 addi sp,sp,48 +800008cc: 00008067 ret -8000090c : -8000090c: fe010113 addi sp,sp,-32 -80000910: 00112e23 sw ra,28(sp) -80000914: 00812c23 sw s0,24(sp) -80000918: 02010413 addi s0,sp,32 -8000091c: 40c1a783 lw a5,1036(gp) # 80016c14 -80000920: 00078513 mv a0,a5 -80000924: e19ff0ef jal ra,8000073c -80000928: 3f41a703 lw a4,1012(gp) # 80016bfc -8000092c: 3ec1a783 lw a5,1004(gp) # 80016bf4 -80000930: 00078513 mv a0,a5 -80000934: 000700e7 jalr a4 # 2000 <_start-0x7fffe000> -80000938: e25ff0ef jal ra,8000075c -8000093c: fea42623 sw a0,-20(s0) -80000940: fec42783 lw a5,-20(s0) -80000944: 00078863 beqz a5,80000954 -80000948: 00000513 li a0,0 -8000094c: df1ff0ef jal ra,8000073c -80000950: 00c0006f j 8000095c -80000954: 00100513 li a0,1 -80000958: de5ff0ef jal ra,8000073c -8000095c: 00000013 nop -80000960: 01c12083 lw ra,28(sp) -80000964: 01812403 lw s0,24(sp) -80000968: 02010113 addi sp,sp,32 -8000096c: 00008067 ret +800008d0 : +800008d0: fe010113 addi sp,sp,-32 +800008d4: 00112e23 sw ra,28(sp) +800008d8: 00812c23 sw s0,24(sp) +800008dc: 02010413 addi s0,sp,32 +800008e0: fea42623 sw a0,-20(s0) +800008e4: feb42423 sw a1,-24(s0) +800008e8: fec42503 lw a0,-20(s0) +800008ec: ee1ff0ef jal ra,800007cc +800008f0: fe842503 lw a0,-24(s0) +800008f4: f15ff0ef jal ra,80000808 +800008f8: 800157b7 lui a5,0x80015 +800008fc: a1878513 addi a0,a5,-1512 # 80014a18 <__BSS_END__+0xffffdddc> +80000900: ecdff0ef jal ra,800007cc +80000904: 00000013 nop +80000908: 01c12083 lw ra,28(sp) +8000090c: 01812403 lw s0,24(sp) +80000910: 02010113 addi sp,sp,32 +80000914: 00008067 ret -80000970 : -80000970: fe010113 addi sp,sp,-32 -80000974: 00112e23 sw ra,28(sp) -80000978: 00812c23 sw s0,24(sp) -8000097c: 02010413 addi s0,sp,32 -80000980: fea42623 sw a0,-20(s0) -80000984: feb42423 sw a1,-24(s0) -80000988: fec42223 sw a2,-28(s0) -8000098c: fed42023 sw a3,-32(s0) -80000990: fe442703 lw a4,-28(s0) -80000994: 3ee1aa23 sw a4,1012(gp) # 80016bfc -80000998: fe042703 lw a4,-32(s0) -8000099c: 3ee1a623 sw a4,1004(gp) # 80016bf4 -800009a0: fe842703 lw a4,-24(s0) -800009a4: 40e1a623 sw a4,1036(gp) # 80016c14 -800009a8: 800017b7 lui a5,0x80001 -800009ac: 90c78793 addi a5,a5,-1780 # 8000090c <__BSS_END__+0xfffe9cd0> -800009b0: 00078593 mv a1,a5 -800009b4: fec42503 lw a0,-20(s0) -800009b8: d7dff0ef jal ra,80000734 -800009bc: f51ff0ef jal ra,8000090c -800009c0: 00000013 nop -800009c4: 01c12083 lw ra,28(sp) -800009c8: 01812403 lw s0,24(sp) -800009cc: 02010113 addi sp,sp,32 -800009d0: 00008067 ret +80000918 : +80000918: fe010113 addi sp,sp,-32 +8000091c: 00112e23 sw ra,28(sp) +80000920: 00812c23 sw s0,24(sp) +80000924: 02010413 addi s0,sp,32 +80000928: 3741a783 lw a5,884(gp) # 80016b7c +8000092c: 00078513 mv a0,a5 +80000930: e15ff0ef jal ra,80000744 +80000934: 36c1a703 lw a4,876(gp) # 80016b74 <_edata> +80000938: 3701a783 lw a5,880(gp) # 80016b78 +8000093c: 00078513 mv a0,a5 +80000940: 000700e7 jalr a4 # 2000 <_start-0x7fffe000> +80000944: e21ff0ef jal ra,80000764 +80000948: 00050793 mv a5,a0 +8000094c: fef42623 sw a5,-20(s0) +80000950: fec42783 lw a5,-20(s0) +80000954: 00078863 beqz a5,80000964 +80000958: 00000513 li a0,0 +8000095c: de9ff0ef jal ra,80000744 +80000960: 00c0006f j 8000096c +80000964: 00100513 li a0,1 +80000968: dddff0ef jal ra,80000744 +8000096c: 00000013 nop +80000970: 01c12083 lw ra,28(sp) +80000974: 01812403 lw s0,24(sp) +80000978: 02010113 addi sp,sp,32 +8000097c: 00008067 ret -800009d4 : -800009d4: fd010113 addi sp,sp,-48 -800009d8: 02112623 sw ra,44(sp) -800009dc: 02812423 sw s0,40(sp) -800009e0: 03010413 addi s0,sp,48 -800009e4: 3fc1a783 lw a5,1020(gp) # 80016c04 -800009e8: 00078513 mv a0,a5 -800009ec: d51ff0ef jal ra,8000073c -800009f0: d7dff0ef jal ra,8000076c -800009f4: 00050793 mv a5,a0 -800009f8: fef42023 sw a5,-32(s0) -800009fc: d61ff0ef jal ra,8000075c -80000a00: 00050793 mv a5,a0 -80000a04: fcf42e23 sw a5,-36(s0) -80000a08: fe042623 sw zero,-20(s0) -80000a0c: 0980006f j 80000aa4 -80000a10: fe042423 sw zero,-24(s0) -80000a14: 0780006f j 80000a8c -80000a18: fe042223 sw zero,-28(s0) -80000a1c: 0580006f j 80000a74 -80000a20: fe842783 lw a5,-24(s0) -80000a24: 00279793 slli a5,a5,0x2 -80000a28: fe042703 lw a4,-32(s0) -80000a2c: 00f707b3 add a5,a4,a5 -80000a30: fcf42c23 sw a5,-40(s0) -80000a34: fe442783 lw a5,-28(s0) -80000a38: 00279793 slli a5,a5,0x2 -80000a3c: fdc42703 lw a4,-36(s0) -80000a40: 00f707b3 add a5,a4,a5 -80000a44: fcf42a23 sw a5,-44(s0) -80000a48: 3e81a803 lw a6,1000(gp) # 80016bf0 -80000a4c: 4041a503 lw a0,1028(gp) # 80016c0c -80000a50: 4081a783 lw a5,1032(gp) # 80016c10 -80000a54: fd842603 lw a2,-40(s0) -80000a58: fd442683 lw a3,-44(s0) -80000a5c: fec42703 lw a4,-20(s0) -80000a60: 00078593 mv a1,a5 -80000a64: 000800e7 jalr a6 -80000a68: fe442783 lw a5,-28(s0) -80000a6c: 00178793 addi a5,a5,1 -80000a70: fef42223 sw a5,-28(s0) -80000a74: fe442703 lw a4,-28(s0) -80000a78: 3f01a783 lw a5,1008(gp) # 80016bf8 -80000a7c: faf762e3 bltu a4,a5,80000a20 -80000a80: fe842783 lw a5,-24(s0) -80000a84: 00178793 addi a5,a5,1 -80000a88: fef42423 sw a5,-24(s0) -80000a8c: fe842703 lw a4,-24(s0) -80000a90: 4001a783 lw a5,1024(gp) # 80016c08 -80000a94: f8f762e3 bltu a4,a5,80000a18 -80000a98: fec42783 lw a5,-20(s0) -80000a9c: 00178793 addi a5,a5,1 -80000aa0: fef42623 sw a5,-20(s0) -80000aa4: fec42703 lw a4,-20(s0) -80000aa8: 3f81a783 lw a5,1016(gp) # 80016c00 -80000aac: f6f762e3 bltu a4,a5,80000a10 -80000ab0: fdc42783 lw a5,-36(s0) -80000ab4: 00078663 beqz a5,80000ac0 -80000ab8: 00000513 li a0,0 -80000abc: c81ff0ef jal ra,8000073c -80000ac0: 00100513 li a0,1 -80000ac4: c79ff0ef jal ra,8000073c -80000ac8: 00000013 nop -80000acc: 02c12083 lw ra,44(sp) -80000ad0: 02812403 lw s0,40(sp) -80000ad4: 03010113 addi sp,sp,48 -80000ad8: 00008067 ret +80000980 : +80000980: fe010113 addi sp,sp,-32 +80000984: 00112e23 sw ra,28(sp) +80000988: 00812c23 sw s0,24(sp) +8000098c: 02010413 addi s0,sp,32 +80000990: fea42623 sw a0,-20(s0) +80000994: feb42423 sw a1,-24(s0) +80000998: fec42223 sw a2,-28(s0) +8000099c: fed42023 sw a3,-32(s0) +800009a0: fe442703 lw a4,-28(s0) +800009a4: 36e1a623 sw a4,876(gp) # 80016b74 <_edata> +800009a8: fe042703 lw a4,-32(s0) +800009ac: 36e1a823 sw a4,880(gp) # 80016b78 +800009b0: fe842703 lw a4,-24(s0) +800009b4: 36e1aa23 sw a4,884(gp) # 80016b7c +800009b8: 800017b7 lui a5,0x80001 +800009bc: 91878793 addi a5,a5,-1768 # 80000918 <__BSS_END__+0xfffe9cdc> +800009c0: 00078593 mv a1,a5 +800009c4: fec42503 lw a0,-20(s0) +800009c8: d75ff0ef jal ra,8000073c +800009cc: f4dff0ef jal ra,80000918 +800009d0: 00000013 nop +800009d4: 01c12083 lw ra,28(sp) +800009d8: 01812403 lw s0,24(sp) +800009dc: 02010113 addi sp,sp,32 +800009e0: 00008067 ret -80000adc : -80000adc: fc010113 addi sp,sp,-64 -80000ae0: 02112e23 sw ra,60(sp) -80000ae4: 02812c23 sw s0,56(sp) -80000ae8: 04010413 addi s0,sp,64 -80000aec: fca42623 sw a0,-52(s0) -80000af0: fcb42423 sw a1,-56(s0) -80000af4: fcc42223 sw a2,-60(s0) -80000af8: fcc42783 lw a5,-52(s0) -80000afc: 0007a703 lw a4,0(a5) -80000b00: 00400793 li a5,4 -80000b04: 02e7f063 bgeu a5,a4,80000b24 -80000b08: 00400713 li a4,4 -80000b0c: 3ee1ae23 sw a4,1020(gp) # 80016c04 -80000b10: fcc42783 lw a5,-52(s0) -80000b14: 0007a783 lw a5,0(a5) -80000b18: 0027d713 srli a4,a5,0x2 -80000b1c: 40e1a023 sw a4,1024(gp) # 80016c08 -80000b20: 0180006f j 80000b38 -80000b24: fcc42783 lw a5,-52(s0) -80000b28: 0007a703 lw a4,0(a5) -80000b2c: 3ee1ae23 sw a4,1020(gp) # 80016c04 -80000b30: 00100713 li a4,1 -80000b34: 40e1a023 sw a4,1024(gp) # 80016c08 -80000b38: fcc42783 lw a5,-52(s0) -80000b3c: 0087a703 lw a4,8(a5) -80000b40: 3ee1ac23 sw a4,1016(gp) # 80016c00 -80000b44: fc842703 lw a4,-56(s0) -80000b48: 3ee1a423 sw a4,1000(gp) # 80016bf0 -80000b4c: fcc42703 lw a4,-52(s0) -80000b50: 40e1a423 sw a4,1032(gp) # 80016c10 -80000b54: fc442703 lw a4,-60(s0) -80000b58: 40e1a223 sw a4,1028(gp) # 80016c0c -80000b5c: fcc42783 lw a5,-52(s0) -80000b60: 0047a703 lw a4,4(a5) -80000b64: 00100793 li a5,1 -80000b68: 06e7f063 bgeu a5,a4,80000bc8 +800009e4 : +800009e4: fd010113 addi sp,sp,-48 +800009e8: 02112623 sw ra,44(sp) +800009ec: 02812423 sw s0,40(sp) +800009f0: 03010413 addi s0,sp,48 +800009f4: 3781a783 lw a5,888(gp) # 80016b80 +800009f8: 00078513 mv a0,a5 +800009fc: d49ff0ef jal ra,80000744 +80000a00: d75ff0ef jal ra,80000774 +80000a04: 00050793 mv a5,a0 +80000a08: fef42023 sw a5,-32(s0) +80000a0c: d59ff0ef jal ra,80000764 +80000a10: 00050793 mv a5,a0 +80000a14: fcf42e23 sw a5,-36(s0) +80000a18: fe042623 sw zero,-20(s0) +80000a1c: fec42703 lw a4,-20(s0) +80000a20: 3881a783 lw a5,904(gp) # 80016b90 +80000a24: 08f77e63 bgeu a4,a5,80000ac0 +80000a28: fe042423 sw zero,-24(s0) +80000a2c: fe842703 lw a4,-24(s0) +80000a30: 3901a783 lw a5,912(gp) # 80016b98 +80000a34: 06f77e63 bgeu a4,a5,80000ab0 +80000a38: fe042223 sw zero,-28(s0) +80000a3c: fe442703 lw a4,-28(s0) +80000a40: 38c1a783 lw a5,908(gp) # 80016b94 +80000a44: 04f77e63 bgeu a4,a5,80000aa0 +80000a48: fe842783 lw a5,-24(s0) +80000a4c: 00279793 slli a5,a5,0x2 +80000a50: fe042703 lw a4,-32(s0) +80000a54: 00f707b3 add a5,a4,a5 +80000a58: fcf42c23 sw a5,-40(s0) +80000a5c: fe442783 lw a5,-28(s0) +80000a60: 00279793 slli a5,a5,0x2 +80000a64: fdc42703 lw a4,-36(s0) +80000a68: 00f707b3 add a5,a4,a5 +80000a6c: fcf42a23 sw a5,-44(s0) +80000a70: 3841a803 lw a6,900(gp) # 80016b8c +80000a74: 37c1a503 lw a0,892(gp) # 80016b84 +80000a78: 3801a783 lw a5,896(gp) # 80016b88 +80000a7c: fd842603 lw a2,-40(s0) +80000a80: fd442683 lw a3,-44(s0) +80000a84: fec42703 lw a4,-20(s0) +80000a88: 00078593 mv a1,a5 +80000a8c: 000800e7 jalr a6 +80000a90: fe442783 lw a5,-28(s0) +80000a94: 00178793 addi a5,a5,1 +80000a98: fef42223 sw a5,-28(s0) +80000a9c: fa1ff06f j 80000a3c +80000aa0: fe842783 lw a5,-24(s0) +80000aa4: 00178793 addi a5,a5,1 +80000aa8: fef42423 sw a5,-24(s0) +80000aac: f81ff06f j 80000a2c +80000ab0: fec42783 lw a5,-20(s0) +80000ab4: 00178793 addi a5,a5,1 +80000ab8: fef42623 sw a5,-20(s0) +80000abc: f61ff06f j 80000a1c +80000ac0: fdc42783 lw a5,-36(s0) +80000ac4: 00078663 beqz a5,80000ad0 +80000ac8: 00000513 li a0,0 +80000acc: c79ff0ef jal ra,80000744 +80000ad0: 00100513 li a0,1 +80000ad4: c71ff0ef jal ra,80000744 +80000ad8: 00000013 nop +80000adc: 02c12083 lw ra,44(sp) +80000ae0: 02812403 lw s0,40(sp) +80000ae4: 03010113 addi sp,sp,48 +80000ae8: 00008067 ret + +80000aec : +80000aec: fc010113 addi sp,sp,-64 +80000af0: 02112e23 sw ra,60(sp) +80000af4: 02812c23 sw s0,56(sp) +80000af8: 04010413 addi s0,sp,64 +80000afc: fca42623 sw a0,-52(s0) +80000b00: fcb42423 sw a1,-56(s0) +80000b04: fcc42223 sw a2,-60(s0) +80000b08: fcc42783 lw a5,-52(s0) +80000b0c: 0007a703 lw a4,0(a5) +80000b10: 00400793 li a5,4 +80000b14: 02e7f063 bgeu a5,a4,80000b34 +80000b18: 00400713 li a4,4 +80000b1c: 36e1ac23 sw a4,888(gp) # 80016b80 +80000b20: fcc42783 lw a5,-52(s0) +80000b24: 0007a783 lw a5,0(a5) +80000b28: 0027d713 srli a4,a5,0x2 +80000b2c: 38e1a823 sw a4,912(gp) # 80016b98 +80000b30: 0180006f j 80000b48 +80000b34: fcc42783 lw a5,-52(s0) +80000b38: 0007a703 lw a4,0(a5) +80000b3c: 36e1ac23 sw a4,888(gp) # 80016b80 +80000b40: 00100713 li a4,1 +80000b44: 38e1a823 sw a4,912(gp) # 80016b98 +80000b48: fcc42783 lw a5,-52(s0) +80000b4c: 0087a703 lw a4,8(a5) +80000b50: 38e1a423 sw a4,904(gp) # 80016b90 +80000b54: fc842703 lw a4,-56(s0) +80000b58: 38e1a223 sw a4,900(gp) # 80016b8c +80000b5c: fcc42703 lw a4,-52(s0) +80000b60: 38e1a023 sw a4,896(gp) # 80016b88 +80000b64: fc442703 lw a4,-60(s0) +80000b68: 36e1ae23 sw a4,892(gp) # 80016b84 80000b6c: fcc42783 lw a5,-52(s0) 80000b70: 0047a703 lw a4,4(a5) -80000b74: 00400793 li a5,4 -80000b78: 02e7f663 bgeu a5,a4,80000ba4 +80000b74: 00100793 li a5,1 +80000b78: 06e7f063 bgeu a5,a4,80000bd8 80000b7c: fcc42783 lw a5,-52(s0) -80000b80: 0047a783 lw a5,4(a5) -80000b84: 0027d713 srli a4,a5,0x2 -80000b88: 3ee1a823 sw a4,1008(gp) # 80016bf8 -80000b8c: 800017b7 lui a5,0x80001 -80000b90: 9d478793 addi a5,a5,-1580 # 800009d4 <__BSS_END__+0xfffe9d98> -80000b94: 00078593 mv a1,a5 -80000b98: 00400513 li a0,4 -80000b9c: b99ff0ef jal ra,80000734 -80000ba0: 0280006f j 80000bc8 -80000ba4: 00100713 li a4,1 -80000ba8: 3ee1a823 sw a4,1008(gp) # 80016bf8 -80000bac: fcc42783 lw a5,-52(s0) -80000bb0: 0047a703 lw a4,4(a5) -80000bb4: 800017b7 lui a5,0x80001 -80000bb8: 9d478793 addi a5,a5,-1580 # 800009d4 <__BSS_END__+0xfffe9d98> -80000bbc: 00078593 mv a1,a5 -80000bc0: 00070513 mv a0,a4 -80000bc4: b71ff0ef jal ra,80000734 -80000bc8: badff0ef jal ra,80000774 -80000bcc: fea42623 sw a0,-20(s0) -80000bd0: badff0ef jal ra,8000077c -80000bd4: fea42423 sw a0,-24(s0) -80000bd8: dfdff0ef jal ra,800009d4 -80000bdc: b99ff0ef jal ra,80000774 -80000be0: fea42223 sw a0,-28(s0) -80000be4: b99ff0ef jal ra,8000077c -80000be8: fea42023 sw a0,-32(s0) -80000bec: fe442703 lw a4,-28(s0) -80000bf0: fec42783 lw a5,-20(s0) -80000bf4: 40f707b3 sub a5,a4,a5 -80000bf8: fcf42e23 sw a5,-36(s0) -80000bfc: fdc42583 lw a1,-36(s0) -80000c00: 800157b7 lui a5,0x80015 -80000c04: ae478513 addi a0,a5,-1308 # 80014ae4 <__BSS_END__+0xffffdea8> -80000c08: 7c4000ef jal ra,800013cc -80000c0c: 00000513 li a0,0 -80000c10: b2dff0ef jal ra,8000073c -80000c14: 00000013 nop -80000c18: 03c12083 lw ra,60(sp) -80000c1c: 03812403 lw s0,56(sp) -80000c20: 04010113 addi sp,sp,64 -80000c24: 00008067 ret +80000b80: 0047a703 lw a4,4(a5) +80000b84: 00400793 li a5,4 +80000b88: 02e7f663 bgeu a5,a4,80000bb4 +80000b8c: fcc42783 lw a5,-52(s0) +80000b90: 0047a783 lw a5,4(a5) +80000b94: 0027d713 srli a4,a5,0x2 +80000b98: 38e1a623 sw a4,908(gp) # 80016b94 +80000b9c: 800017b7 lui a5,0x80001 +80000ba0: 9e478793 addi a5,a5,-1564 # 800009e4 <__BSS_END__+0xfffe9da8> +80000ba4: 00078593 mv a1,a5 +80000ba8: 00400513 li a0,4 +80000bac: b91ff0ef jal ra,8000073c +80000bb0: 0280006f j 80000bd8 +80000bb4: 00100713 li a4,1 +80000bb8: 38e1a623 sw a4,908(gp) # 80016b94 +80000bbc: fcc42783 lw a5,-52(s0) +80000bc0: 0047a703 lw a4,4(a5) +80000bc4: 800017b7 lui a5,0x80001 +80000bc8: 9e478793 addi a5,a5,-1564 # 800009e4 <__BSS_END__+0xfffe9da8> +80000bcc: 00078593 mv a1,a5 +80000bd0: 00070513 mv a0,a4 +80000bd4: b69ff0ef jal ra,8000073c +80000bd8: ba5ff0ef jal ra,8000077c +80000bdc: 00050793 mv a5,a0 +80000be0: fef42623 sw a5,-20(s0) +80000be4: ba1ff0ef jal ra,80000784 +80000be8: 00050793 mv a5,a0 +80000bec: fef42423 sw a5,-24(s0) +80000bf0: df5ff0ef jal ra,800009e4 +80000bf4: b89ff0ef jal ra,8000077c +80000bf8: 00050793 mv a5,a0 +80000bfc: fef42223 sw a5,-28(s0) +80000c00: b85ff0ef jal ra,80000784 +80000c04: 00050793 mv a5,a0 +80000c08: fef42023 sw a5,-32(s0) +80000c0c: fe442703 lw a4,-28(s0) +80000c10: fec42783 lw a5,-20(s0) +80000c14: 40f707b3 sub a5,a4,a5 +80000c18: fcf42e23 sw a5,-36(s0) +80000c1c: fdc42583 lw a1,-36(s0) +80000c20: 800157b7 lui a5,0x80015 +80000c24: a1c78513 addi a0,a5,-1508 # 80014a1c <__BSS_END__+0xffffdde0> +80000c28: 6e0000ef jal ra,80001308 +80000c2c: 00000513 li a0,0 +80000c30: b15ff0ef jal ra,80000744 +80000c34: 00000013 nop +80000c38: 03c12083 lw ra,60(sp) +80000c3c: 03812403 lw s0,56(sp) +80000c40: 04010113 addi sp,sp,64 +80000c44: 00008067 ret -80000c28 : -80000c28: fe010113 addi sp,sp,-32 -80000c2c: 00112e23 sw ra,28(sp) -80000c30: 00812c23 sw s0,24(sp) -80000c34: 02010413 addi s0,sp,32 -80000c38: 800157b7 lui a5,0x80015 -80000c3c: b2878513 addi a0,a5,-1240 # 80014b28 <__BSS_END__+0xffffdeec> -80000c40: b85ff0ef jal ra,800007c4 -80000c44: 00400513 li a0,4 -80000c48: af5ff0ef jal ra,8000073c -80000c4c: b21ff0ef jal ra,8000076c -80000c50: fea42623 sw a0,-20(s0) -80000c54: fec42703 lw a4,-20(s0) -80000c58: 8c418693 addi a3,gp,-1852 # 800160cc -80000c5c: fec42783 lw a5,-20(s0) -80000c60: 00279793 slli a5,a5,0x2 -80000c64: 00f687b3 add a5,a3,a5 -80000c68: 00e7a023 sw a4,0(a5) -80000c6c: 00100513 li a0,1 -80000c70: acdff0ef jal ra,8000073c -80000c74: 8c418793 addi a5,gp,-1852 # 800160cc -80000c78: 0007a783 lw a5,0(a5) -80000c7c: 00078513 mv a0,a5 -80000c80: b81ff0ef jal ra,80000800 -80000c84: 800157b7 lui a5,0x80015 -80000c88: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000c8c: b39ff0ef jal ra,800007c4 -80000c90: 8c418793 addi a5,gp,-1852 # 800160cc -80000c94: 0047a783 lw a5,4(a5) -80000c98: 00078513 mv a0,a5 -80000c9c: b65ff0ef jal ra,80000800 -80000ca0: 800157b7 lui a5,0x80015 -80000ca4: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000ca8: b1dff0ef jal ra,800007c4 -80000cac: 8c418793 addi a5,gp,-1852 # 800160cc -80000cb0: 0087a783 lw a5,8(a5) -80000cb4: 00078513 mv a0,a5 -80000cb8: b49ff0ef jal ra,80000800 -80000cbc: 800157b7 lui a5,0x80015 -80000cc0: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000cc4: b01ff0ef jal ra,800007c4 -80000cc8: 8c418793 addi a5,gp,-1852 # 800160cc -80000ccc: 00c7a783 lw a5,12(a5) -80000cd0: 00078513 mv a0,a5 -80000cd4: b2dff0ef jal ra,80000800 -80000cd8: 800157b7 lui a5,0x80015 -80000cdc: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000ce0: ae5ff0ef jal ra,800007c4 -80000ce4: 00000013 nop -80000ce8: 01c12083 lw ra,28(sp) -80000cec: 01812403 lw s0,24(sp) -80000cf0: 02010113 addi sp,sp,32 -80000cf4: 00008067 ret +80000c48 <_Z8test_tmcv>: +80000c48: fe010113 addi sp,sp,-32 +80000c4c: 00112e23 sw ra,28(sp) +80000c50: 00812c23 sw s0,24(sp) +80000c54: 02010413 addi s0,sp,32 +80000c58: 800157b7 lui a5,0x80015 +80000c5c: a6078513 addi a0,a5,-1440 # 80014a60 <__BSS_END__+0xffffde24> +80000c60: b6dff0ef jal ra,800007cc +80000c64: 00400513 li a0,4 +80000c68: addff0ef jal ra,80000744 +80000c6c: b09ff0ef jal ra,80000774 +80000c70: 00050793 mv a5,a0 +80000c74: fef42623 sw a5,-20(s0) +80000c78: fec42703 lw a4,-20(s0) +80000c7c: 8c418693 addi a3,gp,-1852 # 800160cc +80000c80: fec42783 lw a5,-20(s0) +80000c84: 00279793 slli a5,a5,0x2 +80000c88: 00f687b3 add a5,a3,a5 +80000c8c: 00e7a023 sw a4,0(a5) +80000c90: 00100513 li a0,1 +80000c94: ab1ff0ef jal ra,80000744 +80000c98: 8c418793 addi a5,gp,-1852 # 800160cc +80000c9c: 0007a783 lw a5,0(a5) +80000ca0: 00078513 mv a0,a5 +80000ca4: b65ff0ef jal ra,80000808 +80000ca8: 800157b7 lui a5,0x80015 +80000cac: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000cb0: b1dff0ef jal ra,800007cc +80000cb4: 8c418793 addi a5,gp,-1852 # 800160cc +80000cb8: 0047a783 lw a5,4(a5) +80000cbc: 00078513 mv a0,a5 +80000cc0: b49ff0ef jal ra,80000808 +80000cc4: 800157b7 lui a5,0x80015 +80000cc8: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000ccc: b01ff0ef jal ra,800007cc +80000cd0: 8c418793 addi a5,gp,-1852 # 800160cc +80000cd4: 0087a783 lw a5,8(a5) +80000cd8: 00078513 mv a0,a5 +80000cdc: b2dff0ef jal ra,80000808 +80000ce0: 800157b7 lui a5,0x80015 +80000ce4: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000ce8: ae5ff0ef jal ra,800007cc +80000cec: 8c418793 addi a5,gp,-1852 # 800160cc +80000cf0: 00c7a783 lw a5,12(a5) +80000cf4: 00078513 mv a0,a5 +80000cf8: b11ff0ef jal ra,80000808 +80000cfc: 800157b7 lui a5,0x80015 +80000d00: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000d04: ac9ff0ef jal ra,800007cc +80000d08: 00000013 nop +80000d0c: 01c12083 lw ra,28(sp) +80000d10: 01812403 lw s0,24(sp) +80000d14: 02010113 addi sp,sp,32 +80000d18: 00008067 ret -80000cf8 : -80000cf8: fe010113 addi sp,sp,-32 -80000cfc: 00112e23 sw ra,28(sp) -80000d00: 00812c23 sw s0,24(sp) -80000d04: 02010413 addi s0,sp,32 -80000d08: a65ff0ef jal ra,8000076c -80000d0c: fea42623 sw a0,-20(s0) -80000d10: fec42783 lw a5,-20(s0) -80000d14: 0027b793 sltiu a5,a5,2 -80000d18: fef405a3 sb a5,-21(s0) -80000d1c: feb44783 lbu a5,-21(s0) -80000d20: 00078513 mv a0,a5 -80000d24: a29ff0ef jal ra,8000074c -80000d28: feb44783 lbu a5,-21(s0) -80000d2c: 06078063 beqz a5,80000d8c -80000d30: fec42783 lw a5,-20(s0) -80000d34: 0017b793 seqz a5,a5 -80000d38: fef404a3 sb a5,-23(s0) -80000d3c: fe944783 lbu a5,-23(s0) -80000d40: 00078513 mv a0,a5 -80000d44: a09ff0ef jal ra,8000074c -80000d48: fe944783 lbu a5,-23(s0) -80000d4c: 02078063 beqz a5,80000d6c -80000d50: 42018713 addi a4,gp,1056 # 80016c28 -80000d54: fec42783 lw a5,-20(s0) -80000d58: 00279793 slli a5,a5,0x2 -80000d5c: 00f707b3 add a5,a4,a5 -80000d60: 00a00713 li a4,10 -80000d64: 00e7a023 sw a4,0(a5) -80000d68: 01c0006f j 80000d84 -80000d6c: 42018713 addi a4,gp,1056 # 80016c28 -80000d70: fec42783 lw a5,-20(s0) -80000d74: 00279793 slli a5,a5,0x2 -80000d78: 00f707b3 add a5,a4,a5 -80000d7c: 00b00713 li a4,11 -80000d80: 00e7a023 sw a4,0(a5) -80000d84: 9d1ff0ef jal ra,80000754 -80000d88: 05c0006f j 80000de4 -80000d8c: fec42783 lw a5,-20(s0) -80000d90: 0037b793 sltiu a5,a5,3 -80000d94: fef40523 sb a5,-22(s0) -80000d98: fea44783 lbu a5,-22(s0) -80000d9c: 00078513 mv a0,a5 -80000da0: 9adff0ef jal ra,8000074c -80000da4: fea44783 lbu a5,-22(s0) -80000da8: 02078063 beqz a5,80000dc8 -80000dac: 42018713 addi a4,gp,1056 # 80016c28 -80000db0: fec42783 lw a5,-20(s0) -80000db4: 00279793 slli a5,a5,0x2 -80000db8: 00f707b3 add a5,a4,a5 -80000dbc: 00c00713 li a4,12 -80000dc0: 00e7a023 sw a4,0(a5) -80000dc4: 01c0006f j 80000de0 -80000dc8: 42018713 addi a4,gp,1056 # 80016c28 -80000dcc: fec42783 lw a5,-20(s0) -80000dd0: 00279793 slli a5,a5,0x2 -80000dd4: 00f707b3 add a5,a4,a5 -80000dd8: 00d00713 li a4,13 -80000ddc: 00e7a023 sw a4,0(a5) -80000de0: 975ff0ef jal ra,80000754 -80000de4: 971ff0ef jal ra,80000754 -80000de8: 42018793 addi a5,gp,1056 # 80016c28 -80000dec: 0007a783 lw a5,0(a5) -80000df0: 00078513 mv a0,a5 -80000df4: a0dff0ef jal ra,80000800 -80000df8: 800157b7 lui a5,0x80015 -80000dfc: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000e00: 9c5ff0ef jal ra,800007c4 -80000e04: 42018793 addi a5,gp,1056 # 80016c28 -80000e08: 0047a783 lw a5,4(a5) -80000e0c: 00078513 mv a0,a5 -80000e10: 9f1ff0ef jal ra,80000800 -80000e14: 800157b7 lui a5,0x80015 -80000e18: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000e1c: 9a9ff0ef jal ra,800007c4 -80000e20: 42018793 addi a5,gp,1056 # 80016c28 -80000e24: 0087a783 lw a5,8(a5) -80000e28: 00078513 mv a0,a5 -80000e2c: 9d5ff0ef jal ra,80000800 -80000e30: 800157b7 lui a5,0x80015 -80000e34: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000e38: 98dff0ef jal ra,800007c4 -80000e3c: 42018793 addi a5,gp,1056 # 80016c28 -80000e40: 00c7a783 lw a5,12(a5) -80000e44: 00078513 mv a0,a5 -80000e48: 9b9ff0ef jal ra,80000800 -80000e4c: 800157b7 lui a5,0x80015 -80000e50: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000e54: 971ff0ef jal ra,800007c4 -80000e58: 00000013 nop -80000e5c: 01c12083 lw ra,28(sp) -80000e60: 01812403 lw s0,24(sp) -80000e64: 02010113 addi sp,sp,32 -80000e68: 00008067 ret +80000d1c <_Z15test_divergencev>: +80000d1c: fe010113 addi sp,sp,-32 +80000d20: 00112e23 sw ra,28(sp) +80000d24: 00812c23 sw s0,24(sp) +80000d28: 02010413 addi s0,sp,32 +80000d2c: a49ff0ef jal ra,80000774 +80000d30: 00050793 mv a5,a0 +80000d34: fef42623 sw a5,-20(s0) +80000d38: fec42783 lw a5,-20(s0) +80000d3c: 0027b793 sltiu a5,a5,2 +80000d40: fef405a3 sb a5,-21(s0) +80000d44: feb44783 lbu a5,-21(s0) +80000d48: 00078513 mv a0,a5 +80000d4c: a09ff0ef jal ra,80000754 +80000d50: feb44783 lbu a5,-21(s0) +80000d54: 06078063 beqz a5,80000db4 <_Z15test_divergencev+0x98> +80000d58: fec42783 lw a5,-20(s0) +80000d5c: 0017b793 seqz a5,a5 +80000d60: fef404a3 sb a5,-23(s0) +80000d64: fe944783 lbu a5,-23(s0) +80000d68: 00078513 mv a0,a5 +80000d6c: 9e9ff0ef jal ra,80000754 +80000d70: fe944783 lbu a5,-23(s0) +80000d74: 02078063 beqz a5,80000d94 <_Z15test_divergencev+0x78> +80000d78: 3a818713 addi a4,gp,936 # 80016bb0 +80000d7c: fec42783 lw a5,-20(s0) +80000d80: 00279793 slli a5,a5,0x2 +80000d84: 00f707b3 add a5,a4,a5 +80000d88: 00a00713 li a4,10 +80000d8c: 00e7a023 sw a4,0(a5) +80000d90: 01c0006f j 80000dac <_Z15test_divergencev+0x90> +80000d94: 3a818713 addi a4,gp,936 # 80016bb0 +80000d98: fec42783 lw a5,-20(s0) +80000d9c: 00279793 slli a5,a5,0x2 +80000da0: 00f707b3 add a5,a4,a5 +80000da4: 00b00713 li a4,11 +80000da8: 00e7a023 sw a4,0(a5) +80000dac: 9b1ff0ef jal ra,8000075c +80000db0: 05c0006f j 80000e0c <_Z15test_divergencev+0xf0> +80000db4: fec42783 lw a5,-20(s0) +80000db8: 0037b793 sltiu a5,a5,3 +80000dbc: fef40523 sb a5,-22(s0) +80000dc0: fea44783 lbu a5,-22(s0) +80000dc4: 00078513 mv a0,a5 +80000dc8: 98dff0ef jal ra,80000754 +80000dcc: fea44783 lbu a5,-22(s0) +80000dd0: 02078063 beqz a5,80000df0 <_Z15test_divergencev+0xd4> +80000dd4: 3a818713 addi a4,gp,936 # 80016bb0 +80000dd8: fec42783 lw a5,-20(s0) +80000ddc: 00279793 slli a5,a5,0x2 +80000de0: 00f707b3 add a5,a4,a5 +80000de4: 00c00713 li a4,12 +80000de8: 00e7a023 sw a4,0(a5) +80000dec: 01c0006f j 80000e08 <_Z15test_divergencev+0xec> +80000df0: 3a818713 addi a4,gp,936 # 80016bb0 +80000df4: fec42783 lw a5,-20(s0) +80000df8: 00279793 slli a5,a5,0x2 +80000dfc: 00f707b3 add a5,a4,a5 +80000e00: 00d00713 li a4,13 +80000e04: 00e7a023 sw a4,0(a5) +80000e08: 955ff0ef jal ra,8000075c +80000e0c: 951ff0ef jal ra,8000075c +80000e10: 3a818793 addi a5,gp,936 # 80016bb0 +80000e14: 0007a783 lw a5,0(a5) +80000e18: 00078513 mv a0,a5 +80000e1c: 9edff0ef jal ra,80000808 +80000e20: 800157b7 lui a5,0x80015 +80000e24: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000e28: 9a5ff0ef jal ra,800007cc +80000e2c: 3a818793 addi a5,gp,936 # 80016bb0 +80000e30: 0047a783 lw a5,4(a5) +80000e34: 00078513 mv a0,a5 +80000e38: 9d1ff0ef jal ra,80000808 +80000e3c: 800157b7 lui a5,0x80015 +80000e40: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000e44: 989ff0ef jal ra,800007cc +80000e48: 3a818793 addi a5,gp,936 # 80016bb0 +80000e4c: 0087a783 lw a5,8(a5) +80000e50: 00078513 mv a0,a5 +80000e54: 9b5ff0ef jal ra,80000808 +80000e58: 800157b7 lui a5,0x80015 +80000e5c: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000e60: 96dff0ef jal ra,800007cc +80000e64: 3a818793 addi a5,gp,936 # 80016bb0 +80000e68: 00c7a783 lw a5,12(a5) +80000e6c: 00078513 mv a0,a5 +80000e70: 999ff0ef jal ra,80000808 +80000e74: 800157b7 lui a5,0x80015 +80000e78: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000e7c: 951ff0ef jal ra,800007cc +80000e80: 00000013 nop +80000e84: 01c12083 lw ra,28(sp) +80000e88: 01812403 lw s0,24(sp) +80000e8c: 02010113 addi sp,sp,32 +80000e90: 00008067 ret -80000e6c : -80000e6c: fe010113 addi sp,sp,-32 -80000e70: 00112e23 sw ra,28(sp) -80000e74: 00812c23 sw s0,24(sp) -80000e78: 02010413 addi s0,sp,32 -80000e7c: 8e1ff0ef jal ra,8000075c -80000e80: fea42623 sw a0,-20(s0) -80000e84: 41018713 addi a4,gp,1040 # 80016c18 -80000e88: fec42783 lw a5,-20(s0) -80000e8c: 00279793 slli a5,a5,0x2 -80000e90: 00f707b3 add a5,a4,a5 -80000e94: fec42703 lw a4,-20(s0) -80000e98: 00e7a023 sw a4,0(a5) -80000e9c: 8c1ff0ef jal ra,8000075c -80000ea0: fea42623 sw a0,-20(s0) -80000ea4: fec42783 lw a5,-20(s0) -80000ea8: 00078663 beqz a5,80000eb4 -80000eac: 00000513 li a0,0 -80000eb0: 88dff0ef jal ra,8000073c -80000eb4: 00000013 nop -80000eb8: 01c12083 lw ra,28(sp) -80000ebc: 01812403 lw s0,24(sp) -80000ec0: 02010113 addi sp,sp,32 -80000ec4: 00008067 ret +80000e94 <_Z13simple_kernelv>: +80000e94: fe010113 addi sp,sp,-32 +80000e98: 00112e23 sw ra,28(sp) +80000e9c: 00812c23 sw s0,24(sp) +80000ea0: 02010413 addi s0,sp,32 +80000ea4: 8c1ff0ef jal ra,80000764 +80000ea8: 00050793 mv a5,a0 +80000eac: fef42623 sw a5,-20(s0) +80000eb0: 3b818713 addi a4,gp,952 # 80016bc0 +80000eb4: fec42783 lw a5,-20(s0) +80000eb8: 00279793 slli a5,a5,0x2 +80000ebc: 00f707b3 add a5,a4,a5 +80000ec0: fec42703 lw a4,-20(s0) +80000ec4: 00e7a023 sw a4,0(a5) +80000ec8: 89dff0ef jal ra,80000764 +80000ecc: 00050793 mv a5,a0 +80000ed0: fef42623 sw a5,-20(s0) +80000ed4: fec42783 lw a5,-20(s0) +80000ed8: 00078663 beqz a5,80000ee4 <_Z13simple_kernelv+0x50> +80000edc: 00000513 li a0,0 +80000ee0: 865ff0ef jal ra,80000744 +80000ee4: 00000013 nop +80000ee8: 01c12083 lw ra,28(sp) +80000eec: 01812403 lw s0,24(sp) +80000ef0: 02010113 addi sp,sp,32 +80000ef4: 00008067 ret -80000ec8 : -80000ec8: fe010113 addi sp,sp,-32 -80000ecc: 00112e23 sw ra,28(sp) -80000ed0: 00812c23 sw s0,24(sp) -80000ed4: 02010413 addi s0,sp,32 -80000ed8: 800017b7 lui a5,0x80001 -80000edc: e6c78793 addi a5,a5,-404 # 80000e6c <__BSS_END__+0xfffea230> -80000ee0: fef42623 sw a5,-20(s0) -80000ee4: fec42583 lw a1,-20(s0) -80000ee8: 00400513 li a0,4 -80000eec: 849ff0ef jal ra,80000734 -80000ef0: f7dff0ef jal ra,80000e6c -80000ef4: 41018793 addi a5,gp,1040 # 80016c18 -80000ef8: 0007a783 lw a5,0(a5) -80000efc: 00078513 mv a0,a5 -80000f00: 901ff0ef jal ra,80000800 -80000f04: 800157b7 lui a5,0x80015 -80000f08: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000f0c: 8b9ff0ef jal ra,800007c4 -80000f10: 41018793 addi a5,gp,1040 # 80016c18 -80000f14: 0047a783 lw a5,4(a5) -80000f18: 00078513 mv a0,a5 -80000f1c: 8e5ff0ef jal ra,80000800 -80000f20: 800157b7 lui a5,0x80015 -80000f24: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000f28: 89dff0ef jal ra,800007c4 -80000f2c: 41018793 addi a5,gp,1040 # 80016c18 -80000f30: 0087a783 lw a5,8(a5) -80000f34: 00078513 mv a0,a5 -80000f38: 8c9ff0ef jal ra,80000800 -80000f3c: 800157b7 lui a5,0x80015 -80000f40: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000f44: 881ff0ef jal ra,800007c4 -80000f48: 41018793 addi a5,gp,1040 # 80016c18 -80000f4c: 00c7a783 lw a5,12(a5) -80000f50: 00078513 mv a0,a5 -80000f54: 8adff0ef jal ra,80000800 -80000f58: 800157b7 lui a5,0x80015 -80000f5c: b3878513 addi a0,a5,-1224 # 80014b38 <__BSS_END__+0xffffdefc> -80000f60: 865ff0ef jal ra,800007c4 -80000f64: 00000013 nop -80000f68: 01c12083 lw ra,28(sp) -80000f6c: 01812403 lw s0,24(sp) -80000f70: 02010113 addi sp,sp,32 -80000f74: 00008067 ret +80000ef8 <_Z11test_wsapwnv>: +80000ef8: fe010113 addi sp,sp,-32 +80000efc: 00112e23 sw ra,28(sp) +80000f00: 00812c23 sw s0,24(sp) +80000f04: 02010413 addi s0,sp,32 +80000f08: 800017b7 lui a5,0x80001 +80000f0c: e9478793 addi a5,a5,-364 # 80000e94 <__BSS_END__+0xfffea258> +80000f10: fef42623 sw a5,-20(s0) +80000f14: fec42583 lw a1,-20(s0) +80000f18: 00400513 li a0,4 +80000f1c: 821ff0ef jal ra,8000073c +80000f20: f75ff0ef jal ra,80000e94 <_Z13simple_kernelv> +80000f24: 3b818793 addi a5,gp,952 # 80016bc0 +80000f28: 0007a783 lw a5,0(a5) +80000f2c: 00078513 mv a0,a5 +80000f30: 8d9ff0ef jal ra,80000808 +80000f34: 800157b7 lui a5,0x80015 +80000f38: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000f3c: 891ff0ef jal ra,800007cc +80000f40: 3b818793 addi a5,gp,952 # 80016bc0 +80000f44: 0047a783 lw a5,4(a5) +80000f48: 00078513 mv a0,a5 +80000f4c: 8bdff0ef jal ra,80000808 +80000f50: 800157b7 lui a5,0x80015 +80000f54: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000f58: 875ff0ef jal ra,800007cc +80000f5c: 3b818793 addi a5,gp,952 # 80016bc0 +80000f60: 0087a783 lw a5,8(a5) +80000f64: 00078513 mv a0,a5 +80000f68: 8a1ff0ef jal ra,80000808 +80000f6c: 800157b7 lui a5,0x80015 +80000f70: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000f74: 859ff0ef jal ra,800007cc +80000f78: 3b818793 addi a5,gp,952 # 80016bc0 +80000f7c: 00c7a783 lw a5,12(a5) +80000f80: 00078513 mv a0,a5 +80000f84: 885ff0ef jal ra,80000808 +80000f88: 800157b7 lui a5,0x80015 +80000f8c: a7078513 addi a0,a5,-1424 # 80014a70 <__BSS_END__+0xffffde34> +80000f90: 83dff0ef jal ra,800007cc +80000f94: 00000013 nop +80000f98: 01c12083 lw ra,28(sp) +80000f9c: 01812403 lw s0,24(sp) +80000fa0: 02010113 addi sp,sp,32 +80000fa4: 00008067 ret -80000f78 : -80000f78: ff010113 addi sp,sp,-16 -80000f7c: 00112623 sw ra,12(sp) -80000f80: 00812423 sw s0,8(sp) -80000f84: 01010413 addi s0,sp,16 -80000f88: ca1ff0ef jal ra,80000c28 -80000f8c: 800157b7 lui a5,0x80015 -80000f90: b3c78513 addi a0,a5,-1220 # 80014b3c <__BSS_END__+0xffffdf00> -80000f94: 831ff0ef jal ra,800007c4 -80000f98: 00400513 li a0,4 -80000f9c: fa0ff0ef jal ra,8000073c -80000fa0: d59ff0ef jal ra,80000cf8 -80000fa4: 00100513 li a0,1 -80000fa8: f94ff0ef jal ra,8000073c -80000fac: 800157b7 lui a5,0x80015 -80000fb0: b5078513 addi a0,a5,-1200 # 80014b50 <__BSS_END__+0xffffdf14> -80000fb4: 811ff0ef jal ra,800007c4 -80000fb8: f11ff0ef jal ra,80000ec8 -80000fbc: 00000013 nop -80000fc0: 00c12083 lw ra,12(sp) -80000fc4: 00812403 lw s0,8(sp) -80000fc8: 01010113 addi sp,sp,16 -80000fcc: 00008067 ret +80000fa8 <_Z16intrinsics_testsv>: +80000fa8: ff010113 addi sp,sp,-16 +80000fac: 00112623 sw ra,12(sp) +80000fb0: 00812423 sw s0,8(sp) +80000fb4: 01010413 addi s0,sp,16 +80000fb8: c91ff0ef jal ra,80000c48 <_Z8test_tmcv> +80000fbc: 800157b7 lui a5,0x80015 +80000fc0: a7478513 addi a0,a5,-1420 # 80014a74 <__BSS_END__+0xffffde38> +80000fc4: 809ff0ef jal ra,800007cc +80000fc8: 00400513 li a0,4 +80000fcc: f78ff0ef jal ra,80000744 +80000fd0: d4dff0ef jal ra,80000d1c <_Z15test_divergencev> +80000fd4: 00100513 li a0,1 +80000fd8: f6cff0ef jal ra,80000744 +80000fdc: 800157b7 lui a5,0x80015 +80000fe0: a8878513 addi a0,a5,-1400 # 80014a88 <__BSS_END__+0xffffde4c> +80000fe4: fe8ff0ef jal ra,800007cc +80000fe8: f11ff0ef jal ra,80000ef8 <_Z11test_wsapwnv> +80000fec: 00000013 nop +80000ff0: 00c12083 lw ra,12(sp) +80000ff4: 00812403 lw s0,8(sp) +80000ff8: 01010113 addi sp,sp,16 +80000ffc: 00008067 ret -80000fd0 : -80000fd0: fc010113 addi sp,sp,-64 -80000fd4: 02112e23 sw ra,60(sp) -80000fd8: 02812c23 sw s0,56(sp) -80000fdc: 04010413 addi s0,sp,64 -80000fe0: fca42623 sw a0,-52(s0) -80000fe4: fcc42783 lw a5,-52(s0) -80000fe8: fef42623 sw a5,-20(s0) -80000fec: f70ff0ef jal ra,8000075c -80000ff0: fea42423 sw a0,-24(s0) -80000ff4: f78ff0ef jal ra,8000076c -80000ff8: fea42223 sw a0,-28(s0) -80000ffc: fec42783 lw a5,-20(s0) -80001000: 0107a783 lw a5,16(a5) -80001004: fe842703 lw a4,-24(s0) -80001008: 00f77e63 bgeu a4,a5,80001024 -8000100c: fec42783 lw a5,-20(s0) -80001010: 00c7a783 lw a5,12(a5) -80001014: fe442703 lw a4,-28(s0) -80001018: 00f77663 bgeu a4,a5,80001024 -8000101c: 00100793 li a5,1 -80001020: 0080006f j 80001028 -80001024: 00000793 li a5,0 -80001028: fef401a3 sb a5,-29(s0) -8000102c: fe344783 lbu a5,-29(s0) -80001030: 0017f793 andi a5,a5,1 -80001034: fef401a3 sb a5,-29(s0) -80001038: fe344783 lbu a5,-29(s0) -8000103c: 00078513 mv a0,a5 -80001040: f0cff0ef jal ra,8000074c -80001044: fe344783 lbu a5,-29(s0) -80001048: 06078663 beqz a5,800010b4 -8000104c: fec42783 lw a5,-20(s0) -80001050: 00c7a703 lw a4,12(a5) -80001054: fe842783 lw a5,-24(s0) -80001058: 02f707b3 mul a5,a4,a5 -8000105c: fe442703 lw a4,-28(s0) -80001060: 00f707b3 add a5,a4,a5 -80001064: fcf42e23 sw a5,-36(s0) -80001068: fec42783 lw a5,-20(s0) -8000106c: 0007a703 lw a4,0(a5) -80001070: fdc42783 lw a5,-36(s0) -80001074: 00279793 slli a5,a5,0x2 -80001078: 00f707b3 add a5,a4,a5 -8000107c: 0007a683 lw a3,0(a5) -80001080: fec42783 lw a5,-20(s0) -80001084: 0047a703 lw a4,4(a5) -80001088: fdc42783 lw a5,-36(s0) -8000108c: 00279793 slli a5,a5,0x2 -80001090: 00f707b3 add a5,a4,a5 -80001094: 0007a703 lw a4,0(a5) -80001098: fec42783 lw a5,-20(s0) -8000109c: 0087a603 lw a2,8(a5) -800010a0: fdc42783 lw a5,-36(s0) -800010a4: 00279793 slli a5,a5,0x2 -800010a8: 00f607b3 add a5,a2,a5 -800010ac: 00e68733 add a4,a3,a4 -800010b0: 00e7a023 sw a4,0(a5) -800010b4: ea0ff0ef jal ra,80000754 -800010b8: 00000013 nop -800010bc: 03c12083 lw ra,60(sp) -800010c0: 03812403 lw s0,56(sp) -800010c4: 04010113 addi sp,sp,64 -800010c8: 00008067 ret +80001000 <_Z14mat_add_kernelPv>: +80001000: fc010113 addi sp,sp,-64 +80001004: 02112e23 sw ra,60(sp) +80001008: 02812c23 sw s0,56(sp) +8000100c: 04010413 addi s0,sp,64 +80001010: fca42623 sw a0,-52(s0) +80001014: fcc42783 lw a5,-52(s0) +80001018: fef42623 sw a5,-20(s0) +8000101c: f48ff0ef jal ra,80000764 +80001020: 00050793 mv a5,a0 +80001024: fef42423 sw a5,-24(s0) +80001028: f4cff0ef jal ra,80000774 +8000102c: 00050793 mv a5,a0 +80001030: fef42223 sw a5,-28(s0) +80001034: fec42783 lw a5,-20(s0) +80001038: 0107a783 lw a5,16(a5) +8000103c: fe842703 lw a4,-24(s0) +80001040: 00f77e63 bgeu a4,a5,8000105c <_Z14mat_add_kernelPv+0x5c> +80001044: fec42783 lw a5,-20(s0) +80001048: 00c7a783 lw a5,12(a5) +8000104c: fe442703 lw a4,-28(s0) +80001050: 00f77663 bgeu a4,a5,8000105c <_Z14mat_add_kernelPv+0x5c> +80001054: 00100793 li a5,1 +80001058: 0080006f j 80001060 <_Z14mat_add_kernelPv+0x60> +8000105c: 00000793 li a5,0 +80001060: fef401a3 sb a5,-29(s0) +80001064: fe344783 lbu a5,-29(s0) +80001068: 00078513 mv a0,a5 +8000106c: ee8ff0ef jal ra,80000754 +80001070: fe344783 lbu a5,-29(s0) +80001074: 06078663 beqz a5,800010e0 <_Z14mat_add_kernelPv+0xe0> +80001078: fec42783 lw a5,-20(s0) +8000107c: 00c7a703 lw a4,12(a5) +80001080: fe842783 lw a5,-24(s0) +80001084: 02f707b3 mul a5,a4,a5 +80001088: fe442703 lw a4,-28(s0) +8000108c: 00f707b3 add a5,a4,a5 +80001090: fcf42e23 sw a5,-36(s0) +80001094: fec42783 lw a5,-20(s0) +80001098: 0007a703 lw a4,0(a5) +8000109c: fdc42783 lw a5,-36(s0) +800010a0: 00279793 slli a5,a5,0x2 +800010a4: 00f707b3 add a5,a4,a5 +800010a8: 0007a683 lw a3,0(a5) +800010ac: fec42783 lw a5,-20(s0) +800010b0: 0047a703 lw a4,4(a5) +800010b4: fdc42783 lw a5,-36(s0) +800010b8: 00279793 slli a5,a5,0x2 +800010bc: 00f707b3 add a5,a4,a5 +800010c0: 0007a703 lw a4,0(a5) +800010c4: fec42783 lw a5,-20(s0) +800010c8: 0087a603 lw a2,8(a5) +800010cc: fdc42783 lw a5,-36(s0) +800010d0: 00279793 slli a5,a5,0x2 +800010d4: 00f607b3 add a5,a2,a5 +800010d8: 00e68733 add a4,a3,a4 +800010dc: 00e7a023 sw a4,0(a5) +800010e0: e7cff0ef jal ra,8000075c +800010e4: 00000013 nop +800010e8: 03c12083 lw ra,60(sp) +800010ec: 03812403 lw s0,56(sp) +800010f0: 04010113 addi sp,sp,64 +800010f4: 00008067 ret -800010cc
: -800010cc: f2010113 addi sp,sp,-224 -800010d0: 0c112e23 sw ra,220(sp) -800010d4: 0c812c23 sw s0,216(sp) -800010d8: 0e010413 addi s0,sp,224 -800010dc: 00100513 li a0,1 -800010e0: e5cff0ef jal ra,8000073c -800010e4: 800157b7 lui a5,0x80015 -800010e8: b9c78513 addi a0,a5,-1124 # 80014b9c <__BSS_END__+0xffffdf60> -800010ec: ed8ff0ef jal ra,800007c4 -800010f0: fe042623 sw zero,-20(s0) -800010f4: 0280006f j 8000111c -800010f8: fec42703 lw a4,-20(s0) -800010fc: fec42783 lw a5,-20(s0) -80001100: 00279793 slli a5,a5,0x2 -80001104: ff040693 addi a3,s0,-16 -80001108: 00f687b3 add a5,a3,a5 -8000110c: f4e7a223 sw a4,-188(a5) -80001110: fec42783 lw a5,-20(s0) -80001114: 00178793 addi a5,a5,1 -80001118: fef42623 sw a5,-20(s0) -8000111c: fec42703 lw a4,-20(s0) -80001120: 02300793 li a5,35 -80001124: fce7dae3 bge a5,a4,800010f8 -80001128: fe042423 sw zero,-24(s0) -8000112c: 0340006f j 80001160 -80001130: fe842783 lw a5,-24(s0) +800010f8
: +800010f8: f4010113 addi sp,sp,-192 +800010fc: 0a112e23 sw ra,188(sp) +80001100: 0a812c23 sw s0,184(sp) +80001104: 0c010413 addi s0,sp,192 +80001108: 00100513 li a0,1 +8000110c: e38ff0ef jal ra,80000744 +80001110: 800157b7 lui a5,0x80015 +80001114: ad478513 addi a0,a5,-1324 # 80014ad4 <__BSS_END__+0xffffde98> +80001118: eb4ff0ef jal ra,800007cc +8000111c: fe042623 sw zero,-20(s0) +80001120: fec42703 lw a4,-20(s0) +80001124: 02300793 li a5,35 +80001128: 02e7c663 blt a5,a4,80001154 +8000112c: fec42703 lw a4,-20(s0) +80001130: fec42783 lw a5,-20(s0) 80001134: 00279793 slli a5,a5,0x2 -80001138: ff040713 addi a4,s0,-16 -8000113c: 00f707b3 add a5,a4,a5 -80001140: f447a783 lw a5,-188(a5) -80001144: 00078593 mv a1,a5 -80001148: 800157b7 lui a5,0x80015 -8000114c: bac78513 addi a0,a5,-1108 # 80014bac <__BSS_END__+0xffffdf70> -80001150: f74ff0ef jal ra,800008c4 -80001154: fe842783 lw a5,-24(s0) -80001158: 00178793 addi a5,a5,1 -8000115c: fef42423 sw a5,-24(s0) -80001160: fe842703 lw a4,-24(s0) -80001164: 02300793 li a5,35 -80001168: fce7d4e3 bge a5,a4,80001130 -8000116c: 800157b7 lui a5,0x80015 -80001170: bb478513 addi a0,a5,-1100 # 80014bb4 <__BSS_END__+0xffffdf78> -80001174: e50ff0ef jal ra,800007c4 -80001178: ab1ff0ef jal ra,80000c28 +80001138: ff040693 addi a3,s0,-16 +8000113c: 00f687b3 add a5,a3,a5 +80001140: f4e7ac23 sw a4,-168(a5) +80001144: fec42783 lw a5,-20(s0) +80001148: 00178793 addi a5,a5,1 +8000114c: fef42623 sw a5,-20(s0) +80001150: fd1ff06f j 80001120 +80001154: fe042423 sw zero,-24(s0) +80001158: fe842703 lw a4,-24(s0) +8000115c: 02300793 li a5,35 +80001160: 02e7cc63 blt a5,a4,80001198 +80001164: fe842783 lw a5,-24(s0) +80001168: 00279793 slli a5,a5,0x2 +8000116c: ff040713 addi a4,s0,-16 +80001170: 00f707b3 add a5,a4,a5 +80001174: f587a783 lw a5,-168(a5) +80001178: 00078593 mv a1,a5 8000117c: 800157b7 lui a5,0x80015 -80001180: bc478513 addi a0,a5,-1084 # 80014bc4 <__BSS_END__+0xffffdf88> -80001184: e40ff0ef jal ra,800007c4 -80001188: 00400513 li a0,4 -8000118c: db0ff0ef jal ra,8000073c -80001190: b69ff0ef jal ra,80000cf8 -80001194: 00100513 li a0,1 -80001198: da4ff0ef jal ra,8000073c -8000119c: 800157b7 lui a5,0x80015 -800011a0: bd878513 addi a0,a5,-1064 # 80014bd8 <__BSS_END__+0xffffdf9c> -800011a4: e20ff0ef jal ra,800007c4 -800011a8: d21ff0ef jal ra,80000ec8 -800011ac: 800157b7 lui a5,0x80015 -800011b0: be878513 addi a0,a5,-1048 # 80014be8 <__BSS_END__+0xffffdfac> -800011b4: e10ff0ef jal ra,800007c4 -800011b8: ffff07b7 lui a5,0xffff0 -800011bc: fef42223 sw a5,-28(s0) -800011c0: fe042023 sw zero,-32(s0) -800011c4: fc042e23 sw zero,-36(s0) -800011c8: 0800006f j 80001248 -800011cc: fe442783 lw a5,-28(s0) -800011d0: fe042703 lw a4,-32(s0) -800011d4: 00e7a023 sw a4,0(a5) # ffff0000 <__BSS_END__+0x7ffd93c4> -800011d8: fe442783 lw a5,-28(s0) -800011dc: 0007a783 lw a5,0(a5) -800011e0: fcf42223 sw a5,-60(s0) -800011e4: fe442783 lw a5,-28(s0) -800011e8: 00078593 mv a1,a5 -800011ec: 800157b7 lui a5,0x80015 -800011f0: bfc78513 addi a0,a5,-1028 # 80014bfc <__BSS_END__+0xffffdfc0> -800011f4: ed0ff0ef jal ra,800008c4 -800011f8: fe042583 lw a1,-32(s0) -800011fc: 800157b7 lui a5,0x80015 -80001200: c0478513 addi a0,a5,-1020 # 80014c04 <__BSS_END__+0xffffdfc8> -80001204: ec0ff0ef jal ra,800008c4 -80001208: fc442583 lw a1,-60(s0) -8000120c: 800157b7 lui a5,0x80015 -80001210: c1878513 addi a0,a5,-1000 # 80014c18 <__BSS_END__+0xffffdfdc> -80001214: eb0ff0ef jal ra,800008c4 -80001218: 800157b7 lui a5,0x80015 -8000121c: c2878513 addi a0,a5,-984 # 80014c28 <__BSS_END__+0xffffdfec> -80001220: da4ff0ef jal ra,800007c4 -80001224: fe042783 lw a5,-32(s0) -80001228: 00178793 addi a5,a5,1 -8000122c: fef42023 sw a5,-32(s0) -80001230: fe442783 lw a5,-28(s0) -80001234: 00478793 addi a5,a5,4 -80001238: fef42223 sw a5,-28(s0) -8000123c: fdc42783 lw a5,-36(s0) -80001240: 00178793 addi a5,a5,1 -80001244: fcf42e23 sw a5,-36(s0) -80001248: fdc42703 lw a4,-36(s0) -8000124c: 00400793 li a5,4 -80001250: f6e7dee3 bge a5,a4,800011cc -80001254: 800157b7 lui a5,0x80015 -80001258: c4078513 addi a0,a5,-960 # 80014c40 <__BSS_END__+0xffffe004> -8000125c: d68ff0ef jal ra,800007c4 -80001260: 91418793 addi a5,gp,-1772 # 8001611c -80001264: f2f42023 sw a5,-224(s0) -80001268: 95418793 addi a5,gp,-1708 # 8001615c -8000126c: f2f42223 sw a5,-220(s0) -80001270: 38018793 addi a5,gp,896 # 80016b88 -80001274: f2f42423 sw a5,-216(s0) -80001278: 00400793 li a5,4 -8000127c: f2f42623 sw a5,-212(s0) -80001280: 00400793 li a5,4 -80001284: f2f42823 sw a5,-208(s0) -80001288: 00400793 li a5,4 -8000128c: fcf42823 sw a5,-48(s0) -80001290: 00400793 li a5,4 -80001294: fcf42623 sw a5,-52(s0) -80001298: fd042703 lw a4,-48(s0) -8000129c: fcc42583 lw a1,-52(s0) -800012a0: f2040793 addi a5,s0,-224 -800012a4: 00078693 mv a3,a5 -800012a8: 800017b7 lui a5,0x80001 -800012ac: fd078613 addi a2,a5,-48 # 80000fd0 <__BSS_END__+0xfffea394> -800012b0: 00070513 mv a0,a4 -800012b4: ebcff0ef jal ra,80000970 -800012b8: fc042c23 sw zero,-40(s0) -800012bc: 07c0006f j 80001338 -800012c0: fc042a23 sw zero,-44(s0) -800012c4: 0500006f j 80001314 -800012c8: f2c42703 lw a4,-212(s0) -800012cc: fd842783 lw a5,-40(s0) -800012d0: 02f70733 mul a4,a4,a5 -800012d4: fd442783 lw a5,-44(s0) -800012d8: 00f707b3 add a5,a4,a5 -800012dc: fcf42423 sw a5,-56(s0) -800012e0: 38018713 addi a4,gp,896 # 80016b88 -800012e4: fc842783 lw a5,-56(s0) -800012e8: 00279793 slli a5,a5,0x2 -800012ec: 00f707b3 add a5,a4,a5 -800012f0: 0007a783 lw a5,0(a5) -800012f4: 00078513 mv a0,a5 -800012f8: d08ff0ef jal ra,80000800 -800012fc: 800157b7 lui a5,0x80015 -80001300: c6078513 addi a0,a5,-928 # 80014c60 <__BSS_END__+0xffffe024> -80001304: cc0ff0ef jal ra,800007c4 -80001308: fd442783 lw a5,-44(s0) -8000130c: 00178793 addi a5,a5,1 -80001310: fcf42a23 sw a5,-44(s0) -80001314: f2c42703 lw a4,-212(s0) -80001318: fd442783 lw a5,-44(s0) -8000131c: fae7e6e3 bltu a5,a4,800012c8 -80001320: 800157b7 lui a5,0x80015 -80001324: c6478513 addi a0,a5,-924 # 80014c64 <__BSS_END__+0xffffe028> -80001328: c9cff0ef jal ra,800007c4 -8000132c: fd842783 lw a5,-40(s0) -80001330: 00178793 addi a5,a5,1 -80001334: fcf42c23 sw a5,-40(s0) -80001338: f3042703 lw a4,-208(s0) -8000133c: fd842783 lw a5,-40(s0) -80001340: f8e7e0e3 bltu a5,a4,800012c0 -80001344: 00000793 li a5,0 -80001348: 00078513 mv a0,a5 -8000134c: 0dc12083 lw ra,220(sp) -80001350: 0d812403 lw s0,216(sp) -80001354: 0e010113 addi sp,sp,224 -80001358: 00008067 ret +80001180: b0078513 addi a0,a5,-1280 # 80014b00 <__BSS_END__+0xffffdec4> +80001184: f4cff0ef jal ra,800008d0 +80001188: fe842783 lw a5,-24(s0) +8000118c: 00178793 addi a5,a5,1 +80001190: fef42423 sw a5,-24(s0) +80001194: fc5ff06f j 80001158 +80001198: 800157b7 lui a5,0x80015 +8000119c: b0878513 addi a0,a5,-1272 # 80014b08 <__BSS_END__+0xffffdecc> +800011a0: e2cff0ef jal ra,800007cc +800011a4: aa5ff0ef jal ra,80000c48 <_Z8test_tmcv> +800011a8: 800157b7 lui a5,0x80015 +800011ac: b1878513 addi a0,a5,-1256 # 80014b18 <__BSS_END__+0xffffdedc> +800011b0: e1cff0ef jal ra,800007cc +800011b4: 00400513 li a0,4 +800011b8: d8cff0ef jal ra,80000744 +800011bc: b61ff0ef jal ra,80000d1c <_Z15test_divergencev> +800011c0: 00100513 li a0,1 +800011c4: d80ff0ef jal ra,80000744 +800011c8: 800157b7 lui a5,0x80015 +800011cc: b2c78513 addi a0,a5,-1236 # 80014b2c <__BSS_END__+0xffffdef0> +800011d0: dfcff0ef jal ra,800007cc +800011d4: d25ff0ef jal ra,80000ef8 <_Z11test_wsapwnv> +800011d8: 800157b7 lui a5,0x80015 +800011dc: b3c78513 addi a0,a5,-1220 # 80014b3c <__BSS_END__+0xffffdf00> +800011e0: decff0ef jal ra,800007cc +800011e4: ffff07b7 lui a5,0xffff0 +800011e8: fef42223 sw a5,-28(s0) +800011ec: fe042023 sw zero,-32(s0) +800011f0: fc042e23 sw zero,-36(s0) +800011f4: fdc42703 lw a4,-36(s0) +800011f8: 00400793 li a5,4 +800011fc: 08e7c263 blt a5,a4,80001280 +80001200: fe442783 lw a5,-28(s0) +80001204: fe042703 lw a4,-32(s0) +80001208: 00e7a023 sw a4,0(a5) # ffff0000 <__BSS_END__+0x7ffd93c4> +8000120c: fe442783 lw a5,-28(s0) +80001210: 0007a783 lw a5,0(a5) +80001214: fcf42c23 sw a5,-40(s0) +80001218: fe442783 lw a5,-28(s0) +8000121c: 00078593 mv a1,a5 +80001220: 800157b7 lui a5,0x80015 +80001224: b5078513 addi a0,a5,-1200 # 80014b50 <__BSS_END__+0xffffdf14> +80001228: ea8ff0ef jal ra,800008d0 +8000122c: fe042583 lw a1,-32(s0) +80001230: 800157b7 lui a5,0x80015 +80001234: b5878513 addi a0,a5,-1192 # 80014b58 <__BSS_END__+0xffffdf1c> +80001238: e98ff0ef jal ra,800008d0 +8000123c: fd842583 lw a1,-40(s0) +80001240: 800157b7 lui a5,0x80015 +80001244: b6c78513 addi a0,a5,-1172 # 80014b6c <__BSS_END__+0xffffdf30> +80001248: e88ff0ef jal ra,800008d0 +8000124c: 800157b7 lui a5,0x80015 +80001250: b7c78513 addi a0,a5,-1156 # 80014b7c <__BSS_END__+0xffffdf40> +80001254: d78ff0ef jal ra,800007cc +80001258: fe042783 lw a5,-32(s0) +8000125c: 00178793 addi a5,a5,1 +80001260: fef42023 sw a5,-32(s0) +80001264: fe442783 lw a5,-28(s0) +80001268: 00478793 addi a5,a5,4 +8000126c: fef42223 sw a5,-28(s0) +80001270: fdc42783 lw a5,-36(s0) +80001274: 00178793 addi a5,a5,1 +80001278: fcf42e23 sw a5,-36(s0) +8000127c: f79ff06f j 800011f4 +80001280: 00000793 li a5,0 +80001284: 00078513 mv a0,a5 +80001288: 0bc12083 lw ra,188(sp) +8000128c: 0b812403 lw s0,184(sp) +80001290: 0c010113 addi sp,sp,192 +80001294: 00008067 ret -8000135c : -8000135c: ff010113 addi sp,sp,-16 -80001360: 00000593 li a1,0 -80001364: 00812423 sw s0,8(sp) -80001368: 00112623 sw ra,12(sp) -8000136c: 00050413 mv s0,a0 -80001370: 56d020ef jal ra,800040dc <__call_exitprocs> -80001374: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> -80001378: 03c52783 lw a5,60(a0) -8000137c: 00078463 beqz a5,80001384 -80001380: 000780e7 jalr a5 -80001384: 00040513 mv a0,s0 -80001388: 9d4ff0ef jal ra,8000055c <_exit> +80001298 : +80001298: ff010113 addi sp,sp,-16 +8000129c: 00000593 li a1,0 +800012a0: 00812423 sw s0,8(sp) +800012a4: 00112623 sw ra,12(sp) +800012a8: 00050413 mv s0,a0 +800012ac: 56d020ef jal ra,80004018 <__call_exitprocs> +800012b0: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> +800012b4: 03c52783 lw a5,60(a0) +800012b8: 00078463 beqz a5,800012c0 +800012bc: 000780e7 jalr a5 +800012c0: 00040513 mv a0,s0 +800012c4: aa0ff0ef jal ra,80000564 <_exit> -8000138c <_printf_r>: -8000138c: fc010113 addi sp,sp,-64 -80001390: 02c12423 sw a2,40(sp) -80001394: 02d12623 sw a3,44(sp) -80001398: 02e12823 sw a4,48(sp) -8000139c: 02f12a23 sw a5,52(sp) -800013a0: 03012c23 sw a6,56(sp) -800013a4: 03112e23 sw a7,60(sp) -800013a8: 00058613 mv a2,a1 -800013ac: 00852583 lw a1,8(a0) -800013b0: 02810693 addi a3,sp,40 -800013b4: 00112e23 sw ra,28(sp) -800013b8: 00d12623 sw a3,12(sp) -800013bc: 05c000ef jal ra,80001418 <_vfprintf_r> -800013c0: 01c12083 lw ra,28(sp) -800013c4: 04010113 addi sp,sp,64 -800013c8: 00008067 ret +800012c8 <_printf_r>: +800012c8: fc010113 addi sp,sp,-64 +800012cc: 02c12423 sw a2,40(sp) +800012d0: 02d12623 sw a3,44(sp) +800012d4: 02e12823 sw a4,48(sp) +800012d8: 02f12a23 sw a5,52(sp) +800012dc: 03012c23 sw a6,56(sp) +800012e0: 03112e23 sw a7,60(sp) +800012e4: 00058613 mv a2,a1 +800012e8: 00852583 lw a1,8(a0) +800012ec: 02810693 addi a3,sp,40 +800012f0: 00112e23 sw ra,28(sp) +800012f4: 00d12623 sw a3,12(sp) +800012f8: 05c000ef jal ra,80001354 <_vfprintf_r> +800012fc: 01c12083 lw ra,28(sp) +80001300: 04010113 addi sp,sp,64 +80001304: 00008067 ret -800013cc : -800013cc: 3601a303 lw t1,864(gp) # 80016b68 <_impure_ptr> -800013d0: fc010113 addi sp,sp,-64 -800013d4: 02c12423 sw a2,40(sp) -800013d8: 02d12623 sw a3,44(sp) -800013dc: 02b12223 sw a1,36(sp) -800013e0: 02e12823 sw a4,48(sp) -800013e4: 02f12a23 sw a5,52(sp) -800013e8: 03012c23 sw a6,56(sp) -800013ec: 03112e23 sw a7,60(sp) -800013f0: 00832583 lw a1,8(t1) -800013f4: 02410693 addi a3,sp,36 -800013f8: 00050613 mv a2,a0 -800013fc: 00030513 mv a0,t1 -80001400: 00112e23 sw ra,28(sp) -80001404: 00d12623 sw a3,12(sp) -80001408: 010000ef jal ra,80001418 <_vfprintf_r> -8000140c: 01c12083 lw ra,28(sp) -80001410: 04010113 addi sp,sp,64 -80001414: 00008067 ret +80001308 : +80001308: 3601a303 lw t1,864(gp) # 80016b68 <_impure_ptr> +8000130c: fc010113 addi sp,sp,-64 +80001310: 02c12423 sw a2,40(sp) +80001314: 02d12623 sw a3,44(sp) +80001318: 02b12223 sw a1,36(sp) +8000131c: 02e12823 sw a4,48(sp) +80001320: 02f12a23 sw a5,52(sp) +80001324: 03012c23 sw a6,56(sp) +80001328: 03112e23 sw a7,60(sp) +8000132c: 00832583 lw a1,8(t1) +80001330: 02410693 addi a3,sp,36 +80001334: 00050613 mv a2,a0 +80001338: 00030513 mv a0,t1 +8000133c: 00112e23 sw ra,28(sp) +80001340: 00d12623 sw a3,12(sp) +80001344: 010000ef jal ra,80001354 <_vfprintf_r> +80001348: 01c12083 lw ra,28(sp) +8000134c: 04010113 addi sp,sp,64 +80001350: 00008067 ret -80001418 <_vfprintf_r>: -80001418: e1010113 addi sp,sp,-496 -8000141c: 1e112623 sw ra,492(sp) -80001420: 1f212023 sw s2,480(sp) -80001424: 1d812423 sw s8,456(sp) -80001428: 1da12023 sw s10,448(sp) -8000142c: 00058c13 mv s8,a1 -80001430: 00060913 mv s2,a2 -80001434: 00d12a23 sw a3,20(sp) -80001438: 1e812423 sw s0,488(sp) -8000143c: 1e912223 sw s1,484(sp) -80001440: 1d312e23 sw s3,476(sp) -80001444: 1d412c23 sw s4,472(sp) -80001448: 1d512a23 sw s5,468(sp) -8000144c: 1d612823 sw s6,464(sp) -80001450: 1d712623 sw s7,460(sp) -80001454: 1d912223 sw s9,452(sp) -80001458: 1bb12e23 sw s11,444(sp) -8000145c: 00050d13 mv s10,a0 -80001460: 548060ef jal ra,800079a8 <_localeconv_r> -80001464: 00052783 lw a5,0(a0) -80001468: 00078513 mv a0,a5 -8000146c: 02f12823 sw a5,48(sp) -80001470: 4f0080ef jal ra,80009960 -80001474: 02a12623 sw a0,44(sp) -80001478: 0e012823 sw zero,240(sp) -8000147c: 0e012a23 sw zero,244(sp) -80001480: 0e012c23 sw zero,248(sp) -80001484: 0e012e23 sw zero,252(sp) -80001488: 000d0663 beqz s10,80001494 <_vfprintf_r+0x7c> -8000148c: 038d2703 lw a4,56(s10) -80001490: 0a0708e3 beqz a4,80001d40 <_vfprintf_r+0x928> -80001494: 00cc1683 lh a3,12(s8) -80001498: 01069713 slli a4,a3,0x10 -8000149c: 01269793 slli a5,a3,0x12 -800014a0: 01075713 srli a4,a4,0x10 -800014a4: 0207ca63 bltz a5,800014d8 <_vfprintf_r+0xc0> -800014a8: 00002737 lui a4,0x2 -800014ac: 064c2603 lw a2,100(s8) -800014b0: 00e6e733 or a4,a3,a4 -800014b4: 01071713 slli a4,a4,0x10 -800014b8: ffffe6b7 lui a3,0xffffe -800014bc: 41075713 srai a4,a4,0x10 -800014c0: fff68693 addi a3,a3,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> -800014c4: 00d676b3 and a3,a2,a3 -800014c8: 00ec1623 sh a4,12(s8) -800014cc: 01071713 slli a4,a4,0x10 -800014d0: 06dc2223 sw a3,100(s8) -800014d4: 01075713 srli a4,a4,0x10 -800014d8: 00877693 andi a3,a4,8 -800014dc: 2e068863 beqz a3,800017cc <_vfprintf_r+0x3b4> -800014e0: 010c2683 lw a3,16(s8) -800014e4: 2e068463 beqz a3,800017cc <_vfprintf_r+0x3b4> -800014e8: 01a77713 andi a4,a4,26 -800014ec: 00a00693 li a3,10 -800014f0: 30d70063 beq a4,a3,800017f0 <_vfprintf_r+0x3d8> -800014f4: 10c10793 addi a5,sp,268 -800014f8: 80015737 lui a4,0x80015 -800014fc: 0ef12223 sw a5,228(sp) -80001500: 00078893 mv a7,a5 -80001504: cac70793 addi a5,a4,-852 # 80014cac <__BSS_END__+0xffffe070> -80001508: 80015737 lui a4,0x80015 -8000150c: 00f12c23 sw a5,24(sp) -80001510: 00090b13 mv s6,s2 -80001514: e2870793 addi a5,a4,-472 # 80014e28 <__BSS_END__+0xffffe1ec> -80001518: 00f12423 sw a5,8(sp) -8000151c: 000b4783 lbu a5,0(s6) -80001520: 0e012623 sw zero,236(sp) -80001524: 0e012423 sw zero,232(sp) -80001528: 02012023 sw zero,32(sp) -8000152c: 02012a23 sw zero,52(sp) -80001530: 02012c23 sw zero,56(sp) -80001534: 02012e23 sw zero,60(sp) -80001538: 04012423 sw zero,72(sp) -8000153c: 04012623 sw zero,76(sp) -80001540: 00012623 sw zero,12(sp) -80001544: 22078663 beqz a5,80001770 <_vfprintf_r+0x358> -80001548: 000b0413 mv s0,s6 -8000154c: 02500693 li a3,37 -80001550: 30d78a63 beq a5,a3,80001864 <_vfprintf_r+0x44c> -80001554: 00144783 lbu a5,1(s0) -80001558: 00140413 addi s0,s0,1 -8000155c: fe079ae3 bnez a5,80001550 <_vfprintf_r+0x138> -80001560: 416404b3 sub s1,s0,s6 -80001564: 21640663 beq s0,s6,80001770 <_vfprintf_r+0x358> -80001568: 0ec12683 lw a3,236(sp) -8000156c: 0e812783 lw a5,232(sp) -80001570: 0168a023 sw s6,0(a7) -80001574: 009686b3 add a3,a3,s1 -80001578: 00178793 addi a5,a5,1 -8000157c: 0098a223 sw s1,4(a7) -80001580: 0ed12623 sw a3,236(sp) -80001584: 0ef12423 sw a5,232(sp) -80001588: 00700693 li a3,7 -8000158c: 00888893 addi a7,a7,8 -80001590: 2ef6c263 blt a3,a5,80001874 <_vfprintf_r+0x45c> -80001594: 00c12703 lw a4,12(sp) -80001598: 00044783 lbu a5,0(s0) -8000159c: 00970733 add a4,a4,s1 -800015a0: 00e12623 sw a4,12(sp) -800015a4: 1c078663 beqz a5,80001770 <_vfprintf_r+0x358> -800015a8: 00144483 lbu s1,1(s0) -800015ac: 0c0103a3 sb zero,199(sp) -800015b0: 00140413 addi s0,s0,1 -800015b4: fff00d93 li s11,-1 -800015b8: 00000993 li s3,0 -800015bc: 00000a13 li s4,0 -800015c0: 05a00913 li s2,90 -800015c4: 00900a93 li s5,9 -800015c8: 02a00b93 li s7,42 -800015cc: 00088c93 mv s9,a7 -800015d0: 00140413 addi s0,s0,1 -800015d4: fe048793 addi a5,s1,-32 -800015d8: 04f96463 bltu s2,a5,80001620 <_vfprintf_r+0x208> -800015dc: 01812703 lw a4,24(sp) -800015e0: 00279793 slli a5,a5,0x2 -800015e4: 00e787b3 add a5,a5,a4 -800015e8: 0007a783 lw a5,0(a5) -800015ec: 00078067 jr a5 -800015f0: 00000993 li s3,0 -800015f4: fd048693 addi a3,s1,-48 -800015f8: 00044483 lbu s1,0(s0) -800015fc: 00299793 slli a5,s3,0x2 -80001600: 013787b3 add a5,a5,s3 -80001604: 00179793 slli a5,a5,0x1 -80001608: 00f689b3 add s3,a3,a5 -8000160c: fd048693 addi a3,s1,-48 -80001610: 00140413 addi s0,s0,1 -80001614: fedaf2e3 bgeu s5,a3,800015f8 <_vfprintf_r+0x1e0> -80001618: fe048793 addi a5,s1,-32 -8000161c: fcf970e3 bgeu s2,a5,800015dc <_vfprintf_r+0x1c4> -80001620: 000c8893 mv a7,s9 -80001624: 14048663 beqz s1,80001770 <_vfprintf_r+0x358> -80001628: 14910623 sb s1,332(sp) -8000162c: 0c0103a3 sb zero,199(sp) -80001630: 00100a93 li s5,1 -80001634: 00100c93 li s9,1 -80001638: 14c10b13 addi s6,sp,332 -8000163c: 00012823 sw zero,16(sp) -80001640: 00000d93 li s11,0 -80001644: 02012423 sw zero,40(sp) -80001648: 02012223 sw zero,36(sp) -8000164c: 00012e23 sw zero,28(sp) -80001650: 002a7b93 andi s7,s4,2 -80001654: 000b8463 beqz s7,8000165c <_vfprintf_r+0x244> -80001658: 002a8a93 addi s5,s5,2 -8000165c: 084a7913 andi s2,s4,132 -80001660: 0ec12783 lw a5,236(sp) -80001664: 00091663 bnez s2,80001670 <_vfprintf_r+0x258> -80001668: 41598833 sub a6,s3,s5 -8000166c: 710046e3 bgtz a6,80002578 <_vfprintf_r+0x1160> -80001670: 0c714683 lbu a3,199(sp) -80001674: 02068a63 beqz a3,800016a8 <_vfprintf_r+0x290> -80001678: 0e812683 lw a3,232(sp) -8000167c: 0c710613 addi a2,sp,199 -80001680: 00c8a023 sw a2,0(a7) -80001684: 00178793 addi a5,a5,1 -80001688: 00100613 li a2,1 -8000168c: 00168693 addi a3,a3,1 -80001690: 00c8a223 sw a2,4(a7) -80001694: 0ef12623 sw a5,236(sp) -80001698: 0ed12423 sw a3,232(sp) -8000169c: 00700613 li a2,7 -800016a0: 00888893 addi a7,a7,8 -800016a4: 52d64263 blt a2,a3,80001bc8 <_vfprintf_r+0x7b0> -800016a8: 020b8c63 beqz s7,800016e0 <_vfprintf_r+0x2c8> -800016ac: 0e812683 lw a3,232(sp) -800016b0: 0c810613 addi a2,sp,200 -800016b4: 00c8a023 sw a2,0(a7) -800016b8: 00278793 addi a5,a5,2 -800016bc: 00200613 li a2,2 -800016c0: 00168693 addi a3,a3,1 -800016c4: 00c8a223 sw a2,4(a7) -800016c8: 0ef12623 sw a5,236(sp) -800016cc: 0ed12423 sw a3,232(sp) -800016d0: 00700613 li a2,7 -800016d4: 00888893 addi a7,a7,8 -800016d8: 00d65463 bge a2,a3,800016e0 <_vfprintf_r+0x2c8> -800016dc: 78d0006f j 80002668 <_vfprintf_r+0x1250> -800016e0: 08000693 li a3,128 -800016e4: 3cd90ee3 beq s2,a3,800022c0 <_vfprintf_r+0xea8> -800016e8: 419d8db3 sub s11,s11,s9 -800016ec: 49b04ae3 bgtz s11,80002380 <_vfprintf_r+0xf68> -800016f0: 100a7693 andi a3,s4,256 -800016f4: 280698e3 bnez a3,80002184 <_vfprintf_r+0xd6c> -800016f8: 0e812703 lw a4,232(sp) -800016fc: 019787b3 add a5,a5,s9 -80001700: 0168a023 sw s6,0(a7) -80001704: 00170713 addi a4,a4,1 -80001708: 0198a223 sw s9,4(a7) -8000170c: 0ef12623 sw a5,236(sp) -80001710: 0ee12423 sw a4,232(sp) -80001714: 00700693 li a3,7 -80001718: 54e6c863 blt a3,a4,80001c68 <_vfprintf_r+0x850> -8000171c: 00888893 addi a7,a7,8 -80001720: 004a7a13 andi s4,s4,4 -80001724: 000a0663 beqz s4,80001730 <_vfprintf_r+0x318> -80001728: 415984b3 sub s1,s3,s5 -8000172c: 54904e63 bgtz s1,80001c88 <_vfprintf_r+0x870> -80001730: 0159d463 bge s3,s5,80001738 <_vfprintf_r+0x320> -80001734: 000a8993 mv s3,s5 -80001738: 00c12703 lw a4,12(sp) -8000173c: 01370733 add a4,a4,s3 -80001740: 00e12623 sw a4,12(sp) -80001744: 4e0798e3 bnez a5,80002434 <_vfprintf_r+0x101c> -80001748: 01012783 lw a5,16(sp) -8000174c: 0e012423 sw zero,232(sp) -80001750: 00078863 beqz a5,80001760 <_vfprintf_r+0x348> -80001754: 01012583 lw a1,16(sp) -80001758: 000d0513 mv a0,s10 -8000175c: 278030ef jal ra,800049d4 <_free_r> -80001760: 10c10893 addi a7,sp,268 -80001764: 00040b13 mv s6,s0 -80001768: 000b4783 lbu a5,0(s6) -8000176c: dc079ee3 bnez a5,80001548 <_vfprintf_r+0x130> -80001770: 0ec12783 lw a5,236(sp) -80001774: 00078463 beqz a5,8000177c <_vfprintf_r+0x364> -80001778: 3250106f j 8000329c <_vfprintf_r+0x1e84> -8000177c: 00cc5783 lhu a5,12(s8) -80001780: 0407f793 andi a5,a5,64 -80001784: 00078463 beqz a5,8000178c <_vfprintf_r+0x374> -80001788: 2300206f j 800039b8 <_vfprintf_r+0x25a0> -8000178c: 1ec12083 lw ra,492(sp) -80001790: 1e812403 lw s0,488(sp) -80001794: 00c12503 lw a0,12(sp) -80001798: 1e412483 lw s1,484(sp) -8000179c: 1e012903 lw s2,480(sp) -800017a0: 1dc12983 lw s3,476(sp) -800017a4: 1d812a03 lw s4,472(sp) -800017a8: 1d412a83 lw s5,468(sp) -800017ac: 1d012b03 lw s6,464(sp) -800017b0: 1cc12b83 lw s7,460(sp) -800017b4: 1c812c03 lw s8,456(sp) -800017b8: 1c412c83 lw s9,452(sp) -800017bc: 1c012d03 lw s10,448(sp) -800017c0: 1bc12d83 lw s11,444(sp) -800017c4: 1f010113 addi sp,sp,496 -800017c8: 00008067 ret -800017cc: 000c0593 mv a1,s8 -800017d0: 000d0513 mv a0,s10 -800017d4: 7ac020ef jal ra,80003f80 <__swsetup_r> -800017d8: 00050463 beqz a0,800017e0 <_vfprintf_r+0x3c8> -800017dc: 1dc0206f j 800039b8 <_vfprintf_r+0x25a0> -800017e0: 00cc5703 lhu a4,12(s8) -800017e4: 00a00693 li a3,10 -800017e8: 01a77713 andi a4,a4,26 -800017ec: d0d714e3 bne a4,a3,800014f4 <_vfprintf_r+0xdc> -800017f0: 00ec1703 lh a4,14(s8) -800017f4: d00740e3 bltz a4,800014f4 <_vfprintf_r+0xdc> -800017f8: 01412683 lw a3,20(sp) -800017fc: 00090613 mv a2,s2 -80001800: 000c0593 mv a1,s8 -80001804: 000d0513 mv a0,s10 -80001808: 6b8020ef jal ra,80003ec0 <__sbprintf> -8000180c: 00a12623 sw a0,12(sp) -80001810: f7dff06f j 8000178c <_vfprintf_r+0x374> -80001814: 000d0513 mv a0,s10 -80001818: 190060ef jal ra,800079a8 <_localeconv_r> -8000181c: 00452783 lw a5,4(a0) -80001820: 00078513 mv a0,a5 -80001824: 04f12623 sw a5,76(sp) -80001828: 138080ef jal ra,80009960 -8000182c: 00050793 mv a5,a0 -80001830: 000d0513 mv a0,s10 -80001834: 00078493 mv s1,a5 -80001838: 04f12423 sw a5,72(sp) -8000183c: 16c060ef jal ra,800079a8 <_localeconv_r> -80001840: 00852783 lw a5,8(a0) -80001844: 02f12e23 sw a5,60(sp) -80001848: 00048463 beqz s1,80001850 <_vfprintf_r+0x438> -8000184c: 12c0106f j 80002978 <_vfprintf_r+0x1560> -80001850: 00044483 lbu s1,0(s0) -80001854: d7dff06f j 800015d0 <_vfprintf_r+0x1b8> -80001858: 00044483 lbu s1,0(s0) -8000185c: 020a6a13 ori s4,s4,32 -80001860: d71ff06f j 800015d0 <_vfprintf_r+0x1b8> -80001864: 416404b3 sub s1,s0,s6 -80001868: d16410e3 bne s0,s6,80001568 <_vfprintf_r+0x150> -8000186c: 00044783 lbu a5,0(s0) -80001870: d35ff06f j 800015a4 <_vfprintf_r+0x18c> -80001874: 0e410613 addi a2,sp,228 -80001878: 000c0593 mv a1,s8 -8000187c: 000d0513 mv a0,s10 -80001880: 5190a0ef jal ra,8000c598 <__sprint_r> -80001884: ee051ce3 bnez a0,8000177c <_vfprintf_r+0x364> -80001888: 10c10893 addi a7,sp,268 -8000188c: d09ff06f j 80001594 <_vfprintf_r+0x17c> -80001890: 008a7793 andi a5,s4,8 -80001894: 000c8893 mv a7,s9 -80001898: 00078463 beqz a5,800018a0 <_vfprintf_r+0x488> -8000189c: 12c0106f j 800029c8 <_vfprintf_r+0x15b0> -800018a0: 01412783 lw a5,20(sp) -800018a4: 0b010513 addi a0,sp,176 -800018a8: 01912823 sw s9,16(sp) -800018ac: 00778793 addi a5,a5,7 -800018b0: ff87f793 andi a5,a5,-8 -800018b4: 0007a583 lw a1,0(a5) -800018b8: 0047a603 lw a2,4(a5) -800018bc: 00878793 addi a5,a5,8 -800018c0: 00f12a23 sw a5,20(sp) -800018c4: 3c5120ef jal ra,80014488 <__extenddftf2> -800018c8: 0b012783 lw a5,176(sp) -800018cc: 01012883 lw a7,16(sp) -800018d0: 0ef12823 sw a5,240(sp) -800018d4: 0b412783 lw a5,180(sp) -800018d8: 0ef12a23 sw a5,244(sp) -800018dc: 0b812783 lw a5,184(sp) -800018e0: 0ef12c23 sw a5,248(sp) -800018e4: 0bc12783 lw a5,188(sp) -800018e8: 0ef12e23 sw a5,252(sp) -800018ec: 0f010513 addi a0,sp,240 -800018f0: 01112823 sw a7,16(sp) -800018f4: 048060ef jal ra,8000793c <_ldcheck> -800018f8: 0ca12623 sw a0,204(sp) -800018fc: 00200793 li a5,2 -80001900: 01012883 lw a7,16(sp) -80001904: 00f51463 bne a0,a5,8000190c <_vfprintf_r+0x4f4> -80001908: 4fc0106f j 80002e04 <_vfprintf_r+0x19ec> -8000190c: 00100793 li a5,1 -80001910: 00f51463 bne a0,a5,80001918 <_vfprintf_r+0x500> -80001914: 6440106f j 80002f58 <_vfprintf_r+0x1b40> -80001918: 06100793 li a5,97 -8000191c: 00f49463 bne s1,a5,80001924 <_vfprintf_r+0x50c> -80001920: 1c40206f j 80003ae4 <_vfprintf_r+0x26cc> -80001924: 04100793 li a5,65 -80001928: 00f49463 bne s1,a5,80001930 <_vfprintf_r+0x518> -8000192c: 1910106f j 800032bc <_vfprintf_r+0x1ea4> -80001930: fdf4fb93 andi s7,s1,-33 -80001934: fff00793 li a5,-1 -80001938: 05712223 sw s7,68(sp) -8000193c: 00fd9463 bne s11,a5,80001944 <_vfprintf_r+0x52c> -80001940: 2800206f j 80003bc0 <_vfprintf_r+0x27a8> -80001944: 04700793 li a5,71 -80001948: 00fb9463 bne s7,a5,80001950 <_vfprintf_r+0x538> -8000194c: 1e00206f j 80003b2c <_vfprintf_r+0x2714> -80001950: 0fc12303 lw t1,252(sp) -80001954: 03412423 sw s4,40(sp) -80001958: 0f012e03 lw t3,240(sp) -8000195c: 0f412e83 lw t4,244(sp) -80001960: 0f812f03 lw t5,248(sp) -80001964: 100a6793 ori a5,s4,256 -80001968: 00035463 bgez t1,80001970 <_vfprintf_r+0x558> -8000196c: 3e00206f j 80003d4c <_vfprintf_r+0x2934> -80001970: 04012c23 sw zero,88(sp) -80001974: 00078a13 mv s4,a5 -80001978: 00012823 sw zero,16(sp) -8000197c: 04600793 li a5,70 -80001980: 00fb9463 bne s7,a5,80001988 <_vfprintf_r+0x570> -80001984: 6990106f j 8000381c <_vfprintf_r+0x2404> -80001988: 04500793 li a5,69 -8000198c: 05112823 sw a7,80(sp) -80001990: 00fb8463 beq s7,a5,80001998 <_vfprintf_r+0x580> -80001994: 6090106f j 8000379c <_vfprintf_r+0x2384> -80001998: 001d8913 addi s2,s11,1 -8000199c: 0b010a93 addi s5,sp,176 -800019a0: 00090693 mv a3,s2 -800019a4: 0dc10813 addi a6,sp,220 -800019a8: 0d010793 addi a5,sp,208 -800019ac: 0cc10713 addi a4,sp,204 -800019b0: 00200613 li a2,2 -800019b4: 000a8593 mv a1,s5 -800019b8: 000d0513 mv a0,s10 -800019bc: 0bc12823 sw t3,176(sp) -800019c0: 05c12023 sw t3,64(sp) -800019c4: 0bd12a23 sw t4,180(sp) -800019c8: 03d12223 sw t4,36(sp) -800019cc: 0be12c23 sw t5,184(sp) -800019d0: 03e12023 sw t5,32(sp) -800019d4: 0a612e23 sw t1,188(sp) -800019d8: 00612e23 sw t1,28(sp) -800019dc: 4c9040ef jal ra,800066a4 <_ldtoa_r> -800019e0: 01c12303 lw t1,28(sp) -800019e4: 02012f03 lw t5,32(sp) -800019e8: 02412e83 lw t4,36(sp) -800019ec: 04012e03 lw t3,64(sp) -800019f0: 05012883 lw a7,80(sp) -800019f4: 00050b13 mv s6,a0 -800019f8: 01250933 add s2,a0,s2 -800019fc: 0a010c93 addi s9,sp,160 -80001a00: 000c8593 mv a1,s9 -80001a04: 000a8513 mv a0,s5 -80001a08: 01112e23 sw a7,28(sp) -80001a0c: 0bc12823 sw t3,176(sp) -80001a10: 0bd12a23 sw t4,180(sp) -80001a14: 0be12c23 sw t5,184(sp) -80001a18: 0a612e23 sw t1,188(sp) -80001a1c: 0a012023 sw zero,160(sp) -80001a20: 0a012223 sw zero,164(sp) -80001a24: 0a012423 sw zero,168(sp) -80001a28: 0a012623 sw zero,172(sp) -80001a2c: 7810f0ef jal ra,800119ac <__eqtf2> -80001a30: 01c12883 lw a7,28(sp) -80001a34: 00090713 mv a4,s2 -80001a38: 02050263 beqz a0,80001a5c <_vfprintf_r+0x644> -80001a3c: 0dc12703 lw a4,220(sp) -80001a40: 01277e63 bgeu a4,s2,80001a5c <_vfprintf_r+0x644> -80001a44: 03000693 li a3,48 -80001a48: 00170793 addi a5,a4,1 -80001a4c: 0cf12e23 sw a5,220(sp) -80001a50: 00d70023 sb a3,0(a4) -80001a54: 0dc12703 lw a4,220(sp) -80001a58: ff2768e3 bltu a4,s2,80001a48 <_vfprintf_r+0x630> -80001a5c: 416707b3 sub a5,a4,s6 -80001a60: 02f12023 sw a5,32(sp) -80001a64: 0cc12703 lw a4,204(sp) -80001a68: 04700793 li a5,71 -80001a6c: 00e12e23 sw a4,28(sp) -80001a70: 04412703 lw a4,68(sp) -80001a74: 00f71463 bne a4,a5,80001a7c <_vfprintf_r+0x664> -80001a78: 43d0106f j 800036b4 <_vfprintf_r+0x229c> -80001a7c: 04412703 lw a4,68(sp) -80001a80: 04600793 li a5,70 -80001a84: 00f71463 bne a4,a5,80001a8c <_vfprintf_r+0x674> -80001a88: 67d0106f j 80003904 <_vfprintf_r+0x24ec> -80001a8c: 01c12783 lw a5,28(sp) -80001a90: 04412703 lw a4,68(sp) -80001a94: 04100593 li a1,65 -80001a98: fff78793 addi a5,a5,-1 -80001a9c: 0cf12623 sw a5,204(sp) -80001aa0: 0ff4f693 andi a3,s1,255 -80001aa4: 00000613 li a2,0 -80001aa8: 00b71863 bne a4,a1,80001ab8 <_vfprintf_r+0x6a0> -80001aac: 00f68693 addi a3,a3,15 -80001ab0: 0ff6f693 andi a3,a3,255 -80001ab4: 00100613 li a2,1 -80001ab8: 0cd10a23 sb a3,212(sp) -80001abc: 02b00693 li a3,43 -80001ac0: 0007da63 bgez a5,80001ad4 <_vfprintf_r+0x6bc> -80001ac4: 01c12703 lw a4,28(sp) -80001ac8: 00100793 li a5,1 -80001acc: 02d00693 li a3,45 -80001ad0: 40e787b3 sub a5,a5,a4 -80001ad4: 0cd10aa3 sb a3,213(sp) -80001ad8: 00900693 li a3,9 -80001adc: 00f6c463 blt a3,a5,80001ae4 <_vfprintf_r+0x6cc> -80001ae0: 28c0206f j 80003d6c <_vfprintf_r+0x2954> -80001ae4: 0e310813 addi a6,sp,227 -80001ae8: 00080513 mv a0,a6 -80001aec: 00a00613 li a2,10 -80001af0: 06300e13 li t3,99 -80001af4: 02c7e733 rem a4,a5,a2 -80001af8: 00050593 mv a1,a0 -80001afc: 00078693 mv a3,a5 -80001b00: fff50513 addi a0,a0,-1 -80001b04: 03070713 addi a4,a4,48 -80001b08: fee58fa3 sb a4,-1(a1) -80001b0c: 02c7c7b3 div a5,a5,a2 -80001b10: fede42e3 blt t3,a3,80001af4 <_vfprintf_r+0x6dc> -80001b14: 03078793 addi a5,a5,48 -80001b18: 0ff7f613 andi a2,a5,255 -80001b1c: fec50fa3 sb a2,-1(a0) -80001b20: ffe58793 addi a5,a1,-2 -80001b24: 0107e463 bltu a5,a6,80001b2c <_vfprintf_r+0x714> -80001b28: 3740206f j 80003e9c <_vfprintf_r+0x2a84> -80001b2c: 0d610693 addi a3,sp,214 -80001b30: 0080006f j 80001b38 <_vfprintf_r+0x720> -80001b34: 0007c603 lbu a2,0(a5) -80001b38: 00c68023 sb a2,0(a3) -80001b3c: 00178793 addi a5,a5,1 +80001354 <_vfprintf_r>: +80001354: e1010113 addi sp,sp,-496 +80001358: 1e112623 sw ra,492(sp) +8000135c: 1f212023 sw s2,480(sp) +80001360: 1d812423 sw s8,456(sp) +80001364: 1da12023 sw s10,448(sp) +80001368: 00058c13 mv s8,a1 +8000136c: 00060913 mv s2,a2 +80001370: 00d12a23 sw a3,20(sp) +80001374: 1e812423 sw s0,488(sp) +80001378: 1e912223 sw s1,484(sp) +8000137c: 1d312e23 sw s3,476(sp) +80001380: 1d412c23 sw s4,472(sp) +80001384: 1d512a23 sw s5,468(sp) +80001388: 1d612823 sw s6,464(sp) +8000138c: 1d712623 sw s7,460(sp) +80001390: 1d912223 sw s9,452(sp) +80001394: 1bb12e23 sw s11,444(sp) +80001398: 00050d13 mv s10,a0 +8000139c: 548060ef jal ra,800078e4 <_localeconv_r> +800013a0: 00052783 lw a5,0(a0) +800013a4: 00078513 mv a0,a5 +800013a8: 02f12823 sw a5,48(sp) +800013ac: 4f0080ef jal ra,8000989c +800013b0: 02a12623 sw a0,44(sp) +800013b4: 0e012823 sw zero,240(sp) +800013b8: 0e012a23 sw zero,244(sp) +800013bc: 0e012c23 sw zero,248(sp) +800013c0: 0e012e23 sw zero,252(sp) +800013c4: 000d0663 beqz s10,800013d0 <_vfprintf_r+0x7c> +800013c8: 038d2703 lw a4,56(s10) +800013cc: 0a0708e3 beqz a4,80001c7c <_vfprintf_r+0x928> +800013d0: 00cc1683 lh a3,12(s8) +800013d4: 01069713 slli a4,a3,0x10 +800013d8: 01269793 slli a5,a3,0x12 +800013dc: 01075713 srli a4,a4,0x10 +800013e0: 0207ca63 bltz a5,80001414 <_vfprintf_r+0xc0> +800013e4: 00002737 lui a4,0x2 +800013e8: 064c2603 lw a2,100(s8) +800013ec: 00e6e733 or a4,a3,a4 +800013f0: 01071713 slli a4,a4,0x10 +800013f4: ffffe6b7 lui a3,0xffffe +800013f8: 41075713 srai a4,a4,0x10 +800013fc: fff68693 addi a3,a3,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> +80001400: 00d676b3 and a3,a2,a3 +80001404: 00ec1623 sh a4,12(s8) +80001408: 01071713 slli a4,a4,0x10 +8000140c: 06dc2223 sw a3,100(s8) +80001410: 01075713 srli a4,a4,0x10 +80001414: 00877693 andi a3,a4,8 +80001418: 2e068863 beqz a3,80001708 <_vfprintf_r+0x3b4> +8000141c: 010c2683 lw a3,16(s8) +80001420: 2e068463 beqz a3,80001708 <_vfprintf_r+0x3b4> +80001424: 01a77713 andi a4,a4,26 +80001428: 00a00693 li a3,10 +8000142c: 30d70063 beq a4,a3,8000172c <_vfprintf_r+0x3d8> +80001430: 10c10793 addi a5,sp,268 +80001434: 80015737 lui a4,0x80015 +80001438: 0ef12223 sw a5,228(sp) +8000143c: 00078893 mv a7,a5 +80001440: bd870793 addi a5,a4,-1064 # 80014bd8 <__BSS_END__+0xffffdf9c> +80001444: 80015737 lui a4,0x80015 +80001448: 00f12c23 sw a5,24(sp) +8000144c: 00090b13 mv s6,s2 +80001450: d5470793 addi a5,a4,-684 # 80014d54 <__BSS_END__+0xffffe118> +80001454: 00f12423 sw a5,8(sp) +80001458: 000b4783 lbu a5,0(s6) +8000145c: 0e012623 sw zero,236(sp) +80001460: 0e012423 sw zero,232(sp) +80001464: 02012023 sw zero,32(sp) +80001468: 02012a23 sw zero,52(sp) +8000146c: 02012c23 sw zero,56(sp) +80001470: 02012e23 sw zero,60(sp) +80001474: 04012423 sw zero,72(sp) +80001478: 04012623 sw zero,76(sp) +8000147c: 00012623 sw zero,12(sp) +80001480: 22078663 beqz a5,800016ac <_vfprintf_r+0x358> +80001484: 000b0413 mv s0,s6 +80001488: 02500693 li a3,37 +8000148c: 30d78a63 beq a5,a3,800017a0 <_vfprintf_r+0x44c> +80001490: 00144783 lbu a5,1(s0) +80001494: 00140413 addi s0,s0,1 +80001498: fe079ae3 bnez a5,8000148c <_vfprintf_r+0x138> +8000149c: 416404b3 sub s1,s0,s6 +800014a0: 21640663 beq s0,s6,800016ac <_vfprintf_r+0x358> +800014a4: 0ec12683 lw a3,236(sp) +800014a8: 0e812783 lw a5,232(sp) +800014ac: 0168a023 sw s6,0(a7) +800014b0: 009686b3 add a3,a3,s1 +800014b4: 00178793 addi a5,a5,1 +800014b8: 0098a223 sw s1,4(a7) +800014bc: 0ed12623 sw a3,236(sp) +800014c0: 0ef12423 sw a5,232(sp) +800014c4: 00700693 li a3,7 +800014c8: 00888893 addi a7,a7,8 +800014cc: 2ef6c263 blt a3,a5,800017b0 <_vfprintf_r+0x45c> +800014d0: 00c12703 lw a4,12(sp) +800014d4: 00044783 lbu a5,0(s0) +800014d8: 00970733 add a4,a4,s1 +800014dc: 00e12623 sw a4,12(sp) +800014e0: 1c078663 beqz a5,800016ac <_vfprintf_r+0x358> +800014e4: 00144483 lbu s1,1(s0) +800014e8: 0c0103a3 sb zero,199(sp) +800014ec: 00140413 addi s0,s0,1 +800014f0: fff00d93 li s11,-1 +800014f4: 00000993 li s3,0 +800014f8: 00000a13 li s4,0 +800014fc: 05a00913 li s2,90 +80001500: 00900a93 li s5,9 +80001504: 02a00b93 li s7,42 +80001508: 00088c93 mv s9,a7 +8000150c: 00140413 addi s0,s0,1 +80001510: fe048793 addi a5,s1,-32 +80001514: 04f96463 bltu s2,a5,8000155c <_vfprintf_r+0x208> +80001518: 01812703 lw a4,24(sp) +8000151c: 00279793 slli a5,a5,0x2 +80001520: 00e787b3 add a5,a5,a4 +80001524: 0007a783 lw a5,0(a5) +80001528: 00078067 jr a5 +8000152c: 00000993 li s3,0 +80001530: fd048693 addi a3,s1,-48 +80001534: 00044483 lbu s1,0(s0) +80001538: 00299793 slli a5,s3,0x2 +8000153c: 013787b3 add a5,a5,s3 +80001540: 00179793 slli a5,a5,0x1 +80001544: 00f689b3 add s3,a3,a5 +80001548: fd048693 addi a3,s1,-48 +8000154c: 00140413 addi s0,s0,1 +80001550: fedaf2e3 bgeu s5,a3,80001534 <_vfprintf_r+0x1e0> +80001554: fe048793 addi a5,s1,-32 +80001558: fcf970e3 bgeu s2,a5,80001518 <_vfprintf_r+0x1c4> +8000155c: 000c8893 mv a7,s9 +80001560: 14048663 beqz s1,800016ac <_vfprintf_r+0x358> +80001564: 14910623 sb s1,332(sp) +80001568: 0c0103a3 sb zero,199(sp) +8000156c: 00100a93 li s5,1 +80001570: 00100c93 li s9,1 +80001574: 14c10b13 addi s6,sp,332 +80001578: 00012823 sw zero,16(sp) +8000157c: 00000d93 li s11,0 +80001580: 02012423 sw zero,40(sp) +80001584: 02012223 sw zero,36(sp) +80001588: 00012e23 sw zero,28(sp) +8000158c: 002a7b93 andi s7,s4,2 +80001590: 000b8463 beqz s7,80001598 <_vfprintf_r+0x244> +80001594: 002a8a93 addi s5,s5,2 +80001598: 084a7913 andi s2,s4,132 +8000159c: 0ec12783 lw a5,236(sp) +800015a0: 00091663 bnez s2,800015ac <_vfprintf_r+0x258> +800015a4: 41598833 sub a6,s3,s5 +800015a8: 710046e3 bgtz a6,800024b4 <_vfprintf_r+0x1160> +800015ac: 0c714683 lbu a3,199(sp) +800015b0: 02068a63 beqz a3,800015e4 <_vfprintf_r+0x290> +800015b4: 0e812683 lw a3,232(sp) +800015b8: 0c710613 addi a2,sp,199 +800015bc: 00c8a023 sw a2,0(a7) +800015c0: 00178793 addi a5,a5,1 +800015c4: 00100613 li a2,1 +800015c8: 00168693 addi a3,a3,1 +800015cc: 00c8a223 sw a2,4(a7) +800015d0: 0ef12623 sw a5,236(sp) +800015d4: 0ed12423 sw a3,232(sp) +800015d8: 00700613 li a2,7 +800015dc: 00888893 addi a7,a7,8 +800015e0: 52d64263 blt a2,a3,80001b04 <_vfprintf_r+0x7b0> +800015e4: 020b8c63 beqz s7,8000161c <_vfprintf_r+0x2c8> +800015e8: 0e812683 lw a3,232(sp) +800015ec: 0c810613 addi a2,sp,200 +800015f0: 00c8a023 sw a2,0(a7) +800015f4: 00278793 addi a5,a5,2 +800015f8: 00200613 li a2,2 +800015fc: 00168693 addi a3,a3,1 +80001600: 00c8a223 sw a2,4(a7) +80001604: 0ef12623 sw a5,236(sp) +80001608: 0ed12423 sw a3,232(sp) +8000160c: 00700613 li a2,7 +80001610: 00888893 addi a7,a7,8 +80001614: 00d65463 bge a2,a3,8000161c <_vfprintf_r+0x2c8> +80001618: 78d0006f j 800025a4 <_vfprintf_r+0x1250> +8000161c: 08000693 li a3,128 +80001620: 3cd90ee3 beq s2,a3,800021fc <_vfprintf_r+0xea8> +80001624: 419d8db3 sub s11,s11,s9 +80001628: 49b04ae3 bgtz s11,800022bc <_vfprintf_r+0xf68> +8000162c: 100a7693 andi a3,s4,256 +80001630: 280698e3 bnez a3,800020c0 <_vfprintf_r+0xd6c> +80001634: 0e812703 lw a4,232(sp) +80001638: 019787b3 add a5,a5,s9 +8000163c: 0168a023 sw s6,0(a7) +80001640: 00170713 addi a4,a4,1 +80001644: 0198a223 sw s9,4(a7) +80001648: 0ef12623 sw a5,236(sp) +8000164c: 0ee12423 sw a4,232(sp) +80001650: 00700693 li a3,7 +80001654: 54e6c863 blt a3,a4,80001ba4 <_vfprintf_r+0x850> +80001658: 00888893 addi a7,a7,8 +8000165c: 004a7a13 andi s4,s4,4 +80001660: 000a0663 beqz s4,8000166c <_vfprintf_r+0x318> +80001664: 415984b3 sub s1,s3,s5 +80001668: 54904e63 bgtz s1,80001bc4 <_vfprintf_r+0x870> +8000166c: 0159d463 bge s3,s5,80001674 <_vfprintf_r+0x320> +80001670: 000a8993 mv s3,s5 +80001674: 00c12703 lw a4,12(sp) +80001678: 01370733 add a4,a4,s3 +8000167c: 00e12623 sw a4,12(sp) +80001680: 4e0798e3 bnez a5,80002370 <_vfprintf_r+0x101c> +80001684: 01012783 lw a5,16(sp) +80001688: 0e012423 sw zero,232(sp) +8000168c: 00078863 beqz a5,8000169c <_vfprintf_r+0x348> +80001690: 01012583 lw a1,16(sp) +80001694: 000d0513 mv a0,s10 +80001698: 278030ef jal ra,80004910 <_free_r> +8000169c: 10c10893 addi a7,sp,268 +800016a0: 00040b13 mv s6,s0 +800016a4: 000b4783 lbu a5,0(s6) +800016a8: dc079ee3 bnez a5,80001484 <_vfprintf_r+0x130> +800016ac: 0ec12783 lw a5,236(sp) +800016b0: 00078463 beqz a5,800016b8 <_vfprintf_r+0x364> +800016b4: 3250106f j 800031d8 <_vfprintf_r+0x1e84> +800016b8: 00cc5783 lhu a5,12(s8) +800016bc: 0407f793 andi a5,a5,64 +800016c0: 00078463 beqz a5,800016c8 <_vfprintf_r+0x374> +800016c4: 2300206f j 800038f4 <_vfprintf_r+0x25a0> +800016c8: 1ec12083 lw ra,492(sp) +800016cc: 1e812403 lw s0,488(sp) +800016d0: 00c12503 lw a0,12(sp) +800016d4: 1e412483 lw s1,484(sp) +800016d8: 1e012903 lw s2,480(sp) +800016dc: 1dc12983 lw s3,476(sp) +800016e0: 1d812a03 lw s4,472(sp) +800016e4: 1d412a83 lw s5,468(sp) +800016e8: 1d012b03 lw s6,464(sp) +800016ec: 1cc12b83 lw s7,460(sp) +800016f0: 1c812c03 lw s8,456(sp) +800016f4: 1c412c83 lw s9,452(sp) +800016f8: 1c012d03 lw s10,448(sp) +800016fc: 1bc12d83 lw s11,444(sp) +80001700: 1f010113 addi sp,sp,496 +80001704: 00008067 ret +80001708: 000c0593 mv a1,s8 +8000170c: 000d0513 mv a0,s10 +80001710: 7ac020ef jal ra,80003ebc <__swsetup_r> +80001714: 00050463 beqz a0,8000171c <_vfprintf_r+0x3c8> +80001718: 1dc0206f j 800038f4 <_vfprintf_r+0x25a0> +8000171c: 00cc5703 lhu a4,12(s8) +80001720: 00a00693 li a3,10 +80001724: 01a77713 andi a4,a4,26 +80001728: d0d714e3 bne a4,a3,80001430 <_vfprintf_r+0xdc> +8000172c: 00ec1703 lh a4,14(s8) +80001730: d00740e3 bltz a4,80001430 <_vfprintf_r+0xdc> +80001734: 01412683 lw a3,20(sp) +80001738: 00090613 mv a2,s2 +8000173c: 000c0593 mv a1,s8 +80001740: 000d0513 mv a0,s10 +80001744: 6b8020ef jal ra,80003dfc <__sbprintf> +80001748: 00a12623 sw a0,12(sp) +8000174c: f7dff06f j 800016c8 <_vfprintf_r+0x374> +80001750: 000d0513 mv a0,s10 +80001754: 190060ef jal ra,800078e4 <_localeconv_r> +80001758: 00452783 lw a5,4(a0) +8000175c: 00078513 mv a0,a5 +80001760: 04f12623 sw a5,76(sp) +80001764: 138080ef jal ra,8000989c +80001768: 00050793 mv a5,a0 +8000176c: 000d0513 mv a0,s10 +80001770: 00078493 mv s1,a5 +80001774: 04f12423 sw a5,72(sp) +80001778: 16c060ef jal ra,800078e4 <_localeconv_r> +8000177c: 00852783 lw a5,8(a0) +80001780: 02f12e23 sw a5,60(sp) +80001784: 00048463 beqz s1,8000178c <_vfprintf_r+0x438> +80001788: 12c0106f j 800028b4 <_vfprintf_r+0x1560> +8000178c: 00044483 lbu s1,0(s0) +80001790: d7dff06f j 8000150c <_vfprintf_r+0x1b8> +80001794: 00044483 lbu s1,0(s0) +80001798: 020a6a13 ori s4,s4,32 +8000179c: d71ff06f j 8000150c <_vfprintf_r+0x1b8> +800017a0: 416404b3 sub s1,s0,s6 +800017a4: d16410e3 bne s0,s6,800014a4 <_vfprintf_r+0x150> +800017a8: 00044783 lbu a5,0(s0) +800017ac: d35ff06f j 800014e0 <_vfprintf_r+0x18c> +800017b0: 0e410613 addi a2,sp,228 +800017b4: 000c0593 mv a1,s8 +800017b8: 000d0513 mv a0,s10 +800017bc: 5190a0ef jal ra,8000c4d4 <__sprint_r> +800017c0: ee051ce3 bnez a0,800016b8 <_vfprintf_r+0x364> +800017c4: 10c10893 addi a7,sp,268 +800017c8: d09ff06f j 800014d0 <_vfprintf_r+0x17c> +800017cc: 008a7793 andi a5,s4,8 +800017d0: 000c8893 mv a7,s9 +800017d4: 00078463 beqz a5,800017dc <_vfprintf_r+0x488> +800017d8: 12c0106f j 80002904 <_vfprintf_r+0x15b0> +800017dc: 01412783 lw a5,20(sp) +800017e0: 0b010513 addi a0,sp,176 +800017e4: 01912823 sw s9,16(sp) +800017e8: 00778793 addi a5,a5,7 +800017ec: ff87f793 andi a5,a5,-8 +800017f0: 0007a583 lw a1,0(a5) +800017f4: 0047a603 lw a2,4(a5) +800017f8: 00878793 addi a5,a5,8 +800017fc: 00f12a23 sw a5,20(sp) +80001800: 3c5120ef jal ra,800143c4 <__extenddftf2> +80001804: 0b012783 lw a5,176(sp) +80001808: 01012883 lw a7,16(sp) +8000180c: 0ef12823 sw a5,240(sp) +80001810: 0b412783 lw a5,180(sp) +80001814: 0ef12a23 sw a5,244(sp) +80001818: 0b812783 lw a5,184(sp) +8000181c: 0ef12c23 sw a5,248(sp) +80001820: 0bc12783 lw a5,188(sp) +80001824: 0ef12e23 sw a5,252(sp) +80001828: 0f010513 addi a0,sp,240 +8000182c: 01112823 sw a7,16(sp) +80001830: 048060ef jal ra,80007878 <_ldcheck> +80001834: 0ca12623 sw a0,204(sp) +80001838: 00200793 li a5,2 +8000183c: 01012883 lw a7,16(sp) +80001840: 00f51463 bne a0,a5,80001848 <_vfprintf_r+0x4f4> +80001844: 4fc0106f j 80002d40 <_vfprintf_r+0x19ec> +80001848: 00100793 li a5,1 +8000184c: 00f51463 bne a0,a5,80001854 <_vfprintf_r+0x500> +80001850: 6440106f j 80002e94 <_vfprintf_r+0x1b40> +80001854: 06100793 li a5,97 +80001858: 00f49463 bne s1,a5,80001860 <_vfprintf_r+0x50c> +8000185c: 1c40206f j 80003a20 <_vfprintf_r+0x26cc> +80001860: 04100793 li a5,65 +80001864: 00f49463 bne s1,a5,8000186c <_vfprintf_r+0x518> +80001868: 1910106f j 800031f8 <_vfprintf_r+0x1ea4> +8000186c: fdf4fb93 andi s7,s1,-33 +80001870: fff00793 li a5,-1 +80001874: 05712223 sw s7,68(sp) +80001878: 00fd9463 bne s11,a5,80001880 <_vfprintf_r+0x52c> +8000187c: 2800206f j 80003afc <_vfprintf_r+0x27a8> +80001880: 04700793 li a5,71 +80001884: 00fb9463 bne s7,a5,8000188c <_vfprintf_r+0x538> +80001888: 1e00206f j 80003a68 <_vfprintf_r+0x2714> +8000188c: 0fc12303 lw t1,252(sp) +80001890: 03412423 sw s4,40(sp) +80001894: 0f012e03 lw t3,240(sp) +80001898: 0f412e83 lw t4,244(sp) +8000189c: 0f812f03 lw t5,248(sp) +800018a0: 100a6793 ori a5,s4,256 +800018a4: 00035463 bgez t1,800018ac <_vfprintf_r+0x558> +800018a8: 3e00206f j 80003c88 <_vfprintf_r+0x2934> +800018ac: 04012c23 sw zero,88(sp) +800018b0: 00078a13 mv s4,a5 +800018b4: 00012823 sw zero,16(sp) +800018b8: 04600793 li a5,70 +800018bc: 00fb9463 bne s7,a5,800018c4 <_vfprintf_r+0x570> +800018c0: 6990106f j 80003758 <_vfprintf_r+0x2404> +800018c4: 04500793 li a5,69 +800018c8: 05112823 sw a7,80(sp) +800018cc: 00fb8463 beq s7,a5,800018d4 <_vfprintf_r+0x580> +800018d0: 6090106f j 800036d8 <_vfprintf_r+0x2384> +800018d4: 001d8913 addi s2,s11,1 +800018d8: 0b010a93 addi s5,sp,176 +800018dc: 00090693 mv a3,s2 +800018e0: 0dc10813 addi a6,sp,220 +800018e4: 0d010793 addi a5,sp,208 +800018e8: 0cc10713 addi a4,sp,204 +800018ec: 00200613 li a2,2 +800018f0: 000a8593 mv a1,s5 +800018f4: 000d0513 mv a0,s10 +800018f8: 0bc12823 sw t3,176(sp) +800018fc: 05c12023 sw t3,64(sp) +80001900: 0bd12a23 sw t4,180(sp) +80001904: 03d12223 sw t4,36(sp) +80001908: 0be12c23 sw t5,184(sp) +8000190c: 03e12023 sw t5,32(sp) +80001910: 0a612e23 sw t1,188(sp) +80001914: 00612e23 sw t1,28(sp) +80001918: 4c9040ef jal ra,800065e0 <_ldtoa_r> +8000191c: 01c12303 lw t1,28(sp) +80001920: 02012f03 lw t5,32(sp) +80001924: 02412e83 lw t4,36(sp) +80001928: 04012e03 lw t3,64(sp) +8000192c: 05012883 lw a7,80(sp) +80001930: 00050b13 mv s6,a0 +80001934: 01250933 add s2,a0,s2 +80001938: 0a010c93 addi s9,sp,160 +8000193c: 000c8593 mv a1,s9 +80001940: 000a8513 mv a0,s5 +80001944: 01112e23 sw a7,28(sp) +80001948: 0bc12823 sw t3,176(sp) +8000194c: 0bd12a23 sw t4,180(sp) +80001950: 0be12c23 sw t5,184(sp) +80001954: 0a612e23 sw t1,188(sp) +80001958: 0a012023 sw zero,160(sp) +8000195c: 0a012223 sw zero,164(sp) +80001960: 0a012423 sw zero,168(sp) +80001964: 0a012623 sw zero,172(sp) +80001968: 7810f0ef jal ra,800118e8 <__eqtf2> +8000196c: 01c12883 lw a7,28(sp) +80001970: 00090713 mv a4,s2 +80001974: 02050263 beqz a0,80001998 <_vfprintf_r+0x644> +80001978: 0dc12703 lw a4,220(sp) +8000197c: 01277e63 bgeu a4,s2,80001998 <_vfprintf_r+0x644> +80001980: 03000693 li a3,48 +80001984: 00170793 addi a5,a4,1 +80001988: 0cf12e23 sw a5,220(sp) +8000198c: 00d70023 sb a3,0(a4) +80001990: 0dc12703 lw a4,220(sp) +80001994: ff2768e3 bltu a4,s2,80001984 <_vfprintf_r+0x630> +80001998: 416707b3 sub a5,a4,s6 +8000199c: 02f12023 sw a5,32(sp) +800019a0: 0cc12703 lw a4,204(sp) +800019a4: 04700793 li a5,71 +800019a8: 00e12e23 sw a4,28(sp) +800019ac: 04412703 lw a4,68(sp) +800019b0: 00f71463 bne a4,a5,800019b8 <_vfprintf_r+0x664> +800019b4: 43d0106f j 800035f0 <_vfprintf_r+0x229c> +800019b8: 04412703 lw a4,68(sp) +800019bc: 04600793 li a5,70 +800019c0: 00f71463 bne a4,a5,800019c8 <_vfprintf_r+0x674> +800019c4: 67d0106f j 80003840 <_vfprintf_r+0x24ec> +800019c8: 01c12783 lw a5,28(sp) +800019cc: 04412703 lw a4,68(sp) +800019d0: 04100593 li a1,65 +800019d4: fff78793 addi a5,a5,-1 +800019d8: 0cf12623 sw a5,204(sp) +800019dc: 0ff4f693 andi a3,s1,255 +800019e0: 00000613 li a2,0 +800019e4: 00b71863 bne a4,a1,800019f4 <_vfprintf_r+0x6a0> +800019e8: 00f68693 addi a3,a3,15 +800019ec: 0ff6f693 andi a3,a3,255 +800019f0: 00100613 li a2,1 +800019f4: 0cd10a23 sb a3,212(sp) +800019f8: 02b00693 li a3,43 +800019fc: 0007da63 bgez a5,80001a10 <_vfprintf_r+0x6bc> +80001a00: 01c12703 lw a4,28(sp) +80001a04: 00100793 li a5,1 +80001a08: 02d00693 li a3,45 +80001a0c: 40e787b3 sub a5,a5,a4 +80001a10: 0cd10aa3 sb a3,213(sp) +80001a14: 00900693 li a3,9 +80001a18: 00f6c463 blt a3,a5,80001a20 <_vfprintf_r+0x6cc> +80001a1c: 28c0206f j 80003ca8 <_vfprintf_r+0x2954> +80001a20: 0e310813 addi a6,sp,227 +80001a24: 00080513 mv a0,a6 +80001a28: 00a00613 li a2,10 +80001a2c: 06300e13 li t3,99 +80001a30: 02c7e733 rem a4,a5,a2 +80001a34: 00050593 mv a1,a0 +80001a38: 00078693 mv a3,a5 +80001a3c: fff50513 addi a0,a0,-1 +80001a40: 03070713 addi a4,a4,48 +80001a44: fee58fa3 sb a4,-1(a1) +80001a48: 02c7c7b3 div a5,a5,a2 +80001a4c: fede42e3 blt t3,a3,80001a30 <_vfprintf_r+0x6dc> +80001a50: 03078793 addi a5,a5,48 +80001a54: 0ff7f613 andi a2,a5,255 +80001a58: fec50fa3 sb a2,-1(a0) +80001a5c: ffe58793 addi a5,a1,-2 +80001a60: 0107e463 bltu a5,a6,80001a68 <_vfprintf_r+0x714> +80001a64: 3740206f j 80003dd8 <_vfprintf_r+0x2a84> +80001a68: 0d610693 addi a3,sp,214 +80001a6c: 0080006f j 80001a74 <_vfprintf_r+0x720> +80001a70: 0007c603 lbu a2,0(a5) +80001a74: 00c68023 sb a2,0(a3) +80001a78: 00178793 addi a5,a5,1 +80001a7c: 00168693 addi a3,a3,1 +80001a80: ff0798e3 bne a5,a6,80001a70 <_vfprintf_r+0x71c> +80001a84: 0e510793 addi a5,sp,229 +80001a88: 40b787b3 sub a5,a5,a1 +80001a8c: 0d610713 addi a4,sp,214 +80001a90: 00f707b3 add a5,a4,a5 +80001a94: 0d410693 addi a3,sp,212 +80001a98: 40d787b3 sub a5,a5,a3 +80001a9c: 02f12c23 sw a5,56(sp) +80001aa0: 02012703 lw a4,32(sp) +80001aa4: 03812683 lw a3,56(sp) +80001aa8: 00100793 li a5,1 +80001aac: 00d70cb3 add s9,a4,a3 +80001ab0: 00e7c463 blt a5,a4,80001ab8 <_vfprintf_r+0x764> +80001ab4: 2940206f j 80003d48 <_vfprintf_r+0x29f4> +80001ab8: 02c12783 lw a5,44(sp) +80001abc: 00fc8cb3 add s9,s9,a5 +80001ac0: 02812783 lw a5,40(sp) +80001ac4: fffcca93 not s5,s9 +80001ac8: 41fada93 srai s5,s5,0x1f +80001acc: bff7fa13 andi s4,a5,-1025 +80001ad0: 100a6a13 ori s4,s4,256 +80001ad4: 015cfab3 and s5,s9,s5 +80001ad8: 02012423 sw zero,40(sp) +80001adc: 02012223 sw zero,36(sp) +80001ae0: 00012e23 sw zero,28(sp) +80001ae4: 05812783 lw a5,88(sp) +80001ae8: 00079463 bnez a5,80001af0 <_vfprintf_r+0x79c> +80001aec: 3790106f j 80003664 <_vfprintf_r+0x2310> +80001af0: 02d00793 li a5,45 +80001af4: 0cf103a3 sb a5,199(sp) +80001af8: 00000d93 li s11,0 +80001afc: 001a8a93 addi s5,s5,1 +80001b00: a8dff06f j 8000158c <_vfprintf_r+0x238> +80001b04: 0e410613 addi a2,sp,228 +80001b08: 000c0593 mv a1,s8 +80001b0c: 000d0513 mv a0,s10 +80001b10: 1c50a0ef jal ra,8000c4d4 <__sprint_r> +80001b14: 060518e3 bnez a0,80002384 <_vfprintf_r+0x1030> +80001b18: 0ec12783 lw a5,236(sp) +80001b1c: 10c10893 addi a7,sp,268 +80001b20: ac5ff06f j 800015e4 <_vfprintf_r+0x290> +80001b24: 03012683 lw a3,48(sp) +80001b28: 02c12703 lw a4,44(sp) +80001b2c: 00700613 li a2,7 +80001b30: 00d8a023 sw a3,0(a7) +80001b34: 0e812683 lw a3,232(sp) +80001b38: 00f707b3 add a5,a4,a5 +80001b3c: 00e8a223 sw a4,4(a7) 80001b40: 00168693 addi a3,a3,1 -80001b44: ff0798e3 bne a5,a6,80001b34 <_vfprintf_r+0x71c> -80001b48: 0e510793 addi a5,sp,229 -80001b4c: 40b787b3 sub a5,a5,a1 -80001b50: 0d610713 addi a4,sp,214 -80001b54: 00f707b3 add a5,a4,a5 -80001b58: 0d410693 addi a3,sp,212 -80001b5c: 40d787b3 sub a5,a5,a3 -80001b60: 02f12c23 sw a5,56(sp) -80001b64: 02012703 lw a4,32(sp) -80001b68: 03812683 lw a3,56(sp) -80001b6c: 00100793 li a5,1 -80001b70: 00d70cb3 add s9,a4,a3 -80001b74: 00e7c463 blt a5,a4,80001b7c <_vfprintf_r+0x764> -80001b78: 2940206f j 80003e0c <_vfprintf_r+0x29f4> -80001b7c: 02c12783 lw a5,44(sp) -80001b80: 00fc8cb3 add s9,s9,a5 -80001b84: 02812783 lw a5,40(sp) -80001b88: fffcca93 not s5,s9 -80001b8c: 41fada93 srai s5,s5,0x1f -80001b90: bff7fa13 andi s4,a5,-1025 -80001b94: 100a6a13 ori s4,s4,256 -80001b98: 015cfab3 and s5,s9,s5 -80001b9c: 02012423 sw zero,40(sp) -80001ba0: 02012223 sw zero,36(sp) -80001ba4: 00012e23 sw zero,28(sp) -80001ba8: 05812783 lw a5,88(sp) -80001bac: 00079463 bnez a5,80001bb4 <_vfprintf_r+0x79c> -80001bb0: 3790106f j 80003728 <_vfprintf_r+0x2310> -80001bb4: 02d00793 li a5,45 -80001bb8: 0cf103a3 sb a5,199(sp) -80001bbc: 00000d93 li s11,0 -80001bc0: 001a8a93 addi s5,s5,1 -80001bc4: a8dff06f j 80001650 <_vfprintf_r+0x238> -80001bc8: 0e410613 addi a2,sp,228 -80001bcc: 000c0593 mv a1,s8 -80001bd0: 000d0513 mv a0,s10 -80001bd4: 1c50a0ef jal ra,8000c598 <__sprint_r> -80001bd8: 060518e3 bnez a0,80002448 <_vfprintf_r+0x1030> -80001bdc: 0ec12783 lw a5,236(sp) -80001be0: 10c10893 addi a7,sp,268 -80001be4: ac5ff06f j 800016a8 <_vfprintf_r+0x290> -80001be8: 03012683 lw a3,48(sp) -80001bec: 02c12703 lw a4,44(sp) -80001bf0: 00700613 li a2,7 -80001bf4: 00d8a023 sw a3,0(a7) -80001bf8: 0e812683 lw a3,232(sp) -80001bfc: 00f707b3 add a5,a4,a5 -80001c00: 00e8a223 sw a4,4(a7) -80001c04: 00168693 addi a3,a3,1 -80001c08: 0ef12623 sw a5,236(sp) -80001c0c: 0ed12423 sw a3,232(sp) -80001c10: 00888893 addi a7,a7,8 -80001c14: 02d65463 bge a2,a3,80001c3c <_vfprintf_r+0x824> -80001c18: 0e410613 addi a2,sp,228 -80001c1c: 000c0593 mv a1,s8 -80001c20: 000d0513 mv a0,s10 -80001c24: 1750a0ef jal ra,8000c598 <__sprint_r> -80001c28: 020510e3 bnez a0,80002448 <_vfprintf_r+0x1030> -80001c2c: 0cc12583 lw a1,204(sp) -80001c30: 0ec12783 lw a5,236(sp) -80001c34: 0e812683 lw a3,232(sp) -80001c38: 10c10893 addi a7,sp,268 -80001c3c: 0005d463 bgez a1,80001c44 <_vfprintf_r+0x82c> -80001c40: 5850106f j 800039c4 <_vfprintf_r+0x25ac> -80001c44: 02012703 lw a4,32(sp) -80001c48: 00168693 addi a3,a3,1 -80001c4c: 0168a023 sw s6,0(a7) -80001c50: 00f707b3 add a5,a4,a5 -80001c54: 00e8a223 sw a4,4(a7) -80001c58: 0ef12623 sw a5,236(sp) -80001c5c: 0ed12423 sw a3,232(sp) -80001c60: 00700713 li a4,7 -80001c64: aad75ce3 bge a4,a3,8000171c <_vfprintf_r+0x304> -80001c68: 0e410613 addi a2,sp,228 -80001c6c: 000c0593 mv a1,s8 -80001c70: 000d0513 mv a0,s10 -80001c74: 1250a0ef jal ra,8000c598 <__sprint_r> -80001c78: 7c051863 bnez a0,80002448 <_vfprintf_r+0x1030> -80001c7c: 0ec12783 lw a5,236(sp) -80001c80: 10c10893 addi a7,sp,268 -80001c84: a9dff06f j 80001720 <_vfprintf_r+0x308> -80001c88: 01000693 li a3,16 -80001c8c: 0e812703 lw a4,232(sp) -80001c90: 0096c463 blt a3,s1,80001c98 <_vfprintf_r+0x880> -80001c94: 5190106f j 800039ac <_vfprintf_r+0x2594> -80001c98: 800156b7 lui a3,0x80015 -80001c9c: e1868e93 addi t4,a3,-488 # 80014e18 <__BSS_END__+0xffffe1dc> -80001ca0: 01000913 li s2,16 -80001ca4: 00700a13 li s4,7 -80001ca8: 000e8b13 mv s6,t4 -80001cac: 00c0006f j 80001cb8 <_vfprintf_r+0x8a0> -80001cb0: ff048493 addi s1,s1,-16 -80001cb4: 04995663 bge s2,s1,80001d00 <_vfprintf_r+0x8e8> -80001cb8: 01078793 addi a5,a5,16 -80001cbc: 00170713 addi a4,a4,1 -80001cc0: 0168a023 sw s6,0(a7) -80001cc4: 0128a223 sw s2,4(a7) -80001cc8: 0ef12623 sw a5,236(sp) -80001ccc: 0ee12423 sw a4,232(sp) -80001cd0: 00888893 addi a7,a7,8 -80001cd4: fcea5ee3 bge s4,a4,80001cb0 <_vfprintf_r+0x898> -80001cd8: 0e410613 addi a2,sp,228 -80001cdc: 000c0593 mv a1,s8 -80001ce0: 000d0513 mv a0,s10 -80001ce4: 0b50a0ef jal ra,8000c598 <__sprint_r> -80001ce8: 76051063 bnez a0,80002448 <_vfprintf_r+0x1030> -80001cec: ff048493 addi s1,s1,-16 -80001cf0: 0ec12783 lw a5,236(sp) -80001cf4: 0e812703 lw a4,232(sp) -80001cf8: 10c10893 addi a7,sp,268 -80001cfc: fa994ee3 blt s2,s1,80001cb8 <_vfprintf_r+0x8a0> -80001d00: 000b0e93 mv t4,s6 -80001d04: 009787b3 add a5,a5,s1 -80001d08: 00170713 addi a4,a4,1 -80001d0c: 01d8a023 sw t4,0(a7) -80001d10: 0098a223 sw s1,4(a7) -80001d14: 0ef12623 sw a5,236(sp) -80001d18: 0ee12423 sw a4,232(sp) -80001d1c: 00700693 li a3,7 -80001d20: a0e6d8e3 bge a3,a4,80001730 <_vfprintf_r+0x318> -80001d24: 0e410613 addi a2,sp,228 -80001d28: 000c0593 mv a1,s8 -80001d2c: 000d0513 mv a0,s10 -80001d30: 0690a0ef jal ra,8000c598 <__sprint_r> -80001d34: 70051a63 bnez a0,80002448 <_vfprintf_r+0x1030> -80001d38: 0ec12783 lw a5,236(sp) -80001d3c: 9f5ff06f j 80001730 <_vfprintf_r+0x318> -80001d40: 000d0513 mv a0,s10 -80001d44: 2c5020ef jal ra,80004808 <__sinit> -80001d48: f4cff06f j 80001494 <_vfprintf_r+0x7c> -80001d4c: 01412703 lw a4,20(sp) -80001d50: 000c8893 mv a7,s9 -80001d54: 0c0103a3 sb zero,199(sp) -80001d58: 00072783 lw a5,0(a4) -80001d5c: 00470713 addi a4,a4,4 -80001d60: 00e12a23 sw a4,20(sp) -80001d64: 14f10623 sb a5,332(sp) -80001d68: 00100a93 li s5,1 -80001d6c: 00100c93 li s9,1 -80001d70: 14c10b13 addi s6,sp,332 -80001d74: 8c9ff06f j 8000163c <_vfprintf_r+0x224> -80001d78: 01412783 lw a5,20(sp) -80001d7c: 0c0103a3 sb zero,199(sp) -80001d80: 000c8893 mv a7,s9 -80001d84: 0007ab03 lw s6,0(a5) -80001d88: 00478913 addi s2,a5,4 -80001d8c: 5a0b0ee3 beqz s6,80002b48 <_vfprintf_r+0x1730> -80001d90: fff00793 li a5,-1 -80001d94: 00fd9463 bne s11,a5,80001d9c <_vfprintf_r+0x984> -80001d98: 1000106f j 80002e98 <_vfprintf_r+0x1a80> -80001d9c: 000d8613 mv a2,s11 -80001da0: 00000593 li a1,0 -80001da4: 000b0513 mv a0,s6 -80001da8: 01912a23 sw s9,20(sp) -80001dac: 594060ef jal ra,80008340 -80001db0: 00a12823 sw a0,16(sp) -80001db4: 01412883 lw a7,20(sp) -80001db8: 00051463 bnez a0,80001dc0 <_vfprintf_r+0x9a8> -80001dbc: 31d0106f j 800038d8 <_vfprintf_r+0x24c0> -80001dc0: 01012783 lw a5,16(sp) -80001dc4: 01212a23 sw s2,20(sp) -80001dc8: 00012823 sw zero,16(sp) -80001dcc: 41678cb3 sub s9,a5,s6 -80001dd0: 0c714783 lbu a5,199(sp) -80001dd4: fffcca93 not s5,s9 -80001dd8: 41fada93 srai s5,s5,0x1f -80001ddc: 02012423 sw zero,40(sp) -80001de0: 02012223 sw zero,36(sp) -80001de4: 00012e23 sw zero,28(sp) -80001de8: 015cfab3 and s5,s9,s5 -80001dec: 00000d93 li s11,0 -80001df0: 860780e3 beqz a5,80001650 <_vfprintf_r+0x238> -80001df4: 001a8a93 addi s5,s5,1 -80001df8: 859ff06f j 80001650 <_vfprintf_r+0x238> -80001dfc: 00044483 lbu s1,0(s0) -80001e00: 004a6a13 ori s4,s4,4 -80001e04: fccff06f j 800015d0 <_vfprintf_r+0x1b8> -80001e08: 01412683 lw a3,20(sp) -80001e0c: 020a7793 andi a5,s4,32 -80001e10: 000c8893 mv a7,s9 -80001e14: 0006a703 lw a4,0(a3) -80001e18: 00468693 addi a3,a3,4 -80001e1c: 00d12a23 sw a3,20(sp) -80001e20: 36079ee3 bnez a5,8000299c <_vfprintf_r+0x1584> -80001e24: 010a7793 andi a5,s4,16 -80001e28: 00078463 beqz a5,80001e30 <_vfprintf_r+0xa18> -80001e2c: 05c0106f j 80002e88 <_vfprintf_r+0x1a70> -80001e30: 040a7793 andi a5,s4,64 -80001e34: 00078463 beqz a5,80001e3c <_vfprintf_r+0xa24> -80001e38: 3fc0106f j 80003234 <_vfprintf_r+0x1e1c> -80001e3c: 200a7a13 andi s4,s4,512 -80001e40: 000a1463 bnez s4,80001e48 <_vfprintf_r+0xa30> -80001e44: 0440106f j 80002e88 <_vfprintf_r+0x1a70> -80001e48: 00c12783 lw a5,12(sp) -80001e4c: 00040b13 mv s6,s0 -80001e50: 00f70023 sb a5,0(a4) -80001e54: 915ff06f j 80001768 <_vfprintf_r+0x350> -80001e58: 00044483 lbu s1,0(s0) -80001e5c: 06c00793 li a5,108 -80001e60: 4cf484e3 beq s1,a5,80002b28 <_vfprintf_r+0x1710> -80001e64: 010a6a13 ori s4,s4,16 -80001e68: f68ff06f j 800015d0 <_vfprintf_r+0x1b8> -80001e6c: 01412703 lw a4,20(sp) -80001e70: ffff87b7 lui a5,0xffff8 -80001e74: 8307c793 xori a5,a5,-2000 -80001e78: 0cf11423 sh a5,200(sp) -80001e7c: 00470793 addi a5,a4,4 -80001e80: 00f12a23 sw a5,20(sp) -80001e84: 00072903 lw s2,0(a4) -80001e88: 800157b7 lui a5,0x80015 -80001e8c: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -80001e90: 000c8893 mv a7,s9 -80001e94: 02f12a23 sw a5,52(sp) -80001e98: 00000c93 li s9,0 -80001e9c: 002a6b93 ori s7,s4,2 -80001ea0: 00200793 li a5,2 -80001ea4: 07800493 li s1,120 -80001ea8: 0c0103a3 sb zero,199(sp) -80001eac: fff00713 li a4,-1 -80001eb0: 20ed8663 beq s11,a4,800020bc <_vfprintf_r+0xca4> -80001eb4: 01996733 or a4,s2,s9 -80001eb8: f7fbfa13 andi s4,s7,-129 -80001ebc: 1e071e63 bnez a4,800020b8 <_vfprintf_r+0xca0> -80001ec0: 260d9463 bnez s11,80002128 <_vfprintf_r+0xd10> -80001ec4: 1c079063 bnez a5,80002084 <_vfprintf_r+0xc6c> -80001ec8: 001bfc93 andi s9,s7,1 -80001ecc: 1b010b13 addi s6,sp,432 -80001ed0: 280c9ce3 bnez s9,80002968 <_vfprintf_r+0x1550> -80001ed4: 000c8a93 mv s5,s9 -80001ed8: 01bcd463 bge s9,s11,80001ee0 <_vfprintf_r+0xac8> -80001edc: 000d8a93 mv s5,s11 -80001ee0: 0c714783 lbu a5,199(sp) -80001ee4: 00012823 sw zero,16(sp) -80001ee8: 02012423 sw zero,40(sp) -80001eec: 02012223 sw zero,36(sp) -80001ef0: 00012e23 sw zero,28(sp) -80001ef4: f00790e3 bnez a5,80001df4 <_vfprintf_r+0x9dc> -80001ef8: f58ff06f j 80001650 <_vfprintf_r+0x238> -80001efc: 00044483 lbu s1,0(s0) -80001f00: 06800793 li a5,104 -80001f04: 42f48ae3 beq s1,a5,80002b38 <_vfprintf_r+0x1720> -80001f08: 040a6a13 ori s4,s4,64 -80001f0c: ec4ff06f j 800015d0 <_vfprintf_r+0x1b8> -80001f10: 02b00793 li a5,43 -80001f14: 00044483 lbu s1,0(s0) -80001f18: 0cf103a3 sb a5,199(sp) -80001f1c: eb4ff06f j 800015d0 <_vfprintf_r+0x1b8> -80001f20: 00044483 lbu s1,0(s0) -80001f24: 080a6a13 ori s4,s4,128 -80001f28: ea8ff06f j 800015d0 <_vfprintf_r+0x1b8> -80001f2c: 00044483 lbu s1,0(s0) -80001f30: 00140713 addi a4,s0,1 -80001f34: 01749463 bne s1,s7,80001f3c <_vfprintf_r+0xb24> -80001f38: 7250106f j 80003e5c <_vfprintf_r+0x2a44> -80001f3c: fd048693 addi a3,s1,-48 -80001f40: 00070413 mv s0,a4 -80001f44: 00000d93 li s11,0 -80001f48: e8dae663 bltu s5,a3,800015d4 <_vfprintf_r+0x1bc> -80001f4c: 00044483 lbu s1,0(s0) -80001f50: 002d9793 slli a5,s11,0x2 -80001f54: 01b787b3 add a5,a5,s11 -80001f58: 00179793 slli a5,a5,0x1 -80001f5c: 00d78db3 add s11,a5,a3 -80001f60: fd048693 addi a3,s1,-48 -80001f64: 00140413 addi s0,s0,1 -80001f68: fedaf2e3 bgeu s5,a3,80001f4c <_vfprintf_r+0xb34> -80001f6c: e68ff06f j 800015d4 <_vfprintf_r+0x1bc> -80001f70: 01412783 lw a5,20(sp) -80001f74: 00044483 lbu s1,0(s0) -80001f78: 0007a983 lw s3,0(a5) -80001f7c: 00478793 addi a5,a5,4 -80001f80: 00f12a23 sw a5,20(sp) -80001f84: e409d663 bgez s3,800015d0 <_vfprintf_r+0x1b8> -80001f88: 413009b3 neg s3,s3 -80001f8c: 004a6a13 ori s4,s4,4 -80001f90: e40ff06f j 800015d0 <_vfprintf_r+0x1b8> -80001f94: 00044483 lbu s1,0(s0) -80001f98: 001a6a13 ori s4,s4,1 -80001f9c: e34ff06f j 800015d0 <_vfprintf_r+0x1b8> -80001fa0: 0c714783 lbu a5,199(sp) -80001fa4: 00044483 lbu s1,0(s0) -80001fa8: e2079463 bnez a5,800015d0 <_vfprintf_r+0x1b8> -80001fac: 02000793 li a5,32 -80001fb0: 0cf103a3 sb a5,199(sp) -80001fb4: e1cff06f j 800015d0 <_vfprintf_r+0x1b8> -80001fb8: 000c8893 mv a7,s9 -80001fbc: 010a6a13 ori s4,s4,16 -80001fc0: 020a7793 andi a5,s4,32 -80001fc4: 0c078ee3 beqz a5,800028a0 <_vfprintf_r+0x1488> -80001fc8: 01412783 lw a5,20(sp) -80001fcc: 00778b13 addi s6,a5,7 -80001fd0: ff8b7b13 andi s6,s6,-8 -80001fd4: 000b2903 lw s2,0(s6) -80001fd8: 004b2c83 lw s9,4(s6) -80001fdc: 008b0793 addi a5,s6,8 -80001fe0: 00f12a23 sw a5,20(sp) -80001fe4: bffa7b93 andi s7,s4,-1025 -80001fe8: 00000793 li a5,0 -80001fec: ebdff06f j 80001ea8 <_vfprintf_r+0xa90> -80001ff0: 000c8893 mv a7,s9 -80001ff4: 010a6b93 ori s7,s4,16 -80001ff8: 020bf793 andi a5,s7,32 -80001ffc: 0c0788e3 beqz a5,800028cc <_vfprintf_r+0x14b4> -80002000: 01412783 lw a5,20(sp) -80002004: 00778b13 addi s6,a5,7 -80002008: ff8b7b13 andi s6,s6,-8 -8000200c: 008b0793 addi a5,s6,8 -80002010: 00f12a23 sw a5,20(sp) -80002014: 000b2903 lw s2,0(s6) -80002018: 004b2c83 lw s9,4(s6) -8000201c: 00100793 li a5,1 -80002020: e89ff06f j 80001ea8 <_vfprintf_r+0xa90> -80002024: 00044483 lbu s1,0(s0) -80002028: 008a6a13 ori s4,s4,8 -8000202c: da4ff06f j 800015d0 <_vfprintf_r+0x1b8> -80002030: 000c8893 mv a7,s9 -80002034: 010a6a13 ori s4,s4,16 -80002038: 020a7793 andi a5,s4,32 -8000203c: 0c0780e3 beqz a5,800028fc <_vfprintf_r+0x14e4> -80002040: 01412783 lw a5,20(sp) -80002044: 00778b13 addi s6,a5,7 -80002048: ff8b7b13 andi s6,s6,-8 -8000204c: 004b2783 lw a5,4(s6) -80002050: 000b2903 lw s2,0(s6) -80002054: 008b0713 addi a4,s6,8 -80002058: 00e12a23 sw a4,20(sp) -8000205c: 00078c93 mv s9,a5 -80002060: 0c07c6e3 bltz a5,8000292c <_vfprintf_r+0x1514> -80002064: fff00793 li a5,-1 -80002068: 000a0b93 mv s7,s4 -8000206c: 02fd8463 beq s11,a5,80002094 <_vfprintf_r+0xc7c> -80002070: 019967b3 or a5,s2,s9 -80002074: f7fa7b93 andi s7,s4,-129 -80002078: 00079e63 bnez a5,80002094 <_vfprintf_r+0xc7c> -8000207c: 020d9263 bnez s11,800020a0 <_vfprintf_r+0xc88> -80002080: 000b8a13 mv s4,s7 -80002084: 00000d93 li s11,0 -80002088: 00000c93 li s9,0 -8000208c: 1b010b13 addi s6,sp,432 -80002090: e45ff06f j 80001ed4 <_vfprintf_r+0xabc> -80002094: 3a0c92e3 bnez s9,80002c38 <_vfprintf_r+0x1820> -80002098: 00900793 li a5,9 -8000209c: 3927eee3 bltu a5,s2,80002c38 <_vfprintf_r+0x1820> -800020a0: 03090913 addi s2,s2,48 -800020a4: 1b2107a3 sb s2,431(sp) -800020a8: 000b8a13 mv s4,s7 -800020ac: 00100c93 li s9,1 -800020b0: 1af10b13 addi s6,sp,431 -800020b4: e21ff06f j 80001ed4 <_vfprintf_r+0xabc> -800020b8: 000a0b93 mv s7,s4 -800020bc: 00100713 li a4,1 -800020c0: fce78ae3 beq a5,a4,80002094 <_vfprintf_r+0xc7c> -800020c4: 00200713 li a4,2 -800020c8: 06e78c63 beq a5,a4,80002140 <_vfprintf_r+0xd28> -800020cc: 1b010b13 addi s6,sp,432 -800020d0: 01dc9713 slli a4,s9,0x1d -800020d4: 00797793 andi a5,s2,7 -800020d8: 00395913 srli s2,s2,0x3 -800020dc: 03078793 addi a5,a5,48 -800020e0: 01276933 or s2,a4,s2 -800020e4: 003cdc93 srli s9,s9,0x3 -800020e8: fefb0fa3 sb a5,-1(s6) -800020ec: 01996733 or a4,s2,s9 -800020f0: 000b0613 mv a2,s6 -800020f4: fffb0b13 addi s6,s6,-1 -800020f8: fc071ce3 bnez a4,800020d0 <_vfprintf_r+0xcb8> -800020fc: 001bf693 andi a3,s7,1 -80002100: 06068a63 beqz a3,80002174 <_vfprintf_r+0xd5c> -80002104: 03000693 li a3,48 -80002108: 06d78663 beq a5,a3,80002174 <_vfprintf_r+0xd5c> -8000210c: ffe60613 addi a2,a2,-2 -80002110: 1b010793 addi a5,sp,432 -80002114: fedb0fa3 sb a3,-1(s6) -80002118: 40c78cb3 sub s9,a5,a2 -8000211c: 000b8a13 mv s4,s7 -80002120: 00060b13 mv s6,a2 -80002124: db1ff06f j 80001ed4 <_vfprintf_r+0xabc> -80002128: 00100713 li a4,1 -8000212c: 00e79463 bne a5,a4,80002134 <_vfprintf_r+0xd1c> -80002130: 14d0106f j 80003a7c <_vfprintf_r+0x2664> -80002134: 00200713 li a4,2 -80002138: 000a0b93 mv s7,s4 -8000213c: f8e798e3 bne a5,a4,800020cc <_vfprintf_r+0xcb4> -80002140: 03412683 lw a3,52(sp) -80002144: 1b010b13 addi s6,sp,432 -80002148: 00f97793 andi a5,s2,15 -8000214c: 00f687b3 add a5,a3,a5 -80002150: 0007c703 lbu a4,0(a5) -80002154: 00495913 srli s2,s2,0x4 -80002158: 01cc9793 slli a5,s9,0x1c -8000215c: 0127e933 or s2,a5,s2 -80002160: 004cdc93 srli s9,s9,0x4 -80002164: feeb0fa3 sb a4,-1(s6) -80002168: 019967b3 or a5,s2,s9 -8000216c: fffb0b13 addi s6,s6,-1 -80002170: fc079ce3 bnez a5,80002148 <_vfprintf_r+0xd30> -80002174: 1b010793 addi a5,sp,432 -80002178: 41678cb3 sub s9,a5,s6 -8000217c: 000b8a13 mv s4,s7 -80002180: d55ff06f j 80001ed4 <_vfprintf_r+0xabc> -80002184: 06500693 li a3,101 -80002188: 2c96dc63 bge a3,s1,80002460 <_vfprintf_r+0x1048> -8000218c: 0f012683 lw a3,240(sp) -80002190: 0a010593 addi a1,sp,160 -80002194: 0b010513 addi a0,sp,176 -80002198: 0ad12823 sw a3,176(sp) -8000219c: 0f412683 lw a3,244(sp) -800021a0: 05112223 sw a7,68(sp) -800021a4: 04f12023 sw a5,64(sp) -800021a8: 0ad12a23 sw a3,180(sp) -800021ac: 0f812683 lw a3,248(sp) -800021b0: 0a012023 sw zero,160(sp) -800021b4: 0a012223 sw zero,164(sp) -800021b8: 0ad12c23 sw a3,184(sp) -800021bc: 0fc12683 lw a3,252(sp) -800021c0: 0a012423 sw zero,168(sp) -800021c4: 0a012623 sw zero,172(sp) -800021c8: 0ad12e23 sw a3,188(sp) -800021cc: 7e00f0ef jal ra,800119ac <__eqtf2> -800021d0: 04012783 lw a5,64(sp) -800021d4: 04412883 lw a7,68(sp) -800021d8: 4a051863 bnez a0,80002688 <_vfprintf_r+0x1270> -800021dc: 0e812703 lw a4,232(sp) -800021e0: 800156b7 lui a3,0x80015 -800021e4: ca868693 addi a3,a3,-856 # 80014ca8 <__BSS_END__+0xffffe06c> -800021e8: 00d8a023 sw a3,0(a7) -800021ec: 00178793 addi a5,a5,1 -800021f0: 00100693 li a3,1 -800021f4: 00170713 addi a4,a4,1 -800021f8: 00d8a223 sw a3,4(a7) -800021fc: 0ef12623 sw a5,236(sp) -80002200: 0ee12423 sw a4,232(sp) -80002204: 00700693 li a3,7 -80002208: 00888893 addi a7,a7,8 -8000220c: 3ae6c6e3 blt a3,a4,80002db8 <_vfprintf_r+0x19a0> -80002210: 0cc12703 lw a4,204(sp) -80002214: 02012683 lw a3,32(sp) -80002218: 72d75c63 bge a4,a3,80002950 <_vfprintf_r+0x1538> -8000221c: 03012703 lw a4,48(sp) -80002220: 02c12683 lw a3,44(sp) -80002224: 00888893 addi a7,a7,8 -80002228: fee8ac23 sw a4,-8(a7) -8000222c: 0e812703 lw a4,232(sp) -80002230: 00d787b3 add a5,a5,a3 -80002234: fed8ae23 sw a3,-4(a7) -80002238: 00170713 addi a4,a4,1 -8000223c: 0ef12623 sw a5,236(sp) -80002240: 0ee12423 sw a4,232(sp) -80002244: 00700693 li a3,7 -80002248: 0ce6c0e3 blt a3,a4,80002b08 <_vfprintf_r+0x16f0> -8000224c: 02012703 lw a4,32(sp) -80002250: fff70493 addi s1,a4,-1 -80002254: cc905663 blez s1,80001720 <_vfprintf_r+0x308> -80002258: 01000693 li a3,16 -8000225c: 0e812703 lw a4,232(sp) -80002260: 3696dce3 bge a3,s1,80002dd8 <_vfprintf_r+0x19c0> -80002264: 01000913 li s2,16 -80002268: 00700c93 li s9,7 -8000226c: 00c0006f j 80002278 <_vfprintf_r+0xe60> -80002270: ff048493 addi s1,s1,-16 -80002274: 369952e3 bge s2,s1,80002dd8 <_vfprintf_r+0x19c0> -80002278: 00812683 lw a3,8(sp) -8000227c: 01078793 addi a5,a5,16 -80002280: 00170713 addi a4,a4,1 -80002284: 00d8a023 sw a3,0(a7) -80002288: 0128a223 sw s2,4(a7) -8000228c: 0ef12623 sw a5,236(sp) -80002290: 0ee12423 sw a4,232(sp) +80001b44: 0ef12623 sw a5,236(sp) +80001b48: 0ed12423 sw a3,232(sp) +80001b4c: 00888893 addi a7,a7,8 +80001b50: 02d65463 bge a2,a3,80001b78 <_vfprintf_r+0x824> +80001b54: 0e410613 addi a2,sp,228 +80001b58: 000c0593 mv a1,s8 +80001b5c: 000d0513 mv a0,s10 +80001b60: 1750a0ef jal ra,8000c4d4 <__sprint_r> +80001b64: 020510e3 bnez a0,80002384 <_vfprintf_r+0x1030> +80001b68: 0cc12583 lw a1,204(sp) +80001b6c: 0ec12783 lw a5,236(sp) +80001b70: 0e812683 lw a3,232(sp) +80001b74: 10c10893 addi a7,sp,268 +80001b78: 0005d463 bgez a1,80001b80 <_vfprintf_r+0x82c> +80001b7c: 5850106f j 80003900 <_vfprintf_r+0x25ac> +80001b80: 02012703 lw a4,32(sp) +80001b84: 00168693 addi a3,a3,1 +80001b88: 0168a023 sw s6,0(a7) +80001b8c: 00f707b3 add a5,a4,a5 +80001b90: 00e8a223 sw a4,4(a7) +80001b94: 0ef12623 sw a5,236(sp) +80001b98: 0ed12423 sw a3,232(sp) +80001b9c: 00700713 li a4,7 +80001ba0: aad75ce3 bge a4,a3,80001658 <_vfprintf_r+0x304> +80001ba4: 0e410613 addi a2,sp,228 +80001ba8: 000c0593 mv a1,s8 +80001bac: 000d0513 mv a0,s10 +80001bb0: 1250a0ef jal ra,8000c4d4 <__sprint_r> +80001bb4: 7c051863 bnez a0,80002384 <_vfprintf_r+0x1030> +80001bb8: 0ec12783 lw a5,236(sp) +80001bbc: 10c10893 addi a7,sp,268 +80001bc0: a9dff06f j 8000165c <_vfprintf_r+0x308> +80001bc4: 01000693 li a3,16 +80001bc8: 0e812703 lw a4,232(sp) +80001bcc: 0096c463 blt a3,s1,80001bd4 <_vfprintf_r+0x880> +80001bd0: 5190106f j 800038e8 <_vfprintf_r+0x2594> +80001bd4: 800156b7 lui a3,0x80015 +80001bd8: d4468e93 addi t4,a3,-700 # 80014d44 <__BSS_END__+0xffffe108> +80001bdc: 01000913 li s2,16 +80001be0: 00700a13 li s4,7 +80001be4: 000e8b13 mv s6,t4 +80001be8: 00c0006f j 80001bf4 <_vfprintf_r+0x8a0> +80001bec: ff048493 addi s1,s1,-16 +80001bf0: 04995663 bge s2,s1,80001c3c <_vfprintf_r+0x8e8> +80001bf4: 01078793 addi a5,a5,16 +80001bf8: 00170713 addi a4,a4,1 +80001bfc: 0168a023 sw s6,0(a7) +80001c00: 0128a223 sw s2,4(a7) +80001c04: 0ef12623 sw a5,236(sp) +80001c08: 0ee12423 sw a4,232(sp) +80001c0c: 00888893 addi a7,a7,8 +80001c10: fcea5ee3 bge s4,a4,80001bec <_vfprintf_r+0x898> +80001c14: 0e410613 addi a2,sp,228 +80001c18: 000c0593 mv a1,s8 +80001c1c: 000d0513 mv a0,s10 +80001c20: 0b50a0ef jal ra,8000c4d4 <__sprint_r> +80001c24: 76051063 bnez a0,80002384 <_vfprintf_r+0x1030> +80001c28: ff048493 addi s1,s1,-16 +80001c2c: 0ec12783 lw a5,236(sp) +80001c30: 0e812703 lw a4,232(sp) +80001c34: 10c10893 addi a7,sp,268 +80001c38: fa994ee3 blt s2,s1,80001bf4 <_vfprintf_r+0x8a0> +80001c3c: 000b0e93 mv t4,s6 +80001c40: 009787b3 add a5,a5,s1 +80001c44: 00170713 addi a4,a4,1 +80001c48: 01d8a023 sw t4,0(a7) +80001c4c: 0098a223 sw s1,4(a7) +80001c50: 0ef12623 sw a5,236(sp) +80001c54: 0ee12423 sw a4,232(sp) +80001c58: 00700693 li a3,7 +80001c5c: a0e6d8e3 bge a3,a4,8000166c <_vfprintf_r+0x318> +80001c60: 0e410613 addi a2,sp,228 +80001c64: 000c0593 mv a1,s8 +80001c68: 000d0513 mv a0,s10 +80001c6c: 0690a0ef jal ra,8000c4d4 <__sprint_r> +80001c70: 70051a63 bnez a0,80002384 <_vfprintf_r+0x1030> +80001c74: 0ec12783 lw a5,236(sp) +80001c78: 9f5ff06f j 8000166c <_vfprintf_r+0x318> +80001c7c: 000d0513 mv a0,s10 +80001c80: 2c5020ef jal ra,80004744 <__sinit> +80001c84: f4cff06f j 800013d0 <_vfprintf_r+0x7c> +80001c88: 01412703 lw a4,20(sp) +80001c8c: 000c8893 mv a7,s9 +80001c90: 0c0103a3 sb zero,199(sp) +80001c94: 00072783 lw a5,0(a4) +80001c98: 00470713 addi a4,a4,4 +80001c9c: 00e12a23 sw a4,20(sp) +80001ca0: 14f10623 sb a5,332(sp) +80001ca4: 00100a93 li s5,1 +80001ca8: 00100c93 li s9,1 +80001cac: 14c10b13 addi s6,sp,332 +80001cb0: 8c9ff06f j 80001578 <_vfprintf_r+0x224> +80001cb4: 01412783 lw a5,20(sp) +80001cb8: 0c0103a3 sb zero,199(sp) +80001cbc: 000c8893 mv a7,s9 +80001cc0: 0007ab03 lw s6,0(a5) +80001cc4: 00478913 addi s2,a5,4 +80001cc8: 5a0b0ee3 beqz s6,80002a84 <_vfprintf_r+0x1730> +80001ccc: fff00793 li a5,-1 +80001cd0: 00fd9463 bne s11,a5,80001cd8 <_vfprintf_r+0x984> +80001cd4: 1000106f j 80002dd4 <_vfprintf_r+0x1a80> +80001cd8: 000d8613 mv a2,s11 +80001cdc: 00000593 li a1,0 +80001ce0: 000b0513 mv a0,s6 +80001ce4: 01912a23 sw s9,20(sp) +80001ce8: 594060ef jal ra,8000827c +80001cec: 00a12823 sw a0,16(sp) +80001cf0: 01412883 lw a7,20(sp) +80001cf4: 00051463 bnez a0,80001cfc <_vfprintf_r+0x9a8> +80001cf8: 31d0106f j 80003814 <_vfprintf_r+0x24c0> +80001cfc: 01012783 lw a5,16(sp) +80001d00: 01212a23 sw s2,20(sp) +80001d04: 00012823 sw zero,16(sp) +80001d08: 41678cb3 sub s9,a5,s6 +80001d0c: 0c714783 lbu a5,199(sp) +80001d10: fffcca93 not s5,s9 +80001d14: 41fada93 srai s5,s5,0x1f +80001d18: 02012423 sw zero,40(sp) +80001d1c: 02012223 sw zero,36(sp) +80001d20: 00012e23 sw zero,28(sp) +80001d24: 015cfab3 and s5,s9,s5 +80001d28: 00000d93 li s11,0 +80001d2c: 860780e3 beqz a5,8000158c <_vfprintf_r+0x238> +80001d30: 001a8a93 addi s5,s5,1 +80001d34: 859ff06f j 8000158c <_vfprintf_r+0x238> +80001d38: 00044483 lbu s1,0(s0) +80001d3c: 004a6a13 ori s4,s4,4 +80001d40: fccff06f j 8000150c <_vfprintf_r+0x1b8> +80001d44: 01412683 lw a3,20(sp) +80001d48: 020a7793 andi a5,s4,32 +80001d4c: 000c8893 mv a7,s9 +80001d50: 0006a703 lw a4,0(a3) +80001d54: 00468693 addi a3,a3,4 +80001d58: 00d12a23 sw a3,20(sp) +80001d5c: 36079ee3 bnez a5,800028d8 <_vfprintf_r+0x1584> +80001d60: 010a7793 andi a5,s4,16 +80001d64: 00078463 beqz a5,80001d6c <_vfprintf_r+0xa18> +80001d68: 05c0106f j 80002dc4 <_vfprintf_r+0x1a70> +80001d6c: 040a7793 andi a5,s4,64 +80001d70: 00078463 beqz a5,80001d78 <_vfprintf_r+0xa24> +80001d74: 3fc0106f j 80003170 <_vfprintf_r+0x1e1c> +80001d78: 200a7a13 andi s4,s4,512 +80001d7c: 000a1463 bnez s4,80001d84 <_vfprintf_r+0xa30> +80001d80: 0440106f j 80002dc4 <_vfprintf_r+0x1a70> +80001d84: 00c12783 lw a5,12(sp) +80001d88: 00040b13 mv s6,s0 +80001d8c: 00f70023 sb a5,0(a4) +80001d90: 915ff06f j 800016a4 <_vfprintf_r+0x350> +80001d94: 00044483 lbu s1,0(s0) +80001d98: 06c00793 li a5,108 +80001d9c: 4cf484e3 beq s1,a5,80002a64 <_vfprintf_r+0x1710> +80001da0: 010a6a13 ori s4,s4,16 +80001da4: f68ff06f j 8000150c <_vfprintf_r+0x1b8> +80001da8: 01412703 lw a4,20(sp) +80001dac: ffff87b7 lui a5,0xffff8 +80001db0: 8307c793 xori a5,a5,-2000 +80001db4: 0cf11423 sh a5,200(sp) +80001db8: 00470793 addi a5,a4,4 +80001dbc: 00f12a23 sw a5,20(sp) +80001dc0: 00072903 lw s2,0(a4) +80001dc4: 800157b7 lui a5,0x80015 +80001dc8: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +80001dcc: 000c8893 mv a7,s9 +80001dd0: 02f12a23 sw a5,52(sp) +80001dd4: 00000c93 li s9,0 +80001dd8: 002a6b93 ori s7,s4,2 +80001ddc: 00200793 li a5,2 +80001de0: 07800493 li s1,120 +80001de4: 0c0103a3 sb zero,199(sp) +80001de8: fff00713 li a4,-1 +80001dec: 20ed8663 beq s11,a4,80001ff8 <_vfprintf_r+0xca4> +80001df0: 01996733 or a4,s2,s9 +80001df4: f7fbfa13 andi s4,s7,-129 +80001df8: 1e071e63 bnez a4,80001ff4 <_vfprintf_r+0xca0> +80001dfc: 260d9463 bnez s11,80002064 <_vfprintf_r+0xd10> +80001e00: 1c079063 bnez a5,80001fc0 <_vfprintf_r+0xc6c> +80001e04: 001bfc93 andi s9,s7,1 +80001e08: 1b010b13 addi s6,sp,432 +80001e0c: 280c9ce3 bnez s9,800028a4 <_vfprintf_r+0x1550> +80001e10: 000c8a93 mv s5,s9 +80001e14: 01bcd463 bge s9,s11,80001e1c <_vfprintf_r+0xac8> +80001e18: 000d8a93 mv s5,s11 +80001e1c: 0c714783 lbu a5,199(sp) +80001e20: 00012823 sw zero,16(sp) +80001e24: 02012423 sw zero,40(sp) +80001e28: 02012223 sw zero,36(sp) +80001e2c: 00012e23 sw zero,28(sp) +80001e30: f00790e3 bnez a5,80001d30 <_vfprintf_r+0x9dc> +80001e34: f58ff06f j 8000158c <_vfprintf_r+0x238> +80001e38: 00044483 lbu s1,0(s0) +80001e3c: 06800793 li a5,104 +80001e40: 42f48ae3 beq s1,a5,80002a74 <_vfprintf_r+0x1720> +80001e44: 040a6a13 ori s4,s4,64 +80001e48: ec4ff06f j 8000150c <_vfprintf_r+0x1b8> +80001e4c: 02b00793 li a5,43 +80001e50: 00044483 lbu s1,0(s0) +80001e54: 0cf103a3 sb a5,199(sp) +80001e58: eb4ff06f j 8000150c <_vfprintf_r+0x1b8> +80001e5c: 00044483 lbu s1,0(s0) +80001e60: 080a6a13 ori s4,s4,128 +80001e64: ea8ff06f j 8000150c <_vfprintf_r+0x1b8> +80001e68: 00044483 lbu s1,0(s0) +80001e6c: 00140713 addi a4,s0,1 +80001e70: 01749463 bne s1,s7,80001e78 <_vfprintf_r+0xb24> +80001e74: 7250106f j 80003d98 <_vfprintf_r+0x2a44> +80001e78: fd048693 addi a3,s1,-48 +80001e7c: 00070413 mv s0,a4 +80001e80: 00000d93 li s11,0 +80001e84: e8dae663 bltu s5,a3,80001510 <_vfprintf_r+0x1bc> +80001e88: 00044483 lbu s1,0(s0) +80001e8c: 002d9793 slli a5,s11,0x2 +80001e90: 01b787b3 add a5,a5,s11 +80001e94: 00179793 slli a5,a5,0x1 +80001e98: 00d78db3 add s11,a5,a3 +80001e9c: fd048693 addi a3,s1,-48 +80001ea0: 00140413 addi s0,s0,1 +80001ea4: fedaf2e3 bgeu s5,a3,80001e88 <_vfprintf_r+0xb34> +80001ea8: e68ff06f j 80001510 <_vfprintf_r+0x1bc> +80001eac: 01412783 lw a5,20(sp) +80001eb0: 00044483 lbu s1,0(s0) +80001eb4: 0007a983 lw s3,0(a5) +80001eb8: 00478793 addi a5,a5,4 +80001ebc: 00f12a23 sw a5,20(sp) +80001ec0: e409d663 bgez s3,8000150c <_vfprintf_r+0x1b8> +80001ec4: 413009b3 neg s3,s3 +80001ec8: 004a6a13 ori s4,s4,4 +80001ecc: e40ff06f j 8000150c <_vfprintf_r+0x1b8> +80001ed0: 00044483 lbu s1,0(s0) +80001ed4: 001a6a13 ori s4,s4,1 +80001ed8: e34ff06f j 8000150c <_vfprintf_r+0x1b8> +80001edc: 0c714783 lbu a5,199(sp) +80001ee0: 00044483 lbu s1,0(s0) +80001ee4: e2079463 bnez a5,8000150c <_vfprintf_r+0x1b8> +80001ee8: 02000793 li a5,32 +80001eec: 0cf103a3 sb a5,199(sp) +80001ef0: e1cff06f j 8000150c <_vfprintf_r+0x1b8> +80001ef4: 000c8893 mv a7,s9 +80001ef8: 010a6a13 ori s4,s4,16 +80001efc: 020a7793 andi a5,s4,32 +80001f00: 0c078ee3 beqz a5,800027dc <_vfprintf_r+0x1488> +80001f04: 01412783 lw a5,20(sp) +80001f08: 00778b13 addi s6,a5,7 +80001f0c: ff8b7b13 andi s6,s6,-8 +80001f10: 000b2903 lw s2,0(s6) +80001f14: 004b2c83 lw s9,4(s6) +80001f18: 008b0793 addi a5,s6,8 +80001f1c: 00f12a23 sw a5,20(sp) +80001f20: bffa7b93 andi s7,s4,-1025 +80001f24: 00000793 li a5,0 +80001f28: ebdff06f j 80001de4 <_vfprintf_r+0xa90> +80001f2c: 000c8893 mv a7,s9 +80001f30: 010a6b93 ori s7,s4,16 +80001f34: 020bf793 andi a5,s7,32 +80001f38: 0c0788e3 beqz a5,80002808 <_vfprintf_r+0x14b4> +80001f3c: 01412783 lw a5,20(sp) +80001f40: 00778b13 addi s6,a5,7 +80001f44: ff8b7b13 andi s6,s6,-8 +80001f48: 008b0793 addi a5,s6,8 +80001f4c: 00f12a23 sw a5,20(sp) +80001f50: 000b2903 lw s2,0(s6) +80001f54: 004b2c83 lw s9,4(s6) +80001f58: 00100793 li a5,1 +80001f5c: e89ff06f j 80001de4 <_vfprintf_r+0xa90> +80001f60: 00044483 lbu s1,0(s0) +80001f64: 008a6a13 ori s4,s4,8 +80001f68: da4ff06f j 8000150c <_vfprintf_r+0x1b8> +80001f6c: 000c8893 mv a7,s9 +80001f70: 010a6a13 ori s4,s4,16 +80001f74: 020a7793 andi a5,s4,32 +80001f78: 0c0780e3 beqz a5,80002838 <_vfprintf_r+0x14e4> +80001f7c: 01412783 lw a5,20(sp) +80001f80: 00778b13 addi s6,a5,7 +80001f84: ff8b7b13 andi s6,s6,-8 +80001f88: 004b2783 lw a5,4(s6) +80001f8c: 000b2903 lw s2,0(s6) +80001f90: 008b0713 addi a4,s6,8 +80001f94: 00e12a23 sw a4,20(sp) +80001f98: 00078c93 mv s9,a5 +80001f9c: 0c07c6e3 bltz a5,80002868 <_vfprintf_r+0x1514> +80001fa0: fff00793 li a5,-1 +80001fa4: 000a0b93 mv s7,s4 +80001fa8: 02fd8463 beq s11,a5,80001fd0 <_vfprintf_r+0xc7c> +80001fac: 019967b3 or a5,s2,s9 +80001fb0: f7fa7b93 andi s7,s4,-129 +80001fb4: 00079e63 bnez a5,80001fd0 <_vfprintf_r+0xc7c> +80001fb8: 020d9263 bnez s11,80001fdc <_vfprintf_r+0xc88> +80001fbc: 000b8a13 mv s4,s7 +80001fc0: 00000d93 li s11,0 +80001fc4: 00000c93 li s9,0 +80001fc8: 1b010b13 addi s6,sp,432 +80001fcc: e45ff06f j 80001e10 <_vfprintf_r+0xabc> +80001fd0: 3a0c92e3 bnez s9,80002b74 <_vfprintf_r+0x1820> +80001fd4: 00900793 li a5,9 +80001fd8: 3927eee3 bltu a5,s2,80002b74 <_vfprintf_r+0x1820> +80001fdc: 03090913 addi s2,s2,48 +80001fe0: 1b2107a3 sb s2,431(sp) +80001fe4: 000b8a13 mv s4,s7 +80001fe8: 00100c93 li s9,1 +80001fec: 1af10b13 addi s6,sp,431 +80001ff0: e21ff06f j 80001e10 <_vfprintf_r+0xabc> +80001ff4: 000a0b93 mv s7,s4 +80001ff8: 00100713 li a4,1 +80001ffc: fce78ae3 beq a5,a4,80001fd0 <_vfprintf_r+0xc7c> +80002000: 00200713 li a4,2 +80002004: 06e78c63 beq a5,a4,8000207c <_vfprintf_r+0xd28> +80002008: 1b010b13 addi s6,sp,432 +8000200c: 01dc9713 slli a4,s9,0x1d +80002010: 00797793 andi a5,s2,7 +80002014: 00395913 srli s2,s2,0x3 +80002018: 03078793 addi a5,a5,48 +8000201c: 01276933 or s2,a4,s2 +80002020: 003cdc93 srli s9,s9,0x3 +80002024: fefb0fa3 sb a5,-1(s6) +80002028: 01996733 or a4,s2,s9 +8000202c: 000b0613 mv a2,s6 +80002030: fffb0b13 addi s6,s6,-1 +80002034: fc071ce3 bnez a4,8000200c <_vfprintf_r+0xcb8> +80002038: 001bf693 andi a3,s7,1 +8000203c: 06068a63 beqz a3,800020b0 <_vfprintf_r+0xd5c> +80002040: 03000693 li a3,48 +80002044: 06d78663 beq a5,a3,800020b0 <_vfprintf_r+0xd5c> +80002048: ffe60613 addi a2,a2,-2 +8000204c: 1b010793 addi a5,sp,432 +80002050: fedb0fa3 sb a3,-1(s6) +80002054: 40c78cb3 sub s9,a5,a2 +80002058: 000b8a13 mv s4,s7 +8000205c: 00060b13 mv s6,a2 +80002060: db1ff06f j 80001e10 <_vfprintf_r+0xabc> +80002064: 00100713 li a4,1 +80002068: 00e79463 bne a5,a4,80002070 <_vfprintf_r+0xd1c> +8000206c: 14d0106f j 800039b8 <_vfprintf_r+0x2664> +80002070: 00200713 li a4,2 +80002074: 000a0b93 mv s7,s4 +80002078: f8e798e3 bne a5,a4,80002008 <_vfprintf_r+0xcb4> +8000207c: 03412683 lw a3,52(sp) +80002080: 1b010b13 addi s6,sp,432 +80002084: 00f97793 andi a5,s2,15 +80002088: 00f687b3 add a5,a3,a5 +8000208c: 0007c703 lbu a4,0(a5) +80002090: 00495913 srli s2,s2,0x4 +80002094: 01cc9793 slli a5,s9,0x1c +80002098: 0127e933 or s2,a5,s2 +8000209c: 004cdc93 srli s9,s9,0x4 +800020a0: feeb0fa3 sb a4,-1(s6) +800020a4: 019967b3 or a5,s2,s9 +800020a8: fffb0b13 addi s6,s6,-1 +800020ac: fc079ce3 bnez a5,80002084 <_vfprintf_r+0xd30> +800020b0: 1b010793 addi a5,sp,432 +800020b4: 41678cb3 sub s9,a5,s6 +800020b8: 000b8a13 mv s4,s7 +800020bc: d55ff06f j 80001e10 <_vfprintf_r+0xabc> +800020c0: 06500693 li a3,101 +800020c4: 2c96dc63 bge a3,s1,8000239c <_vfprintf_r+0x1048> +800020c8: 0f012683 lw a3,240(sp) +800020cc: 0a010593 addi a1,sp,160 +800020d0: 0b010513 addi a0,sp,176 +800020d4: 0ad12823 sw a3,176(sp) +800020d8: 0f412683 lw a3,244(sp) +800020dc: 05112223 sw a7,68(sp) +800020e0: 04f12023 sw a5,64(sp) +800020e4: 0ad12a23 sw a3,180(sp) +800020e8: 0f812683 lw a3,248(sp) +800020ec: 0a012023 sw zero,160(sp) +800020f0: 0a012223 sw zero,164(sp) +800020f4: 0ad12c23 sw a3,184(sp) +800020f8: 0fc12683 lw a3,252(sp) +800020fc: 0a012423 sw zero,168(sp) +80002100: 0a012623 sw zero,172(sp) +80002104: 0ad12e23 sw a3,188(sp) +80002108: 7e00f0ef jal ra,800118e8 <__eqtf2> +8000210c: 04012783 lw a5,64(sp) +80002110: 04412883 lw a7,68(sp) +80002114: 4a051863 bnez a0,800025c4 <_vfprintf_r+0x1270> +80002118: 0e812703 lw a4,232(sp) +8000211c: 800156b7 lui a3,0x80015 +80002120: bd468693 addi a3,a3,-1068 # 80014bd4 <__BSS_END__+0xffffdf98> +80002124: 00d8a023 sw a3,0(a7) +80002128: 00178793 addi a5,a5,1 +8000212c: 00100693 li a3,1 +80002130: 00170713 addi a4,a4,1 +80002134: 00d8a223 sw a3,4(a7) +80002138: 0ef12623 sw a5,236(sp) +8000213c: 0ee12423 sw a4,232(sp) +80002140: 00700693 li a3,7 +80002144: 00888893 addi a7,a7,8 +80002148: 3ae6c6e3 blt a3,a4,80002cf4 <_vfprintf_r+0x19a0> +8000214c: 0cc12703 lw a4,204(sp) +80002150: 02012683 lw a3,32(sp) +80002154: 72d75c63 bge a4,a3,8000288c <_vfprintf_r+0x1538> +80002158: 03012703 lw a4,48(sp) +8000215c: 02c12683 lw a3,44(sp) +80002160: 00888893 addi a7,a7,8 +80002164: fee8ac23 sw a4,-8(a7) +80002168: 0e812703 lw a4,232(sp) +8000216c: 00d787b3 add a5,a5,a3 +80002170: fed8ae23 sw a3,-4(a7) +80002174: 00170713 addi a4,a4,1 +80002178: 0ef12623 sw a5,236(sp) +8000217c: 0ee12423 sw a4,232(sp) +80002180: 00700693 li a3,7 +80002184: 0ce6c0e3 blt a3,a4,80002a44 <_vfprintf_r+0x16f0> +80002188: 02012703 lw a4,32(sp) +8000218c: fff70493 addi s1,a4,-1 +80002190: cc905663 blez s1,8000165c <_vfprintf_r+0x308> +80002194: 01000693 li a3,16 +80002198: 0e812703 lw a4,232(sp) +8000219c: 3696dce3 bge a3,s1,80002d14 <_vfprintf_r+0x19c0> +800021a0: 01000913 li s2,16 +800021a4: 00700c93 li s9,7 +800021a8: 00c0006f j 800021b4 <_vfprintf_r+0xe60> +800021ac: ff048493 addi s1,s1,-16 +800021b0: 369952e3 bge s2,s1,80002d14 <_vfprintf_r+0x19c0> +800021b4: 00812683 lw a3,8(sp) +800021b8: 01078793 addi a5,a5,16 +800021bc: 00170713 addi a4,a4,1 +800021c0: 00d8a023 sw a3,0(a7) +800021c4: 0128a223 sw s2,4(a7) +800021c8: 0ef12623 sw a5,236(sp) +800021cc: 0ee12423 sw a4,232(sp) +800021d0: 00888893 addi a7,a7,8 +800021d4: fcecdce3 bge s9,a4,800021ac <_vfprintf_r+0xe58> +800021d8: 0e410613 addi a2,sp,228 +800021dc: 000c0593 mv a1,s8 +800021e0: 000d0513 mv a0,s10 +800021e4: 2f00a0ef jal ra,8000c4d4 <__sprint_r> +800021e8: 18051e63 bnez a0,80002384 <_vfprintf_r+0x1030> +800021ec: 0ec12783 lw a5,236(sp) +800021f0: 0e812703 lw a4,232(sp) +800021f4: 10c10893 addi a7,sp,268 +800021f8: fb5ff06f j 800021ac <_vfprintf_r+0xe58> +800021fc: 41598933 sub s2,s3,s5 +80002200: c3205263 blez s2,80001624 <_vfprintf_r+0x2d0> +80002204: 01000613 li a2,16 +80002208: 0e812683 lw a3,232(sp) +8000220c: 07265463 bge a2,s2,80002274 <_vfprintf_r+0xf20> +80002210: 01000e13 li t3,16 +80002214: 00700b93 li s7,7 +80002218: 00c0006f j 80002224 <_vfprintf_r+0xed0> +8000221c: ff090913 addi s2,s2,-16 +80002220: 052e5a63 bge t3,s2,80002274 <_vfprintf_r+0xf20> +80002224: 00812703 lw a4,8(sp) +80002228: 01078793 addi a5,a5,16 +8000222c: 00168693 addi a3,a3,1 +80002230: 00e8a023 sw a4,0(a7) +80002234: 01c8a223 sw t3,4(a7) +80002238: 0ef12623 sw a5,236(sp) +8000223c: 0ed12423 sw a3,232(sp) +80002240: 00888893 addi a7,a7,8 +80002244: fcdbdce3 bge s7,a3,8000221c <_vfprintf_r+0xec8> +80002248: 0e410613 addi a2,sp,228 +8000224c: 000c0593 mv a1,s8 +80002250: 000d0513 mv a0,s10 +80002254: 2800a0ef jal ra,8000c4d4 <__sprint_r> +80002258: 12051663 bnez a0,80002384 <_vfprintf_r+0x1030> +8000225c: 01000e13 li t3,16 +80002260: ff090913 addi s2,s2,-16 +80002264: 0ec12783 lw a5,236(sp) +80002268: 0e812683 lw a3,232(sp) +8000226c: 10c10893 addi a7,sp,268 +80002270: fb2e4ae3 blt t3,s2,80002224 <_vfprintf_r+0xed0> +80002274: 00812703 lw a4,8(sp) +80002278: 012787b3 add a5,a5,s2 +8000227c: 00168693 addi a3,a3,1 +80002280: 00e8a023 sw a4,0(a7) +80002284: 0128a223 sw s2,4(a7) +80002288: 0ef12623 sw a5,236(sp) +8000228c: 0ed12423 sw a3,232(sp) +80002290: 00700613 li a2,7 80002294: 00888893 addi a7,a7,8 -80002298: fcecdce3 bge s9,a4,80002270 <_vfprintf_r+0xe58> +80002298: b8d65663 bge a2,a3,80001624 <_vfprintf_r+0x2d0> 8000229c: 0e410613 addi a2,sp,228 800022a0: 000c0593 mv a1,s8 800022a4: 000d0513 mv a0,s10 -800022a8: 2f00a0ef jal ra,8000c598 <__sprint_r> -800022ac: 18051e63 bnez a0,80002448 <_vfprintf_r+0x1030> +800022a8: 22c0a0ef jal ra,8000c4d4 <__sprint_r> +800022ac: 0c051c63 bnez a0,80002384 <_vfprintf_r+0x1030> 800022b0: 0ec12783 lw a5,236(sp) -800022b4: 0e812703 lw a4,232(sp) -800022b8: 10c10893 addi a7,sp,268 -800022bc: fb5ff06f j 80002270 <_vfprintf_r+0xe58> -800022c0: 41598933 sub s2,s3,s5 -800022c4: c3205263 blez s2,800016e8 <_vfprintf_r+0x2d0> -800022c8: 01000613 li a2,16 -800022cc: 0e812683 lw a3,232(sp) -800022d0: 07265463 bge a2,s2,80002338 <_vfprintf_r+0xf20> -800022d4: 01000e13 li t3,16 -800022d8: 00700b93 li s7,7 -800022dc: 00c0006f j 800022e8 <_vfprintf_r+0xed0> -800022e0: ff090913 addi s2,s2,-16 -800022e4: 052e5a63 bge t3,s2,80002338 <_vfprintf_r+0xf20> -800022e8: 00812703 lw a4,8(sp) -800022ec: 01078793 addi a5,a5,16 -800022f0: 00168693 addi a3,a3,1 -800022f4: 00e8a023 sw a4,0(a7) -800022f8: 01c8a223 sw t3,4(a7) -800022fc: 0ef12623 sw a5,236(sp) -80002300: 0ed12423 sw a3,232(sp) -80002304: 00888893 addi a7,a7,8 -80002308: fcdbdce3 bge s7,a3,800022e0 <_vfprintf_r+0xec8> -8000230c: 0e410613 addi a2,sp,228 -80002310: 000c0593 mv a1,s8 -80002314: 000d0513 mv a0,s10 -80002318: 2800a0ef jal ra,8000c598 <__sprint_r> -8000231c: 12051663 bnez a0,80002448 <_vfprintf_r+0x1030> -80002320: 01000e13 li t3,16 -80002324: ff090913 addi s2,s2,-16 -80002328: 0ec12783 lw a5,236(sp) -8000232c: 0e812683 lw a3,232(sp) -80002330: 10c10893 addi a7,sp,268 -80002334: fb2e4ae3 blt t3,s2,800022e8 <_vfprintf_r+0xed0> -80002338: 00812703 lw a4,8(sp) -8000233c: 012787b3 add a5,a5,s2 -80002340: 00168693 addi a3,a3,1 -80002344: 00e8a023 sw a4,0(a7) -80002348: 0128a223 sw s2,4(a7) -8000234c: 0ef12623 sw a5,236(sp) -80002350: 0ed12423 sw a3,232(sp) -80002354: 00700613 li a2,7 -80002358: 00888893 addi a7,a7,8 -8000235c: b8d65663 bge a2,a3,800016e8 <_vfprintf_r+0x2d0> -80002360: 0e410613 addi a2,sp,228 -80002364: 000c0593 mv a1,s8 -80002368: 000d0513 mv a0,s10 -8000236c: 22c0a0ef jal ra,8000c598 <__sprint_r> -80002370: 0c051c63 bnez a0,80002448 <_vfprintf_r+0x1030> -80002374: 0ec12783 lw a5,236(sp) -80002378: 10c10893 addi a7,sp,268 -8000237c: b6cff06f j 800016e8 <_vfprintf_r+0x2d0> -80002380: 01000613 li a2,16 -80002384: 0e812683 lw a3,232(sp) -80002388: 07b65263 bge a2,s11,800023ec <_vfprintf_r+0xfd4> -8000238c: 01000b93 li s7,16 -80002390: 00700913 li s2,7 -80002394: 00c0006f j 800023a0 <_vfprintf_r+0xf88> -80002398: ff0d8d93 addi s11,s11,-16 -8000239c: 05bbd863 bge s7,s11,800023ec <_vfprintf_r+0xfd4> -800023a0: 00812703 lw a4,8(sp) -800023a4: 01078793 addi a5,a5,16 -800023a8: 00168693 addi a3,a3,1 -800023ac: 00e8a023 sw a4,0(a7) -800023b0: 0178a223 sw s7,4(a7) -800023b4: 0ef12623 sw a5,236(sp) -800023b8: 0ed12423 sw a3,232(sp) -800023bc: 00888893 addi a7,a7,8 -800023c0: fcd95ce3 bge s2,a3,80002398 <_vfprintf_r+0xf80> -800023c4: 0e410613 addi a2,sp,228 -800023c8: 000c0593 mv a1,s8 -800023cc: 000d0513 mv a0,s10 -800023d0: 1c80a0ef jal ra,8000c598 <__sprint_r> -800023d4: 06051a63 bnez a0,80002448 <_vfprintf_r+0x1030> -800023d8: ff0d8d93 addi s11,s11,-16 -800023dc: 0ec12783 lw a5,236(sp) -800023e0: 0e812683 lw a3,232(sp) -800023e4: 10c10893 addi a7,sp,268 -800023e8: fbbbcce3 blt s7,s11,800023a0 <_vfprintf_r+0xf88> -800023ec: 00812703 lw a4,8(sp) -800023f0: 01b787b3 add a5,a5,s11 -800023f4: 00168693 addi a3,a3,1 -800023f8: 00e8a023 sw a4,0(a7) -800023fc: 01b8a223 sw s11,4(a7) -80002400: 0ef12623 sw a5,236(sp) -80002404: 0ed12423 sw a3,232(sp) -80002408: 00700613 li a2,7 -8000240c: 00888893 addi a7,a7,8 -80002410: aed65063 bge a2,a3,800016f0 <_vfprintf_r+0x2d8> -80002414: 0e410613 addi a2,sp,228 -80002418: 000c0593 mv a1,s8 -8000241c: 000d0513 mv a0,s10 -80002420: 1780a0ef jal ra,8000c598 <__sprint_r> -80002424: 02051263 bnez a0,80002448 <_vfprintf_r+0x1030> -80002428: 0ec12783 lw a5,236(sp) -8000242c: 10c10893 addi a7,sp,268 -80002430: ac0ff06f j 800016f0 <_vfprintf_r+0x2d8> -80002434: 0e410613 addi a2,sp,228 -80002438: 000c0593 mv a1,s8 -8000243c: 000d0513 mv a0,s10 -80002440: 1580a0ef jal ra,8000c598 <__sprint_r> -80002444: b0050263 beqz a0,80001748 <_vfprintf_r+0x330> -80002448: 01012b83 lw s7,16(sp) -8000244c: b20b8863 beqz s7,8000177c <_vfprintf_r+0x364> -80002450: 000b8593 mv a1,s7 -80002454: 000d0513 mv a0,s10 -80002458: 57c020ef jal ra,800049d4 <_free_r> -8000245c: b20ff06f j 8000177c <_vfprintf_r+0x364> -80002460: 0e812683 lw a3,232(sp) -80002464: 00178c93 addi s9,a5,1 -80002468: 02012783 lw a5,32(sp) -8000246c: 00100613 li a2,1 -80002470: 0168a023 sw s6,0(a7) -80002474: 00168493 addi s1,a3,1 -80002478: 00888913 addi s2,a7,8 -8000247c: 38f65663 bge a2,a5,80002808 <_vfprintf_r+0x13f0> -80002480: 00100793 li a5,1 -80002484: 00f8a223 sw a5,4(a7) -80002488: 0f912623 sw s9,236(sp) -8000248c: 0e912423 sw s1,232(sp) -80002490: 00700793 li a5,7 -80002494: 7497ce63 blt a5,s1,80002bf0 <_vfprintf_r+0x17d8> -80002498: 02c12783 lw a5,44(sp) -8000249c: 03012703 lw a4,48(sp) -800024a0: 00148493 addi s1,s1,1 -800024a4: 00fc8cb3 add s9,s9,a5 -800024a8: 00f92223 sw a5,4(s2) -800024ac: 00e92023 sw a4,0(s2) -800024b0: 0f912623 sw s9,236(sp) -800024b4: 0e912423 sw s1,232(sp) -800024b8: 00700793 li a5,7 -800024bc: 00890913 addi s2,s2,8 -800024c0: 7497ca63 blt a5,s1,80002c14 <_vfprintf_r+0x17fc> -800024c4: 0f012783 lw a5,240(sp) -800024c8: 00148613 addi a2,s1,1 -800024cc: 0a010593 addi a1,sp,160 -800024d0: 0af12823 sw a5,176(sp) -800024d4: 0f412783 lw a5,244(sp) -800024d8: 0b010513 addi a0,sp,176 -800024dc: 00c12e23 sw a2,28(sp) -800024e0: 0af12a23 sw a5,180(sp) -800024e4: 0f812783 lw a5,248(sp) -800024e8: 0a012023 sw zero,160(sp) -800024ec: 0a012223 sw zero,164(sp) -800024f0: 0af12c23 sw a5,184(sp) -800024f4: 0fc12783 lw a5,252(sp) -800024f8: 0a012423 sw zero,168(sp) -800024fc: 0a012623 sw zero,172(sp) -80002500: 0af12e23 sw a5,188(sp) -80002504: 4a80f0ef jal ra,800119ac <__eqtf2> -80002508: 01c12603 lw a2,28(sp) -8000250c: 02012783 lw a5,32(sp) -80002510: 00890893 addi a7,s2,8 -80002514: 00060693 mv a3,a2 -80002518: fff78d93 addi s11,a5,-1 -8000251c: 30050a63 beqz a0,80002830 <_vfprintf_r+0x1418> -80002520: 001b0713 addi a4,s6,1 -80002524: 01bc8cb3 add s9,s9,s11 -80002528: 00e92023 sw a4,0(s2) -8000252c: 01b92223 sw s11,4(s2) -80002530: 0f912623 sw s9,236(sp) -80002534: 0ec12423 sw a2,232(sp) -80002538: 00700793 li a5,7 -8000253c: 50c7cc63 blt a5,a2,80002a54 <_vfprintf_r+0x163c> -80002540: 01090793 addi a5,s2,16 -80002544: 00248693 addi a3,s1,2 -80002548: 00088913 mv s2,a7 -8000254c: 00078893 mv a7,a5 -80002550: 03812603 lw a2,56(sp) -80002554: 0d410713 addi a4,sp,212 -80002558: 00e92023 sw a4,0(s2) -8000255c: 019607b3 add a5,a2,s9 -80002560: 00c92223 sw a2,4(s2) -80002564: 0ef12623 sw a5,236(sp) -80002568: 0ed12423 sw a3,232(sp) -8000256c: 00700713 li a4,7 -80002570: 9ad75863 bge a4,a3,80001720 <_vfprintf_r+0x308> -80002574: ef4ff06f j 80001c68 <_vfprintf_r+0x850> -80002578: 80015737 lui a4,0x80015 -8000257c: 01000613 li a2,16 -80002580: 0e812683 lw a3,232(sp) -80002584: e1870e93 addi t4,a4,-488 # 80014e18 <__BSS_END__+0xffffe1dc> -80002588: 09065c63 bge a2,a6,80002620 <_vfprintf_r+0x1208> -8000258c: 04812023 sw s0,64(sp) -80002590: 04912223 sw s1,68(sp) -80002594: 000d0413 mv s0,s10 -80002598: 000c0493 mv s1,s8 -8000259c: 01000e13 li t3,16 -800025a0: 00700293 li t0,7 -800025a4: 00080c13 mv s8,a6 -800025a8: 000e8d13 mv s10,t4 -800025ac: 00c0006f j 800025b8 <_vfprintf_r+0x11a0> -800025b0: ff0c0c13 addi s8,s8,-16 -800025b4: 058e5a63 bge t3,s8,80002608 <_vfprintf_r+0x11f0> -800025b8: 01078793 addi a5,a5,16 -800025bc: 00168693 addi a3,a3,1 -800025c0: 01a8a023 sw s10,0(a7) -800025c4: 01c8a223 sw t3,4(a7) -800025c8: 0ef12623 sw a5,236(sp) -800025cc: 0ed12423 sw a3,232(sp) -800025d0: 00888893 addi a7,a7,8 -800025d4: fcd2dee3 bge t0,a3,800025b0 <_vfprintf_r+0x1198> -800025d8: 0e410613 addi a2,sp,228 -800025dc: 00048593 mv a1,s1 -800025e0: 00040513 mv a0,s0 -800025e4: 7b5090ef jal ra,8000c598 <__sprint_r> -800025e8: 7a051263 bnez a0,80002d8c <_vfprintf_r+0x1974> -800025ec: 01000e13 li t3,16 -800025f0: ff0c0c13 addi s8,s8,-16 -800025f4: 0ec12783 lw a5,236(sp) -800025f8: 0e812683 lw a3,232(sp) -800025fc: 10c10893 addi a7,sp,268 -80002600: 00700293 li t0,7 -80002604: fb8e4ae3 blt t3,s8,800025b8 <_vfprintf_r+0x11a0> -80002608: 000c0813 mv a6,s8 -8000260c: 000d0e93 mv t4,s10 -80002610: 00048c13 mv s8,s1 -80002614: 00040d13 mv s10,s0 -80002618: 04412483 lw s1,68(sp) -8000261c: 04012403 lw s0,64(sp) -80002620: 010787b3 add a5,a5,a6 -80002624: 00168693 addi a3,a3,1 -80002628: 01d8a023 sw t4,0(a7) -8000262c: 0108a223 sw a6,4(a7) -80002630: 0ef12623 sw a5,236(sp) -80002634: 0ed12423 sw a3,232(sp) -80002638: 00700613 li a2,7 -8000263c: 00888893 addi a7,a7,8 -80002640: 00d64463 blt a2,a3,80002648 <_vfprintf_r+0x1230> -80002644: 82cff06f j 80001670 <_vfprintf_r+0x258> -80002648: 0e410613 addi a2,sp,228 -8000264c: 000c0593 mv a1,s8 -80002650: 000d0513 mv a0,s10 -80002654: 745090ef jal ra,8000c598 <__sprint_r> -80002658: de0518e3 bnez a0,80002448 <_vfprintf_r+0x1030> -8000265c: 0ec12783 lw a5,236(sp) -80002660: 10c10893 addi a7,sp,268 -80002664: 80cff06f j 80001670 <_vfprintf_r+0x258> -80002668: 0e410613 addi a2,sp,228 -8000266c: 000c0593 mv a1,s8 -80002670: 000d0513 mv a0,s10 -80002674: 725090ef jal ra,8000c598 <__sprint_r> -80002678: dc0518e3 bnez a0,80002448 <_vfprintf_r+0x1030> -8000267c: 0ec12783 lw a5,236(sp) -80002680: 10c10893 addi a7,sp,268 -80002684: 85cff06f j 800016e0 <_vfprintf_r+0x2c8> -80002688: 0cc12583 lw a1,204(sp) -8000268c: 66b05c63 blez a1,80002d04 <_vfprintf_r+0x18ec> -80002690: 01c12703 lw a4,28(sp) -80002694: 02012683 lw a3,32(sp) -80002698: 00070493 mv s1,a4 -8000269c: 38e6c263 blt a3,a4,80002a20 <_vfprintf_r+0x1608> -800026a0: 02905663 blez s1,800026cc <_vfprintf_r+0x12b4> -800026a4: 0e812683 lw a3,232(sp) -800026a8: 009787b3 add a5,a5,s1 -800026ac: 0168a023 sw s6,0(a7) -800026b0: 00168693 addi a3,a3,1 -800026b4: 0098a223 sw s1,4(a7) -800026b8: 0ef12623 sw a5,236(sp) -800026bc: 0ed12423 sw a3,232(sp) -800026c0: 00700613 li a2,7 -800026c4: 00888893 addi a7,a7,8 -800026c8: 32d642e3 blt a2,a3,800031ec <_vfprintf_r+0x1dd4> -800026cc: fff4c693 not a3,s1 -800026d0: 01c12703 lw a4,28(sp) -800026d4: 41f6d693 srai a3,a3,0x1f -800026d8: 00d4f4b3 and s1,s1,a3 -800026dc: 409704b3 sub s1,a4,s1 -800026e0: 48904463 bgtz s1,80002b68 <_vfprintf_r+0x1750> -800026e4: 01c12703 lw a4,28(sp) -800026e8: 400a7693 andi a3,s4,1024 -800026ec: 00eb0db3 add s11,s6,a4 -800026f0: 0c0698e3 bnez a3,80002fc0 <_vfprintf_r+0x1ba8> -800026f4: 0cc12483 lw s1,204(sp) -800026f8: 02012703 lw a4,32(sp) -800026fc: 00e4c663 blt s1,a4,80002708 <_vfprintf_r+0x12f0> -80002700: 001a7693 andi a3,s4,1 -80002704: 300688e3 beqz a3,80003214 <_vfprintf_r+0x1dfc> -80002708: 03012683 lw a3,48(sp) -8000270c: 02c12703 lw a4,44(sp) -80002710: 00700613 li a2,7 -80002714: 00d8a023 sw a3,0(a7) -80002718: 0e812683 lw a3,232(sp) -8000271c: 00e787b3 add a5,a5,a4 -80002720: 00e8a223 sw a4,4(a7) -80002724: 00168693 addi a3,a3,1 -80002728: 0ef12623 sw a5,236(sp) -8000272c: 0ed12423 sw a3,232(sp) -80002730: 00888893 addi a7,a7,8 -80002734: 00d65463 bge a2,a3,8000273c <_vfprintf_r+0x1324> -80002738: 1780106f j 800038b0 <_vfprintf_r+0x2498> -8000273c: 02012683 lw a3,32(sp) -80002740: 00db0733 add a4,s6,a3 -80002744: 409684b3 sub s1,a3,s1 -80002748: 41b70733 sub a4,a4,s11 -8000274c: 00048913 mv s2,s1 -80002750: 00975463 bge a4,s1,80002758 <_vfprintf_r+0x1340> -80002754: 00070913 mv s2,a4 -80002758: 03205863 blez s2,80002788 <_vfprintf_r+0x1370> -8000275c: 0e812703 lw a4,232(sp) -80002760: 012787b3 add a5,a5,s2 -80002764: 01b8a023 sw s11,0(a7) -80002768: 00170713 addi a4,a4,1 -8000276c: 0128a223 sw s2,4(a7) -80002770: 0ef12623 sw a5,236(sp) -80002774: 0ee12423 sw a4,232(sp) -80002778: 00700693 li a3,7 -8000277c: 00888893 addi a7,a7,8 -80002780: 00e6d463 bge a3,a4,80002788 <_vfprintf_r+0x1370> -80002784: 1c80106f j 8000394c <_vfprintf_r+0x2534> -80002788: fff94713 not a4,s2 -8000278c: 41f75713 srai a4,a4,0x1f -80002790: 00e97733 and a4,s2,a4 -80002794: 40e484b3 sub s1,s1,a4 -80002798: 00904463 bgtz s1,800027a0 <_vfprintf_r+0x1388> -8000279c: f85fe06f j 80001720 <_vfprintf_r+0x308> -800027a0: 01000693 li a3,16 -800027a4: 0e812703 lw a4,232(sp) -800027a8: 6296d863 bge a3,s1,80002dd8 <_vfprintf_r+0x19c0> -800027ac: 01000913 li s2,16 -800027b0: 00700c93 li s9,7 -800027b4: 00c0006f j 800027c0 <_vfprintf_r+0x13a8> -800027b8: ff048493 addi s1,s1,-16 -800027bc: 60995e63 bge s2,s1,80002dd8 <_vfprintf_r+0x19c0> -800027c0: 00812683 lw a3,8(sp) -800027c4: 01078793 addi a5,a5,16 -800027c8: 00170713 addi a4,a4,1 -800027cc: 00d8a023 sw a3,0(a7) -800027d0: 0128a223 sw s2,4(a7) -800027d4: 0ef12623 sw a5,236(sp) -800027d8: 0ee12423 sw a4,232(sp) -800027dc: 00888893 addi a7,a7,8 -800027e0: fcecdce3 bge s9,a4,800027b8 <_vfprintf_r+0x13a0> -800027e4: 0e410613 addi a2,sp,228 -800027e8: 000c0593 mv a1,s8 -800027ec: 000d0513 mv a0,s10 -800027f0: 5a9090ef jal ra,8000c598 <__sprint_r> -800027f4: c4051ae3 bnez a0,80002448 <_vfprintf_r+0x1030> -800027f8: 0ec12783 lw a5,236(sp) -800027fc: 0e812703 lw a4,232(sp) -80002800: 10c10893 addi a7,sp,268 -80002804: fb5ff06f j 800027b8 <_vfprintf_r+0x13a0> -80002808: 001a7793 andi a5,s4,1 -8000280c: c6079ae3 bnez a5,80002480 <_vfprintf_r+0x1068> -80002810: 00c8a223 sw a2,4(a7) -80002814: 0f912623 sw s9,236(sp) -80002818: 0e912423 sw s1,232(sp) -8000281c: 00700793 li a5,7 -80002820: 2297ca63 blt a5,s1,80002a54 <_vfprintf_r+0x163c> -80002824: 00268693 addi a3,a3,2 -80002828: 01088893 addi a7,a7,16 -8000282c: d25ff06f j 80002550 <_vfprintf_r+0x1138> -80002830: d3b050e3 blez s11,80002550 <_vfprintf_r+0x1138> -80002834: 01000713 li a4,16 -80002838: 01b74463 blt a4,s11,80002840 <_vfprintf_r+0x1428> -8000283c: 6180106f j 80003e54 <_vfprintf_r+0x2a3c> -80002840: 00700b13 li s6,7 -80002844: 00060493 mv s1,a2 -80002848: 0100006f j 80002858 <_vfprintf_r+0x1440> -8000284c: ff0d8d93 addi s11,s11,-16 -80002850: 1db75e63 bge a4,s11,80002a2c <_vfprintf_r+0x1614> -80002854: 00148493 addi s1,s1,1 -80002858: 00812783 lw a5,8(sp) -8000285c: 010c8c93 addi s9,s9,16 -80002860: 00e92223 sw a4,4(s2) -80002864: 00f92023 sw a5,0(s2) -80002868: 0f912623 sw s9,236(sp) -8000286c: 0e912423 sw s1,232(sp) -80002870: 00890913 addi s2,s2,8 -80002874: fc9b5ce3 bge s6,s1,8000284c <_vfprintf_r+0x1434> -80002878: 0e410613 addi a2,sp,228 -8000287c: 000c0593 mv a1,s8 -80002880: 000d0513 mv a0,s10 -80002884: 515090ef jal ra,8000c598 <__sprint_r> -80002888: bc0510e3 bnez a0,80002448 <_vfprintf_r+0x1030> -8000288c: 0ec12c83 lw s9,236(sp) -80002890: 0e812483 lw s1,232(sp) -80002894: 10c10913 addi s2,sp,268 -80002898: 01000713 li a4,16 -8000289c: fb1ff06f j 8000284c <_vfprintf_r+0x1434> -800028a0: 01412683 lw a3,20(sp) -800028a4: 010a7793 andi a5,s4,16 -800028a8: 00468713 addi a4,a3,4 -800028ac: 16079263 bnez a5,80002a10 <_vfprintf_r+0x15f8> -800028b0: 040a7793 andi a5,s4,64 -800028b4: 68078463 beqz a5,80002f3c <_vfprintf_r+0x1b24> -800028b8: 01412783 lw a5,20(sp) -800028bc: 00000c93 li s9,0 -800028c0: 00e12a23 sw a4,20(sp) -800028c4: 0007d903 lhu s2,0(a5) -800028c8: f1cff06f j 80001fe4 <_vfprintf_r+0xbcc> -800028cc: 01412683 lw a3,20(sp) -800028d0: 010bf793 andi a5,s7,16 -800028d4: 00468713 addi a4,a3,4 -800028d8: 0c079e63 bnez a5,800029b4 <_vfprintf_r+0x159c> -800028dc: 040bf793 andi a5,s7,64 -800028e0: 60078e63 beqz a5,80002efc <_vfprintf_r+0x1ae4> -800028e4: 01412783 lw a5,20(sp) -800028e8: 00000c93 li s9,0 -800028ec: 00e12a23 sw a4,20(sp) -800028f0: 0007d903 lhu s2,0(a5) -800028f4: 00100793 li a5,1 -800028f8: db0ff06f j 80001ea8 <_vfprintf_r+0xa90> -800028fc: 01412683 lw a3,20(sp) -80002900: 010a7793 andi a5,s4,16 -80002904: 00468713 addi a4,a3,4 -80002908: 0e079a63 bnez a5,800029fc <_vfprintf_r+0x15e4> -8000290c: 040a7793 andi a5,s4,64 -80002910: 60078663 beqz a5,80002f1c <_vfprintf_r+0x1b04> -80002914: 01412783 lw a5,20(sp) -80002918: 00e12a23 sw a4,20(sp) -8000291c: 00079903 lh s2,0(a5) -80002920: 41f95c93 srai s9,s2,0x1f -80002924: 000c8793 mv a5,s9 -80002928: f207de63 bgez a5,80002064 <_vfprintf_r+0xc4c> -8000292c: 012037b3 snez a5,s2 -80002930: 41900cb3 neg s9,s9 -80002934: 40fc8cb3 sub s9,s9,a5 -80002938: 02d00793 li a5,45 -8000293c: 0cf103a3 sb a5,199(sp) -80002940: 41200933 neg s2,s2 -80002944: 000a0b93 mv s7,s4 -80002948: 00100793 li a5,1 -8000294c: d60ff06f j 80001eac <_vfprintf_r+0xa94> -80002950: 001a7713 andi a4,s4,1 -80002954: 00071463 bnez a4,8000295c <_vfprintf_r+0x1544> -80002958: dc9fe06f j 80001720 <_vfprintf_r+0x308> -8000295c: 8c1ff06f j 8000221c <_vfprintf_r+0xe04> -80002960: 000c8893 mv a7,s9 -80002964: ed4ff06f j 80002038 <_vfprintf_r+0xc20> -80002968: 03000793 li a5,48 -8000296c: 1af107a3 sb a5,431(sp) -80002970: 1af10b13 addi s6,sp,431 -80002974: d60ff06f j 80001ed4 <_vfprintf_r+0xabc> -80002978: 03c12783 lw a5,60(sp) -8000297c: 00044483 lbu s1,0(s0) -80002980: 00079463 bnez a5,80002988 <_vfprintf_r+0x1570> -80002984: c4dfe06f j 800015d0 <_vfprintf_r+0x1b8> -80002988: 0007c783 lbu a5,0(a5) -8000298c: 00079463 bnez a5,80002994 <_vfprintf_r+0x157c> -80002990: c41fe06f j 800015d0 <_vfprintf_r+0x1b8> -80002994: 400a6a13 ori s4,s4,1024 -80002998: c39fe06f j 800015d0 <_vfprintf_r+0x1b8> -8000299c: 00c12683 lw a3,12(sp) -800029a0: 00040b13 mv s6,s0 -800029a4: 41f6d793 srai a5,a3,0x1f -800029a8: 00d72023 sw a3,0(a4) -800029ac: 00f72223 sw a5,4(a4) -800029b0: db9fe06f j 80001768 <_vfprintf_r+0x350> -800029b4: 0006a903 lw s2,0(a3) -800029b8: 00000c93 li s9,0 -800029bc: 00e12a23 sw a4,20(sp) -800029c0: 00100793 li a5,1 -800029c4: ce4ff06f j 80001ea8 <_vfprintf_r+0xa90> -800029c8: 01412703 lw a4,20(sp) -800029cc: 00072783 lw a5,0(a4) -800029d0: 00470713 addi a4,a4,4 -800029d4: 00e12a23 sw a4,20(sp) -800029d8: 0007a583 lw a1,0(a5) -800029dc: 0047a603 lw a2,4(a5) -800029e0: 0087a683 lw a3,8(a5) -800029e4: 00c7a783 lw a5,12(a5) -800029e8: 0eb12823 sw a1,240(sp) -800029ec: 0ec12a23 sw a2,244(sp) -800029f0: 0ed12c23 sw a3,248(sp) -800029f4: 0ef12e23 sw a5,252(sp) -800029f8: ef5fe06f j 800018ec <_vfprintf_r+0x4d4> -800029fc: 0006a903 lw s2,0(a3) -80002a00: 00e12a23 sw a4,20(sp) -80002a04: 41f95c93 srai s9,s2,0x1f -80002a08: 000c8793 mv a5,s9 -80002a0c: e54ff06f j 80002060 <_vfprintf_r+0xc48> -80002a10: 0006a903 lw s2,0(a3) -80002a14: 00000c93 li s9,0 -80002a18: 00e12a23 sw a4,20(sp) -80002a1c: dc8ff06f j 80001fe4 <_vfprintf_r+0xbcc> -80002a20: 00068493 mv s1,a3 -80002a24: c89040e3 bgtz s1,800026a4 <_vfprintf_r+0x128c> -80002a28: ca5ff06f j 800026cc <_vfprintf_r+0x12b4> -80002a2c: 00148693 addi a3,s1,1 -80002a30: 00890713 addi a4,s2,8 -80002a34: 00812783 lw a5,8(sp) -80002a38: 01bc8cb3 add s9,s9,s11 -80002a3c: 01b92223 sw s11,4(s2) -80002a40: 00f92023 sw a5,0(s2) -80002a44: 0f912623 sw s9,236(sp) -80002a48: 0ed12423 sw a3,232(sp) -80002a4c: 00700793 li a5,7 -80002a50: 74d7de63 bge a5,a3,800031ac <_vfprintf_r+0x1d94> -80002a54: 0e410613 addi a2,sp,228 -80002a58: 000c0593 mv a1,s8 -80002a5c: 000d0513 mv a0,s10 -80002a60: 339090ef jal ra,8000c598 <__sprint_r> -80002a64: 9e0512e3 bnez a0,80002448 <_vfprintf_r+0x1030> -80002a68: 0e812683 lw a3,232(sp) -80002a6c: 0ec12c83 lw s9,236(sp) -80002a70: 11410893 addi a7,sp,276 -80002a74: 00168693 addi a3,a3,1 -80002a78: 10c10913 addi s2,sp,268 -80002a7c: ad5ff06f j 80002550 <_vfprintf_r+0x1138> -80002a80: 000c8893 mv a7,s9 -80002a84: 000a0b93 mv s7,s4 -80002a88: d70ff06f j 80001ff8 <_vfprintf_r+0xbe0> -80002a8c: 800157b7 lui a5,0x80015 -80002a90: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -80002a94: 000c8893 mv a7,s9 -80002a98: 02f12a23 sw a5,52(sp) -80002a9c: 020a7793 andi a5,s4,32 -80002aa0: 12078863 beqz a5,80002bd0 <_vfprintf_r+0x17b8> -80002aa4: 01412783 lw a5,20(sp) -80002aa8: 00778b13 addi s6,a5,7 -80002aac: ff8b7b13 andi s6,s6,-8 -80002ab0: 000b2903 lw s2,0(s6) -80002ab4: 004b2c83 lw s9,4(s6) -80002ab8: 008b0793 addi a5,s6,8 -80002abc: 00f12a23 sw a5,20(sp) -80002ac0: 001a7793 andi a5,s4,1 -80002ac4: 00078e63 beqz a5,80002ae0 <_vfprintf_r+0x16c8> -80002ac8: 019967b3 or a5,s2,s9 -80002acc: 00078a63 beqz a5,80002ae0 <_vfprintf_r+0x16c8> -80002ad0: 03000793 li a5,48 -80002ad4: 0cf10423 sb a5,200(sp) -80002ad8: 0c9104a3 sb s1,201(sp) -80002adc: 002a6a13 ori s4,s4,2 -80002ae0: bffa7b93 andi s7,s4,-1025 -80002ae4: 00200793 li a5,2 -80002ae8: bc0ff06f j 80001ea8 <_vfprintf_r+0xa90> -80002aec: 800157b7 lui a5,0x80015 -80002af0: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> -80002af4: 000c8893 mv a7,s9 -80002af8: 02f12a23 sw a5,52(sp) -80002afc: fa1ff06f j 80002a9c <_vfprintf_r+0x1684> -80002b00: 000c8893 mv a7,s9 -80002b04: cbcff06f j 80001fc0 <_vfprintf_r+0xba8> -80002b08: 0e410613 addi a2,sp,228 -80002b0c: 000c0593 mv a1,s8 -80002b10: 000d0513 mv a0,s10 -80002b14: 285090ef jal ra,8000c598 <__sprint_r> -80002b18: 920518e3 bnez a0,80002448 <_vfprintf_r+0x1030> -80002b1c: 0ec12783 lw a5,236(sp) -80002b20: 10c10893 addi a7,sp,268 -80002b24: f28ff06f j 8000224c <_vfprintf_r+0xe34> -80002b28: 00144483 lbu s1,1(s0) -80002b2c: 020a6a13 ori s4,s4,32 -80002b30: 00140413 addi s0,s0,1 -80002b34: a9dfe06f j 800015d0 <_vfprintf_r+0x1b8> -80002b38: 00144483 lbu s1,1(s0) -80002b3c: 200a6a13 ori s4,s4,512 -80002b40: 00140413 addi s0,s0,1 -80002b44: a8dfe06f j 800015d0 <_vfprintf_r+0x1b8> -80002b48: 00600793 li a5,6 -80002b4c: 000d8c93 mv s9,s11 -80002b50: 6bb7ee63 bltu a5,s11,8000320c <_vfprintf_r+0x1df4> -80002b54: 80015737 lui a4,0x80015 -80002b58: 000c8a93 mv s5,s9 -80002b5c: 01212a23 sw s2,20(sp) -80002b60: ca070b13 addi s6,a4,-864 # 80014ca0 <__BSS_END__+0xffffe064> -80002b64: ad9fe06f j 8000163c <_vfprintf_r+0x224> -80002b68: 01000613 li a2,16 -80002b6c: 0e812683 lw a3,232(sp) -80002b70: 40965463 bge a2,s1,80002f78 <_vfprintf_r+0x1b60> -80002b74: 01000c93 li s9,16 -80002b78: 00700d93 li s11,7 -80002b7c: 00c0006f j 80002b88 <_vfprintf_r+0x1770> -80002b80: ff048493 addi s1,s1,-16 -80002b84: 3e9cda63 bge s9,s1,80002f78 <_vfprintf_r+0x1b60> -80002b88: 00812703 lw a4,8(sp) -80002b8c: 01078793 addi a5,a5,16 -80002b90: 00168693 addi a3,a3,1 -80002b94: 00e8a023 sw a4,0(a7) -80002b98: 0198a223 sw s9,4(a7) -80002b9c: 0ef12623 sw a5,236(sp) -80002ba0: 0ed12423 sw a3,232(sp) -80002ba4: 00888893 addi a7,a7,8 -80002ba8: fcdddce3 bge s11,a3,80002b80 <_vfprintf_r+0x1768> -80002bac: 0e410613 addi a2,sp,228 -80002bb0: 000c0593 mv a1,s8 -80002bb4: 000d0513 mv a0,s10 -80002bb8: 1e1090ef jal ra,8000c598 <__sprint_r> -80002bbc: 880516e3 bnez a0,80002448 <_vfprintf_r+0x1030> -80002bc0: 0ec12783 lw a5,236(sp) -80002bc4: 0e812683 lw a3,232(sp) -80002bc8: 10c10893 addi a7,sp,268 -80002bcc: fb5ff06f j 80002b80 <_vfprintf_r+0x1768> -80002bd0: 01412683 lw a3,20(sp) -80002bd4: 010a7793 andi a5,s4,16 -80002bd8: 00468713 addi a4,a3,4 -80002bdc: 1c078063 beqz a5,80002d9c <_vfprintf_r+0x1984> -80002be0: 0006a903 lw s2,0(a3) -80002be4: 00000c93 li s9,0 -80002be8: 00e12a23 sw a4,20(sp) -80002bec: ed5ff06f j 80002ac0 <_vfprintf_r+0x16a8> -80002bf0: 0e410613 addi a2,sp,228 -80002bf4: 000c0593 mv a1,s8 -80002bf8: 000d0513 mv a0,s10 -80002bfc: 19d090ef jal ra,8000c598 <__sprint_r> -80002c00: 840514e3 bnez a0,80002448 <_vfprintf_r+0x1030> -80002c04: 0ec12c83 lw s9,236(sp) -80002c08: 0e812483 lw s1,232(sp) -80002c0c: 10c10913 addi s2,sp,268 -80002c10: 889ff06f j 80002498 <_vfprintf_r+0x1080> -80002c14: 0e410613 addi a2,sp,228 -80002c18: 000c0593 mv a1,s8 -80002c1c: 000d0513 mv a0,s10 -80002c20: 179090ef jal ra,8000c598 <__sprint_r> -80002c24: 820512e3 bnez a0,80002448 <_vfprintf_r+0x1030> -80002c28: 0ec12c83 lw s9,236(sp) -80002c2c: 0e812483 lw s1,232(sp) -80002c30: 10c10913 addi s2,sp,268 -80002c34: 891ff06f j 800024c4 <_vfprintf_r+0x10ac> -80002c38: 1b010b13 addi s6,sp,432 -80002c3c: 00000793 li a5,0 -80002c40: 00812823 sw s0,16(sp) -80002c44: 00912e23 sw s1,28(sp) -80002c48: 000b0413 mv s0,s6 -80002c4c: 03312223 sw s3,36(sp) -80002c50: 000c0b13 mv s6,s8 -80002c54: 00090493 mv s1,s2 -80002c58: 000c8993 mv s3,s9 -80002c5c: 400bfa13 andi s4,s7,1024 -80002c60: 03c12c83 lw s9,60(sp) -80002c64: 0ff00a93 li s5,255 -80002c68: 00088c13 mv s8,a7 -80002c6c: 00078913 mv s2,a5 -80002c70: 0240006f j 80002c94 <_vfprintf_r+0x187c> -80002c74: 00a00613 li a2,10 -80002c78: 00000693 li a3,0 -80002c7c: 00048513 mv a0,s1 -80002c80: 00098593 mv a1,s3 -80002c84: 0410d0ef jal ra,800104c4 <__udivdi3> -80002c88: 2a098ae3 beqz s3,8000373c <_vfprintf_r+0x2324> -80002c8c: 00050493 mv s1,a0 -80002c90: 00058993 mv s3,a1 -80002c94: 00a00613 li a2,10 -80002c98: 00000693 li a3,0 -80002c9c: 00048513 mv a0,s1 -80002ca0: 00098593 mv a1,s3 -80002ca4: 4550d0ef jal ra,800108f8 <__umoddi3> -80002ca8: 03050513 addi a0,a0,48 -80002cac: fea40fa3 sb a0,-1(s0) -80002cb0: 00190913 addi s2,s2,1 -80002cb4: fff40413 addi s0,s0,-1 -80002cb8: fa0a0ee3 beqz s4,80002c74 <_vfprintf_r+0x185c> -80002cbc: 000cc683 lbu a3,0(s9) -80002cc0: fad91ae3 bne s2,a3,80002c74 <_vfprintf_r+0x185c> -80002cc4: fb5908e3 beq s2,s5,80002c74 <_vfprintf_r+0x185c> -80002cc8: 4a099263 bnez s3,8000316c <_vfprintf_r+0x1d54> -80002ccc: 00900793 li a5,9 -80002cd0: 4897ee63 bltu a5,s1,8000316c <_vfprintf_r+0x1d54> -80002cd4: 000c0893 mv a7,s8 -80002cd8: 1b010793 addi a5,sp,432 -80002cdc: 000b0c13 mv s8,s6 -80002ce0: 00040b13 mv s6,s0 -80002ce4: 03912e23 sw s9,60(sp) -80002ce8: 01c12483 lw s1,28(sp) -80002cec: 02412983 lw s3,36(sp) -80002cf0: 01012403 lw s0,16(sp) -80002cf4: 03212023 sw s2,32(sp) -80002cf8: 41678cb3 sub s9,a5,s6 -80002cfc: 000b8a13 mv s4,s7 -80002d00: 9d4ff06f j 80001ed4 <_vfprintf_r+0xabc> -80002d04: 0e812683 lw a3,232(sp) -80002d08: 80015637 lui a2,0x80015 -80002d0c: ca860613 addi a2,a2,-856 # 80014ca8 <__BSS_END__+0xffffe06c> -80002d10: 00c8a023 sw a2,0(a7) -80002d14: 00178793 addi a5,a5,1 -80002d18: 00100613 li a2,1 -80002d1c: 00168693 addi a3,a3,1 -80002d20: 00c8a223 sw a2,4(a7) -80002d24: 0ef12623 sw a5,236(sp) -80002d28: 0ed12423 sw a3,232(sp) -80002d2c: 00700613 li a2,7 -80002d30: 00888893 addi a7,a7,8 -80002d34: 48d64463 blt a2,a3,800031bc <_vfprintf_r+0x1da4> -80002d38: 00058463 beqz a1,80002d40 <_vfprintf_r+0x1928> -80002d3c: eadfe06f j 80001be8 <_vfprintf_r+0x7d0> -80002d40: 02012703 lw a4,32(sp) -80002d44: 001a7693 andi a3,s4,1 -80002d48: 00e6e6b3 or a3,a3,a4 -80002d4c: 00069463 bnez a3,80002d54 <_vfprintf_r+0x193c> -80002d50: 9d1fe06f j 80001720 <_vfprintf_r+0x308> -80002d54: 03012683 lw a3,48(sp) -80002d58: 02c12703 lw a4,44(sp) -80002d5c: 00700613 li a2,7 -80002d60: 00d8a023 sw a3,0(a7) -80002d64: 0e812683 lw a3,232(sp) -80002d68: 00f707b3 add a5,a4,a5 -80002d6c: 00e8a223 sw a4,4(a7) -80002d70: 00168693 addi a3,a3,1 -80002d74: 0ef12623 sw a5,236(sp) -80002d78: 0ed12423 sw a3,232(sp) -80002d7c: 00d65463 bge a2,a3,80002d84 <_vfprintf_r+0x196c> -80002d80: e99fe06f j 80001c18 <_vfprintf_r+0x800> -80002d84: 00888893 addi a7,a7,8 -80002d88: ebdfe06f j 80001c44 <_vfprintf_r+0x82c> -80002d8c: 01012b83 lw s7,16(sp) -80002d90: 00040d13 mv s10,s0 -80002d94: 00048c13 mv s8,s1 -80002d98: eb4ff06f j 8000244c <_vfprintf_r+0x1034> -80002d9c: 040a7793 andi a5,s4,64 -80002da0: 14078063 beqz a5,80002ee0 <_vfprintf_r+0x1ac8> -80002da4: 01412783 lw a5,20(sp) -80002da8: 00000c93 li s9,0 -80002dac: 00e12a23 sw a4,20(sp) -80002db0: 0007d903 lhu s2,0(a5) -80002db4: d0dff06f j 80002ac0 <_vfprintf_r+0x16a8> -80002db8: 0e410613 addi a2,sp,228 -80002dbc: 000c0593 mv a1,s8 -80002dc0: 000d0513 mv a0,s10 -80002dc4: 7d4090ef jal ra,8000c598 <__sprint_r> -80002dc8: e8051063 bnez a0,80002448 <_vfprintf_r+0x1030> -80002dcc: 0ec12783 lw a5,236(sp) -80002dd0: 10c10893 addi a7,sp,268 -80002dd4: c3cff06f j 80002210 <_vfprintf_r+0xdf8> -80002dd8: 00812683 lw a3,8(sp) -80002ddc: 009787b3 add a5,a5,s1 -80002de0: 0098a223 sw s1,4(a7) -80002de4: 00d8a023 sw a3,0(a7) -80002de8: 00170713 addi a4,a4,1 -80002dec: 0ef12623 sw a5,236(sp) -80002df0: 0ee12423 sw a4,232(sp) -80002df4: 00700693 li a3,7 -80002df8: 00e6c463 blt a3,a4,80002e00 <_vfprintf_r+0x19e8> -80002dfc: 921fe06f j 8000171c <_vfprintf_r+0x304> -80002e00: e69fe06f j 80001c68 <_vfprintf_r+0x850> -80002e04: 0f012783 lw a5,240(sp) -80002e08: 0a010593 addi a1,sp,160 -80002e0c: 0b010513 addi a0,sp,176 -80002e10: 0af12823 sw a5,176(sp) -80002e14: 0f412783 lw a5,244(sp) -80002e18: 0a012023 sw zero,160(sp) -80002e1c: 0a012223 sw zero,164(sp) -80002e20: 0af12a23 sw a5,180(sp) -80002e24: 0f812783 lw a5,248(sp) -80002e28: 0a012423 sw zero,168(sp) -80002e2c: 0a012623 sw zero,172(sp) -80002e30: 0af12c23 sw a5,184(sp) -80002e34: 0fc12783 lw a5,252(sp) -80002e38: 0af12e23 sw a5,188(sp) -80002e3c: 5810e0ef jal ra,80011bbc <__letf2> -80002e40: 01012883 lw a7,16(sp) -80002e44: 260540e3 bltz a0,800038a4 <_vfprintf_r+0x248c> -80002e48: 0c714783 lbu a5,199(sp) -80002e4c: 04700713 li a4,71 -80002e50: 38975863 bge a4,s1,800031e0 <_vfprintf_r+0x1dc8> -80002e54: 80015737 lui a4,0x80015 -80002e58: c6c70b13 addi s6,a4,-916 # 80014c6c <__BSS_END__+0xffffe030> -80002e5c: 00012823 sw zero,16(sp) -80002e60: 02012423 sw zero,40(sp) -80002e64: 02012223 sw zero,36(sp) -80002e68: 00012e23 sw zero,28(sp) -80002e6c: f7fa7a13 andi s4,s4,-129 -80002e70: 00300a93 li s5,3 -80002e74: 00300c93 li s9,3 -80002e78: 00000d93 li s11,0 -80002e7c: 00078463 beqz a5,80002e84 <_vfprintf_r+0x1a6c> -80002e80: f75fe06f j 80001df4 <_vfprintf_r+0x9dc> -80002e84: fccfe06f j 80001650 <_vfprintf_r+0x238> -80002e88: 00c12783 lw a5,12(sp) -80002e8c: 00040b13 mv s6,s0 -80002e90: 00f72023 sw a5,0(a4) -80002e94: 8d5fe06f j 80001768 <_vfprintf_r+0x350> -80002e98: 000b0513 mv a0,s6 -80002e9c: 05912023 sw s9,64(sp) -80002ea0: 2c1060ef jal ra,80009960 -80002ea4: 0c714783 lbu a5,199(sp) -80002ea8: fff54a93 not s5,a0 -80002eac: 41fada93 srai s5,s5,0x1f -80002eb0: 01212a23 sw s2,20(sp) -80002eb4: 00012823 sw zero,16(sp) -80002eb8: 02012423 sw zero,40(sp) -80002ebc: 02012223 sw zero,36(sp) -80002ec0: 00012e23 sw zero,28(sp) -80002ec4: 04012883 lw a7,64(sp) -80002ec8: 00050c93 mv s9,a0 -80002ecc: 01557ab3 and s5,a0,s5 -80002ed0: 00000d93 li s11,0 -80002ed4: 00078463 beqz a5,80002edc <_vfprintf_r+0x1ac4> -80002ed8: f1dfe06f j 80001df4 <_vfprintf_r+0x9dc> -80002edc: f74fe06f j 80001650 <_vfprintf_r+0x238> -80002ee0: 200a7793 andi a5,s4,512 -80002ee4: 3a078263 beqz a5,80003288 <_vfprintf_r+0x1e70> -80002ee8: 01412783 lw a5,20(sp) -80002eec: 00000c93 li s9,0 -80002ef0: 00e12a23 sw a4,20(sp) -80002ef4: 0007c903 lbu s2,0(a5) -80002ef8: bc9ff06f j 80002ac0 <_vfprintf_r+0x16a8> -80002efc: 200bf793 andi a5,s7,512 -80002f00: 36078863 beqz a5,80003270 <_vfprintf_r+0x1e58> -80002f04: 01412783 lw a5,20(sp) -80002f08: 00000c93 li s9,0 -80002f0c: 00e12a23 sw a4,20(sp) -80002f10: 0007c903 lbu s2,0(a5) -80002f14: 00100793 li a5,1 -80002f18: f91fe06f j 80001ea8 <_vfprintf_r+0xa90> -80002f1c: 200a7793 andi a5,s4,512 -80002f20: 32078c63 beqz a5,80003258 <_vfprintf_r+0x1e40> -80002f24: 01412783 lw a5,20(sp) -80002f28: 00e12a23 sw a4,20(sp) -80002f2c: 00078903 lb s2,0(a5) -80002f30: 41f95c93 srai s9,s2,0x1f -80002f34: 000c8793 mv a5,s9 -80002f38: 928ff06f j 80002060 <_vfprintf_r+0xc48> -80002f3c: 200a7793 andi a5,s4,512 -80002f40: 30078263 beqz a5,80003244 <_vfprintf_r+0x1e2c> -80002f44: 01412783 lw a5,20(sp) -80002f48: 00000c93 li s9,0 -80002f4c: 00e12a23 sw a4,20(sp) -80002f50: 0007c903 lbu s2,0(a5) -80002f54: 890ff06f j 80001fe4 <_vfprintf_r+0xbcc> -80002f58: 0fc12783 lw a5,252(sp) -80002f5c: 3407ca63 bltz a5,800032b0 <_vfprintf_r+0x1e98> -80002f60: 0c714783 lbu a5,199(sp) -80002f64: 04700713 li a4,71 -80002f68: 1c975ce3 bge a4,s1,80003940 <_vfprintf_r+0x2528> -80002f6c: 80015737 lui a4,0x80015 -80002f70: c7470b13 addi s6,a4,-908 # 80014c74 <__BSS_END__+0xffffe038> -80002f74: ee9ff06f j 80002e5c <_vfprintf_r+0x1a44> -80002f78: 00812703 lw a4,8(sp) -80002f7c: 009787b3 add a5,a5,s1 -80002f80: 00168693 addi a3,a3,1 -80002f84: 00e8a023 sw a4,0(a7) -80002f88: 0098a223 sw s1,4(a7) -80002f8c: 0ef12623 sw a5,236(sp) -80002f90: 0ed12423 sw a3,232(sp) -80002f94: 00700613 li a2,7 -80002f98: 00888893 addi a7,a7,8 -80002f9c: f4d65463 bge a2,a3,800026e4 <_vfprintf_r+0x12cc> -80002fa0: 0e410613 addi a2,sp,228 -80002fa4: 000c0593 mv a1,s8 -80002fa8: 000d0513 mv a0,s10 -80002fac: 5ec090ef jal ra,8000c598 <__sprint_r> -80002fb0: c8051c63 bnez a0,80002448 <_vfprintf_r+0x1030> -80002fb4: 0ec12783 lw a5,236(sp) -80002fb8: 10c10893 addi a7,sp,268 -80002fbc: f28ff06f j 800026e4 <_vfprintf_r+0x12cc> -80002fc0: 02012703 lw a4,32(sp) -80002fc4: 02412c83 lw s9,36(sp) -80002fc8: 01412e23 sw s4,28(sp) -80002fcc: 04812023 sw s0,64(sp) -80002fd0: 05312223 sw s3,68(sp) -80002fd4: 03512223 sw s5,36(sp) -80002fd8: 02812983 lw s3,40(sp) -80002fdc: 03612423 sw s6,40(sp) -80002fe0: 00eb0bb3 add s7,s6,a4 -80002fe4: 03c12403 lw s0,60(sp) -80002fe8: 04812a03 lw s4,72(sp) -80002fec: 04c12a83 lw s5,76(sp) -80002ff0: 00700493 li s1,7 -80002ff4: 01000913 li s2,16 -80002ff8: 000c0b13 mv s6,s8 -80002ffc: 080c8863 beqz s9,8000308c <_vfprintf_r+0x1c74> -80003000: 08099863 bnez s3,80003090 <_vfprintf_r+0x1c78> -80003004: fff40413 addi s0,s0,-1 -80003008: fffc8c93 addi s9,s9,-1 -8000300c: 0e812703 lw a4,232(sp) -80003010: 014787b3 add a5,a5,s4 -80003014: 0158a023 sw s5,0(a7) -80003018: 00170713 addi a4,a4,1 -8000301c: 0148a223 sw s4,4(a7) -80003020: 0ef12623 sw a5,236(sp) -80003024: 0ee12423 sw a4,232(sp) -80003028: 00888893 addi a7,a7,8 -8000302c: 0ee4ce63 blt s1,a4,80003128 <_vfprintf_r+0x1d10> -80003030: 00044683 lbu a3,0(s0) -80003034: 41bb8633 sub a2,s7,s11 -80003038: 00068c13 mv s8,a3 -8000303c: 00d65463 bge a2,a3,80003044 <_vfprintf_r+0x1c2c> -80003040: 00060c13 mv s8,a2 -80003044: 03805663 blez s8,80003070 <_vfprintf_r+0x1c58> -80003048: 0e812683 lw a3,232(sp) -8000304c: 018787b3 add a5,a5,s8 -80003050: 01b8a023 sw s11,0(a7) -80003054: 00168693 addi a3,a3,1 -80003058: 0188a223 sw s8,4(a7) -8000305c: 0ef12623 sw a5,236(sp) -80003060: 0ed12423 sw a3,232(sp) -80003064: 0ed4c263 blt s1,a3,80003148 <_vfprintf_r+0x1d30> -80003068: 00044683 lbu a3,0(s0) -8000306c: 00888893 addi a7,a7,8 -80003070: fffc4613 not a2,s8 -80003074: 41f65613 srai a2,a2,0x1f -80003078: 00cc7733 and a4,s8,a2 -8000307c: 40e68c33 sub s8,a3,a4 -80003080: 01804c63 bgtz s8,80003098 <_vfprintf_r+0x1c80> -80003084: 00dd8db3 add s11,s11,a3 -80003088: f60c9ce3 bnez s9,80003000 <_vfprintf_r+0x1be8> -8000308c: 5e098a63 beqz s3,80003680 <_vfprintf_r+0x2268> -80003090: fff98993 addi s3,s3,-1 -80003094: f79ff06f j 8000300c <_vfprintf_r+0x1bf4> -80003098: 0e812683 lw a3,232(sp) -8000309c: 01894863 blt s2,s8,800030ac <_vfprintf_r+0x1c94> -800030a0: 0580006f j 800030f8 <_vfprintf_r+0x1ce0> -800030a4: ff0c0c13 addi s8,s8,-16 -800030a8: 05895863 bge s2,s8,800030f8 <_vfprintf_r+0x1ce0> -800030ac: 00812703 lw a4,8(sp) -800030b0: 01078793 addi a5,a5,16 -800030b4: 00168693 addi a3,a3,1 -800030b8: 00e8a023 sw a4,0(a7) -800030bc: 0128a223 sw s2,4(a7) -800030c0: 0ef12623 sw a5,236(sp) -800030c4: 0ed12423 sw a3,232(sp) -800030c8: 00888893 addi a7,a7,8 -800030cc: fcd4dce3 bge s1,a3,800030a4 <_vfprintf_r+0x1c8c> -800030d0: 0e410613 addi a2,sp,228 -800030d4: 000b0593 mv a1,s6 -800030d8: 000d0513 mv a0,s10 -800030dc: 4bc090ef jal ra,8000c598 <__sprint_r> -800030e0: 66051463 bnez a0,80003748 <_vfprintf_r+0x2330> -800030e4: ff0c0c13 addi s8,s8,-16 -800030e8: 0ec12783 lw a5,236(sp) -800030ec: 0e812683 lw a3,232(sp) -800030f0: 10c10893 addi a7,sp,268 -800030f4: fb894ce3 blt s2,s8,800030ac <_vfprintf_r+0x1c94> -800030f8: 00812703 lw a4,8(sp) -800030fc: 018787b3 add a5,a5,s8 -80003100: 00168693 addi a3,a3,1 -80003104: 00e8a023 sw a4,0(a7) -80003108: 0188a223 sw s8,4(a7) -8000310c: 0ef12623 sw a5,236(sp) -80003110: 0ed12423 sw a3,232(sp) -80003114: 66d4c063 blt s1,a3,80003774 <_vfprintf_r+0x235c> -80003118: 00044683 lbu a3,0(s0) -8000311c: 00888893 addi a7,a7,8 -80003120: 00dd8db3 add s11,s11,a3 -80003124: f65ff06f j 80003088 <_vfprintf_r+0x1c70> +800022b4: 10c10893 addi a7,sp,268 +800022b8: b6cff06f j 80001624 <_vfprintf_r+0x2d0> +800022bc: 01000613 li a2,16 +800022c0: 0e812683 lw a3,232(sp) +800022c4: 07b65263 bge a2,s11,80002328 <_vfprintf_r+0xfd4> +800022c8: 01000b93 li s7,16 +800022cc: 00700913 li s2,7 +800022d0: 00c0006f j 800022dc <_vfprintf_r+0xf88> +800022d4: ff0d8d93 addi s11,s11,-16 +800022d8: 05bbd863 bge s7,s11,80002328 <_vfprintf_r+0xfd4> +800022dc: 00812703 lw a4,8(sp) +800022e0: 01078793 addi a5,a5,16 +800022e4: 00168693 addi a3,a3,1 +800022e8: 00e8a023 sw a4,0(a7) +800022ec: 0178a223 sw s7,4(a7) +800022f0: 0ef12623 sw a5,236(sp) +800022f4: 0ed12423 sw a3,232(sp) +800022f8: 00888893 addi a7,a7,8 +800022fc: fcd95ce3 bge s2,a3,800022d4 <_vfprintf_r+0xf80> +80002300: 0e410613 addi a2,sp,228 +80002304: 000c0593 mv a1,s8 +80002308: 000d0513 mv a0,s10 +8000230c: 1c80a0ef jal ra,8000c4d4 <__sprint_r> +80002310: 06051a63 bnez a0,80002384 <_vfprintf_r+0x1030> +80002314: ff0d8d93 addi s11,s11,-16 +80002318: 0ec12783 lw a5,236(sp) +8000231c: 0e812683 lw a3,232(sp) +80002320: 10c10893 addi a7,sp,268 +80002324: fbbbcce3 blt s7,s11,800022dc <_vfprintf_r+0xf88> +80002328: 00812703 lw a4,8(sp) +8000232c: 01b787b3 add a5,a5,s11 +80002330: 00168693 addi a3,a3,1 +80002334: 00e8a023 sw a4,0(a7) +80002338: 01b8a223 sw s11,4(a7) +8000233c: 0ef12623 sw a5,236(sp) +80002340: 0ed12423 sw a3,232(sp) +80002344: 00700613 li a2,7 +80002348: 00888893 addi a7,a7,8 +8000234c: aed65063 bge a2,a3,8000162c <_vfprintf_r+0x2d8> +80002350: 0e410613 addi a2,sp,228 +80002354: 000c0593 mv a1,s8 +80002358: 000d0513 mv a0,s10 +8000235c: 1780a0ef jal ra,8000c4d4 <__sprint_r> +80002360: 02051263 bnez a0,80002384 <_vfprintf_r+0x1030> +80002364: 0ec12783 lw a5,236(sp) +80002368: 10c10893 addi a7,sp,268 +8000236c: ac0ff06f j 8000162c <_vfprintf_r+0x2d8> +80002370: 0e410613 addi a2,sp,228 +80002374: 000c0593 mv a1,s8 +80002378: 000d0513 mv a0,s10 +8000237c: 1580a0ef jal ra,8000c4d4 <__sprint_r> +80002380: b0050263 beqz a0,80001684 <_vfprintf_r+0x330> +80002384: 01012b83 lw s7,16(sp) +80002388: b20b8863 beqz s7,800016b8 <_vfprintf_r+0x364> +8000238c: 000b8593 mv a1,s7 +80002390: 000d0513 mv a0,s10 +80002394: 57c020ef jal ra,80004910 <_free_r> +80002398: b20ff06f j 800016b8 <_vfprintf_r+0x364> +8000239c: 0e812683 lw a3,232(sp) +800023a0: 00178c93 addi s9,a5,1 +800023a4: 02012783 lw a5,32(sp) +800023a8: 00100613 li a2,1 +800023ac: 0168a023 sw s6,0(a7) +800023b0: 00168493 addi s1,a3,1 +800023b4: 00888913 addi s2,a7,8 +800023b8: 38f65663 bge a2,a5,80002744 <_vfprintf_r+0x13f0> +800023bc: 00100793 li a5,1 +800023c0: 00f8a223 sw a5,4(a7) +800023c4: 0f912623 sw s9,236(sp) +800023c8: 0e912423 sw s1,232(sp) +800023cc: 00700793 li a5,7 +800023d0: 7497ce63 blt a5,s1,80002b2c <_vfprintf_r+0x17d8> +800023d4: 02c12783 lw a5,44(sp) +800023d8: 03012703 lw a4,48(sp) +800023dc: 00148493 addi s1,s1,1 +800023e0: 00fc8cb3 add s9,s9,a5 +800023e4: 00f92223 sw a5,4(s2) +800023e8: 00e92023 sw a4,0(s2) +800023ec: 0f912623 sw s9,236(sp) +800023f0: 0e912423 sw s1,232(sp) +800023f4: 00700793 li a5,7 +800023f8: 00890913 addi s2,s2,8 +800023fc: 7497ca63 blt a5,s1,80002b50 <_vfprintf_r+0x17fc> +80002400: 0f012783 lw a5,240(sp) +80002404: 00148613 addi a2,s1,1 +80002408: 0a010593 addi a1,sp,160 +8000240c: 0af12823 sw a5,176(sp) +80002410: 0f412783 lw a5,244(sp) +80002414: 0b010513 addi a0,sp,176 +80002418: 00c12e23 sw a2,28(sp) +8000241c: 0af12a23 sw a5,180(sp) +80002420: 0f812783 lw a5,248(sp) +80002424: 0a012023 sw zero,160(sp) +80002428: 0a012223 sw zero,164(sp) +8000242c: 0af12c23 sw a5,184(sp) +80002430: 0fc12783 lw a5,252(sp) +80002434: 0a012423 sw zero,168(sp) +80002438: 0a012623 sw zero,172(sp) +8000243c: 0af12e23 sw a5,188(sp) +80002440: 4a80f0ef jal ra,800118e8 <__eqtf2> +80002444: 01c12603 lw a2,28(sp) +80002448: 02012783 lw a5,32(sp) +8000244c: 00890893 addi a7,s2,8 +80002450: 00060693 mv a3,a2 +80002454: fff78d93 addi s11,a5,-1 +80002458: 30050a63 beqz a0,8000276c <_vfprintf_r+0x1418> +8000245c: 001b0713 addi a4,s6,1 +80002460: 01bc8cb3 add s9,s9,s11 +80002464: 00e92023 sw a4,0(s2) +80002468: 01b92223 sw s11,4(s2) +8000246c: 0f912623 sw s9,236(sp) +80002470: 0ec12423 sw a2,232(sp) +80002474: 00700793 li a5,7 +80002478: 50c7cc63 blt a5,a2,80002990 <_vfprintf_r+0x163c> +8000247c: 01090793 addi a5,s2,16 +80002480: 00248693 addi a3,s1,2 +80002484: 00088913 mv s2,a7 +80002488: 00078893 mv a7,a5 +8000248c: 03812603 lw a2,56(sp) +80002490: 0d410713 addi a4,sp,212 +80002494: 00e92023 sw a4,0(s2) +80002498: 019607b3 add a5,a2,s9 +8000249c: 00c92223 sw a2,4(s2) +800024a0: 0ef12623 sw a5,236(sp) +800024a4: 0ed12423 sw a3,232(sp) +800024a8: 00700713 li a4,7 +800024ac: 9ad75863 bge a4,a3,8000165c <_vfprintf_r+0x308> +800024b0: ef4ff06f j 80001ba4 <_vfprintf_r+0x850> +800024b4: 80015737 lui a4,0x80015 +800024b8: 01000613 li a2,16 +800024bc: 0e812683 lw a3,232(sp) +800024c0: d4470e93 addi t4,a4,-700 # 80014d44 <__BSS_END__+0xffffe108> +800024c4: 09065c63 bge a2,a6,8000255c <_vfprintf_r+0x1208> +800024c8: 04812023 sw s0,64(sp) +800024cc: 04912223 sw s1,68(sp) +800024d0: 000d0413 mv s0,s10 +800024d4: 000c0493 mv s1,s8 +800024d8: 01000e13 li t3,16 +800024dc: 00700293 li t0,7 +800024e0: 00080c13 mv s8,a6 +800024e4: 000e8d13 mv s10,t4 +800024e8: 00c0006f j 800024f4 <_vfprintf_r+0x11a0> +800024ec: ff0c0c13 addi s8,s8,-16 +800024f0: 058e5a63 bge t3,s8,80002544 <_vfprintf_r+0x11f0> +800024f4: 01078793 addi a5,a5,16 +800024f8: 00168693 addi a3,a3,1 +800024fc: 01a8a023 sw s10,0(a7) +80002500: 01c8a223 sw t3,4(a7) +80002504: 0ef12623 sw a5,236(sp) +80002508: 0ed12423 sw a3,232(sp) +8000250c: 00888893 addi a7,a7,8 +80002510: fcd2dee3 bge t0,a3,800024ec <_vfprintf_r+0x1198> +80002514: 0e410613 addi a2,sp,228 +80002518: 00048593 mv a1,s1 +8000251c: 00040513 mv a0,s0 +80002520: 7b5090ef jal ra,8000c4d4 <__sprint_r> +80002524: 7a051263 bnez a0,80002cc8 <_vfprintf_r+0x1974> +80002528: 01000e13 li t3,16 +8000252c: ff0c0c13 addi s8,s8,-16 +80002530: 0ec12783 lw a5,236(sp) +80002534: 0e812683 lw a3,232(sp) +80002538: 10c10893 addi a7,sp,268 +8000253c: 00700293 li t0,7 +80002540: fb8e4ae3 blt t3,s8,800024f4 <_vfprintf_r+0x11a0> +80002544: 000c0813 mv a6,s8 +80002548: 000d0e93 mv t4,s10 +8000254c: 00048c13 mv s8,s1 +80002550: 00040d13 mv s10,s0 +80002554: 04412483 lw s1,68(sp) +80002558: 04012403 lw s0,64(sp) +8000255c: 010787b3 add a5,a5,a6 +80002560: 00168693 addi a3,a3,1 +80002564: 01d8a023 sw t4,0(a7) +80002568: 0108a223 sw a6,4(a7) +8000256c: 0ef12623 sw a5,236(sp) +80002570: 0ed12423 sw a3,232(sp) +80002574: 00700613 li a2,7 +80002578: 00888893 addi a7,a7,8 +8000257c: 00d64463 blt a2,a3,80002584 <_vfprintf_r+0x1230> +80002580: 82cff06f j 800015ac <_vfprintf_r+0x258> +80002584: 0e410613 addi a2,sp,228 +80002588: 000c0593 mv a1,s8 +8000258c: 000d0513 mv a0,s10 +80002590: 745090ef jal ra,8000c4d4 <__sprint_r> +80002594: de0518e3 bnez a0,80002384 <_vfprintf_r+0x1030> +80002598: 0ec12783 lw a5,236(sp) +8000259c: 10c10893 addi a7,sp,268 +800025a0: 80cff06f j 800015ac <_vfprintf_r+0x258> +800025a4: 0e410613 addi a2,sp,228 +800025a8: 000c0593 mv a1,s8 +800025ac: 000d0513 mv a0,s10 +800025b0: 725090ef jal ra,8000c4d4 <__sprint_r> +800025b4: dc0518e3 bnez a0,80002384 <_vfprintf_r+0x1030> +800025b8: 0ec12783 lw a5,236(sp) +800025bc: 10c10893 addi a7,sp,268 +800025c0: 85cff06f j 8000161c <_vfprintf_r+0x2c8> +800025c4: 0cc12583 lw a1,204(sp) +800025c8: 66b05c63 blez a1,80002c40 <_vfprintf_r+0x18ec> +800025cc: 01c12703 lw a4,28(sp) +800025d0: 02012683 lw a3,32(sp) +800025d4: 00070493 mv s1,a4 +800025d8: 38e6c263 blt a3,a4,8000295c <_vfprintf_r+0x1608> +800025dc: 02905663 blez s1,80002608 <_vfprintf_r+0x12b4> +800025e0: 0e812683 lw a3,232(sp) +800025e4: 009787b3 add a5,a5,s1 +800025e8: 0168a023 sw s6,0(a7) +800025ec: 00168693 addi a3,a3,1 +800025f0: 0098a223 sw s1,4(a7) +800025f4: 0ef12623 sw a5,236(sp) +800025f8: 0ed12423 sw a3,232(sp) +800025fc: 00700613 li a2,7 +80002600: 00888893 addi a7,a7,8 +80002604: 32d642e3 blt a2,a3,80003128 <_vfprintf_r+0x1dd4> +80002608: fff4c693 not a3,s1 +8000260c: 01c12703 lw a4,28(sp) +80002610: 41f6d693 srai a3,a3,0x1f +80002614: 00d4f4b3 and s1,s1,a3 +80002618: 409704b3 sub s1,a4,s1 +8000261c: 48904463 bgtz s1,80002aa4 <_vfprintf_r+0x1750> +80002620: 01c12703 lw a4,28(sp) +80002624: 400a7693 andi a3,s4,1024 +80002628: 00eb0db3 add s11,s6,a4 +8000262c: 0c0698e3 bnez a3,80002efc <_vfprintf_r+0x1ba8> +80002630: 0cc12483 lw s1,204(sp) +80002634: 02012703 lw a4,32(sp) +80002638: 00e4c663 blt s1,a4,80002644 <_vfprintf_r+0x12f0> +8000263c: 001a7693 andi a3,s4,1 +80002640: 300688e3 beqz a3,80003150 <_vfprintf_r+0x1dfc> +80002644: 03012683 lw a3,48(sp) +80002648: 02c12703 lw a4,44(sp) +8000264c: 00700613 li a2,7 +80002650: 00d8a023 sw a3,0(a7) +80002654: 0e812683 lw a3,232(sp) +80002658: 00e787b3 add a5,a5,a4 +8000265c: 00e8a223 sw a4,4(a7) +80002660: 00168693 addi a3,a3,1 +80002664: 0ef12623 sw a5,236(sp) +80002668: 0ed12423 sw a3,232(sp) +8000266c: 00888893 addi a7,a7,8 +80002670: 00d65463 bge a2,a3,80002678 <_vfprintf_r+0x1324> +80002674: 1780106f j 800037ec <_vfprintf_r+0x2498> +80002678: 02012683 lw a3,32(sp) +8000267c: 00db0733 add a4,s6,a3 +80002680: 409684b3 sub s1,a3,s1 +80002684: 41b70733 sub a4,a4,s11 +80002688: 00048913 mv s2,s1 +8000268c: 00975463 bge a4,s1,80002694 <_vfprintf_r+0x1340> +80002690: 00070913 mv s2,a4 +80002694: 03205863 blez s2,800026c4 <_vfprintf_r+0x1370> +80002698: 0e812703 lw a4,232(sp) +8000269c: 012787b3 add a5,a5,s2 +800026a0: 01b8a023 sw s11,0(a7) +800026a4: 00170713 addi a4,a4,1 +800026a8: 0128a223 sw s2,4(a7) +800026ac: 0ef12623 sw a5,236(sp) +800026b0: 0ee12423 sw a4,232(sp) +800026b4: 00700693 li a3,7 +800026b8: 00888893 addi a7,a7,8 +800026bc: 00e6d463 bge a3,a4,800026c4 <_vfprintf_r+0x1370> +800026c0: 1c80106f j 80003888 <_vfprintf_r+0x2534> +800026c4: fff94713 not a4,s2 +800026c8: 41f75713 srai a4,a4,0x1f +800026cc: 00e97733 and a4,s2,a4 +800026d0: 40e484b3 sub s1,s1,a4 +800026d4: 00904463 bgtz s1,800026dc <_vfprintf_r+0x1388> +800026d8: f85fe06f j 8000165c <_vfprintf_r+0x308> +800026dc: 01000693 li a3,16 +800026e0: 0e812703 lw a4,232(sp) +800026e4: 6296d863 bge a3,s1,80002d14 <_vfprintf_r+0x19c0> +800026e8: 01000913 li s2,16 +800026ec: 00700c93 li s9,7 +800026f0: 00c0006f j 800026fc <_vfprintf_r+0x13a8> +800026f4: ff048493 addi s1,s1,-16 +800026f8: 60995e63 bge s2,s1,80002d14 <_vfprintf_r+0x19c0> +800026fc: 00812683 lw a3,8(sp) +80002700: 01078793 addi a5,a5,16 +80002704: 00170713 addi a4,a4,1 +80002708: 00d8a023 sw a3,0(a7) +8000270c: 0128a223 sw s2,4(a7) +80002710: 0ef12623 sw a5,236(sp) +80002714: 0ee12423 sw a4,232(sp) +80002718: 00888893 addi a7,a7,8 +8000271c: fcecdce3 bge s9,a4,800026f4 <_vfprintf_r+0x13a0> +80002720: 0e410613 addi a2,sp,228 +80002724: 000c0593 mv a1,s8 +80002728: 000d0513 mv a0,s10 +8000272c: 5a9090ef jal ra,8000c4d4 <__sprint_r> +80002730: c4051ae3 bnez a0,80002384 <_vfprintf_r+0x1030> +80002734: 0ec12783 lw a5,236(sp) +80002738: 0e812703 lw a4,232(sp) +8000273c: 10c10893 addi a7,sp,268 +80002740: fb5ff06f j 800026f4 <_vfprintf_r+0x13a0> +80002744: 001a7793 andi a5,s4,1 +80002748: c6079ae3 bnez a5,800023bc <_vfprintf_r+0x1068> +8000274c: 00c8a223 sw a2,4(a7) +80002750: 0f912623 sw s9,236(sp) +80002754: 0e912423 sw s1,232(sp) +80002758: 00700793 li a5,7 +8000275c: 2297ca63 blt a5,s1,80002990 <_vfprintf_r+0x163c> +80002760: 00268693 addi a3,a3,2 +80002764: 01088893 addi a7,a7,16 +80002768: d25ff06f j 8000248c <_vfprintf_r+0x1138> +8000276c: d3b050e3 blez s11,8000248c <_vfprintf_r+0x1138> +80002770: 01000713 li a4,16 +80002774: 01b74463 blt a4,s11,8000277c <_vfprintf_r+0x1428> +80002778: 6180106f j 80003d90 <_vfprintf_r+0x2a3c> +8000277c: 00700b13 li s6,7 +80002780: 00060493 mv s1,a2 +80002784: 0100006f j 80002794 <_vfprintf_r+0x1440> +80002788: ff0d8d93 addi s11,s11,-16 +8000278c: 1db75e63 bge a4,s11,80002968 <_vfprintf_r+0x1614> +80002790: 00148493 addi s1,s1,1 +80002794: 00812783 lw a5,8(sp) +80002798: 010c8c93 addi s9,s9,16 +8000279c: 00e92223 sw a4,4(s2) +800027a0: 00f92023 sw a5,0(s2) +800027a4: 0f912623 sw s9,236(sp) +800027a8: 0e912423 sw s1,232(sp) +800027ac: 00890913 addi s2,s2,8 +800027b0: fc9b5ce3 bge s6,s1,80002788 <_vfprintf_r+0x1434> +800027b4: 0e410613 addi a2,sp,228 +800027b8: 000c0593 mv a1,s8 +800027bc: 000d0513 mv a0,s10 +800027c0: 515090ef jal ra,8000c4d4 <__sprint_r> +800027c4: bc0510e3 bnez a0,80002384 <_vfprintf_r+0x1030> +800027c8: 0ec12c83 lw s9,236(sp) +800027cc: 0e812483 lw s1,232(sp) +800027d0: 10c10913 addi s2,sp,268 +800027d4: 01000713 li a4,16 +800027d8: fb1ff06f j 80002788 <_vfprintf_r+0x1434> +800027dc: 01412683 lw a3,20(sp) +800027e0: 010a7793 andi a5,s4,16 +800027e4: 00468713 addi a4,a3,4 +800027e8: 16079263 bnez a5,8000294c <_vfprintf_r+0x15f8> +800027ec: 040a7793 andi a5,s4,64 +800027f0: 68078463 beqz a5,80002e78 <_vfprintf_r+0x1b24> +800027f4: 01412783 lw a5,20(sp) +800027f8: 00000c93 li s9,0 +800027fc: 00e12a23 sw a4,20(sp) +80002800: 0007d903 lhu s2,0(a5) +80002804: f1cff06f j 80001f20 <_vfprintf_r+0xbcc> +80002808: 01412683 lw a3,20(sp) +8000280c: 010bf793 andi a5,s7,16 +80002810: 00468713 addi a4,a3,4 +80002814: 0c079e63 bnez a5,800028f0 <_vfprintf_r+0x159c> +80002818: 040bf793 andi a5,s7,64 +8000281c: 60078e63 beqz a5,80002e38 <_vfprintf_r+0x1ae4> +80002820: 01412783 lw a5,20(sp) +80002824: 00000c93 li s9,0 +80002828: 00e12a23 sw a4,20(sp) +8000282c: 0007d903 lhu s2,0(a5) +80002830: 00100793 li a5,1 +80002834: db0ff06f j 80001de4 <_vfprintf_r+0xa90> +80002838: 01412683 lw a3,20(sp) +8000283c: 010a7793 andi a5,s4,16 +80002840: 00468713 addi a4,a3,4 +80002844: 0e079a63 bnez a5,80002938 <_vfprintf_r+0x15e4> +80002848: 040a7793 andi a5,s4,64 +8000284c: 60078663 beqz a5,80002e58 <_vfprintf_r+0x1b04> +80002850: 01412783 lw a5,20(sp) +80002854: 00e12a23 sw a4,20(sp) +80002858: 00079903 lh s2,0(a5) +8000285c: 41f95c93 srai s9,s2,0x1f +80002860: 000c8793 mv a5,s9 +80002864: f207de63 bgez a5,80001fa0 <_vfprintf_r+0xc4c> +80002868: 012037b3 snez a5,s2 +8000286c: 41900cb3 neg s9,s9 +80002870: 40fc8cb3 sub s9,s9,a5 +80002874: 02d00793 li a5,45 +80002878: 0cf103a3 sb a5,199(sp) +8000287c: 41200933 neg s2,s2 +80002880: 000a0b93 mv s7,s4 +80002884: 00100793 li a5,1 +80002888: d60ff06f j 80001de8 <_vfprintf_r+0xa94> +8000288c: 001a7713 andi a4,s4,1 +80002890: 00071463 bnez a4,80002898 <_vfprintf_r+0x1544> +80002894: dc9fe06f j 8000165c <_vfprintf_r+0x308> +80002898: 8c1ff06f j 80002158 <_vfprintf_r+0xe04> +8000289c: 000c8893 mv a7,s9 +800028a0: ed4ff06f j 80001f74 <_vfprintf_r+0xc20> +800028a4: 03000793 li a5,48 +800028a8: 1af107a3 sb a5,431(sp) +800028ac: 1af10b13 addi s6,sp,431 +800028b0: d60ff06f j 80001e10 <_vfprintf_r+0xabc> +800028b4: 03c12783 lw a5,60(sp) +800028b8: 00044483 lbu s1,0(s0) +800028bc: 00079463 bnez a5,800028c4 <_vfprintf_r+0x1570> +800028c0: c4dfe06f j 8000150c <_vfprintf_r+0x1b8> +800028c4: 0007c783 lbu a5,0(a5) +800028c8: 00079463 bnez a5,800028d0 <_vfprintf_r+0x157c> +800028cc: c41fe06f j 8000150c <_vfprintf_r+0x1b8> +800028d0: 400a6a13 ori s4,s4,1024 +800028d4: c39fe06f j 8000150c <_vfprintf_r+0x1b8> +800028d8: 00c12683 lw a3,12(sp) +800028dc: 00040b13 mv s6,s0 +800028e0: 41f6d793 srai a5,a3,0x1f +800028e4: 00d72023 sw a3,0(a4) +800028e8: 00f72223 sw a5,4(a4) +800028ec: db9fe06f j 800016a4 <_vfprintf_r+0x350> +800028f0: 0006a903 lw s2,0(a3) +800028f4: 00000c93 li s9,0 +800028f8: 00e12a23 sw a4,20(sp) +800028fc: 00100793 li a5,1 +80002900: ce4ff06f j 80001de4 <_vfprintf_r+0xa90> +80002904: 01412703 lw a4,20(sp) +80002908: 00072783 lw a5,0(a4) +8000290c: 00470713 addi a4,a4,4 +80002910: 00e12a23 sw a4,20(sp) +80002914: 0007a583 lw a1,0(a5) +80002918: 0047a603 lw a2,4(a5) +8000291c: 0087a683 lw a3,8(a5) +80002920: 00c7a783 lw a5,12(a5) +80002924: 0eb12823 sw a1,240(sp) +80002928: 0ec12a23 sw a2,244(sp) +8000292c: 0ed12c23 sw a3,248(sp) +80002930: 0ef12e23 sw a5,252(sp) +80002934: ef5fe06f j 80001828 <_vfprintf_r+0x4d4> +80002938: 0006a903 lw s2,0(a3) +8000293c: 00e12a23 sw a4,20(sp) +80002940: 41f95c93 srai s9,s2,0x1f +80002944: 000c8793 mv a5,s9 +80002948: e54ff06f j 80001f9c <_vfprintf_r+0xc48> +8000294c: 0006a903 lw s2,0(a3) +80002950: 00000c93 li s9,0 +80002954: 00e12a23 sw a4,20(sp) +80002958: dc8ff06f j 80001f20 <_vfprintf_r+0xbcc> +8000295c: 00068493 mv s1,a3 +80002960: c89040e3 bgtz s1,800025e0 <_vfprintf_r+0x128c> +80002964: ca5ff06f j 80002608 <_vfprintf_r+0x12b4> +80002968: 00148693 addi a3,s1,1 +8000296c: 00890713 addi a4,s2,8 +80002970: 00812783 lw a5,8(sp) +80002974: 01bc8cb3 add s9,s9,s11 +80002978: 01b92223 sw s11,4(s2) +8000297c: 00f92023 sw a5,0(s2) +80002980: 0f912623 sw s9,236(sp) +80002984: 0ed12423 sw a3,232(sp) +80002988: 00700793 li a5,7 +8000298c: 74d7de63 bge a5,a3,800030e8 <_vfprintf_r+0x1d94> +80002990: 0e410613 addi a2,sp,228 +80002994: 000c0593 mv a1,s8 +80002998: 000d0513 mv a0,s10 +8000299c: 339090ef jal ra,8000c4d4 <__sprint_r> +800029a0: 9e0512e3 bnez a0,80002384 <_vfprintf_r+0x1030> +800029a4: 0e812683 lw a3,232(sp) +800029a8: 0ec12c83 lw s9,236(sp) +800029ac: 11410893 addi a7,sp,276 +800029b0: 00168693 addi a3,a3,1 +800029b4: 10c10913 addi s2,sp,268 +800029b8: ad5ff06f j 8000248c <_vfprintf_r+0x1138> +800029bc: 000c8893 mv a7,s9 +800029c0: 000a0b93 mv s7,s4 +800029c4: d70ff06f j 80001f34 <_vfprintf_r+0xbe0> +800029c8: 800157b7 lui a5,0x80015 +800029cc: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +800029d0: 000c8893 mv a7,s9 +800029d4: 02f12a23 sw a5,52(sp) +800029d8: 020a7793 andi a5,s4,32 +800029dc: 12078863 beqz a5,80002b0c <_vfprintf_r+0x17b8> +800029e0: 01412783 lw a5,20(sp) +800029e4: 00778b13 addi s6,a5,7 +800029e8: ff8b7b13 andi s6,s6,-8 +800029ec: 000b2903 lw s2,0(s6) +800029f0: 004b2c83 lw s9,4(s6) +800029f4: 008b0793 addi a5,s6,8 +800029f8: 00f12a23 sw a5,20(sp) +800029fc: 001a7793 andi a5,s4,1 +80002a00: 00078e63 beqz a5,80002a1c <_vfprintf_r+0x16c8> +80002a04: 019967b3 or a5,s2,s9 +80002a08: 00078a63 beqz a5,80002a1c <_vfprintf_r+0x16c8> +80002a0c: 03000793 li a5,48 +80002a10: 0cf10423 sb a5,200(sp) +80002a14: 0c9104a3 sb s1,201(sp) +80002a18: 002a6a13 ori s4,s4,2 +80002a1c: bffa7b93 andi s7,s4,-1025 +80002a20: 00200793 li a5,2 +80002a24: bc0ff06f j 80001de4 <_vfprintf_r+0xa90> +80002a28: 800157b7 lui a5,0x80015 +80002a2c: bb878793 addi a5,a5,-1096 # 80014bb8 <__BSS_END__+0xffffdf7c> +80002a30: 000c8893 mv a7,s9 +80002a34: 02f12a23 sw a5,52(sp) +80002a38: fa1ff06f j 800029d8 <_vfprintf_r+0x1684> +80002a3c: 000c8893 mv a7,s9 +80002a40: cbcff06f j 80001efc <_vfprintf_r+0xba8> +80002a44: 0e410613 addi a2,sp,228 +80002a48: 000c0593 mv a1,s8 +80002a4c: 000d0513 mv a0,s10 +80002a50: 285090ef jal ra,8000c4d4 <__sprint_r> +80002a54: 920518e3 bnez a0,80002384 <_vfprintf_r+0x1030> +80002a58: 0ec12783 lw a5,236(sp) +80002a5c: 10c10893 addi a7,sp,268 +80002a60: f28ff06f j 80002188 <_vfprintf_r+0xe34> +80002a64: 00144483 lbu s1,1(s0) +80002a68: 020a6a13 ori s4,s4,32 +80002a6c: 00140413 addi s0,s0,1 +80002a70: a9dfe06f j 8000150c <_vfprintf_r+0x1b8> +80002a74: 00144483 lbu s1,1(s0) +80002a78: 200a6a13 ori s4,s4,512 +80002a7c: 00140413 addi s0,s0,1 +80002a80: a8dfe06f j 8000150c <_vfprintf_r+0x1b8> +80002a84: 00600793 li a5,6 +80002a88: 000d8c93 mv s9,s11 +80002a8c: 6bb7ee63 bltu a5,s11,80003148 <_vfprintf_r+0x1df4> +80002a90: 80015737 lui a4,0x80015 +80002a94: 000c8a93 mv s5,s9 +80002a98: 01212a23 sw s2,20(sp) +80002a9c: bcc70b13 addi s6,a4,-1076 # 80014bcc <__BSS_END__+0xffffdf90> +80002aa0: ad9fe06f j 80001578 <_vfprintf_r+0x224> +80002aa4: 01000613 li a2,16 +80002aa8: 0e812683 lw a3,232(sp) +80002aac: 40965463 bge a2,s1,80002eb4 <_vfprintf_r+0x1b60> +80002ab0: 01000c93 li s9,16 +80002ab4: 00700d93 li s11,7 +80002ab8: 00c0006f j 80002ac4 <_vfprintf_r+0x1770> +80002abc: ff048493 addi s1,s1,-16 +80002ac0: 3e9cda63 bge s9,s1,80002eb4 <_vfprintf_r+0x1b60> +80002ac4: 00812703 lw a4,8(sp) +80002ac8: 01078793 addi a5,a5,16 +80002acc: 00168693 addi a3,a3,1 +80002ad0: 00e8a023 sw a4,0(a7) +80002ad4: 0198a223 sw s9,4(a7) +80002ad8: 0ef12623 sw a5,236(sp) +80002adc: 0ed12423 sw a3,232(sp) +80002ae0: 00888893 addi a7,a7,8 +80002ae4: fcdddce3 bge s11,a3,80002abc <_vfprintf_r+0x1768> +80002ae8: 0e410613 addi a2,sp,228 +80002aec: 000c0593 mv a1,s8 +80002af0: 000d0513 mv a0,s10 +80002af4: 1e1090ef jal ra,8000c4d4 <__sprint_r> +80002af8: 880516e3 bnez a0,80002384 <_vfprintf_r+0x1030> +80002afc: 0ec12783 lw a5,236(sp) +80002b00: 0e812683 lw a3,232(sp) +80002b04: 10c10893 addi a7,sp,268 +80002b08: fb5ff06f j 80002abc <_vfprintf_r+0x1768> +80002b0c: 01412683 lw a3,20(sp) +80002b10: 010a7793 andi a5,s4,16 +80002b14: 00468713 addi a4,a3,4 +80002b18: 1c078063 beqz a5,80002cd8 <_vfprintf_r+0x1984> +80002b1c: 0006a903 lw s2,0(a3) +80002b20: 00000c93 li s9,0 +80002b24: 00e12a23 sw a4,20(sp) +80002b28: ed5ff06f j 800029fc <_vfprintf_r+0x16a8> +80002b2c: 0e410613 addi a2,sp,228 +80002b30: 000c0593 mv a1,s8 +80002b34: 000d0513 mv a0,s10 +80002b38: 19d090ef jal ra,8000c4d4 <__sprint_r> +80002b3c: 840514e3 bnez a0,80002384 <_vfprintf_r+0x1030> +80002b40: 0ec12c83 lw s9,236(sp) +80002b44: 0e812483 lw s1,232(sp) +80002b48: 10c10913 addi s2,sp,268 +80002b4c: 889ff06f j 800023d4 <_vfprintf_r+0x1080> +80002b50: 0e410613 addi a2,sp,228 +80002b54: 000c0593 mv a1,s8 +80002b58: 000d0513 mv a0,s10 +80002b5c: 179090ef jal ra,8000c4d4 <__sprint_r> +80002b60: 820512e3 bnez a0,80002384 <_vfprintf_r+0x1030> +80002b64: 0ec12c83 lw s9,236(sp) +80002b68: 0e812483 lw s1,232(sp) +80002b6c: 10c10913 addi s2,sp,268 +80002b70: 891ff06f j 80002400 <_vfprintf_r+0x10ac> +80002b74: 1b010b13 addi s6,sp,432 +80002b78: 00000793 li a5,0 +80002b7c: 00812823 sw s0,16(sp) +80002b80: 00912e23 sw s1,28(sp) +80002b84: 000b0413 mv s0,s6 +80002b88: 03312223 sw s3,36(sp) +80002b8c: 000c0b13 mv s6,s8 +80002b90: 00090493 mv s1,s2 +80002b94: 000c8993 mv s3,s9 +80002b98: 400bfa13 andi s4,s7,1024 +80002b9c: 03c12c83 lw s9,60(sp) +80002ba0: 0ff00a93 li s5,255 +80002ba4: 00088c13 mv s8,a7 +80002ba8: 00078913 mv s2,a5 +80002bac: 0240006f j 80002bd0 <_vfprintf_r+0x187c> +80002bb0: 00a00613 li a2,10 +80002bb4: 00000693 li a3,0 +80002bb8: 00048513 mv a0,s1 +80002bbc: 00098593 mv a1,s3 +80002bc0: 0410d0ef jal ra,80010400 <__udivdi3> +80002bc4: 2a098ae3 beqz s3,80003678 <_vfprintf_r+0x2324> +80002bc8: 00050493 mv s1,a0 +80002bcc: 00058993 mv s3,a1 +80002bd0: 00a00613 li a2,10 +80002bd4: 00000693 li a3,0 +80002bd8: 00048513 mv a0,s1 +80002bdc: 00098593 mv a1,s3 +80002be0: 4550d0ef jal ra,80010834 <__umoddi3> +80002be4: 03050513 addi a0,a0,48 +80002be8: fea40fa3 sb a0,-1(s0) +80002bec: 00190913 addi s2,s2,1 +80002bf0: fff40413 addi s0,s0,-1 +80002bf4: fa0a0ee3 beqz s4,80002bb0 <_vfprintf_r+0x185c> +80002bf8: 000cc683 lbu a3,0(s9) +80002bfc: fad91ae3 bne s2,a3,80002bb0 <_vfprintf_r+0x185c> +80002c00: fb5908e3 beq s2,s5,80002bb0 <_vfprintf_r+0x185c> +80002c04: 4a099263 bnez s3,800030a8 <_vfprintf_r+0x1d54> +80002c08: 00900793 li a5,9 +80002c0c: 4897ee63 bltu a5,s1,800030a8 <_vfprintf_r+0x1d54> +80002c10: 000c0893 mv a7,s8 +80002c14: 1b010793 addi a5,sp,432 +80002c18: 000b0c13 mv s8,s6 +80002c1c: 00040b13 mv s6,s0 +80002c20: 03912e23 sw s9,60(sp) +80002c24: 01c12483 lw s1,28(sp) +80002c28: 02412983 lw s3,36(sp) +80002c2c: 01012403 lw s0,16(sp) +80002c30: 03212023 sw s2,32(sp) +80002c34: 41678cb3 sub s9,a5,s6 +80002c38: 000b8a13 mv s4,s7 +80002c3c: 9d4ff06f j 80001e10 <_vfprintf_r+0xabc> +80002c40: 0e812683 lw a3,232(sp) +80002c44: 80015637 lui a2,0x80015 +80002c48: bd460613 addi a2,a2,-1068 # 80014bd4 <__BSS_END__+0xffffdf98> +80002c4c: 00c8a023 sw a2,0(a7) +80002c50: 00178793 addi a5,a5,1 +80002c54: 00100613 li a2,1 +80002c58: 00168693 addi a3,a3,1 +80002c5c: 00c8a223 sw a2,4(a7) +80002c60: 0ef12623 sw a5,236(sp) +80002c64: 0ed12423 sw a3,232(sp) +80002c68: 00700613 li a2,7 +80002c6c: 00888893 addi a7,a7,8 +80002c70: 48d64463 blt a2,a3,800030f8 <_vfprintf_r+0x1da4> +80002c74: 00058463 beqz a1,80002c7c <_vfprintf_r+0x1928> +80002c78: eadfe06f j 80001b24 <_vfprintf_r+0x7d0> +80002c7c: 02012703 lw a4,32(sp) +80002c80: 001a7693 andi a3,s4,1 +80002c84: 00e6e6b3 or a3,a3,a4 +80002c88: 00069463 bnez a3,80002c90 <_vfprintf_r+0x193c> +80002c8c: 9d1fe06f j 8000165c <_vfprintf_r+0x308> +80002c90: 03012683 lw a3,48(sp) +80002c94: 02c12703 lw a4,44(sp) +80002c98: 00700613 li a2,7 +80002c9c: 00d8a023 sw a3,0(a7) +80002ca0: 0e812683 lw a3,232(sp) +80002ca4: 00f707b3 add a5,a4,a5 +80002ca8: 00e8a223 sw a4,4(a7) +80002cac: 00168693 addi a3,a3,1 +80002cb0: 0ef12623 sw a5,236(sp) +80002cb4: 0ed12423 sw a3,232(sp) +80002cb8: 00d65463 bge a2,a3,80002cc0 <_vfprintf_r+0x196c> +80002cbc: e99fe06f j 80001b54 <_vfprintf_r+0x800> +80002cc0: 00888893 addi a7,a7,8 +80002cc4: ebdfe06f j 80001b80 <_vfprintf_r+0x82c> +80002cc8: 01012b83 lw s7,16(sp) +80002ccc: 00040d13 mv s10,s0 +80002cd0: 00048c13 mv s8,s1 +80002cd4: eb4ff06f j 80002388 <_vfprintf_r+0x1034> +80002cd8: 040a7793 andi a5,s4,64 +80002cdc: 14078063 beqz a5,80002e1c <_vfprintf_r+0x1ac8> +80002ce0: 01412783 lw a5,20(sp) +80002ce4: 00000c93 li s9,0 +80002ce8: 00e12a23 sw a4,20(sp) +80002cec: 0007d903 lhu s2,0(a5) +80002cf0: d0dff06f j 800029fc <_vfprintf_r+0x16a8> +80002cf4: 0e410613 addi a2,sp,228 +80002cf8: 000c0593 mv a1,s8 +80002cfc: 000d0513 mv a0,s10 +80002d00: 7d4090ef jal ra,8000c4d4 <__sprint_r> +80002d04: e8051063 bnez a0,80002384 <_vfprintf_r+0x1030> +80002d08: 0ec12783 lw a5,236(sp) +80002d0c: 10c10893 addi a7,sp,268 +80002d10: c3cff06f j 8000214c <_vfprintf_r+0xdf8> +80002d14: 00812683 lw a3,8(sp) +80002d18: 009787b3 add a5,a5,s1 +80002d1c: 0098a223 sw s1,4(a7) +80002d20: 00d8a023 sw a3,0(a7) +80002d24: 00170713 addi a4,a4,1 +80002d28: 0ef12623 sw a5,236(sp) +80002d2c: 0ee12423 sw a4,232(sp) +80002d30: 00700693 li a3,7 +80002d34: 00e6c463 blt a3,a4,80002d3c <_vfprintf_r+0x19e8> +80002d38: 921fe06f j 80001658 <_vfprintf_r+0x304> +80002d3c: e69fe06f j 80001ba4 <_vfprintf_r+0x850> +80002d40: 0f012783 lw a5,240(sp) +80002d44: 0a010593 addi a1,sp,160 +80002d48: 0b010513 addi a0,sp,176 +80002d4c: 0af12823 sw a5,176(sp) +80002d50: 0f412783 lw a5,244(sp) +80002d54: 0a012023 sw zero,160(sp) +80002d58: 0a012223 sw zero,164(sp) +80002d5c: 0af12a23 sw a5,180(sp) +80002d60: 0f812783 lw a5,248(sp) +80002d64: 0a012423 sw zero,168(sp) +80002d68: 0a012623 sw zero,172(sp) +80002d6c: 0af12c23 sw a5,184(sp) +80002d70: 0fc12783 lw a5,252(sp) +80002d74: 0af12e23 sw a5,188(sp) +80002d78: 5810e0ef jal ra,80011af8 <__letf2> +80002d7c: 01012883 lw a7,16(sp) +80002d80: 260540e3 bltz a0,800037e0 <_vfprintf_r+0x248c> +80002d84: 0c714783 lbu a5,199(sp) +80002d88: 04700713 li a4,71 +80002d8c: 38975863 bge a4,s1,8000311c <_vfprintf_r+0x1dc8> +80002d90: 80015737 lui a4,0x80015 +80002d94: b9870b13 addi s6,a4,-1128 # 80014b98 <__BSS_END__+0xffffdf5c> +80002d98: 00012823 sw zero,16(sp) +80002d9c: 02012423 sw zero,40(sp) +80002da0: 02012223 sw zero,36(sp) +80002da4: 00012e23 sw zero,28(sp) +80002da8: f7fa7a13 andi s4,s4,-129 +80002dac: 00300a93 li s5,3 +80002db0: 00300c93 li s9,3 +80002db4: 00000d93 li s11,0 +80002db8: 00078463 beqz a5,80002dc0 <_vfprintf_r+0x1a6c> +80002dbc: f75fe06f j 80001d30 <_vfprintf_r+0x9dc> +80002dc0: fccfe06f j 8000158c <_vfprintf_r+0x238> +80002dc4: 00c12783 lw a5,12(sp) +80002dc8: 00040b13 mv s6,s0 +80002dcc: 00f72023 sw a5,0(a4) +80002dd0: 8d5fe06f j 800016a4 <_vfprintf_r+0x350> +80002dd4: 000b0513 mv a0,s6 +80002dd8: 05912023 sw s9,64(sp) +80002ddc: 2c1060ef jal ra,8000989c +80002de0: 0c714783 lbu a5,199(sp) +80002de4: fff54a93 not s5,a0 +80002de8: 41fada93 srai s5,s5,0x1f +80002dec: 01212a23 sw s2,20(sp) +80002df0: 00012823 sw zero,16(sp) +80002df4: 02012423 sw zero,40(sp) +80002df8: 02012223 sw zero,36(sp) +80002dfc: 00012e23 sw zero,28(sp) +80002e00: 04012883 lw a7,64(sp) +80002e04: 00050c93 mv s9,a0 +80002e08: 01557ab3 and s5,a0,s5 +80002e0c: 00000d93 li s11,0 +80002e10: 00078463 beqz a5,80002e18 <_vfprintf_r+0x1ac4> +80002e14: f1dfe06f j 80001d30 <_vfprintf_r+0x9dc> +80002e18: f74fe06f j 8000158c <_vfprintf_r+0x238> +80002e1c: 200a7793 andi a5,s4,512 +80002e20: 3a078263 beqz a5,800031c4 <_vfprintf_r+0x1e70> +80002e24: 01412783 lw a5,20(sp) +80002e28: 00000c93 li s9,0 +80002e2c: 00e12a23 sw a4,20(sp) +80002e30: 0007c903 lbu s2,0(a5) +80002e34: bc9ff06f j 800029fc <_vfprintf_r+0x16a8> +80002e38: 200bf793 andi a5,s7,512 +80002e3c: 36078863 beqz a5,800031ac <_vfprintf_r+0x1e58> +80002e40: 01412783 lw a5,20(sp) +80002e44: 00000c93 li s9,0 +80002e48: 00e12a23 sw a4,20(sp) +80002e4c: 0007c903 lbu s2,0(a5) +80002e50: 00100793 li a5,1 +80002e54: f91fe06f j 80001de4 <_vfprintf_r+0xa90> +80002e58: 200a7793 andi a5,s4,512 +80002e5c: 32078c63 beqz a5,80003194 <_vfprintf_r+0x1e40> +80002e60: 01412783 lw a5,20(sp) +80002e64: 00e12a23 sw a4,20(sp) +80002e68: 00078903 lb s2,0(a5) +80002e6c: 41f95c93 srai s9,s2,0x1f +80002e70: 000c8793 mv a5,s9 +80002e74: 928ff06f j 80001f9c <_vfprintf_r+0xc48> +80002e78: 200a7793 andi a5,s4,512 +80002e7c: 30078263 beqz a5,80003180 <_vfprintf_r+0x1e2c> +80002e80: 01412783 lw a5,20(sp) +80002e84: 00000c93 li s9,0 +80002e88: 00e12a23 sw a4,20(sp) +80002e8c: 0007c903 lbu s2,0(a5) +80002e90: 890ff06f j 80001f20 <_vfprintf_r+0xbcc> +80002e94: 0fc12783 lw a5,252(sp) +80002e98: 3407ca63 bltz a5,800031ec <_vfprintf_r+0x1e98> +80002e9c: 0c714783 lbu a5,199(sp) +80002ea0: 04700713 li a4,71 +80002ea4: 1c975ce3 bge a4,s1,8000387c <_vfprintf_r+0x2528> +80002ea8: 80015737 lui a4,0x80015 +80002eac: ba070b13 addi s6,a4,-1120 # 80014ba0 <__BSS_END__+0xffffdf64> +80002eb0: ee9ff06f j 80002d98 <_vfprintf_r+0x1a44> +80002eb4: 00812703 lw a4,8(sp) +80002eb8: 009787b3 add a5,a5,s1 +80002ebc: 00168693 addi a3,a3,1 +80002ec0: 00e8a023 sw a4,0(a7) +80002ec4: 0098a223 sw s1,4(a7) +80002ec8: 0ef12623 sw a5,236(sp) +80002ecc: 0ed12423 sw a3,232(sp) +80002ed0: 00700613 li a2,7 +80002ed4: 00888893 addi a7,a7,8 +80002ed8: f4d65463 bge a2,a3,80002620 <_vfprintf_r+0x12cc> +80002edc: 0e410613 addi a2,sp,228 +80002ee0: 000c0593 mv a1,s8 +80002ee4: 000d0513 mv a0,s10 +80002ee8: 5ec090ef jal ra,8000c4d4 <__sprint_r> +80002eec: c8051c63 bnez a0,80002384 <_vfprintf_r+0x1030> +80002ef0: 0ec12783 lw a5,236(sp) +80002ef4: 10c10893 addi a7,sp,268 +80002ef8: f28ff06f j 80002620 <_vfprintf_r+0x12cc> +80002efc: 02012703 lw a4,32(sp) +80002f00: 02412c83 lw s9,36(sp) +80002f04: 01412e23 sw s4,28(sp) +80002f08: 04812023 sw s0,64(sp) +80002f0c: 05312223 sw s3,68(sp) +80002f10: 03512223 sw s5,36(sp) +80002f14: 02812983 lw s3,40(sp) +80002f18: 03612423 sw s6,40(sp) +80002f1c: 00eb0bb3 add s7,s6,a4 +80002f20: 03c12403 lw s0,60(sp) +80002f24: 04812a03 lw s4,72(sp) +80002f28: 04c12a83 lw s5,76(sp) +80002f2c: 00700493 li s1,7 +80002f30: 01000913 li s2,16 +80002f34: 000c0b13 mv s6,s8 +80002f38: 080c8863 beqz s9,80002fc8 <_vfprintf_r+0x1c74> +80002f3c: 08099863 bnez s3,80002fcc <_vfprintf_r+0x1c78> +80002f40: fff40413 addi s0,s0,-1 +80002f44: fffc8c93 addi s9,s9,-1 +80002f48: 0e812703 lw a4,232(sp) +80002f4c: 014787b3 add a5,a5,s4 +80002f50: 0158a023 sw s5,0(a7) +80002f54: 00170713 addi a4,a4,1 +80002f58: 0148a223 sw s4,4(a7) +80002f5c: 0ef12623 sw a5,236(sp) +80002f60: 0ee12423 sw a4,232(sp) +80002f64: 00888893 addi a7,a7,8 +80002f68: 0ee4ce63 blt s1,a4,80003064 <_vfprintf_r+0x1d10> +80002f6c: 00044683 lbu a3,0(s0) +80002f70: 41bb8633 sub a2,s7,s11 +80002f74: 00068c13 mv s8,a3 +80002f78: 00d65463 bge a2,a3,80002f80 <_vfprintf_r+0x1c2c> +80002f7c: 00060c13 mv s8,a2 +80002f80: 03805663 blez s8,80002fac <_vfprintf_r+0x1c58> +80002f84: 0e812683 lw a3,232(sp) +80002f88: 018787b3 add a5,a5,s8 +80002f8c: 01b8a023 sw s11,0(a7) +80002f90: 00168693 addi a3,a3,1 +80002f94: 0188a223 sw s8,4(a7) +80002f98: 0ef12623 sw a5,236(sp) +80002f9c: 0ed12423 sw a3,232(sp) +80002fa0: 0ed4c263 blt s1,a3,80003084 <_vfprintf_r+0x1d30> +80002fa4: 00044683 lbu a3,0(s0) +80002fa8: 00888893 addi a7,a7,8 +80002fac: fffc4613 not a2,s8 +80002fb0: 41f65613 srai a2,a2,0x1f +80002fb4: 00cc7733 and a4,s8,a2 +80002fb8: 40e68c33 sub s8,a3,a4 +80002fbc: 01804c63 bgtz s8,80002fd4 <_vfprintf_r+0x1c80> +80002fc0: 00dd8db3 add s11,s11,a3 +80002fc4: f60c9ce3 bnez s9,80002f3c <_vfprintf_r+0x1be8> +80002fc8: 5e098a63 beqz s3,800035bc <_vfprintf_r+0x2268> +80002fcc: fff98993 addi s3,s3,-1 +80002fd0: f79ff06f j 80002f48 <_vfprintf_r+0x1bf4> +80002fd4: 0e812683 lw a3,232(sp) +80002fd8: 01894863 blt s2,s8,80002fe8 <_vfprintf_r+0x1c94> +80002fdc: 0580006f j 80003034 <_vfprintf_r+0x1ce0> +80002fe0: ff0c0c13 addi s8,s8,-16 +80002fe4: 05895863 bge s2,s8,80003034 <_vfprintf_r+0x1ce0> +80002fe8: 00812703 lw a4,8(sp) +80002fec: 01078793 addi a5,a5,16 +80002ff0: 00168693 addi a3,a3,1 +80002ff4: 00e8a023 sw a4,0(a7) +80002ff8: 0128a223 sw s2,4(a7) +80002ffc: 0ef12623 sw a5,236(sp) +80003000: 0ed12423 sw a3,232(sp) +80003004: 00888893 addi a7,a7,8 +80003008: fcd4dce3 bge s1,a3,80002fe0 <_vfprintf_r+0x1c8c> +8000300c: 0e410613 addi a2,sp,228 +80003010: 000b0593 mv a1,s6 +80003014: 000d0513 mv a0,s10 +80003018: 4bc090ef jal ra,8000c4d4 <__sprint_r> +8000301c: 66051463 bnez a0,80003684 <_vfprintf_r+0x2330> +80003020: ff0c0c13 addi s8,s8,-16 +80003024: 0ec12783 lw a5,236(sp) +80003028: 0e812683 lw a3,232(sp) +8000302c: 10c10893 addi a7,sp,268 +80003030: fb894ce3 blt s2,s8,80002fe8 <_vfprintf_r+0x1c94> +80003034: 00812703 lw a4,8(sp) +80003038: 018787b3 add a5,a5,s8 +8000303c: 00168693 addi a3,a3,1 +80003040: 00e8a023 sw a4,0(a7) +80003044: 0188a223 sw s8,4(a7) +80003048: 0ef12623 sw a5,236(sp) +8000304c: 0ed12423 sw a3,232(sp) +80003050: 66d4c063 blt s1,a3,800036b0 <_vfprintf_r+0x235c> +80003054: 00044683 lbu a3,0(s0) +80003058: 00888893 addi a7,a7,8 +8000305c: 00dd8db3 add s11,s11,a3 +80003060: f65ff06f j 80002fc4 <_vfprintf_r+0x1c70> +80003064: 0e410613 addi a2,sp,228 +80003068: 000b0593 mv a1,s6 +8000306c: 000d0513 mv a0,s10 +80003070: 464090ef jal ra,8000c4d4 <__sprint_r> +80003074: 60051863 bnez a0,80003684 <_vfprintf_r+0x2330> +80003078: 0ec12783 lw a5,236(sp) +8000307c: 10c10893 addi a7,sp,268 +80003080: eedff06f j 80002f6c <_vfprintf_r+0x1c18> +80003084: 0e410613 addi a2,sp,228 +80003088: 000b0593 mv a1,s6 +8000308c: 000d0513 mv a0,s10 +80003090: 444090ef jal ra,8000c4d4 <__sprint_r> +80003094: 5e051863 bnez a0,80003684 <_vfprintf_r+0x2330> +80003098: 00044683 lbu a3,0(s0) +8000309c: 0ec12783 lw a5,236(sp) +800030a0: 10c10893 addi a7,sp,268 +800030a4: f09ff06f j 80002fac <_vfprintf_r+0x1c58> +800030a8: 04812783 lw a5,72(sp) +800030ac: 04c12583 lw a1,76(sp) +800030b0: 00000913 li s2,0 +800030b4: 40f40433 sub s0,s0,a5 +800030b8: 00078613 mv a2,a5 +800030bc: 00040513 mv a0,s0 +800030c0: 069060ef jal ra,80009928 +800030c4: 001cc583 lbu a1,1(s9) +800030c8: 00a00613 li a2,10 +800030cc: 00000693 li a3,0 +800030d0: 00b03833 snez a6,a1 +800030d4: 00048513 mv a0,s1 +800030d8: 00098593 mv a1,s3 +800030dc: 010c8cb3 add s9,s9,a6 +800030e0: 3200d0ef jal ra,80010400 <__udivdi3> +800030e4: ae5ff06f j 80002bc8 <_vfprintf_r+0x1874> +800030e8: 00168693 addi a3,a3,1 +800030ec: 00870893 addi a7,a4,8 +800030f0: 00070913 mv s2,a4 +800030f4: b98ff06f j 8000248c <_vfprintf_r+0x1138> +800030f8: 0e410613 addi a2,sp,228 +800030fc: 000c0593 mv a1,s8 +80003100: 000d0513 mv a0,s10 +80003104: 3d0090ef jal ra,8000c4d4 <__sprint_r> +80003108: a6051e63 bnez a0,80002384 <_vfprintf_r+0x1030> +8000310c: 0cc12583 lw a1,204(sp) +80003110: 0ec12783 lw a5,236(sp) +80003114: 10c10893 addi a7,sp,268 +80003118: b5dff06f j 80002c74 <_vfprintf_r+0x1920> +8000311c: 80015737 lui a4,0x80015 +80003120: b9470b13 addi s6,a4,-1132 # 80014b94 <__BSS_END__+0xffffdf58> +80003124: c75ff06f j 80002d98 <_vfprintf_r+0x1a44> 80003128: 0e410613 addi a2,sp,228 -8000312c: 000b0593 mv a1,s6 +8000312c: 000c0593 mv a1,s8 80003130: 000d0513 mv a0,s10 -80003134: 464090ef jal ra,8000c598 <__sprint_r> -80003138: 60051863 bnez a0,80003748 <_vfprintf_r+0x2330> +80003134: 3a0090ef jal ra,8000c4d4 <__sprint_r> +80003138: a4051663 bnez a0,80002384 <_vfprintf_r+0x1030> 8000313c: 0ec12783 lw a5,236(sp) 80003140: 10c10893 addi a7,sp,268 -80003144: eedff06f j 80003030 <_vfprintf_r+0x1c18> -80003148: 0e410613 addi a2,sp,228 -8000314c: 000b0593 mv a1,s6 -80003150: 000d0513 mv a0,s10 -80003154: 444090ef jal ra,8000c598 <__sprint_r> -80003158: 5e051863 bnez a0,80003748 <_vfprintf_r+0x2330> -8000315c: 00044683 lbu a3,0(s0) -80003160: 0ec12783 lw a5,236(sp) -80003164: 10c10893 addi a7,sp,268 -80003168: f09ff06f j 80003070 <_vfprintf_r+0x1c58> -8000316c: 04812783 lw a5,72(sp) -80003170: 04c12583 lw a1,76(sp) -80003174: 00000913 li s2,0 -80003178: 40f40433 sub s0,s0,a5 -8000317c: 00078613 mv a2,a5 -80003180: 00040513 mv a0,s0 -80003184: 069060ef jal ra,800099ec -80003188: 001cc583 lbu a1,1(s9) -8000318c: 00a00613 li a2,10 -80003190: 00000693 li a3,0 -80003194: 00b03833 snez a6,a1 -80003198: 00048513 mv a0,s1 -8000319c: 00098593 mv a1,s3 -800031a0: 010c8cb3 add s9,s9,a6 -800031a4: 3200d0ef jal ra,800104c4 <__udivdi3> -800031a8: ae5ff06f j 80002c8c <_vfprintf_r+0x1874> -800031ac: 00168693 addi a3,a3,1 -800031b0: 00870893 addi a7,a4,8 -800031b4: 00070913 mv s2,a4 -800031b8: b98ff06f j 80002550 <_vfprintf_r+0x1138> -800031bc: 0e410613 addi a2,sp,228 -800031c0: 000c0593 mv a1,s8 -800031c4: 000d0513 mv a0,s10 -800031c8: 3d0090ef jal ra,8000c598 <__sprint_r> -800031cc: a6051e63 bnez a0,80002448 <_vfprintf_r+0x1030> -800031d0: 0cc12583 lw a1,204(sp) -800031d4: 0ec12783 lw a5,236(sp) -800031d8: 10c10893 addi a7,sp,268 -800031dc: b5dff06f j 80002d38 <_vfprintf_r+0x1920> -800031e0: 80015737 lui a4,0x80015 -800031e4: c6870b13 addi s6,a4,-920 # 80014c68 <__BSS_END__+0xffffe02c> -800031e8: c75ff06f j 80002e5c <_vfprintf_r+0x1a44> -800031ec: 0e410613 addi a2,sp,228 -800031f0: 000c0593 mv a1,s8 -800031f4: 000d0513 mv a0,s10 -800031f8: 3a0090ef jal ra,8000c598 <__sprint_r> -800031fc: a4051663 bnez a0,80002448 <_vfprintf_r+0x1030> -80003200: 0ec12783 lw a5,236(sp) -80003204: 10c10893 addi a7,sp,268 -80003208: cc4ff06f j 800026cc <_vfprintf_r+0x12b4> -8000320c: 00600c93 li s9,6 -80003210: 945ff06f j 80002b54 <_vfprintf_r+0x173c> -80003214: 02012683 lw a3,32(sp) -80003218: 00db0733 add a4,s6,a3 -8000321c: 409684b3 sub s1,a3,s1 -80003220: 41b70833 sub a6,a4,s11 -80003224: 00048913 mv s2,s1 -80003228: d6985063 bge a6,s1,80002788 <_vfprintf_r+0x1370> -8000322c: 00080913 mv s2,a6 -80003230: d58ff06f j 80002788 <_vfprintf_r+0x1370> -80003234: 00c12783 lw a5,12(sp) -80003238: 00040b13 mv s6,s0 -8000323c: 00f71023 sh a5,0(a4) -80003240: d28fe06f j 80001768 <_vfprintf_r+0x350> -80003244: 01412783 lw a5,20(sp) -80003248: 00000c93 li s9,0 -8000324c: 00e12a23 sw a4,20(sp) -80003250: 0007a903 lw s2,0(a5) -80003254: d91fe06f j 80001fe4 <_vfprintf_r+0xbcc> -80003258: 01412783 lw a5,20(sp) -8000325c: 00e12a23 sw a4,20(sp) -80003260: 0007a903 lw s2,0(a5) -80003264: 41f95c93 srai s9,s2,0x1f -80003268: 000c8793 mv a5,s9 -8000326c: df5fe06f j 80002060 <_vfprintf_r+0xc48> -80003270: 01412783 lw a5,20(sp) -80003274: 00000c93 li s9,0 -80003278: 00e12a23 sw a4,20(sp) -8000327c: 0007a903 lw s2,0(a5) -80003280: 00100793 li a5,1 -80003284: c25fe06f j 80001ea8 <_vfprintf_r+0xa90> -80003288: 01412783 lw a5,20(sp) -8000328c: 00000c93 li s9,0 -80003290: 00e12a23 sw a4,20(sp) -80003294: 0007a903 lw s2,0(a5) -80003298: 829ff06f j 80002ac0 <_vfprintf_r+0x16a8> -8000329c: 0e410613 addi a2,sp,228 -800032a0: 000c0593 mv a1,s8 -800032a4: 000d0513 mv a0,s10 -800032a8: 2f0090ef jal ra,8000c598 <__sprint_r> -800032ac: cd0fe06f j 8000177c <_vfprintf_r+0x364> -800032b0: 02d00793 li a5,45 -800032b4: 0cf103a3 sb a5,199(sp) -800032b8: cadff06f j 80002f64 <_vfprintf_r+0x1b4c> -800032bc: 03000793 li a5,48 -800032c0: 0cf10423 sb a5,200(sp) -800032c4: 05800793 li a5,88 -800032c8: 002a6713 ori a4,s4,2 -800032cc: 0cf104a3 sb a5,201(sp) -800032d0: 02e12423 sw a4,40(sp) -800032d4: 06300793 li a5,99 -800032d8: 00012823 sw zero,16(sp) -800032dc: 14c10b13 addi s6,sp,332 -800032e0: 03b7c4e3 blt a5,s11,80003b08 <_vfprintf_r+0x26f0> -800032e4: 0fc12303 lw t1,252(sp) -800032e8: fdf4fb93 andi s7,s1,-33 -800032ec: 05712223 sw s7,68(sp) -800032f0: 04012c23 sw zero,88(sp) -800032f4: 0f012e03 lw t3,240(sp) -800032f8: 0f412e83 lw t4,244(sp) -800032fc: 0f812f03 lw t5,248(sp) -80003300: 102a6a13 ori s4,s4,258 -80003304: 44034e63 bltz t1,80003760 <_vfprintf_r+0x2348> -80003308: 06100793 li a5,97 -8000330c: 0af48ee3 beq s1,a5,80003bc8 <_vfprintf_r+0x27b0> -80003310: 04100793 li a5,65 -80003314: 00f48463 beq s1,a5,8000331c <_vfprintf_r+0x1f04> -80003318: e64fe06f j 8000197c <_vfprintf_r+0x564> -8000331c: 0b010a93 addi s5,sp,176 -80003320: 000a8513 mv a0,s5 -80003324: 05112a23 sw a7,84(sp) -80003328: 0bc12823 sw t3,176(sp) -8000332c: 0bd12a23 sw t4,180(sp) -80003330: 0be12c23 sw t5,184(sp) -80003334: 0a612e23 sw t1,188(sp) -80003338: 344110ef jal ra,8001467c <__trunctfdf2> -8000333c: 0cc10613 addi a2,sp,204 -80003340: 22c060ef jal ra,8000956c -80003344: 00058613 mv a2,a1 -80003348: 00050593 mv a1,a0 -8000334c: 000a8513 mv a0,s5 -80003350: 138110ef jal ra,80014488 <__extenddftf2> -80003354: 0b012783 lw a5,176(sp) -80003358: 0a010c93 addi s9,sp,160 -8000335c: 09010913 addi s2,sp,144 -80003360: 08f12823 sw a5,144(sp) -80003364: 0b412783 lw a5,180(sp) -80003368: 08010613 addi a2,sp,128 -8000336c: 00090593 mv a1,s2 -80003370: 08f12a23 sw a5,148(sp) -80003374: 0b812783 lw a5,184(sp) -80003378: 000c8513 mv a0,s9 -8000337c: 04c12023 sw a2,64(sp) -80003380: 08f12c23 sw a5,152(sp) -80003384: 0bc12783 lw a5,188(sp) -80003388: 08012023 sw zero,128(sp) -8000338c: 08012223 sw zero,132(sp) -80003390: 08f12e23 sw a5,156(sp) -80003394: 3ffc07b7 lui a5,0x3ffc0 -80003398: 08f12623 sw a5,140(sp) -8000339c: 08012423 sw zero,136(sp) -800033a0: 1610e0ef jal ra,80011d00 <__multf3> -800033a4: 0a012803 lw a6,160(sp) -800033a8: 0a412e03 lw t3,164(sp) -800033ac: 0a812e83 lw t4,168(sp) -800033b0: 0ac12f03 lw t5,172(sp) -800033b4: 000c8593 mv a1,s9 -800033b8: 000a8513 mv a0,s5 -800033bc: 0b012823 sw a6,176(sp) -800033c0: 05012823 sw a6,80(sp) -800033c4: 0bc12a23 sw t3,180(sp) -800033c8: 03c12223 sw t3,36(sp) -800033cc: 0bd12c23 sw t4,184(sp) -800033d0: 03d12023 sw t4,32(sp) -800033d4: 0be12e23 sw t5,188(sp) -800033d8: 01e12e23 sw t5,28(sp) -800033dc: 0a012023 sw zero,160(sp) -800033e0: 0a012223 sw zero,164(sp) -800033e4: 0a012423 sw zero,168(sp) -800033e8: 0a012623 sw zero,172(sp) -800033ec: 5c00e0ef jal ra,800119ac <__eqtf2> -800033f0: 01c12f03 lw t5,28(sp) -800033f4: 02012e83 lw t4,32(sp) -800033f8: 02412e03 lw t3,36(sp) -800033fc: 05012803 lw a6,80(sp) -80003400: 05412883 lw a7,84(sp) -80003404: 00051663 bnez a0,80003410 <_vfprintf_r+0x1ff8> -80003408: 00100793 li a5,1 -8000340c: 0cf12623 sw a5,204(sp) -80003410: 800157b7 lui a5,0x80015 -80003414: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> -80003418: 02f12223 sw a5,36(sp) -8000341c: fffd8693 addi a3,s11,-1 -80003420: 05412e23 sw s4,92(sp) -80003424: 06912223 sw s1,100(sp) -80003428: 07b12623 sw s11,108(sp) -8000342c: 07a12a23 sw s10,116(sp) -80003430: 07812c23 sw s8,120(sp) -80003434: 06812023 sw s0,96(sp) -80003438: 07312423 sw s3,104(sp) -8000343c: 07112823 sw a7,112(sp) -80003440: 000b0c13 mv s8,s6 -80003444: 00068b93 mv s7,a3 -80003448: 07612e23 sw s6,124(sp) -8000344c: 00080d13 mv s10,a6 -80003450: 000e0d93 mv s11,t3 -80003454: 000e8493 mv s1,t4 -80003458: 000f0a13 mv s4,t5 -8000345c: 0480006f j 800034a4 <_vfprintf_r+0x208c> -80003460: 000c8593 mv a1,s9 -80003464: 000a8513 mv a0,s5 -80003468: 02c12023 sw a2,32(sp) -8000346c: 01f12e23 sw t6,28(sp) -80003470: 0bf12c23 sw t6,184(sp) -80003474: 0ac12e23 sw a2,188(sp) -80003478: 0b612823 sw s6,176(sp) -8000347c: 0b312a23 sw s3,180(sp) -80003480: 0a012023 sw zero,160(sp) -80003484: 0a012223 sw zero,164(sp) -80003488: 0a012423 sw zero,168(sp) -8000348c: 0a012623 sw zero,172(sp) -80003490: 51c0e0ef jal ra,800119ac <__eqtf2> -80003494: 01c12f83 lw t6,28(sp) -80003498: 02012603 lw a2,32(sp) -8000349c: fffb8b93 addi s7,s7,-1 -800034a0: 0e050263 beqz a0,80003584 <_vfprintf_r+0x216c> -800034a4: 400307b7 lui a5,0x40030 -800034a8: 00090613 mv a2,s2 -800034ac: 000c8593 mv a1,s9 -800034b0: 000a8513 mv a0,s5 -800034b4: 08f12e23 sw a5,156(sp) -800034b8: 0ba12023 sw s10,160(sp) -800034bc: 0bb12223 sw s11,164(sp) -800034c0: 0a912423 sw s1,168(sp) -800034c4: 0b412623 sw s4,172(sp) -800034c8: 08012823 sw zero,144(sp) -800034cc: 08012a23 sw zero,148(sp) -800034d0: 08012c23 sw zero,152(sp) -800034d4: 02d0e0ef jal ra,80011d00 <__multf3> -800034d8: 000a8513 mv a0,s5 -800034dc: 549100ef jal ra,80014224 <__fixtfsi> -800034e0: 00050593 mv a1,a0 -800034e4: 00050413 mv s0,a0 -800034e8: 000a8513 mv a0,s5 -800034ec: 0b012983 lw s3,176(sp) -800034f0: 0b412483 lw s1,180(sp) -800034f4: 0b812b03 lw s6,184(sp) -800034f8: 0bc12a03 lw s4,188(sp) -800034fc: 63d100ef jal ra,80014338 <__floatsitf> -80003500: 0b012703 lw a4,176(sp) -80003504: 04012603 lw a2,64(sp) -80003508: 00090593 mv a1,s2 -8000350c: 08e12023 sw a4,128(sp) -80003510: 0b412703 lw a4,180(sp) -80003514: 000c8513 mv a0,s9 -80003518: 09312823 sw s3,144(sp) -8000351c: 08e12223 sw a4,132(sp) -80003520: 0b812703 lw a4,184(sp) -80003524: 08912a23 sw s1,148(sp) -80003528: 09612c23 sw s6,152(sp) -8000352c: 08e12423 sw a4,136(sp) -80003530: 0bc12703 lw a4,188(sp) -80003534: 09412e23 sw s4,156(sp) -80003538: 08e12623 sw a4,140(sp) -8000353c: 7c80f0ef jal ra,80012d04 <__subtf3> -80003540: 02412783 lw a5,36(sp) -80003544: 0a012b03 lw s6,160(sp) -80003548: 0a412983 lw s3,164(sp) -8000354c: 00878733 add a4,a5,s0 -80003550: 00074703 lbu a4,0(a4) -80003554: 0a812f83 lw t6,168(sp) -80003558: 0ac12603 lw a2,172(sp) -8000355c: 05812a23 sw s8,84(sp) -80003560: 00ec0023 sb a4,0(s8) -80003564: 05712823 sw s7,80(sp) -80003568: fff00793 li a5,-1 -8000356c: 001c0c13 addi s8,s8,1 -80003570: 000b0d13 mv s10,s6 -80003574: 00098d93 mv s11,s3 -80003578: 000f8493 mv s1,t6 -8000357c: 00060a13 mv s4,a2 -80003580: eefb90e3 bne s7,a5,80003460 <_vfprintf_r+0x2048> -80003584: 07012883 lw a7,112(sp) -80003588: 000b0393 mv t2,s6 -8000358c: 00098293 mv t0,s3 -80003590: 3ffe0937 lui s2,0x3ffe0 -80003594: 000c8593 mv a1,s9 -80003598: 000a8513 mv a0,s5 -8000359c: 03112023 sw a7,32(sp) -800035a0: 00812e23 sw s0,28(sp) -800035a4: 05c12a03 lw s4,92(sp) -800035a8: 06412483 lw s1,100(sp) -800035ac: 06012403 lw s0,96(sp) -800035b0: 0a712823 sw t2,176(sp) -800035b4: 06712223 sw t2,100(sp) -800035b8: 0a512a23 sw t0,180(sp) -800035bc: 06512023 sw t0,96(sp) -800035c0: 0bf12c23 sw t6,184(sp) -800035c4: 05f12e23 sw t6,92(sp) -800035c8: 0ac12e23 sw a2,188(sp) -800035cc: 04c12023 sw a2,64(sp) -800035d0: 0a012023 sw zero,160(sp) -800035d4: 0a012223 sw zero,164(sp) -800035d8: 0a012423 sw zero,168(sp) -800035dc: 0b212623 sw s2,172(sp) -800035e0: 4980e0ef jal ra,80011a78 <__getf2> -800035e4: 000c0b93 mv s7,s8 -800035e8: 06c12d83 lw s11,108(sp) -800035ec: 07412d03 lw s10,116(sp) -800035f0: 07812c03 lw s8,120(sp) -800035f4: 07c12b03 lw s6,124(sp) -800035f8: 06812983 lw s3,104(sp) -800035fc: 02012883 lw a7,32(sp) -80003600: 48a04263 bgtz a0,80003a84 <_vfprintf_r+0x266c> -80003604: 06412383 lw t2,100(sp) -80003608: 06012283 lw t0,96(sp) -8000360c: 05c12f83 lw t6,92(sp) -80003610: 04012603 lw a2,64(sp) -80003614: 000c8593 mv a1,s9 -80003618: 000a8513 mv a0,s5 -8000361c: 0a712823 sw t2,176(sp) -80003620: 0a512a23 sw t0,180(sp) -80003624: 0bf12c23 sw t6,184(sp) -80003628: 0ac12e23 sw a2,188(sp) -8000362c: 0a012023 sw zero,160(sp) -80003630: 0a012223 sw zero,164(sp) -80003634: 0a012423 sw zero,168(sp) -80003638: 0b212623 sw s2,172(sp) -8000363c: 3700e0ef jal ra,800119ac <__eqtf2> -80003640: 02012883 lw a7,32(sp) -80003644: 00051863 bnez a0,80003654 <_vfprintf_r+0x223c> -80003648: 01c12783 lw a5,28(sp) -8000364c: 0017fc93 andi s9,a5,1 -80003650: 420c9a63 bnez s9,80003a84 <_vfprintf_r+0x266c> -80003654: 05012783 lw a5,80(sp) -80003658: 03000613 li a2,48 -8000365c: 00178693 addi a3,a5,1 # 40030001 <_start-0x3ffcffff> -80003660: 00db86b3 add a3,s7,a3 -80003664: 0007c863 bltz a5,80003674 <_vfprintf_r+0x225c> -80003668: 001b8b93 addi s7,s7,1 -8000366c: fecb8fa3 sb a2,-1(s7) -80003670: ff769ce3 bne a3,s7,80003668 <_vfprintf_r+0x2250> -80003674: 416b87b3 sub a5,s7,s6 -80003678: 02f12023 sw a5,32(sp) -8000367c: be8fe06f j 80001a64 <_vfprintf_r+0x64c> -80003680: 02012703 lw a4,32(sp) -80003684: 000b0c13 mv s8,s6 -80003688: 02812b03 lw s6,40(sp) -8000368c: 02812e23 sw s0,60(sp) -80003690: 01c12a03 lw s4,28(sp) -80003694: 00eb06b3 add a3,s6,a4 -80003698: 04012403 lw s0,64(sp) -8000369c: 04412983 lw s3,68(sp) -800036a0: 02412a83 lw s5,36(sp) -800036a4: 01b6e463 bltu a3,s11,800036ac <_vfprintf_r+0x2294> -800036a8: 84cff06f j 800026f4 <_vfprintf_r+0x12dc> -800036ac: 00068d93 mv s11,a3 -800036b0: 844ff06f j 800026f4 <_vfprintf_r+0x12dc> -800036b4: 01c12703 lw a4,28(sp) -800036b8: ffd00793 li a5,-3 -800036bc: 00f74463 blt a4,a5,800036c4 <_vfprintf_r+0x22ac> -800036c0: 00edda63 bge s11,a4,800036d4 <_vfprintf_r+0x22bc> -800036c4: ffe48493 addi s1,s1,-2 -800036c8: fdf4f793 andi a5,s1,-33 -800036cc: 04f12223 sw a5,68(sp) -800036d0: bbcfe06f j 80001a8c <_vfprintf_r+0x674> -800036d4: 02012783 lw a5,32(sp) -800036d8: 01c12703 lw a4,28(sp) -800036dc: 2af74063 blt a4,a5,8000397c <_vfprintf_r+0x2564> -800036e0: 02812783 lw a5,40(sp) -800036e4: 00070c93 mv s9,a4 -800036e8: 0017f793 andi a5,a5,1 -800036ec: 00078663 beqz a5,800036f8 <_vfprintf_r+0x22e0> -800036f0: 02c12783 lw a5,44(sp) -800036f4: 00f70cb3 add s9,a4,a5 -800036f8: 02812783 lw a5,40(sp) -800036fc: 4007f793 andi a5,a5,1024 -80003700: 00078663 beqz a5,8000370c <_vfprintf_r+0x22f4> -80003704: 01c12783 lw a5,28(sp) -80003708: 5cf04263 bgtz a5,80003ccc <_vfprintf_r+0x28b4> -8000370c: fffcca93 not s5,s9 -80003710: 41fada93 srai s5,s5,0x1f -80003714: 015cfab3 and s5,s9,s5 -80003718: 06700493 li s1,103 -8000371c: 02012423 sw zero,40(sp) -80003720: 02012223 sw zero,36(sp) -80003724: c84fe06f j 80001ba8 <_vfprintf_r+0x790> -80003728: 0c714783 lbu a5,199(sp) -8000372c: 00000d93 li s11,0 -80003730: 00078463 beqz a5,80003738 <_vfprintf_r+0x2320> -80003734: ec0fe06f j 80001df4 <_vfprintf_r+0x9dc> -80003738: f19fd06f j 80001650 <_vfprintf_r+0x238> -8000373c: 00900793 li a5,9 -80003740: d497e663 bltu a5,s1,80002c8c <_vfprintf_r+0x1874> -80003744: d90ff06f j 80002cd4 <_vfprintf_r+0x18bc> -80003748: 01012b83 lw s7,16(sp) -8000374c: 000b0c13 mv s8,s6 -80003750: cfdfe06f j 8000244c <_vfprintf_r+0x1034> -80003754: 03412423 sw s4,40(sp) -80003758: 00012823 sw zero,16(sp) -8000375c: 00090a13 mv s4,s2 -80003760: 800007b7 lui a5,0x80000 -80003764: 0067c333 xor t1,a5,t1 -80003768: 02d00793 li a5,45 -8000376c: 04f12c23 sw a5,88(sp) -80003770: b99ff06f j 80003308 <_vfprintf_r+0x1ef0> -80003774: 0e410613 addi a2,sp,228 -80003778: 000b0593 mv a1,s6 -8000377c: 000d0513 mv a0,s10 -80003780: 619080ef jal ra,8000c598 <__sprint_r> -80003784: fc0512e3 bnez a0,80003748 <_vfprintf_r+0x2330> -80003788: 00044683 lbu a3,0(s0) -8000378c: 0ec12783 lw a5,236(sp) -80003790: 10c10893 addi a7,sp,268 -80003794: 00dd8db3 add s11,s11,a3 -80003798: 8f1ff06f j 80003088 <_vfprintf_r+0x1c70> -8000379c: 0b010a93 addi s5,sp,176 -800037a0: 0d010793 addi a5,sp,208 -800037a4: 0dc10813 addi a6,sp,220 -800037a8: 0cc10713 addi a4,sp,204 -800037ac: 000d8693 mv a3,s11 -800037b0: 00200613 li a2,2 -800037b4: 000a8593 mv a1,s5 -800037b8: 000d0513 mv a0,s10 -800037bc: 0bc12823 sw t3,176(sp) -800037c0: 05c12023 sw t3,64(sp) -800037c4: 0bd12a23 sw t4,180(sp) -800037c8: 03d12223 sw t4,36(sp) -800037cc: 0be12c23 sw t5,184(sp) -800037d0: 03e12023 sw t5,32(sp) -800037d4: 0a612e23 sw t1,188(sp) -800037d8: 00612e23 sw t1,28(sp) -800037dc: 6c9020ef jal ra,800066a4 <_ldtoa_r> -800037e0: 04700793 li a5,71 -800037e4: 01c12303 lw t1,28(sp) -800037e8: 02012f03 lw t5,32(sp) -800037ec: 02412e83 lw t4,36(sp) -800037f0: 04012e03 lw t3,64(sp) -800037f4: 05012883 lw a7,80(sp) -800037f8: 00050b13 mv s6,a0 -800037fc: 08fb9063 bne s7,a5,8000387c <_vfprintf_r+0x2464> -80003800: 02812783 lw a5,40(sp) -80003804: 0017f793 andi a5,a5,1 -80003808: 2e079663 bnez a5,80003af4 <_vfprintf_r+0x26dc> -8000380c: 04700793 li a5,71 -80003810: 0dc12703 lw a4,220(sp) -80003814: 04f12223 sw a5,68(sp) -80003818: a44fe06f j 80001a5c <_vfprintf_r+0x644> -8000381c: 0b010a93 addi s5,sp,176 -80003820: 0dc10813 addi a6,sp,220 -80003824: 0d010793 addi a5,sp,208 -80003828: 0cc10713 addi a4,sp,204 -8000382c: 000d8693 mv a3,s11 -80003830: 00300613 li a2,3 -80003834: 000a8593 mv a1,s5 -80003838: 000d0513 mv a0,s10 -8000383c: 05112823 sw a7,80(sp) -80003840: 0bc12823 sw t3,176(sp) -80003844: 05c12023 sw t3,64(sp) -80003848: 0bd12a23 sw t4,180(sp) -8000384c: 03d12223 sw t4,36(sp) -80003850: 0be12c23 sw t5,184(sp) -80003854: 03e12023 sw t5,32(sp) -80003858: 0a612e23 sw t1,188(sp) -8000385c: 00612e23 sw t1,28(sp) -80003860: 645020ef jal ra,800066a4 <_ldtoa_r> -80003864: 01c12303 lw t1,28(sp) -80003868: 02012f03 lw t5,32(sp) -8000386c: 02412e83 lw t4,36(sp) -80003870: 04012e03 lw t3,64(sp) -80003874: 05012883 lw a7,80(sp) -80003878: 00050b13 mv s6,a0 -8000387c: 04600793 li a5,70 -80003880: 01bb0933 add s2,s6,s11 -80003884: 26fb9e63 bne s7,a5,80003b00 <_vfprintf_r+0x26e8> -80003888: 000b4683 lbu a3,0(s6) -8000388c: 03000793 li a5,48 -80003890: 50f68663 beq a3,a5,80003d9c <_vfprintf_r+0x2984> -80003894: 0a010c93 addi s9,sp,160 -80003898: 0cc12783 lw a5,204(sp) -8000389c: 00f90933 add s2,s2,a5 -800038a0: 960fe06f j 80001a00 <_vfprintf_r+0x5e8> -800038a4: 02d00793 li a5,45 -800038a8: 0cf103a3 sb a5,199(sp) -800038ac: da0ff06f j 80002e4c <_vfprintf_r+0x1a34> -800038b0: 0e410613 addi a2,sp,228 -800038b4: 000c0593 mv a1,s8 -800038b8: 000d0513 mv a0,s10 -800038bc: 4dd080ef jal ra,8000c598 <__sprint_r> -800038c0: 00050463 beqz a0,800038c8 <_vfprintf_r+0x24b0> -800038c4: b85fe06f j 80002448 <_vfprintf_r+0x1030> -800038c8: 0cc12483 lw s1,204(sp) -800038cc: 0ec12783 lw a5,236(sp) -800038d0: 10c10893 addi a7,sp,268 -800038d4: e69fe06f j 8000273c <_vfprintf_r+0x1324> -800038d8: 0c714783 lbu a5,199(sp) -800038dc: 01212a23 sw s2,20(sp) -800038e0: 02012423 sw zero,40(sp) -800038e4: 02012223 sw zero,36(sp) -800038e8: 00012e23 sw zero,28(sp) -800038ec: 000d8a93 mv s5,s11 -800038f0: 000d8c93 mv s9,s11 -800038f4: 00000d93 li s11,0 -800038f8: 00078463 beqz a5,80003900 <_vfprintf_r+0x24e8> -800038fc: cf8fe06f j 80001df4 <_vfprintf_r+0x9dc> -80003900: d51fd06f j 80001650 <_vfprintf_r+0x238> -80003904: 02812783 lw a5,40(sp) -80003908: 01c12703 lw a4,28(sp) -8000390c: 0017f793 andi a5,a5,1 -80003910: 01b7e7b3 or a5,a5,s11 -80003914: 50e05663 blez a4,80003e20 <_vfprintf_r+0x2a08> -80003918: 44079063 bnez a5,80003d58 <_vfprintf_r+0x2940> -8000391c: 01c12c83 lw s9,28(sp) -80003920: 06600493 li s1,102 -80003924: 02812783 lw a5,40(sp) -80003928: 4007f793 andi a5,a5,1024 -8000392c: 3a079263 bnez a5,80003cd0 <_vfprintf_r+0x28b8> -80003930: fffcca93 not s5,s9 -80003934: 41fada93 srai s5,s5,0x1f -80003938: 015cfab3 and s5,s9,s5 -8000393c: de1ff06f j 8000371c <_vfprintf_r+0x2304> -80003940: 80015737 lui a4,0x80015 -80003944: c7070b13 addi s6,a4,-912 # 80014c70 <__BSS_END__+0xffffe034> -80003948: d14ff06f j 80002e5c <_vfprintf_r+0x1a44> -8000394c: 0e410613 addi a2,sp,228 -80003950: 000c0593 mv a1,s8 -80003954: 000d0513 mv a0,s10 -80003958: 441080ef jal ra,8000c598 <__sprint_r> -8000395c: 00050463 beqz a0,80003964 <_vfprintf_r+0x254c> -80003960: ae9fe06f j 80002448 <_vfprintf_r+0x1030> -80003964: 0cc12483 lw s1,204(sp) -80003968: 02012703 lw a4,32(sp) -8000396c: 0ec12783 lw a5,236(sp) -80003970: 10c10893 addi a7,sp,268 -80003974: 409704b3 sub s1,a4,s1 -80003978: e11fe06f j 80002788 <_vfprintf_r+0x1370> -8000397c: 02012783 lw a5,32(sp) -80003980: 02c12703 lw a4,44(sp) -80003984: 06700493 li s1,103 -80003988: 00e78cb3 add s9,a5,a4 -8000398c: 01c12783 lw a5,28(sp) -80003990: f8f04ae3 bgtz a5,80003924 <_vfprintf_r+0x250c> -80003994: 40fc8cb3 sub s9,s9,a5 -80003998: 001c8c93 addi s9,s9,1 -8000399c: fffcca93 not s5,s9 -800039a0: 41fada93 srai s5,s5,0x1f -800039a4: 015cfab3 and s5,s9,s5 -800039a8: d75ff06f j 8000371c <_vfprintf_r+0x2304> -800039ac: 800156b7 lui a3,0x80015 -800039b0: e1868e93 addi t4,a3,-488 # 80014e18 <__BSS_END__+0xffffe1dc> -800039b4: b50fe06f j 80001d04 <_vfprintf_r+0x8ec> -800039b8: fff00793 li a5,-1 -800039bc: 00f12623 sw a5,12(sp) -800039c0: dcdfd06f j 8000178c <_vfprintf_r+0x374> -800039c4: ff000613 li a2,-16 -800039c8: 40b004b3 neg s1,a1 -800039cc: 06c5d263 bge a1,a2,80003a30 <_vfprintf_r+0x2618> -800039d0: 01000913 li s2,16 -800039d4: 00700c93 li s9,7 -800039d8: 00c0006f j 800039e4 <_vfprintf_r+0x25cc> -800039dc: ff048493 addi s1,s1,-16 -800039e0: 04995863 bge s2,s1,80003a30 <_vfprintf_r+0x2618> -800039e4: 00812703 lw a4,8(sp) -800039e8: 01078793 addi a5,a5,16 # 80000010 <__BSS_END__+0xfffe93d4> -800039ec: 00168693 addi a3,a3,1 -800039f0: 00e8a023 sw a4,0(a7) -800039f4: 0128a223 sw s2,4(a7) -800039f8: 0ef12623 sw a5,236(sp) -800039fc: 0ed12423 sw a3,232(sp) -80003a00: 00888893 addi a7,a7,8 -80003a04: fcdcdce3 bge s9,a3,800039dc <_vfprintf_r+0x25c4> -80003a08: 0e410613 addi a2,sp,228 -80003a0c: 000c0593 mv a1,s8 -80003a10: 000d0513 mv a0,s10 -80003a14: 385080ef jal ra,8000c598 <__sprint_r> -80003a18: 00050463 beqz a0,80003a20 <_vfprintf_r+0x2608> -80003a1c: a2dfe06f j 80002448 <_vfprintf_r+0x1030> -80003a20: 0ec12783 lw a5,236(sp) -80003a24: 0e812683 lw a3,232(sp) -80003a28: 10c10893 addi a7,sp,268 -80003a2c: fb1ff06f j 800039dc <_vfprintf_r+0x25c4> -80003a30: 00812703 lw a4,8(sp) -80003a34: 009787b3 add a5,a5,s1 -80003a38: 00168693 addi a3,a3,1 -80003a3c: 00e8a023 sw a4,0(a7) -80003a40: 0098a223 sw s1,4(a7) -80003a44: 0ef12623 sw a5,236(sp) -80003a48: 0ed12423 sw a3,232(sp) -80003a4c: 00700613 li a2,7 -80003a50: b2d65a63 bge a2,a3,80002d84 <_vfprintf_r+0x196c> -80003a54: 0e410613 addi a2,sp,228 -80003a58: 000c0593 mv a1,s8 -80003a5c: 000d0513 mv a0,s10 -80003a60: 339080ef jal ra,8000c598 <__sprint_r> -80003a64: 00050463 beqz a0,80003a6c <_vfprintf_r+0x2654> -80003a68: 9e1fe06f j 80002448 <_vfprintf_r+0x1030> -80003a6c: 0ec12783 lw a5,236(sp) -80003a70: 0e812683 lw a3,232(sp) -80003a74: 10c10893 addi a7,sp,268 -80003a78: 9ccfe06f j 80001c44 <_vfprintf_r+0x82c> -80003a7c: 000a0b93 mv s7,s4 -80003a80: e20fe06f j 800020a0 <_vfprintf_r+0xc88> -80003a84: 05412783 lw a5,84(sp) -80003a88: 000b8693 mv a3,s7 -80003a8c: 0cf12e23 sw a5,220(sp) -80003a90: 02412783 lw a5,36(sp) -80003a94: fffbc603 lbu a2,-1(s7) -80003a98: 00f7c583 lbu a1,15(a5) -80003a9c: 02b61063 bne a2,a1,80003abc <_vfprintf_r+0x26a4> -80003aa0: 03000513 li a0,48 -80003aa4: fea68fa3 sb a0,-1(a3) -80003aa8: 0dc12683 lw a3,220(sp) -80003aac: fff68793 addi a5,a3,-1 -80003ab0: 0cf12e23 sw a5,220(sp) -80003ab4: fff6c603 lbu a2,-1(a3) -80003ab8: fec586e3 beq a1,a2,80003aa4 <_vfprintf_r+0x268c> -80003abc: 00160593 addi a1,a2,1 -80003ac0: 03900513 li a0,57 -80003ac4: 0ff5f593 andi a1,a1,255 -80003ac8: 00a60663 beq a2,a0,80003ad4 <_vfprintf_r+0x26bc> -80003acc: feb68fa3 sb a1,-1(a3) -80003ad0: ba5ff06f j 80003674 <_vfprintf_r+0x225c> -80003ad4: 02412783 lw a5,36(sp) -80003ad8: 00a7c583 lbu a1,10(a5) -80003adc: feb68fa3 sb a1,-1(a3) -80003ae0: b95ff06f j 80003674 <_vfprintf_r+0x225c> -80003ae4: 03000793 li a5,48 -80003ae8: 0cf10423 sb a5,200(sp) -80003aec: 07800793 li a5,120 -80003af0: fd8ff06f j 800032c8 <_vfprintf_r+0x1eb0> -80003af4: 04700793 li a5,71 -80003af8: 01bb0933 add s2,s6,s11 -80003afc: 04f12223 sw a5,68(sp) -80003b00: 0a010c93 addi s9,sp,160 -80003b04: efdfd06f j 80001a00 <_vfprintf_r+0x5e8> -80003b08: 001d8593 addi a1,s11,1 -80003b0c: 000d0513 mv a0,s10 -80003b10: 01112823 sw a7,16(sp) -80003b14: 094040ef jal ra,80007ba8 <_malloc_r> -80003b18: 01012883 lw a7,16(sp) -80003b1c: 00050b13 mv s6,a0 -80003b20: 36050063 beqz a0,80003e80 <_vfprintf_r+0x2a68> -80003b24: 00a12823 sw a0,16(sp) -80003b28: fbcff06f j 800032e4 <_vfprintf_r+0x1ecc> -80003b2c: 000d9463 bnez s11,80003b34 <_vfprintf_r+0x271c> -80003b30: 00100d93 li s11,1 -80003b34: 0fc12303 lw t1,252(sp) -80003b38: 0f012e03 lw t3,240(sp) -80003b3c: 0f412e83 lw t4,244(sp) -80003b40: 0f812f03 lw t5,248(sp) -80003b44: 100a6913 ori s2,s4,256 -80003b48: c00346e3 bltz t1,80003754 <_vfprintf_r+0x233c> -80003b4c: 0b010a93 addi s5,sp,176 -80003b50: 0dc10813 addi a6,sp,220 -80003b54: 0d010793 addi a5,sp,208 -80003b58: 0cc10713 addi a4,sp,204 -80003b5c: 000d8693 mv a3,s11 -80003b60: 00200613 li a2,2 -80003b64: 000a8593 mv a1,s5 -80003b68: 000d0513 mv a0,s10 -80003b6c: 05112223 sw a7,68(sp) -80003b70: 0bc12823 sw t3,176(sp) -80003b74: 05c12023 sw t3,64(sp) -80003b78: 0bd12a23 sw t4,180(sp) -80003b7c: 03d12223 sw t4,36(sp) -80003b80: 0be12c23 sw t5,184(sp) -80003b84: 03e12023 sw t5,32(sp) -80003b88: 0a612e23 sw t1,188(sp) -80003b8c: 00612e23 sw t1,28(sp) -80003b90: 315020ef jal ra,800066a4 <_ldtoa_r> -80003b94: 01c12303 lw t1,28(sp) -80003b98: 03412423 sw s4,40(sp) -80003b9c: 02012f03 lw t5,32(sp) -80003ba0: 02412e83 lw t4,36(sp) -80003ba4: 04012e03 lw t3,64(sp) -80003ba8: 04412883 lw a7,68(sp) -80003bac: 00050b13 mv s6,a0 -80003bb0: 00090a13 mv s4,s2 -80003bb4: 04012c23 sw zero,88(sp) -80003bb8: 00012823 sw zero,16(sp) -80003bbc: c45ff06f j 80003800 <_vfprintf_r+0x23e8> -80003bc0: 00600d93 li s11,6 -80003bc4: d8dfd06f j 80001950 <_vfprintf_r+0x538> -80003bc8: 0b010a93 addi s5,sp,176 -80003bcc: 000a8513 mv a0,s5 -80003bd0: 05112a23 sw a7,84(sp) -80003bd4: 0bc12823 sw t3,176(sp) -80003bd8: 0bd12a23 sw t4,180(sp) -80003bdc: 0be12c23 sw t5,184(sp) -80003be0: 0a612e23 sw t1,188(sp) -80003be4: 299100ef jal ra,8001467c <__trunctfdf2> -80003be8: 0cc10613 addi a2,sp,204 -80003bec: 181050ef jal ra,8000956c -80003bf0: 00058613 mv a2,a1 -80003bf4: 00050593 mv a1,a0 -80003bf8: 000a8513 mv a0,s5 -80003bfc: 08d100ef jal ra,80014488 <__extenddftf2> -80003c00: 0b012783 lw a5,176(sp) -80003c04: 0a010c93 addi s9,sp,160 -80003c08: 09010913 addi s2,sp,144 -80003c0c: 08f12823 sw a5,144(sp) -80003c10: 0b412783 lw a5,180(sp) -80003c14: 08010613 addi a2,sp,128 -80003c18: 00090593 mv a1,s2 -80003c1c: 08f12a23 sw a5,148(sp) -80003c20: 0b812783 lw a5,184(sp) -80003c24: 000c8513 mv a0,s9 -80003c28: 04c12023 sw a2,64(sp) -80003c2c: 08f12c23 sw a5,152(sp) -80003c30: 0bc12783 lw a5,188(sp) -80003c34: 08012023 sw zero,128(sp) -80003c38: 08012223 sw zero,132(sp) -80003c3c: 08f12e23 sw a5,156(sp) -80003c40: 3ffc07b7 lui a5,0x3ffc0 -80003c44: 08f12623 sw a5,140(sp) -80003c48: 08012423 sw zero,136(sp) -80003c4c: 0b40e0ef jal ra,80011d00 <__multf3> -80003c50: 0a012803 lw a6,160(sp) -80003c54: 0a412e03 lw t3,164(sp) -80003c58: 0a812e83 lw t4,168(sp) -80003c5c: 0ac12f03 lw t5,172(sp) -80003c60: 000c8593 mv a1,s9 -80003c64: 000a8513 mv a0,s5 -80003c68: 0b012823 sw a6,176(sp) -80003c6c: 05012823 sw a6,80(sp) -80003c70: 0bc12a23 sw t3,180(sp) -80003c74: 03c12223 sw t3,36(sp) -80003c78: 0bd12c23 sw t4,184(sp) -80003c7c: 03d12023 sw t4,32(sp) -80003c80: 0be12e23 sw t5,188(sp) -80003c84: 01e12e23 sw t5,28(sp) -80003c88: 0a012023 sw zero,160(sp) -80003c8c: 0a012223 sw zero,164(sp) -80003c90: 0a012423 sw zero,168(sp) -80003c94: 0a012623 sw zero,172(sp) -80003c98: 5150d0ef jal ra,800119ac <__eqtf2> -80003c9c: 01c12f03 lw t5,28(sp) -80003ca0: 02012e83 lw t4,32(sp) -80003ca4: 02412e03 lw t3,36(sp) -80003ca8: 05012803 lw a6,80(sp) -80003cac: 05412883 lw a7,84(sp) -80003cb0: 00051663 bnez a0,80003cbc <_vfprintf_r+0x28a4> -80003cb4: 00100793 li a5,1 -80003cb8: 0cf12623 sw a5,204(sp) -80003cbc: 800157b7 lui a5,0x80015 -80003cc0: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -80003cc4: 02f12223 sw a5,36(sp) -80003cc8: f54ff06f j 8000341c <_vfprintf_r+0x2004> -80003ccc: 06700493 li s1,103 -80003cd0: 03c12603 lw a2,60(sp) -80003cd4: 0ff00693 li a3,255 -80003cd8: 00064783 lbu a5,0(a2) -80003cdc: 1ad78a63 beq a5,a3,80003e90 <_vfprintf_r+0x2a78> -80003ce0: 01c12703 lw a4,28(sp) -80003ce4: 00000513 li a0,0 -80003ce8: 00000593 li a1,0 -80003cec: 00e7de63 bge a5,a4,80003d08 <_vfprintf_r+0x28f0> -80003cf0: 40f70733 sub a4,a4,a5 -80003cf4: 00164783 lbu a5,1(a2) -80003cf8: 04078463 beqz a5,80003d40 <_vfprintf_r+0x2928> -80003cfc: 00158593 addi a1,a1,1 -80003d00: 00160613 addi a2,a2,1 -80003d04: fed794e3 bne a5,a3,80003cec <_vfprintf_r+0x28d4> -80003d08: 02c12e23 sw a2,60(sp) -80003d0c: 00e12e23 sw a4,28(sp) -80003d10: 02b12223 sw a1,36(sp) -80003d14: 02a12423 sw a0,40(sp) -80003d18: 02812703 lw a4,40(sp) -80003d1c: 02412783 lw a5,36(sp) -80003d20: 00e787b3 add a5,a5,a4 -80003d24: 04812703 lw a4,72(sp) -80003d28: 02e787b3 mul a5,a5,a4 -80003d2c: 01978cb3 add s9,a5,s9 -80003d30: fffcca93 not s5,s9 -80003d34: 41fada93 srai s5,s5,0x1f -80003d38: 015cfab3 and s5,s9,s5 -80003d3c: e6dfd06f j 80001ba8 <_vfprintf_r+0x790> -80003d40: 00064783 lbu a5,0(a2) -80003d44: 00150513 addi a0,a0,1 -80003d48: fbdff06f j 80003d04 <_vfprintf_r+0x28ec> -80003d4c: 00012823 sw zero,16(sp) -80003d50: 00078a13 mv s4,a5 -80003d54: a0dff06f j 80003760 <_vfprintf_r+0x2348> -80003d58: 02c12783 lw a5,44(sp) -80003d5c: 06600493 li s1,102 -80003d60: 00f70cb3 add s9,a4,a5 -80003d64: 01bc8cb3 add s9,s9,s11 -80003d68: bbdff06f j 80003924 <_vfprintf_r+0x250c> -80003d6c: 0d610693 addi a3,sp,214 -80003d70: 00061863 bnez a2,80003d80 <_vfprintf_r+0x2968> -80003d74: 03000693 li a3,48 -80003d78: 0cd10b23 sb a3,214(sp) -80003d7c: 0d710693 addi a3,sp,215 -80003d80: 1b010713 addi a4,sp,432 -80003d84: 03078793 addi a5,a5,48 -80003d88: 40e68633 sub a2,a3,a4 -80003d8c: 00f68023 sb a5,0(a3) -80003d90: 0dd60793 addi a5,a2,221 -80003d94: 02f12c23 sw a5,56(sp) -80003d98: dcdfd06f j 80001b64 <_vfprintf_r+0x74c> -80003d9c: 0a010c93 addi s9,sp,160 -80003da0: 000c8593 mv a1,s9 -80003da4: 000a8513 mv a0,s5 -80003da8: 05112823 sw a7,80(sp) -80003dac: 0bc12823 sw t3,176(sp) -80003db0: 05c12023 sw t3,64(sp) -80003db4: 0bd12a23 sw t4,180(sp) -80003db8: 03d12223 sw t4,36(sp) -80003dbc: 0be12c23 sw t5,184(sp) -80003dc0: 03e12023 sw t5,32(sp) -80003dc4: 0a612e23 sw t1,188(sp) -80003dc8: 00612e23 sw t1,28(sp) -80003dcc: 0a012023 sw zero,160(sp) -80003dd0: 0a012223 sw zero,164(sp) -80003dd4: 0a012423 sw zero,168(sp) -80003dd8: 0a012623 sw zero,172(sp) -80003ddc: 3d10d0ef jal ra,800119ac <__eqtf2> -80003de0: 01c12303 lw t1,28(sp) -80003de4: 02012f03 lw t5,32(sp) -80003de8: 02412e83 lw t4,36(sp) -80003dec: 04012e03 lw t3,64(sp) -80003df0: 05012883 lw a7,80(sp) -80003df4: aa0502e3 beqz a0,80003898 <_vfprintf_r+0x2480> -80003df8: 00100793 li a5,1 -80003dfc: 41b787b3 sub a5,a5,s11 -80003e00: 0cf12623 sw a5,204(sp) -80003e04: 00f90933 add s2,s2,a5 -80003e08: bf9fd06f j 80001a00 <_vfprintf_r+0x5e8> -80003e0c: 02812783 lw a5,40(sp) -80003e10: 0017f793 andi a5,a5,1 -80003e14: 00079463 bnez a5,80003e1c <_vfprintf_r+0x2a04> -80003e18: d6dfd06f j 80001b84 <_vfprintf_r+0x76c> -80003e1c: d61fd06f j 80001b7c <_vfprintf_r+0x764> -80003e20: 00079a63 bnez a5,80003e34 <_vfprintf_r+0x2a1c> -80003e24: 00100a93 li s5,1 -80003e28: 06600493 li s1,102 -80003e2c: 00100c93 li s9,1 -80003e30: 8edff06f j 8000371c <_vfprintf_r+0x2304> -80003e34: 02c12783 lw a5,44(sp) -80003e38: 06600493 li s1,102 -80003e3c: 00178c93 addi s9,a5,1 -80003e40: 01bc8cb3 add s9,s9,s11 -80003e44: fffcca93 not s5,s9 -80003e48: 41fada93 srai s5,s5,0x1f -80003e4c: 015cfab3 and s5,s9,s5 -80003e50: 8cdff06f j 8000371c <_vfprintf_r+0x2304> -80003e54: 00088713 mv a4,a7 -80003e58: bddfe06f j 80002a34 <_vfprintf_r+0x161c> -80003e5c: 01412783 lw a5,20(sp) -80003e60: 0007ad83 lw s11,0(a5) -80003e64: 00478793 addi a5,a5,4 -80003e68: 000dd463 bgez s11,80003e70 <_vfprintf_r+0x2a58> -80003e6c: fff00d93 li s11,-1 -80003e70: 00144483 lbu s1,1(s0) -80003e74: 00f12a23 sw a5,20(sp) -80003e78: 00070413 mv s0,a4 -80003e7c: f54fd06f j 800015d0 <_vfprintf_r+0x1b8> -80003e80: 00cc5783 lhu a5,12(s8) -80003e84: 0407e793 ori a5,a5,64 -80003e88: 00fc1623 sh a5,12(s8) -80003e8c: 8f1fd06f j 8000177c <_vfprintf_r+0x364> -80003e90: 02012423 sw zero,40(sp) -80003e94: 02012223 sw zero,36(sp) -80003e98: e81ff06f j 80003d18 <_vfprintf_r+0x2900> -80003e9c: 00200793 li a5,2 -80003ea0: 02f12c23 sw a5,56(sp) -80003ea4: cc1fd06f j 80001b64 <_vfprintf_r+0x74c> +80003144: cc4ff06f j 80002608 <_vfprintf_r+0x12b4> +80003148: 00600c93 li s9,6 +8000314c: 945ff06f j 80002a90 <_vfprintf_r+0x173c> +80003150: 02012683 lw a3,32(sp) +80003154: 00db0733 add a4,s6,a3 +80003158: 409684b3 sub s1,a3,s1 +8000315c: 41b70833 sub a6,a4,s11 +80003160: 00048913 mv s2,s1 +80003164: d6985063 bge a6,s1,800026c4 <_vfprintf_r+0x1370> +80003168: 00080913 mv s2,a6 +8000316c: d58ff06f j 800026c4 <_vfprintf_r+0x1370> +80003170: 00c12783 lw a5,12(sp) +80003174: 00040b13 mv s6,s0 +80003178: 00f71023 sh a5,0(a4) +8000317c: d28fe06f j 800016a4 <_vfprintf_r+0x350> +80003180: 01412783 lw a5,20(sp) +80003184: 00000c93 li s9,0 +80003188: 00e12a23 sw a4,20(sp) +8000318c: 0007a903 lw s2,0(a5) +80003190: d91fe06f j 80001f20 <_vfprintf_r+0xbcc> +80003194: 01412783 lw a5,20(sp) +80003198: 00e12a23 sw a4,20(sp) +8000319c: 0007a903 lw s2,0(a5) +800031a0: 41f95c93 srai s9,s2,0x1f +800031a4: 000c8793 mv a5,s9 +800031a8: df5fe06f j 80001f9c <_vfprintf_r+0xc48> +800031ac: 01412783 lw a5,20(sp) +800031b0: 00000c93 li s9,0 +800031b4: 00e12a23 sw a4,20(sp) +800031b8: 0007a903 lw s2,0(a5) +800031bc: 00100793 li a5,1 +800031c0: c25fe06f j 80001de4 <_vfprintf_r+0xa90> +800031c4: 01412783 lw a5,20(sp) +800031c8: 00000c93 li s9,0 +800031cc: 00e12a23 sw a4,20(sp) +800031d0: 0007a903 lw s2,0(a5) +800031d4: 829ff06f j 800029fc <_vfprintf_r+0x16a8> +800031d8: 0e410613 addi a2,sp,228 +800031dc: 000c0593 mv a1,s8 +800031e0: 000d0513 mv a0,s10 +800031e4: 2f0090ef jal ra,8000c4d4 <__sprint_r> +800031e8: cd0fe06f j 800016b8 <_vfprintf_r+0x364> +800031ec: 02d00793 li a5,45 +800031f0: 0cf103a3 sb a5,199(sp) +800031f4: cadff06f j 80002ea0 <_vfprintf_r+0x1b4c> +800031f8: 03000793 li a5,48 +800031fc: 0cf10423 sb a5,200(sp) +80003200: 05800793 li a5,88 +80003204: 002a6713 ori a4,s4,2 +80003208: 0cf104a3 sb a5,201(sp) +8000320c: 02e12423 sw a4,40(sp) +80003210: 06300793 li a5,99 +80003214: 00012823 sw zero,16(sp) +80003218: 14c10b13 addi s6,sp,332 +8000321c: 03b7c4e3 blt a5,s11,80003a44 <_vfprintf_r+0x26f0> +80003220: 0fc12303 lw t1,252(sp) +80003224: fdf4fb93 andi s7,s1,-33 +80003228: 05712223 sw s7,68(sp) +8000322c: 04012c23 sw zero,88(sp) +80003230: 0f012e03 lw t3,240(sp) +80003234: 0f412e83 lw t4,244(sp) +80003238: 0f812f03 lw t5,248(sp) +8000323c: 102a6a13 ori s4,s4,258 +80003240: 44034e63 bltz t1,8000369c <_vfprintf_r+0x2348> +80003244: 06100793 li a5,97 +80003248: 0af48ee3 beq s1,a5,80003b04 <_vfprintf_r+0x27b0> +8000324c: 04100793 li a5,65 +80003250: 00f48463 beq s1,a5,80003258 <_vfprintf_r+0x1f04> +80003254: e64fe06f j 800018b8 <_vfprintf_r+0x564> +80003258: 0b010a93 addi s5,sp,176 +8000325c: 000a8513 mv a0,s5 +80003260: 05112a23 sw a7,84(sp) +80003264: 0bc12823 sw t3,176(sp) +80003268: 0bd12a23 sw t4,180(sp) +8000326c: 0be12c23 sw t5,184(sp) +80003270: 0a612e23 sw t1,188(sp) +80003274: 344110ef jal ra,800145b8 <__trunctfdf2> +80003278: 0cc10613 addi a2,sp,204 +8000327c: 22c060ef jal ra,800094a8 +80003280: 00058613 mv a2,a1 +80003284: 00050593 mv a1,a0 +80003288: 000a8513 mv a0,s5 +8000328c: 138110ef jal ra,800143c4 <__extenddftf2> +80003290: 0b012783 lw a5,176(sp) +80003294: 0a010c93 addi s9,sp,160 +80003298: 09010913 addi s2,sp,144 +8000329c: 08f12823 sw a5,144(sp) +800032a0: 0b412783 lw a5,180(sp) +800032a4: 08010613 addi a2,sp,128 +800032a8: 00090593 mv a1,s2 +800032ac: 08f12a23 sw a5,148(sp) +800032b0: 0b812783 lw a5,184(sp) +800032b4: 000c8513 mv a0,s9 +800032b8: 04c12023 sw a2,64(sp) +800032bc: 08f12c23 sw a5,152(sp) +800032c0: 0bc12783 lw a5,188(sp) +800032c4: 08012023 sw zero,128(sp) +800032c8: 08012223 sw zero,132(sp) +800032cc: 08f12e23 sw a5,156(sp) +800032d0: 3ffc07b7 lui a5,0x3ffc0 +800032d4: 08f12623 sw a5,140(sp) +800032d8: 08012423 sw zero,136(sp) +800032dc: 1610e0ef jal ra,80011c3c <__multf3> +800032e0: 0a012803 lw a6,160(sp) +800032e4: 0a412e03 lw t3,164(sp) +800032e8: 0a812e83 lw t4,168(sp) +800032ec: 0ac12f03 lw t5,172(sp) +800032f0: 000c8593 mv a1,s9 +800032f4: 000a8513 mv a0,s5 +800032f8: 0b012823 sw a6,176(sp) +800032fc: 05012823 sw a6,80(sp) +80003300: 0bc12a23 sw t3,180(sp) +80003304: 03c12223 sw t3,36(sp) +80003308: 0bd12c23 sw t4,184(sp) +8000330c: 03d12023 sw t4,32(sp) +80003310: 0be12e23 sw t5,188(sp) +80003314: 01e12e23 sw t5,28(sp) +80003318: 0a012023 sw zero,160(sp) +8000331c: 0a012223 sw zero,164(sp) +80003320: 0a012423 sw zero,168(sp) +80003324: 0a012623 sw zero,172(sp) +80003328: 5c00e0ef jal ra,800118e8 <__eqtf2> +8000332c: 01c12f03 lw t5,28(sp) +80003330: 02012e83 lw t4,32(sp) +80003334: 02412e03 lw t3,36(sp) +80003338: 05012803 lw a6,80(sp) +8000333c: 05412883 lw a7,84(sp) +80003340: 00051663 bnez a0,8000334c <_vfprintf_r+0x1ff8> +80003344: 00100793 li a5,1 +80003348: 0cf12623 sw a5,204(sp) +8000334c: 800157b7 lui a5,0x80015 +80003350: bb878793 addi a5,a5,-1096 # 80014bb8 <__BSS_END__+0xffffdf7c> +80003354: 02f12223 sw a5,36(sp) +80003358: fffd8693 addi a3,s11,-1 +8000335c: 05412e23 sw s4,92(sp) +80003360: 06912223 sw s1,100(sp) +80003364: 07b12623 sw s11,108(sp) +80003368: 07a12a23 sw s10,116(sp) +8000336c: 07812c23 sw s8,120(sp) +80003370: 06812023 sw s0,96(sp) +80003374: 07312423 sw s3,104(sp) +80003378: 07112823 sw a7,112(sp) +8000337c: 000b0c13 mv s8,s6 +80003380: 00068b93 mv s7,a3 +80003384: 07612e23 sw s6,124(sp) +80003388: 00080d13 mv s10,a6 +8000338c: 000e0d93 mv s11,t3 +80003390: 000e8493 mv s1,t4 +80003394: 000f0a13 mv s4,t5 +80003398: 0480006f j 800033e0 <_vfprintf_r+0x208c> +8000339c: 000c8593 mv a1,s9 +800033a0: 000a8513 mv a0,s5 +800033a4: 02c12023 sw a2,32(sp) +800033a8: 01f12e23 sw t6,28(sp) +800033ac: 0bf12c23 sw t6,184(sp) +800033b0: 0ac12e23 sw a2,188(sp) +800033b4: 0b612823 sw s6,176(sp) +800033b8: 0b312a23 sw s3,180(sp) +800033bc: 0a012023 sw zero,160(sp) +800033c0: 0a012223 sw zero,164(sp) +800033c4: 0a012423 sw zero,168(sp) +800033c8: 0a012623 sw zero,172(sp) +800033cc: 51c0e0ef jal ra,800118e8 <__eqtf2> +800033d0: 01c12f83 lw t6,28(sp) +800033d4: 02012603 lw a2,32(sp) +800033d8: fffb8b93 addi s7,s7,-1 +800033dc: 0e050263 beqz a0,800034c0 <_vfprintf_r+0x216c> +800033e0: 400307b7 lui a5,0x40030 +800033e4: 00090613 mv a2,s2 +800033e8: 000c8593 mv a1,s9 +800033ec: 000a8513 mv a0,s5 +800033f0: 08f12e23 sw a5,156(sp) +800033f4: 0ba12023 sw s10,160(sp) +800033f8: 0bb12223 sw s11,164(sp) +800033fc: 0a912423 sw s1,168(sp) +80003400: 0b412623 sw s4,172(sp) +80003404: 08012823 sw zero,144(sp) +80003408: 08012a23 sw zero,148(sp) +8000340c: 08012c23 sw zero,152(sp) +80003410: 02d0e0ef jal ra,80011c3c <__multf3> +80003414: 000a8513 mv a0,s5 +80003418: 549100ef jal ra,80014160 <__fixtfsi> +8000341c: 00050593 mv a1,a0 +80003420: 00050413 mv s0,a0 +80003424: 000a8513 mv a0,s5 +80003428: 0b012983 lw s3,176(sp) +8000342c: 0b412483 lw s1,180(sp) +80003430: 0b812b03 lw s6,184(sp) +80003434: 0bc12a03 lw s4,188(sp) +80003438: 63d100ef jal ra,80014274 <__floatsitf> +8000343c: 0b012703 lw a4,176(sp) +80003440: 04012603 lw a2,64(sp) +80003444: 00090593 mv a1,s2 +80003448: 08e12023 sw a4,128(sp) +8000344c: 0b412703 lw a4,180(sp) +80003450: 000c8513 mv a0,s9 +80003454: 09312823 sw s3,144(sp) +80003458: 08e12223 sw a4,132(sp) +8000345c: 0b812703 lw a4,184(sp) +80003460: 08912a23 sw s1,148(sp) +80003464: 09612c23 sw s6,152(sp) +80003468: 08e12423 sw a4,136(sp) +8000346c: 0bc12703 lw a4,188(sp) +80003470: 09412e23 sw s4,156(sp) +80003474: 08e12623 sw a4,140(sp) +80003478: 7c80f0ef jal ra,80012c40 <__subtf3> +8000347c: 02412783 lw a5,36(sp) +80003480: 0a012b03 lw s6,160(sp) +80003484: 0a412983 lw s3,164(sp) +80003488: 00878733 add a4,a5,s0 +8000348c: 00074703 lbu a4,0(a4) +80003490: 0a812f83 lw t6,168(sp) +80003494: 0ac12603 lw a2,172(sp) +80003498: 05812a23 sw s8,84(sp) +8000349c: 00ec0023 sb a4,0(s8) +800034a0: 05712823 sw s7,80(sp) +800034a4: fff00793 li a5,-1 +800034a8: 001c0c13 addi s8,s8,1 +800034ac: 000b0d13 mv s10,s6 +800034b0: 00098d93 mv s11,s3 +800034b4: 000f8493 mv s1,t6 +800034b8: 00060a13 mv s4,a2 +800034bc: eefb90e3 bne s7,a5,8000339c <_vfprintf_r+0x2048> +800034c0: 07012883 lw a7,112(sp) +800034c4: 000b0393 mv t2,s6 +800034c8: 00098293 mv t0,s3 +800034cc: 3ffe0937 lui s2,0x3ffe0 +800034d0: 000c8593 mv a1,s9 +800034d4: 000a8513 mv a0,s5 +800034d8: 03112023 sw a7,32(sp) +800034dc: 00812e23 sw s0,28(sp) +800034e0: 05c12a03 lw s4,92(sp) +800034e4: 06412483 lw s1,100(sp) +800034e8: 06012403 lw s0,96(sp) +800034ec: 0a712823 sw t2,176(sp) +800034f0: 06712223 sw t2,100(sp) +800034f4: 0a512a23 sw t0,180(sp) +800034f8: 06512023 sw t0,96(sp) +800034fc: 0bf12c23 sw t6,184(sp) +80003500: 05f12e23 sw t6,92(sp) +80003504: 0ac12e23 sw a2,188(sp) +80003508: 04c12023 sw a2,64(sp) +8000350c: 0a012023 sw zero,160(sp) +80003510: 0a012223 sw zero,164(sp) +80003514: 0a012423 sw zero,168(sp) +80003518: 0b212623 sw s2,172(sp) +8000351c: 4980e0ef jal ra,800119b4 <__getf2> +80003520: 000c0b93 mv s7,s8 +80003524: 06c12d83 lw s11,108(sp) +80003528: 07412d03 lw s10,116(sp) +8000352c: 07812c03 lw s8,120(sp) +80003530: 07c12b03 lw s6,124(sp) +80003534: 06812983 lw s3,104(sp) +80003538: 02012883 lw a7,32(sp) +8000353c: 48a04263 bgtz a0,800039c0 <_vfprintf_r+0x266c> +80003540: 06412383 lw t2,100(sp) +80003544: 06012283 lw t0,96(sp) +80003548: 05c12f83 lw t6,92(sp) +8000354c: 04012603 lw a2,64(sp) +80003550: 000c8593 mv a1,s9 +80003554: 000a8513 mv a0,s5 +80003558: 0a712823 sw t2,176(sp) +8000355c: 0a512a23 sw t0,180(sp) +80003560: 0bf12c23 sw t6,184(sp) +80003564: 0ac12e23 sw a2,188(sp) +80003568: 0a012023 sw zero,160(sp) +8000356c: 0a012223 sw zero,164(sp) +80003570: 0a012423 sw zero,168(sp) +80003574: 0b212623 sw s2,172(sp) +80003578: 3700e0ef jal ra,800118e8 <__eqtf2> +8000357c: 02012883 lw a7,32(sp) +80003580: 00051863 bnez a0,80003590 <_vfprintf_r+0x223c> +80003584: 01c12783 lw a5,28(sp) +80003588: 0017fc93 andi s9,a5,1 +8000358c: 420c9a63 bnez s9,800039c0 <_vfprintf_r+0x266c> +80003590: 05012783 lw a5,80(sp) +80003594: 03000613 li a2,48 +80003598: 00178693 addi a3,a5,1 # 40030001 <_start-0x3ffcffff> +8000359c: 00db86b3 add a3,s7,a3 +800035a0: 0007c863 bltz a5,800035b0 <_vfprintf_r+0x225c> +800035a4: 001b8b93 addi s7,s7,1 +800035a8: fecb8fa3 sb a2,-1(s7) +800035ac: ff769ce3 bne a3,s7,800035a4 <_vfprintf_r+0x2250> +800035b0: 416b87b3 sub a5,s7,s6 +800035b4: 02f12023 sw a5,32(sp) +800035b8: be8fe06f j 800019a0 <_vfprintf_r+0x64c> +800035bc: 02012703 lw a4,32(sp) +800035c0: 000b0c13 mv s8,s6 +800035c4: 02812b03 lw s6,40(sp) +800035c8: 02812e23 sw s0,60(sp) +800035cc: 01c12a03 lw s4,28(sp) +800035d0: 00eb06b3 add a3,s6,a4 +800035d4: 04012403 lw s0,64(sp) +800035d8: 04412983 lw s3,68(sp) +800035dc: 02412a83 lw s5,36(sp) +800035e0: 01b6e463 bltu a3,s11,800035e8 <_vfprintf_r+0x2294> +800035e4: 84cff06f j 80002630 <_vfprintf_r+0x12dc> +800035e8: 00068d93 mv s11,a3 +800035ec: 844ff06f j 80002630 <_vfprintf_r+0x12dc> +800035f0: 01c12703 lw a4,28(sp) +800035f4: ffd00793 li a5,-3 +800035f8: 00f74463 blt a4,a5,80003600 <_vfprintf_r+0x22ac> +800035fc: 00edda63 bge s11,a4,80003610 <_vfprintf_r+0x22bc> +80003600: ffe48493 addi s1,s1,-2 +80003604: fdf4f793 andi a5,s1,-33 +80003608: 04f12223 sw a5,68(sp) +8000360c: bbcfe06f j 800019c8 <_vfprintf_r+0x674> +80003610: 02012783 lw a5,32(sp) +80003614: 01c12703 lw a4,28(sp) +80003618: 2af74063 blt a4,a5,800038b8 <_vfprintf_r+0x2564> +8000361c: 02812783 lw a5,40(sp) +80003620: 00070c93 mv s9,a4 +80003624: 0017f793 andi a5,a5,1 +80003628: 00078663 beqz a5,80003634 <_vfprintf_r+0x22e0> +8000362c: 02c12783 lw a5,44(sp) +80003630: 00f70cb3 add s9,a4,a5 +80003634: 02812783 lw a5,40(sp) +80003638: 4007f793 andi a5,a5,1024 +8000363c: 00078663 beqz a5,80003648 <_vfprintf_r+0x22f4> +80003640: 01c12783 lw a5,28(sp) +80003644: 5cf04263 bgtz a5,80003c08 <_vfprintf_r+0x28b4> +80003648: fffcca93 not s5,s9 +8000364c: 41fada93 srai s5,s5,0x1f +80003650: 015cfab3 and s5,s9,s5 +80003654: 06700493 li s1,103 +80003658: 02012423 sw zero,40(sp) +8000365c: 02012223 sw zero,36(sp) +80003660: c84fe06f j 80001ae4 <_vfprintf_r+0x790> +80003664: 0c714783 lbu a5,199(sp) +80003668: 00000d93 li s11,0 +8000366c: 00078463 beqz a5,80003674 <_vfprintf_r+0x2320> +80003670: ec0fe06f j 80001d30 <_vfprintf_r+0x9dc> +80003674: f19fd06f j 8000158c <_vfprintf_r+0x238> +80003678: 00900793 li a5,9 +8000367c: d497e663 bltu a5,s1,80002bc8 <_vfprintf_r+0x1874> +80003680: d90ff06f j 80002c10 <_vfprintf_r+0x18bc> +80003684: 01012b83 lw s7,16(sp) +80003688: 000b0c13 mv s8,s6 +8000368c: cfdfe06f j 80002388 <_vfprintf_r+0x1034> +80003690: 03412423 sw s4,40(sp) +80003694: 00012823 sw zero,16(sp) +80003698: 00090a13 mv s4,s2 +8000369c: 800007b7 lui a5,0x80000 +800036a0: 0067c333 xor t1,a5,t1 +800036a4: 02d00793 li a5,45 +800036a8: 04f12c23 sw a5,88(sp) +800036ac: b99ff06f j 80003244 <_vfprintf_r+0x1ef0> +800036b0: 0e410613 addi a2,sp,228 +800036b4: 000b0593 mv a1,s6 +800036b8: 000d0513 mv a0,s10 +800036bc: 619080ef jal ra,8000c4d4 <__sprint_r> +800036c0: fc0512e3 bnez a0,80003684 <_vfprintf_r+0x2330> +800036c4: 00044683 lbu a3,0(s0) +800036c8: 0ec12783 lw a5,236(sp) +800036cc: 10c10893 addi a7,sp,268 +800036d0: 00dd8db3 add s11,s11,a3 +800036d4: 8f1ff06f j 80002fc4 <_vfprintf_r+0x1c70> +800036d8: 0b010a93 addi s5,sp,176 +800036dc: 0d010793 addi a5,sp,208 +800036e0: 0dc10813 addi a6,sp,220 +800036e4: 0cc10713 addi a4,sp,204 +800036e8: 000d8693 mv a3,s11 +800036ec: 00200613 li a2,2 +800036f0: 000a8593 mv a1,s5 +800036f4: 000d0513 mv a0,s10 +800036f8: 0bc12823 sw t3,176(sp) +800036fc: 05c12023 sw t3,64(sp) +80003700: 0bd12a23 sw t4,180(sp) +80003704: 03d12223 sw t4,36(sp) +80003708: 0be12c23 sw t5,184(sp) +8000370c: 03e12023 sw t5,32(sp) +80003710: 0a612e23 sw t1,188(sp) +80003714: 00612e23 sw t1,28(sp) +80003718: 6c9020ef jal ra,800065e0 <_ldtoa_r> +8000371c: 04700793 li a5,71 +80003720: 01c12303 lw t1,28(sp) +80003724: 02012f03 lw t5,32(sp) +80003728: 02412e83 lw t4,36(sp) +8000372c: 04012e03 lw t3,64(sp) +80003730: 05012883 lw a7,80(sp) +80003734: 00050b13 mv s6,a0 +80003738: 08fb9063 bne s7,a5,800037b8 <_vfprintf_r+0x2464> +8000373c: 02812783 lw a5,40(sp) +80003740: 0017f793 andi a5,a5,1 +80003744: 2e079663 bnez a5,80003a30 <_vfprintf_r+0x26dc> +80003748: 04700793 li a5,71 +8000374c: 0dc12703 lw a4,220(sp) +80003750: 04f12223 sw a5,68(sp) +80003754: a44fe06f j 80001998 <_vfprintf_r+0x644> +80003758: 0b010a93 addi s5,sp,176 +8000375c: 0dc10813 addi a6,sp,220 +80003760: 0d010793 addi a5,sp,208 +80003764: 0cc10713 addi a4,sp,204 +80003768: 000d8693 mv a3,s11 +8000376c: 00300613 li a2,3 +80003770: 000a8593 mv a1,s5 +80003774: 000d0513 mv a0,s10 +80003778: 05112823 sw a7,80(sp) +8000377c: 0bc12823 sw t3,176(sp) +80003780: 05c12023 sw t3,64(sp) +80003784: 0bd12a23 sw t4,180(sp) +80003788: 03d12223 sw t4,36(sp) +8000378c: 0be12c23 sw t5,184(sp) +80003790: 03e12023 sw t5,32(sp) +80003794: 0a612e23 sw t1,188(sp) +80003798: 00612e23 sw t1,28(sp) +8000379c: 645020ef jal ra,800065e0 <_ldtoa_r> +800037a0: 01c12303 lw t1,28(sp) +800037a4: 02012f03 lw t5,32(sp) +800037a8: 02412e83 lw t4,36(sp) +800037ac: 04012e03 lw t3,64(sp) +800037b0: 05012883 lw a7,80(sp) +800037b4: 00050b13 mv s6,a0 +800037b8: 04600793 li a5,70 +800037bc: 01bb0933 add s2,s6,s11 +800037c0: 26fb9e63 bne s7,a5,80003a3c <_vfprintf_r+0x26e8> +800037c4: 000b4683 lbu a3,0(s6) +800037c8: 03000793 li a5,48 +800037cc: 50f68663 beq a3,a5,80003cd8 <_vfprintf_r+0x2984> +800037d0: 0a010c93 addi s9,sp,160 +800037d4: 0cc12783 lw a5,204(sp) +800037d8: 00f90933 add s2,s2,a5 +800037dc: 960fe06f j 8000193c <_vfprintf_r+0x5e8> +800037e0: 02d00793 li a5,45 +800037e4: 0cf103a3 sb a5,199(sp) +800037e8: da0ff06f j 80002d88 <_vfprintf_r+0x1a34> +800037ec: 0e410613 addi a2,sp,228 +800037f0: 000c0593 mv a1,s8 +800037f4: 000d0513 mv a0,s10 +800037f8: 4dd080ef jal ra,8000c4d4 <__sprint_r> +800037fc: 00050463 beqz a0,80003804 <_vfprintf_r+0x24b0> +80003800: b85fe06f j 80002384 <_vfprintf_r+0x1030> +80003804: 0cc12483 lw s1,204(sp) +80003808: 0ec12783 lw a5,236(sp) +8000380c: 10c10893 addi a7,sp,268 +80003810: e69fe06f j 80002678 <_vfprintf_r+0x1324> +80003814: 0c714783 lbu a5,199(sp) +80003818: 01212a23 sw s2,20(sp) +8000381c: 02012423 sw zero,40(sp) +80003820: 02012223 sw zero,36(sp) +80003824: 00012e23 sw zero,28(sp) +80003828: 000d8a93 mv s5,s11 +8000382c: 000d8c93 mv s9,s11 +80003830: 00000d93 li s11,0 +80003834: 00078463 beqz a5,8000383c <_vfprintf_r+0x24e8> +80003838: cf8fe06f j 80001d30 <_vfprintf_r+0x9dc> +8000383c: d51fd06f j 8000158c <_vfprintf_r+0x238> +80003840: 02812783 lw a5,40(sp) +80003844: 01c12703 lw a4,28(sp) +80003848: 0017f793 andi a5,a5,1 +8000384c: 01b7e7b3 or a5,a5,s11 +80003850: 50e05663 blez a4,80003d5c <_vfprintf_r+0x2a08> +80003854: 44079063 bnez a5,80003c94 <_vfprintf_r+0x2940> +80003858: 01c12c83 lw s9,28(sp) +8000385c: 06600493 li s1,102 +80003860: 02812783 lw a5,40(sp) +80003864: 4007f793 andi a5,a5,1024 +80003868: 3a079263 bnez a5,80003c0c <_vfprintf_r+0x28b8> +8000386c: fffcca93 not s5,s9 +80003870: 41fada93 srai s5,s5,0x1f +80003874: 015cfab3 and s5,s9,s5 +80003878: de1ff06f j 80003658 <_vfprintf_r+0x2304> +8000387c: 80015737 lui a4,0x80015 +80003880: b9c70b13 addi s6,a4,-1124 # 80014b9c <__BSS_END__+0xffffdf60> +80003884: d14ff06f j 80002d98 <_vfprintf_r+0x1a44> +80003888: 0e410613 addi a2,sp,228 +8000388c: 000c0593 mv a1,s8 +80003890: 000d0513 mv a0,s10 +80003894: 441080ef jal ra,8000c4d4 <__sprint_r> +80003898: 00050463 beqz a0,800038a0 <_vfprintf_r+0x254c> +8000389c: ae9fe06f j 80002384 <_vfprintf_r+0x1030> +800038a0: 0cc12483 lw s1,204(sp) +800038a4: 02012703 lw a4,32(sp) +800038a8: 0ec12783 lw a5,236(sp) +800038ac: 10c10893 addi a7,sp,268 +800038b0: 409704b3 sub s1,a4,s1 +800038b4: e11fe06f j 800026c4 <_vfprintf_r+0x1370> +800038b8: 02012783 lw a5,32(sp) +800038bc: 02c12703 lw a4,44(sp) +800038c0: 06700493 li s1,103 +800038c4: 00e78cb3 add s9,a5,a4 +800038c8: 01c12783 lw a5,28(sp) +800038cc: f8f04ae3 bgtz a5,80003860 <_vfprintf_r+0x250c> +800038d0: 40fc8cb3 sub s9,s9,a5 +800038d4: 001c8c93 addi s9,s9,1 +800038d8: fffcca93 not s5,s9 +800038dc: 41fada93 srai s5,s5,0x1f +800038e0: 015cfab3 and s5,s9,s5 +800038e4: d75ff06f j 80003658 <_vfprintf_r+0x2304> +800038e8: 800156b7 lui a3,0x80015 +800038ec: d4468e93 addi t4,a3,-700 # 80014d44 <__BSS_END__+0xffffe108> +800038f0: b50fe06f j 80001c40 <_vfprintf_r+0x8ec> +800038f4: fff00793 li a5,-1 +800038f8: 00f12623 sw a5,12(sp) +800038fc: dcdfd06f j 800016c8 <_vfprintf_r+0x374> +80003900: ff000613 li a2,-16 +80003904: 40b004b3 neg s1,a1 +80003908: 06c5d263 bge a1,a2,8000396c <_vfprintf_r+0x2618> +8000390c: 01000913 li s2,16 +80003910: 00700c93 li s9,7 +80003914: 00c0006f j 80003920 <_vfprintf_r+0x25cc> +80003918: ff048493 addi s1,s1,-16 +8000391c: 04995863 bge s2,s1,8000396c <_vfprintf_r+0x2618> +80003920: 00812703 lw a4,8(sp) +80003924: 01078793 addi a5,a5,16 # 80000010 <__BSS_END__+0xfffe93d4> +80003928: 00168693 addi a3,a3,1 +8000392c: 00e8a023 sw a4,0(a7) +80003930: 0128a223 sw s2,4(a7) +80003934: 0ef12623 sw a5,236(sp) +80003938: 0ed12423 sw a3,232(sp) +8000393c: 00888893 addi a7,a7,8 +80003940: fcdcdce3 bge s9,a3,80003918 <_vfprintf_r+0x25c4> +80003944: 0e410613 addi a2,sp,228 +80003948: 000c0593 mv a1,s8 +8000394c: 000d0513 mv a0,s10 +80003950: 385080ef jal ra,8000c4d4 <__sprint_r> +80003954: 00050463 beqz a0,8000395c <_vfprintf_r+0x2608> +80003958: a2dfe06f j 80002384 <_vfprintf_r+0x1030> +8000395c: 0ec12783 lw a5,236(sp) +80003960: 0e812683 lw a3,232(sp) +80003964: 10c10893 addi a7,sp,268 +80003968: fb1ff06f j 80003918 <_vfprintf_r+0x25c4> +8000396c: 00812703 lw a4,8(sp) +80003970: 009787b3 add a5,a5,s1 +80003974: 00168693 addi a3,a3,1 +80003978: 00e8a023 sw a4,0(a7) +8000397c: 0098a223 sw s1,4(a7) +80003980: 0ef12623 sw a5,236(sp) +80003984: 0ed12423 sw a3,232(sp) +80003988: 00700613 li a2,7 +8000398c: b2d65a63 bge a2,a3,80002cc0 <_vfprintf_r+0x196c> +80003990: 0e410613 addi a2,sp,228 +80003994: 000c0593 mv a1,s8 +80003998: 000d0513 mv a0,s10 +8000399c: 339080ef jal ra,8000c4d4 <__sprint_r> +800039a0: 00050463 beqz a0,800039a8 <_vfprintf_r+0x2654> +800039a4: 9e1fe06f j 80002384 <_vfprintf_r+0x1030> +800039a8: 0ec12783 lw a5,236(sp) +800039ac: 0e812683 lw a3,232(sp) +800039b0: 10c10893 addi a7,sp,268 +800039b4: 9ccfe06f j 80001b80 <_vfprintf_r+0x82c> +800039b8: 000a0b93 mv s7,s4 +800039bc: e20fe06f j 80001fdc <_vfprintf_r+0xc88> +800039c0: 05412783 lw a5,84(sp) +800039c4: 000b8693 mv a3,s7 +800039c8: 0cf12e23 sw a5,220(sp) +800039cc: 02412783 lw a5,36(sp) +800039d0: fffbc603 lbu a2,-1(s7) +800039d4: 00f7c583 lbu a1,15(a5) +800039d8: 02b61063 bne a2,a1,800039f8 <_vfprintf_r+0x26a4> +800039dc: 03000513 li a0,48 +800039e0: fea68fa3 sb a0,-1(a3) +800039e4: 0dc12683 lw a3,220(sp) +800039e8: fff68793 addi a5,a3,-1 +800039ec: 0cf12e23 sw a5,220(sp) +800039f0: fff6c603 lbu a2,-1(a3) +800039f4: fec586e3 beq a1,a2,800039e0 <_vfprintf_r+0x268c> +800039f8: 00160593 addi a1,a2,1 +800039fc: 03900513 li a0,57 +80003a00: 0ff5f593 andi a1,a1,255 +80003a04: 00a60663 beq a2,a0,80003a10 <_vfprintf_r+0x26bc> +80003a08: feb68fa3 sb a1,-1(a3) +80003a0c: ba5ff06f j 800035b0 <_vfprintf_r+0x225c> +80003a10: 02412783 lw a5,36(sp) +80003a14: 00a7c583 lbu a1,10(a5) +80003a18: feb68fa3 sb a1,-1(a3) +80003a1c: b95ff06f j 800035b0 <_vfprintf_r+0x225c> +80003a20: 03000793 li a5,48 +80003a24: 0cf10423 sb a5,200(sp) +80003a28: 07800793 li a5,120 +80003a2c: fd8ff06f j 80003204 <_vfprintf_r+0x1eb0> +80003a30: 04700793 li a5,71 +80003a34: 01bb0933 add s2,s6,s11 +80003a38: 04f12223 sw a5,68(sp) +80003a3c: 0a010c93 addi s9,sp,160 +80003a40: efdfd06f j 8000193c <_vfprintf_r+0x5e8> +80003a44: 001d8593 addi a1,s11,1 +80003a48: 000d0513 mv a0,s10 +80003a4c: 01112823 sw a7,16(sp) +80003a50: 094040ef jal ra,80007ae4 <_malloc_r> +80003a54: 01012883 lw a7,16(sp) +80003a58: 00050b13 mv s6,a0 +80003a5c: 36050063 beqz a0,80003dbc <_vfprintf_r+0x2a68> +80003a60: 00a12823 sw a0,16(sp) +80003a64: fbcff06f j 80003220 <_vfprintf_r+0x1ecc> +80003a68: 000d9463 bnez s11,80003a70 <_vfprintf_r+0x271c> +80003a6c: 00100d93 li s11,1 +80003a70: 0fc12303 lw t1,252(sp) +80003a74: 0f012e03 lw t3,240(sp) +80003a78: 0f412e83 lw t4,244(sp) +80003a7c: 0f812f03 lw t5,248(sp) +80003a80: 100a6913 ori s2,s4,256 +80003a84: c00346e3 bltz t1,80003690 <_vfprintf_r+0x233c> +80003a88: 0b010a93 addi s5,sp,176 +80003a8c: 0dc10813 addi a6,sp,220 +80003a90: 0d010793 addi a5,sp,208 +80003a94: 0cc10713 addi a4,sp,204 +80003a98: 000d8693 mv a3,s11 +80003a9c: 00200613 li a2,2 +80003aa0: 000a8593 mv a1,s5 +80003aa4: 000d0513 mv a0,s10 +80003aa8: 05112223 sw a7,68(sp) +80003aac: 0bc12823 sw t3,176(sp) +80003ab0: 05c12023 sw t3,64(sp) +80003ab4: 0bd12a23 sw t4,180(sp) +80003ab8: 03d12223 sw t4,36(sp) +80003abc: 0be12c23 sw t5,184(sp) +80003ac0: 03e12023 sw t5,32(sp) +80003ac4: 0a612e23 sw t1,188(sp) +80003ac8: 00612e23 sw t1,28(sp) +80003acc: 315020ef jal ra,800065e0 <_ldtoa_r> +80003ad0: 01c12303 lw t1,28(sp) +80003ad4: 03412423 sw s4,40(sp) +80003ad8: 02012f03 lw t5,32(sp) +80003adc: 02412e83 lw t4,36(sp) +80003ae0: 04012e03 lw t3,64(sp) +80003ae4: 04412883 lw a7,68(sp) +80003ae8: 00050b13 mv s6,a0 +80003aec: 00090a13 mv s4,s2 +80003af0: 04012c23 sw zero,88(sp) +80003af4: 00012823 sw zero,16(sp) +80003af8: c45ff06f j 8000373c <_vfprintf_r+0x23e8> +80003afc: 00600d93 li s11,6 +80003b00: d8dfd06f j 8000188c <_vfprintf_r+0x538> +80003b04: 0b010a93 addi s5,sp,176 +80003b08: 000a8513 mv a0,s5 +80003b0c: 05112a23 sw a7,84(sp) +80003b10: 0bc12823 sw t3,176(sp) +80003b14: 0bd12a23 sw t4,180(sp) +80003b18: 0be12c23 sw t5,184(sp) +80003b1c: 0a612e23 sw t1,188(sp) +80003b20: 299100ef jal ra,800145b8 <__trunctfdf2> +80003b24: 0cc10613 addi a2,sp,204 +80003b28: 181050ef jal ra,800094a8 +80003b2c: 00058613 mv a2,a1 +80003b30: 00050593 mv a1,a0 +80003b34: 000a8513 mv a0,s5 +80003b38: 08d100ef jal ra,800143c4 <__extenddftf2> +80003b3c: 0b012783 lw a5,176(sp) +80003b40: 0a010c93 addi s9,sp,160 +80003b44: 09010913 addi s2,sp,144 +80003b48: 08f12823 sw a5,144(sp) +80003b4c: 0b412783 lw a5,180(sp) +80003b50: 08010613 addi a2,sp,128 +80003b54: 00090593 mv a1,s2 +80003b58: 08f12a23 sw a5,148(sp) +80003b5c: 0b812783 lw a5,184(sp) +80003b60: 000c8513 mv a0,s9 +80003b64: 04c12023 sw a2,64(sp) +80003b68: 08f12c23 sw a5,152(sp) +80003b6c: 0bc12783 lw a5,188(sp) +80003b70: 08012023 sw zero,128(sp) +80003b74: 08012223 sw zero,132(sp) +80003b78: 08f12e23 sw a5,156(sp) +80003b7c: 3ffc07b7 lui a5,0x3ffc0 +80003b80: 08f12623 sw a5,140(sp) +80003b84: 08012423 sw zero,136(sp) +80003b88: 0b40e0ef jal ra,80011c3c <__multf3> +80003b8c: 0a012803 lw a6,160(sp) +80003b90: 0a412e03 lw t3,164(sp) +80003b94: 0a812e83 lw t4,168(sp) +80003b98: 0ac12f03 lw t5,172(sp) +80003b9c: 000c8593 mv a1,s9 +80003ba0: 000a8513 mv a0,s5 +80003ba4: 0b012823 sw a6,176(sp) +80003ba8: 05012823 sw a6,80(sp) +80003bac: 0bc12a23 sw t3,180(sp) +80003bb0: 03c12223 sw t3,36(sp) +80003bb4: 0bd12c23 sw t4,184(sp) +80003bb8: 03d12023 sw t4,32(sp) +80003bbc: 0be12e23 sw t5,188(sp) +80003bc0: 01e12e23 sw t5,28(sp) +80003bc4: 0a012023 sw zero,160(sp) +80003bc8: 0a012223 sw zero,164(sp) +80003bcc: 0a012423 sw zero,168(sp) +80003bd0: 0a012623 sw zero,172(sp) +80003bd4: 5150d0ef jal ra,800118e8 <__eqtf2> +80003bd8: 01c12f03 lw t5,28(sp) +80003bdc: 02012e83 lw t4,32(sp) +80003be0: 02412e03 lw t3,36(sp) +80003be4: 05012803 lw a6,80(sp) +80003be8: 05412883 lw a7,84(sp) +80003bec: 00051663 bnez a0,80003bf8 <_vfprintf_r+0x28a4> +80003bf0: 00100793 li a5,1 +80003bf4: 0cf12623 sw a5,204(sp) +80003bf8: 800157b7 lui a5,0x80015 +80003bfc: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +80003c00: 02f12223 sw a5,36(sp) +80003c04: f54ff06f j 80003358 <_vfprintf_r+0x2004> +80003c08: 06700493 li s1,103 +80003c0c: 03c12603 lw a2,60(sp) +80003c10: 0ff00693 li a3,255 +80003c14: 00064783 lbu a5,0(a2) +80003c18: 1ad78a63 beq a5,a3,80003dcc <_vfprintf_r+0x2a78> +80003c1c: 01c12703 lw a4,28(sp) +80003c20: 00000513 li a0,0 +80003c24: 00000593 li a1,0 +80003c28: 00e7de63 bge a5,a4,80003c44 <_vfprintf_r+0x28f0> +80003c2c: 40f70733 sub a4,a4,a5 +80003c30: 00164783 lbu a5,1(a2) +80003c34: 04078463 beqz a5,80003c7c <_vfprintf_r+0x2928> +80003c38: 00158593 addi a1,a1,1 +80003c3c: 00160613 addi a2,a2,1 +80003c40: fed794e3 bne a5,a3,80003c28 <_vfprintf_r+0x28d4> +80003c44: 02c12e23 sw a2,60(sp) +80003c48: 00e12e23 sw a4,28(sp) +80003c4c: 02b12223 sw a1,36(sp) +80003c50: 02a12423 sw a0,40(sp) +80003c54: 02812703 lw a4,40(sp) +80003c58: 02412783 lw a5,36(sp) +80003c5c: 00e787b3 add a5,a5,a4 +80003c60: 04812703 lw a4,72(sp) +80003c64: 02e787b3 mul a5,a5,a4 +80003c68: 01978cb3 add s9,a5,s9 +80003c6c: fffcca93 not s5,s9 +80003c70: 41fada93 srai s5,s5,0x1f +80003c74: 015cfab3 and s5,s9,s5 +80003c78: e6dfd06f j 80001ae4 <_vfprintf_r+0x790> +80003c7c: 00064783 lbu a5,0(a2) +80003c80: 00150513 addi a0,a0,1 +80003c84: fbdff06f j 80003c40 <_vfprintf_r+0x28ec> +80003c88: 00012823 sw zero,16(sp) +80003c8c: 00078a13 mv s4,a5 +80003c90: a0dff06f j 8000369c <_vfprintf_r+0x2348> +80003c94: 02c12783 lw a5,44(sp) +80003c98: 06600493 li s1,102 +80003c9c: 00f70cb3 add s9,a4,a5 +80003ca0: 01bc8cb3 add s9,s9,s11 +80003ca4: bbdff06f j 80003860 <_vfprintf_r+0x250c> +80003ca8: 0d610693 addi a3,sp,214 +80003cac: 00061863 bnez a2,80003cbc <_vfprintf_r+0x2968> +80003cb0: 03000693 li a3,48 +80003cb4: 0cd10b23 sb a3,214(sp) +80003cb8: 0d710693 addi a3,sp,215 +80003cbc: 1b010713 addi a4,sp,432 +80003cc0: 03078793 addi a5,a5,48 +80003cc4: 40e68633 sub a2,a3,a4 +80003cc8: 00f68023 sb a5,0(a3) +80003ccc: 0dd60793 addi a5,a2,221 +80003cd0: 02f12c23 sw a5,56(sp) +80003cd4: dcdfd06f j 80001aa0 <_vfprintf_r+0x74c> +80003cd8: 0a010c93 addi s9,sp,160 +80003cdc: 000c8593 mv a1,s9 +80003ce0: 000a8513 mv a0,s5 +80003ce4: 05112823 sw a7,80(sp) +80003ce8: 0bc12823 sw t3,176(sp) +80003cec: 05c12023 sw t3,64(sp) +80003cf0: 0bd12a23 sw t4,180(sp) +80003cf4: 03d12223 sw t4,36(sp) +80003cf8: 0be12c23 sw t5,184(sp) +80003cfc: 03e12023 sw t5,32(sp) +80003d00: 0a612e23 sw t1,188(sp) +80003d04: 00612e23 sw t1,28(sp) +80003d08: 0a012023 sw zero,160(sp) +80003d0c: 0a012223 sw zero,164(sp) +80003d10: 0a012423 sw zero,168(sp) +80003d14: 0a012623 sw zero,172(sp) +80003d18: 3d10d0ef jal ra,800118e8 <__eqtf2> +80003d1c: 01c12303 lw t1,28(sp) +80003d20: 02012f03 lw t5,32(sp) +80003d24: 02412e83 lw t4,36(sp) +80003d28: 04012e03 lw t3,64(sp) +80003d2c: 05012883 lw a7,80(sp) +80003d30: aa0502e3 beqz a0,800037d4 <_vfprintf_r+0x2480> +80003d34: 00100793 li a5,1 +80003d38: 41b787b3 sub a5,a5,s11 +80003d3c: 0cf12623 sw a5,204(sp) +80003d40: 00f90933 add s2,s2,a5 +80003d44: bf9fd06f j 8000193c <_vfprintf_r+0x5e8> +80003d48: 02812783 lw a5,40(sp) +80003d4c: 0017f793 andi a5,a5,1 +80003d50: 00079463 bnez a5,80003d58 <_vfprintf_r+0x2a04> +80003d54: d6dfd06f j 80001ac0 <_vfprintf_r+0x76c> +80003d58: d61fd06f j 80001ab8 <_vfprintf_r+0x764> +80003d5c: 00079a63 bnez a5,80003d70 <_vfprintf_r+0x2a1c> +80003d60: 00100a93 li s5,1 +80003d64: 06600493 li s1,102 +80003d68: 00100c93 li s9,1 +80003d6c: 8edff06f j 80003658 <_vfprintf_r+0x2304> +80003d70: 02c12783 lw a5,44(sp) +80003d74: 06600493 li s1,102 +80003d78: 00178c93 addi s9,a5,1 +80003d7c: 01bc8cb3 add s9,s9,s11 +80003d80: fffcca93 not s5,s9 +80003d84: 41fada93 srai s5,s5,0x1f +80003d88: 015cfab3 and s5,s9,s5 +80003d8c: 8cdff06f j 80003658 <_vfprintf_r+0x2304> +80003d90: 00088713 mv a4,a7 +80003d94: bddfe06f j 80002970 <_vfprintf_r+0x161c> +80003d98: 01412783 lw a5,20(sp) +80003d9c: 0007ad83 lw s11,0(a5) +80003da0: 00478793 addi a5,a5,4 +80003da4: 000dd463 bgez s11,80003dac <_vfprintf_r+0x2a58> +80003da8: fff00d93 li s11,-1 +80003dac: 00144483 lbu s1,1(s0) +80003db0: 00f12a23 sw a5,20(sp) +80003db4: 00070413 mv s0,a4 +80003db8: f54fd06f j 8000150c <_vfprintf_r+0x1b8> +80003dbc: 00cc5783 lhu a5,12(s8) +80003dc0: 0407e793 ori a5,a5,64 +80003dc4: 00fc1623 sh a5,12(s8) +80003dc8: 8f1fd06f j 800016b8 <_vfprintf_r+0x364> +80003dcc: 02012423 sw zero,40(sp) +80003dd0: 02012223 sw zero,36(sp) +80003dd4: e81ff06f j 80003c54 <_vfprintf_r+0x2900> +80003dd8: 00200793 li a5,2 +80003ddc: 02f12c23 sw a5,56(sp) +80003de0: cc1fd06f j 80001aa0 <_vfprintf_r+0x74c> -80003ea8 : -80003ea8: 00050793 mv a5,a0 -80003eac: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -80003eb0: 00060693 mv a3,a2 -80003eb4: 00058613 mv a2,a1 -80003eb8: 00078593 mv a1,a5 -80003ebc: d5cfd06f j 80001418 <_vfprintf_r> +80003de4 : +80003de4: 00050793 mv a5,a0 +80003de8: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +80003dec: 00060693 mv a3,a2 +80003df0: 00058613 mv a2,a1 +80003df4: 00078593 mv a1,a5 +80003df8: d5cfd06f j 80001354 <_vfprintf_r> -80003ec0 <__sbprintf>: -80003ec0: 00c5d783 lhu a5,12(a1) -80003ec4: 0645ae03 lw t3,100(a1) -80003ec8: 00e5d303 lhu t1,14(a1) -80003ecc: 01c5a883 lw a7,28(a1) -80003ed0: 0245a803 lw a6,36(a1) -80003ed4: b8010113 addi sp,sp,-1152 -80003ed8: ffd7f793 andi a5,a5,-3 -80003edc: 40000713 li a4,1024 -80003ee0: 46812c23 sw s0,1144(sp) -80003ee4: 00f11a23 sh a5,20(sp) -80003ee8: 00058413 mv s0,a1 -80003eec: 07010793 addi a5,sp,112 -80003ef0: 00810593 addi a1,sp,8 -80003ef4: 46912a23 sw s1,1140(sp) -80003ef8: 47212823 sw s2,1136(sp) -80003efc: 46112e23 sw ra,1148(sp) -80003f00: 00050913 mv s2,a0 -80003f04: 07c12623 sw t3,108(sp) -80003f08: 00611b23 sh t1,22(sp) -80003f0c: 03112223 sw a7,36(sp) -80003f10: 03012623 sw a6,44(sp) -80003f14: 00f12423 sw a5,8(sp) -80003f18: 00f12c23 sw a5,24(sp) -80003f1c: 00e12823 sw a4,16(sp) -80003f20: 00e12e23 sw a4,28(sp) -80003f24: 02012023 sw zero,32(sp) -80003f28: cf0fd0ef jal ra,80001418 <_vfprintf_r> -80003f2c: 00050493 mv s1,a0 -80003f30: 02055c63 bgez a0,80003f68 <__sbprintf+0xa8> -80003f34: 01415783 lhu a5,20(sp) -80003f38: 0407f793 andi a5,a5,64 -80003f3c: 00078863 beqz a5,80003f4c <__sbprintf+0x8c> -80003f40: 00c45783 lhu a5,12(s0) -80003f44: 0407e793 ori a5,a5,64 -80003f48: 00f41623 sh a5,12(s0) -80003f4c: 47c12083 lw ra,1148(sp) -80003f50: 47812403 lw s0,1144(sp) -80003f54: 47012903 lw s2,1136(sp) -80003f58: 00048513 mv a0,s1 -80003f5c: 47412483 lw s1,1140(sp) -80003f60: 48010113 addi sp,sp,1152 -80003f64: 00008067 ret -80003f68: 00810593 addi a1,sp,8 -80003f6c: 00090513 mv a0,s2 -80003f70: 4fc000ef jal ra,8000446c <_fflush_r> -80003f74: fc0500e3 beqz a0,80003f34 <__sbprintf+0x74> -80003f78: fff00493 li s1,-1 -80003f7c: fb9ff06f j 80003f34 <__sbprintf+0x74> +80003dfc <__sbprintf>: +80003dfc: 00c5d783 lhu a5,12(a1) +80003e00: 0645ae03 lw t3,100(a1) +80003e04: 00e5d303 lhu t1,14(a1) +80003e08: 01c5a883 lw a7,28(a1) +80003e0c: 0245a803 lw a6,36(a1) +80003e10: b8010113 addi sp,sp,-1152 +80003e14: ffd7f793 andi a5,a5,-3 +80003e18: 40000713 li a4,1024 +80003e1c: 46812c23 sw s0,1144(sp) +80003e20: 00f11a23 sh a5,20(sp) +80003e24: 00058413 mv s0,a1 +80003e28: 07010793 addi a5,sp,112 +80003e2c: 00810593 addi a1,sp,8 +80003e30: 46912a23 sw s1,1140(sp) +80003e34: 47212823 sw s2,1136(sp) +80003e38: 46112e23 sw ra,1148(sp) +80003e3c: 00050913 mv s2,a0 +80003e40: 07c12623 sw t3,108(sp) +80003e44: 00611b23 sh t1,22(sp) +80003e48: 03112223 sw a7,36(sp) +80003e4c: 03012623 sw a6,44(sp) +80003e50: 00f12423 sw a5,8(sp) +80003e54: 00f12c23 sw a5,24(sp) +80003e58: 00e12823 sw a4,16(sp) +80003e5c: 00e12e23 sw a4,28(sp) +80003e60: 02012023 sw zero,32(sp) +80003e64: cf0fd0ef jal ra,80001354 <_vfprintf_r> +80003e68: 00050493 mv s1,a0 +80003e6c: 02055c63 bgez a0,80003ea4 <__sbprintf+0xa8> +80003e70: 01415783 lhu a5,20(sp) +80003e74: 0407f793 andi a5,a5,64 +80003e78: 00078863 beqz a5,80003e88 <__sbprintf+0x8c> +80003e7c: 00c45783 lhu a5,12(s0) +80003e80: 0407e793 ori a5,a5,64 +80003e84: 00f41623 sh a5,12(s0) +80003e88: 47c12083 lw ra,1148(sp) +80003e8c: 47812403 lw s0,1144(sp) +80003e90: 47012903 lw s2,1136(sp) +80003e94: 00048513 mv a0,s1 +80003e98: 47412483 lw s1,1140(sp) +80003e9c: 48010113 addi sp,sp,1152 +80003ea0: 00008067 ret +80003ea4: 00810593 addi a1,sp,8 +80003ea8: 00090513 mv a0,s2 +80003eac: 4fc000ef jal ra,800043a8 <_fflush_r> +80003eb0: fc0500e3 beqz a0,80003e70 <__sbprintf+0x74> +80003eb4: fff00493 li s1,-1 +80003eb8: fb9ff06f j 80003e70 <__sbprintf+0x74> -80003f80 <__swsetup_r>: -80003f80: 3601a783 lw a5,864(gp) # 80016b68 <_impure_ptr> -80003f84: ff010113 addi sp,sp,-16 -80003f88: 00812423 sw s0,8(sp) -80003f8c: 00912223 sw s1,4(sp) -80003f90: 00112623 sw ra,12(sp) -80003f94: 00050493 mv s1,a0 -80003f98: 00058413 mv s0,a1 -80003f9c: 00078663 beqz a5,80003fa8 <__swsetup_r+0x28> -80003fa0: 0387a703 lw a4,56(a5) -80003fa4: 0e070063 beqz a4,80004084 <__swsetup_r+0x104> -80003fa8: 00c41703 lh a4,12(s0) -80003fac: 01071793 slli a5,a4,0x10 -80003fb0: 00877693 andi a3,a4,8 -80003fb4: 0107d793 srli a5,a5,0x10 -80003fb8: 04068063 beqz a3,80003ff8 <__swsetup_r+0x78> -80003fbc: 01042683 lw a3,16(s0) -80003fc0: 06068063 beqz a3,80004020 <__swsetup_r+0xa0> -80003fc4: 0017f613 andi a2,a5,1 -80003fc8: 08060463 beqz a2,80004050 <__swsetup_r+0xd0> -80003fcc: 01442603 lw a2,20(s0) -80003fd0: 00042423 sw zero,8(s0) -80003fd4: 00000513 li a0,0 -80003fd8: 40c00633 neg a2,a2 -80003fdc: 00c42c23 sw a2,24(s0) -80003fe0: 08068663 beqz a3,8000406c <__swsetup_r+0xec> -80003fe4: 00c12083 lw ra,12(sp) -80003fe8: 00812403 lw s0,8(sp) -80003fec: 00412483 lw s1,4(sp) -80003ff0: 01010113 addi sp,sp,16 -80003ff4: 00008067 ret -80003ff8: 0107f693 andi a3,a5,16 -80003ffc: 0c068463 beqz a3,800040c4 <__swsetup_r+0x144> -80004000: 0047f793 andi a5,a5,4 -80004004: 08079663 bnez a5,80004090 <__swsetup_r+0x110> -80004008: 01042683 lw a3,16(s0) -8000400c: 00876713 ori a4,a4,8 -80004010: 01071793 slli a5,a4,0x10 -80004014: 00e41623 sh a4,12(s0) -80004018: 0107d793 srli a5,a5,0x10 -8000401c: fa0694e3 bnez a3,80003fc4 <__swsetup_r+0x44> -80004020: 2807f613 andi a2,a5,640 -80004024: 20000593 li a1,512 -80004028: f8b60ee3 beq a2,a1,80003fc4 <__swsetup_r+0x44> -8000402c: 00040593 mv a1,s0 -80004030: 00048513 mv a0,s1 -80004034: 255030ef jal ra,80007a88 <__smakebuf_r> -80004038: 00c41703 lh a4,12(s0) -8000403c: 01042683 lw a3,16(s0) -80004040: 01071793 slli a5,a4,0x10 -80004044: 0107d793 srli a5,a5,0x10 -80004048: 0017f613 andi a2,a5,1 -8000404c: f80610e3 bnez a2,80003fcc <__swsetup_r+0x4c> -80004050: 0027f613 andi a2,a5,2 -80004054: 00000593 li a1,0 -80004058: 00061463 bnez a2,80004060 <__swsetup_r+0xe0> -8000405c: 01442583 lw a1,20(s0) -80004060: 00b42423 sw a1,8(s0) -80004064: 00000513 li a0,0 -80004068: f6069ee3 bnez a3,80003fe4 <__swsetup_r+0x64> -8000406c: 0807f793 andi a5,a5,128 -80004070: f6078ae3 beqz a5,80003fe4 <__swsetup_r+0x64> -80004074: 04076713 ori a4,a4,64 -80004078: 00e41623 sh a4,12(s0) -8000407c: fff00513 li a0,-1 -80004080: f65ff06f j 80003fe4 <__swsetup_r+0x64> -80004084: 00078513 mv a0,a5 -80004088: 780000ef jal ra,80004808 <__sinit> -8000408c: f1dff06f j 80003fa8 <__swsetup_r+0x28> -80004090: 03042583 lw a1,48(s0) -80004094: 00058e63 beqz a1,800040b0 <__swsetup_r+0x130> -80004098: 04040793 addi a5,s0,64 -8000409c: 00f58863 beq a1,a5,800040ac <__swsetup_r+0x12c> -800040a0: 00048513 mv a0,s1 -800040a4: 131000ef jal ra,800049d4 <_free_r> -800040a8: 00c41703 lh a4,12(s0) -800040ac: 02042823 sw zero,48(s0) -800040b0: 01042683 lw a3,16(s0) -800040b4: fdb77713 andi a4,a4,-37 -800040b8: 00042223 sw zero,4(s0) -800040bc: 00d42023 sw a3,0(s0) -800040c0: f4dff06f j 8000400c <__swsetup_r+0x8c> -800040c4: 00900793 li a5,9 -800040c8: 00f4a023 sw a5,0(s1) -800040cc: 04076713 ori a4,a4,64 -800040d0: 00e41623 sh a4,12(s0) -800040d4: fff00513 li a0,-1 -800040d8: f0dff06f j 80003fe4 <__swsetup_r+0x64> +80003ebc <__swsetup_r>: +80003ebc: 3601a783 lw a5,864(gp) # 80016b68 <_impure_ptr> +80003ec0: ff010113 addi sp,sp,-16 +80003ec4: 00812423 sw s0,8(sp) +80003ec8: 00912223 sw s1,4(sp) +80003ecc: 00112623 sw ra,12(sp) +80003ed0: 00050493 mv s1,a0 +80003ed4: 00058413 mv s0,a1 +80003ed8: 00078663 beqz a5,80003ee4 <__swsetup_r+0x28> +80003edc: 0387a703 lw a4,56(a5) +80003ee0: 0e070063 beqz a4,80003fc0 <__swsetup_r+0x104> +80003ee4: 00c41703 lh a4,12(s0) +80003ee8: 01071793 slli a5,a4,0x10 +80003eec: 00877693 andi a3,a4,8 +80003ef0: 0107d793 srli a5,a5,0x10 +80003ef4: 04068063 beqz a3,80003f34 <__swsetup_r+0x78> +80003ef8: 01042683 lw a3,16(s0) +80003efc: 06068063 beqz a3,80003f5c <__swsetup_r+0xa0> +80003f00: 0017f613 andi a2,a5,1 +80003f04: 08060463 beqz a2,80003f8c <__swsetup_r+0xd0> +80003f08: 01442603 lw a2,20(s0) +80003f0c: 00042423 sw zero,8(s0) +80003f10: 00000513 li a0,0 +80003f14: 40c00633 neg a2,a2 +80003f18: 00c42c23 sw a2,24(s0) +80003f1c: 08068663 beqz a3,80003fa8 <__swsetup_r+0xec> +80003f20: 00c12083 lw ra,12(sp) +80003f24: 00812403 lw s0,8(sp) +80003f28: 00412483 lw s1,4(sp) +80003f2c: 01010113 addi sp,sp,16 +80003f30: 00008067 ret +80003f34: 0107f693 andi a3,a5,16 +80003f38: 0c068463 beqz a3,80004000 <__swsetup_r+0x144> +80003f3c: 0047f793 andi a5,a5,4 +80003f40: 08079663 bnez a5,80003fcc <__swsetup_r+0x110> +80003f44: 01042683 lw a3,16(s0) +80003f48: 00876713 ori a4,a4,8 +80003f4c: 01071793 slli a5,a4,0x10 +80003f50: 00e41623 sh a4,12(s0) +80003f54: 0107d793 srli a5,a5,0x10 +80003f58: fa0694e3 bnez a3,80003f00 <__swsetup_r+0x44> +80003f5c: 2807f613 andi a2,a5,640 +80003f60: 20000593 li a1,512 +80003f64: f8b60ee3 beq a2,a1,80003f00 <__swsetup_r+0x44> +80003f68: 00040593 mv a1,s0 +80003f6c: 00048513 mv a0,s1 +80003f70: 255030ef jal ra,800079c4 <__smakebuf_r> +80003f74: 00c41703 lh a4,12(s0) +80003f78: 01042683 lw a3,16(s0) +80003f7c: 01071793 slli a5,a4,0x10 +80003f80: 0107d793 srli a5,a5,0x10 +80003f84: 0017f613 andi a2,a5,1 +80003f88: f80610e3 bnez a2,80003f08 <__swsetup_r+0x4c> +80003f8c: 0027f613 andi a2,a5,2 +80003f90: 00000593 li a1,0 +80003f94: 00061463 bnez a2,80003f9c <__swsetup_r+0xe0> +80003f98: 01442583 lw a1,20(s0) +80003f9c: 00b42423 sw a1,8(s0) +80003fa0: 00000513 li a0,0 +80003fa4: f6069ee3 bnez a3,80003f20 <__swsetup_r+0x64> +80003fa8: 0807f793 andi a5,a5,128 +80003fac: f6078ae3 beqz a5,80003f20 <__swsetup_r+0x64> +80003fb0: 04076713 ori a4,a4,64 +80003fb4: 00e41623 sh a4,12(s0) +80003fb8: fff00513 li a0,-1 +80003fbc: f65ff06f j 80003f20 <__swsetup_r+0x64> +80003fc0: 00078513 mv a0,a5 +80003fc4: 780000ef jal ra,80004744 <__sinit> +80003fc8: f1dff06f j 80003ee4 <__swsetup_r+0x28> +80003fcc: 03042583 lw a1,48(s0) +80003fd0: 00058e63 beqz a1,80003fec <__swsetup_r+0x130> +80003fd4: 04040793 addi a5,s0,64 +80003fd8: 00f58863 beq a1,a5,80003fe8 <__swsetup_r+0x12c> +80003fdc: 00048513 mv a0,s1 +80003fe0: 131000ef jal ra,80004910 <_free_r> +80003fe4: 00c41703 lh a4,12(s0) +80003fe8: 02042823 sw zero,48(s0) +80003fec: 01042683 lw a3,16(s0) +80003ff0: fdb77713 andi a4,a4,-37 +80003ff4: 00042223 sw zero,4(s0) +80003ff8: 00d42023 sw a3,0(s0) +80003ffc: f4dff06f j 80003f48 <__swsetup_r+0x8c> +80004000: 00900793 li a5,9 +80004004: 00f4a023 sw a5,0(s1) +80004008: 04076713 ori a4,a4,64 +8000400c: 00e41623 sh a4,12(s0) +80004010: fff00513 li a0,-1 +80004014: f0dff06f j 80003f20 <__swsetup_r+0x64> -800040dc <__call_exitprocs>: -800040dc: fd010113 addi sp,sp,-48 -800040e0: 01412c23 sw s4,24(sp) -800040e4: 3501aa03 lw s4,848(gp) # 80016b58 <_global_impure_ptr> -800040e8: 03212023 sw s2,32(sp) -800040ec: 02112623 sw ra,44(sp) -800040f0: 148a2903 lw s2,328(s4) -800040f4: 02812423 sw s0,40(sp) -800040f8: 02912223 sw s1,36(sp) -800040fc: 01312e23 sw s3,28(sp) -80004100: 01512a23 sw s5,20(sp) -80004104: 01612823 sw s6,16(sp) -80004108: 01712623 sw s7,12(sp) -8000410c: 01812423 sw s8,8(sp) -80004110: 04090063 beqz s2,80004150 <__call_exitprocs+0x74> -80004114: 00050b13 mv s6,a0 -80004118: 00058b93 mv s7,a1 -8000411c: 00100a93 li s5,1 -80004120: fff00993 li s3,-1 -80004124: 00492483 lw s1,4(s2) # 3ffe0004 <_start-0x4001fffc> -80004128: fff48413 addi s0,s1,-1 -8000412c: 02044263 bltz s0,80004150 <__call_exitprocs+0x74> -80004130: 00249493 slli s1,s1,0x2 -80004134: 009904b3 add s1,s2,s1 -80004138: 040b8463 beqz s7,80004180 <__call_exitprocs+0xa4> -8000413c: 1044a783 lw a5,260(s1) -80004140: 05778063 beq a5,s7,80004180 <__call_exitprocs+0xa4> -80004144: fff40413 addi s0,s0,-1 -80004148: ffc48493 addi s1,s1,-4 -8000414c: ff3416e3 bne s0,s3,80004138 <__call_exitprocs+0x5c> -80004150: 02c12083 lw ra,44(sp) -80004154: 02812403 lw s0,40(sp) -80004158: 02412483 lw s1,36(sp) -8000415c: 02012903 lw s2,32(sp) -80004160: 01c12983 lw s3,28(sp) -80004164: 01812a03 lw s4,24(sp) -80004168: 01412a83 lw s5,20(sp) -8000416c: 01012b03 lw s6,16(sp) -80004170: 00c12b83 lw s7,12(sp) -80004174: 00812c03 lw s8,8(sp) -80004178: 03010113 addi sp,sp,48 -8000417c: 00008067 ret -80004180: 00492783 lw a5,4(s2) -80004184: 0044a683 lw a3,4(s1) -80004188: fff78793 addi a5,a5,-1 -8000418c: 04878e63 beq a5,s0,800041e8 <__call_exitprocs+0x10c> -80004190: 0004a223 sw zero,4(s1) -80004194: fa0688e3 beqz a3,80004144 <__call_exitprocs+0x68> -80004198: 18892783 lw a5,392(s2) -8000419c: 008a9733 sll a4,s5,s0 -800041a0: 00492c03 lw s8,4(s2) -800041a4: 00f777b3 and a5,a4,a5 -800041a8: 02079263 bnez a5,800041cc <__call_exitprocs+0xf0> -800041ac: 000680e7 jalr a3 -800041b0: 00492703 lw a4,4(s2) -800041b4: 148a2783 lw a5,328(s4) -800041b8: 01871463 bne a4,s8,800041c0 <__call_exitprocs+0xe4> -800041bc: f8f904e3 beq s2,a5,80004144 <__call_exitprocs+0x68> -800041c0: f80788e3 beqz a5,80004150 <__call_exitprocs+0x74> -800041c4: 00078913 mv s2,a5 -800041c8: f5dff06f j 80004124 <__call_exitprocs+0x48> -800041cc: 18c92783 lw a5,396(s2) -800041d0: 0844a583 lw a1,132(s1) -800041d4: 00f77733 and a4,a4,a5 -800041d8: 00071c63 bnez a4,800041f0 <__call_exitprocs+0x114> -800041dc: 000b0513 mv a0,s6 -800041e0: 000680e7 jalr a3 -800041e4: fcdff06f j 800041b0 <__call_exitprocs+0xd4> -800041e8: 00892223 sw s0,4(s2) -800041ec: fa9ff06f j 80004194 <__call_exitprocs+0xb8> -800041f0: 00058513 mv a0,a1 -800041f4: 000680e7 jalr a3 -800041f8: fb9ff06f j 800041b0 <__call_exitprocs+0xd4> +80004018 <__call_exitprocs>: +80004018: fd010113 addi sp,sp,-48 +8000401c: 01412c23 sw s4,24(sp) +80004020: 3501aa03 lw s4,848(gp) # 80016b58 <_global_impure_ptr> +80004024: 03212023 sw s2,32(sp) +80004028: 02112623 sw ra,44(sp) +8000402c: 148a2903 lw s2,328(s4) +80004030: 02812423 sw s0,40(sp) +80004034: 02912223 sw s1,36(sp) +80004038: 01312e23 sw s3,28(sp) +8000403c: 01512a23 sw s5,20(sp) +80004040: 01612823 sw s6,16(sp) +80004044: 01712623 sw s7,12(sp) +80004048: 01812423 sw s8,8(sp) +8000404c: 04090063 beqz s2,8000408c <__call_exitprocs+0x74> +80004050: 00050b13 mv s6,a0 +80004054: 00058b93 mv s7,a1 +80004058: 00100a93 li s5,1 +8000405c: fff00993 li s3,-1 +80004060: 00492483 lw s1,4(s2) # 3ffe0004 <_start-0x4001fffc> +80004064: fff48413 addi s0,s1,-1 +80004068: 02044263 bltz s0,8000408c <__call_exitprocs+0x74> +8000406c: 00249493 slli s1,s1,0x2 +80004070: 009904b3 add s1,s2,s1 +80004074: 040b8463 beqz s7,800040bc <__call_exitprocs+0xa4> +80004078: 1044a783 lw a5,260(s1) +8000407c: 05778063 beq a5,s7,800040bc <__call_exitprocs+0xa4> +80004080: fff40413 addi s0,s0,-1 +80004084: ffc48493 addi s1,s1,-4 +80004088: ff3416e3 bne s0,s3,80004074 <__call_exitprocs+0x5c> +8000408c: 02c12083 lw ra,44(sp) +80004090: 02812403 lw s0,40(sp) +80004094: 02412483 lw s1,36(sp) +80004098: 02012903 lw s2,32(sp) +8000409c: 01c12983 lw s3,28(sp) +800040a0: 01812a03 lw s4,24(sp) +800040a4: 01412a83 lw s5,20(sp) +800040a8: 01012b03 lw s6,16(sp) +800040ac: 00c12b83 lw s7,12(sp) +800040b0: 00812c03 lw s8,8(sp) +800040b4: 03010113 addi sp,sp,48 +800040b8: 00008067 ret +800040bc: 00492783 lw a5,4(s2) +800040c0: 0044a683 lw a3,4(s1) +800040c4: fff78793 addi a5,a5,-1 +800040c8: 04878e63 beq a5,s0,80004124 <__call_exitprocs+0x10c> +800040cc: 0004a223 sw zero,4(s1) +800040d0: fa0688e3 beqz a3,80004080 <__call_exitprocs+0x68> +800040d4: 18892783 lw a5,392(s2) +800040d8: 008a9733 sll a4,s5,s0 +800040dc: 00492c03 lw s8,4(s2) +800040e0: 00f777b3 and a5,a4,a5 +800040e4: 02079263 bnez a5,80004108 <__call_exitprocs+0xf0> +800040e8: 000680e7 jalr a3 +800040ec: 00492703 lw a4,4(s2) +800040f0: 148a2783 lw a5,328(s4) +800040f4: 01871463 bne a4,s8,800040fc <__call_exitprocs+0xe4> +800040f8: f8f904e3 beq s2,a5,80004080 <__call_exitprocs+0x68> +800040fc: f80788e3 beqz a5,8000408c <__call_exitprocs+0x74> +80004100: 00078913 mv s2,a5 +80004104: f5dff06f j 80004060 <__call_exitprocs+0x48> +80004108: 18c92783 lw a5,396(s2) +8000410c: 0844a583 lw a1,132(s1) +80004110: 00f77733 and a4,a4,a5 +80004114: 00071c63 bnez a4,8000412c <__call_exitprocs+0x114> +80004118: 000b0513 mv a0,s6 +8000411c: 000680e7 jalr a3 +80004120: fcdff06f j 800040ec <__call_exitprocs+0xd4> +80004124: 00892223 sw s0,4(s2) +80004128: fa9ff06f j 800040d0 <__call_exitprocs+0xb8> +8000412c: 00058513 mv a0,a1 +80004130: 000680e7 jalr a3 +80004134: fb9ff06f j 800040ec <__call_exitprocs+0xd4> -800041fc : -800041fc: 00050593 mv a1,a0 -80004200: 00000693 li a3,0 -80004204: 00000613 li a2,0 -80004208: 00000513 li a0,0 -8000420c: 7280906f j 8000d934 <__register_exitproc> +80004138 : +80004138: 00050593 mv a1,a0 +8000413c: 00000693 li a3,0 +80004140: 00000613 li a2,0 +80004144: 00000513 li a0,0 +80004148: 7280906f j 8000d870 <__register_exitproc> -80004210 <__sflush_r>: -80004210: 00c59783 lh a5,12(a1) -80004214: fe010113 addi sp,sp,-32 -80004218: 00812c23 sw s0,24(sp) -8000421c: 01312623 sw s3,12(sp) -80004220: 00112e23 sw ra,28(sp) -80004224: 00912a23 sw s1,20(sp) -80004228: 01212823 sw s2,16(sp) -8000422c: 0087f693 andi a3,a5,8 -80004230: 00058413 mv s0,a1 -80004234: 00050993 mv s3,a0 -80004238: 10069a63 bnez a3,8000434c <__sflush_r+0x13c> -8000423c: 00001737 lui a4,0x1 -80004240: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> -80004244: 0045a683 lw a3,4(a1) -80004248: 00e7e7b3 or a5,a5,a4 -8000424c: 00f59623 sh a5,12(a1) -80004250: 18d05463 blez a3,800043d8 <__sflush_r+0x1c8> -80004254: 02842703 lw a4,40(s0) -80004258: 0c070a63 beqz a4,8000432c <__sflush_r+0x11c> -8000425c: 0009a483 lw s1,0(s3) -80004260: 01079693 slli a3,a5,0x10 -80004264: 0009a023 sw zero,0(s3) -80004268: 01379613 slli a2,a5,0x13 -8000426c: 01c42583 lw a1,28(s0) -80004270: 0106d693 srli a3,a3,0x10 -80004274: 16064863 bltz a2,800043e4 <__sflush_r+0x1d4> -80004278: 00100693 li a3,1 -8000427c: 00000613 li a2,0 -80004280: 00098513 mv a0,s3 -80004284: 000700e7 jalr a4 -80004288: fff00793 li a5,-1 -8000428c: 18f50c63 beq a0,a5,80004424 <__sflush_r+0x214> -80004290: 00c45683 lhu a3,12(s0) -80004294: 02842703 lw a4,40(s0) -80004298: 01c42583 lw a1,28(s0) -8000429c: 0046f693 andi a3,a3,4 -800042a0: 00068e63 beqz a3,800042bc <__sflush_r+0xac> -800042a4: 00442683 lw a3,4(s0) -800042a8: 03042783 lw a5,48(s0) -800042ac: 40d50533 sub a0,a0,a3 -800042b0: 00078663 beqz a5,800042bc <__sflush_r+0xac> -800042b4: 03c42783 lw a5,60(s0) -800042b8: 40f50533 sub a0,a0,a5 -800042bc: 00050613 mv a2,a0 -800042c0: 00000693 li a3,0 -800042c4: 00098513 mv a0,s3 -800042c8: 000700e7 jalr a4 -800042cc: fff00793 li a5,-1 -800042d0: 10f51e63 bne a0,a5,800043ec <__sflush_r+0x1dc> -800042d4: 0009a703 lw a4,0(s3) -800042d8: 00c41783 lh a5,12(s0) -800042dc: 16070863 beqz a4,8000444c <__sflush_r+0x23c> -800042e0: 01d00693 li a3,29 -800042e4: 00d70663 beq a4,a3,800042f0 <__sflush_r+0xe0> -800042e8: 01600693 li a3,22 -800042ec: 0cd71463 bne a4,a3,800043b4 <__sflush_r+0x1a4> -800042f0: 01042683 lw a3,16(s0) -800042f4: fffff737 lui a4,0xfffff -800042f8: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> -800042fc: 00e7f7b3 and a5,a5,a4 -80004300: 00f41623 sh a5,12(s0) -80004304: 00042223 sw zero,4(s0) -80004308: 00d42023 sw a3,0(s0) -8000430c: 03042583 lw a1,48(s0) -80004310: 0099a023 sw s1,0(s3) -80004314: 00058c63 beqz a1,8000432c <__sflush_r+0x11c> -80004318: 04040793 addi a5,s0,64 -8000431c: 00f58663 beq a1,a5,80004328 <__sflush_r+0x118> -80004320: 00098513 mv a0,s3 -80004324: 6b0000ef jal ra,800049d4 <_free_r> -80004328: 02042823 sw zero,48(s0) -8000432c: 00000513 li a0,0 -80004330: 01c12083 lw ra,28(sp) -80004334: 01812403 lw s0,24(sp) -80004338: 01412483 lw s1,20(sp) -8000433c: 01012903 lw s2,16(sp) -80004340: 00c12983 lw s3,12(sp) -80004344: 02010113 addi sp,sp,32 -80004348: 00008067 ret -8000434c: 0105a903 lw s2,16(a1) -80004350: fc090ee3 beqz s2,8000432c <__sflush_r+0x11c> -80004354: 0005a483 lw s1,0(a1) -80004358: 01079713 slli a4,a5,0x10 -8000435c: 01075713 srli a4,a4,0x10 -80004360: 00377713 andi a4,a4,3 -80004364: 0125a023 sw s2,0(a1) -80004368: 412484b3 sub s1,s1,s2 -8000436c: 00000793 li a5,0 -80004370: 00071463 bnez a4,80004378 <__sflush_r+0x168> -80004374: 0145a783 lw a5,20(a1) -80004378: 00f42423 sw a5,8(s0) -8000437c: 00904863 bgtz s1,8000438c <__sflush_r+0x17c> -80004380: fadff06f j 8000432c <__sflush_r+0x11c> -80004384: 00a90933 add s2,s2,a0 -80004388: fa9052e3 blez s1,8000432c <__sflush_r+0x11c> -8000438c: 02442783 lw a5,36(s0) -80004390: 01c42583 lw a1,28(s0) -80004394: 00048693 mv a3,s1 -80004398: 00090613 mv a2,s2 -8000439c: 00098513 mv a0,s3 -800043a0: 000780e7 jalr a5 -800043a4: 40a484b3 sub s1,s1,a0 -800043a8: fca04ee3 bgtz a0,80004384 <__sflush_r+0x174> -800043ac: 00c45783 lhu a5,12(s0) -800043b0: fff00513 li a0,-1 -800043b4: 0407e793 ori a5,a5,64 -800043b8: 01c12083 lw ra,28(sp) -800043bc: 00f41623 sh a5,12(s0) -800043c0: 01812403 lw s0,24(sp) -800043c4: 01412483 lw s1,20(sp) -800043c8: 01012903 lw s2,16(sp) -800043cc: 00c12983 lw s3,12(sp) -800043d0: 02010113 addi sp,sp,32 -800043d4: 00008067 ret -800043d8: 03c5a703 lw a4,60(a1) -800043dc: e6e04ce3 bgtz a4,80004254 <__sflush_r+0x44> -800043e0: f4dff06f j 8000432c <__sflush_r+0x11c> -800043e4: 05042503 lw a0,80(s0) -800043e8: eb5ff06f j 8000429c <__sflush_r+0x8c> -800043ec: 00c45783 lhu a5,12(s0) -800043f0: fffff737 lui a4,0xfffff -800043f4: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> -800043f8: 00e7f7b3 and a5,a5,a4 -800043fc: 01042683 lw a3,16(s0) -80004400: 01079793 slli a5,a5,0x10 -80004404: 4107d793 srai a5,a5,0x10 -80004408: 00f41623 sh a5,12(s0) -8000440c: 00042223 sw zero,4(s0) -80004410: 00d42023 sw a3,0(s0) -80004414: 01379713 slli a4,a5,0x13 -80004418: ee075ae3 bgez a4,8000430c <__sflush_r+0xfc> -8000441c: 04a42823 sw a0,80(s0) -80004420: eedff06f j 8000430c <__sflush_r+0xfc> -80004424: 0009a783 lw a5,0(s3) -80004428: e60784e3 beqz a5,80004290 <__sflush_r+0x80> -8000442c: 01d00713 li a4,29 -80004430: 02e78863 beq a5,a4,80004460 <__sflush_r+0x250> -80004434: 01600713 li a4,22 -80004438: 02e78463 beq a5,a4,80004460 <__sflush_r+0x250> -8000443c: 00c45783 lhu a5,12(s0) -80004440: 0407e793 ori a5,a5,64 -80004444: 00f41623 sh a5,12(s0) -80004448: ee9ff06f j 80004330 <__sflush_r+0x120> -8000444c: fffff737 lui a4,0xfffff -80004450: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> -80004454: 01042683 lw a3,16(s0) -80004458: 00e7f7b3 and a5,a5,a4 -8000445c: fadff06f j 80004408 <__sflush_r+0x1f8> -80004460: 0099a023 sw s1,0(s3) -80004464: 00000513 li a0,0 -80004468: ec9ff06f j 80004330 <__sflush_r+0x120> +8000414c <__sflush_r>: +8000414c: 00c59783 lh a5,12(a1) +80004150: fe010113 addi sp,sp,-32 +80004154: 00812c23 sw s0,24(sp) +80004158: 01312623 sw s3,12(sp) +8000415c: 00112e23 sw ra,28(sp) +80004160: 00912a23 sw s1,20(sp) +80004164: 01212823 sw s2,16(sp) +80004168: 0087f693 andi a3,a5,8 +8000416c: 00058413 mv s0,a1 +80004170: 00050993 mv s3,a0 +80004174: 10069a63 bnez a3,80004288 <__sflush_r+0x13c> +80004178: 00001737 lui a4,0x1 +8000417c: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> +80004180: 0045a683 lw a3,4(a1) +80004184: 00e7e7b3 or a5,a5,a4 +80004188: 00f59623 sh a5,12(a1) +8000418c: 18d05463 blez a3,80004314 <__sflush_r+0x1c8> +80004190: 02842703 lw a4,40(s0) +80004194: 0c070a63 beqz a4,80004268 <__sflush_r+0x11c> +80004198: 0009a483 lw s1,0(s3) +8000419c: 01079693 slli a3,a5,0x10 +800041a0: 0009a023 sw zero,0(s3) +800041a4: 01379613 slli a2,a5,0x13 +800041a8: 01c42583 lw a1,28(s0) +800041ac: 0106d693 srli a3,a3,0x10 +800041b0: 16064863 bltz a2,80004320 <__sflush_r+0x1d4> +800041b4: 00100693 li a3,1 +800041b8: 00000613 li a2,0 +800041bc: 00098513 mv a0,s3 +800041c0: 000700e7 jalr a4 +800041c4: fff00793 li a5,-1 +800041c8: 18f50c63 beq a0,a5,80004360 <__sflush_r+0x214> +800041cc: 00c45683 lhu a3,12(s0) +800041d0: 02842703 lw a4,40(s0) +800041d4: 01c42583 lw a1,28(s0) +800041d8: 0046f693 andi a3,a3,4 +800041dc: 00068e63 beqz a3,800041f8 <__sflush_r+0xac> +800041e0: 00442683 lw a3,4(s0) +800041e4: 03042783 lw a5,48(s0) +800041e8: 40d50533 sub a0,a0,a3 +800041ec: 00078663 beqz a5,800041f8 <__sflush_r+0xac> +800041f0: 03c42783 lw a5,60(s0) +800041f4: 40f50533 sub a0,a0,a5 +800041f8: 00050613 mv a2,a0 +800041fc: 00000693 li a3,0 +80004200: 00098513 mv a0,s3 +80004204: 000700e7 jalr a4 +80004208: fff00793 li a5,-1 +8000420c: 10f51e63 bne a0,a5,80004328 <__sflush_r+0x1dc> +80004210: 0009a703 lw a4,0(s3) +80004214: 00c41783 lh a5,12(s0) +80004218: 16070863 beqz a4,80004388 <__sflush_r+0x23c> +8000421c: 01d00693 li a3,29 +80004220: 00d70663 beq a4,a3,8000422c <__sflush_r+0xe0> +80004224: 01600693 li a3,22 +80004228: 0cd71463 bne a4,a3,800042f0 <__sflush_r+0x1a4> +8000422c: 01042683 lw a3,16(s0) +80004230: fffff737 lui a4,0xfffff +80004234: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> +80004238: 00e7f7b3 and a5,a5,a4 +8000423c: 00f41623 sh a5,12(s0) +80004240: 00042223 sw zero,4(s0) +80004244: 00d42023 sw a3,0(s0) +80004248: 03042583 lw a1,48(s0) +8000424c: 0099a023 sw s1,0(s3) +80004250: 00058c63 beqz a1,80004268 <__sflush_r+0x11c> +80004254: 04040793 addi a5,s0,64 +80004258: 00f58663 beq a1,a5,80004264 <__sflush_r+0x118> +8000425c: 00098513 mv a0,s3 +80004260: 6b0000ef jal ra,80004910 <_free_r> +80004264: 02042823 sw zero,48(s0) +80004268: 00000513 li a0,0 +8000426c: 01c12083 lw ra,28(sp) +80004270: 01812403 lw s0,24(sp) +80004274: 01412483 lw s1,20(sp) +80004278: 01012903 lw s2,16(sp) +8000427c: 00c12983 lw s3,12(sp) +80004280: 02010113 addi sp,sp,32 +80004284: 00008067 ret +80004288: 0105a903 lw s2,16(a1) +8000428c: fc090ee3 beqz s2,80004268 <__sflush_r+0x11c> +80004290: 0005a483 lw s1,0(a1) +80004294: 01079713 slli a4,a5,0x10 +80004298: 01075713 srli a4,a4,0x10 +8000429c: 00377713 andi a4,a4,3 +800042a0: 0125a023 sw s2,0(a1) +800042a4: 412484b3 sub s1,s1,s2 +800042a8: 00000793 li a5,0 +800042ac: 00071463 bnez a4,800042b4 <__sflush_r+0x168> +800042b0: 0145a783 lw a5,20(a1) +800042b4: 00f42423 sw a5,8(s0) +800042b8: 00904863 bgtz s1,800042c8 <__sflush_r+0x17c> +800042bc: fadff06f j 80004268 <__sflush_r+0x11c> +800042c0: 00a90933 add s2,s2,a0 +800042c4: fa9052e3 blez s1,80004268 <__sflush_r+0x11c> +800042c8: 02442783 lw a5,36(s0) +800042cc: 01c42583 lw a1,28(s0) +800042d0: 00048693 mv a3,s1 +800042d4: 00090613 mv a2,s2 +800042d8: 00098513 mv a0,s3 +800042dc: 000780e7 jalr a5 +800042e0: 40a484b3 sub s1,s1,a0 +800042e4: fca04ee3 bgtz a0,800042c0 <__sflush_r+0x174> +800042e8: 00c45783 lhu a5,12(s0) +800042ec: fff00513 li a0,-1 +800042f0: 0407e793 ori a5,a5,64 +800042f4: 01c12083 lw ra,28(sp) +800042f8: 00f41623 sh a5,12(s0) +800042fc: 01812403 lw s0,24(sp) +80004300: 01412483 lw s1,20(sp) +80004304: 01012903 lw s2,16(sp) +80004308: 00c12983 lw s3,12(sp) +8000430c: 02010113 addi sp,sp,32 +80004310: 00008067 ret +80004314: 03c5a703 lw a4,60(a1) +80004318: e6e04ce3 bgtz a4,80004190 <__sflush_r+0x44> +8000431c: f4dff06f j 80004268 <__sflush_r+0x11c> +80004320: 05042503 lw a0,80(s0) +80004324: eb5ff06f j 800041d8 <__sflush_r+0x8c> +80004328: 00c45783 lhu a5,12(s0) +8000432c: fffff737 lui a4,0xfffff +80004330: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> +80004334: 00e7f7b3 and a5,a5,a4 +80004338: 01042683 lw a3,16(s0) +8000433c: 01079793 slli a5,a5,0x10 +80004340: 4107d793 srai a5,a5,0x10 +80004344: 00f41623 sh a5,12(s0) +80004348: 00042223 sw zero,4(s0) +8000434c: 00d42023 sw a3,0(s0) +80004350: 01379713 slli a4,a5,0x13 +80004354: ee075ae3 bgez a4,80004248 <__sflush_r+0xfc> +80004358: 04a42823 sw a0,80(s0) +8000435c: eedff06f j 80004248 <__sflush_r+0xfc> +80004360: 0009a783 lw a5,0(s3) +80004364: e60784e3 beqz a5,800041cc <__sflush_r+0x80> +80004368: 01d00713 li a4,29 +8000436c: 02e78863 beq a5,a4,8000439c <__sflush_r+0x250> +80004370: 01600713 li a4,22 +80004374: 02e78463 beq a5,a4,8000439c <__sflush_r+0x250> +80004378: 00c45783 lhu a5,12(s0) +8000437c: 0407e793 ori a5,a5,64 +80004380: 00f41623 sh a5,12(s0) +80004384: ee9ff06f j 8000426c <__sflush_r+0x120> +80004388: fffff737 lui a4,0xfffff +8000438c: 7ff70713 addi a4,a4,2047 # fffff7ff <__BSS_END__+0x7ffe8bc3> +80004390: 01042683 lw a3,16(s0) +80004394: 00e7f7b3 and a5,a5,a4 +80004398: fadff06f j 80004344 <__sflush_r+0x1f8> +8000439c: 0099a023 sw s1,0(s3) +800043a0: 00000513 li a0,0 +800043a4: ec9ff06f j 8000426c <__sflush_r+0x120> -8000446c <_fflush_r>: -8000446c: fe010113 addi sp,sp,-32 -80004470: 00812c23 sw s0,24(sp) -80004474: 00112e23 sw ra,28(sp) -80004478: 00050413 mv s0,a0 -8000447c: 00050663 beqz a0,80004488 <_fflush_r+0x1c> -80004480: 03852783 lw a5,56(a0) -80004484: 02078063 beqz a5,800044a4 <_fflush_r+0x38> -80004488: 00c59783 lh a5,12(a1) -8000448c: 02079663 bnez a5,800044b8 <_fflush_r+0x4c> -80004490: 01c12083 lw ra,28(sp) -80004494: 01812403 lw s0,24(sp) -80004498: 00000513 li a0,0 -8000449c: 02010113 addi sp,sp,32 -800044a0: 00008067 ret -800044a4: 00b12623 sw a1,12(sp) -800044a8: 360000ef jal ra,80004808 <__sinit> -800044ac: 00c12583 lw a1,12(sp) -800044b0: 00c59783 lh a5,12(a1) -800044b4: fc078ee3 beqz a5,80004490 <_fflush_r+0x24> -800044b8: 00040513 mv a0,s0 -800044bc: 01812403 lw s0,24(sp) -800044c0: 01c12083 lw ra,28(sp) -800044c4: 02010113 addi sp,sp,32 -800044c8: d49ff06f j 80004210 <__sflush_r> +800043a8 <_fflush_r>: +800043a8: fe010113 addi sp,sp,-32 +800043ac: 00812c23 sw s0,24(sp) +800043b0: 00112e23 sw ra,28(sp) +800043b4: 00050413 mv s0,a0 +800043b8: 00050663 beqz a0,800043c4 <_fflush_r+0x1c> +800043bc: 03852783 lw a5,56(a0) +800043c0: 02078063 beqz a5,800043e0 <_fflush_r+0x38> +800043c4: 00c59783 lh a5,12(a1) +800043c8: 02079663 bnez a5,800043f4 <_fflush_r+0x4c> +800043cc: 01c12083 lw ra,28(sp) +800043d0: 01812403 lw s0,24(sp) +800043d4: 00000513 li a0,0 +800043d8: 02010113 addi sp,sp,32 +800043dc: 00008067 ret +800043e0: 00b12623 sw a1,12(sp) +800043e4: 360000ef jal ra,80004744 <__sinit> +800043e8: 00c12583 lw a1,12(sp) +800043ec: 00c59783 lh a5,12(a1) +800043f0: fc078ee3 beqz a5,800043cc <_fflush_r+0x24> +800043f4: 00040513 mv a0,s0 +800043f8: 01812403 lw s0,24(sp) +800043fc: 01c12083 lw ra,28(sp) +80004400: 02010113 addi sp,sp,32 +80004404: d49ff06f j 8000414c <__sflush_r> -800044cc : -800044cc: 00050593 mv a1,a0 -800044d0: 00050663 beqz a0,800044dc -800044d4: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -800044d8: f95ff06f j 8000446c <_fflush_r> -800044dc: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> -800044e0: 800045b7 lui a1,0x80004 -800044e4: 46c58593 addi a1,a1,1132 # 8000446c <__BSS_END__+0xfffed830> -800044e8: 0910006f j 80004d78 <_fwalk_reent> +80004408 : +80004408: 00050593 mv a1,a0 +8000440c: 00050663 beqz a0,80004418 +80004410: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +80004414: f95ff06f j 800043a8 <_fflush_r> +80004418: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> +8000441c: 800045b7 lui a1,0x80004 +80004420: 3a858593 addi a1,a1,936 # 800043a8 <__BSS_END__+0xfffed76c> +80004424: 0910006f j 80004cb4 <_fwalk_reent> -800044ec <__fp_lock>: -800044ec: 00000513 li a0,0 -800044f0: 00008067 ret +80004428 <__fp_lock>: +80004428: 00000513 li a0,0 +8000442c: 00008067 ret -800044f4 <_cleanup_r>: -800044f4: 8000e5b7 lui a1,0x8000e -800044f8: ad858593 addi a1,a1,-1320 # 8000dad8 <__BSS_END__+0xffff6e9c> -800044fc: 07d0006f j 80004d78 <_fwalk_reent> +80004430 <_cleanup_r>: +80004430: 8000e5b7 lui a1,0x8000e +80004434: a1458593 addi a1,a1,-1516 # 8000da14 <__BSS_END__+0xffff6dd8> +80004438: 07d0006f j 80004cb4 <_fwalk_reent> -80004500 <__sinit.part.0>: -80004500: fe010113 addi sp,sp,-32 -80004504: 800047b7 lui a5,0x80004 -80004508: 00112e23 sw ra,28(sp) -8000450c: 00812c23 sw s0,24(sp) -80004510: 00912a23 sw s1,20(sp) -80004514: 01212823 sw s2,16(sp) -80004518: 01312623 sw s3,12(sp) -8000451c: 01412423 sw s4,8(sp) -80004520: 01512223 sw s5,4(sp) -80004524: 01612023 sw s6,0(sp) -80004528: 00452403 lw s0,4(a0) -8000452c: 4f478793 addi a5,a5,1268 # 800044f4 <__BSS_END__+0xfffed8b8> -80004530: 02f52e23 sw a5,60(a0) -80004534: 2ec50713 addi a4,a0,748 -80004538: 00300793 li a5,3 -8000453c: 2ee52423 sw a4,744(a0) -80004540: 2ef52223 sw a5,740(a0) -80004544: 2e052023 sw zero,736(a0) -80004548: 00400793 li a5,4 -8000454c: 00050913 mv s2,a0 -80004550: 00f42623 sw a5,12(s0) -80004554: 00800613 li a2,8 -80004558: 00000593 li a1,0 -8000455c: 06042223 sw zero,100(s0) -80004560: 00042023 sw zero,0(s0) -80004564: 00042223 sw zero,4(s0) -80004568: 00042423 sw zero,8(s0) -8000456c: 00042823 sw zero,16(s0) -80004570: 00042a23 sw zero,20(s0) -80004574: 00042c23 sw zero,24(s0) -80004578: 05c40513 addi a0,s0,92 -8000457c: 699030ef jal ra,80008414 -80004580: 80009b37 lui s6,0x80009 -80004584: 00892483 lw s1,8(s2) -80004588: 80009ab7 lui s5,0x80009 -8000458c: 8000aa37 lui s4,0x8000a -80004590: 8000a9b7 lui s3,0x8000a -80004594: 754b0b13 addi s6,s6,1876 # 80009754 <__BSS_END__+0xffff2b18> -80004598: 7b8a8a93 addi s5,s5,1976 # 800097b8 <__BSS_END__+0xffff2b7c> -8000459c: 840a0a13 addi s4,s4,-1984 # 80009840 <__BSS_END__+0xffff2c04> -800045a0: 8a898993 addi s3,s3,-1880 # 800098a8 <__BSS_END__+0xffff2c6c> -800045a4: 000107b7 lui a5,0x10 -800045a8: 03642023 sw s6,32(s0) -800045ac: 03542223 sw s5,36(s0) -800045b0: 03442423 sw s4,40(s0) -800045b4: 03342623 sw s3,44(s0) -800045b8: 00842e23 sw s0,28(s0) -800045bc: 00978793 addi a5,a5,9 # 10009 <_start-0x7ffefff7> -800045c0: 00f4a623 sw a5,12(s1) -800045c4: 00800613 li a2,8 -800045c8: 00000593 li a1,0 -800045cc: 0604a223 sw zero,100(s1) -800045d0: 0004a023 sw zero,0(s1) -800045d4: 0004a223 sw zero,4(s1) -800045d8: 0004a423 sw zero,8(s1) -800045dc: 0004a823 sw zero,16(s1) -800045e0: 0004aa23 sw zero,20(s1) -800045e4: 0004ac23 sw zero,24(s1) -800045e8: 05c48513 addi a0,s1,92 -800045ec: 629030ef jal ra,80008414 -800045f0: 00c92403 lw s0,12(s2) -800045f4: 000207b7 lui a5,0x20 -800045f8: 0364a023 sw s6,32(s1) -800045fc: 0354a223 sw s5,36(s1) -80004600: 0344a423 sw s4,40(s1) -80004604: 0334a623 sw s3,44(s1) -80004608: 0094ae23 sw s1,28(s1) -8000460c: 01278793 addi a5,a5,18 # 20012 <_start-0x7ffdffee> -80004610: 00f42623 sw a5,12(s0) -80004614: 06042223 sw zero,100(s0) -80004618: 00042023 sw zero,0(s0) -8000461c: 00042223 sw zero,4(s0) -80004620: 00042423 sw zero,8(s0) -80004624: 00042823 sw zero,16(s0) -80004628: 00042a23 sw zero,20(s0) -8000462c: 00042c23 sw zero,24(s0) -80004630: 05c40513 addi a0,s0,92 -80004634: 00800613 li a2,8 -80004638: 00000593 li a1,0 -8000463c: 5d9030ef jal ra,80008414 -80004640: 01c12083 lw ra,28(sp) -80004644: 03642023 sw s6,32(s0) -80004648: 03542223 sw s5,36(s0) -8000464c: 03442423 sw s4,40(s0) -80004650: 03342623 sw s3,44(s0) -80004654: 00842e23 sw s0,28(s0) -80004658: 01812403 lw s0,24(sp) -8000465c: 00100793 li a5,1 -80004660: 02f92c23 sw a5,56(s2) -80004664: 01412483 lw s1,20(sp) -80004668: 01012903 lw s2,16(sp) -8000466c: 00c12983 lw s3,12(sp) -80004670: 00812a03 lw s4,8(sp) -80004674: 00412a83 lw s5,4(sp) -80004678: 00012b03 lw s6,0(sp) -8000467c: 02010113 addi sp,sp,32 -80004680: 00008067 ret +8000443c <__sinit.part.0>: +8000443c: fe010113 addi sp,sp,-32 +80004440: 800047b7 lui a5,0x80004 +80004444: 00112e23 sw ra,28(sp) +80004448: 00812c23 sw s0,24(sp) +8000444c: 00912a23 sw s1,20(sp) +80004450: 01212823 sw s2,16(sp) +80004454: 01312623 sw s3,12(sp) +80004458: 01412423 sw s4,8(sp) +8000445c: 01512223 sw s5,4(sp) +80004460: 01612023 sw s6,0(sp) +80004464: 00452403 lw s0,4(a0) +80004468: 43078793 addi a5,a5,1072 # 80004430 <__BSS_END__+0xfffed7f4> +8000446c: 02f52e23 sw a5,60(a0) +80004470: 2ec50713 addi a4,a0,748 +80004474: 00300793 li a5,3 +80004478: 2ee52423 sw a4,744(a0) +8000447c: 2ef52223 sw a5,740(a0) +80004480: 2e052023 sw zero,736(a0) +80004484: 00400793 li a5,4 +80004488: 00050913 mv s2,a0 +8000448c: 00f42623 sw a5,12(s0) +80004490: 00800613 li a2,8 +80004494: 00000593 li a1,0 +80004498: 06042223 sw zero,100(s0) +8000449c: 00042023 sw zero,0(s0) +800044a0: 00042223 sw zero,4(s0) +800044a4: 00042423 sw zero,8(s0) +800044a8: 00042823 sw zero,16(s0) +800044ac: 00042a23 sw zero,20(s0) +800044b0: 00042c23 sw zero,24(s0) +800044b4: 05c40513 addi a0,s0,92 +800044b8: 699030ef jal ra,80008350 +800044bc: 80009b37 lui s6,0x80009 +800044c0: 00892483 lw s1,8(s2) +800044c4: 80009ab7 lui s5,0x80009 +800044c8: 80009a37 lui s4,0x80009 +800044cc: 800099b7 lui s3,0x80009 +800044d0: 690b0b13 addi s6,s6,1680 # 80009690 <__BSS_END__+0xffff2a54> +800044d4: 6f4a8a93 addi s5,s5,1780 # 800096f4 <__BSS_END__+0xffff2ab8> +800044d8: 77ca0a13 addi s4,s4,1916 # 8000977c <__BSS_END__+0xffff2b40> +800044dc: 7e498993 addi s3,s3,2020 # 800097e4 <__BSS_END__+0xffff2ba8> +800044e0: 000107b7 lui a5,0x10 +800044e4: 03642023 sw s6,32(s0) +800044e8: 03542223 sw s5,36(s0) +800044ec: 03442423 sw s4,40(s0) +800044f0: 03342623 sw s3,44(s0) +800044f4: 00842e23 sw s0,28(s0) +800044f8: 00978793 addi a5,a5,9 # 10009 <_start-0x7ffefff7> +800044fc: 00f4a623 sw a5,12(s1) +80004500: 00800613 li a2,8 +80004504: 00000593 li a1,0 +80004508: 0604a223 sw zero,100(s1) +8000450c: 0004a023 sw zero,0(s1) +80004510: 0004a223 sw zero,4(s1) +80004514: 0004a423 sw zero,8(s1) +80004518: 0004a823 sw zero,16(s1) +8000451c: 0004aa23 sw zero,20(s1) +80004520: 0004ac23 sw zero,24(s1) +80004524: 05c48513 addi a0,s1,92 +80004528: 629030ef jal ra,80008350 +8000452c: 00c92403 lw s0,12(s2) +80004530: 000207b7 lui a5,0x20 +80004534: 0364a023 sw s6,32(s1) +80004538: 0354a223 sw s5,36(s1) +8000453c: 0344a423 sw s4,40(s1) +80004540: 0334a623 sw s3,44(s1) +80004544: 0094ae23 sw s1,28(s1) +80004548: 01278793 addi a5,a5,18 # 20012 <_start-0x7ffdffee> +8000454c: 00f42623 sw a5,12(s0) +80004550: 06042223 sw zero,100(s0) +80004554: 00042023 sw zero,0(s0) +80004558: 00042223 sw zero,4(s0) +8000455c: 00042423 sw zero,8(s0) +80004560: 00042823 sw zero,16(s0) +80004564: 00042a23 sw zero,20(s0) +80004568: 00042c23 sw zero,24(s0) +8000456c: 05c40513 addi a0,s0,92 +80004570: 00800613 li a2,8 +80004574: 00000593 li a1,0 +80004578: 5d9030ef jal ra,80008350 +8000457c: 01c12083 lw ra,28(sp) +80004580: 03642023 sw s6,32(s0) +80004584: 03542223 sw s5,36(s0) +80004588: 03442423 sw s4,40(s0) +8000458c: 03342623 sw s3,44(s0) +80004590: 00842e23 sw s0,28(s0) +80004594: 01812403 lw s0,24(sp) +80004598: 00100793 li a5,1 +8000459c: 02f92c23 sw a5,56(s2) +800045a0: 01412483 lw s1,20(sp) +800045a4: 01012903 lw s2,16(sp) +800045a8: 00c12983 lw s3,12(sp) +800045ac: 00812a03 lw s4,8(sp) +800045b0: 00412a83 lw s5,4(sp) +800045b4: 00012b03 lw s6,0(sp) +800045b8: 02010113 addi sp,sp,32 +800045bc: 00008067 ret -80004684 <__fp_unlock>: -80004684: 00000513 li a0,0 -80004688: 00008067 ret +800045c0 <__fp_unlock>: +800045c0: 00000513 li a0,0 +800045c4: 00008067 ret -8000468c <__sfmoreglue>: -8000468c: ff010113 addi sp,sp,-16 -80004690: 00912223 sw s1,4(sp) -80004694: 06800613 li a2,104 -80004698: fff58493 addi s1,a1,-1 -8000469c: 02c484b3 mul s1,s1,a2 -800046a0: 01212023 sw s2,0(sp) -800046a4: 00058913 mv s2,a1 -800046a8: 00812423 sw s0,8(sp) -800046ac: 00112623 sw ra,12(sp) -800046b0: 07448593 addi a1,s1,116 -800046b4: 4f4030ef jal ra,80007ba8 <_malloc_r> -800046b8: 00050413 mv s0,a0 -800046bc: 02050063 beqz a0,800046dc <__sfmoreglue+0x50> -800046c0: 00c50513 addi a0,a0,12 -800046c4: 00042023 sw zero,0(s0) -800046c8: 01242223 sw s2,4(s0) -800046cc: 00a42423 sw a0,8(s0) -800046d0: 06848613 addi a2,s1,104 -800046d4: 00000593 li a1,0 -800046d8: 53d030ef jal ra,80008414 -800046dc: 00c12083 lw ra,12(sp) -800046e0: 00040513 mv a0,s0 -800046e4: 00812403 lw s0,8(sp) -800046e8: 00412483 lw s1,4(sp) -800046ec: 00012903 lw s2,0(sp) -800046f0: 01010113 addi sp,sp,16 -800046f4: 00008067 ret +800045c8 <__sfmoreglue>: +800045c8: ff010113 addi sp,sp,-16 +800045cc: 00912223 sw s1,4(sp) +800045d0: 06800613 li a2,104 +800045d4: fff58493 addi s1,a1,-1 +800045d8: 02c484b3 mul s1,s1,a2 +800045dc: 01212023 sw s2,0(sp) +800045e0: 00058913 mv s2,a1 +800045e4: 00812423 sw s0,8(sp) +800045e8: 00112623 sw ra,12(sp) +800045ec: 07448593 addi a1,s1,116 +800045f0: 4f4030ef jal ra,80007ae4 <_malloc_r> +800045f4: 00050413 mv s0,a0 +800045f8: 02050063 beqz a0,80004618 <__sfmoreglue+0x50> +800045fc: 00c50513 addi a0,a0,12 +80004600: 00042023 sw zero,0(s0) +80004604: 01242223 sw s2,4(s0) +80004608: 00a42423 sw a0,8(s0) +8000460c: 06848613 addi a2,s1,104 +80004610: 00000593 li a1,0 +80004614: 53d030ef jal ra,80008350 +80004618: 00c12083 lw ra,12(sp) +8000461c: 00040513 mv a0,s0 +80004620: 00812403 lw s0,8(sp) +80004624: 00412483 lw s1,4(sp) +80004628: 00012903 lw s2,0(sp) +8000462c: 01010113 addi sp,sp,16 +80004630: 00008067 ret -800046f8 <__sfp>: -800046f8: fe010113 addi sp,sp,-32 -800046fc: 01212823 sw s2,16(sp) -80004700: 3501a903 lw s2,848(gp) # 80016b58 <_global_impure_ptr> -80004704: 01312623 sw s3,12(sp) -80004708: 00112e23 sw ra,28(sp) -8000470c: 03892783 lw a5,56(s2) -80004710: 00812c23 sw s0,24(sp) -80004714: 00912a23 sw s1,20(sp) -80004718: 00050993 mv s3,a0 -8000471c: 0a078663 beqz a5,800047c8 <__sfp+0xd0> -80004720: 2e090913 addi s2,s2,736 -80004724: fff00493 li s1,-1 -80004728: 00492783 lw a5,4(s2) -8000472c: 00892403 lw s0,8(s2) -80004730: fff78793 addi a5,a5,-1 -80004734: 0007d863 bgez a5,80004744 <__sfp+0x4c> -80004738: 0800006f j 800047b8 <__sfp+0xc0> -8000473c: 06840413 addi s0,s0,104 -80004740: 06978c63 beq a5,s1,800047b8 <__sfp+0xc0> -80004744: 00c41703 lh a4,12(s0) -80004748: fff78793 addi a5,a5,-1 -8000474c: fe0718e3 bnez a4,8000473c <__sfp+0x44> -80004750: ffff07b7 lui a5,0xffff0 -80004754: 00178793 addi a5,a5,1 # ffff0001 <__BSS_END__+0x7ffd93c5> -80004758: 06042223 sw zero,100(s0) -8000475c: 00042023 sw zero,0(s0) -80004760: 00042223 sw zero,4(s0) -80004764: 00042423 sw zero,8(s0) -80004768: 00f42623 sw a5,12(s0) -8000476c: 00042823 sw zero,16(s0) -80004770: 00042a23 sw zero,20(s0) -80004774: 00042c23 sw zero,24(s0) -80004778: 00800613 li a2,8 -8000477c: 00000593 li a1,0 -80004780: 05c40513 addi a0,s0,92 -80004784: 491030ef jal ra,80008414 -80004788: 02042823 sw zero,48(s0) -8000478c: 02042a23 sw zero,52(s0) -80004790: 04042223 sw zero,68(s0) -80004794: 04042423 sw zero,72(s0) -80004798: 01c12083 lw ra,28(sp) -8000479c: 00040513 mv a0,s0 -800047a0: 01812403 lw s0,24(sp) -800047a4: 01412483 lw s1,20(sp) -800047a8: 01012903 lw s2,16(sp) -800047ac: 00c12983 lw s3,12(sp) -800047b0: 02010113 addi sp,sp,32 -800047b4: 00008067 ret -800047b8: 00092403 lw s0,0(s2) -800047bc: 00040c63 beqz s0,800047d4 <__sfp+0xdc> -800047c0: 00040913 mv s2,s0 -800047c4: f65ff06f j 80004728 <__sfp+0x30> -800047c8: 00090513 mv a0,s2 -800047cc: d35ff0ef jal ra,80004500 <__sinit.part.0> -800047d0: f51ff06f j 80004720 <__sfp+0x28> -800047d4: 00400593 li a1,4 -800047d8: 00098513 mv a0,s3 -800047dc: eb1ff0ef jal ra,8000468c <__sfmoreglue> -800047e0: 00a92023 sw a0,0(s2) -800047e4: 00050413 mv s0,a0 -800047e8: fc051ce3 bnez a0,800047c0 <__sfp+0xc8> -800047ec: 00c00793 li a5,12 -800047f0: 00f9a023 sw a5,0(s3) -800047f4: fa5ff06f j 80004798 <__sfp+0xa0> +80004634 <__sfp>: +80004634: fe010113 addi sp,sp,-32 +80004638: 01212823 sw s2,16(sp) +8000463c: 3501a903 lw s2,848(gp) # 80016b58 <_global_impure_ptr> +80004640: 01312623 sw s3,12(sp) +80004644: 00112e23 sw ra,28(sp) +80004648: 03892783 lw a5,56(s2) +8000464c: 00812c23 sw s0,24(sp) +80004650: 00912a23 sw s1,20(sp) +80004654: 00050993 mv s3,a0 +80004658: 0a078663 beqz a5,80004704 <__sfp+0xd0> +8000465c: 2e090913 addi s2,s2,736 +80004660: fff00493 li s1,-1 +80004664: 00492783 lw a5,4(s2) +80004668: 00892403 lw s0,8(s2) +8000466c: fff78793 addi a5,a5,-1 +80004670: 0007d863 bgez a5,80004680 <__sfp+0x4c> +80004674: 0800006f j 800046f4 <__sfp+0xc0> +80004678: 06840413 addi s0,s0,104 +8000467c: 06978c63 beq a5,s1,800046f4 <__sfp+0xc0> +80004680: 00c41703 lh a4,12(s0) +80004684: fff78793 addi a5,a5,-1 +80004688: fe0718e3 bnez a4,80004678 <__sfp+0x44> +8000468c: ffff07b7 lui a5,0xffff0 +80004690: 00178793 addi a5,a5,1 # ffff0001 <__BSS_END__+0x7ffd93c5> +80004694: 06042223 sw zero,100(s0) +80004698: 00042023 sw zero,0(s0) +8000469c: 00042223 sw zero,4(s0) +800046a0: 00042423 sw zero,8(s0) +800046a4: 00f42623 sw a5,12(s0) +800046a8: 00042823 sw zero,16(s0) +800046ac: 00042a23 sw zero,20(s0) +800046b0: 00042c23 sw zero,24(s0) +800046b4: 00800613 li a2,8 +800046b8: 00000593 li a1,0 +800046bc: 05c40513 addi a0,s0,92 +800046c0: 491030ef jal ra,80008350 +800046c4: 02042823 sw zero,48(s0) +800046c8: 02042a23 sw zero,52(s0) +800046cc: 04042223 sw zero,68(s0) +800046d0: 04042423 sw zero,72(s0) +800046d4: 01c12083 lw ra,28(sp) +800046d8: 00040513 mv a0,s0 +800046dc: 01812403 lw s0,24(sp) +800046e0: 01412483 lw s1,20(sp) +800046e4: 01012903 lw s2,16(sp) +800046e8: 00c12983 lw s3,12(sp) +800046ec: 02010113 addi sp,sp,32 +800046f0: 00008067 ret +800046f4: 00092403 lw s0,0(s2) +800046f8: 00040c63 beqz s0,80004710 <__sfp+0xdc> +800046fc: 00040913 mv s2,s0 +80004700: f65ff06f j 80004664 <__sfp+0x30> +80004704: 00090513 mv a0,s2 +80004708: d35ff0ef jal ra,8000443c <__sinit.part.0> +8000470c: f51ff06f j 8000465c <__sfp+0x28> +80004710: 00400593 li a1,4 +80004714: 00098513 mv a0,s3 +80004718: eb1ff0ef jal ra,800045c8 <__sfmoreglue> +8000471c: 00a92023 sw a0,0(s2) +80004720: 00050413 mv s0,a0 +80004724: fc051ce3 bnez a0,800046fc <__sfp+0xc8> +80004728: 00c00793 li a5,12 +8000472c: 00f9a023 sw a5,0(s3) +80004730: fa5ff06f j 800046d4 <__sfp+0xa0> -800047f8 <_cleanup>: -800047f8: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> -800047fc: 8000e5b7 lui a1,0x8000e -80004800: ad858593 addi a1,a1,-1320 # 8000dad8 <__BSS_END__+0xffff6e9c> -80004804: 5740006f j 80004d78 <_fwalk_reent> +80004734 <_cleanup>: +80004734: 3501a503 lw a0,848(gp) # 80016b58 <_global_impure_ptr> +80004738: 8000e5b7 lui a1,0x8000e +8000473c: a1458593 addi a1,a1,-1516 # 8000da14 <__BSS_END__+0xffff6dd8> +80004740: 5740006f j 80004cb4 <_fwalk_reent> -80004808 <__sinit>: -80004808: 03852783 lw a5,56(a0) -8000480c: 00078463 beqz a5,80004814 <__sinit+0xc> -80004810: 00008067 ret -80004814: cedff06f j 80004500 <__sinit.part.0> +80004744 <__sinit>: +80004744: 03852783 lw a5,56(a0) +80004748: 00078463 beqz a5,80004750 <__sinit+0xc> +8000474c: 00008067 ret +80004750: cedff06f j 8000443c <__sinit.part.0> -80004818 <__sfp_lock_acquire>: -80004818: 00008067 ret +80004754 <__sfp_lock_acquire>: +80004754: 00008067 ret -8000481c <__sfp_lock_release>: -8000481c: 00008067 ret +80004758 <__sfp_lock_release>: +80004758: 00008067 ret -80004820 <__sinit_lock_acquire>: -80004820: 00008067 ret +8000475c <__sinit_lock_acquire>: +8000475c: 00008067 ret -80004824 <__sinit_lock_release>: -80004824: 00008067 ret +80004760 <__sinit_lock_release>: +80004760: 00008067 ret -80004828 <__fp_lock_all>: -80004828: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -8000482c: 800045b7 lui a1,0x80004 -80004830: 4ec58593 addi a1,a1,1260 # 800044ec <__BSS_END__+0xfffed8b0> -80004834: 4a00006f j 80004cd4 <_fwalk> +80004764 <__fp_lock_all>: +80004764: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +80004768: 800045b7 lui a1,0x80004 +8000476c: 42858593 addi a1,a1,1064 # 80004428 <__BSS_END__+0xfffed7ec> +80004770: 4a00006f j 80004c10 <_fwalk> -80004838 <__fp_unlock_all>: -80004838: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -8000483c: 800045b7 lui a1,0x80004 -80004840: 68458593 addi a1,a1,1668 # 80004684 <__BSS_END__+0xfffeda48> -80004844: 4900006f j 80004cd4 <_fwalk> +80004774 <__fp_unlock_all>: +80004774: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +80004778: 800045b7 lui a1,0x80004 +8000477c: 5c058593 addi a1,a1,1472 # 800045c0 <__BSS_END__+0xfffed984> +80004780: 4900006f j 80004c10 <_fwalk> -80004848 <__libc_fini_array>: -80004848: ff010113 addi sp,sp,-16 -8000484c: 00812423 sw s0,8(sp) -80004850: 800167b7 lui a5,0x80016 -80004854: 80016437 lui s0,0x80016 -80004858: 00440413 addi s0,s0,4 # 80016004 <__BSS_END__+0xfffff3c8> -8000485c: 00478793 addi a5,a5,4 # 80016004 <__BSS_END__+0xfffff3c8> -80004860: 408787b3 sub a5,a5,s0 -80004864: 00912223 sw s1,4(sp) -80004868: 00112623 sw ra,12(sp) -8000486c: 4027d493 srai s1,a5,0x2 -80004870: 02048063 beqz s1,80004890 <__libc_fini_array+0x48> -80004874: ffc78793 addi a5,a5,-4 -80004878: 00878433 add s0,a5,s0 -8000487c: 00042783 lw a5,0(s0) -80004880: fff48493 addi s1,s1,-1 -80004884: ffc40413 addi s0,s0,-4 -80004888: 000780e7 jalr a5 -8000488c: fe0498e3 bnez s1,8000487c <__libc_fini_array+0x34> -80004890: 00c12083 lw ra,12(sp) -80004894: 00812403 lw s0,8(sp) -80004898: 00412483 lw s1,4(sp) -8000489c: 01010113 addi sp,sp,16 -800048a0: 00008067 ret +80004784 <__libc_fini_array>: +80004784: ff010113 addi sp,sp,-16 +80004788: 00812423 sw s0,8(sp) +8000478c: 800167b7 lui a5,0x80016 +80004790: 80016437 lui s0,0x80016 +80004794: 00440413 addi s0,s0,4 # 80016004 <__BSS_END__+0xfffff3c8> +80004798: 00478793 addi a5,a5,4 # 80016004 <__BSS_END__+0xfffff3c8> +8000479c: 408787b3 sub a5,a5,s0 +800047a0: 00912223 sw s1,4(sp) +800047a4: 00112623 sw ra,12(sp) +800047a8: 4027d493 srai s1,a5,0x2 +800047ac: 02048063 beqz s1,800047cc <__libc_fini_array+0x48> +800047b0: ffc78793 addi a5,a5,-4 +800047b4: 00878433 add s0,a5,s0 +800047b8: 00042783 lw a5,0(s0) +800047bc: fff48493 addi s1,s1,-1 +800047c0: ffc40413 addi s0,s0,-4 +800047c4: 000780e7 jalr a5 +800047c8: fe0498e3 bnez s1,800047b8 <__libc_fini_array+0x34> +800047cc: 00c12083 lw ra,12(sp) +800047d0: 00812403 lw s0,8(sp) +800047d4: 00412483 lw s1,4(sp) +800047d8: 01010113 addi sp,sp,16 +800047dc: 00008067 ret -800048a4 <_malloc_trim_r>: -800048a4: fe010113 addi sp,sp,-32 -800048a8: 01312623 sw s3,12(sp) -800048ac: 00812c23 sw s0,24(sp) -800048b0: 00912a23 sw s1,20(sp) -800048b4: 01212823 sw s2,16(sp) -800048b8: 01412423 sw s4,8(sp) -800048bc: 00112e23 sw ra,28(sp) -800048c0: 00058a13 mv s4,a1 -800048c4: 00050913 mv s2,a0 -800048c8: dc018993 addi s3,gp,-576 # 800165c8 <__malloc_av_> -800048cc: 425030ef jal ra,800084f0 <__malloc_lock> -800048d0: 0089a703 lw a4,8(s3) -800048d4: 000017b7 lui a5,0x1 -800048d8: fef78413 addi s0,a5,-17 # fef <_start-0x7ffff011> -800048dc: 00472483 lw s1,4(a4) -800048e0: 41440433 sub s0,s0,s4 -800048e4: ffc4f493 andi s1,s1,-4 -800048e8: 00940433 add s0,s0,s1 -800048ec: 00c45413 srli s0,s0,0xc -800048f0: fff40413 addi s0,s0,-1 -800048f4: 00c41413 slli s0,s0,0xc -800048f8: 00f44e63 blt s0,a5,80004914 <_malloc_trim_r+0x70> -800048fc: 00000593 li a1,0 -80004900: 00090513 mv a0,s2 -80004904: 511040ef jal ra,80009614 <_sbrk_r> -80004908: 0089a783 lw a5,8(s3) -8000490c: 009787b3 add a5,a5,s1 -80004910: 02f50863 beq a0,a5,80004940 <_malloc_trim_r+0x9c> -80004914: 00090513 mv a0,s2 -80004918: 3dd030ef jal ra,800084f4 <__malloc_unlock> -8000491c: 01c12083 lw ra,28(sp) -80004920: 01812403 lw s0,24(sp) -80004924: 01412483 lw s1,20(sp) -80004928: 01012903 lw s2,16(sp) -8000492c: 00c12983 lw s3,12(sp) -80004930: 00812a03 lw s4,8(sp) -80004934: 00000513 li a0,0 -80004938: 02010113 addi sp,sp,32 -8000493c: 00008067 ret -80004940: 408005b3 neg a1,s0 -80004944: 00090513 mv a0,s2 -80004948: 4cd040ef jal ra,80009614 <_sbrk_r> -8000494c: fff00793 li a5,-1 -80004950: 04f50863 beq a0,a5,800049a0 <_malloc_trim_r+0xfc> -80004954: 3c018793 addi a5,gp,960 # 80016bc8 <__malloc_current_mallinfo> -80004958: 0007a703 lw a4,0(a5) -8000495c: 0089a683 lw a3,8(s3) -80004960: 408484b3 sub s1,s1,s0 -80004964: 0014e493 ori s1,s1,1 -80004968: 40870433 sub s0,a4,s0 -8000496c: 00090513 mv a0,s2 -80004970: 0096a223 sw s1,4(a3) -80004974: 0087a023 sw s0,0(a5) -80004978: 37d030ef jal ra,800084f4 <__malloc_unlock> -8000497c: 01c12083 lw ra,28(sp) -80004980: 01812403 lw s0,24(sp) -80004984: 01412483 lw s1,20(sp) -80004988: 01012903 lw s2,16(sp) -8000498c: 00c12983 lw s3,12(sp) -80004990: 00812a03 lw s4,8(sp) -80004994: 00100513 li a0,1 -80004998: 02010113 addi sp,sp,32 -8000499c: 00008067 ret -800049a0: 00000593 li a1,0 -800049a4: 00090513 mv a0,s2 -800049a8: 46d040ef jal ra,80009614 <_sbrk_r> -800049ac: 0089a703 lw a4,8(s3) -800049b0: 00f00693 li a3,15 -800049b4: 40e507b3 sub a5,a0,a4 -800049b8: f4f6dee3 bge a3,a5,80004914 <_malloc_trim_r+0x70> -800049bc: 3641a683 lw a3,868(gp) # 80016b6c <__malloc_sbrk_base> -800049c0: 0017e793 ori a5,a5,1 -800049c4: 00f72223 sw a5,4(a4) -800049c8: 40d50533 sub a0,a0,a3 -800049cc: 3ca1a023 sw a0,960(gp) # 80016bc8 <__malloc_current_mallinfo> -800049d0: f45ff06f j 80004914 <_malloc_trim_r+0x70> +800047e0 <_malloc_trim_r>: +800047e0: fe010113 addi sp,sp,-32 +800047e4: 01312623 sw s3,12(sp) +800047e8: 00812c23 sw s0,24(sp) +800047ec: 00912a23 sw s1,20(sp) +800047f0: 01212823 sw s2,16(sp) +800047f4: 01412423 sw s4,8(sp) +800047f8: 00112e23 sw ra,28(sp) +800047fc: 00058a13 mv s4,a1 +80004800: 00050913 mv s2,a0 +80004804: dc018993 addi s3,gp,-576 # 800165c8 <__malloc_av_> +80004808: 425030ef jal ra,8000842c <__malloc_lock> +8000480c: 0089a703 lw a4,8(s3) +80004810: 000017b7 lui a5,0x1 +80004814: fef78413 addi s0,a5,-17 # fef <_start-0x7ffff011> +80004818: 00472483 lw s1,4(a4) +8000481c: 41440433 sub s0,s0,s4 +80004820: ffc4f493 andi s1,s1,-4 +80004824: 00940433 add s0,s0,s1 +80004828: 00c45413 srli s0,s0,0xc +8000482c: fff40413 addi s0,s0,-1 +80004830: 00c41413 slli s0,s0,0xc +80004834: 00f44e63 blt s0,a5,80004850 <_malloc_trim_r+0x70> +80004838: 00000593 li a1,0 +8000483c: 00090513 mv a0,s2 +80004840: 511040ef jal ra,80009550 <_sbrk_r> +80004844: 0089a783 lw a5,8(s3) +80004848: 009787b3 add a5,a5,s1 +8000484c: 02f50863 beq a0,a5,8000487c <_malloc_trim_r+0x9c> +80004850: 00090513 mv a0,s2 +80004854: 3dd030ef jal ra,80008430 <__malloc_unlock> +80004858: 01c12083 lw ra,28(sp) +8000485c: 01812403 lw s0,24(sp) +80004860: 01412483 lw s1,20(sp) +80004864: 01012903 lw s2,16(sp) +80004868: 00c12983 lw s3,12(sp) +8000486c: 00812a03 lw s4,8(sp) +80004870: 00000513 li a0,0 +80004874: 02010113 addi sp,sp,32 +80004878: 00008067 ret +8000487c: 408005b3 neg a1,s0 +80004880: 00090513 mv a0,s2 +80004884: 4cd040ef jal ra,80009550 <_sbrk_r> +80004888: fff00793 li a5,-1 +8000488c: 04f50863 beq a0,a5,800048dc <_malloc_trim_r+0xfc> +80004890: 40818793 addi a5,gp,1032 # 80016c10 <__malloc_current_mallinfo> +80004894: 0007a703 lw a4,0(a5) +80004898: 0089a683 lw a3,8(s3) +8000489c: 408484b3 sub s1,s1,s0 +800048a0: 0014e493 ori s1,s1,1 +800048a4: 40870433 sub s0,a4,s0 +800048a8: 00090513 mv a0,s2 +800048ac: 0096a223 sw s1,4(a3) +800048b0: 0087a023 sw s0,0(a5) +800048b4: 37d030ef jal ra,80008430 <__malloc_unlock> +800048b8: 01c12083 lw ra,28(sp) +800048bc: 01812403 lw s0,24(sp) +800048c0: 01412483 lw s1,20(sp) +800048c4: 01012903 lw s2,16(sp) +800048c8: 00c12983 lw s3,12(sp) +800048cc: 00812a03 lw s4,8(sp) +800048d0: 00100513 li a0,1 +800048d4: 02010113 addi sp,sp,32 +800048d8: 00008067 ret +800048dc: 00000593 li a1,0 +800048e0: 00090513 mv a0,s2 +800048e4: 46d040ef jal ra,80009550 <_sbrk_r> +800048e8: 0089a703 lw a4,8(s3) +800048ec: 00f00693 li a3,15 +800048f0: 40e507b3 sub a5,a0,a4 +800048f4: f4f6dee3 bge a3,a5,80004850 <_malloc_trim_r+0x70> +800048f8: 3641a683 lw a3,868(gp) # 80016b6c <__malloc_sbrk_base> +800048fc: 0017e793 ori a5,a5,1 +80004900: 00f72223 sw a5,4(a4) +80004904: 40d50533 sub a0,a0,a3 +80004908: 40a1a423 sw a0,1032(gp) # 80016c10 <__malloc_current_mallinfo> +8000490c: f45ff06f j 80004850 <_malloc_trim_r+0x70> -800049d4 <_free_r>: -800049d4: 12058463 beqz a1,80004afc <_free_r+0x128> -800049d8: ff010113 addi sp,sp,-16 -800049dc: 00812423 sw s0,8(sp) -800049e0: 00912223 sw s1,4(sp) -800049e4: 00058413 mv s0,a1 -800049e8: 00050493 mv s1,a0 -800049ec: 00112623 sw ra,12(sp) -800049f0: 301030ef jal ra,800084f0 <__malloc_lock> -800049f4: ffc42803 lw a6,-4(s0) -800049f8: ff840713 addi a4,s0,-8 -800049fc: ffe87793 andi a5,a6,-2 -80004a00: 00f70633 add a2,a4,a5 -80004a04: dc018593 addi a1,gp,-576 # 800165c8 <__malloc_av_> -80004a08: 00462683 lw a3,4(a2) -80004a0c: 0085a503 lw a0,8(a1) -80004a10: ffc6f693 andi a3,a3,-4 -80004a14: 1ac50663 beq a0,a2,80004bc0 <_free_r+0x1ec> -80004a18: 00d62223 sw a3,4(a2) -80004a1c: 00187813 andi a6,a6,1 -80004a20: 00d60533 add a0,a2,a3 -80004a24: 08081e63 bnez a6,80004ac0 <_free_r+0xec> -80004a28: ff842303 lw t1,-8(s0) -80004a2c: 00452803 lw a6,4(a0) -80004a30: 40670733 sub a4,a4,t1 -80004a34: 00872883 lw a7,8(a4) -80004a38: dc818513 addi a0,gp,-568 # 800165d0 <__malloc_av_+0x8> -80004a3c: 006787b3 add a5,a5,t1 -80004a40: 00187813 andi a6,a6,1 -80004a44: 12a88e63 beq a7,a0,80004b80 <_free_r+0x1ac> -80004a48: 00c72303 lw t1,12(a4) -80004a4c: 0068a623 sw t1,12(a7) -80004a50: 01132423 sw a7,8(t1) -80004a54: 1c080e63 beqz a6,80004c30 <_free_r+0x25c> -80004a58: 0017e693 ori a3,a5,1 -80004a5c: 00d72223 sw a3,4(a4) -80004a60: 00f62023 sw a5,0(a2) -80004a64: 1ff00693 li a3,511 -80004a68: 0af6e663 bltu a3,a5,80004b14 <_free_r+0x140> -80004a6c: ff87f693 andi a3,a5,-8 -80004a70: 00868693 addi a3,a3,8 -80004a74: 0045a503 lw a0,4(a1) -80004a78: 00d586b3 add a3,a1,a3 -80004a7c: 0006a603 lw a2,0(a3) -80004a80: 0057d813 srli a6,a5,0x5 -80004a84: 00100793 li a5,1 -80004a88: 010797b3 sll a5,a5,a6 -80004a8c: 00a7e7b3 or a5,a5,a0 -80004a90: ff868513 addi a0,a3,-8 -80004a94: 00a72623 sw a0,12(a4) -80004a98: 00c72423 sw a2,8(a4) -80004a9c: 00f5a223 sw a5,4(a1) -80004aa0: 00e6a023 sw a4,0(a3) -80004aa4: 00e62623 sw a4,12(a2) -80004aa8: 00812403 lw s0,8(sp) -80004aac: 00c12083 lw ra,12(sp) -80004ab0: 00048513 mv a0,s1 -80004ab4: 00412483 lw s1,4(sp) -80004ab8: 01010113 addi sp,sp,16 -80004abc: 2390306f j 800084f4 <__malloc_unlock> -80004ac0: 00452503 lw a0,4(a0) -80004ac4: 00157513 andi a0,a0,1 -80004ac8: 02051c63 bnez a0,80004b00 <_free_r+0x12c> -80004acc: 00d787b3 add a5,a5,a3 -80004ad0: dc818513 addi a0,gp,-568 # 800165d0 <__malloc_av_+0x8> -80004ad4: 00862683 lw a3,8(a2) -80004ad8: 0017e893 ori a7,a5,1 -80004adc: 00f70833 add a6,a4,a5 -80004ae0: 16a68463 beq a3,a0,80004c48 <_free_r+0x274> -80004ae4: 00c62603 lw a2,12(a2) -80004ae8: 00c6a623 sw a2,12(a3) -80004aec: 00d62423 sw a3,8(a2) -80004af0: 01172223 sw a7,4(a4) -80004af4: 00f82023 sw a5,0(a6) -80004af8: f6dff06f j 80004a64 <_free_r+0x90> -80004afc: 00008067 ret -80004b00: 0017e693 ori a3,a5,1 -80004b04: fed42e23 sw a3,-4(s0) -80004b08: 00f62023 sw a5,0(a2) -80004b0c: 1ff00693 li a3,511 -80004b10: f4f6fee3 bgeu a3,a5,80004a6c <_free_r+0x98> -80004b14: 0097d693 srli a3,a5,0x9 -80004b18: 00400613 li a2,4 -80004b1c: 0ed66863 bltu a2,a3,80004c0c <_free_r+0x238> -80004b20: 0067d693 srli a3,a5,0x6 -80004b24: 03968813 addi a6,a3,57 -80004b28: 03868613 addi a2,a3,56 -80004b2c: 00381813 slli a6,a6,0x3 -80004b30: 01058833 add a6,a1,a6 -80004b34: 00082683 lw a3,0(a6) -80004b38: ff880813 addi a6,a6,-8 -80004b3c: 12d80463 beq a6,a3,80004c64 <_free_r+0x290> -80004b40: 0046a603 lw a2,4(a3) -80004b44: ffc67613 andi a2,a2,-4 -80004b48: 00c7f663 bgeu a5,a2,80004b54 <_free_r+0x180> -80004b4c: 0086a683 lw a3,8(a3) -80004b50: fed818e3 bne a6,a3,80004b40 <_free_r+0x16c> -80004b54: 00c6a803 lw a6,12(a3) -80004b58: 01072623 sw a6,12(a4) -80004b5c: 00d72423 sw a3,8(a4) -80004b60: 00812403 lw s0,8(sp) -80004b64: 00c12083 lw ra,12(sp) -80004b68: 00e82423 sw a4,8(a6) -80004b6c: 00048513 mv a0,s1 -80004b70: 00412483 lw s1,4(sp) -80004b74: 00e6a623 sw a4,12(a3) -80004b78: 01010113 addi sp,sp,16 -80004b7c: 1790306f j 800084f4 <__malloc_unlock> -80004b80: 14081263 bnez a6,80004cc4 <_free_r+0x2f0> -80004b84: 00c62583 lw a1,12(a2) -80004b88: 00862603 lw a2,8(a2) -80004b8c: 00f687b3 add a5,a3,a5 -80004b90: 00812403 lw s0,8(sp) -80004b94: 00b62623 sw a1,12(a2) -80004b98: 00c5a423 sw a2,8(a1) -80004b9c: 0017e693 ori a3,a5,1 -80004ba0: 00c12083 lw ra,12(sp) -80004ba4: 00d72223 sw a3,4(a4) -80004ba8: 00048513 mv a0,s1 -80004bac: 00f70733 add a4,a4,a5 -80004bb0: 00412483 lw s1,4(sp) -80004bb4: 00f72023 sw a5,0(a4) -80004bb8: 01010113 addi sp,sp,16 -80004bbc: 1390306f j 800084f4 <__malloc_unlock> -80004bc0: 00187813 andi a6,a6,1 -80004bc4: 00d787b3 add a5,a5,a3 -80004bc8: 02081063 bnez a6,80004be8 <_free_r+0x214> -80004bcc: ff842503 lw a0,-8(s0) -80004bd0: 40a70733 sub a4,a4,a0 -80004bd4: 00c72683 lw a3,12(a4) -80004bd8: 00872603 lw a2,8(a4) -80004bdc: 00a787b3 add a5,a5,a0 -80004be0: 00d62623 sw a3,12(a2) -80004be4: 00c6a423 sw a2,8(a3) -80004be8: 0017e613 ori a2,a5,1 -80004bec: 3681a683 lw a3,872(gp) # 80016b70 <__malloc_trim_threshold> -80004bf0: 00c72223 sw a2,4(a4) -80004bf4: 00e5a423 sw a4,8(a1) -80004bf8: ead7e8e3 bltu a5,a3,80004aa8 <_free_r+0xd4> -80004bfc: 3741a583 lw a1,884(gp) # 80016b7c <__malloc_top_pad> -80004c00: 00048513 mv a0,s1 -80004c04: ca1ff0ef jal ra,800048a4 <_malloc_trim_r> -80004c08: ea1ff06f j 80004aa8 <_free_r+0xd4> -80004c0c: 01400613 li a2,20 -80004c10: 02d67463 bgeu a2,a3,80004c38 <_free_r+0x264> -80004c14: 05400613 li a2,84 -80004c18: 06d66463 bltu a2,a3,80004c80 <_free_r+0x2ac> -80004c1c: 00c7d693 srli a3,a5,0xc -80004c20: 06f68813 addi a6,a3,111 -80004c24: 06e68613 addi a2,a3,110 -80004c28: 00381813 slli a6,a6,0x3 -80004c2c: f05ff06f j 80004b30 <_free_r+0x15c> -80004c30: 00d787b3 add a5,a5,a3 -80004c34: ea1ff06f j 80004ad4 <_free_r+0x100> -80004c38: 05c68813 addi a6,a3,92 -80004c3c: 05b68613 addi a2,a3,91 -80004c40: 00381813 slli a6,a6,0x3 -80004c44: eedff06f j 80004b30 <_free_r+0x15c> -80004c48: 00e5aa23 sw a4,20(a1) -80004c4c: 00e5a823 sw a4,16(a1) -80004c50: 00a72623 sw a0,12(a4) -80004c54: 00a72423 sw a0,8(a4) -80004c58: 01172223 sw a7,4(a4) -80004c5c: 00f82023 sw a5,0(a6) -80004c60: e49ff06f j 80004aa8 <_free_r+0xd4> -80004c64: 0045a503 lw a0,4(a1) -80004c68: 40265613 srai a2,a2,0x2 -80004c6c: 00100793 li a5,1 -80004c70: 00c79633 sll a2,a5,a2 -80004c74: 00a66633 or a2,a2,a0 -80004c78: 00c5a223 sw a2,4(a1) -80004c7c: eddff06f j 80004b58 <_free_r+0x184> -80004c80: 15400613 li a2,340 -80004c84: 00d66c63 bltu a2,a3,80004c9c <_free_r+0x2c8> -80004c88: 00f7d693 srli a3,a5,0xf -80004c8c: 07868813 addi a6,a3,120 -80004c90: 07768613 addi a2,a3,119 -80004c94: 00381813 slli a6,a6,0x3 -80004c98: e99ff06f j 80004b30 <_free_r+0x15c> -80004c9c: 55400613 li a2,1364 -80004ca0: 00d66c63 bltu a2,a3,80004cb8 <_free_r+0x2e4> -80004ca4: 0127d693 srli a3,a5,0x12 -80004ca8: 07d68813 addi a6,a3,125 -80004cac: 07c68613 addi a2,a3,124 -80004cb0: 00381813 slli a6,a6,0x3 -80004cb4: e7dff06f j 80004b30 <_free_r+0x15c> -80004cb8: 3f800813 li a6,1016 -80004cbc: 07e00613 li a2,126 -80004cc0: e71ff06f j 80004b30 <_free_r+0x15c> -80004cc4: 0017e693 ori a3,a5,1 -80004cc8: 00d72223 sw a3,4(a4) -80004ccc: 00f62023 sw a5,0(a2) -80004cd0: dd9ff06f j 80004aa8 <_free_r+0xd4> +80004910 <_free_r>: +80004910: 12058463 beqz a1,80004a38 <_free_r+0x128> +80004914: ff010113 addi sp,sp,-16 +80004918: 00812423 sw s0,8(sp) +8000491c: 00912223 sw s1,4(sp) +80004920: 00058413 mv s0,a1 +80004924: 00050493 mv s1,a0 +80004928: 00112623 sw ra,12(sp) +8000492c: 301030ef jal ra,8000842c <__malloc_lock> +80004930: ffc42803 lw a6,-4(s0) +80004934: ff840713 addi a4,s0,-8 +80004938: ffe87793 andi a5,a6,-2 +8000493c: 00f70633 add a2,a4,a5 +80004940: dc018593 addi a1,gp,-576 # 800165c8 <__malloc_av_> +80004944: 00462683 lw a3,4(a2) +80004948: 0085a503 lw a0,8(a1) +8000494c: ffc6f693 andi a3,a3,-4 +80004950: 1ac50663 beq a0,a2,80004afc <_free_r+0x1ec> +80004954: 00d62223 sw a3,4(a2) +80004958: 00187813 andi a6,a6,1 +8000495c: 00d60533 add a0,a2,a3 +80004960: 08081e63 bnez a6,800049fc <_free_r+0xec> +80004964: ff842303 lw t1,-8(s0) +80004968: 00452803 lw a6,4(a0) +8000496c: 40670733 sub a4,a4,t1 +80004970: 00872883 lw a7,8(a4) +80004974: dc818513 addi a0,gp,-568 # 800165d0 <__malloc_av_+0x8> +80004978: 006787b3 add a5,a5,t1 +8000497c: 00187813 andi a6,a6,1 +80004980: 12a88e63 beq a7,a0,80004abc <_free_r+0x1ac> +80004984: 00c72303 lw t1,12(a4) +80004988: 0068a623 sw t1,12(a7) +8000498c: 01132423 sw a7,8(t1) +80004990: 1c080e63 beqz a6,80004b6c <_free_r+0x25c> +80004994: 0017e693 ori a3,a5,1 +80004998: 00d72223 sw a3,4(a4) +8000499c: 00f62023 sw a5,0(a2) +800049a0: 1ff00693 li a3,511 +800049a4: 0af6e663 bltu a3,a5,80004a50 <_free_r+0x140> +800049a8: ff87f693 andi a3,a5,-8 +800049ac: 00868693 addi a3,a3,8 +800049b0: 0045a503 lw a0,4(a1) +800049b4: 00d586b3 add a3,a1,a3 +800049b8: 0006a603 lw a2,0(a3) +800049bc: 0057d813 srli a6,a5,0x5 +800049c0: 00100793 li a5,1 +800049c4: 010797b3 sll a5,a5,a6 +800049c8: 00a7e7b3 or a5,a5,a0 +800049cc: ff868513 addi a0,a3,-8 +800049d0: 00a72623 sw a0,12(a4) +800049d4: 00c72423 sw a2,8(a4) +800049d8: 00f5a223 sw a5,4(a1) +800049dc: 00e6a023 sw a4,0(a3) +800049e0: 00e62623 sw a4,12(a2) +800049e4: 00812403 lw s0,8(sp) +800049e8: 00c12083 lw ra,12(sp) +800049ec: 00048513 mv a0,s1 +800049f0: 00412483 lw s1,4(sp) +800049f4: 01010113 addi sp,sp,16 +800049f8: 2390306f j 80008430 <__malloc_unlock> +800049fc: 00452503 lw a0,4(a0) +80004a00: 00157513 andi a0,a0,1 +80004a04: 02051c63 bnez a0,80004a3c <_free_r+0x12c> +80004a08: 00d787b3 add a5,a5,a3 +80004a0c: dc818513 addi a0,gp,-568 # 800165d0 <__malloc_av_+0x8> +80004a10: 00862683 lw a3,8(a2) +80004a14: 0017e893 ori a7,a5,1 +80004a18: 00f70833 add a6,a4,a5 +80004a1c: 16a68463 beq a3,a0,80004b84 <_free_r+0x274> +80004a20: 00c62603 lw a2,12(a2) +80004a24: 00c6a623 sw a2,12(a3) +80004a28: 00d62423 sw a3,8(a2) +80004a2c: 01172223 sw a7,4(a4) +80004a30: 00f82023 sw a5,0(a6) +80004a34: f6dff06f j 800049a0 <_free_r+0x90> +80004a38: 00008067 ret +80004a3c: 0017e693 ori a3,a5,1 +80004a40: fed42e23 sw a3,-4(s0) +80004a44: 00f62023 sw a5,0(a2) +80004a48: 1ff00693 li a3,511 +80004a4c: f4f6fee3 bgeu a3,a5,800049a8 <_free_r+0x98> +80004a50: 0097d693 srli a3,a5,0x9 +80004a54: 00400613 li a2,4 +80004a58: 0ed66863 bltu a2,a3,80004b48 <_free_r+0x238> +80004a5c: 0067d693 srli a3,a5,0x6 +80004a60: 03968813 addi a6,a3,57 +80004a64: 03868613 addi a2,a3,56 +80004a68: 00381813 slli a6,a6,0x3 +80004a6c: 01058833 add a6,a1,a6 +80004a70: 00082683 lw a3,0(a6) +80004a74: ff880813 addi a6,a6,-8 +80004a78: 12d80463 beq a6,a3,80004ba0 <_free_r+0x290> +80004a7c: 0046a603 lw a2,4(a3) +80004a80: ffc67613 andi a2,a2,-4 +80004a84: 00c7f663 bgeu a5,a2,80004a90 <_free_r+0x180> +80004a88: 0086a683 lw a3,8(a3) +80004a8c: fed818e3 bne a6,a3,80004a7c <_free_r+0x16c> +80004a90: 00c6a803 lw a6,12(a3) +80004a94: 01072623 sw a6,12(a4) +80004a98: 00d72423 sw a3,8(a4) +80004a9c: 00812403 lw s0,8(sp) +80004aa0: 00c12083 lw ra,12(sp) +80004aa4: 00e82423 sw a4,8(a6) +80004aa8: 00048513 mv a0,s1 +80004aac: 00412483 lw s1,4(sp) +80004ab0: 00e6a623 sw a4,12(a3) +80004ab4: 01010113 addi sp,sp,16 +80004ab8: 1790306f j 80008430 <__malloc_unlock> +80004abc: 14081263 bnez a6,80004c00 <_free_r+0x2f0> +80004ac0: 00c62583 lw a1,12(a2) +80004ac4: 00862603 lw a2,8(a2) +80004ac8: 00f687b3 add a5,a3,a5 +80004acc: 00812403 lw s0,8(sp) +80004ad0: 00b62623 sw a1,12(a2) +80004ad4: 00c5a423 sw a2,8(a1) +80004ad8: 0017e693 ori a3,a5,1 +80004adc: 00c12083 lw ra,12(sp) +80004ae0: 00d72223 sw a3,4(a4) +80004ae4: 00048513 mv a0,s1 +80004ae8: 00f70733 add a4,a4,a5 +80004aec: 00412483 lw s1,4(sp) +80004af0: 00f72023 sw a5,0(a4) +80004af4: 01010113 addi sp,sp,16 +80004af8: 1390306f j 80008430 <__malloc_unlock> +80004afc: 00187813 andi a6,a6,1 +80004b00: 00d787b3 add a5,a5,a3 +80004b04: 02081063 bnez a6,80004b24 <_free_r+0x214> +80004b08: ff842503 lw a0,-8(s0) +80004b0c: 40a70733 sub a4,a4,a0 +80004b10: 00c72683 lw a3,12(a4) +80004b14: 00872603 lw a2,8(a4) +80004b18: 00a787b3 add a5,a5,a0 +80004b1c: 00d62623 sw a3,12(a2) +80004b20: 00c6a423 sw a2,8(a3) +80004b24: 0017e613 ori a2,a5,1 +80004b28: 3681a683 lw a3,872(gp) # 80016b70 <__malloc_trim_threshold> +80004b2c: 00c72223 sw a2,4(a4) +80004b30: 00e5a423 sw a4,8(a1) +80004b34: ead7e8e3 bltu a5,a3,800049e4 <_free_r+0xd4> +80004b38: 39c1a583 lw a1,924(gp) # 80016ba4 <__malloc_top_pad> +80004b3c: 00048513 mv a0,s1 +80004b40: ca1ff0ef jal ra,800047e0 <_malloc_trim_r> +80004b44: ea1ff06f j 800049e4 <_free_r+0xd4> +80004b48: 01400613 li a2,20 +80004b4c: 02d67463 bgeu a2,a3,80004b74 <_free_r+0x264> +80004b50: 05400613 li a2,84 +80004b54: 06d66463 bltu a2,a3,80004bbc <_free_r+0x2ac> +80004b58: 00c7d693 srli a3,a5,0xc +80004b5c: 06f68813 addi a6,a3,111 +80004b60: 06e68613 addi a2,a3,110 +80004b64: 00381813 slli a6,a6,0x3 +80004b68: f05ff06f j 80004a6c <_free_r+0x15c> +80004b6c: 00d787b3 add a5,a5,a3 +80004b70: ea1ff06f j 80004a10 <_free_r+0x100> +80004b74: 05c68813 addi a6,a3,92 +80004b78: 05b68613 addi a2,a3,91 +80004b7c: 00381813 slli a6,a6,0x3 +80004b80: eedff06f j 80004a6c <_free_r+0x15c> +80004b84: 00e5aa23 sw a4,20(a1) +80004b88: 00e5a823 sw a4,16(a1) +80004b8c: 00a72623 sw a0,12(a4) +80004b90: 00a72423 sw a0,8(a4) +80004b94: 01172223 sw a7,4(a4) +80004b98: 00f82023 sw a5,0(a6) +80004b9c: e49ff06f j 800049e4 <_free_r+0xd4> +80004ba0: 0045a503 lw a0,4(a1) +80004ba4: 40265613 srai a2,a2,0x2 +80004ba8: 00100793 li a5,1 +80004bac: 00c79633 sll a2,a5,a2 +80004bb0: 00a66633 or a2,a2,a0 +80004bb4: 00c5a223 sw a2,4(a1) +80004bb8: eddff06f j 80004a94 <_free_r+0x184> +80004bbc: 15400613 li a2,340 +80004bc0: 00d66c63 bltu a2,a3,80004bd8 <_free_r+0x2c8> +80004bc4: 00f7d693 srli a3,a5,0xf +80004bc8: 07868813 addi a6,a3,120 +80004bcc: 07768613 addi a2,a3,119 +80004bd0: 00381813 slli a6,a6,0x3 +80004bd4: e99ff06f j 80004a6c <_free_r+0x15c> +80004bd8: 55400613 li a2,1364 +80004bdc: 00d66c63 bltu a2,a3,80004bf4 <_free_r+0x2e4> +80004be0: 0127d693 srli a3,a5,0x12 +80004be4: 07d68813 addi a6,a3,125 +80004be8: 07c68613 addi a2,a3,124 +80004bec: 00381813 slli a6,a6,0x3 +80004bf0: e7dff06f j 80004a6c <_free_r+0x15c> +80004bf4: 3f800813 li a6,1016 +80004bf8: 07e00613 li a2,126 +80004bfc: e71ff06f j 80004a6c <_free_r+0x15c> +80004c00: 0017e693 ori a3,a5,1 +80004c04: 00d72223 sw a3,4(a4) +80004c08: 00f62023 sw a5,0(a2) +80004c0c: dd9ff06f j 800049e4 <_free_r+0xd4> -80004cd4 <_fwalk>: -80004cd4: fe010113 addi sp,sp,-32 -80004cd8: 01212823 sw s2,16(sp) -80004cdc: 01312623 sw s3,12(sp) -80004ce0: 01412423 sw s4,8(sp) -80004ce4: 01512223 sw s5,4(sp) -80004ce8: 01612023 sw s6,0(sp) -80004cec: 00112e23 sw ra,28(sp) -80004cf0: 00812c23 sw s0,24(sp) -80004cf4: 00912a23 sw s1,20(sp) -80004cf8: 00058b13 mv s6,a1 -80004cfc: 2e050a93 addi s5,a0,736 -80004d00: 00000a13 li s4,0 -80004d04: 00100993 li s3,1 -80004d08: fff00913 li s2,-1 -80004d0c: 004aa483 lw s1,4(s5) -80004d10: 008aa403 lw s0,8(s5) -80004d14: fff48493 addi s1,s1,-1 -80004d18: 0204c663 bltz s1,80004d44 <_fwalk+0x70> -80004d1c: 00c45783 lhu a5,12(s0) -80004d20: fff48493 addi s1,s1,-1 -80004d24: 00f9fc63 bgeu s3,a5,80004d3c <_fwalk+0x68> -80004d28: 00e41783 lh a5,14(s0) -80004d2c: 00040513 mv a0,s0 -80004d30: 01278663 beq a5,s2,80004d3c <_fwalk+0x68> -80004d34: 000b00e7 jalr s6 -80004d38: 00aa6a33 or s4,s4,a0 -80004d3c: 06840413 addi s0,s0,104 -80004d40: fd249ee3 bne s1,s2,80004d1c <_fwalk+0x48> -80004d44: 000aaa83 lw s5,0(s5) -80004d48: fc0a92e3 bnez s5,80004d0c <_fwalk+0x38> -80004d4c: 01c12083 lw ra,28(sp) -80004d50: 01812403 lw s0,24(sp) -80004d54: 01412483 lw s1,20(sp) -80004d58: 01012903 lw s2,16(sp) -80004d5c: 00c12983 lw s3,12(sp) -80004d60: 00412a83 lw s5,4(sp) -80004d64: 00012b03 lw s6,0(sp) -80004d68: 000a0513 mv a0,s4 -80004d6c: 00812a03 lw s4,8(sp) -80004d70: 02010113 addi sp,sp,32 -80004d74: 00008067 ret +80004c10 <_fwalk>: +80004c10: fe010113 addi sp,sp,-32 +80004c14: 01212823 sw s2,16(sp) +80004c18: 01312623 sw s3,12(sp) +80004c1c: 01412423 sw s4,8(sp) +80004c20: 01512223 sw s5,4(sp) +80004c24: 01612023 sw s6,0(sp) +80004c28: 00112e23 sw ra,28(sp) +80004c2c: 00812c23 sw s0,24(sp) +80004c30: 00912a23 sw s1,20(sp) +80004c34: 00058b13 mv s6,a1 +80004c38: 2e050a93 addi s5,a0,736 +80004c3c: 00000a13 li s4,0 +80004c40: 00100993 li s3,1 +80004c44: fff00913 li s2,-1 +80004c48: 004aa483 lw s1,4(s5) +80004c4c: 008aa403 lw s0,8(s5) +80004c50: fff48493 addi s1,s1,-1 +80004c54: 0204c663 bltz s1,80004c80 <_fwalk+0x70> +80004c58: 00c45783 lhu a5,12(s0) +80004c5c: fff48493 addi s1,s1,-1 +80004c60: 00f9fc63 bgeu s3,a5,80004c78 <_fwalk+0x68> +80004c64: 00e41783 lh a5,14(s0) +80004c68: 00040513 mv a0,s0 +80004c6c: 01278663 beq a5,s2,80004c78 <_fwalk+0x68> +80004c70: 000b00e7 jalr s6 +80004c74: 00aa6a33 or s4,s4,a0 +80004c78: 06840413 addi s0,s0,104 +80004c7c: fd249ee3 bne s1,s2,80004c58 <_fwalk+0x48> +80004c80: 000aaa83 lw s5,0(s5) +80004c84: fc0a92e3 bnez s5,80004c48 <_fwalk+0x38> +80004c88: 01c12083 lw ra,28(sp) +80004c8c: 01812403 lw s0,24(sp) +80004c90: 01412483 lw s1,20(sp) +80004c94: 01012903 lw s2,16(sp) +80004c98: 00c12983 lw s3,12(sp) +80004c9c: 00412a83 lw s5,4(sp) +80004ca0: 00012b03 lw s6,0(sp) +80004ca4: 000a0513 mv a0,s4 +80004ca8: 00812a03 lw s4,8(sp) +80004cac: 02010113 addi sp,sp,32 +80004cb0: 00008067 ret -80004d78 <_fwalk_reent>: -80004d78: fd010113 addi sp,sp,-48 -80004d7c: 03212023 sw s2,32(sp) -80004d80: 01312e23 sw s3,28(sp) -80004d84: 01412c23 sw s4,24(sp) -80004d88: 01512a23 sw s5,20(sp) -80004d8c: 01612823 sw s6,16(sp) -80004d90: 01712623 sw s7,12(sp) -80004d94: 02112623 sw ra,44(sp) -80004d98: 02812423 sw s0,40(sp) -80004d9c: 02912223 sw s1,36(sp) -80004da0: 00050a93 mv s5,a0 -80004da4: 00058b93 mv s7,a1 -80004da8: 2e050b13 addi s6,a0,736 -80004dac: 00000a13 li s4,0 -80004db0: 00100993 li s3,1 -80004db4: fff00913 li s2,-1 -80004db8: 004b2483 lw s1,4(s6) -80004dbc: 008b2403 lw s0,8(s6) -80004dc0: fff48493 addi s1,s1,-1 -80004dc4: 0204c863 bltz s1,80004df4 <_fwalk_reent+0x7c> -80004dc8: 00c45783 lhu a5,12(s0) -80004dcc: fff48493 addi s1,s1,-1 -80004dd0: 00f9fe63 bgeu s3,a5,80004dec <_fwalk_reent+0x74> -80004dd4: 00e41783 lh a5,14(s0) -80004dd8: 00040593 mv a1,s0 -80004ddc: 000a8513 mv a0,s5 -80004de0: 01278663 beq a5,s2,80004dec <_fwalk_reent+0x74> -80004de4: 000b80e7 jalr s7 -80004de8: 00aa6a33 or s4,s4,a0 -80004dec: 06840413 addi s0,s0,104 -80004df0: fd249ce3 bne s1,s2,80004dc8 <_fwalk_reent+0x50> -80004df4: 000b2b03 lw s6,0(s6) -80004df8: fc0b10e3 bnez s6,80004db8 <_fwalk_reent+0x40> -80004dfc: 02c12083 lw ra,44(sp) -80004e00: 02812403 lw s0,40(sp) -80004e04: 02412483 lw s1,36(sp) -80004e08: 02012903 lw s2,32(sp) -80004e0c: 01c12983 lw s3,28(sp) -80004e10: 01412a83 lw s5,20(sp) -80004e14: 01012b03 lw s6,16(sp) -80004e18: 00c12b83 lw s7,12(sp) -80004e1c: 000a0513 mv a0,s4 -80004e20: 01812a03 lw s4,24(sp) -80004e24: 03010113 addi sp,sp,48 -80004e28: 00008067 ret +80004cb4 <_fwalk_reent>: +80004cb4: fd010113 addi sp,sp,-48 +80004cb8: 03212023 sw s2,32(sp) +80004cbc: 01312e23 sw s3,28(sp) +80004cc0: 01412c23 sw s4,24(sp) +80004cc4: 01512a23 sw s5,20(sp) +80004cc8: 01612823 sw s6,16(sp) +80004ccc: 01712623 sw s7,12(sp) +80004cd0: 02112623 sw ra,44(sp) +80004cd4: 02812423 sw s0,40(sp) +80004cd8: 02912223 sw s1,36(sp) +80004cdc: 00050a93 mv s5,a0 +80004ce0: 00058b93 mv s7,a1 +80004ce4: 2e050b13 addi s6,a0,736 +80004ce8: 00000a13 li s4,0 +80004cec: 00100993 li s3,1 +80004cf0: fff00913 li s2,-1 +80004cf4: 004b2483 lw s1,4(s6) +80004cf8: 008b2403 lw s0,8(s6) +80004cfc: fff48493 addi s1,s1,-1 +80004d00: 0204c863 bltz s1,80004d30 <_fwalk_reent+0x7c> +80004d04: 00c45783 lhu a5,12(s0) +80004d08: fff48493 addi s1,s1,-1 +80004d0c: 00f9fe63 bgeu s3,a5,80004d28 <_fwalk_reent+0x74> +80004d10: 00e41783 lh a5,14(s0) +80004d14: 00040593 mv a1,s0 +80004d18: 000a8513 mv a0,s5 +80004d1c: 01278663 beq a5,s2,80004d28 <_fwalk_reent+0x74> +80004d20: 000b80e7 jalr s7 +80004d24: 00aa6a33 or s4,s4,a0 +80004d28: 06840413 addi s0,s0,104 +80004d2c: fd249ce3 bne s1,s2,80004d04 <_fwalk_reent+0x50> +80004d30: 000b2b03 lw s6,0(s6) +80004d34: fc0b10e3 bnez s6,80004cf4 <_fwalk_reent+0x40> +80004d38: 02c12083 lw ra,44(sp) +80004d3c: 02812403 lw s0,40(sp) +80004d40: 02412483 lw s1,36(sp) +80004d44: 02012903 lw s2,32(sp) +80004d48: 01c12983 lw s3,28(sp) +80004d4c: 01412a83 lw s5,20(sp) +80004d50: 01012b03 lw s6,16(sp) +80004d54: 00c12b83 lw s7,12(sp) +80004d58: 000a0513 mv a0,s4 +80004d5c: 01812a03 lw s4,24(sp) +80004d60: 03010113 addi sp,sp,48 +80004d64: 00008067 ret -80004e2c : -80004e2c: 00450693 addi a3,a0,4 -80004e30: 00000793 li a5,0 -80004e34: 01a50513 addi a0,a0,26 -80004e38: ffff8837 lui a6,0xffff8 -80004e3c: 01c0006f j 80004e58 -80004e40: 00179793 slli a5,a5,0x1 -80004e44: 00e69023 sh a4,0(a3) -80004e48: 01079793 slli a5,a5,0x10 -80004e4c: 00268693 addi a3,a3,2 -80004e50: 0107d793 srli a5,a5,0x10 -80004e54: 02d50e63 beq a0,a3,80004e90 -80004e58: 0006d703 lhu a4,0(a3) -80004e5c: 00177613 andi a2,a4,1 -80004e60: 00060463 beqz a2,80004e68 -80004e64: 0017e793 ori a5,a5,1 -80004e68: 00175713 srli a4,a4,0x1 -80004e6c: 0027f613 andi a2,a5,2 -80004e70: 010765b3 or a1,a4,a6 -80004e74: fc0606e3 beqz a2,80004e40 -80004e78: 00179793 slli a5,a5,0x1 -80004e7c: 00b69023 sh a1,0(a3) -80004e80: 01079793 slli a5,a5,0x10 -80004e84: 00268693 addi a3,a3,2 -80004e88: 0107d793 srli a5,a5,0x10 -80004e8c: fcd516e3 bne a0,a3,80004e58 -80004e90: 00008067 ret +80004d68 : +80004d68: 00450693 addi a3,a0,4 +80004d6c: 00000793 li a5,0 +80004d70: 01a50513 addi a0,a0,26 +80004d74: ffff8837 lui a6,0xffff8 +80004d78: 01c0006f j 80004d94 +80004d7c: 00179793 slli a5,a5,0x1 +80004d80: 00e69023 sh a4,0(a3) +80004d84: 01079793 slli a5,a5,0x10 +80004d88: 00268693 addi a3,a3,2 +80004d8c: 0107d793 srli a5,a5,0x10 +80004d90: 02d50e63 beq a0,a3,80004dcc +80004d94: 0006d703 lhu a4,0(a3) +80004d98: 00177613 andi a2,a4,1 +80004d9c: 00060463 beqz a2,80004da4 +80004da0: 0017e793 ori a5,a5,1 +80004da4: 00175713 srli a4,a4,0x1 +80004da8: 0027f613 andi a2,a5,2 +80004dac: 010765b3 or a1,a4,a6 +80004db0: fc0606e3 beqz a2,80004d7c +80004db4: 00179793 slli a5,a5,0x1 +80004db8: 00b69023 sh a1,0(a3) +80004dbc: 01079793 slli a5,a5,0x10 +80004dc0: 00268693 addi a3,a3,2 +80004dc4: 0107d793 srli a5,a5,0x10 +80004dc8: fcd516e3 bne a0,a3,80004d94 +80004dcc: 00008067 ret -80004e94 : -80004e94: 01850693 addi a3,a0,24 -80004e98: 00000713 li a4,0 -80004e9c: 00250513 addi a0,a0,2 -80004ea0: 01c0006f j 80004ebc -80004ea4: 00171713 slli a4,a4,0x1 -80004ea8: 00f69023 sh a5,0(a3) -80004eac: 01071713 slli a4,a4,0x10 -80004eb0: ffe68693 addi a3,a3,-2 -80004eb4: 01075713 srli a4,a4,0x10 -80004eb8: 04d50463 beq a0,a3,80004f00 -80004ebc: 0006d783 lhu a5,0(a3) -80004ec0: 01079613 slli a2,a5,0x10 -80004ec4: 41065613 srai a2,a2,0x10 -80004ec8: 00179793 slli a5,a5,0x1 -80004ecc: 00065463 bgez a2,80004ed4 -80004ed0: 00176713 ori a4,a4,1 -80004ed4: 01079793 slli a5,a5,0x10 -80004ed8: 0107d793 srli a5,a5,0x10 -80004edc: 00277613 andi a2,a4,2 -80004ee0: 0017e593 ori a1,a5,1 -80004ee4: fc0600e3 beqz a2,80004ea4 -80004ee8: 00171713 slli a4,a4,0x1 -80004eec: 00b69023 sh a1,0(a3) -80004ef0: 01071713 slli a4,a4,0x10 -80004ef4: ffe68693 addi a3,a3,-2 -80004ef8: 01075713 srli a4,a4,0x10 -80004efc: fcd510e3 bne a0,a3,80004ebc -80004f00: 00008067 ret +80004dd0 : +80004dd0: 01850693 addi a3,a0,24 +80004dd4: 00000713 li a4,0 +80004dd8: 00250513 addi a0,a0,2 +80004ddc: 01c0006f j 80004df8 +80004de0: 00171713 slli a4,a4,0x1 +80004de4: 00f69023 sh a5,0(a3) +80004de8: 01071713 slli a4,a4,0x10 +80004dec: ffe68693 addi a3,a3,-2 +80004df0: 01075713 srli a4,a4,0x10 +80004df4: 04d50463 beq a0,a3,80004e3c +80004df8: 0006d783 lhu a5,0(a3) +80004dfc: 01079613 slli a2,a5,0x10 +80004e00: 41065613 srai a2,a2,0x10 +80004e04: 00179793 slli a5,a5,0x1 +80004e08: 00065463 bgez a2,80004e10 +80004e0c: 00176713 ori a4,a4,1 +80004e10: 01079793 slli a5,a5,0x10 +80004e14: 0107d793 srli a5,a5,0x10 +80004e18: 00277613 andi a2,a4,2 +80004e1c: 0017e593 ori a1,a5,1 +80004e20: fc0600e3 beqz a2,80004de0 +80004e24: 00171713 slli a4,a4,0x1 +80004e28: 00b69023 sh a1,0(a3) +80004e2c: 01071713 slli a4,a4,0x10 +80004e30: ffe68693 addi a3,a3,-2 +80004e34: 01075713 srli a4,a4,0x10 +80004e38: fcd510e3 bne a0,a3,80004df8 +80004e3c: 00008067 ret -80004f04 : -80004f04: fe010113 addi sp,sp,-32 -80004f08: 00010e37 lui t3,0x10 -80004f0c: 00011d23 sh zero,26(sp) -80004f10: 00011e23 sh zero,28(sp) -80004f14: 01858593 addi a1,a1,24 -80004f18: 01c10793 addi a5,sp,28 -80004f1c: 00810813 addi a6,sp,8 -80004f20: fffe0e13 addi t3,t3,-1 # ffff <_start-0x7fff0001> -80004f24: 0005d703 lhu a4,0(a1) -80004f28: ffe78793 addi a5,a5,-2 -80004f2c: ffe58593 addi a1,a1,-2 -80004f30: 02071863 bnez a4,80004f60 -80004f34: fe079f23 sh zero,-2(a5) -80004f38: ff0796e3 bne a5,a6,80004f24 -80004f3c: 00460613 addi a2,a2,4 -80004f40: 01e10693 addi a3,sp,30 -80004f44: 0007d703 lhu a4,0(a5) -80004f48: 00278793 addi a5,a5,2 -80004f4c: 00260613 addi a2,a2,2 -80004f50: fee61f23 sh a4,-2(a2) -80004f54: fed798e3 bne a5,a3,80004f44 -80004f58: 02010113 addi sp,sp,32 -80004f5c: 00008067 ret -80004f60: 02a70733 mul a4,a4,a0 -80004f64: 0027d883 lhu a7,2(a5) -80004f68: 0007d303 lhu t1,0(a5) -80004f6c: 01c776b3 and a3,a4,t3 -80004f70: 011686b3 add a3,a3,a7 -80004f74: 01075713 srli a4,a4,0x10 -80004f78: 0106d893 srli a7,a3,0x10 -80004f7c: 00670733 add a4,a4,t1 -80004f80: 01170733 add a4,a4,a7 -80004f84: 01075893 srli a7,a4,0x10 -80004f88: 00d79123 sh a3,2(a5) -80004f8c: 00e79023 sh a4,0(a5) -80004f90: ff179f23 sh a7,-2(a5) -80004f94: f90798e3 bne a5,a6,80004f24 -80004f98: fa5ff06f j 80004f3c +80004e40 : +80004e40: fe010113 addi sp,sp,-32 +80004e44: 00010e37 lui t3,0x10 +80004e48: 00011d23 sh zero,26(sp) +80004e4c: 00011e23 sh zero,28(sp) +80004e50: 01858593 addi a1,a1,24 +80004e54: 01c10793 addi a5,sp,28 +80004e58: 00810813 addi a6,sp,8 +80004e5c: fffe0e13 addi t3,t3,-1 # ffff <_start-0x7fff0001> +80004e60: 0005d703 lhu a4,0(a1) +80004e64: ffe78793 addi a5,a5,-2 +80004e68: ffe58593 addi a1,a1,-2 +80004e6c: 02071863 bnez a4,80004e9c +80004e70: fe079f23 sh zero,-2(a5) +80004e74: ff0796e3 bne a5,a6,80004e60 +80004e78: 00460613 addi a2,a2,4 +80004e7c: 01e10693 addi a3,sp,30 +80004e80: 0007d703 lhu a4,0(a5) +80004e84: 00278793 addi a5,a5,2 +80004e88: 00260613 addi a2,a2,2 +80004e8c: fee61f23 sh a4,-2(a2) +80004e90: fed798e3 bne a5,a3,80004e80 +80004e94: 02010113 addi sp,sp,32 +80004e98: 00008067 ret +80004e9c: 02a70733 mul a4,a4,a0 +80004ea0: 0027d883 lhu a7,2(a5) +80004ea4: 0007d303 lhu t1,0(a5) +80004ea8: 01c776b3 and a3,a4,t3 +80004eac: 011686b3 add a3,a3,a7 +80004eb0: 01075713 srli a4,a4,0x10 +80004eb4: 0106d893 srli a7,a3,0x10 +80004eb8: 00670733 add a4,a4,t1 +80004ebc: 01170733 add a4,a4,a7 +80004ec0: 01075893 srli a7,a4,0x10 +80004ec4: 00d79123 sh a3,2(a5) +80004ec8: 00e79023 sh a4,0(a5) +80004ecc: ff179f23 sh a7,-2(a5) +80004ed0: f90798e3 bne a5,a6,80004e60 +80004ed4: fa5ff06f j 80004e78 -80004f9c : -80004f9c: 01250713 addi a4,a0,18 -80004fa0: 00055783 lhu a5,0(a0) -80004fa4: 00250513 addi a0,a0,2 -80004fa8: 00079863 bnez a5,80004fb8 -80004fac: fee51ae3 bne a0,a4,80004fa0 -80004fb0: 00000513 li a0,0 -80004fb4: 00008067 ret -80004fb8: 00100513 li a0,1 -80004fbc: 00008067 ret +80004ed8 : +80004ed8: 01250713 addi a4,a0,18 +80004edc: 00055783 lhu a5,0(a0) +80004ee0: 00250513 addi a0,a0,2 +80004ee4: 00079863 bnez a5,80004ef4 +80004ee8: fee51ae3 bne a0,a4,80004edc +80004eec: 00000513 li a0,0 +80004ef0: 00008067 ret +80004ef4: 00100513 li a0,1 +80004ef8: 00008067 ret -80004fc0 : -80004fc0: ff010113 addi sp,sp,-16 -80004fc4: 00912223 sw s1,4(sp) -80004fc8: 01255483 lhu s1,18(a0) -80004fcc: 00812423 sw s0,8(sp) -80004fd0: 00112623 sw ra,12(sp) -80004fd4: fff4c793 not a5,s1 -80004fd8: 01179713 slli a4,a5,0x11 -80004fdc: 00050413 mv s0,a0 -80004fe0: 00071663 bnez a4,80004fec -80004fe4: fb9ff0ef jal ra,80004f9c -80004fe8: 00051863 bnez a0,80004ff8 -80004fec: ffff87b7 lui a5,0xffff8 -80004ff0: 00f4c4b3 xor s1,s1,a5 -80004ff4: 00941923 sh s1,18(s0) -80004ff8: 00c12083 lw ra,12(sp) -80004ffc: 00812403 lw s0,8(sp) -80005000: 00412483 lw s1,4(sp) -80005004: 01010113 addi sp,sp,16 -80005008: 00008067 ret +80004efc : +80004efc: ff010113 addi sp,sp,-16 +80004f00: 00912223 sw s1,4(sp) +80004f04: 01255483 lhu s1,18(a0) +80004f08: 00812423 sw s0,8(sp) +80004f0c: 00112623 sw ra,12(sp) +80004f10: fff4c793 not a5,s1 +80004f14: 01179713 slli a4,a5,0x11 +80004f18: 00050413 mv s0,a0 +80004f1c: 00071663 bnez a4,80004f28 +80004f20: fb9ff0ef jal ra,80004ed8 +80004f24: 00051863 bnez a0,80004f34 +80004f28: ffff87b7 lui a5,0xffff8 +80004f2c: 00f4c4b3 xor s1,s1,a5 +80004f30: 00941923 sh s1,18(s0) +80004f34: 00c12083 lw ra,12(sp) +80004f38: 00812403 lw s0,8(sp) +80004f3c: 00412483 lw s1,4(sp) +80004f40: 01010113 addi sp,sp,16 +80004f44: 00008067 ret -8000500c : -8000500c: ff010113 addi sp,sp,-16 -80005010: 00812423 sw s0,8(sp) -80005014: 01255403 lhu s0,18(a0) -80005018: 00112623 sw ra,12(sp) -8000501c: fff44793 not a5,s0 -80005020: 01179713 slli a4,a5,0x11 -80005024: 00071a63 bnez a4,80005038 -80005028: f75ff0ef jal ra,80004f9c -8000502c: 00050793 mv a5,a0 -80005030: 00000513 li a0,0 -80005034: 00079463 bnez a5,8000503c -80005038: 00f45513 srli a0,s0,0xf -8000503c: 00c12083 lw ra,12(sp) -80005040: 00812403 lw s0,8(sp) -80005044: 01010113 addi sp,sp,16 -80005048: 00008067 ret +80004f48 : +80004f48: ff010113 addi sp,sp,-16 +80004f4c: 00812423 sw s0,8(sp) +80004f50: 01255403 lhu s0,18(a0) +80004f54: 00112623 sw ra,12(sp) +80004f58: fff44793 not a5,s0 +80004f5c: 01179713 slli a4,a5,0x11 +80004f60: 00071a63 bnez a4,80004f74 +80004f64: f75ff0ef jal ra,80004ed8 +80004f68: 00050793 mv a5,a0 +80004f6c: 00000513 li a0,0 +80004f70: 00079463 bnez a5,80004f78 +80004f74: 00f45513 srli a0,s0,0xf +80004f78: 00c12083 lw ra,12(sp) +80004f7c: 00812403 lw s0,8(sp) +80004f80: 01010113 addi sp,sp,16 +80004f84: 00008067 ret -8000504c : -8000504c: 01255783 lhu a5,18(a0) -80005050: fd010113 addi sp,sp,-48 -80005054: 02812423 sw s0,40(sp) -80005058: 00f7d793 srli a5,a5,0xf -8000505c: 02912223 sw s1,36(sp) -80005060: 02112623 sw ra,44(sp) -80005064: 03212023 sw s2,32(sp) -80005068: 01312e23 sw s3,28(sp) -8000506c: 40f007b3 neg a5,a5 -80005070: 00f59023 sh a5,0(a1) -80005074: 01255783 lhu a5,18(a0) -80005078: 00008737 lui a4,0x8 -8000507c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80005080: 00f777b3 and a5,a4,a5 -80005084: 00f59123 sh a5,2(a1) -80005088: 00050493 mv s1,a0 -8000508c: 01050413 addi s0,a0,16 -80005090: 04e78263 beq a5,a4,800050d4 -80005094: 00658793 addi a5,a1,6 -80005098: 00059223 sh zero,4(a1) -8000509c: ffe50513 addi a0,a0,-2 -800050a0: 00045703 lhu a4,0(s0) -800050a4: ffe40413 addi s0,s0,-2 -800050a8: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe13c6> -800050ac: fee79f23 sh a4,-2(a5) -800050b0: fe8518e3 bne a0,s0,800050a0 -800050b4: 00059c23 sh zero,24(a1) -800050b8: 02c12083 lw ra,44(sp) -800050bc: 02812403 lw s0,40(sp) -800050c0: 02412483 lw s1,36(sp) -800050c4: 02012903 lw s2,32(sp) -800050c8: 01c12983 lw s3,28(sp) -800050cc: 03010113 addi sp,sp,48 -800050d0: 00008067 ret -800050d4: 01255703 lhu a4,18(a0) -800050d8: 00458913 addi s2,a1,4 -800050dc: 00e7f733 and a4,a5,a4 -800050e0: 02f71c63 bne a4,a5,80005118 -800050e4: 00b12623 sw a1,12(sp) -800050e8: eb5ff0ef jal ra,80004f9c -800050ec: 00c12583 lw a1,12(sp) -800050f0: 02050463 beqz a0,80005118 -800050f4: 00658793 addi a5,a1,6 -800050f8: 00059223 sh zero,4(a1) -800050fc: ffc48513 addi a0,s1,-4 -80005100: 00045703 lhu a4,0(s0) -80005104: ffe40413 addi s0,s0,-2 -80005108: 00278793 addi a5,a5,2 -8000510c: fee79f23 sh a4,-2(a5) -80005110: fe8518e3 bne a0,s0,80005100 -80005114: fa5ff06f j 800050b8 -80005118: 01a58993 addi s3,a1,26 -8000511c: 00290913 addi s2,s2,2 -80005120: fe091f23 sh zero,-2(s2) -80005124: ff299ce3 bne s3,s2,8000511c -80005128: 02c12083 lw ra,44(sp) -8000512c: 02812403 lw s0,40(sp) -80005130: 02412483 lw s1,36(sp) -80005134: 02012903 lw s2,32(sp) -80005138: 01c12983 lw s3,28(sp) -8000513c: 03010113 addi sp,sp,48 -80005140: 00008067 ret +80004f88 : +80004f88: 01255783 lhu a5,18(a0) +80004f8c: fd010113 addi sp,sp,-48 +80004f90: 02812423 sw s0,40(sp) +80004f94: 00f7d793 srli a5,a5,0xf +80004f98: 02912223 sw s1,36(sp) +80004f9c: 02112623 sw ra,44(sp) +80004fa0: 03212023 sw s2,32(sp) +80004fa4: 01312e23 sw s3,28(sp) +80004fa8: 40f007b3 neg a5,a5 +80004fac: 00f59023 sh a5,0(a1) +80004fb0: 01255783 lhu a5,18(a0) +80004fb4: 00008737 lui a4,0x8 +80004fb8: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80004fbc: 00f777b3 and a5,a4,a5 +80004fc0: 00f59123 sh a5,2(a1) +80004fc4: 00050493 mv s1,a0 +80004fc8: 01050413 addi s0,a0,16 +80004fcc: 04e78263 beq a5,a4,80005010 +80004fd0: 00658793 addi a5,a1,6 +80004fd4: 00059223 sh zero,4(a1) +80004fd8: ffe50513 addi a0,a0,-2 +80004fdc: 00045703 lhu a4,0(s0) +80004fe0: ffe40413 addi s0,s0,-2 +80004fe4: 00278793 addi a5,a5,2 # ffff8002 <__BSS_END__+0x7ffe13c6> +80004fe8: fee79f23 sh a4,-2(a5) +80004fec: fe8518e3 bne a0,s0,80004fdc +80004ff0: 00059c23 sh zero,24(a1) +80004ff4: 02c12083 lw ra,44(sp) +80004ff8: 02812403 lw s0,40(sp) +80004ffc: 02412483 lw s1,36(sp) +80005000: 02012903 lw s2,32(sp) +80005004: 01c12983 lw s3,28(sp) +80005008: 03010113 addi sp,sp,48 +8000500c: 00008067 ret +80005010: 01255703 lhu a4,18(a0) +80005014: 00458913 addi s2,a1,4 +80005018: 00e7f733 and a4,a5,a4 +8000501c: 02f71c63 bne a4,a5,80005054 +80005020: 00b12623 sw a1,12(sp) +80005024: eb5ff0ef jal ra,80004ed8 +80005028: 00c12583 lw a1,12(sp) +8000502c: 02050463 beqz a0,80005054 +80005030: 00658793 addi a5,a1,6 +80005034: 00059223 sh zero,4(a1) +80005038: ffc48513 addi a0,s1,-4 +8000503c: 00045703 lhu a4,0(s0) +80005040: ffe40413 addi s0,s0,-2 +80005044: 00278793 addi a5,a5,2 +80005048: fee79f23 sh a4,-2(a5) +8000504c: fe8518e3 bne a0,s0,8000503c +80005050: fa5ff06f j 80004ff4 +80005054: 01a58993 addi s3,a1,26 +80005058: 00290913 addi s2,s2,2 +8000505c: fe091f23 sh zero,-2(s2) +80005060: ff299ce3 bne s3,s2,80005058 +80005064: 02c12083 lw ra,44(sp) +80005068: 02812403 lw s0,40(sp) +8000506c: 02412483 lw s1,36(sp) +80005070: 02012903 lw s2,32(sp) +80005074: 01c12983 lw s3,28(sp) +80005078: 03010113 addi sp,sp,48 +8000507c: 00008067 ret -80005144 : -80005144: 01255783 lhu a5,18(a0) -80005148: fb010113 addi sp,sp,-80 -8000514c: 04812423 sw s0,72(sp) -80005150: fff7c793 not a5,a5 -80005154: 04912223 sw s1,68(sp) -80005158: 04112623 sw ra,76(sp) -8000515c: 01179713 slli a4,a5,0x11 -80005160: 00050493 mv s1,a0 -80005164: 00058413 mv s0,a1 -80005168: 00071663 bnez a4,80005174 -8000516c: e31ff0ef jal ra,80004f9c -80005170: 08051263 bnez a0,800051f4 -80005174: 01245783 lhu a5,18(s0) -80005178: fff7c793 not a5,a5 -8000517c: 01179713 slli a4,a5,0x11 -80005180: 06070463 beqz a4,800051e8 -80005184: 00810593 addi a1,sp,8 -80005188: 00048513 mv a0,s1 -8000518c: ec1ff0ef jal ra,8000504c -80005190: 02410593 addi a1,sp,36 -80005194: 00040513 mv a0,s0 -80005198: eb5ff0ef jal ra,8000504c -8000519c: 00815583 lhu a1,8(sp) -800051a0: 02415503 lhu a0,36(sp) -800051a4: 04b50c63 beq a0,a1,800051fc -800051a8: 00a10793 addi a5,sp,10 -800051ac: 02610713 addi a4,sp,38 -800051b0: 02010613 addi a2,sp,32 -800051b4: 0007d683 lhu a3,0(a5) -800051b8: 00278793 addi a5,a5,2 -800051bc: 08069a63 bnez a3,80005250 -800051c0: 00075683 lhu a3,0(a4) -800051c4: 00270713 addi a4,a4,2 -800051c8: 08069463 bnez a3,80005250 -800051cc: fec794e3 bne a5,a2,800051b4 -800051d0: 00000513 li a0,0 -800051d4: 04c12083 lw ra,76(sp) -800051d8: 04812403 lw s0,72(sp) -800051dc: 04412483 lw s1,68(sp) -800051e0: 05010113 addi sp,sp,80 -800051e4: 00008067 ret -800051e8: 00040513 mv a0,s0 -800051ec: db1ff0ef jal ra,80004f9c -800051f0: f8050ae3 beqz a0,80005184 -800051f4: ffe00513 li a0,-2 -800051f8: fddff06f j 800051d4 -800051fc: 00153513 seqz a0,a0 -80005200: 00a15603 lhu a2,10(sp) -80005204: 02615683 lhu a3,38(sp) -80005208: 40a00533 neg a0,a0 -8000520c: 00a10713 addi a4,sp,10 -80005210: 02610793 addi a5,sp,38 -80005214: 00257513 andi a0,a0,2 -80005218: fff50513 addi a0,a0,-1 -8000521c: 03c10593 addi a1,sp,60 -80005220: 00278793 addi a5,a5,2 -80005224: 00270713 addi a4,a4,2 -80005228: 00d61e63 bne a2,a3,80005244 -8000522c: fab782e3 beq a5,a1,800051d0 -80005230: 00075603 lhu a2,0(a4) -80005234: 0007d683 lhu a3,0(a5) -80005238: 00270713 addi a4,a4,2 -8000523c: 00278793 addi a5,a5,2 -80005240: fed606e3 beq a2,a3,8000522c -80005244: f8c6e8e3 bltu a3,a2,800051d4 -80005248: 40a00533 neg a0,a0 -8000524c: f89ff06f j 800051d4 -80005250: 00100513 li a0,1 -80005254: f80580e3 beqz a1,800051d4 -80005258: fff00513 li a0,-1 -8000525c: f79ff06f j 800051d4 +80005080 : +80005080: 01255783 lhu a5,18(a0) +80005084: fb010113 addi sp,sp,-80 +80005088: 04812423 sw s0,72(sp) +8000508c: fff7c793 not a5,a5 +80005090: 04912223 sw s1,68(sp) +80005094: 04112623 sw ra,76(sp) +80005098: 01179713 slli a4,a5,0x11 +8000509c: 00050493 mv s1,a0 +800050a0: 00058413 mv s0,a1 +800050a4: 00071663 bnez a4,800050b0 +800050a8: e31ff0ef jal ra,80004ed8 +800050ac: 08051263 bnez a0,80005130 +800050b0: 01245783 lhu a5,18(s0) +800050b4: fff7c793 not a5,a5 +800050b8: 01179713 slli a4,a5,0x11 +800050bc: 06070463 beqz a4,80005124 +800050c0: 00810593 addi a1,sp,8 +800050c4: 00048513 mv a0,s1 +800050c8: ec1ff0ef jal ra,80004f88 +800050cc: 02410593 addi a1,sp,36 +800050d0: 00040513 mv a0,s0 +800050d4: eb5ff0ef jal ra,80004f88 +800050d8: 00815583 lhu a1,8(sp) +800050dc: 02415503 lhu a0,36(sp) +800050e0: 04b50c63 beq a0,a1,80005138 +800050e4: 00a10793 addi a5,sp,10 +800050e8: 02610713 addi a4,sp,38 +800050ec: 02010613 addi a2,sp,32 +800050f0: 0007d683 lhu a3,0(a5) +800050f4: 00278793 addi a5,a5,2 +800050f8: 08069a63 bnez a3,8000518c +800050fc: 00075683 lhu a3,0(a4) +80005100: 00270713 addi a4,a4,2 +80005104: 08069463 bnez a3,8000518c +80005108: fec794e3 bne a5,a2,800050f0 +8000510c: 00000513 li a0,0 +80005110: 04c12083 lw ra,76(sp) +80005114: 04812403 lw s0,72(sp) +80005118: 04412483 lw s1,68(sp) +8000511c: 05010113 addi sp,sp,80 +80005120: 00008067 ret +80005124: 00040513 mv a0,s0 +80005128: db1ff0ef jal ra,80004ed8 +8000512c: f8050ae3 beqz a0,800050c0 +80005130: ffe00513 li a0,-2 +80005134: fddff06f j 80005110 +80005138: 00153513 seqz a0,a0 +8000513c: 00a15603 lhu a2,10(sp) +80005140: 02615683 lhu a3,38(sp) +80005144: 40a00533 neg a0,a0 +80005148: 00a10713 addi a4,sp,10 +8000514c: 02610793 addi a5,sp,38 +80005150: 00257513 andi a0,a0,2 +80005154: fff50513 addi a0,a0,-1 +80005158: 03c10593 addi a1,sp,60 +8000515c: 00278793 addi a5,a5,2 +80005160: 00270713 addi a4,a4,2 +80005164: 00d61e63 bne a2,a3,80005180 +80005168: fab782e3 beq a5,a1,8000510c +8000516c: 00075603 lhu a2,0(a4) +80005170: 0007d683 lhu a3,0(a5) +80005174: 00270713 addi a4,a4,2 +80005178: 00278793 addi a5,a5,2 +8000517c: fed606e3 beq a2,a3,80005168 +80005180: f8c6e8e3 bltu a3,a2,80005110 +80005184: 40a00533 neg a0,a0 +80005188: f89ff06f j 80005110 +8000518c: 00100513 li a0,1 +80005190: f80580e3 beqz a1,80005110 +80005194: fff00513 li a0,-1 +80005198: f79ff06f j 80005110 -80005260 : -80005260: ff010113 addi sp,sp,-16 -80005264: 00112623 sw ra,12(sp) -80005268: d35ff0ef jal ra,80004f9c -8000526c: 00c12083 lw ra,12(sp) -80005270: 00153513 seqz a0,a0 -80005274: 01010113 addi sp,sp,16 -80005278: 00008067 ret +8000519c : +8000519c: ff010113 addi sp,sp,-16 +800051a0: 00112623 sw ra,12(sp) +800051a4: d35ff0ef jal ra,80004ed8 +800051a8: 00c12083 lw ra,12(sp) +800051ac: 00153513 seqz a0,a0 +800051b0: 01010113 addi sp,sp,16 +800051b4: 00008067 ret -8000527c : -8000527c: fe010113 addi sp,sp,-32 -80005280: 00812c23 sw s0,24(sp) -80005284: 00912a23 sw s1,20(sp) -80005288: 00112e23 sw ra,28(sp) -8000528c: 01212823 sw s2,16(sp) -80005290: 01312623 sw s3,12(sp) -80005294: 00058493 mv s1,a1 -80005298: 00050413 mv s0,a0 -8000529c: 0a05c463 bltz a1,80005344 -800052a0: 00f00793 li a5,15 -800052a4: 00058613 mv a2,a1 -800052a8: 00450513 addi a0,a0,4 -800052ac: 01840693 addi a3,s0,24 -800052b0: 00f00593 li a1,15 -800052b4: 0297d463 bge a5,s1,800052dc -800052b8: 00050793 mv a5,a0 -800052bc: 0027d703 lhu a4,2(a5) -800052c0: 00278793 addi a5,a5,2 -800052c4: fee79f23 sh a4,-2(a5) -800052c8: fed79ae3 bne a5,a3,800052bc -800052cc: 00041c23 sh zero,24(s0) -800052d0: ff060613 addi a2,a2,-16 -800052d4: fec5c2e3 blt a1,a2,800052b8 -800052d8: 00f4f493 andi s1,s1,15 +800051b8 : +800051b8: fe010113 addi sp,sp,-32 +800051bc: 00812c23 sw s0,24(sp) +800051c0: 00912a23 sw s1,20(sp) +800051c4: 00112e23 sw ra,28(sp) +800051c8: 01212823 sw s2,16(sp) +800051cc: 01312623 sw s3,12(sp) +800051d0: 00058493 mv s1,a1 +800051d4: 00050413 mv s0,a0 +800051d8: 0a05c463 bltz a1,80005280 +800051dc: 00f00793 li a5,15 +800051e0: 00058613 mv a2,a1 +800051e4: 00450513 addi a0,a0,4 +800051e8: 01840693 addi a3,s0,24 +800051ec: 00f00593 li a1,15 +800051f0: 0297d463 bge a5,s1,80005218 +800051f4: 00050793 mv a5,a0 +800051f8: 0027d703 lhu a4,2(a5) +800051fc: 00278793 addi a5,a5,2 +80005200: fee79f23 sh a4,-2(a5) +80005204: fed79ae3 bne a5,a3,800051f8 +80005208: 00041c23 sh zero,24(s0) +8000520c: ff060613 addi a2,a2,-16 +80005210: fec5c2e3 blt a1,a2,800051f4 +80005214: 00f4f493 andi s1,s1,15 +80005218: 00700793 li a5,7 +8000521c: 0297d863 bge a5,s1,8000524c +80005220: 01840713 addi a4,s0,24 +80005224: 00240593 addi a1,s0,2 +80005228: 00000793 li a5,0 +8000522c: 00075683 lhu a3,0(a4) +80005230: ffe70713 addi a4,a4,-2 +80005234: 00869613 slli a2,a3,0x8 +80005238: 00c7e7b3 or a5,a5,a2 +8000523c: 00f71123 sh a5,2(a4) +80005240: 0086d793 srli a5,a3,0x8 +80005244: feb714e3 bne a4,a1,8000522c +80005248: ff848493 addi s1,s1,-8 +8000524c: 00048a63 beqz s1,80005260 +80005250: fff48493 addi s1,s1,-1 +80005254: 00040513 mv a0,s0 +80005258: b79ff0ef jal ra,80004dd0 +8000525c: fe049ae3 bnez s1,80005250 +80005260: 00000513 li a0,0 +80005264: 01c12083 lw ra,28(sp) +80005268: 01812403 lw s0,24(sp) +8000526c: 01412483 lw s1,20(sp) +80005270: 01012903 lw s2,16(sp) +80005274: 00c12983 lw s3,12(sp) +80005278: 02010113 addi sp,sp,32 +8000527c: 00008067 ret +80005280: ff100793 li a5,-15 +80005284: 40b00933 neg s2,a1 +80005288: 12f5dc63 bge a1,a5,800053c0 +8000528c: 01850593 addi a1,a0,24 +80005290: 00000993 li s3,0 +80005294: 00450693 addi a3,a0,4 +80005298: 00f00613 li a2,15 +8000529c: 01845703 lhu a4,24(s0) +800052a0: 00058793 mv a5,a1 +800052a4: 00e9e9b3 or s3,s3,a4 +800052a8: ffe7d703 lhu a4,-2(a5) +800052ac: ffe78793 addi a5,a5,-2 +800052b0: 00e79123 sh a4,2(a5) +800052b4: fed79ae3 bne a5,a3,800052a8 +800052b8: 00041223 sh zero,4(s0) +800052bc: ff090913 addi s2,s2,-16 +800052c0: fd264ee3 blt a2,s2,8000529c +800052c4: ff000793 li a5,-16 +800052c8: ff100713 li a4,-15 +800052cc: 409787b3 sub a5,a5,s1 +800052d0: 00000913 li s2,0 +800052d4: 0ae4c463 blt s1,a4,8000537c +800052d8: 00f90933 add s2,s2,a5 800052dc: 00700793 li a5,7 -800052e0: 0297d863 bge a5,s1,80005310 -800052e4: 01840713 addi a4,s0,24 -800052e8: 00240593 addi a1,s0,2 -800052ec: 00000793 li a5,0 -800052f0: 00075683 lhu a3,0(a4) -800052f4: ffe70713 addi a4,a4,-2 -800052f8: 00869613 slli a2,a3,0x8 -800052fc: 00c7e7b3 or a5,a5,a2 -80005300: 00f71123 sh a5,2(a4) -80005304: 0086d793 srli a5,a3,0x8 -80005308: feb714e3 bne a4,a1,800052f0 -8000530c: ff848493 addi s1,s1,-8 -80005310: 00048a63 beqz s1,80005324 -80005314: fff48493 addi s1,s1,-1 -80005318: 00040513 mv a0,s0 -8000531c: b79ff0ef jal ra,80004e94 -80005320: fe049ae3 bnez s1,80005314 -80005324: 00000513 li a0,0 -80005328: 01c12083 lw ra,28(sp) -8000532c: 01812403 lw s0,24(sp) -80005330: 01412483 lw s1,20(sp) -80005334: 01012903 lw s2,16(sp) -80005338: 00c12983 lw s3,12(sp) -8000533c: 02010113 addi sp,sp,32 -80005340: 00008067 ret -80005344: ff100793 li a5,-15 -80005348: 40b00933 neg s2,a1 -8000534c: 12f5dc63 bge a1,a5,80005484 -80005350: 01850593 addi a1,a0,24 -80005354: 00000993 li s3,0 -80005358: 00450693 addi a3,a0,4 -8000535c: 00f00613 li a2,15 -80005360: 01845703 lhu a4,24(s0) -80005364: 00058793 mv a5,a1 -80005368: 00e9e9b3 or s3,s3,a4 -8000536c: ffe7d703 lhu a4,-2(a5) -80005370: ffe78793 addi a5,a5,-2 -80005374: 00e79123 sh a4,2(a5) -80005378: fed79ae3 bne a5,a3,8000536c -8000537c: 00041223 sh zero,4(s0) -80005380: ff090913 addi s2,s2,-16 -80005384: fd264ee3 blt a2,s2,80005360 -80005388: ff000793 li a5,-16 -8000538c: ff100713 li a4,-15 -80005390: 409787b3 sub a5,a5,s1 -80005394: 00000913 li s2,0 -80005398: 0ae4c463 blt s1,a4,80005440 -8000539c: 00f90933 add s2,s2,a5 -800053a0: 00700793 li a5,7 -800053a4: 0527d663 bge a5,s2,800053f0 -800053a8: 01099993 slli s3,s3,0x10 -800053ac: 4109d993 srai s3,s3,0x10 -800053b0: 01844783 lbu a5,24(s0) -800053b4: 01a40593 addi a1,s0,26 -800053b8: 00f9e9b3 or s3,s3,a5 -800053bc: 01099993 slli s3,s3,0x10 -800053c0: 0109d993 srli s3,s3,0x10 -800053c4: 00000793 li a5,0 -800053c8: 0006d603 lhu a2,0(a3) -800053cc: 00268693 addi a3,a3,2 -800053d0: 00865713 srli a4,a2,0x8 -800053d4: 00e7e733 or a4,a5,a4 -800053d8: 00861793 slli a5,a2,0x8 -800053dc: 01079793 slli a5,a5,0x10 -800053e0: fee69f23 sh a4,-2(a3) -800053e4: 0107d793 srli a5,a5,0x10 -800053e8: feb690e3 bne a3,a1,800053c8 -800053ec: ff890913 addi s2,s2,-8 -800053f0: 06090c63 beqz s2,80005468 -800053f4: 01845783 lhu a5,24(s0) -800053f8: fff90913 addi s2,s2,-1 -800053fc: 00040513 mv a0,s0 -80005400: 0017f793 andi a5,a5,1 -80005404: 0137e9b3 or s3,a5,s3 -80005408: a25ff0ef jal ra,80004e2c -8000540c: fe0914e3 bnez s2,800053f4 -80005410: 01099793 slli a5,s3,0x10 -80005414: 4107d793 srai a5,a5,0x10 -80005418: 04079063 bnez a5,80005458 -8000541c: 01099513 slli a0,s3,0x10 -80005420: 01055513 srli a0,a0,0x10 -80005424: 01c12083 lw ra,28(sp) -80005428: 01812403 lw s0,24(sp) -8000542c: 01412483 lw s1,20(sp) -80005430: 01012903 lw s2,16(sp) -80005434: 00c12983 lw s3,12(sp) -80005438: 02010113 addi sp,sp,32 -8000543c: 00008067 ret -80005440: ff07f913 andi s2,a5,-16 -80005444: 41200933 neg s2,s2 -80005448: 00f90933 add s2,s2,a5 -8000544c: 00700793 li a5,7 -80005450: fb27d0e3 bge a5,s2,800053f0 -80005454: f55ff06f j 800053a8 -80005458: 00100993 li s3,1 -8000545c: 01099513 slli a0,s3,0x10 -80005460: 01055513 srli a0,a0,0x10 -80005464: fc1ff06f j 80005424 -80005468: 00098513 mv a0,s3 -8000546c: 00099863 bnez s3,8000547c -80005470: 01051513 slli a0,a0,0x10 -80005474: 01055513 srli a0,a0,0x10 -80005478: eb1ff06f j 80005328 -8000547c: 00100513 li a0,1 -80005480: ff1ff06f j 80005470 -80005484: ff900793 li a5,-7 -80005488: 00000993 li s3,0 -8000548c: f6f5d4e3 bge a1,a5,800053f4 -80005490: 00440693 addi a3,s0,4 -80005494: f1dff06f j 800053b0 +800052e0: 0527d663 bge a5,s2,8000532c +800052e4: 01099993 slli s3,s3,0x10 +800052e8: 4109d993 srai s3,s3,0x10 +800052ec: 01844783 lbu a5,24(s0) +800052f0: 01a40593 addi a1,s0,26 +800052f4: 00f9e9b3 or s3,s3,a5 +800052f8: 01099993 slli s3,s3,0x10 +800052fc: 0109d993 srli s3,s3,0x10 +80005300: 00000793 li a5,0 +80005304: 0006d603 lhu a2,0(a3) +80005308: 00268693 addi a3,a3,2 +8000530c: 00865713 srli a4,a2,0x8 +80005310: 00e7e733 or a4,a5,a4 +80005314: 00861793 slli a5,a2,0x8 +80005318: 01079793 slli a5,a5,0x10 +8000531c: fee69f23 sh a4,-2(a3) +80005320: 0107d793 srli a5,a5,0x10 +80005324: feb690e3 bne a3,a1,80005304 +80005328: ff890913 addi s2,s2,-8 +8000532c: 06090c63 beqz s2,800053a4 +80005330: 01845783 lhu a5,24(s0) +80005334: fff90913 addi s2,s2,-1 +80005338: 00040513 mv a0,s0 +8000533c: 0017f793 andi a5,a5,1 +80005340: 0137e9b3 or s3,a5,s3 +80005344: a25ff0ef jal ra,80004d68 +80005348: fe0914e3 bnez s2,80005330 +8000534c: 01099793 slli a5,s3,0x10 +80005350: 4107d793 srai a5,a5,0x10 +80005354: 04079063 bnez a5,80005394 +80005358: 01099513 slli a0,s3,0x10 +8000535c: 01055513 srli a0,a0,0x10 +80005360: 01c12083 lw ra,28(sp) +80005364: 01812403 lw s0,24(sp) +80005368: 01412483 lw s1,20(sp) +8000536c: 01012903 lw s2,16(sp) +80005370: 00c12983 lw s3,12(sp) +80005374: 02010113 addi sp,sp,32 +80005378: 00008067 ret +8000537c: ff07f913 andi s2,a5,-16 +80005380: 41200933 neg s2,s2 +80005384: 00f90933 add s2,s2,a5 +80005388: 00700793 li a5,7 +8000538c: fb27d0e3 bge a5,s2,8000532c +80005390: f55ff06f j 800052e4 +80005394: 00100993 li s3,1 +80005398: 01099513 slli a0,s3,0x10 +8000539c: 01055513 srli a0,a0,0x10 +800053a0: fc1ff06f j 80005360 +800053a4: 00098513 mv a0,s3 +800053a8: 00099863 bnez s3,800053b8 +800053ac: 01051513 slli a0,a0,0x10 +800053b0: 01055513 srli a0,a0,0x10 +800053b4: eb1ff06f j 80005264 +800053b8: 00100513 li a0,1 +800053bc: ff1ff06f j 800053ac +800053c0: ff900793 li a5,-7 +800053c4: 00000993 li s3,0 +800053c8: f6f5d4e3 bge a1,a5,80005330 +800053cc: 00440693 addi a3,s0,4 +800053d0: f1dff06f j 800052ec -80005498 : -80005498: 00455783 lhu a5,4(a0) -8000549c: ff010113 addi sp,sp,-16 -800054a0: 00912223 sw s1,4(sp) -800054a4: 00112623 sw ra,12(sp) -800054a8: 00812423 sw s0,8(sp) -800054ac: 01212023 sw s2,0(sp) -800054b0: 00050493 mv s1,a0 -800054b4: 0c079c63 bnez a5,8000558c -800054b8: 00655703 lhu a4,6(a0) -800054bc: 00000413 li s0,0 -800054c0: 01071793 slli a5,a4,0x10 -800054c4: 4107d793 srai a5,a5,0x10 -800054c8: 0a07c463 bltz a5,80005570 -800054cc: 01a50693 addi a3,a0,26 -800054d0: 0a000613 li a2,160 -800054d4: 02071863 bnez a4,80005504 -800054d8: 00648793 addi a5,s1,6 -800054dc: 0080006f j 800054e4 -800054e0: 0007d703 lhu a4,0(a5) -800054e4: 00278793 addi a5,a5,2 -800054e8: fee79e23 sh a4,-4(a5) -800054ec: fef69ae3 bne a3,a5,800054e0 -800054f0: 00049c23 sh zero,24(s1) -800054f4: 01040413 addi s0,s0,16 -800054f8: 06c40c63 beq s0,a2,80005570 -800054fc: 0064d703 lhu a4,6(s1) -80005500: fc070ce3 beqz a4,800054d8 -80005504: f0077793 andi a5,a4,-256 -80005508: 04079063 bnez a5,80005548 -8000550c: 01848513 addi a0,s1,24 -80005510: 00248593 addi a1,s1,2 -80005514: 00000793 li a5,0 -80005518: 00050713 mv a4,a0 -8000551c: 00075683 lhu a3,0(a4) -80005520: ffe70713 addi a4,a4,-2 -80005524: 00869613 slli a2,a3,0x8 -80005528: 00c7e7b3 or a5,a5,a2 -8000552c: 00f71123 sh a5,2(a4) -80005530: 0086d793 srli a5,a3,0x8 -80005534: fee594e3 bne a1,a4,8000551c -80005538: 0064d703 lhu a4,6(s1) -8000553c: 00840413 addi s0,s0,8 -80005540: f0077793 andi a5,a4,-256 -80005544: fc0788e3 beqz a5,80005514 -80005548: 0a000913 li s2,160 -8000554c: 0140006f j 80005560 -80005550: 00140413 addi s0,s0,1 -80005554: 941ff0ef jal ra,80004e94 -80005558: 00894c63 blt s2,s0,80005570 -8000555c: 0064d703 lhu a4,6(s1) -80005560: 01071713 slli a4,a4,0x10 -80005564: 41075713 srai a4,a4,0x10 -80005568: 00048513 mv a0,s1 -8000556c: fe0752e3 bgez a4,80005550 -80005570: 00c12083 lw ra,12(sp) -80005574: 00040513 mv a0,s0 -80005578: 00812403 lw s0,8(sp) -8000557c: 00412483 lw s1,4(sp) -80005580: 00012903 lw s2,0(sp) -80005584: 01010113 addi sp,sp,16 -80005588: 00008067 ret -8000558c: f007f713 andi a4,a5,-256 -80005590: 00000413 li s0,0 -80005594: 04071063 bnez a4,800055d4 -80005598: f6f00913 li s2,-145 -8000559c: 0140006f j 800055b0 -800055a0: fff40413 addi s0,s0,-1 -800055a4: 889ff0ef jal ra,80004e2c -800055a8: fd2404e3 beq s0,s2,80005570 -800055ac: 0044d783 lhu a5,4(s1) -800055b0: 00048513 mv a0,s1 -800055b4: fe0796e3 bnez a5,800055a0 -800055b8: 00c12083 lw ra,12(sp) -800055bc: 00040513 mv a0,s0 -800055c0: 00812403 lw s0,8(sp) -800055c4: 00412483 lw s1,4(sp) -800055c8: 00012903 lw s2,0(sp) -800055cc: 01010113 addi sp,sp,16 -800055d0: 00008067 ret -800055d4: 00450693 addi a3,a0,4 -800055d8: 01a50593 addi a1,a0,26 -800055dc: 00000713 li a4,0 -800055e0: 0080006f j 800055e8 -800055e4: 0006d783 lhu a5,0(a3) -800055e8: 0087d613 srli a2,a5,0x8 -800055ec: 00c76733 or a4,a4,a2 -800055f0: 00879793 slli a5,a5,0x8 -800055f4: 00e69023 sh a4,0(a3) -800055f8: 01079713 slli a4,a5,0x10 -800055fc: 00268693 addi a3,a3,2 -80005600: 01075713 srli a4,a4,0x10 -80005604: feb690e3 bne a3,a1,800055e4 -80005608: 0044d783 lhu a5,4(s1) -8000560c: ff800413 li s0,-8 -80005610: f89ff06f j 80005598 +800053d4 : +800053d4: 00455783 lhu a5,4(a0) +800053d8: ff010113 addi sp,sp,-16 +800053dc: 00912223 sw s1,4(sp) +800053e0: 00112623 sw ra,12(sp) +800053e4: 00812423 sw s0,8(sp) +800053e8: 01212023 sw s2,0(sp) +800053ec: 00050493 mv s1,a0 +800053f0: 0c079c63 bnez a5,800054c8 +800053f4: 00655703 lhu a4,6(a0) +800053f8: 00000413 li s0,0 +800053fc: 01071793 slli a5,a4,0x10 +80005400: 4107d793 srai a5,a5,0x10 +80005404: 0a07c463 bltz a5,800054ac +80005408: 01a50693 addi a3,a0,26 +8000540c: 0a000613 li a2,160 +80005410: 02071863 bnez a4,80005440 +80005414: 00648793 addi a5,s1,6 +80005418: 0080006f j 80005420 +8000541c: 0007d703 lhu a4,0(a5) +80005420: 00278793 addi a5,a5,2 +80005424: fee79e23 sh a4,-4(a5) +80005428: fef69ae3 bne a3,a5,8000541c +8000542c: 00049c23 sh zero,24(s1) +80005430: 01040413 addi s0,s0,16 +80005434: 06c40c63 beq s0,a2,800054ac +80005438: 0064d703 lhu a4,6(s1) +8000543c: fc070ce3 beqz a4,80005414 +80005440: f0077793 andi a5,a4,-256 +80005444: 04079063 bnez a5,80005484 +80005448: 01848513 addi a0,s1,24 +8000544c: 00248593 addi a1,s1,2 +80005450: 00000793 li a5,0 +80005454: 00050713 mv a4,a0 +80005458: 00075683 lhu a3,0(a4) +8000545c: ffe70713 addi a4,a4,-2 +80005460: 00869613 slli a2,a3,0x8 +80005464: 00c7e7b3 or a5,a5,a2 +80005468: 00f71123 sh a5,2(a4) +8000546c: 0086d793 srli a5,a3,0x8 +80005470: fee594e3 bne a1,a4,80005458 +80005474: 0064d703 lhu a4,6(s1) +80005478: 00840413 addi s0,s0,8 +8000547c: f0077793 andi a5,a4,-256 +80005480: fc0788e3 beqz a5,80005450 +80005484: 0a000913 li s2,160 +80005488: 0140006f j 8000549c +8000548c: 00140413 addi s0,s0,1 +80005490: 941ff0ef jal ra,80004dd0 +80005494: 00894c63 blt s2,s0,800054ac +80005498: 0064d703 lhu a4,6(s1) +8000549c: 01071713 slli a4,a4,0x10 +800054a0: 41075713 srai a4,a4,0x10 +800054a4: 00048513 mv a0,s1 +800054a8: fe0752e3 bgez a4,8000548c +800054ac: 00c12083 lw ra,12(sp) +800054b0: 00040513 mv a0,s0 +800054b4: 00812403 lw s0,8(sp) +800054b8: 00412483 lw s1,4(sp) +800054bc: 00012903 lw s2,0(sp) +800054c0: 01010113 addi sp,sp,16 +800054c4: 00008067 ret +800054c8: f007f713 andi a4,a5,-256 +800054cc: 00000413 li s0,0 +800054d0: 04071063 bnez a4,80005510 +800054d4: f6f00913 li s2,-145 +800054d8: 0140006f j 800054ec +800054dc: fff40413 addi s0,s0,-1 +800054e0: 889ff0ef jal ra,80004d68 +800054e4: fd2404e3 beq s0,s2,800054ac +800054e8: 0044d783 lhu a5,4(s1) +800054ec: 00048513 mv a0,s1 +800054f0: fe0796e3 bnez a5,800054dc +800054f4: 00c12083 lw ra,12(sp) +800054f8: 00040513 mv a0,s0 +800054fc: 00812403 lw s0,8(sp) +80005500: 00412483 lw s1,4(sp) +80005504: 00012903 lw s2,0(sp) +80005508: 01010113 addi sp,sp,16 +8000550c: 00008067 ret +80005510: 00450693 addi a3,a0,4 +80005514: 01a50593 addi a1,a0,26 +80005518: 00000713 li a4,0 +8000551c: 0080006f j 80005524 +80005520: 0006d783 lhu a5,0(a3) +80005524: 0087d613 srli a2,a5,0x8 +80005528: 00c76733 or a4,a4,a2 +8000552c: 00879793 slli a5,a5,0x8 +80005530: 00e69023 sh a4,0(a3) +80005534: 01079713 slli a4,a5,0x10 +80005538: 00268693 addi a3,a3,2 +8000553c: 01075713 srli a4,a4,0x10 +80005540: feb690e3 bne a3,a1,80005520 +80005544: 0044d783 lhu a5,4(s1) +80005548: ff800413 li s0,-8 +8000554c: f89ff06f j 800054d4 -80005614 : -80005614: fe010113 addi sp,sp,-32 -80005618: 00812c23 sw s0,24(sp) -8000561c: 00912a23 sw s1,20(sp) -80005620: 01212823 sw s2,16(sp) -80005624: 01312623 sw s3,12(sp) -80005628: 01412423 sw s4,8(sp) -8000562c: 01512223 sw s5,4(sp) -80005630: 00068913 mv s2,a3 -80005634: 00078493 mv s1,a5 -80005638: 00112e23 sw ra,28(sp) -8000563c: 00050413 mv s0,a0 -80005640: 00058993 mv s3,a1 -80005644: 00060a13 mv s4,a2 -80005648: 00070a93 mv s5,a4 -8000564c: e4dff0ef jal ra,80005498 -80005650: 09000793 li a5,144 -80005654: 40a90933 sub s2,s2,a0 -80005658: 16a7dc63 bge a5,a0,800057d0 -8000565c: 000087b7 lui a5,0x8 -80005660: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -80005664: 1f27da63 bge a5,s2,80005858 -80005668: 1c0a8463 beqz s5,80005830 -8000566c: 0044a503 lw a0,4(s1) -80005670: 0004a783 lw a5,0(s1) -80005674: 06f50a63 beq a0,a5,800056e8 -80005678: 01a48713 addi a4,s1,26 -8000567c: 03448793 addi a5,s1,52 -80005680: 00270713 addi a4,a4,2 -80005684: fe071f23 sh zero,-2(a4) -80005688: fef71ce3 bne a4,a5,80005680 -8000568c: 03800793 li a5,56 -80005690: 32f50c63 beq a0,a5,800059c8 -80005694: 16a7d063 bge a5,a0,800057f4 -80005698: 04000793 li a5,64 -8000569c: 2ef50c63 beq a0,a5,80005994 -800056a0: 07100793 li a5,113 -800056a4: 34f51863 bne a0,a5,800059f4 -800056a8: 400087b7 lui a5,0x40008 -800056ac: fff78793 addi a5,a5,-1 # 40007fff <_start-0x3fff8001> -800056b0: 00a00713 li a4,10 -800056b4: 00f4aa23 sw a5,20(s1) -800056b8: ffff87b7 lui a5,0xffff8 -800056bc: 00e4a423 sw a4,8(s1) -800056c0: 00f49c23 sh a5,24(s1) -800056c4: 00e4a623 sw a4,12(s1) -800056c8: 00a00793 li a5,10 -800056cc: 00008737 lui a4,0x8 -800056d0: 00878793 addi a5,a5,8 # ffff8008 <__BSS_END__+0x7ffe13cc> -800056d4: 00179793 slli a5,a5,0x1 -800056d8: 00f487b3 add a5,s1,a5 -800056dc: 00e79523 sh a4,10(a5) -800056e0: 00a4a023 sw a0,0(s1) -800056e4: 1b205863 blez s2,80005894 -800056e8: 0084a583 lw a1,8(s1) -800056ec: 0144d783 lhu a5,20(s1) -800056f0: 08f00813 li a6,143 -800056f4: 00159613 slli a2,a1,0x1 -800056f8: 00c40633 add a2,s0,a2 -800056fc: 00065703 lhu a4,0(a2) -80005700: 00f776b3 and a3,a4,a5 -80005704: 02a84a63 blt a6,a0,80005738 -80005708: 00b00813 li a6,11 -8000570c: 02b84663 blt a6,a1,80005738 -80005710: 00060793 mv a5,a2 -80005714: 01840593 addi a1,s0,24 -80005718: 0027d703 lhu a4,2(a5) -8000571c: 00070463 beqz a4,80005724 -80005720: 0016e693 ori a3,a3,1 -80005724: 00079123 sh zero,2(a5) -80005728: 00278793 addi a5,a5,2 -8000572c: fef596e3 bne a1,a5,80005718 -80005730: 00065703 lhu a4,0(a2) -80005734: 0144d783 lhu a5,20(s1) -80005738: fff7c793 not a5,a5 -8000573c: 00e7f7b3 and a5,a5,a4 -80005740: 00f61023 sh a5,0(a2) -80005744: 0164d783 lhu a5,22(s1) -80005748: 00d7f733 and a4,a5,a3 -8000574c: 04070063 beqz a4,8000578c -80005750: 1ad78463 beq a5,a3,800058f8 -80005754: 03248613 addi a2,s1,50 -80005758: 01840693 addi a3,s0,24 -8000575c: 01c48493 addi s1,s1,28 -80005760: 00000713 li a4,0 -80005764: 00065783 lhu a5,0(a2) -80005768: 0006d583 lhu a1,0(a3) -8000576c: ffe68693 addi a3,a3,-2 -80005770: ffe60613 addi a2,a2,-2 -80005774: 00b787b3 add a5,a5,a1 -80005778: 00e787b3 add a5,a5,a4 -8000577c: 0107d713 srli a4,a5,0x10 -80005780: 00f69123 sh a5,2(a3) -80005784: 00177713 andi a4,a4,1 -80005788: fc961ee3 bne a2,s1,80005764 -8000578c: 19205863 blez s2,8000591c -80005790: 00445783 lhu a5,4(s0) -80005794: 12079e63 bnez a5,800058d0 -80005798: 000087b7 lui a5,0x8 -8000579c: 00041c23 sh zero,24(s0) -800057a0: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -800057a4: 0927c863 blt a5,s2,80005834 -800057a8: 01241123 sh s2,2(s0) -800057ac: 01c12083 lw ra,28(sp) -800057b0: 01812403 lw s0,24(sp) -800057b4: 01412483 lw s1,20(sp) -800057b8: 01012903 lw s2,16(sp) -800057bc: 00c12983 lw s3,12(sp) -800057c0: 00812a03 lw s4,8(sp) -800057c4: 00412a83 lw s5,4(sp) -800057c8: 02010113 addi sp,sp,32 -800057cc: 00008067 ret -800057d0: 0e095463 bgez s2,800058b8 -800057d4: f7000793 li a5,-144 -800057d8: 08f95c63 bge s2,a5,80005870 -800057dc: 00240793 addi a5,s0,2 -800057e0: 01a40413 addi s0,s0,26 -800057e4: 00278793 addi a5,a5,2 -800057e8: fe079f23 sh zero,-2(a5) -800057ec: fe879ce3 bne a5,s0,800057e4 -800057f0: fbdff06f j 800057ac -800057f4: 01800793 li a5,24 -800057f8: 16f50863 beq a0,a5,80005968 -800057fc: 03500793 li a5,53 -80005800: 1ef51a63 bne a0,a5,800059f4 -80005804: 00001737 lui a4,0x1 -80005808: 040007b7 lui a5,0x4000 -8000580c: 00600693 li a3,6 -80005810: 7ff78793 addi a5,a5,2047 # 40007ff <_start-0x7bfff801> -80005814: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> -80005818: 00f4aa23 sw a5,20(s1) -8000581c: 00d4a423 sw a3,8(s1) -80005820: 00e49c23 sh a4,24(s1) -80005824: 00d4a623 sw a3,12(s1) -80005828: 00600793 li a5,6 -8000582c: ea5ff06f j 800056d0 -80005830: 00041c23 sh zero,24(s0) -80005834: ffff87b7 lui a5,0xffff8 -80005838: fff7c793 not a5,a5 -8000583c: 00f41123 sh a5,2(s0) -80005840: 00440793 addi a5,s0,4 -80005844: 01840413 addi s0,s0,24 -80005848: 00079023 sh zero,0(a5) # ffff8000 <__BSS_END__+0x7ffe13c4> -8000584c: 00278793 addi a5,a5,2 -80005850: fef41ce3 bne s0,a5,80005848 -80005854: f59ff06f j 800057ac -80005858: 00240793 addi a5,s0,2 -8000585c: 01a40413 addi s0,s0,26 -80005860: 00278793 addi a5,a5,2 -80005864: fe079f23 sh zero,-2(a5) -80005868: fe879ce3 bne a5,s0,80005860 -8000586c: f41ff06f j 800057ac -80005870: 00090593 mv a1,s2 -80005874: 00040513 mv a0,s0 -80005878: a05ff0ef jal ra,8000527c -8000587c: 00050463 beqz a0,80005884 -80005880: 00100993 li s3,1 -80005884: 0c0a8c63 beqz s5,8000595c -80005888: 0044a503 lw a0,4(s1) -8000588c: 0004a783 lw a5,0(s1) -80005890: def514e3 bne a0,a5,80005678 -80005894: 09000793 li a5,144 -80005898: 0af50463 beq a0,a5,80005940 -8000589c: 01845783 lhu a5,24(s0) -800058a0: 00040513 mv a0,s0 -800058a4: 0017f793 andi a5,a5,1 -800058a8: 00f9e9b3 or s3,s3,a5 -800058ac: d80ff0ef jal ra,80004e2c -800058b0: 0044a503 lw a0,4(s1) -800058b4: e35ff06f j 800056e8 -800058b8: ee0a80e3 beqz s5,80005798 -800058bc: 0044a503 lw a0,4(s1) -800058c0: 0004a783 lw a5,0(s1) -800058c4: daf51ae3 bne a0,a5,80005678 -800058c8: e32040e3 bgtz s2,800056e8 -800058cc: fc9ff06f j 80005894 -800058d0: 00040513 mv a0,s0 -800058d4: d58ff0ef jal ra,80004e2c -800058d8: 000087b7 lui a5,0x8 -800058dc: 00190913 addi s2,s2,1 -800058e0: 00041c23 sh zero,24(s0) -800058e4: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> -800058e8: f527c6e3 blt a5,s2,80005834 -800058ec: ea095ee3 bgez s2,800057a8 -800058f0: 00041123 sh zero,2(s0) -800058f4: eb9ff06f j 800057ac -800058f8: 0c099463 bnez s3,800059c0 -800058fc: 00c4a783 lw a5,12(s1) -80005900: 0184d703 lhu a4,24(s1) -80005904: 00179793 slli a5,a5,0x1 -80005908: 00f407b3 add a5,s0,a5 -8000590c: 0007d783 lhu a5,0(a5) -80005910: 00e7f7b3 and a5,a5,a4 -80005914: e40790e3 bnez a5,80005754 -80005918: e7204ce3 bgtz s2,80005790 -8000591c: 09000793 li a5,144 -80005920: 00f50663 beq a0,a5,8000592c -80005924: 00040513 mv a0,s0 -80005928: d6cff0ef jal ra,80004e94 -8000592c: 00445783 lhu a5,4(s0) -80005930: fa0790e3 bnez a5,800058d0 -80005934: 00041c23 sh zero,24(s0) -80005938: fa094ce3 bltz s2,800058f0 -8000593c: e6dff06f j 800057a8 -80005940: 0084a603 lw a2,8(s1) -80005944: 0144d783 lhu a5,20(s1) -80005948: 00161613 slli a2,a2,0x1 -8000594c: 00c40633 add a2,s0,a2 -80005950: 00065703 lhu a4,0(a2) -80005954: 00e7f6b3 and a3,a5,a4 -80005958: de1ff06f j 80005738 -8000595c: 00041c23 sh zero,24(s0) -80005960: 00041123 sh zero,2(s0) -80005964: e49ff06f j 800057ac -80005968: 008007b7 lui a5,0x800 -8000596c: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> -80005970: 00400713 li a4,4 -80005974: 00f4aa23 sw a5,20(s1) -80005978: 10000793 li a5,256 -8000597c: 00e4a423 sw a4,8(s1) -80005980: 00f49c23 sh a5,24(s1) -80005984: 00e4a623 sw a4,12(s1) -80005988: 00400793 li a5,4 -8000598c: 10000713 li a4,256 -80005990: d41ff06f j 800056d0 -80005994: 00700793 li a5,7 -80005998: 00f4a423 sw a5,8(s1) -8000599c: 800107b7 lui a5,0x80010 -800059a0: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff93c3> -800059a4: 00f4aa23 sw a5,20(s1) -800059a8: 00100793 li a5,1 -800059ac: 00f49c23 sh a5,24(s1) -800059b0: 00600793 li a5,6 -800059b4: 00f4a623 sw a5,12(s1) -800059b8: 00100713 li a4,1 -800059bc: d15ff06f j 800056d0 -800059c0: d80a0ae3 beqz s4,80005754 -800059c4: dc9ff06f j 8000578c -800059c8: 008007b7 lui a5,0x800 -800059cc: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> -800059d0: 00600713 li a4,6 -800059d4: 00f4aa23 sw a5,20(s1) -800059d8: 10000793 li a5,256 -800059dc: 00e4a423 sw a4,8(s1) -800059e0: 00f49c23 sh a5,24(s1) -800059e4: 00e4a623 sw a4,12(s1) -800059e8: 00600793 li a5,6 -800059ec: 10000713 li a4,256 -800059f0: ce1ff06f j 800056d0 -800059f4: 00c00793 li a5,12 -800059f8: 00f4a423 sw a5,8(s1) -800059fc: 800107b7 lui a5,0x80010 -80005a00: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff93c3> -80005a04: 00f4aa23 sw a5,20(s1) -80005a08: 00100793 li a5,1 -80005a0c: 00f49c23 sh a5,24(s1) -80005a10: 00b00793 li a5,11 -80005a14: 00f4a623 sw a5,12(s1) -80005a18: 00100713 li a4,1 -80005a1c: cb5ff06f j 800056d0 +80005550 : +80005550: fe010113 addi sp,sp,-32 +80005554: 00812c23 sw s0,24(sp) +80005558: 00912a23 sw s1,20(sp) +8000555c: 01212823 sw s2,16(sp) +80005560: 01312623 sw s3,12(sp) +80005564: 01412423 sw s4,8(sp) +80005568: 01512223 sw s5,4(sp) +8000556c: 00068913 mv s2,a3 +80005570: 00078493 mv s1,a5 +80005574: 00112e23 sw ra,28(sp) +80005578: 00050413 mv s0,a0 +8000557c: 00058993 mv s3,a1 +80005580: 00060a13 mv s4,a2 +80005584: 00070a93 mv s5,a4 +80005588: e4dff0ef jal ra,800053d4 +8000558c: 09000793 li a5,144 +80005590: 40a90933 sub s2,s2,a0 +80005594: 16a7dc63 bge a5,a0,8000570c +80005598: 000087b7 lui a5,0x8 +8000559c: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> +800055a0: 1f27da63 bge a5,s2,80005794 +800055a4: 1c0a8463 beqz s5,8000576c +800055a8: 0044a503 lw a0,4(s1) +800055ac: 0004a783 lw a5,0(s1) +800055b0: 06f50a63 beq a0,a5,80005624 +800055b4: 01a48713 addi a4,s1,26 +800055b8: 03448793 addi a5,s1,52 +800055bc: 00270713 addi a4,a4,2 +800055c0: fe071f23 sh zero,-2(a4) +800055c4: fef71ce3 bne a4,a5,800055bc +800055c8: 03800793 li a5,56 +800055cc: 32f50c63 beq a0,a5,80005904 +800055d0: 16a7d063 bge a5,a0,80005730 +800055d4: 04000793 li a5,64 +800055d8: 2ef50c63 beq a0,a5,800058d0 +800055dc: 07100793 li a5,113 +800055e0: 34f51863 bne a0,a5,80005930 +800055e4: 400087b7 lui a5,0x40008 +800055e8: fff78793 addi a5,a5,-1 # 40007fff <_start-0x3fff8001> +800055ec: 00a00713 li a4,10 +800055f0: 00f4aa23 sw a5,20(s1) +800055f4: ffff87b7 lui a5,0xffff8 +800055f8: 00e4a423 sw a4,8(s1) +800055fc: 00f49c23 sh a5,24(s1) +80005600: 00e4a623 sw a4,12(s1) +80005604: 00a00793 li a5,10 +80005608: 00008737 lui a4,0x8 +8000560c: 00878793 addi a5,a5,8 # ffff8008 <__BSS_END__+0x7ffe13cc> +80005610: 00179793 slli a5,a5,0x1 +80005614: 00f487b3 add a5,s1,a5 +80005618: 00e79523 sh a4,10(a5) +8000561c: 00a4a023 sw a0,0(s1) +80005620: 1b205863 blez s2,800057d0 +80005624: 0084a583 lw a1,8(s1) +80005628: 0144d783 lhu a5,20(s1) +8000562c: 08f00813 li a6,143 +80005630: 00159613 slli a2,a1,0x1 +80005634: 00c40633 add a2,s0,a2 +80005638: 00065703 lhu a4,0(a2) +8000563c: 00f776b3 and a3,a4,a5 +80005640: 02a84a63 blt a6,a0,80005674 +80005644: 00b00813 li a6,11 +80005648: 02b84663 blt a6,a1,80005674 +8000564c: 00060793 mv a5,a2 +80005650: 01840593 addi a1,s0,24 +80005654: 0027d703 lhu a4,2(a5) +80005658: 00070463 beqz a4,80005660 +8000565c: 0016e693 ori a3,a3,1 +80005660: 00079123 sh zero,2(a5) +80005664: 00278793 addi a5,a5,2 +80005668: fef596e3 bne a1,a5,80005654 +8000566c: 00065703 lhu a4,0(a2) +80005670: 0144d783 lhu a5,20(s1) +80005674: fff7c793 not a5,a5 +80005678: 00e7f7b3 and a5,a5,a4 +8000567c: 00f61023 sh a5,0(a2) +80005680: 0164d783 lhu a5,22(s1) +80005684: 00d7f733 and a4,a5,a3 +80005688: 04070063 beqz a4,800056c8 +8000568c: 1ad78463 beq a5,a3,80005834 +80005690: 03248613 addi a2,s1,50 +80005694: 01840693 addi a3,s0,24 +80005698: 01c48493 addi s1,s1,28 +8000569c: 00000713 li a4,0 +800056a0: 00065783 lhu a5,0(a2) +800056a4: 0006d583 lhu a1,0(a3) +800056a8: ffe68693 addi a3,a3,-2 +800056ac: ffe60613 addi a2,a2,-2 +800056b0: 00b787b3 add a5,a5,a1 +800056b4: 00e787b3 add a5,a5,a4 +800056b8: 0107d713 srli a4,a5,0x10 +800056bc: 00f69123 sh a5,2(a3) +800056c0: 00177713 andi a4,a4,1 +800056c4: fc961ee3 bne a2,s1,800056a0 +800056c8: 19205863 blez s2,80005858 +800056cc: 00445783 lhu a5,4(s0) +800056d0: 12079e63 bnez a5,8000580c +800056d4: 000087b7 lui a5,0x8 +800056d8: 00041c23 sh zero,24(s0) +800056dc: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> +800056e0: 0927c863 blt a5,s2,80005770 +800056e4: 01241123 sh s2,2(s0) +800056e8: 01c12083 lw ra,28(sp) +800056ec: 01812403 lw s0,24(sp) +800056f0: 01412483 lw s1,20(sp) +800056f4: 01012903 lw s2,16(sp) +800056f8: 00c12983 lw s3,12(sp) +800056fc: 00812a03 lw s4,8(sp) +80005700: 00412a83 lw s5,4(sp) +80005704: 02010113 addi sp,sp,32 +80005708: 00008067 ret +8000570c: 0e095463 bgez s2,800057f4 +80005710: f7000793 li a5,-144 +80005714: 08f95c63 bge s2,a5,800057ac +80005718: 00240793 addi a5,s0,2 +8000571c: 01a40413 addi s0,s0,26 +80005720: 00278793 addi a5,a5,2 +80005724: fe079f23 sh zero,-2(a5) +80005728: fe879ce3 bne a5,s0,80005720 +8000572c: fbdff06f j 800056e8 +80005730: 01800793 li a5,24 +80005734: 16f50863 beq a0,a5,800058a4 +80005738: 03500793 li a5,53 +8000573c: 1ef51a63 bne a0,a5,80005930 +80005740: 00001737 lui a4,0x1 +80005744: 040007b7 lui a5,0x4000 +80005748: 00600693 li a3,6 +8000574c: 7ff78793 addi a5,a5,2047 # 40007ff <_start-0x7bfff801> +80005750: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> +80005754: 00f4aa23 sw a5,20(s1) +80005758: 00d4a423 sw a3,8(s1) +8000575c: 00e49c23 sh a4,24(s1) +80005760: 00d4a623 sw a3,12(s1) +80005764: 00600793 li a5,6 +80005768: ea5ff06f j 8000560c +8000576c: 00041c23 sh zero,24(s0) +80005770: ffff87b7 lui a5,0xffff8 +80005774: fff7c793 not a5,a5 +80005778: 00f41123 sh a5,2(s0) +8000577c: 00440793 addi a5,s0,4 +80005780: 01840413 addi s0,s0,24 +80005784: 00079023 sh zero,0(a5) # ffff8000 <__BSS_END__+0x7ffe13c4> +80005788: 00278793 addi a5,a5,2 +8000578c: fef41ce3 bne s0,a5,80005784 +80005790: f59ff06f j 800056e8 +80005794: 00240793 addi a5,s0,2 +80005798: 01a40413 addi s0,s0,26 +8000579c: 00278793 addi a5,a5,2 +800057a0: fe079f23 sh zero,-2(a5) +800057a4: fe879ce3 bne a5,s0,8000579c +800057a8: f41ff06f j 800056e8 +800057ac: 00090593 mv a1,s2 +800057b0: 00040513 mv a0,s0 +800057b4: a05ff0ef jal ra,800051b8 +800057b8: 00050463 beqz a0,800057c0 +800057bc: 00100993 li s3,1 +800057c0: 0c0a8c63 beqz s5,80005898 +800057c4: 0044a503 lw a0,4(s1) +800057c8: 0004a783 lw a5,0(s1) +800057cc: def514e3 bne a0,a5,800055b4 +800057d0: 09000793 li a5,144 +800057d4: 0af50463 beq a0,a5,8000587c +800057d8: 01845783 lhu a5,24(s0) +800057dc: 00040513 mv a0,s0 +800057e0: 0017f793 andi a5,a5,1 +800057e4: 00f9e9b3 or s3,s3,a5 +800057e8: d80ff0ef jal ra,80004d68 +800057ec: 0044a503 lw a0,4(s1) +800057f0: e35ff06f j 80005624 +800057f4: ee0a80e3 beqz s5,800056d4 +800057f8: 0044a503 lw a0,4(s1) +800057fc: 0004a783 lw a5,0(s1) +80005800: daf51ae3 bne a0,a5,800055b4 +80005804: e32040e3 bgtz s2,80005624 +80005808: fc9ff06f j 800057d0 +8000580c: 00040513 mv a0,s0 +80005810: d58ff0ef jal ra,80004d68 +80005814: 000087b7 lui a5,0x8 +80005818: 00190913 addi s2,s2,1 +8000581c: 00041c23 sh zero,24(s0) +80005820: ffe78793 addi a5,a5,-2 # 7ffe <_start-0x7fff8002> +80005824: f527c6e3 blt a5,s2,80005770 +80005828: ea095ee3 bgez s2,800056e4 +8000582c: 00041123 sh zero,2(s0) +80005830: eb9ff06f j 800056e8 +80005834: 0c099463 bnez s3,800058fc +80005838: 00c4a783 lw a5,12(s1) +8000583c: 0184d703 lhu a4,24(s1) +80005840: 00179793 slli a5,a5,0x1 +80005844: 00f407b3 add a5,s0,a5 +80005848: 0007d783 lhu a5,0(a5) +8000584c: 00e7f7b3 and a5,a5,a4 +80005850: e40790e3 bnez a5,80005690 +80005854: e7204ce3 bgtz s2,800056cc +80005858: 09000793 li a5,144 +8000585c: 00f50663 beq a0,a5,80005868 +80005860: 00040513 mv a0,s0 +80005864: d6cff0ef jal ra,80004dd0 +80005868: 00445783 lhu a5,4(s0) +8000586c: fa0790e3 bnez a5,8000580c +80005870: 00041c23 sh zero,24(s0) +80005874: fa094ce3 bltz s2,8000582c +80005878: e6dff06f j 800056e4 +8000587c: 0084a603 lw a2,8(s1) +80005880: 0144d783 lhu a5,20(s1) +80005884: 00161613 slli a2,a2,0x1 +80005888: 00c40633 add a2,s0,a2 +8000588c: 00065703 lhu a4,0(a2) +80005890: 00e7f6b3 and a3,a5,a4 +80005894: de1ff06f j 80005674 +80005898: 00041c23 sh zero,24(s0) +8000589c: 00041123 sh zero,2(s0) +800058a0: e49ff06f j 800056e8 +800058a4: 008007b7 lui a5,0x800 +800058a8: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> +800058ac: 00400713 li a4,4 +800058b0: 00f4aa23 sw a5,20(s1) +800058b4: 10000793 li a5,256 +800058b8: 00e4a423 sw a4,8(s1) +800058bc: 00f49c23 sh a5,24(s1) +800058c0: 00e4a623 sw a4,12(s1) +800058c4: 00400793 li a5,4 +800058c8: 10000713 li a4,256 +800058cc: d41ff06f j 8000560c +800058d0: 00700793 li a5,7 +800058d4: 00f4a423 sw a5,8(s1) +800058d8: 800107b7 lui a5,0x80010 +800058dc: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff93c3> +800058e0: 00f4aa23 sw a5,20(s1) +800058e4: 00100793 li a5,1 +800058e8: 00f49c23 sh a5,24(s1) +800058ec: 00600793 li a5,6 +800058f0: 00f4a623 sw a5,12(s1) +800058f4: 00100713 li a4,1 +800058f8: d15ff06f j 8000560c +800058fc: d80a0ae3 beqz s4,80005690 +80005900: dc9ff06f j 800056c8 +80005904: 008007b7 lui a5,0x800 +80005908: 0ff78793 addi a5,a5,255 # 8000ff <_start-0x7f7fff01> +8000590c: 00600713 li a4,6 +80005910: 00f4aa23 sw a5,20(s1) +80005914: 10000793 li a5,256 +80005918: 00e4a423 sw a4,8(s1) +8000591c: 00f49c23 sh a5,24(s1) +80005920: 00e4a623 sw a4,12(s1) +80005924: 00600793 li a5,6 +80005928: 10000713 li a4,256 +8000592c: ce1ff06f j 8000560c +80005930: 00c00793 li a5,12 +80005934: 00f4a423 sw a5,8(s1) +80005938: 800107b7 lui a5,0x80010 +8000593c: fff78793 addi a5,a5,-1 # 8000ffff <__BSS_END__+0xffff93c3> +80005940: 00f4aa23 sw a5,20(s1) +80005944: 00100793 li a5,1 +80005948: 00f49c23 sh a5,24(s1) +8000594c: 00b00793 li a5,11 +80005950: 00f4a623 sw a5,12(s1) +80005954: 00100713 li a4,1 +80005958: cb5ff06f j 8000560c -80005a20 : -80005a20: fd010113 addi sp,sp,-48 -80005a24: 02912223 sw s1,36(sp) -80005a28: 01312e23 sw s3,28(sp) -80005a2c: 00058493 mv s1,a1 -80005a30: 00255983 lhu s3,2(a0) -80005a34: 02112623 sw ra,44(sp) -80005a38: 02812423 sw s0,40(sp) -80005a3c: 03212023 sw s2,32(sp) -80005a40: 01412c23 sw s4,24(sp) -80005a44: 00060913 mv s2,a2 -80005a48: 01512a23 sw s5,20(sp) -80005a4c: 01612823 sw s6,16(sp) -80005a50: 01712623 sw s7,12(sp) -80005a54: 01812423 sw s8,8(sp) -80005a58: 01912223 sw s9,4(sp) -80005a5c: 01a12023 sw s10,0(sp) -80005a60: 00050a13 mv s4,a0 -80005a64: a35ff0ef jal ra,80005498 -80005a68: 0024d403 lhu s0,2(s1) -80005a6c: 00050793 mv a5,a0 -80005a70: 00048513 mv a0,s1 -80005a74: 40f989b3 sub s3,s3,a5 -80005a78: 03490a93 addi s5,s2,52 -80005a7c: a1dff0ef jal ra,80005498 -80005a80: 40a40433 sub s0,s0,a0 -80005a84: 04e90713 addi a4,s2,78 -80005a88: 000a8793 mv a5,s5 -80005a8c: 00278793 addi a5,a5,2 -80005a90: fe079f23 sh zero,-2(a5) -80005a94: fee79ce3 bne a5,a4,80005a8c -80005a98: 09344a63 blt s0,s3,80005b2c -80005a9c: 004a0b93 addi s7,s4,4 -80005aa0: 00448b13 addi s6,s1,4 -80005aa4: fff98993 addi s3,s3,-1 -80005aa8: 01aa0c93 addi s9,s4,26 -80005aac: 00248c13 addi s8,s1,2 -80005ab0: 000b0713 mv a4,s6 -80005ab4: 000b8793 mv a5,s7 -80005ab8: 0007d603 lhu a2,0(a5) -80005abc: 00075683 lhu a3,0(a4) -80005ac0: 00278793 addi a5,a5,2 -80005ac4: 00270713 addi a4,a4,2 -80005ac8: 0ad61a63 bne a2,a3,80005b7c -80005acc: ff9796e3 bne a5,s9,80005ab8 -80005ad0: 018a0613 addi a2,s4,24 -80005ad4: 01848713 addi a4,s1,24 -80005ad8: 00000693 li a3,0 -80005adc: 00075783 lhu a5,0(a4) -80005ae0: 00065583 lhu a1,0(a2) -80005ae4: ffe70713 addi a4,a4,-2 -80005ae8: 40d787b3 sub a5,a5,a3 -80005aec: 40b787b3 sub a5,a5,a1 -80005af0: 0107d693 srli a3,a5,0x10 -80005af4: 00f71123 sh a5,2(a4) -80005af8: 0016f693 andi a3,a3,1 -80005afc: ffe60613 addi a2,a2,-2 -80005b00: fcec1ee3 bne s8,a4,80005adc -80005b04: 00100d13 li s10,1 -80005b08: 000a8513 mv a0,s5 -80005b0c: b88ff0ef jal ra,80004e94 -80005b10: 04c95783 lhu a5,76(s2) -80005b14: fff40413 addi s0,s0,-1 -80005b18: 00048513 mv a0,s1 -80005b1c: 00fd6d33 or s10,s10,a5 -80005b20: 05a91623 sh s10,76(s2) -80005b24: b70ff0ef jal ra,80004e94 -80005b28: f93414e3 bne s0,s3,80005ab0 -80005b2c: 00040693 mv a3,s0 -80005b30: 02812403 lw s0,40(sp) -80005b34: 02c12083 lw ra,44(sp) -80005b38: 01c12983 lw s3,28(sp) -80005b3c: 01812a03 lw s4,24(sp) -80005b40: 01412a83 lw s5,20(sp) -80005b44: 01012b03 lw s6,16(sp) -80005b48: 00c12b83 lw s7,12(sp) -80005b4c: 00812c03 lw s8,8(sp) -80005b50: 00412c83 lw s9,4(sp) -80005b54: 00012d03 lw s10,0(sp) -80005b58: 00090793 mv a5,s2 -80005b5c: 00048513 mv a0,s1 -80005b60: 02012903 lw s2,32(sp) -80005b64: 02412483 lw s1,36(sp) -80005b68: 00000713 li a4,0 -80005b6c: 00000613 li a2,0 -80005b70: 00000593 li a1,0 -80005b74: 03010113 addi sp,sp,48 -80005b78: a9dff06f j 80005614 -80005b7c: 00000d13 li s10,0 -80005b80: f8c6e4e3 bltu a3,a2,80005b08 -80005b84: f4dff06f j 80005ad0 +8000595c : +8000595c: fd010113 addi sp,sp,-48 +80005960: 02912223 sw s1,36(sp) +80005964: 01312e23 sw s3,28(sp) +80005968: 00058493 mv s1,a1 +8000596c: 00255983 lhu s3,2(a0) +80005970: 02112623 sw ra,44(sp) +80005974: 02812423 sw s0,40(sp) +80005978: 03212023 sw s2,32(sp) +8000597c: 01412c23 sw s4,24(sp) +80005980: 00060913 mv s2,a2 +80005984: 01512a23 sw s5,20(sp) +80005988: 01612823 sw s6,16(sp) +8000598c: 01712623 sw s7,12(sp) +80005990: 01812423 sw s8,8(sp) +80005994: 01912223 sw s9,4(sp) +80005998: 01a12023 sw s10,0(sp) +8000599c: 00050a13 mv s4,a0 +800059a0: a35ff0ef jal ra,800053d4 +800059a4: 0024d403 lhu s0,2(s1) +800059a8: 00050793 mv a5,a0 +800059ac: 00048513 mv a0,s1 +800059b0: 40f989b3 sub s3,s3,a5 +800059b4: 03490a93 addi s5,s2,52 +800059b8: a1dff0ef jal ra,800053d4 +800059bc: 40a40433 sub s0,s0,a0 +800059c0: 04e90713 addi a4,s2,78 +800059c4: 000a8793 mv a5,s5 +800059c8: 00278793 addi a5,a5,2 +800059cc: fe079f23 sh zero,-2(a5) +800059d0: fee79ce3 bne a5,a4,800059c8 +800059d4: 09344a63 blt s0,s3,80005a68 +800059d8: 004a0b93 addi s7,s4,4 +800059dc: 00448b13 addi s6,s1,4 +800059e0: fff98993 addi s3,s3,-1 +800059e4: 01aa0c93 addi s9,s4,26 +800059e8: 00248c13 addi s8,s1,2 +800059ec: 000b0713 mv a4,s6 +800059f0: 000b8793 mv a5,s7 +800059f4: 0007d603 lhu a2,0(a5) +800059f8: 00075683 lhu a3,0(a4) +800059fc: 00278793 addi a5,a5,2 +80005a00: 00270713 addi a4,a4,2 +80005a04: 0ad61a63 bne a2,a3,80005ab8 +80005a08: ff9796e3 bne a5,s9,800059f4 +80005a0c: 018a0613 addi a2,s4,24 +80005a10: 01848713 addi a4,s1,24 +80005a14: 00000693 li a3,0 +80005a18: 00075783 lhu a5,0(a4) +80005a1c: 00065583 lhu a1,0(a2) +80005a20: ffe70713 addi a4,a4,-2 +80005a24: 40d787b3 sub a5,a5,a3 +80005a28: 40b787b3 sub a5,a5,a1 +80005a2c: 0107d693 srli a3,a5,0x10 +80005a30: 00f71123 sh a5,2(a4) +80005a34: 0016f693 andi a3,a3,1 +80005a38: ffe60613 addi a2,a2,-2 +80005a3c: fcec1ee3 bne s8,a4,80005a18 +80005a40: 00100d13 li s10,1 +80005a44: 000a8513 mv a0,s5 +80005a48: b88ff0ef jal ra,80004dd0 +80005a4c: 04c95783 lhu a5,76(s2) +80005a50: fff40413 addi s0,s0,-1 +80005a54: 00048513 mv a0,s1 +80005a58: 00fd6d33 or s10,s10,a5 +80005a5c: 05a91623 sh s10,76(s2) +80005a60: b70ff0ef jal ra,80004dd0 +80005a64: f93414e3 bne s0,s3,800059ec +80005a68: 00040693 mv a3,s0 +80005a6c: 02812403 lw s0,40(sp) +80005a70: 02c12083 lw ra,44(sp) +80005a74: 01c12983 lw s3,28(sp) +80005a78: 01812a03 lw s4,24(sp) +80005a7c: 01412a83 lw s5,20(sp) +80005a80: 01012b03 lw s6,16(sp) +80005a84: 00c12b83 lw s7,12(sp) +80005a88: 00812c03 lw s8,8(sp) +80005a8c: 00412c83 lw s9,4(sp) +80005a90: 00012d03 lw s10,0(sp) +80005a94: 00090793 mv a5,s2 +80005a98: 00048513 mv a0,s1 +80005a9c: 02012903 lw s2,32(sp) +80005aa0: 02412483 lw s1,36(sp) +80005aa4: 00000713 li a4,0 +80005aa8: 00000613 li a2,0 +80005aac: 00000593 li a1,0 +80005ab0: 03010113 addi sp,sp,48 +80005ab4: a9dff06f j 80005550 +80005ab8: 00000d13 li s10,0 +80005abc: f8c6e4e3 bltu a3,a2,80005a44 +80005ac0: f4dff06f j 80005a0c -80005b88 : -80005b88: 00055703 lhu a4,0(a0) -80005b8c: 00255783 lhu a5,2(a0) -80005b90: 00070663 beqz a4,80005b9c -80005b94: 00008737 lui a4,0x8 -80005b98: 00e7e7b3 or a5,a5,a4 -80005b9c: 00f59923 sh a5,18(a1) -80005ba0: 00255703 lhu a4,2(a0) -80005ba4: 000087b7 lui a5,0x8 -80005ba8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005bac: 02f70463 beq a4,a5,80005bd4 -80005bb0: 00650793 addi a5,a0,6 -80005bb4: 01058593 addi a1,a1,16 -80005bb8: 01850513 addi a0,a0,24 -80005bbc: 0007d703 lhu a4,0(a5) -80005bc0: 00278793 addi a5,a5,2 -80005bc4: ffe58593 addi a1,a1,-2 -80005bc8: 00e59123 sh a4,2(a1) -80005bcc: fea798e3 bne a5,a0,80005bbc -80005bd0: 00008067 ret -80005bd4: 00650793 addi a5,a0,6 -80005bd8: 01a50513 addi a0,a0,26 -80005bdc: 0007d703 lhu a4,0(a5) -80005be0: 00278793 addi a5,a5,2 -80005be4: 02071a63 bnez a4,80005c18 -80005be8: fea79ae3 bne a5,a0,80005bdc -80005bec: 01258713 addi a4,a1,18 -80005bf0: 00058793 mv a5,a1 -80005bf4: 00278793 addi a5,a5,2 -80005bf8: fe079f23 sh zero,-2(a5) -80005bfc: fef71ce3 bne a4,a5,80005bf4 -80005c00: 0125d783 lhu a5,18(a1) -80005c04: 00008737 lui a4,0x8 -80005c08: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80005c0c: 00e7e7b3 or a5,a5,a4 -80005c10: 00f59923 sh a5,18(a1) -80005c14: 00008067 ret -80005c18: 01058713 addi a4,a1,16 -80005c1c: 00058793 mv a5,a1 -80005c20: 00278793 addi a5,a5,2 -80005c24: fe079f23 sh zero,-2(a5) -80005c28: fef71ce3 bne a4,a5,80005c20 -80005c2c: 7fffc7b7 lui a5,0x7fffc -80005c30: 00f5a823 sw a5,16(a1) -80005c34: 00008067 ret +80005ac4 : +80005ac4: 00055703 lhu a4,0(a0) +80005ac8: 00255783 lhu a5,2(a0) +80005acc: 00070663 beqz a4,80005ad8 +80005ad0: 00008737 lui a4,0x8 +80005ad4: 00e7e7b3 or a5,a5,a4 +80005ad8: 00f59923 sh a5,18(a1) +80005adc: 00255703 lhu a4,2(a0) +80005ae0: 000087b7 lui a5,0x8 +80005ae4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80005ae8: 02f70463 beq a4,a5,80005b10 +80005aec: 00650793 addi a5,a0,6 +80005af0: 01058593 addi a1,a1,16 +80005af4: 01850513 addi a0,a0,24 +80005af8: 0007d703 lhu a4,0(a5) +80005afc: 00278793 addi a5,a5,2 +80005b00: ffe58593 addi a1,a1,-2 +80005b04: 00e59123 sh a4,2(a1) +80005b08: fea798e3 bne a5,a0,80005af8 +80005b0c: 00008067 ret +80005b10: 00650793 addi a5,a0,6 +80005b14: 01a50513 addi a0,a0,26 +80005b18: 0007d703 lhu a4,0(a5) +80005b1c: 00278793 addi a5,a5,2 +80005b20: 02071a63 bnez a4,80005b54 +80005b24: fea79ae3 bne a5,a0,80005b18 +80005b28: 01258713 addi a4,a1,18 +80005b2c: 00058793 mv a5,a1 +80005b30: 00278793 addi a5,a5,2 +80005b34: fe079f23 sh zero,-2(a5) +80005b38: fef71ce3 bne a4,a5,80005b30 +80005b3c: 0125d783 lhu a5,18(a1) +80005b40: 00008737 lui a4,0x8 +80005b44: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80005b48: 00e7e7b3 or a5,a5,a4 +80005b4c: 00f59923 sh a5,18(a1) +80005b50: 00008067 ret +80005b54: 01058713 addi a4,a1,16 +80005b58: 00058793 mv a5,a1 +80005b5c: 00278793 addi a5,a5,2 +80005b60: fe079f23 sh zero,-2(a5) +80005b64: fef71ce3 bne a4,a5,80005b5c +80005b68: 7fffc7b7 lui a5,0x7fffc +80005b6c: 00f5a823 sw a5,16(a1) +80005b70: 00008067 ret -80005c38 : -80005c38: f7010113 addi sp,sp,-144 -80005c3c: 07612823 sw s6,112(sp) -80005c40: 01255b03 lhu s6,18(a0) -80005c44: 000087b7 lui a5,0x8 -80005c48: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005c4c: 07412c23 sw s4,120(sp) -80005c50: 0167fa33 and s4,a5,s6 -80005c54: 010a1a13 slli s4,s4,0x10 -80005c58: 08812423 sw s0,136(sp) -80005c5c: 08912223 sw s1,132(sp) -80005c60: 09212023 sw s2,128(sp) -80005c64: 07312e23 sw s3,124(sp) -80005c68: 08112623 sw ra,140(sp) -80005c6c: 07512a23 sw s5,116(sp) -80005c70: 07712623 sw s7,108(sp) -80005c74: 07812423 sw s8,104(sp) -80005c78: 07912223 sw s9,100(sp) -80005c7c: 010a5a13 srli s4,s4,0x10 -80005c80: 00050493 mv s1,a0 -80005c84: 00058913 mv s2,a1 -80005c88: 00060413 mv s0,a2 -80005c8c: 00068993 mv s3,a3 -80005c90: 10fa1263 bne s4,a5,80005d94 -80005c94: b08ff0ef jal ra,80004f9c -80005c98: 28051a63 bnez a0,80005f2c -80005c9c: 01295a83 lhu s5,18(s2) -80005ca0: 015a77b3 and a5,s4,s5 -80005ca4: 2b478263 beq a5,s4,80005f48 -80005ca8: 00048513 mv a0,s1 -80005cac: db4ff0ef jal ra,80005260 -80005cb0: 2e050e63 beqz a0,80005fac -80005cb4: 800155b7 lui a1,0x80015 -80005cb8: e6058593 addi a1,a1,-416 # 80014e60 <__BSS_END__+0xffffe224> -80005cbc: 00090513 mv a0,s2 -80005cc0: c84ff0ef jal ra,80005144 -80005cc4: 36050663 beqz a0,80006030 -80005cc8: 01295a83 lhu s5,18(s2) -80005ccc: 000087b7 lui a5,0x8 -80005cd0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005cd4: 0157fab3 and s5,a5,s5 -80005cd8: 010a9a93 slli s5,s5,0x10 -80005cdc: 010ada93 srli s5,s5,0x10 -80005ce0: 2cfa9463 bne s5,a5,80005fa8 -80005ce4: 00090513 mv a0,s2 -80005ce8: d78ff0ef jal ra,80005260 -80005cec: 32051063 bnez a0,8000600c -80005cf0: 0124d783 lhu a5,18(s1) -80005cf4: 00faf7b3 and a5,s5,a5 -80005cf8: 0b579863 bne a5,s5,80005da8 -80005cfc: 00048513 mv a0,s1 -80005d00: d60ff0ef jal ra,80005260 -80005d04: 00051863 bnez a0,80005d14 -80005d08: 00090513 mv a0,s2 -80005d0c: d54ff0ef jal ra,80005260 -80005d10: 08050c63 beqz a0,80005da8 -80005d14: 00048513 mv a0,s1 -80005d18: af4ff0ef jal ra,8000500c -80005d1c: 00050493 mv s1,a0 -80005d20: 00090513 mv a0,s2 -80005d24: ae8ff0ef jal ra,8000500c -80005d28: 40a484b3 sub s1,s1,a0 -80005d2c: 009034b3 snez s1,s1 -80005d30: 00f49493 slli s1,s1,0xf -80005d34: 00941923 sh s1,18(s0) -80005d38: 01240713 addi a4,s0,18 -80005d3c: 00040793 mv a5,s0 -80005d40: 00278793 addi a5,a5,2 -80005d44: fe079f23 sh zero,-2(a5) -80005d48: fef71ce3 bne a4,a5,80005d40 -80005d4c: 01245783 lhu a5,18(s0) -80005d50: 00008737 lui a4,0x8 -80005d54: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80005d58: 00e7e7b3 or a5,a5,a4 -80005d5c: 00f41923 sh a5,18(s0) -80005d60: 08c12083 lw ra,140(sp) -80005d64: 08812403 lw s0,136(sp) -80005d68: 08412483 lw s1,132(sp) -80005d6c: 08012903 lw s2,128(sp) -80005d70: 07c12983 lw s3,124(sp) -80005d74: 07812a03 lw s4,120(sp) -80005d78: 07412a83 lw s5,116(sp) -80005d7c: 07012b03 lw s6,112(sp) -80005d80: 06c12b83 lw s7,108(sp) -80005d84: 06812c03 lw s8,104(sp) -80005d88: 06412c83 lw s9,100(sp) -80005d8c: 09010113 addi sp,sp,144 -80005d90: 00008067 ret -80005d94: 0125da83 lhu s5,18(a1) -80005d98: 0157f733 and a4,a5,s5 -80005d9c: 01071713 slli a4,a4,0x10 -80005da0: 01075713 srli a4,a4,0x10 -80005da4: 04f70a63 beq a4,a5,80005df8 -80005da8: 00048513 mv a0,s1 -80005dac: 00c10593 addi a1,sp,12 -80005db0: a9cff0ef jal ra,8000504c -80005db4: 00090513 mv a0,s2 -80005db8: 02810593 addi a1,sp,40 -80005dbc: a90ff0ef jal ra,8000504c -80005dc0: 00e15483 lhu s1,14(sp) -80005dc4: 02a15903 lhu s2,42(sp) -80005dc8: 04049c63 bnez s1,80005e20 -80005dcc: 01010793 addi a5,sp,16 -80005dd0: 02410693 addi a3,sp,36 -80005dd4: 20d78863 beq a5,a3,80005fe4 -80005dd8: 0007d703 lhu a4,0(a5) -80005ddc: 00278793 addi a5,a5,2 -80005de0: fe070ae3 beqz a4,80005dd4 -80005de4: 00c10513 addi a0,sp,12 -80005de8: eb0ff0ef jal ra,80005498 -80005dec: 02a15703 lhu a4,42(sp) -80005df0: 40a004b3 neg s1,a0 -80005df4: 0300006f j 80005e24 -80005df8: 00058513 mv a0,a1 -80005dfc: 9a0ff0ef jal ra,80004f9c -80005e00: ec0506e3 beqz a0,80005ccc -80005e04: 01490713 addi a4,s2,20 -80005e08: 00095783 lhu a5,0(s2) -80005e0c: 00290913 addi s2,s2,2 -80005e10: 00240413 addi s0,s0,2 -80005e14: fef41f23 sh a5,-2(s0) -80005e18: fee918e3 bne s2,a4,80005e08 -80005e1c: f45ff06f j 80005d60 -80005e20: 00090713 mv a4,s2 -80005e24: 00090a93 mv s5,s2 -80005e28: 02c10793 addi a5,sp,44 -80005e2c: 04010693 addi a3,sp,64 -80005e30: 02071263 bnez a4,80005e54 -80005e34: 1cf68263 beq a3,a5,80005ff8 -80005e38: 0007d703 lhu a4,0(a5) -80005e3c: 00278793 addi a5,a5,2 -80005e40: fe070ae3 beqz a4,80005e34 -80005e44: 02810513 addi a0,sp,40 -80005e48: e50ff0ef jal ra,80005498 -80005e4c: 02a15703 lhu a4,42(sp) -80005e50: 40a90ab3 sub s5,s2,a0 -80005e54: 02815783 lhu a5,40(sp) -80005e58: 03898c13 addi s8,s3,56 -80005e5c: 02e99b23 sh a4,54(s3) -80005e60: 02f99a23 sh a5,52(s3) -80005e64: 04e98713 addi a4,s3,78 -80005e68: 000c0793 mv a5,s8 -80005e6c: 00079023 sh zero,0(a5) -80005e70: 00278793 addi a5,a5,2 -80005e74: fef71ce3 bne a4,a5,80005e6c -80005e78: 04c98a13 addi s4,s3,76 -80005e7c: 00000b93 li s7,0 -80005e80: 02410913 addi s2,sp,36 -80005e84: 01010c93 addi s9,sp,16 -80005e88: 04610b13 addi s6,sp,70 -80005e8c: 00095503 lhu a0,0(s2) -80005e90: ffe90913 addi s2,s2,-2 -80005e94: 0c051863 bnez a0,80005f64 -80005e98: 04c9d703 lhu a4,76(s3) -80005e9c: 000a0793 mv a5,s4 -80005ea0: 00ebebb3 or s7,s7,a4 -80005ea4: ffe7d703 lhu a4,-2(a5) -80005ea8: ffe78793 addi a5,a5,-2 -80005eac: 00e79123 sh a4,2(a5) -80005eb0: ff879ae3 bne a5,s8,80005ea4 -80005eb4: 02099c23 sh zero,56(s3) -80005eb8: fd991ae3 bne s2,s9,80005e8c -80005ebc: 03498713 addi a4,s3,52 -80005ec0: 02810793 addi a5,sp,40 -80005ec4: 04210593 addi a1,sp,66 -80005ec8: 00075603 lhu a2,0(a4) -80005ecc: 00278793 addi a5,a5,2 -80005ed0: 00270713 addi a4,a4,2 -80005ed4: fec79f23 sh a2,-2(a5) -80005ed8: fef598e3 bne a1,a5,80005ec8 -80005edc: ffffc6b7 lui a3,0xffffc -80005ee0: 015484b3 add s1,s1,s5 -80005ee4: 00268693 addi a3,a3,2 # ffffc002 <__BSS_END__+0x7ffe53c6> -80005ee8: 000b8593 mv a1,s7 -80005eec: 02810513 addi a0,sp,40 -80005ef0: 00098793 mv a5,s3 -80005ef4: 04000713 li a4,64 -80005ef8: 00d486b3 add a3,s1,a3 -80005efc: 00000613 li a2,0 -80005f00: f14ff0ef jal ra,80005614 -80005f04: 02815703 lhu a4,40(sp) -80005f08: 00c15783 lhu a5,12(sp) -80005f0c: 00040593 mv a1,s0 -80005f10: 02810513 addi a0,sp,40 -80005f14: 40e787b3 sub a5,a5,a4 -80005f18: 00f037b3 snez a5,a5 -80005f1c: 40f007b3 neg a5,a5 -80005f20: 02f11423 sh a5,40(sp) -80005f24: c65ff0ef jal ra,80005b88 -80005f28: e39ff06f j 80005d60 -80005f2c: 01448713 addi a4,s1,20 -80005f30: 0004d783 lhu a5,0(s1) -80005f34: 00248493 addi s1,s1,2 +80005b74 : +80005b74: f7010113 addi sp,sp,-144 +80005b78: 07612823 sw s6,112(sp) +80005b7c: 01255b03 lhu s6,18(a0) +80005b80: 000087b7 lui a5,0x8 +80005b84: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80005b88: 07412c23 sw s4,120(sp) +80005b8c: 0167fa33 and s4,a5,s6 +80005b90: 010a1a13 slli s4,s4,0x10 +80005b94: 08812423 sw s0,136(sp) +80005b98: 08912223 sw s1,132(sp) +80005b9c: 09212023 sw s2,128(sp) +80005ba0: 07312e23 sw s3,124(sp) +80005ba4: 08112623 sw ra,140(sp) +80005ba8: 07512a23 sw s5,116(sp) +80005bac: 07712623 sw s7,108(sp) +80005bb0: 07812423 sw s8,104(sp) +80005bb4: 07912223 sw s9,100(sp) +80005bb8: 010a5a13 srli s4,s4,0x10 +80005bbc: 00050493 mv s1,a0 +80005bc0: 00058913 mv s2,a1 +80005bc4: 00060413 mv s0,a2 +80005bc8: 00068993 mv s3,a3 +80005bcc: 10fa1263 bne s4,a5,80005cd0 +80005bd0: b08ff0ef jal ra,80004ed8 +80005bd4: 28051a63 bnez a0,80005e68 +80005bd8: 01295a83 lhu s5,18(s2) +80005bdc: 015a77b3 and a5,s4,s5 +80005be0: 2b478263 beq a5,s4,80005e84 +80005be4: 00048513 mv a0,s1 +80005be8: db4ff0ef jal ra,8000519c +80005bec: 2e050e63 beqz a0,80005ee8 +80005bf0: 800155b7 lui a1,0x80015 +80005bf4: d8c58593 addi a1,a1,-628 # 80014d8c <__BSS_END__+0xffffe150> +80005bf8: 00090513 mv a0,s2 +80005bfc: c84ff0ef jal ra,80005080 +80005c00: 36050663 beqz a0,80005f6c +80005c04: 01295a83 lhu s5,18(s2) +80005c08: 000087b7 lui a5,0x8 +80005c0c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80005c10: 0157fab3 and s5,a5,s5 +80005c14: 010a9a93 slli s5,s5,0x10 +80005c18: 010ada93 srli s5,s5,0x10 +80005c1c: 2cfa9463 bne s5,a5,80005ee4 +80005c20: 00090513 mv a0,s2 +80005c24: d78ff0ef jal ra,8000519c +80005c28: 32051063 bnez a0,80005f48 +80005c2c: 0124d783 lhu a5,18(s1) +80005c30: 00faf7b3 and a5,s5,a5 +80005c34: 0b579863 bne a5,s5,80005ce4 +80005c38: 00048513 mv a0,s1 +80005c3c: d60ff0ef jal ra,8000519c +80005c40: 00051863 bnez a0,80005c50 +80005c44: 00090513 mv a0,s2 +80005c48: d54ff0ef jal ra,8000519c +80005c4c: 08050c63 beqz a0,80005ce4 +80005c50: 00048513 mv a0,s1 +80005c54: af4ff0ef jal ra,80004f48 +80005c58: 00050493 mv s1,a0 +80005c5c: 00090513 mv a0,s2 +80005c60: ae8ff0ef jal ra,80004f48 +80005c64: 40a484b3 sub s1,s1,a0 +80005c68: 009034b3 snez s1,s1 +80005c6c: 00f49493 slli s1,s1,0xf +80005c70: 00941923 sh s1,18(s0) +80005c74: 01240713 addi a4,s0,18 +80005c78: 00040793 mv a5,s0 +80005c7c: 00278793 addi a5,a5,2 +80005c80: fe079f23 sh zero,-2(a5) +80005c84: fef71ce3 bne a4,a5,80005c7c +80005c88: 01245783 lhu a5,18(s0) +80005c8c: 00008737 lui a4,0x8 +80005c90: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80005c94: 00e7e7b3 or a5,a5,a4 +80005c98: 00f41923 sh a5,18(s0) +80005c9c: 08c12083 lw ra,140(sp) +80005ca0: 08812403 lw s0,136(sp) +80005ca4: 08412483 lw s1,132(sp) +80005ca8: 08012903 lw s2,128(sp) +80005cac: 07c12983 lw s3,124(sp) +80005cb0: 07812a03 lw s4,120(sp) +80005cb4: 07412a83 lw s5,116(sp) +80005cb8: 07012b03 lw s6,112(sp) +80005cbc: 06c12b83 lw s7,108(sp) +80005cc0: 06812c03 lw s8,104(sp) +80005cc4: 06412c83 lw s9,100(sp) +80005cc8: 09010113 addi sp,sp,144 +80005ccc: 00008067 ret +80005cd0: 0125da83 lhu s5,18(a1) +80005cd4: 0157f733 and a4,a5,s5 +80005cd8: 01071713 slli a4,a4,0x10 +80005cdc: 01075713 srli a4,a4,0x10 +80005ce0: 04f70a63 beq a4,a5,80005d34 +80005ce4: 00048513 mv a0,s1 +80005ce8: 00c10593 addi a1,sp,12 +80005cec: a9cff0ef jal ra,80004f88 +80005cf0: 00090513 mv a0,s2 +80005cf4: 02810593 addi a1,sp,40 +80005cf8: a90ff0ef jal ra,80004f88 +80005cfc: 00e15483 lhu s1,14(sp) +80005d00: 02a15903 lhu s2,42(sp) +80005d04: 04049c63 bnez s1,80005d5c +80005d08: 01010793 addi a5,sp,16 +80005d0c: 02410693 addi a3,sp,36 +80005d10: 20d78863 beq a5,a3,80005f20 +80005d14: 0007d703 lhu a4,0(a5) +80005d18: 00278793 addi a5,a5,2 +80005d1c: fe070ae3 beqz a4,80005d10 +80005d20: 00c10513 addi a0,sp,12 +80005d24: eb0ff0ef jal ra,800053d4 +80005d28: 02a15703 lhu a4,42(sp) +80005d2c: 40a004b3 neg s1,a0 +80005d30: 0300006f j 80005d60 +80005d34: 00058513 mv a0,a1 +80005d38: 9a0ff0ef jal ra,80004ed8 +80005d3c: ec0506e3 beqz a0,80005c08 +80005d40: 01490713 addi a4,s2,20 +80005d44: 00095783 lhu a5,0(s2) +80005d48: 00290913 addi s2,s2,2 +80005d4c: 00240413 addi s0,s0,2 +80005d50: fef41f23 sh a5,-2(s0) +80005d54: fee918e3 bne s2,a4,80005d44 +80005d58: f45ff06f j 80005c9c +80005d5c: 00090713 mv a4,s2 +80005d60: 00090a93 mv s5,s2 +80005d64: 02c10793 addi a5,sp,44 +80005d68: 04010693 addi a3,sp,64 +80005d6c: 02071263 bnez a4,80005d90 +80005d70: 1cf68263 beq a3,a5,80005f34 +80005d74: 0007d703 lhu a4,0(a5) +80005d78: 00278793 addi a5,a5,2 +80005d7c: fe070ae3 beqz a4,80005d70 +80005d80: 02810513 addi a0,sp,40 +80005d84: e50ff0ef jal ra,800053d4 +80005d88: 02a15703 lhu a4,42(sp) +80005d8c: 40a90ab3 sub s5,s2,a0 +80005d90: 02815783 lhu a5,40(sp) +80005d94: 03898c13 addi s8,s3,56 +80005d98: 02e99b23 sh a4,54(s3) +80005d9c: 02f99a23 sh a5,52(s3) +80005da0: 04e98713 addi a4,s3,78 +80005da4: 000c0793 mv a5,s8 +80005da8: 00079023 sh zero,0(a5) +80005dac: 00278793 addi a5,a5,2 +80005db0: fef71ce3 bne a4,a5,80005da8 +80005db4: 04c98a13 addi s4,s3,76 +80005db8: 00000b93 li s7,0 +80005dbc: 02410913 addi s2,sp,36 +80005dc0: 01010c93 addi s9,sp,16 +80005dc4: 04610b13 addi s6,sp,70 +80005dc8: 00095503 lhu a0,0(s2) +80005dcc: ffe90913 addi s2,s2,-2 +80005dd0: 0c051863 bnez a0,80005ea0 +80005dd4: 04c9d703 lhu a4,76(s3) +80005dd8: 000a0793 mv a5,s4 +80005ddc: 00ebebb3 or s7,s7,a4 +80005de0: ffe7d703 lhu a4,-2(a5) +80005de4: ffe78793 addi a5,a5,-2 +80005de8: 00e79123 sh a4,2(a5) +80005dec: ff879ae3 bne a5,s8,80005de0 +80005df0: 02099c23 sh zero,56(s3) +80005df4: fd991ae3 bne s2,s9,80005dc8 +80005df8: 03498713 addi a4,s3,52 +80005dfc: 02810793 addi a5,sp,40 +80005e00: 04210593 addi a1,sp,66 +80005e04: 00075603 lhu a2,0(a4) +80005e08: 00278793 addi a5,a5,2 +80005e0c: 00270713 addi a4,a4,2 +80005e10: fec79f23 sh a2,-2(a5) +80005e14: fef598e3 bne a1,a5,80005e04 +80005e18: ffffc6b7 lui a3,0xffffc +80005e1c: 015484b3 add s1,s1,s5 +80005e20: 00268693 addi a3,a3,2 # ffffc002 <__BSS_END__+0x7ffe53c6> +80005e24: 000b8593 mv a1,s7 +80005e28: 02810513 addi a0,sp,40 +80005e2c: 00098793 mv a5,s3 +80005e30: 04000713 li a4,64 +80005e34: 00d486b3 add a3,s1,a3 +80005e38: 00000613 li a2,0 +80005e3c: f14ff0ef jal ra,80005550 +80005e40: 02815703 lhu a4,40(sp) +80005e44: 00c15783 lhu a5,12(sp) +80005e48: 00040593 mv a1,s0 +80005e4c: 02810513 addi a0,sp,40 +80005e50: 40e787b3 sub a5,a5,a4 +80005e54: 00f037b3 snez a5,a5 +80005e58: 40f007b3 neg a5,a5 +80005e5c: 02f11423 sh a5,40(sp) +80005e60: c65ff0ef jal ra,80005ac4 +80005e64: e39ff06f j 80005c9c +80005e68: 01448713 addi a4,s1,20 +80005e6c: 0004d783 lhu a5,0(s1) +80005e70: 00248493 addi s1,s1,2 +80005e74: 00240413 addi s0,s0,2 +80005e78: fef41f23 sh a5,-2(s0) +80005e7c: fee498e3 bne s1,a4,80005e6c +80005e80: e1dff06f j 80005c9c +80005e84: 00090513 mv a0,s2 +80005e88: 850ff0ef jal ra,80004ed8 +80005e8c: ea051ae3 bnez a0,80005d40 +80005e90: 00048513 mv a0,s1 +80005e94: b08ff0ef jal ra,8000519c +80005e98: d60508e3 beqz a0,80005c08 +80005e9c: d55ff06f j 80005bf0 +80005ea0: 04410613 addi a2,sp,68 +80005ea4: 02810593 addi a1,sp,40 +80005ea8: f99fe0ef jal ra,80004e40 +80005eac: 000a0593 mv a1,s4 +80005eb0: 00000613 li a2,0 +80005eb4: 05c10713 addi a4,sp,92 +80005eb8: 0005d803 lhu a6,0(a1) +80005ebc: 00075783 lhu a5,0(a4) +80005ec0: ffe58593 addi a1,a1,-2 +80005ec4: ffe70713 addi a4,a4,-2 +80005ec8: 010787b3 add a5,a5,a6 +80005ecc: 00c787b3 add a5,a5,a2 +80005ed0: 0107d613 srli a2,a5,0x10 +80005ed4: 00f59123 sh a5,2(a1) +80005ed8: 00167613 andi a2,a2,1 +80005edc: fd671ee3 bne a4,s6,80005eb8 +80005ee0: ef5ff06f j 80005dd4 +80005ee4: 0124db03 lhu s6,18(s1) +80005ee8: 000087b7 lui a5,0x8 +80005eec: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80005ef0: 0167fb33 and s6,a5,s6 +80005ef4: 010b1b13 slli s6,s6,0x10 +80005ef8: 010b5b13 srli s6,s6,0x10 +80005efc: defb14e3 bne s6,a5,80005ce4 +80005f00: 00048513 mv a0,s1 +80005f04: a98ff0ef jal ra,8000519c +80005f08: d40514e3 bnez a0,80005c50 +80005f0c: 01295783 lhu a5,18(s2) +80005f10: fff7c793 not a5,a5 +80005f14: 01179713 slli a4,a5,0x11 +80005f18: dc0716e3 bnez a4,80005ce4 +80005f1c: d29ff06f j 80005c44 +80005f20: 01440793 addi a5,s0,20 +80005f24: 00240413 addi s0,s0,2 +80005f28: fe041f23 sh zero,-2(s0) +80005f2c: fe879ce3 bne a5,s0,80005f24 +80005f30: d6dff06f j 80005c9c +80005f34: 01440793 addi a5,s0,20 80005f38: 00240413 addi s0,s0,2 -80005f3c: fef41f23 sh a5,-2(s0) -80005f40: fee498e3 bne s1,a4,80005f30 -80005f44: e1dff06f j 80005d60 -80005f48: 00090513 mv a0,s2 -80005f4c: 850ff0ef jal ra,80004f9c -80005f50: ea051ae3 bnez a0,80005e04 -80005f54: 00048513 mv a0,s1 -80005f58: b08ff0ef jal ra,80005260 -80005f5c: d60508e3 beqz a0,80005ccc -80005f60: d55ff06f j 80005cb4 -80005f64: 04410613 addi a2,sp,68 -80005f68: 02810593 addi a1,sp,40 -80005f6c: f99fe0ef jal ra,80004f04 -80005f70: 000a0593 mv a1,s4 -80005f74: 00000613 li a2,0 -80005f78: 05c10713 addi a4,sp,92 -80005f7c: 0005d803 lhu a6,0(a1) -80005f80: 00075783 lhu a5,0(a4) -80005f84: ffe58593 addi a1,a1,-2 -80005f88: ffe70713 addi a4,a4,-2 -80005f8c: 010787b3 add a5,a5,a6 -80005f90: 00c787b3 add a5,a5,a2 -80005f94: 0107d613 srli a2,a5,0x10 -80005f98: 00f59123 sh a5,2(a1) -80005f9c: 00167613 andi a2,a2,1 -80005fa0: fd671ee3 bne a4,s6,80005f7c -80005fa4: ef5ff06f j 80005e98 -80005fa8: 0124db03 lhu s6,18(s1) -80005fac: 000087b7 lui a5,0x8 -80005fb0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80005fb4: 0167fb33 and s6,a5,s6 -80005fb8: 010b1b13 slli s6,s6,0x10 -80005fbc: 010b5b13 srli s6,s6,0x10 -80005fc0: defb14e3 bne s6,a5,80005da8 -80005fc4: 00048513 mv a0,s1 -80005fc8: a98ff0ef jal ra,80005260 -80005fcc: d40514e3 bnez a0,80005d14 -80005fd0: 01295783 lhu a5,18(s2) -80005fd4: fff7c793 not a5,a5 -80005fd8: 01179713 slli a4,a5,0x11 -80005fdc: dc0716e3 bnez a4,80005da8 -80005fe0: d29ff06f j 80005d08 -80005fe4: 01440793 addi a5,s0,20 -80005fe8: 00240413 addi s0,s0,2 -80005fec: fe041f23 sh zero,-2(s0) -80005ff0: fe879ce3 bne a5,s0,80005fe8 -80005ff4: d6dff06f j 80005d60 -80005ff8: 01440793 addi a5,s0,20 -80005ffc: 00240413 addi s0,s0,2 -80006000: fe041f23 sh zero,-2(s0) -80006004: fef41ce3 bne s0,a5,80005ffc -80006008: d59ff06f j 80005d60 -8000600c: 800155b7 lui a1,0x80015 -80006010: e6058593 addi a1,a1,-416 # 80014e60 <__BSS_END__+0xffffe224> -80006014: 00048513 mv a0,s1 -80006018: 92cff0ef jal ra,80005144 -8000601c: 00050a63 beqz a0,80006030 -80006020: 0124d783 lhu a5,18(s1) -80006024: 00faf7b3 and a5,s5,a5 -80006028: f9578ee3 beq a5,s5,80005fc4 -8000602c: fa5ff06f j 80005fd0 -80006030: 01040713 addi a4,s0,16 -80006034: 00040793 mv a5,s0 -80006038: 00278793 addi a5,a5,2 -8000603c: fe079f23 sh zero,-2(a5) -80006040: fee79ce3 bne a5,a4,80006038 -80006044: 7fffc7b7 lui a5,0x7fffc -80006048: 00f42823 sw a5,16(s0) -8000604c: d15ff06f j 80005d60 +80005f3c: fe041f23 sh zero,-2(s0) +80005f40: fef41ce3 bne s0,a5,80005f38 +80005f44: d59ff06f j 80005c9c +80005f48: 800155b7 lui a1,0x80015 +80005f4c: d8c58593 addi a1,a1,-628 # 80014d8c <__BSS_END__+0xffffe150> +80005f50: 00048513 mv a0,s1 +80005f54: 92cff0ef jal ra,80005080 +80005f58: 00050a63 beqz a0,80005f6c +80005f5c: 0124d783 lhu a5,18(s1) +80005f60: 00faf7b3 and a5,s5,a5 +80005f64: f9578ee3 beq a5,s5,80005f00 +80005f68: fa5ff06f j 80005f0c +80005f6c: 01040713 addi a4,s0,16 +80005f70: 00040793 mv a5,s0 +80005f74: 00278793 addi a5,a5,2 +80005f78: fe079f23 sh zero,-2(a5) +80005f7c: fee79ce3 bne a5,a4,80005f74 +80005f80: 7fffc7b7 lui a5,0x7fffc +80005f84: 00f42823 sw a5,16(s0) +80005f88: d15ff06f j 80005c9c -80006050 : -80006050: 01255783 lhu a5,18(a0) -80006054: f5010113 addi sp,sp,-176 -80006058: 0a812423 sw s0,168(sp) -8000605c: fff7c793 not a5,a5 -80006060: 0a912223 sw s1,164(sp) -80006064: 0b212023 sw s2,160(sp) -80006068: 09312e23 sw s3,156(sp) -8000606c: 0a112623 sw ra,172(sp) -80006070: 09412c23 sw s4,152(sp) -80006074: 09512a23 sw s5,148(sp) -80006078: 09612823 sw s6,144(sp) -8000607c: 09712623 sw s7,140(sp) -80006080: 09812423 sw s8,136(sp) -80006084: 09912223 sw s9,132(sp) -80006088: 09a12023 sw s10,128(sp) -8000608c: 07b12e23 sw s11,124(sp) -80006090: 01179713 slli a4,a5,0x11 -80006094: 00050913 mv s2,a0 -80006098: 00058993 mv s3,a1 -8000609c: 00060413 mv s0,a2 -800060a0: 00068493 mv s1,a3 -800060a4: 00071663 bnez a4,800060b0 -800060a8: ef5fe0ef jal ra,80004f9c -800060ac: 38051863 bnez a0,8000643c -800060b0: 0129d783 lhu a5,18(s3) -800060b4: fff7c793 not a5,a5 -800060b8: 01179713 slli a4,a5,0x11 -800060bc: 08070e63 beqz a4,80006158 -800060c0: 80015a37 lui s4,0x80015 -800060c4: e60a0593 addi a1,s4,-416 # 80014e60 <__BSS_END__+0xffffe224> -800060c8: 00090513 mv a0,s2 -800060cc: 878ff0ef jal ra,80005144 -800060d0: 10050463 beqz a0,800061d8 -800060d4: 01295a03 lhu s4,18(s2) -800060d8: 0129d703 lhu a4,18(s3) -800060dc: 000087b7 lui a5,0x8 -800060e0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -800060e4: 0147fa33 and s4,a5,s4 -800060e8: 00e7fab3 and s5,a5,a4 -800060ec: 08fa1a63 bne s4,a5,80006180 -800060f0: 00090513 mv a0,s2 -800060f4: 96cff0ef jal ra,80005260 -800060f8: 10050863 beqz a0,80006208 -800060fc: 014a9863 bne s5,s4,8000610c -80006100: 00098513 mv a0,s3 -80006104: 95cff0ef jal ra,80005260 -80006108: 0e051063 bnez a0,800061e8 -8000610c: 01440793 addi a5,s0,20 -80006110: 00240413 addi s0,s0,2 -80006114: fe041f23 sh zero,-2(s0) -80006118: fef41ce3 bne s0,a5,80006110 -8000611c: 0ac12083 lw ra,172(sp) -80006120: 0a812403 lw s0,168(sp) -80006124: 0a412483 lw s1,164(sp) -80006128: 0a012903 lw s2,160(sp) -8000612c: 09c12983 lw s3,156(sp) -80006130: 09812a03 lw s4,152(sp) -80006134: 09412a83 lw s5,148(sp) -80006138: 09012b03 lw s6,144(sp) -8000613c: 08c12b83 lw s7,140(sp) -80006140: 08812c03 lw s8,136(sp) -80006144: 08412c83 lw s9,132(sp) -80006148: 08012d03 lw s10,128(sp) -8000614c: 07c12d83 lw s11,124(sp) -80006150: 0b010113 addi sp,sp,176 -80006154: 00008067 ret -80006158: 00098513 mv a0,s3 -8000615c: e41fe0ef jal ra,80004f9c -80006160: f60500e3 beqz a0,800060c0 -80006164: 01498713 addi a4,s3,20 -80006168: 0009d783 lhu a5,0(s3) -8000616c: 00298993 addi s3,s3,2 -80006170: 00240413 addi s0,s0,2 -80006174: fef41f23 sh a5,-2(s0) -80006178: fee998e3 bne s3,a4,80006168 -8000617c: fa1ff06f j 8000611c -80006180: 08fa8663 beq s5,a5,8000620c -80006184: 00090513 mv a0,s2 -80006188: 01c10593 addi a1,sp,28 -8000618c: ec1fe0ef jal ra,8000504c -80006190: 03810593 addi a1,sp,56 -80006194: 00098513 mv a0,s3 -80006198: eb5fe0ef jal ra,8000504c -8000619c: 03a15b83 lhu s7,58(sp) -800061a0: 01e15903 lhu s2,30(sp) -800061a4: 0c0b9263 bnez s7,80006268 -800061a8: 03c10793 addi a5,sp,60 -800061ac: 05010d93 addi s11,sp,80 -800061b0: 34fd8e63 beq s11,a5,8000650c -800061b4: 0007d703 lhu a4,0(a5) -800061b8: 00278793 addi a5,a5,2 -800061bc: fe070ae3 beqz a4,800061b0 -800061c0: 03810513 addi a0,sp,56 -800061c4: ad4ff0ef jal ra,80005498 -800061c8: 40a007b3 neg a5,a0 -800061cc: 01e15603 lhu a2,30(sp) -800061d0: 00f12623 sw a5,12(sp) -800061d4: 09c0006f j 80006270 -800061d8: e60a0593 addi a1,s4,-416 -800061dc: 00098513 mv a0,s3 -800061e0: f65fe0ef jal ra,80005144 -800061e4: ee0518e3 bnez a0,800060d4 -800061e8: 01040713 addi a4,s0,16 -800061ec: 00040793 mv a5,s0 +80005f8c : +80005f8c: 01255783 lhu a5,18(a0) +80005f90: f5010113 addi sp,sp,-176 +80005f94: 0a812423 sw s0,168(sp) +80005f98: fff7c793 not a5,a5 +80005f9c: 0a912223 sw s1,164(sp) +80005fa0: 0b212023 sw s2,160(sp) +80005fa4: 09312e23 sw s3,156(sp) +80005fa8: 0a112623 sw ra,172(sp) +80005fac: 09412c23 sw s4,152(sp) +80005fb0: 09512a23 sw s5,148(sp) +80005fb4: 09612823 sw s6,144(sp) +80005fb8: 09712623 sw s7,140(sp) +80005fbc: 09812423 sw s8,136(sp) +80005fc0: 09912223 sw s9,132(sp) +80005fc4: 09a12023 sw s10,128(sp) +80005fc8: 07b12e23 sw s11,124(sp) +80005fcc: 01179713 slli a4,a5,0x11 +80005fd0: 00050913 mv s2,a0 +80005fd4: 00058993 mv s3,a1 +80005fd8: 00060413 mv s0,a2 +80005fdc: 00068493 mv s1,a3 +80005fe0: 00071663 bnez a4,80005fec +80005fe4: ef5fe0ef jal ra,80004ed8 +80005fe8: 38051863 bnez a0,80006378 +80005fec: 0129d783 lhu a5,18(s3) +80005ff0: fff7c793 not a5,a5 +80005ff4: 01179713 slli a4,a5,0x11 +80005ff8: 08070e63 beqz a4,80006094 +80005ffc: 80015a37 lui s4,0x80015 +80006000: d8ca0593 addi a1,s4,-628 # 80014d8c <__BSS_END__+0xffffe150> +80006004: 00090513 mv a0,s2 +80006008: 878ff0ef jal ra,80005080 +8000600c: 10050463 beqz a0,80006114 +80006010: 01295a03 lhu s4,18(s2) +80006014: 0129d703 lhu a4,18(s3) +80006018: 000087b7 lui a5,0x8 +8000601c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80006020: 0147fa33 and s4,a5,s4 +80006024: 00e7fab3 and s5,a5,a4 +80006028: 08fa1a63 bne s4,a5,800060bc +8000602c: 00090513 mv a0,s2 +80006030: 96cff0ef jal ra,8000519c +80006034: 10050863 beqz a0,80006144 +80006038: 014a9863 bne s5,s4,80006048 +8000603c: 00098513 mv a0,s3 +80006040: 95cff0ef jal ra,8000519c +80006044: 0e051063 bnez a0,80006124 +80006048: 01440793 addi a5,s0,20 +8000604c: 00240413 addi s0,s0,2 +80006050: fe041f23 sh zero,-2(s0) +80006054: fef41ce3 bne s0,a5,8000604c +80006058: 0ac12083 lw ra,172(sp) +8000605c: 0a812403 lw s0,168(sp) +80006060: 0a412483 lw s1,164(sp) +80006064: 0a012903 lw s2,160(sp) +80006068: 09c12983 lw s3,156(sp) +8000606c: 09812a03 lw s4,152(sp) +80006070: 09412a83 lw s5,148(sp) +80006074: 09012b03 lw s6,144(sp) +80006078: 08c12b83 lw s7,140(sp) +8000607c: 08812c03 lw s8,136(sp) +80006080: 08412c83 lw s9,132(sp) +80006084: 08012d03 lw s10,128(sp) +80006088: 07c12d83 lw s11,124(sp) +8000608c: 0b010113 addi sp,sp,176 +80006090: 00008067 ret +80006094: 00098513 mv a0,s3 +80006098: e41fe0ef jal ra,80004ed8 +8000609c: f60500e3 beqz a0,80005ffc +800060a0: 01498713 addi a4,s3,20 +800060a4: 0009d783 lhu a5,0(s3) +800060a8: 00298993 addi s3,s3,2 +800060ac: 00240413 addi s0,s0,2 +800060b0: fef41f23 sh a5,-2(s0) +800060b4: fee998e3 bne s3,a4,800060a4 +800060b8: fa1ff06f j 80006058 +800060bc: 08fa8663 beq s5,a5,80006148 +800060c0: 00090513 mv a0,s2 +800060c4: 01c10593 addi a1,sp,28 +800060c8: ec1fe0ef jal ra,80004f88 +800060cc: 03810593 addi a1,sp,56 +800060d0: 00098513 mv a0,s3 +800060d4: eb5fe0ef jal ra,80004f88 +800060d8: 03a15b83 lhu s7,58(sp) +800060dc: 01e15903 lhu s2,30(sp) +800060e0: 0c0b9263 bnez s7,800061a4 +800060e4: 03c10793 addi a5,sp,60 +800060e8: 05010d93 addi s11,sp,80 +800060ec: 34fd8e63 beq s11,a5,80006448 +800060f0: 0007d703 lhu a4,0(a5) +800060f4: 00278793 addi a5,a5,2 +800060f8: fe070ae3 beqz a4,800060ec +800060fc: 03810513 addi a0,sp,56 +80006100: ad4ff0ef jal ra,800053d4 +80006104: 40a007b3 neg a5,a0 +80006108: 01e15603 lhu a2,30(sp) +8000610c: 00f12623 sw a5,12(sp) +80006110: 09c0006f j 800061ac +80006114: d8ca0593 addi a1,s4,-628 +80006118: 00098513 mv a0,s3 +8000611c: f65fe0ef jal ra,80005080 +80006120: ee0518e3 bnez a0,80006010 +80006124: 01040713 addi a4,s0,16 +80006128: 00040793 mv a5,s0 +8000612c: 00278793 addi a5,a5,2 +80006130: fe079f23 sh zero,-2(a5) +80006134: fee79ce3 bne a5,a4,8000612c +80006138: 7fffc7b7 lui a5,0x7fffc +8000613c: 00f42823 sw a5,16(s0) +80006140: f19ff06f j 80006058 +80006144: f74a9ee3 bne s5,s4,800060c0 +80006148: 00098513 mv a0,s3 +8000614c: 850ff0ef jal ra,8000519c +80006150: f60508e3 beqz a0,800060c0 +80006154: 00090513 mv a0,s2 +80006158: df1fe0ef jal ra,80004f48 +8000615c: 00050493 mv s1,a0 +80006160: 00098513 mv a0,s3 +80006164: de5fe0ef jal ra,80004f48 +80006168: 40a487b3 sub a5,s1,a0 +8000616c: 00f037b3 snez a5,a5 +80006170: 00f79793 slli a5,a5,0xf +80006174: 00f41923 sh a5,18(s0) +80006178: 01240713 addi a4,s0,18 +8000617c: 00040793 mv a5,s0 +80006180: 00278793 addi a5,a5,2 # 7fffc002 <_start-0x3ffe> +80006184: fe079f23 sh zero,-2(a5) +80006188: fee79ce3 bne a5,a4,80006180 +8000618c: 01245783 lhu a5,18(s0) +80006190: 00008737 lui a4,0x8 +80006194: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80006198: 00e7e7b3 or a5,a5,a4 +8000619c: 00f41923 sh a5,18(s0) +800061a0: eb9ff06f j 80006058 +800061a4: 01712623 sw s7,12(sp) +800061a8: 00090613 mv a2,s2 +800061ac: 01212423 sw s2,8(sp) +800061b0: 02010793 addi a5,sp,32 +800061b4: 03410693 addi a3,sp,52 +800061b8: 02061263 bnez a2,800061dc +800061bc: 2af68063 beq a3,a5,8000645c +800061c0: 0007d703 lhu a4,0(a5) +800061c4: 00278793 addi a5,a5,2 +800061c8: fe070ae3 beqz a4,800061bc +800061cc: 01c10513 addi a0,sp,28 +800061d0: a04ff0ef jal ra,800053d4 +800061d4: 40a907b3 sub a5,s2,a0 +800061d8: 00f12423 sw a5,8(sp) +800061dc: 03812703 lw a4,56(sp) +800061e0: 03848d13 addi s10,s1,56 +800061e4: 000d0793 mv a5,s10 +800061e8: 02e4aa23 sw a4,52(s1) +800061ec: 04e48913 addi s2,s1,78 800061f0: 00278793 addi a5,a5,2 800061f4: fe079f23 sh zero,-2(a5) -800061f8: fee79ce3 bne a5,a4,800061f0 -800061fc: 7fffc7b7 lui a5,0x7fffc -80006200: 00f42823 sw a5,16(s0) -80006204: f19ff06f j 8000611c -80006208: f74a9ee3 bne s5,s4,80006184 -8000620c: 00098513 mv a0,s3 -80006210: 850ff0ef jal ra,80005260 -80006214: f60508e3 beqz a0,80006184 -80006218: 00090513 mv a0,s2 -8000621c: df1fe0ef jal ra,8000500c -80006220: 00050493 mv s1,a0 -80006224: 00098513 mv a0,s3 -80006228: de5fe0ef jal ra,8000500c -8000622c: 40a487b3 sub a5,s1,a0 -80006230: 00f037b3 snez a5,a5 -80006234: 00f79793 slli a5,a5,0xf -80006238: 00f41923 sh a5,18(s0) -8000623c: 01240713 addi a4,s0,18 -80006240: 00040793 mv a5,s0 -80006244: 00278793 addi a5,a5,2 # 7fffc002 <_start-0x3ffe> -80006248: fe079f23 sh zero,-2(a5) -8000624c: fee79ce3 bne a5,a4,80006244 -80006250: 01245783 lhu a5,18(s0) -80006254: 00008737 lui a4,0x8 -80006258: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -8000625c: 00e7e7b3 or a5,a5,a4 -80006260: 00f41923 sh a5,18(s0) -80006264: eb9ff06f j 8000611c -80006268: 01712623 sw s7,12(sp) -8000626c: 00090613 mv a2,s2 -80006270: 01212423 sw s2,8(sp) -80006274: 02010793 addi a5,sp,32 -80006278: 03410693 addi a3,sp,52 -8000627c: 02061263 bnez a2,800062a0 -80006280: 2af68063 beq a3,a5,80006520 -80006284: 0007d703 lhu a4,0(a5) -80006288: 00278793 addi a5,a5,2 -8000628c: fe070ae3 beqz a4,80006280 -80006290: 01c10513 addi a0,sp,28 -80006294: a04ff0ef jal ra,80005498 -80006298: 40a907b3 sub a5,s2,a0 -8000629c: 00f12423 sw a5,8(sp) -800062a0: 03812703 lw a4,56(sp) -800062a4: 03848d13 addi s10,s1,56 -800062a8: 000d0793 mv a5,s10 -800062ac: 02e4aa23 sw a4,52(s1) -800062b0: 04e48913 addi s2,s1,78 -800062b4: 00278793 addi a5,a5,2 -800062b8: fe079f23 sh zero,-2(a5) -800062bc: fef91ce3 bne s2,a5,800062b4 -800062c0: 03810513 addi a0,sp,56 -800062c4: b69fe0ef jal ra,80004e2c -800062c8: 02215c03 lhu s8,34(sp) -800062cc: 00010a37 lui s4,0x10 -800062d0: 05010d93 addi s11,sp,80 -800062d4: 010c1a93 slli s5,s8,0x10 -800062d8: 418a8ab3 sub s5,s5,s8 -800062dc: 03a10b13 addi s6,sp,58 -800062e0: fffa0a13 addi s4,s4,-1 # ffff <_start-0x7fff0001> -800062e4: 06e10c93 addi s9,sp,110 -800062e8: 05610993 addi s3,sp,86 -800062ec: 03c15783 lhu a5,60(sp) -800062f0: 03e15703 lhu a4,62(sp) -800062f4: 000a0b93 mv s7,s4 -800062f8: 01079793 slli a5,a5,0x10 -800062fc: 00e787b3 add a5,a5,a4 -80006300: 00fae863 bltu s5,a5,80006310 -80006304: 0387d7b3 divu a5,a5,s8 -80006308: 01079b93 slli s7,a5,0x10 -8000630c: 010bdb93 srli s7,s7,0x10 -80006310: 05410613 addi a2,sp,84 -80006314: 01c10593 addi a1,sp,28 -80006318: 000b8513 mv a0,s7 -8000631c: be9fe0ef jal ra,80004f04 -80006320: 03c10713 addi a4,sp,60 -80006324: 05810793 addi a5,sp,88 -80006328: 0007d583 lhu a1,0(a5) -8000632c: 00075603 lhu a2,0(a4) -80006330: 00278793 addi a5,a5,2 -80006334: 00270713 addi a4,a4,2 -80006338: 12c59063 bne a1,a2,80006458 -8000633c: ff9796e3 bne a5,s9,80006328 -80006340: 00000793 li a5,0 -80006344: 06c10593 addi a1,sp,108 -80006348: 000d8613 mv a2,s11 -8000634c: 00065703 lhu a4,0(a2) -80006350: 0005d803 lhu a6,0(a1) -80006354: ffe60613 addi a2,a2,-2 -80006358: 40f70733 sub a4,a4,a5 -8000635c: 41070733 sub a4,a4,a6 -80006360: 01075793 srli a5,a4,0x10 -80006364: 00e61123 sh a4,2(a2) -80006368: 0017f793 andi a5,a5,1 -8000636c: ffe58593 addi a1,a1,-2 -80006370: fd661ee3 bne a2,s6,8000634c -80006374: 017d1023 sh s7,0(s10) -80006378: 03c10793 addi a5,sp,60 -8000637c: 0027d703 lhu a4,2(a5) -80006380: 00278793 addi a5,a5,2 -80006384: fee79f23 sh a4,-2(a5) -80006388: ffb79ae3 bne a5,s11,8000637c -8000638c: 04011823 sh zero,80(sp) -80006390: 002d0d13 addi s10,s10,2 -80006394: f5a91ce3 bne s2,s10,800062ec -80006398: 00000593 li a1,0 -8000639c: 03c10793 addi a5,sp,60 -800063a0: 05210693 addi a3,sp,82 -800063a4: 0007d703 lhu a4,0(a5) -800063a8: 00278793 addi a5,a5,2 -800063ac: 00e5e5b3 or a1,a1,a4 -800063b0: fed79ae3 bne a5,a3,800063a4 -800063b4: 01059793 slli a5,a1,0x10 -800063b8: 4107d793 srai a5,a5,0x10 -800063bc: 00078463 beqz a5,800063c4 -800063c0: 00100593 li a1,1 -800063c4: 01059593 slli a1,a1,0x10 -800063c8: 0105d593 srli a1,a1,0x10 -800063cc: 03448713 addi a4,s1,52 -800063d0: 03810793 addi a5,sp,56 -800063d4: 00075603 lhu a2,0(a4) -800063d8: 00278793 addi a5,a5,2 -800063dc: 00270713 addi a4,a4,2 -800063e0: fec79f23 sh a2,-2(a5) -800063e4: fef698e3 bne a3,a5,800063d4 -800063e8: 00c12783 lw a5,12(sp) -800063ec: 00812703 lw a4,8(sp) -800063f0: 000046b7 lui a3,0x4 -800063f4: fff68693 addi a3,a3,-1 # 3fff <_start-0x7fffc001> -800063f8: 40e78bb3 sub s7,a5,a4 -800063fc: 03810513 addi a0,sp,56 -80006400: 00048793 mv a5,s1 -80006404: 04000713 li a4,64 -80006408: 00db86b3 add a3,s7,a3 -8000640c: 00000613 li a2,0 -80006410: a04ff0ef jal ra,80005614 -80006414: 03815703 lhu a4,56(sp) -80006418: 01c15783 lhu a5,28(sp) -8000641c: 00040593 mv a1,s0 -80006420: 03810513 addi a0,sp,56 -80006424: 40e787b3 sub a5,a5,a4 -80006428: 00f037b3 snez a5,a5 -8000642c: 40f007b3 neg a5,a5 -80006430: 02f11c23 sh a5,56(sp) -80006434: f54ff0ef jal ra,80005b88 -80006438: ce5ff06f j 8000611c -8000643c: 01490713 addi a4,s2,20 -80006440: 00095783 lhu a5,0(s2) -80006444: 00290913 addi s2,s2,2 -80006448: 00240413 addi s0,s0,2 -8000644c: fef41f23 sh a5,-2(s0) -80006450: fee918e3 bne s2,a4,80006440 -80006454: cc9ff06f j 8000611c -80006458: eeb674e3 bgeu a2,a1,80006340 -8000645c: fffb8793 addi a5,s7,-1 -80006460: 01079893 slli a7,a5,0x10 -80006464: 0108d893 srli a7,a7,0x10 -80006468: 00000793 li a5,0 -8000646c: 03410593 addi a1,sp,52 -80006470: 06c10613 addi a2,sp,108 -80006474: 00065703 lhu a4,0(a2) -80006478: 0005d803 lhu a6,0(a1) -8000647c: ffe60613 addi a2,a2,-2 -80006480: 40f70733 sub a4,a4,a5 -80006484: 41070733 sub a4,a4,a6 -80006488: 01075793 srli a5,a4,0x10 -8000648c: 00e61123 sh a4,2(a2) -80006490: 0017f793 andi a5,a5,1 -80006494: ffe58593 addi a1,a1,-2 -80006498: fd361ee3 bne a2,s3,80006474 -8000649c: 03c10713 addi a4,sp,60 -800064a0: 05810793 addi a5,sp,88 -800064a4: 0007d583 lhu a1,0(a5) -800064a8: 00075603 lhu a2,0(a4) -800064ac: 00278793 addi a5,a5,2 -800064b0: 00270713 addi a4,a4,2 -800064b4: 00c59863 bne a1,a2,800064c4 -800064b8: ff9796e3 bne a5,s9,800064a4 -800064bc: 00088b93 mv s7,a7 -800064c0: e81ff06f j 80006340 -800064c4: feb67ce3 bgeu a2,a1,800064bc -800064c8: ffeb8793 addi a5,s7,-2 -800064cc: 01079b93 slli s7,a5,0x10 -800064d0: 010bdb93 srli s7,s7,0x10 -800064d4: 00000613 li a2,0 -800064d8: 03410593 addi a1,sp,52 -800064dc: 06c10713 addi a4,sp,108 -800064e0: 00075783 lhu a5,0(a4) -800064e4: 0005d803 lhu a6,0(a1) -800064e8: ffe70713 addi a4,a4,-2 -800064ec: 40c787b3 sub a5,a5,a2 -800064f0: 410787b3 sub a5,a5,a6 -800064f4: 0107d613 srli a2,a5,0x10 -800064f8: 00f71123 sh a5,2(a4) -800064fc: 00167613 andi a2,a2,1 -80006500: ffe58593 addi a1,a1,-2 -80006504: fd371ee3 bne a4,s3,800064e0 -80006508: e39ff06f j 80006340 -8000650c: 01440793 addi a5,s0,20 -80006510: 00240413 addi s0,s0,2 -80006514: fe041f23 sh zero,-2(s0) -80006518: fe879ce3 bne a5,s0,80006510 -8000651c: c01ff06f j 8000611c -80006520: 01c15703 lhu a4,28(sp) -80006524: 03815783 lhu a5,56(sp) -80006528: 00f70463 beq a4,a5,80006530 -8000652c: 00008637 lui a2,0x8 -80006530: 00c41923 sh a2,18(s0) -80006534: 01240713 addi a4,s0,18 -80006538: 00040793 mv a5,s0 -8000653c: 00278793 addi a5,a5,2 -80006540: fe079f23 sh zero,-2(a5) -80006544: fef71ce3 bne a4,a5,8000653c -80006548: 01245783 lhu a5,18(s0) -8000654c: 00008737 lui a4,0x8 -80006550: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80006554: 00e7e7b3 or a5,a5,a4 -80006558: 00f41923 sh a5,18(s0) -8000655c: bc1ff06f j 8000611c +800061f8: fef91ce3 bne s2,a5,800061f0 +800061fc: 03810513 addi a0,sp,56 +80006200: b69fe0ef jal ra,80004d68 +80006204: 02215c03 lhu s8,34(sp) +80006208: 00010a37 lui s4,0x10 +8000620c: 05010d93 addi s11,sp,80 +80006210: 010c1a93 slli s5,s8,0x10 +80006214: 418a8ab3 sub s5,s5,s8 +80006218: 03a10b13 addi s6,sp,58 +8000621c: fffa0a13 addi s4,s4,-1 # ffff <_start-0x7fff0001> +80006220: 06e10c93 addi s9,sp,110 +80006224: 05610993 addi s3,sp,86 +80006228: 03c15783 lhu a5,60(sp) +8000622c: 03e15703 lhu a4,62(sp) +80006230: 000a0b93 mv s7,s4 +80006234: 01079793 slli a5,a5,0x10 +80006238: 00e787b3 add a5,a5,a4 +8000623c: 00fae863 bltu s5,a5,8000624c +80006240: 0387d7b3 divu a5,a5,s8 +80006244: 01079b93 slli s7,a5,0x10 +80006248: 010bdb93 srli s7,s7,0x10 +8000624c: 05410613 addi a2,sp,84 +80006250: 01c10593 addi a1,sp,28 +80006254: 000b8513 mv a0,s7 +80006258: be9fe0ef jal ra,80004e40 +8000625c: 03c10713 addi a4,sp,60 +80006260: 05810793 addi a5,sp,88 +80006264: 0007d583 lhu a1,0(a5) +80006268: 00075603 lhu a2,0(a4) +8000626c: 00278793 addi a5,a5,2 +80006270: 00270713 addi a4,a4,2 +80006274: 12c59063 bne a1,a2,80006394 +80006278: ff9796e3 bne a5,s9,80006264 +8000627c: 00000793 li a5,0 +80006280: 06c10593 addi a1,sp,108 +80006284: 000d8613 mv a2,s11 +80006288: 00065703 lhu a4,0(a2) +8000628c: 0005d803 lhu a6,0(a1) +80006290: ffe60613 addi a2,a2,-2 +80006294: 40f70733 sub a4,a4,a5 +80006298: 41070733 sub a4,a4,a6 +8000629c: 01075793 srli a5,a4,0x10 +800062a0: 00e61123 sh a4,2(a2) +800062a4: 0017f793 andi a5,a5,1 +800062a8: ffe58593 addi a1,a1,-2 +800062ac: fd661ee3 bne a2,s6,80006288 +800062b0: 017d1023 sh s7,0(s10) +800062b4: 03c10793 addi a5,sp,60 +800062b8: 0027d703 lhu a4,2(a5) +800062bc: 00278793 addi a5,a5,2 +800062c0: fee79f23 sh a4,-2(a5) +800062c4: ffb79ae3 bne a5,s11,800062b8 +800062c8: 04011823 sh zero,80(sp) +800062cc: 002d0d13 addi s10,s10,2 +800062d0: f5a91ce3 bne s2,s10,80006228 +800062d4: 00000593 li a1,0 +800062d8: 03c10793 addi a5,sp,60 +800062dc: 05210693 addi a3,sp,82 +800062e0: 0007d703 lhu a4,0(a5) +800062e4: 00278793 addi a5,a5,2 +800062e8: 00e5e5b3 or a1,a1,a4 +800062ec: fed79ae3 bne a5,a3,800062e0 +800062f0: 01059793 slli a5,a1,0x10 +800062f4: 4107d793 srai a5,a5,0x10 +800062f8: 00078463 beqz a5,80006300 +800062fc: 00100593 li a1,1 +80006300: 01059593 slli a1,a1,0x10 +80006304: 0105d593 srli a1,a1,0x10 +80006308: 03448713 addi a4,s1,52 +8000630c: 03810793 addi a5,sp,56 +80006310: 00075603 lhu a2,0(a4) +80006314: 00278793 addi a5,a5,2 +80006318: 00270713 addi a4,a4,2 +8000631c: fec79f23 sh a2,-2(a5) +80006320: fef698e3 bne a3,a5,80006310 +80006324: 00c12783 lw a5,12(sp) +80006328: 00812703 lw a4,8(sp) +8000632c: 000046b7 lui a3,0x4 +80006330: fff68693 addi a3,a3,-1 # 3fff <_start-0x7fffc001> +80006334: 40e78bb3 sub s7,a5,a4 +80006338: 03810513 addi a0,sp,56 +8000633c: 00048793 mv a5,s1 +80006340: 04000713 li a4,64 +80006344: 00db86b3 add a3,s7,a3 +80006348: 00000613 li a2,0 +8000634c: a04ff0ef jal ra,80005550 +80006350: 03815703 lhu a4,56(sp) +80006354: 01c15783 lhu a5,28(sp) +80006358: 00040593 mv a1,s0 +8000635c: 03810513 addi a0,sp,56 +80006360: 40e787b3 sub a5,a5,a4 +80006364: 00f037b3 snez a5,a5 +80006368: 40f007b3 neg a5,a5 +8000636c: 02f11c23 sh a5,56(sp) +80006370: f54ff0ef jal ra,80005ac4 +80006374: ce5ff06f j 80006058 +80006378: 01490713 addi a4,s2,20 +8000637c: 00095783 lhu a5,0(s2) +80006380: 00290913 addi s2,s2,2 +80006384: 00240413 addi s0,s0,2 +80006388: fef41f23 sh a5,-2(s0) +8000638c: fee918e3 bne s2,a4,8000637c +80006390: cc9ff06f j 80006058 +80006394: eeb674e3 bgeu a2,a1,8000627c +80006398: fffb8793 addi a5,s7,-1 +8000639c: 01079893 slli a7,a5,0x10 +800063a0: 0108d893 srli a7,a7,0x10 +800063a4: 00000793 li a5,0 +800063a8: 03410593 addi a1,sp,52 +800063ac: 06c10613 addi a2,sp,108 +800063b0: 00065703 lhu a4,0(a2) +800063b4: 0005d803 lhu a6,0(a1) +800063b8: ffe60613 addi a2,a2,-2 +800063bc: 40f70733 sub a4,a4,a5 +800063c0: 41070733 sub a4,a4,a6 +800063c4: 01075793 srli a5,a4,0x10 +800063c8: 00e61123 sh a4,2(a2) +800063cc: 0017f793 andi a5,a5,1 +800063d0: ffe58593 addi a1,a1,-2 +800063d4: fd361ee3 bne a2,s3,800063b0 +800063d8: 03c10713 addi a4,sp,60 +800063dc: 05810793 addi a5,sp,88 +800063e0: 0007d583 lhu a1,0(a5) +800063e4: 00075603 lhu a2,0(a4) +800063e8: 00278793 addi a5,a5,2 +800063ec: 00270713 addi a4,a4,2 +800063f0: 00c59863 bne a1,a2,80006400 +800063f4: ff9796e3 bne a5,s9,800063e0 +800063f8: 00088b93 mv s7,a7 +800063fc: e81ff06f j 8000627c +80006400: feb67ce3 bgeu a2,a1,800063f8 +80006404: ffeb8793 addi a5,s7,-2 +80006408: 01079b93 slli s7,a5,0x10 +8000640c: 010bdb93 srli s7,s7,0x10 +80006410: 00000613 li a2,0 +80006414: 03410593 addi a1,sp,52 +80006418: 06c10713 addi a4,sp,108 +8000641c: 00075783 lhu a5,0(a4) +80006420: 0005d803 lhu a6,0(a1) +80006424: ffe70713 addi a4,a4,-2 +80006428: 40c787b3 sub a5,a5,a2 +8000642c: 410787b3 sub a5,a5,a6 +80006430: 0107d613 srli a2,a5,0x10 +80006434: 00f71123 sh a5,2(a4) +80006438: 00167613 andi a2,a2,1 +8000643c: ffe58593 addi a1,a1,-2 +80006440: fd371ee3 bne a4,s3,8000641c +80006444: e39ff06f j 8000627c +80006448: 01440793 addi a5,s0,20 +8000644c: 00240413 addi s0,s0,2 +80006450: fe041f23 sh zero,-2(s0) +80006454: fe879ce3 bne a5,s0,8000644c +80006458: c01ff06f j 80006058 +8000645c: 01c15703 lhu a4,28(sp) +80006460: 03815783 lhu a5,56(sp) +80006464: 00f70463 beq a4,a5,8000646c +80006468: 00008637 lui a2,0x8 +8000646c: 00c41923 sh a2,18(s0) +80006470: 01240713 addi a4,s0,18 +80006474: 00040793 mv a5,s0 +80006478: 00278793 addi a5,a5,2 +8000647c: fe079f23 sh zero,-2(a5) +80006480: fef71ce3 bne a4,a5,80006478 +80006484: 01245783 lhu a5,18(s0) +80006488: 00008737 lui a4,0x8 +8000648c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80006490: 00e7e7b3 or a5,a5,a4 +80006494: 00f41923 sh a5,18(s0) +80006498: bc1ff06f j 80006058 -80006560 : -80006560: fd010113 addi sp,sp,-48 -80006564: 02812423 sw s0,40(sp) -80006568: 02112623 sw ra,44(sp) -8000656c: 00058413 mv s0,a1 -80006570: 00410793 addi a5,sp,4 -80006574: 01e10713 addi a4,sp,30 +8000649c : +8000649c: fd010113 addi sp,sp,-48 +800064a0: 02812423 sw s0,40(sp) +800064a4: 02112623 sw ra,44(sp) +800064a8: 00058413 mv s0,a1 +800064ac: 00410793 addi a5,sp,4 +800064b0: 01e10713 addi a4,sp,30 +800064b4: 00278793 addi a5,a5,2 +800064b8: fe079f23 sh zero,-2(a5) +800064bc: fee79ce3 bne a5,a4,800064b4 +800064c0: 00e55603 lhu a2,14(a0) +800064c4: 01061793 slli a5,a2,0x10 +800064c8: 4107d793 srai a5,a5,0x10 +800064cc: 0607ca63 bltz a5,80006540 +800064d0: 000087b7 lui a5,0x8 +800064d4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800064d8: 00011223 sh zero,4(sp) +800064dc: 00f67633 and a2,a2,a5 +800064e0: 06f60c63 beq a2,a5,80006558 +800064e4: 00e50793 addi a5,a0,14 +800064e8: 00c11323 sh a2,6(sp) +800064ec: 00a10713 addi a4,sp,10 +800064f0: ffe7d683 lhu a3,-2(a5) +800064f4: ffe78793 addi a5,a5,-2 +800064f8: 00270713 addi a4,a4,2 +800064fc: fed71f23 sh a3,-2(a4) +80006500: fef518e3 bne a0,a5,800064f0 +80006504: 02061263 bnez a2,80006528 +80006508: 00011423 sh zero,8(sp) +8000650c: 00040593 mv a1,s0 +80006510: 00410513 addi a0,sp,4 +80006514: db0ff0ef jal ra,80005ac4 +80006518: 02c12083 lw ra,44(sp) +8000651c: 02812403 lw s0,40(sp) +80006520: 03010113 addi sp,sp,48 +80006524: 00008067 ret +80006528: 00100793 li a5,1 +8000652c: fff00593 li a1,-1 +80006530: 00410513 addi a0,sp,4 +80006534: 00f11423 sh a5,8(sp) +80006538: c81fe0ef jal ra,800051b8 +8000653c: fd1ff06f j 8000650c +80006540: fff00793 li a5,-1 +80006544: 00f11223 sh a5,4(sp) +80006548: 000087b7 lui a5,0x8 +8000654c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80006550: 00f67633 and a2,a2,a5 +80006554: f8f618e3 bne a2,a5,800064e4 +80006558: 00050793 mv a5,a0 +8000655c: 00e50693 addi a3,a0,14 +80006560: 0007d703 lhu a4,0(a5) +80006564: 00278793 addi a5,a5,2 +80006568: 04071c63 bnez a4,800065c0 +8000656c: fed79ae3 bne a5,a3,80006560 +80006570: 01440713 addi a4,s0,20 +80006574: 00040793 mv a5,s0 80006578: 00278793 addi a5,a5,2 8000657c: fe079f23 sh zero,-2(a5) -80006580: fee79ce3 bne a5,a4,80006578 -80006584: 00e55603 lhu a2,14(a0) -80006588: 01061793 slli a5,a2,0x10 -8000658c: 4107d793 srai a5,a5,0x10 -80006590: 0607ca63 bltz a5,80006604 -80006594: 000087b7 lui a5,0x8 -80006598: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -8000659c: 00011223 sh zero,4(sp) -800065a0: 00f67633 and a2,a2,a5 -800065a4: 06f60c63 beq a2,a5,8000661c -800065a8: 00e50793 addi a5,a0,14 -800065ac: 00c11323 sh a2,6(sp) -800065b0: 00a10713 addi a4,sp,10 -800065b4: ffe7d683 lhu a3,-2(a5) -800065b8: ffe78793 addi a5,a5,-2 -800065bc: 00270713 addi a4,a4,2 -800065c0: fed71f23 sh a3,-2(a4) -800065c4: fef518e3 bne a0,a5,800065b4 -800065c8: 02061263 bnez a2,800065ec -800065cc: 00011423 sh zero,8(sp) -800065d0: 00040593 mv a1,s0 -800065d4: 00410513 addi a0,sp,4 -800065d8: db0ff0ef jal ra,80005b88 -800065dc: 02c12083 lw ra,44(sp) -800065e0: 02812403 lw s0,40(sp) -800065e4: 03010113 addi sp,sp,48 -800065e8: 00008067 ret -800065ec: 00100793 li a5,1 -800065f0: fff00593 li a1,-1 -800065f4: 00410513 addi a0,sp,4 -800065f8: 00f11423 sh a5,8(sp) -800065fc: c81fe0ef jal ra,8000527c -80006600: fd1ff06f j 800065d0 -80006604: fff00793 li a5,-1 -80006608: 00f11223 sh a5,4(sp) -8000660c: 000087b7 lui a5,0x8 -80006610: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80006614: 00f67633 and a2,a2,a5 -80006618: f8f618e3 bne a2,a5,800065a8 -8000661c: 00050793 mv a5,a0 -80006620: 00e50693 addi a3,a0,14 -80006624: 0007d703 lhu a4,0(a5) -80006628: 00278793 addi a5,a5,2 -8000662c: 04071c63 bnez a4,80006684 -80006630: fed79ae3 bne a5,a3,80006624 -80006634: 01440713 addi a4,s0,20 -80006638: 00040793 mv a5,s0 -8000663c: 00278793 addi a5,a5,2 -80006640: fe079f23 sh zero,-2(a5) -80006644: fef71ce3 bne a4,a5,8000663c -80006648: 01240713 addi a4,s0,18 -8000664c: 00040793 mv a5,s0 -80006650: 00278793 addi a5,a5,2 -80006654: fe079f23 sh zero,-2(a5) -80006658: fef71ce3 bne a4,a5,80006650 -8000665c: 01245783 lhu a5,18(s0) -80006660: 00008737 lui a4,0x8 -80006664: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80006668: 00e7e7b3 or a5,a5,a4 -8000666c: 00f41923 sh a5,18(s0) -80006670: 00e51783 lh a5,14(a0) -80006674: f607d4e3 bgez a5,800065dc -80006678: 00040513 mv a0,s0 -8000667c: 945fe0ef jal ra,80004fc0 -80006680: f5dff06f j 800065dc -80006684: 01040713 addi a4,s0,16 -80006688: 00040793 mv a5,s0 -8000668c: 00278793 addi a5,a5,2 -80006690: fe079f23 sh zero,-2(a5) -80006694: fef71ce3 bne a4,a5,8000668c -80006698: 7fffc7b7 lui a5,0x7fffc -8000669c: 00f42823 sw a5,16(s0) -800066a0: f3dff06f j 800065dc +80006580: fef71ce3 bne a4,a5,80006578 +80006584: 01240713 addi a4,s0,18 +80006588: 00040793 mv a5,s0 +8000658c: 00278793 addi a5,a5,2 +80006590: fe079f23 sh zero,-2(a5) +80006594: fef71ce3 bne a4,a5,8000658c +80006598: 01245783 lhu a5,18(s0) +8000659c: 00008737 lui a4,0x8 +800065a0: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +800065a4: 00e7e7b3 or a5,a5,a4 +800065a8: 00f41923 sh a5,18(s0) +800065ac: 00e51783 lh a5,14(a0) +800065b0: f607d4e3 bgez a5,80006518 +800065b4: 00040513 mv a0,s0 +800065b8: 945fe0ef jal ra,80004efc +800065bc: f5dff06f j 80006518 +800065c0: 01040713 addi a4,s0,16 +800065c4: 00040793 mv a5,s0 +800065c8: 00278793 addi a5,a5,2 +800065cc: fe079f23 sh zero,-2(a5) +800065d0: fef71ce3 bne a4,a5,800065c8 +800065d4: 7fffc7b7 lui a5,0x7fffc +800065d8: 00f42823 sw a5,16(s0) +800065dc: f3dff06f j 80006518 -800066a4 <_ldtoa_r>: -800066a4: 00c5a883 lw a7,12(a1) -800066a8: e1010113 addi sp,sp,-496 -800066ac: 0005ae83 lw t4,0(a1) -800066b0: 0045ae03 lw t3,4(a1) -800066b4: 0085a303 lw t1,8(a1) -800066b8: 03112e23 sw a7,60(sp) -800066bc: 04052583 lw a1,64(a0) -800066c0: fff00893 li a7,-1 -800066c4: 17112023 sw a7,352(sp) -800066c8: 09000893 li a7,144 -800066cc: 1e812423 sw s0,488(sp) -800066d0: 1d412c23 sw s4,472(sp) -800066d4: 1e112623 sw ra,492(sp) -800066d8: 1e912223 sw s1,484(sp) -800066dc: 1f212023 sw s2,480(sp) -800066e0: 1d312e23 sw s3,476(sp) -800066e4: 1d512a23 sw s5,468(sp) -800066e8: 1d612823 sw s6,464(sp) -800066ec: 1d712623 sw s7,460(sp) -800066f0: 1d812423 sw s8,456(sp) -800066f4: 1d912223 sw s9,452(sp) -800066f8: 1da12023 sw s10,448(sp) -800066fc: 1bb12e23 sw s11,444(sp) -80006700: 03d12823 sw t4,48(sp) -80006704: 03c12a23 sw t3,52(sp) -80006708: 02612c23 sw t1,56(sp) -8000670c: 17112223 sw a7,356(sp) -80006710: 00c12023 sw a2,0(sp) -80006714: 00d12423 sw a3,8(sp) -80006718: 00e12623 sw a4,12(sp) -8000671c: 01012c23 sw a6,24(sp) -80006720: 00050a13 mv s4,a0 -80006724: 00078413 mv s0,a5 -80006728: 02058063 beqz a1,80006748 <_ldtoa_r+0xa4> -8000672c: 04452703 lw a4,68(a0) -80006730: 00100793 li a5,1 -80006734: 00e797b3 sll a5,a5,a4 -80006738: 00e5a223 sw a4,4(a1) -8000673c: 00f5a423 sw a5,8(a1) -80006740: 661010ef jal ra,800085a0 <_Bfree> -80006744: 040a2023 sw zero,64(s4) -80006748: 06010993 addi s3,sp,96 -8000674c: 00098593 mv a1,s3 -80006750: 03010513 addi a0,sp,48 -80006754: e0dff0ef jal ra,80006560 -80006758: 00098513 mv a0,s3 -8000675c: 8b1fe0ef jal ra,8000500c -80006760: 00012703 lw a4,0(sp) -80006764: 00a03533 snez a0,a0 -80006768: 00a42023 sw a0,0(s0) -8000676c: 00300793 li a5,3 -80006770: 14f702e3 beq a4,a5,800070b4 <_ldtoa_r+0xa10> -80006774: 01400793 li a5,20 -80006778: 00f12223 sw a5,4(sp) -8000677c: 5e0718e3 bnez a4,8000756c <_ldtoa_r+0xec8> -80006780: 07215783 lhu a5,114(sp) -80006784: 16412703 lw a4,356(sp) -80006788: fff7c793 not a5,a5 -8000678c: 00e12a23 sw a4,20(sp) -80006790: 01179713 slli a4,a5,0x11 -80006794: 00071863 bnez a4,800067a4 <_ldtoa_r+0x100> -80006798: 00098513 mv a0,s3 -8000679c: 801fe0ef jal ra,80004f9c -800067a0: 400514e3 bnez a0,800073a8 <_ldtoa_r+0xd04> -800067a4: 09000793 li a5,144 -800067a8: 16f12223 sw a5,356(sp) -800067ac: 07c10713 addi a4,sp,124 -800067b0: 00098793 mv a5,s3 -800067b4: 07410613 addi a2,sp,116 -800067b8: 0007d683 lhu a3,0(a5) # 7fffc000 <_start-0x4000> -800067bc: 00278793 addi a5,a5,2 -800067c0: 00270713 addi a4,a4,2 -800067c4: fed71f23 sh a3,-2(a4) -800067c8: fec798e3 bne a5,a2,800067b8 <_ldtoa_r+0x114> -800067cc: 08e15603 lhu a2,142(sp) -800067d0: 00012823 sw zero,16(sp) -800067d4: 01061793 slli a5,a2,0x10 -800067d8: 4107d793 srai a5,a5,0x10 -800067dc: 0007de63 bgez a5,800067f8 <_ldtoa_r+0x154> -800067e0: 01161613 slli a2,a2,0x11 -800067e4: 000107b7 lui a5,0x10 -800067e8: 01165613 srli a2,a2,0x11 -800067ec: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -800067f0: 08c11723 sh a2,142(sp) -800067f4: 00f12823 sw a5,16(sp) -800067f8: 80015b37 lui s6,0x80015 -800067fc: e60b0d93 addi s11,s6,-416 # 80014e60 <__BSS_END__+0xffffe224> -80006800: 014d8c13 addi s8,s11,20 -80006804: 00000693 li a3,0 -80006808: 09810793 addi a5,sp,152 -8000680c: 000c0713 mv a4,s8 -80006810: 0ac10d13 addi s10,sp,172 -80006814: 0080006f j 8000681c <_ldtoa_r+0x178> -80006818: 00075683 lhu a3,0(a4) -8000681c: 00278793 addi a5,a5,2 -80006820: fed79f23 sh a3,-2(a5) -80006824: 00270713 addi a4,a4,2 -80006828: ffa798e3 bne a5,s10,80006818 <_ldtoa_r+0x174> -8000682c: 14060863 beqz a2,8000697c <_ldtoa_r+0x2d8> -80006830: 000087b7 lui a5,0x8 -80006834: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80006838: 56f606e3 beq a2,a5,800075a4 <_ldtoa_r+0xf00> -8000683c: 08c11783 lh a5,140(sp) -80006840: 5a07d8e3 bgez a5,800075f0 <_ldtoa_r+0xf4c> -80006844: 07c10593 addi a1,sp,124 -80006848: 000c0513 mv a0,s8 -8000684c: 8f9fe0ef jal ra,80005144 -80006850: 14050263 beqz a0,80006994 <_ldtoa_r+0x2f0> -80006854: 0c054ce3 bltz a0,8000712c <_ldtoa_r+0xa88> -80006858: 08e15783 lhu a5,142(sp) -8000685c: 62079ce3 bnez a5,80007694 <_ldtoa_r+0xff0> -80006860: 08c11783 lh a5,140(sp) -80006864: 00000493 li s1,0 -80006868: 16010913 addi s2,sp,352 -8000686c: 0207c463 bltz a5,80006894 <_ldtoa_r+0x1f0> -80006870: 118d8413 addi s0,s11,280 -80006874: 07c10613 addi a2,sp,124 +800065e0 <_ldtoa_r>: +800065e0: 00c5a883 lw a7,12(a1) +800065e4: e1010113 addi sp,sp,-496 +800065e8: 0005ae83 lw t4,0(a1) +800065ec: 0045ae03 lw t3,4(a1) +800065f0: 0085a303 lw t1,8(a1) +800065f4: 03112e23 sw a7,60(sp) +800065f8: 04052583 lw a1,64(a0) +800065fc: fff00893 li a7,-1 +80006600: 17112023 sw a7,352(sp) +80006604: 09000893 li a7,144 +80006608: 1e812423 sw s0,488(sp) +8000660c: 1d412c23 sw s4,472(sp) +80006610: 1e112623 sw ra,492(sp) +80006614: 1e912223 sw s1,484(sp) +80006618: 1f212023 sw s2,480(sp) +8000661c: 1d312e23 sw s3,476(sp) +80006620: 1d512a23 sw s5,468(sp) +80006624: 1d612823 sw s6,464(sp) +80006628: 1d712623 sw s7,460(sp) +8000662c: 1d812423 sw s8,456(sp) +80006630: 1d912223 sw s9,452(sp) +80006634: 1da12023 sw s10,448(sp) +80006638: 1bb12e23 sw s11,444(sp) +8000663c: 03d12823 sw t4,48(sp) +80006640: 03c12a23 sw t3,52(sp) +80006644: 02612c23 sw t1,56(sp) +80006648: 17112223 sw a7,356(sp) +8000664c: 00c12023 sw a2,0(sp) +80006650: 00d12423 sw a3,8(sp) +80006654: 00e12623 sw a4,12(sp) +80006658: 01012c23 sw a6,24(sp) +8000665c: 00050a13 mv s4,a0 +80006660: 00078413 mv s0,a5 +80006664: 02058063 beqz a1,80006684 <_ldtoa_r+0xa4> +80006668: 04452703 lw a4,68(a0) +8000666c: 00100793 li a5,1 +80006670: 00e797b3 sll a5,a5,a4 +80006674: 00e5a223 sw a4,4(a1) +80006678: 00f5a423 sw a5,8(a1) +8000667c: 661010ef jal ra,800084dc <_Bfree> +80006680: 040a2023 sw zero,64(s4) +80006684: 06010993 addi s3,sp,96 +80006688: 00098593 mv a1,s3 +8000668c: 03010513 addi a0,sp,48 +80006690: e0dff0ef jal ra,8000649c +80006694: 00098513 mv a0,s3 +80006698: 8b1fe0ef jal ra,80004f48 +8000669c: 00012703 lw a4,0(sp) +800066a0: 00a03533 snez a0,a0 +800066a4: 00a42023 sw a0,0(s0) +800066a8: 00300793 li a5,3 +800066ac: 14f702e3 beq a4,a5,80006ff0 <_ldtoa_r+0xa10> +800066b0: 01400793 li a5,20 +800066b4: 00f12223 sw a5,4(sp) +800066b8: 5e0718e3 bnez a4,800074a8 <_ldtoa_r+0xec8> +800066bc: 07215783 lhu a5,114(sp) +800066c0: 16412703 lw a4,356(sp) +800066c4: fff7c793 not a5,a5 +800066c8: 00e12a23 sw a4,20(sp) +800066cc: 01179713 slli a4,a5,0x11 +800066d0: 00071863 bnez a4,800066e0 <_ldtoa_r+0x100> +800066d4: 00098513 mv a0,s3 +800066d8: 801fe0ef jal ra,80004ed8 +800066dc: 400514e3 bnez a0,800072e4 <_ldtoa_r+0xd04> +800066e0: 09000793 li a5,144 +800066e4: 16f12223 sw a5,356(sp) +800066e8: 07c10713 addi a4,sp,124 +800066ec: 00098793 mv a5,s3 +800066f0: 07410613 addi a2,sp,116 +800066f4: 0007d683 lhu a3,0(a5) # 7fffc000 <_start-0x4000> +800066f8: 00278793 addi a5,a5,2 +800066fc: 00270713 addi a4,a4,2 +80006700: fed71f23 sh a3,-2(a4) +80006704: fec798e3 bne a5,a2,800066f4 <_ldtoa_r+0x114> +80006708: 08e15603 lhu a2,142(sp) +8000670c: 00012823 sw zero,16(sp) +80006710: 01061793 slli a5,a2,0x10 +80006714: 4107d793 srai a5,a5,0x10 +80006718: 0007de63 bgez a5,80006734 <_ldtoa_r+0x154> +8000671c: 01161613 slli a2,a2,0x11 +80006720: 000107b7 lui a5,0x10 +80006724: 01165613 srli a2,a2,0x11 +80006728: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +8000672c: 08c11723 sh a2,142(sp) +80006730: 00f12823 sw a5,16(sp) +80006734: 80015b37 lui s6,0x80015 +80006738: d8cb0d93 addi s11,s6,-628 # 80014d8c <__BSS_END__+0xffffe150> +8000673c: 014d8c13 addi s8,s11,20 +80006740: 00000693 li a3,0 +80006744: 09810793 addi a5,sp,152 +80006748: 000c0713 mv a4,s8 +8000674c: 0ac10d13 addi s10,sp,172 +80006750: 0080006f j 80006758 <_ldtoa_r+0x178> +80006754: 00075683 lhu a3,0(a4) +80006758: 00278793 addi a5,a5,2 +8000675c: fed79f23 sh a3,-2(a5) +80006760: 00270713 addi a4,a4,2 +80006764: ffa798e3 bne a5,s10,80006754 <_ldtoa_r+0x174> +80006768: 14060863 beqz a2,800068b8 <_ldtoa_r+0x2d8> +8000676c: 000087b7 lui a5,0x8 +80006770: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80006774: 56f606e3 beq a2,a5,800074e0 <_ldtoa_r+0xf00> +80006778: 08c11783 lh a5,140(sp) +8000677c: 5a07d8e3 bgez a5,8000752c <_ldtoa_r+0xf4c> +80006780: 07c10593 addi a1,sp,124 +80006784: 000c0513 mv a0,s8 +80006788: 8f9fe0ef jal ra,80005080 +8000678c: 14050263 beqz a0,800068d0 <_ldtoa_r+0x2f0> +80006790: 0c054ce3 bltz a0,80007068 <_ldtoa_r+0xa88> +80006794: 08e15783 lhu a5,142(sp) +80006798: 62079ce3 bnez a5,800075d0 <_ldtoa_r+0xff0> +8000679c: 08c11783 lh a5,140(sp) +800067a0: 00000493 li s1,0 +800067a4: 16010913 addi s2,sp,352 +800067a8: 0207c463 bltz a5,800067d0 <_ldtoa_r+0x1f0> +800067ac: 118d8413 addi s0,s11,280 +800067b0: 07c10613 addi a2,sp,124 +800067b4: 00090693 mv a3,s2 +800067b8: 00060593 mv a1,a2 +800067bc: 00040513 mv a0,s0 +800067c0: bb4ff0ef jal ra,80005b74 +800067c4: 08c11783 lh a5,140(sp) +800067c8: fff48493 addi s1,s1,-1 +800067cc: fe07d2e3 bgez a5,800067b0 <_ldtoa_r+0x1d0> +800067d0: 0d010413 addi s0,sp,208 +800067d4: 0e810b93 addi s7,sp,232 +800067d8: 00040713 mv a4,s0 +800067dc: 07c10793 addi a5,sp,124 +800067e0: 09010613 addi a2,sp,144 +800067e4: 0007d683 lhu a3,0(a5) +800067e8: 00278793 addi a5,a5,2 +800067ec: 00270713 addi a4,a4,2 +800067f0: fed71f23 sh a3,-2(a4) +800067f4: fec798e3 bne a5,a2,800067e4 <_ldtoa_r+0x204> +800067f8: 00000693 li a3,0 +800067fc: 09810793 addi a5,sp,152 +80006800: 000c0713 mv a4,s8 +80006804: 0080006f j 8000680c <_ldtoa_r+0x22c> +80006808: 00075683 lhu a3,0(a4) +8000680c: 00278793 addi a5,a5,2 +80006810: fed79f23 sh a3,-2(a5) +80006814: 00270713 addi a4,a4,2 +80006818: ffa798e3 bne a5,s10,80006808 <_ldtoa_r+0x228> +8000681c: 028d8c93 addi s9,s11,40 +80006820: 12cd8d13 addi s10,s11,300 +80006824: fffffab7 lui s5,0xfffff +80006828: 118d8d93 addi s11,s11,280 +8000682c: 00c0006f j 80006838 <_ldtoa_r+0x258> +80006830: 014d0d13 addi s10,s10,20 +80006834: 014c8c93 addi s9,s9,20 +80006838: 00040593 mv a1,s0 +8000683c: 000c0513 mv a0,s8 +80006840: 841fe0ef jal ra,80005080 +80006844: 00050793 mv a5,a0 +80006848: 00040593 mv a1,s0 +8000684c: 000d0513 mv a0,s10 +80006850: 04f05663 blez a5,8000689c <_ldtoa_r+0x2bc> +80006854: 82dfe0ef jal ra,80005080 +80006858: 00050793 mv a5,a0 +8000685c: 00090693 mv a3,s2 +80006860: 00040613 mv a2,s0 +80006864: 00040593 mv a1,s0 +80006868: 000c8513 mv a0,s9 +8000686c: 0207c063 bltz a5,8000688c <_ldtoa_r+0x2ac> +80006870: b04ff0ef jal ra,80005b74 +80006874: 09810613 addi a2,sp,152 80006878: 00090693 mv a3,s2 8000687c: 00060593 mv a1,a2 -80006880: 00040513 mv a0,s0 -80006884: bb4ff0ef jal ra,80005c38 -80006888: 08c11783 lh a5,140(sp) -8000688c: fff48493 addi s1,s1,-1 -80006890: fe07d2e3 bgez a5,80006874 <_ldtoa_r+0x1d0> -80006894: 0d010413 addi s0,sp,208 -80006898: 0e810b93 addi s7,sp,232 -8000689c: 00040713 mv a4,s0 -800068a0: 07c10793 addi a5,sp,124 -800068a4: 09010613 addi a2,sp,144 -800068a8: 0007d683 lhu a3,0(a5) -800068ac: 00278793 addi a5,a5,2 -800068b0: 00270713 addi a4,a4,2 -800068b4: fed71f23 sh a3,-2(a4) -800068b8: fec798e3 bne a5,a2,800068a8 <_ldtoa_r+0x204> -800068bc: 00000693 li a3,0 -800068c0: 09810793 addi a5,sp,152 -800068c4: 000c0713 mv a4,s8 -800068c8: 0080006f j 800068d0 <_ldtoa_r+0x22c> -800068cc: 00075683 lhu a3,0(a4) -800068d0: 00278793 addi a5,a5,2 -800068d4: fed79f23 sh a3,-2(a5) -800068d8: 00270713 addi a4,a4,2 -800068dc: ffa798e3 bne a5,s10,800068cc <_ldtoa_r+0x228> -800068e0: 028d8c93 addi s9,s11,40 -800068e4: 12cd8d13 addi s10,s11,300 -800068e8: fffffab7 lui s5,0xfffff -800068ec: 118d8d93 addi s11,s11,280 -800068f0: 00c0006f j 800068fc <_ldtoa_r+0x258> -800068f4: 014d0d13 addi s10,s10,20 -800068f8: 014c8c93 addi s9,s9,20 -800068fc: 00040593 mv a1,s0 -80006900: 000c0513 mv a0,s8 -80006904: 841fe0ef jal ra,80005144 -80006908: 00050793 mv a5,a0 +80006880: 000c8513 mv a0,s9 +80006884: af0ff0ef jal ra,80005b74 +80006888: 015484b3 add s1,s1,s5 +8000688c: 01fad793 srli a5,s5,0x1f +80006890: 015787b3 add a5,a5,s5 +80006894: 4017da93 srai s5,a5,0x1 +80006898: f9bc9ce3 bne s9,s11,80006830 <_ldtoa_r+0x250> +8000689c: 09810613 addi a2,sp,152 +800068a0: 00090693 mv a3,s2 +800068a4: 000c0593 mv a1,s8 +800068a8: 00060513 mv a0,a2 +800068ac: ee0ff0ef jal ra,80005f8c +800068b0: 12410a93 addi s5,sp,292 +800068b4: 0300006f j 800068e4 <_ldtoa_r+0x304> +800068b8: 07c10793 addi a5,sp,124 +800068bc: 08e10693 addi a3,sp,142 +800068c0: 0007d703 lhu a4,0(a5) +800068c4: 00278793 addi a5,a5,2 +800068c8: ea071ce3 bnez a4,80006780 <_ldtoa_r+0x1a0> +800068cc: fed79ae3 bne a5,a3,800068c0 <_ldtoa_r+0x2e0> +800068d0: 00000493 li s1,0 +800068d4: 12410a93 addi s5,sp,292 +800068d8: 16010913 addi s2,sp,352 +800068dc: 0d010413 addi s0,sp,208 +800068e0: 0e810b93 addi s7,sp,232 +800068e4: 00040593 mv a1,s0 +800068e8: 09810513 addi a0,sp,152 +800068ec: e9cfe0ef jal ra,80004f88 +800068f0: 09810713 addi a4,sp,152 +800068f4: 00040793 mv a5,s0 +800068f8: 0007d683 lhu a3,0(a5) +800068fc: 00278793 addi a5,a5,2 +80006900: 00270713 addi a4,a4,2 +80006904: fed71f23 sh a3,-2(a4) +80006908: ff7798e3 bne a5,s7,800068f8 <_ldtoa_r+0x318> 8000690c: 00040593 mv a1,s0 -80006910: 000d0513 mv a0,s10 -80006914: 04f05663 blez a5,80006960 <_ldtoa_r+0x2bc> -80006918: 82dfe0ef jal ra,80005144 -8000691c: 00050793 mv a5,a0 -80006920: 00090693 mv a3,s2 -80006924: 00040613 mv a2,s0 -80006928: 00040593 mv a1,s0 -8000692c: 000c8513 mv a0,s9 -80006930: 0207c063 bltz a5,80006950 <_ldtoa_r+0x2ac> -80006934: b04ff0ef jal ra,80005c38 -80006938: 09810613 addi a2,sp,152 -8000693c: 00090693 mv a3,s2 -80006940: 00060593 mv a1,a2 -80006944: 000c8513 mv a0,s9 -80006948: af0ff0ef jal ra,80005c38 -8000694c: 015484b3 add s1,s1,s5 -80006950: 01fad793 srli a5,s5,0x1f -80006954: 015787b3 add a5,a5,s5 -80006958: 4017da93 srai s5,a5,0x1 -8000695c: f9bc9ce3 bne s9,s11,800068f4 <_ldtoa_r+0x250> -80006960: 09810613 addi a2,sp,152 -80006964: 00090693 mv a3,s2 -80006968: 000c0593 mv a1,s8 -8000696c: 00060513 mv a0,a2 -80006970: ee0ff0ef jal ra,80006050 -80006974: 12410a93 addi s5,sp,292 -80006978: 0300006f j 800069a8 <_ldtoa_r+0x304> -8000697c: 07c10793 addi a5,sp,124 -80006980: 08e10693 addi a3,sp,142 -80006984: 0007d703 lhu a4,0(a5) -80006988: 00278793 addi a5,a5,2 -8000698c: ea071ce3 bnez a4,80006844 <_ldtoa_r+0x1a0> -80006990: fed79ae3 bne a5,a3,80006984 <_ldtoa_r+0x2e0> -80006994: 00000493 li s1,0 -80006998: 12410a93 addi s5,sp,292 -8000699c: 16010913 addi s2,sp,352 -800069a0: 0d010413 addi s0,sp,208 -800069a4: 0e810b93 addi s7,sp,232 -800069a8: 00040593 mv a1,s0 -800069ac: 09810513 addi a0,sp,152 -800069b0: e9cfe0ef jal ra,8000504c -800069b4: 09810713 addi a4,sp,152 -800069b8: 00040793 mv a5,s0 -800069bc: 0007d683 lhu a3,0(a5) -800069c0: 00278793 addi a5,a5,2 -800069c4: 00270713 addi a4,a4,2 -800069c8: fed71f23 sh a3,-2(a4) -800069cc: ff7798e3 bne a5,s7,800069bc <_ldtoa_r+0x318> -800069d0: 00040593 mv a1,s0 -800069d4: 07c10513 addi a0,sp,124 -800069d8: 0a011823 sh zero,176(sp) -800069dc: e70fe0ef jal ra,8000504c -800069e0: 07c10793 addi a5,sp,124 -800069e4: 00045703 lhu a4,0(s0) -800069e8: 00240413 addi s0,s0,2 -800069ec: 00278793 addi a5,a5,2 -800069f0: fee79f23 sh a4,-2(a5) -800069f4: ff7418e3 bne s0,s7,800069e4 <_ldtoa_r+0x340> -800069f8: 09810513 addi a0,sp,152 -800069fc: 00090613 mv a2,s2 -80006a00: 07c10593 addi a1,sp,124 -80006a04: 08011a23 sh zero,148(sp) -80006a08: 818ff0ef jal ra,80005a20 -80006a0c: 1ac15503 lhu a0,428(sp) -80006a10: 1c051463 bnez a0,80006bd8 <_ldtoa_r+0x534> -80006a14: 09410c93 addi s9,sp,148 -80006a18: 07e10413 addi s0,sp,126 -80006a1c: 0b610c13 addi s8,sp,182 -80006a20: e60b0593 addi a1,s6,-416 -80006a24: 07c10513 addi a0,sp,124 -80006a28: f1cfe0ef jal ra,80005144 -80006a2c: 1a050663 beqz a0,80006bd8 <_ldtoa_r+0x534> -80006a30: 00000713 li a4,0 -80006a34: 000c8693 mv a3,s9 -80006a38: 01c0006f j 80006a54 <_ldtoa_r+0x3b0> -80006a3c: 00171713 slli a4,a4,0x1 -80006a40: 00f69023 sh a5,0(a3) -80006a44: 01071713 slli a4,a4,0x10 -80006a48: ffe68693 addi a3,a3,-2 -80006a4c: 01075713 srli a4,a4,0x10 -80006a50: 04868463 beq a3,s0,80006a98 <_ldtoa_r+0x3f4> -80006a54: 0006d783 lhu a5,0(a3) -80006a58: 01079613 slli a2,a5,0x10 -80006a5c: 41065613 srai a2,a2,0x10 -80006a60: 00179793 slli a5,a5,0x1 -80006a64: 00065463 bgez a2,80006a6c <_ldtoa_r+0x3c8> -80006a68: 00176713 ori a4,a4,1 -80006a6c: 01079793 slli a5,a5,0x10 -80006a70: 0107d793 srli a5,a5,0x10 -80006a74: 00277613 andi a2,a4,2 -80006a78: 0017e593 ori a1,a5,1 -80006a7c: fc0600e3 beqz a2,80006a3c <_ldtoa_r+0x398> -80006a80: 00171713 slli a4,a4,0x1 -80006a84: 00b69023 sh a1,0(a3) -80006a88: 01071713 slli a4,a4,0x10 -80006a8c: ffe68693 addi a3,a3,-2 -80006a90: 01075713 srli a4,a4,0x10 -80006a94: fc8690e3 bne a3,s0,80006a54 <_ldtoa_r+0x3b0> -80006a98: 0b410713 addi a4,sp,180 -80006a9c: 07c10793 addi a5,sp,124 -80006aa0: 0007d683 lhu a3,0(a5) -80006aa4: 00278793 addi a5,a5,2 -80006aa8: 00270713 addi a4,a4,2 -80006aac: fed71f23 sh a3,-2(a4) -80006ab0: ff9798e3 bne a5,s9,80006aa0 <_ldtoa_r+0x3fc> -80006ab4: 0c011623 sh zero,204(sp) -80006ab8: 00000713 li a4,0 -80006abc: 0cc10693 addi a3,sp,204 -80006ac0: 01c0006f j 80006adc <_ldtoa_r+0x438> -80006ac4: 00171713 slli a4,a4,0x1 -80006ac8: 00f69023 sh a5,0(a3) -80006acc: 01071713 slli a4,a4,0x10 -80006ad0: ffe68693 addi a3,a3,-2 -80006ad4: 01075713 srli a4,a4,0x10 -80006ad8: 05868463 beq a3,s8,80006b20 <_ldtoa_r+0x47c> -80006adc: 0006d783 lhu a5,0(a3) -80006ae0: 01079613 slli a2,a5,0x10 -80006ae4: 41065613 srai a2,a2,0x10 -80006ae8: 00179793 slli a5,a5,0x1 -80006aec: 00065463 bgez a2,80006af4 <_ldtoa_r+0x450> -80006af0: 00176713 ori a4,a4,1 -80006af4: 01079793 slli a5,a5,0x10 -80006af8: 0107d793 srli a5,a5,0x10 -80006afc: 00277613 andi a2,a4,2 -80006b00: 0017e593 ori a1,a5,1 -80006b04: fc0600e3 beqz a2,80006ac4 <_ldtoa_r+0x420> -80006b08: 00171713 slli a4,a4,0x1 -80006b0c: 00b69023 sh a1,0(a3) -80006b10: 01071713 slli a4,a4,0x10 -80006b14: ffe68693 addi a3,a3,-2 -80006b18: 01075713 srli a4,a4,0x10 -80006b1c: fd8690e3 bne a3,s8,80006adc <_ldtoa_r+0x438> -80006b20: 00000713 li a4,0 -80006b24: 0cc10693 addi a3,sp,204 -80006b28: 01c0006f j 80006b44 <_ldtoa_r+0x4a0> -80006b2c: 00171713 slli a4,a4,0x1 -80006b30: 00f69023 sh a5,0(a3) -80006b34: 01071713 slli a4,a4,0x10 -80006b38: ffe68693 addi a3,a3,-2 -80006b3c: 01075713 srli a4,a4,0x10 -80006b40: 05868463 beq a3,s8,80006b88 <_ldtoa_r+0x4e4> -80006b44: 0006d783 lhu a5,0(a3) -80006b48: 01079613 slli a2,a5,0x10 -80006b4c: 41065613 srai a2,a2,0x10 -80006b50: 00179793 slli a5,a5,0x1 -80006b54: 00065463 bgez a2,80006b5c <_ldtoa_r+0x4b8> -80006b58: 00176713 ori a4,a4,1 -80006b5c: 01079793 slli a5,a5,0x10 -80006b60: 0107d793 srli a5,a5,0x10 -80006b64: 00277613 andi a2,a4,2 -80006b68: 0017e593 ori a1,a5,1 -80006b6c: fc0600e3 beqz a2,80006b2c <_ldtoa_r+0x488> -80006b70: 00171713 slli a4,a4,0x1 -80006b74: 00b69023 sh a1,0(a3) -80006b78: 01071713 slli a4,a4,0x10 -80006b7c: ffe68693 addi a3,a3,-2 -80006b80: 01075713 srli a4,a4,0x10 -80006b84: fd8690e3 bne a3,s8,80006b44 <_ldtoa_r+0x4a0> -80006b88: 00000613 li a2,0 -80006b8c: 000c8693 mv a3,s9 -80006b90: 0cc10713 addi a4,sp,204 -80006b94: 0006d583 lhu a1,0(a3) -80006b98: 00075783 lhu a5,0(a4) -80006b9c: ffe68693 addi a3,a3,-2 -80006ba0: ffe70713 addi a4,a4,-2 -80006ba4: 00b787b3 add a5,a5,a1 -80006ba8: 00c787b3 add a5,a5,a2 -80006bac: 0107d613 srli a2,a5,0x10 -80006bb0: 00f69123 sh a5,2(a3) -80006bb4: 00167613 andi a2,a2,1 -80006bb8: fd871ee3 bne a4,s8,80006b94 <_ldtoa_r+0x4f0> -80006bbc: 09810513 addi a0,sp,152 -80006bc0: 00090613 mv a2,s2 -80006bc4: 07c10593 addi a1,sp,124 -80006bc8: e59fe0ef jal ra,80005a20 -80006bcc: 1ac15503 lhu a0,428(sp) -80006bd0: fff48493 addi s1,s1,-1 -80006bd4: e40506e3 beqz a0,80006a20 <_ldtoa_r+0x37c> -80006bd8: 01012783 lw a5,16(sp) -80006bdc: 00012683 lw a3,0(sp) -80006be0: 00300713 li a4,3 -80006be4: 00f037b3 snez a5,a5 -80006be8: 40f007b3 neg a5,a5 -80006bec: 00d7f793 andi a5,a5,13 -80006bf0: 02078793 addi a5,a5,32 -80006bf4: 12f10223 sb a5,292(sp) -80006bf8: 00412783 lw a5,4(sp) -80006bfc: 00e69463 bne a3,a4,80006c04 <_ldtoa_r+0x560> -80006c00: 009787b3 add a5,a5,s1 -80006c04: 02a00713 li a4,42 -80006c08: 00078413 mv s0,a5 -80006c0c: 00f75463 bge a4,a5,80006c14 <_ldtoa_r+0x570> -80006c10: 02a00413 li s0,42 -80006c14: 00a00713 li a4,10 -80006c18: 4ee50263 beq a0,a4,800070fc <_ldtoa_r+0xa58> -80006c1c: 03050513 addi a0,a0,48 -80006c20: 02e00713 li a4,46 -80006c24: 12a102a3 sb a0,293(sp) -80006c28: 12e10323 sb a4,294(sp) -80006c2c: 1e07c2e3 bltz a5,80007610 <_ldtoa_r+0xf6c> -80006c30: 12710793 addi a5,sp,295 -80006c34: 00f12823 sw a5,16(sp) -80006c38: 00000c13 li s8,0 -80006c3c: 00912e23 sw s1,28(sp) -80006c40: 000c0493 mv s1,s8 -80006c44: 00090c13 mv s8,s2 -80006c48: 01012903 lw s2,16(sp) -80006c4c: 0b410c93 addi s9,sp,180 -80006c50: 09410d93 addi s11,sp,148 -80006c54: 07e10b93 addi s7,sp,126 -80006c58: 0b610d13 addi s10,sp,182 -80006c5c: 00000713 li a4,0 -80006c60: 000d8613 mv a2,s11 -80006c64: 01c0006f j 80006c80 <_ldtoa_r+0x5dc> -80006c68: 00171713 slli a4,a4,0x1 -80006c6c: 00f61023 sh a5,0(a2) # 8000 <_start-0x7fff8000> -80006c70: 01071713 slli a4,a4,0x10 -80006c74: ffe60613 addi a2,a2,-2 -80006c78: 01075713 srli a4,a4,0x10 -80006c7c: 05760463 beq a2,s7,80006cc4 <_ldtoa_r+0x620> -80006c80: 00065783 lhu a5,0(a2) -80006c84: 01079593 slli a1,a5,0x10 -80006c88: 4105d593 srai a1,a1,0x10 -80006c8c: 00179793 slli a5,a5,0x1 -80006c90: 0005d463 bgez a1,80006c98 <_ldtoa_r+0x5f4> -80006c94: 00176713 ori a4,a4,1 -80006c98: 01079793 slli a5,a5,0x10 -80006c9c: 0107d793 srli a5,a5,0x10 -80006ca0: 00277593 andi a1,a4,2 -80006ca4: 0017e513 ori a0,a5,1 -80006ca8: fc0580e3 beqz a1,80006c68 <_ldtoa_r+0x5c4> -80006cac: 00171713 slli a4,a4,0x1 -80006cb0: 00a61023 sh a0,0(a2) -80006cb4: 01071713 slli a4,a4,0x10 -80006cb8: ffe60613 addi a2,a2,-2 -80006cbc: 01075713 srli a4,a4,0x10 -80006cc0: fd7610e3 bne a2,s7,80006c80 <_ldtoa_r+0x5dc> -80006cc4: 000c8713 mv a4,s9 -80006cc8: 07c10793 addi a5,sp,124 -80006ccc: 0007d603 lhu a2,0(a5) -80006cd0: 00278793 addi a5,a5,2 -80006cd4: 00270713 addi a4,a4,2 -80006cd8: fec71f23 sh a2,-2(a4) -80006cdc: ffb798e3 bne a5,s11,80006ccc <_ldtoa_r+0x628> -80006ce0: 0c011623 sh zero,204(sp) -80006ce4: 00000713 li a4,0 -80006ce8: 0cc10613 addi a2,sp,204 -80006cec: 01c0006f j 80006d08 <_ldtoa_r+0x664> -80006cf0: 00171713 slli a4,a4,0x1 -80006cf4: 00f61023 sh a5,0(a2) -80006cf8: 01071713 slli a4,a4,0x10 -80006cfc: ffe60613 addi a2,a2,-2 -80006d00: 01075713 srli a4,a4,0x10 -80006d04: 05a60463 beq a2,s10,80006d4c <_ldtoa_r+0x6a8> -80006d08: 00065783 lhu a5,0(a2) -80006d0c: 01079593 slli a1,a5,0x10 -80006d10: 4105d593 srai a1,a1,0x10 -80006d14: 00179793 slli a5,a5,0x1 -80006d18: 0005d463 bgez a1,80006d20 <_ldtoa_r+0x67c> -80006d1c: 00176713 ori a4,a4,1 -80006d20: 01079793 slli a5,a5,0x10 -80006d24: 0107d793 srli a5,a5,0x10 -80006d28: 00277593 andi a1,a4,2 -80006d2c: 0017e513 ori a0,a5,1 -80006d30: fc0580e3 beqz a1,80006cf0 <_ldtoa_r+0x64c> -80006d34: 00171713 slli a4,a4,0x1 -80006d38: 00a61023 sh a0,0(a2) -80006d3c: 01071713 slli a4,a4,0x10 -80006d40: ffe60613 addi a2,a2,-2 -80006d44: 01075713 srli a4,a4,0x10 -80006d48: fda610e3 bne a2,s10,80006d08 <_ldtoa_r+0x664> -80006d4c: 00000713 li a4,0 -80006d50: 0cc10613 addi a2,sp,204 -80006d54: 01c0006f j 80006d70 <_ldtoa_r+0x6cc> -80006d58: 00171713 slli a4,a4,0x1 -80006d5c: 00f61023 sh a5,0(a2) -80006d60: 01071713 slli a4,a4,0x10 -80006d64: ffe60613 addi a2,a2,-2 -80006d68: 01075713 srli a4,a4,0x10 -80006d6c: 05a60463 beq a2,s10,80006db4 <_ldtoa_r+0x710> -80006d70: 00065783 lhu a5,0(a2) -80006d74: 01079593 slli a1,a5,0x10 -80006d78: 4105d593 srai a1,a1,0x10 -80006d7c: 00179793 slli a5,a5,0x1 -80006d80: 0005d463 bgez a1,80006d88 <_ldtoa_r+0x6e4> -80006d84: 00176713 ori a4,a4,1 -80006d88: 01079793 slli a5,a5,0x10 -80006d8c: 0107d793 srli a5,a5,0x10 -80006d90: 00277593 andi a1,a4,2 -80006d94: 0017e513 ori a0,a5,1 -80006d98: fc0580e3 beqz a1,80006d58 <_ldtoa_r+0x6b4> -80006d9c: 00171713 slli a4,a4,0x1 -80006da0: 00a61023 sh a0,0(a2) -80006da4: 01071713 slli a4,a4,0x10 -80006da8: ffe60613 addi a2,a2,-2 -80006dac: 01075713 srli a4,a4,0x10 -80006db0: fda610e3 bne a2,s10,80006d70 <_ldtoa_r+0x6cc> -80006db4: 00000593 li a1,0 -80006db8: 000d8613 mv a2,s11 -80006dbc: 0cc10713 addi a4,sp,204 -80006dc0: 00065503 lhu a0,0(a2) -80006dc4: 00075783 lhu a5,0(a4) -80006dc8: ffe60613 addi a2,a2,-2 -80006dcc: ffe70713 addi a4,a4,-2 -80006dd0: 00a787b3 add a5,a5,a0 -80006dd4: 00b787b3 add a5,a5,a1 -80006dd8: 0107d593 srli a1,a5,0x10 -80006ddc: 00f61123 sh a5,2(a2) -80006de0: 0015f593 andi a1,a1,1 -80006de4: fda71ee3 bne a4,s10,80006dc0 <_ldtoa_r+0x71c> -80006de8: 000c0613 mv a2,s8 -80006dec: 07c10593 addi a1,sp,124 -80006df0: 09810513 addi a0,sp,152 -80006df4: c2dfe0ef jal ra,80005a20 -80006df8: 1ac15783 lhu a5,428(sp) -80006dfc: 00990733 add a4,s2,s1 -80006e00: 00148493 addi s1,s1,1 -80006e04: 03078613 addi a2,a5,48 -80006e08: 00c70023 sb a2,0(a4) -80006e0c: e49458e3 bge s0,s1,80006c5c <_ldtoa_r+0x5b8> -80006e10: fff44513 not a0,s0 -80006e14: 01012703 lw a4,16(sp) -80006e18: 41f55513 srai a0,a0,0x1f -80006e1c: 00a47533 and a0,s0,a0 -80006e20: 01c12483 lw s1,28(sp) -80006e24: 00150913 addi s2,a0,1 -80006e28: 01270933 add s2,a4,s2 -80006e2c: 00a70c33 add s8,a4,a0 -80006e30: 00400713 li a4,4 -80006e34: 04f75e63 bge a4,a5,80006e90 <_ldtoa_r+0x7ec> -80006e38: 00500713 li a4,5 -80006e3c: 00e780e3 beq a5,a4,8000763c <_ldtoa_r+0xf98> -80006e40: ffe94783 lbu a5,-2(s2) -80006e44: ffe90713 addi a4,s2,-2 -80006e48: 07f7f793 andi a5,a5,127 -80006e4c: 78044463 bltz s0,800075d4 <_ldtoa_r+0xf30> -80006e50: 02e00693 li a3,46 -80006e54: 03800613 li a2,56 -80006e58: 03000593 li a1,48 -80006e5c: 00d78e63 beq a5,a3,80006e78 <_ldtoa_r+0x7d4> -80006e60: 78f65263 bge a2,a5,800075e4 <_ldtoa_r+0xf40> -80006e64: fff74783 lbu a5,-1(a4) -80006e68: 00b70023 sb a1,0(a4) -80006e6c: fff70713 addi a4,a4,-1 -80006e70: 07f7f793 andi a5,a5,127 -80006e74: fe9ff06f j 80006e5c <_ldtoa_r+0x7b8> -80006e78: fff74783 lbu a5,-1(a4) -80006e7c: 03800693 li a3,56 -80006e80: 00f6f4e3 bgeu a3,a5,80007688 <_ldtoa_r+0xfe4> -80006e84: 03100793 li a5,49 -80006e88: 00148493 addi s1,s1,1 -80006e8c: fef70fa3 sb a5,-1(a4) -80006e90: 800155b7 lui a1,0x80015 -80006e94: 00048613 mv a2,s1 -80006e98: e5c58593 addi a1,a1,-420 # 80014e5c <__BSS_END__+0xffffe220> -80006e9c: 000c0513 mv a0,s8 -80006ea0: 03d020ef jal ra,800096dc -80006ea4: 07215783 lhu a5,114(sp) -80006ea8: 01412703 lw a4,20(sp) -80006eac: 16912823 sw s1,368(sp) -80006eb0: fff7c793 not a5,a5 -80006eb4: 16e12223 sw a4,356(sp) -80006eb8: 01179713 slli a4,a5,0x11 -80006ebc: 00071e63 bnez a4,80006ed8 <_ldtoa_r+0x834> -80006ec0: 00098513 mv a0,s3 -80006ec4: b9cfe0ef jal ra,80005260 -80006ec8: 22051063 bnez a0,800070e8 <_ldtoa_r+0xa44> -80006ecc: 00098513 mv a0,s3 -80006ed0: 8ccfe0ef jal ra,80004f9c -80006ed4: 20051a63 bnez a0,800070e8 <_ldtoa_r+0xa44> -80006ed8: 00c12683 lw a3,12(sp) -80006edc: 12414703 lbu a4,292(sp) -80006ee0: 00148793 addi a5,s1,1 -80006ee4: 00f6a023 sw a5,0(a3) -80006ee8: 000a8793 mv a5,s5 -80006eec: 02070a63 beqz a4,80006f20 <_ldtoa_r+0x87c> -80006ef0: 02e00693 li a3,46 -80006ef4: 1cd70c63 beq a4,a3,800070cc <_ldtoa_r+0xa28> -80006ef8: 0017c703 lbu a4,1(a5) -80006efc: 00178793 addi a5,a5,1 -80006f00: fe071ae3 bnez a4,80006ef4 <_ldtoa_r+0x850> -80006f04: 04500693 li a3,69 -80006f08: 00fae663 bltu s5,a5,80006f14 <_ldtoa_r+0x870> -80006f0c: 0140006f j 80006f20 <_ldtoa_r+0x87c> -80006f10: 01578863 beq a5,s5,80006f20 <_ldtoa_r+0x87c> -80006f14: fff7c703 lbu a4,-1(a5) -80006f18: fff78793 addi a5,a5,-1 -80006f1c: fed71ae3 bne a4,a3,80006f10 <_ldtoa_r+0x86c> -80006f20: 00078023 sb zero,0(a5) -80006f24: 000a8793 mv a5,s5 -80006f28: 02000693 li a3,32 -80006f2c: 02d00613 li a2,45 -80006f30: 0007c703 lbu a4,0(a5) -80006f34: 00d70463 beq a4,a3,80006f3c <_ldtoa_r+0x898> -80006f38: 00c71663 bne a4,a2,80006f44 <_ldtoa_r+0x8a0> -80006f3c: 00178793 addi a5,a5,1 -80006f40: ff1ff06f j 80006f30 <_ldtoa_r+0x88c> -80006f44: 000a8413 mv s0,s5 -80006f48: 00c0006f j 80006f54 <_ldtoa_r+0x8b0> -80006f4c: 0007c703 lbu a4,0(a5) -80006f50: 00068413 mv s0,a3 -80006f54: 00e40023 sb a4,0(s0) -80006f58: 00140693 addi a3,s0,1 -80006f5c: 00178793 addi a5,a5,1 -80006f60: fe0716e3 bnez a4,80006f4c <_ldtoa_r+0x8a8> -80006f64: 00012683 lw a3,0(sp) -80006f68: 00200793 li a5,2 -80006f6c: fff44703 lbu a4,-1(s0) -80006f70: 12f68663 beq a3,a5,8000709c <_ldtoa_r+0x9f8> -80006f74: 00412783 lw a5,4(sp) -80006f78: 00078693 mv a3,a5 -80006f7c: 0097d463 bge a5,s1,80006f84 <_ldtoa_r+0x8e0> -80006f80: 00048693 mv a3,s1 -80006f84: 03000793 li a5,48 -80006f88: 02f71663 bne a4,a5,80006fb4 <_ldtoa_r+0x910> -80006f8c: 415407b3 sub a5,s0,s5 -80006f90: 02f6d263 bge a3,a5,80006fb4 <_ldtoa_r+0x910> -80006f94: 03000613 li a2,48 -80006f98: 0080006f j 80006fa0 <_ldtoa_r+0x8fc> -80006f9c: 00e6dc63 bge a3,a4,80006fb4 <_ldtoa_r+0x910> -80006fa0: ffe44783 lbu a5,-2(s0) -80006fa4: fe040fa3 sb zero,-1(s0) -80006fa8: fff40413 addi s0,s0,-1 -80006fac: 41540733 sub a4,s0,s5 -80006fb0: fec786e3 beq a5,a2,80006f9c <_ldtoa_r+0x8f8> -80006fb4: 00012703 lw a4,0(sp) -80006fb8: 00300793 li a5,3 -80006fbc: 0af70263 beq a4,a5,80007060 <_ldtoa_r+0x9bc> -80006fc0: 00812783 lw a5,8(sp) -80006fc4: 040a2223 sw zero,68(s4) -80006fc8: 00978693 addi a3,a5,9 -80006fcc: 01700793 li a5,23 -80006fd0: 0cd7f263 bgeu a5,a3,80007094 <_ldtoa_r+0x9f0> -80006fd4: 00100713 li a4,1 -80006fd8: 00400793 li a5,4 -80006fdc: 00179793 slli a5,a5,0x1 -80006fe0: 01478613 addi a2,a5,20 -80006fe4: 00070593 mv a1,a4 -80006fe8: 00170713 addi a4,a4,1 -80006fec: fec6f8e3 bgeu a3,a2,80006fdc <_ldtoa_r+0x938> -80006ff0: 04ba2223 sw a1,68(s4) -80006ff4: 000a0513 mv a0,s4 -80006ff8: 500010ef jal ra,800084f8 <_Balloc> -80006ffc: 04aa2023 sw a0,64(s4) -80007000: 000a8593 mv a1,s5 -80007004: 00050493 mv s1,a0 -80007008: 0a9020ef jal ra,800098b0 -8000700c: 01812783 lw a5,24(sp) -80007010: 00078863 beqz a5,80007020 <_ldtoa_r+0x97c> -80007014: 41540433 sub s0,s0,s5 -80007018: 00848433 add s0,s1,s0 -8000701c: 0087a023 sw s0,0(a5) -80007020: 1ec12083 lw ra,492(sp) -80007024: 1e812403 lw s0,488(sp) -80007028: 1e012903 lw s2,480(sp) -8000702c: 1dc12983 lw s3,476(sp) -80007030: 1d812a03 lw s4,472(sp) -80007034: 1d412a83 lw s5,468(sp) -80007038: 1d012b03 lw s6,464(sp) -8000703c: 1cc12b83 lw s7,460(sp) -80007040: 1c812c03 lw s8,456(sp) -80007044: 1c412c83 lw s9,452(sp) -80007048: 1c012d03 lw s10,448(sp) -8000704c: 1bc12d83 lw s11,444(sp) -80007050: 00048513 mv a0,s1 -80007054: 1e412483 lw s1,484(sp) -80007058: 1f010113 addi sp,sp,496 -8000705c: 00008067 ret -80007060: 00412783 lw a5,4(sp) -80007064: 009784b3 add s1,a5,s1 -80007068: 5004c863 bltz s1,80007578 <_ldtoa_r+0xed4> -8000706c: 00c12783 lw a5,12(sp) -80007070: 00812703 lw a4,8(sp) -80007074: 0007a783 lw a5,0(a5) -80007078: 00f707b3 add a5,a4,a5 -8000707c: 00f12423 sw a5,8(sp) -80007080: 00812783 lw a5,8(sp) -80007084: 040a2223 sw zero,68(s4) -80007088: 00378693 addi a3,a5,3 -8000708c: 01700793 li a5,23 -80007090: f4d7e2e3 bltu a5,a3,80006fd4 <_ldtoa_r+0x930> -80007094: 00000593 li a1,0 -80007098: f5dff06f j 80006ff4 <_ldtoa_r+0x950> -8000709c: 03000793 li a5,48 -800070a0: f2f710e3 bne a4,a5,80006fc0 <_ldtoa_r+0x91c> -800070a4: 415407b3 sub a5,s0,s5 -800070a8: 00100693 li a3,1 -800070ac: eef6c4e3 blt a3,a5,80006f94 <_ldtoa_r+0x8f0> -800070b0: f11ff06f j 80006fc0 <_ldtoa_r+0x91c> -800070b4: 00812483 lw s1,8(sp) -800070b8: 00912223 sw s1,4(sp) -800070bc: 02a00793 li a5,42 -800070c0: ec97d063 bge a5,s1,80006780 <_ldtoa_r+0xdc> -800070c4: 00f12223 sw a5,4(sp) -800070c8: eb8ff06f j 80006780 <_ldtoa_r+0xdc> -800070cc: 0007c703 lbu a4,0(a5) -800070d0: e2070ae3 beqz a4,80006f04 <_ldtoa_r+0x860> -800070d4: 0017c703 lbu a4,1(a5) -800070d8: 00178793 addi a5,a5,1 -800070dc: fee78fa3 sb a4,-1(a5) -800070e0: fe071ae3 bnez a4,800070d4 <_ldtoa_r+0xa30> -800070e4: e21ff06f j 80006f04 <_ldtoa_r+0x860> -800070e8: 00c12703 lw a4,12(sp) -800070ec: 000027b7 lui a5,0x2 -800070f0: 70f78793 addi a5,a5,1807 # 270f <_start-0x7fffd8f1> -800070f4: 00f72023 sw a5,0(a4) -800070f8: e2dff06f j 80006f24 <_ldtoa_r+0x880> -800070fc: 03100713 li a4,49 -80007100: 12e102a3 sb a4,293(sp) -80007104: 02e00713 li a4,46 -80007108: 12e10323 sb a4,294(sp) -8000710c: 00148493 addi s1,s1,1 -80007110: 2af05c63 blez a5,800073c8 <_ldtoa_r+0xd24> -80007114: 03000793 li a5,48 -80007118: 12f103a3 sb a5,295(sp) -8000711c: 12810793 addi a5,sp,296 -80007120: fff40413 addi s0,s0,-1 -80007124: 00f12823 sw a5,16(sp) -80007128: b11ff06f j 80006c38 <_ldtoa_r+0x594> -8000712c: 0b410c93 addi s9,sp,180 -80007130: 000c8713 mv a4,s9 -80007134: 07c10793 addi a5,sp,124 -80007138: 09010613 addi a2,sp,144 +80006910: 07c10513 addi a0,sp,124 +80006914: 0a011823 sh zero,176(sp) +80006918: e70fe0ef jal ra,80004f88 +8000691c: 07c10793 addi a5,sp,124 +80006920: 00045703 lhu a4,0(s0) +80006924: 00240413 addi s0,s0,2 +80006928: 00278793 addi a5,a5,2 +8000692c: fee79f23 sh a4,-2(a5) +80006930: ff7418e3 bne s0,s7,80006920 <_ldtoa_r+0x340> +80006934: 09810513 addi a0,sp,152 +80006938: 00090613 mv a2,s2 +8000693c: 07c10593 addi a1,sp,124 +80006940: 08011a23 sh zero,148(sp) +80006944: 818ff0ef jal ra,8000595c +80006948: 1ac15503 lhu a0,428(sp) +8000694c: 1c051463 bnez a0,80006b14 <_ldtoa_r+0x534> +80006950: 09410c93 addi s9,sp,148 +80006954: 07e10413 addi s0,sp,126 +80006958: 0b610c13 addi s8,sp,182 +8000695c: d8cb0593 addi a1,s6,-628 +80006960: 07c10513 addi a0,sp,124 +80006964: f1cfe0ef jal ra,80005080 +80006968: 1a050663 beqz a0,80006b14 <_ldtoa_r+0x534> +8000696c: 00000713 li a4,0 +80006970: 000c8693 mv a3,s9 +80006974: 01c0006f j 80006990 <_ldtoa_r+0x3b0> +80006978: 00171713 slli a4,a4,0x1 +8000697c: 00f69023 sh a5,0(a3) +80006980: 01071713 slli a4,a4,0x10 +80006984: ffe68693 addi a3,a3,-2 +80006988: 01075713 srli a4,a4,0x10 +8000698c: 04868463 beq a3,s0,800069d4 <_ldtoa_r+0x3f4> +80006990: 0006d783 lhu a5,0(a3) +80006994: 01079613 slli a2,a5,0x10 +80006998: 41065613 srai a2,a2,0x10 +8000699c: 00179793 slli a5,a5,0x1 +800069a0: 00065463 bgez a2,800069a8 <_ldtoa_r+0x3c8> +800069a4: 00176713 ori a4,a4,1 +800069a8: 01079793 slli a5,a5,0x10 +800069ac: 0107d793 srli a5,a5,0x10 +800069b0: 00277613 andi a2,a4,2 +800069b4: 0017e593 ori a1,a5,1 +800069b8: fc0600e3 beqz a2,80006978 <_ldtoa_r+0x398> +800069bc: 00171713 slli a4,a4,0x1 +800069c0: 00b69023 sh a1,0(a3) +800069c4: 01071713 slli a4,a4,0x10 +800069c8: ffe68693 addi a3,a3,-2 +800069cc: 01075713 srli a4,a4,0x10 +800069d0: fc8690e3 bne a3,s0,80006990 <_ldtoa_r+0x3b0> +800069d4: 0b410713 addi a4,sp,180 +800069d8: 07c10793 addi a5,sp,124 +800069dc: 0007d683 lhu a3,0(a5) +800069e0: 00278793 addi a5,a5,2 +800069e4: 00270713 addi a4,a4,2 +800069e8: fed71f23 sh a3,-2(a4) +800069ec: ff9798e3 bne a5,s9,800069dc <_ldtoa_r+0x3fc> +800069f0: 0c011623 sh zero,204(sp) +800069f4: 00000713 li a4,0 +800069f8: 0cc10693 addi a3,sp,204 +800069fc: 01c0006f j 80006a18 <_ldtoa_r+0x438> +80006a00: 00171713 slli a4,a4,0x1 +80006a04: 00f69023 sh a5,0(a3) +80006a08: 01071713 slli a4,a4,0x10 +80006a0c: ffe68693 addi a3,a3,-2 +80006a10: 01075713 srli a4,a4,0x10 +80006a14: 05868463 beq a3,s8,80006a5c <_ldtoa_r+0x47c> +80006a18: 0006d783 lhu a5,0(a3) +80006a1c: 01079613 slli a2,a5,0x10 +80006a20: 41065613 srai a2,a2,0x10 +80006a24: 00179793 slli a5,a5,0x1 +80006a28: 00065463 bgez a2,80006a30 <_ldtoa_r+0x450> +80006a2c: 00176713 ori a4,a4,1 +80006a30: 01079793 slli a5,a5,0x10 +80006a34: 0107d793 srli a5,a5,0x10 +80006a38: 00277613 andi a2,a4,2 +80006a3c: 0017e593 ori a1,a5,1 +80006a40: fc0600e3 beqz a2,80006a00 <_ldtoa_r+0x420> +80006a44: 00171713 slli a4,a4,0x1 +80006a48: 00b69023 sh a1,0(a3) +80006a4c: 01071713 slli a4,a4,0x10 +80006a50: ffe68693 addi a3,a3,-2 +80006a54: 01075713 srli a4,a4,0x10 +80006a58: fd8690e3 bne a3,s8,80006a18 <_ldtoa_r+0x438> +80006a5c: 00000713 li a4,0 +80006a60: 0cc10693 addi a3,sp,204 +80006a64: 01c0006f j 80006a80 <_ldtoa_r+0x4a0> +80006a68: 00171713 slli a4,a4,0x1 +80006a6c: 00f69023 sh a5,0(a3) +80006a70: 01071713 slli a4,a4,0x10 +80006a74: ffe68693 addi a3,a3,-2 +80006a78: 01075713 srli a4,a4,0x10 +80006a7c: 05868463 beq a3,s8,80006ac4 <_ldtoa_r+0x4e4> +80006a80: 0006d783 lhu a5,0(a3) +80006a84: 01079613 slli a2,a5,0x10 +80006a88: 41065613 srai a2,a2,0x10 +80006a8c: 00179793 slli a5,a5,0x1 +80006a90: 00065463 bgez a2,80006a98 <_ldtoa_r+0x4b8> +80006a94: 00176713 ori a4,a4,1 +80006a98: 01079793 slli a5,a5,0x10 +80006a9c: 0107d793 srli a5,a5,0x10 +80006aa0: 00277613 andi a2,a4,2 +80006aa4: 0017e593 ori a1,a5,1 +80006aa8: fc0600e3 beqz a2,80006a68 <_ldtoa_r+0x488> +80006aac: 00171713 slli a4,a4,0x1 +80006ab0: 00b69023 sh a1,0(a3) +80006ab4: 01071713 slli a4,a4,0x10 +80006ab8: ffe68693 addi a3,a3,-2 +80006abc: 01075713 srli a4,a4,0x10 +80006ac0: fd8690e3 bne a3,s8,80006a80 <_ldtoa_r+0x4a0> +80006ac4: 00000613 li a2,0 +80006ac8: 000c8693 mv a3,s9 +80006acc: 0cc10713 addi a4,sp,204 +80006ad0: 0006d583 lhu a1,0(a3) +80006ad4: 00075783 lhu a5,0(a4) +80006ad8: ffe68693 addi a3,a3,-2 +80006adc: ffe70713 addi a4,a4,-2 +80006ae0: 00b787b3 add a5,a5,a1 +80006ae4: 00c787b3 add a5,a5,a2 +80006ae8: 0107d613 srli a2,a5,0x10 +80006aec: 00f69123 sh a5,2(a3) +80006af0: 00167613 andi a2,a2,1 +80006af4: fd871ee3 bne a4,s8,80006ad0 <_ldtoa_r+0x4f0> +80006af8: 09810513 addi a0,sp,152 +80006afc: 00090613 mv a2,s2 +80006b00: 07c10593 addi a1,sp,124 +80006b04: e59fe0ef jal ra,8000595c +80006b08: 1ac15503 lhu a0,428(sp) +80006b0c: fff48493 addi s1,s1,-1 +80006b10: e40506e3 beqz a0,8000695c <_ldtoa_r+0x37c> +80006b14: 01012783 lw a5,16(sp) +80006b18: 00012683 lw a3,0(sp) +80006b1c: 00300713 li a4,3 +80006b20: 00f037b3 snez a5,a5 +80006b24: 40f007b3 neg a5,a5 +80006b28: 00d7f793 andi a5,a5,13 +80006b2c: 02078793 addi a5,a5,32 +80006b30: 12f10223 sb a5,292(sp) +80006b34: 00412783 lw a5,4(sp) +80006b38: 00e69463 bne a3,a4,80006b40 <_ldtoa_r+0x560> +80006b3c: 009787b3 add a5,a5,s1 +80006b40: 02a00713 li a4,42 +80006b44: 00078413 mv s0,a5 +80006b48: 00f75463 bge a4,a5,80006b50 <_ldtoa_r+0x570> +80006b4c: 02a00413 li s0,42 +80006b50: 00a00713 li a4,10 +80006b54: 4ee50263 beq a0,a4,80007038 <_ldtoa_r+0xa58> +80006b58: 03050513 addi a0,a0,48 +80006b5c: 02e00713 li a4,46 +80006b60: 12a102a3 sb a0,293(sp) +80006b64: 12e10323 sb a4,294(sp) +80006b68: 1e07c2e3 bltz a5,8000754c <_ldtoa_r+0xf6c> +80006b6c: 12710793 addi a5,sp,295 +80006b70: 00f12823 sw a5,16(sp) +80006b74: 00000c13 li s8,0 +80006b78: 00912e23 sw s1,28(sp) +80006b7c: 000c0493 mv s1,s8 +80006b80: 00090c13 mv s8,s2 +80006b84: 01012903 lw s2,16(sp) +80006b88: 0b410c93 addi s9,sp,180 +80006b8c: 09410d93 addi s11,sp,148 +80006b90: 07e10b93 addi s7,sp,126 +80006b94: 0b610d13 addi s10,sp,182 +80006b98: 00000713 li a4,0 +80006b9c: 000d8613 mv a2,s11 +80006ba0: 01c0006f j 80006bbc <_ldtoa_r+0x5dc> +80006ba4: 00171713 slli a4,a4,0x1 +80006ba8: 00f61023 sh a5,0(a2) # 8000 <_start-0x7fff8000> +80006bac: 01071713 slli a4,a4,0x10 +80006bb0: ffe60613 addi a2,a2,-2 +80006bb4: 01075713 srli a4,a4,0x10 +80006bb8: 05760463 beq a2,s7,80006c00 <_ldtoa_r+0x620> +80006bbc: 00065783 lhu a5,0(a2) +80006bc0: 01079593 slli a1,a5,0x10 +80006bc4: 4105d593 srai a1,a1,0x10 +80006bc8: 00179793 slli a5,a5,0x1 +80006bcc: 0005d463 bgez a1,80006bd4 <_ldtoa_r+0x5f4> +80006bd0: 00176713 ori a4,a4,1 +80006bd4: 01079793 slli a5,a5,0x10 +80006bd8: 0107d793 srli a5,a5,0x10 +80006bdc: 00277593 andi a1,a4,2 +80006be0: 0017e513 ori a0,a5,1 +80006be4: fc0580e3 beqz a1,80006ba4 <_ldtoa_r+0x5c4> +80006be8: 00171713 slli a4,a4,0x1 +80006bec: 00a61023 sh a0,0(a2) +80006bf0: 01071713 slli a4,a4,0x10 +80006bf4: ffe60613 addi a2,a2,-2 +80006bf8: 01075713 srli a4,a4,0x10 +80006bfc: fd7610e3 bne a2,s7,80006bbc <_ldtoa_r+0x5dc> +80006c00: 000c8713 mv a4,s9 +80006c04: 07c10793 addi a5,sp,124 +80006c08: 0007d603 lhu a2,0(a5) +80006c0c: 00278793 addi a5,a5,2 +80006c10: 00270713 addi a4,a4,2 +80006c14: fec71f23 sh a2,-2(a4) +80006c18: ffb798e3 bne a5,s11,80006c08 <_ldtoa_r+0x628> +80006c1c: 0c011623 sh zero,204(sp) +80006c20: 00000713 li a4,0 +80006c24: 0cc10613 addi a2,sp,204 +80006c28: 01c0006f j 80006c44 <_ldtoa_r+0x664> +80006c2c: 00171713 slli a4,a4,0x1 +80006c30: 00f61023 sh a5,0(a2) +80006c34: 01071713 slli a4,a4,0x10 +80006c38: ffe60613 addi a2,a2,-2 +80006c3c: 01075713 srli a4,a4,0x10 +80006c40: 05a60463 beq a2,s10,80006c88 <_ldtoa_r+0x6a8> +80006c44: 00065783 lhu a5,0(a2) +80006c48: 01079593 slli a1,a5,0x10 +80006c4c: 4105d593 srai a1,a1,0x10 +80006c50: 00179793 slli a5,a5,0x1 +80006c54: 0005d463 bgez a1,80006c5c <_ldtoa_r+0x67c> +80006c58: 00176713 ori a4,a4,1 +80006c5c: 01079793 slli a5,a5,0x10 +80006c60: 0107d793 srli a5,a5,0x10 +80006c64: 00277593 andi a1,a4,2 +80006c68: 0017e513 ori a0,a5,1 +80006c6c: fc0580e3 beqz a1,80006c2c <_ldtoa_r+0x64c> +80006c70: 00171713 slli a4,a4,0x1 +80006c74: 00a61023 sh a0,0(a2) +80006c78: 01071713 slli a4,a4,0x10 +80006c7c: ffe60613 addi a2,a2,-2 +80006c80: 01075713 srli a4,a4,0x10 +80006c84: fda610e3 bne a2,s10,80006c44 <_ldtoa_r+0x664> +80006c88: 00000713 li a4,0 +80006c8c: 0cc10613 addi a2,sp,204 +80006c90: 01c0006f j 80006cac <_ldtoa_r+0x6cc> +80006c94: 00171713 slli a4,a4,0x1 +80006c98: 00f61023 sh a5,0(a2) +80006c9c: 01071713 slli a4,a4,0x10 +80006ca0: ffe60613 addi a2,a2,-2 +80006ca4: 01075713 srli a4,a4,0x10 +80006ca8: 05a60463 beq a2,s10,80006cf0 <_ldtoa_r+0x710> +80006cac: 00065783 lhu a5,0(a2) +80006cb0: 01079593 slli a1,a5,0x10 +80006cb4: 4105d593 srai a1,a1,0x10 +80006cb8: 00179793 slli a5,a5,0x1 +80006cbc: 0005d463 bgez a1,80006cc4 <_ldtoa_r+0x6e4> +80006cc0: 00176713 ori a4,a4,1 +80006cc4: 01079793 slli a5,a5,0x10 +80006cc8: 0107d793 srli a5,a5,0x10 +80006ccc: 00277593 andi a1,a4,2 +80006cd0: 0017e513 ori a0,a5,1 +80006cd4: fc0580e3 beqz a1,80006c94 <_ldtoa_r+0x6b4> +80006cd8: 00171713 slli a4,a4,0x1 +80006cdc: 00a61023 sh a0,0(a2) +80006ce0: 01071713 slli a4,a4,0x10 +80006ce4: ffe60613 addi a2,a2,-2 +80006ce8: 01075713 srli a4,a4,0x10 +80006cec: fda610e3 bne a2,s10,80006cac <_ldtoa_r+0x6cc> +80006cf0: 00000593 li a1,0 +80006cf4: 000d8613 mv a2,s11 +80006cf8: 0cc10713 addi a4,sp,204 +80006cfc: 00065503 lhu a0,0(a2) +80006d00: 00075783 lhu a5,0(a4) +80006d04: ffe60613 addi a2,a2,-2 +80006d08: ffe70713 addi a4,a4,-2 +80006d0c: 00a787b3 add a5,a5,a0 +80006d10: 00b787b3 add a5,a5,a1 +80006d14: 0107d593 srli a1,a5,0x10 +80006d18: 00f61123 sh a5,2(a2) +80006d1c: 0015f593 andi a1,a1,1 +80006d20: fda71ee3 bne a4,s10,80006cfc <_ldtoa_r+0x71c> +80006d24: 000c0613 mv a2,s8 +80006d28: 07c10593 addi a1,sp,124 +80006d2c: 09810513 addi a0,sp,152 +80006d30: c2dfe0ef jal ra,8000595c +80006d34: 1ac15783 lhu a5,428(sp) +80006d38: 00990733 add a4,s2,s1 +80006d3c: 00148493 addi s1,s1,1 +80006d40: 03078613 addi a2,a5,48 +80006d44: 00c70023 sb a2,0(a4) +80006d48: e49458e3 bge s0,s1,80006b98 <_ldtoa_r+0x5b8> +80006d4c: fff44513 not a0,s0 +80006d50: 01012703 lw a4,16(sp) +80006d54: 41f55513 srai a0,a0,0x1f +80006d58: 00a47533 and a0,s0,a0 +80006d5c: 01c12483 lw s1,28(sp) +80006d60: 00150913 addi s2,a0,1 +80006d64: 01270933 add s2,a4,s2 +80006d68: 00a70c33 add s8,a4,a0 +80006d6c: 00400713 li a4,4 +80006d70: 04f75e63 bge a4,a5,80006dcc <_ldtoa_r+0x7ec> +80006d74: 00500713 li a4,5 +80006d78: 00e780e3 beq a5,a4,80007578 <_ldtoa_r+0xf98> +80006d7c: ffe94783 lbu a5,-2(s2) +80006d80: ffe90713 addi a4,s2,-2 +80006d84: 07f7f793 andi a5,a5,127 +80006d88: 78044463 bltz s0,80007510 <_ldtoa_r+0xf30> +80006d8c: 02e00693 li a3,46 +80006d90: 03800613 li a2,56 +80006d94: 03000593 li a1,48 +80006d98: 00d78e63 beq a5,a3,80006db4 <_ldtoa_r+0x7d4> +80006d9c: 78f65263 bge a2,a5,80007520 <_ldtoa_r+0xf40> +80006da0: fff74783 lbu a5,-1(a4) +80006da4: 00b70023 sb a1,0(a4) +80006da8: fff70713 addi a4,a4,-1 +80006dac: 07f7f793 andi a5,a5,127 +80006db0: fe9ff06f j 80006d98 <_ldtoa_r+0x7b8> +80006db4: fff74783 lbu a5,-1(a4) +80006db8: 03800693 li a3,56 +80006dbc: 00f6f4e3 bgeu a3,a5,800075c4 <_ldtoa_r+0xfe4> +80006dc0: 03100793 li a5,49 +80006dc4: 00148493 addi s1,s1,1 +80006dc8: fef70fa3 sb a5,-1(a4) +80006dcc: 800155b7 lui a1,0x80015 +80006dd0: 00048613 mv a2,s1 +80006dd4: d8858593 addi a1,a1,-632 # 80014d88 <__BSS_END__+0xffffe14c> +80006dd8: 000c0513 mv a0,s8 +80006ddc: 03d020ef jal ra,80009618 +80006de0: 07215783 lhu a5,114(sp) +80006de4: 01412703 lw a4,20(sp) +80006de8: 16912823 sw s1,368(sp) +80006dec: fff7c793 not a5,a5 +80006df0: 16e12223 sw a4,356(sp) +80006df4: 01179713 slli a4,a5,0x11 +80006df8: 00071e63 bnez a4,80006e14 <_ldtoa_r+0x834> +80006dfc: 00098513 mv a0,s3 +80006e00: b9cfe0ef jal ra,8000519c +80006e04: 22051063 bnez a0,80007024 <_ldtoa_r+0xa44> +80006e08: 00098513 mv a0,s3 +80006e0c: 8ccfe0ef jal ra,80004ed8 +80006e10: 20051a63 bnez a0,80007024 <_ldtoa_r+0xa44> +80006e14: 00c12683 lw a3,12(sp) +80006e18: 12414703 lbu a4,292(sp) +80006e1c: 00148793 addi a5,s1,1 +80006e20: 00f6a023 sw a5,0(a3) +80006e24: 000a8793 mv a5,s5 +80006e28: 02070a63 beqz a4,80006e5c <_ldtoa_r+0x87c> +80006e2c: 02e00693 li a3,46 +80006e30: 1cd70c63 beq a4,a3,80007008 <_ldtoa_r+0xa28> +80006e34: 0017c703 lbu a4,1(a5) +80006e38: 00178793 addi a5,a5,1 +80006e3c: fe071ae3 bnez a4,80006e30 <_ldtoa_r+0x850> +80006e40: 04500693 li a3,69 +80006e44: 00fae663 bltu s5,a5,80006e50 <_ldtoa_r+0x870> +80006e48: 0140006f j 80006e5c <_ldtoa_r+0x87c> +80006e4c: 01578863 beq a5,s5,80006e5c <_ldtoa_r+0x87c> +80006e50: fff7c703 lbu a4,-1(a5) +80006e54: fff78793 addi a5,a5,-1 +80006e58: fed71ae3 bne a4,a3,80006e4c <_ldtoa_r+0x86c> +80006e5c: 00078023 sb zero,0(a5) +80006e60: 000a8793 mv a5,s5 +80006e64: 02000693 li a3,32 +80006e68: 02d00613 li a2,45 +80006e6c: 0007c703 lbu a4,0(a5) +80006e70: 00d70463 beq a4,a3,80006e78 <_ldtoa_r+0x898> +80006e74: 00c71663 bne a4,a2,80006e80 <_ldtoa_r+0x8a0> +80006e78: 00178793 addi a5,a5,1 +80006e7c: ff1ff06f j 80006e6c <_ldtoa_r+0x88c> +80006e80: 000a8413 mv s0,s5 +80006e84: 00c0006f j 80006e90 <_ldtoa_r+0x8b0> +80006e88: 0007c703 lbu a4,0(a5) +80006e8c: 00068413 mv s0,a3 +80006e90: 00e40023 sb a4,0(s0) +80006e94: 00140693 addi a3,s0,1 +80006e98: 00178793 addi a5,a5,1 +80006e9c: fe0716e3 bnez a4,80006e88 <_ldtoa_r+0x8a8> +80006ea0: 00012683 lw a3,0(sp) +80006ea4: 00200793 li a5,2 +80006ea8: fff44703 lbu a4,-1(s0) +80006eac: 12f68663 beq a3,a5,80006fd8 <_ldtoa_r+0x9f8> +80006eb0: 00412783 lw a5,4(sp) +80006eb4: 00078693 mv a3,a5 +80006eb8: 0097d463 bge a5,s1,80006ec0 <_ldtoa_r+0x8e0> +80006ebc: 00048693 mv a3,s1 +80006ec0: 03000793 li a5,48 +80006ec4: 02f71663 bne a4,a5,80006ef0 <_ldtoa_r+0x910> +80006ec8: 415407b3 sub a5,s0,s5 +80006ecc: 02f6d263 bge a3,a5,80006ef0 <_ldtoa_r+0x910> +80006ed0: 03000613 li a2,48 +80006ed4: 0080006f j 80006edc <_ldtoa_r+0x8fc> +80006ed8: 00e6dc63 bge a3,a4,80006ef0 <_ldtoa_r+0x910> +80006edc: ffe44783 lbu a5,-2(s0) +80006ee0: fe040fa3 sb zero,-1(s0) +80006ee4: fff40413 addi s0,s0,-1 +80006ee8: 41540733 sub a4,s0,s5 +80006eec: fec786e3 beq a5,a2,80006ed8 <_ldtoa_r+0x8f8> +80006ef0: 00012703 lw a4,0(sp) +80006ef4: 00300793 li a5,3 +80006ef8: 0af70263 beq a4,a5,80006f9c <_ldtoa_r+0x9bc> +80006efc: 00812783 lw a5,8(sp) +80006f00: 040a2223 sw zero,68(s4) +80006f04: 00978693 addi a3,a5,9 +80006f08: 01700793 li a5,23 +80006f0c: 0cd7f263 bgeu a5,a3,80006fd0 <_ldtoa_r+0x9f0> +80006f10: 00100713 li a4,1 +80006f14: 00400793 li a5,4 +80006f18: 00179793 slli a5,a5,0x1 +80006f1c: 01478613 addi a2,a5,20 +80006f20: 00070593 mv a1,a4 +80006f24: 00170713 addi a4,a4,1 +80006f28: fec6f8e3 bgeu a3,a2,80006f18 <_ldtoa_r+0x938> +80006f2c: 04ba2223 sw a1,68(s4) +80006f30: 000a0513 mv a0,s4 +80006f34: 500010ef jal ra,80008434 <_Balloc> +80006f38: 04aa2023 sw a0,64(s4) +80006f3c: 000a8593 mv a1,s5 +80006f40: 00050493 mv s1,a0 +80006f44: 0a9020ef jal ra,800097ec +80006f48: 01812783 lw a5,24(sp) +80006f4c: 00078863 beqz a5,80006f5c <_ldtoa_r+0x97c> +80006f50: 41540433 sub s0,s0,s5 +80006f54: 00848433 add s0,s1,s0 +80006f58: 0087a023 sw s0,0(a5) +80006f5c: 1ec12083 lw ra,492(sp) +80006f60: 1e812403 lw s0,488(sp) +80006f64: 1e012903 lw s2,480(sp) +80006f68: 1dc12983 lw s3,476(sp) +80006f6c: 1d812a03 lw s4,472(sp) +80006f70: 1d412a83 lw s5,468(sp) +80006f74: 1d012b03 lw s6,464(sp) +80006f78: 1cc12b83 lw s7,460(sp) +80006f7c: 1c812c03 lw s8,456(sp) +80006f80: 1c412c83 lw s9,452(sp) +80006f84: 1c012d03 lw s10,448(sp) +80006f88: 1bc12d83 lw s11,444(sp) +80006f8c: 00048513 mv a0,s1 +80006f90: 1e412483 lw s1,484(sp) +80006f94: 1f010113 addi sp,sp,496 +80006f98: 00008067 ret +80006f9c: 00412783 lw a5,4(sp) +80006fa0: 009784b3 add s1,a5,s1 +80006fa4: 5004c863 bltz s1,800074b4 <_ldtoa_r+0xed4> +80006fa8: 00c12783 lw a5,12(sp) +80006fac: 00812703 lw a4,8(sp) +80006fb0: 0007a783 lw a5,0(a5) +80006fb4: 00f707b3 add a5,a4,a5 +80006fb8: 00f12423 sw a5,8(sp) +80006fbc: 00812783 lw a5,8(sp) +80006fc0: 040a2223 sw zero,68(s4) +80006fc4: 00378693 addi a3,a5,3 +80006fc8: 01700793 li a5,23 +80006fcc: f4d7e2e3 bltu a5,a3,80006f10 <_ldtoa_r+0x930> +80006fd0: 00000593 li a1,0 +80006fd4: f5dff06f j 80006f30 <_ldtoa_r+0x950> +80006fd8: 03000793 li a5,48 +80006fdc: f2f710e3 bne a4,a5,80006efc <_ldtoa_r+0x91c> +80006fe0: 415407b3 sub a5,s0,s5 +80006fe4: 00100693 li a3,1 +80006fe8: eef6c4e3 blt a3,a5,80006ed0 <_ldtoa_r+0x8f0> +80006fec: f11ff06f j 80006efc <_ldtoa_r+0x91c> +80006ff0: 00812483 lw s1,8(sp) +80006ff4: 00912223 sw s1,4(sp) +80006ff8: 02a00793 li a5,42 +80006ffc: ec97d063 bge a5,s1,800066bc <_ldtoa_r+0xdc> +80007000: 00f12223 sw a5,4(sp) +80007004: eb8ff06f j 800066bc <_ldtoa_r+0xdc> +80007008: 0007c703 lbu a4,0(a5) +8000700c: e2070ae3 beqz a4,80006e40 <_ldtoa_r+0x860> +80007010: 0017c703 lbu a4,1(a5) +80007014: 00178793 addi a5,a5,1 +80007018: fee78fa3 sb a4,-1(a5) +8000701c: fe071ae3 bnez a4,80007010 <_ldtoa_r+0xa30> +80007020: e21ff06f j 80006e40 <_ldtoa_r+0x860> +80007024: 00c12703 lw a4,12(sp) +80007028: 000027b7 lui a5,0x2 +8000702c: 70f78793 addi a5,a5,1807 # 270f <_start-0x7fffd8f1> +80007030: 00f72023 sw a5,0(a4) +80007034: e2dff06f j 80006e60 <_ldtoa_r+0x880> +80007038: 03100713 li a4,49 +8000703c: 12e102a3 sb a4,293(sp) +80007040: 02e00713 li a4,46 +80007044: 12e10323 sb a4,294(sp) +80007048: 00148493 addi s1,s1,1 +8000704c: 2af05c63 blez a5,80007304 <_ldtoa_r+0xd24> +80007050: 03000793 li a5,48 +80007054: 12f103a3 sb a5,295(sp) +80007058: 12810793 addi a5,sp,296 +8000705c: fff40413 addi s0,s0,-1 +80007060: 00f12823 sw a5,16(sp) +80007064: b11ff06f j 80006b74 <_ldtoa_r+0x594> +80007068: 0b410c93 addi s9,sp,180 +8000706c: 000c8713 mv a4,s9 +80007070: 07c10793 addi a5,sp,124 +80007074: 09010613 addi a2,sp,144 +80007078: 0007d683 lhu a3,0(a5) +8000707c: 00278793 addi a5,a5,2 +80007080: 00270713 addi a4,a4,2 +80007084: fed71f23 sh a3,-2(a4) +80007088: fec798e3 bne a5,a2,80007078 <_ldtoa_r+0xa98> +8000708c: 000047b7 lui a5,0x4 +80007090: 08e78793 addi a5,a5,142 # 408e <_start-0x7fffbf72> +80007094: 0cf11323 sh a5,198(sp) +80007098: 000087b7 lui a5,0x8 +8000709c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800070a0: 00f12e23 sw a5,28(sp) +800070a4: ffffc7b7 lui a5,0xffffc +800070a8: 12410a93 addi s5,sp,292 +800070ac: 0d010413 addi s0,sp,208 +800070b0: 01000e13 li t3,16 +800070b4: 0c8d8313 addi t1,s11,200 +800070b8: 00278793 addi a5,a5,2 # ffffc002 <__BSS_END__+0x7ffe53c6> +800070bc: 03412423 sw s4,40(sp) +800070c0: 03512223 sw s5,36(sp) +800070c4: 00000493 li s1,0 +800070c8: 000c8a93 mv s5,s9 +800070cc: 16010913 addi s2,sp,352 +800070d0: 00040c93 mv s9,s0 +800070d4: 0aa10b93 addi s7,sp,170 +800070d8: 02f12023 sw a5,32(sp) +800070dc: 000e0a13 mv s4,t3 +800070e0: 00030413 mv s0,t1 +800070e4: 00090693 mv a3,s2 +800070e8: 09810613 addi a2,sp,152 +800070ec: 000a8593 mv a1,s5 +800070f0: 00040513 mv a0,s0 +800070f4: e99fe0ef jal ra,80005f8c +800070f8: 04c10713 addi a4,sp,76 +800070fc: 09810793 addi a5,sp,152 +80007100: 0007d683 lhu a3,0(a5) +80007104: 00278793 addi a5,a5,2 +80007108: 00270713 addi a4,a4,2 +8000710c: fed71f23 sh a3,-2(a4) +80007110: ffa798e3 bne a5,s10,80007100 <_ldtoa_r+0xb20> +80007114: 01c12783 lw a5,28(sp) +80007118: 05e15583 lhu a1,94(sp) +8000711c: 00f5f633 and a2,a1,a5 +80007120: 02012783 lw a5,32(sp) +80007124: 00f60533 add a0,a2,a5 +80007128: 3aa05063 blez a0,800074c8 <_ldtoa_r+0xee8> +8000712c: 09000613 li a2,144 +80007130: 40a60633 sub a2,a2,a0 +80007134: 000c8713 mv a4,s9 +80007138: 04c10793 addi a5,sp,76 8000713c: 0007d683 lhu a3,0(a5) 80007140: 00278793 addi a5,a5,2 80007144: 00270713 addi a4,a4,2 80007148: fed71f23 sh a3,-2(a4) -8000714c: fec798e3 bne a5,a2,8000713c <_ldtoa_r+0xa98> -80007150: 000047b7 lui a5,0x4 -80007154: 08e78793 addi a5,a5,142 # 408e <_start-0x7fffbf72> -80007158: 0cf11323 sh a5,198(sp) -8000715c: 000087b7 lui a5,0x8 -80007160: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80007164: 00f12e23 sw a5,28(sp) -80007168: ffffc7b7 lui a5,0xffffc -8000716c: 12410a93 addi s5,sp,292 -80007170: 0d010413 addi s0,sp,208 -80007174: 01000e13 li t3,16 -80007178: 0c8d8313 addi t1,s11,200 -8000717c: 00278793 addi a5,a5,2 # ffffc002 <__BSS_END__+0x7ffe53c6> -80007180: 03412423 sw s4,40(sp) -80007184: 03512223 sw s5,36(sp) -80007188: 00000493 li s1,0 -8000718c: 000c8a93 mv s5,s9 -80007190: 16010913 addi s2,sp,352 -80007194: 00040c93 mv s9,s0 -80007198: 0aa10b93 addi s7,sp,170 -8000719c: 02f12023 sw a5,32(sp) -800071a0: 000e0a13 mv s4,t3 -800071a4: 00030413 mv s0,t1 -800071a8: 00090693 mv a3,s2 -800071ac: 09810613 addi a2,sp,152 -800071b0: 000a8593 mv a1,s5 -800071b4: 00040513 mv a0,s0 -800071b8: e99fe0ef jal ra,80006050 -800071bc: 04c10713 addi a4,sp,76 -800071c0: 09810793 addi a5,sp,152 -800071c4: 0007d683 lhu a3,0(a5) +8000714c: ff3798e3 bne a5,s3,8000713c <_ldtoa_r+0xb5c> +80007150: 06c05463 blez a2,800071b8 <_ldtoa_r+0xbd8> +80007154: 00f00793 li a5,15 +80007158: 000c8713 mv a4,s9 +8000715c: 02c7dc63 bge a5,a2,80007194 <_ldtoa_r+0xbb4> +80007160: ff060613 addi a2,a2,-16 +80007164: 00465693 srli a3,a2,0x4 +80007168: 00168713 addi a4,a3,1 +8000716c: 00171713 slli a4,a4,0x1 +80007170: 00ec8733 add a4,s9,a4 +80007174: 000c8793 mv a5,s9 +80007178: 00278793 addi a5,a5,2 +8000717c: fe079f23 sh zero,-2(a5) +80007180: fee79ce3 bne a5,a4,80007178 <_ldtoa_r+0xb98> +80007184: 08000613 li a2,128 +80007188: 40a60633 sub a2,a2,a0 +8000718c: 00469693 slli a3,a3,0x4 +80007190: 40d60633 sub a2,a2,a3 +80007194: 00161613 slli a2,a2,0x1 +80007198: 00cd8633 add a2,s11,a2 +8000719c: 00075783 lhu a5,0(a4) +800071a0: 23065683 lhu a3,560(a2) +800071a4: 00d7f7b3 and a5,a5,a3 +800071a8: 00f71023 sh a5,0(a4) +800071ac: 01059593 slli a1,a1,0x10 +800071b0: 4105d593 srai a1,a1,0x10 +800071b4: 1605c063 bltz a1,80007314 <_ldtoa_r+0xd34> +800071b8: 09810793 addi a5,sp,152 +800071bc: 000c8713 mv a4,s9 +800071c0: 0007d603 lhu a2,0(a5) +800071c4: 00075683 lhu a3,0(a4) 800071c8: 00278793 addi a5,a5,2 800071cc: 00270713 addi a4,a4,2 -800071d0: fed71f23 sh a3,-2(a4) -800071d4: ffa798e3 bne a5,s10,800071c4 <_ldtoa_r+0xb20> -800071d8: 01c12783 lw a5,28(sp) -800071dc: 05e15583 lhu a1,94(sp) -800071e0: 00f5f633 and a2,a1,a5 -800071e4: 02012783 lw a5,32(sp) -800071e8: 00f60533 add a0,a2,a5 -800071ec: 3aa05063 blez a0,8000758c <_ldtoa_r+0xee8> -800071f0: 09000613 li a2,144 -800071f4: 40a60633 sub a2,a2,a0 -800071f8: 000c8713 mv a4,s9 -800071fc: 04c10793 addi a5,sp,76 -80007200: 0007d683 lhu a3,0(a5) -80007204: 00278793 addi a5,a5,2 -80007208: 00270713 addi a4,a4,2 -8000720c: fed71f23 sh a3,-2(a4) -80007210: ff3798e3 bne a5,s3,80007200 <_ldtoa_r+0xb5c> -80007214: 06c05463 blez a2,8000727c <_ldtoa_r+0xbd8> -80007218: 00f00793 li a5,15 -8000721c: 000c8713 mv a4,s9 -80007220: 02c7dc63 bge a5,a2,80007258 <_ldtoa_r+0xbb4> -80007224: ff060613 addi a2,a2,-16 -80007228: 00465693 srli a3,a2,0x4 -8000722c: 00168713 addi a4,a3,1 -80007230: 00171713 slli a4,a4,0x1 -80007234: 00ec8733 add a4,s9,a4 +800071d0: 02d61463 bne a2,a3,800071f8 <_ldtoa_r+0xc18> +800071d4: fefb96e3 bne s7,a5,800071c0 <_ldtoa_r+0xbe0> +800071d8: 000a8713 mv a4,s5 +800071dc: 09810793 addi a5,sp,152 +800071e0: 0007d683 lhu a3,0(a5) +800071e4: 00278793 addi a5,a5,2 +800071e8: 00270713 addi a4,a4,2 +800071ec: fed71f23 sh a3,-2(a4) +800071f0: ffa798e3 bne a5,s10,800071e0 <_ldtoa_r+0xc00> +800071f4: 014484b3 add s1,s1,s4 +800071f8: 01440413 addi s0,s0,20 +800071fc: 12cd8793 addi a5,s11,300 +80007200: 001a5a13 srli s4,s4,0x1 +80007204: eef410e3 bne s0,a5,800070e4 <_ldtoa_r+0xb04> +80007208: 0c615783 lhu a5,198(sp) +8000720c: 08e15703 lhu a4,142(sp) +80007210: 000c8413 mv s0,s9 +80007214: 02812a03 lw s4,40(sp) +80007218: 00e787b3 add a5,a5,a4 +8000721c: ffffc737 lui a4,0xffffc +80007220: 000a8c93 mv s9,s5 +80007224: f7270713 addi a4,a4,-142 # ffffbf72 <__BSS_END__+0x7ffe5336> +80007228: 02412a83 lw s5,36(sp) +8000722c: 00e787b3 add a5,a5,a4 +80007230: 0cf11323 sh a5,198(sp) +80007234: 07c10713 addi a4,sp,124 80007238: 000c8793 mv a5,s9 -8000723c: 00278793 addi a5,a5,2 -80007240: fe079f23 sh zero,-2(a5) -80007244: fee79ce3 bne a5,a4,8000723c <_ldtoa_r+0xb98> -80007248: 08000613 li a2,128 -8000724c: 40a60633 sub a2,a2,a0 -80007250: 00469693 slli a3,a3,0x4 -80007254: 40d60633 sub a2,a2,a3 -80007258: 00161613 slli a2,a2,0x1 -8000725c: 00cd8633 add a2,s11,a2 -80007260: 00075783 lhu a5,0(a4) -80007264: 23065683 lhu a3,560(a2) -80007268: 00d7f7b3 and a5,a5,a3 -8000726c: 00f71023 sh a5,0(a4) -80007270: 01059593 slli a1,a1,0x10 -80007274: 4105d593 srai a1,a1,0x10 -80007278: 1605c063 bltz a1,800073d8 <_ldtoa_r+0xd34> -8000727c: 09810793 addi a5,sp,152 -80007280: 000c8713 mv a4,s9 -80007284: 0007d603 lhu a2,0(a5) -80007288: 00075683 lhu a3,0(a4) -8000728c: 00278793 addi a5,a5,2 -80007290: 00270713 addi a4,a4,2 -80007294: 02d61463 bne a2,a3,800072bc <_ldtoa_r+0xc18> -80007298: fefb96e3 bne s7,a5,80007284 <_ldtoa_r+0xbe0> -8000729c: 000a8713 mv a4,s5 -800072a0: 09810793 addi a5,sp,152 -800072a4: 0007d683 lhu a3,0(a5) -800072a8: 00278793 addi a5,a5,2 -800072ac: 00270713 addi a4,a4,2 -800072b0: fed71f23 sh a3,-2(a4) -800072b4: ffa798e3 bne a5,s10,800072a4 <_ldtoa_r+0xc00> -800072b8: 014484b3 add s1,s1,s4 -800072bc: 01440413 addi s0,s0,20 -800072c0: 12cd8793 addi a5,s11,300 -800072c4: 001a5a13 srli s4,s4,0x1 -800072c8: eef410e3 bne s0,a5,800071a8 <_ldtoa_r+0xb04> -800072cc: 0c615783 lhu a5,198(sp) -800072d0: 08e15703 lhu a4,142(sp) -800072d4: 000c8413 mv s0,s9 -800072d8: 02812a03 lw s4,40(sp) -800072dc: 00e787b3 add a5,a5,a4 -800072e0: ffffc737 lui a4,0xffffc -800072e4: 000a8c93 mv s9,s5 -800072e8: f7270713 addi a4,a4,-142 # ffffbf72 <__BSS_END__+0x7ffe5336> -800072ec: 02412a83 lw s5,36(sp) -800072f0: 00e787b3 add a5,a5,a4 -800072f4: 0cf11323 sh a5,198(sp) -800072f8: 07c10713 addi a4,sp,124 -800072fc: 000c8793 mv a5,s9 -80007300: 0c810613 addi a2,sp,200 -80007304: 0007d683 lhu a3,0(a5) -80007308: 00278793 addi a5,a5,2 -8000730c: 00270713 addi a4,a4,2 -80007310: fed71f23 sh a3,-2(a4) -80007314: fec798e3 bne a5,a2,80007304 <_ldtoa_r+0xc60> -80007318: 00000713 li a4,0 -8000731c: 09810793 addi a5,sp,152 -80007320: 0080006f j 80007328 <_ldtoa_r+0xc84> -80007324: 000c5703 lhu a4,0(s8) -80007328: 00278793 addi a5,a5,2 -8000732c: fee79f23 sh a4,-2(a5) -80007330: 002c0c13 addi s8,s8,2 -80007334: ffa798e3 bne a5,s10,80007324 <_ldtoa_r+0xc80> -80007338: 028d8d13 addi s10,s11,40 -8000733c: 00001c37 lui s8,0x1 -80007340: 118d8d93 addi s11,s11,280 -80007344: 0100006f j 80007354 <_ldtoa_r+0xcb0> -80007348: 001c5c13 srli s8,s8,0x1 -8000734c: 29bd0063 beq s10,s11,800075cc <_ldtoa_r+0xf28> -80007350: 014d0d13 addi s10,s10,20 -80007354: 000c8593 mv a1,s9 -80007358: 000d8513 mv a0,s11 -8000735c: de9fd0ef jal ra,80005144 -80007360: 00050793 mv a5,a0 -80007364: 000c8593 mv a1,s9 -80007368: 000d0513 mv a0,s10 -8000736c: 26f04063 bgtz a5,800075cc <_ldtoa_r+0xf28> -80007370: dd5fd0ef jal ra,80005144 -80007374: fca04ae3 bgtz a0,80007348 <_ldtoa_r+0xca4> -80007378: 00090693 mv a3,s2 -8000737c: 000c8613 mv a2,s9 -80007380: 000c8593 mv a1,s9 -80007384: 000d0513 mv a0,s10 -80007388: cc9fe0ef jal ra,80006050 -8000738c: 09810613 addi a2,sp,152 -80007390: 00090693 mv a3,s2 -80007394: 00060593 mv a1,a2 -80007398: 000d0513 mv a0,s10 -8000739c: 89dfe0ef jal ra,80005c38 -800073a0: 018484b3 add s1,s1,s8 -800073a4: fa5ff06f j 80007348 <_ldtoa_r+0xca4> -800073a8: 12410a93 addi s5,sp,292 -800073ac: 800155b7 lui a1,0x80015 -800073b0: e3858593 addi a1,a1,-456 # 80014e38 <__BSS_END__+0xffffe1fc> -800073b4: 000a8513 mv a0,s5 -800073b8: 000024b7 lui s1,0x2 -800073bc: 320020ef jal ra,800096dc -800073c0: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -800073c4: ae1ff06f j 80006ea4 <_ldtoa_r+0x800> -800073c8: 12710c13 addi s8,sp,295 -800073cc: ac0792e3 bnez a5,80006e90 <_ldtoa_r+0x7ec> -800073d0: 01812823 sw s8,16(sp) -800073d4: 865ff06f j 80006c38 <_ldtoa_r+0x594> -800073d8: 04c10793 addi a5,sp,76 -800073dc: 000c8713 mv a4,s9 -800073e0: 00c0006f j 800073ec <_ldtoa_r+0xd48> -800073e4: 05e10693 addi a3,sp,94 -800073e8: e8f68ae3 beq a3,a5,8000727c <_ldtoa_r+0xbd8> -800073ec: 0007d603 lhu a2,0(a5) -800073f0: 00075683 lhu a3,0(a4) -800073f4: 00278793 addi a5,a5,2 -800073f8: 00270713 addi a4,a4,2 -800073fc: fed604e3 beq a2,a3,800073e4 <_ldtoa_r+0xd40> -80007400: 0e215783 lhu a5,226(sp) -80007404: 01c12703 lw a4,28(sp) -80007408: 00f777b3 and a5,a4,a5 -8000740c: 00e79e63 bne a5,a4,80007428 <_ldtoa_r+0xd84> -80007410: 000c8513 mv a0,s9 -80007414: b89fd0ef jal ra,80004f9c -80007418: e60512e3 bnez a0,8000727c <_ldtoa_r+0xbd8> -8000741c: 000c8513 mv a0,s9 -80007420: e41fd0ef jal ra,80005260 -80007424: e4051ce3 bnez a0,8000727c <_ldtoa_r+0xbd8> -80007428: 0ec10593 addi a1,sp,236 -8000742c: 000c0513 mv a0,s8 -80007430: c1dfd0ef jal ra,8000504c -80007434: 10810593 addi a1,sp,264 -80007438: 000c8513 mv a0,s9 -8000743c: c11fd0ef jal ra,8000504c -80007440: 0ec15603 lhu a2,236(sp) -80007444: 10a15503 lhu a0,266(sp) -80007448: 0ee15883 lhu a7,238(sp) -8000744c: fff64613 not a2,a2 -80007450: 01061613 slli a2,a2,0x10 -80007454: 01065613 srli a2,a2,0x10 -80007458: 0ec11623 sh a2,236(sp) -8000745c: 40a885b3 sub a1,a7,a0 -80007460: 00050693 mv a3,a0 -80007464: 06b05e63 blez a1,800074e0 <_ldtoa_r+0xe3c> -80007468: 02412683 lw a3,36(sp) -8000746c: 10810713 addi a4,sp,264 -80007470: 12010793 addi a5,sp,288 -80007474: 00075583 lhu a1,0(a4) -80007478: 00270713 addi a4,a4,2 -8000747c: 00268693 addi a3,a3,2 -80007480: feb69f23 sh a1,-2(a3) -80007484: fef718e3 bne a4,a5,80007474 <_ldtoa_r+0xdd0> -80007488: 12011e23 sh zero,316(sp) -8000748c: 10810713 addi a4,sp,264 -80007490: 0ec10693 addi a3,sp,236 -80007494: 0080006f j 8000749c <_ldtoa_r+0xdf8> -80007498: 0006d603 lhu a2,0(a3) -8000749c: 00270713 addi a4,a4,2 -800074a0: fec71f23 sh a2,-2(a4) -800074a4: 00268693 addi a3,a3,2 -800074a8: fef718e3 bne a4,a5,80007498 <_ldtoa_r+0xdf4> -800074ac: 02412783 lw a5,36(sp) -800074b0: 12011023 sh zero,288(sp) -800074b4: 0ec10713 addi a4,sp,236 -800074b8: 13c10613 addi a2,sp,316 -800074bc: 0007d683 lhu a3,0(a5) -800074c0: 00278793 addi a5,a5,2 -800074c4: 00270713 addi a4,a4,2 -800074c8: fed71f23 sh a3,-2(a4) -800074cc: fec798e3 bne a5,a2,800074bc <_ldtoa_r+0xe18> -800074d0: 10a15683 lhu a3,266(sp) -800074d4: 411505b3 sub a1,a0,a7 -800074d8: 10011223 sh zero,260(sp) -800074dc: 00068513 mv a0,a3 -800074e0: 2c058663 beqz a1,800077ac <_ldtoa_r+0x1108> -800074e4: 02d12623 sw a3,44(sp) -800074e8: f6f00793 li a5,-145 -800074ec: 06f5c863 blt a1,a5,8000755c <_ldtoa_r+0xeb8> -800074f0: 0ec10513 addi a0,sp,236 -800074f4: d89fd0ef jal ra,8000527c -800074f8: 02c12683 lw a3,44(sp) -800074fc: 00050593 mv a1,a0 -80007500: 12010793 addi a5,sp,288 -80007504: 10410513 addi a0,sp,260 -80007508: 0ec15603 lhu a2,236(sp) -8000750c: 10815703 lhu a4,264(sp) -80007510: 2ee60a63 beq a2,a4,80007804 <_ldtoa_r+0x1160> -80007514: 00000713 li a4,0 -80007518: 00070613 mv a2,a4 -8000751c: 0007d703 lhu a4,0(a5) -80007520: 00055803 lhu a6,0(a0) -80007524: ffe78793 addi a5,a5,-2 -80007528: 40c70733 sub a4,a4,a2 -8000752c: 41070733 sub a4,a4,a6 -80007530: 01075613 srli a2,a4,0x10 -80007534: 00e79123 sh a4,2(a5) -80007538: 10a10713 addi a4,sp,266 -8000753c: 00167613 andi a2,a2,1 -80007540: ffe50513 addi a0,a0,-2 -80007544: fce79ce3 bne a5,a4,8000751c <_ldtoa_r+0xe78> -80007548: 00100613 li a2,1 -8000754c: 00090793 mv a5,s2 -80007550: 04000713 li a4,64 -80007554: 10810513 addi a0,sp,264 -80007558: 8bcfe0ef jal ra,80005614 -8000755c: 000c8593 mv a1,s9 -80007560: 10810513 addi a0,sp,264 -80007564: e24fe0ef jal ra,80005b88 -80007568: d15ff06f j 8000727c <_ldtoa_r+0xbd8> -8000756c: 00812783 lw a5,8(sp) -80007570: fff78493 addi s1,a5,-1 -80007574: b45ff06f j 800070b8 <_ldtoa_r+0xa14> -80007578: 00c12783 lw a5,12(sp) -8000757c: 12010223 sb zero,292(sp) -80007580: 000a8413 mv s0,s5 -80007584: 0007a023 sw zero,0(a5) -80007588: af9ff06f j 80007080 <_ldtoa_r+0x9dc> -8000758c: 000c8793 mv a5,s9 -80007590: 0e410713 addi a4,sp,228 -80007594: 00278793 addi a5,a5,2 -80007598: fe079f23 sh zero,-2(a5) -8000759c: fee79ce3 bne a5,a4,80007594 <_ldtoa_r+0xef0> -800075a0: cd1ff06f j 80007270 <_ldtoa_r+0xbcc> -800075a4: 01012783 lw a5,16(sp) -800075a8: 12410a93 addi s5,sp,292 -800075ac: 06078a63 beqz a5,80007620 <_ldtoa_r+0xf7c> -800075b0: 800155b7 lui a1,0x80015 -800075b4: e4058593 addi a1,a1,-448 # 80014e40 <__BSS_END__+0xffffe204> -800075b8: 000a8513 mv a0,s5 -800075bc: 000024b7 lui s1,0x2 -800075c0: 11c020ef jal ra,800096dc -800075c4: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -800075c8: 8ddff06f j 80006ea4 <_ldtoa_r+0x800> -800075cc: 0e810b93 addi s7,sp,232 -800075d0: bd8ff06f j 800069a8 <_ldtoa_r+0x304> -800075d4: 03100793 li a5,49 -800075d8: fef90f23 sb a5,-2(s2) -800075dc: 00148493 addi s1,s1,1 -800075e0: 8b1ff06f j 80006e90 <_ldtoa_r+0x7ec> -800075e4: 00178793 addi a5,a5,1 -800075e8: 00f70023 sb a5,0(a4) -800075ec: 8a5ff06f j 80006e90 <_ldtoa_r+0x7ec> -800075f0: 12410a93 addi s5,sp,292 -800075f4: 800155b7 lui a1,0x80015 -800075f8: e5858593 addi a1,a1,-424 # 80014e58 <__BSS_END__+0xffffe21c> -800075fc: 000a8513 mv a0,s5 -80007600: 000024b7 lui s1,0x2 -80007604: 0d8020ef jal ra,800096dc -80007608: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -8000760c: 899ff06f j 80006ea4 <_ldtoa_r+0x800> -80007610: 1ac15783 lhu a5,428(sp) -80007614: 12610c13 addi s8,sp,294 -80007618: 12710913 addi s2,sp,295 -8000761c: 815ff06f j 80006e30 <_ldtoa_r+0x78c> -80007620: 800155b7 lui a1,0x80015 -80007624: e4c58593 addi a1,a1,-436 # 80014e4c <__BSS_END__+0xffffe210> -80007628: 000a8513 mv a0,s5 -8000762c: 000024b7 lui s1,0x2 -80007630: 0ac020ef jal ra,800096dc -80007634: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> -80007638: 86dff06f j 80006ea4 <_ldtoa_r+0x800> -8000763c: 09810593 addi a1,sp,152 -80007640: 07c10513 addi a0,sp,124 -80007644: d44fe0ef jal ra,80005b88 -80007648: e60b0593 addi a1,s6,-416 -8000764c: 09810513 addi a0,sp,152 -80007650: af5fd0ef jal ra,80005144 -80007654: fe051663 bnez a0,80006e40 <_ldtoa_r+0x79c> -80007658: 82044ce3 bltz s0,80006e90 <_ldtoa_r+0x7ec> -8000765c: ffe94783 lbu a5,-2(s2) -80007660: fd278713 addi a4,a5,-46 -80007664: 00173713 seqz a4,a4 -80007668: fff74713 not a4,a4 -8000766c: 00ec0733 add a4,s8,a4 -80007670: 00074703 lbu a4,0(a4) -80007674: 00177713 andi a4,a4,1 -80007678: 80070ce3 beqz a4,80006e90 <_ldtoa_r+0x7ec> -8000767c: ffe90713 addi a4,s2,-2 -80007680: 07f7f793 andi a5,a5,127 -80007684: fccff06f j 80006e50 <_ldtoa_r+0x7ac> -80007688: 00178793 addi a5,a5,1 -8000768c: fef70fa3 sb a5,-1(a4) -80007690: 801ff06f j 80006e90 <_ldtoa_r+0x7ec> -80007694: 0d010413 addi s0,sp,208 -80007698: 00040593 mv a1,s0 -8000769c: 07c10513 addi a0,sp,124 -800076a0: 00004cb7 lui s9,0x4 -800076a4: 9a9fd0ef jal ra,8000504c -800076a8: 00000493 li s1,0 -800076ac: 0e810b93 addi s7,sp,232 -800076b0: 0cc10913 addi s2,sp,204 -800076b4: 0d210a93 addi s5,sp,210 -800076b8: ffec8c93 addi s9,s9,-2 # 3ffe <_start-0x7fffc002> -800076bc: 0e815783 lhu a5,232(sp) -800076c0: 0077f793 andi a5,a5,7 -800076c4: 0c079a63 bnez a5,80007798 <_ldtoa_r+0x10f4> -800076c8: 0b410713 addi a4,sp,180 -800076cc: 00040793 mv a5,s0 -800076d0: 0007d683 lhu a3,0(a5) -800076d4: 00278793 addi a5,a5,2 -800076d8: 00270713 addi a4,a4,2 -800076dc: fed71f23 sh a3,-2(a4) -800076e0: ff7798e3 bne a5,s7,800076d0 <_ldtoa_r+0x102c> -800076e4: 0b410513 addi a0,sp,180 -800076e8: 0c011623 sh zero,204(sp) -800076ec: f40fd0ef jal ra,80004e2c -800076f0: 0b410513 addi a0,sp,180 -800076f4: f38fd0ef jal ra,80004e2c -800076f8: 00000613 li a2,0 -800076fc: 00090693 mv a3,s2 -80007700: 000b8713 mv a4,s7 -80007704: 0006d583 lhu a1,0(a3) -80007708: 00075783 lhu a5,0(a4) -8000770c: ffe68693 addi a3,a3,-2 -80007710: ffe70713 addi a4,a4,-2 -80007714: 00b787b3 add a5,a5,a1 -80007718: 00c787b3 add a5,a5,a2 -8000771c: 0107d613 srli a2,a5,0x10 -80007720: 00f69123 sh a5,2(a3) -80007724: 00167613 andi a2,a2,1 -80007728: fd571ee3 bne a4,s5,80007704 <_ldtoa_r+0x1060> -8000772c: 0b615783 lhu a5,182(sp) -80007730: 0b815703 lhu a4,184(sp) -80007734: 00378793 addi a5,a5,3 -80007738: 0af11b23 sh a5,182(sp) -8000773c: 02070063 beqz a4,8000775c <_ldtoa_r+0x10b8> -80007740: 0b410513 addi a0,sp,180 -80007744: ee8fd0ef jal ra,80004e2c -80007748: 0b615783 lhu a5,182(sp) -8000774c: 0b815703 lhu a4,184(sp) -80007750: 00178793 addi a5,a5,1 -80007754: 0af11b23 sh a5,182(sp) -80007758: fe0714e3 bnez a4,80007740 <_ldtoa_r+0x109c> -8000775c: 0cc15783 lhu a5,204(sp) -80007760: 02079c63 bnez a5,80007798 <_ldtoa_r+0x10f4> -80007764: 0b615783 lhu a5,182(sp) -80007768: 02fce863 bltu s9,a5,80007798 <_ldtoa_r+0x10f4> -8000776c: 00040713 mv a4,s0 -80007770: 0b410793 addi a5,sp,180 -80007774: 0007d683 lhu a3,0(a5) -80007778: 00278793 addi a5,a5,2 -8000777c: 00270713 addi a4,a4,2 -80007780: fed71f23 sh a3,-2(a4) -80007784: ff2798e3 bne a5,s2,80007774 <_ldtoa_r+0x10d0> -80007788: 0e011423 sh zero,232(sp) -8000778c: fff48493 addi s1,s1,-1 -80007790: fd500793 li a5,-43 -80007794: f2f494e3 bne s1,a5,800076bc <_ldtoa_r+0x1018> -80007798: 07c10593 addi a1,sp,124 -8000779c: 00040513 mv a0,s0 -800077a0: be8fe0ef jal ra,80005b88 -800077a4: 16010913 addi s2,sp,352 -800077a8: 8f4ff06f j 8000689c <_ldtoa_r+0x1f8> -800077ac: 10c10713 addi a4,sp,268 -800077b0: 0f010793 addi a5,sp,240 -800077b4: 0007d883 lhu a7,0(a5) -800077b8: 00075603 lhu a2,0(a4) -800077bc: 00278793 addi a5,a5,2 -800077c0: 00270713 addi a4,a4,2 -800077c4: 02c89863 bne a7,a2,800077f4 <_ldtoa_r+0x1150> -800077c8: 10610613 addi a2,sp,262 -800077cc: fec794e3 bne a5,a2,800077b4 <_ldtoa_r+0x1110> -800077d0: 0ec15703 lhu a4,236(sp) -800077d4: 10815783 lhu a5,264(sp) -800077d8: 06f70263 beq a4,a5,8000783c <_ldtoa_r+0x1198> -800077dc: 000c8793 mv a5,s9 -800077e0: 0e410713 addi a4,sp,228 -800077e4: 00278793 addi a5,a5,2 -800077e8: fe079f23 sh zero,-2(a5) -800077ec: fee79ce3 bne a5,a4,800077e4 <_ldtoa_r+0x1140> -800077f0: a8dff06f j 8000727c <_ldtoa_r+0xbd8> -800077f4: 0d166663 bltu a2,a7,800078c0 <_ldtoa_r+0x121c> -800077f8: 12010793 addi a5,sp,288 -800077fc: 10410513 addi a0,sp,260 -80007800: d09ff06f j 80007508 <_ldtoa_r+0xe64> -80007804: 00000713 li a4,0 -80007808: 0ee10313 addi t1,sp,238 -8000780c: 0007d803 lhu a6,0(a5) -80007810: 00055603 lhu a2,0(a0) -80007814: ffe78793 addi a5,a5,-2 -80007818: ffe50513 addi a0,a0,-2 -8000781c: 01060633 add a2,a2,a6 -80007820: 00e60733 add a4,a2,a4 -80007824: 01075613 srli a2,a4,0x10 -80007828: 00e79123 sh a4,2(a5) -8000782c: 00167713 andi a4,a2,1 -80007830: fc651ee3 bne a0,t1,8000780c <_ldtoa_r+0x1168> -80007834: 00000613 li a2,0 -80007838: d15ff06f j 8000754c <_ldtoa_r+0xea8> -8000783c: 00068713 mv a4,a3 -80007840: 06069263 bnez a3,800078a4 <_ldtoa_r+0x1200> -80007844: 10e11783 lh a5,270(sp) -80007848: 0407ce63 bltz a5,800078a4 <_ldtoa_r+0x1200> -8000784c: 12010693 addi a3,sp,288 -80007850: 0200006f j 80007870 <_ldtoa_r+0x11cc> -80007854: 00f69023 sh a5,0(a3) -80007858: 00171713 slli a4,a4,0x1 -8000785c: 01071713 slli a4,a4,0x10 -80007860: ffe68693 addi a3,a3,-2 -80007864: 10a10793 addi a5,sp,266 -80007868: 01075713 srli a4,a4,0x10 -8000786c: cef688e3 beq a3,a5,8000755c <_ldtoa_r+0xeb8> -80007870: 0006d783 lhu a5,0(a3) -80007874: 01079613 slli a2,a5,0x10 -80007878: 41065613 srai a2,a2,0x10 -8000787c: 00179793 slli a5,a5,0x1 -80007880: 00065463 bgez a2,80007888 <_ldtoa_r+0x11e4> -80007884: 00176713 ori a4,a4,1 -80007888: 01079793 slli a5,a5,0x10 -8000788c: 0107d793 srli a5,a5,0x10 -80007890: 00277613 andi a2,a4,2 -80007894: 0017e593 ori a1,a5,1 -80007898: fa060ee3 beqz a2,80007854 <_ldtoa_r+0x11b0> -8000789c: 00b69023 sh a1,0(a3) -800078a0: fb9ff06f j 80007858 <_ldtoa_r+0x11b4> -800078a4: 10c10613 addi a2,sp,268 -800078a8: 12010793 addi a5,sp,288 -800078ac: 08071263 bnez a4,80007930 <_ldtoa_r+0x128c> -800078b0: 08c78263 beq a5,a2,80007934 <_ldtoa_r+0x1290> -800078b4: 00065703 lhu a4,0(a2) -800078b8: 00260613 addi a2,a2,2 -800078bc: ff1ff06f j 800078ac <_ldtoa_r+0x1208> -800078c0: 02412603 lw a2,36(sp) -800078c4: 10810713 addi a4,sp,264 -800078c8: 12010793 addi a5,sp,288 -800078cc: 00075503 lhu a0,0(a4) -800078d0: 00270713 addi a4,a4,2 -800078d4: 00260613 addi a2,a2,2 -800078d8: fea61f23 sh a0,-2(a2) -800078dc: fef718e3 bne a4,a5,800078cc <_ldtoa_r+0x1228> -800078e0: 12011e23 sh zero,316(sp) -800078e4: 10810613 addi a2,sp,264 -800078e8: 0ec10713 addi a4,sp,236 -800078ec: 10410513 addi a0,sp,260 -800078f0: 00075803 lhu a6,0(a4) -800078f4: 00270713 addi a4,a4,2 -800078f8: 00260613 addi a2,a2,2 -800078fc: ff061f23 sh a6,-2(a2) -80007900: fea718e3 bne a4,a0,800078f0 <_ldtoa_r+0x124c> -80007904: 02412703 lw a4,36(sp) -80007908: 12011023 sh zero,288(sp) -8000790c: 0ec10893 addi a7,sp,236 -80007910: 13c10613 addi a2,sp,316 -80007914: 00075803 lhu a6,0(a4) -80007918: 00270713 addi a4,a4,2 -8000791c: 00288893 addi a7,a7,2 -80007920: ff089f23 sh a6,-2(a7) -80007924: fec718e3 bne a4,a2,80007914 <_ldtoa_r+0x1270> -80007928: 10011223 sh zero,260(sp) -8000792c: bddff06f j 80007508 <_ldtoa_r+0xe64> -80007930: 00168513 addi a0,a3,1 -80007934: 10a11523 sh a0,266(sp) -80007938: c25ff06f j 8000755c <_ldtoa_r+0xeb8> +8000723c: 0c810613 addi a2,sp,200 +80007240: 0007d683 lhu a3,0(a5) +80007244: 00278793 addi a5,a5,2 +80007248: 00270713 addi a4,a4,2 +8000724c: fed71f23 sh a3,-2(a4) +80007250: fec798e3 bne a5,a2,80007240 <_ldtoa_r+0xc60> +80007254: 00000713 li a4,0 +80007258: 09810793 addi a5,sp,152 +8000725c: 0080006f j 80007264 <_ldtoa_r+0xc84> +80007260: 000c5703 lhu a4,0(s8) +80007264: 00278793 addi a5,a5,2 +80007268: fee79f23 sh a4,-2(a5) +8000726c: 002c0c13 addi s8,s8,2 +80007270: ffa798e3 bne a5,s10,80007260 <_ldtoa_r+0xc80> +80007274: 028d8d13 addi s10,s11,40 +80007278: 00001c37 lui s8,0x1 +8000727c: 118d8d93 addi s11,s11,280 +80007280: 0100006f j 80007290 <_ldtoa_r+0xcb0> +80007284: 001c5c13 srli s8,s8,0x1 +80007288: 29bd0063 beq s10,s11,80007508 <_ldtoa_r+0xf28> +8000728c: 014d0d13 addi s10,s10,20 +80007290: 000c8593 mv a1,s9 +80007294: 000d8513 mv a0,s11 +80007298: de9fd0ef jal ra,80005080 +8000729c: 00050793 mv a5,a0 +800072a0: 000c8593 mv a1,s9 +800072a4: 000d0513 mv a0,s10 +800072a8: 26f04063 bgtz a5,80007508 <_ldtoa_r+0xf28> +800072ac: dd5fd0ef jal ra,80005080 +800072b0: fca04ae3 bgtz a0,80007284 <_ldtoa_r+0xca4> +800072b4: 00090693 mv a3,s2 +800072b8: 000c8613 mv a2,s9 +800072bc: 000c8593 mv a1,s9 +800072c0: 000d0513 mv a0,s10 +800072c4: cc9fe0ef jal ra,80005f8c +800072c8: 09810613 addi a2,sp,152 +800072cc: 00090693 mv a3,s2 +800072d0: 00060593 mv a1,a2 +800072d4: 000d0513 mv a0,s10 +800072d8: 89dfe0ef jal ra,80005b74 +800072dc: 018484b3 add s1,s1,s8 +800072e0: fa5ff06f j 80007284 <_ldtoa_r+0xca4> +800072e4: 12410a93 addi s5,sp,292 +800072e8: 800155b7 lui a1,0x80015 +800072ec: d6458593 addi a1,a1,-668 # 80014d64 <__BSS_END__+0xffffe128> +800072f0: 000a8513 mv a0,s5 +800072f4: 000024b7 lui s1,0x2 +800072f8: 320020ef jal ra,80009618 +800072fc: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> +80007300: ae1ff06f j 80006de0 <_ldtoa_r+0x800> +80007304: 12710c13 addi s8,sp,295 +80007308: ac0792e3 bnez a5,80006dcc <_ldtoa_r+0x7ec> +8000730c: 01812823 sw s8,16(sp) +80007310: 865ff06f j 80006b74 <_ldtoa_r+0x594> +80007314: 04c10793 addi a5,sp,76 +80007318: 000c8713 mv a4,s9 +8000731c: 00c0006f j 80007328 <_ldtoa_r+0xd48> +80007320: 05e10693 addi a3,sp,94 +80007324: e8f68ae3 beq a3,a5,800071b8 <_ldtoa_r+0xbd8> +80007328: 0007d603 lhu a2,0(a5) +8000732c: 00075683 lhu a3,0(a4) +80007330: 00278793 addi a5,a5,2 +80007334: 00270713 addi a4,a4,2 +80007338: fed604e3 beq a2,a3,80007320 <_ldtoa_r+0xd40> +8000733c: 0e215783 lhu a5,226(sp) +80007340: 01c12703 lw a4,28(sp) +80007344: 00f777b3 and a5,a4,a5 +80007348: 00e79e63 bne a5,a4,80007364 <_ldtoa_r+0xd84> +8000734c: 000c8513 mv a0,s9 +80007350: b89fd0ef jal ra,80004ed8 +80007354: e60512e3 bnez a0,800071b8 <_ldtoa_r+0xbd8> +80007358: 000c8513 mv a0,s9 +8000735c: e41fd0ef jal ra,8000519c +80007360: e4051ce3 bnez a0,800071b8 <_ldtoa_r+0xbd8> +80007364: 0ec10593 addi a1,sp,236 +80007368: 000c0513 mv a0,s8 +8000736c: c1dfd0ef jal ra,80004f88 +80007370: 10810593 addi a1,sp,264 +80007374: 000c8513 mv a0,s9 +80007378: c11fd0ef jal ra,80004f88 +8000737c: 0ec15603 lhu a2,236(sp) +80007380: 10a15503 lhu a0,266(sp) +80007384: 0ee15883 lhu a7,238(sp) +80007388: fff64613 not a2,a2 +8000738c: 01061613 slli a2,a2,0x10 +80007390: 01065613 srli a2,a2,0x10 +80007394: 0ec11623 sh a2,236(sp) +80007398: 40a885b3 sub a1,a7,a0 +8000739c: 00050693 mv a3,a0 +800073a0: 06b05e63 blez a1,8000741c <_ldtoa_r+0xe3c> +800073a4: 02412683 lw a3,36(sp) +800073a8: 10810713 addi a4,sp,264 +800073ac: 12010793 addi a5,sp,288 +800073b0: 00075583 lhu a1,0(a4) +800073b4: 00270713 addi a4,a4,2 +800073b8: 00268693 addi a3,a3,2 +800073bc: feb69f23 sh a1,-2(a3) +800073c0: fef718e3 bne a4,a5,800073b0 <_ldtoa_r+0xdd0> +800073c4: 12011e23 sh zero,316(sp) +800073c8: 10810713 addi a4,sp,264 +800073cc: 0ec10693 addi a3,sp,236 +800073d0: 0080006f j 800073d8 <_ldtoa_r+0xdf8> +800073d4: 0006d603 lhu a2,0(a3) +800073d8: 00270713 addi a4,a4,2 +800073dc: fec71f23 sh a2,-2(a4) +800073e0: 00268693 addi a3,a3,2 +800073e4: fef718e3 bne a4,a5,800073d4 <_ldtoa_r+0xdf4> +800073e8: 02412783 lw a5,36(sp) +800073ec: 12011023 sh zero,288(sp) +800073f0: 0ec10713 addi a4,sp,236 +800073f4: 13c10613 addi a2,sp,316 +800073f8: 0007d683 lhu a3,0(a5) +800073fc: 00278793 addi a5,a5,2 +80007400: 00270713 addi a4,a4,2 +80007404: fed71f23 sh a3,-2(a4) +80007408: fec798e3 bne a5,a2,800073f8 <_ldtoa_r+0xe18> +8000740c: 10a15683 lhu a3,266(sp) +80007410: 411505b3 sub a1,a0,a7 +80007414: 10011223 sh zero,260(sp) +80007418: 00068513 mv a0,a3 +8000741c: 2c058663 beqz a1,800076e8 <_ldtoa_r+0x1108> +80007420: 02d12623 sw a3,44(sp) +80007424: f6f00793 li a5,-145 +80007428: 06f5c863 blt a1,a5,80007498 <_ldtoa_r+0xeb8> +8000742c: 0ec10513 addi a0,sp,236 +80007430: d89fd0ef jal ra,800051b8 +80007434: 02c12683 lw a3,44(sp) +80007438: 00050593 mv a1,a0 +8000743c: 12010793 addi a5,sp,288 +80007440: 10410513 addi a0,sp,260 +80007444: 0ec15603 lhu a2,236(sp) +80007448: 10815703 lhu a4,264(sp) +8000744c: 2ee60a63 beq a2,a4,80007740 <_ldtoa_r+0x1160> +80007450: 00000713 li a4,0 +80007454: 00070613 mv a2,a4 +80007458: 0007d703 lhu a4,0(a5) +8000745c: 00055803 lhu a6,0(a0) +80007460: ffe78793 addi a5,a5,-2 +80007464: 40c70733 sub a4,a4,a2 +80007468: 41070733 sub a4,a4,a6 +8000746c: 01075613 srli a2,a4,0x10 +80007470: 00e79123 sh a4,2(a5) +80007474: 10a10713 addi a4,sp,266 +80007478: 00167613 andi a2,a2,1 +8000747c: ffe50513 addi a0,a0,-2 +80007480: fce79ce3 bne a5,a4,80007458 <_ldtoa_r+0xe78> +80007484: 00100613 li a2,1 +80007488: 00090793 mv a5,s2 +8000748c: 04000713 li a4,64 +80007490: 10810513 addi a0,sp,264 +80007494: 8bcfe0ef jal ra,80005550 +80007498: 000c8593 mv a1,s9 +8000749c: 10810513 addi a0,sp,264 +800074a0: e24fe0ef jal ra,80005ac4 +800074a4: d15ff06f j 800071b8 <_ldtoa_r+0xbd8> +800074a8: 00812783 lw a5,8(sp) +800074ac: fff78493 addi s1,a5,-1 +800074b0: b45ff06f j 80006ff4 <_ldtoa_r+0xa14> +800074b4: 00c12783 lw a5,12(sp) +800074b8: 12010223 sb zero,292(sp) +800074bc: 000a8413 mv s0,s5 +800074c0: 0007a023 sw zero,0(a5) +800074c4: af9ff06f j 80006fbc <_ldtoa_r+0x9dc> +800074c8: 000c8793 mv a5,s9 +800074cc: 0e410713 addi a4,sp,228 +800074d0: 00278793 addi a5,a5,2 +800074d4: fe079f23 sh zero,-2(a5) +800074d8: fee79ce3 bne a5,a4,800074d0 <_ldtoa_r+0xef0> +800074dc: cd1ff06f j 800071ac <_ldtoa_r+0xbcc> +800074e0: 01012783 lw a5,16(sp) +800074e4: 12410a93 addi s5,sp,292 +800074e8: 06078a63 beqz a5,8000755c <_ldtoa_r+0xf7c> +800074ec: 800155b7 lui a1,0x80015 +800074f0: d6c58593 addi a1,a1,-660 # 80014d6c <__BSS_END__+0xffffe130> +800074f4: 000a8513 mv a0,s5 +800074f8: 000024b7 lui s1,0x2 +800074fc: 11c020ef jal ra,80009618 +80007500: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> +80007504: 8ddff06f j 80006de0 <_ldtoa_r+0x800> +80007508: 0e810b93 addi s7,sp,232 +8000750c: bd8ff06f j 800068e4 <_ldtoa_r+0x304> +80007510: 03100793 li a5,49 +80007514: fef90f23 sb a5,-2(s2) +80007518: 00148493 addi s1,s1,1 +8000751c: 8b1ff06f j 80006dcc <_ldtoa_r+0x7ec> +80007520: 00178793 addi a5,a5,1 +80007524: 00f70023 sb a5,0(a4) +80007528: 8a5ff06f j 80006dcc <_ldtoa_r+0x7ec> +8000752c: 12410a93 addi s5,sp,292 +80007530: 800155b7 lui a1,0x80015 +80007534: d8458593 addi a1,a1,-636 # 80014d84 <__BSS_END__+0xffffe148> +80007538: 000a8513 mv a0,s5 +8000753c: 000024b7 lui s1,0x2 +80007540: 0d8020ef jal ra,80009618 +80007544: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> +80007548: 899ff06f j 80006de0 <_ldtoa_r+0x800> +8000754c: 1ac15783 lhu a5,428(sp) +80007550: 12610c13 addi s8,sp,294 +80007554: 12710913 addi s2,sp,295 +80007558: 815ff06f j 80006d6c <_ldtoa_r+0x78c> +8000755c: 800155b7 lui a1,0x80015 +80007560: d7858593 addi a1,a1,-648 # 80014d78 <__BSS_END__+0xffffe13c> +80007564: 000a8513 mv a0,s5 +80007568: 000024b7 lui s1,0x2 +8000756c: 0ac020ef jal ra,80009618 +80007570: 70f48493 addi s1,s1,1807 # 270f <_start-0x7fffd8f1> +80007574: 86dff06f j 80006de0 <_ldtoa_r+0x800> +80007578: 09810593 addi a1,sp,152 +8000757c: 07c10513 addi a0,sp,124 +80007580: d44fe0ef jal ra,80005ac4 +80007584: d8cb0593 addi a1,s6,-628 +80007588: 09810513 addi a0,sp,152 +8000758c: af5fd0ef jal ra,80005080 +80007590: fe051663 bnez a0,80006d7c <_ldtoa_r+0x79c> +80007594: 82044ce3 bltz s0,80006dcc <_ldtoa_r+0x7ec> +80007598: ffe94783 lbu a5,-2(s2) +8000759c: fd278713 addi a4,a5,-46 +800075a0: 00173713 seqz a4,a4 +800075a4: fff74713 not a4,a4 +800075a8: 00ec0733 add a4,s8,a4 +800075ac: 00074703 lbu a4,0(a4) +800075b0: 00177713 andi a4,a4,1 +800075b4: 80070ce3 beqz a4,80006dcc <_ldtoa_r+0x7ec> +800075b8: ffe90713 addi a4,s2,-2 +800075bc: 07f7f793 andi a5,a5,127 +800075c0: fccff06f j 80006d8c <_ldtoa_r+0x7ac> +800075c4: 00178793 addi a5,a5,1 +800075c8: fef70fa3 sb a5,-1(a4) +800075cc: 801ff06f j 80006dcc <_ldtoa_r+0x7ec> +800075d0: 0d010413 addi s0,sp,208 +800075d4: 00040593 mv a1,s0 +800075d8: 07c10513 addi a0,sp,124 +800075dc: 00004cb7 lui s9,0x4 +800075e0: 9a9fd0ef jal ra,80004f88 +800075e4: 00000493 li s1,0 +800075e8: 0e810b93 addi s7,sp,232 +800075ec: 0cc10913 addi s2,sp,204 +800075f0: 0d210a93 addi s5,sp,210 +800075f4: ffec8c93 addi s9,s9,-2 # 3ffe <_start-0x7fffc002> +800075f8: 0e815783 lhu a5,232(sp) +800075fc: 0077f793 andi a5,a5,7 +80007600: 0c079a63 bnez a5,800076d4 <_ldtoa_r+0x10f4> +80007604: 0b410713 addi a4,sp,180 +80007608: 00040793 mv a5,s0 +8000760c: 0007d683 lhu a3,0(a5) +80007610: 00278793 addi a5,a5,2 +80007614: 00270713 addi a4,a4,2 +80007618: fed71f23 sh a3,-2(a4) +8000761c: ff7798e3 bne a5,s7,8000760c <_ldtoa_r+0x102c> +80007620: 0b410513 addi a0,sp,180 +80007624: 0c011623 sh zero,204(sp) +80007628: f40fd0ef jal ra,80004d68 +8000762c: 0b410513 addi a0,sp,180 +80007630: f38fd0ef jal ra,80004d68 +80007634: 00000613 li a2,0 +80007638: 00090693 mv a3,s2 +8000763c: 000b8713 mv a4,s7 +80007640: 0006d583 lhu a1,0(a3) +80007644: 00075783 lhu a5,0(a4) +80007648: ffe68693 addi a3,a3,-2 +8000764c: ffe70713 addi a4,a4,-2 +80007650: 00b787b3 add a5,a5,a1 +80007654: 00c787b3 add a5,a5,a2 +80007658: 0107d613 srli a2,a5,0x10 +8000765c: 00f69123 sh a5,2(a3) +80007660: 00167613 andi a2,a2,1 +80007664: fd571ee3 bne a4,s5,80007640 <_ldtoa_r+0x1060> +80007668: 0b615783 lhu a5,182(sp) +8000766c: 0b815703 lhu a4,184(sp) +80007670: 00378793 addi a5,a5,3 +80007674: 0af11b23 sh a5,182(sp) +80007678: 02070063 beqz a4,80007698 <_ldtoa_r+0x10b8> +8000767c: 0b410513 addi a0,sp,180 +80007680: ee8fd0ef jal ra,80004d68 +80007684: 0b615783 lhu a5,182(sp) +80007688: 0b815703 lhu a4,184(sp) +8000768c: 00178793 addi a5,a5,1 +80007690: 0af11b23 sh a5,182(sp) +80007694: fe0714e3 bnez a4,8000767c <_ldtoa_r+0x109c> +80007698: 0cc15783 lhu a5,204(sp) +8000769c: 02079c63 bnez a5,800076d4 <_ldtoa_r+0x10f4> +800076a0: 0b615783 lhu a5,182(sp) +800076a4: 02fce863 bltu s9,a5,800076d4 <_ldtoa_r+0x10f4> +800076a8: 00040713 mv a4,s0 +800076ac: 0b410793 addi a5,sp,180 +800076b0: 0007d683 lhu a3,0(a5) +800076b4: 00278793 addi a5,a5,2 +800076b8: 00270713 addi a4,a4,2 +800076bc: fed71f23 sh a3,-2(a4) +800076c0: ff2798e3 bne a5,s2,800076b0 <_ldtoa_r+0x10d0> +800076c4: 0e011423 sh zero,232(sp) +800076c8: fff48493 addi s1,s1,-1 +800076cc: fd500793 li a5,-43 +800076d0: f2f494e3 bne s1,a5,800075f8 <_ldtoa_r+0x1018> +800076d4: 07c10593 addi a1,sp,124 +800076d8: 00040513 mv a0,s0 +800076dc: be8fe0ef jal ra,80005ac4 +800076e0: 16010913 addi s2,sp,352 +800076e4: 8f4ff06f j 800067d8 <_ldtoa_r+0x1f8> +800076e8: 10c10713 addi a4,sp,268 +800076ec: 0f010793 addi a5,sp,240 +800076f0: 0007d883 lhu a7,0(a5) +800076f4: 00075603 lhu a2,0(a4) +800076f8: 00278793 addi a5,a5,2 +800076fc: 00270713 addi a4,a4,2 +80007700: 02c89863 bne a7,a2,80007730 <_ldtoa_r+0x1150> +80007704: 10610613 addi a2,sp,262 +80007708: fec794e3 bne a5,a2,800076f0 <_ldtoa_r+0x1110> +8000770c: 0ec15703 lhu a4,236(sp) +80007710: 10815783 lhu a5,264(sp) +80007714: 06f70263 beq a4,a5,80007778 <_ldtoa_r+0x1198> +80007718: 000c8793 mv a5,s9 +8000771c: 0e410713 addi a4,sp,228 +80007720: 00278793 addi a5,a5,2 +80007724: fe079f23 sh zero,-2(a5) +80007728: fee79ce3 bne a5,a4,80007720 <_ldtoa_r+0x1140> +8000772c: a8dff06f j 800071b8 <_ldtoa_r+0xbd8> +80007730: 0d166663 bltu a2,a7,800077fc <_ldtoa_r+0x121c> +80007734: 12010793 addi a5,sp,288 +80007738: 10410513 addi a0,sp,260 +8000773c: d09ff06f j 80007444 <_ldtoa_r+0xe64> +80007740: 00000713 li a4,0 +80007744: 0ee10313 addi t1,sp,238 +80007748: 0007d803 lhu a6,0(a5) +8000774c: 00055603 lhu a2,0(a0) +80007750: ffe78793 addi a5,a5,-2 +80007754: ffe50513 addi a0,a0,-2 +80007758: 01060633 add a2,a2,a6 +8000775c: 00e60733 add a4,a2,a4 +80007760: 01075613 srli a2,a4,0x10 +80007764: 00e79123 sh a4,2(a5) +80007768: 00167713 andi a4,a2,1 +8000776c: fc651ee3 bne a0,t1,80007748 <_ldtoa_r+0x1168> +80007770: 00000613 li a2,0 +80007774: d15ff06f j 80007488 <_ldtoa_r+0xea8> +80007778: 00068713 mv a4,a3 +8000777c: 06069263 bnez a3,800077e0 <_ldtoa_r+0x1200> +80007780: 10e11783 lh a5,270(sp) +80007784: 0407ce63 bltz a5,800077e0 <_ldtoa_r+0x1200> +80007788: 12010693 addi a3,sp,288 +8000778c: 0200006f j 800077ac <_ldtoa_r+0x11cc> +80007790: 00f69023 sh a5,0(a3) +80007794: 00171713 slli a4,a4,0x1 +80007798: 01071713 slli a4,a4,0x10 +8000779c: ffe68693 addi a3,a3,-2 +800077a0: 10a10793 addi a5,sp,266 +800077a4: 01075713 srli a4,a4,0x10 +800077a8: cef688e3 beq a3,a5,80007498 <_ldtoa_r+0xeb8> +800077ac: 0006d783 lhu a5,0(a3) +800077b0: 01079613 slli a2,a5,0x10 +800077b4: 41065613 srai a2,a2,0x10 +800077b8: 00179793 slli a5,a5,0x1 +800077bc: 00065463 bgez a2,800077c4 <_ldtoa_r+0x11e4> +800077c0: 00176713 ori a4,a4,1 +800077c4: 01079793 slli a5,a5,0x10 +800077c8: 0107d793 srli a5,a5,0x10 +800077cc: 00277613 andi a2,a4,2 +800077d0: 0017e593 ori a1,a5,1 +800077d4: fa060ee3 beqz a2,80007790 <_ldtoa_r+0x11b0> +800077d8: 00b69023 sh a1,0(a3) +800077dc: fb9ff06f j 80007794 <_ldtoa_r+0x11b4> +800077e0: 10c10613 addi a2,sp,268 +800077e4: 12010793 addi a5,sp,288 +800077e8: 08071263 bnez a4,8000786c <_ldtoa_r+0x128c> +800077ec: 08c78263 beq a5,a2,80007870 <_ldtoa_r+0x1290> +800077f0: 00065703 lhu a4,0(a2) +800077f4: 00260613 addi a2,a2,2 +800077f8: ff1ff06f j 800077e8 <_ldtoa_r+0x1208> +800077fc: 02412603 lw a2,36(sp) +80007800: 10810713 addi a4,sp,264 +80007804: 12010793 addi a5,sp,288 +80007808: 00075503 lhu a0,0(a4) +8000780c: 00270713 addi a4,a4,2 +80007810: 00260613 addi a2,a2,2 +80007814: fea61f23 sh a0,-2(a2) +80007818: fef718e3 bne a4,a5,80007808 <_ldtoa_r+0x1228> +8000781c: 12011e23 sh zero,316(sp) +80007820: 10810613 addi a2,sp,264 +80007824: 0ec10713 addi a4,sp,236 +80007828: 10410513 addi a0,sp,260 +8000782c: 00075803 lhu a6,0(a4) +80007830: 00270713 addi a4,a4,2 +80007834: 00260613 addi a2,a2,2 +80007838: ff061f23 sh a6,-2(a2) +8000783c: fea718e3 bne a4,a0,8000782c <_ldtoa_r+0x124c> +80007840: 02412703 lw a4,36(sp) +80007844: 12011023 sh zero,288(sp) +80007848: 0ec10893 addi a7,sp,236 +8000784c: 13c10613 addi a2,sp,316 +80007850: 00075803 lhu a6,0(a4) +80007854: 00270713 addi a4,a4,2 +80007858: 00288893 addi a7,a7,2 +8000785c: ff089f23 sh a6,-2(a7) +80007860: fec718e3 bne a4,a2,80007850 <_ldtoa_r+0x1270> +80007864: 10011223 sh zero,260(sp) +80007868: bddff06f j 80007444 <_ldtoa_r+0xe64> +8000786c: 00168513 addi a0,a3,1 +80007870: 10a11523 sh a0,266(sp) +80007874: c25ff06f j 80007498 <_ldtoa_r+0xeb8> -8000793c <_ldcheck>: -8000793c: 00852703 lw a4,8(a0) -80007940: 00c52783 lw a5,12(a0) -80007944: 00052603 lw a2,0(a0) -80007948: 00452683 lw a3,4(a0) -8000794c: fc010113 addi sp,sp,-64 -80007950: 00010513 mv a0,sp -80007954: 01410593 addi a1,sp,20 -80007958: 00e12423 sw a4,8(sp) -8000795c: 00f12623 sw a5,12(sp) -80007960: 02112e23 sw ra,60(sp) -80007964: 00c12023 sw a2,0(sp) -80007968: 00d12223 sw a3,4(sp) -8000796c: bf5fe0ef jal ra,80006560 -80007970: 02615783 lhu a5,38(sp) -80007974: 00000513 li a0,0 -80007978: fff7c793 not a5,a5 -8000797c: 01179713 slli a4,a5,0x11 -80007980: 00071a63 bnez a4,80007994 <_ldcheck+0x58> -80007984: 01410513 addi a0,sp,20 -80007988: e14fd0ef jal ra,80004f9c -8000798c: 00153513 seqz a0,a0 -80007990: 00150513 addi a0,a0,1 -80007994: 03c12083 lw ra,60(sp) -80007998: 04010113 addi sp,sp,64 +80007878 <_ldcheck>: +80007878: 00852703 lw a4,8(a0) +8000787c: 00c52783 lw a5,12(a0) +80007880: 00052603 lw a2,0(a0) +80007884: 00452683 lw a3,4(a0) +80007888: fc010113 addi sp,sp,-64 +8000788c: 00010513 mv a0,sp +80007890: 01410593 addi a1,sp,20 +80007894: 00e12423 sw a4,8(sp) +80007898: 00f12623 sw a5,12(sp) +8000789c: 02112e23 sw ra,60(sp) +800078a0: 00c12023 sw a2,0(sp) +800078a4: 00d12223 sw a3,4(sp) +800078a8: bf5fe0ef jal ra,8000649c +800078ac: 02615783 lhu a5,38(sp) +800078b0: 00000513 li a0,0 +800078b4: fff7c793 not a5,a5 +800078b8: 01179713 slli a4,a5,0x11 +800078bc: 00071a63 bnez a4,800078d0 <_ldcheck+0x58> +800078c0: 01410513 addi a0,sp,20 +800078c4: e14fd0ef jal ra,80004ed8 +800078c8: 00153513 seqz a0,a0 +800078cc: 00150513 addi a0,a0,1 +800078d0: 03c12083 lw ra,60(sp) +800078d4: 04010113 addi sp,sp,64 +800078d8: 00008067 ret + +800078dc <__localeconv_l>: +800078dc: 0f050513 addi a0,a0,240 +800078e0: 00008067 ret + +800078e4 <_localeconv_r>: +800078e4: 2b818513 addi a0,gp,696 # 80016ac0 <__global_locale+0xf0> +800078e8: 00008067 ret + +800078ec : +800078ec: 2b818513 addi a0,gp,696 # 80016ac0 <__global_locale+0xf0> +800078f0: 00008067 ret + +800078f4 <__swhatbuf_r>: +800078f4: f9010113 addi sp,sp,-112 +800078f8: 06812423 sw s0,104(sp) +800078fc: 00058413 mv s0,a1 +80007900: 00e59583 lh a1,14(a1) +80007904: 06912223 sw s1,100(sp) +80007908: 07212023 sw s2,96(sp) +8000790c: 06112623 sw ra,108(sp) +80007910: 00060493 mv s1,a2 +80007914: 00068913 mv s2,a3 +80007918: 0405ca63 bltz a1,8000796c <__swhatbuf_r+0x78> +8000791c: 00810613 addi a2,sp,8 +80007920: 3e4060ef jal ra,8000dd04 <_fstat_r> +80007924: 04054463 bltz a0,8000796c <__swhatbuf_r+0x78> +80007928: 00c12703 lw a4,12(sp) +8000792c: 0000f7b7 lui a5,0xf +80007930: 06c12083 lw ra,108(sp) +80007934: 00e7f7b3 and a5,a5,a4 +80007938: ffffe737 lui a4,0xffffe +8000793c: 00e787b3 add a5,a5,a4 +80007940: 06812403 lw s0,104(sp) +80007944: 0017b793 seqz a5,a5 +80007948: 00f92023 sw a5,0(s2) +8000794c: 40000793 li a5,1024 +80007950: 00f4a023 sw a5,0(s1) +80007954: 00001537 lui a0,0x1 +80007958: 06412483 lw s1,100(sp) +8000795c: 06012903 lw s2,96(sp) +80007960: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800> +80007964: 07010113 addi sp,sp,112 +80007968: 00008067 ret +8000796c: 00c45783 lhu a5,12(s0) +80007970: 00092023 sw zero,0(s2) +80007974: 0807f793 andi a5,a5,128 +80007978: 02078463 beqz a5,800079a0 <__swhatbuf_r+0xac> +8000797c: 06c12083 lw ra,108(sp) +80007980: 06812403 lw s0,104(sp) +80007984: 04000793 li a5,64 +80007988: 00f4a023 sw a5,0(s1) +8000798c: 06012903 lw s2,96(sp) +80007990: 06412483 lw s1,100(sp) +80007994: 00000513 li a0,0 +80007998: 07010113 addi sp,sp,112 8000799c: 00008067 ret +800079a0: 06c12083 lw ra,108(sp) +800079a4: 06812403 lw s0,104(sp) +800079a8: 40000793 li a5,1024 +800079ac: 00f4a023 sw a5,0(s1) +800079b0: 06012903 lw s2,96(sp) +800079b4: 06412483 lw s1,100(sp) +800079b8: 00000513 li a0,0 +800079bc: 07010113 addi sp,sp,112 +800079c0: 00008067 ret -800079a0 <__localeconv_l>: -800079a0: 0f050513 addi a0,a0,240 -800079a4: 00008067 ret - -800079a8 <_localeconv_r>: -800079a8: 2b818513 addi a0,gp,696 # 80016ac0 <__global_locale+0xf0> -800079ac: 00008067 ret - -800079b0 : -800079b0: 2b818513 addi a0,gp,696 # 80016ac0 <__global_locale+0xf0> -800079b4: 00008067 ret - -800079b8 <__swhatbuf_r>: -800079b8: f9010113 addi sp,sp,-112 -800079bc: 06812423 sw s0,104(sp) -800079c0: 00058413 mv s0,a1 -800079c4: 00e59583 lh a1,14(a1) -800079c8: 06912223 sw s1,100(sp) -800079cc: 07212023 sw s2,96(sp) -800079d0: 06112623 sw ra,108(sp) -800079d4: 00060493 mv s1,a2 -800079d8: 00068913 mv s2,a3 -800079dc: 0405ca63 bltz a1,80007a30 <__swhatbuf_r+0x78> -800079e0: 00810613 addi a2,sp,8 -800079e4: 3e4060ef jal ra,8000ddc8 <_fstat_r> -800079e8: 04054463 bltz a0,80007a30 <__swhatbuf_r+0x78> -800079ec: 00c12703 lw a4,12(sp) -800079f0: 0000f7b7 lui a5,0xf -800079f4: 06c12083 lw ra,108(sp) -800079f8: 00e7f7b3 and a5,a5,a4 -800079fc: ffffe737 lui a4,0xffffe -80007a00: 00e787b3 add a5,a5,a4 -80007a04: 06812403 lw s0,104(sp) -80007a08: 0017b793 seqz a5,a5 -80007a0c: 00f92023 sw a5,0(s2) -80007a10: 40000793 li a5,1024 -80007a14: 00f4a023 sw a5,0(s1) -80007a18: 00001537 lui a0,0x1 -80007a1c: 06412483 lw s1,100(sp) -80007a20: 06012903 lw s2,96(sp) -80007a24: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800> -80007a28: 07010113 addi sp,sp,112 -80007a2c: 00008067 ret -80007a30: 00c45783 lhu a5,12(s0) -80007a34: 00092023 sw zero,0(s2) -80007a38: 0807f793 andi a5,a5,128 -80007a3c: 02078463 beqz a5,80007a64 <__swhatbuf_r+0xac> -80007a40: 06c12083 lw ra,108(sp) -80007a44: 06812403 lw s0,104(sp) -80007a48: 04000793 li a5,64 -80007a4c: 00f4a023 sw a5,0(s1) -80007a50: 06012903 lw s2,96(sp) -80007a54: 06412483 lw s1,100(sp) -80007a58: 00000513 li a0,0 -80007a5c: 07010113 addi sp,sp,112 -80007a60: 00008067 ret -80007a64: 06c12083 lw ra,108(sp) -80007a68: 06812403 lw s0,104(sp) -80007a6c: 40000793 li a5,1024 -80007a70: 00f4a023 sw a5,0(s1) -80007a74: 06012903 lw s2,96(sp) -80007a78: 06412483 lw s1,100(sp) -80007a7c: 00000513 li a0,0 -80007a80: 07010113 addi sp,sp,112 +800079c4 <__smakebuf_r>: +800079c4: 00c5d783 lhu a5,12(a1) +800079c8: fe010113 addi sp,sp,-32 +800079cc: 00812c23 sw s0,24(sp) +800079d0: 00112e23 sw ra,28(sp) +800079d4: 00912a23 sw s1,20(sp) +800079d8: 01212823 sw s2,16(sp) +800079dc: 0027f793 andi a5,a5,2 +800079e0: 00058413 mv s0,a1 +800079e4: 02078863 beqz a5,80007a14 <__smakebuf_r+0x50> +800079e8: 04358793 addi a5,a1,67 +800079ec: 00f5a023 sw a5,0(a1) +800079f0: 00f5a823 sw a5,16(a1) +800079f4: 00100793 li a5,1 +800079f8: 00f5aa23 sw a5,20(a1) +800079fc: 01c12083 lw ra,28(sp) +80007a00: 01812403 lw s0,24(sp) +80007a04: 01412483 lw s1,20(sp) +80007a08: 01012903 lw s2,16(sp) +80007a0c: 02010113 addi sp,sp,32 +80007a10: 00008067 ret +80007a14: 00c10693 addi a3,sp,12 +80007a18: 00810613 addi a2,sp,8 +80007a1c: 00050493 mv s1,a0 +80007a20: ed5ff0ef jal ra,800078f4 <__swhatbuf_r> +80007a24: 00812583 lw a1,8(sp) +80007a28: 00050913 mv s2,a0 +80007a2c: 00048513 mv a0,s1 +80007a30: 0b4000ef jal ra,80007ae4 <_malloc_r> +80007a34: 00c41783 lh a5,12(s0) +80007a38: 04050863 beqz a0,80007a88 <__smakebuf_r+0xc4> +80007a3c: 80004737 lui a4,0x80004 +80007a40: 43070713 addi a4,a4,1072 # 80004430 <__BSS_END__+0xfffed7f4> +80007a44: 02e4ae23 sw a4,60(s1) +80007a48: 00812703 lw a4,8(sp) +80007a4c: 00c12683 lw a3,12(sp) +80007a50: 0807e793 ori a5,a5,128 +80007a54: 00f41623 sh a5,12(s0) +80007a58: 00a42023 sw a0,0(s0) +80007a5c: 00a42823 sw a0,16(s0) +80007a60: 00e42a23 sw a4,20(s0) +80007a64: 04069863 bnez a3,80007ab4 <__smakebuf_r+0xf0> +80007a68: 0127e7b3 or a5,a5,s2 +80007a6c: 01c12083 lw ra,28(sp) +80007a70: 00f41623 sh a5,12(s0) +80007a74: 01812403 lw s0,24(sp) +80007a78: 01412483 lw s1,20(sp) +80007a7c: 01012903 lw s2,16(sp) +80007a80: 02010113 addi sp,sp,32 80007a84: 00008067 ret +80007a88: 2007f713 andi a4,a5,512 +80007a8c: f60718e3 bnez a4,800079fc <__smakebuf_r+0x38> +80007a90: ffc7f793 andi a5,a5,-4 +80007a94: 0027e793 ori a5,a5,2 +80007a98: 04340713 addi a4,s0,67 +80007a9c: 00f41623 sh a5,12(s0) +80007aa0: 00100793 li a5,1 +80007aa4: 00e42023 sw a4,0(s0) +80007aa8: 00e42823 sw a4,16(s0) +80007aac: 00f42a23 sw a5,20(s0) +80007ab0: f4dff06f j 800079fc <__smakebuf_r+0x38> +80007ab4: 00e41583 lh a1,14(s0) +80007ab8: 00048513 mv a0,s1 +80007abc: 754060ef jal ra,8000e210 <_isatty_r> +80007ac0: 00051663 bnez a0,80007acc <__smakebuf_r+0x108> +80007ac4: 00c41783 lh a5,12(s0) +80007ac8: fa1ff06f j 80007a68 <__smakebuf_r+0xa4> +80007acc: 00c45703 lhu a4,12(s0) +80007ad0: ffc77713 andi a4,a4,-4 +80007ad4: 00176713 ori a4,a4,1 +80007ad8: 01071793 slli a5,a4,0x10 +80007adc: 4107d793 srai a5,a5,0x10 +80007ae0: f89ff06f j 80007a68 <__smakebuf_r+0xa4> -80007a88 <__smakebuf_r>: -80007a88: 00c5d783 lhu a5,12(a1) -80007a8c: fe010113 addi sp,sp,-32 -80007a90: 00812c23 sw s0,24(sp) -80007a94: 00112e23 sw ra,28(sp) -80007a98: 00912a23 sw s1,20(sp) -80007a9c: 01212823 sw s2,16(sp) -80007aa0: 0027f793 andi a5,a5,2 -80007aa4: 00058413 mv s0,a1 -80007aa8: 02078863 beqz a5,80007ad8 <__smakebuf_r+0x50> -80007aac: 04358793 addi a5,a1,67 -80007ab0: 00f5a023 sw a5,0(a1) -80007ab4: 00f5a823 sw a5,16(a1) -80007ab8: 00100793 li a5,1 -80007abc: 00f5aa23 sw a5,20(a1) -80007ac0: 01c12083 lw ra,28(sp) -80007ac4: 01812403 lw s0,24(sp) -80007ac8: 01412483 lw s1,20(sp) -80007acc: 01012903 lw s2,16(sp) -80007ad0: 02010113 addi sp,sp,32 -80007ad4: 00008067 ret -80007ad8: 00c10693 addi a3,sp,12 -80007adc: 00810613 addi a2,sp,8 -80007ae0: 00050493 mv s1,a0 -80007ae4: ed5ff0ef jal ra,800079b8 <__swhatbuf_r> -80007ae8: 00812583 lw a1,8(sp) -80007aec: 00050913 mv s2,a0 -80007af0: 00048513 mv a0,s1 -80007af4: 0b4000ef jal ra,80007ba8 <_malloc_r> -80007af8: 00c41783 lh a5,12(s0) -80007afc: 04050863 beqz a0,80007b4c <__smakebuf_r+0xc4> -80007b00: 80004737 lui a4,0x80004 -80007b04: 4f470713 addi a4,a4,1268 # 800044f4 <__BSS_END__+0xfffed8b8> -80007b08: 02e4ae23 sw a4,60(s1) -80007b0c: 00812703 lw a4,8(sp) -80007b10: 00c12683 lw a3,12(sp) -80007b14: 0807e793 ori a5,a5,128 -80007b18: 00f41623 sh a5,12(s0) -80007b1c: 00a42023 sw a0,0(s0) -80007b20: 00a42823 sw a0,16(s0) -80007b24: 00e42a23 sw a4,20(s0) -80007b28: 04069863 bnez a3,80007b78 <__smakebuf_r+0xf0> -80007b2c: 0127e7b3 or a5,a5,s2 -80007b30: 01c12083 lw ra,28(sp) -80007b34: 00f41623 sh a5,12(s0) -80007b38: 01812403 lw s0,24(sp) -80007b3c: 01412483 lw s1,20(sp) -80007b40: 01012903 lw s2,16(sp) -80007b44: 02010113 addi sp,sp,32 -80007b48: 00008067 ret -80007b4c: 2007f713 andi a4,a5,512 -80007b50: f60718e3 bnez a4,80007ac0 <__smakebuf_r+0x38> -80007b54: ffc7f793 andi a5,a5,-4 -80007b58: 0027e793 ori a5,a5,2 -80007b5c: 04340713 addi a4,s0,67 -80007b60: 00f41623 sh a5,12(s0) -80007b64: 00100793 li a5,1 -80007b68: 00e42023 sw a4,0(s0) -80007b6c: 00e42823 sw a4,16(s0) -80007b70: 00f42a23 sw a5,20(s0) -80007b74: f4dff06f j 80007ac0 <__smakebuf_r+0x38> -80007b78: 00e41583 lh a1,14(s0) -80007b7c: 00048513 mv a0,s1 -80007b80: 754060ef jal ra,8000e2d4 <_isatty_r> -80007b84: 00051663 bnez a0,80007b90 <__smakebuf_r+0x108> -80007b88: 00c41783 lh a5,12(s0) -80007b8c: fa1ff06f j 80007b2c <__smakebuf_r+0xa4> -80007b90: 00c45703 lhu a4,12(s0) -80007b94: ffc77713 andi a4,a4,-4 -80007b98: 00176713 ori a4,a4,1 -80007b9c: 01071793 slli a5,a4,0x10 -80007ba0: 4107d793 srai a5,a5,0x10 -80007ba4: f89ff06f j 80007b2c <__smakebuf_r+0xa4> +80007ae4 <_malloc_r>: +80007ae4: fd010113 addi sp,sp,-48 +80007ae8: 01312e23 sw s3,28(sp) +80007aec: 02112623 sw ra,44(sp) +80007af0: 02812423 sw s0,40(sp) +80007af4: 02912223 sw s1,36(sp) +80007af8: 03212023 sw s2,32(sp) +80007afc: 01412c23 sw s4,24(sp) +80007b00: 01512a23 sw s5,20(sp) +80007b04: 01612823 sw s6,16(sp) +80007b08: 01712623 sw s7,12(sp) +80007b0c: 01812423 sw s8,8(sp) +80007b10: 01912223 sw s9,4(sp) +80007b14: 00b58793 addi a5,a1,11 +80007b18: 01600713 li a4,22 +80007b1c: 00050993 mv s3,a0 +80007b20: 06f76463 bltu a4,a5,80007b88 <_malloc_r+0xa4> +80007b24: 01000793 li a5,16 +80007b28: 1eb7e263 bltu a5,a1,80007d0c <_malloc_r+0x228> +80007b2c: 101000ef jal ra,8000842c <__malloc_lock> +80007b30: 01000493 li s1,16 +80007b34: 00200613 li a2,2 +80007b38: 01800793 li a5,24 +80007b3c: dc018913 addi s2,gp,-576 # 800165c8 <__malloc_av_> +80007b40: 00f907b3 add a5,s2,a5 +80007b44: 0047a403 lw s0,4(a5) # f004 <_start-0x7fff0ffc> +80007b48: ff878713 addi a4,a5,-8 +80007b4c: 20e40863 beq s0,a4,80007d5c <_malloc_r+0x278> +80007b50: 00442783 lw a5,4(s0) +80007b54: 00c42683 lw a3,12(s0) +80007b58: 00842603 lw a2,8(s0) +80007b5c: ffc7f793 andi a5,a5,-4 +80007b60: 00f407b3 add a5,s0,a5 +80007b64: 0047a703 lw a4,4(a5) +80007b68: 00d62623 sw a3,12(a2) +80007b6c: 00c6a423 sw a2,8(a3) +80007b70: 00176713 ori a4,a4,1 +80007b74: 00098513 mv a0,s3 +80007b78: 00e7a223 sw a4,4(a5) +80007b7c: 0b5000ef jal ra,80008430 <__malloc_unlock> +80007b80: 00840513 addi a0,s0,8 +80007b84: 1940006f j 80007d18 <_malloc_r+0x234> +80007b88: ff87f493 andi s1,a5,-8 +80007b8c: 1807c063 bltz a5,80007d0c <_malloc_r+0x228> +80007b90: 16b4ee63 bltu s1,a1,80007d0c <_malloc_r+0x228> +80007b94: 099000ef jal ra,8000842c <__malloc_lock> +80007b98: 1f700793 li a5,503 +80007b9c: 4497fa63 bgeu a5,s1,80007ff0 <_malloc_r+0x50c> +80007ba0: 0094d793 srli a5,s1,0x9 +80007ba4: 1a078463 beqz a5,80007d4c <_malloc_r+0x268> +80007ba8: 00400713 li a4,4 +80007bac: 3cf76063 bltu a4,a5,80007f6c <_malloc_r+0x488> +80007bb0: 0064d793 srli a5,s1,0x6 +80007bb4: 03978613 addi a2,a5,57 +80007bb8: 03878513 addi a0,a5,56 +80007bbc: 00361693 slli a3,a2,0x3 +80007bc0: dc018913 addi s2,gp,-576 # 800165c8 <__malloc_av_> +80007bc4: 00d906b3 add a3,s2,a3 +80007bc8: 0046a403 lw s0,4(a3) +80007bcc: ff868693 addi a3,a3,-8 +80007bd0: 02868663 beq a3,s0,80007bfc <_malloc_r+0x118> +80007bd4: 00f00593 li a1,15 +80007bd8: 0100006f j 80007be8 <_malloc_r+0x104> +80007bdc: 32075263 bgez a4,80007f00 <_malloc_r+0x41c> +80007be0: 00c42403 lw s0,12(s0) +80007be4: 00868c63 beq a3,s0,80007bfc <_malloc_r+0x118> +80007be8: 00442783 lw a5,4(s0) +80007bec: ffc7f793 andi a5,a5,-4 +80007bf0: 40978733 sub a4,a5,s1 +80007bf4: fee5d4e3 bge a1,a4,80007bdc <_malloc_r+0xf8> +80007bf8: 00050613 mv a2,a0 +80007bfc: 01092403 lw s0,16(s2) +80007c00: 00890893 addi a7,s2,8 +80007c04: 17140863 beq s0,a7,80007d74 <_malloc_r+0x290> +80007c08: 00442503 lw a0,4(s0) +80007c0c: 00f00693 li a3,15 +80007c10: ffc57513 andi a0,a0,-4 +80007c14: 409507b3 sub a5,a0,s1 +80007c18: 40f6c263 blt a3,a5,8000801c <_malloc_r+0x538> +80007c1c: 01192a23 sw a7,20(s2) +80007c20: 01192823 sw a7,16(s2) +80007c24: 3c07dc63 bgez a5,80007ffc <_malloc_r+0x518> +80007c28: 1ff00793 li a5,511 +80007c2c: 2ea7e063 bltu a5,a0,80007f0c <_malloc_r+0x428> +80007c30: ff857793 andi a5,a0,-8 +80007c34: 00878793 addi a5,a5,8 +80007c38: 00492583 lw a1,4(s2) +80007c3c: 00f907b3 add a5,s2,a5 +80007c40: 0007a683 lw a3,0(a5) +80007c44: 00555513 srli a0,a0,0x5 +80007c48: 00100713 li a4,1 +80007c4c: 00a71733 sll a4,a4,a0 +80007c50: 00b76733 or a4,a4,a1 +80007c54: ff878593 addi a1,a5,-8 +80007c58: 00b42623 sw a1,12(s0) +80007c5c: 00d42423 sw a3,8(s0) +80007c60: 00e92223 sw a4,4(s2) +80007c64: 0087a023 sw s0,0(a5) +80007c68: 0086a623 sw s0,12(a3) +80007c6c: 40265793 srai a5,a2,0x2 +80007c70: 00100593 li a1,1 +80007c74: 00f595b3 sll a1,a1,a5 +80007c78: 10b76863 bltu a4,a1,80007d88 <_malloc_r+0x2a4> +80007c7c: 00e5f7b3 and a5,a1,a4 +80007c80: 02079463 bnez a5,80007ca8 <_malloc_r+0x1c4> +80007c84: 00159593 slli a1,a1,0x1 +80007c88: ffc67613 andi a2,a2,-4 +80007c8c: 00e5f7b3 and a5,a1,a4 +80007c90: 00460613 addi a2,a2,4 +80007c94: 00079a63 bnez a5,80007ca8 <_malloc_r+0x1c4> +80007c98: 00159593 slli a1,a1,0x1 +80007c9c: 00e5f7b3 and a5,a1,a4 +80007ca0: 00460613 addi a2,a2,4 +80007ca4: fe078ae3 beqz a5,80007c98 <_malloc_r+0x1b4> +80007ca8: 00f00813 li a6,15 +80007cac: 00361313 slli t1,a2,0x3 +80007cb0: 00690333 add t1,s2,t1 +80007cb4: 00030513 mv a0,t1 +80007cb8: 00c52783 lw a5,12(a0) +80007cbc: 00060e13 mv t3,a2 +80007cc0: 2cf50863 beq a0,a5,80007f90 <_malloc_r+0x4ac> +80007cc4: 0047a703 lw a4,4(a5) +80007cc8: 00078413 mv s0,a5 +80007ccc: 00c7a783 lw a5,12(a5) +80007cd0: ffc77713 andi a4,a4,-4 +80007cd4: 409706b3 sub a3,a4,s1 +80007cd8: 2cd84863 blt a6,a3,80007fa8 <_malloc_r+0x4c4> +80007cdc: fe06c2e3 bltz a3,80007cc0 <_malloc_r+0x1dc> +80007ce0: 00e40733 add a4,s0,a4 +80007ce4: 00472683 lw a3,4(a4) +80007ce8: 00842603 lw a2,8(s0) +80007cec: 00098513 mv a0,s3 +80007cf0: 0016e693 ori a3,a3,1 +80007cf4: 00d72223 sw a3,4(a4) +80007cf8: 00f62623 sw a5,12(a2) +80007cfc: 00c7a423 sw a2,8(a5) +80007d00: 730000ef jal ra,80008430 <__malloc_unlock> +80007d04: 00840513 addi a0,s0,8 +80007d08: 0100006f j 80007d18 <_malloc_r+0x234> +80007d0c: 00c00793 li a5,12 +80007d10: 00f9a023 sw a5,0(s3) +80007d14: 00000513 li a0,0 +80007d18: 02c12083 lw ra,44(sp) +80007d1c: 02812403 lw s0,40(sp) +80007d20: 02412483 lw s1,36(sp) +80007d24: 02012903 lw s2,32(sp) +80007d28: 01c12983 lw s3,28(sp) +80007d2c: 01812a03 lw s4,24(sp) +80007d30: 01412a83 lw s5,20(sp) +80007d34: 01012b03 lw s6,16(sp) +80007d38: 00c12b83 lw s7,12(sp) +80007d3c: 00812c03 lw s8,8(sp) +80007d40: 00412c83 lw s9,4(sp) +80007d44: 03010113 addi sp,sp,48 +80007d48: 00008067 ret +80007d4c: 20000693 li a3,512 +80007d50: 04000613 li a2,64 +80007d54: 03f00513 li a0,63 +80007d58: e69ff06f j 80007bc0 <_malloc_r+0xdc> +80007d5c: 00c7a403 lw s0,12(a5) +80007d60: 00260613 addi a2,a2,2 +80007d64: de8796e3 bne a5,s0,80007b50 <_malloc_r+0x6c> +80007d68: 01092403 lw s0,16(s2) +80007d6c: 00890893 addi a7,s2,8 +80007d70: e9141ce3 bne s0,a7,80007c08 <_malloc_r+0x124> +80007d74: 00492703 lw a4,4(s2) +80007d78: 40265793 srai a5,a2,0x2 +80007d7c: 00100593 li a1,1 +80007d80: 00f595b3 sll a1,a1,a5 +80007d84: eeb77ce3 bgeu a4,a1,80007c7c <_malloc_r+0x198> +80007d88: 00892403 lw s0,8(s2) +80007d8c: 00442a83 lw s5,4(s0) +80007d90: ffcafb13 andi s6,s5,-4 +80007d94: 009b6863 bltu s6,s1,80007da4 <_malloc_r+0x2c0> +80007d98: 409b07b3 sub a5,s6,s1 +80007d9c: 00f00713 li a4,15 +80007da0: 12f74c63 blt a4,a5,80007ed8 <_malloc_r+0x3f4> +80007da4: 39c1aa83 lw s5,924(gp) # 80016ba4 <__malloc_top_pad> +80007da8: 3641a703 lw a4,868(gp) # 80016b6c <__malloc_sbrk_base> +80007dac: fff00793 li a5,-1 +80007db0: 01640a33 add s4,s0,s6 +80007db4: 01548ab3 add s5,s1,s5 +80007db8: 34f70463 beq a4,a5,80008100 <_malloc_r+0x61c> +80007dbc: 000017b7 lui a5,0x1 +80007dc0: 00f78793 addi a5,a5,15 # 100f <_start-0x7fffeff1> +80007dc4: 00fa8ab3 add s5,s5,a5 +80007dc8: fffff7b7 lui a5,0xfffff +80007dcc: 00fafab3 and s5,s5,a5 +80007dd0: 000a8593 mv a1,s5 +80007dd4: 00098513 mv a0,s3 +80007dd8: 778010ef jal ra,80009550 <_sbrk_r> +80007ddc: fff00793 li a5,-1 +80007de0: 00050b93 mv s7,a0 +80007de4: 28f50663 beq a0,a5,80008070 <_malloc_r+0x58c> +80007de8: 29456263 bltu a0,s4,8000806c <_malloc_r+0x588> +80007dec: 40818c13 addi s8,gp,1032 # 80016c10 <__malloc_current_mallinfo> +80007df0: 000c2583 lw a1,0(s8) # 1000 <_start-0x7ffff000> +80007df4: 00ba85b3 add a1,s5,a1 +80007df8: 00bc2023 sw a1,0(s8) +80007dfc: 00058793 mv a5,a1 +80007e00: 38aa0e63 beq s4,a0,8000819c <_malloc_r+0x6b8> +80007e04: 3641a683 lw a3,868(gp) # 80016b6c <__malloc_sbrk_base> +80007e08: fff00713 li a4,-1 +80007e0c: 3ae68663 beq a3,a4,800081b8 <_malloc_r+0x6d4> +80007e10: 414b8a33 sub s4,s7,s4 +80007e14: 00fa07b3 add a5,s4,a5 +80007e18: 00fc2023 sw a5,0(s8) +80007e1c: 007bfc93 andi s9,s7,7 +80007e20: 300c8263 beqz s9,80008124 <_malloc_r+0x640> +80007e24: 000017b7 lui a5,0x1 +80007e28: 419b8bb3 sub s7,s7,s9 +80007e2c: 00878593 addi a1,a5,8 # 1008 <_start-0x7fffeff8> +80007e30: 008b8b93 addi s7,s7,8 +80007e34: 419585b3 sub a1,a1,s9 +80007e38: 015b8ab3 add s5,s7,s5 +80007e3c: fff78793 addi a5,a5,-1 +80007e40: 415585b3 sub a1,a1,s5 +80007e44: 00f5fa33 and s4,a1,a5 +80007e48: 000a0593 mv a1,s4 +80007e4c: 00098513 mv a0,s3 +80007e50: 700010ef jal ra,80009550 <_sbrk_r> +80007e54: fff00793 li a5,-1 +80007e58: 3af50a63 beq a0,a5,8000820c <_malloc_r+0x728> +80007e5c: 41750533 sub a0,a0,s7 +80007e60: 01450ab3 add s5,a0,s4 +80007e64: 000c2583 lw a1,0(s8) +80007e68: 01792423 sw s7,8(s2) +80007e6c: 001aea93 ori s5,s5,1 +80007e70: 00ba05b3 add a1,s4,a1 +80007e74: 00bc2023 sw a1,0(s8) +80007e78: 015ba223 sw s5,4(s7) +80007e7c: 35240263 beq s0,s2,800081c0 <_malloc_r+0x6dc> +80007e80: 00f00693 li a3,15 +80007e84: 3566f263 bgeu a3,s6,800081c8 <_malloc_r+0x6e4> +80007e88: 00442703 lw a4,4(s0) +80007e8c: ff4b0793 addi a5,s6,-12 +80007e90: ff87f793 andi a5,a5,-8 +80007e94: 00177713 andi a4,a4,1 +80007e98: 00f76733 or a4,a4,a5 +80007e9c: 00e42223 sw a4,4(s0) +80007ea0: 00500613 li a2,5 +80007ea4: 00f40733 add a4,s0,a5 +80007ea8: 00c72223 sw a2,4(a4) +80007eac: 00c72423 sw a2,8(a4) +80007eb0: 36f6e863 bltu a3,a5,80008220 <_malloc_r+0x73c> +80007eb4: 004baa83 lw s5,4(s7) +80007eb8: 000b8413 mv s0,s7 +80007ebc: 3981a703 lw a4,920(gp) # 80016ba0 <__malloc_max_sbrked_mem> +80007ec0: 00b77463 bgeu a4,a1,80007ec8 <_malloc_r+0x3e4> +80007ec4: 38b1ac23 sw a1,920(gp) # 80016ba0 <__malloc_max_sbrked_mem> +80007ec8: 3941a703 lw a4,916(gp) # 80016b9c <__malloc_max_total_mem> +80007ecc: 1ab77663 bgeu a4,a1,80008078 <_malloc_r+0x594> +80007ed0: 38b1aa23 sw a1,916(gp) # 80016b9c <__malloc_max_total_mem> +80007ed4: 1a40006f j 80008078 <_malloc_r+0x594> +80007ed8: 0014e713 ori a4,s1,1 +80007edc: 00e42223 sw a4,4(s0) +80007ee0: 009404b3 add s1,s0,s1 +80007ee4: 00992423 sw s1,8(s2) +80007ee8: 0017e793 ori a5,a5,1 +80007eec: 00098513 mv a0,s3 +80007ef0: 00f4a223 sw a5,4(s1) +80007ef4: 53c000ef jal ra,80008430 <__malloc_unlock> +80007ef8: 00840513 addi a0,s0,8 +80007efc: e1dff06f j 80007d18 <_malloc_r+0x234> +80007f00: 00c42683 lw a3,12(s0) +80007f04: 00842603 lw a2,8(s0) +80007f08: c59ff06f j 80007b60 <_malloc_r+0x7c> +80007f0c: 00955793 srli a5,a0,0x9 +80007f10: 00400713 li a4,4 +80007f14: 14f77263 bgeu a4,a5,80008058 <_malloc_r+0x574> +80007f18: 01400713 li a4,20 +80007f1c: 22f76a63 bltu a4,a5,80008150 <_malloc_r+0x66c> +80007f20: 05c78693 addi a3,a5,92 +80007f24: 05b78593 addi a1,a5,91 +80007f28: 00369693 slli a3,a3,0x3 +80007f2c: 00d906b3 add a3,s2,a3 +80007f30: 0006a783 lw a5,0(a3) +80007f34: ff868693 addi a3,a3,-8 +80007f38: 1cf68863 beq a3,a5,80008108 <_malloc_r+0x624> +80007f3c: 0047a703 lw a4,4(a5) +80007f40: ffc77713 andi a4,a4,-4 +80007f44: 00e57663 bgeu a0,a4,80007f50 <_malloc_r+0x46c> +80007f48: 0087a783 lw a5,8(a5) +80007f4c: fef698e3 bne a3,a5,80007f3c <_malloc_r+0x458> +80007f50: 00c7a683 lw a3,12(a5) +80007f54: 00492703 lw a4,4(s2) +80007f58: 00d42623 sw a3,12(s0) +80007f5c: 00f42423 sw a5,8(s0) +80007f60: 0086a423 sw s0,8(a3) +80007f64: 0087a623 sw s0,12(a5) +80007f68: d05ff06f j 80007c6c <_malloc_r+0x188> +80007f6c: 01400713 li a4,20 +80007f70: 12f77663 bgeu a4,a5,8000809c <_malloc_r+0x5b8> +80007f74: 05400713 li a4,84 +80007f78: 1ef76a63 bltu a4,a5,8000816c <_malloc_r+0x688> +80007f7c: 00c4d793 srli a5,s1,0xc +80007f80: 06f78613 addi a2,a5,111 +80007f84: 06e78513 addi a0,a5,110 +80007f88: 00361693 slli a3,a2,0x3 +80007f8c: c35ff06f j 80007bc0 <_malloc_r+0xdc> +80007f90: 001e0e13 addi t3,t3,1 +80007f94: 003e7793 andi a5,t3,3 +80007f98: 00850513 addi a0,a0,8 +80007f9c: 10078e63 beqz a5,800080b8 <_malloc_r+0x5d4> +80007fa0: 00c52783 lw a5,12(a0) +80007fa4: d1dff06f j 80007cc0 <_malloc_r+0x1dc> +80007fa8: 00842603 lw a2,8(s0) +80007fac: 0014e593 ori a1,s1,1 +80007fb0: 00b42223 sw a1,4(s0) +80007fb4: 00f62623 sw a5,12(a2) +80007fb8: 00c7a423 sw a2,8(a5) +80007fbc: 009404b3 add s1,s0,s1 +80007fc0: 00992a23 sw s1,20(s2) +80007fc4: 00992823 sw s1,16(s2) +80007fc8: 0016e793 ori a5,a3,1 +80007fcc: 0114a623 sw a7,12(s1) +80007fd0: 0114a423 sw a7,8(s1) +80007fd4: 00f4a223 sw a5,4(s1) +80007fd8: 00e40733 add a4,s0,a4 +80007fdc: 00098513 mv a0,s3 +80007fe0: 00d72023 sw a3,0(a4) +80007fe4: 44c000ef jal ra,80008430 <__malloc_unlock> +80007fe8: 00840513 addi a0,s0,8 +80007fec: d2dff06f j 80007d18 <_malloc_r+0x234> +80007ff0: 0034d613 srli a2,s1,0x3 +80007ff4: 00848793 addi a5,s1,8 +80007ff8: b45ff06f j 80007b3c <_malloc_r+0x58> +80007ffc: 00a40733 add a4,s0,a0 +80008000: 00472783 lw a5,4(a4) +80008004: 00098513 mv a0,s3 +80008008: 0017e793 ori a5,a5,1 +8000800c: 00f72223 sw a5,4(a4) +80008010: 420000ef jal ra,80008430 <__malloc_unlock> +80008014: 00840513 addi a0,s0,8 +80008018: d01ff06f j 80007d18 <_malloc_r+0x234> +8000801c: 0014e713 ori a4,s1,1 +80008020: 00e42223 sw a4,4(s0) +80008024: 009404b3 add s1,s0,s1 +80008028: 00992a23 sw s1,20(s2) +8000802c: 00992823 sw s1,16(s2) +80008030: 0017e713 ori a4,a5,1 +80008034: 0114a623 sw a7,12(s1) +80008038: 0114a423 sw a7,8(s1) +8000803c: 00e4a223 sw a4,4(s1) +80008040: 00a40533 add a0,s0,a0 +80008044: 00f52023 sw a5,0(a0) +80008048: 00098513 mv a0,s3 +8000804c: 3e4000ef jal ra,80008430 <__malloc_unlock> +80008050: 00840513 addi a0,s0,8 +80008054: cc5ff06f j 80007d18 <_malloc_r+0x234> +80008058: 00655793 srli a5,a0,0x6 +8000805c: 03978693 addi a3,a5,57 +80008060: 03878593 addi a1,a5,56 +80008064: 00369693 slli a3,a3,0x3 +80008068: ec5ff06f j 80007f2c <_malloc_r+0x448> +8000806c: 11240e63 beq s0,s2,80008188 <_malloc_r+0x6a4> +80008070: 00892403 lw s0,8(s2) +80008074: 00442a83 lw s5,4(s0) +80008078: ffcafa93 andi s5,s5,-4 +8000807c: 409a87b3 sub a5,s5,s1 +80008080: 009ae663 bltu s5,s1,8000808c <_malloc_r+0x5a8> +80008084: 00f00713 li a4,15 +80008088: e4f748e3 blt a4,a5,80007ed8 <_malloc_r+0x3f4> +8000808c: 00098513 mv a0,s3 +80008090: 3a0000ef jal ra,80008430 <__malloc_unlock> +80008094: 00000513 li a0,0 +80008098: c81ff06f j 80007d18 <_malloc_r+0x234> +8000809c: 05c78613 addi a2,a5,92 +800080a0: 05b78513 addi a0,a5,91 +800080a4: 00361693 slli a3,a2,0x3 +800080a8: b19ff06f j 80007bc0 <_malloc_r+0xdc> +800080ac: 00832783 lw a5,8(t1) +800080b0: fff60613 addi a2,a2,-1 +800080b4: 1c679063 bne a5,t1,80008274 <_malloc_r+0x790> +800080b8: 00367793 andi a5,a2,3 +800080bc: ff830313 addi t1,t1,-8 +800080c0: fe0796e3 bnez a5,800080ac <_malloc_r+0x5c8> +800080c4: 00492703 lw a4,4(s2) +800080c8: fff5c793 not a5,a1 +800080cc: 00e7f7b3 and a5,a5,a4 +800080d0: 00f92223 sw a5,4(s2) +800080d4: 00159593 slli a1,a1,0x1 +800080d8: cab7e8e3 bltu a5,a1,80007d88 <_malloc_r+0x2a4> +800080dc: ca0586e3 beqz a1,80007d88 <_malloc_r+0x2a4> +800080e0: 00f5f733 and a4,a1,a5 +800080e4: 00071a63 bnez a4,800080f8 <_malloc_r+0x614> +800080e8: 00159593 slli a1,a1,0x1 +800080ec: 00f5f733 and a4,a1,a5 +800080f0: 004e0e13 addi t3,t3,4 +800080f4: fe070ae3 beqz a4,800080e8 <_malloc_r+0x604> +800080f8: 000e0613 mv a2,t3 +800080fc: bb1ff06f j 80007cac <_malloc_r+0x1c8> +80008100: 010a8a93 addi s5,s5,16 # fffff010 <__BSS_END__+0x7ffe83d4> +80008104: ccdff06f j 80007dd0 <_malloc_r+0x2ec> +80008108: 00492503 lw a0,4(s2) +8000810c: 4025d593 srai a1,a1,0x2 +80008110: 00100713 li a4,1 +80008114: 00b71733 sll a4,a4,a1 +80008118: 00a76733 or a4,a4,a0 +8000811c: 00e92223 sw a4,4(s2) +80008120: e39ff06f j 80007f58 <_malloc_r+0x474> +80008124: 015b85b3 add a1,s7,s5 +80008128: 40b005b3 neg a1,a1 +8000812c: 01459593 slli a1,a1,0x14 +80008130: 0145da13 srli s4,a1,0x14 +80008134: 000a0593 mv a1,s4 +80008138: 00098513 mv a0,s3 +8000813c: 414010ef jal ra,80009550 <_sbrk_r> +80008140: fff00793 li a5,-1 +80008144: d0f51ce3 bne a0,a5,80007e5c <_malloc_r+0x378> +80008148: 00000a13 li s4,0 +8000814c: d19ff06f j 80007e64 <_malloc_r+0x380> +80008150: 05400713 li a4,84 +80008154: 08f76063 bltu a4,a5,800081d4 <_malloc_r+0x6f0> +80008158: 00c55793 srli a5,a0,0xc +8000815c: 06f78693 addi a3,a5,111 +80008160: 06e78593 addi a1,a5,110 +80008164: 00369693 slli a3,a3,0x3 +80008168: dc5ff06f j 80007f2c <_malloc_r+0x448> +8000816c: 15400713 li a4,340 +80008170: 08f76063 bltu a4,a5,800081f0 <_malloc_r+0x70c> +80008174: 00f4d793 srli a5,s1,0xf +80008178: 07878613 addi a2,a5,120 +8000817c: 07778513 addi a0,a5,119 +80008180: 00361693 slli a3,a2,0x3 +80008184: a3dff06f j 80007bc0 <_malloc_r+0xdc> +80008188: 40818c13 addi s8,gp,1032 # 80016c10 <__malloc_current_mallinfo> +8000818c: 000c2783 lw a5,0(s8) +80008190: 00fa87b3 add a5,s5,a5 +80008194: 00fc2023 sw a5,0(s8) +80008198: c6dff06f j 80007e04 <_malloc_r+0x320> +8000819c: 014a1713 slli a4,s4,0x14 +800081a0: c60712e3 bnez a4,80007e04 <_malloc_r+0x320> +800081a4: 00892403 lw s0,8(s2) +800081a8: 015b0ab3 add s5,s6,s5 +800081ac: 001aea93 ori s5,s5,1 +800081b0: 01542223 sw s5,4(s0) +800081b4: d09ff06f j 80007ebc <_malloc_r+0x3d8> +800081b8: 3771a223 sw s7,868(gp) # 80016b6c <__malloc_sbrk_base> +800081bc: c61ff06f j 80007e1c <_malloc_r+0x338> +800081c0: 000b8413 mv s0,s7 +800081c4: cf9ff06f j 80007ebc <_malloc_r+0x3d8> +800081c8: 00100793 li a5,1 +800081cc: 00fba223 sw a5,4(s7) +800081d0: ebdff06f j 8000808c <_malloc_r+0x5a8> +800081d4: 15400713 li a4,340 +800081d8: 06f76263 bltu a4,a5,8000823c <_malloc_r+0x758> +800081dc: 00f55793 srli a5,a0,0xf +800081e0: 07878693 addi a3,a5,120 +800081e4: 07778593 addi a1,a5,119 +800081e8: 00369693 slli a3,a3,0x3 +800081ec: d41ff06f j 80007f2c <_malloc_r+0x448> +800081f0: 55400713 li a4,1364 +800081f4: 06f76263 bltu a4,a5,80008258 <_malloc_r+0x774> +800081f8: 0124d793 srli a5,s1,0x12 +800081fc: 07d78613 addi a2,a5,125 +80008200: 07c78513 addi a0,a5,124 +80008204: 00361693 slli a3,a2,0x3 +80008208: 9b9ff06f j 80007bc0 <_malloc_r+0xdc> +8000820c: ff8c8c93 addi s9,s9,-8 +80008210: 019a8ab3 add s5,s5,s9 +80008214: 417a8ab3 sub s5,s5,s7 +80008218: 00000a13 li s4,0 +8000821c: c49ff06f j 80007e64 <_malloc_r+0x380> +80008220: 00840593 addi a1,s0,8 +80008224: 00098513 mv a0,s3 +80008228: ee8fc0ef jal ra,80004910 <_free_r> +8000822c: 00892403 lw s0,8(s2) +80008230: 000c2583 lw a1,0(s8) +80008234: 00442a83 lw s5,4(s0) +80008238: c85ff06f j 80007ebc <_malloc_r+0x3d8> +8000823c: 55400713 li a4,1364 +80008240: 02f76463 bltu a4,a5,80008268 <_malloc_r+0x784> +80008244: 01255793 srli a5,a0,0x12 +80008248: 07d78693 addi a3,a5,125 +8000824c: 07c78593 addi a1,a5,124 +80008250: 00369693 slli a3,a3,0x3 +80008254: cd9ff06f j 80007f2c <_malloc_r+0x448> +80008258: 3f800693 li a3,1016 +8000825c: 07f00613 li a2,127 +80008260: 07e00513 li a0,126 +80008264: 95dff06f j 80007bc0 <_malloc_r+0xdc> +80008268: 3f800693 li a3,1016 +8000826c: 07e00593 li a1,126 +80008270: cbdff06f j 80007f2c <_malloc_r+0x448> +80008274: 00492783 lw a5,4(s2) +80008278: e5dff06f j 800080d4 <_malloc_r+0x5f0> -80007ba8 <_malloc_r>: -80007ba8: fd010113 addi sp,sp,-48 -80007bac: 01312e23 sw s3,28(sp) -80007bb0: 02112623 sw ra,44(sp) -80007bb4: 02812423 sw s0,40(sp) -80007bb8: 02912223 sw s1,36(sp) -80007bbc: 03212023 sw s2,32(sp) -80007bc0: 01412c23 sw s4,24(sp) -80007bc4: 01512a23 sw s5,20(sp) -80007bc8: 01612823 sw s6,16(sp) -80007bcc: 01712623 sw s7,12(sp) -80007bd0: 01812423 sw s8,8(sp) -80007bd4: 01912223 sw s9,4(sp) -80007bd8: 00b58793 addi a5,a1,11 -80007bdc: 01600713 li a4,22 -80007be0: 00050993 mv s3,a0 -80007be4: 06f76463 bltu a4,a5,80007c4c <_malloc_r+0xa4> -80007be8: 01000793 li a5,16 -80007bec: 1eb7e263 bltu a5,a1,80007dd0 <_malloc_r+0x228> -80007bf0: 101000ef jal ra,800084f0 <__malloc_lock> -80007bf4: 01000493 li s1,16 -80007bf8: 00200613 li a2,2 -80007bfc: 01800793 li a5,24 -80007c00: dc018913 addi s2,gp,-576 # 800165c8 <__malloc_av_> -80007c04: 00f907b3 add a5,s2,a5 -80007c08: 0047a403 lw s0,4(a5) # f004 <_start-0x7fff0ffc> -80007c0c: ff878713 addi a4,a5,-8 -80007c10: 20e40863 beq s0,a4,80007e20 <_malloc_r+0x278> -80007c14: 00442783 lw a5,4(s0) -80007c18: 00c42683 lw a3,12(s0) -80007c1c: 00842603 lw a2,8(s0) -80007c20: ffc7f793 andi a5,a5,-4 -80007c24: 00f407b3 add a5,s0,a5 -80007c28: 0047a703 lw a4,4(a5) -80007c2c: 00d62623 sw a3,12(a2) -80007c30: 00c6a423 sw a2,8(a3) -80007c34: 00176713 ori a4,a4,1 -80007c38: 00098513 mv a0,s3 -80007c3c: 00e7a223 sw a4,4(a5) -80007c40: 0b5000ef jal ra,800084f4 <__malloc_unlock> -80007c44: 00840513 addi a0,s0,8 -80007c48: 1940006f j 80007ddc <_malloc_r+0x234> -80007c4c: ff87f493 andi s1,a5,-8 -80007c50: 1807c063 bltz a5,80007dd0 <_malloc_r+0x228> -80007c54: 16b4ee63 bltu s1,a1,80007dd0 <_malloc_r+0x228> -80007c58: 099000ef jal ra,800084f0 <__malloc_lock> -80007c5c: 1f700793 li a5,503 -80007c60: 4497fa63 bgeu a5,s1,800080b4 <_malloc_r+0x50c> -80007c64: 0094d793 srli a5,s1,0x9 -80007c68: 1a078463 beqz a5,80007e10 <_malloc_r+0x268> -80007c6c: 00400713 li a4,4 -80007c70: 3cf76063 bltu a4,a5,80008030 <_malloc_r+0x488> -80007c74: 0064d793 srli a5,s1,0x6 -80007c78: 03978613 addi a2,a5,57 -80007c7c: 03878513 addi a0,a5,56 -80007c80: 00361693 slli a3,a2,0x3 -80007c84: dc018913 addi s2,gp,-576 # 800165c8 <__malloc_av_> -80007c88: 00d906b3 add a3,s2,a3 -80007c8c: 0046a403 lw s0,4(a3) -80007c90: ff868693 addi a3,a3,-8 -80007c94: 02868663 beq a3,s0,80007cc0 <_malloc_r+0x118> -80007c98: 00f00593 li a1,15 -80007c9c: 0100006f j 80007cac <_malloc_r+0x104> -80007ca0: 32075263 bgez a4,80007fc4 <_malloc_r+0x41c> -80007ca4: 00c42403 lw s0,12(s0) -80007ca8: 00868c63 beq a3,s0,80007cc0 <_malloc_r+0x118> -80007cac: 00442783 lw a5,4(s0) -80007cb0: ffc7f793 andi a5,a5,-4 -80007cb4: 40978733 sub a4,a5,s1 -80007cb8: fee5d4e3 bge a1,a4,80007ca0 <_malloc_r+0xf8> -80007cbc: 00050613 mv a2,a0 -80007cc0: 01092403 lw s0,16(s2) -80007cc4: 00890893 addi a7,s2,8 -80007cc8: 17140863 beq s0,a7,80007e38 <_malloc_r+0x290> -80007ccc: 00442503 lw a0,4(s0) -80007cd0: 00f00693 li a3,15 -80007cd4: ffc57513 andi a0,a0,-4 -80007cd8: 409507b3 sub a5,a0,s1 -80007cdc: 40f6c263 blt a3,a5,800080e0 <_malloc_r+0x538> -80007ce0: 01192a23 sw a7,20(s2) -80007ce4: 01192823 sw a7,16(s2) -80007ce8: 3c07dc63 bgez a5,800080c0 <_malloc_r+0x518> -80007cec: 1ff00793 li a5,511 -80007cf0: 2ea7e063 bltu a5,a0,80007fd0 <_malloc_r+0x428> -80007cf4: ff857793 andi a5,a0,-8 -80007cf8: 00878793 addi a5,a5,8 -80007cfc: 00492583 lw a1,4(s2) -80007d00: 00f907b3 add a5,s2,a5 -80007d04: 0007a683 lw a3,0(a5) -80007d08: 00555513 srli a0,a0,0x5 -80007d0c: 00100713 li a4,1 -80007d10: 00a71733 sll a4,a4,a0 -80007d14: 00b76733 or a4,a4,a1 -80007d18: ff878593 addi a1,a5,-8 -80007d1c: 00b42623 sw a1,12(s0) -80007d20: 00d42423 sw a3,8(s0) -80007d24: 00e92223 sw a4,4(s2) -80007d28: 0087a023 sw s0,0(a5) -80007d2c: 0086a623 sw s0,12(a3) -80007d30: 40265793 srai a5,a2,0x2 -80007d34: 00100593 li a1,1 -80007d38: 00f595b3 sll a1,a1,a5 -80007d3c: 10b76863 bltu a4,a1,80007e4c <_malloc_r+0x2a4> -80007d40: 00e5f7b3 and a5,a1,a4 -80007d44: 02079463 bnez a5,80007d6c <_malloc_r+0x1c4> -80007d48: 00159593 slli a1,a1,0x1 -80007d4c: ffc67613 andi a2,a2,-4 -80007d50: 00e5f7b3 and a5,a1,a4 -80007d54: 00460613 addi a2,a2,4 -80007d58: 00079a63 bnez a5,80007d6c <_malloc_r+0x1c4> -80007d5c: 00159593 slli a1,a1,0x1 -80007d60: 00e5f7b3 and a5,a1,a4 -80007d64: 00460613 addi a2,a2,4 -80007d68: fe078ae3 beqz a5,80007d5c <_malloc_r+0x1b4> -80007d6c: 00f00813 li a6,15 -80007d70: 00361313 slli t1,a2,0x3 -80007d74: 00690333 add t1,s2,t1 -80007d78: 00030513 mv a0,t1 -80007d7c: 00c52783 lw a5,12(a0) -80007d80: 00060e13 mv t3,a2 -80007d84: 2cf50863 beq a0,a5,80008054 <_malloc_r+0x4ac> -80007d88: 0047a703 lw a4,4(a5) -80007d8c: 00078413 mv s0,a5 -80007d90: 00c7a783 lw a5,12(a5) -80007d94: ffc77713 andi a4,a4,-4 -80007d98: 409706b3 sub a3,a4,s1 -80007d9c: 2cd84863 blt a6,a3,8000806c <_malloc_r+0x4c4> -80007da0: fe06c2e3 bltz a3,80007d84 <_malloc_r+0x1dc> -80007da4: 00e40733 add a4,s0,a4 -80007da8: 00472683 lw a3,4(a4) -80007dac: 00842603 lw a2,8(s0) -80007db0: 00098513 mv a0,s3 -80007db4: 0016e693 ori a3,a3,1 -80007db8: 00d72223 sw a3,4(a4) -80007dbc: 00f62623 sw a5,12(a2) -80007dc0: 00c7a423 sw a2,8(a5) -80007dc4: 730000ef jal ra,800084f4 <__malloc_unlock> -80007dc8: 00840513 addi a0,s0,8 -80007dcc: 0100006f j 80007ddc <_malloc_r+0x234> -80007dd0: 00c00793 li a5,12 -80007dd4: 00f9a023 sw a5,0(s3) -80007dd8: 00000513 li a0,0 -80007ddc: 02c12083 lw ra,44(sp) -80007de0: 02812403 lw s0,40(sp) -80007de4: 02412483 lw s1,36(sp) -80007de8: 02012903 lw s2,32(sp) -80007dec: 01c12983 lw s3,28(sp) -80007df0: 01812a03 lw s4,24(sp) -80007df4: 01412a83 lw s5,20(sp) -80007df8: 01012b03 lw s6,16(sp) -80007dfc: 00c12b83 lw s7,12(sp) -80007e00: 00812c03 lw s8,8(sp) -80007e04: 00412c83 lw s9,4(sp) -80007e08: 03010113 addi sp,sp,48 -80007e0c: 00008067 ret -80007e10: 20000693 li a3,512 -80007e14: 04000613 li a2,64 -80007e18: 03f00513 li a0,63 -80007e1c: e69ff06f j 80007c84 <_malloc_r+0xdc> -80007e20: 00c7a403 lw s0,12(a5) -80007e24: 00260613 addi a2,a2,2 -80007e28: de8796e3 bne a5,s0,80007c14 <_malloc_r+0x6c> -80007e2c: 01092403 lw s0,16(s2) -80007e30: 00890893 addi a7,s2,8 -80007e34: e9141ce3 bne s0,a7,80007ccc <_malloc_r+0x124> -80007e38: 00492703 lw a4,4(s2) -80007e3c: 40265793 srai a5,a2,0x2 -80007e40: 00100593 li a1,1 -80007e44: 00f595b3 sll a1,a1,a5 -80007e48: eeb77ce3 bgeu a4,a1,80007d40 <_malloc_r+0x198> -80007e4c: 00892403 lw s0,8(s2) -80007e50: 00442a83 lw s5,4(s0) -80007e54: ffcafb13 andi s6,s5,-4 -80007e58: 009b6863 bltu s6,s1,80007e68 <_malloc_r+0x2c0> -80007e5c: 409b07b3 sub a5,s6,s1 -80007e60: 00f00713 li a4,15 -80007e64: 12f74c63 blt a4,a5,80007f9c <_malloc_r+0x3f4> -80007e68: 3741aa83 lw s5,884(gp) # 80016b7c <__malloc_top_pad> -80007e6c: 3641a703 lw a4,868(gp) # 80016b6c <__malloc_sbrk_base> -80007e70: fff00793 li a5,-1 -80007e74: 01640a33 add s4,s0,s6 -80007e78: 01548ab3 add s5,s1,s5 -80007e7c: 34f70463 beq a4,a5,800081c4 <_malloc_r+0x61c> -80007e80: 000017b7 lui a5,0x1 -80007e84: 00f78793 addi a5,a5,15 # 100f <_start-0x7fffeff1> -80007e88: 00fa8ab3 add s5,s5,a5 -80007e8c: fffff7b7 lui a5,0xfffff -80007e90: 00fafab3 and s5,s5,a5 -80007e94: 000a8593 mv a1,s5 -80007e98: 00098513 mv a0,s3 -80007e9c: 778010ef jal ra,80009614 <_sbrk_r> -80007ea0: fff00793 li a5,-1 -80007ea4: 00050b93 mv s7,a0 -80007ea8: 28f50663 beq a0,a5,80008134 <_malloc_r+0x58c> -80007eac: 29456263 bltu a0,s4,80008130 <_malloc_r+0x588> -80007eb0: 3c018c13 addi s8,gp,960 # 80016bc8 <__malloc_current_mallinfo> -80007eb4: 000c2583 lw a1,0(s8) # 1000 <_start-0x7ffff000> -80007eb8: 00ba85b3 add a1,s5,a1 -80007ebc: 00bc2023 sw a1,0(s8) -80007ec0: 00058793 mv a5,a1 -80007ec4: 38aa0e63 beq s4,a0,80008260 <_malloc_r+0x6b8> -80007ec8: 3641a683 lw a3,868(gp) # 80016b6c <__malloc_sbrk_base> -80007ecc: fff00713 li a4,-1 -80007ed0: 3ae68663 beq a3,a4,8000827c <_malloc_r+0x6d4> -80007ed4: 414b8a33 sub s4,s7,s4 -80007ed8: 00fa07b3 add a5,s4,a5 -80007edc: 00fc2023 sw a5,0(s8) -80007ee0: 007bfc93 andi s9,s7,7 -80007ee4: 300c8263 beqz s9,800081e8 <_malloc_r+0x640> -80007ee8: 000017b7 lui a5,0x1 -80007eec: 419b8bb3 sub s7,s7,s9 -80007ef0: 00878593 addi a1,a5,8 # 1008 <_start-0x7fffeff8> -80007ef4: 008b8b93 addi s7,s7,8 -80007ef8: 419585b3 sub a1,a1,s9 -80007efc: 015b8ab3 add s5,s7,s5 -80007f00: fff78793 addi a5,a5,-1 -80007f04: 415585b3 sub a1,a1,s5 -80007f08: 00f5fa33 and s4,a1,a5 -80007f0c: 000a0593 mv a1,s4 -80007f10: 00098513 mv a0,s3 -80007f14: 700010ef jal ra,80009614 <_sbrk_r> -80007f18: fff00793 li a5,-1 -80007f1c: 3af50a63 beq a0,a5,800082d0 <_malloc_r+0x728> -80007f20: 41750533 sub a0,a0,s7 -80007f24: 01450ab3 add s5,a0,s4 -80007f28: 000c2583 lw a1,0(s8) -80007f2c: 01792423 sw s7,8(s2) -80007f30: 001aea93 ori s5,s5,1 -80007f34: 00ba05b3 add a1,s4,a1 -80007f38: 00bc2023 sw a1,0(s8) -80007f3c: 015ba223 sw s5,4(s7) -80007f40: 35240263 beq s0,s2,80008284 <_malloc_r+0x6dc> -80007f44: 00f00693 li a3,15 -80007f48: 3566f263 bgeu a3,s6,8000828c <_malloc_r+0x6e4> -80007f4c: 00442703 lw a4,4(s0) -80007f50: ff4b0793 addi a5,s6,-12 -80007f54: ff87f793 andi a5,a5,-8 -80007f58: 00177713 andi a4,a4,1 -80007f5c: 00f76733 or a4,a4,a5 -80007f60: 00e42223 sw a4,4(s0) -80007f64: 00500613 li a2,5 -80007f68: 00f40733 add a4,s0,a5 -80007f6c: 00c72223 sw a2,4(a4) -80007f70: 00c72423 sw a2,8(a4) -80007f74: 36f6e863 bltu a3,a5,800082e4 <_malloc_r+0x73c> -80007f78: 004baa83 lw s5,4(s7) -80007f7c: 000b8413 mv s0,s7 -80007f80: 3701a703 lw a4,880(gp) # 80016b78 <__malloc_max_sbrked_mem> -80007f84: 00b77463 bgeu a4,a1,80007f8c <_malloc_r+0x3e4> -80007f88: 36b1a823 sw a1,880(gp) # 80016b78 <__malloc_max_sbrked_mem> -80007f8c: 36c1a703 lw a4,876(gp) # 80016b74 <_edata> -80007f90: 1ab77663 bgeu a4,a1,8000813c <_malloc_r+0x594> -80007f94: 36b1a623 sw a1,876(gp) # 80016b74 <_edata> -80007f98: 1a40006f j 8000813c <_malloc_r+0x594> -80007f9c: 0014e713 ori a4,s1,1 -80007fa0: 00e42223 sw a4,4(s0) -80007fa4: 009404b3 add s1,s0,s1 -80007fa8: 00992423 sw s1,8(s2) -80007fac: 0017e793 ori a5,a5,1 -80007fb0: 00098513 mv a0,s3 -80007fb4: 00f4a223 sw a5,4(s1) -80007fb8: 53c000ef jal ra,800084f4 <__malloc_unlock> -80007fbc: 00840513 addi a0,s0,8 -80007fc0: e1dff06f j 80007ddc <_malloc_r+0x234> -80007fc4: 00c42683 lw a3,12(s0) -80007fc8: 00842603 lw a2,8(s0) -80007fcc: c59ff06f j 80007c24 <_malloc_r+0x7c> -80007fd0: 00955793 srli a5,a0,0x9 -80007fd4: 00400713 li a4,4 -80007fd8: 14f77263 bgeu a4,a5,8000811c <_malloc_r+0x574> -80007fdc: 01400713 li a4,20 -80007fe0: 22f76a63 bltu a4,a5,80008214 <_malloc_r+0x66c> -80007fe4: 05c78693 addi a3,a5,92 -80007fe8: 05b78593 addi a1,a5,91 -80007fec: 00369693 slli a3,a3,0x3 -80007ff0: 00d906b3 add a3,s2,a3 -80007ff4: 0006a783 lw a5,0(a3) -80007ff8: ff868693 addi a3,a3,-8 -80007ffc: 1cf68863 beq a3,a5,800081cc <_malloc_r+0x624> -80008000: 0047a703 lw a4,4(a5) -80008004: ffc77713 andi a4,a4,-4 -80008008: 00e57663 bgeu a0,a4,80008014 <_malloc_r+0x46c> -8000800c: 0087a783 lw a5,8(a5) -80008010: fef698e3 bne a3,a5,80008000 <_malloc_r+0x458> -80008014: 00c7a683 lw a3,12(a5) -80008018: 00492703 lw a4,4(s2) -8000801c: 00d42623 sw a3,12(s0) -80008020: 00f42423 sw a5,8(s0) -80008024: 0086a423 sw s0,8(a3) -80008028: 0087a623 sw s0,12(a5) -8000802c: d05ff06f j 80007d30 <_malloc_r+0x188> -80008030: 01400713 li a4,20 -80008034: 12f77663 bgeu a4,a5,80008160 <_malloc_r+0x5b8> -80008038: 05400713 li a4,84 -8000803c: 1ef76a63 bltu a4,a5,80008230 <_malloc_r+0x688> -80008040: 00c4d793 srli a5,s1,0xc -80008044: 06f78613 addi a2,a5,111 -80008048: 06e78513 addi a0,a5,110 -8000804c: 00361693 slli a3,a2,0x3 -80008050: c35ff06f j 80007c84 <_malloc_r+0xdc> -80008054: 001e0e13 addi t3,t3,1 -80008058: 003e7793 andi a5,t3,3 -8000805c: 00850513 addi a0,a0,8 -80008060: 10078e63 beqz a5,8000817c <_malloc_r+0x5d4> -80008064: 00c52783 lw a5,12(a0) -80008068: d1dff06f j 80007d84 <_malloc_r+0x1dc> -8000806c: 00842603 lw a2,8(s0) -80008070: 0014e593 ori a1,s1,1 -80008074: 00b42223 sw a1,4(s0) -80008078: 00f62623 sw a5,12(a2) -8000807c: 00c7a423 sw a2,8(a5) -80008080: 009404b3 add s1,s0,s1 -80008084: 00992a23 sw s1,20(s2) -80008088: 00992823 sw s1,16(s2) -8000808c: 0016e793 ori a5,a3,1 -80008090: 0114a623 sw a7,12(s1) -80008094: 0114a423 sw a7,8(s1) -80008098: 00f4a223 sw a5,4(s1) -8000809c: 00e40733 add a4,s0,a4 -800080a0: 00098513 mv a0,s3 -800080a4: 00d72023 sw a3,0(a4) -800080a8: 44c000ef jal ra,800084f4 <__malloc_unlock> -800080ac: 00840513 addi a0,s0,8 -800080b0: d2dff06f j 80007ddc <_malloc_r+0x234> -800080b4: 0034d613 srli a2,s1,0x3 -800080b8: 00848793 addi a5,s1,8 -800080bc: b45ff06f j 80007c00 <_malloc_r+0x58> -800080c0: 00a40733 add a4,s0,a0 -800080c4: 00472783 lw a5,4(a4) -800080c8: 00098513 mv a0,s3 -800080cc: 0017e793 ori a5,a5,1 -800080d0: 00f72223 sw a5,4(a4) -800080d4: 420000ef jal ra,800084f4 <__malloc_unlock> -800080d8: 00840513 addi a0,s0,8 -800080dc: d01ff06f j 80007ddc <_malloc_r+0x234> -800080e0: 0014e713 ori a4,s1,1 -800080e4: 00e42223 sw a4,4(s0) -800080e8: 009404b3 add s1,s0,s1 -800080ec: 00992a23 sw s1,20(s2) -800080f0: 00992823 sw s1,16(s2) -800080f4: 0017e713 ori a4,a5,1 -800080f8: 0114a623 sw a7,12(s1) -800080fc: 0114a423 sw a7,8(s1) -80008100: 00e4a223 sw a4,4(s1) -80008104: 00a40533 add a0,s0,a0 -80008108: 00f52023 sw a5,0(a0) -8000810c: 00098513 mv a0,s3 -80008110: 3e4000ef jal ra,800084f4 <__malloc_unlock> -80008114: 00840513 addi a0,s0,8 -80008118: cc5ff06f j 80007ddc <_malloc_r+0x234> -8000811c: 00655793 srli a5,a0,0x6 -80008120: 03978693 addi a3,a5,57 -80008124: 03878593 addi a1,a5,56 -80008128: 00369693 slli a3,a3,0x3 -8000812c: ec5ff06f j 80007ff0 <_malloc_r+0x448> -80008130: 11240e63 beq s0,s2,8000824c <_malloc_r+0x6a4> -80008134: 00892403 lw s0,8(s2) -80008138: 00442a83 lw s5,4(s0) -8000813c: ffcafa93 andi s5,s5,-4 -80008140: 409a87b3 sub a5,s5,s1 -80008144: 009ae663 bltu s5,s1,80008150 <_malloc_r+0x5a8> -80008148: 00f00713 li a4,15 -8000814c: e4f748e3 blt a4,a5,80007f9c <_malloc_r+0x3f4> -80008150: 00098513 mv a0,s3 -80008154: 3a0000ef jal ra,800084f4 <__malloc_unlock> -80008158: 00000513 li a0,0 -8000815c: c81ff06f j 80007ddc <_malloc_r+0x234> -80008160: 05c78613 addi a2,a5,92 -80008164: 05b78513 addi a0,a5,91 -80008168: 00361693 slli a3,a2,0x3 -8000816c: b19ff06f j 80007c84 <_malloc_r+0xdc> -80008170: 00832783 lw a5,8(t1) -80008174: fff60613 addi a2,a2,-1 -80008178: 1c679063 bne a5,t1,80008338 <_malloc_r+0x790> -8000817c: 00367793 andi a5,a2,3 -80008180: ff830313 addi t1,t1,-8 -80008184: fe0796e3 bnez a5,80008170 <_malloc_r+0x5c8> -80008188: 00492703 lw a4,4(s2) -8000818c: fff5c793 not a5,a1 -80008190: 00e7f7b3 and a5,a5,a4 -80008194: 00f92223 sw a5,4(s2) -80008198: 00159593 slli a1,a1,0x1 -8000819c: cab7e8e3 bltu a5,a1,80007e4c <_malloc_r+0x2a4> -800081a0: ca0586e3 beqz a1,80007e4c <_malloc_r+0x2a4> -800081a4: 00f5f733 and a4,a1,a5 -800081a8: 00071a63 bnez a4,800081bc <_malloc_r+0x614> -800081ac: 00159593 slli a1,a1,0x1 -800081b0: 00f5f733 and a4,a1,a5 -800081b4: 004e0e13 addi t3,t3,4 -800081b8: fe070ae3 beqz a4,800081ac <_malloc_r+0x604> -800081bc: 000e0613 mv a2,t3 -800081c0: bb1ff06f j 80007d70 <_malloc_r+0x1c8> -800081c4: 010a8a93 addi s5,s5,16 # fffff010 <__BSS_END__+0x7ffe83d4> -800081c8: ccdff06f j 80007e94 <_malloc_r+0x2ec> -800081cc: 00492503 lw a0,4(s2) -800081d0: 4025d593 srai a1,a1,0x2 -800081d4: 00100713 li a4,1 -800081d8: 00b71733 sll a4,a4,a1 -800081dc: 00a76733 or a4,a4,a0 -800081e0: 00e92223 sw a4,4(s2) -800081e4: e39ff06f j 8000801c <_malloc_r+0x474> -800081e8: 015b85b3 add a1,s7,s5 -800081ec: 40b005b3 neg a1,a1 -800081f0: 01459593 slli a1,a1,0x14 -800081f4: 0145da13 srli s4,a1,0x14 -800081f8: 000a0593 mv a1,s4 -800081fc: 00098513 mv a0,s3 -80008200: 414010ef jal ra,80009614 <_sbrk_r> -80008204: fff00793 li a5,-1 -80008208: d0f51ce3 bne a0,a5,80007f20 <_malloc_r+0x378> -8000820c: 00000a13 li s4,0 -80008210: d19ff06f j 80007f28 <_malloc_r+0x380> -80008214: 05400713 li a4,84 -80008218: 08f76063 bltu a4,a5,80008298 <_malloc_r+0x6f0> -8000821c: 00c55793 srli a5,a0,0xc -80008220: 06f78693 addi a3,a5,111 -80008224: 06e78593 addi a1,a5,110 -80008228: 00369693 slli a3,a3,0x3 -8000822c: dc5ff06f j 80007ff0 <_malloc_r+0x448> -80008230: 15400713 li a4,340 -80008234: 08f76063 bltu a4,a5,800082b4 <_malloc_r+0x70c> -80008238: 00f4d793 srli a5,s1,0xf -8000823c: 07878613 addi a2,a5,120 -80008240: 07778513 addi a0,a5,119 -80008244: 00361693 slli a3,a2,0x3 -80008248: a3dff06f j 80007c84 <_malloc_r+0xdc> -8000824c: 3c018c13 addi s8,gp,960 # 80016bc8 <__malloc_current_mallinfo> -80008250: 000c2783 lw a5,0(s8) -80008254: 00fa87b3 add a5,s5,a5 -80008258: 00fc2023 sw a5,0(s8) -8000825c: c6dff06f j 80007ec8 <_malloc_r+0x320> -80008260: 014a1713 slli a4,s4,0x14 -80008264: c60712e3 bnez a4,80007ec8 <_malloc_r+0x320> -80008268: 00892403 lw s0,8(s2) -8000826c: 015b0ab3 add s5,s6,s5 -80008270: 001aea93 ori s5,s5,1 -80008274: 01542223 sw s5,4(s0) -80008278: d09ff06f j 80007f80 <_malloc_r+0x3d8> -8000827c: 3771a223 sw s7,868(gp) # 80016b6c <__malloc_sbrk_base> -80008280: c61ff06f j 80007ee0 <_malloc_r+0x338> -80008284: 000b8413 mv s0,s7 -80008288: cf9ff06f j 80007f80 <_malloc_r+0x3d8> -8000828c: 00100793 li a5,1 -80008290: 00fba223 sw a5,4(s7) -80008294: ebdff06f j 80008150 <_malloc_r+0x5a8> -80008298: 15400713 li a4,340 -8000829c: 06f76263 bltu a4,a5,80008300 <_malloc_r+0x758> -800082a0: 00f55793 srli a5,a0,0xf -800082a4: 07878693 addi a3,a5,120 -800082a8: 07778593 addi a1,a5,119 -800082ac: 00369693 slli a3,a3,0x3 -800082b0: d41ff06f j 80007ff0 <_malloc_r+0x448> -800082b4: 55400713 li a4,1364 -800082b8: 06f76263 bltu a4,a5,8000831c <_malloc_r+0x774> -800082bc: 0124d793 srli a5,s1,0x12 -800082c0: 07d78613 addi a2,a5,125 -800082c4: 07c78513 addi a0,a5,124 -800082c8: 00361693 slli a3,a2,0x3 -800082cc: 9b9ff06f j 80007c84 <_malloc_r+0xdc> -800082d0: ff8c8c93 addi s9,s9,-8 -800082d4: 019a8ab3 add s5,s5,s9 -800082d8: 417a8ab3 sub s5,s5,s7 -800082dc: 00000a13 li s4,0 -800082e0: c49ff06f j 80007f28 <_malloc_r+0x380> -800082e4: 00840593 addi a1,s0,8 -800082e8: 00098513 mv a0,s3 -800082ec: ee8fc0ef jal ra,800049d4 <_free_r> -800082f0: 00892403 lw s0,8(s2) -800082f4: 000c2583 lw a1,0(s8) -800082f8: 00442a83 lw s5,4(s0) -800082fc: c85ff06f j 80007f80 <_malloc_r+0x3d8> -80008300: 55400713 li a4,1364 -80008304: 02f76463 bltu a4,a5,8000832c <_malloc_r+0x784> -80008308: 01255793 srli a5,a0,0x12 -8000830c: 07d78693 addi a3,a5,125 -80008310: 07c78593 addi a1,a5,124 -80008314: 00369693 slli a3,a3,0x3 -80008318: cd9ff06f j 80007ff0 <_malloc_r+0x448> -8000831c: 3f800693 li a3,1016 -80008320: 07f00613 li a2,127 -80008324: 07e00513 li a0,126 -80008328: 95dff06f j 80007c84 <_malloc_r+0xdc> -8000832c: 3f800693 li a3,1016 -80008330: 07e00593 li a1,126 -80008334: cbdff06f j 80007ff0 <_malloc_r+0x448> -80008338: 00492783 lw a5,4(s2) -8000833c: e5dff06f j 80008198 <_malloc_r+0x5f0> +8000827c : +8000827c: 00357793 andi a5,a0,3 +80008280: 0ff5f693 andi a3,a1,255 +80008284: 02078a63 beqz a5,800082b8 +80008288: fff60793 addi a5,a2,-1 +8000828c: 02060e63 beqz a2,800082c8 +80008290: fff00613 li a2,-1 +80008294: 0180006f j 800082ac +80008298: 00150513 addi a0,a0,1 +8000829c: 00357713 andi a4,a0,3 +800082a0: 00070e63 beqz a4,800082bc +800082a4: fff78793 addi a5,a5,-1 +800082a8: 02c78063 beq a5,a2,800082c8 +800082ac: 00054703 lbu a4,0(a0) +800082b0: fed714e3 bne a4,a3,80008298 +800082b4: 00008067 ret +800082b8: 00060793 mv a5,a2 +800082bc: 00300713 li a4,3 +800082c0: 02f76663 bltu a4,a5,800082ec +800082c4: 00079663 bnez a5,800082d0 +800082c8: 00000513 li a0,0 +800082cc: 00008067 ret +800082d0: 00f507b3 add a5,a0,a5 +800082d4: 00c0006f j 800082e0 +800082d8: 00150513 addi a0,a0,1 +800082dc: fea786e3 beq a5,a0,800082c8 +800082e0: 00054703 lbu a4,0(a0) +800082e4: fed71ae3 bne a4,a3,800082d8 +800082e8: 00008067 ret +800082ec: 00010737 lui a4,0x10 +800082f0: 00859893 slli a7,a1,0x8 +800082f4: fff70713 addi a4,a4,-1 # ffff <_start-0x7fff0001> +800082f8: 00e8f8b3 and a7,a7,a4 +800082fc: 0ff5f593 andi a1,a1,255 +80008300: 00b8e5b3 or a1,a7,a1 +80008304: 01059893 slli a7,a1,0x10 +80008308: 00b8e8b3 or a7,a7,a1 +8000830c: feff0837 lui a6,0xfeff0 +80008310: 808085b7 lui a1,0x80808 +80008314: eff80813 addi a6,a6,-257 # fefefeff <__BSS_END__+0x7efd92c3> +80008318: 08058593 addi a1,a1,128 # 80808080 <__BSS_END__+0x7f1444> +8000831c: 00300313 li t1,3 +80008320: 00052703 lw a4,0(a0) +80008324: 00e8c733 xor a4,a7,a4 +80008328: 01070633 add a2,a4,a6 +8000832c: fff74713 not a4,a4 +80008330: 00e67733 and a4,a2,a4 +80008334: 00b77733 and a4,a4,a1 +80008338: f8071ce3 bnez a4,800082d0 +8000833c: ffc78793 addi a5,a5,-4 +80008340: 00450513 addi a0,a0,4 +80008344: fcf36ee3 bltu t1,a5,80008320 +80008348: f80794e3 bnez a5,800082d0 +8000834c: f7dff06f j 800082c8 -80008340 : -80008340: 00357793 andi a5,a0,3 -80008344: 0ff5f693 andi a3,a1,255 -80008348: 02078a63 beqz a5,8000837c -8000834c: fff60793 addi a5,a2,-1 -80008350: 02060e63 beqz a2,8000838c -80008354: fff00613 li a2,-1 -80008358: 0180006f j 80008370 -8000835c: 00150513 addi a0,a0,1 -80008360: 00357713 andi a4,a0,3 -80008364: 00070e63 beqz a4,80008380 -80008368: fff78793 addi a5,a5,-1 -8000836c: 02c78063 beq a5,a2,8000838c -80008370: 00054703 lbu a4,0(a0) -80008374: fed714e3 bne a4,a3,8000835c -80008378: 00008067 ret -8000837c: 00060793 mv a5,a2 -80008380: 00300713 li a4,3 -80008384: 02f76663 bltu a4,a5,800083b0 -80008388: 00079663 bnez a5,80008394 -8000838c: 00000513 li a0,0 +80008350 : +80008350: 00f00313 li t1,15 +80008354: 00050713 mv a4,a0 +80008358: 02c37e63 bgeu t1,a2,80008394 +8000835c: 00f77793 andi a5,a4,15 +80008360: 0a079063 bnez a5,80008400 +80008364: 08059263 bnez a1,800083e8 +80008368: ff067693 andi a3,a2,-16 +8000836c: 00f67613 andi a2,a2,15 +80008370: 00e686b3 add a3,a3,a4 +80008374: 00b72023 sw a1,0(a4) +80008378: 00b72223 sw a1,4(a4) +8000837c: 00b72423 sw a1,8(a4) +80008380: 00b72623 sw a1,12(a4) +80008384: 01070713 addi a4,a4,16 +80008388: fed766e3 bltu a4,a3,80008374 +8000838c: 00061463 bnez a2,80008394 80008390: 00008067 ret -80008394: 00f507b3 add a5,a0,a5 -80008398: 00c0006f j 800083a4 -8000839c: 00150513 addi a0,a0,1 -800083a0: fea786e3 beq a5,a0,8000838c -800083a4: 00054703 lbu a4,0(a0) -800083a8: fed71ae3 bne a4,a3,8000839c -800083ac: 00008067 ret -800083b0: 00010737 lui a4,0x10 -800083b4: 00859893 slli a7,a1,0x8 -800083b8: fff70713 addi a4,a4,-1 # ffff <_start-0x7fff0001> -800083bc: 00e8f8b3 and a7,a7,a4 -800083c0: 0ff5f593 andi a1,a1,255 -800083c4: 00b8e5b3 or a1,a7,a1 -800083c8: 01059893 slli a7,a1,0x10 -800083cc: 00b8e8b3 or a7,a7,a1 -800083d0: feff0837 lui a6,0xfeff0 -800083d4: 808085b7 lui a1,0x80808 -800083d8: eff80813 addi a6,a6,-257 # fefefeff <__BSS_END__+0x7efd92c3> -800083dc: 08058593 addi a1,a1,128 # 80808080 <__BSS_END__+0x7f1444> -800083e0: 00300313 li t1,3 -800083e4: 00052703 lw a4,0(a0) -800083e8: 00e8c733 xor a4,a7,a4 -800083ec: 01070633 add a2,a4,a6 -800083f0: fff74713 not a4,a4 -800083f4: 00e67733 and a4,a2,a4 -800083f8: 00b77733 and a4,a4,a1 -800083fc: f8071ce3 bnez a4,80008394 -80008400: ffc78793 addi a5,a5,-4 -80008404: 00450513 addi a0,a0,4 -80008408: fcf36ee3 bltu t1,a5,800083e4 -8000840c: f80794e3 bnez a5,80008394 -80008410: f7dff06f j 8000838c +80008394: 40c306b3 sub a3,t1,a2 +80008398: 00269693 slli a3,a3,0x2 +8000839c: 00000297 auipc t0,0x0 +800083a0: 005686b3 add a3,a3,t0 +800083a4: 00c68067 jr 12(a3) +800083a8: 00b70723 sb a1,14(a4) +800083ac: 00b706a3 sb a1,13(a4) +800083b0: 00b70623 sb a1,12(a4) +800083b4: 00b705a3 sb a1,11(a4) +800083b8: 00b70523 sb a1,10(a4) +800083bc: 00b704a3 sb a1,9(a4) +800083c0: 00b70423 sb a1,8(a4) +800083c4: 00b703a3 sb a1,7(a4) +800083c8: 00b70323 sb a1,6(a4) +800083cc: 00b702a3 sb a1,5(a4) +800083d0: 00b70223 sb a1,4(a4) +800083d4: 00b701a3 sb a1,3(a4) +800083d8: 00b70123 sb a1,2(a4) +800083dc: 00b700a3 sb a1,1(a4) +800083e0: 00b70023 sb a1,0(a4) +800083e4: 00008067 ret +800083e8: 0ff5f593 andi a1,a1,255 +800083ec: 00859693 slli a3,a1,0x8 +800083f0: 00d5e5b3 or a1,a1,a3 +800083f4: 01059693 slli a3,a1,0x10 +800083f8: 00d5e5b3 or a1,a1,a3 +800083fc: f6dff06f j 80008368 +80008400: 00279693 slli a3,a5,0x2 +80008404: 00000297 auipc t0,0x0 +80008408: 005686b3 add a3,a3,t0 +8000840c: 00008293 mv t0,ra +80008410: fa0680e7 jalr -96(a3) +80008414: 00028093 mv ra,t0 +80008418: ff078793 addi a5,a5,-16 +8000841c: 40f70733 sub a4,a4,a5 +80008420: 00f60633 add a2,a2,a5 +80008424: f6c378e3 bgeu t1,a2,80008394 +80008428: f3dff06f j 80008364 -80008414 : -80008414: 00f00313 li t1,15 -80008418: 00050713 mv a4,a0 -8000841c: 02c37e63 bgeu t1,a2,80008458 -80008420: 00f77793 andi a5,a4,15 -80008424: 0a079063 bnez a5,800084c4 -80008428: 08059263 bnez a1,800084ac -8000842c: ff067693 andi a3,a2,-16 -80008430: 00f67613 andi a2,a2,15 -80008434: 00e686b3 add a3,a3,a4 -80008438: 00b72023 sw a1,0(a4) -8000843c: 00b72223 sw a1,4(a4) -80008440: 00b72423 sw a1,8(a4) -80008444: 00b72623 sw a1,12(a4) -80008448: 01070713 addi a4,a4,16 -8000844c: fed766e3 bltu a4,a3,80008438 -80008450: 00061463 bnez a2,80008458 -80008454: 00008067 ret -80008458: 40c306b3 sub a3,t1,a2 -8000845c: 00269693 slli a3,a3,0x2 -80008460: 00000297 auipc t0,0x0 -80008464: 005686b3 add a3,a3,t0 -80008468: 00c68067 jr 12(a3) -8000846c: 00b70723 sb a1,14(a4) -80008470: 00b706a3 sb a1,13(a4) -80008474: 00b70623 sb a1,12(a4) -80008478: 00b705a3 sb a1,11(a4) -8000847c: 00b70523 sb a1,10(a4) -80008480: 00b704a3 sb a1,9(a4) -80008484: 00b70423 sb a1,8(a4) -80008488: 00b703a3 sb a1,7(a4) -8000848c: 00b70323 sb a1,6(a4) -80008490: 00b702a3 sb a1,5(a4) -80008494: 00b70223 sb a1,4(a4) -80008498: 00b701a3 sb a1,3(a4) -8000849c: 00b70123 sb a1,2(a4) -800084a0: 00b700a3 sb a1,1(a4) -800084a4: 00b70023 sb a1,0(a4) -800084a8: 00008067 ret -800084ac: 0ff5f593 andi a1,a1,255 -800084b0: 00859693 slli a3,a1,0x8 -800084b4: 00d5e5b3 or a1,a1,a3 -800084b8: 01059693 slli a3,a1,0x10 -800084bc: 00d5e5b3 or a1,a1,a3 -800084c0: f6dff06f j 8000842c -800084c4: 00279693 slli a3,a5,0x2 -800084c8: 00000297 auipc t0,0x0 -800084cc: 005686b3 add a3,a3,t0 -800084d0: 00008293 mv t0,ra -800084d4: fa0680e7 jalr -96(a3) -800084d8: 00028093 mv ra,t0 -800084dc: ff078793 addi a5,a5,-16 -800084e0: 40f70733 sub a4,a4,a5 -800084e4: 00f60633 add a2,a2,a5 -800084e8: f6c378e3 bgeu t1,a2,80008458 -800084ec: f3dff06f j 80008428 +8000842c <__malloc_lock>: +8000842c: 00008067 ret -800084f0 <__malloc_lock>: -800084f0: 00008067 ret +80008430 <__malloc_unlock>: +80008430: 00008067 ret -800084f4 <__malloc_unlock>: -800084f4: 00008067 ret +80008434 <_Balloc>: +80008434: 04c52783 lw a5,76(a0) +80008438: ff010113 addi sp,sp,-16 +8000843c: 00812423 sw s0,8(sp) +80008440: 00912223 sw s1,4(sp) +80008444: 00112623 sw ra,12(sp) +80008448: 01212023 sw s2,0(sp) +8000844c: 00050413 mv s0,a0 +80008450: 00058493 mv s1,a1 +80008454: 02078e63 beqz a5,80008490 <_Balloc+0x5c> +80008458: 00249513 slli a0,s1,0x2 +8000845c: 00a787b3 add a5,a5,a0 +80008460: 0007a503 lw a0,0(a5) +80008464: 04050663 beqz a0,800084b0 <_Balloc+0x7c> +80008468: 00052703 lw a4,0(a0) +8000846c: 00e7a023 sw a4,0(a5) +80008470: 00052823 sw zero,16(a0) +80008474: 00052623 sw zero,12(a0) +80008478: 00c12083 lw ra,12(sp) +8000847c: 00812403 lw s0,8(sp) +80008480: 00412483 lw s1,4(sp) +80008484: 00012903 lw s2,0(sp) +80008488: 01010113 addi sp,sp,16 +8000848c: 00008067 ret +80008490: 02100613 li a2,33 +80008494: 00400593 li a1,4 +80008498: 470050ef jal ra,8000d908 <_calloc_r> +8000849c: 04a42623 sw a0,76(s0) +800084a0: 00050793 mv a5,a0 +800084a4: fa051ae3 bnez a0,80008458 <_Balloc+0x24> +800084a8: 00000513 li a0,0 +800084ac: fcdff06f j 80008478 <_Balloc+0x44> +800084b0: 00100913 li s2,1 +800084b4: 00991933 sll s2,s2,s1 +800084b8: 00590613 addi a2,s2,5 +800084bc: 00261613 slli a2,a2,0x2 +800084c0: 00100593 li a1,1 +800084c4: 00040513 mv a0,s0 +800084c8: 440050ef jal ra,8000d908 <_calloc_r> +800084cc: fc050ee3 beqz a0,800084a8 <_Balloc+0x74> +800084d0: 00952223 sw s1,4(a0) +800084d4: 01252423 sw s2,8(a0) +800084d8: f99ff06f j 80008470 <_Balloc+0x3c> -800084f8 <_Balloc>: -800084f8: 04c52783 lw a5,76(a0) -800084fc: ff010113 addi sp,sp,-16 -80008500: 00812423 sw s0,8(sp) -80008504: 00912223 sw s1,4(sp) -80008508: 00112623 sw ra,12(sp) -8000850c: 01212023 sw s2,0(sp) -80008510: 00050413 mv s0,a0 -80008514: 00058493 mv s1,a1 -80008518: 02078e63 beqz a5,80008554 <_Balloc+0x5c> -8000851c: 00249513 slli a0,s1,0x2 -80008520: 00a787b3 add a5,a5,a0 -80008524: 0007a503 lw a0,0(a5) -80008528: 04050663 beqz a0,80008574 <_Balloc+0x7c> -8000852c: 00052703 lw a4,0(a0) -80008530: 00e7a023 sw a4,0(a5) -80008534: 00052823 sw zero,16(a0) -80008538: 00052623 sw zero,12(a0) -8000853c: 00c12083 lw ra,12(sp) -80008540: 00812403 lw s0,8(sp) -80008544: 00412483 lw s1,4(sp) -80008548: 00012903 lw s2,0(sp) -8000854c: 01010113 addi sp,sp,16 -80008550: 00008067 ret -80008554: 02100613 li a2,33 -80008558: 00400593 li a1,4 -8000855c: 470050ef jal ra,8000d9cc <_calloc_r> -80008560: 04a42623 sw a0,76(s0) -80008564: 00050793 mv a5,a0 -80008568: fa051ae3 bnez a0,8000851c <_Balloc+0x24> -8000856c: 00000513 li a0,0 -80008570: fcdff06f j 8000853c <_Balloc+0x44> -80008574: 00100913 li s2,1 -80008578: 00991933 sll s2,s2,s1 -8000857c: 00590613 addi a2,s2,5 -80008580: 00261613 slli a2,a2,0x2 -80008584: 00100593 li a1,1 -80008588: 00040513 mv a0,s0 -8000858c: 440050ef jal ra,8000d9cc <_calloc_r> -80008590: fc050ee3 beqz a0,8000856c <_Balloc+0x74> -80008594: 00952223 sw s1,4(a0) -80008598: 01252423 sw s2,8(a0) -8000859c: f99ff06f j 80008534 <_Balloc+0x3c> +800084dc <_Bfree>: +800084dc: 02058063 beqz a1,800084fc <_Bfree+0x20> +800084e0: 0045a703 lw a4,4(a1) +800084e4: 04c52783 lw a5,76(a0) +800084e8: 00271713 slli a4,a4,0x2 +800084ec: 00e787b3 add a5,a5,a4 +800084f0: 0007a703 lw a4,0(a5) +800084f4: 00e5a023 sw a4,0(a1) +800084f8: 00b7a023 sw a1,0(a5) +800084fc: 00008067 ret -800085a0 <_Bfree>: -800085a0: 02058063 beqz a1,800085c0 <_Bfree+0x20> -800085a4: 0045a703 lw a4,4(a1) -800085a8: 04c52783 lw a5,76(a0) -800085ac: 00271713 slli a4,a4,0x2 -800085b0: 00e787b3 add a5,a5,a4 -800085b4: 0007a703 lw a4,0(a5) -800085b8: 00e5a023 sw a4,0(a1) -800085bc: 00b7a023 sw a1,0(a5) +80008500 <__multadd>: +80008500: fe010113 addi sp,sp,-32 +80008504: 00912a23 sw s1,20(sp) +80008508: 0105a483 lw s1,16(a1) +8000850c: 00010337 lui t1,0x10 +80008510: 00812c23 sw s0,24(sp) +80008514: 01212823 sw s2,16(sp) +80008518: 01312623 sw s3,12(sp) +8000851c: 00112e23 sw ra,28(sp) +80008520: 01412423 sw s4,8(sp) +80008524: 00058913 mv s2,a1 +80008528: 00050993 mv s3,a0 +8000852c: 00068413 mv s0,a3 +80008530: 01458813 addi a6,a1,20 +80008534: 00000893 li a7,0 +80008538: fff30313 addi t1,t1,-1 # ffff <_start-0x7fff0001> +8000853c: 00082783 lw a5,0(a6) +80008540: 00480813 addi a6,a6,4 +80008544: 00188893 addi a7,a7,1 +80008548: 0067f6b3 and a3,a5,t1 +8000854c: 02c686b3 mul a3,a3,a2 +80008550: 0107d793 srli a5,a5,0x10 +80008554: 02c787b3 mul a5,a5,a2 +80008558: 008686b3 add a3,a3,s0 +8000855c: 0106de13 srli t3,a3,0x10 +80008560: 0066f733 and a4,a3,t1 +80008564: 01c786b3 add a3,a5,t3 +80008568: 01069793 slli a5,a3,0x10 +8000856c: 00e78733 add a4,a5,a4 +80008570: fee82e23 sw a4,-4(a6) +80008574: 0106d413 srli s0,a3,0x10 +80008578: fc98c2e3 blt a7,s1,8000853c <__multadd+0x3c> +8000857c: 02040263 beqz s0,800085a0 <__multadd+0xa0> +80008580: 00892783 lw a5,8(s2) +80008584: 04f4d063 bge s1,a5,800085c4 <__multadd+0xc4> +80008588: 00448793 addi a5,s1,4 +8000858c: 00279793 slli a5,a5,0x2 +80008590: 00f907b3 add a5,s2,a5 +80008594: 0087a223 sw s0,4(a5) +80008598: 00148493 addi s1,s1,1 +8000859c: 00992823 sw s1,16(s2) +800085a0: 01c12083 lw ra,28(sp) +800085a4: 01812403 lw s0,24(sp) +800085a8: 01412483 lw s1,20(sp) +800085ac: 00c12983 lw s3,12(sp) +800085b0: 00812a03 lw s4,8(sp) +800085b4: 00090513 mv a0,s2 +800085b8: 01012903 lw s2,16(sp) +800085bc: 02010113 addi sp,sp,32 800085c0: 00008067 ret +800085c4: 00492583 lw a1,4(s2) +800085c8: 00098513 mv a0,s3 +800085cc: 00158593 addi a1,a1,1 +800085d0: e65ff0ef jal ra,80008434 <_Balloc> +800085d4: 01092603 lw a2,16(s2) +800085d8: 00050a13 mv s4,a0 +800085dc: 00c90593 addi a1,s2,12 +800085e0: 00260613 addi a2,a2,2 +800085e4: 00261613 slli a2,a2,0x2 +800085e8: 00c50513 addi a0,a0,12 +800085ec: 5f1050ef jal ra,8000e3dc +800085f0: 00492703 lw a4,4(s2) +800085f4: 04c9a783 lw a5,76(s3) +800085f8: 00271713 slli a4,a4,0x2 +800085fc: 00e787b3 add a5,a5,a4 +80008600: 0007a703 lw a4,0(a5) +80008604: 00e92023 sw a4,0(s2) +80008608: 0127a023 sw s2,0(a5) +8000860c: 000a0913 mv s2,s4 +80008610: f79ff06f j 80008588 <__multadd+0x88> -800085c4 <__multadd>: -800085c4: fe010113 addi sp,sp,-32 -800085c8: 00912a23 sw s1,20(sp) -800085cc: 0105a483 lw s1,16(a1) -800085d0: 00010337 lui t1,0x10 -800085d4: 00812c23 sw s0,24(sp) -800085d8: 01212823 sw s2,16(sp) -800085dc: 01312623 sw s3,12(sp) -800085e0: 00112e23 sw ra,28(sp) -800085e4: 01412423 sw s4,8(sp) -800085e8: 00058913 mv s2,a1 -800085ec: 00050993 mv s3,a0 -800085f0: 00068413 mv s0,a3 -800085f4: 01458813 addi a6,a1,20 -800085f8: 00000893 li a7,0 -800085fc: fff30313 addi t1,t1,-1 # ffff <_start-0x7fff0001> -80008600: 00082783 lw a5,0(a6) -80008604: 00480813 addi a6,a6,4 -80008608: 00188893 addi a7,a7,1 -8000860c: 0067f6b3 and a3,a5,t1 -80008610: 02c686b3 mul a3,a3,a2 -80008614: 0107d793 srli a5,a5,0x10 -80008618: 02c787b3 mul a5,a5,a2 -8000861c: 008686b3 add a3,a3,s0 -80008620: 0106de13 srli t3,a3,0x10 -80008624: 0066f733 and a4,a3,t1 -80008628: 01c786b3 add a3,a5,t3 -8000862c: 01069793 slli a5,a3,0x10 -80008630: 00e78733 add a4,a5,a4 -80008634: fee82e23 sw a4,-4(a6) -80008638: 0106d413 srli s0,a3,0x10 -8000863c: fc98c2e3 blt a7,s1,80008600 <__multadd+0x3c> -80008640: 02040263 beqz s0,80008664 <__multadd+0xa0> -80008644: 00892783 lw a5,8(s2) -80008648: 04f4d063 bge s1,a5,80008688 <__multadd+0xc4> -8000864c: 00448793 addi a5,s1,4 -80008650: 00279793 slli a5,a5,0x2 -80008654: 00f907b3 add a5,s2,a5 -80008658: 0087a223 sw s0,4(a5) -8000865c: 00148493 addi s1,s1,1 -80008660: 00992823 sw s1,16(s2) -80008664: 01c12083 lw ra,28(sp) -80008668: 01812403 lw s0,24(sp) -8000866c: 01412483 lw s1,20(sp) -80008670: 00c12983 lw s3,12(sp) -80008674: 00812a03 lw s4,8(sp) -80008678: 00090513 mv a0,s2 -8000867c: 01012903 lw s2,16(sp) -80008680: 02010113 addi sp,sp,32 -80008684: 00008067 ret -80008688: 00492583 lw a1,4(s2) -8000868c: 00098513 mv a0,s3 -80008690: 00158593 addi a1,a1,1 -80008694: e65ff0ef jal ra,800084f8 <_Balloc> -80008698: 01092603 lw a2,16(s2) -8000869c: 00050a13 mv s4,a0 -800086a0: 00c90593 addi a1,s2,12 -800086a4: 00260613 addi a2,a2,2 -800086a8: 00261613 slli a2,a2,0x2 -800086ac: 00c50513 addi a0,a0,12 -800086b0: 5f1050ef jal ra,8000e4a0 -800086b4: 00492703 lw a4,4(s2) -800086b8: 04c9a783 lw a5,76(s3) -800086bc: 00271713 slli a4,a4,0x2 -800086c0: 00e787b3 add a5,a5,a4 -800086c4: 0007a703 lw a4,0(a5) -800086c8: 00e92023 sw a4,0(s2) -800086cc: 0127a023 sw s2,0(a5) -800086d0: 000a0913 mv s2,s4 -800086d4: f79ff06f j 8000864c <__multadd+0x88> - -800086d8 <__s2b>: -800086d8: fe010113 addi sp,sp,-32 -800086dc: 00812c23 sw s0,24(sp) -800086e0: 00912a23 sw s1,20(sp) -800086e4: 01212823 sw s2,16(sp) -800086e8: 01312623 sw s3,12(sp) -800086ec: 01412423 sw s4,8(sp) -800086f0: 00868813 addi a6,a3,8 -800086f4: 00900793 li a5,9 -800086f8: 00112e23 sw ra,28(sp) -800086fc: 01512223 sw s5,4(sp) -80008700: 02f84833 div a6,a6,a5 -80008704: 00068993 mv s3,a3 -80008708: 00050913 mv s2,a0 -8000870c: 00058413 mv s0,a1 -80008710: 00060a13 mv s4,a2 -80008714: 00070493 mv s1,a4 -80008718: 0cd7d663 bge a5,a3,800087e4 <__s2b+0x10c> -8000871c: 00100793 li a5,1 +80008614 <__s2b>: +80008614: fe010113 addi sp,sp,-32 +80008618: 00812c23 sw s0,24(sp) +8000861c: 00912a23 sw s1,20(sp) +80008620: 01212823 sw s2,16(sp) +80008624: 01312623 sw s3,12(sp) +80008628: 01412423 sw s4,8(sp) +8000862c: 00868813 addi a6,a3,8 +80008630: 00900793 li a5,9 +80008634: 00112e23 sw ra,28(sp) +80008638: 01512223 sw s5,4(sp) +8000863c: 02f84833 div a6,a6,a5 +80008640: 00068993 mv s3,a3 +80008644: 00050913 mv s2,a0 +80008648: 00058413 mv s0,a1 +8000864c: 00060a13 mv s4,a2 +80008650: 00070493 mv s1,a4 +80008654: 0cd7d663 bge a5,a3,80008720 <__s2b+0x10c> +80008658: 00100793 li a5,1 +8000865c: 00000593 li a1,0 +80008660: 00179793 slli a5,a5,0x1 +80008664: 00158593 addi a1,a1,1 +80008668: ff07cce3 blt a5,a6,80008660 <__s2b+0x4c> +8000866c: 00090513 mv a0,s2 +80008670: dc5ff0ef jal ra,80008434 <_Balloc> +80008674: 00100793 li a5,1 +80008678: 00f52823 sw a5,16(a0) +8000867c: 00952a23 sw s1,20(a0) +80008680: 00900793 li a5,9 +80008684: 00050593 mv a1,a0 +80008688: 0947d663 bge a5,s4,80008714 <__s2b+0x100> +8000868c: 00940a93 addi s5,s0,9 +80008690: 000a8493 mv s1,s5 +80008694: 01440433 add s0,s0,s4 +80008698: 0004c683 lbu a3,0(s1) +8000869c: 00a00613 li a2,10 +800086a0: 00090513 mv a0,s2 +800086a4: fd068693 addi a3,a3,-48 +800086a8: e59ff0ef jal ra,80008500 <__multadd> +800086ac: 00148493 addi s1,s1,1 +800086b0: 00050593 mv a1,a0 +800086b4: fe8492e3 bne s1,s0,80008698 <__s2b+0x84> +800086b8: ff8a0413 addi s0,s4,-8 +800086bc: 008a8433 add s0,s5,s0 +800086c0: 033a5663 bge s4,s3,800086ec <__s2b+0xd8> +800086c4: 414989b3 sub s3,s3,s4 +800086c8: 013409b3 add s3,s0,s3 +800086cc: 00044683 lbu a3,0(s0) +800086d0: 00a00613 li a2,10 +800086d4: 00090513 mv a0,s2 +800086d8: fd068693 addi a3,a3,-48 +800086dc: e25ff0ef jal ra,80008500 <__multadd> +800086e0: 00140413 addi s0,s0,1 +800086e4: 00050593 mv a1,a0 +800086e8: fe8992e3 bne s3,s0,800086cc <__s2b+0xb8> +800086ec: 01c12083 lw ra,28(sp) +800086f0: 01812403 lw s0,24(sp) +800086f4: 01412483 lw s1,20(sp) +800086f8: 01012903 lw s2,16(sp) +800086fc: 00c12983 lw s3,12(sp) +80008700: 00812a03 lw s4,8(sp) +80008704: 00412a83 lw s5,4(sp) +80008708: 00058513 mv a0,a1 +8000870c: 02010113 addi sp,sp,32 +80008710: 00008067 ret +80008714: 00a40413 addi s0,s0,10 +80008718: 00900a13 li s4,9 +8000871c: fa5ff06f j 800086c0 <__s2b+0xac> 80008720: 00000593 li a1,0 -80008724: 00179793 slli a5,a5,0x1 -80008728: 00158593 addi a1,a1,1 -8000872c: ff07cce3 blt a5,a6,80008724 <__s2b+0x4c> -80008730: 00090513 mv a0,s2 -80008734: dc5ff0ef jal ra,800084f8 <_Balloc> -80008738: 00100793 li a5,1 -8000873c: 00f52823 sw a5,16(a0) -80008740: 00952a23 sw s1,20(a0) -80008744: 00900793 li a5,9 -80008748: 00050593 mv a1,a0 -8000874c: 0947d663 bge a5,s4,800087d8 <__s2b+0x100> -80008750: 00940a93 addi s5,s0,9 -80008754: 000a8493 mv s1,s5 -80008758: 01440433 add s0,s0,s4 -8000875c: 0004c683 lbu a3,0(s1) -80008760: 00a00613 li a2,10 -80008764: 00090513 mv a0,s2 -80008768: fd068693 addi a3,a3,-48 -8000876c: e59ff0ef jal ra,800085c4 <__multadd> -80008770: 00148493 addi s1,s1,1 -80008774: 00050593 mv a1,a0 -80008778: fe8492e3 bne s1,s0,8000875c <__s2b+0x84> -8000877c: ff8a0413 addi s0,s4,-8 -80008780: 008a8433 add s0,s5,s0 -80008784: 033a5663 bge s4,s3,800087b0 <__s2b+0xd8> -80008788: 414989b3 sub s3,s3,s4 -8000878c: 013409b3 add s3,s0,s3 -80008790: 00044683 lbu a3,0(s0) -80008794: 00a00613 li a2,10 -80008798: 00090513 mv a0,s2 -8000879c: fd068693 addi a3,a3,-48 -800087a0: e25ff0ef jal ra,800085c4 <__multadd> -800087a4: 00140413 addi s0,s0,1 -800087a8: 00050593 mv a1,a0 -800087ac: fe8992e3 bne s3,s0,80008790 <__s2b+0xb8> -800087b0: 01c12083 lw ra,28(sp) -800087b4: 01812403 lw s0,24(sp) -800087b8: 01412483 lw s1,20(sp) -800087bc: 01012903 lw s2,16(sp) -800087c0: 00c12983 lw s3,12(sp) -800087c4: 00812a03 lw s4,8(sp) -800087c8: 00412a83 lw s5,4(sp) -800087cc: 00058513 mv a0,a1 -800087d0: 02010113 addi sp,sp,32 -800087d4: 00008067 ret -800087d8: 00a40413 addi s0,s0,10 -800087dc: 00900a13 li s4,9 -800087e0: fa5ff06f j 80008784 <__s2b+0xac> -800087e4: 00000593 li a1,0 -800087e8: f49ff06f j 80008730 <__s2b+0x58> +80008724: f49ff06f j 8000866c <__s2b+0x58> -800087ec <__hi0bits>: -800087ec: ffff0737 lui a4,0xffff0 -800087f0: 00e57733 and a4,a0,a4 -800087f4: 00050793 mv a5,a0 -800087f8: 00000513 li a0,0 -800087fc: 00071663 bnez a4,80008808 <__hi0bits+0x1c> -80008800: 01079793 slli a5,a5,0x10 -80008804: 01000513 li a0,16 -80008808: ff000737 lui a4,0xff000 -8000880c: 00e7f733 and a4,a5,a4 -80008810: 00071663 bnez a4,8000881c <__hi0bits+0x30> -80008814: 00850513 addi a0,a0,8 -80008818: 00879793 slli a5,a5,0x8 -8000881c: f0000737 lui a4,0xf0000 -80008820: 00e7f733 and a4,a5,a4 -80008824: 00071663 bnez a4,80008830 <__hi0bits+0x44> -80008828: 00450513 addi a0,a0,4 -8000882c: 00479793 slli a5,a5,0x4 -80008830: c0000737 lui a4,0xc0000 -80008834: 00e7f733 and a4,a5,a4 -80008838: 00071663 bnez a4,80008844 <__hi0bits+0x58> -8000883c: 00250513 addi a0,a0,2 -80008840: 00279793 slli a5,a5,0x2 -80008844: 0007c863 bltz a5,80008854 <__hi0bits+0x68> -80008848: 00179713 slli a4,a5,0x1 -8000884c: 00150513 addi a0,a0,1 -80008850: 00075463 bgez a4,80008858 <__hi0bits+0x6c> -80008854: 00008067 ret -80008858: 02000513 li a0,32 -8000885c: 00008067 ret +80008728 <__hi0bits>: +80008728: ffff0737 lui a4,0xffff0 +8000872c: 00e57733 and a4,a0,a4 +80008730: 00050793 mv a5,a0 +80008734: 00000513 li a0,0 +80008738: 00071663 bnez a4,80008744 <__hi0bits+0x1c> +8000873c: 01079793 slli a5,a5,0x10 +80008740: 01000513 li a0,16 +80008744: ff000737 lui a4,0xff000 +80008748: 00e7f733 and a4,a5,a4 +8000874c: 00071663 bnez a4,80008758 <__hi0bits+0x30> +80008750: 00850513 addi a0,a0,8 +80008754: 00879793 slli a5,a5,0x8 +80008758: f0000737 lui a4,0xf0000 +8000875c: 00e7f733 and a4,a5,a4 +80008760: 00071663 bnez a4,8000876c <__hi0bits+0x44> +80008764: 00450513 addi a0,a0,4 +80008768: 00479793 slli a5,a5,0x4 +8000876c: c0000737 lui a4,0xc0000 +80008770: 00e7f733 and a4,a5,a4 +80008774: 00071663 bnez a4,80008780 <__hi0bits+0x58> +80008778: 00250513 addi a0,a0,2 +8000877c: 00279793 slli a5,a5,0x2 +80008780: 0007c863 bltz a5,80008790 <__hi0bits+0x68> +80008784: 00179713 slli a4,a5,0x1 +80008788: 00150513 addi a0,a0,1 +8000878c: 00075463 bgez a4,80008794 <__hi0bits+0x6c> +80008790: 00008067 ret +80008794: 02000513 li a0,32 +80008798: 00008067 ret -80008860 <__lo0bits>: -80008860: 00052783 lw a5,0(a0) -80008864: 00050713 mv a4,a0 -80008868: 0077f693 andi a3,a5,7 -8000886c: 02068463 beqz a3,80008894 <__lo0bits+0x34> -80008870: 0017f693 andi a3,a5,1 -80008874: 00000513 li a0,0 -80008878: 06069e63 bnez a3,800088f4 <__lo0bits+0x94> -8000887c: 0027f693 andi a3,a5,2 -80008880: 08068063 beqz a3,80008900 <__lo0bits+0xa0> -80008884: 0017d793 srli a5,a5,0x1 -80008888: 00f72023 sw a5,0(a4) # c0000000 <__BSS_END__+0x3ffe93c4> -8000888c: 00100513 li a0,1 -80008890: 00008067 ret -80008894: 01079693 slli a3,a5,0x10 -80008898: 0106d693 srli a3,a3,0x10 -8000889c: 00000513 li a0,0 -800088a0: 00069663 bnez a3,800088ac <__lo0bits+0x4c> -800088a4: 0107d793 srli a5,a5,0x10 -800088a8: 01000513 li a0,16 -800088ac: 0ff7f693 andi a3,a5,255 -800088b0: 00069663 bnez a3,800088bc <__lo0bits+0x5c> -800088b4: 00850513 addi a0,a0,8 -800088b8: 0087d793 srli a5,a5,0x8 -800088bc: 00f7f693 andi a3,a5,15 -800088c0: 00069663 bnez a3,800088cc <__lo0bits+0x6c> -800088c4: 00450513 addi a0,a0,4 -800088c8: 0047d793 srli a5,a5,0x4 -800088cc: 0037f693 andi a3,a5,3 -800088d0: 00069663 bnez a3,800088dc <__lo0bits+0x7c> -800088d4: 00250513 addi a0,a0,2 -800088d8: 0027d793 srli a5,a5,0x2 -800088dc: 0017f693 andi a3,a5,1 -800088e0: 00069c63 bnez a3,800088f8 <__lo0bits+0x98> -800088e4: 0017d793 srli a5,a5,0x1 -800088e8: 00150513 addi a0,a0,1 -800088ec: 00079663 bnez a5,800088f8 <__lo0bits+0x98> -800088f0: 02000513 li a0,32 -800088f4: 00008067 ret -800088f8: 00f72023 sw a5,0(a4) -800088fc: 00008067 ret -80008900: 0027d793 srli a5,a5,0x2 -80008904: 00f72023 sw a5,0(a4) -80008908: 00200513 li a0,2 -8000890c: 00008067 ret +8000879c <__lo0bits>: +8000879c: 00052783 lw a5,0(a0) +800087a0: 00050713 mv a4,a0 +800087a4: 0077f693 andi a3,a5,7 +800087a8: 02068463 beqz a3,800087d0 <__lo0bits+0x34> +800087ac: 0017f693 andi a3,a5,1 +800087b0: 00000513 li a0,0 +800087b4: 06069e63 bnez a3,80008830 <__lo0bits+0x94> +800087b8: 0027f693 andi a3,a5,2 +800087bc: 08068063 beqz a3,8000883c <__lo0bits+0xa0> +800087c0: 0017d793 srli a5,a5,0x1 +800087c4: 00f72023 sw a5,0(a4) # c0000000 <__BSS_END__+0x3ffe93c4> +800087c8: 00100513 li a0,1 +800087cc: 00008067 ret +800087d0: 01079693 slli a3,a5,0x10 +800087d4: 0106d693 srli a3,a3,0x10 +800087d8: 00000513 li a0,0 +800087dc: 00069663 bnez a3,800087e8 <__lo0bits+0x4c> +800087e0: 0107d793 srli a5,a5,0x10 +800087e4: 01000513 li a0,16 +800087e8: 0ff7f693 andi a3,a5,255 +800087ec: 00069663 bnez a3,800087f8 <__lo0bits+0x5c> +800087f0: 00850513 addi a0,a0,8 +800087f4: 0087d793 srli a5,a5,0x8 +800087f8: 00f7f693 andi a3,a5,15 +800087fc: 00069663 bnez a3,80008808 <__lo0bits+0x6c> +80008800: 00450513 addi a0,a0,4 +80008804: 0047d793 srli a5,a5,0x4 +80008808: 0037f693 andi a3,a5,3 +8000880c: 00069663 bnez a3,80008818 <__lo0bits+0x7c> +80008810: 00250513 addi a0,a0,2 +80008814: 0027d793 srli a5,a5,0x2 +80008818: 0017f693 andi a3,a5,1 +8000881c: 00069c63 bnez a3,80008834 <__lo0bits+0x98> +80008820: 0017d793 srli a5,a5,0x1 +80008824: 00150513 addi a0,a0,1 +80008828: 00079663 bnez a5,80008834 <__lo0bits+0x98> +8000882c: 02000513 li a0,32 +80008830: 00008067 ret +80008834: 00f72023 sw a5,0(a4) +80008838: 00008067 ret +8000883c: 0027d793 srli a5,a5,0x2 +80008840: 00f72023 sw a5,0(a4) +80008844: 00200513 li a0,2 +80008848: 00008067 ret -80008910 <__i2b>: -80008910: ff010113 addi sp,sp,-16 -80008914: 00812423 sw s0,8(sp) -80008918: 00058413 mv s0,a1 -8000891c: 00100593 li a1,1 -80008920: 00112623 sw ra,12(sp) -80008924: bd5ff0ef jal ra,800084f8 <_Balloc> -80008928: 00c12083 lw ra,12(sp) -8000892c: 00852a23 sw s0,20(a0) -80008930: 00812403 lw s0,8(sp) -80008934: 00100713 li a4,1 -80008938: 00e52823 sw a4,16(a0) -8000893c: 01010113 addi sp,sp,16 -80008940: 00008067 ret +8000884c <__i2b>: +8000884c: ff010113 addi sp,sp,-16 +80008850: 00812423 sw s0,8(sp) +80008854: 00058413 mv s0,a1 +80008858: 00100593 li a1,1 +8000885c: 00112623 sw ra,12(sp) +80008860: bd5ff0ef jal ra,80008434 <_Balloc> +80008864: 00c12083 lw ra,12(sp) +80008868: 00852a23 sw s0,20(a0) +8000886c: 00812403 lw s0,8(sp) +80008870: 00100713 li a4,1 +80008874: 00e52823 sw a4,16(a0) +80008878: 01010113 addi sp,sp,16 +8000887c: 00008067 ret -80008944 <__multiply>: -80008944: fe010113 addi sp,sp,-32 -80008948: 01212823 sw s2,16(sp) -8000894c: 01312623 sw s3,12(sp) -80008950: 0105a903 lw s2,16(a1) -80008954: 01062983 lw s3,16(a2) -80008958: 00912a23 sw s1,20(sp) -8000895c: 01412423 sw s4,8(sp) -80008960: 00112e23 sw ra,28(sp) -80008964: 00812c23 sw s0,24(sp) -80008968: 00058a13 mv s4,a1 -8000896c: 00060493 mv s1,a2 -80008970: 01394c63 blt s2,s3,80008988 <__multiply+0x44> -80008974: 00098713 mv a4,s3 -80008978: 00058493 mv s1,a1 -8000897c: 00090993 mv s3,s2 -80008980: 00060a13 mv s4,a2 -80008984: 00070913 mv s2,a4 -80008988: 0084a783 lw a5,8(s1) -8000898c: 0044a583 lw a1,4(s1) -80008990: 01298433 add s0,s3,s2 -80008994: 0087a7b3 slt a5,a5,s0 -80008998: 00f585b3 add a1,a1,a5 -8000899c: b5dff0ef jal ra,800084f8 <_Balloc> -800089a0: 01450313 addi t1,a0,20 -800089a4: 00241893 slli a7,s0,0x2 -800089a8: 011308b3 add a7,t1,a7 -800089ac: 00030793 mv a5,t1 -800089b0: 01137863 bgeu t1,a7,800089c0 <__multiply+0x7c> -800089b4: 0007a023 sw zero,0(a5) -800089b8: 00478793 addi a5,a5,4 -800089bc: ff17ece3 bltu a5,a7,800089b4 <__multiply+0x70> -800089c0: 014a0813 addi a6,s4,20 -800089c4: 00291e13 slli t3,s2,0x2 -800089c8: 01448e93 addi t4,s1,20 -800089cc: 00299593 slli a1,s3,0x2 -800089d0: 01c80e33 add t3,a6,t3 -800089d4: 00be85b3 add a1,t4,a1 -800089d8: 13c87663 bgeu a6,t3,80008b04 <__multiply+0x1c0> -800089dc: 01548793 addi a5,s1,21 -800089e0: 00400f13 li t5,4 -800089e4: 16f5f063 bgeu a1,a5,80008b44 <__multiply+0x200> -800089e8: 00010637 lui a2,0x10 -800089ec: fff60613 addi a2,a2,-1 # ffff <_start-0x7fff0001> -800089f0: 0180006f j 80008a08 <__multiply+0xc4> -800089f4: 010fdf93 srli t6,t6,0x10 -800089f8: 080f9863 bnez t6,80008a88 <__multiply+0x144> -800089fc: 00480813 addi a6,a6,4 -80008a00: 00430313 addi t1,t1,4 -80008a04: 11c87063 bgeu a6,t3,80008b04 <__multiply+0x1c0> -80008a08: 00082f83 lw t6,0(a6) -80008a0c: 00cff4b3 and s1,t6,a2 -80008a10: fe0482e3 beqz s1,800089f4 <__multiply+0xb0> -80008a14: 00030393 mv t2,t1 -80008a18: 000e8293 mv t0,t4 -80008a1c: 00000913 li s2,0 -80008a20: 0002a703 lw a4,0(t0) # 800084c8 -80008a24: 0003af83 lw t6,0(t2) -80008a28: 00438393 addi t2,t2,4 -80008a2c: 00c776b3 and a3,a4,a2 -80008a30: 029686b3 mul a3,a3,s1 -80008a34: 01075793 srli a5,a4,0x10 -80008a38: 00cff733 and a4,t6,a2 -80008a3c: 010fdf93 srli t6,t6,0x10 -80008a40: 00428293 addi t0,t0,4 -80008a44: 029787b3 mul a5,a5,s1 -80008a48: 00e686b3 add a3,a3,a4 -80008a4c: 012686b3 add a3,a3,s2 -80008a50: 0106d713 srli a4,a3,0x10 -80008a54: 00c6f6b3 and a3,a3,a2 -80008a58: 01f787b3 add a5,a5,t6 -80008a5c: 00e787b3 add a5,a5,a4 -80008a60: 01079713 slli a4,a5,0x10 -80008a64: 00d766b3 or a3,a4,a3 -80008a68: fed3ae23 sw a3,-4(t2) -80008a6c: 0107d913 srli s2,a5,0x10 -80008a70: fab2e8e3 bltu t0,a1,80008a20 <__multiply+0xdc> -80008a74: 01e307b3 add a5,t1,t5 -80008a78: 0127a023 sw s2,0(a5) -80008a7c: 00082f83 lw t6,0(a6) -80008a80: 010fdf93 srli t6,t6,0x10 -80008a84: f60f8ce3 beqz t6,800089fc <__multiply+0xb8> -80008a88: 00032703 lw a4,0(t1) -80008a8c: 00030293 mv t0,t1 -80008a90: 000e8693 mv a3,t4 -80008a94: 00070493 mv s1,a4 -80008a98: 00000393 li t2,0 -80008a9c: 0006a783 lw a5,0(a3) -80008aa0: 0104d993 srli s3,s1,0x10 -80008aa4: 00c77733 and a4,a4,a2 -80008aa8: 00c7f7b3 and a5,a5,a2 -80008aac: 03f787b3 mul a5,a5,t6 -80008ab0: 0042a483 lw s1,4(t0) -80008ab4: 00428293 addi t0,t0,4 -80008ab8: 00468693 addi a3,a3,4 -80008abc: 00c4f933 and s2,s1,a2 -80008ac0: 013787b3 add a5,a5,s3 -80008ac4: 007787b3 add a5,a5,t2 -80008ac8: 01079393 slli t2,a5,0x10 -80008acc: 00e3e733 or a4,t2,a4 -80008ad0: fee2ae23 sw a4,-4(t0) -80008ad4: ffe6d703 lhu a4,-2(a3) -80008ad8: 0107d793 srli a5,a5,0x10 -80008adc: 03f70733 mul a4,a4,t6 -80008ae0: 01270733 add a4,a4,s2 -80008ae4: 00f70733 add a4,a4,a5 -80008ae8: 01075393 srli t2,a4,0x10 -80008aec: fab6e8e3 bltu a3,a1,80008a9c <__multiply+0x158> -80008af0: 01e307b3 add a5,t1,t5 -80008af4: 00e7a023 sw a4,0(a5) -80008af8: 00480813 addi a6,a6,4 -80008afc: 00430313 addi t1,t1,4 -80008b00: f1c864e3 bltu a6,t3,80008a08 <__multiply+0xc4> -80008b04: 00804863 bgtz s0,80008b14 <__multiply+0x1d0> -80008b08: 0180006f j 80008b20 <__multiply+0x1dc> -80008b0c: fff40413 addi s0,s0,-1 -80008b10: 00040863 beqz s0,80008b20 <__multiply+0x1dc> -80008b14: ffc8a783 lw a5,-4(a7) -80008b18: ffc88893 addi a7,a7,-4 -80008b1c: fe0788e3 beqz a5,80008b0c <__multiply+0x1c8> -80008b20: 01c12083 lw ra,28(sp) -80008b24: 00852823 sw s0,16(a0) -80008b28: 01812403 lw s0,24(sp) -80008b2c: 01412483 lw s1,20(sp) -80008b30: 01012903 lw s2,16(sp) -80008b34: 00c12983 lw s3,12(sp) -80008b38: 00812a03 lw s4,8(sp) -80008b3c: 02010113 addi sp,sp,32 -80008b40: 00008067 ret -80008b44: 40958f33 sub t5,a1,s1 -80008b48: febf0f13 addi t5,t5,-21 -80008b4c: ffcf7f13 andi t5,t5,-4 -80008b50: 004f0f13 addi t5,t5,4 -80008b54: e95ff06f j 800089e8 <__multiply+0xa4> +80008880 <__multiply>: +80008880: fe010113 addi sp,sp,-32 +80008884: 01212823 sw s2,16(sp) +80008888: 01312623 sw s3,12(sp) +8000888c: 0105a903 lw s2,16(a1) +80008890: 01062983 lw s3,16(a2) +80008894: 00912a23 sw s1,20(sp) +80008898: 01412423 sw s4,8(sp) +8000889c: 00112e23 sw ra,28(sp) +800088a0: 00812c23 sw s0,24(sp) +800088a4: 00058a13 mv s4,a1 +800088a8: 00060493 mv s1,a2 +800088ac: 01394c63 blt s2,s3,800088c4 <__multiply+0x44> +800088b0: 00098713 mv a4,s3 +800088b4: 00058493 mv s1,a1 +800088b8: 00090993 mv s3,s2 +800088bc: 00060a13 mv s4,a2 +800088c0: 00070913 mv s2,a4 +800088c4: 0084a783 lw a5,8(s1) +800088c8: 0044a583 lw a1,4(s1) +800088cc: 01298433 add s0,s3,s2 +800088d0: 0087a7b3 slt a5,a5,s0 +800088d4: 00f585b3 add a1,a1,a5 +800088d8: b5dff0ef jal ra,80008434 <_Balloc> +800088dc: 01450313 addi t1,a0,20 +800088e0: 00241893 slli a7,s0,0x2 +800088e4: 011308b3 add a7,t1,a7 +800088e8: 00030793 mv a5,t1 +800088ec: 01137863 bgeu t1,a7,800088fc <__multiply+0x7c> +800088f0: 0007a023 sw zero,0(a5) +800088f4: 00478793 addi a5,a5,4 +800088f8: ff17ece3 bltu a5,a7,800088f0 <__multiply+0x70> +800088fc: 014a0813 addi a6,s4,20 +80008900: 00291e13 slli t3,s2,0x2 +80008904: 01448e93 addi t4,s1,20 +80008908: 00299593 slli a1,s3,0x2 +8000890c: 01c80e33 add t3,a6,t3 +80008910: 00be85b3 add a1,t4,a1 +80008914: 13c87663 bgeu a6,t3,80008a40 <__multiply+0x1c0> +80008918: 01548793 addi a5,s1,21 +8000891c: 00400f13 li t5,4 +80008920: 16f5f063 bgeu a1,a5,80008a80 <__multiply+0x200> +80008924: 00010637 lui a2,0x10 +80008928: fff60613 addi a2,a2,-1 # ffff <_start-0x7fff0001> +8000892c: 0180006f j 80008944 <__multiply+0xc4> +80008930: 010fdf93 srli t6,t6,0x10 +80008934: 080f9863 bnez t6,800089c4 <__multiply+0x144> +80008938: 00480813 addi a6,a6,4 +8000893c: 00430313 addi t1,t1,4 +80008940: 11c87063 bgeu a6,t3,80008a40 <__multiply+0x1c0> +80008944: 00082f83 lw t6,0(a6) +80008948: 00cff4b3 and s1,t6,a2 +8000894c: fe0482e3 beqz s1,80008930 <__multiply+0xb0> +80008950: 00030393 mv t2,t1 +80008954: 000e8293 mv t0,t4 +80008958: 00000913 li s2,0 +8000895c: 0002a703 lw a4,0(t0) # 80008404 +80008960: 0003af83 lw t6,0(t2) +80008964: 00438393 addi t2,t2,4 +80008968: 00c776b3 and a3,a4,a2 +8000896c: 029686b3 mul a3,a3,s1 +80008970: 01075793 srli a5,a4,0x10 +80008974: 00cff733 and a4,t6,a2 +80008978: 010fdf93 srli t6,t6,0x10 +8000897c: 00428293 addi t0,t0,4 +80008980: 029787b3 mul a5,a5,s1 +80008984: 00e686b3 add a3,a3,a4 +80008988: 012686b3 add a3,a3,s2 +8000898c: 0106d713 srli a4,a3,0x10 +80008990: 00c6f6b3 and a3,a3,a2 +80008994: 01f787b3 add a5,a5,t6 +80008998: 00e787b3 add a5,a5,a4 +8000899c: 01079713 slli a4,a5,0x10 +800089a0: 00d766b3 or a3,a4,a3 +800089a4: fed3ae23 sw a3,-4(t2) +800089a8: 0107d913 srli s2,a5,0x10 +800089ac: fab2e8e3 bltu t0,a1,8000895c <__multiply+0xdc> +800089b0: 01e307b3 add a5,t1,t5 +800089b4: 0127a023 sw s2,0(a5) +800089b8: 00082f83 lw t6,0(a6) +800089bc: 010fdf93 srli t6,t6,0x10 +800089c0: f60f8ce3 beqz t6,80008938 <__multiply+0xb8> +800089c4: 00032703 lw a4,0(t1) +800089c8: 00030293 mv t0,t1 +800089cc: 000e8693 mv a3,t4 +800089d0: 00070493 mv s1,a4 +800089d4: 00000393 li t2,0 +800089d8: 0006a783 lw a5,0(a3) +800089dc: 0104d993 srli s3,s1,0x10 +800089e0: 00c77733 and a4,a4,a2 +800089e4: 00c7f7b3 and a5,a5,a2 +800089e8: 03f787b3 mul a5,a5,t6 +800089ec: 0042a483 lw s1,4(t0) +800089f0: 00428293 addi t0,t0,4 +800089f4: 00468693 addi a3,a3,4 +800089f8: 00c4f933 and s2,s1,a2 +800089fc: 013787b3 add a5,a5,s3 +80008a00: 007787b3 add a5,a5,t2 +80008a04: 01079393 slli t2,a5,0x10 +80008a08: 00e3e733 or a4,t2,a4 +80008a0c: fee2ae23 sw a4,-4(t0) +80008a10: ffe6d703 lhu a4,-2(a3) +80008a14: 0107d793 srli a5,a5,0x10 +80008a18: 03f70733 mul a4,a4,t6 +80008a1c: 01270733 add a4,a4,s2 +80008a20: 00f70733 add a4,a4,a5 +80008a24: 01075393 srli t2,a4,0x10 +80008a28: fab6e8e3 bltu a3,a1,800089d8 <__multiply+0x158> +80008a2c: 01e307b3 add a5,t1,t5 +80008a30: 00e7a023 sw a4,0(a5) +80008a34: 00480813 addi a6,a6,4 +80008a38: 00430313 addi t1,t1,4 +80008a3c: f1c864e3 bltu a6,t3,80008944 <__multiply+0xc4> +80008a40: 00804863 bgtz s0,80008a50 <__multiply+0x1d0> +80008a44: 0180006f j 80008a5c <__multiply+0x1dc> +80008a48: fff40413 addi s0,s0,-1 +80008a4c: 00040863 beqz s0,80008a5c <__multiply+0x1dc> +80008a50: ffc8a783 lw a5,-4(a7) +80008a54: ffc88893 addi a7,a7,-4 +80008a58: fe0788e3 beqz a5,80008a48 <__multiply+0x1c8> +80008a5c: 01c12083 lw ra,28(sp) +80008a60: 00852823 sw s0,16(a0) +80008a64: 01812403 lw s0,24(sp) +80008a68: 01412483 lw s1,20(sp) +80008a6c: 01012903 lw s2,16(sp) +80008a70: 00c12983 lw s3,12(sp) +80008a74: 00812a03 lw s4,8(sp) +80008a78: 02010113 addi sp,sp,32 +80008a7c: 00008067 ret +80008a80: 40958f33 sub t5,a1,s1 +80008a84: febf0f13 addi t5,t5,-21 +80008a88: ffcf7f13 andi t5,t5,-4 +80008a8c: 004f0f13 addi t5,t5,4 +80008a90: e95ff06f j 80008924 <__multiply+0xa4> -80008b58 <__pow5mult>: -80008b58: fe010113 addi sp,sp,-32 -80008b5c: 00812c23 sw s0,24(sp) -80008b60: 01312623 sw s3,12(sp) -80008b64: 01412423 sw s4,8(sp) -80008b68: 00112e23 sw ra,28(sp) -80008b6c: 00912a23 sw s1,20(sp) -80008b70: 01212823 sw s2,16(sp) -80008b74: 00367793 andi a5,a2,3 -80008b78: 00060413 mv s0,a2 -80008b7c: 00050993 mv s3,a0 -80008b80: 00058a13 mv s4,a1 -80008b84: 0c079463 bnez a5,80008c4c <__pow5mult+0xf4> -80008b88: 40245413 srai s0,s0,0x2 -80008b8c: 000a0913 mv s2,s4 -80008b90: 06040863 beqz s0,80008c00 <__pow5mult+0xa8> -80008b94: 0489a483 lw s1,72(s3) -80008b98: 0c048e63 beqz s1,80008c74 <__pow5mult+0x11c> -80008b9c: 00147793 andi a5,s0,1 -80008ba0: 000a0913 mv s2,s4 -80008ba4: 02079063 bnez a5,80008bc4 <__pow5mult+0x6c> -80008ba8: 40145413 srai s0,s0,0x1 -80008bac: 04040a63 beqz s0,80008c00 <__pow5mult+0xa8> -80008bb0: 0004a503 lw a0,0(s1) -80008bb4: 06050863 beqz a0,80008c24 <__pow5mult+0xcc> -80008bb8: 00050493 mv s1,a0 -80008bbc: 00147793 andi a5,s0,1 -80008bc0: fe0784e3 beqz a5,80008ba8 <__pow5mult+0x50> -80008bc4: 00048613 mv a2,s1 -80008bc8: 00090593 mv a1,s2 -80008bcc: 00098513 mv a0,s3 -80008bd0: d75ff0ef jal ra,80008944 <__multiply> -80008bd4: 06090863 beqz s2,80008c44 <__pow5mult+0xec> -80008bd8: 00492703 lw a4,4(s2) -80008bdc: 04c9a783 lw a5,76(s3) -80008be0: 40145413 srai s0,s0,0x1 -80008be4: 00271713 slli a4,a4,0x2 -80008be8: 00e787b3 add a5,a5,a4 -80008bec: 0007a703 lw a4,0(a5) -80008bf0: 00e92023 sw a4,0(s2) -80008bf4: 0127a023 sw s2,0(a5) -80008bf8: 00050913 mv s2,a0 -80008bfc: fa041ae3 bnez s0,80008bb0 <__pow5mult+0x58> -80008c00: 01c12083 lw ra,28(sp) -80008c04: 01812403 lw s0,24(sp) -80008c08: 01412483 lw s1,20(sp) -80008c0c: 00c12983 lw s3,12(sp) -80008c10: 00812a03 lw s4,8(sp) -80008c14: 00090513 mv a0,s2 -80008c18: 01012903 lw s2,16(sp) -80008c1c: 02010113 addi sp,sp,32 -80008c20: 00008067 ret -80008c24: 00048613 mv a2,s1 -80008c28: 00048593 mv a1,s1 -80008c2c: 00098513 mv a0,s3 -80008c30: d15ff0ef jal ra,80008944 <__multiply> -80008c34: 00a4a023 sw a0,0(s1) -80008c38: 00052023 sw zero,0(a0) -80008c3c: 00050493 mv s1,a0 -80008c40: f7dff06f j 80008bbc <__pow5mult+0x64> -80008c44: 00050913 mv s2,a0 -80008c48: f61ff06f j 80008ba8 <__pow5mult+0x50> -80008c4c: fff78793 addi a5,a5,-1 -80008c50: 80015737 lui a4,0x80015 -80008c54: 0b870713 addi a4,a4,184 # 800150b8 <__BSS_END__+0xffffe47c> -80008c58: 00279793 slli a5,a5,0x2 -80008c5c: 00f707b3 add a5,a4,a5 -80008c60: 0007a603 lw a2,0(a5) -80008c64: 00000693 li a3,0 -80008c68: 95dff0ef jal ra,800085c4 <__multadd> -80008c6c: 00050a13 mv s4,a0 -80008c70: f19ff06f j 80008b88 <__pow5mult+0x30> -80008c74: 00100593 li a1,1 -80008c78: 00098513 mv a0,s3 -80008c7c: 87dff0ef jal ra,800084f8 <_Balloc> -80008c80: 27100793 li a5,625 -80008c84: 00f52a23 sw a5,20(a0) -80008c88: 00100793 li a5,1 -80008c8c: 00f52823 sw a5,16(a0) -80008c90: 04a9a423 sw a0,72(s3) -80008c94: 00050493 mv s1,a0 -80008c98: 00052023 sw zero,0(a0) -80008c9c: f01ff06f j 80008b9c <__pow5mult+0x44> +80008a94 <__pow5mult>: +80008a94: fe010113 addi sp,sp,-32 +80008a98: 00812c23 sw s0,24(sp) +80008a9c: 01312623 sw s3,12(sp) +80008aa0: 01412423 sw s4,8(sp) +80008aa4: 00112e23 sw ra,28(sp) +80008aa8: 00912a23 sw s1,20(sp) +80008aac: 01212823 sw s2,16(sp) +80008ab0: 00367793 andi a5,a2,3 +80008ab4: 00060413 mv s0,a2 +80008ab8: 00050993 mv s3,a0 +80008abc: 00058a13 mv s4,a1 +80008ac0: 0c079463 bnez a5,80008b88 <__pow5mult+0xf4> +80008ac4: 40245413 srai s0,s0,0x2 +80008ac8: 000a0913 mv s2,s4 +80008acc: 06040863 beqz s0,80008b3c <__pow5mult+0xa8> +80008ad0: 0489a483 lw s1,72(s3) +80008ad4: 0c048e63 beqz s1,80008bb0 <__pow5mult+0x11c> +80008ad8: 00147793 andi a5,s0,1 +80008adc: 000a0913 mv s2,s4 +80008ae0: 02079063 bnez a5,80008b00 <__pow5mult+0x6c> +80008ae4: 40145413 srai s0,s0,0x1 +80008ae8: 04040a63 beqz s0,80008b3c <__pow5mult+0xa8> +80008aec: 0004a503 lw a0,0(s1) +80008af0: 06050863 beqz a0,80008b60 <__pow5mult+0xcc> +80008af4: 00050493 mv s1,a0 +80008af8: 00147793 andi a5,s0,1 +80008afc: fe0784e3 beqz a5,80008ae4 <__pow5mult+0x50> +80008b00: 00048613 mv a2,s1 +80008b04: 00090593 mv a1,s2 +80008b08: 00098513 mv a0,s3 +80008b0c: d75ff0ef jal ra,80008880 <__multiply> +80008b10: 06090863 beqz s2,80008b80 <__pow5mult+0xec> +80008b14: 00492703 lw a4,4(s2) +80008b18: 04c9a783 lw a5,76(s3) +80008b1c: 40145413 srai s0,s0,0x1 +80008b20: 00271713 slli a4,a4,0x2 +80008b24: 00e787b3 add a5,a5,a4 +80008b28: 0007a703 lw a4,0(a5) +80008b2c: 00e92023 sw a4,0(s2) +80008b30: 0127a023 sw s2,0(a5) +80008b34: 00050913 mv s2,a0 +80008b38: fa041ae3 bnez s0,80008aec <__pow5mult+0x58> +80008b3c: 01c12083 lw ra,28(sp) +80008b40: 01812403 lw s0,24(sp) +80008b44: 01412483 lw s1,20(sp) +80008b48: 00c12983 lw s3,12(sp) +80008b4c: 00812a03 lw s4,8(sp) +80008b50: 00090513 mv a0,s2 +80008b54: 01012903 lw s2,16(sp) +80008b58: 02010113 addi sp,sp,32 +80008b5c: 00008067 ret +80008b60: 00048613 mv a2,s1 +80008b64: 00048593 mv a1,s1 +80008b68: 00098513 mv a0,s3 +80008b6c: d15ff0ef jal ra,80008880 <__multiply> +80008b70: 00a4a023 sw a0,0(s1) +80008b74: 00052023 sw zero,0(a0) +80008b78: 00050493 mv s1,a0 +80008b7c: f7dff06f j 80008af8 <__pow5mult+0x64> +80008b80: 00050913 mv s2,a0 +80008b84: f61ff06f j 80008ae4 <__pow5mult+0x50> +80008b88: fff78793 addi a5,a5,-1 +80008b8c: 80015737 lui a4,0x80015 +80008b90: fe070713 addi a4,a4,-32 # 80014fe0 <__BSS_END__+0xffffe3a4> +80008b94: 00279793 slli a5,a5,0x2 +80008b98: 00f707b3 add a5,a4,a5 +80008b9c: 0007a603 lw a2,0(a5) +80008ba0: 00000693 li a3,0 +80008ba4: 95dff0ef jal ra,80008500 <__multadd> +80008ba8: 00050a13 mv s4,a0 +80008bac: f19ff06f j 80008ac4 <__pow5mult+0x30> +80008bb0: 00100593 li a1,1 +80008bb4: 00098513 mv a0,s3 +80008bb8: 87dff0ef jal ra,80008434 <_Balloc> +80008bbc: 27100793 li a5,625 +80008bc0: 00f52a23 sw a5,20(a0) +80008bc4: 00100793 li a5,1 +80008bc8: 00f52823 sw a5,16(a0) +80008bcc: 04a9a423 sw a0,72(s3) +80008bd0: 00050493 mv s1,a0 +80008bd4: 00052023 sw zero,0(a0) +80008bd8: f01ff06f j 80008ad8 <__pow5mult+0x44> -80008ca0 <__lshift>: -80008ca0: fe010113 addi sp,sp,-32 -80008ca4: 01412423 sw s4,8(sp) -80008ca8: 0105aa03 lw s4,16(a1) -80008cac: 0085a783 lw a5,8(a1) -80008cb0: 01312623 sw s3,12(sp) -80008cb4: 40565993 srai s3,a2,0x5 -80008cb8: 01498a33 add s4,s3,s4 -80008cbc: 00812c23 sw s0,24(sp) -80008cc0: 00912a23 sw s1,20(sp) -80008cc4: 01212823 sw s2,16(sp) -80008cc8: 01512223 sw s5,4(sp) -80008ccc: 00112e23 sw ra,28(sp) -80008cd0: 001a0913 addi s2,s4,1 -80008cd4: 00058493 mv s1,a1 -80008cd8: 00060413 mv s0,a2 -80008cdc: 0045a583 lw a1,4(a1) -80008ce0: 00050a93 mv s5,a0 -80008ce4: 0127d863 bge a5,s2,80008cf4 <__lshift+0x54> -80008ce8: 00179793 slli a5,a5,0x1 -80008cec: 00158593 addi a1,a1,1 -80008cf0: ff27cce3 blt a5,s2,80008ce8 <__lshift+0x48> -80008cf4: 000a8513 mv a0,s5 -80008cf8: 801ff0ef jal ra,800084f8 <_Balloc> -80008cfc: 01450813 addi a6,a0,20 -80008d00: 03305463 blez s3,80008d28 <__lshift+0x88> -80008d04: 00598993 addi s3,s3,5 -80008d08: 00299993 slli s3,s3,0x2 -80008d0c: 01350733 add a4,a0,s3 -80008d10: 00080793 mv a5,a6 +80008bdc <__lshift>: +80008bdc: fe010113 addi sp,sp,-32 +80008be0: 01412423 sw s4,8(sp) +80008be4: 0105aa03 lw s4,16(a1) +80008be8: 0085a783 lw a5,8(a1) +80008bec: 01312623 sw s3,12(sp) +80008bf0: 40565993 srai s3,a2,0x5 +80008bf4: 01498a33 add s4,s3,s4 +80008bf8: 00812c23 sw s0,24(sp) +80008bfc: 00912a23 sw s1,20(sp) +80008c00: 01212823 sw s2,16(sp) +80008c04: 01512223 sw s5,4(sp) +80008c08: 00112e23 sw ra,28(sp) +80008c0c: 001a0913 addi s2,s4,1 +80008c10: 00058493 mv s1,a1 +80008c14: 00060413 mv s0,a2 +80008c18: 0045a583 lw a1,4(a1) +80008c1c: 00050a93 mv s5,a0 +80008c20: 0127d863 bge a5,s2,80008c30 <__lshift+0x54> +80008c24: 00179793 slli a5,a5,0x1 +80008c28: 00158593 addi a1,a1,1 +80008c2c: ff27cce3 blt a5,s2,80008c24 <__lshift+0x48> +80008c30: 000a8513 mv a0,s5 +80008c34: 801ff0ef jal ra,80008434 <_Balloc> +80008c38: 01450813 addi a6,a0,20 +80008c3c: 03305463 blez s3,80008c64 <__lshift+0x88> +80008c40: 00598993 addi s3,s3,5 +80008c44: 00299993 slli s3,s3,0x2 +80008c48: 01350733 add a4,a0,s3 +80008c4c: 00080793 mv a5,a6 +80008c50: 00478793 addi a5,a5,4 +80008c54: fe07ae23 sw zero,-4(a5) +80008c58: fee79ce3 bne a5,a4,80008c50 <__lshift+0x74> +80008c5c: fec98993 addi s3,s3,-20 +80008c60: 01380833 add a6,a6,s3 +80008c64: 0104a703 lw a4,16(s1) +80008c68: 01448793 addi a5,s1,20 +80008c6c: 01f47313 andi t1,s0,31 +80008c70: 00271613 slli a2,a4,0x2 +80008c74: 00c78633 add a2,a5,a2 +80008c78: 08030c63 beqz t1,80008d10 <__lshift+0x134> +80008c7c: 02000593 li a1,32 +80008c80: 406585b3 sub a1,a1,t1 +80008c84: 00080893 mv a7,a6 +80008c88: 00000693 li a3,0 +80008c8c: 0007a703 lw a4,0(a5) +80008c90: 00488893 addi a7,a7,4 +80008c94: 00478793 addi a5,a5,4 +80008c98: 00671733 sll a4,a4,t1 +80008c9c: 00d76733 or a4,a4,a3 +80008ca0: fee8ae23 sw a4,-4(a7) +80008ca4: ffc7a703 lw a4,-4(a5) +80008ca8: 00b756b3 srl a3,a4,a1 +80008cac: fec7e0e3 bltu a5,a2,80008c8c <__lshift+0xb0> +80008cb0: 01548713 addi a4,s1,21 +80008cb4: 00400793 li a5,4 +80008cb8: 08e67263 bgeu a2,a4,80008d3c <__lshift+0x160> +80008cbc: 00f80833 add a6,a6,a5 +80008cc0: 00d82023 sw a3,0(a6) +80008cc4: 00068463 beqz a3,80008ccc <__lshift+0xf0> +80008cc8: 00090a13 mv s4,s2 +80008ccc: 0044a703 lw a4,4(s1) +80008cd0: 04caa783 lw a5,76(s5) +80008cd4: 01c12083 lw ra,28(sp) +80008cd8: 00271713 slli a4,a4,0x2 +80008cdc: 00e787b3 add a5,a5,a4 +80008ce0: 0007a703 lw a4,0(a5) +80008ce4: 01452823 sw s4,16(a0) +80008ce8: 01812403 lw s0,24(sp) +80008cec: 00e4a023 sw a4,0(s1) +80008cf0: 0097a023 sw s1,0(a5) +80008cf4: 01012903 lw s2,16(sp) +80008cf8: 01412483 lw s1,20(sp) +80008cfc: 00c12983 lw s3,12(sp) +80008d00: 00812a03 lw s4,8(sp) +80008d04: 00412a83 lw s5,4(sp) +80008d08: 02010113 addi sp,sp,32 +80008d0c: 00008067 ret +80008d10: 0007a703 lw a4,0(a5) 80008d14: 00478793 addi a5,a5,4 -80008d18: fe07ae23 sw zero,-4(a5) -80008d1c: fee79ce3 bne a5,a4,80008d14 <__lshift+0x74> -80008d20: fec98993 addi s3,s3,-20 -80008d24: 01380833 add a6,a6,s3 -80008d28: 0104a703 lw a4,16(s1) -80008d2c: 01448793 addi a5,s1,20 -80008d30: 01f47313 andi t1,s0,31 -80008d34: 00271613 slli a2,a4,0x2 -80008d38: 00c78633 add a2,a5,a2 -80008d3c: 08030c63 beqz t1,80008dd4 <__lshift+0x134> -80008d40: 02000593 li a1,32 -80008d44: 406585b3 sub a1,a1,t1 -80008d48: 00080893 mv a7,a6 -80008d4c: 00000693 li a3,0 -80008d50: 0007a703 lw a4,0(a5) -80008d54: 00488893 addi a7,a7,4 -80008d58: 00478793 addi a5,a5,4 -80008d5c: 00671733 sll a4,a4,t1 -80008d60: 00d76733 or a4,a4,a3 -80008d64: fee8ae23 sw a4,-4(a7) -80008d68: ffc7a703 lw a4,-4(a5) -80008d6c: 00b756b3 srl a3,a4,a1 -80008d70: fec7e0e3 bltu a5,a2,80008d50 <__lshift+0xb0> -80008d74: 01548713 addi a4,s1,21 -80008d78: 00400793 li a5,4 -80008d7c: 08e67263 bgeu a2,a4,80008e00 <__lshift+0x160> -80008d80: 00f80833 add a6,a6,a5 -80008d84: 00d82023 sw a3,0(a6) -80008d88: 00068463 beqz a3,80008d90 <__lshift+0xf0> -80008d8c: 00090a13 mv s4,s2 -80008d90: 0044a703 lw a4,4(s1) -80008d94: 04caa783 lw a5,76(s5) -80008d98: 01c12083 lw ra,28(sp) -80008d9c: 00271713 slli a4,a4,0x2 -80008da0: 00e787b3 add a5,a5,a4 -80008da4: 0007a703 lw a4,0(a5) -80008da8: 01452823 sw s4,16(a0) -80008dac: 01812403 lw s0,24(sp) -80008db0: 00e4a023 sw a4,0(s1) -80008db4: 0097a023 sw s1,0(a5) -80008db8: 01012903 lw s2,16(sp) -80008dbc: 01412483 lw s1,20(sp) -80008dc0: 00c12983 lw s3,12(sp) -80008dc4: 00812a03 lw s4,8(sp) -80008dc8: 00412a83 lw s5,4(sp) -80008dcc: 02010113 addi sp,sp,32 -80008dd0: 00008067 ret -80008dd4: 0007a703 lw a4,0(a5) -80008dd8: 00478793 addi a5,a5,4 -80008ddc: 00480813 addi a6,a6,4 -80008de0: fee82e23 sw a4,-4(a6) -80008de4: fac7f6e3 bgeu a5,a2,80008d90 <__lshift+0xf0> -80008de8: 0007a703 lw a4,0(a5) -80008dec: 00478793 addi a5,a5,4 -80008df0: 00480813 addi a6,a6,4 -80008df4: fee82e23 sw a4,-4(a6) -80008df8: fcc7eee3 bltu a5,a2,80008dd4 <__lshift+0x134> -80008dfc: f95ff06f j 80008d90 <__lshift+0xf0> -80008e00: 409607b3 sub a5,a2,s1 -80008e04: feb78793 addi a5,a5,-21 -80008e08: ffc7f793 andi a5,a5,-4 -80008e0c: 00478793 addi a5,a5,4 -80008e10: 00f80833 add a6,a6,a5 -80008e14: 00d82023 sw a3,0(a6) -80008e18: f6068ce3 beqz a3,80008d90 <__lshift+0xf0> -80008e1c: f71ff06f j 80008d8c <__lshift+0xec> +80008d18: 00480813 addi a6,a6,4 +80008d1c: fee82e23 sw a4,-4(a6) +80008d20: fac7f6e3 bgeu a5,a2,80008ccc <__lshift+0xf0> +80008d24: 0007a703 lw a4,0(a5) +80008d28: 00478793 addi a5,a5,4 +80008d2c: 00480813 addi a6,a6,4 +80008d30: fee82e23 sw a4,-4(a6) +80008d34: fcc7eee3 bltu a5,a2,80008d10 <__lshift+0x134> +80008d38: f95ff06f j 80008ccc <__lshift+0xf0> +80008d3c: 409607b3 sub a5,a2,s1 +80008d40: feb78793 addi a5,a5,-21 +80008d44: ffc7f793 andi a5,a5,-4 +80008d48: 00478793 addi a5,a5,4 +80008d4c: 00f80833 add a6,a6,a5 +80008d50: 00d82023 sw a3,0(a6) +80008d54: f6068ce3 beqz a3,80008ccc <__lshift+0xf0> +80008d58: f71ff06f j 80008cc8 <__lshift+0xec> -80008e20 <__mcmp>: -80008e20: 01052703 lw a4,16(a0) -80008e24: 0105a783 lw a5,16(a1) -80008e28: 00050813 mv a6,a0 -80008e2c: 40f70533 sub a0,a4,a5 -80008e30: 04f71463 bne a4,a5,80008e78 <__mcmp+0x58> -80008e34: 00279793 slli a5,a5,0x2 -80008e38: 01480813 addi a6,a6,20 -80008e3c: 01458593 addi a1,a1,20 -80008e40: 00f80733 add a4,a6,a5 -80008e44: 00f587b3 add a5,a1,a5 -80008e48: 0080006f j 80008e50 <__mcmp+0x30> -80008e4c: 02e87663 bgeu a6,a4,80008e78 <__mcmp+0x58> -80008e50: ffc72683 lw a3,-4(a4) -80008e54: ffc7a603 lw a2,-4(a5) -80008e58: ffc70713 addi a4,a4,-4 -80008e5c: ffc78793 addi a5,a5,-4 -80008e60: fec686e3 beq a3,a2,80008e4c <__mcmp+0x2c> -80008e64: 00c6b6b3 sltu a3,a3,a2 -80008e68: 40d00533 neg a0,a3 -80008e6c: ffe57513 andi a0,a0,-2 -80008e70: 00150513 addi a0,a0,1 -80008e74: 00008067 ret -80008e78: 00008067 ret +80008d5c <__mcmp>: +80008d5c: 01052703 lw a4,16(a0) +80008d60: 0105a783 lw a5,16(a1) +80008d64: 00050813 mv a6,a0 +80008d68: 40f70533 sub a0,a4,a5 +80008d6c: 04f71463 bne a4,a5,80008db4 <__mcmp+0x58> +80008d70: 00279793 slli a5,a5,0x2 +80008d74: 01480813 addi a6,a6,20 +80008d78: 01458593 addi a1,a1,20 +80008d7c: 00f80733 add a4,a6,a5 +80008d80: 00f587b3 add a5,a1,a5 +80008d84: 0080006f j 80008d8c <__mcmp+0x30> +80008d88: 02e87663 bgeu a6,a4,80008db4 <__mcmp+0x58> +80008d8c: ffc72683 lw a3,-4(a4) +80008d90: ffc7a603 lw a2,-4(a5) +80008d94: ffc70713 addi a4,a4,-4 +80008d98: ffc78793 addi a5,a5,-4 +80008d9c: fec686e3 beq a3,a2,80008d88 <__mcmp+0x2c> +80008da0: 00c6b6b3 sltu a3,a3,a2 +80008da4: 40d00533 neg a0,a3 +80008da8: ffe57513 andi a0,a0,-2 +80008dac: 00150513 addi a0,a0,1 +80008db0: 00008067 ret +80008db4: 00008067 ret -80008e7c <__mdiff>: -80008e7c: 0105a783 lw a5,16(a1) -80008e80: 01062703 lw a4,16(a2) -80008e84: fe010113 addi sp,sp,-32 -80008e88: 00812c23 sw s0,24(sp) -80008e8c: 00912a23 sw s1,20(sp) -80008e90: 01212823 sw s2,16(sp) -80008e94: 01312623 sw s3,12(sp) -80008e98: 01412423 sw s4,8(sp) -80008e9c: 00112e23 sw ra,28(sp) -80008ea0: 00058913 mv s2,a1 -80008ea4: 00060993 mv s3,a2 -80008ea8: 40e78a33 sub s4,a5,a4 -80008eac: 01458413 addi s0,a1,20 -80008eb0: 01460493 addi s1,a2,20 -80008eb4: 04e79863 bne a5,a4,80008f04 <__mdiff+0x88> -80008eb8: 00271713 slli a4,a4,0x2 -80008ebc: 00e407b3 add a5,s0,a4 -80008ec0: 00e48733 add a4,s1,a4 -80008ec4: 0080006f j 80008ecc <__mdiff+0x50> -80008ec8: 1af47063 bgeu s0,a5,80009068 <__mdiff+0x1ec> -80008ecc: ffc7a803 lw a6,-4(a5) -80008ed0: ffc72683 lw a3,-4(a4) -80008ed4: ffc78793 addi a5,a5,-4 -80008ed8: ffc70713 addi a4,a4,-4 -80008edc: fed806e3 beq a6,a3,80008ec8 <__mdiff+0x4c> -80008ee0: 02d87663 bgeu a6,a3,80008f0c <__mdiff+0x90> -80008ee4: 00040713 mv a4,s0 -80008ee8: 00090793 mv a5,s2 -80008eec: 00048413 mv s0,s1 -80008ef0: 00098913 mv s2,s3 -80008ef4: 00070493 mv s1,a4 -80008ef8: 00078993 mv s3,a5 -80008efc: 00100a13 li s4,1 -80008f00: 00c0006f j 80008f0c <__mdiff+0x90> -80008f04: fe0a40e3 bltz s4,80008ee4 <__mdiff+0x68> -80008f08: 00000a13 li s4,0 -80008f0c: 00492583 lw a1,4(s2) -80008f10: de8ff0ef jal ra,800084f8 <_Balloc> -80008f14: 01092e03 lw t3,16(s2) -80008f18: 0109af83 lw t6,16(s3) -80008f1c: 01450293 addi t0,a0,20 -80008f20: 002e1e93 slli t4,t3,0x2 -80008f24: 002f9f93 slli t6,t6,0x2 -80008f28: 000108b7 lui a7,0x10 -80008f2c: 01452623 sw s4,12(a0) -80008f30: 01d40eb3 add t4,s0,t4 -80008f34: 01f48fb3 add t6,s1,t6 -80008f38: 00028f13 mv t5,t0 -80008f3c: 00048813 mv a6,s1 -80008f40: 00040313 mv t1,s0 -80008f44: 00000793 li a5,0 -80008f48: fff88893 addi a7,a7,-1 # ffff <_start-0x7fff0001> -80008f4c: 00032703 lw a4,0(t1) -80008f50: 00082583 lw a1,0(a6) -80008f54: 004f0f13 addi t5,t5,4 -80008f58: 011776b3 and a3,a4,a7 -80008f5c: 00f686b3 add a3,a3,a5 -80008f60: 0115f7b3 and a5,a1,a7 -80008f64: 40f686b3 sub a3,a3,a5 -80008f68: 0105d593 srli a1,a1,0x10 -80008f6c: 01075793 srli a5,a4,0x10 -80008f70: 40b787b3 sub a5,a5,a1 -80008f74: 4106d713 srai a4,a3,0x10 -80008f78: 00e787b3 add a5,a5,a4 -80008f7c: 01079713 slli a4,a5,0x10 -80008f80: 0116f6b3 and a3,a3,a7 -80008f84: 00d766b3 or a3,a4,a3 -80008f88: 00480813 addi a6,a6,4 -80008f8c: fedf2e23 sw a3,-4(t5) -80008f90: 00430313 addi t1,t1,4 -80008f94: 4107d793 srai a5,a5,0x10 -80008f98: fbf86ae3 bltu a6,t6,80008f4c <__mdiff+0xd0> -80008f9c: fff4c613 not a2,s1 -80008fa0: 00cf8633 add a2,t6,a2 -80008fa4: 00148493 addi s1,s1,1 -80008fa8: 00265613 srli a2,a2,0x2 -80008fac: 00000713 li a4,0 -80008fb0: 009fe463 bltu t6,s1,80008fb8 <__mdiff+0x13c> -80008fb4: 00261713 slli a4,a2,0x2 -80008fb8: 00e28733 add a4,t0,a4 -80008fbc: 00400593 li a1,4 -80008fc0: 009fe663 bltu t6,s1,80008fcc <__mdiff+0x150> -80008fc4: 00160613 addi a2,a2,1 -80008fc8: 00261593 slli a1,a2,0x2 -80008fcc: 00b40433 add s0,s0,a1 -80008fd0: 00b282b3 add t0,t0,a1 -80008fd4: 05d47e63 bgeu s0,t4,80009030 <__mdiff+0x1b4> -80008fd8: 000108b7 lui a7,0x10 -80008fdc: 00028813 mv a6,t0 -80008fe0: 00040593 mv a1,s0 -80008fe4: fff88893 addi a7,a7,-1 # ffff <_start-0x7fff0001> -80008fe8: 0005a703 lw a4,0(a1) -80008fec: 00480813 addi a6,a6,4 -80008ff0: 00458593 addi a1,a1,4 -80008ff4: 01177633 and a2,a4,a7 -80008ff8: 00f60633 add a2,a2,a5 -80008ffc: 41065693 srai a3,a2,0x10 -80009000: 01075793 srli a5,a4,0x10 -80009004: 00d787b3 add a5,a5,a3 -80009008: 01079693 slli a3,a5,0x10 -8000900c: 01167633 and a2,a2,a7 -80009010: 00c6e6b3 or a3,a3,a2 -80009014: fed82e23 sw a3,-4(a6) -80009018: 4107d793 srai a5,a5,0x10 -8000901c: fdd5e6e3 bltu a1,t4,80008fe8 <__mdiff+0x16c> -80009020: fffe8713 addi a4,t4,-1 -80009024: 40870733 sub a4,a4,s0 -80009028: ffc77713 andi a4,a4,-4 -8000902c: 00e28733 add a4,t0,a4 -80009030: 00069a63 bnez a3,80009044 <__mdiff+0x1c8> -80009034: ffc72783 lw a5,-4(a4) -80009038: fffe0e13 addi t3,t3,-1 -8000903c: ffc70713 addi a4,a4,-4 -80009040: fe078ae3 beqz a5,80009034 <__mdiff+0x1b8> -80009044: 01c12083 lw ra,28(sp) -80009048: 01812403 lw s0,24(sp) -8000904c: 01c52823 sw t3,16(a0) -80009050: 01412483 lw s1,20(sp) -80009054: 01012903 lw s2,16(sp) -80009058: 00c12983 lw s3,12(sp) -8000905c: 00812a03 lw s4,8(sp) -80009060: 02010113 addi sp,sp,32 -80009064: 00008067 ret -80009068: 00000593 li a1,0 -8000906c: c8cff0ef jal ra,800084f8 <_Balloc> -80009070: 01c12083 lw ra,28(sp) -80009074: 01812403 lw s0,24(sp) -80009078: 00100793 li a5,1 -8000907c: 00f52823 sw a5,16(a0) -80009080: 00052a23 sw zero,20(a0) -80009084: 01412483 lw s1,20(sp) -80009088: 01012903 lw s2,16(sp) -8000908c: 00c12983 lw s3,12(sp) -80009090: 00812a03 lw s4,8(sp) -80009094: 02010113 addi sp,sp,32 -80009098: 00008067 ret +80008db8 <__mdiff>: +80008db8: 0105a783 lw a5,16(a1) +80008dbc: 01062703 lw a4,16(a2) +80008dc0: fe010113 addi sp,sp,-32 +80008dc4: 00812c23 sw s0,24(sp) +80008dc8: 00912a23 sw s1,20(sp) +80008dcc: 01212823 sw s2,16(sp) +80008dd0: 01312623 sw s3,12(sp) +80008dd4: 01412423 sw s4,8(sp) +80008dd8: 00112e23 sw ra,28(sp) +80008ddc: 00058913 mv s2,a1 +80008de0: 00060993 mv s3,a2 +80008de4: 40e78a33 sub s4,a5,a4 +80008de8: 01458413 addi s0,a1,20 +80008dec: 01460493 addi s1,a2,20 +80008df0: 04e79863 bne a5,a4,80008e40 <__mdiff+0x88> +80008df4: 00271713 slli a4,a4,0x2 +80008df8: 00e407b3 add a5,s0,a4 +80008dfc: 00e48733 add a4,s1,a4 +80008e00: 0080006f j 80008e08 <__mdiff+0x50> +80008e04: 1af47063 bgeu s0,a5,80008fa4 <__mdiff+0x1ec> +80008e08: ffc7a803 lw a6,-4(a5) +80008e0c: ffc72683 lw a3,-4(a4) +80008e10: ffc78793 addi a5,a5,-4 +80008e14: ffc70713 addi a4,a4,-4 +80008e18: fed806e3 beq a6,a3,80008e04 <__mdiff+0x4c> +80008e1c: 02d87663 bgeu a6,a3,80008e48 <__mdiff+0x90> +80008e20: 00040713 mv a4,s0 +80008e24: 00090793 mv a5,s2 +80008e28: 00048413 mv s0,s1 +80008e2c: 00098913 mv s2,s3 +80008e30: 00070493 mv s1,a4 +80008e34: 00078993 mv s3,a5 +80008e38: 00100a13 li s4,1 +80008e3c: 00c0006f j 80008e48 <__mdiff+0x90> +80008e40: fe0a40e3 bltz s4,80008e20 <__mdiff+0x68> +80008e44: 00000a13 li s4,0 +80008e48: 00492583 lw a1,4(s2) +80008e4c: de8ff0ef jal ra,80008434 <_Balloc> +80008e50: 01092e03 lw t3,16(s2) +80008e54: 0109af83 lw t6,16(s3) +80008e58: 01450293 addi t0,a0,20 +80008e5c: 002e1e93 slli t4,t3,0x2 +80008e60: 002f9f93 slli t6,t6,0x2 +80008e64: 000108b7 lui a7,0x10 +80008e68: 01452623 sw s4,12(a0) +80008e6c: 01d40eb3 add t4,s0,t4 +80008e70: 01f48fb3 add t6,s1,t6 +80008e74: 00028f13 mv t5,t0 +80008e78: 00048813 mv a6,s1 +80008e7c: 00040313 mv t1,s0 +80008e80: 00000793 li a5,0 +80008e84: fff88893 addi a7,a7,-1 # ffff <_start-0x7fff0001> +80008e88: 00032703 lw a4,0(t1) +80008e8c: 00082583 lw a1,0(a6) +80008e90: 004f0f13 addi t5,t5,4 +80008e94: 011776b3 and a3,a4,a7 +80008e98: 00f686b3 add a3,a3,a5 +80008e9c: 0115f7b3 and a5,a1,a7 +80008ea0: 40f686b3 sub a3,a3,a5 +80008ea4: 0105d593 srli a1,a1,0x10 +80008ea8: 01075793 srli a5,a4,0x10 +80008eac: 40b787b3 sub a5,a5,a1 +80008eb0: 4106d713 srai a4,a3,0x10 +80008eb4: 00e787b3 add a5,a5,a4 +80008eb8: 01079713 slli a4,a5,0x10 +80008ebc: 0116f6b3 and a3,a3,a7 +80008ec0: 00d766b3 or a3,a4,a3 +80008ec4: 00480813 addi a6,a6,4 +80008ec8: fedf2e23 sw a3,-4(t5) +80008ecc: 00430313 addi t1,t1,4 +80008ed0: 4107d793 srai a5,a5,0x10 +80008ed4: fbf86ae3 bltu a6,t6,80008e88 <__mdiff+0xd0> +80008ed8: fff4c613 not a2,s1 +80008edc: 00cf8633 add a2,t6,a2 +80008ee0: 00148493 addi s1,s1,1 +80008ee4: 00265613 srli a2,a2,0x2 +80008ee8: 00000713 li a4,0 +80008eec: 009fe463 bltu t6,s1,80008ef4 <__mdiff+0x13c> +80008ef0: 00261713 slli a4,a2,0x2 +80008ef4: 00e28733 add a4,t0,a4 +80008ef8: 00400593 li a1,4 +80008efc: 009fe663 bltu t6,s1,80008f08 <__mdiff+0x150> +80008f00: 00160613 addi a2,a2,1 +80008f04: 00261593 slli a1,a2,0x2 +80008f08: 00b40433 add s0,s0,a1 +80008f0c: 00b282b3 add t0,t0,a1 +80008f10: 05d47e63 bgeu s0,t4,80008f6c <__mdiff+0x1b4> +80008f14: 000108b7 lui a7,0x10 +80008f18: 00028813 mv a6,t0 +80008f1c: 00040593 mv a1,s0 +80008f20: fff88893 addi a7,a7,-1 # ffff <_start-0x7fff0001> +80008f24: 0005a703 lw a4,0(a1) +80008f28: 00480813 addi a6,a6,4 +80008f2c: 00458593 addi a1,a1,4 +80008f30: 01177633 and a2,a4,a7 +80008f34: 00f60633 add a2,a2,a5 +80008f38: 41065693 srai a3,a2,0x10 +80008f3c: 01075793 srli a5,a4,0x10 +80008f40: 00d787b3 add a5,a5,a3 +80008f44: 01079693 slli a3,a5,0x10 +80008f48: 01167633 and a2,a2,a7 +80008f4c: 00c6e6b3 or a3,a3,a2 +80008f50: fed82e23 sw a3,-4(a6) +80008f54: 4107d793 srai a5,a5,0x10 +80008f58: fdd5e6e3 bltu a1,t4,80008f24 <__mdiff+0x16c> +80008f5c: fffe8713 addi a4,t4,-1 +80008f60: 40870733 sub a4,a4,s0 +80008f64: ffc77713 andi a4,a4,-4 +80008f68: 00e28733 add a4,t0,a4 +80008f6c: 00069a63 bnez a3,80008f80 <__mdiff+0x1c8> +80008f70: ffc72783 lw a5,-4(a4) +80008f74: fffe0e13 addi t3,t3,-1 +80008f78: ffc70713 addi a4,a4,-4 +80008f7c: fe078ae3 beqz a5,80008f70 <__mdiff+0x1b8> +80008f80: 01c12083 lw ra,28(sp) +80008f84: 01812403 lw s0,24(sp) +80008f88: 01c52823 sw t3,16(a0) +80008f8c: 01412483 lw s1,20(sp) +80008f90: 01012903 lw s2,16(sp) +80008f94: 00c12983 lw s3,12(sp) +80008f98: 00812a03 lw s4,8(sp) +80008f9c: 02010113 addi sp,sp,32 +80008fa0: 00008067 ret +80008fa4: 00000593 li a1,0 +80008fa8: c8cff0ef jal ra,80008434 <_Balloc> +80008fac: 01c12083 lw ra,28(sp) +80008fb0: 01812403 lw s0,24(sp) +80008fb4: 00100793 li a5,1 +80008fb8: 00f52823 sw a5,16(a0) +80008fbc: 00052a23 sw zero,20(a0) +80008fc0: 01412483 lw s1,20(sp) +80008fc4: 01012903 lw s2,16(sp) +80008fc8: 00c12983 lw s3,12(sp) +80008fcc: 00812a03 lw s4,8(sp) +80008fd0: 02010113 addi sp,sp,32 +80008fd4: 00008067 ret -8000909c <__ulp>: -8000909c: 7ff007b7 lui a5,0x7ff00 -800090a0: 00b7f5b3 and a1,a5,a1 -800090a4: fcc007b7 lui a5,0xfcc00 -800090a8: 00f585b3 add a1,a1,a5 -800090ac: 00b05863 blez a1,800090bc <__ulp+0x20> -800090b0: 00000793 li a5,0 -800090b4: 00078513 mv a0,a5 -800090b8: 00008067 ret -800090bc: 40b005b3 neg a1,a1 -800090c0: 4145d593 srai a1,a1,0x14 -800090c4: 01300793 li a5,19 -800090c8: 00b7c863 blt a5,a1,800090d8 <__ulp+0x3c> -800090cc: 000807b7 lui a5,0x80 -800090d0: 40b7d5b3 sra a1,a5,a1 -800090d4: fddff06f j 800090b0 <__ulp+0x14> -800090d8: fec58713 addi a4,a1,-20 -800090dc: 01e00693 li a3,30 -800090e0: 00000593 li a1,0 -800090e4: 00100793 li a5,1 -800090e8: fce6c6e3 blt a3,a4,800090b4 <__ulp+0x18> -800090ec: 800007b7 lui a5,0x80000 -800090f0: 00e7d7b3 srl a5,a5,a4 -800090f4: 00078513 mv a0,a5 -800090f8: 00008067 ret +80008fd8 <__ulp>: +80008fd8: 7ff007b7 lui a5,0x7ff00 +80008fdc: 00b7f5b3 and a1,a5,a1 +80008fe0: fcc007b7 lui a5,0xfcc00 +80008fe4: 00f585b3 add a1,a1,a5 +80008fe8: 00b05863 blez a1,80008ff8 <__ulp+0x20> +80008fec: 00000793 li a5,0 +80008ff0: 00078513 mv a0,a5 +80008ff4: 00008067 ret +80008ff8: 40b005b3 neg a1,a1 +80008ffc: 4145d593 srai a1,a1,0x14 +80009000: 01300793 li a5,19 +80009004: 00b7c863 blt a5,a1,80009014 <__ulp+0x3c> +80009008: 000807b7 lui a5,0x80 +8000900c: 40b7d5b3 sra a1,a5,a1 +80009010: fddff06f j 80008fec <__ulp+0x14> +80009014: fec58713 addi a4,a1,-20 +80009018: 01e00693 li a3,30 +8000901c: 00000593 li a1,0 +80009020: 00100793 li a5,1 +80009024: fce6c6e3 blt a3,a4,80008ff0 <__ulp+0x18> +80009028: 800007b7 lui a5,0x80000 +8000902c: 00e7d7b3 srl a5,a5,a4 +80009030: 00078513 mv a0,a5 +80009034: 00008067 ret -800090fc <__b2d>: -800090fc: fe010113 addi sp,sp,-32 -80009100: 00912a23 sw s1,20(sp) -80009104: 01052483 lw s1,16(a0) -80009108: 00812c23 sw s0,24(sp) -8000910c: 01450413 addi s0,a0,20 -80009110: 00249493 slli s1,s1,0x2 -80009114: 009404b3 add s1,s0,s1 -80009118: 01212823 sw s2,16(sp) -8000911c: ffc4a903 lw s2,-4(s1) -80009120: 01312623 sw s3,12(sp) -80009124: 01412423 sw s4,8(sp) -80009128: 00090513 mv a0,s2 -8000912c: 00058993 mv s3,a1 -80009130: 00112e23 sw ra,28(sp) -80009134: eb8ff0ef jal ra,800087ec <__hi0bits> -80009138: 02000713 li a4,32 -8000913c: 40a707b3 sub a5,a4,a0 -80009140: 00f9a023 sw a5,0(s3) -80009144: 00a00793 li a5,10 -80009148: ffc48a13 addi s4,s1,-4 -8000914c: 08a7d063 bge a5,a0,800091cc <__b2d+0xd0> -80009150: ff550513 addi a0,a0,-11 -80009154: 05447063 bgeu s0,s4,80009194 <__b2d+0x98> -80009158: ff84a783 lw a5,-8(s1) -8000915c: 04050063 beqz a0,8000919c <__b2d+0xa0> -80009160: 40a706b3 sub a3,a4,a0 -80009164: 00d7d733 srl a4,a5,a3 -80009168: 00a91933 sll s2,s2,a0 -8000916c: 00e96933 or s2,s2,a4 -80009170: ff848613 addi a2,s1,-8 -80009174: 3ff00737 lui a4,0x3ff00 -80009178: 00e96733 or a4,s2,a4 -8000917c: 00a797b3 sll a5,a5,a0 -80009180: 02c47263 bgeu s0,a2,800091a4 <__b2d+0xa8> -80009184: ff44a603 lw a2,-12(s1) -80009188: 00d656b3 srl a3,a2,a3 -8000918c: 00d7e7b3 or a5,a5,a3 -80009190: 0140006f j 800091a4 <__b2d+0xa8> -80009194: 00000793 li a5,0 -80009198: 06051463 bnez a0,80009200 <__b2d+0x104> -8000919c: 3ff00737 lui a4,0x3ff00 -800091a0: 00e96733 or a4,s2,a4 -800091a4: 01c12083 lw ra,28(sp) -800091a8: 01812403 lw s0,24(sp) -800091ac: 01412483 lw s1,20(sp) -800091b0: 01012903 lw s2,16(sp) -800091b4: 00c12983 lw s3,12(sp) -800091b8: 00812a03 lw s4,8(sp) -800091bc: 00078513 mv a0,a5 -800091c0: 00070593 mv a1,a4 -800091c4: 02010113 addi sp,sp,32 -800091c8: 00008067 ret -800091cc: 00b00693 li a3,11 -800091d0: 40a686b3 sub a3,a3,a0 -800091d4: 3ff007b7 lui a5,0x3ff00 -800091d8: 00d95733 srl a4,s2,a3 -800091dc: 00f76733 or a4,a4,a5 -800091e0: 00000793 li a5,0 -800091e4: 01447663 bgeu s0,s4,800091f0 <__b2d+0xf4> -800091e8: ff84a783 lw a5,-8(s1) -800091ec: 00d7d7b3 srl a5,a5,a3 -800091f0: 01550513 addi a0,a0,21 -800091f4: 00a91533 sll a0,s2,a0 -800091f8: 00f567b3 or a5,a0,a5 -800091fc: fa9ff06f j 800091a4 <__b2d+0xa8> -80009200: 00a91533 sll a0,s2,a0 -80009204: 3ff00737 lui a4,0x3ff00 -80009208: 00e56733 or a4,a0,a4 -8000920c: 00000793 li a5,0 -80009210: f95ff06f j 800091a4 <__b2d+0xa8> +80009038 <__b2d>: +80009038: fe010113 addi sp,sp,-32 +8000903c: 00912a23 sw s1,20(sp) +80009040: 01052483 lw s1,16(a0) +80009044: 00812c23 sw s0,24(sp) +80009048: 01450413 addi s0,a0,20 +8000904c: 00249493 slli s1,s1,0x2 +80009050: 009404b3 add s1,s0,s1 +80009054: 01212823 sw s2,16(sp) +80009058: ffc4a903 lw s2,-4(s1) +8000905c: 01312623 sw s3,12(sp) +80009060: 01412423 sw s4,8(sp) +80009064: 00090513 mv a0,s2 +80009068: 00058993 mv s3,a1 +8000906c: 00112e23 sw ra,28(sp) +80009070: eb8ff0ef jal ra,80008728 <__hi0bits> +80009074: 02000713 li a4,32 +80009078: 40a707b3 sub a5,a4,a0 +8000907c: 00f9a023 sw a5,0(s3) +80009080: 00a00793 li a5,10 +80009084: ffc48a13 addi s4,s1,-4 +80009088: 08a7d063 bge a5,a0,80009108 <__b2d+0xd0> +8000908c: ff550513 addi a0,a0,-11 +80009090: 05447063 bgeu s0,s4,800090d0 <__b2d+0x98> +80009094: ff84a783 lw a5,-8(s1) +80009098: 04050063 beqz a0,800090d8 <__b2d+0xa0> +8000909c: 40a706b3 sub a3,a4,a0 +800090a0: 00d7d733 srl a4,a5,a3 +800090a4: 00a91933 sll s2,s2,a0 +800090a8: 00e96933 or s2,s2,a4 +800090ac: ff848613 addi a2,s1,-8 +800090b0: 3ff00737 lui a4,0x3ff00 +800090b4: 00e96733 or a4,s2,a4 +800090b8: 00a797b3 sll a5,a5,a0 +800090bc: 02c47263 bgeu s0,a2,800090e0 <__b2d+0xa8> +800090c0: ff44a603 lw a2,-12(s1) +800090c4: 00d656b3 srl a3,a2,a3 +800090c8: 00d7e7b3 or a5,a5,a3 +800090cc: 0140006f j 800090e0 <__b2d+0xa8> +800090d0: 00000793 li a5,0 +800090d4: 06051463 bnez a0,8000913c <__b2d+0x104> +800090d8: 3ff00737 lui a4,0x3ff00 +800090dc: 00e96733 or a4,s2,a4 +800090e0: 01c12083 lw ra,28(sp) +800090e4: 01812403 lw s0,24(sp) +800090e8: 01412483 lw s1,20(sp) +800090ec: 01012903 lw s2,16(sp) +800090f0: 00c12983 lw s3,12(sp) +800090f4: 00812a03 lw s4,8(sp) +800090f8: 00078513 mv a0,a5 +800090fc: 00070593 mv a1,a4 +80009100: 02010113 addi sp,sp,32 +80009104: 00008067 ret +80009108: 00b00693 li a3,11 +8000910c: 40a686b3 sub a3,a3,a0 +80009110: 3ff007b7 lui a5,0x3ff00 +80009114: 00d95733 srl a4,s2,a3 +80009118: 00f76733 or a4,a4,a5 +8000911c: 00000793 li a5,0 +80009120: 01447663 bgeu s0,s4,8000912c <__b2d+0xf4> +80009124: ff84a783 lw a5,-8(s1) +80009128: 00d7d7b3 srl a5,a5,a3 +8000912c: 01550513 addi a0,a0,21 +80009130: 00a91533 sll a0,s2,a0 +80009134: 00f567b3 or a5,a0,a5 +80009138: fa9ff06f j 800090e0 <__b2d+0xa8> +8000913c: 00a91533 sll a0,s2,a0 +80009140: 3ff00737 lui a4,0x3ff00 +80009144: 00e56733 or a4,a0,a4 +80009148: 00000793 li a5,0 +8000914c: f95ff06f j 800090e0 <__b2d+0xa8> -80009214 <__d2b>: -80009214: fd010113 addi sp,sp,-48 -80009218: 01512a23 sw s5,20(sp) -8000921c: 00058a93 mv s5,a1 -80009220: 00100593 li a1,1 -80009224: 02812423 sw s0,40(sp) -80009228: 02912223 sw s1,36(sp) -8000922c: 03212023 sw s2,32(sp) -80009230: 00060493 mv s1,a2 -80009234: 01312e23 sw s3,28(sp) -80009238: 01412c23 sw s4,24(sp) -8000923c: 00068993 mv s3,a3 -80009240: 00070913 mv s2,a4 -80009244: 02112623 sw ra,44(sp) -80009248: ab0ff0ef jal ra,800084f8 <_Balloc> -8000924c: 0144d713 srli a4,s1,0x14 -80009250: 00100637 lui a2,0x100 -80009254: fff60793 addi a5,a2,-1 # fffff <_start-0x7ff00001> -80009258: 01571693 slli a3,a4,0x15 -8000925c: 00050413 mv s0,a0 -80009260: 0097f7b3 and a5,a5,s1 -80009264: 7ff77a13 andi s4,a4,2047 -80009268: 00068463 beqz a3,80009270 <__d2b+0x5c> -8000926c: 00c7e7b3 or a5,a5,a2 -80009270: 00f12623 sw a5,12(sp) -80009274: 060a8c63 beqz s5,800092ec <__d2b+0xd8> -80009278: 00810513 addi a0,sp,8 -8000927c: 01512423 sw s5,8(sp) -80009280: de0ff0ef jal ra,80008860 <__lo0bits> -80009284: 00c12703 lw a4,12(sp) -80009288: 00050793 mv a5,a0 -8000928c: 0a051663 bnez a0,80009338 <__d2b+0x124> -80009290: 00812683 lw a3,8(sp) -80009294: 00d42a23 sw a3,20(s0) -80009298: 00e034b3 snez s1,a4 -8000929c: 00148493 addi s1,s1,1 -800092a0: 00e42c23 sw a4,24(s0) -800092a4: 00942823 sw s1,16(s0) -800092a8: 060a0463 beqz s4,80009310 <__d2b+0xfc> -800092ac: bcda0a13 addi s4,s4,-1075 -800092b0: 00fa0a33 add s4,s4,a5 -800092b4: 03500513 li a0,53 -800092b8: 0149a023 sw s4,0(s3) -800092bc: 40f507b3 sub a5,a0,a5 -800092c0: 00f92023 sw a5,0(s2) -800092c4: 02c12083 lw ra,44(sp) -800092c8: 00040513 mv a0,s0 -800092cc: 02812403 lw s0,40(sp) -800092d0: 02412483 lw s1,36(sp) -800092d4: 02012903 lw s2,32(sp) -800092d8: 01c12983 lw s3,28(sp) -800092dc: 01812a03 lw s4,24(sp) -800092e0: 01412a83 lw s5,20(sp) -800092e4: 03010113 addi sp,sp,48 -800092e8: 00008067 ret -800092ec: 00c10513 addi a0,sp,12 -800092f0: d70ff0ef jal ra,80008860 <__lo0bits> -800092f4: 00100793 li a5,1 -800092f8: 00f42823 sw a5,16(s0) -800092fc: 00c12783 lw a5,12(sp) -80009300: 00100493 li s1,1 -80009304: 00f42a23 sw a5,20(s0) -80009308: 02050793 addi a5,a0,32 -8000930c: fa0a10e3 bnez s4,800092ac <__d2b+0x98> -80009310: 00249713 slli a4,s1,0x2 -80009314: 00e40733 add a4,s0,a4 -80009318: 01072503 lw a0,16(a4) # 3ff00010 <_start-0x400ffff0> -8000931c: bce78793 addi a5,a5,-1074 # 3feffbce <_start-0x40100432> -80009320: 00f9a023 sw a5,0(s3) -80009324: cc8ff0ef jal ra,800087ec <__hi0bits> -80009328: 00549493 slli s1,s1,0x5 -8000932c: 40a484b3 sub s1,s1,a0 -80009330: 00992023 sw s1,0(s2) -80009334: f91ff06f j 800092c4 <__d2b+0xb0> -80009338: 00812603 lw a2,8(sp) -8000933c: 02000693 li a3,32 -80009340: 40a686b3 sub a3,a3,a0 -80009344: 00d716b3 sll a3,a4,a3 -80009348: 00c6e6b3 or a3,a3,a2 -8000934c: 00a75733 srl a4,a4,a0 -80009350: 00d42a23 sw a3,20(s0) -80009354: 00e12623 sw a4,12(sp) -80009358: f41ff06f j 80009298 <__d2b+0x84> +80009150 <__d2b>: +80009150: fd010113 addi sp,sp,-48 +80009154: 01512a23 sw s5,20(sp) +80009158: 00058a93 mv s5,a1 +8000915c: 00100593 li a1,1 +80009160: 02812423 sw s0,40(sp) +80009164: 02912223 sw s1,36(sp) +80009168: 03212023 sw s2,32(sp) +8000916c: 00060493 mv s1,a2 +80009170: 01312e23 sw s3,28(sp) +80009174: 01412c23 sw s4,24(sp) +80009178: 00068993 mv s3,a3 +8000917c: 00070913 mv s2,a4 +80009180: 02112623 sw ra,44(sp) +80009184: ab0ff0ef jal ra,80008434 <_Balloc> +80009188: 0144d713 srli a4,s1,0x14 +8000918c: 00100637 lui a2,0x100 +80009190: fff60793 addi a5,a2,-1 # fffff <_start-0x7ff00001> +80009194: 01571693 slli a3,a4,0x15 +80009198: 00050413 mv s0,a0 +8000919c: 0097f7b3 and a5,a5,s1 +800091a0: 7ff77a13 andi s4,a4,2047 +800091a4: 00068463 beqz a3,800091ac <__d2b+0x5c> +800091a8: 00c7e7b3 or a5,a5,a2 +800091ac: 00f12623 sw a5,12(sp) +800091b0: 060a8c63 beqz s5,80009228 <__d2b+0xd8> +800091b4: 00810513 addi a0,sp,8 +800091b8: 01512423 sw s5,8(sp) +800091bc: de0ff0ef jal ra,8000879c <__lo0bits> +800091c0: 00c12703 lw a4,12(sp) +800091c4: 00050793 mv a5,a0 +800091c8: 0a051663 bnez a0,80009274 <__d2b+0x124> +800091cc: 00812683 lw a3,8(sp) +800091d0: 00d42a23 sw a3,20(s0) +800091d4: 00e034b3 snez s1,a4 +800091d8: 00148493 addi s1,s1,1 +800091dc: 00e42c23 sw a4,24(s0) +800091e0: 00942823 sw s1,16(s0) +800091e4: 060a0463 beqz s4,8000924c <__d2b+0xfc> +800091e8: bcda0a13 addi s4,s4,-1075 +800091ec: 00fa0a33 add s4,s4,a5 +800091f0: 03500513 li a0,53 +800091f4: 0149a023 sw s4,0(s3) +800091f8: 40f507b3 sub a5,a0,a5 +800091fc: 00f92023 sw a5,0(s2) +80009200: 02c12083 lw ra,44(sp) +80009204: 00040513 mv a0,s0 +80009208: 02812403 lw s0,40(sp) +8000920c: 02412483 lw s1,36(sp) +80009210: 02012903 lw s2,32(sp) +80009214: 01c12983 lw s3,28(sp) +80009218: 01812a03 lw s4,24(sp) +8000921c: 01412a83 lw s5,20(sp) +80009220: 03010113 addi sp,sp,48 +80009224: 00008067 ret +80009228: 00c10513 addi a0,sp,12 +8000922c: d70ff0ef jal ra,8000879c <__lo0bits> +80009230: 00100793 li a5,1 +80009234: 00f42823 sw a5,16(s0) +80009238: 00c12783 lw a5,12(sp) +8000923c: 00100493 li s1,1 +80009240: 00f42a23 sw a5,20(s0) +80009244: 02050793 addi a5,a0,32 +80009248: fa0a10e3 bnez s4,800091e8 <__d2b+0x98> +8000924c: 00249713 slli a4,s1,0x2 +80009250: 00e40733 add a4,s0,a4 +80009254: 01072503 lw a0,16(a4) # 3ff00010 <_start-0x400ffff0> +80009258: bce78793 addi a5,a5,-1074 # 3feffbce <_start-0x40100432> +8000925c: 00f9a023 sw a5,0(s3) +80009260: cc8ff0ef jal ra,80008728 <__hi0bits> +80009264: 00549493 slli s1,s1,0x5 +80009268: 40a484b3 sub s1,s1,a0 +8000926c: 00992023 sw s1,0(s2) +80009270: f91ff06f j 80009200 <__d2b+0xb0> +80009274: 00812603 lw a2,8(sp) +80009278: 02000693 li a3,32 +8000927c: 40a686b3 sub a3,a3,a0 +80009280: 00d716b3 sll a3,a4,a3 +80009284: 00c6e6b3 or a3,a3,a2 +80009288: 00a75733 srl a4,a4,a0 +8000928c: 00d42a23 sw a3,20(s0) +80009290: 00e12623 sw a4,12(sp) +80009294: f41ff06f j 800091d4 <__d2b+0x84> -8000935c <__ratio>: -8000935c: fd010113 addi sp,sp,-48 -80009360: 03212023 sw s2,32(sp) -80009364: 00058913 mv s2,a1 -80009368: 00810593 addi a1,sp,8 -8000936c: 02112623 sw ra,44(sp) -80009370: 02812423 sw s0,40(sp) -80009374: 02912223 sw s1,36(sp) -80009378: 01312e23 sw s3,28(sp) -8000937c: 00050993 mv s3,a0 -80009380: d7dff0ef jal ra,800090fc <__b2d> -80009384: 00050493 mv s1,a0 -80009388: 00058413 mv s0,a1 -8000938c: 00090513 mv a0,s2 -80009390: 00c10593 addi a1,sp,12 -80009394: d69ff0ef jal ra,800090fc <__b2d> -80009398: 01092783 lw a5,16(s2) -8000939c: 0109a703 lw a4,16(s3) -800093a0: 00c12683 lw a3,12(sp) -800093a4: 40f70733 sub a4,a4,a5 -800093a8: 00812783 lw a5,8(sp) -800093ac: 00571713 slli a4,a4,0x5 -800093b0: 40d787b3 sub a5,a5,a3 -800093b4: 00f707b3 add a5,a4,a5 -800093b8: 00050693 mv a3,a0 -800093bc: 02f05e63 blez a5,800093f8 <__ratio+0x9c> -800093c0: 01479793 slli a5,a5,0x14 -800093c4: 00878433 add s0,a5,s0 -800093c8: 00068613 mv a2,a3 -800093cc: 00048513 mv a0,s1 -800093d0: 00058693 mv a3,a1 -800093d4: 00040593 mv a1,s0 -800093d8: 131070ef jal ra,80010d08 <__divdf3> -800093dc: 02c12083 lw ra,44(sp) -800093e0: 02812403 lw s0,40(sp) -800093e4: 02412483 lw s1,36(sp) -800093e8: 02012903 lw s2,32(sp) -800093ec: 01c12983 lw s3,28(sp) -800093f0: 03010113 addi sp,sp,48 -800093f4: 00008067 ret -800093f8: 01479713 slli a4,a5,0x14 -800093fc: 40e585b3 sub a1,a1,a4 -80009400: fc9ff06f j 800093c8 <__ratio+0x6c> +80009298 <__ratio>: +80009298: fd010113 addi sp,sp,-48 +8000929c: 03212023 sw s2,32(sp) +800092a0: 00058913 mv s2,a1 +800092a4: 00810593 addi a1,sp,8 +800092a8: 02112623 sw ra,44(sp) +800092ac: 02812423 sw s0,40(sp) +800092b0: 02912223 sw s1,36(sp) +800092b4: 01312e23 sw s3,28(sp) +800092b8: 00050993 mv s3,a0 +800092bc: d7dff0ef jal ra,80009038 <__b2d> +800092c0: 00050493 mv s1,a0 +800092c4: 00058413 mv s0,a1 +800092c8: 00090513 mv a0,s2 +800092cc: 00c10593 addi a1,sp,12 +800092d0: d69ff0ef jal ra,80009038 <__b2d> +800092d4: 01092783 lw a5,16(s2) +800092d8: 0109a703 lw a4,16(s3) +800092dc: 00c12683 lw a3,12(sp) +800092e0: 40f70733 sub a4,a4,a5 +800092e4: 00812783 lw a5,8(sp) +800092e8: 00571713 slli a4,a4,0x5 +800092ec: 40d787b3 sub a5,a5,a3 +800092f0: 00f707b3 add a5,a4,a5 +800092f4: 00050693 mv a3,a0 +800092f8: 02f05e63 blez a5,80009334 <__ratio+0x9c> +800092fc: 01479793 slli a5,a5,0x14 +80009300: 00878433 add s0,a5,s0 +80009304: 00068613 mv a2,a3 +80009308: 00048513 mv a0,s1 +8000930c: 00058693 mv a3,a1 +80009310: 00040593 mv a1,s0 +80009314: 131070ef jal ra,80010c44 <__divdf3> +80009318: 02c12083 lw ra,44(sp) +8000931c: 02812403 lw s0,40(sp) +80009320: 02412483 lw s1,36(sp) +80009324: 02012903 lw s2,32(sp) +80009328: 01c12983 lw s3,28(sp) +8000932c: 03010113 addi sp,sp,48 +80009330: 00008067 ret +80009334: 01479713 slli a4,a5,0x14 +80009338: 40e585b3 sub a1,a1,a4 +8000933c: fc9ff06f j 80009304 <__ratio+0x6c> -80009404 <_mprec_log10>: -80009404: ff010113 addi sp,sp,-16 -80009408: 01212023 sw s2,0(sp) -8000940c: 00112623 sw ra,12(sp) -80009410: 00812423 sw s0,8(sp) -80009414: 00912223 sw s1,4(sp) -80009418: 01700793 li a5,23 -8000941c: 00050913 mv s2,a0 -80009420: 04a7d663 bge a5,a0,8000946c <_mprec_log10+0x68> -80009424: 3381a783 lw a5,824(gp) # 80016b40 <__SDATA_BEGIN__> -80009428: 33c1a583 lw a1,828(gp) # 80016b44 <__SDATA_BEGIN__+0x4> -8000942c: 3401a403 lw s0,832(gp) # 80016b48 <__SDATA_BEGIN__+0x8> -80009430: 3441a483 lw s1,836(gp) # 80016b4c <__SDATA_BEGIN__+0xc> -80009434: 00078513 mv a0,a5 -80009438: 00040613 mv a2,s0 -8000943c: 00048693 mv a3,s1 -80009440: 7a9070ef jal ra,800113e8 <__muldf3> -80009444: fff90913 addi s2,s2,-1 -80009448: 00050793 mv a5,a0 -8000944c: fe0914e3 bnez s2,80009434 <_mprec_log10+0x30> -80009450: 00c12083 lw ra,12(sp) -80009454: 00812403 lw s0,8(sp) -80009458: 00412483 lw s1,4(sp) -8000945c: 00012903 lw s2,0(sp) -80009460: 00078513 mv a0,a5 -80009464: 01010113 addi sp,sp,16 -80009468: 00008067 ret -8000946c: 800157b7 lui a5,0x80015 -80009470: 00351913 slli s2,a0,0x3 -80009474: 0b878793 addi a5,a5,184 # 800150b8 <__BSS_END__+0xffffe47c> -80009478: 01278933 add s2,a5,s2 -8000947c: 01092783 lw a5,16(s2) -80009480: 00c12083 lw ra,12(sp) -80009484: 00812403 lw s0,8(sp) -80009488: 01492583 lw a1,20(s2) -8000948c: 00412483 lw s1,4(sp) -80009490: 00012903 lw s2,0(sp) -80009494: 00078513 mv a0,a5 -80009498: 01010113 addi sp,sp,16 +80009340 <_mprec_log10>: +80009340: ff010113 addi sp,sp,-16 +80009344: 01212023 sw s2,0(sp) +80009348: 00112623 sw ra,12(sp) +8000934c: 00812423 sw s0,8(sp) +80009350: 00912223 sw s1,4(sp) +80009354: 01700793 li a5,23 +80009358: 00050913 mv s2,a0 +8000935c: 04a7d663 bge a5,a0,800093a8 <_mprec_log10+0x68> +80009360: 3381a783 lw a5,824(gp) # 80016b40 <__SDATA_BEGIN__> +80009364: 33c1a583 lw a1,828(gp) # 80016b44 <__SDATA_BEGIN__+0x4> +80009368: 3401a403 lw s0,832(gp) # 80016b48 <__SDATA_BEGIN__+0x8> +8000936c: 3441a483 lw s1,836(gp) # 80016b4c <__SDATA_BEGIN__+0xc> +80009370: 00078513 mv a0,a5 +80009374: 00040613 mv a2,s0 +80009378: 00048693 mv a3,s1 +8000937c: 7a9070ef jal ra,80011324 <__muldf3> +80009380: fff90913 addi s2,s2,-1 +80009384: 00050793 mv a5,a0 +80009388: fe0914e3 bnez s2,80009370 <_mprec_log10+0x30> +8000938c: 00c12083 lw ra,12(sp) +80009390: 00812403 lw s0,8(sp) +80009394: 00412483 lw s1,4(sp) +80009398: 00012903 lw s2,0(sp) +8000939c: 00078513 mv a0,a5 +800093a0: 01010113 addi sp,sp,16 +800093a4: 00008067 ret +800093a8: 800157b7 lui a5,0x80015 +800093ac: 00351913 slli s2,a0,0x3 +800093b0: fe078793 addi a5,a5,-32 # 80014fe0 <__BSS_END__+0xffffe3a4> +800093b4: 01278933 add s2,a5,s2 +800093b8: 01092783 lw a5,16(s2) +800093bc: 00c12083 lw ra,12(sp) +800093c0: 00812403 lw s0,8(sp) +800093c4: 01492583 lw a1,20(s2) +800093c8: 00412483 lw s1,4(sp) +800093cc: 00012903 lw s2,0(sp) +800093d0: 00078513 mv a0,a5 +800093d4: 01010113 addi sp,sp,16 +800093d8: 00008067 ret + +800093dc <__copybits>: +800093dc: 01062683 lw a3,16(a2) +800093e0: fff58593 addi a1,a1,-1 +800093e4: 4055d593 srai a1,a1,0x5 +800093e8: 00158593 addi a1,a1,1 +800093ec: 01460793 addi a5,a2,20 +800093f0: 00269693 slli a3,a3,0x2 +800093f4: 00259593 slli a1,a1,0x2 +800093f8: 00d786b3 add a3,a5,a3 +800093fc: 00b505b3 add a1,a0,a1 +80009400: 02d7f863 bgeu a5,a3,80009430 <__copybits+0x54> +80009404: 00050713 mv a4,a0 +80009408: 0007a803 lw a6,0(a5) +8000940c: 00478793 addi a5,a5,4 +80009410: 00470713 addi a4,a4,4 +80009414: ff072e23 sw a6,-4(a4) +80009418: fed7e8e3 bltu a5,a3,80009408 <__copybits+0x2c> +8000941c: 40c687b3 sub a5,a3,a2 +80009420: feb78793 addi a5,a5,-21 +80009424: ffc7f793 andi a5,a5,-4 +80009428: 00478793 addi a5,a5,4 +8000942c: 00f50533 add a0,a0,a5 +80009430: 00b57863 bgeu a0,a1,80009440 <__copybits+0x64> +80009434: 00450513 addi a0,a0,4 +80009438: fe052e23 sw zero,-4(a0) +8000943c: feb56ce3 bltu a0,a1,80009434 <__copybits+0x58> +80009440: 00008067 ret + +80009444 <__any_on>: +80009444: 01052703 lw a4,16(a0) +80009448: 4055d613 srai a2,a1,0x5 +8000944c: 01450693 addi a3,a0,20 +80009450: 02c75263 bge a4,a2,80009474 <__any_on+0x30> +80009454: 00271793 slli a5,a4,0x2 +80009458: 00f687b3 add a5,a3,a5 +8000945c: 04f6f263 bgeu a3,a5,800094a0 <__any_on+0x5c> +80009460: ffc7a703 lw a4,-4(a5) +80009464: ffc78793 addi a5,a5,-4 +80009468: fe070ae3 beqz a4,8000945c <__any_on+0x18> +8000946c: 00100513 li a0,1 +80009470: 00008067 ret +80009474: 00261793 slli a5,a2,0x2 +80009478: 00f687b3 add a5,a3,a5 +8000947c: fee650e3 bge a2,a4,8000945c <__any_on+0x18> +80009480: 01f5f593 andi a1,a1,31 +80009484: fc058ce3 beqz a1,8000945c <__any_on+0x18> +80009488: 0007a603 lw a2,0(a5) +8000948c: 00100513 li a0,1 +80009490: 00b65733 srl a4,a2,a1 +80009494: 00b715b3 sll a1,a4,a1 +80009498: fcb602e3 beq a2,a1,8000945c <__any_on+0x18> 8000949c: 00008067 ret +800094a0: 00000513 li a0,0 +800094a4: 00008067 ret -800094a0 <__copybits>: -800094a0: 01062683 lw a3,16(a2) -800094a4: fff58593 addi a1,a1,-1 -800094a8: 4055d593 srai a1,a1,0x5 -800094ac: 00158593 addi a1,a1,1 -800094b0: 01460793 addi a5,a2,20 -800094b4: 00269693 slli a3,a3,0x2 -800094b8: 00259593 slli a1,a1,0x2 -800094bc: 00d786b3 add a3,a5,a3 -800094c0: 00b505b3 add a1,a0,a1 -800094c4: 02d7f863 bgeu a5,a3,800094f4 <__copybits+0x54> -800094c8: 00050713 mv a4,a0 -800094cc: 0007a803 lw a6,0(a5) -800094d0: 00478793 addi a5,a5,4 -800094d4: 00470713 addi a4,a4,4 -800094d8: ff072e23 sw a6,-4(a4) -800094dc: fed7e8e3 bltu a5,a3,800094cc <__copybits+0x2c> -800094e0: 40c687b3 sub a5,a3,a2 -800094e4: feb78793 addi a5,a5,-21 -800094e8: ffc7f793 andi a5,a5,-4 -800094ec: 00478793 addi a5,a5,4 -800094f0: 00f50533 add a0,a0,a5 -800094f4: 00b57863 bgeu a0,a1,80009504 <__copybits+0x64> -800094f8: 00450513 addi a0,a0,4 -800094fc: fe052e23 sw zero,-4(a0) -80009500: feb56ce3 bltu a0,a1,800094f8 <__copybits+0x58> -80009504: 00008067 ret +800094a8 : +800094a8: ff010113 addi sp,sp,-16 +800094ac: 00912223 sw s1,4(sp) +800094b0: 800004b7 lui s1,0x80000 +800094b4: 00812423 sw s0,8(sp) +800094b8: 00112623 sw ra,12(sp) +800094bc: fff4c493 not s1,s1 +800094c0: 00060413 mv s0,a2 +800094c4: 00062023 sw zero,0(a2) +800094c8: 00b4f6b3 and a3,s1,a1 +800094cc: 7ff00637 lui a2,0x7ff00 +800094d0: 00058793 mv a5,a1 +800094d4: 00050713 mv a4,a0 +800094d8: 04c6de63 bge a3,a2,80009534 +800094dc: 00a6e8b3 or a7,a3,a0 +800094e0: 04088a63 beqz a7,80009534 +800094e4: 00c5f633 and a2,a1,a2 +800094e8: 00058813 mv a6,a1 +800094ec: 00000893 li a7,0 +800094f0: 02061063 bnez a2,80009510 +800094f4: 34c1a683 lw a3,844(gp) # 80016b54 <__SDATA_BEGIN__+0x14> +800094f8: 3481a603 lw a2,840(gp) # 80016b50 <__SDATA_BEGIN__+0x10> +800094fc: 629070ef jal ra,80011324 <__muldf3> +80009500: 00050713 mv a4,a0 +80009504: 00058813 mv a6,a1 +80009508: 00b4f6b3 and a3,s1,a1 +8000950c: fca00893 li a7,-54 +80009510: 4146d693 srai a3,a3,0x14 +80009514: 801007b7 lui a5,0x80100 +80009518: fff78793 addi a5,a5,-1 # 800fffff <__BSS_END__+0xe93c3> +8000951c: c0268693 addi a3,a3,-1022 +80009520: 00f87833 and a6,a6,a5 +80009524: 011686b3 add a3,a3,a7 +80009528: 3fe007b7 lui a5,0x3fe00 +8000952c: 00f867b3 or a5,a6,a5 +80009530: 00d42023 sw a3,0(s0) +80009534: 00c12083 lw ra,12(sp) +80009538: 00812403 lw s0,8(sp) +8000953c: 00412483 lw s1,4(sp) +80009540: 00070513 mv a0,a4 +80009544: 00078593 mv a1,a5 +80009548: 01010113 addi sp,sp,16 +8000954c: 00008067 ret -80009508 <__any_on>: -80009508: 01052703 lw a4,16(a0) -8000950c: 4055d613 srai a2,a1,0x5 -80009510: 01450693 addi a3,a0,20 -80009514: 02c75263 bge a4,a2,80009538 <__any_on+0x30> -80009518: 00271793 slli a5,a4,0x2 -8000951c: 00f687b3 add a5,a3,a5 -80009520: 04f6f263 bgeu a3,a5,80009564 <__any_on+0x5c> -80009524: ffc7a703 lw a4,-4(a5) -80009528: ffc78793 addi a5,a5,-4 -8000952c: fe070ae3 beqz a4,80009520 <__any_on+0x18> -80009530: 00100513 li a0,1 -80009534: 00008067 ret -80009538: 00261793 slli a5,a2,0x2 -8000953c: 00f687b3 add a5,a3,a5 -80009540: fee650e3 bge a2,a4,80009520 <__any_on+0x18> -80009544: 01f5f593 andi a1,a1,31 -80009548: fc058ce3 beqz a1,80009520 <__any_on+0x18> -8000954c: 0007a603 lw a2,0(a5) -80009550: 00100513 li a0,1 -80009554: 00b65733 srl a4,a2,a1 -80009558: 00b715b3 sll a1,a4,a1 -8000955c: fcb602e3 beq a2,a1,80009520 <__any_on+0x18> -80009560: 00008067 ret -80009564: 00000513 li a0,0 -80009568: 00008067 ret +80009550 <_sbrk_r>: +80009550: ff010113 addi sp,sp,-16 +80009554: 00812423 sw s0,8(sp) +80009558: 00912223 sw s1,4(sp) +8000955c: 00050413 mv s0,a0 +80009560: 00058513 mv a0,a1 +80009564: 00112623 sw ra,12(sp) +80009568: 4201a823 sw zero,1072(gp) # 80016c38 +8000956c: fa9f60ef jal ra,80000514 <_sbrk> +80009570: fff00793 li a5,-1 +80009574: 00f50c63 beq a0,a5,8000958c <_sbrk_r+0x3c> +80009578: 00c12083 lw ra,12(sp) +8000957c: 00812403 lw s0,8(sp) +80009580: 00412483 lw s1,4(sp) +80009584: 01010113 addi sp,sp,16 +80009588: 00008067 ret +8000958c: 4301a783 lw a5,1072(gp) # 80016c38 +80009590: fe0784e3 beqz a5,80009578 <_sbrk_r+0x28> +80009594: 00c12083 lw ra,12(sp) +80009598: 00f42023 sw a5,0(s0) +8000959c: 00812403 lw s0,8(sp) +800095a0: 00412483 lw s1,4(sp) +800095a4: 01010113 addi sp,sp,16 +800095a8: 00008067 ret -8000956c : -8000956c: ff010113 addi sp,sp,-16 -80009570: 00912223 sw s1,4(sp) -80009574: 800004b7 lui s1,0x80000 -80009578: 00812423 sw s0,8(sp) -8000957c: 00112623 sw ra,12(sp) -80009580: fff4c493 not s1,s1 -80009584: 00060413 mv s0,a2 -80009588: 00062023 sw zero,0(a2) -8000958c: 00b4f6b3 and a3,s1,a1 -80009590: 7ff00637 lui a2,0x7ff00 -80009594: 00058793 mv a5,a1 -80009598: 00050713 mv a4,a0 -8000959c: 04c6de63 bge a3,a2,800095f8 -800095a0: 00a6e8b3 or a7,a3,a0 -800095a4: 04088a63 beqz a7,800095f8 -800095a8: 00c5f633 and a2,a1,a2 -800095ac: 00058813 mv a6,a1 -800095b0: 00000893 li a7,0 -800095b4: 02061063 bnez a2,800095d4 -800095b8: 34c1a683 lw a3,844(gp) # 80016b54 <__SDATA_BEGIN__+0x14> -800095bc: 3481a603 lw a2,840(gp) # 80016b50 <__SDATA_BEGIN__+0x10> -800095c0: 629070ef jal ra,800113e8 <__muldf3> -800095c4: 00050713 mv a4,a0 -800095c8: 00058813 mv a6,a1 -800095cc: 00b4f6b3 and a3,s1,a1 -800095d0: fca00893 li a7,-54 -800095d4: 4146d693 srai a3,a3,0x14 -800095d8: 801007b7 lui a5,0x80100 -800095dc: fff78793 addi a5,a5,-1 # 800fffff <__BSS_END__+0xe93c3> -800095e0: c0268693 addi a3,a3,-1022 -800095e4: 00f87833 and a6,a6,a5 -800095e8: 011686b3 add a3,a3,a7 -800095ec: 3fe007b7 lui a5,0x3fe00 -800095f0: 00f867b3 or a5,a6,a5 -800095f4: 00d42023 sw a3,0(s0) -800095f8: 00c12083 lw ra,12(sp) -800095fc: 00812403 lw s0,8(sp) -80009600: 00412483 lw s1,4(sp) -80009604: 00070513 mv a0,a4 -80009608: 00078593 mv a1,a5 -8000960c: 01010113 addi sp,sp,16 -80009610: 00008067 ret +800095ac <_sprintf_r>: +800095ac: f6010113 addi sp,sp,-160 +800095b0: 08c10e93 addi t4,sp,140 +800095b4: 08f12a23 sw a5,148(sp) +800095b8: 80000337 lui t1,0x80000 +800095bc: ffff07b7 lui a5,0xffff0 +800095c0: 00058e13 mv t3,a1 +800095c4: fff34313 not t1,t1 +800095c8: 08d12623 sw a3,140(sp) +800095cc: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd95cc> +800095d0: 00810593 addi a1,sp,8 +800095d4: 000e8693 mv a3,t4 +800095d8: 06112e23 sw ra,124(sp) +800095dc: 00f12a23 sw a5,20(sp) +800095e0: 08e12823 sw a4,144(sp) +800095e4: 09012c23 sw a6,152(sp) +800095e8: 09112e23 sw a7,156(sp) +800095ec: 01c12423 sw t3,8(sp) +800095f0: 01c12c23 sw t3,24(sp) +800095f4: 00612e23 sw t1,28(sp) +800095f8: 00612823 sw t1,16(sp) +800095fc: 01d12223 sw t4,4(sp) +80009600: 3d0000ef jal ra,800099d0 <_svfprintf_r> +80009604: 00812783 lw a5,8(sp) +80009608: 00078023 sb zero,0(a5) +8000960c: 07c12083 lw ra,124(sp) +80009610: 0a010113 addi sp,sp,160 +80009614: 00008067 ret -80009614 <_sbrk_r>: -80009614: ff010113 addi sp,sp,-16 -80009618: 00812423 sw s0,8(sp) -8000961c: 00912223 sw s1,4(sp) -80009620: 00050413 mv s0,a0 -80009624: 00058513 mv a0,a1 -80009628: 00112623 sw ra,12(sp) -8000962c: 4201a823 sw zero,1072(gp) # 80016c38 -80009630: eddf60ef jal ra,8000050c <_sbrk> -80009634: fff00793 li a5,-1 -80009638: 00f50c63 beq a0,a5,80009650 <_sbrk_r+0x3c> -8000963c: 00c12083 lw ra,12(sp) -80009640: 00812403 lw s0,8(sp) -80009644: 00412483 lw s1,4(sp) -80009648: 01010113 addi sp,sp,16 -8000964c: 00008067 ret -80009650: 4301a783 lw a5,1072(gp) # 80016c38 -80009654: fe0784e3 beqz a5,8000963c <_sbrk_r+0x28> -80009658: 00c12083 lw ra,12(sp) -8000965c: 00f42023 sw a5,0(s0) -80009660: 00812403 lw s0,8(sp) -80009664: 00412483 lw s1,4(sp) -80009668: 01010113 addi sp,sp,16 -8000966c: 00008067 ret +80009618 : +80009618: 00050e13 mv t3,a0 +8000961c: f6010113 addi sp,sp,-160 +80009620: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +80009624: 08810e93 addi t4,sp,136 +80009628: 08f12a23 sw a5,148(sp) +8000962c: 80000337 lui t1,0x80000 +80009630: ffff07b7 lui a5,0xffff0 +80009634: fff34313 not t1,t1 +80009638: 08c12423 sw a2,136(sp) +8000963c: 08d12623 sw a3,140(sp) +80009640: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd95cc> +80009644: 00058613 mv a2,a1 +80009648: 000e8693 mv a3,t4 +8000964c: 00810593 addi a1,sp,8 +80009650: 06112e23 sw ra,124(sp) +80009654: 00f12a23 sw a5,20(sp) +80009658: 08e12823 sw a4,144(sp) +8000965c: 09012c23 sw a6,152(sp) +80009660: 09112e23 sw a7,156(sp) +80009664: 01c12423 sw t3,8(sp) +80009668: 01c12c23 sw t3,24(sp) +8000966c: 00612e23 sw t1,28(sp) +80009670: 00612823 sw t1,16(sp) +80009674: 01d12223 sw t4,4(sp) +80009678: 358000ef jal ra,800099d0 <_svfprintf_r> +8000967c: 00812783 lw a5,8(sp) +80009680: 00078023 sb zero,0(a5) +80009684: 07c12083 lw ra,124(sp) +80009688: 0a010113 addi sp,sp,160 +8000968c: 00008067 ret -80009670 <_sprintf_r>: -80009670: f6010113 addi sp,sp,-160 -80009674: 08c10e93 addi t4,sp,140 -80009678: 08f12a23 sw a5,148(sp) -8000967c: 80000337 lui t1,0x80000 -80009680: ffff07b7 lui a5,0xffff0 -80009684: 00058e13 mv t3,a1 -80009688: fff34313 not t1,t1 -8000968c: 08d12623 sw a3,140(sp) -80009690: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd95cc> -80009694: 00810593 addi a1,sp,8 -80009698: 000e8693 mv a3,t4 -8000969c: 06112e23 sw ra,124(sp) -800096a0: 00f12a23 sw a5,20(sp) -800096a4: 08e12823 sw a4,144(sp) -800096a8: 09012c23 sw a6,152(sp) -800096ac: 09112e23 sw a7,156(sp) -800096b0: 01c12423 sw t3,8(sp) -800096b4: 01c12c23 sw t3,24(sp) -800096b8: 00612e23 sw t1,28(sp) -800096bc: 00612823 sw t1,16(sp) -800096c0: 01d12223 sw t4,4(sp) -800096c4: 3d0000ef jal ra,80009a94 <_svfprintf_r> -800096c8: 00812783 lw a5,8(sp) -800096cc: 00078023 sb zero,0(a5) -800096d0: 07c12083 lw ra,124(sp) -800096d4: 0a010113 addi sp,sp,160 -800096d8: 00008067 ret +80009690 <__sread>: +80009690: ff010113 addi sp,sp,-16 +80009694: 00812423 sw s0,8(sp) +80009698: 00058413 mv s0,a1 +8000969c: 00e59583 lh a1,14(a1) +800096a0: 00112623 sw ra,12(sp) +800096a4: 775040ef jal ra,8000e618 <_read_r> +800096a8: 02054063 bltz a0,800096c8 <__sread+0x38> +800096ac: 05042783 lw a5,80(s0) +800096b0: 00c12083 lw ra,12(sp) +800096b4: 00a787b3 add a5,a5,a0 +800096b8: 04f42823 sw a5,80(s0) +800096bc: 00812403 lw s0,8(sp) +800096c0: 01010113 addi sp,sp,16 +800096c4: 00008067 ret +800096c8: 00c45783 lhu a5,12(s0) +800096cc: fffff737 lui a4,0xfffff +800096d0: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> +800096d4: 00e7f7b3 and a5,a5,a4 +800096d8: 00c12083 lw ra,12(sp) +800096dc: 00f41623 sh a5,12(s0) +800096e0: 00812403 lw s0,8(sp) +800096e4: 01010113 addi sp,sp,16 +800096e8: 00008067 ret -800096dc : -800096dc: 00050e13 mv t3,a0 -800096e0: f6010113 addi sp,sp,-160 -800096e4: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -800096e8: 08810e93 addi t4,sp,136 -800096ec: 08f12a23 sw a5,148(sp) -800096f0: 80000337 lui t1,0x80000 -800096f4: ffff07b7 lui a5,0xffff0 -800096f8: fff34313 not t1,t1 -800096fc: 08c12423 sw a2,136(sp) -80009700: 08d12623 sw a3,140(sp) -80009704: 20878793 addi a5,a5,520 # ffff0208 <__BSS_END__+0x7ffd95cc> -80009708: 00058613 mv a2,a1 -8000970c: 000e8693 mv a3,t4 -80009710: 00810593 addi a1,sp,8 -80009714: 06112e23 sw ra,124(sp) -80009718: 00f12a23 sw a5,20(sp) -8000971c: 08e12823 sw a4,144(sp) -80009720: 09012c23 sw a6,152(sp) -80009724: 09112e23 sw a7,156(sp) -80009728: 01c12423 sw t3,8(sp) -8000972c: 01c12c23 sw t3,24(sp) -80009730: 00612e23 sw t1,28(sp) -80009734: 00612823 sw t1,16(sp) -80009738: 01d12223 sw t4,4(sp) -8000973c: 358000ef jal ra,80009a94 <_svfprintf_r> -80009740: 00812783 lw a5,8(sp) -80009744: 00078023 sb zero,0(a5) -80009748: 07c12083 lw ra,124(sp) -8000974c: 0a010113 addi sp,sp,160 -80009750: 00008067 ret +800096ec <__seofread>: +800096ec: 00000513 li a0,0 +800096f0: 00008067 ret -80009754 <__sread>: -80009754: ff010113 addi sp,sp,-16 -80009758: 00812423 sw s0,8(sp) -8000975c: 00058413 mv s0,a1 -80009760: 00e59583 lh a1,14(a1) -80009764: 00112623 sw ra,12(sp) -80009768: 775040ef jal ra,8000e6dc <_read_r> -8000976c: 02054063 bltz a0,8000978c <__sread+0x38> -80009770: 05042783 lw a5,80(s0) -80009774: 00c12083 lw ra,12(sp) -80009778: 00a787b3 add a5,a5,a0 -8000977c: 04f42823 sw a5,80(s0) -80009780: 00812403 lw s0,8(sp) -80009784: 01010113 addi sp,sp,16 -80009788: 00008067 ret -8000978c: 00c45783 lhu a5,12(s0) -80009790: fffff737 lui a4,0xfffff -80009794: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> -80009798: 00e7f7b3 and a5,a5,a4 -8000979c: 00c12083 lw ra,12(sp) -800097a0: 00f41623 sh a5,12(s0) -800097a4: 00812403 lw s0,8(sp) -800097a8: 01010113 addi sp,sp,16 -800097ac: 00008067 ret +800096f4 <__swrite>: +800096f4: 00c59783 lh a5,12(a1) +800096f8: fe010113 addi sp,sp,-32 +800096fc: 00812c23 sw s0,24(sp) +80009700: 00912a23 sw s1,20(sp) +80009704: 01212823 sw s2,16(sp) +80009708: 01312623 sw s3,12(sp) +8000970c: 00112e23 sw ra,28(sp) +80009710: 1007f713 andi a4,a5,256 +80009714: 00058413 mv s0,a1 +80009718: 00050493 mv s1,a0 +8000971c: 00e59583 lh a1,14(a1) +80009720: 00060913 mv s2,a2 +80009724: 00068993 mv s3,a3 +80009728: 02071e63 bnez a4,80009764 <__swrite+0x70> +8000972c: fffff737 lui a4,0xfffff +80009730: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> +80009734: 00e7f7b3 and a5,a5,a4 +80009738: 00f41623 sh a5,12(s0) +8000973c: 01812403 lw s0,24(sp) +80009740: 01c12083 lw ra,28(sp) +80009744: 00098693 mv a3,s3 +80009748: 00090613 mv a2,s2 +8000974c: 00c12983 lw s3,12(sp) +80009750: 01012903 lw s2,16(sp) +80009754: 00048513 mv a0,s1 +80009758: 01412483 lw s1,20(sp) +8000975c: 02010113 addi sp,sp,32 +80009760: 0a80406f j 8000d808 <_write_r> +80009764: 00200693 li a3,2 +80009768: 00000613 li a2,0 +8000976c: 399040ef jal ra,8000e304 <_lseek_r> +80009770: 00c41783 lh a5,12(s0) +80009774: 00e41583 lh a1,14(s0) +80009778: fb5ff06f j 8000972c <__swrite+0x38> -800097b0 <__seofread>: -800097b0: 00000513 li a0,0 -800097b4: 00008067 ret +8000977c <__sseek>: +8000977c: ff010113 addi sp,sp,-16 +80009780: 00812423 sw s0,8(sp) +80009784: 00058413 mv s0,a1 +80009788: 00e59583 lh a1,14(a1) +8000978c: 00112623 sw ra,12(sp) +80009790: 375040ef jal ra,8000e304 <_lseek_r> +80009794: fff00793 li a5,-1 +80009798: 02f50463 beq a0,a5,800097c0 <__sseek+0x44> +8000979c: 00c45783 lhu a5,12(s0) +800097a0: 00001737 lui a4,0x1 +800097a4: 00c12083 lw ra,12(sp) +800097a8: 00e7e7b3 or a5,a5,a4 +800097ac: 04a42823 sw a0,80(s0) +800097b0: 00f41623 sh a5,12(s0) +800097b4: 00812403 lw s0,8(sp) +800097b8: 01010113 addi sp,sp,16 +800097bc: 00008067 ret +800097c0: 00c45783 lhu a5,12(s0) +800097c4: fffff737 lui a4,0xfffff +800097c8: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> +800097cc: 00e7f7b3 and a5,a5,a4 +800097d0: 00c12083 lw ra,12(sp) +800097d4: 00f41623 sh a5,12(s0) +800097d8: 00812403 lw s0,8(sp) +800097dc: 01010113 addi sp,sp,16 +800097e0: 00008067 ret -800097b8 <__swrite>: -800097b8: 00c59783 lh a5,12(a1) -800097bc: fe010113 addi sp,sp,-32 -800097c0: 00812c23 sw s0,24(sp) -800097c4: 00912a23 sw s1,20(sp) -800097c8: 01212823 sw s2,16(sp) -800097cc: 01312623 sw s3,12(sp) -800097d0: 00112e23 sw ra,28(sp) -800097d4: 1007f713 andi a4,a5,256 -800097d8: 00058413 mv s0,a1 -800097dc: 00050493 mv s1,a0 -800097e0: 00e59583 lh a1,14(a1) -800097e4: 00060913 mv s2,a2 -800097e8: 00068993 mv s3,a3 -800097ec: 02071e63 bnez a4,80009828 <__swrite+0x70> -800097f0: fffff737 lui a4,0xfffff -800097f4: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> -800097f8: 00e7f7b3 and a5,a5,a4 -800097fc: 00f41623 sh a5,12(s0) -80009800: 01812403 lw s0,24(sp) -80009804: 01c12083 lw ra,28(sp) -80009808: 00098693 mv a3,s3 -8000980c: 00090613 mv a2,s2 -80009810: 00c12983 lw s3,12(sp) -80009814: 01012903 lw s2,16(sp) -80009818: 00048513 mv a0,s1 -8000981c: 01412483 lw s1,20(sp) -80009820: 02010113 addi sp,sp,32 -80009824: 0a80406f j 8000d8cc <_write_r> -80009828: 00200693 li a3,2 -8000982c: 00000613 li a2,0 -80009830: 399040ef jal ra,8000e3c8 <_lseek_r> -80009834: 00c41783 lh a5,12(s0) -80009838: 00e41583 lh a1,14(s0) -8000983c: fb5ff06f j 800097f0 <__swrite+0x38> +800097e4 <__sclose>: +800097e4: 00e59583 lh a1,14(a1) +800097e8: 1d00406f j 8000d9b8 <_close_r> -80009840 <__sseek>: -80009840: ff010113 addi sp,sp,-16 -80009844: 00812423 sw s0,8(sp) -80009848: 00058413 mv s0,a1 -8000984c: 00e59583 lh a1,14(a1) -80009850: 00112623 sw ra,12(sp) -80009854: 375040ef jal ra,8000e3c8 <_lseek_r> -80009858: fff00793 li a5,-1 -8000985c: 02f50463 beq a0,a5,80009884 <__sseek+0x44> -80009860: 00c45783 lhu a5,12(s0) -80009864: 00001737 lui a4,0x1 -80009868: 00c12083 lw ra,12(sp) -8000986c: 00e7e7b3 or a5,a5,a4 -80009870: 04a42823 sw a0,80(s0) -80009874: 00f41623 sh a5,12(s0) -80009878: 00812403 lw s0,8(sp) -8000987c: 01010113 addi sp,sp,16 -80009880: 00008067 ret -80009884: 00c45783 lhu a5,12(s0) -80009888: fffff737 lui a4,0xfffff -8000988c: fff70713 addi a4,a4,-1 # ffffefff <__BSS_END__+0x7ffe83c3> -80009890: 00e7f7b3 and a5,a5,a4 -80009894: 00c12083 lw ra,12(sp) -80009898: 00f41623 sh a5,12(s0) -8000989c: 00812403 lw s0,8(sp) -800098a0: 01010113 addi sp,sp,16 -800098a4: 00008067 ret +800097ec : +800097ec: 00b567b3 or a5,a0,a1 +800097f0: 0037f793 andi a5,a5,3 +800097f4: 08079263 bnez a5,80009878 +800097f8: 0005a703 lw a4,0(a1) +800097fc: 7f7f86b7 lui a3,0x7f7f8 +80009800: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> +80009804: 00d777b3 and a5,a4,a3 +80009808: 00d787b3 add a5,a5,a3 +8000980c: 00e7e7b3 or a5,a5,a4 +80009810: 00d7e7b3 or a5,a5,a3 +80009814: fff00613 li a2,-1 +80009818: 06c79e63 bne a5,a2,80009894 +8000981c: 00050613 mv a2,a0 +80009820: fff00813 li a6,-1 +80009824: 00e62023 sw a4,0(a2) # 7ff00000 <_start-0x100000> +80009828: 0045a703 lw a4,4(a1) +8000982c: 00458593 addi a1,a1,4 +80009830: 00460613 addi a2,a2,4 +80009834: 00d777b3 and a5,a4,a3 +80009838: 00d787b3 add a5,a5,a3 +8000983c: 00e7e7b3 or a5,a5,a4 +80009840: 00d7e7b3 or a5,a5,a3 +80009844: ff0780e3 beq a5,a6,80009824 +80009848: 0005c783 lbu a5,0(a1) +8000984c: 0015c703 lbu a4,1(a1) +80009850: 0025c683 lbu a3,2(a1) +80009854: 00f60023 sb a5,0(a2) +80009858: 00078a63 beqz a5,8000986c +8000985c: 00e600a3 sb a4,1(a2) +80009860: 00070663 beqz a4,8000986c +80009864: 00d60123 sb a3,2(a2) +80009868: 00069463 bnez a3,80009870 +8000986c: 00008067 ret +80009870: 000601a3 sb zero,3(a2) +80009874: 00008067 ret +80009878: 00050793 mv a5,a0 +8000987c: 0005c703 lbu a4,0(a1) +80009880: 00178793 addi a5,a5,1 +80009884: 00158593 addi a1,a1,1 +80009888: fee78fa3 sb a4,-1(a5) +8000988c: fe0718e3 bnez a4,8000987c +80009890: 00008067 ret +80009894: 00050613 mv a2,a0 +80009898: fb1ff06f j 80009848 -800098a8 <__sclose>: -800098a8: 00e59583 lh a1,14(a1) -800098ac: 1d00406f j 8000da7c <_close_r> +8000989c : +8000989c: 00357793 andi a5,a0,3 +800098a0: 00050713 mv a4,a0 +800098a4: 04079c63 bnez a5,800098fc +800098a8: 7f7f86b7 lui a3,0x7f7f8 +800098ac: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> +800098b0: fff00593 li a1,-1 +800098b4: 00072603 lw a2,0(a4) +800098b8: 00470713 addi a4,a4,4 +800098bc: 00d677b3 and a5,a2,a3 +800098c0: 00d787b3 add a5,a5,a3 +800098c4: 00c7e7b3 or a5,a5,a2 +800098c8: 00d7e7b3 or a5,a5,a3 +800098cc: feb784e3 beq a5,a1,800098b4 +800098d0: ffc74683 lbu a3,-4(a4) +800098d4: ffd74603 lbu a2,-3(a4) +800098d8: ffe74783 lbu a5,-2(a4) +800098dc: 40a70733 sub a4,a4,a0 +800098e0: 04068063 beqz a3,80009920 +800098e4: 02060a63 beqz a2,80009918 +800098e8: 00f03533 snez a0,a5 +800098ec: 00e50533 add a0,a0,a4 +800098f0: ffe50513 addi a0,a0,-2 +800098f4: 00008067 ret +800098f8: fa0688e3 beqz a3,800098a8 +800098fc: 00074783 lbu a5,0(a4) +80009900: 00170713 addi a4,a4,1 +80009904: 00377693 andi a3,a4,3 +80009908: fe0798e3 bnez a5,800098f8 +8000990c: 40a70733 sub a4,a4,a0 +80009910: fff70513 addi a0,a4,-1 +80009914: 00008067 ret +80009918: ffd70513 addi a0,a4,-3 +8000991c: 00008067 ret +80009920: ffc70513 addi a0,a4,-4 +80009924: 00008067 ret -800098b0 : -800098b0: 00b567b3 or a5,a0,a1 -800098b4: 0037f793 andi a5,a5,3 -800098b8: 08079263 bnez a5,8000993c -800098bc: 0005a703 lw a4,0(a1) -800098c0: 7f7f86b7 lui a3,0x7f7f8 -800098c4: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> -800098c8: 00d777b3 and a5,a4,a3 -800098cc: 00d787b3 add a5,a5,a3 -800098d0: 00e7e7b3 or a5,a5,a4 -800098d4: 00d7e7b3 or a5,a5,a3 -800098d8: fff00613 li a2,-1 -800098dc: 06c79e63 bne a5,a2,80009958 -800098e0: 00050613 mv a2,a0 -800098e4: fff00813 li a6,-1 -800098e8: 00e62023 sw a4,0(a2) # 7ff00000 <_start-0x100000> -800098ec: 0045a703 lw a4,4(a1) -800098f0: 00458593 addi a1,a1,4 -800098f4: 00460613 addi a2,a2,4 -800098f8: 00d777b3 and a5,a4,a3 -800098fc: 00d787b3 add a5,a5,a3 -80009900: 00e7e7b3 or a5,a5,a4 -80009904: 00d7e7b3 or a5,a5,a3 -80009908: ff0780e3 beq a5,a6,800098e8 -8000990c: 0005c783 lbu a5,0(a1) -80009910: 0015c703 lbu a4,1(a1) -80009914: 0025c683 lbu a3,2(a1) -80009918: 00f60023 sb a5,0(a2) -8000991c: 00078a63 beqz a5,80009930 -80009920: 00e600a3 sb a4,1(a2) -80009924: 00070663 beqz a4,80009930 -80009928: 00d60123 sb a3,2(a2) -8000992c: 00069463 bnez a3,80009934 -80009930: 00008067 ret -80009934: 000601a3 sb zero,3(a2) -80009938: 00008067 ret -8000993c: 00050793 mv a5,a0 -80009940: 0005c703 lbu a4,0(a1) -80009944: 00178793 addi a5,a5,1 -80009948: 00158593 addi a1,a1,1 -8000994c: fee78fa3 sb a4,-1(a5) -80009950: fe0718e3 bnez a4,80009940 -80009954: 00008067 ret -80009958: 00050613 mv a2,a0 -8000995c: fb1ff06f j 8000990c +80009928 : +80009928: 00a5e7b3 or a5,a1,a0 +8000992c: 0037f793 andi a5,a5,3 +80009930: 00050713 mv a4,a0 +80009934: 06079863 bnez a5,800099a4 +80009938: 00300793 li a5,3 +8000993c: 06c7f463 bgeu a5,a2,800099a4 +80009940: feff0337 lui t1,0xfeff0 +80009944: 808088b7 lui a7,0x80808 +80009948: eff30313 addi t1,t1,-257 # fefefeff <__BSS_END__+0x7efd92c3> +8000994c: 08088893 addi a7,a7,128 # 80808080 <__BSS_END__+0x7f1444> +80009950: 00300e13 li t3,3 +80009954: 0005a683 lw a3,0(a1) +80009958: 006687b3 add a5,a3,t1 +8000995c: fff6c813 not a6,a3 +80009960: 0107f7b3 and a5,a5,a6 +80009964: 0117f7b3 and a5,a5,a7 +80009968: 02079e63 bnez a5,800099a4 +8000996c: 00d72023 sw a3,0(a4) +80009970: ffc60613 addi a2,a2,-4 +80009974: 00470713 addi a4,a4,4 +80009978: 00458593 addi a1,a1,4 +8000997c: fcce6ce3 bltu t3,a2,80009954 +80009980: 00158593 addi a1,a1,1 +80009984: 00170793 addi a5,a4,1 +80009988: 02060463 beqz a2,800099b0 +8000998c: fff5c683 lbu a3,-1(a1) +80009990: fff60813 addi a6,a2,-1 +80009994: fed78fa3 sb a3,-1(a5) +80009998: 00068e63 beqz a3,800099b4 +8000999c: 00078713 mv a4,a5 +800099a0: 00080613 mv a2,a6 +800099a4: 00158593 addi a1,a1,1 +800099a8: 00170793 addi a5,a4,1 +800099ac: fe0610e3 bnez a2,8000998c +800099b0: 00008067 ret +800099b4: 00c70633 add a2,a4,a2 +800099b8: 00080a63 beqz a6,800099cc +800099bc: 00178793 addi a5,a5,1 +800099c0: fe078fa3 sb zero,-1(a5) +800099c4: fec79ce3 bne a5,a2,800099bc +800099c8: 00008067 ret +800099cc: 00008067 ret -80009960 : -80009960: 00357793 andi a5,a0,3 -80009964: 00050713 mv a4,a0 -80009968: 04079c63 bnez a5,800099c0 -8000996c: 7f7f86b7 lui a3,0x7f7f8 -80009970: f7f68693 addi a3,a3,-129 # 7f7f7f7f <_start-0x808081> -80009974: fff00593 li a1,-1 -80009978: 00072603 lw a2,0(a4) -8000997c: 00470713 addi a4,a4,4 -80009980: 00d677b3 and a5,a2,a3 -80009984: 00d787b3 add a5,a5,a3 -80009988: 00c7e7b3 or a5,a5,a2 -8000998c: 00d7e7b3 or a5,a5,a3 -80009990: feb784e3 beq a5,a1,80009978 -80009994: ffc74683 lbu a3,-4(a4) -80009998: ffd74603 lbu a2,-3(a4) -8000999c: ffe74783 lbu a5,-2(a4) -800099a0: 40a70733 sub a4,a4,a0 -800099a4: 04068063 beqz a3,800099e4 -800099a8: 02060a63 beqz a2,800099dc -800099ac: 00f03533 snez a0,a5 -800099b0: 00e50533 add a0,a0,a4 -800099b4: ffe50513 addi a0,a0,-2 -800099b8: 00008067 ret -800099bc: fa0688e3 beqz a3,8000996c -800099c0: 00074783 lbu a5,0(a4) -800099c4: 00170713 addi a4,a4,1 -800099c8: 00377693 andi a3,a4,3 -800099cc: fe0798e3 bnez a5,800099bc -800099d0: 40a70733 sub a4,a4,a0 -800099d4: fff70513 addi a0,a4,-1 -800099d8: 00008067 ret -800099dc: ffd70513 addi a0,a4,-3 -800099e0: 00008067 ret -800099e4: ffc70513 addi a0,a4,-4 -800099e8: 00008067 ret - -800099ec : -800099ec: 00a5e7b3 or a5,a1,a0 -800099f0: 0037f793 andi a5,a5,3 -800099f4: 00050713 mv a4,a0 -800099f8: 06079863 bnez a5,80009a68 -800099fc: 00300793 li a5,3 -80009a00: 06c7f463 bgeu a5,a2,80009a68 -80009a04: feff0337 lui t1,0xfeff0 -80009a08: 808088b7 lui a7,0x80808 -80009a0c: eff30313 addi t1,t1,-257 # fefefeff <__BSS_END__+0x7efd92c3> -80009a10: 08088893 addi a7,a7,128 # 80808080 <__BSS_END__+0x7f1444> -80009a14: 00300e13 li t3,3 -80009a18: 0005a683 lw a3,0(a1) -80009a1c: 006687b3 add a5,a3,t1 -80009a20: fff6c813 not a6,a3 -80009a24: 0107f7b3 and a5,a5,a6 -80009a28: 0117f7b3 and a5,a5,a7 -80009a2c: 02079e63 bnez a5,80009a68 -80009a30: 00d72023 sw a3,0(a4) -80009a34: ffc60613 addi a2,a2,-4 -80009a38: 00470713 addi a4,a4,4 -80009a3c: 00458593 addi a1,a1,4 -80009a40: fcce6ce3 bltu t3,a2,80009a18 -80009a44: 00158593 addi a1,a1,1 -80009a48: 00170793 addi a5,a4,1 -80009a4c: 02060463 beqz a2,80009a74 -80009a50: fff5c683 lbu a3,-1(a1) -80009a54: fff60813 addi a6,a2,-1 -80009a58: fed78fa3 sb a3,-1(a5) -80009a5c: 00068e63 beqz a3,80009a78 -80009a60: 00078713 mv a4,a5 -80009a64: 00080613 mv a2,a6 -80009a68: 00158593 addi a1,a1,1 -80009a6c: 00170793 addi a5,a4,1 -80009a70: fe0610e3 bnez a2,80009a50 -80009a74: 00008067 ret -80009a78: 00c70633 add a2,a4,a2 -80009a7c: 00080a63 beqz a6,80009a90 -80009a80: 00178793 addi a5,a5,1 -80009a84: fe078fa3 sb zero,-1(a5) -80009a88: fec79ce3 bne a5,a2,80009a80 -80009a8c: 00008067 ret -80009a90: 00008067 ret - -80009a94 <_svfprintf_r>: -80009a94: e1010113 addi sp,sp,-496 -80009a98: 1e112623 sw ra,492(sp) -80009a9c: 1f212023 sw s2,480(sp) -80009aa0: 1d812423 sw s8,456(sp) -80009aa4: 1da12023 sw s10,448(sp) -80009aa8: 00058c13 mv s8,a1 -80009aac: 00060913 mv s2,a2 -80009ab0: 00d12a23 sw a3,20(sp) -80009ab4: 1e812423 sw s0,488(sp) -80009ab8: 1e912223 sw s1,484(sp) -80009abc: 1d312e23 sw s3,476(sp) -80009ac0: 1d412c23 sw s4,472(sp) -80009ac4: 1d512a23 sw s5,468(sp) -80009ac8: 1d612823 sw s6,464(sp) -80009acc: 1d712623 sw s7,460(sp) -80009ad0: 1d912223 sw s9,452(sp) -80009ad4: 1bb12e23 sw s11,444(sp) -80009ad8: 00050d13 mv s10,a0 -80009adc: ecdfd0ef jal ra,800079a8 <_localeconv_r> -80009ae0: 00052783 lw a5,0(a0) -80009ae4: 00078513 mv a0,a5 -80009ae8: 02f12823 sw a5,48(sp) -80009aec: e75ff0ef jal ra,80009960 -80009af0: 00cc5703 lhu a4,12(s8) -80009af4: 0e012823 sw zero,240(sp) -80009af8: 0e012a23 sw zero,244(sp) -80009afc: 0e012c23 sw zero,248(sp) -80009b00: 0e012e23 sw zero,252(sp) -80009b04: 08077713 andi a4,a4,128 -80009b08: 02a12623 sw a0,44(sp) -80009b0c: 00070863 beqz a4,80009b1c <_svfprintf_r+0x88> -80009b10: 010c2703 lw a4,16(s8) -80009b14: 00071463 bnez a4,80009b1c <_svfprintf_r+0x88> -80009b18: 56c0106f j 8000b084 <_svfprintf_r+0x15f0> -80009b1c: 10c10793 addi a5,sp,268 -80009b20: 80015737 lui a4,0x80015 -80009b24: 0ef12223 sw a5,228(sp) -80009b28: 00078893 mv a7,a5 -80009b2c: 1e070793 addi a5,a4,480 # 800151e0 <__BSS_END__+0xffffe5a4> -80009b30: 80015737 lui a4,0x80015 -80009b34: 00f12c23 sw a5,24(sp) -80009b38: 00090b13 mv s6,s2 -80009b3c: 35c70793 addi a5,a4,860 # 8001535c <__BSS_END__+0xffffe720> -80009b40: 00f12423 sw a5,8(sp) -80009b44: 000b4783 lbu a5,0(s6) -80009b48: 0e012623 sw zero,236(sp) -80009b4c: 0e012423 sw zero,232(sp) -80009b50: 02012023 sw zero,32(sp) -80009b54: 02012a23 sw zero,52(sp) -80009b58: 02012c23 sw zero,56(sp) -80009b5c: 02012e23 sw zero,60(sp) -80009b60: 04012423 sw zero,72(sp) -80009b64: 04012623 sw zero,76(sp) -80009b68: 00012623 sw zero,12(sp) -80009b6c: 22078463 beqz a5,80009d94 <_svfprintf_r+0x300> -80009b70: 000b0413 mv s0,s6 -80009b74: 02500693 li a3,37 -80009b78: 2cd78463 beq a5,a3,80009e40 <_svfprintf_r+0x3ac> -80009b7c: 00144783 lbu a5,1(s0) -80009b80: 00140413 addi s0,s0,1 -80009b84: fe079ae3 bnez a5,80009b78 <_svfprintf_r+0xe4> -80009b88: 416404b3 sub s1,s0,s6 -80009b8c: 21640463 beq s0,s6,80009d94 <_svfprintf_r+0x300> -80009b90: 0ec12683 lw a3,236(sp) -80009b94: 0e812783 lw a5,232(sp) -80009b98: 0168a023 sw s6,0(a7) -80009b9c: 009686b3 add a3,a3,s1 -80009ba0: 00178793 addi a5,a5,1 -80009ba4: 0098a223 sw s1,4(a7) -80009ba8: 0ed12623 sw a3,236(sp) -80009bac: 0ef12423 sw a5,232(sp) -80009bb0: 00700693 li a3,7 -80009bb4: 00888893 addi a7,a7,8 -80009bb8: 28f6cc63 blt a3,a5,80009e50 <_svfprintf_r+0x3bc> -80009bbc: 00c12703 lw a4,12(sp) -80009bc0: 00044783 lbu a5,0(s0) -80009bc4: 00970733 add a4,a4,s1 -80009bc8: 00e12623 sw a4,12(sp) -80009bcc: 1c078463 beqz a5,80009d94 <_svfprintf_r+0x300> -80009bd0: 00144483 lbu s1,1(s0) -80009bd4: 0c0103a3 sb zero,199(sp) -80009bd8: 00140413 addi s0,s0,1 -80009bdc: fff00d93 li s11,-1 -80009be0: 00000993 li s3,0 -80009be4: 00000a13 li s4,0 -80009be8: 05a00913 li s2,90 -80009bec: 00900a93 li s5,9 -80009bf0: 02a00b93 li s7,42 -80009bf4: 00088c93 mv s9,a7 -80009bf8: 00140413 addi s0,s0,1 -80009bfc: fe048793 addi a5,s1,-32 # 7fffffe0 <__BSS_END__+0xfffe93a4> -80009c00: 04f96463 bltu s2,a5,80009c48 <_svfprintf_r+0x1b4> -80009c04: 01812703 lw a4,24(sp) -80009c08: 00279793 slli a5,a5,0x2 -80009c0c: 00e787b3 add a5,a5,a4 -80009c10: 0007a783 lw a5,0(a5) -80009c14: 00078067 jr a5 -80009c18: 00000993 li s3,0 -80009c1c: fd048693 addi a3,s1,-48 -80009c20: 00044483 lbu s1,0(s0) -80009c24: 00299793 slli a5,s3,0x2 -80009c28: 013787b3 add a5,a5,s3 -80009c2c: 00179793 slli a5,a5,0x1 -80009c30: 00f689b3 add s3,a3,a5 -80009c34: fd048693 addi a3,s1,-48 -80009c38: 00140413 addi s0,s0,1 -80009c3c: fedaf2e3 bgeu s5,a3,80009c20 <_svfprintf_r+0x18c> -80009c40: fe048793 addi a5,s1,-32 -80009c44: fcf970e3 bgeu s2,a5,80009c04 <_svfprintf_r+0x170> -80009c48: 000c8893 mv a7,s9 -80009c4c: 14048463 beqz s1,80009d94 <_svfprintf_r+0x300> -80009c50: 14910623 sb s1,332(sp) -80009c54: 0c0103a3 sb zero,199(sp) -80009c58: 00100a93 li s5,1 -80009c5c: 00100c93 li s9,1 -80009c60: 14c10b13 addi s6,sp,332 -80009c64: 00012823 sw zero,16(sp) -80009c68: 00000d93 li s11,0 -80009c6c: 02012423 sw zero,40(sp) -80009c70: 02012223 sw zero,36(sp) -80009c74: 00012e23 sw zero,28(sp) -80009c78: 002a7b93 andi s7,s4,2 -80009c7c: 000b8463 beqz s7,80009c84 <_svfprintf_r+0x1f0> -80009c80: 002a8a93 addi s5,s5,2 -80009c84: 084a7913 andi s2,s4,132 -80009c88: 0ec12783 lw a5,236(sp) -80009c8c: 00091663 bnez s2,80009c98 <_svfprintf_r+0x204> -80009c90: 41598833 sub a6,s3,s5 -80009c94: 63004ce3 bgtz a6,8000aacc <_svfprintf_r+0x1038> -80009c98: 0c714683 lbu a3,199(sp) -80009c9c: 02068a63 beqz a3,80009cd0 <_svfprintf_r+0x23c> -80009ca0: 0e812683 lw a3,232(sp) -80009ca4: 0c710613 addi a2,sp,199 -80009ca8: 00c8a023 sw a2,0(a7) -80009cac: 00178793 addi a5,a5,1 -80009cb0: 00100613 li a2,1 -80009cb4: 00168693 addi a3,a3,1 -80009cb8: 00c8a223 sw a2,4(a7) -80009cbc: 0ef12623 sw a5,236(sp) -80009cc0: 0ed12423 sw a3,232(sp) -80009cc4: 00700613 li a2,7 -80009cc8: 00888893 addi a7,a7,8 -80009ccc: 4cd64c63 blt a2,a3,8000a1a4 <_svfprintf_r+0x710> -80009cd0: 020b8a63 beqz s7,80009d04 <_svfprintf_r+0x270> -80009cd4: 0e812683 lw a3,232(sp) -80009cd8: 0c810613 addi a2,sp,200 -80009cdc: 00c8a023 sw a2,0(a7) -80009ce0: 00278793 addi a5,a5,2 -80009ce4: 00200613 li a2,2 -80009ce8: 00168693 addi a3,a3,1 -80009cec: 00c8a223 sw a2,4(a7) -80009cf0: 0ef12623 sw a5,236(sp) -80009cf4: 0ed12423 sw a3,232(sp) -80009cf8: 00700613 li a2,7 -80009cfc: 00888893 addi a7,a7,8 -80009d00: 6ad64ce3 blt a2,a3,8000abb8 <_svfprintf_r+0x1124> -80009d04: 08000693 li a3,128 -80009d08: 42d900e3 beq s2,a3,8000a928 <_svfprintf_r+0xe94> -80009d0c: 419d8db3 sub s11,s11,s9 -80009d10: 4db04ee3 bgtz s11,8000a9ec <_svfprintf_r+0xf58> -80009d14: 100a7693 andi a3,s4,256 -80009d18: 2c069ae3 bnez a3,8000a7ec <_svfprintf_r+0xd58> -80009d1c: 0e812703 lw a4,232(sp) -80009d20: 019787b3 add a5,a5,s9 -80009d24: 0168a023 sw s6,0(a7) -80009d28: 00170713 addi a4,a4,1 -80009d2c: 0198a223 sw s9,4(a7) -80009d30: 0ef12623 sw a5,236(sp) -80009d34: 0ee12423 sw a4,232(sp) -80009d38: 00700693 li a3,7 -80009d3c: 5ae6c063 blt a3,a4,8000a2dc <_svfprintf_r+0x848> -80009d40: 00888893 addi a7,a7,8 -80009d44: 004a7a13 andi s4,s4,4 -80009d48: 000a0663 beqz s4,80009d54 <_svfprintf_r+0x2c0> -80009d4c: 415984b3 sub s1,s3,s5 -80009d50: 5a904663 bgtz s1,8000a2fc <_svfprintf_r+0x868> -80009d54: 0159d463 bge s3,s5,80009d5c <_svfprintf_r+0x2c8> -80009d58: 000a8993 mv s3,s5 -80009d5c: 00c12703 lw a4,12(sp) -80009d60: 01370733 add a4,a4,s3 -80009d64: 00e12623 sw a4,12(sp) -80009d68: 52079ce3 bnez a5,8000aaa0 <_svfprintf_r+0x100c> -80009d6c: 01012783 lw a5,16(sp) -80009d70: 0e012423 sw zero,232(sp) -80009d74: 00078863 beqz a5,80009d84 <_svfprintf_r+0x2f0> -80009d78: 01012583 lw a1,16(sp) -80009d7c: 000d0513 mv a0,s10 -80009d80: c55fa0ef jal ra,800049d4 <_free_r> -80009d84: 10c10893 addi a7,sp,268 -80009d88: 00040b13 mv s6,s0 -80009d8c: 000b4783 lbu a5,0(s6) -80009d90: de0790e3 bnez a5,80009b70 <_svfprintf_r+0xdc> -80009d94: 0ec12783 lw a5,236(sp) -80009d98: 00078463 beqz a5,80009da0 <_svfprintf_r+0x30c> -80009d9c: 3450106f j 8000b8e0 <_svfprintf_r+0x1e4c> -80009da0: 00cc5703 lhu a4,12(s8) -80009da4: 04077713 andi a4,a4,64 -80009da8: 00070463 beqz a4,80009db0 <_svfprintf_r+0x31c> -80009dac: 3f80206f j 8000c1a4 <_svfprintf_r+0x2710> -80009db0: 1ec12083 lw ra,492(sp) -80009db4: 1e812403 lw s0,488(sp) -80009db8: 00c12503 lw a0,12(sp) -80009dbc: 1e412483 lw s1,484(sp) -80009dc0: 1e012903 lw s2,480(sp) -80009dc4: 1dc12983 lw s3,476(sp) -80009dc8: 1d812a03 lw s4,472(sp) -80009dcc: 1d412a83 lw s5,468(sp) -80009dd0: 1d012b03 lw s6,464(sp) -80009dd4: 1cc12b83 lw s7,460(sp) -80009dd8: 1c812c03 lw s8,456(sp) -80009ddc: 1c412c83 lw s9,452(sp) -80009de0: 1c012d03 lw s10,448(sp) -80009de4: 1bc12d83 lw s11,444(sp) -80009de8: 1f010113 addi sp,sp,496 -80009dec: 00008067 ret -80009df0: 000d0513 mv a0,s10 -80009df4: bb5fd0ef jal ra,800079a8 <_localeconv_r> -80009df8: 00452783 lw a5,4(a0) -80009dfc: 00078513 mv a0,a5 -80009e00: 04f12623 sw a5,76(sp) -80009e04: b5dff0ef jal ra,80009960 -80009e08: 00050793 mv a5,a0 -80009e0c: 000d0513 mv a0,s10 -80009e10: 00078493 mv s1,a5 -80009e14: 04f12423 sw a5,72(sp) -80009e18: b91fd0ef jal ra,800079a8 <_localeconv_r> -80009e1c: 00852783 lw a5,8(a0) -80009e20: 02f12e23 sw a5,60(sp) -80009e24: 00048463 beqz s1,80009e2c <_svfprintf_r+0x398> -80009e28: 1640106f j 8000af8c <_svfprintf_r+0x14f8> -80009e2c: 00044483 lbu s1,0(s0) -80009e30: dc9ff06f j 80009bf8 <_svfprintf_r+0x164> -80009e34: 00044483 lbu s1,0(s0) -80009e38: 020a6a13 ori s4,s4,32 -80009e3c: dbdff06f j 80009bf8 <_svfprintf_r+0x164> -80009e40: 416404b3 sub s1,s0,s6 -80009e44: d56416e3 bne s0,s6,80009b90 <_svfprintf_r+0xfc> -80009e48: 00044783 lbu a5,0(s0) -80009e4c: d81ff06f j 80009bcc <_svfprintf_r+0x138> -80009e50: 0e410613 addi a2,sp,228 -80009e54: 000c0593 mv a1,s8 -80009e58: 000d0513 mv a0,s10 -80009e5c: 120050ef jal ra,8000ef7c <__ssprint_r> -80009e60: f40510e3 bnez a0,80009da0 <_svfprintf_r+0x30c> -80009e64: 10c10893 addi a7,sp,268 -80009e68: d55ff06f j 80009bbc <_svfprintf_r+0x128> -80009e6c: 008a7793 andi a5,s4,8 -80009e70: 000c8893 mv a7,s9 -80009e74: 00078463 beqz a5,80009e7c <_svfprintf_r+0x3e8> -80009e78: 0a80106f j 8000af20 <_svfprintf_r+0x148c> -80009e7c: 01412783 lw a5,20(sp) -80009e80: 0b010513 addi a0,sp,176 -80009e84: 01912823 sw s9,16(sp) -80009e88: 00778793 addi a5,a5,7 -80009e8c: ff87f793 andi a5,a5,-8 -80009e90: 0007a583 lw a1,0(a5) -80009e94: 0047a603 lw a2,4(a5) -80009e98: 00878793 addi a5,a5,8 -80009e9c: 00f12a23 sw a5,20(sp) -80009ea0: 5e80a0ef jal ra,80014488 <__extenddftf2> -80009ea4: 0b012783 lw a5,176(sp) -80009ea8: 01012883 lw a7,16(sp) -80009eac: 0ef12823 sw a5,240(sp) -80009eb0: 0b412783 lw a5,180(sp) -80009eb4: 0ef12a23 sw a5,244(sp) -80009eb8: 0b812783 lw a5,184(sp) -80009ebc: 0ef12c23 sw a5,248(sp) -80009ec0: 0bc12783 lw a5,188(sp) -80009ec4: 0ef12e23 sw a5,252(sp) -80009ec8: 0f010513 addi a0,sp,240 -80009ecc: 01112823 sw a7,16(sp) -80009ed0: a6dfd0ef jal ra,8000793c <_ldcheck> -80009ed4: 0ca12623 sw a0,204(sp) -80009ed8: 00200793 li a5,2 -80009edc: 01012883 lw a7,16(sp) -80009ee0: 00f51463 bne a0,a5,80009ee8 <_svfprintf_r+0x454> -80009ee4: 6580106f j 8000b53c <_svfprintf_r+0x1aa8> -80009ee8: 00100793 li a5,1 -80009eec: 00f51463 bne a0,a5,80009ef4 <_svfprintf_r+0x460> -80009ef0: 0750106f j 8000b764 <_svfprintf_r+0x1cd0> -80009ef4: 06100793 li a5,97 -80009ef8: 00f49463 bne s1,a5,80009f00 <_svfprintf_r+0x46c> -80009efc: 19c0206f j 8000c098 <_svfprintf_r+0x2604> -80009f00: 04100793 li a5,65 -80009f04: 00f49463 bne s1,a5,80009f0c <_svfprintf_r+0x478> -80009f08: 52d0106f j 8000bc34 <_svfprintf_r+0x21a0> -80009f0c: fdf4fb93 andi s7,s1,-33 -80009f10: fff00793 li a5,-1 -80009f14: 05712a23 sw s7,84(sp) -80009f18: 00fd9463 bne s11,a5,80009f20 <_svfprintf_r+0x48c> -80009f1c: 2150106f j 8000b930 <_svfprintf_r+0x1e9c> -80009f20: 04700793 li a5,71 -80009f24: 00fb9463 bne s7,a5,80009f2c <_svfprintf_r+0x498> -80009f28: 1e80206f j 8000c110 <_svfprintf_r+0x267c> -80009f2c: 0fc12303 lw t1,252(sp) -80009f30: 03412423 sw s4,40(sp) -80009f34: 0f012e03 lw t3,240(sp) -80009f38: 0f412e83 lw t4,244(sp) -80009f3c: 0f812f03 lw t5,248(sp) -80009f40: 100a6793 ori a5,s4,256 -80009f44: 00035463 bgez t1,80009f4c <_svfprintf_r+0x4b8> -80009f48: 39c0206f j 8000c2e4 <_svfprintf_r+0x2850> -80009f4c: 04012c23 sw zero,88(sp) -80009f50: 00078a13 mv s4,a5 -80009f54: 00012823 sw zero,16(sp) -80009f58: 04600793 li a5,70 -80009f5c: 00fb9463 bne s7,a5,80009f64 <_svfprintf_r+0x4d0> -80009f60: 2b90106f j 8000ba18 <_svfprintf_r+0x1f84> -80009f64: 04500793 li a5,69 -80009f68: 05112223 sw a7,68(sp) -80009f6c: 00fb8463 beq s7,a5,80009f74 <_svfprintf_r+0x4e0> -80009f70: 33d0106f j 8000baac <_svfprintf_r+0x2018> -80009f74: 001d8913 addi s2,s11,1 -80009f78: 0b010a93 addi s5,sp,176 -80009f7c: 00090693 mv a3,s2 -80009f80: 0dc10813 addi a6,sp,220 -80009f84: 0d010793 addi a5,sp,208 -80009f88: 0cc10713 addi a4,sp,204 -80009f8c: 00200613 li a2,2 -80009f90: 000a8593 mv a1,s5 -80009f94: 000d0513 mv a0,s10 -80009f98: 0bc12823 sw t3,176(sp) -80009f9c: 05c12023 sw t3,64(sp) -80009fa0: 0bd12a23 sw t4,180(sp) -80009fa4: 03d12223 sw t4,36(sp) -80009fa8: 0be12c23 sw t5,184(sp) -80009fac: 03e12023 sw t5,32(sp) -80009fb0: 0a612e23 sw t1,188(sp) -80009fb4: 00612e23 sw t1,28(sp) -80009fb8: eecfc0ef jal ra,800066a4 <_ldtoa_r> -80009fbc: 01c12303 lw t1,28(sp) -80009fc0: 02012f03 lw t5,32(sp) -80009fc4: 02412e83 lw t4,36(sp) -80009fc8: 04012e03 lw t3,64(sp) -80009fcc: 04412883 lw a7,68(sp) -80009fd0: 00050b13 mv s6,a0 -80009fd4: 01250933 add s2,a0,s2 -80009fd8: 0a010c93 addi s9,sp,160 -80009fdc: 000c8593 mv a1,s9 -80009fe0: 000a8513 mv a0,s5 -80009fe4: 01112e23 sw a7,28(sp) -80009fe8: 0bc12823 sw t3,176(sp) -80009fec: 0bd12a23 sw t4,180(sp) -80009ff0: 0be12c23 sw t5,184(sp) -80009ff4: 0a612e23 sw t1,188(sp) -80009ff8: 0a012023 sw zero,160(sp) -80009ffc: 0a012223 sw zero,164(sp) -8000a000: 0a012423 sw zero,168(sp) -8000a004: 0a012623 sw zero,172(sp) -8000a008: 1a5070ef jal ra,800119ac <__eqtf2> -8000a00c: 01c12883 lw a7,28(sp) -8000a010: 00090713 mv a4,s2 -8000a014: 02050263 beqz a0,8000a038 <_svfprintf_r+0x5a4> -8000a018: 0dc12703 lw a4,220(sp) -8000a01c: 01277e63 bgeu a4,s2,8000a038 <_svfprintf_r+0x5a4> -8000a020: 03000693 li a3,48 -8000a024: 00170793 addi a5,a4,1 -8000a028: 0cf12e23 sw a5,220(sp) -8000a02c: 00d70023 sb a3,0(a4) -8000a030: 0dc12703 lw a4,220(sp) -8000a034: ff2768e3 bltu a4,s2,8000a024 <_svfprintf_r+0x590> -8000a038: 416707b3 sub a5,a4,s6 -8000a03c: 02f12023 sw a5,32(sp) -8000a040: 0cc12703 lw a4,204(sp) -8000a044: 04700793 li a5,71 -8000a048: 00e12e23 sw a4,28(sp) -8000a04c: 05412703 lw a4,84(sp) -8000a050: 00f71463 bne a4,a5,8000a058 <_svfprintf_r+0x5c4> -8000a054: 1150106f j 8000b968 <_svfprintf_r+0x1ed4> -8000a058: 05412703 lw a4,84(sp) -8000a05c: 04600793 li a5,70 -8000a060: 00f71463 bne a4,a5,8000a068 <_svfprintf_r+0x5d4> -8000a064: 34d0106f j 8000bbb0 <_svfprintf_r+0x211c> -8000a068: 01c12783 lw a5,28(sp) -8000a06c: 05412703 lw a4,84(sp) -8000a070: 04100593 li a1,65 -8000a074: fff78793 addi a5,a5,-1 -8000a078: 0cf12623 sw a5,204(sp) -8000a07c: 0ff4f693 andi a3,s1,255 -8000a080: 00000613 li a2,0 -8000a084: 00b71863 bne a4,a1,8000a094 <_svfprintf_r+0x600> -8000a088: 00f68693 addi a3,a3,15 -8000a08c: 0ff6f693 andi a3,a3,255 -8000a090: 00100613 li a2,1 -8000a094: 0cd10a23 sb a3,212(sp) -8000a098: 02b00693 li a3,43 -8000a09c: 0007da63 bgez a5,8000a0b0 <_svfprintf_r+0x61c> -8000a0a0: 01c12703 lw a4,28(sp) -8000a0a4: 00100793 li a5,1 -8000a0a8: 02d00693 li a3,45 -8000a0ac: 40e787b3 sub a5,a5,a4 -8000a0b0: 0cd10aa3 sb a3,213(sp) -8000a0b4: 00900693 li a3,9 -8000a0b8: 00f6c463 blt a3,a5,8000a0c0 <_svfprintf_r+0x62c> -8000a0bc: 0f40206f j 8000c1b0 <_svfprintf_r+0x271c> -8000a0c0: 0e310813 addi a6,sp,227 -8000a0c4: 00080513 mv a0,a6 -8000a0c8: 00a00613 li a2,10 -8000a0cc: 06300e13 li t3,99 -8000a0d0: 02c7e733 rem a4,a5,a2 -8000a0d4: 00050593 mv a1,a0 -8000a0d8: 00078693 mv a3,a5 -8000a0dc: fff50513 addi a0,a0,-1 -8000a0e0: 03070713 addi a4,a4,48 -8000a0e4: fee58fa3 sb a4,-1(a1) -8000a0e8: 02c7c7b3 div a5,a5,a2 -8000a0ec: fede42e3 blt t3,a3,8000a0d0 <_svfprintf_r+0x63c> -8000a0f0: 03078793 addi a5,a5,48 -8000a0f4: 0ff7f613 andi a2,a5,255 -8000a0f8: fec50fa3 sb a2,-1(a0) -8000a0fc: ffe58793 addi a5,a1,-2 -8000a100: 0107e463 bltu a5,a6,8000a108 <_svfprintf_r+0x674> -8000a104: 3980206f j 8000c49c <_svfprintf_r+0x2a08> -8000a108: 0d610693 addi a3,sp,214 -8000a10c: 0080006f j 8000a114 <_svfprintf_r+0x680> -8000a110: 0007c603 lbu a2,0(a5) -8000a114: 00c68023 sb a2,0(a3) -8000a118: 00178793 addi a5,a5,1 -8000a11c: 00168693 addi a3,a3,1 -8000a120: ff0798e3 bne a5,a6,8000a110 <_svfprintf_r+0x67c> -8000a124: 0e510793 addi a5,sp,229 -8000a128: 40b787b3 sub a5,a5,a1 -8000a12c: 0d610713 addi a4,sp,214 -8000a130: 00f707b3 add a5,a4,a5 -8000a134: 0d410693 addi a3,sp,212 -8000a138: 40d787b3 sub a5,a5,a3 -8000a13c: 02f12c23 sw a5,56(sp) -8000a140: 02012703 lw a4,32(sp) -8000a144: 03812683 lw a3,56(sp) -8000a148: 00100793 li a5,1 -8000a14c: 00d70cb3 add s9,a4,a3 -8000a150: 00e7c463 blt a5,a4,8000a158 <_svfprintf_r+0x6c4> -8000a154: 2300206f j 8000c384 <_svfprintf_r+0x28f0> -8000a158: 02c12783 lw a5,44(sp) -8000a15c: 00fc8cb3 add s9,s9,a5 -8000a160: 02812783 lw a5,40(sp) -8000a164: fffcca93 not s5,s9 -8000a168: 41fada93 srai s5,s5,0x1f -8000a16c: bff7fa13 andi s4,a5,-1025 -8000a170: 100a6a13 ori s4,s4,256 -8000a174: 015cfab3 and s5,s9,s5 -8000a178: 02012423 sw zero,40(sp) -8000a17c: 02012223 sw zero,36(sp) -8000a180: 00012e23 sw zero,28(sp) -8000a184: 05812783 lw a5,88(sp) -8000a188: 00079463 bnez a5,8000a190 <_svfprintf_r+0x6fc> -8000a18c: 0510106f j 8000b9dc <_svfprintf_r+0x1f48> -8000a190: 02d00793 li a5,45 -8000a194: 0cf103a3 sb a5,199(sp) -8000a198: 00000d93 li s11,0 -8000a19c: 001a8a93 addi s5,s5,1 -8000a1a0: ad9ff06f j 80009c78 <_svfprintf_r+0x1e4> -8000a1a4: 0e410613 addi a2,sp,228 -8000a1a8: 000c0593 mv a1,s8 -8000a1ac: 000d0513 mv a0,s10 -8000a1b0: 5cd040ef jal ra,8000ef7c <__ssprint_r> -8000a1b4: 100510e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000a1b8: 0ec12783 lw a5,236(sp) -8000a1bc: 10c10893 addi a7,sp,268 -8000a1c0: b11ff06f j 80009cd0 <_svfprintf_r+0x23c> -8000a1c4: 0e812683 lw a3,232(sp) -8000a1c8: 00178c93 addi s9,a5,1 -8000a1cc: 02012783 lw a5,32(sp) -8000a1d0: 00100613 li a2,1 -8000a1d4: 0168a023 sw s6,0(a7) -8000a1d8: 00168493 addi s1,a3,1 -8000a1dc: 00888913 addi s2,a7,8 -8000a1e0: 36f658e3 bge a2,a5,8000ad50 <_svfprintf_r+0x12bc> -8000a1e4: 00100793 li a5,1 -8000a1e8: 00f8a223 sw a5,4(a7) -8000a1ec: 0f912623 sw s9,236(sp) -8000a1f0: 0e912423 sw s1,232(sp) -8000a1f4: 00700793 li a5,7 -8000a1f8: 4a97c0e3 blt a5,s1,8000ae98 <_svfprintf_r+0x1404> -8000a1fc: 02c12783 lw a5,44(sp) -8000a200: 03012703 lw a4,48(sp) -8000a204: 00148493 addi s1,s1,1 -8000a208: 00fc8cb3 add s9,s9,a5 -8000a20c: 00f92223 sw a5,4(s2) -8000a210: 00e92023 sw a4,0(s2) -8000a214: 0f912623 sw s9,236(sp) -8000a218: 0e912423 sw s1,232(sp) -8000a21c: 00700793 li a5,7 -8000a220: 00890913 addi s2,s2,8 -8000a224: 4897cce3 blt a5,s1,8000aebc <_svfprintf_r+0x1428> -8000a228: 0f012783 lw a5,240(sp) -8000a22c: 00148613 addi a2,s1,1 -8000a230: 0a010593 addi a1,sp,160 -8000a234: 0af12823 sw a5,176(sp) -8000a238: 0f412783 lw a5,244(sp) -8000a23c: 0b010513 addi a0,sp,176 -8000a240: 00c12e23 sw a2,28(sp) -8000a244: 0af12a23 sw a5,180(sp) -8000a248: 0f812783 lw a5,248(sp) -8000a24c: 0a012023 sw zero,160(sp) -8000a250: 0a012223 sw zero,164(sp) -8000a254: 0af12c23 sw a5,184(sp) -8000a258: 0fc12783 lw a5,252(sp) -8000a25c: 0a012423 sw zero,168(sp) -8000a260: 0a012623 sw zero,172(sp) -8000a264: 0af12e23 sw a5,188(sp) -8000a268: 744070ef jal ra,800119ac <__eqtf2> -8000a26c: 01c12603 lw a2,28(sp) -8000a270: 02012783 lw a5,32(sp) -8000a274: 00890893 addi a7,s2,8 -8000a278: 00060693 mv a3,a2 -8000a27c: fff78d93 addi s11,a5,-1 -8000a280: 2e050ce3 beqz a0,8000ad78 <_svfprintf_r+0x12e4> -8000a284: 001b0713 addi a4,s6,1 -8000a288: 01bc8cb3 add s9,s9,s11 -8000a28c: 00e92023 sw a4,0(s2) -8000a290: 01b92223 sw s11,4(s2) -8000a294: 0f912623 sw s9,236(sp) -8000a298: 0ec12423 sw a2,232(sp) -8000a29c: 00700793 li a5,7 -8000a2a0: 00c7d463 bge a5,a2,8000a2a8 <_svfprintf_r+0x814> -8000a2a4: 0180106f j 8000b2bc <_svfprintf_r+0x1828> -8000a2a8: 01090793 addi a5,s2,16 -8000a2ac: 00248693 addi a3,s1,2 -8000a2b0: 00088913 mv s2,a7 -8000a2b4: 00078893 mv a7,a5 -8000a2b8: 03812603 lw a2,56(sp) -8000a2bc: 0d410713 addi a4,sp,212 -8000a2c0: 00e92023 sw a4,0(s2) -8000a2c4: 019607b3 add a5,a2,s9 -8000a2c8: 00c92223 sw a2,4(s2) -8000a2cc: 0ef12623 sw a5,236(sp) -8000a2d0: 0ed12423 sw a3,232(sp) -8000a2d4: 00700713 li a4,7 -8000a2d8: a6d756e3 bge a4,a3,80009d44 <_svfprintf_r+0x2b0> -8000a2dc: 0e410613 addi a2,sp,228 -8000a2e0: 000c0593 mv a1,s8 -8000a2e4: 000d0513 mv a0,s10 -8000a2e8: 495040ef jal ra,8000ef7c <__ssprint_r> -8000a2ec: 7c051463 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000a2f0: 0ec12783 lw a5,236(sp) -8000a2f4: 10c10893 addi a7,sp,268 -8000a2f8: a4dff06f j 80009d44 <_svfprintf_r+0x2b0> -8000a2fc: 01000693 li a3,16 -8000a300: 0e812703 lw a4,232(sp) -8000a304: 0096c463 blt a3,s1,8000a30c <_svfprintf_r+0x878> -8000a308: 1210106f j 8000bc28 <_svfprintf_r+0x2194> -8000a30c: 800156b7 lui a3,0x80015 -8000a310: 34c68e93 addi t4,a3,844 # 8001534c <__BSS_END__+0xffffe710> -8000a314: 01000913 li s2,16 -8000a318: 00700a13 li s4,7 -8000a31c: 000e8b13 mv s6,t4 -8000a320: 00c0006f j 8000a32c <_svfprintf_r+0x898> -8000a324: ff048493 addi s1,s1,-16 -8000a328: 04995663 bge s2,s1,8000a374 <_svfprintf_r+0x8e0> -8000a32c: 01078793 addi a5,a5,16 -8000a330: 00170713 addi a4,a4,1 -8000a334: 0168a023 sw s6,0(a7) -8000a338: 0128a223 sw s2,4(a7) -8000a33c: 0ef12623 sw a5,236(sp) -8000a340: 0ee12423 sw a4,232(sp) -8000a344: 00888893 addi a7,a7,8 -8000a348: fcea5ee3 bge s4,a4,8000a324 <_svfprintf_r+0x890> -8000a34c: 0e410613 addi a2,sp,228 -8000a350: 000c0593 mv a1,s8 -8000a354: 000d0513 mv a0,s10 -8000a358: 425040ef jal ra,8000ef7c <__ssprint_r> -8000a35c: 74051c63 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000a360: ff048493 addi s1,s1,-16 -8000a364: 0ec12783 lw a5,236(sp) -8000a368: 0e812703 lw a4,232(sp) -8000a36c: 10c10893 addi a7,sp,268 -8000a370: fa994ee3 blt s2,s1,8000a32c <_svfprintf_r+0x898> -8000a374: 000b0e93 mv t4,s6 -8000a378: 009787b3 add a5,a5,s1 -8000a37c: 00170713 addi a4,a4,1 -8000a380: 01d8a023 sw t4,0(a7) -8000a384: 0098a223 sw s1,4(a7) -8000a388: 0ef12623 sw a5,236(sp) -8000a38c: 0ee12423 sw a4,232(sp) -8000a390: 00700693 li a3,7 -8000a394: 9ce6d0e3 bge a3,a4,80009d54 <_svfprintf_r+0x2c0> -8000a398: 0e410613 addi a2,sp,228 -8000a39c: 000c0593 mv a1,s8 -8000a3a0: 000d0513 mv a0,s10 -8000a3a4: 3d9040ef jal ra,8000ef7c <__ssprint_r> -8000a3a8: 70051663 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000a3ac: 0ec12783 lw a5,236(sp) -8000a3b0: 9a5ff06f j 80009d54 <_svfprintf_r+0x2c0> -8000a3b4: 01412783 lw a5,20(sp) -8000a3b8: 0c0103a3 sb zero,199(sp) -8000a3bc: 000c8893 mv a7,s9 -8000a3c0: 0007ab03 lw s6,0(a5) -8000a3c4: 00478913 addi s2,a5,4 -8000a3c8: 4e0b02e3 beqz s6,8000b0ac <_svfprintf_r+0x1618> -8000a3cc: fff00793 li a5,-1 -8000a3d0: 00fd9463 bne s11,a5,8000a3d8 <_svfprintf_r+0x944> -8000a3d4: 1fc0106f j 8000b5d0 <_svfprintf_r+0x1b3c> -8000a3d8: 000d8613 mv a2,s11 -8000a3dc: 00000593 li a1,0 -8000a3e0: 000b0513 mv a0,s6 -8000a3e4: 01912a23 sw s9,20(sp) -8000a3e8: f59fd0ef jal ra,80008340 -8000a3ec: 00a12823 sw a0,16(sp) -8000a3f0: 01412883 lw a7,20(sp) -8000a3f4: 00051463 bnez a0,8000a3fc <_svfprintf_r+0x968> -8000a3f8: 75c0106f j 8000bb54 <_svfprintf_r+0x20c0> -8000a3fc: 01012783 lw a5,16(sp) -8000a400: 01212a23 sw s2,20(sp) -8000a404: 00012823 sw zero,16(sp) -8000a408: 41678cb3 sub s9,a5,s6 -8000a40c: 0c714783 lbu a5,199(sp) -8000a410: fffcca93 not s5,s9 -8000a414: 41fada93 srai s5,s5,0x1f -8000a418: 02012423 sw zero,40(sp) -8000a41c: 02012223 sw zero,36(sp) -8000a420: 00012e23 sw zero,28(sp) -8000a424: 015cfab3 and s5,s9,s5 -8000a428: 00000d93 li s11,0 -8000a42c: 840786e3 beqz a5,80009c78 <_svfprintf_r+0x1e4> -8000a430: 001a8a93 addi s5,s5,1 -8000a434: 845ff06f j 80009c78 <_svfprintf_r+0x1e4> -8000a438: 01412703 lw a4,20(sp) -8000a43c: 000c8893 mv a7,s9 -8000a440: 0c0103a3 sb zero,199(sp) -8000a444: 00072783 lw a5,0(a4) -8000a448: 00470713 addi a4,a4,4 -8000a44c: 00e12a23 sw a4,20(sp) -8000a450: 14f10623 sb a5,332(sp) -8000a454: 00100a93 li s5,1 -8000a458: 00100c93 li s9,1 -8000a45c: 14c10b13 addi s6,sp,332 -8000a460: 805ff06f j 80009c64 <_svfprintf_r+0x1d0> -8000a464: 00044483 lbu s1,0(s0) -8000a468: 004a6a13 ori s4,s4,4 -8000a46c: f8cff06f j 80009bf8 <_svfprintf_r+0x164> -8000a470: 01412683 lw a3,20(sp) -8000a474: 020a7793 andi a5,s4,32 -8000a478: 000c8893 mv a7,s9 -8000a47c: 0006a703 lw a4,0(a3) -8000a480: 00468693 addi a3,a3,4 -8000a484: 00d12a23 sw a3,20(sp) -8000a488: 280790e3 bnez a5,8000af08 <_svfprintf_r+0x1474> -8000a48c: 010a7793 andi a5,s4,16 -8000a490: 00078463 beqz a5,8000a498 <_svfprintf_r+0xa04> -8000a494: 12c0106f j 8000b5c0 <_svfprintf_r+0x1b2c> -8000a498: 040a7793 andi a5,s4,64 -8000a49c: 00078463 beqz a5,8000a4a4 <_svfprintf_r+0xa10> -8000a4a0: 3d80106f j 8000b878 <_svfprintf_r+0x1de4> -8000a4a4: 200a7a13 andi s4,s4,512 -8000a4a8: 000a1463 bnez s4,8000a4b0 <_svfprintf_r+0xa1c> -8000a4ac: 1140106f j 8000b5c0 <_svfprintf_r+0x1b2c> -8000a4b0: 00c12783 lw a5,12(sp) -8000a4b4: 00040b13 mv s6,s0 -8000a4b8: 00f70023 sb a5,0(a4) -8000a4bc: 8d1ff06f j 80009d8c <_svfprintf_r+0x2f8> -8000a4c0: 00044483 lbu s1,0(s0) -8000a4c4: 06c00793 li a5,108 -8000a4c8: 38f48ee3 beq s1,a5,8000b064 <_svfprintf_r+0x15d0> -8000a4cc: 010a6a13 ori s4,s4,16 -8000a4d0: f28ff06f j 80009bf8 <_svfprintf_r+0x164> -8000a4d4: 01412703 lw a4,20(sp) -8000a4d8: ffff87b7 lui a5,0xffff8 -8000a4dc: 8307c793 xori a5,a5,-2000 -8000a4e0: 0cf11423 sh a5,200(sp) -8000a4e4: 00470793 addi a5,a4,4 -8000a4e8: 00f12a23 sw a5,20(sp) -8000a4ec: 00072903 lw s2,0(a4) -8000a4f0: 800157b7 lui a5,0x80015 -8000a4f4: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -8000a4f8: 000c8893 mv a7,s9 -8000a4fc: 02f12a23 sw a5,52(sp) -8000a500: 00000c93 li s9,0 -8000a504: 002a6b93 ori s7,s4,2 -8000a508: 00200793 li a5,2 -8000a50c: 07800493 li s1,120 -8000a510: 0c0103a3 sb zero,199(sp) -8000a514: fff00713 li a4,-1 -8000a518: 20ed8663 beq s11,a4,8000a724 <_svfprintf_r+0xc90> -8000a51c: 01996733 or a4,s2,s9 -8000a520: f7fbfa13 andi s4,s7,-129 -8000a524: 1e071e63 bnez a4,8000a720 <_svfprintf_r+0xc8c> -8000a528: 260d9463 bnez s11,8000a790 <_svfprintf_r+0xcfc> -8000a52c: 1c079063 bnez a5,8000a6ec <_svfprintf_r+0xc58> -8000a530: 001bfc93 andi s9,s7,1 -8000a534: 1b010b13 addi s6,sp,432 -8000a538: 1c0c90e3 bnez s9,8000aef8 <_svfprintf_r+0x1464> -8000a53c: 000c8a93 mv s5,s9 -8000a540: 01bcd463 bge s9,s11,8000a548 <_svfprintf_r+0xab4> -8000a544: 000d8a93 mv s5,s11 -8000a548: 0c714783 lbu a5,199(sp) -8000a54c: 00012823 sw zero,16(sp) -8000a550: 02012423 sw zero,40(sp) -8000a554: 02012223 sw zero,36(sp) -8000a558: 00012e23 sw zero,28(sp) -8000a55c: ec079ae3 bnez a5,8000a430 <_svfprintf_r+0x99c> -8000a560: f18ff06f j 80009c78 <_svfprintf_r+0x1e4> -8000a564: 000c8893 mv a7,s9 -8000a568: 010a6a13 ori s4,s4,16 -8000a56c: 020a7793 andi a5,s4,32 -8000a570: 06078ce3 beqz a5,8000ade8 <_svfprintf_r+0x1354> -8000a574: 01412783 lw a5,20(sp) -8000a578: 00778b13 addi s6,a5,7 -8000a57c: ff8b7b13 andi s6,s6,-8 -8000a580: 000b2903 lw s2,0(s6) -8000a584: 004b2c83 lw s9,4(s6) -8000a588: 008b0793 addi a5,s6,8 -8000a58c: 00f12a23 sw a5,20(sp) -8000a590: bffa7b93 andi s7,s4,-1025 -8000a594: 00000793 li a5,0 -8000a598: f79ff06f j 8000a510 <_svfprintf_r+0xa7c> -8000a59c: 00044483 lbu s1,0(s0) -8000a5a0: 06800793 li a5,104 -8000a5a4: 2cf488e3 beq s1,a5,8000b074 <_svfprintf_r+0x15e0> -8000a5a8: 040a6a13 ori s4,s4,64 -8000a5ac: e4cff06f j 80009bf8 <_svfprintf_r+0x164> -8000a5b0: 000c8893 mv a7,s9 -8000a5b4: 010a6b93 ori s7,s4,16 -8000a5b8: 020bf793 andi a5,s7,32 -8000a5bc: 04078ce3 beqz a5,8000ae14 <_svfprintf_r+0x1380> -8000a5c0: 01412783 lw a5,20(sp) -8000a5c4: 00778b13 addi s6,a5,7 -8000a5c8: ff8b7b13 andi s6,s6,-8 -8000a5cc: 008b0793 addi a5,s6,8 -8000a5d0: 00f12a23 sw a5,20(sp) -8000a5d4: 000b2903 lw s2,0(s6) -8000a5d8: 004b2c83 lw s9,4(s6) -8000a5dc: 00100793 li a5,1 -8000a5e0: f31ff06f j 8000a510 <_svfprintf_r+0xa7c> -8000a5e4: 00044483 lbu s1,0(s0) -8000a5e8: 008a6a13 ori s4,s4,8 -8000a5ec: e0cff06f j 80009bf8 <_svfprintf_r+0x164> -8000a5f0: 01412783 lw a5,20(sp) -8000a5f4: 00044483 lbu s1,0(s0) -8000a5f8: 0007a983 lw s3,0(a5) -8000a5fc: 00478793 addi a5,a5,4 -8000a600: 00f12a23 sw a5,20(sp) -8000a604: de09da63 bgez s3,80009bf8 <_svfprintf_r+0x164> -8000a608: 413009b3 neg s3,s3 -8000a60c: 004a6a13 ori s4,s4,4 -8000a610: de8ff06f j 80009bf8 <_svfprintf_r+0x164> -8000a614: 00044483 lbu s1,0(s0) -8000a618: 001a6a13 ori s4,s4,1 -8000a61c: ddcff06f j 80009bf8 <_svfprintf_r+0x164> -8000a620: 0c714783 lbu a5,199(sp) -8000a624: 00044483 lbu s1,0(s0) -8000a628: dc079863 bnez a5,80009bf8 <_svfprintf_r+0x164> -8000a62c: 02000793 li a5,32 -8000a630: 0cf103a3 sb a5,199(sp) -8000a634: dc4ff06f j 80009bf8 <_svfprintf_r+0x164> -8000a638: 00044483 lbu s1,0(s0) -8000a63c: 080a6a13 ori s4,s4,128 -8000a640: db8ff06f j 80009bf8 <_svfprintf_r+0x164> -8000a644: 00044483 lbu s1,0(s0) -8000a648: 00140713 addi a4,s0,1 -8000a64c: 01749463 bne s1,s7,8000a654 <_svfprintf_r+0xbc0> -8000a650: 5f50106f j 8000c444 <_svfprintf_r+0x29b0> -8000a654: fd048693 addi a3,s1,-48 -8000a658: 00070413 mv s0,a4 -8000a65c: 00000d93 li s11,0 -8000a660: d8daee63 bltu s5,a3,80009bfc <_svfprintf_r+0x168> -8000a664: 00044483 lbu s1,0(s0) -8000a668: 002d9793 slli a5,s11,0x2 -8000a66c: 01b787b3 add a5,a5,s11 -8000a670: 00179793 slli a5,a5,0x1 -8000a674: 00d78db3 add s11,a5,a3 -8000a678: fd048693 addi a3,s1,-48 -8000a67c: 00140413 addi s0,s0,1 -8000a680: fedaf2e3 bgeu s5,a3,8000a664 <_svfprintf_r+0xbd0> -8000a684: d78ff06f j 80009bfc <_svfprintf_r+0x168> -8000a688: 02b00793 li a5,43 -8000a68c: 00044483 lbu s1,0(s0) -8000a690: 0cf103a3 sb a5,199(sp) -8000a694: d64ff06f j 80009bf8 <_svfprintf_r+0x164> -8000a698: 000c8893 mv a7,s9 -8000a69c: 010a6a13 ori s4,s4,16 -8000a6a0: 020a7793 andi a5,s4,32 -8000a6a4: 7a078063 beqz a5,8000ae44 <_svfprintf_r+0x13b0> -8000a6a8: 01412783 lw a5,20(sp) -8000a6ac: 00778b13 addi s6,a5,7 -8000a6b0: ff8b7b13 andi s6,s6,-8 -8000a6b4: 004b2783 lw a5,4(s6) -8000a6b8: 000b2903 lw s2,0(s6) -8000a6bc: 008b0713 addi a4,s6,8 -8000a6c0: 00e12a23 sw a4,20(sp) -8000a6c4: 00078c93 mv s9,a5 -8000a6c8: 7a07c663 bltz a5,8000ae74 <_svfprintf_r+0x13e0> -8000a6cc: fff00793 li a5,-1 -8000a6d0: 000a0b93 mv s7,s4 -8000a6d4: 02fd8463 beq s11,a5,8000a6fc <_svfprintf_r+0xc68> -8000a6d8: 019967b3 or a5,s2,s9 -8000a6dc: f7fa7b93 andi s7,s4,-129 -8000a6e0: 00079e63 bnez a5,8000a6fc <_svfprintf_r+0xc68> -8000a6e4: 020d9263 bnez s11,8000a708 <_svfprintf_r+0xc74> -8000a6e8: 000b8a13 mv s4,s7 -8000a6ec: 00000d93 li s11,0 -8000a6f0: 00000c93 li s9,0 -8000a6f4: 1b010b13 addi s6,sp,432 -8000a6f8: e45ff06f j 8000a53c <_svfprintf_r+0xaa8> -8000a6fc: 400c96e3 bnez s9,8000b308 <_svfprintf_r+0x1874> -8000a700: 00900793 li a5,9 -8000a704: 4127e2e3 bltu a5,s2,8000b308 <_svfprintf_r+0x1874> -8000a708: 03090913 addi s2,s2,48 -8000a70c: 1b2107a3 sb s2,431(sp) -8000a710: 000b8a13 mv s4,s7 -8000a714: 00100c93 li s9,1 -8000a718: 1af10b13 addi s6,sp,431 -8000a71c: e21ff06f j 8000a53c <_svfprintf_r+0xaa8> -8000a720: 000a0b93 mv s7,s4 -8000a724: 00100713 li a4,1 -8000a728: fce78ae3 beq a5,a4,8000a6fc <_svfprintf_r+0xc68> -8000a72c: 00200713 li a4,2 -8000a730: 06e78c63 beq a5,a4,8000a7a8 <_svfprintf_r+0xd14> -8000a734: 1b010b13 addi s6,sp,432 -8000a738: 01dc9713 slli a4,s9,0x1d -8000a73c: 00797793 andi a5,s2,7 -8000a740: 00395913 srli s2,s2,0x3 -8000a744: 03078793 addi a5,a5,48 -8000a748: 01276933 or s2,a4,s2 -8000a74c: 003cdc93 srli s9,s9,0x3 -8000a750: fefb0fa3 sb a5,-1(s6) -8000a754: 01996733 or a4,s2,s9 -8000a758: 000b0613 mv a2,s6 -8000a75c: fffb0b13 addi s6,s6,-1 -8000a760: fc071ce3 bnez a4,8000a738 <_svfprintf_r+0xca4> -8000a764: 001bf693 andi a3,s7,1 -8000a768: 06068a63 beqz a3,8000a7dc <_svfprintf_r+0xd48> -8000a76c: 03000693 li a3,48 -8000a770: 06d78663 beq a5,a3,8000a7dc <_svfprintf_r+0xd48> -8000a774: ffe60613 addi a2,a2,-2 -8000a778: 1b010793 addi a5,sp,432 -8000a77c: fedb0fa3 sb a3,-1(s6) -8000a780: 40c78cb3 sub s9,a5,a2 -8000a784: 000b8a13 mv s4,s7 -8000a788: 00060b13 mv s6,a2 -8000a78c: db1ff06f j 8000a53c <_svfprintf_r+0xaa8> -8000a790: 00100713 li a4,1 -8000a794: 00e79463 bne a5,a4,8000a79c <_svfprintf_r+0xd08> -8000a798: 1710106f j 8000c108 <_svfprintf_r+0x2674> -8000a79c: 00200713 li a4,2 -8000a7a0: 000a0b93 mv s7,s4 -8000a7a4: f8e798e3 bne a5,a4,8000a734 <_svfprintf_r+0xca0> -8000a7a8: 03412683 lw a3,52(sp) -8000a7ac: 1b010b13 addi s6,sp,432 -8000a7b0: 00f97793 andi a5,s2,15 -8000a7b4: 00f687b3 add a5,a3,a5 -8000a7b8: 0007c703 lbu a4,0(a5) -8000a7bc: 00495913 srli s2,s2,0x4 -8000a7c0: 01cc9793 slli a5,s9,0x1c -8000a7c4: 0127e933 or s2,a5,s2 -8000a7c8: 004cdc93 srli s9,s9,0x4 -8000a7cc: feeb0fa3 sb a4,-1(s6) -8000a7d0: 019967b3 or a5,s2,s9 -8000a7d4: fffb0b13 addi s6,s6,-1 -8000a7d8: fc079ce3 bnez a5,8000a7b0 <_svfprintf_r+0xd1c> -8000a7dc: 1b010793 addi a5,sp,432 -8000a7e0: 41678cb3 sub s9,a5,s6 -8000a7e4: 000b8a13 mv s4,s7 -8000a7e8: d55ff06f j 8000a53c <_svfprintf_r+0xaa8> -8000a7ec: 06500693 li a3,101 -8000a7f0: 9c96dae3 bge a3,s1,8000a1c4 <_svfprintf_r+0x730> -8000a7f4: 0f012683 lw a3,240(sp) -8000a7f8: 0a010593 addi a1,sp,160 -8000a7fc: 0b010513 addi a0,sp,176 -8000a800: 0ad12823 sw a3,176(sp) -8000a804: 0f412683 lw a3,244(sp) -8000a808: 05112223 sw a7,68(sp) -8000a80c: 04f12023 sw a5,64(sp) -8000a810: 0ad12a23 sw a3,180(sp) -8000a814: 0f812683 lw a3,248(sp) -8000a818: 0a012023 sw zero,160(sp) -8000a81c: 0a012223 sw zero,164(sp) -8000a820: 0ad12c23 sw a3,184(sp) -8000a824: 0fc12683 lw a3,252(sp) -8000a828: 0a012423 sw zero,168(sp) -8000a82c: 0a012623 sw zero,172(sp) -8000a830: 0ad12e23 sw a3,188(sp) -8000a834: 178070ef jal ra,800119ac <__eqtf2> -8000a838: 04012783 lw a5,64(sp) -8000a83c: 04412883 lw a7,68(sp) -8000a840: 38051c63 bnez a0,8000abd8 <_svfprintf_r+0x1144> -8000a844: 0e812703 lw a4,232(sp) -8000a848: 800156b7 lui a3,0x80015 -8000a84c: ca868693 addi a3,a3,-856 # 80014ca8 <__BSS_END__+0xffffe06c> -8000a850: 00d8a023 sw a3,0(a7) -8000a854: 00178793 addi a5,a5,1 -8000a858: 00100693 li a3,1 -8000a85c: 00170713 addi a4,a4,1 -8000a860: 00d8a223 sw a3,4(a7) -8000a864: 0ef12623 sw a5,236(sp) -8000a868: 0ee12423 sw a4,232(sp) -8000a86c: 00700693 li a3,7 -8000a870: 00888893 addi a7,a7,8 -8000a874: 44e6cce3 blt a3,a4,8000b4cc <_svfprintf_r+0x1a38> -8000a878: 0cc12703 lw a4,204(sp) -8000a87c: 02012683 lw a3,32(sp) -8000a880: 66d75063 bge a4,a3,8000aee0 <_svfprintf_r+0x144c> -8000a884: 03012703 lw a4,48(sp) -8000a888: 02c12683 lw a3,44(sp) -8000a88c: 00888893 addi a7,a7,8 -8000a890: fee8ac23 sw a4,-8(a7) -8000a894: 0e812703 lw a4,232(sp) -8000a898: 00d787b3 add a5,a5,a3 -8000a89c: fed8ae23 sw a3,-4(a7) -8000a8a0: 00170713 addi a4,a4,1 -8000a8a4: 0ef12623 sw a5,236(sp) -8000a8a8: 0ee12423 sw a4,232(sp) -8000a8ac: 00700693 li a3,7 -8000a8b0: 76e6cc63 blt a3,a4,8000b028 <_svfprintf_r+0x1594> -8000a8b4: 02012703 lw a4,32(sp) -8000a8b8: fff70493 addi s1,a4,-1 -8000a8bc: c8905463 blez s1,80009d44 <_svfprintf_r+0x2b0> -8000a8c0: 01000693 li a3,16 -8000a8c4: 0e812703 lw a4,232(sp) -8000a8c8: 4296d2e3 bge a3,s1,8000b4ec <_svfprintf_r+0x1a58> -8000a8cc: 01000913 li s2,16 -8000a8d0: 00700c93 li s9,7 -8000a8d4: 00c0006f j 8000a8e0 <_svfprintf_r+0xe4c> -8000a8d8: ff048493 addi s1,s1,-16 -8000a8dc: 409958e3 bge s2,s1,8000b4ec <_svfprintf_r+0x1a58> -8000a8e0: 00812683 lw a3,8(sp) -8000a8e4: 01078793 addi a5,a5,16 -8000a8e8: 00170713 addi a4,a4,1 -8000a8ec: 00d8a023 sw a3,0(a7) -8000a8f0: 0128a223 sw s2,4(a7) -8000a8f4: 0ef12623 sw a5,236(sp) -8000a8f8: 0ee12423 sw a4,232(sp) +800099d0 <_svfprintf_r>: +800099d0: e1010113 addi sp,sp,-496 +800099d4: 1e112623 sw ra,492(sp) +800099d8: 1f212023 sw s2,480(sp) +800099dc: 1d812423 sw s8,456(sp) +800099e0: 1da12023 sw s10,448(sp) +800099e4: 00058c13 mv s8,a1 +800099e8: 00060913 mv s2,a2 +800099ec: 00d12a23 sw a3,20(sp) +800099f0: 1e812423 sw s0,488(sp) +800099f4: 1e912223 sw s1,484(sp) +800099f8: 1d312e23 sw s3,476(sp) +800099fc: 1d412c23 sw s4,472(sp) +80009a00: 1d512a23 sw s5,468(sp) +80009a04: 1d612823 sw s6,464(sp) +80009a08: 1d712623 sw s7,460(sp) +80009a0c: 1d912223 sw s9,452(sp) +80009a10: 1bb12e23 sw s11,444(sp) +80009a14: 00050d13 mv s10,a0 +80009a18: ecdfd0ef jal ra,800078e4 <_localeconv_r> +80009a1c: 00052783 lw a5,0(a0) +80009a20: 00078513 mv a0,a5 +80009a24: 02f12823 sw a5,48(sp) +80009a28: e75ff0ef jal ra,8000989c +80009a2c: 00cc5703 lhu a4,12(s8) +80009a30: 0e012823 sw zero,240(sp) +80009a34: 0e012a23 sw zero,244(sp) +80009a38: 0e012c23 sw zero,248(sp) +80009a3c: 0e012e23 sw zero,252(sp) +80009a40: 08077713 andi a4,a4,128 +80009a44: 02a12623 sw a0,44(sp) +80009a48: 00070863 beqz a4,80009a58 <_svfprintf_r+0x88> +80009a4c: 010c2703 lw a4,16(s8) +80009a50: 00071463 bnez a4,80009a58 <_svfprintf_r+0x88> +80009a54: 56c0106f j 8000afc0 <_svfprintf_r+0x15f0> +80009a58: 10c10793 addi a5,sp,268 +80009a5c: 80015737 lui a4,0x80015 +80009a60: 0ef12223 sw a5,228(sp) +80009a64: 00078893 mv a7,a5 +80009a68: 10870793 addi a5,a4,264 # 80015108 <__BSS_END__+0xffffe4cc> +80009a6c: 80015737 lui a4,0x80015 +80009a70: 00f12c23 sw a5,24(sp) +80009a74: 00090b13 mv s6,s2 +80009a78: 28470793 addi a5,a4,644 # 80015284 <__BSS_END__+0xffffe648> +80009a7c: 00f12423 sw a5,8(sp) +80009a80: 000b4783 lbu a5,0(s6) +80009a84: 0e012623 sw zero,236(sp) +80009a88: 0e012423 sw zero,232(sp) +80009a8c: 02012023 sw zero,32(sp) +80009a90: 02012a23 sw zero,52(sp) +80009a94: 02012c23 sw zero,56(sp) +80009a98: 02012e23 sw zero,60(sp) +80009a9c: 04012423 sw zero,72(sp) +80009aa0: 04012623 sw zero,76(sp) +80009aa4: 00012623 sw zero,12(sp) +80009aa8: 22078463 beqz a5,80009cd0 <_svfprintf_r+0x300> +80009aac: 000b0413 mv s0,s6 +80009ab0: 02500693 li a3,37 +80009ab4: 2cd78463 beq a5,a3,80009d7c <_svfprintf_r+0x3ac> +80009ab8: 00144783 lbu a5,1(s0) +80009abc: 00140413 addi s0,s0,1 +80009ac0: fe079ae3 bnez a5,80009ab4 <_svfprintf_r+0xe4> +80009ac4: 416404b3 sub s1,s0,s6 +80009ac8: 21640463 beq s0,s6,80009cd0 <_svfprintf_r+0x300> +80009acc: 0ec12683 lw a3,236(sp) +80009ad0: 0e812783 lw a5,232(sp) +80009ad4: 0168a023 sw s6,0(a7) +80009ad8: 009686b3 add a3,a3,s1 +80009adc: 00178793 addi a5,a5,1 +80009ae0: 0098a223 sw s1,4(a7) +80009ae4: 0ed12623 sw a3,236(sp) +80009ae8: 0ef12423 sw a5,232(sp) +80009aec: 00700693 li a3,7 +80009af0: 00888893 addi a7,a7,8 +80009af4: 28f6cc63 blt a3,a5,80009d8c <_svfprintf_r+0x3bc> +80009af8: 00c12703 lw a4,12(sp) +80009afc: 00044783 lbu a5,0(s0) +80009b00: 00970733 add a4,a4,s1 +80009b04: 00e12623 sw a4,12(sp) +80009b08: 1c078463 beqz a5,80009cd0 <_svfprintf_r+0x300> +80009b0c: 00144483 lbu s1,1(s0) +80009b10: 0c0103a3 sb zero,199(sp) +80009b14: 00140413 addi s0,s0,1 +80009b18: fff00d93 li s11,-1 +80009b1c: 00000993 li s3,0 +80009b20: 00000a13 li s4,0 +80009b24: 05a00913 li s2,90 +80009b28: 00900a93 li s5,9 +80009b2c: 02a00b93 li s7,42 +80009b30: 00088c93 mv s9,a7 +80009b34: 00140413 addi s0,s0,1 +80009b38: fe048793 addi a5,s1,-32 # 7fffffe0 <__BSS_END__+0xfffe93a4> +80009b3c: 04f96463 bltu s2,a5,80009b84 <_svfprintf_r+0x1b4> +80009b40: 01812703 lw a4,24(sp) +80009b44: 00279793 slli a5,a5,0x2 +80009b48: 00e787b3 add a5,a5,a4 +80009b4c: 0007a783 lw a5,0(a5) +80009b50: 00078067 jr a5 +80009b54: 00000993 li s3,0 +80009b58: fd048693 addi a3,s1,-48 +80009b5c: 00044483 lbu s1,0(s0) +80009b60: 00299793 slli a5,s3,0x2 +80009b64: 013787b3 add a5,a5,s3 +80009b68: 00179793 slli a5,a5,0x1 +80009b6c: 00f689b3 add s3,a3,a5 +80009b70: fd048693 addi a3,s1,-48 +80009b74: 00140413 addi s0,s0,1 +80009b78: fedaf2e3 bgeu s5,a3,80009b5c <_svfprintf_r+0x18c> +80009b7c: fe048793 addi a5,s1,-32 +80009b80: fcf970e3 bgeu s2,a5,80009b40 <_svfprintf_r+0x170> +80009b84: 000c8893 mv a7,s9 +80009b88: 14048463 beqz s1,80009cd0 <_svfprintf_r+0x300> +80009b8c: 14910623 sb s1,332(sp) +80009b90: 0c0103a3 sb zero,199(sp) +80009b94: 00100a93 li s5,1 +80009b98: 00100c93 li s9,1 +80009b9c: 14c10b13 addi s6,sp,332 +80009ba0: 00012823 sw zero,16(sp) +80009ba4: 00000d93 li s11,0 +80009ba8: 02012423 sw zero,40(sp) +80009bac: 02012223 sw zero,36(sp) +80009bb0: 00012e23 sw zero,28(sp) +80009bb4: 002a7b93 andi s7,s4,2 +80009bb8: 000b8463 beqz s7,80009bc0 <_svfprintf_r+0x1f0> +80009bbc: 002a8a93 addi s5,s5,2 +80009bc0: 084a7913 andi s2,s4,132 +80009bc4: 0ec12783 lw a5,236(sp) +80009bc8: 00091663 bnez s2,80009bd4 <_svfprintf_r+0x204> +80009bcc: 41598833 sub a6,s3,s5 +80009bd0: 63004ce3 bgtz a6,8000aa08 <_svfprintf_r+0x1038> +80009bd4: 0c714683 lbu a3,199(sp) +80009bd8: 02068a63 beqz a3,80009c0c <_svfprintf_r+0x23c> +80009bdc: 0e812683 lw a3,232(sp) +80009be0: 0c710613 addi a2,sp,199 +80009be4: 00c8a023 sw a2,0(a7) +80009be8: 00178793 addi a5,a5,1 +80009bec: 00100613 li a2,1 +80009bf0: 00168693 addi a3,a3,1 +80009bf4: 00c8a223 sw a2,4(a7) +80009bf8: 0ef12623 sw a5,236(sp) +80009bfc: 0ed12423 sw a3,232(sp) +80009c00: 00700613 li a2,7 +80009c04: 00888893 addi a7,a7,8 +80009c08: 4cd64c63 blt a2,a3,8000a0e0 <_svfprintf_r+0x710> +80009c0c: 020b8a63 beqz s7,80009c40 <_svfprintf_r+0x270> +80009c10: 0e812683 lw a3,232(sp) +80009c14: 0c810613 addi a2,sp,200 +80009c18: 00c8a023 sw a2,0(a7) +80009c1c: 00278793 addi a5,a5,2 +80009c20: 00200613 li a2,2 +80009c24: 00168693 addi a3,a3,1 +80009c28: 00c8a223 sw a2,4(a7) +80009c2c: 0ef12623 sw a5,236(sp) +80009c30: 0ed12423 sw a3,232(sp) +80009c34: 00700613 li a2,7 +80009c38: 00888893 addi a7,a7,8 +80009c3c: 6ad64ce3 blt a2,a3,8000aaf4 <_svfprintf_r+0x1124> +80009c40: 08000693 li a3,128 +80009c44: 42d900e3 beq s2,a3,8000a864 <_svfprintf_r+0xe94> +80009c48: 419d8db3 sub s11,s11,s9 +80009c4c: 4db04ee3 bgtz s11,8000a928 <_svfprintf_r+0xf58> +80009c50: 100a7693 andi a3,s4,256 +80009c54: 2c069ae3 bnez a3,8000a728 <_svfprintf_r+0xd58> +80009c58: 0e812703 lw a4,232(sp) +80009c5c: 019787b3 add a5,a5,s9 +80009c60: 0168a023 sw s6,0(a7) +80009c64: 00170713 addi a4,a4,1 +80009c68: 0198a223 sw s9,4(a7) +80009c6c: 0ef12623 sw a5,236(sp) +80009c70: 0ee12423 sw a4,232(sp) +80009c74: 00700693 li a3,7 +80009c78: 5ae6c063 blt a3,a4,8000a218 <_svfprintf_r+0x848> +80009c7c: 00888893 addi a7,a7,8 +80009c80: 004a7a13 andi s4,s4,4 +80009c84: 000a0663 beqz s4,80009c90 <_svfprintf_r+0x2c0> +80009c88: 415984b3 sub s1,s3,s5 +80009c8c: 5a904663 bgtz s1,8000a238 <_svfprintf_r+0x868> +80009c90: 0159d463 bge s3,s5,80009c98 <_svfprintf_r+0x2c8> +80009c94: 000a8993 mv s3,s5 +80009c98: 00c12703 lw a4,12(sp) +80009c9c: 01370733 add a4,a4,s3 +80009ca0: 00e12623 sw a4,12(sp) +80009ca4: 52079ce3 bnez a5,8000a9dc <_svfprintf_r+0x100c> +80009ca8: 01012783 lw a5,16(sp) +80009cac: 0e012423 sw zero,232(sp) +80009cb0: 00078863 beqz a5,80009cc0 <_svfprintf_r+0x2f0> +80009cb4: 01012583 lw a1,16(sp) +80009cb8: 000d0513 mv a0,s10 +80009cbc: c55fa0ef jal ra,80004910 <_free_r> +80009cc0: 10c10893 addi a7,sp,268 +80009cc4: 00040b13 mv s6,s0 +80009cc8: 000b4783 lbu a5,0(s6) +80009ccc: de0790e3 bnez a5,80009aac <_svfprintf_r+0xdc> +80009cd0: 0ec12783 lw a5,236(sp) +80009cd4: 00078463 beqz a5,80009cdc <_svfprintf_r+0x30c> +80009cd8: 3450106f j 8000b81c <_svfprintf_r+0x1e4c> +80009cdc: 00cc5703 lhu a4,12(s8) +80009ce0: 04077713 andi a4,a4,64 +80009ce4: 00070463 beqz a4,80009cec <_svfprintf_r+0x31c> +80009ce8: 3f80206f j 8000c0e0 <_svfprintf_r+0x2710> +80009cec: 1ec12083 lw ra,492(sp) +80009cf0: 1e812403 lw s0,488(sp) +80009cf4: 00c12503 lw a0,12(sp) +80009cf8: 1e412483 lw s1,484(sp) +80009cfc: 1e012903 lw s2,480(sp) +80009d00: 1dc12983 lw s3,476(sp) +80009d04: 1d812a03 lw s4,472(sp) +80009d08: 1d412a83 lw s5,468(sp) +80009d0c: 1d012b03 lw s6,464(sp) +80009d10: 1cc12b83 lw s7,460(sp) +80009d14: 1c812c03 lw s8,456(sp) +80009d18: 1c412c83 lw s9,452(sp) +80009d1c: 1c012d03 lw s10,448(sp) +80009d20: 1bc12d83 lw s11,444(sp) +80009d24: 1f010113 addi sp,sp,496 +80009d28: 00008067 ret +80009d2c: 000d0513 mv a0,s10 +80009d30: bb5fd0ef jal ra,800078e4 <_localeconv_r> +80009d34: 00452783 lw a5,4(a0) +80009d38: 00078513 mv a0,a5 +80009d3c: 04f12623 sw a5,76(sp) +80009d40: b5dff0ef jal ra,8000989c +80009d44: 00050793 mv a5,a0 +80009d48: 000d0513 mv a0,s10 +80009d4c: 00078493 mv s1,a5 +80009d50: 04f12423 sw a5,72(sp) +80009d54: b91fd0ef jal ra,800078e4 <_localeconv_r> +80009d58: 00852783 lw a5,8(a0) +80009d5c: 02f12e23 sw a5,60(sp) +80009d60: 00048463 beqz s1,80009d68 <_svfprintf_r+0x398> +80009d64: 1640106f j 8000aec8 <_svfprintf_r+0x14f8> +80009d68: 00044483 lbu s1,0(s0) +80009d6c: dc9ff06f j 80009b34 <_svfprintf_r+0x164> +80009d70: 00044483 lbu s1,0(s0) +80009d74: 020a6a13 ori s4,s4,32 +80009d78: dbdff06f j 80009b34 <_svfprintf_r+0x164> +80009d7c: 416404b3 sub s1,s0,s6 +80009d80: d56416e3 bne s0,s6,80009acc <_svfprintf_r+0xfc> +80009d84: 00044783 lbu a5,0(s0) +80009d88: d81ff06f j 80009b08 <_svfprintf_r+0x138> +80009d8c: 0e410613 addi a2,sp,228 +80009d90: 000c0593 mv a1,s8 +80009d94: 000d0513 mv a0,s10 +80009d98: 120050ef jal ra,8000eeb8 <__ssprint_r> +80009d9c: f40510e3 bnez a0,80009cdc <_svfprintf_r+0x30c> +80009da0: 10c10893 addi a7,sp,268 +80009da4: d55ff06f j 80009af8 <_svfprintf_r+0x128> +80009da8: 008a7793 andi a5,s4,8 +80009dac: 000c8893 mv a7,s9 +80009db0: 00078463 beqz a5,80009db8 <_svfprintf_r+0x3e8> +80009db4: 0a80106f j 8000ae5c <_svfprintf_r+0x148c> +80009db8: 01412783 lw a5,20(sp) +80009dbc: 0b010513 addi a0,sp,176 +80009dc0: 01912823 sw s9,16(sp) +80009dc4: 00778793 addi a5,a5,7 +80009dc8: ff87f793 andi a5,a5,-8 +80009dcc: 0007a583 lw a1,0(a5) +80009dd0: 0047a603 lw a2,4(a5) +80009dd4: 00878793 addi a5,a5,8 +80009dd8: 00f12a23 sw a5,20(sp) +80009ddc: 5e80a0ef jal ra,800143c4 <__extenddftf2> +80009de0: 0b012783 lw a5,176(sp) +80009de4: 01012883 lw a7,16(sp) +80009de8: 0ef12823 sw a5,240(sp) +80009dec: 0b412783 lw a5,180(sp) +80009df0: 0ef12a23 sw a5,244(sp) +80009df4: 0b812783 lw a5,184(sp) +80009df8: 0ef12c23 sw a5,248(sp) +80009dfc: 0bc12783 lw a5,188(sp) +80009e00: 0ef12e23 sw a5,252(sp) +80009e04: 0f010513 addi a0,sp,240 +80009e08: 01112823 sw a7,16(sp) +80009e0c: a6dfd0ef jal ra,80007878 <_ldcheck> +80009e10: 0ca12623 sw a0,204(sp) +80009e14: 00200793 li a5,2 +80009e18: 01012883 lw a7,16(sp) +80009e1c: 00f51463 bne a0,a5,80009e24 <_svfprintf_r+0x454> +80009e20: 6580106f j 8000b478 <_svfprintf_r+0x1aa8> +80009e24: 00100793 li a5,1 +80009e28: 00f51463 bne a0,a5,80009e30 <_svfprintf_r+0x460> +80009e2c: 0750106f j 8000b6a0 <_svfprintf_r+0x1cd0> +80009e30: 06100793 li a5,97 +80009e34: 00f49463 bne s1,a5,80009e3c <_svfprintf_r+0x46c> +80009e38: 19c0206f j 8000bfd4 <_svfprintf_r+0x2604> +80009e3c: 04100793 li a5,65 +80009e40: 00f49463 bne s1,a5,80009e48 <_svfprintf_r+0x478> +80009e44: 52d0106f j 8000bb70 <_svfprintf_r+0x21a0> +80009e48: fdf4fb93 andi s7,s1,-33 +80009e4c: fff00793 li a5,-1 +80009e50: 05712a23 sw s7,84(sp) +80009e54: 00fd9463 bne s11,a5,80009e5c <_svfprintf_r+0x48c> +80009e58: 2150106f j 8000b86c <_svfprintf_r+0x1e9c> +80009e5c: 04700793 li a5,71 +80009e60: 00fb9463 bne s7,a5,80009e68 <_svfprintf_r+0x498> +80009e64: 1e80206f j 8000c04c <_svfprintf_r+0x267c> +80009e68: 0fc12303 lw t1,252(sp) +80009e6c: 03412423 sw s4,40(sp) +80009e70: 0f012e03 lw t3,240(sp) +80009e74: 0f412e83 lw t4,244(sp) +80009e78: 0f812f03 lw t5,248(sp) +80009e7c: 100a6793 ori a5,s4,256 +80009e80: 00035463 bgez t1,80009e88 <_svfprintf_r+0x4b8> +80009e84: 39c0206f j 8000c220 <_svfprintf_r+0x2850> +80009e88: 04012c23 sw zero,88(sp) +80009e8c: 00078a13 mv s4,a5 +80009e90: 00012823 sw zero,16(sp) +80009e94: 04600793 li a5,70 +80009e98: 00fb9463 bne s7,a5,80009ea0 <_svfprintf_r+0x4d0> +80009e9c: 2b90106f j 8000b954 <_svfprintf_r+0x1f84> +80009ea0: 04500793 li a5,69 +80009ea4: 05112223 sw a7,68(sp) +80009ea8: 00fb8463 beq s7,a5,80009eb0 <_svfprintf_r+0x4e0> +80009eac: 33d0106f j 8000b9e8 <_svfprintf_r+0x2018> +80009eb0: 001d8913 addi s2,s11,1 +80009eb4: 0b010a93 addi s5,sp,176 +80009eb8: 00090693 mv a3,s2 +80009ebc: 0dc10813 addi a6,sp,220 +80009ec0: 0d010793 addi a5,sp,208 +80009ec4: 0cc10713 addi a4,sp,204 +80009ec8: 00200613 li a2,2 +80009ecc: 000a8593 mv a1,s5 +80009ed0: 000d0513 mv a0,s10 +80009ed4: 0bc12823 sw t3,176(sp) +80009ed8: 05c12023 sw t3,64(sp) +80009edc: 0bd12a23 sw t4,180(sp) +80009ee0: 03d12223 sw t4,36(sp) +80009ee4: 0be12c23 sw t5,184(sp) +80009ee8: 03e12023 sw t5,32(sp) +80009eec: 0a612e23 sw t1,188(sp) +80009ef0: 00612e23 sw t1,28(sp) +80009ef4: eecfc0ef jal ra,800065e0 <_ldtoa_r> +80009ef8: 01c12303 lw t1,28(sp) +80009efc: 02012f03 lw t5,32(sp) +80009f00: 02412e83 lw t4,36(sp) +80009f04: 04012e03 lw t3,64(sp) +80009f08: 04412883 lw a7,68(sp) +80009f0c: 00050b13 mv s6,a0 +80009f10: 01250933 add s2,a0,s2 +80009f14: 0a010c93 addi s9,sp,160 +80009f18: 000c8593 mv a1,s9 +80009f1c: 000a8513 mv a0,s5 +80009f20: 01112e23 sw a7,28(sp) +80009f24: 0bc12823 sw t3,176(sp) +80009f28: 0bd12a23 sw t4,180(sp) +80009f2c: 0be12c23 sw t5,184(sp) +80009f30: 0a612e23 sw t1,188(sp) +80009f34: 0a012023 sw zero,160(sp) +80009f38: 0a012223 sw zero,164(sp) +80009f3c: 0a012423 sw zero,168(sp) +80009f40: 0a012623 sw zero,172(sp) +80009f44: 1a5070ef jal ra,800118e8 <__eqtf2> +80009f48: 01c12883 lw a7,28(sp) +80009f4c: 00090713 mv a4,s2 +80009f50: 02050263 beqz a0,80009f74 <_svfprintf_r+0x5a4> +80009f54: 0dc12703 lw a4,220(sp) +80009f58: 01277e63 bgeu a4,s2,80009f74 <_svfprintf_r+0x5a4> +80009f5c: 03000693 li a3,48 +80009f60: 00170793 addi a5,a4,1 +80009f64: 0cf12e23 sw a5,220(sp) +80009f68: 00d70023 sb a3,0(a4) +80009f6c: 0dc12703 lw a4,220(sp) +80009f70: ff2768e3 bltu a4,s2,80009f60 <_svfprintf_r+0x590> +80009f74: 416707b3 sub a5,a4,s6 +80009f78: 02f12023 sw a5,32(sp) +80009f7c: 0cc12703 lw a4,204(sp) +80009f80: 04700793 li a5,71 +80009f84: 00e12e23 sw a4,28(sp) +80009f88: 05412703 lw a4,84(sp) +80009f8c: 00f71463 bne a4,a5,80009f94 <_svfprintf_r+0x5c4> +80009f90: 1150106f j 8000b8a4 <_svfprintf_r+0x1ed4> +80009f94: 05412703 lw a4,84(sp) +80009f98: 04600793 li a5,70 +80009f9c: 00f71463 bne a4,a5,80009fa4 <_svfprintf_r+0x5d4> +80009fa0: 34d0106f j 8000baec <_svfprintf_r+0x211c> +80009fa4: 01c12783 lw a5,28(sp) +80009fa8: 05412703 lw a4,84(sp) +80009fac: 04100593 li a1,65 +80009fb0: fff78793 addi a5,a5,-1 +80009fb4: 0cf12623 sw a5,204(sp) +80009fb8: 0ff4f693 andi a3,s1,255 +80009fbc: 00000613 li a2,0 +80009fc0: 00b71863 bne a4,a1,80009fd0 <_svfprintf_r+0x600> +80009fc4: 00f68693 addi a3,a3,15 +80009fc8: 0ff6f693 andi a3,a3,255 +80009fcc: 00100613 li a2,1 +80009fd0: 0cd10a23 sb a3,212(sp) +80009fd4: 02b00693 li a3,43 +80009fd8: 0007da63 bgez a5,80009fec <_svfprintf_r+0x61c> +80009fdc: 01c12703 lw a4,28(sp) +80009fe0: 00100793 li a5,1 +80009fe4: 02d00693 li a3,45 +80009fe8: 40e787b3 sub a5,a5,a4 +80009fec: 0cd10aa3 sb a3,213(sp) +80009ff0: 00900693 li a3,9 +80009ff4: 00f6c463 blt a3,a5,80009ffc <_svfprintf_r+0x62c> +80009ff8: 0f40206f j 8000c0ec <_svfprintf_r+0x271c> +80009ffc: 0e310813 addi a6,sp,227 +8000a000: 00080513 mv a0,a6 +8000a004: 00a00613 li a2,10 +8000a008: 06300e13 li t3,99 +8000a00c: 02c7e733 rem a4,a5,a2 +8000a010: 00050593 mv a1,a0 +8000a014: 00078693 mv a3,a5 +8000a018: fff50513 addi a0,a0,-1 +8000a01c: 03070713 addi a4,a4,48 +8000a020: fee58fa3 sb a4,-1(a1) +8000a024: 02c7c7b3 div a5,a5,a2 +8000a028: fede42e3 blt t3,a3,8000a00c <_svfprintf_r+0x63c> +8000a02c: 03078793 addi a5,a5,48 +8000a030: 0ff7f613 andi a2,a5,255 +8000a034: fec50fa3 sb a2,-1(a0) +8000a038: ffe58793 addi a5,a1,-2 +8000a03c: 0107e463 bltu a5,a6,8000a044 <_svfprintf_r+0x674> +8000a040: 3980206f j 8000c3d8 <_svfprintf_r+0x2a08> +8000a044: 0d610693 addi a3,sp,214 +8000a048: 0080006f j 8000a050 <_svfprintf_r+0x680> +8000a04c: 0007c603 lbu a2,0(a5) +8000a050: 00c68023 sb a2,0(a3) +8000a054: 00178793 addi a5,a5,1 +8000a058: 00168693 addi a3,a3,1 +8000a05c: ff0798e3 bne a5,a6,8000a04c <_svfprintf_r+0x67c> +8000a060: 0e510793 addi a5,sp,229 +8000a064: 40b787b3 sub a5,a5,a1 +8000a068: 0d610713 addi a4,sp,214 +8000a06c: 00f707b3 add a5,a4,a5 +8000a070: 0d410693 addi a3,sp,212 +8000a074: 40d787b3 sub a5,a5,a3 +8000a078: 02f12c23 sw a5,56(sp) +8000a07c: 02012703 lw a4,32(sp) +8000a080: 03812683 lw a3,56(sp) +8000a084: 00100793 li a5,1 +8000a088: 00d70cb3 add s9,a4,a3 +8000a08c: 00e7c463 blt a5,a4,8000a094 <_svfprintf_r+0x6c4> +8000a090: 2300206f j 8000c2c0 <_svfprintf_r+0x28f0> +8000a094: 02c12783 lw a5,44(sp) +8000a098: 00fc8cb3 add s9,s9,a5 +8000a09c: 02812783 lw a5,40(sp) +8000a0a0: fffcca93 not s5,s9 +8000a0a4: 41fada93 srai s5,s5,0x1f +8000a0a8: bff7fa13 andi s4,a5,-1025 +8000a0ac: 100a6a13 ori s4,s4,256 +8000a0b0: 015cfab3 and s5,s9,s5 +8000a0b4: 02012423 sw zero,40(sp) +8000a0b8: 02012223 sw zero,36(sp) +8000a0bc: 00012e23 sw zero,28(sp) +8000a0c0: 05812783 lw a5,88(sp) +8000a0c4: 00079463 bnez a5,8000a0cc <_svfprintf_r+0x6fc> +8000a0c8: 0510106f j 8000b918 <_svfprintf_r+0x1f48> +8000a0cc: 02d00793 li a5,45 +8000a0d0: 0cf103a3 sb a5,199(sp) +8000a0d4: 00000d93 li s11,0 +8000a0d8: 001a8a93 addi s5,s5,1 +8000a0dc: ad9ff06f j 80009bb4 <_svfprintf_r+0x1e4> +8000a0e0: 0e410613 addi a2,sp,228 +8000a0e4: 000c0593 mv a1,s8 +8000a0e8: 000d0513 mv a0,s10 +8000a0ec: 5cd040ef jal ra,8000eeb8 <__ssprint_r> +8000a0f0: 100510e3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a0f4: 0ec12783 lw a5,236(sp) +8000a0f8: 10c10893 addi a7,sp,268 +8000a0fc: b11ff06f j 80009c0c <_svfprintf_r+0x23c> +8000a100: 0e812683 lw a3,232(sp) +8000a104: 00178c93 addi s9,a5,1 +8000a108: 02012783 lw a5,32(sp) +8000a10c: 00100613 li a2,1 +8000a110: 0168a023 sw s6,0(a7) +8000a114: 00168493 addi s1,a3,1 +8000a118: 00888913 addi s2,a7,8 +8000a11c: 36f658e3 bge a2,a5,8000ac8c <_svfprintf_r+0x12bc> +8000a120: 00100793 li a5,1 +8000a124: 00f8a223 sw a5,4(a7) +8000a128: 0f912623 sw s9,236(sp) +8000a12c: 0e912423 sw s1,232(sp) +8000a130: 00700793 li a5,7 +8000a134: 4a97c0e3 blt a5,s1,8000add4 <_svfprintf_r+0x1404> +8000a138: 02c12783 lw a5,44(sp) +8000a13c: 03012703 lw a4,48(sp) +8000a140: 00148493 addi s1,s1,1 +8000a144: 00fc8cb3 add s9,s9,a5 +8000a148: 00f92223 sw a5,4(s2) +8000a14c: 00e92023 sw a4,0(s2) +8000a150: 0f912623 sw s9,236(sp) +8000a154: 0e912423 sw s1,232(sp) +8000a158: 00700793 li a5,7 +8000a15c: 00890913 addi s2,s2,8 +8000a160: 4897cce3 blt a5,s1,8000adf8 <_svfprintf_r+0x1428> +8000a164: 0f012783 lw a5,240(sp) +8000a168: 00148613 addi a2,s1,1 +8000a16c: 0a010593 addi a1,sp,160 +8000a170: 0af12823 sw a5,176(sp) +8000a174: 0f412783 lw a5,244(sp) +8000a178: 0b010513 addi a0,sp,176 +8000a17c: 00c12e23 sw a2,28(sp) +8000a180: 0af12a23 sw a5,180(sp) +8000a184: 0f812783 lw a5,248(sp) +8000a188: 0a012023 sw zero,160(sp) +8000a18c: 0a012223 sw zero,164(sp) +8000a190: 0af12c23 sw a5,184(sp) +8000a194: 0fc12783 lw a5,252(sp) +8000a198: 0a012423 sw zero,168(sp) +8000a19c: 0a012623 sw zero,172(sp) +8000a1a0: 0af12e23 sw a5,188(sp) +8000a1a4: 744070ef jal ra,800118e8 <__eqtf2> +8000a1a8: 01c12603 lw a2,28(sp) +8000a1ac: 02012783 lw a5,32(sp) +8000a1b0: 00890893 addi a7,s2,8 +8000a1b4: 00060693 mv a3,a2 +8000a1b8: fff78d93 addi s11,a5,-1 +8000a1bc: 2e050ce3 beqz a0,8000acb4 <_svfprintf_r+0x12e4> +8000a1c0: 001b0713 addi a4,s6,1 +8000a1c4: 01bc8cb3 add s9,s9,s11 +8000a1c8: 00e92023 sw a4,0(s2) +8000a1cc: 01b92223 sw s11,4(s2) +8000a1d0: 0f912623 sw s9,236(sp) +8000a1d4: 0ec12423 sw a2,232(sp) +8000a1d8: 00700793 li a5,7 +8000a1dc: 00c7d463 bge a5,a2,8000a1e4 <_svfprintf_r+0x814> +8000a1e0: 0180106f j 8000b1f8 <_svfprintf_r+0x1828> +8000a1e4: 01090793 addi a5,s2,16 +8000a1e8: 00248693 addi a3,s1,2 +8000a1ec: 00088913 mv s2,a7 +8000a1f0: 00078893 mv a7,a5 +8000a1f4: 03812603 lw a2,56(sp) +8000a1f8: 0d410713 addi a4,sp,212 +8000a1fc: 00e92023 sw a4,0(s2) +8000a200: 019607b3 add a5,a2,s9 +8000a204: 00c92223 sw a2,4(s2) +8000a208: 0ef12623 sw a5,236(sp) +8000a20c: 0ed12423 sw a3,232(sp) +8000a210: 00700713 li a4,7 +8000a214: a6d756e3 bge a4,a3,80009c80 <_svfprintf_r+0x2b0> +8000a218: 0e410613 addi a2,sp,228 +8000a21c: 000c0593 mv a1,s8 +8000a220: 000d0513 mv a0,s10 +8000a224: 495040ef jal ra,8000eeb8 <__ssprint_r> +8000a228: 7c051463 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a22c: 0ec12783 lw a5,236(sp) +8000a230: 10c10893 addi a7,sp,268 +8000a234: a4dff06f j 80009c80 <_svfprintf_r+0x2b0> +8000a238: 01000693 li a3,16 +8000a23c: 0e812703 lw a4,232(sp) +8000a240: 0096c463 blt a3,s1,8000a248 <_svfprintf_r+0x878> +8000a244: 1210106f j 8000bb64 <_svfprintf_r+0x2194> +8000a248: 800156b7 lui a3,0x80015 +8000a24c: 27468e93 addi t4,a3,628 # 80015274 <__BSS_END__+0xffffe638> +8000a250: 01000913 li s2,16 +8000a254: 00700a13 li s4,7 +8000a258: 000e8b13 mv s6,t4 +8000a25c: 00c0006f j 8000a268 <_svfprintf_r+0x898> +8000a260: ff048493 addi s1,s1,-16 +8000a264: 04995663 bge s2,s1,8000a2b0 <_svfprintf_r+0x8e0> +8000a268: 01078793 addi a5,a5,16 +8000a26c: 00170713 addi a4,a4,1 +8000a270: 0168a023 sw s6,0(a7) +8000a274: 0128a223 sw s2,4(a7) +8000a278: 0ef12623 sw a5,236(sp) +8000a27c: 0ee12423 sw a4,232(sp) +8000a280: 00888893 addi a7,a7,8 +8000a284: fcea5ee3 bge s4,a4,8000a260 <_svfprintf_r+0x890> +8000a288: 0e410613 addi a2,sp,228 +8000a28c: 000c0593 mv a1,s8 +8000a290: 000d0513 mv a0,s10 +8000a294: 425040ef jal ra,8000eeb8 <__ssprint_r> +8000a298: 74051c63 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a29c: ff048493 addi s1,s1,-16 +8000a2a0: 0ec12783 lw a5,236(sp) +8000a2a4: 0e812703 lw a4,232(sp) +8000a2a8: 10c10893 addi a7,sp,268 +8000a2ac: fa994ee3 blt s2,s1,8000a268 <_svfprintf_r+0x898> +8000a2b0: 000b0e93 mv t4,s6 +8000a2b4: 009787b3 add a5,a5,s1 +8000a2b8: 00170713 addi a4,a4,1 +8000a2bc: 01d8a023 sw t4,0(a7) +8000a2c0: 0098a223 sw s1,4(a7) +8000a2c4: 0ef12623 sw a5,236(sp) +8000a2c8: 0ee12423 sw a4,232(sp) +8000a2cc: 00700693 li a3,7 +8000a2d0: 9ce6d0e3 bge a3,a4,80009c90 <_svfprintf_r+0x2c0> +8000a2d4: 0e410613 addi a2,sp,228 +8000a2d8: 000c0593 mv a1,s8 +8000a2dc: 000d0513 mv a0,s10 +8000a2e0: 3d9040ef jal ra,8000eeb8 <__ssprint_r> +8000a2e4: 70051663 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a2e8: 0ec12783 lw a5,236(sp) +8000a2ec: 9a5ff06f j 80009c90 <_svfprintf_r+0x2c0> +8000a2f0: 01412783 lw a5,20(sp) +8000a2f4: 0c0103a3 sb zero,199(sp) +8000a2f8: 000c8893 mv a7,s9 +8000a2fc: 0007ab03 lw s6,0(a5) +8000a300: 00478913 addi s2,a5,4 +8000a304: 4e0b02e3 beqz s6,8000afe8 <_svfprintf_r+0x1618> +8000a308: fff00793 li a5,-1 +8000a30c: 00fd9463 bne s11,a5,8000a314 <_svfprintf_r+0x944> +8000a310: 1fc0106f j 8000b50c <_svfprintf_r+0x1b3c> +8000a314: 000d8613 mv a2,s11 +8000a318: 00000593 li a1,0 +8000a31c: 000b0513 mv a0,s6 +8000a320: 01912a23 sw s9,20(sp) +8000a324: f59fd0ef jal ra,8000827c +8000a328: 00a12823 sw a0,16(sp) +8000a32c: 01412883 lw a7,20(sp) +8000a330: 00051463 bnez a0,8000a338 <_svfprintf_r+0x968> +8000a334: 75c0106f j 8000ba90 <_svfprintf_r+0x20c0> +8000a338: 01012783 lw a5,16(sp) +8000a33c: 01212a23 sw s2,20(sp) +8000a340: 00012823 sw zero,16(sp) +8000a344: 41678cb3 sub s9,a5,s6 +8000a348: 0c714783 lbu a5,199(sp) +8000a34c: fffcca93 not s5,s9 +8000a350: 41fada93 srai s5,s5,0x1f +8000a354: 02012423 sw zero,40(sp) +8000a358: 02012223 sw zero,36(sp) +8000a35c: 00012e23 sw zero,28(sp) +8000a360: 015cfab3 and s5,s9,s5 +8000a364: 00000d93 li s11,0 +8000a368: 840786e3 beqz a5,80009bb4 <_svfprintf_r+0x1e4> +8000a36c: 001a8a93 addi s5,s5,1 +8000a370: 845ff06f j 80009bb4 <_svfprintf_r+0x1e4> +8000a374: 01412703 lw a4,20(sp) +8000a378: 000c8893 mv a7,s9 +8000a37c: 0c0103a3 sb zero,199(sp) +8000a380: 00072783 lw a5,0(a4) +8000a384: 00470713 addi a4,a4,4 +8000a388: 00e12a23 sw a4,20(sp) +8000a38c: 14f10623 sb a5,332(sp) +8000a390: 00100a93 li s5,1 +8000a394: 00100c93 li s9,1 +8000a398: 14c10b13 addi s6,sp,332 +8000a39c: 805ff06f j 80009ba0 <_svfprintf_r+0x1d0> +8000a3a0: 00044483 lbu s1,0(s0) +8000a3a4: 004a6a13 ori s4,s4,4 +8000a3a8: f8cff06f j 80009b34 <_svfprintf_r+0x164> +8000a3ac: 01412683 lw a3,20(sp) +8000a3b0: 020a7793 andi a5,s4,32 +8000a3b4: 000c8893 mv a7,s9 +8000a3b8: 0006a703 lw a4,0(a3) +8000a3bc: 00468693 addi a3,a3,4 +8000a3c0: 00d12a23 sw a3,20(sp) +8000a3c4: 280790e3 bnez a5,8000ae44 <_svfprintf_r+0x1474> +8000a3c8: 010a7793 andi a5,s4,16 +8000a3cc: 00078463 beqz a5,8000a3d4 <_svfprintf_r+0xa04> +8000a3d0: 12c0106f j 8000b4fc <_svfprintf_r+0x1b2c> +8000a3d4: 040a7793 andi a5,s4,64 +8000a3d8: 00078463 beqz a5,8000a3e0 <_svfprintf_r+0xa10> +8000a3dc: 3d80106f j 8000b7b4 <_svfprintf_r+0x1de4> +8000a3e0: 200a7a13 andi s4,s4,512 +8000a3e4: 000a1463 bnez s4,8000a3ec <_svfprintf_r+0xa1c> +8000a3e8: 1140106f j 8000b4fc <_svfprintf_r+0x1b2c> +8000a3ec: 00c12783 lw a5,12(sp) +8000a3f0: 00040b13 mv s6,s0 +8000a3f4: 00f70023 sb a5,0(a4) +8000a3f8: 8d1ff06f j 80009cc8 <_svfprintf_r+0x2f8> +8000a3fc: 00044483 lbu s1,0(s0) +8000a400: 06c00793 li a5,108 +8000a404: 38f48ee3 beq s1,a5,8000afa0 <_svfprintf_r+0x15d0> +8000a408: 010a6a13 ori s4,s4,16 +8000a40c: f28ff06f j 80009b34 <_svfprintf_r+0x164> +8000a410: 01412703 lw a4,20(sp) +8000a414: ffff87b7 lui a5,0xffff8 +8000a418: 8307c793 xori a5,a5,-2000 +8000a41c: 0cf11423 sh a5,200(sp) +8000a420: 00470793 addi a5,a4,4 +8000a424: 00f12a23 sw a5,20(sp) +8000a428: 00072903 lw s2,0(a4) +8000a42c: 800157b7 lui a5,0x80015 +8000a430: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +8000a434: 000c8893 mv a7,s9 +8000a438: 02f12a23 sw a5,52(sp) +8000a43c: 00000c93 li s9,0 +8000a440: 002a6b93 ori s7,s4,2 +8000a444: 00200793 li a5,2 +8000a448: 07800493 li s1,120 +8000a44c: 0c0103a3 sb zero,199(sp) +8000a450: fff00713 li a4,-1 +8000a454: 20ed8663 beq s11,a4,8000a660 <_svfprintf_r+0xc90> +8000a458: 01996733 or a4,s2,s9 +8000a45c: f7fbfa13 andi s4,s7,-129 +8000a460: 1e071e63 bnez a4,8000a65c <_svfprintf_r+0xc8c> +8000a464: 260d9463 bnez s11,8000a6cc <_svfprintf_r+0xcfc> +8000a468: 1c079063 bnez a5,8000a628 <_svfprintf_r+0xc58> +8000a46c: 001bfc93 andi s9,s7,1 +8000a470: 1b010b13 addi s6,sp,432 +8000a474: 1c0c90e3 bnez s9,8000ae34 <_svfprintf_r+0x1464> +8000a478: 000c8a93 mv s5,s9 +8000a47c: 01bcd463 bge s9,s11,8000a484 <_svfprintf_r+0xab4> +8000a480: 000d8a93 mv s5,s11 +8000a484: 0c714783 lbu a5,199(sp) +8000a488: 00012823 sw zero,16(sp) +8000a48c: 02012423 sw zero,40(sp) +8000a490: 02012223 sw zero,36(sp) +8000a494: 00012e23 sw zero,28(sp) +8000a498: ec079ae3 bnez a5,8000a36c <_svfprintf_r+0x99c> +8000a49c: f18ff06f j 80009bb4 <_svfprintf_r+0x1e4> +8000a4a0: 000c8893 mv a7,s9 +8000a4a4: 010a6a13 ori s4,s4,16 +8000a4a8: 020a7793 andi a5,s4,32 +8000a4ac: 06078ce3 beqz a5,8000ad24 <_svfprintf_r+0x1354> +8000a4b0: 01412783 lw a5,20(sp) +8000a4b4: 00778b13 addi s6,a5,7 +8000a4b8: ff8b7b13 andi s6,s6,-8 +8000a4bc: 000b2903 lw s2,0(s6) +8000a4c0: 004b2c83 lw s9,4(s6) +8000a4c4: 008b0793 addi a5,s6,8 +8000a4c8: 00f12a23 sw a5,20(sp) +8000a4cc: bffa7b93 andi s7,s4,-1025 +8000a4d0: 00000793 li a5,0 +8000a4d4: f79ff06f j 8000a44c <_svfprintf_r+0xa7c> +8000a4d8: 00044483 lbu s1,0(s0) +8000a4dc: 06800793 li a5,104 +8000a4e0: 2cf488e3 beq s1,a5,8000afb0 <_svfprintf_r+0x15e0> +8000a4e4: 040a6a13 ori s4,s4,64 +8000a4e8: e4cff06f j 80009b34 <_svfprintf_r+0x164> +8000a4ec: 000c8893 mv a7,s9 +8000a4f0: 010a6b93 ori s7,s4,16 +8000a4f4: 020bf793 andi a5,s7,32 +8000a4f8: 04078ce3 beqz a5,8000ad50 <_svfprintf_r+0x1380> +8000a4fc: 01412783 lw a5,20(sp) +8000a500: 00778b13 addi s6,a5,7 +8000a504: ff8b7b13 andi s6,s6,-8 +8000a508: 008b0793 addi a5,s6,8 +8000a50c: 00f12a23 sw a5,20(sp) +8000a510: 000b2903 lw s2,0(s6) +8000a514: 004b2c83 lw s9,4(s6) +8000a518: 00100793 li a5,1 +8000a51c: f31ff06f j 8000a44c <_svfprintf_r+0xa7c> +8000a520: 00044483 lbu s1,0(s0) +8000a524: 008a6a13 ori s4,s4,8 +8000a528: e0cff06f j 80009b34 <_svfprintf_r+0x164> +8000a52c: 01412783 lw a5,20(sp) +8000a530: 00044483 lbu s1,0(s0) +8000a534: 0007a983 lw s3,0(a5) +8000a538: 00478793 addi a5,a5,4 +8000a53c: 00f12a23 sw a5,20(sp) +8000a540: de09da63 bgez s3,80009b34 <_svfprintf_r+0x164> +8000a544: 413009b3 neg s3,s3 +8000a548: 004a6a13 ori s4,s4,4 +8000a54c: de8ff06f j 80009b34 <_svfprintf_r+0x164> +8000a550: 00044483 lbu s1,0(s0) +8000a554: 001a6a13 ori s4,s4,1 +8000a558: ddcff06f j 80009b34 <_svfprintf_r+0x164> +8000a55c: 0c714783 lbu a5,199(sp) +8000a560: 00044483 lbu s1,0(s0) +8000a564: dc079863 bnez a5,80009b34 <_svfprintf_r+0x164> +8000a568: 02000793 li a5,32 +8000a56c: 0cf103a3 sb a5,199(sp) +8000a570: dc4ff06f j 80009b34 <_svfprintf_r+0x164> +8000a574: 00044483 lbu s1,0(s0) +8000a578: 080a6a13 ori s4,s4,128 +8000a57c: db8ff06f j 80009b34 <_svfprintf_r+0x164> +8000a580: 00044483 lbu s1,0(s0) +8000a584: 00140713 addi a4,s0,1 +8000a588: 01749463 bne s1,s7,8000a590 <_svfprintf_r+0xbc0> +8000a58c: 5f50106f j 8000c380 <_svfprintf_r+0x29b0> +8000a590: fd048693 addi a3,s1,-48 +8000a594: 00070413 mv s0,a4 +8000a598: 00000d93 li s11,0 +8000a59c: d8daee63 bltu s5,a3,80009b38 <_svfprintf_r+0x168> +8000a5a0: 00044483 lbu s1,0(s0) +8000a5a4: 002d9793 slli a5,s11,0x2 +8000a5a8: 01b787b3 add a5,a5,s11 +8000a5ac: 00179793 slli a5,a5,0x1 +8000a5b0: 00d78db3 add s11,a5,a3 +8000a5b4: fd048693 addi a3,s1,-48 +8000a5b8: 00140413 addi s0,s0,1 +8000a5bc: fedaf2e3 bgeu s5,a3,8000a5a0 <_svfprintf_r+0xbd0> +8000a5c0: d78ff06f j 80009b38 <_svfprintf_r+0x168> +8000a5c4: 02b00793 li a5,43 +8000a5c8: 00044483 lbu s1,0(s0) +8000a5cc: 0cf103a3 sb a5,199(sp) +8000a5d0: d64ff06f j 80009b34 <_svfprintf_r+0x164> +8000a5d4: 000c8893 mv a7,s9 +8000a5d8: 010a6a13 ori s4,s4,16 +8000a5dc: 020a7793 andi a5,s4,32 +8000a5e0: 7a078063 beqz a5,8000ad80 <_svfprintf_r+0x13b0> +8000a5e4: 01412783 lw a5,20(sp) +8000a5e8: 00778b13 addi s6,a5,7 +8000a5ec: ff8b7b13 andi s6,s6,-8 +8000a5f0: 004b2783 lw a5,4(s6) +8000a5f4: 000b2903 lw s2,0(s6) +8000a5f8: 008b0713 addi a4,s6,8 +8000a5fc: 00e12a23 sw a4,20(sp) +8000a600: 00078c93 mv s9,a5 +8000a604: 7a07c663 bltz a5,8000adb0 <_svfprintf_r+0x13e0> +8000a608: fff00793 li a5,-1 +8000a60c: 000a0b93 mv s7,s4 +8000a610: 02fd8463 beq s11,a5,8000a638 <_svfprintf_r+0xc68> +8000a614: 019967b3 or a5,s2,s9 +8000a618: f7fa7b93 andi s7,s4,-129 +8000a61c: 00079e63 bnez a5,8000a638 <_svfprintf_r+0xc68> +8000a620: 020d9263 bnez s11,8000a644 <_svfprintf_r+0xc74> +8000a624: 000b8a13 mv s4,s7 +8000a628: 00000d93 li s11,0 +8000a62c: 00000c93 li s9,0 +8000a630: 1b010b13 addi s6,sp,432 +8000a634: e45ff06f j 8000a478 <_svfprintf_r+0xaa8> +8000a638: 400c96e3 bnez s9,8000b244 <_svfprintf_r+0x1874> +8000a63c: 00900793 li a5,9 +8000a640: 4127e2e3 bltu a5,s2,8000b244 <_svfprintf_r+0x1874> +8000a644: 03090913 addi s2,s2,48 +8000a648: 1b2107a3 sb s2,431(sp) +8000a64c: 000b8a13 mv s4,s7 +8000a650: 00100c93 li s9,1 +8000a654: 1af10b13 addi s6,sp,431 +8000a658: e21ff06f j 8000a478 <_svfprintf_r+0xaa8> +8000a65c: 000a0b93 mv s7,s4 +8000a660: 00100713 li a4,1 +8000a664: fce78ae3 beq a5,a4,8000a638 <_svfprintf_r+0xc68> +8000a668: 00200713 li a4,2 +8000a66c: 06e78c63 beq a5,a4,8000a6e4 <_svfprintf_r+0xd14> +8000a670: 1b010b13 addi s6,sp,432 +8000a674: 01dc9713 slli a4,s9,0x1d +8000a678: 00797793 andi a5,s2,7 +8000a67c: 00395913 srli s2,s2,0x3 +8000a680: 03078793 addi a5,a5,48 +8000a684: 01276933 or s2,a4,s2 +8000a688: 003cdc93 srli s9,s9,0x3 +8000a68c: fefb0fa3 sb a5,-1(s6) +8000a690: 01996733 or a4,s2,s9 +8000a694: 000b0613 mv a2,s6 +8000a698: fffb0b13 addi s6,s6,-1 +8000a69c: fc071ce3 bnez a4,8000a674 <_svfprintf_r+0xca4> +8000a6a0: 001bf693 andi a3,s7,1 +8000a6a4: 06068a63 beqz a3,8000a718 <_svfprintf_r+0xd48> +8000a6a8: 03000693 li a3,48 +8000a6ac: 06d78663 beq a5,a3,8000a718 <_svfprintf_r+0xd48> +8000a6b0: ffe60613 addi a2,a2,-2 +8000a6b4: 1b010793 addi a5,sp,432 +8000a6b8: fedb0fa3 sb a3,-1(s6) +8000a6bc: 40c78cb3 sub s9,a5,a2 +8000a6c0: 000b8a13 mv s4,s7 +8000a6c4: 00060b13 mv s6,a2 +8000a6c8: db1ff06f j 8000a478 <_svfprintf_r+0xaa8> +8000a6cc: 00100713 li a4,1 +8000a6d0: 00e79463 bne a5,a4,8000a6d8 <_svfprintf_r+0xd08> +8000a6d4: 1710106f j 8000c044 <_svfprintf_r+0x2674> +8000a6d8: 00200713 li a4,2 +8000a6dc: 000a0b93 mv s7,s4 +8000a6e0: f8e798e3 bne a5,a4,8000a670 <_svfprintf_r+0xca0> +8000a6e4: 03412683 lw a3,52(sp) +8000a6e8: 1b010b13 addi s6,sp,432 +8000a6ec: 00f97793 andi a5,s2,15 +8000a6f0: 00f687b3 add a5,a3,a5 +8000a6f4: 0007c703 lbu a4,0(a5) +8000a6f8: 00495913 srli s2,s2,0x4 +8000a6fc: 01cc9793 slli a5,s9,0x1c +8000a700: 0127e933 or s2,a5,s2 +8000a704: 004cdc93 srli s9,s9,0x4 +8000a708: feeb0fa3 sb a4,-1(s6) +8000a70c: 019967b3 or a5,s2,s9 +8000a710: fffb0b13 addi s6,s6,-1 +8000a714: fc079ce3 bnez a5,8000a6ec <_svfprintf_r+0xd1c> +8000a718: 1b010793 addi a5,sp,432 +8000a71c: 41678cb3 sub s9,a5,s6 +8000a720: 000b8a13 mv s4,s7 +8000a724: d55ff06f j 8000a478 <_svfprintf_r+0xaa8> +8000a728: 06500693 li a3,101 +8000a72c: 9c96dae3 bge a3,s1,8000a100 <_svfprintf_r+0x730> +8000a730: 0f012683 lw a3,240(sp) +8000a734: 0a010593 addi a1,sp,160 +8000a738: 0b010513 addi a0,sp,176 +8000a73c: 0ad12823 sw a3,176(sp) +8000a740: 0f412683 lw a3,244(sp) +8000a744: 05112223 sw a7,68(sp) +8000a748: 04f12023 sw a5,64(sp) +8000a74c: 0ad12a23 sw a3,180(sp) +8000a750: 0f812683 lw a3,248(sp) +8000a754: 0a012023 sw zero,160(sp) +8000a758: 0a012223 sw zero,164(sp) +8000a75c: 0ad12c23 sw a3,184(sp) +8000a760: 0fc12683 lw a3,252(sp) +8000a764: 0a012423 sw zero,168(sp) +8000a768: 0a012623 sw zero,172(sp) +8000a76c: 0ad12e23 sw a3,188(sp) +8000a770: 178070ef jal ra,800118e8 <__eqtf2> +8000a774: 04012783 lw a5,64(sp) +8000a778: 04412883 lw a7,68(sp) +8000a77c: 38051c63 bnez a0,8000ab14 <_svfprintf_r+0x1144> +8000a780: 0e812703 lw a4,232(sp) +8000a784: 800156b7 lui a3,0x80015 +8000a788: bd468693 addi a3,a3,-1068 # 80014bd4 <__BSS_END__+0xffffdf98> +8000a78c: 00d8a023 sw a3,0(a7) +8000a790: 00178793 addi a5,a5,1 +8000a794: 00100693 li a3,1 +8000a798: 00170713 addi a4,a4,1 +8000a79c: 00d8a223 sw a3,4(a7) +8000a7a0: 0ef12623 sw a5,236(sp) +8000a7a4: 0ee12423 sw a4,232(sp) +8000a7a8: 00700693 li a3,7 +8000a7ac: 00888893 addi a7,a7,8 +8000a7b0: 44e6cce3 blt a3,a4,8000b408 <_svfprintf_r+0x1a38> +8000a7b4: 0cc12703 lw a4,204(sp) +8000a7b8: 02012683 lw a3,32(sp) +8000a7bc: 66d75063 bge a4,a3,8000ae1c <_svfprintf_r+0x144c> +8000a7c0: 03012703 lw a4,48(sp) +8000a7c4: 02c12683 lw a3,44(sp) +8000a7c8: 00888893 addi a7,a7,8 +8000a7cc: fee8ac23 sw a4,-8(a7) +8000a7d0: 0e812703 lw a4,232(sp) +8000a7d4: 00d787b3 add a5,a5,a3 +8000a7d8: fed8ae23 sw a3,-4(a7) +8000a7dc: 00170713 addi a4,a4,1 +8000a7e0: 0ef12623 sw a5,236(sp) +8000a7e4: 0ee12423 sw a4,232(sp) +8000a7e8: 00700693 li a3,7 +8000a7ec: 76e6cc63 blt a3,a4,8000af64 <_svfprintf_r+0x1594> +8000a7f0: 02012703 lw a4,32(sp) +8000a7f4: fff70493 addi s1,a4,-1 +8000a7f8: c8905463 blez s1,80009c80 <_svfprintf_r+0x2b0> +8000a7fc: 01000693 li a3,16 +8000a800: 0e812703 lw a4,232(sp) +8000a804: 4296d2e3 bge a3,s1,8000b428 <_svfprintf_r+0x1a58> +8000a808: 01000913 li s2,16 +8000a80c: 00700c93 li s9,7 +8000a810: 00c0006f j 8000a81c <_svfprintf_r+0xe4c> +8000a814: ff048493 addi s1,s1,-16 +8000a818: 409958e3 bge s2,s1,8000b428 <_svfprintf_r+0x1a58> +8000a81c: 00812683 lw a3,8(sp) +8000a820: 01078793 addi a5,a5,16 +8000a824: 00170713 addi a4,a4,1 +8000a828: 00d8a023 sw a3,0(a7) +8000a82c: 0128a223 sw s2,4(a7) +8000a830: 0ef12623 sw a5,236(sp) +8000a834: 0ee12423 sw a4,232(sp) +8000a838: 00888893 addi a7,a7,8 +8000a83c: fcecdce3 bge s9,a4,8000a814 <_svfprintf_r+0xe44> +8000a840: 0e410613 addi a2,sp,228 +8000a844: 000c0593 mv a1,s8 +8000a848: 000d0513 mv a0,s10 +8000a84c: 66c040ef jal ra,8000eeb8 <__ssprint_r> +8000a850: 1a051063 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a854: 0ec12783 lw a5,236(sp) +8000a858: 0e812703 lw a4,232(sp) +8000a85c: 10c10893 addi a7,sp,268 +8000a860: fb5ff06f j 8000a814 <_svfprintf_r+0xe44> +8000a864: 41598933 sub s2,s3,s5 +8000a868: bf205063 blez s2,80009c48 <_svfprintf_r+0x278> +8000a86c: 01000613 li a2,16 +8000a870: 0e812683 lw a3,232(sp) +8000a874: 07265463 bge a2,s2,8000a8dc <_svfprintf_r+0xf0c> +8000a878: 01000e13 li t3,16 +8000a87c: 00700b93 li s7,7 +8000a880: 00c0006f j 8000a88c <_svfprintf_r+0xebc> +8000a884: ff090913 addi s2,s2,-16 +8000a888: 052e5a63 bge t3,s2,8000a8dc <_svfprintf_r+0xf0c> +8000a88c: 00812703 lw a4,8(sp) +8000a890: 01078793 addi a5,a5,16 +8000a894: 00168693 addi a3,a3,1 +8000a898: 00e8a023 sw a4,0(a7) +8000a89c: 01c8a223 sw t3,4(a7) +8000a8a0: 0ef12623 sw a5,236(sp) +8000a8a4: 0ed12423 sw a3,232(sp) +8000a8a8: 00888893 addi a7,a7,8 +8000a8ac: fcdbdce3 bge s7,a3,8000a884 <_svfprintf_r+0xeb4> +8000a8b0: 0e410613 addi a2,sp,228 +8000a8b4: 000c0593 mv a1,s8 +8000a8b8: 000d0513 mv a0,s10 +8000a8bc: 5fc040ef jal ra,8000eeb8 <__ssprint_r> +8000a8c0: 12051863 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a8c4: 01000e13 li t3,16 +8000a8c8: ff090913 addi s2,s2,-16 +8000a8cc: 0ec12783 lw a5,236(sp) +8000a8d0: 0e812683 lw a3,232(sp) +8000a8d4: 10c10893 addi a7,sp,268 +8000a8d8: fb2e4ae3 blt t3,s2,8000a88c <_svfprintf_r+0xebc> +8000a8dc: 00812703 lw a4,8(sp) +8000a8e0: 012787b3 add a5,a5,s2 +8000a8e4: 00168693 addi a3,a3,1 +8000a8e8: 00e8a023 sw a4,0(a7) +8000a8ec: 0128a223 sw s2,4(a7) +8000a8f0: 0ef12623 sw a5,236(sp) +8000a8f4: 0ed12423 sw a3,232(sp) +8000a8f8: 00700613 li a2,7 8000a8fc: 00888893 addi a7,a7,8 -8000a900: fcecdce3 bge s9,a4,8000a8d8 <_svfprintf_r+0xe44> +8000a900: b4d65463 bge a2,a3,80009c48 <_svfprintf_r+0x278> 8000a904: 0e410613 addi a2,sp,228 8000a908: 000c0593 mv a1,s8 8000a90c: 000d0513 mv a0,s10 -8000a910: 66c040ef jal ra,8000ef7c <__ssprint_r> -8000a914: 1a051063 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000a918: 0ec12783 lw a5,236(sp) -8000a91c: 0e812703 lw a4,232(sp) +8000a910: 5a8040ef jal ra,8000eeb8 <__ssprint_r> +8000a914: 0c051e63 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a918: 419d8db3 sub s11,s11,s9 +8000a91c: 0ec12783 lw a5,236(sp) 8000a920: 10c10893 addi a7,sp,268 -8000a924: fb5ff06f j 8000a8d8 <_svfprintf_r+0xe44> -8000a928: 41598933 sub s2,s3,s5 -8000a92c: bf205063 blez s2,80009d0c <_svfprintf_r+0x278> -8000a930: 01000613 li a2,16 -8000a934: 0e812683 lw a3,232(sp) -8000a938: 07265463 bge a2,s2,8000a9a0 <_svfprintf_r+0xf0c> -8000a93c: 01000e13 li t3,16 -8000a940: 00700b93 li s7,7 -8000a944: 00c0006f j 8000a950 <_svfprintf_r+0xebc> -8000a948: ff090913 addi s2,s2,-16 -8000a94c: 052e5a63 bge t3,s2,8000a9a0 <_svfprintf_r+0xf0c> -8000a950: 00812703 lw a4,8(sp) -8000a954: 01078793 addi a5,a5,16 -8000a958: 00168693 addi a3,a3,1 -8000a95c: 00e8a023 sw a4,0(a7) -8000a960: 01c8a223 sw t3,4(a7) -8000a964: 0ef12623 sw a5,236(sp) -8000a968: 0ed12423 sw a3,232(sp) -8000a96c: 00888893 addi a7,a7,8 -8000a970: fcdbdce3 bge s7,a3,8000a948 <_svfprintf_r+0xeb4> -8000a974: 0e410613 addi a2,sp,228 -8000a978: 000c0593 mv a1,s8 -8000a97c: 000d0513 mv a0,s10 -8000a980: 5fc040ef jal ra,8000ef7c <__ssprint_r> -8000a984: 12051863 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000a988: 01000e13 li t3,16 -8000a98c: ff090913 addi s2,s2,-16 -8000a990: 0ec12783 lw a5,236(sp) -8000a994: 0e812683 lw a3,232(sp) -8000a998: 10c10893 addi a7,sp,268 -8000a99c: fb2e4ae3 blt t3,s2,8000a950 <_svfprintf_r+0xebc> -8000a9a0: 00812703 lw a4,8(sp) -8000a9a4: 012787b3 add a5,a5,s2 -8000a9a8: 00168693 addi a3,a3,1 -8000a9ac: 00e8a023 sw a4,0(a7) -8000a9b0: 0128a223 sw s2,4(a7) -8000a9b4: 0ef12623 sw a5,236(sp) -8000a9b8: 0ed12423 sw a3,232(sp) -8000a9bc: 00700613 li a2,7 -8000a9c0: 00888893 addi a7,a7,8 -8000a9c4: b4d65463 bge a2,a3,80009d0c <_svfprintf_r+0x278> -8000a9c8: 0e410613 addi a2,sp,228 -8000a9cc: 000c0593 mv a1,s8 -8000a9d0: 000d0513 mv a0,s10 -8000a9d4: 5a8040ef jal ra,8000ef7c <__ssprint_r> -8000a9d8: 0c051e63 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000a9dc: 419d8db3 sub s11,s11,s9 -8000a9e0: 0ec12783 lw a5,236(sp) -8000a9e4: 10c10893 addi a7,sp,268 -8000a9e8: b3b05663 blez s11,80009d14 <_svfprintf_r+0x280> -8000a9ec: 01000613 li a2,16 -8000a9f0: 0e812683 lw a3,232(sp) -8000a9f4: 07b65263 bge a2,s11,8000aa58 <_svfprintf_r+0xfc4> -8000a9f8: 01000b93 li s7,16 -8000a9fc: 00700913 li s2,7 -8000aa00: 00c0006f j 8000aa0c <_svfprintf_r+0xf78> -8000aa04: ff0d8d93 addi s11,s11,-16 -8000aa08: 05bbd863 bge s7,s11,8000aa58 <_svfprintf_r+0xfc4> -8000aa0c: 00812703 lw a4,8(sp) -8000aa10: 01078793 addi a5,a5,16 -8000aa14: 00168693 addi a3,a3,1 -8000aa18: 00e8a023 sw a4,0(a7) -8000aa1c: 0178a223 sw s7,4(a7) -8000aa20: 0ef12623 sw a5,236(sp) -8000aa24: 0ed12423 sw a3,232(sp) -8000aa28: 00888893 addi a7,a7,8 -8000aa2c: fcd95ce3 bge s2,a3,8000aa04 <_svfprintf_r+0xf70> -8000aa30: 0e410613 addi a2,sp,228 -8000aa34: 000c0593 mv a1,s8 -8000aa38: 000d0513 mv a0,s10 -8000aa3c: 540040ef jal ra,8000ef7c <__ssprint_r> -8000aa40: 06051a63 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000aa44: ff0d8d93 addi s11,s11,-16 -8000aa48: 0ec12783 lw a5,236(sp) -8000aa4c: 0e812683 lw a3,232(sp) -8000aa50: 10c10893 addi a7,sp,268 -8000aa54: fbbbcce3 blt s7,s11,8000aa0c <_svfprintf_r+0xf78> -8000aa58: 00812703 lw a4,8(sp) -8000aa5c: 01b787b3 add a5,a5,s11 -8000aa60: 00168693 addi a3,a3,1 -8000aa64: 00e8a023 sw a4,0(a7) -8000aa68: 01b8a223 sw s11,4(a7) -8000aa6c: 0ef12623 sw a5,236(sp) -8000aa70: 0ed12423 sw a3,232(sp) -8000aa74: 00700613 li a2,7 -8000aa78: 00888893 addi a7,a7,8 -8000aa7c: a8d65c63 bge a2,a3,80009d14 <_svfprintf_r+0x280> -8000aa80: 0e410613 addi a2,sp,228 -8000aa84: 000c0593 mv a1,s8 -8000aa88: 000d0513 mv a0,s10 -8000aa8c: 4f0040ef jal ra,8000ef7c <__ssprint_r> -8000aa90: 02051263 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000aa94: 0ec12783 lw a5,236(sp) -8000aa98: 10c10893 addi a7,sp,268 -8000aa9c: a78ff06f j 80009d14 <_svfprintf_r+0x280> -8000aaa0: 0e410613 addi a2,sp,228 -8000aaa4: 000c0593 mv a1,s8 -8000aaa8: 000d0513 mv a0,s10 -8000aaac: 4d0040ef jal ra,8000ef7c <__ssprint_r> -8000aab0: aa050e63 beqz a0,80009d6c <_svfprintf_r+0x2d8> -8000aab4: 01012b83 lw s7,16(sp) -8000aab8: ae0b8463 beqz s7,80009da0 <_svfprintf_r+0x30c> -8000aabc: 000b8593 mv a1,s7 -8000aac0: 000d0513 mv a0,s10 -8000aac4: f11f90ef jal ra,800049d4 <_free_r> -8000aac8: ad8ff06f j 80009da0 <_svfprintf_r+0x30c> -8000aacc: 80015737 lui a4,0x80015 -8000aad0: 01000613 li a2,16 -8000aad4: 0e812683 lw a3,232(sp) -8000aad8: 34c70e93 addi t4,a4,844 # 8001534c <__BSS_END__+0xffffe710> -8000aadc: 09065c63 bge a2,a6,8000ab74 <_svfprintf_r+0x10e0> -8000aae0: 04812023 sw s0,64(sp) -8000aae4: 04912223 sw s1,68(sp) -8000aae8: 000d0413 mv s0,s10 -8000aaec: 000c0493 mv s1,s8 -8000aaf0: 01000e13 li t3,16 -8000aaf4: 00700293 li t0,7 -8000aaf8: 00080c13 mv s8,a6 -8000aafc: 000e8d13 mv s10,t4 -8000ab00: 00c0006f j 8000ab0c <_svfprintf_r+0x1078> -8000ab04: ff0c0c13 addi s8,s8,-16 -8000ab08: 058e5a63 bge t3,s8,8000ab5c <_svfprintf_r+0x10c8> -8000ab0c: 01078793 addi a5,a5,16 -8000ab10: 00168693 addi a3,a3,1 -8000ab14: 01a8a023 sw s10,0(a7) -8000ab18: 01c8a223 sw t3,4(a7) -8000ab1c: 0ef12623 sw a5,236(sp) -8000ab20: 0ed12423 sw a3,232(sp) -8000ab24: 00888893 addi a7,a7,8 -8000ab28: fcd2dee3 bge t0,a3,8000ab04 <_svfprintf_r+0x1070> -8000ab2c: 0e410613 addi a2,sp,228 -8000ab30: 00048593 mv a1,s1 -8000ab34: 00040513 mv a0,s0 -8000ab38: 444040ef jal ra,8000ef7c <__ssprint_r> -8000ab3c: 160512e3 bnez a0,8000b4a0 <_svfprintf_r+0x1a0c> -8000ab40: 01000e13 li t3,16 -8000ab44: ff0c0c13 addi s8,s8,-16 -8000ab48: 0ec12783 lw a5,236(sp) -8000ab4c: 0e812683 lw a3,232(sp) -8000ab50: 10c10893 addi a7,sp,268 -8000ab54: 00700293 li t0,7 -8000ab58: fb8e4ae3 blt t3,s8,8000ab0c <_svfprintf_r+0x1078> -8000ab5c: 000c0813 mv a6,s8 -8000ab60: 000d0e93 mv t4,s10 -8000ab64: 00048c13 mv s8,s1 -8000ab68: 00040d13 mv s10,s0 -8000ab6c: 04412483 lw s1,68(sp) -8000ab70: 04012403 lw s0,64(sp) -8000ab74: 010787b3 add a5,a5,a6 -8000ab78: 00168693 addi a3,a3,1 -8000ab7c: 01d8a023 sw t4,0(a7) -8000ab80: 0108a223 sw a6,4(a7) -8000ab84: 0ef12623 sw a5,236(sp) -8000ab88: 0ed12423 sw a3,232(sp) -8000ab8c: 00700613 li a2,7 -8000ab90: 00888893 addi a7,a7,8 -8000ab94: 90d65263 bge a2,a3,80009c98 <_svfprintf_r+0x204> -8000ab98: 0e410613 addi a2,sp,228 -8000ab9c: 000c0593 mv a1,s8 -8000aba0: 000d0513 mv a0,s10 -8000aba4: 3d8040ef jal ra,8000ef7c <__ssprint_r> -8000aba8: f00516e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000abac: 0ec12783 lw a5,236(sp) -8000abb0: 10c10893 addi a7,sp,268 -8000abb4: 8e4ff06f j 80009c98 <_svfprintf_r+0x204> -8000abb8: 0e410613 addi a2,sp,228 -8000abbc: 000c0593 mv a1,s8 -8000abc0: 000d0513 mv a0,s10 -8000abc4: 3b8040ef jal ra,8000ef7c <__ssprint_r> -8000abc8: ee0516e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000abcc: 0ec12783 lw a5,236(sp) -8000abd0: 10c10893 addi a7,sp,268 -8000abd4: 930ff06f j 80009d04 <_svfprintf_r+0x270> -8000abd8: 0cc12583 lw a1,204(sp) -8000abdc: 7eb05c63 blez a1,8000b3d4 <_svfprintf_r+0x1940> -8000abe0: 01c12703 lw a4,28(sp) -8000abe4: 02012683 lw a3,32(sp) -8000abe8: 00070493 mv s1,a4 -8000abec: 3ce6c263 blt a3,a4,8000afb0 <_svfprintf_r+0x151c> -8000abf0: 02905663 blez s1,8000ac1c <_svfprintf_r+0x1188> -8000abf4: 0e812683 lw a3,232(sp) -8000abf8: 009787b3 add a5,a5,s1 -8000abfc: 0168a023 sw s6,0(a7) -8000ac00: 00168693 addi a3,a3,1 -8000ac04: 0098a223 sw s1,4(a7) -8000ac08: 0ef12623 sw a5,236(sp) -8000ac0c: 0ed12423 sw a3,232(sp) -8000ac10: 00700613 li a2,7 -8000ac14: 00888893 addi a7,a7,8 -8000ac18: 40d64ce3 blt a2,a3,8000b830 <_svfprintf_r+0x1d9c> -8000ac1c: fff4c693 not a3,s1 -8000ac20: 01c12703 lw a4,28(sp) -8000ac24: 41f6d693 srai a3,a3,0x1f -8000ac28: 00d4f4b3 and s1,s1,a3 -8000ac2c: 409704b3 sub s1,a4,s1 -8000ac30: 48904e63 bgtz s1,8000b0cc <_svfprintf_r+0x1638> -8000ac34: 01c12703 lw a4,28(sp) -8000ac38: 400a7693 andi a3,s4,1024 -8000ac3c: 00eb0db3 add s11,s6,a4 -8000ac40: 4e069a63 bnez a3,8000b134 <_svfprintf_r+0x16a0> -8000ac44: 0cc12483 lw s1,204(sp) -8000ac48: 02012703 lw a4,32(sp) -8000ac4c: 00e4c663 blt s1,a4,8000ac58 <_svfprintf_r+0x11c4> -8000ac50: 001a7693 andi a3,s4,1 -8000ac54: 400682e3 beqz a3,8000b858 <_svfprintf_r+0x1dc4> -8000ac58: 03012683 lw a3,48(sp) -8000ac5c: 02c12703 lw a4,44(sp) -8000ac60: 00700613 li a2,7 -8000ac64: 00d8a023 sw a3,0(a7) -8000ac68: 0e812683 lw a3,232(sp) -8000ac6c: 00e787b3 add a5,a5,a4 -8000ac70: 00e8a223 sw a4,4(a7) -8000ac74: 00168693 addi a3,a3,1 -8000ac78: 0ef12623 sw a5,236(sp) -8000ac7c: 0ed12423 sw a3,232(sp) -8000ac80: 00888893 addi a7,a7,8 -8000ac84: 6ad644e3 blt a2,a3,8000bb2c <_svfprintf_r+0x2098> -8000ac88: 02012683 lw a3,32(sp) -8000ac8c: 00db0733 add a4,s6,a3 -8000ac90: 409684b3 sub s1,a3,s1 -8000ac94: 41b70733 sub a4,a4,s11 -8000ac98: 00048913 mv s2,s1 -8000ac9c: 00975463 bge a4,s1,8000aca4 <_svfprintf_r+0x1210> -8000aca0: 00070913 mv s2,a4 -8000aca4: 03205663 blez s2,8000acd0 <_svfprintf_r+0x123c> -8000aca8: 0e812703 lw a4,232(sp) -8000acac: 012787b3 add a5,a5,s2 -8000acb0: 01b8a023 sw s11,0(a7) -8000acb4: 00170713 addi a4,a4,1 -8000acb8: 0128a223 sw s2,4(a7) -8000acbc: 0ef12623 sw a5,236(sp) -8000acc0: 0ee12423 sw a4,232(sp) -8000acc4: 00700693 li a3,7 -8000acc8: 00888893 addi a7,a7,8 -8000accc: 6ae6cae3 blt a3,a4,8000bb80 <_svfprintf_r+0x20ec> -8000acd0: fff94713 not a4,s2 -8000acd4: 41f75713 srai a4,a4,0x1f -8000acd8: 00e97733 and a4,s2,a4 -8000acdc: 40e484b3 sub s1,s1,a4 -8000ace0: 00904463 bgtz s1,8000ace8 <_svfprintf_r+0x1254> -8000ace4: 860ff06f j 80009d44 <_svfprintf_r+0x2b0> -8000ace8: 01000693 li a3,16 -8000acec: 0e812703 lw a4,232(sp) -8000acf0: 7e96de63 bge a3,s1,8000b4ec <_svfprintf_r+0x1a58> -8000acf4: 01000913 li s2,16 -8000acf8: 00700c93 li s9,7 -8000acfc: 00c0006f j 8000ad08 <_svfprintf_r+0x1274> -8000ad00: ff048493 addi s1,s1,-16 -8000ad04: 7e995463 bge s2,s1,8000b4ec <_svfprintf_r+0x1a58> -8000ad08: 00812683 lw a3,8(sp) -8000ad0c: 01078793 addi a5,a5,16 -8000ad10: 00170713 addi a4,a4,1 -8000ad14: 00d8a023 sw a3,0(a7) -8000ad18: 0128a223 sw s2,4(a7) -8000ad1c: 0ef12623 sw a5,236(sp) -8000ad20: 0ee12423 sw a4,232(sp) -8000ad24: 00888893 addi a7,a7,8 -8000ad28: fcecdce3 bge s9,a4,8000ad00 <_svfprintf_r+0x126c> -8000ad2c: 0e410613 addi a2,sp,228 -8000ad30: 000c0593 mv a1,s8 -8000ad34: 000d0513 mv a0,s10 -8000ad38: 244040ef jal ra,8000ef7c <__ssprint_r> -8000ad3c: d6051ce3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000ad40: 0ec12783 lw a5,236(sp) -8000ad44: 0e812703 lw a4,232(sp) -8000ad48: 10c10893 addi a7,sp,268 -8000ad4c: fb5ff06f j 8000ad00 <_svfprintf_r+0x126c> -8000ad50: 001a7793 andi a5,s4,1 -8000ad54: c8079863 bnez a5,8000a1e4 <_svfprintf_r+0x750> -8000ad58: 00c8a223 sw a2,4(a7) -8000ad5c: 0f912623 sw s9,236(sp) -8000ad60: 0e912423 sw s1,232(sp) -8000ad64: 00700793 li a5,7 -8000ad68: 5497ca63 blt a5,s1,8000b2bc <_svfprintf_r+0x1828> -8000ad6c: 00268693 addi a3,a3,2 -8000ad70: 01088893 addi a7,a7,16 -8000ad74: d44ff06f j 8000a2b8 <_svfprintf_r+0x824> -8000ad78: d5b05063 blez s11,8000a2b8 <_svfprintf_r+0x824> -8000ad7c: 01000713 li a4,16 -8000ad80: 01b74463 blt a4,s11,8000ad88 <_svfprintf_r+0x12f4> -8000ad84: 6b80106f j 8000c43c <_svfprintf_r+0x29a8> -8000ad88: 00700b13 li s6,7 -8000ad8c: 00060493 mv s1,a2 -8000ad90: 0100006f j 8000ada0 <_svfprintf_r+0x130c> -8000ad94: ff0d8d93 addi s11,s11,-16 -8000ad98: 11b75ee3 bge a4,s11,8000b6b4 <_svfprintf_r+0x1c20> -8000ad9c: 00148493 addi s1,s1,1 -8000ada0: 00812783 lw a5,8(sp) -8000ada4: 010c8c93 addi s9,s9,16 -8000ada8: 00e92223 sw a4,4(s2) -8000adac: 00f92023 sw a5,0(s2) -8000adb0: 0f912623 sw s9,236(sp) -8000adb4: 0e912423 sw s1,232(sp) -8000adb8: 00890913 addi s2,s2,8 -8000adbc: fc9b5ce3 bge s6,s1,8000ad94 <_svfprintf_r+0x1300> -8000adc0: 0e410613 addi a2,sp,228 -8000adc4: 000c0593 mv a1,s8 -8000adc8: 000d0513 mv a0,s10 -8000adcc: 1b0040ef jal ra,8000ef7c <__ssprint_r> -8000add0: ce0512e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000add4: 0ec12c83 lw s9,236(sp) -8000add8: 0e812483 lw s1,232(sp) -8000addc: 10c10913 addi s2,sp,268 -8000ade0: 01000713 li a4,16 -8000ade4: fb1ff06f j 8000ad94 <_svfprintf_r+0x1300> -8000ade8: 01412683 lw a3,20(sp) -8000adec: 010a7793 andi a5,s4,16 -8000adf0: 00468713 addi a4,a3,4 -8000adf4: 18079463 bnez a5,8000af7c <_svfprintf_r+0x14e8> -8000adf8: 040a7793 andi a5,s4,64 -8000adfc: 140786e3 beqz a5,8000b748 <_svfprintf_r+0x1cb4> -8000ae00: 01412783 lw a5,20(sp) -8000ae04: 00000c93 li s9,0 -8000ae08: 00e12a23 sw a4,20(sp) -8000ae0c: 0007d903 lhu s2,0(a5) -8000ae10: f80ff06f j 8000a590 <_svfprintf_r+0xafc> -8000ae14: 01412683 lw a3,20(sp) -8000ae18: 010bf793 andi a5,s7,16 -8000ae1c: 00468713 addi a4,a3,4 -8000ae20: 14079463 bnez a5,8000af68 <_svfprintf_r+0x14d4> -8000ae24: 040bf793 andi a5,s7,64 -8000ae28: 100780e3 beqz a5,8000b728 <_svfprintf_r+0x1c94> -8000ae2c: 01412783 lw a5,20(sp) -8000ae30: 00000c93 li s9,0 -8000ae34: 00e12a23 sw a4,20(sp) -8000ae38: 0007d903 lhu s2,0(a5) -8000ae3c: 00100793 li a5,1 -8000ae40: ed0ff06f j 8000a510 <_svfprintf_r+0xa7c> -8000ae44: 01412683 lw a3,20(sp) -8000ae48: 010a7793 andi a5,s4,16 -8000ae4c: 00468713 addi a4,a3,4 -8000ae50: 10079263 bnez a5,8000af54 <_svfprintf_r+0x14c0> -8000ae54: 040a7793 andi a5,s4,64 -8000ae58: 0a0788e3 beqz a5,8000b708 <_svfprintf_r+0x1c74> -8000ae5c: 01412783 lw a5,20(sp) -8000ae60: 00e12a23 sw a4,20(sp) -8000ae64: 00079903 lh s2,0(a5) -8000ae68: 41f95c93 srai s9,s2,0x1f -8000ae6c: 000c8793 mv a5,s9 -8000ae70: 8407dee3 bgez a5,8000a6cc <_svfprintf_r+0xc38> -8000ae74: 012037b3 snez a5,s2 -8000ae78: 41900cb3 neg s9,s9 -8000ae7c: 40fc8cb3 sub s9,s9,a5 -8000ae80: 02d00793 li a5,45 -8000ae84: 0cf103a3 sb a5,199(sp) -8000ae88: 41200933 neg s2,s2 -8000ae8c: 000a0b93 mv s7,s4 -8000ae90: 00100793 li a5,1 -8000ae94: e80ff06f j 8000a514 <_svfprintf_r+0xa80> -8000ae98: 0e410613 addi a2,sp,228 -8000ae9c: 000c0593 mv a1,s8 -8000aea0: 000d0513 mv a0,s10 -8000aea4: 0d8040ef jal ra,8000ef7c <__ssprint_r> -8000aea8: c00516e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000aeac: 0ec12c83 lw s9,236(sp) -8000aeb0: 0e812483 lw s1,232(sp) -8000aeb4: 10c10913 addi s2,sp,268 -8000aeb8: b44ff06f j 8000a1fc <_svfprintf_r+0x768> -8000aebc: 0e410613 addi a2,sp,228 -8000aec0: 000c0593 mv a1,s8 -8000aec4: 000d0513 mv a0,s10 -8000aec8: 0b4040ef jal ra,8000ef7c <__ssprint_r> -8000aecc: be0514e3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000aed0: 0ec12c83 lw s9,236(sp) -8000aed4: 0e812483 lw s1,232(sp) -8000aed8: 10c10913 addi s2,sp,268 -8000aedc: b4cff06f j 8000a228 <_svfprintf_r+0x794> -8000aee0: 001a7713 andi a4,s4,1 -8000aee4: 00071463 bnez a4,8000aeec <_svfprintf_r+0x1458> -8000aee8: e5dfe06f j 80009d44 <_svfprintf_r+0x2b0> -8000aeec: 999ff06f j 8000a884 <_svfprintf_r+0xdf0> -8000aef0: 000c8893 mv a7,s9 -8000aef4: facff06f j 8000a6a0 <_svfprintf_r+0xc0c> -8000aef8: 03000793 li a5,48 -8000aefc: 1af107a3 sb a5,431(sp) -8000af00: 1af10b13 addi s6,sp,431 -8000af04: e38ff06f j 8000a53c <_svfprintf_r+0xaa8> -8000af08: 00c12683 lw a3,12(sp) -8000af0c: 00040b13 mv s6,s0 -8000af10: 41f6d793 srai a5,a3,0x1f -8000af14: 00d72023 sw a3,0(a4) -8000af18: 00f72223 sw a5,4(a4) -8000af1c: e71fe06f j 80009d8c <_svfprintf_r+0x2f8> -8000af20: 01412703 lw a4,20(sp) -8000af24: 00072783 lw a5,0(a4) -8000af28: 00470713 addi a4,a4,4 -8000af2c: 00e12a23 sw a4,20(sp) -8000af30: 0007a583 lw a1,0(a5) -8000af34: 0047a603 lw a2,4(a5) -8000af38: 0087a683 lw a3,8(a5) -8000af3c: 00c7a783 lw a5,12(a5) -8000af40: 0eb12823 sw a1,240(sp) -8000af44: 0ec12a23 sw a2,244(sp) -8000af48: 0ed12c23 sw a3,248(sp) -8000af4c: 0ef12e23 sw a5,252(sp) -8000af50: f79fe06f j 80009ec8 <_svfprintf_r+0x434> -8000af54: 0006a903 lw s2,0(a3) -8000af58: 00e12a23 sw a4,20(sp) -8000af5c: 41f95c93 srai s9,s2,0x1f -8000af60: 000c8793 mv a5,s9 -8000af64: f64ff06f j 8000a6c8 <_svfprintf_r+0xc34> -8000af68: 0006a903 lw s2,0(a3) -8000af6c: 00000c93 li s9,0 -8000af70: 00e12a23 sw a4,20(sp) -8000af74: 00100793 li a5,1 -8000af78: d98ff06f j 8000a510 <_svfprintf_r+0xa7c> -8000af7c: 0006a903 lw s2,0(a3) -8000af80: 00000c93 li s9,0 -8000af84: 00e12a23 sw a4,20(sp) -8000af88: e08ff06f j 8000a590 <_svfprintf_r+0xafc> -8000af8c: 03c12783 lw a5,60(sp) -8000af90: 00044483 lbu s1,0(s0) -8000af94: 00079463 bnez a5,8000af9c <_svfprintf_r+0x1508> -8000af98: c61fe06f j 80009bf8 <_svfprintf_r+0x164> -8000af9c: 0007c783 lbu a5,0(a5) -8000afa0: 00079463 bnez a5,8000afa8 <_svfprintf_r+0x1514> -8000afa4: c55fe06f j 80009bf8 <_svfprintf_r+0x164> -8000afa8: 400a6a13 ori s4,s4,1024 -8000afac: c4dfe06f j 80009bf8 <_svfprintf_r+0x164> -8000afb0: 00068493 mv s1,a3 -8000afb4: c49040e3 bgtz s1,8000abf4 <_svfprintf_r+0x1160> -8000afb8: c65ff06f j 8000ac1c <_svfprintf_r+0x1188> -8000afbc: 000c8893 mv a7,s9 -8000afc0: 000a0b93 mv s7,s4 -8000afc4: df4ff06f j 8000a5b8 <_svfprintf_r+0xb24> -8000afc8: 800157b7 lui a5,0x80015 -8000afcc: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -8000afd0: 000c8893 mv a7,s9 -8000afd4: 02f12a23 sw a5,52(sp) -8000afd8: 020a7793 andi a5,s4,32 -8000afdc: 2c078063 beqz a5,8000b29c <_svfprintf_r+0x1808> -8000afe0: 01412783 lw a5,20(sp) -8000afe4: 00778b13 addi s6,a5,7 -8000afe8: ff8b7b13 andi s6,s6,-8 -8000afec: 000b2903 lw s2,0(s6) -8000aff0: 004b2c83 lw s9,4(s6) -8000aff4: 008b0793 addi a5,s6,8 -8000aff8: 00f12a23 sw a5,20(sp) -8000affc: 001a7793 andi a5,s4,1 -8000b000: 00078e63 beqz a5,8000b01c <_svfprintf_r+0x1588> -8000b004: 019967b3 or a5,s2,s9 -8000b008: 00078a63 beqz a5,8000b01c <_svfprintf_r+0x1588> -8000b00c: 03000793 li a5,48 -8000b010: 0cf10423 sb a5,200(sp) -8000b014: 0c9104a3 sb s1,201(sp) -8000b018: 002a6a13 ori s4,s4,2 -8000b01c: bffa7b93 andi s7,s4,-1025 -8000b020: 00200793 li a5,2 -8000b024: cecff06f j 8000a510 <_svfprintf_r+0xa7c> -8000b028: 0e410613 addi a2,sp,228 -8000b02c: 000c0593 mv a1,s8 -8000b030: 000d0513 mv a0,s10 -8000b034: 749030ef jal ra,8000ef7c <__ssprint_r> -8000b038: a6051ee3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b03c: 0ec12783 lw a5,236(sp) -8000b040: 10c10893 addi a7,sp,268 -8000b044: 871ff06f j 8000a8b4 <_svfprintf_r+0xe20> -8000b048: 800157b7 lui a5,0x80015 -8000b04c: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> -8000b050: 000c8893 mv a7,s9 -8000b054: 02f12a23 sw a5,52(sp) -8000b058: f81ff06f j 8000afd8 <_svfprintf_r+0x1544> -8000b05c: 000c8893 mv a7,s9 -8000b060: d0cff06f j 8000a56c <_svfprintf_r+0xad8> -8000b064: 00144483 lbu s1,1(s0) -8000b068: 020a6a13 ori s4,s4,32 -8000b06c: 00140413 addi s0,s0,1 -8000b070: b89fe06f j 80009bf8 <_svfprintf_r+0x164> -8000b074: 00144483 lbu s1,1(s0) -8000b078: 200a6a13 ori s4,s4,512 -8000b07c: 00140413 addi s0,s0,1 -8000b080: b79fe06f j 80009bf8 <_svfprintf_r+0x164> -8000b084: 04000593 li a1,64 -8000b088: 000d0513 mv a0,s10 -8000b08c: b1dfc0ef jal ra,80007ba8 <_malloc_r> -8000b090: 00ac2023 sw a0,0(s8) -8000b094: 00ac2823 sw a0,16(s8) -8000b098: 00051463 bnez a0,8000b0a0 <_svfprintf_r+0x160c> -8000b09c: 3cc0106f j 8000c468 <_svfprintf_r+0x29d4> -8000b0a0: 04000713 li a4,64 -8000b0a4: 00ec2a23 sw a4,20(s8) -8000b0a8: a75fe06f j 80009b1c <_svfprintf_r+0x88> -8000b0ac: 00600793 li a5,6 -8000b0b0: 000d8c93 mv s9,s11 -8000b0b4: 79b7ee63 bltu a5,s11,8000b850 <_svfprintf_r+0x1dbc> -8000b0b8: 80015737 lui a4,0x80015 -8000b0bc: 000c8a93 mv s5,s9 -8000b0c0: 01212a23 sw s2,20(sp) -8000b0c4: ca070b13 addi s6,a4,-864 # 80014ca0 <__BSS_END__+0xffffe064> -8000b0c8: b9dfe06f j 80009c64 <_svfprintf_r+0x1d0> -8000b0cc: 01000613 li a2,16 -8000b0d0: 0e812683 lw a3,232(sp) -8000b0d4: 6a965863 bge a2,s1,8000b784 <_svfprintf_r+0x1cf0> -8000b0d8: 01000c93 li s9,16 -8000b0dc: 00700d93 li s11,7 -8000b0e0: 00c0006f j 8000b0ec <_svfprintf_r+0x1658> -8000b0e4: ff048493 addi s1,s1,-16 -8000b0e8: 689cde63 bge s9,s1,8000b784 <_svfprintf_r+0x1cf0> -8000b0ec: 00812703 lw a4,8(sp) -8000b0f0: 01078793 addi a5,a5,16 -8000b0f4: 00168693 addi a3,a3,1 -8000b0f8: 00e8a023 sw a4,0(a7) -8000b0fc: 0198a223 sw s9,4(a7) -8000b100: 0ef12623 sw a5,236(sp) -8000b104: 0ed12423 sw a3,232(sp) -8000b108: 00888893 addi a7,a7,8 -8000b10c: fcdddce3 bge s11,a3,8000b0e4 <_svfprintf_r+0x1650> -8000b110: 0e410613 addi a2,sp,228 -8000b114: 000c0593 mv a1,s8 -8000b118: 000d0513 mv a0,s10 -8000b11c: 661030ef jal ra,8000ef7c <__ssprint_r> -8000b120: 98051ae3 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b124: 0ec12783 lw a5,236(sp) -8000b128: 0e812683 lw a3,232(sp) -8000b12c: 10c10893 addi a7,sp,268 -8000b130: fb5ff06f j 8000b0e4 <_svfprintf_r+0x1650> -8000b134: 02012703 lw a4,32(sp) -8000b138: 02412c83 lw s9,36(sp) -8000b13c: 01412e23 sw s4,28(sp) -8000b140: 04812023 sw s0,64(sp) -8000b144: 05312223 sw s3,68(sp) -8000b148: 03512223 sw s5,36(sp) -8000b14c: 02812983 lw s3,40(sp) -8000b150: 03612423 sw s6,40(sp) -8000b154: 00eb0bb3 add s7,s6,a4 -8000b158: 03c12403 lw s0,60(sp) -8000b15c: 04812a03 lw s4,72(sp) -8000b160: 04c12a83 lw s5,76(sp) -8000b164: 00700493 li s1,7 -8000b168: 01000913 li s2,16 -8000b16c: 000c0b13 mv s6,s8 -8000b170: 080c8863 beqz s9,8000b200 <_svfprintf_r+0x176c> -8000b174: 08099863 bnez s3,8000b204 <_svfprintf_r+0x1770> -8000b178: fff40413 addi s0,s0,-1 -8000b17c: fffc8c93 addi s9,s9,-1 -8000b180: 0e812703 lw a4,232(sp) -8000b184: 014787b3 add a5,a5,s4 -8000b188: 0158a023 sw s5,0(a7) -8000b18c: 00170713 addi a4,a4,1 -8000b190: 0148a223 sw s4,4(a7) -8000b194: 0ef12623 sw a5,236(sp) -8000b198: 0ee12423 sw a4,232(sp) -8000b19c: 00888893 addi a7,a7,8 -8000b1a0: 14e4c463 blt s1,a4,8000b2e8 <_svfprintf_r+0x1854> -8000b1a4: 00044683 lbu a3,0(s0) -8000b1a8: 41bb8633 sub a2,s7,s11 -8000b1ac: 00068c13 mv s8,a3 -8000b1b0: 00d65463 bge a2,a3,8000b1b8 <_svfprintf_r+0x1724> -8000b1b4: 00060c13 mv s8,a2 -8000b1b8: 03805663 blez s8,8000b1e4 <_svfprintf_r+0x1750> -8000b1bc: 0e812683 lw a3,232(sp) -8000b1c0: 018787b3 add a5,a5,s8 -8000b1c4: 01b8a023 sw s11,0(a7) -8000b1c8: 00168693 addi a3,a3,1 -8000b1cc: 0188a223 sw s8,4(a7) -8000b1d0: 0ef12623 sw a5,236(sp) -8000b1d4: 0ed12423 sw a3,232(sp) -8000b1d8: 34d4c063 blt s1,a3,8000b518 <_svfprintf_r+0x1a84> -8000b1dc: 00044683 lbu a3,0(s0) -8000b1e0: 00888893 addi a7,a7,8 -8000b1e4: fffc4613 not a2,s8 -8000b1e8: 41f65613 srai a2,a2,0x1f -8000b1ec: 00cc7733 and a4,s8,a2 -8000b1f0: 40e68c33 sub s8,a3,a4 -8000b1f4: 01804c63 bgtz s8,8000b20c <_svfprintf_r+0x1778> -8000b1f8: 00dd8db3 add s11,s11,a3 -8000b1fc: f60c9ce3 bnez s9,8000b174 <_svfprintf_r+0x16e0> -8000b200: 72098c63 beqz s3,8000b938 <_svfprintf_r+0x1ea4> -8000b204: fff98993 addi s3,s3,-1 -8000b208: f79ff06f j 8000b180 <_svfprintf_r+0x16ec> +8000a924: b3b05663 blez s11,80009c50 <_svfprintf_r+0x280> +8000a928: 01000613 li a2,16 +8000a92c: 0e812683 lw a3,232(sp) +8000a930: 07b65263 bge a2,s11,8000a994 <_svfprintf_r+0xfc4> +8000a934: 01000b93 li s7,16 +8000a938: 00700913 li s2,7 +8000a93c: 00c0006f j 8000a948 <_svfprintf_r+0xf78> +8000a940: ff0d8d93 addi s11,s11,-16 +8000a944: 05bbd863 bge s7,s11,8000a994 <_svfprintf_r+0xfc4> +8000a948: 00812703 lw a4,8(sp) +8000a94c: 01078793 addi a5,a5,16 +8000a950: 00168693 addi a3,a3,1 +8000a954: 00e8a023 sw a4,0(a7) +8000a958: 0178a223 sw s7,4(a7) +8000a95c: 0ef12623 sw a5,236(sp) +8000a960: 0ed12423 sw a3,232(sp) +8000a964: 00888893 addi a7,a7,8 +8000a968: fcd95ce3 bge s2,a3,8000a940 <_svfprintf_r+0xf70> +8000a96c: 0e410613 addi a2,sp,228 +8000a970: 000c0593 mv a1,s8 +8000a974: 000d0513 mv a0,s10 +8000a978: 540040ef jal ra,8000eeb8 <__ssprint_r> +8000a97c: 06051a63 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a980: ff0d8d93 addi s11,s11,-16 +8000a984: 0ec12783 lw a5,236(sp) +8000a988: 0e812683 lw a3,232(sp) +8000a98c: 10c10893 addi a7,sp,268 +8000a990: fbbbcce3 blt s7,s11,8000a948 <_svfprintf_r+0xf78> +8000a994: 00812703 lw a4,8(sp) +8000a998: 01b787b3 add a5,a5,s11 +8000a99c: 00168693 addi a3,a3,1 +8000a9a0: 00e8a023 sw a4,0(a7) +8000a9a4: 01b8a223 sw s11,4(a7) +8000a9a8: 0ef12623 sw a5,236(sp) +8000a9ac: 0ed12423 sw a3,232(sp) +8000a9b0: 00700613 li a2,7 +8000a9b4: 00888893 addi a7,a7,8 +8000a9b8: a8d65c63 bge a2,a3,80009c50 <_svfprintf_r+0x280> +8000a9bc: 0e410613 addi a2,sp,228 +8000a9c0: 000c0593 mv a1,s8 +8000a9c4: 000d0513 mv a0,s10 +8000a9c8: 4f0040ef jal ra,8000eeb8 <__ssprint_r> +8000a9cc: 02051263 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000a9d0: 0ec12783 lw a5,236(sp) +8000a9d4: 10c10893 addi a7,sp,268 +8000a9d8: a78ff06f j 80009c50 <_svfprintf_r+0x280> +8000a9dc: 0e410613 addi a2,sp,228 +8000a9e0: 000c0593 mv a1,s8 +8000a9e4: 000d0513 mv a0,s10 +8000a9e8: 4d0040ef jal ra,8000eeb8 <__ssprint_r> +8000a9ec: aa050e63 beqz a0,80009ca8 <_svfprintf_r+0x2d8> +8000a9f0: 01012b83 lw s7,16(sp) +8000a9f4: ae0b8463 beqz s7,80009cdc <_svfprintf_r+0x30c> +8000a9f8: 000b8593 mv a1,s7 +8000a9fc: 000d0513 mv a0,s10 +8000aa00: f11f90ef jal ra,80004910 <_free_r> +8000aa04: ad8ff06f j 80009cdc <_svfprintf_r+0x30c> +8000aa08: 80015737 lui a4,0x80015 +8000aa0c: 01000613 li a2,16 +8000aa10: 0e812683 lw a3,232(sp) +8000aa14: 27470e93 addi t4,a4,628 # 80015274 <__BSS_END__+0xffffe638> +8000aa18: 09065c63 bge a2,a6,8000aab0 <_svfprintf_r+0x10e0> +8000aa1c: 04812023 sw s0,64(sp) +8000aa20: 04912223 sw s1,68(sp) +8000aa24: 000d0413 mv s0,s10 +8000aa28: 000c0493 mv s1,s8 +8000aa2c: 01000e13 li t3,16 +8000aa30: 00700293 li t0,7 +8000aa34: 00080c13 mv s8,a6 +8000aa38: 000e8d13 mv s10,t4 +8000aa3c: 00c0006f j 8000aa48 <_svfprintf_r+0x1078> +8000aa40: ff0c0c13 addi s8,s8,-16 +8000aa44: 058e5a63 bge t3,s8,8000aa98 <_svfprintf_r+0x10c8> +8000aa48: 01078793 addi a5,a5,16 +8000aa4c: 00168693 addi a3,a3,1 +8000aa50: 01a8a023 sw s10,0(a7) +8000aa54: 01c8a223 sw t3,4(a7) +8000aa58: 0ef12623 sw a5,236(sp) +8000aa5c: 0ed12423 sw a3,232(sp) +8000aa60: 00888893 addi a7,a7,8 +8000aa64: fcd2dee3 bge t0,a3,8000aa40 <_svfprintf_r+0x1070> +8000aa68: 0e410613 addi a2,sp,228 +8000aa6c: 00048593 mv a1,s1 +8000aa70: 00040513 mv a0,s0 +8000aa74: 444040ef jal ra,8000eeb8 <__ssprint_r> +8000aa78: 160512e3 bnez a0,8000b3dc <_svfprintf_r+0x1a0c> +8000aa7c: 01000e13 li t3,16 +8000aa80: ff0c0c13 addi s8,s8,-16 +8000aa84: 0ec12783 lw a5,236(sp) +8000aa88: 0e812683 lw a3,232(sp) +8000aa8c: 10c10893 addi a7,sp,268 +8000aa90: 00700293 li t0,7 +8000aa94: fb8e4ae3 blt t3,s8,8000aa48 <_svfprintf_r+0x1078> +8000aa98: 000c0813 mv a6,s8 +8000aa9c: 000d0e93 mv t4,s10 +8000aaa0: 00048c13 mv s8,s1 +8000aaa4: 00040d13 mv s10,s0 +8000aaa8: 04412483 lw s1,68(sp) +8000aaac: 04012403 lw s0,64(sp) +8000aab0: 010787b3 add a5,a5,a6 +8000aab4: 00168693 addi a3,a3,1 +8000aab8: 01d8a023 sw t4,0(a7) +8000aabc: 0108a223 sw a6,4(a7) +8000aac0: 0ef12623 sw a5,236(sp) +8000aac4: 0ed12423 sw a3,232(sp) +8000aac8: 00700613 li a2,7 +8000aacc: 00888893 addi a7,a7,8 +8000aad0: 90d65263 bge a2,a3,80009bd4 <_svfprintf_r+0x204> +8000aad4: 0e410613 addi a2,sp,228 +8000aad8: 000c0593 mv a1,s8 +8000aadc: 000d0513 mv a0,s10 +8000aae0: 3d8040ef jal ra,8000eeb8 <__ssprint_r> +8000aae4: f00516e3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000aae8: 0ec12783 lw a5,236(sp) +8000aaec: 10c10893 addi a7,sp,268 +8000aaf0: 8e4ff06f j 80009bd4 <_svfprintf_r+0x204> +8000aaf4: 0e410613 addi a2,sp,228 +8000aaf8: 000c0593 mv a1,s8 +8000aafc: 000d0513 mv a0,s10 +8000ab00: 3b8040ef jal ra,8000eeb8 <__ssprint_r> +8000ab04: ee0516e3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000ab08: 0ec12783 lw a5,236(sp) +8000ab0c: 10c10893 addi a7,sp,268 +8000ab10: 930ff06f j 80009c40 <_svfprintf_r+0x270> +8000ab14: 0cc12583 lw a1,204(sp) +8000ab18: 7eb05c63 blez a1,8000b310 <_svfprintf_r+0x1940> +8000ab1c: 01c12703 lw a4,28(sp) +8000ab20: 02012683 lw a3,32(sp) +8000ab24: 00070493 mv s1,a4 +8000ab28: 3ce6c263 blt a3,a4,8000aeec <_svfprintf_r+0x151c> +8000ab2c: 02905663 blez s1,8000ab58 <_svfprintf_r+0x1188> +8000ab30: 0e812683 lw a3,232(sp) +8000ab34: 009787b3 add a5,a5,s1 +8000ab38: 0168a023 sw s6,0(a7) +8000ab3c: 00168693 addi a3,a3,1 +8000ab40: 0098a223 sw s1,4(a7) +8000ab44: 0ef12623 sw a5,236(sp) +8000ab48: 0ed12423 sw a3,232(sp) +8000ab4c: 00700613 li a2,7 +8000ab50: 00888893 addi a7,a7,8 +8000ab54: 40d64ce3 blt a2,a3,8000b76c <_svfprintf_r+0x1d9c> +8000ab58: fff4c693 not a3,s1 +8000ab5c: 01c12703 lw a4,28(sp) +8000ab60: 41f6d693 srai a3,a3,0x1f +8000ab64: 00d4f4b3 and s1,s1,a3 +8000ab68: 409704b3 sub s1,a4,s1 +8000ab6c: 48904e63 bgtz s1,8000b008 <_svfprintf_r+0x1638> +8000ab70: 01c12703 lw a4,28(sp) +8000ab74: 400a7693 andi a3,s4,1024 +8000ab78: 00eb0db3 add s11,s6,a4 +8000ab7c: 4e069a63 bnez a3,8000b070 <_svfprintf_r+0x16a0> +8000ab80: 0cc12483 lw s1,204(sp) +8000ab84: 02012703 lw a4,32(sp) +8000ab88: 00e4c663 blt s1,a4,8000ab94 <_svfprintf_r+0x11c4> +8000ab8c: 001a7693 andi a3,s4,1 +8000ab90: 400682e3 beqz a3,8000b794 <_svfprintf_r+0x1dc4> +8000ab94: 03012683 lw a3,48(sp) +8000ab98: 02c12703 lw a4,44(sp) +8000ab9c: 00700613 li a2,7 +8000aba0: 00d8a023 sw a3,0(a7) +8000aba4: 0e812683 lw a3,232(sp) +8000aba8: 00e787b3 add a5,a5,a4 +8000abac: 00e8a223 sw a4,4(a7) +8000abb0: 00168693 addi a3,a3,1 +8000abb4: 0ef12623 sw a5,236(sp) +8000abb8: 0ed12423 sw a3,232(sp) +8000abbc: 00888893 addi a7,a7,8 +8000abc0: 6ad644e3 blt a2,a3,8000ba68 <_svfprintf_r+0x2098> +8000abc4: 02012683 lw a3,32(sp) +8000abc8: 00db0733 add a4,s6,a3 +8000abcc: 409684b3 sub s1,a3,s1 +8000abd0: 41b70733 sub a4,a4,s11 +8000abd4: 00048913 mv s2,s1 +8000abd8: 00975463 bge a4,s1,8000abe0 <_svfprintf_r+0x1210> +8000abdc: 00070913 mv s2,a4 +8000abe0: 03205663 blez s2,8000ac0c <_svfprintf_r+0x123c> +8000abe4: 0e812703 lw a4,232(sp) +8000abe8: 012787b3 add a5,a5,s2 +8000abec: 01b8a023 sw s11,0(a7) +8000abf0: 00170713 addi a4,a4,1 +8000abf4: 0128a223 sw s2,4(a7) +8000abf8: 0ef12623 sw a5,236(sp) +8000abfc: 0ee12423 sw a4,232(sp) +8000ac00: 00700693 li a3,7 +8000ac04: 00888893 addi a7,a7,8 +8000ac08: 6ae6cae3 blt a3,a4,8000babc <_svfprintf_r+0x20ec> +8000ac0c: fff94713 not a4,s2 +8000ac10: 41f75713 srai a4,a4,0x1f +8000ac14: 00e97733 and a4,s2,a4 +8000ac18: 40e484b3 sub s1,s1,a4 +8000ac1c: 00904463 bgtz s1,8000ac24 <_svfprintf_r+0x1254> +8000ac20: 860ff06f j 80009c80 <_svfprintf_r+0x2b0> +8000ac24: 01000693 li a3,16 +8000ac28: 0e812703 lw a4,232(sp) +8000ac2c: 7e96de63 bge a3,s1,8000b428 <_svfprintf_r+0x1a58> +8000ac30: 01000913 li s2,16 +8000ac34: 00700c93 li s9,7 +8000ac38: 00c0006f j 8000ac44 <_svfprintf_r+0x1274> +8000ac3c: ff048493 addi s1,s1,-16 +8000ac40: 7e995463 bge s2,s1,8000b428 <_svfprintf_r+0x1a58> +8000ac44: 00812683 lw a3,8(sp) +8000ac48: 01078793 addi a5,a5,16 +8000ac4c: 00170713 addi a4,a4,1 +8000ac50: 00d8a023 sw a3,0(a7) +8000ac54: 0128a223 sw s2,4(a7) +8000ac58: 0ef12623 sw a5,236(sp) +8000ac5c: 0ee12423 sw a4,232(sp) +8000ac60: 00888893 addi a7,a7,8 +8000ac64: fcecdce3 bge s9,a4,8000ac3c <_svfprintf_r+0x126c> +8000ac68: 0e410613 addi a2,sp,228 +8000ac6c: 000c0593 mv a1,s8 +8000ac70: 000d0513 mv a0,s10 +8000ac74: 244040ef jal ra,8000eeb8 <__ssprint_r> +8000ac78: d6051ce3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000ac7c: 0ec12783 lw a5,236(sp) +8000ac80: 0e812703 lw a4,232(sp) +8000ac84: 10c10893 addi a7,sp,268 +8000ac88: fb5ff06f j 8000ac3c <_svfprintf_r+0x126c> +8000ac8c: 001a7793 andi a5,s4,1 +8000ac90: c8079863 bnez a5,8000a120 <_svfprintf_r+0x750> +8000ac94: 00c8a223 sw a2,4(a7) +8000ac98: 0f912623 sw s9,236(sp) +8000ac9c: 0e912423 sw s1,232(sp) +8000aca0: 00700793 li a5,7 +8000aca4: 5497ca63 blt a5,s1,8000b1f8 <_svfprintf_r+0x1828> +8000aca8: 00268693 addi a3,a3,2 +8000acac: 01088893 addi a7,a7,16 +8000acb0: d44ff06f j 8000a1f4 <_svfprintf_r+0x824> +8000acb4: d5b05063 blez s11,8000a1f4 <_svfprintf_r+0x824> +8000acb8: 01000713 li a4,16 +8000acbc: 01b74463 blt a4,s11,8000acc4 <_svfprintf_r+0x12f4> +8000acc0: 6b80106f j 8000c378 <_svfprintf_r+0x29a8> +8000acc4: 00700b13 li s6,7 +8000acc8: 00060493 mv s1,a2 +8000accc: 0100006f j 8000acdc <_svfprintf_r+0x130c> +8000acd0: ff0d8d93 addi s11,s11,-16 +8000acd4: 11b75ee3 bge a4,s11,8000b5f0 <_svfprintf_r+0x1c20> +8000acd8: 00148493 addi s1,s1,1 +8000acdc: 00812783 lw a5,8(sp) +8000ace0: 010c8c93 addi s9,s9,16 +8000ace4: 00e92223 sw a4,4(s2) +8000ace8: 00f92023 sw a5,0(s2) +8000acec: 0f912623 sw s9,236(sp) +8000acf0: 0e912423 sw s1,232(sp) +8000acf4: 00890913 addi s2,s2,8 +8000acf8: fc9b5ce3 bge s6,s1,8000acd0 <_svfprintf_r+0x1300> +8000acfc: 0e410613 addi a2,sp,228 +8000ad00: 000c0593 mv a1,s8 +8000ad04: 000d0513 mv a0,s10 +8000ad08: 1b0040ef jal ra,8000eeb8 <__ssprint_r> +8000ad0c: ce0512e3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000ad10: 0ec12c83 lw s9,236(sp) +8000ad14: 0e812483 lw s1,232(sp) +8000ad18: 10c10913 addi s2,sp,268 +8000ad1c: 01000713 li a4,16 +8000ad20: fb1ff06f j 8000acd0 <_svfprintf_r+0x1300> +8000ad24: 01412683 lw a3,20(sp) +8000ad28: 010a7793 andi a5,s4,16 +8000ad2c: 00468713 addi a4,a3,4 +8000ad30: 18079463 bnez a5,8000aeb8 <_svfprintf_r+0x14e8> +8000ad34: 040a7793 andi a5,s4,64 +8000ad38: 140786e3 beqz a5,8000b684 <_svfprintf_r+0x1cb4> +8000ad3c: 01412783 lw a5,20(sp) +8000ad40: 00000c93 li s9,0 +8000ad44: 00e12a23 sw a4,20(sp) +8000ad48: 0007d903 lhu s2,0(a5) +8000ad4c: f80ff06f j 8000a4cc <_svfprintf_r+0xafc> +8000ad50: 01412683 lw a3,20(sp) +8000ad54: 010bf793 andi a5,s7,16 +8000ad58: 00468713 addi a4,a3,4 +8000ad5c: 14079463 bnez a5,8000aea4 <_svfprintf_r+0x14d4> +8000ad60: 040bf793 andi a5,s7,64 +8000ad64: 100780e3 beqz a5,8000b664 <_svfprintf_r+0x1c94> +8000ad68: 01412783 lw a5,20(sp) +8000ad6c: 00000c93 li s9,0 +8000ad70: 00e12a23 sw a4,20(sp) +8000ad74: 0007d903 lhu s2,0(a5) +8000ad78: 00100793 li a5,1 +8000ad7c: ed0ff06f j 8000a44c <_svfprintf_r+0xa7c> +8000ad80: 01412683 lw a3,20(sp) +8000ad84: 010a7793 andi a5,s4,16 +8000ad88: 00468713 addi a4,a3,4 +8000ad8c: 10079263 bnez a5,8000ae90 <_svfprintf_r+0x14c0> +8000ad90: 040a7793 andi a5,s4,64 +8000ad94: 0a0788e3 beqz a5,8000b644 <_svfprintf_r+0x1c74> +8000ad98: 01412783 lw a5,20(sp) +8000ad9c: 00e12a23 sw a4,20(sp) +8000ada0: 00079903 lh s2,0(a5) +8000ada4: 41f95c93 srai s9,s2,0x1f +8000ada8: 000c8793 mv a5,s9 +8000adac: 8407dee3 bgez a5,8000a608 <_svfprintf_r+0xc38> +8000adb0: 012037b3 snez a5,s2 +8000adb4: 41900cb3 neg s9,s9 +8000adb8: 40fc8cb3 sub s9,s9,a5 +8000adbc: 02d00793 li a5,45 +8000adc0: 0cf103a3 sb a5,199(sp) +8000adc4: 41200933 neg s2,s2 +8000adc8: 000a0b93 mv s7,s4 +8000adcc: 00100793 li a5,1 +8000add0: e80ff06f j 8000a450 <_svfprintf_r+0xa80> +8000add4: 0e410613 addi a2,sp,228 +8000add8: 000c0593 mv a1,s8 +8000addc: 000d0513 mv a0,s10 +8000ade0: 0d8040ef jal ra,8000eeb8 <__ssprint_r> +8000ade4: c00516e3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000ade8: 0ec12c83 lw s9,236(sp) +8000adec: 0e812483 lw s1,232(sp) +8000adf0: 10c10913 addi s2,sp,268 +8000adf4: b44ff06f j 8000a138 <_svfprintf_r+0x768> +8000adf8: 0e410613 addi a2,sp,228 +8000adfc: 000c0593 mv a1,s8 +8000ae00: 000d0513 mv a0,s10 +8000ae04: 0b4040ef jal ra,8000eeb8 <__ssprint_r> +8000ae08: be0514e3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000ae0c: 0ec12c83 lw s9,236(sp) +8000ae10: 0e812483 lw s1,232(sp) +8000ae14: 10c10913 addi s2,sp,268 +8000ae18: b4cff06f j 8000a164 <_svfprintf_r+0x794> +8000ae1c: 001a7713 andi a4,s4,1 +8000ae20: 00071463 bnez a4,8000ae28 <_svfprintf_r+0x1458> +8000ae24: e5dfe06f j 80009c80 <_svfprintf_r+0x2b0> +8000ae28: 999ff06f j 8000a7c0 <_svfprintf_r+0xdf0> +8000ae2c: 000c8893 mv a7,s9 +8000ae30: facff06f j 8000a5dc <_svfprintf_r+0xc0c> +8000ae34: 03000793 li a5,48 +8000ae38: 1af107a3 sb a5,431(sp) +8000ae3c: 1af10b13 addi s6,sp,431 +8000ae40: e38ff06f j 8000a478 <_svfprintf_r+0xaa8> +8000ae44: 00c12683 lw a3,12(sp) +8000ae48: 00040b13 mv s6,s0 +8000ae4c: 41f6d793 srai a5,a3,0x1f +8000ae50: 00d72023 sw a3,0(a4) +8000ae54: 00f72223 sw a5,4(a4) +8000ae58: e71fe06f j 80009cc8 <_svfprintf_r+0x2f8> +8000ae5c: 01412703 lw a4,20(sp) +8000ae60: 00072783 lw a5,0(a4) +8000ae64: 00470713 addi a4,a4,4 +8000ae68: 00e12a23 sw a4,20(sp) +8000ae6c: 0007a583 lw a1,0(a5) +8000ae70: 0047a603 lw a2,4(a5) +8000ae74: 0087a683 lw a3,8(a5) +8000ae78: 00c7a783 lw a5,12(a5) +8000ae7c: 0eb12823 sw a1,240(sp) +8000ae80: 0ec12a23 sw a2,244(sp) +8000ae84: 0ed12c23 sw a3,248(sp) +8000ae88: 0ef12e23 sw a5,252(sp) +8000ae8c: f79fe06f j 80009e04 <_svfprintf_r+0x434> +8000ae90: 0006a903 lw s2,0(a3) +8000ae94: 00e12a23 sw a4,20(sp) +8000ae98: 41f95c93 srai s9,s2,0x1f +8000ae9c: 000c8793 mv a5,s9 +8000aea0: f64ff06f j 8000a604 <_svfprintf_r+0xc34> +8000aea4: 0006a903 lw s2,0(a3) +8000aea8: 00000c93 li s9,0 +8000aeac: 00e12a23 sw a4,20(sp) +8000aeb0: 00100793 li a5,1 +8000aeb4: d98ff06f j 8000a44c <_svfprintf_r+0xa7c> +8000aeb8: 0006a903 lw s2,0(a3) +8000aebc: 00000c93 li s9,0 +8000aec0: 00e12a23 sw a4,20(sp) +8000aec4: e08ff06f j 8000a4cc <_svfprintf_r+0xafc> +8000aec8: 03c12783 lw a5,60(sp) +8000aecc: 00044483 lbu s1,0(s0) +8000aed0: 00079463 bnez a5,8000aed8 <_svfprintf_r+0x1508> +8000aed4: c61fe06f j 80009b34 <_svfprintf_r+0x164> +8000aed8: 0007c783 lbu a5,0(a5) +8000aedc: 00079463 bnez a5,8000aee4 <_svfprintf_r+0x1514> +8000aee0: c55fe06f j 80009b34 <_svfprintf_r+0x164> +8000aee4: 400a6a13 ori s4,s4,1024 +8000aee8: c4dfe06f j 80009b34 <_svfprintf_r+0x164> +8000aeec: 00068493 mv s1,a3 +8000aef0: c49040e3 bgtz s1,8000ab30 <_svfprintf_r+0x1160> +8000aef4: c65ff06f j 8000ab58 <_svfprintf_r+0x1188> +8000aef8: 000c8893 mv a7,s9 +8000aefc: 000a0b93 mv s7,s4 +8000af00: df4ff06f j 8000a4f4 <_svfprintf_r+0xb24> +8000af04: 800157b7 lui a5,0x80015 +8000af08: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +8000af0c: 000c8893 mv a7,s9 +8000af10: 02f12a23 sw a5,52(sp) +8000af14: 020a7793 andi a5,s4,32 +8000af18: 2c078063 beqz a5,8000b1d8 <_svfprintf_r+0x1808> +8000af1c: 01412783 lw a5,20(sp) +8000af20: 00778b13 addi s6,a5,7 +8000af24: ff8b7b13 andi s6,s6,-8 +8000af28: 000b2903 lw s2,0(s6) +8000af2c: 004b2c83 lw s9,4(s6) +8000af30: 008b0793 addi a5,s6,8 +8000af34: 00f12a23 sw a5,20(sp) +8000af38: 001a7793 andi a5,s4,1 +8000af3c: 00078e63 beqz a5,8000af58 <_svfprintf_r+0x1588> +8000af40: 019967b3 or a5,s2,s9 +8000af44: 00078a63 beqz a5,8000af58 <_svfprintf_r+0x1588> +8000af48: 03000793 li a5,48 +8000af4c: 0cf10423 sb a5,200(sp) +8000af50: 0c9104a3 sb s1,201(sp) +8000af54: 002a6a13 ori s4,s4,2 +8000af58: bffa7b93 andi s7,s4,-1025 +8000af5c: 00200793 li a5,2 +8000af60: cecff06f j 8000a44c <_svfprintf_r+0xa7c> +8000af64: 0e410613 addi a2,sp,228 +8000af68: 000c0593 mv a1,s8 +8000af6c: 000d0513 mv a0,s10 +8000af70: 749030ef jal ra,8000eeb8 <__ssprint_r> +8000af74: a6051ee3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000af78: 0ec12783 lw a5,236(sp) +8000af7c: 10c10893 addi a7,sp,268 +8000af80: 871ff06f j 8000a7f0 <_svfprintf_r+0xe20> +8000af84: 800157b7 lui a5,0x80015 +8000af88: bb878793 addi a5,a5,-1096 # 80014bb8 <__BSS_END__+0xffffdf7c> +8000af8c: 000c8893 mv a7,s9 +8000af90: 02f12a23 sw a5,52(sp) +8000af94: f81ff06f j 8000af14 <_svfprintf_r+0x1544> +8000af98: 000c8893 mv a7,s9 +8000af9c: d0cff06f j 8000a4a8 <_svfprintf_r+0xad8> +8000afa0: 00144483 lbu s1,1(s0) +8000afa4: 020a6a13 ori s4,s4,32 +8000afa8: 00140413 addi s0,s0,1 +8000afac: b89fe06f j 80009b34 <_svfprintf_r+0x164> +8000afb0: 00144483 lbu s1,1(s0) +8000afb4: 200a6a13 ori s4,s4,512 +8000afb8: 00140413 addi s0,s0,1 +8000afbc: b79fe06f j 80009b34 <_svfprintf_r+0x164> +8000afc0: 04000593 li a1,64 +8000afc4: 000d0513 mv a0,s10 +8000afc8: b1dfc0ef jal ra,80007ae4 <_malloc_r> +8000afcc: 00ac2023 sw a0,0(s8) +8000afd0: 00ac2823 sw a0,16(s8) +8000afd4: 00051463 bnez a0,8000afdc <_svfprintf_r+0x160c> +8000afd8: 3cc0106f j 8000c3a4 <_svfprintf_r+0x29d4> +8000afdc: 04000713 li a4,64 +8000afe0: 00ec2a23 sw a4,20(s8) +8000afe4: a75fe06f j 80009a58 <_svfprintf_r+0x88> +8000afe8: 00600793 li a5,6 +8000afec: 000d8c93 mv s9,s11 +8000aff0: 79b7ee63 bltu a5,s11,8000b78c <_svfprintf_r+0x1dbc> +8000aff4: 80015737 lui a4,0x80015 +8000aff8: 000c8a93 mv s5,s9 +8000affc: 01212a23 sw s2,20(sp) +8000b000: bcc70b13 addi s6,a4,-1076 # 80014bcc <__BSS_END__+0xffffdf90> +8000b004: b9dfe06f j 80009ba0 <_svfprintf_r+0x1d0> +8000b008: 01000613 li a2,16 +8000b00c: 0e812683 lw a3,232(sp) +8000b010: 6a965863 bge a2,s1,8000b6c0 <_svfprintf_r+0x1cf0> +8000b014: 01000c93 li s9,16 +8000b018: 00700d93 li s11,7 +8000b01c: 00c0006f j 8000b028 <_svfprintf_r+0x1658> +8000b020: ff048493 addi s1,s1,-16 +8000b024: 689cde63 bge s9,s1,8000b6c0 <_svfprintf_r+0x1cf0> +8000b028: 00812703 lw a4,8(sp) +8000b02c: 01078793 addi a5,a5,16 +8000b030: 00168693 addi a3,a3,1 +8000b034: 00e8a023 sw a4,0(a7) +8000b038: 0198a223 sw s9,4(a7) +8000b03c: 0ef12623 sw a5,236(sp) +8000b040: 0ed12423 sw a3,232(sp) +8000b044: 00888893 addi a7,a7,8 +8000b048: fcdddce3 bge s11,a3,8000b020 <_svfprintf_r+0x1650> +8000b04c: 0e410613 addi a2,sp,228 +8000b050: 000c0593 mv a1,s8 +8000b054: 000d0513 mv a0,s10 +8000b058: 661030ef jal ra,8000eeb8 <__ssprint_r> +8000b05c: 98051ae3 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000b060: 0ec12783 lw a5,236(sp) +8000b064: 0e812683 lw a3,232(sp) +8000b068: 10c10893 addi a7,sp,268 +8000b06c: fb5ff06f j 8000b020 <_svfprintf_r+0x1650> +8000b070: 02012703 lw a4,32(sp) +8000b074: 02412c83 lw s9,36(sp) +8000b078: 01412e23 sw s4,28(sp) +8000b07c: 04812023 sw s0,64(sp) +8000b080: 05312223 sw s3,68(sp) +8000b084: 03512223 sw s5,36(sp) +8000b088: 02812983 lw s3,40(sp) +8000b08c: 03612423 sw s6,40(sp) +8000b090: 00eb0bb3 add s7,s6,a4 +8000b094: 03c12403 lw s0,60(sp) +8000b098: 04812a03 lw s4,72(sp) +8000b09c: 04c12a83 lw s5,76(sp) +8000b0a0: 00700493 li s1,7 +8000b0a4: 01000913 li s2,16 +8000b0a8: 000c0b13 mv s6,s8 +8000b0ac: 080c8863 beqz s9,8000b13c <_svfprintf_r+0x176c> +8000b0b0: 08099863 bnez s3,8000b140 <_svfprintf_r+0x1770> +8000b0b4: fff40413 addi s0,s0,-1 +8000b0b8: fffc8c93 addi s9,s9,-1 +8000b0bc: 0e812703 lw a4,232(sp) +8000b0c0: 014787b3 add a5,a5,s4 +8000b0c4: 0158a023 sw s5,0(a7) +8000b0c8: 00170713 addi a4,a4,1 +8000b0cc: 0148a223 sw s4,4(a7) +8000b0d0: 0ef12623 sw a5,236(sp) +8000b0d4: 0ee12423 sw a4,232(sp) +8000b0d8: 00888893 addi a7,a7,8 +8000b0dc: 14e4c463 blt s1,a4,8000b224 <_svfprintf_r+0x1854> +8000b0e0: 00044683 lbu a3,0(s0) +8000b0e4: 41bb8633 sub a2,s7,s11 +8000b0e8: 00068c13 mv s8,a3 +8000b0ec: 00d65463 bge a2,a3,8000b0f4 <_svfprintf_r+0x1724> +8000b0f0: 00060c13 mv s8,a2 +8000b0f4: 03805663 blez s8,8000b120 <_svfprintf_r+0x1750> +8000b0f8: 0e812683 lw a3,232(sp) +8000b0fc: 018787b3 add a5,a5,s8 +8000b100: 01b8a023 sw s11,0(a7) +8000b104: 00168693 addi a3,a3,1 +8000b108: 0188a223 sw s8,4(a7) +8000b10c: 0ef12623 sw a5,236(sp) +8000b110: 0ed12423 sw a3,232(sp) +8000b114: 34d4c063 blt s1,a3,8000b454 <_svfprintf_r+0x1a84> +8000b118: 00044683 lbu a3,0(s0) +8000b11c: 00888893 addi a7,a7,8 +8000b120: fffc4613 not a2,s8 +8000b124: 41f65613 srai a2,a2,0x1f +8000b128: 00cc7733 and a4,s8,a2 +8000b12c: 40e68c33 sub s8,a3,a4 +8000b130: 01804c63 bgtz s8,8000b148 <_svfprintf_r+0x1778> +8000b134: 00dd8db3 add s11,s11,a3 +8000b138: f60c9ce3 bnez s9,8000b0b0 <_svfprintf_r+0x16e0> +8000b13c: 72098c63 beqz s3,8000b874 <_svfprintf_r+0x1ea4> +8000b140: fff98993 addi s3,s3,-1 +8000b144: f79ff06f j 8000b0bc <_svfprintf_r+0x16ec> +8000b148: 0e812683 lw a3,232(sp) +8000b14c: 01894863 blt s2,s8,8000b15c <_svfprintf_r+0x178c> +8000b150: 0580006f j 8000b1a8 <_svfprintf_r+0x17d8> +8000b154: ff0c0c13 addi s8,s8,-16 +8000b158: 05895863 bge s2,s8,8000b1a8 <_svfprintf_r+0x17d8> +8000b15c: 00812703 lw a4,8(sp) +8000b160: 01078793 addi a5,a5,16 +8000b164: 00168693 addi a3,a3,1 +8000b168: 00e8a023 sw a4,0(a7) +8000b16c: 0128a223 sw s2,4(a7) +8000b170: 0ef12623 sw a5,236(sp) +8000b174: 0ed12423 sw a3,232(sp) +8000b178: 00888893 addi a7,a7,8 +8000b17c: fcd4dce3 bge s1,a3,8000b154 <_svfprintf_r+0x1784> +8000b180: 0e410613 addi a2,sp,228 +8000b184: 000b0593 mv a1,s6 +8000b188: 000d0513 mv a0,s10 +8000b18c: 52d030ef jal ra,8000eeb8 <__ssprint_r> +8000b190: 5a051c63 bnez a0,8000b748 <_svfprintf_r+0x1d78> +8000b194: ff0c0c13 addi s8,s8,-16 +8000b198: 0ec12783 lw a5,236(sp) +8000b19c: 0e812683 lw a3,232(sp) +8000b1a0: 10c10893 addi a7,sp,268 +8000b1a4: fb894ce3 blt s2,s8,8000b15c <_svfprintf_r+0x178c> +8000b1a8: 00812703 lw a4,8(sp) +8000b1ac: 018787b3 add a5,a5,s8 +8000b1b0: 00168693 addi a3,a3,1 +8000b1b4: 00e8a023 sw a4,0(a7) +8000b1b8: 0188a223 sw s8,4(a7) +8000b1bc: 0ef12623 sw a5,236(sp) +8000b1c0: 0ed12423 sw a3,232(sp) +8000b1c4: 76d4c463 blt s1,a3,8000b92c <_svfprintf_r+0x1f5c> +8000b1c8: 00044683 lbu a3,0(s0) +8000b1cc: 00888893 addi a7,a7,8 +8000b1d0: 00dd8db3 add s11,s11,a3 +8000b1d4: f65ff06f j 8000b138 <_svfprintf_r+0x1768> +8000b1d8: 01412683 lw a3,20(sp) +8000b1dc: 010a7793 andi a5,s4,16 +8000b1e0: 00468713 addi a4,a3,4 +8000b1e4: 20078463 beqz a5,8000b3ec <_svfprintf_r+0x1a1c> +8000b1e8: 0006a903 lw s2,0(a3) +8000b1ec: 00000c93 li s9,0 +8000b1f0: 00e12a23 sw a4,20(sp) +8000b1f4: d45ff06f j 8000af38 <_svfprintf_r+0x1568> +8000b1f8: 0e410613 addi a2,sp,228 +8000b1fc: 000c0593 mv a1,s8 +8000b200: 000d0513 mv a0,s10 +8000b204: 4b5030ef jal ra,8000eeb8 <__ssprint_r> +8000b208: fe051463 bnez a0,8000a9f0 <_svfprintf_r+0x1020> 8000b20c: 0e812683 lw a3,232(sp) -8000b210: 01894863 blt s2,s8,8000b220 <_svfprintf_r+0x178c> -8000b214: 0580006f j 8000b26c <_svfprintf_r+0x17d8> -8000b218: ff0c0c13 addi s8,s8,-16 -8000b21c: 05895863 bge s2,s8,8000b26c <_svfprintf_r+0x17d8> -8000b220: 00812703 lw a4,8(sp) -8000b224: 01078793 addi a5,a5,16 -8000b228: 00168693 addi a3,a3,1 -8000b22c: 00e8a023 sw a4,0(a7) -8000b230: 0128a223 sw s2,4(a7) -8000b234: 0ef12623 sw a5,236(sp) -8000b238: 0ed12423 sw a3,232(sp) -8000b23c: 00888893 addi a7,a7,8 -8000b240: fcd4dce3 bge s1,a3,8000b218 <_svfprintf_r+0x1784> -8000b244: 0e410613 addi a2,sp,228 -8000b248: 000b0593 mv a1,s6 -8000b24c: 000d0513 mv a0,s10 -8000b250: 52d030ef jal ra,8000ef7c <__ssprint_r> -8000b254: 5a051c63 bnez a0,8000b80c <_svfprintf_r+0x1d78> -8000b258: ff0c0c13 addi s8,s8,-16 -8000b25c: 0ec12783 lw a5,236(sp) -8000b260: 0e812683 lw a3,232(sp) -8000b264: 10c10893 addi a7,sp,268 -8000b268: fb894ce3 blt s2,s8,8000b220 <_svfprintf_r+0x178c> -8000b26c: 00812703 lw a4,8(sp) -8000b270: 018787b3 add a5,a5,s8 -8000b274: 00168693 addi a3,a3,1 -8000b278: 00e8a023 sw a4,0(a7) -8000b27c: 0188a223 sw s8,4(a7) -8000b280: 0ef12623 sw a5,236(sp) -8000b284: 0ed12423 sw a3,232(sp) -8000b288: 76d4c463 blt s1,a3,8000b9f0 <_svfprintf_r+0x1f5c> -8000b28c: 00044683 lbu a3,0(s0) -8000b290: 00888893 addi a7,a7,8 -8000b294: 00dd8db3 add s11,s11,a3 -8000b298: f65ff06f j 8000b1fc <_svfprintf_r+0x1768> -8000b29c: 01412683 lw a3,20(sp) -8000b2a0: 010a7793 andi a5,s4,16 -8000b2a4: 00468713 addi a4,a3,4 -8000b2a8: 20078463 beqz a5,8000b4b0 <_svfprintf_r+0x1a1c> -8000b2ac: 0006a903 lw s2,0(a3) -8000b2b0: 00000c93 li s9,0 -8000b2b4: 00e12a23 sw a4,20(sp) -8000b2b8: d45ff06f j 8000affc <_svfprintf_r+0x1568> -8000b2bc: 0e410613 addi a2,sp,228 -8000b2c0: 000c0593 mv a1,s8 -8000b2c4: 000d0513 mv a0,s10 -8000b2c8: 4b5030ef jal ra,8000ef7c <__ssprint_r> -8000b2cc: fe051463 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b2d0: 0e812683 lw a3,232(sp) -8000b2d4: 0ec12c83 lw s9,236(sp) -8000b2d8: 11410893 addi a7,sp,276 -8000b2dc: 00168693 addi a3,a3,1 -8000b2e0: 10c10913 addi s2,sp,268 -8000b2e4: fd5fe06f j 8000a2b8 <_svfprintf_r+0x824> -8000b2e8: 0e410613 addi a2,sp,228 -8000b2ec: 000b0593 mv a1,s6 -8000b2f0: 000d0513 mv a0,s10 -8000b2f4: 489030ef jal ra,8000ef7c <__ssprint_r> -8000b2f8: 50051a63 bnez a0,8000b80c <_svfprintf_r+0x1d78> -8000b2fc: 0ec12783 lw a5,236(sp) -8000b300: 10c10893 addi a7,sp,268 -8000b304: ea1ff06f j 8000b1a4 <_svfprintf_r+0x1710> -8000b308: 1b010b13 addi s6,sp,432 -8000b30c: 00000793 li a5,0 -8000b310: 00812823 sw s0,16(sp) -8000b314: 00912e23 sw s1,28(sp) -8000b318: 000b0413 mv s0,s6 -8000b31c: 03312223 sw s3,36(sp) -8000b320: 000c0b13 mv s6,s8 -8000b324: 00090493 mv s1,s2 -8000b328: 000c8993 mv s3,s9 -8000b32c: 400bfa13 andi s4,s7,1024 -8000b330: 03c12c83 lw s9,60(sp) -8000b334: 0ff00a93 li s5,255 -8000b338: 00088c13 mv s8,a7 -8000b33c: 00078913 mv s2,a5 -8000b340: 0240006f j 8000b364 <_svfprintf_r+0x18d0> -8000b344: 00a00613 li a2,10 -8000b348: 00000693 li a3,0 -8000b34c: 00048513 mv a0,s1 -8000b350: 00098593 mv a1,s3 -8000b354: 170050ef jal ra,800104c4 <__udivdi3> -8000b358: 4c098063 beqz s3,8000b818 <_svfprintf_r+0x1d84> -8000b35c: 00050493 mv s1,a0 -8000b360: 00058993 mv s3,a1 -8000b364: 00a00613 li a2,10 -8000b368: 00000693 li a3,0 -8000b36c: 00048513 mv a0,s1 -8000b370: 00098593 mv a1,s3 -8000b374: 584050ef jal ra,800108f8 <__umoddi3> -8000b378: 03050513 addi a0,a0,48 -8000b37c: fea40fa3 sb a0,-1(s0) -8000b380: 00190913 addi s2,s2,1 -8000b384: fff40413 addi s0,s0,-1 -8000b388: fa0a0ee3 beqz s4,8000b344 <_svfprintf_r+0x18b0> -8000b38c: 000cc683 lbu a3,0(s9) -8000b390: fad91ae3 bne s2,a3,8000b344 <_svfprintf_r+0x18b0> -8000b394: fb5908e3 beq s2,s5,8000b344 <_svfprintf_r+0x18b0> -8000b398: 42099a63 bnez s3,8000b7cc <_svfprintf_r+0x1d38> -8000b39c: 00900793 li a5,9 -8000b3a0: 4297e663 bltu a5,s1,8000b7cc <_svfprintf_r+0x1d38> -8000b3a4: 000c0893 mv a7,s8 -8000b3a8: 1b010793 addi a5,sp,432 -8000b3ac: 000b0c13 mv s8,s6 -8000b3b0: 00040b13 mv s6,s0 -8000b3b4: 03912e23 sw s9,60(sp) -8000b3b8: 01c12483 lw s1,28(sp) -8000b3bc: 02412983 lw s3,36(sp) -8000b3c0: 01012403 lw s0,16(sp) -8000b3c4: 03212023 sw s2,32(sp) -8000b3c8: 41678cb3 sub s9,a5,s6 -8000b3cc: 000b8a13 mv s4,s7 -8000b3d0: 96cff06f j 8000a53c <_svfprintf_r+0xaa8> -8000b3d4: 0e812683 lw a3,232(sp) -8000b3d8: 80015637 lui a2,0x80015 -8000b3dc: ca860613 addi a2,a2,-856 # 80014ca8 <__BSS_END__+0xffffe06c> -8000b3e0: 00c8a023 sw a2,0(a7) -8000b3e4: 00178793 addi a5,a5,1 -8000b3e8: 00100613 li a2,1 -8000b3ec: 00168693 addi a3,a3,1 -8000b3f0: 00c8a223 sw a2,4(a7) -8000b3f4: 0ef12623 sw a5,236(sp) -8000b3f8: 0ed12423 sw a3,232(sp) -8000b3fc: 00700613 li a2,7 -8000b400: 00888893 addi a7,a7,8 -8000b404: 06d64c63 blt a2,a3,8000b47c <_svfprintf_r+0x19e8> -8000b408: 20059863 bnez a1,8000b618 <_svfprintf_r+0x1b84> -8000b40c: 02012703 lw a4,32(sp) -8000b410: 001a7693 andi a3,s4,1 -8000b414: 00e6e6b3 or a3,a3,a4 -8000b418: 00069463 bnez a3,8000b420 <_svfprintf_r+0x198c> -8000b41c: 929fe06f j 80009d44 <_svfprintf_r+0x2b0> -8000b420: 03012683 lw a3,48(sp) -8000b424: 02c12703 lw a4,44(sp) -8000b428: 00700613 li a2,7 -8000b42c: 00d8a023 sw a3,0(a7) -8000b430: 0e812683 lw a3,232(sp) -8000b434: 00e787b3 add a5,a5,a4 -8000b438: 00e8a223 sw a4,4(a7) -8000b43c: 00168693 addi a3,a3,1 -8000b440: 0ef12623 sw a5,236(sp) -8000b444: 0ed12423 sw a3,232(sp) -8000b448: 4ad64e63 blt a2,a3,8000b904 <_svfprintf_r+0x1e70> -8000b44c: 00888893 addi a7,a7,8 -8000b450: 02012703 lw a4,32(sp) -8000b454: 00168693 addi a3,a3,1 -8000b458: 0168a023 sw s6,0(a7) -8000b45c: 00e787b3 add a5,a5,a4 -8000b460: 00e8a223 sw a4,4(a7) -8000b464: 0ef12623 sw a5,236(sp) -8000b468: 0ed12423 sw a3,232(sp) -8000b46c: 00700713 li a4,7 -8000b470: 00d74463 blt a4,a3,8000b478 <_svfprintf_r+0x19e4> -8000b474: 8cdfe06f j 80009d40 <_svfprintf_r+0x2ac> -8000b478: e65fe06f j 8000a2dc <_svfprintf_r+0x848> -8000b47c: 0e410613 addi a2,sp,228 -8000b480: 000c0593 mv a1,s8 -8000b484: 000d0513 mv a0,s10 -8000b488: 2f5030ef jal ra,8000ef7c <__ssprint_r> -8000b48c: e2051463 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b490: 0cc12583 lw a1,204(sp) -8000b494: 0ec12783 lw a5,236(sp) -8000b498: 10c10893 addi a7,sp,268 -8000b49c: f6dff06f j 8000b408 <_svfprintf_r+0x1974> -8000b4a0: 01012b83 lw s7,16(sp) -8000b4a4: 00040d13 mv s10,s0 -8000b4a8: 00048c13 mv s8,s1 -8000b4ac: e0cff06f j 8000aab8 <_svfprintf_r+0x1024> -8000b4b0: 040a7793 andi a5,s4,64 -8000b4b4: 22078c63 beqz a5,8000b6ec <_svfprintf_r+0x1c58> -8000b4b8: 01412783 lw a5,20(sp) -8000b4bc: 00000c93 li s9,0 -8000b4c0: 00e12a23 sw a4,20(sp) -8000b4c4: 0007d903 lhu s2,0(a5) -8000b4c8: b35ff06f j 8000affc <_svfprintf_r+0x1568> -8000b4cc: 0e410613 addi a2,sp,228 -8000b4d0: 000c0593 mv a1,s8 -8000b4d4: 000d0513 mv a0,s10 -8000b4d8: 2a5030ef jal ra,8000ef7c <__ssprint_r> -8000b4dc: dc051c63 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b4e0: 0ec12783 lw a5,236(sp) -8000b4e4: 10c10893 addi a7,sp,268 -8000b4e8: b90ff06f j 8000a878 <_svfprintf_r+0xde4> -8000b4ec: 00812683 lw a3,8(sp) -8000b4f0: 009787b3 add a5,a5,s1 -8000b4f4: 0098a223 sw s1,4(a7) -8000b4f8: 00d8a023 sw a3,0(a7) -8000b4fc: 00170713 addi a4,a4,1 -8000b500: 0ef12623 sw a5,236(sp) -8000b504: 0ee12423 sw a4,232(sp) -8000b508: 00700693 li a3,7 -8000b50c: 00e6c463 blt a3,a4,8000b514 <_svfprintf_r+0x1a80> -8000b510: 831fe06f j 80009d40 <_svfprintf_r+0x2ac> -8000b514: dc9fe06f j 8000a2dc <_svfprintf_r+0x848> -8000b518: 0e410613 addi a2,sp,228 -8000b51c: 000b0593 mv a1,s6 -8000b520: 000d0513 mv a0,s10 -8000b524: 259030ef jal ra,8000ef7c <__ssprint_r> -8000b528: 2e051263 bnez a0,8000b80c <_svfprintf_r+0x1d78> -8000b52c: 00044683 lbu a3,0(s0) -8000b530: 0ec12783 lw a5,236(sp) -8000b534: 10c10893 addi a7,sp,268 -8000b538: cadff06f j 8000b1e4 <_svfprintf_r+0x1750> -8000b53c: 0f012783 lw a5,240(sp) -8000b540: 0a010593 addi a1,sp,160 -8000b544: 0b010513 addi a0,sp,176 -8000b548: 0af12823 sw a5,176(sp) -8000b54c: 0f412783 lw a5,244(sp) -8000b550: 0a012023 sw zero,160(sp) -8000b554: 0a012223 sw zero,164(sp) -8000b558: 0af12a23 sw a5,180(sp) -8000b55c: 0f812783 lw a5,248(sp) -8000b560: 0a012423 sw zero,168(sp) -8000b564: 0a012623 sw zero,172(sp) -8000b568: 0af12c23 sw a5,184(sp) -8000b56c: 0fc12783 lw a5,252(sp) -8000b570: 0af12e23 sw a5,188(sp) -8000b574: 648060ef jal ra,80011bbc <__letf2> -8000b578: 01012883 lw a7,16(sp) -8000b57c: 52054263 bltz a0,8000baa0 <_svfprintf_r+0x200c> -8000b580: 0c714783 lbu a5,199(sp) -8000b584: 04700713 li a4,71 -8000b588: 28975e63 bge a4,s1,8000b824 <_svfprintf_r+0x1d90> -8000b58c: 80015737 lui a4,0x80015 -8000b590: c6c70b13 addi s6,a4,-916 # 80014c6c <__BSS_END__+0xffffe030> -8000b594: 00012823 sw zero,16(sp) -8000b598: 02012423 sw zero,40(sp) -8000b59c: 02012223 sw zero,36(sp) -8000b5a0: 00012e23 sw zero,28(sp) -8000b5a4: f7fa7a13 andi s4,s4,-129 -8000b5a8: 00300a93 li s5,3 -8000b5ac: 00300c93 li s9,3 -8000b5b0: 00000d93 li s11,0 -8000b5b4: 00078463 beqz a5,8000b5bc <_svfprintf_r+0x1b28> -8000b5b8: e79fe06f j 8000a430 <_svfprintf_r+0x99c> -8000b5bc: ebcfe06f j 80009c78 <_svfprintf_r+0x1e4> -8000b5c0: 00c12783 lw a5,12(sp) -8000b5c4: 00040b13 mv s6,s0 -8000b5c8: 00f72023 sw a5,0(a4) -8000b5cc: fc0fe06f j 80009d8c <_svfprintf_r+0x2f8> -8000b5d0: 000b0513 mv a0,s6 -8000b5d4: 05912023 sw s9,64(sp) -8000b5d8: b88fe0ef jal ra,80009960 -8000b5dc: 0c714783 lbu a5,199(sp) -8000b5e0: fff54a93 not s5,a0 -8000b5e4: 41fada93 srai s5,s5,0x1f -8000b5e8: 01212a23 sw s2,20(sp) -8000b5ec: 00012823 sw zero,16(sp) -8000b5f0: 02012423 sw zero,40(sp) -8000b5f4: 02012223 sw zero,36(sp) -8000b5f8: 00012e23 sw zero,28(sp) -8000b5fc: 04012883 lw a7,64(sp) -8000b600: 00050c93 mv s9,a0 -8000b604: 01557ab3 and s5,a0,s5 -8000b608: 00000d93 li s11,0 -8000b60c: 00078463 beqz a5,8000b614 <_svfprintf_r+0x1b80> -8000b610: e21fe06f j 8000a430 <_svfprintf_r+0x99c> -8000b614: e64fe06f j 80009c78 <_svfprintf_r+0x1e4> -8000b618: 03012683 lw a3,48(sp) -8000b61c: 02c12703 lw a4,44(sp) -8000b620: 00700613 li a2,7 -8000b624: 00d8a023 sw a3,0(a7) -8000b628: 0e812683 lw a3,232(sp) -8000b62c: 00e787b3 add a5,a5,a4 -8000b630: 00e8a223 sw a4,4(a7) -8000b634: 00168693 addi a3,a3,1 -8000b638: 0ef12623 sw a5,236(sp) -8000b63c: 0ed12423 sw a3,232(sp) -8000b640: 00888893 addi a7,a7,8 -8000b644: 2cd64063 blt a2,a3,8000b904 <_svfprintf_r+0x1e70> -8000b648: e005d4e3 bgez a1,8000b450 <_svfprintf_r+0x19bc> -8000b64c: ff000613 li a2,-16 -8000b650: 40b004b3 neg s1,a1 -8000b654: 26c5d4e3 bge a1,a2,8000c0bc <_svfprintf_r+0x2628> -8000b658: 01000913 li s2,16 -8000b65c: 00700c93 li s9,7 -8000b660: 00c0006f j 8000b66c <_svfprintf_r+0x1bd8> -8000b664: ff048493 addi s1,s1,-16 -8000b668: 24995ae3 bge s2,s1,8000c0bc <_svfprintf_r+0x2628> -8000b66c: 00812703 lw a4,8(sp) -8000b670: 01078793 addi a5,a5,16 -8000b674: 00168693 addi a3,a3,1 -8000b678: 00e8a023 sw a4,0(a7) -8000b67c: 0128a223 sw s2,4(a7) -8000b680: 0ef12623 sw a5,236(sp) -8000b684: 0ed12423 sw a3,232(sp) -8000b688: 00888893 addi a7,a7,8 -8000b68c: fcdcdce3 bge s9,a3,8000b664 <_svfprintf_r+0x1bd0> -8000b690: 0e410613 addi a2,sp,228 -8000b694: 000c0593 mv a1,s8 -8000b698: 000d0513 mv a0,s10 -8000b69c: 0e1030ef jal ra,8000ef7c <__ssprint_r> -8000b6a0: c0051a63 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b6a4: 0ec12783 lw a5,236(sp) -8000b6a8: 0e812683 lw a3,232(sp) -8000b6ac: 10c10893 addi a7,sp,268 -8000b6b0: fb5ff06f j 8000b664 <_svfprintf_r+0x1bd0> -8000b6b4: 00148693 addi a3,s1,1 -8000b6b8: 00890713 addi a4,s2,8 -8000b6bc: 00812783 lw a5,8(sp) -8000b6c0: 01bc8cb3 add s9,s9,s11 -8000b6c4: 01b92223 sw s11,4(s2) -8000b6c8: 00f92023 sw a5,0(s2) -8000b6cc: 0f912623 sw s9,236(sp) -8000b6d0: 0ed12423 sw a3,232(sp) -8000b6d4: 00700793 li a5,7 -8000b6d8: bed7c2e3 blt a5,a3,8000b2bc <_svfprintf_r+0x1828> -8000b6dc: 00168693 addi a3,a3,1 -8000b6e0: 00870893 addi a7,a4,8 -8000b6e4: 00070913 mv s2,a4 -8000b6e8: bd1fe06f j 8000a2b8 <_svfprintf_r+0x824> -8000b6ec: 200a7793 andi a5,s4,512 -8000b6f0: 1c078e63 beqz a5,8000b8cc <_svfprintf_r+0x1e38> -8000b6f4: 01412783 lw a5,20(sp) -8000b6f8: 00000c93 li s9,0 -8000b6fc: 00e12a23 sw a4,20(sp) -8000b700: 0007c903 lbu s2,0(a5) -8000b704: 8f9ff06f j 8000affc <_svfprintf_r+0x1568> -8000b708: 200a7793 andi a5,s4,512 -8000b70c: 1a078463 beqz a5,8000b8b4 <_svfprintf_r+0x1e20> -8000b710: 01412783 lw a5,20(sp) -8000b714: 00e12a23 sw a4,20(sp) -8000b718: 00078903 lb s2,0(a5) -8000b71c: 41f95c93 srai s9,s2,0x1f -8000b720: 000c8793 mv a5,s9 -8000b724: fa5fe06f j 8000a6c8 <_svfprintf_r+0xc34> -8000b728: 200bf793 andi a5,s7,512 -8000b72c: 16078863 beqz a5,8000b89c <_svfprintf_r+0x1e08> -8000b730: 01412783 lw a5,20(sp) -8000b734: 00000c93 li s9,0 -8000b738: 00e12a23 sw a4,20(sp) -8000b73c: 0007c903 lbu s2,0(a5) -8000b740: 00100793 li a5,1 -8000b744: dcdfe06f j 8000a510 <_svfprintf_r+0xa7c> -8000b748: 200a7793 andi a5,s4,512 -8000b74c: 12078e63 beqz a5,8000b888 <_svfprintf_r+0x1df4> -8000b750: 01412783 lw a5,20(sp) -8000b754: 00000c93 li s9,0 -8000b758: 00e12a23 sw a4,20(sp) -8000b75c: 0007c903 lbu s2,0(a5) -8000b760: e31fe06f j 8000a590 <_svfprintf_r+0xafc> -8000b764: 0fc12783 lw a5,252(sp) -8000b768: 1807c863 bltz a5,8000b8f8 <_svfprintf_r+0x1e64> -8000b76c: 0c714783 lbu a5,199(sp) -8000b770: 04700713 li a4,71 -8000b774: 46975c63 bge a4,s1,8000bbec <_svfprintf_r+0x2158> -8000b778: 80015737 lui a4,0x80015 -8000b77c: c7470b13 addi s6,a4,-908 # 80014c74 <__BSS_END__+0xffffe038> -8000b780: e15ff06f j 8000b594 <_svfprintf_r+0x1b00> -8000b784: 00812703 lw a4,8(sp) -8000b788: 009787b3 add a5,a5,s1 -8000b78c: 00168693 addi a3,a3,1 -8000b790: 00e8a023 sw a4,0(a7) -8000b794: 0098a223 sw s1,4(a7) -8000b798: 0ef12623 sw a5,236(sp) -8000b79c: 0ed12423 sw a3,232(sp) -8000b7a0: 00700613 li a2,7 -8000b7a4: 00888893 addi a7,a7,8 -8000b7a8: c8d65663 bge a2,a3,8000ac34 <_svfprintf_r+0x11a0> -8000b7ac: 0e410613 addi a2,sp,228 -8000b7b0: 000c0593 mv a1,s8 -8000b7b4: 000d0513 mv a0,s10 -8000b7b8: 7c4030ef jal ra,8000ef7c <__ssprint_r> -8000b7bc: ae051c63 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b7c0: 0ec12783 lw a5,236(sp) -8000b7c4: 10c10893 addi a7,sp,268 -8000b7c8: c6cff06f j 8000ac34 <_svfprintf_r+0x11a0> -8000b7cc: 04812783 lw a5,72(sp) -8000b7d0: 04c12583 lw a1,76(sp) -8000b7d4: 00000913 li s2,0 -8000b7d8: 40f40433 sub s0,s0,a5 -8000b7dc: 00078613 mv a2,a5 -8000b7e0: 00040513 mv a0,s0 -8000b7e4: a08fe0ef jal ra,800099ec -8000b7e8: 001cc583 lbu a1,1(s9) -8000b7ec: 00a00613 li a2,10 -8000b7f0: 00000693 li a3,0 -8000b7f4: 00b03833 snez a6,a1 -8000b7f8: 00048513 mv a0,s1 -8000b7fc: 00098593 mv a1,s3 -8000b800: 010c8cb3 add s9,s9,a6 -8000b804: 4c1040ef jal ra,800104c4 <__udivdi3> -8000b808: b55ff06f j 8000b35c <_svfprintf_r+0x18c8> -8000b80c: 01012b83 lw s7,16(sp) -8000b810: 000b0c13 mv s8,s6 -8000b814: aa4ff06f j 8000aab8 <_svfprintf_r+0x1024> -8000b818: 00900793 li a5,9 -8000b81c: b497e0e3 bltu a5,s1,8000b35c <_svfprintf_r+0x18c8> -8000b820: b85ff06f j 8000b3a4 <_svfprintf_r+0x1910> -8000b824: 80015737 lui a4,0x80015 -8000b828: c6870b13 addi s6,a4,-920 # 80014c68 <__BSS_END__+0xffffe02c> -8000b82c: d69ff06f j 8000b594 <_svfprintf_r+0x1b00> -8000b830: 0e410613 addi a2,sp,228 -8000b834: 000c0593 mv a1,s8 -8000b838: 000d0513 mv a0,s10 -8000b83c: 740030ef jal ra,8000ef7c <__ssprint_r> -8000b840: a6051a63 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b844: 0ec12783 lw a5,236(sp) -8000b848: 10c10893 addi a7,sp,268 -8000b84c: bd0ff06f j 8000ac1c <_svfprintf_r+0x1188> -8000b850: 00600c93 li s9,6 -8000b854: 865ff06f j 8000b0b8 <_svfprintf_r+0x1624> -8000b858: 02012683 lw a3,32(sp) -8000b85c: 00db0733 add a4,s6,a3 -8000b860: 409684b3 sub s1,a3,s1 -8000b864: 41b70833 sub a6,a4,s11 -8000b868: 00048913 mv s2,s1 -8000b86c: c6985263 bge a6,s1,8000acd0 <_svfprintf_r+0x123c> -8000b870: 00080913 mv s2,a6 -8000b874: c5cff06f j 8000acd0 <_svfprintf_r+0x123c> -8000b878: 00c12783 lw a5,12(sp) -8000b87c: 00040b13 mv s6,s0 -8000b880: 00f71023 sh a5,0(a4) -8000b884: d08fe06f j 80009d8c <_svfprintf_r+0x2f8> -8000b888: 01412783 lw a5,20(sp) -8000b88c: 00000c93 li s9,0 -8000b890: 00e12a23 sw a4,20(sp) -8000b894: 0007a903 lw s2,0(a5) -8000b898: cf9fe06f j 8000a590 <_svfprintf_r+0xafc> -8000b89c: 01412783 lw a5,20(sp) -8000b8a0: 00000c93 li s9,0 -8000b8a4: 00e12a23 sw a4,20(sp) -8000b8a8: 0007a903 lw s2,0(a5) -8000b8ac: 00100793 li a5,1 -8000b8b0: c61fe06f j 8000a510 <_svfprintf_r+0xa7c> -8000b8b4: 01412783 lw a5,20(sp) -8000b8b8: 00e12a23 sw a4,20(sp) -8000b8bc: 0007a903 lw s2,0(a5) -8000b8c0: 41f95c93 srai s9,s2,0x1f -8000b8c4: 000c8793 mv a5,s9 -8000b8c8: e01fe06f j 8000a6c8 <_svfprintf_r+0xc34> -8000b8cc: 01412783 lw a5,20(sp) -8000b8d0: 00000c93 li s9,0 -8000b8d4: 00e12a23 sw a4,20(sp) -8000b8d8: 0007a903 lw s2,0(a5) -8000b8dc: f20ff06f j 8000affc <_svfprintf_r+0x1568> -8000b8e0: 0e410613 addi a2,sp,228 -8000b8e4: 000c0593 mv a1,s8 -8000b8e8: 000d0513 mv a0,s10 -8000b8ec: 690030ef jal ra,8000ef7c <__ssprint_r> -8000b8f0: 00cc5703 lhu a4,12(s8) -8000b8f4: cb0fe06f j 80009da4 <_svfprintf_r+0x310> -8000b8f8: 02d00793 li a5,45 -8000b8fc: 0cf103a3 sb a5,199(sp) -8000b900: e71ff06f j 8000b770 <_svfprintf_r+0x1cdc> -8000b904: 0e410613 addi a2,sp,228 -8000b908: 000c0593 mv a1,s8 -8000b90c: 000d0513 mv a0,s10 -8000b910: 66c030ef jal ra,8000ef7c <__ssprint_r> -8000b914: 9a051063 bnez a0,8000aab4 <_svfprintf_r+0x1020> -8000b918: 0cc12583 lw a1,204(sp) -8000b91c: 0ec12783 lw a5,236(sp) -8000b920: 0e812683 lw a3,232(sp) -8000b924: 10c10893 addi a7,sp,268 -8000b928: b205d4e3 bgez a1,8000b450 <_svfprintf_r+0x19bc> -8000b92c: d21ff06f j 8000b64c <_svfprintf_r+0x1bb8> -8000b930: 00600d93 li s11,6 -8000b934: df8fe06f j 80009f2c <_svfprintf_r+0x498> -8000b938: 02012703 lw a4,32(sp) -8000b93c: 000b0c13 mv s8,s6 -8000b940: 02812b03 lw s6,40(sp) -8000b944: 02812e23 sw s0,60(sp) -8000b948: 01c12a03 lw s4,28(sp) -8000b94c: 00eb06b3 add a3,s6,a4 -8000b950: 04012403 lw s0,64(sp) -8000b954: 04412983 lw s3,68(sp) -8000b958: 02412a83 lw s5,36(sp) -8000b95c: afb6f463 bgeu a3,s11,8000ac44 <_svfprintf_r+0x11b0> -8000b960: 00068d93 mv s11,a3 -8000b964: ae0ff06f j 8000ac44 <_svfprintf_r+0x11b0> -8000b968: 01c12703 lw a4,28(sp) -8000b96c: ffd00793 li a5,-3 -8000b970: 00f74463 blt a4,a5,8000b978 <_svfprintf_r+0x1ee4> -8000b974: 00edda63 bge s11,a4,8000b988 <_svfprintf_r+0x1ef4> -8000b978: ffe48493 addi s1,s1,-2 -8000b97c: fdf4f793 andi a5,s1,-33 -8000b980: 04f12a23 sw a5,84(sp) -8000b984: ee4fe06f j 8000a068 <_svfprintf_r+0x5d4> -8000b988: 02012783 lw a5,32(sp) -8000b98c: 01c12703 lw a4,28(sp) -8000b990: 26f74463 blt a4,a5,8000bbf8 <_svfprintf_r+0x2164> -8000b994: 02812783 lw a5,40(sp) -8000b998: 00070c93 mv s9,a4 -8000b99c: 0017f793 andi a5,a5,1 -8000b9a0: 00078663 beqz a5,8000b9ac <_svfprintf_r+0x1f18> -8000b9a4: 02c12783 lw a5,44(sp) -8000b9a8: 00f70cb3 add s9,a4,a5 -8000b9ac: 02812783 lw a5,40(sp) -8000b9b0: 4007f793 andi a5,a5,1024 -8000b9b4: 00078663 beqz a5,8000b9c0 <_svfprintf_r+0x1f2c> -8000b9b8: 01c12783 lw a5,28(sp) -8000b9bc: 12f04ae3 bgtz a5,8000c2f0 <_svfprintf_r+0x285c> -8000b9c0: fffcca93 not s5,s9 -8000b9c4: 41fada93 srai s5,s5,0x1f -8000b9c8: 015cfab3 and s5,s9,s5 -8000b9cc: 06700493 li s1,103 -8000b9d0: 02012423 sw zero,40(sp) -8000b9d4: 02012223 sw zero,36(sp) -8000b9d8: facfe06f j 8000a184 <_svfprintf_r+0x6f0> -8000b9dc: 0c714783 lbu a5,199(sp) -8000b9e0: 00000d93 li s11,0 -8000b9e4: 00078463 beqz a5,8000b9ec <_svfprintf_r+0x1f58> -8000b9e8: a49fe06f j 8000a430 <_svfprintf_r+0x99c> -8000b9ec: a8cfe06f j 80009c78 <_svfprintf_r+0x1e4> -8000b9f0: 0e410613 addi a2,sp,228 -8000b9f4: 000b0593 mv a1,s6 -8000b9f8: 000d0513 mv a0,s10 -8000b9fc: 580030ef jal ra,8000ef7c <__ssprint_r> -8000ba00: e00516e3 bnez a0,8000b80c <_svfprintf_r+0x1d78> -8000ba04: 00044683 lbu a3,0(s0) -8000ba08: 0ec12783 lw a5,236(sp) -8000ba0c: 10c10893 addi a7,sp,268 -8000ba10: 00dd8db3 add s11,s11,a3 -8000ba14: fe8ff06f j 8000b1fc <_svfprintf_r+0x1768> -8000ba18: 0b010a93 addi s5,sp,176 -8000ba1c: 0dc10813 addi a6,sp,220 -8000ba20: 0d010793 addi a5,sp,208 -8000ba24: 0cc10713 addi a4,sp,204 -8000ba28: 000d8693 mv a3,s11 -8000ba2c: 00300613 li a2,3 -8000ba30: 000a8593 mv a1,s5 -8000ba34: 000d0513 mv a0,s10 -8000ba38: 05112223 sw a7,68(sp) -8000ba3c: 0bc12823 sw t3,176(sp) -8000ba40: 05c12023 sw t3,64(sp) -8000ba44: 0bd12a23 sw t4,180(sp) -8000ba48: 03d12223 sw t4,36(sp) -8000ba4c: 0be12c23 sw t5,184(sp) -8000ba50: 03e12023 sw t5,32(sp) -8000ba54: 0a612e23 sw t1,188(sp) -8000ba58: 00612e23 sw t1,28(sp) -8000ba5c: c49fa0ef jal ra,800066a4 <_ldtoa_r> -8000ba60: 01c12303 lw t1,28(sp) -8000ba64: 02012f03 lw t5,32(sp) -8000ba68: 02412e83 lw t4,36(sp) -8000ba6c: 04012e03 lw t3,64(sp) -8000ba70: 04412883 lw a7,68(sp) -8000ba74: 00050b13 mv s6,a0 -8000ba78: 04600793 li a5,70 -8000ba7c: 01bb0933 add s2,s6,s11 -8000ba80: 62fb9a63 bne s7,a5,8000c0b4 <_svfprintf_r+0x2620> -8000ba84: 000b4683 lbu a3,0(s6) -8000ba88: 03000793 li a5,48 -8000ba8c: 10f686e3 beq a3,a5,8000c398 <_svfprintf_r+0x2904> -8000ba90: 0a010c93 addi s9,sp,160 -8000ba94: 0cc12783 lw a5,204(sp) -8000ba98: 00f90933 add s2,s2,a5 -8000ba9c: d40fe06f j 80009fdc <_svfprintf_r+0x548> -8000baa0: 02d00793 li a5,45 -8000baa4: 0cf103a3 sb a5,199(sp) -8000baa8: addff06f j 8000b584 <_svfprintf_r+0x1af0> -8000baac: 0b010a93 addi s5,sp,176 -8000bab0: 0d010793 addi a5,sp,208 -8000bab4: 0dc10813 addi a6,sp,220 -8000bab8: 0cc10713 addi a4,sp,204 -8000babc: 000d8693 mv a3,s11 -8000bac0: 00200613 li a2,2 -8000bac4: 000a8593 mv a1,s5 -8000bac8: 000d0513 mv a0,s10 -8000bacc: 0bc12823 sw t3,176(sp) -8000bad0: 05c12023 sw t3,64(sp) -8000bad4: 0bd12a23 sw t4,180(sp) -8000bad8: 03d12223 sw t4,36(sp) -8000badc: 0be12c23 sw t5,184(sp) -8000bae0: 03e12023 sw t5,32(sp) -8000bae4: 0a612e23 sw t1,188(sp) -8000bae8: 00612e23 sw t1,28(sp) -8000baec: bb9fa0ef jal ra,800066a4 <_ldtoa_r> -8000baf0: 04700793 li a5,71 -8000baf4: 01c12303 lw t1,28(sp) -8000baf8: 02012f03 lw t5,32(sp) -8000bafc: 02412e83 lw t4,36(sp) -8000bb00: 04012e03 lw t3,64(sp) -8000bb04: 04412883 lw a7,68(sp) -8000bb08: 00050b13 mv s6,a0 -8000bb0c: f6fb96e3 bne s7,a5,8000ba78 <_svfprintf_r+0x1fe4> -8000bb10: 02812783 lw a5,40(sp) -8000bb14: 0017f793 andi a5,a5,1 -8000bb18: 58079863 bnez a5,8000c0a8 <_svfprintf_r+0x2614> -8000bb1c: 04700793 li a5,71 -8000bb20: 0dc12703 lw a4,220(sp) -8000bb24: 04f12a23 sw a5,84(sp) -8000bb28: d10fe06f j 8000a038 <_svfprintf_r+0x5a4> -8000bb2c: 0e410613 addi a2,sp,228 -8000bb30: 000c0593 mv a1,s8 -8000bb34: 000d0513 mv a0,s10 -8000bb38: 444030ef jal ra,8000ef7c <__ssprint_r> -8000bb3c: 00050463 beqz a0,8000bb44 <_svfprintf_r+0x20b0> -8000bb40: f75fe06f j 8000aab4 <_svfprintf_r+0x1020> -8000bb44: 0cc12483 lw s1,204(sp) -8000bb48: 0ec12783 lw a5,236(sp) -8000bb4c: 10c10893 addi a7,sp,268 -8000bb50: 938ff06f j 8000ac88 <_svfprintf_r+0x11f4> -8000bb54: 0c714783 lbu a5,199(sp) -8000bb58: 01212a23 sw s2,20(sp) -8000bb5c: 02012423 sw zero,40(sp) -8000bb60: 02012223 sw zero,36(sp) -8000bb64: 00012e23 sw zero,28(sp) -8000bb68: 000d8a93 mv s5,s11 -8000bb6c: 000d8c93 mv s9,s11 -8000bb70: 00000d93 li s11,0 -8000bb74: 00078463 beqz a5,8000bb7c <_svfprintf_r+0x20e8> -8000bb78: 8b9fe06f j 8000a430 <_svfprintf_r+0x99c> -8000bb7c: 8fcfe06f j 80009c78 <_svfprintf_r+0x1e4> -8000bb80: 0e410613 addi a2,sp,228 -8000bb84: 000c0593 mv a1,s8 -8000bb88: 000d0513 mv a0,s10 -8000bb8c: 3f0030ef jal ra,8000ef7c <__ssprint_r> -8000bb90: 00050463 beqz a0,8000bb98 <_svfprintf_r+0x2104> -8000bb94: f21fe06f j 8000aab4 <_svfprintf_r+0x1020> -8000bb98: 0cc12483 lw s1,204(sp) -8000bb9c: 02012703 lw a4,32(sp) -8000bba0: 0ec12783 lw a5,236(sp) -8000bba4: 10c10893 addi a7,sp,268 -8000bba8: 409704b3 sub s1,a4,s1 -8000bbac: 924ff06f j 8000acd0 <_svfprintf_r+0x123c> -8000bbb0: 02812783 lw a5,40(sp) -8000bbb4: 01c12703 lw a4,28(sp) -8000bbb8: 0017f793 andi a5,a5,1 -8000bbbc: 01b7e7b3 or a5,a5,s11 -8000bbc0: 04e054e3 blez a4,8000c408 <_svfprintf_r+0x2974> -8000bbc4: 7a079663 bnez a5,8000c370 <_svfprintf_r+0x28dc> -8000bbc8: 01c12c83 lw s9,28(sp) -8000bbcc: 06600493 li s1,102 -8000bbd0: 02812783 lw a5,40(sp) -8000bbd4: 4007f793 andi a5,a5,1024 -8000bbd8: 70079e63 bnez a5,8000c2f4 <_svfprintf_r+0x2860> -8000bbdc: fffcca93 not s5,s9 -8000bbe0: 41fada93 srai s5,s5,0x1f -8000bbe4: 015cfab3 and s5,s9,s5 -8000bbe8: de9ff06f j 8000b9d0 <_svfprintf_r+0x1f3c> -8000bbec: 80015737 lui a4,0x80015 -8000bbf0: c7070b13 addi s6,a4,-912 # 80014c70 <__BSS_END__+0xffffe034> -8000bbf4: 9a1ff06f j 8000b594 <_svfprintf_r+0x1b00> -8000bbf8: 02012783 lw a5,32(sp) -8000bbfc: 02c12703 lw a4,44(sp) -8000bc00: 06700493 li s1,103 -8000bc04: 00e78cb3 add s9,a5,a4 -8000bc08: 01c12783 lw a5,28(sp) -8000bc0c: fcf042e3 bgtz a5,8000bbd0 <_svfprintf_r+0x213c> -8000bc10: 40fc8cb3 sub s9,s9,a5 -8000bc14: 001c8c93 addi s9,s9,1 -8000bc18: fffcca93 not s5,s9 -8000bc1c: 41fada93 srai s5,s5,0x1f -8000bc20: 015cfab3 and s5,s9,s5 -8000bc24: dadff06f j 8000b9d0 <_svfprintf_r+0x1f3c> -8000bc28: 800156b7 lui a3,0x80015 -8000bc2c: 34c68e93 addi t4,a3,844 # 8001534c <__BSS_END__+0xffffe710> -8000bc30: f48fe06f j 8000a378 <_svfprintf_r+0x8e4> -8000bc34: 03000793 li a5,48 -8000bc38: 0cf10423 sb a5,200(sp) -8000bc3c: 05800793 li a5,88 -8000bc40: 002a6713 ori a4,s4,2 -8000bc44: 0cf104a3 sb a5,201(sp) -8000bc48: 02e12423 sw a4,40(sp) -8000bc4c: 06300793 li a5,99 -8000bc50: 00012823 sw zero,16(sp) -8000bc54: 14c10b13 addi s6,sp,332 -8000bc58: 41b7ce63 blt a5,s11,8000c074 <_svfprintf_r+0x25e0> -8000bc5c: 0fc12303 lw t1,252(sp) -8000bc60: fdf4fb93 andi s7,s1,-33 -8000bc64: 05712a23 sw s7,84(sp) -8000bc68: 04012c23 sw zero,88(sp) -8000bc6c: 0f012e03 lw t3,240(sp) -8000bc70: 0f412e83 lw t4,244(sp) -8000bc74: 0f812f03 lw t5,248(sp) -8000bc78: 102a6a13 ori s4,s4,258 -8000bc7c: 38034263 bltz t1,8000c000 <_svfprintf_r+0x256c> -8000bc80: 06100793 li a5,97 -8000bc84: 54f48e63 beq s1,a5,8000c1e0 <_svfprintf_r+0x274c> -8000bc88: 04100793 li a5,65 -8000bc8c: 00f48463 beq s1,a5,8000bc94 <_svfprintf_r+0x2200> -8000bc90: ac8fe06f j 80009f58 <_svfprintf_r+0x4c4> -8000bc94: 0b010a93 addi s5,sp,176 -8000bc98: 000a8513 mv a0,s5 -8000bc9c: 05112823 sw a7,80(sp) -8000bca0: 0bc12823 sw t3,176(sp) -8000bca4: 0bd12a23 sw t4,180(sp) -8000bca8: 0be12c23 sw t5,184(sp) -8000bcac: 0a612e23 sw t1,188(sp) -8000bcb0: 1cd080ef jal ra,8001467c <__trunctfdf2> -8000bcb4: 0cc10613 addi a2,sp,204 -8000bcb8: 8b5fd0ef jal ra,8000956c -8000bcbc: 00058613 mv a2,a1 -8000bcc0: 00050593 mv a1,a0 -8000bcc4: 000a8513 mv a0,s5 -8000bcc8: 7c0080ef jal ra,80014488 <__extenddftf2> -8000bccc: 0b012783 lw a5,176(sp) -8000bcd0: 0a010c93 addi s9,sp,160 -8000bcd4: 09010913 addi s2,sp,144 -8000bcd8: 08f12823 sw a5,144(sp) -8000bcdc: 0b412783 lw a5,180(sp) -8000bce0: 08010613 addi a2,sp,128 -8000bce4: 00090593 mv a1,s2 -8000bce8: 08f12a23 sw a5,148(sp) -8000bcec: 0b812783 lw a5,184(sp) -8000bcf0: 000c8513 mv a0,s9 -8000bcf4: 04c12023 sw a2,64(sp) -8000bcf8: 08f12c23 sw a5,152(sp) -8000bcfc: 0bc12783 lw a5,188(sp) -8000bd00: 08012023 sw zero,128(sp) -8000bd04: 08012223 sw zero,132(sp) -8000bd08: 08f12e23 sw a5,156(sp) -8000bd0c: 3ffc07b7 lui a5,0x3ffc0 -8000bd10: 08f12623 sw a5,140(sp) -8000bd14: 08012423 sw zero,136(sp) -8000bd18: 7e9050ef jal ra,80011d00 <__multf3> -8000bd1c: 0a012803 lw a6,160(sp) -8000bd20: 0a412e03 lw t3,164(sp) -8000bd24: 0a812e83 lw t4,168(sp) -8000bd28: 0ac12f03 lw t5,172(sp) -8000bd2c: 000c8593 mv a1,s9 -8000bd30: 000a8513 mv a0,s5 -8000bd34: 0b012823 sw a6,176(sp) -8000bd38: 05012223 sw a6,68(sp) -8000bd3c: 0bc12a23 sw t3,180(sp) -8000bd40: 03c12223 sw t3,36(sp) -8000bd44: 0bd12c23 sw t4,184(sp) -8000bd48: 03d12023 sw t4,32(sp) -8000bd4c: 0be12e23 sw t5,188(sp) -8000bd50: 01e12e23 sw t5,28(sp) -8000bd54: 0a012023 sw zero,160(sp) -8000bd58: 0a012223 sw zero,164(sp) -8000bd5c: 0a012423 sw zero,168(sp) -8000bd60: 0a012623 sw zero,172(sp) -8000bd64: 449050ef jal ra,800119ac <__eqtf2> -8000bd68: 01c12f03 lw t5,28(sp) -8000bd6c: 02012e83 lw t4,32(sp) -8000bd70: 02412e03 lw t3,36(sp) -8000bd74: 04412803 lw a6,68(sp) -8000bd78: 05012883 lw a7,80(sp) -8000bd7c: 00051663 bnez a0,8000bd88 <_svfprintf_r+0x22f4> -8000bd80: 00100793 li a5,1 -8000bd84: 0cf12623 sw a5,204(sp) -8000bd88: 800157b7 lui a5,0x80015 -8000bd8c: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> -8000bd90: 02f12223 sw a5,36(sp) -8000bd94: fffd8693 addi a3,s11,-1 -8000bd98: 05412e23 sw s4,92(sp) -8000bd9c: 06912223 sw s1,100(sp) -8000bda0: 07b12623 sw s11,108(sp) -8000bda4: 07a12a23 sw s10,116(sp) -8000bda8: 07812c23 sw s8,120(sp) -8000bdac: 000b0b93 mv s7,s6 -8000bdb0: 06812023 sw s0,96(sp) -8000bdb4: 07312423 sw s3,104(sp) -8000bdb8: 07112823 sw a7,112(sp) -8000bdbc: 00068c13 mv s8,a3 -8000bdc0: 07612e23 sw s6,124(sp) -8000bdc4: 00080d13 mv s10,a6 -8000bdc8: 000e0d93 mv s11,t3 -8000bdcc: 000e8493 mv s1,t4 -8000bdd0: 000f0a13 mv s4,t5 -8000bdd4: 0480006f j 8000be1c <_svfprintf_r+0x2388> -8000bdd8: 000c8593 mv a1,s9 -8000bddc: 000a8513 mv a0,s5 -8000bde0: 02c12023 sw a2,32(sp) -8000bde4: 01f12e23 sw t6,28(sp) -8000bde8: 0bf12c23 sw t6,184(sp) -8000bdec: 0ac12e23 sw a2,188(sp) -8000bdf0: 0b612823 sw s6,176(sp) -8000bdf4: 0b312a23 sw s3,180(sp) -8000bdf8: 0a012023 sw zero,160(sp) -8000bdfc: 0a012223 sw zero,164(sp) -8000be00: 0a012423 sw zero,168(sp) -8000be04: 0a012623 sw zero,172(sp) -8000be08: 3a5050ef jal ra,800119ac <__eqtf2> -8000be0c: 01c12f83 lw t6,28(sp) -8000be10: 02012603 lw a2,32(sp) -8000be14: fffc0c13 addi s8,s8,-1 -8000be18: 0e050263 beqz a0,8000befc <_svfprintf_r+0x2468> -8000be1c: 400307b7 lui a5,0x40030 -8000be20: 00090613 mv a2,s2 -8000be24: 000c8593 mv a1,s9 -8000be28: 000a8513 mv a0,s5 -8000be2c: 08f12e23 sw a5,156(sp) -8000be30: 0ba12023 sw s10,160(sp) -8000be34: 0bb12223 sw s11,164(sp) -8000be38: 0a912423 sw s1,168(sp) -8000be3c: 0b412623 sw s4,172(sp) -8000be40: 08012823 sw zero,144(sp) -8000be44: 08012a23 sw zero,148(sp) -8000be48: 08012c23 sw zero,152(sp) -8000be4c: 6b5050ef jal ra,80011d00 <__multf3> -8000be50: 000a8513 mv a0,s5 -8000be54: 3d0080ef jal ra,80014224 <__fixtfsi> -8000be58: 00050593 mv a1,a0 -8000be5c: 00050413 mv s0,a0 -8000be60: 000a8513 mv a0,s5 -8000be64: 0b012983 lw s3,176(sp) -8000be68: 0b412483 lw s1,180(sp) -8000be6c: 0b812b03 lw s6,184(sp) -8000be70: 0bc12a03 lw s4,188(sp) -8000be74: 4c4080ef jal ra,80014338 <__floatsitf> -8000be78: 0b012703 lw a4,176(sp) -8000be7c: 04012603 lw a2,64(sp) -8000be80: 00090593 mv a1,s2 -8000be84: 08e12023 sw a4,128(sp) -8000be88: 0b412703 lw a4,180(sp) -8000be8c: 000c8513 mv a0,s9 -8000be90: 09312823 sw s3,144(sp) -8000be94: 08e12223 sw a4,132(sp) -8000be98: 0b812703 lw a4,184(sp) -8000be9c: 08912a23 sw s1,148(sp) -8000bea0: 09612c23 sw s6,152(sp) -8000bea4: 08e12423 sw a4,136(sp) -8000bea8: 0bc12703 lw a4,188(sp) -8000beac: 09412e23 sw s4,156(sp) -8000beb0: 08e12623 sw a4,140(sp) -8000beb4: 651060ef jal ra,80012d04 <__subtf3> -8000beb8: 02412783 lw a5,36(sp) -8000bebc: 0a012b03 lw s6,160(sp) -8000bec0: 0a412983 lw s3,164(sp) -8000bec4: 00878733 add a4,a5,s0 -8000bec8: 00074703 lbu a4,0(a4) -8000becc: 0a812f83 lw t6,168(sp) -8000bed0: 0ac12603 lw a2,172(sp) -8000bed4: 05712823 sw s7,80(sp) -8000bed8: 00eb8023 sb a4,0(s7) -8000bedc: 05812223 sw s8,68(sp) -8000bee0: fff00793 li a5,-1 -8000bee4: 001b8b93 addi s7,s7,1 -8000bee8: 000b0d13 mv s10,s6 -8000beec: 00098d93 mv s11,s3 -8000bef0: 000f8493 mv s1,t6 -8000bef4: 00060a13 mv s4,a2 -8000bef8: eefc10e3 bne s8,a5,8000bdd8 <_svfprintf_r+0x2344> -8000befc: 07012883 lw a7,112(sp) -8000bf00: 000b0393 mv t2,s6 -8000bf04: 00098293 mv t0,s3 -8000bf08: 3ffe0937 lui s2,0x3ffe0 -8000bf0c: 000c8593 mv a1,s9 -8000bf10: 000a8513 mv a0,s5 -8000bf14: 03112023 sw a7,32(sp) -8000bf18: 00812e23 sw s0,28(sp) -8000bf1c: 05c12a03 lw s4,92(sp) -8000bf20: 06412483 lw s1,100(sp) -8000bf24: 06012403 lw s0,96(sp) -8000bf28: 0a712823 sw t2,176(sp) -8000bf2c: 06712223 sw t2,100(sp) -8000bf30: 0a512a23 sw t0,180(sp) -8000bf34: 06512023 sw t0,96(sp) -8000bf38: 0bf12c23 sw t6,184(sp) -8000bf3c: 05f12e23 sw t6,92(sp) -8000bf40: 0ac12e23 sw a2,188(sp) -8000bf44: 04c12023 sw a2,64(sp) -8000bf48: 0a012023 sw zero,160(sp) -8000bf4c: 0a012223 sw zero,164(sp) -8000bf50: 0a012423 sw zero,168(sp) -8000bf54: 0b212623 sw s2,172(sp) -8000bf58: 321050ef jal ra,80011a78 <__getf2> -8000bf5c: 06c12d83 lw s11,108(sp) -8000bf60: 07412d03 lw s10,116(sp) -8000bf64: 07812c03 lw s8,120(sp) -8000bf68: 07c12b03 lw s6,124(sp) -8000bf6c: 06812983 lw s3,104(sp) -8000bf70: 02012883 lw a7,32(sp) -8000bf74: 0aa04063 bgtz a0,8000c014 <_svfprintf_r+0x2580> -8000bf78: 06412383 lw t2,100(sp) -8000bf7c: 06012283 lw t0,96(sp) -8000bf80: 05c12f83 lw t6,92(sp) -8000bf84: 04012603 lw a2,64(sp) -8000bf88: 000c8593 mv a1,s9 -8000bf8c: 000a8513 mv a0,s5 -8000bf90: 0a712823 sw t2,176(sp) -8000bf94: 0a512a23 sw t0,180(sp) -8000bf98: 0bf12c23 sw t6,184(sp) -8000bf9c: 0ac12e23 sw a2,188(sp) -8000bfa0: 0a012023 sw zero,160(sp) -8000bfa4: 0a012223 sw zero,164(sp) -8000bfa8: 0a012423 sw zero,168(sp) -8000bfac: 0b212623 sw s2,172(sp) -8000bfb0: 1fd050ef jal ra,800119ac <__eqtf2> -8000bfb4: 02012883 lw a7,32(sp) -8000bfb8: 00051863 bnez a0,8000bfc8 <_svfprintf_r+0x2534> -8000bfbc: 01c12783 lw a5,28(sp) -8000bfc0: 0017fc93 andi s9,a5,1 -8000bfc4: 040c9863 bnez s9,8000c014 <_svfprintf_r+0x2580> -8000bfc8: 04412783 lw a5,68(sp) -8000bfcc: 03000613 li a2,48 -8000bfd0: 00178693 addi a3,a5,1 # 40030001 <_start-0x3ffcffff> -8000bfd4: 00db86b3 add a3,s7,a3 -8000bfd8: 0007c863 bltz a5,8000bfe8 <_svfprintf_r+0x2554> -8000bfdc: 001b8b93 addi s7,s7,1 -8000bfe0: fecb8fa3 sb a2,-1(s7) -8000bfe4: fedb9ce3 bne s7,a3,8000bfdc <_svfprintf_r+0x2548> -8000bfe8: 416b87b3 sub a5,s7,s6 -8000bfec: 02f12023 sw a5,32(sp) -8000bff0: 850fe06f j 8000a040 <_svfprintf_r+0x5ac> -8000bff4: 03412423 sw s4,40(sp) -8000bff8: 00012823 sw zero,16(sp) -8000bffc: 00090a13 mv s4,s2 -8000c000: 800007b7 lui a5,0x80000 -8000c004: 0067c333 xor t1,a5,t1 -8000c008: 02d00793 li a5,45 -8000c00c: 04f12c23 sw a5,88(sp) -8000c010: c71ff06f j 8000bc80 <_svfprintf_r+0x21ec> -8000c014: 05012783 lw a5,80(sp) -8000c018: 000b8693 mv a3,s7 -8000c01c: 0cf12e23 sw a5,220(sp) -8000c020: 02412783 lw a5,36(sp) -8000c024: fffbc603 lbu a2,-1(s7) -8000c028: 00f7c583 lbu a1,15(a5) # 8000000f <__BSS_END__+0xfffe93d3> -8000c02c: 02b61063 bne a2,a1,8000c04c <_svfprintf_r+0x25b8> -8000c030: 03000513 li a0,48 -8000c034: fea68fa3 sb a0,-1(a3) -8000c038: 0dc12683 lw a3,220(sp) -8000c03c: fff68793 addi a5,a3,-1 -8000c040: 0cf12e23 sw a5,220(sp) -8000c044: fff6c603 lbu a2,-1(a3) -8000c048: fec586e3 beq a1,a2,8000c034 <_svfprintf_r+0x25a0> -8000c04c: 00160593 addi a1,a2,1 -8000c050: 03900513 li a0,57 -8000c054: 0ff5f593 andi a1,a1,255 -8000c058: 00a60663 beq a2,a0,8000c064 <_svfprintf_r+0x25d0> -8000c05c: feb68fa3 sb a1,-1(a3) -8000c060: f89ff06f j 8000bfe8 <_svfprintf_r+0x2554> -8000c064: 02412783 lw a5,36(sp) -8000c068: 00a7c583 lbu a1,10(a5) -8000c06c: feb68fa3 sb a1,-1(a3) -8000c070: f79ff06f j 8000bfe8 <_svfprintf_r+0x2554> -8000c074: 001d8593 addi a1,s11,1 -8000c078: 000d0513 mv a0,s10 -8000c07c: 01112823 sw a7,16(sp) -8000c080: b29fb0ef jal ra,80007ba8 <_malloc_r> -8000c084: 01012883 lw a7,16(sp) -8000c088: 00050b13 mv s6,a0 -8000c08c: 3e050863 beqz a0,8000c47c <_svfprintf_r+0x29e8> -8000c090: 00a12823 sw a0,16(sp) -8000c094: bc9ff06f j 8000bc5c <_svfprintf_r+0x21c8> -8000c098: 03000793 li a5,48 -8000c09c: 0cf10423 sb a5,200(sp) -8000c0a0: 07800793 li a5,120 -8000c0a4: b9dff06f j 8000bc40 <_svfprintf_r+0x21ac> -8000c0a8: 04700793 li a5,71 -8000c0ac: 01bb0933 add s2,s6,s11 -8000c0b0: 04f12a23 sw a5,84(sp) -8000c0b4: 0a010c93 addi s9,sp,160 -8000c0b8: f25fd06f j 80009fdc <_svfprintf_r+0x548> -8000c0bc: 00812703 lw a4,8(sp) -8000c0c0: 009787b3 add a5,a5,s1 -8000c0c4: 00168693 addi a3,a3,1 -8000c0c8: 00e8a023 sw a4,0(a7) -8000c0cc: 0098a223 sw s1,4(a7) -8000c0d0: 0ef12623 sw a5,236(sp) -8000c0d4: 0ed12423 sw a3,232(sp) -8000c0d8: 00700613 li a2,7 -8000c0dc: b6d65863 bge a2,a3,8000b44c <_svfprintf_r+0x19b8> -8000c0e0: 0e410613 addi a2,sp,228 -8000c0e4: 000c0593 mv a1,s8 -8000c0e8: 000d0513 mv a0,s10 -8000c0ec: 691020ef jal ra,8000ef7c <__ssprint_r> -8000c0f0: 00050463 beqz a0,8000c0f8 <_svfprintf_r+0x2664> -8000c0f4: 9c1fe06f j 8000aab4 <_svfprintf_r+0x1020> -8000c0f8: 0ec12783 lw a5,236(sp) -8000c0fc: 0e812683 lw a3,232(sp) -8000c100: 10c10893 addi a7,sp,268 -8000c104: b4cff06f j 8000b450 <_svfprintf_r+0x19bc> -8000c108: 000a0b93 mv s7,s4 -8000c10c: dfcfe06f j 8000a708 <_svfprintf_r+0xc74> -8000c110: 000d9463 bnez s11,8000c118 <_svfprintf_r+0x2684> -8000c114: 00100d93 li s11,1 -8000c118: 0fc12303 lw t1,252(sp) -8000c11c: 0f012e03 lw t3,240(sp) -8000c120: 0f412e83 lw t4,244(sp) -8000c124: 0f812f03 lw t5,248(sp) -8000c128: 100a6913 ori s2,s4,256 -8000c12c: ec0344e3 bltz t1,8000bff4 <_svfprintf_r+0x2560> -8000c130: 0b010a93 addi s5,sp,176 -8000c134: 0dc10813 addi a6,sp,220 -8000c138: 0d010793 addi a5,sp,208 -8000c13c: 0cc10713 addi a4,sp,204 -8000c140: 000d8693 mv a3,s11 -8000c144: 00200613 li a2,2 -8000c148: 000a8593 mv a1,s5 -8000c14c: 000d0513 mv a0,s10 -8000c150: 05112223 sw a7,68(sp) -8000c154: 0bc12823 sw t3,176(sp) -8000c158: 05c12023 sw t3,64(sp) -8000c15c: 0bd12a23 sw t4,180(sp) -8000c160: 03d12223 sw t4,36(sp) -8000c164: 0be12c23 sw t5,184(sp) -8000c168: 03e12023 sw t5,32(sp) -8000c16c: 0a612e23 sw t1,188(sp) -8000c170: 00612e23 sw t1,28(sp) -8000c174: d30fa0ef jal ra,800066a4 <_ldtoa_r> -8000c178: 01c12303 lw t1,28(sp) -8000c17c: 03412423 sw s4,40(sp) -8000c180: 02012f03 lw t5,32(sp) -8000c184: 02412e83 lw t4,36(sp) -8000c188: 04012e03 lw t3,64(sp) -8000c18c: 04412883 lw a7,68(sp) -8000c190: 00050b13 mv s6,a0 -8000c194: 00090a13 mv s4,s2 -8000c198: 00012823 sw zero,16(sp) -8000c19c: 04012c23 sw zero,88(sp) -8000c1a0: 971ff06f j 8000bb10 <_svfprintf_r+0x207c> -8000c1a4: fff00793 li a5,-1 -8000c1a8: 00f12623 sw a5,12(sp) -8000c1ac: c05fd06f j 80009db0 <_svfprintf_r+0x31c> -8000c1b0: 0d610693 addi a3,sp,214 -8000c1b4: 00061863 bnez a2,8000c1c4 <_svfprintf_r+0x2730> -8000c1b8: 03000693 li a3,48 -8000c1bc: 0cd10b23 sb a3,214(sp) -8000c1c0: 0d710693 addi a3,sp,215 -8000c1c4: 1b010713 addi a4,sp,432 -8000c1c8: 03078793 addi a5,a5,48 -8000c1cc: 40e68633 sub a2,a3,a4 -8000c1d0: 00f68023 sb a5,0(a3) -8000c1d4: 0dd60793 addi a5,a2,221 -8000c1d8: 02f12c23 sw a5,56(sp) -8000c1dc: f65fd06f j 8000a140 <_svfprintf_r+0x6ac> -8000c1e0: 0b010a93 addi s5,sp,176 -8000c1e4: 000a8513 mv a0,s5 -8000c1e8: 05112823 sw a7,80(sp) -8000c1ec: 0bc12823 sw t3,176(sp) -8000c1f0: 0bd12a23 sw t4,180(sp) -8000c1f4: 0be12c23 sw t5,184(sp) -8000c1f8: 0a612e23 sw t1,188(sp) -8000c1fc: 480080ef jal ra,8001467c <__trunctfdf2> -8000c200: 0cc10613 addi a2,sp,204 -8000c204: b68fd0ef jal ra,8000956c -8000c208: 00058613 mv a2,a1 -8000c20c: 00050593 mv a1,a0 -8000c210: 000a8513 mv a0,s5 -8000c214: 274080ef jal ra,80014488 <__extenddftf2> -8000c218: 0b012783 lw a5,176(sp) -8000c21c: 0a010c93 addi s9,sp,160 -8000c220: 09010913 addi s2,sp,144 -8000c224: 08f12823 sw a5,144(sp) -8000c228: 0b412783 lw a5,180(sp) -8000c22c: 08010613 addi a2,sp,128 -8000c230: 00090593 mv a1,s2 -8000c234: 08f12a23 sw a5,148(sp) -8000c238: 0b812783 lw a5,184(sp) -8000c23c: 000c8513 mv a0,s9 -8000c240: 04c12023 sw a2,64(sp) -8000c244: 08f12c23 sw a5,152(sp) -8000c248: 0bc12783 lw a5,188(sp) -8000c24c: 08012023 sw zero,128(sp) -8000c250: 08012223 sw zero,132(sp) -8000c254: 08f12e23 sw a5,156(sp) -8000c258: 3ffc07b7 lui a5,0x3ffc0 -8000c25c: 08f12623 sw a5,140(sp) -8000c260: 08012423 sw zero,136(sp) -8000c264: 29d050ef jal ra,80011d00 <__multf3> -8000c268: 0a012803 lw a6,160(sp) -8000c26c: 0a412e03 lw t3,164(sp) -8000c270: 0a812e83 lw t4,168(sp) -8000c274: 0ac12f03 lw t5,172(sp) -8000c278: 000c8593 mv a1,s9 -8000c27c: 000a8513 mv a0,s5 -8000c280: 0b012823 sw a6,176(sp) -8000c284: 05012223 sw a6,68(sp) -8000c288: 0bc12a23 sw t3,180(sp) -8000c28c: 03c12223 sw t3,36(sp) -8000c290: 0bd12c23 sw t4,184(sp) -8000c294: 03d12023 sw t4,32(sp) -8000c298: 0be12e23 sw t5,188(sp) -8000c29c: 01e12e23 sw t5,28(sp) -8000c2a0: 0a012023 sw zero,160(sp) -8000c2a4: 0a012223 sw zero,164(sp) -8000c2a8: 0a012423 sw zero,168(sp) -8000c2ac: 0a012623 sw zero,172(sp) -8000c2b0: 6fc050ef jal ra,800119ac <__eqtf2> -8000c2b4: 01c12f03 lw t5,28(sp) -8000c2b8: 02012e83 lw t4,32(sp) -8000c2bc: 02412e03 lw t3,36(sp) -8000c2c0: 04412803 lw a6,68(sp) -8000c2c4: 05012883 lw a7,80(sp) -8000c2c8: 00051663 bnez a0,8000c2d4 <_svfprintf_r+0x2840> -8000c2cc: 00100793 li a5,1 -8000c2d0: 0cf12623 sw a5,204(sp) -8000c2d4: 800157b7 lui a5,0x80015 -8000c2d8: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -8000c2dc: 02f12223 sw a5,36(sp) -8000c2e0: ab5ff06f j 8000bd94 <_svfprintf_r+0x2300> -8000c2e4: 00012823 sw zero,16(sp) -8000c2e8: 00078a13 mv s4,a5 -8000c2ec: d15ff06f j 8000c000 <_svfprintf_r+0x256c> -8000c2f0: 06700493 li s1,103 -8000c2f4: 03c12603 lw a2,60(sp) -8000c2f8: 0ff00693 li a3,255 -8000c2fc: 00064783 lbu a5,0(a2) -8000c300: 18d78863 beq a5,a3,8000c490 <_svfprintf_r+0x29fc> -8000c304: 01c12703 lw a4,28(sp) -8000c308: 00000513 li a0,0 -8000c30c: 00000593 li a1,0 -8000c310: 00e7de63 bge a5,a4,8000c32c <_svfprintf_r+0x2898> -8000c314: 40f70733 sub a4,a4,a5 -8000c318: 00164783 lbu a5,1(a2) -8000c31c: 04078463 beqz a5,8000c364 <_svfprintf_r+0x28d0> -8000c320: 00158593 addi a1,a1,1 -8000c324: 00160613 addi a2,a2,1 -8000c328: fed794e3 bne a5,a3,8000c310 <_svfprintf_r+0x287c> -8000c32c: 02c12e23 sw a2,60(sp) -8000c330: 00e12e23 sw a4,28(sp) -8000c334: 02b12223 sw a1,36(sp) -8000c338: 02a12423 sw a0,40(sp) -8000c33c: 02812703 lw a4,40(sp) -8000c340: 02412783 lw a5,36(sp) -8000c344: 00e787b3 add a5,a5,a4 -8000c348: 04812703 lw a4,72(sp) -8000c34c: 02e787b3 mul a5,a5,a4 -8000c350: 01978cb3 add s9,a5,s9 -8000c354: fffcca93 not s5,s9 -8000c358: 41fada93 srai s5,s5,0x1f -8000c35c: 015cfab3 and s5,s9,s5 -8000c360: e25fd06f j 8000a184 <_svfprintf_r+0x6f0> -8000c364: 00064783 lbu a5,0(a2) -8000c368: 00150513 addi a0,a0,1 -8000c36c: fbdff06f j 8000c328 <_svfprintf_r+0x2894> -8000c370: 02c12783 lw a5,44(sp) -8000c374: 06600493 li s1,102 -8000c378: 00f70cb3 add s9,a4,a5 -8000c37c: 01bc8cb3 add s9,s9,s11 -8000c380: 851ff06f j 8000bbd0 <_svfprintf_r+0x213c> -8000c384: 02812783 lw a5,40(sp) -8000c388: 0017f793 andi a5,a5,1 -8000c38c: 00079463 bnez a5,8000c394 <_svfprintf_r+0x2900> -8000c390: dd1fd06f j 8000a160 <_svfprintf_r+0x6cc> -8000c394: dc5fd06f j 8000a158 <_svfprintf_r+0x6c4> -8000c398: 0a010c93 addi s9,sp,160 -8000c39c: 000c8593 mv a1,s9 -8000c3a0: 000a8513 mv a0,s5 -8000c3a4: 05112223 sw a7,68(sp) -8000c3a8: 0bc12823 sw t3,176(sp) -8000c3ac: 05c12023 sw t3,64(sp) -8000c3b0: 0bd12a23 sw t4,180(sp) -8000c3b4: 03d12223 sw t4,36(sp) -8000c3b8: 0be12c23 sw t5,184(sp) -8000c3bc: 03e12023 sw t5,32(sp) -8000c3c0: 0a612e23 sw t1,188(sp) -8000c3c4: 00612e23 sw t1,28(sp) -8000c3c8: 0a012023 sw zero,160(sp) -8000c3cc: 0a012223 sw zero,164(sp) -8000c3d0: 0a012423 sw zero,168(sp) -8000c3d4: 0a012623 sw zero,172(sp) -8000c3d8: 5d4050ef jal ra,800119ac <__eqtf2> -8000c3dc: 01c12303 lw t1,28(sp) -8000c3e0: 02012f03 lw t5,32(sp) -8000c3e4: 02412e83 lw t4,36(sp) -8000c3e8: 04012e03 lw t3,64(sp) -8000c3ec: 04412883 lw a7,68(sp) -8000c3f0: ea050263 beqz a0,8000ba94 <_svfprintf_r+0x2000> -8000c3f4: 00100793 li a5,1 -8000c3f8: 41b787b3 sub a5,a5,s11 -8000c3fc: 0cf12623 sw a5,204(sp) -8000c400: 00f90933 add s2,s2,a5 -8000c404: bd9fd06f j 80009fdc <_svfprintf_r+0x548> -8000c408: 00079a63 bnez a5,8000c41c <_svfprintf_r+0x2988> -8000c40c: 00100a93 li s5,1 -8000c410: 06600493 li s1,102 -8000c414: 00100c93 li s9,1 -8000c418: db8ff06f j 8000b9d0 <_svfprintf_r+0x1f3c> -8000c41c: 02c12783 lw a5,44(sp) -8000c420: 06600493 li s1,102 -8000c424: 00178c93 addi s9,a5,1 -8000c428: 01bc8cb3 add s9,s9,s11 -8000c42c: fffcca93 not s5,s9 -8000c430: 41fada93 srai s5,s5,0x1f -8000c434: 015cfab3 and s5,s9,s5 -8000c438: d98ff06f j 8000b9d0 <_svfprintf_r+0x1f3c> -8000c43c: 00088713 mv a4,a7 -8000c440: a7cff06f j 8000b6bc <_svfprintf_r+0x1c28> -8000c444: 01412783 lw a5,20(sp) -8000c448: 0007ad83 lw s11,0(a5) -8000c44c: 00478793 addi a5,a5,4 -8000c450: 000dd463 bgez s11,8000c458 <_svfprintf_r+0x29c4> -8000c454: fff00d93 li s11,-1 -8000c458: 00144483 lbu s1,1(s0) -8000c45c: 00f12a23 sw a5,20(sp) -8000c460: 00070413 mv s0,a4 -8000c464: f94fd06f j 80009bf8 <_svfprintf_r+0x164> -8000c468: 00c00793 li a5,12 -8000c46c: 00fd2023 sw a5,0(s10) -8000c470: fff00793 li a5,-1 -8000c474: 00f12623 sw a5,12(sp) -8000c478: 939fd06f j 80009db0 <_svfprintf_r+0x31c> -8000c47c: 00cc5703 lhu a4,12(s8) -8000c480: 04076793 ori a5,a4,64 -8000c484: 00078713 mv a4,a5 -8000c488: 00fc1623 sh a5,12(s8) -8000c48c: 919fd06f j 80009da4 <_svfprintf_r+0x310> -8000c490: 02012423 sw zero,40(sp) -8000c494: 02012223 sw zero,36(sp) -8000c498: ea5ff06f j 8000c33c <_svfprintf_r+0x28a8> -8000c49c: 00200793 li a5,2 -8000c4a0: 02f12c23 sw a5,56(sp) -8000c4a4: c9dfd06f j 8000a140 <_svfprintf_r+0x6ac> +8000b210: 0ec12c83 lw s9,236(sp) +8000b214: 11410893 addi a7,sp,276 +8000b218: 00168693 addi a3,a3,1 +8000b21c: 10c10913 addi s2,sp,268 +8000b220: fd5fe06f j 8000a1f4 <_svfprintf_r+0x824> +8000b224: 0e410613 addi a2,sp,228 +8000b228: 000b0593 mv a1,s6 +8000b22c: 000d0513 mv a0,s10 +8000b230: 489030ef jal ra,8000eeb8 <__ssprint_r> +8000b234: 50051a63 bnez a0,8000b748 <_svfprintf_r+0x1d78> +8000b238: 0ec12783 lw a5,236(sp) +8000b23c: 10c10893 addi a7,sp,268 +8000b240: ea1ff06f j 8000b0e0 <_svfprintf_r+0x1710> +8000b244: 1b010b13 addi s6,sp,432 +8000b248: 00000793 li a5,0 +8000b24c: 00812823 sw s0,16(sp) +8000b250: 00912e23 sw s1,28(sp) +8000b254: 000b0413 mv s0,s6 +8000b258: 03312223 sw s3,36(sp) +8000b25c: 000c0b13 mv s6,s8 +8000b260: 00090493 mv s1,s2 +8000b264: 000c8993 mv s3,s9 +8000b268: 400bfa13 andi s4,s7,1024 +8000b26c: 03c12c83 lw s9,60(sp) +8000b270: 0ff00a93 li s5,255 +8000b274: 00088c13 mv s8,a7 +8000b278: 00078913 mv s2,a5 +8000b27c: 0240006f j 8000b2a0 <_svfprintf_r+0x18d0> +8000b280: 00a00613 li a2,10 +8000b284: 00000693 li a3,0 +8000b288: 00048513 mv a0,s1 +8000b28c: 00098593 mv a1,s3 +8000b290: 170050ef jal ra,80010400 <__udivdi3> +8000b294: 4c098063 beqz s3,8000b754 <_svfprintf_r+0x1d84> +8000b298: 00050493 mv s1,a0 +8000b29c: 00058993 mv s3,a1 +8000b2a0: 00a00613 li a2,10 +8000b2a4: 00000693 li a3,0 +8000b2a8: 00048513 mv a0,s1 +8000b2ac: 00098593 mv a1,s3 +8000b2b0: 584050ef jal ra,80010834 <__umoddi3> +8000b2b4: 03050513 addi a0,a0,48 +8000b2b8: fea40fa3 sb a0,-1(s0) +8000b2bc: 00190913 addi s2,s2,1 +8000b2c0: fff40413 addi s0,s0,-1 +8000b2c4: fa0a0ee3 beqz s4,8000b280 <_svfprintf_r+0x18b0> +8000b2c8: 000cc683 lbu a3,0(s9) +8000b2cc: fad91ae3 bne s2,a3,8000b280 <_svfprintf_r+0x18b0> +8000b2d0: fb5908e3 beq s2,s5,8000b280 <_svfprintf_r+0x18b0> +8000b2d4: 42099a63 bnez s3,8000b708 <_svfprintf_r+0x1d38> +8000b2d8: 00900793 li a5,9 +8000b2dc: 4297e663 bltu a5,s1,8000b708 <_svfprintf_r+0x1d38> +8000b2e0: 000c0893 mv a7,s8 +8000b2e4: 1b010793 addi a5,sp,432 +8000b2e8: 000b0c13 mv s8,s6 +8000b2ec: 00040b13 mv s6,s0 +8000b2f0: 03912e23 sw s9,60(sp) +8000b2f4: 01c12483 lw s1,28(sp) +8000b2f8: 02412983 lw s3,36(sp) +8000b2fc: 01012403 lw s0,16(sp) +8000b300: 03212023 sw s2,32(sp) +8000b304: 41678cb3 sub s9,a5,s6 +8000b308: 000b8a13 mv s4,s7 +8000b30c: 96cff06f j 8000a478 <_svfprintf_r+0xaa8> +8000b310: 0e812683 lw a3,232(sp) +8000b314: 80015637 lui a2,0x80015 +8000b318: bd460613 addi a2,a2,-1068 # 80014bd4 <__BSS_END__+0xffffdf98> +8000b31c: 00c8a023 sw a2,0(a7) +8000b320: 00178793 addi a5,a5,1 +8000b324: 00100613 li a2,1 +8000b328: 00168693 addi a3,a3,1 +8000b32c: 00c8a223 sw a2,4(a7) +8000b330: 0ef12623 sw a5,236(sp) +8000b334: 0ed12423 sw a3,232(sp) +8000b338: 00700613 li a2,7 +8000b33c: 00888893 addi a7,a7,8 +8000b340: 06d64c63 blt a2,a3,8000b3b8 <_svfprintf_r+0x19e8> +8000b344: 20059863 bnez a1,8000b554 <_svfprintf_r+0x1b84> +8000b348: 02012703 lw a4,32(sp) +8000b34c: 001a7693 andi a3,s4,1 +8000b350: 00e6e6b3 or a3,a3,a4 +8000b354: 00069463 bnez a3,8000b35c <_svfprintf_r+0x198c> +8000b358: 929fe06f j 80009c80 <_svfprintf_r+0x2b0> +8000b35c: 03012683 lw a3,48(sp) +8000b360: 02c12703 lw a4,44(sp) +8000b364: 00700613 li a2,7 +8000b368: 00d8a023 sw a3,0(a7) +8000b36c: 0e812683 lw a3,232(sp) +8000b370: 00e787b3 add a5,a5,a4 +8000b374: 00e8a223 sw a4,4(a7) +8000b378: 00168693 addi a3,a3,1 +8000b37c: 0ef12623 sw a5,236(sp) +8000b380: 0ed12423 sw a3,232(sp) +8000b384: 4ad64e63 blt a2,a3,8000b840 <_svfprintf_r+0x1e70> +8000b388: 00888893 addi a7,a7,8 +8000b38c: 02012703 lw a4,32(sp) +8000b390: 00168693 addi a3,a3,1 +8000b394: 0168a023 sw s6,0(a7) +8000b398: 00e787b3 add a5,a5,a4 +8000b39c: 00e8a223 sw a4,4(a7) +8000b3a0: 0ef12623 sw a5,236(sp) +8000b3a4: 0ed12423 sw a3,232(sp) +8000b3a8: 00700713 li a4,7 +8000b3ac: 00d74463 blt a4,a3,8000b3b4 <_svfprintf_r+0x19e4> +8000b3b0: 8cdfe06f j 80009c7c <_svfprintf_r+0x2ac> +8000b3b4: e65fe06f j 8000a218 <_svfprintf_r+0x848> +8000b3b8: 0e410613 addi a2,sp,228 +8000b3bc: 000c0593 mv a1,s8 +8000b3c0: 000d0513 mv a0,s10 +8000b3c4: 2f5030ef jal ra,8000eeb8 <__ssprint_r> +8000b3c8: e2051463 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000b3cc: 0cc12583 lw a1,204(sp) +8000b3d0: 0ec12783 lw a5,236(sp) +8000b3d4: 10c10893 addi a7,sp,268 +8000b3d8: f6dff06f j 8000b344 <_svfprintf_r+0x1974> +8000b3dc: 01012b83 lw s7,16(sp) +8000b3e0: 00040d13 mv s10,s0 +8000b3e4: 00048c13 mv s8,s1 +8000b3e8: e0cff06f j 8000a9f4 <_svfprintf_r+0x1024> +8000b3ec: 040a7793 andi a5,s4,64 +8000b3f0: 22078c63 beqz a5,8000b628 <_svfprintf_r+0x1c58> +8000b3f4: 01412783 lw a5,20(sp) +8000b3f8: 00000c93 li s9,0 +8000b3fc: 00e12a23 sw a4,20(sp) +8000b400: 0007d903 lhu s2,0(a5) +8000b404: b35ff06f j 8000af38 <_svfprintf_r+0x1568> +8000b408: 0e410613 addi a2,sp,228 +8000b40c: 000c0593 mv a1,s8 +8000b410: 000d0513 mv a0,s10 +8000b414: 2a5030ef jal ra,8000eeb8 <__ssprint_r> +8000b418: dc051c63 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000b41c: 0ec12783 lw a5,236(sp) +8000b420: 10c10893 addi a7,sp,268 +8000b424: b90ff06f j 8000a7b4 <_svfprintf_r+0xde4> +8000b428: 00812683 lw a3,8(sp) +8000b42c: 009787b3 add a5,a5,s1 +8000b430: 0098a223 sw s1,4(a7) +8000b434: 00d8a023 sw a3,0(a7) +8000b438: 00170713 addi a4,a4,1 +8000b43c: 0ef12623 sw a5,236(sp) +8000b440: 0ee12423 sw a4,232(sp) +8000b444: 00700693 li a3,7 +8000b448: 00e6c463 blt a3,a4,8000b450 <_svfprintf_r+0x1a80> +8000b44c: 831fe06f j 80009c7c <_svfprintf_r+0x2ac> +8000b450: dc9fe06f j 8000a218 <_svfprintf_r+0x848> +8000b454: 0e410613 addi a2,sp,228 +8000b458: 000b0593 mv a1,s6 +8000b45c: 000d0513 mv a0,s10 +8000b460: 259030ef jal ra,8000eeb8 <__ssprint_r> +8000b464: 2e051263 bnez a0,8000b748 <_svfprintf_r+0x1d78> +8000b468: 00044683 lbu a3,0(s0) +8000b46c: 0ec12783 lw a5,236(sp) +8000b470: 10c10893 addi a7,sp,268 +8000b474: cadff06f j 8000b120 <_svfprintf_r+0x1750> +8000b478: 0f012783 lw a5,240(sp) +8000b47c: 0a010593 addi a1,sp,160 +8000b480: 0b010513 addi a0,sp,176 +8000b484: 0af12823 sw a5,176(sp) +8000b488: 0f412783 lw a5,244(sp) +8000b48c: 0a012023 sw zero,160(sp) +8000b490: 0a012223 sw zero,164(sp) +8000b494: 0af12a23 sw a5,180(sp) +8000b498: 0f812783 lw a5,248(sp) +8000b49c: 0a012423 sw zero,168(sp) +8000b4a0: 0a012623 sw zero,172(sp) +8000b4a4: 0af12c23 sw a5,184(sp) +8000b4a8: 0fc12783 lw a5,252(sp) +8000b4ac: 0af12e23 sw a5,188(sp) +8000b4b0: 648060ef jal ra,80011af8 <__letf2> +8000b4b4: 01012883 lw a7,16(sp) +8000b4b8: 52054263 bltz a0,8000b9dc <_svfprintf_r+0x200c> +8000b4bc: 0c714783 lbu a5,199(sp) +8000b4c0: 04700713 li a4,71 +8000b4c4: 28975e63 bge a4,s1,8000b760 <_svfprintf_r+0x1d90> +8000b4c8: 80015737 lui a4,0x80015 +8000b4cc: b9870b13 addi s6,a4,-1128 # 80014b98 <__BSS_END__+0xffffdf5c> +8000b4d0: 00012823 sw zero,16(sp) +8000b4d4: 02012423 sw zero,40(sp) +8000b4d8: 02012223 sw zero,36(sp) +8000b4dc: 00012e23 sw zero,28(sp) +8000b4e0: f7fa7a13 andi s4,s4,-129 +8000b4e4: 00300a93 li s5,3 +8000b4e8: 00300c93 li s9,3 +8000b4ec: 00000d93 li s11,0 +8000b4f0: 00078463 beqz a5,8000b4f8 <_svfprintf_r+0x1b28> +8000b4f4: e79fe06f j 8000a36c <_svfprintf_r+0x99c> +8000b4f8: ebcfe06f j 80009bb4 <_svfprintf_r+0x1e4> +8000b4fc: 00c12783 lw a5,12(sp) +8000b500: 00040b13 mv s6,s0 +8000b504: 00f72023 sw a5,0(a4) +8000b508: fc0fe06f j 80009cc8 <_svfprintf_r+0x2f8> +8000b50c: 000b0513 mv a0,s6 +8000b510: 05912023 sw s9,64(sp) +8000b514: b88fe0ef jal ra,8000989c +8000b518: 0c714783 lbu a5,199(sp) +8000b51c: fff54a93 not s5,a0 +8000b520: 41fada93 srai s5,s5,0x1f +8000b524: 01212a23 sw s2,20(sp) +8000b528: 00012823 sw zero,16(sp) +8000b52c: 02012423 sw zero,40(sp) +8000b530: 02012223 sw zero,36(sp) +8000b534: 00012e23 sw zero,28(sp) +8000b538: 04012883 lw a7,64(sp) +8000b53c: 00050c93 mv s9,a0 +8000b540: 01557ab3 and s5,a0,s5 +8000b544: 00000d93 li s11,0 +8000b548: 00078463 beqz a5,8000b550 <_svfprintf_r+0x1b80> +8000b54c: e21fe06f j 8000a36c <_svfprintf_r+0x99c> +8000b550: e64fe06f j 80009bb4 <_svfprintf_r+0x1e4> +8000b554: 03012683 lw a3,48(sp) +8000b558: 02c12703 lw a4,44(sp) +8000b55c: 00700613 li a2,7 +8000b560: 00d8a023 sw a3,0(a7) +8000b564: 0e812683 lw a3,232(sp) +8000b568: 00e787b3 add a5,a5,a4 +8000b56c: 00e8a223 sw a4,4(a7) +8000b570: 00168693 addi a3,a3,1 +8000b574: 0ef12623 sw a5,236(sp) +8000b578: 0ed12423 sw a3,232(sp) +8000b57c: 00888893 addi a7,a7,8 +8000b580: 2cd64063 blt a2,a3,8000b840 <_svfprintf_r+0x1e70> +8000b584: e005d4e3 bgez a1,8000b38c <_svfprintf_r+0x19bc> +8000b588: ff000613 li a2,-16 +8000b58c: 40b004b3 neg s1,a1 +8000b590: 26c5d4e3 bge a1,a2,8000bff8 <_svfprintf_r+0x2628> +8000b594: 01000913 li s2,16 +8000b598: 00700c93 li s9,7 +8000b59c: 00c0006f j 8000b5a8 <_svfprintf_r+0x1bd8> +8000b5a0: ff048493 addi s1,s1,-16 +8000b5a4: 24995ae3 bge s2,s1,8000bff8 <_svfprintf_r+0x2628> +8000b5a8: 00812703 lw a4,8(sp) +8000b5ac: 01078793 addi a5,a5,16 +8000b5b0: 00168693 addi a3,a3,1 +8000b5b4: 00e8a023 sw a4,0(a7) +8000b5b8: 0128a223 sw s2,4(a7) +8000b5bc: 0ef12623 sw a5,236(sp) +8000b5c0: 0ed12423 sw a3,232(sp) +8000b5c4: 00888893 addi a7,a7,8 +8000b5c8: fcdcdce3 bge s9,a3,8000b5a0 <_svfprintf_r+0x1bd0> +8000b5cc: 0e410613 addi a2,sp,228 +8000b5d0: 000c0593 mv a1,s8 +8000b5d4: 000d0513 mv a0,s10 +8000b5d8: 0e1030ef jal ra,8000eeb8 <__ssprint_r> +8000b5dc: c0051a63 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000b5e0: 0ec12783 lw a5,236(sp) +8000b5e4: 0e812683 lw a3,232(sp) +8000b5e8: 10c10893 addi a7,sp,268 +8000b5ec: fb5ff06f j 8000b5a0 <_svfprintf_r+0x1bd0> +8000b5f0: 00148693 addi a3,s1,1 +8000b5f4: 00890713 addi a4,s2,8 +8000b5f8: 00812783 lw a5,8(sp) +8000b5fc: 01bc8cb3 add s9,s9,s11 +8000b600: 01b92223 sw s11,4(s2) +8000b604: 00f92023 sw a5,0(s2) +8000b608: 0f912623 sw s9,236(sp) +8000b60c: 0ed12423 sw a3,232(sp) +8000b610: 00700793 li a5,7 +8000b614: bed7c2e3 blt a5,a3,8000b1f8 <_svfprintf_r+0x1828> +8000b618: 00168693 addi a3,a3,1 +8000b61c: 00870893 addi a7,a4,8 +8000b620: 00070913 mv s2,a4 +8000b624: bd1fe06f j 8000a1f4 <_svfprintf_r+0x824> +8000b628: 200a7793 andi a5,s4,512 +8000b62c: 1c078e63 beqz a5,8000b808 <_svfprintf_r+0x1e38> +8000b630: 01412783 lw a5,20(sp) +8000b634: 00000c93 li s9,0 +8000b638: 00e12a23 sw a4,20(sp) +8000b63c: 0007c903 lbu s2,0(a5) +8000b640: 8f9ff06f j 8000af38 <_svfprintf_r+0x1568> +8000b644: 200a7793 andi a5,s4,512 +8000b648: 1a078463 beqz a5,8000b7f0 <_svfprintf_r+0x1e20> +8000b64c: 01412783 lw a5,20(sp) +8000b650: 00e12a23 sw a4,20(sp) +8000b654: 00078903 lb s2,0(a5) +8000b658: 41f95c93 srai s9,s2,0x1f +8000b65c: 000c8793 mv a5,s9 +8000b660: fa5fe06f j 8000a604 <_svfprintf_r+0xc34> +8000b664: 200bf793 andi a5,s7,512 +8000b668: 16078863 beqz a5,8000b7d8 <_svfprintf_r+0x1e08> +8000b66c: 01412783 lw a5,20(sp) +8000b670: 00000c93 li s9,0 +8000b674: 00e12a23 sw a4,20(sp) +8000b678: 0007c903 lbu s2,0(a5) +8000b67c: 00100793 li a5,1 +8000b680: dcdfe06f j 8000a44c <_svfprintf_r+0xa7c> +8000b684: 200a7793 andi a5,s4,512 +8000b688: 12078e63 beqz a5,8000b7c4 <_svfprintf_r+0x1df4> +8000b68c: 01412783 lw a5,20(sp) +8000b690: 00000c93 li s9,0 +8000b694: 00e12a23 sw a4,20(sp) +8000b698: 0007c903 lbu s2,0(a5) +8000b69c: e31fe06f j 8000a4cc <_svfprintf_r+0xafc> +8000b6a0: 0fc12783 lw a5,252(sp) +8000b6a4: 1807c863 bltz a5,8000b834 <_svfprintf_r+0x1e64> +8000b6a8: 0c714783 lbu a5,199(sp) +8000b6ac: 04700713 li a4,71 +8000b6b0: 46975c63 bge a4,s1,8000bb28 <_svfprintf_r+0x2158> +8000b6b4: 80015737 lui a4,0x80015 +8000b6b8: ba070b13 addi s6,a4,-1120 # 80014ba0 <__BSS_END__+0xffffdf64> +8000b6bc: e15ff06f j 8000b4d0 <_svfprintf_r+0x1b00> +8000b6c0: 00812703 lw a4,8(sp) +8000b6c4: 009787b3 add a5,a5,s1 +8000b6c8: 00168693 addi a3,a3,1 +8000b6cc: 00e8a023 sw a4,0(a7) +8000b6d0: 0098a223 sw s1,4(a7) +8000b6d4: 0ef12623 sw a5,236(sp) +8000b6d8: 0ed12423 sw a3,232(sp) +8000b6dc: 00700613 li a2,7 +8000b6e0: 00888893 addi a7,a7,8 +8000b6e4: c8d65663 bge a2,a3,8000ab70 <_svfprintf_r+0x11a0> +8000b6e8: 0e410613 addi a2,sp,228 +8000b6ec: 000c0593 mv a1,s8 +8000b6f0: 000d0513 mv a0,s10 +8000b6f4: 7c4030ef jal ra,8000eeb8 <__ssprint_r> +8000b6f8: ae051c63 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000b6fc: 0ec12783 lw a5,236(sp) +8000b700: 10c10893 addi a7,sp,268 +8000b704: c6cff06f j 8000ab70 <_svfprintf_r+0x11a0> +8000b708: 04812783 lw a5,72(sp) +8000b70c: 04c12583 lw a1,76(sp) +8000b710: 00000913 li s2,0 +8000b714: 40f40433 sub s0,s0,a5 +8000b718: 00078613 mv a2,a5 +8000b71c: 00040513 mv a0,s0 +8000b720: a08fe0ef jal ra,80009928 +8000b724: 001cc583 lbu a1,1(s9) +8000b728: 00a00613 li a2,10 +8000b72c: 00000693 li a3,0 +8000b730: 00b03833 snez a6,a1 +8000b734: 00048513 mv a0,s1 +8000b738: 00098593 mv a1,s3 +8000b73c: 010c8cb3 add s9,s9,a6 +8000b740: 4c1040ef jal ra,80010400 <__udivdi3> +8000b744: b55ff06f j 8000b298 <_svfprintf_r+0x18c8> +8000b748: 01012b83 lw s7,16(sp) +8000b74c: 000b0c13 mv s8,s6 +8000b750: aa4ff06f j 8000a9f4 <_svfprintf_r+0x1024> +8000b754: 00900793 li a5,9 +8000b758: b497e0e3 bltu a5,s1,8000b298 <_svfprintf_r+0x18c8> +8000b75c: b85ff06f j 8000b2e0 <_svfprintf_r+0x1910> +8000b760: 80015737 lui a4,0x80015 +8000b764: b9470b13 addi s6,a4,-1132 # 80014b94 <__BSS_END__+0xffffdf58> +8000b768: d69ff06f j 8000b4d0 <_svfprintf_r+0x1b00> +8000b76c: 0e410613 addi a2,sp,228 +8000b770: 000c0593 mv a1,s8 +8000b774: 000d0513 mv a0,s10 +8000b778: 740030ef jal ra,8000eeb8 <__ssprint_r> +8000b77c: a6051a63 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000b780: 0ec12783 lw a5,236(sp) +8000b784: 10c10893 addi a7,sp,268 +8000b788: bd0ff06f j 8000ab58 <_svfprintf_r+0x1188> +8000b78c: 00600c93 li s9,6 +8000b790: 865ff06f j 8000aff4 <_svfprintf_r+0x1624> +8000b794: 02012683 lw a3,32(sp) +8000b798: 00db0733 add a4,s6,a3 +8000b79c: 409684b3 sub s1,a3,s1 +8000b7a0: 41b70833 sub a6,a4,s11 +8000b7a4: 00048913 mv s2,s1 +8000b7a8: c6985263 bge a6,s1,8000ac0c <_svfprintf_r+0x123c> +8000b7ac: 00080913 mv s2,a6 +8000b7b0: c5cff06f j 8000ac0c <_svfprintf_r+0x123c> +8000b7b4: 00c12783 lw a5,12(sp) +8000b7b8: 00040b13 mv s6,s0 +8000b7bc: 00f71023 sh a5,0(a4) +8000b7c0: d08fe06f j 80009cc8 <_svfprintf_r+0x2f8> +8000b7c4: 01412783 lw a5,20(sp) +8000b7c8: 00000c93 li s9,0 +8000b7cc: 00e12a23 sw a4,20(sp) +8000b7d0: 0007a903 lw s2,0(a5) +8000b7d4: cf9fe06f j 8000a4cc <_svfprintf_r+0xafc> +8000b7d8: 01412783 lw a5,20(sp) +8000b7dc: 00000c93 li s9,0 +8000b7e0: 00e12a23 sw a4,20(sp) +8000b7e4: 0007a903 lw s2,0(a5) +8000b7e8: 00100793 li a5,1 +8000b7ec: c61fe06f j 8000a44c <_svfprintf_r+0xa7c> +8000b7f0: 01412783 lw a5,20(sp) +8000b7f4: 00e12a23 sw a4,20(sp) +8000b7f8: 0007a903 lw s2,0(a5) +8000b7fc: 41f95c93 srai s9,s2,0x1f +8000b800: 000c8793 mv a5,s9 +8000b804: e01fe06f j 8000a604 <_svfprintf_r+0xc34> +8000b808: 01412783 lw a5,20(sp) +8000b80c: 00000c93 li s9,0 +8000b810: 00e12a23 sw a4,20(sp) +8000b814: 0007a903 lw s2,0(a5) +8000b818: f20ff06f j 8000af38 <_svfprintf_r+0x1568> +8000b81c: 0e410613 addi a2,sp,228 +8000b820: 000c0593 mv a1,s8 +8000b824: 000d0513 mv a0,s10 +8000b828: 690030ef jal ra,8000eeb8 <__ssprint_r> +8000b82c: 00cc5703 lhu a4,12(s8) +8000b830: cb0fe06f j 80009ce0 <_svfprintf_r+0x310> +8000b834: 02d00793 li a5,45 +8000b838: 0cf103a3 sb a5,199(sp) +8000b83c: e71ff06f j 8000b6ac <_svfprintf_r+0x1cdc> +8000b840: 0e410613 addi a2,sp,228 +8000b844: 000c0593 mv a1,s8 +8000b848: 000d0513 mv a0,s10 +8000b84c: 66c030ef jal ra,8000eeb8 <__ssprint_r> +8000b850: 9a051063 bnez a0,8000a9f0 <_svfprintf_r+0x1020> +8000b854: 0cc12583 lw a1,204(sp) +8000b858: 0ec12783 lw a5,236(sp) +8000b85c: 0e812683 lw a3,232(sp) +8000b860: 10c10893 addi a7,sp,268 +8000b864: b205d4e3 bgez a1,8000b38c <_svfprintf_r+0x19bc> +8000b868: d21ff06f j 8000b588 <_svfprintf_r+0x1bb8> +8000b86c: 00600d93 li s11,6 +8000b870: df8fe06f j 80009e68 <_svfprintf_r+0x498> +8000b874: 02012703 lw a4,32(sp) +8000b878: 000b0c13 mv s8,s6 +8000b87c: 02812b03 lw s6,40(sp) +8000b880: 02812e23 sw s0,60(sp) +8000b884: 01c12a03 lw s4,28(sp) +8000b888: 00eb06b3 add a3,s6,a4 +8000b88c: 04012403 lw s0,64(sp) +8000b890: 04412983 lw s3,68(sp) +8000b894: 02412a83 lw s5,36(sp) +8000b898: afb6f463 bgeu a3,s11,8000ab80 <_svfprintf_r+0x11b0> +8000b89c: 00068d93 mv s11,a3 +8000b8a0: ae0ff06f j 8000ab80 <_svfprintf_r+0x11b0> +8000b8a4: 01c12703 lw a4,28(sp) +8000b8a8: ffd00793 li a5,-3 +8000b8ac: 00f74463 blt a4,a5,8000b8b4 <_svfprintf_r+0x1ee4> +8000b8b0: 00edda63 bge s11,a4,8000b8c4 <_svfprintf_r+0x1ef4> +8000b8b4: ffe48493 addi s1,s1,-2 +8000b8b8: fdf4f793 andi a5,s1,-33 +8000b8bc: 04f12a23 sw a5,84(sp) +8000b8c0: ee4fe06f j 80009fa4 <_svfprintf_r+0x5d4> +8000b8c4: 02012783 lw a5,32(sp) +8000b8c8: 01c12703 lw a4,28(sp) +8000b8cc: 26f74463 blt a4,a5,8000bb34 <_svfprintf_r+0x2164> +8000b8d0: 02812783 lw a5,40(sp) +8000b8d4: 00070c93 mv s9,a4 +8000b8d8: 0017f793 andi a5,a5,1 +8000b8dc: 00078663 beqz a5,8000b8e8 <_svfprintf_r+0x1f18> +8000b8e0: 02c12783 lw a5,44(sp) +8000b8e4: 00f70cb3 add s9,a4,a5 +8000b8e8: 02812783 lw a5,40(sp) +8000b8ec: 4007f793 andi a5,a5,1024 +8000b8f0: 00078663 beqz a5,8000b8fc <_svfprintf_r+0x1f2c> +8000b8f4: 01c12783 lw a5,28(sp) +8000b8f8: 12f04ae3 bgtz a5,8000c22c <_svfprintf_r+0x285c> +8000b8fc: fffcca93 not s5,s9 +8000b900: 41fada93 srai s5,s5,0x1f +8000b904: 015cfab3 and s5,s9,s5 +8000b908: 06700493 li s1,103 +8000b90c: 02012423 sw zero,40(sp) +8000b910: 02012223 sw zero,36(sp) +8000b914: facfe06f j 8000a0c0 <_svfprintf_r+0x6f0> +8000b918: 0c714783 lbu a5,199(sp) +8000b91c: 00000d93 li s11,0 +8000b920: 00078463 beqz a5,8000b928 <_svfprintf_r+0x1f58> +8000b924: a49fe06f j 8000a36c <_svfprintf_r+0x99c> +8000b928: a8cfe06f j 80009bb4 <_svfprintf_r+0x1e4> +8000b92c: 0e410613 addi a2,sp,228 +8000b930: 000b0593 mv a1,s6 +8000b934: 000d0513 mv a0,s10 +8000b938: 580030ef jal ra,8000eeb8 <__ssprint_r> +8000b93c: e00516e3 bnez a0,8000b748 <_svfprintf_r+0x1d78> +8000b940: 00044683 lbu a3,0(s0) +8000b944: 0ec12783 lw a5,236(sp) +8000b948: 10c10893 addi a7,sp,268 +8000b94c: 00dd8db3 add s11,s11,a3 +8000b950: fe8ff06f j 8000b138 <_svfprintf_r+0x1768> +8000b954: 0b010a93 addi s5,sp,176 +8000b958: 0dc10813 addi a6,sp,220 +8000b95c: 0d010793 addi a5,sp,208 +8000b960: 0cc10713 addi a4,sp,204 +8000b964: 000d8693 mv a3,s11 +8000b968: 00300613 li a2,3 +8000b96c: 000a8593 mv a1,s5 +8000b970: 000d0513 mv a0,s10 +8000b974: 05112223 sw a7,68(sp) +8000b978: 0bc12823 sw t3,176(sp) +8000b97c: 05c12023 sw t3,64(sp) +8000b980: 0bd12a23 sw t4,180(sp) +8000b984: 03d12223 sw t4,36(sp) +8000b988: 0be12c23 sw t5,184(sp) +8000b98c: 03e12023 sw t5,32(sp) +8000b990: 0a612e23 sw t1,188(sp) +8000b994: 00612e23 sw t1,28(sp) +8000b998: c49fa0ef jal ra,800065e0 <_ldtoa_r> +8000b99c: 01c12303 lw t1,28(sp) +8000b9a0: 02012f03 lw t5,32(sp) +8000b9a4: 02412e83 lw t4,36(sp) +8000b9a8: 04012e03 lw t3,64(sp) +8000b9ac: 04412883 lw a7,68(sp) +8000b9b0: 00050b13 mv s6,a0 +8000b9b4: 04600793 li a5,70 +8000b9b8: 01bb0933 add s2,s6,s11 +8000b9bc: 62fb9a63 bne s7,a5,8000bff0 <_svfprintf_r+0x2620> +8000b9c0: 000b4683 lbu a3,0(s6) +8000b9c4: 03000793 li a5,48 +8000b9c8: 10f686e3 beq a3,a5,8000c2d4 <_svfprintf_r+0x2904> +8000b9cc: 0a010c93 addi s9,sp,160 +8000b9d0: 0cc12783 lw a5,204(sp) +8000b9d4: 00f90933 add s2,s2,a5 +8000b9d8: d40fe06f j 80009f18 <_svfprintf_r+0x548> +8000b9dc: 02d00793 li a5,45 +8000b9e0: 0cf103a3 sb a5,199(sp) +8000b9e4: addff06f j 8000b4c0 <_svfprintf_r+0x1af0> +8000b9e8: 0b010a93 addi s5,sp,176 +8000b9ec: 0d010793 addi a5,sp,208 +8000b9f0: 0dc10813 addi a6,sp,220 +8000b9f4: 0cc10713 addi a4,sp,204 +8000b9f8: 000d8693 mv a3,s11 +8000b9fc: 00200613 li a2,2 +8000ba00: 000a8593 mv a1,s5 +8000ba04: 000d0513 mv a0,s10 +8000ba08: 0bc12823 sw t3,176(sp) +8000ba0c: 05c12023 sw t3,64(sp) +8000ba10: 0bd12a23 sw t4,180(sp) +8000ba14: 03d12223 sw t4,36(sp) +8000ba18: 0be12c23 sw t5,184(sp) +8000ba1c: 03e12023 sw t5,32(sp) +8000ba20: 0a612e23 sw t1,188(sp) +8000ba24: 00612e23 sw t1,28(sp) +8000ba28: bb9fa0ef jal ra,800065e0 <_ldtoa_r> +8000ba2c: 04700793 li a5,71 +8000ba30: 01c12303 lw t1,28(sp) +8000ba34: 02012f03 lw t5,32(sp) +8000ba38: 02412e83 lw t4,36(sp) +8000ba3c: 04012e03 lw t3,64(sp) +8000ba40: 04412883 lw a7,68(sp) +8000ba44: 00050b13 mv s6,a0 +8000ba48: f6fb96e3 bne s7,a5,8000b9b4 <_svfprintf_r+0x1fe4> +8000ba4c: 02812783 lw a5,40(sp) +8000ba50: 0017f793 andi a5,a5,1 +8000ba54: 58079863 bnez a5,8000bfe4 <_svfprintf_r+0x2614> +8000ba58: 04700793 li a5,71 +8000ba5c: 0dc12703 lw a4,220(sp) +8000ba60: 04f12a23 sw a5,84(sp) +8000ba64: d10fe06f j 80009f74 <_svfprintf_r+0x5a4> +8000ba68: 0e410613 addi a2,sp,228 +8000ba6c: 000c0593 mv a1,s8 +8000ba70: 000d0513 mv a0,s10 +8000ba74: 444030ef jal ra,8000eeb8 <__ssprint_r> +8000ba78: 00050463 beqz a0,8000ba80 <_svfprintf_r+0x20b0> +8000ba7c: f75fe06f j 8000a9f0 <_svfprintf_r+0x1020> +8000ba80: 0cc12483 lw s1,204(sp) +8000ba84: 0ec12783 lw a5,236(sp) +8000ba88: 10c10893 addi a7,sp,268 +8000ba8c: 938ff06f j 8000abc4 <_svfprintf_r+0x11f4> +8000ba90: 0c714783 lbu a5,199(sp) +8000ba94: 01212a23 sw s2,20(sp) +8000ba98: 02012423 sw zero,40(sp) +8000ba9c: 02012223 sw zero,36(sp) +8000baa0: 00012e23 sw zero,28(sp) +8000baa4: 000d8a93 mv s5,s11 +8000baa8: 000d8c93 mv s9,s11 +8000baac: 00000d93 li s11,0 +8000bab0: 00078463 beqz a5,8000bab8 <_svfprintf_r+0x20e8> +8000bab4: 8b9fe06f j 8000a36c <_svfprintf_r+0x99c> +8000bab8: 8fcfe06f j 80009bb4 <_svfprintf_r+0x1e4> +8000babc: 0e410613 addi a2,sp,228 +8000bac0: 000c0593 mv a1,s8 +8000bac4: 000d0513 mv a0,s10 +8000bac8: 3f0030ef jal ra,8000eeb8 <__ssprint_r> +8000bacc: 00050463 beqz a0,8000bad4 <_svfprintf_r+0x2104> +8000bad0: f21fe06f j 8000a9f0 <_svfprintf_r+0x1020> +8000bad4: 0cc12483 lw s1,204(sp) +8000bad8: 02012703 lw a4,32(sp) +8000badc: 0ec12783 lw a5,236(sp) +8000bae0: 10c10893 addi a7,sp,268 +8000bae4: 409704b3 sub s1,a4,s1 +8000bae8: 924ff06f j 8000ac0c <_svfprintf_r+0x123c> +8000baec: 02812783 lw a5,40(sp) +8000baf0: 01c12703 lw a4,28(sp) +8000baf4: 0017f793 andi a5,a5,1 +8000baf8: 01b7e7b3 or a5,a5,s11 +8000bafc: 04e054e3 blez a4,8000c344 <_svfprintf_r+0x2974> +8000bb00: 7a079663 bnez a5,8000c2ac <_svfprintf_r+0x28dc> +8000bb04: 01c12c83 lw s9,28(sp) +8000bb08: 06600493 li s1,102 +8000bb0c: 02812783 lw a5,40(sp) +8000bb10: 4007f793 andi a5,a5,1024 +8000bb14: 70079e63 bnez a5,8000c230 <_svfprintf_r+0x2860> +8000bb18: fffcca93 not s5,s9 +8000bb1c: 41fada93 srai s5,s5,0x1f +8000bb20: 015cfab3 and s5,s9,s5 +8000bb24: de9ff06f j 8000b90c <_svfprintf_r+0x1f3c> +8000bb28: 80015737 lui a4,0x80015 +8000bb2c: b9c70b13 addi s6,a4,-1124 # 80014b9c <__BSS_END__+0xffffdf60> +8000bb30: 9a1ff06f j 8000b4d0 <_svfprintf_r+0x1b00> +8000bb34: 02012783 lw a5,32(sp) +8000bb38: 02c12703 lw a4,44(sp) +8000bb3c: 06700493 li s1,103 +8000bb40: 00e78cb3 add s9,a5,a4 +8000bb44: 01c12783 lw a5,28(sp) +8000bb48: fcf042e3 bgtz a5,8000bb0c <_svfprintf_r+0x213c> +8000bb4c: 40fc8cb3 sub s9,s9,a5 +8000bb50: 001c8c93 addi s9,s9,1 +8000bb54: fffcca93 not s5,s9 +8000bb58: 41fada93 srai s5,s5,0x1f +8000bb5c: 015cfab3 and s5,s9,s5 +8000bb60: dadff06f j 8000b90c <_svfprintf_r+0x1f3c> +8000bb64: 800156b7 lui a3,0x80015 +8000bb68: 27468e93 addi t4,a3,628 # 80015274 <__BSS_END__+0xffffe638> +8000bb6c: f48fe06f j 8000a2b4 <_svfprintf_r+0x8e4> +8000bb70: 03000793 li a5,48 +8000bb74: 0cf10423 sb a5,200(sp) +8000bb78: 05800793 li a5,88 +8000bb7c: 002a6713 ori a4,s4,2 +8000bb80: 0cf104a3 sb a5,201(sp) +8000bb84: 02e12423 sw a4,40(sp) +8000bb88: 06300793 li a5,99 +8000bb8c: 00012823 sw zero,16(sp) +8000bb90: 14c10b13 addi s6,sp,332 +8000bb94: 41b7ce63 blt a5,s11,8000bfb0 <_svfprintf_r+0x25e0> +8000bb98: 0fc12303 lw t1,252(sp) +8000bb9c: fdf4fb93 andi s7,s1,-33 +8000bba0: 05712a23 sw s7,84(sp) +8000bba4: 04012c23 sw zero,88(sp) +8000bba8: 0f012e03 lw t3,240(sp) +8000bbac: 0f412e83 lw t4,244(sp) +8000bbb0: 0f812f03 lw t5,248(sp) +8000bbb4: 102a6a13 ori s4,s4,258 +8000bbb8: 38034263 bltz t1,8000bf3c <_svfprintf_r+0x256c> +8000bbbc: 06100793 li a5,97 +8000bbc0: 54f48e63 beq s1,a5,8000c11c <_svfprintf_r+0x274c> +8000bbc4: 04100793 li a5,65 +8000bbc8: 00f48463 beq s1,a5,8000bbd0 <_svfprintf_r+0x2200> +8000bbcc: ac8fe06f j 80009e94 <_svfprintf_r+0x4c4> +8000bbd0: 0b010a93 addi s5,sp,176 +8000bbd4: 000a8513 mv a0,s5 +8000bbd8: 05112823 sw a7,80(sp) +8000bbdc: 0bc12823 sw t3,176(sp) +8000bbe0: 0bd12a23 sw t4,180(sp) +8000bbe4: 0be12c23 sw t5,184(sp) +8000bbe8: 0a612e23 sw t1,188(sp) +8000bbec: 1cd080ef jal ra,800145b8 <__trunctfdf2> +8000bbf0: 0cc10613 addi a2,sp,204 +8000bbf4: 8b5fd0ef jal ra,800094a8 +8000bbf8: 00058613 mv a2,a1 +8000bbfc: 00050593 mv a1,a0 +8000bc00: 000a8513 mv a0,s5 +8000bc04: 7c0080ef jal ra,800143c4 <__extenddftf2> +8000bc08: 0b012783 lw a5,176(sp) +8000bc0c: 0a010c93 addi s9,sp,160 +8000bc10: 09010913 addi s2,sp,144 +8000bc14: 08f12823 sw a5,144(sp) +8000bc18: 0b412783 lw a5,180(sp) +8000bc1c: 08010613 addi a2,sp,128 +8000bc20: 00090593 mv a1,s2 +8000bc24: 08f12a23 sw a5,148(sp) +8000bc28: 0b812783 lw a5,184(sp) +8000bc2c: 000c8513 mv a0,s9 +8000bc30: 04c12023 sw a2,64(sp) +8000bc34: 08f12c23 sw a5,152(sp) +8000bc38: 0bc12783 lw a5,188(sp) +8000bc3c: 08012023 sw zero,128(sp) +8000bc40: 08012223 sw zero,132(sp) +8000bc44: 08f12e23 sw a5,156(sp) +8000bc48: 3ffc07b7 lui a5,0x3ffc0 +8000bc4c: 08f12623 sw a5,140(sp) +8000bc50: 08012423 sw zero,136(sp) +8000bc54: 7e9050ef jal ra,80011c3c <__multf3> +8000bc58: 0a012803 lw a6,160(sp) +8000bc5c: 0a412e03 lw t3,164(sp) +8000bc60: 0a812e83 lw t4,168(sp) +8000bc64: 0ac12f03 lw t5,172(sp) +8000bc68: 000c8593 mv a1,s9 +8000bc6c: 000a8513 mv a0,s5 +8000bc70: 0b012823 sw a6,176(sp) +8000bc74: 05012223 sw a6,68(sp) +8000bc78: 0bc12a23 sw t3,180(sp) +8000bc7c: 03c12223 sw t3,36(sp) +8000bc80: 0bd12c23 sw t4,184(sp) +8000bc84: 03d12023 sw t4,32(sp) +8000bc88: 0be12e23 sw t5,188(sp) +8000bc8c: 01e12e23 sw t5,28(sp) +8000bc90: 0a012023 sw zero,160(sp) +8000bc94: 0a012223 sw zero,164(sp) +8000bc98: 0a012423 sw zero,168(sp) +8000bc9c: 0a012623 sw zero,172(sp) +8000bca0: 449050ef jal ra,800118e8 <__eqtf2> +8000bca4: 01c12f03 lw t5,28(sp) +8000bca8: 02012e83 lw t4,32(sp) +8000bcac: 02412e03 lw t3,36(sp) +8000bcb0: 04412803 lw a6,68(sp) +8000bcb4: 05012883 lw a7,80(sp) +8000bcb8: 00051663 bnez a0,8000bcc4 <_svfprintf_r+0x22f4> +8000bcbc: 00100793 li a5,1 +8000bcc0: 0cf12623 sw a5,204(sp) +8000bcc4: 800157b7 lui a5,0x80015 +8000bcc8: bb878793 addi a5,a5,-1096 # 80014bb8 <__BSS_END__+0xffffdf7c> +8000bccc: 02f12223 sw a5,36(sp) +8000bcd0: fffd8693 addi a3,s11,-1 +8000bcd4: 05412e23 sw s4,92(sp) +8000bcd8: 06912223 sw s1,100(sp) +8000bcdc: 07b12623 sw s11,108(sp) +8000bce0: 07a12a23 sw s10,116(sp) +8000bce4: 07812c23 sw s8,120(sp) +8000bce8: 000b0b93 mv s7,s6 +8000bcec: 06812023 sw s0,96(sp) +8000bcf0: 07312423 sw s3,104(sp) +8000bcf4: 07112823 sw a7,112(sp) +8000bcf8: 00068c13 mv s8,a3 +8000bcfc: 07612e23 sw s6,124(sp) +8000bd00: 00080d13 mv s10,a6 +8000bd04: 000e0d93 mv s11,t3 +8000bd08: 000e8493 mv s1,t4 +8000bd0c: 000f0a13 mv s4,t5 +8000bd10: 0480006f j 8000bd58 <_svfprintf_r+0x2388> +8000bd14: 000c8593 mv a1,s9 +8000bd18: 000a8513 mv a0,s5 +8000bd1c: 02c12023 sw a2,32(sp) +8000bd20: 01f12e23 sw t6,28(sp) +8000bd24: 0bf12c23 sw t6,184(sp) +8000bd28: 0ac12e23 sw a2,188(sp) +8000bd2c: 0b612823 sw s6,176(sp) +8000bd30: 0b312a23 sw s3,180(sp) +8000bd34: 0a012023 sw zero,160(sp) +8000bd38: 0a012223 sw zero,164(sp) +8000bd3c: 0a012423 sw zero,168(sp) +8000bd40: 0a012623 sw zero,172(sp) +8000bd44: 3a5050ef jal ra,800118e8 <__eqtf2> +8000bd48: 01c12f83 lw t6,28(sp) +8000bd4c: 02012603 lw a2,32(sp) +8000bd50: fffc0c13 addi s8,s8,-1 +8000bd54: 0e050263 beqz a0,8000be38 <_svfprintf_r+0x2468> +8000bd58: 400307b7 lui a5,0x40030 +8000bd5c: 00090613 mv a2,s2 +8000bd60: 000c8593 mv a1,s9 +8000bd64: 000a8513 mv a0,s5 +8000bd68: 08f12e23 sw a5,156(sp) +8000bd6c: 0ba12023 sw s10,160(sp) +8000bd70: 0bb12223 sw s11,164(sp) +8000bd74: 0a912423 sw s1,168(sp) +8000bd78: 0b412623 sw s4,172(sp) +8000bd7c: 08012823 sw zero,144(sp) +8000bd80: 08012a23 sw zero,148(sp) +8000bd84: 08012c23 sw zero,152(sp) +8000bd88: 6b5050ef jal ra,80011c3c <__multf3> +8000bd8c: 000a8513 mv a0,s5 +8000bd90: 3d0080ef jal ra,80014160 <__fixtfsi> +8000bd94: 00050593 mv a1,a0 +8000bd98: 00050413 mv s0,a0 +8000bd9c: 000a8513 mv a0,s5 +8000bda0: 0b012983 lw s3,176(sp) +8000bda4: 0b412483 lw s1,180(sp) +8000bda8: 0b812b03 lw s6,184(sp) +8000bdac: 0bc12a03 lw s4,188(sp) +8000bdb0: 4c4080ef jal ra,80014274 <__floatsitf> +8000bdb4: 0b012703 lw a4,176(sp) +8000bdb8: 04012603 lw a2,64(sp) +8000bdbc: 00090593 mv a1,s2 +8000bdc0: 08e12023 sw a4,128(sp) +8000bdc4: 0b412703 lw a4,180(sp) +8000bdc8: 000c8513 mv a0,s9 +8000bdcc: 09312823 sw s3,144(sp) +8000bdd0: 08e12223 sw a4,132(sp) +8000bdd4: 0b812703 lw a4,184(sp) +8000bdd8: 08912a23 sw s1,148(sp) +8000bddc: 09612c23 sw s6,152(sp) +8000bde0: 08e12423 sw a4,136(sp) +8000bde4: 0bc12703 lw a4,188(sp) +8000bde8: 09412e23 sw s4,156(sp) +8000bdec: 08e12623 sw a4,140(sp) +8000bdf0: 651060ef jal ra,80012c40 <__subtf3> +8000bdf4: 02412783 lw a5,36(sp) +8000bdf8: 0a012b03 lw s6,160(sp) +8000bdfc: 0a412983 lw s3,164(sp) +8000be00: 00878733 add a4,a5,s0 +8000be04: 00074703 lbu a4,0(a4) +8000be08: 0a812f83 lw t6,168(sp) +8000be0c: 0ac12603 lw a2,172(sp) +8000be10: 05712823 sw s7,80(sp) +8000be14: 00eb8023 sb a4,0(s7) +8000be18: 05812223 sw s8,68(sp) +8000be1c: fff00793 li a5,-1 +8000be20: 001b8b93 addi s7,s7,1 +8000be24: 000b0d13 mv s10,s6 +8000be28: 00098d93 mv s11,s3 +8000be2c: 000f8493 mv s1,t6 +8000be30: 00060a13 mv s4,a2 +8000be34: eefc10e3 bne s8,a5,8000bd14 <_svfprintf_r+0x2344> +8000be38: 07012883 lw a7,112(sp) +8000be3c: 000b0393 mv t2,s6 +8000be40: 00098293 mv t0,s3 +8000be44: 3ffe0937 lui s2,0x3ffe0 +8000be48: 000c8593 mv a1,s9 +8000be4c: 000a8513 mv a0,s5 +8000be50: 03112023 sw a7,32(sp) +8000be54: 00812e23 sw s0,28(sp) +8000be58: 05c12a03 lw s4,92(sp) +8000be5c: 06412483 lw s1,100(sp) +8000be60: 06012403 lw s0,96(sp) +8000be64: 0a712823 sw t2,176(sp) +8000be68: 06712223 sw t2,100(sp) +8000be6c: 0a512a23 sw t0,180(sp) +8000be70: 06512023 sw t0,96(sp) +8000be74: 0bf12c23 sw t6,184(sp) +8000be78: 05f12e23 sw t6,92(sp) +8000be7c: 0ac12e23 sw a2,188(sp) +8000be80: 04c12023 sw a2,64(sp) +8000be84: 0a012023 sw zero,160(sp) +8000be88: 0a012223 sw zero,164(sp) +8000be8c: 0a012423 sw zero,168(sp) +8000be90: 0b212623 sw s2,172(sp) +8000be94: 321050ef jal ra,800119b4 <__getf2> +8000be98: 06c12d83 lw s11,108(sp) +8000be9c: 07412d03 lw s10,116(sp) +8000bea0: 07812c03 lw s8,120(sp) +8000bea4: 07c12b03 lw s6,124(sp) +8000bea8: 06812983 lw s3,104(sp) +8000beac: 02012883 lw a7,32(sp) +8000beb0: 0aa04063 bgtz a0,8000bf50 <_svfprintf_r+0x2580> +8000beb4: 06412383 lw t2,100(sp) +8000beb8: 06012283 lw t0,96(sp) +8000bebc: 05c12f83 lw t6,92(sp) +8000bec0: 04012603 lw a2,64(sp) +8000bec4: 000c8593 mv a1,s9 +8000bec8: 000a8513 mv a0,s5 +8000becc: 0a712823 sw t2,176(sp) +8000bed0: 0a512a23 sw t0,180(sp) +8000bed4: 0bf12c23 sw t6,184(sp) +8000bed8: 0ac12e23 sw a2,188(sp) +8000bedc: 0a012023 sw zero,160(sp) +8000bee0: 0a012223 sw zero,164(sp) +8000bee4: 0a012423 sw zero,168(sp) +8000bee8: 0b212623 sw s2,172(sp) +8000beec: 1fd050ef jal ra,800118e8 <__eqtf2> +8000bef0: 02012883 lw a7,32(sp) +8000bef4: 00051863 bnez a0,8000bf04 <_svfprintf_r+0x2534> +8000bef8: 01c12783 lw a5,28(sp) +8000befc: 0017fc93 andi s9,a5,1 +8000bf00: 040c9863 bnez s9,8000bf50 <_svfprintf_r+0x2580> +8000bf04: 04412783 lw a5,68(sp) +8000bf08: 03000613 li a2,48 +8000bf0c: 00178693 addi a3,a5,1 # 40030001 <_start-0x3ffcffff> +8000bf10: 00db86b3 add a3,s7,a3 +8000bf14: 0007c863 bltz a5,8000bf24 <_svfprintf_r+0x2554> +8000bf18: 001b8b93 addi s7,s7,1 +8000bf1c: fecb8fa3 sb a2,-1(s7) +8000bf20: fedb9ce3 bne s7,a3,8000bf18 <_svfprintf_r+0x2548> +8000bf24: 416b87b3 sub a5,s7,s6 +8000bf28: 02f12023 sw a5,32(sp) +8000bf2c: 850fe06f j 80009f7c <_svfprintf_r+0x5ac> +8000bf30: 03412423 sw s4,40(sp) +8000bf34: 00012823 sw zero,16(sp) +8000bf38: 00090a13 mv s4,s2 +8000bf3c: 800007b7 lui a5,0x80000 +8000bf40: 0067c333 xor t1,a5,t1 +8000bf44: 02d00793 li a5,45 +8000bf48: 04f12c23 sw a5,88(sp) +8000bf4c: c71ff06f j 8000bbbc <_svfprintf_r+0x21ec> +8000bf50: 05012783 lw a5,80(sp) +8000bf54: 000b8693 mv a3,s7 +8000bf58: 0cf12e23 sw a5,220(sp) +8000bf5c: 02412783 lw a5,36(sp) +8000bf60: fffbc603 lbu a2,-1(s7) +8000bf64: 00f7c583 lbu a1,15(a5) # 8000000f <__BSS_END__+0xfffe93d3> +8000bf68: 02b61063 bne a2,a1,8000bf88 <_svfprintf_r+0x25b8> +8000bf6c: 03000513 li a0,48 +8000bf70: fea68fa3 sb a0,-1(a3) +8000bf74: 0dc12683 lw a3,220(sp) +8000bf78: fff68793 addi a5,a3,-1 +8000bf7c: 0cf12e23 sw a5,220(sp) +8000bf80: fff6c603 lbu a2,-1(a3) +8000bf84: fec586e3 beq a1,a2,8000bf70 <_svfprintf_r+0x25a0> +8000bf88: 00160593 addi a1,a2,1 +8000bf8c: 03900513 li a0,57 +8000bf90: 0ff5f593 andi a1,a1,255 +8000bf94: 00a60663 beq a2,a0,8000bfa0 <_svfprintf_r+0x25d0> +8000bf98: feb68fa3 sb a1,-1(a3) +8000bf9c: f89ff06f j 8000bf24 <_svfprintf_r+0x2554> +8000bfa0: 02412783 lw a5,36(sp) +8000bfa4: 00a7c583 lbu a1,10(a5) +8000bfa8: feb68fa3 sb a1,-1(a3) +8000bfac: f79ff06f j 8000bf24 <_svfprintf_r+0x2554> +8000bfb0: 001d8593 addi a1,s11,1 +8000bfb4: 000d0513 mv a0,s10 +8000bfb8: 01112823 sw a7,16(sp) +8000bfbc: b29fb0ef jal ra,80007ae4 <_malloc_r> +8000bfc0: 01012883 lw a7,16(sp) +8000bfc4: 00050b13 mv s6,a0 +8000bfc8: 3e050863 beqz a0,8000c3b8 <_svfprintf_r+0x29e8> +8000bfcc: 00a12823 sw a0,16(sp) +8000bfd0: bc9ff06f j 8000bb98 <_svfprintf_r+0x21c8> +8000bfd4: 03000793 li a5,48 +8000bfd8: 0cf10423 sb a5,200(sp) +8000bfdc: 07800793 li a5,120 +8000bfe0: b9dff06f j 8000bb7c <_svfprintf_r+0x21ac> +8000bfe4: 04700793 li a5,71 +8000bfe8: 01bb0933 add s2,s6,s11 +8000bfec: 04f12a23 sw a5,84(sp) +8000bff0: 0a010c93 addi s9,sp,160 +8000bff4: f25fd06f j 80009f18 <_svfprintf_r+0x548> +8000bff8: 00812703 lw a4,8(sp) +8000bffc: 009787b3 add a5,a5,s1 +8000c000: 00168693 addi a3,a3,1 +8000c004: 00e8a023 sw a4,0(a7) +8000c008: 0098a223 sw s1,4(a7) +8000c00c: 0ef12623 sw a5,236(sp) +8000c010: 0ed12423 sw a3,232(sp) +8000c014: 00700613 li a2,7 +8000c018: b6d65863 bge a2,a3,8000b388 <_svfprintf_r+0x19b8> +8000c01c: 0e410613 addi a2,sp,228 +8000c020: 000c0593 mv a1,s8 +8000c024: 000d0513 mv a0,s10 +8000c028: 691020ef jal ra,8000eeb8 <__ssprint_r> +8000c02c: 00050463 beqz a0,8000c034 <_svfprintf_r+0x2664> +8000c030: 9c1fe06f j 8000a9f0 <_svfprintf_r+0x1020> +8000c034: 0ec12783 lw a5,236(sp) +8000c038: 0e812683 lw a3,232(sp) +8000c03c: 10c10893 addi a7,sp,268 +8000c040: b4cff06f j 8000b38c <_svfprintf_r+0x19bc> +8000c044: 000a0b93 mv s7,s4 +8000c048: dfcfe06f j 8000a644 <_svfprintf_r+0xc74> +8000c04c: 000d9463 bnez s11,8000c054 <_svfprintf_r+0x2684> +8000c050: 00100d93 li s11,1 +8000c054: 0fc12303 lw t1,252(sp) +8000c058: 0f012e03 lw t3,240(sp) +8000c05c: 0f412e83 lw t4,244(sp) +8000c060: 0f812f03 lw t5,248(sp) +8000c064: 100a6913 ori s2,s4,256 +8000c068: ec0344e3 bltz t1,8000bf30 <_svfprintf_r+0x2560> +8000c06c: 0b010a93 addi s5,sp,176 +8000c070: 0dc10813 addi a6,sp,220 +8000c074: 0d010793 addi a5,sp,208 +8000c078: 0cc10713 addi a4,sp,204 +8000c07c: 000d8693 mv a3,s11 +8000c080: 00200613 li a2,2 +8000c084: 000a8593 mv a1,s5 +8000c088: 000d0513 mv a0,s10 +8000c08c: 05112223 sw a7,68(sp) +8000c090: 0bc12823 sw t3,176(sp) +8000c094: 05c12023 sw t3,64(sp) +8000c098: 0bd12a23 sw t4,180(sp) +8000c09c: 03d12223 sw t4,36(sp) +8000c0a0: 0be12c23 sw t5,184(sp) +8000c0a4: 03e12023 sw t5,32(sp) +8000c0a8: 0a612e23 sw t1,188(sp) +8000c0ac: 00612e23 sw t1,28(sp) +8000c0b0: d30fa0ef jal ra,800065e0 <_ldtoa_r> +8000c0b4: 01c12303 lw t1,28(sp) +8000c0b8: 03412423 sw s4,40(sp) +8000c0bc: 02012f03 lw t5,32(sp) +8000c0c0: 02412e83 lw t4,36(sp) +8000c0c4: 04012e03 lw t3,64(sp) +8000c0c8: 04412883 lw a7,68(sp) +8000c0cc: 00050b13 mv s6,a0 +8000c0d0: 00090a13 mv s4,s2 +8000c0d4: 00012823 sw zero,16(sp) +8000c0d8: 04012c23 sw zero,88(sp) +8000c0dc: 971ff06f j 8000ba4c <_svfprintf_r+0x207c> +8000c0e0: fff00793 li a5,-1 +8000c0e4: 00f12623 sw a5,12(sp) +8000c0e8: c05fd06f j 80009cec <_svfprintf_r+0x31c> +8000c0ec: 0d610693 addi a3,sp,214 +8000c0f0: 00061863 bnez a2,8000c100 <_svfprintf_r+0x2730> +8000c0f4: 03000693 li a3,48 +8000c0f8: 0cd10b23 sb a3,214(sp) +8000c0fc: 0d710693 addi a3,sp,215 +8000c100: 1b010713 addi a4,sp,432 +8000c104: 03078793 addi a5,a5,48 +8000c108: 40e68633 sub a2,a3,a4 +8000c10c: 00f68023 sb a5,0(a3) +8000c110: 0dd60793 addi a5,a2,221 +8000c114: 02f12c23 sw a5,56(sp) +8000c118: f65fd06f j 8000a07c <_svfprintf_r+0x6ac> +8000c11c: 0b010a93 addi s5,sp,176 +8000c120: 000a8513 mv a0,s5 +8000c124: 05112823 sw a7,80(sp) +8000c128: 0bc12823 sw t3,176(sp) +8000c12c: 0bd12a23 sw t4,180(sp) +8000c130: 0be12c23 sw t5,184(sp) +8000c134: 0a612e23 sw t1,188(sp) +8000c138: 480080ef jal ra,800145b8 <__trunctfdf2> +8000c13c: 0cc10613 addi a2,sp,204 +8000c140: b68fd0ef jal ra,800094a8 +8000c144: 00058613 mv a2,a1 +8000c148: 00050593 mv a1,a0 +8000c14c: 000a8513 mv a0,s5 +8000c150: 274080ef jal ra,800143c4 <__extenddftf2> +8000c154: 0b012783 lw a5,176(sp) +8000c158: 0a010c93 addi s9,sp,160 +8000c15c: 09010913 addi s2,sp,144 +8000c160: 08f12823 sw a5,144(sp) +8000c164: 0b412783 lw a5,180(sp) +8000c168: 08010613 addi a2,sp,128 +8000c16c: 00090593 mv a1,s2 +8000c170: 08f12a23 sw a5,148(sp) +8000c174: 0b812783 lw a5,184(sp) +8000c178: 000c8513 mv a0,s9 +8000c17c: 04c12023 sw a2,64(sp) +8000c180: 08f12c23 sw a5,152(sp) +8000c184: 0bc12783 lw a5,188(sp) +8000c188: 08012023 sw zero,128(sp) +8000c18c: 08012223 sw zero,132(sp) +8000c190: 08f12e23 sw a5,156(sp) +8000c194: 3ffc07b7 lui a5,0x3ffc0 +8000c198: 08f12623 sw a5,140(sp) +8000c19c: 08012423 sw zero,136(sp) +8000c1a0: 29d050ef jal ra,80011c3c <__multf3> +8000c1a4: 0a012803 lw a6,160(sp) +8000c1a8: 0a412e03 lw t3,164(sp) +8000c1ac: 0a812e83 lw t4,168(sp) +8000c1b0: 0ac12f03 lw t5,172(sp) +8000c1b4: 000c8593 mv a1,s9 +8000c1b8: 000a8513 mv a0,s5 +8000c1bc: 0b012823 sw a6,176(sp) +8000c1c0: 05012223 sw a6,68(sp) +8000c1c4: 0bc12a23 sw t3,180(sp) +8000c1c8: 03c12223 sw t3,36(sp) +8000c1cc: 0bd12c23 sw t4,184(sp) +8000c1d0: 03d12023 sw t4,32(sp) +8000c1d4: 0be12e23 sw t5,188(sp) +8000c1d8: 01e12e23 sw t5,28(sp) +8000c1dc: 0a012023 sw zero,160(sp) +8000c1e0: 0a012223 sw zero,164(sp) +8000c1e4: 0a012423 sw zero,168(sp) +8000c1e8: 0a012623 sw zero,172(sp) +8000c1ec: 6fc050ef jal ra,800118e8 <__eqtf2> +8000c1f0: 01c12f03 lw t5,28(sp) +8000c1f4: 02012e83 lw t4,32(sp) +8000c1f8: 02412e03 lw t3,36(sp) +8000c1fc: 04412803 lw a6,68(sp) +8000c200: 05012883 lw a7,80(sp) +8000c204: 00051663 bnez a0,8000c210 <_svfprintf_r+0x2840> +8000c208: 00100793 li a5,1 +8000c20c: 0cf12623 sw a5,204(sp) +8000c210: 800157b7 lui a5,0x80015 +8000c214: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +8000c218: 02f12223 sw a5,36(sp) +8000c21c: ab5ff06f j 8000bcd0 <_svfprintf_r+0x2300> +8000c220: 00012823 sw zero,16(sp) +8000c224: 00078a13 mv s4,a5 +8000c228: d15ff06f j 8000bf3c <_svfprintf_r+0x256c> +8000c22c: 06700493 li s1,103 +8000c230: 03c12603 lw a2,60(sp) +8000c234: 0ff00693 li a3,255 +8000c238: 00064783 lbu a5,0(a2) +8000c23c: 18d78863 beq a5,a3,8000c3cc <_svfprintf_r+0x29fc> +8000c240: 01c12703 lw a4,28(sp) +8000c244: 00000513 li a0,0 +8000c248: 00000593 li a1,0 +8000c24c: 00e7de63 bge a5,a4,8000c268 <_svfprintf_r+0x2898> +8000c250: 40f70733 sub a4,a4,a5 +8000c254: 00164783 lbu a5,1(a2) +8000c258: 04078463 beqz a5,8000c2a0 <_svfprintf_r+0x28d0> +8000c25c: 00158593 addi a1,a1,1 +8000c260: 00160613 addi a2,a2,1 +8000c264: fed794e3 bne a5,a3,8000c24c <_svfprintf_r+0x287c> +8000c268: 02c12e23 sw a2,60(sp) +8000c26c: 00e12e23 sw a4,28(sp) +8000c270: 02b12223 sw a1,36(sp) +8000c274: 02a12423 sw a0,40(sp) +8000c278: 02812703 lw a4,40(sp) +8000c27c: 02412783 lw a5,36(sp) +8000c280: 00e787b3 add a5,a5,a4 +8000c284: 04812703 lw a4,72(sp) +8000c288: 02e787b3 mul a5,a5,a4 +8000c28c: 01978cb3 add s9,a5,s9 +8000c290: fffcca93 not s5,s9 +8000c294: 41fada93 srai s5,s5,0x1f +8000c298: 015cfab3 and s5,s9,s5 +8000c29c: e25fd06f j 8000a0c0 <_svfprintf_r+0x6f0> +8000c2a0: 00064783 lbu a5,0(a2) +8000c2a4: 00150513 addi a0,a0,1 +8000c2a8: fbdff06f j 8000c264 <_svfprintf_r+0x2894> +8000c2ac: 02c12783 lw a5,44(sp) +8000c2b0: 06600493 li s1,102 +8000c2b4: 00f70cb3 add s9,a4,a5 +8000c2b8: 01bc8cb3 add s9,s9,s11 +8000c2bc: 851ff06f j 8000bb0c <_svfprintf_r+0x213c> +8000c2c0: 02812783 lw a5,40(sp) +8000c2c4: 0017f793 andi a5,a5,1 +8000c2c8: 00079463 bnez a5,8000c2d0 <_svfprintf_r+0x2900> +8000c2cc: dd1fd06f j 8000a09c <_svfprintf_r+0x6cc> +8000c2d0: dc5fd06f j 8000a094 <_svfprintf_r+0x6c4> +8000c2d4: 0a010c93 addi s9,sp,160 +8000c2d8: 000c8593 mv a1,s9 +8000c2dc: 000a8513 mv a0,s5 +8000c2e0: 05112223 sw a7,68(sp) +8000c2e4: 0bc12823 sw t3,176(sp) +8000c2e8: 05c12023 sw t3,64(sp) +8000c2ec: 0bd12a23 sw t4,180(sp) +8000c2f0: 03d12223 sw t4,36(sp) +8000c2f4: 0be12c23 sw t5,184(sp) +8000c2f8: 03e12023 sw t5,32(sp) +8000c2fc: 0a612e23 sw t1,188(sp) +8000c300: 00612e23 sw t1,28(sp) +8000c304: 0a012023 sw zero,160(sp) +8000c308: 0a012223 sw zero,164(sp) +8000c30c: 0a012423 sw zero,168(sp) +8000c310: 0a012623 sw zero,172(sp) +8000c314: 5d4050ef jal ra,800118e8 <__eqtf2> +8000c318: 01c12303 lw t1,28(sp) +8000c31c: 02012f03 lw t5,32(sp) +8000c320: 02412e83 lw t4,36(sp) +8000c324: 04012e03 lw t3,64(sp) +8000c328: 04412883 lw a7,68(sp) +8000c32c: ea050263 beqz a0,8000b9d0 <_svfprintf_r+0x2000> +8000c330: 00100793 li a5,1 +8000c334: 41b787b3 sub a5,a5,s11 +8000c338: 0cf12623 sw a5,204(sp) +8000c33c: 00f90933 add s2,s2,a5 +8000c340: bd9fd06f j 80009f18 <_svfprintf_r+0x548> +8000c344: 00079a63 bnez a5,8000c358 <_svfprintf_r+0x2988> +8000c348: 00100a93 li s5,1 +8000c34c: 06600493 li s1,102 +8000c350: 00100c93 li s9,1 +8000c354: db8ff06f j 8000b90c <_svfprintf_r+0x1f3c> +8000c358: 02c12783 lw a5,44(sp) +8000c35c: 06600493 li s1,102 +8000c360: 00178c93 addi s9,a5,1 +8000c364: 01bc8cb3 add s9,s9,s11 +8000c368: fffcca93 not s5,s9 +8000c36c: 41fada93 srai s5,s5,0x1f +8000c370: 015cfab3 and s5,s9,s5 +8000c374: d98ff06f j 8000b90c <_svfprintf_r+0x1f3c> +8000c378: 00088713 mv a4,a7 +8000c37c: a7cff06f j 8000b5f8 <_svfprintf_r+0x1c28> +8000c380: 01412783 lw a5,20(sp) +8000c384: 0007ad83 lw s11,0(a5) +8000c388: 00478793 addi a5,a5,4 +8000c38c: 000dd463 bgez s11,8000c394 <_svfprintf_r+0x29c4> +8000c390: fff00d93 li s11,-1 +8000c394: 00144483 lbu s1,1(s0) +8000c398: 00f12a23 sw a5,20(sp) +8000c39c: 00070413 mv s0,a4 +8000c3a0: f94fd06f j 80009b34 <_svfprintf_r+0x164> +8000c3a4: 00c00793 li a5,12 +8000c3a8: 00fd2023 sw a5,0(s10) +8000c3ac: fff00793 li a5,-1 +8000c3b0: 00f12623 sw a5,12(sp) +8000c3b4: 939fd06f j 80009cec <_svfprintf_r+0x31c> +8000c3b8: 00cc5703 lhu a4,12(s8) +8000c3bc: 04076793 ori a5,a4,64 +8000c3c0: 00078713 mv a4,a5 +8000c3c4: 00fc1623 sh a5,12(s8) +8000c3c8: 919fd06f j 80009ce0 <_svfprintf_r+0x310> +8000c3cc: 02012423 sw zero,40(sp) +8000c3d0: 02012223 sw zero,36(sp) +8000c3d4: ea5ff06f j 8000c278 <_svfprintf_r+0x28a8> +8000c3d8: 00200793 li a5,2 +8000c3dc: 02f12c23 sw a5,56(sp) +8000c3e0: c9dfd06f j 8000a07c <_svfprintf_r+0x6ac> -8000c4a8 <__sprint_r.part.0>: -8000c4a8: 0645a783 lw a5,100(a1) -8000c4ac: fd010113 addi sp,sp,-48 -8000c4b0: 01612823 sw s6,16(sp) -8000c4b4: 02112623 sw ra,44(sp) -8000c4b8: 02812423 sw s0,40(sp) -8000c4bc: 02912223 sw s1,36(sp) -8000c4c0: 03212023 sw s2,32(sp) -8000c4c4: 01312e23 sw s3,28(sp) -8000c4c8: 01412c23 sw s4,24(sp) -8000c4cc: 01512a23 sw s5,20(sp) -8000c4d0: 01712623 sw s7,12(sp) -8000c4d4: 01812423 sw s8,8(sp) -8000c4d8: 01279713 slli a4,a5,0x12 -8000c4dc: 00060b13 mv s6,a2 -8000c4e0: 0a075863 bgez a4,8000c590 <__sprint_r.part.0+0xe8> -8000c4e4: 00862783 lw a5,8(a2) -8000c4e8: 00062b83 lw s7,0(a2) -8000c4ec: 00058913 mv s2,a1 -8000c4f0: 00050993 mv s3,a0 -8000c4f4: fff00a93 li s5,-1 -8000c4f8: 08078863 beqz a5,8000c588 <__sprint_r.part.0+0xe0> -8000c4fc: 004bac03 lw s8,4(s7) -8000c500: 000ba403 lw s0,0(s7) -8000c504: 002c5a13 srli s4,s8,0x2 -8000c508: 060a0663 beqz s4,8000c574 <__sprint_r.part.0+0xcc> -8000c50c: 00000493 li s1,0 -8000c510: 00c0006f j 8000c51c <__sprint_r.part.0+0x74> -8000c514: 00440413 addi s0,s0,4 -8000c518: 049a0c63 beq s4,s1,8000c570 <__sprint_r.part.0+0xc8> -8000c51c: 00042583 lw a1,0(s0) -8000c520: 00090613 mv a2,s2 -8000c524: 00098513 mv a0,s3 -8000c528: 7f8010ef jal ra,8000dd20 <_fputwc_r> -8000c52c: 00148493 addi s1,s1,1 -8000c530: ff5512e3 bne a0,s5,8000c514 <__sprint_r.part.0+0x6c> -8000c534: fff00513 li a0,-1 -8000c538: 02c12083 lw ra,44(sp) -8000c53c: 02812403 lw s0,40(sp) -8000c540: 000b2423 sw zero,8(s6) -8000c544: 000b2223 sw zero,4(s6) -8000c548: 02412483 lw s1,36(sp) -8000c54c: 02012903 lw s2,32(sp) -8000c550: 01c12983 lw s3,28(sp) -8000c554: 01812a03 lw s4,24(sp) -8000c558: 01412a83 lw s5,20(sp) -8000c55c: 01012b03 lw s6,16(sp) -8000c560: 00c12b83 lw s7,12(sp) -8000c564: 00812c03 lw s8,8(sp) -8000c568: 03010113 addi sp,sp,48 -8000c56c: 00008067 ret -8000c570: 008b2783 lw a5,8(s6) -8000c574: ffcc7c13 andi s8,s8,-4 -8000c578: 418787b3 sub a5,a5,s8 -8000c57c: 00fb2423 sw a5,8(s6) -8000c580: 008b8b93 addi s7,s7,8 -8000c584: f6079ce3 bnez a5,8000c4fc <__sprint_r.part.0+0x54> -8000c588: 00000513 li a0,0 -8000c58c: fadff06f j 8000c538 <__sprint_r.part.0+0x90> -8000c590: 09d010ef jal ra,8000de2c <__sfvwrite_r> -8000c594: fa5ff06f j 8000c538 <__sprint_r.part.0+0x90> +8000c3e4 <__sprint_r.part.0>: +8000c3e4: 0645a783 lw a5,100(a1) +8000c3e8: fd010113 addi sp,sp,-48 +8000c3ec: 01612823 sw s6,16(sp) +8000c3f0: 02112623 sw ra,44(sp) +8000c3f4: 02812423 sw s0,40(sp) +8000c3f8: 02912223 sw s1,36(sp) +8000c3fc: 03212023 sw s2,32(sp) +8000c400: 01312e23 sw s3,28(sp) +8000c404: 01412c23 sw s4,24(sp) +8000c408: 01512a23 sw s5,20(sp) +8000c40c: 01712623 sw s7,12(sp) +8000c410: 01812423 sw s8,8(sp) +8000c414: 01279713 slli a4,a5,0x12 +8000c418: 00060b13 mv s6,a2 +8000c41c: 0a075863 bgez a4,8000c4cc <__sprint_r.part.0+0xe8> +8000c420: 00862783 lw a5,8(a2) +8000c424: 00062b83 lw s7,0(a2) +8000c428: 00058913 mv s2,a1 +8000c42c: 00050993 mv s3,a0 +8000c430: fff00a93 li s5,-1 +8000c434: 08078863 beqz a5,8000c4c4 <__sprint_r.part.0+0xe0> +8000c438: 004bac03 lw s8,4(s7) +8000c43c: 000ba403 lw s0,0(s7) +8000c440: 002c5a13 srli s4,s8,0x2 +8000c444: 060a0663 beqz s4,8000c4b0 <__sprint_r.part.0+0xcc> +8000c448: 00000493 li s1,0 +8000c44c: 00c0006f j 8000c458 <__sprint_r.part.0+0x74> +8000c450: 00440413 addi s0,s0,4 +8000c454: 049a0c63 beq s4,s1,8000c4ac <__sprint_r.part.0+0xc8> +8000c458: 00042583 lw a1,0(s0) +8000c45c: 00090613 mv a2,s2 +8000c460: 00098513 mv a0,s3 +8000c464: 7f8010ef jal ra,8000dc5c <_fputwc_r> +8000c468: 00148493 addi s1,s1,1 +8000c46c: ff5512e3 bne a0,s5,8000c450 <__sprint_r.part.0+0x6c> +8000c470: fff00513 li a0,-1 +8000c474: 02c12083 lw ra,44(sp) +8000c478: 02812403 lw s0,40(sp) +8000c47c: 000b2423 sw zero,8(s6) +8000c480: 000b2223 sw zero,4(s6) +8000c484: 02412483 lw s1,36(sp) +8000c488: 02012903 lw s2,32(sp) +8000c48c: 01c12983 lw s3,28(sp) +8000c490: 01812a03 lw s4,24(sp) +8000c494: 01412a83 lw s5,20(sp) +8000c498: 01012b03 lw s6,16(sp) +8000c49c: 00c12b83 lw s7,12(sp) +8000c4a0: 00812c03 lw s8,8(sp) +8000c4a4: 03010113 addi sp,sp,48 +8000c4a8: 00008067 ret +8000c4ac: 008b2783 lw a5,8(s6) +8000c4b0: ffcc7c13 andi s8,s8,-4 +8000c4b4: 418787b3 sub a5,a5,s8 +8000c4b8: 00fb2423 sw a5,8(s6) +8000c4bc: 008b8b93 addi s7,s7,8 +8000c4c0: f6079ce3 bnez a5,8000c438 <__sprint_r.part.0+0x54> +8000c4c4: 00000513 li a0,0 +8000c4c8: fadff06f j 8000c474 <__sprint_r.part.0+0x90> +8000c4cc: 09d010ef jal ra,8000dd68 <__sfvwrite_r> +8000c4d0: fa5ff06f j 8000c474 <__sprint_r.part.0+0x90> -8000c598 <__sprint_r>: -8000c598: 00862703 lw a4,8(a2) -8000c59c: 00070463 beqz a4,8000c5a4 <__sprint_r+0xc> -8000c5a0: f09ff06f j 8000c4a8 <__sprint_r.part.0> -8000c5a4: 00062223 sw zero,4(a2) -8000c5a8: 00000513 li a0,0 -8000c5ac: 00008067 ret +8000c4d4 <__sprint_r>: +8000c4d4: 00862703 lw a4,8(a2) +8000c4d8: 00070463 beqz a4,8000c4e0 <__sprint_r+0xc> +8000c4dc: f09ff06f j 8000c3e4 <__sprint_r.part.0> +8000c4e0: 00062223 sw zero,4(a2) +8000c4e4: 00000513 li a0,0 +8000c4e8: 00008067 ret -8000c5b0 <_vfiprintf_r>: -8000c5b0: ed010113 addi sp,sp,-304 -8000c5b4: 11312e23 sw s3,284(sp) -8000c5b8: 11412c23 sw s4,280(sp) -8000c5bc: 11712623 sw s7,268(sp) -8000c5c0: 12112623 sw ra,300(sp) -8000c5c4: 12812423 sw s0,296(sp) -8000c5c8: 12912223 sw s1,292(sp) -8000c5cc: 13212023 sw s2,288(sp) -8000c5d0: 11512a23 sw s5,276(sp) -8000c5d4: 11612823 sw s6,272(sp) -8000c5d8: 11812423 sw s8,264(sp) -8000c5dc: 11912223 sw s9,260(sp) -8000c5e0: 11a12023 sw s10,256(sp) -8000c5e4: 0fb12e23 sw s11,252(sp) -8000c5e8: 00d12823 sw a3,16(sp) -8000c5ec: 00050a13 mv s4,a0 -8000c5f0: 00058993 mv s3,a1 -8000c5f4: 00060b93 mv s7,a2 -8000c5f8: 00050663 beqz a0,8000c604 <_vfiprintf_r+0x54> -8000c5fc: 03852783 lw a5,56(a0) -8000c600: 5e078e63 beqz a5,8000cbfc <_vfiprintf_r+0x64c> -8000c604: 00c99703 lh a4,12(s3) -8000c608: 01071793 slli a5,a4,0x10 -8000c60c: 01271693 slli a3,a4,0x12 -8000c610: 0107d793 srli a5,a5,0x10 -8000c614: 0206ca63 bltz a3,8000c648 <_vfiprintf_r+0x98> -8000c618: 000027b7 lui a5,0x2 -8000c61c: 0649a683 lw a3,100(s3) -8000c620: 00f767b3 or a5,a4,a5 -8000c624: 01079793 slli a5,a5,0x10 -8000c628: ffffe737 lui a4,0xffffe -8000c62c: 4107d793 srai a5,a5,0x10 -8000c630: fff70713 addi a4,a4,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> -8000c634: 00e6f733 and a4,a3,a4 -8000c638: 00f99623 sh a5,12(s3) -8000c63c: 01079793 slli a5,a5,0x10 -8000c640: 06e9a223 sw a4,100(s3) -8000c644: 0107d793 srli a5,a5,0x10 -8000c648: 0087f713 andi a4,a5,8 -8000c64c: 40070063 beqz a4,8000ca4c <_vfiprintf_r+0x49c> -8000c650: 0109a703 lw a4,16(s3) -8000c654: 3e070c63 beqz a4,8000ca4c <_vfiprintf_r+0x49c> -8000c658: 01a7f793 andi a5,a5,26 -8000c65c: 00a00713 li a4,10 -8000c660: 40e78663 beq a5,a4,8000ca6c <_vfiprintf_r+0x4bc> -8000c664: 800157b7 lui a5,0x80015 -8000c668: 36c78793 addi a5,a5,876 # 8001536c <__BSS_END__+0xffffe730> -8000c66c: 80015b37 lui s6,0x80015 -8000c670: 04c10493 addi s1,sp,76 -8000c674: 00f12a23 sw a5,20(sp) -8000c678: 80015937 lui s2,0x80015 -8000c67c: 4d8b0793 addi a5,s6,1240 # 800154d8 <__BSS_END__+0xffffe89c> -8000c680: 000b8c13 mv s8,s7 -8000c684: 04912023 sw s1,64(sp) -8000c688: 04012423 sw zero,72(sp) -8000c68c: 04012223 sw zero,68(sp) -8000c690: 00012c23 sw zero,24(sp) -8000c694: 00012e23 sw zero,28(sp) -8000c698: 02012223 sw zero,36(sp) -8000c69c: 02012023 sw zero,32(sp) -8000c6a0: 00012623 sw zero,12(sp) -8000c6a4: 00f12423 sw a5,8(sp) -8000c6a8: 4e890913 addi s2,s2,1256 # 800154e8 <__BSS_END__+0xffffe8ac> -8000c6ac: 00048b93 mv s7,s1 -8000c6b0: 000c4783 lbu a5,0(s8) -8000c6b4: 26078863 beqz a5,8000c924 <_vfiprintf_r+0x374> -8000c6b8: 000c0413 mv s0,s8 -8000c6bc: 02500713 li a4,37 -8000c6c0: 42e78e63 beq a5,a4,8000cafc <_vfiprintf_r+0x54c> -8000c6c4: 00144783 lbu a5,1(s0) -8000c6c8: 00140413 addi s0,s0,1 -8000c6cc: fe079ae3 bnez a5,8000c6c0 <_vfiprintf_r+0x110> -8000c6d0: 41840cb3 sub s9,s0,s8 -8000c6d4: 25840863 beq s0,s8,8000c924 <_vfiprintf_r+0x374> -8000c6d8: 04812703 lw a4,72(sp) -8000c6dc: 04412783 lw a5,68(sp) -8000c6e0: 018ba023 sw s8,0(s7) -8000c6e4: 00ec8733 add a4,s9,a4 -8000c6e8: 00178793 addi a5,a5,1 -8000c6ec: 019ba223 sw s9,4(s7) -8000c6f0: 04e12423 sw a4,72(sp) -8000c6f4: 04f12223 sw a5,68(sp) -8000c6f8: 00700693 li a3,7 -8000c6fc: 008b8b93 addi s7,s7,8 -8000c700: 02f6d063 bge a3,a5,8000c720 <_vfiprintf_r+0x170> -8000c704: 3a070ae3 beqz a4,8000d2b8 <_vfiprintf_r+0xd08> -8000c708: 04010613 addi a2,sp,64 -8000c70c: 00098593 mv a1,s3 -8000c710: 000a0513 mv a0,s4 -8000c714: d95ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000c718: 20051a63 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000c71c: 00048b93 mv s7,s1 -8000c720: 00c12703 lw a4,12(sp) -8000c724: 00044783 lbu a5,0(s0) -8000c728: 01970733 add a4,a4,s9 -8000c72c: 00e12623 sw a4,12(sp) -8000c730: 1e078a63 beqz a5,8000c924 <_vfiprintf_r+0x374> -8000c734: 00144703 lbu a4,1(s0) -8000c738: 00140c13 addi s8,s0,1 -8000c73c: 02010da3 sb zero,59(sp) -8000c740: fff00a93 li s5,-1 -8000c744: 00012223 sw zero,4(sp) -8000c748: 00000b13 li s6,0 -8000c74c: 05a00c93 li s9,90 -8000c750: 00900d13 li s10,9 -8000c754: 02a00613 li a2,42 -8000c758: 001c0c13 addi s8,s8,1 -8000c75c: fe070793 addi a5,a4,-32 -8000c760: 04fce863 bltu s9,a5,8000c7b0 <_vfiprintf_r+0x200> -8000c764: 01412683 lw a3,20(sp) -8000c768: 00279793 slli a5,a5,0x2 -8000c76c: 00d787b3 add a5,a5,a3 -8000c770: 0007a783 lw a5,0(a5) -8000c774: 00078067 jr a5 -8000c778: 00012223 sw zero,4(sp) -8000c77c: fd070793 addi a5,a4,-48 -8000c780: 00412583 lw a1,4(sp) -8000c784: 000c4703 lbu a4,0(s8) -8000c788: 001c0c13 addi s8,s8,1 -8000c78c: 00259693 slli a3,a1,0x2 -8000c790: 00b686b3 add a3,a3,a1 -8000c794: 00169693 slli a3,a3,0x1 -8000c798: 00d787b3 add a5,a5,a3 -8000c79c: 00f12223 sw a5,4(sp) -8000c7a0: fd070793 addi a5,a4,-48 -8000c7a4: fcfd7ee3 bgeu s10,a5,8000c780 <_vfiprintf_r+0x1d0> -8000c7a8: fe070793 addi a5,a4,-32 -8000c7ac: fafcfce3 bgeu s9,a5,8000c764 <_vfiprintf_r+0x1b4> -8000c7b0: 16070a63 beqz a4,8000c924 <_vfiprintf_r+0x374> -8000c7b4: 08e10623 sb a4,140(sp) -8000c7b8: 02010da3 sb zero,59(sp) -8000c7bc: 00100c93 li s9,1 -8000c7c0: 00100d13 li s10,1 -8000c7c4: 08c10413 addi s0,sp,140 -8000c7c8: 00000a93 li s5,0 -8000c7cc: 002b7f93 andi t6,s6,2 -8000c7d0: 000f8463 beqz t6,8000c7d8 <_vfiprintf_r+0x228> -8000c7d4: 002c8c93 addi s9,s9,2 -8000c7d8: 04412703 lw a4,68(sp) -8000c7dc: 084b7f13 andi t5,s6,132 -8000c7e0: 04812783 lw a5,72(sp) -8000c7e4: 00170693 addi a3,a4,1 -8000c7e8: 00068613 mv a2,a3 -8000c7ec: 000f1863 bnez t5,8000c7fc <_vfiprintf_r+0x24c> -8000c7f0: 00412583 lw a1,4(sp) -8000c7f4: 41958db3 sub s11,a1,s9 -8000c7f8: 09b042e3 bgtz s11,8000d07c <_vfiprintf_r+0xacc> -8000c7fc: 03b14583 lbu a1,59(sp) -8000c800: 008b8693 addi a3,s7,8 -8000c804: 02058c63 beqz a1,8000c83c <_vfiprintf_r+0x28c> -8000c808: 03b10713 addi a4,sp,59 -8000c80c: 00178793 addi a5,a5,1 -8000c810: 00eba023 sw a4,0(s7) -8000c814: 00100713 li a4,1 -8000c818: 00eba223 sw a4,4(s7) -8000c81c: 04f12423 sw a5,72(sp) -8000c820: 04c12223 sw a2,68(sp) -8000c824: 00700713 li a4,7 -8000c828: 7ec74063 blt a4,a2,8000d008 <_vfiprintf_r+0xa58> -8000c82c: 00060713 mv a4,a2 -8000c830: 00068b93 mv s7,a3 -8000c834: 00160613 addi a2,a2,1 -8000c838: 00868693 addi a3,a3,8 -8000c83c: 040f8e63 beqz t6,8000c898 <_vfiprintf_r+0x2e8> -8000c840: 03c10713 addi a4,sp,60 -8000c844: 00278793 addi a5,a5,2 -8000c848: 00eba023 sw a4,0(s7) -8000c84c: 00200713 li a4,2 -8000c850: 00eba223 sw a4,4(s7) -8000c854: 04f12423 sw a5,72(sp) -8000c858: 04c12223 sw a2,68(sp) -8000c85c: 00700713 li a4,7 -8000c860: 00c750e3 bge a4,a2,8000d060 <_vfiprintf_r+0xab0> -8000c864: 2a0784e3 beqz a5,8000d30c <_vfiprintf_r+0xd5c> -8000c868: 04010613 addi a2,sp,64 -8000c86c: 00098593 mv a1,s3 -8000c870: 000a0513 mv a0,s4 -8000c874: 03e12423 sw t5,40(sp) -8000c878: c31ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000c87c: 0a051863 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000c880: 04412703 lw a4,68(sp) -8000c884: 04812783 lw a5,72(sp) -8000c888: 02812f03 lw t5,40(sp) -8000c88c: 05410693 addi a3,sp,84 -8000c890: 00170613 addi a2,a4,1 -8000c894: 00048b93 mv s7,s1 -8000c898: 08000593 li a1,128 -8000c89c: 5abf0663 beq t5,a1,8000ce48 <_vfiprintf_r+0x898> -8000c8a0: 41aa8ab3 sub s5,s5,s10 -8000c8a4: 69504263 bgtz s5,8000cf28 <_vfiprintf_r+0x978> -8000c8a8: 00fd07b3 add a5,s10,a5 -8000c8ac: 008ba023 sw s0,0(s7) -8000c8b0: 01aba223 sw s10,4(s7) -8000c8b4: 04f12423 sw a5,72(sp) -8000c8b8: 04c12223 sw a2,68(sp) -8000c8bc: 00700713 li a4,7 -8000c8c0: 02c75263 bge a4,a2,8000c8e4 <_vfiprintf_r+0x334> -8000c8c4: 0a078ee3 beqz a5,8000d180 <_vfiprintf_r+0xbd0> -8000c8c8: 04010613 addi a2,sp,64 -8000c8cc: 00098593 mv a1,s3 +8000c4ec <_vfiprintf_r>: +8000c4ec: ed010113 addi sp,sp,-304 +8000c4f0: 11312e23 sw s3,284(sp) +8000c4f4: 11412c23 sw s4,280(sp) +8000c4f8: 11712623 sw s7,268(sp) +8000c4fc: 12112623 sw ra,300(sp) +8000c500: 12812423 sw s0,296(sp) +8000c504: 12912223 sw s1,292(sp) +8000c508: 13212023 sw s2,288(sp) +8000c50c: 11512a23 sw s5,276(sp) +8000c510: 11612823 sw s6,272(sp) +8000c514: 11812423 sw s8,264(sp) +8000c518: 11912223 sw s9,260(sp) +8000c51c: 11a12023 sw s10,256(sp) +8000c520: 0fb12e23 sw s11,252(sp) +8000c524: 00d12823 sw a3,16(sp) +8000c528: 00050a13 mv s4,a0 +8000c52c: 00058993 mv s3,a1 +8000c530: 00060b93 mv s7,a2 +8000c534: 00050663 beqz a0,8000c540 <_vfiprintf_r+0x54> +8000c538: 03852783 lw a5,56(a0) +8000c53c: 5e078e63 beqz a5,8000cb38 <_vfiprintf_r+0x64c> +8000c540: 00c99703 lh a4,12(s3) +8000c544: 01071793 slli a5,a4,0x10 +8000c548: 01271693 slli a3,a4,0x12 +8000c54c: 0107d793 srli a5,a5,0x10 +8000c550: 0206ca63 bltz a3,8000c584 <_vfiprintf_r+0x98> +8000c554: 000027b7 lui a5,0x2 +8000c558: 0649a683 lw a3,100(s3) +8000c55c: 00f767b3 or a5,a4,a5 +8000c560: 01079793 slli a5,a5,0x10 +8000c564: ffffe737 lui a4,0xffffe +8000c568: 4107d793 srai a5,a5,0x10 +8000c56c: fff70713 addi a4,a4,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> +8000c570: 00e6f733 and a4,a3,a4 +8000c574: 00f99623 sh a5,12(s3) +8000c578: 01079793 slli a5,a5,0x10 +8000c57c: 06e9a223 sw a4,100(s3) +8000c580: 0107d793 srli a5,a5,0x10 +8000c584: 0087f713 andi a4,a5,8 +8000c588: 40070063 beqz a4,8000c988 <_vfiprintf_r+0x49c> +8000c58c: 0109a703 lw a4,16(s3) +8000c590: 3e070c63 beqz a4,8000c988 <_vfiprintf_r+0x49c> +8000c594: 01a7f793 andi a5,a5,26 +8000c598: 00a00713 li a4,10 +8000c59c: 40e78663 beq a5,a4,8000c9a8 <_vfiprintf_r+0x4bc> +8000c5a0: 800157b7 lui a5,0x80015 +8000c5a4: 29478793 addi a5,a5,660 # 80015294 <__BSS_END__+0xffffe658> +8000c5a8: 80015b37 lui s6,0x80015 +8000c5ac: 04c10493 addi s1,sp,76 +8000c5b0: 00f12a23 sw a5,20(sp) +8000c5b4: 80015937 lui s2,0x80015 +8000c5b8: 400b0793 addi a5,s6,1024 # 80015400 <__BSS_END__+0xffffe7c4> +8000c5bc: 000b8c13 mv s8,s7 +8000c5c0: 04912023 sw s1,64(sp) +8000c5c4: 04012423 sw zero,72(sp) +8000c5c8: 04012223 sw zero,68(sp) +8000c5cc: 00012c23 sw zero,24(sp) +8000c5d0: 00012e23 sw zero,28(sp) +8000c5d4: 02012223 sw zero,36(sp) +8000c5d8: 02012023 sw zero,32(sp) +8000c5dc: 00012623 sw zero,12(sp) +8000c5e0: 00f12423 sw a5,8(sp) +8000c5e4: 41090913 addi s2,s2,1040 # 80015410 <__BSS_END__+0xffffe7d4> +8000c5e8: 00048b93 mv s7,s1 +8000c5ec: 000c4783 lbu a5,0(s8) +8000c5f0: 26078863 beqz a5,8000c860 <_vfiprintf_r+0x374> +8000c5f4: 000c0413 mv s0,s8 +8000c5f8: 02500713 li a4,37 +8000c5fc: 42e78e63 beq a5,a4,8000ca38 <_vfiprintf_r+0x54c> +8000c600: 00144783 lbu a5,1(s0) +8000c604: 00140413 addi s0,s0,1 +8000c608: fe079ae3 bnez a5,8000c5fc <_vfiprintf_r+0x110> +8000c60c: 41840cb3 sub s9,s0,s8 +8000c610: 25840863 beq s0,s8,8000c860 <_vfiprintf_r+0x374> +8000c614: 04812703 lw a4,72(sp) +8000c618: 04412783 lw a5,68(sp) +8000c61c: 018ba023 sw s8,0(s7) +8000c620: 00ec8733 add a4,s9,a4 +8000c624: 00178793 addi a5,a5,1 +8000c628: 019ba223 sw s9,4(s7) +8000c62c: 04e12423 sw a4,72(sp) +8000c630: 04f12223 sw a5,68(sp) +8000c634: 00700693 li a3,7 +8000c638: 008b8b93 addi s7,s7,8 +8000c63c: 02f6d063 bge a3,a5,8000c65c <_vfiprintf_r+0x170> +8000c640: 3a070ae3 beqz a4,8000d1f4 <_vfiprintf_r+0xd08> +8000c644: 04010613 addi a2,sp,64 +8000c648: 00098593 mv a1,s3 +8000c64c: 000a0513 mv a0,s4 +8000c650: d95ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000c654: 20051a63 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000c658: 00048b93 mv s7,s1 +8000c65c: 00c12703 lw a4,12(sp) +8000c660: 00044783 lbu a5,0(s0) +8000c664: 01970733 add a4,a4,s9 +8000c668: 00e12623 sw a4,12(sp) +8000c66c: 1e078a63 beqz a5,8000c860 <_vfiprintf_r+0x374> +8000c670: 00144703 lbu a4,1(s0) +8000c674: 00140c13 addi s8,s0,1 +8000c678: 02010da3 sb zero,59(sp) +8000c67c: fff00a93 li s5,-1 +8000c680: 00012223 sw zero,4(sp) +8000c684: 00000b13 li s6,0 +8000c688: 05a00c93 li s9,90 +8000c68c: 00900d13 li s10,9 +8000c690: 02a00613 li a2,42 +8000c694: 001c0c13 addi s8,s8,1 +8000c698: fe070793 addi a5,a4,-32 +8000c69c: 04fce863 bltu s9,a5,8000c6ec <_vfiprintf_r+0x200> +8000c6a0: 01412683 lw a3,20(sp) +8000c6a4: 00279793 slli a5,a5,0x2 +8000c6a8: 00d787b3 add a5,a5,a3 +8000c6ac: 0007a783 lw a5,0(a5) +8000c6b0: 00078067 jr a5 +8000c6b4: 00012223 sw zero,4(sp) +8000c6b8: fd070793 addi a5,a4,-48 +8000c6bc: 00412583 lw a1,4(sp) +8000c6c0: 000c4703 lbu a4,0(s8) +8000c6c4: 001c0c13 addi s8,s8,1 +8000c6c8: 00259693 slli a3,a1,0x2 +8000c6cc: 00b686b3 add a3,a3,a1 +8000c6d0: 00169693 slli a3,a3,0x1 +8000c6d4: 00d787b3 add a5,a5,a3 +8000c6d8: 00f12223 sw a5,4(sp) +8000c6dc: fd070793 addi a5,a4,-48 +8000c6e0: fcfd7ee3 bgeu s10,a5,8000c6bc <_vfiprintf_r+0x1d0> +8000c6e4: fe070793 addi a5,a4,-32 +8000c6e8: fafcfce3 bgeu s9,a5,8000c6a0 <_vfiprintf_r+0x1b4> +8000c6ec: 16070a63 beqz a4,8000c860 <_vfiprintf_r+0x374> +8000c6f0: 08e10623 sb a4,140(sp) +8000c6f4: 02010da3 sb zero,59(sp) +8000c6f8: 00100c93 li s9,1 +8000c6fc: 00100d13 li s10,1 +8000c700: 08c10413 addi s0,sp,140 +8000c704: 00000a93 li s5,0 +8000c708: 002b7f93 andi t6,s6,2 +8000c70c: 000f8463 beqz t6,8000c714 <_vfiprintf_r+0x228> +8000c710: 002c8c93 addi s9,s9,2 +8000c714: 04412703 lw a4,68(sp) +8000c718: 084b7f13 andi t5,s6,132 +8000c71c: 04812783 lw a5,72(sp) +8000c720: 00170693 addi a3,a4,1 +8000c724: 00068613 mv a2,a3 +8000c728: 000f1863 bnez t5,8000c738 <_vfiprintf_r+0x24c> +8000c72c: 00412583 lw a1,4(sp) +8000c730: 41958db3 sub s11,a1,s9 +8000c734: 09b042e3 bgtz s11,8000cfb8 <_vfiprintf_r+0xacc> +8000c738: 03b14583 lbu a1,59(sp) +8000c73c: 008b8693 addi a3,s7,8 +8000c740: 02058c63 beqz a1,8000c778 <_vfiprintf_r+0x28c> +8000c744: 03b10713 addi a4,sp,59 +8000c748: 00178793 addi a5,a5,1 +8000c74c: 00eba023 sw a4,0(s7) +8000c750: 00100713 li a4,1 +8000c754: 00eba223 sw a4,4(s7) +8000c758: 04f12423 sw a5,72(sp) +8000c75c: 04c12223 sw a2,68(sp) +8000c760: 00700713 li a4,7 +8000c764: 7ec74063 blt a4,a2,8000cf44 <_vfiprintf_r+0xa58> +8000c768: 00060713 mv a4,a2 +8000c76c: 00068b93 mv s7,a3 +8000c770: 00160613 addi a2,a2,1 +8000c774: 00868693 addi a3,a3,8 +8000c778: 040f8e63 beqz t6,8000c7d4 <_vfiprintf_r+0x2e8> +8000c77c: 03c10713 addi a4,sp,60 +8000c780: 00278793 addi a5,a5,2 +8000c784: 00eba023 sw a4,0(s7) +8000c788: 00200713 li a4,2 +8000c78c: 00eba223 sw a4,4(s7) +8000c790: 04f12423 sw a5,72(sp) +8000c794: 04c12223 sw a2,68(sp) +8000c798: 00700713 li a4,7 +8000c79c: 00c750e3 bge a4,a2,8000cf9c <_vfiprintf_r+0xab0> +8000c7a0: 2a0784e3 beqz a5,8000d248 <_vfiprintf_r+0xd5c> +8000c7a4: 04010613 addi a2,sp,64 +8000c7a8: 00098593 mv a1,s3 +8000c7ac: 000a0513 mv a0,s4 +8000c7b0: 03e12423 sw t5,40(sp) +8000c7b4: c31ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000c7b8: 0a051863 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000c7bc: 04412703 lw a4,68(sp) +8000c7c0: 04812783 lw a5,72(sp) +8000c7c4: 02812f03 lw t5,40(sp) +8000c7c8: 05410693 addi a3,sp,84 +8000c7cc: 00170613 addi a2,a4,1 +8000c7d0: 00048b93 mv s7,s1 +8000c7d4: 08000593 li a1,128 +8000c7d8: 5abf0663 beq t5,a1,8000cd84 <_vfiprintf_r+0x898> +8000c7dc: 41aa8ab3 sub s5,s5,s10 +8000c7e0: 69504263 bgtz s5,8000ce64 <_vfiprintf_r+0x978> +8000c7e4: 00fd07b3 add a5,s10,a5 +8000c7e8: 008ba023 sw s0,0(s7) +8000c7ec: 01aba223 sw s10,4(s7) +8000c7f0: 04f12423 sw a5,72(sp) +8000c7f4: 04c12223 sw a2,68(sp) +8000c7f8: 00700713 li a4,7 +8000c7fc: 02c75263 bge a4,a2,8000c820 <_vfiprintf_r+0x334> +8000c800: 0a078ee3 beqz a5,8000d0bc <_vfiprintf_r+0xbd0> +8000c804: 04010613 addi a2,sp,64 +8000c808: 00098593 mv a1,s3 +8000c80c: 000a0513 mv a0,s4 +8000c810: bd5ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000c814: 04051a63 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000c818: 04812783 lw a5,72(sp) +8000c81c: 00048693 mv a3,s1 +8000c820: 004b7313 andi t1,s6,4 +8000c824: 00030863 beqz t1,8000c834 <_vfiprintf_r+0x348> +8000c828: 00412703 lw a4,4(sp) +8000c82c: 41970bb3 sub s7,a4,s9 +8000c830: 0b7044e3 bgtz s7,8000d0d8 <_vfiprintf_r+0xbec> +8000c834: 00412403 lw s0,4(sp) +8000c838: 01945463 bge s0,s9,8000c840 <_vfiprintf_r+0x354> +8000c83c: 000c8413 mv s0,s9 +8000c840: 00c12703 lw a4,12(sp) +8000c844: 00870733 add a4,a4,s0 +8000c848: 00e12623 sw a4,12(sp) +8000c84c: 6c079863 bnez a5,8000cf1c <_vfiprintf_r+0xa30> +8000c850: 000c4783 lbu a5,0(s8) +8000c854: 04012223 sw zero,68(sp) +8000c858: 00048b93 mv s7,s1 +8000c85c: d8079ce3 bnez a5,8000c5f4 <_vfiprintf_r+0x108> +8000c860: 04812783 lw a5,72(sp) +8000c864: 64079ae3 bnez a5,8000d6b8 <_vfiprintf_r+0x11cc> +8000c868: 00c9d783 lhu a5,12(s3) +8000c86c: 0407f793 andi a5,a5,64 +8000c870: 680792e3 bnez a5,8000d6f4 <_vfiprintf_r+0x1208> +8000c874: 12c12083 lw ra,300(sp) +8000c878: 12812403 lw s0,296(sp) +8000c87c: 00c12503 lw a0,12(sp) +8000c880: 12412483 lw s1,292(sp) +8000c884: 12012903 lw s2,288(sp) +8000c888: 11c12983 lw s3,284(sp) +8000c88c: 11812a03 lw s4,280(sp) +8000c890: 11412a83 lw s5,276(sp) +8000c894: 11012b03 lw s6,272(sp) +8000c898: 10c12b83 lw s7,268(sp) +8000c89c: 10812c03 lw s8,264(sp) +8000c8a0: 10412c83 lw s9,260(sp) +8000c8a4: 10012d03 lw s10,256(sp) +8000c8a8: 0fc12d83 lw s11,252(sp) +8000c8ac: 13010113 addi sp,sp,304 +8000c8b0: 00008067 ret +8000c8b4: 000a0513 mv a0,s4 +8000c8b8: 82cfb0ef jal ra,800078e4 <_localeconv_r> +8000c8bc: 00452783 lw a5,4(a0) +8000c8c0: 00078513 mv a0,a5 +8000c8c4: 02f12023 sw a5,32(sp) +8000c8c8: fd5fc0ef jal ra,8000989c +8000c8cc: 00050793 mv a5,a0 8000c8d0: 000a0513 mv a0,s4 -8000c8d4: bd5ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000c8d8: 04051a63 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000c8dc: 04812783 lw a5,72(sp) -8000c8e0: 00048693 mv a3,s1 -8000c8e4: 004b7313 andi t1,s6,4 -8000c8e8: 00030863 beqz t1,8000c8f8 <_vfiprintf_r+0x348> -8000c8ec: 00412703 lw a4,4(sp) -8000c8f0: 41970bb3 sub s7,a4,s9 -8000c8f4: 0b7044e3 bgtz s7,8000d19c <_vfiprintf_r+0xbec> -8000c8f8: 00412403 lw s0,4(sp) -8000c8fc: 01945463 bge s0,s9,8000c904 <_vfiprintf_r+0x354> -8000c900: 000c8413 mv s0,s9 -8000c904: 00c12703 lw a4,12(sp) -8000c908: 00870733 add a4,a4,s0 -8000c90c: 00e12623 sw a4,12(sp) -8000c910: 6c079863 bnez a5,8000cfe0 <_vfiprintf_r+0xa30> -8000c914: 000c4783 lbu a5,0(s8) -8000c918: 04012223 sw zero,68(sp) -8000c91c: 00048b93 mv s7,s1 -8000c920: d8079ce3 bnez a5,8000c6b8 <_vfiprintf_r+0x108> -8000c924: 04812783 lw a5,72(sp) -8000c928: 64079ae3 bnez a5,8000d77c <_vfiprintf_r+0x11cc> -8000c92c: 00c9d783 lhu a5,12(s3) -8000c930: 0407f793 andi a5,a5,64 -8000c934: 680792e3 bnez a5,8000d7b8 <_vfiprintf_r+0x1208> -8000c938: 12c12083 lw ra,300(sp) -8000c93c: 12812403 lw s0,296(sp) -8000c940: 00c12503 lw a0,12(sp) -8000c944: 12412483 lw s1,292(sp) -8000c948: 12012903 lw s2,288(sp) -8000c94c: 11c12983 lw s3,284(sp) -8000c950: 11812a03 lw s4,280(sp) -8000c954: 11412a83 lw s5,276(sp) -8000c958: 11012b03 lw s6,272(sp) -8000c95c: 10c12b83 lw s7,268(sp) -8000c960: 10812c03 lw s8,264(sp) -8000c964: 10412c83 lw s9,260(sp) -8000c968: 10012d03 lw s10,256(sp) -8000c96c: 0fc12d83 lw s11,252(sp) -8000c970: 13010113 addi sp,sp,304 -8000c974: 00008067 ret -8000c978: 000a0513 mv a0,s4 -8000c97c: 82cfb0ef jal ra,800079a8 <_localeconv_r> -8000c980: 00452783 lw a5,4(a0) -8000c984: 00078513 mv a0,a5 -8000c988: 02f12023 sw a5,32(sp) -8000c98c: fd5fc0ef jal ra,80009960 -8000c990: 00050793 mv a5,a0 -8000c994: 000a0513 mv a0,s4 -8000c998: 00078413 mv s0,a5 -8000c99c: 02f12223 sw a5,36(sp) -8000c9a0: 808fb0ef jal ra,800079a8 <_localeconv_r> -8000c9a4: 00852783 lw a5,8(a0) -8000c9a8: 02a00613 li a2,42 -8000c9ac: 00f12e23 sw a5,28(sp) -8000c9b0: 2a0418e3 bnez s0,8000d460 <_vfiprintf_r+0xeb0> -8000c9b4: 000c4703 lbu a4,0(s8) -8000c9b8: da1ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000c9bc: 000c4703 lbu a4,0(s8) -8000c9c0: 020b6b13 ori s6,s6,32 -8000c9c4: d95ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000c9c8: 010b6b13 ori s6,s6,16 -8000c9cc: 020b7793 andi a5,s6,32 -8000c9d0: 16078463 beqz a5,8000cb38 <_vfiprintf_r+0x588> -8000c9d4: 01012783 lw a5,16(sp) -8000c9d8: 00778793 addi a5,a5,7 -8000c9dc: ff87f793 andi a5,a5,-8 -8000c9e0: 0047a703 lw a4,4(a5) +8000c8d4: 00078413 mv s0,a5 +8000c8d8: 02f12223 sw a5,36(sp) +8000c8dc: 808fb0ef jal ra,800078e4 <_localeconv_r> +8000c8e0: 00852783 lw a5,8(a0) +8000c8e4: 02a00613 li a2,42 +8000c8e8: 00f12e23 sw a5,28(sp) +8000c8ec: 2a0418e3 bnez s0,8000d39c <_vfiprintf_r+0xeb0> +8000c8f0: 000c4703 lbu a4,0(s8) +8000c8f4: da1ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000c8f8: 000c4703 lbu a4,0(s8) +8000c8fc: 020b6b13 ori s6,s6,32 +8000c900: d95ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000c904: 010b6b13 ori s6,s6,16 +8000c908: 020b7793 andi a5,s6,32 +8000c90c: 16078463 beqz a5,8000ca74 <_vfiprintf_r+0x588> +8000c910: 01012783 lw a5,16(sp) +8000c914: 00778793 addi a5,a5,7 +8000c918: ff87f793 andi a5,a5,-8 +8000c91c: 0047a703 lw a4,4(a5) +8000c920: 0007ad03 lw s10,0(a5) +8000c924: 00878793 addi a5,a5,8 +8000c928: 00f12823 sw a5,16(sp) +8000c92c: 00070c93 mv s9,a4 +8000c930: 16074a63 bltz a4,8000caa4 <_vfiprintf_r+0x5b8> +8000c934: fff00713 li a4,-1 +8000c938: 000b0d93 mv s11,s6 +8000c93c: 00ea8863 beq s5,a4,8000c94c <_vfiprintf_r+0x460> +8000c940: 019d6733 or a4,s10,s9 +8000c944: f7fb7d93 andi s11,s6,-129 +8000c948: 0a070ce3 beqz a4,8000d200 <_vfiprintf_r+0xd14> +8000c94c: 160c96e3 bnez s9,8000d2b8 <_vfiprintf_r+0xdcc> +8000c950: 00900713 li a4,9 +8000c954: 17a762e3 bltu a4,s10,8000d2b8 <_vfiprintf_r+0xdcc> +8000c958: 030d0793 addi a5,s10,48 +8000c95c: 0ef107a3 sb a5,239(sp) +8000c960: 000d8b13 mv s6,s11 +8000c964: 00100d13 li s10,1 +8000c968: 0ef10413 addi s0,sp,239 +8000c96c: 000a8c93 mv s9,s5 +8000c970: 01aad463 bge s5,s10,8000c978 <_vfiprintf_r+0x48c> +8000c974: 000d0c93 mv s9,s10 +8000c978: 03b14783 lbu a5,59(sp) +8000c97c: 00f037b3 snez a5,a5 +8000c980: 00fc8cb3 add s9,s9,a5 +8000c984: d85ff06f j 8000c708 <_vfiprintf_r+0x21c> +8000c988: 00098593 mv a1,s3 +8000c98c: 000a0513 mv a0,s4 +8000c990: d2cf70ef jal ra,80003ebc <__swsetup_r> +8000c994: 560510e3 bnez a0,8000d6f4 <_vfiprintf_r+0x1208> +8000c998: 00c9d783 lhu a5,12(s3) +8000c99c: 00a00713 li a4,10 +8000c9a0: 01a7f793 andi a5,a5,26 +8000c9a4: bee79ee3 bne a5,a4,8000c5a0 <_vfiprintf_r+0xb4> +8000c9a8: 00e99783 lh a5,14(s3) +8000c9ac: be07cae3 bltz a5,8000c5a0 <_vfiprintf_r+0xb4> +8000c9b0: 01012683 lw a3,16(sp) +8000c9b4: 000b8613 mv a2,s7 +8000c9b8: 00098593 mv a1,s3 +8000c9bc: 000a0513 mv a0,s4 +8000c9c0: 589000ef jal ra,8000d748 <__sbprintf> +8000c9c4: 00a12623 sw a0,12(sp) +8000c9c8: eadff06f j 8000c874 <_vfiprintf_r+0x388> +8000c9cc: 010b6b13 ori s6,s6,16 +8000c9d0: 020b7793 andi a5,s6,32 +8000c9d4: 06078a63 beqz a5,8000ca48 <_vfiprintf_r+0x55c> +8000c9d8: 01012783 lw a5,16(sp) +8000c9dc: 00778793 addi a5,a5,7 +8000c9e0: ff87f793 andi a5,a5,-8 8000c9e4: 0007ad03 lw s10,0(a5) -8000c9e8: 00878793 addi a5,a5,8 -8000c9ec: 00f12823 sw a5,16(sp) -8000c9f0: 00070c93 mv s9,a4 -8000c9f4: 16074a63 bltz a4,8000cb68 <_vfiprintf_r+0x5b8> -8000c9f8: fff00713 li a4,-1 -8000c9fc: 000b0d93 mv s11,s6 -8000ca00: 00ea8863 beq s5,a4,8000ca10 <_vfiprintf_r+0x460> -8000ca04: 019d6733 or a4,s10,s9 -8000ca08: f7fb7d93 andi s11,s6,-129 -8000ca0c: 0a070ce3 beqz a4,8000d2c4 <_vfiprintf_r+0xd14> -8000ca10: 160c96e3 bnez s9,8000d37c <_vfiprintf_r+0xdcc> -8000ca14: 00900713 li a4,9 -8000ca18: 17a762e3 bltu a4,s10,8000d37c <_vfiprintf_r+0xdcc> -8000ca1c: 030d0793 addi a5,s10,48 -8000ca20: 0ef107a3 sb a5,239(sp) -8000ca24: 000d8b13 mv s6,s11 -8000ca28: 00100d13 li s10,1 -8000ca2c: 0ef10413 addi s0,sp,239 -8000ca30: 000a8c93 mv s9,s5 -8000ca34: 01aad463 bge s5,s10,8000ca3c <_vfiprintf_r+0x48c> -8000ca38: 000d0c93 mv s9,s10 -8000ca3c: 03b14783 lbu a5,59(sp) -8000ca40: 00f037b3 snez a5,a5 -8000ca44: 00fc8cb3 add s9,s9,a5 -8000ca48: d85ff06f j 8000c7cc <_vfiprintf_r+0x21c> -8000ca4c: 00098593 mv a1,s3 -8000ca50: 000a0513 mv a0,s4 -8000ca54: d2cf70ef jal ra,80003f80 <__swsetup_r> -8000ca58: 560510e3 bnez a0,8000d7b8 <_vfiprintf_r+0x1208> -8000ca5c: 00c9d783 lhu a5,12(s3) -8000ca60: 00a00713 li a4,10 -8000ca64: 01a7f793 andi a5,a5,26 -8000ca68: bee79ee3 bne a5,a4,8000c664 <_vfiprintf_r+0xb4> -8000ca6c: 00e99783 lh a5,14(s3) -8000ca70: be07cae3 bltz a5,8000c664 <_vfiprintf_r+0xb4> +8000c9e8: 0047ac83 lw s9,4(a5) +8000c9ec: 00878793 addi a5,a5,8 +8000c9f0: 00f12823 sw a5,16(sp) +8000c9f4: bffb7d93 andi s11,s6,-1025 +8000c9f8: 00000713 li a4,0 +8000c9fc: 02010da3 sb zero,59(sp) +8000ca00: fff00693 li a3,-1 +8000ca04: 0cda8463 beq s5,a3,8000cacc <_vfiprintf_r+0x5e0> +8000ca08: 019d66b3 or a3,s10,s9 +8000ca0c: f7fdfb13 andi s6,s11,-129 +8000ca10: 5a069063 bnez a3,8000cfb0 <_vfiprintf_r+0xac4> +8000ca14: 300a9c63 bnez s5,8000cd2c <_vfiprintf_r+0x840> +8000ca18: 7e071863 bnez a4,8000d208 <_vfiprintf_r+0xd1c> +8000ca1c: 001dfd13 andi s10,s11,1 +8000ca20: 0f010413 addi s0,sp,240 +8000ca24: f40d04e3 beqz s10,8000c96c <_vfiprintf_r+0x480> +8000ca28: 03000793 li a5,48 +8000ca2c: 0ef107a3 sb a5,239(sp) +8000ca30: 0ef10413 addi s0,sp,239 +8000ca34: f39ff06f j 8000c96c <_vfiprintf_r+0x480> +8000ca38: 41840cb3 sub s9,s0,s8 +8000ca3c: bd841ce3 bne s0,s8,8000c614 <_vfiprintf_r+0x128> +8000ca40: 00044783 lbu a5,0(s0) +8000ca44: c29ff06f j 8000c66c <_vfiprintf_r+0x180> +8000ca48: 01012683 lw a3,16(sp) +8000ca4c: 010b7793 andi a5,s6,16 +8000ca50: 00468713 addi a4,a3,4 +8000ca54: 16079ce3 bnez a5,8000d3cc <_vfiprintf_r+0xee0> +8000ca58: 040b7793 andi a5,s6,64 +8000ca5c: 380788e3 beqz a5,8000d5ec <_vfiprintf_r+0x1100> +8000ca60: 01012783 lw a5,16(sp) +8000ca64: 00000c93 li s9,0 +8000ca68: 00e12823 sw a4,16(sp) +8000ca6c: 0007dd03 lhu s10,0(a5) +8000ca70: f85ff06f j 8000c9f4 <_vfiprintf_r+0x508> 8000ca74: 01012683 lw a3,16(sp) -8000ca78: 000b8613 mv a2,s7 -8000ca7c: 00098593 mv a1,s3 -8000ca80: 000a0513 mv a0,s4 -8000ca84: 589000ef jal ra,8000d80c <__sbprintf> -8000ca88: 00a12623 sw a0,12(sp) -8000ca8c: eadff06f j 8000c938 <_vfiprintf_r+0x388> -8000ca90: 010b6b13 ori s6,s6,16 -8000ca94: 020b7793 andi a5,s6,32 -8000ca98: 06078a63 beqz a5,8000cb0c <_vfiprintf_r+0x55c> -8000ca9c: 01012783 lw a5,16(sp) -8000caa0: 00778793 addi a5,a5,7 -8000caa4: ff87f793 andi a5,a5,-8 -8000caa8: 0007ad03 lw s10,0(a5) -8000caac: 0047ac83 lw s9,4(a5) -8000cab0: 00878793 addi a5,a5,8 -8000cab4: 00f12823 sw a5,16(sp) -8000cab8: bffb7d93 andi s11,s6,-1025 -8000cabc: 00000713 li a4,0 -8000cac0: 02010da3 sb zero,59(sp) -8000cac4: fff00693 li a3,-1 -8000cac8: 0cda8463 beq s5,a3,8000cb90 <_vfiprintf_r+0x5e0> -8000cacc: 019d66b3 or a3,s10,s9 -8000cad0: f7fdfb13 andi s6,s11,-129 -8000cad4: 5a069063 bnez a3,8000d074 <_vfiprintf_r+0xac4> -8000cad8: 300a9c63 bnez s5,8000cdf0 <_vfiprintf_r+0x840> -8000cadc: 7e071863 bnez a4,8000d2cc <_vfiprintf_r+0xd1c> -8000cae0: 001dfd13 andi s10,s11,1 -8000cae4: 0f010413 addi s0,sp,240 -8000cae8: f40d04e3 beqz s10,8000ca30 <_vfiprintf_r+0x480> -8000caec: 03000793 li a5,48 -8000caf0: 0ef107a3 sb a5,239(sp) -8000caf4: 0ef10413 addi s0,sp,239 -8000caf8: f39ff06f j 8000ca30 <_vfiprintf_r+0x480> -8000cafc: 41840cb3 sub s9,s0,s8 -8000cb00: bd841ce3 bne s0,s8,8000c6d8 <_vfiprintf_r+0x128> -8000cb04: 00044783 lbu a5,0(s0) -8000cb08: c29ff06f j 8000c730 <_vfiprintf_r+0x180> -8000cb0c: 01012683 lw a3,16(sp) -8000cb10: 010b7793 andi a5,s6,16 -8000cb14: 00468713 addi a4,a3,4 -8000cb18: 16079ce3 bnez a5,8000d490 <_vfiprintf_r+0xee0> -8000cb1c: 040b7793 andi a5,s6,64 -8000cb20: 380788e3 beqz a5,8000d6b0 <_vfiprintf_r+0x1100> -8000cb24: 01012783 lw a5,16(sp) -8000cb28: 00000c93 li s9,0 -8000cb2c: 00e12823 sw a4,16(sp) -8000cb30: 0007dd03 lhu s10,0(a5) -8000cb34: f85ff06f j 8000cab8 <_vfiprintf_r+0x508> -8000cb38: 01012683 lw a3,16(sp) -8000cb3c: 010b7793 andi a5,s6,16 -8000cb40: 00468713 addi a4,a3,4 -8000cb44: 100794e3 bnez a5,8000d44c <_vfiprintf_r+0xe9c> -8000cb48: 040b7793 andi a5,s6,64 -8000cb4c: 320782e3 beqz a5,8000d670 <_vfiprintf_r+0x10c0> -8000cb50: 01012783 lw a5,16(sp) -8000cb54: 00e12823 sw a4,16(sp) -8000cb58: 00079d03 lh s10,0(a5) -8000cb5c: 41fd5c93 srai s9,s10,0x1f -8000cb60: 000c8713 mv a4,s9 -8000cb64: e8075ae3 bgez a4,8000c9f8 <_vfiprintf_r+0x448> -8000cb68: 01a03733 snez a4,s10 -8000cb6c: 41900eb3 neg t4,s9 -8000cb70: 40ee8cb3 sub s9,t4,a4 -8000cb74: 02d00713 li a4,45 -8000cb78: 02e10da3 sb a4,59(sp) -8000cb7c: fff00693 li a3,-1 -8000cb80: 41a00d33 neg s10,s10 -8000cb84: 000b0d93 mv s11,s6 -8000cb88: 00100713 li a4,1 -8000cb8c: f4da90e3 bne s5,a3,8000cacc <_vfiprintf_r+0x51c> -8000cb90: 00100693 li a3,1 -8000cb94: e6d70ee3 beq a4,a3,8000ca10 <_vfiprintf_r+0x460> -8000cb98: 00200693 li a3,2 -8000cb9c: 26d70463 beq a4,a3,8000ce04 <_vfiprintf_r+0x854> -8000cba0: 0f010413 addi s0,sp,240 -8000cba4: 01dc9793 slli a5,s9,0x1d -8000cba8: 007d7713 andi a4,s10,7 -8000cbac: 003d5d13 srli s10,s10,0x3 -8000cbb0: 03070713 addi a4,a4,48 -8000cbb4: 01a7ed33 or s10,a5,s10 -8000cbb8: 003cdc93 srli s9,s9,0x3 -8000cbbc: fee40fa3 sb a4,-1(s0) -8000cbc0: 019d67b3 or a5,s10,s9 -8000cbc4: 00040613 mv a2,s0 -8000cbc8: fff40413 addi s0,s0,-1 -8000cbcc: fc079ce3 bnez a5,8000cba4 <_vfiprintf_r+0x5f4> -8000cbd0: 001df793 andi a5,s11,1 -8000cbd4: 26078263 beqz a5,8000ce38 <_vfiprintf_r+0x888> -8000cbd8: 03000793 li a5,48 -8000cbdc: 24f70e63 beq a4,a5,8000ce38 <_vfiprintf_r+0x888> -8000cbe0: ffe60613 addi a2,a2,-2 -8000cbe4: fef40fa3 sb a5,-1(s0) -8000cbe8: 0f010793 addi a5,sp,240 -8000cbec: 40c78d33 sub s10,a5,a2 -8000cbf0: 000d8b13 mv s6,s11 -8000cbf4: 00060413 mv s0,a2 -8000cbf8: e39ff06f j 8000ca30 <_vfiprintf_r+0x480> -8000cbfc: c0df70ef jal ra,80004808 <__sinit> -8000cc00: a05ff06f j 8000c604 <_vfiprintf_r+0x54> -8000cc04: 01012783 lw a5,16(sp) -8000cc08: 02010da3 sb zero,59(sp) -8000cc0c: 0007a403 lw s0,0(a5) -8000cc10: 00478d93 addi s11,a5,4 -8000cc14: 220400e3 beqz s0,8000d634 <_vfiprintf_r+0x1084> -8000cc18: fff00793 li a5,-1 -8000cc1c: 12fa88e3 beq s5,a5,8000d54c <_vfiprintf_r+0xf9c> -8000cc20: 000a8613 mv a2,s5 -8000cc24: 00000593 li a1,0 -8000cc28: 00040513 mv a0,s0 -8000cc2c: f14fb0ef jal ra,80008340 -8000cc30: 360500e3 beqz a0,8000d790 <_vfiprintf_r+0x11e0> -8000cc34: 40850d33 sub s10,a0,s0 -8000cc38: 01b12823 sw s11,16(sp) -8000cc3c: 00000a93 li s5,0 -8000cc40: df1ff06f j 8000ca30 <_vfiprintf_r+0x480> -8000cc44: 01012703 lw a4,16(sp) -8000cc48: 02010da3 sb zero,59(sp) -8000cc4c: 00100c93 li s9,1 -8000cc50: 00072783 lw a5,0(a4) -8000cc54: 00470713 addi a4,a4,4 -8000cc58: 00e12823 sw a4,16(sp) -8000cc5c: 08f10623 sb a5,140(sp) -8000cc60: 00100d13 li s10,1 -8000cc64: 08c10413 addi s0,sp,140 -8000cc68: b61ff06f j 8000c7c8 <_vfiprintf_r+0x218> -8000cc6c: 01012783 lw a5,16(sp) -8000cc70: ffff8737 lui a4,0xffff8 -8000cc74: 83074713 xori a4,a4,-2000 -8000cc78: 0007ad03 lw s10,0(a5) -8000cc7c: 00478793 addi a5,a5,4 -8000cc80: 00f12823 sw a5,16(sp) -8000cc84: 800157b7 lui a5,0x80015 -8000cc88: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -8000cc8c: 02e11e23 sh a4,60(sp) -8000cc90: 00000c93 li s9,0 -8000cc94: 002b6d93 ori s11,s6,2 -8000cc98: 00f12c23 sw a5,24(sp) -8000cc9c: 00200713 li a4,2 -8000cca0: e21ff06f j 8000cac0 <_vfiprintf_r+0x510> +8000ca78: 010b7793 andi a5,s6,16 +8000ca7c: 00468713 addi a4,a3,4 +8000ca80: 100794e3 bnez a5,8000d388 <_vfiprintf_r+0xe9c> +8000ca84: 040b7793 andi a5,s6,64 +8000ca88: 320782e3 beqz a5,8000d5ac <_vfiprintf_r+0x10c0> +8000ca8c: 01012783 lw a5,16(sp) +8000ca90: 00e12823 sw a4,16(sp) +8000ca94: 00079d03 lh s10,0(a5) +8000ca98: 41fd5c93 srai s9,s10,0x1f +8000ca9c: 000c8713 mv a4,s9 +8000caa0: e8075ae3 bgez a4,8000c934 <_vfiprintf_r+0x448> +8000caa4: 01a03733 snez a4,s10 +8000caa8: 41900eb3 neg t4,s9 +8000caac: 40ee8cb3 sub s9,t4,a4 +8000cab0: 02d00713 li a4,45 +8000cab4: 02e10da3 sb a4,59(sp) +8000cab8: fff00693 li a3,-1 +8000cabc: 41a00d33 neg s10,s10 +8000cac0: 000b0d93 mv s11,s6 +8000cac4: 00100713 li a4,1 +8000cac8: f4da90e3 bne s5,a3,8000ca08 <_vfiprintf_r+0x51c> +8000cacc: 00100693 li a3,1 +8000cad0: e6d70ee3 beq a4,a3,8000c94c <_vfiprintf_r+0x460> +8000cad4: 00200693 li a3,2 +8000cad8: 26d70463 beq a4,a3,8000cd40 <_vfiprintf_r+0x854> +8000cadc: 0f010413 addi s0,sp,240 +8000cae0: 01dc9793 slli a5,s9,0x1d +8000cae4: 007d7713 andi a4,s10,7 +8000cae8: 003d5d13 srli s10,s10,0x3 +8000caec: 03070713 addi a4,a4,48 +8000caf0: 01a7ed33 or s10,a5,s10 +8000caf4: 003cdc93 srli s9,s9,0x3 +8000caf8: fee40fa3 sb a4,-1(s0) +8000cafc: 019d67b3 or a5,s10,s9 +8000cb00: 00040613 mv a2,s0 +8000cb04: fff40413 addi s0,s0,-1 +8000cb08: fc079ce3 bnez a5,8000cae0 <_vfiprintf_r+0x5f4> +8000cb0c: 001df793 andi a5,s11,1 +8000cb10: 26078263 beqz a5,8000cd74 <_vfiprintf_r+0x888> +8000cb14: 03000793 li a5,48 +8000cb18: 24f70e63 beq a4,a5,8000cd74 <_vfiprintf_r+0x888> +8000cb1c: ffe60613 addi a2,a2,-2 +8000cb20: fef40fa3 sb a5,-1(s0) +8000cb24: 0f010793 addi a5,sp,240 +8000cb28: 40c78d33 sub s10,a5,a2 +8000cb2c: 000d8b13 mv s6,s11 +8000cb30: 00060413 mv s0,a2 +8000cb34: e39ff06f j 8000c96c <_vfiprintf_r+0x480> +8000cb38: c0df70ef jal ra,80004744 <__sinit> +8000cb3c: a05ff06f j 8000c540 <_vfiprintf_r+0x54> +8000cb40: 01012783 lw a5,16(sp) +8000cb44: 02010da3 sb zero,59(sp) +8000cb48: 0007a403 lw s0,0(a5) +8000cb4c: 00478d93 addi s11,a5,4 +8000cb50: 220400e3 beqz s0,8000d570 <_vfiprintf_r+0x1084> +8000cb54: fff00793 li a5,-1 +8000cb58: 12fa88e3 beq s5,a5,8000d488 <_vfiprintf_r+0xf9c> +8000cb5c: 000a8613 mv a2,s5 +8000cb60: 00000593 li a1,0 +8000cb64: 00040513 mv a0,s0 +8000cb68: f14fb0ef jal ra,8000827c +8000cb6c: 360500e3 beqz a0,8000d6cc <_vfiprintf_r+0x11e0> +8000cb70: 40850d33 sub s10,a0,s0 +8000cb74: 01b12823 sw s11,16(sp) +8000cb78: 00000a93 li s5,0 +8000cb7c: df1ff06f j 8000c96c <_vfiprintf_r+0x480> +8000cb80: 01012703 lw a4,16(sp) +8000cb84: 02010da3 sb zero,59(sp) +8000cb88: 00100c93 li s9,1 +8000cb8c: 00072783 lw a5,0(a4) +8000cb90: 00470713 addi a4,a4,4 +8000cb94: 00e12823 sw a4,16(sp) +8000cb98: 08f10623 sb a5,140(sp) +8000cb9c: 00100d13 li s10,1 +8000cba0: 08c10413 addi s0,sp,140 +8000cba4: b61ff06f j 8000c704 <_vfiprintf_r+0x218> +8000cba8: 01012783 lw a5,16(sp) +8000cbac: ffff8737 lui a4,0xffff8 +8000cbb0: 83074713 xori a4,a4,-2000 +8000cbb4: 0007ad03 lw s10,0(a5) +8000cbb8: 00478793 addi a5,a5,4 +8000cbbc: 00f12823 sw a5,16(sp) +8000cbc0: 800157b7 lui a5,0x80015 +8000cbc4: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +8000cbc8: 02e11e23 sh a4,60(sp) +8000cbcc: 00000c93 li s9,0 +8000cbd0: 002b6d93 ori s11,s6,2 +8000cbd4: 00f12c23 sw a5,24(sp) +8000cbd8: 00200713 li a4,2 +8000cbdc: e21ff06f j 8000c9fc <_vfiprintf_r+0x510> +8000cbe0: 000c4703 lbu a4,0(s8) +8000cbe4: 06c00793 li a5,108 +8000cbe8: 16f706e3 beq a4,a5,8000d554 <_vfiprintf_r+0x1068> +8000cbec: 010b6b13 ori s6,s6,16 +8000cbf0: aa5ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000cbf4: 000c4703 lbu a4,0(s8) +8000cbf8: 06800793 li a5,104 +8000cbfc: 14f704e3 beq a4,a5,8000d544 <_vfiprintf_r+0x1058> +8000cc00: 040b6b13 ori s6,s6,64 +8000cc04: a91ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000cc08: 010b6d93 ori s11,s6,16 +8000cc0c: 020df793 andi a5,s11,32 +8000cc10: 60078463 beqz a5,8000d218 <_vfiprintf_r+0xd2c> +8000cc14: 01012783 lw a5,16(sp) +8000cc18: 00100713 li a4,1 +8000cc1c: 00778793 addi a5,a5,7 +8000cc20: ff87f793 andi a5,a5,-8 +8000cc24: 0007ad03 lw s10,0(a5) +8000cc28: 0047ac83 lw s9,4(a5) +8000cc2c: 00878793 addi a5,a5,8 +8000cc30: 00f12823 sw a5,16(sp) +8000cc34: dc9ff06f j 8000c9fc <_vfiprintf_r+0x510> +8000cc38: 000c4703 lbu a4,0(s8) +8000cc3c: 080b6b13 ori s6,s6,128 +8000cc40: a55ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000cc44: 01012683 lw a3,16(sp) +8000cc48: 000c4703 lbu a4,0(s8) +8000cc4c: 0006a783 lw a5,0(a3) +8000cc50: 00468693 addi a3,a3,4 +8000cc54: 00d12823 sw a3,16(sp) +8000cc58: 00f12223 sw a5,4(sp) +8000cc5c: a207dce3 bgez a5,8000c694 <_vfiprintf_r+0x1a8> +8000cc60: 40f007b3 neg a5,a5 +8000cc64: 00f12223 sw a5,4(sp) +8000cc68: 004b6b13 ori s6,s6,4 +8000cc6c: a29ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000cc70: 000c4703 lbu a4,0(s8) +8000cc74: 001b6b13 ori s6,s6,1 +8000cc78: a1dff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000cc7c: 03b14783 lbu a5,59(sp) +8000cc80: 000c4703 lbu a4,0(s8) +8000cc84: a00798e3 bnez a5,8000c694 <_vfiprintf_r+0x1a8> +8000cc88: 02000793 li a5,32 +8000cc8c: 02f10da3 sb a5,59(sp) +8000cc90: a05ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000cc94: 000c4703 lbu a4,0(s8) +8000cc98: 004b6b13 ori s6,s6,4 +8000cc9c: 9f9ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000cca0: 02b00793 li a5,43 8000cca4: 000c4703 lbu a4,0(s8) -8000cca8: 06c00793 li a5,108 -8000ccac: 16f706e3 beq a4,a5,8000d618 <_vfiprintf_r+0x1068> -8000ccb0: 010b6b13 ori s6,s6,16 -8000ccb4: aa5ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000ccb8: 000c4703 lbu a4,0(s8) -8000ccbc: 06800793 li a5,104 -8000ccc0: 14f704e3 beq a4,a5,8000d608 <_vfiprintf_r+0x1058> -8000ccc4: 040b6b13 ori s6,s6,64 -8000ccc8: a91ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000cccc: 010b6d93 ori s11,s6,16 -8000ccd0: 020df793 andi a5,s11,32 -8000ccd4: 60078463 beqz a5,8000d2dc <_vfiprintf_r+0xd2c> -8000ccd8: 01012783 lw a5,16(sp) -8000ccdc: 00100713 li a4,1 -8000cce0: 00778793 addi a5,a5,7 -8000cce4: ff87f793 andi a5,a5,-8 -8000cce8: 0007ad03 lw s10,0(a5) -8000ccec: 0047ac83 lw s9,4(a5) -8000ccf0: 00878793 addi a5,a5,8 -8000ccf4: 00f12823 sw a5,16(sp) -8000ccf8: dc9ff06f j 8000cac0 <_vfiprintf_r+0x510> -8000ccfc: 000c4703 lbu a4,0(s8) -8000cd00: 080b6b13 ori s6,s6,128 -8000cd04: a55ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000cd08: 01012683 lw a3,16(sp) -8000cd0c: 000c4703 lbu a4,0(s8) -8000cd10: 0006a783 lw a5,0(a3) -8000cd14: 00468693 addi a3,a3,4 -8000cd18: 00d12823 sw a3,16(sp) -8000cd1c: 00f12223 sw a5,4(sp) -8000cd20: a207dce3 bgez a5,8000c758 <_vfiprintf_r+0x1a8> -8000cd24: 40f007b3 neg a5,a5 -8000cd28: 00f12223 sw a5,4(sp) -8000cd2c: 004b6b13 ori s6,s6,4 -8000cd30: a29ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000cd34: 000c4703 lbu a4,0(s8) -8000cd38: 001b6b13 ori s6,s6,1 -8000cd3c: a1dff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000cd40: 03b14783 lbu a5,59(sp) -8000cd44: 000c4703 lbu a4,0(s8) -8000cd48: a00798e3 bnez a5,8000c758 <_vfiprintf_r+0x1a8> -8000cd4c: 02000793 li a5,32 -8000cd50: 02f10da3 sb a5,59(sp) -8000cd54: a05ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000cd58: 000c4703 lbu a4,0(s8) -8000cd5c: 004b6b13 ori s6,s6,4 -8000cd60: 9f9ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000cd64: 02b00793 li a5,43 -8000cd68: 000c4703 lbu a4,0(s8) -8000cd6c: 02f10da3 sb a5,59(sp) -8000cd70: 9e9ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000cd74: 000c4703 lbu a4,0(s8) -8000cd78: 001c0693 addi a3,s8,1 -8000cd7c: 24c70ae3 beq a4,a2,8000d7d0 <_vfiprintf_r+0x1220> -8000cd80: fd070793 addi a5,a4,-48 # ffff7fd0 <__BSS_END__+0x7ffe1394> -8000cd84: 00068c13 mv s8,a3 -8000cd88: 00000a93 li s5,0 -8000cd8c: 9cfd68e3 bltu s10,a5,8000c75c <_vfiprintf_r+0x1ac> -8000cd90: 000c4703 lbu a4,0(s8) -8000cd94: 002a9693 slli a3,s5,0x2 -8000cd98: 01568ab3 add s5,a3,s5 -8000cd9c: 001a9a93 slli s5,s5,0x1 -8000cda0: 00fa8ab3 add s5,s5,a5 -8000cda4: fd070793 addi a5,a4,-48 -8000cda8: 001c0c13 addi s8,s8,1 -8000cdac: fefd72e3 bgeu s10,a5,8000cd90 <_vfiprintf_r+0x7e0> -8000cdb0: 9adff06f j 8000c75c <_vfiprintf_r+0x1ac> -8000cdb4: 01012683 lw a3,16(sp) -8000cdb8: 020b7793 andi a5,s6,32 -8000cdbc: 0006a703 lw a4,0(a3) -8000cdc0: 00468693 addi a3,a3,4 -8000cdc4: 00d12823 sw a3,16(sp) -8000cdc8: 6a079a63 bnez a5,8000d47c <_vfiprintf_r+0xecc> -8000cdcc: 010b7793 andi a5,s6,16 -8000cdd0: 04079ce3 bnez a5,8000d628 <_vfiprintf_r+0x1078> -8000cdd4: 040b7793 andi a5,s6,64 -8000cdd8: 140790e3 bnez a5,8000d718 <_vfiprintf_r+0x1168> -8000cddc: 200b7313 andi t1,s6,512 -8000cde0: 040304e3 beqz t1,8000d628 <_vfiprintf_r+0x1078> -8000cde4: 00c12783 lw a5,12(sp) -8000cde8: 00f70023 sb a5,0(a4) -8000cdec: 8c5ff06f j 8000c6b0 <_vfiprintf_r+0x100> -8000cdf0: 00100693 li a3,1 -8000cdf4: 1ad70ee3 beq a4,a3,8000d7b0 <_vfiprintf_r+0x1200> -8000cdf8: 00200693 li a3,2 -8000cdfc: 000b0d93 mv s11,s6 -8000ce00: dad710e3 bne a4,a3,8000cba0 <_vfiprintf_r+0x5f0> -8000ce04: 01812683 lw a3,24(sp) -8000ce08: 0f010413 addi s0,sp,240 -8000ce0c: 00fd7793 andi a5,s10,15 -8000ce10: 00f687b3 add a5,a3,a5 -8000ce14: 0007c703 lbu a4,0(a5) -8000ce18: 004d5d13 srli s10,s10,0x4 -8000ce1c: 01cc9793 slli a5,s9,0x1c -8000ce20: 01a7ed33 or s10,a5,s10 -8000ce24: 004cdc93 srli s9,s9,0x4 -8000ce28: fee40fa3 sb a4,-1(s0) -8000ce2c: 019d67b3 or a5,s10,s9 -8000ce30: fff40413 addi s0,s0,-1 -8000ce34: fc079ce3 bnez a5,8000ce0c <_vfiprintf_r+0x85c> -8000ce38: 0f010793 addi a5,sp,240 -8000ce3c: 40878d33 sub s10,a5,s0 -8000ce40: 000d8b13 mv s6,s11 -8000ce44: bedff06f j 8000ca30 <_vfiprintf_r+0x480> -8000ce48: 00412583 lw a1,4(sp) -8000ce4c: 41958db3 sub s11,a1,s9 -8000ce50: a5b058e3 blez s11,8000c8a0 <_vfiprintf_r+0x2f0> -8000ce54: 01000593 li a1,16 -8000ce58: 17b5d6e3 bge a1,s11,8000d7c4 <_vfiprintf_r+0x1214> -8000ce5c: 01000e93 li t4,16 -8000ce60: 00700f13 li t5,7 -8000ce64: 0180006f j 8000ce7c <_vfiprintf_r+0x8cc> -8000ce68: 00270613 addi a2,a4,2 -8000ce6c: 008b8b93 addi s7,s7,8 -8000ce70: 00068713 mv a4,a3 -8000ce74: ff0d8d93 addi s11,s11,-16 -8000ce78: 05bedc63 bge t4,s11,8000ced0 <_vfiprintf_r+0x920> -8000ce7c: 01078793 addi a5,a5,16 -8000ce80: 00170693 addi a3,a4,1 -8000ce84: 012ba023 sw s2,0(s7) -8000ce88: 01dba223 sw t4,4(s7) -8000ce8c: 04f12423 sw a5,72(sp) -8000ce90: 04d12223 sw a3,68(sp) -8000ce94: fcdf5ae3 bge t5,a3,8000ce68 <_vfiprintf_r+0x8b8> -8000ce98: 16078063 beqz a5,8000cff8 <_vfiprintf_r+0xa48> -8000ce9c: 04010613 addi a2,sp,64 -8000cea0: 00098593 mv a1,s3 -8000cea4: 000a0513 mv a0,s4 -8000cea8: e00ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000ceac: a80510e3 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000ceb0: 04412703 lw a4,68(sp) -8000ceb4: 01000e93 li t4,16 -8000ceb8: ff0d8d93 addi s11,s11,-16 -8000cebc: 04812783 lw a5,72(sp) -8000cec0: 00048b93 mv s7,s1 -8000cec4: 00170613 addi a2,a4,1 -8000cec8: 00700f13 li t5,7 -8000cecc: fbbec8e3 blt t4,s11,8000ce7c <_vfiprintf_r+0x8cc> -8000ced0: 00060593 mv a1,a2 -8000ced4: 008b8513 addi a0,s7,8 -8000ced8: 01b787b3 add a5,a5,s11 -8000cedc: 012ba023 sw s2,0(s7) -8000cee0: 01bba223 sw s11,4(s7) -8000cee4: 04f12423 sw a5,72(sp) -8000cee8: 04b12223 sw a1,68(sp) -8000ceec: 00700713 li a4,7 -8000cef0: 52b75a63 bge a4,a1,8000d424 <_vfiprintf_r+0xe74> -8000cef4: 7e078663 beqz a5,8000d6e0 <_vfiprintf_r+0x1130> -8000cef8: 04010613 addi a2,sp,64 -8000cefc: 00098593 mv a1,s3 -8000cf00: 000a0513 mv a0,s4 -8000cf04: da4ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000cf08: a20512e3 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000cf0c: 04412703 lw a4,68(sp) -8000cf10: 41aa8ab3 sub s5,s5,s10 -8000cf14: 04812783 lw a5,72(sp) -8000cf18: 05410693 addi a3,sp,84 -8000cf1c: 00170613 addi a2,a4,1 -8000cf20: 00048b93 mv s7,s1 -8000cf24: 995052e3 blez s5,8000c8a8 <_vfiprintf_r+0x2f8> -8000cf28: 01000593 li a1,16 -8000cf2c: 7b55d063 bge a1,s5,8000d6cc <_vfiprintf_r+0x111c> -8000cf30: 01000893 li a7,16 -8000cf34: 00700d93 li s11,7 -8000cf38: 0180006f j 8000cf50 <_vfiprintf_r+0x9a0> -8000cf3c: 00270613 addi a2,a4,2 -8000cf40: 008b8b93 addi s7,s7,8 -8000cf44: 00068713 mv a4,a3 -8000cf48: ff0a8a93 addi s5,s5,-16 -8000cf4c: 0558da63 bge a7,s5,8000cfa0 <_vfiprintf_r+0x9f0> -8000cf50: 01078793 addi a5,a5,16 -8000cf54: 00170693 addi a3,a4,1 -8000cf58: 012ba023 sw s2,0(s7) -8000cf5c: 011ba223 sw a7,4(s7) -8000cf60: 04f12423 sw a5,72(sp) -8000cf64: 04d12223 sw a3,68(sp) -8000cf68: fcdddae3 bge s11,a3,8000cf3c <_vfiprintf_r+0x98c> -8000cf6c: 06078263 beqz a5,8000cfd0 <_vfiprintf_r+0xa20> -8000cf70: 04010613 addi a2,sp,64 -8000cf74: 00098593 mv a1,s3 -8000cf78: 000a0513 mv a0,s4 -8000cf7c: d2cff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000cf80: 9a0516e3 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000cf84: 04412703 lw a4,68(sp) -8000cf88: 01000893 li a7,16 -8000cf8c: ff0a8a93 addi s5,s5,-16 -8000cf90: 04812783 lw a5,72(sp) -8000cf94: 00048b93 mv s7,s1 -8000cf98: 00170613 addi a2,a4,1 -8000cf9c: fb58cae3 blt a7,s5,8000cf50 <_vfiprintf_r+0x9a0> -8000cfa0: 008b8593 addi a1,s7,8 -8000cfa4: 015787b3 add a5,a5,s5 -8000cfa8: 012ba023 sw s2,0(s7) -8000cfac: 015ba223 sw s5,4(s7) -8000cfb0: 04f12423 sw a5,72(sp) -8000cfb4: 04c12223 sw a2,68(sp) -8000cfb8: 00700713 li a4,7 -8000cfbc: 2cc74663 blt a4,a2,8000d288 <_vfiprintf_r+0xcd8> -8000cfc0: 00160613 addi a2,a2,1 -8000cfc4: 00858693 addi a3,a1,8 -8000cfc8: 00058b93 mv s7,a1 -8000cfcc: 8ddff06f j 8000c8a8 <_vfiprintf_r+0x2f8> -8000cfd0: 00100613 li a2,1 -8000cfd4: 00000713 li a4,0 -8000cfd8: 00048b93 mv s7,s1 -8000cfdc: f6dff06f j 8000cf48 <_vfiprintf_r+0x998> -8000cfe0: 04010613 addi a2,sp,64 -8000cfe4: 00098593 mv a1,s3 -8000cfe8: 000a0513 mv a0,s4 -8000cfec: cbcff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000cff0: 920502e3 beqz a0,8000c914 <_vfiprintf_r+0x364> -8000cff4: 939ff06f j 8000c92c <_vfiprintf_r+0x37c> -8000cff8: 00100613 li a2,1 -8000cffc: 00000713 li a4,0 -8000d000: 00048b93 mv s7,s1 -8000d004: e71ff06f j 8000ce74 <_vfiprintf_r+0x8c4> -8000d008: 30078c63 beqz a5,8000d320 <_vfiprintf_r+0xd70> -8000d00c: 04010613 addi a2,sp,64 -8000d010: 00098593 mv a1,s3 -8000d014: 000a0513 mv a0,s4 -8000d018: 03e12623 sw t5,44(sp) -8000d01c: 03f12423 sw t6,40(sp) -8000d020: c88ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000d024: 900514e3 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000d028: 04412703 lw a4,68(sp) -8000d02c: 04812783 lw a5,72(sp) -8000d030: 02c12f03 lw t5,44(sp) -8000d034: 02812f83 lw t6,40(sp) -8000d038: 05410693 addi a3,sp,84 -8000d03c: 00170613 addi a2,a4,1 -8000d040: 00048b93 mv s7,s1 -8000d044: ff8ff06f j 8000c83c <_vfiprintf_r+0x28c> -8000d048: 03c10793 addi a5,sp,60 -8000d04c: 04f12623 sw a5,76(sp) -8000d050: 00200793 li a5,2 -8000d054: 04f12823 sw a5,80(sp) -8000d058: 00100613 li a2,1 -8000d05c: 05410693 addi a3,sp,84 -8000d060: 00060713 mv a4,a2 -8000d064: 00068b93 mv s7,a3 -8000d068: 00170613 addi a2,a4,1 -8000d06c: 008b8693 addi a3,s7,8 -8000d070: 829ff06f j 8000c898 <_vfiprintf_r+0x2e8> -8000d074: 000b0d93 mv s11,s6 -8000d078: b19ff06f j 8000cb90 <_vfiprintf_r+0x5e0> -8000d07c: 01000613 li a2,16 -8000d080: 73b65063 bge a2,s11,8000d7a0 <_vfiprintf_r+0x11f0> -8000d084: 000b8613 mv a2,s7 -8000d088: 01000e93 li t4,16 -8000d08c: 00040b93 mv s7,s0 -8000d090: 00700293 li t0,7 -8000d094: 00098413 mv s0,s3 -8000d098: 03f12423 sw t6,40(sp) -8000d09c: 000d8993 mv s3,s11 -8000d0a0: 000c0d93 mv s11,s8 -8000d0a4: 000a8c13 mv s8,s5 -8000d0a8: 000f0a93 mv s5,t5 -8000d0ac: 01c0006f j 8000d0c8 <_vfiprintf_r+0xb18> -8000d0b0: 00270513 addi a0,a4,2 -8000d0b4: 00860613 addi a2,a2,8 -8000d0b8: 00068713 mv a4,a3 -8000d0bc: ff098993 addi s3,s3,-16 -8000d0c0: 053ede63 bge t4,s3,8000d11c <_vfiprintf_r+0xb6c> -8000d0c4: 00170693 addi a3,a4,1 -8000d0c8: 00812583 lw a1,8(sp) -8000d0cc: 01078793 addi a5,a5,16 -8000d0d0: 01d62223 sw t4,4(a2) -8000d0d4: 00b62023 sw a1,0(a2) -8000d0d8: 04f12423 sw a5,72(sp) -8000d0dc: 04d12223 sw a3,68(sp) -8000d0e0: fcd2d8e3 bge t0,a3,8000d0b0 <_vfiprintf_r+0xb00> -8000d0e4: 08078663 beqz a5,8000d170 <_vfiprintf_r+0xbc0> -8000d0e8: 04010613 addi a2,sp,64 -8000d0ec: 00040593 mv a1,s0 -8000d0f0: 000a0513 mv a0,s4 -8000d0f4: bb4ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000d0f8: 4c051663 bnez a0,8000d5c4 <_vfiprintf_r+0x1014> -8000d0fc: 04412703 lw a4,68(sp) -8000d100: 01000e93 li t4,16 -8000d104: ff098993 addi s3,s3,-16 -8000d108: 04812783 lw a5,72(sp) -8000d10c: 00048613 mv a2,s1 -8000d110: 00170513 addi a0,a4,1 -8000d114: 00700293 li t0,7 -8000d118: fb3ec6e3 blt t4,s3,8000d0c4 <_vfiprintf_r+0xb14> -8000d11c: 02812f83 lw t6,40(sp) -8000d120: 000a8f13 mv t5,s5 -8000d124: 00050593 mv a1,a0 -8000d128: 000c0a93 mv s5,s8 -8000d12c: 000d8c13 mv s8,s11 -8000d130: 00098d93 mv s11,s3 -8000d134: 00040993 mv s3,s0 -8000d138: 000b8413 mv s0,s7 -8000d13c: 00060b93 mv s7,a2 -8000d140: 00812703 lw a4,8(sp) -8000d144: 01b787b3 add a5,a5,s11 -8000d148: 01bba223 sw s11,4(s7) -8000d14c: 00eba023 sw a4,0(s7) -8000d150: 04f12423 sw a5,72(sp) -8000d154: 04b12223 sw a1,68(sp) -8000d158: 00700713 li a4,7 -8000d15c: 1eb74263 blt a4,a1,8000d340 <_vfiprintf_r+0xd90> -8000d160: 008b8b93 addi s7,s7,8 -8000d164: 00158613 addi a2,a1,1 -8000d168: 00058713 mv a4,a1 -8000d16c: e90ff06f j 8000c7fc <_vfiprintf_r+0x24c> -8000d170: 00000713 li a4,0 -8000d174: 00100513 li a0,1 -8000d178: 00048613 mv a2,s1 -8000d17c: f41ff06f j 8000d0bc <_vfiprintf_r+0xb0c> -8000d180: 04012223 sw zero,68(sp) -8000d184: 004b7313 andi t1,s6,4 -8000d188: 0e030263 beqz t1,8000d26c <_vfiprintf_r+0xcbc> -8000d18c: 00412703 lw a4,4(sp) -8000d190: 41970bb3 sub s7,a4,s9 -8000d194: 0d705c63 blez s7,8000d26c <_vfiprintf_r+0xcbc> -8000d198: 00048693 mv a3,s1 -8000d19c: 01000713 li a4,16 -8000d1a0: 04412603 lw a2,68(sp) -8000d1a4: 61775263 bge a4,s7,8000d7a8 <_vfiprintf_r+0x11f8> -8000d1a8: 01000d13 li s10,16 -8000d1ac: 00700d93 li s11,7 -8000d1b0: 0180006f j 8000d1c8 <_vfiprintf_r+0xc18> -8000d1b4: 00260513 addi a0,a2,2 -8000d1b8: 00868693 addi a3,a3,8 -8000d1bc: 00070613 mv a2,a4 -8000d1c0: ff0b8b93 addi s7,s7,-16 -8000d1c4: 057d5a63 bge s10,s7,8000d218 <_vfiprintf_r+0xc68> -8000d1c8: 00812583 lw a1,8(sp) -8000d1cc: 01078793 addi a5,a5,16 -8000d1d0: 00160713 addi a4,a2,1 -8000d1d4: 00b6a023 sw a1,0(a3) -8000d1d8: 01a6a223 sw s10,4(a3) -8000d1dc: 04f12423 sw a5,72(sp) -8000d1e0: 04e12223 sw a4,68(sp) -8000d1e4: fcedd8e3 bge s11,a4,8000d1b4 <_vfiprintf_r+0xc04> -8000d1e8: 06078a63 beqz a5,8000d25c <_vfiprintf_r+0xcac> -8000d1ec: 04010613 addi a2,sp,64 -8000d1f0: 00098593 mv a1,s3 -8000d1f4: 000a0513 mv a0,s4 -8000d1f8: ab0ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000d1fc: f2051863 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000d200: 04412603 lw a2,68(sp) -8000d204: ff0b8b93 addi s7,s7,-16 -8000d208: 04812783 lw a5,72(sp) -8000d20c: 00048693 mv a3,s1 -8000d210: 00160513 addi a0,a2,1 -8000d214: fb7d4ae3 blt s10,s7,8000d1c8 <_vfiprintf_r+0xc18> -8000d218: 00050593 mv a1,a0 -8000d21c: 00812703 lw a4,8(sp) -8000d220: 017787b3 add a5,a5,s7 -8000d224: 0176a223 sw s7,4(a3) -8000d228: 00e6a023 sw a4,0(a3) -8000d22c: 04f12423 sw a5,72(sp) -8000d230: 04b12223 sw a1,68(sp) -8000d234: 00700713 li a4,7 -8000d238: ecb75063 bge a4,a1,8000c8f8 <_vfiprintf_r+0x348> -8000d23c: 02078863 beqz a5,8000d26c <_vfiprintf_r+0xcbc> -8000d240: 04010613 addi a2,sp,64 -8000d244: 00098593 mv a1,s3 -8000d248: 000a0513 mv a0,s4 -8000d24c: a5cff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000d250: ec051e63 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000d254: 04812783 lw a5,72(sp) -8000d258: ea0ff06f j 8000c8f8 <_vfiprintf_r+0x348> -8000d25c: 00100513 li a0,1 -8000d260: 00000613 li a2,0 -8000d264: 00048693 mv a3,s1 -8000d268: f59ff06f j 8000d1c0 <_vfiprintf_r+0xc10> -8000d26c: 00412403 lw s0,4(sp) -8000d270: 01945463 bge s0,s9,8000d278 <_vfiprintf_r+0xcc8> -8000d274: 000c8413 mv s0,s9 -8000d278: 00c12783 lw a5,12(sp) -8000d27c: 008787b3 add a5,a5,s0 -8000d280: 00f12623 sw a5,12(sp) -8000d284: e90ff06f j 8000c914 <_vfiprintf_r+0x364> -8000d288: 34078263 beqz a5,8000d5cc <_vfiprintf_r+0x101c> -8000d28c: 04010613 addi a2,sp,64 -8000d290: 00098593 mv a1,s3 -8000d294: 000a0513 mv a0,s4 -8000d298: a10ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000d29c: e8051863 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000d2a0: 04412603 lw a2,68(sp) -8000d2a4: 04812783 lw a5,72(sp) -8000d2a8: 05410693 addi a3,sp,84 -8000d2ac: 00160613 addi a2,a2,1 -8000d2b0: 00048b93 mv s7,s1 -8000d2b4: df4ff06f j 8000c8a8 <_vfiprintf_r+0x2f8> -8000d2b8: 04012223 sw zero,68(sp) -8000d2bc: 00048b93 mv s7,s1 -8000d2c0: c60ff06f j 8000c720 <_vfiprintf_r+0x170> -8000d2c4: f40a9c63 bnez s5,8000ca1c <_vfiprintf_r+0x46c> -8000d2c8: 000d8b13 mv s6,s11 -8000d2cc: 00000a93 li s5,0 -8000d2d0: 00000d13 li s10,0 +8000cca8: 02f10da3 sb a5,59(sp) +8000ccac: 9e9ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000ccb0: 000c4703 lbu a4,0(s8) +8000ccb4: 001c0693 addi a3,s8,1 +8000ccb8: 24c70ae3 beq a4,a2,8000d70c <_vfiprintf_r+0x1220> +8000ccbc: fd070793 addi a5,a4,-48 # ffff7fd0 <__BSS_END__+0x7ffe1394> +8000ccc0: 00068c13 mv s8,a3 +8000ccc4: 00000a93 li s5,0 +8000ccc8: 9cfd68e3 bltu s10,a5,8000c698 <_vfiprintf_r+0x1ac> +8000cccc: 000c4703 lbu a4,0(s8) +8000ccd0: 002a9693 slli a3,s5,0x2 +8000ccd4: 01568ab3 add s5,a3,s5 +8000ccd8: 001a9a93 slli s5,s5,0x1 +8000ccdc: 00fa8ab3 add s5,s5,a5 +8000cce0: fd070793 addi a5,a4,-48 +8000cce4: 001c0c13 addi s8,s8,1 +8000cce8: fefd72e3 bgeu s10,a5,8000cccc <_vfiprintf_r+0x7e0> +8000ccec: 9adff06f j 8000c698 <_vfiprintf_r+0x1ac> +8000ccf0: 01012683 lw a3,16(sp) +8000ccf4: 020b7793 andi a5,s6,32 +8000ccf8: 0006a703 lw a4,0(a3) +8000ccfc: 00468693 addi a3,a3,4 +8000cd00: 00d12823 sw a3,16(sp) +8000cd04: 6a079a63 bnez a5,8000d3b8 <_vfiprintf_r+0xecc> +8000cd08: 010b7793 andi a5,s6,16 +8000cd0c: 04079ce3 bnez a5,8000d564 <_vfiprintf_r+0x1078> +8000cd10: 040b7793 andi a5,s6,64 +8000cd14: 140790e3 bnez a5,8000d654 <_vfiprintf_r+0x1168> +8000cd18: 200b7313 andi t1,s6,512 +8000cd1c: 040304e3 beqz t1,8000d564 <_vfiprintf_r+0x1078> +8000cd20: 00c12783 lw a5,12(sp) +8000cd24: 00f70023 sb a5,0(a4) +8000cd28: 8c5ff06f j 8000c5ec <_vfiprintf_r+0x100> +8000cd2c: 00100693 li a3,1 +8000cd30: 1ad70ee3 beq a4,a3,8000d6ec <_vfiprintf_r+0x1200> +8000cd34: 00200693 li a3,2 +8000cd38: 000b0d93 mv s11,s6 +8000cd3c: dad710e3 bne a4,a3,8000cadc <_vfiprintf_r+0x5f0> +8000cd40: 01812683 lw a3,24(sp) +8000cd44: 0f010413 addi s0,sp,240 +8000cd48: 00fd7793 andi a5,s10,15 +8000cd4c: 00f687b3 add a5,a3,a5 +8000cd50: 0007c703 lbu a4,0(a5) +8000cd54: 004d5d13 srli s10,s10,0x4 +8000cd58: 01cc9793 slli a5,s9,0x1c +8000cd5c: 01a7ed33 or s10,a5,s10 +8000cd60: 004cdc93 srli s9,s9,0x4 +8000cd64: fee40fa3 sb a4,-1(s0) +8000cd68: 019d67b3 or a5,s10,s9 +8000cd6c: fff40413 addi s0,s0,-1 +8000cd70: fc079ce3 bnez a5,8000cd48 <_vfiprintf_r+0x85c> +8000cd74: 0f010793 addi a5,sp,240 +8000cd78: 40878d33 sub s10,a5,s0 +8000cd7c: 000d8b13 mv s6,s11 +8000cd80: bedff06f j 8000c96c <_vfiprintf_r+0x480> +8000cd84: 00412583 lw a1,4(sp) +8000cd88: 41958db3 sub s11,a1,s9 +8000cd8c: a5b058e3 blez s11,8000c7dc <_vfiprintf_r+0x2f0> +8000cd90: 01000593 li a1,16 +8000cd94: 17b5d6e3 bge a1,s11,8000d700 <_vfiprintf_r+0x1214> +8000cd98: 01000e93 li t4,16 +8000cd9c: 00700f13 li t5,7 +8000cda0: 0180006f j 8000cdb8 <_vfiprintf_r+0x8cc> +8000cda4: 00270613 addi a2,a4,2 +8000cda8: 008b8b93 addi s7,s7,8 +8000cdac: 00068713 mv a4,a3 +8000cdb0: ff0d8d93 addi s11,s11,-16 +8000cdb4: 05bedc63 bge t4,s11,8000ce0c <_vfiprintf_r+0x920> +8000cdb8: 01078793 addi a5,a5,16 +8000cdbc: 00170693 addi a3,a4,1 +8000cdc0: 012ba023 sw s2,0(s7) +8000cdc4: 01dba223 sw t4,4(s7) +8000cdc8: 04f12423 sw a5,72(sp) +8000cdcc: 04d12223 sw a3,68(sp) +8000cdd0: fcdf5ae3 bge t5,a3,8000cda4 <_vfiprintf_r+0x8b8> +8000cdd4: 16078063 beqz a5,8000cf34 <_vfiprintf_r+0xa48> +8000cdd8: 04010613 addi a2,sp,64 +8000cddc: 00098593 mv a1,s3 +8000cde0: 000a0513 mv a0,s4 +8000cde4: e00ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000cde8: a80510e3 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000cdec: 04412703 lw a4,68(sp) +8000cdf0: 01000e93 li t4,16 +8000cdf4: ff0d8d93 addi s11,s11,-16 +8000cdf8: 04812783 lw a5,72(sp) +8000cdfc: 00048b93 mv s7,s1 +8000ce00: 00170613 addi a2,a4,1 +8000ce04: 00700f13 li t5,7 +8000ce08: fbbec8e3 blt t4,s11,8000cdb8 <_vfiprintf_r+0x8cc> +8000ce0c: 00060593 mv a1,a2 +8000ce10: 008b8513 addi a0,s7,8 +8000ce14: 01b787b3 add a5,a5,s11 +8000ce18: 012ba023 sw s2,0(s7) +8000ce1c: 01bba223 sw s11,4(s7) +8000ce20: 04f12423 sw a5,72(sp) +8000ce24: 04b12223 sw a1,68(sp) +8000ce28: 00700713 li a4,7 +8000ce2c: 52b75a63 bge a4,a1,8000d360 <_vfiprintf_r+0xe74> +8000ce30: 7e078663 beqz a5,8000d61c <_vfiprintf_r+0x1130> +8000ce34: 04010613 addi a2,sp,64 +8000ce38: 00098593 mv a1,s3 +8000ce3c: 000a0513 mv a0,s4 +8000ce40: da4ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000ce44: a20512e3 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000ce48: 04412703 lw a4,68(sp) +8000ce4c: 41aa8ab3 sub s5,s5,s10 +8000ce50: 04812783 lw a5,72(sp) +8000ce54: 05410693 addi a3,sp,84 +8000ce58: 00170613 addi a2,a4,1 +8000ce5c: 00048b93 mv s7,s1 +8000ce60: 995052e3 blez s5,8000c7e4 <_vfiprintf_r+0x2f8> +8000ce64: 01000593 li a1,16 +8000ce68: 7b55d063 bge a1,s5,8000d608 <_vfiprintf_r+0x111c> +8000ce6c: 01000893 li a7,16 +8000ce70: 00700d93 li s11,7 +8000ce74: 0180006f j 8000ce8c <_vfiprintf_r+0x9a0> +8000ce78: 00270613 addi a2,a4,2 +8000ce7c: 008b8b93 addi s7,s7,8 +8000ce80: 00068713 mv a4,a3 +8000ce84: ff0a8a93 addi s5,s5,-16 +8000ce88: 0558da63 bge a7,s5,8000cedc <_vfiprintf_r+0x9f0> +8000ce8c: 01078793 addi a5,a5,16 +8000ce90: 00170693 addi a3,a4,1 +8000ce94: 012ba023 sw s2,0(s7) +8000ce98: 011ba223 sw a7,4(s7) +8000ce9c: 04f12423 sw a5,72(sp) +8000cea0: 04d12223 sw a3,68(sp) +8000cea4: fcdddae3 bge s11,a3,8000ce78 <_vfiprintf_r+0x98c> +8000cea8: 06078263 beqz a5,8000cf0c <_vfiprintf_r+0xa20> +8000ceac: 04010613 addi a2,sp,64 +8000ceb0: 00098593 mv a1,s3 +8000ceb4: 000a0513 mv a0,s4 +8000ceb8: d2cff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000cebc: 9a0516e3 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000cec0: 04412703 lw a4,68(sp) +8000cec4: 01000893 li a7,16 +8000cec8: ff0a8a93 addi s5,s5,-16 +8000cecc: 04812783 lw a5,72(sp) +8000ced0: 00048b93 mv s7,s1 +8000ced4: 00170613 addi a2,a4,1 +8000ced8: fb58cae3 blt a7,s5,8000ce8c <_vfiprintf_r+0x9a0> +8000cedc: 008b8593 addi a1,s7,8 +8000cee0: 015787b3 add a5,a5,s5 +8000cee4: 012ba023 sw s2,0(s7) +8000cee8: 015ba223 sw s5,4(s7) +8000ceec: 04f12423 sw a5,72(sp) +8000cef0: 04c12223 sw a2,68(sp) +8000cef4: 00700713 li a4,7 +8000cef8: 2cc74663 blt a4,a2,8000d1c4 <_vfiprintf_r+0xcd8> +8000cefc: 00160613 addi a2,a2,1 +8000cf00: 00858693 addi a3,a1,8 +8000cf04: 00058b93 mv s7,a1 +8000cf08: 8ddff06f j 8000c7e4 <_vfiprintf_r+0x2f8> +8000cf0c: 00100613 li a2,1 +8000cf10: 00000713 li a4,0 +8000cf14: 00048b93 mv s7,s1 +8000cf18: f6dff06f j 8000ce84 <_vfiprintf_r+0x998> +8000cf1c: 04010613 addi a2,sp,64 +8000cf20: 00098593 mv a1,s3 +8000cf24: 000a0513 mv a0,s4 +8000cf28: cbcff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000cf2c: 920502e3 beqz a0,8000c850 <_vfiprintf_r+0x364> +8000cf30: 939ff06f j 8000c868 <_vfiprintf_r+0x37c> +8000cf34: 00100613 li a2,1 +8000cf38: 00000713 li a4,0 +8000cf3c: 00048b93 mv s7,s1 +8000cf40: e71ff06f j 8000cdb0 <_vfiprintf_r+0x8c4> +8000cf44: 30078c63 beqz a5,8000d25c <_vfiprintf_r+0xd70> +8000cf48: 04010613 addi a2,sp,64 +8000cf4c: 00098593 mv a1,s3 +8000cf50: 000a0513 mv a0,s4 +8000cf54: 03e12623 sw t5,44(sp) +8000cf58: 03f12423 sw t6,40(sp) +8000cf5c: c88ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000cf60: 900514e3 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000cf64: 04412703 lw a4,68(sp) +8000cf68: 04812783 lw a5,72(sp) +8000cf6c: 02c12f03 lw t5,44(sp) +8000cf70: 02812f83 lw t6,40(sp) +8000cf74: 05410693 addi a3,sp,84 +8000cf78: 00170613 addi a2,a4,1 +8000cf7c: 00048b93 mv s7,s1 +8000cf80: ff8ff06f j 8000c778 <_vfiprintf_r+0x28c> +8000cf84: 03c10793 addi a5,sp,60 +8000cf88: 04f12623 sw a5,76(sp) +8000cf8c: 00200793 li a5,2 +8000cf90: 04f12823 sw a5,80(sp) +8000cf94: 00100613 li a2,1 +8000cf98: 05410693 addi a3,sp,84 +8000cf9c: 00060713 mv a4,a2 +8000cfa0: 00068b93 mv s7,a3 +8000cfa4: 00170613 addi a2,a4,1 +8000cfa8: 008b8693 addi a3,s7,8 +8000cfac: 829ff06f j 8000c7d4 <_vfiprintf_r+0x2e8> +8000cfb0: 000b0d93 mv s11,s6 +8000cfb4: b19ff06f j 8000cacc <_vfiprintf_r+0x5e0> +8000cfb8: 01000613 li a2,16 +8000cfbc: 73b65063 bge a2,s11,8000d6dc <_vfiprintf_r+0x11f0> +8000cfc0: 000b8613 mv a2,s7 +8000cfc4: 01000e93 li t4,16 +8000cfc8: 00040b93 mv s7,s0 +8000cfcc: 00700293 li t0,7 +8000cfd0: 00098413 mv s0,s3 +8000cfd4: 03f12423 sw t6,40(sp) +8000cfd8: 000d8993 mv s3,s11 +8000cfdc: 000c0d93 mv s11,s8 +8000cfe0: 000a8c13 mv s8,s5 +8000cfe4: 000f0a93 mv s5,t5 +8000cfe8: 01c0006f j 8000d004 <_vfiprintf_r+0xb18> +8000cfec: 00270513 addi a0,a4,2 +8000cff0: 00860613 addi a2,a2,8 +8000cff4: 00068713 mv a4,a3 +8000cff8: ff098993 addi s3,s3,-16 +8000cffc: 053ede63 bge t4,s3,8000d058 <_vfiprintf_r+0xb6c> +8000d000: 00170693 addi a3,a4,1 +8000d004: 00812583 lw a1,8(sp) +8000d008: 01078793 addi a5,a5,16 +8000d00c: 01d62223 sw t4,4(a2) +8000d010: 00b62023 sw a1,0(a2) +8000d014: 04f12423 sw a5,72(sp) +8000d018: 04d12223 sw a3,68(sp) +8000d01c: fcd2d8e3 bge t0,a3,8000cfec <_vfiprintf_r+0xb00> +8000d020: 08078663 beqz a5,8000d0ac <_vfiprintf_r+0xbc0> +8000d024: 04010613 addi a2,sp,64 +8000d028: 00040593 mv a1,s0 +8000d02c: 000a0513 mv a0,s4 +8000d030: bb4ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000d034: 4c051663 bnez a0,8000d500 <_vfiprintf_r+0x1014> +8000d038: 04412703 lw a4,68(sp) +8000d03c: 01000e93 li t4,16 +8000d040: ff098993 addi s3,s3,-16 +8000d044: 04812783 lw a5,72(sp) +8000d048: 00048613 mv a2,s1 +8000d04c: 00170513 addi a0,a4,1 +8000d050: 00700293 li t0,7 +8000d054: fb3ec6e3 blt t4,s3,8000d000 <_vfiprintf_r+0xb14> +8000d058: 02812f83 lw t6,40(sp) +8000d05c: 000a8f13 mv t5,s5 +8000d060: 00050593 mv a1,a0 +8000d064: 000c0a93 mv s5,s8 +8000d068: 000d8c13 mv s8,s11 +8000d06c: 00098d93 mv s11,s3 +8000d070: 00040993 mv s3,s0 +8000d074: 000b8413 mv s0,s7 +8000d078: 00060b93 mv s7,a2 +8000d07c: 00812703 lw a4,8(sp) +8000d080: 01b787b3 add a5,a5,s11 +8000d084: 01bba223 sw s11,4(s7) +8000d088: 00eba023 sw a4,0(s7) +8000d08c: 04f12423 sw a5,72(sp) +8000d090: 04b12223 sw a1,68(sp) +8000d094: 00700713 li a4,7 +8000d098: 1eb74263 blt a4,a1,8000d27c <_vfiprintf_r+0xd90> +8000d09c: 008b8b93 addi s7,s7,8 +8000d0a0: 00158613 addi a2,a1,1 +8000d0a4: 00058713 mv a4,a1 +8000d0a8: e90ff06f j 8000c738 <_vfiprintf_r+0x24c> +8000d0ac: 00000713 li a4,0 +8000d0b0: 00100513 li a0,1 +8000d0b4: 00048613 mv a2,s1 +8000d0b8: f41ff06f j 8000cff8 <_vfiprintf_r+0xb0c> +8000d0bc: 04012223 sw zero,68(sp) +8000d0c0: 004b7313 andi t1,s6,4 +8000d0c4: 0e030263 beqz t1,8000d1a8 <_vfiprintf_r+0xcbc> +8000d0c8: 00412703 lw a4,4(sp) +8000d0cc: 41970bb3 sub s7,a4,s9 +8000d0d0: 0d705c63 blez s7,8000d1a8 <_vfiprintf_r+0xcbc> +8000d0d4: 00048693 mv a3,s1 +8000d0d8: 01000713 li a4,16 +8000d0dc: 04412603 lw a2,68(sp) +8000d0e0: 61775263 bge a4,s7,8000d6e4 <_vfiprintf_r+0x11f8> +8000d0e4: 01000d13 li s10,16 +8000d0e8: 00700d93 li s11,7 +8000d0ec: 0180006f j 8000d104 <_vfiprintf_r+0xc18> +8000d0f0: 00260513 addi a0,a2,2 +8000d0f4: 00868693 addi a3,a3,8 +8000d0f8: 00070613 mv a2,a4 +8000d0fc: ff0b8b93 addi s7,s7,-16 +8000d100: 057d5a63 bge s10,s7,8000d154 <_vfiprintf_r+0xc68> +8000d104: 00812583 lw a1,8(sp) +8000d108: 01078793 addi a5,a5,16 +8000d10c: 00160713 addi a4,a2,1 +8000d110: 00b6a023 sw a1,0(a3) +8000d114: 01a6a223 sw s10,4(a3) +8000d118: 04f12423 sw a5,72(sp) +8000d11c: 04e12223 sw a4,68(sp) +8000d120: fcedd8e3 bge s11,a4,8000d0f0 <_vfiprintf_r+0xc04> +8000d124: 06078a63 beqz a5,8000d198 <_vfiprintf_r+0xcac> +8000d128: 04010613 addi a2,sp,64 +8000d12c: 00098593 mv a1,s3 +8000d130: 000a0513 mv a0,s4 +8000d134: ab0ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000d138: f2051863 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000d13c: 04412603 lw a2,68(sp) +8000d140: ff0b8b93 addi s7,s7,-16 +8000d144: 04812783 lw a5,72(sp) +8000d148: 00048693 mv a3,s1 +8000d14c: 00160513 addi a0,a2,1 +8000d150: fb7d4ae3 blt s10,s7,8000d104 <_vfiprintf_r+0xc18> +8000d154: 00050593 mv a1,a0 +8000d158: 00812703 lw a4,8(sp) +8000d15c: 017787b3 add a5,a5,s7 +8000d160: 0176a223 sw s7,4(a3) +8000d164: 00e6a023 sw a4,0(a3) +8000d168: 04f12423 sw a5,72(sp) +8000d16c: 04b12223 sw a1,68(sp) +8000d170: 00700713 li a4,7 +8000d174: ecb75063 bge a4,a1,8000c834 <_vfiprintf_r+0x348> +8000d178: 02078863 beqz a5,8000d1a8 <_vfiprintf_r+0xcbc> +8000d17c: 04010613 addi a2,sp,64 +8000d180: 00098593 mv a1,s3 +8000d184: 000a0513 mv a0,s4 +8000d188: a5cff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000d18c: ec051e63 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000d190: 04812783 lw a5,72(sp) +8000d194: ea0ff06f j 8000c834 <_vfiprintf_r+0x348> +8000d198: 00100513 li a0,1 +8000d19c: 00000613 li a2,0 +8000d1a0: 00048693 mv a3,s1 +8000d1a4: f59ff06f j 8000d0fc <_vfiprintf_r+0xc10> +8000d1a8: 00412403 lw s0,4(sp) +8000d1ac: 01945463 bge s0,s9,8000d1b4 <_vfiprintf_r+0xcc8> +8000d1b0: 000c8413 mv s0,s9 +8000d1b4: 00c12783 lw a5,12(sp) +8000d1b8: 008787b3 add a5,a5,s0 +8000d1bc: 00f12623 sw a5,12(sp) +8000d1c0: e90ff06f j 8000c850 <_vfiprintf_r+0x364> +8000d1c4: 34078263 beqz a5,8000d508 <_vfiprintf_r+0x101c> +8000d1c8: 04010613 addi a2,sp,64 +8000d1cc: 00098593 mv a1,s3 +8000d1d0: 000a0513 mv a0,s4 +8000d1d4: a10ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000d1d8: e8051863 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000d1dc: 04412603 lw a2,68(sp) +8000d1e0: 04812783 lw a5,72(sp) +8000d1e4: 05410693 addi a3,sp,84 +8000d1e8: 00160613 addi a2,a2,1 +8000d1ec: 00048b93 mv s7,s1 +8000d1f0: df4ff06f j 8000c7e4 <_vfiprintf_r+0x2f8> +8000d1f4: 04012223 sw zero,68(sp) +8000d1f8: 00048b93 mv s7,s1 +8000d1fc: c60ff06f j 8000c65c <_vfiprintf_r+0x170> +8000d200: f40a9c63 bnez s5,8000c958 <_vfiprintf_r+0x46c> +8000d204: 000d8b13 mv s6,s11 +8000d208: 00000a93 li s5,0 +8000d20c: 00000d13 li s10,0 +8000d210: 0f010413 addi s0,sp,240 +8000d214: f58ff06f j 8000c96c <_vfiprintf_r+0x480> +8000d218: 01012683 lw a3,16(sp) +8000d21c: 010df793 andi a5,s11,16 +8000d220: 00468713 addi a4,a3,4 +8000d224: 14079863 bnez a5,8000d374 <_vfiprintf_r+0xe88> +8000d228: 040df793 andi a5,s11,64 +8000d22c: 3a078063 beqz a5,8000d5cc <_vfiprintf_r+0x10e0> +8000d230: 01012783 lw a5,16(sp) +8000d234: 00000c93 li s9,0 +8000d238: 00e12823 sw a4,16(sp) +8000d23c: 0007dd03 lhu s10,0(a5) +8000d240: 00100713 li a4,1 +8000d244: fb8ff06f j 8000c9fc <_vfiprintf_r+0x510> +8000d248: 05410693 addi a3,sp,84 +8000d24c: 00100613 li a2,1 +8000d250: 00000713 li a4,0 +8000d254: 00048b93 mv s7,s1 +8000d258: d7cff06f j 8000c7d4 <_vfiprintf_r+0x2e8> +8000d25c: 180f8063 beqz t6,8000d3dc <_vfiprintf_r+0xef0> +8000d260: 03c10793 addi a5,sp,60 +8000d264: 04f12623 sw a5,76(sp) +8000d268: 00200793 li a5,2 +8000d26c: 04f12823 sw a5,80(sp) +8000d270: 00100713 li a4,1 +8000d274: 05410b93 addi s7,sp,84 +8000d278: d2dff06f j 8000cfa4 <_vfiprintf_r+0xab8> +8000d27c: 22078263 beqz a5,8000d4a0 <_vfiprintf_r+0xfb4> +8000d280: 04010613 addi a2,sp,64 +8000d284: 00098593 mv a1,s3 +8000d288: 000a0513 mv a0,s4 +8000d28c: 03e12623 sw t5,44(sp) +8000d290: 03f12423 sw t6,40(sp) +8000d294: 950ff0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000d298: dc051863 bnez a0,8000c868 <_vfiprintf_r+0x37c> +8000d29c: 04412703 lw a4,68(sp) +8000d2a0: 04812783 lw a5,72(sp) +8000d2a4: 02c12f03 lw t5,44(sp) +8000d2a8: 02812f83 lw t6,40(sp) +8000d2ac: 00048b93 mv s7,s1 +8000d2b0: 00170613 addi a2,a4,1 +8000d2b4: c84ff06f j 8000c738 <_vfiprintf_r+0x24c> +8000d2b8: 400df793 andi a5,s11,1024 +8000d2bc: 03412423 sw s4,40(sp) +8000d2c0: 03312623 sw s3,44(sp) +8000d2c4: 000c8a13 mv s4,s9 +8000d2c8: 000d0993 mv s3,s10 +8000d2cc: 00000b13 li s6,0 +8000d2d0: 01c12d03 lw s10,28(sp) 8000d2d4: 0f010413 addi s0,sp,240 -8000d2d8: f58ff06f j 8000ca30 <_vfiprintf_r+0x480> -8000d2dc: 01012683 lw a3,16(sp) -8000d2e0: 010df793 andi a5,s11,16 -8000d2e4: 00468713 addi a4,a3,4 -8000d2e8: 14079863 bnez a5,8000d438 <_vfiprintf_r+0xe88> -8000d2ec: 040df793 andi a5,s11,64 -8000d2f0: 3a078063 beqz a5,8000d690 <_vfiprintf_r+0x10e0> -8000d2f4: 01012783 lw a5,16(sp) -8000d2f8: 00000c93 li s9,0 -8000d2fc: 00e12823 sw a4,16(sp) -8000d300: 0007dd03 lhu s10,0(a5) -8000d304: 00100713 li a4,1 -8000d308: fb8ff06f j 8000cac0 <_vfiprintf_r+0x510> -8000d30c: 05410693 addi a3,sp,84 -8000d310: 00100613 li a2,1 -8000d314: 00000713 li a4,0 -8000d318: 00048b93 mv s7,s1 -8000d31c: d7cff06f j 8000c898 <_vfiprintf_r+0x2e8> -8000d320: 180f8063 beqz t6,8000d4a0 <_vfiprintf_r+0xef0> -8000d324: 03c10793 addi a5,sp,60 -8000d328: 04f12623 sw a5,76(sp) -8000d32c: 00200793 li a5,2 -8000d330: 04f12823 sw a5,80(sp) -8000d334: 00100713 li a4,1 -8000d338: 05410b93 addi s7,sp,84 -8000d33c: d2dff06f j 8000d068 <_vfiprintf_r+0xab8> -8000d340: 22078263 beqz a5,8000d564 <_vfiprintf_r+0xfb4> -8000d344: 04010613 addi a2,sp,64 -8000d348: 00098593 mv a1,s3 -8000d34c: 000a0513 mv a0,s4 -8000d350: 03e12623 sw t5,44(sp) -8000d354: 03f12423 sw t6,40(sp) -8000d358: 950ff0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000d35c: dc051863 bnez a0,8000c92c <_vfiprintf_r+0x37c> -8000d360: 04412703 lw a4,68(sp) -8000d364: 04812783 lw a5,72(sp) -8000d368: 02c12f03 lw t5,44(sp) -8000d36c: 02812f83 lw t6,40(sp) -8000d370: 00048b93 mv s7,s1 -8000d374: 00170613 addi a2,a4,1 -8000d378: c84ff06f j 8000c7fc <_vfiprintf_r+0x24c> -8000d37c: 400df793 andi a5,s11,1024 -8000d380: 03412423 sw s4,40(sp) -8000d384: 03312623 sw s3,44(sp) -8000d388: 000c8a13 mv s4,s9 -8000d38c: 000d0993 mv s3,s10 -8000d390: 00000b13 li s6,0 -8000d394: 01c12d03 lw s10,28(sp) -8000d398: 0f010413 addi s0,sp,240 -8000d39c: 00078c93 mv s9,a5 -8000d3a0: 0240006f j 8000d3c4 <_vfiprintf_r+0xe14> -8000d3a4: 00a00613 li a2,10 -8000d3a8: 00000693 li a3,0 -8000d3ac: 00098513 mv a0,s3 -8000d3b0: 000a0593 mv a1,s4 -8000d3b4: 110030ef jal ra,800104c4 <__udivdi3> -8000d3b8: 300a0e63 beqz s4,8000d6d4 <_vfiprintf_r+0x1124> -8000d3bc: 00050993 mv s3,a0 -8000d3c0: 00058a13 mv s4,a1 -8000d3c4: 00a00613 li a2,10 -8000d3c8: 00000693 li a3,0 -8000d3cc: 00098513 mv a0,s3 -8000d3d0: 000a0593 mv a1,s4 -8000d3d4: 524030ef jal ra,800108f8 <__umoddi3> -8000d3d8: 03050513 addi a0,a0,48 -8000d3dc: fea40fa3 sb a0,-1(s0) -8000d3e0: 001b0b13 addi s6,s6,1 -8000d3e4: fff40413 addi s0,s0,-1 -8000d3e8: fa0c8ee3 beqz s9,8000d3a4 <_vfiprintf_r+0xdf4> -8000d3ec: 000d4683 lbu a3,0(s10) -8000d3f0: fb669ae3 bne a3,s6,8000d3a4 <_vfiprintf_r+0xdf4> -8000d3f4: 0ff00793 li a5,255 -8000d3f8: fafb06e3 beq s6,a5,8000d3a4 <_vfiprintf_r+0xdf4> -8000d3fc: 180a1463 bnez s4,8000d584 <_vfiprintf_r+0xfd4> -8000d400: 00900793 li a5,9 -8000d404: 1937e063 bltu a5,s3,8000d584 <_vfiprintf_r+0xfd4> -8000d408: 0f010793 addi a5,sp,240 -8000d40c: 01a12e23 sw s10,28(sp) -8000d410: 02812a03 lw s4,40(sp) -8000d414: 02c12983 lw s3,44(sp) -8000d418: 40878d33 sub s10,a5,s0 -8000d41c: 000d8b13 mv s6,s11 -8000d420: e10ff06f j 8000ca30 <_vfiprintf_r+0x480> -8000d424: 00158613 addi a2,a1,1 -8000d428: 00850693 addi a3,a0,8 -8000d42c: 00058713 mv a4,a1 -8000d430: 00050b93 mv s7,a0 -8000d434: c6cff06f j 8000c8a0 <_vfiprintf_r+0x2f0> -8000d438: 00e12823 sw a4,16(sp) -8000d43c: 0006ad03 lw s10,0(a3) -8000d440: 00000c93 li s9,0 -8000d444: 00100713 li a4,1 -8000d448: e78ff06f j 8000cac0 <_vfiprintf_r+0x510> -8000d44c: 0006ad03 lw s10,0(a3) -8000d450: 00e12823 sw a4,16(sp) -8000d454: 41fd5c93 srai s9,s10,0x1f -8000d458: 000c8713 mv a4,s9 -8000d45c: d98ff06f j 8000c9f4 <_vfiprintf_r+0x444> -8000d460: 01c12783 lw a5,28(sp) -8000d464: 000c4703 lbu a4,0(s8) -8000d468: ae078863 beqz a5,8000c758 <_vfiprintf_r+0x1a8> -8000d46c: 0007c783 lbu a5,0(a5) -8000d470: ae078463 beqz a5,8000c758 <_vfiprintf_r+0x1a8> -8000d474: 400b6b13 ori s6,s6,1024 -8000d478: ae0ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000d47c: 00c12683 lw a3,12(sp) -8000d480: 41f6d793 srai a5,a3,0x1f -8000d484: 00d72023 sw a3,0(a4) -8000d488: 00f72223 sw a5,4(a4) -8000d48c: a24ff06f j 8000c6b0 <_vfiprintf_r+0x100> -8000d490: 0006ad03 lw s10,0(a3) -8000d494: 00000c93 li s9,0 -8000d498: 00e12823 sw a4,16(sp) -8000d49c: e1cff06f j 8000cab8 <_vfiprintf_r+0x508> -8000d4a0: 00000713 li a4,0 -8000d4a4: 05410693 addi a3,sp,84 -8000d4a8: 00100613 li a2,1 -8000d4ac: 00048b93 mv s7,s1 -8000d4b0: be8ff06f j 8000c898 <_vfiprintf_r+0x2e8> -8000d4b4: 000b0d93 mv s11,s6 -8000d4b8: 819ff06f j 8000ccd0 <_vfiprintf_r+0x720> -8000d4bc: 800157b7 lui a5,0x80015 -8000d4c0: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> -8000d4c4: 00f12c23 sw a5,24(sp) -8000d4c8: 020b7793 andi a5,s6,32 -8000d4cc: 06078063 beqz a5,8000d52c <_vfiprintf_r+0xf7c> -8000d4d0: 01012783 lw a5,16(sp) -8000d4d4: 00778793 addi a5,a5,7 -8000d4d8: ff87f793 andi a5,a5,-8 -8000d4dc: 0007ad03 lw s10,0(a5) -8000d4e0: 0047ac83 lw s9,4(a5) -8000d4e4: 00878793 addi a5,a5,8 -8000d4e8: 00f12823 sw a5,16(sp) -8000d4ec: 001b7693 andi a3,s6,1 -8000d4f0: 00068e63 beqz a3,8000d50c <_vfiprintf_r+0xf5c> -8000d4f4: 019d66b3 or a3,s10,s9 -8000d4f8: 00068a63 beqz a3,8000d50c <_vfiprintf_r+0xf5c> -8000d4fc: 03000693 li a3,48 -8000d500: 02d10e23 sb a3,60(sp) -8000d504: 02e10ea3 sb a4,61(sp) -8000d508: 002b6b13 ori s6,s6,2 -8000d50c: bffb7d93 andi s11,s6,-1025 -8000d510: 00200713 li a4,2 -8000d514: dacff06f j 8000cac0 <_vfiprintf_r+0x510> -8000d518: 800157b7 lui a5,0x80015 -8000d51c: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -8000d520: 00f12c23 sw a5,24(sp) -8000d524: 020b7793 andi a5,s6,32 -8000d528: fa0794e3 bnez a5,8000d4d0 <_vfiprintf_r+0xf20> -8000d52c: 01012603 lw a2,16(sp) -8000d530: 010b7793 andi a5,s6,16 -8000d534: 00460693 addi a3,a2,4 -8000d538: 0a078a63 beqz a5,8000d5ec <_vfiprintf_r+0x103c> -8000d53c: 00062d03 lw s10,0(a2) -8000d540: 00000c93 li s9,0 -8000d544: 00d12823 sw a3,16(sp) -8000d548: fa5ff06f j 8000d4ec <_vfiprintf_r+0xf3c> -8000d54c: 00040513 mv a0,s0 -8000d550: c10fc0ef jal ra,80009960 -8000d554: 00050d13 mv s10,a0 -8000d558: 01b12823 sw s11,16(sp) -8000d55c: 00000a93 li s5,0 -8000d560: cd0ff06f j 8000ca30 <_vfiprintf_r+0x480> -8000d564: 03b14703 lbu a4,59(sp) -8000d568: 18071a63 bnez a4,8000d6fc <_vfiprintf_r+0x114c> -8000d56c: ac0f9ee3 bnez t6,8000d048 <_vfiprintf_r+0xa98> -8000d570: 00000713 li a4,0 -8000d574: 00100613 li a2,1 -8000d578: 05410693 addi a3,sp,84 -8000d57c: 00048b93 mv s7,s1 -8000d580: b18ff06f j 8000c898 <_vfiprintf_r+0x2e8> -8000d584: 02412783 lw a5,36(sp) -8000d588: 02012583 lw a1,32(sp) -8000d58c: 00000b13 li s6,0 -8000d590: 40f40433 sub s0,s0,a5 -8000d594: 00078613 mv a2,a5 -8000d598: 00040513 mv a0,s0 -8000d59c: c50fc0ef jal ra,800099ec -8000d5a0: 001d4583 lbu a1,1(s10) -8000d5a4: 00a00613 li a2,10 -8000d5a8: 00000693 li a3,0 -8000d5ac: 00b03733 snez a4,a1 -8000d5b0: 00098513 mv a0,s3 -8000d5b4: 000a0593 mv a1,s4 -8000d5b8: 00ed0d33 add s10,s10,a4 -8000d5bc: 709020ef jal ra,800104c4 <__udivdi3> -8000d5c0: dfdff06f j 8000d3bc <_vfiprintf_r+0xe0c> -8000d5c4: 00040993 mv s3,s0 -8000d5c8: b64ff06f j 8000c92c <_vfiprintf_r+0x37c> -8000d5cc: 00100713 li a4,1 -8000d5d0: 000d0793 mv a5,s10 -8000d5d4: 04812623 sw s0,76(sp) -8000d5d8: 05a12823 sw s10,80(sp) -8000d5dc: 05a12423 sw s10,72(sp) -8000d5e0: 04e12223 sw a4,68(sp) -8000d5e4: 05410693 addi a3,sp,84 -8000d5e8: afcff06f j 8000c8e4 <_vfiprintf_r+0x334> -8000d5ec: 040b7793 andi a5,s6,64 -8000d5f0: 06078263 beqz a5,8000d654 <_vfiprintf_r+0x10a4> +8000d2d8: 00078c93 mv s9,a5 +8000d2dc: 0240006f j 8000d300 <_vfiprintf_r+0xe14> +8000d2e0: 00a00613 li a2,10 +8000d2e4: 00000693 li a3,0 +8000d2e8: 00098513 mv a0,s3 +8000d2ec: 000a0593 mv a1,s4 +8000d2f0: 110030ef jal ra,80010400 <__udivdi3> +8000d2f4: 300a0e63 beqz s4,8000d610 <_vfiprintf_r+0x1124> +8000d2f8: 00050993 mv s3,a0 +8000d2fc: 00058a13 mv s4,a1 +8000d300: 00a00613 li a2,10 +8000d304: 00000693 li a3,0 +8000d308: 00098513 mv a0,s3 +8000d30c: 000a0593 mv a1,s4 +8000d310: 524030ef jal ra,80010834 <__umoddi3> +8000d314: 03050513 addi a0,a0,48 +8000d318: fea40fa3 sb a0,-1(s0) +8000d31c: 001b0b13 addi s6,s6,1 +8000d320: fff40413 addi s0,s0,-1 +8000d324: fa0c8ee3 beqz s9,8000d2e0 <_vfiprintf_r+0xdf4> +8000d328: 000d4683 lbu a3,0(s10) +8000d32c: fb669ae3 bne a3,s6,8000d2e0 <_vfiprintf_r+0xdf4> +8000d330: 0ff00793 li a5,255 +8000d334: fafb06e3 beq s6,a5,8000d2e0 <_vfiprintf_r+0xdf4> +8000d338: 180a1463 bnez s4,8000d4c0 <_vfiprintf_r+0xfd4> +8000d33c: 00900793 li a5,9 +8000d340: 1937e063 bltu a5,s3,8000d4c0 <_vfiprintf_r+0xfd4> +8000d344: 0f010793 addi a5,sp,240 +8000d348: 01a12e23 sw s10,28(sp) +8000d34c: 02812a03 lw s4,40(sp) +8000d350: 02c12983 lw s3,44(sp) +8000d354: 40878d33 sub s10,a5,s0 +8000d358: 000d8b13 mv s6,s11 +8000d35c: e10ff06f j 8000c96c <_vfiprintf_r+0x480> +8000d360: 00158613 addi a2,a1,1 +8000d364: 00850693 addi a3,a0,8 +8000d368: 00058713 mv a4,a1 +8000d36c: 00050b93 mv s7,a0 +8000d370: c6cff06f j 8000c7dc <_vfiprintf_r+0x2f0> +8000d374: 00e12823 sw a4,16(sp) +8000d378: 0006ad03 lw s10,0(a3) +8000d37c: 00000c93 li s9,0 +8000d380: 00100713 li a4,1 +8000d384: e78ff06f j 8000c9fc <_vfiprintf_r+0x510> +8000d388: 0006ad03 lw s10,0(a3) +8000d38c: 00e12823 sw a4,16(sp) +8000d390: 41fd5c93 srai s9,s10,0x1f +8000d394: 000c8713 mv a4,s9 +8000d398: d98ff06f j 8000c930 <_vfiprintf_r+0x444> +8000d39c: 01c12783 lw a5,28(sp) +8000d3a0: 000c4703 lbu a4,0(s8) +8000d3a4: ae078863 beqz a5,8000c694 <_vfiprintf_r+0x1a8> +8000d3a8: 0007c783 lbu a5,0(a5) +8000d3ac: ae078463 beqz a5,8000c694 <_vfiprintf_r+0x1a8> +8000d3b0: 400b6b13 ori s6,s6,1024 +8000d3b4: ae0ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000d3b8: 00c12683 lw a3,12(sp) +8000d3bc: 41f6d793 srai a5,a3,0x1f +8000d3c0: 00d72023 sw a3,0(a4) +8000d3c4: 00f72223 sw a5,4(a4) +8000d3c8: a24ff06f j 8000c5ec <_vfiprintf_r+0x100> +8000d3cc: 0006ad03 lw s10,0(a3) +8000d3d0: 00000c93 li s9,0 +8000d3d4: 00e12823 sw a4,16(sp) +8000d3d8: e1cff06f j 8000c9f4 <_vfiprintf_r+0x508> +8000d3dc: 00000713 li a4,0 +8000d3e0: 05410693 addi a3,sp,84 +8000d3e4: 00100613 li a2,1 +8000d3e8: 00048b93 mv s7,s1 +8000d3ec: be8ff06f j 8000c7d4 <_vfiprintf_r+0x2e8> +8000d3f0: 000b0d93 mv s11,s6 +8000d3f4: 819ff06f j 8000cc0c <_vfiprintf_r+0x720> +8000d3f8: 800157b7 lui a5,0x80015 +8000d3fc: bb878793 addi a5,a5,-1096 # 80014bb8 <__BSS_END__+0xffffdf7c> +8000d400: 00f12c23 sw a5,24(sp) +8000d404: 020b7793 andi a5,s6,32 +8000d408: 06078063 beqz a5,8000d468 <_vfiprintf_r+0xf7c> +8000d40c: 01012783 lw a5,16(sp) +8000d410: 00778793 addi a5,a5,7 +8000d414: ff87f793 andi a5,a5,-8 +8000d418: 0007ad03 lw s10,0(a5) +8000d41c: 0047ac83 lw s9,4(a5) +8000d420: 00878793 addi a5,a5,8 +8000d424: 00f12823 sw a5,16(sp) +8000d428: 001b7693 andi a3,s6,1 +8000d42c: 00068e63 beqz a3,8000d448 <_vfiprintf_r+0xf5c> +8000d430: 019d66b3 or a3,s10,s9 +8000d434: 00068a63 beqz a3,8000d448 <_vfiprintf_r+0xf5c> +8000d438: 03000693 li a3,48 +8000d43c: 02d10e23 sb a3,60(sp) +8000d440: 02e10ea3 sb a4,61(sp) +8000d444: 002b6b13 ori s6,s6,2 +8000d448: bffb7d93 andi s11,s6,-1025 +8000d44c: 00200713 li a4,2 +8000d450: dacff06f j 8000c9fc <_vfiprintf_r+0x510> +8000d454: 800157b7 lui a5,0x80015 +8000d458: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +8000d45c: 00f12c23 sw a5,24(sp) +8000d460: 020b7793 andi a5,s6,32 +8000d464: fa0794e3 bnez a5,8000d40c <_vfiprintf_r+0xf20> +8000d468: 01012603 lw a2,16(sp) +8000d46c: 010b7793 andi a5,s6,16 +8000d470: 00460693 addi a3,a2,4 +8000d474: 0a078a63 beqz a5,8000d528 <_vfiprintf_r+0x103c> +8000d478: 00062d03 lw s10,0(a2) +8000d47c: 00000c93 li s9,0 +8000d480: 00d12823 sw a3,16(sp) +8000d484: fa5ff06f j 8000d428 <_vfiprintf_r+0xf3c> +8000d488: 00040513 mv a0,s0 +8000d48c: c10fc0ef jal ra,8000989c +8000d490: 00050d13 mv s10,a0 +8000d494: 01b12823 sw s11,16(sp) +8000d498: 00000a93 li s5,0 +8000d49c: cd0ff06f j 8000c96c <_vfiprintf_r+0x480> +8000d4a0: 03b14703 lbu a4,59(sp) +8000d4a4: 18071a63 bnez a4,8000d638 <_vfiprintf_r+0x114c> +8000d4a8: ac0f9ee3 bnez t6,8000cf84 <_vfiprintf_r+0xa98> +8000d4ac: 00000713 li a4,0 +8000d4b0: 00100613 li a2,1 +8000d4b4: 05410693 addi a3,sp,84 +8000d4b8: 00048b93 mv s7,s1 +8000d4bc: b18ff06f j 8000c7d4 <_vfiprintf_r+0x2e8> +8000d4c0: 02412783 lw a5,36(sp) +8000d4c4: 02012583 lw a1,32(sp) +8000d4c8: 00000b13 li s6,0 +8000d4cc: 40f40433 sub s0,s0,a5 +8000d4d0: 00078613 mv a2,a5 +8000d4d4: 00040513 mv a0,s0 +8000d4d8: c50fc0ef jal ra,80009928 +8000d4dc: 001d4583 lbu a1,1(s10) +8000d4e0: 00a00613 li a2,10 +8000d4e4: 00000693 li a3,0 +8000d4e8: 00b03733 snez a4,a1 +8000d4ec: 00098513 mv a0,s3 +8000d4f0: 000a0593 mv a1,s4 +8000d4f4: 00ed0d33 add s10,s10,a4 +8000d4f8: 709020ef jal ra,80010400 <__udivdi3> +8000d4fc: dfdff06f j 8000d2f8 <_vfiprintf_r+0xe0c> +8000d500: 00040993 mv s3,s0 +8000d504: b64ff06f j 8000c868 <_vfiprintf_r+0x37c> +8000d508: 00100713 li a4,1 +8000d50c: 000d0793 mv a5,s10 +8000d510: 04812623 sw s0,76(sp) +8000d514: 05a12823 sw s10,80(sp) +8000d518: 05a12423 sw s10,72(sp) +8000d51c: 04e12223 sw a4,68(sp) +8000d520: 05410693 addi a3,sp,84 +8000d524: afcff06f j 8000c820 <_vfiprintf_r+0x334> +8000d528: 040b7793 andi a5,s6,64 +8000d52c: 06078263 beqz a5,8000d590 <_vfiprintf_r+0x10a4> +8000d530: 01012783 lw a5,16(sp) +8000d534: 00000c93 li s9,0 +8000d538: 00d12823 sw a3,16(sp) +8000d53c: 0007dd03 lhu s10,0(a5) +8000d540: ee9ff06f j 8000d428 <_vfiprintf_r+0xf3c> +8000d544: 001c4703 lbu a4,1(s8) +8000d548: 200b6b13 ori s6,s6,512 +8000d54c: 001c0c13 addi s8,s8,1 +8000d550: 944ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000d554: 001c4703 lbu a4,1(s8) +8000d558: 020b6b13 ori s6,s6,32 +8000d55c: 001c0c13 addi s8,s8,1 +8000d560: 934ff06f j 8000c694 <_vfiprintf_r+0x1a8> +8000d564: 00c12783 lw a5,12(sp) +8000d568: 00f72023 sw a5,0(a4) +8000d56c: 880ff06f j 8000c5ec <_vfiprintf_r+0x100> +8000d570: 00600793 li a5,6 +8000d574: 000a8d13 mv s10,s5 +8000d578: 0b57ec63 bltu a5,s5,8000d630 <_vfiprintf_r+0x1144> +8000d57c: 80015e37 lui t3,0x80015 +8000d580: 000d0c93 mv s9,s10 +8000d584: 01b12823 sw s11,16(sp) +8000d588: bcce0413 addi s0,t3,-1076 # 80014bcc <__BSS_END__+0xffffdf90> +8000d58c: 978ff06f j 8000c704 <_vfiprintf_r+0x218> +8000d590: 200b7793 andi a5,s6,512 +8000d594: 10078863 beqz a5,8000d6a4 <_vfiprintf_r+0x11b8> +8000d598: 01012783 lw a5,16(sp) +8000d59c: 00000c93 li s9,0 +8000d5a0: 00d12823 sw a3,16(sp) +8000d5a4: 0007cd03 lbu s10,0(a5) +8000d5a8: e81ff06f j 8000d428 <_vfiprintf_r+0xf3c> +8000d5ac: 200b7793 andi a5,s6,512 +8000d5b0: 0c078e63 beqz a5,8000d68c <_vfiprintf_r+0x11a0> +8000d5b4: 01012783 lw a5,16(sp) +8000d5b8: 00e12823 sw a4,16(sp) +8000d5bc: 00078d03 lb s10,0(a5) +8000d5c0: 41fd5c93 srai s9,s10,0x1f +8000d5c4: 000c8713 mv a4,s9 +8000d5c8: b68ff06f j 8000c930 <_vfiprintf_r+0x444> +8000d5cc: 200df793 andi a5,s11,512 +8000d5d0: 0a078263 beqz a5,8000d674 <_vfiprintf_r+0x1188> +8000d5d4: 01012783 lw a5,16(sp) +8000d5d8: 00000c93 li s9,0 +8000d5dc: 00e12823 sw a4,16(sp) +8000d5e0: 0007cd03 lbu s10,0(a5) +8000d5e4: 00100713 li a4,1 +8000d5e8: c14ff06f j 8000c9fc <_vfiprintf_r+0x510> +8000d5ec: 200b7793 andi a5,s6,512 +8000d5f0: 06078863 beqz a5,8000d660 <_vfiprintf_r+0x1174> 8000d5f4: 01012783 lw a5,16(sp) 8000d5f8: 00000c93 li s9,0 -8000d5fc: 00d12823 sw a3,16(sp) -8000d600: 0007dd03 lhu s10,0(a5) -8000d604: ee9ff06f j 8000d4ec <_vfiprintf_r+0xf3c> -8000d608: 001c4703 lbu a4,1(s8) -8000d60c: 200b6b13 ori s6,s6,512 -8000d610: 001c0c13 addi s8,s8,1 -8000d614: 944ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000d618: 001c4703 lbu a4,1(s8) -8000d61c: 020b6b13 ori s6,s6,32 -8000d620: 001c0c13 addi s8,s8,1 -8000d624: 934ff06f j 8000c758 <_vfiprintf_r+0x1a8> -8000d628: 00c12783 lw a5,12(sp) -8000d62c: 00f72023 sw a5,0(a4) -8000d630: 880ff06f j 8000c6b0 <_vfiprintf_r+0x100> -8000d634: 00600793 li a5,6 -8000d638: 000a8d13 mv s10,s5 -8000d63c: 0b57ec63 bltu a5,s5,8000d6f4 <_vfiprintf_r+0x1144> -8000d640: 80015e37 lui t3,0x80015 -8000d644: 000d0c93 mv s9,s10 -8000d648: 01b12823 sw s11,16(sp) -8000d64c: ca0e0413 addi s0,t3,-864 # 80014ca0 <__BSS_END__+0xffffe064> -8000d650: 978ff06f j 8000c7c8 <_vfiprintf_r+0x218> -8000d654: 200b7793 andi a5,s6,512 -8000d658: 10078863 beqz a5,8000d768 <_vfiprintf_r+0x11b8> -8000d65c: 01012783 lw a5,16(sp) -8000d660: 00000c93 li s9,0 -8000d664: 00d12823 sw a3,16(sp) -8000d668: 0007cd03 lbu s10,0(a5) -8000d66c: e81ff06f j 8000d4ec <_vfiprintf_r+0xf3c> -8000d670: 200b7793 andi a5,s6,512 -8000d674: 0c078e63 beqz a5,8000d750 <_vfiprintf_r+0x11a0> -8000d678: 01012783 lw a5,16(sp) +8000d5fc: 00e12823 sw a4,16(sp) +8000d600: 0007cd03 lbu s10,0(a5) +8000d604: bf0ff06f j 8000c9f4 <_vfiprintf_r+0x508> +8000d608: 00068593 mv a1,a3 +8000d60c: 8d5ff06f j 8000cee0 <_vfiprintf_r+0x9f4> +8000d610: 00900793 li a5,9 +8000d614: cf37e2e3 bltu a5,s3,8000d2f8 <_vfiprintf_r+0xe0c> +8000d618: d2dff06f j 8000d344 <_vfiprintf_r+0xe58> +8000d61c: 05410693 addi a3,sp,84 +8000d620: 00100613 li a2,1 +8000d624: 00000713 li a4,0 +8000d628: 00048b93 mv s7,s1 +8000d62c: 9b0ff06f j 8000c7dc <_vfiprintf_r+0x2f0> +8000d630: 00600d13 li s10,6 +8000d634: f49ff06f j 8000d57c <_vfiprintf_r+0x1090> +8000d638: 03b10793 addi a5,sp,59 +8000d63c: 04f12623 sw a5,76(sp) +8000d640: 00100793 li a5,1 +8000d644: 04f12823 sw a5,80(sp) +8000d648: 00100613 li a2,1 +8000d64c: 05410693 addi a3,sp,84 +8000d650: 918ff06f j 8000c768 <_vfiprintf_r+0x27c> +8000d654: 00c12783 lw a5,12(sp) +8000d658: 00f71023 sh a5,0(a4) +8000d65c: f91fe06f j 8000c5ec <_vfiprintf_r+0x100> +8000d660: 01012783 lw a5,16(sp) +8000d664: 00000c93 li s9,0 +8000d668: 00e12823 sw a4,16(sp) +8000d66c: 0007ad03 lw s10,0(a5) +8000d670: b84ff06f j 8000c9f4 <_vfiprintf_r+0x508> +8000d674: 01012783 lw a5,16(sp) +8000d678: 00000c93 li s9,0 8000d67c: 00e12823 sw a4,16(sp) -8000d680: 00078d03 lb s10,0(a5) -8000d684: 41fd5c93 srai s9,s10,0x1f -8000d688: 000c8713 mv a4,s9 -8000d68c: b68ff06f j 8000c9f4 <_vfiprintf_r+0x444> -8000d690: 200df793 andi a5,s11,512 -8000d694: 0a078263 beqz a5,8000d738 <_vfiprintf_r+0x1188> -8000d698: 01012783 lw a5,16(sp) -8000d69c: 00000c93 li s9,0 -8000d6a0: 00e12823 sw a4,16(sp) -8000d6a4: 0007cd03 lbu s10,0(a5) -8000d6a8: 00100713 li a4,1 -8000d6ac: c14ff06f j 8000cac0 <_vfiprintf_r+0x510> -8000d6b0: 200b7793 andi a5,s6,512 -8000d6b4: 06078863 beqz a5,8000d724 <_vfiprintf_r+0x1174> -8000d6b8: 01012783 lw a5,16(sp) -8000d6bc: 00000c93 li s9,0 -8000d6c0: 00e12823 sw a4,16(sp) -8000d6c4: 0007cd03 lbu s10,0(a5) -8000d6c8: bf0ff06f j 8000cab8 <_vfiprintf_r+0x508> -8000d6cc: 00068593 mv a1,a3 -8000d6d0: 8d5ff06f j 8000cfa4 <_vfiprintf_r+0x9f4> -8000d6d4: 00900793 li a5,9 -8000d6d8: cf37e2e3 bltu a5,s3,8000d3bc <_vfiprintf_r+0xe0c> -8000d6dc: d2dff06f j 8000d408 <_vfiprintf_r+0xe58> -8000d6e0: 05410693 addi a3,sp,84 -8000d6e4: 00100613 li a2,1 -8000d6e8: 00000713 li a4,0 -8000d6ec: 00048b93 mv s7,s1 -8000d6f0: 9b0ff06f j 8000c8a0 <_vfiprintf_r+0x2f0> -8000d6f4: 00600d13 li s10,6 -8000d6f8: f49ff06f j 8000d640 <_vfiprintf_r+0x1090> -8000d6fc: 03b10793 addi a5,sp,59 -8000d700: 04f12623 sw a5,76(sp) -8000d704: 00100793 li a5,1 -8000d708: 04f12823 sw a5,80(sp) -8000d70c: 00100613 li a2,1 -8000d710: 05410693 addi a3,sp,84 -8000d714: 918ff06f j 8000c82c <_vfiprintf_r+0x27c> -8000d718: 00c12783 lw a5,12(sp) -8000d71c: 00f71023 sh a5,0(a4) -8000d720: f91fe06f j 8000c6b0 <_vfiprintf_r+0x100> -8000d724: 01012783 lw a5,16(sp) -8000d728: 00000c93 li s9,0 -8000d72c: 00e12823 sw a4,16(sp) -8000d730: 0007ad03 lw s10,0(a5) -8000d734: b84ff06f j 8000cab8 <_vfiprintf_r+0x508> -8000d738: 01012783 lw a5,16(sp) -8000d73c: 00000c93 li s9,0 -8000d740: 00e12823 sw a4,16(sp) -8000d744: 0007ad03 lw s10,0(a5) -8000d748: 00100713 li a4,1 -8000d74c: b74ff06f j 8000cac0 <_vfiprintf_r+0x510> -8000d750: 01012783 lw a5,16(sp) -8000d754: 00e12823 sw a4,16(sp) -8000d758: 0007ad03 lw s10,0(a5) -8000d75c: 41fd5c93 srai s9,s10,0x1f -8000d760: 000c8713 mv a4,s9 -8000d764: a90ff06f j 8000c9f4 <_vfiprintf_r+0x444> -8000d768: 01012783 lw a5,16(sp) -8000d76c: 00000c93 li s9,0 -8000d770: 00d12823 sw a3,16(sp) -8000d774: 0007ad03 lw s10,0(a5) -8000d778: d75ff06f j 8000d4ec <_vfiprintf_r+0xf3c> -8000d77c: 04010613 addi a2,sp,64 -8000d780: 00098593 mv a1,s3 -8000d784: 000a0513 mv a0,s4 -8000d788: d21fe0ef jal ra,8000c4a8 <__sprint_r.part.0> -8000d78c: 9a0ff06f j 8000c92c <_vfiprintf_r+0x37c> -8000d790: 000a8d13 mv s10,s5 -8000d794: 01b12823 sw s11,16(sp) -8000d798: 00000a93 li s5,0 -8000d79c: a94ff06f j 8000ca30 <_vfiprintf_r+0x480> -8000d7a0: 00068593 mv a1,a3 -8000d7a4: 99dff06f j 8000d140 <_vfiprintf_r+0xb90> -8000d7a8: 00160593 addi a1,a2,1 -8000d7ac: a71ff06f j 8000d21c <_vfiprintf_r+0xc6c> -8000d7b0: 000b0d93 mv s11,s6 -8000d7b4: a68ff06f j 8000ca1c <_vfiprintf_r+0x46c> -8000d7b8: fff00793 li a5,-1 -8000d7bc: 00f12623 sw a5,12(sp) -8000d7c0: 978ff06f j 8000c938 <_vfiprintf_r+0x388> -8000d7c4: 00068513 mv a0,a3 -8000d7c8: 00060593 mv a1,a2 -8000d7cc: f0cff06f j 8000ced8 <_vfiprintf_r+0x928> -8000d7d0: 01012783 lw a5,16(sp) -8000d7d4: 0007aa83 lw s5,0(a5) -8000d7d8: 00478793 addi a5,a5,4 -8000d7dc: 000ad463 bgez s5,8000d7e4 <_vfiprintf_r+0x1234> -8000d7e0: fff00a93 li s5,-1 -8000d7e4: 001c4703 lbu a4,1(s8) -8000d7e8: 00f12823 sw a5,16(sp) -8000d7ec: 00068c13 mv s8,a3 -8000d7f0: f69fe06f j 8000c758 <_vfiprintf_r+0x1a8> +8000d680: 0007ad03 lw s10,0(a5) +8000d684: 00100713 li a4,1 +8000d688: b74ff06f j 8000c9fc <_vfiprintf_r+0x510> +8000d68c: 01012783 lw a5,16(sp) +8000d690: 00e12823 sw a4,16(sp) +8000d694: 0007ad03 lw s10,0(a5) +8000d698: 41fd5c93 srai s9,s10,0x1f +8000d69c: 000c8713 mv a4,s9 +8000d6a0: a90ff06f j 8000c930 <_vfiprintf_r+0x444> +8000d6a4: 01012783 lw a5,16(sp) +8000d6a8: 00000c93 li s9,0 +8000d6ac: 00d12823 sw a3,16(sp) +8000d6b0: 0007ad03 lw s10,0(a5) +8000d6b4: d75ff06f j 8000d428 <_vfiprintf_r+0xf3c> +8000d6b8: 04010613 addi a2,sp,64 +8000d6bc: 00098593 mv a1,s3 +8000d6c0: 000a0513 mv a0,s4 +8000d6c4: d21fe0ef jal ra,8000c3e4 <__sprint_r.part.0> +8000d6c8: 9a0ff06f j 8000c868 <_vfiprintf_r+0x37c> +8000d6cc: 000a8d13 mv s10,s5 +8000d6d0: 01b12823 sw s11,16(sp) +8000d6d4: 00000a93 li s5,0 +8000d6d8: a94ff06f j 8000c96c <_vfiprintf_r+0x480> +8000d6dc: 00068593 mv a1,a3 +8000d6e0: 99dff06f j 8000d07c <_vfiprintf_r+0xb90> +8000d6e4: 00160593 addi a1,a2,1 +8000d6e8: a71ff06f j 8000d158 <_vfiprintf_r+0xc6c> +8000d6ec: 000b0d93 mv s11,s6 +8000d6f0: a68ff06f j 8000c958 <_vfiprintf_r+0x46c> +8000d6f4: fff00793 li a5,-1 +8000d6f8: 00f12623 sw a5,12(sp) +8000d6fc: 978ff06f j 8000c874 <_vfiprintf_r+0x388> +8000d700: 00068513 mv a0,a3 +8000d704: 00060593 mv a1,a2 +8000d708: f0cff06f j 8000ce14 <_vfiprintf_r+0x928> +8000d70c: 01012783 lw a5,16(sp) +8000d710: 0007aa83 lw s5,0(a5) +8000d714: 00478793 addi a5,a5,4 +8000d718: 000ad463 bgez s5,8000d720 <_vfiprintf_r+0x1234> +8000d71c: fff00a93 li s5,-1 +8000d720: 001c4703 lbu a4,1(s8) +8000d724: 00f12823 sw a5,16(sp) +8000d728: 00068c13 mv s8,a3 +8000d72c: f69fe06f j 8000c694 <_vfiprintf_r+0x1a8> -8000d7f4 : -8000d7f4: 00050793 mv a5,a0 -8000d7f8: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -8000d7fc: 00060693 mv a3,a2 -8000d800: 00058613 mv a2,a1 -8000d804: 00078593 mv a1,a5 -8000d808: da9fe06f j 8000c5b0 <_vfiprintf_r> +8000d730 : +8000d730: 00050793 mv a5,a0 +8000d734: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +8000d738: 00060693 mv a3,a2 +8000d73c: 00058613 mv a2,a1 +8000d740: 00078593 mv a1,a5 +8000d744: da9fe06f j 8000c4ec <_vfiprintf_r> -8000d80c <__sbprintf>: -8000d80c: 00c5d783 lhu a5,12(a1) -8000d810: 0645ae03 lw t3,100(a1) -8000d814: 00e5d303 lhu t1,14(a1) -8000d818: 01c5a883 lw a7,28(a1) -8000d81c: 0245a803 lw a6,36(a1) -8000d820: b8010113 addi sp,sp,-1152 -8000d824: ffd7f793 andi a5,a5,-3 -8000d828: 40000713 li a4,1024 -8000d82c: 46812c23 sw s0,1144(sp) -8000d830: 00f11a23 sh a5,20(sp) -8000d834: 00058413 mv s0,a1 -8000d838: 07010793 addi a5,sp,112 -8000d83c: 00810593 addi a1,sp,8 -8000d840: 46912a23 sw s1,1140(sp) -8000d844: 47212823 sw s2,1136(sp) -8000d848: 46112e23 sw ra,1148(sp) -8000d84c: 00050913 mv s2,a0 -8000d850: 07c12623 sw t3,108(sp) -8000d854: 00611b23 sh t1,22(sp) -8000d858: 03112223 sw a7,36(sp) -8000d85c: 03012623 sw a6,44(sp) -8000d860: 00f12423 sw a5,8(sp) -8000d864: 00f12c23 sw a5,24(sp) -8000d868: 00e12823 sw a4,16(sp) -8000d86c: 00e12e23 sw a4,28(sp) -8000d870: 02012023 sw zero,32(sp) -8000d874: d3dfe0ef jal ra,8000c5b0 <_vfiprintf_r> -8000d878: 00050493 mv s1,a0 -8000d87c: 02055c63 bgez a0,8000d8b4 <__sbprintf+0xa8> -8000d880: 01415783 lhu a5,20(sp) -8000d884: 0407f793 andi a5,a5,64 -8000d888: 00078863 beqz a5,8000d898 <__sbprintf+0x8c> -8000d88c: 00c45783 lhu a5,12(s0) -8000d890: 0407e793 ori a5,a5,64 -8000d894: 00f41623 sh a5,12(s0) -8000d898: 47c12083 lw ra,1148(sp) -8000d89c: 47812403 lw s0,1144(sp) -8000d8a0: 47012903 lw s2,1136(sp) -8000d8a4: 00048513 mv a0,s1 -8000d8a8: 47412483 lw s1,1140(sp) -8000d8ac: 48010113 addi sp,sp,1152 -8000d8b0: 00008067 ret -8000d8b4: 00810593 addi a1,sp,8 -8000d8b8: 00090513 mv a0,s2 -8000d8bc: bb1f60ef jal ra,8000446c <_fflush_r> -8000d8c0: fc0500e3 beqz a0,8000d880 <__sbprintf+0x74> -8000d8c4: fff00493 li s1,-1 -8000d8c8: fb9ff06f j 8000d880 <__sbprintf+0x74> +8000d748 <__sbprintf>: +8000d748: 00c5d783 lhu a5,12(a1) +8000d74c: 0645ae03 lw t3,100(a1) +8000d750: 00e5d303 lhu t1,14(a1) +8000d754: 01c5a883 lw a7,28(a1) +8000d758: 0245a803 lw a6,36(a1) +8000d75c: b8010113 addi sp,sp,-1152 +8000d760: ffd7f793 andi a5,a5,-3 +8000d764: 40000713 li a4,1024 +8000d768: 46812c23 sw s0,1144(sp) +8000d76c: 00f11a23 sh a5,20(sp) +8000d770: 00058413 mv s0,a1 +8000d774: 07010793 addi a5,sp,112 +8000d778: 00810593 addi a1,sp,8 +8000d77c: 46912a23 sw s1,1140(sp) +8000d780: 47212823 sw s2,1136(sp) +8000d784: 46112e23 sw ra,1148(sp) +8000d788: 00050913 mv s2,a0 +8000d78c: 07c12623 sw t3,108(sp) +8000d790: 00611b23 sh t1,22(sp) +8000d794: 03112223 sw a7,36(sp) +8000d798: 03012623 sw a6,44(sp) +8000d79c: 00f12423 sw a5,8(sp) +8000d7a0: 00f12c23 sw a5,24(sp) +8000d7a4: 00e12823 sw a4,16(sp) +8000d7a8: 00e12e23 sw a4,28(sp) +8000d7ac: 02012023 sw zero,32(sp) +8000d7b0: d3dfe0ef jal ra,8000c4ec <_vfiprintf_r> +8000d7b4: 00050493 mv s1,a0 +8000d7b8: 02055c63 bgez a0,8000d7f0 <__sbprintf+0xa8> +8000d7bc: 01415783 lhu a5,20(sp) +8000d7c0: 0407f793 andi a5,a5,64 +8000d7c4: 00078863 beqz a5,8000d7d4 <__sbprintf+0x8c> +8000d7c8: 00c45783 lhu a5,12(s0) +8000d7cc: 0407e793 ori a5,a5,64 +8000d7d0: 00f41623 sh a5,12(s0) +8000d7d4: 47c12083 lw ra,1148(sp) +8000d7d8: 47812403 lw s0,1144(sp) +8000d7dc: 47012903 lw s2,1136(sp) +8000d7e0: 00048513 mv a0,s1 +8000d7e4: 47412483 lw s1,1140(sp) +8000d7e8: 48010113 addi sp,sp,1152 +8000d7ec: 00008067 ret +8000d7f0: 00810593 addi a1,sp,8 +8000d7f4: 00090513 mv a0,s2 +8000d7f8: bb1f60ef jal ra,800043a8 <_fflush_r> +8000d7fc: fc0500e3 beqz a0,8000d7bc <__sbprintf+0x74> +8000d800: fff00493 li s1,-1 +8000d804: fb9ff06f j 8000d7bc <__sbprintf+0x74> -8000d8cc <_write_r>: -8000d8cc: ff010113 addi sp,sp,-16 -8000d8d0: 00058713 mv a4,a1 -8000d8d4: 00812423 sw s0,8(sp) -8000d8d8: 00912223 sw s1,4(sp) -8000d8dc: 00060593 mv a1,a2 -8000d8e0: 00050413 mv s0,a0 -8000d8e4: 00068613 mv a2,a3 -8000d8e8: 00070513 mv a0,a4 -8000d8ec: 00112623 sw ra,12(sp) -8000d8f0: 4201a823 sw zero,1072(gp) # 80016c38 -8000d8f4: b89f20ef jal ra,8000047c <_write> -8000d8f8: fff00793 li a5,-1 -8000d8fc: 00f50c63 beq a0,a5,8000d914 <_write_r+0x48> -8000d900: 00c12083 lw ra,12(sp) -8000d904: 00812403 lw s0,8(sp) -8000d908: 00412483 lw s1,4(sp) -8000d90c: 01010113 addi sp,sp,16 -8000d910: 00008067 ret -8000d914: 4301a783 lw a5,1072(gp) # 80016c38 -8000d918: fe0784e3 beqz a5,8000d900 <_write_r+0x34> -8000d91c: 00c12083 lw ra,12(sp) -8000d920: 00f42023 sw a5,0(s0) -8000d924: 00812403 lw s0,8(sp) -8000d928: 00412483 lw s1,4(sp) -8000d92c: 01010113 addi sp,sp,16 -8000d930: 00008067 ret +8000d808 <_write_r>: +8000d808: ff010113 addi sp,sp,-16 +8000d80c: 00058713 mv a4,a1 +8000d810: 00812423 sw s0,8(sp) +8000d814: 00912223 sw s1,4(sp) +8000d818: 00060593 mv a1,a2 +8000d81c: 00050413 mv s0,a0 +8000d820: 00068613 mv a2,a3 +8000d824: 00070513 mv a0,a4 +8000d828: 00112623 sw ra,12(sp) +8000d82c: 4201a823 sw zero,1072(gp) # 80016c38 +8000d830: c55f20ef jal ra,80000484 <_write> +8000d834: fff00793 li a5,-1 +8000d838: 00f50c63 beq a0,a5,8000d850 <_write_r+0x48> +8000d83c: 00c12083 lw ra,12(sp) +8000d840: 00812403 lw s0,8(sp) +8000d844: 00412483 lw s1,4(sp) +8000d848: 01010113 addi sp,sp,16 +8000d84c: 00008067 ret +8000d850: 4301a783 lw a5,1072(gp) # 80016c38 +8000d854: fe0784e3 beqz a5,8000d83c <_write_r+0x34> +8000d858: 00c12083 lw ra,12(sp) +8000d85c: 00f42023 sw a5,0(s0) +8000d860: 00812403 lw s0,8(sp) +8000d864: 00412483 lw s1,4(sp) +8000d868: 01010113 addi sp,sp,16 +8000d86c: 00008067 ret -8000d934 <__register_exitproc>: -8000d934: 3501a703 lw a4,848(gp) # 80016b58 <_global_impure_ptr> -8000d938: 14872783 lw a5,328(a4) -8000d93c: 04078c63 beqz a5,8000d994 <__register_exitproc+0x60> -8000d940: 0047a703 lw a4,4(a5) -8000d944: 01f00813 li a6,31 -8000d948: 06e84e63 blt a6,a4,8000d9c4 <__register_exitproc+0x90> -8000d94c: 00271813 slli a6,a4,0x2 -8000d950: 02050663 beqz a0,8000d97c <__register_exitproc+0x48> -8000d954: 01078333 add t1,a5,a6 -8000d958: 08c32423 sw a2,136(t1) -8000d95c: 1887a883 lw a7,392(a5) -8000d960: 00100613 li a2,1 -8000d964: 00e61633 sll a2,a2,a4 -8000d968: 00c8e8b3 or a7,a7,a2 -8000d96c: 1917a423 sw a7,392(a5) -8000d970: 10d32423 sw a3,264(t1) -8000d974: 00200693 li a3,2 -8000d978: 02d50463 beq a0,a3,8000d9a0 <__register_exitproc+0x6c> -8000d97c: 00170713 addi a4,a4,1 -8000d980: 00e7a223 sw a4,4(a5) -8000d984: 010787b3 add a5,a5,a6 -8000d988: 00b7a423 sw a1,8(a5) -8000d98c: 00000513 li a0,0 -8000d990: 00008067 ret -8000d994: 14c70793 addi a5,a4,332 -8000d998: 14f72423 sw a5,328(a4) -8000d99c: fa5ff06f j 8000d940 <__register_exitproc+0xc> -8000d9a0: 18c7a683 lw a3,396(a5) -8000d9a4: 00170713 addi a4,a4,1 -8000d9a8: 00e7a223 sw a4,4(a5) -8000d9ac: 00c6e633 or a2,a3,a2 -8000d9b0: 18c7a623 sw a2,396(a5) -8000d9b4: 010787b3 add a5,a5,a6 -8000d9b8: 00b7a423 sw a1,8(a5) -8000d9bc: 00000513 li a0,0 -8000d9c0: 00008067 ret -8000d9c4: fff00513 li a0,-1 -8000d9c8: 00008067 ret +8000d870 <__register_exitproc>: +8000d870: 3501a703 lw a4,848(gp) # 80016b58 <_global_impure_ptr> +8000d874: 14872783 lw a5,328(a4) +8000d878: 04078c63 beqz a5,8000d8d0 <__register_exitproc+0x60> +8000d87c: 0047a703 lw a4,4(a5) +8000d880: 01f00813 li a6,31 +8000d884: 06e84e63 blt a6,a4,8000d900 <__register_exitproc+0x90> +8000d888: 00271813 slli a6,a4,0x2 +8000d88c: 02050663 beqz a0,8000d8b8 <__register_exitproc+0x48> +8000d890: 01078333 add t1,a5,a6 +8000d894: 08c32423 sw a2,136(t1) +8000d898: 1887a883 lw a7,392(a5) +8000d89c: 00100613 li a2,1 +8000d8a0: 00e61633 sll a2,a2,a4 +8000d8a4: 00c8e8b3 or a7,a7,a2 +8000d8a8: 1917a423 sw a7,392(a5) +8000d8ac: 10d32423 sw a3,264(t1) +8000d8b0: 00200693 li a3,2 +8000d8b4: 02d50463 beq a0,a3,8000d8dc <__register_exitproc+0x6c> +8000d8b8: 00170713 addi a4,a4,1 +8000d8bc: 00e7a223 sw a4,4(a5) +8000d8c0: 010787b3 add a5,a5,a6 +8000d8c4: 00b7a423 sw a1,8(a5) +8000d8c8: 00000513 li a0,0 +8000d8cc: 00008067 ret +8000d8d0: 14c70793 addi a5,a4,332 +8000d8d4: 14f72423 sw a5,328(a4) +8000d8d8: fa5ff06f j 8000d87c <__register_exitproc+0xc> +8000d8dc: 18c7a683 lw a3,396(a5) +8000d8e0: 00170713 addi a4,a4,1 +8000d8e4: 00e7a223 sw a4,4(a5) +8000d8e8: 00c6e633 or a2,a3,a2 +8000d8ec: 18c7a623 sw a2,396(a5) +8000d8f0: 010787b3 add a5,a5,a6 +8000d8f4: 00b7a423 sw a1,8(a5) +8000d8f8: 00000513 li a0,0 +8000d8fc: 00008067 ret +8000d900: fff00513 li a0,-1 +8000d904: 00008067 ret -8000d9cc <_calloc_r>: -8000d9cc: 02c585b3 mul a1,a1,a2 -8000d9d0: ff010113 addi sp,sp,-16 -8000d9d4: 00812423 sw s0,8(sp) -8000d9d8: 00112623 sw ra,12(sp) -8000d9dc: 9ccfa0ef jal ra,80007ba8 <_malloc_r> -8000d9e0: 00050413 mv s0,a0 -8000d9e4: 02050863 beqz a0,8000da14 <_calloc_r+0x48> -8000d9e8: ffc52603 lw a2,-4(a0) -8000d9ec: 02400713 li a4,36 -8000d9f0: ffc67613 andi a2,a2,-4 -8000d9f4: ffc60613 addi a2,a2,-4 -8000d9f8: 06c76063 bltu a4,a2,8000da58 <_calloc_r+0x8c> -8000d9fc: 01300693 li a3,19 -8000da00: 00050793 mv a5,a0 -8000da04: 02c6e263 bltu a3,a2,8000da28 <_calloc_r+0x5c> -8000da08: 0007a023 sw zero,0(a5) -8000da0c: 0007a223 sw zero,4(a5) -8000da10: 0007a423 sw zero,8(a5) -8000da14: 00c12083 lw ra,12(sp) -8000da18: 00040513 mv a0,s0 -8000da1c: 00812403 lw s0,8(sp) -8000da20: 01010113 addi sp,sp,16 -8000da24: 00008067 ret -8000da28: 00052023 sw zero,0(a0) -8000da2c: 00052223 sw zero,4(a0) -8000da30: 01b00793 li a5,27 -8000da34: 04c7f063 bgeu a5,a2,8000da74 <_calloc_r+0xa8> -8000da38: 00052423 sw zero,8(a0) -8000da3c: 00052623 sw zero,12(a0) -8000da40: 01050793 addi a5,a0,16 -8000da44: fce612e3 bne a2,a4,8000da08 <_calloc_r+0x3c> -8000da48: 00052823 sw zero,16(a0) -8000da4c: 01850793 addi a5,a0,24 -8000da50: 00052a23 sw zero,20(a0) -8000da54: fb5ff06f j 8000da08 <_calloc_r+0x3c> -8000da58: 00000593 li a1,0 -8000da5c: 9b9fa0ef jal ra,80008414 -8000da60: 00c12083 lw ra,12(sp) -8000da64: 00040513 mv a0,s0 -8000da68: 00812403 lw s0,8(sp) -8000da6c: 01010113 addi sp,sp,16 -8000da70: 00008067 ret -8000da74: 00850793 addi a5,a0,8 -8000da78: f91ff06f j 8000da08 <_calloc_r+0x3c> +8000d908 <_calloc_r>: +8000d908: 02c585b3 mul a1,a1,a2 +8000d90c: ff010113 addi sp,sp,-16 +8000d910: 00812423 sw s0,8(sp) +8000d914: 00112623 sw ra,12(sp) +8000d918: 9ccfa0ef jal ra,80007ae4 <_malloc_r> +8000d91c: 00050413 mv s0,a0 +8000d920: 02050863 beqz a0,8000d950 <_calloc_r+0x48> +8000d924: ffc52603 lw a2,-4(a0) +8000d928: 02400713 li a4,36 +8000d92c: ffc67613 andi a2,a2,-4 +8000d930: ffc60613 addi a2,a2,-4 +8000d934: 06c76063 bltu a4,a2,8000d994 <_calloc_r+0x8c> +8000d938: 01300693 li a3,19 +8000d93c: 00050793 mv a5,a0 +8000d940: 02c6e263 bltu a3,a2,8000d964 <_calloc_r+0x5c> +8000d944: 0007a023 sw zero,0(a5) +8000d948: 0007a223 sw zero,4(a5) +8000d94c: 0007a423 sw zero,8(a5) +8000d950: 00c12083 lw ra,12(sp) +8000d954: 00040513 mv a0,s0 +8000d958: 00812403 lw s0,8(sp) +8000d95c: 01010113 addi sp,sp,16 +8000d960: 00008067 ret +8000d964: 00052023 sw zero,0(a0) +8000d968: 00052223 sw zero,4(a0) +8000d96c: 01b00793 li a5,27 +8000d970: 04c7f063 bgeu a5,a2,8000d9b0 <_calloc_r+0xa8> +8000d974: 00052423 sw zero,8(a0) +8000d978: 00052623 sw zero,12(a0) +8000d97c: 01050793 addi a5,a0,16 +8000d980: fce612e3 bne a2,a4,8000d944 <_calloc_r+0x3c> +8000d984: 00052823 sw zero,16(a0) +8000d988: 01850793 addi a5,a0,24 +8000d98c: 00052a23 sw zero,20(a0) +8000d990: fb5ff06f j 8000d944 <_calloc_r+0x3c> +8000d994: 00000593 li a1,0 +8000d998: 9b9fa0ef jal ra,80008350 +8000d99c: 00c12083 lw ra,12(sp) +8000d9a0: 00040513 mv a0,s0 +8000d9a4: 00812403 lw s0,8(sp) +8000d9a8: 01010113 addi sp,sp,16 +8000d9ac: 00008067 ret +8000d9b0: 00850793 addi a5,a0,8 +8000d9b4: f91ff06f j 8000d944 <_calloc_r+0x3c> -8000da7c <_close_r>: -8000da7c: ff010113 addi sp,sp,-16 -8000da80: 00812423 sw s0,8(sp) -8000da84: 00912223 sw s1,4(sp) -8000da88: 00050413 mv s0,a0 -8000da8c: 00058513 mv a0,a1 -8000da90: 00112623 sw ra,12(sp) -8000da94: 4201a823 sw zero,1072(gp) # 80016c38 -8000da98: ff4f20ef jal ra,8000028c <_close> -8000da9c: fff00793 li a5,-1 -8000daa0: 00f50c63 beq a0,a5,8000dab8 <_close_r+0x3c> -8000daa4: 00c12083 lw ra,12(sp) -8000daa8: 00812403 lw s0,8(sp) -8000daac: 00412483 lw s1,4(sp) -8000dab0: 01010113 addi sp,sp,16 -8000dab4: 00008067 ret -8000dab8: 4301a783 lw a5,1072(gp) # 80016c38 -8000dabc: fe0784e3 beqz a5,8000daa4 <_close_r+0x28> -8000dac0: 00c12083 lw ra,12(sp) -8000dac4: 00f42023 sw a5,0(s0) -8000dac8: 00812403 lw s0,8(sp) -8000dacc: 00412483 lw s1,4(sp) -8000dad0: 01010113 addi sp,sp,16 -8000dad4: 00008067 ret +8000d9b8 <_close_r>: +8000d9b8: ff010113 addi sp,sp,-16 +8000d9bc: 00812423 sw s0,8(sp) +8000d9c0: 00912223 sw s1,4(sp) +8000d9c4: 00050413 mv s0,a0 +8000d9c8: 00058513 mv a0,a1 +8000d9cc: 00112623 sw ra,12(sp) +8000d9d0: 4201a823 sw zero,1072(gp) # 80016c38 +8000d9d4: 8c1f20ef jal ra,80000294 <_close> +8000d9d8: fff00793 li a5,-1 +8000d9dc: 00f50c63 beq a0,a5,8000d9f4 <_close_r+0x3c> +8000d9e0: 00c12083 lw ra,12(sp) +8000d9e4: 00812403 lw s0,8(sp) +8000d9e8: 00412483 lw s1,4(sp) +8000d9ec: 01010113 addi sp,sp,16 +8000d9f0: 00008067 ret +8000d9f4: 4301a783 lw a5,1072(gp) # 80016c38 +8000d9f8: fe0784e3 beqz a5,8000d9e0 <_close_r+0x28> +8000d9fc: 00c12083 lw ra,12(sp) +8000da00: 00f42023 sw a5,0(s0) +8000da04: 00812403 lw s0,8(sp) +8000da08: 00412483 lw s1,4(sp) +8000da0c: 01010113 addi sp,sp,16 +8000da10: 00008067 ret -8000dad8 <_fclose_r>: -8000dad8: ff010113 addi sp,sp,-16 -8000dadc: 00112623 sw ra,12(sp) -8000dae0: 00812423 sw s0,8(sp) -8000dae4: 00912223 sw s1,4(sp) -8000dae8: 01212023 sw s2,0(sp) -8000daec: 02058063 beqz a1,8000db0c <_fclose_r+0x34> -8000daf0: 00058413 mv s0,a1 -8000daf4: 00050493 mv s1,a0 -8000daf8: 00050663 beqz a0,8000db04 <_fclose_r+0x2c> -8000dafc: 03852783 lw a5,56(a0) -8000db00: 0a078c63 beqz a5,8000dbb8 <_fclose_r+0xe0> -8000db04: 00c41783 lh a5,12(s0) -8000db08: 02079263 bnez a5,8000db2c <_fclose_r+0x54> -8000db0c: 00c12083 lw ra,12(sp) -8000db10: 00812403 lw s0,8(sp) -8000db14: 00000913 li s2,0 -8000db18: 00412483 lw s1,4(sp) -8000db1c: 00090513 mv a0,s2 -8000db20: 00012903 lw s2,0(sp) -8000db24: 01010113 addi sp,sp,16 -8000db28: 00008067 ret -8000db2c: 00040593 mv a1,s0 -8000db30: 00048513 mv a0,s1 -8000db34: edcf60ef jal ra,80004210 <__sflush_r> -8000db38: 02c42783 lw a5,44(s0) -8000db3c: 00050913 mv s2,a0 -8000db40: 00078a63 beqz a5,8000db54 <_fclose_r+0x7c> -8000db44: 01c42583 lw a1,28(s0) -8000db48: 00048513 mv a0,s1 -8000db4c: 000780e7 jalr a5 -8000db50: 06054c63 bltz a0,8000dbc8 <_fclose_r+0xf0> -8000db54: 00c45783 lhu a5,12(s0) -8000db58: 0807f793 andi a5,a5,128 -8000db5c: 06079e63 bnez a5,8000dbd8 <_fclose_r+0x100> -8000db60: 03042583 lw a1,48(s0) -8000db64: 00058c63 beqz a1,8000db7c <_fclose_r+0xa4> -8000db68: 04040793 addi a5,s0,64 -8000db6c: 00f58663 beq a1,a5,8000db78 <_fclose_r+0xa0> -8000db70: 00048513 mv a0,s1 -8000db74: e61f60ef jal ra,800049d4 <_free_r> -8000db78: 02042823 sw zero,48(s0) -8000db7c: 04442583 lw a1,68(s0) -8000db80: 00058863 beqz a1,8000db90 <_fclose_r+0xb8> -8000db84: 00048513 mv a0,s1 -8000db88: e4df60ef jal ra,800049d4 <_free_r> -8000db8c: 04042223 sw zero,68(s0) -8000db90: c89f60ef jal ra,80004818 <__sfp_lock_acquire> -8000db94: 00041623 sh zero,12(s0) -8000db98: c85f60ef jal ra,8000481c <__sfp_lock_release> -8000db9c: 00c12083 lw ra,12(sp) -8000dba0: 00812403 lw s0,8(sp) -8000dba4: 00412483 lw s1,4(sp) -8000dba8: 00090513 mv a0,s2 -8000dbac: 00012903 lw s2,0(sp) -8000dbb0: 01010113 addi sp,sp,16 -8000dbb4: 00008067 ret -8000dbb8: c51f60ef jal ra,80004808 <__sinit> -8000dbbc: 00c41783 lh a5,12(s0) -8000dbc0: f40786e3 beqz a5,8000db0c <_fclose_r+0x34> -8000dbc4: f69ff06f j 8000db2c <_fclose_r+0x54> -8000dbc8: 00c45783 lhu a5,12(s0) -8000dbcc: fff00913 li s2,-1 -8000dbd0: 0807f793 andi a5,a5,128 -8000dbd4: f80786e3 beqz a5,8000db60 <_fclose_r+0x88> -8000dbd8: 01042583 lw a1,16(s0) -8000dbdc: 00048513 mv a0,s1 -8000dbe0: df5f60ef jal ra,800049d4 <_free_r> -8000dbe4: f7dff06f j 8000db60 <_fclose_r+0x88> +8000da14 <_fclose_r>: +8000da14: ff010113 addi sp,sp,-16 +8000da18: 00112623 sw ra,12(sp) +8000da1c: 00812423 sw s0,8(sp) +8000da20: 00912223 sw s1,4(sp) +8000da24: 01212023 sw s2,0(sp) +8000da28: 02058063 beqz a1,8000da48 <_fclose_r+0x34> +8000da2c: 00058413 mv s0,a1 +8000da30: 00050493 mv s1,a0 +8000da34: 00050663 beqz a0,8000da40 <_fclose_r+0x2c> +8000da38: 03852783 lw a5,56(a0) +8000da3c: 0a078c63 beqz a5,8000daf4 <_fclose_r+0xe0> +8000da40: 00c41783 lh a5,12(s0) +8000da44: 02079263 bnez a5,8000da68 <_fclose_r+0x54> +8000da48: 00c12083 lw ra,12(sp) +8000da4c: 00812403 lw s0,8(sp) +8000da50: 00000913 li s2,0 +8000da54: 00412483 lw s1,4(sp) +8000da58: 00090513 mv a0,s2 +8000da5c: 00012903 lw s2,0(sp) +8000da60: 01010113 addi sp,sp,16 +8000da64: 00008067 ret +8000da68: 00040593 mv a1,s0 +8000da6c: 00048513 mv a0,s1 +8000da70: edcf60ef jal ra,8000414c <__sflush_r> +8000da74: 02c42783 lw a5,44(s0) +8000da78: 00050913 mv s2,a0 +8000da7c: 00078a63 beqz a5,8000da90 <_fclose_r+0x7c> +8000da80: 01c42583 lw a1,28(s0) +8000da84: 00048513 mv a0,s1 +8000da88: 000780e7 jalr a5 +8000da8c: 06054c63 bltz a0,8000db04 <_fclose_r+0xf0> +8000da90: 00c45783 lhu a5,12(s0) +8000da94: 0807f793 andi a5,a5,128 +8000da98: 06079e63 bnez a5,8000db14 <_fclose_r+0x100> +8000da9c: 03042583 lw a1,48(s0) +8000daa0: 00058c63 beqz a1,8000dab8 <_fclose_r+0xa4> +8000daa4: 04040793 addi a5,s0,64 +8000daa8: 00f58663 beq a1,a5,8000dab4 <_fclose_r+0xa0> +8000daac: 00048513 mv a0,s1 +8000dab0: e61f60ef jal ra,80004910 <_free_r> +8000dab4: 02042823 sw zero,48(s0) +8000dab8: 04442583 lw a1,68(s0) +8000dabc: 00058863 beqz a1,8000dacc <_fclose_r+0xb8> +8000dac0: 00048513 mv a0,s1 +8000dac4: e4df60ef jal ra,80004910 <_free_r> +8000dac8: 04042223 sw zero,68(s0) +8000dacc: c89f60ef jal ra,80004754 <__sfp_lock_acquire> +8000dad0: 00041623 sh zero,12(s0) +8000dad4: c85f60ef jal ra,80004758 <__sfp_lock_release> +8000dad8: 00c12083 lw ra,12(sp) +8000dadc: 00812403 lw s0,8(sp) +8000dae0: 00412483 lw s1,4(sp) +8000dae4: 00090513 mv a0,s2 +8000dae8: 00012903 lw s2,0(sp) +8000daec: 01010113 addi sp,sp,16 +8000daf0: 00008067 ret +8000daf4: c51f60ef jal ra,80004744 <__sinit> +8000daf8: 00c41783 lh a5,12(s0) +8000dafc: f40786e3 beqz a5,8000da48 <_fclose_r+0x34> +8000db00: f69ff06f j 8000da68 <_fclose_r+0x54> +8000db04: 00c45783 lhu a5,12(s0) +8000db08: fff00913 li s2,-1 +8000db0c: 0807f793 andi a5,a5,128 +8000db10: f80786e3 beqz a5,8000da9c <_fclose_r+0x88> +8000db14: 01042583 lw a1,16(s0) +8000db18: 00048513 mv a0,s1 +8000db1c: df5f60ef jal ra,80004910 <_free_r> +8000db20: f7dff06f j 8000da9c <_fclose_r+0x88> -8000dbe8 : -8000dbe8: 00050593 mv a1,a0 -8000dbec: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -8000dbf0: ee9ff06f j 8000dad8 <_fclose_r> +8000db24 : +8000db24: 00050593 mv a1,a0 +8000db28: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +8000db2c: ee9ff06f j 8000da14 <_fclose_r> -8000dbf4 <__fputwc>: -8000dbf4: fd010113 addi sp,sp,-48 -8000dbf8: 02812423 sw s0,40(sp) -8000dbfc: 01312e23 sw s3,28(sp) -8000dc00: 01612823 sw s6,16(sp) -8000dc04: 02112623 sw ra,44(sp) -8000dc08: 02912223 sw s1,36(sp) -8000dc0c: 03212023 sw s2,32(sp) -8000dc10: 01412c23 sw s4,24(sp) -8000dc14: 01512a23 sw s5,20(sp) -8000dc18: 00050b13 mv s6,a0 -8000dc1c: 00058993 mv s3,a1 -8000dc20: 00060413 mv s0,a2 -8000dc24: 788000ef jal ra,8000e3ac <__locale_mb_cur_max> -8000dc28: 00100793 li a5,1 -8000dc2c: 02f51063 bne a0,a5,8000dc4c <__fputwc+0x58> -8000dc30: fff98793 addi a5,s3,-1 -8000dc34: 0fe00713 li a4,254 -8000dc38: 00f76a63 bltu a4,a5,8000dc4c <__fputwc+0x58> -8000dc3c: 0ff9f713 andi a4,s3,255 -8000dc40: 00e10623 sb a4,12(sp) -8000dc44: 00100913 li s2,1 -8000dc48: 02c0006f j 8000dc74 <__fputwc+0x80> -8000dc4c: 05c40693 addi a3,s0,92 -8000dc50: 00098613 mv a2,s3 -8000dc54: 00c10593 addi a1,sp,12 -8000dc58: 000b0513 mv a0,s6 -8000dc5c: 730020ef jal ra,8001038c <_wcrtomb_r> -8000dc60: fff00793 li a5,-1 -8000dc64: 00050913 mv s2,a0 -8000dc68: 0af50463 beq a0,a5,8000dd10 <__fputwc+0x11c> -8000dc6c: 08050e63 beqz a0,8000dd08 <__fputwc+0x114> -8000dc70: 00c14703 lbu a4,12(sp) -8000dc74: 00000493 li s1,0 -8000dc78: fff00a13 li s4,-1 -8000dc7c: 00a00a93 li s5,10 -8000dc80: 0280006f j 8000dca8 <__fputwc+0xb4> -8000dc84: 00042783 lw a5,0(s0) -8000dc88: 00178693 addi a3,a5,1 -8000dc8c: 00d42023 sw a3,0(s0) -8000dc90: 00e78023 sb a4,0(a5) -8000dc94: 00148493 addi s1,s1,1 -8000dc98: 00c10793 addi a5,sp,12 -8000dc9c: 009787b3 add a5,a5,s1 -8000dca0: 0724f463 bgeu s1,s2,8000dd08 <__fputwc+0x114> -8000dca4: 0007c703 lbu a4,0(a5) -8000dca8: 00842783 lw a5,8(s0) -8000dcac: fff78793 addi a5,a5,-1 -8000dcb0: 00f42423 sw a5,8(s0) -8000dcb4: fc07d8e3 bgez a5,8000dc84 <__fputwc+0x90> -8000dcb8: 01842683 lw a3,24(s0) -8000dcbc: 00070593 mv a1,a4 -8000dcc0: 00040613 mv a2,s0 -8000dcc4: 000b0513 mv a0,s6 -8000dcc8: 00d7c463 blt a5,a3,8000dcd0 <__fputwc+0xdc> -8000dccc: fb571ce3 bne a4,s5,8000dc84 <__fputwc+0x90> -8000dcd0: 524020ef jal ra,800101f4 <__swbuf_r> -8000dcd4: fd4510e3 bne a0,s4,8000dc94 <__fputwc+0xa0> -8000dcd8: fff00913 li s2,-1 -8000dcdc: 02c12083 lw ra,44(sp) -8000dce0: 02812403 lw s0,40(sp) -8000dce4: 02412483 lw s1,36(sp) -8000dce8: 01c12983 lw s3,28(sp) -8000dcec: 01812a03 lw s4,24(sp) -8000dcf0: 01412a83 lw s5,20(sp) -8000dcf4: 01012b03 lw s6,16(sp) -8000dcf8: 00090513 mv a0,s2 -8000dcfc: 02012903 lw s2,32(sp) -8000dd00: 03010113 addi sp,sp,48 -8000dd04: 00008067 ret -8000dd08: 00098913 mv s2,s3 -8000dd0c: fd1ff06f j 8000dcdc <__fputwc+0xe8> -8000dd10: 00c45783 lhu a5,12(s0) -8000dd14: 0407e793 ori a5,a5,64 -8000dd18: 00f41623 sh a5,12(s0) -8000dd1c: fc1ff06f j 8000dcdc <__fputwc+0xe8> +8000db30 <__fputwc>: +8000db30: fd010113 addi sp,sp,-48 +8000db34: 02812423 sw s0,40(sp) +8000db38: 01312e23 sw s3,28(sp) +8000db3c: 01612823 sw s6,16(sp) +8000db40: 02112623 sw ra,44(sp) +8000db44: 02912223 sw s1,36(sp) +8000db48: 03212023 sw s2,32(sp) +8000db4c: 01412c23 sw s4,24(sp) +8000db50: 01512a23 sw s5,20(sp) +8000db54: 00050b13 mv s6,a0 +8000db58: 00058993 mv s3,a1 +8000db5c: 00060413 mv s0,a2 +8000db60: 788000ef jal ra,8000e2e8 <__locale_mb_cur_max> +8000db64: 00100793 li a5,1 +8000db68: 02f51063 bne a0,a5,8000db88 <__fputwc+0x58> +8000db6c: fff98793 addi a5,s3,-1 +8000db70: 0fe00713 li a4,254 +8000db74: 00f76a63 bltu a4,a5,8000db88 <__fputwc+0x58> +8000db78: 0ff9f713 andi a4,s3,255 +8000db7c: 00e10623 sb a4,12(sp) +8000db80: 00100913 li s2,1 +8000db84: 02c0006f j 8000dbb0 <__fputwc+0x80> +8000db88: 05c40693 addi a3,s0,92 +8000db8c: 00098613 mv a2,s3 +8000db90: 00c10593 addi a1,sp,12 +8000db94: 000b0513 mv a0,s6 +8000db98: 730020ef jal ra,800102c8 <_wcrtomb_r> +8000db9c: fff00793 li a5,-1 +8000dba0: 00050913 mv s2,a0 +8000dba4: 0af50463 beq a0,a5,8000dc4c <__fputwc+0x11c> +8000dba8: 08050e63 beqz a0,8000dc44 <__fputwc+0x114> +8000dbac: 00c14703 lbu a4,12(sp) +8000dbb0: 00000493 li s1,0 +8000dbb4: fff00a13 li s4,-1 +8000dbb8: 00a00a93 li s5,10 +8000dbbc: 0280006f j 8000dbe4 <__fputwc+0xb4> +8000dbc0: 00042783 lw a5,0(s0) +8000dbc4: 00178693 addi a3,a5,1 +8000dbc8: 00d42023 sw a3,0(s0) +8000dbcc: 00e78023 sb a4,0(a5) +8000dbd0: 00148493 addi s1,s1,1 +8000dbd4: 00c10793 addi a5,sp,12 +8000dbd8: 009787b3 add a5,a5,s1 +8000dbdc: 0724f463 bgeu s1,s2,8000dc44 <__fputwc+0x114> +8000dbe0: 0007c703 lbu a4,0(a5) +8000dbe4: 00842783 lw a5,8(s0) +8000dbe8: fff78793 addi a5,a5,-1 +8000dbec: 00f42423 sw a5,8(s0) +8000dbf0: fc07d8e3 bgez a5,8000dbc0 <__fputwc+0x90> +8000dbf4: 01842683 lw a3,24(s0) +8000dbf8: 00070593 mv a1,a4 +8000dbfc: 00040613 mv a2,s0 +8000dc00: 000b0513 mv a0,s6 +8000dc04: 00d7c463 blt a5,a3,8000dc0c <__fputwc+0xdc> +8000dc08: fb571ce3 bne a4,s5,8000dbc0 <__fputwc+0x90> +8000dc0c: 524020ef jal ra,80010130 <__swbuf_r> +8000dc10: fd4510e3 bne a0,s4,8000dbd0 <__fputwc+0xa0> +8000dc14: fff00913 li s2,-1 +8000dc18: 02c12083 lw ra,44(sp) +8000dc1c: 02812403 lw s0,40(sp) +8000dc20: 02412483 lw s1,36(sp) +8000dc24: 01c12983 lw s3,28(sp) +8000dc28: 01812a03 lw s4,24(sp) +8000dc2c: 01412a83 lw s5,20(sp) +8000dc30: 01012b03 lw s6,16(sp) +8000dc34: 00090513 mv a0,s2 +8000dc38: 02012903 lw s2,32(sp) +8000dc3c: 03010113 addi sp,sp,48 +8000dc40: 00008067 ret +8000dc44: 00098913 mv s2,s3 +8000dc48: fd1ff06f j 8000dc18 <__fputwc+0xe8> +8000dc4c: 00c45783 lhu a5,12(s0) +8000dc50: 0407e793 ori a5,a5,64 +8000dc54: 00f41623 sh a5,12(s0) +8000dc58: fc1ff06f j 8000dc18 <__fputwc+0xe8> -8000dd20 <_fputwc_r>: -8000dd20: 00c61783 lh a5,12(a2) -8000dd24: 01279713 slli a4,a5,0x12 -8000dd28: 02074063 bltz a4,8000dd48 <_fputwc_r+0x28> -8000dd2c: 06462703 lw a4,100(a2) -8000dd30: 000026b7 lui a3,0x2 -8000dd34: 00d7e7b3 or a5,a5,a3 -8000dd38: 000026b7 lui a3,0x2 -8000dd3c: 00d76733 or a4,a4,a3 -8000dd40: 00f61623 sh a5,12(a2) -8000dd44: 06e62223 sw a4,100(a2) -8000dd48: eadff06f j 8000dbf4 <__fputwc> +8000dc5c <_fputwc_r>: +8000dc5c: 00c61783 lh a5,12(a2) +8000dc60: 01279713 slli a4,a5,0x12 +8000dc64: 02074063 bltz a4,8000dc84 <_fputwc_r+0x28> +8000dc68: 06462703 lw a4,100(a2) +8000dc6c: 000026b7 lui a3,0x2 +8000dc70: 00d7e7b3 or a5,a5,a3 +8000dc74: 000026b7 lui a3,0x2 +8000dc78: 00d76733 or a4,a4,a3 +8000dc7c: 00f61623 sh a5,12(a2) +8000dc80: 06e62223 sw a4,100(a2) +8000dc84: eadff06f j 8000db30 <__fputwc> -8000dd4c : -8000dd4c: fe010113 addi sp,sp,-32 -8000dd50: 00812c23 sw s0,24(sp) -8000dd54: 3601a403 lw s0,864(gp) # 80016b68 <_impure_ptr> -8000dd58: 00112e23 sw ra,28(sp) -8000dd5c: 00058613 mv a2,a1 -8000dd60: 00050593 mv a1,a0 -8000dd64: 00040663 beqz s0,8000dd70 -8000dd68: 03842783 lw a5,56(s0) -8000dd6c: 04078063 beqz a5,8000ddac -8000dd70: 00c61783 lh a5,12(a2) -8000dd74: 01279713 slli a4,a5,0x12 -8000dd78: 02074063 bltz a4,8000dd98 -8000dd7c: 06462703 lw a4,100(a2) -8000dd80: 000026b7 lui a3,0x2 -8000dd84: 00d7e7b3 or a5,a5,a3 -8000dd88: 000026b7 lui a3,0x2 -8000dd8c: 00d76733 or a4,a4,a3 -8000dd90: 00f61623 sh a5,12(a2) -8000dd94: 06e62223 sw a4,100(a2) -8000dd98: 00040513 mv a0,s0 -8000dd9c: 01812403 lw s0,24(sp) -8000dda0: 01c12083 lw ra,28(sp) -8000dda4: 02010113 addi sp,sp,32 -8000dda8: e4dff06f j 8000dbf4 <__fputwc> -8000ddac: 00a12423 sw a0,8(sp) -8000ddb0: 00040513 mv a0,s0 -8000ddb4: 00c12623 sw a2,12(sp) -8000ddb8: a51f60ef jal ra,80004808 <__sinit> -8000ddbc: 00c12603 lw a2,12(sp) -8000ddc0: 00812583 lw a1,8(sp) -8000ddc4: fadff06f j 8000dd70 +8000dc88 : +8000dc88: fe010113 addi sp,sp,-32 +8000dc8c: 00812c23 sw s0,24(sp) +8000dc90: 3601a403 lw s0,864(gp) # 80016b68 <_impure_ptr> +8000dc94: 00112e23 sw ra,28(sp) +8000dc98: 00058613 mv a2,a1 +8000dc9c: 00050593 mv a1,a0 +8000dca0: 00040663 beqz s0,8000dcac +8000dca4: 03842783 lw a5,56(s0) +8000dca8: 04078063 beqz a5,8000dce8 +8000dcac: 00c61783 lh a5,12(a2) +8000dcb0: 01279713 slli a4,a5,0x12 +8000dcb4: 02074063 bltz a4,8000dcd4 +8000dcb8: 06462703 lw a4,100(a2) +8000dcbc: 000026b7 lui a3,0x2 +8000dcc0: 00d7e7b3 or a5,a5,a3 +8000dcc4: 000026b7 lui a3,0x2 +8000dcc8: 00d76733 or a4,a4,a3 +8000dccc: 00f61623 sh a5,12(a2) +8000dcd0: 06e62223 sw a4,100(a2) +8000dcd4: 00040513 mv a0,s0 +8000dcd8: 01812403 lw s0,24(sp) +8000dcdc: 01c12083 lw ra,28(sp) +8000dce0: 02010113 addi sp,sp,32 +8000dce4: e4dff06f j 8000db30 <__fputwc> +8000dce8: 00a12423 sw a0,8(sp) +8000dcec: 00040513 mv a0,s0 +8000dcf0: 00c12623 sw a2,12(sp) +8000dcf4: a51f60ef jal ra,80004744 <__sinit> +8000dcf8: 00c12603 lw a2,12(sp) +8000dcfc: 00812583 lw a1,8(sp) +8000dd00: fadff06f j 8000dcac -8000ddc8 <_fstat_r>: -8000ddc8: ff010113 addi sp,sp,-16 -8000ddcc: 00058713 mv a4,a1 -8000ddd0: 00812423 sw s0,8(sp) -8000ddd4: 00912223 sw s1,4(sp) -8000ddd8: 00050413 mv s0,a0 -8000dddc: 00060593 mv a1,a2 -8000dde0: 00070513 mv a0,a4 -8000dde4: 00112623 sw ra,12(sp) -8000dde8: 4201a823 sw zero,1072(gp) # 80016c38 -8000ddec: cbcf20ef jal ra,800002a8 <_fstat> -8000ddf0: fff00793 li a5,-1 -8000ddf4: 00f50c63 beq a0,a5,8000de0c <_fstat_r+0x44> -8000ddf8: 00c12083 lw ra,12(sp) -8000ddfc: 00812403 lw s0,8(sp) -8000de00: 00412483 lw s1,4(sp) -8000de04: 01010113 addi sp,sp,16 -8000de08: 00008067 ret -8000de0c: 4301a783 lw a5,1072(gp) # 80016c38 -8000de10: fe0784e3 beqz a5,8000ddf8 <_fstat_r+0x30> -8000de14: 00c12083 lw ra,12(sp) -8000de18: 00f42023 sw a5,0(s0) -8000de1c: 00812403 lw s0,8(sp) -8000de20: 00412483 lw s1,4(sp) -8000de24: 01010113 addi sp,sp,16 -8000de28: 00008067 ret +8000dd04 <_fstat_r>: +8000dd04: ff010113 addi sp,sp,-16 +8000dd08: 00058713 mv a4,a1 +8000dd0c: 00812423 sw s0,8(sp) +8000dd10: 00912223 sw s1,4(sp) +8000dd14: 00050413 mv s0,a0 +8000dd18: 00060593 mv a1,a2 +8000dd1c: 00070513 mv a0,a4 +8000dd20: 00112623 sw ra,12(sp) +8000dd24: 4201a823 sw zero,1072(gp) # 80016c38 +8000dd28: d88f20ef jal ra,800002b0 <_fstat> +8000dd2c: fff00793 li a5,-1 +8000dd30: 00f50c63 beq a0,a5,8000dd48 <_fstat_r+0x44> +8000dd34: 00c12083 lw ra,12(sp) +8000dd38: 00812403 lw s0,8(sp) +8000dd3c: 00412483 lw s1,4(sp) +8000dd40: 01010113 addi sp,sp,16 +8000dd44: 00008067 ret +8000dd48: 4301a783 lw a5,1072(gp) # 80016c38 +8000dd4c: fe0784e3 beqz a5,8000dd34 <_fstat_r+0x30> +8000dd50: 00c12083 lw ra,12(sp) +8000dd54: 00f42023 sw a5,0(s0) +8000dd58: 00812403 lw s0,8(sp) +8000dd5c: 00412483 lw s1,4(sp) +8000dd60: 01010113 addi sp,sp,16 +8000dd64: 00008067 ret -8000de2c <__sfvwrite_r>: -8000de2c: 00862783 lw a5,8(a2) -8000de30: 32078e63 beqz a5,8000e16c <__sfvwrite_r+0x340> -8000de34: 00c5d783 lhu a5,12(a1) -8000de38: fd010113 addi sp,sp,-48 -8000de3c: 02812423 sw s0,40(sp) -8000de40: 01412c23 sw s4,24(sp) -8000de44: 01512a23 sw s5,20(sp) -8000de48: 02112623 sw ra,44(sp) -8000de4c: 02912223 sw s1,36(sp) -8000de50: 03212023 sw s2,32(sp) -8000de54: 01312e23 sw s3,28(sp) -8000de58: 01612823 sw s6,16(sp) -8000de5c: 01712623 sw s7,12(sp) -8000de60: 01812423 sw s8,8(sp) -8000de64: 01912223 sw s9,4(sp) -8000de68: 01a12023 sw s10,0(sp) -8000de6c: 0087f713 andi a4,a5,8 -8000de70: 00060a13 mv s4,a2 -8000de74: 00050a93 mv s5,a0 -8000de78: 00058413 mv s0,a1 -8000de7c: 08070663 beqz a4,8000df08 <__sfvwrite_r+0xdc> -8000de80: 0105a703 lw a4,16(a1) -8000de84: 08070263 beqz a4,8000df08 <__sfvwrite_r+0xdc> -8000de88: 0027f713 andi a4,a5,2 -8000de8c: 000a2483 lw s1,0(s4) -8000de90: 08070c63 beqz a4,8000df28 <__sfvwrite_r+0xfc> -8000de94: 02442783 lw a5,36(s0) -8000de98: 01c42583 lw a1,28(s0) -8000de9c: 80000b37 lui s6,0x80000 -8000dea0: 00000993 li s3,0 -8000dea4: 00000913 li s2,0 -8000dea8: c00b4b13 xori s6,s6,-1024 -8000deac: 00098613 mv a2,s3 -8000deb0: 000a8513 mv a0,s5 -8000deb4: 04090263 beqz s2,8000def8 <__sfvwrite_r+0xcc> -8000deb8: 00090693 mv a3,s2 -8000debc: 012b7463 bgeu s6,s2,8000dec4 <__sfvwrite_r+0x98> -8000dec0: 000b0693 mv a3,s6 -8000dec4: 000780e7 jalr a5 -8000dec8: 28a05863 blez a0,8000e158 <__sfvwrite_r+0x32c> -8000decc: 008a2783 lw a5,8(s4) -8000ded0: 00a989b3 add s3,s3,a0 -8000ded4: 40a90933 sub s2,s2,a0 -8000ded8: 40a78533 sub a0,a5,a0 -8000dedc: 00aa2423 sw a0,8(s4) -8000dee0: 20050a63 beqz a0,8000e0f4 <__sfvwrite_r+0x2c8> -8000dee4: 02442783 lw a5,36(s0) -8000dee8: 01c42583 lw a1,28(s0) -8000deec: 00098613 mv a2,s3 -8000def0: 000a8513 mv a0,s5 -8000def4: fc0912e3 bnez s2,8000deb8 <__sfvwrite_r+0x8c> -8000def8: 0004a983 lw s3,0(s1) -8000defc: 0044a903 lw s2,4(s1) -8000df00: 00848493 addi s1,s1,8 -8000df04: fa9ff06f j 8000deac <__sfvwrite_r+0x80> -8000df08: 00040593 mv a1,s0 -8000df0c: 000a8513 mv a0,s5 -8000df10: 870f60ef jal ra,80003f80 <__swsetup_r> -8000df14: 3a051c63 bnez a0,8000e2cc <__sfvwrite_r+0x4a0> -8000df18: 00c45783 lhu a5,12(s0) -8000df1c: 000a2483 lw s1,0(s4) -8000df20: 0027f713 andi a4,a5,2 -8000df24: f60718e3 bnez a4,8000de94 <__sfvwrite_r+0x68> -8000df28: 0017f713 andi a4,a5,1 -8000df2c: 24071463 bnez a4,8000e174 <__sfvwrite_r+0x348> -8000df30: 00842c83 lw s9,8(s0) -8000df34: 00042503 lw a0,0(s0) -8000df38: 80000b37 lui s6,0x80000 -8000df3c: ffeb4b93 xori s7,s6,-2 -8000df40: 00000c13 li s8,0 -8000df44: 00000913 li s2,0 -8000df48: fffb4b13 not s6,s6 -8000df4c: 0e090e63 beqz s2,8000e048 <__sfvwrite_r+0x21c> -8000df50: 2007f713 andi a4,a5,512 -8000df54: 24070c63 beqz a4,8000e1ac <__sfvwrite_r+0x380> -8000df58: 000c8d13 mv s10,s9 -8000df5c: 2f996263 bltu s2,s9,8000e240 <__sfvwrite_r+0x414> -8000df60: 4807f713 andi a4,a5,1152 -8000df64: 08070a63 beqz a4,8000dff8 <__sfvwrite_r+0x1cc> -8000df68: 01442983 lw s3,20(s0) -8000df6c: 01042583 lw a1,16(s0) -8000df70: 00190713 addi a4,s2,1 -8000df74: 00199693 slli a3,s3,0x1 -8000df78: 013686b3 add a3,a3,s3 -8000df7c: 01f6d993 srli s3,a3,0x1f -8000df80: 40b50d33 sub s10,a0,a1 -8000df84: 00d989b3 add s3,s3,a3 -8000df88: 4019d993 srai s3,s3,0x1 -8000df8c: 01a70733 add a4,a4,s10 -8000df90: 00098613 mv a2,s3 -8000df94: 00e9f663 bgeu s3,a4,8000dfa0 <__sfvwrite_r+0x174> -8000df98: 00070993 mv s3,a4 -8000df9c: 00070613 mv a2,a4 -8000dfa0: 4007f793 andi a5,a5,1024 -8000dfa4: 2e078463 beqz a5,8000e28c <__sfvwrite_r+0x460> -8000dfa8: 00060593 mv a1,a2 -8000dfac: 000a8513 mv a0,s5 -8000dfb0: bf9f90ef jal ra,80007ba8 <_malloc_r> -8000dfb4: 00050c93 mv s9,a0 -8000dfb8: 30050263 beqz a0,8000e2bc <__sfvwrite_r+0x490> -8000dfbc: 01042583 lw a1,16(s0) -8000dfc0: 000d0613 mv a2,s10 -8000dfc4: 4dc000ef jal ra,8000e4a0 -8000dfc8: 00c45783 lhu a5,12(s0) -8000dfcc: b7f7f793 andi a5,a5,-1153 -8000dfd0: 0807e793 ori a5,a5,128 -8000dfd4: 00f41623 sh a5,12(s0) -8000dfd8: 01ac8533 add a0,s9,s10 -8000dfdc: 41a987b3 sub a5,s3,s10 -8000dfe0: 01942823 sw s9,16(s0) -8000dfe4: 00a42023 sw a0,0(s0) -8000dfe8: 01342a23 sw s3,20(s0) -8000dfec: 00090c93 mv s9,s2 -8000dff0: 00f42423 sw a5,8(s0) -8000dff4: 00090d13 mv s10,s2 -8000dff8: 000d0613 mv a2,s10 -8000dffc: 000c0593 mv a1,s8 -8000e000: 5bc000ef jal ra,8000e5bc -8000e004: 00842703 lw a4,8(s0) -8000e008: 00042783 lw a5,0(s0) -8000e00c: 00090993 mv s3,s2 -8000e010: 41970cb3 sub s9,a4,s9 -8000e014: 01a787b3 add a5,a5,s10 -8000e018: 01942423 sw s9,8(s0) -8000e01c: 00f42023 sw a5,0(s0) -8000e020: 00000913 li s2,0 -8000e024: 008a2603 lw a2,8(s4) -8000e028: 013c0c33 add s8,s8,s3 -8000e02c: 413609b3 sub s3,a2,s3 -8000e030: 013a2423 sw s3,8(s4) -8000e034: 0c098063 beqz s3,8000e0f4 <__sfvwrite_r+0x2c8> -8000e038: 00842c83 lw s9,8(s0) -8000e03c: 00042503 lw a0,0(s0) -8000e040: 00c45783 lhu a5,12(s0) -8000e044: f00916e3 bnez s2,8000df50 <__sfvwrite_r+0x124> -8000e048: 0004ac03 lw s8,0(s1) -8000e04c: 0044a903 lw s2,4(s1) -8000e050: 00848493 addi s1,s1,8 -8000e054: ef9ff06f j 8000df4c <__sfvwrite_r+0x120> -8000e058: 0044a983 lw s3,4(s1) -8000e05c: 0004ac03 lw s8,0(s1) -8000e060: 00848493 addi s1,s1,8 -8000e064: fe098ae3 beqz s3,8000e058 <__sfvwrite_r+0x22c> -8000e068: 00098613 mv a2,s3 -8000e06c: 00a00593 li a1,10 -8000e070: 000c0513 mv a0,s8 -8000e074: accfa0ef jal ra,80008340 -8000e078: 12050463 beqz a0,8000e1a0 <__sfvwrite_r+0x374> -8000e07c: 00150513 addi a0,a0,1 -8000e080: 41850b33 sub s6,a0,s8 -8000e084: 000b0793 mv a5,s6 -8000e088: 00098b93 mv s7,s3 -8000e08c: 0137f463 bgeu a5,s3,8000e094 <__sfvwrite_r+0x268> -8000e090: 00078b93 mv s7,a5 -8000e094: 00042503 lw a0,0(s0) -8000e098: 01042783 lw a5,16(s0) -8000e09c: 01442683 lw a3,20(s0) -8000e0a0: 00a7f863 bgeu a5,a0,8000e0b0 <__sfvwrite_r+0x284> -8000e0a4: 00842903 lw s2,8(s0) -8000e0a8: 01268933 add s2,a3,s2 -8000e0ac: 09794263 blt s2,s7,8000e130 <__sfvwrite_r+0x304> -8000e0b0: 1adbc863 blt s7,a3,8000e260 <__sfvwrite_r+0x434> -8000e0b4: 02442783 lw a5,36(s0) -8000e0b8: 01c42583 lw a1,28(s0) -8000e0bc: 000c0613 mv a2,s8 -8000e0c0: 000a8513 mv a0,s5 -8000e0c4: 000780e7 jalr a5 -8000e0c8: 00050913 mv s2,a0 -8000e0cc: 08a05663 blez a0,8000e158 <__sfvwrite_r+0x32c> -8000e0d0: 412b0b33 sub s6,s6,s2 -8000e0d4: 00100513 li a0,1 -8000e0d8: 160b0a63 beqz s6,8000e24c <__sfvwrite_r+0x420> -8000e0dc: 008a2603 lw a2,8(s4) -8000e0e0: 012c0c33 add s8,s8,s2 -8000e0e4: 412989b3 sub s3,s3,s2 -8000e0e8: 41260933 sub s2,a2,s2 -8000e0ec: 012a2423 sw s2,8(s4) -8000e0f0: 08091a63 bnez s2,8000e184 <__sfvwrite_r+0x358> -8000e0f4: 00000513 li a0,0 -8000e0f8: 02c12083 lw ra,44(sp) -8000e0fc: 02812403 lw s0,40(sp) -8000e100: 02412483 lw s1,36(sp) -8000e104: 02012903 lw s2,32(sp) -8000e108: 01c12983 lw s3,28(sp) -8000e10c: 01812a03 lw s4,24(sp) -8000e110: 01412a83 lw s5,20(sp) -8000e114: 01012b03 lw s6,16(sp) -8000e118: 00c12b83 lw s7,12(sp) -8000e11c: 00812c03 lw s8,8(sp) -8000e120: 00412c83 lw s9,4(sp) -8000e124: 00012d03 lw s10,0(sp) -8000e128: 03010113 addi sp,sp,48 -8000e12c: 00008067 ret -8000e130: 000c0593 mv a1,s8 -8000e134: 00090613 mv a2,s2 -8000e138: 484000ef jal ra,8000e5bc -8000e13c: 00042783 lw a5,0(s0) -8000e140: 00040593 mv a1,s0 -8000e144: 000a8513 mv a0,s5 -8000e148: 012787b3 add a5,a5,s2 -8000e14c: 00f42023 sw a5,0(s0) -8000e150: b1cf60ef jal ra,8000446c <_fflush_r> -8000e154: f6050ee3 beqz a0,8000e0d0 <__sfvwrite_r+0x2a4> -8000e158: 00c41783 lh a5,12(s0) -8000e15c: 0407e793 ori a5,a5,64 -8000e160: 00f41623 sh a5,12(s0) -8000e164: fff00513 li a0,-1 -8000e168: f91ff06f j 8000e0f8 <__sfvwrite_r+0x2cc> -8000e16c: 00000513 li a0,0 -8000e170: 00008067 ret -8000e174: 00000b13 li s6,0 -8000e178: 00000513 li a0,0 -8000e17c: 00000c13 li s8,0 -8000e180: 00000993 li s3,0 -8000e184: ec098ae3 beqz s3,8000e058 <__sfvwrite_r+0x22c> -8000e188: ee051ee3 bnez a0,8000e084 <__sfvwrite_r+0x258> -8000e18c: 00098613 mv a2,s3 -8000e190: 00a00593 li a1,10 -8000e194: 000c0513 mv a0,s8 -8000e198: 9a8fa0ef jal ra,80008340 -8000e19c: ee0510e3 bnez a0,8000e07c <__sfvwrite_r+0x250> -8000e1a0: 00198793 addi a5,s3,1 -8000e1a4: 00078b13 mv s6,a5 -8000e1a8: ee1ff06f j 8000e088 <__sfvwrite_r+0x25c> -8000e1ac: 01042783 lw a5,16(s0) -8000e1b0: 04a7e263 bltu a5,a0,8000e1f4 <__sfvwrite_r+0x3c8> -8000e1b4: 01442783 lw a5,20(s0) -8000e1b8: 02f96e63 bltu s2,a5,8000e1f4 <__sfvwrite_r+0x3c8> -8000e1bc: 00090693 mv a3,s2 -8000e1c0: 012bf463 bgeu s7,s2,8000e1c8 <__sfvwrite_r+0x39c> -8000e1c4: 000b0693 mv a3,s6 -8000e1c8: 02f6c6b3 div a3,a3,a5 -8000e1cc: 02442703 lw a4,36(s0) -8000e1d0: 01c42583 lw a1,28(s0) -8000e1d4: 000c0613 mv a2,s8 -8000e1d8: 000a8513 mv a0,s5 -8000e1dc: 02f686b3 mul a3,a3,a5 -8000e1e0: 000700e7 jalr a4 -8000e1e4: 00050993 mv s3,a0 -8000e1e8: f6a058e3 blez a0,8000e158 <__sfvwrite_r+0x32c> -8000e1ec: 41390933 sub s2,s2,s3 -8000e1f0: e35ff06f j 8000e024 <__sfvwrite_r+0x1f8> -8000e1f4: 000c8993 mv s3,s9 -8000e1f8: 01997463 bgeu s2,s9,8000e200 <__sfvwrite_r+0x3d4> -8000e1fc: 00090993 mv s3,s2 -8000e200: 00098613 mv a2,s3 -8000e204: 000c0593 mv a1,s8 -8000e208: 3b4000ef jal ra,8000e5bc -8000e20c: 00842783 lw a5,8(s0) -8000e210: 00042703 lw a4,0(s0) -8000e214: 413787b3 sub a5,a5,s3 -8000e218: 01370733 add a4,a4,s3 -8000e21c: 00f42423 sw a5,8(s0) -8000e220: 00e42023 sw a4,0(s0) -8000e224: fc0794e3 bnez a5,8000e1ec <__sfvwrite_r+0x3c0> -8000e228: 00040593 mv a1,s0 -8000e22c: 000a8513 mv a0,s5 -8000e230: a3cf60ef jal ra,8000446c <_fflush_r> -8000e234: f20512e3 bnez a0,8000e158 <__sfvwrite_r+0x32c> -8000e238: 41390933 sub s2,s2,s3 -8000e23c: de9ff06f j 8000e024 <__sfvwrite_r+0x1f8> -8000e240: 00090c93 mv s9,s2 -8000e244: 00090d13 mv s10,s2 -8000e248: db1ff06f j 8000dff8 <__sfvwrite_r+0x1cc> -8000e24c: 00040593 mv a1,s0 -8000e250: 000a8513 mv a0,s5 -8000e254: a18f60ef jal ra,8000446c <_fflush_r> -8000e258: e80502e3 beqz a0,8000e0dc <__sfvwrite_r+0x2b0> -8000e25c: efdff06f j 8000e158 <__sfvwrite_r+0x32c> -8000e260: 000b8613 mv a2,s7 -8000e264: 000c0593 mv a1,s8 -8000e268: 354000ef jal ra,8000e5bc -8000e26c: 00842783 lw a5,8(s0) -8000e270: 00042603 lw a2,0(s0) -8000e274: 000b8913 mv s2,s7 -8000e278: 417787b3 sub a5,a5,s7 -8000e27c: 01760633 add a2,a2,s7 -8000e280: 00f42423 sw a5,8(s0) -8000e284: 00c42023 sw a2,0(s0) -8000e288: e49ff06f j 8000e0d0 <__sfvwrite_r+0x2a4> -8000e28c: 000a8513 mv a0,s5 -8000e290: 4b4000ef jal ra,8000e744 <_realloc_r> -8000e294: 00050c93 mv s9,a0 -8000e298: d40510e3 bnez a0,8000dfd8 <__sfvwrite_r+0x1ac> -8000e29c: 01042583 lw a1,16(s0) -8000e2a0: 000a8513 mv a0,s5 -8000e2a4: f30f60ef jal ra,800049d4 <_free_r> -8000e2a8: 00c41783 lh a5,12(s0) -8000e2ac: 00c00713 li a4,12 -8000e2b0: 00eaa023 sw a4,0(s5) -8000e2b4: f7f7f793 andi a5,a5,-129 -8000e2b8: ea5ff06f j 8000e15c <__sfvwrite_r+0x330> -8000e2bc: 00c00713 li a4,12 -8000e2c0: 00c41783 lh a5,12(s0) -8000e2c4: 00eaa023 sw a4,0(s5) -8000e2c8: e95ff06f j 8000e15c <__sfvwrite_r+0x330> -8000e2cc: fff00513 li a0,-1 -8000e2d0: e29ff06f j 8000e0f8 <__sfvwrite_r+0x2cc> +8000dd68 <__sfvwrite_r>: +8000dd68: 00862783 lw a5,8(a2) +8000dd6c: 32078e63 beqz a5,8000e0a8 <__sfvwrite_r+0x340> +8000dd70: 00c5d783 lhu a5,12(a1) +8000dd74: fd010113 addi sp,sp,-48 +8000dd78: 02812423 sw s0,40(sp) +8000dd7c: 01412c23 sw s4,24(sp) +8000dd80: 01512a23 sw s5,20(sp) +8000dd84: 02112623 sw ra,44(sp) +8000dd88: 02912223 sw s1,36(sp) +8000dd8c: 03212023 sw s2,32(sp) +8000dd90: 01312e23 sw s3,28(sp) +8000dd94: 01612823 sw s6,16(sp) +8000dd98: 01712623 sw s7,12(sp) +8000dd9c: 01812423 sw s8,8(sp) +8000dda0: 01912223 sw s9,4(sp) +8000dda4: 01a12023 sw s10,0(sp) +8000dda8: 0087f713 andi a4,a5,8 +8000ddac: 00060a13 mv s4,a2 +8000ddb0: 00050a93 mv s5,a0 +8000ddb4: 00058413 mv s0,a1 +8000ddb8: 08070663 beqz a4,8000de44 <__sfvwrite_r+0xdc> +8000ddbc: 0105a703 lw a4,16(a1) +8000ddc0: 08070263 beqz a4,8000de44 <__sfvwrite_r+0xdc> +8000ddc4: 0027f713 andi a4,a5,2 +8000ddc8: 000a2483 lw s1,0(s4) +8000ddcc: 08070c63 beqz a4,8000de64 <__sfvwrite_r+0xfc> +8000ddd0: 02442783 lw a5,36(s0) +8000ddd4: 01c42583 lw a1,28(s0) +8000ddd8: 80000b37 lui s6,0x80000 +8000dddc: 00000993 li s3,0 +8000dde0: 00000913 li s2,0 +8000dde4: c00b4b13 xori s6,s6,-1024 +8000dde8: 00098613 mv a2,s3 +8000ddec: 000a8513 mv a0,s5 +8000ddf0: 04090263 beqz s2,8000de34 <__sfvwrite_r+0xcc> +8000ddf4: 00090693 mv a3,s2 +8000ddf8: 012b7463 bgeu s6,s2,8000de00 <__sfvwrite_r+0x98> +8000ddfc: 000b0693 mv a3,s6 +8000de00: 000780e7 jalr a5 +8000de04: 28a05863 blez a0,8000e094 <__sfvwrite_r+0x32c> +8000de08: 008a2783 lw a5,8(s4) +8000de0c: 00a989b3 add s3,s3,a0 +8000de10: 40a90933 sub s2,s2,a0 +8000de14: 40a78533 sub a0,a5,a0 +8000de18: 00aa2423 sw a0,8(s4) +8000de1c: 20050a63 beqz a0,8000e030 <__sfvwrite_r+0x2c8> +8000de20: 02442783 lw a5,36(s0) +8000de24: 01c42583 lw a1,28(s0) +8000de28: 00098613 mv a2,s3 +8000de2c: 000a8513 mv a0,s5 +8000de30: fc0912e3 bnez s2,8000ddf4 <__sfvwrite_r+0x8c> +8000de34: 0004a983 lw s3,0(s1) +8000de38: 0044a903 lw s2,4(s1) +8000de3c: 00848493 addi s1,s1,8 +8000de40: fa9ff06f j 8000dde8 <__sfvwrite_r+0x80> +8000de44: 00040593 mv a1,s0 +8000de48: 000a8513 mv a0,s5 +8000de4c: 870f60ef jal ra,80003ebc <__swsetup_r> +8000de50: 3a051c63 bnez a0,8000e208 <__sfvwrite_r+0x4a0> +8000de54: 00c45783 lhu a5,12(s0) +8000de58: 000a2483 lw s1,0(s4) +8000de5c: 0027f713 andi a4,a5,2 +8000de60: f60718e3 bnez a4,8000ddd0 <__sfvwrite_r+0x68> +8000de64: 0017f713 andi a4,a5,1 +8000de68: 24071463 bnez a4,8000e0b0 <__sfvwrite_r+0x348> +8000de6c: 00842c83 lw s9,8(s0) +8000de70: 00042503 lw a0,0(s0) +8000de74: 80000b37 lui s6,0x80000 +8000de78: ffeb4b93 xori s7,s6,-2 +8000de7c: 00000c13 li s8,0 +8000de80: 00000913 li s2,0 +8000de84: fffb4b13 not s6,s6 +8000de88: 0e090e63 beqz s2,8000df84 <__sfvwrite_r+0x21c> +8000de8c: 2007f713 andi a4,a5,512 +8000de90: 24070c63 beqz a4,8000e0e8 <__sfvwrite_r+0x380> +8000de94: 000c8d13 mv s10,s9 +8000de98: 2f996263 bltu s2,s9,8000e17c <__sfvwrite_r+0x414> +8000de9c: 4807f713 andi a4,a5,1152 +8000dea0: 08070a63 beqz a4,8000df34 <__sfvwrite_r+0x1cc> +8000dea4: 01442983 lw s3,20(s0) +8000dea8: 01042583 lw a1,16(s0) +8000deac: 00190713 addi a4,s2,1 +8000deb0: 00199693 slli a3,s3,0x1 +8000deb4: 013686b3 add a3,a3,s3 +8000deb8: 01f6d993 srli s3,a3,0x1f +8000debc: 40b50d33 sub s10,a0,a1 +8000dec0: 00d989b3 add s3,s3,a3 +8000dec4: 4019d993 srai s3,s3,0x1 +8000dec8: 01a70733 add a4,a4,s10 +8000decc: 00098613 mv a2,s3 +8000ded0: 00e9f663 bgeu s3,a4,8000dedc <__sfvwrite_r+0x174> +8000ded4: 00070993 mv s3,a4 +8000ded8: 00070613 mv a2,a4 +8000dedc: 4007f793 andi a5,a5,1024 +8000dee0: 2e078463 beqz a5,8000e1c8 <__sfvwrite_r+0x460> +8000dee4: 00060593 mv a1,a2 +8000dee8: 000a8513 mv a0,s5 +8000deec: bf9f90ef jal ra,80007ae4 <_malloc_r> +8000def0: 00050c93 mv s9,a0 +8000def4: 30050263 beqz a0,8000e1f8 <__sfvwrite_r+0x490> +8000def8: 01042583 lw a1,16(s0) +8000defc: 000d0613 mv a2,s10 +8000df00: 4dc000ef jal ra,8000e3dc +8000df04: 00c45783 lhu a5,12(s0) +8000df08: b7f7f793 andi a5,a5,-1153 +8000df0c: 0807e793 ori a5,a5,128 +8000df10: 00f41623 sh a5,12(s0) +8000df14: 01ac8533 add a0,s9,s10 +8000df18: 41a987b3 sub a5,s3,s10 +8000df1c: 01942823 sw s9,16(s0) +8000df20: 00a42023 sw a0,0(s0) +8000df24: 01342a23 sw s3,20(s0) +8000df28: 00090c93 mv s9,s2 +8000df2c: 00f42423 sw a5,8(s0) +8000df30: 00090d13 mv s10,s2 +8000df34: 000d0613 mv a2,s10 +8000df38: 000c0593 mv a1,s8 +8000df3c: 5bc000ef jal ra,8000e4f8 +8000df40: 00842703 lw a4,8(s0) +8000df44: 00042783 lw a5,0(s0) +8000df48: 00090993 mv s3,s2 +8000df4c: 41970cb3 sub s9,a4,s9 +8000df50: 01a787b3 add a5,a5,s10 +8000df54: 01942423 sw s9,8(s0) +8000df58: 00f42023 sw a5,0(s0) +8000df5c: 00000913 li s2,0 +8000df60: 008a2603 lw a2,8(s4) +8000df64: 013c0c33 add s8,s8,s3 +8000df68: 413609b3 sub s3,a2,s3 +8000df6c: 013a2423 sw s3,8(s4) +8000df70: 0c098063 beqz s3,8000e030 <__sfvwrite_r+0x2c8> +8000df74: 00842c83 lw s9,8(s0) +8000df78: 00042503 lw a0,0(s0) +8000df7c: 00c45783 lhu a5,12(s0) +8000df80: f00916e3 bnez s2,8000de8c <__sfvwrite_r+0x124> +8000df84: 0004ac03 lw s8,0(s1) +8000df88: 0044a903 lw s2,4(s1) +8000df8c: 00848493 addi s1,s1,8 +8000df90: ef9ff06f j 8000de88 <__sfvwrite_r+0x120> +8000df94: 0044a983 lw s3,4(s1) +8000df98: 0004ac03 lw s8,0(s1) +8000df9c: 00848493 addi s1,s1,8 +8000dfa0: fe098ae3 beqz s3,8000df94 <__sfvwrite_r+0x22c> +8000dfa4: 00098613 mv a2,s3 +8000dfa8: 00a00593 li a1,10 +8000dfac: 000c0513 mv a0,s8 +8000dfb0: accfa0ef jal ra,8000827c +8000dfb4: 12050463 beqz a0,8000e0dc <__sfvwrite_r+0x374> +8000dfb8: 00150513 addi a0,a0,1 +8000dfbc: 41850b33 sub s6,a0,s8 +8000dfc0: 000b0793 mv a5,s6 +8000dfc4: 00098b93 mv s7,s3 +8000dfc8: 0137f463 bgeu a5,s3,8000dfd0 <__sfvwrite_r+0x268> +8000dfcc: 00078b93 mv s7,a5 +8000dfd0: 00042503 lw a0,0(s0) +8000dfd4: 01042783 lw a5,16(s0) +8000dfd8: 01442683 lw a3,20(s0) +8000dfdc: 00a7f863 bgeu a5,a0,8000dfec <__sfvwrite_r+0x284> +8000dfe0: 00842903 lw s2,8(s0) +8000dfe4: 01268933 add s2,a3,s2 +8000dfe8: 09794263 blt s2,s7,8000e06c <__sfvwrite_r+0x304> +8000dfec: 1adbc863 blt s7,a3,8000e19c <__sfvwrite_r+0x434> +8000dff0: 02442783 lw a5,36(s0) +8000dff4: 01c42583 lw a1,28(s0) +8000dff8: 000c0613 mv a2,s8 +8000dffc: 000a8513 mv a0,s5 +8000e000: 000780e7 jalr a5 +8000e004: 00050913 mv s2,a0 +8000e008: 08a05663 blez a0,8000e094 <__sfvwrite_r+0x32c> +8000e00c: 412b0b33 sub s6,s6,s2 +8000e010: 00100513 li a0,1 +8000e014: 160b0a63 beqz s6,8000e188 <__sfvwrite_r+0x420> +8000e018: 008a2603 lw a2,8(s4) +8000e01c: 012c0c33 add s8,s8,s2 +8000e020: 412989b3 sub s3,s3,s2 +8000e024: 41260933 sub s2,a2,s2 +8000e028: 012a2423 sw s2,8(s4) +8000e02c: 08091a63 bnez s2,8000e0c0 <__sfvwrite_r+0x358> +8000e030: 00000513 li a0,0 +8000e034: 02c12083 lw ra,44(sp) +8000e038: 02812403 lw s0,40(sp) +8000e03c: 02412483 lw s1,36(sp) +8000e040: 02012903 lw s2,32(sp) +8000e044: 01c12983 lw s3,28(sp) +8000e048: 01812a03 lw s4,24(sp) +8000e04c: 01412a83 lw s5,20(sp) +8000e050: 01012b03 lw s6,16(sp) +8000e054: 00c12b83 lw s7,12(sp) +8000e058: 00812c03 lw s8,8(sp) +8000e05c: 00412c83 lw s9,4(sp) +8000e060: 00012d03 lw s10,0(sp) +8000e064: 03010113 addi sp,sp,48 +8000e068: 00008067 ret +8000e06c: 000c0593 mv a1,s8 +8000e070: 00090613 mv a2,s2 +8000e074: 484000ef jal ra,8000e4f8 +8000e078: 00042783 lw a5,0(s0) +8000e07c: 00040593 mv a1,s0 +8000e080: 000a8513 mv a0,s5 +8000e084: 012787b3 add a5,a5,s2 +8000e088: 00f42023 sw a5,0(s0) +8000e08c: b1cf60ef jal ra,800043a8 <_fflush_r> +8000e090: f6050ee3 beqz a0,8000e00c <__sfvwrite_r+0x2a4> +8000e094: 00c41783 lh a5,12(s0) +8000e098: 0407e793 ori a5,a5,64 +8000e09c: 00f41623 sh a5,12(s0) +8000e0a0: fff00513 li a0,-1 +8000e0a4: f91ff06f j 8000e034 <__sfvwrite_r+0x2cc> +8000e0a8: 00000513 li a0,0 +8000e0ac: 00008067 ret +8000e0b0: 00000b13 li s6,0 +8000e0b4: 00000513 li a0,0 +8000e0b8: 00000c13 li s8,0 +8000e0bc: 00000993 li s3,0 +8000e0c0: ec098ae3 beqz s3,8000df94 <__sfvwrite_r+0x22c> +8000e0c4: ee051ee3 bnez a0,8000dfc0 <__sfvwrite_r+0x258> +8000e0c8: 00098613 mv a2,s3 +8000e0cc: 00a00593 li a1,10 +8000e0d0: 000c0513 mv a0,s8 +8000e0d4: 9a8fa0ef jal ra,8000827c +8000e0d8: ee0510e3 bnez a0,8000dfb8 <__sfvwrite_r+0x250> +8000e0dc: 00198793 addi a5,s3,1 +8000e0e0: 00078b13 mv s6,a5 +8000e0e4: ee1ff06f j 8000dfc4 <__sfvwrite_r+0x25c> +8000e0e8: 01042783 lw a5,16(s0) +8000e0ec: 04a7e263 bltu a5,a0,8000e130 <__sfvwrite_r+0x3c8> +8000e0f0: 01442783 lw a5,20(s0) +8000e0f4: 02f96e63 bltu s2,a5,8000e130 <__sfvwrite_r+0x3c8> +8000e0f8: 00090693 mv a3,s2 +8000e0fc: 012bf463 bgeu s7,s2,8000e104 <__sfvwrite_r+0x39c> +8000e100: 000b0693 mv a3,s6 +8000e104: 02f6c6b3 div a3,a3,a5 +8000e108: 02442703 lw a4,36(s0) +8000e10c: 01c42583 lw a1,28(s0) +8000e110: 000c0613 mv a2,s8 +8000e114: 000a8513 mv a0,s5 +8000e118: 02f686b3 mul a3,a3,a5 +8000e11c: 000700e7 jalr a4 +8000e120: 00050993 mv s3,a0 +8000e124: f6a058e3 blez a0,8000e094 <__sfvwrite_r+0x32c> +8000e128: 41390933 sub s2,s2,s3 +8000e12c: e35ff06f j 8000df60 <__sfvwrite_r+0x1f8> +8000e130: 000c8993 mv s3,s9 +8000e134: 01997463 bgeu s2,s9,8000e13c <__sfvwrite_r+0x3d4> +8000e138: 00090993 mv s3,s2 +8000e13c: 00098613 mv a2,s3 +8000e140: 000c0593 mv a1,s8 +8000e144: 3b4000ef jal ra,8000e4f8 +8000e148: 00842783 lw a5,8(s0) +8000e14c: 00042703 lw a4,0(s0) +8000e150: 413787b3 sub a5,a5,s3 +8000e154: 01370733 add a4,a4,s3 +8000e158: 00f42423 sw a5,8(s0) +8000e15c: 00e42023 sw a4,0(s0) +8000e160: fc0794e3 bnez a5,8000e128 <__sfvwrite_r+0x3c0> +8000e164: 00040593 mv a1,s0 +8000e168: 000a8513 mv a0,s5 +8000e16c: a3cf60ef jal ra,800043a8 <_fflush_r> +8000e170: f20512e3 bnez a0,8000e094 <__sfvwrite_r+0x32c> +8000e174: 41390933 sub s2,s2,s3 +8000e178: de9ff06f j 8000df60 <__sfvwrite_r+0x1f8> +8000e17c: 00090c93 mv s9,s2 +8000e180: 00090d13 mv s10,s2 +8000e184: db1ff06f j 8000df34 <__sfvwrite_r+0x1cc> +8000e188: 00040593 mv a1,s0 +8000e18c: 000a8513 mv a0,s5 +8000e190: a18f60ef jal ra,800043a8 <_fflush_r> +8000e194: e80502e3 beqz a0,8000e018 <__sfvwrite_r+0x2b0> +8000e198: efdff06f j 8000e094 <__sfvwrite_r+0x32c> +8000e19c: 000b8613 mv a2,s7 +8000e1a0: 000c0593 mv a1,s8 +8000e1a4: 354000ef jal ra,8000e4f8 +8000e1a8: 00842783 lw a5,8(s0) +8000e1ac: 00042603 lw a2,0(s0) +8000e1b0: 000b8913 mv s2,s7 +8000e1b4: 417787b3 sub a5,a5,s7 +8000e1b8: 01760633 add a2,a2,s7 +8000e1bc: 00f42423 sw a5,8(s0) +8000e1c0: 00c42023 sw a2,0(s0) +8000e1c4: e49ff06f j 8000e00c <__sfvwrite_r+0x2a4> +8000e1c8: 000a8513 mv a0,s5 +8000e1cc: 4b4000ef jal ra,8000e680 <_realloc_r> +8000e1d0: 00050c93 mv s9,a0 +8000e1d4: d40510e3 bnez a0,8000df14 <__sfvwrite_r+0x1ac> +8000e1d8: 01042583 lw a1,16(s0) +8000e1dc: 000a8513 mv a0,s5 +8000e1e0: f30f60ef jal ra,80004910 <_free_r> +8000e1e4: 00c41783 lh a5,12(s0) +8000e1e8: 00c00713 li a4,12 +8000e1ec: 00eaa023 sw a4,0(s5) +8000e1f0: f7f7f793 andi a5,a5,-129 +8000e1f4: ea5ff06f j 8000e098 <__sfvwrite_r+0x330> +8000e1f8: 00c00713 li a4,12 +8000e1fc: 00c41783 lh a5,12(s0) +8000e200: 00eaa023 sw a4,0(s5) +8000e204: e95ff06f j 8000e098 <__sfvwrite_r+0x330> +8000e208: fff00513 li a0,-1 +8000e20c: e29ff06f j 8000e034 <__sfvwrite_r+0x2cc> -8000e2d4 <_isatty_r>: -8000e2d4: ff010113 addi sp,sp,-16 -8000e2d8: 00812423 sw s0,8(sp) -8000e2dc: 00912223 sw s1,4(sp) -8000e2e0: 00050413 mv s0,a0 -8000e2e4: 00058513 mv a0,a1 -8000e2e8: 00112623 sw ra,12(sp) -8000e2ec: 4201a823 sw zero,1072(gp) # 80016c38 -8000e2f0: fedf10ef jal ra,800002dc <_isatty> -8000e2f4: fff00793 li a5,-1 -8000e2f8: 00f50c63 beq a0,a5,8000e310 <_isatty_r+0x3c> -8000e2fc: 00c12083 lw ra,12(sp) -8000e300: 00812403 lw s0,8(sp) -8000e304: 00412483 lw s1,4(sp) -8000e308: 01010113 addi sp,sp,16 -8000e30c: 00008067 ret -8000e310: 4301a783 lw a5,1072(gp) # 80016c38 -8000e314: fe0784e3 beqz a5,8000e2fc <_isatty_r+0x28> -8000e318: 00c12083 lw ra,12(sp) -8000e31c: 00f42023 sw a5,0(s0) -8000e320: 00812403 lw s0,8(sp) -8000e324: 00412483 lw s1,4(sp) -8000e328: 01010113 addi sp,sp,16 -8000e32c: 00008067 ret +8000e210 <_isatty_r>: +8000e210: ff010113 addi sp,sp,-16 +8000e214: 00812423 sw s0,8(sp) +8000e218: 00912223 sw s1,4(sp) +8000e21c: 00050413 mv s0,a0 +8000e220: 00058513 mv a0,a1 +8000e224: 00112623 sw ra,12(sp) +8000e228: 4201a823 sw zero,1072(gp) # 80016c38 +8000e22c: 8b8f20ef jal ra,800002e4 <_isatty> +8000e230: fff00793 li a5,-1 +8000e234: 00f50c63 beq a0,a5,8000e24c <_isatty_r+0x3c> +8000e238: 00c12083 lw ra,12(sp) +8000e23c: 00812403 lw s0,8(sp) +8000e240: 00412483 lw s1,4(sp) +8000e244: 01010113 addi sp,sp,16 +8000e248: 00008067 ret +8000e24c: 4301a783 lw a5,1072(gp) # 80016c38 +8000e250: fe0784e3 beqz a5,8000e238 <_isatty_r+0x28> +8000e254: 00c12083 lw ra,12(sp) +8000e258: 00f42023 sw a5,0(s0) +8000e25c: 00812403 lw s0,8(sp) +8000e260: 00412483 lw s1,4(sp) +8000e264: 01010113 addi sp,sp,16 +8000e268: 00008067 ret -8000e330 <_setlocale_r>: -8000e330: ff010113 addi sp,sp,-16 -8000e334: 00112623 sw ra,12(sp) -8000e338: 00812423 sw s0,8(sp) -8000e33c: 00912223 sw s1,4(sp) -8000e340: 02060c63 beqz a2,8000e378 <_setlocale_r+0x48> -8000e344: 800155b7 lui a1,0x80015 -8000e348: 4fc58593 addi a1,a1,1276 # 800154fc <__BSS_END__+0xffffe8c0> -8000e34c: 00060513 mv a0,a2 -8000e350: 00060413 mv s0,a2 -8000e354: 2ad000ef jal ra,8000ee00 -8000e358: 800154b7 lui s1,0x80015 -8000e35c: 02051263 bnez a0,8000e380 <_setlocale_r+0x50> -8000e360: 4f848513 addi a0,s1,1272 # 800154f8 <__BSS_END__+0xffffe8bc> -8000e364: 00c12083 lw ra,12(sp) -8000e368: 00812403 lw s0,8(sp) -8000e36c: 00412483 lw s1,4(sp) -8000e370: 01010113 addi sp,sp,16 -8000e374: 00008067 ret -8000e378: 800154b7 lui s1,0x80015 -8000e37c: fe5ff06f j 8000e360 <_setlocale_r+0x30> -8000e380: 4f848593 addi a1,s1,1272 # 800154f8 <__BSS_END__+0xffffe8bc> -8000e384: 00040513 mv a0,s0 -8000e388: 279000ef jal ra,8000ee00 -8000e38c: fc050ae3 beqz a0,8000e360 <_setlocale_r+0x30> -8000e390: 800155b7 lui a1,0x80015 -8000e394: c9c58593 addi a1,a1,-868 # 80014c9c <__BSS_END__+0xffffe060> -8000e398: 00040513 mv a0,s0 -8000e39c: 265000ef jal ra,8000ee00 -8000e3a0: fc0500e3 beqz a0,8000e360 <_setlocale_r+0x30> -8000e3a4: 00000513 li a0,0 -8000e3a8: fbdff06f j 8000e364 <_setlocale_r+0x34> +8000e26c <_setlocale_r>: +8000e26c: ff010113 addi sp,sp,-16 +8000e270: 00112623 sw ra,12(sp) +8000e274: 00812423 sw s0,8(sp) +8000e278: 00912223 sw s1,4(sp) +8000e27c: 02060c63 beqz a2,8000e2b4 <_setlocale_r+0x48> +8000e280: 800155b7 lui a1,0x80015 +8000e284: 42458593 addi a1,a1,1060 # 80015424 <__BSS_END__+0xffffe7e8> +8000e288: 00060513 mv a0,a2 +8000e28c: 00060413 mv s0,a2 +8000e290: 2ad000ef jal ra,8000ed3c +8000e294: 800154b7 lui s1,0x80015 +8000e298: 02051263 bnez a0,8000e2bc <_setlocale_r+0x50> +8000e29c: 42048513 addi a0,s1,1056 # 80015420 <__BSS_END__+0xffffe7e4> +8000e2a0: 00c12083 lw ra,12(sp) +8000e2a4: 00812403 lw s0,8(sp) +8000e2a8: 00412483 lw s1,4(sp) +8000e2ac: 01010113 addi sp,sp,16 +8000e2b0: 00008067 ret +8000e2b4: 800154b7 lui s1,0x80015 +8000e2b8: fe5ff06f j 8000e29c <_setlocale_r+0x30> +8000e2bc: 42048593 addi a1,s1,1056 # 80015420 <__BSS_END__+0xffffe7e4> +8000e2c0: 00040513 mv a0,s0 +8000e2c4: 279000ef jal ra,8000ed3c +8000e2c8: fc050ae3 beqz a0,8000e29c <_setlocale_r+0x30> +8000e2cc: 800155b7 lui a1,0x80015 +8000e2d0: bc858593 addi a1,a1,-1080 # 80014bc8 <__BSS_END__+0xffffdf8c> +8000e2d4: 00040513 mv a0,s0 +8000e2d8: 265000ef jal ra,8000ed3c +8000e2dc: fc0500e3 beqz a0,8000e29c <_setlocale_r+0x30> +8000e2e0: 00000513 li a0,0 +8000e2e4: fbdff06f j 8000e2a0 <_setlocale_r+0x34> -8000e3ac <__locale_mb_cur_max>: -8000e3ac: 2f01c503 lbu a0,752(gp) # 80016af8 <__global_locale+0x128> -8000e3b0: 00008067 ret +8000e2e8 <__locale_mb_cur_max>: +8000e2e8: 2f01c503 lbu a0,752(gp) # 80016af8 <__global_locale+0x128> +8000e2ec: 00008067 ret -8000e3b4 : -8000e3b4: 00050793 mv a5,a0 -8000e3b8: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -8000e3bc: 00058613 mv a2,a1 -8000e3c0: 00078593 mv a1,a5 -8000e3c4: f6dff06f j 8000e330 <_setlocale_r> +8000e2f0 : +8000e2f0: 00050793 mv a5,a0 +8000e2f4: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +8000e2f8: 00058613 mv a2,a1 +8000e2fc: 00078593 mv a1,a5 +8000e300: f6dff06f j 8000e26c <_setlocale_r> -8000e3c8 <_lseek_r>: -8000e3c8: ff010113 addi sp,sp,-16 -8000e3cc: 00058713 mv a4,a1 -8000e3d0: 00812423 sw s0,8(sp) -8000e3d4: 00912223 sw s1,4(sp) -8000e3d8: 00060593 mv a1,a2 -8000e3dc: 00050413 mv s0,a0 -8000e3e0: 00068613 mv a2,a3 -8000e3e4: 00070513 mv a0,a4 -8000e3e8: 00112623 sw ra,12(sp) -8000e3ec: 4201a823 sw zero,1072(gp) # 80016c38 -8000e3f0: f11f10ef jal ra,80000300 <_lseek> -8000e3f4: fff00793 li a5,-1 -8000e3f8: 00f50c63 beq a0,a5,8000e410 <_lseek_r+0x48> -8000e3fc: 00c12083 lw ra,12(sp) -8000e400: 00812403 lw s0,8(sp) -8000e404: 00412483 lw s1,4(sp) -8000e408: 01010113 addi sp,sp,16 -8000e40c: 00008067 ret -8000e410: 4301a783 lw a5,1072(gp) # 80016c38 -8000e414: fe0784e3 beqz a5,8000e3fc <_lseek_r+0x34> -8000e418: 00c12083 lw ra,12(sp) -8000e41c: 00f42023 sw a5,0(s0) -8000e420: 00812403 lw s0,8(sp) -8000e424: 00412483 lw s1,4(sp) -8000e428: 01010113 addi sp,sp,16 -8000e42c: 00008067 ret +8000e304 <_lseek_r>: +8000e304: ff010113 addi sp,sp,-16 +8000e308: 00058713 mv a4,a1 +8000e30c: 00812423 sw s0,8(sp) +8000e310: 00912223 sw s1,4(sp) +8000e314: 00060593 mv a1,a2 +8000e318: 00050413 mv s0,a0 +8000e31c: 00068613 mv a2,a3 +8000e320: 00070513 mv a0,a4 +8000e324: 00112623 sw ra,12(sp) +8000e328: 4201a823 sw zero,1072(gp) # 80016c38 +8000e32c: fddf10ef jal ra,80000308 <_lseek> +8000e330: fff00793 li a5,-1 +8000e334: 00f50c63 beq a0,a5,8000e34c <_lseek_r+0x48> +8000e338: 00c12083 lw ra,12(sp) +8000e33c: 00812403 lw s0,8(sp) +8000e340: 00412483 lw s1,4(sp) +8000e344: 01010113 addi sp,sp,16 +8000e348: 00008067 ret +8000e34c: 4301a783 lw a5,1072(gp) # 80016c38 +8000e350: fe0784e3 beqz a5,8000e338 <_lseek_r+0x34> +8000e354: 00c12083 lw ra,12(sp) +8000e358: 00f42023 sw a5,0(s0) +8000e35c: 00812403 lw s0,8(sp) +8000e360: 00412483 lw s1,4(sp) +8000e364: 01010113 addi sp,sp,16 +8000e368: 00008067 ret -8000e430 <_mbtowc_r>: -8000e430: 2ac1a303 lw t1,684(gp) # 80016ab4 <__global_locale+0xe4> -8000e434: 00030067 jr t1 +8000e36c <_mbtowc_r>: +8000e36c: 2ac1a303 lw t1,684(gp) # 80016ab4 <__global_locale+0xe4> +8000e370: 00030067 jr t1 -8000e438 <__ascii_mbtowc>: -8000e438: 02058063 beqz a1,8000e458 <__ascii_mbtowc+0x20> -8000e43c: 04060263 beqz a2,8000e480 <__ascii_mbtowc+0x48> -8000e440: 04068863 beqz a3,8000e490 <__ascii_mbtowc+0x58> -8000e444: 00064783 lbu a5,0(a2) -8000e448: 00f5a023 sw a5,0(a1) -8000e44c: 00064503 lbu a0,0(a2) -8000e450: 00a03533 snez a0,a0 -8000e454: 00008067 ret -8000e458: ff010113 addi sp,sp,-16 -8000e45c: 00c10593 addi a1,sp,12 -8000e460: 02060463 beqz a2,8000e488 <__ascii_mbtowc+0x50> -8000e464: 02068a63 beqz a3,8000e498 <__ascii_mbtowc+0x60> -8000e468: 00064783 lbu a5,0(a2) -8000e46c: 00f5a023 sw a5,0(a1) -8000e470: 00064503 lbu a0,0(a2) -8000e474: 00a03533 snez a0,a0 -8000e478: 01010113 addi sp,sp,16 -8000e47c: 00008067 ret -8000e480: 00000513 li a0,0 -8000e484: 00008067 ret -8000e488: 00000513 li a0,0 -8000e48c: fedff06f j 8000e478 <__ascii_mbtowc+0x40> -8000e490: ffe00513 li a0,-2 -8000e494: 00008067 ret -8000e498: ffe00513 li a0,-2 -8000e49c: fddff06f j 8000e478 <__ascii_mbtowc+0x40> +8000e374 <__ascii_mbtowc>: +8000e374: 02058063 beqz a1,8000e394 <__ascii_mbtowc+0x20> +8000e378: 04060263 beqz a2,8000e3bc <__ascii_mbtowc+0x48> +8000e37c: 04068863 beqz a3,8000e3cc <__ascii_mbtowc+0x58> +8000e380: 00064783 lbu a5,0(a2) +8000e384: 00f5a023 sw a5,0(a1) +8000e388: 00064503 lbu a0,0(a2) +8000e38c: 00a03533 snez a0,a0 +8000e390: 00008067 ret +8000e394: ff010113 addi sp,sp,-16 +8000e398: 00c10593 addi a1,sp,12 +8000e39c: 02060463 beqz a2,8000e3c4 <__ascii_mbtowc+0x50> +8000e3a0: 02068a63 beqz a3,8000e3d4 <__ascii_mbtowc+0x60> +8000e3a4: 00064783 lbu a5,0(a2) +8000e3a8: 00f5a023 sw a5,0(a1) +8000e3ac: 00064503 lbu a0,0(a2) +8000e3b0: 00a03533 snez a0,a0 +8000e3b4: 01010113 addi sp,sp,16 +8000e3b8: 00008067 ret +8000e3bc: 00000513 li a0,0 +8000e3c0: 00008067 ret +8000e3c4: 00000513 li a0,0 +8000e3c8: fedff06f j 8000e3b4 <__ascii_mbtowc+0x40> +8000e3cc: ffe00513 li a0,-2 +8000e3d0: 00008067 ret +8000e3d4: ffe00513 li a0,-2 +8000e3d8: fddff06f j 8000e3b4 <__ascii_mbtowc+0x40> -8000e4a0 : -8000e4a0: 00a5c7b3 xor a5,a1,a0 -8000e4a4: 0037f793 andi a5,a5,3 -8000e4a8: 00c508b3 add a7,a0,a2 -8000e4ac: 06079263 bnez a5,8000e510 -8000e4b0: 00300793 li a5,3 -8000e4b4: 04c7fe63 bgeu a5,a2,8000e510 -8000e4b8: 00357793 andi a5,a0,3 -8000e4bc: 00050713 mv a4,a0 -8000e4c0: 06079863 bnez a5,8000e530 -8000e4c4: ffc8f613 andi a2,a7,-4 -8000e4c8: fe060793 addi a5,a2,-32 -8000e4cc: 08f76c63 bltu a4,a5,8000e564 -8000e4d0: 02c77c63 bgeu a4,a2,8000e508 -8000e4d4: 00058693 mv a3,a1 -8000e4d8: 00070793 mv a5,a4 -8000e4dc: 0006a803 lw a6,0(a3) # 2000 <_start-0x7fffe000> -8000e4e0: 00478793 addi a5,a5,4 -8000e4e4: 00468693 addi a3,a3,4 -8000e4e8: ff07ae23 sw a6,-4(a5) -8000e4ec: fec7e8e3 bltu a5,a2,8000e4dc -8000e4f0: fff60793 addi a5,a2,-1 -8000e4f4: 40e787b3 sub a5,a5,a4 -8000e4f8: ffc7f793 andi a5,a5,-4 -8000e4fc: 00478793 addi a5,a5,4 -8000e500: 00f70733 add a4,a4,a5 -8000e504: 00f585b3 add a1,a1,a5 -8000e508: 01176863 bltu a4,a7,8000e518 -8000e50c: 00008067 ret -8000e510: 00050713 mv a4,a0 -8000e514: ff157ce3 bgeu a0,a7,8000e50c -8000e518: 0005c783 lbu a5,0(a1) -8000e51c: 00170713 addi a4,a4,1 -8000e520: 00158593 addi a1,a1,1 -8000e524: fef70fa3 sb a5,-1(a4) -8000e528: ff1768e3 bltu a4,a7,8000e518 -8000e52c: 00008067 ret -8000e530: 0005c683 lbu a3,0(a1) -8000e534: 00170713 addi a4,a4,1 -8000e538: 00377793 andi a5,a4,3 -8000e53c: fed70fa3 sb a3,-1(a4) -8000e540: 00158593 addi a1,a1,1 -8000e544: f80780e3 beqz a5,8000e4c4 -8000e548: 0005c683 lbu a3,0(a1) -8000e54c: 00170713 addi a4,a4,1 -8000e550: 00377793 andi a5,a4,3 -8000e554: fed70fa3 sb a3,-1(a4) -8000e558: 00158593 addi a1,a1,1 -8000e55c: fc079ae3 bnez a5,8000e530 -8000e560: f65ff06f j 8000e4c4 -8000e564: 0045a683 lw a3,4(a1) -8000e568: 0005a283 lw t0,0(a1) -8000e56c: 0085af83 lw t6,8(a1) -8000e570: 00c5af03 lw t5,12(a1) -8000e574: 0105ae83 lw t4,16(a1) -8000e578: 0145ae03 lw t3,20(a1) -8000e57c: 0185a303 lw t1,24(a1) -8000e580: 01c5a803 lw a6,28(a1) -8000e584: 00d72223 sw a3,4(a4) -8000e588: 0205a683 lw a3,32(a1) -8000e58c: 00572023 sw t0,0(a4) -8000e590: 01f72423 sw t6,8(a4) -8000e594: 01e72623 sw t5,12(a4) -8000e598: 01d72823 sw t4,16(a4) -8000e59c: 01c72a23 sw t3,20(a4) -8000e5a0: 00672c23 sw t1,24(a4) -8000e5a4: 01072e23 sw a6,28(a4) -8000e5a8: 02d72023 sw a3,32(a4) -8000e5ac: 02470713 addi a4,a4,36 -8000e5b0: 02458593 addi a1,a1,36 -8000e5b4: faf768e3 bltu a4,a5,8000e564 -8000e5b8: f19ff06f j 8000e4d0 +8000e3dc : +8000e3dc: 00a5c7b3 xor a5,a1,a0 +8000e3e0: 0037f793 andi a5,a5,3 +8000e3e4: 00c508b3 add a7,a0,a2 +8000e3e8: 06079263 bnez a5,8000e44c +8000e3ec: 00300793 li a5,3 +8000e3f0: 04c7fe63 bgeu a5,a2,8000e44c +8000e3f4: 00357793 andi a5,a0,3 +8000e3f8: 00050713 mv a4,a0 +8000e3fc: 06079863 bnez a5,8000e46c +8000e400: ffc8f613 andi a2,a7,-4 +8000e404: fe060793 addi a5,a2,-32 +8000e408: 08f76c63 bltu a4,a5,8000e4a0 +8000e40c: 02c77c63 bgeu a4,a2,8000e444 +8000e410: 00058693 mv a3,a1 +8000e414: 00070793 mv a5,a4 +8000e418: 0006a803 lw a6,0(a3) # 2000 <_start-0x7fffe000> +8000e41c: 00478793 addi a5,a5,4 +8000e420: 00468693 addi a3,a3,4 +8000e424: ff07ae23 sw a6,-4(a5) +8000e428: fec7e8e3 bltu a5,a2,8000e418 +8000e42c: fff60793 addi a5,a2,-1 +8000e430: 40e787b3 sub a5,a5,a4 +8000e434: ffc7f793 andi a5,a5,-4 +8000e438: 00478793 addi a5,a5,4 +8000e43c: 00f70733 add a4,a4,a5 +8000e440: 00f585b3 add a1,a1,a5 +8000e444: 01176863 bltu a4,a7,8000e454 +8000e448: 00008067 ret +8000e44c: 00050713 mv a4,a0 +8000e450: ff157ce3 bgeu a0,a7,8000e448 +8000e454: 0005c783 lbu a5,0(a1) +8000e458: 00170713 addi a4,a4,1 +8000e45c: 00158593 addi a1,a1,1 +8000e460: fef70fa3 sb a5,-1(a4) +8000e464: ff1768e3 bltu a4,a7,8000e454 +8000e468: 00008067 ret +8000e46c: 0005c683 lbu a3,0(a1) +8000e470: 00170713 addi a4,a4,1 +8000e474: 00377793 andi a5,a4,3 +8000e478: fed70fa3 sb a3,-1(a4) +8000e47c: 00158593 addi a1,a1,1 +8000e480: f80780e3 beqz a5,8000e400 +8000e484: 0005c683 lbu a3,0(a1) +8000e488: 00170713 addi a4,a4,1 +8000e48c: 00377793 andi a5,a4,3 +8000e490: fed70fa3 sb a3,-1(a4) +8000e494: 00158593 addi a1,a1,1 +8000e498: fc079ae3 bnez a5,8000e46c +8000e49c: f65ff06f j 8000e400 +8000e4a0: 0045a683 lw a3,4(a1) +8000e4a4: 0005a283 lw t0,0(a1) +8000e4a8: 0085af83 lw t6,8(a1) +8000e4ac: 00c5af03 lw t5,12(a1) +8000e4b0: 0105ae83 lw t4,16(a1) +8000e4b4: 0145ae03 lw t3,20(a1) +8000e4b8: 0185a303 lw t1,24(a1) +8000e4bc: 01c5a803 lw a6,28(a1) +8000e4c0: 00d72223 sw a3,4(a4) +8000e4c4: 0205a683 lw a3,32(a1) +8000e4c8: 00572023 sw t0,0(a4) +8000e4cc: 01f72423 sw t6,8(a4) +8000e4d0: 01e72623 sw t5,12(a4) +8000e4d4: 01d72823 sw t4,16(a4) +8000e4d8: 01c72a23 sw t3,20(a4) +8000e4dc: 00672c23 sw t1,24(a4) +8000e4e0: 01072e23 sw a6,28(a4) +8000e4e4: 02d72023 sw a3,32(a4) +8000e4e8: 02470713 addi a4,a4,36 +8000e4ec: 02458593 addi a1,a1,36 +8000e4f0: faf768e3 bltu a4,a5,8000e4a0 +8000e4f4: f19ff06f j 8000e40c -8000e5bc : -8000e5bc: 02a5f663 bgeu a1,a0,8000e5e8 -8000e5c0: 00c587b3 add a5,a1,a2 -8000e5c4: 02f57263 bgeu a0,a5,8000e5e8 -8000e5c8: 00c50733 add a4,a0,a2 -8000e5cc: 0e060a63 beqz a2,8000e6c0 -8000e5d0: fff7c683 lbu a3,-1(a5) -8000e5d4: fff78793 addi a5,a5,-1 -8000e5d8: fff70713 addi a4,a4,-1 -8000e5dc: 00d70023 sb a3,0(a4) -8000e5e0: fef598e3 bne a1,a5,8000e5d0 -8000e5e4: 00008067 ret -8000e5e8: 00f00793 li a5,15 -8000e5ec: 02c7e863 bltu a5,a2,8000e61c -8000e5f0: 00050793 mv a5,a0 -8000e5f4: fff60693 addi a3,a2,-1 -8000e5f8: 0c060c63 beqz a2,8000e6d0 -8000e5fc: 00168693 addi a3,a3,1 -8000e600: 00d786b3 add a3,a5,a3 -8000e604: 0005c703 lbu a4,0(a1) -8000e608: 00178793 addi a5,a5,1 -8000e60c: 00158593 addi a1,a1,1 -8000e610: fee78fa3 sb a4,-1(a5) -8000e614: fed798e3 bne a5,a3,8000e604 -8000e618: 00008067 ret -8000e61c: 00a5e7b3 or a5,a1,a0 -8000e620: 0037f793 andi a5,a5,3 -8000e624: 0a079063 bnez a5,8000e6c4 -8000e628: ff060893 addi a7,a2,-16 -8000e62c: ff08f893 andi a7,a7,-16 -8000e630: 01088893 addi a7,a7,16 -8000e634: 01150833 add a6,a0,a7 -8000e638: 00058713 mv a4,a1 -8000e63c: 00050793 mv a5,a0 -8000e640: 00072683 lw a3,0(a4) -8000e644: 01070713 addi a4,a4,16 -8000e648: 01078793 addi a5,a5,16 -8000e64c: fed7a823 sw a3,-16(a5) -8000e650: ff472683 lw a3,-12(a4) -8000e654: fed7aa23 sw a3,-12(a5) -8000e658: ff872683 lw a3,-8(a4) -8000e65c: fed7ac23 sw a3,-8(a5) -8000e660: ffc72683 lw a3,-4(a4) -8000e664: fed7ae23 sw a3,-4(a5) -8000e668: fcf81ce3 bne a6,a5,8000e640 -8000e66c: 00c67713 andi a4,a2,12 -8000e670: 011585b3 add a1,a1,a7 -8000e674: 00f67813 andi a6,a2,15 -8000e678: 04070e63 beqz a4,8000e6d4 -8000e67c: 00058713 mv a4,a1 -8000e680: 00078893 mv a7,a5 -8000e684: 00300e13 li t3,3 -8000e688: 00072303 lw t1,0(a4) -8000e68c: 00470713 addi a4,a4,4 -8000e690: 40e806b3 sub a3,a6,a4 -8000e694: 0068a023 sw t1,0(a7) -8000e698: 00d586b3 add a3,a1,a3 -8000e69c: 00488893 addi a7,a7,4 -8000e6a0: fede64e3 bltu t3,a3,8000e688 -8000e6a4: ffc80713 addi a4,a6,-4 -8000e6a8: ffc77713 andi a4,a4,-4 -8000e6ac: 00470713 addi a4,a4,4 -8000e6b0: 00367613 andi a2,a2,3 -8000e6b4: 00e787b3 add a5,a5,a4 -8000e6b8: 00e585b3 add a1,a1,a4 -8000e6bc: f39ff06f j 8000e5f4 -8000e6c0: 00008067 ret -8000e6c4: fff60693 addi a3,a2,-1 -8000e6c8: 00050793 mv a5,a0 -8000e6cc: f31ff06f j 8000e5fc -8000e6d0: 00008067 ret -8000e6d4: 00080613 mv a2,a6 -8000e6d8: f1dff06f j 8000e5f4 +8000e4f8 : +8000e4f8: 02a5f663 bgeu a1,a0,8000e524 +8000e4fc: 00c587b3 add a5,a1,a2 +8000e500: 02f57263 bgeu a0,a5,8000e524 +8000e504: 00c50733 add a4,a0,a2 +8000e508: 0e060a63 beqz a2,8000e5fc +8000e50c: fff7c683 lbu a3,-1(a5) +8000e510: fff78793 addi a5,a5,-1 +8000e514: fff70713 addi a4,a4,-1 +8000e518: 00d70023 sb a3,0(a4) +8000e51c: fef598e3 bne a1,a5,8000e50c +8000e520: 00008067 ret +8000e524: 00f00793 li a5,15 +8000e528: 02c7e863 bltu a5,a2,8000e558 +8000e52c: 00050793 mv a5,a0 +8000e530: fff60693 addi a3,a2,-1 +8000e534: 0c060c63 beqz a2,8000e60c +8000e538: 00168693 addi a3,a3,1 +8000e53c: 00d786b3 add a3,a5,a3 +8000e540: 0005c703 lbu a4,0(a1) +8000e544: 00178793 addi a5,a5,1 +8000e548: 00158593 addi a1,a1,1 +8000e54c: fee78fa3 sb a4,-1(a5) +8000e550: fed798e3 bne a5,a3,8000e540 +8000e554: 00008067 ret +8000e558: 00a5e7b3 or a5,a1,a0 +8000e55c: 0037f793 andi a5,a5,3 +8000e560: 0a079063 bnez a5,8000e600 +8000e564: ff060893 addi a7,a2,-16 +8000e568: ff08f893 andi a7,a7,-16 +8000e56c: 01088893 addi a7,a7,16 +8000e570: 01150833 add a6,a0,a7 +8000e574: 00058713 mv a4,a1 +8000e578: 00050793 mv a5,a0 +8000e57c: 00072683 lw a3,0(a4) +8000e580: 01070713 addi a4,a4,16 +8000e584: 01078793 addi a5,a5,16 +8000e588: fed7a823 sw a3,-16(a5) +8000e58c: ff472683 lw a3,-12(a4) +8000e590: fed7aa23 sw a3,-12(a5) +8000e594: ff872683 lw a3,-8(a4) +8000e598: fed7ac23 sw a3,-8(a5) +8000e59c: ffc72683 lw a3,-4(a4) +8000e5a0: fed7ae23 sw a3,-4(a5) +8000e5a4: fcf81ce3 bne a6,a5,8000e57c +8000e5a8: 00c67713 andi a4,a2,12 +8000e5ac: 011585b3 add a1,a1,a7 +8000e5b0: 00f67813 andi a6,a2,15 +8000e5b4: 04070e63 beqz a4,8000e610 +8000e5b8: 00058713 mv a4,a1 +8000e5bc: 00078893 mv a7,a5 +8000e5c0: 00300e13 li t3,3 +8000e5c4: 00072303 lw t1,0(a4) +8000e5c8: 00470713 addi a4,a4,4 +8000e5cc: 40e806b3 sub a3,a6,a4 +8000e5d0: 0068a023 sw t1,0(a7) +8000e5d4: 00d586b3 add a3,a1,a3 +8000e5d8: 00488893 addi a7,a7,4 +8000e5dc: fede64e3 bltu t3,a3,8000e5c4 +8000e5e0: ffc80713 addi a4,a6,-4 +8000e5e4: ffc77713 andi a4,a4,-4 +8000e5e8: 00470713 addi a4,a4,4 +8000e5ec: 00367613 andi a2,a2,3 +8000e5f0: 00e787b3 add a5,a5,a4 +8000e5f4: 00e585b3 add a1,a1,a4 +8000e5f8: f39ff06f j 8000e530 +8000e5fc: 00008067 ret +8000e600: fff60693 addi a3,a2,-1 +8000e604: 00050793 mv a5,a0 +8000e608: f31ff06f j 8000e538 +8000e60c: 00008067 ret +8000e610: 00080613 mv a2,a6 +8000e614: f1dff06f j 8000e530 -8000e6dc <_read_r>: -8000e6dc: ff010113 addi sp,sp,-16 -8000e6e0: 00058713 mv a4,a1 -8000e6e4: 00812423 sw s0,8(sp) -8000e6e8: 00912223 sw s1,4(sp) -8000e6ec: 00060593 mv a1,a2 -8000e6f0: 00050413 mv s0,a0 -8000e6f4: 00068613 mv a2,a3 -8000e6f8: 00070513 mv a0,a4 -8000e6fc: 00112623 sw ra,12(sp) -8000e700: 4201a823 sw zero,1072(gp) # 80016c38 -8000e704: cc5f10ef jal ra,800003c8 <_read> -8000e708: fff00793 li a5,-1 -8000e70c: 00f50c63 beq a0,a5,8000e724 <_read_r+0x48> -8000e710: 00c12083 lw ra,12(sp) -8000e714: 00812403 lw s0,8(sp) -8000e718: 00412483 lw s1,4(sp) -8000e71c: 01010113 addi sp,sp,16 -8000e720: 00008067 ret -8000e724: 4301a783 lw a5,1072(gp) # 80016c38 -8000e728: fe0784e3 beqz a5,8000e710 <_read_r+0x34> -8000e72c: 00c12083 lw ra,12(sp) -8000e730: 00f42023 sw a5,0(s0) -8000e734: 00812403 lw s0,8(sp) -8000e738: 00412483 lw s1,4(sp) -8000e73c: 01010113 addi sp,sp,16 -8000e740: 00008067 ret +8000e618 <_read_r>: +8000e618: ff010113 addi sp,sp,-16 +8000e61c: 00058713 mv a4,a1 +8000e620: 00812423 sw s0,8(sp) +8000e624: 00912223 sw s1,4(sp) +8000e628: 00060593 mv a1,a2 +8000e62c: 00050413 mv s0,a0 +8000e630: 00068613 mv a2,a3 +8000e634: 00070513 mv a0,a4 +8000e638: 00112623 sw ra,12(sp) +8000e63c: 4201a823 sw zero,1072(gp) # 80016c38 +8000e640: d91f10ef jal ra,800003d0 <_read> +8000e644: fff00793 li a5,-1 +8000e648: 00f50c63 beq a0,a5,8000e660 <_read_r+0x48> +8000e64c: 00c12083 lw ra,12(sp) +8000e650: 00812403 lw s0,8(sp) +8000e654: 00412483 lw s1,4(sp) +8000e658: 01010113 addi sp,sp,16 +8000e65c: 00008067 ret +8000e660: 4301a783 lw a5,1072(gp) # 80016c38 +8000e664: fe0784e3 beqz a5,8000e64c <_read_r+0x34> +8000e668: 00c12083 lw ra,12(sp) +8000e66c: 00f42023 sw a5,0(s0) +8000e670: 00812403 lw s0,8(sp) +8000e674: 00412483 lw s1,4(sp) +8000e678: 01010113 addi sp,sp,16 +8000e67c: 00008067 ret -8000e744 <_realloc_r>: -8000e744: fd010113 addi sp,sp,-48 -8000e748: 03212023 sw s2,32(sp) -8000e74c: 02112623 sw ra,44(sp) -8000e750: 02812423 sw s0,40(sp) -8000e754: 02912223 sw s1,36(sp) -8000e758: 01312e23 sw s3,28(sp) -8000e75c: 01412c23 sw s4,24(sp) -8000e760: 01512a23 sw s5,20(sp) -8000e764: 01612823 sw s6,16(sp) -8000e768: 01712623 sw s7,12(sp) -8000e76c: 01812423 sw s8,8(sp) -8000e770: 00060913 mv s2,a2 -8000e774: 22058263 beqz a1,8000e998 <_realloc_r+0x254> -8000e778: 00058413 mv s0,a1 -8000e77c: 00050993 mv s3,a0 -8000e780: d71f90ef jal ra,800084f0 <__malloc_lock> -8000e784: 00b90493 addi s1,s2,11 -8000e788: 01600793 li a5,22 -8000e78c: 0e97fc63 bgeu a5,s1,8000e884 <_realloc_r+0x140> -8000e790: ff84f493 andi s1,s1,-8 -8000e794: 00048713 mv a4,s1 -8000e798: 0e04cc63 bltz s1,8000e890 <_realloc_r+0x14c> -8000e79c: 0f24ea63 bltu s1,s2,8000e890 <_realloc_r+0x14c> -8000e7a0: ffc42783 lw a5,-4(s0) -8000e7a4: ff840a93 addi s5,s0,-8 -8000e7a8: ffc7fa13 andi s4,a5,-4 -8000e7ac: 014a8b33 add s6,s5,s4 -8000e7b0: 18ea5a63 bge s4,a4,8000e944 <_realloc_r+0x200> -8000e7b4: dc018b93 addi s7,gp,-576 # 800165c8 <__malloc_av_> -8000e7b8: 008ba603 lw a2,8(s7) -8000e7bc: 004b2683 lw a3,4(s6) # 80000004 <__BSS_END__+0xfffe93c8> -8000e7c0: 23660e63 beq a2,s6,8000e9fc <_realloc_r+0x2b8> -8000e7c4: ffe6f613 andi a2,a3,-2 -8000e7c8: 00cb0633 add a2,s6,a2 -8000e7cc: 00462603 lw a2,4(a2) -8000e7d0: 00167613 andi a2,a2,1 -8000e7d4: 1a061463 bnez a2,8000e97c <_realloc_r+0x238> -8000e7d8: ffc6f693 andi a3,a3,-4 -8000e7dc: 00da0633 add a2,s4,a3 -8000e7e0: 32e65e63 bge a2,a4,8000eb1c <_realloc_r+0x3d8> -8000e7e4: 0017f793 andi a5,a5,1 -8000e7e8: 02079463 bnez a5,8000e810 <_realloc_r+0xcc> -8000e7ec: ff842c03 lw s8,-8(s0) -8000e7f0: 418a8c33 sub s8,s5,s8 -8000e7f4: 004c2783 lw a5,4(s8) -8000e7f8: ffc7f793 andi a5,a5,-4 -8000e7fc: 00d786b3 add a3,a5,a3 -8000e800: 01468bb3 add s7,a3,s4 -8000e804: 34ebda63 bge s7,a4,8000eb58 <_realloc_r+0x414> -8000e808: 00fa0bb3 add s7,s4,a5 -8000e80c: 0cebd263 bge s7,a4,8000e8d0 <_realloc_r+0x18c> -8000e810: 00090593 mv a1,s2 -8000e814: 00098513 mv a0,s3 -8000e818: b90f90ef jal ra,80007ba8 <_malloc_r> -8000e81c: 00050913 mv s2,a0 -8000e820: 04050c63 beqz a0,8000e878 <_realloc_r+0x134> -8000e824: ffc42783 lw a5,-4(s0) -8000e828: ff850713 addi a4,a0,-8 -8000e82c: ffe7f793 andi a5,a5,-2 -8000e830: 00fa87b3 add a5,s5,a5 -8000e834: 30e78263 beq a5,a4,8000eb38 <_realloc_r+0x3f4> -8000e838: ffca0613 addi a2,s4,-4 -8000e83c: 02400793 li a5,36 -8000e840: 30c7e663 bltu a5,a2,8000eb4c <_realloc_r+0x408> -8000e844: 01300713 li a4,19 -8000e848: 00042683 lw a3,0(s0) -8000e84c: 26c76c63 bltu a4,a2,8000eac4 <_realloc_r+0x380> -8000e850: 00050793 mv a5,a0 -8000e854: 00040713 mv a4,s0 -8000e858: 00d7a023 sw a3,0(a5) -8000e85c: 00472683 lw a3,4(a4) -8000e860: 00d7a223 sw a3,4(a5) -8000e864: 00872703 lw a4,8(a4) -8000e868: 00e7a423 sw a4,8(a5) -8000e86c: 00040593 mv a1,s0 -8000e870: 00098513 mv a0,s3 -8000e874: 960f60ef jal ra,800049d4 <_free_r> -8000e878: 00098513 mv a0,s3 -8000e87c: c79f90ef jal ra,800084f4 <__malloc_unlock> -8000e880: 01c0006f j 8000e89c <_realloc_r+0x158> -8000e884: 01000493 li s1,16 -8000e888: 01000713 li a4,16 -8000e88c: f124fae3 bgeu s1,s2,8000e7a0 <_realloc_r+0x5c> -8000e890: 00c00793 li a5,12 -8000e894: 00f9a023 sw a5,0(s3) -8000e898: 00000913 li s2,0 -8000e89c: 02c12083 lw ra,44(sp) -8000e8a0: 02812403 lw s0,40(sp) -8000e8a4: 02412483 lw s1,36(sp) -8000e8a8: 01c12983 lw s3,28(sp) -8000e8ac: 01812a03 lw s4,24(sp) -8000e8b0: 01412a83 lw s5,20(sp) -8000e8b4: 01012b03 lw s6,16(sp) -8000e8b8: 00c12b83 lw s7,12(sp) -8000e8bc: 00812c03 lw s8,8(sp) -8000e8c0: 00090513 mv a0,s2 -8000e8c4: 02012903 lw s2,32(sp) -8000e8c8: 03010113 addi sp,sp,48 -8000e8cc: 00008067 ret -8000e8d0: 00cc2783 lw a5,12(s8) -8000e8d4: 008c2703 lw a4,8(s8) -8000e8d8: ffca0613 addi a2,s4,-4 -8000e8dc: 02400693 li a3,36 -8000e8e0: 00f72623 sw a5,12(a4) -8000e8e4: 00e7a423 sw a4,8(a5) -8000e8e8: 008c0913 addi s2,s8,8 -8000e8ec: 017c0b33 add s6,s8,s7 -8000e8f0: 2ec6e463 bltu a3,a2,8000ebd8 <_realloc_r+0x494> -8000e8f4: 01300593 li a1,19 -8000e8f8: 00042703 lw a4,0(s0) -8000e8fc: 00090793 mv a5,s2 -8000e900: 02c5f263 bgeu a1,a2,8000e924 <_realloc_r+0x1e0> -8000e904: 00ec2423 sw a4,8(s8) -8000e908: 00442703 lw a4,4(s0) -8000e90c: 01b00793 li a5,27 -8000e910: 00ec2623 sw a4,12(s8) -8000e914: 30c7e263 bltu a5,a2,8000ec18 <_realloc_r+0x4d4> -8000e918: 00842703 lw a4,8(s0) -8000e91c: 010c0793 addi a5,s8,16 -8000e920: 00840413 addi s0,s0,8 -8000e924: 00e7a023 sw a4,0(a5) -8000e928: 00442703 lw a4,4(s0) -8000e92c: 000b8a13 mv s4,s7 -8000e930: 000c0a93 mv s5,s8 -8000e934: 00e7a223 sw a4,4(a5) -8000e938: 00842703 lw a4,8(s0) -8000e93c: 00090413 mv s0,s2 -8000e940: 00e7a423 sw a4,8(a5) -8000e944: 004aa783 lw a5,4(s5) -8000e948: 409a0733 sub a4,s4,s1 -8000e94c: 00f00693 li a3,15 -8000e950: 0017f793 andi a5,a5,1 -8000e954: 06e6ec63 bltu a3,a4,8000e9cc <_realloc_r+0x288> -8000e958: 00fa67b3 or a5,s4,a5 -8000e95c: 00faa223 sw a5,4(s5) -8000e960: 004b2783 lw a5,4(s6) -8000e964: 0017e793 ori a5,a5,1 -8000e968: 00fb2223 sw a5,4(s6) -8000e96c: 00098513 mv a0,s3 -8000e970: b85f90ef jal ra,800084f4 <__malloc_unlock> -8000e974: 00040913 mv s2,s0 -8000e978: f25ff06f j 8000e89c <_realloc_r+0x158> -8000e97c: 0017f793 andi a5,a5,1 -8000e980: e80798e3 bnez a5,8000e810 <_realloc_r+0xcc> -8000e984: ff842c03 lw s8,-8(s0) -8000e988: 418a8c33 sub s8,s5,s8 -8000e98c: 004c2783 lw a5,4(s8) -8000e990: ffc7f793 andi a5,a5,-4 -8000e994: e75ff06f j 8000e808 <_realloc_r+0xc4> -8000e998: 02812403 lw s0,40(sp) -8000e99c: 02c12083 lw ra,44(sp) -8000e9a0: 02412483 lw s1,36(sp) -8000e9a4: 02012903 lw s2,32(sp) -8000e9a8: 01c12983 lw s3,28(sp) -8000e9ac: 01812a03 lw s4,24(sp) -8000e9b0: 01412a83 lw s5,20(sp) -8000e9b4: 01012b03 lw s6,16(sp) -8000e9b8: 00c12b83 lw s7,12(sp) -8000e9bc: 00812c03 lw s8,8(sp) -8000e9c0: 00060593 mv a1,a2 -8000e9c4: 03010113 addi sp,sp,48 -8000e9c8: 9e0f906f j 80007ba8 <_malloc_r> -8000e9cc: 0097e7b3 or a5,a5,s1 -8000e9d0: 00faa223 sw a5,4(s5) -8000e9d4: 009a85b3 add a1,s5,s1 -8000e9d8: 00176713 ori a4,a4,1 -8000e9dc: 00e5a223 sw a4,4(a1) -8000e9e0: 004b2783 lw a5,4(s6) -8000e9e4: 00858593 addi a1,a1,8 +8000e680 <_realloc_r>: +8000e680: fd010113 addi sp,sp,-48 +8000e684: 03212023 sw s2,32(sp) +8000e688: 02112623 sw ra,44(sp) +8000e68c: 02812423 sw s0,40(sp) +8000e690: 02912223 sw s1,36(sp) +8000e694: 01312e23 sw s3,28(sp) +8000e698: 01412c23 sw s4,24(sp) +8000e69c: 01512a23 sw s5,20(sp) +8000e6a0: 01612823 sw s6,16(sp) +8000e6a4: 01712623 sw s7,12(sp) +8000e6a8: 01812423 sw s8,8(sp) +8000e6ac: 00060913 mv s2,a2 +8000e6b0: 22058263 beqz a1,8000e8d4 <_realloc_r+0x254> +8000e6b4: 00058413 mv s0,a1 +8000e6b8: 00050993 mv s3,a0 +8000e6bc: d71f90ef jal ra,8000842c <__malloc_lock> +8000e6c0: 00b90493 addi s1,s2,11 +8000e6c4: 01600793 li a5,22 +8000e6c8: 0e97fc63 bgeu a5,s1,8000e7c0 <_realloc_r+0x140> +8000e6cc: ff84f493 andi s1,s1,-8 +8000e6d0: 00048713 mv a4,s1 +8000e6d4: 0e04cc63 bltz s1,8000e7cc <_realloc_r+0x14c> +8000e6d8: 0f24ea63 bltu s1,s2,8000e7cc <_realloc_r+0x14c> +8000e6dc: ffc42783 lw a5,-4(s0) +8000e6e0: ff840a93 addi s5,s0,-8 +8000e6e4: ffc7fa13 andi s4,a5,-4 +8000e6e8: 014a8b33 add s6,s5,s4 +8000e6ec: 18ea5a63 bge s4,a4,8000e880 <_realloc_r+0x200> +8000e6f0: dc018b93 addi s7,gp,-576 # 800165c8 <__malloc_av_> +8000e6f4: 008ba603 lw a2,8(s7) +8000e6f8: 004b2683 lw a3,4(s6) # 80000004 <__BSS_END__+0xfffe93c8> +8000e6fc: 23660e63 beq a2,s6,8000e938 <_realloc_r+0x2b8> +8000e700: ffe6f613 andi a2,a3,-2 +8000e704: 00cb0633 add a2,s6,a2 +8000e708: 00462603 lw a2,4(a2) +8000e70c: 00167613 andi a2,a2,1 +8000e710: 1a061463 bnez a2,8000e8b8 <_realloc_r+0x238> +8000e714: ffc6f693 andi a3,a3,-4 +8000e718: 00da0633 add a2,s4,a3 +8000e71c: 32e65e63 bge a2,a4,8000ea58 <_realloc_r+0x3d8> +8000e720: 0017f793 andi a5,a5,1 +8000e724: 02079463 bnez a5,8000e74c <_realloc_r+0xcc> +8000e728: ff842c03 lw s8,-8(s0) +8000e72c: 418a8c33 sub s8,s5,s8 +8000e730: 004c2783 lw a5,4(s8) +8000e734: ffc7f793 andi a5,a5,-4 +8000e738: 00d786b3 add a3,a5,a3 +8000e73c: 01468bb3 add s7,a3,s4 +8000e740: 34ebda63 bge s7,a4,8000ea94 <_realloc_r+0x414> +8000e744: 00fa0bb3 add s7,s4,a5 +8000e748: 0cebd263 bge s7,a4,8000e80c <_realloc_r+0x18c> +8000e74c: 00090593 mv a1,s2 +8000e750: 00098513 mv a0,s3 +8000e754: b90f90ef jal ra,80007ae4 <_malloc_r> +8000e758: 00050913 mv s2,a0 +8000e75c: 04050c63 beqz a0,8000e7b4 <_realloc_r+0x134> +8000e760: ffc42783 lw a5,-4(s0) +8000e764: ff850713 addi a4,a0,-8 +8000e768: ffe7f793 andi a5,a5,-2 +8000e76c: 00fa87b3 add a5,s5,a5 +8000e770: 30e78263 beq a5,a4,8000ea74 <_realloc_r+0x3f4> +8000e774: ffca0613 addi a2,s4,-4 +8000e778: 02400793 li a5,36 +8000e77c: 30c7e663 bltu a5,a2,8000ea88 <_realloc_r+0x408> +8000e780: 01300713 li a4,19 +8000e784: 00042683 lw a3,0(s0) +8000e788: 26c76c63 bltu a4,a2,8000ea00 <_realloc_r+0x380> +8000e78c: 00050793 mv a5,a0 +8000e790: 00040713 mv a4,s0 +8000e794: 00d7a023 sw a3,0(a5) +8000e798: 00472683 lw a3,4(a4) +8000e79c: 00d7a223 sw a3,4(a5) +8000e7a0: 00872703 lw a4,8(a4) +8000e7a4: 00e7a423 sw a4,8(a5) +8000e7a8: 00040593 mv a1,s0 +8000e7ac: 00098513 mv a0,s3 +8000e7b0: 960f60ef jal ra,80004910 <_free_r> +8000e7b4: 00098513 mv a0,s3 +8000e7b8: c79f90ef jal ra,80008430 <__malloc_unlock> +8000e7bc: 01c0006f j 8000e7d8 <_realloc_r+0x158> +8000e7c0: 01000493 li s1,16 +8000e7c4: 01000713 li a4,16 +8000e7c8: f124fae3 bgeu s1,s2,8000e6dc <_realloc_r+0x5c> +8000e7cc: 00c00793 li a5,12 +8000e7d0: 00f9a023 sw a5,0(s3) +8000e7d4: 00000913 li s2,0 +8000e7d8: 02c12083 lw ra,44(sp) +8000e7dc: 02812403 lw s0,40(sp) +8000e7e0: 02412483 lw s1,36(sp) +8000e7e4: 01c12983 lw s3,28(sp) +8000e7e8: 01812a03 lw s4,24(sp) +8000e7ec: 01412a83 lw s5,20(sp) +8000e7f0: 01012b03 lw s6,16(sp) +8000e7f4: 00c12b83 lw s7,12(sp) +8000e7f8: 00812c03 lw s8,8(sp) +8000e7fc: 00090513 mv a0,s2 +8000e800: 02012903 lw s2,32(sp) +8000e804: 03010113 addi sp,sp,48 +8000e808: 00008067 ret +8000e80c: 00cc2783 lw a5,12(s8) +8000e810: 008c2703 lw a4,8(s8) +8000e814: ffca0613 addi a2,s4,-4 +8000e818: 02400693 li a3,36 +8000e81c: 00f72623 sw a5,12(a4) +8000e820: 00e7a423 sw a4,8(a5) +8000e824: 008c0913 addi s2,s8,8 +8000e828: 017c0b33 add s6,s8,s7 +8000e82c: 2ec6e463 bltu a3,a2,8000eb14 <_realloc_r+0x494> +8000e830: 01300593 li a1,19 +8000e834: 00042703 lw a4,0(s0) +8000e838: 00090793 mv a5,s2 +8000e83c: 02c5f263 bgeu a1,a2,8000e860 <_realloc_r+0x1e0> +8000e840: 00ec2423 sw a4,8(s8) +8000e844: 00442703 lw a4,4(s0) +8000e848: 01b00793 li a5,27 +8000e84c: 00ec2623 sw a4,12(s8) +8000e850: 30c7e263 bltu a5,a2,8000eb54 <_realloc_r+0x4d4> +8000e854: 00842703 lw a4,8(s0) +8000e858: 010c0793 addi a5,s8,16 +8000e85c: 00840413 addi s0,s0,8 +8000e860: 00e7a023 sw a4,0(a5) +8000e864: 00442703 lw a4,4(s0) +8000e868: 000b8a13 mv s4,s7 +8000e86c: 000c0a93 mv s5,s8 +8000e870: 00e7a223 sw a4,4(a5) +8000e874: 00842703 lw a4,8(s0) +8000e878: 00090413 mv s0,s2 +8000e87c: 00e7a423 sw a4,8(a5) +8000e880: 004aa783 lw a5,4(s5) +8000e884: 409a0733 sub a4,s4,s1 +8000e888: 00f00693 li a3,15 +8000e88c: 0017f793 andi a5,a5,1 +8000e890: 06e6ec63 bltu a3,a4,8000e908 <_realloc_r+0x288> +8000e894: 00fa67b3 or a5,s4,a5 +8000e898: 00faa223 sw a5,4(s5) +8000e89c: 004b2783 lw a5,4(s6) +8000e8a0: 0017e793 ori a5,a5,1 +8000e8a4: 00fb2223 sw a5,4(s6) +8000e8a8: 00098513 mv a0,s3 +8000e8ac: b85f90ef jal ra,80008430 <__malloc_unlock> +8000e8b0: 00040913 mv s2,s0 +8000e8b4: f25ff06f j 8000e7d8 <_realloc_r+0x158> +8000e8b8: 0017f793 andi a5,a5,1 +8000e8bc: e80798e3 bnez a5,8000e74c <_realloc_r+0xcc> +8000e8c0: ff842c03 lw s8,-8(s0) +8000e8c4: 418a8c33 sub s8,s5,s8 +8000e8c8: 004c2783 lw a5,4(s8) +8000e8cc: ffc7f793 andi a5,a5,-4 +8000e8d0: e75ff06f j 8000e744 <_realloc_r+0xc4> +8000e8d4: 02812403 lw s0,40(sp) +8000e8d8: 02c12083 lw ra,44(sp) +8000e8dc: 02412483 lw s1,36(sp) +8000e8e0: 02012903 lw s2,32(sp) +8000e8e4: 01c12983 lw s3,28(sp) +8000e8e8: 01812a03 lw s4,24(sp) +8000e8ec: 01412a83 lw s5,20(sp) +8000e8f0: 01012b03 lw s6,16(sp) +8000e8f4: 00c12b83 lw s7,12(sp) +8000e8f8: 00812c03 lw s8,8(sp) +8000e8fc: 00060593 mv a1,a2 +8000e900: 03010113 addi sp,sp,48 +8000e904: 9e0f906f j 80007ae4 <_malloc_r> +8000e908: 0097e7b3 or a5,a5,s1 +8000e90c: 00faa223 sw a5,4(s5) +8000e910: 009a85b3 add a1,s5,s1 +8000e914: 00176713 ori a4,a4,1 +8000e918: 00e5a223 sw a4,4(a1) +8000e91c: 004b2783 lw a5,4(s6) +8000e920: 00858593 addi a1,a1,8 +8000e924: 00098513 mv a0,s3 +8000e928: 0017e793 ori a5,a5,1 +8000e92c: 00fb2223 sw a5,4(s6) +8000e930: fe1f50ef jal ra,80004910 <_free_r> +8000e934: f75ff06f j 8000e8a8 <_realloc_r+0x228> +8000e938: ffc6f693 andi a3,a3,-4 +8000e93c: 00da0633 add a2,s4,a3 +8000e940: 01048593 addi a1,s1,16 +8000e944: 0eb65063 bge a2,a1,8000ea24 <_realloc_r+0x3a4> +8000e948: 0017f793 andi a5,a5,1 +8000e94c: e00790e3 bnez a5,8000e74c <_realloc_r+0xcc> +8000e950: ff842c03 lw s8,-8(s0) +8000e954: 418a8c33 sub s8,s5,s8 +8000e958: 004c2783 lw a5,4(s8) +8000e95c: ffc7f793 andi a5,a5,-4 +8000e960: 00d786b3 add a3,a5,a3 +8000e964: 01468b33 add s6,a3,s4 +8000e968: dcbb4ee3 blt s6,a1,8000e744 <_realloc_r+0xc4> +8000e96c: 00cc2783 lw a5,12(s8) +8000e970: 008c2703 lw a4,8(s8) +8000e974: ffca0613 addi a2,s4,-4 +8000e978: 02400693 li a3,36 +8000e97c: 00f72623 sw a5,12(a4) +8000e980: 00e7a423 sw a4,8(a5) +8000e984: 008c0913 addi s2,s8,8 +8000e988: 20c6ee63 bltu a3,a2,8000eba4 <_realloc_r+0x524> +8000e98c: 01300593 li a1,19 +8000e990: 00042703 lw a4,0(s0) +8000e994: 00090793 mv a5,s2 +8000e998: 02c5f263 bgeu a1,a2,8000e9bc <_realloc_r+0x33c> +8000e99c: 00ec2423 sw a4,8(s8) +8000e9a0: 00442703 lw a4,4(s0) +8000e9a4: 01b00793 li a5,27 +8000e9a8: 00ec2623 sw a4,12(s8) +8000e9ac: 20c7e463 bltu a5,a2,8000ebb4 <_realloc_r+0x534> +8000e9b0: 00842703 lw a4,8(s0) +8000e9b4: 010c0793 addi a5,s8,16 +8000e9b8: 00840413 addi s0,s0,8 +8000e9bc: 00e7a023 sw a4,0(a5) +8000e9c0: 00442703 lw a4,4(s0) +8000e9c4: 00e7a223 sw a4,4(a5) +8000e9c8: 00842703 lw a4,8(s0) +8000e9cc: 00e7a423 sw a4,8(a5) +8000e9d0: 009c0733 add a4,s8,s1 +8000e9d4: 409b07b3 sub a5,s6,s1 +8000e9d8: 00eba423 sw a4,8(s7) +8000e9dc: 0017e793 ori a5,a5,1 +8000e9e0: 00f72223 sw a5,4(a4) +8000e9e4: 004c2783 lw a5,4(s8) 8000e9e8: 00098513 mv a0,s3 -8000e9ec: 0017e793 ori a5,a5,1 -8000e9f0: 00fb2223 sw a5,4(s6) -8000e9f4: fe1f50ef jal ra,800049d4 <_free_r> -8000e9f8: f75ff06f j 8000e96c <_realloc_r+0x228> -8000e9fc: ffc6f693 andi a3,a3,-4 -8000ea00: 00da0633 add a2,s4,a3 -8000ea04: 01048593 addi a1,s1,16 -8000ea08: 0eb65063 bge a2,a1,8000eae8 <_realloc_r+0x3a4> -8000ea0c: 0017f793 andi a5,a5,1 -8000ea10: e00790e3 bnez a5,8000e810 <_realloc_r+0xcc> -8000ea14: ff842c03 lw s8,-8(s0) -8000ea18: 418a8c33 sub s8,s5,s8 -8000ea1c: 004c2783 lw a5,4(s8) -8000ea20: ffc7f793 andi a5,a5,-4 -8000ea24: 00d786b3 add a3,a5,a3 -8000ea28: 01468b33 add s6,a3,s4 -8000ea2c: dcbb4ee3 blt s6,a1,8000e808 <_realloc_r+0xc4> -8000ea30: 00cc2783 lw a5,12(s8) -8000ea34: 008c2703 lw a4,8(s8) -8000ea38: ffca0613 addi a2,s4,-4 -8000ea3c: 02400693 li a3,36 -8000ea40: 00f72623 sw a5,12(a4) -8000ea44: 00e7a423 sw a4,8(a5) -8000ea48: 008c0913 addi s2,s8,8 -8000ea4c: 20c6ee63 bltu a3,a2,8000ec68 <_realloc_r+0x524> -8000ea50: 01300593 li a1,19 -8000ea54: 00042703 lw a4,0(s0) -8000ea58: 00090793 mv a5,s2 -8000ea5c: 02c5f263 bgeu a1,a2,8000ea80 <_realloc_r+0x33c> -8000ea60: 00ec2423 sw a4,8(s8) -8000ea64: 00442703 lw a4,4(s0) -8000ea68: 01b00793 li a5,27 -8000ea6c: 00ec2623 sw a4,12(s8) -8000ea70: 20c7e463 bltu a5,a2,8000ec78 <_realloc_r+0x534> -8000ea74: 00842703 lw a4,8(s0) -8000ea78: 010c0793 addi a5,s8,16 -8000ea7c: 00840413 addi s0,s0,8 -8000ea80: 00e7a023 sw a4,0(a5) -8000ea84: 00442703 lw a4,4(s0) -8000ea88: 00e7a223 sw a4,4(a5) -8000ea8c: 00842703 lw a4,8(s0) -8000ea90: 00e7a423 sw a4,8(a5) -8000ea94: 009c0733 add a4,s8,s1 -8000ea98: 409b07b3 sub a5,s6,s1 -8000ea9c: 00eba423 sw a4,8(s7) -8000eaa0: 0017e793 ori a5,a5,1 -8000eaa4: 00f72223 sw a5,4(a4) -8000eaa8: 004c2783 lw a5,4(s8) -8000eaac: 00098513 mv a0,s3 -8000eab0: 0017f793 andi a5,a5,1 -8000eab4: 0097e4b3 or s1,a5,s1 -8000eab8: 009c2223 sw s1,4(s8) -8000eabc: a39f90ef jal ra,800084f4 <__malloc_unlock> -8000eac0: dddff06f j 8000e89c <_realloc_r+0x158> -8000eac4: 00d52023 sw a3,0(a0) -8000eac8: 00442683 lw a3,4(s0) -8000eacc: 01b00713 li a4,27 -8000ead0: 00d52223 sw a3,4(a0) -8000ead4: 12c76063 bltu a4,a2,8000ebf4 <_realloc_r+0x4b0> -8000ead8: 00842683 lw a3,8(s0) -8000eadc: 00840713 addi a4,s0,8 -8000eae0: 00850793 addi a5,a0,8 -8000eae4: d75ff06f j 8000e858 <_realloc_r+0x114> -8000eae8: 009a8ab3 add s5,s5,s1 -8000eaec: 409607b3 sub a5,a2,s1 -8000eaf0: 015ba423 sw s5,8(s7) -8000eaf4: 0017e793 ori a5,a5,1 -8000eaf8: 00faa223 sw a5,4(s5) -8000eafc: ffc42783 lw a5,-4(s0) -8000eb00: 00098513 mv a0,s3 -8000eb04: 00040913 mv s2,s0 -8000eb08: 0017f793 andi a5,a5,1 -8000eb0c: 0097e4b3 or s1,a5,s1 -8000eb10: fe942e23 sw s1,-4(s0) -8000eb14: 9e1f90ef jal ra,800084f4 <__malloc_unlock> -8000eb18: d85ff06f j 8000e89c <_realloc_r+0x158> -8000eb1c: 00cb2783 lw a5,12(s6) -8000eb20: 008b2703 lw a4,8(s6) -8000eb24: 00060a13 mv s4,a2 -8000eb28: 00ca8b33 add s6,s5,a2 -8000eb2c: 00f72623 sw a5,12(a4) -8000eb30: 00e7a423 sw a4,8(a5) -8000eb34: e11ff06f j 8000e944 <_realloc_r+0x200> -8000eb38: ffc52783 lw a5,-4(a0) -8000eb3c: ffc7f793 andi a5,a5,-4 -8000eb40: 00fa0a33 add s4,s4,a5 -8000eb44: 014a8b33 add s6,s5,s4 -8000eb48: dfdff06f j 8000e944 <_realloc_r+0x200> -8000eb4c: 00040593 mv a1,s0 -8000eb50: a6dff0ef jal ra,8000e5bc -8000eb54: d19ff06f j 8000e86c <_realloc_r+0x128> -8000eb58: 00cb2783 lw a5,12(s6) -8000eb5c: 008b2703 lw a4,8(s6) -8000eb60: ffca0613 addi a2,s4,-4 -8000eb64: 02400693 li a3,36 -8000eb68: 00f72623 sw a5,12(a4) -8000eb6c: 00e7a423 sw a4,8(a5) -8000eb70: 008c2703 lw a4,8(s8) -8000eb74: 00cc2783 lw a5,12(s8) -8000eb78: 008c0913 addi s2,s8,8 -8000eb7c: 017c0b33 add s6,s8,s7 -8000eb80: 00f72623 sw a5,12(a4) -8000eb84: 00e7a423 sw a4,8(a5) -8000eb88: 04c6e863 bltu a3,a2,8000ebd8 <_realloc_r+0x494> -8000eb8c: 01300693 li a3,19 -8000eb90: 00042703 lw a4,0(s0) -8000eb94: 00090793 mv a5,s2 -8000eb98: d8c6f6e3 bgeu a3,a2,8000e924 <_realloc_r+0x1e0> -8000eb9c: 00ec2423 sw a4,8(s8) -8000eba0: 00442703 lw a4,4(s0) -8000eba4: 01b00793 li a5,27 -8000eba8: 00ec2623 sw a4,12(s8) -8000ebac: 00842703 lw a4,8(s0) -8000ebb0: d6c7f6e3 bgeu a5,a2,8000e91c <_realloc_r+0x1d8> -8000ebb4: 00ec2823 sw a4,16(s8) -8000ebb8: 00c42703 lw a4,12(s0) -8000ebbc: 02400793 li a5,36 -8000ebc0: 00ec2a23 sw a4,20(s8) +8000e9ec: 0017f793 andi a5,a5,1 +8000e9f0: 0097e4b3 or s1,a5,s1 +8000e9f4: 009c2223 sw s1,4(s8) +8000e9f8: a39f90ef jal ra,80008430 <__malloc_unlock> +8000e9fc: dddff06f j 8000e7d8 <_realloc_r+0x158> +8000ea00: 00d52023 sw a3,0(a0) +8000ea04: 00442683 lw a3,4(s0) +8000ea08: 01b00713 li a4,27 +8000ea0c: 00d52223 sw a3,4(a0) +8000ea10: 12c76063 bltu a4,a2,8000eb30 <_realloc_r+0x4b0> +8000ea14: 00842683 lw a3,8(s0) +8000ea18: 00840713 addi a4,s0,8 +8000ea1c: 00850793 addi a5,a0,8 +8000ea20: d75ff06f j 8000e794 <_realloc_r+0x114> +8000ea24: 009a8ab3 add s5,s5,s1 +8000ea28: 409607b3 sub a5,a2,s1 +8000ea2c: 015ba423 sw s5,8(s7) +8000ea30: 0017e793 ori a5,a5,1 +8000ea34: 00faa223 sw a5,4(s5) +8000ea38: ffc42783 lw a5,-4(s0) +8000ea3c: 00098513 mv a0,s3 +8000ea40: 00040913 mv s2,s0 +8000ea44: 0017f793 andi a5,a5,1 +8000ea48: 0097e4b3 or s1,a5,s1 +8000ea4c: fe942e23 sw s1,-4(s0) +8000ea50: 9e1f90ef jal ra,80008430 <__malloc_unlock> +8000ea54: d85ff06f j 8000e7d8 <_realloc_r+0x158> +8000ea58: 00cb2783 lw a5,12(s6) +8000ea5c: 008b2703 lw a4,8(s6) +8000ea60: 00060a13 mv s4,a2 +8000ea64: 00ca8b33 add s6,s5,a2 +8000ea68: 00f72623 sw a5,12(a4) +8000ea6c: 00e7a423 sw a4,8(a5) +8000ea70: e11ff06f j 8000e880 <_realloc_r+0x200> +8000ea74: ffc52783 lw a5,-4(a0) +8000ea78: ffc7f793 andi a5,a5,-4 +8000ea7c: 00fa0a33 add s4,s4,a5 +8000ea80: 014a8b33 add s6,s5,s4 +8000ea84: dfdff06f j 8000e880 <_realloc_r+0x200> +8000ea88: 00040593 mv a1,s0 +8000ea8c: a6dff0ef jal ra,8000e4f8 +8000ea90: d19ff06f j 8000e7a8 <_realloc_r+0x128> +8000ea94: 00cb2783 lw a5,12(s6) +8000ea98: 008b2703 lw a4,8(s6) +8000ea9c: ffca0613 addi a2,s4,-4 +8000eaa0: 02400693 li a3,36 +8000eaa4: 00f72623 sw a5,12(a4) +8000eaa8: 00e7a423 sw a4,8(a5) +8000eaac: 008c2703 lw a4,8(s8) +8000eab0: 00cc2783 lw a5,12(s8) +8000eab4: 008c0913 addi s2,s8,8 +8000eab8: 017c0b33 add s6,s8,s7 +8000eabc: 00f72623 sw a5,12(a4) +8000eac0: 00e7a423 sw a4,8(a5) +8000eac4: 04c6e863 bltu a3,a2,8000eb14 <_realloc_r+0x494> +8000eac8: 01300693 li a3,19 +8000eacc: 00042703 lw a4,0(s0) +8000ead0: 00090793 mv a5,s2 +8000ead4: d8c6f6e3 bgeu a3,a2,8000e860 <_realloc_r+0x1e0> +8000ead8: 00ec2423 sw a4,8(s8) +8000eadc: 00442703 lw a4,4(s0) +8000eae0: 01b00793 li a5,27 +8000eae4: 00ec2623 sw a4,12(s8) +8000eae8: 00842703 lw a4,8(s0) +8000eaec: d6c7f6e3 bgeu a5,a2,8000e858 <_realloc_r+0x1d8> +8000eaf0: 00ec2823 sw a4,16(s8) +8000eaf4: 00c42703 lw a4,12(s0) +8000eaf8: 02400793 li a5,36 +8000eafc: 00ec2a23 sw a4,20(s8) +8000eb00: 01042703 lw a4,16(s0) +8000eb04: 06f60463 beq a2,a5,8000eb6c <_realloc_r+0x4ec> +8000eb08: 018c0793 addi a5,s8,24 +8000eb0c: 01040413 addi s0,s0,16 +8000eb10: d51ff06f j 8000e860 <_realloc_r+0x1e0> +8000eb14: 00040593 mv a1,s0 +8000eb18: 00090513 mv a0,s2 +8000eb1c: 9ddff0ef jal ra,8000e4f8 +8000eb20: 00090413 mv s0,s2 +8000eb24: 000b8a13 mv s4,s7 +8000eb28: 000c0a93 mv s5,s8 +8000eb2c: d55ff06f j 8000e880 <_realloc_r+0x200> +8000eb30: 00842703 lw a4,8(s0) +8000eb34: 00e52423 sw a4,8(a0) +8000eb38: 00c42703 lw a4,12(s0) +8000eb3c: 00e52623 sw a4,12(a0) +8000eb40: 01042683 lw a3,16(s0) +8000eb44: 04f60263 beq a2,a5,8000eb88 <_realloc_r+0x508> +8000eb48: 01040713 addi a4,s0,16 +8000eb4c: 01050793 addi a5,a0,16 +8000eb50: c45ff06f j 8000e794 <_realloc_r+0x114> +8000eb54: 00842783 lw a5,8(s0) +8000eb58: 00fc2823 sw a5,16(s8) +8000eb5c: 00c42783 lw a5,12(s0) +8000eb60: 00fc2a23 sw a5,20(s8) +8000eb64: 01042703 lw a4,16(s0) +8000eb68: fad610e3 bne a2,a3,8000eb08 <_realloc_r+0x488> +8000eb6c: 00ec2c23 sw a4,24(s8) +8000eb70: 01442703 lw a4,20(s0) +8000eb74: 020c0793 addi a5,s8,32 +8000eb78: 01840413 addi s0,s0,24 +8000eb7c: 00ec2e23 sw a4,28(s8) +8000eb80: 00042703 lw a4,0(s0) +8000eb84: cddff06f j 8000e860 <_realloc_r+0x1e0> +8000eb88: 00d52823 sw a3,16(a0) +8000eb8c: 01442683 lw a3,20(s0) +8000eb90: 01840713 addi a4,s0,24 +8000eb94: 01850793 addi a5,a0,24 +8000eb98: 00d52a23 sw a3,20(a0) +8000eb9c: 01842683 lw a3,24(s0) +8000eba0: bf5ff06f j 8000e794 <_realloc_r+0x114> +8000eba4: 00040593 mv a1,s0 +8000eba8: 00090513 mv a0,s2 +8000ebac: 94dff0ef jal ra,8000e4f8 +8000ebb0: e21ff06f j 8000e9d0 <_realloc_r+0x350> +8000ebb4: 00842783 lw a5,8(s0) +8000ebb8: 00fc2823 sw a5,16(s8) +8000ebbc: 00c42783 lw a5,12(s0) +8000ebc0: 00fc2a23 sw a5,20(s8) 8000ebc4: 01042703 lw a4,16(s0) -8000ebc8: 06f60463 beq a2,a5,8000ec30 <_realloc_r+0x4ec> +8000ebc8: 00d60863 beq a2,a3,8000ebd8 <_realloc_r+0x558> 8000ebcc: 018c0793 addi a5,s8,24 8000ebd0: 01040413 addi s0,s0,16 -8000ebd4: d51ff06f j 8000e924 <_realloc_r+0x1e0> -8000ebd8: 00040593 mv a1,s0 -8000ebdc: 00090513 mv a0,s2 -8000ebe0: 9ddff0ef jal ra,8000e5bc -8000ebe4: 00090413 mv s0,s2 -8000ebe8: 000b8a13 mv s4,s7 -8000ebec: 000c0a93 mv s5,s8 -8000ebf0: d55ff06f j 8000e944 <_realloc_r+0x200> -8000ebf4: 00842703 lw a4,8(s0) -8000ebf8: 00e52423 sw a4,8(a0) -8000ebfc: 00c42703 lw a4,12(s0) -8000ec00: 00e52623 sw a4,12(a0) -8000ec04: 01042683 lw a3,16(s0) -8000ec08: 04f60263 beq a2,a5,8000ec4c <_realloc_r+0x508> -8000ec0c: 01040713 addi a4,s0,16 -8000ec10: 01050793 addi a5,a0,16 -8000ec14: c45ff06f j 8000e858 <_realloc_r+0x114> -8000ec18: 00842783 lw a5,8(s0) -8000ec1c: 00fc2823 sw a5,16(s8) -8000ec20: 00c42783 lw a5,12(s0) -8000ec24: 00fc2a23 sw a5,20(s8) -8000ec28: 01042703 lw a4,16(s0) -8000ec2c: fad610e3 bne a2,a3,8000ebcc <_realloc_r+0x488> -8000ec30: 00ec2c23 sw a4,24(s8) -8000ec34: 01442703 lw a4,20(s0) -8000ec38: 020c0793 addi a5,s8,32 -8000ec3c: 01840413 addi s0,s0,24 -8000ec40: 00ec2e23 sw a4,28(s8) -8000ec44: 00042703 lw a4,0(s0) -8000ec48: cddff06f j 8000e924 <_realloc_r+0x1e0> -8000ec4c: 00d52823 sw a3,16(a0) -8000ec50: 01442683 lw a3,20(s0) -8000ec54: 01840713 addi a4,s0,24 -8000ec58: 01850793 addi a5,a0,24 -8000ec5c: 00d52a23 sw a3,20(a0) -8000ec60: 01842683 lw a3,24(s0) -8000ec64: bf5ff06f j 8000e858 <_realloc_r+0x114> -8000ec68: 00040593 mv a1,s0 -8000ec6c: 00090513 mv a0,s2 -8000ec70: 94dff0ef jal ra,8000e5bc -8000ec74: e21ff06f j 8000ea94 <_realloc_r+0x350> -8000ec78: 00842783 lw a5,8(s0) -8000ec7c: 00fc2823 sw a5,16(s8) -8000ec80: 00c42783 lw a5,12(s0) -8000ec84: 00fc2a23 sw a5,20(s8) -8000ec88: 01042703 lw a4,16(s0) -8000ec8c: 00d60863 beq a2,a3,8000ec9c <_realloc_r+0x558> -8000ec90: 018c0793 addi a5,s8,24 -8000ec94: 01040413 addi s0,s0,16 -8000ec98: de9ff06f j 8000ea80 <_realloc_r+0x33c> -8000ec9c: 00ec2c23 sw a4,24(s8) -8000eca0: 01442703 lw a4,20(s0) -8000eca4: 020c0793 addi a5,s8,32 -8000eca8: 01840413 addi s0,s0,24 -8000ecac: 00ec2e23 sw a4,28(s8) -8000ecb0: 00042703 lw a4,0(s0) -8000ecb4: dcdff06f j 8000ea80 <_realloc_r+0x33c> +8000ebd4: de9ff06f j 8000e9bc <_realloc_r+0x33c> +8000ebd8: 00ec2c23 sw a4,24(s8) +8000ebdc: 01442703 lw a4,20(s0) +8000ebe0: 020c0793 addi a5,s8,32 +8000ebe4: 01840413 addi s0,s0,24 +8000ebe8: 00ec2e23 sw a4,28(s8) +8000ebec: 00042703 lw a4,0(s0) +8000ebf0: dcdff06f j 8000e9bc <_realloc_r+0x33c> -8000ecb8 : -8000ecb8: ff010113 addi sp,sp,-16 -8000ecbc: 00812423 sw s0,8(sp) -8000ecc0: 00058413 mv s0,a1 -8000ecc4: 0005a583 lw a1,0(a1) -8000ecc8: 00912223 sw s1,4(sp) -8000eccc: 00112623 sw ra,12(sp) -8000ecd0: 00050493 mv s1,a0 -8000ecd4: 00058463 beqz a1,8000ecdc -8000ecd8: fe1ff0ef jal ra,8000ecb8 -8000ecdc: 00040593 mv a1,s0 -8000ece0: 00812403 lw s0,8(sp) -8000ece4: 00c12083 lw ra,12(sp) -8000ece8: 00048513 mv a0,s1 -8000ecec: 00412483 lw s1,4(sp) -8000ecf0: 01010113 addi sp,sp,16 -8000ecf4: ce1f506f j 800049d4 <_free_r> +8000ebf4 : +8000ebf4: ff010113 addi sp,sp,-16 +8000ebf8: 00812423 sw s0,8(sp) +8000ebfc: 00058413 mv s0,a1 +8000ec00: 0005a583 lw a1,0(a1) +8000ec04: 00912223 sw s1,4(sp) +8000ec08: 00112623 sw ra,12(sp) +8000ec0c: 00050493 mv s1,a0 +8000ec10: 00058463 beqz a1,8000ec18 +8000ec14: fe1ff0ef jal ra,8000ebf4 +8000ec18: 00040593 mv a1,s0 +8000ec1c: 00812403 lw s0,8(sp) +8000ec20: 00c12083 lw ra,12(sp) +8000ec24: 00048513 mv a0,s1 +8000ec28: 00412483 lw s1,4(sp) +8000ec2c: 01010113 addi sp,sp,16 +8000ec30: ce1f506f j 80004910 <_free_r> -8000ecf8 <_reclaim_reent>: -8000ecf8: 3601a783 lw a5,864(gp) # 80016b68 <_impure_ptr> -8000ecfc: 10a78063 beq a5,a0,8000edfc <_reclaim_reent+0x104> -8000ed00: 04c52583 lw a1,76(a0) -8000ed04: fe010113 addi sp,sp,-32 -8000ed08: 00912a23 sw s1,20(sp) -8000ed0c: 00112e23 sw ra,28(sp) -8000ed10: 00812c23 sw s0,24(sp) -8000ed14: 01212823 sw s2,16(sp) -8000ed18: 01312623 sw s3,12(sp) -8000ed1c: 00050493 mv s1,a0 -8000ed20: 04058063 beqz a1,8000ed60 <_reclaim_reent+0x68> -8000ed24: 00000913 li s2,0 -8000ed28: 08000993 li s3,128 -8000ed2c: 012587b3 add a5,a1,s2 -8000ed30: 0007a403 lw s0,0(a5) -8000ed34: 00040e63 beqz s0,8000ed50 <_reclaim_reent+0x58> -8000ed38: 00040593 mv a1,s0 -8000ed3c: 00042403 lw s0,0(s0) -8000ed40: 00048513 mv a0,s1 -8000ed44: c91f50ef jal ra,800049d4 <_free_r> -8000ed48: fe0418e3 bnez s0,8000ed38 <_reclaim_reent+0x40> -8000ed4c: 04c4a583 lw a1,76(s1) -8000ed50: 00490913 addi s2,s2,4 -8000ed54: fd391ce3 bne s2,s3,8000ed2c <_reclaim_reent+0x34> -8000ed58: 00048513 mv a0,s1 -8000ed5c: c79f50ef jal ra,800049d4 <_free_r> -8000ed60: 0404a583 lw a1,64(s1) -8000ed64: 00058663 beqz a1,8000ed70 <_reclaim_reent+0x78> -8000ed68: 00048513 mv a0,s1 -8000ed6c: c69f50ef jal ra,800049d4 <_free_r> -8000ed70: 1484a403 lw s0,328(s1) -8000ed74: 02040063 beqz s0,8000ed94 <_reclaim_reent+0x9c> -8000ed78: 14c48913 addi s2,s1,332 -8000ed7c: 01240c63 beq s0,s2,8000ed94 <_reclaim_reent+0x9c> -8000ed80: 00040593 mv a1,s0 -8000ed84: 00042403 lw s0,0(s0) -8000ed88: 00048513 mv a0,s1 -8000ed8c: c49f50ef jal ra,800049d4 <_free_r> -8000ed90: fe8918e3 bne s2,s0,8000ed80 <_reclaim_reent+0x88> -8000ed94: 0544a583 lw a1,84(s1) -8000ed98: 00058663 beqz a1,8000eda4 <_reclaim_reent+0xac> -8000ed9c: 00048513 mv a0,s1 -8000eda0: c35f50ef jal ra,800049d4 <_free_r> -8000eda4: 0384a783 lw a5,56(s1) -8000eda8: 02078c63 beqz a5,8000ede0 <_reclaim_reent+0xe8> -8000edac: 03c4a783 lw a5,60(s1) -8000edb0: 00048513 mv a0,s1 -8000edb4: 000780e7 jalr a5 -8000edb8: 2e04a583 lw a1,736(s1) -8000edbc: 02058263 beqz a1,8000ede0 <_reclaim_reent+0xe8> -8000edc0: 01812403 lw s0,24(sp) -8000edc4: 01c12083 lw ra,28(sp) -8000edc8: 01012903 lw s2,16(sp) -8000edcc: 00c12983 lw s3,12(sp) -8000edd0: 00048513 mv a0,s1 -8000edd4: 01412483 lw s1,20(sp) -8000edd8: 02010113 addi sp,sp,32 -8000eddc: eddff06f j 8000ecb8 -8000ede0: 01c12083 lw ra,28(sp) -8000ede4: 01812403 lw s0,24(sp) -8000ede8: 01412483 lw s1,20(sp) -8000edec: 01012903 lw s2,16(sp) -8000edf0: 00c12983 lw s3,12(sp) -8000edf4: 02010113 addi sp,sp,32 -8000edf8: 00008067 ret -8000edfc: 00008067 ret +8000ec34 <_reclaim_reent>: +8000ec34: 3601a783 lw a5,864(gp) # 80016b68 <_impure_ptr> +8000ec38: 10a78063 beq a5,a0,8000ed38 <_reclaim_reent+0x104> +8000ec3c: 04c52583 lw a1,76(a0) +8000ec40: fe010113 addi sp,sp,-32 +8000ec44: 00912a23 sw s1,20(sp) +8000ec48: 00112e23 sw ra,28(sp) +8000ec4c: 00812c23 sw s0,24(sp) +8000ec50: 01212823 sw s2,16(sp) +8000ec54: 01312623 sw s3,12(sp) +8000ec58: 00050493 mv s1,a0 +8000ec5c: 04058063 beqz a1,8000ec9c <_reclaim_reent+0x68> +8000ec60: 00000913 li s2,0 +8000ec64: 08000993 li s3,128 +8000ec68: 012587b3 add a5,a1,s2 +8000ec6c: 0007a403 lw s0,0(a5) +8000ec70: 00040e63 beqz s0,8000ec8c <_reclaim_reent+0x58> +8000ec74: 00040593 mv a1,s0 +8000ec78: 00042403 lw s0,0(s0) +8000ec7c: 00048513 mv a0,s1 +8000ec80: c91f50ef jal ra,80004910 <_free_r> +8000ec84: fe0418e3 bnez s0,8000ec74 <_reclaim_reent+0x40> +8000ec88: 04c4a583 lw a1,76(s1) +8000ec8c: 00490913 addi s2,s2,4 +8000ec90: fd391ce3 bne s2,s3,8000ec68 <_reclaim_reent+0x34> +8000ec94: 00048513 mv a0,s1 +8000ec98: c79f50ef jal ra,80004910 <_free_r> +8000ec9c: 0404a583 lw a1,64(s1) +8000eca0: 00058663 beqz a1,8000ecac <_reclaim_reent+0x78> +8000eca4: 00048513 mv a0,s1 +8000eca8: c69f50ef jal ra,80004910 <_free_r> +8000ecac: 1484a403 lw s0,328(s1) +8000ecb0: 02040063 beqz s0,8000ecd0 <_reclaim_reent+0x9c> +8000ecb4: 14c48913 addi s2,s1,332 +8000ecb8: 01240c63 beq s0,s2,8000ecd0 <_reclaim_reent+0x9c> +8000ecbc: 00040593 mv a1,s0 +8000ecc0: 00042403 lw s0,0(s0) +8000ecc4: 00048513 mv a0,s1 +8000ecc8: c49f50ef jal ra,80004910 <_free_r> +8000eccc: fe8918e3 bne s2,s0,8000ecbc <_reclaim_reent+0x88> +8000ecd0: 0544a583 lw a1,84(s1) +8000ecd4: 00058663 beqz a1,8000ece0 <_reclaim_reent+0xac> +8000ecd8: 00048513 mv a0,s1 +8000ecdc: c35f50ef jal ra,80004910 <_free_r> +8000ece0: 0384a783 lw a5,56(s1) +8000ece4: 02078c63 beqz a5,8000ed1c <_reclaim_reent+0xe8> +8000ece8: 03c4a783 lw a5,60(s1) +8000ecec: 00048513 mv a0,s1 +8000ecf0: 000780e7 jalr a5 +8000ecf4: 2e04a583 lw a1,736(s1) +8000ecf8: 02058263 beqz a1,8000ed1c <_reclaim_reent+0xe8> +8000ecfc: 01812403 lw s0,24(sp) +8000ed00: 01c12083 lw ra,28(sp) +8000ed04: 01012903 lw s2,16(sp) +8000ed08: 00c12983 lw s3,12(sp) +8000ed0c: 00048513 mv a0,s1 +8000ed10: 01412483 lw s1,20(sp) +8000ed14: 02010113 addi sp,sp,32 +8000ed18: eddff06f j 8000ebf4 +8000ed1c: 01c12083 lw ra,28(sp) +8000ed20: 01812403 lw s0,24(sp) +8000ed24: 01412483 lw s1,20(sp) +8000ed28: 01012903 lw s2,16(sp) +8000ed2c: 00c12983 lw s3,12(sp) +8000ed30: 02010113 addi sp,sp,32 +8000ed34: 00008067 ret +8000ed38: 00008067 ret -8000ee00 : -8000ee00: 00b56733 or a4,a0,a1 -8000ee04: fff00393 li t2,-1 -8000ee08: 00377713 andi a4,a4,3 -8000ee0c: 10071063 bnez a4,8000ef0c -8000ee10: 7f7f87b7 lui a5,0x7f7f8 -8000ee14: f7f78793 addi a5,a5,-129 # 7f7f7f7f <_start-0x808081> -8000ee18: 00052603 lw a2,0(a0) -8000ee1c: 0005a683 lw a3,0(a1) -8000ee20: 00f672b3 and t0,a2,a5 -8000ee24: 00f66333 or t1,a2,a5 -8000ee28: 00f282b3 add t0,t0,a5 -8000ee2c: 0062e2b3 or t0,t0,t1 -8000ee30: 10729263 bne t0,t2,8000ef34 -8000ee34: 08d61663 bne a2,a3,8000eec0 -8000ee38: 00452603 lw a2,4(a0) -8000ee3c: 0045a683 lw a3,4(a1) -8000ee40: 00f672b3 and t0,a2,a5 -8000ee44: 00f66333 or t1,a2,a5 -8000ee48: 00f282b3 add t0,t0,a5 -8000ee4c: 0062e2b3 or t0,t0,t1 -8000ee50: 0c729e63 bne t0,t2,8000ef2c -8000ee54: 06d61663 bne a2,a3,8000eec0 -8000ee58: 00852603 lw a2,8(a0) -8000ee5c: 0085a683 lw a3,8(a1) -8000ee60: 00f672b3 and t0,a2,a5 -8000ee64: 00f66333 or t1,a2,a5 -8000ee68: 00f282b3 add t0,t0,a5 -8000ee6c: 0062e2b3 or t0,t0,t1 -8000ee70: 0c729863 bne t0,t2,8000ef40 -8000ee74: 04d61663 bne a2,a3,8000eec0 -8000ee78: 00c52603 lw a2,12(a0) -8000ee7c: 00c5a683 lw a3,12(a1) -8000ee80: 00f672b3 and t0,a2,a5 -8000ee84: 00f66333 or t1,a2,a5 -8000ee88: 00f282b3 add t0,t0,a5 -8000ee8c: 0062e2b3 or t0,t0,t1 -8000ee90: 0c729263 bne t0,t2,8000ef54 -8000ee94: 02d61663 bne a2,a3,8000eec0 -8000ee98: 01052603 lw a2,16(a0) -8000ee9c: 0105a683 lw a3,16(a1) -8000eea0: 00f672b3 and t0,a2,a5 -8000eea4: 00f66333 or t1,a2,a5 -8000eea8: 00f282b3 add t0,t0,a5 -8000eeac: 0062e2b3 or t0,t0,t1 -8000eeb0: 0a729c63 bne t0,t2,8000ef68 -8000eeb4: 01450513 addi a0,a0,20 -8000eeb8: 01458593 addi a1,a1,20 -8000eebc: f4d60ee3 beq a2,a3,8000ee18 -8000eec0: 01061713 slli a4,a2,0x10 -8000eec4: 01069793 slli a5,a3,0x10 -8000eec8: 00f71e63 bne a4,a5,8000eee4 -8000eecc: 01065713 srli a4,a2,0x10 -8000eed0: 0106d793 srli a5,a3,0x10 -8000eed4: 40f70533 sub a0,a4,a5 -8000eed8: 0ff57593 andi a1,a0,255 -8000eedc: 02059063 bnez a1,8000eefc -8000eee0: 00008067 ret -8000eee4: 01075713 srli a4,a4,0x10 -8000eee8: 0107d793 srli a5,a5,0x10 -8000eeec: 40f70533 sub a0,a4,a5 -8000eef0: 0ff57593 andi a1,a0,255 -8000eef4: 00059463 bnez a1,8000eefc -8000eef8: 00008067 ret -8000eefc: 0ff77713 andi a4,a4,255 -8000ef00: 0ff7f793 andi a5,a5,255 -8000ef04: 40f70533 sub a0,a4,a5 -8000ef08: 00008067 ret -8000ef0c: 00054603 lbu a2,0(a0) -8000ef10: 0005c683 lbu a3,0(a1) -8000ef14: 00150513 addi a0,a0,1 -8000ef18: 00158593 addi a1,a1,1 -8000ef1c: 00d61463 bne a2,a3,8000ef24 -8000ef20: fe0616e3 bnez a2,8000ef0c -8000ef24: 40d60533 sub a0,a2,a3 -8000ef28: 00008067 ret -8000ef2c: 00450513 addi a0,a0,4 -8000ef30: 00458593 addi a1,a1,4 -8000ef34: fcd61ce3 bne a2,a3,8000ef0c -8000ef38: 00000513 li a0,0 -8000ef3c: 00008067 ret -8000ef40: 00850513 addi a0,a0,8 -8000ef44: 00858593 addi a1,a1,8 -8000ef48: fcd612e3 bne a2,a3,8000ef0c -8000ef4c: 00000513 li a0,0 -8000ef50: 00008067 ret -8000ef54: 00c50513 addi a0,a0,12 -8000ef58: 00c58593 addi a1,a1,12 -8000ef5c: fad618e3 bne a2,a3,8000ef0c -8000ef60: 00000513 li a0,0 -8000ef64: 00008067 ret -8000ef68: 01050513 addi a0,a0,16 -8000ef6c: 01058593 addi a1,a1,16 -8000ef70: f8d61ee3 bne a2,a3,8000ef0c -8000ef74: 00000513 li a0,0 -8000ef78: 00008067 ret +8000ed3c : +8000ed3c: 00b56733 or a4,a0,a1 +8000ed40: fff00393 li t2,-1 +8000ed44: 00377713 andi a4,a4,3 +8000ed48: 10071063 bnez a4,8000ee48 +8000ed4c: 7f7f87b7 lui a5,0x7f7f8 +8000ed50: f7f78793 addi a5,a5,-129 # 7f7f7f7f <_start-0x808081> +8000ed54: 00052603 lw a2,0(a0) +8000ed58: 0005a683 lw a3,0(a1) +8000ed5c: 00f672b3 and t0,a2,a5 +8000ed60: 00f66333 or t1,a2,a5 +8000ed64: 00f282b3 add t0,t0,a5 +8000ed68: 0062e2b3 or t0,t0,t1 +8000ed6c: 10729263 bne t0,t2,8000ee70 +8000ed70: 08d61663 bne a2,a3,8000edfc +8000ed74: 00452603 lw a2,4(a0) +8000ed78: 0045a683 lw a3,4(a1) +8000ed7c: 00f672b3 and t0,a2,a5 +8000ed80: 00f66333 or t1,a2,a5 +8000ed84: 00f282b3 add t0,t0,a5 +8000ed88: 0062e2b3 or t0,t0,t1 +8000ed8c: 0c729e63 bne t0,t2,8000ee68 +8000ed90: 06d61663 bne a2,a3,8000edfc +8000ed94: 00852603 lw a2,8(a0) +8000ed98: 0085a683 lw a3,8(a1) +8000ed9c: 00f672b3 and t0,a2,a5 +8000eda0: 00f66333 or t1,a2,a5 +8000eda4: 00f282b3 add t0,t0,a5 +8000eda8: 0062e2b3 or t0,t0,t1 +8000edac: 0c729863 bne t0,t2,8000ee7c +8000edb0: 04d61663 bne a2,a3,8000edfc +8000edb4: 00c52603 lw a2,12(a0) +8000edb8: 00c5a683 lw a3,12(a1) +8000edbc: 00f672b3 and t0,a2,a5 +8000edc0: 00f66333 or t1,a2,a5 +8000edc4: 00f282b3 add t0,t0,a5 +8000edc8: 0062e2b3 or t0,t0,t1 +8000edcc: 0c729263 bne t0,t2,8000ee90 +8000edd0: 02d61663 bne a2,a3,8000edfc +8000edd4: 01052603 lw a2,16(a0) +8000edd8: 0105a683 lw a3,16(a1) +8000eddc: 00f672b3 and t0,a2,a5 +8000ede0: 00f66333 or t1,a2,a5 +8000ede4: 00f282b3 add t0,t0,a5 +8000ede8: 0062e2b3 or t0,t0,t1 +8000edec: 0a729c63 bne t0,t2,8000eea4 +8000edf0: 01450513 addi a0,a0,20 +8000edf4: 01458593 addi a1,a1,20 +8000edf8: f4d60ee3 beq a2,a3,8000ed54 +8000edfc: 01061713 slli a4,a2,0x10 +8000ee00: 01069793 slli a5,a3,0x10 +8000ee04: 00f71e63 bne a4,a5,8000ee20 +8000ee08: 01065713 srli a4,a2,0x10 +8000ee0c: 0106d793 srli a5,a3,0x10 +8000ee10: 40f70533 sub a0,a4,a5 +8000ee14: 0ff57593 andi a1,a0,255 +8000ee18: 02059063 bnez a1,8000ee38 +8000ee1c: 00008067 ret +8000ee20: 01075713 srli a4,a4,0x10 +8000ee24: 0107d793 srli a5,a5,0x10 +8000ee28: 40f70533 sub a0,a4,a5 +8000ee2c: 0ff57593 andi a1,a0,255 +8000ee30: 00059463 bnez a1,8000ee38 +8000ee34: 00008067 ret +8000ee38: 0ff77713 andi a4,a4,255 +8000ee3c: 0ff7f793 andi a5,a5,255 +8000ee40: 40f70533 sub a0,a4,a5 +8000ee44: 00008067 ret +8000ee48: 00054603 lbu a2,0(a0) +8000ee4c: 0005c683 lbu a3,0(a1) +8000ee50: 00150513 addi a0,a0,1 +8000ee54: 00158593 addi a1,a1,1 +8000ee58: 00d61463 bne a2,a3,8000ee60 +8000ee5c: fe0616e3 bnez a2,8000ee48 +8000ee60: 40d60533 sub a0,a2,a3 +8000ee64: 00008067 ret +8000ee68: 00450513 addi a0,a0,4 +8000ee6c: 00458593 addi a1,a1,4 +8000ee70: fcd61ce3 bne a2,a3,8000ee48 +8000ee74: 00000513 li a0,0 +8000ee78: 00008067 ret +8000ee7c: 00850513 addi a0,a0,8 +8000ee80: 00858593 addi a1,a1,8 +8000ee84: fcd612e3 bne a2,a3,8000ee48 +8000ee88: 00000513 li a0,0 +8000ee8c: 00008067 ret +8000ee90: 00c50513 addi a0,a0,12 +8000ee94: 00c58593 addi a1,a1,12 +8000ee98: fad618e3 bne a2,a3,8000ee48 +8000ee9c: 00000513 li a0,0 +8000eea0: 00008067 ret +8000eea4: 01050513 addi a0,a0,16 +8000eea8: 01058593 addi a1,a1,16 +8000eeac: f8d61ee3 bne a2,a3,8000ee48 +8000eeb0: 00000513 li a0,0 +8000eeb4: 00008067 ret -8000ef7c <__ssprint_r>: -8000ef7c: 00862783 lw a5,8(a2) -8000ef80: fd010113 addi sp,sp,-48 -8000ef84: 01512a23 sw s5,20(sp) -8000ef88: 02112623 sw ra,44(sp) -8000ef8c: 02812423 sw s0,40(sp) -8000ef90: 02912223 sw s1,36(sp) -8000ef94: 03212023 sw s2,32(sp) -8000ef98: 01312e23 sw s3,28(sp) -8000ef9c: 01412c23 sw s4,24(sp) -8000efa0: 01612823 sw s6,16(sp) -8000efa4: 01712623 sw s7,12(sp) -8000efa8: 01812423 sw s8,8(sp) -8000efac: 00060a93 mv s5,a2 -8000efb0: 14078863 beqz a5,8000f100 <__ssprint_r+0x184> -8000efb4: 00050b13 mv s6,a0 -8000efb8: 00062983 lw s3,0(a2) -8000efbc: 0005a503 lw a0,0(a1) -8000efc0: 0085a483 lw s1,8(a1) -8000efc4: 00058413 mv s0,a1 -8000efc8: 0d40006f j 8000f09c <__ssprint_r+0x120> -8000efcc: 00c45783 lhu a5,12(s0) -8000efd0: 4807f713 andi a4,a5,1152 -8000efd4: 08070a63 beqz a4,8000f068 <__ssprint_r+0xec> -8000efd8: 01442683 lw a3,20(s0) -8000efdc: 01042583 lw a1,16(s0) -8000efe0: 00190713 addi a4,s2,1 -8000efe4: 00169493 slli s1,a3,0x1 -8000efe8: 00d486b3 add a3,s1,a3 -8000efec: 01f6d493 srli s1,a3,0x1f -8000eff0: 40b50a33 sub s4,a0,a1 -8000eff4: 00d484b3 add s1,s1,a3 -8000eff8: 4014d493 srai s1,s1,0x1 -8000effc: 01470733 add a4,a4,s4 -8000f000: 00048613 mv a2,s1 -8000f004: 00e4f663 bgeu s1,a4,8000f010 <__ssprint_r+0x94> -8000f008: 00070493 mv s1,a4 -8000f00c: 00070613 mv a2,a4 -8000f010: 4007f793 andi a5,a5,1024 -8000f014: 0a078663 beqz a5,8000f0c0 <__ssprint_r+0x144> -8000f018: 00060593 mv a1,a2 -8000f01c: 000b0513 mv a0,s6 -8000f020: b89f80ef jal ra,80007ba8 <_malloc_r> -8000f024: 00050c13 mv s8,a0 -8000f028: 0a050a63 beqz a0,8000f0dc <__ssprint_r+0x160> -8000f02c: 01042583 lw a1,16(s0) -8000f030: 000a0613 mv a2,s4 -8000f034: c6cff0ef jal ra,8000e4a0 -8000f038: 00c45783 lhu a5,12(s0) -8000f03c: b7f7f793 andi a5,a5,-1153 -8000f040: 0807e793 ori a5,a5,128 -8000f044: 00f41623 sh a5,12(s0) -8000f048: 014c0533 add a0,s8,s4 -8000f04c: 41448a33 sub s4,s1,s4 -8000f050: 00942a23 sw s1,20(s0) -8000f054: 01442423 sw s4,8(s0) -8000f058: 01842823 sw s8,16(s0) -8000f05c: 00a42023 sw a0,0(s0) -8000f060: 00090493 mv s1,s2 -8000f064: 00090a13 mv s4,s2 -8000f068: 000a0613 mv a2,s4 -8000f06c: 000b8593 mv a1,s7 -8000f070: d4cff0ef jal ra,8000e5bc -8000f074: 00842703 lw a4,8(s0) -8000f078: 00042503 lw a0,0(s0) -8000f07c: 008aa783 lw a5,8(s5) -8000f080: 409704b3 sub s1,a4,s1 -8000f084: 01450533 add a0,a0,s4 -8000f088: 00942423 sw s1,8(s0) -8000f08c: 00a42023 sw a0,0(s0) -8000f090: 41278933 sub s2,a5,s2 -8000f094: 012aa423 sw s2,8(s5) -8000f098: 06090463 beqz s2,8000f100 <__ssprint_r+0x184> -8000f09c: 0049a903 lw s2,4(s3) -8000f0a0: 0009ab83 lw s7,0(s3) -8000f0a4: 00048a13 mv s4,s1 -8000f0a8: 00898993 addi s3,s3,8 -8000f0ac: fe0908e3 beqz s2,8000f09c <__ssprint_r+0x120> -8000f0b0: f0997ee3 bgeu s2,s1,8000efcc <__ssprint_r+0x50> -8000f0b4: 00090493 mv s1,s2 -8000f0b8: 00090a13 mv s4,s2 -8000f0bc: fadff06f j 8000f068 <__ssprint_r+0xec> -8000f0c0: 000b0513 mv a0,s6 -8000f0c4: e80ff0ef jal ra,8000e744 <_realloc_r> -8000f0c8: 00050c13 mv s8,a0 -8000f0cc: f6051ee3 bnez a0,8000f048 <__ssprint_r+0xcc> -8000f0d0: 01042583 lw a1,16(s0) -8000f0d4: 000b0513 mv a0,s6 -8000f0d8: 8fdf50ef jal ra,800049d4 <_free_r> -8000f0dc: 00c00793 li a5,12 -8000f0e0: 00fb2023 sw a5,0(s6) -8000f0e4: 00c45783 lhu a5,12(s0) -8000f0e8: fff00513 li a0,-1 -8000f0ec: 0407e793 ori a5,a5,64 -8000f0f0: 00f41623 sh a5,12(s0) -8000f0f4: 000aa423 sw zero,8(s5) -8000f0f8: 000aa223 sw zero,4(s5) -8000f0fc: 00c0006f j 8000f108 <__ssprint_r+0x18c> -8000f100: 000aa223 sw zero,4(s5) -8000f104: 00000513 li a0,0 -8000f108: 02c12083 lw ra,44(sp) -8000f10c: 02812403 lw s0,40(sp) -8000f110: 02412483 lw s1,36(sp) -8000f114: 02012903 lw s2,32(sp) -8000f118: 01c12983 lw s3,28(sp) -8000f11c: 01812a03 lw s4,24(sp) -8000f120: 01412a83 lw s5,20(sp) -8000f124: 01012b03 lw s6,16(sp) -8000f128: 00c12b83 lw s7,12(sp) -8000f12c: 00812c03 lw s8,8(sp) -8000f130: 03010113 addi sp,sp,48 -8000f134: 00008067 ret +8000eeb8 <__ssprint_r>: +8000eeb8: 00862783 lw a5,8(a2) +8000eebc: fd010113 addi sp,sp,-48 +8000eec0: 01512a23 sw s5,20(sp) +8000eec4: 02112623 sw ra,44(sp) +8000eec8: 02812423 sw s0,40(sp) +8000eecc: 02912223 sw s1,36(sp) +8000eed0: 03212023 sw s2,32(sp) +8000eed4: 01312e23 sw s3,28(sp) +8000eed8: 01412c23 sw s4,24(sp) +8000eedc: 01612823 sw s6,16(sp) +8000eee0: 01712623 sw s7,12(sp) +8000eee4: 01812423 sw s8,8(sp) +8000eee8: 00060a93 mv s5,a2 +8000eeec: 14078863 beqz a5,8000f03c <__ssprint_r+0x184> +8000eef0: 00050b13 mv s6,a0 +8000eef4: 00062983 lw s3,0(a2) +8000eef8: 0005a503 lw a0,0(a1) +8000eefc: 0085a483 lw s1,8(a1) +8000ef00: 00058413 mv s0,a1 +8000ef04: 0d40006f j 8000efd8 <__ssprint_r+0x120> +8000ef08: 00c45783 lhu a5,12(s0) +8000ef0c: 4807f713 andi a4,a5,1152 +8000ef10: 08070a63 beqz a4,8000efa4 <__ssprint_r+0xec> +8000ef14: 01442683 lw a3,20(s0) +8000ef18: 01042583 lw a1,16(s0) +8000ef1c: 00190713 addi a4,s2,1 +8000ef20: 00169493 slli s1,a3,0x1 +8000ef24: 00d486b3 add a3,s1,a3 +8000ef28: 01f6d493 srli s1,a3,0x1f +8000ef2c: 40b50a33 sub s4,a0,a1 +8000ef30: 00d484b3 add s1,s1,a3 +8000ef34: 4014d493 srai s1,s1,0x1 +8000ef38: 01470733 add a4,a4,s4 +8000ef3c: 00048613 mv a2,s1 +8000ef40: 00e4f663 bgeu s1,a4,8000ef4c <__ssprint_r+0x94> +8000ef44: 00070493 mv s1,a4 +8000ef48: 00070613 mv a2,a4 +8000ef4c: 4007f793 andi a5,a5,1024 +8000ef50: 0a078663 beqz a5,8000effc <__ssprint_r+0x144> +8000ef54: 00060593 mv a1,a2 +8000ef58: 000b0513 mv a0,s6 +8000ef5c: b89f80ef jal ra,80007ae4 <_malloc_r> +8000ef60: 00050c13 mv s8,a0 +8000ef64: 0a050a63 beqz a0,8000f018 <__ssprint_r+0x160> +8000ef68: 01042583 lw a1,16(s0) +8000ef6c: 000a0613 mv a2,s4 +8000ef70: c6cff0ef jal ra,8000e3dc +8000ef74: 00c45783 lhu a5,12(s0) +8000ef78: b7f7f793 andi a5,a5,-1153 +8000ef7c: 0807e793 ori a5,a5,128 +8000ef80: 00f41623 sh a5,12(s0) +8000ef84: 014c0533 add a0,s8,s4 +8000ef88: 41448a33 sub s4,s1,s4 +8000ef8c: 00942a23 sw s1,20(s0) +8000ef90: 01442423 sw s4,8(s0) +8000ef94: 01842823 sw s8,16(s0) +8000ef98: 00a42023 sw a0,0(s0) +8000ef9c: 00090493 mv s1,s2 +8000efa0: 00090a13 mv s4,s2 +8000efa4: 000a0613 mv a2,s4 +8000efa8: 000b8593 mv a1,s7 +8000efac: d4cff0ef jal ra,8000e4f8 +8000efb0: 00842703 lw a4,8(s0) +8000efb4: 00042503 lw a0,0(s0) +8000efb8: 008aa783 lw a5,8(s5) +8000efbc: 409704b3 sub s1,a4,s1 +8000efc0: 01450533 add a0,a0,s4 +8000efc4: 00942423 sw s1,8(s0) +8000efc8: 00a42023 sw a0,0(s0) +8000efcc: 41278933 sub s2,a5,s2 +8000efd0: 012aa423 sw s2,8(s5) +8000efd4: 06090463 beqz s2,8000f03c <__ssprint_r+0x184> +8000efd8: 0049a903 lw s2,4(s3) +8000efdc: 0009ab83 lw s7,0(s3) +8000efe0: 00048a13 mv s4,s1 +8000efe4: 00898993 addi s3,s3,8 +8000efe8: fe0908e3 beqz s2,8000efd8 <__ssprint_r+0x120> +8000efec: f0997ee3 bgeu s2,s1,8000ef08 <__ssprint_r+0x50> +8000eff0: 00090493 mv s1,s2 +8000eff4: 00090a13 mv s4,s2 +8000eff8: fadff06f j 8000efa4 <__ssprint_r+0xec> +8000effc: 000b0513 mv a0,s6 +8000f000: e80ff0ef jal ra,8000e680 <_realloc_r> +8000f004: 00050c13 mv s8,a0 +8000f008: f6051ee3 bnez a0,8000ef84 <__ssprint_r+0xcc> +8000f00c: 01042583 lw a1,16(s0) +8000f010: 000b0513 mv a0,s6 +8000f014: 8fdf50ef jal ra,80004910 <_free_r> +8000f018: 00c00793 li a5,12 +8000f01c: 00fb2023 sw a5,0(s6) +8000f020: 00c45783 lhu a5,12(s0) +8000f024: fff00513 li a0,-1 +8000f028: 0407e793 ori a5,a5,64 +8000f02c: 00f41623 sh a5,12(s0) +8000f030: 000aa423 sw zero,8(s5) +8000f034: 000aa223 sw zero,4(s5) +8000f038: 00c0006f j 8000f044 <__ssprint_r+0x18c> +8000f03c: 000aa223 sw zero,4(s5) +8000f040: 00000513 li a0,0 +8000f044: 02c12083 lw ra,44(sp) +8000f048: 02812403 lw s0,40(sp) +8000f04c: 02412483 lw s1,36(sp) +8000f050: 02012903 lw s2,32(sp) +8000f054: 01c12983 lw s3,28(sp) +8000f058: 01812a03 lw s4,24(sp) +8000f05c: 01412a83 lw s5,20(sp) +8000f060: 01012b03 lw s6,16(sp) +8000f064: 00c12b83 lw s7,12(sp) +8000f068: 00812c03 lw s8,8(sp) +8000f06c: 03010113 addi sp,sp,48 +8000f070: 00008067 ret -8000f138 <_svfiprintf_r>: -8000f138: 00c5d783 lhu a5,12(a1) -8000f13c: ed010113 addi sp,sp,-304 -8000f140: 11412c23 sw s4,280(sp) -8000f144: 11612823 sw s6,272(sp) -8000f148: 11a12023 sw s10,256(sp) -8000f14c: 12112623 sw ra,300(sp) -8000f150: 12812423 sw s0,296(sp) -8000f154: 12912223 sw s1,292(sp) -8000f158: 13212023 sw s2,288(sp) -8000f15c: 11312e23 sw s3,284(sp) -8000f160: 11512a23 sw s5,276(sp) -8000f164: 11712623 sw s7,268(sp) -8000f168: 11812423 sw s8,264(sp) -8000f16c: 11912223 sw s9,260(sp) -8000f170: 0fb12e23 sw s11,252(sp) -8000f174: 0807f793 andi a5,a5,128 -8000f178: 00d12623 sw a3,12(sp) -8000f17c: 00058a13 mv s4,a1 -8000f180: 00050b13 mv s6,a0 -8000f184: 00060d13 mv s10,a2 -8000f188: 00078663 beqz a5,8000f194 <_svfiprintf_r+0x5c> -8000f18c: 0105a783 lw a5,16(a1) -8000f190: 5e0784e3 beqz a5,8000ff78 <_svfiprintf_r+0xe40> -8000f194: 800157b7 lui a5,0x80015 -8000f198: 04c10a93 addi s5,sp,76 -8000f19c: 50878793 addi a5,a5,1288 # 80015508 <__BSS_END__+0xffffe8cc> -8000f1a0: 80015bb7 lui s7,0x80015 -8000f1a4: 800154b7 lui s1,0x80015 -8000f1a8: 000d0993 mv s3,s10 -8000f1ac: 05512023 sw s5,64(sp) -8000f1b0: 04012423 sw zero,72(sp) -8000f1b4: 04012223 sw zero,68(sp) -8000f1b8: 00012a23 sw zero,20(sp) -8000f1bc: 00012c23 sw zero,24(sp) -8000f1c0: 02012023 sw zero,32(sp) -8000f1c4: 00012e23 sw zero,28(sp) -8000f1c8: 00012423 sw zero,8(sp) -8000f1cc: 00f12823 sw a5,16(sp) -8000f1d0: 674b8b93 addi s7,s7,1652 # 80015674 <__BSS_END__+0xffffea38> -8000f1d4: 68448493 addi s1,s1,1668 # 80015684 <__BSS_END__+0xffffea48> -8000f1d8: 000a8d13 mv s10,s5 -8000f1dc: 0009c783 lbu a5,0(s3) -8000f1e0: 20078c63 beqz a5,8000f3f8 <_svfiprintf_r+0x2c0> -8000f1e4: 00098413 mv s0,s3 -8000f1e8: 02500693 li a3,37 -8000f1ec: 2ad78863 beq a5,a3,8000f49c <_svfiprintf_r+0x364> -8000f1f0: 00144783 lbu a5,1(s0) -8000f1f4: 00140413 addi s0,s0,1 -8000f1f8: fe079ae3 bnez a5,8000f1ec <_svfiprintf_r+0xb4> -8000f1fc: 41340c33 sub s8,s0,s3 -8000f200: 1f340c63 beq s0,s3,8000f3f8 <_svfiprintf_r+0x2c0> -8000f204: 04812683 lw a3,72(sp) -8000f208: 04412783 lw a5,68(sp) -8000f20c: 013d2023 sw s3,0(s10) -8000f210: 018686b3 add a3,a3,s8 -8000f214: 00178793 addi a5,a5,1 -8000f218: 018d2223 sw s8,4(s10) -8000f21c: 04d12423 sw a3,72(sp) -8000f220: 04f12223 sw a5,68(sp) -8000f224: 00700693 li a3,7 -8000f228: 008d0d13 addi s10,s10,8 -8000f22c: 28f6c063 blt a3,a5,8000f4ac <_svfiprintf_r+0x374> -8000f230: 00812703 lw a4,8(sp) -8000f234: 00044783 lbu a5,0(s0) -8000f238: 01870733 add a4,a4,s8 -8000f23c: 00e12423 sw a4,8(sp) -8000f240: 1a078c63 beqz a5,8000f3f8 <_svfiprintf_r+0x2c0> -8000f244: fff00893 li a7,-1 -8000f248: 00144683 lbu a3,1(s0) -8000f24c: 00140993 addi s3,s0,1 -8000f250: 02010da3 sb zero,59(sp) -8000f254: 00012223 sw zero,4(sp) -8000f258: 00000913 li s2,0 -8000f25c: 05a00c13 li s8,90 -8000f260: 00900c93 li s9,9 -8000f264: 02a00593 li a1,42 -8000f268: 00088413 mv s0,a7 -8000f26c: 00198993 addi s3,s3,1 -8000f270: fe068793 addi a5,a3,-32 -8000f274: 04fc6863 bltu s8,a5,8000f2c4 <_svfiprintf_r+0x18c> -8000f278: 01012703 lw a4,16(sp) -8000f27c: 00279793 slli a5,a5,0x2 -8000f280: 00e787b3 add a5,a5,a4 -8000f284: 0007a783 lw a5,0(a5) -8000f288: 00078067 jr a5 -8000f28c: 00012223 sw zero,4(sp) -8000f290: fd068793 addi a5,a3,-48 -8000f294: 00412603 lw a2,4(sp) -8000f298: 0009c683 lbu a3,0(s3) -8000f29c: 00198993 addi s3,s3,1 -8000f2a0: 00261713 slli a4,a2,0x2 -8000f2a4: 00c70733 add a4,a4,a2 -8000f2a8: 00171713 slli a4,a4,0x1 -8000f2ac: 00e787b3 add a5,a5,a4 -8000f2b0: 00f12223 sw a5,4(sp) -8000f2b4: fd068793 addi a5,a3,-48 -8000f2b8: fcfcfee3 bgeu s9,a5,8000f294 <_svfiprintf_r+0x15c> -8000f2bc: fe068793 addi a5,a3,-32 -8000f2c0: fafc7ce3 bgeu s8,a5,8000f278 <_svfiprintf_r+0x140> -8000f2c4: 12068a63 beqz a3,8000f3f8 <_svfiprintf_r+0x2c0> -8000f2c8: 08d10623 sb a3,140(sp) -8000f2cc: 02010da3 sb zero,59(sp) -8000f2d0: 00100c13 li s8,1 -8000f2d4: 00100c93 li s9,1 -8000f2d8: 08c10413 addi s0,sp,140 -8000f2dc: 00000893 li a7,0 -8000f2e0: 00297f13 andi t5,s2,2 -8000f2e4: 000f0463 beqz t5,8000f2ec <_svfiprintf_r+0x1b4> -8000f2e8: 002c0c13 addi s8,s8,2 -8000f2ec: 08497e93 andi t4,s2,132 -8000f2f0: 04812783 lw a5,72(sp) -8000f2f4: 04412603 lw a2,68(sp) -8000f2f8: 000e9863 bnez t4,8000f308 <_svfiprintf_r+0x1d0> +8000f074 <_svfiprintf_r>: +8000f074: 00c5d783 lhu a5,12(a1) +8000f078: ed010113 addi sp,sp,-304 +8000f07c: 11412c23 sw s4,280(sp) +8000f080: 11612823 sw s6,272(sp) +8000f084: 11a12023 sw s10,256(sp) +8000f088: 12112623 sw ra,300(sp) +8000f08c: 12812423 sw s0,296(sp) +8000f090: 12912223 sw s1,292(sp) +8000f094: 13212023 sw s2,288(sp) +8000f098: 11312e23 sw s3,284(sp) +8000f09c: 11512a23 sw s5,276(sp) +8000f0a0: 11712623 sw s7,268(sp) +8000f0a4: 11812423 sw s8,264(sp) +8000f0a8: 11912223 sw s9,260(sp) +8000f0ac: 0fb12e23 sw s11,252(sp) +8000f0b0: 0807f793 andi a5,a5,128 +8000f0b4: 00d12623 sw a3,12(sp) +8000f0b8: 00058a13 mv s4,a1 +8000f0bc: 00050b13 mv s6,a0 +8000f0c0: 00060d13 mv s10,a2 +8000f0c4: 00078663 beqz a5,8000f0d0 <_svfiprintf_r+0x5c> +8000f0c8: 0105a783 lw a5,16(a1) +8000f0cc: 5e0784e3 beqz a5,8000feb4 <_svfiprintf_r+0xe40> +8000f0d0: 800157b7 lui a5,0x80015 +8000f0d4: 04c10a93 addi s5,sp,76 +8000f0d8: 43078793 addi a5,a5,1072 # 80015430 <__BSS_END__+0xffffe7f4> +8000f0dc: 80015bb7 lui s7,0x80015 +8000f0e0: 800154b7 lui s1,0x80015 +8000f0e4: 000d0993 mv s3,s10 +8000f0e8: 05512023 sw s5,64(sp) +8000f0ec: 04012423 sw zero,72(sp) +8000f0f0: 04012223 sw zero,68(sp) +8000f0f4: 00012a23 sw zero,20(sp) +8000f0f8: 00012c23 sw zero,24(sp) +8000f0fc: 02012023 sw zero,32(sp) +8000f100: 00012e23 sw zero,28(sp) +8000f104: 00012423 sw zero,8(sp) +8000f108: 00f12823 sw a5,16(sp) +8000f10c: 59cb8b93 addi s7,s7,1436 # 8001559c <__BSS_END__+0xffffe960> +8000f110: 5ac48493 addi s1,s1,1452 # 800155ac <__BSS_END__+0xffffe970> +8000f114: 000a8d13 mv s10,s5 +8000f118: 0009c783 lbu a5,0(s3) +8000f11c: 20078c63 beqz a5,8000f334 <_svfiprintf_r+0x2c0> +8000f120: 00098413 mv s0,s3 +8000f124: 02500693 li a3,37 +8000f128: 2ad78863 beq a5,a3,8000f3d8 <_svfiprintf_r+0x364> +8000f12c: 00144783 lbu a5,1(s0) +8000f130: 00140413 addi s0,s0,1 +8000f134: fe079ae3 bnez a5,8000f128 <_svfiprintf_r+0xb4> +8000f138: 41340c33 sub s8,s0,s3 +8000f13c: 1f340c63 beq s0,s3,8000f334 <_svfiprintf_r+0x2c0> +8000f140: 04812683 lw a3,72(sp) +8000f144: 04412783 lw a5,68(sp) +8000f148: 013d2023 sw s3,0(s10) +8000f14c: 018686b3 add a3,a3,s8 +8000f150: 00178793 addi a5,a5,1 +8000f154: 018d2223 sw s8,4(s10) +8000f158: 04d12423 sw a3,72(sp) +8000f15c: 04f12223 sw a5,68(sp) +8000f160: 00700693 li a3,7 +8000f164: 008d0d13 addi s10,s10,8 +8000f168: 28f6c063 blt a3,a5,8000f3e8 <_svfiprintf_r+0x374> +8000f16c: 00812703 lw a4,8(sp) +8000f170: 00044783 lbu a5,0(s0) +8000f174: 01870733 add a4,a4,s8 +8000f178: 00e12423 sw a4,8(sp) +8000f17c: 1a078c63 beqz a5,8000f334 <_svfiprintf_r+0x2c0> +8000f180: fff00893 li a7,-1 +8000f184: 00144683 lbu a3,1(s0) +8000f188: 00140993 addi s3,s0,1 +8000f18c: 02010da3 sb zero,59(sp) +8000f190: 00012223 sw zero,4(sp) +8000f194: 00000913 li s2,0 +8000f198: 05a00c13 li s8,90 +8000f19c: 00900c93 li s9,9 +8000f1a0: 02a00593 li a1,42 +8000f1a4: 00088413 mv s0,a7 +8000f1a8: 00198993 addi s3,s3,1 +8000f1ac: fe068793 addi a5,a3,-32 +8000f1b0: 04fc6863 bltu s8,a5,8000f200 <_svfiprintf_r+0x18c> +8000f1b4: 01012703 lw a4,16(sp) +8000f1b8: 00279793 slli a5,a5,0x2 +8000f1bc: 00e787b3 add a5,a5,a4 +8000f1c0: 0007a783 lw a5,0(a5) +8000f1c4: 00078067 jr a5 +8000f1c8: 00012223 sw zero,4(sp) +8000f1cc: fd068793 addi a5,a3,-48 +8000f1d0: 00412603 lw a2,4(sp) +8000f1d4: 0009c683 lbu a3,0(s3) +8000f1d8: 00198993 addi s3,s3,1 +8000f1dc: 00261713 slli a4,a2,0x2 +8000f1e0: 00c70733 add a4,a4,a2 +8000f1e4: 00171713 slli a4,a4,0x1 +8000f1e8: 00e787b3 add a5,a5,a4 +8000f1ec: 00f12223 sw a5,4(sp) +8000f1f0: fd068793 addi a5,a3,-48 +8000f1f4: fcfcfee3 bgeu s9,a5,8000f1d0 <_svfiprintf_r+0x15c> +8000f1f8: fe068793 addi a5,a3,-32 +8000f1fc: fafc7ce3 bgeu s8,a5,8000f1b4 <_svfiprintf_r+0x140> +8000f200: 12068a63 beqz a3,8000f334 <_svfiprintf_r+0x2c0> +8000f204: 08d10623 sb a3,140(sp) +8000f208: 02010da3 sb zero,59(sp) +8000f20c: 00100c13 li s8,1 +8000f210: 00100c93 li s9,1 +8000f214: 08c10413 addi s0,sp,140 +8000f218: 00000893 li a7,0 +8000f21c: 00297f13 andi t5,s2,2 +8000f220: 000f0463 beqz t5,8000f228 <_svfiprintf_r+0x1b4> +8000f224: 002c0c13 addi s8,s8,2 +8000f228: 08497e93 andi t4,s2,132 +8000f22c: 04812783 lw a5,72(sp) +8000f230: 04412603 lw a2,68(sp) +8000f234: 000e9863 bnez t4,8000f244 <_svfiprintf_r+0x1d0> +8000f238: 00412703 lw a4,4(sp) +8000f23c: 41870db3 sub s11,a4,s8 +8000f240: 7bb04a63 bgtz s11,8000f9f4 <_svfiprintf_r+0x980> +8000f244: 03b14503 lbu a0,59(sp) +8000f248: 00160593 addi a1,a2,1 +8000f24c: 008d0693 addi a3,s10,8 +8000f250: 04050063 beqz a0,8000f290 <_svfiprintf_r+0x21c> +8000f254: 03b10513 addi a0,sp,59 +8000f258: 00178793 addi a5,a5,1 +8000f25c: 00ad2023 sw a0,0(s10) +8000f260: 00100513 li a0,1 +8000f264: 00ad2223 sw a0,4(s10) +8000f268: 04f12423 sw a5,72(sp) +8000f26c: 04b12223 sw a1,68(sp) +8000f270: 00700513 li a0,7 +8000f274: 0ab540e3 blt a0,a1,8000fb14 <_svfiprintf_r+0xaa0> +8000f278: 00260f93 addi t6,a2,2 +8000f27c: 010d0513 addi a0,s10,16 +8000f280: 00058613 mv a2,a1 +8000f284: 00068d13 mv s10,a3 +8000f288: 000f8593 mv a1,t6 +8000f28c: 00050693 mv a3,a0 +8000f290: 020f0c63 beqz t5,8000f2c8 <_svfiprintf_r+0x254> +8000f294: 03c10613 addi a2,sp,60 +8000f298: 00278793 addi a5,a5,2 +8000f29c: 00cd2023 sw a2,0(s10) +8000f2a0: 00200613 li a2,2 +8000f2a4: 00cd2223 sw a2,4(s10) +8000f2a8: 04f12423 sw a5,72(sp) +8000f2ac: 04b12223 sw a1,68(sp) +8000f2b0: 00700713 li a4,7 +8000f2b4: 0ab742e3 blt a4,a1,8000fb58 <_svfiprintf_r+0xae4> +8000f2b8: 00058613 mv a2,a1 +8000f2bc: 00068d13 mv s10,a3 +8000f2c0: 00158593 addi a1,a1,1 +8000f2c4: 00868693 addi a3,a3,8 +8000f2c8: 08000513 li a0,128 +8000f2cc: 54ae8c63 beq t4,a0,8000f824 <_svfiprintf_r+0x7b0> +8000f2d0: 41988db3 sub s11,a7,s9 +8000f2d4: 63b04463 bgtz s11,8000f8fc <_svfiprintf_r+0x888> +8000f2d8: 00fc87b3 add a5,s9,a5 +8000f2dc: 008d2023 sw s0,0(s10) +8000f2e0: 019d2223 sw s9,4(s10) +8000f2e4: 04f12423 sw a5,72(sp) +8000f2e8: 04b12223 sw a1,68(sp) +8000f2ec: 00700713 li a4,7 +8000f2f0: 6cb74263 blt a4,a1,8000f9b4 <_svfiprintf_r+0x940> +8000f2f4: 00497313 andi t1,s2,4 +8000f2f8: 00030863 beqz t1,8000f308 <_svfiprintf_r+0x294> 8000f2fc: 00412703 lw a4,4(sp) -8000f300: 41870db3 sub s11,a4,s8 -8000f304: 7bb04a63 bgtz s11,8000fab8 <_svfiprintf_r+0x980> -8000f308: 03b14503 lbu a0,59(sp) -8000f30c: 00160593 addi a1,a2,1 -8000f310: 008d0693 addi a3,s10,8 -8000f314: 04050063 beqz a0,8000f354 <_svfiprintf_r+0x21c> -8000f318: 03b10513 addi a0,sp,59 -8000f31c: 00178793 addi a5,a5,1 -8000f320: 00ad2023 sw a0,0(s10) -8000f324: 00100513 li a0,1 -8000f328: 00ad2223 sw a0,4(s10) -8000f32c: 04f12423 sw a5,72(sp) -8000f330: 04b12223 sw a1,68(sp) -8000f334: 00700513 li a0,7 -8000f338: 0ab540e3 blt a0,a1,8000fbd8 <_svfiprintf_r+0xaa0> -8000f33c: 00260f93 addi t6,a2,2 -8000f340: 010d0513 addi a0,s10,16 -8000f344: 00058613 mv a2,a1 -8000f348: 00068d13 mv s10,a3 -8000f34c: 000f8593 mv a1,t6 -8000f350: 00050693 mv a3,a0 -8000f354: 020f0c63 beqz t5,8000f38c <_svfiprintf_r+0x254> -8000f358: 03c10613 addi a2,sp,60 -8000f35c: 00278793 addi a5,a5,2 -8000f360: 00cd2023 sw a2,0(s10) -8000f364: 00200613 li a2,2 -8000f368: 00cd2223 sw a2,4(s10) -8000f36c: 04f12423 sw a5,72(sp) -8000f370: 04b12223 sw a1,68(sp) -8000f374: 00700713 li a4,7 -8000f378: 0ab742e3 blt a4,a1,8000fc1c <_svfiprintf_r+0xae4> -8000f37c: 00058613 mv a2,a1 -8000f380: 00068d13 mv s10,a3 -8000f384: 00158593 addi a1,a1,1 -8000f388: 00868693 addi a3,a3,8 -8000f38c: 08000513 li a0,128 -8000f390: 54ae8c63 beq t4,a0,8000f8e8 <_svfiprintf_r+0x7b0> -8000f394: 41988db3 sub s11,a7,s9 -8000f398: 63b04463 bgtz s11,8000f9c0 <_svfiprintf_r+0x888> -8000f39c: 00fc87b3 add a5,s9,a5 -8000f3a0: 008d2023 sw s0,0(s10) -8000f3a4: 019d2223 sw s9,4(s10) -8000f3a8: 04f12423 sw a5,72(sp) -8000f3ac: 04b12223 sw a1,68(sp) -8000f3b0: 00700713 li a4,7 -8000f3b4: 6cb74263 blt a4,a1,8000fa78 <_svfiprintf_r+0x940> -8000f3b8: 00497313 andi t1,s2,4 -8000f3bc: 00030863 beqz t1,8000f3cc <_svfiprintf_r+0x294> -8000f3c0: 00412703 lw a4,4(sp) -8000f3c4: 41870cb3 sub s9,a4,s8 -8000f3c8: 099048e3 bgtz s9,8000fc58 <_svfiprintf_r+0xb20> -8000f3cc: 00412403 lw s0,4(sp) -8000f3d0: 01845463 bge s0,s8,8000f3d8 <_svfiprintf_r+0x2a0> -8000f3d4: 000c0413 mv s0,s8 -8000f3d8: 00812703 lw a4,8(sp) -8000f3dc: 00870733 add a4,a4,s0 -8000f3e0: 00e12423 sw a4,8(sp) -8000f3e4: 6a079a63 bnez a5,8000fa98 <_svfiprintf_r+0x960> -8000f3e8: 0009c783 lbu a5,0(s3) -8000f3ec: 04012223 sw zero,68(sp) -8000f3f0: 000a8d13 mv s10,s5 -8000f3f4: de0798e3 bnez a5,8000f1e4 <_svfiprintf_r+0xac> -8000f3f8: 04812783 lw a5,72(sp) -8000f3fc: 56079ee3 bnez a5,80010178 <_svfiprintf_r+0x1040> -8000f400: 00ca5783 lhu a5,12(s4) -8000f404: 0407f793 andi a5,a5,64 -8000f408: 5a0794e3 bnez a5,800101b0 <_svfiprintf_r+0x1078> -8000f40c: 12c12083 lw ra,300(sp) -8000f410: 12812403 lw s0,296(sp) -8000f414: 00812503 lw a0,8(sp) -8000f418: 12412483 lw s1,292(sp) -8000f41c: 12012903 lw s2,288(sp) -8000f420: 11c12983 lw s3,284(sp) -8000f424: 11812a03 lw s4,280(sp) -8000f428: 11412a83 lw s5,276(sp) -8000f42c: 11012b03 lw s6,272(sp) -8000f430: 10c12b83 lw s7,268(sp) -8000f434: 10812c03 lw s8,264(sp) -8000f438: 10412c83 lw s9,260(sp) -8000f43c: 10012d03 lw s10,256(sp) -8000f440: 0fc12d83 lw s11,252(sp) -8000f444: 13010113 addi sp,sp,304 -8000f448: 00008067 ret -8000f44c: 000b0513 mv a0,s6 -8000f450: d58f80ef jal ra,800079a8 <_localeconv_r> -8000f454: 00452783 lw a5,4(a0) -8000f458: 00078513 mv a0,a5 -8000f45c: 00f12e23 sw a5,28(sp) -8000f460: d00fa0ef jal ra,80009960 -8000f464: 00050793 mv a5,a0 -8000f468: 000b0513 mv a0,s6 -8000f46c: 00078d93 mv s11,a5 -8000f470: 02f12023 sw a5,32(sp) -8000f474: d34f80ef jal ra,800079a8 <_localeconv_r> -8000f478: 00852783 lw a5,8(a0) -8000f47c: 02a00593 li a1,42 -8000f480: 00f12c23 sw a5,24(sp) -8000f484: 1e0d98e3 bnez s11,8000fe74 <_svfiprintf_r+0xd3c> -8000f488: 0009c683 lbu a3,0(s3) -8000f48c: de1ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f490: 0009c683 lbu a3,0(s3) -8000f494: 02096913 ori s2,s2,32 -8000f498: dd5ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f49c: 41340c33 sub s8,s0,s3 -8000f4a0: d73412e3 bne s0,s3,8000f204 <_svfiprintf_r+0xcc> -8000f4a4: 00044783 lbu a5,0(s0) -8000f4a8: d99ff06f j 8000f240 <_svfiprintf_r+0x108> -8000f4ac: 04010613 addi a2,sp,64 -8000f4b0: 000a0593 mv a1,s4 -8000f4b4: 000b0513 mv a0,s6 -8000f4b8: ac5ff0ef jal ra,8000ef7c <__ssprint_r> -8000f4bc: f40512e3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000f4c0: 000a8d13 mv s10,s5 -8000f4c4: d6dff06f j 8000f230 <_svfiprintf_r+0xf8> -8000f4c8: 00c12783 lw a5,12(sp) -8000f4cc: 00040893 mv a7,s0 -8000f4d0: 02010da3 sb zero,59(sp) -8000f4d4: 0007a403 lw s0,0(a5) -8000f4d8: 00478d93 addi s11,a5,4 -8000f4dc: 380404e3 beqz s0,80010064 <_svfiprintf_r+0xf2c> -8000f4e0: fff00793 li a5,-1 -8000f4e4: 26f88ee3 beq a7,a5,8000ff60 <_svfiprintf_r+0xe28> -8000f4e8: 00088613 mv a2,a7 -8000f4ec: 00000593 li a1,0 -8000f4f0: 00040513 mv a0,s0 -8000f4f4: 01112623 sw a7,12(sp) -8000f4f8: e49f80ef jal ra,80008340 -8000f4fc: 00c12883 lw a7,12(sp) -8000f500: 480506e3 beqz a0,8001018c <_svfiprintf_r+0x1054> -8000f504: 40850cb3 sub s9,a0,s0 -8000f508: 01b12623 sw s11,12(sp) -8000f50c: 00000893 li a7,0 -8000f510: 0940006f j 8000f5a4 <_svfiprintf_r+0x46c> -8000f514: 00c12703 lw a4,12(sp) -8000f518: 02010da3 sb zero,59(sp) -8000f51c: 00100c13 li s8,1 -8000f520: 00072783 lw a5,0(a4) -8000f524: 00470713 addi a4,a4,4 -8000f528: 00e12623 sw a4,12(sp) -8000f52c: 08f10623 sb a5,140(sp) -8000f530: 00100c93 li s9,1 -8000f534: 08c10413 addi s0,sp,140 -8000f538: da5ff06f j 8000f2dc <_svfiprintf_r+0x1a4> -8000f53c: 02097793 andi a5,s2,32 -8000f540: 00040893 mv a7,s0 -8000f544: 0e078e63 beqz a5,8000f640 <_svfiprintf_r+0x508> -8000f548: 00c12783 lw a5,12(sp) -8000f54c: 00778793 addi a5,a5,7 -8000f550: ff87f793 andi a5,a5,-8 -8000f554: 0047a683 lw a3,4(a5) -8000f558: 0007ac83 lw s9,0(a5) -8000f55c: 00878793 addi a5,a5,8 -8000f560: 00f12623 sw a5,12(sp) -8000f564: 00068c13 mv s8,a3 -8000f568: 1006c463 bltz a3,8000f670 <_svfiprintf_r+0x538> -8000f56c: fff00693 li a3,-1 -8000f570: 00090d93 mv s11,s2 -8000f574: 00d88863 beq a7,a3,8000f584 <_svfiprintf_r+0x44c> -8000f578: 018ce6b3 or a3,s9,s8 -8000f57c: f7f97d93 andi s11,s2,-129 -8000f580: 76068e63 beqz a3,8000fcfc <_svfiprintf_r+0xbc4> -8000f584: 000c1ce3 bnez s8,8000fd9c <_svfiprintf_r+0xc64> -8000f588: 00900693 li a3,9 -8000f58c: 0196e8e3 bltu a3,s9,8000fd9c <_svfiprintf_r+0xc64> -8000f590: 030c8793 addi a5,s9,48 -8000f594: 0ef107a3 sb a5,239(sp) -8000f598: 000d8913 mv s2,s11 -8000f59c: 00100c93 li s9,1 -8000f5a0: 0ef10413 addi s0,sp,239 -8000f5a4: 00088c13 mv s8,a7 -8000f5a8: 0198d463 bge a7,s9,8000f5b0 <_svfiprintf_r+0x478> -8000f5ac: 000c8c13 mv s8,s9 -8000f5b0: 03b14783 lbu a5,59(sp) -8000f5b4: 00f037b3 snez a5,a5 -8000f5b8: 00fc0c33 add s8,s8,a5 -8000f5bc: d25ff06f j 8000f2e0 <_svfiprintf_r+0x1a8> -8000f5c0: 00040893 mv a7,s0 -8000f5c4: 01096913 ori s2,s2,16 -8000f5c8: 02097793 andi a5,s2,32 -8000f5cc: 74078463 beqz a5,8000fd14 <_svfiprintf_r+0xbdc> -8000f5d0: 00c12783 lw a5,12(sp) -8000f5d4: 00778793 addi a5,a5,7 -8000f5d8: ff87f793 andi a5,a5,-8 -8000f5dc: 0007ac83 lw s9,0(a5) -8000f5e0: 0047ac03 lw s8,4(a5) -8000f5e4: 00878793 addi a5,a5,8 -8000f5e8: 00f12623 sw a5,12(sp) -8000f5ec: bff97d93 andi s11,s2,-1025 -8000f5f0: 00000693 li a3,0 -8000f5f4: 02010da3 sb zero,59(sp) -8000f5f8: fff00613 li a2,-1 -8000f5fc: 08c88e63 beq a7,a2,8000f698 <_svfiprintf_r+0x560> -8000f600: 018ce633 or a2,s9,s8 -8000f604: f7fdf913 andi s2,s11,-129 -8000f608: 4a061463 bnez a2,8000fab0 <_svfiprintf_r+0x978> -8000f60c: 28089263 bnez a7,8000f890 <_svfiprintf_r+0x758> -8000f610: 6e069a63 bnez a3,8000fd04 <_svfiprintf_r+0xbcc> -8000f614: 001dfc93 andi s9,s11,1 -8000f618: 0f010413 addi s0,sp,240 -8000f61c: f80c84e3 beqz s9,8000f5a4 <_svfiprintf_r+0x46c> -8000f620: 03000793 li a5,48 -8000f624: 0ef107a3 sb a5,239(sp) -8000f628: 0ef10413 addi s0,sp,239 -8000f62c: f79ff06f j 8000f5a4 <_svfiprintf_r+0x46c> -8000f630: 01096913 ori s2,s2,16 -8000f634: 02097793 andi a5,s2,32 -8000f638: 00040893 mv a7,s0 -8000f63c: f00796e3 bnez a5,8000f548 <_svfiprintf_r+0x410> -8000f640: 00c12703 lw a4,12(sp) -8000f644: 01097793 andi a5,s2,16 -8000f648: 00470693 addi a3,a4,4 -8000f64c: 040792e3 bnez a5,8000fe90 <_svfiprintf_r+0xd58> -8000f650: 04097793 andi a5,s2,64 -8000f654: 260786e3 beqz a5,800100c0 <_svfiprintf_r+0xf88> -8000f658: 00c12783 lw a5,12(sp) -8000f65c: 00d12623 sw a3,12(sp) -8000f660: 00079c83 lh s9,0(a5) -8000f664: 41fcdc13 srai s8,s9,0x1f -8000f668: 000c0693 mv a3,s8 -8000f66c: f006d0e3 bgez a3,8000f56c <_svfiprintf_r+0x434> -8000f670: 019036b3 snez a3,s9 -8000f674: 41800eb3 neg t4,s8 -8000f678: 40de8c33 sub s8,t4,a3 -8000f67c: 02d00693 li a3,45 -8000f680: 02d10da3 sb a3,59(sp) -8000f684: fff00613 li a2,-1 -8000f688: 41900cb3 neg s9,s9 -8000f68c: 00090d93 mv s11,s2 -8000f690: 00100693 li a3,1 -8000f694: f6c896e3 bne a7,a2,8000f600 <_svfiprintf_r+0x4c8> -8000f698: 00100613 li a2,1 -8000f69c: eec684e3 beq a3,a2,8000f584 <_svfiprintf_r+0x44c> -8000f6a0: 00200613 li a2,2 -8000f6a4: 20c68063 beq a3,a2,8000f8a4 <_svfiprintf_r+0x76c> -8000f6a8: 0f010413 addi s0,sp,240 -8000f6ac: 01dc1793 slli a5,s8,0x1d -8000f6b0: 007cf693 andi a3,s9,7 -8000f6b4: 003cdc93 srli s9,s9,0x3 -8000f6b8: 03068693 addi a3,a3,48 -8000f6bc: 0197ecb3 or s9,a5,s9 -8000f6c0: 003c5c13 srli s8,s8,0x3 -8000f6c4: fed40fa3 sb a3,-1(s0) -8000f6c8: 018ce7b3 or a5,s9,s8 -8000f6cc: 00040593 mv a1,s0 -8000f6d0: fff40413 addi s0,s0,-1 -8000f6d4: fc079ce3 bnez a5,8000f6ac <_svfiprintf_r+0x574> -8000f6d8: 001df793 andi a5,s11,1 -8000f6dc: 1e078e63 beqz a5,8000f8d8 <_svfiprintf_r+0x7a0> -8000f6e0: 03000793 li a5,48 -8000f6e4: 1ef68a63 beq a3,a5,8000f8d8 <_svfiprintf_r+0x7a0> -8000f6e8: ffe58593 addi a1,a1,-2 -8000f6ec: fef40fa3 sb a5,-1(s0) -8000f6f0: 0f010793 addi a5,sp,240 -8000f6f4: 40b78cb3 sub s9,a5,a1 -8000f6f8: 000d8913 mv s2,s11 -8000f6fc: 00058413 mv s0,a1 -8000f700: ea5ff06f j 8000f5a4 <_svfiprintf_r+0x46c> -8000f704: 00040893 mv a7,s0 -8000f708: 01096d93 ori s11,s2,16 -8000f70c: 020df793 andi a5,s11,32 -8000f710: 62078863 beqz a5,8000fd40 <_svfiprintf_r+0xc08> -8000f714: 00c12783 lw a5,12(sp) -8000f718: 00100693 li a3,1 -8000f71c: 00778913 addi s2,a5,7 -8000f720: ff897913 andi s2,s2,-8 -8000f724: 00890793 addi a5,s2,8 -8000f728: 00092c83 lw s9,0(s2) -8000f72c: 00492c03 lw s8,4(s2) -8000f730: 00f12623 sw a5,12(sp) -8000f734: ec1ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> -8000f738: 00c12783 lw a5,12(sp) -8000f73c: ffff86b7 lui a3,0xffff8 -8000f740: 8306c693 xori a3,a3,-2000 -8000f744: 0007ac83 lw s9,0(a5) -8000f748: 00478793 addi a5,a5,4 -8000f74c: 00f12623 sw a5,12(sp) -8000f750: 800157b7 lui a5,0x80015 -8000f754: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -8000f758: 02d11e23 sh a3,60(sp) -8000f75c: 00040893 mv a7,s0 -8000f760: 00000c13 li s8,0 -8000f764: 00296d93 ori s11,s2,2 -8000f768: 00f12a23 sw a5,20(sp) -8000f76c: 00200693 li a3,2 -8000f770: e85ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> -8000f774: 0009c683 lbu a3,0(s3) -8000f778: 08096913 ori s2,s2,128 -8000f77c: af1ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f780: 0009c683 lbu a3,0(s3) -8000f784: 00198713 addi a4,s3,1 -8000f788: 22b68ae3 beq a3,a1,800101bc <_svfiprintf_r+0x1084> -8000f78c: fd068793 addi a5,a3,-48 # ffff7fd0 <__BSS_END__+0x7ffe1394> -8000f790: 00070993 mv s3,a4 -8000f794: 00000413 li s0,0 -8000f798: acfcece3 bltu s9,a5,8000f270 <_svfiprintf_r+0x138> -8000f79c: 0009c683 lbu a3,0(s3) -8000f7a0: 00241713 slli a4,s0,0x2 -8000f7a4: 008708b3 add a7,a4,s0 -8000f7a8: 00189893 slli a7,a7,0x1 -8000f7ac: 00f88433 add s0,a7,a5 -8000f7b0: fd068793 addi a5,a3,-48 -8000f7b4: 00198993 addi s3,s3,1 -8000f7b8: fefcf2e3 bgeu s9,a5,8000f79c <_svfiprintf_r+0x664> -8000f7bc: ab5ff06f j 8000f270 <_svfiprintf_r+0x138> -8000f7c0: 0009c683 lbu a3,0(s3) -8000f7c4: 00496913 ori s2,s2,4 -8000f7c8: aa5ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f7cc: 02b00793 li a5,43 -8000f7d0: 0009c683 lbu a3,0(s3) -8000f7d4: 02f10da3 sb a5,59(sp) -8000f7d8: a95ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f7dc: 00c12703 lw a4,12(sp) -8000f7e0: 0009c683 lbu a3,0(s3) -8000f7e4: 00072783 lw a5,0(a4) -8000f7e8: 00470713 addi a4,a4,4 -8000f7ec: 00e12623 sw a4,12(sp) -8000f7f0: 00f12223 sw a5,4(sp) -8000f7f4: a607dce3 bgez a5,8000f26c <_svfiprintf_r+0x134> -8000f7f8: 40f007b3 neg a5,a5 -8000f7fc: 00f12223 sw a5,4(sp) -8000f800: 00496913 ori s2,s2,4 -8000f804: a69ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f808: 0009c683 lbu a3,0(s3) -8000f80c: 00196913 ori s2,s2,1 -8000f810: a5dff06f j 8000f26c <_svfiprintf_r+0x134> -8000f814: 03b14783 lbu a5,59(sp) -8000f818: 0009c683 lbu a3,0(s3) -8000f81c: a40798e3 bnez a5,8000f26c <_svfiprintf_r+0x134> -8000f820: 02000793 li a5,32 -8000f824: 02f10da3 sb a5,59(sp) -8000f828: a45ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f82c: 0009c683 lbu a3,0(s3) -8000f830: 06800793 li a5,104 -8000f834: 7ef68e63 beq a3,a5,80010030 <_svfiprintf_r+0xef8> -8000f838: 04096913 ori s2,s2,64 -8000f83c: a31ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f840: 00c12703 lw a4,12(sp) -8000f844: 02097793 andi a5,s2,32 -8000f848: 00072683 lw a3,0(a4) -8000f84c: 00470713 addi a4,a4,4 -8000f850: 00e12623 sw a4,12(sp) -8000f854: 5e079c63 bnez a5,8000fe4c <_svfiprintf_r+0xd14> -8000f858: 01097793 andi a5,s2,16 -8000f85c: 7e079e63 bnez a5,80010058 <_svfiprintf_r+0xf20> -8000f860: 04097793 andi a5,s2,64 -8000f864: 100794e3 bnez a5,8001016c <_svfiprintf_r+0x1034> -8000f868: 20097313 andi t1,s2,512 -8000f86c: 7e030663 beqz t1,80010058 <_svfiprintf_r+0xf20> -8000f870: 00812783 lw a5,8(sp) -8000f874: 00f68023 sb a5,0(a3) -8000f878: 965ff06f j 8000f1dc <_svfiprintf_r+0xa4> -8000f87c: 0009c683 lbu a3,0(s3) -8000f880: 06c00793 li a5,108 -8000f884: 7af68e63 beq a3,a5,80010040 <_svfiprintf_r+0xf08> -8000f888: 01096913 ori s2,s2,16 -8000f88c: 9e1ff06f j 8000f26c <_svfiprintf_r+0x134> -8000f890: 00100613 li a2,1 -8000f894: 10c684e3 beq a3,a2,8001019c <_svfiprintf_r+0x1064> -8000f898: 00200613 li a2,2 -8000f89c: 00090d93 mv s11,s2 -8000f8a0: e0c694e3 bne a3,a2,8000f6a8 <_svfiprintf_r+0x570> -8000f8a4: 01412683 lw a3,20(sp) -8000f8a8: 0f010413 addi s0,sp,240 -8000f8ac: 00fcf793 andi a5,s9,15 -8000f8b0: 00f687b3 add a5,a3,a5 -8000f8b4: 0007c703 lbu a4,0(a5) -8000f8b8: 004cdc93 srli s9,s9,0x4 -8000f8bc: 01cc1793 slli a5,s8,0x1c -8000f8c0: 0197ecb3 or s9,a5,s9 -8000f8c4: 004c5c13 srli s8,s8,0x4 -8000f8c8: fee40fa3 sb a4,-1(s0) -8000f8cc: 018ce7b3 or a5,s9,s8 -8000f8d0: fff40413 addi s0,s0,-1 -8000f8d4: fc079ce3 bnez a5,8000f8ac <_svfiprintf_r+0x774> -8000f8d8: 0f010793 addi a5,sp,240 -8000f8dc: 40878cb3 sub s9,a5,s0 -8000f8e0: 000d8913 mv s2,s11 -8000f8e4: cc1ff06f j 8000f5a4 <_svfiprintf_r+0x46c> -8000f8e8: 00412703 lw a4,4(sp) -8000f8ec: 41870db3 sub s11,a4,s8 -8000f8f0: abb052e3 blez s11,8000f394 <_svfiprintf_r+0x25c> -8000f8f4: 01000513 li a0,16 -8000f8f8: 0bb556e3 bge a0,s11,800101a4 <_svfiprintf_r+0x106c> -8000f8fc: 02812223 sw s0,36(sp) -8000f900: 01000693 li a3,16 -8000f904: 000a0413 mv s0,s4 -8000f908: 00700e93 li t4,7 -8000f90c: 000d8a13 mv s4,s11 -8000f910: 00098d93 mv s11,s3 -8000f914: 00088993 mv s3,a7 -8000f918: 00c0006f j 8000f924 <_svfiprintf_r+0x7ec> -8000f91c: ff0a0a13 addi s4,s4,-16 -8000f920: 0546da63 bge a3,s4,8000f974 <_svfiprintf_r+0x83c> -8000f924: 01078793 addi a5,a5,16 -8000f928: 00160613 addi a2,a2,1 -8000f92c: 009d2023 sw s1,0(s10) -8000f930: 00dd2223 sw a3,4(s10) -8000f934: 04f12423 sw a5,72(sp) -8000f938: 04c12223 sw a2,68(sp) -8000f93c: 008d0d13 addi s10,s10,8 -8000f940: fccedee3 bge t4,a2,8000f91c <_svfiprintf_r+0x7e4> -8000f944: 04010613 addi a2,sp,64 -8000f948: 00040593 mv a1,s0 -8000f94c: 000b0513 mv a0,s6 -8000f950: e2cff0ef jal ra,8000ef7c <__ssprint_r> -8000f954: 6e051e63 bnez a0,80010050 <_svfiprintf_r+0xf18> -8000f958: 01000693 li a3,16 -8000f95c: ff0a0a13 addi s4,s4,-16 -8000f960: 04812783 lw a5,72(sp) -8000f964: 04412603 lw a2,68(sp) -8000f968: 000a8d13 mv s10,s5 -8000f96c: 00700e93 li t4,7 -8000f970: fb46cae3 blt a3,s4,8000f924 <_svfiprintf_r+0x7ec> -8000f974: 00098893 mv a7,s3 -8000f978: 000d8993 mv s3,s11 -8000f97c: 000a0d93 mv s11,s4 -8000f980: 00040a13 mv s4,s0 -8000f984: 02412403 lw s0,36(sp) -8000f988: 00160613 addi a2,a2,1 -8000f98c: 008d0513 addi a0,s10,8 -8000f990: 01b787b3 add a5,a5,s11 -8000f994: 009d2023 sw s1,0(s10) -8000f998: 01bd2223 sw s11,4(s10) -8000f99c: 04f12423 sw a5,72(sp) -8000f9a0: 04c12223 sw a2,68(sp) -8000f9a4: 00700713 li a4,7 -8000f9a8: 64c74a63 blt a4,a2,8000fffc <_svfiprintf_r+0xec4> -8000f9ac: 41988db3 sub s11,a7,s9 -8000f9b0: 00160593 addi a1,a2,1 -8000f9b4: 00850693 addi a3,a0,8 -8000f9b8: 00050d13 mv s10,a0 -8000f9bc: 9fb050e3 blez s11,8000f39c <_svfiprintf_r+0x264> -8000f9c0: 01000513 li a0,16 -8000f9c4: 73b55e63 bge a0,s11,80010100 <_svfiprintf_r+0xfc8> -8000f9c8: 01000693 li a3,16 -8000f9cc: 00700893 li a7,7 -8000f9d0: 00c0006f j 8000f9dc <_svfiprintf_r+0x8a4> -8000f9d4: ff0d8d93 addi s11,s11,-16 -8000f9d8: 05b6da63 bge a3,s11,8000fa2c <_svfiprintf_r+0x8f4> -8000f9dc: 01078793 addi a5,a5,16 -8000f9e0: 00160613 addi a2,a2,1 -8000f9e4: 009d2023 sw s1,0(s10) -8000f9e8: 00dd2223 sw a3,4(s10) -8000f9ec: 04f12423 sw a5,72(sp) -8000f9f0: 04c12223 sw a2,68(sp) -8000f9f4: 008d0d13 addi s10,s10,8 -8000f9f8: fcc8dee3 bge a7,a2,8000f9d4 <_svfiprintf_r+0x89c> -8000f9fc: 04010613 addi a2,sp,64 -8000fa00: 000a0593 mv a1,s4 -8000fa04: 000b0513 mv a0,s6 -8000fa08: d74ff0ef jal ra,8000ef7c <__ssprint_r> -8000fa0c: 9e051ae3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000fa10: 01000693 li a3,16 -8000fa14: ff0d8d93 addi s11,s11,-16 -8000fa18: 04812783 lw a5,72(sp) -8000fa1c: 04412603 lw a2,68(sp) -8000fa20: 000a8d13 mv s10,s5 -8000fa24: 00700893 li a7,7 -8000fa28: fbb6cae3 blt a3,s11,8000f9dc <_svfiprintf_r+0x8a4> -8000fa2c: 00160593 addi a1,a2,1 -8000fa30: 008d0613 addi a2,s10,8 -8000fa34: 01b787b3 add a5,a5,s11 -8000fa38: 009d2023 sw s1,0(s10) -8000fa3c: 01bd2223 sw s11,4(s10) -8000fa40: 04f12423 sw a5,72(sp) -8000fa44: 04b12223 sw a1,68(sp) -8000fa48: 00700713 li a4,7 -8000fa4c: 32b74263 blt a4,a1,8000fd70 <_svfiprintf_r+0xc38> -8000fa50: 00060d13 mv s10,a2 -8000fa54: 00158593 addi a1,a1,1 -8000fa58: 00fc87b3 add a5,s9,a5 -8000fa5c: 008d2023 sw s0,0(s10) -8000fa60: 019d2223 sw s9,4(s10) -8000fa64: 04f12423 sw a5,72(sp) -8000fa68: 04b12223 sw a1,68(sp) -8000fa6c: 00700713 li a4,7 -8000fa70: 00860693 addi a3,a2,8 -8000fa74: 94b752e3 bge a4,a1,8000f3b8 <_svfiprintf_r+0x280> -8000fa78: 04010613 addi a2,sp,64 -8000fa7c: 000a0593 mv a1,s4 -8000fa80: 000b0513 mv a0,s6 -8000fa84: cf8ff0ef jal ra,8000ef7c <__ssprint_r> -8000fa88: 96051ce3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000fa8c: 04812783 lw a5,72(sp) -8000fa90: 000a8693 mv a3,s5 -8000fa94: 925ff06f j 8000f3b8 <_svfiprintf_r+0x280> -8000fa98: 04010613 addi a2,sp,64 -8000fa9c: 000a0593 mv a1,s4 -8000faa0: 000b0513 mv a0,s6 -8000faa4: cd8ff0ef jal ra,8000ef7c <__ssprint_r> -8000faa8: 940500e3 beqz a0,8000f3e8 <_svfiprintf_r+0x2b0> -8000faac: 955ff06f j 8000f400 <_svfiprintf_r+0x2c8> -8000fab0: 00090d93 mv s11,s2 -8000fab4: be5ff06f j 8000f698 <_svfiprintf_r+0x560> -8000fab8: 01000693 li a3,16 -8000fabc: 0bb6de63 bge a3,s11,8000fb78 <_svfiprintf_r+0xa40> -8000fac0: 000d0713 mv a4,s10 -8000fac4: 00700f93 li t6,7 -8000fac8: 000c0d13 mv s10,s8 -8000facc: 03e12223 sw t5,36(sp) -8000fad0: 00090c13 mv s8,s2 -8000fad4: 03d12423 sw t4,40(sp) -8000fad8: 000a0913 mv s2,s4 -8000fadc: 00098a13 mv s4,s3 -8000fae0: 00040993 mv s3,s0 -8000fae4: 000d8413 mv s0,s11 -8000fae8: 000c8d93 mv s11,s9 -8000faec: 00088c93 mv s9,a7 -8000faf0: 00c0006f j 8000fafc <_svfiprintf_r+0x9c4> -8000faf4: ff040413 addi s0,s0,-16 -8000faf8: 0486da63 bge a3,s0,8000fb4c <_svfiprintf_r+0xa14> -8000fafc: 01078793 addi a5,a5,16 -8000fb00: 00160613 addi a2,a2,1 -8000fb04: 01772023 sw s7,0(a4) -8000fb08: 00d72223 sw a3,4(a4) -8000fb0c: 04f12423 sw a5,72(sp) -8000fb10: 04c12223 sw a2,68(sp) -8000fb14: 00870713 addi a4,a4,8 -8000fb18: fccfdee3 bge t6,a2,8000faf4 <_svfiprintf_r+0x9bc> -8000fb1c: 04010613 addi a2,sp,64 -8000fb20: 00090593 mv a1,s2 -8000fb24: 000b0513 mv a0,s6 -8000fb28: c54ff0ef jal ra,8000ef7c <__ssprint_r> -8000fb2c: 4a051663 bnez a0,8000ffd8 <_svfiprintf_r+0xea0> -8000fb30: 01000693 li a3,16 -8000fb34: ff040413 addi s0,s0,-16 +8000f300: 41870cb3 sub s9,a4,s8 +8000f304: 099048e3 bgtz s9,8000fb94 <_svfiprintf_r+0xb20> +8000f308: 00412403 lw s0,4(sp) +8000f30c: 01845463 bge s0,s8,8000f314 <_svfiprintf_r+0x2a0> +8000f310: 000c0413 mv s0,s8 +8000f314: 00812703 lw a4,8(sp) +8000f318: 00870733 add a4,a4,s0 +8000f31c: 00e12423 sw a4,8(sp) +8000f320: 6a079a63 bnez a5,8000f9d4 <_svfiprintf_r+0x960> +8000f324: 0009c783 lbu a5,0(s3) +8000f328: 04012223 sw zero,68(sp) +8000f32c: 000a8d13 mv s10,s5 +8000f330: de0798e3 bnez a5,8000f120 <_svfiprintf_r+0xac> +8000f334: 04812783 lw a5,72(sp) +8000f338: 56079ee3 bnez a5,800100b4 <_svfiprintf_r+0x1040> +8000f33c: 00ca5783 lhu a5,12(s4) +8000f340: 0407f793 andi a5,a5,64 +8000f344: 5a0794e3 bnez a5,800100ec <_svfiprintf_r+0x1078> +8000f348: 12c12083 lw ra,300(sp) +8000f34c: 12812403 lw s0,296(sp) +8000f350: 00812503 lw a0,8(sp) +8000f354: 12412483 lw s1,292(sp) +8000f358: 12012903 lw s2,288(sp) +8000f35c: 11c12983 lw s3,284(sp) +8000f360: 11812a03 lw s4,280(sp) +8000f364: 11412a83 lw s5,276(sp) +8000f368: 11012b03 lw s6,272(sp) +8000f36c: 10c12b83 lw s7,268(sp) +8000f370: 10812c03 lw s8,264(sp) +8000f374: 10412c83 lw s9,260(sp) +8000f378: 10012d03 lw s10,256(sp) +8000f37c: 0fc12d83 lw s11,252(sp) +8000f380: 13010113 addi sp,sp,304 +8000f384: 00008067 ret +8000f388: 000b0513 mv a0,s6 +8000f38c: d58f80ef jal ra,800078e4 <_localeconv_r> +8000f390: 00452783 lw a5,4(a0) +8000f394: 00078513 mv a0,a5 +8000f398: 00f12e23 sw a5,28(sp) +8000f39c: d00fa0ef jal ra,8000989c +8000f3a0: 00050793 mv a5,a0 +8000f3a4: 000b0513 mv a0,s6 +8000f3a8: 00078d93 mv s11,a5 +8000f3ac: 02f12023 sw a5,32(sp) +8000f3b0: d34f80ef jal ra,800078e4 <_localeconv_r> +8000f3b4: 00852783 lw a5,8(a0) +8000f3b8: 02a00593 li a1,42 +8000f3bc: 00f12c23 sw a5,24(sp) +8000f3c0: 1e0d98e3 bnez s11,8000fdb0 <_svfiprintf_r+0xd3c> +8000f3c4: 0009c683 lbu a3,0(s3) +8000f3c8: de1ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f3cc: 0009c683 lbu a3,0(s3) +8000f3d0: 02096913 ori s2,s2,32 +8000f3d4: dd5ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f3d8: 41340c33 sub s8,s0,s3 +8000f3dc: d73412e3 bne s0,s3,8000f140 <_svfiprintf_r+0xcc> +8000f3e0: 00044783 lbu a5,0(s0) +8000f3e4: d99ff06f j 8000f17c <_svfiprintf_r+0x108> +8000f3e8: 04010613 addi a2,sp,64 +8000f3ec: 000a0593 mv a1,s4 +8000f3f0: 000b0513 mv a0,s6 +8000f3f4: ac5ff0ef jal ra,8000eeb8 <__ssprint_r> +8000f3f8: f40512e3 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000f3fc: 000a8d13 mv s10,s5 +8000f400: d6dff06f j 8000f16c <_svfiprintf_r+0xf8> +8000f404: 00c12783 lw a5,12(sp) +8000f408: 00040893 mv a7,s0 +8000f40c: 02010da3 sb zero,59(sp) +8000f410: 0007a403 lw s0,0(a5) +8000f414: 00478d93 addi s11,a5,4 +8000f418: 380404e3 beqz s0,8000ffa0 <_svfiprintf_r+0xf2c> +8000f41c: fff00793 li a5,-1 +8000f420: 26f88ee3 beq a7,a5,8000fe9c <_svfiprintf_r+0xe28> +8000f424: 00088613 mv a2,a7 +8000f428: 00000593 li a1,0 +8000f42c: 00040513 mv a0,s0 +8000f430: 01112623 sw a7,12(sp) +8000f434: e49f80ef jal ra,8000827c +8000f438: 00c12883 lw a7,12(sp) +8000f43c: 480506e3 beqz a0,800100c8 <_svfiprintf_r+0x1054> +8000f440: 40850cb3 sub s9,a0,s0 +8000f444: 01b12623 sw s11,12(sp) +8000f448: 00000893 li a7,0 +8000f44c: 0940006f j 8000f4e0 <_svfiprintf_r+0x46c> +8000f450: 00c12703 lw a4,12(sp) +8000f454: 02010da3 sb zero,59(sp) +8000f458: 00100c13 li s8,1 +8000f45c: 00072783 lw a5,0(a4) +8000f460: 00470713 addi a4,a4,4 +8000f464: 00e12623 sw a4,12(sp) +8000f468: 08f10623 sb a5,140(sp) +8000f46c: 00100c93 li s9,1 +8000f470: 08c10413 addi s0,sp,140 +8000f474: da5ff06f j 8000f218 <_svfiprintf_r+0x1a4> +8000f478: 02097793 andi a5,s2,32 +8000f47c: 00040893 mv a7,s0 +8000f480: 0e078e63 beqz a5,8000f57c <_svfiprintf_r+0x508> +8000f484: 00c12783 lw a5,12(sp) +8000f488: 00778793 addi a5,a5,7 +8000f48c: ff87f793 andi a5,a5,-8 +8000f490: 0047a683 lw a3,4(a5) +8000f494: 0007ac83 lw s9,0(a5) +8000f498: 00878793 addi a5,a5,8 +8000f49c: 00f12623 sw a5,12(sp) +8000f4a0: 00068c13 mv s8,a3 +8000f4a4: 1006c463 bltz a3,8000f5ac <_svfiprintf_r+0x538> +8000f4a8: fff00693 li a3,-1 +8000f4ac: 00090d93 mv s11,s2 +8000f4b0: 00d88863 beq a7,a3,8000f4c0 <_svfiprintf_r+0x44c> +8000f4b4: 018ce6b3 or a3,s9,s8 +8000f4b8: f7f97d93 andi s11,s2,-129 +8000f4bc: 76068e63 beqz a3,8000fc38 <_svfiprintf_r+0xbc4> +8000f4c0: 000c1ce3 bnez s8,8000fcd8 <_svfiprintf_r+0xc64> +8000f4c4: 00900693 li a3,9 +8000f4c8: 0196e8e3 bltu a3,s9,8000fcd8 <_svfiprintf_r+0xc64> +8000f4cc: 030c8793 addi a5,s9,48 +8000f4d0: 0ef107a3 sb a5,239(sp) +8000f4d4: 000d8913 mv s2,s11 +8000f4d8: 00100c93 li s9,1 +8000f4dc: 0ef10413 addi s0,sp,239 +8000f4e0: 00088c13 mv s8,a7 +8000f4e4: 0198d463 bge a7,s9,8000f4ec <_svfiprintf_r+0x478> +8000f4e8: 000c8c13 mv s8,s9 +8000f4ec: 03b14783 lbu a5,59(sp) +8000f4f0: 00f037b3 snez a5,a5 +8000f4f4: 00fc0c33 add s8,s8,a5 +8000f4f8: d25ff06f j 8000f21c <_svfiprintf_r+0x1a8> +8000f4fc: 00040893 mv a7,s0 +8000f500: 01096913 ori s2,s2,16 +8000f504: 02097793 andi a5,s2,32 +8000f508: 74078463 beqz a5,8000fc50 <_svfiprintf_r+0xbdc> +8000f50c: 00c12783 lw a5,12(sp) +8000f510: 00778793 addi a5,a5,7 +8000f514: ff87f793 andi a5,a5,-8 +8000f518: 0007ac83 lw s9,0(a5) +8000f51c: 0047ac03 lw s8,4(a5) +8000f520: 00878793 addi a5,a5,8 +8000f524: 00f12623 sw a5,12(sp) +8000f528: bff97d93 andi s11,s2,-1025 +8000f52c: 00000693 li a3,0 +8000f530: 02010da3 sb zero,59(sp) +8000f534: fff00613 li a2,-1 +8000f538: 08c88e63 beq a7,a2,8000f5d4 <_svfiprintf_r+0x560> +8000f53c: 018ce633 or a2,s9,s8 +8000f540: f7fdf913 andi s2,s11,-129 +8000f544: 4a061463 bnez a2,8000f9ec <_svfiprintf_r+0x978> +8000f548: 28089263 bnez a7,8000f7cc <_svfiprintf_r+0x758> +8000f54c: 6e069a63 bnez a3,8000fc40 <_svfiprintf_r+0xbcc> +8000f550: 001dfc93 andi s9,s11,1 +8000f554: 0f010413 addi s0,sp,240 +8000f558: f80c84e3 beqz s9,8000f4e0 <_svfiprintf_r+0x46c> +8000f55c: 03000793 li a5,48 +8000f560: 0ef107a3 sb a5,239(sp) +8000f564: 0ef10413 addi s0,sp,239 +8000f568: f79ff06f j 8000f4e0 <_svfiprintf_r+0x46c> +8000f56c: 01096913 ori s2,s2,16 +8000f570: 02097793 andi a5,s2,32 +8000f574: 00040893 mv a7,s0 +8000f578: f00796e3 bnez a5,8000f484 <_svfiprintf_r+0x410> +8000f57c: 00c12703 lw a4,12(sp) +8000f580: 01097793 andi a5,s2,16 +8000f584: 00470693 addi a3,a4,4 +8000f588: 040792e3 bnez a5,8000fdcc <_svfiprintf_r+0xd58> +8000f58c: 04097793 andi a5,s2,64 +8000f590: 260786e3 beqz a5,8000fffc <_svfiprintf_r+0xf88> +8000f594: 00c12783 lw a5,12(sp) +8000f598: 00d12623 sw a3,12(sp) +8000f59c: 00079c83 lh s9,0(a5) +8000f5a0: 41fcdc13 srai s8,s9,0x1f +8000f5a4: 000c0693 mv a3,s8 +8000f5a8: f006d0e3 bgez a3,8000f4a8 <_svfiprintf_r+0x434> +8000f5ac: 019036b3 snez a3,s9 +8000f5b0: 41800eb3 neg t4,s8 +8000f5b4: 40de8c33 sub s8,t4,a3 +8000f5b8: 02d00693 li a3,45 +8000f5bc: 02d10da3 sb a3,59(sp) +8000f5c0: fff00613 li a2,-1 +8000f5c4: 41900cb3 neg s9,s9 +8000f5c8: 00090d93 mv s11,s2 +8000f5cc: 00100693 li a3,1 +8000f5d0: f6c896e3 bne a7,a2,8000f53c <_svfiprintf_r+0x4c8> +8000f5d4: 00100613 li a2,1 +8000f5d8: eec684e3 beq a3,a2,8000f4c0 <_svfiprintf_r+0x44c> +8000f5dc: 00200613 li a2,2 +8000f5e0: 20c68063 beq a3,a2,8000f7e0 <_svfiprintf_r+0x76c> +8000f5e4: 0f010413 addi s0,sp,240 +8000f5e8: 01dc1793 slli a5,s8,0x1d +8000f5ec: 007cf693 andi a3,s9,7 +8000f5f0: 003cdc93 srli s9,s9,0x3 +8000f5f4: 03068693 addi a3,a3,48 +8000f5f8: 0197ecb3 or s9,a5,s9 +8000f5fc: 003c5c13 srli s8,s8,0x3 +8000f600: fed40fa3 sb a3,-1(s0) +8000f604: 018ce7b3 or a5,s9,s8 +8000f608: 00040593 mv a1,s0 +8000f60c: fff40413 addi s0,s0,-1 +8000f610: fc079ce3 bnez a5,8000f5e8 <_svfiprintf_r+0x574> +8000f614: 001df793 andi a5,s11,1 +8000f618: 1e078e63 beqz a5,8000f814 <_svfiprintf_r+0x7a0> +8000f61c: 03000793 li a5,48 +8000f620: 1ef68a63 beq a3,a5,8000f814 <_svfiprintf_r+0x7a0> +8000f624: ffe58593 addi a1,a1,-2 +8000f628: fef40fa3 sb a5,-1(s0) +8000f62c: 0f010793 addi a5,sp,240 +8000f630: 40b78cb3 sub s9,a5,a1 +8000f634: 000d8913 mv s2,s11 +8000f638: 00058413 mv s0,a1 +8000f63c: ea5ff06f j 8000f4e0 <_svfiprintf_r+0x46c> +8000f640: 00040893 mv a7,s0 +8000f644: 01096d93 ori s11,s2,16 +8000f648: 020df793 andi a5,s11,32 +8000f64c: 62078863 beqz a5,8000fc7c <_svfiprintf_r+0xc08> +8000f650: 00c12783 lw a5,12(sp) +8000f654: 00100693 li a3,1 +8000f658: 00778913 addi s2,a5,7 +8000f65c: ff897913 andi s2,s2,-8 +8000f660: 00890793 addi a5,s2,8 +8000f664: 00092c83 lw s9,0(s2) +8000f668: 00492c03 lw s8,4(s2) +8000f66c: 00f12623 sw a5,12(sp) +8000f670: ec1ff06f j 8000f530 <_svfiprintf_r+0x4bc> +8000f674: 00c12783 lw a5,12(sp) +8000f678: ffff86b7 lui a3,0xffff8 +8000f67c: 8306c693 xori a3,a3,-2000 +8000f680: 0007ac83 lw s9,0(a5) +8000f684: 00478793 addi a5,a5,4 +8000f688: 00f12623 sw a5,12(sp) +8000f68c: 800157b7 lui a5,0x80015 +8000f690: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +8000f694: 02d11e23 sh a3,60(sp) +8000f698: 00040893 mv a7,s0 +8000f69c: 00000c13 li s8,0 +8000f6a0: 00296d93 ori s11,s2,2 +8000f6a4: 00f12a23 sw a5,20(sp) +8000f6a8: 00200693 li a3,2 +8000f6ac: e85ff06f j 8000f530 <_svfiprintf_r+0x4bc> +8000f6b0: 0009c683 lbu a3,0(s3) +8000f6b4: 08096913 ori s2,s2,128 +8000f6b8: af1ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f6bc: 0009c683 lbu a3,0(s3) +8000f6c0: 00198713 addi a4,s3,1 +8000f6c4: 22b68ae3 beq a3,a1,800100f8 <_svfiprintf_r+0x1084> +8000f6c8: fd068793 addi a5,a3,-48 # ffff7fd0 <__BSS_END__+0x7ffe1394> +8000f6cc: 00070993 mv s3,a4 +8000f6d0: 00000413 li s0,0 +8000f6d4: acfcece3 bltu s9,a5,8000f1ac <_svfiprintf_r+0x138> +8000f6d8: 0009c683 lbu a3,0(s3) +8000f6dc: 00241713 slli a4,s0,0x2 +8000f6e0: 008708b3 add a7,a4,s0 +8000f6e4: 00189893 slli a7,a7,0x1 +8000f6e8: 00f88433 add s0,a7,a5 +8000f6ec: fd068793 addi a5,a3,-48 +8000f6f0: 00198993 addi s3,s3,1 +8000f6f4: fefcf2e3 bgeu s9,a5,8000f6d8 <_svfiprintf_r+0x664> +8000f6f8: ab5ff06f j 8000f1ac <_svfiprintf_r+0x138> +8000f6fc: 0009c683 lbu a3,0(s3) +8000f700: 00496913 ori s2,s2,4 +8000f704: aa5ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f708: 02b00793 li a5,43 +8000f70c: 0009c683 lbu a3,0(s3) +8000f710: 02f10da3 sb a5,59(sp) +8000f714: a95ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f718: 00c12703 lw a4,12(sp) +8000f71c: 0009c683 lbu a3,0(s3) +8000f720: 00072783 lw a5,0(a4) +8000f724: 00470713 addi a4,a4,4 +8000f728: 00e12623 sw a4,12(sp) +8000f72c: 00f12223 sw a5,4(sp) +8000f730: a607dce3 bgez a5,8000f1a8 <_svfiprintf_r+0x134> +8000f734: 40f007b3 neg a5,a5 +8000f738: 00f12223 sw a5,4(sp) +8000f73c: 00496913 ori s2,s2,4 +8000f740: a69ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f744: 0009c683 lbu a3,0(s3) +8000f748: 00196913 ori s2,s2,1 +8000f74c: a5dff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f750: 03b14783 lbu a5,59(sp) +8000f754: 0009c683 lbu a3,0(s3) +8000f758: a40798e3 bnez a5,8000f1a8 <_svfiprintf_r+0x134> +8000f75c: 02000793 li a5,32 +8000f760: 02f10da3 sb a5,59(sp) +8000f764: a45ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f768: 0009c683 lbu a3,0(s3) +8000f76c: 06800793 li a5,104 +8000f770: 7ef68e63 beq a3,a5,8000ff6c <_svfiprintf_r+0xef8> +8000f774: 04096913 ori s2,s2,64 +8000f778: a31ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f77c: 00c12703 lw a4,12(sp) +8000f780: 02097793 andi a5,s2,32 +8000f784: 00072683 lw a3,0(a4) +8000f788: 00470713 addi a4,a4,4 +8000f78c: 00e12623 sw a4,12(sp) +8000f790: 5e079c63 bnez a5,8000fd88 <_svfiprintf_r+0xd14> +8000f794: 01097793 andi a5,s2,16 +8000f798: 7e079e63 bnez a5,8000ff94 <_svfiprintf_r+0xf20> +8000f79c: 04097793 andi a5,s2,64 +8000f7a0: 100794e3 bnez a5,800100a8 <_svfiprintf_r+0x1034> +8000f7a4: 20097313 andi t1,s2,512 +8000f7a8: 7e030663 beqz t1,8000ff94 <_svfiprintf_r+0xf20> +8000f7ac: 00812783 lw a5,8(sp) +8000f7b0: 00f68023 sb a5,0(a3) +8000f7b4: 965ff06f j 8000f118 <_svfiprintf_r+0xa4> +8000f7b8: 0009c683 lbu a3,0(s3) +8000f7bc: 06c00793 li a5,108 +8000f7c0: 7af68e63 beq a3,a5,8000ff7c <_svfiprintf_r+0xf08> +8000f7c4: 01096913 ori s2,s2,16 +8000f7c8: 9e1ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000f7cc: 00100613 li a2,1 +8000f7d0: 10c684e3 beq a3,a2,800100d8 <_svfiprintf_r+0x1064> +8000f7d4: 00200613 li a2,2 +8000f7d8: 00090d93 mv s11,s2 +8000f7dc: e0c694e3 bne a3,a2,8000f5e4 <_svfiprintf_r+0x570> +8000f7e0: 01412683 lw a3,20(sp) +8000f7e4: 0f010413 addi s0,sp,240 +8000f7e8: 00fcf793 andi a5,s9,15 +8000f7ec: 00f687b3 add a5,a3,a5 +8000f7f0: 0007c703 lbu a4,0(a5) +8000f7f4: 004cdc93 srli s9,s9,0x4 +8000f7f8: 01cc1793 slli a5,s8,0x1c +8000f7fc: 0197ecb3 or s9,a5,s9 +8000f800: 004c5c13 srli s8,s8,0x4 +8000f804: fee40fa3 sb a4,-1(s0) +8000f808: 018ce7b3 or a5,s9,s8 +8000f80c: fff40413 addi s0,s0,-1 +8000f810: fc079ce3 bnez a5,8000f7e8 <_svfiprintf_r+0x774> +8000f814: 0f010793 addi a5,sp,240 +8000f818: 40878cb3 sub s9,a5,s0 +8000f81c: 000d8913 mv s2,s11 +8000f820: cc1ff06f j 8000f4e0 <_svfiprintf_r+0x46c> +8000f824: 00412703 lw a4,4(sp) +8000f828: 41870db3 sub s11,a4,s8 +8000f82c: abb052e3 blez s11,8000f2d0 <_svfiprintf_r+0x25c> +8000f830: 01000513 li a0,16 +8000f834: 0bb556e3 bge a0,s11,800100e0 <_svfiprintf_r+0x106c> +8000f838: 02812223 sw s0,36(sp) +8000f83c: 01000693 li a3,16 +8000f840: 000a0413 mv s0,s4 +8000f844: 00700e93 li t4,7 +8000f848: 000d8a13 mv s4,s11 +8000f84c: 00098d93 mv s11,s3 +8000f850: 00088993 mv s3,a7 +8000f854: 00c0006f j 8000f860 <_svfiprintf_r+0x7ec> +8000f858: ff0a0a13 addi s4,s4,-16 +8000f85c: 0546da63 bge a3,s4,8000f8b0 <_svfiprintf_r+0x83c> +8000f860: 01078793 addi a5,a5,16 +8000f864: 00160613 addi a2,a2,1 +8000f868: 009d2023 sw s1,0(s10) +8000f86c: 00dd2223 sw a3,4(s10) +8000f870: 04f12423 sw a5,72(sp) +8000f874: 04c12223 sw a2,68(sp) +8000f878: 008d0d13 addi s10,s10,8 +8000f87c: fccedee3 bge t4,a2,8000f858 <_svfiprintf_r+0x7e4> +8000f880: 04010613 addi a2,sp,64 +8000f884: 00040593 mv a1,s0 +8000f888: 000b0513 mv a0,s6 +8000f88c: e2cff0ef jal ra,8000eeb8 <__ssprint_r> +8000f890: 6e051e63 bnez a0,8000ff8c <_svfiprintf_r+0xf18> +8000f894: 01000693 li a3,16 +8000f898: ff0a0a13 addi s4,s4,-16 +8000f89c: 04812783 lw a5,72(sp) +8000f8a0: 04412603 lw a2,68(sp) +8000f8a4: 000a8d13 mv s10,s5 +8000f8a8: 00700e93 li t4,7 +8000f8ac: fb46cae3 blt a3,s4,8000f860 <_svfiprintf_r+0x7ec> +8000f8b0: 00098893 mv a7,s3 +8000f8b4: 000d8993 mv s3,s11 +8000f8b8: 000a0d93 mv s11,s4 +8000f8bc: 00040a13 mv s4,s0 +8000f8c0: 02412403 lw s0,36(sp) +8000f8c4: 00160613 addi a2,a2,1 +8000f8c8: 008d0513 addi a0,s10,8 +8000f8cc: 01b787b3 add a5,a5,s11 +8000f8d0: 009d2023 sw s1,0(s10) +8000f8d4: 01bd2223 sw s11,4(s10) +8000f8d8: 04f12423 sw a5,72(sp) +8000f8dc: 04c12223 sw a2,68(sp) +8000f8e0: 00700713 li a4,7 +8000f8e4: 64c74a63 blt a4,a2,8000ff38 <_svfiprintf_r+0xec4> +8000f8e8: 41988db3 sub s11,a7,s9 +8000f8ec: 00160593 addi a1,a2,1 +8000f8f0: 00850693 addi a3,a0,8 +8000f8f4: 00050d13 mv s10,a0 +8000f8f8: 9fb050e3 blez s11,8000f2d8 <_svfiprintf_r+0x264> +8000f8fc: 01000513 li a0,16 +8000f900: 73b55e63 bge a0,s11,8001003c <_svfiprintf_r+0xfc8> +8000f904: 01000693 li a3,16 +8000f908: 00700893 li a7,7 +8000f90c: 00c0006f j 8000f918 <_svfiprintf_r+0x8a4> +8000f910: ff0d8d93 addi s11,s11,-16 +8000f914: 05b6da63 bge a3,s11,8000f968 <_svfiprintf_r+0x8f4> +8000f918: 01078793 addi a5,a5,16 +8000f91c: 00160613 addi a2,a2,1 +8000f920: 009d2023 sw s1,0(s10) +8000f924: 00dd2223 sw a3,4(s10) +8000f928: 04f12423 sw a5,72(sp) +8000f92c: 04c12223 sw a2,68(sp) +8000f930: 008d0d13 addi s10,s10,8 +8000f934: fcc8dee3 bge a7,a2,8000f910 <_svfiprintf_r+0x89c> +8000f938: 04010613 addi a2,sp,64 +8000f93c: 000a0593 mv a1,s4 +8000f940: 000b0513 mv a0,s6 +8000f944: d74ff0ef jal ra,8000eeb8 <__ssprint_r> +8000f948: 9e051ae3 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000f94c: 01000693 li a3,16 +8000f950: ff0d8d93 addi s11,s11,-16 +8000f954: 04812783 lw a5,72(sp) +8000f958: 04412603 lw a2,68(sp) +8000f95c: 000a8d13 mv s10,s5 +8000f960: 00700893 li a7,7 +8000f964: fbb6cae3 blt a3,s11,8000f918 <_svfiprintf_r+0x8a4> +8000f968: 00160593 addi a1,a2,1 +8000f96c: 008d0613 addi a2,s10,8 +8000f970: 01b787b3 add a5,a5,s11 +8000f974: 009d2023 sw s1,0(s10) +8000f978: 01bd2223 sw s11,4(s10) +8000f97c: 04f12423 sw a5,72(sp) +8000f980: 04b12223 sw a1,68(sp) +8000f984: 00700713 li a4,7 +8000f988: 32b74263 blt a4,a1,8000fcac <_svfiprintf_r+0xc38> +8000f98c: 00060d13 mv s10,a2 +8000f990: 00158593 addi a1,a1,1 +8000f994: 00fc87b3 add a5,s9,a5 +8000f998: 008d2023 sw s0,0(s10) +8000f99c: 019d2223 sw s9,4(s10) +8000f9a0: 04f12423 sw a5,72(sp) +8000f9a4: 04b12223 sw a1,68(sp) +8000f9a8: 00700713 li a4,7 +8000f9ac: 00860693 addi a3,a2,8 +8000f9b0: 94b752e3 bge a4,a1,8000f2f4 <_svfiprintf_r+0x280> +8000f9b4: 04010613 addi a2,sp,64 +8000f9b8: 000a0593 mv a1,s4 +8000f9bc: 000b0513 mv a0,s6 +8000f9c0: cf8ff0ef jal ra,8000eeb8 <__ssprint_r> +8000f9c4: 96051ce3 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000f9c8: 04812783 lw a5,72(sp) +8000f9cc: 000a8693 mv a3,s5 +8000f9d0: 925ff06f j 8000f2f4 <_svfiprintf_r+0x280> +8000f9d4: 04010613 addi a2,sp,64 +8000f9d8: 000a0593 mv a1,s4 +8000f9dc: 000b0513 mv a0,s6 +8000f9e0: cd8ff0ef jal ra,8000eeb8 <__ssprint_r> +8000f9e4: 940500e3 beqz a0,8000f324 <_svfiprintf_r+0x2b0> +8000f9e8: 955ff06f j 8000f33c <_svfiprintf_r+0x2c8> +8000f9ec: 00090d93 mv s11,s2 +8000f9f0: be5ff06f j 8000f5d4 <_svfiprintf_r+0x560> +8000f9f4: 01000693 li a3,16 +8000f9f8: 0bb6de63 bge a3,s11,8000fab4 <_svfiprintf_r+0xa40> +8000f9fc: 000d0713 mv a4,s10 +8000fa00: 00700f93 li t6,7 +8000fa04: 000c0d13 mv s10,s8 +8000fa08: 03e12223 sw t5,36(sp) +8000fa0c: 00090c13 mv s8,s2 +8000fa10: 03d12423 sw t4,40(sp) +8000fa14: 000a0913 mv s2,s4 +8000fa18: 00098a13 mv s4,s3 +8000fa1c: 00040993 mv s3,s0 +8000fa20: 000d8413 mv s0,s11 +8000fa24: 000c8d93 mv s11,s9 +8000fa28: 00088c93 mv s9,a7 +8000fa2c: 00c0006f j 8000fa38 <_svfiprintf_r+0x9c4> +8000fa30: ff040413 addi s0,s0,-16 +8000fa34: 0486da63 bge a3,s0,8000fa88 <_svfiprintf_r+0xa14> +8000fa38: 01078793 addi a5,a5,16 +8000fa3c: 00160613 addi a2,a2,1 +8000fa40: 01772023 sw s7,0(a4) +8000fa44: 00d72223 sw a3,4(a4) +8000fa48: 04f12423 sw a5,72(sp) +8000fa4c: 04c12223 sw a2,68(sp) +8000fa50: 00870713 addi a4,a4,8 +8000fa54: fccfdee3 bge t6,a2,8000fa30 <_svfiprintf_r+0x9bc> +8000fa58: 04010613 addi a2,sp,64 +8000fa5c: 00090593 mv a1,s2 +8000fa60: 000b0513 mv a0,s6 +8000fa64: c54ff0ef jal ra,8000eeb8 <__ssprint_r> +8000fa68: 4a051663 bnez a0,8000ff14 <_svfiprintf_r+0xea0> +8000fa6c: 01000693 li a3,16 +8000fa70: ff040413 addi s0,s0,-16 +8000fa74: 04812783 lw a5,72(sp) +8000fa78: 04412603 lw a2,68(sp) +8000fa7c: 000a8713 mv a4,s5 +8000fa80: 00700f93 li t6,7 +8000fa84: fa86cae3 blt a3,s0,8000fa38 <_svfiprintf_r+0x9c4> +8000fa88: 02412f03 lw t5,36(sp) +8000fa8c: 02812e83 lw t4,40(sp) +8000fa90: 000c8893 mv a7,s9 +8000fa94: 000d8c93 mv s9,s11 +8000fa98: 00040d93 mv s11,s0 +8000fa9c: 00098413 mv s0,s3 +8000faa0: 000a0993 mv s3,s4 +8000faa4: 00090a13 mv s4,s2 +8000faa8: 000c0913 mv s2,s8 +8000faac: 000d0c13 mv s8,s10 +8000fab0: 00070d13 mv s10,a4 +8000fab4: 01b787b3 add a5,a5,s11 +8000fab8: 00160613 addi a2,a2,1 +8000fabc: 017d2023 sw s7,0(s10) +8000fac0: 01bd2223 sw s11,4(s10) +8000fac4: 04f12423 sw a5,72(sp) +8000fac8: 04c12223 sw a2,68(sp) +8000facc: 00700693 li a3,7 +8000fad0: 008d0d13 addi s10,s10,8 +8000fad4: f6c6d863 bge a3,a2,8000f244 <_svfiprintf_r+0x1d0> +8000fad8: 04010613 addi a2,sp,64 +8000fadc: 000a0593 mv a1,s4 +8000fae0: 000b0513 mv a0,s6 +8000fae4: 03112623 sw a7,44(sp) +8000fae8: 03d12423 sw t4,40(sp) +8000faec: 03e12223 sw t5,36(sp) +8000faf0: bc8ff0ef jal ra,8000eeb8 <__ssprint_r> +8000faf4: 840514e3 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000faf8: 04812783 lw a5,72(sp) +8000fafc: 04412603 lw a2,68(sp) +8000fb00: 02c12883 lw a7,44(sp) +8000fb04: 02812e83 lw t4,40(sp) +8000fb08: 02412f03 lw t5,36(sp) +8000fb0c: 000a8d13 mv s10,s5 +8000fb10: f34ff06f j 8000f244 <_svfiprintf_r+0x1d0> +8000fb14: 04010613 addi a2,sp,64 +8000fb18: 000a0593 mv a1,s4 +8000fb1c: 000b0513 mv a0,s6 +8000fb20: 03112623 sw a7,44(sp) +8000fb24: 03d12423 sw t4,40(sp) +8000fb28: 03e12223 sw t5,36(sp) +8000fb2c: b8cff0ef jal ra,8000eeb8 <__ssprint_r> +8000fb30: 800516e3 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000fb34: 04412603 lw a2,68(sp) 8000fb38: 04812783 lw a5,72(sp) -8000fb3c: 04412603 lw a2,68(sp) -8000fb40: 000a8713 mv a4,s5 -8000fb44: 00700f93 li t6,7 -8000fb48: fa86cae3 blt a3,s0,8000fafc <_svfiprintf_r+0x9c4> -8000fb4c: 02412f03 lw t5,36(sp) -8000fb50: 02812e83 lw t4,40(sp) -8000fb54: 000c8893 mv a7,s9 -8000fb58: 000d8c93 mv s9,s11 -8000fb5c: 00040d93 mv s11,s0 -8000fb60: 00098413 mv s0,s3 -8000fb64: 000a0993 mv s3,s4 -8000fb68: 00090a13 mv s4,s2 -8000fb6c: 000c0913 mv s2,s8 -8000fb70: 000d0c13 mv s8,s10 -8000fb74: 00070d13 mv s10,a4 -8000fb78: 01b787b3 add a5,a5,s11 -8000fb7c: 00160613 addi a2,a2,1 -8000fb80: 017d2023 sw s7,0(s10) -8000fb84: 01bd2223 sw s11,4(s10) -8000fb88: 04f12423 sw a5,72(sp) -8000fb8c: 04c12223 sw a2,68(sp) -8000fb90: 00700693 li a3,7 -8000fb94: 008d0d13 addi s10,s10,8 -8000fb98: f6c6d863 bge a3,a2,8000f308 <_svfiprintf_r+0x1d0> -8000fb9c: 04010613 addi a2,sp,64 -8000fba0: 000a0593 mv a1,s4 -8000fba4: 000b0513 mv a0,s6 -8000fba8: 03112623 sw a7,44(sp) -8000fbac: 03d12423 sw t4,40(sp) -8000fbb0: 03e12223 sw t5,36(sp) -8000fbb4: bc8ff0ef jal ra,8000ef7c <__ssprint_r> -8000fbb8: 840514e3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000fbbc: 04812783 lw a5,72(sp) -8000fbc0: 04412603 lw a2,68(sp) -8000fbc4: 02c12883 lw a7,44(sp) -8000fbc8: 02812e83 lw t4,40(sp) -8000fbcc: 02412f03 lw t5,36(sp) -8000fbd0: 000a8d13 mv s10,s5 -8000fbd4: f34ff06f j 8000f308 <_svfiprintf_r+0x1d0> -8000fbd8: 04010613 addi a2,sp,64 -8000fbdc: 000a0593 mv a1,s4 -8000fbe0: 000b0513 mv a0,s6 -8000fbe4: 03112623 sw a7,44(sp) -8000fbe8: 03d12423 sw t4,40(sp) -8000fbec: 03e12223 sw t5,36(sp) -8000fbf0: b8cff0ef jal ra,8000ef7c <__ssprint_r> -8000fbf4: 800516e3 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000fbf8: 04412603 lw a2,68(sp) -8000fbfc: 04812783 lw a5,72(sp) -8000fc00: 02c12883 lw a7,44(sp) -8000fc04: 02812e83 lw t4,40(sp) -8000fc08: 02412f03 lw t5,36(sp) -8000fc0c: 05410693 addi a3,sp,84 -8000fc10: 00160593 addi a1,a2,1 -8000fc14: 000a8d13 mv s10,s5 -8000fc18: f3cff06f j 8000f354 <_svfiprintf_r+0x21c> +8000fb3c: 02c12883 lw a7,44(sp) +8000fb40: 02812e83 lw t4,40(sp) +8000fb44: 02412f03 lw t5,36(sp) +8000fb48: 05410693 addi a3,sp,84 +8000fb4c: 00160593 addi a1,a2,1 +8000fb50: 000a8d13 mv s10,s5 +8000fb54: f3cff06f j 8000f290 <_svfiprintf_r+0x21c> +8000fb58: 04010613 addi a2,sp,64 +8000fb5c: 000a0593 mv a1,s4 +8000fb60: 000b0513 mv a0,s6 +8000fb64: 03112423 sw a7,40(sp) +8000fb68: 03d12223 sw t4,36(sp) +8000fb6c: b4cff0ef jal ra,8000eeb8 <__ssprint_r> +8000fb70: fc051663 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000fb74: 04412603 lw a2,68(sp) +8000fb78: 04812783 lw a5,72(sp) +8000fb7c: 02812883 lw a7,40(sp) +8000fb80: 02412e83 lw t4,36(sp) +8000fb84: 05410693 addi a3,sp,84 +8000fb88: 00160593 addi a1,a2,1 +8000fb8c: 000a8d13 mv s10,s5 +8000fb90: f38ff06f j 8000f2c8 <_svfiprintf_r+0x254> +8000fb94: 01000613 li a2,16 +8000fb98: 04412703 lw a4,68(sp) +8000fb9c: 07965063 bge a2,s9,8000fbfc <_svfiprintf_r+0xb88> +8000fba0: 01000d93 li s11,16 +8000fba4: 00700413 li s0,7 +8000fba8: 00c0006f j 8000fbb4 <_svfiprintf_r+0xb40> +8000fbac: ff0c8c93 addi s9,s9,-16 +8000fbb0: 059dd663 bge s11,s9,8000fbfc <_svfiprintf_r+0xb88> +8000fbb4: 01078793 addi a5,a5,16 +8000fbb8: 00170713 addi a4,a4,1 +8000fbbc: 0176a023 sw s7,0(a3) +8000fbc0: 01b6a223 sw s11,4(a3) +8000fbc4: 04f12423 sw a5,72(sp) +8000fbc8: 04e12223 sw a4,68(sp) +8000fbcc: 00868693 addi a3,a3,8 +8000fbd0: fce45ee3 bge s0,a4,8000fbac <_svfiprintf_r+0xb38> +8000fbd4: 04010613 addi a2,sp,64 +8000fbd8: 000a0593 mv a1,s4 +8000fbdc: 000b0513 mv a0,s6 +8000fbe0: ad8ff0ef jal ra,8000eeb8 <__ssprint_r> +8000fbe4: f4051c63 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000fbe8: ff0c8c93 addi s9,s9,-16 +8000fbec: 04812783 lw a5,72(sp) +8000fbf0: 04412703 lw a4,68(sp) +8000fbf4: 000a8693 mv a3,s5 +8000fbf8: fb9dcee3 blt s11,s9,8000fbb4 <_svfiprintf_r+0xb40> +8000fbfc: 019787b3 add a5,a5,s9 +8000fc00: 00170713 addi a4,a4,1 +8000fc04: 0176a023 sw s7,0(a3) +8000fc08: 0196a223 sw s9,4(a3) +8000fc0c: 04f12423 sw a5,72(sp) +8000fc10: 04e12223 sw a4,68(sp) +8000fc14: 00700693 li a3,7 +8000fc18: eee6d863 bge a3,a4,8000f308 <_svfiprintf_r+0x294> 8000fc1c: 04010613 addi a2,sp,64 8000fc20: 000a0593 mv a1,s4 8000fc24: 000b0513 mv a0,s6 -8000fc28: 03112423 sw a7,40(sp) -8000fc2c: 03d12223 sw t4,36(sp) -8000fc30: b4cff0ef jal ra,8000ef7c <__ssprint_r> -8000fc34: fc051663 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000fc38: 04412603 lw a2,68(sp) -8000fc3c: 04812783 lw a5,72(sp) -8000fc40: 02812883 lw a7,40(sp) -8000fc44: 02412e83 lw t4,36(sp) -8000fc48: 05410693 addi a3,sp,84 -8000fc4c: 00160593 addi a1,a2,1 -8000fc50: 000a8d13 mv s10,s5 -8000fc54: f38ff06f j 8000f38c <_svfiprintf_r+0x254> -8000fc58: 01000613 li a2,16 -8000fc5c: 04412703 lw a4,68(sp) -8000fc60: 07965063 bge a2,s9,8000fcc0 <_svfiprintf_r+0xb88> -8000fc64: 01000d93 li s11,16 -8000fc68: 00700413 li s0,7 -8000fc6c: 00c0006f j 8000fc78 <_svfiprintf_r+0xb40> -8000fc70: ff0c8c93 addi s9,s9,-16 -8000fc74: 059dd663 bge s11,s9,8000fcc0 <_svfiprintf_r+0xb88> -8000fc78: 01078793 addi a5,a5,16 -8000fc7c: 00170713 addi a4,a4,1 -8000fc80: 0176a023 sw s7,0(a3) -8000fc84: 01b6a223 sw s11,4(a3) -8000fc88: 04f12423 sw a5,72(sp) -8000fc8c: 04e12223 sw a4,68(sp) -8000fc90: 00868693 addi a3,a3,8 -8000fc94: fce45ee3 bge s0,a4,8000fc70 <_svfiprintf_r+0xb38> -8000fc98: 04010613 addi a2,sp,64 -8000fc9c: 000a0593 mv a1,s4 -8000fca0: 000b0513 mv a0,s6 -8000fca4: ad8ff0ef jal ra,8000ef7c <__ssprint_r> -8000fca8: f4051c63 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000fcac: ff0c8c93 addi s9,s9,-16 -8000fcb0: 04812783 lw a5,72(sp) -8000fcb4: 04412703 lw a4,68(sp) -8000fcb8: 000a8693 mv a3,s5 -8000fcbc: fb9dcee3 blt s11,s9,8000fc78 <_svfiprintf_r+0xb40> -8000fcc0: 019787b3 add a5,a5,s9 -8000fcc4: 00170713 addi a4,a4,1 -8000fcc8: 0176a023 sw s7,0(a3) -8000fccc: 0196a223 sw s9,4(a3) -8000fcd0: 04f12423 sw a5,72(sp) -8000fcd4: 04e12223 sw a4,68(sp) -8000fcd8: 00700693 li a3,7 -8000fcdc: eee6d863 bge a3,a4,8000f3cc <_svfiprintf_r+0x294> -8000fce0: 04010613 addi a2,sp,64 -8000fce4: 000a0593 mv a1,s4 -8000fce8: 000b0513 mv a0,s6 -8000fcec: a90ff0ef jal ra,8000ef7c <__ssprint_r> -8000fcf0: f0051863 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000fcf4: 04812783 lw a5,72(sp) -8000fcf8: ed4ff06f j 8000f3cc <_svfiprintf_r+0x294> -8000fcfc: 88089ae3 bnez a7,8000f590 <_svfiprintf_r+0x458> -8000fd00: 000d8913 mv s2,s11 -8000fd04: 00000893 li a7,0 -8000fd08: 00000c93 li s9,0 -8000fd0c: 0f010413 addi s0,sp,240 -8000fd10: 895ff06f j 8000f5a4 <_svfiprintf_r+0x46c> -8000fd14: 00c12703 lw a4,12(sp) -8000fd18: 01097793 andi a5,s2,16 -8000fd1c: 00470693 addi a3,a4,4 -8000fd20: 18079263 bnez a5,8000fea4 <_svfiprintf_r+0xd6c> -8000fd24: 04097793 andi a5,s2,64 -8000fd28: 36078e63 beqz a5,800100a4 <_svfiprintf_r+0xf6c> -8000fd2c: 00c12783 lw a5,12(sp) -8000fd30: 00000c13 li s8,0 -8000fd34: 00d12623 sw a3,12(sp) -8000fd38: 0007dc83 lhu s9,0(a5) -8000fd3c: 8b1ff06f j 8000f5ec <_svfiprintf_r+0x4b4> -8000fd40: 00c12703 lw a4,12(sp) -8000fd44: 010df793 andi a5,s11,16 -8000fd48: 00470693 addi a3,a4,4 -8000fd4c: 10079a63 bnez a5,8000fe60 <_svfiprintf_r+0xd28> -8000fd50: 040df793 andi a5,s11,64 -8000fd54: 38078663 beqz a5,800100e0 <_svfiprintf_r+0xfa8> -8000fd58: 00c12783 lw a5,12(sp) -8000fd5c: 00000c13 li s8,0 -8000fd60: 00d12623 sw a3,12(sp) -8000fd64: 0007dc83 lhu s9,0(a5) -8000fd68: 00100693 li a3,1 -8000fd6c: 889ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> -8000fd70: 04010613 addi a2,sp,64 -8000fd74: 000a0593 mv a1,s4 -8000fd78: 000b0513 mv a0,s6 -8000fd7c: a00ff0ef jal ra,8000ef7c <__ssprint_r> -8000fd80: e8051063 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -8000fd84: 04412583 lw a1,68(sp) -8000fd88: 04812783 lw a5,72(sp) -8000fd8c: 05410693 addi a3,sp,84 -8000fd90: 00158593 addi a1,a1,1 -8000fd94: 000a8d13 mv s10,s5 -8000fd98: e04ff06f j 8000f39c <_svfiprintf_r+0x264> -8000fd9c: 400df793 andi a5,s11,1024 -8000fda0: 03412423 sw s4,40(sp) -8000fda4: 03312623 sw s3,44(sp) -8000fda8: 000c0a13 mv s4,s8 -8000fdac: 000c8993 mv s3,s9 -8000fdb0: 00000913 li s2,0 -8000fdb4: 01812c83 lw s9,24(sp) -8000fdb8: 0f010413 addi s0,sp,240 -8000fdbc: 03112223 sw a7,36(sp) -8000fdc0: 00078c13 mv s8,a5 -8000fdc4: 0240006f j 8000fde8 <_svfiprintf_r+0xcb0> -8000fdc8: 00a00613 li a2,10 -8000fdcc: 00000693 li a3,0 -8000fdd0: 00098513 mv a0,s3 -8000fdd4: 000a0593 mv a1,s4 -8000fdd8: 6ec000ef jal ra,800104c4 <__udivdi3> -8000fddc: 320a0663 beqz s4,80010108 <_svfiprintf_r+0xfd0> -8000fde0: 00050993 mv s3,a0 -8000fde4: 00058a13 mv s4,a1 -8000fde8: 00a00613 li a2,10 -8000fdec: 00000693 li a3,0 -8000fdf0: 00098513 mv a0,s3 -8000fdf4: 000a0593 mv a1,s4 -8000fdf8: 301000ef jal ra,800108f8 <__umoddi3> -8000fdfc: 03050513 addi a0,a0,48 -8000fe00: fea40fa3 sb a0,-1(s0) -8000fe04: 00190913 addi s2,s2,1 -8000fe08: fff40413 addi s0,s0,-1 -8000fe0c: fa0c0ee3 beqz s8,8000fdc8 <_svfiprintf_r+0xc90> -8000fe10: 000cc683 lbu a3,0(s9) -8000fe14: fb269ae3 bne a3,s2,8000fdc8 <_svfiprintf_r+0xc90> -8000fe18: 0ff00793 li a5,255 -8000fe1c: faf906e3 beq s2,a5,8000fdc8 <_svfiprintf_r+0xc90> -8000fe20: 160a1c63 bnez s4,8000ff98 <_svfiprintf_r+0xe60> -8000fe24: 00900793 li a5,9 -8000fe28: 1737e863 bltu a5,s3,8000ff98 <_svfiprintf_r+0xe60> -8000fe2c: 0f010793 addi a5,sp,240 -8000fe30: 01912c23 sw s9,24(sp) -8000fe34: 02412883 lw a7,36(sp) -8000fe38: 02812a03 lw s4,40(sp) -8000fe3c: 02c12983 lw s3,44(sp) -8000fe40: 40878cb3 sub s9,a5,s0 -8000fe44: 000d8913 mv s2,s11 -8000fe48: f5cff06f j 8000f5a4 <_svfiprintf_r+0x46c> -8000fe4c: 00812703 lw a4,8(sp) -8000fe50: 41f75793 srai a5,a4,0x1f -8000fe54: 00e6a023 sw a4,0(a3) -8000fe58: 00f6a223 sw a5,4(a3) -8000fe5c: b80ff06f j 8000f1dc <_svfiprintf_r+0xa4> -8000fe60: 00d12623 sw a3,12(sp) -8000fe64: 00072c83 lw s9,0(a4) -8000fe68: 00000c13 li s8,0 -8000fe6c: 00100693 li a3,1 -8000fe70: f84ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> -8000fe74: 01812783 lw a5,24(sp) -8000fe78: 0009c683 lbu a3,0(s3) -8000fe7c: be078863 beqz a5,8000f26c <_svfiprintf_r+0x134> -8000fe80: 0007c783 lbu a5,0(a5) -8000fe84: be078463 beqz a5,8000f26c <_svfiprintf_r+0x134> -8000fe88: 40096913 ori s2,s2,1024 -8000fe8c: be0ff06f j 8000f26c <_svfiprintf_r+0x134> -8000fe90: 00072c83 lw s9,0(a4) -8000fe94: 00d12623 sw a3,12(sp) -8000fe98: 41fcdc13 srai s8,s9,0x1f -8000fe9c: 000c0693 mv a3,s8 -8000fea0: ec8ff06f j 8000f568 <_svfiprintf_r+0x430> -8000fea4: 00072c83 lw s9,0(a4) -8000fea8: 00000c13 li s8,0 -8000feac: 00d12623 sw a3,12(sp) -8000feb0: f3cff06f j 8000f5ec <_svfiprintf_r+0x4b4> -8000feb4: 800157b7 lui a5,0x80015 -8000feb8: c8c78793 addi a5,a5,-884 # 80014c8c <__BSS_END__+0xffffe050> -8000febc: 00f12a23 sw a5,20(sp) -8000fec0: 02097793 andi a5,s2,32 -8000fec4: 00040893 mv a7,s0 -8000fec8: 06078c63 beqz a5,8000ff40 <_svfiprintf_r+0xe08> -8000fecc: 00c12783 lw a5,12(sp) -8000fed0: 00778793 addi a5,a5,7 -8000fed4: ff87f793 andi a5,a5,-8 -8000fed8: 0007ac83 lw s9,0(a5) -8000fedc: 0047ac03 lw s8,4(a5) -8000fee0: 00878793 addi a5,a5,8 -8000fee4: 00f12623 sw a5,12(sp) -8000fee8: 00197613 andi a2,s2,1 -8000feec: 00060e63 beqz a2,8000ff08 <_svfiprintf_r+0xdd0> -8000fef0: 018ce633 or a2,s9,s8 -8000fef4: 00060a63 beqz a2,8000ff08 <_svfiprintf_r+0xdd0> -8000fef8: 03000613 li a2,48 -8000fefc: 02c10e23 sb a2,60(sp) -8000ff00: 02d10ea3 sb a3,61(sp) -8000ff04: 00296913 ori s2,s2,2 -8000ff08: bff97d93 andi s11,s2,-1025 -8000ff0c: 00200693 li a3,2 -8000ff10: ee4ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> -8000ff14: 00040893 mv a7,s0 -8000ff18: 00090d93 mv s11,s2 -8000ff1c: ff0ff06f j 8000f70c <_svfiprintf_r+0x5d4> -8000ff20: 00040893 mv a7,s0 -8000ff24: ea4ff06f j 8000f5c8 <_svfiprintf_r+0x490> -8000ff28: 800157b7 lui a5,0x80015 -8000ff2c: c7878793 addi a5,a5,-904 # 80014c78 <__BSS_END__+0xffffe03c> -8000ff30: 00f12a23 sw a5,20(sp) -8000ff34: 02097793 andi a5,s2,32 -8000ff38: 00040893 mv a7,s0 -8000ff3c: f80798e3 bnez a5,8000fecc <_svfiprintf_r+0xd94> -8000ff40: 00c12703 lw a4,12(sp) -8000ff44: 01097793 andi a5,s2,16 -8000ff48: 00470613 addi a2,a4,4 -8000ff4c: 08078a63 beqz a5,8000ffe0 <_svfiprintf_r+0xea8> -8000ff50: 00072c83 lw s9,0(a4) -8000ff54: 00000c13 li s8,0 -8000ff58: 00c12623 sw a2,12(sp) -8000ff5c: f8dff06f j 8000fee8 <_svfiprintf_r+0xdb0> -8000ff60: 00040513 mv a0,s0 -8000ff64: 9fdf90ef jal ra,80009960 -8000ff68: 00050c93 mv s9,a0 -8000ff6c: 01b12623 sw s11,12(sp) -8000ff70: 00000893 li a7,0 -8000ff74: e30ff06f j 8000f5a4 <_svfiprintf_r+0x46c> -8000ff78: 04000593 li a1,64 -8000ff7c: c2df70ef jal ra,80007ba8 <_malloc_r> -8000ff80: 00aa2023 sw a0,0(s4) -8000ff84: 00aa2823 sw a0,16(s4) -8000ff88: 24050c63 beqz a0,800101e0 <_svfiprintf_r+0x10a8> -8000ff8c: 04000793 li a5,64 -8000ff90: 00fa2a23 sw a5,20(s4) -8000ff94: a00ff06f j 8000f194 <_svfiprintf_r+0x5c> -8000ff98: 02012783 lw a5,32(sp) -8000ff9c: 01c12583 lw a1,28(sp) -8000ffa0: 00000913 li s2,0 -8000ffa4: 40f40433 sub s0,s0,a5 -8000ffa8: 00078613 mv a2,a5 -8000ffac: 00040513 mv a0,s0 -8000ffb0: a3df90ef jal ra,800099ec -8000ffb4: 001cc583 lbu a1,1(s9) -8000ffb8: 00a00613 li a2,10 -8000ffbc: 00000693 li a3,0 -8000ffc0: 00b03833 snez a6,a1 -8000ffc4: 00098513 mv a0,s3 -8000ffc8: 000a0593 mv a1,s4 -8000ffcc: 010c8cb3 add s9,s9,a6 -8000ffd0: 4f4000ef jal ra,800104c4 <__udivdi3> -8000ffd4: e0dff06f j 8000fde0 <_svfiprintf_r+0xca8> -8000ffd8: 00090a13 mv s4,s2 -8000ffdc: c24ff06f j 8000f400 <_svfiprintf_r+0x2c8> -8000ffe0: 04097793 andi a5,s2,64 -8000ffe4: 0a078263 beqz a5,80010088 <_svfiprintf_r+0xf50> +8000fc28: a90ff0ef jal ra,8000eeb8 <__ssprint_r> +8000fc2c: f0051863 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000fc30: 04812783 lw a5,72(sp) +8000fc34: ed4ff06f j 8000f308 <_svfiprintf_r+0x294> +8000fc38: 88089ae3 bnez a7,8000f4cc <_svfiprintf_r+0x458> +8000fc3c: 000d8913 mv s2,s11 +8000fc40: 00000893 li a7,0 +8000fc44: 00000c93 li s9,0 +8000fc48: 0f010413 addi s0,sp,240 +8000fc4c: 895ff06f j 8000f4e0 <_svfiprintf_r+0x46c> +8000fc50: 00c12703 lw a4,12(sp) +8000fc54: 01097793 andi a5,s2,16 +8000fc58: 00470693 addi a3,a4,4 +8000fc5c: 18079263 bnez a5,8000fde0 <_svfiprintf_r+0xd6c> +8000fc60: 04097793 andi a5,s2,64 +8000fc64: 36078e63 beqz a5,8000ffe0 <_svfiprintf_r+0xf6c> +8000fc68: 00c12783 lw a5,12(sp) +8000fc6c: 00000c13 li s8,0 +8000fc70: 00d12623 sw a3,12(sp) +8000fc74: 0007dc83 lhu s9,0(a5) +8000fc78: 8b1ff06f j 8000f528 <_svfiprintf_r+0x4b4> +8000fc7c: 00c12703 lw a4,12(sp) +8000fc80: 010df793 andi a5,s11,16 +8000fc84: 00470693 addi a3,a4,4 +8000fc88: 10079a63 bnez a5,8000fd9c <_svfiprintf_r+0xd28> +8000fc8c: 040df793 andi a5,s11,64 +8000fc90: 38078663 beqz a5,8001001c <_svfiprintf_r+0xfa8> +8000fc94: 00c12783 lw a5,12(sp) +8000fc98: 00000c13 li s8,0 +8000fc9c: 00d12623 sw a3,12(sp) +8000fca0: 0007dc83 lhu s9,0(a5) +8000fca4: 00100693 li a3,1 +8000fca8: 889ff06f j 8000f530 <_svfiprintf_r+0x4bc> +8000fcac: 04010613 addi a2,sp,64 +8000fcb0: 000a0593 mv a1,s4 +8000fcb4: 000b0513 mv a0,s6 +8000fcb8: a00ff0ef jal ra,8000eeb8 <__ssprint_r> +8000fcbc: e8051063 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000fcc0: 04412583 lw a1,68(sp) +8000fcc4: 04812783 lw a5,72(sp) +8000fcc8: 05410693 addi a3,sp,84 +8000fccc: 00158593 addi a1,a1,1 +8000fcd0: 000a8d13 mv s10,s5 +8000fcd4: e04ff06f j 8000f2d8 <_svfiprintf_r+0x264> +8000fcd8: 400df793 andi a5,s11,1024 +8000fcdc: 03412423 sw s4,40(sp) +8000fce0: 03312623 sw s3,44(sp) +8000fce4: 000c0a13 mv s4,s8 +8000fce8: 000c8993 mv s3,s9 +8000fcec: 00000913 li s2,0 +8000fcf0: 01812c83 lw s9,24(sp) +8000fcf4: 0f010413 addi s0,sp,240 +8000fcf8: 03112223 sw a7,36(sp) +8000fcfc: 00078c13 mv s8,a5 +8000fd00: 0240006f j 8000fd24 <_svfiprintf_r+0xcb0> +8000fd04: 00a00613 li a2,10 +8000fd08: 00000693 li a3,0 +8000fd0c: 00098513 mv a0,s3 +8000fd10: 000a0593 mv a1,s4 +8000fd14: 6ec000ef jal ra,80010400 <__udivdi3> +8000fd18: 320a0663 beqz s4,80010044 <_svfiprintf_r+0xfd0> +8000fd1c: 00050993 mv s3,a0 +8000fd20: 00058a13 mv s4,a1 +8000fd24: 00a00613 li a2,10 +8000fd28: 00000693 li a3,0 +8000fd2c: 00098513 mv a0,s3 +8000fd30: 000a0593 mv a1,s4 +8000fd34: 301000ef jal ra,80010834 <__umoddi3> +8000fd38: 03050513 addi a0,a0,48 +8000fd3c: fea40fa3 sb a0,-1(s0) +8000fd40: 00190913 addi s2,s2,1 +8000fd44: fff40413 addi s0,s0,-1 +8000fd48: fa0c0ee3 beqz s8,8000fd04 <_svfiprintf_r+0xc90> +8000fd4c: 000cc683 lbu a3,0(s9) +8000fd50: fb269ae3 bne a3,s2,8000fd04 <_svfiprintf_r+0xc90> +8000fd54: 0ff00793 li a5,255 +8000fd58: faf906e3 beq s2,a5,8000fd04 <_svfiprintf_r+0xc90> +8000fd5c: 160a1c63 bnez s4,8000fed4 <_svfiprintf_r+0xe60> +8000fd60: 00900793 li a5,9 +8000fd64: 1737e863 bltu a5,s3,8000fed4 <_svfiprintf_r+0xe60> +8000fd68: 0f010793 addi a5,sp,240 +8000fd6c: 01912c23 sw s9,24(sp) +8000fd70: 02412883 lw a7,36(sp) +8000fd74: 02812a03 lw s4,40(sp) +8000fd78: 02c12983 lw s3,44(sp) +8000fd7c: 40878cb3 sub s9,a5,s0 +8000fd80: 000d8913 mv s2,s11 +8000fd84: f5cff06f j 8000f4e0 <_svfiprintf_r+0x46c> +8000fd88: 00812703 lw a4,8(sp) +8000fd8c: 41f75793 srai a5,a4,0x1f +8000fd90: 00e6a023 sw a4,0(a3) +8000fd94: 00f6a223 sw a5,4(a3) +8000fd98: b80ff06f j 8000f118 <_svfiprintf_r+0xa4> +8000fd9c: 00d12623 sw a3,12(sp) +8000fda0: 00072c83 lw s9,0(a4) +8000fda4: 00000c13 li s8,0 +8000fda8: 00100693 li a3,1 +8000fdac: f84ff06f j 8000f530 <_svfiprintf_r+0x4bc> +8000fdb0: 01812783 lw a5,24(sp) +8000fdb4: 0009c683 lbu a3,0(s3) +8000fdb8: be078863 beqz a5,8000f1a8 <_svfiprintf_r+0x134> +8000fdbc: 0007c783 lbu a5,0(a5) +8000fdc0: be078463 beqz a5,8000f1a8 <_svfiprintf_r+0x134> +8000fdc4: 40096913 ori s2,s2,1024 +8000fdc8: be0ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000fdcc: 00072c83 lw s9,0(a4) +8000fdd0: 00d12623 sw a3,12(sp) +8000fdd4: 41fcdc13 srai s8,s9,0x1f +8000fdd8: 000c0693 mv a3,s8 +8000fddc: ec8ff06f j 8000f4a4 <_svfiprintf_r+0x430> +8000fde0: 00072c83 lw s9,0(a4) +8000fde4: 00000c13 li s8,0 +8000fde8: 00d12623 sw a3,12(sp) +8000fdec: f3cff06f j 8000f528 <_svfiprintf_r+0x4b4> +8000fdf0: 800157b7 lui a5,0x80015 +8000fdf4: bb878793 addi a5,a5,-1096 # 80014bb8 <__BSS_END__+0xffffdf7c> +8000fdf8: 00f12a23 sw a5,20(sp) +8000fdfc: 02097793 andi a5,s2,32 +8000fe00: 00040893 mv a7,s0 +8000fe04: 06078c63 beqz a5,8000fe7c <_svfiprintf_r+0xe08> +8000fe08: 00c12783 lw a5,12(sp) +8000fe0c: 00778793 addi a5,a5,7 +8000fe10: ff87f793 andi a5,a5,-8 +8000fe14: 0007ac83 lw s9,0(a5) +8000fe18: 0047ac03 lw s8,4(a5) +8000fe1c: 00878793 addi a5,a5,8 +8000fe20: 00f12623 sw a5,12(sp) +8000fe24: 00197613 andi a2,s2,1 +8000fe28: 00060e63 beqz a2,8000fe44 <_svfiprintf_r+0xdd0> +8000fe2c: 018ce633 or a2,s9,s8 +8000fe30: 00060a63 beqz a2,8000fe44 <_svfiprintf_r+0xdd0> +8000fe34: 03000613 li a2,48 +8000fe38: 02c10e23 sb a2,60(sp) +8000fe3c: 02d10ea3 sb a3,61(sp) +8000fe40: 00296913 ori s2,s2,2 +8000fe44: bff97d93 andi s11,s2,-1025 +8000fe48: 00200693 li a3,2 +8000fe4c: ee4ff06f j 8000f530 <_svfiprintf_r+0x4bc> +8000fe50: 00040893 mv a7,s0 +8000fe54: 00090d93 mv s11,s2 +8000fe58: ff0ff06f j 8000f648 <_svfiprintf_r+0x5d4> +8000fe5c: 00040893 mv a7,s0 +8000fe60: ea4ff06f j 8000f504 <_svfiprintf_r+0x490> +8000fe64: 800157b7 lui a5,0x80015 +8000fe68: ba478793 addi a5,a5,-1116 # 80014ba4 <__BSS_END__+0xffffdf68> +8000fe6c: 00f12a23 sw a5,20(sp) +8000fe70: 02097793 andi a5,s2,32 +8000fe74: 00040893 mv a7,s0 +8000fe78: f80798e3 bnez a5,8000fe08 <_svfiprintf_r+0xd94> +8000fe7c: 00c12703 lw a4,12(sp) +8000fe80: 01097793 andi a5,s2,16 +8000fe84: 00470613 addi a2,a4,4 +8000fe88: 08078a63 beqz a5,8000ff1c <_svfiprintf_r+0xea8> +8000fe8c: 00072c83 lw s9,0(a4) +8000fe90: 00000c13 li s8,0 +8000fe94: 00c12623 sw a2,12(sp) +8000fe98: f8dff06f j 8000fe24 <_svfiprintf_r+0xdb0> +8000fe9c: 00040513 mv a0,s0 +8000fea0: 9fdf90ef jal ra,8000989c +8000fea4: 00050c93 mv s9,a0 +8000fea8: 01b12623 sw s11,12(sp) +8000feac: 00000893 li a7,0 +8000feb0: e30ff06f j 8000f4e0 <_svfiprintf_r+0x46c> +8000feb4: 04000593 li a1,64 +8000feb8: c2df70ef jal ra,80007ae4 <_malloc_r> +8000febc: 00aa2023 sw a0,0(s4) +8000fec0: 00aa2823 sw a0,16(s4) +8000fec4: 24050c63 beqz a0,8001011c <_svfiprintf_r+0x10a8> +8000fec8: 04000793 li a5,64 +8000fecc: 00fa2a23 sw a5,20(s4) +8000fed0: a00ff06f j 8000f0d0 <_svfiprintf_r+0x5c> +8000fed4: 02012783 lw a5,32(sp) +8000fed8: 01c12583 lw a1,28(sp) +8000fedc: 00000913 li s2,0 +8000fee0: 40f40433 sub s0,s0,a5 +8000fee4: 00078613 mv a2,a5 +8000fee8: 00040513 mv a0,s0 +8000feec: a3df90ef jal ra,80009928 +8000fef0: 001cc583 lbu a1,1(s9) +8000fef4: 00a00613 li a2,10 +8000fef8: 00000693 li a3,0 +8000fefc: 00b03833 snez a6,a1 +8000ff00: 00098513 mv a0,s3 +8000ff04: 000a0593 mv a1,s4 +8000ff08: 010c8cb3 add s9,s9,a6 +8000ff0c: 4f4000ef jal ra,80010400 <__udivdi3> +8000ff10: e0dff06f j 8000fd1c <_svfiprintf_r+0xca8> +8000ff14: 00090a13 mv s4,s2 +8000ff18: c24ff06f j 8000f33c <_svfiprintf_r+0x2c8> +8000ff1c: 04097793 andi a5,s2,64 +8000ff20: 0a078263 beqz a5,8000ffc4 <_svfiprintf_r+0xf50> +8000ff24: 00c12783 lw a5,12(sp) +8000ff28: 00000c13 li s8,0 +8000ff2c: 00c12623 sw a2,12(sp) +8000ff30: 0007dc83 lhu s9,0(a5) +8000ff34: ef1ff06f j 8000fe24 <_svfiprintf_r+0xdb0> +8000ff38: 04010613 addi a2,sp,64 +8000ff3c: 000a0593 mv a1,s4 +8000ff40: 000b0513 mv a0,s6 +8000ff44: 03112223 sw a7,36(sp) +8000ff48: f71fe0ef jal ra,8000eeb8 <__ssprint_r> +8000ff4c: be051863 bnez a0,8000f33c <_svfiprintf_r+0x2c8> +8000ff50: 04412603 lw a2,68(sp) +8000ff54: 04812783 lw a5,72(sp) +8000ff58: 02412883 lw a7,36(sp) +8000ff5c: 05410693 addi a3,sp,84 +8000ff60: 00160593 addi a1,a2,1 +8000ff64: 000a8d13 mv s10,s5 +8000ff68: b68ff06f j 8000f2d0 <_svfiprintf_r+0x25c> +8000ff6c: 0019c683 lbu a3,1(s3) +8000ff70: 20096913 ori s2,s2,512 +8000ff74: 00198993 addi s3,s3,1 +8000ff78: a30ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000ff7c: 0019c683 lbu a3,1(s3) +8000ff80: 02096913 ori s2,s2,32 +8000ff84: 00198993 addi s3,s3,1 +8000ff88: a20ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8000ff8c: 00040a13 mv s4,s0 +8000ff90: bacff06f j 8000f33c <_svfiprintf_r+0x2c8> +8000ff94: 00812783 lw a5,8(sp) +8000ff98: 00f6a023 sw a5,0(a3) +8000ff9c: 97cff06f j 8000f118 <_svfiprintf_r+0xa4> +8000ffa0: 00600793 li a5,6 +8000ffa4: 00088c93 mv s9,a7 +8000ffa8: 0117f463 bgeu a5,a7,8000ffb0 <_svfiprintf_r+0xf3c> +8000ffac: 00600c93 li s9,6 +8000ffb0: 80015e37 lui t3,0x80015 +8000ffb4: 000c8c13 mv s8,s9 +8000ffb8: 01b12623 sw s11,12(sp) +8000ffbc: bcce0413 addi s0,t3,-1076 # 80014bcc <__BSS_END__+0xffffdf90> +8000ffc0: a58ff06f j 8000f218 <_svfiprintf_r+0x1a4> +8000ffc4: 20097793 andi a5,s2,512 +8000ffc8: 0c078663 beqz a5,80010094 <_svfiprintf_r+0x1020> +8000ffcc: 00c12783 lw a5,12(sp) +8000ffd0: 00000c13 li s8,0 +8000ffd4: 00c12623 sw a2,12(sp) +8000ffd8: 0007cc83 lbu s9,0(a5) +8000ffdc: e49ff06f j 8000fe24 <_svfiprintf_r+0xdb0> +8000ffe0: 20097793 andi a5,s2,512 +8000ffe4: 08078e63 beqz a5,80010080 <_svfiprintf_r+0x100c> 8000ffe8: 00c12783 lw a5,12(sp) 8000ffec: 00000c13 li s8,0 -8000fff0: 00c12623 sw a2,12(sp) -8000fff4: 0007dc83 lhu s9,0(a5) -8000fff8: ef1ff06f j 8000fee8 <_svfiprintf_r+0xdb0> -8000fffc: 04010613 addi a2,sp,64 -80010000: 000a0593 mv a1,s4 -80010004: 000b0513 mv a0,s6 -80010008: 03112223 sw a7,36(sp) -8001000c: f71fe0ef jal ra,8000ef7c <__ssprint_r> -80010010: be051863 bnez a0,8000f400 <_svfiprintf_r+0x2c8> -80010014: 04412603 lw a2,68(sp) -80010018: 04812783 lw a5,72(sp) -8001001c: 02412883 lw a7,36(sp) -80010020: 05410693 addi a3,sp,84 -80010024: 00160593 addi a1,a2,1 -80010028: 000a8d13 mv s10,s5 -8001002c: b68ff06f j 8000f394 <_svfiprintf_r+0x25c> -80010030: 0019c683 lbu a3,1(s3) -80010034: 20096913 ori s2,s2,512 -80010038: 00198993 addi s3,s3,1 -8001003c: a30ff06f j 8000f26c <_svfiprintf_r+0x134> -80010040: 0019c683 lbu a3,1(s3) -80010044: 02096913 ori s2,s2,32 -80010048: 00198993 addi s3,s3,1 -8001004c: a20ff06f j 8000f26c <_svfiprintf_r+0x134> -80010050: 00040a13 mv s4,s0 -80010054: bacff06f j 8000f400 <_svfiprintf_r+0x2c8> -80010058: 00812783 lw a5,8(sp) -8001005c: 00f6a023 sw a5,0(a3) -80010060: 97cff06f j 8000f1dc <_svfiprintf_r+0xa4> -80010064: 00600793 li a5,6 -80010068: 00088c93 mv s9,a7 -8001006c: 0117f463 bgeu a5,a7,80010074 <_svfiprintf_r+0xf3c> -80010070: 00600c93 li s9,6 -80010074: 80015e37 lui t3,0x80015 -80010078: 000c8c13 mv s8,s9 -8001007c: 01b12623 sw s11,12(sp) -80010080: ca0e0413 addi s0,t3,-864 # 80014ca0 <__BSS_END__+0xffffe064> -80010084: a58ff06f j 8000f2dc <_svfiprintf_r+0x1a4> -80010088: 20097793 andi a5,s2,512 -8001008c: 0c078663 beqz a5,80010158 <_svfiprintf_r+0x1020> -80010090: 00c12783 lw a5,12(sp) -80010094: 00000c13 li s8,0 -80010098: 00c12623 sw a2,12(sp) -8001009c: 0007cc83 lbu s9,0(a5) -800100a0: e49ff06f j 8000fee8 <_svfiprintf_r+0xdb0> -800100a4: 20097793 andi a5,s2,512 -800100a8: 08078e63 beqz a5,80010144 <_svfiprintf_r+0x100c> -800100ac: 00c12783 lw a5,12(sp) -800100b0: 00000c13 li s8,0 -800100b4: 00d12623 sw a3,12(sp) -800100b8: 0007cc83 lbu s9,0(a5) -800100bc: d30ff06f j 8000f5ec <_svfiprintf_r+0x4b4> -800100c0: 20097793 andi a5,s2,512 -800100c4: 06078463 beqz a5,8001012c <_svfiprintf_r+0xff4> -800100c8: 00c12783 lw a5,12(sp) -800100cc: 00d12623 sw a3,12(sp) -800100d0: 00078c83 lb s9,0(a5) -800100d4: 41fcdc13 srai s8,s9,0x1f -800100d8: 000c0693 mv a3,s8 -800100dc: c8cff06f j 8000f568 <_svfiprintf_r+0x430> -800100e0: 200df793 andi a5,s11,512 -800100e4: 02078863 beqz a5,80010114 <_svfiprintf_r+0xfdc> -800100e8: 00c12783 lw a5,12(sp) -800100ec: 00000c13 li s8,0 -800100f0: 00d12623 sw a3,12(sp) -800100f4: 0007cc83 lbu s9,0(a5) -800100f8: 00100693 li a3,1 -800100fc: cf8ff06f j 8000f5f4 <_svfiprintf_r+0x4bc> -80010100: 00068613 mv a2,a3 -80010104: 931ff06f j 8000fa34 <_svfiprintf_r+0x8fc> -80010108: 00900793 li a5,9 -8001010c: cd37eae3 bltu a5,s3,8000fde0 <_svfiprintf_r+0xca8> -80010110: d1dff06f j 8000fe2c <_svfiprintf_r+0xcf4> -80010114: 00c12783 lw a5,12(sp) -80010118: 00000c13 li s8,0 -8001011c: 00d12623 sw a3,12(sp) -80010120: 0007ac83 lw s9,0(a5) -80010124: 00100693 li a3,1 -80010128: cccff06f j 8000f5f4 <_svfiprintf_r+0x4bc> -8001012c: 00c12783 lw a5,12(sp) -80010130: 00d12623 sw a3,12(sp) -80010134: 0007ac83 lw s9,0(a5) -80010138: 41fcdc13 srai s8,s9,0x1f -8001013c: 000c0693 mv a3,s8 -80010140: c28ff06f j 8000f568 <_svfiprintf_r+0x430> -80010144: 00c12783 lw a5,12(sp) -80010148: 00000c13 li s8,0 -8001014c: 00d12623 sw a3,12(sp) -80010150: 0007ac83 lw s9,0(a5) -80010154: c98ff06f j 8000f5ec <_svfiprintf_r+0x4b4> -80010158: 00c12783 lw a5,12(sp) -8001015c: 00000c13 li s8,0 -80010160: 00c12623 sw a2,12(sp) -80010164: 0007ac83 lw s9,0(a5) -80010168: d81ff06f j 8000fee8 <_svfiprintf_r+0xdb0> -8001016c: 00812783 lw a5,8(sp) -80010170: 00f69023 sh a5,0(a3) -80010174: 868ff06f j 8000f1dc <_svfiprintf_r+0xa4> -80010178: 04010613 addi a2,sp,64 -8001017c: 000a0593 mv a1,s4 -80010180: 000b0513 mv a0,s6 -80010184: df9fe0ef jal ra,8000ef7c <__ssprint_r> -80010188: a78ff06f j 8000f400 <_svfiprintf_r+0x2c8> -8001018c: 00088c93 mv s9,a7 -80010190: 01b12623 sw s11,12(sp) -80010194: 00000893 li a7,0 -80010198: c0cff06f j 8000f5a4 <_svfiprintf_r+0x46c> -8001019c: 00090d93 mv s11,s2 -800101a0: bf0ff06f j 8000f590 <_svfiprintf_r+0x458> -800101a4: 00068513 mv a0,a3 -800101a8: 00058613 mv a2,a1 -800101ac: fe4ff06f j 8000f990 <_svfiprintf_r+0x858> -800101b0: fff00793 li a5,-1 -800101b4: 00f12423 sw a5,8(sp) -800101b8: a54ff06f j 8000f40c <_svfiprintf_r+0x2d4> -800101bc: 00c12783 lw a5,12(sp) -800101c0: 0007a403 lw s0,0(a5) -800101c4: 00478793 addi a5,a5,4 -800101c8: 00045463 bgez s0,800101d0 <_svfiprintf_r+0x1098> -800101cc: fff00413 li s0,-1 -800101d0: 0019c683 lbu a3,1(s3) -800101d4: 00f12623 sw a5,12(sp) -800101d8: 00070993 mv s3,a4 -800101dc: 890ff06f j 8000f26c <_svfiprintf_r+0x134> -800101e0: 00c00793 li a5,12 -800101e4: 00fb2023 sw a5,0(s6) -800101e8: fff00793 li a5,-1 -800101ec: 00f12423 sw a5,8(sp) -800101f0: a1cff06f j 8000f40c <_svfiprintf_r+0x2d4> +8000fff0: 00d12623 sw a3,12(sp) +8000fff4: 0007cc83 lbu s9,0(a5) +8000fff8: d30ff06f j 8000f528 <_svfiprintf_r+0x4b4> +8000fffc: 20097793 andi a5,s2,512 +80010000: 06078463 beqz a5,80010068 <_svfiprintf_r+0xff4> +80010004: 00c12783 lw a5,12(sp) +80010008: 00d12623 sw a3,12(sp) +8001000c: 00078c83 lb s9,0(a5) +80010010: 41fcdc13 srai s8,s9,0x1f +80010014: 000c0693 mv a3,s8 +80010018: c8cff06f j 8000f4a4 <_svfiprintf_r+0x430> +8001001c: 200df793 andi a5,s11,512 +80010020: 02078863 beqz a5,80010050 <_svfiprintf_r+0xfdc> +80010024: 00c12783 lw a5,12(sp) +80010028: 00000c13 li s8,0 +8001002c: 00d12623 sw a3,12(sp) +80010030: 0007cc83 lbu s9,0(a5) +80010034: 00100693 li a3,1 +80010038: cf8ff06f j 8000f530 <_svfiprintf_r+0x4bc> +8001003c: 00068613 mv a2,a3 +80010040: 931ff06f j 8000f970 <_svfiprintf_r+0x8fc> +80010044: 00900793 li a5,9 +80010048: cd37eae3 bltu a5,s3,8000fd1c <_svfiprintf_r+0xca8> +8001004c: d1dff06f j 8000fd68 <_svfiprintf_r+0xcf4> +80010050: 00c12783 lw a5,12(sp) +80010054: 00000c13 li s8,0 +80010058: 00d12623 sw a3,12(sp) +8001005c: 0007ac83 lw s9,0(a5) +80010060: 00100693 li a3,1 +80010064: cccff06f j 8000f530 <_svfiprintf_r+0x4bc> +80010068: 00c12783 lw a5,12(sp) +8001006c: 00d12623 sw a3,12(sp) +80010070: 0007ac83 lw s9,0(a5) +80010074: 41fcdc13 srai s8,s9,0x1f +80010078: 000c0693 mv a3,s8 +8001007c: c28ff06f j 8000f4a4 <_svfiprintf_r+0x430> +80010080: 00c12783 lw a5,12(sp) +80010084: 00000c13 li s8,0 +80010088: 00d12623 sw a3,12(sp) +8001008c: 0007ac83 lw s9,0(a5) +80010090: c98ff06f j 8000f528 <_svfiprintf_r+0x4b4> +80010094: 00c12783 lw a5,12(sp) +80010098: 00000c13 li s8,0 +8001009c: 00c12623 sw a2,12(sp) +800100a0: 0007ac83 lw s9,0(a5) +800100a4: d81ff06f j 8000fe24 <_svfiprintf_r+0xdb0> +800100a8: 00812783 lw a5,8(sp) +800100ac: 00f69023 sh a5,0(a3) +800100b0: 868ff06f j 8000f118 <_svfiprintf_r+0xa4> +800100b4: 04010613 addi a2,sp,64 +800100b8: 000a0593 mv a1,s4 +800100bc: 000b0513 mv a0,s6 +800100c0: df9fe0ef jal ra,8000eeb8 <__ssprint_r> +800100c4: a78ff06f j 8000f33c <_svfiprintf_r+0x2c8> +800100c8: 00088c93 mv s9,a7 +800100cc: 01b12623 sw s11,12(sp) +800100d0: 00000893 li a7,0 +800100d4: c0cff06f j 8000f4e0 <_svfiprintf_r+0x46c> +800100d8: 00090d93 mv s11,s2 +800100dc: bf0ff06f j 8000f4cc <_svfiprintf_r+0x458> +800100e0: 00068513 mv a0,a3 +800100e4: 00058613 mv a2,a1 +800100e8: fe4ff06f j 8000f8cc <_svfiprintf_r+0x858> +800100ec: fff00793 li a5,-1 +800100f0: 00f12423 sw a5,8(sp) +800100f4: a54ff06f j 8000f348 <_svfiprintf_r+0x2d4> +800100f8: 00c12783 lw a5,12(sp) +800100fc: 0007a403 lw s0,0(a5) +80010100: 00478793 addi a5,a5,4 +80010104: 00045463 bgez s0,8001010c <_svfiprintf_r+0x1098> +80010108: fff00413 li s0,-1 +8001010c: 0019c683 lbu a3,1(s3) +80010110: 00f12623 sw a5,12(sp) +80010114: 00070993 mv s3,a4 +80010118: 890ff06f j 8000f1a8 <_svfiprintf_r+0x134> +8001011c: 00c00793 li a5,12 +80010120: 00fb2023 sw a5,0(s6) +80010124: fff00793 li a5,-1 +80010128: 00f12423 sw a5,8(sp) +8001012c: a1cff06f j 8000f348 <_svfiprintf_r+0x2d4> -800101f4 <__swbuf_r>: -800101f4: fe010113 addi sp,sp,-32 -800101f8: 00812c23 sw s0,24(sp) -800101fc: 00912a23 sw s1,20(sp) -80010200: 01212823 sw s2,16(sp) -80010204: 00112e23 sw ra,28(sp) -80010208: 01312623 sw s3,12(sp) -8001020c: 00050913 mv s2,a0 -80010210: 00058493 mv s1,a1 -80010214: 00060413 mv s0,a2 -80010218: 00050663 beqz a0,80010224 <__swbuf_r+0x30> -8001021c: 03852783 lw a5,56(a0) -80010220: 14078863 beqz a5,80010370 <__swbuf_r+0x17c> -80010224: 00c41703 lh a4,12(s0) -80010228: 01842683 lw a3,24(s0) -8001022c: 00877793 andi a5,a4,8 -80010230: 00d42423 sw a3,8(s0) -80010234: 01071693 slli a3,a4,0x10 -80010238: 0106d693 srli a3,a3,0x10 -8001023c: 08078263 beqz a5,800102c0 <__swbuf_r+0xcc> -80010240: 01042783 lw a5,16(s0) -80010244: 06078e63 beqz a5,800102c0 <__swbuf_r+0xcc> -80010248: 01269613 slli a2,a3,0x12 -8001024c: 0ff4f993 andi s3,s1,255 -80010250: 0ff4f493 andi s1,s1,255 -80010254: 08065e63 bgez a2,800102f0 <__swbuf_r+0xfc> -80010258: 00042703 lw a4,0(s0) -8001025c: 01442683 lw a3,20(s0) -80010260: 40f707b3 sub a5,a4,a5 -80010264: 0ad7de63 bge a5,a3,80010320 <__swbuf_r+0x12c> -80010268: 00842683 lw a3,8(s0) -8001026c: 00170613 addi a2,a4,1 -80010270: 00c42023 sw a2,0(s0) -80010274: fff68693 addi a3,a3,-1 -80010278: 00d42423 sw a3,8(s0) -8001027c: 01370023 sb s3,0(a4) -80010280: 01442703 lw a4,20(s0) -80010284: 00178793 addi a5,a5,1 -80010288: 0cf70863 beq a4,a5,80010358 <__swbuf_r+0x164> -8001028c: 00c45783 lhu a5,12(s0) -80010290: 0017f793 andi a5,a5,1 -80010294: 00078663 beqz a5,800102a0 <__swbuf_r+0xac> -80010298: 00a00793 li a5,10 -8001029c: 0af48e63 beq s1,a5,80010358 <__swbuf_r+0x164> -800102a0: 01c12083 lw ra,28(sp) -800102a4: 01812403 lw s0,24(sp) -800102a8: 01012903 lw s2,16(sp) -800102ac: 00c12983 lw s3,12(sp) -800102b0: 00048513 mv a0,s1 -800102b4: 01412483 lw s1,20(sp) -800102b8: 02010113 addi sp,sp,32 -800102bc: 00008067 ret -800102c0: 00040593 mv a1,s0 -800102c4: 00090513 mv a0,s2 -800102c8: cb9f30ef jal ra,80003f80 <__swsetup_r> -800102cc: 08051e63 bnez a0,80010368 <__swbuf_r+0x174> -800102d0: 00c41703 lh a4,12(s0) -800102d4: 0ff4f993 andi s3,s1,255 -800102d8: 01042783 lw a5,16(s0) -800102dc: 01071693 slli a3,a4,0x10 -800102e0: 0106d693 srli a3,a3,0x10 -800102e4: 01269613 slli a2,a3,0x12 -800102e8: 0ff4f493 andi s1,s1,255 -800102ec: f60646e3 bltz a2,80010258 <__swbuf_r+0x64> -800102f0: 06442683 lw a3,100(s0) -800102f4: 00002637 lui a2,0x2 -800102f8: 00c76733 or a4,a4,a2 -800102fc: ffffe637 lui a2,0xffffe -80010300: fff60613 addi a2,a2,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> -80010304: 00c6f6b3 and a3,a3,a2 -80010308: 00e41623 sh a4,12(s0) -8001030c: 00042703 lw a4,0(s0) -80010310: 06d42223 sw a3,100(s0) -80010314: 01442683 lw a3,20(s0) -80010318: 40f707b3 sub a5,a4,a5 -8001031c: f4d7c6e3 blt a5,a3,80010268 <__swbuf_r+0x74> -80010320: 00040593 mv a1,s0 -80010324: 00090513 mv a0,s2 -80010328: 944f40ef jal ra,8000446c <_fflush_r> -8001032c: 02051e63 bnez a0,80010368 <__swbuf_r+0x174> -80010330: 00042703 lw a4,0(s0) -80010334: 00842683 lw a3,8(s0) -80010338: 00100793 li a5,1 -8001033c: 00170613 addi a2,a4,1 -80010340: fff68693 addi a3,a3,-1 -80010344: 00c42023 sw a2,0(s0) -80010348: 00d42423 sw a3,8(s0) -8001034c: 01370023 sb s3,0(a4) -80010350: 01442703 lw a4,20(s0) -80010354: f2f71ce3 bne a4,a5,8001028c <__swbuf_r+0x98> -80010358: 00040593 mv a1,s0 -8001035c: 00090513 mv a0,s2 -80010360: 90cf40ef jal ra,8000446c <_fflush_r> -80010364: f2050ee3 beqz a0,800102a0 <__swbuf_r+0xac> -80010368: fff00493 li s1,-1 -8001036c: f35ff06f j 800102a0 <__swbuf_r+0xac> -80010370: c98f40ef jal ra,80004808 <__sinit> -80010374: eb1ff06f j 80010224 <__swbuf_r+0x30> +80010130 <__swbuf_r>: +80010130: fe010113 addi sp,sp,-32 +80010134: 00812c23 sw s0,24(sp) +80010138: 00912a23 sw s1,20(sp) +8001013c: 01212823 sw s2,16(sp) +80010140: 00112e23 sw ra,28(sp) +80010144: 01312623 sw s3,12(sp) +80010148: 00050913 mv s2,a0 +8001014c: 00058493 mv s1,a1 +80010150: 00060413 mv s0,a2 +80010154: 00050663 beqz a0,80010160 <__swbuf_r+0x30> +80010158: 03852783 lw a5,56(a0) +8001015c: 14078863 beqz a5,800102ac <__swbuf_r+0x17c> +80010160: 00c41703 lh a4,12(s0) +80010164: 01842683 lw a3,24(s0) +80010168: 00877793 andi a5,a4,8 +8001016c: 00d42423 sw a3,8(s0) +80010170: 01071693 slli a3,a4,0x10 +80010174: 0106d693 srli a3,a3,0x10 +80010178: 08078263 beqz a5,800101fc <__swbuf_r+0xcc> +8001017c: 01042783 lw a5,16(s0) +80010180: 06078e63 beqz a5,800101fc <__swbuf_r+0xcc> +80010184: 01269613 slli a2,a3,0x12 +80010188: 0ff4f993 andi s3,s1,255 +8001018c: 0ff4f493 andi s1,s1,255 +80010190: 08065e63 bgez a2,8001022c <__swbuf_r+0xfc> +80010194: 00042703 lw a4,0(s0) +80010198: 01442683 lw a3,20(s0) +8001019c: 40f707b3 sub a5,a4,a5 +800101a0: 0ad7de63 bge a5,a3,8001025c <__swbuf_r+0x12c> +800101a4: 00842683 lw a3,8(s0) +800101a8: 00170613 addi a2,a4,1 +800101ac: 00c42023 sw a2,0(s0) +800101b0: fff68693 addi a3,a3,-1 +800101b4: 00d42423 sw a3,8(s0) +800101b8: 01370023 sb s3,0(a4) +800101bc: 01442703 lw a4,20(s0) +800101c0: 00178793 addi a5,a5,1 +800101c4: 0cf70863 beq a4,a5,80010294 <__swbuf_r+0x164> +800101c8: 00c45783 lhu a5,12(s0) +800101cc: 0017f793 andi a5,a5,1 +800101d0: 00078663 beqz a5,800101dc <__swbuf_r+0xac> +800101d4: 00a00793 li a5,10 +800101d8: 0af48e63 beq s1,a5,80010294 <__swbuf_r+0x164> +800101dc: 01c12083 lw ra,28(sp) +800101e0: 01812403 lw s0,24(sp) +800101e4: 01012903 lw s2,16(sp) +800101e8: 00c12983 lw s3,12(sp) +800101ec: 00048513 mv a0,s1 +800101f0: 01412483 lw s1,20(sp) +800101f4: 02010113 addi sp,sp,32 +800101f8: 00008067 ret +800101fc: 00040593 mv a1,s0 +80010200: 00090513 mv a0,s2 +80010204: cb9f30ef jal ra,80003ebc <__swsetup_r> +80010208: 08051e63 bnez a0,800102a4 <__swbuf_r+0x174> +8001020c: 00c41703 lh a4,12(s0) +80010210: 0ff4f993 andi s3,s1,255 +80010214: 01042783 lw a5,16(s0) +80010218: 01071693 slli a3,a4,0x10 +8001021c: 0106d693 srli a3,a3,0x10 +80010220: 01269613 slli a2,a3,0x12 +80010224: 0ff4f493 andi s1,s1,255 +80010228: f60646e3 bltz a2,80010194 <__swbuf_r+0x64> +8001022c: 06442683 lw a3,100(s0) +80010230: 00002637 lui a2,0x2 +80010234: 00c76733 or a4,a4,a2 +80010238: ffffe637 lui a2,0xffffe +8001023c: fff60613 addi a2,a2,-1 # ffffdfff <__BSS_END__+0x7ffe73c3> +80010240: 00c6f6b3 and a3,a3,a2 +80010244: 00e41623 sh a4,12(s0) +80010248: 00042703 lw a4,0(s0) +8001024c: 06d42223 sw a3,100(s0) +80010250: 01442683 lw a3,20(s0) +80010254: 40f707b3 sub a5,a4,a5 +80010258: f4d7c6e3 blt a5,a3,800101a4 <__swbuf_r+0x74> +8001025c: 00040593 mv a1,s0 +80010260: 00090513 mv a0,s2 +80010264: 944f40ef jal ra,800043a8 <_fflush_r> +80010268: 02051e63 bnez a0,800102a4 <__swbuf_r+0x174> +8001026c: 00042703 lw a4,0(s0) +80010270: 00842683 lw a3,8(s0) +80010274: 00100793 li a5,1 +80010278: 00170613 addi a2,a4,1 +8001027c: fff68693 addi a3,a3,-1 +80010280: 00c42023 sw a2,0(s0) +80010284: 00d42423 sw a3,8(s0) +80010288: 01370023 sb s3,0(a4) +8001028c: 01442703 lw a4,20(s0) +80010290: f2f71ce3 bne a4,a5,800101c8 <__swbuf_r+0x98> +80010294: 00040593 mv a1,s0 +80010298: 00090513 mv a0,s2 +8001029c: 90cf40ef jal ra,800043a8 <_fflush_r> +800102a0: f2050ee3 beqz a0,800101dc <__swbuf_r+0xac> +800102a4: fff00493 li s1,-1 +800102a8: f35ff06f j 800101dc <__swbuf_r+0xac> +800102ac: c98f40ef jal ra,80004744 <__sinit> +800102b0: eb1ff06f j 80010160 <__swbuf_r+0x30> -80010378 <__swbuf>: -80010378: 00050793 mv a5,a0 -8001037c: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> -80010380: 00058613 mv a2,a1 -80010384: 00078593 mv a1,a5 -80010388: e6dff06f j 800101f4 <__swbuf_r> +800102b4 <__swbuf>: +800102b4: 00050793 mv a5,a0 +800102b8: 3601a503 lw a0,864(gp) # 80016b68 <_impure_ptr> +800102bc: 00058613 mv a2,a1 +800102c0: 00078593 mv a1,a5 +800102c4: e6dff06f j 80010130 <__swbuf_r> -8001038c <_wcrtomb_r>: -8001038c: fe010113 addi sp,sp,-32 -80010390: 00812c23 sw s0,24(sp) -80010394: 00912a23 sw s1,20(sp) -80010398: 00112e23 sw ra,28(sp) -8001039c: 2a81a783 lw a5,680(gp) # 80016ab0 <__global_locale+0xe0> -800103a0: 00050413 mv s0,a0 -800103a4: 00068493 mv s1,a3 -800103a8: 02058263 beqz a1,800103cc <_wcrtomb_r+0x40> -800103ac: 000780e7 jalr a5 -800103b0: fff00793 li a5,-1 -800103b4: 02f50663 beq a0,a5,800103e0 <_wcrtomb_r+0x54> -800103b8: 01c12083 lw ra,28(sp) -800103bc: 01812403 lw s0,24(sp) -800103c0: 01412483 lw s1,20(sp) -800103c4: 02010113 addi sp,sp,32 -800103c8: 00008067 ret -800103cc: 00000613 li a2,0 -800103d0: 00410593 addi a1,sp,4 -800103d4: 000780e7 jalr a5 -800103d8: fff00793 li a5,-1 -800103dc: fcf51ee3 bne a0,a5,800103b8 <_wcrtomb_r+0x2c> -800103e0: 0004a023 sw zero,0(s1) -800103e4: 08a00793 li a5,138 -800103e8: 01c12083 lw ra,28(sp) -800103ec: 00f42023 sw a5,0(s0) -800103f0: 01812403 lw s0,24(sp) -800103f4: 01412483 lw s1,20(sp) -800103f8: 02010113 addi sp,sp,32 +800102c8 <_wcrtomb_r>: +800102c8: fe010113 addi sp,sp,-32 +800102cc: 00812c23 sw s0,24(sp) +800102d0: 00912a23 sw s1,20(sp) +800102d4: 00112e23 sw ra,28(sp) +800102d8: 2a81a783 lw a5,680(gp) # 80016ab0 <__global_locale+0xe0> +800102dc: 00050413 mv s0,a0 +800102e0: 00068493 mv s1,a3 +800102e4: 02058263 beqz a1,80010308 <_wcrtomb_r+0x40> +800102e8: 000780e7 jalr a5 +800102ec: fff00793 li a5,-1 +800102f0: 02f50663 beq a0,a5,8001031c <_wcrtomb_r+0x54> +800102f4: 01c12083 lw ra,28(sp) +800102f8: 01812403 lw s0,24(sp) +800102fc: 01412483 lw s1,20(sp) +80010300: 02010113 addi sp,sp,32 +80010304: 00008067 ret +80010308: 00000613 li a2,0 +8001030c: 00410593 addi a1,sp,4 +80010310: 000780e7 jalr a5 +80010314: fff00793 li a5,-1 +80010318: fcf51ee3 bne a0,a5,800102f4 <_wcrtomb_r+0x2c> +8001031c: 0004a023 sw zero,0(s1) +80010320: 08a00793 li a5,138 +80010324: 01c12083 lw ra,28(sp) +80010328: 00f42023 sw a5,0(s0) +8001032c: 01812403 lw s0,24(sp) +80010330: 01412483 lw s1,20(sp) +80010334: 02010113 addi sp,sp,32 +80010338: 00008067 ret + +8001033c : +8001033c: fe010113 addi sp,sp,-32 +80010340: 00812c23 sw s0,24(sp) +80010344: 00912a23 sw s1,20(sp) +80010348: 00112e23 sw ra,28(sp) +8001034c: 3601a483 lw s1,864(gp) # 80016b68 <_impure_ptr> +80010350: 2a81a783 lw a5,680(gp) # 80016ab0 <__global_locale+0xe0> +80010354: 00060413 mv s0,a2 +80010358: 02050a63 beqz a0,8001038c +8001035c: 00058613 mv a2,a1 +80010360: 00040693 mv a3,s0 +80010364: 00050593 mv a1,a0 +80010368: 00048513 mv a0,s1 +8001036c: 000780e7 jalr a5 +80010370: fff00793 li a5,-1 +80010374: 02f50a63 beq a0,a5,800103a8 +80010378: 01c12083 lw ra,28(sp) +8001037c: 01812403 lw s0,24(sp) +80010380: 01412483 lw s1,20(sp) +80010384: 02010113 addi sp,sp,32 +80010388: 00008067 ret +8001038c: 00060693 mv a3,a2 +80010390: 00410593 addi a1,sp,4 +80010394: 00000613 li a2,0 +80010398: 00048513 mv a0,s1 +8001039c: 000780e7 jalr a5 +800103a0: fff00793 li a5,-1 +800103a4: fcf51ae3 bne a0,a5,80010378 +800103a8: 00042023 sw zero,0(s0) +800103ac: 01c12083 lw ra,28(sp) +800103b0: 01812403 lw s0,24(sp) +800103b4: 08a00793 li a5,138 +800103b8: 00f4a023 sw a5,0(s1) +800103bc: 01412483 lw s1,20(sp) +800103c0: 02010113 addi sp,sp,32 +800103c4: 00008067 ret + +800103c8 <_wctomb_r>: +800103c8: 2a81a303 lw t1,680(gp) # 80016ab0 <__global_locale+0xe0> +800103cc: 00030067 jr t1 + +800103d0 <__ascii_wctomb>: +800103d0: 02058463 beqz a1,800103f8 <__ascii_wctomb+0x28> +800103d4: 0ff00793 li a5,255 +800103d8: 00c7e863 bltu a5,a2,800103e8 <__ascii_wctomb+0x18> +800103dc: 00c58023 sb a2,0(a1) +800103e0: 00100513 li a0,1 +800103e4: 00008067 ret +800103e8: 08a00793 li a5,138 +800103ec: 00f52023 sw a5,0(a0) +800103f0: fff00513 li a0,-1 +800103f4: 00008067 ret +800103f8: 00000513 li a0,0 800103fc: 00008067 ret -80010400 : -80010400: fe010113 addi sp,sp,-32 -80010404: 00812c23 sw s0,24(sp) -80010408: 00912a23 sw s1,20(sp) -8001040c: 00112e23 sw ra,28(sp) -80010410: 3601a483 lw s1,864(gp) # 80016b68 <_impure_ptr> -80010414: 2a81a783 lw a5,680(gp) # 80016ab0 <__global_locale+0xe0> -80010418: 00060413 mv s0,a2 -8001041c: 02050a63 beqz a0,80010450 -80010420: 00058613 mv a2,a1 -80010424: 00040693 mv a3,s0 -80010428: 00050593 mv a1,a0 -8001042c: 00048513 mv a0,s1 -80010430: 000780e7 jalr a5 -80010434: fff00793 li a5,-1 -80010438: 02f50a63 beq a0,a5,8001046c -8001043c: 01c12083 lw ra,28(sp) -80010440: 01812403 lw s0,24(sp) -80010444: 01412483 lw s1,20(sp) -80010448: 02010113 addi sp,sp,32 -8001044c: 00008067 ret -80010450: 00060693 mv a3,a2 -80010454: 00410593 addi a1,sp,4 -80010458: 00000613 li a2,0 -8001045c: 00048513 mv a0,s1 -80010460: 000780e7 jalr a5 -80010464: fff00793 li a5,-1 -80010468: fcf51ae3 bne a0,a5,8001043c -8001046c: 00042023 sw zero,0(s0) -80010470: 01c12083 lw ra,28(sp) -80010474: 01812403 lw s0,24(sp) -80010478: 08a00793 li a5,138 -8001047c: 00f4a023 sw a5,0(s1) -80010480: 01412483 lw s1,20(sp) -80010484: 02010113 addi sp,sp,32 -80010488: 00008067 ret +80010400 <__udivdi3>: +80010400: 00050893 mv a7,a0 +80010404: 00058793 mv a5,a1 +80010408: 00060813 mv a6,a2 +8001040c: 00068513 mv a0,a3 +80010410: 00088313 mv t1,a7 +80010414: 28069463 bnez a3,8001069c <__udivdi3+0x29c> +80010418: 800156b7 lui a3,0x80015 +8001041c: 77468693 addi a3,a3,1908 # 80015774 <__BSS_END__+0xffffeb38> +80010420: 0ec5f663 bgeu a1,a2,8001050c <__udivdi3+0x10c> +80010424: 00010737 lui a4,0x10 +80010428: 0ce67863 bgeu a2,a4,800104f8 <__udivdi3+0xf8> +8001042c: 0ff00713 li a4,255 +80010430: 00c73733 sltu a4,a4,a2 +80010434: 00371713 slli a4,a4,0x3 +80010438: 00e65533 srl a0,a2,a4 +8001043c: 00a686b3 add a3,a3,a0 +80010440: 0006c683 lbu a3,0(a3) +80010444: 02000513 li a0,32 +80010448: 00e68733 add a4,a3,a4 +8001044c: 40e506b3 sub a3,a0,a4 +80010450: 00e50c63 beq a0,a4,80010468 <__udivdi3+0x68> +80010454: 00d797b3 sll a5,a5,a3 +80010458: 00e8d733 srl a4,a7,a4 +8001045c: 00d61833 sll a6,a2,a3 +80010460: 00f765b3 or a1,a4,a5 +80010464: 00d89333 sll t1,a7,a3 +80010468: 01085893 srli a7,a6,0x10 +8001046c: 0315d7b3 divu a5,a1,a7 +80010470: 01081613 slli a2,a6,0x10 +80010474: 01065613 srli a2,a2,0x10 +80010478: 01035713 srli a4,t1,0x10 +8001047c: 0315f6b3 remu a3,a1,a7 +80010480: 00078513 mv a0,a5 +80010484: 02f605b3 mul a1,a2,a5 +80010488: 01069693 slli a3,a3,0x10 +8001048c: 00e6e733 or a4,a3,a4 +80010490: 00b77e63 bgeu a4,a1,800104ac <__udivdi3+0xac> +80010494: 01070733 add a4,a4,a6 +80010498: fff78513 addi a0,a5,-1 +8001049c: 01076863 bltu a4,a6,800104ac <__udivdi3+0xac> +800104a0: 00b77663 bgeu a4,a1,800104ac <__udivdi3+0xac> +800104a4: ffe78513 addi a0,a5,-2 +800104a8: 01070733 add a4,a4,a6 +800104ac: 40b70733 sub a4,a4,a1 +800104b0: 031777b3 remu a5,a4,a7 +800104b4: 01031313 slli t1,t1,0x10 +800104b8: 01035313 srli t1,t1,0x10 +800104bc: 03175733 divu a4,a4,a7 +800104c0: 01079793 slli a5,a5,0x10 +800104c4: 0067e333 or t1,a5,t1 +800104c8: 02e606b3 mul a3,a2,a4 +800104cc: 00070613 mv a2,a4 +800104d0: 00d37c63 bgeu t1,a3,800104e8 <__udivdi3+0xe8> +800104d4: 00680333 add t1,a6,t1 +800104d8: fff70613 addi a2,a4,-1 # ffff <_start-0x7fff0001> +800104dc: 01036663 bltu t1,a6,800104e8 <__udivdi3+0xe8> +800104e0: 00d37463 bgeu t1,a3,800104e8 <__udivdi3+0xe8> +800104e4: ffe70613 addi a2,a4,-2 +800104e8: 01051513 slli a0,a0,0x10 +800104ec: 00c56533 or a0,a0,a2 +800104f0: 00000593 li a1,0 +800104f4: 0e40006f j 800105d8 <__udivdi3+0x1d8> +800104f8: 01000537 lui a0,0x1000 +800104fc: 01000713 li a4,16 +80010500: f2a66ce3 bltu a2,a0,80010438 <__udivdi3+0x38> +80010504: 01800713 li a4,24 +80010508: f31ff06f j 80010438 <__udivdi3+0x38> +8001050c: 00061663 bnez a2,80010518 <__udivdi3+0x118> +80010510: 00100713 li a4,1 +80010514: 02c75833 divu a6,a4,a2 +80010518: 00010737 lui a4,0x10 +8001051c: 0ce87063 bgeu a6,a4,800105dc <__udivdi3+0x1dc> +80010520: 0ff00713 li a4,255 +80010524: 01077463 bgeu a4,a6,8001052c <__udivdi3+0x12c> +80010528: 00800513 li a0,8 +8001052c: 00a85733 srl a4,a6,a0 +80010530: 00e686b3 add a3,a3,a4 +80010534: 0006c703 lbu a4,0(a3) +80010538: 02000613 li a2,32 +8001053c: 00a70733 add a4,a4,a0 +80010540: 40e606b3 sub a3,a2,a4 +80010544: 0ae61663 bne a2,a4,800105f0 <__udivdi3+0x1f0> +80010548: 410787b3 sub a5,a5,a6 +8001054c: 00100593 li a1,1 +80010550: 01085893 srli a7,a6,0x10 +80010554: 01081613 slli a2,a6,0x10 +80010558: 01065613 srli a2,a2,0x10 +8001055c: 01035713 srli a4,t1,0x10 +80010560: 0317f6b3 remu a3,a5,a7 +80010564: 0317d7b3 divu a5,a5,a7 +80010568: 01069693 slli a3,a3,0x10 +8001056c: 00e6e733 or a4,a3,a4 +80010570: 02f60e33 mul t3,a2,a5 +80010574: 00078513 mv a0,a5 +80010578: 01c77e63 bgeu a4,t3,80010594 <__udivdi3+0x194> +8001057c: 01070733 add a4,a4,a6 +80010580: fff78513 addi a0,a5,-1 +80010584: 01076863 bltu a4,a6,80010594 <__udivdi3+0x194> +80010588: 01c77663 bgeu a4,t3,80010594 <__udivdi3+0x194> +8001058c: ffe78513 addi a0,a5,-2 +80010590: 01070733 add a4,a4,a6 +80010594: 41c70733 sub a4,a4,t3 +80010598: 031777b3 remu a5,a4,a7 +8001059c: 01031313 slli t1,t1,0x10 +800105a0: 01035313 srli t1,t1,0x10 +800105a4: 03175733 divu a4,a4,a7 +800105a8: 01079793 slli a5,a5,0x10 +800105ac: 0067e333 or t1,a5,t1 +800105b0: 02e606b3 mul a3,a2,a4 +800105b4: 00070613 mv a2,a4 +800105b8: 00d37c63 bgeu t1,a3,800105d0 <__udivdi3+0x1d0> +800105bc: 00680333 add t1,a6,t1 +800105c0: fff70613 addi a2,a4,-1 # ffff <_start-0x7fff0001> +800105c4: 01036663 bltu t1,a6,800105d0 <__udivdi3+0x1d0> +800105c8: 00d37463 bgeu t1,a3,800105d0 <__udivdi3+0x1d0> +800105cc: ffe70613 addi a2,a4,-2 +800105d0: 01051513 slli a0,a0,0x10 +800105d4: 00c56533 or a0,a0,a2 +800105d8: 00008067 ret +800105dc: 01000737 lui a4,0x1000 +800105e0: 01000513 li a0,16 +800105e4: f4e864e3 bltu a6,a4,8001052c <__udivdi3+0x12c> +800105e8: 01800513 li a0,24 +800105ec: f41ff06f j 8001052c <__udivdi3+0x12c> +800105f0: 00d81833 sll a6,a6,a3 +800105f4: 00e7d5b3 srl a1,a5,a4 +800105f8: 00d89333 sll t1,a7,a3 +800105fc: 00d797b3 sll a5,a5,a3 +80010600: 00e8d733 srl a4,a7,a4 +80010604: 01085893 srli a7,a6,0x10 +80010608: 00f76633 or a2,a4,a5 +8001060c: 0315f733 remu a4,a1,a7 +80010610: 01081793 slli a5,a6,0x10 +80010614: 0107d793 srli a5,a5,0x10 +80010618: 01065513 srli a0,a2,0x10 +8001061c: 0315d5b3 divu a1,a1,a7 +80010620: 01071713 slli a4,a4,0x10 +80010624: 00a76733 or a4,a4,a0 +80010628: 02b786b3 mul a3,a5,a1 +8001062c: 00058513 mv a0,a1 +80010630: 00d77e63 bgeu a4,a3,8001064c <__udivdi3+0x24c> +80010634: 01070733 add a4,a4,a6 +80010638: fff58513 addi a0,a1,-1 +8001063c: 01076863 bltu a4,a6,8001064c <__udivdi3+0x24c> +80010640: 00d77663 bgeu a4,a3,8001064c <__udivdi3+0x24c> +80010644: ffe58513 addi a0,a1,-2 +80010648: 01070733 add a4,a4,a6 +8001064c: 40d706b3 sub a3,a4,a3 +80010650: 0316f733 remu a4,a3,a7 +80010654: 01061613 slli a2,a2,0x10 +80010658: 01065613 srli a2,a2,0x10 +8001065c: 0316d6b3 divu a3,a3,a7 +80010660: 01071713 slli a4,a4,0x10 +80010664: 02d788b3 mul a7,a5,a3 +80010668: 00c767b3 or a5,a4,a2 +8001066c: 00068713 mv a4,a3 +80010670: 0117fe63 bgeu a5,a7,8001068c <__udivdi3+0x28c> +80010674: 010787b3 add a5,a5,a6 +80010678: fff68713 addi a4,a3,-1 +8001067c: 0107e863 bltu a5,a6,8001068c <__udivdi3+0x28c> +80010680: 0117f663 bgeu a5,a7,8001068c <__udivdi3+0x28c> +80010684: ffe68713 addi a4,a3,-2 +80010688: 010787b3 add a5,a5,a6 +8001068c: 01051593 slli a1,a0,0x10 +80010690: 411787b3 sub a5,a5,a7 +80010694: 00e5e5b3 or a1,a1,a4 +80010698: eb9ff06f j 80010550 <__udivdi3+0x150> +8001069c: 18d5e663 bltu a1,a3,80010828 <__udivdi3+0x428> +800106a0: 00010737 lui a4,0x10 +800106a4: 04e6f463 bgeu a3,a4,800106ec <__udivdi3+0x2ec> +800106a8: 0ff00713 li a4,255 +800106ac: 00d735b3 sltu a1,a4,a3 +800106b0: 00359593 slli a1,a1,0x3 +800106b4: 80015737 lui a4,0x80015 +800106b8: 00b6d533 srl a0,a3,a1 +800106bc: 77470713 addi a4,a4,1908 # 80015774 <__BSS_END__+0xffffeb38> +800106c0: 00a70733 add a4,a4,a0 +800106c4: 00074703 lbu a4,0(a4) +800106c8: 02000513 li a0,32 +800106cc: 00b70733 add a4,a4,a1 +800106d0: 40e505b3 sub a1,a0,a4 +800106d4: 02e51663 bne a0,a4,80010700 <__udivdi3+0x300> +800106d8: 00100513 li a0,1 +800106dc: eef6eee3 bltu a3,a5,800105d8 <__udivdi3+0x1d8> +800106e0: 00c8b533 sltu a0,a7,a2 +800106e4: 00154513 xori a0,a0,1 +800106e8: ef1ff06f j 800105d8 <__udivdi3+0x1d8> +800106ec: 01000737 lui a4,0x1000 +800106f0: 01000593 li a1,16 +800106f4: fce6e0e3 bltu a3,a4,800106b4 <__udivdi3+0x2b4> +800106f8: 01800593 li a1,24 +800106fc: fb9ff06f j 800106b4 <__udivdi3+0x2b4> +80010700: 00e65333 srl t1,a2,a4 +80010704: 00b696b3 sll a3,a3,a1 +80010708: 00d36333 or t1,t1,a3 +8001070c: 01035513 srli a0,t1,0x10 +80010710: 00b61eb3 sll t4,a2,a1 +80010714: 00e7d633 srl a2,a5,a4 +80010718: 02a676b3 remu a3,a2,a0 +8001071c: 00b797b3 sll a5,a5,a1 +80010720: 00e8d733 srl a4,a7,a4 +80010724: 00f76833 or a6,a4,a5 +80010728: 01031793 slli a5,t1,0x10 +8001072c: 0107d793 srli a5,a5,0x10 +80010730: 01085713 srli a4,a6,0x10 +80010734: 02a65633 divu a2,a2,a0 +80010738: 01069693 slli a3,a3,0x10 +8001073c: 00e6e733 or a4,a3,a4 +80010740: 02c78f33 mul t5,a5,a2 +80010744: 00060e13 mv t3,a2 +80010748: 01e77e63 bgeu a4,t5,80010764 <__udivdi3+0x364> +8001074c: 00670733 add a4,a4,t1 +80010750: fff60e13 addi t3,a2,-1 +80010754: 00676863 bltu a4,t1,80010764 <__udivdi3+0x364> +80010758: 01e77663 bgeu a4,t5,80010764 <__udivdi3+0x364> +8001075c: ffe60e13 addi t3,a2,-2 +80010760: 00670733 add a4,a4,t1 +80010764: 41e70733 sub a4,a4,t5 +80010768: 02a776b3 remu a3,a4,a0 +8001076c: 02a75733 divu a4,a4,a0 +80010770: 01069693 slli a3,a3,0x10 +80010774: 02e78633 mul a2,a5,a4 +80010778: 01081793 slli a5,a6,0x10 +8001077c: 0107d793 srli a5,a5,0x10 +80010780: 00f6e7b3 or a5,a3,a5 +80010784: 00070693 mv a3,a4 +80010788: 00c7fe63 bgeu a5,a2,800107a4 <__udivdi3+0x3a4> +8001078c: 006787b3 add a5,a5,t1 +80010790: fff70693 addi a3,a4,-1 # ffffff <_start-0x7f000001> +80010794: 0067e863 bltu a5,t1,800107a4 <__udivdi3+0x3a4> +80010798: 00c7f663 bgeu a5,a2,800107a4 <__udivdi3+0x3a4> +8001079c: ffe70693 addi a3,a4,-2 +800107a0: 006787b3 add a5,a5,t1 +800107a4: 010e1513 slli a0,t3,0x10 +800107a8: 00010e37 lui t3,0x10 +800107ac: 00d56533 or a0,a0,a3 +800107b0: fffe0693 addi a3,t3,-1 # ffff <_start-0x7fff0001> +800107b4: 00d57833 and a6,a0,a3 +800107b8: 40c787b3 sub a5,a5,a2 +800107bc: 00def6b3 and a3,t4,a3 +800107c0: 01055613 srli a2,a0,0x10 +800107c4: 010ede93 srli t4,t4,0x10 +800107c8: 02d80333 mul t1,a6,a3 +800107cc: 02d606b3 mul a3,a2,a3 +800107d0: 01035713 srli a4,t1,0x10 +800107d4: 03d80833 mul a6,a6,t4 +800107d8: 00d80833 add a6,a6,a3 +800107dc: 01070733 add a4,a4,a6 +800107e0: 03d60633 mul a2,a2,t4 +800107e4: 00d77463 bgeu a4,a3,800107ec <__udivdi3+0x3ec> +800107e8: 01c60633 add a2,a2,t3 +800107ec: 01075693 srli a3,a4,0x10 +800107f0: 00c68633 add a2,a3,a2 +800107f4: 02c7e663 bltu a5,a2,80010820 <__udivdi3+0x420> +800107f8: cec79ce3 bne a5,a2,800104f0 <__udivdi3+0xf0> +800107fc: 000107b7 lui a5,0x10 +80010800: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +80010804: 00f77733 and a4,a4,a5 +80010808: 01071713 slli a4,a4,0x10 +8001080c: 00f37333 and t1,t1,a5 +80010810: 00b898b3 sll a7,a7,a1 +80010814: 00670733 add a4,a4,t1 +80010818: 00000593 li a1,0 +8001081c: dae8fee3 bgeu a7,a4,800105d8 <__udivdi3+0x1d8> +80010820: fff50513 addi a0,a0,-1 # ffffff <_start-0x7f000001> +80010824: ccdff06f j 800104f0 <__udivdi3+0xf0> +80010828: 00000593 li a1,0 +8001082c: 00000513 li a0,0 +80010830: da9ff06f j 800105d8 <__udivdi3+0x1d8> -8001048c <_wctomb_r>: -8001048c: 2a81a303 lw t1,680(gp) # 80016ab0 <__global_locale+0xe0> -80010490: 00030067 jr t1 - -80010494 <__ascii_wctomb>: -80010494: 02058463 beqz a1,800104bc <__ascii_wctomb+0x28> -80010498: 0ff00793 li a5,255 -8001049c: 00c7e863 bltu a5,a2,800104ac <__ascii_wctomb+0x18> -800104a0: 00c58023 sb a2,0(a1) -800104a4: 00100513 li a0,1 -800104a8: 00008067 ret -800104ac: 08a00793 li a5,138 -800104b0: 00f52023 sw a5,0(a0) -800104b4: fff00513 li a0,-1 -800104b8: 00008067 ret -800104bc: 00000513 li a0,0 -800104c0: 00008067 ret - -800104c4 <__udivdi3>: -800104c4: 00050893 mv a7,a0 -800104c8: 00058793 mv a5,a1 -800104cc: 00060813 mv a6,a2 -800104d0: 00068513 mv a0,a3 -800104d4: 00088313 mv t1,a7 -800104d8: 28069463 bnez a3,80010760 <__udivdi3+0x29c> -800104dc: 800166b7 lui a3,0x80016 -800104e0: 84c68693 addi a3,a3,-1972 # 8001584c <__BSS_END__+0xffffec10> -800104e4: 0ec5f663 bgeu a1,a2,800105d0 <__udivdi3+0x10c> -800104e8: 00010737 lui a4,0x10 -800104ec: 0ce67863 bgeu a2,a4,800105bc <__udivdi3+0xf8> -800104f0: 0ff00713 li a4,255 -800104f4: 00c73733 sltu a4,a4,a2 -800104f8: 00371713 slli a4,a4,0x3 -800104fc: 00e65533 srl a0,a2,a4 -80010500: 00a686b3 add a3,a3,a0 -80010504: 0006c683 lbu a3,0(a3) -80010508: 02000513 li a0,32 -8001050c: 00e68733 add a4,a3,a4 -80010510: 40e506b3 sub a3,a0,a4 -80010514: 00e50c63 beq a0,a4,8001052c <__udivdi3+0x68> -80010518: 00d797b3 sll a5,a5,a3 -8001051c: 00e8d733 srl a4,a7,a4 -80010520: 00d61833 sll a6,a2,a3 -80010524: 00f765b3 or a1,a4,a5 -80010528: 00d89333 sll t1,a7,a3 -8001052c: 01085893 srli a7,a6,0x10 -80010530: 0315d7b3 divu a5,a1,a7 -80010534: 01081613 slli a2,a6,0x10 -80010538: 01065613 srli a2,a2,0x10 -8001053c: 01035713 srli a4,t1,0x10 -80010540: 0315f6b3 remu a3,a1,a7 -80010544: 00078513 mv a0,a5 -80010548: 02f605b3 mul a1,a2,a5 -8001054c: 01069693 slli a3,a3,0x10 -80010550: 00e6e733 or a4,a3,a4 -80010554: 00b77e63 bgeu a4,a1,80010570 <__udivdi3+0xac> -80010558: 01070733 add a4,a4,a6 -8001055c: fff78513 addi a0,a5,-1 -80010560: 01076863 bltu a4,a6,80010570 <__udivdi3+0xac> -80010564: 00b77663 bgeu a4,a1,80010570 <__udivdi3+0xac> -80010568: ffe78513 addi a0,a5,-2 -8001056c: 01070733 add a4,a4,a6 -80010570: 40b70733 sub a4,a4,a1 -80010574: 031777b3 remu a5,a4,a7 -80010578: 01031313 slli t1,t1,0x10 -8001057c: 01035313 srli t1,t1,0x10 -80010580: 03175733 divu a4,a4,a7 -80010584: 01079793 slli a5,a5,0x10 -80010588: 0067e333 or t1,a5,t1 -8001058c: 02e606b3 mul a3,a2,a4 -80010590: 00070613 mv a2,a4 -80010594: 00d37c63 bgeu t1,a3,800105ac <__udivdi3+0xe8> -80010598: 00680333 add t1,a6,t1 -8001059c: fff70613 addi a2,a4,-1 # ffff <_start-0x7fff0001> -800105a0: 01036663 bltu t1,a6,800105ac <__udivdi3+0xe8> -800105a4: 00d37463 bgeu t1,a3,800105ac <__udivdi3+0xe8> -800105a8: ffe70613 addi a2,a4,-2 -800105ac: 01051513 slli a0,a0,0x10 -800105b0: 00c56533 or a0,a0,a2 -800105b4: 00000593 li a1,0 -800105b8: 0e40006f j 8001069c <__udivdi3+0x1d8> -800105bc: 01000537 lui a0,0x1000 -800105c0: 01000713 li a4,16 -800105c4: f2a66ce3 bltu a2,a0,800104fc <__udivdi3+0x38> -800105c8: 01800713 li a4,24 -800105cc: f31ff06f j 800104fc <__udivdi3+0x38> -800105d0: 00061663 bnez a2,800105dc <__udivdi3+0x118> -800105d4: 00100713 li a4,1 -800105d8: 02c75833 divu a6,a4,a2 -800105dc: 00010737 lui a4,0x10 -800105e0: 0ce87063 bgeu a6,a4,800106a0 <__udivdi3+0x1dc> -800105e4: 0ff00713 li a4,255 -800105e8: 01077463 bgeu a4,a6,800105f0 <__udivdi3+0x12c> -800105ec: 00800513 li a0,8 -800105f0: 00a85733 srl a4,a6,a0 -800105f4: 00e686b3 add a3,a3,a4 -800105f8: 0006c703 lbu a4,0(a3) -800105fc: 02000613 li a2,32 -80010600: 00a70733 add a4,a4,a0 -80010604: 40e606b3 sub a3,a2,a4 -80010608: 0ae61663 bne a2,a4,800106b4 <__udivdi3+0x1f0> -8001060c: 410787b3 sub a5,a5,a6 -80010610: 00100593 li a1,1 -80010614: 01085893 srli a7,a6,0x10 -80010618: 01081613 slli a2,a6,0x10 -8001061c: 01065613 srli a2,a2,0x10 -80010620: 01035713 srli a4,t1,0x10 -80010624: 0317f6b3 remu a3,a5,a7 -80010628: 0317d7b3 divu a5,a5,a7 -8001062c: 01069693 slli a3,a3,0x10 -80010630: 00e6e733 or a4,a3,a4 -80010634: 02f60e33 mul t3,a2,a5 -80010638: 00078513 mv a0,a5 -8001063c: 01c77e63 bgeu a4,t3,80010658 <__udivdi3+0x194> -80010640: 01070733 add a4,a4,a6 -80010644: fff78513 addi a0,a5,-1 -80010648: 01076863 bltu a4,a6,80010658 <__udivdi3+0x194> -8001064c: 01c77663 bgeu a4,t3,80010658 <__udivdi3+0x194> -80010650: ffe78513 addi a0,a5,-2 -80010654: 01070733 add a4,a4,a6 -80010658: 41c70733 sub a4,a4,t3 -8001065c: 031777b3 remu a5,a4,a7 -80010660: 01031313 slli t1,t1,0x10 -80010664: 01035313 srli t1,t1,0x10 -80010668: 03175733 divu a4,a4,a7 -8001066c: 01079793 slli a5,a5,0x10 -80010670: 0067e333 or t1,a5,t1 -80010674: 02e606b3 mul a3,a2,a4 -80010678: 00070613 mv a2,a4 -8001067c: 00d37c63 bgeu t1,a3,80010694 <__udivdi3+0x1d0> -80010680: 00680333 add t1,a6,t1 -80010684: fff70613 addi a2,a4,-1 # ffff <_start-0x7fff0001> -80010688: 01036663 bltu t1,a6,80010694 <__udivdi3+0x1d0> -8001068c: 00d37463 bgeu t1,a3,80010694 <__udivdi3+0x1d0> -80010690: ffe70613 addi a2,a4,-2 -80010694: 01051513 slli a0,a0,0x10 -80010698: 00c56533 or a0,a0,a2 -8001069c: 00008067 ret -800106a0: 01000737 lui a4,0x1000 -800106a4: 01000513 li a0,16 -800106a8: f4e864e3 bltu a6,a4,800105f0 <__udivdi3+0x12c> -800106ac: 01800513 li a0,24 -800106b0: f41ff06f j 800105f0 <__udivdi3+0x12c> -800106b4: 00d81833 sll a6,a6,a3 -800106b8: 00e7d5b3 srl a1,a5,a4 -800106bc: 00d89333 sll t1,a7,a3 -800106c0: 00d797b3 sll a5,a5,a3 -800106c4: 00e8d733 srl a4,a7,a4 -800106c8: 01085893 srli a7,a6,0x10 -800106cc: 00f76633 or a2,a4,a5 -800106d0: 0315f733 remu a4,a1,a7 -800106d4: 01081793 slli a5,a6,0x10 -800106d8: 0107d793 srli a5,a5,0x10 -800106dc: 01065513 srli a0,a2,0x10 -800106e0: 0315d5b3 divu a1,a1,a7 -800106e4: 01071713 slli a4,a4,0x10 -800106e8: 00a76733 or a4,a4,a0 -800106ec: 02b786b3 mul a3,a5,a1 -800106f0: 00058513 mv a0,a1 -800106f4: 00d77e63 bgeu a4,a3,80010710 <__udivdi3+0x24c> -800106f8: 01070733 add a4,a4,a6 -800106fc: fff58513 addi a0,a1,-1 -80010700: 01076863 bltu a4,a6,80010710 <__udivdi3+0x24c> -80010704: 00d77663 bgeu a4,a3,80010710 <__udivdi3+0x24c> -80010708: ffe58513 addi a0,a1,-2 -8001070c: 01070733 add a4,a4,a6 -80010710: 40d706b3 sub a3,a4,a3 -80010714: 0316f733 remu a4,a3,a7 -80010718: 01061613 slli a2,a2,0x10 -8001071c: 01065613 srli a2,a2,0x10 -80010720: 0316d6b3 divu a3,a3,a7 -80010724: 01071713 slli a4,a4,0x10 -80010728: 02d788b3 mul a7,a5,a3 -8001072c: 00c767b3 or a5,a4,a2 -80010730: 00068713 mv a4,a3 -80010734: 0117fe63 bgeu a5,a7,80010750 <__udivdi3+0x28c> -80010738: 010787b3 add a5,a5,a6 -8001073c: fff68713 addi a4,a3,-1 -80010740: 0107e863 bltu a5,a6,80010750 <__udivdi3+0x28c> -80010744: 0117f663 bgeu a5,a7,80010750 <__udivdi3+0x28c> -80010748: ffe68713 addi a4,a3,-2 -8001074c: 010787b3 add a5,a5,a6 -80010750: 01051593 slli a1,a0,0x10 -80010754: 411787b3 sub a5,a5,a7 -80010758: 00e5e5b3 or a1,a1,a4 -8001075c: eb9ff06f j 80010614 <__udivdi3+0x150> -80010760: 18d5e663 bltu a1,a3,800108ec <__udivdi3+0x428> -80010764: 00010737 lui a4,0x10 -80010768: 04e6f463 bgeu a3,a4,800107b0 <__udivdi3+0x2ec> -8001076c: 0ff00713 li a4,255 -80010770: 00d735b3 sltu a1,a4,a3 -80010774: 00359593 slli a1,a1,0x3 -80010778: 80016737 lui a4,0x80016 -8001077c: 00b6d533 srl a0,a3,a1 -80010780: 84c70713 addi a4,a4,-1972 # 8001584c <__BSS_END__+0xffffec10> -80010784: 00a70733 add a4,a4,a0 -80010788: 00074703 lbu a4,0(a4) -8001078c: 02000513 li a0,32 -80010790: 00b70733 add a4,a4,a1 -80010794: 40e505b3 sub a1,a0,a4 -80010798: 02e51663 bne a0,a4,800107c4 <__udivdi3+0x300> -8001079c: 00100513 li a0,1 -800107a0: eef6eee3 bltu a3,a5,8001069c <__udivdi3+0x1d8> -800107a4: 00c8b533 sltu a0,a7,a2 -800107a8: 00154513 xori a0,a0,1 -800107ac: ef1ff06f j 8001069c <__udivdi3+0x1d8> -800107b0: 01000737 lui a4,0x1000 -800107b4: 01000593 li a1,16 -800107b8: fce6e0e3 bltu a3,a4,80010778 <__udivdi3+0x2b4> -800107bc: 01800593 li a1,24 -800107c0: fb9ff06f j 80010778 <__udivdi3+0x2b4> -800107c4: 00e65333 srl t1,a2,a4 -800107c8: 00b696b3 sll a3,a3,a1 -800107cc: 00d36333 or t1,t1,a3 -800107d0: 01035513 srli a0,t1,0x10 -800107d4: 00b61eb3 sll t4,a2,a1 -800107d8: 00e7d633 srl a2,a5,a4 -800107dc: 02a676b3 remu a3,a2,a0 -800107e0: 00b797b3 sll a5,a5,a1 -800107e4: 00e8d733 srl a4,a7,a4 -800107e8: 00f76833 or a6,a4,a5 -800107ec: 01031793 slli a5,t1,0x10 -800107f0: 0107d793 srli a5,a5,0x10 -800107f4: 01085713 srli a4,a6,0x10 -800107f8: 02a65633 divu a2,a2,a0 -800107fc: 01069693 slli a3,a3,0x10 -80010800: 00e6e733 or a4,a3,a4 -80010804: 02c78f33 mul t5,a5,a2 -80010808: 00060e13 mv t3,a2 -8001080c: 01e77e63 bgeu a4,t5,80010828 <__udivdi3+0x364> -80010810: 00670733 add a4,a4,t1 -80010814: fff60e13 addi t3,a2,-1 -80010818: 00676863 bltu a4,t1,80010828 <__udivdi3+0x364> -8001081c: 01e77663 bgeu a4,t5,80010828 <__udivdi3+0x364> -80010820: ffe60e13 addi t3,a2,-2 -80010824: 00670733 add a4,a4,t1 -80010828: 41e70733 sub a4,a4,t5 -8001082c: 02a776b3 remu a3,a4,a0 -80010830: 02a75733 divu a4,a4,a0 -80010834: 01069693 slli a3,a3,0x10 -80010838: 02e78633 mul a2,a5,a4 -8001083c: 01081793 slli a5,a6,0x10 -80010840: 0107d793 srli a5,a5,0x10 -80010844: 00f6e7b3 or a5,a3,a5 -80010848: 00070693 mv a3,a4 -8001084c: 00c7fe63 bgeu a5,a2,80010868 <__udivdi3+0x3a4> -80010850: 006787b3 add a5,a5,t1 -80010854: fff70693 addi a3,a4,-1 # ffffff <_start-0x7f000001> -80010858: 0067e863 bltu a5,t1,80010868 <__udivdi3+0x3a4> -8001085c: 00c7f663 bgeu a5,a2,80010868 <__udivdi3+0x3a4> -80010860: ffe70693 addi a3,a4,-2 -80010864: 006787b3 add a5,a5,t1 -80010868: 010e1513 slli a0,t3,0x10 -8001086c: 00010e37 lui t3,0x10 -80010870: 00d56533 or a0,a0,a3 -80010874: fffe0693 addi a3,t3,-1 # ffff <_start-0x7fff0001> -80010878: 00d57833 and a6,a0,a3 -8001087c: 40c787b3 sub a5,a5,a2 -80010880: 00def6b3 and a3,t4,a3 -80010884: 01055613 srli a2,a0,0x10 -80010888: 010ede93 srli t4,t4,0x10 -8001088c: 02d80333 mul t1,a6,a3 -80010890: 02d606b3 mul a3,a2,a3 -80010894: 01035713 srli a4,t1,0x10 -80010898: 03d80833 mul a6,a6,t4 -8001089c: 00d80833 add a6,a6,a3 -800108a0: 01070733 add a4,a4,a6 -800108a4: 03d60633 mul a2,a2,t4 -800108a8: 00d77463 bgeu a4,a3,800108b0 <__udivdi3+0x3ec> -800108ac: 01c60633 add a2,a2,t3 -800108b0: 01075693 srli a3,a4,0x10 -800108b4: 00c68633 add a2,a3,a2 -800108b8: 02c7e663 bltu a5,a2,800108e4 <__udivdi3+0x420> -800108bc: cec79ce3 bne a5,a2,800105b4 <__udivdi3+0xf0> -800108c0: 000107b7 lui a5,0x10 -800108c4: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -800108c8: 00f77733 and a4,a4,a5 -800108cc: 01071713 slli a4,a4,0x10 -800108d0: 00f37333 and t1,t1,a5 -800108d4: 00b898b3 sll a7,a7,a1 -800108d8: 00670733 add a4,a4,t1 -800108dc: 00000593 li a1,0 -800108e0: dae8fee3 bgeu a7,a4,8001069c <__udivdi3+0x1d8> -800108e4: fff50513 addi a0,a0,-1 # ffffff <_start-0x7f000001> -800108e8: ccdff06f j 800105b4 <__udivdi3+0xf0> -800108ec: 00000593 li a1,0 -800108f0: 00000513 li a0,0 -800108f4: da9ff06f j 8001069c <__udivdi3+0x1d8> - -800108f8 <__umoddi3>: -800108f8: 00060893 mv a7,a2 -800108fc: 00068713 mv a4,a3 -80010900: 00050793 mv a5,a0 -80010904: 00058813 mv a6,a1 -80010908: 22069c63 bnez a3,80010b40 <__umoddi3+0x248> -8001090c: 800166b7 lui a3,0x80016 -80010910: 84c68693 addi a3,a3,-1972 # 8001584c <__BSS_END__+0xffffec10> -80010914: 0cc5fc63 bgeu a1,a2,800109ec <__umoddi3+0xf4> -80010918: 00010337 lui t1,0x10 -8001091c: 0a667e63 bgeu a2,t1,800109d8 <__umoddi3+0xe0> -80010920: 0ff00313 li t1,255 -80010924: 00c37463 bgeu t1,a2,8001092c <__umoddi3+0x34> -80010928: 00800713 li a4,8 -8001092c: 00e65333 srl t1,a2,a4 -80010930: 006686b3 add a3,a3,t1 -80010934: 0006ce03 lbu t3,0(a3) -80010938: 00ee0e33 add t3,t3,a4 -8001093c: 02000713 li a4,32 -80010940: 41c70333 sub t1,a4,t3 -80010944: 01c70c63 beq a4,t3,8001095c <__umoddi3+0x64> -80010948: 006595b3 sll a1,a1,t1 -8001094c: 01c55e33 srl t3,a0,t3 -80010950: 006618b3 sll a7,a2,t1 -80010954: 00be6833 or a6,t3,a1 -80010958: 006517b3 sll a5,a0,t1 -8001095c: 0108d613 srli a2,a7,0x10 -80010960: 02c87733 remu a4,a6,a2 -80010964: 01089513 slli a0,a7,0x10 -80010968: 01055513 srli a0,a0,0x10 -8001096c: 0107d693 srli a3,a5,0x10 -80010970: 02c85833 divu a6,a6,a2 -80010974: 01071713 slli a4,a4,0x10 -80010978: 00d766b3 or a3,a4,a3 -8001097c: 03050833 mul a6,a0,a6 -80010980: 0106fa63 bgeu a3,a6,80010994 <__umoddi3+0x9c> -80010984: 011686b3 add a3,a3,a7 -80010988: 0116e663 bltu a3,a7,80010994 <__umoddi3+0x9c> -8001098c: 0106f463 bgeu a3,a6,80010994 <__umoddi3+0x9c> +80010834 <__umoddi3>: +80010834: 00060893 mv a7,a2 +80010838: 00068713 mv a4,a3 +8001083c: 00050793 mv a5,a0 +80010840: 00058813 mv a6,a1 +80010844: 22069c63 bnez a3,80010a7c <__umoddi3+0x248> +80010848: 800156b7 lui a3,0x80015 +8001084c: 77468693 addi a3,a3,1908 # 80015774 <__BSS_END__+0xffffeb38> +80010850: 0cc5fc63 bgeu a1,a2,80010928 <__umoddi3+0xf4> +80010854: 00010337 lui t1,0x10 +80010858: 0a667e63 bgeu a2,t1,80010914 <__umoddi3+0xe0> +8001085c: 0ff00313 li t1,255 +80010860: 00c37463 bgeu t1,a2,80010868 <__umoddi3+0x34> +80010864: 00800713 li a4,8 +80010868: 00e65333 srl t1,a2,a4 +8001086c: 006686b3 add a3,a3,t1 +80010870: 0006ce03 lbu t3,0(a3) +80010874: 00ee0e33 add t3,t3,a4 +80010878: 02000713 li a4,32 +8001087c: 41c70333 sub t1,a4,t3 +80010880: 01c70c63 beq a4,t3,80010898 <__umoddi3+0x64> +80010884: 006595b3 sll a1,a1,t1 +80010888: 01c55e33 srl t3,a0,t3 +8001088c: 006618b3 sll a7,a2,t1 +80010890: 00be6833 or a6,t3,a1 +80010894: 006517b3 sll a5,a0,t1 +80010898: 0108d613 srli a2,a7,0x10 +8001089c: 02c87733 remu a4,a6,a2 +800108a0: 01089513 slli a0,a7,0x10 +800108a4: 01055513 srli a0,a0,0x10 +800108a8: 0107d693 srli a3,a5,0x10 +800108ac: 02c85833 divu a6,a6,a2 +800108b0: 01071713 slli a4,a4,0x10 +800108b4: 00d766b3 or a3,a4,a3 +800108b8: 03050833 mul a6,a0,a6 +800108bc: 0106fa63 bgeu a3,a6,800108d0 <__umoddi3+0x9c> +800108c0: 011686b3 add a3,a3,a7 +800108c4: 0116e663 bltu a3,a7,800108d0 <__umoddi3+0x9c> +800108c8: 0106f463 bgeu a3,a6,800108d0 <__umoddi3+0x9c> +800108cc: 011686b3 add a3,a3,a7 +800108d0: 410686b3 sub a3,a3,a6 +800108d4: 02c6f733 remu a4,a3,a2 +800108d8: 01079793 slli a5,a5,0x10 +800108dc: 0107d793 srli a5,a5,0x10 +800108e0: 02c6d6b3 divu a3,a3,a2 +800108e4: 02d506b3 mul a3,a0,a3 +800108e8: 01071513 slli a0,a4,0x10 +800108ec: 00f567b3 or a5,a0,a5 +800108f0: 00d7fa63 bgeu a5,a3,80010904 <__umoddi3+0xd0> +800108f4: 011787b3 add a5,a5,a7 +800108f8: 0117e663 bltu a5,a7,80010904 <__umoddi3+0xd0> +800108fc: 00d7f463 bgeu a5,a3,80010904 <__umoddi3+0xd0> +80010900: 011787b3 add a5,a5,a7 +80010904: 40d787b3 sub a5,a5,a3 +80010908: 0067d533 srl a0,a5,t1 +8001090c: 00000593 li a1,0 +80010910: 00008067 ret +80010914: 01000337 lui t1,0x1000 +80010918: 01000713 li a4,16 +8001091c: f46666e3 bltu a2,t1,80010868 <__umoddi3+0x34> +80010920: 01800713 li a4,24 +80010924: f45ff06f j 80010868 <__umoddi3+0x34> +80010928: 00061663 bnez a2,80010934 <__umoddi3+0x100> +8001092c: 00100613 li a2,1 +80010930: 031658b3 divu a7,a2,a7 +80010934: 00010637 lui a2,0x10 +80010938: 0ac8f263 bgeu a7,a2,800109dc <__umoddi3+0x1a8> +8001093c: 0ff00613 li a2,255 +80010940: 01167463 bgeu a2,a7,80010948 <__umoddi3+0x114> +80010944: 00800713 li a4,8 +80010948: 00e8d633 srl a2,a7,a4 +8001094c: 00c686b3 add a3,a3,a2 +80010950: 0006ce03 lbu t3,0(a3) +80010954: 00ee0e33 add t3,t3,a4 +80010958: 02000713 li a4,32 +8001095c: 41c70333 sub t1,a4,t3 +80010960: 09c71863 bne a4,t3,800109f0 <__umoddi3+0x1bc> +80010964: 411585b3 sub a1,a1,a7 +80010968: 0108d713 srli a4,a7,0x10 +8001096c: 01089513 slli a0,a7,0x10 +80010970: 01055513 srli a0,a0,0x10 +80010974: 0107d613 srli a2,a5,0x10 +80010978: 02e5f6b3 remu a3,a1,a4 +8001097c: 02e5d5b3 divu a1,a1,a4 +80010980: 01069693 slli a3,a3,0x10 +80010984: 00c6e6b3 or a3,a3,a2 +80010988: 02b505b3 mul a1,a0,a1 +8001098c: 00b6fa63 bgeu a3,a1,800109a0 <__umoddi3+0x16c> 80010990: 011686b3 add a3,a3,a7 -80010994: 410686b3 sub a3,a3,a6 -80010998: 02c6f733 remu a4,a3,a2 -8001099c: 01079793 slli a5,a5,0x10 -800109a0: 0107d793 srli a5,a5,0x10 -800109a4: 02c6d6b3 divu a3,a3,a2 -800109a8: 02d506b3 mul a3,a0,a3 -800109ac: 01071513 slli a0,a4,0x10 -800109b0: 00f567b3 or a5,a0,a5 -800109b4: 00d7fa63 bgeu a5,a3,800109c8 <__umoddi3+0xd0> -800109b8: 011787b3 add a5,a5,a7 -800109bc: 0117e663 bltu a5,a7,800109c8 <__umoddi3+0xd0> -800109c0: 00d7f463 bgeu a5,a3,800109c8 <__umoddi3+0xd0> +80010994: 0116e663 bltu a3,a7,800109a0 <__umoddi3+0x16c> +80010998: 00b6f463 bgeu a3,a1,800109a0 <__umoddi3+0x16c> +8001099c: 011686b3 add a3,a3,a7 +800109a0: 40b685b3 sub a1,a3,a1 +800109a4: 02e5f6b3 remu a3,a1,a4 +800109a8: 01079793 slli a5,a5,0x10 +800109ac: 0107d793 srli a5,a5,0x10 +800109b0: 02e5d5b3 divu a1,a1,a4 +800109b4: 02b505b3 mul a1,a0,a1 +800109b8: 01069513 slli a0,a3,0x10 +800109bc: 00f567b3 or a5,a0,a5 +800109c0: 00b7fa63 bgeu a5,a1,800109d4 <__umoddi3+0x1a0> 800109c4: 011787b3 add a5,a5,a7 -800109c8: 40d787b3 sub a5,a5,a3 -800109cc: 0067d533 srl a0,a5,t1 -800109d0: 00000593 li a1,0 -800109d4: 00008067 ret -800109d8: 01000337 lui t1,0x1000 -800109dc: 01000713 li a4,16 -800109e0: f46666e3 bltu a2,t1,8001092c <__umoddi3+0x34> -800109e4: 01800713 li a4,24 -800109e8: f45ff06f j 8001092c <__umoddi3+0x34> -800109ec: 00061663 bnez a2,800109f8 <__umoddi3+0x100> -800109f0: 00100613 li a2,1 -800109f4: 031658b3 divu a7,a2,a7 -800109f8: 00010637 lui a2,0x10 -800109fc: 0ac8f263 bgeu a7,a2,80010aa0 <__umoddi3+0x1a8> -80010a00: 0ff00613 li a2,255 -80010a04: 01167463 bgeu a2,a7,80010a0c <__umoddi3+0x114> -80010a08: 00800713 li a4,8 -80010a0c: 00e8d633 srl a2,a7,a4 -80010a10: 00c686b3 add a3,a3,a2 -80010a14: 0006ce03 lbu t3,0(a3) -80010a18: 00ee0e33 add t3,t3,a4 -80010a1c: 02000713 li a4,32 -80010a20: 41c70333 sub t1,a4,t3 -80010a24: 09c71863 bne a4,t3,80010ab4 <__umoddi3+0x1bc> -80010a28: 411585b3 sub a1,a1,a7 -80010a2c: 0108d713 srli a4,a7,0x10 -80010a30: 01089513 slli a0,a7,0x10 -80010a34: 01055513 srli a0,a0,0x10 -80010a38: 0107d613 srli a2,a5,0x10 -80010a3c: 02e5f6b3 remu a3,a1,a4 -80010a40: 02e5d5b3 divu a1,a1,a4 -80010a44: 01069693 slli a3,a3,0x10 -80010a48: 00c6e6b3 or a3,a3,a2 -80010a4c: 02b505b3 mul a1,a0,a1 -80010a50: 00b6fa63 bgeu a3,a1,80010a64 <__umoddi3+0x16c> -80010a54: 011686b3 add a3,a3,a7 -80010a58: 0116e663 bltu a3,a7,80010a64 <__umoddi3+0x16c> -80010a5c: 00b6f463 bgeu a3,a1,80010a64 <__umoddi3+0x16c> -80010a60: 011686b3 add a3,a3,a7 -80010a64: 40b685b3 sub a1,a3,a1 -80010a68: 02e5f6b3 remu a3,a1,a4 -80010a6c: 01079793 slli a5,a5,0x10 -80010a70: 0107d793 srli a5,a5,0x10 -80010a74: 02e5d5b3 divu a1,a1,a4 -80010a78: 02b505b3 mul a1,a0,a1 -80010a7c: 01069513 slli a0,a3,0x10 -80010a80: 00f567b3 or a5,a0,a5 -80010a84: 00b7fa63 bgeu a5,a1,80010a98 <__umoddi3+0x1a0> -80010a88: 011787b3 add a5,a5,a7 -80010a8c: 0117e663 bltu a5,a7,80010a98 <__umoddi3+0x1a0> -80010a90: 00b7f463 bgeu a5,a1,80010a98 <__umoddi3+0x1a0> -80010a94: 011787b3 add a5,a5,a7 -80010a98: 40b787b3 sub a5,a5,a1 -80010a9c: f31ff06f j 800109cc <__umoddi3+0xd4> -80010aa0: 01000637 lui a2,0x1000 -80010aa4: 01000713 li a4,16 -80010aa8: f6c8e2e3 bltu a7,a2,80010a0c <__umoddi3+0x114> -80010aac: 01800713 li a4,24 -80010ab0: f5dff06f j 80010a0c <__umoddi3+0x114> -80010ab4: 006898b3 sll a7,a7,t1 -80010ab8: 01c5d733 srl a4,a1,t3 -80010abc: 006517b3 sll a5,a0,t1 -80010ac0: 01c55e33 srl t3,a0,t3 -80010ac4: 0108d513 srli a0,a7,0x10 -80010ac8: 02a776b3 remu a3,a4,a0 -80010acc: 006595b3 sll a1,a1,t1 -80010ad0: 00be6e33 or t3,t3,a1 -80010ad4: 01089593 slli a1,a7,0x10 -80010ad8: 0105d593 srli a1,a1,0x10 -80010adc: 010e5613 srli a2,t3,0x10 -80010ae0: 02a75733 divu a4,a4,a0 -80010ae4: 01069693 slli a3,a3,0x10 -80010ae8: 00c6e6b3 or a3,a3,a2 -80010aec: 02e58733 mul a4,a1,a4 -80010af0: 00e6fa63 bgeu a3,a4,80010b04 <__umoddi3+0x20c> -80010af4: 011686b3 add a3,a3,a7 -80010af8: 0116e663 bltu a3,a7,80010b04 <__umoddi3+0x20c> -80010afc: 00e6f463 bgeu a3,a4,80010b04 <__umoddi3+0x20c> -80010b00: 011686b3 add a3,a3,a7 -80010b04: 40e68633 sub a2,a3,a4 -80010b08: 02a676b3 remu a3,a2,a0 -80010b0c: 010e1e13 slli t3,t3,0x10 -80010b10: 010e5e13 srli t3,t3,0x10 -80010b14: 02a65633 divu a2,a2,a0 -80010b18: 01069693 slli a3,a3,0x10 -80010b1c: 02c58633 mul a2,a1,a2 -80010b20: 01c6e5b3 or a1,a3,t3 -80010b24: 00c5fa63 bgeu a1,a2,80010b38 <__umoddi3+0x240> -80010b28: 011585b3 add a1,a1,a7 -80010b2c: 0115e663 bltu a1,a7,80010b38 <__umoddi3+0x240> -80010b30: 00c5f463 bgeu a1,a2,80010b38 <__umoddi3+0x240> -80010b34: 011585b3 add a1,a1,a7 -80010b38: 40c585b3 sub a1,a1,a2 -80010b3c: ef1ff06f j 80010a2c <__umoddi3+0x134> -80010b40: e8d5eae3 bltu a1,a3,800109d4 <__umoddi3+0xdc> -80010b44: 00010737 lui a4,0x10 -80010b48: 04e6fc63 bgeu a3,a4,80010ba0 <__umoddi3+0x2a8> -80010b4c: 0ff00e13 li t3,255 -80010b50: 00de3733 sltu a4,t3,a3 -80010b54: 00371713 slli a4,a4,0x3 -80010b58: 800168b7 lui a7,0x80016 -80010b5c: 00e6d333 srl t1,a3,a4 -80010b60: 84c88893 addi a7,a7,-1972 # 8001584c <__BSS_END__+0xffffec10> -80010b64: 006888b3 add a7,a7,t1 -80010b68: 0008ce03 lbu t3,0(a7) -80010b6c: 00ee0e33 add t3,t3,a4 -80010b70: 02000713 li a4,32 -80010b74: 41c70333 sub t1,a4,t3 -80010b78: 03c71e63 bne a4,t3,80010bb4 <__umoddi3+0x2bc> -80010b7c: 00b6e463 bltu a3,a1,80010b84 <__umoddi3+0x28c> -80010b80: 00c56a63 bltu a0,a2,80010b94 <__umoddi3+0x29c> -80010b84: 40c507b3 sub a5,a0,a2 -80010b88: 40d585b3 sub a1,a1,a3 -80010b8c: 00f53533 sltu a0,a0,a5 -80010b90: 40a58833 sub a6,a1,a0 -80010b94: 00078513 mv a0,a5 -80010b98: 00080593 mv a1,a6 -80010b9c: e39ff06f j 800109d4 <__umoddi3+0xdc> -80010ba0: 010008b7 lui a7,0x1000 -80010ba4: 01000713 li a4,16 -80010ba8: fb16e8e3 bltu a3,a7,80010b58 <__umoddi3+0x260> -80010bac: 01800713 li a4,24 -80010bb0: fa9ff06f j 80010b58 <__umoddi3+0x260> -80010bb4: 01c65733 srl a4,a2,t3 -80010bb8: 006696b3 sll a3,a3,t1 -80010bbc: 00d76f33 or t5,a4,a3 -80010bc0: 01c5d7b3 srl a5,a1,t3 -80010bc4: 010f5713 srli a4,t5,0x10 -80010bc8: 02e7f8b3 remu a7,a5,a4 -80010bcc: 006595b3 sll a1,a1,t1 -80010bd0: 01c55833 srl a6,a0,t3 -80010bd4: 00b86833 or a6,a6,a1 -80010bd8: 010f1593 slli a1,t5,0x10 -80010bdc: 0105d593 srli a1,a1,0x10 -80010be0: 01085693 srli a3,a6,0x10 -80010be4: 00661633 sll a2,a2,t1 -80010be8: 00651533 sll a0,a0,t1 -80010bec: 02e7d7b3 divu a5,a5,a4 -80010bf0: 01089893 slli a7,a7,0x10 -80010bf4: 00d8e6b3 or a3,a7,a3 -80010bf8: 02f58eb3 mul t4,a1,a5 -80010bfc: 00078893 mv a7,a5 -80010c00: 01d6fe63 bgeu a3,t4,80010c1c <__umoddi3+0x324> -80010c04: 01e686b3 add a3,a3,t5 -80010c08: fff78893 addi a7,a5,-1 -80010c0c: 01e6e863 bltu a3,t5,80010c1c <__umoddi3+0x324> -80010c10: 01d6f663 bgeu a3,t4,80010c1c <__umoddi3+0x324> -80010c14: ffe78893 addi a7,a5,-2 -80010c18: 01e686b3 add a3,a3,t5 -80010c1c: 41d686b3 sub a3,a3,t4 -80010c20: 02e6feb3 remu t4,a3,a4 -80010c24: 01081813 slli a6,a6,0x10 -80010c28: 01085813 srli a6,a6,0x10 -80010c2c: 02e6d6b3 divu a3,a3,a4 -80010c30: 010e9e93 slli t4,t4,0x10 -80010c34: 010eeeb3 or t4,t4,a6 -80010c38: 02d585b3 mul a1,a1,a3 -80010c3c: 00068793 mv a5,a3 -80010c40: 00befe63 bgeu t4,a1,80010c5c <__umoddi3+0x364> -80010c44: 01ee8eb3 add t4,t4,t5 -80010c48: fff68793 addi a5,a3,-1 -80010c4c: 01eee863 bltu t4,t5,80010c5c <__umoddi3+0x364> -80010c50: 00bef663 bgeu t4,a1,80010c5c <__umoddi3+0x364> -80010c54: ffe68793 addi a5,a3,-2 -80010c58: 01ee8eb3 add t4,t4,t5 -80010c5c: 40be85b3 sub a1,t4,a1 -80010c60: 01089893 slli a7,a7,0x10 -80010c64: 00010eb7 lui t4,0x10 -80010c68: 00f8e8b3 or a7,a7,a5 -80010c6c: fffe8793 addi a5,t4,-1 # ffff <_start-0x7fff0001> -80010c70: 00f8f833 and a6,a7,a5 -80010c74: 01065693 srli a3,a2,0x10 -80010c78: 0108d893 srli a7,a7,0x10 -80010c7c: 00f677b3 and a5,a2,a5 -80010c80: 02f80733 mul a4,a6,a5 -80010c84: 02f887b3 mul a5,a7,a5 -80010c88: 02d80833 mul a6,a6,a3 -80010c8c: 02d888b3 mul a7,a7,a3 -80010c90: 00f80833 add a6,a6,a5 -80010c94: 01075693 srli a3,a4,0x10 -80010c98: 010686b3 add a3,a3,a6 -80010c9c: 00f6f463 bgeu a3,a5,80010ca4 <__umoddi3+0x3ac> -80010ca0: 01d888b3 add a7,a7,t4 -80010ca4: 000107b7 lui a5,0x10 -80010ca8: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -80010cac: 0106d813 srli a6,a3,0x10 -80010cb0: 00f6f6b3 and a3,a3,a5 -80010cb4: 01069693 slli a3,a3,0x10 -80010cb8: 00f77733 and a4,a4,a5 -80010cbc: 011808b3 add a7,a6,a7 -80010cc0: 00e68733 add a4,a3,a4 -80010cc4: 0115e663 bltu a1,a7,80010cd0 <__umoddi3+0x3d8> -80010cc8: 01159e63 bne a1,a7,80010ce4 <__umoddi3+0x3ec> -80010ccc: 00e57c63 bgeu a0,a4,80010ce4 <__umoddi3+0x3ec> -80010cd0: 40c70633 sub a2,a4,a2 -80010cd4: 00c73733 sltu a4,a4,a2 -80010cd8: 01e70733 add a4,a4,t5 -80010cdc: 40e888b3 sub a7,a7,a4 -80010ce0: 00060713 mv a4,a2 -80010ce4: 40e50733 sub a4,a0,a4 -80010ce8: 00e53533 sltu a0,a0,a4 -80010cec: 411585b3 sub a1,a1,a7 -80010cf0: 40a585b3 sub a1,a1,a0 -80010cf4: 01c597b3 sll a5,a1,t3 -80010cf8: 00675733 srl a4,a4,t1 -80010cfc: 00e7e533 or a0,a5,a4 -80010d00: 0065d5b3 srl a1,a1,t1 -80010d04: cd1ff06f j 800109d4 <__umoddi3+0xdc> +800109c8: 0117e663 bltu a5,a7,800109d4 <__umoddi3+0x1a0> +800109cc: 00b7f463 bgeu a5,a1,800109d4 <__umoddi3+0x1a0> +800109d0: 011787b3 add a5,a5,a7 +800109d4: 40b787b3 sub a5,a5,a1 +800109d8: f31ff06f j 80010908 <__umoddi3+0xd4> +800109dc: 01000637 lui a2,0x1000 +800109e0: 01000713 li a4,16 +800109e4: f6c8e2e3 bltu a7,a2,80010948 <__umoddi3+0x114> +800109e8: 01800713 li a4,24 +800109ec: f5dff06f j 80010948 <__umoddi3+0x114> +800109f0: 006898b3 sll a7,a7,t1 +800109f4: 01c5d733 srl a4,a1,t3 +800109f8: 006517b3 sll a5,a0,t1 +800109fc: 01c55e33 srl t3,a0,t3 +80010a00: 0108d513 srli a0,a7,0x10 +80010a04: 02a776b3 remu a3,a4,a0 +80010a08: 006595b3 sll a1,a1,t1 +80010a0c: 00be6e33 or t3,t3,a1 +80010a10: 01089593 slli a1,a7,0x10 +80010a14: 0105d593 srli a1,a1,0x10 +80010a18: 010e5613 srli a2,t3,0x10 +80010a1c: 02a75733 divu a4,a4,a0 +80010a20: 01069693 slli a3,a3,0x10 +80010a24: 00c6e6b3 or a3,a3,a2 +80010a28: 02e58733 mul a4,a1,a4 +80010a2c: 00e6fa63 bgeu a3,a4,80010a40 <__umoddi3+0x20c> +80010a30: 011686b3 add a3,a3,a7 +80010a34: 0116e663 bltu a3,a7,80010a40 <__umoddi3+0x20c> +80010a38: 00e6f463 bgeu a3,a4,80010a40 <__umoddi3+0x20c> +80010a3c: 011686b3 add a3,a3,a7 +80010a40: 40e68633 sub a2,a3,a4 +80010a44: 02a676b3 remu a3,a2,a0 +80010a48: 010e1e13 slli t3,t3,0x10 +80010a4c: 010e5e13 srli t3,t3,0x10 +80010a50: 02a65633 divu a2,a2,a0 +80010a54: 01069693 slli a3,a3,0x10 +80010a58: 02c58633 mul a2,a1,a2 +80010a5c: 01c6e5b3 or a1,a3,t3 +80010a60: 00c5fa63 bgeu a1,a2,80010a74 <__umoddi3+0x240> +80010a64: 011585b3 add a1,a1,a7 +80010a68: 0115e663 bltu a1,a7,80010a74 <__umoddi3+0x240> +80010a6c: 00c5f463 bgeu a1,a2,80010a74 <__umoddi3+0x240> +80010a70: 011585b3 add a1,a1,a7 +80010a74: 40c585b3 sub a1,a1,a2 +80010a78: ef1ff06f j 80010968 <__umoddi3+0x134> +80010a7c: e8d5eae3 bltu a1,a3,80010910 <__umoddi3+0xdc> +80010a80: 00010737 lui a4,0x10 +80010a84: 04e6fc63 bgeu a3,a4,80010adc <__umoddi3+0x2a8> +80010a88: 0ff00e13 li t3,255 +80010a8c: 00de3733 sltu a4,t3,a3 +80010a90: 00371713 slli a4,a4,0x3 +80010a94: 800158b7 lui a7,0x80015 +80010a98: 00e6d333 srl t1,a3,a4 +80010a9c: 77488893 addi a7,a7,1908 # 80015774 <__BSS_END__+0xffffeb38> +80010aa0: 006888b3 add a7,a7,t1 +80010aa4: 0008ce03 lbu t3,0(a7) +80010aa8: 00ee0e33 add t3,t3,a4 +80010aac: 02000713 li a4,32 +80010ab0: 41c70333 sub t1,a4,t3 +80010ab4: 03c71e63 bne a4,t3,80010af0 <__umoddi3+0x2bc> +80010ab8: 00b6e463 bltu a3,a1,80010ac0 <__umoddi3+0x28c> +80010abc: 00c56a63 bltu a0,a2,80010ad0 <__umoddi3+0x29c> +80010ac0: 40c507b3 sub a5,a0,a2 +80010ac4: 40d585b3 sub a1,a1,a3 +80010ac8: 00f53533 sltu a0,a0,a5 +80010acc: 40a58833 sub a6,a1,a0 +80010ad0: 00078513 mv a0,a5 +80010ad4: 00080593 mv a1,a6 +80010ad8: e39ff06f j 80010910 <__umoddi3+0xdc> +80010adc: 010008b7 lui a7,0x1000 +80010ae0: 01000713 li a4,16 +80010ae4: fb16e8e3 bltu a3,a7,80010a94 <__umoddi3+0x260> +80010ae8: 01800713 li a4,24 +80010aec: fa9ff06f j 80010a94 <__umoddi3+0x260> +80010af0: 01c65733 srl a4,a2,t3 +80010af4: 006696b3 sll a3,a3,t1 +80010af8: 00d76f33 or t5,a4,a3 +80010afc: 01c5d7b3 srl a5,a1,t3 +80010b00: 010f5713 srli a4,t5,0x10 +80010b04: 02e7f8b3 remu a7,a5,a4 +80010b08: 006595b3 sll a1,a1,t1 +80010b0c: 01c55833 srl a6,a0,t3 +80010b10: 00b86833 or a6,a6,a1 +80010b14: 010f1593 slli a1,t5,0x10 +80010b18: 0105d593 srli a1,a1,0x10 +80010b1c: 01085693 srli a3,a6,0x10 +80010b20: 00661633 sll a2,a2,t1 +80010b24: 00651533 sll a0,a0,t1 +80010b28: 02e7d7b3 divu a5,a5,a4 +80010b2c: 01089893 slli a7,a7,0x10 +80010b30: 00d8e6b3 or a3,a7,a3 +80010b34: 02f58eb3 mul t4,a1,a5 +80010b38: 00078893 mv a7,a5 +80010b3c: 01d6fe63 bgeu a3,t4,80010b58 <__umoddi3+0x324> +80010b40: 01e686b3 add a3,a3,t5 +80010b44: fff78893 addi a7,a5,-1 +80010b48: 01e6e863 bltu a3,t5,80010b58 <__umoddi3+0x324> +80010b4c: 01d6f663 bgeu a3,t4,80010b58 <__umoddi3+0x324> +80010b50: ffe78893 addi a7,a5,-2 +80010b54: 01e686b3 add a3,a3,t5 +80010b58: 41d686b3 sub a3,a3,t4 +80010b5c: 02e6feb3 remu t4,a3,a4 +80010b60: 01081813 slli a6,a6,0x10 +80010b64: 01085813 srli a6,a6,0x10 +80010b68: 02e6d6b3 divu a3,a3,a4 +80010b6c: 010e9e93 slli t4,t4,0x10 +80010b70: 010eeeb3 or t4,t4,a6 +80010b74: 02d585b3 mul a1,a1,a3 +80010b78: 00068793 mv a5,a3 +80010b7c: 00befe63 bgeu t4,a1,80010b98 <__umoddi3+0x364> +80010b80: 01ee8eb3 add t4,t4,t5 +80010b84: fff68793 addi a5,a3,-1 +80010b88: 01eee863 bltu t4,t5,80010b98 <__umoddi3+0x364> +80010b8c: 00bef663 bgeu t4,a1,80010b98 <__umoddi3+0x364> +80010b90: ffe68793 addi a5,a3,-2 +80010b94: 01ee8eb3 add t4,t4,t5 +80010b98: 40be85b3 sub a1,t4,a1 +80010b9c: 01089893 slli a7,a7,0x10 +80010ba0: 00010eb7 lui t4,0x10 +80010ba4: 00f8e8b3 or a7,a7,a5 +80010ba8: fffe8793 addi a5,t4,-1 # ffff <_start-0x7fff0001> +80010bac: 00f8f833 and a6,a7,a5 +80010bb0: 01065693 srli a3,a2,0x10 +80010bb4: 0108d893 srli a7,a7,0x10 +80010bb8: 00f677b3 and a5,a2,a5 +80010bbc: 02f80733 mul a4,a6,a5 +80010bc0: 02f887b3 mul a5,a7,a5 +80010bc4: 02d80833 mul a6,a6,a3 +80010bc8: 02d888b3 mul a7,a7,a3 +80010bcc: 00f80833 add a6,a6,a5 +80010bd0: 01075693 srli a3,a4,0x10 +80010bd4: 010686b3 add a3,a3,a6 +80010bd8: 00f6f463 bgeu a3,a5,80010be0 <__umoddi3+0x3ac> +80010bdc: 01d888b3 add a7,a7,t4 +80010be0: 000107b7 lui a5,0x10 +80010be4: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +80010be8: 0106d813 srli a6,a3,0x10 +80010bec: 00f6f6b3 and a3,a3,a5 +80010bf0: 01069693 slli a3,a3,0x10 +80010bf4: 00f77733 and a4,a4,a5 +80010bf8: 011808b3 add a7,a6,a7 +80010bfc: 00e68733 add a4,a3,a4 +80010c00: 0115e663 bltu a1,a7,80010c0c <__umoddi3+0x3d8> +80010c04: 01159e63 bne a1,a7,80010c20 <__umoddi3+0x3ec> +80010c08: 00e57c63 bgeu a0,a4,80010c20 <__umoddi3+0x3ec> +80010c0c: 40c70633 sub a2,a4,a2 +80010c10: 00c73733 sltu a4,a4,a2 +80010c14: 01e70733 add a4,a4,t5 +80010c18: 40e888b3 sub a7,a7,a4 +80010c1c: 00060713 mv a4,a2 +80010c20: 40e50733 sub a4,a0,a4 +80010c24: 00e53533 sltu a0,a0,a4 +80010c28: 411585b3 sub a1,a1,a7 +80010c2c: 40a585b3 sub a1,a1,a0 +80010c30: 01c597b3 sll a5,a1,t3 +80010c34: 00675733 srl a4,a4,t1 +80010c38: 00e7e533 or a0,a5,a4 +80010c3c: 0065d5b3 srl a1,a1,t1 +80010c40: cd1ff06f j 80010910 <__umoddi3+0xdc> -80010d08 <__divdf3>: -80010d08: fd010113 addi sp,sp,-48 -80010d0c: 0145d793 srli a5,a1,0x14 -80010d10: 02912223 sw s1,36(sp) -80010d14: 03212023 sw s2,32(sp) -80010d18: 01412c23 sw s4,24(sp) -80010d1c: 01612823 sw s6,16(sp) -80010d20: 01812423 sw s8,8(sp) -80010d24: 00c59493 slli s1,a1,0xc -80010d28: 02112623 sw ra,44(sp) -80010d2c: 02812423 sw s0,40(sp) -80010d30: 01312e23 sw s3,28(sp) -80010d34: 01512a23 sw s5,20(sp) -80010d38: 01712623 sw s7,12(sp) -80010d3c: 01579713 slli a4,a5,0x15 -80010d40: 00050913 mv s2,a0 -80010d44: 00060b13 mv s6,a2 -80010d48: 00068c13 mv s8,a3 -80010d4c: 00c4d493 srli s1,s1,0xc -80010d50: 01f5da13 srli s4,a1,0x1f -80010d54: 0a070463 beqz a4,80010dfc <__divdf3+0xf4> -80010d58: 7ff7fa93 andi s5,a5,2047 -80010d5c: 7ff00793 li a5,2047 -80010d60: 10fa8063 beq s5,a5,80010e60 <__divdf3+0x158> -80010d64: 01d55993 srli s3,a0,0x1d -80010d68: 00349493 slli s1,s1,0x3 -80010d6c: 0099e4b3 or s1,s3,s1 -80010d70: 008009b7 lui s3,0x800 -80010d74: 0134e9b3 or s3,s1,s3 -80010d78: 00351413 slli s0,a0,0x3 -80010d7c: c01a8a93 addi s5,s5,-1023 -80010d80: 00000b93 li s7,0 -80010d84: 014c5793 srli a5,s8,0x14 -80010d88: 00cc1513 slli a0,s8,0xc -80010d8c: 01579713 slli a4,a5,0x15 -80010d90: 00c55493 srli s1,a0,0xc -80010d94: 7ff7f593 andi a1,a5,2047 -80010d98: 01fc5c13 srli s8,s8,0x1f -80010d9c: 10070063 beqz a4,80010e9c <__divdf3+0x194> -80010da0: 7ff00793 li a5,2047 -80010da4: 16f58263 beq a1,a5,80010f08 <__divdf3+0x200> -80010da8: 00349513 slli a0,s1,0x3 -80010dac: 01db5793 srli a5,s6,0x1d -80010db0: 00a7e533 or a0,a5,a0 -80010db4: 008004b7 lui s1,0x800 -80010db8: 009564b3 or s1,a0,s1 -80010dbc: 003b1f93 slli t6,s6,0x3 -80010dc0: c0158513 addi a0,a1,-1023 -80010dc4: 00000613 li a2,0 -80010dc8: 002b9793 slli a5,s7,0x2 -80010dcc: 00c7e7b3 or a5,a5,a2 -80010dd0: fff78793 addi a5,a5,-1 -80010dd4: 00e00713 li a4,14 -80010dd8: 018a46b3 xor a3,s4,s8 -80010ddc: 40aa85b3 sub a1,s5,a0 -80010de0: 16f76063 bltu a4,a5,80010f40 <__divdf3+0x238> -80010de4: 80015737 lui a4,0x80015 -80010de8: 00279793 slli a5,a5,0x2 -80010dec: 79870713 addi a4,a4,1944 # 80015798 <__BSS_END__+0xffffeb5c> -80010df0: 00e787b3 add a5,a5,a4 -80010df4: 0007a783 lw a5,0(a5) -80010df8: 00078067 jr a5 -80010dfc: 00a4e9b3 or s3,s1,a0 -80010e00: 06098e63 beqz s3,80010e7c <__divdf3+0x174> -80010e04: 04048063 beqz s1,80010e44 <__divdf3+0x13c> -80010e08: 00048513 mv a0,s1 -80010e0c: 3bd030ef jal ra,800149c8 <__clzsi2> -80010e10: ff550793 addi a5,a0,-11 -80010e14: 01c00713 li a4,28 -80010e18: 02f74c63 blt a4,a5,80010e50 <__divdf3+0x148> -80010e1c: 01d00993 li s3,29 -80010e20: ff850413 addi s0,a0,-8 -80010e24: 40f989b3 sub s3,s3,a5 -80010e28: 008494b3 sll s1,s1,s0 -80010e2c: 013959b3 srl s3,s2,s3 -80010e30: 0099e9b3 or s3,s3,s1 -80010e34: 00891433 sll s0,s2,s0 -80010e38: c0d00593 li a1,-1011 -80010e3c: 40a58ab3 sub s5,a1,a0 -80010e40: f41ff06f j 80010d80 <__divdf3+0x78> -80010e44: 385030ef jal ra,800149c8 <__clzsi2> -80010e48: 02050513 addi a0,a0,32 -80010e4c: fc5ff06f j 80010e10 <__divdf3+0x108> -80010e50: fd850493 addi s1,a0,-40 -80010e54: 009919b3 sll s3,s2,s1 -80010e58: 00000413 li s0,0 -80010e5c: fddff06f j 80010e38 <__divdf3+0x130> -80010e60: 00a4e9b3 or s3,s1,a0 -80010e64: 02098463 beqz s3,80010e8c <__divdf3+0x184> -80010e68: 00050413 mv s0,a0 -80010e6c: 00048993 mv s3,s1 -80010e70: 7ff00a93 li s5,2047 -80010e74: 00300b93 li s7,3 -80010e78: f0dff06f j 80010d84 <__divdf3+0x7c> -80010e7c: 00000413 li s0,0 -80010e80: 00000a93 li s5,0 -80010e84: 00100b93 li s7,1 -80010e88: efdff06f j 80010d84 <__divdf3+0x7c> -80010e8c: 00000413 li s0,0 -80010e90: 7ff00a93 li s5,2047 -80010e94: 00200b93 li s7,2 -80010e98: eedff06f j 80010d84 <__divdf3+0x7c> -80010e9c: 0164efb3 or t6,s1,s6 -80010ea0: 080f8063 beqz t6,80010f20 <__divdf3+0x218> -80010ea4: 04048263 beqz s1,80010ee8 <__divdf3+0x1e0> -80010ea8: 00048513 mv a0,s1 -80010eac: 31d030ef jal ra,800149c8 <__clzsi2> -80010eb0: 00050593 mv a1,a0 -80010eb4: ff558793 addi a5,a1,-11 -80010eb8: 01c00713 li a4,28 -80010ebc: 02f74e63 blt a4,a5,80010ef8 <__divdf3+0x1f0> -80010ec0: 01d00693 li a3,29 -80010ec4: ff858f93 addi t6,a1,-8 -80010ec8: 40f686b3 sub a3,a3,a5 -80010ecc: 01f49533 sll a0,s1,t6 -80010ed0: 00db56b3 srl a3,s6,a3 -80010ed4: 00a6e4b3 or s1,a3,a0 -80010ed8: 01fb1fb3 sll t6,s6,t6 -80010edc: c0d00713 li a4,-1011 -80010ee0: 40b70533 sub a0,a4,a1 -80010ee4: ee1ff06f j 80010dc4 <__divdf3+0xbc> -80010ee8: 000b0513 mv a0,s6 -80010eec: 2dd030ef jal ra,800149c8 <__clzsi2> -80010ef0: 02050593 addi a1,a0,32 -80010ef4: fc1ff06f j 80010eb4 <__divdf3+0x1ac> -80010ef8: fd858513 addi a0,a1,-40 -80010efc: 00ab14b3 sll s1,s6,a0 -80010f00: 00000f93 li t6,0 -80010f04: fd9ff06f j 80010edc <__divdf3+0x1d4> -80010f08: 0164efb3 or t6,s1,s6 -80010f0c: 020f8263 beqz t6,80010f30 <__divdf3+0x228> -80010f10: 000b0f93 mv t6,s6 -80010f14: 7ff00513 li a0,2047 -80010f18: 00300613 li a2,3 -80010f1c: eadff06f j 80010dc8 <__divdf3+0xc0> -80010f20: 00000493 li s1,0 -80010f24: 00000513 li a0,0 -80010f28: 00100613 li a2,1 -80010f2c: e9dff06f j 80010dc8 <__divdf3+0xc0> -80010f30: 00000493 li s1,0 -80010f34: 7ff00513 li a0,2047 -80010f38: 00200613 li a2,2 -80010f3c: e8dff06f j 80010dc8 <__divdf3+0xc0> -80010f40: 0134e663 bltu s1,s3,80010f4c <__divdf3+0x244> -80010f44: 34999c63 bne s3,s1,8001129c <__divdf3+0x594> -80010f48: 35f46a63 bltu s0,t6,8001129c <__divdf3+0x594> -80010f4c: 01f99613 slli a2,s3,0x1f -80010f50: 00145713 srli a4,s0,0x1 -80010f54: 01f41793 slli a5,s0,0x1f -80010f58: 0019d993 srli s3,s3,0x1 -80010f5c: 00e66433 or s0,a2,a4 -80010f60: 00849513 slli a0,s1,0x8 -80010f64: 018fd893 srli a7,t6,0x18 -80010f68: 00a8e8b3 or a7,a7,a0 -80010f6c: 01055513 srli a0,a0,0x10 -80010f70: 02a9d833 divu a6,s3,a0 -80010f74: 01089e93 slli t4,a7,0x10 -80010f78: 010ede93 srli t4,t4,0x10 -80010f7c: 01045713 srli a4,s0,0x10 -80010f80: 008f9313 slli t1,t6,0x8 -80010f84: 02a9f4b3 remu s1,s3,a0 -80010f88: 00080f93 mv t6,a6 -80010f8c: 030e8633 mul a2,t4,a6 -80010f90: 01049993 slli s3,s1,0x10 -80010f94: 01376733 or a4,a4,s3 -80010f98: 00c77e63 bgeu a4,a2,80010fb4 <__divdf3+0x2ac> -80010f9c: 01170733 add a4,a4,a7 -80010fa0: fff80f93 addi t6,a6,-1 -80010fa4: 01176863 bltu a4,a7,80010fb4 <__divdf3+0x2ac> -80010fa8: 00c77663 bgeu a4,a2,80010fb4 <__divdf3+0x2ac> -80010fac: ffe80f93 addi t6,a6,-2 +80010c44 <__divdf3>: +80010c44: fd010113 addi sp,sp,-48 +80010c48: 0145d793 srli a5,a1,0x14 +80010c4c: 02912223 sw s1,36(sp) +80010c50: 03212023 sw s2,32(sp) +80010c54: 01412c23 sw s4,24(sp) +80010c58: 01612823 sw s6,16(sp) +80010c5c: 01812423 sw s8,8(sp) +80010c60: 00c59493 slli s1,a1,0xc +80010c64: 02112623 sw ra,44(sp) +80010c68: 02812423 sw s0,40(sp) +80010c6c: 01312e23 sw s3,28(sp) +80010c70: 01512a23 sw s5,20(sp) +80010c74: 01712623 sw s7,12(sp) +80010c78: 01579713 slli a4,a5,0x15 +80010c7c: 00050913 mv s2,a0 +80010c80: 00060b13 mv s6,a2 +80010c84: 00068c13 mv s8,a3 +80010c88: 00c4d493 srli s1,s1,0xc +80010c8c: 01f5da13 srli s4,a1,0x1f +80010c90: 0a070463 beqz a4,80010d38 <__divdf3+0xf4> +80010c94: 7ff7fa93 andi s5,a5,2047 +80010c98: 7ff00793 li a5,2047 +80010c9c: 10fa8063 beq s5,a5,80010d9c <__divdf3+0x158> +80010ca0: 01d55993 srli s3,a0,0x1d +80010ca4: 00349493 slli s1,s1,0x3 +80010ca8: 0099e4b3 or s1,s3,s1 +80010cac: 008009b7 lui s3,0x800 +80010cb0: 0134e9b3 or s3,s1,s3 +80010cb4: 00351413 slli s0,a0,0x3 +80010cb8: c01a8a93 addi s5,s5,-1023 +80010cbc: 00000b93 li s7,0 +80010cc0: 014c5793 srli a5,s8,0x14 +80010cc4: 00cc1513 slli a0,s8,0xc +80010cc8: 01579713 slli a4,a5,0x15 +80010ccc: 00c55493 srli s1,a0,0xc +80010cd0: 7ff7f593 andi a1,a5,2047 +80010cd4: 01fc5c13 srli s8,s8,0x1f +80010cd8: 10070063 beqz a4,80010dd8 <__divdf3+0x194> +80010cdc: 7ff00793 li a5,2047 +80010ce0: 16f58263 beq a1,a5,80010e44 <__divdf3+0x200> +80010ce4: 00349513 slli a0,s1,0x3 +80010ce8: 01db5793 srli a5,s6,0x1d +80010cec: 00a7e533 or a0,a5,a0 +80010cf0: 008004b7 lui s1,0x800 +80010cf4: 009564b3 or s1,a0,s1 +80010cf8: 003b1f93 slli t6,s6,0x3 +80010cfc: c0158513 addi a0,a1,-1023 +80010d00: 00000613 li a2,0 +80010d04: 002b9793 slli a5,s7,0x2 +80010d08: 00c7e7b3 or a5,a5,a2 +80010d0c: fff78793 addi a5,a5,-1 +80010d10: 00e00713 li a4,14 +80010d14: 018a46b3 xor a3,s4,s8 +80010d18: 40aa85b3 sub a1,s5,a0 +80010d1c: 16f76063 bltu a4,a5,80010e7c <__divdf3+0x238> +80010d20: 80015737 lui a4,0x80015 +80010d24: 00279793 slli a5,a5,0x2 +80010d28: 6c070713 addi a4,a4,1728 # 800156c0 <__BSS_END__+0xffffea84> +80010d2c: 00e787b3 add a5,a5,a4 +80010d30: 0007a783 lw a5,0(a5) +80010d34: 00078067 jr a5 +80010d38: 00a4e9b3 or s3,s1,a0 +80010d3c: 06098e63 beqz s3,80010db8 <__divdf3+0x174> +80010d40: 04048063 beqz s1,80010d80 <__divdf3+0x13c> +80010d44: 00048513 mv a0,s1 +80010d48: 3bd030ef jal ra,80014904 <__clzsi2> +80010d4c: ff550793 addi a5,a0,-11 +80010d50: 01c00713 li a4,28 +80010d54: 02f74c63 blt a4,a5,80010d8c <__divdf3+0x148> +80010d58: 01d00993 li s3,29 +80010d5c: ff850413 addi s0,a0,-8 +80010d60: 40f989b3 sub s3,s3,a5 +80010d64: 008494b3 sll s1,s1,s0 +80010d68: 013959b3 srl s3,s2,s3 +80010d6c: 0099e9b3 or s3,s3,s1 +80010d70: 00891433 sll s0,s2,s0 +80010d74: c0d00593 li a1,-1011 +80010d78: 40a58ab3 sub s5,a1,a0 +80010d7c: f41ff06f j 80010cbc <__divdf3+0x78> +80010d80: 385030ef jal ra,80014904 <__clzsi2> +80010d84: 02050513 addi a0,a0,32 +80010d88: fc5ff06f j 80010d4c <__divdf3+0x108> +80010d8c: fd850493 addi s1,a0,-40 +80010d90: 009919b3 sll s3,s2,s1 +80010d94: 00000413 li s0,0 +80010d98: fddff06f j 80010d74 <__divdf3+0x130> +80010d9c: 00a4e9b3 or s3,s1,a0 +80010da0: 02098463 beqz s3,80010dc8 <__divdf3+0x184> +80010da4: 00050413 mv s0,a0 +80010da8: 00048993 mv s3,s1 +80010dac: 7ff00a93 li s5,2047 +80010db0: 00300b93 li s7,3 +80010db4: f0dff06f j 80010cc0 <__divdf3+0x7c> +80010db8: 00000413 li s0,0 +80010dbc: 00000a93 li s5,0 +80010dc0: 00100b93 li s7,1 +80010dc4: efdff06f j 80010cc0 <__divdf3+0x7c> +80010dc8: 00000413 li s0,0 +80010dcc: 7ff00a93 li s5,2047 +80010dd0: 00200b93 li s7,2 +80010dd4: eedff06f j 80010cc0 <__divdf3+0x7c> +80010dd8: 0164efb3 or t6,s1,s6 +80010ddc: 080f8063 beqz t6,80010e5c <__divdf3+0x218> +80010de0: 04048263 beqz s1,80010e24 <__divdf3+0x1e0> +80010de4: 00048513 mv a0,s1 +80010de8: 31d030ef jal ra,80014904 <__clzsi2> +80010dec: 00050593 mv a1,a0 +80010df0: ff558793 addi a5,a1,-11 +80010df4: 01c00713 li a4,28 +80010df8: 02f74e63 blt a4,a5,80010e34 <__divdf3+0x1f0> +80010dfc: 01d00693 li a3,29 +80010e00: ff858f93 addi t6,a1,-8 +80010e04: 40f686b3 sub a3,a3,a5 +80010e08: 01f49533 sll a0,s1,t6 +80010e0c: 00db56b3 srl a3,s6,a3 +80010e10: 00a6e4b3 or s1,a3,a0 +80010e14: 01fb1fb3 sll t6,s6,t6 +80010e18: c0d00713 li a4,-1011 +80010e1c: 40b70533 sub a0,a4,a1 +80010e20: ee1ff06f j 80010d00 <__divdf3+0xbc> +80010e24: 000b0513 mv a0,s6 +80010e28: 2dd030ef jal ra,80014904 <__clzsi2> +80010e2c: 02050593 addi a1,a0,32 +80010e30: fc1ff06f j 80010df0 <__divdf3+0x1ac> +80010e34: fd858513 addi a0,a1,-40 +80010e38: 00ab14b3 sll s1,s6,a0 +80010e3c: 00000f93 li t6,0 +80010e40: fd9ff06f j 80010e18 <__divdf3+0x1d4> +80010e44: 0164efb3 or t6,s1,s6 +80010e48: 020f8263 beqz t6,80010e6c <__divdf3+0x228> +80010e4c: 000b0f93 mv t6,s6 +80010e50: 7ff00513 li a0,2047 +80010e54: 00300613 li a2,3 +80010e58: eadff06f j 80010d04 <__divdf3+0xc0> +80010e5c: 00000493 li s1,0 +80010e60: 00000513 li a0,0 +80010e64: 00100613 li a2,1 +80010e68: e9dff06f j 80010d04 <__divdf3+0xc0> +80010e6c: 00000493 li s1,0 +80010e70: 7ff00513 li a0,2047 +80010e74: 00200613 li a2,2 +80010e78: e8dff06f j 80010d04 <__divdf3+0xc0> +80010e7c: 0134e663 bltu s1,s3,80010e88 <__divdf3+0x244> +80010e80: 34999c63 bne s3,s1,800111d8 <__divdf3+0x594> +80010e84: 35f46a63 bltu s0,t6,800111d8 <__divdf3+0x594> +80010e88: 01f99613 slli a2,s3,0x1f +80010e8c: 00145713 srli a4,s0,0x1 +80010e90: 01f41793 slli a5,s0,0x1f +80010e94: 0019d993 srli s3,s3,0x1 +80010e98: 00e66433 or s0,a2,a4 +80010e9c: 00849513 slli a0,s1,0x8 +80010ea0: 018fd893 srli a7,t6,0x18 +80010ea4: 00a8e8b3 or a7,a7,a0 +80010ea8: 01055513 srli a0,a0,0x10 +80010eac: 02a9d833 divu a6,s3,a0 +80010eb0: 01089e93 slli t4,a7,0x10 +80010eb4: 010ede93 srli t4,t4,0x10 +80010eb8: 01045713 srli a4,s0,0x10 +80010ebc: 008f9313 slli t1,t6,0x8 +80010ec0: 02a9f4b3 remu s1,s3,a0 +80010ec4: 00080f93 mv t6,a6 +80010ec8: 030e8633 mul a2,t4,a6 +80010ecc: 01049993 slli s3,s1,0x10 +80010ed0: 01376733 or a4,a4,s3 +80010ed4: 00c77e63 bgeu a4,a2,80010ef0 <__divdf3+0x2ac> +80010ed8: 01170733 add a4,a4,a7 +80010edc: fff80f93 addi t6,a6,-1 +80010ee0: 01176863 bltu a4,a7,80010ef0 <__divdf3+0x2ac> +80010ee4: 00c77663 bgeu a4,a2,80010ef0 <__divdf3+0x2ac> +80010ee8: ffe80f93 addi t6,a6,-2 +80010eec: 01170733 add a4,a4,a7 +80010ef0: 40c70733 sub a4,a4,a2 +80010ef4: 02a75e33 divu t3,a4,a0 +80010ef8: 01041413 slli s0,s0,0x10 +80010efc: 01045413 srli s0,s0,0x10 +80010f00: 02a77733 remu a4,a4,a0 +80010f04: 000e0613 mv a2,t3 +80010f08: 03ce8833 mul a6,t4,t3 +80010f0c: 01071713 slli a4,a4,0x10 +80010f10: 00e46733 or a4,s0,a4 +80010f14: 01077e63 bgeu a4,a6,80010f30 <__divdf3+0x2ec> +80010f18: 01170733 add a4,a4,a7 +80010f1c: fffe0613 addi a2,t3,-1 +80010f20: 01176863 bltu a4,a7,80010f30 <__divdf3+0x2ec> +80010f24: 01077663 bgeu a4,a6,80010f30 <__divdf3+0x2ec> +80010f28: ffee0613 addi a2,t3,-2 +80010f2c: 01170733 add a4,a4,a7 +80010f30: 41070433 sub s0,a4,a6 +80010f34: 010f9f93 slli t6,t6,0x10 +80010f38: 00010837 lui a6,0x10 +80010f3c: 00cfefb3 or t6,t6,a2 +80010f40: fff80e13 addi t3,a6,-1 # ffff <_start-0x7fff0001> +80010f44: 010fd613 srli a2,t6,0x10 +80010f48: 01cff733 and a4,t6,t3 +80010f4c: 01035f13 srli t5,t1,0x10 +80010f50: 01c37e33 and t3,t1,t3 +80010f54: 02ee03b3 mul t2,t3,a4 +80010f58: 03c604b3 mul s1,a2,t3 +80010f5c: 02ef0733 mul a4,t5,a4 +80010f60: 03e602b3 mul t0,a2,t5 +80010f64: 00970633 add a2,a4,s1 +80010f68: 0103d713 srli a4,t2,0x10 +80010f6c: 00c70733 add a4,a4,a2 +80010f70: 00977463 bgeu a4,s1,80010f78 <__divdf3+0x334> +80010f74: 010282b3 add t0,t0,a6 +80010f78: 01075613 srli a2,a4,0x10 +80010f7c: 00560633 add a2,a2,t0 +80010f80: 000102b7 lui t0,0x10 +80010f84: fff28293 addi t0,t0,-1 # ffff <_start-0x7fff0001> +80010f88: 00577833 and a6,a4,t0 +80010f8c: 01081813 slli a6,a6,0x10 +80010f90: 0053f3b3 and t2,t2,t0 +80010f94: 00780833 add a6,a6,t2 +80010f98: 00c46863 bltu s0,a2,80010fa8 <__divdf3+0x364> +80010f9c: 000f8493 mv s1,t6 +80010fa0: 04c41463 bne s0,a2,80010fe8 <__divdf3+0x3a4> +80010fa4: 0507f263 bgeu a5,a6,80010fe8 <__divdf3+0x3a4> +80010fa8: 006787b3 add a5,a5,t1 +80010fac: 0067b733 sltu a4,a5,t1 80010fb0: 01170733 add a4,a4,a7 -80010fb4: 40c70733 sub a4,a4,a2 -80010fb8: 02a75e33 divu t3,a4,a0 -80010fbc: 01041413 slli s0,s0,0x10 -80010fc0: 01045413 srli s0,s0,0x10 -80010fc4: 02a77733 remu a4,a4,a0 -80010fc8: 000e0613 mv a2,t3 -80010fcc: 03ce8833 mul a6,t4,t3 -80010fd0: 01071713 slli a4,a4,0x10 -80010fd4: 00e46733 or a4,s0,a4 -80010fd8: 01077e63 bgeu a4,a6,80010ff4 <__divdf3+0x2ec> +80010fb4: 00e40433 add s0,s0,a4 +80010fb8: ffff8493 addi s1,t6,-1 +80010fbc: 0088e663 bltu a7,s0,80010fc8 <__divdf3+0x384> +80010fc0: 02889463 bne a7,s0,80010fe8 <__divdf3+0x3a4> +80010fc4: 0267e263 bltu a5,t1,80010fe8 <__divdf3+0x3a4> +80010fc8: 00c46663 bltu s0,a2,80010fd4 <__divdf3+0x390> +80010fcc: 00861e63 bne a2,s0,80010fe8 <__divdf3+0x3a4> +80010fd0: 0107fc63 bgeu a5,a6,80010fe8 <__divdf3+0x3a4> +80010fd4: 006787b3 add a5,a5,t1 +80010fd8: 0067b733 sltu a4,a5,t1 80010fdc: 01170733 add a4,a4,a7 -80010fe0: fffe0613 addi a2,t3,-1 -80010fe4: 01176863 bltu a4,a7,80010ff4 <__divdf3+0x2ec> -80010fe8: 01077663 bgeu a4,a6,80010ff4 <__divdf3+0x2ec> -80010fec: ffee0613 addi a2,t3,-2 -80010ff0: 01170733 add a4,a4,a7 -80010ff4: 41070433 sub s0,a4,a6 -80010ff8: 010f9f93 slli t6,t6,0x10 -80010ffc: 00010837 lui a6,0x10 -80011000: 00cfefb3 or t6,t6,a2 -80011004: fff80e13 addi t3,a6,-1 # ffff <_start-0x7fff0001> -80011008: 010fd613 srli a2,t6,0x10 -8001100c: 01cff733 and a4,t6,t3 -80011010: 01035f13 srli t5,t1,0x10 -80011014: 01c37e33 and t3,t1,t3 -80011018: 02ee03b3 mul t2,t3,a4 -8001101c: 03c604b3 mul s1,a2,t3 -80011020: 02ef0733 mul a4,t5,a4 -80011024: 03e602b3 mul t0,a2,t5 -80011028: 00970633 add a2,a4,s1 -8001102c: 0103d713 srli a4,t2,0x10 -80011030: 00c70733 add a4,a4,a2 -80011034: 00977463 bgeu a4,s1,8001103c <__divdf3+0x334> -80011038: 010282b3 add t0,t0,a6 -8001103c: 01075613 srli a2,a4,0x10 -80011040: 00560633 add a2,a2,t0 -80011044: 000102b7 lui t0,0x10 -80011048: fff28293 addi t0,t0,-1 # ffff <_start-0x7fff0001> -8001104c: 00577833 and a6,a4,t0 -80011050: 01081813 slli a6,a6,0x10 -80011054: 0053f3b3 and t2,t2,t0 -80011058: 00780833 add a6,a6,t2 -8001105c: 00c46863 bltu s0,a2,8001106c <__divdf3+0x364> -80011060: 000f8493 mv s1,t6 -80011064: 04c41463 bne s0,a2,800110ac <__divdf3+0x3a4> -80011068: 0507f263 bgeu a5,a6,800110ac <__divdf3+0x3a4> -8001106c: 006787b3 add a5,a5,t1 -80011070: 0067b733 sltu a4,a5,t1 -80011074: 01170733 add a4,a4,a7 -80011078: 00e40433 add s0,s0,a4 -8001107c: ffff8493 addi s1,t6,-1 -80011080: 0088e663 bltu a7,s0,8001108c <__divdf3+0x384> -80011084: 02889463 bne a7,s0,800110ac <__divdf3+0x3a4> -80011088: 0267e263 bltu a5,t1,800110ac <__divdf3+0x3a4> -8001108c: 00c46663 bltu s0,a2,80011098 <__divdf3+0x390> -80011090: 00861e63 bne a2,s0,800110ac <__divdf3+0x3a4> -80011094: 0107fc63 bgeu a5,a6,800110ac <__divdf3+0x3a4> -80011098: 006787b3 add a5,a5,t1 -8001109c: 0067b733 sltu a4,a5,t1 -800110a0: 01170733 add a4,a4,a7 -800110a4: ffef8493 addi s1,t6,-2 -800110a8: 00e40433 add s0,s0,a4 -800110ac: 41078833 sub a6,a5,a6 -800110b0: 40c40433 sub s0,s0,a2 -800110b4: 0107b7b3 sltu a5,a5,a6 -800110b8: 40f40433 sub s0,s0,a5 -800110bc: fff00f93 li t6,-1 -800110c0: 12888463 beq a7,s0,800111e8 <__divdf3+0x4e0> -800110c4: 02a45fb3 divu t6,s0,a0 -800110c8: 01085713 srli a4,a6,0x10 -800110cc: 02a47433 remu s0,s0,a0 -800110d0: 000f8613 mv a2,t6 -800110d4: 03fe87b3 mul a5,t4,t6 -800110d8: 01041413 slli s0,s0,0x10 -800110dc: 00876433 or s0,a4,s0 -800110e0: 00f47e63 bgeu s0,a5,800110fc <__divdf3+0x3f4> -800110e4: 01140433 add s0,s0,a7 -800110e8: ffff8613 addi a2,t6,-1 -800110ec: 01146863 bltu s0,a7,800110fc <__divdf3+0x3f4> -800110f0: 00f47663 bgeu s0,a5,800110fc <__divdf3+0x3f4> -800110f4: ffef8613 addi a2,t6,-2 -800110f8: 01140433 add s0,s0,a7 -800110fc: 40f40433 sub s0,s0,a5 -80011100: 02a45733 divu a4,s0,a0 -80011104: 01081813 slli a6,a6,0x10 -80011108: 01085813 srli a6,a6,0x10 -8001110c: 02a47433 remu s0,s0,a0 -80011110: 00070793 mv a5,a4 -80011114: 02ee8eb3 mul t4,t4,a4 -80011118: 01041413 slli s0,s0,0x10 -8001111c: 00886433 or s0,a6,s0 -80011120: 01d47e63 bgeu s0,t4,8001113c <__divdf3+0x434> -80011124: 01140433 add s0,s0,a7 -80011128: fff70793 addi a5,a4,-1 -8001112c: 01146863 bltu s0,a7,8001113c <__divdf3+0x434> -80011130: 01d47663 bgeu s0,t4,8001113c <__divdf3+0x434> -80011134: ffe70793 addi a5,a4,-2 -80011138: 01140433 add s0,s0,a7 -8001113c: 01061613 slli a2,a2,0x10 -80011140: 00f66633 or a2,a2,a5 -80011144: 01061793 slli a5,a2,0x10 -80011148: 0107d793 srli a5,a5,0x10 -8001114c: 01065713 srli a4,a2,0x10 -80011150: 02ef0833 mul a6,t5,a4 -80011154: 41d40433 sub s0,s0,t4 -80011158: 02ff0f33 mul t5,t5,a5 -8001115c: 03c78eb3 mul t4,a5,t3 -80011160: 03c70e33 mul t3,a4,t3 -80011164: 010ed793 srli a5,t4,0x10 -80011168: 01cf0f33 add t5,t5,t3 -8001116c: 01e787b3 add a5,a5,t5 -80011170: 01c7f663 bgeu a5,t3,8001117c <__divdf3+0x474> -80011174: 00010737 lui a4,0x10 -80011178: 00e80833 add a6,a6,a4 -8001117c: 0107d713 srli a4,a5,0x10 -80011180: 01070733 add a4,a4,a6 -80011184: 00010837 lui a6,0x10 -80011188: fff80813 addi a6,a6,-1 # ffff <_start-0x7fff0001> -8001118c: 0107f533 and a0,a5,a6 -80011190: 01051513 slli a0,a0,0x10 -80011194: 010efeb3 and t4,t4,a6 -80011198: 01d50533 add a0,a0,t4 -8001119c: 00e46863 bltu s0,a4,800111ac <__divdf3+0x4a4> -800111a0: 24e41063 bne s0,a4,800113e0 <__divdf3+0x6d8> -800111a4: 00060f93 mv t6,a2 -800111a8: 04050063 beqz a0,800111e8 <__divdf3+0x4e0> -800111ac: 00888433 add s0,a7,s0 -800111b0: fff60f93 addi t6,a2,-1 # ffffff <_start-0x7f000001> -800111b4: 03146463 bltu s0,a7,800111dc <__divdf3+0x4d4> -800111b8: 00e46663 bltu s0,a4,800111c4 <__divdf3+0x4bc> -800111bc: 22e41063 bne s0,a4,800113dc <__divdf3+0x6d4> -800111c0: 02a37063 bgeu t1,a0,800111e0 <__divdf3+0x4d8> -800111c4: 00131793 slli a5,t1,0x1 -800111c8: 0067b333 sltu t1,a5,t1 -800111cc: 011308b3 add a7,t1,a7 -800111d0: ffe60f93 addi t6,a2,-2 -800111d4: 01140433 add s0,s0,a7 -800111d8: 00078313 mv t1,a5 -800111dc: 00e41463 bne s0,a4,800111e4 <__divdf3+0x4dc> -800111e0: 00650463 beq a0,t1,800111e8 <__divdf3+0x4e0> -800111e4: 001fef93 ori t6,t6,1 -800111e8: 3ff58793 addi a5,a1,1023 -800111ec: 10f05863 blez a5,800112fc <__divdf3+0x5f4> -800111f0: 007ff713 andi a4,t6,7 -800111f4: 02070063 beqz a4,80011214 <__divdf3+0x50c> -800111f8: 00fff713 andi a4,t6,15 -800111fc: 00400613 li a2,4 -80011200: 00c70a63 beq a4,a2,80011214 <__divdf3+0x50c> -80011204: 004f8613 addi a2,t6,4 -80011208: 01f63fb3 sltu t6,a2,t6 -8001120c: 01f484b3 add s1,s1,t6 -80011210: 00060f93 mv t6,a2 -80011214: 00749713 slli a4,s1,0x7 -80011218: 00075a63 bgez a4,8001122c <__divdf3+0x524> -8001121c: ff0007b7 lui a5,0xff000 -80011220: fff78793 addi a5,a5,-1 # feffffff <__BSS_END__+0x7efe93c3> -80011224: 00f4f4b3 and s1,s1,a5 -80011228: 40058793 addi a5,a1,1024 -8001122c: 7fe00713 li a4,2046 -80011230: 0af74063 blt a4,a5,800112d0 <__divdf3+0x5c8> -80011234: 003fdf93 srli t6,t6,0x3 -80011238: 01d49713 slli a4,s1,0x1d -8001123c: 01f76733 or a4,a4,t6 -80011240: 0034d513 srli a0,s1,0x3 -80011244: 01479793 slli a5,a5,0x14 -80011248: 7ff00637 lui a2,0x7ff00 -8001124c: 00c51513 slli a0,a0,0xc -80011250: 02c12083 lw ra,44(sp) -80011254: 02812403 lw s0,40(sp) -80011258: 00c7f7b3 and a5,a5,a2 -8001125c: 00c55513 srli a0,a0,0xc -80011260: 00a7e533 or a0,a5,a0 -80011264: 01f69693 slli a3,a3,0x1f -80011268: 00d567b3 or a5,a0,a3 -8001126c: 02412483 lw s1,36(sp) -80011270: 02012903 lw s2,32(sp) -80011274: 01c12983 lw s3,28(sp) -80011278: 01812a03 lw s4,24(sp) -8001127c: 01412a83 lw s5,20(sp) -80011280: 01012b03 lw s6,16(sp) -80011284: 00c12b83 lw s7,12(sp) -80011288: 00812c03 lw s8,8(sp) -8001128c: 00070513 mv a0,a4 -80011290: 00078593 mv a1,a5 -80011294: 03010113 addi sp,sp,48 -80011298: 00008067 ret -8001129c: fff58593 addi a1,a1,-1 -800112a0: 00000793 li a5,0 -800112a4: cbdff06f j 80010f60 <__divdf3+0x258> -800112a8: 000a0693 mv a3,s4 -800112ac: 00098493 mv s1,s3 -800112b0: 00040f93 mv t6,s0 -800112b4: 000b8613 mv a2,s7 -800112b8: 00300793 li a5,3 -800112bc: 0ef60863 beq a2,a5,800113ac <__divdf3+0x6a4> -800112c0: 00100793 li a5,1 -800112c4: 0ef60e63 beq a2,a5,800113c0 <__divdf3+0x6b8> -800112c8: 00200793 li a5,2 -800112cc: f0f61ee3 bne a2,a5,800111e8 <__divdf3+0x4e0> -800112d0: 00000513 li a0,0 -800112d4: 00000713 li a4,0 -800112d8: 7ff00793 li a5,2047 -800112dc: f69ff06f j 80011244 <__divdf3+0x53c> -800112e0: 000c0693 mv a3,s8 -800112e4: fd5ff06f j 800112b8 <__divdf3+0x5b0> -800112e8: 000804b7 lui s1,0x80 -800112ec: 00000f93 li t6,0 -800112f0: 00000693 li a3,0 -800112f4: 00300613 li a2,3 -800112f8: fc1ff06f j 800112b8 <__divdf3+0x5b0> -800112fc: 00100513 li a0,1 -80011300: 40f50533 sub a0,a0,a5 -80011304: 03800713 li a4,56 -80011308: 0aa74c63 blt a4,a0,800113c0 <__divdf3+0x6b8> -8001130c: 01f00713 li a4,31 -80011310: 06a74463 blt a4,a0,80011378 <__divdf3+0x670> -80011314: 41e58593 addi a1,a1,1054 -80011318: 00b497b3 sll a5,s1,a1 -8001131c: 00afd733 srl a4,t6,a0 -80011320: 00bf95b3 sll a1,t6,a1 -80011324: 00e7e7b3 or a5,a5,a4 -80011328: 00b035b3 snez a1,a1 -8001132c: 00b7e7b3 or a5,a5,a1 -80011330: 00a4d533 srl a0,s1,a0 -80011334: 0077f713 andi a4,a5,7 -80011338: 02070063 beqz a4,80011358 <__divdf3+0x650> -8001133c: 00f7f713 andi a4,a5,15 -80011340: 00400613 li a2,4 -80011344: 00c70a63 beq a4,a2,80011358 <__divdf3+0x650> -80011348: 00478713 addi a4,a5,4 -8001134c: 00f737b3 sltu a5,a4,a5 -80011350: 00f50533 add a0,a0,a5 -80011354: 00070793 mv a5,a4 -80011358: 00851713 slli a4,a0,0x8 -8001135c: 06074863 bltz a4,800113cc <__divdf3+0x6c4> -80011360: 01d51713 slli a4,a0,0x1d -80011364: 0037d793 srli a5,a5,0x3 -80011368: 00f76733 or a4,a4,a5 -8001136c: 00355513 srli a0,a0,0x3 -80011370: 00000793 li a5,0 -80011374: ed1ff06f j 80011244 <__divdf3+0x53c> -80011378: fe100713 li a4,-31 -8001137c: 40f707b3 sub a5,a4,a5 -80011380: 02000613 li a2,32 -80011384: 00f4d7b3 srl a5,s1,a5 -80011388: 00000713 li a4,0 -8001138c: 00c50663 beq a0,a2,80011398 <__divdf3+0x690> -80011390: 43e58593 addi a1,a1,1086 -80011394: 00b49733 sll a4,s1,a1 -80011398: 01f76fb3 or t6,a4,t6 -8001139c: 01f03fb3 snez t6,t6 -800113a0: 01f7e7b3 or a5,a5,t6 -800113a4: 00000513 li a0,0 -800113a8: f8dff06f j 80011334 <__divdf3+0x62c> -800113ac: 00080537 lui a0,0x80 -800113b0: 00000713 li a4,0 -800113b4: 7ff00793 li a5,2047 -800113b8: 00000693 li a3,0 -800113bc: e89ff06f j 80011244 <__divdf3+0x53c> -800113c0: 00000513 li a0,0 -800113c4: 00000713 li a4,0 -800113c8: fa9ff06f j 80011370 <__divdf3+0x668> -800113cc: 00000513 li a0,0 -800113d0: 00000713 li a4,0 -800113d4: 00100793 li a5,1 -800113d8: e6dff06f j 80011244 <__divdf3+0x53c> -800113dc: 000f8613 mv a2,t6 -800113e0: 00060f93 mv t6,a2 -800113e4: e01ff06f j 800111e4 <__divdf3+0x4dc> +80010fe0: ffef8493 addi s1,t6,-2 +80010fe4: 00e40433 add s0,s0,a4 +80010fe8: 41078833 sub a6,a5,a6 +80010fec: 40c40433 sub s0,s0,a2 +80010ff0: 0107b7b3 sltu a5,a5,a6 +80010ff4: 40f40433 sub s0,s0,a5 +80010ff8: fff00f93 li t6,-1 +80010ffc: 12888463 beq a7,s0,80011124 <__divdf3+0x4e0> +80011000: 02a45fb3 divu t6,s0,a0 +80011004: 01085713 srli a4,a6,0x10 +80011008: 02a47433 remu s0,s0,a0 +8001100c: 000f8613 mv a2,t6 +80011010: 03fe87b3 mul a5,t4,t6 +80011014: 01041413 slli s0,s0,0x10 +80011018: 00876433 or s0,a4,s0 +8001101c: 00f47e63 bgeu s0,a5,80011038 <__divdf3+0x3f4> +80011020: 01140433 add s0,s0,a7 +80011024: ffff8613 addi a2,t6,-1 +80011028: 01146863 bltu s0,a7,80011038 <__divdf3+0x3f4> +8001102c: 00f47663 bgeu s0,a5,80011038 <__divdf3+0x3f4> +80011030: ffef8613 addi a2,t6,-2 +80011034: 01140433 add s0,s0,a7 +80011038: 40f40433 sub s0,s0,a5 +8001103c: 02a45733 divu a4,s0,a0 +80011040: 01081813 slli a6,a6,0x10 +80011044: 01085813 srli a6,a6,0x10 +80011048: 02a47433 remu s0,s0,a0 +8001104c: 00070793 mv a5,a4 +80011050: 02ee8eb3 mul t4,t4,a4 +80011054: 01041413 slli s0,s0,0x10 +80011058: 00886433 or s0,a6,s0 +8001105c: 01d47e63 bgeu s0,t4,80011078 <__divdf3+0x434> +80011060: 01140433 add s0,s0,a7 +80011064: fff70793 addi a5,a4,-1 +80011068: 01146863 bltu s0,a7,80011078 <__divdf3+0x434> +8001106c: 01d47663 bgeu s0,t4,80011078 <__divdf3+0x434> +80011070: ffe70793 addi a5,a4,-2 +80011074: 01140433 add s0,s0,a7 +80011078: 01061613 slli a2,a2,0x10 +8001107c: 00f66633 or a2,a2,a5 +80011080: 01061793 slli a5,a2,0x10 +80011084: 0107d793 srli a5,a5,0x10 +80011088: 01065713 srli a4,a2,0x10 +8001108c: 02ef0833 mul a6,t5,a4 +80011090: 41d40433 sub s0,s0,t4 +80011094: 02ff0f33 mul t5,t5,a5 +80011098: 03c78eb3 mul t4,a5,t3 +8001109c: 03c70e33 mul t3,a4,t3 +800110a0: 010ed793 srli a5,t4,0x10 +800110a4: 01cf0f33 add t5,t5,t3 +800110a8: 01e787b3 add a5,a5,t5 +800110ac: 01c7f663 bgeu a5,t3,800110b8 <__divdf3+0x474> +800110b0: 00010737 lui a4,0x10 +800110b4: 00e80833 add a6,a6,a4 +800110b8: 0107d713 srli a4,a5,0x10 +800110bc: 01070733 add a4,a4,a6 +800110c0: 00010837 lui a6,0x10 +800110c4: fff80813 addi a6,a6,-1 # ffff <_start-0x7fff0001> +800110c8: 0107f533 and a0,a5,a6 +800110cc: 01051513 slli a0,a0,0x10 +800110d0: 010efeb3 and t4,t4,a6 +800110d4: 01d50533 add a0,a0,t4 +800110d8: 00e46863 bltu s0,a4,800110e8 <__divdf3+0x4a4> +800110dc: 24e41063 bne s0,a4,8001131c <__divdf3+0x6d8> +800110e0: 00060f93 mv t6,a2 +800110e4: 04050063 beqz a0,80011124 <__divdf3+0x4e0> +800110e8: 00888433 add s0,a7,s0 +800110ec: fff60f93 addi t6,a2,-1 # ffffff <_start-0x7f000001> +800110f0: 03146463 bltu s0,a7,80011118 <__divdf3+0x4d4> +800110f4: 00e46663 bltu s0,a4,80011100 <__divdf3+0x4bc> +800110f8: 22e41063 bne s0,a4,80011318 <__divdf3+0x6d4> +800110fc: 02a37063 bgeu t1,a0,8001111c <__divdf3+0x4d8> +80011100: 00131793 slli a5,t1,0x1 +80011104: 0067b333 sltu t1,a5,t1 +80011108: 011308b3 add a7,t1,a7 +8001110c: ffe60f93 addi t6,a2,-2 +80011110: 01140433 add s0,s0,a7 +80011114: 00078313 mv t1,a5 +80011118: 00e41463 bne s0,a4,80011120 <__divdf3+0x4dc> +8001111c: 00650463 beq a0,t1,80011124 <__divdf3+0x4e0> +80011120: 001fef93 ori t6,t6,1 +80011124: 3ff58793 addi a5,a1,1023 +80011128: 10f05863 blez a5,80011238 <__divdf3+0x5f4> +8001112c: 007ff713 andi a4,t6,7 +80011130: 02070063 beqz a4,80011150 <__divdf3+0x50c> +80011134: 00fff713 andi a4,t6,15 +80011138: 00400613 li a2,4 +8001113c: 00c70a63 beq a4,a2,80011150 <__divdf3+0x50c> +80011140: 004f8613 addi a2,t6,4 +80011144: 01f63fb3 sltu t6,a2,t6 +80011148: 01f484b3 add s1,s1,t6 +8001114c: 00060f93 mv t6,a2 +80011150: 00749713 slli a4,s1,0x7 +80011154: 00075a63 bgez a4,80011168 <__divdf3+0x524> +80011158: ff0007b7 lui a5,0xff000 +8001115c: fff78793 addi a5,a5,-1 # feffffff <__BSS_END__+0x7efe93c3> +80011160: 00f4f4b3 and s1,s1,a5 +80011164: 40058793 addi a5,a1,1024 +80011168: 7fe00713 li a4,2046 +8001116c: 0af74063 blt a4,a5,8001120c <__divdf3+0x5c8> +80011170: 003fdf93 srli t6,t6,0x3 +80011174: 01d49713 slli a4,s1,0x1d +80011178: 01f76733 or a4,a4,t6 +8001117c: 0034d513 srli a0,s1,0x3 +80011180: 01479793 slli a5,a5,0x14 +80011184: 7ff00637 lui a2,0x7ff00 +80011188: 00c51513 slli a0,a0,0xc +8001118c: 02c12083 lw ra,44(sp) +80011190: 02812403 lw s0,40(sp) +80011194: 00c7f7b3 and a5,a5,a2 +80011198: 00c55513 srli a0,a0,0xc +8001119c: 00a7e533 or a0,a5,a0 +800111a0: 01f69693 slli a3,a3,0x1f +800111a4: 00d567b3 or a5,a0,a3 +800111a8: 02412483 lw s1,36(sp) +800111ac: 02012903 lw s2,32(sp) +800111b0: 01c12983 lw s3,28(sp) +800111b4: 01812a03 lw s4,24(sp) +800111b8: 01412a83 lw s5,20(sp) +800111bc: 01012b03 lw s6,16(sp) +800111c0: 00c12b83 lw s7,12(sp) +800111c4: 00812c03 lw s8,8(sp) +800111c8: 00070513 mv a0,a4 +800111cc: 00078593 mv a1,a5 +800111d0: 03010113 addi sp,sp,48 +800111d4: 00008067 ret +800111d8: fff58593 addi a1,a1,-1 +800111dc: 00000793 li a5,0 +800111e0: cbdff06f j 80010e9c <__divdf3+0x258> +800111e4: 000a0693 mv a3,s4 +800111e8: 00098493 mv s1,s3 +800111ec: 00040f93 mv t6,s0 +800111f0: 000b8613 mv a2,s7 +800111f4: 00300793 li a5,3 +800111f8: 0ef60863 beq a2,a5,800112e8 <__divdf3+0x6a4> +800111fc: 00100793 li a5,1 +80011200: 0ef60e63 beq a2,a5,800112fc <__divdf3+0x6b8> +80011204: 00200793 li a5,2 +80011208: f0f61ee3 bne a2,a5,80011124 <__divdf3+0x4e0> +8001120c: 00000513 li a0,0 +80011210: 00000713 li a4,0 +80011214: 7ff00793 li a5,2047 +80011218: f69ff06f j 80011180 <__divdf3+0x53c> +8001121c: 000c0693 mv a3,s8 +80011220: fd5ff06f j 800111f4 <__divdf3+0x5b0> +80011224: 000804b7 lui s1,0x80 +80011228: 00000f93 li t6,0 +8001122c: 00000693 li a3,0 +80011230: 00300613 li a2,3 +80011234: fc1ff06f j 800111f4 <__divdf3+0x5b0> +80011238: 00100513 li a0,1 +8001123c: 40f50533 sub a0,a0,a5 +80011240: 03800713 li a4,56 +80011244: 0aa74c63 blt a4,a0,800112fc <__divdf3+0x6b8> +80011248: 01f00713 li a4,31 +8001124c: 06a74463 blt a4,a0,800112b4 <__divdf3+0x670> +80011250: 41e58593 addi a1,a1,1054 +80011254: 00b497b3 sll a5,s1,a1 +80011258: 00afd733 srl a4,t6,a0 +8001125c: 00bf95b3 sll a1,t6,a1 +80011260: 00e7e7b3 or a5,a5,a4 +80011264: 00b035b3 snez a1,a1 +80011268: 00b7e7b3 or a5,a5,a1 +8001126c: 00a4d533 srl a0,s1,a0 +80011270: 0077f713 andi a4,a5,7 +80011274: 02070063 beqz a4,80011294 <__divdf3+0x650> +80011278: 00f7f713 andi a4,a5,15 +8001127c: 00400613 li a2,4 +80011280: 00c70a63 beq a4,a2,80011294 <__divdf3+0x650> +80011284: 00478713 addi a4,a5,4 +80011288: 00f737b3 sltu a5,a4,a5 +8001128c: 00f50533 add a0,a0,a5 +80011290: 00070793 mv a5,a4 +80011294: 00851713 slli a4,a0,0x8 +80011298: 06074863 bltz a4,80011308 <__divdf3+0x6c4> +8001129c: 01d51713 slli a4,a0,0x1d +800112a0: 0037d793 srli a5,a5,0x3 +800112a4: 00f76733 or a4,a4,a5 +800112a8: 00355513 srli a0,a0,0x3 +800112ac: 00000793 li a5,0 +800112b0: ed1ff06f j 80011180 <__divdf3+0x53c> +800112b4: fe100713 li a4,-31 +800112b8: 40f707b3 sub a5,a4,a5 +800112bc: 02000613 li a2,32 +800112c0: 00f4d7b3 srl a5,s1,a5 +800112c4: 00000713 li a4,0 +800112c8: 00c50663 beq a0,a2,800112d4 <__divdf3+0x690> +800112cc: 43e58593 addi a1,a1,1086 +800112d0: 00b49733 sll a4,s1,a1 +800112d4: 01f76fb3 or t6,a4,t6 +800112d8: 01f03fb3 snez t6,t6 +800112dc: 01f7e7b3 or a5,a5,t6 +800112e0: 00000513 li a0,0 +800112e4: f8dff06f j 80011270 <__divdf3+0x62c> +800112e8: 00080537 lui a0,0x80 +800112ec: 00000713 li a4,0 +800112f0: 7ff00793 li a5,2047 +800112f4: 00000693 li a3,0 +800112f8: e89ff06f j 80011180 <__divdf3+0x53c> +800112fc: 00000513 li a0,0 +80011300: 00000713 li a4,0 +80011304: fa9ff06f j 800112ac <__divdf3+0x668> +80011308: 00000513 li a0,0 +8001130c: 00000713 li a4,0 +80011310: 00100793 li a5,1 +80011314: e6dff06f j 80011180 <__divdf3+0x53c> +80011318: 000f8613 mv a2,t6 +8001131c: 00060f93 mv t6,a2 +80011320: e01ff06f j 80011120 <__divdf3+0x4dc> -800113e8 <__muldf3>: -800113e8: fd010113 addi sp,sp,-48 -800113ec: 0145d793 srli a5,a1,0x14 -800113f0: 02812423 sw s0,40(sp) -800113f4: 02912223 sw s1,36(sp) -800113f8: 01312e23 sw s3,28(sp) -800113fc: 01412c23 sw s4,24(sp) -80011400: 01512a23 sw s5,20(sp) -80011404: 00c59493 slli s1,a1,0xc -80011408: 02112623 sw ra,44(sp) -8001140c: 03212023 sw s2,32(sp) -80011410: 01612823 sw s6,16(sp) -80011414: 01712623 sw s7,12(sp) -80011418: 01579713 slli a4,a5,0x15 -8001141c: 00050413 mv s0,a0 -80011420: 00060993 mv s3,a2 -80011424: 00068a93 mv s5,a3 -80011428: 00c4d493 srli s1,s1,0xc -8001142c: 01f5da13 srli s4,a1,0x1f -80011430: 0a070663 beqz a4,800114dc <__muldf3+0xf4> -80011434: 7ff7fb13 andi s6,a5,2047 -80011438: 7ff00793 li a5,2047 -8001143c: 10fb0263 beq s6,a5,80011540 <__muldf3+0x158> -80011440: 01d55793 srli a5,a0,0x1d -80011444: 00349493 slli s1,s1,0x3 -80011448: 0097e4b3 or s1,a5,s1 -8001144c: 008007b7 lui a5,0x800 -80011450: 00f4e4b3 or s1,s1,a5 -80011454: 00351913 slli s2,a0,0x3 -80011458: c01b0b13 addi s6,s6,-1023 -8001145c: 00000b93 li s7,0 -80011460: 014ad793 srli a5,s5,0x14 -80011464: 00ca9413 slli s0,s5,0xc -80011468: 01579713 slli a4,a5,0x15 -8001146c: 00c45413 srli s0,s0,0xc -80011470: 7ff7f513 andi a0,a5,2047 -80011474: 01fada93 srli s5,s5,0x1f -80011478: 10070063 beqz a4,80011578 <__muldf3+0x190> -8001147c: 7ff00793 li a5,2047 -80011480: 16f50063 beq a0,a5,800115e0 <__muldf3+0x1f8> -80011484: 01d9d793 srli a5,s3,0x1d -80011488: 00341413 slli s0,s0,0x3 -8001148c: 0087e433 or s0,a5,s0 -80011490: 008007b7 lui a5,0x800 -80011494: 00f46433 or s0,s0,a5 -80011498: c0150513 addi a0,a0,-1023 # 7fc01 <_start-0x7ff803ff> -8001149c: 00399793 slli a5,s3,0x3 -800114a0: 00000713 li a4,0 -800114a4: 002b9693 slli a3,s7,0x2 -800114a8: 00e6e6b3 or a3,a3,a4 -800114ac: 00ab0533 add a0,s6,a0 -800114b0: fff68693 addi a3,a3,-1 -800114b4: 00e00813 li a6,14 -800114b8: 015a4633 xor a2,s4,s5 -800114bc: 00150593 addi a1,a0,1 -800114c0: 14d86c63 bltu a6,a3,80011618 <__muldf3+0x230> -800114c4: 80015537 lui a0,0x80015 -800114c8: 00269693 slli a3,a3,0x2 -800114cc: 7d450513 addi a0,a0,2004 # 800157d4 <__BSS_END__+0xffffeb98> -800114d0: 00a686b3 add a3,a3,a0 -800114d4: 0006a683 lw a3,0(a3) -800114d8: 00068067 jr a3 -800114dc: 00a4e933 or s2,s1,a0 -800114e0: 06090c63 beqz s2,80011558 <__muldf3+0x170> -800114e4: 04048063 beqz s1,80011524 <__muldf3+0x13c> -800114e8: 00048513 mv a0,s1 -800114ec: 4dc030ef jal ra,800149c8 <__clzsi2> -800114f0: ff550713 addi a4,a0,-11 -800114f4: 01c00793 li a5,28 -800114f8: 02e7cc63 blt a5,a4,80011530 <__muldf3+0x148> -800114fc: 01d00793 li a5,29 -80011500: ff850913 addi s2,a0,-8 -80011504: 40e787b3 sub a5,a5,a4 -80011508: 012494b3 sll s1,s1,s2 -8001150c: 00f457b3 srl a5,s0,a5 -80011510: 0097e4b3 or s1,a5,s1 -80011514: 01241933 sll s2,s0,s2 -80011518: c0d00b13 li s6,-1011 -8001151c: 40ab0b33 sub s6,s6,a0 -80011520: f3dff06f j 8001145c <__muldf3+0x74> -80011524: 4a4030ef jal ra,800149c8 <__clzsi2> -80011528: 02050513 addi a0,a0,32 -8001152c: fc5ff06f j 800114f0 <__muldf3+0x108> -80011530: fd850493 addi s1,a0,-40 -80011534: 009414b3 sll s1,s0,s1 -80011538: 00000913 li s2,0 -8001153c: fddff06f j 80011518 <__muldf3+0x130> -80011540: 00a4e933 or s2,s1,a0 -80011544: 02090263 beqz s2,80011568 <__muldf3+0x180> -80011548: 00050913 mv s2,a0 -8001154c: 7ff00b13 li s6,2047 -80011550: 00300b93 li s7,3 -80011554: f0dff06f j 80011460 <__muldf3+0x78> -80011558: 00000493 li s1,0 -8001155c: 00000b13 li s6,0 -80011560: 00100b93 li s7,1 -80011564: efdff06f j 80011460 <__muldf3+0x78> -80011568: 00000493 li s1,0 -8001156c: 7ff00b13 li s6,2047 -80011570: 00200b93 li s7,2 -80011574: eedff06f j 80011460 <__muldf3+0x78> -80011578: 013467b3 or a5,s0,s3 -8001157c: 06078e63 beqz a5,800115f8 <__muldf3+0x210> -80011580: 04040063 beqz s0,800115c0 <__muldf3+0x1d8> -80011584: 00040513 mv a0,s0 -80011588: 440030ef jal ra,800149c8 <__clzsi2> -8001158c: ff550693 addi a3,a0,-11 -80011590: 01c00793 li a5,28 -80011594: 02d7ce63 blt a5,a3,800115d0 <__muldf3+0x1e8> -80011598: 01d00713 li a4,29 -8001159c: ff850793 addi a5,a0,-8 -800115a0: 40d70733 sub a4,a4,a3 -800115a4: 00f41433 sll s0,s0,a5 -800115a8: 00e9d733 srl a4,s3,a4 -800115ac: 00876433 or s0,a4,s0 -800115b0: 00f997b3 sll a5,s3,a5 -800115b4: c0d00713 li a4,-1011 -800115b8: 40a70533 sub a0,a4,a0 -800115bc: ee5ff06f j 800114a0 <__muldf3+0xb8> -800115c0: 00098513 mv a0,s3 -800115c4: 404030ef jal ra,800149c8 <__clzsi2> -800115c8: 02050513 addi a0,a0,32 -800115cc: fc1ff06f j 8001158c <__muldf3+0x1a4> -800115d0: fd850413 addi s0,a0,-40 -800115d4: 00899433 sll s0,s3,s0 -800115d8: 00000793 li a5,0 -800115dc: fd9ff06f j 800115b4 <__muldf3+0x1cc> -800115e0: 013467b3 or a5,s0,s3 -800115e4: 02078263 beqz a5,80011608 <__muldf3+0x220> -800115e8: 00098793 mv a5,s3 -800115ec: 7ff00513 li a0,2047 -800115f0: 00300713 li a4,3 -800115f4: eb1ff06f j 800114a4 <__muldf3+0xbc> -800115f8: 00000413 li s0,0 -800115fc: 00000513 li a0,0 -80011600: 00100713 li a4,1 -80011604: ea1ff06f j 800114a4 <__muldf3+0xbc> -80011608: 00000413 li s0,0 -8001160c: 7ff00513 li a0,2047 -80011610: 00200713 li a4,2 -80011614: e91ff06f j 800114a4 <__muldf3+0xbc> -80011618: 00010f37 lui t5,0x10 -8001161c: ffff0713 addi a4,t5,-1 # ffff <_start-0x7fff0001> -80011620: 01095693 srli a3,s2,0x10 -80011624: 0107d313 srli t1,a5,0x10 -80011628: 00e97933 and s2,s2,a4 -8001162c: 00e7f7b3 and a5,a5,a4 -80011630: 032308b3 mul a7,t1,s2 -80011634: 02f90833 mul a6,s2,a5 -80011638: 02f68fb3 mul t6,a3,a5 -8001163c: 01f88eb3 add t4,a7,t6 -80011640: 01085893 srli a7,a6,0x10 -80011644: 01d888b3 add a7,a7,t4 -80011648: 02668e33 mul t3,a3,t1 -8001164c: 01f8f463 bgeu a7,t6,80011654 <__muldf3+0x26c> -80011650: 01ee0e33 add t3,t3,t5 -80011654: 0108d293 srli t0,a7,0x10 -80011658: 00e8f8b3 and a7,a7,a4 -8001165c: 00e87833 and a6,a6,a4 -80011660: 01045f13 srli t5,s0,0x10 -80011664: 01089893 slli a7,a7,0x10 -80011668: 00e47433 and s0,s0,a4 -8001166c: 010888b3 add a7,a7,a6 -80011670: 02868733 mul a4,a3,s0 -80011674: 02890833 mul a6,s2,s0 -80011678: 032f0933 mul s2,t5,s2 -8001167c: 00e90eb3 add t4,s2,a4 -80011680: 01085913 srli s2,a6,0x10 -80011684: 01d90933 add s2,s2,t4 -80011688: 03e686b3 mul a3,a3,t5 -8001168c: 00e97663 bgeu s2,a4,80011698 <__muldf3+0x2b0> -80011690: 00010737 lui a4,0x10 -80011694: 00e686b3 add a3,a3,a4 -80011698: 01095e93 srli t4,s2,0x10 -8001169c: 00de8eb3 add t4,t4,a3 -800116a0: 000106b7 lui a3,0x10 -800116a4: fff68f93 addi t6,a3,-1 # ffff <_start-0x7fff0001> -800116a8: 01f97933 and s2,s2,t6 -800116ac: 01f87833 and a6,a6,t6 -800116b0: 0104d713 srli a4,s1,0x10 -800116b4: 01091913 slli s2,s2,0x10 -800116b8: 01f4f4b3 and s1,s1,t6 -800116bc: 029783b3 mul t2,a5,s1 -800116c0: 01090933 add s2,s2,a6 -800116c4: 012282b3 add t0,t0,s2 -800116c8: 02930833 mul a6,t1,s1 -800116cc: 02f707b3 mul a5,a4,a5 -800116d0: 02e30fb3 mul t6,t1,a4 -800116d4: 00f80333 add t1,a6,a5 -800116d8: 0103d813 srli a6,t2,0x10 -800116dc: 00680833 add a6,a6,t1 -800116e0: 00f87463 bgeu a6,a5,800116e8 <__muldf3+0x300> -800116e4: 00df8fb3 add t6,t6,a3 -800116e8: 01085793 srli a5,a6,0x10 -800116ec: 000106b7 lui a3,0x10 -800116f0: 01f78fb3 add t6,a5,t6 -800116f4: fff68793 addi a5,a3,-1 # ffff <_start-0x7fff0001> -800116f8: 00f87833 and a6,a6,a5 -800116fc: 00f3f7b3 and a5,t2,a5 -80011700: 029403b3 mul t2,s0,s1 -80011704: 01081813 slli a6,a6,0x10 -80011708: 00f80833 add a6,a6,a5 -8001170c: 02870433 mul s0,a4,s0 -80011710: 029f04b3 mul s1,t5,s1 -80011714: 02ef0333 mul t1,t5,a4 -80011718: 008484b3 add s1,s1,s0 -8001171c: 0103d713 srli a4,t2,0x10 -80011720: 009704b3 add s1,a4,s1 -80011724: 0084f463 bgeu s1,s0,8001172c <__muldf3+0x344> -80011728: 00d30333 add t1,t1,a3 -8001172c: 000107b7 lui a5,0x10 -80011730: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> -80011734: 00f4f6b3 and a3,s1,a5 -80011738: 01069693 slli a3,a3,0x10 -8001173c: 00f3f7b3 and a5,t2,a5 -80011740: 005e0e33 add t3,t3,t0 -80011744: 00f686b3 add a3,a3,a5 -80011748: 012e3933 sltu s2,t3,s2 -8001174c: 01d686b3 add a3,a3,t4 -80011750: 01268733 add a4,a3,s2 -80011754: 010e0e33 add t3,t3,a6 -80011758: 010e3833 sltu a6,t3,a6 -8001175c: 01f70f33 add t5,a4,t6 -80011760: 010f02b3 add t0,t5,a6 -80011764: 01d6b6b3 sltu a3,a3,t4 -80011768: 01273733 sltu a4,a4,s2 -8001176c: 00e6e733 or a4,a3,a4 -80011770: 0102b833 sltu a6,t0,a6 -80011774: 0104d493 srli s1,s1,0x10 -80011778: 01ff3fb3 sltu t6,t5,t6 -8001177c: 00970733 add a4,a4,s1 -80011780: 010fe833 or a6,t6,a6 -80011784: 009e1793 slli a5,t3,0x9 -80011788: 01070733 add a4,a4,a6 -8001178c: 00670733 add a4,a4,t1 -80011790: 0117e7b3 or a5,a5,a7 -80011794: 00971713 slli a4,a4,0x9 -80011798: 00f037b3 snez a5,a5 -8001179c: 017e5e13 srli t3,t3,0x17 -800117a0: 0172d413 srli s0,t0,0x17 -800117a4: 01c7e7b3 or a5,a5,t3 -800117a8: 00929293 slli t0,t0,0x9 -800117ac: 00771693 slli a3,a4,0x7 -800117b0: 00876433 or s0,a4,s0 -800117b4: 0057e7b3 or a5,a5,t0 -800117b8: 1006d463 bgez a3,800118c0 <__muldf3+0x4d8> -800117bc: 0017d713 srli a4,a5,0x1 -800117c0: 0017f793 andi a5,a5,1 -800117c4: 00f767b3 or a5,a4,a5 -800117c8: 01f41713 slli a4,s0,0x1f -800117cc: 00e7e7b3 or a5,a5,a4 -800117d0: 00145413 srli s0,s0,0x1 -800117d4: 3ff58693 addi a3,a1,1023 -800117d8: 0ed05863 blez a3,800118c8 <__muldf3+0x4e0> -800117dc: 0077f713 andi a4,a5,7 -800117e0: 02070063 beqz a4,80011800 <__muldf3+0x418> -800117e4: 00f7f713 andi a4,a5,15 -800117e8: 00400513 li a0,4 -800117ec: 00a70a63 beq a4,a0,80011800 <__muldf3+0x418> -800117f0: 00478713 addi a4,a5,4 -800117f4: 00f737b3 sltu a5,a4,a5 -800117f8: 00f40433 add s0,s0,a5 -800117fc: 00070793 mv a5,a4 -80011800: 00741713 slli a4,s0,0x7 -80011804: 00075a63 bgez a4,80011818 <__muldf3+0x430> -80011808: ff000737 lui a4,0xff000 -8001180c: fff70713 addi a4,a4,-1 # feffffff <__BSS_END__+0x7efe93c3> -80011810: 00e47433 and s0,s0,a4 -80011814: 40058693 addi a3,a1,1024 -80011818: 7fe00713 li a4,2046 -8001181c: 16d74863 blt a4,a3,8001198c <__muldf3+0x5a4> -80011820: 0037d713 srli a4,a5,0x3 -80011824: 01d41793 slli a5,s0,0x1d -80011828: 00e7e7b3 or a5,a5,a4 -8001182c: 00345413 srli s0,s0,0x3 -80011830: 01469713 slli a4,a3,0x14 -80011834: 00c41413 slli s0,s0,0xc -80011838: 7ff006b7 lui a3,0x7ff00 -8001183c: 00d77733 and a4,a4,a3 -80011840: 00c45413 srli s0,s0,0xc -80011844: 00876433 or s0,a4,s0 -80011848: 01f61613 slli a2,a2,0x1f -8001184c: 02c12083 lw ra,44(sp) -80011850: 00c46733 or a4,s0,a2 -80011854: 02812403 lw s0,40(sp) -80011858: 02412483 lw s1,36(sp) -8001185c: 02012903 lw s2,32(sp) -80011860: 01c12983 lw s3,28(sp) -80011864: 01812a03 lw s4,24(sp) -80011868: 01412a83 lw s5,20(sp) -8001186c: 01012b03 lw s6,16(sp) -80011870: 00c12b83 lw s7,12(sp) -80011874: 00078513 mv a0,a5 -80011878: 00070593 mv a1,a4 -8001187c: 03010113 addi sp,sp,48 -80011880: 00008067 ret -80011884: 000a0613 mv a2,s4 -80011888: 00048413 mv s0,s1 -8001188c: 00090793 mv a5,s2 -80011890: 000b8713 mv a4,s7 -80011894: 00200693 li a3,2 -80011898: 0ed70a63 beq a4,a3,8001198c <__muldf3+0x5a4> -8001189c: 00300693 li a3,3 -800118a0: 0cd70c63 beq a4,a3,80011978 <__muldf3+0x590> -800118a4: 00100693 li a3,1 -800118a8: f2d716e3 bne a4,a3,800117d4 <__muldf3+0x3ec> +80011324 <__muldf3>: +80011324: fd010113 addi sp,sp,-48 +80011328: 0145d793 srli a5,a1,0x14 +8001132c: 02812423 sw s0,40(sp) +80011330: 02912223 sw s1,36(sp) +80011334: 01312e23 sw s3,28(sp) +80011338: 01412c23 sw s4,24(sp) +8001133c: 01512a23 sw s5,20(sp) +80011340: 00c59493 slli s1,a1,0xc +80011344: 02112623 sw ra,44(sp) +80011348: 03212023 sw s2,32(sp) +8001134c: 01612823 sw s6,16(sp) +80011350: 01712623 sw s7,12(sp) +80011354: 01579713 slli a4,a5,0x15 +80011358: 00050413 mv s0,a0 +8001135c: 00060993 mv s3,a2 +80011360: 00068a93 mv s5,a3 +80011364: 00c4d493 srli s1,s1,0xc +80011368: 01f5da13 srli s4,a1,0x1f +8001136c: 0a070663 beqz a4,80011418 <__muldf3+0xf4> +80011370: 7ff7fb13 andi s6,a5,2047 +80011374: 7ff00793 li a5,2047 +80011378: 10fb0263 beq s6,a5,8001147c <__muldf3+0x158> +8001137c: 01d55793 srli a5,a0,0x1d +80011380: 00349493 slli s1,s1,0x3 +80011384: 0097e4b3 or s1,a5,s1 +80011388: 008007b7 lui a5,0x800 +8001138c: 00f4e4b3 or s1,s1,a5 +80011390: 00351913 slli s2,a0,0x3 +80011394: c01b0b13 addi s6,s6,-1023 +80011398: 00000b93 li s7,0 +8001139c: 014ad793 srli a5,s5,0x14 +800113a0: 00ca9413 slli s0,s5,0xc +800113a4: 01579713 slli a4,a5,0x15 +800113a8: 00c45413 srli s0,s0,0xc +800113ac: 7ff7f513 andi a0,a5,2047 +800113b0: 01fada93 srli s5,s5,0x1f +800113b4: 10070063 beqz a4,800114b4 <__muldf3+0x190> +800113b8: 7ff00793 li a5,2047 +800113bc: 16f50063 beq a0,a5,8001151c <__muldf3+0x1f8> +800113c0: 01d9d793 srli a5,s3,0x1d +800113c4: 00341413 slli s0,s0,0x3 +800113c8: 0087e433 or s0,a5,s0 +800113cc: 008007b7 lui a5,0x800 +800113d0: 00f46433 or s0,s0,a5 +800113d4: c0150513 addi a0,a0,-1023 # 7fc01 <_start-0x7ff803ff> +800113d8: 00399793 slli a5,s3,0x3 +800113dc: 00000713 li a4,0 +800113e0: 002b9693 slli a3,s7,0x2 +800113e4: 00e6e6b3 or a3,a3,a4 +800113e8: 00ab0533 add a0,s6,a0 +800113ec: fff68693 addi a3,a3,-1 +800113f0: 00e00813 li a6,14 +800113f4: 015a4633 xor a2,s4,s5 +800113f8: 00150593 addi a1,a0,1 +800113fc: 14d86c63 bltu a6,a3,80011554 <__muldf3+0x230> +80011400: 80015537 lui a0,0x80015 +80011404: 00269693 slli a3,a3,0x2 +80011408: 6fc50513 addi a0,a0,1788 # 800156fc <__BSS_END__+0xffffeac0> +8001140c: 00a686b3 add a3,a3,a0 +80011410: 0006a683 lw a3,0(a3) +80011414: 00068067 jr a3 +80011418: 00a4e933 or s2,s1,a0 +8001141c: 06090c63 beqz s2,80011494 <__muldf3+0x170> +80011420: 04048063 beqz s1,80011460 <__muldf3+0x13c> +80011424: 00048513 mv a0,s1 +80011428: 4dc030ef jal ra,80014904 <__clzsi2> +8001142c: ff550713 addi a4,a0,-11 +80011430: 01c00793 li a5,28 +80011434: 02e7cc63 blt a5,a4,8001146c <__muldf3+0x148> +80011438: 01d00793 li a5,29 +8001143c: ff850913 addi s2,a0,-8 +80011440: 40e787b3 sub a5,a5,a4 +80011444: 012494b3 sll s1,s1,s2 +80011448: 00f457b3 srl a5,s0,a5 +8001144c: 0097e4b3 or s1,a5,s1 +80011450: 01241933 sll s2,s0,s2 +80011454: c0d00b13 li s6,-1011 +80011458: 40ab0b33 sub s6,s6,a0 +8001145c: f3dff06f j 80011398 <__muldf3+0x74> +80011460: 4a4030ef jal ra,80014904 <__clzsi2> +80011464: 02050513 addi a0,a0,32 +80011468: fc5ff06f j 8001142c <__muldf3+0x108> +8001146c: fd850493 addi s1,a0,-40 +80011470: 009414b3 sll s1,s0,s1 +80011474: 00000913 li s2,0 +80011478: fddff06f j 80011454 <__muldf3+0x130> +8001147c: 00a4e933 or s2,s1,a0 +80011480: 02090263 beqz s2,800114a4 <__muldf3+0x180> +80011484: 00050913 mv s2,a0 +80011488: 7ff00b13 li s6,2047 +8001148c: 00300b93 li s7,3 +80011490: f0dff06f j 8001139c <__muldf3+0x78> +80011494: 00000493 li s1,0 +80011498: 00000b13 li s6,0 +8001149c: 00100b93 li s7,1 +800114a0: efdff06f j 8001139c <__muldf3+0x78> +800114a4: 00000493 li s1,0 +800114a8: 7ff00b13 li s6,2047 +800114ac: 00200b93 li s7,2 +800114b0: eedff06f j 8001139c <__muldf3+0x78> +800114b4: 013467b3 or a5,s0,s3 +800114b8: 06078e63 beqz a5,80011534 <__muldf3+0x210> +800114bc: 04040063 beqz s0,800114fc <__muldf3+0x1d8> +800114c0: 00040513 mv a0,s0 +800114c4: 440030ef jal ra,80014904 <__clzsi2> +800114c8: ff550693 addi a3,a0,-11 +800114cc: 01c00793 li a5,28 +800114d0: 02d7ce63 blt a5,a3,8001150c <__muldf3+0x1e8> +800114d4: 01d00713 li a4,29 +800114d8: ff850793 addi a5,a0,-8 +800114dc: 40d70733 sub a4,a4,a3 +800114e0: 00f41433 sll s0,s0,a5 +800114e4: 00e9d733 srl a4,s3,a4 +800114e8: 00876433 or s0,a4,s0 +800114ec: 00f997b3 sll a5,s3,a5 +800114f0: c0d00713 li a4,-1011 +800114f4: 40a70533 sub a0,a4,a0 +800114f8: ee5ff06f j 800113dc <__muldf3+0xb8> +800114fc: 00098513 mv a0,s3 +80011500: 404030ef jal ra,80014904 <__clzsi2> +80011504: 02050513 addi a0,a0,32 +80011508: fc1ff06f j 800114c8 <__muldf3+0x1a4> +8001150c: fd850413 addi s0,a0,-40 +80011510: 00899433 sll s0,s3,s0 +80011514: 00000793 li a5,0 +80011518: fd9ff06f j 800114f0 <__muldf3+0x1cc> +8001151c: 013467b3 or a5,s0,s3 +80011520: 02078263 beqz a5,80011544 <__muldf3+0x220> +80011524: 00098793 mv a5,s3 +80011528: 7ff00513 li a0,2047 +8001152c: 00300713 li a4,3 +80011530: eb1ff06f j 800113e0 <__muldf3+0xbc> +80011534: 00000413 li s0,0 +80011538: 00000513 li a0,0 +8001153c: 00100713 li a4,1 +80011540: ea1ff06f j 800113e0 <__muldf3+0xbc> +80011544: 00000413 li s0,0 +80011548: 7ff00513 li a0,2047 +8001154c: 00200713 li a4,2 +80011550: e91ff06f j 800113e0 <__muldf3+0xbc> +80011554: 00010f37 lui t5,0x10 +80011558: ffff0713 addi a4,t5,-1 # ffff <_start-0x7fff0001> +8001155c: 01095693 srli a3,s2,0x10 +80011560: 0107d313 srli t1,a5,0x10 +80011564: 00e97933 and s2,s2,a4 +80011568: 00e7f7b3 and a5,a5,a4 +8001156c: 032308b3 mul a7,t1,s2 +80011570: 02f90833 mul a6,s2,a5 +80011574: 02f68fb3 mul t6,a3,a5 +80011578: 01f88eb3 add t4,a7,t6 +8001157c: 01085893 srli a7,a6,0x10 +80011580: 01d888b3 add a7,a7,t4 +80011584: 02668e33 mul t3,a3,t1 +80011588: 01f8f463 bgeu a7,t6,80011590 <__muldf3+0x26c> +8001158c: 01ee0e33 add t3,t3,t5 +80011590: 0108d293 srli t0,a7,0x10 +80011594: 00e8f8b3 and a7,a7,a4 +80011598: 00e87833 and a6,a6,a4 +8001159c: 01045f13 srli t5,s0,0x10 +800115a0: 01089893 slli a7,a7,0x10 +800115a4: 00e47433 and s0,s0,a4 +800115a8: 010888b3 add a7,a7,a6 +800115ac: 02868733 mul a4,a3,s0 +800115b0: 02890833 mul a6,s2,s0 +800115b4: 032f0933 mul s2,t5,s2 +800115b8: 00e90eb3 add t4,s2,a4 +800115bc: 01085913 srli s2,a6,0x10 +800115c0: 01d90933 add s2,s2,t4 +800115c4: 03e686b3 mul a3,a3,t5 +800115c8: 00e97663 bgeu s2,a4,800115d4 <__muldf3+0x2b0> +800115cc: 00010737 lui a4,0x10 +800115d0: 00e686b3 add a3,a3,a4 +800115d4: 01095e93 srli t4,s2,0x10 +800115d8: 00de8eb3 add t4,t4,a3 +800115dc: 000106b7 lui a3,0x10 +800115e0: fff68f93 addi t6,a3,-1 # ffff <_start-0x7fff0001> +800115e4: 01f97933 and s2,s2,t6 +800115e8: 01f87833 and a6,a6,t6 +800115ec: 0104d713 srli a4,s1,0x10 +800115f0: 01091913 slli s2,s2,0x10 +800115f4: 01f4f4b3 and s1,s1,t6 +800115f8: 029783b3 mul t2,a5,s1 +800115fc: 01090933 add s2,s2,a6 +80011600: 012282b3 add t0,t0,s2 +80011604: 02930833 mul a6,t1,s1 +80011608: 02f707b3 mul a5,a4,a5 +8001160c: 02e30fb3 mul t6,t1,a4 +80011610: 00f80333 add t1,a6,a5 +80011614: 0103d813 srli a6,t2,0x10 +80011618: 00680833 add a6,a6,t1 +8001161c: 00f87463 bgeu a6,a5,80011624 <__muldf3+0x300> +80011620: 00df8fb3 add t6,t6,a3 +80011624: 01085793 srli a5,a6,0x10 +80011628: 000106b7 lui a3,0x10 +8001162c: 01f78fb3 add t6,a5,t6 +80011630: fff68793 addi a5,a3,-1 # ffff <_start-0x7fff0001> +80011634: 00f87833 and a6,a6,a5 +80011638: 00f3f7b3 and a5,t2,a5 +8001163c: 029403b3 mul t2,s0,s1 +80011640: 01081813 slli a6,a6,0x10 +80011644: 00f80833 add a6,a6,a5 +80011648: 02870433 mul s0,a4,s0 +8001164c: 029f04b3 mul s1,t5,s1 +80011650: 02ef0333 mul t1,t5,a4 +80011654: 008484b3 add s1,s1,s0 +80011658: 0103d713 srli a4,t2,0x10 +8001165c: 009704b3 add s1,a4,s1 +80011660: 0084f463 bgeu s1,s0,80011668 <__muldf3+0x344> +80011664: 00d30333 add t1,t1,a3 +80011668: 000107b7 lui a5,0x10 +8001166c: fff78793 addi a5,a5,-1 # ffff <_start-0x7fff0001> +80011670: 00f4f6b3 and a3,s1,a5 +80011674: 01069693 slli a3,a3,0x10 +80011678: 00f3f7b3 and a5,t2,a5 +8001167c: 005e0e33 add t3,t3,t0 +80011680: 00f686b3 add a3,a3,a5 +80011684: 012e3933 sltu s2,t3,s2 +80011688: 01d686b3 add a3,a3,t4 +8001168c: 01268733 add a4,a3,s2 +80011690: 010e0e33 add t3,t3,a6 +80011694: 010e3833 sltu a6,t3,a6 +80011698: 01f70f33 add t5,a4,t6 +8001169c: 010f02b3 add t0,t5,a6 +800116a0: 01d6b6b3 sltu a3,a3,t4 +800116a4: 01273733 sltu a4,a4,s2 +800116a8: 00e6e733 or a4,a3,a4 +800116ac: 0102b833 sltu a6,t0,a6 +800116b0: 0104d493 srli s1,s1,0x10 +800116b4: 01ff3fb3 sltu t6,t5,t6 +800116b8: 00970733 add a4,a4,s1 +800116bc: 010fe833 or a6,t6,a6 +800116c0: 009e1793 slli a5,t3,0x9 +800116c4: 01070733 add a4,a4,a6 +800116c8: 00670733 add a4,a4,t1 +800116cc: 0117e7b3 or a5,a5,a7 +800116d0: 00971713 slli a4,a4,0x9 +800116d4: 00f037b3 snez a5,a5 +800116d8: 017e5e13 srli t3,t3,0x17 +800116dc: 0172d413 srli s0,t0,0x17 +800116e0: 01c7e7b3 or a5,a5,t3 +800116e4: 00929293 slli t0,t0,0x9 +800116e8: 00771693 slli a3,a4,0x7 +800116ec: 00876433 or s0,a4,s0 +800116f0: 0057e7b3 or a5,a5,t0 +800116f4: 1006d463 bgez a3,800117fc <__muldf3+0x4d8> +800116f8: 0017d713 srli a4,a5,0x1 +800116fc: 0017f793 andi a5,a5,1 +80011700: 00f767b3 or a5,a4,a5 +80011704: 01f41713 slli a4,s0,0x1f +80011708: 00e7e7b3 or a5,a5,a4 +8001170c: 00145413 srli s0,s0,0x1 +80011710: 3ff58693 addi a3,a1,1023 +80011714: 0ed05863 blez a3,80011804 <__muldf3+0x4e0> +80011718: 0077f713 andi a4,a5,7 +8001171c: 02070063 beqz a4,8001173c <__muldf3+0x418> +80011720: 00f7f713 andi a4,a5,15 +80011724: 00400513 li a0,4 +80011728: 00a70a63 beq a4,a0,8001173c <__muldf3+0x418> +8001172c: 00478713 addi a4,a5,4 +80011730: 00f737b3 sltu a5,a4,a5 +80011734: 00f40433 add s0,s0,a5 +80011738: 00070793 mv a5,a4 +8001173c: 00741713 slli a4,s0,0x7 +80011740: 00075a63 bgez a4,80011754 <__muldf3+0x430> +80011744: ff000737 lui a4,0xff000 +80011748: fff70713 addi a4,a4,-1 # feffffff <__BSS_END__+0x7efe93c3> +8001174c: 00e47433 and s0,s0,a4 +80011750: 40058693 addi a3,a1,1024 +80011754: 7fe00713 li a4,2046 +80011758: 16d74863 blt a4,a3,800118c8 <__muldf3+0x5a4> +8001175c: 0037d713 srli a4,a5,0x3 +80011760: 01d41793 slli a5,s0,0x1d +80011764: 00e7e7b3 or a5,a5,a4 +80011768: 00345413 srli s0,s0,0x3 +8001176c: 01469713 slli a4,a3,0x14 +80011770: 00c41413 slli s0,s0,0xc +80011774: 7ff006b7 lui a3,0x7ff00 +80011778: 00d77733 and a4,a4,a3 +8001177c: 00c45413 srli s0,s0,0xc +80011780: 00876433 or s0,a4,s0 +80011784: 01f61613 slli a2,a2,0x1f +80011788: 02c12083 lw ra,44(sp) +8001178c: 00c46733 or a4,s0,a2 +80011790: 02812403 lw s0,40(sp) +80011794: 02412483 lw s1,36(sp) +80011798: 02012903 lw s2,32(sp) +8001179c: 01c12983 lw s3,28(sp) +800117a0: 01812a03 lw s4,24(sp) +800117a4: 01412a83 lw s5,20(sp) +800117a8: 01012b03 lw s6,16(sp) +800117ac: 00c12b83 lw s7,12(sp) +800117b0: 00078513 mv a0,a5 +800117b4: 00070593 mv a1,a4 +800117b8: 03010113 addi sp,sp,48 +800117bc: 00008067 ret +800117c0: 000a0613 mv a2,s4 +800117c4: 00048413 mv s0,s1 +800117c8: 00090793 mv a5,s2 +800117cc: 000b8713 mv a4,s7 +800117d0: 00200693 li a3,2 +800117d4: 0ed70a63 beq a4,a3,800118c8 <__muldf3+0x5a4> +800117d8: 00300693 li a3,3 +800117dc: 0cd70c63 beq a4,a3,800118b4 <__muldf3+0x590> +800117e0: 00100693 li a3,1 +800117e4: f2d716e3 bne a4,a3,80011710 <__muldf3+0x3ec> +800117e8: 00000413 li s0,0 +800117ec: 00000793 li a5,0 +800117f0: 0880006f j 80011878 <__muldf3+0x554> +800117f4: 000a8613 mv a2,s5 +800117f8: fd9ff06f j 800117d0 <__muldf3+0x4ac> +800117fc: 00050593 mv a1,a0 +80011800: f11ff06f j 80011710 <__muldf3+0x3ec> +80011804: 00100513 li a0,1 +80011808: 40d50533 sub a0,a0,a3 +8001180c: 03800713 li a4,56 +80011810: fca74ce3 blt a4,a0,800117e8 <__muldf3+0x4c4> +80011814: 01f00713 li a4,31 +80011818: 06a74463 blt a4,a0,80011880 <__muldf3+0x55c> +8001181c: 41e58593 addi a1,a1,1054 +80011820: 00b41733 sll a4,s0,a1 +80011824: 00a7d6b3 srl a3,a5,a0 +80011828: 00b797b3 sll a5,a5,a1 +8001182c: 00d76733 or a4,a4,a3 +80011830: 00f037b3 snez a5,a5 +80011834: 00f767b3 or a5,a4,a5 +80011838: 00a45433 srl s0,s0,a0 +8001183c: 0077f713 andi a4,a5,7 +80011840: 02070063 beqz a4,80011860 <__muldf3+0x53c> +80011844: 00f7f713 andi a4,a5,15 +80011848: 00400693 li a3,4 +8001184c: 00d70a63 beq a4,a3,80011860 <__muldf3+0x53c> +80011850: 00478713 addi a4,a5,4 +80011854: 00f737b3 sltu a5,a4,a5 +80011858: 00f40433 add s0,s0,a5 +8001185c: 00070793 mv a5,a4 +80011860: 00841713 slli a4,s0,0x8 +80011864: 06074a63 bltz a4,800118d8 <__muldf3+0x5b4> +80011868: 01d41713 slli a4,s0,0x1d +8001186c: 0037d793 srli a5,a5,0x3 +80011870: 00f767b3 or a5,a4,a5 +80011874: 00345413 srli s0,s0,0x3 +80011878: 00000693 li a3,0 +8001187c: ef1ff06f j 8001176c <__muldf3+0x448> +80011880: fe100713 li a4,-31 +80011884: 40d70733 sub a4,a4,a3 +80011888: 02000813 li a6,32 +8001188c: 00e45733 srl a4,s0,a4 +80011890: 00000693 li a3,0 +80011894: 01050663 beq a0,a6,800118a0 <__muldf3+0x57c> +80011898: 43e58593 addi a1,a1,1086 +8001189c: 00b416b3 sll a3,s0,a1 +800118a0: 00f6e7b3 or a5,a3,a5 +800118a4: 00f037b3 snez a5,a5 +800118a8: 00f767b3 or a5,a4,a5 800118ac: 00000413 li s0,0 -800118b0: 00000793 li a5,0 -800118b4: 0880006f j 8001193c <__muldf3+0x554> -800118b8: 000a8613 mv a2,s5 -800118bc: fd9ff06f j 80011894 <__muldf3+0x4ac> -800118c0: 00050593 mv a1,a0 -800118c4: f11ff06f j 800117d4 <__muldf3+0x3ec> -800118c8: 00100513 li a0,1 -800118cc: 40d50533 sub a0,a0,a3 -800118d0: 03800713 li a4,56 -800118d4: fca74ce3 blt a4,a0,800118ac <__muldf3+0x4c4> -800118d8: 01f00713 li a4,31 -800118dc: 06a74463 blt a4,a0,80011944 <__muldf3+0x55c> -800118e0: 41e58593 addi a1,a1,1054 -800118e4: 00b41733 sll a4,s0,a1 -800118e8: 00a7d6b3 srl a3,a5,a0 -800118ec: 00b797b3 sll a5,a5,a1 -800118f0: 00d76733 or a4,a4,a3 -800118f4: 00f037b3 snez a5,a5 -800118f8: 00f767b3 or a5,a4,a5 -800118fc: 00a45433 srl s0,s0,a0 -80011900: 0077f713 andi a4,a5,7 -80011904: 02070063 beqz a4,80011924 <__muldf3+0x53c> -80011908: 00f7f713 andi a4,a5,15 -8001190c: 00400693 li a3,4 -80011910: 00d70a63 beq a4,a3,80011924 <__muldf3+0x53c> -80011914: 00478713 addi a4,a5,4 -80011918: 00f737b3 sltu a5,a4,a5 -8001191c: 00f40433 add s0,s0,a5 -80011920: 00070793 mv a5,a4 -80011924: 00841713 slli a4,s0,0x8 -80011928: 06074a63 bltz a4,8001199c <__muldf3+0x5b4> -8001192c: 01d41713 slli a4,s0,0x1d -80011930: 0037d793 srli a5,a5,0x3 -80011934: 00f767b3 or a5,a4,a5 -80011938: 00345413 srli s0,s0,0x3 -8001193c: 00000693 li a3,0 -80011940: ef1ff06f j 80011830 <__muldf3+0x448> -80011944: fe100713 li a4,-31 -80011948: 40d70733 sub a4,a4,a3 -8001194c: 02000813 li a6,32 -80011950: 00e45733 srl a4,s0,a4 -80011954: 00000693 li a3,0 -80011958: 01050663 beq a0,a6,80011964 <__muldf3+0x57c> -8001195c: 43e58593 addi a1,a1,1086 -80011960: 00b416b3 sll a3,s0,a1 -80011964: 00f6e7b3 or a5,a3,a5 -80011968: 00f037b3 snez a5,a5 -8001196c: 00f767b3 or a5,a4,a5 -80011970: 00000413 li s0,0 -80011974: f8dff06f j 80011900 <__muldf3+0x518> -80011978: 00080437 lui s0,0x80 -8001197c: 00000793 li a5,0 -80011980: 7ff00693 li a3,2047 -80011984: 00000613 li a2,0 -80011988: ea9ff06f j 80011830 <__muldf3+0x448> -8001198c: 00000413 li s0,0 -80011990: 00000793 li a5,0 -80011994: 7ff00693 li a3,2047 -80011998: e99ff06f j 80011830 <__muldf3+0x448> -8001199c: 00000413 li s0,0 -800119a0: 00000793 li a5,0 -800119a4: 00100693 li a3,1 -800119a8: e89ff06f j 80011830 <__muldf3+0x448> +800118b0: f8dff06f j 8001183c <__muldf3+0x518> +800118b4: 00080437 lui s0,0x80 +800118b8: 00000793 li a5,0 +800118bc: 7ff00693 li a3,2047 +800118c0: 00000613 li a2,0 +800118c4: ea9ff06f j 8001176c <__muldf3+0x448> +800118c8: 00000413 li s0,0 +800118cc: 00000793 li a5,0 +800118d0: 7ff00693 li a3,2047 +800118d4: e99ff06f j 8001176c <__muldf3+0x448> +800118d8: 00000413 li s0,0 +800118dc: 00000793 li a5,0 +800118e0: 00100693 li a3,1 +800118e4: e89ff06f j 8001176c <__muldf3+0x448> -800119ac <__eqtf2>: -800119ac: 00c52783 lw a5,12(a0) -800119b0: 0005af03 lw t5,0(a1) -800119b4: 0045af83 lw t6,4(a1) -800119b8: 0085a283 lw t0,8(a1) -800119bc: 00c5a583 lw a1,12(a1) -800119c0: 00008737 lui a4,0x8 -800119c4: 0107d693 srli a3,a5,0x10 -800119c8: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -800119cc: 01079813 slli a6,a5,0x10 -800119d0: 01059e93 slli t4,a1,0x10 -800119d4: 01f7d613 srli a2,a5,0x1f -800119d8: 00e6f6b3 and a3,a3,a4 -800119dc: 0105d793 srli a5,a1,0x10 -800119e0: 00052883 lw a7,0(a0) -800119e4: 00452303 lw t1,4(a0) -800119e8: 00852e03 lw t3,8(a0) -800119ec: ff010113 addi sp,sp,-16 -800119f0: 01085813 srli a6,a6,0x10 -800119f4: 010ede93 srli t4,t4,0x10 -800119f8: 00e7f7b3 and a5,a5,a4 -800119fc: 01f5d593 srli a1,a1,0x1f -80011a00: 02e69063 bne a3,a4,80011a20 <__eqtf2+0x74> -80011a04: 0068e733 or a4,a7,t1 -80011a08: 01c76733 or a4,a4,t3 -80011a0c: 01076733 or a4,a4,a6 -80011a10: 00100513 li a0,1 -80011a14: 04071a63 bnez a4,80011a68 <__eqtf2+0xbc> -80011a18: 04d79863 bne a5,a3,80011a68 <__eqtf2+0xbc> -80011a1c: 0080006f j 80011a24 <__eqtf2+0x78> -80011a20: 00e79c63 bne a5,a4,80011a38 <__eqtf2+0x8c> -80011a24: 01ff6733 or a4,t5,t6 -80011a28: 00576733 or a4,a4,t0 -80011a2c: 01d76733 or a4,a4,t4 -80011a30: 00100513 li a0,1 -80011a34: 02071a63 bnez a4,80011a68 <__eqtf2+0xbc> -80011a38: 00100513 li a0,1 -80011a3c: 02d79663 bne a5,a3,80011a68 <__eqtf2+0xbc> -80011a40: 03e89463 bne a7,t5,80011a68 <__eqtf2+0xbc> -80011a44: 03f31263 bne t1,t6,80011a68 <__eqtf2+0xbc> -80011a48: 025e1063 bne t3,t0,80011a68 <__eqtf2+0xbc> -80011a4c: 01d81e63 bne a6,t4,80011a68 <__eqtf2+0xbc> -80011a50: 02b60063 beq a2,a1,80011a70 <__eqtf2+0xc4> -80011a54: 00079a63 bnez a5,80011a68 <__eqtf2+0xbc> -80011a58: 0068e533 or a0,a7,t1 -80011a5c: 01c56533 or a0,a0,t3 -80011a60: 01056533 or a0,a0,a6 -80011a64: 00a03533 snez a0,a0 -80011a68: 01010113 addi sp,sp,16 -80011a6c: 00008067 ret -80011a70: 00000513 li a0,0 -80011a74: ff5ff06f j 80011a68 <__eqtf2+0xbc> +800118e8 <__eqtf2>: +800118e8: 00c52783 lw a5,12(a0) +800118ec: 0005af03 lw t5,0(a1) +800118f0: 0045af83 lw t6,4(a1) +800118f4: 0085a283 lw t0,8(a1) +800118f8: 00c5a583 lw a1,12(a1) +800118fc: 00008737 lui a4,0x8 +80011900: 0107d693 srli a3,a5,0x10 +80011904: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80011908: 01079813 slli a6,a5,0x10 +8001190c: 01059e93 slli t4,a1,0x10 +80011910: 01f7d613 srli a2,a5,0x1f +80011914: 00e6f6b3 and a3,a3,a4 +80011918: 0105d793 srli a5,a1,0x10 +8001191c: 00052883 lw a7,0(a0) +80011920: 00452303 lw t1,4(a0) +80011924: 00852e03 lw t3,8(a0) +80011928: ff010113 addi sp,sp,-16 +8001192c: 01085813 srli a6,a6,0x10 +80011930: 010ede93 srli t4,t4,0x10 +80011934: 00e7f7b3 and a5,a5,a4 +80011938: 01f5d593 srli a1,a1,0x1f +8001193c: 02e69063 bne a3,a4,8001195c <__eqtf2+0x74> +80011940: 0068e733 or a4,a7,t1 +80011944: 01c76733 or a4,a4,t3 +80011948: 01076733 or a4,a4,a6 +8001194c: 00100513 li a0,1 +80011950: 04071a63 bnez a4,800119a4 <__eqtf2+0xbc> +80011954: 04d79863 bne a5,a3,800119a4 <__eqtf2+0xbc> +80011958: 0080006f j 80011960 <__eqtf2+0x78> +8001195c: 00e79c63 bne a5,a4,80011974 <__eqtf2+0x8c> +80011960: 01ff6733 or a4,t5,t6 +80011964: 00576733 or a4,a4,t0 +80011968: 01d76733 or a4,a4,t4 +8001196c: 00100513 li a0,1 +80011970: 02071a63 bnez a4,800119a4 <__eqtf2+0xbc> +80011974: 00100513 li a0,1 +80011978: 02d79663 bne a5,a3,800119a4 <__eqtf2+0xbc> +8001197c: 03e89463 bne a7,t5,800119a4 <__eqtf2+0xbc> +80011980: 03f31263 bne t1,t6,800119a4 <__eqtf2+0xbc> +80011984: 025e1063 bne t3,t0,800119a4 <__eqtf2+0xbc> +80011988: 01d81e63 bne a6,t4,800119a4 <__eqtf2+0xbc> +8001198c: 02b60063 beq a2,a1,800119ac <__eqtf2+0xc4> +80011990: 00079a63 bnez a5,800119a4 <__eqtf2+0xbc> +80011994: 0068e533 or a0,a7,t1 +80011998: 01c56533 or a0,a0,t3 +8001199c: 01056533 or a0,a0,a6 +800119a0: 00a03533 snez a0,a0 +800119a4: 01010113 addi sp,sp,16 +800119a8: 00008067 ret +800119ac: 00000513 li a0,0 +800119b0: ff5ff06f j 800119a4 <__eqtf2+0xbc> -80011a78 <__getf2>: -80011a78: 00052f83 lw t6,0(a0) -80011a7c: 00452803 lw a6,4(a0) -80011a80: 00852e03 lw t3,8(a0) -80011a84: 00c52503 lw a0,12(a0) -80011a88: 00c5a683 lw a3,12(a1) -80011a8c: 000087b7 lui a5,0x8 -80011a90: 01055613 srli a2,a0,0x10 -80011a94: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80011a98: 01069313 slli t1,a3,0x10 -80011a9c: 0106d713 srli a4,a3,0x10 -80011aa0: 0005a283 lw t0,0(a1) -80011aa4: 0045a883 lw a7,4(a1) -80011aa8: 0085ae83 lw t4,8(a1) -80011aac: 00f67633 and a2,a2,a5 -80011ab0: 01051593 slli a1,a0,0x10 -80011ab4: ff010113 addi sp,sp,-16 -80011ab8: 0105d593 srli a1,a1,0x10 -80011abc: 01f55513 srli a0,a0,0x1f -80011ac0: 01035313 srli t1,t1,0x10 -80011ac4: 00f77733 and a4,a4,a5 -80011ac8: 01f6d693 srli a3,a3,0x1f -80011acc: 00f61e63 bne a2,a5,80011ae8 <__getf2+0x70> -80011ad0: 010fe7b3 or a5,t6,a6 -80011ad4: 01c7e7b3 or a5,a5,t3 -80011ad8: 00b7e7b3 or a5,a5,a1 -80011adc: 0c078863 beqz a5,80011bac <__getf2+0x134> -80011ae0: ffe00513 li a0,-2 -80011ae4: 0640006f j 80011b48 <__getf2+0xd0> -80011ae8: 00f71a63 bne a4,a5,80011afc <__getf2+0x84> -80011aec: 0112e7b3 or a5,t0,a7 -80011af0: 01d7e7b3 or a5,a5,t4 -80011af4: 0067e7b3 or a5,a5,t1 -80011af8: fe0794e3 bnez a5,80011ae0 <__getf2+0x68> -80011afc: 0a061a63 bnez a2,80011bb0 <__getf2+0x138> -80011b00: 010fe7b3 or a5,t6,a6 -80011b04: 01c7e7b3 or a5,a5,t3 -80011b08: 00b7e7b3 or a5,a5,a1 -80011b0c: 0017b793 seqz a5,a5 -80011b10: 00071a63 bnez a4,80011b24 <__getf2+0xac> -80011b14: 0112ef33 or t5,t0,a7 -80011b18: 01df6f33 or t5,t5,t4 -80011b1c: 006f6f33 or t5,t5,t1 -80011b20: 060f0a63 beqz t5,80011b94 <__getf2+0x11c> -80011b24: 00079c63 bnez a5,80011b3c <__getf2+0xc4> -80011b28: 00a69463 bne a3,a0,80011b30 <__getf2+0xb8> -80011b2c: 02c75263 bge a4,a2,80011b50 <__getf2+0xd8> -80011b30: 04050e63 beqz a0,80011b8c <__getf2+0x114> -80011b34: fff00513 li a0,-1 -80011b38: 0100006f j 80011b48 <__getf2+0xd0> -80011b3c: fff00513 li a0,-1 -80011b40: 00068463 beqz a3,80011b48 <__getf2+0xd0> -80011b44: 00068513 mv a0,a3 -80011b48: 01010113 addi sp,sp,16 -80011b4c: 00008067 ret -80011b50: 00e65663 bge a2,a4,80011b5c <__getf2+0xe4> -80011b54: fe051ae3 bnez a0,80011b48 <__getf2+0xd0> -80011b58: fddff06f j 80011b34 <__getf2+0xbc> -80011b5c: fcb36ae3 bltu t1,a1,80011b30 <__getf2+0xb8> -80011b60: 02659e63 bne a1,t1,80011b9c <__getf2+0x124> -80011b64: fdcee6e3 bltu t4,t3,80011b30 <__getf2+0xb8> -80011b68: 03de1e63 bne t3,t4,80011ba4 <__getf2+0x12c> -80011b6c: fd08e2e3 bltu a7,a6,80011b30 <__getf2+0xb8> -80011b70: 01181463 bne a6,a7,80011b78 <__getf2+0x100> -80011b74: fbf2eee3 bltu t0,t6,80011b30 <__getf2+0xb8> -80011b78: fd186ee3 bltu a6,a7,80011b54 <__getf2+0xdc> -80011b7c: 01181463 bne a6,a7,80011b84 <__getf2+0x10c> -80011b80: fc5feae3 bltu t6,t0,80011b54 <__getf2+0xdc> -80011b84: 00000513 li a0,0 -80011b88: fc1ff06f j 80011b48 <__getf2+0xd0> -80011b8c: 00100513 li a0,1 -80011b90: fb9ff06f j 80011b48 <__getf2+0xd0> -80011b94: fe0798e3 bnez a5,80011b84 <__getf2+0x10c> -80011b98: f99ff06f j 80011b30 <__getf2+0xb8> -80011b9c: fa65ece3 bltu a1,t1,80011b54 <__getf2+0xdc> -80011ba0: fe5ff06f j 80011b84 <__getf2+0x10c> -80011ba4: fbde68e3 bltu t3,t4,80011b54 <__getf2+0xdc> -80011ba8: fddff06f j 80011b84 <__getf2+0x10c> -80011bac: f4c700e3 beq a4,a2,80011aec <__getf2+0x74> -80011bb0: f6071ce3 bnez a4,80011b28 <__getf2+0xb0> -80011bb4: 00000793 li a5,0 -80011bb8: f5dff06f j 80011b14 <__getf2+0x9c> +800119b4 <__getf2>: +800119b4: 00052f83 lw t6,0(a0) +800119b8: 00452803 lw a6,4(a0) +800119bc: 00852e03 lw t3,8(a0) +800119c0: 00c52503 lw a0,12(a0) +800119c4: 00c5a683 lw a3,12(a1) +800119c8: 000087b7 lui a5,0x8 +800119cc: 01055613 srli a2,a0,0x10 +800119d0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800119d4: 01069313 slli t1,a3,0x10 +800119d8: 0106d713 srli a4,a3,0x10 +800119dc: 0005a283 lw t0,0(a1) +800119e0: 0045a883 lw a7,4(a1) +800119e4: 0085ae83 lw t4,8(a1) +800119e8: 00f67633 and a2,a2,a5 +800119ec: 01051593 slli a1,a0,0x10 +800119f0: ff010113 addi sp,sp,-16 +800119f4: 0105d593 srli a1,a1,0x10 +800119f8: 01f55513 srli a0,a0,0x1f +800119fc: 01035313 srli t1,t1,0x10 +80011a00: 00f77733 and a4,a4,a5 +80011a04: 01f6d693 srli a3,a3,0x1f +80011a08: 00f61e63 bne a2,a5,80011a24 <__getf2+0x70> +80011a0c: 010fe7b3 or a5,t6,a6 +80011a10: 01c7e7b3 or a5,a5,t3 +80011a14: 00b7e7b3 or a5,a5,a1 +80011a18: 0c078863 beqz a5,80011ae8 <__getf2+0x134> +80011a1c: ffe00513 li a0,-2 +80011a20: 0640006f j 80011a84 <__getf2+0xd0> +80011a24: 00f71a63 bne a4,a5,80011a38 <__getf2+0x84> +80011a28: 0112e7b3 or a5,t0,a7 +80011a2c: 01d7e7b3 or a5,a5,t4 +80011a30: 0067e7b3 or a5,a5,t1 +80011a34: fe0794e3 bnez a5,80011a1c <__getf2+0x68> +80011a38: 0a061a63 bnez a2,80011aec <__getf2+0x138> +80011a3c: 010fe7b3 or a5,t6,a6 +80011a40: 01c7e7b3 or a5,a5,t3 +80011a44: 00b7e7b3 or a5,a5,a1 +80011a48: 0017b793 seqz a5,a5 +80011a4c: 00071a63 bnez a4,80011a60 <__getf2+0xac> +80011a50: 0112ef33 or t5,t0,a7 +80011a54: 01df6f33 or t5,t5,t4 +80011a58: 006f6f33 or t5,t5,t1 +80011a5c: 060f0a63 beqz t5,80011ad0 <__getf2+0x11c> +80011a60: 00079c63 bnez a5,80011a78 <__getf2+0xc4> +80011a64: 00a69463 bne a3,a0,80011a6c <__getf2+0xb8> +80011a68: 02c75263 bge a4,a2,80011a8c <__getf2+0xd8> +80011a6c: 04050e63 beqz a0,80011ac8 <__getf2+0x114> +80011a70: fff00513 li a0,-1 +80011a74: 0100006f j 80011a84 <__getf2+0xd0> +80011a78: fff00513 li a0,-1 +80011a7c: 00068463 beqz a3,80011a84 <__getf2+0xd0> +80011a80: 00068513 mv a0,a3 +80011a84: 01010113 addi sp,sp,16 +80011a88: 00008067 ret +80011a8c: 00e65663 bge a2,a4,80011a98 <__getf2+0xe4> +80011a90: fe051ae3 bnez a0,80011a84 <__getf2+0xd0> +80011a94: fddff06f j 80011a70 <__getf2+0xbc> +80011a98: fcb36ae3 bltu t1,a1,80011a6c <__getf2+0xb8> +80011a9c: 02659e63 bne a1,t1,80011ad8 <__getf2+0x124> +80011aa0: fdcee6e3 bltu t4,t3,80011a6c <__getf2+0xb8> +80011aa4: 03de1e63 bne t3,t4,80011ae0 <__getf2+0x12c> +80011aa8: fd08e2e3 bltu a7,a6,80011a6c <__getf2+0xb8> +80011aac: 01181463 bne a6,a7,80011ab4 <__getf2+0x100> +80011ab0: fbf2eee3 bltu t0,t6,80011a6c <__getf2+0xb8> +80011ab4: fd186ee3 bltu a6,a7,80011a90 <__getf2+0xdc> +80011ab8: 01181463 bne a6,a7,80011ac0 <__getf2+0x10c> +80011abc: fc5feae3 bltu t6,t0,80011a90 <__getf2+0xdc> +80011ac0: 00000513 li a0,0 +80011ac4: fc1ff06f j 80011a84 <__getf2+0xd0> +80011ac8: 00100513 li a0,1 +80011acc: fb9ff06f j 80011a84 <__getf2+0xd0> +80011ad0: fe0798e3 bnez a5,80011ac0 <__getf2+0x10c> +80011ad4: f99ff06f j 80011a6c <__getf2+0xb8> +80011ad8: fa65ece3 bltu a1,t1,80011a90 <__getf2+0xdc> +80011adc: fe5ff06f j 80011ac0 <__getf2+0x10c> +80011ae0: fbde68e3 bltu t3,t4,80011a90 <__getf2+0xdc> +80011ae4: fddff06f j 80011ac0 <__getf2+0x10c> +80011ae8: f4c700e3 beq a4,a2,80011a28 <__getf2+0x74> +80011aec: f6071ce3 bnez a4,80011a64 <__getf2+0xb0> +80011af0: 00000793 li a5,0 +80011af4: f5dff06f j 80011a50 <__getf2+0x9c> -80011bbc <__letf2>: -80011bbc: 00052f83 lw t6,0(a0) -80011bc0: 00452803 lw a6,4(a0) -80011bc4: 00852e03 lw t3,8(a0) -80011bc8: 00c52503 lw a0,12(a0) -80011bcc: 00c5a683 lw a3,12(a1) -80011bd0: 000087b7 lui a5,0x8 -80011bd4: 01055613 srli a2,a0,0x10 -80011bd8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80011bdc: 01069313 slli t1,a3,0x10 -80011be0: 0106d713 srli a4,a3,0x10 -80011be4: 0005a283 lw t0,0(a1) -80011be8: 0045a883 lw a7,4(a1) -80011bec: 0085ae83 lw t4,8(a1) -80011bf0: 00f67633 and a2,a2,a5 -80011bf4: 01051593 slli a1,a0,0x10 -80011bf8: ff010113 addi sp,sp,-16 -80011bfc: 0105d593 srli a1,a1,0x10 -80011c00: 01f55513 srli a0,a0,0x1f -80011c04: 01035313 srli t1,t1,0x10 -80011c08: 00f77733 and a4,a4,a5 -80011c0c: 01f6d693 srli a3,a3,0x1f -80011c10: 00f61e63 bne a2,a5,80011c2c <__letf2+0x70> -80011c14: 010fe7b3 or a5,t6,a6 -80011c18: 01c7e7b3 or a5,a5,t3 -80011c1c: 00b7e7b3 or a5,a5,a1 -80011c20: 0c078863 beqz a5,80011cf0 <__letf2+0x134> -80011c24: 00200513 li a0,2 -80011c28: 0640006f j 80011c8c <__letf2+0xd0> -80011c2c: 00f71a63 bne a4,a5,80011c40 <__letf2+0x84> -80011c30: 0112e7b3 or a5,t0,a7 -80011c34: 01d7e7b3 or a5,a5,t4 -80011c38: 0067e7b3 or a5,a5,t1 -80011c3c: fe0794e3 bnez a5,80011c24 <__letf2+0x68> -80011c40: 0a061a63 bnez a2,80011cf4 <__letf2+0x138> -80011c44: 010fe7b3 or a5,t6,a6 -80011c48: 01c7e7b3 or a5,a5,t3 -80011c4c: 00b7e7b3 or a5,a5,a1 -80011c50: 0017b793 seqz a5,a5 -80011c54: 00071a63 bnez a4,80011c68 <__letf2+0xac> -80011c58: 0112ef33 or t5,t0,a7 -80011c5c: 01df6f33 or t5,t5,t4 -80011c60: 006f6f33 or t5,t5,t1 -80011c64: 060f0a63 beqz t5,80011cd8 <__letf2+0x11c> -80011c68: 00079c63 bnez a5,80011c80 <__letf2+0xc4> -80011c6c: 00a69463 bne a3,a0,80011c74 <__letf2+0xb8> -80011c70: 02c75263 bge a4,a2,80011c94 <__letf2+0xd8> -80011c74: 04050e63 beqz a0,80011cd0 <__letf2+0x114> -80011c78: fff00513 li a0,-1 -80011c7c: 0100006f j 80011c8c <__letf2+0xd0> -80011c80: fff00513 li a0,-1 -80011c84: 00068463 beqz a3,80011c8c <__letf2+0xd0> -80011c88: 00068513 mv a0,a3 -80011c8c: 01010113 addi sp,sp,16 -80011c90: 00008067 ret -80011c94: 00e65663 bge a2,a4,80011ca0 <__letf2+0xe4> -80011c98: fe051ae3 bnez a0,80011c8c <__letf2+0xd0> -80011c9c: fddff06f j 80011c78 <__letf2+0xbc> -80011ca0: fcb36ae3 bltu t1,a1,80011c74 <__letf2+0xb8> -80011ca4: 02659e63 bne a1,t1,80011ce0 <__letf2+0x124> -80011ca8: fdcee6e3 bltu t4,t3,80011c74 <__letf2+0xb8> -80011cac: 03de1e63 bne t3,t4,80011ce8 <__letf2+0x12c> -80011cb0: fd08e2e3 bltu a7,a6,80011c74 <__letf2+0xb8> -80011cb4: 01181463 bne a6,a7,80011cbc <__letf2+0x100> -80011cb8: fbf2eee3 bltu t0,t6,80011c74 <__letf2+0xb8> -80011cbc: fd186ee3 bltu a6,a7,80011c98 <__letf2+0xdc> -80011cc0: 01181463 bne a6,a7,80011cc8 <__letf2+0x10c> -80011cc4: fc5feae3 bltu t6,t0,80011c98 <__letf2+0xdc> -80011cc8: 00000513 li a0,0 -80011ccc: fc1ff06f j 80011c8c <__letf2+0xd0> -80011cd0: 00100513 li a0,1 -80011cd4: fb9ff06f j 80011c8c <__letf2+0xd0> -80011cd8: fe0798e3 bnez a5,80011cc8 <__letf2+0x10c> -80011cdc: f99ff06f j 80011c74 <__letf2+0xb8> -80011ce0: fa65ece3 bltu a1,t1,80011c98 <__letf2+0xdc> -80011ce4: fe5ff06f j 80011cc8 <__letf2+0x10c> -80011ce8: fbde68e3 bltu t3,t4,80011c98 <__letf2+0xdc> -80011cec: fddff06f j 80011cc8 <__letf2+0x10c> -80011cf0: f4c700e3 beq a4,a2,80011c30 <__letf2+0x74> -80011cf4: f6071ce3 bnez a4,80011c6c <__letf2+0xb0> -80011cf8: 00000793 li a5,0 -80011cfc: f5dff06f j 80011c58 <__letf2+0x9c> +80011af8 <__letf2>: +80011af8: 00052f83 lw t6,0(a0) +80011afc: 00452803 lw a6,4(a0) +80011b00: 00852e03 lw t3,8(a0) +80011b04: 00c52503 lw a0,12(a0) +80011b08: 00c5a683 lw a3,12(a1) +80011b0c: 000087b7 lui a5,0x8 +80011b10: 01055613 srli a2,a0,0x10 +80011b14: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80011b18: 01069313 slli t1,a3,0x10 +80011b1c: 0106d713 srli a4,a3,0x10 +80011b20: 0005a283 lw t0,0(a1) +80011b24: 0045a883 lw a7,4(a1) +80011b28: 0085ae83 lw t4,8(a1) +80011b2c: 00f67633 and a2,a2,a5 +80011b30: 01051593 slli a1,a0,0x10 +80011b34: ff010113 addi sp,sp,-16 +80011b38: 0105d593 srli a1,a1,0x10 +80011b3c: 01f55513 srli a0,a0,0x1f +80011b40: 01035313 srli t1,t1,0x10 +80011b44: 00f77733 and a4,a4,a5 +80011b48: 01f6d693 srli a3,a3,0x1f +80011b4c: 00f61e63 bne a2,a5,80011b68 <__letf2+0x70> +80011b50: 010fe7b3 or a5,t6,a6 +80011b54: 01c7e7b3 or a5,a5,t3 +80011b58: 00b7e7b3 or a5,a5,a1 +80011b5c: 0c078863 beqz a5,80011c2c <__letf2+0x134> +80011b60: 00200513 li a0,2 +80011b64: 0640006f j 80011bc8 <__letf2+0xd0> +80011b68: 00f71a63 bne a4,a5,80011b7c <__letf2+0x84> +80011b6c: 0112e7b3 or a5,t0,a7 +80011b70: 01d7e7b3 or a5,a5,t4 +80011b74: 0067e7b3 or a5,a5,t1 +80011b78: fe0794e3 bnez a5,80011b60 <__letf2+0x68> +80011b7c: 0a061a63 bnez a2,80011c30 <__letf2+0x138> +80011b80: 010fe7b3 or a5,t6,a6 +80011b84: 01c7e7b3 or a5,a5,t3 +80011b88: 00b7e7b3 or a5,a5,a1 +80011b8c: 0017b793 seqz a5,a5 +80011b90: 00071a63 bnez a4,80011ba4 <__letf2+0xac> +80011b94: 0112ef33 or t5,t0,a7 +80011b98: 01df6f33 or t5,t5,t4 +80011b9c: 006f6f33 or t5,t5,t1 +80011ba0: 060f0a63 beqz t5,80011c14 <__letf2+0x11c> +80011ba4: 00079c63 bnez a5,80011bbc <__letf2+0xc4> +80011ba8: 00a69463 bne a3,a0,80011bb0 <__letf2+0xb8> +80011bac: 02c75263 bge a4,a2,80011bd0 <__letf2+0xd8> +80011bb0: 04050e63 beqz a0,80011c0c <__letf2+0x114> +80011bb4: fff00513 li a0,-1 +80011bb8: 0100006f j 80011bc8 <__letf2+0xd0> +80011bbc: fff00513 li a0,-1 +80011bc0: 00068463 beqz a3,80011bc8 <__letf2+0xd0> +80011bc4: 00068513 mv a0,a3 +80011bc8: 01010113 addi sp,sp,16 +80011bcc: 00008067 ret +80011bd0: 00e65663 bge a2,a4,80011bdc <__letf2+0xe4> +80011bd4: fe051ae3 bnez a0,80011bc8 <__letf2+0xd0> +80011bd8: fddff06f j 80011bb4 <__letf2+0xbc> +80011bdc: fcb36ae3 bltu t1,a1,80011bb0 <__letf2+0xb8> +80011be0: 02659e63 bne a1,t1,80011c1c <__letf2+0x124> +80011be4: fdcee6e3 bltu t4,t3,80011bb0 <__letf2+0xb8> +80011be8: 03de1e63 bne t3,t4,80011c24 <__letf2+0x12c> +80011bec: fd08e2e3 bltu a7,a6,80011bb0 <__letf2+0xb8> +80011bf0: 01181463 bne a6,a7,80011bf8 <__letf2+0x100> +80011bf4: fbf2eee3 bltu t0,t6,80011bb0 <__letf2+0xb8> +80011bf8: fd186ee3 bltu a6,a7,80011bd4 <__letf2+0xdc> +80011bfc: 01181463 bne a6,a7,80011c04 <__letf2+0x10c> +80011c00: fc5feae3 bltu t6,t0,80011bd4 <__letf2+0xdc> +80011c04: 00000513 li a0,0 +80011c08: fc1ff06f j 80011bc8 <__letf2+0xd0> +80011c0c: 00100513 li a0,1 +80011c10: fb9ff06f j 80011bc8 <__letf2+0xd0> +80011c14: fe0798e3 bnez a5,80011c04 <__letf2+0x10c> +80011c18: f99ff06f j 80011bb0 <__letf2+0xb8> +80011c1c: fa65ece3 bltu a1,t1,80011bd4 <__letf2+0xdc> +80011c20: fe5ff06f j 80011c04 <__letf2+0x10c> +80011c24: fbde68e3 bltu t3,t4,80011bd4 <__letf2+0xdc> +80011c28: fddff06f j 80011c04 <__letf2+0x10c> +80011c2c: f4c700e3 beq a4,a2,80011b6c <__letf2+0x74> +80011c30: f6071ce3 bnez a4,80011ba8 <__letf2+0xb0> +80011c34: 00000793 li a5,0 +80011c38: f5dff06f j 80011b94 <__letf2+0x9c> -80011d00 <__multf3>: -80011d00: f4010113 addi sp,sp,-192 -80011d04: 0a912a23 sw s1,180(sp) -80011d08: 00c5a483 lw s1,12(a1) -80011d0c: 0005a683 lw a3,0(a1) -80011d10: 0045a783 lw a5,4(a1) -80011d14: 00a12423 sw a0,8(sp) -80011d18: 0085a503 lw a0,8(a1) -80011d1c: 01049713 slli a4,s1,0x10 -80011d20: 0b212823 sw s2,176(sp) -80011d24: 0b312623 sw s3,172(sp) -80011d28: 00c62903 lw s2,12(a2) # 7ff0000c <_start-0xffff4> -80011d2c: 00062983 lw s3,0(a2) -80011d30: 0b412423 sw s4,168(sp) -80011d34: 0b512223 sw s5,164(sp) -80011d38: 00862a03 lw s4,8(a2) -80011d3c: 00462a83 lw s5,4(a2) -80011d40: 00008637 lui a2,0x8 -80011d44: 0a812c23 sw s0,184(sp) -80011d48: 01075713 srli a4,a4,0x10 -80011d4c: 0104d413 srli s0,s1,0x10 -80011d50: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> -80011d54: 06912623 sw s1,108(sp) -80011d58: 0a112e23 sw ra,188(sp) -80011d5c: 0b612023 sw s6,160(sp) -80011d60: 09712e23 sw s7,156(sp) -80011d64: 09812c23 sw s8,152(sp) -80011d68: 09912a23 sw s9,148(sp) -80011d6c: 09a12823 sw s10,144(sp) -80011d70: 09b12623 sw s11,140(sp) -80011d74: 06d12023 sw a3,96(sp) -80011d78: 06f12223 sw a5,100(sp) -80011d7c: 06a12423 sw a0,104(sp) -80011d80: 02d12823 sw a3,48(sp) -80011d84: 02f12a23 sw a5,52(sp) -80011d88: 02a12c23 sw a0,56(sp) -80011d8c: 02e12e23 sw a4,60(sp) -80011d90: 00c47433 and s0,s0,a2 -80011d94: 01f4d493 srli s1,s1,0x1f -80011d98: 12040863 beqz s0,80011ec8 <__multf3+0x1c8> -80011d9c: 24c40663 beq s0,a2,80011fe8 <__multf3+0x2e8> -80011da0: 000107b7 lui a5,0x10 -80011da4: 00f767b3 or a5,a4,a5 -80011da8: 02f12e23 sw a5,60(sp) -80011dac: 03010613 addi a2,sp,48 -80011db0: 03c10793 addi a5,sp,60 -80011db4: 0007a703 lw a4,0(a5) # 10000 <_start-0x7fff0000> -80011db8: ffc7a683 lw a3,-4(a5) -80011dbc: ffc78793 addi a5,a5,-4 -80011dc0: 00371713 slli a4,a4,0x3 -80011dc4: 01d6d693 srli a3,a3,0x1d -80011dc8: 00d76733 or a4,a4,a3 -80011dcc: 00e7a223 sw a4,4(a5) -80011dd0: fef612e3 bne a2,a5,80011db4 <__multf3+0xb4> -80011dd4: 03012783 lw a5,48(sp) -80011dd8: ffffc537 lui a0,0xffffc -80011ddc: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe53c5> -80011de0: 00379793 slli a5,a5,0x3 -80011de4: 02f12823 sw a5,48(sp) -80011de8: 00a40433 add s0,s0,a0 -80011dec: 00000b13 li s6,0 -80011df0: 01091513 slli a0,s2,0x10 -80011df4: 00008737 lui a4,0x8 -80011df8: 01095793 srli a5,s2,0x10 -80011dfc: 01055513 srli a0,a0,0x10 -80011e00: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80011e04: 07212623 sw s2,108(sp) -80011e08: 07312023 sw s3,96(sp) -80011e0c: 07512223 sw s5,100(sp) -80011e10: 07412423 sw s4,104(sp) -80011e14: 05312023 sw s3,64(sp) -80011e18: 05512223 sw s5,68(sp) -80011e1c: 05412423 sw s4,72(sp) -80011e20: 04a12623 sw a0,76(sp) -80011e24: 00e7f7b3 and a5,a5,a4 -80011e28: 01f95913 srli s2,s2,0x1f -80011e2c: 1e078263 beqz a5,80012010 <__multf3+0x310> -80011e30: 30e78063 beq a5,a4,80012130 <__multf3+0x430> -80011e34: 00010a37 lui s4,0x10 -80011e38: 01456a33 or s4,a0,s4 -80011e3c: 05412623 sw s4,76(sp) -80011e40: 04010593 addi a1,sp,64 -80011e44: 04c10713 addi a4,sp,76 -80011e48: 00072683 lw a3,0(a4) -80011e4c: ffc72603 lw a2,-4(a4) -80011e50: ffc70713 addi a4,a4,-4 -80011e54: 00369693 slli a3,a3,0x3 -80011e58: 01d65613 srli a2,a2,0x1d -80011e5c: 00c6e6b3 or a3,a3,a2 -80011e60: 00d72223 sw a3,4(a4) -80011e64: fee592e3 bne a1,a4,80011e48 <__multf3+0x148> -80011e68: 04012703 lw a4,64(sp) -80011e6c: ffffc537 lui a0,0xffffc -80011e70: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe53c5> -80011e74: 00371713 slli a4,a4,0x3 -80011e78: 04e12023 sw a4,64(sp) -80011e7c: 00a787b3 add a5,a5,a0 -80011e80: 00000713 li a4,0 -80011e84: 008787b3 add a5,a5,s0 -80011e88: 00f12e23 sw a5,28(sp) -80011e8c: 00178793 addi a5,a5,1 -80011e90: 00f12c23 sw a5,24(sp) -80011e94: 002b1793 slli a5,s6,0x2 -80011e98: 0124c6b3 xor a3,s1,s2 -80011e9c: 00e7e7b3 or a5,a5,a4 -80011ea0: 00d12623 sw a3,12(sp) -80011ea4: fff78793 addi a5,a5,-1 -80011ea8: 00e00693 li a3,14 -80011eac: 2af6e663 bltu a3,a5,80012158 <__multf3+0x458> -80011eb0: 800166b7 lui a3,0x80016 -80011eb4: 00279793 slli a5,a5,0x2 -80011eb8: 81068693 addi a3,a3,-2032 # 80015810 <__BSS_END__+0xffffebd4> -80011ebc: 00d787b3 add a5,a5,a3 -80011ec0: 0007a783 lw a5,0(a5) -80011ec4: 00078067 jr a5 -80011ec8: 00d7e633 or a2,a5,a3 -80011ecc: 00a66633 or a2,a2,a0 -80011ed0: 00e66633 or a2,a2,a4 -80011ed4: 12060863 beqz a2,80012004 <__multf3+0x304> -80011ed8: 06070063 beqz a4,80011f38 <__multf3+0x238> -80011edc: 00070513 mv a0,a4 -80011ee0: 2e9020ef jal ra,800149c8 <__clzsi2> -80011ee4: ff450693 addi a3,a0,-12 -80011ee8: 4056d793 srai a5,a3,0x5 -80011eec: 01f6f693 andi a3,a3,31 -80011ef0: 06068e63 beqz a3,80011f6c <__multf3+0x26c> -80011ef4: ffc00713 li a4,-4 -80011ef8: 02e78733 mul a4,a5,a4 -80011efc: 03010313 addi t1,sp,48 -80011f00: 02000813 li a6,32 -80011f04: 00279593 slli a1,a5,0x2 -80011f08: 40d80833 sub a6,a6,a3 -80011f0c: 00c70713 addi a4,a4,12 -80011f10: 00e30733 add a4,t1,a4 -80011f14: 08e31463 bne t1,a4,80011f9c <__multf3+0x29c> -80011f18: 08010713 addi a4,sp,128 -80011f1c: 00b705b3 add a1,a4,a1 -80011f20: 03012703 lw a4,48(sp) -80011f24: fff78793 addi a5,a5,-1 -80011f28: 00d716b3 sll a3,a4,a3 -80011f2c: fad5a823 sw a3,-80(a1) -80011f30: fff00693 li a3,-1 -80011f34: 0a00006f j 80011fd4 <__multf3+0x2d4> -80011f38: 00050863 beqz a0,80011f48 <__multf3+0x248> -80011f3c: 28d020ef jal ra,800149c8 <__clzsi2> -80011f40: 02050513 addi a0,a0,32 -80011f44: fa1ff06f j 80011ee4 <__multf3+0x1e4> -80011f48: 00078a63 beqz a5,80011f5c <__multf3+0x25c> -80011f4c: 00078513 mv a0,a5 -80011f50: 279020ef jal ra,800149c8 <__clzsi2> -80011f54: 04050513 addi a0,a0,64 -80011f58: f8dff06f j 80011ee4 <__multf3+0x1e4> -80011f5c: 00068513 mv a0,a3 -80011f60: 269020ef jal ra,800149c8 <__clzsi2> -80011f64: 06050513 addi a0,a0,96 -80011f68: f7dff06f j 80011ee4 <__multf3+0x1e4> -80011f6c: ffc00613 li a2,-4 -80011f70: 02c78633 mul a2,a5,a2 -80011f74: 03c10713 addi a4,sp,60 -80011f78: 00300693 li a3,3 -80011f7c: 00c705b3 add a1,a4,a2 -80011f80: 0005a583 lw a1,0(a1) -80011f84: fff68693 addi a3,a3,-1 -80011f88: ffc70713 addi a4,a4,-4 -80011f8c: 00b72223 sw a1,4(a4) -80011f90: fef6d6e3 bge a3,a5,80011f7c <__multf3+0x27c> -80011f94: fff78793 addi a5,a5,-1 -80011f98: f99ff06f j 80011f30 <__multf3+0x230> -80011f9c: ffc72603 lw a2,-4(a4) -80011fa0: 00072883 lw a7,0(a4) -80011fa4: 00b70e33 add t3,a4,a1 -80011fa8: 01065633 srl a2,a2,a6 -80011fac: 00d898b3 sll a7,a7,a3 -80011fb0: 01166633 or a2,a2,a7 -80011fb4: 00ce2023 sw a2,0(t3) -80011fb8: ffc70713 addi a4,a4,-4 -80011fbc: f59ff06f j 80011f14 <__multf3+0x214> -80011fc0: 00279713 slli a4,a5,0x2 -80011fc4: 03010613 addi a2,sp,48 -80011fc8: 00e60733 add a4,a2,a4 -80011fcc: 00072023 sw zero,0(a4) -80011fd0: fff78793 addi a5,a5,-1 -80011fd4: fed796e3 bne a5,a3,80011fc0 <__multf3+0x2c0> -80011fd8: ffffc437 lui s0,0xffffc -80011fdc: 01140413 addi s0,s0,17 # ffffc011 <__BSS_END__+0x7ffe53d5> -80011fe0: 40a40433 sub s0,s0,a0 -80011fe4: e09ff06f j 80011dec <__multf3+0xec> -80011fe8: 00d7e7b3 or a5,a5,a3 -80011fec: 00a7e7b3 or a5,a5,a0 -80011ff0: 00e7e7b3 or a5,a5,a4 -80011ff4: 00300b13 li s6,3 -80011ff8: de079ce3 bnez a5,80011df0 <__multf3+0xf0> -80011ffc: 00200b13 li s6,2 -80012000: df1ff06f j 80011df0 <__multf3+0xf0> -80012004: 00000413 li s0,0 -80012008: 00100b13 li s6,1 -8001200c: de5ff06f j 80011df0 <__multf3+0xf0> -80012010: 0159e7b3 or a5,s3,s5 -80012014: 0147e7b3 or a5,a5,s4 -80012018: 00a7e7b3 or a5,a5,a0 -8001201c: 12078863 beqz a5,8001214c <__multf3+0x44c> -80012020: 04050e63 beqz a0,8001207c <__multf3+0x37c> -80012024: 1a5020ef jal ra,800149c8 <__clzsi2> -80012028: ff450693 addi a3,a0,-12 -8001202c: 4056d793 srai a5,a3,0x5 -80012030: 01f6f693 andi a3,a3,31 -80012034: 08068063 beqz a3,800120b4 <__multf3+0x3b4> -80012038: ffc00713 li a4,-4 -8001203c: 02e78733 mul a4,a5,a4 -80012040: 04010313 addi t1,sp,64 -80012044: 02000813 li a6,32 -80012048: 00279593 slli a1,a5,0x2 -8001204c: 40d80833 sub a6,a6,a3 -80012050: 00c70713 addi a4,a4,12 -80012054: 00e30733 add a4,t1,a4 -80012058: 08e31663 bne t1,a4,800120e4 <__multf3+0x3e4> -8001205c: 08010713 addi a4,sp,128 -80012060: 00b705b3 add a1,a4,a1 -80012064: 04012703 lw a4,64(sp) -80012068: fff78793 addi a5,a5,-1 -8001206c: 00d716b3 sll a3,a4,a3 -80012070: fcd5a023 sw a3,-64(a1) -80012074: fff00693 li a3,-1 -80012078: 0a40006f j 8001211c <__multf3+0x41c> -8001207c: 000a0a63 beqz s4,80012090 <__multf3+0x390> -80012080: 000a0513 mv a0,s4 -80012084: 145020ef jal ra,800149c8 <__clzsi2> -80012088: 02050513 addi a0,a0,32 -8001208c: f9dff06f j 80012028 <__multf3+0x328> -80012090: 000a8a63 beqz s5,800120a4 <__multf3+0x3a4> -80012094: 000a8513 mv a0,s5 -80012098: 131020ef jal ra,800149c8 <__clzsi2> -8001209c: 04050513 addi a0,a0,64 -800120a0: f89ff06f j 80012028 <__multf3+0x328> -800120a4: 00098513 mv a0,s3 -800120a8: 121020ef jal ra,800149c8 <__clzsi2> -800120ac: 06050513 addi a0,a0,96 -800120b0: f79ff06f j 80012028 <__multf3+0x328> -800120b4: ffc00613 li a2,-4 -800120b8: 02c78633 mul a2,a5,a2 -800120bc: 04c10713 addi a4,sp,76 -800120c0: 00300693 li a3,3 -800120c4: 00c705b3 add a1,a4,a2 -800120c8: 0005a583 lw a1,0(a1) -800120cc: fff68693 addi a3,a3,-1 -800120d0: ffc70713 addi a4,a4,-4 -800120d4: 00b72223 sw a1,4(a4) -800120d8: fef6d6e3 bge a3,a5,800120c4 <__multf3+0x3c4> -800120dc: fff78793 addi a5,a5,-1 -800120e0: f95ff06f j 80012074 <__multf3+0x374> -800120e4: ffc72603 lw a2,-4(a4) -800120e8: 00072883 lw a7,0(a4) -800120ec: 00b70e33 add t3,a4,a1 -800120f0: 01065633 srl a2,a2,a6 -800120f4: 00d898b3 sll a7,a7,a3 -800120f8: 01166633 or a2,a2,a7 -800120fc: 00ce2023 sw a2,0(t3) -80012100: ffc70713 addi a4,a4,-4 -80012104: f55ff06f j 80012058 <__multf3+0x358> -80012108: 00279713 slli a4,a5,0x2 -8001210c: 04010613 addi a2,sp,64 -80012110: 00e60733 add a4,a2,a4 -80012114: 00072023 sw zero,0(a4) -80012118: fff78793 addi a5,a5,-1 -8001211c: fed796e3 bne a5,a3,80012108 <__multf3+0x408> -80012120: ffffc7b7 lui a5,0xffffc -80012124: 01178793 addi a5,a5,17 # ffffc011 <__BSS_END__+0x7ffe53d5> -80012128: 40a787b3 sub a5,a5,a0 -8001212c: d55ff06f j 80011e80 <__multf3+0x180> -80012130: 0159e9b3 or s3,s3,s5 -80012134: 0149ea33 or s4,s3,s4 -80012138: 00aa6a33 or s4,s4,a0 -8001213c: 00300713 li a4,3 -80012140: d40a12e3 bnez s4,80011e84 <__multf3+0x184> -80012144: 00200713 li a4,2 -80012148: d3dff06f j 80011e84 <__multf3+0x184> -8001214c: 00000793 li a5,0 -80012150: 00100713 li a4,1 -80012154: d31ff06f j 80011e84 <__multf3+0x184> -80012158: 03012703 lw a4,48(sp) -8001215c: 04012e03 lw t3,64(sp) -80012160: 00010537 lui a0,0x10 -80012164: fff50693 addi a3,a0,-1 # ffff <_start-0x7fff0001> -80012168: 01075f93 srli t6,a4,0x10 -8001216c: 010e5a93 srli s5,t3,0x10 -80012170: 00d77733 and a4,a4,a3 -80012174: 00de7e33 and t3,t3,a3 -80012178: 02ea87b3 mul a5,s5,a4 -8001217c: 02ee0633 mul a2,t3,a4 -80012180: 03cf8833 mul a6,t6,t3 -80012184: 010785b3 add a1,a5,a6 -80012188: 01065793 srli a5,a2,0x10 -8001218c: 00b787b3 add a5,a5,a1 -80012190: 035f8bb3 mul s7,t6,s5 -80012194: 0107f463 bgeu a5,a6,8001219c <__multf3+0x49c> -80012198: 00ab8bb3 add s7,s7,a0 -8001219c: 04412f03 lw t5,68(sp) -800121a0: 0107d993 srli s3,a5,0x10 -800121a4: 00d7f7b3 and a5,a5,a3 -800121a8: 00d67633 and a2,a2,a3 -800121ac: 01079793 slli a5,a5,0x10 -800121b0: 00c787b3 add a5,a5,a2 -800121b4: 010f5493 srli s1,t5,0x10 -800121b8: 00df7f33 and t5,t5,a3 -800121bc: 02ef06b3 mul a3,t5,a4 -800121c0: 02f12023 sw a5,32(sp) -800121c4: 06f12023 sw a5,96(sp) -800121c8: 03ef8633 mul a2,t6,t5 -800121cc: 02e487b3 mul a5,s1,a4 -800121d0: 00c78533 add a0,a5,a2 -800121d4: 0106d793 srli a5,a3,0x10 -800121d8: 00a787b3 add a5,a5,a0 -800121dc: 029f8b33 mul s6,t6,s1 -800121e0: 00c7f663 bgeu a5,a2,800121ec <__multf3+0x4ec> -800121e4: 00010637 lui a2,0x10 -800121e8: 00cb0b33 add s6,s6,a2 -800121ec: 00010637 lui a2,0x10 -800121f0: fff60593 addi a1,a2,-1 # ffff <_start-0x7fff0001> -800121f4: 00b7f533 and a0,a5,a1 -800121f8: 0107d293 srli t0,a5,0x10 -800121fc: 03412783 lw a5,52(sp) -80012200: 00b6f6b3 and a3,a3,a1 -80012204: 01051513 slli a0,a0,0x10 -80012208: 0107d913 srli s2,a5,0x10 -8001220c: 00b7f5b3 and a1,a5,a1 -80012210: 02ba87b3 mul a5,s5,a1 -80012214: 00d50533 add a0,a0,a3 -80012218: 00a989b3 add s3,s3,a0 -8001221c: 03c586b3 mul a3,a1,t3 -80012220: 03c90333 mul t1,s2,t3 -80012224: 00678833 add a6,a5,t1 -80012228: 0106d793 srli a5,a3,0x10 -8001222c: 010787b3 add a5,a5,a6 -80012230: 032a88b3 mul a7,s5,s2 -80012234: 0067f463 bgeu a5,t1,8001223c <__multf3+0x53c> -80012238: 00c888b3 add a7,a7,a2 -8001223c: 00010337 lui t1,0x10 -80012240: fff30613 addi a2,t1,-1 # ffff <_start-0x7fff0001> -80012244: 0107da13 srli s4,a5,0x10 -80012248: 00c7f833 and a6,a5,a2 -8001224c: 00c6f6b3 and a3,a3,a2 -80012250: 011a0a33 add s4,s4,a7 -80012254: 01081813 slli a6,a6,0x10 -80012258: 03e588b3 mul a7,a1,t5 -8001225c: 00d80833 add a6,a6,a3 -80012260: 03e90633 mul a2,s2,t5 -80012264: 0108d693 srli a3,a7,0x10 -80012268: 02b487b3 mul a5,s1,a1 -8001226c: 00c787b3 add a5,a5,a2 -80012270: 00f687b3 add a5,a3,a5 -80012274: 03248eb3 mul t4,s1,s2 -80012278: 00c7f463 bgeu a5,a2,80012280 <__multf3+0x580> -8001227c: 006e8eb3 add t4,t4,t1 -80012280: 0107d693 srli a3,a5,0x10 -80012284: 01d686b3 add a3,a3,t4 -80012288: 00010437 lui s0,0x10 -8001228c: 04812e83 lw t4,72(sp) -80012290: fff40613 addi a2,s0,-1 # ffff <_start-0x7fff0001> -80012294: 02d12223 sw a3,36(sp) -80012298: 00c7f6b3 and a3,a5,a2 -8001229c: 00c8f8b3 and a7,a7,a2 -800122a0: 010ed393 srli t2,t4,0x10 -800122a4: 01069693 slli a3,a3,0x10 -800122a8: 00cefeb3 and t4,t4,a2 -800122ac: 02ee8333 mul t1,t4,a4 -800122b0: 011686b3 add a3,a3,a7 -800122b4: 03df8c33 mul s8,t6,t4 -800122b8: 02e388b3 mul a7,t2,a4 -800122bc: 018887b3 add a5,a7,s8 -800122c0: 01035893 srli a7,t1,0x10 -800122c4: 00f888b3 add a7,a7,a5 -800122c8: 027f8633 mul a2,t6,t2 -800122cc: 0188f463 bgeu a7,s8,800122d4 <__multf3+0x5d4> -800122d0: 00860633 add a2,a2,s0 -800122d4: 0108d793 srli a5,a7,0x10 -800122d8: 00010cb7 lui s9,0x10 -800122dc: 00c787b3 add a5,a5,a2 -800122e0: fffc8613 addi a2,s9,-1 # ffff <_start-0x7fff0001> -800122e4: 02f12423 sw a5,40(sp) -800122e8: 00c8f7b3 and a5,a7,a2 -800122ec: 03812883 lw a7,56(sp) -800122f0: 00c37333 and t1,t1,a2 -800122f4: 01079793 slli a5,a5,0x10 -800122f8: 0108d413 srli s0,a7,0x10 -800122fc: 00c8f633 and a2,a7,a2 -80012300: 03c608b3 mul a7,a2,t3 -80012304: 006787b3 add a5,a5,t1 -80012308: 03c40d33 mul s10,s0,t3 -8001230c: 0108dd93 srli s11,a7,0x10 -80012310: 02ca8333 mul t1,s5,a2 -80012314: 01a30333 add t1,t1,s10 -80012318: 006d8333 add t1,s11,t1 -8001231c: 028a8c33 mul s8,s5,s0 -80012320: 01a37463 bgeu t1,s10,80012328 <__multf3+0x628> -80012324: 019c0c33 add s8,s8,s9 -80012328: 01035c93 srli s9,t1,0x10 -8001232c: 018c8c33 add s8,s9,s8 -80012330: 00010cb7 lui s9,0x10 -80012334: 013b89b3 add s3,s7,s3 -80012338: fffc8d13 addi s10,s9,-1 # ffff <_start-0x7fff0001> -8001233c: 00a9b533 sltu a0,s3,a0 -80012340: 01a37333 and t1,t1,s10 -80012344: 00a282b3 add t0,t0,a0 -80012348: 01031313 slli t1,t1,0x10 -8001234c: 01a8f8b3 and a7,a7,s10 -80012350: 01628b33 add s6,t0,s6 -80012354: 011308b3 add a7,t1,a7 -80012358: 01098333 add t1,s3,a6 -8001235c: 01033833 sltu a6,t1,a6 -80012360: 00612823 sw t1,16(sp) -80012364: 06612223 sw t1,100(sp) -80012368: 014b0333 add t1,s6,s4 -8001236c: 010302b3 add t0,t1,a6 -80012370: 01433a33 sltu s4,t1,s4 -80012374: 0102b833 sltu a6,t0,a6 -80012378: 00d289b3 add s3,t0,a3 -8001237c: 010a6833 or a6,s4,a6 -80012380: 00ab3533 sltu a0,s6,a0 -80012384: 00d9b6b3 sltu a3,s3,a3 -80012388: 00a80533 add a0,a6,a0 -8001238c: 00f989b3 add s3,s3,a5 -80012390: 02412803 lw a6,36(sp) -80012394: 01198333 add t1,s3,a7 -80012398: 011338b3 sltu a7,t1,a7 -8001239c: 00612a23 sw t1,20(sp) -800123a0: 06612423 sw t1,104(sp) -800123a4: 02412303 lw t1,36(sp) -800123a8: 01050533 add a0,a0,a6 -800123ac: 02812803 lw a6,40(sp) -800123b0: 00d50db3 add s11,a0,a3 -800123b4: 00ddb6b3 sltu a3,s11,a3 -800123b8: 00653533 sltu a0,a0,t1 -800123bc: 00f9b7b3 sltu a5,s3,a5 -800123c0: 010d8bb3 add s7,s11,a6 -800123c4: 00d566b3 or a3,a0,a3 -800123c8: 02812503 lw a0,40(sp) -800123cc: 00fb8833 add a6,s7,a5 -800123d0: 04c12303 lw t1,76(sp) -800123d4: 018809b3 add s3,a6,s8 -800123d8: 01198b33 add s6,s3,a7 -800123dc: 00abbbb3 sltu s7,s7,a0 -800123e0: 00f837b3 sltu a5,a6,a5 -800123e4: 00fbe7b3 or a5,s7,a5 -800123e8: 011b38b3 sltu a7,s6,a7 -800123ec: 0189bc33 sltu s8,s3,s8 -800123f0: 00f686b3 add a3,a3,a5 -800123f4: 01035293 srli t0,t1,0x10 -800123f8: 011c6a33 or s4,s8,a7 -800123fc: 01a37333 and t1,t1,s10 -80012400: 02e307b3 mul a5,t1,a4 -80012404: 01468a33 add s4,a3,s4 -80012408: 02e28733 mul a4,t0,a4 -8001240c: 0107d893 srli a7,a5,0x10 -80012410: 026f86b3 mul a3,t6,t1 -80012414: 00d70733 add a4,a4,a3 -80012418: 00e888b3 add a7,a7,a4 -8001241c: 025f8fb3 mul t6,t6,t0 -80012420: 00d8f463 bgeu a7,a3,80012428 <__multf3+0x728> -80012424: 019f8fb3 add t6,t6,s9 -80012428: 03c12983 lw s3,60(sp) -8001242c: 000106b7 lui a3,0x10 -80012430: fff68513 addi a0,a3,-1 # ffff <_start-0x7fff0001> -80012434: 0108dd13 srli s10,a7,0x10 -80012438: 00a8f8b3 and a7,a7,a0 -8001243c: 00a7f7b3 and a5,a5,a0 -80012440: 01fd0d33 add s10,s10,t6 -80012444: 01089893 slli a7,a7,0x10 -80012448: 0109df93 srli t6,s3,0x10 -8001244c: 00a9f9b3 and s3,s3,a0 -80012450: 03fa8cb3 mul s9,s5,t6 -80012454: 00f888b3 add a7,a7,a5 -80012458: 033a8ab3 mul s5,s5,s3 -8001245c: 03c987b3 mul a5,s3,t3 -80012460: 03cf8e33 mul t3,t6,t3 -80012464: 0107d813 srli a6,a5,0x10 -80012468: 01ca8ab3 add s5,s5,t3 -8001246c: 01580ab3 add s5,a6,s5 -80012470: 01caf463 bgeu s5,t3,80012478 <__multf3+0x778> -80012474: 00dc8cb3 add s9,s9,a3 -80012478: 00010bb7 lui s7,0x10 -8001247c: fffb8713 addi a4,s7,-1 # ffff <_start-0x7fff0001> -80012480: 010ad813 srli a6,s5,0x10 -80012484: 01980cb3 add s9,a6,s9 -80012488: 00eaf833 and a6,s5,a4 -8001248c: 00e7f7b3 and a5,a5,a4 -80012490: 01081813 slli a6,a6,0x10 -80012494: 02be86b3 mul a3,t4,a1 -80012498: 00f80833 add a6,a6,a5 -8001249c: 03d90e33 mul t3,s2,t4 -800124a0: 0106d513 srli a0,a3,0x10 -800124a4: 02b387b3 mul a5,t2,a1 -800124a8: 01c787b3 add a5,a5,t3 -800124ac: 00f507b3 add a5,a0,a5 -800124b0: 02790733 mul a4,s2,t2 -800124b4: 01c7f463 bgeu a5,t3,800124bc <__multf3+0x7bc> -800124b8: 01770733 add a4,a4,s7 -800124bc: 0107d513 srli a0,a5,0x10 -800124c0: 00e50733 add a4,a0,a4 -800124c4: 00010bb7 lui s7,0x10 -800124c8: 02e12223 sw a4,36(sp) -800124cc: fffb8713 addi a4,s7,-1 # ffff <_start-0x7fff0001> -800124d0: 00e7f533 and a0,a5,a4 -800124d4: 00e6f6b3 and a3,a3,a4 -800124d8: 03e40e33 mul t3,s0,t5 -800124dc: 01051513 slli a0,a0,0x10 -800124e0: 00d50533 add a0,a0,a3 -800124e4: 03e60733 mul a4,a2,t5 -800124e8: 02c487b3 mul a5,s1,a2 -800124ec: 01075693 srli a3,a4,0x10 -800124f0: 01c787b3 add a5,a5,t3 -800124f4: 00f687b3 add a5,a3,a5 -800124f8: 02848ab3 mul s5,s1,s0 -800124fc: 01c7f463 bgeu a5,t3,80012504 <__multf3+0x804> -80012500: 017a8ab3 add s5,s5,s7 -80012504: 00010db7 lui s11,0x10 -80012508: fffd8e13 addi t3,s11,-1 # ffff <_start-0x7fff0001> -8001250c: 01c7f6b3 and a3,a5,t3 -80012510: 0107db93 srli s7,a5,0x10 -80012514: 011b07b3 add a5,s6,a7 -80012518: 01c77733 and a4,a4,t3 -8001251c: 0117b8b3 sltu a7,a5,a7 -80012520: 01aa0a33 add s4,s4,s10 -80012524: 01069693 slli a3,a3,0x10 -80012528: 00e686b3 add a3,a3,a4 -8001252c: 011a0733 add a4,s4,a7 -80012530: 02e12423 sw a4,40(sp) -80012534: 010787b3 add a5,a5,a6 -80012538: 01aa3a33 sltu s4,s4,s10 -8001253c: 02812d03 lw s10,40(sp) -80012540: 0107b833 sltu a6,a5,a6 -80012544: 01970b33 add s6,a4,s9 -80012548: 010b0733 add a4,s6,a6 -8001254c: 02e12623 sw a4,44(sp) -80012550: 011d38b3 sltu a7,s10,a7 -80012554: 011a6a33 or s4,s4,a7 -80012558: 02c12883 lw a7,44(sp) -8001255c: 02412e03 lw t3,36(sp) -80012560: 00a787b3 add a5,a5,a0 -80012564: 0108b833 sltu a6,a7,a6 -80012568: 019b3b33 sltu s6,s6,s9 -8001256c: 00a7b533 sltu a0,a5,a0 -80012570: 01c70733 add a4,a4,t3 -80012574: 010b6b33 or s6,s6,a6 -80012578: 02412803 lw a6,36(sp) -8001257c: 00a70c33 add s8,a4,a0 -80012580: 015b8bb3 add s7,s7,s5 -80012584: 00d787b3 add a5,a5,a3 -80012588: 00d7b6b3 sltu a3,a5,a3 -8001258c: 017c0ab3 add s5,s8,s7 -80012590: 00da8e33 add t3,s5,a3 -80012594: 01073733 sltu a4,a4,a6 -80012598: 00ac3533 sltu a0,s8,a0 -8001259c: 00a76733 or a4,a4,a0 -800125a0: 00de36b3 sltu a3,t3,a3 -800125a4: 016a0a33 add s4,s4,s6 -800125a8: 017abab3 sltu s5,s5,s7 -800125ac: 00ea0a33 add s4,s4,a4 -800125b0: 00daeab3 or s5,s5,a3 -800125b4: 02ce8833 mul a6,t4,a2 -800125b8: 015a06b3 add a3,s4,s5 -800125bc: 06f12623 sw a5,108(sp) -800125c0: 03d40a33 mul s4,s0,t4 -800125c4: 01085513 srli a0,a6,0x10 -800125c8: 02c38733 mul a4,t2,a2 -800125cc: 01470733 add a4,a4,s4 -800125d0: 00e50733 add a4,a0,a4 -800125d4: 028388b3 mul a7,t2,s0 -800125d8: 01477463 bgeu a4,s4,800125e0 <__multf3+0x8e0> -800125dc: 01b888b3 add a7,a7,s11 -800125e0: 00010a37 lui s4,0x10 -800125e4: 01075513 srli a0,a4,0x10 -800125e8: fffa0a93 addi s5,s4,-1 # ffff <_start-0x7fff0001> -800125ec: 011508b3 add a7,a0,a7 -800125f0: 01577533 and a0,a4,s5 -800125f4: 01587833 and a6,a6,s5 -800125f8: 01051513 slli a0,a0,0x10 -800125fc: 02690ab3 mul s5,s2,t1 -80012600: 01050533 add a0,a0,a6 -80012604: 02b30833 mul a6,t1,a1 -80012608: 02b285b3 mul a1,t0,a1 -8001260c: 01085713 srli a4,a6,0x10 -80012610: 015585b3 add a1,a1,s5 -80012614: 00b70733 add a4,a4,a1 -80012618: 02590933 mul s2,s2,t0 -8001261c: 01577463 bgeu a4,s5,80012624 <__multf3+0x924> -80012620: 01490933 add s2,s2,s4 -80012624: 00010ab7 lui s5,0x10 -80012628: 01075593 srli a1,a4,0x10 -8001262c: fffa8a13 addi s4,s5,-1 # ffff <_start-0x7fff0001> -80012630: 01487833 and a6,a6,s4 -80012634: 01258933 add s2,a1,s2 -80012638: 014775b3 and a1,a4,s4 -8001263c: 01059593 slli a1,a1,0x10 -80012640: 03e98733 mul a4,s3,t5 -80012644: 010585b3 add a1,a1,a6 -80012648: 03ef8f33 mul t5,t6,t5 -8001264c: 01075813 srli a6,a4,0x10 -80012650: 03f48a33 mul s4,s1,t6 -80012654: 033484b3 mul s1,s1,s3 -80012658: 01e484b3 add s1,s1,t5 -8001265c: 009804b3 add s1,a6,s1 -80012660: 01e4f463 bgeu s1,t5,80012668 <__multf3+0x968> -80012664: 015a0a33 add s4,s4,s5 -80012668: 0104db13 srli s6,s1,0x10 -8001266c: 014b0b33 add s6,s6,s4 -80012670: 00010a37 lui s4,0x10 -80012674: fffa0f13 addi t5,s4,-1 # ffff <_start-0x7fff0001> -80012678: 01e4f833 and a6,s1,t5 -8001267c: 01e77733 and a4,a4,t5 -80012680: 026404b3 mul s1,s0,t1 -80012684: 01081813 slli a6,a6,0x10 -80012688: 00e80833 add a6,a6,a4 -8001268c: 02660f33 mul t5,a2,t1 -80012690: 02c28633 mul a2,t0,a2 -80012694: 010f5713 srli a4,t5,0x10 -80012698: 00960633 add a2,a2,s1 -8001269c: 00c70633 add a2,a4,a2 -800126a0: 02540433 mul s0,s0,t0 -800126a4: 00967463 bgeu a2,s1,800126ac <__multf3+0x9ac> -800126a8: 01440433 add s0,s0,s4 -800126ac: 00010a37 lui s4,0x10 -800126b0: 01065713 srli a4,a2,0x10 -800126b4: fffa0493 addi s1,s4,-1 # ffff <_start-0x7fff0001> -800126b8: 00870433 add s0,a4,s0 -800126bc: 00967733 and a4,a2,s1 -800126c0: 009f7f33 and t5,t5,s1 -800126c4: 01071713 slli a4,a4,0x10 -800126c8: 03f384b3 mul s1,t2,t6 -800126cc: 01e70733 add a4,a4,t5 -800126d0: 033383b3 mul t2,t2,s3 -800126d4: 03d98f33 mul t5,s3,t4 -800126d8: 03df8eb3 mul t4,t6,t4 -800126dc: 010f5613 srli a2,t5,0x10 -800126e0: 01d383b3 add t2,t2,t4 -800126e4: 00760633 add a2,a2,t2 -800126e8: 01d67463 bgeu a2,t4,800126f0 <__multf3+0x9f0> -800126ec: 014484b3 add s1,s1,s4 -800126f0: 01065c13 srli s8,a2,0x10 -800126f4: 00010cb7 lui s9,0x10 -800126f8: 009c0c33 add s8,s8,s1 -800126fc: 00ae0e33 add t3,t3,a0 -80012700: fffc8493 addi s1,s9,-1 # ffff <_start-0x7fff0001> -80012704: 00ae3533 sltu a0,t3,a0 -80012708: 011686b3 add a3,a3,a7 -8001270c: 00967633 and a2,a2,s1 -80012710: 00a68d33 add s10,a3,a0 -80012714: 009f7f33 and t5,t5,s1 -80012718: 00be0e33 add t3,t3,a1 -8001271c: 01061613 slli a2,a2,0x10 -80012720: 01e60633 add a2,a2,t5 -80012724: 00be35b3 sltu a1,t3,a1 -80012728: 012d0f33 add t5,s10,s2 -8001272c: 010e0e33 add t3,t3,a6 -80012730: 00bf03b3 add t2,t5,a1 -80012734: 01638eb3 add t4,t2,s6 -80012738: 07c12823 sw t3,112(sp) -8001273c: 010e3e33 sltu t3,t3,a6 -80012740: 01ce8db3 add s11,t4,t3 -80012744: 0116b6b3 sltu a3,a3,a7 -80012748: 00b3b5b3 sltu a1,t2,a1 -8001274c: 00ad3533 sltu a0,s10,a0 -80012750: 012f3933 sltu s2,t5,s2 -80012754: 00a6e533 or a0,a3,a0 -80012758: 00b96933 or s2,s2,a1 -8001275c: 016ebeb3 sltu t4,t4,s6 -80012760: 01cdbe33 sltu t3,s11,t3 -80012764: 01250533 add a0,a0,s2 -80012768: 01ceeeb3 or t4,t4,t3 -8001276c: 00ed8833 add a6,s11,a4 -80012770: 01d50533 add a0,a0,t4 -80012774: 00e83733 sltu a4,a6,a4 -80012778: 00850533 add a0,a0,s0 -8001277c: 00e506b3 add a3,a0,a4 -80012780: 00853433 sltu s0,a0,s0 -80012784: 02698533 mul a0,s3,t1 -80012788: 00c80833 add a6,a6,a2 -8001278c: 00e6b733 sltu a4,a3,a4 -80012790: 00c83633 sltu a2,a6,a2 -80012794: 018686b3 add a3,a3,s8 -80012798: 00c685b3 add a1,a3,a2 -8001279c: 0186bc33 sltu s8,a3,s8 -800127a0: 00c5b633 sltu a2,a1,a2 -800127a4: 07012a23 sw a6,116(sp) -800127a8: 00e46733 or a4,s0,a4 -800127ac: 026f8333 mul t1,t6,t1 -800127b0: 01055693 srli a3,a0,0x10 -800127b4: 00cc6633 or a2,s8,a2 -800127b8: 033289b3 mul s3,t0,s3 -800127bc: 006989b3 add s3,s3,t1 -800127c0: 03f28fb3 mul t6,t0,t6 -800127c4: 013682b3 add t0,a3,s3 -800127c8: 0062f463 bgeu t0,t1,800127d0 <__multf3+0xad0> -800127cc: 019f8fb3 add t6,t6,s9 -800127d0: 0092f6b3 and a3,t0,s1 -800127d4: 01069693 slli a3,a3,0x10 -800127d8: 009574b3 and s1,a0,s1 -800127dc: 0102d293 srli t0,t0,0x10 -800127e0: 009684b3 add s1,a3,s1 -800127e4: 00e282b3 add t0,t0,a4 -800127e8: 01012683 lw a3,16(sp) -800127ec: 02012703 lw a4,32(sp) -800127f0: 009585b3 add a1,a1,s1 -800127f4: 0095b4b3 sltu s1,a1,s1 -800127f8: 00d769b3 or s3,a4,a3 -800127fc: 01412703 lw a4,20(sp) -80012800: 00c282b3 add t0,t0,a2 -80012804: 009282b3 add t0,t0,s1 -80012808: 013769b3 or s3,a4,s3 -8001280c: 01f28fb3 add t6,t0,t6 -80012810: 00d79793 slli a5,a5,0xd -80012814: 06b12c23 sw a1,120(sp) -80012818: 07f12e23 sw t6,124(sp) -8001281c: 0137e7b3 or a5,a5,s3 -80012820: 06010713 addi a4,sp,96 -80012824: 07010593 addi a1,sp,112 -80012828: 00c72683 lw a3,12(a4) -8001282c: 01072603 lw a2,16(a4) -80012830: 00470713 addi a4,a4,4 -80012834: 0136d693 srli a3,a3,0x13 -80012838: 00d61613 slli a2,a2,0xd -8001283c: 00c6e6b3 or a3,a3,a2 -80012840: fed72e23 sw a3,-4(a4) -80012844: fee592e3 bne a1,a4,80012828 <__multf3+0xb28> -80012848: 06012703 lw a4,96(sp) -8001284c: 06812683 lw a3,104(sp) -80012850: 00f037b3 snez a5,a5 -80012854: 00e7e7b3 or a5,a5,a4 -80012858: 04d12c23 sw a3,88(sp) -8001285c: 06c12703 lw a4,108(sp) -80012860: 06412683 lw a3,100(sp) -80012864: 04f12823 sw a5,80(sp) -80012868: 04e12e23 sw a4,92(sp) -8001286c: 04d12a23 sw a3,84(sp) -80012870: 00b71693 slli a3,a4,0xb -80012874: 2006dc63 bgez a3,80012a8c <__multf3+0xd8c> -80012878: 01f79793 slli a5,a5,0x1f -8001287c: 05010713 addi a4,sp,80 -80012880: 05c10593 addi a1,sp,92 -80012884: 00072683 lw a3,0(a4) -80012888: 00472603 lw a2,4(a4) -8001288c: 00470713 addi a4,a4,4 -80012890: 0016d693 srli a3,a3,0x1 -80012894: 01f61613 slli a2,a2,0x1f -80012898: 00c6e6b3 or a3,a3,a2 -8001289c: fed72e23 sw a3,-4(a4) -800128a0: fee592e3 bne a1,a4,80012884 <__multf3+0xb84> -800128a4: 05c12703 lw a4,92(sp) -800128a8: 00f037b3 snez a5,a5 -800128ac: 00175713 srli a4,a4,0x1 -800128b0: 04e12e23 sw a4,92(sp) -800128b4: 05012703 lw a4,80(sp) -800128b8: 00f767b3 or a5,a4,a5 -800128bc: 04f12823 sw a5,80(sp) -800128c0: 01812703 lw a4,24(sp) -800128c4: 000047b7 lui a5,0x4 -800128c8: fff78793 addi a5,a5,-1 # 3fff <_start-0x7fffc001> -800128cc: 00f707b3 add a5,a4,a5 -800128d0: 1ef05063 blez a5,80012ab0 <__multf3+0xdb0> -800128d4: 05012703 lw a4,80(sp) -800128d8: 00777693 andi a3,a4,7 -800128dc: 04068463 beqz a3,80012924 <__multf3+0xc24> -800128e0: 00f77693 andi a3,a4,15 -800128e4: 00400613 li a2,4 -800128e8: 02c68e63 beq a3,a2,80012924 <__multf3+0xc24> -800128ec: 05412683 lw a3,84(sp) -800128f0: 00470713 addi a4,a4,4 -800128f4: 04e12823 sw a4,80(sp) -800128f8: 00473713 sltiu a4,a4,4 -800128fc: 00d706b3 add a3,a4,a3 -80012900: 00e6b733 sltu a4,a3,a4 -80012904: 04d12a23 sw a3,84(sp) -80012908: 05812683 lw a3,88(sp) -8001290c: 00d706b3 add a3,a4,a3 -80012910: 04d12c23 sw a3,88(sp) -80012914: 00e6b6b3 sltu a3,a3,a4 -80012918: 05c12703 lw a4,92(sp) -8001291c: 00e686b3 add a3,a3,a4 -80012920: 04d12e23 sw a3,92(sp) -80012924: 05c12703 lw a4,92(sp) -80012928: 00b71693 slli a3,a4,0xb -8001292c: 0206d063 bgez a3,8001294c <__multf3+0xc4c> -80012930: fff007b7 lui a5,0xfff00 -80012934: fff78793 addi a5,a5,-1 # ffefffff <__BSS_END__+0x7fee93c3> -80012938: 00f77733 and a4,a4,a5 -8001293c: 04e12e23 sw a4,92(sp) -80012940: 01812703 lw a4,24(sp) -80012944: 000047b7 lui a5,0x4 -80012948: 00f707b3 add a5,a4,a5 -8001294c: 05010713 addi a4,sp,80 -80012950: 05c10593 addi a1,sp,92 -80012954: 00072683 lw a3,0(a4) -80012958: 00472603 lw a2,4(a4) -8001295c: 00470713 addi a4,a4,4 -80012960: 0036d693 srli a3,a3,0x3 -80012964: 01d61613 slli a2,a2,0x1d -80012968: 00c6e6b3 or a3,a3,a2 -8001296c: fed72e23 sw a3,-4(a4) -80012970: feb712e3 bne a4,a1,80012954 <__multf3+0xc54> -80012974: 00008737 lui a4,0x8 -80012978: ffe70693 addi a3,a4,-2 # 7ffe <_start-0x7fff8002> -8001297c: 10f6ce63 blt a3,a5,80012a98 <__multf3+0xd98> -80012980: 05c12703 lw a4,92(sp) -80012984: 00375713 srli a4,a4,0x3 -80012988: 04e12e23 sw a4,92(sp) -8001298c: 05c12703 lw a4,92(sp) -80012990: 01179793 slli a5,a5,0x11 -80012994: 0117d793 srli a5,a5,0x11 -80012998: 06e11623 sh a4,108(sp) -8001299c: 00c12703 lw a4,12(sp) -800129a0: 0bc12083 lw ra,188(sp) -800129a4: 0b812403 lw s0,184(sp) -800129a8: 00f71713 slli a4,a4,0xf -800129ac: 00f767b3 or a5,a4,a5 -800129b0: 06f11723 sh a5,110(sp) -800129b4: 00812703 lw a4,8(sp) -800129b8: 05012783 lw a5,80(sp) -800129bc: 0b412483 lw s1,180(sp) -800129c0: 0b012903 lw s2,176(sp) -800129c4: 00f72023 sw a5,0(a4) -800129c8: 05412783 lw a5,84(sp) -800129cc: 0ac12983 lw s3,172(sp) -800129d0: 0a812a03 lw s4,168(sp) -800129d4: 00f72223 sw a5,4(a4) -800129d8: 05812783 lw a5,88(sp) -800129dc: 0a412a83 lw s5,164(sp) -800129e0: 0a012b03 lw s6,160(sp) -800129e4: 00f72423 sw a5,8(a4) -800129e8: 06c12783 lw a5,108(sp) -800129ec: 09c12b83 lw s7,156(sp) -800129f0: 09812c03 lw s8,152(sp) -800129f4: 00f72623 sw a5,12(a4) -800129f8: 09412c83 lw s9,148(sp) -800129fc: 09012d03 lw s10,144(sp) -80012a00: 08c12d83 lw s11,140(sp) -80012a04: 00070513 mv a0,a4 -80012a08: 0c010113 addi sp,sp,192 -80012a0c: 00008067 ret -80012a10: 00912623 sw s1,12(sp) -80012a14: 03012783 lw a5,48(sp) -80012a18: 04f12823 sw a5,80(sp) -80012a1c: 03412783 lw a5,52(sp) -80012a20: 04f12a23 sw a5,84(sp) -80012a24: 03812783 lw a5,56(sp) -80012a28: 04f12c23 sw a5,88(sp) -80012a2c: 03c12783 lw a5,60(sp) -80012a30: 04f12e23 sw a5,92(sp) -80012a34: 00200793 li a5,2 -80012a38: 28fb0863 beq s6,a5,80012cc8 <__multf3+0xfc8> -80012a3c: 00300793 li a5,3 -80012a40: 2afb0263 beq s6,a5,80012ce4 <__multf3+0xfe4> -80012a44: 00100793 li a5,1 -80012a48: e6fb1ce3 bne s6,a5,800128c0 <__multf3+0xbc0> -80012a4c: 04012e23 sw zero,92(sp) -80012a50: 04012c23 sw zero,88(sp) -80012a54: 04012a23 sw zero,84(sp) -80012a58: 04012823 sw zero,80(sp) -80012a5c: 22c0006f j 80012c88 <__multf3+0xf88> -80012a60: 01212623 sw s2,12(sp) -80012a64: 04012783 lw a5,64(sp) -80012a68: 00070b13 mv s6,a4 -80012a6c: 04f12823 sw a5,80(sp) -80012a70: 04412783 lw a5,68(sp) -80012a74: 04f12a23 sw a5,84(sp) -80012a78: 04812783 lw a5,72(sp) -80012a7c: 04f12c23 sw a5,88(sp) -80012a80: 04c12783 lw a5,76(sp) -80012a84: 04f12e23 sw a5,92(sp) -80012a88: fadff06f j 80012a34 <__multf3+0xd34> -80012a8c: 01c12783 lw a5,28(sp) -80012a90: 00f12c23 sw a5,24(sp) -80012a94: e2dff06f j 800128c0 <__multf3+0xbc0> -80012a98: 04012e23 sw zero,92(sp) -80012a9c: 04012c23 sw zero,88(sp) -80012aa0: 04012a23 sw zero,84(sp) -80012aa4: 04012823 sw zero,80(sp) -80012aa8: fff70793 addi a5,a4,-1 -80012aac: ee1ff06f j 8001298c <__multf3+0xc8c> -80012ab0: 00100693 li a3,1 -80012ab4: 40f686b3 sub a3,a3,a5 -80012ab8: 07400793 li a5,116 -80012abc: 1cd7ca63 blt a5,a3,80012c90 <__multf3+0xf90> -80012ac0: 4056d513 srai a0,a3,0x5 -80012ac4: 00000793 li a5,0 -80012ac8: 00000713 li a4,0 -80012acc: 04a71663 bne a4,a0,80012b18 <__multf3+0xe18> -80012ad0: 01f6f693 andi a3,a3,31 -80012ad4: 00251593 slli a1,a0,0x2 -80012ad8: 04069e63 bnez a3,80012b34 <__multf3+0xe34> -80012adc: 00300613 li a2,3 -80012ae0: 05010713 addi a4,sp,80 -80012ae4: 40a60633 sub a2,a2,a0 -80012ae8: 00b70833 add a6,a4,a1 -80012aec: 00082803 lw a6,0(a6) -80012af0: 00168693 addi a3,a3,1 -80012af4: 00470713 addi a4,a4,4 -80012af8: ff072e23 sw a6,-4(a4) -80012afc: fed656e3 bge a2,a3,80012ae8 <__multf3+0xde8> -80012b00: 00400713 li a4,4 -80012b04: 40a70533 sub a0,a4,a0 -80012b08: 00100713 li a4,1 -80012b0c: 08a05063 blez a0,80012b8c <__multf3+0xe8c> -80012b10: 00050713 mv a4,a0 -80012b14: 0780006f j 80012b8c <__multf3+0xe8c> -80012b18: 00271613 slli a2,a4,0x2 -80012b1c: 05010593 addi a1,sp,80 -80012b20: 00c58633 add a2,a1,a2 -80012b24: 00062603 lw a2,0(a2) -80012b28: 00170713 addi a4,a4,1 -80012b2c: 00c7e7b3 or a5,a5,a2 -80012b30: f9dff06f j 80012acc <__multf3+0xdcc> -80012b34: 08010713 addi a4,sp,128 -80012b38: 00b70733 add a4,a4,a1 -80012b3c: fd072703 lw a4,-48(a4) -80012b40: 02000893 li a7,32 -80012b44: 40d888b3 sub a7,a7,a3 -80012b48: 01171733 sll a4,a4,a7 -80012b4c: 00e7e7b3 or a5,a5,a4 -80012b50: 00300613 li a2,3 -80012b54: 05010713 addi a4,sp,80 -80012b58: 00b705b3 add a1,a4,a1 -80012b5c: 00000813 li a6,0 -80012b60: 40a60633 sub a2,a2,a0 -80012b64: 00458593 addi a1,a1,4 -80012b68: 02c84663 blt a6,a2,80012b94 <__multf3+0xe94> -80012b6c: 08010593 addi a1,sp,128 -80012b70: 00261613 slli a2,a2,0x2 -80012b74: 00c58633 add a2,a1,a2 -80012b78: 05c12583 lw a1,92(sp) -80012b7c: 00400713 li a4,4 -80012b80: 40a70733 sub a4,a4,a0 -80012b84: 00d5d6b3 srl a3,a1,a3 -80012b88: fcd62823 sw a3,-48(a2) -80012b8c: 00400613 li a2,4 -80012b90: 0440006f j 80012bd4 <__multf3+0xed4> -80012b94: 00281313 slli t1,a6,0x2 -80012b98: 05010713 addi a4,sp,80 -80012b9c: 0005ae03 lw t3,0(a1) -80012ba0: 00670333 add t1,a4,t1 -80012ba4: ffc5a703 lw a4,-4(a1) -80012ba8: 011e1e33 sll t3,t3,a7 -80012bac: 00180813 addi a6,a6,1 -80012bb0: 00d75733 srl a4,a4,a3 -80012bb4: 01c76733 or a4,a4,t3 -80012bb8: 00e32023 sw a4,0(t1) -80012bbc: fa9ff06f j 80012b64 <__multf3+0xe64> -80012bc0: 00271693 slli a3,a4,0x2 -80012bc4: 05010593 addi a1,sp,80 -80012bc8: 00d586b3 add a3,a1,a3 -80012bcc: 0006a023 sw zero,0(a3) -80012bd0: 00170713 addi a4,a4,1 -80012bd4: fec716e3 bne a4,a2,80012bc0 <__multf3+0xec0> -80012bd8: 05012683 lw a3,80(sp) -80012bdc: 00f037b3 snez a5,a5 -80012be0: 00d7e7b3 or a5,a5,a3 -80012be4: 04f12823 sw a5,80(sp) -80012be8: 0077f693 andi a3,a5,7 -80012bec: 04068263 beqz a3,80012c30 <__multf3+0xf30> -80012bf0: 00f7f693 andi a3,a5,15 -80012bf4: 02e68e63 beq a3,a4,80012c30 <__multf3+0xf30> -80012bf8: 05412703 lw a4,84(sp) -80012bfc: 00478793 addi a5,a5,4 # 4004 <_start-0x7fffbffc> -80012c00: 04f12823 sw a5,80(sp) -80012c04: 0047b793 sltiu a5,a5,4 -80012c08: 00e78733 add a4,a5,a4 -80012c0c: 00f737b3 sltu a5,a4,a5 -80012c10: 04e12a23 sw a4,84(sp) -80012c14: 05812703 lw a4,88(sp) -80012c18: 00e78733 add a4,a5,a4 -80012c1c: 04e12c23 sw a4,88(sp) -80012c20: 00f73733 sltu a4,a4,a5 -80012c24: 05c12783 lw a5,92(sp) -80012c28: 00f70733 add a4,a4,a5 -80012c2c: 04e12e23 sw a4,92(sp) -80012c30: 05c12783 lw a5,92(sp) -80012c34: 00c79713 slli a4,a5,0xc -80012c38: 00075e63 bgez a4,80012c54 <__multf3+0xf54> -80012c3c: 04012e23 sw zero,92(sp) -80012c40: 04012c23 sw zero,88(sp) -80012c44: 04012a23 sw zero,84(sp) -80012c48: 04012823 sw zero,80(sp) -80012c4c: 00100793 li a5,1 -80012c50: d3dff06f j 8001298c <__multf3+0xc8c> -80012c54: 05010793 addi a5,sp,80 -80012c58: 05c10613 addi a2,sp,92 -80012c5c: 0007a703 lw a4,0(a5) -80012c60: 0047a683 lw a3,4(a5) -80012c64: 00478793 addi a5,a5,4 -80012c68: 00375713 srli a4,a4,0x3 -80012c6c: 01d69693 slli a3,a3,0x1d -80012c70: 00d76733 or a4,a4,a3 -80012c74: fee7ae23 sw a4,-4(a5) -80012c78: fef612e3 bne a2,a5,80012c5c <__multf3+0xf5c> -80012c7c: 05c12783 lw a5,92(sp) -80012c80: 0037d793 srli a5,a5,0x3 -80012c84: 04f12e23 sw a5,92(sp) -80012c88: 00000793 li a5,0 -80012c8c: d01ff06f j 8001298c <__multf3+0xc8c> -80012c90: 05412783 lw a5,84(sp) -80012c94: 05012703 lw a4,80(sp) -80012c98: 00f76733 or a4,a4,a5 -80012c9c: 05812783 lw a5,88(sp) -80012ca0: 00f76733 or a4,a4,a5 -80012ca4: 05c12783 lw a5,92(sp) -80012ca8: 00f76733 or a4,a4,a5 -80012cac: 00000793 li a5,0 -80012cb0: cc070ee3 beqz a4,8001298c <__multf3+0xc8c> -80012cb4: 04012e23 sw zero,92(sp) -80012cb8: 04012c23 sw zero,88(sp) -80012cbc: 04012a23 sw zero,84(sp) -80012cc0: 04012823 sw zero,80(sp) -80012cc4: cc9ff06f j 8001298c <__multf3+0xc8c> -80012cc8: 000087b7 lui a5,0x8 -80012ccc: 04012e23 sw zero,92(sp) -80012cd0: 04012c23 sw zero,88(sp) -80012cd4: 04012a23 sw zero,84(sp) -80012cd8: 04012823 sw zero,80(sp) -80012cdc: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012ce0: cadff06f j 8001298c <__multf3+0xc8c> -80012ce4: 000087b7 lui a5,0x8 -80012ce8: 04f12e23 sw a5,92(sp) -80012cec: 04012c23 sw zero,88(sp) -80012cf0: 04012a23 sw zero,84(sp) -80012cf4: 04012823 sw zero,80(sp) -80012cf8: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012cfc: 00012623 sw zero,12(sp) -80012d00: c8dff06f j 8001298c <__multf3+0xc8c> +80011c3c <__multf3>: +80011c3c: f4010113 addi sp,sp,-192 +80011c40: 0a912a23 sw s1,180(sp) +80011c44: 00c5a483 lw s1,12(a1) +80011c48: 0005a683 lw a3,0(a1) +80011c4c: 0045a783 lw a5,4(a1) +80011c50: 00a12423 sw a0,8(sp) +80011c54: 0085a503 lw a0,8(a1) +80011c58: 01049713 slli a4,s1,0x10 +80011c5c: 0b212823 sw s2,176(sp) +80011c60: 0b312623 sw s3,172(sp) +80011c64: 00c62903 lw s2,12(a2) # 7ff0000c <_start-0xffff4> +80011c68: 00062983 lw s3,0(a2) +80011c6c: 0b412423 sw s4,168(sp) +80011c70: 0b512223 sw s5,164(sp) +80011c74: 00862a03 lw s4,8(a2) +80011c78: 00462a83 lw s5,4(a2) +80011c7c: 00008637 lui a2,0x8 +80011c80: 0a812c23 sw s0,184(sp) +80011c84: 01075713 srli a4,a4,0x10 +80011c88: 0104d413 srli s0,s1,0x10 +80011c8c: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +80011c90: 06912623 sw s1,108(sp) +80011c94: 0a112e23 sw ra,188(sp) +80011c98: 0b612023 sw s6,160(sp) +80011c9c: 09712e23 sw s7,156(sp) +80011ca0: 09812c23 sw s8,152(sp) +80011ca4: 09912a23 sw s9,148(sp) +80011ca8: 09a12823 sw s10,144(sp) +80011cac: 09b12623 sw s11,140(sp) +80011cb0: 06d12023 sw a3,96(sp) +80011cb4: 06f12223 sw a5,100(sp) +80011cb8: 06a12423 sw a0,104(sp) +80011cbc: 02d12823 sw a3,48(sp) +80011cc0: 02f12a23 sw a5,52(sp) +80011cc4: 02a12c23 sw a0,56(sp) +80011cc8: 02e12e23 sw a4,60(sp) +80011ccc: 00c47433 and s0,s0,a2 +80011cd0: 01f4d493 srli s1,s1,0x1f +80011cd4: 12040863 beqz s0,80011e04 <__multf3+0x1c8> +80011cd8: 24c40663 beq s0,a2,80011f24 <__multf3+0x2e8> +80011cdc: 000107b7 lui a5,0x10 +80011ce0: 00f767b3 or a5,a4,a5 +80011ce4: 02f12e23 sw a5,60(sp) +80011ce8: 03010613 addi a2,sp,48 +80011cec: 03c10793 addi a5,sp,60 +80011cf0: 0007a703 lw a4,0(a5) # 10000 <_start-0x7fff0000> +80011cf4: ffc7a683 lw a3,-4(a5) +80011cf8: ffc78793 addi a5,a5,-4 +80011cfc: 00371713 slli a4,a4,0x3 +80011d00: 01d6d693 srli a3,a3,0x1d +80011d04: 00d76733 or a4,a4,a3 +80011d08: 00e7a223 sw a4,4(a5) +80011d0c: fef612e3 bne a2,a5,80011cf0 <__multf3+0xb4> +80011d10: 03012783 lw a5,48(sp) +80011d14: ffffc537 lui a0,0xffffc +80011d18: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe53c5> +80011d1c: 00379793 slli a5,a5,0x3 +80011d20: 02f12823 sw a5,48(sp) +80011d24: 00a40433 add s0,s0,a0 +80011d28: 00000b13 li s6,0 +80011d2c: 01091513 slli a0,s2,0x10 +80011d30: 00008737 lui a4,0x8 +80011d34: 01095793 srli a5,s2,0x10 +80011d38: 01055513 srli a0,a0,0x10 +80011d3c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80011d40: 07212623 sw s2,108(sp) +80011d44: 07312023 sw s3,96(sp) +80011d48: 07512223 sw s5,100(sp) +80011d4c: 07412423 sw s4,104(sp) +80011d50: 05312023 sw s3,64(sp) +80011d54: 05512223 sw s5,68(sp) +80011d58: 05412423 sw s4,72(sp) +80011d5c: 04a12623 sw a0,76(sp) +80011d60: 00e7f7b3 and a5,a5,a4 +80011d64: 01f95913 srli s2,s2,0x1f +80011d68: 1e078263 beqz a5,80011f4c <__multf3+0x310> +80011d6c: 30e78063 beq a5,a4,8001206c <__multf3+0x430> +80011d70: 00010a37 lui s4,0x10 +80011d74: 01456a33 or s4,a0,s4 +80011d78: 05412623 sw s4,76(sp) +80011d7c: 04010593 addi a1,sp,64 +80011d80: 04c10713 addi a4,sp,76 +80011d84: 00072683 lw a3,0(a4) +80011d88: ffc72603 lw a2,-4(a4) +80011d8c: ffc70713 addi a4,a4,-4 +80011d90: 00369693 slli a3,a3,0x3 +80011d94: 01d65613 srli a2,a2,0x1d +80011d98: 00c6e6b3 or a3,a3,a2 +80011d9c: 00d72223 sw a3,4(a4) +80011da0: fee592e3 bne a1,a4,80011d84 <__multf3+0x148> +80011da4: 04012703 lw a4,64(sp) +80011da8: ffffc537 lui a0,0xffffc +80011dac: 00150513 addi a0,a0,1 # ffffc001 <__BSS_END__+0x7ffe53c5> +80011db0: 00371713 slli a4,a4,0x3 +80011db4: 04e12023 sw a4,64(sp) +80011db8: 00a787b3 add a5,a5,a0 +80011dbc: 00000713 li a4,0 +80011dc0: 008787b3 add a5,a5,s0 +80011dc4: 00f12e23 sw a5,28(sp) +80011dc8: 00178793 addi a5,a5,1 +80011dcc: 00f12c23 sw a5,24(sp) +80011dd0: 002b1793 slli a5,s6,0x2 +80011dd4: 0124c6b3 xor a3,s1,s2 +80011dd8: 00e7e7b3 or a5,a5,a4 +80011ddc: 00d12623 sw a3,12(sp) +80011de0: fff78793 addi a5,a5,-1 +80011de4: 00e00693 li a3,14 +80011de8: 2af6e663 bltu a3,a5,80012094 <__multf3+0x458> +80011dec: 800156b7 lui a3,0x80015 +80011df0: 00279793 slli a5,a5,0x2 +80011df4: 73868693 addi a3,a3,1848 # 80015738 <__BSS_END__+0xffffeafc> +80011df8: 00d787b3 add a5,a5,a3 +80011dfc: 0007a783 lw a5,0(a5) +80011e00: 00078067 jr a5 +80011e04: 00d7e633 or a2,a5,a3 +80011e08: 00a66633 or a2,a2,a0 +80011e0c: 00e66633 or a2,a2,a4 +80011e10: 12060863 beqz a2,80011f40 <__multf3+0x304> +80011e14: 06070063 beqz a4,80011e74 <__multf3+0x238> +80011e18: 00070513 mv a0,a4 +80011e1c: 2e9020ef jal ra,80014904 <__clzsi2> +80011e20: ff450693 addi a3,a0,-12 +80011e24: 4056d793 srai a5,a3,0x5 +80011e28: 01f6f693 andi a3,a3,31 +80011e2c: 06068e63 beqz a3,80011ea8 <__multf3+0x26c> +80011e30: ffc00713 li a4,-4 +80011e34: 02e78733 mul a4,a5,a4 +80011e38: 03010313 addi t1,sp,48 +80011e3c: 02000813 li a6,32 +80011e40: 00279593 slli a1,a5,0x2 +80011e44: 40d80833 sub a6,a6,a3 +80011e48: 00c70713 addi a4,a4,12 +80011e4c: 00e30733 add a4,t1,a4 +80011e50: 08e31463 bne t1,a4,80011ed8 <__multf3+0x29c> +80011e54: 08010713 addi a4,sp,128 +80011e58: 00b705b3 add a1,a4,a1 +80011e5c: 03012703 lw a4,48(sp) +80011e60: fff78793 addi a5,a5,-1 +80011e64: 00d716b3 sll a3,a4,a3 +80011e68: fad5a823 sw a3,-80(a1) +80011e6c: fff00693 li a3,-1 +80011e70: 0a00006f j 80011f10 <__multf3+0x2d4> +80011e74: 00050863 beqz a0,80011e84 <__multf3+0x248> +80011e78: 28d020ef jal ra,80014904 <__clzsi2> +80011e7c: 02050513 addi a0,a0,32 +80011e80: fa1ff06f j 80011e20 <__multf3+0x1e4> +80011e84: 00078a63 beqz a5,80011e98 <__multf3+0x25c> +80011e88: 00078513 mv a0,a5 +80011e8c: 279020ef jal ra,80014904 <__clzsi2> +80011e90: 04050513 addi a0,a0,64 +80011e94: f8dff06f j 80011e20 <__multf3+0x1e4> +80011e98: 00068513 mv a0,a3 +80011e9c: 269020ef jal ra,80014904 <__clzsi2> +80011ea0: 06050513 addi a0,a0,96 +80011ea4: f7dff06f j 80011e20 <__multf3+0x1e4> +80011ea8: ffc00613 li a2,-4 +80011eac: 02c78633 mul a2,a5,a2 +80011eb0: 03c10713 addi a4,sp,60 +80011eb4: 00300693 li a3,3 +80011eb8: 00c705b3 add a1,a4,a2 +80011ebc: 0005a583 lw a1,0(a1) +80011ec0: fff68693 addi a3,a3,-1 +80011ec4: ffc70713 addi a4,a4,-4 +80011ec8: 00b72223 sw a1,4(a4) +80011ecc: fef6d6e3 bge a3,a5,80011eb8 <__multf3+0x27c> +80011ed0: fff78793 addi a5,a5,-1 +80011ed4: f99ff06f j 80011e6c <__multf3+0x230> +80011ed8: ffc72603 lw a2,-4(a4) +80011edc: 00072883 lw a7,0(a4) +80011ee0: 00b70e33 add t3,a4,a1 +80011ee4: 01065633 srl a2,a2,a6 +80011ee8: 00d898b3 sll a7,a7,a3 +80011eec: 01166633 or a2,a2,a7 +80011ef0: 00ce2023 sw a2,0(t3) +80011ef4: ffc70713 addi a4,a4,-4 +80011ef8: f59ff06f j 80011e50 <__multf3+0x214> +80011efc: 00279713 slli a4,a5,0x2 +80011f00: 03010613 addi a2,sp,48 +80011f04: 00e60733 add a4,a2,a4 +80011f08: 00072023 sw zero,0(a4) +80011f0c: fff78793 addi a5,a5,-1 +80011f10: fed796e3 bne a5,a3,80011efc <__multf3+0x2c0> +80011f14: ffffc437 lui s0,0xffffc +80011f18: 01140413 addi s0,s0,17 # ffffc011 <__BSS_END__+0x7ffe53d5> +80011f1c: 40a40433 sub s0,s0,a0 +80011f20: e09ff06f j 80011d28 <__multf3+0xec> +80011f24: 00d7e7b3 or a5,a5,a3 +80011f28: 00a7e7b3 or a5,a5,a0 +80011f2c: 00e7e7b3 or a5,a5,a4 +80011f30: 00300b13 li s6,3 +80011f34: de079ce3 bnez a5,80011d2c <__multf3+0xf0> +80011f38: 00200b13 li s6,2 +80011f3c: df1ff06f j 80011d2c <__multf3+0xf0> +80011f40: 00000413 li s0,0 +80011f44: 00100b13 li s6,1 +80011f48: de5ff06f j 80011d2c <__multf3+0xf0> +80011f4c: 0159e7b3 or a5,s3,s5 +80011f50: 0147e7b3 or a5,a5,s4 +80011f54: 00a7e7b3 or a5,a5,a0 +80011f58: 12078863 beqz a5,80012088 <__multf3+0x44c> +80011f5c: 04050e63 beqz a0,80011fb8 <__multf3+0x37c> +80011f60: 1a5020ef jal ra,80014904 <__clzsi2> +80011f64: ff450693 addi a3,a0,-12 +80011f68: 4056d793 srai a5,a3,0x5 +80011f6c: 01f6f693 andi a3,a3,31 +80011f70: 08068063 beqz a3,80011ff0 <__multf3+0x3b4> +80011f74: ffc00713 li a4,-4 +80011f78: 02e78733 mul a4,a5,a4 +80011f7c: 04010313 addi t1,sp,64 +80011f80: 02000813 li a6,32 +80011f84: 00279593 slli a1,a5,0x2 +80011f88: 40d80833 sub a6,a6,a3 +80011f8c: 00c70713 addi a4,a4,12 +80011f90: 00e30733 add a4,t1,a4 +80011f94: 08e31663 bne t1,a4,80012020 <__multf3+0x3e4> +80011f98: 08010713 addi a4,sp,128 +80011f9c: 00b705b3 add a1,a4,a1 +80011fa0: 04012703 lw a4,64(sp) +80011fa4: fff78793 addi a5,a5,-1 +80011fa8: 00d716b3 sll a3,a4,a3 +80011fac: fcd5a023 sw a3,-64(a1) +80011fb0: fff00693 li a3,-1 +80011fb4: 0a40006f j 80012058 <__multf3+0x41c> +80011fb8: 000a0a63 beqz s4,80011fcc <__multf3+0x390> +80011fbc: 000a0513 mv a0,s4 +80011fc0: 145020ef jal ra,80014904 <__clzsi2> +80011fc4: 02050513 addi a0,a0,32 +80011fc8: f9dff06f j 80011f64 <__multf3+0x328> +80011fcc: 000a8a63 beqz s5,80011fe0 <__multf3+0x3a4> +80011fd0: 000a8513 mv a0,s5 +80011fd4: 131020ef jal ra,80014904 <__clzsi2> +80011fd8: 04050513 addi a0,a0,64 +80011fdc: f89ff06f j 80011f64 <__multf3+0x328> +80011fe0: 00098513 mv a0,s3 +80011fe4: 121020ef jal ra,80014904 <__clzsi2> +80011fe8: 06050513 addi a0,a0,96 +80011fec: f79ff06f j 80011f64 <__multf3+0x328> +80011ff0: ffc00613 li a2,-4 +80011ff4: 02c78633 mul a2,a5,a2 +80011ff8: 04c10713 addi a4,sp,76 +80011ffc: 00300693 li a3,3 +80012000: 00c705b3 add a1,a4,a2 +80012004: 0005a583 lw a1,0(a1) +80012008: fff68693 addi a3,a3,-1 +8001200c: ffc70713 addi a4,a4,-4 +80012010: 00b72223 sw a1,4(a4) +80012014: fef6d6e3 bge a3,a5,80012000 <__multf3+0x3c4> +80012018: fff78793 addi a5,a5,-1 +8001201c: f95ff06f j 80011fb0 <__multf3+0x374> +80012020: ffc72603 lw a2,-4(a4) +80012024: 00072883 lw a7,0(a4) +80012028: 00b70e33 add t3,a4,a1 +8001202c: 01065633 srl a2,a2,a6 +80012030: 00d898b3 sll a7,a7,a3 +80012034: 01166633 or a2,a2,a7 +80012038: 00ce2023 sw a2,0(t3) +8001203c: ffc70713 addi a4,a4,-4 +80012040: f55ff06f j 80011f94 <__multf3+0x358> +80012044: 00279713 slli a4,a5,0x2 +80012048: 04010613 addi a2,sp,64 +8001204c: 00e60733 add a4,a2,a4 +80012050: 00072023 sw zero,0(a4) +80012054: fff78793 addi a5,a5,-1 +80012058: fed796e3 bne a5,a3,80012044 <__multf3+0x408> +8001205c: ffffc7b7 lui a5,0xffffc +80012060: 01178793 addi a5,a5,17 # ffffc011 <__BSS_END__+0x7ffe53d5> +80012064: 40a787b3 sub a5,a5,a0 +80012068: d55ff06f j 80011dbc <__multf3+0x180> +8001206c: 0159e9b3 or s3,s3,s5 +80012070: 0149ea33 or s4,s3,s4 +80012074: 00aa6a33 or s4,s4,a0 +80012078: 00300713 li a4,3 +8001207c: d40a12e3 bnez s4,80011dc0 <__multf3+0x184> +80012080: 00200713 li a4,2 +80012084: d3dff06f j 80011dc0 <__multf3+0x184> +80012088: 00000793 li a5,0 +8001208c: 00100713 li a4,1 +80012090: d31ff06f j 80011dc0 <__multf3+0x184> +80012094: 03012703 lw a4,48(sp) +80012098: 04012e03 lw t3,64(sp) +8001209c: 00010537 lui a0,0x10 +800120a0: fff50693 addi a3,a0,-1 # ffff <_start-0x7fff0001> +800120a4: 01075f93 srli t6,a4,0x10 +800120a8: 010e5a93 srli s5,t3,0x10 +800120ac: 00d77733 and a4,a4,a3 +800120b0: 00de7e33 and t3,t3,a3 +800120b4: 02ea87b3 mul a5,s5,a4 +800120b8: 02ee0633 mul a2,t3,a4 +800120bc: 03cf8833 mul a6,t6,t3 +800120c0: 010785b3 add a1,a5,a6 +800120c4: 01065793 srli a5,a2,0x10 +800120c8: 00b787b3 add a5,a5,a1 +800120cc: 035f8bb3 mul s7,t6,s5 +800120d0: 0107f463 bgeu a5,a6,800120d8 <__multf3+0x49c> +800120d4: 00ab8bb3 add s7,s7,a0 +800120d8: 04412f03 lw t5,68(sp) +800120dc: 0107d993 srli s3,a5,0x10 +800120e0: 00d7f7b3 and a5,a5,a3 +800120e4: 00d67633 and a2,a2,a3 +800120e8: 01079793 slli a5,a5,0x10 +800120ec: 00c787b3 add a5,a5,a2 +800120f0: 010f5493 srli s1,t5,0x10 +800120f4: 00df7f33 and t5,t5,a3 +800120f8: 02ef06b3 mul a3,t5,a4 +800120fc: 02f12023 sw a5,32(sp) +80012100: 06f12023 sw a5,96(sp) +80012104: 03ef8633 mul a2,t6,t5 +80012108: 02e487b3 mul a5,s1,a4 +8001210c: 00c78533 add a0,a5,a2 +80012110: 0106d793 srli a5,a3,0x10 +80012114: 00a787b3 add a5,a5,a0 +80012118: 029f8b33 mul s6,t6,s1 +8001211c: 00c7f663 bgeu a5,a2,80012128 <__multf3+0x4ec> +80012120: 00010637 lui a2,0x10 +80012124: 00cb0b33 add s6,s6,a2 +80012128: 00010637 lui a2,0x10 +8001212c: fff60593 addi a1,a2,-1 # ffff <_start-0x7fff0001> +80012130: 00b7f533 and a0,a5,a1 +80012134: 0107d293 srli t0,a5,0x10 +80012138: 03412783 lw a5,52(sp) +8001213c: 00b6f6b3 and a3,a3,a1 +80012140: 01051513 slli a0,a0,0x10 +80012144: 0107d913 srli s2,a5,0x10 +80012148: 00b7f5b3 and a1,a5,a1 +8001214c: 02ba87b3 mul a5,s5,a1 +80012150: 00d50533 add a0,a0,a3 +80012154: 00a989b3 add s3,s3,a0 +80012158: 03c586b3 mul a3,a1,t3 +8001215c: 03c90333 mul t1,s2,t3 +80012160: 00678833 add a6,a5,t1 +80012164: 0106d793 srli a5,a3,0x10 +80012168: 010787b3 add a5,a5,a6 +8001216c: 032a88b3 mul a7,s5,s2 +80012170: 0067f463 bgeu a5,t1,80012178 <__multf3+0x53c> +80012174: 00c888b3 add a7,a7,a2 +80012178: 00010337 lui t1,0x10 +8001217c: fff30613 addi a2,t1,-1 # ffff <_start-0x7fff0001> +80012180: 0107da13 srli s4,a5,0x10 +80012184: 00c7f833 and a6,a5,a2 +80012188: 00c6f6b3 and a3,a3,a2 +8001218c: 011a0a33 add s4,s4,a7 +80012190: 01081813 slli a6,a6,0x10 +80012194: 03e588b3 mul a7,a1,t5 +80012198: 00d80833 add a6,a6,a3 +8001219c: 03e90633 mul a2,s2,t5 +800121a0: 0108d693 srli a3,a7,0x10 +800121a4: 02b487b3 mul a5,s1,a1 +800121a8: 00c787b3 add a5,a5,a2 +800121ac: 00f687b3 add a5,a3,a5 +800121b0: 03248eb3 mul t4,s1,s2 +800121b4: 00c7f463 bgeu a5,a2,800121bc <__multf3+0x580> +800121b8: 006e8eb3 add t4,t4,t1 +800121bc: 0107d693 srli a3,a5,0x10 +800121c0: 01d686b3 add a3,a3,t4 +800121c4: 00010437 lui s0,0x10 +800121c8: 04812e83 lw t4,72(sp) +800121cc: fff40613 addi a2,s0,-1 # ffff <_start-0x7fff0001> +800121d0: 02d12223 sw a3,36(sp) +800121d4: 00c7f6b3 and a3,a5,a2 +800121d8: 00c8f8b3 and a7,a7,a2 +800121dc: 010ed393 srli t2,t4,0x10 +800121e0: 01069693 slli a3,a3,0x10 +800121e4: 00cefeb3 and t4,t4,a2 +800121e8: 02ee8333 mul t1,t4,a4 +800121ec: 011686b3 add a3,a3,a7 +800121f0: 03df8c33 mul s8,t6,t4 +800121f4: 02e388b3 mul a7,t2,a4 +800121f8: 018887b3 add a5,a7,s8 +800121fc: 01035893 srli a7,t1,0x10 +80012200: 00f888b3 add a7,a7,a5 +80012204: 027f8633 mul a2,t6,t2 +80012208: 0188f463 bgeu a7,s8,80012210 <__multf3+0x5d4> +8001220c: 00860633 add a2,a2,s0 +80012210: 0108d793 srli a5,a7,0x10 +80012214: 00010cb7 lui s9,0x10 +80012218: 00c787b3 add a5,a5,a2 +8001221c: fffc8613 addi a2,s9,-1 # ffff <_start-0x7fff0001> +80012220: 02f12423 sw a5,40(sp) +80012224: 00c8f7b3 and a5,a7,a2 +80012228: 03812883 lw a7,56(sp) +8001222c: 00c37333 and t1,t1,a2 +80012230: 01079793 slli a5,a5,0x10 +80012234: 0108d413 srli s0,a7,0x10 +80012238: 00c8f633 and a2,a7,a2 +8001223c: 03c608b3 mul a7,a2,t3 +80012240: 006787b3 add a5,a5,t1 +80012244: 03c40d33 mul s10,s0,t3 +80012248: 0108dd93 srli s11,a7,0x10 +8001224c: 02ca8333 mul t1,s5,a2 +80012250: 01a30333 add t1,t1,s10 +80012254: 006d8333 add t1,s11,t1 +80012258: 028a8c33 mul s8,s5,s0 +8001225c: 01a37463 bgeu t1,s10,80012264 <__multf3+0x628> +80012260: 019c0c33 add s8,s8,s9 +80012264: 01035c93 srli s9,t1,0x10 +80012268: 018c8c33 add s8,s9,s8 +8001226c: 00010cb7 lui s9,0x10 +80012270: 013b89b3 add s3,s7,s3 +80012274: fffc8d13 addi s10,s9,-1 # ffff <_start-0x7fff0001> +80012278: 00a9b533 sltu a0,s3,a0 +8001227c: 01a37333 and t1,t1,s10 +80012280: 00a282b3 add t0,t0,a0 +80012284: 01031313 slli t1,t1,0x10 +80012288: 01a8f8b3 and a7,a7,s10 +8001228c: 01628b33 add s6,t0,s6 +80012290: 011308b3 add a7,t1,a7 +80012294: 01098333 add t1,s3,a6 +80012298: 01033833 sltu a6,t1,a6 +8001229c: 00612823 sw t1,16(sp) +800122a0: 06612223 sw t1,100(sp) +800122a4: 014b0333 add t1,s6,s4 +800122a8: 010302b3 add t0,t1,a6 +800122ac: 01433a33 sltu s4,t1,s4 +800122b0: 0102b833 sltu a6,t0,a6 +800122b4: 00d289b3 add s3,t0,a3 +800122b8: 010a6833 or a6,s4,a6 +800122bc: 00ab3533 sltu a0,s6,a0 +800122c0: 00d9b6b3 sltu a3,s3,a3 +800122c4: 00a80533 add a0,a6,a0 +800122c8: 00f989b3 add s3,s3,a5 +800122cc: 02412803 lw a6,36(sp) +800122d0: 01198333 add t1,s3,a7 +800122d4: 011338b3 sltu a7,t1,a7 +800122d8: 00612a23 sw t1,20(sp) +800122dc: 06612423 sw t1,104(sp) +800122e0: 02412303 lw t1,36(sp) +800122e4: 01050533 add a0,a0,a6 +800122e8: 02812803 lw a6,40(sp) +800122ec: 00d50db3 add s11,a0,a3 +800122f0: 00ddb6b3 sltu a3,s11,a3 +800122f4: 00653533 sltu a0,a0,t1 +800122f8: 00f9b7b3 sltu a5,s3,a5 +800122fc: 010d8bb3 add s7,s11,a6 +80012300: 00d566b3 or a3,a0,a3 +80012304: 02812503 lw a0,40(sp) +80012308: 00fb8833 add a6,s7,a5 +8001230c: 04c12303 lw t1,76(sp) +80012310: 018809b3 add s3,a6,s8 +80012314: 01198b33 add s6,s3,a7 +80012318: 00abbbb3 sltu s7,s7,a0 +8001231c: 00f837b3 sltu a5,a6,a5 +80012320: 00fbe7b3 or a5,s7,a5 +80012324: 011b38b3 sltu a7,s6,a7 +80012328: 0189bc33 sltu s8,s3,s8 +8001232c: 00f686b3 add a3,a3,a5 +80012330: 01035293 srli t0,t1,0x10 +80012334: 011c6a33 or s4,s8,a7 +80012338: 01a37333 and t1,t1,s10 +8001233c: 02e307b3 mul a5,t1,a4 +80012340: 01468a33 add s4,a3,s4 +80012344: 02e28733 mul a4,t0,a4 +80012348: 0107d893 srli a7,a5,0x10 +8001234c: 026f86b3 mul a3,t6,t1 +80012350: 00d70733 add a4,a4,a3 +80012354: 00e888b3 add a7,a7,a4 +80012358: 025f8fb3 mul t6,t6,t0 +8001235c: 00d8f463 bgeu a7,a3,80012364 <__multf3+0x728> +80012360: 019f8fb3 add t6,t6,s9 +80012364: 03c12983 lw s3,60(sp) +80012368: 000106b7 lui a3,0x10 +8001236c: fff68513 addi a0,a3,-1 # ffff <_start-0x7fff0001> +80012370: 0108dd13 srli s10,a7,0x10 +80012374: 00a8f8b3 and a7,a7,a0 +80012378: 00a7f7b3 and a5,a5,a0 +8001237c: 01fd0d33 add s10,s10,t6 +80012380: 01089893 slli a7,a7,0x10 +80012384: 0109df93 srli t6,s3,0x10 +80012388: 00a9f9b3 and s3,s3,a0 +8001238c: 03fa8cb3 mul s9,s5,t6 +80012390: 00f888b3 add a7,a7,a5 +80012394: 033a8ab3 mul s5,s5,s3 +80012398: 03c987b3 mul a5,s3,t3 +8001239c: 03cf8e33 mul t3,t6,t3 +800123a0: 0107d813 srli a6,a5,0x10 +800123a4: 01ca8ab3 add s5,s5,t3 +800123a8: 01580ab3 add s5,a6,s5 +800123ac: 01caf463 bgeu s5,t3,800123b4 <__multf3+0x778> +800123b0: 00dc8cb3 add s9,s9,a3 +800123b4: 00010bb7 lui s7,0x10 +800123b8: fffb8713 addi a4,s7,-1 # ffff <_start-0x7fff0001> +800123bc: 010ad813 srli a6,s5,0x10 +800123c0: 01980cb3 add s9,a6,s9 +800123c4: 00eaf833 and a6,s5,a4 +800123c8: 00e7f7b3 and a5,a5,a4 +800123cc: 01081813 slli a6,a6,0x10 +800123d0: 02be86b3 mul a3,t4,a1 +800123d4: 00f80833 add a6,a6,a5 +800123d8: 03d90e33 mul t3,s2,t4 +800123dc: 0106d513 srli a0,a3,0x10 +800123e0: 02b387b3 mul a5,t2,a1 +800123e4: 01c787b3 add a5,a5,t3 +800123e8: 00f507b3 add a5,a0,a5 +800123ec: 02790733 mul a4,s2,t2 +800123f0: 01c7f463 bgeu a5,t3,800123f8 <__multf3+0x7bc> +800123f4: 01770733 add a4,a4,s7 +800123f8: 0107d513 srli a0,a5,0x10 +800123fc: 00e50733 add a4,a0,a4 +80012400: 00010bb7 lui s7,0x10 +80012404: 02e12223 sw a4,36(sp) +80012408: fffb8713 addi a4,s7,-1 # ffff <_start-0x7fff0001> +8001240c: 00e7f533 and a0,a5,a4 +80012410: 00e6f6b3 and a3,a3,a4 +80012414: 03e40e33 mul t3,s0,t5 +80012418: 01051513 slli a0,a0,0x10 +8001241c: 00d50533 add a0,a0,a3 +80012420: 03e60733 mul a4,a2,t5 +80012424: 02c487b3 mul a5,s1,a2 +80012428: 01075693 srli a3,a4,0x10 +8001242c: 01c787b3 add a5,a5,t3 +80012430: 00f687b3 add a5,a3,a5 +80012434: 02848ab3 mul s5,s1,s0 +80012438: 01c7f463 bgeu a5,t3,80012440 <__multf3+0x804> +8001243c: 017a8ab3 add s5,s5,s7 +80012440: 00010db7 lui s11,0x10 +80012444: fffd8e13 addi t3,s11,-1 # ffff <_start-0x7fff0001> +80012448: 01c7f6b3 and a3,a5,t3 +8001244c: 0107db93 srli s7,a5,0x10 +80012450: 011b07b3 add a5,s6,a7 +80012454: 01c77733 and a4,a4,t3 +80012458: 0117b8b3 sltu a7,a5,a7 +8001245c: 01aa0a33 add s4,s4,s10 +80012460: 01069693 slli a3,a3,0x10 +80012464: 00e686b3 add a3,a3,a4 +80012468: 011a0733 add a4,s4,a7 +8001246c: 02e12423 sw a4,40(sp) +80012470: 010787b3 add a5,a5,a6 +80012474: 01aa3a33 sltu s4,s4,s10 +80012478: 02812d03 lw s10,40(sp) +8001247c: 0107b833 sltu a6,a5,a6 +80012480: 01970b33 add s6,a4,s9 +80012484: 010b0733 add a4,s6,a6 +80012488: 02e12623 sw a4,44(sp) +8001248c: 011d38b3 sltu a7,s10,a7 +80012490: 011a6a33 or s4,s4,a7 +80012494: 02c12883 lw a7,44(sp) +80012498: 02412e03 lw t3,36(sp) +8001249c: 00a787b3 add a5,a5,a0 +800124a0: 0108b833 sltu a6,a7,a6 +800124a4: 019b3b33 sltu s6,s6,s9 +800124a8: 00a7b533 sltu a0,a5,a0 +800124ac: 01c70733 add a4,a4,t3 +800124b0: 010b6b33 or s6,s6,a6 +800124b4: 02412803 lw a6,36(sp) +800124b8: 00a70c33 add s8,a4,a0 +800124bc: 015b8bb3 add s7,s7,s5 +800124c0: 00d787b3 add a5,a5,a3 +800124c4: 00d7b6b3 sltu a3,a5,a3 +800124c8: 017c0ab3 add s5,s8,s7 +800124cc: 00da8e33 add t3,s5,a3 +800124d0: 01073733 sltu a4,a4,a6 +800124d4: 00ac3533 sltu a0,s8,a0 +800124d8: 00a76733 or a4,a4,a0 +800124dc: 00de36b3 sltu a3,t3,a3 +800124e0: 016a0a33 add s4,s4,s6 +800124e4: 017abab3 sltu s5,s5,s7 +800124e8: 00ea0a33 add s4,s4,a4 +800124ec: 00daeab3 or s5,s5,a3 +800124f0: 02ce8833 mul a6,t4,a2 +800124f4: 015a06b3 add a3,s4,s5 +800124f8: 06f12623 sw a5,108(sp) +800124fc: 03d40a33 mul s4,s0,t4 +80012500: 01085513 srli a0,a6,0x10 +80012504: 02c38733 mul a4,t2,a2 +80012508: 01470733 add a4,a4,s4 +8001250c: 00e50733 add a4,a0,a4 +80012510: 028388b3 mul a7,t2,s0 +80012514: 01477463 bgeu a4,s4,8001251c <__multf3+0x8e0> +80012518: 01b888b3 add a7,a7,s11 +8001251c: 00010a37 lui s4,0x10 +80012520: 01075513 srli a0,a4,0x10 +80012524: fffa0a93 addi s5,s4,-1 # ffff <_start-0x7fff0001> +80012528: 011508b3 add a7,a0,a7 +8001252c: 01577533 and a0,a4,s5 +80012530: 01587833 and a6,a6,s5 +80012534: 01051513 slli a0,a0,0x10 +80012538: 02690ab3 mul s5,s2,t1 +8001253c: 01050533 add a0,a0,a6 +80012540: 02b30833 mul a6,t1,a1 +80012544: 02b285b3 mul a1,t0,a1 +80012548: 01085713 srli a4,a6,0x10 +8001254c: 015585b3 add a1,a1,s5 +80012550: 00b70733 add a4,a4,a1 +80012554: 02590933 mul s2,s2,t0 +80012558: 01577463 bgeu a4,s5,80012560 <__multf3+0x924> +8001255c: 01490933 add s2,s2,s4 +80012560: 00010ab7 lui s5,0x10 +80012564: 01075593 srli a1,a4,0x10 +80012568: fffa8a13 addi s4,s5,-1 # ffff <_start-0x7fff0001> +8001256c: 01487833 and a6,a6,s4 +80012570: 01258933 add s2,a1,s2 +80012574: 014775b3 and a1,a4,s4 +80012578: 01059593 slli a1,a1,0x10 +8001257c: 03e98733 mul a4,s3,t5 +80012580: 010585b3 add a1,a1,a6 +80012584: 03ef8f33 mul t5,t6,t5 +80012588: 01075813 srli a6,a4,0x10 +8001258c: 03f48a33 mul s4,s1,t6 +80012590: 033484b3 mul s1,s1,s3 +80012594: 01e484b3 add s1,s1,t5 +80012598: 009804b3 add s1,a6,s1 +8001259c: 01e4f463 bgeu s1,t5,800125a4 <__multf3+0x968> +800125a0: 015a0a33 add s4,s4,s5 +800125a4: 0104db13 srli s6,s1,0x10 +800125a8: 014b0b33 add s6,s6,s4 +800125ac: 00010a37 lui s4,0x10 +800125b0: fffa0f13 addi t5,s4,-1 # ffff <_start-0x7fff0001> +800125b4: 01e4f833 and a6,s1,t5 +800125b8: 01e77733 and a4,a4,t5 +800125bc: 026404b3 mul s1,s0,t1 +800125c0: 01081813 slli a6,a6,0x10 +800125c4: 00e80833 add a6,a6,a4 +800125c8: 02660f33 mul t5,a2,t1 +800125cc: 02c28633 mul a2,t0,a2 +800125d0: 010f5713 srli a4,t5,0x10 +800125d4: 00960633 add a2,a2,s1 +800125d8: 00c70633 add a2,a4,a2 +800125dc: 02540433 mul s0,s0,t0 +800125e0: 00967463 bgeu a2,s1,800125e8 <__multf3+0x9ac> +800125e4: 01440433 add s0,s0,s4 +800125e8: 00010a37 lui s4,0x10 +800125ec: 01065713 srli a4,a2,0x10 +800125f0: fffa0493 addi s1,s4,-1 # ffff <_start-0x7fff0001> +800125f4: 00870433 add s0,a4,s0 +800125f8: 00967733 and a4,a2,s1 +800125fc: 009f7f33 and t5,t5,s1 +80012600: 01071713 slli a4,a4,0x10 +80012604: 03f384b3 mul s1,t2,t6 +80012608: 01e70733 add a4,a4,t5 +8001260c: 033383b3 mul t2,t2,s3 +80012610: 03d98f33 mul t5,s3,t4 +80012614: 03df8eb3 mul t4,t6,t4 +80012618: 010f5613 srli a2,t5,0x10 +8001261c: 01d383b3 add t2,t2,t4 +80012620: 00760633 add a2,a2,t2 +80012624: 01d67463 bgeu a2,t4,8001262c <__multf3+0x9f0> +80012628: 014484b3 add s1,s1,s4 +8001262c: 01065c13 srli s8,a2,0x10 +80012630: 00010cb7 lui s9,0x10 +80012634: 009c0c33 add s8,s8,s1 +80012638: 00ae0e33 add t3,t3,a0 +8001263c: fffc8493 addi s1,s9,-1 # ffff <_start-0x7fff0001> +80012640: 00ae3533 sltu a0,t3,a0 +80012644: 011686b3 add a3,a3,a7 +80012648: 00967633 and a2,a2,s1 +8001264c: 00a68d33 add s10,a3,a0 +80012650: 009f7f33 and t5,t5,s1 +80012654: 00be0e33 add t3,t3,a1 +80012658: 01061613 slli a2,a2,0x10 +8001265c: 01e60633 add a2,a2,t5 +80012660: 00be35b3 sltu a1,t3,a1 +80012664: 012d0f33 add t5,s10,s2 +80012668: 010e0e33 add t3,t3,a6 +8001266c: 00bf03b3 add t2,t5,a1 +80012670: 01638eb3 add t4,t2,s6 +80012674: 07c12823 sw t3,112(sp) +80012678: 010e3e33 sltu t3,t3,a6 +8001267c: 01ce8db3 add s11,t4,t3 +80012680: 0116b6b3 sltu a3,a3,a7 +80012684: 00b3b5b3 sltu a1,t2,a1 +80012688: 00ad3533 sltu a0,s10,a0 +8001268c: 012f3933 sltu s2,t5,s2 +80012690: 00a6e533 or a0,a3,a0 +80012694: 00b96933 or s2,s2,a1 +80012698: 016ebeb3 sltu t4,t4,s6 +8001269c: 01cdbe33 sltu t3,s11,t3 +800126a0: 01250533 add a0,a0,s2 +800126a4: 01ceeeb3 or t4,t4,t3 +800126a8: 00ed8833 add a6,s11,a4 +800126ac: 01d50533 add a0,a0,t4 +800126b0: 00e83733 sltu a4,a6,a4 +800126b4: 00850533 add a0,a0,s0 +800126b8: 00e506b3 add a3,a0,a4 +800126bc: 00853433 sltu s0,a0,s0 +800126c0: 02698533 mul a0,s3,t1 +800126c4: 00c80833 add a6,a6,a2 +800126c8: 00e6b733 sltu a4,a3,a4 +800126cc: 00c83633 sltu a2,a6,a2 +800126d0: 018686b3 add a3,a3,s8 +800126d4: 00c685b3 add a1,a3,a2 +800126d8: 0186bc33 sltu s8,a3,s8 +800126dc: 00c5b633 sltu a2,a1,a2 +800126e0: 07012a23 sw a6,116(sp) +800126e4: 00e46733 or a4,s0,a4 +800126e8: 026f8333 mul t1,t6,t1 +800126ec: 01055693 srli a3,a0,0x10 +800126f0: 00cc6633 or a2,s8,a2 +800126f4: 033289b3 mul s3,t0,s3 +800126f8: 006989b3 add s3,s3,t1 +800126fc: 03f28fb3 mul t6,t0,t6 +80012700: 013682b3 add t0,a3,s3 +80012704: 0062f463 bgeu t0,t1,8001270c <__multf3+0xad0> +80012708: 019f8fb3 add t6,t6,s9 +8001270c: 0092f6b3 and a3,t0,s1 +80012710: 01069693 slli a3,a3,0x10 +80012714: 009574b3 and s1,a0,s1 +80012718: 0102d293 srli t0,t0,0x10 +8001271c: 009684b3 add s1,a3,s1 +80012720: 00e282b3 add t0,t0,a4 +80012724: 01012683 lw a3,16(sp) +80012728: 02012703 lw a4,32(sp) +8001272c: 009585b3 add a1,a1,s1 +80012730: 0095b4b3 sltu s1,a1,s1 +80012734: 00d769b3 or s3,a4,a3 +80012738: 01412703 lw a4,20(sp) +8001273c: 00c282b3 add t0,t0,a2 +80012740: 009282b3 add t0,t0,s1 +80012744: 013769b3 or s3,a4,s3 +80012748: 01f28fb3 add t6,t0,t6 +8001274c: 00d79793 slli a5,a5,0xd +80012750: 06b12c23 sw a1,120(sp) +80012754: 07f12e23 sw t6,124(sp) +80012758: 0137e7b3 or a5,a5,s3 +8001275c: 06010713 addi a4,sp,96 +80012760: 07010593 addi a1,sp,112 +80012764: 00c72683 lw a3,12(a4) +80012768: 01072603 lw a2,16(a4) +8001276c: 00470713 addi a4,a4,4 +80012770: 0136d693 srli a3,a3,0x13 +80012774: 00d61613 slli a2,a2,0xd +80012778: 00c6e6b3 or a3,a3,a2 +8001277c: fed72e23 sw a3,-4(a4) +80012780: fee592e3 bne a1,a4,80012764 <__multf3+0xb28> +80012784: 06012703 lw a4,96(sp) +80012788: 06812683 lw a3,104(sp) +8001278c: 00f037b3 snez a5,a5 +80012790: 00e7e7b3 or a5,a5,a4 +80012794: 04d12c23 sw a3,88(sp) +80012798: 06c12703 lw a4,108(sp) +8001279c: 06412683 lw a3,100(sp) +800127a0: 04f12823 sw a5,80(sp) +800127a4: 04e12e23 sw a4,92(sp) +800127a8: 04d12a23 sw a3,84(sp) +800127ac: 00b71693 slli a3,a4,0xb +800127b0: 2006dc63 bgez a3,800129c8 <__multf3+0xd8c> +800127b4: 01f79793 slli a5,a5,0x1f +800127b8: 05010713 addi a4,sp,80 +800127bc: 05c10593 addi a1,sp,92 +800127c0: 00072683 lw a3,0(a4) +800127c4: 00472603 lw a2,4(a4) +800127c8: 00470713 addi a4,a4,4 +800127cc: 0016d693 srli a3,a3,0x1 +800127d0: 01f61613 slli a2,a2,0x1f +800127d4: 00c6e6b3 or a3,a3,a2 +800127d8: fed72e23 sw a3,-4(a4) +800127dc: fee592e3 bne a1,a4,800127c0 <__multf3+0xb84> +800127e0: 05c12703 lw a4,92(sp) +800127e4: 00f037b3 snez a5,a5 +800127e8: 00175713 srli a4,a4,0x1 +800127ec: 04e12e23 sw a4,92(sp) +800127f0: 05012703 lw a4,80(sp) +800127f4: 00f767b3 or a5,a4,a5 +800127f8: 04f12823 sw a5,80(sp) +800127fc: 01812703 lw a4,24(sp) +80012800: 000047b7 lui a5,0x4 +80012804: fff78793 addi a5,a5,-1 # 3fff <_start-0x7fffc001> +80012808: 00f707b3 add a5,a4,a5 +8001280c: 1ef05063 blez a5,800129ec <__multf3+0xdb0> +80012810: 05012703 lw a4,80(sp) +80012814: 00777693 andi a3,a4,7 +80012818: 04068463 beqz a3,80012860 <__multf3+0xc24> +8001281c: 00f77693 andi a3,a4,15 +80012820: 00400613 li a2,4 +80012824: 02c68e63 beq a3,a2,80012860 <__multf3+0xc24> +80012828: 05412683 lw a3,84(sp) +8001282c: 00470713 addi a4,a4,4 +80012830: 04e12823 sw a4,80(sp) +80012834: 00473713 sltiu a4,a4,4 +80012838: 00d706b3 add a3,a4,a3 +8001283c: 00e6b733 sltu a4,a3,a4 +80012840: 04d12a23 sw a3,84(sp) +80012844: 05812683 lw a3,88(sp) +80012848: 00d706b3 add a3,a4,a3 +8001284c: 04d12c23 sw a3,88(sp) +80012850: 00e6b6b3 sltu a3,a3,a4 +80012854: 05c12703 lw a4,92(sp) +80012858: 00e686b3 add a3,a3,a4 +8001285c: 04d12e23 sw a3,92(sp) +80012860: 05c12703 lw a4,92(sp) +80012864: 00b71693 slli a3,a4,0xb +80012868: 0206d063 bgez a3,80012888 <__multf3+0xc4c> +8001286c: fff007b7 lui a5,0xfff00 +80012870: fff78793 addi a5,a5,-1 # ffefffff <__BSS_END__+0x7fee93c3> +80012874: 00f77733 and a4,a4,a5 +80012878: 04e12e23 sw a4,92(sp) +8001287c: 01812703 lw a4,24(sp) +80012880: 000047b7 lui a5,0x4 +80012884: 00f707b3 add a5,a4,a5 +80012888: 05010713 addi a4,sp,80 +8001288c: 05c10593 addi a1,sp,92 +80012890: 00072683 lw a3,0(a4) +80012894: 00472603 lw a2,4(a4) +80012898: 00470713 addi a4,a4,4 +8001289c: 0036d693 srli a3,a3,0x3 +800128a0: 01d61613 slli a2,a2,0x1d +800128a4: 00c6e6b3 or a3,a3,a2 +800128a8: fed72e23 sw a3,-4(a4) +800128ac: feb712e3 bne a4,a1,80012890 <__multf3+0xc54> +800128b0: 00008737 lui a4,0x8 +800128b4: ffe70693 addi a3,a4,-2 # 7ffe <_start-0x7fff8002> +800128b8: 10f6ce63 blt a3,a5,800129d4 <__multf3+0xd98> +800128bc: 05c12703 lw a4,92(sp) +800128c0: 00375713 srli a4,a4,0x3 +800128c4: 04e12e23 sw a4,92(sp) +800128c8: 05c12703 lw a4,92(sp) +800128cc: 01179793 slli a5,a5,0x11 +800128d0: 0117d793 srli a5,a5,0x11 +800128d4: 06e11623 sh a4,108(sp) +800128d8: 00c12703 lw a4,12(sp) +800128dc: 0bc12083 lw ra,188(sp) +800128e0: 0b812403 lw s0,184(sp) +800128e4: 00f71713 slli a4,a4,0xf +800128e8: 00f767b3 or a5,a4,a5 +800128ec: 06f11723 sh a5,110(sp) +800128f0: 00812703 lw a4,8(sp) +800128f4: 05012783 lw a5,80(sp) +800128f8: 0b412483 lw s1,180(sp) +800128fc: 0b012903 lw s2,176(sp) +80012900: 00f72023 sw a5,0(a4) +80012904: 05412783 lw a5,84(sp) +80012908: 0ac12983 lw s3,172(sp) +8001290c: 0a812a03 lw s4,168(sp) +80012910: 00f72223 sw a5,4(a4) +80012914: 05812783 lw a5,88(sp) +80012918: 0a412a83 lw s5,164(sp) +8001291c: 0a012b03 lw s6,160(sp) +80012920: 00f72423 sw a5,8(a4) +80012924: 06c12783 lw a5,108(sp) +80012928: 09c12b83 lw s7,156(sp) +8001292c: 09812c03 lw s8,152(sp) +80012930: 00f72623 sw a5,12(a4) +80012934: 09412c83 lw s9,148(sp) +80012938: 09012d03 lw s10,144(sp) +8001293c: 08c12d83 lw s11,140(sp) +80012940: 00070513 mv a0,a4 +80012944: 0c010113 addi sp,sp,192 +80012948: 00008067 ret +8001294c: 00912623 sw s1,12(sp) +80012950: 03012783 lw a5,48(sp) +80012954: 04f12823 sw a5,80(sp) +80012958: 03412783 lw a5,52(sp) +8001295c: 04f12a23 sw a5,84(sp) +80012960: 03812783 lw a5,56(sp) +80012964: 04f12c23 sw a5,88(sp) +80012968: 03c12783 lw a5,60(sp) +8001296c: 04f12e23 sw a5,92(sp) +80012970: 00200793 li a5,2 +80012974: 28fb0863 beq s6,a5,80012c04 <__multf3+0xfc8> +80012978: 00300793 li a5,3 +8001297c: 2afb0263 beq s6,a5,80012c20 <__multf3+0xfe4> +80012980: 00100793 li a5,1 +80012984: e6fb1ce3 bne s6,a5,800127fc <__multf3+0xbc0> +80012988: 04012e23 sw zero,92(sp) +8001298c: 04012c23 sw zero,88(sp) +80012990: 04012a23 sw zero,84(sp) +80012994: 04012823 sw zero,80(sp) +80012998: 22c0006f j 80012bc4 <__multf3+0xf88> +8001299c: 01212623 sw s2,12(sp) +800129a0: 04012783 lw a5,64(sp) +800129a4: 00070b13 mv s6,a4 +800129a8: 04f12823 sw a5,80(sp) +800129ac: 04412783 lw a5,68(sp) +800129b0: 04f12a23 sw a5,84(sp) +800129b4: 04812783 lw a5,72(sp) +800129b8: 04f12c23 sw a5,88(sp) +800129bc: 04c12783 lw a5,76(sp) +800129c0: 04f12e23 sw a5,92(sp) +800129c4: fadff06f j 80012970 <__multf3+0xd34> +800129c8: 01c12783 lw a5,28(sp) +800129cc: 00f12c23 sw a5,24(sp) +800129d0: e2dff06f j 800127fc <__multf3+0xbc0> +800129d4: 04012e23 sw zero,92(sp) +800129d8: 04012c23 sw zero,88(sp) +800129dc: 04012a23 sw zero,84(sp) +800129e0: 04012823 sw zero,80(sp) +800129e4: fff70793 addi a5,a4,-1 +800129e8: ee1ff06f j 800128c8 <__multf3+0xc8c> +800129ec: 00100693 li a3,1 +800129f0: 40f686b3 sub a3,a3,a5 +800129f4: 07400793 li a5,116 +800129f8: 1cd7ca63 blt a5,a3,80012bcc <__multf3+0xf90> +800129fc: 4056d513 srai a0,a3,0x5 +80012a00: 00000793 li a5,0 +80012a04: 00000713 li a4,0 +80012a08: 04a71663 bne a4,a0,80012a54 <__multf3+0xe18> +80012a0c: 01f6f693 andi a3,a3,31 +80012a10: 00251593 slli a1,a0,0x2 +80012a14: 04069e63 bnez a3,80012a70 <__multf3+0xe34> +80012a18: 00300613 li a2,3 +80012a1c: 05010713 addi a4,sp,80 +80012a20: 40a60633 sub a2,a2,a0 +80012a24: 00b70833 add a6,a4,a1 +80012a28: 00082803 lw a6,0(a6) +80012a2c: 00168693 addi a3,a3,1 +80012a30: 00470713 addi a4,a4,4 +80012a34: ff072e23 sw a6,-4(a4) +80012a38: fed656e3 bge a2,a3,80012a24 <__multf3+0xde8> +80012a3c: 00400713 li a4,4 +80012a40: 40a70533 sub a0,a4,a0 +80012a44: 00100713 li a4,1 +80012a48: 08a05063 blez a0,80012ac8 <__multf3+0xe8c> +80012a4c: 00050713 mv a4,a0 +80012a50: 0780006f j 80012ac8 <__multf3+0xe8c> +80012a54: 00271613 slli a2,a4,0x2 +80012a58: 05010593 addi a1,sp,80 +80012a5c: 00c58633 add a2,a1,a2 +80012a60: 00062603 lw a2,0(a2) +80012a64: 00170713 addi a4,a4,1 +80012a68: 00c7e7b3 or a5,a5,a2 +80012a6c: f9dff06f j 80012a08 <__multf3+0xdcc> +80012a70: 08010713 addi a4,sp,128 +80012a74: 00b70733 add a4,a4,a1 +80012a78: fd072703 lw a4,-48(a4) +80012a7c: 02000893 li a7,32 +80012a80: 40d888b3 sub a7,a7,a3 +80012a84: 01171733 sll a4,a4,a7 +80012a88: 00e7e7b3 or a5,a5,a4 +80012a8c: 00300613 li a2,3 +80012a90: 05010713 addi a4,sp,80 +80012a94: 00b705b3 add a1,a4,a1 +80012a98: 00000813 li a6,0 +80012a9c: 40a60633 sub a2,a2,a0 +80012aa0: 00458593 addi a1,a1,4 +80012aa4: 02c84663 blt a6,a2,80012ad0 <__multf3+0xe94> +80012aa8: 08010593 addi a1,sp,128 +80012aac: 00261613 slli a2,a2,0x2 +80012ab0: 00c58633 add a2,a1,a2 +80012ab4: 05c12583 lw a1,92(sp) +80012ab8: 00400713 li a4,4 +80012abc: 40a70733 sub a4,a4,a0 +80012ac0: 00d5d6b3 srl a3,a1,a3 +80012ac4: fcd62823 sw a3,-48(a2) +80012ac8: 00400613 li a2,4 +80012acc: 0440006f j 80012b10 <__multf3+0xed4> +80012ad0: 00281313 slli t1,a6,0x2 +80012ad4: 05010713 addi a4,sp,80 +80012ad8: 0005ae03 lw t3,0(a1) +80012adc: 00670333 add t1,a4,t1 +80012ae0: ffc5a703 lw a4,-4(a1) +80012ae4: 011e1e33 sll t3,t3,a7 +80012ae8: 00180813 addi a6,a6,1 +80012aec: 00d75733 srl a4,a4,a3 +80012af0: 01c76733 or a4,a4,t3 +80012af4: 00e32023 sw a4,0(t1) +80012af8: fa9ff06f j 80012aa0 <__multf3+0xe64> +80012afc: 00271693 slli a3,a4,0x2 +80012b00: 05010593 addi a1,sp,80 +80012b04: 00d586b3 add a3,a1,a3 +80012b08: 0006a023 sw zero,0(a3) +80012b0c: 00170713 addi a4,a4,1 +80012b10: fec716e3 bne a4,a2,80012afc <__multf3+0xec0> +80012b14: 05012683 lw a3,80(sp) +80012b18: 00f037b3 snez a5,a5 +80012b1c: 00d7e7b3 or a5,a5,a3 +80012b20: 04f12823 sw a5,80(sp) +80012b24: 0077f693 andi a3,a5,7 +80012b28: 04068263 beqz a3,80012b6c <__multf3+0xf30> +80012b2c: 00f7f693 andi a3,a5,15 +80012b30: 02e68e63 beq a3,a4,80012b6c <__multf3+0xf30> +80012b34: 05412703 lw a4,84(sp) +80012b38: 00478793 addi a5,a5,4 # 4004 <_start-0x7fffbffc> +80012b3c: 04f12823 sw a5,80(sp) +80012b40: 0047b793 sltiu a5,a5,4 +80012b44: 00e78733 add a4,a5,a4 +80012b48: 00f737b3 sltu a5,a4,a5 +80012b4c: 04e12a23 sw a4,84(sp) +80012b50: 05812703 lw a4,88(sp) +80012b54: 00e78733 add a4,a5,a4 +80012b58: 04e12c23 sw a4,88(sp) +80012b5c: 00f73733 sltu a4,a4,a5 +80012b60: 05c12783 lw a5,92(sp) +80012b64: 00f70733 add a4,a4,a5 +80012b68: 04e12e23 sw a4,92(sp) +80012b6c: 05c12783 lw a5,92(sp) +80012b70: 00c79713 slli a4,a5,0xc +80012b74: 00075e63 bgez a4,80012b90 <__multf3+0xf54> +80012b78: 04012e23 sw zero,92(sp) +80012b7c: 04012c23 sw zero,88(sp) +80012b80: 04012a23 sw zero,84(sp) +80012b84: 04012823 sw zero,80(sp) +80012b88: 00100793 li a5,1 +80012b8c: d3dff06f j 800128c8 <__multf3+0xc8c> +80012b90: 05010793 addi a5,sp,80 +80012b94: 05c10613 addi a2,sp,92 +80012b98: 0007a703 lw a4,0(a5) +80012b9c: 0047a683 lw a3,4(a5) +80012ba0: 00478793 addi a5,a5,4 +80012ba4: 00375713 srli a4,a4,0x3 +80012ba8: 01d69693 slli a3,a3,0x1d +80012bac: 00d76733 or a4,a4,a3 +80012bb0: fee7ae23 sw a4,-4(a5) +80012bb4: fef612e3 bne a2,a5,80012b98 <__multf3+0xf5c> +80012bb8: 05c12783 lw a5,92(sp) +80012bbc: 0037d793 srli a5,a5,0x3 +80012bc0: 04f12e23 sw a5,92(sp) +80012bc4: 00000793 li a5,0 +80012bc8: d01ff06f j 800128c8 <__multf3+0xc8c> +80012bcc: 05412783 lw a5,84(sp) +80012bd0: 05012703 lw a4,80(sp) +80012bd4: 00f76733 or a4,a4,a5 +80012bd8: 05812783 lw a5,88(sp) +80012bdc: 00f76733 or a4,a4,a5 +80012be0: 05c12783 lw a5,92(sp) +80012be4: 00f76733 or a4,a4,a5 +80012be8: 00000793 li a5,0 +80012bec: cc070ee3 beqz a4,800128c8 <__multf3+0xc8c> +80012bf0: 04012e23 sw zero,92(sp) +80012bf4: 04012c23 sw zero,88(sp) +80012bf8: 04012a23 sw zero,84(sp) +80012bfc: 04012823 sw zero,80(sp) +80012c00: cc9ff06f j 800128c8 <__multf3+0xc8c> +80012c04: 000087b7 lui a5,0x8 +80012c08: 04012e23 sw zero,92(sp) +80012c0c: 04012c23 sw zero,88(sp) +80012c10: 04012a23 sw zero,84(sp) +80012c14: 04012823 sw zero,80(sp) +80012c18: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80012c1c: cadff06f j 800128c8 <__multf3+0xc8c> +80012c20: 000087b7 lui a5,0x8 +80012c24: 04f12e23 sw a5,92(sp) +80012c28: 04012c23 sw zero,88(sp) +80012c2c: 04012a23 sw zero,84(sp) +80012c30: 04012823 sw zero,80(sp) +80012c34: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80012c38: 00012623 sw zero,12(sp) +80012c3c: c8dff06f j 800128c8 <__multf3+0xc8c> -80012d04 <__subtf3>: -80012d04: fa010113 addi sp,sp,-96 -80012d08: 0085a783 lw a5,8(a1) -80012d0c: 05212823 sw s2,80(sp) -80012d10: 00c5a903 lw s2,12(a1) -80012d14: 0005a883 lw a7,0(a1) -80012d18: 0045a703 lw a4,4(a1) -80012d1c: 04912a23 sw s1,84(sp) -80012d20: 02f12c23 sw a5,56(sp) -80012d24: 00050493 mv s1,a0 -80012d28: 00f12c23 sw a5,24(sp) -80012d2c: 00062803 lw a6,0(a2) -80012d30: 01091793 slli a5,s2,0x10 -80012d34: 00462503 lw a0,4(a2) -80012d38: 00862683 lw a3,8(a2) -80012d3c: 00c62e03 lw t3,12(a2) -80012d40: 04812c23 sw s0,88(sp) -80012d44: 0107d793 srli a5,a5,0x10 -80012d48: 00191413 slli s0,s2,0x1 -80012d4c: 03212e23 sw s2,60(sp) -80012d50: 04112e23 sw ra,92(sp) -80012d54: 05312623 sw s3,76(sp) -80012d58: 05412423 sw s4,72(sp) -80012d5c: 05512223 sw s5,68(sp) -80012d60: 05612023 sw s6,64(sp) -80012d64: 03112823 sw a7,48(sp) -80012d68: 02e12a23 sw a4,52(sp) -80012d6c: 01112823 sw a7,16(sp) -80012d70: 00e12a23 sw a4,20(sp) -80012d74: 00f12e23 sw a5,28(sp) -80012d78: 01145413 srli s0,s0,0x11 -80012d7c: 01f95913 srli s2,s2,0x1f -80012d80: 01010f13 addi t5,sp,16 -80012d84: 01c10593 addi a1,sp,28 -80012d88: 0005a783 lw a5,0(a1) -80012d8c: ffc5a703 lw a4,-4(a1) -80012d90: ffc58593 addi a1,a1,-4 -80012d94: 00379793 slli a5,a5,0x3 -80012d98: 01d75713 srli a4,a4,0x1d -80012d9c: 00e7e7b3 or a5,a5,a4 -80012da0: 00f5a223 sw a5,4(a1) -80012da4: febf12e3 bne t5,a1,80012d88 <__subtf3+0x84> -80012da8: 01012703 lw a4,16(sp) -80012dac: 010e1793 slli a5,t3,0x10 -80012db0: 001e1e93 slli t4,t3,0x1 -80012db4: 00371713 slli a4,a4,0x3 -80012db8: 0107d793 srli a5,a5,0x10 -80012dbc: 03012823 sw a6,48(sp) -80012dc0: 02d12c23 sw a3,56(sp) -80012dc4: 03c12e23 sw t3,60(sp) -80012dc8: 03012023 sw a6,32(sp) -80012dcc: 02d12423 sw a3,40(sp) -80012dd0: 00e12823 sw a4,16(sp) -80012dd4: 02a12a23 sw a0,52(sp) -80012dd8: 02a12223 sw a0,36(sp) -80012ddc: 02f12623 sw a5,44(sp) -80012de0: 011ede93 srli t4,t4,0x11 -80012de4: 01fe5e13 srli t3,t3,0x1f -80012de8: 02010813 addi a6,sp,32 -80012dec: 02c10693 addi a3,sp,44 -80012df0: 0006a783 lw a5,0(a3) -80012df4: ffc6a603 lw a2,-4(a3) -80012df8: ffc68693 addi a3,a3,-4 -80012dfc: 00379793 slli a5,a5,0x3 -80012e00: 01d65613 srli a2,a2,0x1d -80012e04: 00c7e7b3 or a5,a5,a2 -80012e08: 00f6a223 sw a5,4(a3) -80012e0c: fed812e3 bne a6,a3,80012df0 <__subtf3+0xec> -80012e10: 02012783 lw a5,32(sp) -80012e14: 00008637 lui a2,0x8 -80012e18: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> -80012e1c: 00379793 slli a5,a5,0x3 -80012e20: 02f12023 sw a5,32(sp) -80012e24: 02ce9063 bne t4,a2,80012e44 <__subtf3+0x140> -80012e28: 02812503 lw a0,40(sp) -80012e2c: 02412603 lw a2,36(sp) -80012e30: 00a66633 or a2,a2,a0 -80012e34: 02c12503 lw a0,44(sp) -80012e38: 00a66633 or a2,a2,a0 -80012e3c: 00f66633 or a2,a2,a5 -80012e40: 00061463 bnez a2,80012e48 <__subtf3+0x144> -80012e44: 001e4e13 xori t3,t3,1 -80012e48: 41d40333 sub t1,s0,t4 -80012e4c: 0f2e1ee3 bne t3,s2,80013748 <__subtf3+0xa44> -80012e50: 44605a63 blez t1,800132a4 <__subtf3+0x5a0> -80012e54: 01412f03 lw t5,20(sp) -80012e58: 01812e03 lw t3,24(sp) -80012e5c: 01c12883 lw a7,28(sp) -80012e60: 0a0e9c63 bnez t4,80012f18 <__subtf3+0x214> -80012e64: 02412503 lw a0,36(sp) -80012e68: 02812603 lw a2,40(sp) -80012e6c: 02c12e83 lw t4,44(sp) -80012e70: 00c565b3 or a1,a0,a2 -80012e74: 01d5e5b3 or a1,a1,t4 -80012e78: 00f5e5b3 or a1,a1,a5 -80012e7c: 00059e63 bnez a1,80012e98 <__subtf3+0x194> -80012e80: 02e12823 sw a4,48(sp) -80012e84: 03e12a23 sw t5,52(sp) -80012e88: 03c12c23 sw t3,56(sp) -80012e8c: 03112e23 sw a7,60(sp) -80012e90: 00030413 mv s0,t1 -80012e94: 0a00006f j 80012f34 <__subtf3+0x230> -80012e98: fff30593 addi a1,t1,-1 -80012e9c: 04059a63 bnez a1,80012ef0 <__subtf3+0x1ec> -80012ea0: 00f707b3 add a5,a4,a5 -80012ea4: 00e7b733 sltu a4,a5,a4 -80012ea8: 01e505b3 add a1,a0,t5 -80012eac: 02f12823 sw a5,48(sp) -80012eb0: 00e587b3 add a5,a1,a4 -80012eb4: 00e7b733 sltu a4,a5,a4 -80012eb8: 01e5b5b3 sltu a1,a1,t5 -80012ebc: 00e5e733 or a4,a1,a4 -80012ec0: 02f12a23 sw a5,52(sp) -80012ec4: 01c607b3 add a5,a2,t3 -80012ec8: 00e786b3 add a3,a5,a4 -80012ecc: 00e6b733 sltu a4,a3,a4 -80012ed0: 01c7b7b3 sltu a5,a5,t3 -80012ed4: 00e7e7b3 or a5,a5,a4 -80012ed8: 011e88b3 add a7,t4,a7 -80012edc: 011787b3 add a5,a5,a7 -80012ee0: 02d12c23 sw a3,56(sp) -80012ee4: 02f12e23 sw a5,60(sp) -80012ee8: 00100413 li s0,1 -80012eec: 32c0006f j 80013218 <__subtf3+0x514> -80012ef0: 000087b7 lui a5,0x8 -80012ef4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012ef8: f8f304e3 beq t1,a5,80012e80 <__subtf3+0x17c> -80012efc: 07400793 li a5,116 -80012f00: 1ab7d463 bge a5,a1,800130a8 <__subtf3+0x3a4> -80012f04: 02012623 sw zero,44(sp) -80012f08: 02012423 sw zero,40(sp) -80012f0c: 02012223 sw zero,36(sp) -80012f10: 00100793 li a5,1 -80012f14: 2a80006f j 800131bc <__subtf3+0x4b8> -80012f18: 000087b7 lui a5,0x8 -80012f1c: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80012f20: 16f41663 bne s0,a5,8001308c <__subtf3+0x388> -80012f24: 02e12823 sw a4,48(sp) -80012f28: 03e12a23 sw t5,52(sp) -80012f2c: 03c12c23 sw t3,56(sp) -80012f30: 03112e23 sw a7,60(sp) +80012c40 <__subtf3>: +80012c40: fa010113 addi sp,sp,-96 +80012c44: 0085a783 lw a5,8(a1) +80012c48: 05212823 sw s2,80(sp) +80012c4c: 00c5a903 lw s2,12(a1) +80012c50: 0005a883 lw a7,0(a1) +80012c54: 0045a703 lw a4,4(a1) +80012c58: 04912a23 sw s1,84(sp) +80012c5c: 02f12c23 sw a5,56(sp) +80012c60: 00050493 mv s1,a0 +80012c64: 00f12c23 sw a5,24(sp) +80012c68: 00062803 lw a6,0(a2) +80012c6c: 01091793 slli a5,s2,0x10 +80012c70: 00462503 lw a0,4(a2) +80012c74: 00862683 lw a3,8(a2) +80012c78: 00c62e03 lw t3,12(a2) +80012c7c: 04812c23 sw s0,88(sp) +80012c80: 0107d793 srli a5,a5,0x10 +80012c84: 00191413 slli s0,s2,0x1 +80012c88: 03212e23 sw s2,60(sp) +80012c8c: 04112e23 sw ra,92(sp) +80012c90: 05312623 sw s3,76(sp) +80012c94: 05412423 sw s4,72(sp) +80012c98: 05512223 sw s5,68(sp) +80012c9c: 05612023 sw s6,64(sp) +80012ca0: 03112823 sw a7,48(sp) +80012ca4: 02e12a23 sw a4,52(sp) +80012ca8: 01112823 sw a7,16(sp) +80012cac: 00e12a23 sw a4,20(sp) +80012cb0: 00f12e23 sw a5,28(sp) +80012cb4: 01145413 srli s0,s0,0x11 +80012cb8: 01f95913 srli s2,s2,0x1f +80012cbc: 01010f13 addi t5,sp,16 +80012cc0: 01c10593 addi a1,sp,28 +80012cc4: 0005a783 lw a5,0(a1) +80012cc8: ffc5a703 lw a4,-4(a1) +80012ccc: ffc58593 addi a1,a1,-4 +80012cd0: 00379793 slli a5,a5,0x3 +80012cd4: 01d75713 srli a4,a4,0x1d +80012cd8: 00e7e7b3 or a5,a5,a4 +80012cdc: 00f5a223 sw a5,4(a1) +80012ce0: febf12e3 bne t5,a1,80012cc4 <__subtf3+0x84> +80012ce4: 01012703 lw a4,16(sp) +80012ce8: 010e1793 slli a5,t3,0x10 +80012cec: 001e1e93 slli t4,t3,0x1 +80012cf0: 00371713 slli a4,a4,0x3 +80012cf4: 0107d793 srli a5,a5,0x10 +80012cf8: 03012823 sw a6,48(sp) +80012cfc: 02d12c23 sw a3,56(sp) +80012d00: 03c12e23 sw t3,60(sp) +80012d04: 03012023 sw a6,32(sp) +80012d08: 02d12423 sw a3,40(sp) +80012d0c: 00e12823 sw a4,16(sp) +80012d10: 02a12a23 sw a0,52(sp) +80012d14: 02a12223 sw a0,36(sp) +80012d18: 02f12623 sw a5,44(sp) +80012d1c: 011ede93 srli t4,t4,0x11 +80012d20: 01fe5e13 srli t3,t3,0x1f +80012d24: 02010813 addi a6,sp,32 +80012d28: 02c10693 addi a3,sp,44 +80012d2c: 0006a783 lw a5,0(a3) +80012d30: ffc6a603 lw a2,-4(a3) +80012d34: ffc68693 addi a3,a3,-4 +80012d38: 00379793 slli a5,a5,0x3 +80012d3c: 01d65613 srli a2,a2,0x1d +80012d40: 00c7e7b3 or a5,a5,a2 +80012d44: 00f6a223 sw a5,4(a3) +80012d48: fed812e3 bne a6,a3,80012d2c <__subtf3+0xec> +80012d4c: 02012783 lw a5,32(sp) +80012d50: 00008637 lui a2,0x8 +80012d54: fff60613 addi a2,a2,-1 # 7fff <_start-0x7fff8001> +80012d58: 00379793 slli a5,a5,0x3 +80012d5c: 02f12023 sw a5,32(sp) +80012d60: 02ce9063 bne t4,a2,80012d80 <__subtf3+0x140> +80012d64: 02812503 lw a0,40(sp) +80012d68: 02412603 lw a2,36(sp) +80012d6c: 00a66633 or a2,a2,a0 +80012d70: 02c12503 lw a0,44(sp) +80012d74: 00a66633 or a2,a2,a0 +80012d78: 00f66633 or a2,a2,a5 +80012d7c: 00061463 bnez a2,80012d84 <__subtf3+0x144> +80012d80: 001e4e13 xori t3,t3,1 +80012d84: 41d40333 sub t1,s0,t4 +80012d88: 0f2e1ee3 bne t3,s2,80013684 <__subtf3+0xa44> +80012d8c: 44605a63 blez t1,800131e0 <__subtf3+0x5a0> +80012d90: 01412f03 lw t5,20(sp) +80012d94: 01812e03 lw t3,24(sp) +80012d98: 01c12883 lw a7,28(sp) +80012d9c: 0a0e9c63 bnez t4,80012e54 <__subtf3+0x214> +80012da0: 02412503 lw a0,36(sp) +80012da4: 02812603 lw a2,40(sp) +80012da8: 02c12e83 lw t4,44(sp) +80012dac: 00c565b3 or a1,a0,a2 +80012db0: 01d5e5b3 or a1,a1,t4 +80012db4: 00f5e5b3 or a1,a1,a5 +80012db8: 00059e63 bnez a1,80012dd4 <__subtf3+0x194> +80012dbc: 02e12823 sw a4,48(sp) +80012dc0: 03e12a23 sw t5,52(sp) +80012dc4: 03c12c23 sw t3,56(sp) +80012dc8: 03112e23 sw a7,60(sp) +80012dcc: 00030413 mv s0,t1 +80012dd0: 0a00006f j 80012e70 <__subtf3+0x230> +80012dd4: fff30593 addi a1,t1,-1 +80012dd8: 04059a63 bnez a1,80012e2c <__subtf3+0x1ec> +80012ddc: 00f707b3 add a5,a4,a5 +80012de0: 00e7b733 sltu a4,a5,a4 +80012de4: 01e505b3 add a1,a0,t5 +80012de8: 02f12823 sw a5,48(sp) +80012dec: 00e587b3 add a5,a1,a4 +80012df0: 00e7b733 sltu a4,a5,a4 +80012df4: 01e5b5b3 sltu a1,a1,t5 +80012df8: 00e5e733 or a4,a1,a4 +80012dfc: 02f12a23 sw a5,52(sp) +80012e00: 01c607b3 add a5,a2,t3 +80012e04: 00e786b3 add a3,a5,a4 +80012e08: 00e6b733 sltu a4,a3,a4 +80012e0c: 01c7b7b3 sltu a5,a5,t3 +80012e10: 00e7e7b3 or a5,a5,a4 +80012e14: 011e88b3 add a7,t4,a7 +80012e18: 011787b3 add a5,a5,a7 +80012e1c: 02d12c23 sw a3,56(sp) +80012e20: 02f12e23 sw a5,60(sp) +80012e24: 00100413 li s0,1 +80012e28: 32c0006f j 80013154 <__subtf3+0x514> +80012e2c: 000087b7 lui a5,0x8 +80012e30: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80012e34: f8f304e3 beq t1,a5,80012dbc <__subtf3+0x17c> +80012e38: 07400793 li a5,116 +80012e3c: 1ab7d463 bge a5,a1,80012fe4 <__subtf3+0x3a4> +80012e40: 02012623 sw zero,44(sp) +80012e44: 02012423 sw zero,40(sp) +80012e48: 02012223 sw zero,36(sp) +80012e4c: 00100793 li a5,1 +80012e50: 2a80006f j 800130f8 <__subtf3+0x4b8> +80012e54: 000087b7 lui a5,0x8 +80012e58: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80012e5c: 16f41663 bne s0,a5,80012fc8 <__subtf3+0x388> +80012e60: 02e12823 sw a4,48(sp) +80012e64: 03e12a23 sw t5,52(sp) +80012e68: 03c12c23 sw t3,56(sp) +80012e6c: 03112e23 sw a7,60(sp) +80012e70: 03012783 lw a5,48(sp) +80012e74: 0077f713 andi a4,a5,7 +80012e78: 04070463 beqz a4,80012ec0 <__subtf3+0x280> +80012e7c: 00f7f713 andi a4,a5,15 +80012e80: 00400693 li a3,4 +80012e84: 02d70e63 beq a4,a3,80012ec0 <__subtf3+0x280> +80012e88: 03412703 lw a4,52(sp) +80012e8c: 00478793 addi a5,a5,4 +80012e90: 02f12823 sw a5,48(sp) +80012e94: 0047b793 sltiu a5,a5,4 +80012e98: 00e78733 add a4,a5,a4 +80012e9c: 00f737b3 sltu a5,a4,a5 +80012ea0: 02e12a23 sw a4,52(sp) +80012ea4: 03812703 lw a4,56(sp) +80012ea8: 00e78733 add a4,a5,a4 +80012eac: 02e12c23 sw a4,56(sp) +80012eb0: 00f73733 sltu a4,a4,a5 +80012eb4: 03c12783 lw a5,60(sp) +80012eb8: 00f70733 add a4,a4,a5 +80012ebc: 02e12e23 sw a4,60(sp) +80012ec0: 03c12783 lw a5,60(sp) +80012ec4: 00c79713 slli a4,a5,0xc +80012ec8: 02075463 bgez a4,80012ef0 <__subtf3+0x2b0> +80012ecc: 00008737 lui a4,0x8 +80012ed0: 00140413 addi s0,s0,1 +80012ed4: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80012ed8: 00e41463 bne s0,a4,80012ee0 <__subtf3+0x2a0> +80012edc: 2700106f j 8001414c <__subtf3+0x150c> +80012ee0: fff80737 lui a4,0xfff80 +80012ee4: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> +80012ee8: 00e7f7b3 and a5,a5,a4 +80012eec: 02f12e23 sw a5,60(sp) +80012ef0: 03010793 addi a5,sp,48 +80012ef4: 03c10613 addi a2,sp,60 +80012ef8: 0007a703 lw a4,0(a5) +80012efc: 0047a683 lw a3,4(a5) +80012f00: 00478793 addi a5,a5,4 +80012f04: 00375713 srli a4,a4,0x3 +80012f08: 01d69693 slli a3,a3,0x1d +80012f0c: 00d76733 or a4,a4,a3 +80012f10: fee7ae23 sw a4,-4(a5) +80012f14: fef612e3 bne a2,a5,80012ef8 <__subtf3+0x2b8> +80012f18: 03c12783 lw a5,60(sp) +80012f1c: 000086b7 lui a3,0x8 +80012f20: 0037d713 srli a4,a5,0x3 +80012f24: 02e12e23 sw a4,60(sp) +80012f28: fff68793 addi a5,a3,-1 # 7fff <_start-0x7fff8001> +80012f2c: 02f41a63 bne s0,a5,80012f60 <__subtf3+0x320> +80012f30: 03412603 lw a2,52(sp) 80012f34: 03012783 lw a5,48(sp) -80012f38: 0077f713 andi a4,a5,7 -80012f3c: 04070463 beqz a4,80012f84 <__subtf3+0x280> -80012f40: 00f7f713 andi a4,a5,15 -80012f44: 00400693 li a3,4 -80012f48: 02d70e63 beq a4,a3,80012f84 <__subtf3+0x280> -80012f4c: 03412703 lw a4,52(sp) -80012f50: 00478793 addi a5,a5,4 -80012f54: 02f12823 sw a5,48(sp) -80012f58: 0047b793 sltiu a5,a5,4 -80012f5c: 00e78733 add a4,a5,a4 -80012f60: 00f737b3 sltu a5,a4,a5 -80012f64: 02e12a23 sw a4,52(sp) -80012f68: 03812703 lw a4,56(sp) -80012f6c: 00e78733 add a4,a5,a4 -80012f70: 02e12c23 sw a4,56(sp) -80012f74: 00f73733 sltu a4,a4,a5 -80012f78: 03c12783 lw a5,60(sp) -80012f7c: 00f70733 add a4,a4,a5 -80012f80: 02e12e23 sw a4,60(sp) -80012f84: 03c12783 lw a5,60(sp) -80012f88: 00c79713 slli a4,a5,0xc -80012f8c: 02075463 bgez a4,80012fb4 <__subtf3+0x2b0> -80012f90: 00008737 lui a4,0x8 -80012f94: 00140413 addi s0,s0,1 -80012f98: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80012f9c: 00e41463 bne s0,a4,80012fa4 <__subtf3+0x2a0> -80012fa0: 2700106f j 80014210 <__subtf3+0x150c> -80012fa4: fff80737 lui a4,0xfff80 -80012fa8: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> -80012fac: 00e7f7b3 and a5,a5,a4 -80012fb0: 02f12e23 sw a5,60(sp) -80012fb4: 03010793 addi a5,sp,48 -80012fb8: 03c10613 addi a2,sp,60 -80012fbc: 0007a703 lw a4,0(a5) -80012fc0: 0047a683 lw a3,4(a5) -80012fc4: 00478793 addi a5,a5,4 -80012fc8: 00375713 srli a4,a4,0x3 -80012fcc: 01d69693 slli a3,a3,0x1d -80012fd0: 00d76733 or a4,a4,a3 -80012fd4: fee7ae23 sw a4,-4(a5) -80012fd8: fef612e3 bne a2,a5,80012fbc <__subtf3+0x2b8> -80012fdc: 03c12783 lw a5,60(sp) -80012fe0: 000086b7 lui a3,0x8 -80012fe4: 0037d713 srli a4,a5,0x3 -80012fe8: 02e12e23 sw a4,60(sp) -80012fec: fff68793 addi a5,a3,-1 # 7fff <_start-0x7fff8001> -80012ff0: 02f41a63 bne s0,a5,80013024 <__subtf3+0x320> -80012ff4: 03412603 lw a2,52(sp) -80012ff8: 03012783 lw a5,48(sp) -80012ffc: 00c7e7b3 or a5,a5,a2 -80013000: 03812603 lw a2,56(sp) -80013004: 00c7e7b3 or a5,a5,a2 -80013008: 00e7e7b3 or a5,a5,a4 -8001300c: 00078c63 beqz a5,80013024 <__subtf3+0x320> -80013010: 02d12e23 sw a3,60(sp) -80013014: 02012c23 sw zero,56(sp) -80013018: 02012a23 sw zero,52(sp) -8001301c: 02012823 sw zero,48(sp) -80013020: 00000913 li s2,0 -80013024: 03c12783 lw a5,60(sp) -80013028: 01141413 slli s0,s0,0x11 -8001302c: 01145413 srli s0,s0,0x11 -80013030: 00f11623 sh a5,12(sp) -80013034: 03012783 lw a5,48(sp) -80013038: 00f91913 slli s2,s2,0xf -8001303c: 00896933 or s2,s2,s0 -80013040: 00f4a023 sw a5,0(s1) # 80000 <_start-0x7ff80000> -80013044: 03412783 lw a5,52(sp) -80013048: 01211723 sh s2,14(sp) -8001304c: 05c12083 lw ra,92(sp) -80013050: 00f4a223 sw a5,4(s1) -80013054: 03812783 lw a5,56(sp) -80013058: 05812403 lw s0,88(sp) -8001305c: 05012903 lw s2,80(sp) -80013060: 00f4a423 sw a5,8(s1) -80013064: 00c12783 lw a5,12(sp) -80013068: 04c12983 lw s3,76(sp) -8001306c: 04812a03 lw s4,72(sp) -80013070: 00f4a623 sw a5,12(s1) -80013074: 04412a83 lw s5,68(sp) -80013078: 04012b03 lw s6,64(sp) -8001307c: 00048513 mv a0,s1 -80013080: 05412483 lw s1,84(sp) -80013084: 06010113 addi sp,sp,96 -80013088: 00008067 ret -8001308c: 02c12783 lw a5,44(sp) -80013090: 00080637 lui a2,0x80 -80013094: 00c7e7b3 or a5,a5,a2 -80013098: 02f12623 sw a5,44(sp) -8001309c: 07400793 li a5,116 -800130a0: e667c2e3 blt a5,t1,80012f04 <__subtf3+0x200> -800130a4: 00030593 mv a1,t1 -800130a8: 4055de93 srai t4,a1,0x5 -800130ac: 00000793 li a5,0 -800130b0: 00000613 li a2,0 -800130b4: 05d61663 bne a2,t4,80013100 <__subtf3+0x3fc> -800130b8: 01f5f593 andi a1,a1,31 -800130bc: 002e9313 slli t1,t4,0x2 -800130c0: 04059c63 bnez a1,80013118 <__subtf3+0x414> -800130c4: 00300593 li a1,3 -800130c8: 00000613 li a2,0 -800130cc: 41d585b3 sub a1,a1,t4 -800130d0: 00668533 add a0,a3,t1 -800130d4: 00052503 lw a0,0(a0) -800130d8: 00160613 addi a2,a2,1 # 80001 <_start-0x7ff7ffff> -800130dc: 00468693 addi a3,a3,4 -800130e0: fea6ae23 sw a0,-4(a3) -800130e4: fec5d6e3 bge a1,a2,800130d0 <__subtf3+0x3cc> -800130e8: 00400613 li a2,4 -800130ec: 41d60eb3 sub t4,a2,t4 -800130f0: 00100613 li a2,1 -800130f4: 07d05c63 blez t4,8001316c <__subtf3+0x468> -800130f8: 000e8613 mv a2,t4 -800130fc: 0700006f j 8001316c <__subtf3+0x468> -80013100: 00261513 slli a0,a2,0x2 -80013104: 00a80533 add a0,a6,a0 -80013108: 00052503 lw a0,0(a0) -8001310c: 00160613 addi a2,a2,1 -80013110: 00a7e7b3 or a5,a5,a0 -80013114: fa1ff06f j 800130b4 <__subtf3+0x3b0> -80013118: 04010693 addi a3,sp,64 -8001311c: 006686b3 add a3,a3,t1 -80013120: fe06a683 lw a3,-32(a3) -80013124: 02000f93 li t6,32 -80013128: 40bf8fb3 sub t6,t6,a1 -8001312c: 01f696b3 sll a3,a3,t6 -80013130: 00300513 li a0,3 -80013134: 00d7e7b3 or a5,a5,a3 -80013138: 00680333 add t1,a6,t1 -8001313c: 00000613 li a2,0 -80013140: 41d50533 sub a0,a0,t4 -80013144: 00430313 addi t1,t1,4 -80013148: 02a64663 blt a2,a0,80013174 <__subtf3+0x470> -8001314c: 04010693 addi a3,sp,64 -80013150: 00251513 slli a0,a0,0x2 -80013154: 00a68533 add a0,a3,a0 -80013158: 02c12683 lw a3,44(sp) -8001315c: 00400613 li a2,4 -80013160: 41d60633 sub a2,a2,t4 -80013164: 00b6d5b3 srl a1,a3,a1 -80013168: feb52023 sw a1,-32(a0) -8001316c: 00400593 li a1,4 -80013170: 03c0006f j 800131ac <__subtf3+0x4a8> -80013174: ffc32683 lw a3,-4(t1) -80013178: 00032383 lw t2,0(t1) -8001317c: 00261293 slli t0,a2,0x2 -80013180: 00b6d6b3 srl a3,a3,a1 -80013184: 01f393b3 sll t2,t2,t6 -80013188: 005802b3 add t0,a6,t0 -8001318c: 0076e6b3 or a3,a3,t2 -80013190: 00d2a023 sw a3,0(t0) -80013194: 00160613 addi a2,a2,1 -80013198: fadff06f j 80013144 <__subtf3+0x440> -8001319c: 00261693 slli a3,a2,0x2 -800131a0: 00d806b3 add a3,a6,a3 -800131a4: 0006a023 sw zero,0(a3) -800131a8: 00160613 addi a2,a2,1 -800131ac: feb618e3 bne a2,a1,8001319c <__subtf3+0x498> -800131b0: 02012683 lw a3,32(sp) -800131b4: 00f037b3 snez a5,a5 -800131b8: 00f6e7b3 or a5,a3,a5 -800131bc: 02f12023 sw a5,32(sp) -800131c0: 02012583 lw a1,32(sp) -800131c4: 02412603 lw a2,36(sp) -800131c8: 00b705b3 add a1,a4,a1 -800131cc: 00e5b733 sltu a4,a1,a4 -800131d0: 00cf0633 add a2,t5,a2 -800131d4: 00e606b3 add a3,a2,a4 -800131d8: 02b12823 sw a1,48(sp) -800131dc: 01e635b3 sltu a1,a2,t5 -800131e0: 02812603 lw a2,40(sp) -800131e4: 00e6b733 sltu a4,a3,a4 -800131e8: 00e5e5b3 or a1,a1,a4 -800131ec: 02d12a23 sw a3,52(sp) -800131f0: 00ce06b3 add a3,t3,a2 -800131f4: 00b687b3 add a5,a3,a1 -800131f8: 00b7b5b3 sltu a1,a5,a1 -800131fc: 02f12c23 sw a5,56(sp) -80013200: 02c12783 lw a5,44(sp) -80013204: 01c6b6b3 sltu a3,a3,t3 -80013208: 00b6e6b3 or a3,a3,a1 -8001320c: 00f888b3 add a7,a7,a5 -80013210: 011686b3 add a3,a3,a7 -80013214: 02d12e23 sw a3,60(sp) -80013218: 03c12783 lw a5,60(sp) -8001321c: 00c79713 slli a4,a5,0xc -80013220: d0075ae3 bgez a4,80012f34 <__subtf3+0x230> -80013224: fff80737 lui a4,0xfff80 -80013228: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> -8001322c: 00e7f7b3 and a5,a5,a4 -80013230: 02f12e23 sw a5,60(sp) -80013234: 03012783 lw a5,48(sp) -80013238: 00140413 addi s0,s0,1 -8001323c: 03c10593 addi a1,sp,60 -80013240: 01f79713 slli a4,a5,0x1f -80013244: 03010793 addi a5,sp,48 -80013248: 0007a683 lw a3,0(a5) -8001324c: 0047a603 lw a2,4(a5) -80013250: 00478793 addi a5,a5,4 -80013254: 0016d693 srli a3,a3,0x1 -80013258: 01f61613 slli a2,a2,0x1f -8001325c: 00c6e6b3 or a3,a3,a2 -80013260: fed7ae23 sw a3,-4(a5) -80013264: fef592e3 bne a1,a5,80013248 <__subtf3+0x544> -80013268: 03c12783 lw a5,60(sp) -8001326c: 0017d793 srli a5,a5,0x1 -80013270: 02f12e23 sw a5,60(sp) -80013274: 00e037b3 snez a5,a4 -80013278: 03012703 lw a4,48(sp) -8001327c: 00f767b3 or a5,a4,a5 -80013280: 02f12823 sw a5,48(sp) -80013284: 000087b7 lui a5,0x8 -80013288: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -8001328c: caf414e3 bne s0,a5,80012f34 <__subtf3+0x230> -80013290: 02012e23 sw zero,60(sp) -80013294: 02012c23 sw zero,56(sp) -80013298: 02012a23 sw zero,52(sp) -8001329c: 02012823 sw zero,48(sp) -800132a0: c95ff06f j 80012f34 <__subtf3+0x230> -800132a4: 02412683 lw a3,36(sp) -800132a8: 02812603 lw a2,40(sp) -800132ac: 02c12503 lw a0,44(sp) -800132b0: 28030463 beqz t1,80013538 <__subtf3+0x834> -800132b4: 408e8e33 sub t3,t4,s0 -800132b8: 0a041a63 bnez s0,8001336c <__subtf3+0x668> -800132bc: 01412883 lw a7,20(sp) -800132c0: 01812803 lw a6,24(sp) -800132c4: 01c12f83 lw t6,28(sp) -800132c8: 0108e333 or t1,a7,a6 -800132cc: 01f36333 or t1,t1,t6 -800132d0: 00e36333 or t1,t1,a4 -800132d4: 00031e63 bnez t1,800132f0 <__subtf3+0x5ec> -800132d8: 02f12823 sw a5,48(sp) -800132dc: 02d12a23 sw a3,52(sp) -800132e0: 02c12c23 sw a2,56(sp) -800132e4: 02a12e23 sw a0,60(sp) -800132e8: 000e0413 mv s0,t3 -800132ec: c49ff06f j 80012f34 <__subtf3+0x230> -800132f0: fffe0313 addi t1,t3,-1 -800132f4: 04031863 bnez t1,80013344 <__subtf3+0x640> -800132f8: 00f70733 add a4,a4,a5 -800132fc: 00f737b3 sltu a5,a4,a5 -80013300: 00d885b3 add a1,a7,a3 -80013304: 02e12823 sw a4,48(sp) -80013308: 00f58733 add a4,a1,a5 -8001330c: 00f737b3 sltu a5,a4,a5 -80013310: 00d5b6b3 sltu a3,a1,a3 -80013314: 00f6e6b3 or a3,a3,a5 -80013318: 02e12a23 sw a4,52(sp) -8001331c: 00c80733 add a4,a6,a2 -80013320: 00d707b3 add a5,a4,a3 -80013324: 00d7b6b3 sltu a3,a5,a3 -80013328: 00c73733 sltu a4,a4,a2 -8001332c: 00d76733 or a4,a4,a3 -80013330: 00af8533 add a0,t6,a0 -80013334: 00a70533 add a0,a4,a0 -80013338: 02f12c23 sw a5,56(sp) -8001333c: 02a12e23 sw a0,60(sp) -80013340: ba9ff06f j 80012ee8 <__subtf3+0x1e4> -80013344: 00008737 lui a4,0x8 -80013348: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -8001334c: f8ee06e3 beq t3,a4,800132d8 <__subtf3+0x5d4> -80013350: 07400713 li a4,116 -80013354: 04675c63 bge a4,t1,800133ac <__subtf3+0x6a8> -80013358: 00012e23 sw zero,28(sp) -8001335c: 00012c23 sw zero,24(sp) -80013360: 00012a23 sw zero,20(sp) -80013364: 00100713 li a4,1 -80013368: 16c0006f j 800134d4 <__subtf3+0x7d0> -8001336c: 00008737 lui a4,0x8 -80013370: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80013374: 00ee9e63 bne t4,a4,80013390 <__subtf3+0x68c> -80013378: 02f12823 sw a5,48(sp) -8001337c: 02d12a23 sw a3,52(sp) -80013380: 02c12c23 sw a2,56(sp) -80013384: 02a12e23 sw a0,60(sp) -80013388: 000e8413 mv s0,t4 -8001338c: ba9ff06f j 80012f34 <__subtf3+0x230> -80013390: 01c12703 lw a4,28(sp) -80013394: 00080837 lui a6,0x80 -80013398: 01076733 or a4,a4,a6 -8001339c: 00e12e23 sw a4,28(sp) -800133a0: 07400713 li a4,116 -800133a4: fbc74ae3 blt a4,t3,80013358 <__subtf3+0x654> -800133a8: 000e0313 mv t1,t3 -800133ac: 02000713 li a4,32 -800133b0: 02e34e33 div t3,t1,a4 -800133b4: 00000f93 li t6,0 -800133b8: 00000713 li a4,0 -800133bc: 05c74a63 blt a4,t3,80013410 <__subtf3+0x70c> -800133c0: 000e0893 mv a7,t3 -800133c4: 000e5463 bgez t3,800133cc <__subtf3+0x6c8> -800133c8: 00000893 li a7,0 -800133cc: 01f37713 andi a4,t1,31 -800133d0: 002e1813 slli a6,t3,0x2 -800133d4: 04071a63 bnez a4,80013428 <__subtf3+0x724> -800133d8: 00300893 li a7,3 -800133dc: 41c888b3 sub a7,a7,t3 -800133e0: 01058333 add t1,a1,a6 -800133e4: 00032303 lw t1,0(t1) -800133e8: 00170713 addi a4,a4,1 -800133ec: 00458593 addi a1,a1,4 -800133f0: fe65ae23 sw t1,-4(a1) -800133f4: fee8d6e3 bge a7,a4,800133e0 <__subtf3+0x6dc> -800133f8: 00400713 li a4,4 -800133fc: 41c70e33 sub t3,a4,t3 -80013400: 00100713 li a4,1 -80013404: 09c05063 blez t3,80013484 <__subtf3+0x780> -80013408: 000e0713 mv a4,t3 -8001340c: 0780006f j 80013484 <__subtf3+0x780> -80013410: 00271813 slli a6,a4,0x2 -80013414: 010f0833 add a6,t5,a6 -80013418: 00082803 lw a6,0(a6) # 80000 <_start-0x7ff80000> -8001341c: 00170713 addi a4,a4,1 -80013420: 010fefb3 or t6,t6,a6 -80013424: f99ff06f j 800133bc <__subtf3+0x6b8> -80013428: 02000713 li a4,32 -8001342c: 02e36333 rem t1,t1,a4 -80013430: 04010593 addi a1,sp,64 -80013434: 00289893 slli a7,a7,0x2 -80013438: 011588b3 add a7,a1,a7 -8001343c: fd08a583 lw a1,-48(a7) # ffffd0 <_start-0x7f000030> -80013440: 010f0833 add a6,t5,a6 -80013444: 00000293 li t0,0 -80013448: 40670733 sub a4,a4,t1 -8001344c: 00e595b3 sll a1,a1,a4 -80013450: 00bfefb3 or t6,t6,a1 -80013454: 00300593 li a1,3 -80013458: 41c585b3 sub a1,a1,t3 -8001345c: 00480813 addi a6,a6,4 -80013460: 02b2c663 blt t0,a1,8001348c <__subtf3+0x788> -80013464: 04010813 addi a6,sp,64 -80013468: 00259593 slli a1,a1,0x2 -8001346c: 00b805b3 add a1,a6,a1 -80013470: 01c12803 lw a6,28(sp) -80013474: 00400713 li a4,4 -80013478: 41c70733 sub a4,a4,t3 -8001347c: 00685333 srl t1,a6,t1 -80013480: fc65a823 sw t1,-48(a1) -80013484: 00300813 li a6,3 -80013488: 03c0006f j 800134c4 <__subtf3+0x7c0> -8001348c: ffc82883 lw a7,-4(a6) -80013490: 00082403 lw s0,0(a6) -80013494: 00229393 slli t2,t0,0x2 -80013498: 0068d8b3 srl a7,a7,t1 -8001349c: 00e41433 sll s0,s0,a4 -800134a0: 007f03b3 add t2,t5,t2 -800134a4: 0088e8b3 or a7,a7,s0 -800134a8: 0113a023 sw a7,0(t2) -800134ac: 00128293 addi t0,t0,1 -800134b0: fadff06f j 8001345c <__subtf3+0x758> -800134b4: 00271593 slli a1,a4,0x2 -800134b8: 00bf05b3 add a1,t5,a1 -800134bc: 0005a023 sw zero,0(a1) -800134c0: 00170713 addi a4,a4,1 -800134c4: fee858e3 bge a6,a4,800134b4 <__subtf3+0x7b0> -800134c8: 01012583 lw a1,16(sp) -800134cc: 01f03733 snez a4,t6 -800134d0: 00e5e733 or a4,a1,a4 -800134d4: 00e12823 sw a4,16(sp) -800134d8: 01012703 lw a4,16(sp) -800134dc: 01412583 lw a1,20(sp) -800134e0: 000e8413 mv s0,t4 -800134e4: 00e78733 add a4,a5,a4 -800134e8: 00f737b3 sltu a5,a4,a5 -800134ec: 00b685b3 add a1,a3,a1 -800134f0: 02e12823 sw a4,48(sp) -800134f4: 00f58733 add a4,a1,a5 -800134f8: 00f737b3 sltu a5,a4,a5 -800134fc: 02e12a23 sw a4,52(sp) -80013500: 01812703 lw a4,24(sp) -80013504: 00d5b6b3 sltu a3,a1,a3 -80013508: 00f6e6b3 or a3,a3,a5 -8001350c: 00e60733 add a4,a2,a4 -80013510: 00d707b3 add a5,a4,a3 -80013514: 00c73733 sltu a4,a4,a2 -80013518: 01c12603 lw a2,28(sp) -8001351c: 00d7b6b3 sltu a3,a5,a3 -80013520: 00d76733 or a4,a4,a3 -80013524: 00c50533 add a0,a0,a2 -80013528: 00a70533 add a0,a4,a0 -8001352c: 02f12c23 sw a5,56(sp) -80013530: 02a12e23 sw a0,60(sp) -80013534: ce5ff06f j 80013218 <__subtf3+0x514> -80013538: 00008fb7 lui t6,0x8 -8001353c: 00140593 addi a1,s0,1 -80013540: ffef8813 addi a6,t6,-2 # 7ffe <_start-0x7fff8002> -80013544: 0105f833 and a6,a1,a6 -80013548: 01412f03 lw t5,20(sp) -8001354c: 01812e83 lw t4,24(sp) -80013550: 01c12e03 lw t3,28(sp) -80013554: 03010893 addi a7,sp,48 -80013558: 03c10313 addi t1,sp,60 -8001355c: 14081663 bnez a6,800136a8 <__subtf3+0x9a4> -80013560: 01df6833 or a6,t5,t4 -80013564: 01c86833 or a6,a6,t3 -80013568: 00e86833 or a6,a6,a4 -8001356c: 0a041663 bnez s0,80013618 <__subtf3+0x914> -80013570: 00081c63 bnez a6,80013588 <__subtf3+0x884> -80013574: 02f12823 sw a5,48(sp) -80013578: 02d12a23 sw a3,52(sp) -8001357c: 02c12c23 sw a2,56(sp) -80013580: 02a12e23 sw a0,60(sp) -80013584: 9b1ff06f j 80012f34 <__subtf3+0x230> -80013588: 00c6e5b3 or a1,a3,a2 -8001358c: 00a5e5b3 or a1,a1,a0 -80013590: 00f5e5b3 or a1,a1,a5 -80013594: 00059c63 bnez a1,800135ac <__subtf3+0x8a8> -80013598: 02e12823 sw a4,48(sp) -8001359c: 03e12a23 sw t5,52(sp) -800135a0: 03d12c23 sw t4,56(sp) -800135a4: 03c12e23 sw t3,60(sp) -800135a8: 98dff06f j 80012f34 <__subtf3+0x230> -800135ac: 00f707b3 add a5,a4,a5 -800135b0: 00e7b733 sltu a4,a5,a4 -800135b4: 00df05b3 add a1,t5,a3 -800135b8: 02f12823 sw a5,48(sp) -800135bc: 00e587b3 add a5,a1,a4 -800135c0: 01e5b6b3 sltu a3,a1,t5 -800135c4: 00e7b733 sltu a4,a5,a4 -800135c8: 00e6e733 or a4,a3,a4 -800135cc: 00ce8633 add a2,t4,a2 -800135d0: 00e606b3 add a3,a2,a4 -800135d4: 00e6b733 sltu a4,a3,a4 -800135d8: 01d63633 sltu a2,a2,t4 -800135dc: 00e66633 or a2,a2,a4 -800135e0: 00ae0533 add a0,t3,a0 -800135e4: 00a60633 add a2,a2,a0 -800135e8: 02f12a23 sw a5,52(sp) -800135ec: 02d12c23 sw a3,56(sp) -800135f0: 00c61793 slli a5,a2,0xc -800135f4: 0007c663 bltz a5,80013600 <__subtf3+0x8fc> -800135f8: 02c12e23 sw a2,60(sp) -800135fc: 939ff06f j 80012f34 <__subtf3+0x230> -80013600: fff807b7 lui a5,0xfff80 -80013604: fff78793 addi a5,a5,-1 # fff7ffff <__BSS_END__+0x7ff693c3> -80013608: 00f67633 and a2,a2,a5 -8001360c: 02c12e23 sw a2,60(sp) -80013610: 00100413 li s0,1 -80013614: 921ff06f j 80012f34 <__subtf3+0x230> -80013618: 00081e63 bnez a6,80013634 <__subtf3+0x930> -8001361c: 02f12823 sw a5,48(sp) -80013620: 02d12a23 sw a3,52(sp) -80013624: 02c12c23 sw a2,56(sp) +80012f38: 00c7e7b3 or a5,a5,a2 +80012f3c: 03812603 lw a2,56(sp) +80012f40: 00c7e7b3 or a5,a5,a2 +80012f44: 00e7e7b3 or a5,a5,a4 +80012f48: 00078c63 beqz a5,80012f60 <__subtf3+0x320> +80012f4c: 02d12e23 sw a3,60(sp) +80012f50: 02012c23 sw zero,56(sp) +80012f54: 02012a23 sw zero,52(sp) +80012f58: 02012823 sw zero,48(sp) +80012f5c: 00000913 li s2,0 +80012f60: 03c12783 lw a5,60(sp) +80012f64: 01141413 slli s0,s0,0x11 +80012f68: 01145413 srli s0,s0,0x11 +80012f6c: 00f11623 sh a5,12(sp) +80012f70: 03012783 lw a5,48(sp) +80012f74: 00f91913 slli s2,s2,0xf +80012f78: 00896933 or s2,s2,s0 +80012f7c: 00f4a023 sw a5,0(s1) # 80000 <_start-0x7ff80000> +80012f80: 03412783 lw a5,52(sp) +80012f84: 01211723 sh s2,14(sp) +80012f88: 05c12083 lw ra,92(sp) +80012f8c: 00f4a223 sw a5,4(s1) +80012f90: 03812783 lw a5,56(sp) +80012f94: 05812403 lw s0,88(sp) +80012f98: 05012903 lw s2,80(sp) +80012f9c: 00f4a423 sw a5,8(s1) +80012fa0: 00c12783 lw a5,12(sp) +80012fa4: 04c12983 lw s3,76(sp) +80012fa8: 04812a03 lw s4,72(sp) +80012fac: 00f4a623 sw a5,12(s1) +80012fb0: 04412a83 lw s5,68(sp) +80012fb4: 04012b03 lw s6,64(sp) +80012fb8: 00048513 mv a0,s1 +80012fbc: 05412483 lw s1,84(sp) +80012fc0: 06010113 addi sp,sp,96 +80012fc4: 00008067 ret +80012fc8: 02c12783 lw a5,44(sp) +80012fcc: 00080637 lui a2,0x80 +80012fd0: 00c7e7b3 or a5,a5,a2 +80012fd4: 02f12623 sw a5,44(sp) +80012fd8: 07400793 li a5,116 +80012fdc: e667c2e3 blt a5,t1,80012e40 <__subtf3+0x200> +80012fe0: 00030593 mv a1,t1 +80012fe4: 4055de93 srai t4,a1,0x5 +80012fe8: 00000793 li a5,0 +80012fec: 00000613 li a2,0 +80012ff0: 05d61663 bne a2,t4,8001303c <__subtf3+0x3fc> +80012ff4: 01f5f593 andi a1,a1,31 +80012ff8: 002e9313 slli t1,t4,0x2 +80012ffc: 04059c63 bnez a1,80013054 <__subtf3+0x414> +80013000: 00300593 li a1,3 +80013004: 00000613 li a2,0 +80013008: 41d585b3 sub a1,a1,t4 +8001300c: 00668533 add a0,a3,t1 +80013010: 00052503 lw a0,0(a0) +80013014: 00160613 addi a2,a2,1 # 80001 <_start-0x7ff7ffff> +80013018: 00468693 addi a3,a3,4 +8001301c: fea6ae23 sw a0,-4(a3) +80013020: fec5d6e3 bge a1,a2,8001300c <__subtf3+0x3cc> +80013024: 00400613 li a2,4 +80013028: 41d60eb3 sub t4,a2,t4 +8001302c: 00100613 li a2,1 +80013030: 07d05c63 blez t4,800130a8 <__subtf3+0x468> +80013034: 000e8613 mv a2,t4 +80013038: 0700006f j 800130a8 <__subtf3+0x468> +8001303c: 00261513 slli a0,a2,0x2 +80013040: 00a80533 add a0,a6,a0 +80013044: 00052503 lw a0,0(a0) +80013048: 00160613 addi a2,a2,1 +8001304c: 00a7e7b3 or a5,a5,a0 +80013050: fa1ff06f j 80012ff0 <__subtf3+0x3b0> +80013054: 04010693 addi a3,sp,64 +80013058: 006686b3 add a3,a3,t1 +8001305c: fe06a683 lw a3,-32(a3) +80013060: 02000f93 li t6,32 +80013064: 40bf8fb3 sub t6,t6,a1 +80013068: 01f696b3 sll a3,a3,t6 +8001306c: 00300513 li a0,3 +80013070: 00d7e7b3 or a5,a5,a3 +80013074: 00680333 add t1,a6,t1 +80013078: 00000613 li a2,0 +8001307c: 41d50533 sub a0,a0,t4 +80013080: 00430313 addi t1,t1,4 +80013084: 02a64663 blt a2,a0,800130b0 <__subtf3+0x470> +80013088: 04010693 addi a3,sp,64 +8001308c: 00251513 slli a0,a0,0x2 +80013090: 00a68533 add a0,a3,a0 +80013094: 02c12683 lw a3,44(sp) +80013098: 00400613 li a2,4 +8001309c: 41d60633 sub a2,a2,t4 +800130a0: 00b6d5b3 srl a1,a3,a1 +800130a4: feb52023 sw a1,-32(a0) +800130a8: 00400593 li a1,4 +800130ac: 03c0006f j 800130e8 <__subtf3+0x4a8> +800130b0: ffc32683 lw a3,-4(t1) +800130b4: 00032383 lw t2,0(t1) +800130b8: 00261293 slli t0,a2,0x2 +800130bc: 00b6d6b3 srl a3,a3,a1 +800130c0: 01f393b3 sll t2,t2,t6 +800130c4: 005802b3 add t0,a6,t0 +800130c8: 0076e6b3 or a3,a3,t2 +800130cc: 00d2a023 sw a3,0(t0) +800130d0: 00160613 addi a2,a2,1 +800130d4: fadff06f j 80013080 <__subtf3+0x440> +800130d8: 00261693 slli a3,a2,0x2 +800130dc: 00d806b3 add a3,a6,a3 +800130e0: 0006a023 sw zero,0(a3) +800130e4: 00160613 addi a2,a2,1 +800130e8: feb618e3 bne a2,a1,800130d8 <__subtf3+0x498> +800130ec: 02012683 lw a3,32(sp) +800130f0: 00f037b3 snez a5,a5 +800130f4: 00f6e7b3 or a5,a3,a5 +800130f8: 02f12023 sw a5,32(sp) +800130fc: 02012583 lw a1,32(sp) +80013100: 02412603 lw a2,36(sp) +80013104: 00b705b3 add a1,a4,a1 +80013108: 00e5b733 sltu a4,a1,a4 +8001310c: 00cf0633 add a2,t5,a2 +80013110: 00e606b3 add a3,a2,a4 +80013114: 02b12823 sw a1,48(sp) +80013118: 01e635b3 sltu a1,a2,t5 +8001311c: 02812603 lw a2,40(sp) +80013120: 00e6b733 sltu a4,a3,a4 +80013124: 00e5e5b3 or a1,a1,a4 +80013128: 02d12a23 sw a3,52(sp) +8001312c: 00ce06b3 add a3,t3,a2 +80013130: 00b687b3 add a5,a3,a1 +80013134: 00b7b5b3 sltu a1,a5,a1 +80013138: 02f12c23 sw a5,56(sp) +8001313c: 02c12783 lw a5,44(sp) +80013140: 01c6b6b3 sltu a3,a3,t3 +80013144: 00b6e6b3 or a3,a3,a1 +80013148: 00f888b3 add a7,a7,a5 +8001314c: 011686b3 add a3,a3,a7 +80013150: 02d12e23 sw a3,60(sp) +80013154: 03c12783 lw a5,60(sp) +80013158: 00c79713 slli a4,a5,0xc +8001315c: d0075ae3 bgez a4,80012e70 <__subtf3+0x230> +80013160: fff80737 lui a4,0xfff80 +80013164: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> +80013168: 00e7f7b3 and a5,a5,a4 +8001316c: 02f12e23 sw a5,60(sp) +80013170: 03012783 lw a5,48(sp) +80013174: 00140413 addi s0,s0,1 +80013178: 03c10593 addi a1,sp,60 +8001317c: 01f79713 slli a4,a5,0x1f +80013180: 03010793 addi a5,sp,48 +80013184: 0007a683 lw a3,0(a5) +80013188: 0047a603 lw a2,4(a5) +8001318c: 00478793 addi a5,a5,4 +80013190: 0016d693 srli a3,a3,0x1 +80013194: 01f61613 slli a2,a2,0x1f +80013198: 00c6e6b3 or a3,a3,a2 +8001319c: fed7ae23 sw a3,-4(a5) +800131a0: fef592e3 bne a1,a5,80013184 <__subtf3+0x544> +800131a4: 03c12783 lw a5,60(sp) +800131a8: 0017d793 srli a5,a5,0x1 +800131ac: 02f12e23 sw a5,60(sp) +800131b0: 00e037b3 snez a5,a4 +800131b4: 03012703 lw a4,48(sp) +800131b8: 00f767b3 or a5,a4,a5 +800131bc: 02f12823 sw a5,48(sp) +800131c0: 000087b7 lui a5,0x8 +800131c4: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800131c8: caf414e3 bne s0,a5,80012e70 <__subtf3+0x230> +800131cc: 02012e23 sw zero,60(sp) +800131d0: 02012c23 sw zero,56(sp) +800131d4: 02012a23 sw zero,52(sp) +800131d8: 02012823 sw zero,48(sp) +800131dc: c95ff06f j 80012e70 <__subtf3+0x230> +800131e0: 02412683 lw a3,36(sp) +800131e4: 02812603 lw a2,40(sp) +800131e8: 02c12503 lw a0,44(sp) +800131ec: 28030463 beqz t1,80013474 <__subtf3+0x834> +800131f0: 408e8e33 sub t3,t4,s0 +800131f4: 0a041a63 bnez s0,800132a8 <__subtf3+0x668> +800131f8: 01412883 lw a7,20(sp) +800131fc: 01812803 lw a6,24(sp) +80013200: 01c12f83 lw t6,28(sp) +80013204: 0108e333 or t1,a7,a6 +80013208: 01f36333 or t1,t1,t6 +8001320c: 00e36333 or t1,t1,a4 +80013210: 00031e63 bnez t1,8001322c <__subtf3+0x5ec> +80013214: 02f12823 sw a5,48(sp) +80013218: 02d12a23 sw a3,52(sp) +8001321c: 02c12c23 sw a2,56(sp) +80013220: 02a12e23 sw a0,60(sp) +80013224: 000e0413 mv s0,t3 +80013228: c49ff06f j 80012e70 <__subtf3+0x230> +8001322c: fffe0313 addi t1,t3,-1 +80013230: 04031863 bnez t1,80013280 <__subtf3+0x640> +80013234: 00f70733 add a4,a4,a5 +80013238: 00f737b3 sltu a5,a4,a5 +8001323c: 00d885b3 add a1,a7,a3 +80013240: 02e12823 sw a4,48(sp) +80013244: 00f58733 add a4,a1,a5 +80013248: 00f737b3 sltu a5,a4,a5 +8001324c: 00d5b6b3 sltu a3,a1,a3 +80013250: 00f6e6b3 or a3,a3,a5 +80013254: 02e12a23 sw a4,52(sp) +80013258: 00c80733 add a4,a6,a2 +8001325c: 00d707b3 add a5,a4,a3 +80013260: 00d7b6b3 sltu a3,a5,a3 +80013264: 00c73733 sltu a4,a4,a2 +80013268: 00d76733 or a4,a4,a3 +8001326c: 00af8533 add a0,t6,a0 +80013270: 00a70533 add a0,a4,a0 +80013274: 02f12c23 sw a5,56(sp) +80013278: 02a12e23 sw a0,60(sp) +8001327c: ba9ff06f j 80012e24 <__subtf3+0x1e4> +80013280: 00008737 lui a4,0x8 +80013284: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80013288: f8ee06e3 beq t3,a4,80013214 <__subtf3+0x5d4> +8001328c: 07400713 li a4,116 +80013290: 04675c63 bge a4,t1,800132e8 <__subtf3+0x6a8> +80013294: 00012e23 sw zero,28(sp) +80013298: 00012c23 sw zero,24(sp) +8001329c: 00012a23 sw zero,20(sp) +800132a0: 00100713 li a4,1 +800132a4: 16c0006f j 80013410 <__subtf3+0x7d0> +800132a8: 00008737 lui a4,0x8 +800132ac: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +800132b0: 00ee9e63 bne t4,a4,800132cc <__subtf3+0x68c> +800132b4: 02f12823 sw a5,48(sp) +800132b8: 02d12a23 sw a3,52(sp) +800132bc: 02c12c23 sw a2,56(sp) +800132c0: 02a12e23 sw a0,60(sp) +800132c4: 000e8413 mv s0,t4 +800132c8: ba9ff06f j 80012e70 <__subtf3+0x230> +800132cc: 01c12703 lw a4,28(sp) +800132d0: 00080837 lui a6,0x80 +800132d4: 01076733 or a4,a4,a6 +800132d8: 00e12e23 sw a4,28(sp) +800132dc: 07400713 li a4,116 +800132e0: fbc74ae3 blt a4,t3,80013294 <__subtf3+0x654> +800132e4: 000e0313 mv t1,t3 +800132e8: 02000713 li a4,32 +800132ec: 02e34e33 div t3,t1,a4 +800132f0: 00000f93 li t6,0 +800132f4: 00000713 li a4,0 +800132f8: 05c74a63 blt a4,t3,8001334c <__subtf3+0x70c> +800132fc: 000e0893 mv a7,t3 +80013300: 000e5463 bgez t3,80013308 <__subtf3+0x6c8> +80013304: 00000893 li a7,0 +80013308: 01f37713 andi a4,t1,31 +8001330c: 002e1813 slli a6,t3,0x2 +80013310: 04071a63 bnez a4,80013364 <__subtf3+0x724> +80013314: 00300893 li a7,3 +80013318: 41c888b3 sub a7,a7,t3 +8001331c: 01058333 add t1,a1,a6 +80013320: 00032303 lw t1,0(t1) +80013324: 00170713 addi a4,a4,1 +80013328: 00458593 addi a1,a1,4 +8001332c: fe65ae23 sw t1,-4(a1) +80013330: fee8d6e3 bge a7,a4,8001331c <__subtf3+0x6dc> +80013334: 00400713 li a4,4 +80013338: 41c70e33 sub t3,a4,t3 +8001333c: 00100713 li a4,1 +80013340: 09c05063 blez t3,800133c0 <__subtf3+0x780> +80013344: 000e0713 mv a4,t3 +80013348: 0780006f j 800133c0 <__subtf3+0x780> +8001334c: 00271813 slli a6,a4,0x2 +80013350: 010f0833 add a6,t5,a6 +80013354: 00082803 lw a6,0(a6) # 80000 <_start-0x7ff80000> +80013358: 00170713 addi a4,a4,1 +8001335c: 010fefb3 or t6,t6,a6 +80013360: f99ff06f j 800132f8 <__subtf3+0x6b8> +80013364: 02000713 li a4,32 +80013368: 02e36333 rem t1,t1,a4 +8001336c: 04010593 addi a1,sp,64 +80013370: 00289893 slli a7,a7,0x2 +80013374: 011588b3 add a7,a1,a7 +80013378: fd08a583 lw a1,-48(a7) # ffffd0 <_start-0x7f000030> +8001337c: 010f0833 add a6,t5,a6 +80013380: 00000293 li t0,0 +80013384: 40670733 sub a4,a4,t1 +80013388: 00e595b3 sll a1,a1,a4 +8001338c: 00bfefb3 or t6,t6,a1 +80013390: 00300593 li a1,3 +80013394: 41c585b3 sub a1,a1,t3 +80013398: 00480813 addi a6,a6,4 +8001339c: 02b2c663 blt t0,a1,800133c8 <__subtf3+0x788> +800133a0: 04010813 addi a6,sp,64 +800133a4: 00259593 slli a1,a1,0x2 +800133a8: 00b805b3 add a1,a6,a1 +800133ac: 01c12803 lw a6,28(sp) +800133b0: 00400713 li a4,4 +800133b4: 41c70733 sub a4,a4,t3 +800133b8: 00685333 srl t1,a6,t1 +800133bc: fc65a823 sw t1,-48(a1) +800133c0: 00300813 li a6,3 +800133c4: 03c0006f j 80013400 <__subtf3+0x7c0> +800133c8: ffc82883 lw a7,-4(a6) +800133cc: 00082403 lw s0,0(a6) +800133d0: 00229393 slli t2,t0,0x2 +800133d4: 0068d8b3 srl a7,a7,t1 +800133d8: 00e41433 sll s0,s0,a4 +800133dc: 007f03b3 add t2,t5,t2 +800133e0: 0088e8b3 or a7,a7,s0 +800133e4: 0113a023 sw a7,0(t2) +800133e8: 00128293 addi t0,t0,1 +800133ec: fadff06f j 80013398 <__subtf3+0x758> +800133f0: 00271593 slli a1,a4,0x2 +800133f4: 00bf05b3 add a1,t5,a1 +800133f8: 0005a023 sw zero,0(a1) +800133fc: 00170713 addi a4,a4,1 +80013400: fee858e3 bge a6,a4,800133f0 <__subtf3+0x7b0> +80013404: 01012583 lw a1,16(sp) +80013408: 01f03733 snez a4,t6 +8001340c: 00e5e733 or a4,a1,a4 +80013410: 00e12823 sw a4,16(sp) +80013414: 01012703 lw a4,16(sp) +80013418: 01412583 lw a1,20(sp) +8001341c: 000e8413 mv s0,t4 +80013420: 00e78733 add a4,a5,a4 +80013424: 00f737b3 sltu a5,a4,a5 +80013428: 00b685b3 add a1,a3,a1 +8001342c: 02e12823 sw a4,48(sp) +80013430: 00f58733 add a4,a1,a5 +80013434: 00f737b3 sltu a5,a4,a5 +80013438: 02e12a23 sw a4,52(sp) +8001343c: 01812703 lw a4,24(sp) +80013440: 00d5b6b3 sltu a3,a1,a3 +80013444: 00f6e6b3 or a3,a3,a5 +80013448: 00e60733 add a4,a2,a4 +8001344c: 00d707b3 add a5,a4,a3 +80013450: 00c73733 sltu a4,a4,a2 +80013454: 01c12603 lw a2,28(sp) +80013458: 00d7b6b3 sltu a3,a5,a3 +8001345c: 00d76733 or a4,a4,a3 +80013460: 00c50533 add a0,a0,a2 +80013464: 00a70533 add a0,a4,a0 +80013468: 02f12c23 sw a5,56(sp) +8001346c: 02a12e23 sw a0,60(sp) +80013470: ce5ff06f j 80013154 <__subtf3+0x514> +80013474: 00008fb7 lui t6,0x8 +80013478: 00140593 addi a1,s0,1 +8001347c: ffef8813 addi a6,t6,-2 # 7ffe <_start-0x7fff8002> +80013480: 0105f833 and a6,a1,a6 +80013484: 01412f03 lw t5,20(sp) +80013488: 01812e83 lw t4,24(sp) +8001348c: 01c12e03 lw t3,28(sp) +80013490: 03010893 addi a7,sp,48 +80013494: 03c10313 addi t1,sp,60 +80013498: 14081663 bnez a6,800135e4 <__subtf3+0x9a4> +8001349c: 01df6833 or a6,t5,t4 +800134a0: 01c86833 or a6,a6,t3 +800134a4: 00e86833 or a6,a6,a4 +800134a8: 0a041663 bnez s0,80013554 <__subtf3+0x914> +800134ac: 00081c63 bnez a6,800134c4 <__subtf3+0x884> +800134b0: 02f12823 sw a5,48(sp) +800134b4: 02d12a23 sw a3,52(sp) +800134b8: 02c12c23 sw a2,56(sp) +800134bc: 02a12e23 sw a0,60(sp) +800134c0: 9b1ff06f j 80012e70 <__subtf3+0x230> +800134c4: 00c6e5b3 or a1,a3,a2 +800134c8: 00a5e5b3 or a1,a1,a0 +800134cc: 00f5e5b3 or a1,a1,a5 +800134d0: 00059c63 bnez a1,800134e8 <__subtf3+0x8a8> +800134d4: 02e12823 sw a4,48(sp) +800134d8: 03e12a23 sw t5,52(sp) +800134dc: 03d12c23 sw t4,56(sp) +800134e0: 03c12e23 sw t3,60(sp) +800134e4: 98dff06f j 80012e70 <__subtf3+0x230> +800134e8: 00f707b3 add a5,a4,a5 +800134ec: 00e7b733 sltu a4,a5,a4 +800134f0: 00df05b3 add a1,t5,a3 +800134f4: 02f12823 sw a5,48(sp) +800134f8: 00e587b3 add a5,a1,a4 +800134fc: 01e5b6b3 sltu a3,a1,t5 +80013500: 00e7b733 sltu a4,a5,a4 +80013504: 00e6e733 or a4,a3,a4 +80013508: 00ce8633 add a2,t4,a2 +8001350c: 00e606b3 add a3,a2,a4 +80013510: 00e6b733 sltu a4,a3,a4 +80013514: 01d63633 sltu a2,a2,t4 +80013518: 00e66633 or a2,a2,a4 +8001351c: 00ae0533 add a0,t3,a0 +80013520: 00a60633 add a2,a2,a0 +80013524: 02f12a23 sw a5,52(sp) +80013528: 02d12c23 sw a3,56(sp) +8001352c: 00c61793 slli a5,a2,0xc +80013530: 0007c663 bltz a5,8001353c <__subtf3+0x8fc> +80013534: 02c12e23 sw a2,60(sp) +80013538: 939ff06f j 80012e70 <__subtf3+0x230> +8001353c: fff807b7 lui a5,0xfff80 +80013540: fff78793 addi a5,a5,-1 # fff7ffff <__BSS_END__+0x7ff693c3> +80013544: 00f67633 and a2,a2,a5 +80013548: 02c12e23 sw a2,60(sp) +8001354c: 00100413 li s0,1 +80013550: 921ff06f j 80012e70 <__subtf3+0x230> +80013554: 00081e63 bnez a6,80013570 <__subtf3+0x930> +80013558: 02f12823 sw a5,48(sp) +8001355c: 02d12a23 sw a3,52(sp) +80013560: 02c12c23 sw a2,56(sp) +80013564: 02a12e23 sw a0,60(sp) +80013568: ffff8413 addi s0,t6,-1 +8001356c: 905ff06f j 80012e70 <__subtf3+0x230> +80013570: 00c6e6b3 or a3,a3,a2 +80013574: 00a6e533 or a0,a3,a0 +80013578: 00f567b3 or a5,a0,a5 +8001357c: 00079c63 bnez a5,80013594 <__subtf3+0x954> +80013580: 02e12823 sw a4,48(sp) +80013584: 03e12a23 sw t5,52(sp) +80013588: 03d12c23 sw t4,56(sp) +8001358c: 03c12e23 sw t3,60(sp) +80013590: fd9ff06f j 80013568 <__subtf3+0x928> +80013594: 03f12e23 sw t6,60(sp) +80013598: 02012c23 sw zero,56(sp) +8001359c: 02012a23 sw zero,52(sp) +800135a0: 02012823 sw zero,48(sp) +800135a4: 00030713 mv a4,t1 +800135a8: 00072783 lw a5,0(a4) +800135ac: ffc72683 lw a3,-4(a4) +800135b0: ffc70713 addi a4,a4,-4 +800135b4: 00379793 slli a5,a5,0x3 +800135b8: 01d6d693 srli a3,a3,0x1d +800135bc: 00d7e7b3 or a5,a5,a3 +800135c0: 00f72223 sw a5,4(a4) +800135c4: fee892e3 bne a7,a4,800135a8 <__subtf3+0x968> +800135c8: 03012783 lw a5,48(sp) +800135cc: 00008437 lui s0,0x8 +800135d0: 00000913 li s2,0 +800135d4: 00379793 slli a5,a5,0x3 +800135d8: 02f12823 sw a5,48(sp) +800135dc: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> +800135e0: 891ff06f j 80012e70 <__subtf3+0x230> +800135e4: 00f707b3 add a5,a4,a5 +800135e8: 00e7b733 sltu a4,a5,a4 +800135ec: 00df06b3 add a3,t5,a3 +800135f0: 02f12823 sw a5,48(sp) +800135f4: 00e687b3 add a5,a3,a4 +800135f8: 00e7b733 sltu a4,a5,a4 +800135fc: 01e6b6b3 sltu a3,a3,t5 +80013600: 00e6e733 or a4,a3,a4 +80013604: 00ce86b3 add a3,t4,a2 +80013608: 02f12a23 sw a5,52(sp) +8001360c: 00e687b3 add a5,a3,a4 +80013610: 01d6b633 sltu a2,a3,t4 +80013614: 00e7b6b3 sltu a3,a5,a4 +80013618: 00d666b3 or a3,a2,a3 +8001361c: 00ae0533 add a0,t3,a0 +80013620: 00a68533 add a0,a3,a0 +80013624: 02f12c23 sw a5,56(sp) 80013628: 02a12e23 sw a0,60(sp) -8001362c: ffff8413 addi s0,t6,-1 -80013630: 905ff06f j 80012f34 <__subtf3+0x230> -80013634: 00c6e6b3 or a3,a3,a2 -80013638: 00a6e533 or a0,a3,a0 -8001363c: 00f567b3 or a5,a0,a5 -80013640: 00079c63 bnez a5,80013658 <__subtf3+0x954> -80013644: 02e12823 sw a4,48(sp) -80013648: 03e12a23 sw t5,52(sp) -8001364c: 03d12c23 sw t4,56(sp) -80013650: 03c12e23 sw t3,60(sp) -80013654: fd9ff06f j 8001362c <__subtf3+0x928> -80013658: 03f12e23 sw t6,60(sp) -8001365c: 02012c23 sw zero,56(sp) -80013660: 02012a23 sw zero,52(sp) -80013664: 02012823 sw zero,48(sp) -80013668: 00030713 mv a4,t1 -8001366c: 00072783 lw a5,0(a4) -80013670: ffc72683 lw a3,-4(a4) -80013674: ffc70713 addi a4,a4,-4 -80013678: 00379793 slli a5,a5,0x3 -8001367c: 01d6d693 srli a3,a3,0x1d -80013680: 00d7e7b3 or a5,a5,a3 -80013684: 00f72223 sw a5,4(a4) -80013688: fee892e3 bne a7,a4,8001366c <__subtf3+0x968> -8001368c: 03012783 lw a5,48(sp) -80013690: 00008437 lui s0,0x8 -80013694: 00000913 li s2,0 -80013698: 00379793 slli a5,a5,0x3 -8001369c: 02f12823 sw a5,48(sp) -800136a0: fff40413 addi s0,s0,-1 # 7fff <_start-0x7fff8001> -800136a4: 891ff06f j 80012f34 <__subtf3+0x230> -800136a8: 00f707b3 add a5,a4,a5 -800136ac: 00e7b733 sltu a4,a5,a4 -800136b0: 00df06b3 add a3,t5,a3 -800136b4: 02f12823 sw a5,48(sp) -800136b8: 00e687b3 add a5,a3,a4 -800136bc: 00e7b733 sltu a4,a5,a4 -800136c0: 01e6b6b3 sltu a3,a3,t5 -800136c4: 00e6e733 or a4,a3,a4 -800136c8: 00ce86b3 add a3,t4,a2 -800136cc: 02f12a23 sw a5,52(sp) -800136d0: 00e687b3 add a5,a3,a4 -800136d4: 01d6b633 sltu a2,a3,t4 -800136d8: 00e7b6b3 sltu a3,a5,a4 -800136dc: 00d666b3 or a3,a2,a3 -800136e0: 00ae0533 add a0,t3,a0 -800136e4: 00a68533 add a0,a3,a0 -800136e8: 02f12c23 sw a5,56(sp) -800136ec: 02a12e23 sw a0,60(sp) -800136f0: 00088793 mv a5,a7 -800136f4: 0007a703 lw a4,0(a5) -800136f8: 0047a683 lw a3,4(a5) -800136fc: 00478793 addi a5,a5,4 -80013700: 00175713 srli a4,a4,0x1 -80013704: 01f69693 slli a3,a3,0x1f -80013708: 00d76733 or a4,a4,a3 -8001370c: fee7ae23 sw a4,-4(a5) -80013710: fef312e3 bne t1,a5,800136f4 <__subtf3+0x9f0> -80013714: 000087b7 lui a5,0x8 -80013718: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -8001371c: 00f58c63 beq a1,a5,80013734 <__subtf3+0xa30> -80013720: 03c12783 lw a5,60(sp) -80013724: 0017d793 srli a5,a5,0x1 -80013728: 02f12e23 sw a5,60(sp) -8001372c: 00058413 mv s0,a1 -80013730: 805ff06f j 80012f34 <__subtf3+0x230> -80013734: 02012e23 sw zero,60(sp) -80013738: 02012c23 sw zero,56(sp) -8001373c: 02012a23 sw zero,52(sp) -80013740: 02012823 sw zero,48(sp) -80013744: fe9ff06f j 8001372c <__subtf3+0xa28> -80013748: 2a605e63 blez t1,80013a04 <__subtf3+0xd00> -8001374c: 01412883 lw a7,20(sp) -80013750: 01812e03 lw t3,24(sp) -80013754: 01c12f03 lw t5,28(sp) -80013758: 0c0e9463 bnez t4,80013820 <__subtf3+0xb1c> -8001375c: 02412e83 lw t4,36(sp) -80013760: 02812503 lw a0,40(sp) -80013764: 02c12583 lw a1,44(sp) -80013768: 00aee633 or a2,t4,a0 -8001376c: 00b66633 or a2,a2,a1 -80013770: 00f66633 or a2,a2,a5 -80013774: 00061c63 bnez a2,8001378c <__subtf3+0xa88> -80013778: 02e12823 sw a4,48(sp) -8001377c: 03112a23 sw a7,52(sp) -80013780: 03c12c23 sw t3,56(sp) -80013784: 03e12e23 sw t5,60(sp) -80013788: f08ff06f j 80012e90 <__subtf3+0x18c> -8001378c: fff30613 addi a2,t1,-1 -80013790: 06061463 bnez a2,800137f8 <__subtf3+0xaf4> -80013794: 40f707b3 sub a5,a4,a5 -80013798: 41d886b3 sub a3,a7,t4 -8001379c: 00f73833 sltu a6,a4,a5 -800137a0: 00d8b333 sltu t1,a7,a3 -800137a4: 41068833 sub a6,a3,a6 -800137a8: 00000693 li a3,0 -800137ac: 00f77663 bgeu a4,a5,800137b8 <__subtf3+0xab4> -800137b0: 411e88b3 sub a7,t4,a7 -800137b4: 0018b693 seqz a3,a7 -800137b8: 0066e8b3 or a7,a3,t1 -800137bc: 40ae0733 sub a4,t3,a0 -800137c0: 00ee36b3 sltu a3,t3,a4 -800137c4: 41170733 sub a4,a4,a7 -800137c8: 00088663 beqz a7,800137d4 <__subtf3+0xad0> -800137cc: 41c50e33 sub t3,a0,t3 -800137d0: 001e3613 seqz a2,t3 -800137d4: 40bf05b3 sub a1,t5,a1 -800137d8: 00d66633 or a2,a2,a3 -800137dc: 40c585b3 sub a1,a1,a2 -800137e0: 02b12e23 sw a1,60(sp) -800137e4: 02e12c23 sw a4,56(sp) -800137e8: 03012a23 sw a6,52(sp) -800137ec: 02f12823 sw a5,48(sp) -800137f0: 00100413 li s0,1 -800137f4: 1f00006f j 800139e4 <__subtf3+0xce0> -800137f8: 000087b7 lui a5,0x8 -800137fc: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80013800: f6f30ce3 beq t1,a5,80013778 <__subtf3+0xa74> -80013804: 07400793 li a5,116 -80013808: 04c7da63 bge a5,a2,8001385c <__subtf3+0xb58> -8001380c: 02012623 sw zero,44(sp) -80013810: 02012423 sw zero,40(sp) -80013814: 02012223 sw zero,36(sp) -80013818: 00100793 li a5,1 -8001381c: 1540006f j 80013970 <__subtf3+0xc6c> -80013820: 000087b7 lui a5,0x8 -80013824: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80013828: 00f41c63 bne s0,a5,80013840 <__subtf3+0xb3c> -8001382c: 02e12823 sw a4,48(sp) -80013830: 03112a23 sw a7,52(sp) -80013834: 03c12c23 sw t3,56(sp) -80013838: 03e12e23 sw t5,60(sp) -8001383c: ef8ff06f j 80012f34 <__subtf3+0x230> -80013840: 02c12783 lw a5,44(sp) -80013844: 00080637 lui a2,0x80 -80013848: 00c7e7b3 or a5,a5,a2 -8001384c: 02f12623 sw a5,44(sp) -80013850: 07400793 li a5,116 -80013854: fa67cce3 blt a5,t1,8001380c <__subtf3+0xb08> -80013858: 00030613 mv a2,t1 -8001385c: 40565513 srai a0,a2,0x5 -80013860: 00000313 li t1,0 -80013864: 00000793 li a5,0 -80013868: 04a79663 bne a5,a0,800138b4 <__subtf3+0xbb0> -8001386c: 01f67593 andi a1,a2,31 -80013870: 00251613 slli a2,a0,0x2 -80013874: 04059c63 bnez a1,800138cc <__subtf3+0xbc8> -80013878: 00300593 li a1,3 -8001387c: 00000793 li a5,0 -80013880: 40a585b3 sub a1,a1,a0 -80013884: 00c68eb3 add t4,a3,a2 -80013888: 000eae83 lw t4,0(t4) -8001388c: 00178793 addi a5,a5,1 -80013890: 00468693 addi a3,a3,4 -80013894: ffd6ae23 sw t4,-4(a3) -80013898: fef5d6e3 bge a1,a5,80013884 <__subtf3+0xb80> -8001389c: 00400793 li a5,4 -800138a0: 40a78533 sub a0,a5,a0 -800138a4: 00100793 li a5,1 -800138a8: 06a05c63 blez a0,80013920 <__subtf3+0xc1c> -800138ac: 00050793 mv a5,a0 -800138b0: 0700006f j 80013920 <__subtf3+0xc1c> -800138b4: 00279593 slli a1,a5,0x2 -800138b8: 00b805b3 add a1,a6,a1 -800138bc: 0005a583 lw a1,0(a1) -800138c0: 00178793 addi a5,a5,1 -800138c4: 00b36333 or t1,t1,a1 -800138c8: fa1ff06f j 80013868 <__subtf3+0xb64> -800138cc: 04010793 addi a5,sp,64 -800138d0: 00c787b3 add a5,a5,a2 -800138d4: fe07a783 lw a5,-32(a5) -800138d8: 02000f93 li t6,32 -800138dc: 40bf8fb3 sub t6,t6,a1 -800138e0: 01f797b3 sll a5,a5,t6 -800138e4: 00300693 li a3,3 -800138e8: 00f36333 or t1,t1,a5 -800138ec: 00c80633 add a2,a6,a2 -800138f0: 00000e93 li t4,0 -800138f4: 40a686b3 sub a3,a3,a0 -800138f8: 00460613 addi a2,a2,4 # 80004 <_start-0x7ff7fffc> -800138fc: 02dec663 blt t4,a3,80013928 <__subtf3+0xc24> -80013900: 04010613 addi a2,sp,64 -80013904: 00269693 slli a3,a3,0x2 -80013908: 00d606b3 add a3,a2,a3 -8001390c: 02c12603 lw a2,44(sp) -80013910: 00400793 li a5,4 -80013914: 40a787b3 sub a5,a5,a0 -80013918: 00b65633 srl a2,a2,a1 -8001391c: fec6a023 sw a2,-32(a3) -80013920: 00400613 li a2,4 -80013924: 03c0006f j 80013960 <__subtf3+0xc5c> -80013928: ffc62783 lw a5,-4(a2) -8001392c: 00062383 lw t2,0(a2) -80013930: 002e9293 slli t0,t4,0x2 -80013934: 00b7d7b3 srl a5,a5,a1 -80013938: 01f393b3 sll t2,t2,t6 -8001393c: 005802b3 add t0,a6,t0 -80013940: 0077e7b3 or a5,a5,t2 -80013944: 00f2a023 sw a5,0(t0) -80013948: 001e8e93 addi t4,t4,1 -8001394c: fadff06f j 800138f8 <__subtf3+0xbf4> -80013950: 00279693 slli a3,a5,0x2 -80013954: 00d806b3 add a3,a6,a3 -80013958: 0006a023 sw zero,0(a3) -8001395c: 00178793 addi a5,a5,1 -80013960: fec798e3 bne a5,a2,80013950 <__subtf3+0xc4c> -80013964: 02012683 lw a3,32(sp) -80013968: 006037b3 snez a5,t1 -8001396c: 00f6e7b3 or a5,a3,a5 -80013970: 02f12023 sw a5,32(sp) -80013974: 02012783 lw a5,32(sp) -80013978: 02412583 lw a1,36(sp) -8001397c: 40f707b3 sub a5,a4,a5 -80013980: 40b88633 sub a2,a7,a1 -80013984: 00f736b3 sltu a3,a4,a5 -80013988: 00c8b533 sltu a0,a7,a2 -8001398c: 40d60633 sub a2,a2,a3 -80013990: 00000693 li a3,0 -80013994: 00f77663 bgeu a4,a5,800139a0 <__subtf3+0xc9c> -80013998: 411588b3 sub a7,a1,a7 -8001399c: 0018b693 seqz a3,a7 -800139a0: 00a6e8b3 or a7,a3,a0 -800139a4: 02812503 lw a0,40(sp) -800139a8: 00000693 li a3,0 -800139ac: 40ae0733 sub a4,t3,a0 -800139b0: 00ee3833 sltu a6,t3,a4 -800139b4: 41170733 sub a4,a4,a7 -800139b8: 00088663 beqz a7,800139c4 <__subtf3+0xcc0> -800139bc: 41c50e33 sub t3,a0,t3 -800139c0: 001e3693 seqz a3,t3 -800139c4: 02c12583 lw a1,44(sp) -800139c8: 0106e6b3 or a3,a3,a6 -800139cc: 02e12c23 sw a4,56(sp) -800139d0: 40bf05b3 sub a1,t5,a1 -800139d4: 40d585b3 sub a1,a1,a3 -800139d8: 02b12e23 sw a1,60(sp) -800139dc: 02c12a23 sw a2,52(sp) -800139e0: 02f12823 sw a5,48(sp) -800139e4: 03c12783 lw a5,60(sp) -800139e8: 00c79713 slli a4,a5,0xc -800139ec: d4075463 bgez a4,80012f34 <__subtf3+0x230> -800139f0: 00080737 lui a4,0x80 -800139f4: fff70713 addi a4,a4,-1 # 7ffff <_start-0x7ff80001> -800139f8: 00e7f7b3 and a5,a5,a4 -800139fc: 02f12e23 sw a5,60(sp) -80013a00: 5800006f j 80013f80 <__subtf3+0x127c> -80013a04: 02412803 lw a6,36(sp) -80013a08: 02812883 lw a7,40(sp) -80013a0c: 02c12683 lw a3,44(sp) -80013a10: 2c030263 beqz t1,80013cd4 <__subtf3+0xfd0> -80013a14: 408e8333 sub t1,t4,s0 -80013a18: 0c041263 bnez s0,80013adc <__subtf3+0xdd8> -80013a1c: 01412283 lw t0,20(sp) -80013a20: 01812f83 lw t6,24(sp) -80013a24: 01c12503 lw a0,28(sp) -80013a28: 01f2e633 or a2,t0,t6 -80013a2c: 00a66633 or a2,a2,a0 -80013a30: 00e66633 or a2,a2,a4 -80013a34: 02061063 bnez a2,80013a54 <__subtf3+0xd50> -80013a38: 02f12823 sw a5,48(sp) -80013a3c: 03012a23 sw a6,52(sp) -80013a40: 03112c23 sw a7,56(sp) -80013a44: 02d12e23 sw a3,60(sp) -80013a48: 00030413 mv s0,t1 -80013a4c: 000e0913 mv s2,t3 -80013a50: ce4ff06f j 80012f34 <__subtf3+0x230> -80013a54: fff30613 addi a2,t1,-1 -80013a58: 06061463 bnez a2,80013ac0 <__subtf3+0xdbc> -80013a5c: 40e78733 sub a4,a5,a4 -80013a60: 405805b3 sub a1,a6,t0 -80013a64: 00e7b333 sltu t1,a5,a4 -80013a68: 00b83eb3 sltu t4,a6,a1 -80013a6c: 40658333 sub t1,a1,t1 -80013a70: 00000593 li a1,0 -80013a74: 00e7f663 bgeu a5,a4,80013a80 <__subtf3+0xd7c> -80013a78: 41028833 sub a6,t0,a6 -80013a7c: 00183593 seqz a1,a6 -80013a80: 01d5e833 or a6,a1,t4 -80013a84: 41f885b3 sub a1,a7,t6 -80013a88: 00b8b7b3 sltu a5,a7,a1 -80013a8c: 410585b3 sub a1,a1,a6 -80013a90: 00080663 beqz a6,80013a9c <__subtf3+0xd98> -80013a94: 411f88b3 sub a7,t6,a7 -80013a98: 0018b613 seqz a2,a7 -80013a9c: 40a68533 sub a0,a3,a0 -80013aa0: 00f66633 or a2,a2,a5 -80013aa4: 40c50533 sub a0,a0,a2 -80013aa8: 02a12e23 sw a0,60(sp) -80013aac: 02b12c23 sw a1,56(sp) -80013ab0: 02612a23 sw t1,52(sp) -80013ab4: 02e12823 sw a4,48(sp) -80013ab8: 000e0913 mv s2,t3 -80013abc: d35ff06f j 800137f0 <__subtf3+0xaec> -80013ac0: 00008737 lui a4,0x8 -80013ac4: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80013ac8: f6e308e3 beq t1,a4,80013a38 <__subtf3+0xd34> -80013acc: 07400713 li a4,116 -80013ad0: 1ec74863 blt a4,a2,80013cc0 <__subtf3+0xfbc> -80013ad4: 00060313 mv t1,a2 -80013ad8: 0400006f j 80013b18 <__subtf3+0xe14> -80013adc: 00008737 lui a4,0x8 -80013ae0: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> -80013ae4: 00ee9e63 bne t4,a4,80013b00 <__subtf3+0xdfc> -80013ae8: 02f12823 sw a5,48(sp) -80013aec: 03012a23 sw a6,52(sp) -80013af0: 03112c23 sw a7,56(sp) -80013af4: 02d12e23 sw a3,60(sp) -80013af8: 000e8413 mv s0,t4 -80013afc: f51ff06f j 80013a4c <__subtf3+0xd48> -80013b00: 01c12703 lw a4,28(sp) -80013b04: 00080637 lui a2,0x80 -80013b08: 00c76733 or a4,a4,a2 -80013b0c: 00e12e23 sw a4,28(sp) -80013b10: 07400713 li a4,116 -80013b14: 1a674663 blt a4,t1,80013cc0 <__subtf3+0xfbc> -80013b18: 02000713 li a4,32 -80013b1c: 02e34fb3 div t6,t1,a4 -80013b20: 00000293 li t0,0 -80013b24: 00000713 li a4,0 -80013b28: 05f74a63 blt a4,t6,80013b7c <__subtf3+0xe78> -80013b2c: 000f8513 mv a0,t6 -80013b30: 000fd463 bgez t6,80013b38 <__subtf3+0xe34> -80013b34: 00000513 li a0,0 -80013b38: 01f37713 andi a4,t1,31 -80013b3c: 002f9613 slli a2,t6,0x2 -80013b40: 04071a63 bnez a4,80013b94 <__subtf3+0xe90> -80013b44: 00300513 li a0,3 -80013b48: 41f50533 sub a0,a0,t6 -80013b4c: 00c58333 add t1,a1,a2 -80013b50: 00032303 lw t1,0(t1) -80013b54: 00170713 addi a4,a4,1 -80013b58: 00458593 addi a1,a1,4 -80013b5c: fe65ae23 sw t1,-4(a1) -80013b60: fee556e3 bge a0,a4,80013b4c <__subtf3+0xe48> -80013b64: 00400713 li a4,4 -80013b68: 41f70fb3 sub t6,a4,t6 -80013b6c: 00100713 li a4,1 -80013b70: 09f05063 blez t6,80013bf0 <__subtf3+0xeec> -80013b74: 000f8713 mv a4,t6 -80013b78: 0780006f j 80013bf0 <__subtf3+0xeec> -80013b7c: 00271613 slli a2,a4,0x2 -80013b80: 00cf0633 add a2,t5,a2 -80013b84: 00062603 lw a2,0(a2) # 80000 <_start-0x7ff80000> -80013b88: 00170713 addi a4,a4,1 -80013b8c: 00c2e2b3 or t0,t0,a2 -80013b90: f99ff06f j 80013b28 <__subtf3+0xe24> -80013b94: 02000713 li a4,32 -80013b98: 02e36333 rem t1,t1,a4 -80013b9c: 04010593 addi a1,sp,64 -80013ba0: 00251513 slli a0,a0,0x2 -80013ba4: 00a58533 add a0,a1,a0 -80013ba8: fd052583 lw a1,-48(a0) -80013bac: 00000393 li t2,0 -80013bb0: 40670733 sub a4,a4,t1 -80013bb4: 00e595b3 sll a1,a1,a4 -80013bb8: 00b2e2b3 or t0,t0,a1 -80013bbc: 00cf05b3 add a1,t5,a2 -80013bc0: 00300613 li a2,3 -80013bc4: 41f60633 sub a2,a2,t6 -80013bc8: 00458593 addi a1,a1,4 -80013bcc: 02c3c663 blt t2,a2,80013bf8 <__subtf3+0xef4> -80013bd0: 04010593 addi a1,sp,64 -80013bd4: 00261613 slli a2,a2,0x2 -80013bd8: 00c58633 add a2,a1,a2 -80013bdc: 01c12583 lw a1,28(sp) -80013be0: 00400713 li a4,4 -80013be4: 41f70733 sub a4,a4,t6 -80013be8: 0065d333 srl t1,a1,t1 -80013bec: fc662823 sw t1,-48(a2) -80013bf0: 00300593 li a1,3 -80013bf4: 03c0006f j 80013c30 <__subtf3+0xf2c> -80013bf8: ffc5a503 lw a0,-4(a1) -80013bfc: 0005a903 lw s2,0(a1) -80013c00: 00239413 slli s0,t2,0x2 -80013c04: 00655533 srl a0,a0,t1 -80013c08: 00e91933 sll s2,s2,a4 -80013c0c: 008f0433 add s0,t5,s0 -80013c10: 01256533 or a0,a0,s2 -80013c14: 00a42023 sw a0,0(s0) -80013c18: 00138393 addi t2,t2,1 -80013c1c: fadff06f j 80013bc8 <__subtf3+0xec4> -80013c20: 00271613 slli a2,a4,0x2 -80013c24: 00cf0633 add a2,t5,a2 -80013c28: 00062023 sw zero,0(a2) -80013c2c: 00170713 addi a4,a4,1 -80013c30: fee5d8e3 bge a1,a4,80013c20 <__subtf3+0xf1c> -80013c34: 01012603 lw a2,16(sp) -80013c38: 00503733 snez a4,t0 -80013c3c: 00e66733 or a4,a2,a4 -80013c40: 00e12823 sw a4,16(sp) -80013c44: 01012703 lw a4,16(sp) -80013c48: 01412503 lw a0,20(sp) -80013c4c: 40e78733 sub a4,a5,a4 -80013c50: 40a805b3 sub a1,a6,a0 -80013c54: 00e7b633 sltu a2,a5,a4 -80013c58: 00b83333 sltu t1,a6,a1 -80013c5c: 40c585b3 sub a1,a1,a2 -80013c60: 00000613 li a2,0 -80013c64: 00e7f663 bgeu a5,a4,80013c70 <__subtf3+0xf6c> -80013c68: 41050833 sub a6,a0,a6 -80013c6c: 00183613 seqz a2,a6 -80013c70: 01812503 lw a0,24(sp) -80013c74: 00666833 or a6,a2,t1 -80013c78: 00000613 li a2,0 -80013c7c: 40a887b3 sub a5,a7,a0 -80013c80: 00f8b333 sltu t1,a7,a5 -80013c84: 410787b3 sub a5,a5,a6 -80013c88: 00080663 beqz a6,80013c94 <__subtf3+0xf90> -80013c8c: 411508b3 sub a7,a0,a7 -80013c90: 0018b613 seqz a2,a7 -80013c94: 01c12503 lw a0,28(sp) -80013c98: 00666633 or a2,a2,t1 -80013c9c: 02f12c23 sw a5,56(sp) -80013ca0: 40a686b3 sub a3,a3,a0 -80013ca4: 40c686b3 sub a3,a3,a2 -80013ca8: 02d12e23 sw a3,60(sp) -80013cac: 02b12a23 sw a1,52(sp) -80013cb0: 02e12823 sw a4,48(sp) -80013cb4: 000e8413 mv s0,t4 -80013cb8: 000e0913 mv s2,t3 -80013cbc: d29ff06f j 800139e4 <__subtf3+0xce0> -80013cc0: 00012e23 sw zero,28(sp) -80013cc4: 00012c23 sw zero,24(sp) -80013cc8: 00012a23 sw zero,20(sp) -80013ccc: 00100713 li a4,1 -80013cd0: f71ff06f j 80013c40 <__subtf3+0xf3c> -80013cd4: 00008f37 lui t5,0x8 -80013cd8: ffef0613 addi a2,t5,-2 # 7ffe <_start-0x7fff8002> -80013cdc: 00140e93 addi t4,s0,1 -80013ce0: 00cefeb3 and t4,t4,a2 -80013ce4: 01812583 lw a1,24(sp) -80013ce8: 01412603 lw a2,20(sp) -80013cec: 01c12503 lw a0,28(sp) -80013cf0: 1c0e9c63 bnez t4,80013ec8 <__subtf3+0x11c4> -80013cf4: 01186333 or t1,a6,a7 -80013cf8: 00b66eb3 or t4,a2,a1 -80013cfc: 00d36333 or t1,t1,a3 -80013d00: 00aeeeb3 or t4,t4,a0 -80013d04: 00f36333 or t1,t1,a5 -80013d08: 00eeeeb3 or t4,t4,a4 -80013d0c: 10041663 bnez s0,80013e18 <__subtf3+0x1114> -80013d10: 020e9463 bnez t4,80013d38 <__subtf3+0x1034> -80013d14: 02f12823 sw a5,48(sp) -80013d18: 03012a23 sw a6,52(sp) -80013d1c: 03112c23 sw a7,56(sp) -80013d20: 02d12e23 sw a3,60(sp) -80013d24: 000e0913 mv s2,t3 -80013d28: a0031663 bnez t1,80012f34 <__subtf3+0x230> -80013d2c: 00000413 li s0,0 -80013d30: 00000913 li s2,0 -80013d34: a00ff06f j 80012f34 <__subtf3+0x230> -80013d38: 00031a63 bnez t1,80013d4c <__subtf3+0x1048> +8001362c: 00088793 mv a5,a7 +80013630: 0007a703 lw a4,0(a5) +80013634: 0047a683 lw a3,4(a5) +80013638: 00478793 addi a5,a5,4 +8001363c: 00175713 srli a4,a4,0x1 +80013640: 01f69693 slli a3,a3,0x1f +80013644: 00d76733 or a4,a4,a3 +80013648: fee7ae23 sw a4,-4(a5) +8001364c: fef312e3 bne t1,a5,80013630 <__subtf3+0x9f0> +80013650: 000087b7 lui a5,0x8 +80013654: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80013658: 00f58c63 beq a1,a5,80013670 <__subtf3+0xa30> +8001365c: 03c12783 lw a5,60(sp) +80013660: 0017d793 srli a5,a5,0x1 +80013664: 02f12e23 sw a5,60(sp) +80013668: 00058413 mv s0,a1 +8001366c: 805ff06f j 80012e70 <__subtf3+0x230> +80013670: 02012e23 sw zero,60(sp) +80013674: 02012c23 sw zero,56(sp) +80013678: 02012a23 sw zero,52(sp) +8001367c: 02012823 sw zero,48(sp) +80013680: fe9ff06f j 80013668 <__subtf3+0xa28> +80013684: 2a605e63 blez t1,80013940 <__subtf3+0xd00> +80013688: 01412883 lw a7,20(sp) +8001368c: 01812e03 lw t3,24(sp) +80013690: 01c12f03 lw t5,28(sp) +80013694: 0c0e9463 bnez t4,8001375c <__subtf3+0xb1c> +80013698: 02412e83 lw t4,36(sp) +8001369c: 02812503 lw a0,40(sp) +800136a0: 02c12583 lw a1,44(sp) +800136a4: 00aee633 or a2,t4,a0 +800136a8: 00b66633 or a2,a2,a1 +800136ac: 00f66633 or a2,a2,a5 +800136b0: 00061c63 bnez a2,800136c8 <__subtf3+0xa88> +800136b4: 02e12823 sw a4,48(sp) +800136b8: 03112a23 sw a7,52(sp) +800136bc: 03c12c23 sw t3,56(sp) +800136c0: 03e12e23 sw t5,60(sp) +800136c4: f08ff06f j 80012dcc <__subtf3+0x18c> +800136c8: fff30613 addi a2,t1,-1 +800136cc: 06061463 bnez a2,80013734 <__subtf3+0xaf4> +800136d0: 40f707b3 sub a5,a4,a5 +800136d4: 41d886b3 sub a3,a7,t4 +800136d8: 00f73833 sltu a6,a4,a5 +800136dc: 00d8b333 sltu t1,a7,a3 +800136e0: 41068833 sub a6,a3,a6 +800136e4: 00000693 li a3,0 +800136e8: 00f77663 bgeu a4,a5,800136f4 <__subtf3+0xab4> +800136ec: 411e88b3 sub a7,t4,a7 +800136f0: 0018b693 seqz a3,a7 +800136f4: 0066e8b3 or a7,a3,t1 +800136f8: 40ae0733 sub a4,t3,a0 +800136fc: 00ee36b3 sltu a3,t3,a4 +80013700: 41170733 sub a4,a4,a7 +80013704: 00088663 beqz a7,80013710 <__subtf3+0xad0> +80013708: 41c50e33 sub t3,a0,t3 +8001370c: 001e3613 seqz a2,t3 +80013710: 40bf05b3 sub a1,t5,a1 +80013714: 00d66633 or a2,a2,a3 +80013718: 40c585b3 sub a1,a1,a2 +8001371c: 02b12e23 sw a1,60(sp) +80013720: 02e12c23 sw a4,56(sp) +80013724: 03012a23 sw a6,52(sp) +80013728: 02f12823 sw a5,48(sp) +8001372c: 00100413 li s0,1 +80013730: 1f00006f j 80013920 <__subtf3+0xce0> +80013734: 000087b7 lui a5,0x8 +80013738: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +8001373c: f6f30ce3 beq t1,a5,800136b4 <__subtf3+0xa74> +80013740: 07400793 li a5,116 +80013744: 04c7da63 bge a5,a2,80013798 <__subtf3+0xb58> +80013748: 02012623 sw zero,44(sp) +8001374c: 02012423 sw zero,40(sp) +80013750: 02012223 sw zero,36(sp) +80013754: 00100793 li a5,1 +80013758: 1540006f j 800138ac <__subtf3+0xc6c> +8001375c: 000087b7 lui a5,0x8 +80013760: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +80013764: 00f41c63 bne s0,a5,8001377c <__subtf3+0xb3c> +80013768: 02e12823 sw a4,48(sp) +8001376c: 03112a23 sw a7,52(sp) +80013770: 03c12c23 sw t3,56(sp) +80013774: 03e12e23 sw t5,60(sp) +80013778: ef8ff06f j 80012e70 <__subtf3+0x230> +8001377c: 02c12783 lw a5,44(sp) +80013780: 00080637 lui a2,0x80 +80013784: 00c7e7b3 or a5,a5,a2 +80013788: 02f12623 sw a5,44(sp) +8001378c: 07400793 li a5,116 +80013790: fa67cce3 blt a5,t1,80013748 <__subtf3+0xb08> +80013794: 00030613 mv a2,t1 +80013798: 40565513 srai a0,a2,0x5 +8001379c: 00000313 li t1,0 +800137a0: 00000793 li a5,0 +800137a4: 04a79663 bne a5,a0,800137f0 <__subtf3+0xbb0> +800137a8: 01f67593 andi a1,a2,31 +800137ac: 00251613 slli a2,a0,0x2 +800137b0: 04059c63 bnez a1,80013808 <__subtf3+0xbc8> +800137b4: 00300593 li a1,3 +800137b8: 00000793 li a5,0 +800137bc: 40a585b3 sub a1,a1,a0 +800137c0: 00c68eb3 add t4,a3,a2 +800137c4: 000eae83 lw t4,0(t4) +800137c8: 00178793 addi a5,a5,1 +800137cc: 00468693 addi a3,a3,4 +800137d0: ffd6ae23 sw t4,-4(a3) +800137d4: fef5d6e3 bge a1,a5,800137c0 <__subtf3+0xb80> +800137d8: 00400793 li a5,4 +800137dc: 40a78533 sub a0,a5,a0 +800137e0: 00100793 li a5,1 +800137e4: 06a05c63 blez a0,8001385c <__subtf3+0xc1c> +800137e8: 00050793 mv a5,a0 +800137ec: 0700006f j 8001385c <__subtf3+0xc1c> +800137f0: 00279593 slli a1,a5,0x2 +800137f4: 00b805b3 add a1,a6,a1 +800137f8: 0005a583 lw a1,0(a1) +800137fc: 00178793 addi a5,a5,1 +80013800: 00b36333 or t1,t1,a1 +80013804: fa1ff06f j 800137a4 <__subtf3+0xb64> +80013808: 04010793 addi a5,sp,64 +8001380c: 00c787b3 add a5,a5,a2 +80013810: fe07a783 lw a5,-32(a5) +80013814: 02000f93 li t6,32 +80013818: 40bf8fb3 sub t6,t6,a1 +8001381c: 01f797b3 sll a5,a5,t6 +80013820: 00300693 li a3,3 +80013824: 00f36333 or t1,t1,a5 +80013828: 00c80633 add a2,a6,a2 +8001382c: 00000e93 li t4,0 +80013830: 40a686b3 sub a3,a3,a0 +80013834: 00460613 addi a2,a2,4 # 80004 <_start-0x7ff7fffc> +80013838: 02dec663 blt t4,a3,80013864 <__subtf3+0xc24> +8001383c: 04010613 addi a2,sp,64 +80013840: 00269693 slli a3,a3,0x2 +80013844: 00d606b3 add a3,a2,a3 +80013848: 02c12603 lw a2,44(sp) +8001384c: 00400793 li a5,4 +80013850: 40a787b3 sub a5,a5,a0 +80013854: 00b65633 srl a2,a2,a1 +80013858: fec6a023 sw a2,-32(a3) +8001385c: 00400613 li a2,4 +80013860: 03c0006f j 8001389c <__subtf3+0xc5c> +80013864: ffc62783 lw a5,-4(a2) +80013868: 00062383 lw t2,0(a2) +8001386c: 002e9293 slli t0,t4,0x2 +80013870: 00b7d7b3 srl a5,a5,a1 +80013874: 01f393b3 sll t2,t2,t6 +80013878: 005802b3 add t0,a6,t0 +8001387c: 0077e7b3 or a5,a5,t2 +80013880: 00f2a023 sw a5,0(t0) +80013884: 001e8e93 addi t4,t4,1 +80013888: fadff06f j 80013834 <__subtf3+0xbf4> +8001388c: 00279693 slli a3,a5,0x2 +80013890: 00d806b3 add a3,a6,a3 +80013894: 0006a023 sw zero,0(a3) +80013898: 00178793 addi a5,a5,1 +8001389c: fec798e3 bne a5,a2,8001388c <__subtf3+0xc4c> +800138a0: 02012683 lw a3,32(sp) +800138a4: 006037b3 snez a5,t1 +800138a8: 00f6e7b3 or a5,a3,a5 +800138ac: 02f12023 sw a5,32(sp) +800138b0: 02012783 lw a5,32(sp) +800138b4: 02412583 lw a1,36(sp) +800138b8: 40f707b3 sub a5,a4,a5 +800138bc: 40b88633 sub a2,a7,a1 +800138c0: 00f736b3 sltu a3,a4,a5 +800138c4: 00c8b533 sltu a0,a7,a2 +800138c8: 40d60633 sub a2,a2,a3 +800138cc: 00000693 li a3,0 +800138d0: 00f77663 bgeu a4,a5,800138dc <__subtf3+0xc9c> +800138d4: 411588b3 sub a7,a1,a7 +800138d8: 0018b693 seqz a3,a7 +800138dc: 00a6e8b3 or a7,a3,a0 +800138e0: 02812503 lw a0,40(sp) +800138e4: 00000693 li a3,0 +800138e8: 40ae0733 sub a4,t3,a0 +800138ec: 00ee3833 sltu a6,t3,a4 +800138f0: 41170733 sub a4,a4,a7 +800138f4: 00088663 beqz a7,80013900 <__subtf3+0xcc0> +800138f8: 41c50e33 sub t3,a0,t3 +800138fc: 001e3693 seqz a3,t3 +80013900: 02c12583 lw a1,44(sp) +80013904: 0106e6b3 or a3,a3,a6 +80013908: 02e12c23 sw a4,56(sp) +8001390c: 40bf05b3 sub a1,t5,a1 +80013910: 40d585b3 sub a1,a1,a3 +80013914: 02b12e23 sw a1,60(sp) +80013918: 02c12a23 sw a2,52(sp) +8001391c: 02f12823 sw a5,48(sp) +80013920: 03c12783 lw a5,60(sp) +80013924: 00c79713 slli a4,a5,0xc +80013928: d4075463 bgez a4,80012e70 <__subtf3+0x230> +8001392c: 00080737 lui a4,0x80 +80013930: fff70713 addi a4,a4,-1 # 7ffff <_start-0x7ff80001> +80013934: 00e7f7b3 and a5,a5,a4 +80013938: 02f12e23 sw a5,60(sp) +8001393c: 5800006f j 80013ebc <__subtf3+0x127c> +80013940: 02412803 lw a6,36(sp) +80013944: 02812883 lw a7,40(sp) +80013948: 02c12683 lw a3,44(sp) +8001394c: 2c030263 beqz t1,80013c10 <__subtf3+0xfd0> +80013950: 408e8333 sub t1,t4,s0 +80013954: 0c041263 bnez s0,80013a18 <__subtf3+0xdd8> +80013958: 01412283 lw t0,20(sp) +8001395c: 01812f83 lw t6,24(sp) +80013960: 01c12503 lw a0,28(sp) +80013964: 01f2e633 or a2,t0,t6 +80013968: 00a66633 or a2,a2,a0 +8001396c: 00e66633 or a2,a2,a4 +80013970: 02061063 bnez a2,80013990 <__subtf3+0xd50> +80013974: 02f12823 sw a5,48(sp) +80013978: 03012a23 sw a6,52(sp) +8001397c: 03112c23 sw a7,56(sp) +80013980: 02d12e23 sw a3,60(sp) +80013984: 00030413 mv s0,t1 +80013988: 000e0913 mv s2,t3 +8001398c: ce4ff06f j 80012e70 <__subtf3+0x230> +80013990: fff30613 addi a2,t1,-1 +80013994: 06061463 bnez a2,800139fc <__subtf3+0xdbc> +80013998: 40e78733 sub a4,a5,a4 +8001399c: 405805b3 sub a1,a6,t0 +800139a0: 00e7b333 sltu t1,a5,a4 +800139a4: 00b83eb3 sltu t4,a6,a1 +800139a8: 40658333 sub t1,a1,t1 +800139ac: 00000593 li a1,0 +800139b0: 00e7f663 bgeu a5,a4,800139bc <__subtf3+0xd7c> +800139b4: 41028833 sub a6,t0,a6 +800139b8: 00183593 seqz a1,a6 +800139bc: 01d5e833 or a6,a1,t4 +800139c0: 41f885b3 sub a1,a7,t6 +800139c4: 00b8b7b3 sltu a5,a7,a1 +800139c8: 410585b3 sub a1,a1,a6 +800139cc: 00080663 beqz a6,800139d8 <__subtf3+0xd98> +800139d0: 411f88b3 sub a7,t6,a7 +800139d4: 0018b613 seqz a2,a7 +800139d8: 40a68533 sub a0,a3,a0 +800139dc: 00f66633 or a2,a2,a5 +800139e0: 40c50533 sub a0,a0,a2 +800139e4: 02a12e23 sw a0,60(sp) +800139e8: 02b12c23 sw a1,56(sp) +800139ec: 02612a23 sw t1,52(sp) +800139f0: 02e12823 sw a4,48(sp) +800139f4: 000e0913 mv s2,t3 +800139f8: d35ff06f j 8001372c <__subtf3+0xaec> +800139fc: 00008737 lui a4,0x8 +80013a00: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80013a04: f6e308e3 beq t1,a4,80013974 <__subtf3+0xd34> +80013a08: 07400713 li a4,116 +80013a0c: 1ec74863 blt a4,a2,80013bfc <__subtf3+0xfbc> +80013a10: 00060313 mv t1,a2 +80013a14: 0400006f j 80013a54 <__subtf3+0xe14> +80013a18: 00008737 lui a4,0x8 +80013a1c: fff70713 addi a4,a4,-1 # 7fff <_start-0x7fff8001> +80013a20: 00ee9e63 bne t4,a4,80013a3c <__subtf3+0xdfc> +80013a24: 02f12823 sw a5,48(sp) +80013a28: 03012a23 sw a6,52(sp) +80013a2c: 03112c23 sw a7,56(sp) +80013a30: 02d12e23 sw a3,60(sp) +80013a34: 000e8413 mv s0,t4 +80013a38: f51ff06f j 80013988 <__subtf3+0xd48> +80013a3c: 01c12703 lw a4,28(sp) +80013a40: 00080637 lui a2,0x80 +80013a44: 00c76733 or a4,a4,a2 +80013a48: 00e12e23 sw a4,28(sp) +80013a4c: 07400713 li a4,116 +80013a50: 1a674663 blt a4,t1,80013bfc <__subtf3+0xfbc> +80013a54: 02000713 li a4,32 +80013a58: 02e34fb3 div t6,t1,a4 +80013a5c: 00000293 li t0,0 +80013a60: 00000713 li a4,0 +80013a64: 05f74a63 blt a4,t6,80013ab8 <__subtf3+0xe78> +80013a68: 000f8513 mv a0,t6 +80013a6c: 000fd463 bgez t6,80013a74 <__subtf3+0xe34> +80013a70: 00000513 li a0,0 +80013a74: 01f37713 andi a4,t1,31 +80013a78: 002f9613 slli a2,t6,0x2 +80013a7c: 04071a63 bnez a4,80013ad0 <__subtf3+0xe90> +80013a80: 00300513 li a0,3 +80013a84: 41f50533 sub a0,a0,t6 +80013a88: 00c58333 add t1,a1,a2 +80013a8c: 00032303 lw t1,0(t1) +80013a90: 00170713 addi a4,a4,1 +80013a94: 00458593 addi a1,a1,4 +80013a98: fe65ae23 sw t1,-4(a1) +80013a9c: fee556e3 bge a0,a4,80013a88 <__subtf3+0xe48> +80013aa0: 00400713 li a4,4 +80013aa4: 41f70fb3 sub t6,a4,t6 +80013aa8: 00100713 li a4,1 +80013aac: 09f05063 blez t6,80013b2c <__subtf3+0xeec> +80013ab0: 000f8713 mv a4,t6 +80013ab4: 0780006f j 80013b2c <__subtf3+0xeec> +80013ab8: 00271613 slli a2,a4,0x2 +80013abc: 00cf0633 add a2,t5,a2 +80013ac0: 00062603 lw a2,0(a2) # 80000 <_start-0x7ff80000> +80013ac4: 00170713 addi a4,a4,1 +80013ac8: 00c2e2b3 or t0,t0,a2 +80013acc: f99ff06f j 80013a64 <__subtf3+0xe24> +80013ad0: 02000713 li a4,32 +80013ad4: 02e36333 rem t1,t1,a4 +80013ad8: 04010593 addi a1,sp,64 +80013adc: 00251513 slli a0,a0,0x2 +80013ae0: 00a58533 add a0,a1,a0 +80013ae4: fd052583 lw a1,-48(a0) +80013ae8: 00000393 li t2,0 +80013aec: 40670733 sub a4,a4,t1 +80013af0: 00e595b3 sll a1,a1,a4 +80013af4: 00b2e2b3 or t0,t0,a1 +80013af8: 00cf05b3 add a1,t5,a2 +80013afc: 00300613 li a2,3 +80013b00: 41f60633 sub a2,a2,t6 +80013b04: 00458593 addi a1,a1,4 +80013b08: 02c3c663 blt t2,a2,80013b34 <__subtf3+0xef4> +80013b0c: 04010593 addi a1,sp,64 +80013b10: 00261613 slli a2,a2,0x2 +80013b14: 00c58633 add a2,a1,a2 +80013b18: 01c12583 lw a1,28(sp) +80013b1c: 00400713 li a4,4 +80013b20: 41f70733 sub a4,a4,t6 +80013b24: 0065d333 srl t1,a1,t1 +80013b28: fc662823 sw t1,-48(a2) +80013b2c: 00300593 li a1,3 +80013b30: 03c0006f j 80013b6c <__subtf3+0xf2c> +80013b34: ffc5a503 lw a0,-4(a1) +80013b38: 0005a903 lw s2,0(a1) +80013b3c: 00239413 slli s0,t2,0x2 +80013b40: 00655533 srl a0,a0,t1 +80013b44: 00e91933 sll s2,s2,a4 +80013b48: 008f0433 add s0,t5,s0 +80013b4c: 01256533 or a0,a0,s2 +80013b50: 00a42023 sw a0,0(s0) +80013b54: 00138393 addi t2,t2,1 +80013b58: fadff06f j 80013b04 <__subtf3+0xec4> +80013b5c: 00271613 slli a2,a4,0x2 +80013b60: 00cf0633 add a2,t5,a2 +80013b64: 00062023 sw zero,0(a2) +80013b68: 00170713 addi a4,a4,1 +80013b6c: fee5d8e3 bge a1,a4,80013b5c <__subtf3+0xf1c> +80013b70: 01012603 lw a2,16(sp) +80013b74: 00503733 snez a4,t0 +80013b78: 00e66733 or a4,a2,a4 +80013b7c: 00e12823 sw a4,16(sp) +80013b80: 01012703 lw a4,16(sp) +80013b84: 01412503 lw a0,20(sp) +80013b88: 40e78733 sub a4,a5,a4 +80013b8c: 40a805b3 sub a1,a6,a0 +80013b90: 00e7b633 sltu a2,a5,a4 +80013b94: 00b83333 sltu t1,a6,a1 +80013b98: 40c585b3 sub a1,a1,a2 +80013b9c: 00000613 li a2,0 +80013ba0: 00e7f663 bgeu a5,a4,80013bac <__subtf3+0xf6c> +80013ba4: 41050833 sub a6,a0,a6 +80013ba8: 00183613 seqz a2,a6 +80013bac: 01812503 lw a0,24(sp) +80013bb0: 00666833 or a6,a2,t1 +80013bb4: 00000613 li a2,0 +80013bb8: 40a887b3 sub a5,a7,a0 +80013bbc: 00f8b333 sltu t1,a7,a5 +80013bc0: 410787b3 sub a5,a5,a6 +80013bc4: 00080663 beqz a6,80013bd0 <__subtf3+0xf90> +80013bc8: 411508b3 sub a7,a0,a7 +80013bcc: 0018b613 seqz a2,a7 +80013bd0: 01c12503 lw a0,28(sp) +80013bd4: 00666633 or a2,a2,t1 +80013bd8: 02f12c23 sw a5,56(sp) +80013bdc: 40a686b3 sub a3,a3,a0 +80013be0: 40c686b3 sub a3,a3,a2 +80013be4: 02d12e23 sw a3,60(sp) +80013be8: 02b12a23 sw a1,52(sp) +80013bec: 02e12823 sw a4,48(sp) +80013bf0: 000e8413 mv s0,t4 +80013bf4: 000e0913 mv s2,t3 +80013bf8: d29ff06f j 80013920 <__subtf3+0xce0> +80013bfc: 00012e23 sw zero,28(sp) +80013c00: 00012c23 sw zero,24(sp) +80013c04: 00012a23 sw zero,20(sp) +80013c08: 00100713 li a4,1 +80013c0c: f71ff06f j 80013b7c <__subtf3+0xf3c> +80013c10: 00008f37 lui t5,0x8 +80013c14: ffef0613 addi a2,t5,-2 # 7ffe <_start-0x7fff8002> +80013c18: 00140e93 addi t4,s0,1 +80013c1c: 00cefeb3 and t4,t4,a2 +80013c20: 01812583 lw a1,24(sp) +80013c24: 01412603 lw a2,20(sp) +80013c28: 01c12503 lw a0,28(sp) +80013c2c: 1c0e9c63 bnez t4,80013e04 <__subtf3+0x11c4> +80013c30: 01186333 or t1,a6,a7 +80013c34: 00b66eb3 or t4,a2,a1 +80013c38: 00d36333 or t1,t1,a3 +80013c3c: 00aeeeb3 or t4,t4,a0 +80013c40: 00f36333 or t1,t1,a5 +80013c44: 00eeeeb3 or t4,t4,a4 +80013c48: 10041663 bnez s0,80013d54 <__subtf3+0x1114> +80013c4c: 020e9463 bnez t4,80013c74 <__subtf3+0x1034> +80013c50: 02f12823 sw a5,48(sp) +80013c54: 03012a23 sw a6,52(sp) +80013c58: 03112c23 sw a7,56(sp) +80013c5c: 02d12e23 sw a3,60(sp) +80013c60: 000e0913 mv s2,t3 +80013c64: a0031663 bnez t1,80012e70 <__subtf3+0x230> +80013c68: 00000413 li s0,0 +80013c6c: 00000913 li s2,0 +80013c70: a00ff06f j 80012e70 <__subtf3+0x230> +80013c74: 00031a63 bnez t1,80013c88 <__subtf3+0x1048> +80013c78: 02e12823 sw a4,48(sp) +80013c7c: 02c12a23 sw a2,52(sp) +80013c80: 02b12c23 sw a1,56(sp) +80013c84: 839ff06f j 800134bc <__subtf3+0x87c> +80013c88: 40f70333 sub t1,a4,a5 +80013c8c: 410603b3 sub t2,a2,a6 +80013c90: 00673fb3 sltu t6,a4,t1 +80013c94: 00763eb3 sltu t4,a2,t2 +80013c98: 41f38fb3 sub t6,t2,t6 +80013c9c: 00000f13 li t5,0 +80013ca0: 00677463 bgeu a4,t1,80013ca8 <__subtf3+0x1068> +80013ca4: 0013bf13 seqz t5,t2 +80013ca8: 411582b3 sub t0,a1,a7 +80013cac: 01df6f33 or t5,t5,t4 +80013cb0: 0055bab3 sltu s5,a1,t0 +80013cb4: 41e28a33 sub s4,t0,t5 +80013cb8: 00000993 li s3,0 +80013cbc: 000f0463 beqz t5,80013cc4 <__subtf3+0x1084> +80013cc0: 0012b993 seqz s3,t0 +80013cc4: 40d50eb3 sub t4,a0,a3 +80013cc8: 0159e9b3 or s3,s3,s5 +80013ccc: 413e8eb3 sub t4,t4,s3 +80013cd0: 03d12e23 sw t4,60(sp) +80013cd4: 03412c23 sw s4,56(sp) +80013cd8: 03f12a23 sw t6,52(sp) +80013cdc: 02612823 sw t1,48(sp) +80013ce0: 00ce9f13 slli t5,t4,0xc +80013ce4: 060f5063 bgez t5,80013d44 <__subtf3+0x1104> +80013ce8: 40c80633 sub a2,a6,a2 +80013cec: 40e78733 sub a4,a5,a4 +80013cf0: 00c83333 sltu t1,a6,a2 +80013cf4: 00e7b833 sltu a6,a5,a4 +80013cf8: 41060633 sub a2,a2,a6 +80013cfc: 00000813 li a6,0 +80013d00: 00e7f463 bgeu a5,a4,80013d08 <__subtf3+0x10c8> +80013d04: 0013b813 seqz a6,t2 +80013d08: 00686833 or a6,a6,t1 +80013d0c: 40b885b3 sub a1,a7,a1 +80013d10: 00b8b8b3 sltu a7,a7,a1 +80013d14: 00000313 li t1,0 +80013d18: 410585b3 sub a1,a1,a6 +80013d1c: 00080463 beqz a6,80013d24 <__subtf3+0x10e4> +80013d20: 0012b313 seqz t1,t0 +80013d24: 40a68533 sub a0,a3,a0 +80013d28: 01136333 or t1,t1,a7 +80013d2c: 40650333 sub t1,a0,t1 +80013d30: 02612e23 sw t1,60(sp) +80013d34: 02b12c23 sw a1,56(sp) +80013d38: 02c12a23 sw a2,52(sp) 80013d3c: 02e12823 sw a4,48(sp) -80013d40: 02c12a23 sw a2,52(sp) -80013d44: 02b12c23 sw a1,56(sp) -80013d48: 839ff06f j 80013580 <__subtf3+0x87c> -80013d4c: 40f70333 sub t1,a4,a5 -80013d50: 410603b3 sub t2,a2,a6 -80013d54: 00673fb3 sltu t6,a4,t1 -80013d58: 00763eb3 sltu t4,a2,t2 -80013d5c: 41f38fb3 sub t6,t2,t6 -80013d60: 00000f13 li t5,0 -80013d64: 00677463 bgeu a4,t1,80013d6c <__subtf3+0x1068> -80013d68: 0013bf13 seqz t5,t2 -80013d6c: 411582b3 sub t0,a1,a7 -80013d70: 01df6f33 or t5,t5,t4 -80013d74: 0055bab3 sltu s5,a1,t0 -80013d78: 41e28a33 sub s4,t0,t5 -80013d7c: 00000993 li s3,0 -80013d80: 000f0463 beqz t5,80013d88 <__subtf3+0x1084> -80013d84: 0012b993 seqz s3,t0 -80013d88: 40d50eb3 sub t4,a0,a3 -80013d8c: 0159e9b3 or s3,s3,s5 -80013d90: 413e8eb3 sub t4,t4,s3 -80013d94: 03d12e23 sw t4,60(sp) -80013d98: 03412c23 sw s4,56(sp) -80013d9c: 03f12a23 sw t6,52(sp) -80013da0: 02612823 sw t1,48(sp) -80013da4: 00ce9f13 slli t5,t4,0xc -80013da8: 060f5063 bgez t5,80013e08 <__subtf3+0x1104> -80013dac: 40c80633 sub a2,a6,a2 -80013db0: 40e78733 sub a4,a5,a4 -80013db4: 00c83333 sltu t1,a6,a2 -80013db8: 00e7b833 sltu a6,a5,a4 -80013dbc: 41060633 sub a2,a2,a6 -80013dc0: 00000813 li a6,0 -80013dc4: 00e7f463 bgeu a5,a4,80013dcc <__subtf3+0x10c8> -80013dc8: 0013b813 seqz a6,t2 -80013dcc: 00686833 or a6,a6,t1 -80013dd0: 40b885b3 sub a1,a7,a1 -80013dd4: 00b8b8b3 sltu a7,a7,a1 -80013dd8: 00000313 li t1,0 -80013ddc: 410585b3 sub a1,a1,a6 -80013de0: 00080463 beqz a6,80013de8 <__subtf3+0x10e4> -80013de4: 0012b313 seqz t1,t0 -80013de8: 40a68533 sub a0,a3,a0 -80013dec: 01136333 or t1,t1,a7 -80013df0: 40650333 sub t1,a0,t1 -80013df4: 02612e23 sw t1,60(sp) -80013df8: 02b12c23 sw a1,56(sp) -80013dfc: 02c12a23 sw a2,52(sp) -80013e00: 02e12823 sw a4,48(sp) -80013e04: c49ff06f j 80013a4c <__subtf3+0xd48> -80013e08: 01f36333 or t1,t1,t6 -80013e0c: 01436333 or t1,t1,s4 -80013e10: 01d36333 or t1,t1,t4 -80013e14: f15ff06f j 80013d28 <__subtf3+0x1024> -80013e18: 03010f93 addi t6,sp,48 -80013e1c: 040e9e63 bnez t4,80013e78 <__subtf3+0x1174> -80013e20: 02031e63 bnez t1,80013e5c <__subtf3+0x1158> -80013e24: 03e12e23 sw t5,60(sp) -80013e28: 02012c23 sw zero,56(sp) -80013e2c: 02012a23 sw zero,52(sp) -80013e30: 02012823 sw zero,48(sp) -80013e34: 03c10793 addi a5,sp,60 -80013e38: 0007a703 lw a4,0(a5) -80013e3c: ffc7a683 lw a3,-4(a5) -80013e40: ffc78793 addi a5,a5,-4 -80013e44: 00371713 slli a4,a4,0x3 -80013e48: 01d6d693 srli a3,a3,0x1d -80013e4c: 00d76733 or a4,a4,a3 -80013e50: 00e7a223 sw a4,4(a5) -80013e54: feff92e3 bne t6,a5,80013e38 <__subtf3+0x1134> -80013e58: 835ff06f j 8001368c <__subtf3+0x988> -80013e5c: 02f12823 sw a5,48(sp) -80013e60: 03012a23 sw a6,52(sp) -80013e64: 03112c23 sw a7,56(sp) -80013e68: 02d12e23 sw a3,60(sp) -80013e6c: 000e0913 mv s2,t3 -80013e70: ffff0413 addi s0,t5,-1 -80013e74: 8c0ff06f j 80012f34 <__subtf3+0x230> -80013e78: 00031c63 bnez t1,80013e90 <__subtf3+0x118c> -80013e7c: 02e12823 sw a4,48(sp) -80013e80: 02c12a23 sw a2,52(sp) -80013e84: 02b12c23 sw a1,56(sp) -80013e88: 02a12e23 sw a0,60(sp) -80013e8c: fe5ff06f j 80013e70 <__subtf3+0x116c> -80013e90: 03e12e23 sw t5,60(sp) -80013e94: 02012c23 sw zero,56(sp) -80013e98: 02012a23 sw zero,52(sp) -80013e9c: 02012823 sw zero,48(sp) -80013ea0: 03c10793 addi a5,sp,60 -80013ea4: 0007a703 lw a4,0(a5) -80013ea8: ffc7a683 lw a3,-4(a5) -80013eac: ffc78793 addi a5,a5,-4 -80013eb0: 00371713 slli a4,a4,0x3 -80013eb4: 01d6d693 srli a3,a3,0x1d -80013eb8: 00d76733 or a4,a4,a3 -80013ebc: 00e7a223 sw a4,4(a5) -80013ec0: feff92e3 bne t6,a5,80013ea4 <__subtf3+0x11a0> -80013ec4: fc8ff06f j 8001368c <__subtf3+0x988> -80013ec8: 40f70eb3 sub t4,a4,a5 -80013ecc: 410609b3 sub s3,a2,a6 -80013ed0: 01d732b3 sltu t0,a4,t4 -80013ed4: 01363f33 sltu t5,a2,s3 -80013ed8: 405982b3 sub t0,s3,t0 -80013edc: 00000f93 li t6,0 -80013ee0: 01d77463 bgeu a4,t4,80013ee8 <__subtf3+0x11e4> -80013ee4: 0019bf93 seqz t6,s3 -80013ee8: 411583b3 sub t2,a1,a7 -80013eec: 01efefb3 or t6,t6,t5 -80013ef0: 0075bb33 sltu s6,a1,t2 -80013ef4: 41f38ab3 sub s5,t2,t6 -80013ef8: 00000a13 li s4,0 -80013efc: 000f8463 beqz t6,80013f04 <__subtf3+0x1200> -80013f00: 0013ba13 seqz s4,t2 -80013f04: 40d50f33 sub t5,a0,a3 -80013f08: 016a6a33 or s4,s4,s6 -80013f0c: 414f0f33 sub t5,t5,s4 -80013f10: 03e12e23 sw t5,60(sp) -80013f14: 03512c23 sw s5,56(sp) -80013f18: 02512a23 sw t0,52(sp) -80013f1c: 03d12823 sw t4,48(sp) -80013f20: 00cf1f93 slli t6,t5,0xc -80013f24: 0c0fd063 bgez t6,80013fe4 <__subtf3+0x12e0> -80013f28: 40c80633 sub a2,a6,a2 -80013f2c: 40e78733 sub a4,a5,a4 -80013f30: 00c83eb3 sltu t4,a6,a2 -80013f34: 00e7b833 sltu a6,a5,a4 -80013f38: 41060633 sub a2,a2,a6 -80013f3c: 00000813 li a6,0 -80013f40: 00e7f463 bgeu a5,a4,80013f48 <__subtf3+0x1244> -80013f44: 0019b813 seqz a6,s3 -80013f48: 40b885b3 sub a1,a7,a1 -80013f4c: 01d86833 or a6,a6,t4 -80013f50: 00b8b8b3 sltu a7,a7,a1 -80013f54: 410585b3 sub a1,a1,a6 -80013f58: 00080463 beqz a6,80013f60 <__subtf3+0x125c> -80013f5c: 0013b313 seqz t1,t2 -80013f60: 40a68533 sub a0,a3,a0 -80013f64: 011366b3 or a3,t1,a7 -80013f68: 40d506b3 sub a3,a0,a3 -80013f6c: 02d12e23 sw a3,60(sp) -80013f70: 02b12c23 sw a1,56(sp) -80013f74: 02c12a23 sw a2,52(sp) -80013f78: 02e12823 sw a4,48(sp) -80013f7c: 000e0913 mv s2,t3 -80013f80: 03c12503 lw a0,60(sp) -80013f84: 06050a63 beqz a0,80013ff8 <__subtf3+0x12f4> -80013f88: 241000ef jal ra,800149c8 <__clzsi2> -80013f8c: ff450793 addi a5,a0,-12 -80013f90: 02000613 li a2,32 -80013f94: 01f7f693 andi a3,a5,31 -80013f98: 02c7c733 div a4,a5,a2 -80013f9c: 08068a63 beqz a3,80014030 <__subtf3+0x132c> -80013fa0: ffc00693 li a3,-4 -80013fa4: 03010313 addi t1,sp,48 -80013fa8: 00271513 slli a0,a4,0x2 -80013fac: 02c7e833 rem a6,a5,a2 -80013fb0: 02d706b3 mul a3,a4,a3 -80013fb4: 41060633 sub a2,a2,a6 -80013fb8: 00c68693 addi a3,a3,12 -80013fbc: 00d306b3 add a3,t1,a3 -80013fc0: 0ad31063 bne t1,a3,80014060 <__subtf3+0x135c> -80013fc4: 04010693 addi a3,sp,64 -80013fc8: 00a68533 add a0,a3,a0 -80013fcc: 03012683 lw a3,48(sp) +80013d40: c49ff06f j 80013988 <__subtf3+0xd48> +80013d44: 01f36333 or t1,t1,t6 +80013d48: 01436333 or t1,t1,s4 +80013d4c: 01d36333 or t1,t1,t4 +80013d50: f15ff06f j 80013c64 <__subtf3+0x1024> +80013d54: 03010f93 addi t6,sp,48 +80013d58: 040e9e63 bnez t4,80013db4 <__subtf3+0x1174> +80013d5c: 02031e63 bnez t1,80013d98 <__subtf3+0x1158> +80013d60: 03e12e23 sw t5,60(sp) +80013d64: 02012c23 sw zero,56(sp) +80013d68: 02012a23 sw zero,52(sp) +80013d6c: 02012823 sw zero,48(sp) +80013d70: 03c10793 addi a5,sp,60 +80013d74: 0007a703 lw a4,0(a5) +80013d78: ffc7a683 lw a3,-4(a5) +80013d7c: ffc78793 addi a5,a5,-4 +80013d80: 00371713 slli a4,a4,0x3 +80013d84: 01d6d693 srli a3,a3,0x1d +80013d88: 00d76733 or a4,a4,a3 +80013d8c: 00e7a223 sw a4,4(a5) +80013d90: feff92e3 bne t6,a5,80013d74 <__subtf3+0x1134> +80013d94: 835ff06f j 800135c8 <__subtf3+0x988> +80013d98: 02f12823 sw a5,48(sp) +80013d9c: 03012a23 sw a6,52(sp) +80013da0: 03112c23 sw a7,56(sp) +80013da4: 02d12e23 sw a3,60(sp) +80013da8: 000e0913 mv s2,t3 +80013dac: ffff0413 addi s0,t5,-1 +80013db0: 8c0ff06f j 80012e70 <__subtf3+0x230> +80013db4: 00031c63 bnez t1,80013dcc <__subtf3+0x118c> +80013db8: 02e12823 sw a4,48(sp) +80013dbc: 02c12a23 sw a2,52(sp) +80013dc0: 02b12c23 sw a1,56(sp) +80013dc4: 02a12e23 sw a0,60(sp) +80013dc8: fe5ff06f j 80013dac <__subtf3+0x116c> +80013dcc: 03e12e23 sw t5,60(sp) +80013dd0: 02012c23 sw zero,56(sp) +80013dd4: 02012a23 sw zero,52(sp) +80013dd8: 02012823 sw zero,48(sp) +80013ddc: 03c10793 addi a5,sp,60 +80013de0: 0007a703 lw a4,0(a5) +80013de4: ffc7a683 lw a3,-4(a5) +80013de8: ffc78793 addi a5,a5,-4 +80013dec: 00371713 slli a4,a4,0x3 +80013df0: 01d6d693 srli a3,a3,0x1d +80013df4: 00d76733 or a4,a4,a3 +80013df8: 00e7a223 sw a4,4(a5) +80013dfc: feff92e3 bne t6,a5,80013de0 <__subtf3+0x11a0> +80013e00: fc8ff06f j 800135c8 <__subtf3+0x988> +80013e04: 40f70eb3 sub t4,a4,a5 +80013e08: 410609b3 sub s3,a2,a6 +80013e0c: 01d732b3 sltu t0,a4,t4 +80013e10: 01363f33 sltu t5,a2,s3 +80013e14: 405982b3 sub t0,s3,t0 +80013e18: 00000f93 li t6,0 +80013e1c: 01d77463 bgeu a4,t4,80013e24 <__subtf3+0x11e4> +80013e20: 0019bf93 seqz t6,s3 +80013e24: 411583b3 sub t2,a1,a7 +80013e28: 01efefb3 or t6,t6,t5 +80013e2c: 0075bb33 sltu s6,a1,t2 +80013e30: 41f38ab3 sub s5,t2,t6 +80013e34: 00000a13 li s4,0 +80013e38: 000f8463 beqz t6,80013e40 <__subtf3+0x1200> +80013e3c: 0013ba13 seqz s4,t2 +80013e40: 40d50f33 sub t5,a0,a3 +80013e44: 016a6a33 or s4,s4,s6 +80013e48: 414f0f33 sub t5,t5,s4 +80013e4c: 03e12e23 sw t5,60(sp) +80013e50: 03512c23 sw s5,56(sp) +80013e54: 02512a23 sw t0,52(sp) +80013e58: 03d12823 sw t4,48(sp) +80013e5c: 00cf1f93 slli t6,t5,0xc +80013e60: 0c0fd063 bgez t6,80013f20 <__subtf3+0x12e0> +80013e64: 40c80633 sub a2,a6,a2 +80013e68: 40e78733 sub a4,a5,a4 +80013e6c: 00c83eb3 sltu t4,a6,a2 +80013e70: 00e7b833 sltu a6,a5,a4 +80013e74: 41060633 sub a2,a2,a6 +80013e78: 00000813 li a6,0 +80013e7c: 00e7f463 bgeu a5,a4,80013e84 <__subtf3+0x1244> +80013e80: 0019b813 seqz a6,s3 +80013e84: 40b885b3 sub a1,a7,a1 +80013e88: 01d86833 or a6,a6,t4 +80013e8c: 00b8b8b3 sltu a7,a7,a1 +80013e90: 410585b3 sub a1,a1,a6 +80013e94: 00080463 beqz a6,80013e9c <__subtf3+0x125c> +80013e98: 0013b313 seqz t1,t2 +80013e9c: 40a68533 sub a0,a3,a0 +80013ea0: 011366b3 or a3,t1,a7 +80013ea4: 40d506b3 sub a3,a0,a3 +80013ea8: 02d12e23 sw a3,60(sp) +80013eac: 02b12c23 sw a1,56(sp) +80013eb0: 02c12a23 sw a2,52(sp) +80013eb4: 02e12823 sw a4,48(sp) +80013eb8: 000e0913 mv s2,t3 +80013ebc: 03c12503 lw a0,60(sp) +80013ec0: 06050a63 beqz a0,80013f34 <__subtf3+0x12f4> +80013ec4: 241000ef jal ra,80014904 <__clzsi2> +80013ec8: ff450793 addi a5,a0,-12 +80013ecc: 02000613 li a2,32 +80013ed0: 01f7f693 andi a3,a5,31 +80013ed4: 02c7c733 div a4,a5,a2 +80013ed8: 08068a63 beqz a3,80013f6c <__subtf3+0x132c> +80013edc: ffc00693 li a3,-4 +80013ee0: 03010313 addi t1,sp,48 +80013ee4: 00271513 slli a0,a4,0x2 +80013ee8: 02c7e833 rem a6,a5,a2 +80013eec: 02d706b3 mul a3,a4,a3 +80013ef0: 41060633 sub a2,a2,a6 +80013ef4: 00c68693 addi a3,a3,12 +80013ef8: 00d306b3 add a3,t1,a3 +80013efc: 0ad31063 bne t1,a3,80013f9c <__subtf3+0x135c> +80013f00: 04010693 addi a3,sp,64 +80013f04: 00a68533 add a0,a3,a0 +80013f08: 03012683 lw a3,48(sp) +80013f0c: fff70713 addi a4,a4,-1 +80013f10: 010696b3 sll a3,a3,a6 +80013f14: fed52823 sw a3,-16(a0) +80013f18: fff00613 li a2,-1 +80013f1c: 0b80006f j 80013fd4 <__subtf3+0x1394> +80013f20: 005eeeb3 or t4,t4,t0 +80013f24: 015eeeb3 or t4,t4,s5 +80013f28: 01eeeeb3 or t4,t4,t5 +80013f2c: d20e8ee3 beqz t4,80013c68 <__subtf3+0x1028> +80013f30: f8dff06f j 80013ebc <__subtf3+0x127c> +80013f34: 03812503 lw a0,56(sp) +80013f38: 00050863 beqz a0,80013f48 <__subtf3+0x1308> +80013f3c: 1c9000ef jal ra,80014904 <__clzsi2> +80013f40: 02050513 addi a0,a0,32 +80013f44: f85ff06f j 80013ec8 <__subtf3+0x1288> +80013f48: 03412503 lw a0,52(sp) +80013f4c: 00050863 beqz a0,80013f5c <__subtf3+0x131c> +80013f50: 1b5000ef jal ra,80014904 <__clzsi2> +80013f54: 04050513 addi a0,a0,64 +80013f58: f71ff06f j 80013ec8 <__subtf3+0x1288> +80013f5c: 03012503 lw a0,48(sp) +80013f60: 1a5000ef jal ra,80014904 <__clzsi2> +80013f64: 06050513 addi a0,a0,96 +80013f68: f61ff06f j 80013ec8 <__subtf3+0x1288> +80013f6c: ffc00593 li a1,-4 +80013f70: 02b705b3 mul a1,a4,a1 +80013f74: 03c10693 addi a3,sp,60 +80013f78: 00300613 li a2,3 +80013f7c: 00b68533 add a0,a3,a1 +80013f80: 00052503 lw a0,0(a0) +80013f84: fff60613 addi a2,a2,-1 +80013f88: ffc68693 addi a3,a3,-4 +80013f8c: 00a6a223 sw a0,4(a3) +80013f90: fee656e3 bge a2,a4,80013f7c <__subtf3+0x133c> +80013f94: fff70713 addi a4,a4,-1 +80013f98: f81ff06f j 80013f18 <__subtf3+0x12d8> +80013f9c: ffc6a583 lw a1,-4(a3) +80013fa0: 0006a883 lw a7,0(a3) +80013fa4: 00a68e33 add t3,a3,a0 +80013fa8: 00c5d5b3 srl a1,a1,a2 +80013fac: 010898b3 sll a7,a7,a6 +80013fb0: 0115e5b3 or a1,a1,a7 +80013fb4: 00be2023 sw a1,0(t3) +80013fb8: ffc68693 addi a3,a3,-4 +80013fbc: f41ff06f j 80013efc <__subtf3+0x12bc> +80013fc0: 00271693 slli a3,a4,0x2 +80013fc4: 03010593 addi a1,sp,48 +80013fc8: 00d586b3 add a3,a1,a3 +80013fcc: 0006a023 sw zero,0(a3) 80013fd0: fff70713 addi a4,a4,-1 -80013fd4: 010696b3 sll a3,a3,a6 -80013fd8: fed52823 sw a3,-16(a0) -80013fdc: fff00613 li a2,-1 -80013fe0: 0b80006f j 80014098 <__subtf3+0x1394> -80013fe4: 005eeeb3 or t4,t4,t0 -80013fe8: 015eeeb3 or t4,t4,s5 -80013fec: 01eeeeb3 or t4,t4,t5 -80013ff0: d20e8ee3 beqz t4,80013d2c <__subtf3+0x1028> -80013ff4: f8dff06f j 80013f80 <__subtf3+0x127c> -80013ff8: 03812503 lw a0,56(sp) -80013ffc: 00050863 beqz a0,8001400c <__subtf3+0x1308> -80014000: 1c9000ef jal ra,800149c8 <__clzsi2> -80014004: 02050513 addi a0,a0,32 -80014008: f85ff06f j 80013f8c <__subtf3+0x1288> -8001400c: 03412503 lw a0,52(sp) -80014010: 00050863 beqz a0,80014020 <__subtf3+0x131c> -80014014: 1b5000ef jal ra,800149c8 <__clzsi2> -80014018: 04050513 addi a0,a0,64 -8001401c: f71ff06f j 80013f8c <__subtf3+0x1288> -80014020: 03012503 lw a0,48(sp) -80014024: 1a5000ef jal ra,800149c8 <__clzsi2> -80014028: 06050513 addi a0,a0,96 -8001402c: f61ff06f j 80013f8c <__subtf3+0x1288> -80014030: ffc00593 li a1,-4 -80014034: 02b705b3 mul a1,a4,a1 -80014038: 03c10693 addi a3,sp,60 -8001403c: 00300613 li a2,3 -80014040: 00b68533 add a0,a3,a1 -80014044: 00052503 lw a0,0(a0) -80014048: fff60613 addi a2,a2,-1 -8001404c: ffc68693 addi a3,a3,-4 -80014050: 00a6a223 sw a0,4(a3) -80014054: fee656e3 bge a2,a4,80014040 <__subtf3+0x133c> -80014058: fff70713 addi a4,a4,-1 -8001405c: f81ff06f j 80013fdc <__subtf3+0x12d8> -80014060: ffc6a583 lw a1,-4(a3) -80014064: 0006a883 lw a7,0(a3) -80014068: 00a68e33 add t3,a3,a0 -8001406c: 00c5d5b3 srl a1,a1,a2 -80014070: 010898b3 sll a7,a7,a6 -80014074: 0115e5b3 or a1,a1,a7 -80014078: 00be2023 sw a1,0(t3) -8001407c: ffc68693 addi a3,a3,-4 -80014080: f41ff06f j 80013fc0 <__subtf3+0x12bc> -80014084: 00271693 slli a3,a4,0x2 -80014088: 03010593 addi a1,sp,48 -8001408c: 00d586b3 add a3,a1,a3 -80014090: 0006a023 sw zero,0(a3) -80014094: fff70713 addi a4,a4,-1 -80014098: fec716e3 bne a4,a2,80014084 <__subtf3+0x1380> -8001409c: 1487cc63 blt a5,s0,800141f4 <__subtf3+0x14f0> -800140a0: 40878433 sub s0,a5,s0 -800140a4: 00140413 addi s0,s0,1 -800140a8: 02000713 li a4,32 -800140ac: 02e44533 div a0,s0,a4 -800140b0: 00000813 li a6,0 -800140b4: 00000793 li a5,0 -800140b8: 04a7ce63 blt a5,a0,80014114 <__subtf3+0x1410> -800140bc: 00050613 mv a2,a0 -800140c0: 00055463 bgez a0,800140c8 <__subtf3+0x13c4> -800140c4: 00000613 li a2,0 -800140c8: 01f47793 andi a5,s0,31 -800140cc: 00251693 slli a3,a0,0x2 -800140d0: 06079063 bnez a5,80014130 <__subtf3+0x142c> -800140d4: 00300613 li a2,3 -800140d8: 03010793 addi a5,sp,48 -800140dc: 00000713 li a4,0 -800140e0: 40a60633 sub a2,a2,a0 -800140e4: 00d785b3 add a1,a5,a3 -800140e8: 0005a583 lw a1,0(a1) +80013fd4: fec716e3 bne a4,a2,80013fc0 <__subtf3+0x1380> +80013fd8: 1487cc63 blt a5,s0,80014130 <__subtf3+0x14f0> +80013fdc: 40878433 sub s0,a5,s0 +80013fe0: 00140413 addi s0,s0,1 +80013fe4: 02000713 li a4,32 +80013fe8: 02e44533 div a0,s0,a4 +80013fec: 00000813 li a6,0 +80013ff0: 00000793 li a5,0 +80013ff4: 04a7ce63 blt a5,a0,80014050 <__subtf3+0x1410> +80013ff8: 00050613 mv a2,a0 +80013ffc: 00055463 bgez a0,80014004 <__subtf3+0x13c4> +80014000: 00000613 li a2,0 +80014004: 01f47793 andi a5,s0,31 +80014008: 00251693 slli a3,a0,0x2 +8001400c: 06079063 bnez a5,8001406c <__subtf3+0x142c> +80014010: 00300613 li a2,3 +80014014: 03010793 addi a5,sp,48 +80014018: 00000713 li a4,0 +8001401c: 40a60633 sub a2,a2,a0 +80014020: 00d785b3 add a1,a5,a3 +80014024: 0005a583 lw a1,0(a1) +80014028: 00170713 addi a4,a4,1 +8001402c: 00478793 addi a5,a5,4 +80014030: feb7ae23 sw a1,-4(a5) +80014034: fee656e3 bge a2,a4,80014020 <__subtf3+0x13e0> +80014038: 00400713 li a4,4 +8001403c: 40a70533 sub a0,a4,a0 +80014040: 00100713 li a4,1 +80014044: 08a05463 blez a0,800140cc <__subtf3+0x148c> +80014048: 00050713 mv a4,a0 +8001404c: 0800006f j 800140cc <__subtf3+0x148c> +80014050: 00279713 slli a4,a5,0x2 +80014054: 03010693 addi a3,sp,48 +80014058: 00e68733 add a4,a3,a4 +8001405c: 00072703 lw a4,0(a4) +80014060: 00178793 addi a5,a5,1 +80014064: 00e86833 or a6,a6,a4 +80014068: f8dff06f j 80013ff4 <__subtf3+0x13b4> +8001406c: 02000593 li a1,32 +80014070: 02b46433 rem s0,s0,a1 +80014074: 04010793 addi a5,sp,64 +80014078: 00261613 slli a2,a2,0x2 +8001407c: 00c78633 add a2,a5,a2 +80014080: ff062783 lw a5,-16(a2) +80014084: 00000713 li a4,0 +80014088: 408585b3 sub a1,a1,s0 +8001408c: 00b797b3 sll a5,a5,a1 +80014090: 00f86833 or a6,a6,a5 +80014094: 03010793 addi a5,sp,48 +80014098: 00d786b3 add a3,a5,a3 +8001409c: 00300793 li a5,3 +800140a0: 40a787b3 sub a5,a5,a0 +800140a4: 00468693 addi a3,a3,4 +800140a8: 02f74663 blt a4,a5,800140d4 <__subtf3+0x1494> +800140ac: 04010693 addi a3,sp,64 +800140b0: 00279793 slli a5,a5,0x2 +800140b4: 00f687b3 add a5,a3,a5 +800140b8: 03c12683 lw a3,60(sp) +800140bc: 00400713 li a4,4 +800140c0: 40a70733 sub a4,a4,a0 +800140c4: 0086d433 srl s0,a3,s0 +800140c8: fe87a823 sw s0,-16(a5) +800140cc: 00300693 li a3,3 +800140d0: 0440006f j 80014114 <__subtf3+0x14d4> +800140d4: 00271893 slli a7,a4,0x2 +800140d8: 03010613 addi a2,sp,48 +800140dc: 0006a303 lw t1,0(a3) +800140e0: 011608b3 add a7,a2,a7 +800140e4: ffc6a603 lw a2,-4(a3) +800140e8: 00b31333 sll t1,t1,a1 800140ec: 00170713 addi a4,a4,1 -800140f0: 00478793 addi a5,a5,4 -800140f4: feb7ae23 sw a1,-4(a5) -800140f8: fee656e3 bge a2,a4,800140e4 <__subtf3+0x13e0> -800140fc: 00400713 li a4,4 -80014100: 40a70533 sub a0,a4,a0 -80014104: 00100713 li a4,1 -80014108: 08a05463 blez a0,80014190 <__subtf3+0x148c> -8001410c: 00050713 mv a4,a0 -80014110: 0800006f j 80014190 <__subtf3+0x148c> -80014114: 00279713 slli a4,a5,0x2 -80014118: 03010693 addi a3,sp,48 -8001411c: 00e68733 add a4,a3,a4 -80014120: 00072703 lw a4,0(a4) -80014124: 00178793 addi a5,a5,1 -80014128: 00e86833 or a6,a6,a4 -8001412c: f8dff06f j 800140b8 <__subtf3+0x13b4> -80014130: 02000593 li a1,32 -80014134: 02b46433 rem s0,s0,a1 -80014138: 04010793 addi a5,sp,64 -8001413c: 00261613 slli a2,a2,0x2 -80014140: 00c78633 add a2,a5,a2 -80014144: ff062783 lw a5,-16(a2) -80014148: 00000713 li a4,0 -8001414c: 408585b3 sub a1,a1,s0 -80014150: 00b797b3 sll a5,a5,a1 -80014154: 00f86833 or a6,a6,a5 -80014158: 03010793 addi a5,sp,48 -8001415c: 00d786b3 add a3,a5,a3 -80014160: 00300793 li a5,3 -80014164: 40a787b3 sub a5,a5,a0 -80014168: 00468693 addi a3,a3,4 -8001416c: 02f74663 blt a4,a5,80014198 <__subtf3+0x1494> -80014170: 04010693 addi a3,sp,64 -80014174: 00279793 slli a5,a5,0x2 -80014178: 00f687b3 add a5,a3,a5 -8001417c: 03c12683 lw a3,60(sp) -80014180: 00400713 li a4,4 -80014184: 40a70733 sub a4,a4,a0 -80014188: 0086d433 srl s0,a3,s0 -8001418c: fe87a823 sw s0,-16(a5) -80014190: 00300693 li a3,3 -80014194: 0440006f j 800141d8 <__subtf3+0x14d4> -80014198: 00271893 slli a7,a4,0x2 -8001419c: 03010613 addi a2,sp,48 -800141a0: 0006a303 lw t1,0(a3) -800141a4: 011608b3 add a7,a2,a7 -800141a8: ffc6a603 lw a2,-4(a3) -800141ac: 00b31333 sll t1,t1,a1 -800141b0: 00170713 addi a4,a4,1 -800141b4: 00865633 srl a2,a2,s0 -800141b8: 00666633 or a2,a2,t1 -800141bc: 00c8a023 sw a2,0(a7) -800141c0: fa9ff06f j 80014168 <__subtf3+0x1464> -800141c4: 00271793 slli a5,a4,0x2 -800141c8: 03010613 addi a2,sp,48 -800141cc: 00f607b3 add a5,a2,a5 -800141d0: 0007a023 sw zero,0(a5) -800141d4: 00170713 addi a4,a4,1 -800141d8: fee6d6e3 bge a3,a4,800141c4 <__subtf3+0x14c0> -800141dc: 03012703 lw a4,48(sp) -800141e0: 010037b3 snez a5,a6 -800141e4: 00000413 li s0,0 -800141e8: 00f767b3 or a5,a4,a5 -800141ec: 02f12823 sw a5,48(sp) -800141f0: d45fe06f j 80012f34 <__subtf3+0x230> -800141f4: 40f40433 sub s0,s0,a5 -800141f8: 03c12783 lw a5,60(sp) -800141fc: fff80737 lui a4,0xfff80 -80014200: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> -80014204: 00e7f7b3 and a5,a5,a4 -80014208: 02f12e23 sw a5,60(sp) -8001420c: d29fe06f j 80012f34 <__subtf3+0x230> -80014210: 02012e23 sw zero,60(sp) -80014214: 02012c23 sw zero,56(sp) -80014218: 02012a23 sw zero,52(sp) -8001421c: 02012823 sw zero,48(sp) -80014220: d95fe06f j 80012fb4 <__subtf3+0x2b0> +800140f0: 00865633 srl a2,a2,s0 +800140f4: 00666633 or a2,a2,t1 +800140f8: 00c8a023 sw a2,0(a7) +800140fc: fa9ff06f j 800140a4 <__subtf3+0x1464> +80014100: 00271793 slli a5,a4,0x2 +80014104: 03010613 addi a2,sp,48 +80014108: 00f607b3 add a5,a2,a5 +8001410c: 0007a023 sw zero,0(a5) +80014110: 00170713 addi a4,a4,1 +80014114: fee6d6e3 bge a3,a4,80014100 <__subtf3+0x14c0> +80014118: 03012703 lw a4,48(sp) +8001411c: 010037b3 snez a5,a6 +80014120: 00000413 li s0,0 +80014124: 00f767b3 or a5,a4,a5 +80014128: 02f12823 sw a5,48(sp) +8001412c: d45fe06f j 80012e70 <__subtf3+0x230> +80014130: 40f40433 sub s0,s0,a5 +80014134: 03c12783 lw a5,60(sp) +80014138: fff80737 lui a4,0xfff80 +8001413c: fff70713 addi a4,a4,-1 # fff7ffff <__BSS_END__+0x7ff693c3> +80014140: 00e7f7b3 and a5,a5,a4 +80014144: 02f12e23 sw a5,60(sp) +80014148: d29fe06f j 80012e70 <__subtf3+0x230> +8001414c: 02012e23 sw zero,60(sp) +80014150: 02012c23 sw zero,56(sp) +80014154: 02012a23 sw zero,52(sp) +80014158: 02012823 sw zero,48(sp) +8001415c: d95fe06f j 80012ef0 <__subtf3+0x2b0> -80014224 <__fixtfsi>: -80014224: 00852783 lw a5,8(a0) -80014228: 00452703 lw a4,4(a0) -8001422c: 00c52683 lw a3,12(a0) -80014230: 00052603 lw a2,0(a0) -80014234: fe010113 addi sp,sp,-32 -80014238: 00e12223 sw a4,4(sp) -8001423c: 00f12423 sw a5,8(sp) -80014240: 00f12c23 sw a5,24(sp) -80014244: 00004737 lui a4,0x4 -80014248: 00169793 slli a5,a3,0x1 -8001424c: 0117d593 srli a1,a5,0x11 -80014250: 00c12023 sw a2,0(sp) -80014254: 00d12623 sw a3,12(sp) -80014258: 00c12823 sw a2,16(sp) -8001425c: ffe70793 addi a5,a4,-2 # 3ffe <_start-0x7fffc002> -80014260: 00000513 li a0,0 -80014264: 00b7de63 bge a5,a1,80014280 <__fixtfsi+0x5c> -80014268: 01d70793 addi a5,a4,29 -8001426c: 01f6d813 srli a6,a3,0x1f -80014270: 00b7dc63 bge a5,a1,80014288 <__fixtfsi+0x64> -80014274: 80000537 lui a0,0x80000 -80014278: fff54513 not a0,a0 -8001427c: 00a80533 add a0,a6,a0 -80014280: 02010113 addi sp,sp,32 -80014284: 00008067 ret -80014288: 01069693 slli a3,a3,0x10 -8001428c: 000107b7 lui a5,0x10 -80014290: 0106d693 srli a3,a3,0x10 -80014294: 00f6e6b3 or a3,a3,a5 -80014298: 06f70793 addi a5,a4,111 -8001429c: 40b787b3 sub a5,a5,a1 -800142a0: 4057d713 srai a4,a5,0x5 -800142a4: 00d12e23 sw a3,28(sp) -800142a8: 01f7f793 andi a5,a5,31 -800142ac: 04078863 beqz a5,800142fc <__fixtfsi+0xd8> -800142b0: 02000513 li a0,32 -800142b4: ffe70893 addi a7,a4,-2 -800142b8: 40f50533 sub a0,a0,a5 -800142bc: 00271713 slli a4,a4,0x2 -800142c0: 02010e13 addi t3,sp,32 -800142c4: 00a69533 sll a0,a3,a0 -800142c8: 00000313 li t1,0 -800142cc: 00000593 li a1,0 -800142d0: 0018b893 seqz a7,a7 -800142d4: 00ee0733 add a4,t3,a4 -800142d8: 0515c463 blt a1,a7,80014320 <__fixtfsi+0xfc> -800142dc: 00030463 beqz t1,800142e4 <__fixtfsi+0xc0> -800142e0: 00c12823 sw a2,16(sp) -800142e4: 00259593 slli a1,a1,0x2 -800142e8: 02010713 addi a4,sp,32 -800142ec: 00b705b3 add a1,a4,a1 -800142f0: 00f6d6b3 srl a3,a3,a5 -800142f4: fed5a823 sw a3,-16(a1) -800142f8: 0180006f j 80014310 <__fixtfsi+0xec> -800142fc: 02010793 addi a5,sp,32 -80014300: 00271713 slli a4,a4,0x2 -80014304: 00e78733 add a4,a5,a4 -80014308: ff072783 lw a5,-16(a4) -8001430c: 00f12823 sw a5,16(sp) -80014310: 01012503 lw a0,16(sp) -80014314: f60806e3 beqz a6,80014280 <__fixtfsi+0x5c> -80014318: 40a00533 neg a0,a0 -8001431c: f65ff06f j 80014280 <__fixtfsi+0x5c> -80014320: ff072603 lw a2,-16(a4) -80014324: 00100313 li t1,1 -80014328: 00100593 li a1,1 -8001432c: 00f65633 srl a2,a2,a5 -80014330: 00a66633 or a2,a2,a0 -80014334: fa5ff06f j 800142d8 <__fixtfsi+0xb4> +80014160 <__fixtfsi>: +80014160: 00852783 lw a5,8(a0) +80014164: 00452703 lw a4,4(a0) +80014168: 00c52683 lw a3,12(a0) +8001416c: 00052603 lw a2,0(a0) +80014170: fe010113 addi sp,sp,-32 +80014174: 00e12223 sw a4,4(sp) +80014178: 00f12423 sw a5,8(sp) +8001417c: 00f12c23 sw a5,24(sp) +80014180: 00004737 lui a4,0x4 +80014184: 00169793 slli a5,a3,0x1 +80014188: 0117d593 srli a1,a5,0x11 +8001418c: 00c12023 sw a2,0(sp) +80014190: 00d12623 sw a3,12(sp) +80014194: 00c12823 sw a2,16(sp) +80014198: ffe70793 addi a5,a4,-2 # 3ffe <_start-0x7fffc002> +8001419c: 00000513 li a0,0 +800141a0: 00b7de63 bge a5,a1,800141bc <__fixtfsi+0x5c> +800141a4: 01d70793 addi a5,a4,29 +800141a8: 01f6d813 srli a6,a3,0x1f +800141ac: 00b7dc63 bge a5,a1,800141c4 <__fixtfsi+0x64> +800141b0: 80000537 lui a0,0x80000 +800141b4: fff54513 not a0,a0 +800141b8: 00a80533 add a0,a6,a0 +800141bc: 02010113 addi sp,sp,32 +800141c0: 00008067 ret +800141c4: 01069693 slli a3,a3,0x10 +800141c8: 000107b7 lui a5,0x10 +800141cc: 0106d693 srli a3,a3,0x10 +800141d0: 00f6e6b3 or a3,a3,a5 +800141d4: 06f70793 addi a5,a4,111 +800141d8: 40b787b3 sub a5,a5,a1 +800141dc: 4057d713 srai a4,a5,0x5 +800141e0: 00d12e23 sw a3,28(sp) +800141e4: 01f7f793 andi a5,a5,31 +800141e8: 04078863 beqz a5,80014238 <__fixtfsi+0xd8> +800141ec: 02000513 li a0,32 +800141f0: ffe70893 addi a7,a4,-2 +800141f4: 40f50533 sub a0,a0,a5 +800141f8: 00271713 slli a4,a4,0x2 +800141fc: 02010e13 addi t3,sp,32 +80014200: 00a69533 sll a0,a3,a0 +80014204: 00000313 li t1,0 +80014208: 00000593 li a1,0 +8001420c: 0018b893 seqz a7,a7 +80014210: 00ee0733 add a4,t3,a4 +80014214: 0515c463 blt a1,a7,8001425c <__fixtfsi+0xfc> +80014218: 00030463 beqz t1,80014220 <__fixtfsi+0xc0> +8001421c: 00c12823 sw a2,16(sp) +80014220: 00259593 slli a1,a1,0x2 +80014224: 02010713 addi a4,sp,32 +80014228: 00b705b3 add a1,a4,a1 +8001422c: 00f6d6b3 srl a3,a3,a5 +80014230: fed5a823 sw a3,-16(a1) +80014234: 0180006f j 8001424c <__fixtfsi+0xec> +80014238: 02010793 addi a5,sp,32 +8001423c: 00271713 slli a4,a4,0x2 +80014240: 00e78733 add a4,a5,a4 +80014244: ff072783 lw a5,-16(a4) +80014248: 00f12823 sw a5,16(sp) +8001424c: 01012503 lw a0,16(sp) +80014250: f60806e3 beqz a6,800141bc <__fixtfsi+0x5c> +80014254: 40a00533 neg a0,a0 +80014258: f65ff06f j 800141bc <__fixtfsi+0x5c> +8001425c: ff072603 lw a2,-16(a4) +80014260: 00100313 li t1,1 +80014264: 00100593 li a1,1 +80014268: 00f65633 srl a2,a2,a5 +8001426c: 00a66633 or a2,a2,a0 +80014270: fa5ff06f j 80014214 <__fixtfsi+0xb4> -80014338 <__floatsitf>: -80014338: fd010113 addi sp,sp,-48 -8001433c: 02912223 sw s1,36(sp) -80014340: 02112623 sw ra,44(sp) -80014344: 02812423 sw s0,40(sp) -80014348: 03212023 sw s2,32(sp) -8001434c: 00050493 mv s1,a0 -80014350: 12058063 beqz a1,80014470 <__floatsitf+0x138> -80014354: 41f5d793 srai a5,a1,0x1f -80014358: 00b7c433 xor s0,a5,a1 -8001435c: 40f40433 sub s0,s0,a5 -80014360: 00040513 mv a0,s0 -80014364: 01f5d913 srli s2,a1,0x1f -80014368: 660000ef jal ra,800149c8 <__clzsi2> -8001436c: 00004737 lui a4,0x4 -80014370: 01e70713 addi a4,a4,30 # 401e <_start-0x7fffbfe2> -80014374: 05150793 addi a5,a0,81 # 80000051 <__BSS_END__+0xfffe9415> -80014378: 40a705b3 sub a1,a4,a0 -8001437c: 00812823 sw s0,16(sp) -80014380: 4057d713 srai a4,a5,0x5 -80014384: 00012a23 sw zero,20(sp) -80014388: 00012c23 sw zero,24(sp) -8001438c: 00012e23 sw zero,28(sp) -80014390: 01f7f793 andi a5,a5,31 -80014394: 02078c63 beqz a5,800143cc <__floatsitf+0x94> -80014398: 00200693 li a3,2 -8001439c: 0cd71663 bne a4,a3,80014468 <__floatsitf+0x130> -800143a0: 02000693 li a3,32 -800143a4: 40f686b3 sub a3,a3,a5 -800143a8: 00d456b3 srl a3,s0,a3 -800143ac: 00d12e23 sw a3,28(sp) -800143b0: fff70693 addi a3,a4,-1 -800143b4: 02010613 addi a2,sp,32 -800143b8: 00271713 slli a4,a4,0x2 -800143bc: 00e60733 add a4,a2,a4 -800143c0: 00f417b3 sll a5,s0,a5 -800143c4: fef72823 sw a5,-16(a4) -800143c8: 0340006f j 800143fc <__floatsitf+0xc4> -800143cc: 00300793 li a5,3 -800143d0: 40e787b3 sub a5,a5,a4 -800143d4: 02010693 addi a3,sp,32 -800143d8: 00279793 slli a5,a5,0x2 -800143dc: 00f687b3 add a5,a3,a5 -800143e0: ff07a783 lw a5,-16(a5) # fff0 <_start-0x7fff0010> -800143e4: 00200693 li a3,2 -800143e8: 00f12e23 sw a5,28(sp) -800143ec: 00200793 li a5,2 -800143f0: 00f71663 bne a4,a5,800143fc <__floatsitf+0xc4> -800143f4: 00812c23 sw s0,24(sp) -800143f8: 00100693 li a3,1 -800143fc: fff00793 li a5,-1 -80014400: 00269713 slli a4,a3,0x2 -80014404: 01010613 addi a2,sp,16 -80014408: 00e60733 add a4,a2,a4 -8001440c: 00072023 sw zero,0(a4) -80014410: fff68693 addi a3,a3,-1 -80014414: fef696e3 bne a3,a5,80014400 <__floatsitf+0xc8> -80014418: 01c12783 lw a5,28(sp) -8001441c: 02c12083 lw ra,44(sp) -80014420: 02812403 lw s0,40(sp) -80014424: 00f11623 sh a5,12(sp) -80014428: 00f91793 slli a5,s2,0xf -8001442c: 00b7e5b3 or a1,a5,a1 -80014430: 01012783 lw a5,16(sp) -80014434: 00b11723 sh a1,14(sp) -80014438: 02012903 lw s2,32(sp) -8001443c: 00f4a023 sw a5,0(s1) -80014440: 01412783 lw a5,20(sp) -80014444: 00048513 mv a0,s1 -80014448: 00f4a223 sw a5,4(s1) -8001444c: 01812783 lw a5,24(sp) -80014450: 00f4a423 sw a5,8(s1) -80014454: 00c12783 lw a5,12(sp) -80014458: 00f4a623 sw a5,12(s1) -8001445c: 02412483 lw s1,36(sp) -80014460: 03010113 addi sp,sp,48 -80014464: 00008067 ret -80014468: 00300713 li a4,3 -8001446c: f45ff06f j 800143b0 <__floatsitf+0x78> -80014470: 00012e23 sw zero,28(sp) -80014474: 00012c23 sw zero,24(sp) -80014478: 00012a23 sw zero,20(sp) -8001447c: 00012823 sw zero,16(sp) -80014480: 00000913 li s2,0 -80014484: f95ff06f j 80014418 <__floatsitf+0xe0> +80014274 <__floatsitf>: +80014274: fd010113 addi sp,sp,-48 +80014278: 02912223 sw s1,36(sp) +8001427c: 02112623 sw ra,44(sp) +80014280: 02812423 sw s0,40(sp) +80014284: 03212023 sw s2,32(sp) +80014288: 00050493 mv s1,a0 +8001428c: 12058063 beqz a1,800143ac <__floatsitf+0x138> +80014290: 41f5d793 srai a5,a1,0x1f +80014294: 00b7c433 xor s0,a5,a1 +80014298: 40f40433 sub s0,s0,a5 +8001429c: 00040513 mv a0,s0 +800142a0: 01f5d913 srli s2,a1,0x1f +800142a4: 660000ef jal ra,80014904 <__clzsi2> +800142a8: 00004737 lui a4,0x4 +800142ac: 01e70713 addi a4,a4,30 # 401e <_start-0x7fffbfe2> +800142b0: 05150793 addi a5,a0,81 # 80000051 <__BSS_END__+0xfffe9415> +800142b4: 40a705b3 sub a1,a4,a0 +800142b8: 00812823 sw s0,16(sp) +800142bc: 4057d713 srai a4,a5,0x5 +800142c0: 00012a23 sw zero,20(sp) +800142c4: 00012c23 sw zero,24(sp) +800142c8: 00012e23 sw zero,28(sp) +800142cc: 01f7f793 andi a5,a5,31 +800142d0: 02078c63 beqz a5,80014308 <__floatsitf+0x94> +800142d4: 00200693 li a3,2 +800142d8: 0cd71663 bne a4,a3,800143a4 <__floatsitf+0x130> +800142dc: 02000693 li a3,32 +800142e0: 40f686b3 sub a3,a3,a5 +800142e4: 00d456b3 srl a3,s0,a3 +800142e8: 00d12e23 sw a3,28(sp) +800142ec: fff70693 addi a3,a4,-1 +800142f0: 02010613 addi a2,sp,32 +800142f4: 00271713 slli a4,a4,0x2 +800142f8: 00e60733 add a4,a2,a4 +800142fc: 00f417b3 sll a5,s0,a5 +80014300: fef72823 sw a5,-16(a4) +80014304: 0340006f j 80014338 <__floatsitf+0xc4> +80014308: 00300793 li a5,3 +8001430c: 40e787b3 sub a5,a5,a4 +80014310: 02010693 addi a3,sp,32 +80014314: 00279793 slli a5,a5,0x2 +80014318: 00f687b3 add a5,a3,a5 +8001431c: ff07a783 lw a5,-16(a5) # fff0 <_start-0x7fff0010> +80014320: 00200693 li a3,2 +80014324: 00f12e23 sw a5,28(sp) +80014328: 00200793 li a5,2 +8001432c: 00f71663 bne a4,a5,80014338 <__floatsitf+0xc4> +80014330: 00812c23 sw s0,24(sp) +80014334: 00100693 li a3,1 +80014338: fff00793 li a5,-1 +8001433c: 00269713 slli a4,a3,0x2 +80014340: 01010613 addi a2,sp,16 +80014344: 00e60733 add a4,a2,a4 +80014348: 00072023 sw zero,0(a4) +8001434c: fff68693 addi a3,a3,-1 +80014350: fef696e3 bne a3,a5,8001433c <__floatsitf+0xc8> +80014354: 01c12783 lw a5,28(sp) +80014358: 02c12083 lw ra,44(sp) +8001435c: 02812403 lw s0,40(sp) +80014360: 00f11623 sh a5,12(sp) +80014364: 00f91793 slli a5,s2,0xf +80014368: 00b7e5b3 or a1,a5,a1 +8001436c: 01012783 lw a5,16(sp) +80014370: 00b11723 sh a1,14(sp) +80014374: 02012903 lw s2,32(sp) +80014378: 00f4a023 sw a5,0(s1) +8001437c: 01412783 lw a5,20(sp) +80014380: 00048513 mv a0,s1 +80014384: 00f4a223 sw a5,4(s1) +80014388: 01812783 lw a5,24(sp) +8001438c: 00f4a423 sw a5,8(s1) +80014390: 00c12783 lw a5,12(sp) +80014394: 00f4a623 sw a5,12(s1) +80014398: 02412483 lw s1,36(sp) +8001439c: 03010113 addi sp,sp,48 +800143a0: 00008067 ret +800143a4: 00300713 li a4,3 +800143a8: f45ff06f j 800142ec <__floatsitf+0x78> +800143ac: 00012e23 sw zero,28(sp) +800143b0: 00012c23 sw zero,24(sp) +800143b4: 00012a23 sw zero,20(sp) +800143b8: 00012823 sw zero,16(sp) +800143bc: 00000913 li s2,0 +800143c0: f95ff06f j 80014354 <__floatsitf+0xe0> -80014488 <__extenddftf2>: -80014488: 01465793 srli a5,a2,0x14 -8001448c: 00c61713 slli a4,a2,0xc -80014490: 7ff7f793 andi a5,a5,2047 -80014494: fd010113 addi sp,sp,-48 -80014498: 00c75713 srli a4,a4,0xc -8001449c: 00178693 addi a3,a5,1 -800144a0: 02812423 sw s0,40(sp) -800144a4: 02912223 sw s1,36(sp) -800144a8: 03212023 sw s2,32(sp) -800144ac: 02112623 sw ra,44(sp) -800144b0: 00b12823 sw a1,16(sp) -800144b4: 00e12a23 sw a4,20(sp) -800144b8: 00012e23 sw zero,28(sp) -800144bc: 00012c23 sw zero,24(sp) -800144c0: 7fe6f693 andi a3,a3,2046 -800144c4: 00050913 mv s2,a0 -800144c8: 00058413 mv s0,a1 -800144cc: 01f65493 srli s1,a2,0x1f -800144d0: 08068263 beqz a3,80014554 <__extenddftf2+0xcc> -800144d4: 000046b7 lui a3,0x4 -800144d8: c0068693 addi a3,a3,-1024 # 3c00 <_start-0x7fffc400> -800144dc: 00d787b3 add a5,a5,a3 -800144e0: 0045d513 srli a0,a1,0x4 -800144e4: 00475693 srli a3,a4,0x4 -800144e8: 01c71713 slli a4,a4,0x1c -800144ec: 00a76733 or a4,a4,a0 -800144f0: 01c59413 slli s0,a1,0x1c -800144f4: 00d12e23 sw a3,28(sp) -800144f8: 00e12c23 sw a4,24(sp) -800144fc: 00812a23 sw s0,20(sp) -80014500: 00012823 sw zero,16(sp) -80014504: 00f49493 slli s1,s1,0xf -80014508: 00f4e7b3 or a5,s1,a5 -8001450c: 00f11723 sh a5,14(sp) -80014510: 01012783 lw a5,16(sp) -80014514: 01c12703 lw a4,28(sp) -80014518: 02c12083 lw ra,44(sp) -8001451c: 00f92023 sw a5,0(s2) -80014520: 01412783 lw a5,20(sp) -80014524: 00e11623 sh a4,12(sp) -80014528: 02812403 lw s0,40(sp) -8001452c: 00f92223 sw a5,4(s2) -80014530: 01812783 lw a5,24(sp) -80014534: 02412483 lw s1,36(sp) -80014538: 00090513 mv a0,s2 -8001453c: 00f92423 sw a5,8(s2) -80014540: 00c12783 lw a5,12(sp) -80014544: 00f92623 sw a5,12(s2) -80014548: 02012903 lw s2,32(sp) -8001454c: 03010113 addi sp,sp,48 -80014550: 00008067 ret -80014554: 00b76533 or a0,a4,a1 -80014558: 0e079463 bnez a5,80014640 <__extenddftf2+0x1b8> -8001455c: fa0504e3 beqz a0,80014504 <__extenddftf2+0x7c> -80014560: 04070c63 beqz a4,800145b8 <__extenddftf2+0x130> -80014564: 00070513 mv a0,a4 -80014568: 460000ef jal ra,800149c8 <__clzsi2> -8001456c: 03150593 addi a1,a0,49 -80014570: 4055d713 srai a4,a1,0x5 -80014574: 01f5f593 andi a1,a1,31 -80014578: 04058663 beqz a1,800145c4 <__extenddftf2+0x13c> -8001457c: ffc00693 li a3,-4 -80014580: 02d706b3 mul a3,a4,a3 -80014584: 01010313 addi t1,sp,16 -80014588: 02000813 li a6,32 -8001458c: 00271613 slli a2,a4,0x2 -80014590: 40b80833 sub a6,a6,a1 -80014594: 00c68693 addi a3,a3,12 -80014598: 00d306b3 add a3,t1,a3 -8001459c: 08d31063 bne t1,a3,8001461c <__extenddftf2+0x194> -800145a0: 02010793 addi a5,sp,32 -800145a4: 00c78633 add a2,a5,a2 -800145a8: 00b415b3 sll a1,s0,a1 -800145ac: fff70713 addi a4,a4,-1 -800145b0: feb62823 sw a1,-16(a2) -800145b4: 03c0006f j 800145f0 <__extenddftf2+0x168> -800145b8: 410000ef jal ra,800149c8 <__clzsi2> -800145bc: 02050513 addi a0,a0,32 -800145c0: fadff06f j 8001456c <__extenddftf2+0xe4> -800145c4: ffc00613 li a2,-4 -800145c8: 02c70633 mul a2,a4,a2 -800145cc: 01c10793 addi a5,sp,28 -800145d0: 00300693 li a3,3 -800145d4: 00c785b3 add a1,a5,a2 -800145d8: 0005a583 lw a1,0(a1) -800145dc: fff68693 addi a3,a3,-1 -800145e0: ffc78793 addi a5,a5,-4 -800145e4: 00b7a223 sw a1,4(a5) -800145e8: fee6d6e3 bge a3,a4,800145d4 <__extenddftf2+0x14c> -800145ec: fff70713 addi a4,a4,-1 -800145f0: fff00693 li a3,-1 -800145f4: 00271793 slli a5,a4,0x2 -800145f8: 01010613 addi a2,sp,16 -800145fc: 00f607b3 add a5,a2,a5 -80014600: 0007a023 sw zero,0(a5) -80014604: fff70713 addi a4,a4,-1 -80014608: fed716e3 bne a4,a3,800145f4 <__extenddftf2+0x16c> -8001460c: 000047b7 lui a5,0x4 -80014610: c0c78793 addi a5,a5,-1012 # 3c0c <_start-0x7fffc3f4> -80014614: 40a787b3 sub a5,a5,a0 -80014618: eedff06f j 80014504 <__extenddftf2+0x7c> -8001461c: ffc6a783 lw a5,-4(a3) -80014620: 0006a883 lw a7,0(a3) -80014624: 00c68e33 add t3,a3,a2 -80014628: 0107d7b3 srl a5,a5,a6 -8001462c: 00b898b3 sll a7,a7,a1 -80014630: 0117e7b3 or a5,a5,a7 -80014634: 00fe2023 sw a5,0(t3) -80014638: ffc68693 addi a3,a3,-4 -8001463c: f61ff06f j 8001459c <__extenddftf2+0x114> -80014640: 000087b7 lui a5,0x8 -80014644: 02050863 beqz a0,80014674 <__extenddftf2+0x1ec> -80014648: 01c71793 slli a5,a4,0x1c -8001464c: 0045d693 srli a3,a1,0x4 -80014650: 00d7e7b3 or a5,a5,a3 -80014654: 00f12c23 sw a5,24(sp) -80014658: 00475713 srli a4,a4,0x4 -8001465c: 000087b7 lui a5,0x8 -80014660: 01c59413 slli s0,a1,0x1c -80014664: 00f76733 or a4,a4,a5 -80014668: 00812a23 sw s0,20(sp) -8001466c: 00012823 sw zero,16(sp) -80014670: 00e12e23 sw a4,28(sp) -80014674: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> -80014678: e8dff06f j 80014504 <__extenddftf2+0x7c> +800143c4 <__extenddftf2>: +800143c4: 01465793 srli a5,a2,0x14 +800143c8: 00c61713 slli a4,a2,0xc +800143cc: 7ff7f793 andi a5,a5,2047 +800143d0: fd010113 addi sp,sp,-48 +800143d4: 00c75713 srli a4,a4,0xc +800143d8: 00178693 addi a3,a5,1 +800143dc: 02812423 sw s0,40(sp) +800143e0: 02912223 sw s1,36(sp) +800143e4: 03212023 sw s2,32(sp) +800143e8: 02112623 sw ra,44(sp) +800143ec: 00b12823 sw a1,16(sp) +800143f0: 00e12a23 sw a4,20(sp) +800143f4: 00012e23 sw zero,28(sp) +800143f8: 00012c23 sw zero,24(sp) +800143fc: 7fe6f693 andi a3,a3,2046 +80014400: 00050913 mv s2,a0 +80014404: 00058413 mv s0,a1 +80014408: 01f65493 srli s1,a2,0x1f +8001440c: 08068263 beqz a3,80014490 <__extenddftf2+0xcc> +80014410: 000046b7 lui a3,0x4 +80014414: c0068693 addi a3,a3,-1024 # 3c00 <_start-0x7fffc400> +80014418: 00d787b3 add a5,a5,a3 +8001441c: 0045d513 srli a0,a1,0x4 +80014420: 00475693 srli a3,a4,0x4 +80014424: 01c71713 slli a4,a4,0x1c +80014428: 00a76733 or a4,a4,a0 +8001442c: 01c59413 slli s0,a1,0x1c +80014430: 00d12e23 sw a3,28(sp) +80014434: 00e12c23 sw a4,24(sp) +80014438: 00812a23 sw s0,20(sp) +8001443c: 00012823 sw zero,16(sp) +80014440: 00f49493 slli s1,s1,0xf +80014444: 00f4e7b3 or a5,s1,a5 +80014448: 00f11723 sh a5,14(sp) +8001444c: 01012783 lw a5,16(sp) +80014450: 01c12703 lw a4,28(sp) +80014454: 02c12083 lw ra,44(sp) +80014458: 00f92023 sw a5,0(s2) +8001445c: 01412783 lw a5,20(sp) +80014460: 00e11623 sh a4,12(sp) +80014464: 02812403 lw s0,40(sp) +80014468: 00f92223 sw a5,4(s2) +8001446c: 01812783 lw a5,24(sp) +80014470: 02412483 lw s1,36(sp) +80014474: 00090513 mv a0,s2 +80014478: 00f92423 sw a5,8(s2) +8001447c: 00c12783 lw a5,12(sp) +80014480: 00f92623 sw a5,12(s2) +80014484: 02012903 lw s2,32(sp) +80014488: 03010113 addi sp,sp,48 +8001448c: 00008067 ret +80014490: 00b76533 or a0,a4,a1 +80014494: 0e079463 bnez a5,8001457c <__extenddftf2+0x1b8> +80014498: fa0504e3 beqz a0,80014440 <__extenddftf2+0x7c> +8001449c: 04070c63 beqz a4,800144f4 <__extenddftf2+0x130> +800144a0: 00070513 mv a0,a4 +800144a4: 460000ef jal ra,80014904 <__clzsi2> +800144a8: 03150593 addi a1,a0,49 +800144ac: 4055d713 srai a4,a1,0x5 +800144b0: 01f5f593 andi a1,a1,31 +800144b4: 04058663 beqz a1,80014500 <__extenddftf2+0x13c> +800144b8: ffc00693 li a3,-4 +800144bc: 02d706b3 mul a3,a4,a3 +800144c0: 01010313 addi t1,sp,16 +800144c4: 02000813 li a6,32 +800144c8: 00271613 slli a2,a4,0x2 +800144cc: 40b80833 sub a6,a6,a1 +800144d0: 00c68693 addi a3,a3,12 +800144d4: 00d306b3 add a3,t1,a3 +800144d8: 08d31063 bne t1,a3,80014558 <__extenddftf2+0x194> +800144dc: 02010793 addi a5,sp,32 +800144e0: 00c78633 add a2,a5,a2 +800144e4: 00b415b3 sll a1,s0,a1 +800144e8: fff70713 addi a4,a4,-1 +800144ec: feb62823 sw a1,-16(a2) +800144f0: 03c0006f j 8001452c <__extenddftf2+0x168> +800144f4: 410000ef jal ra,80014904 <__clzsi2> +800144f8: 02050513 addi a0,a0,32 +800144fc: fadff06f j 800144a8 <__extenddftf2+0xe4> +80014500: ffc00613 li a2,-4 +80014504: 02c70633 mul a2,a4,a2 +80014508: 01c10793 addi a5,sp,28 +8001450c: 00300693 li a3,3 +80014510: 00c785b3 add a1,a5,a2 +80014514: 0005a583 lw a1,0(a1) +80014518: fff68693 addi a3,a3,-1 +8001451c: ffc78793 addi a5,a5,-4 +80014520: 00b7a223 sw a1,4(a5) +80014524: fee6d6e3 bge a3,a4,80014510 <__extenddftf2+0x14c> +80014528: fff70713 addi a4,a4,-1 +8001452c: fff00693 li a3,-1 +80014530: 00271793 slli a5,a4,0x2 +80014534: 01010613 addi a2,sp,16 +80014538: 00f607b3 add a5,a2,a5 +8001453c: 0007a023 sw zero,0(a5) +80014540: fff70713 addi a4,a4,-1 +80014544: fed716e3 bne a4,a3,80014530 <__extenddftf2+0x16c> +80014548: 000047b7 lui a5,0x4 +8001454c: c0c78793 addi a5,a5,-1012 # 3c0c <_start-0x7fffc3f4> +80014550: 40a787b3 sub a5,a5,a0 +80014554: eedff06f j 80014440 <__extenddftf2+0x7c> +80014558: ffc6a783 lw a5,-4(a3) +8001455c: 0006a883 lw a7,0(a3) +80014560: 00c68e33 add t3,a3,a2 +80014564: 0107d7b3 srl a5,a5,a6 +80014568: 00b898b3 sll a7,a7,a1 +8001456c: 0117e7b3 or a5,a5,a7 +80014570: 00fe2023 sw a5,0(t3) +80014574: ffc68693 addi a3,a3,-4 +80014578: f61ff06f j 800144d8 <__extenddftf2+0x114> +8001457c: 000087b7 lui a5,0x8 +80014580: 02050863 beqz a0,800145b0 <__extenddftf2+0x1ec> +80014584: 01c71793 slli a5,a4,0x1c +80014588: 0045d693 srli a3,a1,0x4 +8001458c: 00d7e7b3 or a5,a5,a3 +80014590: 00f12c23 sw a5,24(sp) +80014594: 00475713 srli a4,a4,0x4 +80014598: 000087b7 lui a5,0x8 +8001459c: 01c59413 slli s0,a1,0x1c +800145a0: 00f76733 or a4,a4,a5 +800145a4: 00812a23 sw s0,20(sp) +800145a8: 00012823 sw zero,16(sp) +800145ac: 00e12e23 sw a4,28(sp) +800145b0: fff78793 addi a5,a5,-1 # 7fff <_start-0x7fff8001> +800145b4: e8dff06f j 80014440 <__extenddftf2+0x7c> -8001467c <__trunctfdf2>: -8001467c: 00c52583 lw a1,12(a0) -80014680: 00852783 lw a5,8(a0) -80014684: 00452703 lw a4,4(a0) -80014688: fe010113 addi sp,sp,-32 -8001468c: 00052683 lw a3,0(a0) -80014690: 00f12423 sw a5,8(sp) -80014694: 00f12c23 sw a5,24(sp) -80014698: 01059793 slli a5,a1,0x10 -8001469c: 00e12223 sw a4,4(sp) -800146a0: 00e12a23 sw a4,20(sp) -800146a4: 0107d793 srli a5,a5,0x10 -800146a8: 00159713 slli a4,a1,0x1 -800146ac: 00b12623 sw a1,12(sp) -800146b0: 00d12023 sw a3,0(sp) -800146b4: 00d12823 sw a3,16(sp) -800146b8: 00f12e23 sw a5,28(sp) -800146bc: 01175713 srli a4,a4,0x11 -800146c0: 01f5d593 srli a1,a1,0x1f -800146c4: 01010813 addi a6,sp,16 -800146c8: 01c10613 addi a2,sp,28 -800146cc: 00062783 lw a5,0(a2) -800146d0: ffc62683 lw a3,-4(a2) -800146d4: ffc60613 addi a2,a2,-4 -800146d8: 00379793 slli a5,a5,0x3 -800146dc: 01d6d693 srli a3,a3,0x1d -800146e0: 00d7e7b3 or a5,a5,a3 -800146e4: 00f62223 sw a5,4(a2) -800146e8: fec812e3 bne a6,a2,800146cc <__trunctfdf2+0x50> -800146ec: 01012683 lw a3,16(sp) -800146f0: 00170793 addi a5,a4,1 -800146f4: 00369513 slli a0,a3,0x3 -800146f8: 000086b7 lui a3,0x8 -800146fc: ffe68693 addi a3,a3,-2 # 7ffe <_start-0x7fff8002> -80014700: 00a12823 sw a0,16(sp) -80014704: 00d7f7b3 and a5,a5,a3 -80014708: 1c078463 beqz a5,800148d0 <__trunctfdf2+0x254> -8001470c: ffffc7b7 lui a5,0xffffc -80014710: 40078793 addi a5,a5,1024 # ffffc400 <__BSS_END__+0x7ffe57c4> -80014714: 00f70733 add a4,a4,a5 -80014718: 7fe00793 li a5,2046 -8001471c: 20e7c663 blt a5,a4,80014928 <__trunctfdf2+0x2ac> -80014720: 06e05863 blez a4,80014790 <__trunctfdf2+0x114> -80014724: 01812803 lw a6,24(sp) -80014728: 01c12603 lw a2,28(sp) -8001472c: 01412783 lw a5,20(sp) -80014730: 01c85693 srli a3,a6,0x1c -80014734: 00461613 slli a2,a2,0x4 -80014738: 00d66633 or a2,a2,a3 -8001473c: 00479693 slli a3,a5,0x4 -80014740: 00a6e6b3 or a3,a3,a0 -80014744: 01c7d793 srli a5,a5,0x1c -80014748: 00481813 slli a6,a6,0x4 -8001474c: 00d036b3 snez a3,a3 -80014750: 0107e7b3 or a5,a5,a6 -80014754: 00f6e6b3 or a3,a3,a5 -80014758: 00c12a23 sw a2,20(sp) -8001475c: 00d12823 sw a3,16(sp) -80014760: 01012683 lw a3,16(sp) -80014764: 01412783 lw a5,20(sp) -80014768: 0076f613 andi a2,a3,7 -8001476c: 1c060463 beqz a2,80014934 <__trunctfdf2+0x2b8> -80014770: 00f6f613 andi a2,a3,15 -80014774: 00400513 li a0,4 -80014778: 1aa60e63 beq a2,a0,80014934 <__trunctfdf2+0x2b8> -8001477c: 00468613 addi a2,a3,4 -80014780: 00d636b3 sltu a3,a2,a3 -80014784: 00d787b3 add a5,a5,a3 -80014788: 00060693 mv a3,a2 -8001478c: 1a80006f j 80014934 <__trunctfdf2+0x2b8> -80014790: fcc00793 li a5,-52 -80014794: 00f75c63 bge a4,a5,800147ac <__trunctfdf2+0x130> -80014798: 00012a23 sw zero,20(sp) -8001479c: 00100793 li a5,1 -800147a0: 00f12823 sw a5,16(sp) -800147a4: 00000713 li a4,0 -800147a8: fb9ff06f j 80014760 <__trunctfdf2+0xe4> -800147ac: 01c12783 lw a5,28(sp) -800147b0: 00080f37 lui t5,0x80 -800147b4: 03d00693 li a3,61 -800147b8: 00ff6f33 or t5,t5,a5 -800147bc: 40e686b3 sub a3,a3,a4 -800147c0: 01e12e23 sw t5,28(sp) -800147c4: 4056de93 srai t4,a3,0x5 -800147c8: 00080713 mv a4,a6 -800147cc: 00000793 li a5,0 -800147d0: 00000e13 li t3,0 -800147d4: 00072503 lw a0,0(a4) -800147d8: 00178793 addi a5,a5,1 -800147dc: 00470713 addi a4,a4,4 -800147e0: 00ae6e33 or t3,t3,a0 -800147e4: fefe98e3 bne t4,a5,800147d4 <__trunctfdf2+0x158> -800147e8: 01f6f713 andi a4,a3,31 -800147ec: 002e9693 slli a3,t4,0x2 -800147f0: 04071063 bnez a4,80014830 <__trunctfdf2+0x1b4> -800147f4: 00300713 li a4,3 -800147f8: 00000793 li a5,0 -800147fc: 41d70733 sub a4,a4,t4 -80014800: 00d60533 add a0,a2,a3 -80014804: 00052503 lw a0,0(a0) -80014808: 00178793 addi a5,a5,1 -8001480c: 00460613 addi a2,a2,4 -80014810: fea62e23 sw a0,-4(a2) -80014814: fef756e3 bge a4,a5,80014800 <__trunctfdf2+0x184> -80014818: 00400713 li a4,4 -8001481c: 41d70733 sub a4,a4,t4 -80014820: 00100793 li a5,1 -80014824: 04e05e63 blez a4,80014880 <__trunctfdf2+0x204> -80014828: 00070793 mv a5,a4 -8001482c: 0540006f j 80014880 <__trunctfdf2+0x204> -80014830: 02010793 addi a5,sp,32 -80014834: 00d787b3 add a5,a5,a3 -80014838: ff07a783 lw a5,-16(a5) -8001483c: 02000313 li t1,32 -80014840: 40e30333 sub t1,t1,a4 -80014844: 006797b3 sll a5,a5,t1 -80014848: 00d80633 add a2,a6,a3 -8001484c: 00300693 li a3,3 -80014850: 00fe6e33 or t3,t3,a5 -80014854: 00000893 li a7,0 -80014858: 41d686b3 sub a3,a3,t4 -8001485c: 00460613 addi a2,a2,4 -80014860: 04d8c463 blt a7,a3,800148a8 <__trunctfdf2+0x22c> -80014864: 00269693 slli a3,a3,0x2 -80014868: 02010613 addi a2,sp,32 -8001486c: 00400793 li a5,4 -80014870: 00d606b3 add a3,a2,a3 -80014874: 00ef5733 srl a4,t5,a4 -80014878: 41d787b3 sub a5,a5,t4 -8001487c: fee6a823 sw a4,-16(a3) -80014880: 00400693 li a3,4 -80014884: 00279713 slli a4,a5,0x2 -80014888: 00e80733 add a4,a6,a4 -8001488c: 00072023 sw zero,0(a4) -80014890: 00178793 addi a5,a5,1 -80014894: fed798e3 bne a5,a3,80014884 <__trunctfdf2+0x208> -80014898: 01012703 lw a4,16(sp) -8001489c: 01c037b3 snez a5,t3 -800148a0: 00f767b3 or a5,a4,a5 -800148a4: efdff06f j 800147a0 <__trunctfdf2+0x124> -800148a8: ffc62503 lw a0,-4(a2) -800148ac: 00062f83 lw t6,0(a2) -800148b0: 00289793 slli a5,a7,0x2 -800148b4: 00e55533 srl a0,a0,a4 -800148b8: 006f9fb3 sll t6,t6,t1 -800148bc: 00f807b3 add a5,a6,a5 -800148c0: 01f56533 or a0,a0,t6 -800148c4: 00a7a023 sw a0,0(a5) -800148c8: 00188893 addi a7,a7,1 -800148cc: f91ff06f j 8001485c <__trunctfdf2+0x1e0> -800148d0: 01412603 lw a2,20(sp) -800148d4: 01812783 lw a5,24(sp) -800148d8: 01c12803 lw a6,28(sp) -800148dc: 00f666b3 or a3,a2,a5 -800148e0: 0106e6b3 or a3,a3,a6 -800148e4: 00a6e6b3 or a3,a3,a0 -800148e8: 00071863 bnez a4,800148f8 <__trunctfdf2+0x27c> -800148ec: 00d036b3 snez a3,a3 +800145b8 <__trunctfdf2>: +800145b8: 00c52583 lw a1,12(a0) +800145bc: 00852783 lw a5,8(a0) +800145c0: 00452703 lw a4,4(a0) +800145c4: fe010113 addi sp,sp,-32 +800145c8: 00052683 lw a3,0(a0) +800145cc: 00f12423 sw a5,8(sp) +800145d0: 00f12c23 sw a5,24(sp) +800145d4: 01059793 slli a5,a1,0x10 +800145d8: 00e12223 sw a4,4(sp) +800145dc: 00e12a23 sw a4,20(sp) +800145e0: 0107d793 srli a5,a5,0x10 +800145e4: 00159713 slli a4,a1,0x1 +800145e8: 00b12623 sw a1,12(sp) +800145ec: 00d12023 sw a3,0(sp) +800145f0: 00d12823 sw a3,16(sp) +800145f4: 00f12e23 sw a5,28(sp) +800145f8: 01175713 srli a4,a4,0x11 +800145fc: 01f5d593 srli a1,a1,0x1f +80014600: 01010813 addi a6,sp,16 +80014604: 01c10613 addi a2,sp,28 +80014608: 00062783 lw a5,0(a2) +8001460c: ffc62683 lw a3,-4(a2) +80014610: ffc60613 addi a2,a2,-4 +80014614: 00379793 slli a5,a5,0x3 +80014618: 01d6d693 srli a3,a3,0x1d +8001461c: 00d7e7b3 or a5,a5,a3 +80014620: 00f62223 sw a5,4(a2) +80014624: fec812e3 bne a6,a2,80014608 <__trunctfdf2+0x50> +80014628: 01012683 lw a3,16(sp) +8001462c: 00170793 addi a5,a4,1 +80014630: 00369513 slli a0,a3,0x3 +80014634: 000086b7 lui a3,0x8 +80014638: ffe68693 addi a3,a3,-2 # 7ffe <_start-0x7fff8002> +8001463c: 00a12823 sw a0,16(sp) +80014640: 00d7f7b3 and a5,a5,a3 +80014644: 1c078463 beqz a5,8001480c <__trunctfdf2+0x254> +80014648: ffffc7b7 lui a5,0xffffc +8001464c: 40078793 addi a5,a5,1024 # ffffc400 <__BSS_END__+0x7ffe57c4> +80014650: 00f70733 add a4,a4,a5 +80014654: 7fe00793 li a5,2046 +80014658: 20e7c663 blt a5,a4,80014864 <__trunctfdf2+0x2ac> +8001465c: 06e05863 blez a4,800146cc <__trunctfdf2+0x114> +80014660: 01812803 lw a6,24(sp) +80014664: 01c12603 lw a2,28(sp) +80014668: 01412783 lw a5,20(sp) +8001466c: 01c85693 srli a3,a6,0x1c +80014670: 00461613 slli a2,a2,0x4 +80014674: 00d66633 or a2,a2,a3 +80014678: 00479693 slli a3,a5,0x4 +8001467c: 00a6e6b3 or a3,a3,a0 +80014680: 01c7d793 srli a5,a5,0x1c +80014684: 00481813 slli a6,a6,0x4 +80014688: 00d036b3 snez a3,a3 +8001468c: 0107e7b3 or a5,a5,a6 +80014690: 00f6e6b3 or a3,a3,a5 +80014694: 00c12a23 sw a2,20(sp) +80014698: 00d12823 sw a3,16(sp) +8001469c: 01012683 lw a3,16(sp) +800146a0: 01412783 lw a5,20(sp) +800146a4: 0076f613 andi a2,a3,7 +800146a8: 1c060463 beqz a2,80014870 <__trunctfdf2+0x2b8> +800146ac: 00f6f613 andi a2,a3,15 +800146b0: 00400513 li a0,4 +800146b4: 1aa60e63 beq a2,a0,80014870 <__trunctfdf2+0x2b8> +800146b8: 00468613 addi a2,a3,4 +800146bc: 00d636b3 sltu a3,a2,a3 +800146c0: 00d787b3 add a5,a5,a3 +800146c4: 00060693 mv a3,a2 +800146c8: 1a80006f j 80014870 <__trunctfdf2+0x2b8> +800146cc: fcc00793 li a5,-52 +800146d0: 00f75c63 bge a4,a5,800146e8 <__trunctfdf2+0x130> +800146d4: 00012a23 sw zero,20(sp) +800146d8: 00100793 li a5,1 +800146dc: 00f12823 sw a5,16(sp) +800146e0: 00000713 li a4,0 +800146e4: fb9ff06f j 8001469c <__trunctfdf2+0xe4> +800146e8: 01c12783 lw a5,28(sp) +800146ec: 00080f37 lui t5,0x80 +800146f0: 03d00693 li a3,61 +800146f4: 00ff6f33 or t5,t5,a5 +800146f8: 40e686b3 sub a3,a3,a4 +800146fc: 01e12e23 sw t5,28(sp) +80014700: 4056de93 srai t4,a3,0x5 +80014704: 00080713 mv a4,a6 +80014708: 00000793 li a5,0 +8001470c: 00000e13 li t3,0 +80014710: 00072503 lw a0,0(a4) +80014714: 00178793 addi a5,a5,1 +80014718: 00470713 addi a4,a4,4 +8001471c: 00ae6e33 or t3,t3,a0 +80014720: fefe98e3 bne t4,a5,80014710 <__trunctfdf2+0x158> +80014724: 01f6f713 andi a4,a3,31 +80014728: 002e9693 slli a3,t4,0x2 +8001472c: 04071063 bnez a4,8001476c <__trunctfdf2+0x1b4> +80014730: 00300713 li a4,3 +80014734: 00000793 li a5,0 +80014738: 41d70733 sub a4,a4,t4 +8001473c: 00d60533 add a0,a2,a3 +80014740: 00052503 lw a0,0(a0) +80014744: 00178793 addi a5,a5,1 +80014748: 00460613 addi a2,a2,4 +8001474c: fea62e23 sw a0,-4(a2) +80014750: fef756e3 bge a4,a5,8001473c <__trunctfdf2+0x184> +80014754: 00400713 li a4,4 +80014758: 41d70733 sub a4,a4,t4 +8001475c: 00100793 li a5,1 +80014760: 04e05e63 blez a4,800147bc <__trunctfdf2+0x204> +80014764: 00070793 mv a5,a4 +80014768: 0540006f j 800147bc <__trunctfdf2+0x204> +8001476c: 02010793 addi a5,sp,32 +80014770: 00d787b3 add a5,a5,a3 +80014774: ff07a783 lw a5,-16(a5) +80014778: 02000313 li t1,32 +8001477c: 40e30333 sub t1,t1,a4 +80014780: 006797b3 sll a5,a5,t1 +80014784: 00d80633 add a2,a6,a3 +80014788: 00300693 li a3,3 +8001478c: 00fe6e33 or t3,t3,a5 +80014790: 00000893 li a7,0 +80014794: 41d686b3 sub a3,a3,t4 +80014798: 00460613 addi a2,a2,4 +8001479c: 04d8c463 blt a7,a3,800147e4 <__trunctfdf2+0x22c> +800147a0: 00269693 slli a3,a3,0x2 +800147a4: 02010613 addi a2,sp,32 +800147a8: 00400793 li a5,4 +800147ac: 00d606b3 add a3,a2,a3 +800147b0: 00ef5733 srl a4,t5,a4 +800147b4: 41d787b3 sub a5,a5,t4 +800147b8: fee6a823 sw a4,-16(a3) +800147bc: 00400693 li a3,4 +800147c0: 00279713 slli a4,a5,0x2 +800147c4: 00e80733 add a4,a6,a4 +800147c8: 00072023 sw zero,0(a4) +800147cc: 00178793 addi a5,a5,1 +800147d0: fed798e3 bne a5,a3,800147c0 <__trunctfdf2+0x208> +800147d4: 01012703 lw a4,16(sp) +800147d8: 01c037b3 snez a5,t3 +800147dc: 00f767b3 or a5,a4,a5 +800147e0: efdff06f j 800146dc <__trunctfdf2+0x124> +800147e4: ffc62503 lw a0,-4(a2) +800147e8: 00062f83 lw t6,0(a2) +800147ec: 00289793 slli a5,a7,0x2 +800147f0: 00e55533 srl a0,a0,a4 +800147f4: 006f9fb3 sll t6,t6,t1 +800147f8: 00f807b3 add a5,a6,a5 +800147fc: 01f56533 or a0,a0,t6 +80014800: 00a7a023 sw a0,0(a5) +80014804: 00188893 addi a7,a7,1 +80014808: f91ff06f j 80014798 <__trunctfdf2+0x1e0> +8001480c: 01412603 lw a2,20(sp) +80014810: 01812783 lw a5,24(sp) +80014814: 01c12803 lw a6,28(sp) +80014818: 00f666b3 or a3,a2,a5 +8001481c: 0106e6b3 or a3,a3,a6 +80014820: 00a6e6b3 or a3,a3,a0 +80014824: 00071863 bnez a4,80014834 <__trunctfdf2+0x27c> +80014828: 00d036b3 snez a3,a3 +8001482c: 00000793 li a5,0 +80014830: e75ff06f j 800146a4 <__trunctfdf2+0xec> +80014834: 0a068e63 beqz a3,800148f0 <__trunctfdf2+0x338> +80014838: 01c65693 srli a3,a2,0x1c +8001483c: 00481813 slli a6,a6,0x4 +80014840: 00479613 slli a2,a5,0x4 +80014844: 01c7d793 srli a5,a5,0x1c +80014848: 00400737 lui a4,0x400 +8001484c: 00c6e6b3 or a3,a3,a2 +80014850: 0107e7b3 or a5,a5,a6 +80014854: 00e7e7b3 or a5,a5,a4 +80014858: ff86f693 andi a3,a3,-8 +8001485c: 7ff00713 li a4,2047 +80014860: e45ff06f j 800146a4 <__trunctfdf2+0xec> +80014864: 00000793 li a5,0 +80014868: 00000693 li a3,0 +8001486c: 7ff00713 li a4,2047 +80014870: 00879613 slli a2,a5,0x8 +80014874: 00065e63 bgez a2,80014890 <__trunctfdf2+0x2d8> +80014878: 00170713 addi a4,a4,1 # 400001 <_start-0x7fbfffff> +8001487c: 7ff00613 li a2,2047 +80014880: 06c70c63 beq a4,a2,800148f8 <__trunctfdf2+0x340> +80014884: ff800637 lui a2,0xff800 +80014888: fff60613 addi a2,a2,-1 # ff7fffff <__BSS_END__+0x7f7e93c3> +8001488c: 00c7f7b3 and a5,a5,a2 +80014890: 01d79613 slli a2,a5,0x1d +80014894: 0036d693 srli a3,a3,0x3 +80014898: 00d666b3 or a3,a2,a3 +8001489c: 7ff00613 li a2,2047 +800148a0: 0037d793 srli a5,a5,0x3 +800148a4: 00c71e63 bne a4,a2,800148c0 <__trunctfdf2+0x308> +800148a8: 00f6e6b3 or a3,a3,a5 +800148ac: 00000793 li a5,0 +800148b0: 00068863 beqz a3,800148c0 <__trunctfdf2+0x308> +800148b4: 000807b7 lui a5,0x80 +800148b8: 00000693 li a3,0 +800148bc: 00000593 li a1,0 +800148c0: 01471713 slli a4,a4,0x14 +800148c4: 7ff00637 lui a2,0x7ff00 +800148c8: 00c79793 slli a5,a5,0xc +800148cc: 00c77733 and a4,a4,a2 +800148d0: 00c7d793 srli a5,a5,0xc +800148d4: 01f59593 slli a1,a1,0x1f +800148d8: 00f767b3 or a5,a4,a5 +800148dc: 00b7e733 or a4,a5,a1 +800148e0: 00068513 mv a0,a3 +800148e4: 00070593 mv a1,a4 +800148e8: 02010113 addi sp,sp,32 +800148ec: 00008067 ret 800148f0: 00000793 li a5,0 -800148f4: e75ff06f j 80014768 <__trunctfdf2+0xec> -800148f8: 0a068e63 beqz a3,800149b4 <__trunctfdf2+0x338> -800148fc: 01c65693 srli a3,a2,0x1c -80014900: 00481813 slli a6,a6,0x4 -80014904: 00479613 slli a2,a5,0x4 -80014908: 01c7d793 srli a5,a5,0x1c -8001490c: 00400737 lui a4,0x400 -80014910: 00c6e6b3 or a3,a3,a2 -80014914: 0107e7b3 or a5,a5,a6 -80014918: 00e7e7b3 or a5,a5,a4 -8001491c: ff86f693 andi a3,a3,-8 -80014920: 7ff00713 li a4,2047 -80014924: e45ff06f j 80014768 <__trunctfdf2+0xec> -80014928: 00000793 li a5,0 -8001492c: 00000693 li a3,0 -80014930: 7ff00713 li a4,2047 -80014934: 00879613 slli a2,a5,0x8 -80014938: 00065e63 bgez a2,80014954 <__trunctfdf2+0x2d8> -8001493c: 00170713 addi a4,a4,1 # 400001 <_start-0x7fbfffff> -80014940: 7ff00613 li a2,2047 -80014944: 06c70c63 beq a4,a2,800149bc <__trunctfdf2+0x340> -80014948: ff800637 lui a2,0xff800 -8001494c: fff60613 addi a2,a2,-1 # ff7fffff <__BSS_END__+0x7f7e93c3> -80014950: 00c7f7b3 and a5,a5,a2 -80014954: 01d79613 slli a2,a5,0x1d -80014958: 0036d693 srli a3,a3,0x3 -8001495c: 00d666b3 or a3,a2,a3 -80014960: 7ff00613 li a2,2047 -80014964: 0037d793 srli a5,a5,0x3 -80014968: 00c71e63 bne a4,a2,80014984 <__trunctfdf2+0x308> -8001496c: 00f6e6b3 or a3,a3,a5 -80014970: 00000793 li a5,0 -80014974: 00068863 beqz a3,80014984 <__trunctfdf2+0x308> -80014978: 000807b7 lui a5,0x80 -8001497c: 00000693 li a3,0 -80014980: 00000593 li a1,0 -80014984: 01471713 slli a4,a4,0x14 -80014988: 7ff00637 lui a2,0x7ff00 -8001498c: 00c79793 slli a5,a5,0xc -80014990: 00c77733 and a4,a4,a2 -80014994: 00c7d793 srli a5,a5,0xc -80014998: 01f59593 slli a1,a1,0x1f -8001499c: 00f767b3 or a5,a4,a5 -800149a0: 00b7e733 or a4,a5,a1 -800149a4: 00068513 mv a0,a3 -800149a8: 00070593 mv a1,a4 -800149ac: 02010113 addi sp,sp,32 -800149b0: 00008067 ret -800149b4: 00000793 li a5,0 -800149b8: f79ff06f j 80014930 <__trunctfdf2+0x2b4> -800149bc: 00000793 li a5,0 -800149c0: 00000693 li a3,0 -800149c4: f91ff06f j 80014954 <__trunctfdf2+0x2d8> +800148f4: f79ff06f j 8001486c <__trunctfdf2+0x2b4> +800148f8: 00000793 li a5,0 +800148fc: 00000693 li a3,0 +80014900: f91ff06f j 80014890 <__trunctfdf2+0x2d8> -800149c8 <__clzsi2>: -800149c8: 000107b7 lui a5,0x10 -800149cc: 02f57a63 bgeu a0,a5,80014a00 <__clzsi2+0x38> -800149d0: 0ff00793 li a5,255 -800149d4: 00a7b7b3 sltu a5,a5,a0 -800149d8: 00379793 slli a5,a5,0x3 -800149dc: 80016737 lui a4,0x80016 -800149e0: 02000693 li a3,32 -800149e4: 40f686b3 sub a3,a3,a5 -800149e8: 00f55533 srl a0,a0,a5 -800149ec: 84c70793 addi a5,a4,-1972 # 8001584c <__BSS_END__+0xffffec10> -800149f0: 00a78533 add a0,a5,a0 -800149f4: 00054503 lbu a0,0(a0) -800149f8: 40a68533 sub a0,a3,a0 -800149fc: 00008067 ret -80014a00: 01000737 lui a4,0x1000 -80014a04: 01000793 li a5,16 -80014a08: fce56ae3 bltu a0,a4,800149dc <__clzsi2+0x14> -80014a0c: 01800793 li a5,24 -80014a10: fcdff06f j 800149dc <__clzsi2+0x14> +80014904 <__clzsi2>: +80014904: 000107b7 lui a5,0x10 +80014908: 02f57a63 bgeu a0,a5,8001493c <__clzsi2+0x38> +8001490c: 0ff00793 li a5,255 +80014910: 00a7b7b3 sltu a5,a5,a0 +80014914: 00379793 slli a5,a5,0x3 +80014918: 80015737 lui a4,0x80015 +8001491c: 02000693 li a3,32 +80014920: 40f686b3 sub a3,a3,a5 +80014924: 00f55533 srl a0,a0,a5 +80014928: 77470793 addi a5,a4,1908 # 80015774 <__BSS_END__+0xffffeb38> +8001492c: 00a78533 add a0,a5,a0 +80014930: 00054503 lbu a0,0(a0) +80014934: 40a68533 sub a0,a3,a0 +80014938: 00008067 ret +8001493c: 01000737 lui a4,0x1000 +80014940: 01000793 li a5,16 +80014944: fce56ae3 bltu a0,a4,80014918 <__clzsi2+0x14> +80014948: 01800793 li a5,24 +8001494c: fcdff06f j 80014918 <__clzsi2+0x14> Disassembly of section .rodata: -80014a18 : -80014a18: 0030 addi a2,sp,8 +80014950 : +80014950: 0030 addi a2,sp,8 +80014952: 0000 unimp +80014954: 0031 c.nop 12 +80014956: 0000 unimp +80014958: 0032 c.slli zero,0xc +8001495a: 0000 unimp +8001495c: 00000033 add zero,zero,zero +80014960: 0034 addi a3,sp,8 +80014962: 0000 unimp +80014964: 0035 c.nop 13 +80014966: 0000 unimp +80014968: 0036 c.slli zero,0xd +8001496a: 0000 unimp +8001496c: 00000037 lui zero,0x0 +80014970: 0038 addi a4,sp,8 +80014972: 0000 unimp +80014974: 0039 c.nop 14 +80014976: 0000 unimp +80014978: 0061 c.nop 24 +8001497a: 0000 unimp +8001497c: 0062 c.slli zero,0x18 +8001497e: 0000 unimp +80014980: 00000063 beqz zero,80014980 <__clzsi2+0x7c> +80014984: 0064 addi s1,sp,12 +80014986: 0000 unimp +80014988: 0065 c.nop 25 +8001498a: 0000 unimp +8001498c: 0066 c.slli zero,0x19 +8001498e: 0000 unimp +80014990: 5245 li tp,-15 +80014992: 4f52 lw t5,20(sp) +80014994: 3a52 fld fs4,304(sp) +80014996: 5f20 lw s0,120(a4) +80014998: 6e75 lui t3,0x1d +8001499a: 696c flw fa1,84(a0) +8001499c: 6b6e flw fs6,216(sp) +8001499e: 6e20 flw fs0,88(a2) +800149a0: 7920746f jal s0,8001c132 <__BSS_END__+0x54f6> +800149a4: 7465 lui s0,0xffff9 +800149a6: 6920 flw fs0,80(a0) +800149a8: 706d c.lui zero,0xffffb +800149aa: 656c flw fa1,76(a0) +800149ac: 656d lui a0,0x1b +800149ae: 746e flw fs0,248(sp) +800149b0: 6465 lui s0,0x19 +800149b2: 000a c.slli zero,0x2 +800149b4: 5245 li tp,-15 +800149b6: 4f52 lw t5,20(sp) +800149b8: 3a52 fld fs4,304(sp) +800149ba: 5f20 lw s0,120(a4) +800149bc: 696c flw fa1,84(a0) +800149be: 6b6e flw fs6,216(sp) +800149c0: 6e20 flw fs0,88(a2) +800149c2: 7920746f jal s0,8001c154 <__BSS_END__+0x5518> +800149c6: 7465 lui s0,0xffff9 +800149c8: 6920 flw fs0,80(a0) +800149ca: 706d c.lui zero,0xffffb +800149cc: 656c flw fa1,76(a0) +800149ce: 656d lui a0,0x1b +800149d0: 746e flw fs0,248(sp) +800149d2: 6465 lui s0,0x19 +800149d4: 000a c.slli zero,0x2 +800149d6: 0000 unimp +800149d8: 0030 addi a2,sp,8 +800149da: 0000 unimp +800149dc: 0031 c.nop 12 +800149de: 0000 unimp +800149e0: 0032 c.slli zero,0xc +800149e2: 0000 unimp +800149e4: 00000033 add zero,zero,zero +800149e8: 0034 addi a3,sp,8 +800149ea: 0000 unimp +800149ec: 0035 c.nop 13 +800149ee: 0000 unimp +800149f0: 0036 c.slli zero,0xd +800149f2: 0000 unimp +800149f4: 00000037 lui zero,0x0 +800149f8: 0038 addi a4,sp,8 +800149fa: 0000 unimp +800149fc: 0039 c.nop 14 +800149fe: 0000 unimp +80014a00: 0061 c.nop 24 +80014a02: 0000 unimp +80014a04: 0062 c.slli zero,0x18 +80014a06: 0000 unimp +80014a08: 00000063 beqz zero,80014a08 <__clzsi2+0x104> +80014a0c: 0064 addi s1,sp,12 +80014a0e: 0000 unimp +80014a10: 0065 c.nop 25 +80014a12: 0000 unimp +80014a14: 0066 c.slli zero,0x19 +80014a16: 0000 unimp +80014a18: 000a c.slli zero,0x2 80014a1a: 0000 unimp -80014a1c: 0031 c.nop 12 -80014a1e: 0000 unimp -80014a20: 0032 c.slli zero,0xc +80014a1c: 6425 lui s0,0x9 +80014a1e: 000a c.slli zero,0x2 +80014a20: 0030 addi a2,sp,8 80014a22: 0000 unimp -80014a24: 00000033 add zero,zero,zero -80014a28: 0034 addi a3,sp,8 +80014a24: 0031 c.nop 12 +80014a26: 0000 unimp +80014a28: 0032 c.slli zero,0xc 80014a2a: 0000 unimp -80014a2c: 0035 c.nop 13 -80014a2e: 0000 unimp -80014a30: 0036 c.slli zero,0xd +80014a2c: 00000033 add zero,zero,zero +80014a30: 0034 addi a3,sp,8 80014a32: 0000 unimp -80014a34: 00000037 lui zero,0x0 -80014a38: 0038 addi a4,sp,8 +80014a34: 0035 c.nop 13 +80014a36: 0000 unimp +80014a38: 0036 c.slli zero,0xd 80014a3a: 0000 unimp -80014a3c: 0039 c.nop 14 -80014a3e: 0000 unimp -80014a40: 0061 c.nop 24 +80014a3c: 00000037 lui zero,0x0 +80014a40: 0038 addi a4,sp,8 80014a42: 0000 unimp -80014a44: 0062 c.slli zero,0x18 +80014a44: 0039 c.nop 14 80014a46: 0000 unimp -80014a48: 00000063 beqz zero,80014a48 <__clzsi2+0x80> -80014a4c: 0064 addi s1,sp,12 +80014a48: 0061 c.nop 24 +80014a4a: 0000 unimp +80014a4c: 0062 c.slli zero,0x18 80014a4e: 0000 unimp -80014a50: 0065 c.nop 25 -80014a52: 0000 unimp -80014a54: 0066 c.slli zero,0x19 +80014a50: 00000063 beqz zero,80014a50 <__clzsi2+0x14c> +80014a54: 0064 addi s1,sp,12 80014a56: 0000 unimp -80014a58: 5245 li tp,-15 -80014a5a: 4f52 lw t5,20(sp) -80014a5c: 3a52 fld fs4,304(sp) -80014a5e: 5f20 lw s0,120(a4) -80014a60: 6e75 lui t3,0x1d -80014a62: 696c flw fa1,84(a0) -80014a64: 6b6e flw fs6,216(sp) -80014a66: 6e20 flw fs0,88(a2) -80014a68: 7920746f jal s0,8001c1fa <__BSS_END__+0x55be> -80014a6c: 7465 lui s0,0xffff9 -80014a6e: 6920 flw fs0,80(a0) -80014a70: 706d c.lui zero,0xffffb -80014a72: 656c flw fa1,76(a0) -80014a74: 656d lui a0,0x1b -80014a76: 746e flw fs0,248(sp) -80014a78: 6465 lui s0,0x19 -80014a7a: 000a c.slli zero,0x2 -80014a7c: 5245 li tp,-15 -80014a7e: 4f52 lw t5,20(sp) -80014a80: 3a52 fld fs4,304(sp) -80014a82: 5f20 lw s0,120(a4) -80014a84: 696c flw fa1,84(a0) -80014a86: 6b6e flw fs6,216(sp) -80014a88: 6e20 flw fs0,88(a2) -80014a8a: 7920746f jal s0,8001c21c <__BSS_END__+0x55e0> -80014a8e: 7465 lui s0,0xffff9 -80014a90: 6920 flw fs0,80(a0) -80014a92: 706d c.lui zero,0xffffb -80014a94: 656c flw fa1,76(a0) -80014a96: 656d lui a0,0x1b -80014a98: 746e flw fs0,248(sp) -80014a9a: 6465 lui s0,0x19 -80014a9c: 000a c.slli zero,0x2 +80014a58: 0065 c.nop 25 +80014a5a: 0000 unimp +80014a5c: 0066 c.slli zero,0x19 +80014a5e: 0000 unimp +80014a60: 6574 flw fa3,76(a0) +80014a62: 6e697473 csrrci s0,0x6e6,18 +80014a66: 6d745f67 0x6d745f67 +80014a6a: 00000a63 beqz zero,80014a7e <__clzsi2+0x17a> +80014a6e: 0000 unimp +80014a70: 000a c.slli zero,0x2 +80014a72: 0000 unimp +80014a74: 6574 flw fa3,76(a0) +80014a76: 645f7473 csrrci s0,0x645,30 +80014a7a: 7669 lui a2,0xffffa +80014a7c: 7265 lui tp,0xffff9 +80014a7e: 636e6567 0x636e6567 +80014a82: 0a65 addi s4,s4,25 +80014a84: 0000 unimp +80014a86: 0000 unimp +80014a88: 6574 flw fa3,76(a0) +80014a8a: 735f7473 csrrci s0,0x735,30 +80014a8e: 6170 flw fa2,68(a0) +80014a90: 000a6e77 0xa6e77 +80014a94: 0030 addi a2,sp,8 +80014a96: 0000 unimp +80014a98: 0031 c.nop 12 +80014a9a: 0000 unimp +80014a9c: 0032 c.slli zero,0xc 80014a9e: 0000 unimp -80014aa0: 0030 addi a2,sp,8 -80014aa2: 0000 unimp -80014aa4: 0031 c.nop 12 +80014aa0: 00000033 add zero,zero,zero +80014aa4: 0034 addi a3,sp,8 80014aa6: 0000 unimp -80014aa8: 0032 c.slli zero,0xc +80014aa8: 0035 c.nop 13 80014aaa: 0000 unimp -80014aac: 00000033 add zero,zero,zero -80014ab0: 0034 addi a3,sp,8 -80014ab2: 0000 unimp -80014ab4: 0035 c.nop 13 +80014aac: 0036 c.slli zero,0xd +80014aae: 0000 unimp +80014ab0: 00000037 lui zero,0x0 +80014ab4: 0038 addi a4,sp,8 80014ab6: 0000 unimp -80014ab8: 0036 c.slli zero,0xd +80014ab8: 0039 c.nop 14 80014aba: 0000 unimp -80014abc: 00000037 lui zero,0x0 -80014ac0: 0038 addi a4,sp,8 +80014abc: 0061 c.nop 24 +80014abe: 0000 unimp +80014ac0: 0062 c.slli zero,0x18 80014ac2: 0000 unimp -80014ac4: 0039 c.nop 14 -80014ac6: 0000 unimp -80014ac8: 0061 c.nop 24 +80014ac4: 00000063 beqz zero,80014ac4 <__clzsi2+0x1c0> +80014ac8: 0064 addi s1,sp,12 80014aca: 0000 unimp -80014acc: 0062 c.slli zero,0x18 +80014acc: 0065 c.nop 25 80014ace: 0000 unimp -80014ad0: 00000063 beqz zero,80014ad0 <__clzsi2+0x108> -80014ad4: 0064 addi s1,sp,12 -80014ad6: 0000 unimp -80014ad8: 0065 c.nop 25 -80014ada: 0000 unimp -80014adc: 0066 c.slli zero,0x19 -80014ade: 0000 unimp -80014ae0: 000a c.slli zero,0x2 -80014ae2: 0000 unimp -80014ae4: 6425 lui s0,0x9 -80014ae6: 000a c.slli zero,0x2 -80014ae8: 0030 addi a2,sp,8 -80014aea: 0000 unimp -80014aec: 0031 c.nop 12 -80014aee: 0000 unimp -80014af0: 0032 c.slli zero,0xc -80014af2: 0000 unimp -80014af4: 00000033 add zero,zero,zero -80014af8: 0034 addi a3,sp,8 -80014afa: 0000 unimp -80014afc: 0035 c.nop 13 +80014ad0: 0066 c.slli zero,0x19 +80014ad2: 0000 unimp +80014ad4: 654c flw fa1,12(a0) +80014ad6: 2774 fld fa3,200(a4) +80014ad8: 74732073 csrs 0x747,t1 +80014adc: 7261 lui tp,0xffff8 +80014ade: 2e74 fld fa3,216(a2) +80014ae0: 2e2e fld ft8,200(sp) +80014ae2: 2820 fld fs0,80(s0) +80014ae4: 6854 flw fa3,20(s0) +80014ae6: 7369 lui t1,0xffffa +80014ae8: 6d20 flw fs0,88(a0) +80014aea: 6769 lui a4,0x1a +80014aec: 7468 flw fa0,108(s0) +80014aee: 7420 flw fs0,104(s0) +80014af0: 6b61 lui s6,0x18 +80014af2: 2065 jal 80014b9a <__clzsi2+0x296> +80014af4: 2061 jal 80014b7c <__clzsi2+0x278> +80014af6: 6c696877 0x6c696877 +80014afa: 2965 jal 80014fb2 +80014afc: 000a c.slli zero,0x2 80014afe: 0000 unimp -80014b00: 0036 c.slli zero,0xd -80014b02: 0000 unimp -80014b04: 00000037 lui zero,0x0 -80014b08: 0038 addi a4,sp,8 -80014b0a: 0000 unimp -80014b0c: 0039 c.nop 14 -80014b0e: 0000 unimp -80014b10: 0061 c.nop 24 -80014b12: 0000 unimp -80014b14: 0062 c.slli zero,0x18 +80014b00: 6156 flw ft2,84(sp) +80014b02: 756c flw fa1,108(a0) +80014b04: 3a65 jal 800144bc <__extenddftf2+0xf8> +80014b06: 0020 addi s0,sp,8 +80014b08: 706d6953 0x706d6953 +80014b0c: 656c flw fa1,76(a0) +80014b0e: 4d20 lw s0,88(a0) +80014b10: 6961 lui s2,0x18 +80014b12: 0a6e slli s4,s4,0x1b +80014b14: 0000 unimp 80014b16: 0000 unimp -80014b18: 00000063 beqz zero,80014b18 <__clzsi2+0x150> -80014b1c: 0064 addi s1,sp,12 -80014b1e: 0000 unimp -80014b20: 0065 c.nop 25 -80014b22: 0000 unimp -80014b24: 0066 c.slli zero,0x19 -80014b26: 0000 unimp -80014b28: 6574 flw fa3,76(a0) -80014b2a: 6e697473 csrrci s0,0x6e6,18 -80014b2e: 6d745f67 0x6d745f67 -80014b32: 00000a63 beqz zero,80014b46 <__clzsi2+0x17e> -80014b36: 0000 unimp -80014b38: 000a c.slli zero,0x2 +80014b18: 6574 flw fa3,76(a0) +80014b1a: 645f7473 csrrci s0,0x645,30 +80014b1e: 7669 lui a2,0xffffa +80014b20: 7265 lui tp,0xffff9 +80014b22: 636e6567 0x636e6567 +80014b26: 0a65 addi s4,s4,25 +80014b28: 0000 unimp +80014b2a: 0000 unimp +80014b2c: 6574 flw fa3,76(a0) +80014b2e: 775f7473 csrrci s0,0x775,30 +80014b32: 77617073 csrci 0x776,2 +80014b36: 0a6e slli s4,s4,0x1b +80014b38: 0000 unimp 80014b3a: 0000 unimp -80014b3c: 6574 flw fa3,76(a0) -80014b3e: 645f7473 csrrci s0,0x645,30 -80014b42: 7669 lui a2,0xffffa -80014b44: 7265 lui tp,0xffff9 -80014b46: 636e6567 0x636e6567 -80014b4a: 0a65 addi s4,s4,25 -80014b4c: 0000 unimp -80014b4e: 0000 unimp -80014b50: 6574 flw fa3,76(a0) -80014b52: 735f7473 csrrci s0,0x735,30 -80014b56: 6170 flw fa2,68(a0) -80014b58: 000a6e77 0xa6e77 -80014b5c: 0030 addi a2,sp,8 -80014b5e: 0000 unimp -80014b60: 0031 c.nop 12 -80014b62: 0000 unimp -80014b64: 0032 c.slli zero,0xc -80014b66: 0000 unimp -80014b68: 00000033 add zero,zero,zero -80014b6c: 0034 addi a3,sp,8 -80014b6e: 0000 unimp -80014b70: 0035 c.nop 13 -80014b72: 0000 unimp -80014b74: 0036 c.slli zero,0xd -80014b76: 0000 unimp -80014b78: 00000037 lui zero,0x0 -80014b7c: 0038 addi a4,sp,8 -80014b7e: 0000 unimp -80014b80: 0039 c.nop 14 -80014b82: 0000 unimp -80014b84: 0061 c.nop 24 -80014b86: 0000 unimp -80014b88: 0062 c.slli zero,0x18 -80014b8a: 0000 unimp -80014b8c: 00000063 beqz zero,80014b8c <__clzsi2+0x1c4> -80014b90: 0064 addi s1,sp,12 +80014b3c: 72616853 0x72616853 +80014b40: 6465 lui s0,0x19 +80014b42: 4d20 lw s0,88(a0) +80014b44: 6d65 lui s10,0x19 +80014b46: 2079726f jal tp,800ac54c <__BSS_END__+0x95910> +80014b4a: 6574 flw fa3,76(a0) +80014b4c: 000a7473 csrrci s0,ustatus,20 +80014b50: 7470 flw fa2,108(s0) +80014b52: 3a72 fld fs4,312(sp) +80014b54: 0020 addi s0,sp,8 +80014b56: 0000 unimp +80014b58: 6769724f fnmadd.q ft4,fs2,fs6,fa2 +80014b5c: 6e69 lui t3,0x1a +80014b5e: 6c61 lui s8,0x18 +80014b60: 5620 lw s0,104(a2) +80014b62: 6c61 lui s8,0x18 +80014b64: 6575 lui a0,0x1d +80014b66: 203a fld ft0,392(sp) +80014b68: 0000 unimp +80014b6a: 0000 unimp +80014b6c: 6552 flw fa0,20(sp) +80014b6e: 6461 lui s0,0x18 +80014b70: 5620 lw s0,104(a2) +80014b72: 6c61 lui s8,0x18 +80014b74: 6575 lui a0,0x1d +80014b76: 203a fld ft0,392(sp) +80014b78: 0000 unimp +80014b7a: 0000 unimp +80014b7c: 2d2d jal 800151b6 <__mprec_bigtens+0xd6> +80014b7e: 2d2d jal 800151b8 <__mprec_bigtens+0xd8> +80014b80: 2d2d jal 800151ba <__mprec_bigtens+0xda> +80014b82: 2d2d jal 800151bc <__mprec_bigtens+0xdc> +80014b84: 2d2d jal 800151be <__mprec_bigtens+0xde> +80014b86: 2d2d jal 800151c0 <__mprec_bigtens+0xe0> +80014b88: 2d2d jal 800151c2 <__mprec_bigtens+0xe2> +80014b8a: 2d2d jal 800151c4 <__mprec_bigtens+0xe4> +80014b8c: 2d2d jal 800151c6 <__mprec_bigtens+0xe6> +80014b8e: 0a2d addi s4,s4,11 +80014b90: 0000 unimp 80014b92: 0000 unimp -80014b94: 0065 c.nop 25 -80014b96: 0000 unimp -80014b98: 0066 c.slli zero,0x19 -80014b9a: 0000 unimp -80014b9c: 654c flw fa1,12(a0) -80014b9e: 2774 fld fa3,200(a4) -80014ba0: 74732073 csrs 0x747,t1 -80014ba4: 7261 lui tp,0xffff8 -80014ba6: 2e74 fld fa3,216(a2) -80014ba8: 2e2e fld ft8,200(sp) -80014baa: 000a c.slli zero,0x2 -80014bac: 6156 flw ft2,84(sp) -80014bae: 756c flw fa1,108(a0) -80014bb0: 3a65 jal 80014568 <__extenddftf2+0xe0> -80014bb2: 0020 addi s0,sp,8 -80014bb4: 706d6953 0x706d6953 -80014bb8: 656c flw fa1,76(a0) -80014bba: 4d20 lw s0,88(a0) -80014bbc: 6961 lui s2,0x18 -80014bbe: 0a6e slli s4,s4,0x1b -80014bc0: 0000 unimp -80014bc2: 0000 unimp -80014bc4: 6574 flw fa3,76(a0) -80014bc6: 645f7473 csrrci s0,0x645,30 -80014bca: 7669 lui a2,0xffffa -80014bcc: 7265 lui tp,0xffff9 -80014bce: 636e6567 0x636e6567 -80014bd2: 0a65 addi s4,s4,25 -80014bd4: 0000 unimp +80014b94: 4e49 li t3,18 +80014b96: 0046 c.slli zero,0x11 +80014b98: 6e69 lui t3,0x1a +80014b9a: 0066 c.slli zero,0x19 +80014b9c: 414e lw sp,208(sp) +80014b9e: 004e c.slli zero,0x13 +80014ba0: 616e flw ft2,216(sp) +80014ba2: 006e c.slli zero,0x1b +80014ba4: 3130 fld fa2,96(a0) +80014ba6: 3332 fld ft6,296(sp) +80014ba8: 3534 fld fa3,104(a0) +80014baa: 3736 fld fa4,360(sp) +80014bac: 3938 fld fa4,112(a0) +80014bae: 6261 lui tp,0x18 +80014bb0: 66656463 bltu a0,t1,80015218 <__mprec_bigtens+0x138> +80014bb4: 0000 unimp +80014bb6: 0000 unimp +80014bb8: 3130 fld fa2,96(a0) +80014bba: 3332 fld ft6,296(sp) +80014bbc: 3534 fld fa3,104(a0) +80014bbe: 3736 fld fa4,360(sp) +80014bc0: 3938 fld fa4,112(a0) +80014bc2: 4241 li tp,16 +80014bc4: 46454443 fmadd.q fs0,fa0,ft4,fs0,rmm +80014bc8: 0000 unimp +80014bca: 0000 unimp +80014bcc: 6e28 flw fa0,88(a2) +80014bce: 6c75 lui s8,0x1d +80014bd0: 296c fld fa1,208(a0) +80014bd2: 0000 unimp +80014bd4: 0030 addi a2,sp,8 80014bd6: 0000 unimp -80014bd8: 6574 flw fa3,76(a0) -80014bda: 775f7473 csrrci s0,0x775,30 -80014bde: 77617073 csrci 0x776,2 -80014be2: 0a6e slli s4,s4,0x1b -80014be4: 0000 unimp -80014be6: 0000 unimp -80014be8: 72616853 0x72616853 -80014bec: 6465 lui s0,0x19 -80014bee: 4d20 lw s0,88(a0) -80014bf0: 6d65 lui s10,0x19 -80014bf2: 2079726f jal tp,800ac5f8 <__BSS_END__+0x959bc> -80014bf6: 6574 flw fa3,76(a0) -80014bf8: 000a7473 csrrci s0,ustatus,20 -80014bfc: 7470 flw fa2,108(s0) -80014bfe: 3a72 fld fs4,312(sp) -80014c00: 0020 addi s0,sp,8 -80014c02: 0000 unimp -80014c04: 6769724f fnmadd.q ft4,fs2,fs6,fa2 -80014c08: 6e69 lui t3,0x1a -80014c0a: 6c61 lui s8,0x18 -80014c0c: 5620 lw s0,104(a2) -80014c0e: 6c61 lui s8,0x18 -80014c10: 6575 lui a0,0x1d -80014c12: 203a fld ft0,392(sp) -80014c14: 0000 unimp -80014c16: 0000 unimp -80014c18: 6552 flw fa0,20(sp) -80014c1a: 6461 lui s0,0x18 -80014c1c: 5620 lw s0,104(a2) -80014c1e: 6c61 lui s8,0x18 -80014c20: 6575 lui a0,0x1d -80014c22: 203a fld ft0,392(sp) -80014c24: 0000 unimp -80014c26: 0000 unimp -80014c28: 2d2d jal 80015262 <__mprec_bigtens+0xaa> -80014c2a: 2d2d jal 80015264 <__mprec_bigtens+0xac> -80014c2c: 2d2d jal 80015266 <__mprec_bigtens+0xae> -80014c2e: 2d2d jal 80015268 <__mprec_bigtens+0xb0> -80014c30: 2d2d jal 8001526a <__mprec_bigtens+0xb2> -80014c32: 2d2d jal 8001526c <__mprec_bigtens+0xb4> -80014c34: 2d2d jal 8001526e <__mprec_bigtens+0xb6> -80014c36: 2d2d jal 80015270 <__mprec_bigtens+0xb8> -80014c38: 2d2d jal 80015272 <__mprec_bigtens+0xba> -80014c3a: 0a2d addi s4,s4,11 -80014c3c: 0000 unimp -80014c3e: 0000 unimp -80014c40: 7876 flw fa6,124(sp) -80014c42: 735f 6170 6e77 0x6e776170735f -80014c48: 70726157 0x70726157 -80014c4c: 616d2073 csrs 0x616,s10 -80014c50: 5f74 lw a3,124(a4) -80014c52: 6461 lui s0,0x18 -80014c54: 5f64 lw s1,124(a4) -80014c56: 6e72656b 0x6e72656b -80014c5a: 6c65 lui s8,0x19 -80014c5c: 000a c.slli zero,0x2 -80014c5e: 0000 unimp -80014c60: 0020 addi s0,sp,8 -80014c62: 0000 unimp -80014c64: 000a c.slli zero,0x2 -80014c66: 0000 unimp -80014c68: 4e49 li t3,18 -80014c6a: 0046 c.slli zero,0x11 -80014c6c: 6e69 lui t3,0x1a -80014c6e: 0066 c.slli zero,0x19 -80014c70: 414e lw sp,208(sp) -80014c72: 004e c.slli zero,0x13 -80014c74: 616e flw ft2,216(sp) -80014c76: 006e c.slli zero,0x1b -80014c78: 3130 fld fa2,96(a0) -80014c7a: 3332 fld ft6,296(sp) -80014c7c: 3534 fld fa3,104(a0) -80014c7e: 3736 fld fa4,360(sp) -80014c80: 3938 fld fa4,112(a0) -80014c82: 6261 lui tp,0x18 -80014c84: 66656463 bltu a0,t1,800152ec <__mprec_bigtens+0x134> -80014c88: 0000 unimp -80014c8a: 0000 unimp -80014c8c: 3130 fld fa2,96(a0) -80014c8e: 3332 fld ft6,296(sp) -80014c90: 3534 fld fa3,104(a0) -80014c92: 3736 fld fa4,360(sp) -80014c94: 3938 fld fa4,112(a0) -80014c96: 4241 li tp,16 -80014c98: 46454443 fmadd.q fs0,fa0,ft4,fs0,rmm -80014c9c: 0000 unimp -80014c9e: 0000 unimp -80014ca0: 6e28 flw fa0,88(a2) -80014ca2: 6c75 lui s8,0x1d -80014ca4: 296c fld fa1,208(a0) -80014ca6: 0000 unimp -80014ca8: 0030 addi a2,sp,8 -80014caa: 0000 unimp -80014cac: 1fa0 addi s0,sp,1016 +80014bd8: 1edc addi a5,sp,884 +80014bda: 8000 0x8000 +80014bdc: 155c addi a5,sp,676 +80014bde: 8000 0x8000 +80014be0: 155c addi a5,sp,676 +80014be2: 8000 0x8000 +80014be4: 1ed0 addi a2,sp,884 +80014be6: 8000 0x8000 +80014be8: 155c addi a5,sp,676 +80014bea: 8000 0x8000 +80014bec: 155c addi a5,sp,676 +80014bee: 8000 0x8000 +80014bf0: 155c addi a5,sp,676 +80014bf2: 8000 0x8000 +80014bf4: 1750 addi a2,sp,932 +80014bf6: 8000 0x8000 +80014bf8: 155c addi a5,sp,676 +80014bfa: 8000 0x8000 +80014bfc: 155c addi a5,sp,676 +80014bfe: 8000 0x8000 +80014c00: 1eac addi a1,sp,888 +80014c02: 8000 0x8000 +80014c04: 1e4c addi a1,sp,820 +80014c06: 8000 0x8000 +80014c08: 155c addi a5,sp,676 +80014c0a: 8000 0x8000 +80014c0c: 1d38 addi a4,sp,696 +80014c0e: 8000 0x8000 +80014c10: 1e68 addi a0,sp,828 +80014c12: 8000 0x8000 +80014c14: 155c addi a5,sp,676 +80014c16: 8000 0x8000 +80014c18: 1e5c addi a5,sp,820 +80014c1a: 8000 0x8000 +80014c1c: 152c addi a1,sp,680 +80014c1e: 8000 0x8000 +80014c20: 152c addi a1,sp,680 +80014c22: 8000 0x8000 +80014c24: 152c addi a1,sp,680 +80014c26: 8000 0x8000 +80014c28: 152c addi a1,sp,680 +80014c2a: 8000 0x8000 +80014c2c: 152c addi a1,sp,680 +80014c2e: 8000 0x8000 +80014c30: 152c addi a1,sp,680 +80014c32: 8000 0x8000 +80014c34: 152c addi a1,sp,680 +80014c36: 8000 0x8000 +80014c38: 152c addi a1,sp,680 +80014c3a: 8000 0x8000 +80014c3c: 152c addi a1,sp,680 +80014c3e: 8000 0x8000 +80014c40: 155c addi a5,sp,676 +80014c42: 8000 0x8000 +80014c44: 155c addi a5,sp,676 +80014c46: 8000 0x8000 +80014c48: 155c addi a5,sp,676 +80014c4a: 8000 0x8000 +80014c4c: 155c addi a5,sp,676 +80014c4e: 8000 0x8000 +80014c50: 155c addi a5,sp,676 +80014c52: 8000 0x8000 +80014c54: 155c addi a5,sp,676 +80014c56: 8000 0x8000 +80014c58: 155c addi a5,sp,676 +80014c5a: 8000 0x8000 +80014c5c: 17cc addi a1,sp,996 +80014c5e: 8000 0x8000 +80014c60: 155c addi a5,sp,676 +80014c62: 8000 0x8000 +80014c64: 1c88 addi a0,sp,624 +80014c66: 8000 0x8000 +80014c68: 1f6c addi a1,sp,956 +80014c6a: 8000 0x8000 +80014c6c: 17cc addi a1,sp,996 +80014c6e: 8000 0x8000 +80014c70: 17cc addi a1,sp,996 +80014c72: 8000 0x8000 +80014c74: 17cc addi a1,sp,996 +80014c76: 8000 0x8000 +80014c78: 155c addi a5,sp,676 +80014c7a: 8000 0x8000 +80014c7c: 155c addi a5,sp,676 +80014c7e: 8000 0x8000 +80014c80: 155c addi a5,sp,676 +80014c82: 8000 0x8000 +80014c84: 155c addi a5,sp,676 +80014c86: 8000 0x8000 +80014c88: 1f60 addi s0,sp,956 +80014c8a: 8000 0x8000 +80014c8c: 155c addi a5,sp,676 +80014c8e: 8000 0x8000 +80014c90: 155c addi a5,sp,676 +80014c92: 8000 0x8000 +80014c94: 1ef4 addi a3,sp,892 +80014c96: 8000 0x8000 +80014c98: 155c addi a5,sp,676 +80014c9a: 8000 0x8000 +80014c9c: 155c addi a5,sp,676 +80014c9e: 8000 0x8000 +80014ca0: 155c addi a5,sp,676 +80014ca2: 8000 0x8000 +80014ca4: 1cb4 addi a3,sp,632 +80014ca6: 8000 0x8000 +80014ca8: 155c addi a5,sp,676 +80014caa: 8000 0x8000 +80014cac: 1f2c addi a1,sp,952 80014cae: 8000 0x8000 -80014cb0: 1620 addi s0,sp,808 +80014cb0: 155c addi a5,sp,676 80014cb2: 8000 0x8000 -80014cb4: 1620 addi s0,sp,808 +80014cb4: 155c addi a5,sp,676 80014cb6: 8000 0x8000 -80014cb8: 1f94 addi a3,sp,1008 +80014cb8: 2a28 fld fa0,80(a2) 80014cba: 8000 0x8000 -80014cbc: 1620 addi s0,sp,808 +80014cbc: 155c addi a5,sp,676 80014cbe: 8000 0x8000 -80014cc0: 1620 addi s0,sp,808 +80014cc0: 155c addi a5,sp,676 80014cc2: 8000 0x8000 -80014cc4: 1620 addi s0,sp,808 +80014cc4: 155c addi a5,sp,676 80014cc6: 8000 0x8000 -80014cc8: 1814 addi a3,sp,48 +80014cc8: 155c addi a5,sp,676 80014cca: 8000 0x8000 -80014ccc: 1620 addi s0,sp,808 +80014ccc: 155c addi a5,sp,676 80014cce: 8000 0x8000 -80014cd0: 1620 addi s0,sp,808 +80014cd0: 155c addi a5,sp,676 80014cd2: 8000 0x8000 -80014cd4: 1f70 addi a2,sp,956 +80014cd4: 155c addi a5,sp,676 80014cd6: 8000 0x8000 -80014cd8: 1f10 addi a2,sp,944 +80014cd8: 155c addi a5,sp,676 80014cda: 8000 0x8000 -80014cdc: 1620 addi s0,sp,808 +80014cdc: 17cc addi a1,sp,996 80014cde: 8000 0x8000 -80014ce0: 1dfc addi a5,sp,764 +80014ce0: 155c addi a5,sp,676 80014ce2: 8000 0x8000 -80014ce4: 1f2c addi a1,sp,952 +80014ce4: 1c88 addi a0,sp,624 80014ce6: 8000 0x8000 -80014ce8: 1620 addi s0,sp,808 +80014ce8: 289c fld fa5,16(s1) 80014cea: 8000 0x8000 -80014cec: 1f20 addi s0,sp,952 +80014cec: 17cc addi a1,sp,996 80014cee: 8000 0x8000 -80014cf0: 15f0 addi a2,sp,748 +80014cf0: 17cc addi a1,sp,996 80014cf2: 8000 0x8000 -80014cf4: 15f0 addi a2,sp,748 +80014cf4: 17cc addi a1,sp,996 80014cf6: 8000 0x8000 -80014cf8: 15f0 addi a2,sp,748 +80014cf8: 1e38 addi a4,sp,824 80014cfa: 8000 0x8000 -80014cfc: 15f0 addi a2,sp,748 +80014cfc: 289c fld fa5,16(s1) 80014cfe: 8000 0x8000 -80014d00: 15f0 addi a2,sp,748 +80014d00: 1794 addi a3,sp,992 80014d02: 8000 0x8000 -80014d04: 15f0 addi a2,sp,748 +80014d04: 155c addi a5,sp,676 80014d06: 8000 0x8000 -80014d08: 15f0 addi a2,sp,748 +80014d08: 1d94 addi a3,sp,752 80014d0a: 8000 0x8000 -80014d0c: 15f0 addi a2,sp,748 +80014d0c: 155c addi a5,sp,676 80014d0e: 8000 0x8000 -80014d10: 15f0 addi a2,sp,748 +80014d10: 1d44 addi s1,sp,692 80014d12: 8000 0x8000 -80014d14: 1620 addi s0,sp,808 +80014d14: 2a3c fld fa5,80(a2) 80014d16: 8000 0x8000 -80014d18: 1620 addi s0,sp,808 +80014d18: 1da8 addi a0,sp,760 80014d1a: 8000 0x8000 -80014d1c: 1620 addi s0,sp,808 +80014d1c: 1794 addi a3,sp,992 80014d1e: 8000 0x8000 -80014d20: 1620 addi s0,sp,808 +80014d20: 155c addi a5,sp,676 80014d22: 8000 0x8000 -80014d24: 1620 addi s0,sp,808 +80014d24: 1cb4 addi a3,sp,632 80014d26: 8000 0x8000 -80014d28: 1620 addi s0,sp,808 +80014d28: 178c addi a1,sp,992 80014d2a: 8000 0x8000 -80014d2c: 1620 addi s0,sp,808 +80014d2c: 29bc fld fa5,80(a1) 80014d2e: 8000 0x8000 -80014d30: 1890 addi a2,sp,112 +80014d30: 155c addi a5,sp,676 80014d32: 8000 0x8000 -80014d34: 1620 addi s0,sp,808 +80014d34: 155c addi a5,sp,676 80014d36: 8000 0x8000 -80014d38: 1d4c addi a1,sp,692 +80014d38: 29c8 fld fa0,144(a1) 80014d3a: 8000 0x8000 -80014d3c: 2030 fld fa2,64(s0) +80014d3c: 155c addi a5,sp,676 80014d3e: 8000 0x8000 -80014d40: 1890 addi a2,sp,112 +80014d40: 178c addi a1,sp,992 80014d42: 8000 0x8000 -80014d44: 1890 addi a2,sp,112 -80014d46: 8000 0x8000 -80014d48: 1890 addi a2,sp,112 -80014d4a: 8000 0x8000 -80014d4c: 1620 addi s0,sp,808 -80014d4e: 8000 0x8000 -80014d50: 1620 addi s0,sp,808 -80014d52: 8000 0x8000 -80014d54: 1620 addi s0,sp,808 -80014d56: 8000 0x8000 -80014d58: 1620 addi s0,sp,808 -80014d5a: 8000 0x8000 -80014d5c: 2024 fld fs1,64(s0) -80014d5e: 8000 0x8000 -80014d60: 1620 addi s0,sp,808 -80014d62: 8000 0x8000 -80014d64: 1620 addi s0,sp,808 -80014d66: 8000 0x8000 -80014d68: 1fb8 addi a4,sp,1016 -80014d6a: 8000 0x8000 -80014d6c: 1620 addi s0,sp,808 -80014d6e: 8000 0x8000 -80014d70: 1620 addi s0,sp,808 -80014d72: 8000 0x8000 -80014d74: 1620 addi s0,sp,808 -80014d76: 8000 0x8000 -80014d78: 1d78 addi a4,sp,700 -80014d7a: 8000 0x8000 -80014d7c: 1620 addi s0,sp,808 -80014d7e: 8000 0x8000 -80014d80: 1ff0 addi a2,sp,1020 -80014d82: 8000 0x8000 -80014d84: 1620 addi s0,sp,808 -80014d86: 8000 0x8000 -80014d88: 1620 addi s0,sp,808 -80014d8a: 8000 0x8000 -80014d8c: 2aec fld fa1,208(a3) -80014d8e: 8000 0x8000 -80014d90: 1620 addi s0,sp,808 -80014d92: 8000 0x8000 -80014d94: 1620 addi s0,sp,808 -80014d96: 8000 0x8000 -80014d98: 1620 addi s0,sp,808 -80014d9a: 8000 0x8000 -80014d9c: 1620 addi s0,sp,808 -80014d9e: 8000 0x8000 -80014da0: 1620 addi s0,sp,808 -80014da2: 8000 0x8000 -80014da4: 1620 addi s0,sp,808 -80014da6: 8000 0x8000 -80014da8: 1620 addi s0,sp,808 -80014daa: 8000 0x8000 -80014dac: 1620 addi s0,sp,808 -80014dae: 8000 0x8000 -80014db0: 1890 addi a2,sp,112 -80014db2: 8000 0x8000 -80014db4: 1620 addi s0,sp,808 -80014db6: 8000 0x8000 -80014db8: 1d4c addi a1,sp,692 -80014dba: 8000 0x8000 -80014dbc: 2960 fld fs0,208(a0) -80014dbe: 8000 0x8000 -80014dc0: 1890 addi a2,sp,112 -80014dc2: 8000 0x8000 -80014dc4: 1890 addi a2,sp,112 -80014dc6: 8000 0x8000 -80014dc8: 1890 addi a2,sp,112 -80014dca: 8000 0x8000 -80014dcc: 1efc addi a5,sp,892 -80014dce: 8000 0x8000 -80014dd0: 2960 fld fs0,208(a0) -80014dd2: 8000 0x8000 -80014dd4: 1858 addi a4,sp,52 -80014dd6: 8000 0x8000 -80014dd8: 1620 addi s0,sp,808 -80014dda: 8000 0x8000 -80014ddc: 1e58 addi a4,sp,820 -80014dde: 8000 0x8000 -80014de0: 1620 addi s0,sp,808 -80014de2: 8000 0x8000 -80014de4: 1e08 addi a0,sp,816 -80014de6: 8000 0x8000 -80014de8: 2b00 fld fs0,16(a4) -80014dea: 8000 0x8000 -80014dec: 1e6c addi a1,sp,828 -80014dee: 8000 0x8000 -80014df0: 1858 addi a4,sp,52 -80014df2: 8000 0x8000 -80014df4: 1620 addi s0,sp,808 -80014df6: 8000 0x8000 -80014df8: 1d78 addi a4,sp,700 -80014dfa: 8000 0x8000 -80014dfc: 1850 addi a2,sp,52 -80014dfe: 8000 0x8000 -80014e00: 2a80 fld fs0,16(a3) -80014e02: 8000 0x8000 -80014e04: 1620 addi s0,sp,808 -80014e06: 8000 0x8000 -80014e08: 1620 addi s0,sp,808 -80014e0a: 8000 0x8000 -80014e0c: 2a8c fld fa1,16(a3) -80014e0e: 8000 0x8000 -80014e10: 1620 addi s0,sp,808 -80014e12: 8000 0x8000 -80014e14: 1850 addi a2,sp,52 -80014e16: 8000 0x8000 -80014e18 : -80014e18: 2020 fld fs0,64(s0) -80014e1a: 2020 fld fs0,64(s0) -80014e1c: 2020 fld fs0,64(s0) -80014e1e: 2020 fld fs0,64(s0) -80014e20: 2020 fld fs0,64(s0) -80014e22: 2020 fld fs0,64(s0) -80014e24: 2020 fld fs0,64(s0) -80014e26: 2020 fld fs0,64(s0) +80014d44 : +80014d44: 2020 fld fs0,64(s0) +80014d46: 2020 fld fs0,64(s0) +80014d48: 2020 fld fs0,64(s0) +80014d4a: 2020 fld fs0,64(s0) +80014d4c: 2020 fld fs0,64(s0) +80014d4e: 2020 fld fs0,64(s0) +80014d50: 2020 fld fs0,64(s0) +80014d52: 2020 fld fs0,64(s0) -80014e28 : -80014e28: 3030 fld fa2,96(s0) -80014e2a: 3030 fld fa2,96(s0) -80014e2c: 3030 fld fa2,96(s0) -80014e2e: 3030 fld fa2,96(s0) -80014e30: 3030 fld fa2,96(s0) -80014e32: 3030 fld fa2,96(s0) -80014e34: 3030 fld fa2,96(s0) -80014e36: 3030 fld fa2,96(s0) -80014e38: 4e20 lw s0,88(a2) -80014e3a: 4e61 li t3,24 -80014e3c: 0020 addi s0,sp,8 -80014e3e: 0000 unimp -80014e40: 2d20 fld fs0,88(a0) -80014e42: 6e49 lui t3,0x12 -80014e44: 6966 flw fs2,88(sp) -80014e46: 696e flw fs2,216(sp) -80014e48: 7974 flw fa3,116(a0) -80014e4a: 0020 addi s0,sp,8 -80014e4c: 4920 lw s0,80(a0) -80014e4e: 666e flw fa2,216(sp) -80014e50: 6e69 lui t3,0x1a -80014e52: 7469 lui s0,0xffffa -80014e54: 2079 jal 80014ee2 -80014e56: 0000 unimp -80014e58: 614e flw ft2,208(sp) -80014e5a: 004e c.slli zero,0x13 -80014e5c: 2545 jal 800154fc -80014e5e: 0064 addi s1,sp,12 +80014d54 : +80014d54: 3030 fld fa2,96(s0) +80014d56: 3030 fld fa2,96(s0) +80014d58: 3030 fld fa2,96(s0) +80014d5a: 3030 fld fa2,96(s0) +80014d5c: 3030 fld fa2,96(s0) +80014d5e: 3030 fld fa2,96(s0) +80014d60: 3030 fld fa2,96(s0) +80014d62: 3030 fld fa2,96(s0) +80014d64: 4e20 lw s0,88(a2) +80014d66: 4e61 li t3,24 +80014d68: 0020 addi s0,sp,8 +80014d6a: 0000 unimp +80014d6c: 2d20 fld fs0,88(a0) +80014d6e: 6e49 lui t3,0x12 +80014d70: 6966 flw fs2,88(sp) +80014d72: 696e flw fs2,216(sp) +80014d74: 7974 flw fa3,116(a0) +80014d76: 0020 addi s0,sp,8 +80014d78: 4920 lw s0,80(a0) +80014d7a: 666e flw fa2,216(sp) +80014d7c: 6e69 lui t3,0x1a +80014d7e: 7469 lui s0,0xffffa +80014d80: 2079 jal 80014e0e +80014d82: 0000 unimp +80014d84: 614e flw ft2,208(sp) +80014d86: 004e c.slli zero,0x13 +80014d88: 2545 jal 80015428 +80014d8a: 0064 addi s1,sp,12 -80014e60 : +80014d8c : ... -80014e74 : +80014da0 : ... -80014e84: 8000 0x8000 -80014e86: 3fff 0x3fff +80014db0: 8000 0x8000 +80014db2: 3fff 0x3fff -80014e88 : -80014e88: 6576 flw fa0,92(sp) -80014e8a: 4a92 lw s5,4(sp) -80014e8c: 804a c.mv zero,s2 -80014e8e: c94c153f 8a20979a 0x8a20979ac94c153f -80014e96: 5202 lw tp,32(sp) -80014e98: c460 sw s0,76(s0) -80014e9a: 7525 lui a0,0xfffe9 -80014e9c: 6a32 flw fs4,12(sp) -80014e9e: ce52 sw s4,28(sp) -80014ea0: 329a fld ft5,416(sp) -80014ea2: 28ce fld fa7,208(sp) -80014ea4: a74d j 80015646 -80014ea6: 5de4 lw s1,124(a1) -80014ea8: c53d beqz a0,80014f16 -80014eaa: 3b5d jal 80014c60 <__clzsi2+0x298> -80014eac: 5a929e8b 0x5a929e8b -80014eb0: 526c lw a1,100(a2) -80014eb2: 50ce lw ra,240(sp) -80014eb4: 3d28f18b 0x3d28f18b -80014eb8: 650d lui a0,0x3 -80014eba: 81750c17 auipc s8,0x81750 -80014ebe: 7586 flw fa1,96(sp) -80014ec0: c976 sw t4,144(sp) -80014ec2: 4d48 lw a0,28(a0) -80014ec4: 9c66 add s8,s8,s9 -80014ec6: 58f8 lw a4,116(s1) -80014ec8: bc50 fsd fa2,184(s0) -80014eca: 5c54 lw a3,60(s0) -80014ecc: cc65 beqz s0,80014fc4 -80014ece: 91c6 add gp,gp,a7 -80014ed0: a60e fsd ft3,264(sp) -80014ed2: a0ae fsd fa1,64(sp) -80014ed4: e319 bnez a4,80014eda -80014ed6: 851e46a3 0x851e46a3 -80014eda: 98feeab7 lui s5,0x98fee -80014ede: ddbb901b 0xddbb901b -80014ee2: de8d beqz a3,80014e1c -80014ee4: 9df9 0x9df9 -80014ee6: aa7eebfb 0xaa7eebfb -80014eea: 4351 li t1,20 -80014eec: 0235 addi tp,tp,13 -80014eee: 36b10137 lui sp,0x36b10 -80014ef2: 336c fld fa1,224(a4) -80014ef4: 8cdfc66f jal a2,800117c0 <__muldf3+0x3d8> -80014ef8: 80e9 srli s1,s1,0x1a -80014efa: 47c9 li a5,18 -80014efc: 93ba add t2,t2,a4 -80014efe: 41a8 lw a0,64(a1) -80014f00: 50f8 lw a4,100(s1) -80014f02: c76b25fb 0xc76b25fb -80014f06: 6b71 lui s6,0x1c -80014f08: a6d53cbf 1f49ffcf 0x1f49ffcfa6d53cbf -80014f10: c278 sw a4,68(a2) -80014f12: 000040d3 fadd.s ft1,ft0,ft0,rmm -80014f16: 0000 unimp -80014f18: 0000 unimp -80014f1a: 0000 unimp -80014f1c: f020 fsw fs0,96(s0) -80014f1e: b59d j 80014d84 <__clzsi2+0x3bc> -80014f20: 2b70 fld fa2,208(a4) -80014f22: ada8 fsd fa0,88(a1) -80014f24: 9dc5 0x9dc5 -80014f26: 4069 c.li zero,26 +80014db4 : +80014db4: 6576 flw fa0,92(sp) +80014db6: 4a92 lw s5,4(sp) +80014db8: 804a c.mv zero,s2 +80014dba: c94c153f 8a20979a 0x8a20979ac94c153f +80014dc2: 5202 lw tp,32(sp) +80014dc4: c460 sw s0,76(s0) +80014dc6: 7525 lui a0,0xfffe9 +80014dc8: 6a32 flw fs4,12(sp) +80014dca: ce52 sw s4,28(sp) +80014dcc: 329a fld ft5,416(sp) +80014dce: 28ce fld fa7,208(sp) +80014dd0: a74d j 80015572 +80014dd2: 5de4 lw s1,124(a1) +80014dd4: c53d beqz a0,80014e42 +80014dd6: 3b5d jal 80014b8c <__clzsi2+0x288> +80014dd8: 5a929e8b 0x5a929e8b +80014ddc: 526c lw a1,100(a2) +80014dde: 50ce lw ra,240(sp) +80014de0: 3d28f18b 0x3d28f18b +80014de4: 650d lui a0,0x3 +80014de6: 81750c17 auipc s8,0x81750 +80014dea: 7586 flw fa1,96(sp) +80014dec: c976 sw t4,144(sp) +80014dee: 4d48 lw a0,28(a0) +80014df0: 9c66 add s8,s8,s9 +80014df2: 58f8 lw a4,116(s1) +80014df4: bc50 fsd fa2,184(s0) +80014df6: 5c54 lw a3,60(s0) +80014df8: cc65 beqz s0,80014ef0 +80014dfa: 91c6 add gp,gp,a7 +80014dfc: a60e fsd ft3,264(sp) +80014dfe: a0ae fsd fa1,64(sp) +80014e00: e319 bnez a4,80014e06 +80014e02: 851e46a3 0x851e46a3 +80014e06: 98feeab7 lui s5,0x98fee +80014e0a: ddbb901b 0xddbb901b +80014e0e: de8d beqz a3,80014d48 +80014e10: 9df9 0x9df9 +80014e12: aa7eebfb 0xaa7eebfb +80014e16: 4351 li t1,20 +80014e18: 0235 addi tp,tp,13 +80014e1a: 36b10137 lui sp,0x36b10 +80014e1e: 336c fld fa1,224(a4) +80014e20: 8cdfc66f jal a2,800116ec <__muldf3+0x3c8> +80014e24: 80e9 srli s1,s1,0x1a +80014e26: 47c9 li a5,18 +80014e28: 93ba add t2,t2,a4 +80014e2a: 41a8 lw a0,64(a1) +80014e2c: 50f8 lw a4,100(s1) +80014e2e: c76b25fb 0xc76b25fb +80014e32: 6b71 lui s6,0x1c +80014e34: a6d53cbf 1f49ffcf 0x1f49ffcfa6d53cbf +80014e3c: c278 sw a4,68(a2) +80014e3e: 000040d3 fadd.s ft1,ft0,ft0,rmm +80014e42: 0000 unimp +80014e44: 0000 unimp +80014e46: 0000 unimp +80014e48: f020 fsw fs0,96(s0) +80014e4a: b59d j 80014cb0 <__clzsi2+0x3ac> +80014e4c: 2b70 fld fa2,208(a4) +80014e4e: ada8 fsd fa0,88(a1) +80014e50: 9dc5 0x9dc5 +80014e52: 4069 c.li zero,26 ... -80014f34: 0400 addi s0,sp,512 -80014f36: 8e1bc9bf 00004034 0x40348e1bc9bf +80014e60: 0400 addi s0,sp,512 +80014e62: 8e1bc9bf 00004034 0x40348e1bc9bf ... -80014f4a: 2000 fld fs0,0(s0) -80014f4c: bebc fsd fa5,120(a3) -80014f4e: 4019 c.li zero,6 +80014e76: 2000 fld fs0,0(s0) +80014e78: bebc fsd fa5,120(a3) +80014e7a: 4019 c.li zero,6 ... -80014f60: 9c40 0x9c40 -80014f62: 400c lw a1,0(s0) +80014e8c: 9c40 0x9c40 +80014e8e: 400c lw a1,0(s0) ... -80014f74: c800 sw s0,16(s0) -80014f76: 4005 c.li zero,1 +80014ea0: c800 sw s0,16(s0) +80014ea2: 4005 c.li zero,1 ... -80014f88: a000 fsd fs0,0(s0) -80014f8a: 4002 0x4002 +80014eb4: a000 fsd fs0,0(s0) +80014eb6: 4002 0x4002 -80014f8c : -80014f8c: 2030 fld fa2,64(s0) -80014f8e: cffc sw a5,92(a5) -80014f90: 8123a1c3 fmadd.s ft3,ft7,fs2,fa6,rdn -80014f94: 9fde2de3 0x9fde2de3 -80014f98: d2ce sw s3,100(sp) -80014f9a: 04c8 addi a0,sp,580 -80014f9c: a6dd j 80015382 -80014f9e: 0ad8 addi a4,sp,340 -80014fa0: 8264 0x8264 -80014fa2: f2ead2cb fnmsub.d ft5,fs5,fa4,ft10,unknown -80014fa6: 12d4 addi a3,sp,356 -80014fa8: 4925 li s2,9 -80014faa: 2de4 fld fs1,216(a1) -80014fac: 3436 fld fs0,360(sp) -80014fae: ceae534f fnmadd.q ft6,ft8,fa0,fs9,unknown -80014fb2: f53f256b 0xf53f256b -80014fb6: f698 fsw fa4,40(a3) -80014fb8: 01586bd3 fadd.s fs7,fa6,fs5,unknown -80014fbc: 87a6 mv a5,s1 -80014fbe: c0bd beqz s1,80015024 -80014fc0: 82a5da57 0x82a5da57 -80014fc4: a2a6 fsd fs1,320(sp) -80014fc6: 32b5 jal 80014932 <__trunctfdf2+0x2b6> -80014fc8: e731 bnez a4,80015014 -80014fca: 04d4 addi a3,sp,580 -80014fcc: e3f2 fsw ft8,196(sp) -80014fce: d332 sw a2,164(sp) -80014fd0: 7132 flw ft2,44(sp) -80014fd2: d21c sw a5,32(a2) -80014fd4: ee32db23 0xee32db23 -80014fd8: 9049 srli s0,s0,0x32 -80014fda: 395a fld fs2,432(sp) -80014fdc: a23e fsd fa5,256(sp) -80014fde: 5308 lw a0,32(a4) -80014fe0: 1155fefb 0x1155fefb -80014fe4: fa91 bnez a3,80014ef8 -80014fe6: 1939 addi s2,s2,-18 -80014fe8: 637a flw ft6,156(sp) -80014fea: 4325 li t1,9 -80014fec: c031 beqz s0,80015030 -80014fee: 3cac fld fa1,120(s1) -80014ff0: e26d bnez a2,800150d2 <__mprec_tens+0xa> -80014ff2: dbde sw s7,244(sp) -80014ff4: d05d beqz s0,80014f9a -80014ff6: b3f6 fsd ft9,480(sp) -80014ff8: ac7c fsd fa5,216(s0) -80014ffa: e4a0 fsw fs0,72(s1) -80014ffc: 64bc flw fa5,72(s1) -80014ffe: 467c lw a5,76(a2) -80015000: ddd0 sw a2,60(a1) -80015002: 3e55 jal 80014bb6 <__clzsi2+0x1ee> -80015004: 2a20 fld fs0,80(a2) -80015006: 6224 flw fs1,64(a2) -80015008: 98d747b3 0x98d747b3 -8001500c: e9a53f23 0xe9a53f23 -80015010: a539 j 8001561e -80015012: a87fea27 0xa87fea27 -80015016: 3f2a fld ft10,168(sp) -80015018: 4af20b5b 0x4af20b5b -8001501c: a581 j 8001565c -8001501e: 18ed addi a7,a7,-5 -80015020: 67de flw fa5,212(sp) -80015022: 94ba add s1,s1,a4 -80015024: 4539 li a0,14 -80015026: 1ead addi t4,t4,-21 -80015028: cfb1 beqz a5,80015084 -8001502a: 3f94 fld fa3,56(a5) -8001502c: bf71 j 80014fc8 -8001502e: 7989a9b3 0x7989a9b3 -80015032: be68 fsd fa0,248(a2) -80015034: 4c2e lw s8,200(sp) -80015036: c44de15b 0xc44de15b -8001503a: 94be add s1,s1,a5 -8001503c: e695 bnez a3,80015068 -8001503e: 3fc9 jal 80015010 -80015040: 3d4d jal 80014ef2 -80015042: 7c3d lui s8,0xfffef -80015044: 36ba fld fa3,424(sp) -80015046: fdc20d2b 0xfdc20d2b -8001504a: cefc sw a5,92(a3) -8001504c: 8461 srai s0,s0,0x18 -8001504e: 7711 lui a4,0xfffe4 -80015050: abcc fsd fa1,144(a5) -80015052: 3fe4 fld fs1,248(a5) -80015054: c155 beqz a0,800150f8 <__mprec_tens+0x30> -80015056: a4a8 fsd fa0,72(s1) -80015058: 404e 0x404e -8001505a: d3c36113 ori sp,t1,-708 -8001505e: e219652b 0xe219652b -80015062: 1758 addi a4,sp,932 -80015064: 3ff1d1b7 lui gp,0x3ff1d -80015068: d70a sw sp,172(sp) -8001506a: 0a3d70a3 0xa3d70a3 -8001506e: 3d70a3d7 0x3d70a3d7 -80015072: d70a sw sp,172(sp) -80015074: 0a3d70a3 0xa3d70a3 -80015078: 3ff8a3d7 0x3ff8a3d7 -8001507c: cccd beqz s1,80015136 <__mprec_tens+0x6e> -8001507e: cccc sw a1,28(s1) -80015080: cccc sw a1,28(s1) -80015082: cccc sw a1,28(s1) -80015084: cccc sw a1,28(s1) -80015086: cccc sw a1,28(s1) -80015088: cccc sw a1,28(s1) -8001508a: cccc sw a1,28(s1) -8001508c: cccc sw a1,28(s1) -8001508e: 0xffff3ffb +80014eb8 : +80014eb8: 2030 fld fa2,64(s0) +80014eba: cffc sw a5,92(a5) +80014ebc: 8123a1c3 fmadd.s ft3,ft7,fs2,fa6,rdn +80014ec0: 9fde2de3 0x9fde2de3 +80014ec4: d2ce sw s3,100(sp) +80014ec6: 04c8 addi a0,sp,580 +80014ec8: a6dd j 800152ae +80014eca: 0ad8 addi a4,sp,340 +80014ecc: 8264 0x8264 +80014ece: f2ead2cb fnmsub.d ft5,fs5,fa4,ft10,unknown +80014ed2: 12d4 addi a3,sp,356 +80014ed4: 4925 li s2,9 +80014ed6: 2de4 fld fs1,216(a1) +80014ed8: 3436 fld fs0,360(sp) +80014eda: ceae534f fnmadd.q ft6,ft8,fa0,fs9,unknown +80014ede: f53f256b 0xf53f256b +80014ee2: f698 fsw fa4,40(a3) +80014ee4: 01586bd3 fadd.s fs7,fa6,fs5,unknown +80014ee8: 87a6 mv a5,s1 +80014eea: c0bd beqz s1,80014f50 +80014eec: 82a5da57 0x82a5da57 +80014ef0: a2a6 fsd fs1,320(sp) +80014ef2: 32b5 jal 8001485e <__trunctfdf2+0x2a6> +80014ef4: e731 bnez a4,80014f40 +80014ef6: 04d4 addi a3,sp,580 +80014ef8: e3f2 fsw ft8,196(sp) +80014efa: d332 sw a2,164(sp) +80014efc: 7132 flw ft2,44(sp) +80014efe: d21c sw a5,32(a2) +80014f00: ee32db23 0xee32db23 +80014f04: 9049 srli s0,s0,0x32 +80014f06: 395a fld fs2,432(sp) +80014f08: a23e fsd fa5,256(sp) +80014f0a: 5308 lw a0,32(a4) +80014f0c: 1155fefb 0x1155fefb +80014f10: fa91 bnez a3,80014e24 +80014f12: 1939 addi s2,s2,-18 +80014f14: 637a flw ft6,156(sp) +80014f16: 4325 li t1,9 +80014f18: c031 beqz s0,80014f5c +80014f1a: 3cac fld fa1,120(s1) +80014f1c: e26d bnez a2,80014ffe <__mprec_tens+0xe> +80014f1e: dbde sw s7,244(sp) +80014f20: d05d beqz s0,80014ec6 +80014f22: b3f6 fsd ft9,480(sp) +80014f24: ac7c fsd fa5,216(s0) +80014f26: e4a0 fsw fs0,72(s1) +80014f28: 64bc flw fa5,72(s1) +80014f2a: 467c lw a5,76(a2) +80014f2c: ddd0 sw a2,60(a1) +80014f2e: 3e55 jal 80014ae2 <__clzsi2+0x1de> +80014f30: 2a20 fld fs0,80(a2) +80014f32: 6224 flw fs1,64(a2) +80014f34: 98d747b3 0x98d747b3 +80014f38: e9a53f23 0xe9a53f23 +80014f3c: a539 j 8001554a +80014f3e: a87fea27 0xa87fea27 +80014f42: 3f2a fld ft10,168(sp) +80014f44: 4af20b5b 0x4af20b5b +80014f48: a581 j 80015588 +80014f4a: 18ed addi a7,a7,-5 +80014f4c: 67de flw fa5,212(sp) +80014f4e: 94ba add s1,s1,a4 +80014f50: 4539 li a0,14 +80014f52: 1ead addi t4,t4,-21 +80014f54: cfb1 beqz a5,80014fb0 +80014f56: 3f94 fld fa3,56(a5) +80014f58: bf71 j 80014ef4 +80014f5a: 7989a9b3 0x7989a9b3 +80014f5e: be68 fsd fa0,248(a2) +80014f60: 4c2e lw s8,200(sp) +80014f62: c44de15b 0xc44de15b +80014f66: 94be add s1,s1,a5 +80014f68: e695 bnez a3,80014f94 +80014f6a: 3fc9 jal 80014f3c +80014f6c: 3d4d jal 80014e1e +80014f6e: 7c3d lui s8,0xfffef +80014f70: 36ba fld fa3,424(sp) +80014f72: fdc20d2b 0xfdc20d2b +80014f76: cefc sw a5,92(a3) +80014f78: 8461 srai s0,s0,0x18 +80014f7a: 7711 lui a4,0xfffe4 +80014f7c: abcc fsd fa1,144(a5) +80014f7e: 3fe4 fld fs1,248(a5) +80014f80: c155 beqz a0,80015024 <__mprec_tens+0x34> +80014f82: a4a8 fsd fa0,72(s1) +80014f84: 404e 0x404e +80014f86: d3c36113 ori sp,t1,-708 +80014f8a: e219652b 0xe219652b +80014f8e: 1758 addi a4,sp,932 +80014f90: 3ff1d1b7 lui gp,0x3ff1d +80014f94: d70a sw sp,172(sp) +80014f96: 0a3d70a3 0xa3d70a3 +80014f9a: 3d70a3d7 0x3d70a3d7 +80014f9e: d70a sw sp,172(sp) +80014fa0: 0a3d70a3 0xa3d70a3 +80014fa4: 3ff8a3d7 0x3ff8a3d7 +80014fa8: cccd beqz s1,80015062 <__mprec_tens+0x72> +80014faa: cccc sw a1,28(s1) +80014fac: cccc sw a1,28(s1) +80014fae: cccc sw a1,28(s1) +80014fb0: cccc sw a1,28(s1) +80014fb2: cccc sw a1,28(s1) +80014fb4: cccc sw a1,28(s1) +80014fb6: cccc sw a1,28(s1) +80014fb8: cccc sw a1,28(s1) +80014fba: 0xffff3ffb -80015090 : -80015090: ffff 0xffff -80015092: fffe fsw ft11,252(sp) -80015094: fffc fsw fa5,124(a5) -80015096: fff8 fsw fa4,124(a5) -80015098: fff0 fsw fa2,124(a5) -8001509a: ffe0 fsw fs0,124(a5) -8001509c: ffc0 fsw fs0,60(a5) -8001509e: ff80 fsw fs0,56(a5) -800150a0: ff00 fsw fs0,56(a4) -800150a2: fe00 fsw fs0,56(a2) -800150a4: fc00 fsw fs0,56(s0) -800150a6: f800 fsw fs0,48(s0) -800150a8: f000 fsw fs0,32(s0) -800150aa: e000 fsw fs0,0(s0) -800150ac: c000 sw s0,0(s0) -800150ae: 8000 0x8000 +80014fbc : +80014fbc: ffff 0xffff +80014fbe: fffe fsw ft11,252(sp) +80014fc0: fffc fsw fa5,124(a5) +80014fc2: fff8 fsw fa4,124(a5) +80014fc4: fff0 fsw fa2,124(a5) +80014fc6: ffe0 fsw fs0,124(a5) +80014fc8: ffc0 fsw fs0,60(a5) +80014fca: ff80 fsw fs0,56(a5) +80014fcc: ff00 fsw fs0,56(a4) +80014fce: fe00 fsw fs0,56(a2) +80014fd0: fc00 fsw fs0,56(s0) +80014fd2: f800 fsw fs0,48(s0) +80014fd4: f000 fsw fs0,32(s0) +80014fd6: e000 fsw fs0,0(s0) +80014fd8: c000 sw s0,0(s0) +80014fda: 8000 0x8000 +80014fdc: 0000 unimp ... -800150b8 : -800150b8: 0005 c.nop 1 -800150ba: 0000 unimp -800150bc: 0019 c.nop 6 -800150be: 0000 unimp -800150c0: 007d c.nop 31 -800150c2: 0000 unimp -800150c4: 0000 unimp +80014fe0 : +80014fe0: 0005 c.nop 1 +80014fe2: 0000 unimp +80014fe4: 0019 c.nop 6 +80014fe6: 0000 unimp +80014fe8: 007d c.nop 31 +80014fea: 0000 unimp +80014fec: 0000 unimp ... -800150c8 <__mprec_tens>: -800150c8: 0000 unimp -800150ca: 0000 unimp -800150cc: 0000 unimp -800150ce: 3ff0 fld fa2,248(a5) -800150d0: 0000 unimp -800150d2: 0000 unimp -800150d4: 0000 unimp -800150d6: 4024 lw s1,64(s0) -800150d8: 0000 unimp -800150da: 0000 unimp -800150dc: 0000 unimp -800150de: 4059 c.li zero,22 -800150e0: 0000 unimp -800150e2: 0000 unimp -800150e4: 4000 lw s0,0(s0) -800150e6: 0000408f 0x408f -800150ea: 0000 unimp -800150ec: 8800 0x8800 -800150ee: 000040c3 fmadd.s ft1,ft0,ft0,ft0,rmm -800150f2: 0000 unimp -800150f4: 6a00 flw fs0,16(a2) -800150f6: 40f8 lw a4,68(s1) -800150f8: 0000 unimp -800150fa: 0000 unimp -800150fc: 8480 0x8480 -800150fe: 412e lw sp,200(sp) -80015100: 0000 unimp -80015102: 0000 unimp -80015104: 12d0 addi a2,sp,356 -80015106: 00004163 bltz zero,80015108 <__mprec_tens+0x40> -8001510a: 0000 unimp -8001510c: d784 sw s1,40(a5) -8001510e: 00004197 auipc gp,0x4 -80015112: 0000 unimp -80015114: cd65 beqz a0,8001520c <__mprec_bigtens+0x54> -80015116: 41cd li gp,19 -80015118: 0000 unimp -8001511a: 2000 fld fs0,0(s0) -8001511c: a05f 4202 0000 0x4202a05f -80015122: e800 fsw fs0,16(s0) -80015124: 4876 lw a6,92(sp) -80015126: 00004237 lui tp,0x4 -8001512a: a200 fsd fs0,0(a2) -8001512c: 1a94 addi a3,sp,368 -8001512e: 426d li tp,27 -80015130: 0000 unimp -80015132: e540 fsw fs0,12(a0) -80015134: 309c fld fa5,32(s1) -80015136: 42a2 lw t0,8(sp) -80015138: 0000 unimp -8001513a: 1e90 addi a2,sp,880 -8001513c: bcc4 fsd fs1,184(s1) -8001513e: 42d6 lw t0,84(sp) -80015140: 0000 unimp -80015142: 2634 fld fa3,72(a2) -80015144: 6bf5 lui s7,0x1d -80015146: 430c lw a1,0(a4) -80015148: 8000 0x8000 -8001514a: 37e0 fld fs0,232(a5) -8001514c: c379 beqz a4,80015212 <__mprec_bigtens+0x5a> -8001514e: 4341 li t1,16 -80015150: a000 fsd fs0,0(s0) -80015152: 85d8 0x85d8 -80015154: 43763457 0x43763457 -80015158: c800 sw s0,16(s0) -8001515a: 674e flw fa4,208(sp) -8001515c: c16d beqz a0,8001523e <__mprec_bigtens+0x86> -8001515e: 3d0043ab 0x3d0043ab -80015162: 6091 lui ra,0x4 -80015164: 58e4 lw s1,116(s1) -80015166: 43e1 li t2,24 -80015168: 8c40 0x8c40 -8001516a: 78b5 lui a7,0xfffed -8001516c: af1d j 800158a2 <__clz_tab+0x56> -8001516e: 4415 li s0,5 -80015170: ef50 fsw fa2,28(a4) -80015172: d6e2 sw s8,108(sp) -80015174: 1ae4 addi s1,sp,380 -80015176: d592444b 0xd592444b -8001517a: 064d addi a2,a2,19 -8001517c: 4480f0cf 0x4480f0cf -80015180: 4af6 lw s5,92(sp) -80015182: c7e1 beqz a5,8001524a <__mprec_bigtens+0x92> -80015184: 2d02 fld fs10,0(sp) -80015186: 44b5 li s1,13 -80015188: 9db4 0x9db4 -8001518a: 79d9 lui s3,0xffff6 -8001518c: 44ea7843 0x44ea7843 +80014ff0 <__mprec_tens>: +80014ff0: 0000 unimp +80014ff2: 0000 unimp +80014ff4: 0000 unimp +80014ff6: 3ff0 fld fa2,248(a5) +80014ff8: 0000 unimp +80014ffa: 0000 unimp +80014ffc: 0000 unimp +80014ffe: 4024 lw s1,64(s0) +80015000: 0000 unimp +80015002: 0000 unimp +80015004: 0000 unimp +80015006: 4059 c.li zero,22 +80015008: 0000 unimp +8001500a: 0000 unimp +8001500c: 4000 lw s0,0(s0) +8001500e: 0000408f 0x408f +80015012: 0000 unimp +80015014: 8800 0x8800 +80015016: 000040c3 fmadd.s ft1,ft0,ft0,ft0,rmm +8001501a: 0000 unimp +8001501c: 6a00 flw fs0,16(a2) +8001501e: 40f8 lw a4,68(s1) +80015020: 0000 unimp +80015022: 0000 unimp +80015024: 8480 0x8480 +80015026: 412e lw sp,200(sp) +80015028: 0000 unimp +8001502a: 0000 unimp +8001502c: 12d0 addi a2,sp,356 +8001502e: 00004163 bltz zero,80015030 <__mprec_tens+0x40> +80015032: 0000 unimp +80015034: d784 sw s1,40(a5) +80015036: 00004197 auipc gp,0x4 +8001503a: 0000 unimp +8001503c: cd65 beqz a0,80015134 <__mprec_bigtens+0x54> +8001503e: 41cd li gp,19 +80015040: 0000 unimp +80015042: 2000 fld fs0,0(s0) +80015044: a05f 4202 0000 0x4202a05f +8001504a: e800 fsw fs0,16(s0) +8001504c: 4876 lw a6,92(sp) +8001504e: 00004237 lui tp,0x4 +80015052: a200 fsd fs0,0(a2) +80015054: 1a94 addi a3,sp,368 +80015056: 426d li tp,27 +80015058: 0000 unimp +8001505a: e540 fsw fs0,12(a0) +8001505c: 309c fld fa5,32(s1) +8001505e: 42a2 lw t0,8(sp) +80015060: 0000 unimp +80015062: 1e90 addi a2,sp,880 +80015064: bcc4 fsd fs1,184(s1) +80015066: 42d6 lw t0,84(sp) +80015068: 0000 unimp +8001506a: 2634 fld fa3,72(a2) +8001506c: 6bf5 lui s7,0x1d +8001506e: 430c lw a1,0(a4) +80015070: 8000 0x8000 +80015072: 37e0 fld fs0,232(a5) +80015074: c379 beqz a4,8001513a <__mprec_bigtens+0x5a> +80015076: 4341 li t1,16 +80015078: a000 fsd fs0,0(s0) +8001507a: 85d8 0x85d8 +8001507c: 43763457 0x43763457 +80015080: c800 sw s0,16(s0) +80015082: 674e flw fa4,208(sp) +80015084: c16d beqz a0,80015166 <__mprec_bigtens+0x86> +80015086: 3d0043ab 0x3d0043ab +8001508a: 6091 lui ra,0x4 +8001508c: 58e4 lw s1,116(s1) +8001508e: 43e1 li t2,24 +80015090: 8c40 0x8c40 +80015092: 78b5 lui a7,0xfffed +80015094: af1d j 800157ca <__clz_tab+0x56> +80015096: 4415 li s0,5 +80015098: ef50 fsw fa2,28(a4) +8001509a: d6e2 sw s8,108(sp) +8001509c: 1ae4 addi s1,sp,380 +8001509e: d592444b 0xd592444b +800150a2: 064d addi a2,a2,19 +800150a4: 4480f0cf 0x4480f0cf +800150a8: 4af6 lw s5,92(sp) +800150aa: c7e1 beqz a5,80015172 <__mprec_bigtens+0x92> +800150ac: 2d02 fld fs10,0(sp) +800150ae: 44b5 li s1,13 +800150b0: 9db4 0x9db4 +800150b2: 79d9 lui s3,0xffff6 +800150b4: 44ea7843 0x44ea7843 -80015190 <__mprec_tinytens>: -80015190: 89bc 0x89bc -80015192: 97d8 0x97d8 -80015194: d2b2 sw a2,100(sp) -80015196: 3c9c fld fa5,56(s1) -80015198: d5a8a733 0xd5a8a733 -8001519c: 3949f623 0x3949f623 -800151a0: a73d j 800158ce <__clz_tab+0x82> -800151a2: 44f4 lw a3,76(s1) -800151a4: 0ffd addi t6,t6,31 -800151a6: 32a5 jal 80014b0e <__clzsi2+0x146> -800151a8: 979d srai a5,a5,0x27 -800151aa: cf8c sw a1,24(a5) -800151ac: ba08 fsd fa0,48(a2) -800151ae: 6f43255b 0x6f43255b -800151b2: 64ac flw fa1,72(s1) -800151b4: 0628 addi a0,sp,776 -800151b6: 0ac8 addi a0,sp,340 +800150b8 <__mprec_tinytens>: +800150b8: 89bc 0x89bc +800150ba: 97d8 0x97d8 +800150bc: d2b2 sw a2,100(sp) +800150be: 3c9c fld fa5,56(s1) +800150c0: d5a8a733 0xd5a8a733 +800150c4: 3949f623 0x3949f623 +800150c8: a73d j 800157f6 <__clz_tab+0x82> +800150ca: 44f4 lw a3,76(s1) +800150cc: 0ffd addi t6,t6,31 +800150ce: 32a5 jal 80014a36 <__clzsi2+0x132> +800150d0: 979d srai a5,a5,0x27 +800150d2: cf8c sw a1,24(a5) +800150d4: ba08 fsd fa0,48(a2) +800150d6: 6f43255b 0x6f43255b +800150da: 64ac flw fa1,72(s1) +800150dc: 0628 addi a0,sp,776 +800150de: 0ac8 addi a0,sp,340 -800151b8 <__mprec_bigtens>: -800151b8: 8000 0x8000 -800151ba: 37e0 fld fs0,232(a5) -800151bc: c379 beqz a4,80015282 <__mprec_bigtens+0xca> -800151be: 4341 li t1,16 -800151c0: b5056e17 auipc t3,0xb5056 -800151c4: b8b5 j 80014a40 <__clzsi2+0x78> -800151c6: f9f54693 xori a3,a0,-97 -800151ca: 4f03e93f 1d324d38 0x1d324d384f03e93f -800151d2: f930 fsw fa2,112(a0) -800151d4: 7748 flw fa0,44(a4) -800151d6: 5a82 lw s5,32(sp) -800151d8: bf3c fsd fa5,120(a4) -800151da: 4fdd7f73 csrrci t5,0x4fd,26 -800151de: 7515 lui a0,0xfffe5 -800151e0: a620 fsd fs0,72(a2) +800150e0 <__mprec_bigtens>: +800150e0: 8000 0x8000 +800150e2: 37e0 fld fs0,232(a5) +800150e4: c379 beqz a4,800151aa <__mprec_bigtens+0xca> +800150e6: 4341 li t1,16 +800150e8: b5056e17 auipc t3,0xb5056 +800150ec: b8b5 j 80014968 <__clzsi2+0x64> +800150ee: f9f54693 xori a3,a0,-97 +800150f2: 4f03e93f 1d324d38 0x1d324d384f03e93f +800150fa: f930 fsw fa2,112(a0) +800150fc: 7748 flw fa0,44(a4) +800150fe: 5a82 lw s5,32(sp) +80015100: bf3c fsd fa5,120(a4) +80015102: 4fdd7f73 csrrci t5,0x4fd,26 +80015106: 7515 lui a0,0xfffe5 +80015108: a55c fsd fa5,136(a0) +8001510a: 8000 0x8000 +8001510c: 9b84 0x9b84 +8001510e: 8000 0x8000 +80015110: 9b84 0x9b84 +80015112: 8000 0x8000 +80015114: a550 fsd fa2,136(a0) +80015116: 8000 0x8000 +80015118: 9b84 0x9b84 +8001511a: 8000 0x8000 +8001511c: 9b84 0x9b84 +8001511e: 8000 0x8000 +80015120: 9b84 0x9b84 +80015122: 8000 0x8000 +80015124: 9d2c 0x9d2c +80015126: 8000 0x8000 +80015128: 9b84 0x9b84 +8001512a: 8000 0x8000 +8001512c: 9b84 0x9b84 +8001512e: 8000 0x8000 +80015130: a52c fsd fa1,72(a0) +80015132: 8000 0x8000 +80015134: a5c4 fsd fs1,136(a1) +80015136: 8000 0x8000 +80015138: 9b84 0x9b84 +8001513a: 8000 0x8000 +8001513c: a3a0 fsd fs0,64(a5) +8001513e: 8000 0x8000 +80015140: a580 fsd fs0,8(a1) +80015142: 8000 0x8000 +80015144: 9b84 0x9b84 +80015146: 8000 0x8000 +80015148: a574 fsd fa3,200(a0) +8001514a: 8000 0x8000 +8001514c: 9b54 0x9b54 +8001514e: 8000 0x8000 +80015150: 9b54 0x9b54 +80015152: 8000 0x8000 +80015154: 9b54 0x9b54 +80015156: 8000 0x8000 +80015158: 9b54 0x9b54 +8001515a: 8000 0x8000 +8001515c: 9b54 0x9b54 +8001515e: 8000 0x8000 +80015160: 9b54 0x9b54 +80015162: 8000 0x8000 +80015164: 9b54 0x9b54 +80015166: 8000 0x8000 +80015168: 9b54 0x9b54 +8001516a: 8000 0x8000 +8001516c: 9b54 0x9b54 +8001516e: 8000 0x8000 +80015170: 9b84 0x9b84 +80015172: 8000 0x8000 +80015174: 9b84 0x9b84 +80015176: 8000 0x8000 +80015178: 9b84 0x9b84 +8001517a: 8000 0x8000 +8001517c: 9b84 0x9b84 +8001517e: 8000 0x8000 +80015180: 9b84 0x9b84 +80015182: 8000 0x8000 +80015184: 9b84 0x9b84 +80015186: 8000 0x8000 +80015188: 9b84 0x9b84 +8001518a: 8000 0x8000 +8001518c: 9da8 0x9da8 +8001518e: 8000 0x8000 +80015190: 9b84 0x9b84 +80015192: 8000 0x8000 +80015194: a374 fsd fa3,192(a4) +80015196: 8000 0x8000 +80015198: a5d4 fsd fa3,136(a1) +8001519a: 8000 0x8000 +8001519c: 9da8 0x9da8 +8001519e: 8000 0x8000 +800151a0: 9da8 0x9da8 +800151a2: 8000 0x8000 +800151a4: 9da8 0x9da8 +800151a6: 8000 0x8000 +800151a8: 9b84 0x9b84 +800151aa: 8000 0x8000 +800151ac: 9b84 0x9b84 +800151ae: 8000 0x8000 +800151b0: 9b84 0x9b84 +800151b2: 8000 0x8000 +800151b4: 9b84 0x9b84 +800151b6: 8000 0x8000 +800151b8: a520 fsd fs0,72(a0) +800151ba: 8000 0x8000 +800151bc: 9b84 0x9b84 +800151be: 8000 0x8000 +800151c0: 9b84 0x9b84 +800151c2: 8000 0x8000 +800151c4: a4a0 fsd fs0,72(s1) +800151c6: 8000 0x8000 +800151c8: 9b84 0x9b84 +800151ca: 8000 0x8000 +800151cc: 9b84 0x9b84 +800151ce: 8000 0x8000 +800151d0: 9b84 0x9b84 +800151d2: 8000 0x8000 +800151d4: a2f0 fsd fa2,192(a3) +800151d6: 8000 0x8000 +800151d8: 9b84 0x9b84 +800151da: 8000 0x8000 +800151dc: a4ec fsd fa1,200(s1) +800151de: 8000 0x8000 +800151e0: 9b84 0x9b84 800151e2: 8000 0x8000 -800151e4: 9c48 0x9c48 +800151e4: 9b84 0x9b84 800151e6: 8000 0x8000 -800151e8: 9c48 0x9c48 +800151e8: af84 fsd fs1,24(a5) 800151ea: 8000 0x8000 -800151ec: a614 fsd fa3,8(a2) +800151ec: 9b84 0x9b84 800151ee: 8000 0x8000 -800151f0: 9c48 0x9c48 +800151f0: 9b84 0x9b84 800151f2: 8000 0x8000 -800151f4: 9c48 0x9c48 +800151f4: 9b84 0x9b84 800151f6: 8000 0x8000 -800151f8: 9c48 0x9c48 +800151f8: 9b84 0x9b84 800151fa: 8000 0x8000 -800151fc: 9df0 0x9df0 +800151fc: 9b84 0x9b84 800151fe: 8000 0x8000 -80015200: 9c48 0x9c48 +80015200: 9b84 0x9b84 80015202: 8000 0x8000 -80015204: 9c48 0x9c48 +80015204: 9b84 0x9b84 80015206: 8000 0x8000 -80015208: a5f0 fsd fa2,200(a1) +80015208: 9b84 0x9b84 8001520a: 8000 0x8000 -8001520c: a688 fsd fa0,8(a3) +8001520c: 9da8 0x9da8 8001520e: 8000 0x8000 -80015210: 9c48 0x9c48 +80015210: 9b84 0x9b84 80015212: 8000 0x8000 -80015214: a464 fsd fs1,200(s0) +80015214: a374 fsd fa3,192(a4) 80015216: 8000 0x8000 -80015218: a644 fsd fs1,136(a2) +80015218: ae2c fsd fa1,88(a2) 8001521a: 8000 0x8000 -8001521c: 9c48 0x9c48 +8001521c: 9da8 0x9da8 8001521e: 8000 0x8000 -80015220: a638 fsd fa4,72(a2) +80015220: 9da8 0x9da8 80015222: 8000 0x8000 -80015224: 9c18 0x9c18 +80015224: 9da8 0x9da8 80015226: 8000 0x8000 -80015228: 9c18 0x9c18 +80015228: a4d8 fsd fa4,136(s1) 8001522a: 8000 0x8000 -8001522c: 9c18 0x9c18 +8001522c: ae2c fsd fa1,88(a2) 8001522e: 8000 0x8000 -80015230: 9c18 0x9c18 +80015230: 9d70 0x9d70 80015232: 8000 0x8000 -80015234: 9c18 0x9c18 +80015234: 9b84 0x9b84 80015236: 8000 0x8000 -80015238: 9c18 0x9c18 +80015238: a3fc fsd fa5,192(a5) 8001523a: 8000 0x8000 -8001523c: 9c18 0x9c18 +8001523c: 9b84 0x9b84 8001523e: 8000 0x8000 -80015240: 9c18 0x9c18 +80015240: a3ac fsd fa1,64(a5) 80015242: 8000 0x8000 -80015244: 9c18 0x9c18 +80015244: af98 fsd fa4,24(a5) 80015246: 8000 0x8000 -80015248: 9c48 0x9c48 +80015248: a410 fsd fa2,8(s0) 8001524a: 8000 0x8000 -8001524c: 9c48 0x9c48 +8001524c: 9d70 0x9d70 8001524e: 8000 0x8000 -80015250: 9c48 0x9c48 +80015250: 9b84 0x9b84 80015252: 8000 0x8000 -80015254: 9c48 0x9c48 +80015254: a2f0 fsd fa2,192(a3) 80015256: 8000 0x8000 -80015258: 9c48 0x9c48 +80015258: 9d68 0x9d68 8001525a: 8000 0x8000 -8001525c: 9c48 0x9c48 +8001525c: aef8 fsd fa4,216(a3) 8001525e: 8000 0x8000 -80015260: 9c48 0x9c48 +80015260: 9b84 0x9b84 80015262: 8000 0x8000 -80015264: 9e6c 0x9e6c +80015264: 9b84 0x9b84 80015266: 8000 0x8000 -80015268: 9c48 0x9c48 +80015268: af04 fsd fs1,24(a4) 8001526a: 8000 0x8000 -8001526c: a438 fsd fa4,72(s0) +8001526c: 9b84 0x9b84 8001526e: 8000 0x8000 -80015270: a698 fsd fa4,8(a3) +80015270: 9d68 0x9d68 80015272: 8000 0x8000 -80015274: 9e6c 0x9e6c -80015276: 8000 0x8000 -80015278: 9e6c 0x9e6c -8001527a: 8000 0x8000 -8001527c: 9e6c 0x9e6c -8001527e: 8000 0x8000 -80015280: 9c48 0x9c48 -80015282: 8000 0x8000 -80015284: 9c48 0x9c48 -80015286: 8000 0x8000 -80015288: 9c48 0x9c48 -8001528a: 8000 0x8000 -8001528c: 9c48 0x9c48 -8001528e: 8000 0x8000 -80015290: a5e4 fsd fs1,200(a1) -80015292: 8000 0x8000 -80015294: 9c48 0x9c48 + +80015274 : +80015274: 2020 fld fs0,64(s0) +80015276: 2020 fld fs0,64(s0) +80015278: 2020 fld fs0,64(s0) +8001527a: 2020 fld fs0,64(s0) +8001527c: 2020 fld fs0,64(s0) +8001527e: 2020 fld fs0,64(s0) +80015280: 2020 fld fs0,64(s0) +80015282: 2020 fld fs0,64(s0) + +80015284 : +80015284: 3030 fld fa2,96(s0) +80015286: 3030 fld fa2,96(s0) +80015288: 3030 fld fa2,96(s0) +8001528a: 3030 fld fa2,96(s0) +8001528c: 3030 fld fa2,96(s0) +8001528e: 3030 fld fa2,96(s0) +80015290: 3030 fld fa2,96(s0) +80015292: 3030 fld fa2,96(s0) +80015294: cc7c sw a5,92(s0) 80015296: 8000 0x8000 -80015298: 9c48 0x9c48 +80015298: c6ec sw a1,76(a3) 8001529a: 8000 0x8000 -8001529c: a564 fsd fs1,200(a0) +8001529c: c6ec sw a1,76(a3) 8001529e: 8000 0x8000 -800152a0: 9c48 0x9c48 +800152a0: cc70 sw a2,92(s0) 800152a2: 8000 0x8000 -800152a4: 9c48 0x9c48 +800152a4: c6ec sw a1,76(a3) 800152a6: 8000 0x8000 -800152a8: 9c48 0x9c48 +800152a8: c6ec sw a1,76(a3) 800152aa: 8000 0x8000 -800152ac: a3b4 fsd fa3,64(a5) +800152ac: c6ec sw a1,76(a3) 800152ae: 8000 0x8000 -800152b0: 9c48 0x9c48 +800152b0: c8b4 sw a3,80(s1) 800152b2: 8000 0x8000 -800152b4: a5b0 fsd fa2,72(a1) +800152b4: c6ec sw a1,76(a3) 800152b6: 8000 0x8000 -800152b8: 9c48 0x9c48 +800152b8: c6ec sw a1,76(a3) 800152ba: 8000 0x8000 -800152bc: 9c48 0x9c48 +800152bc: cc44 sw s1,28(s0) 800152be: 8000 0x8000 -800152c0: b048 fsd fa0,160(s0) +800152c0: cca0 sw s0,88(s1) 800152c2: 8000 0x8000 -800152c4: 9c48 0x9c48 +800152c4: c6ec sw a1,76(a3) 800152c6: 8000 0x8000 -800152c8: 9c48 0x9c48 +800152c8: cc94 sw a3,24(s1) 800152ca: 8000 0x8000 -800152cc: 9c48 0x9c48 +800152cc: ccb0 sw a2,88(s1) 800152ce: 8000 0x8000 -800152d0: 9c48 0x9c48 +800152d0: c6ec sw a1,76(a3) 800152d2: 8000 0x8000 -800152d4: 9c48 0x9c48 +800152d4: cc38 sw a4,88(s0) 800152d6: 8000 0x8000 -800152d8: 9c48 0x9c48 +800152d8: c6b4 sw a3,72(a3) 800152da: 8000 0x8000 -800152dc: 9c48 0x9c48 +800152dc: c6b4 sw a3,72(a3) 800152de: 8000 0x8000 -800152e0: 9c48 0x9c48 +800152e0: c6b4 sw a3,72(a3) 800152e2: 8000 0x8000 -800152e4: 9e6c 0x9e6c +800152e4: c6b4 sw a3,72(a3) 800152e6: 8000 0x8000 -800152e8: 9c48 0x9c48 +800152e8: c6b4 sw a3,72(a3) 800152ea: 8000 0x8000 -800152ec: a438 fsd fa4,72(s0) +800152ec: c6b4 sw a3,72(a3) 800152ee: 8000 0x8000 -800152f0: aef0 fsd fa2,216(a3) +800152f0: c6b4 sw a3,72(a3) 800152f2: 8000 0x8000 -800152f4: 9e6c 0x9e6c +800152f4: c6b4 sw a3,72(a3) 800152f6: 8000 0x8000 -800152f8: 9e6c 0x9e6c +800152f8: c6b4 sw a3,72(a3) 800152fa: 8000 0x8000 -800152fc: 9e6c 0x9e6c +800152fc: c6ec sw a1,76(a3) 800152fe: 8000 0x8000 -80015300: a59c fsd fa5,8(a1) +80015300: c6ec sw a1,76(a3) 80015302: 8000 0x8000 -80015304: aef0 fsd fa2,216(a3) +80015304: c6ec sw a1,76(a3) 80015306: 8000 0x8000 -80015308: 9e34 0x9e34 +80015308: c6ec sw a1,76(a3) 8001530a: 8000 0x8000 -8001530c: 9c48 0x9c48 +8001530c: c6ec sw a1,76(a3) 8001530e: 8000 0x8000 -80015310: a4c0 fsd fs0,136(s1) +80015310: c6ec sw a1,76(a3) 80015312: 8000 0x8000 -80015314: 9c48 0x9c48 +80015314: c6ec sw a1,76(a3) 80015316: 8000 0x8000 -80015318: a470 fsd fa2,200(s0) +80015318: c6ec sw a1,76(a3) 8001531a: 8000 0x8000 -8001531c: b05c fsd fa5,160(s0) +8001531c: c6ec sw a1,76(a3) 8001531e: 8000 0x8000 -80015320: a4d4 fsd fa3,136(s1) +80015320: cb80 sw s0,16(a5) 80015322: 8000 0x8000 -80015324: 9e34 0x9e34 +80015324: c904 sw s1,16(a0) 80015326: 8000 0x8000 -80015328: 9c48 0x9c48 +80015328: c6ec sw a1,76(a3) 8001532a: 8000 0x8000 -8001532c: a3b4 fsd fa3,64(a5) +8001532c: c6ec sw a1,76(a3) 8001532e: 8000 0x8000 -80015330: 9e2c 0x9e2c +80015330: c6ec sw a1,76(a3) 80015332: 8000 0x8000 -80015334: afbc fsd fa5,88(a5) +80015334: c6ec sw a1,76(a3) 80015336: 8000 0x8000 -80015338: 9c48 0x9c48 +80015338: c6ec sw a1,76(a3) 8001533a: 8000 0x8000 -8001533c: 9c48 0x9c48 +8001533c: c6ec sw a1,76(a3) 8001533e: 8000 0x8000 -80015340: afc8 fsd fa0,152(a5) +80015340: c6ec sw a1,76(a3) 80015342: 8000 0x8000 -80015344: 9c48 0x9c48 +80015344: c6ec sw a1,76(a3) 80015346: 8000 0x8000 -80015348: 9e2c 0x9e2c +80015348: c6ec sw a1,76(a3) 8001534a: 8000 0x8000 - -8001534c : -8001534c: 2020 fld fs0,64(s0) -8001534e: 2020 fld fs0,64(s0) -80015350: 2020 fld fs0,64(s0) -80015352: 2020 fld fs0,64(s0) -80015354: 2020 fld fs0,64(s0) -80015356: 2020 fld fs0,64(s0) -80015358: 2020 fld fs0,64(s0) -8001535a: 2020 fld fs0,64(s0) - -8001535c : -8001535c: 3030 fld fa2,96(s0) -8001535e: 3030 fld fa2,96(s0) -80015360: 3030 fld fa2,96(s0) -80015362: 3030 fld fa2,96(s0) -80015364: 3030 fld fa2,96(s0) -80015366: 3030 fld fa2,96(s0) -80015368: 3030 fld fa2,96(s0) -8001536a: 3030 fld fa2,96(s0) -8001536c: cd40 sw s0,28(a0) +8001534c: c6ec sw a1,76(a3) +8001534e: 8000 0x8000 +80015350: c9cc sw a1,20(a1) +80015352: 8000 0x8000 +80015354: c6ec sw a1,76(a3) +80015356: 8000 0x8000 +80015358: c6ec sw a1,76(a3) +8001535a: 8000 0x8000 +8001535c: c6ec sw a1,76(a3) +8001535e: 8000 0x8000 +80015360: cb40 sw s0,20(a4) +80015362: 8000 0x8000 +80015364: c6ec sw a1,76(a3) +80015366: 8000 0x8000 +80015368: cc08 sw a0,24(s0) +8001536a: 8000 0x8000 +8001536c: c6ec sw a1,76(a3) 8001536e: 8000 0x8000 -80015370: c7b0 sw a2,72(a5) +80015370: c6ec sw a1,76(a3) 80015372: 8000 0x8000 -80015374: c7b0 sw a2,72(a5) +80015374: d3f8 sw a4,100(a5) 80015376: 8000 0x8000 -80015378: cd34 sw a3,88(a0) +80015378: c6ec sw a1,76(a3) 8001537a: 8000 0x8000 -8001537c: c7b0 sw a2,72(a5) +8001537c: c6ec sw a1,76(a3) 8001537e: 8000 0x8000 -80015380: c7b0 sw a2,72(a5) +80015380: c6ec sw a1,76(a3) 80015382: 8000 0x8000 -80015384: c7b0 sw a2,72(a5) +80015384: c6ec sw a1,76(a3) 80015386: 8000 0x8000 -80015388: c978 sw a4,84(a0) +80015388: c6ec sw a1,76(a3) 8001538a: 8000 0x8000 -8001538c: c7b0 sw a2,72(a5) +8001538c: c6ec sw a1,76(a3) 8001538e: 8000 0x8000 -80015390: c7b0 sw a2,72(a5) +80015390: c6ec sw a1,76(a3) 80015392: 8000 0x8000 -80015394: cd08 sw a0,24(a0) +80015394: c6ec sw a1,76(a3) 80015396: 8000 0x8000 -80015398: cd64 sw s1,92(a0) +80015398: c6ec sw a1,76(a3) 8001539a: 8000 0x8000 -8001539c: c7b0 sw a2,72(a5) +8001539c: c6ec sw a1,76(a3) 8001539e: 8000 0x8000 -800153a0: cd58 sw a4,28(a0) +800153a0: cb80 sw s0,16(a5) 800153a2: 8000 0x8000 -800153a4: cd74 sw a3,92(a0) +800153a4: c908 sw a0,16(a0) 800153a6: 8000 0x8000 -800153a8: c7b0 sw a2,72(a5) +800153a8: c6ec sw a1,76(a3) 800153aa: 8000 0x8000 -800153ac: ccfc sw a5,92(s1) +800153ac: c6ec sw a1,76(a3) 800153ae: 8000 0x8000 -800153b0: c778 sw a4,76(a4) +800153b0: c6ec sw a1,76(a3) 800153b2: 8000 0x8000 -800153b4: c778 sw a4,76(a4) +800153b4: cbf4 sw a3,84(a5) 800153b6: 8000 0x8000 -800153b8: c778 sw a4,76(a4) +800153b8: c908 sw a0,16(a0) 800153ba: 8000 0x8000 -800153bc: c778 sw a4,76(a4) +800153bc: c8f8 sw a4,84(s1) 800153be: 8000 0x8000 -800153c0: c778 sw a4,76(a4) +800153c0: c6ec sw a1,76(a3) 800153c2: 8000 0x8000 -800153c4: c778 sw a4,76(a4) +800153c4: cbe0 sw s0,84(a5) 800153c6: 8000 0x8000 -800153c8: c778 sw a4,76(a4) +800153c8: c6ec sw a1,76(a3) 800153ca: 8000 0x8000 -800153cc: c778 sw a4,76(a4) +800153cc: ccf0 sw a2,92(s1) 800153ce: 8000 0x8000 -800153d0: c778 sw a4,76(a4) +800153d0: c9d0 sw a2,20(a1) 800153d2: 8000 0x8000 -800153d4: c7b0 sw a2,72(a5) +800153d4: cba8 sw a0,80(a5) 800153d6: 8000 0x8000 -800153d8: c7b0 sw a2,72(a5) +800153d8: c8f8 sw a4,84(s1) 800153da: 8000 0x8000 -800153dc: c7b0 sw a2,72(a5) +800153dc: c6ec sw a1,76(a3) 800153de: 8000 0x8000 -800153e0: c7b0 sw a2,72(a5) +800153e0: cb40 sw s0,20(a4) 800153e2: 8000 0x8000 -800153e4: c7b0 sw a2,72(a5) +800153e4: c8f0 sw a2,84(s1) 800153e6: 8000 0x8000 -800153e8: c7b0 sw a2,72(a5) +800153e8: d3f0 sw a2,100(a5) 800153ea: 8000 0x8000 -800153ec: c7b0 sw a2,72(a5) +800153ec: c6ec sw a1,76(a3) 800153ee: 8000 0x8000 -800153f0: c7b0 sw a2,72(a5) +800153f0: c6ec sw a1,76(a3) 800153f2: 8000 0x8000 -800153f4: c7b0 sw a2,72(a5) +800153f4: d454 sw a3,44(s0) 800153f6: 8000 0x8000 -800153f8: cc44 sw s1,28(s0) +800153f8: c6ec sw a1,76(a3) 800153fa: 8000 0x8000 -800153fc: c9c8 sw a0,20(a1) +800153fc: c8f0 sw a2,84(s1) 800153fe: 8000 0x8000 -80015400: c7b0 sw a2,72(a5) -80015402: 8000 0x8000 -80015404: c7b0 sw a2,72(a5) -80015406: 8000 0x8000 -80015408: c7b0 sw a2,72(a5) -8001540a: 8000 0x8000 -8001540c: c7b0 sw a2,72(a5) -8001540e: 8000 0x8000 -80015410: c7b0 sw a2,72(a5) -80015412: 8000 0x8000 -80015414: c7b0 sw a2,72(a5) -80015416: 8000 0x8000 -80015418: c7b0 sw a2,72(a5) -8001541a: 8000 0x8000 -8001541c: c7b0 sw a2,72(a5) -8001541e: 8000 0x8000 -80015420: c7b0 sw a2,72(a5) -80015422: 8000 0x8000 -80015424: c7b0 sw a2,72(a5) -80015426: 8000 0x8000 -80015428: ca90 sw a2,16(a3) -8001542a: 8000 0x8000 -8001542c: c7b0 sw a2,72(a5) -8001542e: 8000 0x8000 -80015430: c7b0 sw a2,72(a5) + +80015400 : +80015400: 2020 fld fs0,64(s0) +80015402: 2020 fld fs0,64(s0) +80015404: 2020 fld fs0,64(s0) +80015406: 2020 fld fs0,64(s0) +80015408: 2020 fld fs0,64(s0) +8001540a: 2020 fld fs0,64(s0) +8001540c: 2020 fld fs0,64(s0) +8001540e: 2020 fld fs0,64(s0) + +80015410 : +80015410: 3030 fld fa2,96(s0) +80015412: 3030 fld fa2,96(s0) +80015414: 3030 fld fa2,96(s0) +80015416: 3030 fld fa2,96(s0) +80015418: 3030 fld fa2,96(s0) +8001541a: 3030 fld fa2,96(s0) +8001541c: 3030 fld fa2,96(s0) +8001541e: 3030 fld fa2,96(s0) +80015420: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne +80015424: 4f50 lw a2,28(a4) +80015426: 00584953 fadd.s fs2,fa6,ft5,rmm +8001542a: 0000 unimp +8001542c: 002e c.slli zero,0xb +8001542e: 0000 unimp +80015430: f750 fsw fa2,44(a4) 80015432: 8000 0x8000 -80015434: c7b0 sw a2,72(a5) +80015434: f200 fsw fs0,32(a2) 80015436: 8000 0x8000 -80015438: cc04 sw s1,24(s0) +80015438: f200 fsw fs0,32(a2) 8001543a: 8000 0x8000 -8001543c: c7b0 sw a2,72(a5) +8001543c: f744 fsw fs1,44(a4) 8001543e: 8000 0x8000 -80015440: cccc sw a1,28(s1) +80015440: f200 fsw fs0,32(a2) 80015442: 8000 0x8000 -80015444: c7b0 sw a2,72(a5) +80015444: f200 fsw fs0,32(a2) 80015446: 8000 0x8000 -80015448: c7b0 sw a2,72(a5) +80015448: f200 fsw fs0,32(a2) 8001544a: 8000 0x8000 -8001544c: d4bc sw a5,104(s1) +8001544c: f388 fsw fa0,32(a5) 8001544e: 8000 0x8000 -80015450: c7b0 sw a2,72(a5) +80015450: f200 fsw fs0,32(a2) 80015452: 8000 0x8000 -80015454: c7b0 sw a2,72(a5) +80015454: f200 fsw fs0,32(a2) 80015456: 8000 0x8000 -80015458: c7b0 sw a2,72(a5) +80015458: f718 fsw fa4,40(a4) 8001545a: 8000 0x8000 -8001545c: c7b0 sw a2,72(a5) +8001545c: f708 fsw fa0,40(a4) 8001545e: 8000 0x8000 -80015460: c7b0 sw a2,72(a5) +80015460: f200 fsw fs0,32(a2) 80015462: 8000 0x8000 -80015464: c7b0 sw a2,72(a5) +80015464: f6fc fsw fa5,108(a3) 80015466: 8000 0x8000 -80015468: c7b0 sw a2,72(a5) +80015468: f6bc fsw fa5,104(a3) 8001546a: 8000 0x8000 -8001546c: c7b0 sw a2,72(a5) +8001546c: f200 fsw fs0,32(a2) 8001546e: 8000 0x8000 -80015470: c7b0 sw a2,72(a5) +80015470: f6b0 fsw fa2,104(a3) 80015472: 8000 0x8000 -80015474: c7b0 sw a2,72(a5) +80015474: f1c8 fsw fa0,36(a1) 80015476: 8000 0x8000 -80015478: cc44 sw s1,28(s0) +80015478: f1c8 fsw fa0,36(a1) 8001547a: 8000 0x8000 -8001547c: c9cc sw a1,20(a1) +8001547c: f1c8 fsw fa0,36(a1) 8001547e: 8000 0x8000 -80015480: c7b0 sw a2,72(a5) +80015480: f1c8 fsw fa0,36(a1) 80015482: 8000 0x8000 -80015484: c7b0 sw a2,72(a5) +80015484: f1c8 fsw fa0,36(a1) 80015486: 8000 0x8000 -80015488: c7b0 sw a2,72(a5) +80015488: f1c8 fsw fa0,36(a1) 8001548a: 8000 0x8000 -8001548c: ccb8 sw a4,88(s1) +8001548c: f1c8 fsw fa0,36(a1) 8001548e: 8000 0x8000 -80015490: c9cc sw a1,20(a1) +80015490: f1c8 fsw fa0,36(a1) 80015492: 8000 0x8000 -80015494: c9bc sw a5,80(a1) +80015494: f1c8 fsw fa0,36(a1) 80015496: 8000 0x8000 -80015498: c7b0 sw a2,72(a5) +80015498: f200 fsw fs0,32(a2) 8001549a: 8000 0x8000 -8001549c: cca4 sw s1,88(s1) +8001549c: f200 fsw fs0,32(a2) 8001549e: 8000 0x8000 -800154a0: c7b0 sw a2,72(a5) +800154a0: f200 fsw fs0,32(a2) 800154a2: 8000 0x8000 -800154a4: cdb4 sw a3,88(a1) +800154a4: f200 fsw fs0,32(a2) 800154a6: 8000 0x8000 -800154a8: ca94 sw a3,16(a3) +800154a8: f200 fsw fs0,32(a2) 800154aa: 8000 0x8000 -800154ac: cc6c sw a1,92(s0) +800154ac: f200 fsw fs0,32(a2) 800154ae: 8000 0x8000 -800154b0: c9bc sw a5,80(a1) +800154b0: f200 fsw fs0,32(a2) 800154b2: 8000 0x8000 -800154b4: c7b0 sw a2,72(a5) +800154b4: f200 fsw fs0,32(a2) 800154b6: 8000 0x8000 -800154b8: cc04 sw s1,24(s0) +800154b8: f200 fsw fs0,32(a2) 800154ba: 8000 0x8000 -800154bc: c9b4 sw a3,80(a1) +800154bc: f450 fsw fa2,44(s0) 800154be: 8000 0x8000 -800154c0: d4b4 sw a3,104(s1) +800154c0: f56c fsw fa1,108(a0) 800154c2: 8000 0x8000 -800154c4: c7b0 sw a2,72(a5) +800154c4: f200 fsw fs0,32(a2) 800154c6: 8000 0x8000 -800154c8: c7b0 sw a2,72(a5) +800154c8: f200 fsw fs0,32(a2) 800154ca: 8000 0x8000 -800154cc: d518 sw a4,40(a0) +800154cc: f200 fsw fs0,32(a2) 800154ce: 8000 0x8000 -800154d0: c7b0 sw a2,72(a5) +800154d0: f200 fsw fs0,32(a2) 800154d2: 8000 0x8000 -800154d4: c9b4 sw a3,80(a1) +800154d4: f200 fsw fs0,32(a2) 800154d6: 8000 0x8000 - -800154d8 : -800154d8: 2020 fld fs0,64(s0) -800154da: 2020 fld fs0,64(s0) -800154dc: 2020 fld fs0,64(s0) -800154de: 2020 fld fs0,64(s0) -800154e0: 2020 fld fs0,64(s0) -800154e2: 2020 fld fs0,64(s0) -800154e4: 2020 fld fs0,64(s0) -800154e6: 2020 fld fs0,64(s0) - -800154e8 : -800154e8: 3030 fld fa2,96(s0) -800154ea: 3030 fld fa2,96(s0) -800154ec: 3030 fld fa2,96(s0) -800154ee: 3030 fld fa2,96(s0) -800154f0: 3030 fld fa2,96(s0) -800154f2: 3030 fld fa2,96(s0) -800154f4: 3030 fld fa2,96(s0) -800154f6: 3030 fld fa2,96(s0) -800154f8: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne -800154fc: 4f50 lw a2,28(a4) -800154fe: 00584953 fadd.s fs2,fa6,ft5,rmm -80015502: 0000 unimp -80015504: 002e c.slli zero,0xb -80015506: 0000 unimp -80015508: f814 fsw fa3,48(s0) +800154d8: f200 fsw fs0,32(a2) +800154da: 8000 0x8000 +800154dc: f200 fsw fs0,32(a2) +800154de: 8000 0x8000 +800154e0: f200 fsw fs0,32(a2) +800154e2: 8000 0x8000 +800154e4: f200 fsw fs0,32(a2) +800154e6: 8000 0x8000 +800154e8: f200 fsw fs0,32(a2) +800154ea: 8000 0x8000 +800154ec: f4fc fsw fa5,108(s1) +800154ee: 8000 0x8000 +800154f0: f200 fsw fs0,32(a2) +800154f2: 8000 0x8000 +800154f4: f200 fsw fs0,32(a2) +800154f6: 8000 0x8000 +800154f8: f200 fsw fs0,32(a2) +800154fa: 8000 0x8000 +800154fc: f404 fsw fs1,40(s0) +800154fe: 8000 0x8000 +80015500: f200 fsw fs0,32(a2) +80015502: 8000 0x8000 +80015504: f640 fsw fs0,44(a2) +80015506: 8000 0x8000 +80015508: f200 fsw fs0,32(a2) 8001550a: 8000 0x8000 -8001550c: f2c4 fsw fs1,36(a3) +8001550c: f200 fsw fs0,32(a2) 8001550e: 8000 0x8000 -80015510: f2c4 fsw fs1,36(a3) +80015510: fdf0 fsw fa2,124(a1) 80015512: 8000 0x8000 -80015514: f808 fsw fa0,48(s0) +80015514: f200 fsw fs0,32(a2) 80015516: 8000 0x8000 -80015518: f2c4 fsw fs1,36(a3) +80015518: f200 fsw fs0,32(a2) 8001551a: 8000 0x8000 -8001551c: f2c4 fsw fs1,36(a3) +8001551c: f200 fsw fs0,32(a2) 8001551e: 8000 0x8000 -80015520: f2c4 fsw fs1,36(a3) +80015520: f200 fsw fs0,32(a2) 80015522: 8000 0x8000 -80015524: f44c fsw fa1,44(s0) +80015524: f200 fsw fs0,32(a2) 80015526: 8000 0x8000 -80015528: f2c4 fsw fs1,36(a3) +80015528: f200 fsw fs0,32(a2) 8001552a: 8000 0x8000 -8001552c: f2c4 fsw fs1,36(a3) +8001552c: f200 fsw fs0,32(a2) 8001552e: 8000 0x8000 -80015530: f7dc fsw fa5,44(a5) +80015530: f200 fsw fs0,32(a2) 80015532: 8000 0x8000 -80015534: f7cc fsw fa1,44(a5) +80015534: f200 fsw fs0,32(a2) 80015536: 8000 0x8000 -80015538: f2c4 fsw fs1,36(a3) +80015538: f200 fsw fs0,32(a2) 8001553a: 8000 0x8000 -8001553c: f7c0 fsw fs0,44(a5) +8001553c: f450 fsw fa2,44(s0) 8001553e: 8000 0x8000 -80015540: f780 fsw fs0,40(a5) +80015540: f478 fsw fa4,108(s0) 80015542: 8000 0x8000 -80015544: f2c4 fsw fs1,36(a3) +80015544: f200 fsw fs0,32(a2) 80015546: 8000 0x8000 -80015548: f774 fsw fa3,108(a4) +80015548: f200 fsw fs0,32(a2) 8001554a: 8000 0x8000 -8001554c: f28c fsw fa1,32(a3) +8001554c: f200 fsw fs0,32(a2) 8001554e: 8000 0x8000 -80015550: f28c fsw fa1,32(a3) +80015550: f768 fsw fa0,108(a4) 80015552: 8000 0x8000 -80015554: f28c fsw fa1,32(a3) +80015554: f478 fsw fa4,108(s0) 80015556: 8000 0x8000 -80015558: f28c fsw fa1,32(a3) +80015558: f3cc fsw fa1,36(a5) 8001555a: 8000 0x8000 -8001555c: f28c fsw fa1,32(a3) +8001555c: f200 fsw fs0,32(a2) 8001555e: 8000 0x8000 -80015560: f28c fsw fa1,32(a3) +80015560: f7b8 fsw fa4,104(a5) 80015562: 8000 0x8000 -80015564: f28c fsw fa1,32(a3) +80015564: f200 fsw fs0,32(a2) 80015566: 8000 0x8000 -80015568: f28c fsw fa1,32(a3) +80015568: f77c fsw fa5,108(a4) 8001556a: 8000 0x8000 -8001556c: f28c fsw fa1,32(a3) +8001556c: fe5c fsw fa5,60(a2) 8001556e: 8000 0x8000 -80015570: f2c4 fsw fs1,36(a3) +80015570: f674 fsw fa3,108(a2) 80015572: 8000 0x8000 -80015574: f2c4 fsw fs1,36(a3) +80015574: f3cc fsw fa1,36(a5) 80015576: 8000 0x8000 -80015578: f2c4 fsw fs1,36(a3) +80015578: f200 fsw fs0,32(a2) 8001557a: 8000 0x8000 -8001557c: f2c4 fsw fs1,36(a3) +8001557c: f404 fsw fs1,40(s0) 8001557e: 8000 0x8000 -80015580: f2c4 fsw fs1,36(a3) +80015580: f3c4 fsw fs1,36(a5) 80015582: 8000 0x8000 -80015584: f2c4 fsw fs1,36(a3) +80015584: fe50 fsw fa2,60(a2) 80015586: 8000 0x8000 -80015588: f2c4 fsw fs1,36(a3) +80015588: f200 fsw fs0,32(a2) 8001558a: 8000 0x8000 -8001558c: f2c4 fsw fs1,36(a3) +8001558c: f200 fsw fs0,32(a2) 8001558e: 8000 0x8000 -80015590: f2c4 fsw fs1,36(a3) +80015590: fe64 fsw fs1,124(a2) 80015592: 8000 0x8000 -80015594: f514 fsw fa3,40(a0) +80015594: f200 fsw fs0,32(a2) 80015596: 8000 0x8000 -80015598: f630 fsw fa2,104(a2) +80015598: f3c4 fsw fs1,36(a5) 8001559a: 8000 0x8000 -8001559c: f2c4 fsw fs1,36(a3) -8001559e: 8000 0x8000 -800155a0: f2c4 fsw fs1,36(a3) -800155a2: 8000 0x8000 -800155a4: f2c4 fsw fs1,36(a3) -800155a6: 8000 0x8000 -800155a8: f2c4 fsw fs1,36(a3) -800155aa: 8000 0x8000 -800155ac: f2c4 fsw fs1,36(a3) -800155ae: 8000 0x8000 -800155b0: f2c4 fsw fs1,36(a3) -800155b2: 8000 0x8000 -800155b4: f2c4 fsw fs1,36(a3) -800155b6: 8000 0x8000 -800155b8: f2c4 fsw fs1,36(a3) -800155ba: 8000 0x8000 -800155bc: f2c4 fsw fs1,36(a3) -800155be: 8000 0x8000 -800155c0: f2c4 fsw fs1,36(a3) -800155c2: 8000 0x8000 -800155c4: f5c0 fsw fs0,44(a1) -800155c6: 8000 0x8000 -800155c8: f2c4 fsw fs1,36(a3) -800155ca: 8000 0x8000 -800155cc: f2c4 fsw fs1,36(a3) -800155ce: 8000 0x8000 -800155d0: f2c4 fsw fs1,36(a3) -800155d2: 8000 0x8000 -800155d4: f4c8 fsw fa0,44(s1) -800155d6: 8000 0x8000 -800155d8: f2c4 fsw fs1,36(a3) -800155da: 8000 0x8000 -800155dc: f704 fsw fs1,40(a4) -800155de: 8000 0x8000 -800155e0: f2c4 fsw fs1,36(a3) -800155e2: 8000 0x8000 -800155e4: f2c4 fsw fs1,36(a3) -800155e6: 8000 0x8000 -800155e8: feb4 fsw fa3,120(a3) -800155ea: 8000 0x8000 -800155ec: f2c4 fsw fs1,36(a3) -800155ee: 8000 0x8000 -800155f0: f2c4 fsw fs1,36(a3) -800155f2: 8000 0x8000 -800155f4: f2c4 fsw fs1,36(a3) -800155f6: 8000 0x8000 -800155f8: f2c4 fsw fs1,36(a3) -800155fa: 8000 0x8000 -800155fc: f2c4 fsw fs1,36(a3) -800155fe: 8000 0x8000 -80015600: f2c4 fsw fs1,36(a3) -80015602: 8000 0x8000 -80015604: f2c4 fsw fs1,36(a3) -80015606: 8000 0x8000 -80015608: f2c4 fsw fs1,36(a3) -8001560a: 8000 0x8000 -8001560c: f2c4 fsw fs1,36(a3) -8001560e: 8000 0x8000 -80015610: f2c4 fsw fs1,36(a3) -80015612: 8000 0x8000 -80015614: f514 fsw fa3,40(a0) -80015616: 8000 0x8000 -80015618: f53c fsw fa5,104(a0) -8001561a: 8000 0x8000 -8001561c: f2c4 fsw fs1,36(a3) -8001561e: 8000 0x8000 -80015620: f2c4 fsw fs1,36(a3) -80015622: 8000 0x8000 -80015624: f2c4 fsw fs1,36(a3) -80015626: 8000 0x8000 -80015628: f82c fsw fa1,112(s0) -8001562a: 8000 0x8000 -8001562c: f53c fsw fa5,104(a0) -8001562e: 8000 0x8000 -80015630: f490 fsw fa2,40(s1) -80015632: 8000 0x8000 -80015634: f2c4 fsw fs1,36(a3) -80015636: 8000 0x8000 -80015638: f87c fsw fa5,116(s0) -8001563a: 8000 0x8000 -8001563c: f2c4 fsw fs1,36(a3) -8001563e: 8000 0x8000 -80015640: f840 fsw fs0,52(s0) -80015642: 8000 0x8000 -80015644: ff20 fsw fs0,120(a4) -80015646: 8000 0x8000 -80015648: f738 fsw fa4,104(a4) -8001564a: 8000 0x8000 -8001564c: f490 fsw fa2,40(s1) -8001564e: 8000 0x8000 -80015650: f2c4 fsw fs1,36(a3) -80015652: 8000 0x8000 -80015654: f4c8 fsw fa0,44(s1) -80015656: 8000 0x8000 -80015658: f488 fsw fa0,40(s1) -8001565a: 8000 0x8000 -8001565c: ff14 fsw fa3,56(a4) -8001565e: 8000 0x8000 -80015660: f2c4 fsw fs1,36(a3) -80015662: 8000 0x8000 -80015664: f2c4 fsw fs1,36(a3) -80015666: 8000 0x8000 -80015668: ff28 fsw fa0,120(a4) -8001566a: 8000 0x8000 -8001566c: f2c4 fsw fs1,36(a3) -8001566e: 8000 0x8000 -80015670: f488 fsw fa0,40(s1) -80015672: 8000 0x8000 -80015674 : -80015674: 2020 fld fs0,64(s0) -80015676: 2020 fld fs0,64(s0) -80015678: 2020 fld fs0,64(s0) -8001567a: 2020 fld fs0,64(s0) -8001567c: 2020 fld fs0,64(s0) -8001567e: 2020 fld fs0,64(s0) -80015680: 2020 fld fs0,64(s0) -80015682: 2020 fld fs0,64(s0) +8001559c : +8001559c: 2020 fld fs0,64(s0) +8001559e: 2020 fld fs0,64(s0) +800155a0: 2020 fld fs0,64(s0) +800155a2: 2020 fld fs0,64(s0) +800155a4: 2020 fld fs0,64(s0) +800155a6: 2020 fld fs0,64(s0) +800155a8: 2020 fld fs0,64(s0) +800155aa: 2020 fld fs0,64(s0) -80015684 : -80015684: 3030 fld fa2,96(s0) -80015686: 3030 fld fa2,96(s0) -80015688: 3030 fld fa2,96(s0) -8001568a: 3030 fld fa2,96(s0) -8001568c: 3030 fld fa2,96(s0) -8001568e: 3030 fld fa2,96(s0) -80015690: 3030 fld fa2,96(s0) -80015692: 3030 fld fa2,96(s0) +800155ac : +800155ac: 3030 fld fa2,96(s0) +800155ae: 3030 fld fa2,96(s0) +800155b0: 3030 fld fa2,96(s0) +800155b2: 3030 fld fa2,96(s0) +800155b4: 3030 fld fa2,96(s0) +800155b6: 3030 fld fa2,96(s0) +800155b8: 3030 fld fa2,96(s0) +800155ba: 3030 fld fa2,96(s0) -80015694 <_ctype_>: -80015694: 2000 fld fs0,0(s0) -80015696: 2020 fld fs0,64(s0) -80015698: 2020 fld fs0,64(s0) -8001569a: 2020 fld fs0,64(s0) -8001569c: 2020 fld fs0,64(s0) -8001569e: 2828 fld fa0,80(s0) -800156a0: 2828 fld fa0,80(s0) -800156a2: 2028 fld fa0,64(s0) -800156a4: 2020 fld fs0,64(s0) -800156a6: 2020 fld fs0,64(s0) -800156a8: 2020 fld fs0,64(s0) -800156aa: 2020 fld fs0,64(s0) -800156ac: 2020 fld fs0,64(s0) -800156ae: 2020 fld fs0,64(s0) -800156b0: 2020 fld fs0,64(s0) -800156b2: 2020 fld fs0,64(s0) -800156b4: 8820 0x8820 -800156b6: 1010 addi a2,sp,32 -800156b8: 1010 addi a2,sp,32 -800156ba: 1010 addi a2,sp,32 -800156bc: 1010 addi a2,sp,32 -800156be: 1010 addi a2,sp,32 -800156c0: 1010 addi a2,sp,32 -800156c2: 1010 addi a2,sp,32 -800156c4: 0410 addi a2,sp,512 -800156c6: 0404 addi s1,sp,512 -800156c8: 0404 addi s1,sp,512 -800156ca: 0404 addi s1,sp,512 -800156cc: 0404 addi s1,sp,512 -800156ce: 1004 addi s1,sp,32 -800156d0: 1010 addi a2,sp,32 -800156d2: 1010 addi a2,sp,32 -800156d4: 1010 addi a2,sp,32 -800156d6: 4141 li sp,16 -800156d8: 4141 li sp,16 -800156da: 4141 li sp,16 -800156dc: 0101 addi sp,sp,0 -800156de: 0101 addi sp,sp,0 -800156e0: 0101 addi sp,sp,0 -800156e2: 0101 addi sp,sp,0 -800156e4: 0101 addi sp,sp,0 -800156e6: 0101 addi sp,sp,0 -800156e8: 0101 addi sp,sp,0 -800156ea: 0101 addi sp,sp,0 -800156ec: 0101 addi sp,sp,0 -800156ee: 0101 addi sp,sp,0 -800156f0: 1010 addi a2,sp,32 -800156f2: 1010 addi a2,sp,32 -800156f4: 1010 addi a2,sp,32 -800156f6: 4242 lw tp,16(sp) -800156f8: 4242 lw tp,16(sp) -800156fa: 4242 lw tp,16(sp) -800156fc: 0202 c.slli64 tp -800156fe: 0202 c.slli64 tp -80015700: 0202 c.slli64 tp -80015702: 0202 c.slli64 tp -80015704: 0202 c.slli64 tp -80015706: 0202 c.slli64 tp -80015708: 0202 c.slli64 tp -8001570a: 0202 c.slli64 tp -8001570c: 0202 c.slli64 tp -8001570e: 0202 c.slli64 tp -80015710: 1010 addi a2,sp,32 -80015712: 1010 addi a2,sp,32 -80015714: 0020 addi s0,sp,8 +800155bc <_ctype_>: +800155bc: 2000 fld fs0,0(s0) +800155be: 2020 fld fs0,64(s0) +800155c0: 2020 fld fs0,64(s0) +800155c2: 2020 fld fs0,64(s0) +800155c4: 2020 fld fs0,64(s0) +800155c6: 2828 fld fa0,80(s0) +800155c8: 2828 fld fa0,80(s0) +800155ca: 2028 fld fa0,64(s0) +800155cc: 2020 fld fs0,64(s0) +800155ce: 2020 fld fs0,64(s0) +800155d0: 2020 fld fs0,64(s0) +800155d2: 2020 fld fs0,64(s0) +800155d4: 2020 fld fs0,64(s0) +800155d6: 2020 fld fs0,64(s0) +800155d8: 2020 fld fs0,64(s0) +800155da: 2020 fld fs0,64(s0) +800155dc: 8820 0x8820 +800155de: 1010 addi a2,sp,32 +800155e0: 1010 addi a2,sp,32 +800155e2: 1010 addi a2,sp,32 +800155e4: 1010 addi a2,sp,32 +800155e6: 1010 addi a2,sp,32 +800155e8: 1010 addi a2,sp,32 +800155ea: 1010 addi a2,sp,32 +800155ec: 0410 addi a2,sp,512 +800155ee: 0404 addi s1,sp,512 +800155f0: 0404 addi s1,sp,512 +800155f2: 0404 addi s1,sp,512 +800155f4: 0404 addi s1,sp,512 +800155f6: 1004 addi s1,sp,32 +800155f8: 1010 addi a2,sp,32 +800155fa: 1010 addi a2,sp,32 +800155fc: 1010 addi a2,sp,32 +800155fe: 4141 li sp,16 +80015600: 4141 li sp,16 +80015602: 4141 li sp,16 +80015604: 0101 addi sp,sp,0 +80015606: 0101 addi sp,sp,0 +80015608: 0101 addi sp,sp,0 +8001560a: 0101 addi sp,sp,0 +8001560c: 0101 addi sp,sp,0 +8001560e: 0101 addi sp,sp,0 +80015610: 0101 addi sp,sp,0 +80015612: 0101 addi sp,sp,0 +80015614: 0101 addi sp,sp,0 +80015616: 0101 addi sp,sp,0 +80015618: 1010 addi a2,sp,32 +8001561a: 1010 addi a2,sp,32 +8001561c: 1010 addi a2,sp,32 +8001561e: 4242 lw tp,16(sp) +80015620: 4242 lw tp,16(sp) +80015622: 4242 lw tp,16(sp) +80015624: 0202 c.slli64 tp +80015626: 0202 c.slli64 tp +80015628: 0202 c.slli64 tp +8001562a: 0202 c.slli64 tp +8001562c: 0202 c.slli64 tp +8001562e: 0202 c.slli64 tp +80015630: 0202 c.slli64 tp +80015632: 0202 c.slli64 tp +80015634: 0202 c.slli64 tp +80015636: 0202 c.slli64 tp +80015638: 1010 addi a2,sp,32 +8001563a: 1010 addi a2,sp,32 +8001563c: 0020 addi s0,sp,8 ... -80015796: 0000 unimp -80015798: 12d0 addi a2,sp,356 -8001579a: 8001 c.srli64 s0 -8001579c: 13c0 addi s0,sp,484 -8001579e: 8001 c.srli64 s0 -800157a0: 12e0 addi s0,sp,364 -800157a2: 8001 c.srli64 s0 -800157a4: 13c0 addi s0,sp,484 -800157a6: 8001 c.srli64 s0 -800157a8: 13ac addi a1,sp,488 -800157aa: 8001 c.srli64 s0 -800157ac: 13c0 addi s0,sp,484 -800157ae: 8001 c.srli64 s0 -800157b0: 12e0 addi s0,sp,364 -800157b2: 8001 c.srli64 s0 -800157b4: 12d0 addi a2,sp,356 -800157b6: 8001 c.srli64 s0 -800157b8: 12d0 addi a2,sp,356 -800157ba: 8001 c.srli64 s0 -800157bc: 13ac addi a1,sp,488 -800157be: 8001 c.srli64 s0 -800157c0: 12e0 addi s0,sp,364 -800157c2: 8001 c.srli64 s0 -800157c4: 12a8 addi a0,sp,360 -800157c6: 8001 c.srli64 s0 -800157c8: 12a8 addi a0,sp,360 -800157ca: 8001 c.srli64 s0 -800157cc: 12a8 addi a0,sp,360 -800157ce: 8001 c.srli64 s0 -800157d0: 12e8 addi a0,sp,364 -800157d2: 8001 c.srli64 s0 -800157d4: 1894 addi a3,sp,112 -800157d6: 8001 c.srli64 s0 -800157d8: 1894 addi a3,sp,112 -800157da: 8001 c.srli64 s0 -800157dc: 18b8 addi a4,sp,120 -800157de: 8001 c.srli64 s0 -800157e0: 1888 addi a0,sp,112 -800157e2: 8001 c.srli64 s0 -800157e4: 1888 addi a0,sp,112 -800157e6: 8001 c.srli64 s0 -800157e8: 1978 addi a4,sp,188 -800157ea: 8001 c.srli64 s0 -800157ec: 18b8 addi a4,sp,120 -800157ee: 8001 c.srli64 s0 -800157f0: 1888 addi a0,sp,112 -800157f2: 8001 c.srli64 s0 -800157f4: 1978 addi a4,sp,188 -800157f6: 8001 c.srli64 s0 -800157f8: 1888 addi a0,sp,112 -800157fa: 8001 c.srli64 s0 -800157fc: 18b8 addi a4,sp,120 -800157fe: 8001 c.srli64 s0 -80015800: 1884 addi s1,sp,112 -80015802: 8001 c.srli64 s0 -80015804: 1884 addi s1,sp,112 -80015806: 8001 c.srli64 s0 -80015808: 1884 addi s1,sp,112 -8001580a: 8001 c.srli64 s0 -8001580c: 1978 addi a4,sp,188 -8001580e: 8001 c.srli64 s0 -80015810: 2a64 fld fs1,208(a2) -80015812: 8001 c.srli64 s0 -80015814: 2a64 fld fs1,208(a2) -80015816: 8001 c.srli64 s0 -80015818: 2a60 fld fs0,208(a2) -8001581a: 8001 c.srli64 s0 -8001581c: 2a14 fld fa3,16(a2) -8001581e: 8001 c.srli64 s0 -80015820: 2a14 fld fa3,16(a2) -80015822: 8001 c.srli64 s0 -80015824: 2ce4 fld fs1,216(s1) -80015826: 8001 c.srli64 s0 -80015828: 2a60 fld fs0,208(a2) -8001582a: 8001 c.srli64 s0 -8001582c: 2a14 fld fa3,16(a2) -8001582e: 8001 c.srli64 s0 -80015830: 2ce4 fld fs1,216(s1) -80015832: 8001 c.srli64 s0 -80015834: 2a14 fld fa3,16(a2) -80015836: 8001 c.srli64 s0 -80015838: 2a60 fld fs0,208(a2) -8001583a: 8001 c.srli64 s0 -8001583c: 2a10 fld fa2,16(a2) -8001583e: 8001 c.srli64 s0 -80015840: 2a10 fld fa2,16(a2) -80015842: 8001 c.srli64 s0 -80015844: 2a10 fld fa2,16(a2) -80015846: 8001 c.srli64 s0 -80015848: 2ce4 fld fs1,216(s1) -8001584a: 8001 c.srli64 s0 +800156be: 0000 unimp +800156c0: 120c addi a1,sp,288 +800156c2: 8001 c.srli64 s0 +800156c4: 12fc addi a5,sp,364 +800156c6: 8001 c.srli64 s0 +800156c8: 121c addi a5,sp,288 +800156ca: 8001 c.srli64 s0 +800156cc: 12fc addi a5,sp,364 +800156ce: 8001 c.srli64 s0 +800156d0: 12e8 addi a0,sp,364 +800156d2: 8001 c.srli64 s0 +800156d4: 12fc addi a5,sp,364 +800156d6: 8001 c.srli64 s0 +800156d8: 121c addi a5,sp,288 +800156da: 8001 c.srli64 s0 +800156dc: 120c addi a1,sp,288 +800156de: 8001 c.srli64 s0 +800156e0: 120c addi a1,sp,288 +800156e2: 8001 c.srli64 s0 +800156e4: 12e8 addi a0,sp,364 +800156e6: 8001 c.srli64 s0 +800156e8: 121c addi a5,sp,288 +800156ea: 8001 c.srli64 s0 +800156ec: 11e4 addi s1,sp,236 +800156ee: 8001 c.srli64 s0 +800156f0: 11e4 addi s1,sp,236 +800156f2: 8001 c.srli64 s0 +800156f4: 11e4 addi s1,sp,236 +800156f6: 8001 c.srli64 s0 +800156f8: 1224 addi s1,sp,296 +800156fa: 8001 c.srli64 s0 +800156fc: 17d0 addi a2,sp,996 +800156fe: 8001 c.srli64 s0 +80015700: 17d0 addi a2,sp,996 +80015702: 8001 c.srli64 s0 +80015704: 17f4 addi a3,sp,1004 +80015706: 8001 c.srli64 s0 +80015708: 17c4 addi s1,sp,996 +8001570a: 8001 c.srli64 s0 +8001570c: 17c4 addi s1,sp,996 +8001570e: 8001 c.srli64 s0 +80015710: 18b4 addi a3,sp,120 +80015712: 8001 c.srli64 s0 +80015714: 17f4 addi a3,sp,1004 +80015716: 8001 c.srli64 s0 +80015718: 17c4 addi s1,sp,996 +8001571a: 8001 c.srli64 s0 +8001571c: 18b4 addi a3,sp,120 +8001571e: 8001 c.srli64 s0 +80015720: 17c4 addi s1,sp,996 +80015722: 8001 c.srli64 s0 +80015724: 17f4 addi a3,sp,1004 +80015726: 8001 c.srli64 s0 +80015728: 17c0 addi s0,sp,996 +8001572a: 8001 c.srli64 s0 +8001572c: 17c0 addi s0,sp,996 +8001572e: 8001 c.srli64 s0 +80015730: 17c0 addi s0,sp,996 +80015732: 8001 c.srli64 s0 +80015734: 18b4 addi a3,sp,120 +80015736: 8001 c.srli64 s0 +80015738: 29a0 fld fs0,80(a1) +8001573a: 8001 c.srli64 s0 +8001573c: 29a0 fld fs0,80(a1) +8001573e: 8001 c.srli64 s0 +80015740: 299c fld fa5,16(a1) +80015742: 8001 c.srli64 s0 +80015744: 2950 fld fa2,144(a0) +80015746: 8001 c.srli64 s0 +80015748: 2950 fld fa2,144(a0) +8001574a: 8001 c.srli64 s0 +8001574c: 2c20 fld fs0,88(s0) +8001574e: 8001 c.srli64 s0 +80015750: 299c fld fa5,16(a1) +80015752: 8001 c.srli64 s0 +80015754: 2950 fld fa2,144(a0) +80015756: 8001 c.srli64 s0 +80015758: 2c20 fld fs0,88(s0) +8001575a: 8001 c.srli64 s0 +8001575c: 2950 fld fa2,144(a0) +8001575e: 8001 c.srli64 s0 +80015760: 299c fld fa5,16(a1) +80015762: 8001 c.srli64 s0 +80015764: 294c fld fa1,144(a0) +80015766: 8001 c.srli64 s0 +80015768: 294c fld fa1,144(a0) +8001576a: 8001 c.srli64 s0 +8001576c: 294c fld fa1,144(a0) +8001576e: 8001 c.srli64 s0 +80015770: 2c20 fld fs0,88(s0) +80015772: 8001 c.srli64 s0 -8001584c <__clz_tab>: -8001584c: 0100 addi s0,sp,128 -8001584e: 0202 c.slli64 tp -80015850: 03030303 lb t1,48(t1) -80015854: 0404 addi s1,sp,512 -80015856: 0404 addi s1,sp,512 -80015858: 0404 addi s1,sp,512 -8001585a: 0404 addi s1,sp,512 -8001585c: 0505 addi a0,a0,1 -8001585e: 0505 addi a0,a0,1 -80015860: 0505 addi a0,a0,1 -80015862: 0505 addi a0,a0,1 -80015864: 0505 addi a0,a0,1 -80015866: 0505 addi a0,a0,1 -80015868: 0505 addi a0,a0,1 -8001586a: 0505 addi a0,a0,1 -8001586c: 0606 slli a2,a2,0x1 -8001586e: 0606 slli a2,a2,0x1 -80015870: 0606 slli a2,a2,0x1 -80015872: 0606 slli a2,a2,0x1 -80015874: 0606 slli a2,a2,0x1 -80015876: 0606 slli a2,a2,0x1 -80015878: 0606 slli a2,a2,0x1 -8001587a: 0606 slli a2,a2,0x1 -8001587c: 0606 slli a2,a2,0x1 -8001587e: 0606 slli a2,a2,0x1 -80015880: 0606 slli a2,a2,0x1 -80015882: 0606 slli a2,a2,0x1 -80015884: 0606 slli a2,a2,0x1 -80015886: 0606 slli a2,a2,0x1 -80015888: 0606 slli a2,a2,0x1 -8001588a: 0606 slli a2,a2,0x1 -8001588c: 07070707 0x7070707 -80015890: 07070707 0x7070707 -80015894: 07070707 0x7070707 -80015898: 07070707 0x7070707 -8001589c: 07070707 0x7070707 -800158a0: 07070707 0x7070707 -800158a4: 07070707 0x7070707 -800158a8: 07070707 0x7070707 -800158ac: 07070707 0x7070707 -800158b0: 07070707 0x7070707 -800158b4: 07070707 0x7070707 -800158b8: 07070707 0x7070707 -800158bc: 07070707 0x7070707 -800158c0: 07070707 0x7070707 -800158c4: 07070707 0x7070707 -800158c8: 07070707 0x7070707 -800158cc: 0808 addi a0,sp,16 -800158ce: 0808 addi a0,sp,16 -800158d0: 0808 addi a0,sp,16 -800158d2: 0808 addi a0,sp,16 -800158d4: 0808 addi a0,sp,16 -800158d6: 0808 addi a0,sp,16 -800158d8: 0808 addi a0,sp,16 -800158da: 0808 addi a0,sp,16 -800158dc: 0808 addi a0,sp,16 -800158de: 0808 addi a0,sp,16 -800158e0: 0808 addi a0,sp,16 -800158e2: 0808 addi a0,sp,16 -800158e4: 0808 addi a0,sp,16 -800158e6: 0808 addi a0,sp,16 -800158e8: 0808 addi a0,sp,16 -800158ea: 0808 addi a0,sp,16 -800158ec: 0808 addi a0,sp,16 -800158ee: 0808 addi a0,sp,16 -800158f0: 0808 addi a0,sp,16 -800158f2: 0808 addi a0,sp,16 -800158f4: 0808 addi a0,sp,16 -800158f6: 0808 addi a0,sp,16 -800158f8: 0808 addi a0,sp,16 -800158fa: 0808 addi a0,sp,16 -800158fc: 0808 addi a0,sp,16 -800158fe: 0808 addi a0,sp,16 -80015900: 0808 addi a0,sp,16 -80015902: 0808 addi a0,sp,16 -80015904: 0808 addi a0,sp,16 -80015906: 0808 addi a0,sp,16 -80015908: 0808 addi a0,sp,16 -8001590a: 0808 addi a0,sp,16 -8001590c: 0808 addi a0,sp,16 -8001590e: 0808 addi a0,sp,16 -80015910: 0808 addi a0,sp,16 -80015912: 0808 addi a0,sp,16 -80015914: 0808 addi a0,sp,16 -80015916: 0808 addi a0,sp,16 -80015918: 0808 addi a0,sp,16 -8001591a: 0808 addi a0,sp,16 -8001591c: 0808 addi a0,sp,16 -8001591e: 0808 addi a0,sp,16 -80015920: 0808 addi a0,sp,16 -80015922: 0808 addi a0,sp,16 -80015924: 0808 addi a0,sp,16 -80015926: 0808 addi a0,sp,16 -80015928: 0808 addi a0,sp,16 -8001592a: 0808 addi a0,sp,16 -8001592c: 0808 addi a0,sp,16 -8001592e: 0808 addi a0,sp,16 -80015930: 0808 addi a0,sp,16 -80015932: 0808 addi a0,sp,16 -80015934: 0808 addi a0,sp,16 -80015936: 0808 addi a0,sp,16 -80015938: 0808 addi a0,sp,16 -8001593a: 0808 addi a0,sp,16 -8001593c: 0808 addi a0,sp,16 -8001593e: 0808 addi a0,sp,16 -80015940: 0808 addi a0,sp,16 -80015942: 0808 addi a0,sp,16 -80015944: 0808 addi a0,sp,16 -80015946: 0808 addi a0,sp,16 -80015948: 0808 addi a0,sp,16 -8001594a: 0808 addi a0,sp,16 +80015774 <__clz_tab>: +80015774: 0100 addi s0,sp,128 +80015776: 0202 c.slli64 tp +80015778: 03030303 lb t1,48(t1) # ffffa030 <__BSS_END__+0x7ffe33f4> +8001577c: 0404 addi s1,sp,512 +8001577e: 0404 addi s1,sp,512 +80015780: 0404 addi s1,sp,512 +80015782: 0404 addi s1,sp,512 +80015784: 0505 addi a0,a0,1 +80015786: 0505 addi a0,a0,1 +80015788: 0505 addi a0,a0,1 +8001578a: 0505 addi a0,a0,1 +8001578c: 0505 addi a0,a0,1 +8001578e: 0505 addi a0,a0,1 +80015790: 0505 addi a0,a0,1 +80015792: 0505 addi a0,a0,1 +80015794: 0606 slli a2,a2,0x1 +80015796: 0606 slli a2,a2,0x1 +80015798: 0606 slli a2,a2,0x1 +8001579a: 0606 slli a2,a2,0x1 +8001579c: 0606 slli a2,a2,0x1 +8001579e: 0606 slli a2,a2,0x1 +800157a0: 0606 slli a2,a2,0x1 +800157a2: 0606 slli a2,a2,0x1 +800157a4: 0606 slli a2,a2,0x1 +800157a6: 0606 slli a2,a2,0x1 +800157a8: 0606 slli a2,a2,0x1 +800157aa: 0606 slli a2,a2,0x1 +800157ac: 0606 slli a2,a2,0x1 +800157ae: 0606 slli a2,a2,0x1 +800157b0: 0606 slli a2,a2,0x1 +800157b2: 0606 slli a2,a2,0x1 +800157b4: 07070707 0x7070707 +800157b8: 07070707 0x7070707 +800157bc: 07070707 0x7070707 +800157c0: 07070707 0x7070707 +800157c4: 07070707 0x7070707 +800157c8: 07070707 0x7070707 +800157cc: 07070707 0x7070707 +800157d0: 07070707 0x7070707 +800157d4: 07070707 0x7070707 +800157d8: 07070707 0x7070707 +800157dc: 07070707 0x7070707 +800157e0: 07070707 0x7070707 +800157e4: 07070707 0x7070707 +800157e8: 07070707 0x7070707 +800157ec: 07070707 0x7070707 +800157f0: 07070707 0x7070707 +800157f4: 0808 addi a0,sp,16 +800157f6: 0808 addi a0,sp,16 +800157f8: 0808 addi a0,sp,16 +800157fa: 0808 addi a0,sp,16 +800157fc: 0808 addi a0,sp,16 +800157fe: 0808 addi a0,sp,16 +80015800: 0808 addi a0,sp,16 +80015802: 0808 addi a0,sp,16 +80015804: 0808 addi a0,sp,16 +80015806: 0808 addi a0,sp,16 +80015808: 0808 addi a0,sp,16 +8001580a: 0808 addi a0,sp,16 +8001580c: 0808 addi a0,sp,16 +8001580e: 0808 addi a0,sp,16 +80015810: 0808 addi a0,sp,16 +80015812: 0808 addi a0,sp,16 +80015814: 0808 addi a0,sp,16 +80015816: 0808 addi a0,sp,16 +80015818: 0808 addi a0,sp,16 +8001581a: 0808 addi a0,sp,16 +8001581c: 0808 addi a0,sp,16 +8001581e: 0808 addi a0,sp,16 +80015820: 0808 addi a0,sp,16 +80015822: 0808 addi a0,sp,16 +80015824: 0808 addi a0,sp,16 +80015826: 0808 addi a0,sp,16 +80015828: 0808 addi a0,sp,16 +8001582a: 0808 addi a0,sp,16 +8001582c: 0808 addi a0,sp,16 +8001582e: 0808 addi a0,sp,16 +80015830: 0808 addi a0,sp,16 +80015832: 0808 addi a0,sp,16 +80015834: 0808 addi a0,sp,16 +80015836: 0808 addi a0,sp,16 +80015838: 0808 addi a0,sp,16 +8001583a: 0808 addi a0,sp,16 +8001583c: 0808 addi a0,sp,16 +8001583e: 0808 addi a0,sp,16 +80015840: 0808 addi a0,sp,16 +80015842: 0808 addi a0,sp,16 +80015844: 0808 addi a0,sp,16 +80015846: 0808 addi a0,sp,16 +80015848: 0808 addi a0,sp,16 +8001584a: 0808 addi a0,sp,16 +8001584c: 0808 addi a0,sp,16 +8001584e: 0808 addi a0,sp,16 +80015850: 0808 addi a0,sp,16 +80015852: 0808 addi a0,sp,16 +80015854: 0808 addi a0,sp,16 +80015856: 0808 addi a0,sp,16 +80015858: 0808 addi a0,sp,16 +8001585a: 0808 addi a0,sp,16 +8001585c: 0808 addi a0,sp,16 +8001585e: 0808 addi a0,sp,16 +80015860: 0808 addi a0,sp,16 +80015862: 0808 addi a0,sp,16 +80015864: 0808 addi a0,sp,16 +80015866: 0808 addi a0,sp,16 +80015868: 0808 addi a0,sp,16 +8001586a: 0808 addi a0,sp,16 +8001586c: 0808 addi a0,sp,16 +8001586e: 0808 addi a0,sp,16 +80015870: 0808 addi a0,sp,16 +80015872: 0808 addi a0,sp,16 Disassembly of section .eh_frame: -8001594c <.eh_frame>: -8001594c: 0010 0x10 -8001594e: 0000 unimp -80015950: 0000 unimp -80015952: 0000 unimp -80015954: 7a01 lui s4,0xfffe0 -80015956: 0052 c.slli zero,0x14 -80015958: 7c01 lui s8,0xfffe0 -8001595a: 0101 addi sp,sp,0 -8001595c: 00020d1b 0x20d1b -80015960: 0010 0x10 -80015962: 0000 unimp -80015964: 0018 0x18 +80015874 <.eh_frame>: +80015874: 0010 0x10 +80015876: 0000 unimp +80015878: 0000 unimp +8001587a: 0000 unimp +8001587c: 7a01 lui s4,0xfffe0 +8001587e: 0052 c.slli zero,0x14 +80015880: 7c01 lui s8,0xfffe0 +80015882: 0101 addi sp,sp,0 +80015884: 00020d1b 0x20d1b +80015888: 0020 addi s0,sp,8 +8001588a: 0000 unimp +8001588c: 0018 0x18 +8001588e: 0000 unimp +80015890: a7f8 fsd fa4,200(a5) +80015892: fffe fsw ft11,252(sp) +80015894: 0108 addi a0,sp,128 +80015896: 0000 unimp +80015898: 4400 lw s0,8(s0) +8001589a: 300e fld ft0,224(sp) +8001589c: 8844 0x8844 +8001589e: 4401 li s0,0 +800158a0: 080c addi a1,sp,16 +800158a2: 0200 addi s0,sp,256 +800158a4: c8f4 sw a3,84(s1) +800158a6: 020c addi a1,sp,256 +800158a8: 4430 lw a2,72(s0) +800158aa: 000e c.slli zero,0x3 +800158ac: 0020 addi s0,sp,8 +800158ae: 0000 unimp +800158b0: 003c addi a5,sp,8 +800158b2: 0000 unimp +800158b4: a8dc fsd fa5,144(s1) +800158b6: fffe fsw ft11,252(sp) +800158b8: 0104 addi s1,sp,128 +800158ba: 0000 unimp +800158bc: 4400 lw s0,8(s0) +800158be: 400e 0x400e +800158c0: 8844 0x8844 +800158c2: 4401 li s0,0 +800158c4: 080c addi a1,sp,16 +800158c6: 0200 addi s0,sp,256 +800158c8: c8f0 sw a2,84(s1) +800158ca: 020c addi a1,sp,256 +800158cc: 4440 lw s0,12(s0) +800158ce: 000e c.slli zero,0x3 +800158d0: 0020 addi s0,sp,8 +800158d2: 0000 unimp +800158d4: 0060 addi s0,sp,12 +800158d6: 0000 unimp +800158d8: a9bc fsd fa5,80(a1) +800158da: fffe fsw ft11,252(sp) +800158dc: 001c 0x1c +800158de: 0000 unimp +800158e0: 4400 lw s0,8(s0) +800158e2: 100e c.slli zero,0x23 +800158e4: 8844 0x8844 +800158e6: 4401 li s0,0 +800158e8: 080c addi a1,sp,16 +800158ea: 4800 lw s0,16(s0) +800158ec: 0cc8 addi a0,sp,596 +800158ee: 1002 c.slli zero,0x20 +800158f0: 0e44 addi s1,sp,788 +800158f2: 0000 unimp +800158f4: 0020 addi s0,sp,8 +800158f6: 0000 unimp +800158f8: 0084 addi s1,sp,64 +800158fa: 0000 unimp +800158fc: a9b4 fsd fa3,80(a1) +800158fe: fffe fsw ft11,252(sp) +80015900: 0034 addi a3,sp,8 +80015902: 0000 unimp +80015904: 4400 lw s0,8(s0) +80015906: 200e fld ft0,192(sp) +80015908: 8844 0x8844 +8001590a: 4401 li s0,0 +8001590c: 080c addi a1,sp,16 +8001590e: 6000 flw fs0,0(s0) +80015910: 0cc8 addi a0,sp,596 +80015912: 2002 fld ft0,0(sp) +80015914: 0e44 addi s1,sp,788 +80015916: 0000 unimp +80015918: 0020 addi s0,sp,8 +8001591a: 0000 unimp +8001591c: 00a8 addi a0,sp,72 +8001591e: 0000 unimp +80015920: a9c4 fsd fs1,144(a1) +80015922: fffe fsw ft11,252(sp) +80015924: 0024 addi s1,sp,8 +80015926: 0000 unimp +80015928: 4400 lw s0,8(s0) +8001592a: 200e fld ft0,192(sp) +8001592c: 8844 0x8844 +8001592e: 4401 li s0,0 +80015930: 080c addi a1,sp,16 +80015932: 5000 lw s0,32(s0) +80015934: 0cc8 addi a0,sp,596 +80015936: 2002 fld ft0,0(sp) +80015938: 0e44 addi s1,sp,788 +8001593a: 0000 unimp +8001593c: 0024 addi s1,sp,8 +8001593e: 0000 unimp +80015940: 00cc addi a1,sp,68 +80015942: 0000 unimp +80015944: a9c4 fsd fs1,144(a1) +80015946: fffe fsw ft11,252(sp) +80015948: 00c8 addi a0,sp,68 +8001594a: 0000 unimp +8001594c: 4400 lw s0,8(s0) +8001594e: 300e fld ft0,224(sp) +80015950: 8148 0x8148 +80015952: 8801 andi s0,s0,0 +80015954: 4402 lw s0,0(sp) +80015956: 080c addi a1,sp,16 +80015958: 0200 addi s0,sp,256 +8001595a: c1ac sw a1,64(a1) +8001595c: c844 sw s1,20(s0) +8001595e: 020c addi a1,sp,256 +80015960: 4430 lw a2,72(s0) +80015962: 000e c.slli zero,0x3 +80015964: 0024 addi s1,sp,8 80015966: 0000 unimp -80015968: ab5c fsd fa5,144(a4) -8001596a: ffff 0xffff -8001596c: 0434 addi a3,sp,520 -8001596e: 0000 unimp -80015970: 0000 unimp +80015968: 00f4 addi a3,sp,76 +8001596a: 0000 unimp +8001596c: aa64 fsd fs1,208(a2) +8001596e: fffe fsw ft11,252(sp) +80015970: 00b4 addi a3,sp,72 80015972: 0000 unimp -80015974: 0010 0x10 -80015976: 0000 unimp -80015978: 002c addi a1,sp,8 -8001597a: 0000 unimp -8001597c: af7c fsd fa5,216(a4) -8001597e: ffff 0xffff -80015980: 0410 addi a2,sp,512 -80015982: 0000 unimp -80015984: 0000 unimp +80015974: 4400 lw s0,8(s0) +80015976: 300e fld ft0,224(sp) +80015978: 8148 0x8148 +8001597a: 8801 andi s0,s0,0 +8001597c: 4402 lw s0,0(sp) +8001597e: 080c addi a1,sp,16 +80015980: 0200 addi s0,sp,256 +80015982: c198 sw a4,0(a1) +80015984: c844 sw s1,20(s0) +80015986: 020c addi a1,sp,256 +80015988: 4430 lw a2,72(s0) +8001598a: 000e c.slli zero,0x3 +8001598c: 0024 addi s1,sp,8 +8001598e: 0000 unimp +80015990: 011c addi a5,sp,128 +80015992: 0000 unimp +80015994: aaf0 fsd fa2,208(a3) +80015996: fffe fsw ft11,252(sp) +80015998: 0090 addi a2,sp,64 +8001599a: 0000 unimp +8001599c: 4400 lw s0,8(s0) +8001599e: 300e fld ft0,224(sp) +800159a0: 8148 0x8148 +800159a2: 8801 andi s0,s0,0 +800159a4: 4402 lw s0,0(sp) +800159a6: 080c addi a1,sp,16 +800159a8: 0200 addi s0,sp,256 +800159aa: c174 sw a3,68(a0) +800159ac: c844 sw s1,20(s0) +800159ae: 020c addi a1,sp,256 +800159b0: 4430 lw a2,72(s0) +800159b2: 000e c.slli zero,0x3 +800159b4: 0020 addi s0,sp,8 +800159b6: 0000 unimp +800159b8: 0144 addi s1,sp,132 +800159ba: 0000 unimp +800159bc: ab58 fsd fa4,144(a4) +800159be: fffe fsw ft11,252(sp) +800159c0: 0050 addi a2,sp,4 +800159c2: 0000 unimp +800159c4: 4400 lw s0,8(s0) +800159c6: 300e fld ft0,224(sp) +800159c8: 8844 0x8844 +800159ca: 4401 li s0,0 +800159cc: 080c addi a1,sp,16 +800159ce: 0200 addi s0,sp,256 +800159d0: c83c sw a5,80(s0) +800159d2: 020c addi a1,sp,256 +800159d4: 4430 lw a2,72(s0) +800159d6: 000e c.slli zero,0x3 +800159d8: 0024 addi s1,sp,8 +800159da: 0000 unimp +800159dc: 0168 addi a0,sp,140 +800159de: 0000 unimp +800159e0: ab84 fsd fs1,16(a5) +800159e2: fffe fsw ft11,252(sp) +800159e4: 0030 addi a2,sp,8 +800159e6: 0000 unimp +800159e8: 4400 lw s0,8(s0) +800159ea: 200e fld ft0,192(sp) +800159ec: 8148 0x8148 +800159ee: 8801 andi s0,s0,0 +800159f0: 4402 lw s0,0(sp) +800159f2: 080c addi a1,sp,16 +800159f4: 5400 lw s0,40(s0) +800159f6: 44c1 li s1,16 +800159f8: 0cc8 addi a0,sp,596 +800159fa: 2002 fld ft0,0(sp) +800159fc: 0e44 addi s1,sp,788 +800159fe: 0000 unimp +80015a00: 0024 addi s1,sp,8 +80015a02: 0000 unimp +80015a04: 0190 addi a2,sp,192 +80015a06: 0000 unimp +80015a08: ab8c fsd fa1,16(a5) +80015a0a: fffe fsw ft11,252(sp) +80015a0c: 00c8 addi a0,sp,68 +80015a0e: 0000 unimp +80015a10: 4400 lw s0,8(s0) +80015a12: 300e fld ft0,224(sp) +80015a14: 8148 0x8148 +80015a16: 8801 andi s0,s0,0 +80015a18: 4402 lw s0,0(sp) +80015a1a: 080c addi a1,sp,16 +80015a1c: 0200 addi s0,sp,256 +80015a1e: c1ac sw a1,64(a1) +80015a20: c844 sw s1,20(s0) +80015a22: 020c addi a1,sp,256 +80015a24: 4430 lw a2,72(s0) +80015a26: 000e c.slli zero,0x3 +80015a28: 0024 addi s1,sp,8 +80015a2a: 0000 unimp +80015a2c: 01b8 addi a4,sp,200 +80015a2e: 0000 unimp +80015a30: ac2c fsd fa1,88(s0) +80015a32: fffe fsw ft11,252(sp) +80015a34: 002c addi a1,sp,8 +80015a36: 0000 unimp +80015a38: 4400 lw s0,8(s0) +80015a3a: 100e c.slli zero,0x23 +80015a3c: 8148 0x8148 +80015a3e: 8801 andi s0,s0,0 +80015a40: 4402 lw s0,0(sp) +80015a42: 080c addi a1,sp,16 +80015a44: 5000 lw s0,32(s0) +80015a46: 44c1 li s1,16 +80015a48: 0cc8 addi a0,sp,596 +80015a4a: 1002 c.slli zero,0x20 +80015a4c: 0e44 addi s1,sp,788 +80015a4e: 0000 unimp +80015a50: 0024 addi s1,sp,8 +80015a52: 0000 unimp +80015a54: 01e0 addi s0,sp,204 +80015a56: 0000 unimp +80015a58: ac30 fsd fa2,88(s0) +80015a5a: fffe fsw ft11,252(sp) +80015a5c: 002c addi a1,sp,8 +80015a5e: 0000 unimp +80015a60: 4400 lw s0,8(s0) +80015a62: 100e c.slli zero,0x23 +80015a64: 8148 0x8148 +80015a66: 8801 andi s0,s0,0 +80015a68: 4402 lw s0,0(sp) +80015a6a: 080c addi a1,sp,16 +80015a6c: 5000 lw s0,32(s0) +80015a6e: 44c1 li s1,16 +80015a70: 0cc8 addi a0,sp,596 +80015a72: 1002 c.slli zero,0x20 +80015a74: 0e44 addi s1,sp,788 +80015a76: 0000 unimp +80015a78: 0024 addi s1,sp,8 +80015a7a: 0000 unimp +80015a7c: 0208 addi a0,sp,256 +80015a7e: 0000 unimp +80015a80: ac34 fsd fa3,88(s0) +80015a82: fffe fsw ft11,252(sp) +80015a84: 0030 addi a2,sp,8 +80015a86: 0000 unimp +80015a88: 4400 lw s0,8(s0) +80015a8a: 100e c.slli zero,0x23 +80015a8c: 8148 0x8148 +80015a8e: 8801 andi s0,s0,0 +80015a90: 4402 lw s0,0(sp) +80015a92: 080c addi a1,sp,16 +80015a94: 5400 lw s0,40(s0) +80015a96: 44c1 li s1,16 +80015a98: 0cc8 addi a0,sp,596 +80015a9a: 1002 c.slli zero,0x20 +80015a9c: 0e44 addi s1,sp,788 +80015a9e: 0000 unimp +80015aa0: 0020 addi s0,sp,8 +80015aa2: 0000 unimp +80015aa4: 0230 addi a2,sp,264 +80015aa6: 0000 unimp +80015aa8: ac3c fsd fa5,88(s0) +80015aaa: fffe fsw ft11,252(sp) +80015aac: 0028 addi a0,sp,8 +80015aae: 0000 unimp +80015ab0: 4400 lw s0,8(s0) +80015ab2: 100e c.slli zero,0x23 +80015ab4: 8844 0x8844 +80015ab6: 4401 li s0,0 +80015ab8: 080c addi a1,sp,16 +80015aba: 5400 lw s0,40(s0) +80015abc: 0cc8 addi a0,sp,596 +80015abe: 1002 c.slli zero,0x20 +80015ac0: 0e44 addi s1,sp,788 +80015ac2: 0000 unimp +80015ac4: 0024 addi s1,sp,8 +80015ac6: 0000 unimp +80015ac8: 0254 addi a3,sp,260 +80015aca: 0000 unimp +80015acc: ac40 fsd fs0,152(s0) +80015ace: fffe fsw ft11,252(sp) +80015ad0: 0030 addi a2,sp,8 +80015ad2: 0000 unimp +80015ad4: 4400 lw s0,8(s0) +80015ad6: 100e c.slli zero,0x23 +80015ad8: 8148 0x8148 +80015ada: 8801 andi s0,s0,0 +80015adc: 4402 lw s0,0(sp) +80015ade: 080c addi a1,sp,16 +80015ae0: 5400 lw s0,40(s0) +80015ae2: 44c1 li s1,16 +80015ae4: 0cc8 addi a0,sp,596 +80015ae6: 1002 c.slli zero,0x20 +80015ae8: 0e44 addi s1,sp,788 +80015aea: 0000 unimp +80015aec: 0024 addi s1,sp,8 +80015aee: 0000 unimp +80015af0: 027c addi a5,sp,268 +80015af2: 0000 unimp +80015af4: ad14 fsd fa3,24(a0) +80015af6: fffe fsw ft11,252(sp) +80015af8: 00c8 addi a0,sp,68 +80015afa: 0000 unimp +80015afc: 4400 lw s0,8(s0) +80015afe: 300e fld ft0,224(sp) +80015b00: 8148 0x8148 +80015b02: 8801 andi s0,s0,0 +80015b04: 4402 lw s0,0(sp) +80015b06: 080c addi a1,sp,16 +80015b08: 0200 addi s0,sp,256 +80015b0a: c1ac sw a1,64(a1) +80015b0c: c844 sw s1,20(s0) +80015b0e: 020c addi a1,sp,256 +80015b10: 4430 lw a2,72(s0) +80015b12: 000e c.slli zero,0x3 +80015b14: 0024 addi s1,sp,8 +80015b16: 0000 unimp +80015b18: 02a4 addi s1,sp,328 +80015b1a: 0000 unimp +80015b1c: adb4 fsd fa3,88(a1) +80015b1e: fffe fsw ft11,252(sp) +80015b20: 0048 addi a0,sp,4 +80015b22: 0000 unimp +80015b24: 4400 lw s0,8(s0) +80015b26: 200e fld ft0,192(sp) +80015b28: 8148 0x8148 +80015b2a: 8801 andi s0,s0,0 +80015b2c: 4402 lw s0,0(sp) +80015b2e: 080c addi a1,sp,16 +80015b30: 6c00 flw fs0,24(s0) +80015b32: 44c1 li s1,16 +80015b34: 0cc8 addi a0,sp,596 +80015b36: 2002 fld ft0,0(sp) +80015b38: 0e44 addi s1,sp,788 +80015b3a: 0000 unimp +80015b3c: 0024 addi s1,sp,8 +80015b3e: 0000 unimp +80015b40: 02cc addi a1,sp,324 +80015b42: 0000 unimp +80015b44: add4 fsd fa3,152(a1) +80015b46: fffe fsw ft11,252(sp) +80015b48: 0068 addi a0,sp,12 +80015b4a: 0000 unimp +80015b4c: 4400 lw s0,8(s0) +80015b4e: 200e fld ft0,192(sp) +80015b50: 8148 0x8148 +80015b52: 8801 andi s0,s0,0 +80015b54: 4402 lw s0,0(sp) +80015b56: 080c addi a1,sp,16 +80015b58: 0200 addi s0,sp,256 +80015b5a: c14c sw a1,4(a0) +80015b5c: c844 sw s1,20(s0) +80015b5e: 020c addi a1,sp,256 +80015b60: 4420 lw s0,72(s0) +80015b62: 000e c.slli zero,0x3 +80015b64: 0024 addi s1,sp,8 +80015b66: 0000 unimp +80015b68: 02f4 addi a3,sp,332 +80015b6a: 0000 unimp +80015b6c: ae14 fsd fa3,24(a2) +80015b6e: fffe fsw ft11,252(sp) +80015b70: 0064 addi s1,sp,12 +80015b72: 0000 unimp +80015b74: 4400 lw s0,8(s0) +80015b76: 200e fld ft0,192(sp) +80015b78: 8148 0x8148 +80015b7a: 8801 andi s0,s0,0 +80015b7c: 4402 lw s0,0(sp) +80015b7e: 080c addi a1,sp,16 +80015b80: 0200 addi s0,sp,256 +80015b82: c148 sw a0,4(a0) +80015b84: c844 sw s1,20(s0) +80015b86: 020c addi a1,sp,256 +80015b88: 4420 lw s0,72(s0) +80015b8a: 000e c.slli zero,0x3 +80015b8c: 0028 addi a0,sp,8 +80015b8e: 0000 unimp +80015b90: 031c addi a5,sp,384 +80015b92: 0000 unimp +80015b94: ae50 fsd fa2,152(a2) +80015b96: fffe fsw ft11,252(sp) +80015b98: 0108 addi a0,sp,128 +80015b9a: 0000 unimp +80015b9c: 4400 lw s0,8(s0) +80015b9e: 300e fld ft0,224(sp) +80015ba0: 8148 0x8148 +80015ba2: 8801 andi s0,s0,0 +80015ba4: 4402 lw s0,0(sp) +80015ba6: 080c addi a1,sp,16 +80015ba8: 0300 addi s0,sp,384 +80015baa: 00ec addi a1,sp,76 +80015bac: 44c1 li s1,16 +80015bae: 0cc8 addi a0,sp,596 +80015bb0: 3002 fld ft0,32(sp) +80015bb2: 0e44 addi s1,sp,788 +80015bb4: 0000 unimp +80015bb6: 0000 unimp +80015bb8: 0028 addi a0,sp,8 +80015bba: 0000 unimp +80015bbc: 0348 addi a0,sp,388 +80015bbe: 0000 unimp +80015bc0: af2c fsd fa1,88(a4) +80015bc2: fffe fsw ft11,252(sp) +80015bc4: 015c addi a5,sp,132 +80015bc6: 0000 unimp +80015bc8: 4400 lw s0,8(s0) +80015bca: 400e 0x400e +80015bcc: 8148 0x8148 +80015bce: 8801 andi s0,s0,0 +80015bd0: 4402 lw s0,0(sp) +80015bd2: 080c addi a1,sp,16 +80015bd4: 0300 addi s0,sp,384 +80015bd6: 0140 addi s0,sp,132 +80015bd8: 44c1 li s1,16 +80015bda: 0cc8 addi a0,sp,596 +80015bdc: 4002 0x4002 +80015bde: 0e44 addi s1,sp,788 +80015be0: 0000 unimp +80015be2: 0000 unimp +80015be4: 0024 addi s1,sp,8 +80015be6: 0000 unimp +80015be8: 0374 addi a3,sp,396 +80015bea: 0000 unimp +80015bec: b05c fsd fa5,160(s0) +80015bee: fffe fsw ft11,252(sp) +80015bf0: 00d4 addi a3,sp,68 +80015bf2: 0000 unimp +80015bf4: 4400 lw s0,8(s0) +80015bf6: 200e fld ft0,192(sp) +80015bf8: 8148 0x8148 +80015bfa: 8801 andi s0,s0,0 +80015bfc: 4402 lw s0,0(sp) +80015bfe: 080c addi a1,sp,16 +80015c00: 0200 addi s0,sp,256 +80015c02: c1b8 sw a4,64(a1) +80015c04: c844 sw s1,20(s0) +80015c06: 020c addi a1,sp,256 +80015c08: 4420 lw s0,72(s0) +80015c0a: 000e c.slli zero,0x3 +80015c0c: 0028 addi a0,sp,8 +80015c0e: 0000 unimp +80015c10: 039c addi a5,sp,448 +80015c12: 0000 unimp +80015c14: b108 fsd fa0,32(a0) +80015c16: fffe fsw ft11,252(sp) +80015c18: 0178 addi a4,sp,140 +80015c1a: 0000 unimp +80015c1c: 4400 lw s0,8(s0) +80015c1e: 200e fld ft0,192(sp) +80015c20: 8148 0x8148 +80015c22: 8801 andi s0,s0,0 +80015c24: 4402 lw s0,0(sp) +80015c26: 080c addi a1,sp,16 +80015c28: 0300 addi s0,sp,384 +80015c2a: 015c addi a5,sp,132 +80015c2c: 44c1 li s1,16 +80015c2e: 0cc8 addi a0,sp,596 +80015c30: 2002 fld ft0,0(sp) +80015c32: 0e44 addi s1,sp,788 +80015c34: 0000 unimp +80015c36: 0000 unimp +80015c38: 0024 addi s1,sp,8 +80015c3a: 0000 unimp +80015c3c: 03c8 addi a0,sp,452 +80015c3e: 0000 unimp +80015c40: b254 fsd fa3,160(a2) +80015c42: fffe fsw ft11,252(sp) +80015c44: 0064 addi s1,sp,12 +80015c46: 0000 unimp +80015c48: 4400 lw s0,8(s0) +80015c4a: 200e fld ft0,192(sp) +80015c4c: 8148 0x8148 +80015c4e: 8801 andi s0,s0,0 +80015c50: 4402 lw s0,0(sp) +80015c52: 080c addi a1,sp,16 +80015c54: 0200 addi s0,sp,256 +80015c56: c148 sw a0,4(a0) +80015c58: c844 sw s1,20(s0) +80015c5a: 020c addi a1,sp,256 +80015c5c: 4420 lw s0,72(s0) +80015c5e: 000e c.slli zero,0x3 +80015c60: 0024 addi s1,sp,8 +80015c62: 0000 unimp +80015c64: 03f0 addi a2,sp,460 +80015c66: 0000 unimp +80015c68: b290 fsd fa2,32(a3) +80015c6a: fffe fsw ft11,252(sp) +80015c6c: 00b0 addi a2,sp,72 +80015c6e: 0000 unimp +80015c70: 4400 lw s0,8(s0) +80015c72: 200e fld ft0,192(sp) +80015c74: 8148 0x8148 +80015c76: 8801 andi s0,s0,0 +80015c78: 4402 lw s0,0(sp) +80015c7a: 080c addi a1,sp,16 +80015c7c: 0200 addi s0,sp,256 +80015c7e: c194 sw a3,0(a1) +80015c80: c844 sw s1,20(s0) +80015c82: 020c addi a1,sp,256 +80015c84: 4420 lw s0,72(s0) +80015c86: 000e c.slli zero,0x3 +80015c88: 0024 addi s1,sp,8 +80015c8a: 0000 unimp +80015c8c: 0418 addi a4,sp,512 +80015c8e: 0000 unimp +80015c90: b318 fsd fa4,32(a4) +80015c92: fffe fsw ft11,252(sp) +80015c94: 0058 addi a4,sp,4 +80015c96: 0000 unimp +80015c98: 4400 lw s0,8(s0) +80015c9a: 100e c.slli zero,0x23 +80015c9c: 8148 0x8148 +80015c9e: 8801 andi s0,s0,0 +80015ca0: 4402 lw s0,0(sp) +80015ca2: 080c addi a1,sp,16 +80015ca4: 0200 addi s0,sp,256 +80015ca6: c13c sw a5,64(a0) +80015ca8: c844 sw s1,20(s0) +80015caa: 020c addi a1,sp,256 +80015cac: 4410 lw a2,8(s0) +80015cae: 000e c.slli zero,0x3 +80015cb0: 0024 addi s1,sp,8 +80015cb2: 0000 unimp +80015cb4: 0440 addi s0,sp,516 +80015cb6: 0000 unimp +80015cb8: b348 fsd fa0,160(a4) +80015cba: fffe fsw ft11,252(sp) +80015cbc: 00f8 addi a4,sp,76 +80015cbe: 0000 unimp +80015cc0: 4400 lw s0,8(s0) +80015cc2: 400e 0x400e +80015cc4: 8148 0x8148 +80015cc6: 8801 andi s0,s0,0 +80015cc8: 4402 lw s0,0(sp) +80015cca: 080c addi a1,sp,16 +80015ccc: 0200 addi s0,sp,256 +80015cce: c1dc sw a5,4(a1) +80015cd0: c844 sw s1,20(s0) +80015cd2: 020c addi a1,sp,256 +80015cd4: 4440 lw s0,12(s0) +80015cd6: 000e c.slli zero,0x3 +80015cd8: 0028 addi a0,sp,8 +80015cda: 0000 unimp +80015cdc: 0468 addi a0,sp,524 +80015cde: 0000 unimp +80015ce0: b418 fsd fa4,40(s0) +80015ce2: fffe fsw ft11,252(sp) +80015ce4: 01a0 addi s0,sp,200 +80015ce6: 0000 unimp +80015ce8: 4400 lw s0,8(s0) +80015cea: c00e sw gp,0(sp) +80015cec: 4801 li a6,0 +80015cee: 0181 addi gp,gp,0 +80015cf0: 0288 addi a0,sp,320 +80015cf2: 0c44 addi s1,sp,532 +80015cf4: 0008 0x8 +80015cf6: c1018403 lb s0,-1008(gp) # 80018c46 <__BSS_END__+0x200a> +80015cfa: c844 sw s1,20(s0) +80015cfc: 020c addi a1,sp,256 +80015cfe: 01c0 addi s0,sp,196 +80015d00: 0e44 addi s1,sp,788 +80015d02: 0000 unimp +80015d04: 0010 0x10 +80015d06: 0000 unimp +80015d08: 0494 addi a3,sp,576 +80015d0a: 0000 unimp +80015d0c: a6f4 fsd fa3,200(a3) +80015d0e: ffff 0xffff +80015d10: 0434 addi a3,sp,520 +80015d12: 0000 unimp +80015d14: 0000 unimp +80015d16: 0000 unimp +80015d18: 0010 0x10 +80015d1a: 0000 unimp +80015d1c: 04a8 addi a0,sp,584 +80015d1e: 0000 unimp +80015d20: ab14 fsd fa3,16(a4) +80015d22: ffff 0xffff +80015d24: 0410 addi a2,sp,512 +80015d26: 0000 unimp +80015d28: 0000 unimp ... Disassembly of section .init_array: 80016000 <__fini_array_end-0x4>: -80016000: 001c 0x1c +80016000: 0024 addi s1,sp,8 80016002: 8000 0x8000 Disassembly of section .data: @@ -23316,106 +23839,106 @@ Disassembly of section .data: 80016008: 0000 unimp ... -8001600c : -8001600c: 4a18 lw a4,16(a2) +8001600c <_ZL6hextoa>: +8001600c: 4950 lw a2,20(a0) 8001600e: 8001 c.srli64 s0 -80016010: 4a1c lw a5,16(a2) +80016010: 4954 lw a3,20(a0) 80016012: 8001 c.srli64 s0 -80016014: 4a20 lw s0,80(a2) +80016014: 4958 lw a4,20(a0) 80016016: 8001 c.srli64 s0 -80016018: 4a24 lw s1,80(a2) +80016018: 495c lw a5,20(a0) 8001601a: 8001 c.srli64 s0 -8001601c: 4a28 lw a0,80(a2) +8001601c: 4960 lw s0,84(a0) 8001601e: 8001 c.srli64 s0 -80016020: 4a2c lw a1,80(a2) +80016020: 4964 lw s1,84(a0) 80016022: 8001 c.srli64 s0 -80016024: 4a30 lw a2,80(a2) +80016024: 4968 lw a0,84(a0) 80016026: 8001 c.srli64 s0 -80016028: 4a34 lw a3,80(a2) +80016028: 496c lw a1,84(a0) 8001602a: 8001 c.srli64 s0 -8001602c: 4a38 lw a4,80(a2) +8001602c: 4970 lw a2,84(a0) 8001602e: 8001 c.srli64 s0 -80016030: 4a3c lw a5,80(a2) +80016030: 4974 lw a3,84(a0) 80016032: 8001 c.srli64 s0 -80016034: 4a40 lw s0,20(a2) +80016034: 4978 lw a4,84(a0) 80016036: 8001 c.srli64 s0 -80016038: 4a44 lw s1,20(a2) +80016038: 497c lw a5,84(a0) 8001603a: 8001 c.srli64 s0 -8001603c: 4a48 lw a0,20(a2) +8001603c: 4980 lw s0,16(a1) 8001603e: 8001 c.srli64 s0 -80016040: 4a4c lw a1,20(a2) +80016040: 4984 lw s1,16(a1) 80016042: 8001 c.srli64 s0 -80016044: 4a50 lw a2,20(a2) +80016044: 4988 lw a0,16(a1) 80016046: 8001 c.srli64 s0 -80016048: 4a54 lw a3,20(a2) +80016048: 498c lw a1,16(a1) 8001604a: 8001 c.srli64 s0 -8001604c : -8001604c: 4aa0 lw s0,80(a3) +8001604c <_ZL6hextoa>: +8001604c: 49d8 lw a4,20(a1) 8001604e: 8001 c.srli64 s0 -80016050: 4aa4 lw s1,80(a3) +80016050: 49dc lw a5,20(a1) 80016052: 8001 c.srli64 s0 -80016054: 4aa8 lw a0,80(a3) +80016054: 49e0 lw s0,84(a1) 80016056: 8001 c.srli64 s0 -80016058: 4aac lw a1,80(a3) +80016058: 49e4 lw s1,84(a1) 8001605a: 8001 c.srli64 s0 -8001605c: 4ab0 lw a2,80(a3) +8001605c: 49e8 lw a0,84(a1) 8001605e: 8001 c.srli64 s0 -80016060: 4ab4 lw a3,80(a3) +80016060: 49ec lw a1,84(a1) 80016062: 8001 c.srli64 s0 -80016064: 4ab8 lw a4,80(a3) +80016064: 49f0 lw a2,84(a1) 80016066: 8001 c.srli64 s0 -80016068: 4abc lw a5,80(a3) +80016068: 49f4 lw a3,84(a1) 8001606a: 8001 c.srli64 s0 -8001606c: 4ac0 lw s0,20(a3) +8001606c: 49f8 lw a4,84(a1) 8001606e: 8001 c.srli64 s0 -80016070: 4ac4 lw s1,20(a3) +80016070: 49fc lw a5,84(a1) 80016072: 8001 c.srli64 s0 -80016074: 4ac8 lw a0,20(a3) +80016074: 4a00 lw s0,16(a2) 80016076: 8001 c.srli64 s0 -80016078: 4acc lw a1,20(a3) +80016078: 4a04 lw s1,16(a2) 8001607a: 8001 c.srli64 s0 -8001607c: 4ad0 lw a2,20(a3) +8001607c: 4a08 lw a0,16(a2) 8001607e: 8001 c.srli64 s0 -80016080: 4ad4 lw a3,20(a3) +80016080: 4a0c lw a1,16(a2) 80016082: 8001 c.srli64 s0 -80016084: 4ad8 lw a4,20(a3) +80016084: 4a10 lw a2,16(a2) 80016086: 8001 c.srli64 s0 -80016088: 4adc lw a5,20(a3) +80016088: 4a14 lw a3,16(a2) 8001608a: 8001 c.srli64 s0 -8001608c : -8001608c: 4ae8 lw a0,84(a3) +8001608c <_ZL6hextoa>: +8001608c: 4a20 lw s0,80(a2) 8001608e: 8001 c.srli64 s0 -80016090: 4aec lw a1,84(a3) +80016090: 4a24 lw s1,80(a2) 80016092: 8001 c.srli64 s0 -80016094: 4af0 lw a2,84(a3) +80016094: 4a28 lw a0,80(a2) 80016096: 8001 c.srli64 s0 -80016098: 4af4 lw a3,84(a3) +80016098: 4a2c lw a1,80(a2) 8001609a: 8001 c.srli64 s0 -8001609c: 4af8 lw a4,84(a3) +8001609c: 4a30 lw a2,80(a2) 8001609e: 8001 c.srli64 s0 -800160a0: 4afc lw a5,84(a3) +800160a0: 4a34 lw a3,80(a2) 800160a2: 8001 c.srli64 s0 -800160a4: 4b00 lw s0,16(a4) +800160a4: 4a38 lw a4,80(a2) 800160a6: 8001 c.srli64 s0 -800160a8: 4b04 lw s1,16(a4) +800160a8: 4a3c lw a5,80(a2) 800160aa: 8001 c.srli64 s0 -800160ac: 4b08 lw a0,16(a4) +800160ac: 4a40 lw s0,20(a2) 800160ae: 8001 c.srli64 s0 -800160b0: 4b0c lw a1,16(a4) +800160b0: 4a44 lw s1,20(a2) 800160b2: 8001 c.srli64 s0 -800160b4: 4b10 lw a2,16(a4) +800160b4: 4a48 lw a0,20(a2) 800160b6: 8001 c.srli64 s0 -800160b8: 4b14 lw a3,16(a4) +800160b8: 4a4c lw a1,20(a2) 800160ba: 8001 c.srli64 s0 -800160bc: 4b18 lw a4,16(a4) +800160bc: 4a50 lw a2,20(a2) 800160be: 8001 c.srli64 s0 -800160c0: 4b1c lw a5,16(a4) +800160c0: 4a54 lw a3,20(a2) 800160c2: 8001 c.srli64 s0 -800160c4: 4b20 lw s0,80(a4) +800160c4: 4a58 lw a4,20(a2) 800160c6: 8001 c.srli64 s0 -800160c8: 4b24 lw s1,80(a4) +800160c8: 4a5c lw a5,20(a2) 800160ca: 8001 c.srli64 s0 800160cc : @@ -23428,38 +23951,38 @@ Disassembly of section .data: 800160d8: 0005 c.nop 1 ... -800160dc : -800160dc: 4b5c lw a5,20(a4) +800160dc <_ZL6hextoa>: +800160dc: 4a94 lw a3,16(a3) 800160de: 8001 c.srli64 s0 -800160e0: 4b60 lw s0,84(a4) +800160e0: 4a98 lw a4,16(a3) 800160e2: 8001 c.srli64 s0 -800160e4: 4b64 lw s1,84(a4) +800160e4: 4a9c lw a5,16(a3) 800160e6: 8001 c.srli64 s0 -800160e8: 4b68 lw a0,84(a4) +800160e8: 4aa0 lw s0,80(a3) 800160ea: 8001 c.srli64 s0 -800160ec: 4b6c lw a1,84(a4) +800160ec: 4aa4 lw s1,80(a3) 800160ee: 8001 c.srli64 s0 -800160f0: 4b70 lw a2,84(a4) +800160f0: 4aa8 lw a0,80(a3) 800160f2: 8001 c.srli64 s0 -800160f4: 4b74 lw a3,84(a4) +800160f4: 4aac lw a1,80(a3) 800160f6: 8001 c.srli64 s0 -800160f8: 4b78 lw a4,84(a4) +800160f8: 4ab0 lw a2,80(a3) 800160fa: 8001 c.srli64 s0 -800160fc: 4b7c lw a5,84(a4) +800160fc: 4ab4 lw a3,80(a3) 800160fe: 8001 c.srli64 s0 -80016100: 4b80 lw s0,16(a5) +80016100: 4ab8 lw a4,80(a3) 80016102: 8001 c.srli64 s0 -80016104: 4b84 lw s1,16(a5) +80016104: 4abc lw a5,80(a3) 80016106: 8001 c.srli64 s0 -80016108: 4b88 lw a0,16(a5) +80016108: 4ac0 lw s0,20(a3) 8001610a: 8001 c.srli64 s0 -8001610c: 4b8c lw a1,16(a5) +8001610c: 4ac4 lw s1,20(a3) 8001610e: 8001 c.srli64 s0 -80016110: 4b90 lw a2,16(a5) +80016110: 4ac8 lw a0,20(a3) 80016112: 8001 c.srli64 s0 -80016114: 4b94 lw a3,16(a5) +80016114: 4acc lw a1,20(a3) 80016116: 8001 c.srli64 s0 -80016118: 4b98 lw a4,16(a5) +80016118: 4ad0 lw a2,20(a3) 8001611a: 8001 c.srli64 s0 8001611c : @@ -24081,33 +24604,33 @@ Disassembly of section .data: ... 80016a90: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne ... -80016ab0: 0494 addi a3,sp,576 +80016ab0: 03d0 addi a2,sp,452 80016ab2: 8001 c.srli64 s0 -80016ab4: e438 fsw fa4,72(s0) +80016ab4: e374 fsw fa3,68(a4) 80016ab6: 8000 0x8000 80016ab8: 0000 unimp 80016aba: 0000 unimp -80016abc: 5694 lw a3,40(a3) +80016abc: 55bc lw a5,104(a1) 80016abe: 8001 c.srli64 s0 -80016ac0: 5504 lw s1,40(a0) +80016ac0: 542c lw a1,104(s0) 80016ac2: 8001 c.srli64 s0 -80016ac4: 4c9c lw a5,24(s1) +80016ac4: 4bc8 lw a0,20(a5) 80016ac6: 8001 c.srli64 s0 -80016ac8: 4c9c lw a5,24(s1) +80016ac8: 4bc8 lw a0,20(a5) 80016aca: 8001 c.srli64 s0 -80016acc: 4c9c lw a5,24(s1) +80016acc: 4bc8 lw a0,20(a5) 80016ace: 8001 c.srli64 s0 -80016ad0: 4c9c lw a5,24(s1) +80016ad0: 4bc8 lw a0,20(a5) 80016ad2: 8001 c.srli64 s0 -80016ad4: 4c9c lw a5,24(s1) +80016ad4: 4bc8 lw a0,20(a5) 80016ad6: 8001 c.srli64 s0 -80016ad8: 4c9c lw a5,24(s1) +80016ad8: 4bc8 lw a0,20(a5) 80016ada: 8001 c.srli64 s0 -80016adc: 4c9c lw a5,24(s1) +80016adc: 4bc8 lw a0,20(a5) 80016ade: 8001 c.srli64 s0 -80016ae0: 4c9c lw a5,24(s1) +80016ae0: 4bc8 lw a0,20(a5) 80016ae2: 8001 c.srli64 s0 -80016ae4: 4c9c lw a5,24(s1) +80016ae4: 4bc8 lw a0,20(a5) 80016ae6: 8001 c.srli64 s0 80016ae8: ffff 0xffff 80016aea: ffff 0xffff @@ -24150,11 +24673,11 @@ Disassembly of section .sdata: 80016b5c: 0000 unimp 80016b5e: 7000 flw fs0,32(s0) -80016b60 : +80016b60 <_ZL10heap_start>: 80016b60: 0000 unimp 80016b62: 1000 addi s0,sp,32 -80016b64 : +80016b64 <_ZL8head_end>: 80016b64: 0000 unimp 80016b66: 2000 fld fs0,0(s0) @@ -24172,78 +24695,78 @@ Disassembly of section .sdata: Disassembly of section .sbss: -80016b74 <__malloc_max_total_mem>: +80016b74 : 80016b74: 0000 unimp ... -80016b78 <__malloc_max_sbrked_mem>: +80016b78 : 80016b78: 0000 unimp ... -80016b7c <__malloc_top_pad>: +80016b7c : 80016b7c: 0000 unimp ... -80016b80 <_PathLocale>: +80016b80 : 80016b80: 0000 unimp ... +80016b84 : +80016b84: 0000 unimp + ... + +80016b88 : +80016b88: 0000 unimp + ... + +80016b8c : +80016b8c: 0000 unimp + ... + +80016b90 : +80016b90: 0000 unimp + ... + +80016b94 : +80016b94: 0000 unimp + ... + +80016b98 : +80016b98: 0000 unimp + ... + +80016b9c <__malloc_max_total_mem>: +80016b9c: 0000 unimp + ... + +80016ba0 <__malloc_max_sbrked_mem>: +80016ba0: 0000 unimp + ... + +80016ba4 <__malloc_top_pad>: +80016ba4: 0000 unimp + ... + +80016ba8 <_PathLocale>: +80016ba8: 0000 unimp + ... + Disassembly of section .bss: -80016b84 : -80016b84: 0000 unimp +80016bac <_ZL9curr_time>: +80016bac: 0000 unimp ... -80016b88 : +80016bb0 : ... -80016bc8 <__malloc_current_mallinfo>: +80016bc0 : ... -80016bf0 : -80016bf0: 0000 unimp +80016bd0 : ... -80016bf4 : -80016bf4: 0000 unimp - ... - -80016bf8 : -80016bf8: 0000 unimp - ... - -80016bfc : -80016bfc: 0000 unimp - ... - -80016c00 : -80016c00: 0000 unimp - ... - -80016c04 : -80016c04: 0000 unimp - ... - -80016c08 : -80016c08: 0000 unimp - ... - -80016c0c : -80016c0c: 0000 unimp - ... - -80016c10 : -80016c10: 0000 unimp - ... - -80016c14 : -80016c14: 0000 unimp - ... - -80016c18 : - ... - -80016c28 : +80016c10 <__malloc_current_mallinfo>: ... 80016c38 : @@ -24292,7 +24815,7 @@ Disassembly of section .debug_aranges: a: 0004 0x4 c: 0000 unimp e: 0000 unimp - 10: 04c4 addi s1,sp,580 + 10: 0400 addi s0,sp,512 12: 8001 c.srli64 s0 14: 0434 addi a3,sp,520 ... @@ -24305,7 +24828,7 @@ Disassembly of section .debug_aranges: 2a: 0004 0x4 2c: 0000 unimp 2e: 0000 unimp - 30: 08f8 addi a4,sp,92 + 30: 0834 addi a3,sp,24 32: 8001 c.srli64 s0 34: 0410 addi a2,sp,512 ... @@ -24318,7 +24841,7 @@ Disassembly of section .debug_aranges: 4a: 0004 0x4 4c: 0000 unimp 4e: 0000 unimp - 50: 0d08 addi a0,sp,656 + 50: 0c44 addi s1,sp,532 52: 8001 c.srli64 s0 54: 06e0 addi s0,sp,844 ... @@ -24331,7 +24854,7 @@ Disassembly of section .debug_aranges: 6a: 0004 0x4 6c: 0000 unimp 6e: 0000 unimp - 70: 13e8 addi a0,sp,492 + 70: 1324 addi s1,sp,424 72: 8001 c.srli64 s0 74: 05c4 addi s1,sp,708 ... @@ -24344,7 +24867,7 @@ Disassembly of section .debug_aranges: 8a: 0004 0x4 8c: 0000 unimp 8e: 0000 unimp - 90: 19ac addi a1,sp,248 + 90: 18e8 addi a0,sp,124 92: 8001 c.srli64 s0 94: 00cc addi a1,sp,68 ... @@ -24357,7 +24880,7 @@ Disassembly of section .debug_aranges: aa: 0004 0x4 ac: 0000 unimp ae: 0000 unimp - b0: 1a78 addi a4,sp,316 + b0: 19b4 addi a3,sp,248 b2: 8001 c.srli64 s0 b4: 0144 addi s1,sp,132 ... @@ -24370,7 +24893,7 @@ Disassembly of section .debug_aranges: ca: 0004 0x4 cc: 0000 unimp ce: 0000 unimp - d0: 1bbc addi a5,sp,504 + d0: 1af8 addi a4,sp,380 d2: 8001 c.srli64 s0 d4: 0144 addi s1,sp,132 ... @@ -24383,7 +24906,7 @@ Disassembly of section .debug_aranges: ea: 0004 0x4 ec: 0000 unimp ee: 0000 unimp - f0: 1d00 addi s0,sp,688 + f0: 1c3c addi a5,sp,568 f2: 8001 c.srli64 s0 f4: 1004 addi s1,sp,32 ... @@ -24396,7 +24919,7 @@ Disassembly of section .debug_aranges: 10a: 0004 0x4 10c: 0000 unimp 10e: 0000 unimp - 110: 2d04 fld fs1,24(a0) + 110: 2c40 fld fs0,152(s0) 112: 8001 c.srli64 s0 114: 1520 addi s0,sp,680 ... @@ -24409,7 +24932,7 @@ Disassembly of section .debug_aranges: 12a: 0004 0x4 12c: 0000 unimp 12e: 0000 unimp - 130: 4224 lw s1,64(a2) + 130: 4160 lw s0,68(a0) 132: 8001 c.srli64 s0 134: 0114 addi a3,sp,128 ... @@ -24422,7 +24945,7 @@ Disassembly of section .debug_aranges: 14a: 0004 0x4 14c: 0000 unimp 14e: 0000 unimp - 150: 4338 lw a4,64(a4) + 150: 4274 lw a3,68(a2) 152: 8001 c.srli64 s0 154: 0150 addi a2,sp,132 ... @@ -24435,7 +24958,7 @@ Disassembly of section .debug_aranges: 16a: 0004 0x4 16c: 0000 unimp 16e: 0000 unimp - 170: 4488 lw a0,8(s1) + 170: 43c4 lw s1,4(a5) 172: 8001 c.srli64 s0 174: 01f4 addi a3,sp,204 ... @@ -24448,7 +24971,7 @@ Disassembly of section .debug_aranges: 18a: 0004 0x4 18c: 0000 unimp 18e: 0000 unimp - 190: 467c lw a5,76(a2) + 190: 45b8 lw a4,72(a1) 192: 8001 c.srli64 s0 194: 034c addi a1,sp,388 ... @@ -24467,7 +24990,7 @@ Disassembly of section .debug_aranges: 1c2: 0004 0x4 1c4: 0000 unimp 1c6: 0000 unimp - 1c8: 49c8 lw a0,20(a1) + 1c8: 4904 lw s1,16(a0) 1ca: 8001 c.srli64 s0 1cc: 004c addi a1,sp,4 ... @@ -24487,7 +25010,7 @@ Disassembly of section .debug_info: 12: 0004 0x4 14: ed00 fsw fs0,24(a0) 16: 0005 c.nop 1 - 18: c400 sw s0,8(s0) + 18: 0000 unimp 1a: 0104 addi s1,sp,128 1c: 3480 fld fs0,40(s1) 1e: 0004 0x4 @@ -25784,7 +26307,7 @@ Disassembly of section .debug_info: bf8: 0105 addi sp,sp,1 bfa: 0b34 addi a3,sp,408 bfc: 0000 unimp - bfe: 04c4 addi s1,sp,580 + bfe: 0400 addi s0,sp,512 c00: 8001 c.srli64 s0 c02: 0434 addi a3,sp,520 c04: 0000 unimp @@ -25807,7 +26330,7 @@ Disassembly of section .debug_info: c28: 0000 unimp c2a: cd29 beqz a0,c84 <_start-0x7ffff37c> c2c: 000e c.slli zero,0x3 - c2e: c800 sw s0,16(s0) + c2e: 0400 addi s0,sp,512 c30: 0104 addi s1,sp,128 c32: 0080 addi s0,sp,64 c34: 0000 unimp @@ -25885,8 +26408,8 @@ Disassembly of section .debug_info: cdc: 0005 c.nop 1 cde: 0000 unimp ce0: 000fbc2f 0xfbc2f - ce4: 2c00 fld fs0,24(s0) - ce6: 0105 addi sp,sp,1 + ce4: 6800 flw fs0,16(s0) + ce6: 0104 addi s1,sp,128 ce8: 8880 0x8880 cea: 0000 unimp cec: 3100 fld fs0,32(a0) @@ -26025,8 +26548,8 @@ Disassembly of section .debug_info: e0c: 0009 c.nop 2 e0e: 0000 unimp e10: 00109e2f 0x109e2f - e14: 1400 addi s0,sp,544 - e16: 0106 slli sp,sp,0x1 + e14: 5000 lw s0,32(s0) + e16: 0105 addi sp,sp,1 e18: 8880 0x8880 e1a: 0000 unimp e1c: 6100 flw fs0,0(a0) @@ -26482,7 +27005,7 @@ Disassembly of section .debug_info: 1258: 0000 unimp 125a: 05ed addi a1,a1,27 125c: 0000 unimp - 125e: 08f8 addi a4,sp,92 + 125e: 0834 addi a3,sp,24 1260: 8001 c.srli64 s0 1262: 0410 addi a2,sp,512 1264: 0000 unimp @@ -27814,7 +28337,7 @@ Disassembly of section .debug_info: 1e3a: 0100 addi s0,sp,128 1e3c: 051a slli a0,a0,0x6 1e3e: 3401 jal 183e <_start-0x7fffe7c2> - 1e40: f800000b 0xf800000b + 1e40: 3400000b 0x3400000b 1e44: 0108 addi a0,sp,128 1e46: 1080 addi s0,sp,96 1e48: 0004 0x4 @@ -27841,7 +28364,7 @@ Disassembly of section .debug_info: 1e7a: 0d05 addi s10,s10,1 1e7c: 0000 unimp 1e7e: 292a fld fs2,136(sp) - 1e80: f800000f 0xf800000f + 1e80: 3400000f 0x3400000f 1e84: 0108 addi a0,sp,128 1e86: 0080 addi s0,sp,64 1e88: 0001 nop @@ -27920,8 +28443,8 @@ Disassembly of section .debug_info: 1f32: 0000 unimp 1f34: 1830 addi a2,sp,56 1f36: 0010 0x10 - 1f38: 5c00 lw s0,56(s0) - 1f3a: 0109 addi sp,sp,2 + 1f38: 9800 0x9800 + 1f3a: 0108 addi a0,sp,128 1f3c: 7080 flw fs0,32(s1) 1f3e: 0000 unimp 1f40: 3c00 fld fs0,56(s0) @@ -27969,7 +28492,7 @@ Disassembly of section .debug_info: 1fa0: 3000 fld fs0,32(s0) 1fa2: 10fa slli ra,ra,0x3e 1fa4: 0000 unimp - 1fa6: 0a2c addi a1,sp,280 + 1fa6: 0968 addi a0,sp,156 1fa8: 8001 c.srli64 s0 1faa: 0074 addi a3,sp,12 1fac: 0000 unimp @@ -28058,7 +28581,7 @@ Disassembly of section .debug_info: 205c: 0000 unimp 205e: 3000 fld fs0,32(s0) 2060: 0000117b 0x117b - 2064: 0b84 addi s1,sp,464 + 2064: 0ac0 addi s0,sp,340 2066: 8001 c.srli64 s0 2068: 0010 0x10 206a: 0000 unimp @@ -28070,8 +28593,9 @@ Disassembly of section .debug_info: 2076: 00000013 nop 207a: 8e31 xor a2,a2,a2 207c: 0011 c.nop 4 - 207e: b400 fsd fs0,40(s0) - 2080: 5480010b 0x5480010b + 207e: f000 fsw fs0,32(s0) + 2080: 010a slli sp,sp,0x2 + 2082: 5480 lw s0,40(s1) 2084: 0001 nop 2086: 3200 fld fs0,32(a2) 2088: 0000118f 0x118f @@ -28148,7 +28672,7 @@ Disassembly of section .debug_info: 2136: 005d c.nop 23 2138: 7630 flw fa2,104(a2) 213a: 0012 c.slli zero,0x4 - 213c: d000 sw s0,32(s0) + 213c: 0c00 addi s0,sp,528 213e: 010c addi a1,sp,128 2140: 1480 addi s0,sp,608 2142: 0000 unimp @@ -28160,7 +28684,7 @@ Disassembly of section .debug_info: 2152: 3100 fld fs0,32(a0) 2154: 1289 addi t0,t0,-30 2156: 0000 unimp - 2158: 0ce4 addi s1,sp,604 + 2158: 0c20 addi s0,sp,536 215a: 8001 c.srli64 s0 215c: 0010 0x10 215e: 0000 unimp @@ -28537,8 +29061,8 @@ Disassembly of section .debug_info: 24f8: 0009 c.nop 2 24fa: ed00 fsw fs0,24(a0) 24fc: 0005 c.nop 1 - 24fe: 0800 addi s0,sp,16 - 2500: 010d addi sp,sp,3 + 24fe: 4400 lw s0,8(s0) + 2500: 010c addi a1,sp,128 2502: e080 fsw fs0,0(s1) 2504: 0006 c.slli zero,0x1 2506: a800 fsd fs0,16(s0) @@ -28656,8 +29180,8 @@ Disassembly of section .debug_info: 2604: 2301 jal 2b04 <_start-0x7fffd4fc> 2606: 9d01 0x9d01 2608: 0000 unimp - 260a: 0800 addi s0,sp,16 - 260c: 010d addi sp,sp,3 + 260a: 4400 lw s0,8(s0) + 260c: 010c addi a1,sp,128 260e: e080 fsw fs0,0(s1) 2610: 0006 c.slli zero,0x1 2612: 0100 addi s0,sp,128 @@ -28937,7 +29461,7 @@ Disassembly of section .debug_info: 289a: 219c fld fa5,0(a1) 289c: 0000 unimp 289e: 1800 addi s0,sp,48 - 28a0: 1004 addi s1,sp,32 + 28a0: 0f40 addi s0,sp,916 28a2: 8001 c.srli64 s0 28a4: 0058 addi a4,sp,4 28a6: 0000 unimp @@ -29023,7 +29547,7 @@ Disassembly of section .debug_info: 295a: 0000 unimp 295c: 0000238b 0x238b 2960: 1800 addi s0,sp,48 - 2962: 10ac addi a1,sp,104 + 2962: 0fe8 addi a0,sp,988 2964: 8001 c.srli64 s0 2966: 0010 0x10 2968: 0000 unimp @@ -29173,8 +29697,8 @@ Disassembly of section .debug_info: 2aae: 263d jal 2ddc <_start-0x7fffd224> 2ab0: 0000 unimp 2ab2: 0000 unimp - 2ab4: 0418 addi a4,sp,512 - 2ab6: 0112 slli sp,sp,0x4 + 2ab4: 4018 lw a4,0(s0) + 2ab6: 0111 addi sp,sp,4 2ab8: 1080 addi s0,sp,96 2aba: 0000 unimp 2abc: ec00 fsw fs0,24(s0) @@ -29245,7 +29769,7 @@ Disassembly of section .debug_info: 2b78: 00072803 lw a6,0(a4) 2b7c: 0000 unimp 2b7e: 1800 addi s0,sp,48 - 2b80: 1348 addi a0,sp,420 + 2b80: 1284 addi s1,sp,352 2b82: 8001 c.srli64 s0 2b84: 0010 0x10 2b86: 0000 unimp @@ -29311,7 +29835,7 @@ Disassembly of section .debug_info: 2c26: 800c 0x800c 2c28: ed00000b 0xed00000b 2c2c: 0005 c.nop 1 - 2c2e: e800 fsw fs0,16(s0) + 2c2e: 2400 fld fs0,8(s0) 2c30: c4800113 li sp,-952 2c34: 0005 c.nop 1 2c36: 4300 lw s0,0(a4) @@ -29429,7 +29953,7 @@ Disassembly of section .debug_info: 2d34: 2301 jal 3234 <_start-0x7fffcdcc> 2d36: 9d01 0x9d01 2d38: 0000 unimp - 2d3a: e800 fsw fs0,16(s0) + 2d3a: 2400 fld fs0,8(s0) 2d3c: c4800113 li sp,-952 2d40: 0005 c.nop 1 2d42: 0100 addi s0,sp,128 @@ -29933,7 +30457,7 @@ Disassembly of section .debug_info: 31fc: b300 fsd fs0,32(a4) 31fe: 00000033 add zero,zero,zero 3202: 0000 unimp - 3204: f019 bnez s0,310a <_start-0x7fffcef6> + 3204: 2c19 jal 341a <_start-0x7fffcbe6> 3206: 10800117 auipc sp,0x10800 320a: 0000 unimp 320c: 0c00 addi s0,sp,528 @@ -30004,7 +30528,7 @@ Disassembly of section .debug_info: 32c8: 00074803 lbu a6,0(a4) 32cc: 0000 unimp 32ce: 1900 addi s0,sp,176 - 32d0: 1914 addi a3,sp,176 + 32d0: 1850 addi a2,sp,52 32d2: 8001 c.srli64 s0 32d4: 0010 0x10 32d6: 0000 unimp @@ -30077,8 +30601,8 @@ Disassembly of section .debug_info: 3384: 000c 0xc 3386: ed00 fsw fs0,24(a0) 3388: 0005 c.nop 1 - 338a: ac00 fsd fs0,24(s0) - 338c: 0119 addi sp,sp,6 + 338a: e800 fsw fs0,16(s0) + 338c: 0118 addi a4,sp,128 338e: cc80 sw s0,24(s1) 3390: 0000 unimp 3392: 1900 addi s0,sp,176 @@ -30209,8 +30733,8 @@ Disassembly of section .debug_info: 34b6: 2301 jal 39b6 <_start-0x7fffc64a> 34b8: 2501 jal 3ab8 <_start-0x7fffc548> 34ba: 0000 unimp - 34bc: ac00 fsd fs0,24(s0) - 34be: 0119 addi sp,sp,6 + 34bc: e800 fsw fs0,16(s0) + 34be: 0118 addi a4,sp,128 34c0: cc80 sw s0,24(s1) 34c2: 0000 unimp 34c4: 0100 addi s0,sp,128 @@ -30362,8 +30886,8 @@ Disassembly of section .debug_info: 361c: 000c 0xc 361e: ed00 fsw fs0,24(a0) 3620: 0005 c.nop 1 - 3622: 7800 flw fs0,48(s0) - 3624: 011a slli sp,sp,0x6 + 3622: b400 fsd fs0,40(s0) + 3624: 0119 addi sp,sp,6 3626: 4480 lw s0,8(s1) 3628: 0001 nop 362a: fb00 fsw fs0,48(a4) @@ -30494,8 +31018,8 @@ Disassembly of section .debug_info: 374e: 2301 jal 3c4e <_start-0x7fffc3b2> 3750: 2501 jal 3d50 <_start-0x7fffc2b0> 3752: 0000 unimp - 3754: 7800 flw fs0,48(s0) - 3756: 011a slli sp,sp,0x6 + 3754: b400 fsd fs0,40(s0) + 3756: 0119 addi sp,sp,6 3758: 4480 lw s0,8(s1) 375a: 0001 nop 375c: 0100 addi s0,sp,128 @@ -30650,8 +31174,9 @@ Disassembly of section .debug_info: 38b2: 000c 0xc 38b4: ed00 fsw fs0,24(a0) 38b6: 0005 c.nop 1 - 38b8: bc00 fsd fs0,56(s0) - 38ba: 4480011b 0x4480011b + 38b8: f800 fsw fs0,48(s0) + 38ba: 011a slli sp,sp,0x6 + 38bc: 4480 lw s0,8(s1) 38be: 0001 nop 38c0: b800 fsd fs0,48(s0) 38c2: 0036 c.slli zero,0xd @@ -30780,8 +31305,9 @@ Disassembly of section .debug_info: 39e4: 2301 jal 3ee4 <_start-0x7fffc11c> 39e6: 2501 jal 3fe6 <_start-0x7fffc01a> 39e8: 0000 unimp - 39ea: bc00 fsd fs0,56(s0) - 39ec: 4480011b 0x4480011b + 39ea: f800 fsw fs0,48(s0) + 39ec: 011a slli sp,sp,0x6 + 39ee: 4480 lw s0,8(s1) 39f0: 0001 nop 39f2: 0100 addi s0,sp,128 39f4: 829c 0x829c @@ -30934,8 +31460,8 @@ Disassembly of section .debug_info: 3b46: 120c addi a1,sp,288 3b48: ed00000f 0xed00000f 3b4c: 0005 c.nop 1 - 3b4e: 0000 unimp - 3b50: 011d addi sp,sp,7 + 3b4e: 3c00 fld fs0,56(s0) + 3b50: 011c addi a5,sp,128 3b52: 0480 addi s0,sp,576 3b54: 0010 0x10 3b56: 7500 flw fs0,40(a0) @@ -31062,7 +31588,7 @@ Disassembly of section .debug_info: 3c7a: 0100 addi s0,sp,128 3c7c: 00960123 sb s1,2(a2) 3c80: 0000 unimp - 3c82: 1d00 addi s0,sp,688 + 3c82: 1c3c addi a5,sp,568 3c84: 8001 c.srli64 s0 3c86: 1004 addi s1,sp,32 3c88: 0000 unimp @@ -32598,7 +33124,7 @@ Disassembly of section .debug_info: 4aaa: 00a4 addi s1,sp,72 4aac: 0000 unimp 4aae: 1a00 addi s0,sp,304 - 4ab0: 2878 fld fa4,208(s0) + 4ab0: 27b4 fld fa3,72(a5) 4ab2: 8001 c.srli64 s0 4ab4: 0048 addi a0,sp,4 4ab6: 0000 unimp @@ -32610,7 +33136,7 @@ Disassembly of section .debug_info: 4ac2: 032e slli t1,t1,0xb 4ac4: 0025 c.nop 9 4ac6: 0000 unimp - 4ac8: 0128781b 0x128781b + 4ac8: 0127b41b 0x127b41b 4acc: 3c80 fld fs0,56(s1) 4ace: 0000 unimp 4ad0: 1200 addi s0,sp,288 @@ -32649,7 +33175,7 @@ Disassembly of section .debug_info: 4b1e: 00a5 addi ra,ra,9 4b20: 0000 unimp 4b22: 1a00 addi s0,sp,304 - 4b24: 28ec fld fa1,208(s1) + 4b24: 2828 fld fa0,80(s0) 4b26: 8001 c.srli64 s0 4b28: 0038 addi a4,sp,8 4b2a: 0000 unimp @@ -32756,8 +33282,8 @@ Disassembly of section .debug_info: 4c24: 0113032f 0x113032f 4c28: 0000 unimp 4c2a: 0000 unimp - 4c2c: c01a sw t1,0(sp) - 4c2e: 012a slli sp,sp,0xa + 4c2c: fc1a fsw ft6,56(sp) + 4c2e: 0129 addi sp,sp,10 4c30: 2880 fld fs0,16(s1) 4c32: 0001 nop 4c34: 6a00 flw fs0,16(a2) @@ -32807,7 +33333,7 @@ Disassembly of section .debug_info: 4c9a: a96e fsd fs11,144(sp) 4c9c: 0000 unimp 4c9e: 0000 unimp - 4ca0: f81a fsw ft6,48(sp) + 4ca0: 341a fld fs0,416(sp) 4ca2: 3880012b 0x3880012b 4ca6: 0000 unimp 4ca8: 8800 0x8800 @@ -32836,9 +33362,8 @@ Disassembly of section .debug_info: 4cda: 2f01 jal 53ea <_start-0x7fffac16> 4cdc: 00011303 lh t1,0(sp) 4ce0: 0000 unimp - 4ce2: 5c1a lw s8,164(sp) - 4ce4: 012c addi a1,sp,136 - 4ce6: 2c80 fld fs0,24(s1) + 4ce2: 981a add a6,a6,t1 + 4ce4: 2c80012b 0x2c80012b 4ce8: 0000 unimp 4cea: ee00 fsw fs0,24(a2) 4cec: 0011 c.nop 4 @@ -32919,8 +33444,8 @@ Disassembly of section .debug_info: 4da4: 0010 0x10 4da6: ed00 fsw fs0,24(a0) 4da8: 0005 c.nop 1 - 4daa: 0400 addi s0,sp,512 - 4dac: 012d addi sp,sp,11 + 4daa: 4000 lw s0,0(s0) + 4dac: 012c addi a1,sp,136 4dae: 2080 fld fs0,0(s1) 4db0: 0015 c.nop 5 4db2: 9c00 0x9c00 @@ -33046,8 +33571,8 @@ Disassembly of section .debug_info: 4eca: 2301 jal 53ca <_start-0x7fffac36> 4ecc: 8901 andi a0,a0,0 4ece: 0000 unimp - 4ed0: 0400 addi s0,sp,512 - 4ed2: 012d addi sp,sp,11 + 4ed0: 4000 lw s0,0(s0) + 4ed2: 012c addi a1,sp,136 4ed4: 2080 fld fs0,0(s1) 4ed6: 0015 c.nop 5 4ed8: 0100 addi s0,sp,128 @@ -33220,21 +33745,21 @@ Disassembly of section .debug_info: 5092: 1118 addi a4,sp,160 5094: 0000 unimp 5096: 2e01 jal 53a6 <_start-0x7fffac5a> - 5098: 01309c03 lh s8,19(ra) + 5098: 012fd803 lhu a6,18(t6) 509c: 1980 addi s0,sp,240 509e: 0fde slli t6,t6,0x17 50a0: 0000 unimp 50a2: 2e01 jal 53b2 <_start-0x7fffac4e> - 50a4: 0133a003 lw zero,19(t2) + 50a4: 0132dc03 lhu s8,19(t0) # b013 <_start-0x7fff4fed> 50a8: 1980 addi s0,sp,240 50aa: 111d addi sp,sp,-25 50ac: 0000 unimp 50ae: 2e01 jal 53be <_start-0x7fffac42> - 50b0: 01321803 lh a6,19(tp) # fffe5013 <__BSS_END__+0x7ffce3d7> + 50b0: 01315403 lhu s0,19(sp) 50b4: 1980 addi s0,sp,240 50b6: 00000fe3 beqz zero,58d4 <_start-0x7fffa72c> 50ba: 2e01 jal 53ca <_start-0x7fffac36> - 50bc: 012f3403 0x12f3403 + 50bc: 012e7003 0x12e7003 50c0: 1280 addi s0,sp,352 50c2: 10e5 addi ra,ra,-7 50c4: 0000 unimp @@ -33243,7 +33768,7 @@ Disassembly of section .debug_info: 50cc: a400 fsd fs0,8(s0) 50ce: 00b1 addi ra,ra,12 50d0: 1a00 addi s0,sp,304 - 50d2: 2ea0 fld fs0,88(a3) + 50d2: 2ddc fld fa5,152(a1) 50d4: 8001 c.srli64 s0 50d6: 0048 addi a0,sp,4 50d8: 0000 unimp @@ -33274,7 +33799,7 @@ Disassembly of section .debug_info: 510a: b3be fsd fa5,480(sp) 510c: 0000 unimp 510e: 1a00 addi s0,sp,304 - 5110: 30a8 fld fa0,96(s1) + 5110: 2fe4 fld fs1,216(a5) 5112: 8001 c.srli64 s0 5114: 0114 addi a3,sp,128 5116: 0000 unimp @@ -33325,7 +33850,7 @@ Disassembly of section .debug_info: 517e: 00b5 addi ra,ra,13 5180: 0000 unimp 5182: 1a00 addi s0,sp,304 - 5184: 31c0 fld fs0,160(a1) + 5184: 30fc fld fa5,224(s1) 5186: 8001 c.srli64 s0 5188: 0058 addi a4,sp,4 518a: 0000 unimp @@ -33355,7 +33880,7 @@ Disassembly of section .debug_info: 51bc: b5ec fsd fa1,232(a1) 51be: 0000 unimp 51c0: 1a00 addi s0,sp,304 - 51c2: 32f8 fld fa4,224(a3) + 51c2: 3234 fld fa3,96(a2) 51c4: 8001 c.srli64 s0 51c6: 004c addi a1,sp,4 51c8: 0000 unimp @@ -33384,7 +33909,7 @@ Disassembly of section .debug_info: 51f8: 0000 unimp 51fa: 0000b6bb 0xb6bb 51fe: 1a00 addi s0,sp,304 - 5200: 33ac fld fa1,96(a5) + 5200: 32e8 fld fa0,224(a3) 5202: 8001 c.srli64 s0 5204: 0128 addi a0,sp,136 5206: 0000 unimp @@ -33530,7 +34055,7 @@ Disassembly of section .debug_info: 5348: 032e slli t1,t1,0xb 534a: 00000df7 0xdf7 534e: 1a00 addi s0,sp,304 - 5350: 3668 fld fa0,232(a2) + 5350: 35a4 fld fs1,104(a1) 5352: 8001 c.srli64 s0 5354: 0024 addi s1,sp,8 5356: 0000 unimp @@ -33563,7 +34088,7 @@ Disassembly of section .debug_info: 5398: ba22 fsd fs0,304(sp) 539a: 0000 unimp 539c: 1a00 addi s0,sp,304 - 539e: 36a8 fld fa0,104(a3) + 539e: 35e4 fld fs1,232(a1) 53a0: 8001 c.srli64 s0 53a2: 0048 addi a0,sp,4 53a4: 0000 unimp @@ -33691,27 +34216,27 @@ Disassembly of section .debug_info: 54c2: 1006 c.slli zero,0x21 54c4: 0000 unimp 54c6: 2e01 jal 57d6 <_start-0x7fffa82a> - 54c8: 01385003 lhu zero,19(a6) # 1064cb <_start-0x7fef9b35> + 54c8: 01378c03 lb s8,19(a5) # fffe3013 <__BSS_END__+0x7ffcc3d7> 54cc: 1980 addi s0,sp,240 54ce: 0fec addi a1,sp,988 54d0: 0000 unimp 54d2: 2e01 jal 57e2 <_start-0x7fffa81e> - 54d4: 013b1003 lh zero,19(s6) # 5f6a5 <_start-0x7ffa095b> + 54d4: 013a4c03 lbu s8,19(s4) # 17013 <_start-0x7ffe8fed> 54d8: 1980 addi s0,sp,240 54da: 10e0 addi s0,sp,108 54dc: 0000 unimp 54de: 2e01 jal 57ee <_start-0x7fffa812> - 54e0: 0139e403 0x139e403 + 54e0: 01392003 lw zero,19(s2) # 82297 <_start-0x7ff7dd69> 54e4: 1980 addi s0,sp,240 54e6: 1122 slli sp,sp,0x28 54e8: 0000 unimp 54ea: 2e01 jal 57fa <_start-0x7fffa806> - 54ec: 013f8003 lb zero,19(t6) + 54ec: 013ebc03 0x13ebc03 54f0: 1980 addi s0,sp,240 54f2: 10fc addi a5,sp,108 54f4: 0000 unimp 54f6: 2e01 jal 5806 <_start-0x7fffa7fa> - 54f8: 012f3403 0x12f3403 + 54f8: 012e7003 0x12e7003 54fc: 1280 addi s0,sp,352 54fe: 10e5 addi ra,ra,-7 5500: 0000 unimp @@ -33720,7 +34245,7 @@ Disassembly of section .debug_info: 5508: 6f00 flw fs0,24(a4) 550a: 00bc addi a5,sp,72 550c: 1a00 addi s0,sp,304 - 550e: 3794 fld fa3,40(a5) + 550e: 36d0 fld fa2,168(a3) 5510: 8001 c.srli64 s0 5512: 005c addi a5,sp,4 5514: 0000 unimp @@ -33756,7 +34281,7 @@ Disassembly of section .debug_info: 5554: 0000 unimp 5556: 0000bec3 fmadd.s ft9,ft1,ft0,ft0,rup 555a: 1a00 addi s0,sp,304 - 555c: 385c fld fa5,176(s0) + 555c: 3798 fld fa4,40(a5) 555e: 8001 c.srli64 s0 5560: 0114 addi a3,sp,128 5562: 0000 unimp @@ -33796,7 +34321,7 @@ Disassembly of section .debug_info: 55ca: 00c0 addi s0,sp,68 55cc: 0000 unimp 55ce: 1a00 addi s0,sp,304 - 55d0: 3974 fld fa3,240(a0) + 55d0: 38b0 fld fa2,112(s1) 55d2: 8001 c.srli64 s0 55d4: 0070 addi a2,sp,12 55d6: 0000 unimp @@ -33831,7 +34356,7 @@ Disassembly of section .debug_info: 5618: c11a sw t1,128(sp) 561a: 0000 unimp 561c: 1a00 addi s0,sp,304 - 561e: 3a5c fld fa5,176(a2) + 561e: 3998 fld fa4,48(a1) 5620: 8001 c.srli64 s0 5622: 005c addi a5,sp,4 5624: 0000 unimp @@ -33868,7 +34393,7 @@ Disassembly of section .debug_info: 5666: c212 sw tp,4(sp) 5668: 0000 unimp 566a: 1a00 addi s0,sp,304 - 566c: 3b18 fld fa4,48(a4) + 566c: 3a54 fld fa3,176(a2) 566e: 8001 c.srli64 s0 5670: 0128 addi a0,sp,136 5672: 0000 unimp @@ -33918,7 +34443,7 @@ Disassembly of section .debug_info: 56d8: a900 fsd fs0,16(a0) 56da: 000000c3 fmadd.s ft1,ft0,ft0,ft0,rne 56de: 1a00 addi s0,sp,304 - 56e0: 3c44 fld fs1,184(s0) + 56e0: 3b80 fld fs0,48(a5) 56e2: 8001 c.srli64 s0 56e4: 0070 addi a2,sp,12 56e6: 0000 unimp @@ -33954,7 +34479,7 @@ Disassembly of section .debug_info: 5728: c492 sw tp,72(sp) 572a: 0000 unimp 572c: 1a00 addi s0,sp,304 - 572e: 3d4c fld fa1,184(a0) + 572e: 3c88 fld fa0,56(s1) 5730: 8001 c.srli64 s0 5732: 0058 addi a4,sp,4 5734: 0000 unimp @@ -33990,7 +34515,7 @@ Disassembly of section .debug_info: 5774: 0000 unimp 5776: 0000c657 0xc657 577a: 1a00 addi s0,sp,304 - 577c: 3dac fld fa1,120(a1) + 577c: 3ce8 fld fa0,248(s1) 577e: 8001 c.srli64 s0 5780: 005c addi a5,sp,4 5782: 0000 unimp @@ -34025,7 +34550,7 @@ Disassembly of section .debug_info: 57c4: c724 sw s1,72(a4) 57c6: 0000 unimp 57c8: 1a00 addi s0,sp,304 - 57ca: 3e34 fld fa3,120(a2) + 57ca: 3d70 fld fa2,248(a0) 57cc: 8001 c.srli64 s0 57ce: 0028 addi a0,sp,8 57d0: 0000 unimp @@ -34135,7 +34660,7 @@ Disassembly of section .debug_info: 58c8: c7de sw s7,204(sp) 58ca: 0000 unimp 58cc: 1a00 addi s0,sp,304 - 58ce: 3ec8 fld fa0,184(a3) + 58ce: 3e04 fld fs1,56(a2) 58d0: 8001 c.srli64 s0 58d2: 0058 addi a4,sp,4 58d4: 0000 unimp @@ -34172,7 +34697,7 @@ Disassembly of section .debug_info: 5916: c996 sw t0,208(sp) 5918: 0000 unimp 591a: 1a00 addi s0,sp,304 - 591c: 3f28 fld fa0,120(a4) + 591c: 3e64 fld fs1,248(a2) 591e: 8001 c.srli64 s0 5920: 0054 addi a3,sp,4 5922: 0000 unimp @@ -34368,7 +34893,7 @@ Disassembly of section .debug_info: 5ae2: 00010603 lb a2,0(sp) 5ae6: 0000 unimp 5ae8: 1a00 addi s0,sp,304 - 5aea: 2f4c fld fa1,152(a4) + 5aea: 2e88 fld fa0,24(a3) 5aec: 8001 c.srli64 s0 5aee: 0038 addi a4,sp,8 5af0: 0000 unimp @@ -34461,7 +34986,7 @@ Disassembly of section .debug_info: 5bc0: 0000 unimp 5bc2: 05ed addi a1,a1,27 5bc4: 0000 unimp - 5bc6: 4224 lw s1,64(a2) + 5bc6: 4160 lw s0,68(a0) 5bc8: 8001 c.srli64 s0 5bca: 0114 addi a3,sp,128 5bcc: 0000 unimp @@ -34491,7 +35016,7 @@ Disassembly of section .debug_info: 5bfe: 0000 unimp 5c00: 0500 addi s0,sp,640 5c02: 00000047 fmsub.s ft0,ft0,ft0,ft0,rne - 5c06: b7080103 lb sp,-1168(a6) + 5c06: b7080103 lb sp,-1168(a6) # 106028 <_start-0x7fef9fd8> 5c0a: 0006 c.slli zero,0x1 5c0c: 0400 addi s0,sp,512 5c0e: 0174 addi a3,sp,140 @@ -34601,7 +35126,7 @@ Disassembly of section .debug_info: 5cfe: 0100 addi s0,sp,128 5d00: 00330123 sb gp,2(t1) 5d04: 0000 unimp - 5d06: 4224 lw s1,64(a2) + 5d06: 4160 lw s0,68(a0) 5d08: 8001 c.srli64 s0 5d0a: 0114 addi a3,sp,128 5d0c: 0000 unimp @@ -34628,7 +35153,7 @@ Disassembly of section .debug_info: 5d3a: 1400 addi s0,sp,544 5d3c: 5f41 li t5,-16 5d3e: 26010063 beqz sp,5f9e <_start-0x7fffa062> - 5d42: 0002a903 lw s2,0(t0) # b000 <_start-0x7fff5000> + 5d42: 0002a903 lw s2,0(t0) 5d46: 1500 addi s0,sp,672 5d48: 5f41 li t5,-16 5d4a: 26010073 0x26010073 @@ -34760,8 +35285,9 @@ Disassembly of section .debug_info: 5e7c: 0011 c.nop 4 5e7e: ed00 fsw fs0,24(a0) 5e80: 0005 c.nop 1 - 5e82: 3800 fld fs0,48(s0) - 5e84: 50800143 fmadd.s ft2,ft0,fs0,fa0,rne + 5e82: 7400 flw fs0,40(s0) + 5e84: 0142 slli sp,sp,0x10 + 5e86: 5080 lw s0,32(s1) 5e88: 0001 nop 5e8a: 0500 addi s0,sp,640 5e8c: 0089 addi ra,ra,2 @@ -34898,8 +35424,9 @@ Disassembly of section .debug_info: 5fbc: 2401 jal 61bc <_start-0x7fff9e44> 5fbe: a301 j 64be <_start-0x7fff9b42> 5fc0: 0000 unimp - 5fc2: 3800 fld fs0,48(s0) - 5fc4: 50800143 fmadd.s ft2,ft0,fs0,fa0,rne + 5fc2: 7400 flw fs0,40(s0) + 5fc4: 0142 slli sp,sp,0x10 + 5fc6: 5080 lw s0,32(s1) 5fc8: 0001 nop 5fca: 0100 addi s0,sp,128 5fcc: aa9c fsd fa5,16(a3) @@ -35166,9 +35693,8 @@ Disassembly of section .debug_info: 623a: 0011 c.nop 4 623c: ed00 fsw fs0,24(a0) 623e: 0005 c.nop 1 - 6240: 8800 0x8800 - 6242: 0144 addi s1,sp,132 - 6244: f480 fsw fs0,40(s1) + 6240: c400 sw s0,8(s0) + 6242: f4800143 0xf4800143 6246: 0001 nop 6248: a200 fsd fs0,0(a2) 624a: 008c addi a1,sp,64 @@ -35351,7 +35877,7 @@ Disassembly of section .debug_info: 63e4: 0125 addi sp,sp,9 63e6: 010c addi a1,sp,128 63e8: 0000 unimp - 63ea: 4488 lw a0,8(s1) + 63ea: 43c4 lw s1,4(a5) 63ec: 8001 c.srli64 s0 63ee: 01f4 addi a3,sp,204 63f0: 0000 unimp @@ -35445,7 +35971,7 @@ Disassembly of section .debug_info: 64c6: 2d01 jal 6ad6 <_start-0x7fff952a> 64c8: 0000e603 0xe603 64cc: 0000 unimp - 64ce: e019 bnez s0,64d4 <_start-0x7fff9b2c> + 64ce: 1c19 addi s8,s8,-26 64d0: 0144 addi s1,sp,132 64d2: 2480 fld fs0,8(s1) 64d4: 0000 unimp @@ -35497,8 +36023,8 @@ Disassembly of section .debug_info: 654a: 2f01 jal 6c5a <_start-0x7fff93a6> 654c: 0003e203 0x3e203 6550: 0000 unimp - 6552: 6019 c.lui zero,0x6 - 6554: 0145 addi sp,sp,17 + 6552: 9c19 0x9c19 + 6554: 0144 addi s1,sp,132 6556: e080 fsw fs0,0(s1) 6558: 0000 unimp 655a: 8e00 0x8e00 @@ -35591,8 +36117,8 @@ Disassembly of section .debug_info: 6630: 0012 c.slli zero,0x4 6632: ed00 fsw fs0,24(a0) 6634: 0005 c.nop 1 - 6636: 7c00 flw fs0,56(s0) - 6638: 0146 slli sp,sp,0x11 + 6636: b800 fsd fs0,48(s0) + 6638: 0145 addi sp,sp,17 663a: 4c80 lw s0,24(s1) 663c: 8c000003 lb zero,-1856(zero) # fffff8c0 <__BSS_END__+0x7ffe8c84> 6640: 0092 slli ra,ra,0x4 @@ -35771,7 +36297,7 @@ Disassembly of section .debug_info: 67da: 0124 addi s1,sp,136 67dc: 0089 addi ra,ra,2 67de: 0000 unimp - 67e0: 467c lw a5,76(a2) + 67e0: 45b8 lw a4,72(a1) 67e2: 8001 c.srli64 s0 67e4: 034c addi a1,sp,388 67e6: 0000 unimp @@ -35927,8 +36453,9 @@ Disassembly of section .debug_info: 6968: 0000 unimp 696a: 0000dedb 0xdedb 696e: 0000 unimp - 6970: 241a fld fs0,384(sp) - 6972: 3c800147 0x3c800147 + 6970: 601a flw ft0,132(sp) + 6972: 0146 slli sp,sp,0x11 + 6974: 3c80 fld fs0,56(s1) 6976: 0000 unimp 6978: b600 fsd fs0,40(a2) 697a: 1b000003 lb zero,432(zero) # 1b0 <_start-0x7ffffe50> @@ -36069,7 +36596,7 @@ Disassembly of section .debug_info: 6ae0: 00018903 lb s2,0(gp) # 80016808 <__global_pointer$> 6ae4: 0000 unimp 6ae6: 1a00 addi s0,sp,304 - 6ae8: 477c lw a5,76(a4) + 6ae8: 46b8 lw a4,72(a3) 6aea: 8001 c.srli64 s0 6aec: 0014 0x14 6aee: 0000 unimp @@ -36093,8 +36620,8 @@ Disassembly of section .debug_info: 6b20: 0189 addi gp,gp,2 6b22: 0000 unimp 6b24: 0000 unimp - 6b26: 841e mv s0,t2 - 6b28: 0149 addi sp,sp,18 + 6b26: c01e sw t2,0(sp) + 6b28: 0148 addi a0,sp,132 6b2a: 2080 fld fs0,0(s1) 6b2c: 0000 unimp 6b2e: 1b00 addi s0,sp,432 @@ -36234,7 +36761,7 @@ Disassembly of section .debug_info: 6c68: 3005 jal 6488 <_start-0x7fff9b78> 6c6a: 0005 c.nop 1 6c6c: 0300 addi s0,sp,384 - 6c6e: 010b1b23 sh a6,22(s6) + 6c6e: 010b1b23 sh a6,22(s6) # 5f6a8 <_start-0x7ffa0958> 6c72: 0000 unimp 6c74: 720d lui tp,0xfffe3 6c76: 18000003 lb zero,384(zero) # 180 <_start-0x7ffffe80> @@ -37332,7 +37859,7 @@ Disassembly of section .debug_info: 76b0: b20d j 6fd2 <_start-0x7fff902e> 76b2: 0f02 c.slli64 t5 76b4: 0305 addi t1,t1,1 - 76b6: 584c lw a1,52(s0) + 76b6: 5774 lw a3,108(a4) 76b8: 8001 c.srli64 s0 76ba: d300 sw s0,32(a4) 76bc: 0400000b 0x400000b @@ -37346,7 +37873,7 @@ Disassembly of section .debug_info: 76ce: 0000 unimp 76d0: 05ed addi a1,a1,27 76d2: 0000 unimp - 76d4: 49c8 lw a0,20(a1) + 76d4: 4904 lw s1,16(a0) 76d6: 8001 c.srli64 s0 76d8: 004c addi a1,sp,4 76da: 0000 unimp @@ -37431,7 +37958,7 @@ Disassembly of section .debug_info: 7798: 0b00 addi s0,sp,400 779a: 0339 addi t1,t1,14 779c: 0000 unimp - 779e: 2507a403 lw s0,592(a5) # fffe3250 <__BSS_END__+0x7ffcc614> + 779e: 2507a403 lw s0,592(a5) 77a2: 0000 unimp 77a4: 0000 unimp 77a6: 0005c50b 0x5c50b @@ -38642,7 +39169,7 @@ Disassembly of section .debug_info: 823c: 0102 c.slli64 sp 823e: 0025 c.nop 9 8240: 0000 unimp - 8242: 49c8 lw a0,20(a1) + 8242: 4904 lw s1,16(a0) 8244: 8001 c.srli64 s0 8246: 004c addi a1,sp,4 8248: 0000 unimp @@ -41408,7 +41935,7 @@ Disassembly of section .debug_line: 206: 0500 addi s0,sp,640 208: 0001 nop 20a: 0205 addi tp,tp,1 - 20c: 04c4 addi s1,sp,580 + 20c: 0400 addi s0,sp,512 20e: 8001 c.srli64 s0 210: 010aa603 lw a2,16(s5) # 67d8 <_start-0x7fff9828> 214: 0305 addi t1,t1,1 @@ -42361,7 +42888,7 @@ Disassembly of section .debug_line: b0a: 0000 unimp b0c: 0105 addi sp,sp,1 b0e: 0500 addi s0,sp,640 - b10: f802 fsw ft0,48(sp) + b10: 3402 fld fs0,32(sp) b12: 0108 addi a0,sp,128 b14: 0380 addi s0,sp,448 b16: 0a9a slli s5,s5,0x6 @@ -43295,7 +43822,7 @@ Disassembly of section .debug_line: 1344: 0500 addi s0,sp,640 1346: 0001 nop 1348: 0205 addi tp,tp,1 - 134a: 0d08 addi a0,sp,656 + 134a: 0c44 addi s1,sp,532 134c: 8001 c.srli64 s0 134e: 05012303 lw t1,80(sp) 1352: 09010303 lb t1,144(sp) @@ -45132,7 +45659,7 @@ Disassembly of section .debug_line: 22de: 0000 unimp 22e0: 0105 addi sp,sp,1 22e2: 0500 addi s0,sp,640 - 22e4: e802 fsw ft0,16(sp) + 22e4: 2402 fld fs0,0(sp) 22e6: 03800113 li sp,56 22ea: 03050123 sb a6,34(a0) # ffffb022 <__BSS_END__+0x7ffe43e6> 22ee: 00090103 lb sp,0(s2) @@ -46556,8 +47083,8 @@ Disassembly of section .debug_line: 30c2: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> 30c6: 0105 addi sp,sp,1 30c8: 0500 addi s0,sp,640 - 30ca: ac02 fsd ft0,24(sp) - 30cc: 0119 addi sp,sp,6 + 30ca: e802 fsw ft0,16(sp) + 30cc: 0118 addi a4,sp,128 30ce: 0380 addi s0,sp,448 30d0: 03050123 sb a6,34(a0) 30d4: 00090103 lb sp,0(s2) @@ -46853,8 +47380,8 @@ Disassembly of section .debug_line: 33a4: 00000003 lb zero,0(zero) # 0 <_start-0x80000000> 33a8: 0105 addi sp,sp,1 33aa: 0500 addi s0,sp,640 - 33ac: 7802 flw fa6,32(sp) - 33ae: 011a slli sp,sp,0x6 + 33ac: b402 fsd ft0,40(sp) + 33ae: 0119 addi sp,sp,6 33b0: 0380 addi s0,sp,448 33b2: 03050123 sb a6,34(a0) 33b6: 00090103 lb sp,0(s2) @@ -47235,7 +47762,7 @@ Disassembly of section .debug_line: 3764: 0500 addi s0,sp,640 3766: 0001 nop 3768: 0205 addi tp,tp,1 - 376a: 1bbc addi a5,sp,504 + 376a: 1af8 addi a4,sp,380 376c: 8001 c.srli64 s0 376e: 05012303 lw t1,80(sp) 3772: 09010303 lb t1,144(sp) @@ -47651,8 +48178,8 @@ Disassembly of section .debug_line: 3b0e: 0000 unimp 3b10: 0105 addi sp,sp,1 3b12: 0500 addi s0,sp,640 - 3b14: 0002 c.slli64 zero - 3b16: 011d addi sp,sp,7 + 3b14: 3c02 fld fs8,32(sp) + 3b16: 011c addi a5,sp,128 3b18: 0380 addi s0,sp,448 3b1a: 03050123 sb a6,34(a0) # ffffb022 <__BSS_END__+0x7ffe43e6> 3b1e: 00090103 lb sp,0(s2) @@ -51264,7 +51791,7 @@ Disassembly of section .debug_line: 5e36: 0500 addi s0,sp,640 5e38: 0001 nop 5e3a: 0205 addi tp,tp,1 - 5e3c: 2d04 fld fs1,24(a0) + 5e3c: 2c40 fld fs0,152(s0) 5e3e: 8001 c.srli64 s0 5e40: 05012303 lw t1,80(sp) 5e44: 09010303 lb t1,144(sp) @@ -55477,7 +56004,7 @@ Disassembly of section .debug_line: 8660: 0500 addi s0,sp,640 8662: 0001 nop 8664: 0205 addi tp,tp,1 - 8666: 4224 lw s1,64(a2) + 8666: 4160 lw s0,68(a0) 8668: 8001 c.srli64 s0 866a: 05012303 lw t1,80(sp) 866e: 09010303 lb t1,144(sp) @@ -55864,7 +56391,7 @@ Disassembly of section .debug_line: 89a2: 0500 addi s0,sp,640 89a4: 0001 nop 89a6: 0205 addi tp,tp,1 - 89a8: 4338 lw a4,64(a4) + 89a8: 4274 lw a3,68(a2) 89aa: 8001 c.srli64 s0 89ac: 05012403 lw s0,80(sp) 89b0: 09010303 lb t1,144(sp) @@ -56282,9 +56809,8 @@ Disassembly of section .debug_line: 8d4c: 0000 unimp 8d4e: 0105 addi sp,sp,1 8d50: 0500 addi s0,sp,640 - 8d52: 8802 jr a6 - 8d54: 0144 addi s1,sp,132 - 8d56: 0380 addi s0,sp,448 + 8d52: c402 sw zero,8(sp) + 8d54: 03800143 fmadd.d ft2,ft0,fs8,ft0,rne 8d58: 0125 addi sp,sp,9 8d5a: 0305 addi t1,t1,1 8d5c: 00090103 lb sp,0(s2) @@ -56885,7 +57411,7 @@ Disassembly of section .debug_line: 9336: 0500 addi s0,sp,640 9338: 0001 nop 933a: 0205 addi tp,tp,1 - 933c: 467c lw a5,76(a2) + 933c: 45b8 lw a4,72(a1) 933e: 8001 c.srli64 s0 9340: 05012403 lw s0,80(sp) 9344: 09010303 lb t1,144(sp) @@ -58045,7 +58571,7 @@ Disassembly of section .debug_line: 9da4: 0000 unimp 9da6: 0105 addi sp,sp,1 9da8: 0500 addi s0,sp,640 - 9daa: c802 sw zero,16(sp) + 9daa: 0402 c.slli64 s0 9dac: 0149 addi sp,sp,18 9dae: 0380 addi s0,sp,448 9db0: 05c2 slli a1,a1,0x10 @@ -58123,7 +58649,7 @@ Disassembly of section .debug_frame: 12: 0000 unimp 14: 0000 unimp 16: 0000 unimp - 18: 0d08 addi a0,sp,656 + 18: 0c44 addi s1,sp,532 1a: 8001 c.srli64 s0 1c: 06e0 addi s0,sp,844 1e: 0000 unimp @@ -58165,7 +58691,7 @@ Disassembly of section .debug_frame: 6a: 0000 unimp 6c: 0058 addi a4,sp,4 6e: 0000 unimp - 70: 13e8 addi a0,sp,492 + 70: 1324 addi s1,sp,424 72: 8001 c.srli64 s0 74: 05c4 addi s1,sp,708 76: 0000 unimp @@ -58205,7 +58731,7 @@ Disassembly of section .debug_frame: be: 0000 unimp c0: 00ac addi a1,sp,72 c2: 0000 unimp - c4: 19ac addi a1,sp,248 + c4: 18e8 addi a0,sp,124 c6: 8001 c.srli64 s0 c8: 00cc addi a1,sp,68 ca: 0000 unimp @@ -58226,7 +58752,7 @@ Disassembly of section .debug_frame: ea: 0000 unimp ec: 00d8 addi a4,sp,68 ee: 0000 unimp - f0: 1a78 addi a4,sp,316 + f0: 19b4 addi a3,sp,248 f2: 8001 c.srli64 s0 f4: 0144 addi s1,sp,132 f6: 0000 unimp @@ -58247,7 +58773,7 @@ Disassembly of section .debug_frame: 116: 0000 unimp 118: 0104 addi s1,sp,128 11a: 0000 unimp - 11c: 1bbc addi a5,sp,504 + 11c: 1af8 addi a4,sp,380 11e: 8001 c.srli64 s0 120: 0144 addi s1,sp,132 122: 0000 unimp @@ -58268,7 +58794,7 @@ Disassembly of section .debug_frame: 142: 0000 unimp 144: 0130 addi a2,sp,136 146: 0000 unimp - 148: 1d00 addi s0,sp,688 + 148: 1c3c addi a5,sp,568 14a: 8001 c.srli64 s0 14c: 1004 addi s1,sp,32 14e: 0000 unimp @@ -58315,7 +58841,7 @@ Disassembly of section .debug_frame: 1aa: 0000 unimp 1ac: 0198 addi a4,sp,192 1ae: 0000 unimp - 1b0: 2d04 fld fs1,24(a0) + 1b0: 2c40 fld fs0,152(s0) 1b2: 8001 c.srli64 s0 1b4: 1520 addi s0,sp,680 1b6: 0000 unimp @@ -58352,7 +58878,7 @@ Disassembly of section .debug_frame: 1fa: 0000 unimp 1fc: 01e8 addi a0,sp,204 1fe: 0000 unimp - 200: 4224 lw s1,64(a2) + 200: 4160 lw s0,68(a0) 202: 8001 c.srli64 s0 204: 0114 addi a3,sp,128 206: 0000 unimp @@ -58374,7 +58900,7 @@ Disassembly of section .debug_frame: 226: 0000 unimp 228: 0214 addi a3,sp,256 22a: 0000 unimp - 22c: 4338 lw a4,64(a4) + 22c: 4274 lw a3,68(a2) 22e: 8001 c.srli64 s0 230: 0150 addi a2,sp,132 232: 0000 unimp @@ -58403,7 +58929,7 @@ Disassembly of section .debug_frame: 262: 0000 unimp 264: 0250 addi a2,sp,260 266: 0000 unimp - 268: 4488 lw a0,8(s1) + 268: 43c4 lw s1,4(a5) 26a: 8001 c.srli64 s0 26c: 01f4 addi a3,sp,204 26e: 0000 unimp @@ -58432,7 +58958,7 @@ Disassembly of section .debug_frame: 29e: 0000 unimp 2a0: 028c addi a1,sp,320 2a2: 0000 unimp - 2a4: 467c lw a5,76(a2) + 2a4: 45b8 lw a4,72(a1) 2a6: 8001 c.srli64 s0 2a8: 034c addi a1,sp,388 2aa: 0000 unimp @@ -58453,7 +58979,7 @@ Disassembly of section .debug_frame: 2ca: 0000 unimp 2cc: 02b8 addi a4,sp,328 2ce: 0000 unimp - 2d0: 49c8 lw a0,20(a1) + 2d0: 4904 lw s1,16(a0) 2d2: 8001 c.srli64 s0 2d4: 004c addi a1,sp,4 ... diff --git a/runtime/mains/simple/vx_simple_main.elf b/runtime/mains/simple/vx_simple_main.elf index 1406072ac36a079fc97818cc32ef91066032f42d..1b90f779b58402007cf9aae1d1c23252b9f195cf 100644 GIT binary patch delta 13010 zcma)C4O~^_{ePZwF5C;gaCu48P;Nqs$_xz^6%7hS9T_DpbQC(Eut=ERsVnLp0|m>H z?NEm%DU~UinR=;1jBUEGs8~{&Vx!Qcq|NHOSkgxD|NhPk_j`>d(;-z3!O`=Z2@?Y2@8m50&cjQaLzV__ehMHvdU`Cp}Ue0Af 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z!2?H>;12_?IEdF}{1pt@8v~s42>!W->K_r}K*(K-QYk_@6?i6A7%BMEfrFfm;auQM zr$Vy`*vIL1%K_fwxJ~zlBqhpyp~I)S>iN3W1Hlb8wy7SFjnl zXt|@7R{*D>G8PMY9e6!fXiw6A1LKoqcVRmQoa^N955UEA|J(QM3JC2;l57#;Tfl(< z*rNy|LUIonEOOL|9>DnQ+3i3d;7q)jlnaLj0yiwgKZ)2D=+5o}F2`3XyMxidxl{0r zmqfQ2j!`G}I0+9Rxk5oa1d8!Q6D06d;1H)Rcm}wp!0|vbAGoYQd;hdN$$ehN@-fpU zYmKMndj>AZ$jM$Zmo3Pco0YmOd+yR~8m6aaEKX-y>=}8Ydq(<_Y0r<*lr!>p_Zef8 zU&y*w|JNB=HuXuJpOO9iXm;n{OlW7%$!B~QF3w)MaPhK*^OmJ%XDrKJrtNK%qqW}} z@nJ9Gyd0vZo|jKZ-o#3Mb=lmkR~Ktzn&bsNmMvVAm6;*_`a*xdNgm6!i_P*%51VB6 zqIvprm*fzxsh8#Py==7fg|B2Rou9FIUWR`7vit_urnbld_{8~4iyZ8U&?rGTl Date: Thu, 26 Mar 2020 01:41:01 -0400 Subject: [PATCH 49/66] code refactoring --- rtl/Makefile | 2 +- rtl/VX_define.v | 4 +- rtl/Vortex.v | 5 +-- rtl/Vortex_SOC.v | 97 +++++++++++++++++++----------------------------- 4 files changed, 44 insertions(+), 64 deletions(-) diff --git a/rtl/Makefile b/rtl/Makefile index a99fd562..0154e0bd 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -85,4 +85,4 @@ runRel: wRel (cd obj_dir && ./VVortex) clean: - rm obj_dir/* + rm -rf obj_dir diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 3d1b0a5f..bcd3b87d 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -127,8 +127,10 @@ `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) -`define SINGLE_CORE_BENCH 1 +//`define SINGLE_CORE_BENCH + `define GLOBAL_BLOCK_SIZE_BYTES 16 + // ========================================= Dcache Configurable Knobs ========================================= // General Cache Knobs diff --git a/rtl/Vortex.v b/rtl/Vortex.v index d5454d7d..9759216e 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -6,7 +6,6 @@ module Vortex parameter CORE_ID = 0 ) ( - `ifdef SINGLE_CORE_BENCH input wire clk, input wire reset, @@ -53,10 +52,10 @@ module Vortex input wire [31:0] I_snp_req_addr, output wire I_snp_req_delay, - - output wire out_ebreak + `else + input wire clk, input wire reset, // IO diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index 1d37b36d..1d926c53 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -3,40 +3,40 @@ module Vortex_SOC ( - input wire clk, - input wire reset, - // IO - output wire io_valid[`NUMBER_CORES-1:0], - output wire[31:0] io_data [`NUMBER_CORES-1:0], + // System Clock + input wire clk, + input wire reset, - output wire[31:0] number_cores, + // IO + output wire io_valid[`NUMBER_CORES-1:0], + output wire[31:0] io_data [`NUMBER_CORES-1:0], + + output wire[31:0] number_cores, // DRAM Dcache Req - output wire out_dram_req, - output wire out_dram_req_write, - output wire out_dram_req_read, - output wire [31:0] out_dram_req_addr, - output wire [31:0] out_dram_req_size, - output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG], - output wire [31:0] out_dram_expected_lat, + output wire out_dram_req, + output wire out_dram_req_write, + output wire out_dram_req_read, + output wire [31:0] out_dram_req_addr, + output wire [31:0] out_dram_req_size, + output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] out_dram_expected_lat, // DRAM Dcache Res - output wire out_dram_fill_accept, - input wire out_dram_fill_rsp, - input wire [31:0] out_dram_fill_rsp_addr, - input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + output wire out_dram_fill_accept, + input wire out_dram_fill_rsp, + input wire [31:0] out_dram_fill_rsp_addr, + input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], - input wire l3c_snp_req, - input wire l3c_snp_req_addr, - output wire l3c_snp_req_delay, + input wire llc_snp_req, + input wire llc_snp_req_addr, + output wire llc_snp_req_delay, - - output wire out_ebreak - ); + output wire out_ebreak +); `ifdef L3C - // DRAM Dcache Req wire [`NUMBER_CLUSTERS-1:0] dram_req; wire [`NUMBER_CLUSTERS-1:0] dram_req_write; @@ -54,11 +54,7 @@ module Vortex_SOC ( assign number_cores = `NUMBER_CORES; - // IO - // wire per_core_io_valid[`NUMBER_CORES-1:0]; - // wire[31:0] per_core_io_data[`NUMBER_CORES-1:0]; - - // Out ebreak + // Out ebreak wire[`NUMBER_CORES-1:0] per_core_out_ebreak; assign out_ebreak = (&per_core_out_ebreak); @@ -71,18 +67,17 @@ module Vortex_SOC ( wire l3c_core_accept; - - wire l3c_snp_fwd; - wire[31:0] l3c_snp_fwd_addr; - wire[`L3NUMBER_REQUESTS-1:0] l3c_snp_fwd_delay_temp; - wire l3c_snp_fwd_delay; + wire l3c_snp_fwd; + wire[31:0] l3c_snp_fwd_addr; + wire[`L3NUMBER_REQUESTS-1:0] l3c_snp_fwd_delay_temp; + wire l3c_snp_fwd_delay; assign l3c_snp_fwd_delay = (|l3c_snp_fwd_delay_temp); - wire[`L3NUMBER_REQUESTS-1:0] l3c_wb; - wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr; - wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data; + wire[`L3NUMBER_REQUESTS-1:0] l3c_wb; + wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr; + wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data; wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_req_data; wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_fill_rsp_data; @@ -95,9 +90,6 @@ module Vortex_SOC ( end endgenerate - - - // genvar l3c_curr_core; generate @@ -203,9 +195,9 @@ module Vortex_SOC ( .dram_snp_full (dram_snp_full), // Snoop Request - .snp_req (l3c_snp_req), - .snp_req_addr (l3c_snp_req_addr), - .snp_req_delay (l3c_snp_req_delay), + .snp_req (llc_snp_req), + .snp_req_addr (llc_snp_req_addr), + .snp_req_delay (llc_snp_req_delay), .snp_fwd (l3c_snp_fwd), .snp_fwd_addr (l3c_snp_fwd_addr), @@ -227,8 +219,6 @@ module Vortex_SOC ( for (curr_cluster = 0; curr_cluster < `NUMBER_CLUSTERS; curr_cluster=curr_cluster+1) begin ////////////////////// BEGIN CLUSTER ///////////////// - - // DRAM Dcache Req wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req; wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write; @@ -260,8 +250,6 @@ module Vortex_SOC ( wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr; wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; - - // Snoop Requests wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dcache_snp_req; wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_dcache_snp_req_addr; @@ -271,7 +259,6 @@ module Vortex_SOC ( wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_icache_snp_req_addr; wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_icache_snp_req_delay; - // generate for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin @@ -346,8 +333,6 @@ module Vortex_SOC ( // endgenerate - - // // generate for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin // Core Request @@ -492,7 +477,6 @@ module Vortex_SOC ( `else - assign number_cores = `NUMBER_CORES; // IO @@ -545,6 +529,7 @@ module Vortex_SOC ( assign io_valid[curr_core] = per_core_io_valid[curr_core]; assign io_data [curr_core] = per_core_io_data [curr_core]; + Vortex #(.CORE_ID(curr_core)) vortex_core( .clk (clk), .reset (reset), @@ -735,16 +720,10 @@ module Vortex_SOC ( .dram_snp_full (dram_snp_full), // Snoop Request - .snp_req (l3c_snp_req), - .snp_req_addr (l3c_snp_req_addr) + .snp_req (llc_snp_req), + .snp_req_addr (llc_snp_req_addr) ); - - - //////////////////// L2 Cache //////////////////// - - - `endif From a7eb9a0c38333bce4969821f12f5beca34c67359 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 26 Mar 2020 03:20:46 -0400 Subject: [PATCH 50/66] code refactoring --- rtl/VX_define.v | 2 +- rtl/VX_define_synth.v | 1 - rtl/Vortex.v | 170 +++++++++++++++++++----------------------- rtl/Vortex_SOC.v | 15 ++-- 4 files changed, 84 insertions(+), 104 deletions(-) diff --git a/rtl/VX_define.v b/rtl/VX_define.v index bcd3b87d..4f3eb68b 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -127,7 +127,7 @@ `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) -//`define SINGLE_CORE_BENCH +`define SINGLE_CORE_BENCH `define GLOBAL_BLOCK_SIZE_BYTES 16 diff --git a/rtl/VX_define_synth.v b/rtl/VX_define_synth.v index a55023d9..79d1a158 100644 --- a/rtl/VX_define_synth.v +++ b/rtl/VX_define_synth.v @@ -12,7 +12,6 @@ // L2 Cache size `define LLCACHE_SIZE_BYTES 8192 - // `define QUEUE_FORCE_MLAB 1 // Use l3 cache (required for cluster behavior) diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 9759216e..8660861f 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -2,110 +2,92 @@ `include "VX_cache_config.v" module Vortex - #( + #( parameter CORE_ID = 0 - ) - ( - `ifdef SINGLE_CORE_BENCH - input wire clk, - input wire reset, - // IO - output wire io_valid, - output wire[31:0] io_data, + ) ( +`ifdef SINGLE_CORE_BENCH - // DRAM Dcache Req - output wire dram_req, - output wire dram_req_write, - output wire dram_req_read, - output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, - output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], - output wire [31:0] dram_expected_lat, + // Clock + input wire clk, + input wire reset, - // DRAM Dcache Res - output wire dram_fill_accept, - input wire dram_fill_rsp, - input wire [31:0] dram_fill_rsp_addr, - input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + // IO + output wire io_valid, + output wire[31:0] io_data, + + // DRAM Dcache Req + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG], + output wire [31:0] dram_expected_lat, + + // DRAM Dcache Res + output wire dram_fill_accept, + input wire dram_fill_rsp, + input wire [31:0] dram_fill_rsp_addr, + input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + + // LLC Snooping + input wire snp_req, + input wire [31:0] snp_req_addr, + output wire snp_req_delay, + + output wire out_ebreak + +`else + + input wire clk, + input wire reset, + // IO + output wire io_valid, + output wire[31:0] io_data, + + // DRAM Dcache Req + output wire dram_req, + output wire dram_req_write, + output wire dram_req_read, + output wire [31:0] dram_req_addr, + output wire [31:0] dram_req_size, + output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data, + output wire [31:0] dram_expected_lat, + + // DRAM Dcache Res + output wire dram_fill_accept, + input wire dram_fill_rsp, + input wire [31:0] dram_fill_rsp_addr, + input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, - // DRAM Icache Req - output wire I_dram_req, - output wire I_dram_req_write, - output wire I_dram_req_read, - output wire [31:0] I_dram_req_addr, - output wire [31:0] I_dram_req_size, - output wire [31:0] I_dram_req_data[`IBANK_LINE_SIZE_RNG], - output wire [31:0] I_dram_expected_lat, + // DRAM Icache Req + output wire I_dram_req, + output wire I_dram_req_write, + output wire I_dram_req_read, + output wire [31:0] I_dram_req_addr, + output wire [31:0] I_dram_req_size, + output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data, + output wire [31:0] I_dram_expected_lat, - // DRAM Icache Res - output wire I_dram_fill_accept, - input wire I_dram_fill_rsp, - input wire [31:0] I_dram_fill_rsp_addr, - input wire [31:0] I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG], - - input wire snp_req, - input wire [31:0] snp_req_addr, - output wire snp_req_delay, - - input wire I_snp_req, - input wire [31:0] I_snp_req_addr, - output wire I_snp_req_delay, - - output wire out_ebreak - - `else - - input wire clk, - input wire reset, - // IO - output wire io_valid, - output wire[31:0] io_data, - - // DRAM Dcache Req - output wire dram_req, - output wire dram_req_write, - output wire dram_req_read, - output wire [31:0] dram_req_addr, - output wire [31:0] dram_req_size, - output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data, - output wire [31:0] dram_expected_lat, - - // DRAM Dcache Res - output wire dram_fill_accept, - input wire dram_fill_rsp, - input wire [31:0] dram_fill_rsp_addr, - input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data, + // DRAM Icache Res + output wire I_dram_fill_accept, + input wire I_dram_fill_rsp, + input wire [31:0] I_dram_fill_rsp_addr, + input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data, - // DRAM Icache Req - output wire I_dram_req, - output wire I_dram_req_write, - output wire I_dram_req_read, - output wire [31:0] I_dram_req_addr, - output wire [31:0] I_dram_req_size, - output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data, - output wire [31:0] I_dram_expected_lat, + input wire snp_req, + input wire [31:0] snp_req_addr, + output wire snp_req_delay, - // DRAM Icache Res - output wire I_dram_fill_accept, - input wire I_dram_fill_rsp, - input wire [31:0] I_dram_fill_rsp_addr, - input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data, + input wire I_snp_req, + input wire [31:0] I_snp_req_addr, + output wire I_snp_req_delay, - - input wire snp_req, - input wire [31:0] snp_req_addr, - output wire snp_req_delay, - - input wire I_snp_req, - input wire [31:0] I_snp_req_addr, - output wire I_snp_req_delay, - - - output wire out_ebreak - `endif - ); + output wire out_ebreak +`endif +); wire scheduler_empty; wire out_ebreak_unqual; diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index 1d926c53..f2630c90 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -3,9 +3,9 @@ module Vortex_SOC ( - // System Clock - input wire clk, - input wire reset, + // Clock + input wire clk, + input wire reset, // IO output wire io_valid[`NUMBER_CORES-1:0], @@ -13,7 +13,7 @@ module Vortex_SOC ( output wire[31:0] number_cores, - // DRAM Dcache Req + // DRAM Req output wire out_dram_req, output wire out_dram_req_write, output wire out_dram_req_read, @@ -22,12 +22,13 @@ module Vortex_SOC ( output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG], output wire [31:0] out_dram_expected_lat, - // DRAM Dcache Res + // DRAM Res output wire out_dram_fill_accept, input wire out_dram_fill_rsp, input wire [31:0] out_dram_fill_rsp_addr, input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], + // LLC Snooping input wire llc_snp_req, input wire llc_snp_req_addr, output wire llc_snp_req_delay, @@ -529,7 +530,7 @@ module Vortex_SOC ( assign io_valid[curr_core] = per_core_io_valid[curr_core]; assign io_data [curr_core] = per_core_io_data [curr_core]; - + Vortex #(.CORE_ID(curr_core)) vortex_core( .clk (clk), .reset (reset), @@ -605,8 +606,6 @@ module Vortex_SOC ( // end // endgenerate - - // genvar l2c_curr_core; generate From 9621acff5b6e235d36450755ea1cd926321adbe6 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 26 Mar 2020 03:54:23 -0400 Subject: [PATCH 51/66] fixed Modelsim build errors --- rtl/VX_cache/VX_bank.v | 50 +++++++++++++------------------ rtl/VX_cache/VX_snp_fwd_arb.v | 1 + rtl/VX_cache/VX_tag_data_access.v | 13 ++++---- rtl/VX_define.v | 2 +- 4 files changed, 27 insertions(+), 39 deletions(-) diff --git a/rtl/VX_cache/VX_bank.v b/rtl/VX_cache/VX_bank.v index 355e15c8..5627df5d 100644 --- a/rtl/VX_cache/VX_bank.v +++ b/rtl/VX_cache/VX_bank.v @@ -242,6 +242,9 @@ module VX_bank wire[31:0] miss_add_pc; + wire[31:0] addr_st2; + wire is_fill_st2; + VX_cache_miss_resrv #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), .BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES), @@ -298,6 +301,11 @@ module VX_bank wire stall_bank_pipe; reg is_fill_in_pipe; + wire valid_st1 [STAGE_1_CYCLES-1:0]; + wire is_fill_st1 [STAGE_1_CYCLES-1:0]; + wire going_to_write_st1[STAGE_1_CYCLES-1:0]; + wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0]; + reg[16:0] p_stage; always @(*) begin is_fill_in_pipe = 0; @@ -316,7 +324,6 @@ module VX_bank assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe; assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0; - integer st1_cycle; always @(*) begin @@ -334,9 +341,6 @@ module VX_bank end end - - - wire qual_is_fill_st0; wire qual_valid_st0; wire [31:0] qual_addr_st0; @@ -347,12 +351,8 @@ module VX_bank wire qual_is_snp; wire [31:0] qual_pc_st0; - wire valid_st1 [STAGE_1_CYCLES-1:0]; - wire going_to_write_st1[STAGE_1_CYCLES-1:0]; - wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0]; wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0]; - wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; - wire is_fill_st1 [STAGE_1_CYCLES-1:0]; + wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0]; wire is_snp_st1 [STAGE_1_CYCLES-1:0]; wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0]; @@ -493,16 +493,14 @@ module VX_bank wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1]; - wire valid_st2; - wire[31:0] addr_st2; + wire valid_st2; wire[`WORD_SIZE_RNG] writeword_st2; wire[`WORD_SIZE_RNG] readword_st2; wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st2; wire miss_st2; wire dirty_st2; wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2; - wire[`TAG_SELECT_SIZE_RNG] readtag_st2; - wire is_fill_st2; + wire[`TAG_SELECT_SIZE_RNG] readtag_st2; wire fill_saw_dirty_st2; wire is_snp_st2; wire [31:0] pc_st2; @@ -517,6 +515,10 @@ module VX_bank .out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 }) ); + wire cwbq_full; + wire dwbq_full; + wire ffsq_full; + wire invalidate_fill; // Enqueue to miss reserv if it's a valid miss assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full)); @@ -534,8 +536,7 @@ module VX_bank wire [1:0] cwbq_wb = miss_add_wb; wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num; wire [31:0] cwbq_pc = pc_st2; - - wire cwbq_full; + wire cwbq_empty; assign bank_wb_valid = !cwbq_empty; VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue( @@ -556,11 +557,8 @@ module VX_bank wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK; wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2; wire dwbq_empty; - wire dwbq_full; - - - wire invalidate_fill; - wire possible_fill = valid_st2 && miss_st2; + + wire possible_fill = valid_st2 && miss_st2; wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK; VX_fill_invalidator #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), @@ -611,8 +609,7 @@ module VX_bank .full (dwbq_full) ); - wire snp_fwd_push; - wire ffsq_full; + wire snp_fwd_push; wire ffsq_empty; assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full)); @@ -628,13 +625,6 @@ module VX_bank .full (ffsq_full) ); - - assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full); -endmodule : VX_bank - - - - - +endmodule : VX_bank \ No newline at end of file diff --git a/rtl/VX_cache/VX_snp_fwd_arb.v b/rtl/VX_cache/VX_snp_fwd_arb.v index 354e1fdd..320381be 100644 --- a/rtl/VX_cache/VX_snp_fwd_arb.v +++ b/rtl/VX_cache/VX_snp_fwd_arb.v @@ -1,3 +1,4 @@ +`include "VX_cache_config.v" module VX_snp_fwd_arb #( diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 2d3672b8..b69d6a89 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -93,6 +93,7 @@ module VX_tag_data_access wire[`DBANK_LINE_SIZE_RNG][3:0] use_write_enable; wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data; + wire sw, sb, sh; wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e))); @@ -230,9 +231,9 @@ module VX_tag_data_access /////////////////////// STORE LOGIC /////////////////// - wire sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE); - wire sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE); - wire sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE); + assign sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE); + assign sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE); + assign sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE); wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); @@ -279,8 +280,4 @@ module VX_tag_data_access assign fill_saw_dirty_st1e = force_write && dirty_st1e && miss_st1e; assign invalidate_line = is_snp_st1e && !miss_st1e; -endmodule - - - - +endmodule \ No newline at end of file diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 4f3eb68b..bcd3b87d 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -127,7 +127,7 @@ `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) -`define SINGLE_CORE_BENCH +//`define SINGLE_CORE_BENCH `define GLOBAL_BLOCK_SIZE_BYTES 16 From 8fd742edd860e77ce4e1b49153bf3b5f068a1a31 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 26 Mar 2020 03:56:44 -0400 Subject: [PATCH 52/66] fixed Modelsim build errors --- rtl/VX_alu.v | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/rtl/VX_alu.v b/rtl/VX_alu.v index 53b05b2d..07b090e6 100644 --- a/rtl/VX_alu.v +++ b/rtl/VX_alu.v @@ -25,6 +25,9 @@ module VX_alu( wire[63:0] mul_data_a, mul_data_b; wire[63:0] mul_result; + wire[31:0] ALU_in1; + wire[31:0] ALU_in2; + VX_divide #( .WIDTHN(32), .WIDTHD(32), @@ -123,9 +126,6 @@ module VX_alu( `ifdef SYN_FUNC wire which_in2; - - wire[31:0] ALU_in1; - wire[31:0] ALU_in2; wire[31:0] upper_immed; assign which_in2 = in_rs2_src == `RS2_IMMED; @@ -164,10 +164,7 @@ module VX_alu( end `else - wire which_in2; - - wire[31:0] ALU_in1; - wire[31:0] ALU_in2; + wire which_in2; wire[31:0] upper_immed; @@ -209,4 +206,4 @@ module VX_alu( end `endif -endmodule : VX_alu +endmodule : VX_alu \ No newline at end of file From 33d8c507dff459c8c942c92c0af09773d43326b9 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Thu, 26 Mar 2020 00:03:50 -0400 Subject: [PATCH 53/66] Remove VX_define.h and *_synth and runtime/config.h --- rtl/VX_define_synth.v | 20 -------- rtl/simulate/VX_define.h | 100 --------------------------------------- runtime/config.h | 2 - 3 files changed, 122 deletions(-) delete mode 100644 rtl/VX_define_synth.v delete mode 100644 rtl/simulate/VX_define.h delete mode 100644 runtime/config.h diff --git a/rtl/VX_define_synth.v b/rtl/VX_define_synth.v deleted file mode 100644 index 79d1a158..00000000 --- a/rtl/VX_define_synth.v +++ /dev/null @@ -1,20 +0,0 @@ - -`ifndef VX_DEFINE_SYNTH -`define VX_DEFINE_SYNTH - -`define NT 8 -`define NW 8 -`define NUMBER_CORES_PER_CLUSTER 1 -`define NUMBER_CLUSTERS 1 -`define DCACHE_SIZE_BYTES 4096 -`define ICACHE_SIZE_BYTES 1024 - -// L2 Cache size -`define LLCACHE_SIZE_BYTES 8192 - -// `define QUEUE_FORCE_MLAB 1 - -// Use l3 cache (required for cluster behavior) -// `define L3C 1 - -`endif diff --git a/rtl/simulate/VX_define.h b/rtl/simulate/VX_define.h deleted file mode 100644 index ed10c77f..00000000 --- a/rtl/simulate/VX_define.h +++ /dev/null @@ -1,100 +0,0 @@ -#define NT 4 -#define NT_M1 (NT-1) - -#define NW 8 - -#define CACHE_NUM_BANKS 8 -#define CACHE_WORDS_PER_BLOCK 4 - -#define R_INST 51 -#define L_INST 3 -#define ALU_INST 19 -#define S_INST 35 -#define B_INST 99 -#define LUI_INST 55 -#define AUIPC_INST 23 -#define JAL_INST 111 -#define JALR_INST 103 -#define SYS_INST 115 - - -#define WB_ALU 1 -#define WB_MEM 2 -#define WB_JAL 3 -#define NO_WB 0 - - -#define RS2_IMMED 1 -#define RS2_REG 0 - - -#define NO_MEM_READ 7 -#define LB_MEM_READ 0 -#define LH_MEM_READ 1 -#define LW_MEM_READ 2 -#define LBU_MEM_READ 4 -#define LHU_MEM_READ 5 - - -#define NO_MEM_WRITE 7 -#define SB_MEM_WRITE 0 -#define SH_MEM_WRITE 1 -#define SW_MEM_WRITE 2 - - -#define NO_BRANCH 0 -#define BEQ 1 -#define BNE 2 -#define BLT 3 -#define BGT 4 -#define BLTU 5 -#define BGTU 6 - - -#define NO_ALU 15 -#define ADD 0 -#define SUB 1 -#define SLLA 2 -#define SLT 3 -#define SLTU 4 -#define XOR 5 -#define SRL 6 -#define SRA 7 -#define OR 8 -#define AND 9 -#define SUBU 10 -#define LUI_ALU 11 -#define AUIPC_ALU 12 -#define CSR_ALU_RW 13 -#define CSR_ALU_RS 14 -#define CSR_ALU_RC 15 - - - -// WRITEBACK -#define WB_ALU 1 -#define WB_MEM 2 -#define WB_JAL 3 -#define NO_WB 0 - - -// JAL -#define JUMP 1 -#define NO_JUMP 0 - -// STALLS -#define STALL 1 -#define NO_STALL 0 - - -#define TAKEN 1 -#define NOT_TAKEN 0 - - -#define ZERO_REG 0 - - -// COLORS -#define GREEN "\033[32m" -#define RED "\033[31m" -#define DEFAULT "\033[39m" diff --git a/runtime/config.h b/runtime/config.h deleted file mode 100644 index 304cca89..00000000 --- a/runtime/config.h +++ /dev/null @@ -1,2 +0,0 @@ -#define TOTAL_THREADS 4 -#define TOTAL_WARPS 4 From 3b74f071a76d4b7f473aff741326a2969791e962 Mon Sep 17 00:00:00 2001 From: wgulian3 Date: Thu, 26 Mar 2020 04:05:23 -0400 Subject: [PATCH 54/66] Generate define overrides based on env vars for C and Verilog. gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code. --- .gitignore | 3 +- rtl/.gitignore | 4 + rtl/Makefile | 16 ++- rtl/VX_define.v | 270 +++++++++++++++++++++++++++++++++++++++++---- rtl/gen_config.py | 139 +++++++++++++++++++++++ runtime/.gitignore | 1 + runtime/Makefile | 6 + 7 files changed, 408 insertions(+), 31 deletions(-) create mode 100644 rtl/.gitignore create mode 100755 rtl/gen_config.py create mode 100644 runtime/.gitignore create mode 100644 runtime/Makefile diff --git a/.gitignore b/.gitignore index 736cd776..8d425cc4 100644 --- a/.gitignore +++ b/.gitignore @@ -4,5 +4,6 @@ ./rtl/modelsim/*.vcd *.vcd .* +!.gitignore *.pyc -__pycache__ \ No newline at end of file +__pycache__ diff --git a/rtl/.gitignore b/rtl/.gitignore new file mode 100644 index 00000000..f46f5734 --- /dev/null +++ b/rtl/.gitignore @@ -0,0 +1,4 @@ +/simulate/VX_define.h +/simulate/VX_define_synth.h +/VX_define_synth.v +/results.txt \ No newline at end of file diff --git a/rtl/Makefile b/rtl/Makefile index 0154e0bd..2cb83a4c 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -34,29 +34,33 @@ MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG= THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))' ) +.PHONY: build_config +build_config: + ./gen_config.py --rtl_locations + # -LDFLAGS '-lsystemc' -VERILATOR: +VERILATOR: build_config echo "#define VCD_OFF" > simulate/tb_debug.h verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW) -VERILATORnoWarnings: +VERILATORnoWarnings: build_config echo "#define VCD_OFF" > simulate/tb_debug.h verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB) -VERILATORnoWarningsRel: +VERILATORnoWarningsRel: build_config echo "#define VCD_OFF" > simulate/tb_debug.h verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CFRel) $(WNO) --threads $(THREADS) -VERILATORMULTInoWarnings: +VERILATORMULTInoWarnings: build_config echo "#define VCD_OFF" > simulate/tb_debug.h verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) $(CF) $(WNO) $(DEB) -compdebug: +compdebug: build_config echo "#define VCD_OUTPUT" > simulate/tb_debug.h verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) -compdebugmulti: +compdebugmulti: build_config echo "#define VCD_OUTPUT" > simulate/tb_debug.h verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 4f3eb68b..9271c16f 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -3,6 +3,22 @@ `include "./VX_define_synth.v" +`ifndef NT +`define NT 4 +`endif +`ifndef NW +`define NW 8 +`endif +`ifndef NUMBER_CORES_PER_CLUSTER +`define NUMBER_CORES_PER_CLUSTER 2 +`endif +`ifndef NUMBER_CLUSTERS +`define NUMBER_CLUSTERS 1 +`endif + +// `define QUEUE_FORCE_MLAB 1 +// `define L3C 1 + `define NT_M1 (`NT-1) // NW_M1 is actually log2(NW) @@ -15,7 +31,9 @@ // `define ASIC 1 // `define SYN_FUNC 1 +`ifndef NUM_BARRIERS `define NUM_BARRIERS 4 +`endif `define R_INST 7'd51 `define L_INST 7'd3 @@ -105,8 +123,8 @@ `define NO_STALL 1'h0 -`define TAKEN 1'b1 -`define NOT_TAKEN 1'b0 +`define TAKEN 1'h1 +`define NOT_TAKEN 1'h0 `define ZERO_REG 5'h0 @@ -125,59 +143,103 @@ -199 +`ifndef NUMBER_CORES `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) +`endif -`define SINGLE_CORE_BENCH - +// `define SINGLE_CORE_BENCH 0 +`ifndef GLOBAL_BLOCK_SIZE_BYTES `define GLOBAL_BLOCK_SIZE_BYTES 16 - +`endif // ========================================= Dcache Configurable Knobs ========================================= // General Cache Knobs + // Size of cache in bytes + `ifndef DCACHE_SIZE_BYTES + `define DCACHE_SIZE_BYTES 4096 + `endif // Size of line inside a bank in bytes + `ifndef DBANK_LINE_SIZE_BYTES `define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES + `endif // Number of banks {1, 2, 4, 8,...} + `ifndef DNUMBER_BANKS `define DNUMBER_BANKS 8 + `endif // Size of a word in bytes + `ifndef DWORD_SIZE_BYTES `define DWORD_SIZE_BYTES 4 + `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} + `ifndef DNUMBER_REQUESTS `define DNUMBER_REQUESTS `NT + `endif // Number of cycles to complete stage 1 (read from memory) - `define DSTAGE_1_CYCLES 1 + `ifndef DSTAGE_1_CYCLES + `define DSTAGE_1_CYCLES 2 + `endif // Function ID + `ifndef DFUNC_ID `define DFUNC_ID 0 + `endif // Bank Number of words in a line + `ifndef DBANK_LINE_SIZE_WORDS `define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES) + `endif + `ifndef DBANK_LINE_SIZE_RNG `define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0 + `endif // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size + `ifndef DREQQ_SIZE `define DREQQ_SIZE `NW + `endif // Miss Reserv Queue Knob + `ifndef DMRVQ_SIZE `define DMRVQ_SIZE (`NW*`NT) + `endif // Dram Fill Rsp Queue Size + `ifndef DDFPQ_SIZE `define DDFPQ_SIZE 2 + `endif // Snoop Req Queue + `ifndef DSNRQ_SIZE `define DSNRQ_SIZE 8 + `endif // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size + `ifndef DCWBQ_SIZE `define DCWBQ_SIZE `DREQQ_SIZE + `endif // Dram Writeback Queue Size + `ifndef DDWBQ_SIZE `define DDWBQ_SIZE 4 + `endif // Dram Fill Req Queue Size + `ifndef DDFQQ_SIZE `define DDFQQ_SIZE `DREQQ_SIZE + `endif // Lower Level Cache Hit Queue Size + `ifndef DLLVQ_SIZE `define DLLVQ_SIZE 0 + `endif // Fill Forward SNP Queue + `ifndef DFFSQ_SIZE `define DFFSQ_SIZE 8 + `endif // Fill Invalidator Size {Fill invalidator must be active} - `define DFILL_INVALIDAOR_SIZE 0 + `ifndef DFILL_INVALIDAOR_SIZE + `define DFILL_INVALIDAOR_SIZE 16 + `endif // Dram knobs + `ifndef DSIMULATED_DRAM_LATENCY_CYCLES `define DSIMULATED_DRAM_LATENCY_CYCLES 10 + `endif // ========================================= Dcache Configurable Knobs ========================================= @@ -185,50 +247,92 @@ // ========================================= Icache Configurable Knobs ========================================= // General Cache Knobs + // Size of cache in bytes + `ifndef ICACHE_SIZE_BYTES + `define ICACHE_SIZE_BYTES 1024 + `endif // Size of line inside a bank in bytes + `ifndef IBANK_LINE_SIZE_BYTES `define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES + `endif // Number of banks {1, 2, 4, 8,...} + `ifndef INUMBER_BANKS `define INUMBER_BANKS 8 + `endif // Size of a word in bytes + `ifndef IWORD_SIZE_BYTES `define IWORD_SIZE_BYTES 4 + `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} + `ifndef INUMBER_REQUESTS `define INUMBER_REQUESTS 1 + `endif // Number of cycles to complete stage 1 (read from memory) - `define ISTAGE_1_CYCLES 1 + `ifndef ISTAGE_1_CYCLES + `define ISTAGE_1_CYCLES 2 + `endif // Function ID + `ifndef IFUNC_ID `define IFUNC_ID 1 + `endif // Bank Number of words in a line + `ifndef IBANK_LINE_SIZE_WORDS `define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES) + `endif + `ifndef IBANK_LINE_SIZE_RNG `define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0 + `endif // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size + `ifndef IREQQ_SIZE `define IREQQ_SIZE `NW + `endif // Miss Reserv Queue Knob + `ifndef IMRVQ_SIZE `define IMRVQ_SIZE `IREQQ_SIZE + `endif // Dram Fill Rsp Queue Size + `ifndef IDFPQ_SIZE `define IDFPQ_SIZE 2 + `endif // Snoop Req Queue + `ifndef ISNRQ_SIZE `define ISNRQ_SIZE 8 + `endif // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size + `ifndef ICWBQ_SIZE `define ICWBQ_SIZE `IREQQ_SIZE + `endif // Dram Writeback Queue Size - `define IDWBQ_SIZE 16 + `ifndef IDWBQ_SIZE + `define IDWBQ_SIZE 0 + `endif // Dram Fill Req Queue Size + `ifndef IDFQQ_SIZE `define IDFQQ_SIZE `IREQQ_SIZE + `endif // Lower Level Cache Hit Queue Size - `define ILLVQ_SIZE 16 + `ifndef ILLVQ_SIZE + `define ILLVQ_SIZE 0 + `endif // Fill Forward SNP Queue + `ifndef IFFSQ_SIZE `define IFFSQ_SIZE 8 + `endif // Fill Invalidator Size {Fill invalidator must be active} - `define IFILL_INVALIDAOR_SIZE 0 + `ifndef IFILL_INVALIDAOR_SIZE + `define IFILL_INVALIDAOR_SIZE 16 + `endif // Dram knobs + `ifndef ISIMULATED_DRAM_LATENCY_CYCLES `define ISIMULATED_DRAM_LATENCY_CYCLES 10 + `endif // ========================================= Icache Configurable Knobs ========================================= @@ -236,51 +340,91 @@ // General Cache Knobs // Size of cache in bytes + `ifndef SCACHE_SIZE_BYTES `define SCACHE_SIZE_BYTES 1024 + `endif // Size of line inside a bank in bytes + `ifndef SBANK_LINE_SIZE_BYTES `define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES + `endif // Number of banks {1, 2, 4, 8,...} + `ifndef SNUMBER_BANKS `define SNUMBER_BANKS 8 + `endif // Size of a word in bytes + `ifndef SWORD_SIZE_BYTES `define SWORD_SIZE_BYTES 4 + `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} + `ifndef SNUMBER_REQUESTS `define SNUMBER_REQUESTS `NT + `endif // Number of cycles to complete stage 1 (read from memory) - `define SSTAGE_1_CYCLES 1 + `ifndef SSTAGE_1_CYCLES + `define SSTAGE_1_CYCLES 2 + `endif // Function ID + `ifndef SFUNC_ID `define SFUNC_ID 2 + `endif // Bank Number of words in a line + `ifndef SBANK_LINE_SIZE_WORDS `define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES) + `endif + `ifndef SBANK_LINE_SIZE_RNG `define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0 + `endif // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size + `ifndef SREQQ_SIZE `define SREQQ_SIZE `NW + `endif // Miss Reserv Queue Knob + `ifndef SMRVQ_SIZE `define SMRVQ_SIZE `SREQQ_SIZE + `endif // Dram Fill Rsp Queue Size - `define SDFPQ_SIZE 16 + `ifndef SDFPQ_SIZE + `define SDFPQ_SIZE 0 + `endif // Snoop Req Queue - `define SSNRQ_SIZE 16 + `ifndef SSNRQ_SIZE + `define SSNRQ_SIZE 0 + `endif // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size + `ifndef SCWBQ_SIZE `define SCWBQ_SIZE `SREQQ_SIZE + `endif // Dram Writeback Queue Size - `define SDWBQ_SIZE 16 + `ifndef SDWBQ_SIZE + `define SDWBQ_SIZE 0 + `endif // Dram Fill Req Queue Size - `define SDFQQ_SIZE 16 + `ifndef SDFQQ_SIZE + `define SDFQQ_SIZE 0 + `endif // Lower Level Cache Hit Queue Size - `define SLLVQ_SIZE 16 + `ifndef SLLVQ_SIZE + `define SLLVQ_SIZE 0 + `endif // Fill Forward SNP Queue - `define SFFSQ_SIZE 16 + `ifndef SFFSQ_SIZE + `define SFFSQ_SIZE 0 + `endif // Fill Invalidator Size {Fill invalidator must be active} - `define SFILL_INVALIDAOR_SIZE 0 + `ifndef SFILL_INVALIDAOR_SIZE + `define SFILL_INVALIDAOR_SIZE 16 + `endif // Dram knobs + `ifndef SSIMULATED_DRAM_LATENCY_CYCLES `define SSIMULATED_DRAM_LATENCY_CYCLES 10 + `endif // ========================================= SM Configurable Knobs ========================================= @@ -289,50 +433,90 @@ // ========================================= L2cache Configurable Knobs ========================================= // General Cache Knobs + // Size of cache in bytes + `ifndef LLCACHE_SIZE_BYTES + `define LLCACHE_SIZE_BYTES 1024 + `endif // Size of line inside a bank in bytes + `ifndef LLBANK_LINE_SIZE_BYTES `define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES + `endif // Number of banks {1, 2, 4, 8,...} + `ifndef LLNUMBER_BANKS `define LLNUMBER_BANKS 8 + `endif // Size of a word in bytes + `ifndef LLWORD_SIZE_BYTES `define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) + `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} + `ifndef LLNUMBER_REQUESTS `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER) + `endif // Number of cycles to complete stage 1 (read from memory) - `define LLSTAGE_1_CYCLES 1 + `ifndef LLSTAGE_1_CYCLES + `define LLSTAGE_1_CYCLES 2 + `endif // Function ID `define LLFUNC_ID 3 // Bank Number of words in a line + `ifndef LLBANK_LINE_SIZE_WORDS `define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES) + `endif + `ifndef LLBANK_LINE_SIZE_RNG `define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0 + `endif // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size + `ifndef LLREQQ_SIZE `define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER) + `endif // Miss Reserv Queue Knob + `ifndef LLMRVQ_SIZE `define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER) + `endif // Dram Fill Rsp Queue Size + `ifndef LLDFPQ_SIZE `define LLDFPQ_SIZE 2 + `endif // Snoop Req Queue + `ifndef LLSNRQ_SIZE `define LLSNRQ_SIZE 8 + `endif // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size + `ifndef LLCWBQ_SIZE `define LLCWBQ_SIZE `LLREQQ_SIZE + `endif // Dram Writeback Queue Size + `ifndef LLDWBQ_SIZE `define LLDWBQ_SIZE 4 + `endif // Dram Fill Req Queue Size + `ifndef LLDFQQ_SIZE `define LLDFQQ_SIZE `LLREQQ_SIZE + `endif // Lower Level Cache Hit Queue Size - `define LLLLVQ_SIZE 16 + `ifndef LLLLVQ_SIZE + `define LLLLVQ_SIZE 0 + `endif // Fill Forward SNP Queue + `ifndef LLFFSQ_SIZE `define LLFFSQ_SIZE 8 + `endif // Fill Invalidator Size {Fill invalidator must be active} - `define LLFILL_INVALIDAOR_SIZE 0 + `ifndef LLFILL_INVALIDAOR_SIZE + `define LLFILL_INVALIDAOR_SIZE 16 + `endif // Dram knobs + `ifndef LLSIMULATED_DRAM_LATENCY_CYCLES `define LLSIMULATED_DRAM_LATENCY_CYCLES 10 + `endif // ========================================= L2cache Configurable Knobs ========================================= @@ -340,51 +524,89 @@ // ========================================= L3cache Configurable Knobs ========================================= // General Cache Knobs // Size of cache in bytes + `ifndef L3CACHE_SIZE_BYTES `define L3CACHE_SIZE_BYTES 1024 + `endif // Size of line inside a bank in bytes + `ifndef L3BANK_LINE_SIZE_BYTES `define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES + `endif // Number of banks {1, 2, 4, 8,...} + `ifndef L3NUMBER_BANKS `define L3NUMBER_BANKS 8 + `endif // Size of a word in bytes + `ifndef L3WORD_SIZE_BYTES `define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES) + `endif // Number of Word requests per cycle {1, 2, 4, 8, ...} + `ifndef L3NUMBER_REQUESTS `define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS) + `endif // Number of cycles to complete stage 1 (read from memory) - `define L3STAGE_1_CYCLES 1 + `ifndef L3STAGE_1_CYCLES + `define L3STAGE_1_CYCLES 2 + `endif // Function ID `define L3FUNC_ID 3 // Bank Number of words in a line + `ifndef L3BANK_LINE_SIZE_WORDS `define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES) + `endif + `ifndef L3BANK_LINE_SIZE_RNG `define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0 + `endif // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size + `ifndef L3REQQ_SIZE `define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS) + `endif // Miss Reserv Queue Knob + `ifndef L3MRVQ_SIZE `define L3MRVQ_SIZE `LLREQQ_SIZE + `endif // Dram Fill Rsp Queue Size + `ifndef L3DFPQ_SIZE `define L3DFPQ_SIZE 2 + `endif // Snoop Req Queue + `ifndef L3SNRQ_SIZE `define L3SNRQ_SIZE 8 + `endif // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size + `ifndef L3CWBQ_SIZE `define L3CWBQ_SIZE `L3REQQ_SIZE + `endif // Dram Writeback Queue Size + `ifndef L3DWBQ_SIZE `define L3DWBQ_SIZE 4 + `endif // Dram Fill Req Queue Size + `ifndef L3DFQQ_SIZE `define L3DFQQ_SIZE `L3REQQ_SIZE + `endif // Lower Level Cache Hit Queue Size + `ifndef L3LLVQ_SIZE `define L3LLVQ_SIZE 0 + `endif // Fill Forward SNP Queue + `ifndef L3FFSQ_SIZE `define L3FFSQ_SIZE 8 + `endif // Fill Invalidator Size {Fill invalidator must be active} - `define L3FILL_INVALIDAOR_SIZE 0 + `ifndef L3FILL_INVALIDAOR_SIZE + `define L3FILL_INVALIDAOR_SIZE 16 + `endif // Dram knobs + `ifndef L3SIMULATED_DRAM_LATENCY_CYCLES `define L3SIMULATED_DRAM_LATENCY_CYCLES 10 + `endif // ========================================= L3cache Configurable Knobs ========================================= diff --git a/rtl/gen_config.py b/rtl/gen_config.py new file mode 100755 index 00000000..5835fbac --- /dev/null +++ b/rtl/gen_config.py @@ -0,0 +1,139 @@ +#!/usr/bin/env python3 +# coding=utf-8 +from __future__ import print_function + +import os +import os.path as path +import re +import argparse +from datetime import datetime + +rtl_root = path.dirname(path.realpath(__file__)) + +defines = {} +for k, v in os.environ.items(): + if k.upper().startswith('V_'): + defines[k[2:]] = v + +print('Custom params:', ', '.join(['='.join(x) for x in defines.items()])) + +parser = argparse.ArgumentParser() +parser.add_argument('--outc', default='none', help='Output C header') +parser.add_argument('--outv', default='none', help='Output Verilog header') +parser.add_argument('--rtl_locations', action='store_true', help='use outc and outv for rtl and rtl/simulate') + +args = parser.parse_args() + +if args.rtl_locations: + args.outc = path.join(rtl_root, 'simulate/VX_define.h') + args.outv = path.join(rtl_root, 'VX_define_synth.v') + +if args.outc == 'none' and args.outv == 'none': + print('Warning: not emitting any files. Specify arguments') + +if args.outv != 'none': + with open(args.outv, 'w') as f: + print(''' +// auto-generated by gen_config.py. DO NOT EDIT +// Generated at {date} + +`ifndef VX_DEFINE_SYNTH +`define VX_DEFINE_SYNTH +'''[1:].format(date=datetime.now()), file=f) + + for k, v in defines.items(): + print('`define {} {}'.format(k, v), file=f) + + print('\n`endif', file=f) + +if args.outc != 'none': + with open(args.outc, 'w') as f: + print(''' +// auto-generated by gen_config.py. DO NOT EDIT +// Generated at {date} + +#ifndef VX_DEFINE_SYNTH +#define VX_DEFINE_SYNTH +'''[1:].format(date=datetime.now()), file=f) + + for k, v in defines.items(): + print('#define {} {}'.format(k, v), file=f) + + print('\n#endif', file=f) + +translation_rules = [ + (re.compile(r'^$'), r''), + (re.compile(r'^( *)`ifndef ([^ ]+)$'), r'\1#ifndef \2'), + (re.compile(r'^( *)`define ([^ ]+)$'), r'\1#define \2'), + # (re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r'\1#include "VX_define_synth.h"'), + (re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r''), + (re.compile(r'^( *)`define ([^ ]+) (.+)$'), r'\1#define \2 \3'), + (re.compile(r'^( *)`endif$'), r'\1#endif'), + (re.compile(r'^( *)// (.*)$'), r'\1// \2'), +] + +post_rules = [ + (re.compile(r"\d+'d(\d+)"), r'\1'), + + # non-standard C but supported by GCC and Clang + (re.compile(r"\d+'b([01]+)"), r'0b\1'), + (re.compile(r"\d+'h([\da-fA-F]+)"), r'0x\1'), + + # fix macro references (does not support escaped identifiers §5.6.1) + (re.compile(r"`([A-Za-z_][$_0-9A-Za-z]*)"), r'\1'), +] + + +def post_process_line(line): + for pat, repl in post_rules: + line = pat.sub(repl, line) + return line + + +in_expansion = False + +if args.outc != 'none': + with open(args.outc, 'a') as f: + print(''' +// auto-generated by gen_config.py. DO NOT EDIT +// Generated at {date} + +// Translated from VX_define.v: +'''[1:].format(date=datetime.now()), file=f) + with open(path.join(rtl_root, 'VX_define.v'), 'r') as r: + for line in r: + if in_expansion: + f.write(post_process_line(line)) + if not line.strip().endswith('\\'): + in_expansion = False + else: + for pat, repl in translation_rules: + if pat.match(line): + if line.strip().endswith('\\'): + in_expansion = True + f.write(post_process_line(pat.sub(repl, line))) + break + else: + raise ValueError('failed to find rule for: ' + line) + + print(''' +// Misc + +#define THREADS_PER_WARP NT +#define WARPS_PER_CORE NW +#define NUMBER_WI (NW * NT * NUMBER_CORES_PER_CLUSTER * NUMBER_CLUSTERS) + +// legacy +#define TOTAL_THREADS NUMBER_WI +#define TOTAL_WARPS (NW * NUMBER_CORES_PER_CLUSTER * NUMBER_CLUSTERS) + + + +// COLORS +#define GREEN "\\033[32m" +#define RED "\\033[31m" +#define DEFAULT "\\033[39m" +'''[1:], file=f) + + + diff --git a/runtime/.gitignore b/runtime/.gitignore new file mode 100644 index 00000000..18e58a75 --- /dev/null +++ b/runtime/.gitignore @@ -0,0 +1 @@ +/config.h diff --git a/runtime/Makefile b/runtime/Makefile new file mode 100644 index 00000000..2a6bdb37 --- /dev/null +++ b/runtime/Makefile @@ -0,0 +1,6 @@ + +.PHONY: build_config +build_config: + ../rtl/gen_config.py --outv none --outc ./config.h + + From a82dd9387d8eb5e82269d5a67f5bd66062aa6efe Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 26 Mar 2020 04:14:36 -0400 Subject: [PATCH 55/66] refactoring RTL simulator and Makefile --- rtl/Makefile | 33 +++++------- rtl/simulate/{test_bench.h => Vortex.h} | 44 +++++----------- .../{multi_test_bench.h => Vortex_SOC.h} | 52 +++++++------------ rtl/simulate/multi_test_bench.cpp | 25 +++++---- rtl/simulate/ram.h | 15 +++--- rtl/simulate/test_bench.cpp | 27 ++++++---- 6 files changed, 87 insertions(+), 109 deletions(-) rename rtl/simulate/{test_bench.h => Vortex.h} (93%) rename rtl/simulate/{multi_test_bench.h => Vortex_SOC.h} (91%) diff --git a/rtl/Makefile b/rtl/Makefile index 0154e0bd..645e5a06 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -1,6 +1,5 @@ all: RUNFILE - INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate SINGLE_CORE=Vortex.v @@ -19,12 +18,9 @@ LIGHTW=-Wno-UNOPTFLAT # LIB=-LDFLAGS '-L/usr/local/systemc/' LIB= -CF=-CFLAGS '-std=c++11 -fms-extensions' - -CFRel=-CFLAGS '-std=c++11 -fms-extensions -O3 -DVL_THREADED' - -DEB=--trace --prof-cfuncs -DVL_DEBUG=1 +CF = -std=c++11 -fms-extensions +DEB=--trace -DVL_DEBUG=1 MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) @@ -32,33 +28,27 @@ MAKECPPRel=(cd obj_dir && make -j -f VVortex.mk) MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) -THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))' ) +THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') # -LDFLAGS '-lsystemc' VERILATOR: - echo "#define VCD_OFF" > simulate/tb_debug.h - verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW) + verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(LIGHTW) VERILATORnoWarnings: - echo "#define VCD_OFF" > simulate/tb_debug.h - verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB) + verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB) VERILATORnoWarningsRel: - echo "#define VCD_OFF" > simulate/tb_debug.h - verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CFRel) $(WNO) --threads $(THREADS) + verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) --threads $(THREADS) VERILATORMULTInoWarnings: - echo "#define VCD_OFF" > simulate/tb_debug.h - verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) $(CF) $(WNO) $(DEB) + verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) $(DEB) --threads $(THREADS) compdebug: - echo "#define VCD_OUTPUT" > simulate/tb_debug.h - verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) + verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) compdebugmulti: - echo "#define VCD_OUTPUT" > simulate/tb_debug.h - verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) + verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) RUNFILE: VERILATOR $(MAKECPP) @@ -81,8 +71,11 @@ dmulticore: compdebugmulti run: w (cd obj_dir && ./VVortex) +run-multicore: multicore + (cd obj_dir && ./VVortex_SOC) + runRel: wRel (cd obj_dir && ./VVortex) clean: - rm -rf obj_dir + rm -rf obj_dir \ No newline at end of file diff --git a/rtl/simulate/test_bench.h b/rtl/simulate/Vortex.h similarity index 93% rename from rtl/simulate/test_bench.h rename to rtl/simulate/Vortex.h index e8c5f222..1a9d5883 100644 --- a/rtl/simulate/test_bench.h +++ b/rtl/simulate/Vortex.h @@ -16,8 +16,6 @@ #include "VVortex__Syms.h" #include "verilated.h" -#include "tb_debug.h" - #ifdef VCD_OUTPUT #include #endif @@ -40,17 +38,16 @@ typedef struct class Vortex { public: - Vortex(); + Vortex(RAM* ram); ~Vortex(); - bool simulate(std::string); - private: - void ProcessFile(void); + bool simulate(); + private: void print_stats(bool = true); bool ibus_driver(); bool dbus_driver(); void io_handler(); - RAM ram; + RAM* ram; VVortex * vortex; @@ -62,7 +59,6 @@ class Vortex long int curr_cycle; bool stop; bool unit_test; - std::string instruction_file_name; std::ofstream results; int stats_static_inst; int stats_dynamic_inst; @@ -87,11 +83,12 @@ class Vortex -Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), +Vortex::Vortex(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) { + this->ram = ram; this->vortex = new VVortex; #ifdef VCD_OUTPUT this->m_trace = new VerilatedVcdC; @@ -110,12 +107,6 @@ Vortex::~Vortex() delete this->vortex; } - -void Vortex::ProcessFile(void) -{ - loadHexImpl(this->instruction_file_name.c_str(), &this->ram); -} - void Vortex::print_stats(bool cycle_test) { @@ -139,7 +130,7 @@ void Vortex::print_stats(bool cycle_test) uint32_t status; - ram.getWord(0, &status); + ram->getWord(0, &status); if (this->unit_test) { @@ -202,7 +193,7 @@ bool Vortex::ibus_driver() { unsigned curr_addr = dram_req.base_addr + (i*4); unsigned data_rd; - ram.getWord(curr_addr, &data_rd); + ram->getWord(curr_addr, &data_rd); dram_req.data[i] = data_rd; } // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; @@ -218,7 +209,7 @@ bool Vortex::ibus_driver() { unsigned curr_addr = base_addr + (i*4); unsigned data_wr = vortex->I_dram_req_data[i]; - ram.writeWord(curr_addr, &data_wr); + ram->writeWord(curr_addr, &data_wr); } } } @@ -301,7 +292,7 @@ bool Vortex::dbus_driver() { unsigned curr_addr = dram_req.base_addr + (i*4); unsigned data_rd; - ram.getWord(curr_addr, &data_rd); + ram->getWord(curr_addr, &data_rd); dram_req.data[i] = data_rd; } // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; @@ -317,7 +308,7 @@ bool Vortex::dbus_driver() { unsigned curr_addr = base_addr + (i*4); unsigned data_wr = vortex->dram_req_data[i]; - ram.writeWord(curr_addr, &data_wr); + ram->writeWord(curr_addr, &data_wr); } } } @@ -347,17 +338,10 @@ bool Vortex::dbus_driver() -bool Vortex::simulate(std::string file_to_simulate) +bool Vortex::simulate() { - - this->instruction_file_name = file_to_simulate; - // this->results << "\n****************\t" << file_to_simulate << "\t****************\n"; - - this->ProcessFile(); - // auto start_time = std::chrono::high_resolution_clock::now(); - static bool stop = false; static int counter = 0; counter = 0; @@ -470,7 +454,7 @@ bool Vortex::simulate(std::string file_to_simulate) // std::cout << "Something: " << result << '\n'; // uint32_t status; - // ram.getWord(0, &status); + // ram->getWord(0, &status); this->print_stats(); @@ -478,4 +462,4 @@ bool Vortex::simulate(std::string file_to_simulate) return (status == 1); // return (1 == 1); -} +} \ No newline at end of file diff --git a/rtl/simulate/multi_test_bench.h b/rtl/simulate/Vortex_SOC.h similarity index 91% rename from rtl/simulate/multi_test_bench.h rename to rtl/simulate/Vortex_SOC.h index 1e783ca0..374693f8 100644 --- a/rtl/simulate/multi_test_bench.h +++ b/rtl/simulate/Vortex_SOC.h @@ -15,8 +15,6 @@ #include "VVortex_SOC.h" #include "verilated.h" -#include "tb_debug.h" - #ifdef VCD_OUTPUT #include #endif @@ -36,20 +34,19 @@ typedef struct unsigned * data; } dram_req_t; -class Vortex +class Vortex_SOC { public: - Vortex(); - ~Vortex(); - bool simulate(std::string); + Vortex_SOC(RAM* ram); + ~Vortex_SOC(); + bool simulate(); private: - void ProcessFile(void); void print_stats(bool = true); bool ibus_driver(); bool dbus_driver(); void io_handler(); - RAM ram; + RAM* ram; VVortex_SOC * vortex; @@ -61,7 +58,6 @@ class Vortex long int curr_cycle; bool stop; bool unit_test; - std::string instruction_file_name; std::ofstream results; int stats_static_inst; int stats_dynamic_inst; @@ -85,11 +81,12 @@ class Vortex -Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), +Vortex_SOC::Vortex_SOC(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) { + this->ram = ram; this->vortex = new VVortex_SOC; #ifdef VCD_OUTPUT this->m_trace = new VerilatedVcdC; @@ -99,7 +96,7 @@ Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stat this->results.open("../results.txt"); } -Vortex::~Vortex() +Vortex_SOC::~Vortex_SOC() { #ifdef VCD_OUTPUT m_trace->close(); @@ -108,13 +105,7 @@ Vortex::~Vortex() delete this->vortex; } - -void Vortex::ProcessFile(void) -{ - loadHexImpl(this->instruction_file_name.c_str(), &this->ram); -} - -void Vortex::print_stats(bool cycle_test) +void Vortex_SOC::print_stats(bool cycle_test) { if (cycle_test) @@ -137,7 +128,7 @@ void Vortex::print_stats(bool cycle_test) uint32_t status; - ram.getWord(0, &status); + ram->getWord(0, &status); if (this->unit_test) { @@ -162,14 +153,14 @@ void Vortex::print_stats(bool cycle_test) } -bool Vortex::ibus_driver() +bool Vortex_SOC::ibus_driver() { return false; } -void Vortex::io_handler() +void Vortex_SOC::io_handler() { // std::cout << "Checking\n"; for (int c = 0; c < vortex->number_cores; c++) @@ -188,7 +179,7 @@ void Vortex::io_handler() } -bool Vortex::dbus_driver() +bool Vortex_SOC::dbus_driver() { // Iterate through each element, and get pop index @@ -224,7 +215,7 @@ bool Vortex::dbus_driver() { unsigned curr_addr = dram_req.base_addr + (i*4); unsigned data_rd; - ram.getWord(curr_addr, &data_rd); + ram->getWord(curr_addr, &data_rd); dram_req.data[i] = data_rd; } // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; @@ -240,7 +231,7 @@ bool Vortex::dbus_driver() { unsigned curr_addr = base_addr + (i*4); unsigned data_wr = vortex->out_dram_req_data[i]; - ram.writeWord(curr_addr, &data_wr); + ram->writeWord(curr_addr, &data_wr); } } } @@ -270,17 +261,10 @@ bool Vortex::dbus_driver() -bool Vortex::simulate(std::string file_to_simulate) +bool Vortex_SOC::simulate() { - - this->instruction_file_name = file_to_simulate; - // this->results << "\n****************\t" << file_to_simulate << "\t****************\n"; - - this->ProcessFile(); - // auto start_time = std::chrono::high_resolution_clock::now(); - static bool stop = false; static int counter = 0; counter = 0; @@ -394,7 +378,7 @@ bool Vortex::simulate(std::string file_to_simulate) // std::cout << "Something: " << result << '\n'; // uint32_t status; - // ram.getWord(0, &status); + // ram->getWord(0, &status); this->print_stats(); @@ -402,4 +386,4 @@ bool Vortex::simulate(std::string file_to_simulate) return (status == 1); // return (1 == 1); -} +} \ No newline at end of file diff --git a/rtl/simulate/multi_test_bench.cpp b/rtl/simulate/multi_test_bench.cpp index 6da0928e..7dcc0436 100644 --- a/rtl/simulate/multi_test_bench.cpp +++ b/rtl/simulate/multi_test_bench.cpp @@ -1,4 +1,4 @@ -#include "multi_test_bench.h" +#include "Vortex_SOC.h" #define NUM_TESTS 46 @@ -65,13 +65,16 @@ int main(int argc, char **argv) }; for (std::string s : tests) { - Vortex v; - - std::cerr << DEFAULT << "\n---------------------------------------\n"; + std::cerr << DEFAULT << "\n---------------------------------------\n"; std::cerr << s << std::endl; - bool curr = v.simulate(s); + RAM ram; + loadHexImpl(s.c_str(), &ram); + + Vortex_SOC v(&ram); + bool curr = v.simulate(); + if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl; if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl; std::cerr << DEFAULT; @@ -90,7 +93,7 @@ int main(int argc, char **argv) char testing[] = "../../runtime/mains/simple/vx_simple_main.hex"; // char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex"; // char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; - Vortex v; + // const char *testing; // if (argc >= 2) { @@ -99,14 +102,18 @@ int main(int argc, char **argv) // testing = "../../kernel/vortex_test.hex"; // } - std::cerr << testing << std::endl; + std::cerr << testing << std::endl; + RAM ram; + loadHexImpl(testing, &ram); + + Vortex_SOC v(&ram); + bool curr = v.simulate(); - bool curr = v.simulate(testing); if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; return !curr; #endif -} +} \ No newline at end of file diff --git a/rtl/simulate/ram.h b/rtl/simulate/ram.h index 13f78e94..39fb011e 100644 --- a/rtl/simulate/ram.h +++ b/rtl/simulate/ram.h @@ -1,5 +1,4 @@ #ifndef __RAM__ - #define __RAM__ // #include "string.h" @@ -12,8 +11,8 @@ class RAM; uint32_t hti(char); -uint32_t hToI(char *, uint32_t); -void loadHexImpl(char *,RAM*); +uint32_t hToI(const char *, uint32_t); +void loadHexImpl(const char *,RAM*); class RAM{ public: @@ -26,6 +25,10 @@ public: for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i]; } + size_t size() const { + return (1ull << 32); + } + void clear(){ for(uint32_t i = 0;i < (1 << 12);i++) { @@ -149,7 +152,7 @@ public: // MEMORY UTILS -uint32_t hti(char c) { +inline uint32_t hti(char c) { if (c >= 'A' && c <= 'F') return c - 'A' + 10; if (c >= 'a' && c <= 'f') @@ -157,7 +160,7 @@ uint32_t hti(char c) { return c - '0'; } -uint32_t hToI(char *c, uint32_t size) { +inline uint32_t hToI(const char *c, uint32_t size) { uint32_t value = 0; for (uint32_t i = 0; i < size; i++) { value += hti(c[i]) << ((size - i - 1) * 4); @@ -167,7 +170,7 @@ uint32_t hToI(char *c, uint32_t size) { -void loadHexImpl(const char *path, RAM* mem) { +inline void loadHexImpl(const char *path, RAM* mem) { mem->clear(); FILE *fp = fopen(path, "r"); if(fp == 0){ diff --git a/rtl/simulate/test_bench.cpp b/rtl/simulate/test_bench.cpp index 66c0b617..391c93db 100644 --- a/rtl/simulate/test_bench.cpp +++ b/rtl/simulate/test_bench.cpp @@ -1,4 +1,4 @@ -#include "test_bench.h" +#include "Vortex.h" #define NUM_TESTS 46 @@ -66,13 +66,16 @@ int main(int argc, char **argv) }; for (std::string s : tests) { - Vortex v; - std::cerr << DEFAULT << "\n---------------------------------------\n"; std::cerr << s << std::endl; - bool curr = v.simulate(s); + RAM ram; + loadHexImpl(s.c_str(), &ram); + + Vortex v(&ram); + bool curr = v.simulate(); + if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl; if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl; std::cerr << DEFAULT; @@ -89,9 +92,9 @@ int main(int argc, char **argv) #else char testing[] = "../../runtime/mains/simple/vx_simple_main.hex"; - // char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex"; - // char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; - Vortex v; + //char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex"; + //char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; + // const char *testing; // if (argc >= 2) { @@ -100,14 +103,18 @@ int main(int argc, char **argv) // testing = "../../kernel/vortex_test.hex"; // } - std::cerr << testing << std::endl; + std::cerr << testing << std::endl; + RAM ram; + loadHexImpl(testing, &ram); + + Vortex v(&ram); + bool curr = v.simulate(); - bool curr = v.simulate(testing); if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; return !curr; #endif -} +} \ No newline at end of file From 985b01cb99cb378f74d13a20148d3a48873ac9c9 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 12:41:03 -0400 Subject: [PATCH 56/66] adding back build_config target dependency --- rtl/Makefile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/rtl/Makefile b/rtl/Makefile index 32aee812..2dfc0c32 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -35,23 +35,23 @@ build_config: ./gen_config.py --rtl_locations # -LDFLAGS '-lsystemc' -VERILATOR: +VERILATOR: build_config verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(LIGHTW) -VERILATORnoWarnings: +VERILATORnoWarnings: build_config verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB) -VERILATORnoWarningsRel: +VERILATORnoWarningsRel: build_config verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) --threads $(THREADS) -VERILATORMULTInoWarnings: +VERILATORMULTInoWarnings: build_config verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) $(DEB) --threads $(THREADS) -compdebug: +compdebug: build_config verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) -compdebugmulti: +compdebugmulti: build_config verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) RUNFILE: VERILATOR From 3df21b6e715503b084842c0c1dc39b97c47ab8db Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 13:19:11 -0400 Subject: [PATCH 57/66] fixed regression bug with Vortex.v model hanging issue --- rtl/VX_define.v | 108 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 89 insertions(+), 19 deletions(-) diff --git a/rtl/VX_define.v b/rtl/VX_define.v index fa496680..eea7f791 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -6,12 +6,15 @@ `ifndef NT `define NT 4 `endif + `ifndef NW `define NW 8 `endif + `ifndef NUMBER_CORES_PER_CLUSTER `define NUMBER_CORES_PER_CLUSTER 2 `endif + `ifndef NUMBER_CLUSTERS `define NUMBER_CLUSTERS 1 `endif @@ -160,26 +163,32 @@ `ifndef DCACHE_SIZE_BYTES `define DCACHE_SIZE_BYTES 4096 `endif + // Size of line inside a bank in bytes `ifndef DBANK_LINE_SIZE_BYTES `define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES `endif + // Number of banks {1, 2, 4, 8,...} `ifndef DNUMBER_BANKS `define DNUMBER_BANKS 8 `endif + // Size of a word in bytes `ifndef DWORD_SIZE_BYTES `define DWORD_SIZE_BYTES 4 `endif + // Number of Word requests per cycle {1, 2, 4, 8, ...} `ifndef DNUMBER_REQUESTS `define DNUMBER_REQUESTS `NT `endif + // Number of cycles to complete stage 1 (read from memory) `ifndef DSTAGE_1_CYCLES - `define DSTAGE_1_CYCLES 2 + `define DSTAGE_1_CYCLES 1 `endif + // Function ID `ifndef DFUNC_ID `define DFUNC_ID 0 @@ -235,7 +244,7 @@ // Fill Invalidator Size {Fill invalidator must be active} `ifndef DFILL_INVALIDAOR_SIZE - `define DFILL_INVALIDAOR_SIZE 16 + `define DFILL_INVALIDAOR_SIZE 0 `endif // Dram knobs @@ -253,26 +262,32 @@ `ifndef ICACHE_SIZE_BYTES `define ICACHE_SIZE_BYTES 1024 `endif + // Size of line inside a bank in bytes `ifndef IBANK_LINE_SIZE_BYTES `define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES `endif + // Number of banks {1, 2, 4, 8,...} `ifndef INUMBER_BANKS `define INUMBER_BANKS 8 `endif + // Size of a word in bytes `ifndef IWORD_SIZE_BYTES `define IWORD_SIZE_BYTES 4 `endif + // Number of Word requests per cycle {1, 2, 4, 8, ...} `ifndef INUMBER_REQUESTS `define INUMBER_REQUESTS 1 `endif + // Number of cycles to complete stage 1 (read from memory) `ifndef ISTAGE_1_CYCLES - `define ISTAGE_1_CYCLES 2 + `define ISTAGE_1_CYCLES 1 `endif + // Function ID `ifndef IFUNC_ID `define IFUNC_ID 1 @@ -282,45 +297,55 @@ `ifndef IBANK_LINE_SIZE_WORDS `define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES) `endif + `ifndef IBANK_LINE_SIZE_RNG `define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0 `endif + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size `ifndef IREQQ_SIZE `define IREQQ_SIZE `NW `endif + // Miss Reserv Queue Knob `ifndef IMRVQ_SIZE `define IMRVQ_SIZE `IREQQ_SIZE `endif + // Dram Fill Rsp Queue Size `ifndef IDFPQ_SIZE `define IDFPQ_SIZE 2 `endif + // Snoop Req Queue `ifndef ISNRQ_SIZE `define ISNRQ_SIZE 8 `endif // Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size `ifndef ICWBQ_SIZE `define ICWBQ_SIZE `IREQQ_SIZE `endif + // Dram Writeback Queue Size `ifndef IDWBQ_SIZE - `define IDWBQ_SIZE 0 + `define IDWBQ_SIZE 16 `endif + // Dram Fill Req Queue Size `ifndef IDFQQ_SIZE `define IDFQQ_SIZE `IREQQ_SIZE `endif + // Lower Level Cache Hit Queue Size `ifndef ILLVQ_SIZE - `define ILLVQ_SIZE 0 + `define ILLVQ_SIZE 16 `endif + // Fill Forward SNP Queue `ifndef IFFSQ_SIZE `define IFFSQ_SIZE 8 @@ -328,7 +353,7 @@ // Fill Invalidator Size {Fill invalidator must be active} `ifndef IFILL_INVALIDAOR_SIZE - `define IFILL_INVALIDAOR_SIZE 16 + `define IFILL_INVALIDAOR_SIZE 0 `endif // Dram knobs @@ -345,26 +370,32 @@ `ifndef SCACHE_SIZE_BYTES `define SCACHE_SIZE_BYTES 1024 `endif + // Size of line inside a bank in bytes `ifndef SBANK_LINE_SIZE_BYTES `define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES `endif + // Number of banks {1, 2, 4, 8,...} `ifndef SNUMBER_BANKS `define SNUMBER_BANKS 8 `endif + // Size of a word in bytes `ifndef SWORD_SIZE_BYTES `define SWORD_SIZE_BYTES 4 `endif + // Number of Word requests per cycle {1, 2, 4, 8, ...} `ifndef SNUMBER_REQUESTS `define SNUMBER_REQUESTS `NT `endif + // Number of cycles to complete stage 1 (read from memory) `ifndef SSTAGE_1_CYCLES - `define SSTAGE_1_CYCLES 2 + `define SSTAGE_1_CYCLES 1 `endif + // Function ID `ifndef SFUNC_ID `define SFUNC_ID 2 @@ -374,53 +405,63 @@ `ifndef SBANK_LINE_SIZE_WORDS `define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES) `endif + `ifndef SBANK_LINE_SIZE_RNG `define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0 `endif + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size `ifndef SREQQ_SIZE `define SREQQ_SIZE `NW `endif + // Miss Reserv Queue Knob `ifndef SMRVQ_SIZE `define SMRVQ_SIZE `SREQQ_SIZE `endif + // Dram Fill Rsp Queue Size `ifndef SDFPQ_SIZE - `define SDFPQ_SIZE 0 + `define SDFPQ_SIZE 16 `endif + // Snoop Req Queue `ifndef SSNRQ_SIZE - `define SSNRQ_SIZE 0 + `define SSNRQ_SIZE 16 `endif // Queues for writebacks Knobs {1, 2, 4, 8, ...} + // Core Writeback Queue Size `ifndef SCWBQ_SIZE `define SCWBQ_SIZE `SREQQ_SIZE `endif + // Dram Writeback Queue Size `ifndef SDWBQ_SIZE - `define SDWBQ_SIZE 0 + `define SDWBQ_SIZE 16 `endif + // Dram Fill Req Queue Size `ifndef SDFQQ_SIZE - `define SDFQQ_SIZE 0 + `define SDFQQ_SIZE 16 `endif + // Lower Level Cache Hit Queue Size `ifndef SLLVQ_SIZE - `define SLLVQ_SIZE 0 + `define SLLVQ_SIZE 16 `endif + // Fill Forward SNP Queue `ifndef SFFSQ_SIZE - `define SFFSQ_SIZE 0 + `define SFFSQ_SIZE 16 `endif // Fill Invalidator Size {Fill invalidator must be active} `ifndef SFILL_INVALIDAOR_SIZE - `define SFILL_INVALIDAOR_SIZE 16 + `define SFILL_INVALIDAOR_SIZE 0 `endif // Dram knobs @@ -439,26 +480,32 @@ `ifndef LLCACHE_SIZE_BYTES `define LLCACHE_SIZE_BYTES 1024 `endif + // Size of line inside a bank in bytes `ifndef LLBANK_LINE_SIZE_BYTES `define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES `endif + // Number of banks {1, 2, 4, 8,...} `ifndef LLNUMBER_BANKS `define LLNUMBER_BANKS 8 `endif + // Size of a word in bytes `ifndef LLWORD_SIZE_BYTES `define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) `endif + // Number of Word requests per cycle {1, 2, 4, 8, ...} `ifndef LLNUMBER_REQUESTS `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER) `endif + // Number of cycles to complete stage 1 (read from memory) `ifndef LLSTAGE_1_CYCLES - `define LLSTAGE_1_CYCLES 2 + `define LLSTAGE_1_CYCLES 1 `endif + // Function ID `define LLFUNC_ID 3 @@ -466,6 +513,7 @@ `ifndef LLBANK_LINE_SIZE_WORDS `define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES) `endif + `ifndef LLBANK_LINE_SIZE_RNG `define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0 `endif @@ -475,14 +523,17 @@ `ifndef LLREQQ_SIZE `define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER) `endif + // Miss Reserv Queue Knob `ifndef LLMRVQ_SIZE `define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER) `endif + // Dram Fill Rsp Queue Size `ifndef LLDFPQ_SIZE `define LLDFPQ_SIZE 2 `endif + // Snoop Req Queue `ifndef LLSNRQ_SIZE `define LLSNRQ_SIZE 8 @@ -493,18 +544,22 @@ `ifndef LLCWBQ_SIZE `define LLCWBQ_SIZE `LLREQQ_SIZE `endif + // Dram Writeback Queue Size `ifndef LLDWBQ_SIZE `define LLDWBQ_SIZE 4 `endif + // Dram Fill Req Queue Size `ifndef LLDFQQ_SIZE `define LLDFQQ_SIZE `LLREQQ_SIZE `endif + // Lower Level Cache Hit Queue Size `ifndef LLLLVQ_SIZE - `define LLLLVQ_SIZE 0 + `define LLLLVQ_SIZE 16 `endif + // Fill Forward SNP Queue `ifndef LLFFSQ_SIZE `define LLFFSQ_SIZE 8 @@ -512,7 +567,7 @@ // Fill Invalidator Size {Fill invalidator must be active} `ifndef LLFILL_INVALIDAOR_SIZE - `define LLFILL_INVALIDAOR_SIZE 16 + `define LLFILL_INVALIDAOR_SIZE 0 `endif // Dram knobs @@ -529,26 +584,32 @@ `ifndef L3CACHE_SIZE_BYTES `define L3CACHE_SIZE_BYTES 1024 `endif + // Size of line inside a bank in bytes `ifndef L3BANK_LINE_SIZE_BYTES `define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES `endif + // Number of banks {1, 2, 4, 8,...} `ifndef L3NUMBER_BANKS `define L3NUMBER_BANKS 8 `endif + // Size of a word in bytes `ifndef L3WORD_SIZE_BYTES `define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES) `endif + // Number of Word requests per cycle {1, 2, 4, 8, ...} `ifndef L3NUMBER_REQUESTS `define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS) `endif + // Number of cycles to complete stage 1 (read from memory) `ifndef L3STAGE_1_CYCLES - `define L3STAGE_1_CYCLES 2 + `define L3STAGE_1_CYCLES 1 `endif + // Function ID `define L3FUNC_ID 3 @@ -556,23 +617,28 @@ `ifndef L3BANK_LINE_SIZE_WORDS `define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES) `endif + `ifndef L3BANK_LINE_SIZE_RNG `define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0 `endif + // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size `ifndef L3REQQ_SIZE `define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS) `endif + // Miss Reserv Queue Knob `ifndef L3MRVQ_SIZE `define L3MRVQ_SIZE `LLREQQ_SIZE `endif + // Dram Fill Rsp Queue Size `ifndef L3DFPQ_SIZE `define L3DFPQ_SIZE 2 `endif + // Snoop Req Queue `ifndef L3SNRQ_SIZE `define L3SNRQ_SIZE 8 @@ -583,18 +649,22 @@ `ifndef L3CWBQ_SIZE `define L3CWBQ_SIZE `L3REQQ_SIZE `endif + // Dram Writeback Queue Size `ifndef L3DWBQ_SIZE `define L3DWBQ_SIZE 4 `endif + // Dram Fill Req Queue Size `ifndef L3DFQQ_SIZE `define L3DFQQ_SIZE `L3REQQ_SIZE `endif + // Lower Level Cache Hit Queue Size `ifndef L3LLVQ_SIZE `define L3LLVQ_SIZE 0 `endif + // Fill Forward SNP Queue `ifndef L3FFSQ_SIZE `define L3FFSQ_SIZE 8 @@ -602,7 +672,7 @@ // Fill Invalidator Size {Fill invalidator must be active} `ifndef L3FILL_INVALIDAOR_SIZE - `define L3FILL_INVALIDAOR_SIZE 16 + `define L3FILL_INVALIDAOR_SIZE 0 `endif // Dram knobs From 6dc3d0d3715b0e138090649efe8571897bff58bd Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 13:56:16 -0400 Subject: [PATCH 58/66] refactor VX_define.v --- rtl/VX_define.v | 1052 ++++++++++++++++++++++++----------------------- 1 file changed, 529 insertions(+), 523 deletions(-) diff --git a/rtl/VX_define.v b/rtl/VX_define.v index eea7f791..7c0840fd 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -159,528 +159,534 @@ // ========================================= Dcache Configurable Knobs ========================================= // General Cache Knobs - // Size of cache in bytes - `ifndef DCACHE_SIZE_BYTES - `define DCACHE_SIZE_BYTES 4096 - `endif - - // Size of line inside a bank in bytes - `ifndef DBANK_LINE_SIZE_BYTES - `define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES - `endif - - // Number of banks {1, 2, 4, 8,...} - `ifndef DNUMBER_BANKS - `define DNUMBER_BANKS 8 - `endif - - // Size of a word in bytes - `ifndef DWORD_SIZE_BYTES - `define DWORD_SIZE_BYTES 4 - `endif - - // Number of Word requests per cycle {1, 2, 4, 8, ...} - `ifndef DNUMBER_REQUESTS - `define DNUMBER_REQUESTS `NT - `endif - - // Number of cycles to complete stage 1 (read from memory) - `ifndef DSTAGE_1_CYCLES - `define DSTAGE_1_CYCLES 1 - `endif - - // Function ID - `ifndef DFUNC_ID - `define DFUNC_ID 0 - `endif - - // Bank Number of words in a line - `ifndef DBANK_LINE_SIZE_WORDS - `define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES) - `endif - `ifndef DBANK_LINE_SIZE_RNG - `define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0 - `endif -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - - // Core Request Queue Size - `ifndef DREQQ_SIZE - `define DREQQ_SIZE `NW - `endif - // Miss Reserv Queue Knob - `ifndef DMRVQ_SIZE - `define DMRVQ_SIZE (`NW*`NT) - `endif - // Dram Fill Rsp Queue Size - `ifndef DDFPQ_SIZE - `define DDFPQ_SIZE 2 - `endif - // Snoop Req Queue - `ifndef DSNRQ_SIZE - `define DSNRQ_SIZE 8 - `endif - -// Queues for writebacks Knobs {1, 2, 4, 8, ...} - // Core Writeback Queue Size - `ifndef DCWBQ_SIZE - `define DCWBQ_SIZE `DREQQ_SIZE - `endif - // Dram Writeback Queue Size - `ifndef DDWBQ_SIZE - `define DDWBQ_SIZE 4 - `endif - // Dram Fill Req Queue Size - `ifndef DDFQQ_SIZE - `define DDFQQ_SIZE `DREQQ_SIZE - `endif - // Lower Level Cache Hit Queue Size - `ifndef DLLVQ_SIZE - `define DLLVQ_SIZE 0 - `endif - // Fill Forward SNP Queue - `ifndef DFFSQ_SIZE - `define DFFSQ_SIZE 8 - `endif - - // Fill Invalidator Size {Fill invalidator must be active} - `ifndef DFILL_INVALIDAOR_SIZE - `define DFILL_INVALIDAOR_SIZE 0 - `endif - -// Dram knobs - `ifndef DSIMULATED_DRAM_LATENCY_CYCLES - `define DSIMULATED_DRAM_LATENCY_CYCLES 10 - `endif - -// ========================================= Dcache Configurable Knobs ========================================= - - -// ========================================= Icache Configurable Knobs ========================================= - -// General Cache Knobs - // Size of cache in bytes - `ifndef ICACHE_SIZE_BYTES - `define ICACHE_SIZE_BYTES 1024 - `endif - - // Size of line inside a bank in bytes - `ifndef IBANK_LINE_SIZE_BYTES - `define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES - `endif - - // Number of banks {1, 2, 4, 8,...} - `ifndef INUMBER_BANKS - `define INUMBER_BANKS 8 - `endif - - // Size of a word in bytes - `ifndef IWORD_SIZE_BYTES - `define IWORD_SIZE_BYTES 4 - `endif - - // Number of Word requests per cycle {1, 2, 4, 8, ...} - `ifndef INUMBER_REQUESTS - `define INUMBER_REQUESTS 1 - `endif - - // Number of cycles to complete stage 1 (read from memory) - `ifndef ISTAGE_1_CYCLES - `define ISTAGE_1_CYCLES 1 - `endif - - // Function ID - `ifndef IFUNC_ID - `define IFUNC_ID 1 - `endif - - // Bank Number of words in a line - `ifndef IBANK_LINE_SIZE_WORDS - `define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES) - `endif - - `ifndef IBANK_LINE_SIZE_RNG - `define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0 - `endif - -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - - // Core Request Queue Size - `ifndef IREQQ_SIZE - `define IREQQ_SIZE `NW - `endif - - // Miss Reserv Queue Knob - `ifndef IMRVQ_SIZE - `define IMRVQ_SIZE `IREQQ_SIZE - `endif - - // Dram Fill Rsp Queue Size - `ifndef IDFPQ_SIZE - `define IDFPQ_SIZE 2 - `endif - - // Snoop Req Queue - `ifndef ISNRQ_SIZE - `define ISNRQ_SIZE 8 - `endif - -// Queues for writebacks Knobs {1, 2, 4, 8, ...} - - // Core Writeback Queue Size - `ifndef ICWBQ_SIZE - `define ICWBQ_SIZE `IREQQ_SIZE - `endif - - // Dram Writeback Queue Size - `ifndef IDWBQ_SIZE - `define IDWBQ_SIZE 16 - `endif - - // Dram Fill Req Queue Size - `ifndef IDFQQ_SIZE - `define IDFQQ_SIZE `IREQQ_SIZE - `endif - - // Lower Level Cache Hit Queue Size - `ifndef ILLVQ_SIZE - `define ILLVQ_SIZE 16 - `endif - - // Fill Forward SNP Queue - `ifndef IFFSQ_SIZE - `define IFFSQ_SIZE 8 - `endif - - // Fill Invalidator Size {Fill invalidator must be active} - `ifndef IFILL_INVALIDAOR_SIZE - `define IFILL_INVALIDAOR_SIZE 0 - `endif - -// Dram knobs - `ifndef ISIMULATED_DRAM_LATENCY_CYCLES - `define ISIMULATED_DRAM_LATENCY_CYCLES 10 - `endif - -// ========================================= Icache Configurable Knobs ========================================= - -// ========================================= SM Configurable Knobs ========================================= - -// General Cache Knobs - // Size of cache in bytes - `ifndef SCACHE_SIZE_BYTES - `define SCACHE_SIZE_BYTES 1024 - `endif - - // Size of line inside a bank in bytes - `ifndef SBANK_LINE_SIZE_BYTES - `define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES - `endif - - // Number of banks {1, 2, 4, 8,...} - `ifndef SNUMBER_BANKS - `define SNUMBER_BANKS 8 - `endif - - // Size of a word in bytes - `ifndef SWORD_SIZE_BYTES - `define SWORD_SIZE_BYTES 4 - `endif - - // Number of Word requests per cycle {1, 2, 4, 8, ...} - `ifndef SNUMBER_REQUESTS - `define SNUMBER_REQUESTS `NT - `endif - - // Number of cycles to complete stage 1 (read from memory) - `ifndef SSTAGE_1_CYCLES - `define SSTAGE_1_CYCLES 1 - `endif - - // Function ID - `ifndef SFUNC_ID - `define SFUNC_ID 2 - `endif - - // Bank Number of words in a line - `ifndef SBANK_LINE_SIZE_WORDS - `define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES) - `endif - - `ifndef SBANK_LINE_SIZE_RNG - `define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0 - `endif - -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - - // Core Request Queue Size - `ifndef SREQQ_SIZE - `define SREQQ_SIZE `NW - `endif - - // Miss Reserv Queue Knob - `ifndef SMRVQ_SIZE - `define SMRVQ_SIZE `SREQQ_SIZE - `endif - - // Dram Fill Rsp Queue Size - `ifndef SDFPQ_SIZE - `define SDFPQ_SIZE 16 - `endif - - // Snoop Req Queue - `ifndef SSNRQ_SIZE - `define SSNRQ_SIZE 16 - `endif - -// Queues for writebacks Knobs {1, 2, 4, 8, ...} - - // Core Writeback Queue Size - `ifndef SCWBQ_SIZE - `define SCWBQ_SIZE `SREQQ_SIZE - `endif - - // Dram Writeback Queue Size - `ifndef SDWBQ_SIZE - `define SDWBQ_SIZE 16 - `endif - - // Dram Fill Req Queue Size - `ifndef SDFQQ_SIZE - `define SDFQQ_SIZE 16 - `endif - - // Lower Level Cache Hit Queue Size - `ifndef SLLVQ_SIZE - `define SLLVQ_SIZE 16 - `endif - - // Fill Forward SNP Queue - `ifndef SFFSQ_SIZE - `define SFFSQ_SIZE 16 - `endif - - // Fill Invalidator Size {Fill invalidator must be active} - `ifndef SFILL_INVALIDAOR_SIZE - `define SFILL_INVALIDAOR_SIZE 0 - `endif - -// Dram knobs - `ifndef SSIMULATED_DRAM_LATENCY_CYCLES - `define SSIMULATED_DRAM_LATENCY_CYCLES 10 - `endif - -// ========================================= SM Configurable Knobs ========================================= - - - -// ========================================= L2cache Configurable Knobs ========================================= - -// General Cache Knobs - // Size of cache in bytes - `ifndef LLCACHE_SIZE_BYTES - `define LLCACHE_SIZE_BYTES 1024 - `endif - - // Size of line inside a bank in bytes - `ifndef LLBANK_LINE_SIZE_BYTES - `define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES - `endif - - // Number of banks {1, 2, 4, 8,...} - `ifndef LLNUMBER_BANKS - `define LLNUMBER_BANKS 8 - `endif - - // Size of a word in bytes - `ifndef LLWORD_SIZE_BYTES - `define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) - `endif - - // Number of Word requests per cycle {1, 2, 4, 8, ...} - `ifndef LLNUMBER_REQUESTS - `define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER) - `endif - - // Number of cycles to complete stage 1 (read from memory) - `ifndef LLSTAGE_1_CYCLES - `define LLSTAGE_1_CYCLES 1 - `endif - - // Function ID - `define LLFUNC_ID 3 - - // Bank Number of words in a line - `ifndef LLBANK_LINE_SIZE_WORDS - `define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES) - `endif - - `ifndef LLBANK_LINE_SIZE_RNG - `define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0 - `endif -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - - // Core Request Queue Size - `ifndef LLREQQ_SIZE - `define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER) - `endif - - // Miss Reserv Queue Knob - `ifndef LLMRVQ_SIZE - `define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER) - `endif - - // Dram Fill Rsp Queue Size - `ifndef LLDFPQ_SIZE - `define LLDFPQ_SIZE 2 - `endif - - // Snoop Req Queue - `ifndef LLSNRQ_SIZE - `define LLSNRQ_SIZE 8 - `endif - -// Queues for writebacks Knobs {1, 2, 4, 8, ...} - // Core Writeback Queue Size - `ifndef LLCWBQ_SIZE - `define LLCWBQ_SIZE `LLREQQ_SIZE - `endif - - // Dram Writeback Queue Size - `ifndef LLDWBQ_SIZE - `define LLDWBQ_SIZE 4 - `endif - - // Dram Fill Req Queue Size - `ifndef LLDFQQ_SIZE - `define LLDFQQ_SIZE `LLREQQ_SIZE - `endif - - // Lower Level Cache Hit Queue Size - `ifndef LLLLVQ_SIZE - `define LLLLVQ_SIZE 16 - `endif - - // Fill Forward SNP Queue - `ifndef LLFFSQ_SIZE - `define LLFFSQ_SIZE 8 - `endif - - // Fill Invalidator Size {Fill invalidator must be active} - `ifndef LLFILL_INVALIDAOR_SIZE - `define LLFILL_INVALIDAOR_SIZE 0 - `endif - -// Dram knobs - `ifndef LLSIMULATED_DRAM_LATENCY_CYCLES - `define LLSIMULATED_DRAM_LATENCY_CYCLES 10 - `endif - -// ========================================= L2cache Configurable Knobs ========================================= - - -// ========================================= L3cache Configurable Knobs ========================================= -// General Cache Knobs - // Size of cache in bytes - `ifndef L3CACHE_SIZE_BYTES - `define L3CACHE_SIZE_BYTES 1024 - `endif - - // Size of line inside a bank in bytes - `ifndef L3BANK_LINE_SIZE_BYTES - `define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES - `endif - - // Number of banks {1, 2, 4, 8,...} - `ifndef L3NUMBER_BANKS - `define L3NUMBER_BANKS 8 - `endif - - // Size of a word in bytes - `ifndef L3WORD_SIZE_BYTES - `define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES) - `endif - - // Number of Word requests per cycle {1, 2, 4, 8, ...} - `ifndef L3NUMBER_REQUESTS - `define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS) - `endif - - // Number of cycles to complete stage 1 (read from memory) - `ifndef L3STAGE_1_CYCLES - `define L3STAGE_1_CYCLES 1 - `endif - - // Function ID - `define L3FUNC_ID 3 - - // Bank Number of words in a line - `ifndef L3BANK_LINE_SIZE_WORDS - `define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES) - `endif - - `ifndef L3BANK_LINE_SIZE_RNG - `define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0 - `endif - -// Queues feeding into banks Knobs {1, 2, 4, 8, ...} - - // Core Request Queue Size - `ifndef L3REQQ_SIZE - `define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS) - `endif - - // Miss Reserv Queue Knob - `ifndef L3MRVQ_SIZE - `define L3MRVQ_SIZE `LLREQQ_SIZE - `endif - - // Dram Fill Rsp Queue Size - `ifndef L3DFPQ_SIZE - `define L3DFPQ_SIZE 2 - `endif - - // Snoop Req Queue - `ifndef L3SNRQ_SIZE - `define L3SNRQ_SIZE 8 - `endif - -// Queues for writebacks Knobs {1, 2, 4, 8, ...} - // Core Writeback Queue Size - `ifndef L3CWBQ_SIZE - `define L3CWBQ_SIZE `L3REQQ_SIZE - `endif - - // Dram Writeback Queue Size - `ifndef L3DWBQ_SIZE - `define L3DWBQ_SIZE 4 - `endif - - // Dram Fill Req Queue Size - `ifndef L3DFQQ_SIZE - `define L3DFQQ_SIZE `L3REQQ_SIZE - `endif - - // Lower Level Cache Hit Queue Size - `ifndef L3LLVQ_SIZE - `define L3LLVQ_SIZE 0 - `endif - - // Fill Forward SNP Queue - `ifndef L3FFSQ_SIZE - `define L3FFSQ_SIZE 8 - `endif - - // Fill Invalidator Size {Fill invalidator must be active} - `ifndef L3FILL_INVALIDAOR_SIZE - `define L3FILL_INVALIDAOR_SIZE 0 - `endif - -// Dram knobs - `ifndef L3SIMULATED_DRAM_LATENCY_CYCLES - `define L3SIMULATED_DRAM_LATENCY_CYCLES 10 - `endif - -// ========================================= L3cache Configurable Knobs ========================================= - +// Size of cache in bytes +`ifndef DCACHE_SIZE_BYTES +`define DCACHE_SIZE_BYTES 4096 +`endif + +// Size of line inside a bank in bytes +`ifndef DBANK_LINE_SIZE_BYTES +`define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES +`endif + +// Number of banks {1, 2, 4, 8,...} +`ifndef DNUMBER_BANKS +`define DNUMBER_BANKS 8 +`endif + +// Size of a word in bytes +`ifndef DWORD_SIZE_BYTES +`define DWORD_SIZE_BYTES 4 +`endif + +// Number of Word requests per cycle {1, 2, 4, 8, ...} +`ifndef DNUMBER_REQUESTS +`define DNUMBER_REQUESTS `NT +`endif + +// Number of cycles to complete stage 1 (read from memory) +`ifndef DSTAGE_1_CYCLES +`define DSTAGE_1_CYCLES 1 +`endif + +// Function ID +`ifndef DFUNC_ID +`define DFUNC_ID 0 +`endif + +// Bank Number of words in a line +`ifndef DBANK_LINE_SIZE_WORDS +`define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES) +`endif + +// Bank Number of words range +`ifndef DBANK_LINE_SIZE_RNG +`define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0 +`endif + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + +// Core Request Queue Size +`ifndef DREQQ_SIZE +`define DREQQ_SIZE `NW +`endif + +// Miss Reserv Queue Knob +`ifndef DMRVQ_SIZE +`define DMRVQ_SIZE (`NW*`NT) +`endif + +// Dram Fill Rsp Queue Size +`ifndef DDFPQ_SIZE +`define DDFPQ_SIZE 2 +`endif + +// Snoop Req Queue +`ifndef DSNRQ_SIZE +`define DSNRQ_SIZE 8 +`endif + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + +// Core Writeback Queue Size +`ifndef DCWBQ_SIZE +`define DCWBQ_SIZE `DREQQ_SIZE +`endif + +// Dram Writeback Queue Size +`ifndef DDWBQ_SIZE +`define DDWBQ_SIZE 4 +`endif + +// Dram Fill Req Queue Size +`ifndef DDFQQ_SIZE +`define DDFQQ_SIZE `DREQQ_SIZE +`endif + +// Lower Level Cache Hit Queue Size +`ifndef DLLVQ_SIZE +`define DLLVQ_SIZE 0 +`endif + +// Fill Forward SNP Queue +`ifndef DFFSQ_SIZE +`define DFFSQ_SIZE 8 +`endif + +// Fill Invalidator Size {Fill invalidator must be active} +`ifndef DFILL_INVALIDAOR_SIZE +`define DFILL_INVALIDAOR_SIZE 0 +`endif + +// Dram knobs +`ifndef DSIMULATED_DRAM_LATENCY_CYCLES +`define DSIMULATED_DRAM_LATENCY_CYCLES 10 +`endif + +// ========================================= Icache Configurable Knobs ========================================= + +// General Cache Knobs + +// Size of cache in bytes +`ifndef ICACHE_SIZE_BYTES +`define ICACHE_SIZE_BYTES 1024 +`endif + +// Size of line inside a bank in bytes +`ifndef IBANK_LINE_SIZE_BYTES +`define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES +`endif + +// Number of banks {1, 2, 4, 8,...} +`ifndef INUMBER_BANKS +`define INUMBER_BANKS 8 +`endif + +// Size of a word in bytes +`ifndef IWORD_SIZE_BYTES +`define IWORD_SIZE_BYTES 4 +`endif + +// Number of Word requests per cycle {1, 2, 4, 8, ...} +`ifndef INUMBER_REQUESTS +`define INUMBER_REQUESTS 1 +`endif + +// Number of cycles to complete stage 1 (read from memory) +`ifndef ISTAGE_1_CYCLES +`define ISTAGE_1_CYCLES 1 +`endif + +// Function ID +`ifndef IFUNC_ID +`define IFUNC_ID 1 +`endif + +// Bank Number of words in a line +`ifndef IBANK_LINE_SIZE_WORDS +`define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES) +`endif + +// Bank Number of words range +`ifndef IBANK_LINE_SIZE_RNG +`define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0 +`endif + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + +// Core Request Queue Size +`ifndef IREQQ_SIZE +`define IREQQ_SIZE `NW +`endif + +// Miss Reserv Queue Knob +`ifndef IMRVQ_SIZE +`define IMRVQ_SIZE `IREQQ_SIZE +`endif + +// Dram Fill Rsp Queue Size +`ifndef IDFPQ_SIZE +`define IDFPQ_SIZE 2 +`endif + +// Snoop Req Queue +`ifndef ISNRQ_SIZE +`define ISNRQ_SIZE 8 +`endif + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + +// Core Writeback Queue Size +`ifndef ICWBQ_SIZE +`define ICWBQ_SIZE `IREQQ_SIZE +`endif + +// Dram Writeback Queue Size +`ifndef IDWBQ_SIZE +`define IDWBQ_SIZE 16 +`endif + +// Dram Fill Req Queue Size +`ifndef IDFQQ_SIZE +`define IDFQQ_SIZE `IREQQ_SIZE +`endif + +// Lower Level Cache Hit Queue Size +`ifndef ILLVQ_SIZE +`define ILLVQ_SIZE 16 +`endif + +// Fill Forward SNP Queue +`ifndef IFFSQ_SIZE +`define IFFSQ_SIZE 8 +`endif + +// Fill Invalidator Size {Fill invalidator must be active} +`ifndef IFILL_INVALIDAOR_SIZE +`define IFILL_INVALIDAOR_SIZE 0 +`endif + +// Dram knobs +`ifndef ISIMULATED_DRAM_LATENCY_CYCLES +`define ISIMULATED_DRAM_LATENCY_CYCLES 10 +`endif + +// ========================================= SM Configurable Knobs ========================================= + +// General Cache Knobs +// Size of cache in bytes +`ifndef SCACHE_SIZE_BYTES +`define SCACHE_SIZE_BYTES 1024 +`endif + +// Size of line inside a bank in bytes +`ifndef SBANK_LINE_SIZE_BYTES +`define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES +`endif + +// Number of banks {1, 2, 4, 8,...} +`ifndef SNUMBER_BANKS +`define SNUMBER_BANKS 8 +`endif + +// Size of a word in bytes +`ifndef SWORD_SIZE_BYTES +`define SWORD_SIZE_BYTES 4 +`endif + +// Number of Word requests per cycle {1, 2, 4, 8, ...} +`ifndef SNUMBER_REQUESTS +`define SNUMBER_REQUESTS `NT +`endif + +// Number of cycles to complete stage 1 (read from memory) +`ifndef SSTAGE_1_CYCLES +`define SSTAGE_1_CYCLES 1 +`endif + +// Function ID +`ifndef SFUNC_ID +`define SFUNC_ID 2 +`endif + +// Bank Number of words in a line +`ifndef SBANK_LINE_SIZE_WORDS +`define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES) +`endif + +`ifndef SBANK_LINE_SIZE_RNG +`define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0 +`endif + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + +// Core Request Queue Size +`ifndef SREQQ_SIZE +`define SREQQ_SIZE `NW +`endif + +// Miss Reserv Queue Knob +`ifndef SMRVQ_SIZE +`define SMRVQ_SIZE `SREQQ_SIZE +`endif + +// Dram Fill Rsp Queue Size +`ifndef SDFPQ_SIZE +`define SDFPQ_SIZE 16 +`endif + +// Snoop Req Queue +`ifndef SSNRQ_SIZE +`define SSNRQ_SIZE 16 +`endif + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + +// Core Writeback Queue Size +`ifndef SCWBQ_SIZE +`define SCWBQ_SIZE `SREQQ_SIZE +`endif + +// Dram Writeback Queue Size +`ifndef SDWBQ_SIZE +`define SDWBQ_SIZE 16 +`endif + +// Dram Fill Req Queue Size +`ifndef SDFQQ_SIZE +`define SDFQQ_SIZE 16 +`endif + +// Lower Level Cache Hit Queue Size +`ifndef SLLVQ_SIZE +`define SLLVQ_SIZE 16 +`endif + +// Fill Forward SNP Queue +`ifndef SFFSQ_SIZE +`define SFFSQ_SIZE 16 +`endif + +// Fill Invalidator Size {Fill invalidator must be active} +`ifndef SFILL_INVALIDAOR_SIZE +`define SFILL_INVALIDAOR_SIZE 0 +`endif + +// Dram knobs +`ifndef SSIMULATED_DRAM_LATENCY_CYCLES +`define SSIMULATED_DRAM_LATENCY_CYCLES 10 +`endif + +// ========================================= L2cache Configurable Knobs ========================================= + +// General Cache Knobs + +// Size of cache in bytes +`ifndef LLCACHE_SIZE_BYTES +`define LLCACHE_SIZE_BYTES 1024 +`endif + +// Size of line inside a bank in bytes +`ifndef LLBANK_LINE_SIZE_BYTES +`define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES +`endif + +// Number of banks {1, 2, 4, 8,...} +`ifndef LLNUMBER_BANKS +`define LLNUMBER_BANKS 8 +`endif + +// Size of a word in bytes +`ifndef LLWORD_SIZE_BYTES +`define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES) +`endif + +// Number of Word requests per cycle {1, 2, 4, 8, ...} +`ifndef LLNUMBER_REQUESTS +`define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER) +`endif + +// Number of cycles to complete stage 1 (read from memory) +`ifndef LLSTAGE_1_CYCLES +`define LLSTAGE_1_CYCLES 1 +`endif + +// Function ID +`define LLFUNC_ID 3 + +// Bank Number of words in a line +`ifndef LLBANK_LINE_SIZE_WORDS +`define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES) +`endif + +`ifndef LLBANK_LINE_SIZE_RNG +`define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0 +`endif + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + +// Core Request Queue Size +`ifndef LLREQQ_SIZE +`define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER) +`endif + +// Miss Reserv Queue Knob +`ifndef LLMRVQ_SIZE +`define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER) +`endif + +// Dram Fill Rsp Queue Size +`ifndef LLDFPQ_SIZE +`define LLDFPQ_SIZE 2 +`endif + +// Snoop Req Queue +`ifndef LLSNRQ_SIZE +`define LLSNRQ_SIZE 8 +`endif + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + +// Core Writeback Queue Size +`ifndef LLCWBQ_SIZE +`define LLCWBQ_SIZE `LLREQQ_SIZE +`endif + +// Dram Writeback Queue Size +`ifndef LLDWBQ_SIZE +`define LLDWBQ_SIZE 4 +`endif + +// Dram Fill Req Queue Size +`ifndef LLDFQQ_SIZE +`define LLDFQQ_SIZE `LLREQQ_SIZE +`endif + +// Lower Level Cache Hit Queue Size +`ifndef LLLLVQ_SIZE +`define LLLLVQ_SIZE 16 +`endif + +// Fill Forward SNP Queue +`ifndef LLFFSQ_SIZE +`define LLFFSQ_SIZE 8 +`endif + +// Fill Invalidator Size {Fill invalidator must be active} +`ifndef LLFILL_INVALIDAOR_SIZE +`define LLFILL_INVALIDAOR_SIZE 0 +`endif + +// Dram knobs +`ifndef LLSIMULATED_DRAM_LATENCY_CYCLES +`define LLSIMULATED_DRAM_LATENCY_CYCLES 10 +`endif + +// ========================================= L3cache Configurable Knobs ========================================= + +// General Cache Knobs + +// Size of cache in bytes +`ifndef L3CACHE_SIZE_BYTES +`define L3CACHE_SIZE_BYTES 1024 +`endif + +// Size of line inside a bank in bytes +`ifndef L3BANK_LINE_SIZE_BYTES +`define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES +`endif + +// Number of banks {1, 2, 4, 8,...} +`ifndef L3NUMBER_BANKS +`define L3NUMBER_BANKS 8 +`endif + +// Size of a word in bytes +`ifndef L3WORD_SIZE_BYTES +`define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES) +`endif + +// Number of Word requests per cycle {1, 2, 4, 8, ...} +`ifndef L3NUMBER_REQUESTS +`define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS) +`endif + +// Number of cycles to complete stage 1 (read from memory) +`ifndef L3STAGE_1_CYCLES +`define L3STAGE_1_CYCLES 1 +`endif + +// Function ID +`define L3FUNC_ID 3 + +// Bank Number of words in a line +`ifndef L3BANK_LINE_SIZE_WORDS +`define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES) +`endif + +`ifndef L3BANK_LINE_SIZE_RNG +`define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0 +`endif + +// Queues feeding into banks Knobs {1, 2, 4, 8, ...} + +// Core Request Queue Size +`ifndef L3REQQ_SIZE +`define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS) +`endif + +// Miss Reserv Queue Knob +`ifndef L3MRVQ_SIZE +`define L3MRVQ_SIZE `LLREQQ_SIZE +`endif + +// Dram Fill Rsp Queue Size +`ifndef L3DFPQ_SIZE +`define L3DFPQ_SIZE 2 +`endif + +// Snoop Req Queue +`ifndef L3SNRQ_SIZE +`define L3SNRQ_SIZE 8 +`endif + +// Queues for writebacks Knobs {1, 2, 4, 8, ...} + +// Core Writeback Queue Size +`ifndef L3CWBQ_SIZE +`define L3CWBQ_SIZE `L3REQQ_SIZE +`endif + +// Dram Writeback Queue Size +`ifndef L3DWBQ_SIZE +`define L3DWBQ_SIZE 4 +`endif + +// Dram Fill Req Queue Size +`ifndef L3DFQQ_SIZE +`define L3DFQQ_SIZE `L3REQQ_SIZE +`endif + +// Lower Level Cache Hit Queue Size +`ifndef L3LLVQ_SIZE +`define L3LLVQ_SIZE 0 +`endif + +// Fill Forward SNP Queue +`ifndef L3FFSQ_SIZE +`define L3FFSQ_SIZE 8 +`endif + +// Fill Invalidator Size {Fill invalidator must be active} +`ifndef L3FILL_INVALIDAOR_SIZE +`define L3FILL_INVALIDAOR_SIZE 0 +`endif + +// Dram knobs +`ifndef L3SIMULATED_DRAM_LATENCY_CYCLES +`define L3SIMULATED_DRAM_LATENCY_CYCLES 10 +`endif + + // VX_DEFINE `endif From 614797e52f9e3d0da523efed67a45fb7ff147138 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Fri, 27 Mar 2020 13:15:23 -0700 Subject: [PATCH 59/66] Migrating fpga_synthesis_temp to main --- rtl/VX_cache/VX_tag_data_access.v | 2 +- rtl/VX_cache/VX_tag_data_structure.v | 3 ++- rtl/VX_define.v | 2 +- rtl/VX_lsu.v | 12 +++++++++++- runtime/mains/simple/vx_simple_main.c | 19 ++++++++++--------- 5 files changed, 25 insertions(+), 13 deletions(-) diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index b69d6a89..2c8417b8 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -262,7 +262,7 @@ module VX_tag_data_access end endgenerate - assign use_write_enable = we; + assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we; assign use_write_data = data_write; /////////////////////// diff --git a/rtl/VX_cache/VX_tag_data_structure.v b/rtl/VX_cache/VX_tag_data_structure.v index 55b9cc9e..71c7a82d 100644 --- a/rtl/VX_cache/VX_tag_data_structure.v +++ b/rtl/VX_cache/VX_tag_data_structure.v @@ -71,7 +71,8 @@ module VX_tag_data_structure reg dirty[`BANK_LINE_COUNT-1:0]; - wire[`TAG_SELECT_SIZE_RNG] kkkkkk = write_addr[`TAG_SELECT_ADDR_RNG]; + wire[`TAG_SELECT_ADDR_RNG] curr_tag = write_addr[`TAG_SELECT_ADDR_RNG]; + wire[`LINE_SELECT_ADDR_RNG] curr_inx = write_addr[`LINE_SELECT_ADDR_RNG]; assign read_valid = valid[read_addr[`LINE_SELECT_ADDR_RNG]]; assign read_dirty = dirty[read_addr[`LINE_SELECT_ADDR_RNG]]; diff --git a/rtl/VX_define.v b/rtl/VX_define.v index 7c0840fd..97749c83 100644 --- a/rtl/VX_define.v +++ b/rtl/VX_define.v @@ -12,7 +12,7 @@ `endif `ifndef NUMBER_CORES_PER_CLUSTER -`define NUMBER_CORES_PER_CLUSTER 2 +`define NUMBER_CORES_PER_CLUSTER 1 `endif `ifndef NUMBER_CLUSTERS diff --git a/rtl/VX_lsu.v b/rtl/VX_lsu.v index b962b738..a0abf1ff 100644 --- a/rtl/VX_lsu.v +++ b/rtl/VX_lsu.v @@ -69,7 +69,16 @@ module VX_lsu ( assign VX_mem_wb.wb_valid = VX_dcache_rsp.core_wb_valid; assign VX_mem_wb.wb_warp_num = VX_dcache_rsp.core_wb_warp_num; assign VX_mem_wb.loaded_data = VX_dcache_rsp.core_wb_readdata; - assign VX_mem_wb.mem_wb_pc = VX_dcache_rsp.core_wb_pc[0]; + + wire[(`CLOG2(`NT))-1:0] use_pc_index; + wire found; + VX_generic_priority_encoder #(.N(`NT)) pick_first_pc( + .valids(VX_dcache_rsp.core_wb_valid), + .index (use_pc_index), + .found (found) + ); + + assign VX_mem_wb.mem_wb_pc = VX_dcache_rsp.core_wb_pc[use_pc_index]; @@ -78,3 +87,4 @@ module VX_lsu ( endmodule // Memory + diff --git a/runtime/mains/simple/vx_simple_main.c b/runtime/mains/simple/vx_simple_main.c index 1d53458d..6cb5d966 100644 --- a/runtime/mains/simple/vx_simple_main.c +++ b/runtime/mains/simple/vx_simple_main.c @@ -39,12 +39,13 @@ void mat_add_kernel(void * void_arguments) bool valid = (wid < arguments->numRows) && (tid < arguments->numColums); - __if (valid) - { + // __if (valid) + // { unsigned index = (wid * arguments->numColums) + tid; - arguments->z[index] = arguments->x[index] + arguments->y[index]; - } - __endif + unsigned val = arguments->x[index] + arguments->y[index]; + arguments->z[index] = val; + // } + // __endif } int main() @@ -79,8 +80,8 @@ int main() // Test wspawn - vx_print_str("test_wspawn\n"); - test_wsapwn(); + // vx_print_str("test_wspawn\n"); + // test_wsapwn(); vx_print_str("Shared Memory test\n"); unsigned * ptr = (unsigned *) 0xFFFF0000; @@ -113,9 +114,9 @@ int main() // vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments); - // for (int i = 0; i < arguments.numRows; i++) + // for (int i = 0; i < numWarps; i++) // { - // for (int j = 0; j < arguments.numColums; j++) + // for (int j = 0; j < numThreads; j++) // { // unsigned index = (i * arguments.numColums) + j; // vx_print_hex(z[index]); From 5a5c9f3981a1f82ddc6d356edd7a26893f26aa3b Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 20:19:16 -0400 Subject: [PATCH 60/66] merging changes from OPAE branch making this branch --- benchmarks/new_opencl/bfs/CLHelper.h | 848 + benchmarks/new_opencl/bfs/Makefile | 44 + benchmarks/new_opencl/bfs/README | 0 benchmarks/new_opencl/bfs/graph4096.txt | 28677 ++ benchmarks/new_opencl/bfs/kernel.cl | 53 + benchmarks/new_opencl/bfs/kernel.pocl | Bin 0 -> 280860 bytes benchmarks/new_opencl/bfs/main.cc | 297 + benchmarks/new_opencl/bfs/run | 1 + benchmarks/new_opencl/bfs/timer.cc | 78 + benchmarks/new_opencl/bfs/timer.h | 101 + benchmarks/new_opencl/bfs/util.h | 72 + benchmarks/new_opencl/guassian/Makefile | 44 + .../new_opencl/guassian/OriginalParallel.c | 241 + benchmarks/new_opencl/guassian/README.txt | 60 + benchmarks/new_opencl/guassian/clutils.cpp | 1443 + benchmarks/new_opencl/guassian/clutils.h | 281 + benchmarks/new_opencl/guassian/gaussianElim.h | 40 + .../new_opencl/guassian/gettimeofday.cpp | 74 + benchmarks/new_opencl/guassian/gettimeofday.h | 17 + benchmarks/new_opencl/guassian/kernel.cl | 49 + benchmarks/new_opencl/guassian/kernel.pocl | Bin 0 -> 287484 bytes benchmarks/new_opencl/guassian/main.cc | 411 + benchmarks/new_opencl/guassian/matrix4.txt | 11 + benchmarks/new_opencl/guassian/run | 1 + benchmarks/new_opencl/guassian/utils.cpp | 204 + benchmarks/new_opencl/guassian/utils.h | 84 + benchmarks/new_opencl/include/CL/cl.h | 1804 + benchmarks/new_opencl/include/CL/cl.hpp | 12459 + benchmarks/new_opencl/include/CL/cl2.hpp | 10119 + benchmarks/new_opencl/include/CL/cl_d3d10.h | 131 + benchmarks/new_opencl/include/CL/cl_d3d11.h | 131 + .../include/CL/cl_dx9_media_sharing.h | 132 + .../include/CL/cl_dx9_media_sharing_intel.h | 182 + benchmarks/new_opencl/include/CL/cl_egl.h | 132 + benchmarks/new_opencl/include/CL/cl_ext.h | 762 + .../new_opencl/include/CL/cl_ext_intel.h | 423 + benchmarks/new_opencl/include/CL/cl_gl.h | 171 + benchmarks/new_opencl/include/CL/cl_gl_ext.h | 52 + .../new_opencl/include/CL/cl_platform.h | 1384 + .../CL/cl_va_api_media_sharing_intel.h | 172 + benchmarks/new_opencl/include/CL/cl_version.h | 86 + benchmarks/new_opencl/include/CL/opencl.h | 47 + benchmarks/new_opencl/lib/libOpenCL.so | Bin 0 -> 2038104 bytes benchmarks/new_opencl/lib/libOpenCL.so.2 | Bin 0 -> 2038104 bytes benchmarks/new_opencl/lib/libOpenCL.so.2.5.0 | Bin 0 -> 2038104 bytes benchmarks/new_opencl/nearn/Makefile | 44 + benchmarks/new_opencl/nearn/README.txt | 33 + benchmarks/new_opencl/nearn/cane4_0.db | 10691 + benchmarks/new_opencl/nearn/cane4_1.db | 10691 + benchmarks/new_opencl/nearn/cane4_2.db | 10691 + benchmarks/new_opencl/nearn/cane4_3.db | 10691 + benchmarks/new_opencl/nearn/clutils.cpp | 1443 + benchmarks/new_opencl/nearn/clutils.h | 281 + benchmarks/new_opencl/nearn/filelist.txt | 4 + benchmarks/new_opencl/nearn/ipoint.h | 29 + benchmarks/new_opencl/nearn/kernel.cl | 22 + benchmarks/new_opencl/nearn/kernel.pocl | Bin 0 -> 193922 bytes benchmarks/new_opencl/nearn/main.cc | 346 + benchmarks/new_opencl/nearn/nearestNeighbor.h | 50 + benchmarks/new_opencl/nearn/run | 1 + benchmarks/new_opencl/nearn/utils.cpp | 204 + benchmarks/new_opencl/nearn/utils.h | 84 + benchmarks/new_opencl/results.txt | 7 + benchmarks/new_opencl/saxpy/Makefile | 44 + benchmarks/new_opencl/saxpy/README | 0 benchmarks/new_opencl/saxpy/kernel.cl | 5 + benchmarks/new_opencl/saxpy/kernel.pocl | Bin 0 -> 185600 bytes benchmarks/new_opencl/saxpy/main.cc | 221 + benchmarks/new_opencl/sfilter/Makefile | 44 + benchmarks/new_opencl/sfilter/README | 0 benchmarks/new_opencl/sfilter/kernel.cl | 21 + benchmarks/new_opencl/sfilter/kernel.pocl | Bin 0 -> 196593 bytes benchmarks/new_opencl/sfilter/main.cc | 319 + benchmarks/new_opencl/sgemm/Makefile | 44 + benchmarks/new_opencl/sgemm/README | 0 benchmarks/new_opencl/sgemm/kernel.cl | 9 + benchmarks/new_opencl/sgemm/kernel.pocl | Bin 0 -> 185630 bytes benchmarks/new_opencl/sgemm/main.cc | 243 + benchmarks/new_opencl/sgemm/sgemm | Bin 0 -> 51840 bytes benchmarks/new_opencl/vecadd/Makefile | 44 + benchmarks/new_opencl/vecadd/README | 0 benchmarks/new_opencl/vecadd/kernel.cl | 8 + benchmarks/new_opencl/vecadd/kernel.pocl | Bin 0 -> 187461 bytes benchmarks/new_opencl/vecadd/main.cc | 187 + benchmarks/opencl/BlackScholes/Makefile | 2 +- benchmarks/opencl/DotProduct/Makefile | 2 +- benchmarks/opencl/VectorHypot/Makefile | 2 +- benchmarks/opencl/bfs/Makefile | 2 +- benchmarks/opencl/convolution/Makefile | 68 + benchmarks/opencl/convolution/input.bmp | Bin 0 -> 44922 bytes benchmarks/opencl/convolution/kernel.cl | 54 + benchmarks/opencl/convolution/main.cpp | 261 + benchmarks/opencl/convolution/utils.cpp | 180 + benchmarks/opencl/convolution/utils.h | 11 + benchmarks/opencl/cutcp/Makefile | 2 +- benchmarks/opencl/guassian/Makefile | 2 +- benchmarks/opencl/kmeans/Makefile | 2 +- benchmarks/opencl/lbm/Makefile | 2 +- benchmarks/opencl/mri-q/Makefile | 2 +- benchmarks/opencl/nearn/Makefile | 2 +- benchmarks/opencl/reduce0/Makefile | 2 +- benchmarks/opencl/sad/Makefile | 2 +- benchmarks/opencl/saxpy/Makefile | 2 +- benchmarks/opencl/sfilter/Makefile | 2 +- benchmarks/opencl/sgemm/Makefile | 2 +- benchmarks/opencl/spmv/Makefile | 2 +- benchmarks/opencl/stencil/Makefile | 2 +- benchmarks/opencl/transpose/Makefile | 2 +- benchmarks/opencl/vecadd/Makefile | 2 +- driver/dogfood/Memcpy/hw/rtl/_hdr | 603 + driver/dogfood/Memcpy/hw/rtl/cci_hello.json | 18 + driver/dogfood/Memcpy/hw/rtl/cci_hello_afu.sv | 653 + .../Memcpy/hw/rtl/cci_hello_afu_working.sv | 621 + driver/dogfood/Memcpy/hw/rtl/sources.txt | 2 + driver/dogfood/Memcpy/hw/sim/setup_ase | 11 + driver/dogfood/Memcpy/sw/Makefile | 41 + driver/dogfood/Memcpy/sw/cci_hello.c | 210 + driver/dogfood/Memcpy/sw/obj/afu_json_info.h | 13 + driver/dogfood/Memcpy/sw/obj/cci_hello.o | Bin 0 -> 5336 bytes driver/hw/Makefile | 24 + driver/hw/ccip_interface_reg.sv | 48 + driver/hw/ccip_std_afu.sv | 172 + driver/hw/sources.txt | 116 + driver/hw/vortex_afu.json | 37 + driver/hw/vortex_afu.sv | 638 + {opae => driver}/opae_setup.sh | 0 driver/set_env.sh | 6 + driver/sw/Makefile | 19 + driver/sw/include/vortex.h | 67 + driver/sw/opae/Makefile | 66 + driver/sw/opae/vortex.cpp | 349 + driver/sw/rtlsim/Makefile | 49 + driver/sw/rtlsim/vortex.cpp | 327 + driver/sw/simx/Makefile | 37 + driver/sw/simx/libvortex.so | Bin 0 -> 405672 bytes driver/sw/simx/vortex.cpp | 324 + driver/sw/vx_utils.cpp | 91 + driver/tests/basic/Makefile | 37 + driver/tests/basic/basic | Bin 0 -> 18968 bytes driver/tests/basic/basic.cpp | 107 + driver/tests/demo/Makefile | 70 + driver/tests/demo/demo | Bin 0 -> 105576 bytes driver/tests/demo/demo.bin | Bin 0 -> 5188 bytes driver/tests/demo/demo.cpp | 75 + driver/tests/demo/demo.elf | Bin 0 -> 36456 bytes driver/tests/demo/demo.hex | 269 + driver/tests/demo/kernel.c | 25 + driver/tests/demo/run.log | 372144 +++++++++++++++ driver/tests/results.txt | 0 old_rtl/Makefile | 52 + old_rtl/VX_alu.v | 139 + old_rtl/VX_back_end.v | 133 + old_rtl/VX_countones.v | 22 + old_rtl/VX_csr_data.v | 82 + old_rtl/VX_csr_handler.v | 84 + old_rtl/VX_csr_pipe.v | 105 + old_rtl/VX_csr_wrapper.v | 38 + old_rtl/VX_decode.v | 361 + old_rtl/VX_define.v | 269 + old_rtl/VX_define_synth.v | 2 + old_rtl/VX_dmem_controller.v | 188 + old_rtl/VX_execute_unit.v | 168 + old_rtl/VX_fetch.v | 103 + old_rtl/VX_front_end.v | 89 + old_rtl/VX_generic_priority_encoder.v | 27 + old_rtl/VX_generic_register.v | 34 + old_rtl/VX_generic_stack.v | 38 + old_rtl/VX_gpgpu_inst.v | 85 + old_rtl/VX_gpr.v | 172 + old_rtl/VX_gpr_stage.v | 223 + old_rtl/VX_gpr_wrapper.v | 70 + old_rtl/VX_inst_multiplex.v | 95 + old_rtl/VX_lsu.v | 106 + old_rtl/VX_lsu_addr_gen.v | 17 + old_rtl/VX_priority_encoder.v | 20 + old_rtl/VX_priority_encoder_w_mask.v | 32 + old_rtl/VX_scheduler.v | 69 + old_rtl/VX_warp.v | 86 + old_rtl/VX_warp_scheduler.v | 321 + old_rtl/VX_writeback.v | 111 + old_rtl/Vortex.v | 249 + old_rtl/byte_enabled_simple_dual_port_ram.v | 53 + old_rtl/cache/Makefile | 12 + old_rtl/cache/Notes | 46 + old_rtl/cache/VX_Cache_Bank.v | 253 + old_rtl/cache/VX_cache_bank_valid.v | 30 + old_rtl/cache/VX_cache_data.v | 233 + old_rtl/cache/VX_cache_data_per_index.v | 163 + old_rtl/cache/VX_d_cache.v | 387 + old_rtl/cache/VX_d_cache_encapsulate.v | 118 + old_rtl/cache/VX_d_cache_tb.v | 58 + old_rtl/cache/VX_generic_pe.v | 24 + old_rtl/cache/cache_set.v | 233 + old_rtl/cache/d_cache_test_bench.cpp | 29 + old_rtl/cache/d_cache_test_bench.h | 355 + old_rtl/cache/d_cache_test_bench_debug.h | 1 + old_rtl/interfaces/VX_branch_response_inter.v | 18 + old_rtl/interfaces/VX_csr_req_inter.v | 24 + old_rtl/interfaces/VX_csr_wb_inter.v | 21 + old_rtl/interfaces/VX_dcache_request_inter.v | 19 + old_rtl/interfaces/VX_dcache_response_inter.v | 16 + old_rtl/interfaces/VX_dram_req_rsp_inter.v | 27 + old_rtl/interfaces/VX_exec_unit_req_inter.v | 51 + old_rtl/interfaces/VX_frE_to_bckE_req_inter.v | 46 + old_rtl/interfaces/VX_gpr_clone_inter.v | 18 + old_rtl/interfaces/VX_gpr_data_inter.v | 14 + old_rtl/interfaces/VX_gpr_jal_inter.v | 14 + old_rtl/interfaces/VX_gpr_read_inter.v | 17 + old_rtl/interfaces/VX_gpr_wspawn_inter.v | 18 + old_rtl/interfaces/VX_gpu_inst_req_inter.v | 27 + old_rtl/interfaces/VX_icache_request_inter.v | 19 + old_rtl/interfaces/VX_icache_response_inter.v | 18 + old_rtl/interfaces/VX_inst_exec_wb_inter.v | 21 + old_rtl/interfaces/VX_inst_mem_wb_inter.v | 21 + old_rtl/interfaces/VX_inst_meta_inter.v | 16 + old_rtl/interfaces/VX_jal_response_inter.v | 17 + old_rtl/interfaces/VX_join_inter.v | 17 + old_rtl/interfaces/VX_lsu_req_inter.v | 24 + old_rtl/interfaces/VX_mem_req_inter.v | 28 + old_rtl/interfaces/VX_mw_wb_inter.v | 22 + old_rtl/interfaces/VX_warp_ctl_inter.v | 36 + old_rtl/interfaces/VX_wb_inter.v | 21 + old_rtl/interfaces/VX_wstall_inter.v | 15 + old_rtl/modelsim/Makefile | 124 + old_rtl/modelsim/cshrc.modelsim | 8 + old_rtl/modelsim/modelsim.mpf | 2275 + old_rtl/modelsim/vortex_dpi.cpp | 328 + old_rtl/modelsim/vortex_dpi.h | 8 + old_rtl/modelsim/vortex_tb.v | 160 + old_rtl/modelsim/work/_info | 1084 + old_rtl/modelsim/work/_lib.qdb | Bin 0 -> 49152 bytes old_rtl/modelsim/work/_lib1_0.qdb | Bin 0 -> 32768 bytes old_rtl/modelsim/work/_lib1_0.qpg | Bin 0 -> 65536 bytes old_rtl/modelsim/work/_lib1_0.qtl | Bin 0 -> 158073 bytes old_rtl/modelsim/work/_vmake | 4 + old_rtl/pipe_regs/VX_d_e_reg.v | 36 + old_rtl/pipe_regs/VX_f_d_reg.v | 28 + old_rtl/quartus/Makefile | 70 + old_rtl/quartus/VX_gpr_syn.qpf | 30 + old_rtl/quartus/VX_gpr_syn.qsf | 63 + old_rtl/quartus/asm.chg | 1 + old_rtl/quartus/fit.chg | 1 + old_rtl/quartus/map.chg | 1 + old_rtl/quartus/project.tcl | 88 + old_rtl/quartus/smart.log | 27 + old_rtl/quartus/sta.chg | 1 + old_rtl/quartus/syn.chg | 1 + old_rtl/quartus/vortex.ini | 40 + old_rtl/quartus/vortex.sdc | 1 + old_rtl/results.txt | 7 + old_rtl/shared_memory/VX_bank_valids.v | 36 + .../shared_memory/VX_priority_encoder_sm.v | 115 + old_rtl/shared_memory/VX_shared_memory.v | 178 + .../shared_memory/VX_shared_memory_block.v | 115 + old_rtl/simulate/VX_define.h | 100 + old_rtl/simulate/ram.h | 245 + {rtl => old_rtl}/simulate/tb_debug.h | 0 old_rtl/simulate/test_bench.cpp | 105 + old_rtl/simulate/test_bench.h | 433 + rtl/simulate/Vortex.cpp | 315 + rtl/simulate/Vortex_SOC.cpp | 248 + runtime/qemu/vx_api.c | 27 + simX/out | 2 - simX/reading_data.txt | 1 - simX/results.txt | 1 - simX/test.sh | 143 - simX/test_runtime.sh | 17 + 267 files changed, 498191 insertions(+), 166 deletions(-) create mode 100755 benchmarks/new_opencl/bfs/CLHelper.h create mode 100644 benchmarks/new_opencl/bfs/Makefile create mode 100644 benchmarks/new_opencl/bfs/README create mode 100755 benchmarks/new_opencl/bfs/graph4096.txt create mode 100755 benchmarks/new_opencl/bfs/kernel.cl create mode 100644 benchmarks/new_opencl/bfs/kernel.pocl create mode 100755 benchmarks/new_opencl/bfs/main.cc create mode 100755 benchmarks/new_opencl/bfs/run create mode 100755 benchmarks/new_opencl/bfs/timer.cc create mode 100755 benchmarks/new_opencl/bfs/timer.h create mode 100755 benchmarks/new_opencl/bfs/util.h create mode 100644 benchmarks/new_opencl/guassian/Makefile create mode 100755 benchmarks/new_opencl/guassian/OriginalParallel.c create mode 100755 benchmarks/new_opencl/guassian/README.txt create mode 100755 benchmarks/new_opencl/guassian/clutils.cpp create mode 100755 benchmarks/new_opencl/guassian/clutils.h create mode 100755 benchmarks/new_opencl/guassian/gaussianElim.h create mode 100755 benchmarks/new_opencl/guassian/gettimeofday.cpp create mode 100755 benchmarks/new_opencl/guassian/gettimeofday.h create mode 100755 benchmarks/new_opencl/guassian/kernel.cl create mode 100644 benchmarks/new_opencl/guassian/kernel.pocl create mode 100755 benchmarks/new_opencl/guassian/main.cc create mode 100755 benchmarks/new_opencl/guassian/matrix4.txt create mode 100755 benchmarks/new_opencl/guassian/run create mode 100755 benchmarks/new_opencl/guassian/utils.cpp create mode 100755 benchmarks/new_opencl/guassian/utils.h create mode 100644 benchmarks/new_opencl/include/CL/cl.h create mode 100644 benchmarks/new_opencl/include/CL/cl.hpp create mode 100644 benchmarks/new_opencl/include/CL/cl2.hpp create mode 100644 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old_rtl/modelsim/work/_vmake create mode 100644 old_rtl/pipe_regs/VX_d_e_reg.v create mode 100644 old_rtl/pipe_regs/VX_f_d_reg.v create mode 100644 old_rtl/quartus/Makefile create mode 100644 old_rtl/quartus/VX_gpr_syn.qpf create mode 100644 old_rtl/quartus/VX_gpr_syn.qsf create mode 100644 old_rtl/quartus/asm.chg create mode 100644 old_rtl/quartus/fit.chg create mode 100644 old_rtl/quartus/map.chg create mode 100644 old_rtl/quartus/project.tcl create mode 100644 old_rtl/quartus/smart.log create mode 100644 old_rtl/quartus/sta.chg create mode 100644 old_rtl/quartus/syn.chg create mode 100644 old_rtl/quartus/vortex.ini create mode 100644 old_rtl/quartus/vortex.sdc create mode 100644 old_rtl/results.txt create mode 100644 old_rtl/shared_memory/VX_bank_valids.v create mode 100644 old_rtl/shared_memory/VX_priority_encoder_sm.v create mode 100644 old_rtl/shared_memory/VX_shared_memory.v create mode 100644 old_rtl/shared_memory/VX_shared_memory_block.v create mode 100644 old_rtl/simulate/VX_define.h create mode 100644 old_rtl/simulate/ram.h rename {rtl => old_rtl}/simulate/tb_debug.h (100%) create mode 100644 old_rtl/simulate/test_bench.cpp create mode 100644 old_rtl/simulate/test_bench.h create mode 100644 rtl/simulate/Vortex.cpp create mode 100644 rtl/simulate/Vortex_SOC.cpp create mode 100644 runtime/qemu/vx_api.c delete mode 100644 simX/out delete mode 100644 simX/reading_data.txt delete mode 100644 simX/results.txt delete mode 100644 simX/test.sh create mode 100755 simX/test_runtime.sh diff --git a/benchmarks/new_opencl/bfs/CLHelper.h b/benchmarks/new_opencl/bfs/CLHelper.h new file mode 100755 index 00000000..4ea9b747 --- /dev/null +++ b/benchmarks/new_opencl/bfs/CLHelper.h @@ -0,0 +1,848 @@ +//------------------------------------------ +//--cambine:helper function for OpenCL +//--programmer: Jianbin Fang +//--date: 27/12/2010 +//------------------------------------------ +#ifndef _CL_HELPER_ +#define _CL_HELPER_ + +#include +#include +#include +#include +#include + + +using std::string; +using std::ifstream; +using std::cerr; +using std::endl; +using std::cout; +//#pragma OPENCL EXTENSION cl_nv_compiler_options:enable +#define WORK_DIM 2 // work-items dimensions + +struct oclHandleStruct { + cl_context context; + cl_device_id *devices; + cl_command_queue queue; + cl_program program; + cl_int cl_status; + std::string error_str; + std::vector kernel; +}; + +struct oclHandleStruct oclHandles; + +char kernel_file[100] = "Kernels.cl"; +int total_kernels = 2; +string kernel_names[2] = {"BFS_1", "BFS_2"}; +int work_group_size = 512; +int device_id_inused = 0; // deviced id used (default : 0) + +int read_kernel_file(const char* filename, uint8_t** data, size_t* size) { + if (nullptr == filename || nullptr == data || 0 == size) + return -1; + + FILE* fp = fopen(filename, "r"); + if (NULL == fp) { + fprintf(stderr, "Failed to load kernel."); + return -1; + } + fseek(fp , 0 , SEEK_END); + long fsize = ftell(fp); + rewind(fp); + + *data = (uint8_t*)malloc(fsize); + *size = fread(*data, 1, fsize, fp); + + fclose(fp); + + return 0; +} + +/* + * Converts the contents of a file into a string + */ +string FileToString(const string fileName) { + ifstream f(fileName.c_str(), ifstream::in | ifstream::binary); + + try { + size_t size; + char *str; + string s; + + if (f.is_open()) { + size_t fileSize; + f.seekg(0, ifstream::end); + size = fileSize = f.tellg(); + f.seekg(0, ifstream::beg); + + str = new char[size + 1]; + if (!str) + throw(string("Could not allocate memory")); + + f.read(str, fileSize); + f.close(); + str[size] = '\0'; + + s = str; + delete[] str; + return s; + } + } catch (std::string msg) { + cerr << "Exception caught in FileToString(): " << msg << endl; + if (f.is_open()) + f.close(); + } catch (...) { + cerr << "Exception caught in FileToString()" << endl; + if (f.is_open()) + f.close(); + } + string errorMsg = "FileToString()::Error: Unable to open file " + fileName; + throw(errorMsg); +} +//--------------------------------------- +// Read command line parameters +// +void _clCmdParams(int argc, char *argv[]) { + for (int i = 0; i < argc; ++i) { + switch (argv[i][1]) { + case 'g': //--g stands for size of work group + if (++i < argc) { + sscanf(argv[i], "%u", &work_group_size); + } else { + std::cerr << "Could not read argument after option " << argv[i - 1] + << std::endl; + throw; + } + break; + case 'd': //--d stands for device id used in computaion + if (++i < argc) { + sscanf(argv[i], "%u", &device_id_inused); + } else { + std::cerr << "Could not read argument after option " << argv[i - 1] + << std::endl; + throw; + } + break; + default:; + } + } +} + +//--------------------------------------- +// Initlize CL objects +//--description: there are 5 steps to initialize all the OpenCL objects needed +//--revised on 04/01/2011: get the number of devices and +// devices have no relationship with context +void _clInit() { + printf("_clInit()\n"); + + int DEVICE_ID_INUSED = device_id_inused; + cl_int resultCL; + + oclHandles.context = NULL; + oclHandles.devices = NULL; + oclHandles.queue = NULL; + oclHandles.program = NULL; + + cl_uint deviceListSize; + + //----------------------------------------------- + //--cambine-1: find the available platforms and select one + + cl_uint numPlatforms = 1; + cl_platform_id targetPlatform = NULL; + + cl_platform_id *allPlatforms = + (cl_platform_id *)malloc(numPlatforms * sizeof(cl_platform_id)); + + resultCL = clGetPlatformIDs(numPlatforms, allPlatforms, NULL); + if (resultCL != CL_SUCCESS) + throw(string("InitCL()::Error: Getting platform ids (clGetPlatformIDs)")); + + // Select the target platform. Default: first platform + targetPlatform = allPlatforms[0]; + + /*for (int i = 0; i < numPlatforms; i++) +{ +char pbuff[128]; +resultCL = clGetPlatformInfo( allPlatforms[i], + CL_PLATFORM_VENDOR, + sizeof(pbuff), + pbuff, + NULL); +if (resultCL != CL_SUCCESS) +throw (string("InitCL()::Error: Getting platform info (clGetPlatformInfo)")); + + //printf("vedor is %s\n",pbuff); + +} +free(allPlatforms);*/ + + //----------------------------------------------- + //--cambine-2: create an OpenCL context + /*cl_context_properties cprops[3] = { CL_CONTEXT_PLATFORM, + (cl_context_properties)targetPlatform, 0 }; + oclHandles.context = clCreateContextFromType(cprops, + CL_DEVICE_TYPE_GPU, + NULL, + NULL, + &resultCL); + + if ((resultCL != CL_SUCCESS) || (oclHandles.context == NULL)) + throw (string("InitCL()::Error: Creating Context + (clCreateContextFromType)")); + + //----------------------------------------------- + //--cambine-3: detect OpenCL devices + // First, get the size of device list + oclHandles.cl_status = clGetDeviceIDs(targetPlatform, CL_DEVICE_TYPE_GPU, 0, + NULL, &deviceListSize); + if(oclHandles.cl_status!=CL_SUCCESS){ + throw(string("exception in _clInit -> clGetDeviceIDs")); + } + if (deviceListSize == 0) + throw(string("InitCL()::Error: No devices found.")); + + printf("OK1()\n"); + + //std::cout<<"device number:"< clGetDeviceIDs-2")); + } + + oclHandles.context = clCreateContext(NULL, deviceListSize, oclHandles.devices, + NULL, NULL, &resultCL); + if ((resultCL != CL_SUCCESS) || (oclHandles.context == NULL)) + throw(string("InitCL()::Error: Creating Context (clCreateContext)")); + + //----------------------------------------------- + //--cambine-4: Create an OpenCL command queue + oclHandles.queue = clCreateCommandQueue( + oclHandles.context, oclHandles.devices[DEVICE_ID_INUSED], 0, &resultCL); + printf("resultCL=%d, queue=0x%x\n", resultCL, oclHandles.queue); + + if ((resultCL != CL_SUCCESS) || (oclHandles.queue == NULL)) + throw(string("InitCL()::Creating Command Queue. (clCreateCommandQueue)")); + //----------------------------------------------- + //--cambine-5: Load CL file, build CL program object, create CL kernel object + /*std::string source_str = FileToString(kernel_file); + const char * source = source_str.c_str(); + size_t sourceSize[] = { source_str.length() };*/ + + //oclHandles.program = clCreateProgramWithBuiltInKernels( + // oclHandles.context, 1, &oclHandles.devices[DEVICE_ID_INUSED], + // "BFS_1;BFS_2", &resultCL); + /*oclHandles.program = clCreateProgramWithSource(oclHandles.context, + 1, + &source, + sourceSize, + &resultCL);*/ + // read kernel binary from file + uint8_t *kernel_bin = NULL; + size_t kernel_size; + cl_int binary_status = 0; + if (0 != read_kernel_file("kernel.pocl", &kernel_bin, &kernel_size)) + std::abort(); + + oclHandles.program = clCreateProgramWithBinary( + oclHandles.context, 1, &oclHandles.devices[DEVICE_ID_INUSED], &kernel_size, &kernel_bin, &binary_status, &resultCL); + free(kernel_bin); + + if ((resultCL != CL_SUCCESS) || (oclHandles.program == NULL)) + throw(string("InitCL()::Error: Loading Binary into cl_program. " + "(clCreateProgramWithBinary)")); + + // insert debug information + // std::string options= "-cl-nv-verbose"; //Doesn't work on AMD machines + // options += " -cl-nv-opt-level=3"; + resultCL = clBuildProgram(oclHandles.program, deviceListSize, + oclHandles.devices, NULL, NULL, NULL); + if ((resultCL != CL_SUCCESS) || (oclHandles.program == NULL)) { + cerr << "InitCL()::Error: In clBuildProgram" << endl; + + size_t length; + resultCL = clGetProgramBuildInfo(oclHandles.program, + oclHandles.devices[DEVICE_ID_INUSED], + CL_PROGRAM_BUILD_LOG, 0, NULL, &length); + if (resultCL != CL_SUCCESS) + throw(string("InitCL()::Error: Getting Program build " + "info(clGetProgramBuildInfo)")); + + char *buffer = (char *)malloc(length); + resultCL = clGetProgramBuildInfo( + oclHandles.program, oclHandles.devices[DEVICE_ID_INUSED], + CL_PROGRAM_BUILD_LOG, length, buffer, NULL); + if (resultCL != CL_SUCCESS) + throw(string("InitCL()::Error: Getting Program build " + "info(clGetProgramBuildInfo)")); + + cerr << buffer << endl; + free(buffer); + + throw(string("InitCL()::Error: Building Program (clBuildProgram)")); + } + +// get program information in intermediate representation +#ifdef PTX_MSG + size_t binary_sizes[deviceListSize]; + char *binaries[deviceListSize]; + // figure out number of devices and the sizes of the binary for each device. + oclHandles.cl_status = + clGetProgramInfo(oclHandles.program, CL_PROGRAM_BINARY_SIZES, + sizeof(size_t) * deviceListSize, &binary_sizes, NULL); + if (oclHandles.cl_status != CL_SUCCESS) { + throw(string("--cambine:exception in _InitCL -> clGetProgramInfo-2")); + } + + std::cout << "--cambine:" << binary_sizes << std::endl; + // copy over all of the generated binaries. + for (int i = 0; i < deviceListSize; i++) + binaries[i] = (char *)malloc(sizeof(char) * (binary_sizes[i] + 1)); + oclHandles.cl_status = + clGetProgramInfo(oclHandles.program, CL_PROGRAM_BINARIES, + sizeof(char *) * deviceListSize, binaries, NULL); + if (oclHandles.cl_status != CL_SUCCESS) { + throw(string("--cambine:exception in _InitCL -> clGetProgramInfo-3")); + } + for (int i = 0; i < deviceListSize; i++) + binaries[i][binary_sizes[i]] = '\0'; + std::cout << "--cambine:writing ptd information..." << std::endl; + FILE *ptx_file = fopen("cl.ptx", "w"); + if (ptx_file == NULL) { + throw(string("exceptions in allocate ptx file.")); + } + fprintf(ptx_file, "%s", binaries[DEVICE_ID_INUSED]); + fclose(ptx_file); + std::cout << "--cambine:writing ptd information done." << std::endl; + for (int i = 0; i < deviceListSize; i++) + free(binaries[i]); +#endif + + for (int nKernel = 0; nKernel < total_kernels; nKernel++) { + /* get a kernel object handle for a kernel with the given name */ + cl_kernel kernel = clCreateKernel( + oclHandles.program, (kernel_names[nKernel]).c_str(), &resultCL); + + if ((resultCL != CL_SUCCESS) || (kernel == NULL)) { + string errorMsg = "InitCL()::Error: Creating Kernel (clCreateKernel) \"" + + kernel_names[nKernel] + "\""; + throw(errorMsg); + } + + oclHandles.kernel.push_back(kernel); + } +// get resource alocation information +#ifdef RES_MSG + char *build_log; + size_t ret_val_size; + oclHandles.cl_status = clGetProgramBuildInfo( + oclHandles.program, oclHandles.devices[DEVICE_ID_INUSED], + CL_PROGRAM_BUILD_LOG, 0, NULL, &ret_val_size); + if (oclHandles.cl_status != CL_SUCCESS) { + throw(string("exceptions in _InitCL -> getting resource information")); + } + + build_log = (char *)malloc(ret_val_size + 1); + oclHandles.cl_status = clGetProgramBuildInfo( + oclHandles.program, oclHandles.devices[DEVICE_ID_INUSED], + CL_PROGRAM_BUILD_LOG, ret_val_size, build_log, NULL); + if (oclHandles.cl_status != CL_SUCCESS) { + throw(string( + "exceptions in _InitCL -> getting resources allocation information-2")); + } + build_log[ret_val_size] = '\0'; + std::cout << "--cambine:" << build_log << std::endl; + free(build_log); +#endif +} + +//--------------------------------------- +// release CL objects +void _clRelease() { + char errorFlag = false; + + for (int nKernel = 0; nKernel < oclHandles.kernel.size(); nKernel++) { + if (oclHandles.kernel[nKernel] != NULL) { + cl_int resultCL = clReleaseKernel(oclHandles.kernel[nKernel]); + if (resultCL != CL_SUCCESS) { + cerr << "ReleaseCL()::Error: In clReleaseKernel" << endl; + errorFlag = true; + } + oclHandles.kernel[nKernel] = NULL; + } + oclHandles.kernel.clear(); + } + + if (oclHandles.program != NULL) { + cl_int resultCL = clReleaseProgram(oclHandles.program); + if (resultCL != CL_SUCCESS) { + cerr << "ReleaseCL()::Error: In clReleaseProgram" << endl; + errorFlag = true; + } + oclHandles.program = NULL; + } + + if (oclHandles.queue != NULL) { + cl_int resultCL = clReleaseCommandQueue(oclHandles.queue); + if (resultCL != CL_SUCCESS) { + cerr << "ReleaseCL()::Error: In clReleaseCommandQueue" << endl; + errorFlag = true; + } + oclHandles.queue = NULL; + } + + free(oclHandles.devices); + + if (oclHandles.context != NULL) { + cl_int resultCL = clReleaseContext(oclHandles.context); + if (resultCL != CL_SUCCESS) { + cerr << "ReleaseCL()::Error: In clReleaseContext" << endl; + errorFlag = true; + } + oclHandles.context = NULL; + } + + if (errorFlag) + throw(string("ReleaseCL()::Error encountered.")); +} +//-------------------------------------------------------- +//--cambine:create buffer and then copy data from host to device +cl_mem _clCreateAndCpyMem(int size, void *h_mem_source) throw(string) { + cl_mem d_mem; + d_mem = clCreateBuffer(oclHandles.context, + CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR, size, + h_mem_source, &oclHandles.cl_status); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clCreateAndCpyMem()")); +#endif + return d_mem; +} +//------------------------------------------------------- +//--cambine: create read only buffer for devices +//--date: 17/01/2011 +cl_mem _clMallocRW(int size, void *h_mem_ptr) throw(string) { + cl_mem d_mem; + d_mem = clCreateBuffer(oclHandles.context, + CL_MEM_READ_WRITE | CL_MEM_COPY_HOST_PTR, size, + h_mem_ptr, &oclHandles.cl_status); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clMallocRW")); +#endif + return d_mem; +} +//------------------------------------------------------- +//--cambine: create read and write buffer for devices +//--date: 17/01/2011 +cl_mem _clMalloc(int size, void *h_mem_ptr) throw(string) { + cl_mem d_mem; + d_mem = clCreateBuffer(oclHandles.context, + CL_MEM_WRITE_ONLY | CL_MEM_COPY_HOST_PTR, size, + h_mem_ptr, &oclHandles.cl_status); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clMalloc")); +#endif + return d_mem; +} + +//------------------------------------------------------- +//--cambine: transfer data from host to device +//--date: 17/01/2011 +void _clMemcpyH2D(cl_mem d_mem, int size, const void *h_mem_ptr) throw(string) { + oclHandles.cl_status = clEnqueueWriteBuffer( + oclHandles.queue, d_mem, CL_TRUE, 0, size, h_mem_ptr, 0, NULL, NULL); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clMemcpyH2D")); +#endif +} +//-------------------------------------------------------- +//--cambine:create buffer and then copy data from host to device with pinned +// memory +cl_mem _clCreateAndCpyPinnedMem(int size, float *h_mem_source) throw(string) { + cl_mem d_mem, d_mem_pinned; + float *h_mem_pinned = NULL; + d_mem_pinned = clCreateBuffer(oclHandles.context, + CL_MEM_READ_ONLY | CL_MEM_ALLOC_HOST_PTR, size, + NULL, &oclHandles.cl_status); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clCreateAndCpyMem()->d_mem_pinned")); +#endif + //------------ + d_mem = clCreateBuffer(oclHandles.context, CL_MEM_READ_ONLY, size, NULL, + &oclHandles.cl_status); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clCreateAndCpyMem() -> d_mem ")); +#endif + //---------- + h_mem_pinned = (cl_float *)clEnqueueMapBuffer( + oclHandles.queue, d_mem_pinned, CL_TRUE, CL_MAP_WRITE, 0, size, 0, NULL, + NULL, &oclHandles.cl_status); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clCreateAndCpyMem() -> clEnqueueMapBuffer")); +#endif + int element_number = size / sizeof(float); +#pragma omp parallel for + for (int i = 0; i < element_number; i++) { + h_mem_pinned[i] = h_mem_source[i]; + } + //---------- + oclHandles.cl_status = clEnqueueWriteBuffer( + oclHandles.queue, d_mem, CL_TRUE, 0, size, h_mem_pinned, 0, NULL, NULL); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clCreateAndCpyMem() -> clEnqueueWriteBuffer")); +#endif + + return d_mem; +} + +//-------------------------------------------------------- +//--cambine:create write only buffer on device +cl_mem _clMallocWO(int size) throw(string) { + cl_mem d_mem; + d_mem = clCreateBuffer(oclHandles.context, CL_MEM_WRITE_ONLY, size, 0, + &oclHandles.cl_status); +#ifdef ERRMSG + if (oclHandles.cl_status != CL_SUCCESS) + throw(string("excpetion in _clCreateMem()")); +#endif + return d_mem; +} + +//-------------------------------------------------------- +// transfer data from device to host +void _clMemcpyD2H(cl_mem d_mem, int size, void *h_mem) throw(string) { + oclHandles.cl_status = clEnqueueReadBuffer(oclHandles.queue, d_mem, CL_TRUE, + 0, size, h_mem, 0, 0, 0); +#ifdef ERRMSG + oclHandles.error_str = "excpetion in _clCpyMemD2H -> "; + switch (oclHandles.cl_status) { + case CL_INVALID_COMMAND_QUEUE: + oclHandles.error_str += "CL_INVALID_COMMAND_QUEUE"; + break; + case CL_INVALID_CONTEXT: + oclHandles.error_str += "CL_INVALID_CONTEXT"; + break; + case CL_INVALID_MEM_OBJECT: + oclHandles.error_str += "CL_INVALID_MEM_OBJECT"; + break; + case CL_INVALID_VALUE: + oclHandles.error_str += "CL_INVALID_VALUE"; + break; + case CL_INVALID_EVENT_WAIT_LIST: + oclHandles.error_str += "CL_INVALID_EVENT_WAIT_LIST"; + break; + case CL_MEM_OBJECT_ALLOCATION_FAILURE: + oclHandles.error_str += "CL_MEM_OBJECT_ALLOCATION_FAILURE"; + break; + case CL_OUT_OF_HOST_MEMORY: + oclHandles.error_str += "CL_OUT_OF_HOST_MEMORY"; + break; + default: + oclHandles.error_str += "Unknown reason"; + break; + } + if (oclHandles.cl_status != CL_SUCCESS) + throw(oclHandles.error_str); +#endif +} + +//-------------------------------------------------------- +// set kernel arguments +void _clSetArgs(int kernel_id, int arg_idx, void *d_mem, + int size = 0) throw(string) { + if (!size) { + oclHandles.cl_status = clSetKernelArg(oclHandles.kernel[kernel_id], arg_idx, + sizeof(d_mem), &d_mem); +#ifdef ERRMSG + oclHandles.error_str = "excpetion in _clSetKernelArg() "; + switch (oclHandles.cl_status) { + case CL_INVALID_KERNEL: + oclHandles.error_str += "CL_INVALID_KERNEL"; + break; + case CL_INVALID_ARG_INDEX: + oclHandles.error_str += "CL_INVALID_ARG_INDEX"; + break; + case CL_INVALID_ARG_VALUE: + oclHandles.error_str += "CL_INVALID_ARG_VALUE"; + break; + case CL_INVALID_MEM_OBJECT: + oclHandles.error_str += "CL_INVALID_MEM_OBJECT"; + break; + case CL_INVALID_SAMPLER: + oclHandles.error_str += "CL_INVALID_SAMPLER"; + break; + case CL_INVALID_ARG_SIZE: + oclHandles.error_str += "CL_INVALID_ARG_SIZE"; + break; + case CL_OUT_OF_RESOURCES: + oclHandles.error_str += "CL_OUT_OF_RESOURCES"; + break; + case CL_OUT_OF_HOST_MEMORY: + oclHandles.error_str += "CL_OUT_OF_HOST_MEMORY"; + break; + default: + oclHandles.error_str += "Unknown reason"; + break; + } + if (oclHandles.cl_status != CL_SUCCESS) + throw(oclHandles.error_str); +#endif + } else { + oclHandles.cl_status = + clSetKernelArg(oclHandles.kernel[kernel_id], arg_idx, size, d_mem); +#ifdef ERRMSG + oclHandles.error_str = "excpetion in _clSetKernelArg() "; + switch (oclHandles.cl_status) { + case CL_INVALID_KERNEL: + oclHandles.error_str += "CL_INVALID_KERNEL"; + break; + case CL_INVALID_ARG_INDEX: + oclHandles.error_str += "CL_INVALID_ARG_INDEX"; + break; + case CL_INVALID_ARG_VALUE: + oclHandles.error_str += "CL_INVALID_ARG_VALUE"; + break; + case CL_INVALID_MEM_OBJECT: + oclHandles.error_str += "CL_INVALID_MEM_OBJECT"; + break; + case CL_INVALID_SAMPLER: + oclHandles.error_str += "CL_INVALID_SAMPLER"; + break; + case CL_INVALID_ARG_SIZE: + oclHandles.error_str += "CL_INVALID_ARG_SIZE"; + break; + case CL_OUT_OF_RESOURCES: + oclHandles.error_str += "CL_OUT_OF_RESOURCES"; + break; + case CL_OUT_OF_HOST_MEMORY: + oclHandles.error_str += "CL_OUT_OF_HOST_MEMORY"; + break; + default: + oclHandles.error_str += "Unknown reason"; + break; + } + if (oclHandles.cl_status != CL_SUCCESS) + throw(oclHandles.error_str); +#endif + } +} +void _clFinish() throw(string) { + oclHandles.cl_status = clFinish(oclHandles.queue); +#ifdef ERRMSG + oclHandles.error_str = "excpetion in _clFinish"; + switch (oclHandles.cl_status) { + case CL_INVALID_COMMAND_QUEUE: + oclHandles.error_str += "CL_INVALID_COMMAND_QUEUE"; + break; + case CL_OUT_OF_RESOURCES: + oclHandles.error_str += "CL_OUT_OF_RESOURCES"; + break; + case CL_OUT_OF_HOST_MEMORY: + oclHandles.error_str += "CL_OUT_OF_HOST_MEMORY"; + break; + default: + oclHandles.error_str += "Unknown reasons"; + break; + } + if (oclHandles.cl_status != CL_SUCCESS) { + throw(oclHandles.error_str); + } +#endif +} +//-------------------------------------------------------- +//--cambine:enqueue kernel +void _clInvokeKernel(int kernel_id, int work_items, + int work_group_size) throw(string) { + cl_uint work_dim = WORK_DIM; + cl_event e[1]; + if (work_items % work_group_size != 0) // process situations that work_items + // cannot be divided by work_group_size + work_items = + work_items + (work_group_size - (work_items % work_group_size)); + size_t local_work_size[] = {work_group_size, 1}; + size_t global_work_size[] = {work_items, 1}; + oclHandles.cl_status = clEnqueueNDRangeKernel( + oclHandles.queue, oclHandles.kernel[kernel_id], work_dim, 0, + global_work_size, local_work_size, 0, 0, &(e[0])); +#ifdef ERRMSG + oclHandles.error_str = "excpetion in _clInvokeKernel() -> "; + switch (oclHandles.cl_status) { + case CL_INVALID_PROGRAM_EXECUTABLE: + oclHandles.error_str += "CL_INVALID_PROGRAM_EXECUTABLE"; + break; + case CL_INVALID_COMMAND_QUEUE: + oclHandles.error_str += "CL_INVALID_COMMAND_QUEUE"; + break; + case CL_INVALID_KERNEL: + oclHandles.error_str += "CL_INVALID_KERNEL"; + break; + case CL_INVALID_CONTEXT: + oclHandles.error_str += "CL_INVALID_CONTEXT"; + break; + case CL_INVALID_KERNEL_ARGS: + oclHandles.error_str += "CL_INVALID_KERNEL_ARGS"; + break; + case CL_INVALID_WORK_DIMENSION: + oclHandles.error_str += "CL_INVALID_WORK_DIMENSION"; + break; + case CL_INVALID_GLOBAL_WORK_SIZE: + oclHandles.error_str += "CL_INVALID_GLOBAL_WORK_SIZE"; + break; + case CL_INVALID_WORK_GROUP_SIZE: + oclHandles.error_str += "CL_INVALID_WORK_GROUP_SIZE"; + break; + case CL_INVALID_WORK_ITEM_SIZE: + oclHandles.error_str += "CL_INVALID_WORK_ITEM_SIZE"; + break; + case CL_INVALID_GLOBAL_OFFSET: + oclHandles.error_str += "CL_INVALID_GLOBAL_OFFSET"; + break; + case CL_OUT_OF_RESOURCES: + oclHandles.error_str += "CL_OUT_OF_RESOURCES"; + break; + case CL_MEM_OBJECT_ALLOCATION_FAILURE: + oclHandles.error_str += "CL_MEM_OBJECT_ALLOCATION_FAILURE"; + break; + case CL_INVALID_EVENT_WAIT_LIST: + oclHandles.error_str += "CL_INVALID_EVENT_WAIT_LIST"; + break; + case CL_OUT_OF_HOST_MEMORY: + oclHandles.error_str += "CL_OUT_OF_HOST_MEMORY"; + break; + default: + oclHandles.error_str += "Unkown reseason"; + break; + } + if (oclHandles.cl_status != CL_SUCCESS) + throw(oclHandles.error_str); +#endif + //_clFinish(); + // oclHandles.cl_status = clWaitForEvents(1, &e[0]); + // #ifdef ERRMSG + // if (oclHandles.cl_status!= CL_SUCCESS) + // throw(string("excpetion in _clEnqueueNDRange() -> clWaitForEvents")); + // #endif +} +void _clInvokeKernel2D(int kernel_id, int range_x, int range_y, int group_x, + int group_y) throw(string) { + cl_uint work_dim = WORK_DIM; + size_t local_work_size[] = {group_x, group_y}; + size_t global_work_size[] = {range_x, range_y}; + cl_event e[1]; + /*if(work_items%work_group_size != 0) //process situations that work_items + cannot be divided by work_group_size + work_items = work_items + (work_group_size-(work_items%work_group_size));*/ + oclHandles.cl_status = clEnqueueNDRangeKernel( + oclHandles.queue, oclHandles.kernel[kernel_id], work_dim, 0, + global_work_size, local_work_size, 0, 0, &(e[0])); +#ifdef ERRMSG + oclHandles.error_str = "excpetion in _clInvokeKernel() -> "; + switch (oclHandles.cl_status) { + case CL_INVALID_PROGRAM_EXECUTABLE: + oclHandles.error_str += "CL_INVALID_PROGRAM_EXECUTABLE"; + break; + case CL_INVALID_COMMAND_QUEUE: + oclHandles.error_str += "CL_INVALID_COMMAND_QUEUE"; + break; + case CL_INVALID_KERNEL: + oclHandles.error_str += "CL_INVALID_KERNEL"; + break; + case CL_INVALID_CONTEXT: + oclHandles.error_str += "CL_INVALID_CONTEXT"; + break; + case CL_INVALID_KERNEL_ARGS: + oclHandles.error_str += "CL_INVALID_KERNEL_ARGS"; + break; + case CL_INVALID_WORK_DIMENSION: + oclHandles.error_str += "CL_INVALID_WORK_DIMENSION"; + break; + case CL_INVALID_GLOBAL_WORK_SIZE: + oclHandles.error_str += "CL_INVALID_GLOBAL_WORK_SIZE"; + break; + case CL_INVALID_WORK_GROUP_SIZE: + oclHandles.error_str += "CL_INVALID_WORK_GROUP_SIZE"; + break; + case CL_INVALID_WORK_ITEM_SIZE: + oclHandles.error_str += "CL_INVALID_WORK_ITEM_SIZE"; + break; + case CL_INVALID_GLOBAL_OFFSET: + oclHandles.error_str += "CL_INVALID_GLOBAL_OFFSET"; + break; + case CL_OUT_OF_RESOURCES: + oclHandles.error_str += "CL_OUT_OF_RESOURCES"; + break; + case CL_MEM_OBJECT_ALLOCATION_FAILURE: + oclHandles.error_str += "CL_MEM_OBJECT_ALLOCATION_FAILURE"; + break; + case CL_INVALID_EVENT_WAIT_LIST: + oclHandles.error_str += "CL_INVALID_EVENT_WAIT_LIST"; + break; + case CL_OUT_OF_HOST_MEMORY: + oclHandles.error_str += "CL_OUT_OF_HOST_MEMORY"; + break; + default: + oclHandles.error_str += "Unkown reseason"; + break; + } + if (oclHandles.cl_status != CL_SUCCESS) + throw(oclHandles.error_str); +#endif + //_clFinish(); + /*oclHandles.cl_status = clWaitForEvents(1, &e[0]); + + #ifdef ERRMSG + + if (oclHandles.cl_status!= CL_SUCCESS) + + throw(string("excpetion in _clEnqueueNDRange() -> clWaitForEvents")); + + #endif*/ +} + +//-------------------------------------------------------- +// release OpenCL objects +void _clFree(cl_mem ob) throw(string) { + if (ob != NULL) + oclHandles.cl_status = clReleaseMemObject(ob); +#ifdef ERRMSG + oclHandles.error_str = "excpetion in _clFree() ->"; + switch (oclHandles.cl_status) { + case CL_INVALID_MEM_OBJECT: + oclHandles.error_str += "CL_INVALID_MEM_OBJECT"; + break; + case CL_OUT_OF_RESOURCES: + oclHandles.error_str += "CL_OUT_OF_RESOURCES"; + break; + case CL_OUT_OF_HOST_MEMORY: + oclHandles.error_str += "CL_OUT_OF_HOST_MEMORY"; + break; + default: + oclHandles.error_str += "Unkown reseason"; + break; + } + if (oclHandles.cl_status != CL_SUCCESS) + throw(oclHandles.error_str); +#endif +} +#endif //_CL_HELPER_ diff --git a/benchmarks/new_opencl/bfs/Makefile b/benchmarks/new_opencl/bfs/Makefile new file mode 100644 index 00000000..6c877d51 --- /dev/null +++ b/benchmarks/new_opencl/bfs/Makefile @@ -0,0 +1,44 @@ +RISCV_TOOL_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) +POCLCC_PATH ?= $(wildcard ~/dev/pocl/drops_vortex_cc) +POCLRT_PATH ?= $(wildcard ..) +DRIVER_PATH ?= $(wildcard ../../../driver/sw) + +CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I$(POCLRT_PATH)/include + +LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex + +PROJECT = bfs + +SRCS = main.cc + +all: $(PROJECT) + +kernel.pocl: kernel.cl + POCL_DEBUG=all POCL_DEBUG_LLVM_PASSES=1 LD_LIBRARY_PATH=$(RISCV_TOOL_PATH)/lib:$(POCLCC_PATH)/lib:$(DRIVER_PATH)/simx $(POCLCC_PATH)/bin/poclcc -o kernel.pocl kernel.cl + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +run-fpga: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-ase: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-simx: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-rtlsim: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/benchmarks/new_opencl/bfs/README b/benchmarks/new_opencl/bfs/README new file mode 100644 index 00000000..e69de29b diff --git a/benchmarks/new_opencl/bfs/graph4096.txt b/benchmarks/new_opencl/bfs/graph4096.txt new file mode 100755 index 00000000..56743261 --- /dev/null +++ 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+3328 9 +2147 9 +2813 2 +1841 3 +3458 9 +777 5 +3564 2 diff --git a/benchmarks/new_opencl/bfs/kernel.cl b/benchmarks/new_opencl/bfs/kernel.cl new file mode 100755 index 00000000..51ce5a08 --- /dev/null +++ b/benchmarks/new_opencl/bfs/kernel.cl @@ -0,0 +1,53 @@ +/* ============================================================ +//--cambine: kernel funtion of Breadth-First-Search +//--author: created by Jianbin Fang +//--date: 06/12/2010 +============================================================ */ + +//#pragma OPENCL EXTENSION cl_khr_byte_addressable_store: enable + +//Structure to hold a node information +typedef struct{ + int starting; + int no_of_edges; +} Node; + +//--7 parameters +__kernel void BFS_1( const __global Node* g_graph_nodes, + const __global int* g_graph_edges, + __global char* g_graph_mask, + __global char* g_updating_graph_mask, + __global char* g_graph_visited, + __global int* g_cost, + const int no_of_nodes){ + int tid = get_global_id(0); + if( tidlNCIL|bo>ZY%vU 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ze?6J}Rp#5rrF0!1m9MSViUz*iUFS!=E6)y{_wF>lm-{ilZF1dv=RaPa)E_&q%q+^1 zd%gYp?S386TCL~^_qOpn{Y>hQaxdDW&UyZ|-2b?-7#W*&=X`r1;?U<~%x&$~JMNhI zBl#H{GVG2av01myoi}sF=VPps9@}zHFJB@r4Y2k6L zXz1U(G^fY4+ z7Vy2?pW(MnuKTwAHkN9Pz>t04*<=$~07JuECiK_vLp%k0ke_`CbZ=Zyn~P ziUPeT{adc(zWn|zc{<5`O%DVN{?elnI`1$1F@KSN@-O;-_^-E*G{#T9sp3Q#-jNZLXK1$AC6~0`Pn*dlJ?E#b1ANRcHr|0{tOuoAJ48~8>ZYTAYYpGt-0^0uzJm%KR literal 0 HcmV?d00001 diff --git a/benchmarks/new_opencl/bfs/main.cc b/benchmarks/new_opencl/bfs/main.cc new file mode 100755 index 00000000..138ec864 --- /dev/null +++ b/benchmarks/new_opencl/bfs/main.cc @@ -0,0 +1,297 @@ +//--by Jianbin Fang + +#include +#include +#include +#include +#include +#include +#include + +#ifdef PROFILING +#include "timer.h" +#endif + +#include "CLHelper.h" +#include "util.h" + +#define MAX_THREADS_PER_BLOCK 256 + +// Structure to hold a node information +struct Node { + int starting; + int no_of_edges; +}; + +//---------------------------------------------------------- +//--bfs on cpu +//--programmer: jianbin +//--date: 26/01/2011 +//--note: width is changed to the new_width +//---------------------------------------------------------- +void run_bfs_cpu(int no_of_nodes, Node *h_graph_nodes, int edge_list_size, + int *h_graph_edges, char *h_graph_mask, + char *h_updating_graph_mask, char *h_graph_visited, + int *h_cost_ref) { + char stop; + int k = 0; + do { + // if no thread changes this value then the loop stops + stop = false; + for (int tid = 0; tid < no_of_nodes; tid++) { + if (h_graph_mask[tid] == true) { + h_graph_mask[tid] = false; + for (int i = h_graph_nodes[tid].starting; + i < (h_graph_nodes[tid].no_of_edges + h_graph_nodes[tid].starting); + i++) { + int id = + h_graph_edges[i]; //--cambine: node id is connected with node tid + if (!h_graph_visited[id]) { //--cambine: if node id has not been + //visited, enter the body below + h_cost_ref[id] = h_cost_ref[tid] + 1; + h_updating_graph_mask[id] = true; + } + } + } + } + + for (int tid = 0; tid < no_of_nodes; tid++) { + if (h_updating_graph_mask[tid] == true) { + h_graph_mask[tid] = true; + h_graph_visited[tid] = true; + stop = true; + h_updating_graph_mask[tid] = false; + } + } + k++; + } while (stop); +} +//---------------------------------------------------------- +//--breadth first search on GPUs +//---------------------------------------------------------- +void run_bfs_gpu(int no_of_nodes, Node *h_graph_nodes, int edge_list_size, + int *h_graph_edges, char *h_graph_mask, + char *h_updating_graph_mask, char *h_graph_visited, + int *h_cost) throw(std::string) { + + // int number_elements = height*width; + char h_over; + cl_mem d_graph_nodes, d_graph_edges, d_graph_mask, d_updating_graph_mask, + d_graph_visited, d_cost, d_over; + try { + //--1 transfer data from host to device + _clInit(); + d_graph_nodes = _clMalloc(no_of_nodes * sizeof(Node), h_graph_nodes); + d_graph_edges = _clMalloc(edge_list_size * sizeof(int), h_graph_edges); + d_graph_mask = _clMallocRW(no_of_nodes * sizeof(char), h_graph_mask); + d_updating_graph_mask = + _clMallocRW(no_of_nodes * sizeof(char), h_updating_graph_mask); + d_graph_visited = _clMallocRW(no_of_nodes * sizeof(char), h_graph_visited); + + d_cost = _clMallocRW(no_of_nodes * sizeof(int), h_cost); + d_over = _clMallocRW(sizeof(char), &h_over); + + _clMemcpyH2D(d_graph_nodes, no_of_nodes * sizeof(Node), h_graph_nodes); + _clMemcpyH2D(d_graph_edges, edge_list_size * sizeof(int), h_graph_edges); + _clMemcpyH2D(d_graph_mask, no_of_nodes * sizeof(char), h_graph_mask); + _clMemcpyH2D(d_updating_graph_mask, no_of_nodes * sizeof(char), + h_updating_graph_mask); + _clMemcpyH2D(d_graph_visited, no_of_nodes * sizeof(char), h_graph_visited); + _clMemcpyH2D(d_cost, no_of_nodes * sizeof(int), h_cost); + +//--2 invoke kernel +#ifdef PROFILING + timer kernel_timer; + double kernel_time = 0.0; + kernel_timer.reset(); + kernel_timer.start(); +#endif + do { + h_over = false; + _clMemcpyH2D(d_over, sizeof(char), &h_over); + //--kernel 0 + int kernel_id = 0; + int kernel_idx = 0; + _clSetArgs(kernel_id, kernel_idx++, d_graph_nodes); + _clSetArgs(kernel_id, kernel_idx++, d_graph_edges); + _clSetArgs(kernel_id, kernel_idx++, d_graph_mask); + _clSetArgs(kernel_id, kernel_idx++, d_updating_graph_mask); + _clSetArgs(kernel_id, kernel_idx++, d_graph_visited); + _clSetArgs(kernel_id, kernel_idx++, d_cost); + _clSetArgs(kernel_id, kernel_idx++, &no_of_nodes, sizeof(int)); + + // int work_items = no_of_nodes; + _clInvokeKernel(kernel_id, no_of_nodes, work_group_size); + + //--kernel 1 + kernel_id = 1; + kernel_idx = 0; + _clSetArgs(kernel_id, kernel_idx++, d_graph_mask); + _clSetArgs(kernel_id, kernel_idx++, d_updating_graph_mask); + _clSetArgs(kernel_id, kernel_idx++, d_graph_visited); + _clSetArgs(kernel_id, kernel_idx++, d_over); + _clSetArgs(kernel_id, kernel_idx++, &no_of_nodes, sizeof(int)); + + // work_items = no_of_nodes; + _clInvokeKernel(kernel_id, no_of_nodes, work_group_size); + + _clMemcpyD2H(d_over, sizeof(char), &h_over); + } while (h_over); + + _clFinish(); +#ifdef PROFILING + kernel_timer.stop(); + kernel_time = kernel_timer.getTimeInSeconds(); +#endif + //--3 transfer data from device to host + _clMemcpyD2H(d_cost, no_of_nodes * sizeof(int), h_cost); +//--statistics +#ifdef PROFILING + std::cout << "kernel time(s):" << kernel_time << std::endl; +#endif + //--4 release cl resources. + _clFree(d_graph_nodes); + _clFree(d_graph_edges); + _clFree(d_graph_mask); + _clFree(d_updating_graph_mask); + _clFree(d_graph_visited); + _clFree(d_cost); + _clFree(d_over); + _clRelease(); + } catch (std::string msg) { + _clFree(d_graph_nodes); + _clFree(d_graph_edges); + _clFree(d_graph_mask); + _clFree(d_updating_graph_mask); + _clFree(d_graph_visited); + _clFree(d_cost); + _clFree(d_over); + _clRelease(); + std::string e_str = "in run_transpose_gpu -> "; + e_str += msg; + throw(e_str); + } + return; +} + +//---------------------------------------------------------- +//--cambine: main function +//--author: created by Jianbin Fang +//--date: 25/01/2011 +//---------------------------------------------------------- +int main(int argc, char *argv[]) { + printf("enter demo main\n"); + + int no_of_nodes; + int edge_list_size; + FILE *fp; + Node *h_graph_nodes; + char *h_graph_mask, *h_updating_graph_mask, *h_graph_visited; + + try { + char *input_f = "graph4096.txt"; + printf("Reading File\n"); + // Read in Graph from a file + fp = fopen(input_f, "r"); + if (!fp) { + printf("Error Reading graph file\n"); + return 0; + } + + printf("Reading File completed!\n"); + + int source = 0; + + fscanf(fp, "%d", &no_of_nodes); + + int num_of_blocks = 1; + int num_of_threads_per_block = no_of_nodes; + + // Make execution Parameters according to the number of nodes + // Distribute threads across multiple Blocks if necessary + if (no_of_nodes > MAX_THREADS_PER_BLOCK) { + num_of_blocks = (int)ceil(no_of_nodes / (double)MAX_THREADS_PER_BLOCK); + num_of_threads_per_block = MAX_THREADS_PER_BLOCK; + } + work_group_size = num_of_threads_per_block; + // allocate host memory + h_graph_nodes = (Node *)malloc(sizeof(Node) * no_of_nodes); + h_graph_mask = (char *)malloc(sizeof(char) * no_of_nodes); + h_updating_graph_mask = (char *)malloc(sizeof(char) * no_of_nodes); + h_graph_visited = (char *)malloc(sizeof(char) * no_of_nodes); + + int start, edgeno; + // initalize the memory + for (int i = 0; i < no_of_nodes; i++) { + fscanf(fp, "%d %d", &start, &edgeno); + h_graph_nodes[i].starting = start; + h_graph_nodes[i].no_of_edges = edgeno; + h_graph_mask[i] = false; + h_updating_graph_mask[i] = false; + h_graph_visited[i] = false; + } + // read the source node from the file + fscanf(fp, "%d", &source); + source = 0; + // set the source node as true in the mask + h_graph_mask[source] = true; + h_graph_visited[source] = true; + fscanf(fp, "%d", &edge_list_size); + int id, cost; + int *h_graph_edges = (int *)malloc(sizeof(int) * edge_list_size); + for (int i = 0; i < edge_list_size; i++) { + fscanf(fp, "%d", &id); + fscanf(fp, "%d", &cost); + h_graph_edges[i] = id; + } + + if (fp) + fclose(fp); + // allocate mem for the result on host side + int *h_cost = (int *)malloc(sizeof(int) * no_of_nodes); + int *h_cost_ref = (int *)malloc(sizeof(int) * no_of_nodes); + for (int i = 0; i < no_of_nodes; i++) { + h_cost[i] = -1; + h_cost_ref[i] = -1; + } + h_cost[source] = 0; + h_cost_ref[source] = 0; + //--------------------------------------------------------- + //--gpu entry + run_bfs_gpu(no_of_nodes, h_graph_nodes, edge_list_size, h_graph_edges, + h_graph_mask, h_updating_graph_mask, h_graph_visited, h_cost); + //--------------------------------------------------------- + //--cpu entry + // initalize the memory again + for (int i = 0; i < no_of_nodes; i++) { + h_graph_mask[i] = false; + h_updating_graph_mask[i] = false; + h_graph_visited[i] = false; + } + // set the source node as true in the mask + source = 0; + h_graph_mask[source] = true; + h_graph_visited[source] = true; + run_bfs_cpu(no_of_nodes, h_graph_nodes, edge_list_size, h_graph_edges, + h_graph_mask, h_updating_graph_mask, h_graph_visited, + h_cost_ref); + //--------------------------------------------------------- + //--result varification + compare_results(h_cost_ref, h_cost, no_of_nodes); + // release host memory + free(h_graph_nodes); + free(h_graph_mask); + free(h_updating_graph_mask); + free(h_graph_visited); + + } catch (std::string msg) { + std::cout << "--cambine: exception in main ->" << msg << std::endl; + // release host memory + free(h_graph_nodes); + free(h_graph_mask); + free(h_updating_graph_mask); + free(h_graph_visited); + } + + return 0; +} diff --git a/benchmarks/new_opencl/bfs/run b/benchmarks/new_opencl/bfs/run new file mode 100755 index 00000000..7fa690ed --- /dev/null +++ b/benchmarks/new_opencl/bfs/run @@ -0,0 +1 @@ +./bfs ../../data/bfs/graph1MW_6.txt \ No newline at end of file diff --git a/benchmarks/new_opencl/bfs/timer.cc b/benchmarks/new_opencl/bfs/timer.cc new file mode 100755 index 00000000..3e907f4c --- /dev/null +++ b/benchmarks/new_opencl/bfs/timer.cc @@ -0,0 +1,78 @@ +#include +#include +#include +#include + +#include "timer.h" + + +using namespace std; + +double timer::CPU_speed_in_MHz = timer::get_CPU_speed_in_MHz(); + + +double timer::get_CPU_speed_in_MHz() +{ +#if defined __linux__ + ifstream infile("/proc/cpuinfo"); + char buffer[256], *colon; + + while (infile.good()) { + infile.getline(buffer, 256); + + if (strncmp("cpu MHz", buffer, 7) == 0 && (colon = strchr(buffer, ':')) != 0) + return atof(colon + 2); + } +#endif + + return 0.0; +} + + +void timer::print_time(ostream &str, const char *which, double time) const +{ + static const char *units[] = { " ns", " us", " ms", " s", " ks", 0 }; + const char **unit = units; + + time = 1000.0 * time / CPU_speed_in_MHz; + + while (time >= 999.5 && unit[1] != 0) { + time /= 1000.0; + ++ unit; + } + + str << which << " = " << setprecision(3) << setw(4) << time << *unit; +} + + +ostream &timer::print(ostream &str) +{ + str << left << setw(25) << (name != 0 ? name : "timer") << ": " << right; + + if (CPU_speed_in_MHz == 0) + str << "could not determine CPU speed\n"; + else if (count > 0) { + double total = static_cast(total_time); + + print_time(str, "avg", total / static_cast(count)); + print_time(str, ", total", total); + str << ", count = " << setw(9) << count << '\n'; + } + else + str << "not used\n"; + + return str; +} + + +ostream &operator << (ostream &str, class timer &timer) +{ + return timer.print(str); +} + +double timer::getTimeInSeconds() +{ + double total = static_cast(total_time); + double res = (total / 1000000.0) / CPU_speed_in_MHz; + return res; +} diff --git a/benchmarks/new_opencl/bfs/timer.h b/benchmarks/new_opencl/bfs/timer.h new file mode 100755 index 00000000..b142e279 --- /dev/null +++ b/benchmarks/new_opencl/bfs/timer.h @@ -0,0 +1,101 @@ +#ifndef timer_h +#define timer_h + +#include + +class timer { +public: + timer(const char *name = 0); + timer(const char *name, std::ostream &write_on_exit); + + ~timer(); + + void start(), stop(); + void reset(); + std::ostream &print(std::ostream &); + + double getTimeInSeconds(); + +private: + void print_time(std::ostream &, const char *which, double time) const; + + union { + long long total_time; + struct { +#if defined __PPC__ + int high, low; +#else + int low, high; +#endif + }; + }; + + unsigned long long count; + const char *const name; + std::ostream *const write_on_exit; + + static double CPU_speed_in_MHz, get_CPU_speed_in_MHz(); +}; + +std::ostream &operator<<(std::ostream &, class timer &); + +inline void timer::reset() { + total_time = 0; + count = 0; +} + +inline timer::timer(const char *name) : name(name), write_on_exit(0) { + reset(); +} + +inline timer::timer(const char *name, std::ostream &write_on_exit) + : name(name), write_on_exit(&write_on_exit) { + reset(); +} + +inline timer::~timer() { + if (write_on_exit != 0) + print(*write_on_exit); +} + +inline void timer::start() { +#if (defined __PATHSCALE__) && (defined __i386 || defined __x86_64) + unsigned eax, edx; + + asm volatile("rdtsc" : "=a"(eax), "=d"(edx)); + + total_time -= ((unsigned long long)edx << 32) + eax; +#elif (defined __GNUC__ || defined __INTEL_COMPILER) && \ + (defined __i386 || defined __x86_64) + asm volatile("rdtsc\n\t" + "subl %%eax, %0\n\t" + "sbbl %%edx, %1" + : "+m"(low), "+m"(high) + : + : "eax", "edx"); +#else +#error Compiler/Architecture not recognized +#endif +} + +inline void timer::stop() { +#if (defined __PATHSCALE__) && (defined __i386 || defined __x86_64) + unsigned eax, edx; + + asm volatile("rdtsc" : "=a"(eax), "=d"(edx)); + + total_time += ((unsigned long long)edx << 32) + eax; +#elif (defined __GNUC__ || defined __INTEL_COMPILER) && \ + (defined __i386 || defined __x86_64) + asm volatile("rdtsc\n\t" + "addl %%eax, %0\n\t" + "adcl %%edx, %1" + : "+m"(low), "+m"(high) + : + : "eax", "edx"); +#endif + + ++count; +} + +#endif diff --git a/benchmarks/new_opencl/bfs/util.h b/benchmarks/new_opencl/bfs/util.h new file mode 100755 index 00000000..425edfba --- /dev/null +++ b/benchmarks/new_opencl/bfs/util.h @@ -0,0 +1,72 @@ +#ifndef _C_UTIL_ +#define _C_UTIL_ +#include +#include + +//------------------------------------------------------------------- +//--initialize array with maximum limit +//------------------------------------------------------------------- +template +void fill(datatype *A, const int n, const datatype maxi){ + for (int j = 0; j < n; j++) + { + A[j] = ((datatype) maxi * (rand() / (RAND_MAX + 1.0f))); + } +} + +//--print matrix +template +void print_matrix(datatype *A, int height, int width){ + for(int i=0; i +void verify_array(const datatype *cpuResults, const datatype *gpuResults, const int size){ + + char passed = true; +#pragma omp parallel for + for (int i=0; i MAX_RELATIVE_ERROR){ + passed = false; + } + } + if (passed){ + std::cout << "--cambine:passed:-)" << endl; + } + else{ + std::cout << "--cambine: failed:-(" << endl; + } + return ; +} +template +void compare_results(const datatype *cpu_results, const datatype *gpu_results, const int size){ + + char passed = true; +//#pragma omp parallel for + for (int i=0; i .depend; + +clean: + rm -rf $(PROJECT) *.o *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/benchmarks/new_opencl/guassian/OriginalParallel.c b/benchmarks/new_opencl/guassian/OriginalParallel.c new file mode 100755 index 00000000..6a899b68 --- /dev/null +++ b/benchmarks/new_opencl/guassian/OriginalParallel.c @@ -0,0 +1,241 @@ +/*----------------------------------------------------------- +** ge_p.c -- The program is to solve a linear system Ax = b +** by using Gaussian Elimination. The algorithm on page 101 +** ("Foundations of Parallel Programming") is used. +** The sequential version is ge_s.c. This parallel +** implementation converts three independent for() loops +** into three Fans. Use the data file ge_3.dat to verify +** the correction of the output. +** +** Written by Andreas Kura, 02/15/95 +** Modified by Chong-wei Xu, /04/20/95 +**----------------------------------------------------------- +*/ +#include +#include + +int Size, t; +float **a, *b; +BEGIN_SHARED_DECL + float **m; +END_SHARED_DECL; +FILE *fp; + +void InitProblemOnce(); +void InitPerRun(); +void ForwardSub(); +void Fan1(); +void Fan2(); +void Fan3(); +void InitMat(); +void InitAry(); +void PrintMat(); +void PrintAry(); + +main () +{ + InitializeUs(); + MakeSharedVariables; /* to make SHARED m */ + + InitProblemOnce(); + InitPerRun(); + ForwardSub(); + + printf("The result of matrix m is: \n"); + PrintMat(SHARED m, Size, Size); + printf("The result of matrix a is: \n"); + PrintMat(a, Size, Size); + printf("The result of array b is: \n"); + PrintAry(b, Size); +} + +/*------------------------------------------------------ +** InitProblemOnce -- Initialize all of matrices and +** vectors by opening a data file specified by the user. +** +** We used dynamic array **a, *b, and **m to allocate +** the memory storages. +**------------------------------------------------------ +*/ +void InitProblemOnce() +{ + char filename[30]; + + printf("Enter the data file name: "); + scanf("%s", filename); + printf("The file name is: %s\n", filename); + + fp = fopen(filename, "r"); + + fscanf(fp, "%d", &Size); + a = (float **) UsAllocScatterMatrix(Size, Size, sizeof(float)); + /* + a = (float **) malloc(Size * sizeof(float *)); + for (i=0; i +#include +#include +#include + +#include + +#include "clutils.h" +#include "utils.h" + + +// The following variables have file scope to simplify +// the utility functions + +//! All discoverable OpenCL platforms +static cl_platform_id* platforms = NULL; +static cl_uint numPlatforms; + +//! All discoverable OpenCL devices (one pointer per platform) +static cl_device_id* devices = NULL; +static cl_uint* numDevices; + +//! The chosen OpenCL platform +static cl_platform_id platform = NULL; + +//! The chosen OpenCL device +static cl_device_id device = NULL; + +//! OpenCL context +static cl_context context = NULL; + +//! OpenCL command queue +static cl_command_queue commandQueue = NULL; +static cl_command_queue commandQueueProf = NULL; +static cl_command_queue commandQueueNoProf = NULL; + +//! Global status of events +static bool eventsEnabled = false; + + +//------------------------------------------------------- +// Initialization and Cleanup +//------------------------------------------------------- + +//! Initialize OpenCl environment on one device +/*! + Init function for one device. Looks for supported devices and creates a context + \return returns a context initialized +*/ +/*cl_context cl_init(char devicePreference) +{ + cl_int status; + + // Discover and populate the platforms + status = clGetPlatformIDs(0, NULL, &numPlatforms); + cl_errChk(status, "Getting platform IDs", true); + if (numPlatforms > 0) + { + // Get all the platforms + platforms = (cl_platform_id*)alloc(numPlatforms * + sizeof(cl_platform_id)); + + status = clGetPlatformIDs(numPlatforms, platforms, NULL); + cl_errChk(status, "Getting platform IDs", true); + } + else + { + // If no platforms are available, we shouldn't continue + printf("No OpenCL platforms found\n"); + exit(-1); + } + + // Allocate space for the device lists and lengths + numDevices = (cl_uint*)alloc(sizeof(cl_uint)*numPlatforms); + devices = (cl_device_id**)alloc(sizeof(cl_device_id*)*numPlatforms); + + // If a device preference was supplied, we'll limit the search of devices + // based on type + cl_device_type deviceType = CL_DEVICE_TYPE_ALL; + if(devicePreference == 'c') { + deviceType = CL_DEVICE_TYPE_CPU; + } + if(devicePreference == 'g') { + deviceType = CL_DEVICE_TYPE_GPU; + } + + // Traverse the platforms array printing information and + // populating devices + for(unsigned int i = 0; i < numPlatforms ; i++) + { + // Print out some basic info about the platform + char* platformName = NULL; + char* platformVendor = NULL; + + platformName = cl_getPlatformName(platforms[i]); + platformVendor = cl_getPlatformVendor(platforms[i]); + + status = clGetDeviceIDs(platforms[i], deviceType, 0, NULL, &numDevices[i]); + cl_errChk(status, "Getting device IDs", false); + if(status != CL_SUCCESS) { + printf("This is a known NVIDIA bug (if platform == AMD then die)\n"); + printf("Setting number of devices to 0 and continuing\n"); + numDevices[i] = 0; + } + + printf("Platform %d (%d devices):\n", i, numDevices[i]); + printf("\tName: %s\n", platformName); + printf("\tVendor: %s\n", platformVendor); + + free(platformName); + free(platformVendor); + + // Populate OpenCL devices if any exist + if(numDevices[i] != 0) + { + // Allocate an array of devices of size "numDevices" + devices[i] = (cl_device_id*)alloc(sizeof(cl_device_id)*numDevices[i]); + + // Populate Arrray with devices + status = clGetDeviceIDs(platforms[i], deviceType, numDevices[i], + devices[i], NULL); + cl_errChk(status, "Getting device IDs", true); + } + + // Print some information about each device + for( unsigned int j = 0; j < numDevices[i]; j++) + { + char* deviceName = NULL; + char* deviceVendor = NULL; + + printf("\tDevice %d:\n", j); + + deviceName = cl_getDeviceName(devices[i][j]); + deviceVendor = cl_getDeviceVendor(devices[i][j]); + + printf("\t\tName: %s\n", deviceName); + printf("\t\tVendor: %s\n", deviceVendor); + + free(deviceName); + free(deviceVendor); + } + } + + // Hard-code in the platform/device to use, or uncomment 'scanf' + // to decide at runtime + cl_uint chosen_platform, chosen_device; + // UNCOMMENT the following two lines to manually select device each time + //printf("Enter Platform and Device No (Seperated by Space) \n"); + //scanf("%d %d", &chosen_platform, &chosen_device); + chosen_platform = 0; + chosen_device = 0; + printf("Using Platform %d, Device %d \n", chosen_platform, chosen_device); + + // Do a sanity check of platform/device selection + if(chosen_platform >= numPlatforms || + chosen_device >= numDevices[chosen_platform]) { + printf("Invalid platform/device combination\n"); + exit(-1); + } + + // Set the selected platform and device + platform = platforms[chosen_platform]; + device = devices[chosen_platform][chosen_device]; + + // Create the context + cl_context_properties cps[3] = {CL_CONTEXT_PLATFORM, + (cl_context_properties)(platform), 0}; + context = clCreateContext(cps, 1, &device, NULL, NULL, &status); + cl_errChk(status, "Creating context", true); + + // Create the command queue + commandQueueProf = clCreateCommandQueue(context, device, + CL_QUEUE_PROFILING_ENABLE, &status); + cl_errChk(status, "creating command queue", true); + + commandQueueNoProf = clCreateCommandQueue(context, device, 0, &status); + cl_errChk(status, "creating command queue", true); + + if(eventsEnabled) { + printf("Profiling enabled\n"); + commandQueue = commandQueueProf; + } + else { + printf("Profiling disabled\n"); + commandQueue = commandQueueNoProf; + } + + return context; +}*/ + +cl_context cl_init_context(int platform, int dev,int quiet) { + int printInfo=1; + if (platform >= 0 && dev >= 0) printInfo = 0; + cl_int status; + // Used to iterate through the platforms and devices, respectively + cl_uint numPlatforms; + cl_uint numDevices; + + // These will hold the platform and device we select (can potentially be + // multiple, but we're just doing one for now) + // cl_platform_id platform = NULL; + + /*status = clGetPlatformIDs(0, NULL, &numPlatforms); + if (printInfo) printf("Number of platforms detected:%d\n", numPlatforms); + + // Print some information about the available platforms + cl_platform_id *platforms = NULL; + cl_device_id * devices = NULL; + if (numPlatforms > 0) + { + // get all the platforms + platforms = (cl_platform_id*)malloc(numPlatforms * + sizeof(cl_platform_id)); + status = clGetPlatformIDs(numPlatforms, platforms, NULL); + + // Traverse the platforms array + if (printInfo) printf("Checking For OpenCl Compatible Devices\n"); + for(unsigned int i = 0; i < numPlatforms ; i++) + { + char pbuf[100]; + if (printInfo) printf("Platform %d:\t", i); + status = clGetPlatformInfo(platforms[i], CL_PLATFORM_VENDOR, + sizeof(pbuf), pbuf, NULL); + if (printInfo) printf("Vendor: %s\n", pbuf); + + //unsigned int numDevices; + + status = clGetDeviceIDs(platforms[i], CL_DEVICE_TYPE_ALL, 0, NULL, &numDevices); + if(cl_errChk(status, "checking for devices",true)) + exit(1); + if(numDevices == 0) { + printf("There are no devices for Platform %d\n",i); + exit(0); + } + else + { + if (printInfo) printf("\tNo of devices for Platform %d is %u\n",i, numDevices); + //! Allocate an array of devices of size "numDevices" + devices = (cl_device_id*)malloc(sizeof(cl_device_id)*numDevices); + //! Populate Arrray with devices + status = clGetDeviceIDs(platforms[i], CL_DEVICE_TYPE_ALL, numDevices, + devices, NULL); + if(cl_errChk(status, "getting device IDs",true)) { + exit(1); + } + } + for( unsigned int j = 0; j < numDevices; j++) + { + char dbuf[100]; + char deviceStr[100]; + if (printInfo) printf("\tDevice: %d\t", j); + status = clGetDeviceInfo(devices[j], CL_DEVICE_VENDOR, sizeof(dbuf), + deviceStr, NULL); + cl_errChk(status, "Getting Device Info\n",true); + if (printInfo) printf("Vendor: %s", deviceStr); + status = clGetDeviceInfo(devices[j], CL_DEVICE_NAME, sizeof(dbuf), + dbuf, NULL); + if (printInfo) printf("\n\t\tName: %s\n", dbuf); + } + } + } + else + { + // If no platforms are available, we're sunk! + printf("No OpenCL platforms found\n"); + exit(0); + } + + int platform_touse; + unsigned int device_touse; + if (printInfo) printf("Enter Platform and Device No (Seperated by Space) \n"); + if (printInfo) scanf("%d %d", &platform_touse, &device_touse); + else { + platform_touse = platform; + device_touse = dev; + } + if (!quiet) printf("Using Platform %d \t Device No %d \n",platform_touse, device_touse); + + //! Recheck how many devices does our chosen platform have + status = clGetDeviceIDs(platforms[platform_touse], CL_DEVICE_TYPE_ALL, 0, NULL, &numDevices); + + if(device_touse > numDevices) + { + printf("Invalid Device Number\n"); + exit(1); + } + + //! Populate devices array with all the visible devices of our chosen platform + devices = (cl_device_id *)malloc(sizeof(cl_device_id)*numDevices); + status = clGetDeviceIDs(platforms[platform_touse], + CL_DEVICE_TYPE_ALL, numDevices, + devices, NULL); + if(cl_errChk(status,"Error in Getting Devices\n",true)) exit(1); + + + //!Check if Device requested is a CPU or a GPU + cl_device_type dtype; + device = devices[device_touse]; + status = clGetDeviceInfo(devices[device_touse], + CL_DEVICE_TYPE, + sizeof(dtype), + (void *)&dtype, + NULL); + if(cl_errChk(status,"Error in Getting Device Info\n",true)) exit(1); + if(dtype == CL_DEVICE_TYPE_GPU) { + if (!quiet) printf("Creating GPU Context\n\n"); + } + else if (dtype == CL_DEVICE_TYPE_CPU) { + if (!quiet) printf("Creating CPU Context\n\n"); + } + else perror("This Context Type Not Supported\n"); + + cl_context_properties cps[3] = {CL_CONTEXT_PLATFORM, + (cl_context_properties)(platforms[platform_touse]), 0}; + + cl_context_properties *cprops = cps; + + context = clCreateContextFromType( + cprops, (cl_device_type)dtype, + NULL, NULL, &status); + if(cl_errChk(status, "creating Context",true)) { + exit(1); + }*/ + + // Getting platform and device information + + numPlatforms = 1; + numDevices = 1; + int platform_touse = 0; + int device_touse = 0; + platforms = (cl_platform_id*)malloc(numPlatforms * sizeof(cl_platform_id)); + devices = (cl_device_id*)malloc(sizeof(cl_device_id)*numDevices); + + status = clGetPlatformIDs(1, platforms, NULL); + cl_errChk(status, "Oops!", true); + status = clGetDeviceIDs(platforms[0], CL_DEVICE_TYPE_DEFAULT, 1, devices, NULL); + cl_errChk(status, "Oops!", true); + context = clCreateContext(NULL, 1, devices, NULL, NULL, &status); + cl_errChk(status, "Oops!", true); + + device=devices[device_touse]; + +#define PROFILING + +#ifdef PROFILING + + commandQueue = clCreateCommandQueue(context, + devices[device_touse], CL_QUEUE_PROFILING_ENABLE, &status); + +#else + + clCommandQueue = clCreateCommandQueue(clGPUContext, + devices[device_touse], NULL, &status); + +#endif // PROFILING + + if(cl_errChk(status, "creating command queue",true)) { + exit(1); + } + return context; +} +/*! + Release all resources that the user doesn't have access to. +*/ +void cl_cleanup() +{ + // Free the command queue + if(commandQueue) { + clReleaseCommandQueue(commandQueue); + } + + // Free the context + if(context) { + clReleaseContext(context); + } + + free(devices); + free(numDevices); + + // Free the platforms + free(platforms); +} + +//! Release a kernel object +/*! + \param mem The kernel object to release +*/ +void cl_freeKernel(cl_kernel kernel) +{ + cl_int status; + + if(kernel != NULL) { + status = clReleaseKernel(kernel); + cl_errChk(status, "Releasing kernel object", true); + } +} + +//! Release memory allocated on the device +/*! + \param mem The device pointer to release +*/ +void cl_freeMem(cl_mem mem) +{ + cl_int status; + + if(mem != NULL) { + status = clReleaseMemObject(mem); + cl_errChk(status, "Releasing mem object", true); + } +} + +//! Release a program object +/*! + \param mem The program object to release +*/ +void cl_freeProgram(cl_program program) +{ + cl_int status; + + if(program != NULL) { + status = clReleaseProgram(program); + cl_errChk(status, "Releasing program object", true); + } +} + +//! Returns a reference to the command queue +/*! + Returns a reference to the command queue \n + Used for any OpenCl call that needs the command queue declared in clutils.cpp +*/ +cl_command_queue cl_getCommandQueue() +{ + return commandQueue; +} + +//------------------------------------------------------- +// Synchronization functions +//------------------------------------------------------- + +/*! + Wait till all pending commands in queue are finished +*/ +void cl_sync() +{ + clFinish(commandQueue); +} + + +//------------------------------------------------------- +// Memory allocation +//------------------------------------------------------- + +//! Allocate a buffer on a device +/*! + \param mem_size Size of memory in bytes + \param flags Optional cl_mem_flags + \return Returns a cl_mem object that points to device memory +*/ +cl_mem cl_allocBuffer(size_t mem_size, cl_mem_flags flags) +{ + cl_mem mem; + cl_int status; + + /*! + Logging information for keeping track of device memory + */ + static int allocationCount = 1; + static size_t allocationSize = 0; + + allocationCount++; + allocationSize += mem_size; + + mem = clCreateBuffer(context, flags, mem_size, NULL, &status); + + cl_errChk(status, "creating buffer", true); + + return mem; +} + +//! Allocate constant memory on device +/*! + \param mem_size Size of memory in bytes + \param host_ptr Host pointer that contains the data + \return Returns a cl_mem object that points to device memory +*/ +cl_mem cl_allocBufferConst(size_t mem_size, void* host_ptr) +{ + cl_mem mem; + cl_int status; + + mem = clCreateBuffer(context, CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR, + mem_size, host_ptr, &status); + cl_errChk(status, "Error creating const mem buffer", true); + + return mem; +} + +//! Allocate a buffer on device pinning the host memory at host_ptr +/*! + \param mem_size Size of memory in bytes + \return Returns a cl_mem object that points to pinned memory on the host +*/ +cl_mem cl_allocBufferPinned(size_t mem_size) +{ + cl_mem mem; + cl_int status; + + mem = clCreateBuffer(context, CL_MEM_READ_WRITE | CL_MEM_ALLOC_HOST_PTR, + mem_size, NULL, &status); + cl_errChk(status, "Error allocating pinned memory", true); + + return mem; +} + +//! Allocate an image on a device +/*! + \param height Number of rows in the image + \param width Number of columns in the image + \param elemSize Size of the elements in the image + \param flags Optional cl_mem_flags + \return Returns a cl_mem object that points to device memory +*/ +cl_mem cl_allocImage(size_t height, size_t width, char type, cl_mem_flags flags) +{ + cl_mem mem; + cl_int status; + + size_t elemSize = 0; + + cl_image_format format; + format.image_channel_order = CL_R; + + switch(type) { + case 'f': + elemSize = sizeof(float); + format.image_channel_data_type = CL_FLOAT; + break; + case 'i': + elemSize = sizeof(int); + format.image_channel_data_type = CL_SIGNED_INT32; + break; + default: + printf("Error creating image: Unsupported image type.\n"); + exit(-1); + } + + /*! + Logging information for keeping track of device memory + */ + static int allocationCount = 1; + static size_t allocationSize = 0; + + allocationCount++; + allocationSize += height*width*elemSize; + + // Create the image + mem = clCreateImage2D(context, flags, &format, width, height, 0, NULL, &status); + + //cl_errChk(status, "creating image", true); + if(status != CL_SUCCESS) { + printf("Error creating image: Images may not be supported for this device.\n"); + printSupportedImageFormats(); + getchar(); + exit(-1); + } + + return mem; +} + + +//------------------------------------------------------- +// Data transfers +//------------------------------------------------------- + + +// Copy and map a buffer +void* cl_copyAndMapBuffer(cl_mem dst, cl_mem src, size_t size) { + + void* ptr; // Pointer to the pinned memory that will be returned + + cl_copyBufferToBuffer(dst, src, size); + + ptr = cl_mapBuffer(dst, size, CL_MAP_READ); + + return ptr; +} + +// Copy a buffer +void cl_copyBufferToBuffer(cl_mem dst, cl_mem src, size_t size) +{ + cl_int status; + status = clEnqueueCopyBuffer(commandQueue, src, dst, 0, 0, size, 0, NULL, + NULL); + cl_errChk(status, "Copying buffer", true); + +} + +//! Copy a buffer to the device +/*! + \param dst Valid device pointer + \param src Host pointer that contains the data + \param mem_size Size of data to copy + \param blocking Blocking or non-blocking operation +*/ +void cl_copyBufferToDevice(cl_mem dst, void* src, size_t mem_size, cl_bool blocking) +{ + cl_int status; + status = clEnqueueWriteBuffer(commandQueue, dst, blocking, 0, + mem_size, src, 0, NULL, NULL); + cl_errChk(status, "Writing buffer", true); + +} + +//! Copy a buffer to the host +/*! + \param dst Valid host pointer + \param src Device pointer that contains the data + \param mem_size Size of data to copy + \param blocking Blocking or non-blocking operation +*/ +void cl_copyBufferToHost(void* dst, cl_mem src, size_t mem_size, cl_bool blocking) +{ + cl_int status; + status = clEnqueueReadBuffer(commandQueue, src, blocking, 0, + mem_size, dst, 0, NULL, NULL); + cl_errChk(status, "Reading buffer", true); + +} + +//! Copy a buffer to a 2D image +/*! + \param src Valid device buffer + \param dst Empty device image + \param mem_size Size of data to copy +*/ +void cl_copyBufferToImage(cl_mem buffer, cl_mem image, int height, int width) +{ + size_t origin[3] = {0, 0, 0}; + size_t region[3] = {width, height, 1}; + + cl_int status; + status = clEnqueueCopyBufferToImage(commandQueue, buffer, image, 0, + origin, region, 0, NULL, NULL); + cl_errChk(status, "Copying buffer to image", true); + +} + +// Copy data to an image on the device +/*! + \param dst Valid device pointer + \param src Host pointer that contains the data + \param height Height of the image + \param width Width of the image +*/ +void cl_copyImageToDevice(cl_mem dst, void* src, size_t height, size_t width) +{ + cl_int status; + size_t origin[3] = {0, 0, 0}; + size_t region[3] = {width, height, 1}; + + status = clEnqueueWriteImage(commandQueue, dst, CL_TRUE, origin, + region, 0, 0, src, 0, NULL, NULL); + cl_errChk(status, "Writing image", true); +} + +//! Copy an image to the host +/*! + \param dst Valid host pointer + \param src Device pointer that contains the data + \param height Height of the image + \param width Width of the image +*/ +void cl_copyImageToHost(void* dst, cl_mem src, size_t height, size_t width) +{ + cl_int status; + size_t origin[3] = {0, 0, 0}; + size_t region[3] = {width, height, 1}; + + status = clEnqueueReadImage(commandQueue, src, CL_TRUE, origin, + region, 0, 0, dst, 0, NULL, NULL); + cl_errChk(status, "Reading image", true); +} + +//! Map a buffer into a host address +/*! + \param mem cl_mem object + \param mem_size Size of memory in bytes + \param flags Optional cl_mem_flags + \return Returns a host pointer that points to the mapped region +*/ +void *cl_mapBuffer(cl_mem mem, size_t mem_size, cl_mem_flags flags) +{ + cl_int status; + void *ptr; + + ptr = (void *)clEnqueueMapBuffer(commandQueue, mem, CL_TRUE, flags, + 0, mem_size, 0, NULL, NULL, &status); + + cl_errChk(status, "Error mapping a buffer", true); + + return ptr; +} + +//! Unmap a buffer or image +/*! + \param mem cl_mem object + \param ptr A host pointer that points to the mapped region +*/ +void cl_unmapBuffer(cl_mem mem, void *ptr) +{ + + // TODO It looks like AMD doesn't support profiling unmapping yet. Leaving the + // commented code here until it's supported + + cl_int status; + + status = clEnqueueUnmapMemObject(commandQueue, mem, ptr, 0, NULL, NULL); + + cl_errChk(status, "Error unmapping a buffer or image", true); +} + +void cl_writeToZCBuffer(cl_mem mem, void* data, size_t size) +{ + + void* ptr; + + ptr = cl_mapBuffer(mem, size, CL_MAP_WRITE); + + memcpy(ptr, data, size); + + cl_unmapBuffer(mem, ptr); +} + +static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) { + if (nullptr == filename || nullptr == data || 0 == size) + return -1; + + FILE* fp = fopen(filename, "r"); + if (NULL == fp) { + fprintf(stderr, "Failed to load kernel."); + return -1; + } + fseek(fp , 0 , SEEK_END); + long fsize = ftell(fp); + rewind(fp); + + *data = (uint8_t*)malloc(fsize); + *size = fread(*data, 1, fsize, fp); + + fclose(fp); + + return 0; +} + +//------------------------------------------------------- +// Program and kernels +//------------------------------------------------------- + +//! Convert source code file into cl_program +/*! +Compile Opencl source file into a cl_program. The cl_program will be made into a kernel in PrecompileKernels() + +\param kernelPath Filename of OpenCl code +\param compileoptions Compilation options +\param verbosebuild Switch to enable verbose Output +*/ +cl_program cl_compileProgram(char* kernelPath, char* compileoptions, bool verbosebuild ) +{ + cl_int status; + FILE *fp = NULL; + char *source = NULL; + long int size; + + /*printf("\t%s\n", kernelPath); + + // Determine the size of the source file +#ifdef _WIN32 + fopen_s(&fp, kernelPath, "rb"); +#else + fp = fopen(kernelPath, "rb"); +#endif + if(!fp) { + printf("Could not open kernel file\n"); + exit(-1); + } + status = fseek(fp, 0, SEEK_END); + if(status != 0) { + printf("Error seeking to end of file\n"); + exit(-1); + } + size = ftell(fp); + if(size < 0) { + printf("Error getting file position\n"); + exit(-1); + } + rewind(fp); + + // Allocate enough space for the source code + source = (char *)alloc(size + 1); + + // fill with NULLs (just for fun) + for (int i = 0; i < size+1; i++) { + source[i] = '\0'; + } + + // Read in the source code + fread(source, 1, size, fp); + source[size] = '\0';*/ + + // Create the program object + //cl_program clProgramReturn = clCreateProgramWithSource(context, 1, (const char **)&source, NULL, &status); + //cl_program clProgramReturn = clCreateProgramWithBuiltInKernels(context, 1, &device, "Fan1;Fan2", &status); + // read kernel binary from file + uint8_t *kernel_bin = NULL; + size_t kernel_size; + cl_int binary_status = 0; + status = read_kernel_file("kernel.pocl", &kernel_bin, &kernel_size); + cl_errChk(status, "read_kernel_file", true); + cl_program clProgramReturn = clCreateProgramWithBinary( + context, 1, &device, &kernel_size, &kernel_bin, &binary_status, &status); + free(kernel_bin); + cl_errChk(status, "Creating program", true); + + //free(source); + //fclose(fp); + + // Try to compile the program + status = clBuildProgram(clProgramReturn, 0, NULL, compileoptions, NULL, NULL); + if(cl_errChk(status, "Building program", false) || verbosebuild == 1) + { + + cl_build_status build_status; + + clGetProgramBuildInfo(clProgramReturn, device, CL_PROGRAM_BUILD_STATUS, + sizeof(cl_build_status), &build_status, NULL); + + if(build_status == CL_SUCCESS && verbosebuild == 0) { + return clProgramReturn; + } + + //char *build_log; + size_t ret_val_size; + printf("Device: %p",device); + clGetProgramBuildInfo(clProgramReturn, device, CL_PROGRAM_BUILD_LOG, 0, + NULL, &ret_val_size); + + char *build_log = (char*)alloc(ret_val_size+1); + + clGetProgramBuildInfo(clProgramReturn, device, CL_PROGRAM_BUILD_LOG, + ret_val_size+1, build_log, NULL); + + // to be careful, terminate with \0 + // there's no information in the reference whether the string is 0 + // terminated or not + build_log[ret_val_size] = '\0'; + + printf("Build log:\n %s...\n", build_log); + if(build_status != CL_SUCCESS) { + getchar(); + exit(-1); + } + else + return clProgramReturn; + } + + // print the ptx information + // printBinaries(clProgram); + + return clProgramReturn; +} + +//! Create a kernel from compiled source +/*! +Create a kernel from compiled source + +\param program Compiled OpenCL program +\param kernel_name Name of the kernel in the program +\return Returns a cl_kernel object for the specified kernel +*/ +cl_kernel cl_createKernel(cl_program program, const char* kernel_name) { + + cl_kernel kernel; + cl_int status; + + kernel = clCreateKernel(program, kernel_name, &status); + cl_errChk(status, "Creating kernel", true); + + return kernel; +} + +//! Set an argument for a OpenCL kernel +/*! +Set an argument for a OpenCL kernel + +\param kernel The kernel for which the argument is being set +\param index The argument index +\param size The size of the argument +\param data A pointer to the argument +*/ +void cl_setKernelArg(cl_kernel kernel, unsigned int index, size_t size, + void* data) +{ + cl_int status; + status = clSetKernelArg(kernel, index, size, data); + + cl_errChk(status, "Setting kernel arg", true); +} + + +//------------------------------------------------------- +// Profiling/events +//------------------------------------------------------- + + +//! Time kernel execution using cl_event +/*! + Prints out the time taken between the start and end of an event + \param event_time +*/ +double cl_computeExecTime(cl_event event_time) +{ + cl_int status; + cl_ulong starttime; + cl_ulong endtime; + + double elapsed; + + status = clGetEventProfilingInfo(event_time, CL_PROFILING_COMMAND_START, + sizeof(cl_ulong), &starttime, NULL); + cl_errChk(status, "profiling start", true); + + status = clGetEventProfilingInfo(event_time, CL_PROFILING_COMMAND_END, + sizeof(cl_ulong), &endtime, NULL); + cl_errChk(status, "profiling end", true); + + // Convert to ms + elapsed = (double)(endtime-starttime)/1000000.0; + + return elapsed; +} + +//! Compute the elapsed time between two timer values +double cl_computeTime(cl_time start, cl_time end) +{ +#ifdef _WIN32 + __int64 freq; + int status; + + status = QueryPerformanceFrequency((LARGE_INTEGER*)&freq); + if(status == 0) { + perror("QueryPerformanceFrequency"); + exit(-1); + } + + // Return time in ms + return double(end-start)/(double(freq)/1000.0); +#else + + return end-start; +#endif +} + +//! Grab the current time using a system-specific timer +void cl_getTime(cl_time* time) +{ + +#ifdef _WIN32 + int status = QueryPerformanceCounter((LARGE_INTEGER*)time); + if(status == 0) { + perror("QueryPerformanceCounter"); + exit(-1); + } +#else + // Use gettimeofday to get the current time + struct timeval curTime; + gettimeofday(&curTime, NULL); + + // Convert timeval into double + *time = curTime.tv_sec * 1000 + (double)curTime.tv_usec/1000; +#endif +} + + + +//------------------------------------------------------- +// Error handling +//------------------------------------------------------- + +//! OpenCl error code list +/*! + An array of character strings used to give the error corresponding to the error code \n + + The error code is the index within this array +*/ +char *cl_errs[MAX_ERR_VAL] = { + (char *)"CL_SUCCESS", // 0 + (char *)"CL_DEVICE_NOT_FOUND", //-1 + (char *)"CL_DEVICE_NOT_AVAILABLE", //-2 + (char *)"CL_COMPILER_NOT_AVAILABLE", //-3 + (char *)"CL_MEM_OBJECT_ALLOCATION_FAILURE", //-4 + (char *)"CL_OUT_OF_RESOURCES", //-5 + (char *)"CL_OUT_OF_HOST_MEMORY", //-6 + (char *)"CL_PROFILING_INFO_NOT_AVAILABLE", //-7 + (char *)"CL_MEM_COPY_OVERLAP", //-8 + (char *)"CL_IMAGE_FORMAT_MISMATCH", //-9 + (char *)"CL_IMAGE_FORMAT_NOT_SUPPORTED", //-10 + (char *)"CL_BUILD_PROGRAM_FAILURE", //-11 + (char *)"CL_MAP_FAILURE", //-12 + (char *)"", //-13 + (char *)"", //-14 + (char *)"", //-15 + (char *)"", //-16 + (char *)"", //-17 + (char *)"", //-18 + (char *)"", //-19 + (char *)"", //-20 + (char *)"", //-21 + (char *)"", //-22 + (char *)"", //-23 + (char *)"", //-24 + (char *)"", //-25 + (char *)"", //-26 + (char *)"", //-27 + (char *)"", //-28 + (char *)"", //-29 + (char *)"CL_INVALID_VALUE", //-30 + (char *)"CL_INVALID_DEVICE_TYPE", //-31 + (char *)"CL_INVALID_PLATFORM", //-32 + (char *)"CL_INVALID_DEVICE", //-33 + (char *)"CL_INVALID_CONTEXT", //-34 + (char *)"CL_INVALID_QUEUE_PROPERTIES", //-35 + (char *)"CL_INVALID_COMMAND_QUEUE", //-36 + (char *)"CL_INVALID_HOST_PTR", //-37 + (char *)"CL_INVALID_MEM_OBJECT", //-38 + (char *)"CL_INVALID_IMAGE_FORMAT_DESCRIPTOR", //-39 + (char *)"CL_INVALID_IMAGE_SIZE", //-40 + (char *)"CL_INVALID_SAMPLER", //-41 + (char *)"CL_INVALID_BINARY", //-42 + (char *)"CL_INVALID_BUILD_OPTIONS", //-43 + (char *)"CL_INVALID_PROGRAM", //-44 + (char *)"CL_INVALID_PROGRAM_EXECUTABLE", //-45 + (char *)"CL_INVALID_KERNEL_NAME", //-46 + (char *)"CL_INVALID_KERNEL_DEFINITION", //-47 + (char *)"CL_INVALID_KERNEL", //-48 + (char *)"CL_INVALID_ARG_INDEX", //-49 + (char *)"CL_INVALID_ARG_VALUE", //-50 + (char *)"CL_INVALID_ARG_SIZE", //-51 + (char *)"CL_INVALID_KERNEL_ARGS", //-52 + (char *)"CL_INVALID_WORK_DIMENSION ", //-53 + (char *)"CL_INVALID_WORK_GROUP_SIZE", //-54 + (char *)"CL_INVALID_WORK_ITEM_SIZE", //-55 + (char *)"CL_INVALID_GLOBAL_OFFSET", //-56 + (char *)"CL_INVALID_EVENT_WAIT_LIST", //-57 + (char *)"CL_INVALID_EVENT", //-58 + (char *)"CL_INVALID_OPERATION", //-59 + (char *)"CL_INVALID_GL_OBJECT", //-60 + (char *)"CL_INVALID_BUFFER_SIZE", //-61 + (char *)"CL_INVALID_MIP_LEVEL", //-62 + (char *)"CL_INVALID_GLOBAL_WORK_SIZE"}; //-63 + +//! OpenCl Error checker +/*! +Checks for error code as per cl_int returned by OpenCl +\param status Error value as cl_int +\param msg User provided error message +\return True if Error Seen, False if no error +*/ +int cl_errChk(const cl_int status, const char * msg, bool exitOnErr) +{ + + if(status != CL_SUCCESS) { + printf("OpenCL Error: %d %s %s\n", status, cl_errs[-status], msg); + + if(exitOnErr) { + exit(-1); + } + + return true; + } + return false; +} + +// Queries the supported image formats for the device and prints +// them to the screen + void printSupportedImageFormats() +{ + cl_uint numFormats; + cl_int status; + + status = clGetSupportedImageFormats(context, 0, CL_MEM_OBJECT_IMAGE2D, + 0, NULL, &numFormats); + cl_errChk(status, "getting supported image formats", true); + + cl_image_format* imageFormats = NULL; + imageFormats = (cl_image_format*)alloc(sizeof(cl_image_format)*numFormats); + + status = clGetSupportedImageFormats(context, 0, CL_MEM_OBJECT_IMAGE2D, + numFormats, imageFormats, NULL); + + printf("There are %d supported image formats\n", numFormats); + + cl_uint orders[]={CL_R, CL_A, CL_INTENSITY, CL_LUMINANCE, CL_RG, + CL_RA, CL_RGB, CL_RGBA, CL_ARGB, CL_BGRA}; + char *orderstr[]={(char *)"CL_R", (char *)"CL_A",(char *)"CL_INTENSITY", (char *)"CL_LUMINANCE", (char *)"CL_RG", + (char *)"CL_RA", (char *)"CL_RGB", (char *)"CL_RGBA", (char *)"CL_ARGB", (char *)"CL_BGRA"}; + + cl_uint types[]={ + CL_SNORM_INT8 , CL_SNORM_INT16, CL_UNORM_INT8, CL_UNORM_INT16, + CL_UNORM_SHORT_565, CL_UNORM_SHORT_555, CL_UNORM_INT_101010,CL_SIGNED_INT8, + CL_SIGNED_INT16, CL_SIGNED_INT32, CL_UNSIGNED_INT8, CL_UNSIGNED_INT16, + CL_UNSIGNED_INT32, CL_HALF_FLOAT, CL_FLOAT}; + + char * typesstr[]={ + (char *)"CL_SNORM_INT8" ,(char *)"CL_SNORM_INT16",(char *)"CL_UNORM_INT8",(char *)"CL_UNORM_INT16", + (char *)"CL_UNORM_SHORT_565",(char *)"CL_UNORM_SHORT_555",(char *)"CL_UNORM_INT_101010", + (char *)"CL_SIGNED_INT8",(char *)"CL_SIGNED_INT16",(char *)"CL_SIGNED_INT32",(char *)"CL_UNSIGNED_INT8", + (char *)"CL_UNSIGNED_INT16",(char *)"CL_UNSIGNED_INT32",(char *)"CL_HALF_FLOAT",(char *)"CL_FLOAT"}; + + printf("Supported Formats:\n"); + for(int i = 0; i < (int)numFormats; i++) { + printf("\tFormat %d: ", i); + + for(int j = 0; j < (int)(sizeof(orders)/sizeof(cl_int)); j++) { + if(imageFormats[i].image_channel_order == orders[j]) { + printf("%s, ", orderstr[j]); + } + } + for(int j = 0; j < (int)(sizeof(types)/sizeof(cl_int)); j++) { + if(imageFormats[i].image_channel_data_type == types[j]) { + printf("%s, ", typesstr[j]); + } + } + printf("\n"); + } + + free(imageFormats); +} + + +//------------------------------------------------------- +// Platform and device information +//------------------------------------------------------- + +//! Returns true if AMD is the device vendor +bool cl_deviceIsAMD(cl_device_id dev) { + + bool retval = false; + + char* vendor = cl_getDeviceVendor(dev); + + if(strncmp(vendor, "Advanced", 8) == 0) { + retval = true; + } + + free(vendor); + + return retval; +} + +//! Returns true if NVIDIA is the device vendor +bool cl_deviceIsNVIDIA(cl_device_id dev) { + + bool retval = false; + + char* vendor = cl_getDeviceVendor(dev); + + if(strncmp(vendor, "NVIDIA", 6) == 0) { + retval = true; + } + + free(vendor); + + return retval; +} + +//! Returns true if NVIDIA is the device vendor +bool cl_platformIsNVIDIA(cl_platform_id plat) { + + bool retval = false; + + char* vendor = cl_getPlatformVendor(plat); + + if(strncmp(vendor, "NVIDIA", 6) == 0) { + retval = true; + } + + free(vendor); + + return retval; +} + +//! Get the name of the vendor for a device +char* cl_getDeviceDriverVersion(cl_device_id dev) +{ + cl_int status; + size_t devInfoSize; + char* devInfoStr = NULL; + + // If dev is NULL, set it to the default device + if(dev == NULL) { + dev = device; + } + + // Print the vendor + status = clGetDeviceInfo(dev, CL_DRIVER_VERSION, 0, + NULL, &devInfoSize); + cl_errChk(status, "Getting vendor name", true); + + devInfoStr = (char*)alloc(devInfoSize); + + status = clGetDeviceInfo(dev, CL_DRIVER_VERSION, devInfoSize, + devInfoStr, NULL); + cl_errChk(status, "Getting vendor name", true); + + return devInfoStr; +} + +//! The the name of the device as supplied by the OpenCL implementation +char* cl_getDeviceName(cl_device_id dev) +{ + cl_int status; + size_t devInfoSize; + char* devInfoStr = NULL; + + // If dev is NULL, set it to the default device + if(dev == NULL) { + dev = device; + } + + // Print the name + status = clGetDeviceInfo(dev, CL_DEVICE_NAME, 0, + NULL, &devInfoSize); + cl_errChk(status, "Getting device name", true); + + devInfoStr = (char*)alloc(devInfoSize); + + status = clGetDeviceInfo(dev, CL_DEVICE_NAME, devInfoSize, + devInfoStr, NULL); + cl_errChk(status, "Getting device name", true); + + return(devInfoStr); +} + +//! Get the name of the vendor for a device +char* cl_getDeviceVendor(cl_device_id dev) +{ + cl_int status; + size_t devInfoSize; + char* devInfoStr = NULL; + + // If dev is NULL, set it to the default device + if(dev == NULL) { + dev = device; + } + + // Print the vendor + status = clGetDeviceInfo(dev, CL_DEVICE_VENDOR, 0, + NULL, &devInfoSize); + cl_errChk(status, "Getting vendor name", true); + + devInfoStr = (char*)alloc(devInfoSize); + + status = clGetDeviceInfo(dev, CL_DEVICE_VENDOR, devInfoSize, + devInfoStr, NULL); + cl_errChk(status, "Getting vendor name", true); + + return devInfoStr; +} + +//! Get the name of the vendor for a device +char* cl_getDeviceVersion(cl_device_id dev) +{ + cl_int status; + size_t devInfoSize; + char* devInfoStr = NULL; + + // If dev is NULL, set it to the default device + if(dev == NULL) { + dev = device; + } + + // Print the vendor + status = clGetDeviceInfo(dev, CL_DEVICE_VERSION, 0, + NULL, &devInfoSize); + cl_errChk(status, "Getting vendor name", true); + + devInfoStr = (char*)alloc(devInfoSize); + + status = clGetDeviceInfo(dev, CL_DEVICE_VERSION, devInfoSize, + devInfoStr, NULL); + cl_errChk(status, "Getting vendor name", true); + + return devInfoStr; +} + +//! The the name of the device as supplied by the OpenCL implementation +char* cl_getPlatformName(cl_platform_id platform) +{ + cl_int status; + size_t platformInfoSize; + char* platformInfoStr = NULL; + + // Print the name + status = clGetPlatformInfo(platform, CL_PLATFORM_NAME, 0, + NULL, &platformInfoSize); + cl_errChk(status, "Getting platform name", true); + + platformInfoStr = (char*)alloc(platformInfoSize); + + status = clGetPlatformInfo(platform, CL_PLATFORM_NAME, platformInfoSize, + platformInfoStr, NULL); + cl_errChk(status, "Getting platform name", true); + + return(platformInfoStr); +} + +//! The the name of the device as supplied by the OpenCL implementation +char* cl_getPlatformVendor(cl_platform_id platform) +{ + cl_int status; + size_t platformInfoSize; + char* platformInfoStr = NULL; + + // Print the name + status = clGetPlatformInfo(platform, CL_PLATFORM_VENDOR, 0, + NULL, &platformInfoSize); + cl_errChk(status, "Getting platform name", true); + + platformInfoStr = (char*)alloc(platformInfoSize); + + status = clGetPlatformInfo(platform, CL_PLATFORM_VENDOR, platformInfoSize, + platformInfoStr, NULL); + cl_errChk(status, "Getting platform name", true); + + return(platformInfoStr); +} + +//------------------------------------------------------- +// Utility functions +//------------------------------------------------------- + +//! Take a string and an int, and return a string +char* catStringWithInt(const char* string, int integer) { + + if(integer > 99999) { + printf("Can't handle event identifiers with 6 digits\n"); + exit(-1); + } + + // 5 characters for the identifier, 1 for the null terminator + int strLen = strlen(string)+5+1; + char* eventStr = (char*)alloc(sizeof(char)*strLen); + + char tmp[6]; + + strcpy(eventStr, string); + strncat(eventStr, itoa_portable(integer, tmp, 10), 5); + + return eventStr; +} + +/** + ** C++ version 0.4 char* style "itoa": + ** Written by Lukás Chmela + ** Released under GPLv3. + **/ +//portable itoa function +char* itoa_portable(int value, char* result, int base) { + // check that the base if valid + if (base < 2 || base > 36) { *result = '\0'; return result; } + + char* ptr = result, *ptr1 = result, tmp_char; + int tmp_value; + + do { + tmp_value = value; + value /= base; + *ptr++ = "zyxwvutsrqponmlkjihgfedcba9876543210123456789abcdefghijklmnopqrstuvwxyz" [35 + (tmp_value - value * base)]; + } while ( value ); + + //Apply negative sign + if (tmp_value < 0) *ptr++ = '-'; + *ptr-- = '\0'; + + while(ptr1 < ptr) { + tmp_char = *ptr; + *ptr--= *ptr1; + *ptr1++ = tmp_char; + } + + return result; +} diff --git a/benchmarks/new_opencl/guassian/clutils.h b/benchmarks/new_opencl/guassian/clutils.h new file mode 100755 index 00000000..51177d07 --- /dev/null +++ b/benchmarks/new_opencl/guassian/clutils.h @@ -0,0 +1,281 @@ +/****************************************************************************\ + * Copyright (c) 2011, Advanced Micro Devices, Inc. * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or without * + * modification, are permitted provided that the following conditions * + * are met: * + * * + * Redistributions of source code must retain the above copyright notice, * + * this list of conditions and the following disclaimer. * + * * + * Redistributions in binary form must reproduce the above copyright notice, * + * this list of conditions and the following disclaimer in the documentation * + * and/or other materials provided with the distribution. * + * * + * Neither the name of the copyright holder nor the names of its contributors * + * may be used to endorse or promote products derived from this software * + * without specific prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * + * * + * If you use the software (in whole or in part), you shall adhere to all * + * applicable U.S., European, and other export laws, including but not * + * limited to the U.S. Export Administration Regulations (“EAR”), (15 C.F.R. * + * Sections 730 through 774), and E.U. Council Regulation (EC) No 1334/2000 * + * of 22 June 2000. Further, pursuant to Section 740.6 of the EAR, you * + * hereby certify that, except pursuant to a license granted by the United * + * States Department of Commerce Bureau of Industry and Security or as * + * otherwise permitted pursuant to a License Exception under the U.S. Export * + * Administration Regulations ("EAR"), you will not (1) export, re-export or * + * release to a national of a country in Country Groups D:1, E:1 or E:2 any * + * restricted technology, software, or source code you receive hereunder, * + * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such * + * technology or software, if such foreign produced direct product is subject * + * to national security controls as identified on the Commerce Control List * + *(currently found in Supplement 1 to Part 774 of EAR). For the most current * + * Country Group listings, or for additional information about the EAR or * + * your obligations under those regulations, please refer to the U.S. Bureau * + * of Industry and Security’s website at http://www.bis.doc.gov/. * + \****************************************************************************/ + +#ifndef __CL_UTILS_H__ +#define __CL_UTILS_H__ + +#include + +// The cl_time type is OS specific +#ifdef _WIN32 +#include +#include +typedef __int64 cl_time; +#else +#include +typedef double cl_time; +#endif + +//------------------------------------------------------- +// Initialization and Cleanup +//------------------------------------------------------- + +// Detects platforms and devices, creates context and command queue +cl_context cl_init(char devicePreference='\0'); + +// Creates a context given a platform and a device +cl_context cl_init_context(int platform,int dev,int quiet=0); + +// Releases resources used by clutils +void cl_cleanup(); + +// Releases a kernel object +void cl_freeKernel(cl_kernel kernel); + +// Releases a memory object +void cl_freeMem(cl_mem mem); + +// Releases a program object +void cl_freeProgram(cl_program program); + +// Returns the global command queue +cl_command_queue cl_getCommandQueue(); + + +//------------------------------------------------------- +// Synchronization functions +//------------------------------------------------------- + +// Performs a clFinish on the command queue +void cl_sync(); + + +//------------------------------------------------------- +// Memory allocation +//------------------------------------------------------- + +// Allocates a regular buffer on the device +cl_mem cl_allocBuffer(size_t mem_size, + cl_mem_flags flags = CL_MEM_READ_WRITE); + +// XXX I don't think this does exactly what we want it to do +// Allocates a read-only buffer and transfers the data +cl_mem cl_allocBufferConst(size_t mem_size, void* host_ptr); + +// Allocates pinned memory on the host +cl_mem cl_allocBufferPinned(size_t mem_size); + +// Allocates an image on the device +cl_mem cl_allocImage(size_t height, size_t width, char type, + cl_mem_flags flags = CL_MEM_READ_WRITE); + + + +//------------------------------------------------------- +// Data transfers +//------------------------------------------------------- + +// Copies a buffer from the device to pinned memory on the host and +// maps it so it can be read +void* cl_copyAndMapBuffer(cl_mem dst, cl_mem src, size_t size); + +// Copies from one buffer to another +void cl_copyBufferToBuffer(cl_mem dst, cl_mem src, size_t size); + +// Copies data to a buffer on the device +void cl_copyBufferToDevice(cl_mem dst, void *src, size_t mem_size, + cl_bool blocking = CL_TRUE); + +// Copies data to an image on the device +void cl_copyImageToDevice(cl_mem dst, void* src, size_t height, size_t width); + +// Copies an image from the device to the host +void cl_copyImageToHost(void* dst, cl_mem src, size_t height, size_t width); + +// Copies data from a device buffer to the host +void cl_copyBufferToHost(void *dst, cl_mem src, size_t mem_size, + cl_bool blocking = CL_TRUE); + +// Copies data from a buffer on the device to an image on the device +void cl_copyBufferToImage(cl_mem src, cl_mem dst, int height, int width); + +// Maps a buffer +void* cl_mapBuffer(cl_mem mem, size_t mem_size, cl_mem_flags flags); + +// Unmaps a buffer +void cl_unmapBuffer(cl_mem mem, void *ptr); + +// Writes data to a zero-copy buffer on the device +void cl_writeToZCBuffer(cl_mem mem, void* data, size_t size); + +//------------------------------------------------------- +// Program and kernels +//------------------------------------------------------- + +// Compiles a program +cl_program cl_compileProgram(char* kernelPath, char* compileoptions, + bool verboseoptions = 0); + +// Creates a kernel +cl_kernel cl_createKernel(cl_program program, const char* kernelName); + + +// Sets a kernel argument +void cl_setKernelArg(cl_kernel kernel, unsigned int index, size_t size, + void* data); + + +//------------------------------------------------------- +// Profiling/events +//------------------------------------------------------- + +// Computes the execution time (start to end) for an event +double cl_computeExecTime(cl_event); + +// Compute the elapsed time between two CPU timer values +double cl_computeTime(cl_time start, cl_time end); + +// Creates an event from CPU timers +void cl_createUserEvent(cl_time start, cl_time end, char* desc); + +// Disable logging of events +void cl_disableEvents(); + +// Enable logging of events +void cl_enableEvents(); + +// Query the current system time +void cl_getTime(cl_time* time); + +// Calls a function which prints events to the terminal +void cl_printEvents(); + +// Calls a function which writes the events to a file +void cl_writeEventsToFile(char* path); + + +//------------------------------------------------------- +// Error handling +//------------------------------------------------------- + +// Compare a status value to CL_SUCCESS and optionally exit on error +int cl_errChk(const cl_int status, const char *msg, bool exitOnErr); + +// Queries the supported image formats for the device and prints +// them to the screen +void printSupportedImageFormats(); + +//------------------------------------------------------- +// Platform and device information +//------------------------------------------------------- + +bool cl_deviceIsAMD(cl_device_id dev=NULL); +bool cl_deviceIsNVIDIA(cl_device_id dev=NULL); +bool cl_platformIsNVIDIA(cl_platform_id plat=NULL); +char* cl_getDeviceDriverVersion(cl_device_id dev=NULL); +char* cl_getDeviceName(cl_device_id dev=NULL); +char* cl_getDeviceVendor(cl_device_id dev=NULL); +char* cl_getDeviceVersion(cl_device_id dev=NULL); +char* cl_getPlatformName(cl_platform_id platform); +char* cl_getPlatformVendor(cl_platform_id platform); + +//------------------------------------------------------- +// Utility functions +//------------------------------------------------------- + +char* catStringWithInt(const char* str, int integer); + +char* itoa_portable(int value, char* result, int base); + +//------------------------------------------------------- +// Data types +//------------------------------------------------------- +typedef struct{ + int x; + int y; +} int2; + +typedef struct{ + float x; + float y; +}float2; + +typedef struct{ + float x; + float y; + float z; + float w; +}float4; + +//------------------------------------------------------- +// Defines +//------------------------------------------------------- + +#define MAX_ERR_VAL 64 + +#define NUM_PROGRAMS 7 + +#define NUM_KERNELS 13 +#define KERNEL_INIT_DET 0 +#define KERNEL_BUILD_DET 1 +#define KERNEL_SURF_DESC 2 +#define KERNEL_NORM_DESC 3 +#define KERNEL_NON_MAX_SUP 4 +#define KERNEL_GET_ORIENT1 5 +#define KERNEL_GET_ORIENT2 6 +#define KERNEL_NN 7 +#define KERNEL_SCAN 8 +#define KERNEL_SCAN4 9 +#define KERNEL_TRANSPOSE 10 +#define KERNEL_SCANIMAGE 11 +#define KERNEL_TRANSPOSEIMAGE 12 + +#endif diff --git a/benchmarks/new_opencl/guassian/gaussianElim.h b/benchmarks/new_opencl/guassian/gaussianElim.h new file mode 100755 index 00000000..5d905d7e --- /dev/null +++ b/benchmarks/new_opencl/guassian/gaussianElim.h @@ -0,0 +1,40 @@ +#ifndef _GAUSSIANELIM +#define _GAUSSIANELIM + +#include +#include +#include +#include +#include +#include +#include + +#include "clutils.h" + +// All OpenCL headers +#if defined (__APPLE__) || defined(MACOSX) + #include +#else + #include +#endif + +float *OpenClGaussianElimination( + cl_context context, + int timing); + +void printUsage(); +int parseCommandline(int argc, char *argv[], char* filename, + int *q, int *t, int *p, int *d); + +void InitPerRun(int size,float *m); +void ForwardSub(cl_context context, float *a, float *b, float *m, int size,int timing); +void BackSub(float *a, float *b, float *finalVec, int size); +void Fan1(float *m, float *a, int Size, int t); +void Fan2(float *m, float *a, float *b,int Size, int j1, int t); +//void Fan3(float *m, float *b, int Size, int t); +void InitMat(FILE *fp, int size, float *ary, int nrow, int ncol); +void InitAry(FILE *fp, float *ary, int ary_size); +void PrintMat(float *ary, int size, int nrow, int ncolumn); +void PrintAry(float *ary, int ary_size); +float eventTime(cl_event event,cl_command_queue command_queue); +#endif diff --git a/benchmarks/new_opencl/guassian/gettimeofday.cpp b/benchmarks/new_opencl/guassian/gettimeofday.cpp new file mode 100755 index 00000000..a0486593 --- /dev/null +++ b/benchmarks/new_opencl/guassian/gettimeofday.cpp @@ -0,0 +1,74 @@ +#include "stdio.h" +#include +#include +#include +//using namespace System; +using namespace std; + +#if defined(_MSC_VER) || defined(_MSC_EXTENSIONS) + #define DELTA_EPOCH_IN_MICROSECS 11644473600000000Ui64 +#else + #define DELTA_EPOCH_IN_MICROSECS 11644473600000000ULL +#endif + +struct timezone +{ + int tz_minuteswest; /* minutes W of Greenwich */ + int tz_dsttime; /* type of dst correction */ +}; + + +// Definition of a gettimeofday function + int gettimeofday(struct timeval *tv, struct timezone *tz) +{ +// Define a structure to receive the current Windows filetime + FILETIME ft; + +// Initialize the present time to 0 and the timezone to UTC + unsigned __int64 tmpres = 0; + static int tzflag = 0; + + if (NULL != tv) + { + GetSystemTimeAsFileTime(&ft); + +// The GetSystemTimeAsFileTime returns the number of 100 nanosecond +// intervals since Jan 1, 1601 in a structure. Copy the high bits to +// the 64 bit tmpres, shift it left by 32 then or in the low 32 bits. + tmpres |= ft.dwHighDateTime; + tmpres <<= 32; + tmpres |= ft.dwLowDateTime; + +// Convert to microseconds by dividing by 10 + tmpres /= 10; + +// The Unix epoch starts on Jan 1 1970. Need to subtract the difference +// in seconds from Jan 1 1601. + tmpres -= DELTA_EPOCH_IN_MICROSECS; + +// Finally change microseconds to seconds and place in the seconds value. +// The modulus picks up the microseconds. + tv->tv_sec = (long)(tmpres / 1000000UL); + tv->tv_usec = (long)(tmpres % 1000000UL); + } + + if (NULL != tz) + { + if (!tzflag) + { + _tzset(); + tzflag++; + } + +// Adjust for the timezone west of Greenwich + long seconds_diff; + _get_timezone(&seconds_diff); + tz->tz_minuteswest = seconds_diff / 60; + int hours_offset; + _get_daylight(&hours_offset); + tz->tz_dsttime = hours_offset; + } + + return 0; +} + diff --git a/benchmarks/new_opencl/guassian/gettimeofday.h b/benchmarks/new_opencl/guassian/gettimeofday.h new file mode 100755 index 00000000..8db1f7a9 --- /dev/null +++ b/benchmarks/new_opencl/guassian/gettimeofday.h @@ -0,0 +1,17 @@ + +#ifdef _WIN32 +#include +/** +Based on code seen at. + +http://www.winehq.org/pipermail/wine-devel/2003-June/018082.html + +http://msdn.microsoft.com/en-us/library/ms740560 + +*/ +int gettimeofday(struct timeval *tv, struct timezone *tz); +#else +#include +#endif + + diff --git a/benchmarks/new_opencl/guassian/kernel.cl b/benchmarks/new_opencl/guassian/kernel.cl new file mode 100755 index 00000000..c370e9b2 --- /dev/null +++ b/benchmarks/new_opencl/guassian/kernel.cl @@ -0,0 +1,49 @@ +//#pragma OPENCL EXTENSION cl_khr_byte_addressable_store : enable + +typedef struct latLong + { + float lat; + float lng; + } LatLong; + +__kernel void Fan1(__global float *m_dev, + __global float *a_dev, + __global float *b_dev, + const int size, + const int t) { + int globalId = get_global_id(0); + + if (globalId < size-1-t) { + *(m_dev + size * (globalId + t + 1)+t) = *(a_dev + size * (globalId + t + 1) + t) / *(a_dev + size * t + t); + } +} + + +__kernel void Fan2(__global float *m_dev, + __global float *a_dev, + __global float *b_dev, + const int size, + const int t) { + int globalId = get_global_id(0); + + int globalIdx = get_global_id(0); + int globalIdy = get_global_id(1); + if (globalIdx < size-1-t && globalIdy < size-t) { + a_dev[size*(globalIdx+1+t)+(globalIdy+t)] -= m_dev[size*(globalIdx+1+t)+t] * a_dev[size*t+(globalIdy+t)]; + + if(globalIdy == 0){ + b_dev[globalIdx+1+t] -= m_dev[size*(globalIdx+1+t)+(globalIdy+t)] * b_dev[t]; + } + } +// One dimensional +// int globalIdx = globalId % size; +// int globalIdy = globalId / size; +// +// if (globalIdx < size-1-t && globalIdy < size-t) { +// a_dev[size*(globalIdx+1+t)+(globalIdy+t)] -= m_dev[size*(globalIdx+1+t)+t] * a_dev[size*t+(globalIdy+t)]; +// } +// if(globalIdy == 0){ +// b_dev[globalIdx+1+t] -= m_dev[size*(globalIdx+1+t)+(globalIdy+t)] * b_dev[t]; +// } + +} diff --git a/benchmarks/new_opencl/guassian/kernel.pocl b/benchmarks/new_opencl/guassian/kernel.pocl new file mode 100644 index 0000000000000000000000000000000000000000..ed4240e2643e5b94085f9c8d4dac0c92dbf111b0 GIT binary patch literal 287484 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&platform, + &device)) { + printUsage(); + return 0; + } + + context = cl_init_context(platform, device, quiet); + + fp = fopen(filename, "r"); + fscanf(fp, "%d", &size); + + a = (float *)malloc(size * size * sizeof(float)); + + printf("OK\n"); + + InitMat(fp, size, a, size, size); + // printf("The input matrix a is:\n"); + // PrintMat(a, size, size, size); + b = (float *)malloc(size * sizeof(float)); + + InitAry(fp, b, size); + // printf("The input array b is:\n"); + // PrintAry(b, size); + + // create the solution matrix + m = (float *)malloc(size * size * sizeof(float)); + + // create a new vector to hold the final answer + finalVec = (float *)malloc(size * sizeof(float)); + + InitPerRun(size, m); + + // begin timing + + // run kernels + ForwardSub(context, a, b, m, size, timing); + + // end timing + if (!quiet) { + printf("The result of matrix m is: \n"); + + PrintMat(m, size, size, size); + printf("The result of matrix a is: \n"); + PrintMat(a, size, size, size); + printf("The result of array b is: \n"); + PrintAry(b, size); + + BackSub(a, b, finalVec, size); + printf("The final solution is: \n"); + PrintAry(finalVec, size); + } + + fclose(fp); + free(m); + free(a); + free(b); + free(finalVec); + // OpenClGaussianElimination(context,timing); + + return 0; +} + +/*------------------------------------------------------ + ** ForwardSub() -- Forward substitution of Gaussian + ** elimination. + **------------------------------------------------------ + */ +void ForwardSub(cl_context context, float *a, float *b, float *m, int size, + int timing) { + // 1. set up kernels + cl_kernel fan1_kernel, fan2_kernel; + cl_int status = 0; + cl_program gaussianElim_program; + cl_event writeEvent, kernelEvent, readEvent; + float writeTime = 0, readTime = 0, kernelTime = 0; + float writeMB = 0, readMB = 0; + + gaussianElim_program = cl_compileProgram((char *)"gaussianElim_kernels.cl", NULL); + + fan1_kernel = clCreateKernel(gaussianElim_program, "Fan1", &status); + status = cl_errChk(status, (char *)"Error Creating Fan1 kernel", true); + if (status) + exit(1); + + fan2_kernel = clCreateKernel(gaussianElim_program, "Fan2", &status); + status = cl_errChk(status, (char *)"Error Creating Fan2 kernel", true); + if (status) + exit(1); + + // 2. set up memory on device and send ipts data to device + + cl_mem a_dev, b_dev, m_dev; + + cl_int error = 0; + + a_dev = clCreateBuffer(context, CL_MEM_READ_WRITE, + sizeof(float) * size * size, NULL, &error); + + b_dev = clCreateBuffer(context, CL_MEM_READ_WRITE, sizeof(float) * size, NULL, + &error); + + m_dev = clCreateBuffer(context, CL_MEM_READ_WRITE, + sizeof(float) * size * size, NULL, &error); + + cl_command_queue command_queue = cl_getCommandQueue(); + + error = clEnqueueWriteBuffer(command_queue, a_dev, + 1, // change to 0 for nonblocking write + 0, // offset + sizeof(float) * size * size, a, 0, NULL, + &writeEvent); + + if (timing) + writeTime += eventTime(writeEvent, command_queue); + clReleaseEvent(writeEvent); + + error = clEnqueueWriteBuffer(command_queue, b_dev, + 1, // change to 0 for nonblocking write + 0, // offset + sizeof(float) * size, b, 0, NULL, &writeEvent); + if (timing) + writeTime += eventTime(writeEvent, command_queue); + clReleaseEvent(writeEvent); + + error = clEnqueueWriteBuffer(command_queue, m_dev, + 1, // change to 0 for nonblocking write + 0, // offset + sizeof(float) * size * size, m, 0, NULL, + &writeEvent); + if (timing) + writeTime += eventTime(writeEvent, command_queue); + clReleaseEvent(writeEvent); + writeMB = (float)(sizeof(float) * size * (size + size + 1) / 1e6); + + // 3. Determine block sizes + size_t globalWorksizeFan1[1]; + size_t globalWorksizeFan2[2]; + + globalWorksizeFan1[0] = size; + globalWorksizeFan2[0] = size; + globalWorksizeFan2[1] = size; + + int t; + // 4. Setup and Run kernels + for (t = 0; t < (size - 1); t++) { + // kernel args + cl_int argchk; + argchk = clSetKernelArg(fan1_kernel, 0, sizeof(cl_mem), (void *)&m_dev); + argchk |= clSetKernelArg(fan1_kernel, 1, sizeof(cl_mem), (void *)&a_dev); + argchk |= clSetKernelArg(fan1_kernel, 2, sizeof(cl_mem), (void *)&b_dev); + argchk |= clSetKernelArg(fan1_kernel, 3, sizeof(int), (void *)&size); + argchk |= clSetKernelArg(fan1_kernel, 4, sizeof(int), (void *)&t); + + cl_errChk(argchk, "ERROR in Setting Fan1 kernel args", true); + + // launch kernel + error = + clEnqueueNDRangeKernel(command_queue, fan1_kernel, 1, 0, + globalWorksizeFan1, NULL, 0, NULL, &kernelEvent); + + cl_errChk(error, "ERROR in Executing Fan1 Kernel", true); + if (timing) { + // printf("here1a\n"); + kernelTime += eventTime(kernelEvent, command_queue); + // printf("here1b\n"); + } + clReleaseEvent(kernelEvent); + // Fan1<<>>(m_cuda,a_cuda,Size,t); + // cudaThreadSynchronize(); + + // kernel args + argchk = clSetKernelArg(fan2_kernel, 0, sizeof(cl_mem), (void *)&m_dev); + argchk |= clSetKernelArg(fan2_kernel, 1, sizeof(cl_mem), (void *)&a_dev); + argchk |= clSetKernelArg(fan2_kernel, 2, sizeof(cl_mem), (void *)&b_dev); + argchk |= clSetKernelArg(fan2_kernel, 3, sizeof(int), (void *)&size); + argchk |= clSetKernelArg(fan2_kernel, 4, sizeof(int), (void *)&t); + + cl_errChk(argchk, "ERROR in Setting Fan2 kernel args", true); + + // launch kernel + error = + clEnqueueNDRangeKernel(command_queue, fan2_kernel, 2, 0, + globalWorksizeFan2, NULL, 0, NULL, &kernelEvent); + + cl_errChk(error, "ERROR in Executing Fan1 Kernel", true); + if (timing) { + // printf("here2a\n"); + kernelTime += eventTime(kernelEvent, command_queue); + // printf("here2b\n"); + } + clReleaseEvent(kernelEvent); + // Fan2<<>>(m_cuda,a_cuda,b_cuda,Size,Size-t,t); + // cudaThreadSynchronize(); + } + // 5. transfer data off of device + error = + clEnqueueReadBuffer(command_queue, a_dev, + 1, // change to 0 for nonblocking write + 0, // offset + sizeof(float) * size * size, a, 0, NULL, &readEvent); + + cl_errChk(error, "ERROR with clEnqueueReadBuffer", true); + if (timing) + readTime += eventTime(readEvent, command_queue); + clReleaseEvent(readEvent); + + error = clEnqueueReadBuffer(command_queue, b_dev, + 1, // change to 0 for nonblocking write + 0, // offset + sizeof(float) * size, b, 0, NULL, &readEvent); + cl_errChk(error, "ERROR with clEnqueueReadBuffer", true); + if (timing) + readTime += eventTime(readEvent, command_queue); + clReleaseEvent(readEvent); + + error = + clEnqueueReadBuffer(command_queue, m_dev, + 1, // change to 0 for nonblocking write + 0, // offset + sizeof(float) * size * size, m, 0, NULL, &readEvent); + + cl_errChk(error, "ERROR with clEnqueueReadBuffer", true); + if (timing) + readTime += eventTime(readEvent, command_queue); + clReleaseEvent(readEvent); + readMB = (float)(sizeof(float) * size * (size + size + 1) / 1e6); + + if (timing) { + printf("Matrix Size\tWrite(s) [size]\t\tKernel(s)\tRead(s) " + "[size]\t\tTotal(s)\n"); + printf("%dx%d \t", size, size); + + printf("%f [%.2fMB]\t", writeTime, writeMB); + + printf("%f\t", kernelTime); + + printf("%f [%.2fMB]\t", readTime, readMB); + + printf("%f\n\n", writeTime + kernelTime + readTime); + } +} + +float eventTime(cl_event event, cl_command_queue command_queue) { + cl_int error = 0; + cl_ulong eventStart, eventEnd; + clFinish(command_queue); + error = clGetEventProfilingInfo(event, CL_PROFILING_COMMAND_START, + sizeof(cl_ulong), &eventStart, NULL); + cl_errChk(error, "ERROR in Event Profiling.", true); + error = clGetEventProfilingInfo(event, CL_PROFILING_COMMAND_END, + sizeof(cl_ulong), &eventEnd, NULL); + cl_errChk(error, "ERROR in Event Profiling.", true); + + return (float)((eventEnd - eventStart) / 1e9); +} + +int parseCommandline(int argc, char *argv[], char *filename, int *q, int *t, + int *p, int *d) { + int i; + // if (argc < 2) return 1; // error + strncpy(filename, "matrix4.txt", 100); + char flag; + + for (i = 1; i < argc; i++) { + if (argv[i][0] == '-') { // flag + flag = argv[i][1]; + switch (flag) { + case 'h': // help + return 1; + break; + case 'q': // quiet + *q = 1; + break; + case 't': // timing + *t = 1; + break; + case 'p': // platform + i++; + *p = atoi(argv[i]); + break; + case 'd': // device + i++; + *d = atoi(argv[i]); + break; + } + } + } + if ((*d >= 0 && *p < 0) || + (*p >= 0 && + *d < 0)) // both p and d must be specified if either are specified + return 1; + return 0; +} + +void printUsage() { + printf("Gaussian Elimination Usage\n"); + printf("\n"); + printf("gaussianElimination [filename] [-hqt] [-p [int] -d [int]]\n"); + printf("\n"); + printf("example:\n"); + printf("$ ./gaussianElimination matrix4.txt\n"); + printf("\n"); + printf("filename the filename that holds the matrix data\n"); + printf("\n"); + printf("-h Display the help file\n"); + printf("-q Quiet mode. Suppress all text output.\n"); + printf("-t Print timing information.\n"); + printf("\n"); + printf("-p [int] Choose the platform (must choose both platform and " + "device)\n"); + printf("-d [int] Choose the device (must choose both platform and " + "device)\n"); + printf("\n"); + printf("\n"); + printf("Notes: 1. The filename is required as the first parameter.\n"); + printf(" 2. If you declare either the device or the platform,\n"); + printf(" you must declare both.\n\n"); +} + +/*------------------------------------------------------ + ** InitPerRun() -- Initialize the contents of the + ** multipier matrix **m + **------------------------------------------------------ + */ +void InitPerRun(int size, float *m) { + int i; + for (i = 0; i < size * size; i++) + *(m + i) = 0.0; +} +void BackSub(float *a, float *b, float *finalVec, int size) { + // solve "bottom up" + int i, j; + for (i = 0; i < size; i++) { + finalVec[size - i - 1] = b[size - i - 1]; + for (j = 0; j < i; j++) { + finalVec[size - i - 1] -= *(a + size * (size - i - 1) + (size - j - 1)) * + finalVec[size - j - 1]; + } + finalVec[size - i - 1] = + finalVec[size - i - 1] / *(a + size * (size - i - 1) + (size - i - 1)); + } +} +void InitMat(FILE *fp, int size, float *ary, int nrow, int ncol) { + int i, j; + + for (i = 0; i < nrow; i++) { + for (j = 0; j < ncol; j++) { + fscanf(fp, "%f", ary + size * i + j); + } + } +} +/*------------------------------------------------------ + ** InitAry() -- Initialize the array (vector) by reading + ** data from the data file + **------------------------------------------------------ + */ +void InitAry(FILE *fp, float *ary, int ary_size) { + int i; + + for (i = 0; i < ary_size; i++) { + fscanf(fp, "%f", &ary[i]); + } +} +/*------------------------------------------------------ + ** PrintMat() -- Print the contents of the matrix + **------------------------------------------------------ + */ +void PrintMat(float *ary, int size, int nrow, int ncol) { + int i, j; + + for (i = 0; i < nrow; i++) { + for (j = 0; j < ncol; j++) { + printf("%8.2f ", *(ary + size * i + j)); + } + printf("\n"); + } + printf("\n"); +} + +/*------------------------------------------------------ + ** PrintAry() -- Print the contents of the array (vector) + **------------------------------------------------------ + */ +void PrintAry(float *ary, int ary_size) { + int i; + for (i = 0; i < ary_size; i++) { + printf("%.2f ", ary[i]); + } + printf("\n\n"); +} +#endif diff --git a/benchmarks/new_opencl/guassian/matrix4.txt b/benchmarks/new_opencl/guassian/matrix4.txt new file mode 100755 index 00000000..abf30b49 --- /dev/null +++ b/benchmarks/new_opencl/guassian/matrix4.txt @@ -0,0 +1,11 @@ +4 + +-0.6 -0.5 0.7 0.3 +-0.3 -0.9 0.3 0.7 +-0.4 -0.5 -0.3 -0.8 +0.0 -0.1 0.2 0.9 + +-0.85 -0.68 0.24 -0.53 + +0.7 0.0 -0.4 -0.5 + diff --git a/benchmarks/new_opencl/guassian/run b/benchmarks/new_opencl/guassian/run new file mode 100755 index 00000000..31683b1b --- /dev/null +++ b/benchmarks/new_opencl/guassian/run @@ -0,0 +1 @@ +./gaussian ../../data/gaussian/matrix4.txt \ No newline at end of file diff --git a/benchmarks/new_opencl/guassian/utils.cpp b/benchmarks/new_opencl/guassian/utils.cpp new file mode 100755 index 00000000..b0f9115f --- /dev/null +++ b/benchmarks/new_opencl/guassian/utils.cpp @@ -0,0 +1,204 @@ +/****************************************************************************\ + * Copyright (c) 2011, Advanced Micro Devices, Inc. * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or without * + * modification, are permitted provided that the following conditions * + * are met: * + * * + * Redistributions of source code must retain the above copyright notice, * + * this list of conditions and the following disclaimer. * + * * + * Redistributions in binary form must reproduce the above copyright notice, * + * this list of conditions and the following disclaimer in the documentation * + * and/or other materials provided with the distribution. * + * * + * Neither the name of the copyright holder nor the names of its contributors * + * may be used to endorse or promote products derived from this software * + * without specific prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * + * * + * If you use the software (in whole or in part), you shall adhere to all * + * applicable U.S., European, and other export laws, including but not * + * limited to the U.S. Export Administration Regulations (“EAR”), (15 C.F.R. * + * Sections 730 through 774), and E.U. Council Regulation (EC) No 1334/2000 * + * of 22 June 2000. Further, pursuant to Section 740.6 of the EAR, you * + * hereby certify that, except pursuant to a license granted by the United * + * States Department of Commerce Bureau of Industry and Security or as * + * otherwise permitted pursuant to a License Exception under the U.S. Export * + * Administration Regulations ("EAR"), you will not (1) export, re-export or * + * release to a national of a country in Country Groups D:1, E:1 or E:2 any * + * restricted technology, software, or source code you receive hereunder, * + * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such * + * technology or software, if such foreign produced direct product is subject * + * to national security controls as identified on the Commerce Control List * + *(currently found in Supplement 1 to Part 774 of EAR). For the most current * + * Country Group listings, or for additional information about the EAR or * + * your obligations under those regulations, please refer to the U.S. Bureau * + * of Industry and Security’s website at http://www.bis.doc.gov/. * + \****************************************************************************/ + +#include +#include +#include +#include + +#include "utils.h" + +static bool usingImages = true; + +//! A wrapper for malloc that checks the return value +void* alloc(size_t size) { + + void* ptr = NULL; + ptr = malloc(size); + if(ptr == NULL) { + perror("malloc"); + exit(-1); + } + + return ptr; +} + +// This function checks to make sure a file exists before we open it +void checkFile(char* filename) +{ + + struct stat fileStatus; + if(stat(filename, &fileStatus) != 0) { + printf("Error opening file: %s\n", filename); + exit(-1); + } + else { + if(!(S_IFREG & fileStatus.st_mode)) { + printf("File %s is not a regular file\n", filename); + exit(-1); + } + } +} + + +// This function checks to make sure a directory exists +void checkDir(char* dirpath) +{ + + struct stat fileStatus; + if(stat(dirpath, &fileStatus) != 0) { + printf("Directory does not exist: %s\n", dirpath); + exit(-1); + } + else { + if(!(S_IFDIR & fileStatus.st_mode)) { + printf("Directory was not provided: %s\n", dirpath); + exit(-1); + } + } +} + +// Parse the command line arguments +void parseArguments(int argc, char** argv, char** input, char** events, + char** ipts, char* devicePref, bool* verifyResults) +{ + + for(int i = 2; i < argc; i++) { + if(strcmp(argv[i], "-d") == 0) { // Event dump found + if(i == argc-1) { + printf("Usage: -e Needs directory path\n"); + exit(-1); + } + devicePref[0] = argv[i+1][0]; + i++; + continue; + } + if(strcmp(argv[i], "-e") == 0) { // Event dump found + if(i == argc-1) { + printf("Usage: -e Needs directory path\n"); + exit(-1); + } + *events = argv[i+1]; + i++; + continue; + } + if(strcmp(argv[i], "-i") == 0) { // Input found + if(i == argc-1) { + printf("Usage: -i Needs directory path\n"); + exit(-1); + } + *input = argv[i+1]; + i++; + continue; + } + if(strcmp(argv[i], "-l") == 0) { // Ipts dump found + if(i == argc-1) { + printf("Usage: -l Needs directory path\n"); + exit(-1); + } + *ipts = argv[i+1]; + i++; + continue; + } + if(strcmp(argv[i], "-n") == 0) { // Don't use OpenCL images + setUsingImages(false); + continue; + } + if(strcmp(argv[i], "-v") == 0) { // Verify results + *verifyResults = true; + continue; + } + } +} + + +// This function that takes a positive integer 'value' and returns +// the nearest multiple of 'multiple' (used for padding columns) +unsigned int roundUp(unsigned int value, unsigned int multiple) { + + unsigned int remainder = value % multiple; + + // Make the value a multiple of multiple + if(remainder != 0) { + value += (multiple-remainder); + } + + return value; +} + + +// Concatenate two strings and return a pointer to the new string +char* smartStrcat(char* str1, char* str2) +{ + char* newStr = NULL; + + newStr = (char*)alloc((strlen(str1)+strlen(str2)+1)*sizeof(char)); + + strcpy(newStr, str1); + strcat(newStr, str2); + + return newStr; +} + + +// Set the value of using images to true if they are being +// used, or false if they are not +void setUsingImages(bool val) +{ + usingImages = val; +} + + +// Return whether or not images are being used +bool isUsingImages() +{ + return usingImages; +} diff --git a/benchmarks/new_opencl/guassian/utils.h b/benchmarks/new_opencl/guassian/utils.h new file mode 100755 index 00000000..1e901ced --- /dev/null +++ b/benchmarks/new_opencl/guassian/utils.h @@ -0,0 +1,84 @@ +/****************************************************************************\ + * Copyright (c) 2011, Advanced Micro Devices, Inc. * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or without * + * modification, are permitted provided that the following conditions * + * are met: * + * * + * Redistributions of source code must retain the above copyright notice, * + * this list of conditions and the following disclaimer. * + * * + * Redistributions in binary form must reproduce the above copyright notice, * + * this list of conditions and the following disclaimer in the documentation * + * and/or other materials provided with the distribution. * + * * + * Neither the name of the copyright holder nor the names of its contributors * + * may be used to endorse or promote products derived from this software * + * without specific prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * + * * + * If you use the software (in whole or in part), you shall adhere to all * + * applicable U.S., European, and other export laws, including but not * + * limited to the U.S. Export Administration Regulations (“EAR”), (15 C.F.R. * + * Sections 730 through 774), and E.U. Council Regulation (EC) No 1334/2000 * + * of 22 June 2000. Further, pursuant to Section 740.6 of the EAR, you * + * hereby certify that, except pursuant to a license granted by the United * + * States Department of Commerce Bureau of Industry and Security or as * + * otherwise permitted pursuant to a License Exception under the U.S. Export * + * Administration Regulations ("EAR"), you will not (1) export, re-export or * + * release to a national of a country in Country Groups D:1, E:1 or E:2 any * + * restricted technology, software, or source code you receive hereunder, * + * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such * + * technology or software, if such foreign produced direct product is subject * + * to national security controls as identified on the Commerce Control List * + *(currently found in Supplement 1 to Part 774 of EAR). For the most current * + * Country Group listings, or for additional information about the EAR or * + * your obligations under those regulations, please refer to the U.S. Bureau * + * of Industry and Security’s website at http://www.bis.doc.gov/. * + \****************************************************************************/ + +#ifndef _UTILS_ +#define _UTILS_ + +// Wrapper for malloc +void* alloc(size_t size); + +// Checks for existence of directory +void checkDir(char* dirpath); + +// Check for existence of file +void checkFile(char* filename); + +// Parse the input command line options to the program +void parseArguments(int argc, char** argv, char** input, char** events, + char** ipts, char* devicePref, bool* verifyResults); + + +// Print the program usage information +void printUsage(); + +// Rounds up size to the nearest multiple of multiple +unsigned int roundUp(unsigned int value, unsigned int multiple); + +// Concatenate two strings, creating a new one +char* smartStrcat(char* str1, char* str2); + +// Set the value of usingImages +void setUsingImages(bool val); + +// Return whether or not images are being used +bool isUsingImages(); + +#endif diff --git a/benchmarks/new_opencl/include/CL/cl.h b/benchmarks/new_opencl/include/CL/cl.h new file mode 100644 index 00000000..32ae73fc --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl.h @@ -0,0 +1,1804 @@ +/******************************************************************************* + * Copyright (c) 2008-2019 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + ******************************************************************************/ + +#ifndef __OPENCL_CL_H +#define __OPENCL_CL_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ + +typedef struct _cl_platform_id * cl_platform_id; +typedef struct _cl_device_id * cl_device_id; +typedef struct _cl_context * cl_context; +typedef struct _cl_command_queue * cl_command_queue; +typedef struct _cl_mem * cl_mem; +typedef struct _cl_program * cl_program; +typedef struct _cl_kernel * cl_kernel; +typedef struct _cl_event * cl_event; +typedef struct _cl_sampler * cl_sampler; + +typedef cl_uint cl_bool; /* WARNING! Unlike cl_ types in cl_platform.h, cl_bool is not guaranteed to be the same size as the bool in kernels. */ +typedef cl_ulong cl_bitfield; +typedef cl_bitfield cl_device_type; +typedef cl_uint cl_platform_info; +typedef cl_uint cl_device_info; +typedef cl_bitfield cl_device_fp_config; +typedef cl_uint cl_device_mem_cache_type; +typedef cl_uint cl_device_local_mem_type; +typedef cl_bitfield cl_device_exec_capabilities; +#ifdef CL_VERSION_2_0 +typedef cl_bitfield cl_device_svm_capabilities; +#endif +typedef cl_bitfield cl_command_queue_properties; +#ifdef CL_VERSION_1_2 +typedef intptr_t cl_device_partition_property; +typedef cl_bitfield cl_device_affinity_domain; +#endif + +typedef intptr_t cl_context_properties; +typedef cl_uint cl_context_info; +#ifdef CL_VERSION_2_0 +typedef cl_bitfield cl_queue_properties; +#endif +typedef cl_uint cl_command_queue_info; +typedef cl_uint cl_channel_order; +typedef cl_uint cl_channel_type; +typedef cl_bitfield cl_mem_flags; +#ifdef CL_VERSION_2_0 +typedef cl_bitfield cl_svm_mem_flags; +#endif +typedef cl_uint cl_mem_object_type; +typedef cl_uint cl_mem_info; +#ifdef CL_VERSION_1_2 +typedef cl_bitfield cl_mem_migration_flags; +#endif +typedef cl_uint cl_image_info; +#ifdef CL_VERSION_1_1 +typedef cl_uint cl_buffer_create_type; +#endif +typedef cl_uint cl_addressing_mode; +typedef cl_uint cl_filter_mode; +typedef cl_uint cl_sampler_info; +typedef cl_bitfield cl_map_flags; +#ifdef CL_VERSION_2_0 +typedef intptr_t cl_pipe_properties; +typedef cl_uint cl_pipe_info; +#endif +typedef cl_uint cl_program_info; +typedef cl_uint cl_program_build_info; +#ifdef CL_VERSION_1_2 +typedef cl_uint cl_program_binary_type; +#endif +typedef cl_int cl_build_status; +typedef cl_uint cl_kernel_info; +#ifdef CL_VERSION_1_2 +typedef cl_uint cl_kernel_arg_info; +typedef cl_uint cl_kernel_arg_address_qualifier; +typedef cl_uint cl_kernel_arg_access_qualifier; +typedef cl_bitfield cl_kernel_arg_type_qualifier; +#endif +typedef cl_uint cl_kernel_work_group_info; +#ifdef CL_VERSION_2_1 +typedef cl_uint cl_kernel_sub_group_info; +#endif +typedef cl_uint cl_event_info; +typedef cl_uint cl_command_type; +typedef cl_uint cl_profiling_info; +#ifdef CL_VERSION_2_0 +typedef cl_bitfield cl_sampler_properties; +typedef cl_uint cl_kernel_exec_info; +#endif + +typedef struct _cl_image_format { + cl_channel_order image_channel_order; + cl_channel_type image_channel_data_type; +} cl_image_format; + +#ifdef CL_VERSION_1_2 + +typedef struct _cl_image_desc { + cl_mem_object_type image_type; + size_t image_width; + size_t image_height; + size_t image_depth; + size_t image_array_size; + size_t image_row_pitch; + size_t image_slice_pitch; + cl_uint num_mip_levels; + cl_uint num_samples; +#ifdef CL_VERSION_2_0 +#ifdef __GNUC__ + __extension__ /* Prevents warnings about anonymous union in -pedantic builds */ +#endif +#ifdef _MSC_VER +#pragma warning( push ) +#pragma warning( disable : 4201 ) /* Prevents warning about nameless struct/union in /W4 /Za builds */ +#endif + union { +#endif + cl_mem buffer; +#ifdef CL_VERSION_2_0 + cl_mem mem_object; + }; +#ifdef _MSC_VER +#pragma warning( pop ) +#endif +#endif +} cl_image_desc; + +#endif + +#ifdef CL_VERSION_1_1 + +typedef struct _cl_buffer_region { + size_t origin; + size_t size; +} cl_buffer_region; + +#endif + +/******************************************************************************/ + +/* Error Codes */ +#define CL_SUCCESS 0 +#define CL_DEVICE_NOT_FOUND -1 +#define CL_DEVICE_NOT_AVAILABLE -2 +#define CL_COMPILER_NOT_AVAILABLE -3 +#define CL_MEM_OBJECT_ALLOCATION_FAILURE -4 +#define CL_OUT_OF_RESOURCES -5 +#define CL_OUT_OF_HOST_MEMORY -6 +#define CL_PROFILING_INFO_NOT_AVAILABLE -7 +#define CL_MEM_COPY_OVERLAP -8 +#define CL_IMAGE_FORMAT_MISMATCH -9 +#define CL_IMAGE_FORMAT_NOT_SUPPORTED -10 +#define CL_BUILD_PROGRAM_FAILURE -11 +#define CL_MAP_FAILURE -12 +#ifdef CL_VERSION_1_1 +#define CL_MISALIGNED_SUB_BUFFER_OFFSET -13 +#define CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST -14 +#endif +#ifdef CL_VERSION_1_2 +#define CL_COMPILE_PROGRAM_FAILURE -15 +#define CL_LINKER_NOT_AVAILABLE -16 +#define CL_LINK_PROGRAM_FAILURE -17 +#define CL_DEVICE_PARTITION_FAILED -18 +#define CL_KERNEL_ARG_INFO_NOT_AVAILABLE -19 +#endif + +#define CL_INVALID_VALUE -30 +#define CL_INVALID_DEVICE_TYPE -31 +#define CL_INVALID_PLATFORM -32 +#define CL_INVALID_DEVICE -33 +#define CL_INVALID_CONTEXT -34 +#define CL_INVALID_QUEUE_PROPERTIES -35 +#define CL_INVALID_COMMAND_QUEUE -36 +#define CL_INVALID_HOST_PTR -37 +#define CL_INVALID_MEM_OBJECT -38 +#define CL_INVALID_IMAGE_FORMAT_DESCRIPTOR -39 +#define CL_INVALID_IMAGE_SIZE -40 +#define CL_INVALID_SAMPLER -41 +#define CL_INVALID_BINARY -42 +#define CL_INVALID_BUILD_OPTIONS -43 +#define CL_INVALID_PROGRAM -44 +#define CL_INVALID_PROGRAM_EXECUTABLE -45 +#define CL_INVALID_KERNEL_NAME -46 +#define CL_INVALID_KERNEL_DEFINITION -47 +#define CL_INVALID_KERNEL -48 +#define CL_INVALID_ARG_INDEX -49 +#define CL_INVALID_ARG_VALUE -50 +#define CL_INVALID_ARG_SIZE -51 +#define CL_INVALID_KERNEL_ARGS -52 +#define CL_INVALID_WORK_DIMENSION -53 +#define CL_INVALID_WORK_GROUP_SIZE -54 +#define CL_INVALID_WORK_ITEM_SIZE -55 +#define CL_INVALID_GLOBAL_OFFSET -56 +#define CL_INVALID_EVENT_WAIT_LIST -57 +#define CL_INVALID_EVENT -58 +#define CL_INVALID_OPERATION -59 +#define CL_INVALID_GL_OBJECT -60 +#define CL_INVALID_BUFFER_SIZE -61 +#define CL_INVALID_MIP_LEVEL -62 +#define CL_INVALID_GLOBAL_WORK_SIZE -63 +#ifdef CL_VERSION_1_1 +#define CL_INVALID_PROPERTY -64 +#endif +#ifdef CL_VERSION_1_2 +#define CL_INVALID_IMAGE_DESCRIPTOR -65 +#define CL_INVALID_COMPILER_OPTIONS -66 +#define CL_INVALID_LINKER_OPTIONS -67 +#define CL_INVALID_DEVICE_PARTITION_COUNT -68 +#endif +#ifdef CL_VERSION_2_0 +#define CL_INVALID_PIPE_SIZE -69 +#define CL_INVALID_DEVICE_QUEUE -70 +#endif +#ifdef CL_VERSION_2_2 +#define CL_INVALID_SPEC_ID -71 +#define CL_MAX_SIZE_RESTRICTION_EXCEEDED -72 +#endif + + +/* cl_bool */ +#define CL_FALSE 0 +#define CL_TRUE 1 +#ifdef CL_VERSION_1_2 +#define CL_BLOCKING CL_TRUE +#define CL_NON_BLOCKING CL_FALSE +#endif + +/* cl_platform_info */ +#define CL_PLATFORM_PROFILE 0x0900 +#define CL_PLATFORM_VERSION 0x0901 +#define CL_PLATFORM_NAME 0x0902 +#define CL_PLATFORM_VENDOR 0x0903 +#define CL_PLATFORM_EXTENSIONS 0x0904 +#ifdef CL_VERSION_2_1 +#define CL_PLATFORM_HOST_TIMER_RESOLUTION 0x0905 +#endif + +/* cl_device_type - bitfield */ +#define CL_DEVICE_TYPE_DEFAULT (1 << 0) +#define CL_DEVICE_TYPE_CPU (1 << 1) +#define CL_DEVICE_TYPE_GPU (1 << 2) +#define CL_DEVICE_TYPE_ACCELERATOR (1 << 3) +#ifdef CL_VERSION_1_2 +#define CL_DEVICE_TYPE_CUSTOM (1 << 4) +#endif +#define CL_DEVICE_TYPE_ALL 0xFFFFFFFF + +/* cl_device_info */ +#define CL_DEVICE_TYPE 0x1000 +#define CL_DEVICE_VENDOR_ID 0x1001 +#define CL_DEVICE_MAX_COMPUTE_UNITS 0x1002 +#define CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS 0x1003 +#define CL_DEVICE_MAX_WORK_GROUP_SIZE 0x1004 +#define CL_DEVICE_MAX_WORK_ITEM_SIZES 0x1005 +#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR 0x1006 +#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT 0x1007 +#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT 0x1008 +#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG 0x1009 +#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT 0x100A +#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE 0x100B +#define CL_DEVICE_MAX_CLOCK_FREQUENCY 0x100C +#define CL_DEVICE_ADDRESS_BITS 0x100D +#define CL_DEVICE_MAX_READ_IMAGE_ARGS 0x100E +#define CL_DEVICE_MAX_WRITE_IMAGE_ARGS 0x100F +#define CL_DEVICE_MAX_MEM_ALLOC_SIZE 0x1010 +#define CL_DEVICE_IMAGE2D_MAX_WIDTH 0x1011 +#define CL_DEVICE_IMAGE2D_MAX_HEIGHT 0x1012 +#define CL_DEVICE_IMAGE3D_MAX_WIDTH 0x1013 +#define CL_DEVICE_IMAGE3D_MAX_HEIGHT 0x1014 +#define CL_DEVICE_IMAGE3D_MAX_DEPTH 0x1015 +#define CL_DEVICE_IMAGE_SUPPORT 0x1016 +#define CL_DEVICE_MAX_PARAMETER_SIZE 0x1017 +#define CL_DEVICE_MAX_SAMPLERS 0x1018 +#define CL_DEVICE_MEM_BASE_ADDR_ALIGN 0x1019 +#define CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE 0x101A +#define CL_DEVICE_SINGLE_FP_CONFIG 0x101B +#define CL_DEVICE_GLOBAL_MEM_CACHE_TYPE 0x101C +#define CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE 0x101D +#define CL_DEVICE_GLOBAL_MEM_CACHE_SIZE 0x101E +#define CL_DEVICE_GLOBAL_MEM_SIZE 0x101F +#define CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE 0x1020 +#define CL_DEVICE_MAX_CONSTANT_ARGS 0x1021 +#define CL_DEVICE_LOCAL_MEM_TYPE 0x1022 +#define CL_DEVICE_LOCAL_MEM_SIZE 0x1023 +#define CL_DEVICE_ERROR_CORRECTION_SUPPORT 0x1024 +#define CL_DEVICE_PROFILING_TIMER_RESOLUTION 0x1025 +#define CL_DEVICE_ENDIAN_LITTLE 0x1026 +#define CL_DEVICE_AVAILABLE 0x1027 +#define CL_DEVICE_COMPILER_AVAILABLE 0x1028 +#define CL_DEVICE_EXECUTION_CAPABILITIES 0x1029 +#define CL_DEVICE_QUEUE_PROPERTIES 0x102A /* deprecated */ +#ifdef CL_VERSION_2_0 +#define CL_DEVICE_QUEUE_ON_HOST_PROPERTIES 0x102A +#endif +#define CL_DEVICE_NAME 0x102B +#define CL_DEVICE_VENDOR 0x102C +#define CL_DRIVER_VERSION 0x102D +#define CL_DEVICE_PROFILE 0x102E +#define CL_DEVICE_VERSION 0x102F +#define CL_DEVICE_EXTENSIONS 0x1030 +#define CL_DEVICE_PLATFORM 0x1031 +#ifdef CL_VERSION_1_2 +#define CL_DEVICE_DOUBLE_FP_CONFIG 0x1032 +#endif +/* 0x1033 reserved for CL_DEVICE_HALF_FP_CONFIG which is already defined in "cl_ext.h" */ +#ifdef CL_VERSION_1_1 +#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF 0x1034 +#define CL_DEVICE_HOST_UNIFIED_MEMORY 0x1035 /* deprecated */ +#define CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR 0x1036 +#define CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT 0x1037 +#define CL_DEVICE_NATIVE_VECTOR_WIDTH_INT 0x1038 +#define CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG 0x1039 +#define CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT 0x103A +#define CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE 0x103B +#define CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF 0x103C +#define CL_DEVICE_OPENCL_C_VERSION 0x103D +#endif +#ifdef CL_VERSION_1_2 +#define CL_DEVICE_LINKER_AVAILABLE 0x103E +#define CL_DEVICE_BUILT_IN_KERNELS 0x103F +#define CL_DEVICE_IMAGE_MAX_BUFFER_SIZE 0x1040 +#define CL_DEVICE_IMAGE_MAX_ARRAY_SIZE 0x1041 +#define CL_DEVICE_PARENT_DEVICE 0x1042 +#define CL_DEVICE_PARTITION_MAX_SUB_DEVICES 0x1043 +#define CL_DEVICE_PARTITION_PROPERTIES 0x1044 +#define CL_DEVICE_PARTITION_AFFINITY_DOMAIN 0x1045 +#define CL_DEVICE_PARTITION_TYPE 0x1046 +#define CL_DEVICE_REFERENCE_COUNT 0x1047 +#define CL_DEVICE_PREFERRED_INTEROP_USER_SYNC 0x1048 +#define CL_DEVICE_PRINTF_BUFFER_SIZE 0x1049 +#endif +#ifdef CL_VERSION_2_0 +#define CL_DEVICE_IMAGE_PITCH_ALIGNMENT 0x104A +#define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT 0x104B +#define CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS 0x104C +#define CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE 0x104D +#define CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES 0x104E +#define CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE 0x104F +#define CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE 0x1050 +#define CL_DEVICE_MAX_ON_DEVICE_QUEUES 0x1051 +#define CL_DEVICE_MAX_ON_DEVICE_EVENTS 0x1052 +#define CL_DEVICE_SVM_CAPABILITIES 0x1053 +#define CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE 0x1054 +#define CL_DEVICE_MAX_PIPE_ARGS 0x1055 +#define CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS 0x1056 +#define CL_DEVICE_PIPE_MAX_PACKET_SIZE 0x1057 +#define CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT 0x1058 +#define CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT 0x1059 +#define CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT 0x105A +#endif +#ifdef CL_VERSION_2_1 +#define CL_DEVICE_IL_VERSION 0x105B +#define CL_DEVICE_MAX_NUM_SUB_GROUPS 0x105C +#define CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS 0x105D +#endif + +/* cl_device_fp_config - bitfield */ +#define CL_FP_DENORM (1 << 0) +#define CL_FP_INF_NAN (1 << 1) +#define CL_FP_ROUND_TO_NEAREST (1 << 2) +#define CL_FP_ROUND_TO_ZERO (1 << 3) +#define CL_FP_ROUND_TO_INF (1 << 4) +#define CL_FP_FMA (1 << 5) +#ifdef CL_VERSION_1_1 +#define CL_FP_SOFT_FLOAT (1 << 6) +#endif +#ifdef CL_VERSION_1_2 +#define CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT (1 << 7) +#endif + +/* cl_device_mem_cache_type */ +#define CL_NONE 0x0 +#define CL_READ_ONLY_CACHE 0x1 +#define CL_READ_WRITE_CACHE 0x2 + +/* cl_device_local_mem_type */ +#define CL_LOCAL 0x1 +#define CL_GLOBAL 0x2 + +/* cl_device_exec_capabilities - bitfield */ +#define CL_EXEC_KERNEL (1 << 0) +#define CL_EXEC_NATIVE_KERNEL (1 << 1) + +/* cl_command_queue_properties - bitfield */ +#define CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE (1 << 0) +#define CL_QUEUE_PROFILING_ENABLE (1 << 1) +#ifdef CL_VERSION_2_0 +#define CL_QUEUE_ON_DEVICE (1 << 2) +#define CL_QUEUE_ON_DEVICE_DEFAULT (1 << 3) +#endif + +/* cl_context_info */ +#define CL_CONTEXT_REFERENCE_COUNT 0x1080 +#define CL_CONTEXT_DEVICES 0x1081 +#define CL_CONTEXT_PROPERTIES 0x1082 +#ifdef CL_VERSION_1_1 +#define CL_CONTEXT_NUM_DEVICES 0x1083 +#endif + +/* cl_context_properties */ +#define CL_CONTEXT_PLATFORM 0x1084 +#ifdef CL_VERSION_1_2 +#define CL_CONTEXT_INTEROP_USER_SYNC 0x1085 +#endif + +#ifdef CL_VERSION_1_2 + +/* cl_device_partition_property */ +#define CL_DEVICE_PARTITION_EQUALLY 0x1086 +#define CL_DEVICE_PARTITION_BY_COUNTS 0x1087 +#define CL_DEVICE_PARTITION_BY_COUNTS_LIST_END 0x0 +#define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN 0x1088 + +#endif + +#ifdef CL_VERSION_1_2 + +/* cl_device_affinity_domain */ +#define CL_DEVICE_AFFINITY_DOMAIN_NUMA (1 << 0) +#define CL_DEVICE_AFFINITY_DOMAIN_L4_CACHE (1 << 1) +#define CL_DEVICE_AFFINITY_DOMAIN_L3_CACHE (1 << 2) +#define CL_DEVICE_AFFINITY_DOMAIN_L2_CACHE (1 << 3) +#define CL_DEVICE_AFFINITY_DOMAIN_L1_CACHE (1 << 4) +#define CL_DEVICE_AFFINITY_DOMAIN_NEXT_PARTITIONABLE (1 << 5) + +#endif + +#ifdef CL_VERSION_2_0 + +/* cl_device_svm_capabilities */ +#define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER (1 << 0) +#define CL_DEVICE_SVM_FINE_GRAIN_BUFFER (1 << 1) +#define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM (1 << 2) +#define CL_DEVICE_SVM_ATOMICS (1 << 3) + +#endif + +/* cl_command_queue_info */ +#define CL_QUEUE_CONTEXT 0x1090 +#define CL_QUEUE_DEVICE 0x1091 +#define CL_QUEUE_REFERENCE_COUNT 0x1092 +#define CL_QUEUE_PROPERTIES 0x1093 +#ifdef CL_VERSION_2_0 +#define CL_QUEUE_SIZE 0x1094 +#endif +#ifdef CL_VERSION_2_1 +#define CL_QUEUE_DEVICE_DEFAULT 0x1095 +#endif + +/* cl_mem_flags and cl_svm_mem_flags - bitfield */ +#define CL_MEM_READ_WRITE (1 << 0) +#define CL_MEM_WRITE_ONLY (1 << 1) +#define CL_MEM_READ_ONLY (1 << 2) +#define CL_MEM_USE_HOST_PTR (1 << 3) +#define CL_MEM_ALLOC_HOST_PTR (1 << 4) +#define CL_MEM_COPY_HOST_PTR (1 << 5) +/* reserved (1 << 6) */ +#ifdef CL_VERSION_1_2 +#define CL_MEM_HOST_WRITE_ONLY (1 << 7) +#define CL_MEM_HOST_READ_ONLY (1 << 8) +#define CL_MEM_HOST_NO_ACCESS (1 << 9) +#endif +#ifdef CL_VERSION_2_0 +#define CL_MEM_SVM_FINE_GRAIN_BUFFER (1 << 10) /* used by cl_svm_mem_flags only */ +#define CL_MEM_SVM_ATOMICS (1 << 11) /* used by cl_svm_mem_flags only */ +#define CL_MEM_KERNEL_READ_AND_WRITE (1 << 12) +#endif + +#ifdef CL_VERSION_1_2 + +/* cl_mem_migration_flags - bitfield */ +#define CL_MIGRATE_MEM_OBJECT_HOST (1 << 0) +#define CL_MIGRATE_MEM_OBJECT_CONTENT_UNDEFINED (1 << 1) + +#endif + +/* cl_channel_order */ +#define CL_R 0x10B0 +#define CL_A 0x10B1 +#define CL_RG 0x10B2 +#define CL_RA 0x10B3 +#define CL_RGB 0x10B4 +#define CL_RGBA 0x10B5 +#define CL_BGRA 0x10B6 +#define CL_ARGB 0x10B7 +#define CL_INTENSITY 0x10B8 +#define CL_LUMINANCE 0x10B9 +#ifdef CL_VERSION_1_1 +#define CL_Rx 0x10BA +#define CL_RGx 0x10BB +#define CL_RGBx 0x10BC +#endif +#ifdef CL_VERSION_1_2 +#define CL_DEPTH 0x10BD +#define CL_DEPTH_STENCIL 0x10BE +#endif +#ifdef CL_VERSION_2_0 +#define CL_sRGB 0x10BF +#define CL_sRGBx 0x10C0 +#define CL_sRGBA 0x10C1 +#define CL_sBGRA 0x10C2 +#define CL_ABGR 0x10C3 +#endif + +/* cl_channel_type */ +#define CL_SNORM_INT8 0x10D0 +#define CL_SNORM_INT16 0x10D1 +#define CL_UNORM_INT8 0x10D2 +#define CL_UNORM_INT16 0x10D3 +#define CL_UNORM_SHORT_565 0x10D4 +#define CL_UNORM_SHORT_555 0x10D5 +#define CL_UNORM_INT_101010 0x10D6 +#define CL_SIGNED_INT8 0x10D7 +#define CL_SIGNED_INT16 0x10D8 +#define CL_SIGNED_INT32 0x10D9 +#define CL_UNSIGNED_INT8 0x10DA +#define CL_UNSIGNED_INT16 0x10DB +#define CL_UNSIGNED_INT32 0x10DC +#define CL_HALF_FLOAT 0x10DD +#define CL_FLOAT 0x10DE +#ifdef CL_VERSION_1_2 +#define CL_UNORM_INT24 0x10DF +#endif +#ifdef CL_VERSION_2_1 +#define CL_UNORM_INT_101010_2 0x10E0 +#endif + +/* cl_mem_object_type */ +#define CL_MEM_OBJECT_BUFFER 0x10F0 +#define CL_MEM_OBJECT_IMAGE2D 0x10F1 +#define CL_MEM_OBJECT_IMAGE3D 0x10F2 +#ifdef CL_VERSION_1_2 +#define CL_MEM_OBJECT_IMAGE2D_ARRAY 0x10F3 +#define CL_MEM_OBJECT_IMAGE1D 0x10F4 +#define CL_MEM_OBJECT_IMAGE1D_ARRAY 0x10F5 +#define CL_MEM_OBJECT_IMAGE1D_BUFFER 0x10F6 +#endif +#ifdef CL_VERSION_2_0 +#define CL_MEM_OBJECT_PIPE 0x10F7 +#endif + +/* cl_mem_info */ +#define CL_MEM_TYPE 0x1100 +#define CL_MEM_FLAGS 0x1101 +#define CL_MEM_SIZE 0x1102 +#define CL_MEM_HOST_PTR 0x1103 +#define CL_MEM_MAP_COUNT 0x1104 +#define CL_MEM_REFERENCE_COUNT 0x1105 +#define CL_MEM_CONTEXT 0x1106 +#ifdef CL_VERSION_1_1 +#define CL_MEM_ASSOCIATED_MEMOBJECT 0x1107 +#define CL_MEM_OFFSET 0x1108 +#endif +#ifdef CL_VERSION_2_0 +#define CL_MEM_USES_SVM_POINTER 0x1109 +#endif + +/* cl_image_info */ +#define CL_IMAGE_FORMAT 0x1110 +#define CL_IMAGE_ELEMENT_SIZE 0x1111 +#define CL_IMAGE_ROW_PITCH 0x1112 +#define CL_IMAGE_SLICE_PITCH 0x1113 +#define CL_IMAGE_WIDTH 0x1114 +#define CL_IMAGE_HEIGHT 0x1115 +#define CL_IMAGE_DEPTH 0x1116 +#ifdef CL_VERSION_1_2 +#define CL_IMAGE_ARRAY_SIZE 0x1117 +#define CL_IMAGE_BUFFER 0x1118 +#define CL_IMAGE_NUM_MIP_LEVELS 0x1119 +#define CL_IMAGE_NUM_SAMPLES 0x111A +#endif + +#ifdef CL_VERSION_2_0 + +/* cl_pipe_info */ +#define CL_PIPE_PACKET_SIZE 0x1120 +#define CL_PIPE_MAX_PACKETS 0x1121 + +#endif + +/* cl_addressing_mode */ +#define CL_ADDRESS_NONE 0x1130 +#define CL_ADDRESS_CLAMP_TO_EDGE 0x1131 +#define CL_ADDRESS_CLAMP 0x1132 +#define CL_ADDRESS_REPEAT 0x1133 +#ifdef CL_VERSION_1_1 +#define CL_ADDRESS_MIRRORED_REPEAT 0x1134 +#endif + +/* cl_filter_mode */ +#define CL_FILTER_NEAREST 0x1140 +#define CL_FILTER_LINEAR 0x1141 + +/* cl_sampler_info */ +#define CL_SAMPLER_REFERENCE_COUNT 0x1150 +#define CL_SAMPLER_CONTEXT 0x1151 +#define CL_SAMPLER_NORMALIZED_COORDS 0x1152 +#define CL_SAMPLER_ADDRESSING_MODE 0x1153 +#define CL_SAMPLER_FILTER_MODE 0x1154 +#ifdef CL_VERSION_2_0 +/* These enumerants are for the cl_khr_mipmap_image extension. + They have since been added to cl_ext.h with an appropriate + KHR suffix, but are left here for backwards compatibility. */ +#define CL_SAMPLER_MIP_FILTER_MODE 0x1155 +#define CL_SAMPLER_LOD_MIN 0x1156 +#define CL_SAMPLER_LOD_MAX 0x1157 +#endif + +/* cl_map_flags - bitfield */ +#define CL_MAP_READ (1 << 0) +#define CL_MAP_WRITE (1 << 1) +#ifdef CL_VERSION_1_2 +#define CL_MAP_WRITE_INVALIDATE_REGION (1 << 2) +#endif + +/* cl_program_info */ +#define CL_PROGRAM_REFERENCE_COUNT 0x1160 +#define CL_PROGRAM_CONTEXT 0x1161 +#define CL_PROGRAM_NUM_DEVICES 0x1162 +#define CL_PROGRAM_DEVICES 0x1163 +#define CL_PROGRAM_SOURCE 0x1164 +#define CL_PROGRAM_BINARY_SIZES 0x1165 +#define CL_PROGRAM_BINARIES 0x1166 +#ifdef CL_VERSION_1_2 +#define CL_PROGRAM_NUM_KERNELS 0x1167 +#define CL_PROGRAM_KERNEL_NAMES 0x1168 +#endif +#ifdef CL_VERSION_2_1 +#define CL_PROGRAM_IL 0x1169 +#endif +#ifdef CL_VERSION_2_2 +#define CL_PROGRAM_SCOPE_GLOBAL_CTORS_PRESENT 0x116A +#define CL_PROGRAM_SCOPE_GLOBAL_DTORS_PRESENT 0x116B +#endif + +/* cl_program_build_info */ +#define CL_PROGRAM_BUILD_STATUS 0x1181 +#define CL_PROGRAM_BUILD_OPTIONS 0x1182 +#define CL_PROGRAM_BUILD_LOG 0x1183 +#ifdef CL_VERSION_1_2 +#define CL_PROGRAM_BINARY_TYPE 0x1184 +#endif +#ifdef CL_VERSION_2_0 +#define CL_PROGRAM_BUILD_GLOBAL_VARIABLE_TOTAL_SIZE 0x1185 +#endif + +#ifdef CL_VERSION_1_2 + +/* cl_program_binary_type */ +#define CL_PROGRAM_BINARY_TYPE_NONE 0x0 +#define CL_PROGRAM_BINARY_TYPE_COMPILED_OBJECT 0x1 +#define CL_PROGRAM_BINARY_TYPE_LIBRARY 0x2 +#define CL_PROGRAM_BINARY_TYPE_EXECUTABLE 0x4 + +#endif + +/* cl_build_status */ +#define CL_BUILD_SUCCESS 0 +#define CL_BUILD_NONE -1 +#define CL_BUILD_ERROR -2 +#define CL_BUILD_IN_PROGRESS -3 + +/* cl_kernel_info */ +#define CL_KERNEL_FUNCTION_NAME 0x1190 +#define CL_KERNEL_NUM_ARGS 0x1191 +#define CL_KERNEL_REFERENCE_COUNT 0x1192 +#define CL_KERNEL_CONTEXT 0x1193 +#define CL_KERNEL_PROGRAM 0x1194 +#ifdef CL_VERSION_1_2 +#define CL_KERNEL_ATTRIBUTES 0x1195 +#endif +#ifdef CL_VERSION_2_1 +#define CL_KERNEL_MAX_NUM_SUB_GROUPS 0x11B9 +#define CL_KERNEL_COMPILE_NUM_SUB_GROUPS 0x11BA +#endif + +#ifdef CL_VERSION_1_2 + +/* cl_kernel_arg_info */ +#define CL_KERNEL_ARG_ADDRESS_QUALIFIER 0x1196 +#define CL_KERNEL_ARG_ACCESS_QUALIFIER 0x1197 +#define CL_KERNEL_ARG_TYPE_NAME 0x1198 +#define CL_KERNEL_ARG_TYPE_QUALIFIER 0x1199 +#define CL_KERNEL_ARG_NAME 0x119A + +#endif + +#ifdef CL_VERSION_1_2 + +/* cl_kernel_arg_address_qualifier */ +#define CL_KERNEL_ARG_ADDRESS_GLOBAL 0x119B +#define CL_KERNEL_ARG_ADDRESS_LOCAL 0x119C +#define CL_KERNEL_ARG_ADDRESS_CONSTANT 0x119D +#define CL_KERNEL_ARG_ADDRESS_PRIVATE 0x119E + +#endif + +#ifdef CL_VERSION_1_2 + +/* cl_kernel_arg_access_qualifier */ +#define CL_KERNEL_ARG_ACCESS_READ_ONLY 0x11A0 +#define CL_KERNEL_ARG_ACCESS_WRITE_ONLY 0x11A1 +#define CL_KERNEL_ARG_ACCESS_READ_WRITE 0x11A2 +#define CL_KERNEL_ARG_ACCESS_NONE 0x11A3 + +#endif + +#ifdef CL_VERSION_1_2 + +/* cl_kernel_arg_type_qualifier */ +#define CL_KERNEL_ARG_TYPE_NONE 0 +#define CL_KERNEL_ARG_TYPE_CONST (1 << 0) +#define CL_KERNEL_ARG_TYPE_RESTRICT (1 << 1) +#define CL_KERNEL_ARG_TYPE_VOLATILE (1 << 2) +#ifdef CL_VERSION_2_0 +#define CL_KERNEL_ARG_TYPE_PIPE (1 << 3) +#endif + +#endif + +/* cl_kernel_work_group_info */ +#define CL_KERNEL_WORK_GROUP_SIZE 0x11B0 +#define CL_KERNEL_COMPILE_WORK_GROUP_SIZE 0x11B1 +#define CL_KERNEL_LOCAL_MEM_SIZE 0x11B2 +#define CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE 0x11B3 +#define CL_KERNEL_PRIVATE_MEM_SIZE 0x11B4 +#ifdef CL_VERSION_1_2 +#define CL_KERNEL_GLOBAL_WORK_SIZE 0x11B5 +#endif + +#ifdef CL_VERSION_2_1 + +/* cl_kernel_sub_group_info */ +#define CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE 0x2033 +#define CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE 0x2034 +#define CL_KERNEL_LOCAL_SIZE_FOR_SUB_GROUP_COUNT 0x11B8 + +#endif + +#ifdef CL_VERSION_2_0 + +/* cl_kernel_exec_info */ +#define CL_KERNEL_EXEC_INFO_SVM_PTRS 0x11B6 +#define CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM 0x11B7 + +#endif + +/* cl_event_info */ +#define CL_EVENT_COMMAND_QUEUE 0x11D0 +#define CL_EVENT_COMMAND_TYPE 0x11D1 +#define CL_EVENT_REFERENCE_COUNT 0x11D2 +#define CL_EVENT_COMMAND_EXECUTION_STATUS 0x11D3 +#ifdef CL_VERSION_1_1 +#define CL_EVENT_CONTEXT 0x11D4 +#endif + +/* cl_command_type */ +#define CL_COMMAND_NDRANGE_KERNEL 0x11F0 +#define CL_COMMAND_TASK 0x11F1 +#define CL_COMMAND_NATIVE_KERNEL 0x11F2 +#define CL_COMMAND_READ_BUFFER 0x11F3 +#define CL_COMMAND_WRITE_BUFFER 0x11F4 +#define CL_COMMAND_COPY_BUFFER 0x11F5 +#define CL_COMMAND_READ_IMAGE 0x11F6 +#define CL_COMMAND_WRITE_IMAGE 0x11F7 +#define CL_COMMAND_COPY_IMAGE 0x11F8 +#define CL_COMMAND_COPY_IMAGE_TO_BUFFER 0x11F9 +#define CL_COMMAND_COPY_BUFFER_TO_IMAGE 0x11FA +#define CL_COMMAND_MAP_BUFFER 0x11FB +#define CL_COMMAND_MAP_IMAGE 0x11FC +#define CL_COMMAND_UNMAP_MEM_OBJECT 0x11FD +#define CL_COMMAND_MARKER 0x11FE +#define CL_COMMAND_ACQUIRE_GL_OBJECTS 0x11FF +#define CL_COMMAND_RELEASE_GL_OBJECTS 0x1200 +#ifdef CL_VERSION_1_1 +#define CL_COMMAND_READ_BUFFER_RECT 0x1201 +#define CL_COMMAND_WRITE_BUFFER_RECT 0x1202 +#define CL_COMMAND_COPY_BUFFER_RECT 0x1203 +#define CL_COMMAND_USER 0x1204 +#endif +#ifdef CL_VERSION_1_2 +#define CL_COMMAND_BARRIER 0x1205 +#define CL_COMMAND_MIGRATE_MEM_OBJECTS 0x1206 +#define CL_COMMAND_FILL_BUFFER 0x1207 +#define CL_COMMAND_FILL_IMAGE 0x1208 +#endif +#ifdef CL_VERSION_2_0 +#define CL_COMMAND_SVM_FREE 0x1209 +#define CL_COMMAND_SVM_MEMCPY 0x120A +#define CL_COMMAND_SVM_MEMFILL 0x120B +#define CL_COMMAND_SVM_MAP 0x120C +#define CL_COMMAND_SVM_UNMAP 0x120D +#endif + +/* command execution status */ +#define CL_COMPLETE 0x0 +#define CL_RUNNING 0x1 +#define CL_SUBMITTED 0x2 +#define CL_QUEUED 0x3 + +#ifdef CL_VERSION_1_1 + +/* cl_buffer_create_type */ +#define CL_BUFFER_CREATE_TYPE_REGION 0x1220 + +#endif + +/* cl_profiling_info */ +#define CL_PROFILING_COMMAND_QUEUED 0x1280 +#define CL_PROFILING_COMMAND_SUBMIT 0x1281 +#define CL_PROFILING_COMMAND_START 0x1282 +#define CL_PROFILING_COMMAND_END 0x1283 +#ifdef CL_VERSION_2_0 +#define CL_PROFILING_COMMAND_COMPLETE 0x1284 +#endif + +/********************************************************************************************************/ + +/* Platform API */ +extern CL_API_ENTRY cl_int CL_API_CALL +clGetPlatformIDs(cl_uint num_entries, + cl_platform_id * platforms, + cl_uint * num_platforms) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetPlatformInfo(cl_platform_id platform, + cl_platform_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +/* Device APIs */ +extern CL_API_ENTRY cl_int CL_API_CALL +clGetDeviceIDs(cl_platform_id platform, + cl_device_type device_type, + cl_uint num_entries, + cl_device_id * devices, + cl_uint * num_devices) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetDeviceInfo(cl_device_id device, + cl_device_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clCreateSubDevices(cl_device_id in_device, + const cl_device_partition_property * properties, + cl_uint num_devices, + cl_device_id * out_devices, + cl_uint * num_devices_ret) CL_API_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainDevice(cl_device_id device) CL_API_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseDevice(cl_device_id device) CL_API_SUFFIX__VERSION_1_2; + +#endif + +#ifdef CL_VERSION_2_1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetDefaultDeviceCommandQueue(cl_context context, + cl_device_id device, + cl_command_queue command_queue) CL_API_SUFFIX__VERSION_2_1; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetDeviceAndHostTimer(cl_device_id device, + cl_ulong* device_timestamp, + cl_ulong* host_timestamp) CL_API_SUFFIX__VERSION_2_1; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetHostTimer(cl_device_id device, + cl_ulong * host_timestamp) CL_API_SUFFIX__VERSION_2_1; + +#endif + +/* Context APIs */ +extern CL_API_ENTRY cl_context CL_API_CALL +clCreateContext(const cl_context_properties * properties, + cl_uint num_devices, + const cl_device_id * devices, + void (CL_CALLBACK * pfn_notify)(const char * errinfo, + const void * private_info, + size_t cb, + void * user_data), + void * user_data, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_context CL_API_CALL +clCreateContextFromType(const cl_context_properties * properties, + cl_device_type device_type, + void (CL_CALLBACK * pfn_notify)(const char * errinfo, + const void * private_info, + size_t cb, + void * user_data), + void * user_data, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainContext(cl_context context) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseContext(cl_context context) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetContextInfo(cl_context context, + cl_context_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +/* Command Queue APIs */ + +#ifdef CL_VERSION_2_0 + +extern CL_API_ENTRY cl_command_queue CL_API_CALL +clCreateCommandQueueWithProperties(cl_context context, + cl_device_id device, + const cl_queue_properties * properties, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_2_0; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainCommandQueue(cl_command_queue command_queue) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseCommandQueue(cl_command_queue command_queue) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetCommandQueueInfo(cl_command_queue command_queue, + cl_command_queue_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +/* Memory Object APIs */ +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateBuffer(cl_context context, + cl_mem_flags flags, + size_t size, + void * host_ptr, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_1 + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateSubBuffer(cl_mem buffer, + cl_mem_flags flags, + cl_buffer_create_type buffer_create_type, + const void * buffer_create_info, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_1; + +#endif + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateImage(cl_context context, + cl_mem_flags flags, + const cl_image_format * image_format, + const cl_image_desc * image_desc, + void * host_ptr, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2; + +#endif + +#ifdef CL_VERSION_2_0 + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreatePipe(cl_context context, + cl_mem_flags flags, + cl_uint pipe_packet_size, + cl_uint pipe_max_packets, + const cl_pipe_properties * properties, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_2_0; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainMemObject(cl_mem memobj) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseMemObject(cl_mem memobj) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetSupportedImageFormats(cl_context context, + cl_mem_flags flags, + cl_mem_object_type image_type, + cl_uint num_entries, + cl_image_format * image_formats, + cl_uint * num_image_formats) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetMemObjectInfo(cl_mem memobj, + cl_mem_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetImageInfo(cl_mem image, + cl_image_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_2_0 + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetPipeInfo(cl_mem pipe, + cl_pipe_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_2_0; + +#endif + +#ifdef CL_VERSION_1_1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetMemObjectDestructorCallback(cl_mem memobj, + void (CL_CALLBACK * pfn_notify)(cl_mem memobj, + void * user_data), + void * user_data) CL_API_SUFFIX__VERSION_1_1; + +#endif + +/* SVM Allocation APIs */ + +#ifdef CL_VERSION_2_0 + +extern CL_API_ENTRY void * CL_API_CALL +clSVMAlloc(cl_context context, + cl_svm_mem_flags flags, + size_t size, + cl_uint alignment) CL_API_SUFFIX__VERSION_2_0; + +extern CL_API_ENTRY void CL_API_CALL +clSVMFree(cl_context context, + void * svm_pointer) CL_API_SUFFIX__VERSION_2_0; + +#endif + +/* Sampler APIs */ + +#ifdef CL_VERSION_2_0 + +extern CL_API_ENTRY cl_sampler CL_API_CALL +clCreateSamplerWithProperties(cl_context context, + const cl_sampler_properties * sampler_properties, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_2_0; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainSampler(cl_sampler sampler) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseSampler(cl_sampler sampler) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetSamplerInfo(cl_sampler sampler, + cl_sampler_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +/* Program Object APIs */ +extern CL_API_ENTRY cl_program CL_API_CALL +clCreateProgramWithSource(cl_context context, + cl_uint count, + const char ** strings, + const size_t * lengths, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_program CL_API_CALL +clCreateProgramWithBinary(cl_context context, + cl_uint num_devices, + const cl_device_id * device_list, + const size_t * lengths, + const unsigned char ** binaries, + cl_int * binary_status, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_program CL_API_CALL +clCreateProgramWithBuiltInKernels(cl_context context, + cl_uint num_devices, + const cl_device_id * device_list, + const char * kernel_names, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2; + +#endif + +#ifdef CL_VERSION_2_1 + +extern CL_API_ENTRY cl_program CL_API_CALL +clCreateProgramWithIL(cl_context context, + const void* il, + size_t length, + cl_int* errcode_ret) CL_API_SUFFIX__VERSION_2_1; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainProgram(cl_program program) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseProgram(cl_program program) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clBuildProgram(cl_program program, + cl_uint num_devices, + const cl_device_id * device_list, + const char * options, + void (CL_CALLBACK * pfn_notify)(cl_program program, + void * user_data), + void * user_data) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clCompileProgram(cl_program program, + cl_uint num_devices, + const cl_device_id * device_list, + const char * options, + cl_uint num_input_headers, + const cl_program * input_headers, + const char ** header_include_names, + void (CL_CALLBACK * pfn_notify)(cl_program program, + void * user_data), + void * user_data) CL_API_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_program CL_API_CALL +clLinkProgram(cl_context context, + cl_uint num_devices, + const cl_device_id * device_list, + const char * options, + cl_uint num_input_programs, + const cl_program * input_programs, + void (CL_CALLBACK * pfn_notify)(cl_program program, + void * user_data), + void * user_data, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2; + +#endif + +#ifdef CL_VERSION_2_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetProgramReleaseCallback(cl_program program, + void (CL_CALLBACK * pfn_notify)(cl_program program, + void * user_data), + void * user_data) CL_API_SUFFIX__VERSION_2_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetProgramSpecializationConstant(cl_program program, + cl_uint spec_id, + size_t spec_size, + const void* spec_value) CL_API_SUFFIX__VERSION_2_2; + +#endif + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clUnloadPlatformCompiler(cl_platform_id platform) CL_API_SUFFIX__VERSION_1_2; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetProgramInfo(cl_program program, + cl_program_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetProgramBuildInfo(cl_program program, + cl_device_id device, + cl_program_build_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +/* Kernel Object APIs */ +extern CL_API_ENTRY cl_kernel CL_API_CALL +clCreateKernel(cl_program program, + const char * kernel_name, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clCreateKernelsInProgram(cl_program program, + cl_uint num_kernels, + cl_kernel * kernels, + cl_uint * num_kernels_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_2_1 + +extern CL_API_ENTRY cl_kernel CL_API_CALL +clCloneKernel(cl_kernel source_kernel, + cl_int* errcode_ret) CL_API_SUFFIX__VERSION_2_1; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainKernel(cl_kernel kernel) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseKernel(cl_kernel kernel) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetKernelArg(cl_kernel kernel, + cl_uint arg_index, + size_t arg_size, + const void * arg_value) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_2_0 + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetKernelArgSVMPointer(cl_kernel kernel, + cl_uint arg_index, + const void * arg_value) CL_API_SUFFIX__VERSION_2_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetKernelExecInfo(cl_kernel kernel, + cl_kernel_exec_info param_name, + size_t param_value_size, + const void * param_value) CL_API_SUFFIX__VERSION_2_0; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetKernelInfo(cl_kernel kernel, + cl_kernel_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetKernelArgInfo(cl_kernel kernel, + cl_uint arg_indx, + cl_kernel_arg_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_2; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetKernelWorkGroupInfo(cl_kernel kernel, + cl_device_id device, + cl_kernel_work_group_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_2_1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetKernelSubGroupInfo(cl_kernel kernel, + cl_device_id device, + cl_kernel_sub_group_info param_name, + size_t input_value_size, + const void* input_value, + size_t param_value_size, + void* param_value, + size_t* param_value_size_ret) CL_API_SUFFIX__VERSION_2_1; + +#endif + +/* Event Object APIs */ +extern CL_API_ENTRY cl_int CL_API_CALL +clWaitForEvents(cl_uint num_events, + const cl_event * event_list) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetEventInfo(cl_event event, + cl_event_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_1 + +extern CL_API_ENTRY cl_event CL_API_CALL +clCreateUserEvent(cl_context context, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_1; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainEvent(cl_event event) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseEvent(cl_event event) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetUserEventStatus(cl_event event, + cl_int execution_status) CL_API_SUFFIX__VERSION_1_1; + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetEventCallback(cl_event event, + cl_int command_exec_callback_type, + void (CL_CALLBACK * pfn_notify)(cl_event event, + cl_int event_command_status, + void * user_data), + void * user_data) CL_API_SUFFIX__VERSION_1_1; + +#endif + +/* Profiling APIs */ +extern CL_API_ENTRY cl_int CL_API_CALL +clGetEventProfilingInfo(cl_event event, + cl_profiling_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +/* Flush and Finish APIs */ +extern CL_API_ENTRY cl_int CL_API_CALL +clFlush(cl_command_queue command_queue) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clFinish(cl_command_queue command_queue) CL_API_SUFFIX__VERSION_1_0; + +/* Enqueued Commands APIs */ +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueReadBuffer(cl_command_queue command_queue, + cl_mem buffer, + cl_bool blocking_read, + size_t offset, + size_t size, + void * ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueReadBufferRect(cl_command_queue command_queue, + cl_mem buffer, + cl_bool blocking_read, + const size_t * buffer_offset, + const size_t * host_offset, + const size_t * region, + size_t buffer_row_pitch, + size_t buffer_slice_pitch, + size_t host_row_pitch, + size_t host_slice_pitch, + void * ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_1; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueWriteBuffer(cl_command_queue command_queue, + cl_mem buffer, + cl_bool blocking_write, + size_t offset, + size_t size, + const void * ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueWriteBufferRect(cl_command_queue command_queue, + cl_mem buffer, + cl_bool blocking_write, + const size_t * buffer_offset, + const size_t * host_offset, + const size_t * region, + size_t buffer_row_pitch, + size_t buffer_slice_pitch, + size_t host_row_pitch, + size_t host_slice_pitch, + const void * ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_1; + +#endif + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueFillBuffer(cl_command_queue command_queue, + cl_mem buffer, + const void * pattern, + size_t pattern_size, + size_t offset, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueCopyBuffer(cl_command_queue command_queue, + cl_mem src_buffer, + cl_mem dst_buffer, + size_t src_offset, + size_t dst_offset, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueCopyBufferRect(cl_command_queue command_queue, + cl_mem src_buffer, + cl_mem dst_buffer, + const size_t * src_origin, + const size_t * dst_origin, + const size_t * region, + size_t src_row_pitch, + size_t src_slice_pitch, + size_t dst_row_pitch, + size_t dst_slice_pitch, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_1; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueReadImage(cl_command_queue command_queue, + cl_mem image, + cl_bool blocking_read, + const size_t * origin, + const size_t * region, + size_t row_pitch, + size_t slice_pitch, + void * ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueWriteImage(cl_command_queue command_queue, + cl_mem image, + cl_bool blocking_write, + const size_t * origin, + const size_t * region, + size_t input_row_pitch, + size_t input_slice_pitch, + const void * ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueFillImage(cl_command_queue command_queue, + cl_mem image, + const void * fill_color, + const size_t * origin, + const size_t * region, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueCopyImage(cl_command_queue command_queue, + cl_mem src_image, + cl_mem dst_image, + const size_t * src_origin, + const size_t * dst_origin, + const size_t * region, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueCopyImageToBuffer(cl_command_queue command_queue, + cl_mem src_image, + cl_mem dst_buffer, + const size_t * src_origin, + const size_t * region, + size_t dst_offset, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueCopyBufferToImage(cl_command_queue command_queue, + cl_mem src_buffer, + cl_mem dst_image, + size_t src_offset, + const size_t * dst_origin, + const size_t * region, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY void * CL_API_CALL +clEnqueueMapBuffer(cl_command_queue command_queue, + cl_mem buffer, + cl_bool blocking_map, + cl_map_flags map_flags, + size_t offset, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY void * CL_API_CALL +clEnqueueMapImage(cl_command_queue command_queue, + cl_mem image, + cl_bool blocking_map, + cl_map_flags map_flags, + const size_t * origin, + const size_t * region, + size_t * image_row_pitch, + size_t * image_slice_pitch, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueUnmapMemObject(cl_command_queue command_queue, + cl_mem memobj, + void * mapped_ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueMigrateMemObjects(cl_command_queue command_queue, + cl_uint num_mem_objects, + const cl_mem * mem_objects, + cl_mem_migration_flags flags, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +#endif + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueNDRangeKernel(cl_command_queue command_queue, + cl_kernel kernel, + cl_uint work_dim, + const size_t * global_work_offset, + const size_t * global_work_size, + const size_t * local_work_size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueNativeKernel(cl_command_queue command_queue, + void (CL_CALLBACK * user_func)(void *), + void * args, + size_t cb_args, + cl_uint num_mem_objects, + const cl_mem * mem_list, + const void ** args_mem_loc, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueMarkerWithWaitList(cl_command_queue command_queue, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueBarrierWithWaitList(cl_command_queue command_queue, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +#endif + +#ifdef CL_VERSION_2_0 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMFree(cl_command_queue command_queue, + cl_uint num_svm_pointers, + void * svm_pointers[], + void (CL_CALLBACK * pfn_free_func)(cl_command_queue queue, + cl_uint num_svm_pointers, + void * svm_pointers[], + void * user_data), + void * user_data, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_2_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMMemcpy(cl_command_queue command_queue, + cl_bool blocking_copy, + void * dst_ptr, + const void * src_ptr, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_2_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMMemFill(cl_command_queue command_queue, + void * svm_ptr, + const void * pattern, + size_t pattern_size, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_2_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMMap(cl_command_queue command_queue, + cl_bool blocking_map, + cl_map_flags flags, + void * svm_ptr, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_2_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMUnmap(cl_command_queue command_queue, + void * svm_ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_2_0; + +#endif + +#ifdef CL_VERSION_2_1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMMigrateMem(cl_command_queue command_queue, + cl_uint num_svm_pointers, + const void ** svm_pointers, + const size_t * sizes, + cl_mem_migration_flags flags, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_2_1; + +#endif + +#ifdef CL_VERSION_1_2 + +/* Extension function access + * + * Returns the extension function address for the given function name, + * or NULL if a valid function can not be found. The client must + * check to make sure the address is not NULL, before using or + * calling the returned function address. + */ +extern CL_API_ENTRY void * CL_API_CALL +clGetExtensionFunctionAddressForPlatform(cl_platform_id platform, + const char * func_name) CL_API_SUFFIX__VERSION_1_2; + +#endif + +#ifdef CL_USE_DEPRECATED_OPENCL_1_0_APIS + /* + * WARNING: + * This API introduces mutable state into the OpenCL implementation. It has been REMOVED + * to better facilitate thread safety. The 1.0 API is not thread safe. It is not tested by the + * OpenCL 1.1 conformance test, and consequently may not work or may not work dependably. + * It is likely to be non-performant. Use of this API is not advised. Use at your own risk. + * + * Software developers previously relying on this API are instructed to set the command queue + * properties when creating the queue, instead. + */ + extern CL_API_ENTRY cl_int CL_API_CALL + clSetCommandQueueProperty(cl_command_queue command_queue, + cl_command_queue_properties properties, + cl_bool enable, + cl_command_queue_properties * old_properties) CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED; +#endif /* CL_USE_DEPRECATED_OPENCL_1_0_APIS */ + +/* Deprecated OpenCL 1.1 APIs */ +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL +clCreateImage2D(cl_context context, + cl_mem_flags flags, + const cl_image_format * image_format, + size_t image_width, + size_t image_height, + size_t image_row_pitch, + void * host_ptr, + cl_int * errcode_ret) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL +clCreateImage3D(cl_context context, + cl_mem_flags flags, + const cl_image_format * image_format, + size_t image_width, + size_t image_height, + size_t image_depth, + size_t image_row_pitch, + size_t image_slice_pitch, + void * host_ptr, + cl_int * errcode_ret) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int CL_API_CALL +clEnqueueMarker(cl_command_queue command_queue, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int CL_API_CALL +clEnqueueWaitForEvents(cl_command_queue command_queue, + cl_uint num_events, + const cl_event * event_list) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int CL_API_CALL +clEnqueueBarrier(cl_command_queue command_queue) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int CL_API_CALL +clUnloadCompiler(void) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED void * CL_API_CALL +clGetExtensionFunctionAddress(const char * func_name) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +/* Deprecated OpenCL 2.0 APIs */ +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_2_DEPRECATED cl_command_queue CL_API_CALL +clCreateCommandQueue(cl_context context, + cl_device_id device, + cl_command_queue_properties properties, + cl_int * errcode_ret) CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_2_DEPRECATED cl_sampler CL_API_CALL +clCreateSampler(cl_context context, + cl_bool normalized_coords, + cl_addressing_mode addressing_mode, + cl_filter_mode filter_mode, + cl_int * errcode_ret) CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_2_DEPRECATED cl_int CL_API_CALL +clEnqueueTask(cl_command_queue command_queue, + cl_kernel kernel, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED; + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_H */ diff --git a/benchmarks/new_opencl/include/CL/cl.hpp b/benchmarks/new_opencl/include/CL/cl.hpp new file mode 100644 index 00000000..9edb0e47 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl.hpp @@ -0,0 +1,12459 @@ +/******************************************************************************* + * Copyright (c) 2008-2013 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + ******************************************************************************/ + +/*! \file + * + * \brief C++ bindings for OpenCL 1.0 (rev 48), OpenCL 1.1 (rev 33) and + * OpenCL 1.2 (rev 15) + * \author Benedict R. Gaster, Laurent Morichetti and Lee Howes + * + * Additions and fixes from: + * Brian Cole, March 3rd 2010 and April 2012 + * Matt Gruenke, April 2012. + * Bruce Merry, February 2013. + * Tom Deakin and Simon McIntosh-Smith, July 2013 + * + * \version 1.2.6 + * \date August 2013 + * + * Optional extension support + * + * cl + * cl_ext_device_fission + * #define USE_CL_DEVICE_FISSION + */ + +/*! \mainpage + * \section intro Introduction + * For many large applications C++ is the language of choice and so it seems + * reasonable to define C++ bindings for OpenCL. + * + * + * The interface is contained with a single C++ header file \em cl.hpp and all + * definitions are contained within the namespace \em cl. There is no additional + * requirement to include \em cl.h and to use either the C++ or original C + * bindings it is enough to simply include \em cl.hpp. + * + * The bindings themselves are lightweight and correspond closely to the + * underlying C API. Using the C++ bindings introduces no additional execution + * overhead. + * + * For detail documentation on the bindings see: + * + * The OpenCL C++ Wrapper API 1.2 (revision 09) + * http://www.khronos.org/registry/cl/specs/opencl-cplusplus-1.2.pdf + * + * \section example Example + * + * The following example shows a general use case for the C++ + * bindings, including support for the optional exception feature and + * also the supplied vector and string classes, see following sections for + * decriptions of these features. + * + * \code + * #define __CL_ENABLE_EXCEPTIONS + * + * #if defined(__APPLE__) || defined(__MACOSX) + * #include + * #else + * #include + * #endif + * #include + * #include + * #include + * + * const char * helloStr = "__kernel void " + * "hello(void) " + * "{ " + * " " + * "} "; + * + * int + * main(void) + * { + * cl_int err = CL_SUCCESS; + * try { + * + * std::vector platforms; + * cl::Platform::get(&platforms); + * if (platforms.size() == 0) { + * std::cout << "Platform size 0\n"; + * return -1; + * } + * + * cl_context_properties properties[] = + * { CL_CONTEXT_PLATFORM, (cl_context_properties)(platforms[0])(), 0}; + * cl::Context context(CL_DEVICE_TYPE_CPU, properties); + * + * std::vector devices = context.getInfo(); + * + * cl::Program::Sources source(1, + * std::make_pair(helloStr,strlen(helloStr))); + * cl::Program program_ = cl::Program(context, source); + * program_.build(devices); + * + * cl::Kernel kernel(program_, "hello", &err); + * + * cl::Event event; + * cl::CommandQueue queue(context, devices[0], 0, &err); + * queue.enqueueNDRangeKernel( + * kernel, + * cl::NullRange, + * cl::NDRange(4,4), + * cl::NullRange, + * NULL, + * &event); + * + * event.wait(); + * } + * catch (cl::Error err) { + * std::cerr + * << "ERROR: " + * << err.what() + * << "(" + * << err.err() + * << ")" + * << std::endl; + * } + * + * return EXIT_SUCCESS; + * } + * + * \endcode + * + */ +#ifndef CL_HPP_ +#define CL_HPP_ + +#ifdef _WIN32 + +#include +#include +#include +#include + +#if defined(__CL_ENABLE_EXCEPTIONS) +#include +#endif // #if defined(__CL_ENABLE_EXCEPTIONS) + +#pragma push_macro("max") +#undef max +#if defined(USE_DX_INTEROP) +#include +#include +#endif +#endif // _WIN32 + +// +#if defined(USE_CL_DEVICE_FISSION) +#include +#endif + +#if defined(__APPLE__) || defined(__MACOSX) +#include +#include +#include +#elif defined(__ANDROID__) +#include +#include +#else +#include +#include +#endif // !__APPLE__ + +// To avoid accidentally taking ownership of core OpenCL types +// such as cl_kernel constructors are made explicit +// under OpenCL 1.2 +#if defined(CL_VERSION_1_2) && !defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +#define __CL_EXPLICIT_CONSTRUCTORS explicit +#else // #if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +#define __CL_EXPLICIT_CONSTRUCTORS +#endif // #if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + +// Define deprecated prefixes and suffixes to ensure compilation +// in case they are not pre-defined +#if !defined(CL_EXT_PREFIX__VERSION_1_1_DEPRECATED) +#define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED +#endif // #if !defined(CL_EXT_PREFIX__VERSION_1_1_DEPRECATED) +#if !defined(CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED) +#define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED +#endif // #if !defined(CL_EXT_PREFIX__VERSION_1_1_DEPRECATED) + +#if !defined(CL_CALLBACK) +#define CL_CALLBACK +#endif //CL_CALLBACK + +#include +#include + +#if !defined(__NO_STD_VECTOR) +#include +#endif + +#if !defined(__NO_STD_STRING) +#include +#endif + +#if defined(linux) || defined(__APPLE__) || defined(__MACOSX) || defined(__ANDROID__) || defined(__FreeBSD_kernel__) || defined(__GNU__) +#include + +#endif // linux + +#include + + +/*! \namespace cl + * + * \brief The OpenCL C++ bindings are defined within this namespace. + * + */ +namespace cl { + +class Memory; + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) || (defined(CL_VERSION_1_1) && !defined(CL_VERSION_1_2)) +#define __INIT_CL_EXT_FCN_PTR(name) \ + if(!pfn_##name) { \ + pfn_##name = (PFN_##name) \ + clGetExtensionFunctionAddress(#name); \ + if(!pfn_##name) { \ + } \ + } +#endif // #if defined(CL_VERSION_1_1) + +#if defined(CL_VERSION_1_2) +#define __INIT_CL_EXT_FCN_PTR_PLATFORM(platform, name) \ + if(!pfn_##name) { \ + pfn_##name = (PFN_##name) \ + clGetExtensionFunctionAddressForPlatform(platform, #name); \ + if(!pfn_##name) { \ + } \ + } +#endif // #if defined(CL_VERSION_1_1) + +class Program; +class Device; +class Context; +class CommandQueue; +class Memory; +class Buffer; + +#if defined(__CL_ENABLE_EXCEPTIONS) +/*! \brief Exception class + * + * This may be thrown by API functions when __CL_ENABLE_EXCEPTIONS is defined. + */ +class Error : public std::exception +{ +private: + cl_int err_; + const char * errStr_; +public: + /*! \brief Create a new CL error exception for a given error code + * and corresponding message. + * + * \param err error code value. + * + * \param errStr a descriptive string that must remain in scope until + * handling of the exception has concluded. If set, it + * will be returned by what(). + */ + Error(cl_int err, const char * errStr = NULL) : err_(err), errStr_(errStr) + {} + + ~Error() throw() {} + + /*! \brief Get error string associated with exception + * + * \return A memory pointer to the error message string. + */ + virtual const char * what() const throw () + { + if (errStr_ == NULL) { + return "empty"; + } + else { + return errStr_; + } + } + + /*! \brief Get error code associated with exception + * + * \return The error code. + */ + cl_int err(void) const { return err_; } +}; + +#define __ERR_STR(x) #x +#else +#define __ERR_STR(x) NULL +#endif // __CL_ENABLE_EXCEPTIONS + + +namespace detail +{ +#if defined(__CL_ENABLE_EXCEPTIONS) +static inline cl_int errHandler ( + cl_int err, + const char * errStr = NULL) +{ + if (err != CL_SUCCESS) { + throw Error(err, errStr); + } + return err; +} +#else +static inline cl_int errHandler (cl_int err, const char * errStr = NULL) +{ + (void) errStr; // suppress unused variable warning + return err; +} +#endif // __CL_ENABLE_EXCEPTIONS +} + + + +//! \cond DOXYGEN_DETAIL +#if !defined(__CL_USER_OVERRIDE_ERROR_STRINGS) +#define __GET_DEVICE_INFO_ERR __ERR_STR(clGetDeviceInfo) +#define __GET_PLATFORM_INFO_ERR __ERR_STR(clGetPlatformInfo) +#define __GET_DEVICE_IDS_ERR __ERR_STR(clGetDeviceIDs) +#define __GET_PLATFORM_IDS_ERR __ERR_STR(clGetPlatformIDs) +#define __GET_CONTEXT_INFO_ERR __ERR_STR(clGetContextInfo) +#define __GET_EVENT_INFO_ERR __ERR_STR(clGetEventInfo) +#define __GET_EVENT_PROFILE_INFO_ERR __ERR_STR(clGetEventProfileInfo) +#define __GET_MEM_OBJECT_INFO_ERR __ERR_STR(clGetMemObjectInfo) +#define __GET_IMAGE_INFO_ERR __ERR_STR(clGetImageInfo) +#define __GET_SAMPLER_INFO_ERR __ERR_STR(clGetSamplerInfo) +#define __GET_KERNEL_INFO_ERR __ERR_STR(clGetKernelInfo) +#if defined(CL_VERSION_1_2) +#define __GET_KERNEL_ARG_INFO_ERR __ERR_STR(clGetKernelArgInfo) +#endif // #if defined(CL_VERSION_1_2) +#define __GET_KERNEL_WORK_GROUP_INFO_ERR __ERR_STR(clGetKernelWorkGroupInfo) +#define __GET_PROGRAM_INFO_ERR __ERR_STR(clGetProgramInfo) +#define __GET_PROGRAM_BUILD_INFO_ERR __ERR_STR(clGetProgramBuildInfo) +#define __GET_COMMAND_QUEUE_INFO_ERR __ERR_STR(clGetCommandQueueInfo) + +#define __CREATE_CONTEXT_ERR __ERR_STR(clCreateContext) +#define __CREATE_CONTEXT_FROM_TYPE_ERR __ERR_STR(clCreateContextFromType) +#define __GET_SUPPORTED_IMAGE_FORMATS_ERR __ERR_STR(clGetSupportedImageFormats) + +#define __CREATE_BUFFER_ERR __ERR_STR(clCreateBuffer) +#define __COPY_ERR __ERR_STR(cl::copy) +#define __CREATE_SUBBUFFER_ERR __ERR_STR(clCreateSubBuffer) +#define __CREATE_GL_BUFFER_ERR __ERR_STR(clCreateFromGLBuffer) +#define __CREATE_GL_RENDER_BUFFER_ERR __ERR_STR(clCreateFromGLBuffer) +#define __GET_GL_OBJECT_INFO_ERR __ERR_STR(clGetGLObjectInfo) +#if defined(CL_VERSION_1_2) +#define __CREATE_IMAGE_ERR __ERR_STR(clCreateImage) +#define __CREATE_GL_TEXTURE_ERR __ERR_STR(clCreateFromGLTexture) +#define __IMAGE_DIMENSION_ERR __ERR_STR(Incorrect image dimensions) +#endif // #if defined(CL_VERSION_1_2) +#define __CREATE_SAMPLER_ERR __ERR_STR(clCreateSampler) +#define __SET_MEM_OBJECT_DESTRUCTOR_CALLBACK_ERR __ERR_STR(clSetMemObjectDestructorCallback) + +#define __CREATE_USER_EVENT_ERR __ERR_STR(clCreateUserEvent) +#define __SET_USER_EVENT_STATUS_ERR __ERR_STR(clSetUserEventStatus) +#define __SET_EVENT_CALLBACK_ERR __ERR_STR(clSetEventCallback) +#define __WAIT_FOR_EVENTS_ERR __ERR_STR(clWaitForEvents) + +#define __CREATE_KERNEL_ERR __ERR_STR(clCreateKernel) +#define __SET_KERNEL_ARGS_ERR __ERR_STR(clSetKernelArg) +#define __CREATE_PROGRAM_WITH_SOURCE_ERR __ERR_STR(clCreateProgramWithSource) +#define __CREATE_PROGRAM_WITH_BINARY_ERR __ERR_STR(clCreateProgramWithBinary) +#if defined(CL_VERSION_1_2) +#define __CREATE_PROGRAM_WITH_BUILT_IN_KERNELS_ERR __ERR_STR(clCreateProgramWithBuiltInKernels) +#endif // #if defined(CL_VERSION_1_2) +#define __BUILD_PROGRAM_ERR __ERR_STR(clBuildProgram) +#if defined(CL_VERSION_1_2) +#define __COMPILE_PROGRAM_ERR __ERR_STR(clCompileProgram) + +#endif // #if defined(CL_VERSION_1_2) +#define __CREATE_KERNELS_IN_PROGRAM_ERR __ERR_STR(clCreateKernelsInProgram) + +#define __CREATE_COMMAND_QUEUE_ERR __ERR_STR(clCreateCommandQueue) +#define __SET_COMMAND_QUEUE_PROPERTY_ERR __ERR_STR(clSetCommandQueueProperty) +#define __ENQUEUE_READ_BUFFER_ERR __ERR_STR(clEnqueueReadBuffer) +#define __ENQUEUE_READ_BUFFER_RECT_ERR __ERR_STR(clEnqueueReadBufferRect) +#define __ENQUEUE_WRITE_BUFFER_ERR __ERR_STR(clEnqueueWriteBuffer) +#define __ENQUEUE_WRITE_BUFFER_RECT_ERR __ERR_STR(clEnqueueWriteBufferRect) +#define __ENQUEUE_COPY_BUFFER_ERR __ERR_STR(clEnqueueCopyBuffer) +#define __ENQUEUE_COPY_BUFFER_RECT_ERR __ERR_STR(clEnqueueCopyBufferRect) +#define __ENQUEUE_FILL_BUFFER_ERR __ERR_STR(clEnqueueFillBuffer) +#define __ENQUEUE_READ_IMAGE_ERR __ERR_STR(clEnqueueReadImage) +#define __ENQUEUE_WRITE_IMAGE_ERR __ERR_STR(clEnqueueWriteImage) +#define __ENQUEUE_COPY_IMAGE_ERR __ERR_STR(clEnqueueCopyImage) +#define __ENQUEUE_FILL_IMAGE_ERR __ERR_STR(clEnqueueFillImage) +#define __ENQUEUE_COPY_IMAGE_TO_BUFFER_ERR __ERR_STR(clEnqueueCopyImageToBuffer) +#define __ENQUEUE_COPY_BUFFER_TO_IMAGE_ERR __ERR_STR(clEnqueueCopyBufferToImage) +#define __ENQUEUE_MAP_BUFFER_ERR __ERR_STR(clEnqueueMapBuffer) +#define __ENQUEUE_MAP_IMAGE_ERR __ERR_STR(clEnqueueMapImage) +#define __ENQUEUE_UNMAP_MEM_OBJECT_ERR __ERR_STR(clEnqueueUnMapMemObject) +#define __ENQUEUE_NDRANGE_KERNEL_ERR __ERR_STR(clEnqueueNDRangeKernel) +#define __ENQUEUE_TASK_ERR __ERR_STR(clEnqueueTask) +#define __ENQUEUE_NATIVE_KERNEL __ERR_STR(clEnqueueNativeKernel) +#if defined(CL_VERSION_1_2) +#define __ENQUEUE_MIGRATE_MEM_OBJECTS_ERR __ERR_STR(clEnqueueMigrateMemObjects) +#endif // #if defined(CL_VERSION_1_2) + +#define __ENQUEUE_ACQUIRE_GL_ERR __ERR_STR(clEnqueueAcquireGLObjects) +#define __ENQUEUE_RELEASE_GL_ERR __ERR_STR(clEnqueueReleaseGLObjects) + + +#define __RETAIN_ERR __ERR_STR(Retain Object) +#define __RELEASE_ERR __ERR_STR(Release Object) +#define __FLUSH_ERR __ERR_STR(clFlush) +#define __FINISH_ERR __ERR_STR(clFinish) +#define __VECTOR_CAPACITY_ERR __ERR_STR(Vector capacity error) + +/** + * CL 1.2 version that uses device fission. + */ +#if defined(CL_VERSION_1_2) +#define __CREATE_SUB_DEVICES __ERR_STR(clCreateSubDevices) +#else +#define __CREATE_SUB_DEVICES __ERR_STR(clCreateSubDevicesEXT) +#endif // #if defined(CL_VERSION_1_2) + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) || (defined(CL_VERSION_1_1) && !defined(CL_VERSION_1_2)) +#define __ENQUEUE_MARKER_ERR __ERR_STR(clEnqueueMarker) +#define __ENQUEUE_WAIT_FOR_EVENTS_ERR __ERR_STR(clEnqueueWaitForEvents) +#define __ENQUEUE_BARRIER_ERR __ERR_STR(clEnqueueBarrier) +#define __UNLOAD_COMPILER_ERR __ERR_STR(clUnloadCompiler) +#define __CREATE_GL_TEXTURE_2D_ERR __ERR_STR(clCreateFromGLTexture2D) +#define __CREATE_GL_TEXTURE_3D_ERR __ERR_STR(clCreateFromGLTexture3D) +#define __CREATE_IMAGE2D_ERR __ERR_STR(clCreateImage2D) +#define __CREATE_IMAGE3D_ERR __ERR_STR(clCreateImage3D) +#endif // #if defined(CL_VERSION_1_1) + +#endif // __CL_USER_OVERRIDE_ERROR_STRINGS +//! \endcond + +/** + * CL 1.2 marker and barrier commands + */ +#if defined(CL_VERSION_1_2) +#define __ENQUEUE_MARKER_WAIT_LIST_ERR __ERR_STR(clEnqueueMarkerWithWaitList) +#define __ENQUEUE_BARRIER_WAIT_LIST_ERR __ERR_STR(clEnqueueBarrierWithWaitList) +#endif // #if defined(CL_VERSION_1_2) + +#if !defined(__USE_DEV_STRING) && !defined(__NO_STD_STRING) +typedef std::string STRING_CLASS; +#elif !defined(__USE_DEV_STRING) + +/*! \class string + * \brief Simple string class, that provides a limited subset of std::string + * functionality but avoids many of the issues that come with that class. + + * \note Deprecated. Please use std::string as default or + * re-define the string class to match the std::string + * interface by defining STRING_CLASS + */ +class CL_EXT_PREFIX__VERSION_1_1_DEPRECATED string CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED +{ +private: + ::size_t size_; + char * str_; +public: + //! \brief Constructs an empty string, allocating no memory. + string(void) : size_(0), str_(NULL) + { + } + + /*! \brief Constructs a string populated from an arbitrary value of + * specified size. + * + * An extra '\0' is added, in case none was contained in str. + * + * \param str the initial value of the string instance. Note that '\0' + * characters receive no special treatment. If NULL, + * the string is left empty, with a size of 0. + * + * \param size the number of characters to copy from str. + */ + string(const char * str, ::size_t size) : + size_(size), + str_(NULL) + { + if( size > 0 ) { + str_ = new char[size_+1]; + if (str_ != NULL) { + memcpy(str_, str, size_ * sizeof(char)); + str_[size_] = '\0'; + } + else { + size_ = 0; + } + } + } + + /*! \brief Constructs a string populated from a null-terminated value. + * + * \param str the null-terminated initial value of the string instance. + * If NULL, the string is left empty, with a size of 0. + */ + string(const char * str) : + size_(0), + str_(NULL) + { + if( str ) { + size_= ::strlen(str); + } + if( size_ > 0 ) { + str_ = new char[size_ + 1]; + if (str_ != NULL) { + memcpy(str_, str, (size_ + 1) * sizeof(char)); + } + } + } + + void resize( ::size_t n ) + { + if( size_ == n ) { + return; + } + if (n == 0) { + if( str_ ) { + delete [] str_; + } + str_ = NULL; + size_ = 0; + } + else { + char *newString = new char[n + 1]; + int copySize = n; + if( size_ < n ) { + copySize = size_; + } + size_ = n; + + if(str_) { + memcpy(newString, str_, (copySize + 1) * sizeof(char)); + } + if( copySize < size_ ) { + memset(newString + copySize, 0, size_ - copySize); + } + newString[size_] = '\0'; + + delete [] str_; + str_ = newString; + } + } + + const char& operator[] ( ::size_t pos ) const + { + return str_[pos]; + } + + char& operator[] ( ::size_t pos ) + { + return str_[pos]; + } + + /*! \brief Copies the value of another string to this one. + * + * \param rhs the string to copy. + * + * \returns a reference to the modified instance. + */ + string& operator=(const string& rhs) + { + if (this == &rhs) { + return *this; + } + + if( str_ != NULL ) { + delete [] str_; + str_ = NULL; + size_ = 0; + } + + if (rhs.size_ == 0 || rhs.str_ == NULL) { + str_ = NULL; + size_ = 0; + } + else { + str_ = new char[rhs.size_ + 1]; + size_ = rhs.size_; + + if (str_ != NULL) { + memcpy(str_, rhs.str_, (size_ + 1) * sizeof(char)); + } + else { + size_ = 0; + } + } + + return *this; + } + + /*! \brief Constructs a string by copying the value of another instance. + * + * \param rhs the string to copy. + */ + string(const string& rhs) : + size_(0), + str_(NULL) + { + *this = rhs; + } + + //! \brief Destructor - frees memory used to hold the current value. + ~string() + { + delete[] str_; + str_ = NULL; + } + + //! \brief Queries the length of the string, excluding any added '\0's. + ::size_t size(void) const { return size_; } + + //! \brief Queries the length of the string, excluding any added '\0's. + ::size_t length(void) const { return size(); } + + /*! \brief Returns a pointer to the private copy held by this instance, + * or "" if empty/unset. + */ + const char * c_str(void) const { return (str_) ? str_ : "";} +}; +typedef cl::string STRING_CLASS; +#endif // #elif !defined(__USE_DEV_STRING) + +#if !defined(__USE_DEV_VECTOR) && !defined(__NO_STD_VECTOR) +#define VECTOR_CLASS std::vector +#elif !defined(__USE_DEV_VECTOR) +#define VECTOR_CLASS cl::vector + +#if !defined(__MAX_DEFAULT_VECTOR_SIZE) +#define __MAX_DEFAULT_VECTOR_SIZE 10 +#endif + +/*! \class vector + * \brief Fixed sized vector implementation that mirroring + * + * \note Deprecated. Please use std::vector as default or + * re-define the vector class to match the std::vector + * interface by defining VECTOR_CLASS + + * \note Not recommended for use with custom objects as + * current implementation will construct N elements + * + * std::vector functionality. + * \brief Fixed sized vector compatible with std::vector. + * + * \note + * This differs from std::vector<> not just in memory allocation, + * but also in terms of when members are constructed, destroyed, + * and assigned instead of being copy constructed. + * + * \param T type of element contained in the vector. + * + * \param N maximum size of the vector. + */ +template +class CL_EXT_PREFIX__VERSION_1_1_DEPRECATED vector CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED +{ +private: + T data_[N]; + unsigned int size_; + +public: + //! \brief Constructs an empty vector with no memory allocated. + vector() : + size_(static_cast(0)) + {} + + //! \brief Deallocates the vector's memory and destroys all of its elements. + ~vector() + { + clear(); + } + + //! \brief Returns the number of elements currently contained. + unsigned int size(void) const + { + return size_; + } + + /*! \brief Empties the vector of all elements. + * \note + * This does not deallocate memory but will invoke destructors + * on contained elements. + */ + void clear() + { + while(!empty()) { + pop_back(); + } + } + + /*! \brief Appends an element after the last valid element. + * Calling this on a vector that has reached capacity will throw an + * exception if exceptions are enabled. + */ + void push_back (const T& x) + { + if (size() < N) { + new (&data_[size_]) T(x); + size_++; + } else { + detail::errHandler(CL_MEM_OBJECT_ALLOCATION_FAILURE, __VECTOR_CAPACITY_ERR); + } + } + + /*! \brief Removes the last valid element from the vector. + * Calling this on an empty vector will throw an exception + * if exceptions are enabled. + */ + void pop_back(void) + { + if (size_ != 0) { + --size_; + data_[size_].~T(); + } else { + detail::errHandler(CL_MEM_OBJECT_ALLOCATION_FAILURE, __VECTOR_CAPACITY_ERR); + } + } + + /*! \brief Constructs with a value copied from another. + * + * \param vec the vector to copy. + */ + vector(const vector& vec) : + size_(vec.size_) + { + if (size_ != 0) { + assign(vec.begin(), vec.end()); + } + } + + /*! \brief Constructs with a specified number of initial elements. + * + * \param size number of initial elements. + * + * \param val value of initial elements. + */ + vector(unsigned int size, const T& val = T()) : + size_(0) + { + for (unsigned int i = 0; i < size; i++) { + push_back(val); + } + } + + /*! \brief Overwrites the current content with that copied from another + * instance. + * + * \param rhs vector to copy. + * + * \returns a reference to this. + */ + vector& operator=(const vector& rhs) + { + if (this == &rhs) { + return *this; + } + + if (rhs.size_ != 0) { + assign(rhs.begin(), rhs.end()); + } else { + clear(); + } + + return *this; + } + + /*! \brief Tests equality against another instance. + * + * \param vec the vector against which to compare. + */ + bool operator==(vector &vec) + { + if (size() != vec.size()) { + return false; + } + + for( unsigned int i = 0; i < size(); ++i ) { + if( operator[](i) != vec[i] ) { + return false; + } + } + return true; + } + + //! \brief Conversion operator to T*. + operator T* () { return data_; } + + //! \brief Conversion operator to const T*. + operator const T* () const { return data_; } + + //! \brief Tests whether this instance has any elements. + bool empty (void) const + { + return size_==0; + } + + //! \brief Returns the maximum number of elements this instance can hold. + unsigned int max_size (void) const + { + return N; + } + + //! \brief Returns the maximum number of elements this instance can hold. + unsigned int capacity () const + { + return N; + } + + /*! \brief Returns a reference to a given element. + * + * \param index which element to access. * + * \note + * The caller is responsible for ensuring index is >= 0 and < size(). + */ + T& operator[](int index) + { + return data_[index]; + } + + /*! \brief Returns a const reference to a given element. + * + * \param index which element to access. + * + * \note + * The caller is responsible for ensuring index is >= 0 and < size(). + */ + const T& operator[](int index) const + { + return data_[index]; + } + + /*! \brief Assigns elements of the vector based on a source iterator range. + * + * \param start Beginning iterator of source range + * \param end Enditerator of source range + * + * \note + * Will throw an exception if exceptions are enabled and size exceeded. + */ + template + void assign(I start, I end) + { + clear(); + while(start != end) { + push_back(*start); + start++; + } + } + + /*! \class iterator + * \brief Const iterator class for vectors + */ + class iterator + { + private: + const vector *vec_; + int index_; + + /** + * Internal iterator constructor to capture reference + * to the vector it iterates over rather than taking + * the vector by copy. + */ + iterator (const vector &vec, int index) : + vec_(&vec) + { + if( !vec.empty() ) { + index_ = index; + } else { + index_ = -1; + } + } + + public: + iterator(void) : + index_(-1), + vec_(NULL) + { + } + + iterator(const iterator& rhs) : + vec_(rhs.vec_), + index_(rhs.index_) + { + } + + ~iterator(void) {} + + static iterator begin(const cl::vector &vec) + { + iterator i(vec, 0); + + return i; + } + + static iterator end(const cl::vector &vec) + { + iterator i(vec, vec.size()); + + return i; + } + + bool operator==(iterator i) + { + return ((vec_ == i.vec_) && + (index_ == i.index_)); + } + + bool operator!=(iterator i) + { + return (!(*this==i)); + } + + iterator& operator++() + { + ++index_; + return *this; + } + + iterator operator++(int) + { + iterator retVal(*this); + ++index_; + return retVal; + } + + iterator& operator--() + { + --index_; + return *this; + } + + iterator operator--(int) + { + iterator retVal(*this); + --index_; + return retVal; + } + + const T& operator *() const + { + return (*vec_)[index_]; + } + }; + + iterator begin(void) + { + return iterator::begin(*this); + } + + iterator begin(void) const + { + return iterator::begin(*this); + } + + iterator end(void) + { + return iterator::end(*this); + } + + iterator end(void) const + { + return iterator::end(*this); + } + + T& front(void) + { + return data_[0]; + } + + T& back(void) + { + return data_[size_]; + } + + const T& front(void) const + { + return data_[0]; + } + + const T& back(void) const + { + return data_[size_-1]; + } +}; +#endif // #if !defined(__USE_DEV_VECTOR) && !defined(__NO_STD_VECTOR) + + + + + +namespace detail { +#define __DEFAULT_NOT_INITIALIZED 1 +#define __DEFAULT_BEING_INITIALIZED 2 +#define __DEFAULT_INITIALIZED 4 + + /* + * Compare and exchange primitives are needed for handling of defaults + */ + inline int compare_exchange(volatile int * dest, int exchange, int comparand) + { +#ifdef _WIN32 + return (int)(InterlockedCompareExchange( + (volatile long*)dest, + (long)exchange, + (long)comparand)); +#elif defined(__APPLE__) || defined(__MACOSX) + return OSAtomicOr32Orig((uint32_t)exchange, (volatile uint32_t*)dest); +#else // !_WIN32 || defined(__APPLE__) || defined(__MACOSX) + return (__sync_val_compare_and_swap( + dest, + comparand, + exchange)); +#endif // !_WIN32 + } + + inline void fence() { +#ifdef _MSC_VER + _mm_mfence(); +#else + __sync_synchronize(); +#endif + } +} // namespace details + + +/*! \brief class used to interface between C++ and + * OpenCL C calls that require arrays of size_t values, whose + * size is known statically. + */ +template +class size_t +{ +private: + ::size_t data_[N]; + +public: + //! \brief Initialize size_t to all 0s + size_t() + { + for( int i = 0; i < N; ++i ) { + data_[i] = 0; + } + } + + ::size_t& operator[](int index) + { + return data_[index]; + } + + const ::size_t& operator[](int index) const + { + return data_[index]; + } + + //! \brief Conversion operator to T*. + operator ::size_t* () { return data_; } + + //! \brief Conversion operator to const T*. + operator const ::size_t* () const { return data_; } +}; + +namespace detail { + +// Generic getInfoHelper. The final parameter is used to guide overload +// resolution: the actual parameter passed is an int, which makes this +// a worse conversion sequence than a specialization that declares the +// parameter as an int. +template +inline cl_int getInfoHelper(Functor f, cl_uint name, T* param, long) +{ + return f(name, sizeof(T), param, NULL); +} + +// Specialized getInfoHelper for VECTOR_CLASS params +template +inline cl_int getInfoHelper(Func f, cl_uint name, VECTOR_CLASS* param, long) +{ + ::size_t required; + cl_int err = f(name, 0, NULL, &required); + if (err != CL_SUCCESS) { + return err; + } + + T* value = (T*) alloca(required); + err = f(name, required, value, NULL); + if (err != CL_SUCCESS) { + return err; + } + + param->assign(&value[0], &value[required/sizeof(T)]); + return CL_SUCCESS; +} + +/* Specialization for reference-counted types. This depends on the + * existence of Wrapper::cl_type, and none of the other types having the + * cl_type member. Note that simplify specifying the parameter as Wrapper + * does not work, because when using a derived type (e.g. Context) the generic + * template will provide a better match. + */ +template +inline cl_int getInfoHelper(Func f, cl_uint name, VECTOR_CLASS* param, int, typename T::cl_type = 0) +{ + ::size_t required; + cl_int err = f(name, 0, NULL, &required); + if (err != CL_SUCCESS) { + return err; + } + + typename T::cl_type * value = (typename T::cl_type *) alloca(required); + err = f(name, required, value, NULL); + if (err != CL_SUCCESS) { + return err; + } + + ::size_t elements = required / sizeof(typename T::cl_type); + param->assign(&value[0], &value[elements]); + for (::size_t i = 0; i < elements; i++) + { + if (value[i] != NULL) + { + err = (*param)[i].retain(); + if (err != CL_SUCCESS) { + return err; + } + } + } + return CL_SUCCESS; +} + +// Specialized for getInfo +template +inline cl_int getInfoHelper(Func f, cl_uint name, VECTOR_CLASS* param, int) +{ + cl_int err = f(name, param->size() * sizeof(char *), &(*param)[0], NULL); + + if (err != CL_SUCCESS) { + return err; + } + + return CL_SUCCESS; +} + +// Specialized GetInfoHelper for STRING_CLASS params +template +inline cl_int getInfoHelper(Func f, cl_uint name, STRING_CLASS* param, long) +{ + ::size_t required; + cl_int err = f(name, 0, NULL, &required); + if (err != CL_SUCCESS) { + return err; + } + + char* value = (char*) alloca(required); + err = f(name, required, value, NULL); + if (err != CL_SUCCESS) { + return err; + } + + *param = value; + return CL_SUCCESS; +} + +// Specialized GetInfoHelper for cl::size_t params +template +inline cl_int getInfoHelper(Func f, cl_uint name, size_t* param, long) +{ + ::size_t required; + cl_int err = f(name, 0, NULL, &required); + if (err != CL_SUCCESS) { + return err; + } + + ::size_t* value = (::size_t*) alloca(required); + err = f(name, required, value, NULL); + if (err != CL_SUCCESS) { + return err; + } + + for(int i = 0; i < N; ++i) { + (*param)[i] = value[i]; + } + + return CL_SUCCESS; +} + +template struct ReferenceHandler; + +/* Specialization for reference-counted types. This depends on the + * existence of Wrapper::cl_type, and none of the other types having the + * cl_type member. Note that simplify specifying the parameter as Wrapper + * does not work, because when using a derived type (e.g. Context) the generic + * template will provide a better match. + */ +template +inline cl_int getInfoHelper(Func f, cl_uint name, T* param, int, typename T::cl_type = 0) +{ + typename T::cl_type value; + cl_int err = f(name, sizeof(value), &value, NULL); + if (err != CL_SUCCESS) { + return err; + } + *param = value; + if (value != NULL) + { + err = param->retain(); + if (err != CL_SUCCESS) { + return err; + } + } + return CL_SUCCESS; +} + +#define __PARAM_NAME_INFO_1_0(F) \ + F(cl_platform_info, CL_PLATFORM_PROFILE, STRING_CLASS) \ + F(cl_platform_info, CL_PLATFORM_VERSION, STRING_CLASS) \ + F(cl_platform_info, CL_PLATFORM_NAME, STRING_CLASS) \ + F(cl_platform_info, CL_PLATFORM_VENDOR, STRING_CLASS) \ + F(cl_platform_info, CL_PLATFORM_EXTENSIONS, STRING_CLASS) \ + \ + F(cl_device_info, CL_DEVICE_TYPE, cl_device_type) \ + F(cl_device_info, CL_DEVICE_VENDOR_ID, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_COMPUTE_UNITS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_WORK_GROUP_SIZE, ::size_t) \ + F(cl_device_info, CL_DEVICE_MAX_WORK_ITEM_SIZES, VECTOR_CLASS< ::size_t>) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_CLOCK_FREQUENCY, cl_uint) \ + F(cl_device_info, CL_DEVICE_ADDRESS_BITS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_READ_IMAGE_ARGS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_WRITE_IMAGE_ARGS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_MEM_ALLOC_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_IMAGE2D_MAX_WIDTH, ::size_t) \ + F(cl_device_info, CL_DEVICE_IMAGE2D_MAX_HEIGHT, ::size_t) \ + F(cl_device_info, CL_DEVICE_IMAGE3D_MAX_WIDTH, ::size_t) \ + F(cl_device_info, CL_DEVICE_IMAGE3D_MAX_HEIGHT, ::size_t) \ + F(cl_device_info, CL_DEVICE_IMAGE3D_MAX_DEPTH, ::size_t) \ + F(cl_device_info, CL_DEVICE_IMAGE_SUPPORT, cl_bool) \ + F(cl_device_info, CL_DEVICE_MAX_PARAMETER_SIZE, ::size_t) \ + F(cl_device_info, CL_DEVICE_MAX_SAMPLERS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MEM_BASE_ADDR_ALIGN, cl_uint) \ + F(cl_device_info, CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE, cl_uint) \ + F(cl_device_info, CL_DEVICE_SINGLE_FP_CONFIG, cl_device_fp_config) \ + F(cl_device_info, CL_DEVICE_GLOBAL_MEM_CACHE_TYPE, cl_device_mem_cache_type) \ + F(cl_device_info, CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE, cl_uint)\ + F(cl_device_info, CL_DEVICE_GLOBAL_MEM_CACHE_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_GLOBAL_MEM_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_MAX_CONSTANT_ARGS, cl_uint) \ + F(cl_device_info, CL_DEVICE_LOCAL_MEM_TYPE, cl_device_local_mem_type) \ + F(cl_device_info, CL_DEVICE_LOCAL_MEM_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_ERROR_CORRECTION_SUPPORT, cl_bool) \ + F(cl_device_info, CL_DEVICE_PROFILING_TIMER_RESOLUTION, ::size_t) \ + F(cl_device_info, CL_DEVICE_ENDIAN_LITTLE, cl_bool) \ + F(cl_device_info, CL_DEVICE_AVAILABLE, cl_bool) \ + F(cl_device_info, CL_DEVICE_COMPILER_AVAILABLE, cl_bool) \ + F(cl_device_info, CL_DEVICE_EXECUTION_CAPABILITIES, cl_device_exec_capabilities) \ + F(cl_device_info, CL_DEVICE_QUEUE_PROPERTIES, cl_command_queue_properties) \ + F(cl_device_info, CL_DEVICE_PLATFORM, cl_platform_id) \ + F(cl_device_info, CL_DEVICE_NAME, STRING_CLASS) \ + F(cl_device_info, CL_DEVICE_VENDOR, STRING_CLASS) \ + F(cl_device_info, CL_DRIVER_VERSION, STRING_CLASS) \ + F(cl_device_info, CL_DEVICE_PROFILE, STRING_CLASS) \ + F(cl_device_info, CL_DEVICE_VERSION, STRING_CLASS) \ + F(cl_device_info, CL_DEVICE_EXTENSIONS, STRING_CLASS) \ + \ + F(cl_context_info, CL_CONTEXT_REFERENCE_COUNT, cl_uint) \ + F(cl_context_info, CL_CONTEXT_DEVICES, VECTOR_CLASS) \ + F(cl_context_info, CL_CONTEXT_PROPERTIES, VECTOR_CLASS) \ + \ + F(cl_event_info, CL_EVENT_COMMAND_QUEUE, cl::CommandQueue) \ + F(cl_event_info, CL_EVENT_COMMAND_TYPE, cl_command_type) \ + F(cl_event_info, CL_EVENT_REFERENCE_COUNT, cl_uint) \ + F(cl_event_info, CL_EVENT_COMMAND_EXECUTION_STATUS, cl_uint) \ + \ + F(cl_profiling_info, CL_PROFILING_COMMAND_QUEUED, cl_ulong) \ + F(cl_profiling_info, CL_PROFILING_COMMAND_SUBMIT, cl_ulong) \ + F(cl_profiling_info, CL_PROFILING_COMMAND_START, cl_ulong) \ + F(cl_profiling_info, CL_PROFILING_COMMAND_END, cl_ulong) \ + \ + F(cl_mem_info, CL_MEM_TYPE, cl_mem_object_type) \ + F(cl_mem_info, CL_MEM_FLAGS, cl_mem_flags) \ + F(cl_mem_info, CL_MEM_SIZE, ::size_t) \ + F(cl_mem_info, CL_MEM_HOST_PTR, void*) \ + F(cl_mem_info, CL_MEM_MAP_COUNT, cl_uint) \ + F(cl_mem_info, CL_MEM_REFERENCE_COUNT, cl_uint) \ + F(cl_mem_info, CL_MEM_CONTEXT, cl::Context) \ + \ + F(cl_image_info, CL_IMAGE_FORMAT, cl_image_format) \ + F(cl_image_info, CL_IMAGE_ELEMENT_SIZE, ::size_t) \ + F(cl_image_info, CL_IMAGE_ROW_PITCH, ::size_t) \ + F(cl_image_info, CL_IMAGE_SLICE_PITCH, ::size_t) \ + F(cl_image_info, CL_IMAGE_WIDTH, ::size_t) \ + F(cl_image_info, CL_IMAGE_HEIGHT, ::size_t) \ + F(cl_image_info, CL_IMAGE_DEPTH, ::size_t) \ + \ + F(cl_sampler_info, CL_SAMPLER_REFERENCE_COUNT, cl_uint) \ + F(cl_sampler_info, CL_SAMPLER_CONTEXT, cl::Context) \ + F(cl_sampler_info, CL_SAMPLER_NORMALIZED_COORDS, cl_addressing_mode) \ + F(cl_sampler_info, CL_SAMPLER_ADDRESSING_MODE, cl_filter_mode) \ + F(cl_sampler_info, CL_SAMPLER_FILTER_MODE, cl_bool) \ + \ + F(cl_program_info, CL_PROGRAM_REFERENCE_COUNT, cl_uint) \ + F(cl_program_info, CL_PROGRAM_CONTEXT, cl::Context) \ + F(cl_program_info, CL_PROGRAM_NUM_DEVICES, cl_uint) \ + F(cl_program_info, CL_PROGRAM_DEVICES, VECTOR_CLASS) \ + F(cl_program_info, CL_PROGRAM_SOURCE, STRING_CLASS) \ + F(cl_program_info, CL_PROGRAM_BINARY_SIZES, VECTOR_CLASS< ::size_t>) \ + F(cl_program_info, CL_PROGRAM_BINARIES, VECTOR_CLASS) \ + \ + F(cl_program_build_info, CL_PROGRAM_BUILD_STATUS, cl_build_status) \ + F(cl_program_build_info, CL_PROGRAM_BUILD_OPTIONS, STRING_CLASS) \ + F(cl_program_build_info, CL_PROGRAM_BUILD_LOG, STRING_CLASS) \ + \ + F(cl_kernel_info, CL_KERNEL_FUNCTION_NAME, STRING_CLASS) \ + F(cl_kernel_info, CL_KERNEL_NUM_ARGS, cl_uint) \ + F(cl_kernel_info, CL_KERNEL_REFERENCE_COUNT, cl_uint) \ + F(cl_kernel_info, CL_KERNEL_CONTEXT, cl::Context) \ + F(cl_kernel_info, CL_KERNEL_PROGRAM, cl::Program) \ + \ + F(cl_kernel_work_group_info, CL_KERNEL_WORK_GROUP_SIZE, ::size_t) \ + F(cl_kernel_work_group_info, CL_KERNEL_COMPILE_WORK_GROUP_SIZE, cl::size_t<3>) \ + F(cl_kernel_work_group_info, CL_KERNEL_LOCAL_MEM_SIZE, cl_ulong) \ + \ + F(cl_command_queue_info, CL_QUEUE_CONTEXT, cl::Context) \ + F(cl_command_queue_info, CL_QUEUE_DEVICE, cl::Device) \ + F(cl_command_queue_info, CL_QUEUE_REFERENCE_COUNT, cl_uint) \ + F(cl_command_queue_info, CL_QUEUE_PROPERTIES, cl_command_queue_properties) + +#if defined(CL_VERSION_1_1) +#define __PARAM_NAME_INFO_1_1(F) \ + F(cl_context_info, CL_CONTEXT_NUM_DEVICES, cl_uint)\ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_INT, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF, cl_uint) \ + F(cl_device_info, CL_DEVICE_DOUBLE_FP_CONFIG, cl_device_fp_config) \ + F(cl_device_info, CL_DEVICE_HALF_FP_CONFIG, cl_device_fp_config) \ + F(cl_device_info, CL_DEVICE_HOST_UNIFIED_MEMORY, cl_bool) \ + F(cl_device_info, CL_DEVICE_OPENCL_C_VERSION, STRING_CLASS) \ + \ + F(cl_mem_info, CL_MEM_ASSOCIATED_MEMOBJECT, cl::Memory) \ + F(cl_mem_info, CL_MEM_OFFSET, ::size_t) \ + \ + F(cl_kernel_work_group_info, CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE, ::size_t) \ + F(cl_kernel_work_group_info, CL_KERNEL_PRIVATE_MEM_SIZE, cl_ulong) \ + \ + F(cl_event_info, CL_EVENT_CONTEXT, cl::Context) +#endif // CL_VERSION_1_1 + + +#if defined(CL_VERSION_1_2) +#define __PARAM_NAME_INFO_1_2(F) \ + F(cl_image_info, CL_IMAGE_BUFFER, cl::Buffer) \ + \ + F(cl_program_info, CL_PROGRAM_NUM_KERNELS, ::size_t) \ + F(cl_program_info, CL_PROGRAM_KERNEL_NAMES, STRING_CLASS) \ + \ + F(cl_program_build_info, CL_PROGRAM_BINARY_TYPE, cl_program_binary_type) \ + \ + F(cl_kernel_info, CL_KERNEL_ATTRIBUTES, STRING_CLASS) \ + \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_ADDRESS_QUALIFIER, cl_kernel_arg_address_qualifier) \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_ACCESS_QUALIFIER, cl_kernel_arg_access_qualifier) \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_TYPE_NAME, STRING_CLASS) \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_NAME, STRING_CLASS) \ + \ + F(cl_device_info, CL_DEVICE_PARENT_DEVICE, cl_device_id) \ + F(cl_device_info, CL_DEVICE_PARTITION_PROPERTIES, VECTOR_CLASS) \ + F(cl_device_info, CL_DEVICE_PARTITION_TYPE, VECTOR_CLASS) \ + F(cl_device_info, CL_DEVICE_REFERENCE_COUNT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_INTEROP_USER_SYNC, ::size_t) \ + F(cl_device_info, CL_DEVICE_PARTITION_AFFINITY_DOMAIN, cl_device_affinity_domain) \ + F(cl_device_info, CL_DEVICE_BUILT_IN_KERNELS, STRING_CLASS) +#endif // #if defined(CL_VERSION_1_2) + +#if defined(USE_CL_DEVICE_FISSION) +#define __PARAM_NAME_DEVICE_FISSION(F) \ + F(cl_device_info, CL_DEVICE_PARENT_DEVICE_EXT, cl_device_id) \ + F(cl_device_info, CL_DEVICE_PARTITION_TYPES_EXT, VECTOR_CLASS) \ + F(cl_device_info, CL_DEVICE_AFFINITY_DOMAINS_EXT, VECTOR_CLASS) \ + F(cl_device_info, CL_DEVICE_REFERENCE_COUNT_EXT , cl_uint) \ + F(cl_device_info, CL_DEVICE_PARTITION_STYLE_EXT, VECTOR_CLASS) +#endif // USE_CL_DEVICE_FISSION + +template +struct param_traits {}; + +#define __CL_DECLARE_PARAM_TRAITS(token, param_name, T) \ +struct token; \ +template<> \ +struct param_traits \ +{ \ + enum { value = param_name }; \ + typedef T param_type; \ +}; + +__PARAM_NAME_INFO_1_0(__CL_DECLARE_PARAM_TRAITS) +#if defined(CL_VERSION_1_1) +__PARAM_NAME_INFO_1_1(__CL_DECLARE_PARAM_TRAITS) +#endif // CL_VERSION_1_1 +#if defined(CL_VERSION_1_2) +__PARAM_NAME_INFO_1_2(__CL_DECLARE_PARAM_TRAITS) +#endif // CL_VERSION_1_1 + +#if defined(USE_CL_DEVICE_FISSION) +__PARAM_NAME_DEVICE_FISSION(__CL_DECLARE_PARAM_TRAITS); +#endif // USE_CL_DEVICE_FISSION + +#ifdef CL_PLATFORM_ICD_SUFFIX_KHR +__CL_DECLARE_PARAM_TRAITS(cl_platform_info, CL_PLATFORM_ICD_SUFFIX_KHR, STRING_CLASS) +#endif + +#ifdef CL_DEVICE_PROFILING_TIMER_OFFSET_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_PROFILING_TIMER_OFFSET_AMD, cl_ulong) +#endif + +#ifdef CL_DEVICE_GLOBAL_FREE_MEMORY_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_GLOBAL_FREE_MEMORY_AMD, VECTOR_CLASS< ::size_t>) +#endif +#ifdef CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_SIMD_WIDTH_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_SIMD_WIDTH_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_WAVEFRONT_WIDTH_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_WAVEFRONT_WIDTH_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_LOCAL_MEM_BANKS_AMD +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_LOCAL_MEM_BANKS_AMD, cl_uint) +#endif + +#ifdef CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV, cl_uint) +#endif +#ifdef CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV, cl_uint) +#endif +#ifdef CL_DEVICE_REGISTERS_PER_BLOCK_NV +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_REGISTERS_PER_BLOCK_NV, cl_uint) +#endif +#ifdef CL_DEVICE_WARP_SIZE_NV +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_WARP_SIZE_NV, cl_uint) +#endif +#ifdef CL_DEVICE_GPU_OVERLAP_NV +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_GPU_OVERLAP_NV, cl_bool) +#endif +#ifdef CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV, cl_bool) +#endif +#ifdef CL_DEVICE_INTEGRATED_MEMORY_NV +__CL_DECLARE_PARAM_TRAITS(cl_device_info, CL_DEVICE_INTEGRATED_MEMORY_NV, cl_bool) +#endif + +// Convenience functions + +template +inline cl_int +getInfo(Func f, cl_uint name, T* param) +{ + return getInfoHelper(f, name, param, 0); +} + +template +struct GetInfoFunctor0 +{ + Func f_; const Arg0& arg0_; + cl_int operator ()( + cl_uint param, ::size_t size, void* value, ::size_t* size_ret) + { return f_(arg0_, param, size, value, size_ret); } +}; + +template +struct GetInfoFunctor1 +{ + Func f_; const Arg0& arg0_; const Arg1& arg1_; + cl_int operator ()( + cl_uint param, ::size_t size, void* value, ::size_t* size_ret) + { return f_(arg0_, arg1_, param, size, value, size_ret); } +}; + +template +inline cl_int +getInfo(Func f, const Arg0& arg0, cl_uint name, T* param) +{ + GetInfoFunctor0 f0 = { f, arg0 }; + return getInfoHelper(f0, name, param, 0); +} + +template +inline cl_int +getInfo(Func f, const Arg0& arg0, const Arg1& arg1, cl_uint name, T* param) +{ + GetInfoFunctor1 f0 = { f, arg0, arg1 }; + return getInfoHelper(f0, name, param, 0); +} + +template +struct ReferenceHandler +{ }; + +#if defined(CL_VERSION_1_2) +/** + * OpenCL 1.2 devices do have retain/release. + */ +template <> +struct ReferenceHandler +{ + /** + * Retain the device. + * \param device A valid device created using createSubDevices + * \return + * CL_SUCCESS if the function executed successfully. + * CL_INVALID_DEVICE if device was not a valid subdevice + * CL_OUT_OF_RESOURCES + * CL_OUT_OF_HOST_MEMORY + */ + static cl_int retain(cl_device_id device) + { return ::clRetainDevice(device); } + /** + * Retain the device. + * \param device A valid device created using createSubDevices + * \return + * CL_SUCCESS if the function executed successfully. + * CL_INVALID_DEVICE if device was not a valid subdevice + * CL_OUT_OF_RESOURCES + * CL_OUT_OF_HOST_MEMORY + */ + static cl_int release(cl_device_id device) + { return ::clReleaseDevice(device); } +}; +#else // #if defined(CL_VERSION_1_2) +/** + * OpenCL 1.1 devices do not have retain/release. + */ +template <> +struct ReferenceHandler +{ + // cl_device_id does not have retain(). + static cl_int retain(cl_device_id) + { return CL_SUCCESS; } + // cl_device_id does not have release(). + static cl_int release(cl_device_id) + { return CL_SUCCESS; } +}; +#endif // #if defined(CL_VERSION_1_2) + +template <> +struct ReferenceHandler +{ + // cl_platform_id does not have retain(). + static cl_int retain(cl_platform_id) + { return CL_SUCCESS; } + // cl_platform_id does not have release(). + static cl_int release(cl_platform_id) + { return CL_SUCCESS; } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_context context) + { return ::clRetainContext(context); } + static cl_int release(cl_context context) + { return ::clReleaseContext(context); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_command_queue queue) + { return ::clRetainCommandQueue(queue); } + static cl_int release(cl_command_queue queue) + { return ::clReleaseCommandQueue(queue); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_mem memory) + { return ::clRetainMemObject(memory); } + static cl_int release(cl_mem memory) + { return ::clReleaseMemObject(memory); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_sampler sampler) + { return ::clRetainSampler(sampler); } + static cl_int release(cl_sampler sampler) + { return ::clReleaseSampler(sampler); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_program program) + { return ::clRetainProgram(program); } + static cl_int release(cl_program program) + { return ::clReleaseProgram(program); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_kernel kernel) + { return ::clRetainKernel(kernel); } + static cl_int release(cl_kernel kernel) + { return ::clReleaseKernel(kernel); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_event event) + { return ::clRetainEvent(event); } + static cl_int release(cl_event event) + { return ::clReleaseEvent(event); } +}; + + +// Extracts version number with major in the upper 16 bits, minor in the lower 16 +static cl_uint getVersion(const char *versionInfo) +{ + int highVersion = 0; + int lowVersion = 0; + int index = 7; + while(versionInfo[index] != '.' ) { + highVersion *= 10; + highVersion += versionInfo[index]-'0'; + ++index; + } + ++index; + while(versionInfo[index] != ' ' ) { + lowVersion *= 10; + lowVersion += versionInfo[index]-'0'; + ++index; + } + return (highVersion << 16) | lowVersion; +} + +static cl_uint getPlatformVersion(cl_platform_id platform) +{ + ::size_t size = 0; + clGetPlatformInfo(platform, CL_PLATFORM_VERSION, 0, NULL, &size); + char *versionInfo = (char *) alloca(size); + clGetPlatformInfo(platform, CL_PLATFORM_VERSION, size, &versionInfo[0], &size); + return getVersion(versionInfo); +} + +static cl_uint getDevicePlatformVersion(cl_device_id device) +{ + cl_platform_id platform; + clGetDeviceInfo(device, CL_DEVICE_PLATFORM, sizeof(platform), &platform, NULL); + return getPlatformVersion(platform); +} + +#if defined(CL_VERSION_1_2) && defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +static cl_uint getContextPlatformVersion(cl_context context) +{ + // The platform cannot be queried directly, so we first have to grab a + // device and obtain its context + ::size_t size = 0; + clGetContextInfo(context, CL_CONTEXT_DEVICES, 0, NULL, &size); + if (size == 0) + return 0; + cl_device_id *devices = (cl_device_id *) alloca(size); + clGetContextInfo(context, CL_CONTEXT_DEVICES, size, devices, NULL); + return getDevicePlatformVersion(devices[0]); +} +#endif // #if defined(CL_VERSION_1_2) && defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + +template +class Wrapper +{ +public: + typedef T cl_type; + +protected: + cl_type object_; + +public: + Wrapper() : object_(NULL) { } + + Wrapper(const cl_type &obj) : object_(obj) { } + + ~Wrapper() + { + if (object_ != NULL) { release(); } + } + + Wrapper(const Wrapper& rhs) + { + object_ = rhs.object_; + if (object_ != NULL) { detail::errHandler(retain(), __RETAIN_ERR); } + } + + Wrapper& operator = (const Wrapper& rhs) + { + if (object_ != NULL) { detail::errHandler(release(), __RELEASE_ERR); } + object_ = rhs.object_; + if (object_ != NULL) { detail::errHandler(retain(), __RETAIN_ERR); } + return *this; + } + + Wrapper& operator = (const cl_type &rhs) + { + if (object_ != NULL) { detail::errHandler(release(), __RELEASE_ERR); } + object_ = rhs; + return *this; + } + + cl_type operator ()() const { return object_; } + + cl_type& operator ()() { return object_; } + +protected: + template + friend inline cl_int getInfoHelper(Func, cl_uint, U*, int, typename U::cl_type); + + cl_int retain() const + { + return ReferenceHandler::retain(object_); + } + + cl_int release() const + { + return ReferenceHandler::release(object_); + } +}; + +template <> +class Wrapper +{ +public: + typedef cl_device_id cl_type; + +protected: + cl_type object_; + bool referenceCountable_; + + static bool isReferenceCountable(cl_device_id device) + { + bool retVal = false; + if (device != NULL) { + int version = getDevicePlatformVersion(device); + if(version > ((1 << 16) + 1)) { + retVal = true; + } + } + return retVal; + } + +public: + Wrapper() : object_(NULL), referenceCountable_(false) + { + } + + Wrapper(const cl_type &obj) : object_(obj), referenceCountable_(false) + { + referenceCountable_ = isReferenceCountable(obj); + } + + ~Wrapper() + { + if (object_ != NULL) { release(); } + } + + Wrapper(const Wrapper& rhs) + { + object_ = rhs.object_; + referenceCountable_ = isReferenceCountable(object_); + if (object_ != NULL) { detail::errHandler(retain(), __RETAIN_ERR); } + } + + Wrapper& operator = (const Wrapper& rhs) + { + if (object_ != NULL) { detail::errHandler(release(), __RELEASE_ERR); } + object_ = rhs.object_; + referenceCountable_ = rhs.referenceCountable_; + if (object_ != NULL) { detail::errHandler(retain(), __RETAIN_ERR); } + return *this; + } + + Wrapper& operator = (const cl_type &rhs) + { + if (object_ != NULL) { detail::errHandler(release(), __RELEASE_ERR); } + object_ = rhs; + referenceCountable_ = isReferenceCountable(object_); + return *this; + } + + cl_type operator ()() const { return object_; } + + cl_type& operator ()() { return object_; } + +protected: + template + friend inline cl_int getInfoHelper(Func, cl_uint, U*, int, typename U::cl_type); + + template + friend inline cl_int getInfoHelper(Func, cl_uint, VECTOR_CLASS*, int, typename U::cl_type); + + cl_int retain() const + { + if( referenceCountable_ ) { + return ReferenceHandler::retain(object_); + } + else { + return CL_SUCCESS; + } + } + + cl_int release() const + { + if( referenceCountable_ ) { + return ReferenceHandler::release(object_); + } + else { + return CL_SUCCESS; + } + } +}; + +} // namespace detail +//! \endcond + +/*! \stuct ImageFormat + * \brief Adds constructors and member functions for cl_image_format. + * + * \see cl_image_format + */ +struct ImageFormat : public cl_image_format +{ + //! \brief Default constructor - performs no initialization. + ImageFormat(){} + + //! \brief Initializing constructor. + ImageFormat(cl_channel_order order, cl_channel_type type) + { + image_channel_order = order; + image_channel_data_type = type; + } + + //! \brief Assignment operator. + ImageFormat& operator = (const ImageFormat& rhs) + { + if (this != &rhs) { + this->image_channel_data_type = rhs.image_channel_data_type; + this->image_channel_order = rhs.image_channel_order; + } + return *this; + } +}; + +/*! \brief Class interface for cl_device_id. + * + * \note Copies of these objects are inexpensive, since they don't 'own' + * any underlying resources or data structures. + * + * \see cl_device_id + */ +class Device : public detail::Wrapper +{ +public: + //! \brief Default constructor - initializes to NULL. + Device() : detail::Wrapper() { } + + /*! \brief Copy constructor. + * + * This simply copies the device ID value, which is an inexpensive operation. + */ + Device(const Device& device) : detail::Wrapper(device) { } + + /*! \brief Constructor from cl_device_id. + * + * This simply copies the device ID value, which is an inexpensive operation. + */ + Device(const cl_device_id &device) : detail::Wrapper(device) { } + + /*! \brief Returns the first device on the default context. + * + * \see Context::getDefault() + */ + static Device getDefault(cl_int * err = NULL); + + /*! \brief Assignment operator from Device. + * + * This simply copies the device ID value, which is an inexpensive operation. + */ + Device& operator = (const Device& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment operator from cl_device_id. + * + * This simply copies the device ID value, which is an inexpensive operation. + */ + Device& operator = (const cl_device_id& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetDeviceInfo(). + template + cl_int getInfo(cl_device_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetDeviceInfo, object_, name, param), + __GET_DEVICE_INFO_ERR); + } + + //! \brief Wrapper for clGetDeviceInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_device_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /** + * CL 1.2 version + */ +#if defined(CL_VERSION_1_2) + //! \brief Wrapper for clCreateSubDevicesEXT(). + cl_int createSubDevices( + const cl_device_partition_property * properties, + VECTOR_CLASS* devices) + { + cl_uint n = 0; + cl_int err = clCreateSubDevices(object_, properties, 0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_SUB_DEVICES); + } + + cl_device_id* ids = (cl_device_id*) alloca(n * sizeof(cl_device_id)); + err = clCreateSubDevices(object_, properties, n, ids, NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_SUB_DEVICES); + } + + devices->assign(&ids[0], &ids[n]); + return CL_SUCCESS; + } +#endif // #if defined(CL_VERSION_1_2) + +/** + * CL 1.1 version that uses device fission. + */ +#if defined(CL_VERSION_1_1) +#if defined(USE_CL_DEVICE_FISSION) + cl_int createSubDevices( + const cl_device_partition_property_ext * properties, + VECTOR_CLASS* devices) + { + typedef CL_API_ENTRY cl_int + ( CL_API_CALL * PFN_clCreateSubDevicesEXT)( + cl_device_id /*in_device*/, + const cl_device_partition_property_ext * /* properties */, + cl_uint /*num_entries*/, + cl_device_id * /*out_devices*/, + cl_uint * /*num_devices*/ ) CL_EXT_SUFFIX__VERSION_1_1; + + static PFN_clCreateSubDevicesEXT pfn_clCreateSubDevicesEXT = NULL; + __INIT_CL_EXT_FCN_PTR(clCreateSubDevicesEXT); + + cl_uint n = 0; + cl_int err = pfn_clCreateSubDevicesEXT(object_, properties, 0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_SUB_DEVICES); + } + + cl_device_id* ids = (cl_device_id*) alloca(n * sizeof(cl_device_id)); + err = pfn_clCreateSubDevicesEXT(object_, properties, n, ids, NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_SUB_DEVICES); + } + + devices->assign(&ids[0], &ids[n]); + return CL_SUCCESS; + } +#endif // #if defined(USE_CL_DEVICE_FISSION) +#endif // #if defined(CL_VERSION_1_1) +}; + +/*! \brief Class interface for cl_platform_id. + * + * \note Copies of these objects are inexpensive, since they don't 'own' + * any underlying resources or data structures. + * + * \see cl_platform_id + */ +class Platform : public detail::Wrapper +{ +public: + //! \brief Default constructor - initializes to NULL. + Platform() : detail::Wrapper() { } + + /*! \brief Copy constructor. + * + * This simply copies the platform ID value, which is an inexpensive operation. + */ + Platform(const Platform& platform) : detail::Wrapper(platform) { } + + /*! \brief Constructor from cl_platform_id. + * + * This simply copies the platform ID value, which is an inexpensive operation. + */ + Platform(const cl_platform_id &platform) : detail::Wrapper(platform) { } + + /*! \brief Assignment operator from Platform. + * + * This simply copies the platform ID value, which is an inexpensive operation. + */ + Platform& operator = (const Platform& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment operator from cl_platform_id. + * + * This simply copies the platform ID value, which is an inexpensive operation. + */ + Platform& operator = (const cl_platform_id& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetPlatformInfo(). + cl_int getInfo(cl_platform_info name, STRING_CLASS* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetPlatformInfo, object_, name, param), + __GET_PLATFORM_INFO_ERR); + } + + //! \brief Wrapper for clGetPlatformInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_platform_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /*! \brief Gets a list of devices for this platform. + * + * Wraps clGetDeviceIDs(). + */ + cl_int getDevices( + cl_device_type type, + VECTOR_CLASS* devices) const + { + cl_uint n = 0; + if( devices == NULL ) { + return detail::errHandler(CL_INVALID_ARG_VALUE, __GET_DEVICE_IDS_ERR); + } + cl_int err = ::clGetDeviceIDs(object_, type, 0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_DEVICE_IDS_ERR); + } + + cl_device_id* ids = (cl_device_id*) alloca(n * sizeof(cl_device_id)); + err = ::clGetDeviceIDs(object_, type, n, ids, NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_DEVICE_IDS_ERR); + } + + devices->assign(&ids[0], &ids[n]); + return CL_SUCCESS; + } + +#if defined(USE_DX_INTEROP) + /*! \brief Get the list of available D3D10 devices. + * + * \param d3d_device_source. + * + * \param d3d_object. + * + * \param d3d_device_set. + * + * \param devices returns a vector of OpenCL D3D10 devices found. The cl::Device + * values returned in devices can be used to identify a specific OpenCL + * device. If \a devices argument is NULL, this argument is ignored. + * + * \return One of the following values: + * - CL_SUCCESS if the function is executed successfully. + * + * The application can query specific capabilities of the OpenCL device(s) + * returned by cl::getDevices. This can be used by the application to + * determine which device(s) to use. + * + * \note In the case that exceptions are enabled and a return value + * other than CL_SUCCESS is generated, then cl::Error exception is + * generated. + */ + cl_int getDevices( + cl_d3d10_device_source_khr d3d_device_source, + void * d3d_object, + cl_d3d10_device_set_khr d3d_device_set, + VECTOR_CLASS* devices) const + { + typedef CL_API_ENTRY cl_int (CL_API_CALL *PFN_clGetDeviceIDsFromD3D10KHR)( + cl_platform_id platform, + cl_d3d10_device_source_khr d3d_device_source, + void * d3d_object, + cl_d3d10_device_set_khr d3d_device_set, + cl_uint num_entries, + cl_device_id * devices, + cl_uint* num_devices); + + if( devices == NULL ) { + return detail::errHandler(CL_INVALID_ARG_VALUE, __GET_DEVICE_IDS_ERR); + } + + static PFN_clGetDeviceIDsFromD3D10KHR pfn_clGetDeviceIDsFromD3D10KHR = NULL; + __INIT_CL_EXT_FCN_PTR_PLATFORM(object_, clGetDeviceIDsFromD3D10KHR); + + cl_uint n = 0; + cl_int err = pfn_clGetDeviceIDsFromD3D10KHR( + object_, + d3d_device_source, + d3d_object, + d3d_device_set, + 0, + NULL, + &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_DEVICE_IDS_ERR); + } + + cl_device_id* ids = (cl_device_id*) alloca(n * sizeof(cl_device_id)); + err = pfn_clGetDeviceIDsFromD3D10KHR( + object_, + d3d_device_source, + d3d_object, + d3d_device_set, + n, + ids, + NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_DEVICE_IDS_ERR); + } + + devices->assign(&ids[0], &ids[n]); + return CL_SUCCESS; + } +#endif + + /*! \brief Gets a list of available platforms. + * + * Wraps clGetPlatformIDs(). + */ + static cl_int get( + VECTOR_CLASS* platforms) + { + cl_uint n = 0; + + if( platforms == NULL ) { + return detail::errHandler(CL_INVALID_ARG_VALUE, __GET_PLATFORM_IDS_ERR); + } + + cl_int err = ::clGetPlatformIDs(0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_PLATFORM_IDS_ERR); + } + + cl_platform_id* ids = (cl_platform_id*) alloca( + n * sizeof(cl_platform_id)); + err = ::clGetPlatformIDs(n, ids, NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_PLATFORM_IDS_ERR); + } + + platforms->assign(&ids[0], &ids[n]); + return CL_SUCCESS; + } + + /*! \brief Gets the first available platform. + * + * Wraps clGetPlatformIDs(), returning the first result. + */ + static cl_int get( + Platform * platform) + { + cl_uint n = 0; + + if( platform == NULL ) { + return detail::errHandler(CL_INVALID_ARG_VALUE, __GET_PLATFORM_IDS_ERR); + } + + cl_int err = ::clGetPlatformIDs(0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_PLATFORM_IDS_ERR); + } + + cl_platform_id* ids = (cl_platform_id*) alloca( + n * sizeof(cl_platform_id)); + err = ::clGetPlatformIDs(n, ids, NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_PLATFORM_IDS_ERR); + } + + *platform = ids[0]; + return CL_SUCCESS; + } + + /*! \brief Gets the first available platform, returning it by value. + * + * Wraps clGetPlatformIDs(), returning the first result. + */ + static Platform get( + cl_int * errResult = NULL) + { + Platform platform; + cl_uint n = 0; + cl_int err = ::clGetPlatformIDs(0, NULL, &n); + if (err != CL_SUCCESS) { + detail::errHandler(err, __GET_PLATFORM_IDS_ERR); + if (errResult != NULL) { + *errResult = err; + } + } + + cl_platform_id* ids = (cl_platform_id*) alloca( + n * sizeof(cl_platform_id)); + err = ::clGetPlatformIDs(n, ids, NULL); + + if (err != CL_SUCCESS) { + detail::errHandler(err, __GET_PLATFORM_IDS_ERR); + } + + if (errResult != NULL) { + *errResult = err; + } + + return ids[0]; + } + + static Platform getDefault( + cl_int *errResult = NULL ) + { + return get(errResult); + } + + +#if defined(CL_VERSION_1_2) + //! \brief Wrapper for clUnloadCompiler(). + cl_int + unloadCompiler() + { + return ::clUnloadPlatformCompiler(object_); + } +#endif // #if defined(CL_VERSION_1_2) +}; // class Platform + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) || (defined(CL_VERSION_1_1) && !defined(CL_VERSION_1_2)) +/** + * Unload the OpenCL compiler. + * \note Deprecated for OpenCL 1.2. Use Platform::unloadCompiler instead. + */ +inline CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int +UnloadCompiler() CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; +inline cl_int +UnloadCompiler() +{ + return ::clUnloadCompiler(); +} +#endif // #if defined(CL_VERSION_1_1) + +/*! \brief Class interface for cl_context. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_context as the original. For details, see + * clRetainContext() and clReleaseContext(). + * + * \see cl_context + */ +class Context + : public detail::Wrapper +{ +private: + static volatile int default_initialized_; + static Context default_; + static volatile cl_int default_error_; +public: + /*! \brief Destructor. + * + * This calls clReleaseContext() on the value held by this instance. + */ + ~Context() { } + + /*! \brief Constructs a context including a list of specified devices. + * + * Wraps clCreateContext(). + */ + Context( + const VECTOR_CLASS& devices, + cl_context_properties* properties = NULL, + void (CL_CALLBACK * notifyFptr)( + const char *, + const void *, + ::size_t, + void *) = NULL, + void* data = NULL, + cl_int* err = NULL) + { + cl_int error; + + ::size_t numDevices = devices.size(); + cl_device_id* deviceIDs = (cl_device_id*) alloca(numDevices * sizeof(cl_device_id)); + for( ::size_t deviceIndex = 0; deviceIndex < numDevices; ++deviceIndex ) { + deviceIDs[deviceIndex] = (devices[deviceIndex])(); + } + + object_ = ::clCreateContext( + properties, (cl_uint) numDevices, + deviceIDs, + notifyFptr, data, &error); + + detail::errHandler(error, __CREATE_CONTEXT_ERR); + if (err != NULL) { + *err = error; + } + } + + Context( + const Device& device, + cl_context_properties* properties = NULL, + void (CL_CALLBACK * notifyFptr)( + const char *, + const void *, + ::size_t, + void *) = NULL, + void* data = NULL, + cl_int* err = NULL) + { + cl_int error; + + cl_device_id deviceID = device(); + + object_ = ::clCreateContext( + properties, 1, + &deviceID, + notifyFptr, data, &error); + + detail::errHandler(error, __CREATE_CONTEXT_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Constructs a context including all or a subset of devices of a specified type. + * + * Wraps clCreateContextFromType(). + */ + Context( + cl_device_type type, + cl_context_properties* properties = NULL, + void (CL_CALLBACK * notifyFptr)( + const char *, + const void *, + ::size_t, + void *) = NULL, + void* data = NULL, + cl_int* err = NULL) + { + cl_int error; + +#if !defined(__APPLE__) || !defined(__MACOS) + cl_context_properties prop[4] = {CL_CONTEXT_PLATFORM, 0, 0, 0 }; + + if (properties == NULL) { + // Get a valid platform ID as we cannot send in a blank one + VECTOR_CLASS platforms; + error = Platform::get(&platforms); + if (error != CL_SUCCESS) { + detail::errHandler(error, __CREATE_CONTEXT_FROM_TYPE_ERR); + if (err != NULL) { + *err = error; + } + return; + } + + // Check the platforms we found for a device of our specified type + cl_context_properties platform_id = 0; + for (unsigned int i = 0; i < platforms.size(); i++) { + + VECTOR_CLASS devices; + +#if defined(__CL_ENABLE_EXCEPTIONS) + try { +#endif + + error = platforms[i].getDevices(type, &devices); + +#if defined(__CL_ENABLE_EXCEPTIONS) + } catch (Error) {} + // Catch if exceptions are enabled as we don't want to exit if first platform has no devices of type + // We do error checking next anyway, and can throw there if needed +#endif + + // Only squash CL_SUCCESS and CL_DEVICE_NOT_FOUND + if (error != CL_SUCCESS && error != CL_DEVICE_NOT_FOUND) { + detail::errHandler(error, __CREATE_CONTEXT_FROM_TYPE_ERR); + if (err != NULL) { + *err = error; + } + } + + if (devices.size() > 0) { + platform_id = (cl_context_properties)platforms[i](); + break; + } + } + + if (platform_id == 0) { + detail::errHandler(CL_DEVICE_NOT_FOUND, __CREATE_CONTEXT_FROM_TYPE_ERR); + if (err != NULL) { + *err = CL_DEVICE_NOT_FOUND; + } + return; + } + + prop[1] = platform_id; + properties = &prop[0]; + } +#endif + object_ = ::clCreateContextFromType( + properties, type, notifyFptr, data, &error); + + detail::errHandler(error, __CREATE_CONTEXT_FROM_TYPE_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Returns a singleton context including all devices of CL_DEVICE_TYPE_DEFAULT. + * + * \note All calls to this function return the same cl_context as the first. + */ + static Context getDefault(cl_int * err = NULL) + { + int state = detail::compare_exchange( + &default_initialized_, + __DEFAULT_BEING_INITIALIZED, __DEFAULT_NOT_INITIALIZED); + + if (state & __DEFAULT_INITIALIZED) { + if (err != NULL) { + *err = default_error_; + } + return default_; + } + + if (state & __DEFAULT_BEING_INITIALIZED) { + // Assume writes will propagate eventually... + while(default_initialized_ != __DEFAULT_INITIALIZED) { + detail::fence(); + } + + if (err != NULL) { + *err = default_error_; + } + return default_; + } + + cl_int error; + default_ = Context( + CL_DEVICE_TYPE_DEFAULT, + NULL, + NULL, + NULL, + &error); + + detail::fence(); + + default_error_ = error; + // Assume writes will propagate eventually... + default_initialized_ = __DEFAULT_INITIALIZED; + + detail::fence(); + + if (err != NULL) { + *err = default_error_; + } + return default_; + + } + + //! \brief Default constructor - initializes to NULL. + Context() : detail::Wrapper() { } + + /*! \brief Copy constructor. + * + * This calls clRetainContext() on the parameter's cl_context. + */ + Context(const Context& context) : detail::Wrapper(context) { } + + /*! \brief Constructor from cl_context - takes ownership. + * + * This effectively transfers ownership of a refcount on the cl_context + * into the new Context object. + */ + __CL_EXPLICIT_CONSTRUCTORS Context(const cl_context& context) : detail::Wrapper(context) { } + + /*! \brief Assignment operator from Context. + * + * This calls clRetainContext() on the parameter and clReleaseContext() on + * the previous value held by this instance. + */ + Context& operator = (const Context& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment operator from cl_context - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseContext() on the value previously held by this instance. + */ + Context& operator = (const cl_context& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetContextInfo(). + template + cl_int getInfo(cl_context_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetContextInfo, object_, name, param), + __GET_CONTEXT_INFO_ERR); + } + + //! \brief Wrapper for clGetContextInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_context_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /*! \brief Gets a list of supported image formats. + * + * Wraps clGetSupportedImageFormats(). + */ + cl_int getSupportedImageFormats( + cl_mem_flags flags, + cl_mem_object_type type, + VECTOR_CLASS* formats) const + { + cl_uint numEntries; + cl_int err = ::clGetSupportedImageFormats( + object_, + flags, + type, + 0, + NULL, + &numEntries); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_SUPPORTED_IMAGE_FORMATS_ERR); + } + + ImageFormat* value = (ImageFormat*) + alloca(numEntries * sizeof(ImageFormat)); + err = ::clGetSupportedImageFormats( + object_, + flags, + type, + numEntries, + (cl_image_format*) value, + NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_SUPPORTED_IMAGE_FORMATS_ERR); + } + + formats->assign(&value[0], &value[numEntries]); + return CL_SUCCESS; + } +}; + +inline Device Device::getDefault(cl_int * err) +{ + cl_int error; + Device device; + + Context context = Context::getDefault(&error); + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + + if (error != CL_SUCCESS) { + if (err != NULL) { + *err = error; + } + } + else { + device = context.getInfo()[0]; + if (err != NULL) { + *err = CL_SUCCESS; + } + } + + return device; +} + + +#ifdef _WIN32 +__declspec(selectany) volatile int Context::default_initialized_ = __DEFAULT_NOT_INITIALIZED; +__declspec(selectany) Context Context::default_; +__declspec(selectany) volatile cl_int Context::default_error_ = CL_SUCCESS; +#else +__attribute__((weak)) volatile int Context::default_initialized_ = __DEFAULT_NOT_INITIALIZED; +__attribute__((weak)) Context Context::default_; +__attribute__((weak)) volatile cl_int Context::default_error_ = CL_SUCCESS; +#endif + +/*! \brief Class interface for cl_event. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_event as the original. For details, see + * clRetainEvent() and clReleaseEvent(). + * + * \see cl_event + */ +class Event : public detail::Wrapper +{ +public: + /*! \brief Destructor. + * + * This calls clReleaseEvent() on the value held by this instance. + */ + ~Event() { } + + //! \brief Default constructor - initializes to NULL. + Event() : detail::Wrapper() { } + + /*! \brief Copy constructor. + * + * This calls clRetainEvent() on the parameter's cl_event. + */ + Event(const Event& event) : detail::Wrapper(event) { } + + /*! \brief Constructor from cl_event - takes ownership. + * + * This effectively transfers ownership of a refcount on the cl_event + * into the new Event object. + */ + Event(const cl_event& event) : detail::Wrapper(event) { } + + /*! \brief Assignment operator from cl_event - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseEvent() on the value previously held by this instance. + */ + Event& operator = (const Event& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment operator from cl_event. + * + * This calls clRetainEvent() on the parameter and clReleaseEvent() on + * the previous value held by this instance. + */ + Event& operator = (const cl_event& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetEventInfo(). + template + cl_int getInfo(cl_event_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetEventInfo, object_, name, param), + __GET_EVENT_INFO_ERR); + } + + //! \brief Wrapper for clGetEventInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_event_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + //! \brief Wrapper for clGetEventProfilingInfo(). + template + cl_int getProfilingInfo(cl_profiling_info name, T* param) const + { + return detail::errHandler(detail::getInfo( + &::clGetEventProfilingInfo, object_, name, param), + __GET_EVENT_PROFILE_INFO_ERR); + } + + //! \brief Wrapper for clGetEventProfilingInfo() that returns by value. + template typename + detail::param_traits::param_type + getProfilingInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_profiling_info, name>::param_type param; + cl_int result = getProfilingInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /*! \brief Blocks the calling thread until this event completes. + * + * Wraps clWaitForEvents(). + */ + cl_int wait() const + { + return detail::errHandler( + ::clWaitForEvents(1, &object_), + __WAIT_FOR_EVENTS_ERR); + } + +#if defined(CL_VERSION_1_1) + /*! \brief Registers a user callback function for a specific command execution status. + * + * Wraps clSetEventCallback(). + */ + cl_int setCallback( + cl_int type, + void (CL_CALLBACK * pfn_notify)(cl_event, cl_int, void *), + void * user_data = NULL) + { + return detail::errHandler( + ::clSetEventCallback( + object_, + type, + pfn_notify, + user_data), + __SET_EVENT_CALLBACK_ERR); + } +#endif + + /*! \brief Blocks the calling thread until every event specified is complete. + * + * Wraps clWaitForEvents(). + */ + static cl_int + waitForEvents(const VECTOR_CLASS& events) + { + return detail::errHandler( + ::clWaitForEvents( + (cl_uint) events.size(), (cl_event*)&events.front()), + __WAIT_FOR_EVENTS_ERR); + } +}; + +#if defined(CL_VERSION_1_1) +/*! \brief Class interface for user events (a subset of cl_event's). + * + * See Event for details about copy semantics, etc. + */ +class UserEvent : public Event +{ +public: + /*! \brief Constructs a user event on a given context. + * + * Wraps clCreateUserEvent(). + */ + UserEvent( + const Context& context, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateUserEvent( + context(), + &error); + + detail::errHandler(error, __CREATE_USER_EVENT_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + UserEvent() : Event() { } + + //! \brief Copy constructor - performs shallow copy. + UserEvent(const UserEvent& event) : Event(event) { } + + //! \brief Assignment Operator - performs shallow copy. + UserEvent& operator = (const UserEvent& rhs) + { + if (this != &rhs) { + Event::operator=(rhs); + } + return *this; + } + + /*! \brief Sets the execution status of a user event object. + * + * Wraps clSetUserEventStatus(). + */ + cl_int setStatus(cl_int status) + { + return detail::errHandler( + ::clSetUserEventStatus(object_,status), + __SET_USER_EVENT_STATUS_ERR); + } +}; +#endif + +/*! \brief Blocks the calling thread until every event specified is complete. + * + * Wraps clWaitForEvents(). + */ +inline static cl_int +WaitForEvents(const VECTOR_CLASS& events) +{ + return detail::errHandler( + ::clWaitForEvents( + (cl_uint) events.size(), (cl_event*)&events.front()), + __WAIT_FOR_EVENTS_ERR); +} + +/*! \brief Class interface for cl_mem. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_mem as the original. For details, see + * clRetainMemObject() and clReleaseMemObject(). + * + * \see cl_mem + */ +class Memory : public detail::Wrapper +{ +public: + + /*! \brief Destructor. + * + * This calls clReleaseMemObject() on the value held by this instance. + */ + ~Memory() {} + + //! \brief Default constructor - initializes to NULL. + Memory() : detail::Wrapper() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * This calls clRetainMemObject() on the parameter's cl_mem. + */ + Memory(const Memory& memory) : detail::Wrapper(memory) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * This effectively transfers ownership of a refcount on the cl_mem + * into the new Memory object. + */ + __CL_EXPLICIT_CONSTRUCTORS Memory(const cl_mem& memory) : detail::Wrapper(memory) { } + + /*! \brief Assignment operator from Memory. + * + * This calls clRetainMemObject() on the parameter and clReleaseMemObject() + * on the previous value held by this instance. + */ + Memory& operator = (const Memory& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment operator from cl_mem - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseMemObject() on the value previously held by this instance. + */ + Memory& operator = (const cl_mem& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetMemObjectInfo(). + template + cl_int getInfo(cl_mem_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetMemObjectInfo, object_, name, param), + __GET_MEM_OBJECT_INFO_ERR); + } + + //! \brief Wrapper for clGetMemObjectInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_mem_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + +#if defined(CL_VERSION_1_1) + /*! \brief Registers a callback function to be called when the memory object + * is no longer needed. + * + * Wraps clSetMemObjectDestructorCallback(). + * + * Repeated calls to this function, for a given cl_mem value, will append + * to the list of functions called (in reverse order) when memory object's + * resources are freed and the memory object is deleted. + * + * \note + * The registered callbacks are associated with the underlying cl_mem + * value - not the Memory class instance. + */ + cl_int setDestructorCallback( + void (CL_CALLBACK * pfn_notify)(cl_mem, void *), + void * user_data = NULL) + { + return detail::errHandler( + ::clSetMemObjectDestructorCallback( + object_, + pfn_notify, + user_data), + __SET_MEM_OBJECT_DESTRUCTOR_CALLBACK_ERR); + } +#endif + +}; + +// Pre-declare copy functions +class Buffer; +template< typename IteratorType > +cl_int copy( IteratorType startIterator, IteratorType endIterator, cl::Buffer &buffer ); +template< typename IteratorType > +cl_int copy( const cl::Buffer &buffer, IteratorType startIterator, IteratorType endIterator ); +template< typename IteratorType > +cl_int copy( const CommandQueue &queue, IteratorType startIterator, IteratorType endIterator, cl::Buffer &buffer ); +template< typename IteratorType > +cl_int copy( const CommandQueue &queue, const cl::Buffer &buffer, IteratorType startIterator, IteratorType endIterator ); + + +/*! \brief Class interface for Buffer Memory Objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Buffer : public Memory +{ +public: + + /*! \brief Constructs a Buffer in a specified context. + * + * Wraps clCreateBuffer(). + * + * \param host_ptr Storage to be used if the CL_MEM_USE_HOST_PTR flag was + * specified. Note alignment & exclusivity requirements. + */ + Buffer( + const Context& context, + cl_mem_flags flags, + ::size_t size, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + object_ = ::clCreateBuffer(context(), flags, size, host_ptr, &error); + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Constructs a Buffer in the default context. + * + * Wraps clCreateBuffer(). + * + * \param host_ptr Storage to be used if the CL_MEM_USE_HOST_PTR flag was + * specified. Note alignment & exclusivity requirements. + * + * \see Context::getDefault() + */ + Buffer( + cl_mem_flags flags, + ::size_t size, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + + Context context = Context::getDefault(err); + + object_ = ::clCreateBuffer(context(), flags, size, host_ptr, &error); + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! + * \brief Construct a Buffer from a host container via iterators. + * IteratorType must be random access. + * If useHostPtr is specified iterators must represent contiguous data. + */ + template< typename IteratorType > + Buffer( + IteratorType startIterator, + IteratorType endIterator, + bool readOnly, + bool useHostPtr = false, + cl_int* err = NULL) + { + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + cl_mem_flags flags = 0; + if( readOnly ) { + flags |= CL_MEM_READ_ONLY; + } + else { + flags |= CL_MEM_READ_WRITE; + } + if( useHostPtr ) { + flags |= CL_MEM_USE_HOST_PTR; + } + + ::size_t size = sizeof(DataType)*(endIterator - startIterator); + + Context context = Context::getDefault(err); + + if( useHostPtr ) { + object_ = ::clCreateBuffer(context(), flags, size, static_cast(&*startIterator), &error); + } else { + object_ = ::clCreateBuffer(context(), flags, size, 0, &error); + } + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + if( !useHostPtr ) { + error = cl::copy(startIterator, endIterator, *this); + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + } + + /*! + * \brief Construct a Buffer from a host container via iterators using a specified context. + * IteratorType must be random access. + * If useHostPtr is specified iterators must represent contiguous data. + */ + template< typename IteratorType > + Buffer(const Context &context, IteratorType startIterator, IteratorType endIterator, + bool readOnly, bool useHostPtr = false, cl_int* err = NULL); + + //! \brief Default constructor - initializes to NULL. + Buffer() : Memory() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + Buffer(const Buffer& buffer) : Memory(buffer) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS Buffer(const cl_mem& buffer) : Memory(buffer) { } + + /*! \brief Assignment from Buffer - performs shallow copy. + * + * See Memory for further details. + */ + Buffer& operator = (const Buffer& rhs) + { + if (this != &rhs) { + Memory::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Buffer& operator = (const cl_mem& rhs) + { + Memory::operator=(rhs); + return *this; + } + +#if defined(CL_VERSION_1_1) + /*! \brief Creates a new buffer object from this. + * + * Wraps clCreateSubBuffer(). + */ + Buffer createSubBuffer( + cl_mem_flags flags, + cl_buffer_create_type buffer_create_type, + const void * buffer_create_info, + cl_int * err = NULL) + { + Buffer result; + cl_int error; + result.object_ = ::clCreateSubBuffer( + object_, + flags, + buffer_create_type, + buffer_create_info, + &error); + + detail::errHandler(error, __CREATE_SUBBUFFER_ERR); + if (err != NULL) { + *err = error; + } + + return result; + } +#endif +}; + +#if defined (USE_DX_INTEROP) +/*! \brief Class interface for creating OpenCL buffers from ID3D10Buffer's. + * + * This is provided to facilitate interoperability with Direct3D. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class BufferD3D10 : public Buffer +{ +public: + typedef CL_API_ENTRY cl_mem (CL_API_CALL *PFN_clCreateFromD3D10BufferKHR)( + cl_context context, cl_mem_flags flags, ID3D10Buffer* buffer, + cl_int* errcode_ret); + + /*! \brief Constructs a BufferD3D10, in a specified context, from a + * given ID3D10Buffer. + * + * Wraps clCreateFromD3D10BufferKHR(). + */ + BufferD3D10( + const Context& context, + cl_mem_flags flags, + ID3D10Buffer* bufobj, + cl_int * err = NULL) + { + static PFN_clCreateFromD3D10BufferKHR pfn_clCreateFromD3D10BufferKHR = NULL; + +#if defined(CL_VERSION_1_2) + vector props = context.getInfo(); + cl_platform platform = -1; + for( int i = 0; i < props.size(); ++i ) { + if( props[i] == CL_CONTEXT_PLATFORM ) { + platform = props[i+1]; + } + } + __INIT_CL_EXT_FCN_PTR_PLATFORM(platform, clCreateFromD3D10BufferKHR); +#endif +#if defined(CL_VERSION_1_1) + __INIT_CL_EXT_FCN_PTR(clCreateFromD3D10BufferKHR); +#endif + + cl_int error; + object_ = pfn_clCreateFromD3D10BufferKHR( + context(), + flags, + bufobj, + &error); + + detail::errHandler(error, __CREATE_GL_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + BufferD3D10() : Buffer() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + BufferD3D10(const BufferD3D10& buffer) : Buffer(buffer) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS BufferD3D10(const cl_mem& buffer) : Buffer(buffer) { } + + /*! \brief Assignment from BufferD3D10 - performs shallow copy. + * + * See Memory for further details. + */ + BufferD3D10& operator = (const BufferD3D10& rhs) + { + if (this != &rhs) { + Buffer::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + BufferD3D10& operator = (const cl_mem& rhs) + { + Buffer::operator=(rhs); + return *this; + } +}; +#endif + +/*! \brief Class interface for GL Buffer Memory Objects. + * + * This is provided to facilitate interoperability with OpenGL. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class BufferGL : public Buffer +{ +public: + /*! \brief Constructs a BufferGL in a specified context, from a given + * GL buffer. + * + * Wraps clCreateFromGLBuffer(). + */ + BufferGL( + const Context& context, + cl_mem_flags flags, + GLuint bufobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLBuffer( + context(), + flags, + bufobj, + &error); + + detail::errHandler(error, __CREATE_GL_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + BufferGL() : Buffer() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + BufferGL(const BufferGL& buffer) : Buffer(buffer) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS BufferGL(const cl_mem& buffer) : Buffer(buffer) { } + + /*! \brief Assignment from BufferGL - performs shallow copy. + * + * See Memory for further details. + */ + BufferGL& operator = (const BufferGL& rhs) + { + if (this != &rhs) { + Buffer::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + BufferGL& operator = (const cl_mem& rhs) + { + Buffer::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetGLObjectInfo(). + cl_int getObjectInfo( + cl_gl_object_type *type, + GLuint * gl_object_name) + { + return detail::errHandler( + ::clGetGLObjectInfo(object_,type,gl_object_name), + __GET_GL_OBJECT_INFO_ERR); + } +}; + +/*! \brief Class interface for GL Render Buffer Memory Objects. + * + * This is provided to facilitate interoperability with OpenGL. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class BufferRenderGL : public Buffer +{ +public: + /*! \brief Constructs a BufferRenderGL in a specified context, from a given + * GL Renderbuffer. + * + * Wraps clCreateFromGLRenderbuffer(). + */ + BufferRenderGL( + const Context& context, + cl_mem_flags flags, + GLuint bufobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLRenderbuffer( + context(), + flags, + bufobj, + &error); + + detail::errHandler(error, __CREATE_GL_RENDER_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + BufferRenderGL() : Buffer() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + BufferRenderGL(const BufferGL& buffer) : Buffer(buffer) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS BufferRenderGL(const cl_mem& buffer) : Buffer(buffer) { } + + /*! \brief Assignment from BufferGL - performs shallow copy. + * + * See Memory for further details. + */ + BufferRenderGL& operator = (const BufferRenderGL& rhs) + { + if (this != &rhs) { + Buffer::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + BufferRenderGL& operator = (const cl_mem& rhs) + { + Buffer::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetGLObjectInfo(). + cl_int getObjectInfo( + cl_gl_object_type *type, + GLuint * gl_object_name) + { + return detail::errHandler( + ::clGetGLObjectInfo(object_,type,gl_object_name), + __GET_GL_OBJECT_INFO_ERR); + } +}; + +/*! \brief C++ base class for Image Memory objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image : public Memory +{ +protected: + //! \brief Default constructor - initializes to NULL. + Image() : Memory() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + Image(const Image& image) : Memory(image) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS Image(const cl_mem& image) : Memory(image) { } + + /*! \brief Assignment from Image - performs shallow copy. + * + * See Memory for further details. + */ + Image& operator = (const Image& rhs) + { + if (this != &rhs) { + Memory::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image& operator = (const cl_mem& rhs) + { + Memory::operator=(rhs); + return *this; + } + +public: + //! \brief Wrapper for clGetImageInfo(). + template + cl_int getImageInfo(cl_image_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetImageInfo, object_, name, param), + __GET_IMAGE_INFO_ERR); + } + + //! \brief Wrapper for clGetImageInfo() that returns by value. + template typename + detail::param_traits::param_type + getImageInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_image_info, name>::param_type param; + cl_int result = getImageInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } +}; + +#if defined(CL_VERSION_1_2) +/*! \brief Class interface for 1D Image Memory objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image1D : public Image +{ +public: + /*! \brief Constructs a 1D Image in a specified context. + * + * Wraps clCreateImage(). + */ + Image1D( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + ::size_t width, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE1D, + width, + 0, 0, 0, 0, 0, 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + Image1D() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + Image1D(const Image1D& image1D) : Image(image1D) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS Image1D(const cl_mem& image1D) : Image(image1D) { } + + /*! \brief Assignment from Image1D - performs shallow copy. + * + * See Memory for further details. + */ + Image1D& operator = (const Image1D& rhs) + { + if (this != &rhs) { + Image::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image1D& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } +}; + +/*! \class Image1DBuffer + * \brief Image interface for 1D buffer images. + */ +class Image1DBuffer : public Image +{ +public: + Image1DBuffer( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + ::size_t width, + const Buffer &buffer, + cl_int* err = NULL) + { + cl_int error; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE1D_BUFFER, + width, + 0, 0, 0, 0, 0, 0, 0, + buffer() + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + NULL, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } + + Image1DBuffer() { } + + Image1DBuffer(const Image1DBuffer& image1D) : Image(image1D) { } + + __CL_EXPLICIT_CONSTRUCTORS Image1DBuffer(const cl_mem& image1D) : Image(image1D) { } + + Image1DBuffer& operator = (const Image1DBuffer& rhs) + { + if (this != &rhs) { + Image::operator=(rhs); + } + return *this; + } + + Image1DBuffer& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } +}; + +/*! \class Image1DArray + * \brief Image interface for arrays of 1D images. + */ +class Image1DArray : public Image +{ +public: + Image1DArray( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + ::size_t arraySize, + ::size_t width, + ::size_t rowPitch, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE1D_ARRAY, + width, + 0, 0, // height, depth (unused) + arraySize, + rowPitch, + 0, 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } + + Image1DArray() { } + + Image1DArray(const Image1DArray& imageArray) : Image(imageArray) { } + + __CL_EXPLICIT_CONSTRUCTORS Image1DArray(const cl_mem& imageArray) : Image(imageArray) { } + + Image1DArray& operator = (const Image1DArray& rhs) + { + if (this != &rhs) { + Image::operator=(rhs); + } + return *this; + } + + Image1DArray& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } +}; +#endif // #if defined(CL_VERSION_1_2) + + +/*! \brief Class interface for 2D Image Memory objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image2D : public Image +{ +public: + /*! \brief Constructs a 1D Image in a specified context. + * + * Wraps clCreateImage(). + */ + Image2D( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + ::size_t width, + ::size_t height, + ::size_t row_pitch = 0, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + bool useCreateImage; + +#if defined(CL_VERSION_1_2) && defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useCreateImage = (version >= 0x10002); // OpenCL 1.2 or above + } +#elif defined(CL_VERSION_1_2) + useCreateImage = true; +#else + useCreateImage = false; +#endif + +#if defined(CL_VERSION_1_2) + if (useCreateImage) + { + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE2D, + width, + height, + 0, 0, // depth, array size (unused) + row_pitch, + 0, 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // #if defined(CL_VERSION_1_2) +#if !defined(CL_VERSION_1_2) || defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + if (!useCreateImage) + { + object_ = ::clCreateImage2D( + context(), flags,&format, width, height, row_pitch, host_ptr, &error); + + detail::errHandler(error, __CREATE_IMAGE2D_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // #if !defined(CL_VERSION_1_2) || defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + } + + //! \brief Default constructor - initializes to NULL. + Image2D() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + Image2D(const Image2D& image2D) : Image(image2D) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS Image2D(const cl_mem& image2D) : Image(image2D) { } + + /*! \brief Assignment from Image2D - performs shallow copy. + * + * See Memory for further details. + */ + Image2D& operator = (const Image2D& rhs) + { + if (this != &rhs) { + Image::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image2D& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } +}; + + +#if !defined(CL_VERSION_1_2) +/*! \brief Class interface for GL 2D Image Memory objects. + * + * This is provided to facilitate interoperability with OpenGL. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + * \note Deprecated for OpenCL 1.2. Please use ImageGL instead. + */ +class CL_EXT_PREFIX__VERSION_1_1_DEPRECATED Image2DGL CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED : public Image2D +{ +public: + /*! \brief Constructs an Image2DGL in a specified context, from a given + * GL Texture. + * + * Wraps clCreateFromGLTexture2D(). + */ + Image2DGL( + const Context& context, + cl_mem_flags flags, + GLenum target, + GLint miplevel, + GLuint texobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLTexture2D( + context(), + flags, + target, + miplevel, + texobj, + &error); + + detail::errHandler(error, __CREATE_GL_TEXTURE_2D_ERR); + if (err != NULL) { + *err = error; + } + + } + + //! \brief Default constructor - initializes to NULL. + Image2DGL() : Image2D() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + Image2DGL(const Image2DGL& image) : Image2D(image) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS Image2DGL(const cl_mem& image) : Image2D(image) { } + + /*! \brief Assignment from Image2DGL - performs shallow copy. + * + * See Memory for further details. + */ + Image2DGL& operator = (const Image2DGL& rhs) + { + if (this != &rhs) { + Image2D::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image2DGL& operator = (const cl_mem& rhs) + { + Image2D::operator=(rhs); + return *this; + } +}; +#endif // #if !defined(CL_VERSION_1_2) + +#if defined(CL_VERSION_1_2) +/*! \class Image2DArray + * \brief Image interface for arrays of 2D images. + */ +class Image2DArray : public Image +{ +public: + Image2DArray( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + ::size_t arraySize, + ::size_t width, + ::size_t height, + ::size_t rowPitch, + ::size_t slicePitch, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE2D_ARRAY, + width, + height, + 0, // depth (unused) + arraySize, + rowPitch, + slicePitch, + 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } + + Image2DArray() { } + + Image2DArray(const Image2DArray& imageArray) : Image(imageArray) { } + + __CL_EXPLICIT_CONSTRUCTORS Image2DArray(const cl_mem& imageArray) : Image(imageArray) { } + + Image2DArray& operator = (const Image2DArray& rhs) + { + if (this != &rhs) { + Image::operator=(rhs); + } + return *this; + } + + Image2DArray& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } +}; +#endif // #if defined(CL_VERSION_1_2) + +/*! \brief Class interface for 3D Image Memory objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image3D : public Image +{ +public: + /*! \brief Constructs a 3D Image in a specified context. + * + * Wraps clCreateImage(). + */ + Image3D( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + ::size_t width, + ::size_t height, + ::size_t depth, + ::size_t row_pitch = 0, + ::size_t slice_pitch = 0, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + bool useCreateImage; + +#if defined(CL_VERSION_1_2) && defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useCreateImage = (version >= 0x10002); // OpenCL 1.2 or above + } +#elif defined(CL_VERSION_1_2) + useCreateImage = true; +#else + useCreateImage = false; +#endif + +#if defined(CL_VERSION_1_2) + if (useCreateImage) + { + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE3D, + width, + height, + depth, + 0, // array size (unused) + row_pitch, + slice_pitch, + 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // #if defined(CL_VERSION_1_2) +#if !defined(CL_VERSION_1_2) || defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + if (!useCreateImage) + { + object_ = ::clCreateImage3D( + context(), flags, &format, width, height, depth, row_pitch, + slice_pitch, host_ptr, &error); + + detail::errHandler(error, __CREATE_IMAGE3D_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // #if !defined(CL_VERSION_1_2) || defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + } + + //! \brief Default constructor - initializes to NULL. + Image3D() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + Image3D(const Image3D& image3D) : Image(image3D) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS Image3D(const cl_mem& image3D) : Image(image3D) { } + + /*! \brief Assignment from Image3D - performs shallow copy. + * + * See Memory for further details. + */ + Image3D& operator = (const Image3D& rhs) + { + if (this != &rhs) { + Image::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image3D& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } +}; + +#if !defined(CL_VERSION_1_2) +/*! \brief Class interface for GL 3D Image Memory objects. + * + * This is provided to facilitate interoperability with OpenGL. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image3DGL : public Image3D +{ +public: + /*! \brief Constructs an Image3DGL in a specified context, from a given + * GL Texture. + * + * Wraps clCreateFromGLTexture3D(). + */ + Image3DGL( + const Context& context, + cl_mem_flags flags, + GLenum target, + GLint miplevel, + GLuint texobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLTexture3D( + context(), + flags, + target, + miplevel, + texobj, + &error); + + detail::errHandler(error, __CREATE_GL_TEXTURE_3D_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + Image3DGL() : Image3D() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * See Memory for further details. + */ + Image3DGL(const Image3DGL& image) : Image3D(image) { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * See Memory for further details. + */ + __CL_EXPLICIT_CONSTRUCTORS Image3DGL(const cl_mem& image) : Image3D(image) { } + + /*! \brief Assignment from Image3DGL - performs shallow copy. + * + * See Memory for further details. + */ + Image3DGL& operator = (const Image3DGL& rhs) + { + if (this != &rhs) { + Image3D::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image3DGL& operator = (const cl_mem& rhs) + { + Image3D::operator=(rhs); + return *this; + } +}; +#endif // #if !defined(CL_VERSION_1_2) + +#if defined(CL_VERSION_1_2) +/*! \class ImageGL + * \brief general image interface for GL interop. + * We abstract the 2D and 3D GL images into a single instance here + * that wraps all GL sourced images on the grounds that setup information + * was performed by OpenCL anyway. + */ +class ImageGL : public Image +{ +public: + ImageGL( + const Context& context, + cl_mem_flags flags, + GLenum target, + GLint miplevel, + GLuint texobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLTexture( + context(), + flags, + target, + miplevel, + texobj, + &error); + + detail::errHandler(error, __CREATE_GL_TEXTURE_ERR); + if (err != NULL) { + *err = error; + } + } + + ImageGL() : Image() { } + + ImageGL(const ImageGL& image) : Image(image) { } + + __CL_EXPLICIT_CONSTRUCTORS ImageGL(const cl_mem& image) : Image(image) { } + + ImageGL& operator = (const ImageGL& rhs) + { + if (this != &rhs) { + Image::operator=(rhs); + } + return *this; + } + + ImageGL& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } +}; +#endif // #if defined(CL_VERSION_1_2) + +/*! \brief Class interface for cl_sampler. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_sampler as the original. For details, see + * clRetainSampler() and clReleaseSampler(). + * + * \see cl_sampler + */ +class Sampler : public detail::Wrapper +{ +public: + /*! \brief Destructor. + * + * This calls clReleaseSampler() on the value held by this instance. + */ + ~Sampler() { } + + //! \brief Default constructor - initializes to NULL. + Sampler() { } + + /*! \brief Constructs a Sampler in a specified context. + * + * Wraps clCreateSampler(). + */ + Sampler( + const Context& context, + cl_bool normalized_coords, + cl_addressing_mode addressing_mode, + cl_filter_mode filter_mode, + cl_int* err = NULL) + { + cl_int error; + object_ = ::clCreateSampler( + context(), + normalized_coords, + addressing_mode, + filter_mode, + &error); + + detail::errHandler(error, __CREATE_SAMPLER_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Copy constructor - performs shallow copy. + * + * This calls clRetainSampler() on the parameter's cl_sampler. + */ + Sampler(const Sampler& sampler) : detail::Wrapper(sampler) { } + + /*! \brief Constructor from cl_sampler - takes ownership. + * + * This effectively transfers ownership of a refcount on the cl_sampler + * into the new Sampler object. + */ + Sampler(const cl_sampler& sampler) : detail::Wrapper(sampler) { } + + /*! \brief Assignment operator from Sampler. + * + * This calls clRetainSampler() on the parameter and clReleaseSampler() + * on the previous value held by this instance. + */ + Sampler& operator = (const Sampler& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment operator from cl_sampler - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseSampler() on the value previously held by this instance. + */ + Sampler& operator = (const cl_sampler& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetSamplerInfo(). + template + cl_int getInfo(cl_sampler_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetSamplerInfo, object_, name, param), + __GET_SAMPLER_INFO_ERR); + } + + //! \brief Wrapper for clGetSamplerInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_sampler_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } +}; + +class Program; +class CommandQueue; +class Kernel; + +//! \brief Class interface for specifying NDRange values. +class NDRange +{ +private: + size_t<3> sizes_; + cl_uint dimensions_; + +public: + //! \brief Default constructor - resulting range has zero dimensions. + NDRange() + : dimensions_(0) + { } + + //! \brief Constructs one-dimensional range. + NDRange(::size_t size0) + : dimensions_(1) + { + sizes_[0] = size0; + } + + //! \brief Constructs two-dimensional range. + NDRange(::size_t size0, ::size_t size1) + : dimensions_(2) + { + sizes_[0] = size0; + sizes_[1] = size1; + } + + //! \brief Constructs three-dimensional range. + NDRange(::size_t size0, ::size_t size1, ::size_t size2) + : dimensions_(3) + { + sizes_[0] = size0; + sizes_[1] = size1; + sizes_[2] = size2; + } + + /*! \brief Conversion operator to const ::size_t *. + * + * \returns a pointer to the size of the first dimension. + */ + operator const ::size_t*() const { + return (const ::size_t*) sizes_; + } + + //! \brief Queries the number of dimensions in the range. + ::size_t dimensions() const { return dimensions_; } +}; + +//! \brief A zero-dimensional range. +static const NDRange NullRange; + +//! \brief Local address wrapper for use with Kernel::setArg +struct LocalSpaceArg +{ + ::size_t size_; +}; + +namespace detail { + +template +struct KernelArgumentHandler +{ + static ::size_t size(const T&) { return sizeof(T); } + static T* ptr(T& value) { return &value; } +}; + +template <> +struct KernelArgumentHandler +{ + static ::size_t size(const LocalSpaceArg& value) { return value.size_; } + static void* ptr(LocalSpaceArg&) { return NULL; } +}; + +} +//! \endcond + +/*! __local + * \brief Helper function for generating LocalSpaceArg objects. + * Deprecated. Replaced with Local. + */ +inline CL_EXT_PREFIX__VERSION_1_1_DEPRECATED LocalSpaceArg +__local(::size_t size) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; +inline LocalSpaceArg +__local(::size_t size) +{ + LocalSpaceArg ret = { size }; + return ret; +} + +/*! Local + * \brief Helper function for generating LocalSpaceArg objects. + */ +inline LocalSpaceArg +Local(::size_t size) +{ + LocalSpaceArg ret = { size }; + return ret; +} + +//class KernelFunctor; + +/*! \brief Class interface for cl_kernel. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_kernel as the original. For details, see + * clRetainKernel() and clReleaseKernel(). + * + * \see cl_kernel + */ +class Kernel : public detail::Wrapper +{ +public: + inline Kernel(const Program& program, const char* name, cl_int* err = NULL); + + /*! \brief Destructor. + * + * This calls clReleaseKernel() on the value held by this instance. + */ + ~Kernel() { } + + //! \brief Default constructor - initializes to NULL. + Kernel() { } + + /*! \brief Copy constructor - performs shallow copy. + * + * This calls clRetainKernel() on the parameter's cl_kernel. + */ + Kernel(const Kernel& kernel) : detail::Wrapper(kernel) { } + + /*! \brief Constructor from cl_kernel - takes ownership. + * + * This effectively transfers ownership of a refcount on the cl_kernel + * into the new Kernel object. + */ + __CL_EXPLICIT_CONSTRUCTORS Kernel(const cl_kernel& kernel) : detail::Wrapper(kernel) { } + + /*! \brief Assignment operator from Kernel. + * + * This calls clRetainKernel() on the parameter and clReleaseKernel() + * on the previous value held by this instance. + */ + Kernel& operator = (const Kernel& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + /*! \brief Assignment operator from cl_kernel - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseKernel() on the value previously held by this instance. + */ + Kernel& operator = (const cl_kernel& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + template + cl_int getInfo(cl_kernel_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetKernelInfo, object_, name, param), + __GET_KERNEL_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_kernel_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + +#if defined(CL_VERSION_1_2) + template + cl_int getArgInfo(cl_uint argIndex, cl_kernel_arg_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetKernelArgInfo, object_, argIndex, name, param), + __GET_KERNEL_ARG_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getArgInfo(cl_uint argIndex, cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_kernel_arg_info, name>::param_type param; + cl_int result = getArgInfo(argIndex, name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } +#endif // #if defined(CL_VERSION_1_2) + + template + cl_int getWorkGroupInfo( + const Device& device, cl_kernel_work_group_info name, T* param) const + { + return detail::errHandler( + detail::getInfo( + &::clGetKernelWorkGroupInfo, object_, device(), name, param), + __GET_KERNEL_WORK_GROUP_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getWorkGroupInfo(const Device& device, cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_kernel_work_group_info, name>::param_type param; + cl_int result = getWorkGroupInfo(device, name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + template + cl_int setArg(cl_uint index, T value) + { + return detail::errHandler( + ::clSetKernelArg( + object_, + index, + detail::KernelArgumentHandler::size(value), + detail::KernelArgumentHandler::ptr(value)), + __SET_KERNEL_ARGS_ERR); + } + + cl_int setArg(cl_uint index, ::size_t size, void* argPtr) + { + return detail::errHandler( + ::clSetKernelArg(object_, index, size, argPtr), + __SET_KERNEL_ARGS_ERR); + } +}; + +/*! \class Program + * \brief Program interface that implements cl_program. + */ +class Program : public detail::Wrapper +{ +public: + typedef VECTOR_CLASS > Binaries; + typedef VECTOR_CLASS > Sources; + + Program( + const STRING_CLASS& source, + bool build = false, + cl_int* err = NULL) + { + cl_int error; + + const char * strings = source.c_str(); + const ::size_t length = source.size(); + + Context context = Context::getDefault(err); + + object_ = ::clCreateProgramWithSource( + context(), (cl_uint)1, &strings, &length, &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_SOURCE_ERR); + + if (error == CL_SUCCESS && build) { + + error = ::clBuildProgram( + object_, + 0, + NULL, + "", + NULL, + NULL); + + detail::errHandler(error, __BUILD_PROGRAM_ERR); + } + + if (err != NULL) { + *err = error; + } + } + + Program( + const Context& context, + const STRING_CLASS& source, + bool build = false, + cl_int* err = NULL) + { + cl_int error; + + const char * strings = source.c_str(); + const ::size_t length = source.size(); + + object_ = ::clCreateProgramWithSource( + context(), (cl_uint)1, &strings, &length, &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_SOURCE_ERR); + + if (error == CL_SUCCESS && build) { + + error = ::clBuildProgram( + object_, + 0, + NULL, + "", + NULL, + NULL); + + detail::errHandler(error, __BUILD_PROGRAM_ERR); + } + + if (err != NULL) { + *err = error; + } + } + + Program( + const Context& context, + const Sources& sources, + cl_int* err = NULL) + { + cl_int error; + + const ::size_t n = (::size_t)sources.size(); + ::size_t* lengths = (::size_t*) alloca(n * sizeof(::size_t)); + const char** strings = (const char**) alloca(n * sizeof(const char*)); + + for (::size_t i = 0; i < n; ++i) { + strings[i] = sources[(int)i].first; + lengths[i] = sources[(int)i].second; + } + + object_ = ::clCreateProgramWithSource( + context(), (cl_uint)n, strings, lengths, &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_SOURCE_ERR); + if (err != NULL) { + *err = error; + } + } + + /** + * Construct a program object from a list of devices and a per-device list of binaries. + * \param context A valid OpenCL context in which to construct the program. + * \param devices A vector of OpenCL device objects for which the program will be created. + * \param binaries A vector of pairs of a pointer to a binary object and its length. + * \param binaryStatus An optional vector that on completion will be resized to + * match the size of binaries and filled with values to specify if each binary + * was successfully loaded. + * Set to CL_SUCCESS if the binary was successfully loaded. + * Set to CL_INVALID_VALUE if the length is 0 or the binary pointer is NULL. + * Set to CL_INVALID_BINARY if the binary provided is not valid for the matching device. + * \param err if non-NULL will be set to CL_SUCCESS on successful operation or one of the following errors: + * CL_INVALID_CONTEXT if context is not a valid context. + * CL_INVALID_VALUE if the length of devices is zero; or if the length of binaries does not match the length of devices; + * or if any entry in binaries is NULL or has length 0. + * CL_INVALID_DEVICE if OpenCL devices listed in devices are not in the list of devices associated with context. + * CL_INVALID_BINARY if an invalid program binary was encountered for any device. binaryStatus will return specific status for each device. + * CL_OUT_OF_HOST_MEMORY if there is a failure to allocate resources required by the OpenCL implementation on the host. + */ + Program( + const Context& context, + const VECTOR_CLASS& devices, + const Binaries& binaries, + VECTOR_CLASS* binaryStatus = NULL, + cl_int* err = NULL) + { + cl_int error; + + const ::size_t numDevices = devices.size(); + + // Catch size mismatch early and return + if(binaries.size() != numDevices) { + error = CL_INVALID_VALUE; + detail::errHandler(error, __CREATE_PROGRAM_WITH_BINARY_ERR); + if (err != NULL) { + *err = error; + } + return; + } + + ::size_t* lengths = (::size_t*) alloca(numDevices * sizeof(::size_t)); + const unsigned char** images = (const unsigned char**) alloca(numDevices * sizeof(const unsigned char**)); + + for (::size_t i = 0; i < numDevices; ++i) { + images[i] = (const unsigned char*)binaries[i].first; + lengths[i] = binaries[(int)i].second; + } + + cl_device_id* deviceIDs = (cl_device_id*) alloca(numDevices * sizeof(cl_device_id)); + for( ::size_t deviceIndex = 0; deviceIndex < numDevices; ++deviceIndex ) { + deviceIDs[deviceIndex] = (devices[deviceIndex])(); + } + + if(binaryStatus) { + binaryStatus->resize(numDevices); + } + + object_ = ::clCreateProgramWithBinary( + context(), (cl_uint) devices.size(), + deviceIDs, + lengths, images, binaryStatus != NULL + ? &binaryStatus->front() + : NULL, &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_BINARY_ERR); + if (err != NULL) { + *err = error; + } + } + + +#if defined(CL_VERSION_1_2) + /** + * Create program using builtin kernels. + * \param kernelNames Semi-colon separated list of builtin kernel names + */ + Program( + const Context& context, + const VECTOR_CLASS& devices, + const STRING_CLASS& kernelNames, + cl_int* err = NULL) + { + cl_int error; + + + ::size_t numDevices = devices.size(); + cl_device_id* deviceIDs = (cl_device_id*) alloca(numDevices * sizeof(cl_device_id)); + for( ::size_t deviceIndex = 0; deviceIndex < numDevices; ++deviceIndex ) { + deviceIDs[deviceIndex] = (devices[deviceIndex])(); + } + + object_ = ::clCreateProgramWithBuiltInKernels( + context(), + (cl_uint) devices.size(), + deviceIDs, + kernelNames.c_str(), + &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_BUILT_IN_KERNELS_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // #if defined(CL_VERSION_1_2) + + Program() { } + + Program(const Program& program) : detail::Wrapper(program) { } + + __CL_EXPLICIT_CONSTRUCTORS Program(const cl_program& program) : detail::Wrapper(program) { } + + Program& operator = (const Program& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + Program& operator = (const cl_program& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + cl_int build( + const VECTOR_CLASS& devices, + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL) const + { + ::size_t numDevices = devices.size(); + cl_device_id* deviceIDs = (cl_device_id*) alloca(numDevices * sizeof(cl_device_id)); + for( ::size_t deviceIndex = 0; deviceIndex < numDevices; ++deviceIndex ) { + deviceIDs[deviceIndex] = (devices[deviceIndex])(); + } + + return detail::errHandler( + ::clBuildProgram( + object_, + (cl_uint) + devices.size(), + deviceIDs, + options, + notifyFptr, + data), + __BUILD_PROGRAM_ERR); + } + + cl_int build( + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL) const + { + return detail::errHandler( + ::clBuildProgram( + object_, + 0, + NULL, + options, + notifyFptr, + data), + __BUILD_PROGRAM_ERR); + } + +#if defined(CL_VERSION_1_2) + cl_int compile( + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL) const + { + return detail::errHandler( + ::clCompileProgram( + object_, + 0, + NULL, + options, + 0, + NULL, + NULL, + notifyFptr, + data), + __COMPILE_PROGRAM_ERR); + } +#endif + + template + cl_int getInfo(cl_program_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetProgramInfo, object_, name, param), + __GET_PROGRAM_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_program_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + template + cl_int getBuildInfo( + const Device& device, cl_program_build_info name, T* param) const + { + return detail::errHandler( + detail::getInfo( + &::clGetProgramBuildInfo, object_, device(), name, param), + __GET_PROGRAM_BUILD_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getBuildInfo(const Device& device, cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_program_build_info, name>::param_type param; + cl_int result = getBuildInfo(device, name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + cl_int createKernels(VECTOR_CLASS* kernels) + { + cl_uint numKernels; + cl_int err = ::clCreateKernelsInProgram(object_, 0, NULL, &numKernels); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_KERNELS_IN_PROGRAM_ERR); + } + + Kernel* value = (Kernel*) alloca(numKernels * sizeof(Kernel)); + err = ::clCreateKernelsInProgram( + object_, numKernels, (cl_kernel*) value, NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_KERNELS_IN_PROGRAM_ERR); + } + + kernels->assign(&value[0], &value[numKernels]); + return CL_SUCCESS; + } +}; + +#if defined(CL_VERSION_1_2) +inline Program linkProgram( + Program input1, + Program input2, + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL, + cl_int* err = NULL) +{ + cl_int err_local = CL_SUCCESS; + + cl_program programs[2] = { input1(), input2() }; + + Context ctx = input1.getInfo(); + + cl_program prog = ::clLinkProgram( + ctx(), + 0, + NULL, + options, + 2, + programs, + notifyFptr, + data, + &err_local); + + detail::errHandler(err_local,__COMPILE_PROGRAM_ERR); + if (err != NULL) { + *err = err_local; + } + + return Program(prog); +} + +inline Program linkProgram( + VECTOR_CLASS inputPrograms, + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL, + cl_int* err = NULL) +{ + cl_int err_local = CL_SUCCESS; + + cl_program * programs = (cl_program*) alloca(inputPrograms.size() * sizeof(cl_program)); + + if (programs != NULL) { + for (unsigned int i = 0; i < inputPrograms.size(); i++) { + programs[i] = inputPrograms[i](); + } + } + + cl_program prog = ::clLinkProgram( + Context::getDefault()(), + 0, + NULL, + options, + (cl_uint)inputPrograms.size(), + programs, + notifyFptr, + data, + &err_local); + + detail::errHandler(err_local,__COMPILE_PROGRAM_ERR); + if (err != NULL) { + *err = err_local; + } + + return Program(prog); +} +#endif + +template<> +inline VECTOR_CLASS cl::Program::getInfo(cl_int* err) const +{ + VECTOR_CLASS< ::size_t> sizes = getInfo(); + VECTOR_CLASS binaries; + for (VECTOR_CLASS< ::size_t>::iterator s = sizes.begin(); s != sizes.end(); ++s) + { + char *ptr = NULL; + if (*s != 0) + ptr = new char[*s]; + binaries.push_back(ptr); + } + + cl_int result = getInfo(CL_PROGRAM_BINARIES, &binaries); + if (err != NULL) { + *err = result; + } + return binaries; +} + +inline Kernel::Kernel(const Program& program, const char* name, cl_int* err) +{ + cl_int error; + + object_ = ::clCreateKernel(program(), name, &error); + detail::errHandler(error, __CREATE_KERNEL_ERR); + + if (err != NULL) { + *err = error; + } + +} + +/*! \class CommandQueue + * \brief CommandQueue interface for cl_command_queue. + */ +class CommandQueue : public detail::Wrapper +{ +private: + static volatile int default_initialized_; + static CommandQueue default_; + static volatile cl_int default_error_; +public: + CommandQueue( + cl_command_queue_properties properties, + cl_int* err = NULL) + { + cl_int error; + + Context context = Context::getDefault(&error); + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + + if (error != CL_SUCCESS) { + if (err != NULL) { + *err = error; + } + } + else { + Device device = context.getInfo()[0]; + + object_ = ::clCreateCommandQueue( + context(), device(), properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } + } + /*! + * \brief Constructs a CommandQueue for an implementation defined device in the given context + */ + explicit CommandQueue( + const Context& context, + cl_command_queue_properties properties = 0, + cl_int* err = NULL) + { + cl_int error; + VECTOR_CLASS devices; + error = context.getInfo(CL_CONTEXT_DEVICES, &devices); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + + if (error != CL_SUCCESS) + { + if (err != NULL) { + *err = error; + } + return; + } + + object_ = ::clCreateCommandQueue(context(), devices[0](), properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + + if (err != NULL) { + *err = error; + } + + } + + CommandQueue( + const Context& context, + const Device& device, + cl_command_queue_properties properties = 0, + cl_int* err = NULL) + { + cl_int error; + object_ = ::clCreateCommandQueue( + context(), device(), properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } + + static CommandQueue getDefault(cl_int * err = NULL) + { + int state = detail::compare_exchange( + &default_initialized_, + __DEFAULT_BEING_INITIALIZED, __DEFAULT_NOT_INITIALIZED); + + if (state & __DEFAULT_INITIALIZED) { + if (err != NULL) { + *err = default_error_; + } + return default_; + } + + if (state & __DEFAULT_BEING_INITIALIZED) { + // Assume writes will propagate eventually... + while(default_initialized_ != __DEFAULT_INITIALIZED) { + detail::fence(); + } + + if (err != NULL) { + *err = default_error_; + } + return default_; + } + + cl_int error; + + Context context = Context::getDefault(&error); + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + + if (error != CL_SUCCESS) { + if (err != NULL) { + *err = error; + } + } + else { + Device device = context.getInfo()[0]; + + default_ = CommandQueue(context, device, 0, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } + + detail::fence(); + + default_error_ = error; + // Assume writes will propagate eventually... + default_initialized_ = __DEFAULT_INITIALIZED; + + detail::fence(); + + if (err != NULL) { + *err = default_error_; + } + return default_; + + } + + CommandQueue() { } + + CommandQueue(const CommandQueue& commandQueue) : detail::Wrapper(commandQueue) { } + + CommandQueue(const cl_command_queue& commandQueue) : detail::Wrapper(commandQueue) { } + + CommandQueue& operator = (const CommandQueue& rhs) + { + if (this != &rhs) { + detail::Wrapper::operator=(rhs); + } + return *this; + } + + CommandQueue& operator = (const cl_command_queue& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + template + cl_int getInfo(cl_command_queue_info name, T* param) const + { + return detail::errHandler( + detail::getInfo( + &::clGetCommandQueueInfo, object_, name, param), + __GET_COMMAND_QUEUE_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_command_queue_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + cl_int enqueueReadBuffer( + const Buffer& buffer, + cl_bool blocking, + ::size_t offset, + ::size_t size, + void* ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueReadBuffer( + object_, buffer(), blocking, offset, size, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_READ_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueWriteBuffer( + const Buffer& buffer, + cl_bool blocking, + ::size_t offset, + ::size_t size, + const void* ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueWriteBuffer( + object_, buffer(), blocking, offset, size, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_WRITE_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueCopyBuffer( + const Buffer& src, + const Buffer& dst, + ::size_t src_offset, + ::size_t dst_offset, + ::size_t size, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyBuffer( + object_, src(), dst(), src_offset, dst_offset, size, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_COPY_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueReadBufferRect( + const Buffer& buffer, + cl_bool blocking, + const size_t<3>& buffer_offset, + const size_t<3>& host_offset, + const size_t<3>& region, + ::size_t buffer_row_pitch, + ::size_t buffer_slice_pitch, + ::size_t host_row_pitch, + ::size_t host_slice_pitch, + void *ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueReadBufferRect( + object_, + buffer(), + blocking, + (const ::size_t *)buffer_offset, + (const ::size_t *)host_offset, + (const ::size_t *)region, + buffer_row_pitch, + buffer_slice_pitch, + host_row_pitch, + host_slice_pitch, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_READ_BUFFER_RECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueWriteBufferRect( + const Buffer& buffer, + cl_bool blocking, + const size_t<3>& buffer_offset, + const size_t<3>& host_offset, + const size_t<3>& region, + ::size_t buffer_row_pitch, + ::size_t buffer_slice_pitch, + ::size_t host_row_pitch, + ::size_t host_slice_pitch, + void *ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueWriteBufferRect( + object_, + buffer(), + blocking, + (const ::size_t *)buffer_offset, + (const ::size_t *)host_offset, + (const ::size_t *)region, + buffer_row_pitch, + buffer_slice_pitch, + host_row_pitch, + host_slice_pitch, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_WRITE_BUFFER_RECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueCopyBufferRect( + const Buffer& src, + const Buffer& dst, + const size_t<3>& src_origin, + const size_t<3>& dst_origin, + const size_t<3>& region, + ::size_t src_row_pitch, + ::size_t src_slice_pitch, + ::size_t dst_row_pitch, + ::size_t dst_slice_pitch, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyBufferRect( + object_, + src(), + dst(), + (const ::size_t *)src_origin, + (const ::size_t *)dst_origin, + (const ::size_t *)region, + src_row_pitch, + src_slice_pitch, + dst_row_pitch, + dst_slice_pitch, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_COPY_BUFFER_RECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +#if defined(CL_VERSION_1_2) + /** + * Enqueue a command to fill a buffer object with a pattern + * of a given size. The pattern is specified a as vector. + * \tparam PatternType The datatype of the pattern field. + * The pattern type must be an accepted OpenCL data type. + */ + template + cl_int enqueueFillBuffer( + const Buffer& buffer, + PatternType pattern, + ::size_t offset, + ::size_t size, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueFillBuffer( + object_, + buffer(), + static_cast(&pattern), + sizeof(PatternType), + offset, + size, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_FILL_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // #if defined(CL_VERSION_1_2) + + cl_int enqueueReadImage( + const Image& image, + cl_bool blocking, + const size_t<3>& origin, + const size_t<3>& region, + ::size_t row_pitch, + ::size_t slice_pitch, + void* ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueReadImage( + object_, image(), blocking, (const ::size_t *) origin, + (const ::size_t *) region, row_pitch, slice_pitch, ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_READ_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueWriteImage( + const Image& image, + cl_bool blocking, + const size_t<3>& origin, + const size_t<3>& region, + ::size_t row_pitch, + ::size_t slice_pitch, + void* ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueWriteImage( + object_, image(), blocking, (const ::size_t *) origin, + (const ::size_t *) region, row_pitch, slice_pitch, ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_WRITE_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueCopyImage( + const Image& src, + const Image& dst, + const size_t<3>& src_origin, + const size_t<3>& dst_origin, + const size_t<3>& region, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyImage( + object_, src(), dst(), (const ::size_t *) src_origin, + (const ::size_t *)dst_origin, (const ::size_t *) region, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_COPY_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +#if defined(CL_VERSION_1_2) + /** + * Enqueue a command to fill an image object with a specified color. + * \param fillColor is the color to use to fill the image. + * This is a four component RGBA floating-point color value if + * the image channel data type is not an unnormalized signed or + * unsigned data type. + */ + cl_int enqueueFillImage( + const Image& image, + cl_float4 fillColor, + const size_t<3>& origin, + const size_t<3>& region, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueFillImage( + object_, + image(), + static_cast(&fillColor), + (const ::size_t *) origin, + (const ::size_t *) region, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_FILL_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueue a command to fill an image object with a specified color. + * \param fillColor is the color to use to fill the image. + * This is a four component RGBA signed integer color value if + * the image channel data type is an unnormalized signed integer + * type. + */ + cl_int enqueueFillImage( + const Image& image, + cl_int4 fillColor, + const size_t<3>& origin, + const size_t<3>& region, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueFillImage( + object_, + image(), + static_cast(&fillColor), + (const ::size_t *) origin, + (const ::size_t *) region, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_FILL_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueue a command to fill an image object with a specified color. + * \param fillColor is the color to use to fill the image. + * This is a four component RGBA unsigned integer color value if + * the image channel data type is an unnormalized unsigned integer + * type. + */ + cl_int enqueueFillImage( + const Image& image, + cl_uint4 fillColor, + const size_t<3>& origin, + const size_t<3>& region, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueFillImage( + object_, + image(), + static_cast(&fillColor), + (const ::size_t *) origin, + (const ::size_t *) region, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_FILL_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // #if defined(CL_VERSION_1_2) + + cl_int enqueueCopyImageToBuffer( + const Image& src, + const Buffer& dst, + const size_t<3>& src_origin, + const size_t<3>& region, + ::size_t dst_offset, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyImageToBuffer( + object_, src(), dst(), (const ::size_t *) src_origin, + (const ::size_t *) region, dst_offset, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_COPY_IMAGE_TO_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueCopyBufferToImage( + const Buffer& src, + const Image& dst, + ::size_t src_offset, + const size_t<3>& dst_origin, + const size_t<3>& region, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyBufferToImage( + object_, src(), dst(), src_offset, + (const ::size_t *) dst_origin, (const ::size_t *) region, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_COPY_BUFFER_TO_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + void* enqueueMapBuffer( + const Buffer& buffer, + cl_bool blocking, + cl_map_flags flags, + ::size_t offset, + ::size_t size, + const VECTOR_CLASS* events = NULL, + Event* event = NULL, + cl_int* err = NULL) const + { + cl_int error; + void * result = ::clEnqueueMapBuffer( + object_, buffer(), blocking, flags, offset, size, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (cl_event*) event, + &error); + + detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + return result; + } + + void* enqueueMapImage( + const Image& buffer, + cl_bool blocking, + cl_map_flags flags, + const size_t<3>& origin, + const size_t<3>& region, + ::size_t * row_pitch, + ::size_t * slice_pitch, + const VECTOR_CLASS* events = NULL, + Event* event = NULL, + cl_int* err = NULL) const + { + cl_int error; + void * result = ::clEnqueueMapImage( + object_, buffer(), blocking, flags, + (const ::size_t *) origin, (const ::size_t *) region, + row_pitch, slice_pitch, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (cl_event*) event, + &error); + + detail::errHandler(error, __ENQUEUE_MAP_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + return result; + } + + cl_int enqueueUnmapMemObject( + const Memory& memory, + void* mapped_ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueUnmapMemObject( + object_, memory(), mapped_ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +#if defined(CL_VERSION_1_2) + /** + * Enqueues a marker command which waits for either a list of events to complete, + * or all previously enqueued commands to complete. + * + * Enqueues a marker command which waits for either a list of events to complete, + * or if the list is empty it waits for all commands previously enqueued in command_queue + * to complete before it completes. This command returns an event which can be waited on, + * i.e. this event can be waited on to insure that all events either in the event_wait_list + * or all previously enqueued commands, queued before this command to command_queue, + * have completed. + */ + cl_int enqueueMarkerWithWaitList( + const VECTOR_CLASS *events = 0, + Event *event = 0) + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueMarkerWithWaitList( + object_, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_MARKER_WAIT_LIST_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * A synchronization point that enqueues a barrier operation. + * + * Enqueues a barrier command which waits for either a list of events to complete, + * or if the list is empty it waits for all commands previously enqueued in command_queue + * to complete before it completes. This command blocks command execution, that is, any + * following commands enqueued after it do not execute until it completes. This command + * returns an event which can be waited on, i.e. this event can be waited on to insure that + * all events either in the event_wait_list or all previously enqueued commands, queued + * before this command to command_queue, have completed. + */ + cl_int enqueueBarrierWithWaitList( + const VECTOR_CLASS *events = 0, + Event *event = 0) + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueBarrierWithWaitList( + object_, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_BARRIER_WAIT_LIST_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueues a command to indicate with which device a set of memory objects + * should be associated. + */ + cl_int enqueueMigrateMemObjects( + const VECTOR_CLASS &memObjects, + cl_mem_migration_flags flags, + const VECTOR_CLASS* events = NULL, + Event* event = NULL + ) + { + cl_event tmp; + + cl_mem* localMemObjects = static_cast(alloca(memObjects.size() * sizeof(cl_mem))); + for( int i = 0; i < (int)memObjects.size(); ++i ) { + localMemObjects[i] = memObjects[i](); + } + + + cl_int err = detail::errHandler( + ::clEnqueueMigrateMemObjects( + object_, + (cl_uint)memObjects.size(), + static_cast(localMemObjects), + flags, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // #if defined(CL_VERSION_1_2) + + cl_int enqueueNDRangeKernel( + const Kernel& kernel, + const NDRange& offset, + const NDRange& global, + const NDRange& local = NullRange, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueNDRangeKernel( + object_, kernel(), (cl_uint) global.dimensions(), + offset.dimensions() != 0 ? (const ::size_t*) offset : NULL, + (const ::size_t*) global, + local.dimensions() != 0 ? (const ::size_t*) local : NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_NDRANGE_KERNEL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueTask( + const Kernel& kernel, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueTask( + object_, kernel(), + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_TASK_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueNativeKernel( + void (CL_CALLBACK *userFptr)(void *), + std::pair args, + const VECTOR_CLASS* mem_objects = NULL, + const VECTOR_CLASS* mem_locs = NULL, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_mem * mems = (mem_objects != NULL && mem_objects->size() > 0) + ? (cl_mem*) alloca(mem_objects->size() * sizeof(cl_mem)) + : NULL; + + if (mems != NULL) { + for (unsigned int i = 0; i < mem_objects->size(); i++) { + mems[i] = ((*mem_objects)[i])(); + } + } + + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueNativeKernel( + object_, userFptr, args.first, args.second, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + mems, + (mem_locs != NULL) ? (const void **) &mem_locs->front() : NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_NATIVE_KERNEL); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) || (defined(CL_VERSION_1_1) && !defined(CL_VERSION_1_2)) + CL_EXT_PREFIX__VERSION_1_1_DEPRECATED + cl_int enqueueMarker(Event* event = NULL) const CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED + { + return detail::errHandler( + ::clEnqueueMarker(object_, (cl_event*) event), + __ENQUEUE_MARKER_ERR); + } + + CL_EXT_PREFIX__VERSION_1_1_DEPRECATED + cl_int enqueueWaitForEvents(const VECTOR_CLASS& events) const CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED + { + return detail::errHandler( + ::clEnqueueWaitForEvents( + object_, + (cl_uint) events.size(), + (const cl_event*) &events.front()), + __ENQUEUE_WAIT_FOR_EVENTS_ERR); + } +#endif // #if defined(CL_VERSION_1_1) + + cl_int enqueueAcquireGLObjects( + const VECTOR_CLASS* mem_objects = NULL, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueAcquireGLObjects( + object_, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + (mem_objects != NULL) ? (const cl_mem *) &mem_objects->front(): NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_ACQUIRE_GL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueReleaseGLObjects( + const VECTOR_CLASS* mem_objects = NULL, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueReleaseGLObjects( + object_, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + (mem_objects != NULL) ? (const cl_mem *) &mem_objects->front(): NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_RELEASE_GL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +#if defined (USE_DX_INTEROP) +typedef CL_API_ENTRY cl_int (CL_API_CALL *PFN_clEnqueueAcquireD3D10ObjectsKHR)( + cl_command_queue command_queue, cl_uint num_objects, + const cl_mem* mem_objects, cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, cl_event* event); +typedef CL_API_ENTRY cl_int (CL_API_CALL *PFN_clEnqueueReleaseD3D10ObjectsKHR)( + cl_command_queue command_queue, cl_uint num_objects, + const cl_mem* mem_objects, cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, cl_event* event); + + cl_int enqueueAcquireD3D10Objects( + const VECTOR_CLASS* mem_objects = NULL, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + static PFN_clEnqueueAcquireD3D10ObjectsKHR pfn_clEnqueueAcquireD3D10ObjectsKHR = NULL; +#if defined(CL_VERSION_1_2) + cl_context context = getInfo(); + cl::Device device(getInfo()); + cl_platform_id platform = device.getInfo(); + __INIT_CL_EXT_FCN_PTR_PLATFORM(platform, clEnqueueAcquireD3D10ObjectsKHR); +#endif +#if defined(CL_VERSION_1_1) + __INIT_CL_EXT_FCN_PTR(clEnqueueAcquireD3D10ObjectsKHR); +#endif + + cl_event tmp; + cl_int err = detail::errHandler( + pfn_clEnqueueAcquireD3D10ObjectsKHR( + object_, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + (mem_objects != NULL) ? (const cl_mem *) &mem_objects->front(): NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_ACQUIRE_GL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueReleaseD3D10Objects( + const VECTOR_CLASS* mem_objects = NULL, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) const + { + static PFN_clEnqueueReleaseD3D10ObjectsKHR pfn_clEnqueueReleaseD3D10ObjectsKHR = NULL; +#if defined(CL_VERSION_1_2) + cl_context context = getInfo(); + cl::Device device(getInfo()); + cl_platform_id platform = device.getInfo(); + __INIT_CL_EXT_FCN_PTR_PLATFORM(platform, clEnqueueReleaseD3D10ObjectsKHR); +#endif // #if defined(CL_VERSION_1_2) +#if defined(CL_VERSION_1_1) + __INIT_CL_EXT_FCN_PTR(clEnqueueReleaseD3D10ObjectsKHR); +#endif // #if defined(CL_VERSION_1_1) + + cl_event tmp; + cl_int err = detail::errHandler( + pfn_clEnqueueReleaseD3D10ObjectsKHR( + object_, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + (mem_objects != NULL) ? (const cl_mem *) &mem_objects->front(): NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_RELEASE_GL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) || (defined(CL_VERSION_1_1) && !defined(CL_VERSION_1_2)) + CL_EXT_PREFIX__VERSION_1_1_DEPRECATED + cl_int enqueueBarrier() const CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED + { + return detail::errHandler( + ::clEnqueueBarrier(object_), + __ENQUEUE_BARRIER_ERR); + } +#endif // #if defined(CL_VERSION_1_1) + + cl_int flush() const + { + return detail::errHandler(::clFlush(object_), __FLUSH_ERR); + } + + cl_int finish() const + { + return detail::errHandler(::clFinish(object_), __FINISH_ERR); + } +}; + +#ifdef _WIN32 +__declspec(selectany) volatile int CommandQueue::default_initialized_ = __DEFAULT_NOT_INITIALIZED; +__declspec(selectany) CommandQueue CommandQueue::default_; +__declspec(selectany) volatile cl_int CommandQueue::default_error_ = CL_SUCCESS; +#else +__attribute__((weak)) volatile int CommandQueue::default_initialized_ = __DEFAULT_NOT_INITIALIZED; +__attribute__((weak)) CommandQueue CommandQueue::default_; +__attribute__((weak)) volatile cl_int CommandQueue::default_error_ = CL_SUCCESS; +#endif + +template< typename IteratorType > +Buffer::Buffer( + const Context &context, + IteratorType startIterator, + IteratorType endIterator, + bool readOnly, + bool useHostPtr, + cl_int* err) +{ + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + cl_mem_flags flags = 0; + if( readOnly ) { + flags |= CL_MEM_READ_ONLY; + } + else { + flags |= CL_MEM_READ_WRITE; + } + if( useHostPtr ) { + flags |= CL_MEM_USE_HOST_PTR; + } + + ::size_t size = sizeof(DataType)*(endIterator - startIterator); + + if( useHostPtr ) { + object_ = ::clCreateBuffer(context(), flags, size, static_cast(&*startIterator), &error); + } else { + object_ = ::clCreateBuffer(context(), flags, size, 0, &error); + } + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + if( !useHostPtr ) { + CommandQueue queue(context, 0, &error); + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + error = cl::copy(queue, startIterator, endIterator, *this); + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } +} + +inline cl_int enqueueReadBuffer( + const Buffer& buffer, + cl_bool blocking, + ::size_t offset, + ::size_t size, + void* ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueReadBuffer(buffer, blocking, offset, size, ptr, events, event); +} + +inline cl_int enqueueWriteBuffer( + const Buffer& buffer, + cl_bool blocking, + ::size_t offset, + ::size_t size, + const void* ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueWriteBuffer(buffer, blocking, offset, size, ptr, events, event); +} + +inline void* enqueueMapBuffer( + const Buffer& buffer, + cl_bool blocking, + cl_map_flags flags, + ::size_t offset, + ::size_t size, + const VECTOR_CLASS* events = NULL, + Event* event = NULL, + cl_int* err = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + void * result = ::clEnqueueMapBuffer( + queue(), buffer(), blocking, flags, offset, size, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (cl_event*) event, + &error); + + detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + return result; +} + +inline cl_int enqueueUnmapMemObject( + const Memory& memory, + void* mapped_ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + if (error != CL_SUCCESS) { + return error; + } + + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueUnmapMemObject( + queue(), memory(), mapped_ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; +} + +inline cl_int enqueueCopyBuffer( + const Buffer& src, + const Buffer& dst, + ::size_t src_offset, + ::size_t dst_offset, + ::size_t size, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyBuffer(src, dst, src_offset, dst_offset, size, events, event); +} + +/** + * Blocking copy operation between iterators and a buffer. + * Host to Device. + * Uses default command queue. + */ +template< typename IteratorType > +inline cl_int copy( IteratorType startIterator, IteratorType endIterator, cl::Buffer &buffer ) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) + return error; + + return cl::copy(queue, startIterator, endIterator, buffer); +} + +/** + * Blocking copy operation between iterators and a buffer. + * Device to Host. + * Uses default command queue. + */ +template< typename IteratorType > +inline cl_int copy( const cl::Buffer &buffer, IteratorType startIterator, IteratorType endIterator ) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) + return error; + + return cl::copy(queue, buffer, startIterator, endIterator); +} + +/** + * Blocking copy operation between iterators and a buffer. + * Host to Device. + * Uses specified queue. + */ +template< typename IteratorType > +inline cl_int copy( const CommandQueue &queue, IteratorType startIterator, IteratorType endIterator, cl::Buffer &buffer ) +{ + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + ::size_t length = endIterator-startIterator; + ::size_t byteLength = length*sizeof(DataType); + + DataType *pointer = + static_cast(queue.enqueueMapBuffer(buffer, CL_TRUE, CL_MAP_WRITE, 0, byteLength, 0, 0, &error)); + // if exceptions enabled, enqueueMapBuffer will throw + if( error != CL_SUCCESS ) { + return error; + } +#if defined(_MSC_VER) + std::copy( + startIterator, + endIterator, + stdext::checked_array_iterator( + pointer, length)); +#else + std::copy(startIterator, endIterator, pointer); +#endif + Event endEvent; + error = queue.enqueueUnmapMemObject(buffer, pointer, 0, &endEvent); + // if exceptions enabled, enqueueUnmapMemObject will throw + if( error != CL_SUCCESS ) { + return error; + } + endEvent.wait(); + return CL_SUCCESS; +} + +/** + * Blocking copy operation between iterators and a buffer. + * Device to Host. + * Uses specified queue. + */ +template< typename IteratorType > +inline cl_int copy( const CommandQueue &queue, const cl::Buffer &buffer, IteratorType startIterator, IteratorType endIterator ) +{ + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + ::size_t length = endIterator-startIterator; + ::size_t byteLength = length*sizeof(DataType); + + DataType *pointer = + static_cast(queue.enqueueMapBuffer(buffer, CL_TRUE, CL_MAP_READ, 0, byteLength, 0, 0, &error)); + // if exceptions enabled, enqueueMapBuffer will throw + if( error != CL_SUCCESS ) { + return error; + } + std::copy(pointer, pointer + length, startIterator); + Event endEvent; + error = queue.enqueueUnmapMemObject(buffer, pointer, 0, &endEvent); + // if exceptions enabled, enqueueUnmapMemObject will throw + if( error != CL_SUCCESS ) { + return error; + } + endEvent.wait(); + return CL_SUCCESS; +} + +#if defined(CL_VERSION_1_1) +inline cl_int enqueueReadBufferRect( + const Buffer& buffer, + cl_bool blocking, + const size_t<3>& buffer_offset, + const size_t<3>& host_offset, + const size_t<3>& region, + ::size_t buffer_row_pitch, + ::size_t buffer_slice_pitch, + ::size_t host_row_pitch, + ::size_t host_slice_pitch, + void *ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueReadBufferRect( + buffer, + blocking, + buffer_offset, + host_offset, + region, + buffer_row_pitch, + buffer_slice_pitch, + host_row_pitch, + host_slice_pitch, + ptr, + events, + event); +} + +inline cl_int enqueueWriteBufferRect( + const Buffer& buffer, + cl_bool blocking, + const size_t<3>& buffer_offset, + const size_t<3>& host_offset, + const size_t<3>& region, + ::size_t buffer_row_pitch, + ::size_t buffer_slice_pitch, + ::size_t host_row_pitch, + ::size_t host_slice_pitch, + void *ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueWriteBufferRect( + buffer, + blocking, + buffer_offset, + host_offset, + region, + buffer_row_pitch, + buffer_slice_pitch, + host_row_pitch, + host_slice_pitch, + ptr, + events, + event); +} + +inline cl_int enqueueCopyBufferRect( + const Buffer& src, + const Buffer& dst, + const size_t<3>& src_origin, + const size_t<3>& dst_origin, + const size_t<3>& region, + ::size_t src_row_pitch, + ::size_t src_slice_pitch, + ::size_t dst_row_pitch, + ::size_t dst_slice_pitch, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyBufferRect( + src, + dst, + src_origin, + dst_origin, + region, + src_row_pitch, + src_slice_pitch, + dst_row_pitch, + dst_slice_pitch, + events, + event); +} +#endif + +inline cl_int enqueueReadImage( + const Image& image, + cl_bool blocking, + const size_t<3>& origin, + const size_t<3>& region, + ::size_t row_pitch, + ::size_t slice_pitch, + void* ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueReadImage( + image, + blocking, + origin, + region, + row_pitch, + slice_pitch, + ptr, + events, + event); +} + +inline cl_int enqueueWriteImage( + const Image& image, + cl_bool blocking, + const size_t<3>& origin, + const size_t<3>& region, + ::size_t row_pitch, + ::size_t slice_pitch, + void* ptr, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueWriteImage( + image, + blocking, + origin, + region, + row_pitch, + slice_pitch, + ptr, + events, + event); +} + +inline cl_int enqueueCopyImage( + const Image& src, + const Image& dst, + const size_t<3>& src_origin, + const size_t<3>& dst_origin, + const size_t<3>& region, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyImage( + src, + dst, + src_origin, + dst_origin, + region, + events, + event); +} + +inline cl_int enqueueCopyImageToBuffer( + const Image& src, + const Buffer& dst, + const size_t<3>& src_origin, + const size_t<3>& region, + ::size_t dst_offset, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyImageToBuffer( + src, + dst, + src_origin, + region, + dst_offset, + events, + event); +} + +inline cl_int enqueueCopyBufferToImage( + const Buffer& src, + const Image& dst, + ::size_t src_offset, + const size_t<3>& dst_origin, + const size_t<3>& region, + const VECTOR_CLASS* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyBufferToImage( + src, + dst, + src_offset, + dst_origin, + region, + events, + event); +} + + +inline cl_int flush(void) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.flush(); +} + +inline cl_int finish(void) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + + return queue.finish(); +} + +// Kernel Functor support +// New interface as of September 2011 +// Requires the C++11 std::tr1::function (note do not support TR1) +// Visual Studio 2010 and GCC 4.2 + +struct EnqueueArgs +{ + CommandQueue queue_; + const NDRange offset_; + const NDRange global_; + const NDRange local_; + VECTOR_CLASS events_; + + EnqueueArgs(NDRange global) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(NullRange) + { + + } + + EnqueueArgs(NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(local) + { + + } + + EnqueueArgs(NDRange offset, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(offset), + global_(global), + local_(local) + { + + } + + EnqueueArgs(Event e, NDRange global) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(NullRange) + { + events_.push_back(e); + } + + EnqueueArgs(Event e, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(local) + { + events_.push_back(e); + } + + EnqueueArgs(Event e, NDRange offset, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(offset), + global_(global), + local_(local) + { + events_.push_back(e); + } + + EnqueueArgs(const VECTOR_CLASS &events, NDRange global) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(NullRange), + events_(events) + { + + } + + EnqueueArgs(const VECTOR_CLASS &events, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(local), + events_(events) + { + + } + + EnqueueArgs(const VECTOR_CLASS &events, NDRange offset, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(offset), + global_(global), + local_(local), + events_(events) + { + + } + + EnqueueArgs(CommandQueue &queue, NDRange global) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(NullRange) + { + + } + + EnqueueArgs(CommandQueue &queue, NDRange global, NDRange local) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(local) + { + + } + + EnqueueArgs(CommandQueue &queue, NDRange offset, NDRange global, NDRange local) : + queue_(queue), + offset_(offset), + global_(global), + local_(local) + { + + } + + EnqueueArgs(CommandQueue &queue, Event e, NDRange global) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(NullRange) + { + events_.push_back(e); + } + + EnqueueArgs(CommandQueue &queue, Event e, NDRange global, NDRange local) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(local) + { + events_.push_back(e); + } + + EnqueueArgs(CommandQueue &queue, Event e, NDRange offset, NDRange global, NDRange local) : + queue_(queue), + offset_(offset), + global_(global), + local_(local) + { + events_.push_back(e); + } + + EnqueueArgs(CommandQueue &queue, const VECTOR_CLASS &events, NDRange global) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(NullRange), + events_(events) + { + + } + + EnqueueArgs(CommandQueue &queue, const VECTOR_CLASS &events, NDRange global, NDRange local) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(local), + events_(events) + { + + } + + EnqueueArgs(CommandQueue &queue, const VECTOR_CLASS &events, NDRange offset, NDRange global, NDRange local) : + queue_(queue), + offset_(offset), + global_(global), + local_(local), + events_(events) + { + + } +}; + +namespace detail { + +class NullType {}; + +template +struct SetArg +{ + static void set (Kernel kernel, T0 arg) + { + kernel.setArg(index, arg); + } +}; + +template +struct SetArg +{ + static void set (Kernel, NullType) + { + } +}; + +template < + typename T0, typename T1, typename T2, typename T3, + typename T4, typename T5, typename T6, typename T7, + typename T8, typename T9, typename T10, typename T11, + typename T12, typename T13, typename T14, typename T15, + typename T16, typename T17, typename T18, typename T19, + typename T20, typename T21, typename T22, typename T23, + typename T24, typename T25, typename T26, typename T27, + typename T28, typename T29, typename T30, typename T31 +> +class KernelFunctorGlobal +{ +private: + Kernel kernel_; + +public: + KernelFunctorGlobal( + Kernel kernel) : + kernel_(kernel) + {} + + KernelFunctorGlobal( + const Program& program, + const STRING_CLASS name, + cl_int * err = NULL) : + kernel_(program, name.c_str(), err) + {} + + Event operator() ( + const EnqueueArgs& args, + T0 t0, + T1 t1 = NullType(), + T2 t2 = NullType(), + T3 t3 = NullType(), + T4 t4 = NullType(), + T5 t5 = NullType(), + T6 t6 = NullType(), + T7 t7 = NullType(), + T8 t8 = NullType(), + T9 t9 = NullType(), + T10 t10 = NullType(), + T11 t11 = NullType(), + T12 t12 = NullType(), + T13 t13 = NullType(), + T14 t14 = NullType(), + T15 t15 = NullType(), + T16 t16 = NullType(), + T17 t17 = NullType(), + T18 t18 = NullType(), + T19 t19 = NullType(), + T20 t20 = NullType(), + T21 t21 = NullType(), + T22 t22 = NullType(), + T23 t23 = NullType(), + T24 t24 = NullType(), + T25 t25 = NullType(), + T26 t26 = NullType(), + T27 t27 = NullType(), + T28 t28 = NullType(), + T29 t29 = NullType(), + T30 t30 = NullType(), + T31 t31 = NullType() + ) + { + Event event; + SetArg<0, T0>::set(kernel_, t0); + SetArg<1, T1>::set(kernel_, t1); + SetArg<2, T2>::set(kernel_, t2); + SetArg<3, T3>::set(kernel_, t3); + SetArg<4, T4>::set(kernel_, t4); + SetArg<5, T5>::set(kernel_, t5); + SetArg<6, T6>::set(kernel_, t6); + SetArg<7, T7>::set(kernel_, t7); + SetArg<8, T8>::set(kernel_, t8); + SetArg<9, T9>::set(kernel_, t9); + SetArg<10, T10>::set(kernel_, t10); + SetArg<11, T11>::set(kernel_, t11); + SetArg<12, T12>::set(kernel_, t12); + SetArg<13, T13>::set(kernel_, t13); + SetArg<14, T14>::set(kernel_, t14); + SetArg<15, T15>::set(kernel_, t15); + SetArg<16, T16>::set(kernel_, t16); + SetArg<17, T17>::set(kernel_, t17); + SetArg<18, T18>::set(kernel_, t18); + SetArg<19, T19>::set(kernel_, t19); + SetArg<20, T20>::set(kernel_, t20); + SetArg<21, T21>::set(kernel_, t21); + SetArg<22, T22>::set(kernel_, t22); + SetArg<23, T23>::set(kernel_, t23); + SetArg<24, T24>::set(kernel_, t24); + SetArg<25, T25>::set(kernel_, t25); + SetArg<26, T26>::set(kernel_, t26); + SetArg<27, T27>::set(kernel_, t27); + SetArg<28, T28>::set(kernel_, t28); + SetArg<29, T29>::set(kernel_, t29); + SetArg<30, T30>::set(kernel_, t30); + SetArg<31, T31>::set(kernel_, t31); + + args.queue_.enqueueNDRangeKernel( + kernel_, + args.offset_, + args.global_, + args.local_, + &args.events_, + &event); + + return event; + } + +}; + +//------------------------------------------------------------------------------------------------------ + + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23, + typename T24, + typename T25, + typename T26, + typename T27, + typename T28, + typename T29, + typename T30, + typename T31> +struct functionImplementation_ +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + T29, + T30, + T31> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 32)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + T29, + T30, + T31); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23, + T24 arg24, + T25 arg25, + T26 arg26, + T27 arg27, + T28 arg28, + T29 arg29, + T30 arg30, + T31 arg31) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23, + arg24, + arg25, + arg26, + arg27, + arg28, + arg29, + arg30, + arg31); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23, + typename T24, + typename T25, + typename T26, + typename T27, + typename T28, + typename T29, + typename T30> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + T29, + T30, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + T29, + T30, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 31)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + T29, + T30); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23, + T24 arg24, + T25 arg25, + T26 arg26, + T27 arg27, + T28 arg28, + T29 arg29, + T30 arg30) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23, + arg24, + arg25, + arg26, + arg27, + arg28, + arg29, + arg30); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23, + typename T24, + typename T25, + typename T26, + typename T27, + typename T28, + typename T29> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + T29, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + T29, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 30)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + T29); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23, + T24 arg24, + T25 arg25, + T26 arg26, + T27 arg27, + T28 arg28, + T29 arg29) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23, + arg24, + arg25, + arg26, + arg27, + arg28, + arg29); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23, + typename T24, + typename T25, + typename T26, + typename T27, + typename T28> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 29)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + T28); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23, + T24 arg24, + T25 arg25, + T26 arg26, + T27 arg27, + T28 arg28) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23, + arg24, + arg25, + arg26, + arg27, + arg28); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23, + typename T24, + typename T25, + typename T26, + typename T27> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 28)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + T27); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23, + T24 arg24, + T25 arg25, + T26 arg26, + T27 arg27) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23, + arg24, + arg25, + arg26, + arg27); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23, + typename T24, + typename T25, + typename T26> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 27)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + T26); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23, + T24 arg24, + T25 arg25, + T26 arg26) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23, + arg24, + arg25, + arg26); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23, + typename T24, + typename T25> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 26)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + T25); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23, + T24 arg24, + T25 arg25) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23, + arg24, + arg25); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23, + typename T24> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 25)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + T24); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23, + T24 arg24) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23, + arg24); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22, + typename T23> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 24)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + T23); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22, + T23 arg23) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22, + arg23); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21, + typename T22> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 23)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + T22); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21, + T22 arg22) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21, + arg22); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20, + typename T21> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 22)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + T21); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20, + T21 arg21) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20, + arg21); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19, + typename T20> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 21)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + T20); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19, + T20 arg20) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19, + arg20); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18, + typename T19> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 20)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + T19); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18, + T19 arg19) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18, + arg19); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17, + typename T18> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 19)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + T18); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17, + T18 arg18) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17, + arg18); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16, + typename T17> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 18)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + T17); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16, + T17 arg17) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16, + arg17); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15, + typename T16> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 17)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + T16); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15, + T16 arg16) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15, + arg16); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14, + typename T15> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 16)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + T15); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14, + T15 arg15) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14, + arg15); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13, + typename T14> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 15)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + T14); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13, + T14 arg14) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13, + arg14); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12, + typename T13> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 14)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + T13); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12, + T13 arg13) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12, + arg13); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11, + typename T12> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 13)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + T12); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11, + T12 arg12) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11, + arg12); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10, + typename T11> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 12)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + T11); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10, + T11 arg11) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10, + arg11); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9, + typename T10> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 11)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + T10); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9, + T10 arg10) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9, + arg10); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8, + typename T9> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 10)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + T9); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8, + T9 arg9) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8, + arg9); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7, + typename T8> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 9)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + T8); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7, + T8 arg8) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7, + arg8); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6, + typename T7> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 8)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6, + T7); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6, + T7 arg7) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6, + arg7); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5, + typename T6> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + T6, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + T6, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 7)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5, + T6); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5, + T6 arg6) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5, + arg6); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4, + typename T5> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + T5, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + T5, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 6)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4, + T5); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4, + T5 arg5) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4, + arg5); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3, + typename T4> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + T4, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + T4, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 5)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3, + T4); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3, + T4 arg4) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3, + arg4); + } + + +}; + +template< + typename T0, + typename T1, + typename T2, + typename T3> +struct functionImplementation_ +< T0, + T1, + T2, + T3, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + T3, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 4)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2, + T3); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2, + T3 arg3) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2, + arg3); + } + + +}; + +template< + typename T0, + typename T1, + typename T2> +struct functionImplementation_ +< T0, + T1, + T2, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + T2, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 3)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1, + T2); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1, + T2 arg2) + { + return functor_( + enqueueArgs, + arg0, + arg1, + arg2); + } + + +}; + +template< + typename T0, + typename T1> +struct functionImplementation_ +< T0, + T1, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + T1, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 2)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0, + T1); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0, + T1 arg1) + { + return functor_( + enqueueArgs, + arg0, + arg1); + } + + +}; + +template< + typename T0> +struct functionImplementation_ +< T0, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> +{ + typedef detail::KernelFunctorGlobal< + T0, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType, + NullType> FunctorType; + + FunctorType functor_; + + functionImplementation_(const FunctorType &functor) : + functor_(functor) + { + + #if (defined(_WIN32) && defined(_VARIADIC_MAX) && (_VARIADIC_MAX < 1)) + // Fail variadic expansion for dev11 + static_assert(0, "Visual Studio has a hard limit of argument count for a std::function expansion. Please define _VARIADIC_MAX to be 10. If you need more arguments than that VC12 and below cannot support it."); + #endif + + } + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + T0); + + Event operator()( + const EnqueueArgs& enqueueArgs, + T0 arg0) + { + return functor_( + enqueueArgs, + arg0); + } + + +}; + + + + + +} // namespace detail + +//---------------------------------------------------------------------------------------------- + +template < + typename T0, typename T1 = detail::NullType, typename T2 = detail::NullType, + typename T3 = detail::NullType, typename T4 = detail::NullType, + typename T5 = detail::NullType, typename T6 = detail::NullType, + typename T7 = detail::NullType, typename T8 = detail::NullType, + typename T9 = detail::NullType, typename T10 = detail::NullType, + typename T11 = detail::NullType, typename T12 = detail::NullType, + typename T13 = detail::NullType, typename T14 = detail::NullType, + typename T15 = detail::NullType, typename T16 = detail::NullType, + typename T17 = detail::NullType, typename T18 = detail::NullType, + typename T19 = detail::NullType, typename T20 = detail::NullType, + typename T21 = detail::NullType, typename T22 = detail::NullType, + typename T23 = detail::NullType, typename T24 = detail::NullType, + typename T25 = detail::NullType, typename T26 = detail::NullType, + typename T27 = detail::NullType, typename T28 = detail::NullType, + typename T29 = detail::NullType, typename T30 = detail::NullType, + typename T31 = detail::NullType +> +struct make_kernel : + public detail::functionImplementation_< + T0, T1, T2, T3, + T4, T5, T6, T7, + T8, T9, T10, T11, + T12, T13, T14, T15, + T16, T17, T18, T19, + T20, T21, T22, T23, + T24, T25, T26, T27, + T28, T29, T30, T31 + > +{ +public: + typedef detail::KernelFunctorGlobal< + T0, T1, T2, T3, + T4, T5, T6, T7, + T8, T9, T10, T11, + T12, T13, T14, T15, + T16, T17, T18, T19, + T20, T21, T22, T23, + T24, T25, T26, T27, + T28, T29, T30, T31 + > FunctorType; + + make_kernel( + const Program& program, + const STRING_CLASS name, + cl_int * err = NULL) : + detail::functionImplementation_< + T0, T1, T2, T3, + T4, T5, T6, T7, + T8, T9, T10, T11, + T12, T13, T14, T15, + T16, T17, T18, T19, + T20, T21, T22, T23, + T24, T25, T26, T27, + T28, T29, T30, T31 + >( + FunctorType(program, name, err)) + {} + + make_kernel( + const Kernel kernel) : + detail::functionImplementation_< + T0, T1, T2, T3, + T4, T5, T6, T7, + T8, T9, T10, T11, + T12, T13, T14, T15, + T16, T17, T18, T19, + T20, T21, T22, T23, + T24, T25, T26, T27, + T28, T29, T30, T31 + >( + FunctorType(kernel)) + {} +}; + + +//---------------------------------------------------------------------------------------------------------------------- + +#undef __ERR_STR +#if !defined(__CL_USER_OVERRIDE_ERROR_STRINGS) +#undef __GET_DEVICE_INFO_ERR +#undef __GET_PLATFORM_INFO_ERR +#undef __GET_DEVICE_IDS_ERR +#undef __GET_CONTEXT_INFO_ERR +#undef __GET_EVENT_INFO_ERR +#undef __GET_EVENT_PROFILE_INFO_ERR +#undef __GET_MEM_OBJECT_INFO_ERR +#undef __GET_IMAGE_INFO_ERR +#undef __GET_SAMPLER_INFO_ERR +#undef __GET_KERNEL_INFO_ERR +#undef __GET_KERNEL_ARG_INFO_ERR +#undef __GET_KERNEL_WORK_GROUP_INFO_ERR +#undef __GET_PROGRAM_INFO_ERR +#undef __GET_PROGRAM_BUILD_INFO_ERR +#undef __GET_COMMAND_QUEUE_INFO_ERR + +#undef __CREATE_CONTEXT_ERR +#undef __CREATE_CONTEXT_FROM_TYPE_ERR +#undef __GET_SUPPORTED_IMAGE_FORMATS_ERR + +#undef __CREATE_BUFFER_ERR +#undef __CREATE_SUBBUFFER_ERR +#undef __CREATE_IMAGE2D_ERR +#undef __CREATE_IMAGE3D_ERR +#undef __CREATE_SAMPLER_ERR +#undef __SET_MEM_OBJECT_DESTRUCTOR_CALLBACK_ERR + +#undef __CREATE_USER_EVENT_ERR +#undef __SET_USER_EVENT_STATUS_ERR +#undef __SET_EVENT_CALLBACK_ERR +#undef __SET_PRINTF_CALLBACK_ERR + +#undef __WAIT_FOR_EVENTS_ERR + +#undef __CREATE_KERNEL_ERR +#undef __SET_KERNEL_ARGS_ERR +#undef __CREATE_PROGRAM_WITH_SOURCE_ERR +#undef __CREATE_PROGRAM_WITH_BINARY_ERR +#undef __CREATE_PROGRAM_WITH_BUILT_IN_KERNELS_ERR +#undef __BUILD_PROGRAM_ERR +#undef __CREATE_KERNELS_IN_PROGRAM_ERR + +#undef __CREATE_COMMAND_QUEUE_ERR +#undef __SET_COMMAND_QUEUE_PROPERTY_ERR +#undef __ENQUEUE_READ_BUFFER_ERR +#undef __ENQUEUE_WRITE_BUFFER_ERR +#undef __ENQUEUE_READ_BUFFER_RECT_ERR +#undef __ENQUEUE_WRITE_BUFFER_RECT_ERR +#undef __ENQUEUE_COPY_BUFFER_ERR +#undef __ENQUEUE_COPY_BUFFER_RECT_ERR +#undef __ENQUEUE_READ_IMAGE_ERR +#undef __ENQUEUE_WRITE_IMAGE_ERR +#undef __ENQUEUE_COPY_IMAGE_ERR +#undef __ENQUEUE_COPY_IMAGE_TO_BUFFER_ERR +#undef __ENQUEUE_COPY_BUFFER_TO_IMAGE_ERR +#undef __ENQUEUE_MAP_BUFFER_ERR +#undef __ENQUEUE_MAP_IMAGE_ERR +#undef __ENQUEUE_UNMAP_MEM_OBJECT_ERR +#undef __ENQUEUE_NDRANGE_KERNEL_ERR +#undef __ENQUEUE_TASK_ERR +#undef __ENQUEUE_NATIVE_KERNEL + +#undef __CL_EXPLICIT_CONSTRUCTORS + +#undef __UNLOAD_COMPILER_ERR +#endif //__CL_USER_OVERRIDE_ERROR_STRINGS + +#undef __CL_FUNCTION_TYPE + +// Extensions +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_VERSION_1_1) +#undef __INIT_CL_EXT_FCN_PTR +#endif // #if defined(CL_VERSION_1_1) +#undef __CREATE_SUB_DEVICES + +#if defined(USE_CL_DEVICE_FISSION) +#undef __PARAM_NAME_DEVICE_FISSION +#endif // USE_CL_DEVICE_FISSION + +#undef __DEFAULT_NOT_INITIALIZED +#undef __DEFAULT_BEING_INITIALIZED +#undef __DEFAULT_INITIALIZED + +} // namespace cl + +#ifdef _WIN32 +#pragma pop_macro("max") +#endif // _WIN32 + +#endif // CL_HPP_ diff --git a/benchmarks/new_opencl/include/CL/cl2.hpp b/benchmarks/new_opencl/include/CL/cl2.hpp new file mode 100644 index 00000000..da5ee88c --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl2.hpp @@ -0,0 +1,10119 @@ +/******************************************************************************* + * Copyright (c) 2008-2016 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + ******************************************************************************/ + +/*! \file + * + * \brief C++ bindings for OpenCL 1.0 (rev 48), OpenCL 1.1 (rev 33), + * OpenCL 1.2 (rev 15), OpenCL 2.0 (rev 29) and OpenCL 2.1 (rev 17). + * \author Lee Howes and Bruce Merry + * + * Derived from the OpenCL 1.x C++ bindings written by + * Benedict R. Gaster, Laurent Morichetti and Lee Howes + * With additions and fixes from: + * Brian Cole, March 3rd 2010 and April 2012 + * Matt Gruenke, April 2012. + * Bruce Merry, February 2013. + * Tom Deakin and Simon McIntosh-Smith, July 2013 + * James Price, 2015- + * \version 2.1.0 + * \date 2018-12-07 + * + * Optional extension support + * + * cl_ext_device_fission + * #define CL_HPP_USE_CL_DEVICE_FISSION + * cl_khr_d3d10_sharing + * #define CL_HPP_USE_DX_INTEROP + * cl_khr_sub_groups + * #define CL_HPP_USE_CL_SUB_GROUPS_KHR + * cl_khr_image2d_from_buffer + * #define CL_HPP_USE_CL_IMAGE2D_FROM_BUFFER_KHR + * + * Doxygen documentation for this header is available here: + * + * http://khronosgroup.github.io/OpenCL-CLHPP/ + * + * The latest version of this header can be found on the GitHub releases page: + * + * https://github.com/KhronosGroup/OpenCL-CLHPP/releases + * + * Bugs and patches can be submitted to the GitHub repository: + * + * https://github.com/KhronosGroup/OpenCL-CLHPP + */ + +/*! \mainpage + * \section intro Introduction + * For many large applications C++ is the language of choice and so it seems + * reasonable to define C++ bindings for OpenCL. + * + * The interface is contained with a single C++ header file \em cl2.hpp and all + * definitions are contained within the namespace \em cl. There is no additional + * requirement to include \em cl.h and to use either the C++ or original C + * bindings; it is enough to simply include \em cl2.hpp. + * + * The bindings themselves are lightweight and correspond closely to the + * underlying C API. Using the C++ bindings introduces no additional execution + * overhead. + * + * There are numerous compatibility, portability and memory management + * fixes in the new header as well as additional OpenCL 2.0 features. + * As a result the header is not directly backward compatible and for this + * reason we release it as cl2.hpp rather than a new version of cl.hpp. + * + * + * \section compatibility Compatibility + * Due to the evolution of the underlying OpenCL API the 2.0 C++ bindings + * include an updated approach to defining supported feature versions + * and the range of valid underlying OpenCL runtime versions supported. + * + * The combination of preprocessor macros CL_HPP_TARGET_OPENCL_VERSION and + * CL_HPP_MINIMUM_OPENCL_VERSION control this range. These are three digit + * decimal values representing OpenCL runime versions. The default for + * the target is 200, representing OpenCL 2.0 and the minimum is also + * defined as 200. These settings would use 2.0 API calls only. + * If backward compatibility with a 1.2 runtime is required, the minimum + * version may be set to 120. + * + * Note that this is a compile-time setting, and so affects linking against + * a particular SDK version rather than the versioning of the loaded runtime. + * + * The earlier versions of the header included basic vector and string + * classes based loosely on STL versions. These were difficult to + * maintain and very rarely used. For the 2.0 header we now assume + * the presence of the standard library unless requested otherwise. + * We use std::array, std::vector, std::shared_ptr and std::string + * throughout to safely manage memory and reduce the chance of a + * recurrance of earlier memory management bugs. + * + * These classes are used through typedefs in the cl namespace: + * cl::array, cl::vector, cl::pointer and cl::string. + * In addition cl::allocate_pointer forwards to std::allocate_shared + * by default. + * In all cases these standard library classes can be replaced with + * custom interface-compatible versions using the CL_HPP_NO_STD_ARRAY, + * CL_HPP_NO_STD_VECTOR, CL_HPP_NO_STD_UNIQUE_PTR and + * CL_HPP_NO_STD_STRING macros. + * + * The OpenCL 1.x versions of the C++ bindings included a size_t wrapper + * class to interface with kernel enqueue. This caused unpleasant interactions + * with the standard size_t declaration and led to namespacing bugs. + * In the 2.0 version we have replaced this with a std::array-based interface. + * However, the old behaviour can be regained for backward compatibility + * using the CL_HPP_ENABLE_SIZE_T_COMPATIBILITY macro. + * + * Finally, the program construction interface used a clumsy vector-of-pairs + * design in the earlier versions. We have replaced that with a cleaner + * vector-of-vectors and vector-of-strings design. However, for backward + * compatibility old behaviour can be regained with the + * CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY macro. + * + * In OpenCL 2.0 OpenCL C is not entirely backward compatibility with + * earlier versions. As a result a flag must be passed to the OpenCL C + * compiled to request OpenCL 2.0 compilation of kernels with 1.2 as + * the default in the absence of the flag. + * In some cases the C++ bindings automatically compile code for ease. + * For those cases the compilation defaults to OpenCL C 2.0. + * If this is not wanted, the CL_HPP_CL_1_2_DEFAULT_BUILD macro may + * be specified to assume 1.2 compilation. + * If more fine-grained decisions on a per-kernel bases are required + * then explicit build operations that take the flag should be used. + * + * + * \section parameterization Parameters + * This header may be parameterized by a set of preprocessor macros. + * + * - CL_HPP_TARGET_OPENCL_VERSION + * + * Defines the target OpenCL runtime version to build the header + * against. Defaults to 200, representing OpenCL 2.0. + * + * - CL_HPP_NO_STD_STRING + * + * Do not use the standard library string class. cl::string is not + * defined and may be defined by the user before cl2.hpp is + * included. + * + * - CL_HPP_NO_STD_VECTOR + * + * Do not use the standard library vector class. cl::vector is not + * defined and may be defined by the user before cl2.hpp is + * included. + * + * - CL_HPP_NO_STD_ARRAY + * + * Do not use the standard library array class. cl::array is not + * defined and may be defined by the user before cl2.hpp is + * included. + * + * - CL_HPP_NO_STD_UNIQUE_PTR + * + * Do not use the standard library unique_ptr class. cl::pointer and + * the cl::allocate_pointer functions are not defined and may be + * defined by the user before cl2.hpp is included. + * + * - CL_HPP_ENABLE_DEVICE_FISSION + * + * Enables device fission for OpenCL 1.2 platforms. + * + * - CL_HPP_ENABLE_EXCEPTIONS + * + * Enable exceptions for use in the C++ bindings header. This is the + * preferred error handling mechanism but is not required. + * + * - CL_HPP_ENABLE_SIZE_T_COMPATIBILITY + * + * Backward compatibility option to support cl.hpp-style size_t + * class. Replaces the updated std::array derived version and + * removal of size_t from the namespace. Note that in this case the + * new size_t class is placed in the cl::compatibility namespace and + * thus requires an additional using declaration for direct backward + * compatibility. + * + * - CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY + * + * Enable older vector of pairs interface for construction of + * programs. + * + * - CL_HPP_CL_1_2_DEFAULT_BUILD + * + * Default to OpenCL C 1.2 compilation rather than OpenCL C 2.0 + * applies to use of cl::Program construction and other program + * build variants. + * + * - CL_HPP_USE_CL_SUB_GROUPS_KHR + * + * Enable the cl_khr_subgroups extension. + * + * - CL_HPP_USE_IL_KHR + * + * Enable the cl_khr_il_program extension. + * + * + * \section example Example + * + * The following example shows a general use case for the C++ + * bindings, including support for the optional exception feature and + * also the supplied vector and string classes, see following sections for + * decriptions of these features. + * + * \code + #define CL_HPP_ENABLE_EXCEPTIONS + #define CL_HPP_TARGET_OPENCL_VERSION 200 + + #include + #include + #include + #include + #include + + const int numElements = 32; + + int main(void) + { + // Filter for a 2.0 platform and set it as the default + std::vector platforms; + cl::Platform::get(&platforms); + cl::Platform plat; + for (auto &p : platforms) { + std::string platver = p.getInfo(); + if (platver.find("OpenCL 2.") != std::string::npos) { + plat = p; + } + } + if (plat() == 0) { + std::cout << "No OpenCL 2.0 platform found."; + return -1; + } + + cl::Platform newP = cl::Platform::setDefault(plat); + if (newP != plat) { + std::cout << "Error setting default platform."; + return -1; + } + + // Use C++11 raw string literals for kernel source code + std::string kernel1{R"CLC( + global int globalA; + kernel void updateGlobal() + { + globalA = 75; + } + )CLC"}; + std::string kernel2{R"CLC( + typedef struct { global int *bar; } Foo; + kernel void vectorAdd(global const Foo* aNum, global const int *inputA, global const int *inputB, + global int *output, int val, write_only pipe int outPipe, queue_t childQueue) + { + output[get_global_id(0)] = inputA[get_global_id(0)] + inputB[get_global_id(0)] + val + *(aNum->bar); + write_pipe(outPipe, &val); + queue_t default_queue = get_default_queue(); + ndrange_t ndrange = ndrange_1D(get_global_size(0)/2, get_global_size(0)/2); + + // Have a child kernel write into third quarter of output + enqueue_kernel(default_queue, CLK_ENQUEUE_FLAGS_WAIT_KERNEL, ndrange, + ^{ + output[get_global_size(0)*2 + get_global_id(0)] = + inputA[get_global_size(0)*2 + get_global_id(0)] + inputB[get_global_size(0)*2 + get_global_id(0)] + globalA; + }); + + // Have a child kernel write into last quarter of output + enqueue_kernel(childQueue, CLK_ENQUEUE_FLAGS_WAIT_KERNEL, ndrange, + ^{ + output[get_global_size(0)*3 + get_global_id(0)] = + inputA[get_global_size(0)*3 + get_global_id(0)] + inputB[get_global_size(0)*3 + get_global_id(0)] + globalA + 2; + }); + } + )CLC"}; + + // New simpler string interface style + std::vector programStrings {kernel1, kernel2}; + + cl::Program vectorAddProgram(programStrings); + try { + vectorAddProgram.build("-cl-std=CL2.0"); + } + catch (...) { + // Print build info for all devices + cl_int buildErr = CL_SUCCESS; + auto buildInfo = vectorAddProgram.getBuildInfo(&buildErr); + for (auto &pair : buildInfo) { + std::cerr << pair.second << std::endl << std::endl; + } + + return 1; + } + + typedef struct { int *bar; } Foo; + + // Get and run kernel that initializes the program-scope global + // A test for kernels that take no arguments + auto program2Kernel = + cl::KernelFunctor<>(vectorAddProgram, "updateGlobal"); + program2Kernel( + cl::EnqueueArgs( + cl::NDRange(1))); + + ////////////////// + // SVM allocations + + auto anSVMInt = cl::allocate_svm>(); + *anSVMInt = 5; + cl::SVMAllocator>> svmAllocReadOnly; + auto fooPointer = cl::allocate_pointer(svmAllocReadOnly); + fooPointer->bar = anSVMInt.get(); + cl::SVMAllocator> svmAlloc; + std::vector>> inputA(numElements, 1, svmAlloc); + cl::coarse_svm_vector inputB(numElements, 2, svmAlloc); + + // + ////////////// + + // Traditional cl_mem allocations + std::vector output(numElements, 0xdeadbeef); + cl::Buffer outputBuffer(begin(output), end(output), false); + cl::Pipe aPipe(sizeof(cl_int), numElements / 2); + + // Default command queue, also passed in as a parameter + cl::DeviceCommandQueue defaultDeviceQueue = cl::DeviceCommandQueue::makeDefault( + cl::Context::getDefault(), cl::Device::getDefault()); + + auto vectorAddKernel = + cl::KernelFunctor< + decltype(fooPointer)&, + int*, + cl::coarse_svm_vector&, + cl::Buffer, + int, + cl::Pipe&, + cl::DeviceCommandQueue + >(vectorAddProgram, "vectorAdd"); + + // Ensure that the additional SVM pointer is available to the kernel + // This one was not passed as a parameter + vectorAddKernel.setSVMPointers(anSVMInt); + + // Hand control of coarse allocations to runtime + cl::enqueueUnmapSVM(anSVMInt); + cl::enqueueUnmapSVM(fooPointer); + cl::unmapSVM(inputB); + cl::unmapSVM(output2); + + cl_int error; + vectorAddKernel( + cl::EnqueueArgs( + cl::NDRange(numElements/2), + cl::NDRange(numElements/2)), + fooPointer, + inputA.data(), + inputB, + outputBuffer, + 3, + aPipe, + defaultDeviceQueue, + error + ); + + cl::copy(outputBuffer, begin(output), end(output)); + // Grab the SVM output vector using a map + cl::mapSVM(output2); + + cl::Device d = cl::Device::getDefault(); + + std::cout << "Output:\n"; + for (int i = 1; i < numElements; ++i) { + std::cout << "\t" << output[i] << "\n"; + } + std::cout << "\n\n"; + + return 0; + } + * + * \endcode + * + */ +#ifndef CL_HPP_ +#define CL_HPP_ + +/* Handle deprecated preprocessor definitions. In each case, we only check for + * the old name if the new name is not defined, so that user code can define + * both and hence work with either version of the bindings. + */ +#if !defined(CL_HPP_USE_DX_INTEROP) && defined(USE_DX_INTEROP) +# pragma message("cl2.hpp: USE_DX_INTEROP is deprecated. Define CL_HPP_USE_DX_INTEROP instead") +# define CL_HPP_USE_DX_INTEROP +#endif +#if !defined(CL_HPP_USE_CL_DEVICE_FISSION) && defined(USE_CL_DEVICE_FISSION) +# pragma message("cl2.hpp: USE_CL_DEVICE_FISSION is deprecated. Define CL_HPP_USE_CL_DEVICE_FISSION instead") +# define CL_HPP_USE_CL_DEVICE_FISSION +#endif +#if !defined(CL_HPP_ENABLE_EXCEPTIONS) && defined(__CL_ENABLE_EXCEPTIONS) +# pragma message("cl2.hpp: __CL_ENABLE_EXCEPTIONS is deprecated. Define CL_HPP_ENABLE_EXCEPTIONS instead") +# define CL_HPP_ENABLE_EXCEPTIONS +#endif +#if !defined(CL_HPP_NO_STD_VECTOR) && defined(__NO_STD_VECTOR) +# pragma message("cl2.hpp: __NO_STD_VECTOR is deprecated. Define CL_HPP_NO_STD_VECTOR instead") +# define CL_HPP_NO_STD_VECTOR +#endif +#if !defined(CL_HPP_NO_STD_STRING) && defined(__NO_STD_STRING) +# pragma message("cl2.hpp: __NO_STD_STRING is deprecated. Define CL_HPP_NO_STD_STRING instead") +# define CL_HPP_NO_STD_STRING +#endif +#if defined(VECTOR_CLASS) +# pragma message("cl2.hpp: VECTOR_CLASS is deprecated. Alias cl::vector instead") +#endif +#if defined(STRING_CLASS) +# pragma message("cl2.hpp: STRING_CLASS is deprecated. Alias cl::string instead.") +#endif +#if !defined(CL_HPP_USER_OVERRIDE_ERROR_STRINGS) && defined(__CL_USER_OVERRIDE_ERROR_STRINGS) +# pragma message("cl2.hpp: __CL_USER_OVERRIDE_ERROR_STRINGS is deprecated. Define CL_HPP_USER_OVERRIDE_ERROR_STRINGS instead") +# define CL_HPP_USER_OVERRIDE_ERROR_STRINGS +#endif + +/* Warn about features that are no longer supported + */ +#if defined(__USE_DEV_VECTOR) +# pragma message("cl2.hpp: __USE_DEV_VECTOR is no longer supported. Expect compilation errors") +#endif +#if defined(__USE_DEV_STRING) +# pragma message("cl2.hpp: __USE_DEV_STRING is no longer supported. Expect compilation errors") +#endif + +/* Detect which version to target */ +#if !defined(CL_HPP_TARGET_OPENCL_VERSION) +# pragma message("cl2.hpp: CL_HPP_TARGET_OPENCL_VERSION is not defined. It will default to 210 (OpenCL 2.1)") +# define CL_HPP_TARGET_OPENCL_VERSION 210 +#endif +#if CL_HPP_TARGET_OPENCL_VERSION != 100 && CL_HPP_TARGET_OPENCL_VERSION != 110 && CL_HPP_TARGET_OPENCL_VERSION != 120 && CL_HPP_TARGET_OPENCL_VERSION != 200 && CL_HPP_TARGET_OPENCL_VERSION != 210 +# pragma message("cl2.hpp: CL_HPP_TARGET_OPENCL_VERSION is not a valid value (100, 110, 120, 200 or 210). It will be set to 210") +# undef CL_HPP_TARGET_OPENCL_VERSION +# define CL_HPP_TARGET_OPENCL_VERSION 210 +#endif + +/* Forward target OpenCL version to C headers if necessary */ +#if defined(CL_TARGET_OPENCL_VERSION) +/* Warn if prior definition of CL_TARGET_OPENCL_VERSION is lower than + * requested C++ bindings version */ +#if CL_TARGET_OPENCL_VERSION < CL_HPP_TARGET_OPENCL_VERSION +# pragma message("CL_TARGET_OPENCL_VERSION is already defined as is lower than CL_HPP_TARGET_OPENCL_VERSION") +#endif +#else +# define CL_TARGET_OPENCL_VERSION CL_HPP_TARGET_OPENCL_VERSION +#endif + +#if !defined(CL_HPP_MINIMUM_OPENCL_VERSION) +# define CL_HPP_MINIMUM_OPENCL_VERSION 200 +#endif +#if CL_HPP_MINIMUM_OPENCL_VERSION != 100 && CL_HPP_MINIMUM_OPENCL_VERSION != 110 && CL_HPP_MINIMUM_OPENCL_VERSION != 120 && CL_HPP_MINIMUM_OPENCL_VERSION != 200 && CL_HPP_MINIMUM_OPENCL_VERSION != 210 +# pragma message("cl2.hpp: CL_HPP_MINIMUM_OPENCL_VERSION is not a valid value (100, 110, 120, 200 or 210). It will be set to 100") +# undef CL_HPP_MINIMUM_OPENCL_VERSION +# define CL_HPP_MINIMUM_OPENCL_VERSION 100 +#endif +#if CL_HPP_MINIMUM_OPENCL_VERSION > CL_HPP_TARGET_OPENCL_VERSION +# error "CL_HPP_MINIMUM_OPENCL_VERSION must not be greater than CL_HPP_TARGET_OPENCL_VERSION" +#endif + +#if CL_HPP_MINIMUM_OPENCL_VERSION <= 100 && !defined(CL_USE_DEPRECATED_OPENCL_1_0_APIS) +# define CL_USE_DEPRECATED_OPENCL_1_0_APIS +#endif +#if CL_HPP_MINIMUM_OPENCL_VERSION <= 110 && !defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +# define CL_USE_DEPRECATED_OPENCL_1_1_APIS +#endif +#if CL_HPP_MINIMUM_OPENCL_VERSION <= 120 && !defined(CL_USE_DEPRECATED_OPENCL_1_2_APIS) +# define CL_USE_DEPRECATED_OPENCL_1_2_APIS +#endif +#if CL_HPP_MINIMUM_OPENCL_VERSION <= 200 && !defined(CL_USE_DEPRECATED_OPENCL_2_0_APIS) +# define CL_USE_DEPRECATED_OPENCL_2_0_APIS +#endif +#if CL_HPP_MINIMUM_OPENCL_VERSION <= 210 && !defined(CL_USE_DEPRECATED_OPENCL_2_1_APIS) +# define CL_USE_DEPRECATED_OPENCL_2_1_APIS +#endif + +#ifdef _WIN32 + +#include + +#if defined(CL_HPP_USE_DX_INTEROP) +#include +#include +#endif +#endif // _WIN32 + +#if defined(_MSC_VER) +#include +#endif // _MSC_VER + + // Check for a valid C++ version + +// Need to do both tests here because for some reason __cplusplus is not +// updated in visual studio +#if (!defined(_MSC_VER) && __cplusplus < 201103L) || (defined(_MSC_VER) && _MSC_VER < 1700) +#error Visual studio 2013 or another C++11-supporting compiler required +#endif + +// +#if defined(CL_HPP_USE_CL_DEVICE_FISSION) || defined(CL_HPP_USE_CL_SUB_GROUPS_KHR) +#include +#endif + +#if defined(__APPLE__) || defined(__MACOSX) +#include +#else +#include +#endif // !__APPLE__ + +#if (__cplusplus >= 201103L) +#define CL_HPP_NOEXCEPT_ noexcept +#else +#define CL_HPP_NOEXCEPT_ +#endif + +#if defined(_MSC_VER) +# define CL_HPP_DEFINE_STATIC_MEMBER_ __declspec(selectany) +#else +# define CL_HPP_DEFINE_STATIC_MEMBER_ +#endif // !_MSC_VER + +// Define deprecated prefixes and suffixes to ensure compilation +// in case they are not pre-defined +#if !defined(CL_EXT_PREFIX__VERSION_1_1_DEPRECATED) +#define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED +#endif // #if !defined(CL_EXT_PREFIX__VERSION_1_1_DEPRECATED) +#if !defined(CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED) +#define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED +#endif // #if !defined(CL_EXT_PREFIX__VERSION_1_1_DEPRECATED) + +#if !defined(CL_EXT_PREFIX__VERSION_1_2_DEPRECATED) +#define CL_EXT_PREFIX__VERSION_1_2_DEPRECATED +#endif // #if !defined(CL_EXT_PREFIX__VERSION_1_2_DEPRECATED) +#if !defined(CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED) +#define CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED +#endif // #if !defined(CL_EXT_PREFIX__VERSION_1_2_DEPRECATED) + +#if !defined(CL_CALLBACK) +#define CL_CALLBACK +#endif //CL_CALLBACK + +#include +#include +#include +#include +#include +#include + + +// Define a size_type to represent a correctly resolved size_t +#if defined(CL_HPP_ENABLE_SIZE_T_COMPATIBILITY) +namespace cl { + using size_type = ::size_t; +} // namespace cl +#else // #if defined(CL_HPP_ENABLE_SIZE_T_COMPATIBILITY) +namespace cl { + using size_type = size_t; +} // namespace cl +#endif // #if defined(CL_HPP_ENABLE_SIZE_T_COMPATIBILITY) + + +#if defined(CL_HPP_ENABLE_EXCEPTIONS) +#include +#endif // #if defined(CL_HPP_ENABLE_EXCEPTIONS) + +#if !defined(CL_HPP_NO_STD_VECTOR) +#include +namespace cl { + template < class T, class Alloc = std::allocator > + using vector = std::vector; +} // namespace cl +#endif // #if !defined(CL_HPP_NO_STD_VECTOR) + +#if !defined(CL_HPP_NO_STD_STRING) +#include +namespace cl { + using string = std::string; +} // namespace cl +#endif // #if !defined(CL_HPP_NO_STD_STRING) + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + +#if !defined(CL_HPP_NO_STD_UNIQUE_PTR) +#include +namespace cl { + // Replace unique_ptr and allocate_pointer for internal use + // to allow user to replace them + template + using pointer = std::unique_ptr; +} // namespace cl +#endif +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 +#if !defined(CL_HPP_NO_STD_ARRAY) +#include +namespace cl { + template < class T, size_type N > + using array = std::array; +} // namespace cl +#endif // #if !defined(CL_HPP_NO_STD_ARRAY) + +// Define size_type appropriately to allow backward-compatibility +// use of the old size_t interface class +#if defined(CL_HPP_ENABLE_SIZE_T_COMPATIBILITY) +namespace cl { + namespace compatibility { + /*! \brief class used to interface between C++ and + * OpenCL C calls that require arrays of size_t values, whose + * size is known statically. + */ + template + class size_t + { + private: + size_type data_[N]; + + public: + //! \brief Initialize size_t to all 0s + size_t() + { + for (int i = 0; i < N; ++i) { + data_[i] = 0; + } + } + + size_t(const array &rhs) + { + for (int i = 0; i < N; ++i) { + data_[i] = rhs[i]; + } + } + + size_type& operator[](int index) + { + return data_[index]; + } + + const size_type& operator[](int index) const + { + return data_[index]; + } + + //! \brief Conversion operator to T*. + operator size_type* () { return data_; } + + //! \brief Conversion operator to const T*. + operator const size_type* () const { return data_; } + + operator array() const + { + array ret; + + for (int i = 0; i < N; ++i) { + ret[i] = data_[i]; + } + return ret; + } + }; + } // namespace compatibility + + template + using size_t = compatibility::size_t; +} // namespace cl +#endif // #if defined(CL_HPP_ENABLE_SIZE_T_COMPATIBILITY) + +// Helper alias to avoid confusing the macros +namespace cl { + namespace detail { + using size_t_array = array; + } // namespace detail +} // namespace cl + + +/*! \namespace cl + * + * \brief The OpenCL C++ bindings are defined within this namespace. + * + */ +namespace cl { + class Memory; + +#define CL_HPP_INIT_CL_EXT_FCN_PTR_(name) \ + if (!pfn_##name) { \ + pfn_##name = (PFN_##name) \ + clGetExtensionFunctionAddress(#name); \ + if (!pfn_##name) { \ + } \ + } + +#define CL_HPP_INIT_CL_EXT_FCN_PTR_PLATFORM_(platform, name) \ + if (!pfn_##name) { \ + pfn_##name = (PFN_##name) \ + clGetExtensionFunctionAddressForPlatform(platform, #name); \ + if (!pfn_##name) { \ + } \ + } + + class Program; + class Device; + class Context; + class CommandQueue; + class DeviceCommandQueue; + class Memory; + class Buffer; + class Pipe; + +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + /*! \brief Exception class + * + * This may be thrown by API functions when CL_HPP_ENABLE_EXCEPTIONS is defined. + */ + class Error : public std::exception + { + private: + cl_int err_; + const char * errStr_; + public: + /*! \brief Create a new CL error exception for a given error code + * and corresponding message. + * + * \param err error code value. + * + * \param errStr a descriptive string that must remain in scope until + * handling of the exception has concluded. If set, it + * will be returned by what(). + */ + Error(cl_int err, const char * errStr = NULL) : err_(err), errStr_(errStr) + {} + + ~Error() throw() {} + + /*! \brief Get error string associated with exception + * + * \return A memory pointer to the error message string. + */ + virtual const char * what() const throw () + { + if (errStr_ == NULL) { + return "empty"; + } + else { + return errStr_; + } + } + + /*! \brief Get error code associated with exception + * + * \return The error code. + */ + cl_int err(void) const { return err_; } + }; +#define CL_HPP_ERR_STR_(x) #x +#else +#define CL_HPP_ERR_STR_(x) NULL +#endif // CL_HPP_ENABLE_EXCEPTIONS + + +namespace detail +{ +#if defined(CL_HPP_ENABLE_EXCEPTIONS) +static inline cl_int errHandler ( + cl_int err, + const char * errStr = NULL) +{ + if (err != CL_SUCCESS) { + throw Error(err, errStr); + } + return err; +} +#else +static inline cl_int errHandler (cl_int err, const char * errStr = NULL) +{ + (void) errStr; // suppress unused variable warning + return err; +} +#endif // CL_HPP_ENABLE_EXCEPTIONS +} + + + +//! \cond DOXYGEN_DETAIL +#if !defined(CL_HPP_USER_OVERRIDE_ERROR_STRINGS) +#define __GET_DEVICE_INFO_ERR CL_HPP_ERR_STR_(clGetDeviceInfo) +#define __GET_PLATFORM_INFO_ERR CL_HPP_ERR_STR_(clGetPlatformInfo) +#define __GET_DEVICE_IDS_ERR CL_HPP_ERR_STR_(clGetDeviceIDs) +#define __GET_PLATFORM_IDS_ERR CL_HPP_ERR_STR_(clGetPlatformIDs) +#define __GET_CONTEXT_INFO_ERR CL_HPP_ERR_STR_(clGetContextInfo) +#define __GET_EVENT_INFO_ERR CL_HPP_ERR_STR_(clGetEventInfo) +#define __GET_EVENT_PROFILE_INFO_ERR CL_HPP_ERR_STR_(clGetEventProfileInfo) +#define __GET_MEM_OBJECT_INFO_ERR CL_HPP_ERR_STR_(clGetMemObjectInfo) +#define __GET_IMAGE_INFO_ERR CL_HPP_ERR_STR_(clGetImageInfo) +#define __GET_SAMPLER_INFO_ERR CL_HPP_ERR_STR_(clGetSamplerInfo) +#define __GET_KERNEL_INFO_ERR CL_HPP_ERR_STR_(clGetKernelInfo) +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __GET_KERNEL_ARG_INFO_ERR CL_HPP_ERR_STR_(clGetKernelArgInfo) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +#define __GET_KERNEL_SUB_GROUP_INFO_ERR CL_HPP_ERR_STR_(clGetKernelSubGroupInfo) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#define __GET_KERNEL_WORK_GROUP_INFO_ERR CL_HPP_ERR_STR_(clGetKernelWorkGroupInfo) +#define __GET_PROGRAM_INFO_ERR CL_HPP_ERR_STR_(clGetProgramInfo) +#define __GET_PROGRAM_BUILD_INFO_ERR CL_HPP_ERR_STR_(clGetProgramBuildInfo) +#define __GET_COMMAND_QUEUE_INFO_ERR CL_HPP_ERR_STR_(clGetCommandQueueInfo) + +#define __CREATE_CONTEXT_ERR CL_HPP_ERR_STR_(clCreateContext) +#define __CREATE_CONTEXT_FROM_TYPE_ERR CL_HPP_ERR_STR_(clCreateContextFromType) +#define __GET_SUPPORTED_IMAGE_FORMATS_ERR CL_HPP_ERR_STR_(clGetSupportedImageFormats) + +#define __CREATE_BUFFER_ERR CL_HPP_ERR_STR_(clCreateBuffer) +#define __COPY_ERR CL_HPP_ERR_STR_(cl::copy) +#define __CREATE_SUBBUFFER_ERR CL_HPP_ERR_STR_(clCreateSubBuffer) +#define __CREATE_GL_BUFFER_ERR CL_HPP_ERR_STR_(clCreateFromGLBuffer) +#define __CREATE_GL_RENDER_BUFFER_ERR CL_HPP_ERR_STR_(clCreateFromGLBuffer) +#define __GET_GL_OBJECT_INFO_ERR CL_HPP_ERR_STR_(clGetGLObjectInfo) +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __CREATE_IMAGE_ERR CL_HPP_ERR_STR_(clCreateImage) +#define __CREATE_GL_TEXTURE_ERR CL_HPP_ERR_STR_(clCreateFromGLTexture) +#define __IMAGE_DIMENSION_ERR CL_HPP_ERR_STR_(Incorrect image dimensions) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __SET_MEM_OBJECT_DESTRUCTOR_CALLBACK_ERR CL_HPP_ERR_STR_(clSetMemObjectDestructorCallback) + +#define __CREATE_USER_EVENT_ERR CL_HPP_ERR_STR_(clCreateUserEvent) +#define __SET_USER_EVENT_STATUS_ERR CL_HPP_ERR_STR_(clSetUserEventStatus) +#define __SET_EVENT_CALLBACK_ERR CL_HPP_ERR_STR_(clSetEventCallback) +#define __WAIT_FOR_EVENTS_ERR CL_HPP_ERR_STR_(clWaitForEvents) + +#define __CREATE_KERNEL_ERR CL_HPP_ERR_STR_(clCreateKernel) +#define __SET_KERNEL_ARGS_ERR CL_HPP_ERR_STR_(clSetKernelArg) +#define __CREATE_PROGRAM_WITH_SOURCE_ERR CL_HPP_ERR_STR_(clCreateProgramWithSource) +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +#define __CREATE_PROGRAM_WITH_IL_ERR CL_HPP_ERR_STR_(clCreateProgramWithIL) +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 +#define __CREATE_PROGRAM_WITH_BINARY_ERR CL_HPP_ERR_STR_(clCreateProgramWithBinary) +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 +#define __CREATE_PROGRAM_WITH_IL_ERR CL_HPP_ERR_STR_(clCreateProgramWithIL) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 210 +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __CREATE_PROGRAM_WITH_BUILT_IN_KERNELS_ERR CL_HPP_ERR_STR_(clCreateProgramWithBuiltInKernels) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __BUILD_PROGRAM_ERR CL_HPP_ERR_STR_(clBuildProgram) +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __COMPILE_PROGRAM_ERR CL_HPP_ERR_STR_(clCompileProgram) +#define __LINK_PROGRAM_ERR CL_HPP_ERR_STR_(clLinkProgram) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __CREATE_KERNELS_IN_PROGRAM_ERR CL_HPP_ERR_STR_(clCreateKernelsInProgram) + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +#define __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR CL_HPP_ERR_STR_(clCreateCommandQueueWithProperties) +#define __CREATE_SAMPLER_WITH_PROPERTIES_ERR CL_HPP_ERR_STR_(clCreateSamplerWithProperties) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#define __SET_COMMAND_QUEUE_PROPERTY_ERR CL_HPP_ERR_STR_(clSetCommandQueueProperty) +#define __ENQUEUE_READ_BUFFER_ERR CL_HPP_ERR_STR_(clEnqueueReadBuffer) +#define __ENQUEUE_READ_BUFFER_RECT_ERR CL_HPP_ERR_STR_(clEnqueueReadBufferRect) +#define __ENQUEUE_WRITE_BUFFER_ERR CL_HPP_ERR_STR_(clEnqueueWriteBuffer) +#define __ENQUEUE_WRITE_BUFFER_RECT_ERR CL_HPP_ERR_STR_(clEnqueueWriteBufferRect) +#define __ENQEUE_COPY_BUFFER_ERR CL_HPP_ERR_STR_(clEnqueueCopyBuffer) +#define __ENQEUE_COPY_BUFFER_RECT_ERR CL_HPP_ERR_STR_(clEnqueueCopyBufferRect) +#define __ENQUEUE_FILL_BUFFER_ERR CL_HPP_ERR_STR_(clEnqueueFillBuffer) +#define __ENQUEUE_READ_IMAGE_ERR CL_HPP_ERR_STR_(clEnqueueReadImage) +#define __ENQUEUE_WRITE_IMAGE_ERR CL_HPP_ERR_STR_(clEnqueueWriteImage) +#define __ENQUEUE_COPY_IMAGE_ERR CL_HPP_ERR_STR_(clEnqueueCopyImage) +#define __ENQUEUE_FILL_IMAGE_ERR CL_HPP_ERR_STR_(clEnqueueFillImage) +#define __ENQUEUE_COPY_IMAGE_TO_BUFFER_ERR CL_HPP_ERR_STR_(clEnqueueCopyImageToBuffer) +#define __ENQUEUE_COPY_BUFFER_TO_IMAGE_ERR CL_HPP_ERR_STR_(clEnqueueCopyBufferToImage) +#define __ENQUEUE_MAP_BUFFER_ERR CL_HPP_ERR_STR_(clEnqueueMapBuffer) +#define __ENQUEUE_MAP_IMAGE_ERR CL_HPP_ERR_STR_(clEnqueueMapImage) +#define __ENQUEUE_UNMAP_MEM_OBJECT_ERR CL_HPP_ERR_STR_(clEnqueueUnMapMemObject) +#define __ENQUEUE_NDRANGE_KERNEL_ERR CL_HPP_ERR_STR_(clEnqueueNDRangeKernel) +#define __ENQUEUE_NATIVE_KERNEL CL_HPP_ERR_STR_(clEnqueueNativeKernel) +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __ENQUEUE_MIGRATE_MEM_OBJECTS_ERR CL_HPP_ERR_STR_(clEnqueueMigrateMemObjects) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 +#define __ENQUEUE_MIGRATE_SVM_ERR CL_HPP_ERR_STR_(clEnqueueSVMMigrateMem) +#define __SET_DEFAULT_DEVICE_COMMAND_QUEUE_ERR CL_HPP_ERR_STR_(clSetDefaultDeviceCommandQueue) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 210 + + +#define __ENQUEUE_ACQUIRE_GL_ERR CL_HPP_ERR_STR_(clEnqueueAcquireGLObjects) +#define __ENQUEUE_RELEASE_GL_ERR CL_HPP_ERR_STR_(clEnqueueReleaseGLObjects) + +#define __CREATE_PIPE_ERR CL_HPP_ERR_STR_(clCreatePipe) +#define __GET_PIPE_INFO_ERR CL_HPP_ERR_STR_(clGetPipeInfo) + + +#define __RETAIN_ERR CL_HPP_ERR_STR_(Retain Object) +#define __RELEASE_ERR CL_HPP_ERR_STR_(Release Object) +#define __FLUSH_ERR CL_HPP_ERR_STR_(clFlush) +#define __FINISH_ERR CL_HPP_ERR_STR_(clFinish) +#define __VECTOR_CAPACITY_ERR CL_HPP_ERR_STR_(Vector capacity error) + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 +#define __GET_HOST_TIMER_ERR CL_HPP_ERR_STR_(clGetHostTimer) +#define __GET_DEVICE_AND_HOST_TIMER_ERR CL_HPP_ERR_STR_(clGetDeviceAndHostTimer) +#endif + + +/** + * CL 1.2 version that uses device fission. + */ +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __CREATE_SUB_DEVICES_ERR CL_HPP_ERR_STR_(clCreateSubDevices) +#else +#define __CREATE_SUB_DEVICES_ERR CL_HPP_ERR_STR_(clCreateSubDevicesEXT) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +#define __ENQUEUE_MARKER_ERR CL_HPP_ERR_STR_(clEnqueueMarker) +#define __ENQUEUE_WAIT_FOR_EVENTS_ERR CL_HPP_ERR_STR_(clEnqueueWaitForEvents) +#define __ENQUEUE_BARRIER_ERR CL_HPP_ERR_STR_(clEnqueueBarrier) +#define __UNLOAD_COMPILER_ERR CL_HPP_ERR_STR_(clUnloadCompiler) +#define __CREATE_GL_TEXTURE_2D_ERR CL_HPP_ERR_STR_(clCreateFromGLTexture2D) +#define __CREATE_GL_TEXTURE_3D_ERR CL_HPP_ERR_STR_(clCreateFromGLTexture3D) +#define __CREATE_IMAGE2D_ERR CL_HPP_ERR_STR_(clCreateImage2D) +#define __CREATE_IMAGE3D_ERR CL_HPP_ERR_STR_(clCreateImage3D) +#endif // #if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + +/** + * Deprecated APIs for 2.0 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_2_APIS) +#define __CREATE_COMMAND_QUEUE_ERR CL_HPP_ERR_STR_(clCreateCommandQueue) +#define __ENQUEUE_TASK_ERR CL_HPP_ERR_STR_(clEnqueueTask) +#define __CREATE_SAMPLER_ERR CL_HPP_ERR_STR_(clCreateSampler) +#endif // #if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + +/** + * CL 1.2 marker and barrier commands + */ +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +#define __ENQUEUE_MARKER_WAIT_LIST_ERR CL_HPP_ERR_STR_(clEnqueueMarkerWithWaitList) +#define __ENQUEUE_BARRIER_WAIT_LIST_ERR CL_HPP_ERR_STR_(clEnqueueBarrierWithWaitList) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 +#define __CLONE_KERNEL_ERR CL_HPP_ERR_STR_(clCloneKernel) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 210 + +#endif // CL_HPP_USER_OVERRIDE_ERROR_STRINGS +//! \endcond + + +namespace detail { + +// Generic getInfoHelper. The final parameter is used to guide overload +// resolution: the actual parameter passed is an int, which makes this +// a worse conversion sequence than a specialization that declares the +// parameter as an int. +template +inline cl_int getInfoHelper(Functor f, cl_uint name, T* param, long) +{ + return f(name, sizeof(T), param, NULL); +} + +// Specialized for getInfo +// Assumes that the output vector was correctly resized on the way in +template +inline cl_int getInfoHelper(Func f, cl_uint name, vector>* param, int) +{ + if (name != CL_PROGRAM_BINARIES) { + return CL_INVALID_VALUE; + } + if (param) { + // Create array of pointers, calculate total size and pass pointer array in + size_type numBinaries = param->size(); + vector binariesPointers(numBinaries); + + for (size_type i = 0; i < numBinaries; ++i) + { + binariesPointers[i] = (*param)[i].data(); + } + + cl_int err = f(name, numBinaries * sizeof(unsigned char*), binariesPointers.data(), NULL); + + if (err != CL_SUCCESS) { + return err; + } + } + + + return CL_SUCCESS; +} + +// Specialized getInfoHelper for vector params +template +inline cl_int getInfoHelper(Func f, cl_uint name, vector* param, long) +{ + size_type required; + cl_int err = f(name, 0, NULL, &required); + if (err != CL_SUCCESS) { + return err; + } + const size_type elements = required / sizeof(T); + + // Temporary to avoid changing param on an error + vector localData(elements); + err = f(name, required, localData.data(), NULL); + if (err != CL_SUCCESS) { + return err; + } + if (param) { + *param = std::move(localData); + } + + return CL_SUCCESS; +} + +/* Specialization for reference-counted types. This depends on the + * existence of Wrapper::cl_type, and none of the other types having the + * cl_type member. Note that simplify specifying the parameter as Wrapper + * does not work, because when using a derived type (e.g. Context) the generic + * template will provide a better match. + */ +template +inline cl_int getInfoHelper( + Func f, cl_uint name, vector* param, int, typename T::cl_type = 0) +{ + size_type required; + cl_int err = f(name, 0, NULL, &required); + if (err != CL_SUCCESS) { + return err; + } + + const size_type elements = required / sizeof(typename T::cl_type); + + vector value(elements); + err = f(name, required, value.data(), NULL); + if (err != CL_SUCCESS) { + return err; + } + + if (param) { + // Assign to convert CL type to T for each element + param->resize(elements); + + // Assign to param, constructing with retain behaviour + // to correctly capture each underlying CL object + for (size_type i = 0; i < elements; i++) { + (*param)[i] = T(value[i], true); + } + } + return CL_SUCCESS; +} + +// Specialized GetInfoHelper for string params +template +inline cl_int getInfoHelper(Func f, cl_uint name, string* param, long) +{ + size_type required; + cl_int err = f(name, 0, NULL, &required); + if (err != CL_SUCCESS) { + return err; + } + + // std::string has a constant data member + // a char vector does not + if (required > 0) { + vector value(required); + err = f(name, required, value.data(), NULL); + if (err != CL_SUCCESS) { + return err; + } + if (param) { + param->assign(begin(value), prev(end(value))); + } + } + else if (param) { + param->assign(""); + } + return CL_SUCCESS; +} + +// Specialized GetInfoHelper for clsize_t params +template +inline cl_int getInfoHelper(Func f, cl_uint name, array* param, long) +{ + size_type required; + cl_int err = f(name, 0, NULL, &required); + if (err != CL_SUCCESS) { + return err; + } + + size_type elements = required / sizeof(size_type); + vector value(elements, 0); + + err = f(name, required, value.data(), NULL); + if (err != CL_SUCCESS) { + return err; + } + + // Bound the copy with N to prevent overruns + // if passed N > than the amount copied + if (elements > N) { + elements = N; + } + for (size_type i = 0; i < elements; ++i) { + (*param)[i] = value[i]; + } + + return CL_SUCCESS; +} + +template struct ReferenceHandler; + +/* Specialization for reference-counted types. This depends on the + * existence of Wrapper::cl_type, and none of the other types having the + * cl_type member. Note that simplify specifying the parameter as Wrapper + * does not work, because when using a derived type (e.g. Context) the generic + * template will provide a better match. + */ +template +inline cl_int getInfoHelper(Func f, cl_uint name, T* param, int, typename T::cl_type = 0) +{ + typename T::cl_type value; + cl_int err = f(name, sizeof(value), &value, NULL); + if (err != CL_SUCCESS) { + return err; + } + *param = value; + if (value != NULL) + { + err = param->retain(); + if (err != CL_SUCCESS) { + return err; + } + } + return CL_SUCCESS; +} + +#define CL_HPP_PARAM_NAME_INFO_1_0_(F) \ + F(cl_platform_info, CL_PLATFORM_PROFILE, string) \ + F(cl_platform_info, CL_PLATFORM_VERSION, string) \ + F(cl_platform_info, CL_PLATFORM_NAME, string) \ + F(cl_platform_info, CL_PLATFORM_VENDOR, string) \ + F(cl_platform_info, CL_PLATFORM_EXTENSIONS, string) \ + \ + F(cl_device_info, CL_DEVICE_TYPE, cl_device_type) \ + F(cl_device_info, CL_DEVICE_VENDOR_ID, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_COMPUTE_UNITS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_WORK_GROUP_SIZE, size_type) \ + F(cl_device_info, CL_DEVICE_MAX_WORK_ITEM_SIZES, cl::vector) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_CLOCK_FREQUENCY, cl_uint) \ + F(cl_device_info, CL_DEVICE_ADDRESS_BITS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_READ_IMAGE_ARGS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_WRITE_IMAGE_ARGS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_MEM_ALLOC_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_IMAGE2D_MAX_WIDTH, size_type) \ + F(cl_device_info, CL_DEVICE_IMAGE2D_MAX_HEIGHT, size_type) \ + F(cl_device_info, CL_DEVICE_IMAGE3D_MAX_WIDTH, size_type) \ + F(cl_device_info, CL_DEVICE_IMAGE3D_MAX_HEIGHT, size_type) \ + F(cl_device_info, CL_DEVICE_IMAGE3D_MAX_DEPTH, size_type) \ + F(cl_device_info, CL_DEVICE_IMAGE_SUPPORT, cl_bool) \ + F(cl_device_info, CL_DEVICE_MAX_PARAMETER_SIZE, size_type) \ + F(cl_device_info, CL_DEVICE_MAX_SAMPLERS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MEM_BASE_ADDR_ALIGN, cl_uint) \ + F(cl_device_info, CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE, cl_uint) \ + F(cl_device_info, CL_DEVICE_SINGLE_FP_CONFIG, cl_device_fp_config) \ + F(cl_device_info, CL_DEVICE_DOUBLE_FP_CONFIG, cl_device_fp_config) \ + F(cl_device_info, CL_DEVICE_HALF_FP_CONFIG, cl_device_fp_config) \ + F(cl_device_info, CL_DEVICE_GLOBAL_MEM_CACHE_TYPE, cl_device_mem_cache_type) \ + F(cl_device_info, CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE, cl_uint)\ + F(cl_device_info, CL_DEVICE_GLOBAL_MEM_CACHE_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_GLOBAL_MEM_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_MAX_CONSTANT_ARGS, cl_uint) \ + F(cl_device_info, CL_DEVICE_LOCAL_MEM_TYPE, cl_device_local_mem_type) \ + F(cl_device_info, CL_DEVICE_LOCAL_MEM_SIZE, cl_ulong) \ + F(cl_device_info, CL_DEVICE_ERROR_CORRECTION_SUPPORT, cl_bool) \ + F(cl_device_info, CL_DEVICE_PROFILING_TIMER_RESOLUTION, size_type) \ + F(cl_device_info, CL_DEVICE_ENDIAN_LITTLE, cl_bool) \ + F(cl_device_info, CL_DEVICE_AVAILABLE, cl_bool) \ + F(cl_device_info, CL_DEVICE_COMPILER_AVAILABLE, cl_bool) \ + F(cl_device_info, CL_DEVICE_EXECUTION_CAPABILITIES, cl_device_exec_capabilities) \ + F(cl_device_info, CL_DEVICE_PLATFORM, cl_platform_id) \ + F(cl_device_info, CL_DEVICE_NAME, string) \ + F(cl_device_info, CL_DEVICE_VENDOR, string) \ + F(cl_device_info, CL_DRIVER_VERSION, string) \ + F(cl_device_info, CL_DEVICE_PROFILE, string) \ + F(cl_device_info, CL_DEVICE_VERSION, string) \ + F(cl_device_info, CL_DEVICE_EXTENSIONS, string) \ + \ + F(cl_context_info, CL_CONTEXT_REFERENCE_COUNT, cl_uint) \ + F(cl_context_info, CL_CONTEXT_DEVICES, cl::vector) \ + F(cl_context_info, CL_CONTEXT_PROPERTIES, cl::vector) \ + \ + F(cl_event_info, CL_EVENT_COMMAND_QUEUE, cl::CommandQueue) \ + F(cl_event_info, CL_EVENT_COMMAND_TYPE, cl_command_type) \ + F(cl_event_info, CL_EVENT_REFERENCE_COUNT, cl_uint) \ + F(cl_event_info, CL_EVENT_COMMAND_EXECUTION_STATUS, cl_int) \ + \ + F(cl_profiling_info, CL_PROFILING_COMMAND_QUEUED, cl_ulong) \ + F(cl_profiling_info, CL_PROFILING_COMMAND_SUBMIT, cl_ulong) \ + F(cl_profiling_info, CL_PROFILING_COMMAND_START, cl_ulong) \ + F(cl_profiling_info, CL_PROFILING_COMMAND_END, cl_ulong) \ + \ + F(cl_mem_info, CL_MEM_TYPE, cl_mem_object_type) \ + F(cl_mem_info, CL_MEM_FLAGS, cl_mem_flags) \ + F(cl_mem_info, CL_MEM_SIZE, size_type) \ + F(cl_mem_info, CL_MEM_HOST_PTR, void*) \ + F(cl_mem_info, CL_MEM_MAP_COUNT, cl_uint) \ + F(cl_mem_info, CL_MEM_REFERENCE_COUNT, cl_uint) \ + F(cl_mem_info, CL_MEM_CONTEXT, cl::Context) \ + \ + F(cl_image_info, CL_IMAGE_FORMAT, cl_image_format) \ + F(cl_image_info, CL_IMAGE_ELEMENT_SIZE, size_type) \ + F(cl_image_info, CL_IMAGE_ROW_PITCH, size_type) \ + F(cl_image_info, CL_IMAGE_SLICE_PITCH, size_type) \ + F(cl_image_info, CL_IMAGE_WIDTH, size_type) \ + F(cl_image_info, CL_IMAGE_HEIGHT, size_type) \ + F(cl_image_info, CL_IMAGE_DEPTH, size_type) \ + \ + F(cl_sampler_info, CL_SAMPLER_REFERENCE_COUNT, cl_uint) \ + F(cl_sampler_info, CL_SAMPLER_CONTEXT, cl::Context) \ + F(cl_sampler_info, CL_SAMPLER_NORMALIZED_COORDS, cl_bool) \ + F(cl_sampler_info, CL_SAMPLER_ADDRESSING_MODE, cl_addressing_mode) \ + F(cl_sampler_info, CL_SAMPLER_FILTER_MODE, cl_filter_mode) \ + \ + F(cl_program_info, CL_PROGRAM_REFERENCE_COUNT, cl_uint) \ + F(cl_program_info, CL_PROGRAM_CONTEXT, cl::Context) \ + F(cl_program_info, CL_PROGRAM_NUM_DEVICES, cl_uint) \ + F(cl_program_info, CL_PROGRAM_DEVICES, cl::vector) \ + F(cl_program_info, CL_PROGRAM_SOURCE, string) \ + F(cl_program_info, CL_PROGRAM_BINARY_SIZES, cl::vector) \ + F(cl_program_info, CL_PROGRAM_BINARIES, cl::vector>) \ + \ + F(cl_program_build_info, CL_PROGRAM_BUILD_STATUS, cl_build_status) \ + F(cl_program_build_info, CL_PROGRAM_BUILD_OPTIONS, string) \ + F(cl_program_build_info, CL_PROGRAM_BUILD_LOG, string) \ + \ + F(cl_kernel_info, CL_KERNEL_FUNCTION_NAME, string) \ + F(cl_kernel_info, CL_KERNEL_NUM_ARGS, cl_uint) \ + F(cl_kernel_info, CL_KERNEL_REFERENCE_COUNT, cl_uint) \ + F(cl_kernel_info, CL_KERNEL_CONTEXT, cl::Context) \ + F(cl_kernel_info, CL_KERNEL_PROGRAM, cl::Program) \ + \ + F(cl_kernel_work_group_info, CL_KERNEL_WORK_GROUP_SIZE, size_type) \ + F(cl_kernel_work_group_info, CL_KERNEL_COMPILE_WORK_GROUP_SIZE, cl::detail::size_t_array) \ + F(cl_kernel_work_group_info, CL_KERNEL_LOCAL_MEM_SIZE, cl_ulong) \ + \ + F(cl_command_queue_info, CL_QUEUE_CONTEXT, cl::Context) \ + F(cl_command_queue_info, CL_QUEUE_DEVICE, cl::Device) \ + F(cl_command_queue_info, CL_QUEUE_REFERENCE_COUNT, cl_uint) \ + F(cl_command_queue_info, CL_QUEUE_PROPERTIES, cl_command_queue_properties) + + +#define CL_HPP_PARAM_NAME_INFO_1_1_(F) \ + F(cl_context_info, CL_CONTEXT_NUM_DEVICES, cl_uint)\ + F(cl_device_info, CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_INT, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE, cl_uint) \ + F(cl_device_info, CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF, cl_uint) \ + F(cl_device_info, CL_DEVICE_OPENCL_C_VERSION, string) \ + \ + F(cl_mem_info, CL_MEM_ASSOCIATED_MEMOBJECT, cl::Memory) \ + F(cl_mem_info, CL_MEM_OFFSET, size_type) \ + \ + F(cl_kernel_work_group_info, CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE, size_type) \ + F(cl_kernel_work_group_info, CL_KERNEL_PRIVATE_MEM_SIZE, cl_ulong) \ + \ + F(cl_event_info, CL_EVENT_CONTEXT, cl::Context) + +#define CL_HPP_PARAM_NAME_INFO_1_2_(F) \ + F(cl_program_info, CL_PROGRAM_NUM_KERNELS, size_type) \ + F(cl_program_info, CL_PROGRAM_KERNEL_NAMES, string) \ + \ + F(cl_program_build_info, CL_PROGRAM_BINARY_TYPE, cl_program_binary_type) \ + \ + F(cl_kernel_info, CL_KERNEL_ATTRIBUTES, string) \ + \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_ADDRESS_QUALIFIER, cl_kernel_arg_address_qualifier) \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_ACCESS_QUALIFIER, cl_kernel_arg_access_qualifier) \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_TYPE_NAME, string) \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_NAME, string) \ + F(cl_kernel_arg_info, CL_KERNEL_ARG_TYPE_QUALIFIER, cl_kernel_arg_type_qualifier) \ + \ + F(cl_device_info, CL_DEVICE_PARENT_DEVICE, cl::Device) \ + F(cl_device_info, CL_DEVICE_PARTITION_PROPERTIES, cl::vector) \ + F(cl_device_info, CL_DEVICE_PARTITION_TYPE, cl::vector) \ + F(cl_device_info, CL_DEVICE_REFERENCE_COUNT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_INTEROP_USER_SYNC, size_type) \ + F(cl_device_info, CL_DEVICE_PARTITION_AFFINITY_DOMAIN, cl_device_affinity_domain) \ + F(cl_device_info, CL_DEVICE_BUILT_IN_KERNELS, string) \ + \ + F(cl_image_info, CL_IMAGE_ARRAY_SIZE, size_type) \ + F(cl_image_info, CL_IMAGE_NUM_MIP_LEVELS, cl_uint) \ + F(cl_image_info, CL_IMAGE_NUM_SAMPLES, cl_uint) + +#define CL_HPP_PARAM_NAME_INFO_2_0_(F) \ + F(cl_device_info, CL_DEVICE_QUEUE_ON_HOST_PROPERTIES, cl_command_queue_properties) \ + F(cl_device_info, CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES, cl_command_queue_properties) \ + F(cl_device_info, CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE, cl_uint) \ + F(cl_device_info, CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_ON_DEVICE_QUEUES, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_ON_DEVICE_EVENTS, cl_uint) \ + F(cl_device_info, CL_DEVICE_MAX_PIPE_ARGS, cl_uint) \ + F(cl_device_info, CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS, cl_uint) \ + F(cl_device_info, CL_DEVICE_PIPE_MAX_PACKET_SIZE, cl_uint) \ + F(cl_device_info, CL_DEVICE_SVM_CAPABILITIES, cl_device_svm_capabilities) \ + F(cl_device_info, CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT, cl_uint) \ + F(cl_device_info, CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT, cl_uint) \ + F(cl_command_queue_info, CL_QUEUE_SIZE, cl_uint) \ + F(cl_mem_info, CL_MEM_USES_SVM_POINTER, cl_bool) \ + F(cl_program_build_info, CL_PROGRAM_BUILD_GLOBAL_VARIABLE_TOTAL_SIZE, size_type) \ + F(cl_pipe_info, CL_PIPE_PACKET_SIZE, cl_uint) \ + F(cl_pipe_info, CL_PIPE_MAX_PACKETS, cl_uint) + +#define CL_HPP_PARAM_NAME_INFO_SUBGROUP_KHR_(F) \ + F(cl_kernel_sub_group_info, CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE_KHR, size_type) \ + F(cl_kernel_sub_group_info, CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE_KHR, size_type) + +#define CL_HPP_PARAM_NAME_INFO_IL_KHR_(F) \ + F(cl_device_info, CL_DEVICE_IL_VERSION_KHR, string) \ + F(cl_program_info, CL_PROGRAM_IL_KHR, cl::vector) + +#define CL_HPP_PARAM_NAME_INFO_2_1_(F) \ + F(cl_platform_info, CL_PLATFORM_HOST_TIMER_RESOLUTION, size_type) \ + F(cl_program_info, CL_PROGRAM_IL, cl::vector) \ + F(cl_kernel_info, CL_KERNEL_MAX_NUM_SUB_GROUPS, size_type) \ + F(cl_kernel_info, CL_KERNEL_COMPILE_NUM_SUB_GROUPS, size_type) \ + F(cl_device_info, CL_DEVICE_MAX_NUM_SUB_GROUPS, cl_uint) \ + F(cl_device_info, CL_DEVICE_IL_VERSION, string) \ + F(cl_device_info, CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS, cl_bool) \ + F(cl_command_queue_info, CL_QUEUE_DEVICE_DEFAULT, cl::DeviceCommandQueue) \ + F(cl_kernel_sub_group_info, CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE, size_type) \ + F(cl_kernel_sub_group_info, CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE, size_type) \ + F(cl_kernel_sub_group_info, CL_KERNEL_LOCAL_SIZE_FOR_SUB_GROUP_COUNT, cl::detail::size_t_array) + +#define CL_HPP_PARAM_NAME_DEVICE_FISSION_(F) \ + F(cl_device_info, CL_DEVICE_PARENT_DEVICE_EXT, cl_device_id) \ + F(cl_device_info, CL_DEVICE_PARTITION_TYPES_EXT, cl::vector) \ + F(cl_device_info, CL_DEVICE_AFFINITY_DOMAINS_EXT, cl::vector) \ + F(cl_device_info, CL_DEVICE_REFERENCE_COUNT_EXT , cl_uint) \ + F(cl_device_info, CL_DEVICE_PARTITION_STYLE_EXT, cl::vector) + +template +struct param_traits {}; + +#define CL_HPP_DECLARE_PARAM_TRAITS_(token, param_name, T) \ +struct token; \ +template<> \ +struct param_traits \ +{ \ + enum { value = param_name }; \ + typedef T param_type; \ +}; + +CL_HPP_PARAM_NAME_INFO_1_0_(CL_HPP_DECLARE_PARAM_TRAITS_) +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 +CL_HPP_PARAM_NAME_INFO_1_1_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 110 +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +CL_HPP_PARAM_NAME_INFO_1_2_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +CL_HPP_PARAM_NAME_INFO_2_0_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 +CL_HPP_PARAM_NAME_INFO_2_1_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 210 + +#if defined(CL_HPP_USE_CL_SUB_GROUPS_KHR) && CL_HPP_TARGET_OPENCL_VERSION < 210 +CL_HPP_PARAM_NAME_INFO_SUBGROUP_KHR_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // #if defined(CL_HPP_USE_CL_SUB_GROUPS_KHR) && CL_HPP_TARGET_OPENCL_VERSION < 210 + +#if defined(CL_HPP_USE_IL_KHR) +CL_HPP_PARAM_NAME_INFO_IL_KHR_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // #if defined(CL_HPP_USE_IL_KHR) + + +// Flags deprecated in OpenCL 2.0 +#define CL_HPP_PARAM_NAME_INFO_1_0_DEPRECATED_IN_2_0_(F) \ + F(cl_device_info, CL_DEVICE_QUEUE_PROPERTIES, cl_command_queue_properties) + +#define CL_HPP_PARAM_NAME_INFO_1_1_DEPRECATED_IN_2_0_(F) \ + F(cl_device_info, CL_DEVICE_HOST_UNIFIED_MEMORY, cl_bool) + +#define CL_HPP_PARAM_NAME_INFO_1_2_DEPRECATED_IN_2_0_(F) \ + F(cl_image_info, CL_IMAGE_BUFFER, cl::Buffer) + +// Include deprecated query flags based on versions +// Only include deprecated 1.0 flags if 2.0 not active as there is an enum clash +#if CL_HPP_TARGET_OPENCL_VERSION > 100 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 && CL_HPP_TARGET_OPENCL_VERSION < 200 +CL_HPP_PARAM_NAME_INFO_1_0_DEPRECATED_IN_2_0_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 110 +#if CL_HPP_TARGET_OPENCL_VERSION > 110 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 +CL_HPP_PARAM_NAME_INFO_1_1_DEPRECATED_IN_2_0_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 120 +#if CL_HPP_TARGET_OPENCL_VERSION > 120 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 +CL_HPP_PARAM_NAME_INFO_1_2_DEPRECATED_IN_2_0_(CL_HPP_DECLARE_PARAM_TRAITS_) +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 200 + +#if defined(CL_HPP_USE_CL_DEVICE_FISSION) +CL_HPP_PARAM_NAME_DEVICE_FISSION_(CL_HPP_DECLARE_PARAM_TRAITS_); +#endif // CL_HPP_USE_CL_DEVICE_FISSION + +#ifdef CL_PLATFORM_ICD_SUFFIX_KHR +CL_HPP_DECLARE_PARAM_TRAITS_(cl_platform_info, CL_PLATFORM_ICD_SUFFIX_KHR, string) +#endif + +#ifdef CL_DEVICE_PROFILING_TIMER_OFFSET_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_PROFILING_TIMER_OFFSET_AMD, cl_ulong) +#endif + +#ifdef CL_DEVICE_GLOBAL_FREE_MEMORY_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_GLOBAL_FREE_MEMORY_AMD, vector) +#endif +#ifdef CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_SIMD_WIDTH_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_SIMD_WIDTH_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_WAVEFRONT_WIDTH_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_WAVEFRONT_WIDTH_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD, cl_uint) +#endif +#ifdef CL_DEVICE_LOCAL_MEM_BANKS_AMD +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_LOCAL_MEM_BANKS_AMD, cl_uint) +#endif + +#ifdef CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV, cl_uint) +#endif +#ifdef CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV, cl_uint) +#endif +#ifdef CL_DEVICE_REGISTERS_PER_BLOCK_NV +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_REGISTERS_PER_BLOCK_NV, cl_uint) +#endif +#ifdef CL_DEVICE_WARP_SIZE_NV +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_WARP_SIZE_NV, cl_uint) +#endif +#ifdef CL_DEVICE_GPU_OVERLAP_NV +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_GPU_OVERLAP_NV, cl_bool) +#endif +#ifdef CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV, cl_bool) +#endif +#ifdef CL_DEVICE_INTEGRATED_MEMORY_NV +CL_HPP_DECLARE_PARAM_TRAITS_(cl_device_info, CL_DEVICE_INTEGRATED_MEMORY_NV, cl_bool) +#endif + +// Convenience functions + +template +inline cl_int +getInfo(Func f, cl_uint name, T* param) +{ + return getInfoHelper(f, name, param, 0); +} + +template +struct GetInfoFunctor0 +{ + Func f_; const Arg0& arg0_; + cl_int operator ()( + cl_uint param, size_type size, void* value, size_type* size_ret) + { return f_(arg0_, param, size, value, size_ret); } +}; + +template +struct GetInfoFunctor1 +{ + Func f_; const Arg0& arg0_; const Arg1& arg1_; + cl_int operator ()( + cl_uint param, size_type size, void* value, size_type* size_ret) + { return f_(arg0_, arg1_, param, size, value, size_ret); } +}; + +template +inline cl_int +getInfo(Func f, const Arg0& arg0, cl_uint name, T* param) +{ + GetInfoFunctor0 f0 = { f, arg0 }; + return getInfoHelper(f0, name, param, 0); +} + +template +inline cl_int +getInfo(Func f, const Arg0& arg0, const Arg1& arg1, cl_uint name, T* param) +{ + GetInfoFunctor1 f0 = { f, arg0, arg1 }; + return getInfoHelper(f0, name, param, 0); +} + + +template +struct ReferenceHandler +{ }; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +/** + * OpenCL 1.2 devices do have retain/release. + */ +template <> +struct ReferenceHandler +{ + /** + * Retain the device. + * \param device A valid device created using createSubDevices + * \return + * CL_SUCCESS if the function executed successfully. + * CL_INVALID_DEVICE if device was not a valid subdevice + * CL_OUT_OF_RESOURCES + * CL_OUT_OF_HOST_MEMORY + */ + static cl_int retain(cl_device_id device) + { return ::clRetainDevice(device); } + /** + * Retain the device. + * \param device A valid device created using createSubDevices + * \return + * CL_SUCCESS if the function executed successfully. + * CL_INVALID_DEVICE if device was not a valid subdevice + * CL_OUT_OF_RESOURCES + * CL_OUT_OF_HOST_MEMORY + */ + static cl_int release(cl_device_id device) + { return ::clReleaseDevice(device); } +}; +#else // CL_HPP_TARGET_OPENCL_VERSION >= 120 +/** + * OpenCL 1.1 devices do not have retain/release. + */ +template <> +struct ReferenceHandler +{ + // cl_device_id does not have retain(). + static cl_int retain(cl_device_id) + { return CL_SUCCESS; } + // cl_device_id does not have release(). + static cl_int release(cl_device_id) + { return CL_SUCCESS; } +}; +#endif // ! (CL_HPP_TARGET_OPENCL_VERSION >= 120) + +template <> +struct ReferenceHandler +{ + // cl_platform_id does not have retain(). + static cl_int retain(cl_platform_id) + { return CL_SUCCESS; } + // cl_platform_id does not have release(). + static cl_int release(cl_platform_id) + { return CL_SUCCESS; } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_context context) + { return ::clRetainContext(context); } + static cl_int release(cl_context context) + { return ::clReleaseContext(context); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_command_queue queue) + { return ::clRetainCommandQueue(queue); } + static cl_int release(cl_command_queue queue) + { return ::clReleaseCommandQueue(queue); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_mem memory) + { return ::clRetainMemObject(memory); } + static cl_int release(cl_mem memory) + { return ::clReleaseMemObject(memory); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_sampler sampler) + { return ::clRetainSampler(sampler); } + static cl_int release(cl_sampler sampler) + { return ::clReleaseSampler(sampler); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_program program) + { return ::clRetainProgram(program); } + static cl_int release(cl_program program) + { return ::clReleaseProgram(program); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_kernel kernel) + { return ::clRetainKernel(kernel); } + static cl_int release(cl_kernel kernel) + { return ::clReleaseKernel(kernel); } +}; + +template <> +struct ReferenceHandler +{ + static cl_int retain(cl_event event) + { return ::clRetainEvent(event); } + static cl_int release(cl_event event) + { return ::clReleaseEvent(event); } +}; + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 && CL_HPP_MINIMUM_OPENCL_VERSION < 120 +// Extracts version number with major in the upper 16 bits, minor in the lower 16 +static cl_uint getVersion(const vector &versionInfo) +{ + int highVersion = 0; + int lowVersion = 0; + int index = 7; + while(versionInfo[index] != '.' ) { + highVersion *= 10; + highVersion += versionInfo[index]-'0'; + ++index; + } + ++index; + while(versionInfo[index] != ' ' && versionInfo[index] != '\0') { + lowVersion *= 10; + lowVersion += versionInfo[index]-'0'; + ++index; + } + return (highVersion << 16) | lowVersion; +} + +static cl_uint getPlatformVersion(cl_platform_id platform) +{ + size_type size = 0; + clGetPlatformInfo(platform, CL_PLATFORM_VERSION, 0, NULL, &size); + + vector versionInfo(size); + clGetPlatformInfo(platform, CL_PLATFORM_VERSION, size, versionInfo.data(), &size); + return getVersion(versionInfo); +} + +static cl_uint getDevicePlatformVersion(cl_device_id device) +{ + cl_platform_id platform; + clGetDeviceInfo(device, CL_DEVICE_PLATFORM, sizeof(platform), &platform, NULL); + return getPlatformVersion(platform); +} + +static cl_uint getContextPlatformVersion(cl_context context) +{ + // The platform cannot be queried directly, so we first have to grab a + // device and obtain its context + size_type size = 0; + clGetContextInfo(context, CL_CONTEXT_DEVICES, 0, NULL, &size); + if (size == 0) + return 0; + vector devices(size/sizeof(cl_device_id)); + clGetContextInfo(context, CL_CONTEXT_DEVICES, size, devices.data(), NULL); + return getDevicePlatformVersion(devices[0]); +} +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 && CL_HPP_MINIMUM_OPENCL_VERSION < 120 + +template +class Wrapper +{ +public: + typedef T cl_type; + +protected: + cl_type object_; + +public: + Wrapper() : object_(NULL) { } + + Wrapper(const cl_type &obj, bool retainObject) : object_(obj) + { + if (retainObject) { + detail::errHandler(retain(), __RETAIN_ERR); + } + } + + ~Wrapper() + { + if (object_ != NULL) { release(); } + } + + Wrapper(const Wrapper& rhs) + { + object_ = rhs.object_; + detail::errHandler(retain(), __RETAIN_ERR); + } + + Wrapper(Wrapper&& rhs) CL_HPP_NOEXCEPT_ + { + object_ = rhs.object_; + rhs.object_ = NULL; + } + + Wrapper& operator = (const Wrapper& rhs) + { + if (this != &rhs) { + detail::errHandler(release(), __RELEASE_ERR); + object_ = rhs.object_; + detail::errHandler(retain(), __RETAIN_ERR); + } + return *this; + } + + Wrapper& operator = (Wrapper&& rhs) + { + if (this != &rhs) { + detail::errHandler(release(), __RELEASE_ERR); + object_ = rhs.object_; + rhs.object_ = NULL; + } + return *this; + } + + Wrapper& operator = (const cl_type &rhs) + { + detail::errHandler(release(), __RELEASE_ERR); + object_ = rhs; + return *this; + } + + const cl_type& operator ()() const { return object_; } + + cl_type& operator ()() { return object_; } + + const cl_type get() const { return object_; } + + cl_type get() { return object_; } + + +protected: + template + friend inline cl_int getInfoHelper(Func, cl_uint, U*, int, typename U::cl_type); + + cl_int retain() const + { + if (object_ != nullptr) { + return ReferenceHandler::retain(object_); + } + else { + return CL_SUCCESS; + } + } + + cl_int release() const + { + if (object_ != nullptr) { + return ReferenceHandler::release(object_); + } + else { + return CL_SUCCESS; + } + } +}; + +template <> +class Wrapper +{ +public: + typedef cl_device_id cl_type; + +protected: + cl_type object_; + bool referenceCountable_; + + static bool isReferenceCountable(cl_device_id device) + { + bool retVal = false; +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 120 + if (device != NULL) { + int version = getDevicePlatformVersion(device); + if(version > ((1 << 16) + 1)) { + retVal = true; + } + } +#else // CL_HPP_MINIMUM_OPENCL_VERSION < 120 + retVal = true; +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 120 +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + return retVal; + } + +public: + Wrapper() : object_(NULL), referenceCountable_(false) + { + } + + Wrapper(const cl_type &obj, bool retainObject) : + object_(obj), + referenceCountable_(false) + { + referenceCountable_ = isReferenceCountable(obj); + + if (retainObject) { + detail::errHandler(retain(), __RETAIN_ERR); + } + } + + ~Wrapper() + { + release(); + } + + Wrapper(const Wrapper& rhs) + { + object_ = rhs.object_; + referenceCountable_ = isReferenceCountable(object_); + detail::errHandler(retain(), __RETAIN_ERR); + } + + Wrapper(Wrapper&& rhs) CL_HPP_NOEXCEPT_ + { + object_ = rhs.object_; + referenceCountable_ = rhs.referenceCountable_; + rhs.object_ = NULL; + rhs.referenceCountable_ = false; + } + + Wrapper& operator = (const Wrapper& rhs) + { + if (this != &rhs) { + detail::errHandler(release(), __RELEASE_ERR); + object_ = rhs.object_; + referenceCountable_ = rhs.referenceCountable_; + detail::errHandler(retain(), __RETAIN_ERR); + } + return *this; + } + + Wrapper& operator = (Wrapper&& rhs) + { + if (this != &rhs) { + detail::errHandler(release(), __RELEASE_ERR); + object_ = rhs.object_; + referenceCountable_ = rhs.referenceCountable_; + rhs.object_ = NULL; + rhs.referenceCountable_ = false; + } + return *this; + } + + Wrapper& operator = (const cl_type &rhs) + { + detail::errHandler(release(), __RELEASE_ERR); + object_ = rhs; + referenceCountable_ = isReferenceCountable(object_); + return *this; + } + + const cl_type& operator ()() const { return object_; } + + cl_type& operator ()() { return object_; } + + cl_type get() const { return object_; } + +protected: + template + friend inline cl_int getInfoHelper(Func, cl_uint, U*, int, typename U::cl_type); + + template + friend inline cl_int getInfoHelper(Func, cl_uint, vector*, int, typename U::cl_type); + + cl_int retain() const + { + if( object_ != nullptr && referenceCountable_ ) { + return ReferenceHandler::retain(object_); + } + else { + return CL_SUCCESS; + } + } + + cl_int release() const + { + if (object_ != nullptr && referenceCountable_) { + return ReferenceHandler::release(object_); + } + else { + return CL_SUCCESS; + } + } +}; + +template +inline bool operator==(const Wrapper &lhs, const Wrapper &rhs) +{ + return lhs() == rhs(); +} + +template +inline bool operator!=(const Wrapper &lhs, const Wrapper &rhs) +{ + return !operator==(lhs, rhs); +} + +} // namespace detail +//! \endcond + + +using BuildLogType = vector::param_type>>; +#if defined(CL_HPP_ENABLE_EXCEPTIONS) +/** +* Exception class for build errors to carry build info +*/ +class BuildError : public Error +{ +private: + BuildLogType buildLogs; +public: + BuildError(cl_int err, const char * errStr, const BuildLogType &vec) : Error(err, errStr), buildLogs(vec) + { + } + + BuildLogType getBuildLog() const + { + return buildLogs; + } +}; +namespace detail { + static inline cl_int buildErrHandler( + cl_int err, + const char * errStr, + const BuildLogType &buildLogs) + { + if (err != CL_SUCCESS) { + throw BuildError(err, errStr, buildLogs); + } + return err; + } +} // namespace detail + +#else +namespace detail { + static inline cl_int buildErrHandler( + cl_int err, + const char * errStr, + const BuildLogType &buildLogs) + { + (void)buildLogs; // suppress unused variable warning + (void)errStr; + return err; + } +} // namespace detail +#endif // #if defined(CL_HPP_ENABLE_EXCEPTIONS) + + +/*! \stuct ImageFormat + * \brief Adds constructors and member functions for cl_image_format. + * + * \see cl_image_format + */ +struct ImageFormat : public cl_image_format +{ + //! \brief Default constructor - performs no initialization. + ImageFormat(){} + + //! \brief Initializing constructor. + ImageFormat(cl_channel_order order, cl_channel_type type) + { + image_channel_order = order; + image_channel_data_type = type; + } + + //! \brief Assignment operator. + ImageFormat& operator = (const ImageFormat& rhs) + { + if (this != &rhs) { + this->image_channel_data_type = rhs.image_channel_data_type; + this->image_channel_order = rhs.image_channel_order; + } + return *this; + } +}; + +/*! \brief Class interface for cl_device_id. + * + * \note Copies of these objects are inexpensive, since they don't 'own' + * any underlying resources or data structures. + * + * \see cl_device_id + */ +class Device : public detail::Wrapper +{ +private: + static std::once_flag default_initialized_; + static Device default_; + static cl_int default_error_; + + /*! \brief Create the default context. + * + * This sets @c default_ and @c default_error_. It does not throw + * @c cl::Error. + */ + static void makeDefault(); + + /*! \brief Create the default platform from a provided platform. + * + * This sets @c default_. It does not throw + * @c cl::Error. + */ + static void makeDefaultProvided(const Device &p) { + default_ = p; + } + +public: +#ifdef CL_HPP_UNIT_TEST_ENABLE + /*! \brief Reset the default. + * + * This sets @c default_ to an empty value to support cleanup in + * the unit test framework. + * This function is not thread safe. + */ + static void unitTestClearDefault() { + default_ = Device(); + } +#endif // #ifdef CL_HPP_UNIT_TEST_ENABLE + + //! \brief Default constructor - initializes to NULL. + Device() : detail::Wrapper() { } + + /*! \brief Constructor from cl_device_id. + * + * This simply copies the device ID value, which is an inexpensive operation. + */ + explicit Device(const cl_device_id &device, bool retainObject = false) : + detail::Wrapper(device, retainObject) { } + + /*! \brief Returns the first device on the default context. + * + * \see Context::getDefault() + */ + static Device getDefault( + cl_int *errResult = NULL) + { + std::call_once(default_initialized_, makeDefault); + detail::errHandler(default_error_); + if (errResult != NULL) { + *errResult = default_error_; + } + return default_; + } + + /** + * Modify the default device to be used by + * subsequent operations. + * Will only set the default if no default was previously created. + * @return updated default device. + * Should be compared to the passed value to ensure that it was updated. + */ + static Device setDefault(const Device &default_device) + { + std::call_once(default_initialized_, makeDefaultProvided, std::cref(default_device)); + detail::errHandler(default_error_); + return default_; + } + + /*! \brief Assignment operator from cl_device_id. + * + * This simply copies the device ID value, which is an inexpensive operation. + */ + Device& operator = (const cl_device_id& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Device(const Device& dev) : detail::Wrapper(dev) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Device& operator = (const Device &dev) + { + detail::Wrapper::operator=(dev); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Device(Device&& dev) CL_HPP_NOEXCEPT_ : detail::Wrapper(std::move(dev)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Device& operator = (Device &&dev) + { + detail::Wrapper::operator=(std::move(dev)); + return *this; + } + + //! \brief Wrapper for clGetDeviceInfo(). + template + cl_int getInfo(cl_device_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetDeviceInfo, object_, name, param), + __GET_DEVICE_INFO_ERR); + } + + //! \brief Wrapper for clGetDeviceInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_device_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 + /** + * Return the current value of the host clock as seen by the device. + * The resolution of the device timer may be queried with the + * CL_DEVICE_PROFILING_TIMER_RESOLUTION query. + * @return The host timer value. + */ + cl_ulong getHostTimer(cl_int *error = nullptr) + { + cl_ulong retVal = 0; + cl_int err = + clGetHostTimer(this->get(), &retVal); + detail::errHandler( + err, + __GET_HOST_TIMER_ERR); + if (error) { + *error = err; + } + return retVal; + } + + /** + * Return a synchronized pair of host and device timestamps as seen by device. + * Use to correlate the clocks and get the host timer only using getHostTimer + * as a lower cost mechanism in between calls. + * The resolution of the host timer may be queried with the + * CL_PLATFORM_HOST_TIMER_RESOLUTION query. + * The resolution of the device timer may be queried with the + * CL_DEVICE_PROFILING_TIMER_RESOLUTION query. + * @return A pair of (device timer, host timer) timer values. + */ + std::pair getDeviceAndHostTimer(cl_int *error = nullptr) + { + std::pair retVal; + cl_int err = + clGetDeviceAndHostTimer(this->get(), &(retVal.first), &(retVal.second)); + detail::errHandler( + err, + __GET_DEVICE_AND_HOST_TIMER_ERR); + if (error) { + *error = err; + } + return retVal; + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + /** + * CL 1.2 version + */ +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + //! \brief Wrapper for clCreateSubDevices(). + cl_int createSubDevices( + const cl_device_partition_property * properties, + vector* devices) + { + cl_uint n = 0; + cl_int err = clCreateSubDevices(object_, properties, 0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_SUB_DEVICES_ERR); + } + + vector ids(n); + err = clCreateSubDevices(object_, properties, n, ids.data(), NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_SUB_DEVICES_ERR); + } + + // Cannot trivially assign because we need to capture intermediates + // with safe construction + if (devices) { + devices->resize(ids.size()); + + // Assign to param, constructing with retain behaviour + // to correctly capture each underlying CL object + for (size_type i = 0; i < ids.size(); i++) { + // We do not need to retain because this device is being created + // by the runtime + (*devices)[i] = Device(ids[i], false); + } + } + + return CL_SUCCESS; + } +#elif defined(CL_HPP_USE_CL_DEVICE_FISSION) + +/** + * CL 1.1 version that uses device fission extension. + */ + cl_int createSubDevices( + const cl_device_partition_property_ext * properties, + vector* devices) + { + typedef CL_API_ENTRY cl_int + ( CL_API_CALL * PFN_clCreateSubDevicesEXT)( + cl_device_id /*in_device*/, + const cl_device_partition_property_ext * /* properties */, + cl_uint /*num_entries*/, + cl_device_id * /*out_devices*/, + cl_uint * /*num_devices*/ ) CL_EXT_SUFFIX__VERSION_1_1; + + static PFN_clCreateSubDevicesEXT pfn_clCreateSubDevicesEXT = NULL; + CL_HPP_INIT_CL_EXT_FCN_PTR_(clCreateSubDevicesEXT); + + cl_uint n = 0; + cl_int err = pfn_clCreateSubDevicesEXT(object_, properties, 0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_SUB_DEVICES_ERR); + } + + vector ids(n); + err = pfn_clCreateSubDevicesEXT(object_, properties, n, ids.data(), NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_SUB_DEVICES_ERR); + } + // Cannot trivially assign because we need to capture intermediates + // with safe construction + if (devices) { + devices->resize(ids.size()); + + // Assign to param, constructing with retain behaviour + // to correctly capture each underlying CL object + for (size_type i = 0; i < ids.size(); i++) { + // We do not need to retain because this device is being created + // by the runtime + (*devices)[i] = Device(ids[i], false); + } + } + return CL_SUCCESS; + } +#endif // defined(CL_HPP_USE_CL_DEVICE_FISSION) +}; + +CL_HPP_DEFINE_STATIC_MEMBER_ std::once_flag Device::default_initialized_; +CL_HPP_DEFINE_STATIC_MEMBER_ Device Device::default_; +CL_HPP_DEFINE_STATIC_MEMBER_ cl_int Device::default_error_ = CL_SUCCESS; + +/*! \brief Class interface for cl_platform_id. + * + * \note Copies of these objects are inexpensive, since they don't 'own' + * any underlying resources or data structures. + * + * \see cl_platform_id + */ +class Platform : public detail::Wrapper +{ +private: + static std::once_flag default_initialized_; + static Platform default_; + static cl_int default_error_; + + /*! \brief Create the default context. + * + * This sets @c default_ and @c default_error_. It does not throw + * @c cl::Error. + */ + static void makeDefault() { + /* Throwing an exception from a call_once invocation does not do + * what we wish, so we catch it and save the error. + */ +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + try +#endif + { + // If default wasn't passed ,generate one + // Otherwise set it + cl_uint n = 0; + + cl_int err = ::clGetPlatformIDs(0, NULL, &n); + if (err != CL_SUCCESS) { + default_error_ = err; + return; + } + if (n == 0) { + default_error_ = CL_INVALID_PLATFORM; + return; + } + + vector ids(n); + err = ::clGetPlatformIDs(n, ids.data(), NULL); + if (err != CL_SUCCESS) { + default_error_ = err; + return; + } + + default_ = Platform(ids[0]); + } +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + catch (cl::Error &e) { + default_error_ = e.err(); + } +#endif + } + + /*! \brief Create the default platform from a provided platform. + * + * This sets @c default_. It does not throw + * @c cl::Error. + */ + static void makeDefaultProvided(const Platform &p) { + default_ = p; + } + +public: +#ifdef CL_HPP_UNIT_TEST_ENABLE + /*! \brief Reset the default. + * + * This sets @c default_ to an empty value to support cleanup in + * the unit test framework. + * This function is not thread safe. + */ + static void unitTestClearDefault() { + default_ = Platform(); + } +#endif // #ifdef CL_HPP_UNIT_TEST_ENABLE + + //! \brief Default constructor - initializes to NULL. + Platform() : detail::Wrapper() { } + + /*! \brief Constructor from cl_platform_id. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * This simply copies the platform ID value, which is an inexpensive operation. + */ + explicit Platform(const cl_platform_id &platform, bool retainObject = false) : + detail::Wrapper(platform, retainObject) { } + + /*! \brief Assignment operator from cl_platform_id. + * + * This simply copies the platform ID value, which is an inexpensive operation. + */ + Platform& operator = (const cl_platform_id& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + static Platform getDefault( + cl_int *errResult = NULL) + { + std::call_once(default_initialized_, makeDefault); + detail::errHandler(default_error_); + if (errResult != NULL) { + *errResult = default_error_; + } + return default_; + } + + /** + * Modify the default platform to be used by + * subsequent operations. + * Will only set the default if no default was previously created. + * @return updated default platform. + * Should be compared to the passed value to ensure that it was updated. + */ + static Platform setDefault(const Platform &default_platform) + { + std::call_once(default_initialized_, makeDefaultProvided, std::cref(default_platform)); + detail::errHandler(default_error_); + return default_; + } + + //! \brief Wrapper for clGetPlatformInfo(). + cl_int getInfo(cl_platform_info name, string* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetPlatformInfo, object_, name, param), + __GET_PLATFORM_INFO_ERR); + } + + //! \brief Wrapper for clGetPlatformInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_platform_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /*! \brief Gets a list of devices for this platform. + * + * Wraps clGetDeviceIDs(). + */ + cl_int getDevices( + cl_device_type type, + vector* devices) const + { + cl_uint n = 0; + if( devices == NULL ) { + return detail::errHandler(CL_INVALID_ARG_VALUE, __GET_DEVICE_IDS_ERR); + } + cl_int err = ::clGetDeviceIDs(object_, type, 0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_DEVICE_IDS_ERR); + } + + vector ids(n); + err = ::clGetDeviceIDs(object_, type, n, ids.data(), NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_DEVICE_IDS_ERR); + } + + // Cannot trivially assign because we need to capture intermediates + // with safe construction + // We must retain things we obtain from the API to avoid releasing + // API-owned objects. + if (devices) { + devices->resize(ids.size()); + + // Assign to param, constructing with retain behaviour + // to correctly capture each underlying CL object + for (size_type i = 0; i < ids.size(); i++) { + (*devices)[i] = Device(ids[i], true); + } + } + return CL_SUCCESS; + } + +#if defined(CL_HPP_USE_DX_INTEROP) + /*! \brief Get the list of available D3D10 devices. + * + * \param d3d_device_source. + * + * \param d3d_object. + * + * \param d3d_device_set. + * + * \param devices returns a vector of OpenCL D3D10 devices found. The cl::Device + * values returned in devices can be used to identify a specific OpenCL + * device. If \a devices argument is NULL, this argument is ignored. + * + * \return One of the following values: + * - CL_SUCCESS if the function is executed successfully. + * + * The application can query specific capabilities of the OpenCL device(s) + * returned by cl::getDevices. This can be used by the application to + * determine which device(s) to use. + * + * \note In the case that exceptions are enabled and a return value + * other than CL_SUCCESS is generated, then cl::Error exception is + * generated. + */ + cl_int getDevices( + cl_d3d10_device_source_khr d3d_device_source, + void * d3d_object, + cl_d3d10_device_set_khr d3d_device_set, + vector* devices) const + { + typedef CL_API_ENTRY cl_int (CL_API_CALL *PFN_clGetDeviceIDsFromD3D10KHR)( + cl_platform_id platform, + cl_d3d10_device_source_khr d3d_device_source, + void * d3d_object, + cl_d3d10_device_set_khr d3d_device_set, + cl_uint num_entries, + cl_device_id * devices, + cl_uint* num_devices); + + if( devices == NULL ) { + return detail::errHandler(CL_INVALID_ARG_VALUE, __GET_DEVICE_IDS_ERR); + } + + static PFN_clGetDeviceIDsFromD3D10KHR pfn_clGetDeviceIDsFromD3D10KHR = NULL; + CL_HPP_INIT_CL_EXT_FCN_PTR_PLATFORM_(object_, clGetDeviceIDsFromD3D10KHR); + + cl_uint n = 0; + cl_int err = pfn_clGetDeviceIDsFromD3D10KHR( + object_, + d3d_device_source, + d3d_object, + d3d_device_set, + 0, + NULL, + &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_DEVICE_IDS_ERR); + } + + vector ids(n); + err = pfn_clGetDeviceIDsFromD3D10KHR( + object_, + d3d_device_source, + d3d_object, + d3d_device_set, + n, + ids.data(), + NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_DEVICE_IDS_ERR); + } + + // Cannot trivially assign because we need to capture intermediates + // with safe construction + // We must retain things we obtain from the API to avoid releasing + // API-owned objects. + if (devices) { + devices->resize(ids.size()); + + // Assign to param, constructing with retain behaviour + // to correctly capture each underlying CL object + for (size_type i = 0; i < ids.size(); i++) { + (*devices)[i] = Device(ids[i], true); + } + } + return CL_SUCCESS; + } +#endif + + /*! \brief Gets a list of available platforms. + * + * Wraps clGetPlatformIDs(). + */ + static cl_int get( + vector* platforms) + { + cl_uint n = 0; + + if( platforms == NULL ) { + return detail::errHandler(CL_INVALID_ARG_VALUE, __GET_PLATFORM_IDS_ERR); + } + + cl_int err = ::clGetPlatformIDs(0, NULL, &n); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_PLATFORM_IDS_ERR); + } + + vector ids(n); + err = ::clGetPlatformIDs(n, ids.data(), NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_PLATFORM_IDS_ERR); + } + + if (platforms) { + platforms->resize(ids.size()); + + // Platforms don't reference count + for (size_type i = 0; i < ids.size(); i++) { + (*platforms)[i] = Platform(ids[i]); + } + } + return CL_SUCCESS; + } + + /*! \brief Gets the first available platform. + * + * Wraps clGetPlatformIDs(), returning the first result. + */ + static cl_int get( + Platform * platform) + { + cl_int err; + Platform default_platform = Platform::getDefault(&err); + if (platform) { + *platform = default_platform; + } + return err; + } + + /*! \brief Gets the first available platform, returning it by value. + * + * \return Returns a valid platform if one is available. + * If no platform is available will return a null platform. + * Throws an exception if no platforms are available + * or an error condition occurs. + * Wraps clGetPlatformIDs(), returning the first result. + */ + static Platform get( + cl_int * errResult = NULL) + { + cl_int err; + Platform default_platform = Platform::getDefault(&err); + if (errResult) { + *errResult = err; + } + return default_platform; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + //! \brief Wrapper for clUnloadCompiler(). + cl_int + unloadCompiler() + { + return ::clUnloadPlatformCompiler(object_); + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +}; // class Platform + +CL_HPP_DEFINE_STATIC_MEMBER_ std::once_flag Platform::default_initialized_; +CL_HPP_DEFINE_STATIC_MEMBER_ Platform Platform::default_; +CL_HPP_DEFINE_STATIC_MEMBER_ cl_int Platform::default_error_ = CL_SUCCESS; + + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +/** + * Unload the OpenCL compiler. + * \note Deprecated for OpenCL 1.2. Use Platform::unloadCompiler instead. + */ +inline CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int +UnloadCompiler() CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; +inline cl_int +UnloadCompiler() +{ + return ::clUnloadCompiler(); +} +#endif // #if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + +/*! \brief Class interface for cl_context. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_context as the original. For details, see + * clRetainContext() and clReleaseContext(). + * + * \see cl_context + */ +class Context + : public detail::Wrapper +{ +private: + static std::once_flag default_initialized_; + static Context default_; + static cl_int default_error_; + + /*! \brief Create the default context from the default device type in the default platform. + * + * This sets @c default_ and @c default_error_. It does not throw + * @c cl::Error. + */ + static void makeDefault() { + /* Throwing an exception from a call_once invocation does not do + * what we wish, so we catch it and save the error. + */ +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + try +#endif + { +#if !defined(__APPLE__) && !defined(__MACOS) + const Platform &p = Platform::getDefault(); + cl_platform_id defaultPlatform = p(); + cl_context_properties properties[3] = { + CL_CONTEXT_PLATFORM, (cl_context_properties)defaultPlatform, 0 + }; +#else // #if !defined(__APPLE__) && !defined(__MACOS) + cl_context_properties *properties = nullptr; +#endif // #if !defined(__APPLE__) && !defined(__MACOS) + + default_ = Context( + CL_DEVICE_TYPE_DEFAULT, + properties, + NULL, + NULL, + &default_error_); + } +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + catch (cl::Error &e) { + default_error_ = e.err(); + } +#endif + } + + + /*! \brief Create the default context from a provided Context. + * + * This sets @c default_. It does not throw + * @c cl::Error. + */ + static void makeDefaultProvided(const Context &c) { + default_ = c; + } + +public: +#ifdef CL_HPP_UNIT_TEST_ENABLE + /*! \brief Reset the default. + * + * This sets @c default_ to an empty value to support cleanup in + * the unit test framework. + * This function is not thread safe. + */ + static void unitTestClearDefault() { + default_ = Context(); + } +#endif // #ifdef CL_HPP_UNIT_TEST_ENABLE + + /*! \brief Constructs a context including a list of specified devices. + * + * Wraps clCreateContext(). + */ + Context( + const vector& devices, + cl_context_properties* properties = NULL, + void (CL_CALLBACK * notifyFptr)( + const char *, + const void *, + size_type, + void *) = NULL, + void* data = NULL, + cl_int* err = NULL) + { + cl_int error; + + size_type numDevices = devices.size(); + vector deviceIDs(numDevices); + + for( size_type deviceIndex = 0; deviceIndex < numDevices; ++deviceIndex ) { + deviceIDs[deviceIndex] = (devices[deviceIndex])(); + } + + object_ = ::clCreateContext( + properties, (cl_uint) numDevices, + deviceIDs.data(), + notifyFptr, data, &error); + + detail::errHandler(error, __CREATE_CONTEXT_ERR); + if (err != NULL) { + *err = error; + } + } + + Context( + const Device& device, + cl_context_properties* properties = NULL, + void (CL_CALLBACK * notifyFptr)( + const char *, + const void *, + size_type, + void *) = NULL, + void* data = NULL, + cl_int* err = NULL) + { + cl_int error; + + cl_device_id deviceID = device(); + + object_ = ::clCreateContext( + properties, 1, + &deviceID, + notifyFptr, data, &error); + + detail::errHandler(error, __CREATE_CONTEXT_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Constructs a context including all or a subset of devices of a specified type. + * + * Wraps clCreateContextFromType(). + */ + Context( + cl_device_type type, + cl_context_properties* properties = NULL, + void (CL_CALLBACK * notifyFptr)( + const char *, + const void *, + size_type, + void *) = NULL, + void* data = NULL, + cl_int* err = NULL) + { + cl_int error; + +#if !defined(__APPLE__) && !defined(__MACOS) + cl_context_properties prop[4] = {CL_CONTEXT_PLATFORM, 0, 0, 0 }; + + if (properties == NULL) { + // Get a valid platform ID as we cannot send in a blank one + vector platforms; + error = Platform::get(&platforms); + if (error != CL_SUCCESS) { + detail::errHandler(error, __CREATE_CONTEXT_FROM_TYPE_ERR); + if (err != NULL) { + *err = error; + } + return; + } + + // Check the platforms we found for a device of our specified type + cl_context_properties platform_id = 0; + for (unsigned int i = 0; i < platforms.size(); i++) { + + vector devices; + +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + try { +#endif + + error = platforms[i].getDevices(type, &devices); + +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + } catch (cl::Error& e) { + error = e.err(); + } + // Catch if exceptions are enabled as we don't want to exit if first platform has no devices of type + // We do error checking next anyway, and can throw there if needed +#endif + + // Only squash CL_SUCCESS and CL_DEVICE_NOT_FOUND + if (error != CL_SUCCESS && error != CL_DEVICE_NOT_FOUND) { + detail::errHandler(error, __CREATE_CONTEXT_FROM_TYPE_ERR); + if (err != NULL) { + *err = error; + } + } + + if (devices.size() > 0) { + platform_id = (cl_context_properties)platforms[i](); + break; + } + } + + if (platform_id == 0) { + detail::errHandler(CL_DEVICE_NOT_FOUND, __CREATE_CONTEXT_FROM_TYPE_ERR); + if (err != NULL) { + *err = CL_DEVICE_NOT_FOUND; + } + return; + } + + prop[1] = platform_id; + properties = &prop[0]; + } +#endif + object_ = ::clCreateContextFromType( + properties, type, notifyFptr, data, &error); + + detail::errHandler(error, __CREATE_CONTEXT_FROM_TYPE_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Context(const Context& ctx) : detail::Wrapper(ctx) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Context& operator = (const Context &ctx) + { + detail::Wrapper::operator=(ctx); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Context(Context&& ctx) CL_HPP_NOEXCEPT_ : detail::Wrapper(std::move(ctx)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Context& operator = (Context &&ctx) + { + detail::Wrapper::operator=(std::move(ctx)); + return *this; + } + + + /*! \brief Returns a singleton context including all devices of CL_DEVICE_TYPE_DEFAULT. + * + * \note All calls to this function return the same cl_context as the first. + */ + static Context getDefault(cl_int * err = NULL) + { + std::call_once(default_initialized_, makeDefault); + detail::errHandler(default_error_); + if (err != NULL) { + *err = default_error_; + } + return default_; + } + + /** + * Modify the default context to be used by + * subsequent operations. + * Will only set the default if no default was previously created. + * @return updated default context. + * Should be compared to the passed value to ensure that it was updated. + */ + static Context setDefault(const Context &default_context) + { + std::call_once(default_initialized_, makeDefaultProvided, std::cref(default_context)); + detail::errHandler(default_error_); + return default_; + } + + //! \brief Default constructor - initializes to NULL. + Context() : detail::Wrapper() { } + + /*! \brief Constructor from cl_context - takes ownership. + * + * This effectively transfers ownership of a refcount on the cl_context + * into the new Context object. + */ + explicit Context(const cl_context& context, bool retainObject = false) : + detail::Wrapper(context, retainObject) { } + + /*! \brief Assignment operator from cl_context - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseContext() on the value previously held by this instance. + */ + Context& operator = (const cl_context& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetContextInfo(). + template + cl_int getInfo(cl_context_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetContextInfo, object_, name, param), + __GET_CONTEXT_INFO_ERR); + } + + //! \brief Wrapper for clGetContextInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_context_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /*! \brief Gets a list of supported image formats. + * + * Wraps clGetSupportedImageFormats(). + */ + cl_int getSupportedImageFormats( + cl_mem_flags flags, + cl_mem_object_type type, + vector* formats) const + { + cl_uint numEntries; + + if (!formats) { + return CL_SUCCESS; + } + + cl_int err = ::clGetSupportedImageFormats( + object_, + flags, + type, + 0, + NULL, + &numEntries); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_SUPPORTED_IMAGE_FORMATS_ERR); + } + + if (numEntries > 0) { + vector value(numEntries); + err = ::clGetSupportedImageFormats( + object_, + flags, + type, + numEntries, + (cl_image_format*)value.data(), + NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __GET_SUPPORTED_IMAGE_FORMATS_ERR); + } + + formats->assign(begin(value), end(value)); + } + else { + // If no values are being returned, ensure an empty vector comes back + formats->clear(); + } + + return CL_SUCCESS; + } +}; + +inline void Device::makeDefault() +{ + /* Throwing an exception from a call_once invocation does not do + * what we wish, so we catch it and save the error. + */ +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + try +#endif + { + cl_int error = 0; + + Context context = Context::getDefault(&error); + detail::errHandler(error, __CREATE_CONTEXT_ERR); + + if (error != CL_SUCCESS) { + default_error_ = error; + } + else { + default_ = context.getInfo()[0]; + default_error_ = CL_SUCCESS; + } + } +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + catch (cl::Error &e) { + default_error_ = e.err(); + } +#endif +} + +CL_HPP_DEFINE_STATIC_MEMBER_ std::once_flag Context::default_initialized_; +CL_HPP_DEFINE_STATIC_MEMBER_ Context Context::default_; +CL_HPP_DEFINE_STATIC_MEMBER_ cl_int Context::default_error_ = CL_SUCCESS; + +/*! \brief Class interface for cl_event. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_event as the original. For details, see + * clRetainEvent() and clReleaseEvent(). + * + * \see cl_event + */ +class Event : public detail::Wrapper +{ +public: + //! \brief Default constructor - initializes to NULL. + Event() : detail::Wrapper() { } + + /*! \brief Constructor from cl_event - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * This effectively transfers ownership of a refcount on the cl_event + * into the new Event object. + */ + explicit Event(const cl_event& event, bool retainObject = false) : + detail::Wrapper(event, retainObject) { } + + /*! \brief Assignment operator from cl_event - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseEvent() on the value previously held by this instance. + */ + Event& operator = (const cl_event& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + //! \brief Wrapper for clGetEventInfo(). + template + cl_int getInfo(cl_event_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetEventInfo, object_, name, param), + __GET_EVENT_INFO_ERR); + } + + //! \brief Wrapper for clGetEventInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_event_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + //! \brief Wrapper for clGetEventProfilingInfo(). + template + cl_int getProfilingInfo(cl_profiling_info name, T* param) const + { + return detail::errHandler(detail::getInfo( + &::clGetEventProfilingInfo, object_, name, param), + __GET_EVENT_PROFILE_INFO_ERR); + } + + //! \brief Wrapper for clGetEventProfilingInfo() that returns by value. + template typename + detail::param_traits::param_type + getProfilingInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_profiling_info, name>::param_type param; + cl_int result = getProfilingInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /*! \brief Blocks the calling thread until this event completes. + * + * Wraps clWaitForEvents(). + */ + cl_int wait() const + { + return detail::errHandler( + ::clWaitForEvents(1, &object_), + __WAIT_FOR_EVENTS_ERR); + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 + /*! \brief Registers a user callback function for a specific command execution status. + * + * Wraps clSetEventCallback(). + */ + cl_int setCallback( + cl_int type, + void (CL_CALLBACK * pfn_notify)(cl_event, cl_int, void *), + void * user_data = NULL) + { + return detail::errHandler( + ::clSetEventCallback( + object_, + type, + pfn_notify, + user_data), + __SET_EVENT_CALLBACK_ERR); + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 110 + + /*! \brief Blocks the calling thread until every event specified is complete. + * + * Wraps clWaitForEvents(). + */ + static cl_int + waitForEvents(const vector& events) + { + return detail::errHandler( + ::clWaitForEvents( + (cl_uint) events.size(), (events.size() > 0) ? (cl_event*)&events.front() : NULL), + __WAIT_FOR_EVENTS_ERR); + } +}; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 +/*! \brief Class interface for user events (a subset of cl_event's). + * + * See Event for details about copy semantics, etc. + */ +class UserEvent : public Event +{ +public: + /*! \brief Constructs a user event on a given context. + * + * Wraps clCreateUserEvent(). + */ + UserEvent( + const Context& context, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateUserEvent( + context(), + &error); + + detail::errHandler(error, __CREATE_USER_EVENT_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + UserEvent() : Event() { } + + /*! \brief Sets the execution status of a user event object. + * + * Wraps clSetUserEventStatus(). + */ + cl_int setStatus(cl_int status) + { + return detail::errHandler( + ::clSetUserEventStatus(object_,status), + __SET_USER_EVENT_STATUS_ERR); + } +}; +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 110 + +/*! \brief Blocks the calling thread until every event specified is complete. + * + * Wraps clWaitForEvents(). + */ +inline static cl_int +WaitForEvents(const vector& events) +{ + return detail::errHandler( + ::clWaitForEvents( + (cl_uint) events.size(), (events.size() > 0) ? (cl_event*)&events.front() : NULL), + __WAIT_FOR_EVENTS_ERR); +} + +/*! \brief Class interface for cl_mem. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_mem as the original. For details, see + * clRetainMemObject() and clReleaseMemObject(). + * + * \see cl_mem + */ +class Memory : public detail::Wrapper +{ +public: + //! \brief Default constructor - initializes to NULL. + Memory() : detail::Wrapper() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * Optionally transfer ownership of a refcount on the cl_mem + * into the new Memory object. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * + * See Memory for further details. + */ + explicit Memory(const cl_mem& memory, bool retainObject) : + detail::Wrapper(memory, retainObject) { } + + /*! \brief Assignment operator from cl_mem - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseMemObject() on the value previously held by this instance. + */ + Memory& operator = (const cl_mem& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Memory(const Memory& mem) : detail::Wrapper(mem) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Memory& operator = (const Memory &mem) + { + detail::Wrapper::operator=(mem); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Memory(Memory&& mem) CL_HPP_NOEXCEPT_ : detail::Wrapper(std::move(mem)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Memory& operator = (Memory &&mem) + { + detail::Wrapper::operator=(std::move(mem)); + return *this; + } + + + //! \brief Wrapper for clGetMemObjectInfo(). + template + cl_int getInfo(cl_mem_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetMemObjectInfo, object_, name, param), + __GET_MEM_OBJECT_INFO_ERR); + } + + //! \brief Wrapper for clGetMemObjectInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_mem_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 + /*! \brief Registers a callback function to be called when the memory object + * is no longer needed. + * + * Wraps clSetMemObjectDestructorCallback(). + * + * Repeated calls to this function, for a given cl_mem value, will append + * to the list of functions called (in reverse order) when memory object's + * resources are freed and the memory object is deleted. + * + * \note + * The registered callbacks are associated with the underlying cl_mem + * value - not the Memory class instance. + */ + cl_int setDestructorCallback( + void (CL_CALLBACK * pfn_notify)(cl_mem, void *), + void * user_data = NULL) + { + return detail::errHandler( + ::clSetMemObjectDestructorCallback( + object_, + pfn_notify, + user_data), + __SET_MEM_OBJECT_DESTRUCTOR_CALLBACK_ERR); + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 110 + +}; + +// Pre-declare copy functions +class Buffer; +template< typename IteratorType > +cl_int copy( IteratorType startIterator, IteratorType endIterator, cl::Buffer &buffer ); +template< typename IteratorType > +cl_int copy( const cl::Buffer &buffer, IteratorType startIterator, IteratorType endIterator ); +template< typename IteratorType > +cl_int copy( const CommandQueue &queue, IteratorType startIterator, IteratorType endIterator, cl::Buffer &buffer ); +template< typename IteratorType > +cl_int copy( const CommandQueue &queue, const cl::Buffer &buffer, IteratorType startIterator, IteratorType endIterator ); + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +namespace detail +{ + class SVMTraitNull + { + public: + static cl_svm_mem_flags getSVMMemFlags() + { + return 0; + } + }; +} // namespace detail + +template +class SVMTraitReadWrite +{ +public: + static cl_svm_mem_flags getSVMMemFlags() + { + return CL_MEM_READ_WRITE | + Trait::getSVMMemFlags(); + } +}; + +template +class SVMTraitReadOnly +{ +public: + static cl_svm_mem_flags getSVMMemFlags() + { + return CL_MEM_READ_ONLY | + Trait::getSVMMemFlags(); + } +}; + +template +class SVMTraitWriteOnly +{ +public: + static cl_svm_mem_flags getSVMMemFlags() + { + return CL_MEM_WRITE_ONLY | + Trait::getSVMMemFlags(); + } +}; + +template> +class SVMTraitCoarse +{ +public: + static cl_svm_mem_flags getSVMMemFlags() + { + return Trait::getSVMMemFlags(); + } +}; + +template> +class SVMTraitFine +{ +public: + static cl_svm_mem_flags getSVMMemFlags() + { + return CL_MEM_SVM_FINE_GRAIN_BUFFER | + Trait::getSVMMemFlags(); + } +}; + +template> +class SVMTraitAtomic +{ +public: + static cl_svm_mem_flags getSVMMemFlags() + { + return + CL_MEM_SVM_FINE_GRAIN_BUFFER | + CL_MEM_SVM_ATOMICS | + Trait::getSVMMemFlags(); + } +}; + +// Pre-declare SVM map function +template +inline cl_int enqueueMapSVM( + T* ptr, + cl_bool blocking, + cl_map_flags flags, + size_type size, + const vector* events = NULL, + Event* event = NULL); + +/** + * STL-like allocator class for managing SVM objects provided for convenience. + * + * Note that while this behaves like an allocator for the purposes of constructing vectors and similar objects, + * care must be taken when using with smart pointers. + * The allocator should not be used to construct a unique_ptr if we are using coarse-grained SVM mode because + * the coarse-grained management behaviour would behave incorrectly with respect to reference counting. + * + * Instead the allocator embeds a Deleter which may be used with unique_ptr and is used + * with the allocate_shared and allocate_ptr supplied operations. + */ +template +class SVMAllocator { +private: + Context context_; + +public: + typedef T value_type; + typedef value_type* pointer; + typedef const value_type* const_pointer; + typedef value_type& reference; + typedef const value_type& const_reference; + typedef std::size_t size_type; + typedef std::ptrdiff_t difference_type; + + template + struct rebind + { + typedef SVMAllocator other; + }; + + template + friend class SVMAllocator; + + SVMAllocator() : + context_(Context::getDefault()) + { + } + + explicit SVMAllocator(cl::Context context) : + context_(context) + { + } + + + SVMAllocator(const SVMAllocator &other) : + context_(other.context_) + { + } + + template + SVMAllocator(const SVMAllocator &other) : + context_(other.context_) + { + } + + ~SVMAllocator() + { + } + + pointer address(reference r) CL_HPP_NOEXCEPT_ + { + return std::addressof(r); + } + + const_pointer address(const_reference r) CL_HPP_NOEXCEPT_ + { + return std::addressof(r); + } + + /** + * Allocate an SVM pointer. + * + * If the allocator is coarse-grained, this will take ownership to allow + * containers to correctly construct data in place. + */ + pointer allocate( + size_type size, + typename cl::SVMAllocator::const_pointer = 0) + { + // Allocate memory with default alignment matching the size of the type + void* voidPointer = + clSVMAlloc( + context_(), + SVMTrait::getSVMMemFlags(), + size*sizeof(T), + 0); + pointer retValue = reinterpret_cast( + voidPointer); +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + if (!retValue) { + std::bad_alloc excep; + throw excep; + } +#endif // #if defined(CL_HPP_ENABLE_EXCEPTIONS) + + // If allocation was coarse-grained then map it + if (!(SVMTrait::getSVMMemFlags() & CL_MEM_SVM_FINE_GRAIN_BUFFER)) { + cl_int err = enqueueMapSVM(retValue, CL_TRUE, CL_MAP_READ | CL_MAP_WRITE, size*sizeof(T)); + if (err != CL_SUCCESS) { + std::bad_alloc excep; + throw excep; + } + } + + // If exceptions disabled, return null pointer from allocator + return retValue; + } + + void deallocate(pointer p, size_type) + { + clSVMFree(context_(), p); + } + + /** + * Return the maximum possible allocation size. + * This is the minimum of the maximum sizes of all devices in the context. + */ + size_type max_size() const CL_HPP_NOEXCEPT_ + { + size_type maxSize = std::numeric_limits::max() / sizeof(T); + + for (const Device &d : context_.getInfo()) { + maxSize = std::min( + maxSize, + static_cast(d.getInfo())); + } + + return maxSize; + } + + template< class U, class... Args > + void construct(U* p, Args&&... args) + { + new(p)T(args...); + } + + template< class U > + void destroy(U* p) + { + p->~U(); + } + + /** + * Returns true if the contexts match. + */ + inline bool operator==(SVMAllocator const& rhs) + { + return (context_==rhs.context_); + } + + inline bool operator!=(SVMAllocator const& a) + { + return !operator==(a); + } +}; // class SVMAllocator return cl::pointer(tmp, detail::Deleter{alloc, copies}); + + +template +class SVMAllocator { +public: + typedef void value_type; + typedef value_type* pointer; + typedef const value_type* const_pointer; + + template + struct rebind + { + typedef SVMAllocator other; + }; + + template + friend class SVMAllocator; +}; + +#if !defined(CL_HPP_NO_STD_UNIQUE_PTR) +namespace detail +{ + template + class Deleter { + private: + Alloc alloc_; + size_type copies_; + + public: + typedef typename std::allocator_traits::pointer pointer; + + Deleter(const Alloc &alloc, size_type copies) : alloc_{ alloc }, copies_{ copies } + { + } + + void operator()(pointer ptr) const { + Alloc tmpAlloc{ alloc_ }; + std::allocator_traits::destroy(tmpAlloc, std::addressof(*ptr)); + std::allocator_traits::deallocate(tmpAlloc, ptr, copies_); + } + }; +} // namespace detail + +/** + * Allocation operation compatible with std::allocate_ptr. + * Creates a unique_ptr by default. + * This requirement is to ensure that the control block is not + * allocated in memory inaccessible to the host. + */ +template +cl::pointer> allocate_pointer(const Alloc &alloc_, Args&&... args) +{ + Alloc alloc(alloc_); + static const size_type copies = 1; + + // Ensure that creation of the management block and the + // object are dealt with separately such that we only provide a deleter + + T* tmp = std::allocator_traits::allocate(alloc, copies); + if (!tmp) { + std::bad_alloc excep; + throw excep; + } + try { + std::allocator_traits::construct( + alloc, + std::addressof(*tmp), + std::forward(args)...); + + return cl::pointer>(tmp, detail::Deleter{alloc, copies}); + } + catch (std::bad_alloc b) + { + std::allocator_traits::deallocate(alloc, tmp, copies); + throw; + } +} + +template< class T, class SVMTrait, class... Args > +cl::pointer>> allocate_svm(Args... args) +{ + SVMAllocator alloc; + return cl::allocate_pointer(alloc, args...); +} + +template< class T, class SVMTrait, class... Args > +cl::pointer>> allocate_svm(const cl::Context &c, Args... args) +{ + SVMAllocator alloc(c); + return cl::allocate_pointer(alloc, args...); +} +#endif // #if !defined(CL_HPP_NO_STD_UNIQUE_PTR) + +/*! \brief Vector alias to simplify contruction of coarse-grained SVM containers. + * + */ +template < class T > +using coarse_svm_vector = vector>>; + +/*! \brief Vector alias to simplify contruction of fine-grained SVM containers. +* +*/ +template < class T > +using fine_svm_vector = vector>>; + +/*! \brief Vector alias to simplify contruction of fine-grained SVM containers that support platform atomics. +* +*/ +template < class T > +using atomic_svm_vector = vector>>; + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + + +/*! \brief Class interface for Buffer Memory Objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Buffer : public Memory +{ +public: + + /*! \brief Constructs a Buffer in a specified context. + * + * Wraps clCreateBuffer(). + * + * \param host_ptr Storage to be used if the CL_MEM_USE_HOST_PTR flag was + * specified. Note alignment & exclusivity requirements. + */ + Buffer( + const Context& context, + cl_mem_flags flags, + size_type size, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + object_ = ::clCreateBuffer(context(), flags, size, host_ptr, &error); + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Constructs a Buffer in the default context. + * + * Wraps clCreateBuffer(). + * + * \param host_ptr Storage to be used if the CL_MEM_USE_HOST_PTR flag was + * specified. Note alignment & exclusivity requirements. + * + * \see Context::getDefault() + */ + Buffer( + cl_mem_flags flags, + size_type size, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + + Context context = Context::getDefault(err); + + object_ = ::clCreateBuffer(context(), flags, size, host_ptr, &error); + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! + * \brief Construct a Buffer from a host container via iterators. + * IteratorType must be random access. + * If useHostPtr is specified iterators must represent contiguous data. + */ + template< typename IteratorType > + Buffer( + IteratorType startIterator, + IteratorType endIterator, + bool readOnly, + bool useHostPtr = false, + cl_int* err = NULL) + { + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + cl_mem_flags flags = 0; + if( readOnly ) { + flags |= CL_MEM_READ_ONLY; + } + else { + flags |= CL_MEM_READ_WRITE; + } + if( useHostPtr ) { + flags |= CL_MEM_USE_HOST_PTR; + } + + size_type size = sizeof(DataType)*(endIterator - startIterator); + + Context context = Context::getDefault(err); + + if( useHostPtr ) { + object_ = ::clCreateBuffer(context(), flags, size, static_cast(&*startIterator), &error); + } else { + object_ = ::clCreateBuffer(context(), flags, size, 0, &error); + } + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + if( !useHostPtr ) { + error = cl::copy(startIterator, endIterator, *this); + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + } + + /*! + * \brief Construct a Buffer from a host container via iterators using a specified context. + * IteratorType must be random access. + * If useHostPtr is specified iterators must represent contiguous data. + */ + template< typename IteratorType > + Buffer(const Context &context, IteratorType startIterator, IteratorType endIterator, + bool readOnly, bool useHostPtr = false, cl_int* err = NULL); + + /*! + * \brief Construct a Buffer from a host container via iterators using a specified queue. + * If useHostPtr is specified iterators must be random access. + */ + template< typename IteratorType > + Buffer(const CommandQueue &queue, IteratorType startIterator, IteratorType endIterator, + bool readOnly, bool useHostPtr = false, cl_int* err = NULL); + + //! \brief Default constructor - initializes to NULL. + Buffer() : Memory() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with earlier versions. + * + * See Memory for further details. + */ + explicit Buffer(const cl_mem& buffer, bool retainObject = false) : + Memory(buffer, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Buffer& operator = (const cl_mem& rhs) + { + Memory::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Buffer(const Buffer& buf) : Memory(buf) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Buffer& operator = (const Buffer &buf) + { + Memory::operator=(buf); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Buffer(Buffer&& buf) CL_HPP_NOEXCEPT_ : Memory(std::move(buf)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Buffer& operator = (Buffer &&buf) + { + Memory::operator=(std::move(buf)); + return *this; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 + /*! \brief Creates a new buffer object from this. + * + * Wraps clCreateSubBuffer(). + */ + Buffer createSubBuffer( + cl_mem_flags flags, + cl_buffer_create_type buffer_create_type, + const void * buffer_create_info, + cl_int * err = NULL) + { + Buffer result; + cl_int error; + result.object_ = ::clCreateSubBuffer( + object_, + flags, + buffer_create_type, + buffer_create_info, + &error); + + detail::errHandler(error, __CREATE_SUBBUFFER_ERR); + if (err != NULL) { + *err = error; + } + + return result; + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 110 +}; + +#if defined (CL_HPP_USE_DX_INTEROP) +/*! \brief Class interface for creating OpenCL buffers from ID3D10Buffer's. + * + * This is provided to facilitate interoperability with Direct3D. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class BufferD3D10 : public Buffer +{ +public: + + + /*! \brief Constructs a BufferD3D10, in a specified context, from a + * given ID3D10Buffer. + * + * Wraps clCreateFromD3D10BufferKHR(). + */ + BufferD3D10( + const Context& context, + cl_mem_flags flags, + ID3D10Buffer* bufobj, + cl_int * err = NULL) : pfn_clCreateFromD3D10BufferKHR(nullptr) + { + typedef CL_API_ENTRY cl_mem (CL_API_CALL *PFN_clCreateFromD3D10BufferKHR)( + cl_context context, cl_mem_flags flags, ID3D10Buffer* buffer, + cl_int* errcode_ret); + PFN_clCreateFromD3D10BufferKHR pfn_clCreateFromD3D10BufferKHR; +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + vector props = context.getInfo(); + cl_platform platform = -1; + for( int i = 0; i < props.size(); ++i ) { + if( props[i] == CL_CONTEXT_PLATFORM ) { + platform = props[i+1]; + } + } + CL_HPP_INIT_CL_EXT_FCN_PTR_PLATFORM_(platform, clCreateFromD3D10BufferKHR); +#elif CL_HPP_TARGET_OPENCL_VERSION >= 110 + CL_HPP_INIT_CL_EXT_FCN_PTR_(clCreateFromD3D10BufferKHR); +#endif + + cl_int error; + object_ = pfn_clCreateFromD3D10BufferKHR( + context(), + flags, + bufobj, + &error); + + detail::errHandler(error, __CREATE_GL_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + BufferD3D10() : Buffer() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit BufferD3D10(const cl_mem& buffer, bool retainObject = false) : + Buffer(buffer, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + BufferD3D10& operator = (const cl_mem& rhs) + { + Buffer::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + BufferD3D10(const BufferD3D10& buf) : + Buffer(buf) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + BufferD3D10& operator = (const BufferD3D10 &buf) + { + Buffer::operator=(buf); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + BufferD3D10(BufferD3D10&& buf) CL_HPP_NOEXCEPT_ : Buffer(std::move(buf)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + BufferD3D10& operator = (BufferD3D10 &&buf) + { + Buffer::operator=(std::move(buf)); + return *this; + } +}; +#endif + +/*! \brief Class interface for GL Buffer Memory Objects. + * + * This is provided to facilitate interoperability with OpenGL. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class BufferGL : public Buffer +{ +public: + /*! \brief Constructs a BufferGL in a specified context, from a given + * GL buffer. + * + * Wraps clCreateFromGLBuffer(). + */ + BufferGL( + const Context& context, + cl_mem_flags flags, + cl_GLuint bufobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLBuffer( + context(), + flags, + bufobj, + &error); + + detail::errHandler(error, __CREATE_GL_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + BufferGL() : Buffer() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit BufferGL(const cl_mem& buffer, bool retainObject = false) : + Buffer(buffer, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + BufferGL& operator = (const cl_mem& rhs) + { + Buffer::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + BufferGL(const BufferGL& buf) : Buffer(buf) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + BufferGL& operator = (const BufferGL &buf) + { + Buffer::operator=(buf); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + BufferGL(BufferGL&& buf) CL_HPP_NOEXCEPT_ : Buffer(std::move(buf)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + BufferGL& operator = (BufferGL &&buf) + { + Buffer::operator=(std::move(buf)); + return *this; + } + + //! \brief Wrapper for clGetGLObjectInfo(). + cl_int getObjectInfo( + cl_gl_object_type *type, + cl_GLuint * gl_object_name) + { + return detail::errHandler( + ::clGetGLObjectInfo(object_,type,gl_object_name), + __GET_GL_OBJECT_INFO_ERR); + } +}; + +/*! \brief Class interface for GL Render Buffer Memory Objects. + * + * This is provided to facilitate interoperability with OpenGL. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class BufferRenderGL : public Buffer +{ +public: + /*! \brief Constructs a BufferRenderGL in a specified context, from a given + * GL Renderbuffer. + * + * Wraps clCreateFromGLRenderbuffer(). + */ + BufferRenderGL( + const Context& context, + cl_mem_flags flags, + cl_GLuint bufobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLRenderbuffer( + context(), + flags, + bufobj, + &error); + + detail::errHandler(error, __CREATE_GL_RENDER_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + BufferRenderGL() : Buffer() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit BufferRenderGL(const cl_mem& buffer, bool retainObject = false) : + Buffer(buffer, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + BufferRenderGL& operator = (const cl_mem& rhs) + { + Buffer::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + BufferRenderGL(const BufferRenderGL& buf) : Buffer(buf) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + BufferRenderGL& operator = (const BufferRenderGL &buf) + { + Buffer::operator=(buf); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + BufferRenderGL(BufferRenderGL&& buf) CL_HPP_NOEXCEPT_ : Buffer(std::move(buf)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + BufferRenderGL& operator = (BufferRenderGL &&buf) + { + Buffer::operator=(std::move(buf)); + return *this; + } + + //! \brief Wrapper for clGetGLObjectInfo(). + cl_int getObjectInfo( + cl_gl_object_type *type, + cl_GLuint * gl_object_name) + { + return detail::errHandler( + ::clGetGLObjectInfo(object_,type,gl_object_name), + __GET_GL_OBJECT_INFO_ERR); + } +}; + +/*! \brief C++ base class for Image Memory objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image : public Memory +{ +protected: + //! \brief Default constructor - initializes to NULL. + Image() : Memory() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image(const cl_mem& image, bool retainObject = false) : + Memory(image, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image& operator = (const cl_mem& rhs) + { + Memory::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image(const Image& img) : Memory(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image& operator = (const Image &img) + { + Memory::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image(Image&& img) CL_HPP_NOEXCEPT_ : Memory(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image& operator = (Image &&img) + { + Memory::operator=(std::move(img)); + return *this; + } + + +public: + //! \brief Wrapper for clGetImageInfo(). + template + cl_int getImageInfo(cl_image_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetImageInfo, object_, name, param), + __GET_IMAGE_INFO_ERR); + } + + //! \brief Wrapper for clGetImageInfo() that returns by value. + template typename + detail::param_traits::param_type + getImageInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_image_info, name>::param_type param; + cl_int result = getImageInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } +}; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +/*! \brief Class interface for 1D Image Memory objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image1D : public Image +{ +public: + /*! \brief Constructs a 1D Image in a specified context. + * + * Wraps clCreateImage(). + */ + Image1D( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + size_type width, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE1D, + width, + 0, 0, 0, 0, 0, 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + Image1D() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image1D(const cl_mem& image1D, bool retainObject = false) : + Image(image1D, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image1D& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image1D(const Image1D& img) : Image(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image1D& operator = (const Image1D &img) + { + Image::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image1D(Image1D&& img) CL_HPP_NOEXCEPT_ : Image(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image1D& operator = (Image1D &&img) + { + Image::operator=(std::move(img)); + return *this; + } + +}; + +/*! \class Image1DBuffer + * \brief Image interface for 1D buffer images. + */ +class Image1DBuffer : public Image +{ +public: + Image1DBuffer( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + size_type width, + const Buffer &buffer, + cl_int* err = NULL) + { + cl_int error; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE1D_BUFFER, + width, + 0, 0, 0, 0, 0, 0, 0, + buffer() + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + NULL, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } + + Image1DBuffer() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image1DBuffer(const cl_mem& image1D, bool retainObject = false) : + Image(image1D, retainObject) { } + + Image1DBuffer& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image1DBuffer(const Image1DBuffer& img) : Image(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image1DBuffer& operator = (const Image1DBuffer &img) + { + Image::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image1DBuffer(Image1DBuffer&& img) CL_HPP_NOEXCEPT_ : Image(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image1DBuffer& operator = (Image1DBuffer &&img) + { + Image::operator=(std::move(img)); + return *this; + } + +}; + +/*! \class Image1DArray + * \brief Image interface for arrays of 1D images. + */ +class Image1DArray : public Image +{ +public: + Image1DArray( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + size_type arraySize, + size_type width, + size_type rowPitch, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE1D_ARRAY, + width, + 0, 0, // height, depth (unused) + arraySize, + rowPitch, + 0, 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } + + Image1DArray() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image1DArray(const cl_mem& imageArray, bool retainObject = false) : + Image(imageArray, retainObject) { } + + + Image1DArray& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image1DArray(const Image1DArray& img) : Image(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image1DArray& operator = (const Image1DArray &img) + { + Image::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image1DArray(Image1DArray&& img) CL_HPP_NOEXCEPT_ : Image(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image1DArray& operator = (Image1DArray &&img) + { + Image::operator=(std::move(img)); + return *this; + } + +}; +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 120 + + +/*! \brief Class interface for 2D Image Memory objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image2D : public Image +{ +public: + /*! \brief Constructs a 2D Image in a specified context. + * + * Wraps clCreateImage(). + */ + Image2D( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + size_type width, + size_type height, + size_type row_pitch = 0, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + bool useCreateImage; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 && CL_HPP_MINIMUM_OPENCL_VERSION < 120 + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useCreateImage = (version >= 0x10002); // OpenCL 1.2 or above + } +#elif CL_HPP_TARGET_OPENCL_VERSION >= 120 + useCreateImage = true; +#else + useCreateImage = false; +#endif + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + if (useCreateImage) + { + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE2D, + width, + height, + 0, 0, // depth, array size (unused) + row_pitch, + 0, 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 120 + if (!useCreateImage) + { + object_ = ::clCreateImage2D( + context(), flags,&format, width, height, row_pitch, host_ptr, &error); + + detail::errHandler(error, __CREATE_IMAGE2D_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 120 + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 || defined(CL_HPP_USE_CL_IMAGE2D_FROM_BUFFER_KHR) + /*! \brief Constructs a 2D Image from a buffer. + * \note This will share storage with the underlying buffer. + * + * Wraps clCreateImage(). + */ + Image2D( + const Context& context, + ImageFormat format, + const Buffer &sourceBuffer, + size_type width, + size_type height, + size_type row_pitch = 0, + cl_int* err = nullptr) + { + cl_int error; + + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE2D, + width, + height, + 0, 0, // depth, array size (unused) + row_pitch, + 0, 0, 0, + // Use buffer as input to image + sourceBuffer() + }; + object_ = ::clCreateImage( + context(), + 0, // flags inherited from buffer + &format, + &desc, + nullptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != nullptr) { + *err = error; + } + } +#endif //#if CL_HPP_TARGET_OPENCL_VERSION >= 200 || defined(CL_HPP_USE_CL_IMAGE2D_FROM_BUFFER_KHR) + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + /*! \brief Constructs a 2D Image from an image. + * \note This will share storage with the underlying image but may + * reinterpret the channel order and type. + * + * The image will be created matching with a descriptor matching the source. + * + * \param order is the channel order to reinterpret the image data as. + * The channel order may differ as described in the OpenCL + * 2.0 API specification. + * + * Wraps clCreateImage(). + */ + Image2D( + const Context& context, + cl_channel_order order, + const Image &sourceImage, + cl_int* err = nullptr) + { + cl_int error; + + // Descriptor fields have to match source image + size_type sourceWidth = + sourceImage.getImageInfo(); + size_type sourceHeight = + sourceImage.getImageInfo(); + size_type sourceRowPitch = + sourceImage.getImageInfo(); + cl_uint sourceNumMIPLevels = + sourceImage.getImageInfo(); + cl_uint sourceNumSamples = + sourceImage.getImageInfo(); + cl_image_format sourceFormat = + sourceImage.getImageInfo(); + + // Update only the channel order. + // Channel format inherited from source. + sourceFormat.image_channel_order = order; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE2D, + sourceWidth, + sourceHeight, + 0, 0, // depth (unused), array size (unused) + sourceRowPitch, + 0, // slice pitch (unused) + sourceNumMIPLevels, + sourceNumSamples, + // Use buffer as input to image + sourceImage() + }; + object_ = ::clCreateImage( + context(), + 0, // flags should be inherited from mem_object + &sourceFormat, + &desc, + nullptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != nullptr) { + *err = error; + } + } +#endif //#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + + //! \brief Default constructor - initializes to NULL. + Image2D() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image2D(const cl_mem& image2D, bool retainObject = false) : + Image(image2D, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image2D& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image2D(const Image2D& img) : Image(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image2D& operator = (const Image2D &img) + { + Image::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image2D(Image2D&& img) CL_HPP_NOEXCEPT_ : Image(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image2D& operator = (Image2D &&img) + { + Image::operator=(std::move(img)); + return *this; + } + +}; + + +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +/*! \brief Class interface for GL 2D Image Memory objects. + * + * This is provided to facilitate interoperability with OpenGL. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + * \note Deprecated for OpenCL 1.2. Please use ImageGL instead. + */ +class CL_EXT_PREFIX__VERSION_1_1_DEPRECATED Image2DGL : public Image2D +{ +public: + /*! \brief Constructs an Image2DGL in a specified context, from a given + * GL Texture. + * + * Wraps clCreateFromGLTexture2D(). + */ + Image2DGL( + const Context& context, + cl_mem_flags flags, + cl_GLenum target, + cl_GLint miplevel, + cl_GLuint texobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLTexture2D( + context(), + flags, + target, + miplevel, + texobj, + &error); + + detail::errHandler(error, __CREATE_GL_TEXTURE_2D_ERR); + if (err != NULL) { + *err = error; + } + + } + + //! \brief Default constructor - initializes to NULL. + Image2DGL() : Image2D() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image2DGL(const cl_mem& image, bool retainObject = false) : + Image2D(image, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + *c + * See Memory for further details. + */ + Image2DGL& operator = (const cl_mem& rhs) + { + Image2D::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image2DGL(const Image2DGL& img) : Image2D(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image2DGL& operator = (const Image2DGL &img) + { + Image2D::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image2DGL(Image2DGL&& img) CL_HPP_NOEXCEPT_ : Image2D(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image2DGL& operator = (Image2DGL &&img) + { + Image2D::operator=(std::move(img)); + return *this; + } + +} CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; +#endif // CL_USE_DEPRECATED_OPENCL_1_1_APIS + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +/*! \class Image2DArray + * \brief Image interface for arrays of 2D images. + */ +class Image2DArray : public Image +{ +public: + Image2DArray( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + size_type arraySize, + size_type width, + size_type height, + size_type rowPitch, + size_type slicePitch, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE2D_ARRAY, + width, + height, + 0, // depth (unused) + arraySize, + rowPitch, + slicePitch, + 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } + + Image2DArray() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image2DArray(const cl_mem& imageArray, bool retainObject = false) : Image(imageArray, retainObject) { } + + Image2DArray& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image2DArray(const Image2DArray& img) : Image(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image2DArray& operator = (const Image2DArray &img) + { + Image::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image2DArray(Image2DArray&& img) CL_HPP_NOEXCEPT_ : Image(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image2DArray& operator = (Image2DArray &&img) + { + Image::operator=(std::move(img)); + return *this; + } +}; +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 120 + +/*! \brief Class interface for 3D Image Memory objects. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image3D : public Image +{ +public: + /*! \brief Constructs a 3D Image in a specified context. + * + * Wraps clCreateImage(). + */ + Image3D( + const Context& context, + cl_mem_flags flags, + ImageFormat format, + size_type width, + size_type height, + size_type depth, + size_type row_pitch = 0, + size_type slice_pitch = 0, + void* host_ptr = NULL, + cl_int* err = NULL) + { + cl_int error; + bool useCreateImage; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 && CL_HPP_MINIMUM_OPENCL_VERSION < 120 + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useCreateImage = (version >= 0x10002); // OpenCL 1.2 or above + } +#elif CL_HPP_TARGET_OPENCL_VERSION >= 120 + useCreateImage = true; +#else + useCreateImage = false; +#endif + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + if (useCreateImage) + { + cl_image_desc desc = + { + CL_MEM_OBJECT_IMAGE3D, + width, + height, + depth, + 0, // array size (unused) + row_pitch, + slice_pitch, + 0, 0, 0 + }; + object_ = ::clCreateImage( + context(), + flags, + &format, + &desc, + host_ptr, + &error); + + detail::errHandler(error, __CREATE_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 120 + if (!useCreateImage) + { + object_ = ::clCreateImage3D( + context(), flags, &format, width, height, depth, row_pitch, + slice_pitch, host_ptr, &error); + + detail::errHandler(error, __CREATE_IMAGE3D_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 120 + } + + //! \brief Default constructor - initializes to NULL. + Image3D() : Image() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image3D(const cl_mem& image3D, bool retainObject = false) : + Image(image3D, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image3D& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image3D(const Image3D& img) : Image(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image3D& operator = (const Image3D &img) + { + Image::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image3D(Image3D&& img) CL_HPP_NOEXCEPT_ : Image(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image3D& operator = (Image3D &&img) + { + Image::operator=(std::move(img)); + return *this; + } +}; + +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +/*! \brief Class interface for GL 3D Image Memory objects. + * + * This is provided to facilitate interoperability with OpenGL. + * + * See Memory for details about copy semantics, etc. + * + * \see Memory + */ +class Image3DGL : public Image3D +{ +public: + /*! \brief Constructs an Image3DGL in a specified context, from a given + * GL Texture. + * + * Wraps clCreateFromGLTexture3D(). + */ + Image3DGL( + const Context& context, + cl_mem_flags flags, + cl_GLenum target, + cl_GLint miplevel, + cl_GLuint texobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLTexture3D( + context(), + flags, + target, + miplevel, + texobj, + &error); + + detail::errHandler(error, __CREATE_GL_TEXTURE_3D_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + Image3DGL() : Image3D() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit Image3DGL(const cl_mem& image, bool retainObject = false) : + Image3D(image, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Image3DGL& operator = (const cl_mem& rhs) + { + Image3D::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image3DGL(const Image3DGL& img) : Image3D(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Image3DGL& operator = (const Image3DGL &img) + { + Image3D::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Image3DGL(Image3DGL&& img) CL_HPP_NOEXCEPT_ : Image3D(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Image3DGL& operator = (Image3DGL &&img) + { + Image3D::operator=(std::move(img)); + return *this; + } +}; +#endif // CL_USE_DEPRECATED_OPENCL_1_1_APIS + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +/*! \class ImageGL + * \brief general image interface for GL interop. + * We abstract the 2D and 3D GL images into a single instance here + * that wraps all GL sourced images on the grounds that setup information + * was performed by OpenCL anyway. + */ +class ImageGL : public Image +{ +public: + ImageGL( + const Context& context, + cl_mem_flags flags, + cl_GLenum target, + cl_GLint miplevel, + cl_GLuint texobj, + cl_int * err = NULL) + { + cl_int error; + object_ = ::clCreateFromGLTexture( + context(), + flags, + target, + miplevel, + texobj, + &error); + + detail::errHandler(error, __CREATE_GL_TEXTURE_ERR); + if (err != NULL) { + *err = error; + } + } + + ImageGL() : Image() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * See Memory for further details. + */ + explicit ImageGL(const cl_mem& image, bool retainObject = false) : + Image(image, retainObject) { } + + ImageGL& operator = (const cl_mem& rhs) + { + Image::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + ImageGL(const ImageGL& img) : Image(img) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + ImageGL& operator = (const ImageGL &img) + { + Image::operator=(img); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + ImageGL(ImageGL&& img) CL_HPP_NOEXCEPT_ : Image(std::move(img)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + ImageGL& operator = (ImageGL &&img) + { + Image::operator=(std::move(img)); + return *this; + } +}; +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +/*! \brief Class interface for Pipe Memory Objects. +* +* See Memory for details about copy semantics, etc. +* +* \see Memory +*/ +class Pipe : public Memory +{ +public: + + /*! \brief Constructs a Pipe in a specified context. + * + * Wraps clCreatePipe(). + * @param context Context in which to create the pipe. + * @param flags Bitfield. Only CL_MEM_READ_WRITE and CL_MEM_HOST_NO_ACCESS are valid. + * @param packet_size Size in bytes of a single packet of the pipe. + * @param max_packets Number of packets that may be stored in the pipe. + * + */ + Pipe( + const Context& context, + cl_uint packet_size, + cl_uint max_packets, + cl_int* err = NULL) + { + cl_int error; + + cl_mem_flags flags = CL_MEM_READ_WRITE | CL_MEM_HOST_NO_ACCESS; + object_ = ::clCreatePipe(context(), flags, packet_size, max_packets, nullptr, &error); + + detail::errHandler(error, __CREATE_PIPE_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Constructs a Pipe in a the default context. + * + * Wraps clCreatePipe(). + * @param flags Bitfield. Only CL_MEM_READ_WRITE and CL_MEM_HOST_NO_ACCESS are valid. + * @param packet_size Size in bytes of a single packet of the pipe. + * @param max_packets Number of packets that may be stored in the pipe. + * + */ + Pipe( + cl_uint packet_size, + cl_uint max_packets, + cl_int* err = NULL) + { + cl_int error; + + Context context = Context::getDefault(err); + + cl_mem_flags flags = CL_MEM_READ_WRITE | CL_MEM_HOST_NO_ACCESS; + object_ = ::clCreatePipe(context(), flags, packet_size, max_packets, nullptr, &error); + + detail::errHandler(error, __CREATE_PIPE_ERR); + if (err != NULL) { + *err = error; + } + } + + //! \brief Default constructor - initializes to NULL. + Pipe() : Memory() { } + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with earlier versions. + * + * See Memory for further details. + */ + explicit Pipe(const cl_mem& pipe, bool retainObject = false) : + Memory(pipe, retainObject) { } + + /*! \brief Assignment from cl_mem - performs shallow copy. + * + * See Memory for further details. + */ + Pipe& operator = (const cl_mem& rhs) + { + Memory::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Pipe(const Pipe& pipe) : Memory(pipe) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Pipe& operator = (const Pipe &pipe) + { + Memory::operator=(pipe); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Pipe(Pipe&& pipe) CL_HPP_NOEXCEPT_ : Memory(std::move(pipe)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Pipe& operator = (Pipe &&pipe) + { + Memory::operator=(std::move(pipe)); + return *this; + } + + //! \brief Wrapper for clGetMemObjectInfo(). + template + cl_int getInfo(cl_pipe_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetPipeInfo, object_, name, param), + __GET_PIPE_INFO_ERR); + } + + //! \brief Wrapper for clGetMemObjectInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_pipe_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } +}; // class Pipe +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 + + +/*! \brief Class interface for cl_sampler. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_sampler as the original. For details, see + * clRetainSampler() and clReleaseSampler(). + * + * \see cl_sampler + */ +class Sampler : public detail::Wrapper +{ +public: + //! \brief Default constructor - initializes to NULL. + Sampler() { } + + /*! \brief Constructs a Sampler in a specified context. + * + * Wraps clCreateSampler(). + */ + Sampler( + const Context& context, + cl_bool normalized_coords, + cl_addressing_mode addressing_mode, + cl_filter_mode filter_mode, + cl_int* err = NULL) + { + cl_int error; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + cl_sampler_properties sampler_properties[] = { + CL_SAMPLER_NORMALIZED_COORDS, normalized_coords, + CL_SAMPLER_ADDRESSING_MODE, addressing_mode, + CL_SAMPLER_FILTER_MODE, filter_mode, + 0 }; + object_ = ::clCreateSamplerWithProperties( + context(), + sampler_properties, + &error); + + detail::errHandler(error, __CREATE_SAMPLER_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } +#else + object_ = ::clCreateSampler( + context(), + normalized_coords, + addressing_mode, + filter_mode, + &error); + + detail::errHandler(error, __CREATE_SAMPLER_ERR); + if (err != NULL) { + *err = error; + } +#endif + } + + /*! \brief Constructor from cl_sampler - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * This effectively transfers ownership of a refcount on the cl_sampler + * into the new Sampler object. + */ + explicit Sampler(const cl_sampler& sampler, bool retainObject = false) : + detail::Wrapper(sampler, retainObject) { } + + /*! \brief Assignment operator from cl_sampler - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseSampler() on the value previously held by this instance. + */ + Sampler& operator = (const cl_sampler& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Sampler(const Sampler& sam) : detail::Wrapper(sam) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Sampler& operator = (const Sampler &sam) + { + detail::Wrapper::operator=(sam); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Sampler(Sampler&& sam) CL_HPP_NOEXCEPT_ : detail::Wrapper(std::move(sam)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Sampler& operator = (Sampler &&sam) + { + detail::Wrapper::operator=(std::move(sam)); + return *this; + } + + //! \brief Wrapper for clGetSamplerInfo(). + template + cl_int getInfo(cl_sampler_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetSamplerInfo, object_, name, param), + __GET_SAMPLER_INFO_ERR); + } + + //! \brief Wrapper for clGetSamplerInfo() that returns by value. + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_sampler_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } +}; + +class Program; +class CommandQueue; +class DeviceCommandQueue; +class Kernel; + +//! \brief Class interface for specifying NDRange values. +class NDRange +{ +private: + size_type sizes_[3]; + cl_uint dimensions_; + +public: + //! \brief Default constructor - resulting range has zero dimensions. + NDRange() + : dimensions_(0) + { + sizes_[0] = 0; + sizes_[1] = 0; + sizes_[2] = 0; + } + + //! \brief Constructs one-dimensional range. + NDRange(size_type size0) + : dimensions_(1) + { + sizes_[0] = size0; + sizes_[1] = 1; + sizes_[2] = 1; + } + + //! \brief Constructs two-dimensional range. + NDRange(size_type size0, size_type size1) + : dimensions_(2) + { + sizes_[0] = size0; + sizes_[1] = size1; + sizes_[2] = 1; + } + + //! \brief Constructs three-dimensional range. + NDRange(size_type size0, size_type size1, size_type size2) + : dimensions_(3) + { + sizes_[0] = size0; + sizes_[1] = size1; + sizes_[2] = size2; + } + + /*! \brief Conversion operator to const size_type *. + * + * \returns a pointer to the size of the first dimension. + */ + operator const size_type*() const { + return sizes_; + } + + //! \brief Queries the number of dimensions in the range. + size_type dimensions() const + { + return dimensions_; + } + + //! \brief Returns the size of the object in bytes based on the + // runtime number of dimensions + size_type size() const + { + return dimensions_*sizeof(size_type); + } + + size_type* get() + { + return sizes_; + } + + const size_type* get() const + { + return sizes_; + } +}; + +//! \brief A zero-dimensional range. +static const NDRange NullRange; + +//! \brief Local address wrapper for use with Kernel::setArg +struct LocalSpaceArg +{ + size_type size_; +}; + +namespace detail { + +template +struct KernelArgumentHandler; + +// Enable for objects that are not subclasses of memory +// Pointers, constants etc +template +struct KernelArgumentHandler::value>::type> +{ + static size_type size(const T&) { return sizeof(T); } + static const T* ptr(const T& value) { return &value; } +}; + +// Enable for subclasses of memory where we want to get a reference to the cl_mem out +// and pass that in for safety +template +struct KernelArgumentHandler::value>::type> +{ + static size_type size(const T&) { return sizeof(cl_mem); } + static const cl_mem* ptr(const T& value) { return &(value()); } +}; + +// Specialization for DeviceCommandQueue defined later + +template <> +struct KernelArgumentHandler +{ + static size_type size(const LocalSpaceArg& value) { return value.size_; } + static const void* ptr(const LocalSpaceArg&) { return NULL; } +}; + +} +//! \endcond + +/*! Local + * \brief Helper function for generating LocalSpaceArg objects. + */ +inline LocalSpaceArg +Local(size_type size) +{ + LocalSpaceArg ret = { size }; + return ret; +} + +/*! \brief Class interface for cl_kernel. + * + * \note Copies of these objects are shallow, meaning that the copy will refer + * to the same underlying cl_kernel as the original. For details, see + * clRetainKernel() and clReleaseKernel(). + * + * \see cl_kernel + */ +class Kernel : public detail::Wrapper +{ +public: + inline Kernel(const Program& program, const char* name, cl_int* err = NULL); + + //! \brief Default constructor - initializes to NULL. + Kernel() { } + + /*! \brief Constructor from cl_kernel - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + * This effectively transfers ownership of a refcount on the cl_kernel + * into the new Kernel object. + */ + explicit Kernel(const cl_kernel& kernel, bool retainObject = false) : + detail::Wrapper(kernel, retainObject) { } + + /*! \brief Assignment operator from cl_kernel - takes ownership. + * + * This effectively transfers ownership of a refcount on the rhs and calls + * clReleaseKernel() on the value previously held by this instance. + */ + Kernel& operator = (const cl_kernel& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Kernel(const Kernel& kernel) : detail::Wrapper(kernel) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Kernel& operator = (const Kernel &kernel) + { + detail::Wrapper::operator=(kernel); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Kernel(Kernel&& kernel) CL_HPP_NOEXCEPT_ : detail::Wrapper(std::move(kernel)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Kernel& operator = (Kernel &&kernel) + { + detail::Wrapper::operator=(std::move(kernel)); + return *this; + } + + template + cl_int getInfo(cl_kernel_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetKernelInfo, object_, name, param), + __GET_KERNEL_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_kernel_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + template + cl_int getArgInfo(cl_uint argIndex, cl_kernel_arg_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetKernelArgInfo, object_, argIndex, name, param), + __GET_KERNEL_ARG_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getArgInfo(cl_uint argIndex, cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_kernel_arg_info, name>::param_type param; + cl_int result = getArgInfo(argIndex, name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + + template + cl_int getWorkGroupInfo( + const Device& device, cl_kernel_work_group_info name, T* param) const + { + return detail::errHandler( + detail::getInfo( + &::clGetKernelWorkGroupInfo, object_, device(), name, param), + __GET_KERNEL_WORK_GROUP_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getWorkGroupInfo(const Device& device, cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_kernel_work_group_info, name>::param_type param; + cl_int result = getWorkGroupInfo(device, name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + +#if (CL_HPP_TARGET_OPENCL_VERSION >= 200 && defined(CL_HPP_USE_CL_SUB_GROUPS_KHR)) || CL_HPP_TARGET_OPENCL_VERSION >= 210 + cl_int getSubGroupInfo(const cl::Device &dev, cl_kernel_sub_group_info name, const cl::NDRange &range, size_type* param) const + { +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + return detail::errHandler( + clGetKernelSubGroupInfo(object_, dev(), name, range.size(), range.get(), sizeof(size_type), param, nullptr), + __GET_KERNEL_SUB_GROUP_INFO_ERR); + +#else // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + typedef clGetKernelSubGroupInfoKHR_fn PFN_clGetKernelSubGroupInfoKHR; + static PFN_clGetKernelSubGroupInfoKHR pfn_clGetKernelSubGroupInfoKHR = NULL; + CL_HPP_INIT_CL_EXT_FCN_PTR_(clGetKernelSubGroupInfoKHR); + + return detail::errHandler( + pfn_clGetKernelSubGroupInfoKHR(object_, dev(), name, range.size(), range.get(), sizeof(size_type), param, nullptr), + __GET_KERNEL_SUB_GROUP_INFO_ERR); + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + } + + template + size_type getSubGroupInfo(const cl::Device &dev, const cl::NDRange &range, cl_int* err = NULL) const + { + size_type param; + cl_int result = getSubGroupInfo(dev, name, range, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + /*! \brief setArg overload taking a shared_ptr type + */ + template + cl_int setArg(cl_uint index, const cl::pointer &argPtr) + { + return detail::errHandler( + ::clSetKernelArgSVMPointer(object_, index, argPtr.get()), + __SET_KERNEL_ARGS_ERR); + } + + /*! \brief setArg overload taking a vector type. + */ + template + cl_int setArg(cl_uint index, const cl::vector &argPtr) + { + return detail::errHandler( + ::clSetKernelArgSVMPointer(object_, index, argPtr.data()), + __SET_KERNEL_ARGS_ERR); + } + + /*! \brief setArg overload taking a pointer type + */ + template + typename std::enable_if::value, cl_int>::type + setArg(cl_uint index, const T argPtr) + { + return detail::errHandler( + ::clSetKernelArgSVMPointer(object_, index, argPtr), + __SET_KERNEL_ARGS_ERR); + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + + /*! \brief setArg overload taking a POD type + */ + template + typename std::enable_if::value, cl_int>::type + setArg(cl_uint index, const T &value) + { + return detail::errHandler( + ::clSetKernelArg( + object_, + index, + detail::KernelArgumentHandler::size(value), + detail::KernelArgumentHandler::ptr(value)), + __SET_KERNEL_ARGS_ERR); + } + + cl_int setArg(cl_uint index, size_type size, const void* argPtr) + { + return detail::errHandler( + ::clSetKernelArg(object_, index, size, argPtr), + __SET_KERNEL_ARGS_ERR); + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + /*! + * Specify a vector of SVM pointers that the kernel may access in + * addition to its arguments. + */ + cl_int setSVMPointers(const vector &pointerList) + { + return detail::errHandler( + ::clSetKernelExecInfo( + object_, + CL_KERNEL_EXEC_INFO_SVM_PTRS, + sizeof(void*)*pointerList.size(), + pointerList.data())); + } + + /*! + * Specify a std::array of SVM pointers that the kernel may access in + * addition to its arguments. + */ + template + cl_int setSVMPointers(const std::array &pointerList) + { + return detail::errHandler( + ::clSetKernelExecInfo( + object_, + CL_KERNEL_EXEC_INFO_SVM_PTRS, + sizeof(void*)*pointerList.size(), + pointerList.data())); + } + + /*! \brief Enable fine-grained system SVM. + * + * \note It is only possible to enable fine-grained system SVM if all devices + * in the context associated with kernel support it. + * + * \param svmEnabled True if fine-grained system SVM is requested. False otherwise. + * \return CL_SUCCESS if the function was executed succesfully. CL_INVALID_OPERATION + * if no devices in the context support fine-grained system SVM. + * + * \see clSetKernelExecInfo + */ + cl_int enableFineGrainedSystemSVM(bool svmEnabled) + { + cl_bool svmEnabled_ = svmEnabled ? CL_TRUE : CL_FALSE; + return detail::errHandler( + ::clSetKernelExecInfo( + object_, + CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM, + sizeof(cl_bool), + &svmEnabled_ + ) + ); + } + + template + void setSVMPointersHelper(std::array &pointerList, const pointer &t0, const pointer &t1, Ts & ... ts) + { + pointerList[index] = static_cast(t0.get()); + setSVMPointersHelper(pointerList, t1, ts...); + } + + template + typename std::enable_if::value, void>::type + setSVMPointersHelper(std::array &pointerList, T0 t0, T1 t1, Ts... ts) + { + pointerList[index] = static_cast(t0); + setSVMPointersHelper(pointerList, t1, ts...); + } + + template + void setSVMPointersHelper(std::array &pointerList, const pointer &t0) + { + pointerList[index] = static_cast(t0.get()); + } + + + template + typename std::enable_if::value, void>::type + setSVMPointersHelper(std::array &pointerList, T0 t0) + { + pointerList[index] = static_cast(t0); + } + + template + cl_int setSVMPointers(const T0 &t0, Ts & ... ts) + { + std::array pointerList; + + setSVMPointersHelper<0, 1 + sizeof...(Ts)>(pointerList, t0, ts...); + return detail::errHandler( + ::clSetKernelExecInfo( + object_, + CL_KERNEL_EXEC_INFO_SVM_PTRS, + sizeof(void*)*(1 + sizeof...(Ts)), + pointerList.data())); + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 + /** + * Make a deep copy of the kernel object including its arguments. + * @return A new kernel object with internal state entirely separate from that + * of the original but with any arguments set on the original intact. + */ + Kernel clone() + { + cl_int error; + Kernel retValue(clCloneKernel(this->get(), &error)); + + detail::errHandler(error, __CLONE_KERNEL_ERR); + return retValue; + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 +}; + +/*! \class Program + * \brief Program interface that implements cl_program. + */ +class Program : public detail::Wrapper +{ +public: +#if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + typedef vector> Binaries; + typedef vector Sources; +#else // #if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + typedef vector > Binaries; + typedef vector > Sources; +#endif // #if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + + Program( + const string& source, + bool build = false, + cl_int* err = NULL) + { + cl_int error; + + const char * strings = source.c_str(); + const size_type length = source.size(); + + Context context = Context::getDefault(err); + + object_ = ::clCreateProgramWithSource( + context(), (cl_uint)1, &strings, &length, &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_SOURCE_ERR); + + if (error == CL_SUCCESS && build) { + + error = ::clBuildProgram( + object_, + 0, + NULL, +#if !defined(CL_HPP_CL_1_2_DEFAULT_BUILD) + "-cl-std=CL2.0", +#else + "", +#endif // #if !defined(CL_HPP_CL_1_2_DEFAULT_BUILD) + NULL, + NULL); + + detail::buildErrHandler(error, __BUILD_PROGRAM_ERR, getBuildInfo()); + } + + if (err != NULL) { + *err = error; + } + } + + Program( + const Context& context, + const string& source, + bool build = false, + cl_int* err = NULL) + { + cl_int error; + + const char * strings = source.c_str(); + const size_type length = source.size(); + + object_ = ::clCreateProgramWithSource( + context(), (cl_uint)1, &strings, &length, &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_SOURCE_ERR); + + if (error == CL_SUCCESS && build) { + error = ::clBuildProgram( + object_, + 0, + NULL, +#if !defined(CL_HPP_CL_1_2_DEFAULT_BUILD) + "-cl-std=CL2.0", +#else + "", +#endif // #if !defined(CL_HPP_CL_1_2_DEFAULT_BUILD) + NULL, + NULL); + + detail::buildErrHandler(error, __BUILD_PROGRAM_ERR, getBuildInfo()); + } + + if (err != NULL) { + *err = error; + } + } + + /** + * Create a program from a vector of source strings and the default context. + * Does not compile or link the program. + */ + Program( + const Sources& sources, + cl_int* err = NULL) + { + cl_int error; + Context context = Context::getDefault(err); + + const size_type n = (size_type)sources.size(); + + vector lengths(n); + vector strings(n); + + for (size_type i = 0; i < n; ++i) { +#if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + strings[i] = sources[(int)i].data(); + lengths[i] = sources[(int)i].length(); +#else // #if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + strings[i] = sources[(int)i].first; + lengths[i] = sources[(int)i].second; +#endif // #if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + } + + object_ = ::clCreateProgramWithSource( + context(), (cl_uint)n, strings.data(), lengths.data(), &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_SOURCE_ERR); + if (err != NULL) { + *err = error; + } + } + + /** + * Create a program from a vector of source strings and a provided context. + * Does not compile or link the program. + */ + Program( + const Context& context, + const Sources& sources, + cl_int* err = NULL) + { + cl_int error; + + const size_type n = (size_type)sources.size(); + + vector lengths(n); + vector strings(n); + + for (size_type i = 0; i < n; ++i) { +#if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + strings[i] = sources[(int)i].data(); + lengths[i] = sources[(int)i].length(); +#else // #if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + strings[i] = sources[(int)i].first; + lengths[i] = sources[(int)i].second; +#endif // #if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + } + + object_ = ::clCreateProgramWithSource( + context(), (cl_uint)n, strings.data(), lengths.data(), &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_SOURCE_ERR); + if (err != NULL) { + *err = error; + } + } + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 || (CL_HPP_TARGET_OPENCL_VERSION==200 && defined(CL_HPP_USE_IL_KHR)) + /** + * Program constructor to allow construction of program from SPIR-V or another IL. + * Valid for either OpenCL >= 2.1 or when CL_HPP_USE_IL_KHR is defined. + */ + Program( + const vector& IL, + bool build = false, + cl_int* err = NULL) + { + cl_int error; + + Context context = Context::getDefault(err); + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + object_ = ::clCreateProgramWithIL( + context(), static_cast(IL.data()), IL.size(), &error); + +#else // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + typedef clCreateProgramWithILKHR_fn PFN_clCreateProgramWithILKHR; + static PFN_clCreateProgramWithILKHR pfn_clCreateProgramWithILKHR = NULL; + CL_HPP_INIT_CL_EXT_FCN_PTR_(clCreateProgramWithILKHR); + + return detail::errHandler( + pfn_clCreateProgramWithILKHR( + context(), static_cast(IL.data()), IL.size(), &error); + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + detail::errHandler(error, __CREATE_PROGRAM_WITH_IL_ERR); + + if (error == CL_SUCCESS && build) { + + error = ::clBuildProgram( + object_, + 0, + NULL, +#if !defined(CL_HPP_CL_1_2_DEFAULT_BUILD) + "-cl-std=CL2.0", +#else + "", +#endif // #if !defined(CL_HPP_CL_1_2_DEFAULT_BUILD) + NULL, + NULL); + + detail::buildErrHandler(error, __BUILD_PROGRAM_ERR, getBuildInfo()); + } + + if (err != NULL) { + *err = error; + } + } + + /** + * Program constructor to allow construction of program from SPIR-V or another IL + * for a specific context. + * Valid for either OpenCL >= 2.1 or when CL_HPP_USE_IL_KHR is defined. + */ + Program( + const Context& context, + const vector& IL, + bool build = false, + cl_int* err = NULL) + { + cl_int error; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + object_ = ::clCreateProgramWithIL( + context(), static_cast(IL.data()), IL.size(), &error); + +#else // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + typedef clCreateProgramWithILKHR_fn PFN_clCreateProgramWithILKHR; + static PFN_clCreateProgramWithILKHR pfn_clCreateProgramWithILKHR = NULL; + CL_HPP_INIT_CL_EXT_FCN_PTR_(clCreateProgramWithILKHR); + + return detail::errHandler( + pfn_clCreateProgramWithILKHR( + context(), static_cast(IL.data()), IL.size(), &error); + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + detail::errHandler(error, __CREATE_PROGRAM_WITH_IL_ERR); + + if (error == CL_SUCCESS && build) { + error = ::clBuildProgram( + object_, + 0, + NULL, +#if !defined(CL_HPP_CL_1_2_DEFAULT_BUILD) + "-cl-std=CL2.0", +#else + "", +#endif // #if !defined(CL_HPP_CL_1_2_DEFAULT_BUILD) + NULL, + NULL); + + detail::buildErrHandler(error, __BUILD_PROGRAM_ERR, getBuildInfo()); + } + + if (err != NULL) { + *err = error; + } + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + /** + * Construct a program object from a list of devices and a per-device list of binaries. + * \param context A valid OpenCL context in which to construct the program. + * \param devices A vector of OpenCL device objects for which the program will be created. + * \param binaries A vector of pairs of a pointer to a binary object and its length. + * \param binaryStatus An optional vector that on completion will be resized to + * match the size of binaries and filled with values to specify if each binary + * was successfully loaded. + * Set to CL_SUCCESS if the binary was successfully loaded. + * Set to CL_INVALID_VALUE if the length is 0 or the binary pointer is NULL. + * Set to CL_INVALID_BINARY if the binary provided is not valid for the matching device. + * \param err if non-NULL will be set to CL_SUCCESS on successful operation or one of the following errors: + * CL_INVALID_CONTEXT if context is not a valid context. + * CL_INVALID_VALUE if the length of devices is zero; or if the length of binaries does not match the length of devices; + * or if any entry in binaries is NULL or has length 0. + * CL_INVALID_DEVICE if OpenCL devices listed in devices are not in the list of devices associated with context. + * CL_INVALID_BINARY if an invalid program binary was encountered for any device. binaryStatus will return specific status for each device. + * CL_OUT_OF_HOST_MEMORY if there is a failure to allocate resources required by the OpenCL implementation on the host. + */ + Program( + const Context& context, + const vector& devices, + const Binaries& binaries, + vector* binaryStatus = NULL, + cl_int* err = NULL) + { + cl_int error; + + const size_type numDevices = devices.size(); + + // Catch size mismatch early and return + if(binaries.size() != numDevices) { + error = CL_INVALID_VALUE; + detail::errHandler(error, __CREATE_PROGRAM_WITH_BINARY_ERR); + if (err != NULL) { + *err = error; + } + return; + } + + + vector lengths(numDevices); + vector images(numDevices); +#if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + for (size_type i = 0; i < numDevices; ++i) { + images[i] = binaries[i].data(); + lengths[i] = binaries[(int)i].size(); + } +#else // #if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + for (size_type i = 0; i < numDevices; ++i) { + images[i] = (const unsigned char*)binaries[i].first; + lengths[i] = binaries[(int)i].second; + } +#endif // #if !defined(CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY) + + vector deviceIDs(numDevices); + for( size_type deviceIndex = 0; deviceIndex < numDevices; ++deviceIndex ) { + deviceIDs[deviceIndex] = (devices[deviceIndex])(); + } + + if(binaryStatus) { + binaryStatus->resize(numDevices); + } + + object_ = ::clCreateProgramWithBinary( + context(), (cl_uint) devices.size(), + deviceIDs.data(), + lengths.data(), images.data(), (binaryStatus != NULL && numDevices > 0) + ? &binaryStatus->front() + : NULL, &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_BINARY_ERR); + if (err != NULL) { + *err = error; + } + } + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + /** + * Create program using builtin kernels. + * \param kernelNames Semi-colon separated list of builtin kernel names + */ + Program( + const Context& context, + const vector& devices, + const string& kernelNames, + cl_int* err = NULL) + { + cl_int error; + + + size_type numDevices = devices.size(); + vector deviceIDs(numDevices); + for( size_type deviceIndex = 0; deviceIndex < numDevices; ++deviceIndex ) { + deviceIDs[deviceIndex] = (devices[deviceIndex])(); + } + + object_ = ::clCreateProgramWithBuiltInKernels( + context(), + (cl_uint) devices.size(), + deviceIDs.data(), + kernelNames.c_str(), + &error); + + detail::errHandler(error, __CREATE_PROGRAM_WITH_BUILT_IN_KERNELS_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + + Program() { } + + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + */ + explicit Program(const cl_program& program, bool retainObject = false) : + detail::Wrapper(program, retainObject) { } + + Program& operator = (const cl_program& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + Program(const Program& program) : detail::Wrapper(program) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + Program& operator = (const Program &program) + { + detail::Wrapper::operator=(program); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + Program(Program&& program) CL_HPP_NOEXCEPT_ : detail::Wrapper(std::move(program)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + Program& operator = (Program &&program) + { + detail::Wrapper::operator=(std::move(program)); + return *this; + } + + cl_int build( + const vector& devices, + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL) const + { + size_type numDevices = devices.size(); + vector deviceIDs(numDevices); + + for( size_type deviceIndex = 0; deviceIndex < numDevices; ++deviceIndex ) { + deviceIDs[deviceIndex] = (devices[deviceIndex])(); + } + + cl_int buildError = ::clBuildProgram( + object_, + (cl_uint) + devices.size(), + deviceIDs.data(), + options, + notifyFptr, + data); + + return detail::buildErrHandler(buildError, __BUILD_PROGRAM_ERR, getBuildInfo()); + } + + cl_int build( + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL) const + { + cl_int buildError = ::clBuildProgram( + object_, + 0, + NULL, + options, + notifyFptr, + data); + + + return detail::buildErrHandler(buildError, __BUILD_PROGRAM_ERR, getBuildInfo()); + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + cl_int compile( + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL) const + { + cl_int error = ::clCompileProgram( + object_, + 0, + NULL, + options, + 0, + NULL, + NULL, + notifyFptr, + data); + return detail::buildErrHandler(error, __COMPILE_PROGRAM_ERR, getBuildInfo()); + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + + template + cl_int getInfo(cl_program_info name, T* param) const + { + return detail::errHandler( + detail::getInfo(&::clGetProgramInfo, object_, name, param), + __GET_PROGRAM_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_program_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + template + cl_int getBuildInfo( + const Device& device, cl_program_build_info name, T* param) const + { + return detail::errHandler( + detail::getInfo( + &::clGetProgramBuildInfo, object_, device(), name, param), + __GET_PROGRAM_BUILD_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getBuildInfo(const Device& device, cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_program_build_info, name>::param_type param; + cl_int result = getBuildInfo(device, name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /** + * Build info function that returns a vector of device/info pairs for the specified + * info type and for all devices in the program. + * On an error reading the info for any device, an empty vector of info will be returned. + */ + template + vector::param_type>> + getBuildInfo(cl_int *err = NULL) const + { + cl_int result = CL_SUCCESS; + + auto devs = getInfo(&result); + vector::param_type>> + devInfo; + + // If there was an initial error from getInfo return the error + if (result != CL_SUCCESS) { + if (err != NULL) { + *err = result; + } + return devInfo; + } + + for (const cl::Device &d : devs) { + typename detail::param_traits< + detail::cl_program_build_info, name>::param_type param; + result = getBuildInfo(d, name, ¶m); + devInfo.push_back( + std::pair::param_type> + (d, param)); + if (result != CL_SUCCESS) { + // On error, leave the loop and return the error code + break; + } + } + if (err != NULL) { + *err = result; + } + if (result != CL_SUCCESS) { + devInfo.clear(); + } + return devInfo; + } + + cl_int createKernels(vector* kernels) + { + cl_uint numKernels; + cl_int err = ::clCreateKernelsInProgram(object_, 0, NULL, &numKernels); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_KERNELS_IN_PROGRAM_ERR); + } + + vector value(numKernels); + + err = ::clCreateKernelsInProgram( + object_, numKernels, value.data(), NULL); + if (err != CL_SUCCESS) { + return detail::errHandler(err, __CREATE_KERNELS_IN_PROGRAM_ERR); + } + + if (kernels) { + kernels->resize(value.size()); + + // Assign to param, constructing with retain behaviour + // to correctly capture each underlying CL object + for (size_type i = 0; i < value.size(); i++) { + // We do not need to retain because this kernel is being created + // by the runtime + (*kernels)[i] = Kernel(value[i], false); + } + } + return CL_SUCCESS; + } +}; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 +inline Program linkProgram( + Program input1, + Program input2, + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL, + cl_int* err = NULL) +{ + cl_int error_local = CL_SUCCESS; + + cl_program programs[2] = { input1(), input2() }; + + Context ctx = input1.getInfo(&error_local); + if(error_local!=CL_SUCCESS) { + detail::errHandler(error_local, __LINK_PROGRAM_ERR); + } + + cl_program prog = ::clLinkProgram( + ctx(), + 0, + NULL, + options, + 2, + programs, + notifyFptr, + data, + &error_local); + + detail::errHandler(error_local,__COMPILE_PROGRAM_ERR); + if (err != NULL) { + *err = error_local; + } + + return Program(prog); +} + +inline Program linkProgram( + vector inputPrograms, + const char* options = NULL, + void (CL_CALLBACK * notifyFptr)(cl_program, void *) = NULL, + void* data = NULL, + cl_int* err = NULL) +{ + cl_int error_local = CL_SUCCESS; + + vector programs(inputPrograms.size()); + + for (unsigned int i = 0; i < inputPrograms.size(); i++) { + programs[i] = inputPrograms[i](); + } + + Context ctx; + if(inputPrograms.size() > 0) { + ctx = inputPrograms[0].getInfo(&error_local); + if(error_local!=CL_SUCCESS) { + detail::errHandler(error_local, __LINK_PROGRAM_ERR); + } + } + cl_program prog = ::clLinkProgram( + ctx(), + 0, + NULL, + options, + (cl_uint)inputPrograms.size(), + programs.data(), + notifyFptr, + data, + &error_local); + + detail::errHandler(error_local,__COMPILE_PROGRAM_ERR); + if (err != NULL) { + *err = error_local; + } + + return Program(prog, false); +} +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + +// Template specialization for CL_PROGRAM_BINARIES +template <> +inline cl_int cl::Program::getInfo(cl_program_info name, vector>* param) const +{ + if (name != CL_PROGRAM_BINARIES) { + return CL_INVALID_VALUE; + } + if (param) { + // Resize the parameter array appropriately for each allocation + // and pass down to the helper + + vector sizes = getInfo(); + size_type numBinaries = sizes.size(); + + // Resize the parameter array and constituent arrays + param->resize(numBinaries); + for (size_type i = 0; i < numBinaries; ++i) { + (*param)[i].resize(sizes[i]); + } + + return detail::errHandler( + detail::getInfo(&::clGetProgramInfo, object_, name, param), + __GET_PROGRAM_INFO_ERR); + } + + return CL_SUCCESS; +} + +template<> +inline vector> cl::Program::getInfo(cl_int* err) const +{ + vector> binariesVectors; + + cl_int result = getInfo(CL_PROGRAM_BINARIES, &binariesVectors); + if (err != NULL) { + *err = result; + } + return binariesVectors; +} + +inline Kernel::Kernel(const Program& program, const char* name, cl_int* err) +{ + cl_int error; + + object_ = ::clCreateKernel(program(), name, &error); + detail::errHandler(error, __CREATE_KERNEL_ERR); + + if (err != NULL) { + *err = error; + } + +} + +enum class QueueProperties : cl_command_queue_properties +{ + None = 0, + Profiling = CL_QUEUE_PROFILING_ENABLE, + OutOfOrder = CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE, +}; + +inline QueueProperties operator|(QueueProperties lhs, QueueProperties rhs) +{ + return static_cast(static_cast(lhs) | static_cast(rhs)); +} + +/*! \class CommandQueue + * \brief CommandQueue interface for cl_command_queue. + */ +class CommandQueue : public detail::Wrapper +{ +private: + static std::once_flag default_initialized_; + static CommandQueue default_; + static cl_int default_error_; + + /*! \brief Create the default command queue returned by @ref getDefault. + * + * It sets default_error_ to indicate success or failure. It does not throw + * @c cl::Error. + */ + static void makeDefault() + { + /* We don't want to throw an error from this function, so we have to + * catch and set the error flag. + */ +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + try +#endif + { + int error; + Context context = Context::getDefault(&error); + + if (error != CL_SUCCESS) { + default_error_ = error; + } + else { + Device device = Device::getDefault(); + default_ = CommandQueue(context, device, 0, &default_error_); + } + } +#if defined(CL_HPP_ENABLE_EXCEPTIONS) + catch (cl::Error &e) { + default_error_ = e.err(); + } +#endif + } + + /*! \brief Create the default command queue. + * + * This sets @c default_. It does not throw + * @c cl::Error. + */ + static void makeDefaultProvided(const CommandQueue &c) { + default_ = c; + } + +public: +#ifdef CL_HPP_UNIT_TEST_ENABLE + /*! \brief Reset the default. + * + * This sets @c default_ to an empty value to support cleanup in + * the unit test framework. + * This function is not thread safe. + */ + static void unitTestClearDefault() { + default_ = CommandQueue(); + } +#endif // #ifdef CL_HPP_UNIT_TEST_ENABLE + + + /*! + * \brief Constructs a CommandQueue based on passed properties. + * Will return an CL_INVALID_QUEUE_PROPERTIES error if CL_QUEUE_ON_DEVICE is specified. + */ + CommandQueue( + cl_command_queue_properties properties, + cl_int* err = NULL) + { + cl_int error; + + Context context = Context::getDefault(&error); + detail::errHandler(error, __CREATE_CONTEXT_ERR); + + if (error != CL_SUCCESS) { + if (err != NULL) { + *err = error; + } + } + else { + Device device = context.getInfo()[0]; + bool useWithProperties; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useWithProperties = (version >= 0x20000); // OpenCL 2.0 or above + } +#elif CL_HPP_TARGET_OPENCL_VERSION >= 200 + useWithProperties = true; +#else + useWithProperties = false; +#endif + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + if (useWithProperties) { + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, properties, 0 }; + if ((properties & CL_QUEUE_ON_DEVICE) == 0) { + object_ = ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error); + } + else { + error = CL_INVALID_QUEUE_PROPERTIES; + } + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 200 + if (!useWithProperties) { + object_ = ::clCreateCommandQueue( + context(), device(), properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 200 + } + } + + /*! + * \brief Constructs a CommandQueue based on passed properties. + * Will return an CL_INVALID_QUEUE_PROPERTIES error if CL_QUEUE_ON_DEVICE is specified. + */ + CommandQueue( + QueueProperties properties, + cl_int* err = NULL) + { + cl_int error; + + Context context = Context::getDefault(&error); + detail::errHandler(error, __CREATE_CONTEXT_ERR); + + if (error != CL_SUCCESS) { + if (err != NULL) { + *err = error; + } + } + else { + Device device = context.getInfo()[0]; + bool useWithProperties; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useWithProperties = (version >= 0x20000); // OpenCL 2.0 or above + } +#elif CL_HPP_TARGET_OPENCL_VERSION >= 200 + useWithProperties = true; +#else + useWithProperties = false; +#endif + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + if (useWithProperties) { + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, static_cast(properties), 0 }; + + object_ = ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 200 + if (!useWithProperties) { + object_ = ::clCreateCommandQueue( + context(), device(), static_cast(properties), &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 200 + + } + } + + /*! + * \brief Constructs a CommandQueue for an implementation defined device in the given context + * Will return an CL_INVALID_QUEUE_PROPERTIES error if CL_QUEUE_ON_DEVICE is specified. + */ + explicit CommandQueue( + const Context& context, + cl_command_queue_properties properties = 0, + cl_int* err = NULL) + { + cl_int error; + bool useWithProperties; + vector devices; + error = context.getInfo(CL_CONTEXT_DEVICES, &devices); + + detail::errHandler(error, __CREATE_CONTEXT_ERR); + + if (error != CL_SUCCESS) + { + if (err != NULL) { + *err = error; + } + return; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useWithProperties = (version >= 0x20000); // OpenCL 2.0 or above + } +#elif CL_HPP_TARGET_OPENCL_VERSION >= 200 + useWithProperties = true; +#else + useWithProperties = false; +#endif + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + if (useWithProperties) { + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, properties, 0 }; + if ((properties & CL_QUEUE_ON_DEVICE) == 0) { + object_ = ::clCreateCommandQueueWithProperties( + context(), devices[0](), queue_properties, &error); + } + else { + error = CL_INVALID_QUEUE_PROPERTIES; + } + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 200 + if (!useWithProperties) { + object_ = ::clCreateCommandQueue( + context(), devices[0](), properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 200 + } + + /*! + * \brief Constructs a CommandQueue for an implementation defined device in the given context + * Will return an CL_INVALID_QUEUE_PROPERTIES error if CL_QUEUE_ON_DEVICE is specified. + */ + explicit CommandQueue( + const Context& context, + QueueProperties properties, + cl_int* err = NULL) + { + cl_int error; + bool useWithProperties; + vector devices; + error = context.getInfo(CL_CONTEXT_DEVICES, &devices); + + detail::errHandler(error, __CREATE_CONTEXT_ERR); + + if (error != CL_SUCCESS) + { + if (err != NULL) { + *err = error; + } + return; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useWithProperties = (version >= 0x20000); // OpenCL 2.0 or above + } +#elif CL_HPP_TARGET_OPENCL_VERSION >= 200 + useWithProperties = true; +#else + useWithProperties = false; +#endif + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + if (useWithProperties) { + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, static_cast(properties), 0 }; + object_ = ::clCreateCommandQueueWithProperties( + context(), devices[0](), queue_properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 200 + if (!useWithProperties) { + object_ = ::clCreateCommandQueue( + context(), devices[0](), static_cast(properties), &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 200 + } + + /*! + * \brief Constructs a CommandQueue for a passed device and context + * Will return an CL_INVALID_QUEUE_PROPERTIES error if CL_QUEUE_ON_DEVICE is specified. + */ + CommandQueue( + const Context& context, + const Device& device, + cl_command_queue_properties properties = 0, + cl_int* err = NULL) + { + cl_int error; + bool useWithProperties; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useWithProperties = (version >= 0x20000); // OpenCL 2.0 or above + } +#elif CL_HPP_TARGET_OPENCL_VERSION >= 200 + useWithProperties = true; +#else + useWithProperties = false; +#endif + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + if (useWithProperties) { + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, properties, 0 }; + object_ = ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 200 + if (!useWithProperties) { + object_ = ::clCreateCommandQueue( + context(), device(), properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 200 + } + + /*! + * \brief Constructs a CommandQueue for a passed device and context + * Will return an CL_INVALID_QUEUE_PROPERTIES error if CL_QUEUE_ON_DEVICE is specified. + */ + CommandQueue( + const Context& context, + const Device& device, + QueueProperties properties, + cl_int* err = NULL) + { + cl_int error; + bool useWithProperties; + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 && CL_HPP_MINIMUM_OPENCL_VERSION < 200 + // Run-time decision based on the actual platform + { + cl_uint version = detail::getContextPlatformVersion(context()); + useWithProperties = (version >= 0x20000); // OpenCL 2.0 or above + } +#elif CL_HPP_TARGET_OPENCL_VERSION >= 200 + useWithProperties = true; +#else + useWithProperties = false; +#endif + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + if (useWithProperties) { + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, static_cast(properties), 0 }; + object_ = ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 +#if CL_HPP_MINIMUM_OPENCL_VERSION < 200 + if (!useWithProperties) { + object_ = ::clCreateCommandQueue( + context(), device(), static_cast(properties), &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + } +#endif // CL_HPP_MINIMUM_OPENCL_VERSION < 200 + } + + static CommandQueue getDefault(cl_int * err = NULL) + { + std::call_once(default_initialized_, makeDefault); +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + detail::errHandler(default_error_, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); +#else // CL_HPP_TARGET_OPENCL_VERSION >= 200 + detail::errHandler(default_error_, __CREATE_COMMAND_QUEUE_ERR); +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 200 + if (err != NULL) { + *err = default_error_; + } + return default_; + } + + /** + * Modify the default command queue to be used by + * subsequent operations. + * Will only set the default if no default was previously created. + * @return updated default command queue. + * Should be compared to the passed value to ensure that it was updated. + */ + static CommandQueue setDefault(const CommandQueue &default_queue) + { + std::call_once(default_initialized_, makeDefaultProvided, std::cref(default_queue)); + detail::errHandler(default_error_); + return default_; + } + + CommandQueue() { } + + + /*! \brief Constructor from cl_mem - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + */ + explicit CommandQueue(const cl_command_queue& commandQueue, bool retainObject = false) : + detail::Wrapper(commandQueue, retainObject) { } + + CommandQueue& operator = (const cl_command_queue& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + CommandQueue(const CommandQueue& queue) : detail::Wrapper(queue) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + CommandQueue& operator = (const CommandQueue &queue) + { + detail::Wrapper::operator=(queue); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + CommandQueue(CommandQueue&& queue) CL_HPP_NOEXCEPT_ : detail::Wrapper(std::move(queue)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + CommandQueue& operator = (CommandQueue &&queue) + { + detail::Wrapper::operator=(std::move(queue)); + return *this; + } + + template + cl_int getInfo(cl_command_queue_info name, T* param) const + { + return detail::errHandler( + detail::getInfo( + &::clGetCommandQueueInfo, object_, name, param), + __GET_COMMAND_QUEUE_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_command_queue_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + cl_int enqueueReadBuffer( + const Buffer& buffer, + cl_bool blocking, + size_type offset, + size_type size, + void* ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueReadBuffer( + object_, buffer(), blocking, offset, size, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_READ_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueWriteBuffer( + const Buffer& buffer, + cl_bool blocking, + size_type offset, + size_type size, + const void* ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueWriteBuffer( + object_, buffer(), blocking, offset, size, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_WRITE_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueCopyBuffer( + const Buffer& src, + const Buffer& dst, + size_type src_offset, + size_type dst_offset, + size_type size, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyBuffer( + object_, src(), dst(), src_offset, dst_offset, size, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQEUE_COPY_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 + cl_int enqueueReadBufferRect( + const Buffer& buffer, + cl_bool blocking, + const array& buffer_offset, + const array& host_offset, + const array& region, + size_type buffer_row_pitch, + size_type buffer_slice_pitch, + size_type host_row_pitch, + size_type host_slice_pitch, + void *ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueReadBufferRect( + object_, + buffer(), + blocking, + buffer_offset.data(), + host_offset.data(), + region.data(), + buffer_row_pitch, + buffer_slice_pitch, + host_row_pitch, + host_slice_pitch, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_READ_BUFFER_RECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueWriteBufferRect( + const Buffer& buffer, + cl_bool blocking, + const array& buffer_offset, + const array& host_offset, + const array& region, + size_type buffer_row_pitch, + size_type buffer_slice_pitch, + size_type host_row_pitch, + size_type host_slice_pitch, + const void *ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueWriteBufferRect( + object_, + buffer(), + blocking, + buffer_offset.data(), + host_offset.data(), + region.data(), + buffer_row_pitch, + buffer_slice_pitch, + host_row_pitch, + host_slice_pitch, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_WRITE_BUFFER_RECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueCopyBufferRect( + const Buffer& src, + const Buffer& dst, + const array& src_origin, + const array& dst_origin, + const array& region, + size_type src_row_pitch, + size_type src_slice_pitch, + size_type dst_row_pitch, + size_type dst_slice_pitch, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyBufferRect( + object_, + src(), + dst(), + src_origin.data(), + dst_origin.data(), + region.data(), + src_row_pitch, + src_slice_pitch, + dst_row_pitch, + dst_slice_pitch, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQEUE_COPY_BUFFER_RECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 110 +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + /** + * Enqueue a command to fill a buffer object with a pattern + * of a given size. The pattern is specified as a vector type. + * \tparam PatternType The datatype of the pattern field. + * The pattern type must be an accepted OpenCL data type. + * \tparam offset Is the offset in bytes into the buffer at + * which to start filling. This must be a multiple of + * the pattern size. + * \tparam size Is the size in bytes of the region to fill. + * This must be a multiple of the pattern size. + */ + template + cl_int enqueueFillBuffer( + const Buffer& buffer, + PatternType pattern, + size_type offset, + size_type size, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueFillBuffer( + object_, + buffer(), + static_cast(&pattern), + sizeof(PatternType), + offset, + size, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_FILL_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + + cl_int enqueueReadImage( + const Image& image, + cl_bool blocking, + const array& origin, + const array& region, + size_type row_pitch, + size_type slice_pitch, + void* ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueReadImage( + object_, + image(), + blocking, + origin.data(), + region.data(), + row_pitch, + slice_pitch, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_READ_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueWriteImage( + const Image& image, + cl_bool blocking, + const array& origin, + const array& region, + size_type row_pitch, + size_type slice_pitch, + const void* ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueWriteImage( + object_, + image(), + blocking, + origin.data(), + region.data(), + row_pitch, + slice_pitch, + ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_WRITE_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueCopyImage( + const Image& src, + const Image& dst, + const array& src_origin, + const array& dst_origin, + const array& region, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyImage( + object_, + src(), + dst(), + src_origin.data(), + dst_origin.data(), + region.data(), + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_COPY_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + /** + * Enqueue a command to fill an image object with a specified color. + * \param fillColor is the color to use to fill the image. + * This is a four component RGBA floating-point color value if + * the image channel data type is not an unnormalized signed or + * unsigned data type. + */ + cl_int enqueueFillImage( + const Image& image, + cl_float4 fillColor, + const array& origin, + const array& region, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueFillImage( + object_, + image(), + static_cast(&fillColor), + origin.data(), + region.data(), + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_FILL_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueue a command to fill an image object with a specified color. + * \param fillColor is the color to use to fill the image. + * This is a four component RGBA signed integer color value if + * the image channel data type is an unnormalized signed integer + * type. + */ + cl_int enqueueFillImage( + const Image& image, + cl_int4 fillColor, + const array& origin, + const array& region, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueFillImage( + object_, + image(), + static_cast(&fillColor), + origin.data(), + region.data(), + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_FILL_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueue a command to fill an image object with a specified color. + * \param fillColor is the color to use to fill the image. + * This is a four component RGBA unsigned integer color value if + * the image channel data type is an unnormalized unsigned integer + * type. + */ + cl_int enqueueFillImage( + const Image& image, + cl_uint4 fillColor, + const array& origin, + const array& region, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueFillImage( + object_, + image(), + static_cast(&fillColor), + origin.data(), + region.data(), + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_FILL_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + + cl_int enqueueCopyImageToBuffer( + const Image& src, + const Buffer& dst, + const array& src_origin, + const array& region, + size_type dst_offset, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyImageToBuffer( + object_, + src(), + dst(), + src_origin.data(), + region.data(), + dst_offset, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_COPY_IMAGE_TO_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueCopyBufferToImage( + const Buffer& src, + const Image& dst, + size_type src_offset, + const array& dst_origin, + const array& region, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueCopyBufferToImage( + object_, + src(), + dst(), + src_offset, + dst_origin.data(), + region.data(), + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_COPY_BUFFER_TO_IMAGE_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + void* enqueueMapBuffer( + const Buffer& buffer, + cl_bool blocking, + cl_map_flags flags, + size_type offset, + size_type size, + const vector* events = NULL, + Event* event = NULL, + cl_int* err = NULL) const + { + cl_event tmp; + cl_int error; + void * result = ::clEnqueueMapBuffer( + object_, buffer(), blocking, flags, offset, size, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL, + &error); + + detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + if (event != NULL && error == CL_SUCCESS) + *event = tmp; + + return result; + } + + void* enqueueMapImage( + const Image& buffer, + cl_bool blocking, + cl_map_flags flags, + const array& origin, + const array& region, + size_type * row_pitch, + size_type * slice_pitch, + const vector* events = NULL, + Event* event = NULL, + cl_int* err = NULL) const + { + cl_event tmp; + cl_int error; + void * result = ::clEnqueueMapImage( + object_, buffer(), blocking, flags, + origin.data(), + region.data(), + row_pitch, slice_pitch, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL, + &error); + + detail::errHandler(error, __ENQUEUE_MAP_IMAGE_ERR); + if (err != NULL) { + *err = error; + } + if (event != NULL && error == CL_SUCCESS) + *event = tmp; + return result; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + /** + * Enqueues a command that will allow the host to update a region of a coarse-grained SVM buffer. + * This variant takes a raw SVM pointer. + */ + template + cl_int enqueueMapSVM( + T* ptr, + cl_bool blocking, + cl_map_flags flags, + size_type size, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler(::clEnqueueSVMMap( + object_, blocking, flags, static_cast(ptr), size, + (events != NULL) ? (cl_uint)events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*)&events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_MAP_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + + /** + * Enqueues a command that will allow the host to update a region of a coarse-grained SVM buffer. + * This variant takes a cl::pointer instance. + */ + template + cl_int enqueueMapSVM( + cl::pointer &ptr, + cl_bool blocking, + cl_map_flags flags, + size_type size, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler(::clEnqueueSVMMap( + object_, blocking, flags, static_cast(ptr.get()), size, + (events != NULL) ? (cl_uint)events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*)&events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_MAP_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueues a command that will allow the host to update a region of a coarse-grained SVM buffer. + * This variant takes a cl::vector instance. + */ + template + cl_int enqueueMapSVM( + cl::vector &container, + cl_bool blocking, + cl_map_flags flags, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler(::clEnqueueSVMMap( + object_, blocking, flags, static_cast(container.data()), container.size(), + (events != NULL) ? (cl_uint)events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*)&events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_MAP_BUFFER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + + cl_int enqueueUnmapMemObject( + const Memory& memory, + void* mapped_ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueUnmapMemObject( + object_, memory(), mapped_ptr, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + /** + * Enqueues a command that will release a coarse-grained SVM buffer back to the OpenCL runtime. + * This variant takes a raw SVM pointer. + */ + template + cl_int enqueueUnmapSVM( + T* ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueSVMUnmap( + object_, static_cast(ptr), + (events != NULL) ? (cl_uint)events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*)&events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueues a command that will release a coarse-grained SVM buffer back to the OpenCL runtime. + * This variant takes a cl::pointer instance. + */ + template + cl_int enqueueUnmapSVM( + cl::pointer &ptr, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueSVMUnmap( + object_, static_cast(ptr.get()), + (events != NULL) ? (cl_uint)events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*)&events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueues a command that will release a coarse-grained SVM buffer back to the OpenCL runtime. + * This variant takes a cl::vector instance. + */ + template + cl_int enqueueUnmapSVM( + cl::vector &container, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueSVMUnmap( + object_, static_cast(container.data()), + (events != NULL) ? (cl_uint)events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*)&events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + /** + * Enqueues a marker command which waits for either a list of events to complete, + * or all previously enqueued commands to complete. + * + * Enqueues a marker command which waits for either a list of events to complete, + * or if the list is empty it waits for all commands previously enqueued in command_queue + * to complete before it completes. This command returns an event which can be waited on, + * i.e. this event can be waited on to insure that all events either in the event_wait_list + * or all previously enqueued commands, queued before this command to command_queue, + * have completed. + */ + cl_int enqueueMarkerWithWaitList( + const vector *events = 0, + Event *event = 0) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueMarkerWithWaitList( + object_, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_MARKER_WAIT_LIST_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * A synchronization point that enqueues a barrier operation. + * + * Enqueues a barrier command which waits for either a list of events to complete, + * or if the list is empty it waits for all commands previously enqueued in command_queue + * to complete before it completes. This command blocks command execution, that is, any + * following commands enqueued after it do not execute until it completes. This command + * returns an event which can be waited on, i.e. this event can be waited on to insure that + * all events either in the event_wait_list or all previously enqueued commands, queued + * before this command to command_queue, have completed. + */ + cl_int enqueueBarrierWithWaitList( + const vector *events = 0, + Event *event = 0) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueBarrierWithWaitList( + object_, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_BARRIER_WAIT_LIST_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueues a command to indicate with which device a set of memory objects + * should be associated. + */ + cl_int enqueueMigrateMemObjects( + const vector &memObjects, + cl_mem_migration_flags flags, + const vector* events = NULL, + Event* event = NULL + ) const + { + cl_event tmp; + + vector localMemObjects(memObjects.size()); + + for( int i = 0; i < (int)memObjects.size(); ++i ) { + localMemObjects[i] = memObjects[i](); + } + + cl_int err = detail::errHandler( + ::clEnqueueMigrateMemObjects( + object_, + (cl_uint)memObjects.size(), + localMemObjects.data(), + flags, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 + /** + * Enqueues a command that will allow the host associate ranges within a set of + * SVM allocations with a device. + * @param sizes - The length from each pointer to migrate. + */ + template + cl_int enqueueMigrateSVM( + const cl::vector &svmRawPointers, + const cl::vector &sizes, + cl_mem_migration_flags flags = 0, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler(::clEnqueueSVMMigrateMem( + object_, + svmRawPointers.size(), static_cast(svmRawPointers.data()), + sizes.data(), // array of sizes not passed + flags, + (events != NULL) ? (cl_uint)events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*)&events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_MIGRATE_SVM_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + /** + * Enqueues a command that will allow the host associate a set of SVM allocations with + * a device. + */ + template + cl_int enqueueMigrateSVM( + const cl::vector &svmRawPointers, + cl_mem_migration_flags flags = 0, + const vector* events = NULL, + Event* event = NULL) const + { + return enqueueMigrateSVM(svmRawPointers, cl::vector(svmRawPointers.size()), flags, events, event); + } + + + /** + * Enqueues a command that will allow the host associate ranges within a set of + * SVM allocations with a device. + * @param sizes - The length from each pointer to migrate. + */ + template + cl_int enqueueMigrateSVM( + const cl::vector> &svmPointers, + const cl::vector &sizes, + cl_mem_migration_flags flags = 0, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl::vector svmRawPointers; + svmRawPointers.reserve(svmPointers.size()); + for (auto p : svmPointers) { + svmRawPointers.push_back(static_cast(p.get())); + } + + return enqueueMigrateSVM(svmRawPointers, sizes, flags, events, event); + } + + + /** + * Enqueues a command that will allow the host associate a set of SVM allocations with + * a device. + */ + template + cl_int enqueueMigrateSVM( + const cl::vector> &svmPointers, + cl_mem_migration_flags flags = 0, + const vector* events = NULL, + Event* event = NULL) const + { + return enqueueMigrateSVM(svmPointers, cl::vector(svmPointers.size()), flags, events, event); + } + + /** + * Enqueues a command that will allow the host associate ranges within a set of + * SVM allocations with a device. + * @param sizes - The length from the beginning of each container to migrate. + */ + template + cl_int enqueueMigrateSVM( + const cl::vector> &svmContainers, + const cl::vector &sizes, + cl_mem_migration_flags flags = 0, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl::vector svmRawPointers; + svmRawPointers.reserve(svmContainers.size()); + for (auto p : svmContainers) { + svmRawPointers.push_back(static_cast(p.data())); + } + + return enqueueMigrateSVM(svmRawPointers, sizes, flags, events, event); + } + + /** + * Enqueues a command that will allow the host associate a set of SVM allocations with + * a device. + */ + template + cl_int enqueueMigrateSVM( + const cl::vector> &svmContainers, + cl_mem_migration_flags flags = 0, + const vector* events = NULL, + Event* event = NULL) const + { + return enqueueMigrateSVM(svmContainers, cl::vector(svmContainers.size()), flags, events, event); + } + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 + + cl_int enqueueNDRangeKernel( + const Kernel& kernel, + const NDRange& offset, + const NDRange& global, + const NDRange& local = NullRange, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueNDRangeKernel( + object_, kernel(), (cl_uint) global.dimensions(), + offset.dimensions() != 0 ? (const size_type*) offset : NULL, + (const size_type*) global, + local.dimensions() != 0 ? (const size_type*) local : NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_NDRANGE_KERNEL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +#if defined(CL_USE_DEPRECATED_OPENCL_1_2_APIS) + CL_EXT_PREFIX__VERSION_1_2_DEPRECATED cl_int enqueueTask( + const Kernel& kernel, + const vector* events = NULL, + Event* event = NULL) const CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueTask( + object_, kernel(), + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_TASK_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif // #if defined(CL_USE_DEPRECATED_OPENCL_1_2_APIS) + + cl_int enqueueNativeKernel( + void (CL_CALLBACK *userFptr)(void *), + std::pair args, + const vector* mem_objects = NULL, + const vector* mem_locs = NULL, + const vector* events = NULL, + Event* event = NULL) const + { + size_type elements = 0; + if (mem_objects != NULL) { + elements = mem_objects->size(); + } + vector mems(elements); + for (unsigned int i = 0; i < elements; i++) { + mems[i] = ((*mem_objects)[i])(); + } + + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueNativeKernel( + object_, userFptr, args.first, args.second, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + mems.data(), + (mem_locs != NULL && mem_locs->size() > 0) ? (const void **) &mem_locs->front() : NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_NATIVE_KERNEL); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + CL_EXT_PREFIX__VERSION_1_1_DEPRECATED + cl_int enqueueMarker(Event* event = NULL) const CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueMarker( + object_, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_MARKER_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + CL_EXT_PREFIX__VERSION_1_1_DEPRECATED + cl_int enqueueWaitForEvents(const vector& events) const CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED + { + return detail::errHandler( + ::clEnqueueWaitForEvents( + object_, + (cl_uint) events.size(), + events.size() > 0 ? (const cl_event*) &events.front() : NULL), + __ENQUEUE_WAIT_FOR_EVENTS_ERR); + } +#endif // defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + + cl_int enqueueAcquireGLObjects( + const vector* mem_objects = NULL, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueAcquireGLObjects( + object_, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + (mem_objects != NULL && mem_objects->size() > 0) ? (const cl_mem *) &mem_objects->front(): NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_ACQUIRE_GL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueReleaseGLObjects( + const vector* mem_objects = NULL, + const vector* events = NULL, + Event* event = NULL) const + { + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueReleaseGLObjects( + object_, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + (mem_objects != NULL && mem_objects->size() > 0) ? (const cl_mem *) &mem_objects->front(): NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_RELEASE_GL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + +#if defined (CL_HPP_USE_DX_INTEROP) +typedef CL_API_ENTRY cl_int (CL_API_CALL *PFN_clEnqueueAcquireD3D10ObjectsKHR)( + cl_command_queue command_queue, cl_uint num_objects, + const cl_mem* mem_objects, cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, cl_event* event); +typedef CL_API_ENTRY cl_int (CL_API_CALL *PFN_clEnqueueReleaseD3D10ObjectsKHR)( + cl_command_queue command_queue, cl_uint num_objects, + const cl_mem* mem_objects, cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, cl_event* event); + + cl_int enqueueAcquireD3D10Objects( + const vector* mem_objects = NULL, + const vector* events = NULL, + Event* event = NULL) const + { + static PFN_clEnqueueAcquireD3D10ObjectsKHR pfn_clEnqueueAcquireD3D10ObjectsKHR = NULL; +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + cl_context context = getInfo(); + cl::Device device(getInfo()); + cl_platform_id platform = device.getInfo(); + CL_HPP_INIT_CL_EXT_FCN_PTR_PLATFORM_(platform, clEnqueueAcquireD3D10ObjectsKHR); +#endif +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 + CL_HPP_INIT_CL_EXT_FCN_PTR_(clEnqueueAcquireD3D10ObjectsKHR); +#endif + + cl_event tmp; + cl_int err = detail::errHandler( + pfn_clEnqueueAcquireD3D10ObjectsKHR( + object_, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + (mem_objects != NULL && mem_objects->size() > 0) ? (const cl_mem *) &mem_objects->front(): NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_ACQUIRE_GL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } + + cl_int enqueueReleaseD3D10Objects( + const vector* mem_objects = NULL, + const vector* events = NULL, + Event* event = NULL) const + { + static PFN_clEnqueueReleaseD3D10ObjectsKHR pfn_clEnqueueReleaseD3D10ObjectsKHR = NULL; +#if CL_HPP_TARGET_OPENCL_VERSION >= 120 + cl_context context = getInfo(); + cl::Device device(getInfo()); + cl_platform_id platform = device.getInfo(); + CL_HPP_INIT_CL_EXT_FCN_PTR_PLATFORM_(platform, clEnqueueReleaseD3D10ObjectsKHR); +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 120 +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 + CL_HPP_INIT_CL_EXT_FCN_PTR_(clEnqueueReleaseD3D10ObjectsKHR); +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 110 + + cl_event tmp; + cl_int err = detail::errHandler( + pfn_clEnqueueReleaseD3D10ObjectsKHR( + object_, + (mem_objects != NULL) ? (cl_uint) mem_objects->size() : 0, + (mem_objects != NULL && mem_objects->size() > 0) ? (const cl_mem *) &mem_objects->front(): NULL, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_RELEASE_GL_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; + } +#endif + +/** + * Deprecated APIs for 1.2 + */ +#if defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) + CL_EXT_PREFIX__VERSION_1_1_DEPRECATED + cl_int enqueueBarrier() const CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED + { + return detail::errHandler( + ::clEnqueueBarrier(object_), + __ENQUEUE_BARRIER_ERR); + } +#endif // CL_USE_DEPRECATED_OPENCL_1_1_APIS + + cl_int flush() const + { + return detail::errHandler(::clFlush(object_), __FLUSH_ERR); + } + + cl_int finish() const + { + return detail::errHandler(::clFinish(object_), __FINISH_ERR); + } +}; // CommandQueue + +CL_HPP_DEFINE_STATIC_MEMBER_ std::once_flag CommandQueue::default_initialized_; +CL_HPP_DEFINE_STATIC_MEMBER_ CommandQueue CommandQueue::default_; +CL_HPP_DEFINE_STATIC_MEMBER_ cl_int CommandQueue::default_error_ = CL_SUCCESS; + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +enum class DeviceQueueProperties : cl_command_queue_properties +{ + None = 0, + Profiling = CL_QUEUE_PROFILING_ENABLE, +}; + +inline DeviceQueueProperties operator|(DeviceQueueProperties lhs, DeviceQueueProperties rhs) +{ + return static_cast(static_cast(lhs) | static_cast(rhs)); +} + +/*! \class DeviceCommandQueue + * \brief DeviceCommandQueue interface for device cl_command_queues. + */ +class DeviceCommandQueue : public detail::Wrapper +{ +public: + + /*! + * Trivial empty constructor to create a null queue. + */ + DeviceCommandQueue() { } + + /*! + * Default construct device command queue on default context and device + */ + DeviceCommandQueue(DeviceQueueProperties properties, cl_int* err = NULL) + { + cl_int error; + cl::Context context = cl::Context::getDefault(); + cl::Device device = cl::Device::getDefault(); + + cl_command_queue_properties mergedProperties = + CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE | CL_QUEUE_ON_DEVICE | static_cast(properties); + + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, mergedProperties, 0 }; + object_ = ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! + * Create a device command queue for a specified device in the passed context. + */ + DeviceCommandQueue( + const Context& context, + const Device& device, + DeviceQueueProperties properties = DeviceQueueProperties::None, + cl_int* err = NULL) + { + cl_int error; + + cl_command_queue_properties mergedProperties = + CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE | CL_QUEUE_ON_DEVICE | static_cast(properties); + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, mergedProperties, 0 }; + object_ = ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! + * Create a device command queue for a specified device in the passed context. + */ + DeviceCommandQueue( + const Context& context, + const Device& device, + cl_uint queueSize, + DeviceQueueProperties properties = DeviceQueueProperties::None, + cl_int* err = NULL) + { + cl_int error; + + cl_command_queue_properties mergedProperties = + CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE | CL_QUEUE_ON_DEVICE | static_cast(properties); + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, mergedProperties, + CL_QUEUE_SIZE, queueSize, + 0 }; + object_ = ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + } + + /*! \brief Constructor from cl_command_queue - takes ownership. + * + * \param retainObject will cause the constructor to retain its cl object. + * Defaults to false to maintain compatibility with + * earlier versions. + */ + explicit DeviceCommandQueue(const cl_command_queue& commandQueue, bool retainObject = false) : + detail::Wrapper(commandQueue, retainObject) { } + + DeviceCommandQueue& operator = (const cl_command_queue& rhs) + { + detail::Wrapper::operator=(rhs); + return *this; + } + + /*! \brief Copy constructor to forward copy to the superclass correctly. + * Required for MSVC. + */ + DeviceCommandQueue(const DeviceCommandQueue& queue) : detail::Wrapper(queue) {} + + /*! \brief Copy assignment to forward copy to the superclass correctly. + * Required for MSVC. + */ + DeviceCommandQueue& operator = (const DeviceCommandQueue &queue) + { + detail::Wrapper::operator=(queue); + return *this; + } + + /*! \brief Move constructor to forward move to the superclass correctly. + * Required for MSVC. + */ + DeviceCommandQueue(DeviceCommandQueue&& queue) CL_HPP_NOEXCEPT_ : detail::Wrapper(std::move(queue)) {} + + /*! \brief Move assignment to forward move to the superclass correctly. + * Required for MSVC. + */ + DeviceCommandQueue& operator = (DeviceCommandQueue &&queue) + { + detail::Wrapper::operator=(std::move(queue)); + return *this; + } + + template + cl_int getInfo(cl_command_queue_info name, T* param) const + { + return detail::errHandler( + detail::getInfo( + &::clGetCommandQueueInfo, object_, name, param), + __GET_COMMAND_QUEUE_INFO_ERR); + } + + template typename + detail::param_traits::param_type + getInfo(cl_int* err = NULL) const + { + typename detail::param_traits< + detail::cl_command_queue_info, name>::param_type param; + cl_int result = getInfo(name, ¶m); + if (err != NULL) { + *err = result; + } + return param; + } + + /*! + * Create a new default device command queue for the default device, + * in the default context and of the default size. + * If there is already a default queue for the specified device this + * function will return the pre-existing queue. + */ + static DeviceCommandQueue makeDefault( + cl_int *err = nullptr) + { + cl_int error; + cl::Context context = cl::Context::getDefault(); + cl::Device device = cl::Device::getDefault(); + + cl_command_queue_properties properties = + CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE | CL_QUEUE_ON_DEVICE | CL_QUEUE_ON_DEVICE_DEFAULT; + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, properties, + 0 }; + DeviceCommandQueue deviceQueue( + ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error)); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + + return deviceQueue; + } + + /*! + * Create a new default device command queue for the specified device + * and of the default size. + * If there is already a default queue for the specified device this + * function will return the pre-existing queue. + */ + static DeviceCommandQueue makeDefault( + const Context &context, const Device &device, cl_int *err = nullptr) + { + cl_int error; + + cl_command_queue_properties properties = + CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE | CL_QUEUE_ON_DEVICE | CL_QUEUE_ON_DEVICE_DEFAULT; + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, properties, + 0 }; + DeviceCommandQueue deviceQueue( + ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error)); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + + return deviceQueue; + } + + /*! + * Create a new default device command queue for the specified device + * and of the requested size in bytes. + * If there is already a default queue for the specified device this + * function will return the pre-existing queue. + */ + static DeviceCommandQueue makeDefault( + const Context &context, const Device &device, cl_uint queueSize, cl_int *err = nullptr) + { + cl_int error; + + cl_command_queue_properties properties = + CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE | CL_QUEUE_ON_DEVICE | CL_QUEUE_ON_DEVICE_DEFAULT; + cl_queue_properties queue_properties[] = { + CL_QUEUE_PROPERTIES, properties, + CL_QUEUE_SIZE, queueSize, + 0 }; + DeviceCommandQueue deviceQueue( + ::clCreateCommandQueueWithProperties( + context(), device(), queue_properties, &error)); + + detail::errHandler(error, __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR); + if (err != NULL) { + *err = error; + } + + return deviceQueue; + } + + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 210 + /*! + * Modify the default device command queue to be used for subsequent kernels. + * This can update the default command queue for a device repeatedly to account + * for kernels that rely on the default. + * @return updated default device command queue. + */ + static DeviceCommandQueue updateDefault(const Context &context, const Device &device, const DeviceCommandQueue &default_queue, cl_int *err = nullptr) + { + cl_int error; + error = clSetDefaultDeviceCommandQueue(context.get(), device.get(), default_queue.get()); + + detail::errHandler(error, __SET_DEFAULT_DEVICE_COMMAND_QUEUE_ERR); + if (err != NULL) { + *err = error; + } + return default_queue; + } + + /*! + * Return the current default command queue for the specified command queue + */ + static DeviceCommandQueue getDefault(const CommandQueue &queue, cl_int * err = NULL) + { + return queue.getInfo(err); + } + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 210 +}; // DeviceCommandQueue + +namespace detail +{ + // Specialization for device command queue + template <> + struct KernelArgumentHandler + { + static size_type size(const cl::DeviceCommandQueue&) { return sizeof(cl_command_queue); } + static const cl_command_queue* ptr(const cl::DeviceCommandQueue& value) { return &(value()); } + }; +} // namespace detail + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + + +template< typename IteratorType > +Buffer::Buffer( + const Context &context, + IteratorType startIterator, + IteratorType endIterator, + bool readOnly, + bool useHostPtr, + cl_int* err) +{ + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + cl_mem_flags flags = 0; + if( readOnly ) { + flags |= CL_MEM_READ_ONLY; + } + else { + flags |= CL_MEM_READ_WRITE; + } + if( useHostPtr ) { + flags |= CL_MEM_USE_HOST_PTR; + } + + size_type size = sizeof(DataType)*(endIterator - startIterator); + + if( useHostPtr ) { + object_ = ::clCreateBuffer(context(), flags, size, static_cast(&*startIterator), &error); + } else { + object_ = ::clCreateBuffer(context(), flags, size, 0, &error); + } + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + if( !useHostPtr ) { + CommandQueue queue(context, 0, &error); + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + error = cl::copy(queue, startIterator, endIterator, *this); + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } +} + +template< typename IteratorType > +Buffer::Buffer( + const CommandQueue &queue, + IteratorType startIterator, + IteratorType endIterator, + bool readOnly, + bool useHostPtr, + cl_int* err) +{ + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + cl_mem_flags flags = 0; + if (readOnly) { + flags |= CL_MEM_READ_ONLY; + } + else { + flags |= CL_MEM_READ_WRITE; + } + if (useHostPtr) { + flags |= CL_MEM_USE_HOST_PTR; + } + + size_type size = sizeof(DataType)*(endIterator - startIterator); + + Context context = queue.getInfo(); + + if (useHostPtr) { + object_ = ::clCreateBuffer(context(), flags, size, static_cast(&*startIterator), &error); + } + else { + object_ = ::clCreateBuffer(context(), flags, size, 0, &error); + } + + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + if (!useHostPtr) { + error = cl::copy(queue, startIterator, endIterator, *this); + detail::errHandler(error, __CREATE_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + } +} + +inline cl_int enqueueReadBuffer( + const Buffer& buffer, + cl_bool blocking, + size_type offset, + size_type size, + void* ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueReadBuffer(buffer, blocking, offset, size, ptr, events, event); +} + +inline cl_int enqueueWriteBuffer( + const Buffer& buffer, + cl_bool blocking, + size_type offset, + size_type size, + const void* ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueWriteBuffer(buffer, blocking, offset, size, ptr, events, event); +} + +inline void* enqueueMapBuffer( + const Buffer& buffer, + cl_bool blocking, + cl_map_flags flags, + size_type offset, + size_type size, + const vector* events = NULL, + Event* event = NULL, + cl_int* err = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + + void * result = ::clEnqueueMapBuffer( + queue(), buffer(), blocking, flags, offset, size, + (events != NULL) ? (cl_uint) events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*) &events->front() : NULL, + (cl_event*) event, + &error); + + detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + if (err != NULL) { + *err = error; + } + return result; +} + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +/** + * Enqueues to the default queue a command that will allow the host to + * update a region of a coarse-grained SVM buffer. + * This variant takes a raw SVM pointer. + */ +template +inline cl_int enqueueMapSVM( + T* ptr, + cl_bool blocking, + cl_map_flags flags, + size_type size, + const vector* events, + Event* event) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) { + return detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + } + + return queue.enqueueMapSVM( + ptr, blocking, flags, size, events, event); +} + +/** + * Enqueues to the default queue a command that will allow the host to + * update a region of a coarse-grained SVM buffer. + * This variant takes a cl::pointer instance. + */ +template +inline cl_int enqueueMapSVM( + cl::pointer ptr, + cl_bool blocking, + cl_map_flags flags, + size_type size, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) { + return detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + } + + return queue.enqueueMapSVM( + ptr, blocking, flags, size, events, event); +} + +/** + * Enqueues to the default queue a command that will allow the host to + * update a region of a coarse-grained SVM buffer. + * This variant takes a cl::vector instance. + */ +template +inline cl_int enqueueMapSVM( + cl::vector container, + cl_bool blocking, + cl_map_flags flags, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) { + return detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + } + + return queue.enqueueMapSVM( + container, blocking, flags, events, event); +} + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + +inline cl_int enqueueUnmapMemObject( + const Memory& memory, + void* mapped_ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + detail::errHandler(error, __ENQUEUE_MAP_BUFFER_ERR); + if (error != CL_SUCCESS) { + return error; + } + + cl_event tmp; + cl_int err = detail::errHandler( + ::clEnqueueUnmapMemObject( + queue(), memory(), mapped_ptr, + (events != NULL) ? (cl_uint)events->size() : 0, + (events != NULL && events->size() > 0) ? (cl_event*)&events->front() : NULL, + (event != NULL) ? &tmp : NULL), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + + if (event != NULL && err == CL_SUCCESS) + *event = tmp; + + return err; +} + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +/** + * Enqueues to the default queue a command that will release a coarse-grained + * SVM buffer back to the OpenCL runtime. + * This variant takes a raw SVM pointer. + */ +template +inline cl_int enqueueUnmapSVM( + T* ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) { + return detail::errHandler(error, __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + } + + return detail::errHandler(queue.enqueueUnmapSVM(ptr, events, event), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + +} + +/** + * Enqueues to the default queue a command that will release a coarse-grained + * SVM buffer back to the OpenCL runtime. + * This variant takes a cl::pointer instance. + */ +template +inline cl_int enqueueUnmapSVM( + cl::pointer &ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) { + return detail::errHandler(error, __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + } + + return detail::errHandler(queue.enqueueUnmapSVM(ptr, events, event), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); +} + +/** + * Enqueues to the default queue a command that will release a coarse-grained + * SVM buffer back to the OpenCL runtime. + * This variant takes a cl::vector instance. + */ +template +inline cl_int enqueueUnmapSVM( + cl::vector &container, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) { + return detail::errHandler(error, __ENQUEUE_UNMAP_MEM_OBJECT_ERR); + } + + return detail::errHandler(queue.enqueueUnmapSVM(container, events, event), + __ENQUEUE_UNMAP_MEM_OBJECT_ERR); +} + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + +inline cl_int enqueueCopyBuffer( + const Buffer& src, + const Buffer& dst, + size_type src_offset, + size_type dst_offset, + size_type size, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyBuffer(src, dst, src_offset, dst_offset, size, events, event); +} + +/** + * Blocking copy operation between iterators and a buffer. + * Host to Device. + * Uses default command queue. + */ +template< typename IteratorType > +inline cl_int copy( IteratorType startIterator, IteratorType endIterator, cl::Buffer &buffer ) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) + return error; + + return cl::copy(queue, startIterator, endIterator, buffer); +} + +/** + * Blocking copy operation between iterators and a buffer. + * Device to Host. + * Uses default command queue. + */ +template< typename IteratorType > +inline cl_int copy( const cl::Buffer &buffer, IteratorType startIterator, IteratorType endIterator ) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + if (error != CL_SUCCESS) + return error; + + return cl::copy(queue, buffer, startIterator, endIterator); +} + +/** + * Blocking copy operation between iterators and a buffer. + * Host to Device. + * Uses specified queue. + */ +template< typename IteratorType > +inline cl_int copy( const CommandQueue &queue, IteratorType startIterator, IteratorType endIterator, cl::Buffer &buffer ) +{ + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + size_type length = endIterator-startIterator; + size_type byteLength = length*sizeof(DataType); + + DataType *pointer = + static_cast(queue.enqueueMapBuffer(buffer, CL_TRUE, CL_MAP_WRITE, 0, byteLength, 0, 0, &error)); + // if exceptions enabled, enqueueMapBuffer will throw + if( error != CL_SUCCESS ) { + return error; + } +#if defined(_MSC_VER) + std::copy( + startIterator, + endIterator, + stdext::checked_array_iterator( + pointer, length)); +#else + std::copy(startIterator, endIterator, pointer); +#endif + Event endEvent; + error = queue.enqueueUnmapMemObject(buffer, pointer, 0, &endEvent); + // if exceptions enabled, enqueueUnmapMemObject will throw + if( error != CL_SUCCESS ) { + return error; + } + endEvent.wait(); + return CL_SUCCESS; +} + +/** + * Blocking copy operation between iterators and a buffer. + * Device to Host. + * Uses specified queue. + */ +template< typename IteratorType > +inline cl_int copy( const CommandQueue &queue, const cl::Buffer &buffer, IteratorType startIterator, IteratorType endIterator ) +{ + typedef typename std::iterator_traits::value_type DataType; + cl_int error; + + size_type length = endIterator-startIterator; + size_type byteLength = length*sizeof(DataType); + + DataType *pointer = + static_cast(queue.enqueueMapBuffer(buffer, CL_TRUE, CL_MAP_READ, 0, byteLength, 0, 0, &error)); + // if exceptions enabled, enqueueMapBuffer will throw + if( error != CL_SUCCESS ) { + return error; + } + std::copy(pointer, pointer + length, startIterator); + Event endEvent; + error = queue.enqueueUnmapMemObject(buffer, pointer, 0, &endEvent); + // if exceptions enabled, enqueueUnmapMemObject will throw + if( error != CL_SUCCESS ) { + return error; + } + endEvent.wait(); + return CL_SUCCESS; +} + + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 +/** + * Blocking SVM map operation - performs a blocking map underneath. + */ +template +inline cl_int mapSVM(cl::vector &container) +{ + return enqueueMapSVM(container, CL_TRUE, CL_MAP_READ | CL_MAP_WRITE); +} + +/** +* Blocking SVM map operation - performs a blocking map underneath. +*/ +template +inline cl_int unmapSVM(cl::vector &container) +{ + return enqueueUnmapSVM(container); +} + +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + +#if CL_HPP_TARGET_OPENCL_VERSION >= 110 +inline cl_int enqueueReadBufferRect( + const Buffer& buffer, + cl_bool blocking, + const array& buffer_offset, + const array& host_offset, + const array& region, + size_type buffer_row_pitch, + size_type buffer_slice_pitch, + size_type host_row_pitch, + size_type host_slice_pitch, + void *ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueReadBufferRect( + buffer, + blocking, + buffer_offset, + host_offset, + region, + buffer_row_pitch, + buffer_slice_pitch, + host_row_pitch, + host_slice_pitch, + ptr, + events, + event); +} + +inline cl_int enqueueWriteBufferRect( + const Buffer& buffer, + cl_bool blocking, + const array& buffer_offset, + const array& host_offset, + const array& region, + size_type buffer_row_pitch, + size_type buffer_slice_pitch, + size_type host_row_pitch, + size_type host_slice_pitch, + const void *ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueWriteBufferRect( + buffer, + blocking, + buffer_offset, + host_offset, + region, + buffer_row_pitch, + buffer_slice_pitch, + host_row_pitch, + host_slice_pitch, + ptr, + events, + event); +} + +inline cl_int enqueueCopyBufferRect( + const Buffer& src, + const Buffer& dst, + const array& src_origin, + const array& dst_origin, + const array& region, + size_type src_row_pitch, + size_type src_slice_pitch, + size_type dst_row_pitch, + size_type dst_slice_pitch, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyBufferRect( + src, + dst, + src_origin, + dst_origin, + region, + src_row_pitch, + src_slice_pitch, + dst_row_pitch, + dst_slice_pitch, + events, + event); +} +#endif // CL_HPP_TARGET_OPENCL_VERSION >= 110 + +inline cl_int enqueueReadImage( + const Image& image, + cl_bool blocking, + const array& origin, + const array& region, + size_type row_pitch, + size_type slice_pitch, + void* ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueReadImage( + image, + blocking, + origin, + region, + row_pitch, + slice_pitch, + ptr, + events, + event); +} + +inline cl_int enqueueWriteImage( + const Image& image, + cl_bool blocking, + const array& origin, + const array& region, + size_type row_pitch, + size_type slice_pitch, + const void* ptr, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueWriteImage( + image, + blocking, + origin, + region, + row_pitch, + slice_pitch, + ptr, + events, + event); +} + +inline cl_int enqueueCopyImage( + const Image& src, + const Image& dst, + const array& src_origin, + const array& dst_origin, + const array& region, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyImage( + src, + dst, + src_origin, + dst_origin, + region, + events, + event); +} + +inline cl_int enqueueCopyImageToBuffer( + const Image& src, + const Buffer& dst, + const array& src_origin, + const array& region, + size_type dst_offset, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyImageToBuffer( + src, + dst, + src_origin, + region, + dst_offset, + events, + event); +} + +inline cl_int enqueueCopyBufferToImage( + const Buffer& src, + const Image& dst, + size_type src_offset, + const array& dst_origin, + const array& region, + const vector* events = NULL, + Event* event = NULL) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.enqueueCopyBufferToImage( + src, + dst, + src_offset, + dst_origin, + region, + events, + event); +} + + +inline cl_int flush(void) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + return queue.flush(); +} + +inline cl_int finish(void) +{ + cl_int error; + CommandQueue queue = CommandQueue::getDefault(&error); + + if (error != CL_SUCCESS) { + return error; + } + + + return queue.finish(); +} + +class EnqueueArgs +{ +private: + CommandQueue queue_; + const NDRange offset_; + const NDRange global_; + const NDRange local_; + vector events_; + + template + friend class KernelFunctor; + +public: + EnqueueArgs(NDRange global) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(NullRange) + { + + } + + EnqueueArgs(NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(local) + { + + } + + EnqueueArgs(NDRange offset, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(offset), + global_(global), + local_(local) + { + + } + + EnqueueArgs(Event e, NDRange global) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(NullRange) + { + events_.push_back(e); + } + + EnqueueArgs(Event e, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(local) + { + events_.push_back(e); + } + + EnqueueArgs(Event e, NDRange offset, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(offset), + global_(global), + local_(local) + { + events_.push_back(e); + } + + EnqueueArgs(const vector &events, NDRange global) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(NullRange), + events_(events) + { + + } + + EnqueueArgs(const vector &events, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(NullRange), + global_(global), + local_(local), + events_(events) + { + + } + + EnqueueArgs(const vector &events, NDRange offset, NDRange global, NDRange local) : + queue_(CommandQueue::getDefault()), + offset_(offset), + global_(global), + local_(local), + events_(events) + { + + } + + EnqueueArgs(CommandQueue &queue, NDRange global) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(NullRange) + { + + } + + EnqueueArgs(CommandQueue &queue, NDRange global, NDRange local) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(local) + { + + } + + EnqueueArgs(CommandQueue &queue, NDRange offset, NDRange global, NDRange local) : + queue_(queue), + offset_(offset), + global_(global), + local_(local) + { + + } + + EnqueueArgs(CommandQueue &queue, Event e, NDRange global) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(NullRange) + { + events_.push_back(e); + } + + EnqueueArgs(CommandQueue &queue, Event e, NDRange global, NDRange local) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(local) + { + events_.push_back(e); + } + + EnqueueArgs(CommandQueue &queue, Event e, NDRange offset, NDRange global, NDRange local) : + queue_(queue), + offset_(offset), + global_(global), + local_(local) + { + events_.push_back(e); + } + + EnqueueArgs(CommandQueue &queue, const vector &events, NDRange global) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(NullRange), + events_(events) + { + + } + + EnqueueArgs(CommandQueue &queue, const vector &events, NDRange global, NDRange local) : + queue_(queue), + offset_(NullRange), + global_(global), + local_(local), + events_(events) + { + + } + + EnqueueArgs(CommandQueue &queue, const vector &events, NDRange offset, NDRange global, NDRange local) : + queue_(queue), + offset_(offset), + global_(global), + local_(local), + events_(events) + { + + } +}; + + +//---------------------------------------------------------------------------------------------- + + +/** + * Type safe kernel functor. + * + */ +template +class KernelFunctor +{ +private: + Kernel kernel_; + + template + void setArgs(T0&& t0, T1s&&... t1s) + { + kernel_.setArg(index, t0); + setArgs(std::forward(t1s)...); + } + + template + void setArgs(T0&& t0) + { + kernel_.setArg(index, t0); + } + + template + void setArgs() + { + } + + +public: + KernelFunctor(Kernel kernel) : kernel_(kernel) + {} + + KernelFunctor( + const Program& program, + const string name, + cl_int * err = NULL) : + kernel_(program, name.c_str(), err) + {} + + //! \brief Return type of the functor + typedef Event result_type; + + /** + * Enqueue kernel. + * @param args Launch parameters of the kernel. + * @param t0... List of kernel arguments based on the template type of the functor. + */ + Event operator() ( + const EnqueueArgs& args, + Ts... ts) + { + Event event; + setArgs<0>(std::forward(ts)...); + + args.queue_.enqueueNDRangeKernel( + kernel_, + args.offset_, + args.global_, + args.local_, + &args.events_, + &event); + + return event; + } + + /** + * Enqueue kernel with support for error code. + * @param args Launch parameters of the kernel. + * @param t0... List of kernel arguments based on the template type of the functor. + * @param error Out parameter returning the error code from the execution. + */ + Event operator() ( + const EnqueueArgs& args, + Ts... ts, + cl_int &error) + { + Event event; + setArgs<0>(std::forward(ts)...); + + error = args.queue_.enqueueNDRangeKernel( + kernel_, + args.offset_, + args.global_, + args.local_, + &args.events_, + &event); + + return event; + } + +#if CL_HPP_TARGET_OPENCL_VERSION >= 200 + cl_int setSVMPointers(const vector &pointerList) + { + return kernel_.setSVMPointers(pointerList); + } + + template + cl_int setSVMPointers(const T0 &t0, T1s &... ts) + { + return kernel_.setSVMPointers(t0, ts...); + } +#endif // #if CL_HPP_TARGET_OPENCL_VERSION >= 200 + + Kernel getKernel() + { + return kernel_; + } +}; + +namespace compatibility { + /** + * Backward compatibility class to ensure that cl.hpp code works with cl2.hpp. + * Please use KernelFunctor directly. + */ + template + struct make_kernel + { + typedef KernelFunctor FunctorType; + + FunctorType functor_; + + make_kernel( + const Program& program, + const string name, + cl_int * err = NULL) : + functor_(FunctorType(program, name, err)) + {} + + make_kernel( + const Kernel kernel) : + functor_(FunctorType(kernel)) + {} + + //! \brief Return type of the functor + typedef Event result_type; + + //! \brief Function signature of kernel functor with no event dependency. + typedef Event type_( + const EnqueueArgs&, + Ts...); + + Event operator()( + const EnqueueArgs& enqueueArgs, + Ts... args) + { + return functor_( + enqueueArgs, args...); + } + }; +} // namespace compatibility + + +//---------------------------------------------------------------------------------------------------------------------- + +#undef CL_HPP_ERR_STR_ +#if !defined(CL_HPP_USER_OVERRIDE_ERROR_STRINGS) +#undef __GET_DEVICE_INFO_ERR +#undef __GET_PLATFORM_INFO_ERR +#undef __GET_DEVICE_IDS_ERR +#undef __GET_PLATFORM_IDS_ERR +#undef __GET_CONTEXT_INFO_ERR +#undef __GET_EVENT_INFO_ERR +#undef __GET_EVENT_PROFILE_INFO_ERR +#undef __GET_MEM_OBJECT_INFO_ERR +#undef __GET_IMAGE_INFO_ERR +#undef __GET_SAMPLER_INFO_ERR +#undef __GET_KERNEL_INFO_ERR +#undef __GET_KERNEL_ARG_INFO_ERR +#undef __GET_KERNEL_SUB_GROUP_INFO_ERR +#undef __GET_KERNEL_WORK_GROUP_INFO_ERR +#undef __GET_PROGRAM_INFO_ERR +#undef __GET_PROGRAM_BUILD_INFO_ERR +#undef __GET_COMMAND_QUEUE_INFO_ERR +#undef __CREATE_CONTEXT_ERR +#undef __CREATE_CONTEXT_FROM_TYPE_ERR +#undef __GET_SUPPORTED_IMAGE_FORMATS_ERR +#undef __CREATE_BUFFER_ERR +#undef __COPY_ERR +#undef __CREATE_SUBBUFFER_ERR +#undef __CREATE_GL_BUFFER_ERR +#undef __CREATE_GL_RENDER_BUFFER_ERR +#undef __GET_GL_OBJECT_INFO_ERR +#undef __CREATE_IMAGE_ERR +#undef __CREATE_GL_TEXTURE_ERR +#undef __IMAGE_DIMENSION_ERR +#undef __SET_MEM_OBJECT_DESTRUCTOR_CALLBACK_ERR +#undef __CREATE_USER_EVENT_ERR +#undef __SET_USER_EVENT_STATUS_ERR +#undef __SET_EVENT_CALLBACK_ERR +#undef __WAIT_FOR_EVENTS_ERR +#undef __CREATE_KERNEL_ERR +#undef __SET_KERNEL_ARGS_ERR +#undef __CREATE_PROGRAM_WITH_SOURCE_ERR +#undef __CREATE_PROGRAM_WITH_IL_ERR +#undef __CREATE_PROGRAM_WITH_BINARY_ERR +#undef __CREATE_PROGRAM_WITH_IL_ERR +#undef __CREATE_PROGRAM_WITH_BUILT_IN_KERNELS_ERR +#undef __BUILD_PROGRAM_ERR +#undef __COMPILE_PROGRAM_ERR +#undef __LINK_PROGRAM_ERR +#undef __CREATE_KERNELS_IN_PROGRAM_ERR +#undef __CREATE_COMMAND_QUEUE_WITH_PROPERTIES_ERR +#undef __CREATE_SAMPLER_WITH_PROPERTIES_ERR +#undef __SET_COMMAND_QUEUE_PROPERTY_ERR +#undef __ENQUEUE_READ_BUFFER_ERR +#undef __ENQUEUE_READ_BUFFER_RECT_ERR +#undef __ENQUEUE_WRITE_BUFFER_ERR +#undef __ENQUEUE_WRITE_BUFFER_RECT_ERR +#undef __ENQEUE_COPY_BUFFER_ERR +#undef __ENQEUE_COPY_BUFFER_RECT_ERR +#undef __ENQUEUE_FILL_BUFFER_ERR +#undef __ENQUEUE_READ_IMAGE_ERR +#undef __ENQUEUE_WRITE_IMAGE_ERR +#undef __ENQUEUE_COPY_IMAGE_ERR +#undef __ENQUEUE_FILL_IMAGE_ERR +#undef __ENQUEUE_COPY_IMAGE_TO_BUFFER_ERR +#undef __ENQUEUE_COPY_BUFFER_TO_IMAGE_ERR +#undef __ENQUEUE_MAP_BUFFER_ERR +#undef __ENQUEUE_MAP_IMAGE_ERR +#undef __ENQUEUE_UNMAP_MEM_OBJECT_ERR +#undef __ENQUEUE_NDRANGE_KERNEL_ERR +#undef __ENQUEUE_NATIVE_KERNEL +#undef __ENQUEUE_MIGRATE_MEM_OBJECTS_ERR +#undef __ENQUEUE_MIGRATE_SVM_ERR +#undef __ENQUEUE_ACQUIRE_GL_ERR +#undef __ENQUEUE_RELEASE_GL_ERR +#undef __CREATE_PIPE_ERR +#undef __GET_PIPE_INFO_ERR +#undef __RETAIN_ERR +#undef __RELEASE_ERR +#undef __FLUSH_ERR +#undef __FINISH_ERR +#undef __VECTOR_CAPACITY_ERR +#undef __CREATE_SUB_DEVICES_ERR +#undef __CREATE_SUB_DEVICES_ERR +#undef __ENQUEUE_MARKER_ERR +#undef __ENQUEUE_WAIT_FOR_EVENTS_ERR +#undef __ENQUEUE_BARRIER_ERR +#undef __UNLOAD_COMPILER_ERR +#undef __CREATE_GL_TEXTURE_2D_ERR +#undef __CREATE_GL_TEXTURE_3D_ERR +#undef __CREATE_IMAGE2D_ERR +#undef __CREATE_IMAGE3D_ERR +#undef __CREATE_COMMAND_QUEUE_ERR +#undef __ENQUEUE_TASK_ERR +#undef __CREATE_SAMPLER_ERR +#undef __ENQUEUE_MARKER_WAIT_LIST_ERR +#undef __ENQUEUE_BARRIER_WAIT_LIST_ERR +#undef __CLONE_KERNEL_ERR +#undef __GET_HOST_TIMER_ERR +#undef __GET_DEVICE_AND_HOST_TIMER_ERR + +#endif //CL_HPP_USER_OVERRIDE_ERROR_STRINGS + +// Extensions +#undef CL_HPP_INIT_CL_EXT_FCN_PTR_ +#undef CL_HPP_INIT_CL_EXT_FCN_PTR_PLATFORM_ + +#if defined(CL_HPP_USE_CL_DEVICE_FISSION) +#undef CL_HPP_PARAM_NAME_DEVICE_FISSION_ +#endif // CL_HPP_USE_CL_DEVICE_FISSION + +#undef CL_HPP_NOEXCEPT_ +#undef CL_HPP_DEFINE_STATIC_MEMBER_ + +} // namespace cl + +#endif // CL_HPP_ diff --git a/benchmarks/new_opencl/include/CL/cl_d3d10.h b/benchmarks/new_opencl/include/CL/cl_d3d10.h new file mode 100644 index 00000000..d5960a43 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_d3d10.h @@ -0,0 +1,131 @@ +/********************************************************************************** + * Copyright (c) 2008-2015 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + **********************************************************************************/ + +/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */ + +#ifndef __OPENCL_CL_D3D10_H +#define __OPENCL_CL_D3D10_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * cl_khr_d3d10_sharing */ +#define cl_khr_d3d10_sharing 1 + +typedef cl_uint cl_d3d10_device_source_khr; +typedef cl_uint cl_d3d10_device_set_khr; + +/******************************************************************************/ + +/* Error Codes */ +#define CL_INVALID_D3D10_DEVICE_KHR -1002 +#define CL_INVALID_D3D10_RESOURCE_KHR -1003 +#define CL_D3D10_RESOURCE_ALREADY_ACQUIRED_KHR -1004 +#define CL_D3D10_RESOURCE_NOT_ACQUIRED_KHR -1005 + +/* cl_d3d10_device_source_nv */ +#define CL_D3D10_DEVICE_KHR 0x4010 +#define CL_D3D10_DXGI_ADAPTER_KHR 0x4011 + +/* cl_d3d10_device_set_nv */ +#define CL_PREFERRED_DEVICES_FOR_D3D10_KHR 0x4012 +#define CL_ALL_DEVICES_FOR_D3D10_KHR 0x4013 + +/* cl_context_info */ +#define CL_CONTEXT_D3D10_DEVICE_KHR 0x4014 +#define CL_CONTEXT_D3D10_PREFER_SHARED_RESOURCES_KHR 0x402C + +/* cl_mem_info */ +#define CL_MEM_D3D10_RESOURCE_KHR 0x4015 + +/* cl_image_info */ +#define CL_IMAGE_D3D10_SUBRESOURCE_KHR 0x4016 + +/* cl_command_type */ +#define CL_COMMAND_ACQUIRE_D3D10_OBJECTS_KHR 0x4017 +#define CL_COMMAND_RELEASE_D3D10_OBJECTS_KHR 0x4018 + +/******************************************************************************/ + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromD3D10KHR_fn)( + cl_platform_id platform, + cl_d3d10_device_source_khr d3d_device_source, + void * d3d_object, + cl_d3d10_device_set_khr d3d_device_set, + cl_uint num_entries, + cl_device_id * devices, + cl_uint * num_devices) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10BufferKHR_fn)( + cl_context context, + cl_mem_flags flags, + ID3D10Buffer * resource, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10Texture2DKHR_fn)( + cl_context context, + cl_mem_flags flags, + ID3D10Texture2D * resource, + UINT subresource, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10Texture3DKHR_fn)( + cl_context context, + cl_mem_flags flags, + ID3D10Texture3D * resource, + UINT subresource, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireD3D10ObjectsKHR_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseD3D10ObjectsKHR_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_D3D10_H */ + diff --git a/benchmarks/new_opencl/include/CL/cl_d3d11.h b/benchmarks/new_opencl/include/CL/cl_d3d11.h new file mode 100644 index 00000000..39f90723 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_d3d11.h @@ -0,0 +1,131 @@ +/********************************************************************************** + * Copyright (c) 2008-2015 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + **********************************************************************************/ + +/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */ + +#ifndef __OPENCL_CL_D3D11_H +#define __OPENCL_CL_D3D11_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * cl_khr_d3d11_sharing */ +#define cl_khr_d3d11_sharing 1 + +typedef cl_uint cl_d3d11_device_source_khr; +typedef cl_uint cl_d3d11_device_set_khr; + +/******************************************************************************/ + +/* Error Codes */ +#define CL_INVALID_D3D11_DEVICE_KHR -1006 +#define CL_INVALID_D3D11_RESOURCE_KHR -1007 +#define CL_D3D11_RESOURCE_ALREADY_ACQUIRED_KHR -1008 +#define CL_D3D11_RESOURCE_NOT_ACQUIRED_KHR -1009 + +/* cl_d3d11_device_source */ +#define CL_D3D11_DEVICE_KHR 0x4019 +#define CL_D3D11_DXGI_ADAPTER_KHR 0x401A + +/* cl_d3d11_device_set */ +#define CL_PREFERRED_DEVICES_FOR_D3D11_KHR 0x401B +#define CL_ALL_DEVICES_FOR_D3D11_KHR 0x401C + +/* cl_context_info */ +#define CL_CONTEXT_D3D11_DEVICE_KHR 0x401D +#define CL_CONTEXT_D3D11_PREFER_SHARED_RESOURCES_KHR 0x402D + +/* cl_mem_info */ +#define CL_MEM_D3D11_RESOURCE_KHR 0x401E + +/* cl_image_info */ +#define CL_IMAGE_D3D11_SUBRESOURCE_KHR 0x401F + +/* cl_command_type */ +#define CL_COMMAND_ACQUIRE_D3D11_OBJECTS_KHR 0x4020 +#define CL_COMMAND_RELEASE_D3D11_OBJECTS_KHR 0x4021 + +/******************************************************************************/ + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromD3D11KHR_fn)( + cl_platform_id platform, + cl_d3d11_device_source_khr d3d_device_source, + void * d3d_object, + cl_d3d11_device_set_khr d3d_device_set, + cl_uint num_entries, + cl_device_id * devices, + cl_uint * num_devices) CL_API_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11BufferKHR_fn)( + cl_context context, + cl_mem_flags flags, + ID3D11Buffer * resource, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11Texture2DKHR_fn)( + cl_context context, + cl_mem_flags flags, + ID3D11Texture2D * resource, + UINT subresource, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11Texture3DKHR_fn)( + cl_context context, + cl_mem_flags flags, + ID3D11Texture3D * resource, + UINT subresource, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireD3D11ObjectsKHR_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseD3D11ObjectsKHR_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_D3D11_H */ + diff --git a/benchmarks/new_opencl/include/CL/cl_dx9_media_sharing.h b/benchmarks/new_opencl/include/CL/cl_dx9_media_sharing.h new file mode 100644 index 00000000..2729e8b9 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_dx9_media_sharing.h @@ -0,0 +1,132 @@ +/********************************************************************************** + * Copyright (c) 2008-2015 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + **********************************************************************************/ + +/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */ + +#ifndef __OPENCL_CL_DX9_MEDIA_SHARING_H +#define __OPENCL_CL_DX9_MEDIA_SHARING_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* cl_khr_dx9_media_sharing */ +#define cl_khr_dx9_media_sharing 1 + +typedef cl_uint cl_dx9_media_adapter_type_khr; +typedef cl_uint cl_dx9_media_adapter_set_khr; + +#if defined(_WIN32) +#include +typedef struct _cl_dx9_surface_info_khr +{ + IDirect3DSurface9 *resource; + HANDLE shared_handle; +} cl_dx9_surface_info_khr; +#endif + + +/******************************************************************************/ + +/* Error Codes */ +#define CL_INVALID_DX9_MEDIA_ADAPTER_KHR -1010 +#define CL_INVALID_DX9_MEDIA_SURFACE_KHR -1011 +#define CL_DX9_MEDIA_SURFACE_ALREADY_ACQUIRED_KHR -1012 +#define CL_DX9_MEDIA_SURFACE_NOT_ACQUIRED_KHR -1013 + +/* cl_media_adapter_type_khr */ +#define CL_ADAPTER_D3D9_KHR 0x2020 +#define CL_ADAPTER_D3D9EX_KHR 0x2021 +#define CL_ADAPTER_DXVA_KHR 0x2022 + +/* cl_media_adapter_set_khr */ +#define CL_PREFERRED_DEVICES_FOR_DX9_MEDIA_ADAPTER_KHR 0x2023 +#define CL_ALL_DEVICES_FOR_DX9_MEDIA_ADAPTER_KHR 0x2024 + +/* cl_context_info */ +#define CL_CONTEXT_ADAPTER_D3D9_KHR 0x2025 +#define CL_CONTEXT_ADAPTER_D3D9EX_KHR 0x2026 +#define CL_CONTEXT_ADAPTER_DXVA_KHR 0x2027 + +/* cl_mem_info */ +#define CL_MEM_DX9_MEDIA_ADAPTER_TYPE_KHR 0x2028 +#define CL_MEM_DX9_MEDIA_SURFACE_INFO_KHR 0x2029 + +/* cl_image_info */ +#define CL_IMAGE_DX9_MEDIA_PLANE_KHR 0x202A + +/* cl_command_type */ +#define CL_COMMAND_ACQUIRE_DX9_MEDIA_SURFACES_KHR 0x202B +#define CL_COMMAND_RELEASE_DX9_MEDIA_SURFACES_KHR 0x202C + +/******************************************************************************/ + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromDX9MediaAdapterKHR_fn)( + cl_platform_id platform, + cl_uint num_media_adapters, + cl_dx9_media_adapter_type_khr * media_adapter_type, + void * media_adapters, + cl_dx9_media_adapter_set_khr media_adapter_set, + cl_uint num_entries, + cl_device_id * devices, + cl_uint * num_devices) CL_API_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromDX9MediaSurfaceKHR_fn)( + cl_context context, + cl_mem_flags flags, + cl_dx9_media_adapter_type_khr adapter_type, + void * surface_info, + cl_uint plane, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireDX9MediaSurfacesKHR_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseDX9MediaSurfacesKHR_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_2; + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_DX9_MEDIA_SHARING_H */ + diff --git a/benchmarks/new_opencl/include/CL/cl_dx9_media_sharing_intel.h b/benchmarks/new_opencl/include/CL/cl_dx9_media_sharing_intel.h new file mode 100644 index 00000000..737e6856 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_dx9_media_sharing_intel.h @@ -0,0 +1,182 @@ +/********************************************************************************** + * Copyright (c) 2008-2019 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + **********************************************************************************/ +/*****************************************************************************\ + +Copyright (c) 2013-2019 Intel Corporation All Rights Reserved. + +THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE +MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +File Name: cl_dx9_media_sharing_intel.h + +Abstract: + +Notes: + +\*****************************************************************************/ + +#ifndef __OPENCL_CL_DX9_MEDIA_SHARING_INTEL_H +#define __OPENCL_CL_DX9_MEDIA_SHARING_INTEL_H + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*************************************** +* cl_intel_dx9_media_sharing extension * +****************************************/ + +#define cl_intel_dx9_media_sharing 1 + +typedef cl_uint cl_dx9_device_source_intel; +typedef cl_uint cl_dx9_device_set_intel; + +/* error codes */ +#define CL_INVALID_DX9_DEVICE_INTEL -1010 +#define CL_INVALID_DX9_RESOURCE_INTEL -1011 +#define CL_DX9_RESOURCE_ALREADY_ACQUIRED_INTEL -1012 +#define CL_DX9_RESOURCE_NOT_ACQUIRED_INTEL -1013 + +/* cl_dx9_device_source_intel */ +#define CL_D3D9_DEVICE_INTEL 0x4022 +#define CL_D3D9EX_DEVICE_INTEL 0x4070 +#define CL_DXVA_DEVICE_INTEL 0x4071 + +/* cl_dx9_device_set_intel */ +#define CL_PREFERRED_DEVICES_FOR_DX9_INTEL 0x4024 +#define CL_ALL_DEVICES_FOR_DX9_INTEL 0x4025 + +/* cl_context_info */ +#define CL_CONTEXT_D3D9_DEVICE_INTEL 0x4026 +#define CL_CONTEXT_D3D9EX_DEVICE_INTEL 0x4072 +#define CL_CONTEXT_DXVA_DEVICE_INTEL 0x4073 + +/* cl_mem_info */ +#define CL_MEM_DX9_RESOURCE_INTEL 0x4027 +#define CL_MEM_DX9_SHARED_HANDLE_INTEL 0x4074 + +/* cl_image_info */ +#define CL_IMAGE_DX9_PLANE_INTEL 0x4075 + +/* cl_command_type */ +#define CL_COMMAND_ACQUIRE_DX9_OBJECTS_INTEL 0x402A +#define CL_COMMAND_RELEASE_DX9_OBJECTS_INTEL 0x402B +/******************************************************************************/ + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetDeviceIDsFromDX9INTEL( + cl_platform_id platform, + cl_dx9_device_source_intel dx9_device_source, + void* dx9_object, + cl_dx9_device_set_intel dx9_device_set, + cl_uint num_entries, + cl_device_id* devices, + cl_uint* num_devices) CL_EXT_SUFFIX__VERSION_1_1; + +typedef CL_API_ENTRY cl_int (CL_API_CALL* clGetDeviceIDsFromDX9INTEL_fn)( + cl_platform_id platform, + cl_dx9_device_source_intel dx9_device_source, + void* dx9_object, + cl_dx9_device_set_intel dx9_device_set, + cl_uint num_entries, + cl_device_id* devices, + cl_uint* num_devices) CL_EXT_SUFFIX__VERSION_1_1; + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateFromDX9MediaSurfaceINTEL( + cl_context context, + cl_mem_flags flags, + IDirect3DSurface9* resource, + HANDLE sharedHandle, + UINT plane, + cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_1; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromDX9MediaSurfaceINTEL_fn)( + cl_context context, + cl_mem_flags flags, + IDirect3DSurface9* resource, + HANDLE sharedHandle, + UINT plane, + cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_1; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueAcquireDX9ObjectsINTEL( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem* mem_objects, + cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, + cl_event* event) CL_EXT_SUFFIX__VERSION_1_1; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireDX9ObjectsINTEL_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem* mem_objects, + cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, + cl_event* event) CL_EXT_SUFFIX__VERSION_1_1; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueReleaseDX9ObjectsINTEL( + cl_command_queue command_queue, + cl_uint num_objects, + cl_mem* mem_objects, + cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, + cl_event* event) CL_EXT_SUFFIX__VERSION_1_1; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseDX9ObjectsINTEL_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + cl_mem* mem_objects, + cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, + cl_event* event) CL_EXT_SUFFIX__VERSION_1_1; + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_DX9_MEDIA_SHARING_INTEL_H */ + diff --git a/benchmarks/new_opencl/include/CL/cl_egl.h b/benchmarks/new_opencl/include/CL/cl_egl.h new file mode 100644 index 00000000..bc4d998e --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_egl.h @@ -0,0 +1,132 @@ +/******************************************************************************* + * Copyright (c) 2008-2019 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + ******************************************************************************/ + +#ifndef __OPENCL_CL_EGL_H +#define __OPENCL_CL_EGL_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Command type for events created with clEnqueueAcquireEGLObjectsKHR */ +#define CL_COMMAND_EGL_FENCE_SYNC_OBJECT_KHR 0x202F +#define CL_COMMAND_ACQUIRE_EGL_OBJECTS_KHR 0x202D +#define CL_COMMAND_RELEASE_EGL_OBJECTS_KHR 0x202E + +/* Error type for clCreateFromEGLImageKHR */ +#define CL_INVALID_EGL_OBJECT_KHR -1093 +#define CL_EGL_RESOURCE_NOT_ACQUIRED_KHR -1092 + +/* CLeglImageKHR is an opaque handle to an EGLImage */ +typedef void* CLeglImageKHR; + +/* CLeglDisplayKHR is an opaque handle to an EGLDisplay */ +typedef void* CLeglDisplayKHR; + +/* CLeglSyncKHR is an opaque handle to an EGLSync object */ +typedef void* CLeglSyncKHR; + +/* properties passed to clCreateFromEGLImageKHR */ +typedef intptr_t cl_egl_image_properties_khr; + + +#define cl_khr_egl_image 1 + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateFromEGLImageKHR(cl_context context, + CLeglDisplayKHR egldisplay, + CLeglImageKHR eglimage, + cl_mem_flags flags, + const cl_egl_image_properties_khr * properties, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromEGLImageKHR_fn)( + cl_context context, + CLeglDisplayKHR egldisplay, + CLeglImageKHR eglimage, + cl_mem_flags flags, + const cl_egl_image_properties_khr * properties, + cl_int * errcode_ret); + + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueAcquireEGLObjectsKHR(cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireEGLObjectsKHR_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event); + + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueReleaseEGLObjectsKHR(cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseEGLObjectsKHR_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event); + + +#define cl_khr_egl_event 1 + +extern CL_API_ENTRY cl_event CL_API_CALL +clCreateEventFromEGLSyncKHR(cl_context context, + CLeglSyncKHR sync, + CLeglDisplayKHR display, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_event (CL_API_CALL *clCreateEventFromEGLSyncKHR_fn)( + cl_context context, + CLeglSyncKHR sync, + CLeglDisplayKHR display, + cl_int * errcode_ret); + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_EGL_H */ diff --git a/benchmarks/new_opencl/include/CL/cl_ext.h b/benchmarks/new_opencl/include/CL/cl_ext.h new file mode 100644 index 00000000..5c185915 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_ext.h @@ -0,0 +1,762 @@ +/******************************************************************************* + * Copyright (c) 2008-2019 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + ******************************************************************************/ + +/* cl_ext.h contains OpenCL extensions which don't have external */ +/* (OpenGL, D3D) dependencies. */ + +#ifndef __CL_EXT_H +#define __CL_EXT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* cl_khr_fp64 extension - no extension #define since it has no functions */ +/* CL_DEVICE_DOUBLE_FP_CONFIG is defined in CL.h for OpenCL >= 120 */ + +#if CL_TARGET_OPENCL_VERSION <= 110 +#define CL_DEVICE_DOUBLE_FP_CONFIG 0x1032 +#endif + +/* cl_khr_fp16 extension - no extension #define since it has no functions */ +#define CL_DEVICE_HALF_FP_CONFIG 0x1033 + +/* Memory object destruction + * + * Apple extension for use to manage externally allocated buffers used with cl_mem objects with CL_MEM_USE_HOST_PTR + * + * Registers a user callback function that will be called when the memory object is deleted and its resources + * freed. Each call to clSetMemObjectCallbackFn registers the specified user callback function on a callback + * stack associated with memobj. The registered user callback functions are called in the reverse order in + * which they were registered. The user callback functions are called and then the memory object is deleted + * and its resources freed. This provides a mechanism for the application (and libraries) using memobj to be + * notified when the memory referenced by host_ptr, specified when the memory object is created and used as + * the storage bits for the memory object, can be reused or freed. + * + * The application may not call CL api's with the cl_mem object passed to the pfn_notify. + * + * Please check for the "cl_APPLE_SetMemObjectDestructor" extension using clGetDeviceInfo(CL_DEVICE_EXTENSIONS) + * before using. + */ +#define cl_APPLE_SetMemObjectDestructor 1 +cl_int CL_API_ENTRY clSetMemObjectDestructorAPPLE( cl_mem memobj, + void (* pfn_notify)(cl_mem memobj, void * user_data), + void * user_data) CL_EXT_SUFFIX__VERSION_1_0; + + +/* Context Logging Functions + * + * The next three convenience functions are intended to be used as the pfn_notify parameter to clCreateContext(). + * Please check for the "cl_APPLE_ContextLoggingFunctions" extension using clGetDeviceInfo(CL_DEVICE_EXTENSIONS) + * before using. + * + * clLogMessagesToSystemLog forwards on all log messages to the Apple System Logger + */ +#define cl_APPLE_ContextLoggingFunctions 1 +extern void CL_API_ENTRY clLogMessagesToSystemLogAPPLE( const char * errstr, + const void * private_info, + size_t cb, + void * user_data) CL_EXT_SUFFIX__VERSION_1_0; + +/* clLogMessagesToStdout sends all log messages to the file descriptor stdout */ +extern void CL_API_ENTRY clLogMessagesToStdoutAPPLE( const char * errstr, + const void * private_info, + size_t cb, + void * user_data) CL_EXT_SUFFIX__VERSION_1_0; + +/* clLogMessagesToStderr sends all log messages to the file descriptor stderr */ +extern void CL_API_ENTRY clLogMessagesToStderrAPPLE( const char * errstr, + const void * private_info, + size_t cb, + void * user_data) CL_EXT_SUFFIX__VERSION_1_0; + + +/************************ +* cl_khr_icd extension * +************************/ +#define cl_khr_icd 1 + +/* cl_platform_info */ +#define CL_PLATFORM_ICD_SUFFIX_KHR 0x0920 + +/* Additional Error Codes */ +#define CL_PLATFORM_NOT_FOUND_KHR -1001 + +extern CL_API_ENTRY cl_int CL_API_CALL +clIcdGetPlatformIDsKHR(cl_uint num_entries, + cl_platform_id * platforms, + cl_uint * num_platforms); + +typedef CL_API_ENTRY cl_int +(CL_API_CALL *clIcdGetPlatformIDsKHR_fn)(cl_uint num_entries, + cl_platform_id * platforms, + cl_uint * num_platforms); + + +/******************************* + * cl_khr_il_program extension * + *******************************/ +#define cl_khr_il_program 1 + +/* New property to clGetDeviceInfo for retrieving supported intermediate + * languages + */ +#define CL_DEVICE_IL_VERSION_KHR 0x105B + +/* New property to clGetProgramInfo for retrieving for retrieving the IL of a + * program + */ +#define CL_PROGRAM_IL_KHR 0x1169 + +extern CL_API_ENTRY cl_program CL_API_CALL +clCreateProgramWithILKHR(cl_context context, + const void * il, + size_t length, + cl_int * errcode_ret); + +typedef CL_API_ENTRY cl_program +(CL_API_CALL *clCreateProgramWithILKHR_fn)(cl_context context, + const void * il, + size_t length, + cl_int * errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; + +/* Extension: cl_khr_image2d_from_buffer + * + * This extension allows a 2D image to be created from a cl_mem buffer without + * a copy. The type associated with a 2D image created from a buffer in an + * OpenCL program is image2d_t. Both the sampler and sampler-less read_image + * built-in functions are supported for 2D images and 2D images created from + * a buffer. Similarly, the write_image built-ins are also supported for 2D + * images created from a buffer. + * + * When the 2D image from buffer is created, the client must specify the + * width, height, image format (i.e. channel order and channel data type) + * and optionally the row pitch. + * + * The pitch specified must be a multiple of + * CL_DEVICE_IMAGE_PITCH_ALIGNMENT_KHR pixels. + * The base address of the buffer must be aligned to + * CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT_KHR pixels. + */ + +#define CL_DEVICE_IMAGE_PITCH_ALIGNMENT_KHR 0x104A +#define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT_KHR 0x104B + + +/************************************** + * cl_khr_initialize_memory extension * + **************************************/ + +#define CL_CONTEXT_MEMORY_INITIALIZE_KHR 0x2030 + + +/************************************** + * cl_khr_terminate_context extension * + **************************************/ + +#define CL_DEVICE_TERMINATE_CAPABILITY_KHR 0x2031 +#define CL_CONTEXT_TERMINATE_KHR 0x2032 + +#define cl_khr_terminate_context 1 +extern CL_API_ENTRY cl_int CL_API_CALL +clTerminateContextKHR(cl_context context) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int +(CL_API_CALL *clTerminateContextKHR_fn)(cl_context context) CL_EXT_SUFFIX__VERSION_1_2; + + +/* + * Extension: cl_khr_spir + * + * This extension adds support to create an OpenCL program object from a + * Standard Portable Intermediate Representation (SPIR) instance + */ + +#define CL_DEVICE_SPIR_VERSIONS 0x40E0 +#define CL_PROGRAM_BINARY_TYPE_INTERMEDIATE 0x40E1 + + +/***************************************** + * cl_khr_create_command_queue extension * + *****************************************/ +#define cl_khr_create_command_queue 1 + +typedef cl_bitfield cl_queue_properties_khr; + +extern CL_API_ENTRY cl_command_queue CL_API_CALL +clCreateCommandQueueWithPropertiesKHR(cl_context context, + cl_device_id device, + const cl_queue_properties_khr* properties, + cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_command_queue +(CL_API_CALL *clCreateCommandQueueWithPropertiesKHR_fn)(cl_context context, + cl_device_id device, + const cl_queue_properties_khr* properties, + cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; + + +/****************************************** +* cl_nv_device_attribute_query extension * +******************************************/ + +/* cl_nv_device_attribute_query extension - no extension #define since it has no functions */ +#define CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV 0x4000 +#define CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV 0x4001 +#define CL_DEVICE_REGISTERS_PER_BLOCK_NV 0x4002 +#define CL_DEVICE_WARP_SIZE_NV 0x4003 +#define CL_DEVICE_GPU_OVERLAP_NV 0x4004 +#define CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV 0x4005 +#define CL_DEVICE_INTEGRATED_MEMORY_NV 0x4006 + + +/********************************* +* cl_amd_device_attribute_query * +*********************************/ + +#define CL_DEVICE_PROFILING_TIMER_OFFSET_AMD 0x4036 + + +/********************************* +* cl_arm_printf extension +*********************************/ + +#define CL_PRINTF_CALLBACK_ARM 0x40B0 +#define CL_PRINTF_BUFFERSIZE_ARM 0x40B1 + + +/*********************************** +* cl_ext_device_fission extension +***********************************/ +#define cl_ext_device_fission 1 + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseDeviceEXT(cl_device_id device) CL_EXT_SUFFIX__VERSION_1_1; + +typedef CL_API_ENTRY cl_int +(CL_API_CALL *clReleaseDeviceEXT_fn)(cl_device_id device) CL_EXT_SUFFIX__VERSION_1_1; + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainDeviceEXT(cl_device_id device) CL_EXT_SUFFIX__VERSION_1_1; + +typedef CL_API_ENTRY cl_int +(CL_API_CALL *clRetainDeviceEXT_fn)(cl_device_id device) CL_EXT_SUFFIX__VERSION_1_1; + +typedef cl_ulong cl_device_partition_property_ext; +extern CL_API_ENTRY cl_int CL_API_CALL +clCreateSubDevicesEXT(cl_device_id in_device, + const cl_device_partition_property_ext * properties, + cl_uint num_entries, + cl_device_id * out_devices, + cl_uint * num_devices) CL_EXT_SUFFIX__VERSION_1_1; + +typedef CL_API_ENTRY cl_int +(CL_API_CALL * clCreateSubDevicesEXT_fn)(cl_device_id in_device, + const cl_device_partition_property_ext * properties, + cl_uint num_entries, + cl_device_id * out_devices, + cl_uint * num_devices) CL_EXT_SUFFIX__VERSION_1_1; + +/* cl_device_partition_property_ext */ +#define CL_DEVICE_PARTITION_EQUALLY_EXT 0x4050 +#define CL_DEVICE_PARTITION_BY_COUNTS_EXT 0x4051 +#define CL_DEVICE_PARTITION_BY_NAMES_EXT 0x4052 +#define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT 0x4053 + +/* clDeviceGetInfo selectors */ +#define CL_DEVICE_PARENT_DEVICE_EXT 0x4054 +#define CL_DEVICE_PARTITION_TYPES_EXT 0x4055 +#define CL_DEVICE_AFFINITY_DOMAINS_EXT 0x4056 +#define CL_DEVICE_REFERENCE_COUNT_EXT 0x4057 +#define CL_DEVICE_PARTITION_STYLE_EXT 0x4058 + +/* error codes */ +#define CL_DEVICE_PARTITION_FAILED_EXT -1057 +#define CL_INVALID_PARTITION_COUNT_EXT -1058 +#define CL_INVALID_PARTITION_NAME_EXT -1059 + +/* CL_AFFINITY_DOMAINs */ +#define CL_AFFINITY_DOMAIN_L1_CACHE_EXT 0x1 +#define CL_AFFINITY_DOMAIN_L2_CACHE_EXT 0x2 +#define CL_AFFINITY_DOMAIN_L3_CACHE_EXT 0x3 +#define CL_AFFINITY_DOMAIN_L4_CACHE_EXT 0x4 +#define CL_AFFINITY_DOMAIN_NUMA_EXT 0x10 +#define CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT 0x100 + +/* cl_device_partition_property_ext list terminators */ +#define CL_PROPERTIES_LIST_END_EXT ((cl_device_partition_property_ext) 0) +#define CL_PARTITION_BY_COUNTS_LIST_END_EXT ((cl_device_partition_property_ext) 0) +#define CL_PARTITION_BY_NAMES_LIST_END_EXT ((cl_device_partition_property_ext) 0 - 1) + + +/*********************************** + * cl_ext_migrate_memobject extension definitions + ***********************************/ +#define cl_ext_migrate_memobject 1 + +typedef cl_bitfield cl_mem_migration_flags_ext; + +#define CL_MIGRATE_MEM_OBJECT_HOST_EXT 0x1 + +#define CL_COMMAND_MIGRATE_MEM_OBJECT_EXT 0x4040 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueMigrateMemObjectEXT(cl_command_queue command_queue, + cl_uint num_mem_objects, + const cl_mem * mem_objects, + cl_mem_migration_flags_ext flags, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event); + +typedef CL_API_ENTRY cl_int +(CL_API_CALL *clEnqueueMigrateMemObjectEXT_fn)(cl_command_queue command_queue, + cl_uint num_mem_objects, + const cl_mem * mem_objects, + cl_mem_migration_flags_ext flags, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event); + + +/********************************* +* cl_qcom_ext_host_ptr extension +*********************************/ +#define cl_qcom_ext_host_ptr 1 + +#define CL_MEM_EXT_HOST_PTR_QCOM (1 << 29) + +#define CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM 0x40A0 +#define CL_DEVICE_PAGE_SIZE_QCOM 0x40A1 +#define CL_IMAGE_ROW_ALIGNMENT_QCOM 0x40A2 +#define CL_IMAGE_SLICE_ALIGNMENT_QCOM 0x40A3 +#define CL_MEM_HOST_UNCACHED_QCOM 0x40A4 +#define CL_MEM_HOST_WRITEBACK_QCOM 0x40A5 +#define CL_MEM_HOST_WRITETHROUGH_QCOM 0x40A6 +#define CL_MEM_HOST_WRITE_COMBINING_QCOM 0x40A7 + +typedef cl_uint cl_image_pitch_info_qcom; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetDeviceImageInfoQCOM(cl_device_id device, + size_t image_width, + size_t image_height, + const cl_image_format *image_format, + cl_image_pitch_info_qcom param_name, + size_t param_value_size, + void *param_value, + size_t *param_value_size_ret); + +typedef struct _cl_mem_ext_host_ptr +{ + /* Type of external memory allocation. */ + /* Legal values will be defined in layered extensions. */ + cl_uint allocation_type; + + /* Host cache policy for this external memory allocation. */ + cl_uint host_cache_policy; + +} cl_mem_ext_host_ptr; + + +/******************************************* +* cl_qcom_ext_host_ptr_iocoherent extension +********************************************/ + +/* Cache policy specifying io-coherence */ +#define CL_MEM_HOST_IOCOHERENT_QCOM 0x40A9 + + +/********************************* +* cl_qcom_ion_host_ptr extension +*********************************/ + +#define CL_MEM_ION_HOST_PTR_QCOM 0x40A8 + +typedef struct _cl_mem_ion_host_ptr +{ + /* Type of external memory allocation. */ + /* Must be CL_MEM_ION_HOST_PTR_QCOM for ION allocations. */ + cl_mem_ext_host_ptr ext_host_ptr; + + /* ION file descriptor */ + int ion_filedesc; + + /* Host pointer to the ION allocated memory */ + void* ion_hostptr; + +} cl_mem_ion_host_ptr; + + +/********************************* +* cl_qcom_android_native_buffer_host_ptr extension +*********************************/ + +#define CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM 0x40C6 + +typedef struct _cl_mem_android_native_buffer_host_ptr +{ + /* Type of external memory allocation. */ + /* Must be CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM for Android native buffers. */ + cl_mem_ext_host_ptr ext_host_ptr; + + /* Virtual pointer to the android native buffer */ + void* anb_ptr; + +} cl_mem_android_native_buffer_host_ptr; + + +/****************************************** + * cl_img_yuv_image extension * + ******************************************/ + +/* Image formats used in clCreateImage */ +#define CL_NV21_IMG 0x40D0 +#define CL_YV12_IMG 0x40D1 + + +/****************************************** + * cl_img_cached_allocations extension * + ******************************************/ + +/* Flag values used by clCreateBuffer */ +#define CL_MEM_USE_UNCACHED_CPU_MEMORY_IMG (1 << 26) +#define CL_MEM_USE_CACHED_CPU_MEMORY_IMG (1 << 27) + + +/****************************************** + * cl_img_use_gralloc_ptr extension * + ******************************************/ +#define cl_img_use_gralloc_ptr 1 + +/* Flag values used by clCreateBuffer */ +#define CL_MEM_USE_GRALLOC_PTR_IMG (1 << 28) + +/* To be used by clGetEventInfo: */ +#define CL_COMMAND_ACQUIRE_GRALLOC_OBJECTS_IMG 0x40D2 +#define CL_COMMAND_RELEASE_GRALLOC_OBJECTS_IMG 0x40D3 + +/* Error code from clEnqueueReleaseGrallocObjectsIMG */ +#define CL_GRALLOC_RESOURCE_NOT_ACQUIRED_IMG 0x40D4 + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueAcquireGrallocObjectsIMG(cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueReleaseGrallocObjectsIMG(cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_2; + + +/********************************* +* cl_khr_subgroups extension +*********************************/ +#define cl_khr_subgroups 1 + +#if !defined(CL_VERSION_2_1) +/* For OpenCL 2.1 and newer, cl_kernel_sub_group_info is declared in CL.h. + In hindsight, there should have been a khr suffix on this type for + the extension, but keeping it un-suffixed to maintain backwards + compatibility. */ +typedef cl_uint cl_kernel_sub_group_info; +#endif + +/* cl_kernel_sub_group_info */ +#define CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE_KHR 0x2033 +#define CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE_KHR 0x2034 + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetKernelSubGroupInfoKHR(cl_kernel in_kernel, + cl_device_id in_device, + cl_kernel_sub_group_info param_name, + size_t input_value_size, + const void * input_value, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED; + +typedef CL_API_ENTRY cl_int +(CL_API_CALL * clGetKernelSubGroupInfoKHR_fn)(cl_kernel in_kernel, + cl_device_id in_device, + cl_kernel_sub_group_info param_name, + size_t input_value_size, + const void * input_value, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED; + + +/********************************* +* cl_khr_mipmap_image extension +*********************************/ + +/* cl_sampler_properties */ +#define CL_SAMPLER_MIP_FILTER_MODE_KHR 0x1155 +#define CL_SAMPLER_LOD_MIN_KHR 0x1156 +#define CL_SAMPLER_LOD_MAX_KHR 0x1157 + + +/********************************* +* cl_khr_priority_hints extension +*********************************/ +/* This extension define is for backwards compatibility. + It shouldn't be required since this extension has no new functions. */ +#define cl_khr_priority_hints 1 + +typedef cl_uint cl_queue_priority_khr; + +/* cl_command_queue_properties */ +#define CL_QUEUE_PRIORITY_KHR 0x1096 + +/* cl_queue_priority_khr */ +#define CL_QUEUE_PRIORITY_HIGH_KHR (1<<0) +#define CL_QUEUE_PRIORITY_MED_KHR (1<<1) +#define CL_QUEUE_PRIORITY_LOW_KHR (1<<2) + + +/********************************* +* cl_khr_throttle_hints extension +*********************************/ +/* This extension define is for backwards compatibility. + It shouldn't be required since this extension has no new functions. */ +#define cl_khr_throttle_hints 1 + +typedef cl_uint cl_queue_throttle_khr; + +/* cl_command_queue_properties */ +#define CL_QUEUE_THROTTLE_KHR 0x1097 + +/* cl_queue_throttle_khr */ +#define CL_QUEUE_THROTTLE_HIGH_KHR (1<<0) +#define CL_QUEUE_THROTTLE_MED_KHR (1<<1) +#define CL_QUEUE_THROTTLE_LOW_KHR (1<<2) + + +/********************************* +* cl_khr_subgroup_named_barrier +*********************************/ +/* This extension define is for backwards compatibility. + It shouldn't be required since this extension has no new functions. */ +#define cl_khr_subgroup_named_barrier 1 + +/* cl_device_info */ +#define CL_DEVICE_MAX_NAMED_BARRIER_COUNT_KHR 0x2035 + + +/********************************** + * cl_arm_import_memory extension * + **********************************/ +#define cl_arm_import_memory 1 + +typedef intptr_t cl_import_properties_arm; + +/* Default and valid proporties name for cl_arm_import_memory */ +#define CL_IMPORT_TYPE_ARM 0x40B2 + +/* Host process memory type default value for CL_IMPORT_TYPE_ARM property */ +#define CL_IMPORT_TYPE_HOST_ARM 0x40B3 + +/* DMA BUF memory type value for CL_IMPORT_TYPE_ARM property */ +#define CL_IMPORT_TYPE_DMA_BUF_ARM 0x40B4 + +/* Protected DMA BUF memory type value for CL_IMPORT_TYPE_ARM property */ +#define CL_IMPORT_TYPE_PROTECTED_ARM 0x40B5 + +/* This extension adds a new function that allows for direct memory import into + * OpenCL via the clImportMemoryARM function. + * + * Memory imported through this interface will be mapped into the device's page + * tables directly, providing zero copy access. It will never fall back to copy + * operations and aliased buffers. + * + * Types of memory supported for import are specified as additional extension + * strings. + * + * This extension produces cl_mem allocations which are compatible with all other + * users of cl_mem in the standard API. + * + * This extension maps pages with the same properties as the normal buffer creation + * function clCreateBuffer. + */ +extern CL_API_ENTRY cl_mem CL_API_CALL +clImportMemoryARM( cl_context context, + cl_mem_flags flags, + const cl_import_properties_arm *properties, + void *memory, + size_t size, + cl_int *errcode_ret) CL_EXT_SUFFIX__VERSION_1_0; + + +/****************************************** + * cl_arm_shared_virtual_memory extension * + ******************************************/ +#define cl_arm_shared_virtual_memory 1 + +/* Used by clGetDeviceInfo */ +#define CL_DEVICE_SVM_CAPABILITIES_ARM 0x40B6 + +/* Used by clGetMemObjectInfo */ +#define CL_MEM_USES_SVM_POINTER_ARM 0x40B7 + +/* Used by clSetKernelExecInfoARM: */ +#define CL_KERNEL_EXEC_INFO_SVM_PTRS_ARM 0x40B8 +#define CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM_ARM 0x40B9 + +/* To be used by clGetEventInfo: */ +#define CL_COMMAND_SVM_FREE_ARM 0x40BA +#define CL_COMMAND_SVM_MEMCPY_ARM 0x40BB +#define CL_COMMAND_SVM_MEMFILL_ARM 0x40BC +#define CL_COMMAND_SVM_MAP_ARM 0x40BD +#define CL_COMMAND_SVM_UNMAP_ARM 0x40BE + +/* Flag values returned by clGetDeviceInfo with CL_DEVICE_SVM_CAPABILITIES_ARM as the param_name. */ +#define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER_ARM (1 << 0) +#define CL_DEVICE_SVM_FINE_GRAIN_BUFFER_ARM (1 << 1) +#define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM_ARM (1 << 2) +#define CL_DEVICE_SVM_ATOMICS_ARM (1 << 3) + +/* Flag values used by clSVMAllocARM: */ +#define CL_MEM_SVM_FINE_GRAIN_BUFFER_ARM (1 << 10) +#define CL_MEM_SVM_ATOMICS_ARM (1 << 11) + +typedef cl_bitfield cl_svm_mem_flags_arm; +typedef cl_uint cl_kernel_exec_info_arm; +typedef cl_bitfield cl_device_svm_capabilities_arm; + +extern CL_API_ENTRY void * CL_API_CALL +clSVMAllocARM(cl_context context, + cl_svm_mem_flags_arm flags, + size_t size, + cl_uint alignment) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY void CL_API_CALL +clSVMFreeARM(cl_context context, + void * svm_pointer) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMFreeARM(cl_command_queue command_queue, + cl_uint num_svm_pointers, + void * svm_pointers[], + void (CL_CALLBACK * pfn_free_func)(cl_command_queue queue, + cl_uint num_svm_pointers, + void * svm_pointers[], + void * user_data), + void * user_data, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMMemcpyARM(cl_command_queue command_queue, + cl_bool blocking_copy, + void * dst_ptr, + const void * src_ptr, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMMemFillARM(cl_command_queue command_queue, + void * svm_ptr, + const void * pattern, + size_t pattern_size, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMMapARM(cl_command_queue command_queue, + cl_bool blocking_map, + cl_map_flags flags, + void * svm_ptr, + size_t size, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueSVMUnmapARM(cl_command_queue command_queue, + void * svm_ptr, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetKernelArgSVMPointerARM(cl_kernel kernel, + cl_uint arg_index, + const void * arg_value) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clSetKernelExecInfoARM(cl_kernel kernel, + cl_kernel_exec_info_arm param_name, + size_t param_value_size, + const void * param_value) CL_EXT_SUFFIX__VERSION_1_2; + +/******************************** + * cl_arm_get_core_id extension * + ********************************/ + +#ifdef CL_VERSION_1_2 + +#define cl_arm_get_core_id 1 + +/* Device info property for bitfield of cores present */ +#define CL_DEVICE_COMPUTE_UNITS_BITFIELD_ARM 0x40BF + +#endif /* CL_VERSION_1_2 */ + +/********************************* +* cl_arm_job_slot_selection +*********************************/ + +#define cl_arm_job_slot_selection 1 + +/* cl_device_info */ +#define CL_DEVICE_JOB_SLOTS_ARM 0x41E0 + +/* cl_command_queue_properties */ +#define CL_QUEUE_JOB_SLOT_ARM 0x41E1 + +#ifdef __cplusplus +} +#endif + + +#endif /* __CL_EXT_H */ diff --git a/benchmarks/new_opencl/include/CL/cl_ext_intel.h b/benchmarks/new_opencl/include/CL/cl_ext_intel.h new file mode 100644 index 00000000..9d1e4b58 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_ext_intel.h @@ -0,0 +1,423 @@ +/******************************************************************************* + * Copyright (c) 2008-2019 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + ******************************************************************************/ +/*****************************************************************************\ + +Copyright (c) 2013-2019 Intel Corporation All Rights Reserved. + +THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE +MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +File Name: cl_ext_intel.h + +Abstract: + +Notes: + +\*****************************************************************************/ + +#ifndef __CL_EXT_INTEL_H +#define __CL_EXT_INTEL_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*************************************** +* cl_intel_thread_local_exec extension * +****************************************/ + +#define cl_intel_thread_local_exec 1 + +#define CL_QUEUE_THREAD_LOCAL_EXEC_ENABLE_INTEL (((cl_bitfield)1) << 31) + +/*********************************************** +* cl_intel_device_partition_by_names extension * +************************************************/ + +#define cl_intel_device_partition_by_names 1 + +#define CL_DEVICE_PARTITION_BY_NAMES_INTEL 0x4052 +#define CL_PARTITION_BY_NAMES_LIST_END_INTEL -1 + +/************************************************ +* cl_intel_accelerator extension * +* cl_intel_motion_estimation extension * +* cl_intel_advanced_motion_estimation extension * +*************************************************/ + +#define cl_intel_accelerator 1 +#define cl_intel_motion_estimation 1 +#define cl_intel_advanced_motion_estimation 1 + +typedef struct _cl_accelerator_intel* cl_accelerator_intel; +typedef cl_uint cl_accelerator_type_intel; +typedef cl_uint cl_accelerator_info_intel; + +typedef struct _cl_motion_estimation_desc_intel { + cl_uint mb_block_type; + cl_uint subpixel_mode; + cl_uint sad_adjust_mode; + cl_uint search_path_type; +} cl_motion_estimation_desc_intel; + +/* error codes */ +#define CL_INVALID_ACCELERATOR_INTEL -1094 +#define CL_INVALID_ACCELERATOR_TYPE_INTEL -1095 +#define CL_INVALID_ACCELERATOR_DESCRIPTOR_INTEL -1096 +#define CL_ACCELERATOR_TYPE_NOT_SUPPORTED_INTEL -1097 + +/* cl_accelerator_type_intel */ +#define CL_ACCELERATOR_TYPE_MOTION_ESTIMATION_INTEL 0x0 + +/* cl_accelerator_info_intel */ +#define CL_ACCELERATOR_DESCRIPTOR_INTEL 0x4090 +#define CL_ACCELERATOR_REFERENCE_COUNT_INTEL 0x4091 +#define CL_ACCELERATOR_CONTEXT_INTEL 0x4092 +#define CL_ACCELERATOR_TYPE_INTEL 0x4093 + +/* cl_motion_detect_desc_intel flags */ +#define CL_ME_MB_TYPE_16x16_INTEL 0x0 +#define CL_ME_MB_TYPE_8x8_INTEL 0x1 +#define CL_ME_MB_TYPE_4x4_INTEL 0x2 + +#define CL_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0 +#define CL_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1 +#define CL_ME_SUBPIXEL_MODE_QPEL_INTEL 0x2 + +#define CL_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0 +#define CL_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x1 + +#define CL_ME_SEARCH_PATH_RADIUS_2_2_INTEL 0x0 +#define CL_ME_SEARCH_PATH_RADIUS_4_4_INTEL 0x1 +#define CL_ME_SEARCH_PATH_RADIUS_16_12_INTEL 0x5 + +#define CL_ME_SKIP_BLOCK_TYPE_16x16_INTEL 0x0 +#define CL_ME_CHROMA_INTRA_PREDICT_ENABLED_INTEL 0x1 +#define CL_ME_LUMA_INTRA_PREDICT_ENABLED_INTEL 0x2 +#define CL_ME_SKIP_BLOCK_TYPE_8x8_INTEL 0x4 + +#define CL_ME_FORWARD_INPUT_MODE_INTEL 0x1 +#define CL_ME_BACKWARD_INPUT_MODE_INTEL 0x2 +#define CL_ME_BIDIRECTION_INPUT_MODE_INTEL 0x3 + +#define CL_ME_BIDIR_WEIGHT_QUARTER_INTEL 16 +#define CL_ME_BIDIR_WEIGHT_THIRD_INTEL 21 +#define CL_ME_BIDIR_WEIGHT_HALF_INTEL 32 +#define CL_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 43 +#define CL_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 48 + +#define CL_ME_COST_PENALTY_NONE_INTEL 0x0 +#define CL_ME_COST_PENALTY_LOW_INTEL 0x1 +#define CL_ME_COST_PENALTY_NORMAL_INTEL 0x2 +#define CL_ME_COST_PENALTY_HIGH_INTEL 0x3 + +#define CL_ME_COST_PRECISION_QPEL_INTEL 0x0 +#define CL_ME_COST_PRECISION_HPEL_INTEL 0x1 +#define CL_ME_COST_PRECISION_PEL_INTEL 0x2 +#define CL_ME_COST_PRECISION_DPEL_INTEL 0x3 + +#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0 +#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 +#define CL_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2 +#define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3 + +#define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4 +#define CL_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4 +#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5 +#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6 +#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7 +#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8 + +#define CL_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0 +#define CL_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 +#define CL_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2 +#define CL_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3 + +/* cl_device_info */ +#define CL_DEVICE_ME_VERSION_INTEL 0x407E + +#define CL_ME_VERSION_LEGACY_INTEL 0x0 +#define CL_ME_VERSION_ADVANCED_VER_1_INTEL 0x1 +#define CL_ME_VERSION_ADVANCED_VER_2_INTEL 0x2 + +extern CL_API_ENTRY cl_accelerator_intel CL_API_CALL +clCreateAcceleratorINTEL( + cl_context context, + cl_accelerator_type_intel accelerator_type, + size_t descriptor_size, + const void* descriptor, + cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_accelerator_intel (CL_API_CALL *clCreateAcceleratorINTEL_fn)( + cl_context context, + cl_accelerator_type_intel accelerator_type, + size_t descriptor_size, + const void* descriptor, + cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetAcceleratorInfoINTEL( + cl_accelerator_intel accelerator, + cl_accelerator_info_intel param_name, + size_t param_value_size, + void* param_value, + size_t* param_value_size_ret) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetAcceleratorInfoINTEL_fn)( + cl_accelerator_intel accelerator, + cl_accelerator_info_intel param_name, + size_t param_value_size, + void* param_value, + size_t* param_value_size_ret) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clRetainAcceleratorINTEL( + cl_accelerator_intel accelerator) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clRetainAcceleratorINTEL_fn)( + cl_accelerator_intel accelerator) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clReleaseAcceleratorINTEL( + cl_accelerator_intel accelerator) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clReleaseAcceleratorINTEL_fn)( + cl_accelerator_intel accelerator) CL_EXT_SUFFIX__VERSION_1_2; + +/****************************************** +* cl_intel_simultaneous_sharing extension * +*******************************************/ + +#define cl_intel_simultaneous_sharing 1 + +#define CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL 0x4104 +#define CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL 0x4105 + +/*********************************** +* cl_intel_egl_image_yuv extension * +************************************/ + +#define cl_intel_egl_image_yuv 1 + +#define CL_EGL_YUV_PLANE_INTEL 0x4107 + +/******************************** +* cl_intel_packed_yuv extension * +*********************************/ + +#define cl_intel_packed_yuv 1 + +#define CL_YUYV_INTEL 0x4076 +#define CL_UYVY_INTEL 0x4077 +#define CL_YVYU_INTEL 0x4078 +#define CL_VYUY_INTEL 0x4079 + +/******************************************** +* cl_intel_required_subgroup_size extension * +*********************************************/ + +#define cl_intel_required_subgroup_size 1 + +#define CL_DEVICE_SUB_GROUP_SIZES_INTEL 0x4108 +#define CL_KERNEL_SPILL_MEM_SIZE_INTEL 0x4109 +#define CL_KERNEL_COMPILE_SUB_GROUP_SIZE_INTEL 0x410A + +/**************************************** +* cl_intel_driver_diagnostics extension * +*****************************************/ + +#define cl_intel_driver_diagnostics 1 + +typedef cl_uint cl_diagnostics_verbose_level; + +#define CL_CONTEXT_SHOW_DIAGNOSTICS_INTEL 0x4106 + +#define CL_CONTEXT_DIAGNOSTICS_LEVEL_ALL_INTEL ( 0xff ) +#define CL_CONTEXT_DIAGNOSTICS_LEVEL_GOOD_INTEL ( 1 ) +#define CL_CONTEXT_DIAGNOSTICS_LEVEL_BAD_INTEL ( 1 << 1 ) +#define CL_CONTEXT_DIAGNOSTICS_LEVEL_NEUTRAL_INTEL ( 1 << 2 ) + +/******************************** +* cl_intel_planar_yuv extension * +*********************************/ + +#define CL_NV12_INTEL 0x410E + +#define CL_MEM_NO_ACCESS_INTEL ( 1 << 24 ) +#define CL_MEM_ACCESS_FLAGS_UNRESTRICTED_INTEL ( 1 << 25 ) + +#define CL_DEVICE_PLANAR_YUV_MAX_WIDTH_INTEL 0x417E +#define CL_DEVICE_PLANAR_YUV_MAX_HEIGHT_INTEL 0x417F + +/******************************************************* +* cl_intel_device_side_avc_motion_estimation extension * +********************************************************/ + +#define CL_DEVICE_AVC_ME_VERSION_INTEL 0x410B +#define CL_DEVICE_AVC_ME_SUPPORTS_TEXTURE_SAMPLER_USE_INTEL 0x410C +#define CL_DEVICE_AVC_ME_SUPPORTS_PREEMPTION_INTEL 0x410D + +#define CL_AVC_ME_VERSION_0_INTEL 0x0; // No support. +#define CL_AVC_ME_VERSION_1_INTEL 0x1; // First supported version. + +#define CL_AVC_ME_MAJOR_16x16_INTEL 0x0 +#define CL_AVC_ME_MAJOR_16x8_INTEL 0x1 +#define CL_AVC_ME_MAJOR_8x16_INTEL 0x2 +#define CL_AVC_ME_MAJOR_8x8_INTEL 0x3 + +#define CL_AVC_ME_MINOR_8x8_INTEL 0x0 +#define CL_AVC_ME_MINOR_8x4_INTEL 0x1 +#define CL_AVC_ME_MINOR_4x8_INTEL 0x2 +#define CL_AVC_ME_MINOR_4x4_INTEL 0x3 + +#define CL_AVC_ME_MAJOR_FORWARD_INTEL 0x0 +#define CL_AVC_ME_MAJOR_BACKWARD_INTEL 0x1 +#define CL_AVC_ME_MAJOR_BIDIRECTIONAL_INTEL 0x2 + +#define CL_AVC_ME_PARTITION_MASK_ALL_INTEL 0x0 +#define CL_AVC_ME_PARTITION_MASK_16x16_INTEL 0x7E +#define CL_AVC_ME_PARTITION_MASK_16x8_INTEL 0x7D +#define CL_AVC_ME_PARTITION_MASK_8x16_INTEL 0x7B +#define CL_AVC_ME_PARTITION_MASK_8x8_INTEL 0x77 +#define CL_AVC_ME_PARTITION_MASK_8x4_INTEL 0x6F +#define CL_AVC_ME_PARTITION_MASK_4x8_INTEL 0x5F +#define CL_AVC_ME_PARTITION_MASK_4x4_INTEL 0x3F + +#define CL_AVC_ME_SEARCH_WINDOW_EXHAUSTIVE_INTEL 0x0 +#define CL_AVC_ME_SEARCH_WINDOW_SMALL_INTEL 0x1 +#define CL_AVC_ME_SEARCH_WINDOW_TINY_INTEL 0x2 +#define CL_AVC_ME_SEARCH_WINDOW_EXTRA_TINY_INTEL 0x3 +#define CL_AVC_ME_SEARCH_WINDOW_DIAMOND_INTEL 0x4 +#define CL_AVC_ME_SEARCH_WINDOW_LARGE_DIAMOND_INTEL 0x5 +#define CL_AVC_ME_SEARCH_WINDOW_RESERVED0_INTEL 0x6 +#define CL_AVC_ME_SEARCH_WINDOW_RESERVED1_INTEL 0x7 +#define CL_AVC_ME_SEARCH_WINDOW_CUSTOM_INTEL 0x8 +#define CL_AVC_ME_SEARCH_WINDOW_16x12_RADIUS_INTEL 0x9 +#define CL_AVC_ME_SEARCH_WINDOW_4x4_RADIUS_INTEL 0x2 +#define CL_AVC_ME_SEARCH_WINDOW_2x2_RADIUS_INTEL 0xa + +#define CL_AVC_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0 +#define CL_AVC_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x2 + +#define CL_AVC_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0 +#define CL_AVC_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1 +#define CL_AVC_ME_SUBPIXEL_MODE_QPEL_INTEL 0x3 + +#define CL_AVC_ME_COST_PRECISION_QPEL_INTEL 0x0 +#define CL_AVC_ME_COST_PRECISION_HPEL_INTEL 0x1 +#define CL_AVC_ME_COST_PRECISION_PEL_INTEL 0x2 +#define CL_AVC_ME_COST_PRECISION_DPEL_INTEL 0x3 + +#define CL_AVC_ME_BIDIR_WEIGHT_QUARTER_INTEL 0x10 +#define CL_AVC_ME_BIDIR_WEIGHT_THIRD_INTEL 0x15 +#define CL_AVC_ME_BIDIR_WEIGHT_HALF_INTEL 0x20 +#define CL_AVC_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 0x2B +#define CL_AVC_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 0x30 + +#define CL_AVC_ME_BORDER_REACHED_LEFT_INTEL 0x0 +#define CL_AVC_ME_BORDER_REACHED_RIGHT_INTEL 0x2 +#define CL_AVC_ME_BORDER_REACHED_TOP_INTEL 0x4 +#define CL_AVC_ME_BORDER_REACHED_BOTTOM_INTEL 0x8 + +#define CL_AVC_ME_SKIP_BLOCK_PARTITION_16x16_INTEL 0x0 +#define CL_AVC_ME_SKIP_BLOCK_PARTITION_8x8_INTEL 0x4000 + +#define CL_AVC_ME_SKIP_BLOCK_16x16_FORWARD_ENABLE_INTEL ( 0x1 << 24 ) +#define CL_AVC_ME_SKIP_BLOCK_16x16_BACKWARD_ENABLE_INTEL ( 0x2 << 24 ) +#define CL_AVC_ME_SKIP_BLOCK_16x16_DUAL_ENABLE_INTEL ( 0x3 << 24 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_FORWARD_ENABLE_INTEL ( 0x55 << 24 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_BACKWARD_ENABLE_INTEL ( 0xAA << 24 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_DUAL_ENABLE_INTEL ( 0xFF << 24 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_0_FORWARD_ENABLE_INTEL ( 0x1 << 24 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_0_BACKWARD_ENABLE_INTEL ( 0x2 << 24 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_1_FORWARD_ENABLE_INTEL ( 0x1 << 26 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_1_BACKWARD_ENABLE_INTEL ( 0x2 << 26 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_2_FORWARD_ENABLE_INTEL ( 0x1 << 28 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_2_BACKWARD_ENABLE_INTEL ( 0x2 << 28 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_3_FORWARD_ENABLE_INTEL ( 0x1 << 30 ) +#define CL_AVC_ME_SKIP_BLOCK_8x8_3_BACKWARD_ENABLE_INTEL ( 0x2 << 30 ) + +#define CL_AVC_ME_BLOCK_BASED_SKIP_4x4_INTEL 0x00 +#define CL_AVC_ME_BLOCK_BASED_SKIP_8x8_INTEL 0x80 + +#define CL_AVC_ME_INTRA_16x16_INTEL 0x0 +#define CL_AVC_ME_INTRA_8x8_INTEL 0x1 +#define CL_AVC_ME_INTRA_4x4_INTEL 0x2 + +#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_16x16_INTEL 0x6 +#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_8x8_INTEL 0x5 +#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_4x4_INTEL 0x3 + +#define CL_AVC_ME_INTRA_NEIGHBOR_LEFT_MASK_ENABLE_INTEL 0x60 +#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_MASK_ENABLE_INTEL 0x10 +#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_RIGHT_MASK_ENABLE_INTEL 0x8 +#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_LEFT_MASK_ENABLE_INTEL 0x4 + +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7 +#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8 +#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0 +#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 +#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2 +#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3 + +#define CL_AVC_ME_FRAME_FORWARD_INTEL 0x1 +#define CL_AVC_ME_FRAME_BACKWARD_INTEL 0x2 +#define CL_AVC_ME_FRAME_DUAL_INTEL 0x3 + +#define CL_AVC_ME_SLICE_TYPE_PRED_INTEL 0x0 +#define CL_AVC_ME_SLICE_TYPE_BPRED_INTEL 0x1 +#define CL_AVC_ME_SLICE_TYPE_INTRA_INTEL 0x2 + +#define CL_AVC_ME_INTERLACED_SCAN_TOP_FIELD_INTEL 0x0 +#define CL_AVC_ME_INTERLACED_SCAN_BOTTOM_FIELD_INTEL 0x1 + +#ifdef __cplusplus +} +#endif + +#endif /* __CL_EXT_INTEL_H */ diff --git a/benchmarks/new_opencl/include/CL/cl_gl.h b/benchmarks/new_opencl/include/CL/cl_gl.h new file mode 100644 index 00000000..fbdaf629 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_gl.h @@ -0,0 +1,171 @@ +/********************************************************************************** + * Copyright (c) 2008-2019 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + **********************************************************************************/ + +#ifndef __OPENCL_CL_GL_H +#define __OPENCL_CL_GL_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef cl_uint cl_gl_object_type; +typedef cl_uint cl_gl_texture_info; +typedef cl_uint cl_gl_platform_info; +typedef struct __GLsync *cl_GLsync; + +/* cl_gl_object_type = 0x2000 - 0x200F enum values are currently taken */ +#define CL_GL_OBJECT_BUFFER 0x2000 +#define CL_GL_OBJECT_TEXTURE2D 0x2001 +#define CL_GL_OBJECT_TEXTURE3D 0x2002 +#define CL_GL_OBJECT_RENDERBUFFER 0x2003 +#ifdef CL_VERSION_1_2 +#define CL_GL_OBJECT_TEXTURE2D_ARRAY 0x200E +#define CL_GL_OBJECT_TEXTURE1D 0x200F +#define CL_GL_OBJECT_TEXTURE1D_ARRAY 0x2010 +#define CL_GL_OBJECT_TEXTURE_BUFFER 0x2011 +#endif + +/* cl_gl_texture_info */ +#define CL_GL_TEXTURE_TARGET 0x2004 +#define CL_GL_MIPMAP_LEVEL 0x2005 +#ifdef CL_VERSION_1_2 +#define CL_GL_NUM_SAMPLES 0x2012 +#endif + + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateFromGLBuffer(cl_context context, + cl_mem_flags flags, + cl_GLuint bufobj, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +#ifdef CL_VERSION_1_2 + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateFromGLTexture(cl_context context, + cl_mem_flags flags, + cl_GLenum target, + cl_GLint miplevel, + cl_GLuint texture, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_2; + +#endif + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateFromGLRenderbuffer(cl_context context, + cl_mem_flags flags, + cl_GLuint renderbuffer, + cl_int * errcode_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetGLObjectInfo(cl_mem memobj, + cl_gl_object_type * gl_object_type, + cl_GLuint * gl_object_name) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetGLTextureInfo(cl_mem memobj, + cl_gl_texture_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueAcquireGLObjects(cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueReleaseGLObjects(cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem * mem_objects, + cl_uint num_events_in_wait_list, + const cl_event * event_wait_list, + cl_event * event) CL_API_SUFFIX__VERSION_1_0; + + +/* Deprecated OpenCL 1.1 APIs */ +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL +clCreateFromGLTexture2D(cl_context context, + cl_mem_flags flags, + cl_GLenum target, + cl_GLint miplevel, + cl_GLuint texture, + cl_int * errcode_ret) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL +clCreateFromGLTexture3D(cl_context context, + cl_mem_flags flags, + cl_GLenum target, + cl_GLint miplevel, + cl_GLuint texture, + cl_int * errcode_ret) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED; + +/* cl_khr_gl_sharing extension */ + +#define cl_khr_gl_sharing 1 + +typedef cl_uint cl_gl_context_info; + +/* Additional Error Codes */ +#define CL_INVALID_GL_SHAREGROUP_REFERENCE_KHR -1000 + +/* cl_gl_context_info */ +#define CL_CURRENT_DEVICE_FOR_GL_CONTEXT_KHR 0x2006 +#define CL_DEVICES_FOR_GL_CONTEXT_KHR 0x2007 + +/* Additional cl_context_properties */ +#define CL_GL_CONTEXT_KHR 0x2008 +#define CL_EGL_DISPLAY_KHR 0x2009 +#define CL_GLX_DISPLAY_KHR 0x200A +#define CL_WGL_HDC_KHR 0x200B +#define CL_CGL_SHAREGROUP_KHR 0x200C + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetGLContextInfoKHR(const cl_context_properties * properties, + cl_gl_context_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetGLContextInfoKHR_fn)( + const cl_context_properties * properties, + cl_gl_context_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret); + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_GL_H */ diff --git a/benchmarks/new_opencl/include/CL/cl_gl_ext.h b/benchmarks/new_opencl/include/CL/cl_gl_ext.h new file mode 100644 index 00000000..c26d31ab --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_gl_ext.h @@ -0,0 +1,52 @@ +/********************************************************************************** + * Copyright (c) 2008-2019 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + **********************************************************************************/ + +#ifndef __OPENCL_CL_GL_EXT_H +#define __OPENCL_CL_GL_EXT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + * cl_khr_gl_event extension + */ +#define CL_COMMAND_GL_FENCE_SYNC_OBJECT_KHR 0x200D + +extern CL_API_ENTRY cl_event CL_API_CALL +clCreateEventFromGLsyncKHR(cl_context context, + cl_GLsync cl_GLsync, + cl_int * errcode_ret) CL_EXT_SUFFIX__VERSION_1_1; + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_GL_EXT_H */ diff --git a/benchmarks/new_opencl/include/CL/cl_platform.h b/benchmarks/new_opencl/include/CL/cl_platform.h new file mode 100644 index 00000000..7f4ddea5 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_platform.h @@ -0,0 +1,1384 @@ +/********************************************************************************** + * Copyright (c) 2008-2018 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + **********************************************************************************/ + +#ifndef __CL_PLATFORM_H +#define __CL_PLATFORM_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(_WIN32) + #define CL_API_ENTRY + #define CL_API_CALL __stdcall + #define CL_CALLBACK __stdcall +#else + #define CL_API_ENTRY + #define CL_API_CALL + #define CL_CALLBACK +#endif + +/* + * Deprecation flags refer to the last version of the header in which the + * feature was not deprecated. + * + * E.g. VERSION_1_1_DEPRECATED means the feature is present in 1.1 without + * deprecation but is deprecated in versions later than 1.1. + */ + +#define CL_EXTENSION_WEAK_LINK +#define CL_API_SUFFIX__VERSION_1_0 +#define CL_EXT_SUFFIX__VERSION_1_0 +#define CL_API_SUFFIX__VERSION_1_1 +#define CL_EXT_SUFFIX__VERSION_1_1 +#define CL_API_SUFFIX__VERSION_1_2 +#define CL_EXT_SUFFIX__VERSION_1_2 +#define CL_API_SUFFIX__VERSION_2_0 +#define CL_EXT_SUFFIX__VERSION_2_0 +#define CL_API_SUFFIX__VERSION_2_1 +#define CL_EXT_SUFFIX__VERSION_2_1 +#define CL_API_SUFFIX__VERSION_2_2 +#define CL_EXT_SUFFIX__VERSION_2_2 + + +#ifdef __GNUC__ + #define CL_EXT_SUFFIX_DEPRECATED __attribute__((deprecated)) + #define CL_EXT_PREFIX_DEPRECATED +#elif defined(_WIN32) + #define CL_EXT_SUFFIX_DEPRECATED + #define CL_EXT_PREFIX_DEPRECATED __declspec(deprecated) +#else + #define CL_EXT_SUFFIX_DEPRECATED + #define CL_EXT_PREFIX_DEPRECATED +#endif + +#ifdef CL_USE_DEPRECATED_OPENCL_1_0_APIS + #define CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED + #define CL_EXT_PREFIX__VERSION_1_0_DEPRECATED +#else + #define CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED CL_EXT_SUFFIX_DEPRECATED + #define CL_EXT_PREFIX__VERSION_1_0_DEPRECATED CL_EXT_PREFIX_DEPRECATED +#endif + +#ifdef CL_USE_DEPRECATED_OPENCL_1_1_APIS + #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED + #define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED +#else + #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED CL_EXT_SUFFIX_DEPRECATED + #define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED CL_EXT_PREFIX_DEPRECATED +#endif + +#ifdef CL_USE_DEPRECATED_OPENCL_1_2_APIS + #define CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED + #define CL_EXT_PREFIX__VERSION_1_2_DEPRECATED +#else + #define CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED CL_EXT_SUFFIX_DEPRECATED + #define CL_EXT_PREFIX__VERSION_1_2_DEPRECATED CL_EXT_PREFIX_DEPRECATED + #endif + +#ifdef CL_USE_DEPRECATED_OPENCL_2_0_APIS + #define CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED + #define CL_EXT_PREFIX__VERSION_2_0_DEPRECATED +#else + #define CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED CL_EXT_SUFFIX_DEPRECATED + #define CL_EXT_PREFIX__VERSION_2_0_DEPRECATED CL_EXT_PREFIX_DEPRECATED +#endif + +#ifdef CL_USE_DEPRECATED_OPENCL_2_1_APIS + #define CL_EXT_SUFFIX__VERSION_2_1_DEPRECATED + #define CL_EXT_PREFIX__VERSION_2_1_DEPRECATED +#else + #define CL_EXT_SUFFIX__VERSION_2_1_DEPRECATED CL_EXT_SUFFIX_DEPRECATED + #define CL_EXT_PREFIX__VERSION_2_1_DEPRECATED CL_EXT_PREFIX_DEPRECATED +#endif + +#if (defined (_WIN32) && defined(_MSC_VER)) + +/* scalar types */ +typedef signed __int8 cl_char; +typedef unsigned __int8 cl_uchar; +typedef signed __int16 cl_short; +typedef unsigned __int16 cl_ushort; +typedef signed __int32 cl_int; +typedef unsigned __int32 cl_uint; +typedef signed __int64 cl_long; +typedef unsigned __int64 cl_ulong; + +typedef unsigned __int16 cl_half; +typedef float cl_float; +typedef double cl_double; + +/* Macro names and corresponding values defined by OpenCL */ +#define CL_CHAR_BIT 8 +#define CL_SCHAR_MAX 127 +#define CL_SCHAR_MIN (-127-1) +#define CL_CHAR_MAX CL_SCHAR_MAX +#define CL_CHAR_MIN CL_SCHAR_MIN +#define CL_UCHAR_MAX 255 +#define CL_SHRT_MAX 32767 +#define CL_SHRT_MIN (-32767-1) +#define CL_USHRT_MAX 65535 +#define CL_INT_MAX 2147483647 +#define CL_INT_MIN (-2147483647-1) +#define CL_UINT_MAX 0xffffffffU +#define CL_LONG_MAX ((cl_long) 0x7FFFFFFFFFFFFFFFLL) +#define CL_LONG_MIN ((cl_long) -0x7FFFFFFFFFFFFFFFLL - 1LL) +#define CL_ULONG_MAX ((cl_ulong) 0xFFFFFFFFFFFFFFFFULL) + +#define CL_FLT_DIG 6 +#define CL_FLT_MANT_DIG 24 +#define CL_FLT_MAX_10_EXP +38 +#define CL_FLT_MAX_EXP +128 +#define CL_FLT_MIN_10_EXP -37 +#define CL_FLT_MIN_EXP -125 +#define CL_FLT_RADIX 2 +#define CL_FLT_MAX 340282346638528859811704183484516925440.0f +#define CL_FLT_MIN 1.175494350822287507969e-38f +#define CL_FLT_EPSILON 1.1920928955078125e-7f + +#define CL_HALF_DIG 3 +#define CL_HALF_MANT_DIG 11 +#define CL_HALF_MAX_10_EXP +4 +#define CL_HALF_MAX_EXP +16 +#define CL_HALF_MIN_10_EXP -4 +#define CL_HALF_MIN_EXP -13 +#define CL_HALF_RADIX 2 +#define CL_HALF_MAX 65504.0f +#define CL_HALF_MIN 6.103515625e-05f +#define CL_HALF_EPSILON 9.765625e-04f + +#define CL_DBL_DIG 15 +#define CL_DBL_MANT_DIG 53 +#define CL_DBL_MAX_10_EXP +308 +#define CL_DBL_MAX_EXP +1024 +#define CL_DBL_MIN_10_EXP -307 +#define CL_DBL_MIN_EXP -1021 +#define CL_DBL_RADIX 2 +#define CL_DBL_MAX 1.7976931348623158e+308 +#define CL_DBL_MIN 2.225073858507201383090e-308 +#define CL_DBL_EPSILON 2.220446049250313080847e-16 + +#define CL_M_E 2.7182818284590452354 +#define CL_M_LOG2E 1.4426950408889634074 +#define CL_M_LOG10E 0.43429448190325182765 +#define CL_M_LN2 0.69314718055994530942 +#define CL_M_LN10 2.30258509299404568402 +#define CL_M_PI 3.14159265358979323846 +#define CL_M_PI_2 1.57079632679489661923 +#define CL_M_PI_4 0.78539816339744830962 +#define CL_M_1_PI 0.31830988618379067154 +#define CL_M_2_PI 0.63661977236758134308 +#define CL_M_2_SQRTPI 1.12837916709551257390 +#define CL_M_SQRT2 1.41421356237309504880 +#define CL_M_SQRT1_2 0.70710678118654752440 + +#define CL_M_E_F 2.718281828f +#define CL_M_LOG2E_F 1.442695041f +#define CL_M_LOG10E_F 0.434294482f +#define CL_M_LN2_F 0.693147181f +#define CL_M_LN10_F 2.302585093f +#define CL_M_PI_F 3.141592654f +#define CL_M_PI_2_F 1.570796327f +#define CL_M_PI_4_F 0.785398163f +#define CL_M_1_PI_F 0.318309886f +#define CL_M_2_PI_F 0.636619772f +#define CL_M_2_SQRTPI_F 1.128379167f +#define CL_M_SQRT2_F 1.414213562f +#define CL_M_SQRT1_2_F 0.707106781f + +#define CL_NAN (CL_INFINITY - CL_INFINITY) +#define CL_HUGE_VALF ((cl_float) 1e50) +#define CL_HUGE_VAL ((cl_double) 1e500) +#define CL_MAXFLOAT CL_FLT_MAX +#define CL_INFINITY CL_HUGE_VALF + +#else + +#include + +/* scalar types */ +typedef int8_t cl_char; +typedef uint8_t cl_uchar; +typedef int16_t cl_short; +typedef uint16_t cl_ushort; +typedef int32_t cl_int; +typedef uint32_t cl_uint; +typedef int64_t cl_long; +typedef uint64_t cl_ulong; + +typedef uint16_t cl_half; +typedef float cl_float; +typedef double cl_double; + +/* Macro names and corresponding values defined by OpenCL */ +#define CL_CHAR_BIT 8 +#define CL_SCHAR_MAX 127 +#define CL_SCHAR_MIN (-127-1) +#define CL_CHAR_MAX CL_SCHAR_MAX +#define CL_CHAR_MIN CL_SCHAR_MIN +#define CL_UCHAR_MAX 255 +#define CL_SHRT_MAX 32767 +#define CL_SHRT_MIN (-32767-1) +#define CL_USHRT_MAX 65535 +#define CL_INT_MAX 2147483647 +#define CL_INT_MIN (-2147483647-1) +#define CL_UINT_MAX 0xffffffffU +#define CL_LONG_MAX ((cl_long) 0x7FFFFFFFFFFFFFFFLL) +#define CL_LONG_MIN ((cl_long) -0x7FFFFFFFFFFFFFFFLL - 1LL) +#define CL_ULONG_MAX ((cl_ulong) 0xFFFFFFFFFFFFFFFFULL) + +#define CL_FLT_DIG 6 +#define CL_FLT_MANT_DIG 24 +#define CL_FLT_MAX_10_EXP +38 +#define CL_FLT_MAX_EXP +128 +#define CL_FLT_MIN_10_EXP -37 +#define CL_FLT_MIN_EXP -125 +#define CL_FLT_RADIX 2 +#define CL_FLT_MAX 340282346638528859811704183484516925440.0f +#define CL_FLT_MIN 1.175494350822287507969e-38f +#define CL_FLT_EPSILON 1.1920928955078125e-7f + +#define CL_HALF_DIG 3 +#define CL_HALF_MANT_DIG 11 +#define CL_HALF_MAX_10_EXP +4 +#define CL_HALF_MAX_EXP +16 +#define CL_HALF_MIN_10_EXP -4 +#define CL_HALF_MIN_EXP -13 +#define CL_HALF_RADIX 2 +#define CL_HALF_MAX 65504.0f +#define CL_HALF_MIN 6.103515625e-05f +#define CL_HALF_EPSILON 9.765625e-04f + +#define CL_DBL_DIG 15 +#define CL_DBL_MANT_DIG 53 +#define CL_DBL_MAX_10_EXP +308 +#define CL_DBL_MAX_EXP +1024 +#define CL_DBL_MIN_10_EXP -307 +#define CL_DBL_MIN_EXP -1021 +#define CL_DBL_RADIX 2 +#define CL_DBL_MAX 179769313486231570814527423731704356798070567525844996598917476803157260780028538760589558632766878171540458953514382464234321326889464182768467546703537516986049910576551282076245490090389328944075868508455133942304583236903222948165808559332123348274797826204144723168738177180919299881250404026184124858368.0 +#define CL_DBL_MIN 2.225073858507201383090e-308 +#define CL_DBL_EPSILON 2.220446049250313080847e-16 + +#define CL_M_E 2.7182818284590452354 +#define CL_M_LOG2E 1.4426950408889634074 +#define CL_M_LOG10E 0.43429448190325182765 +#define CL_M_LN2 0.69314718055994530942 +#define CL_M_LN10 2.30258509299404568402 +#define CL_M_PI 3.14159265358979323846 +#define CL_M_PI_2 1.57079632679489661923 +#define CL_M_PI_4 0.78539816339744830962 +#define CL_M_1_PI 0.31830988618379067154 +#define CL_M_2_PI 0.63661977236758134308 +#define CL_M_2_SQRTPI 1.12837916709551257390 +#define CL_M_SQRT2 1.41421356237309504880 +#define CL_M_SQRT1_2 0.70710678118654752440 + +#define CL_M_E_F 2.718281828f +#define CL_M_LOG2E_F 1.442695041f +#define CL_M_LOG10E_F 0.434294482f +#define CL_M_LN2_F 0.693147181f +#define CL_M_LN10_F 2.302585093f +#define CL_M_PI_F 3.141592654f +#define CL_M_PI_2_F 1.570796327f +#define CL_M_PI_4_F 0.785398163f +#define CL_M_1_PI_F 0.318309886f +#define CL_M_2_PI_F 0.636619772f +#define CL_M_2_SQRTPI_F 1.128379167f +#define CL_M_SQRT2_F 1.414213562f +#define CL_M_SQRT1_2_F 0.707106781f + +#if defined( __GNUC__ ) + #define CL_HUGE_VALF __builtin_huge_valf() + #define CL_HUGE_VAL __builtin_huge_val() + #define CL_NAN __builtin_nanf( "" ) +#else + #define CL_HUGE_VALF ((cl_float) 1e50) + #define CL_HUGE_VAL ((cl_double) 1e500) + float nanf( const char * ); + #define CL_NAN nanf( "" ) +#endif +#define CL_MAXFLOAT CL_FLT_MAX +#define CL_INFINITY CL_HUGE_VALF + +#endif + +#include + +/* Mirror types to GL types. Mirror types allow us to avoid deciding which 87s to load based on whether we are using GL or GLES here. */ +typedef unsigned int cl_GLuint; +typedef int cl_GLint; +typedef unsigned int cl_GLenum; + +/* + * Vector types + * + * Note: OpenCL requires that all types be naturally aligned. + * This means that vector types must be naturally aligned. + * For example, a vector of four floats must be aligned to + * a 16 byte boundary (calculated as 4 * the natural 4-byte + * alignment of the float). The alignment qualifiers here + * will only function properly if your compiler supports them + * and if you don't actively work to defeat them. For example, + * in order for a cl_float4 to be 16 byte aligned in a struct, + * the start of the struct must itself be 16-byte aligned. + * + * Maintaining proper alignment is the user's responsibility. + */ + +/* Define basic vector types */ +#if defined( __VEC__ ) + #include /* may be omitted depending on compiler. AltiVec spec provides no way to detect whether the header is required. */ + typedef __vector unsigned char __cl_uchar16; + typedef __vector signed char __cl_char16; + typedef __vector unsigned short __cl_ushort8; + typedef __vector signed short __cl_short8; + typedef __vector unsigned int __cl_uint4; + typedef __vector signed int __cl_int4; + typedef __vector float __cl_float4; + #define __CL_UCHAR16__ 1 + #define __CL_CHAR16__ 1 + #define __CL_USHORT8__ 1 + #define __CL_SHORT8__ 1 + #define __CL_UINT4__ 1 + #define __CL_INT4__ 1 + #define __CL_FLOAT4__ 1 +#endif + +#if defined( __SSE__ ) + #if defined( __MINGW64__ ) + #include + #else + #include + #endif + #if defined( __GNUC__ ) + typedef float __cl_float4 __attribute__((vector_size(16))); + #else + typedef __m128 __cl_float4; + #endif + #define __CL_FLOAT4__ 1 +#endif + +#if defined( __SSE2__ ) + #if defined( __MINGW64__ ) + #include + #else + #include + #endif + #if defined( __GNUC__ ) + typedef cl_uchar __cl_uchar16 __attribute__((vector_size(16))); + typedef cl_char __cl_char16 __attribute__((vector_size(16))); + typedef cl_ushort __cl_ushort8 __attribute__((vector_size(16))); + typedef cl_short __cl_short8 __attribute__((vector_size(16))); + typedef cl_uint __cl_uint4 __attribute__((vector_size(16))); + typedef cl_int __cl_int4 __attribute__((vector_size(16))); + typedef cl_ulong __cl_ulong2 __attribute__((vector_size(16))); + typedef cl_long __cl_long2 __attribute__((vector_size(16))); + typedef cl_double __cl_double2 __attribute__((vector_size(16))); + #else + typedef __m128i __cl_uchar16; + typedef __m128i __cl_char16; + typedef __m128i __cl_ushort8; + typedef __m128i __cl_short8; + typedef __m128i __cl_uint4; + typedef __m128i __cl_int4; + typedef __m128i __cl_ulong2; + typedef __m128i __cl_long2; + typedef __m128d __cl_double2; + #endif + #define __CL_UCHAR16__ 1 + #define __CL_CHAR16__ 1 + #define __CL_USHORT8__ 1 + #define __CL_SHORT8__ 1 + #define __CL_INT4__ 1 + #define __CL_UINT4__ 1 + #define __CL_ULONG2__ 1 + #define __CL_LONG2__ 1 + #define __CL_DOUBLE2__ 1 +#endif + +#if defined( __MMX__ ) + #include + #if defined( __GNUC__ ) + typedef cl_uchar __cl_uchar8 __attribute__((vector_size(8))); + typedef cl_char __cl_char8 __attribute__((vector_size(8))); + typedef cl_ushort __cl_ushort4 __attribute__((vector_size(8))); + typedef cl_short __cl_short4 __attribute__((vector_size(8))); + typedef cl_uint __cl_uint2 __attribute__((vector_size(8))); + typedef cl_int __cl_int2 __attribute__((vector_size(8))); + typedef cl_ulong __cl_ulong1 __attribute__((vector_size(8))); + typedef cl_long __cl_long1 __attribute__((vector_size(8))); + typedef cl_float __cl_float2 __attribute__((vector_size(8))); + #else + typedef __m64 __cl_uchar8; + typedef __m64 __cl_char8; + typedef __m64 __cl_ushort4; + typedef __m64 __cl_short4; + typedef __m64 __cl_uint2; + typedef __m64 __cl_int2; + typedef __m64 __cl_ulong1; + typedef __m64 __cl_long1; + typedef __m64 __cl_float2; + #endif + #define __CL_UCHAR8__ 1 + #define __CL_CHAR8__ 1 + #define __CL_USHORT4__ 1 + #define __CL_SHORT4__ 1 + #define __CL_INT2__ 1 + #define __CL_UINT2__ 1 + #define __CL_ULONG1__ 1 + #define __CL_LONG1__ 1 + #define __CL_FLOAT2__ 1 +#endif + +#if defined( __AVX__ ) + #if defined( __MINGW64__ ) + #include + #else + #include + #endif + #if defined( __GNUC__ ) + typedef cl_float __cl_float8 __attribute__((vector_size(32))); + typedef cl_double __cl_double4 __attribute__((vector_size(32))); + #else + typedef __m256 __cl_float8; + typedef __m256d __cl_double4; + #endif + #define __CL_FLOAT8__ 1 + #define __CL_DOUBLE4__ 1 +#endif + +/* Define capabilities for anonymous struct members. */ +#if !defined(__cplusplus) && defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define __CL_HAS_ANON_STRUCT__ 1 +#define __CL_ANON_STRUCT__ +#elif defined( __GNUC__) && ! defined( __STRICT_ANSI__ ) +#define __CL_HAS_ANON_STRUCT__ 1 +#define __CL_ANON_STRUCT__ __extension__ +#elif defined( _WIN32) && defined(_MSC_VER) + #if _MSC_VER >= 1500 + /* Microsoft Developer Studio 2008 supports anonymous structs, but + * complains by default. */ + #define __CL_HAS_ANON_STRUCT__ 1 + #define __CL_ANON_STRUCT__ + /* Disable warning C4201: nonstandard extension used : nameless + * struct/union */ + #pragma warning( push ) + #pragma warning( disable : 4201 ) + #endif +#else +#define __CL_HAS_ANON_STRUCT__ 0 +#define __CL_ANON_STRUCT__ +#endif + +/* Define alignment keys */ +#if defined( __GNUC__ ) + #define CL_ALIGNED(_x) __attribute__ ((aligned(_x))) +#elif defined( _WIN32) && (_MSC_VER) + /* Alignment keys neutered on windows because MSVC can't swallow function arguments with alignment requirements */ + /* http://msdn.microsoft.com/en-us/library/373ak2y1%28VS.71%29.aspx */ + /* #include */ + /* #define CL_ALIGNED(_x) _CRT_ALIGN(_x) */ + #define CL_ALIGNED(_x) +#else + #warning Need to implement some method to align data here + #define CL_ALIGNED(_x) +#endif + +/* Indicate whether .xyzw, .s0123 and .hi.lo are supported */ +#if __CL_HAS_ANON_STRUCT__ + /* .xyzw and .s0123...{f|F} are supported */ + #define CL_HAS_NAMED_VECTOR_FIELDS 1 + /* .hi and .lo are supported */ + #define CL_HAS_HI_LO_VECTOR_FIELDS 1 +#endif + +/* Define cl_vector types */ + +/* ---- cl_charn ---- */ +typedef union +{ + cl_char CL_ALIGNED(2) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_char x, y; }; + __CL_ANON_STRUCT__ struct{ cl_char s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_char lo, hi; }; +#endif +#if defined( __CL_CHAR2__) + __cl_char2 v2; +#endif +}cl_char2; + +typedef union +{ + cl_char CL_ALIGNED(4) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_char x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_char s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_char2 lo, hi; }; +#endif +#if defined( __CL_CHAR2__) + __cl_char2 v2[2]; +#endif +#if defined( __CL_CHAR4__) + __cl_char4 v4; +#endif +}cl_char4; + +/* cl_char3 is identical in size, alignment and behavior to cl_char4. See section 6.1.5. */ +typedef cl_char4 cl_char3; + +typedef union +{ + cl_char CL_ALIGNED(8) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_char x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_char s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_char4 lo, hi; }; +#endif +#if defined( __CL_CHAR2__) + __cl_char2 v2[4]; +#endif +#if defined( __CL_CHAR4__) + __cl_char4 v4[2]; +#endif +#if defined( __CL_CHAR8__ ) + __cl_char8 v8; +#endif +}cl_char8; + +typedef union +{ + cl_char CL_ALIGNED(16) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_char x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_char s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_char8 lo, hi; }; +#endif +#if defined( __CL_CHAR2__) + __cl_char2 v2[8]; +#endif +#if defined( __CL_CHAR4__) + __cl_char4 v4[4]; +#endif +#if defined( __CL_CHAR8__ ) + __cl_char8 v8[2]; +#endif +#if defined( __CL_CHAR16__ ) + __cl_char16 v16; +#endif +}cl_char16; + + +/* ---- cl_ucharn ---- */ +typedef union +{ + cl_uchar CL_ALIGNED(2) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_uchar x, y; }; + __CL_ANON_STRUCT__ struct{ cl_uchar s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_uchar lo, hi; }; +#endif +#if defined( __cl_uchar2__) + __cl_uchar2 v2; +#endif +}cl_uchar2; + +typedef union +{ + cl_uchar CL_ALIGNED(4) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_uchar x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_uchar s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_uchar2 lo, hi; }; +#endif +#if defined( __CL_UCHAR2__) + __cl_uchar2 v2[2]; +#endif +#if defined( __CL_UCHAR4__) + __cl_uchar4 v4; +#endif +}cl_uchar4; + +/* cl_uchar3 is identical in size, alignment and behavior to cl_uchar4. See section 6.1.5. */ +typedef cl_uchar4 cl_uchar3; + +typedef union +{ + cl_uchar CL_ALIGNED(8) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_uchar x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_uchar s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_uchar4 lo, hi; }; +#endif +#if defined( __CL_UCHAR2__) + __cl_uchar2 v2[4]; +#endif +#if defined( __CL_UCHAR4__) + __cl_uchar4 v4[2]; +#endif +#if defined( __CL_UCHAR8__ ) + __cl_uchar8 v8; +#endif +}cl_uchar8; + +typedef union +{ + cl_uchar CL_ALIGNED(16) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_uchar x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_uchar s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_uchar8 lo, hi; }; +#endif +#if defined( __CL_UCHAR2__) + __cl_uchar2 v2[8]; +#endif +#if defined( __CL_UCHAR4__) + __cl_uchar4 v4[4]; +#endif +#if defined( __CL_UCHAR8__ ) + __cl_uchar8 v8[2]; +#endif +#if defined( __CL_UCHAR16__ ) + __cl_uchar16 v16; +#endif +}cl_uchar16; + + +/* ---- cl_shortn ---- */ +typedef union +{ + cl_short CL_ALIGNED(4) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_short x, y; }; + __CL_ANON_STRUCT__ struct{ cl_short s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_short lo, hi; }; +#endif +#if defined( __CL_SHORT2__) + __cl_short2 v2; +#endif +}cl_short2; + +typedef union +{ + cl_short CL_ALIGNED(8) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_short x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_short s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_short2 lo, hi; }; +#endif +#if defined( __CL_SHORT2__) + __cl_short2 v2[2]; +#endif +#if defined( __CL_SHORT4__) + __cl_short4 v4; +#endif +}cl_short4; + +/* cl_short3 is identical in size, alignment and behavior to cl_short4. See section 6.1.5. */ +typedef cl_short4 cl_short3; + +typedef union +{ + cl_short CL_ALIGNED(16) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_short x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_short s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_short4 lo, hi; }; +#endif +#if defined( __CL_SHORT2__) + __cl_short2 v2[4]; +#endif +#if defined( __CL_SHORT4__) + __cl_short4 v4[2]; +#endif +#if defined( __CL_SHORT8__ ) + __cl_short8 v8; +#endif +}cl_short8; + +typedef union +{ + cl_short CL_ALIGNED(32) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_short x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_short s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_short8 lo, hi; }; +#endif +#if defined( __CL_SHORT2__) + __cl_short2 v2[8]; +#endif +#if defined( __CL_SHORT4__) + __cl_short4 v4[4]; +#endif +#if defined( __CL_SHORT8__ ) + __cl_short8 v8[2]; +#endif +#if defined( __CL_SHORT16__ ) + __cl_short16 v16; +#endif +}cl_short16; + + +/* ---- cl_ushortn ---- */ +typedef union +{ + cl_ushort CL_ALIGNED(4) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_ushort x, y; }; + __CL_ANON_STRUCT__ struct{ cl_ushort s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_ushort lo, hi; }; +#endif +#if defined( __CL_USHORT2__) + __cl_ushort2 v2; +#endif +}cl_ushort2; + +typedef union +{ + cl_ushort CL_ALIGNED(8) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_ushort x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_ushort s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_ushort2 lo, hi; }; +#endif +#if defined( __CL_USHORT2__) + __cl_ushort2 v2[2]; +#endif +#if defined( __CL_USHORT4__) + __cl_ushort4 v4; +#endif +}cl_ushort4; + +/* cl_ushort3 is identical in size, alignment and behavior to cl_ushort4. See section 6.1.5. */ +typedef cl_ushort4 cl_ushort3; + +typedef union +{ + cl_ushort CL_ALIGNED(16) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_ushort x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_ushort s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_ushort4 lo, hi; }; +#endif +#if defined( __CL_USHORT2__) + __cl_ushort2 v2[4]; +#endif +#if defined( __CL_USHORT4__) + __cl_ushort4 v4[2]; +#endif +#if defined( __CL_USHORT8__ ) + __cl_ushort8 v8; +#endif +}cl_ushort8; + +typedef union +{ + cl_ushort CL_ALIGNED(32) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_ushort x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_ushort s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_ushort8 lo, hi; }; +#endif +#if defined( __CL_USHORT2__) + __cl_ushort2 v2[8]; +#endif +#if defined( __CL_USHORT4__) + __cl_ushort4 v4[4]; +#endif +#if defined( __CL_USHORT8__ ) + __cl_ushort8 v8[2]; +#endif +#if defined( __CL_USHORT16__ ) + __cl_ushort16 v16; +#endif +}cl_ushort16; + + +/* ---- cl_halfn ---- */ +typedef union +{ + cl_half CL_ALIGNED(4) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_half x, y; }; + __CL_ANON_STRUCT__ struct{ cl_half s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_half lo, hi; }; +#endif +#if defined( __CL_HALF2__) + __cl_half2 v2; +#endif +}cl_half2; + +typedef union +{ + cl_half CL_ALIGNED(8) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_half x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_half s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_half2 lo, hi; }; +#endif +#if defined( __CL_HALF2__) + __cl_half2 v2[2]; +#endif +#if defined( __CL_HALF4__) + __cl_half4 v4; +#endif +}cl_half4; + +/* cl_half3 is identical in size, alignment and behavior to cl_half4. See section 6.1.5. */ +typedef cl_half4 cl_half3; + +typedef union +{ + cl_half CL_ALIGNED(16) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_half x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_half s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_half4 lo, hi; }; +#endif +#if defined( __CL_HALF2__) + __cl_half2 v2[4]; +#endif +#if defined( __CL_HALF4__) + __cl_half4 v4[2]; +#endif +#if defined( __CL_HALF8__ ) + __cl_half8 v8; +#endif +}cl_half8; + +typedef union +{ + cl_half CL_ALIGNED(32) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_half x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_half s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_half8 lo, hi; }; +#endif +#if defined( __CL_HALF2__) + __cl_half2 v2[8]; +#endif +#if defined( __CL_HALF4__) + __cl_half4 v4[4]; +#endif +#if defined( __CL_HALF8__ ) + __cl_half8 v8[2]; +#endif +#if defined( __CL_HALF16__ ) + __cl_half16 v16; +#endif +}cl_half16; + +/* ---- cl_intn ---- */ +typedef union +{ + cl_int CL_ALIGNED(8) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_int x, y; }; + __CL_ANON_STRUCT__ struct{ cl_int s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_int lo, hi; }; +#endif +#if defined( __CL_INT2__) + __cl_int2 v2; +#endif +}cl_int2; + +typedef union +{ + cl_int CL_ALIGNED(16) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_int x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_int s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_int2 lo, hi; }; +#endif +#if defined( __CL_INT2__) + __cl_int2 v2[2]; +#endif +#if defined( __CL_INT4__) + __cl_int4 v4; +#endif +}cl_int4; + +/* cl_int3 is identical in size, alignment and behavior to cl_int4. See section 6.1.5. */ +typedef cl_int4 cl_int3; + +typedef union +{ + cl_int CL_ALIGNED(32) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_int x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_int s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_int4 lo, hi; }; +#endif +#if defined( __CL_INT2__) + __cl_int2 v2[4]; +#endif +#if defined( __CL_INT4__) + __cl_int4 v4[2]; +#endif +#if defined( __CL_INT8__ ) + __cl_int8 v8; +#endif +}cl_int8; + +typedef union +{ + cl_int CL_ALIGNED(64) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_int x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_int s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_int8 lo, hi; }; +#endif +#if defined( __CL_INT2__) + __cl_int2 v2[8]; +#endif +#if defined( __CL_INT4__) + __cl_int4 v4[4]; +#endif +#if defined( __CL_INT8__ ) + __cl_int8 v8[2]; +#endif +#if defined( __CL_INT16__ ) + __cl_int16 v16; +#endif +}cl_int16; + + +/* ---- cl_uintn ---- */ +typedef union +{ + cl_uint CL_ALIGNED(8) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_uint x, y; }; + __CL_ANON_STRUCT__ struct{ cl_uint s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_uint lo, hi; }; +#endif +#if defined( __CL_UINT2__) + __cl_uint2 v2; +#endif +}cl_uint2; + +typedef union +{ + cl_uint CL_ALIGNED(16) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_uint x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_uint s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_uint2 lo, hi; }; +#endif +#if defined( __CL_UINT2__) + __cl_uint2 v2[2]; +#endif +#if defined( __CL_UINT4__) + __cl_uint4 v4; +#endif +}cl_uint4; + +/* cl_uint3 is identical in size, alignment and behavior to cl_uint4. See section 6.1.5. */ +typedef cl_uint4 cl_uint3; + +typedef union +{ + cl_uint CL_ALIGNED(32) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_uint x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_uint s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_uint4 lo, hi; }; +#endif +#if defined( __CL_UINT2__) + __cl_uint2 v2[4]; +#endif +#if defined( __CL_UINT4__) + __cl_uint4 v4[2]; +#endif +#if defined( __CL_UINT8__ ) + __cl_uint8 v8; +#endif +}cl_uint8; + +typedef union +{ + cl_uint CL_ALIGNED(64) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_uint x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_uint s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_uint8 lo, hi; }; +#endif +#if defined( __CL_UINT2__) + __cl_uint2 v2[8]; +#endif +#if defined( __CL_UINT4__) + __cl_uint4 v4[4]; +#endif +#if defined( __CL_UINT8__ ) + __cl_uint8 v8[2]; +#endif +#if defined( __CL_UINT16__ ) + __cl_uint16 v16; +#endif +}cl_uint16; + +/* ---- cl_longn ---- */ +typedef union +{ + cl_long CL_ALIGNED(16) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_long x, y; }; + __CL_ANON_STRUCT__ struct{ cl_long s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_long lo, hi; }; +#endif +#if defined( __CL_LONG2__) + __cl_long2 v2; +#endif +}cl_long2; + +typedef union +{ + cl_long CL_ALIGNED(32) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_long x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_long s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_long2 lo, hi; }; +#endif +#if defined( __CL_LONG2__) + __cl_long2 v2[2]; +#endif +#if defined( __CL_LONG4__) + __cl_long4 v4; +#endif +}cl_long4; + +/* cl_long3 is identical in size, alignment and behavior to cl_long4. See section 6.1.5. */ +typedef cl_long4 cl_long3; + +typedef union +{ + cl_long CL_ALIGNED(64) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_long x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_long s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_long4 lo, hi; }; +#endif +#if defined( __CL_LONG2__) + __cl_long2 v2[4]; +#endif +#if defined( __CL_LONG4__) + __cl_long4 v4[2]; +#endif +#if defined( __CL_LONG8__ ) + __cl_long8 v8; +#endif +}cl_long8; + +typedef union +{ + cl_long CL_ALIGNED(128) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_long x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_long s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_long8 lo, hi; }; +#endif +#if defined( __CL_LONG2__) + __cl_long2 v2[8]; +#endif +#if defined( __CL_LONG4__) + __cl_long4 v4[4]; +#endif +#if defined( __CL_LONG8__ ) + __cl_long8 v8[2]; +#endif +#if defined( __CL_LONG16__ ) + __cl_long16 v16; +#endif +}cl_long16; + + +/* ---- cl_ulongn ---- */ +typedef union +{ + cl_ulong CL_ALIGNED(16) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_ulong x, y; }; + __CL_ANON_STRUCT__ struct{ cl_ulong s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_ulong lo, hi; }; +#endif +#if defined( __CL_ULONG2__) + __cl_ulong2 v2; +#endif +}cl_ulong2; + +typedef union +{ + cl_ulong CL_ALIGNED(32) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_ulong x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_ulong s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_ulong2 lo, hi; }; +#endif +#if defined( __CL_ULONG2__) + __cl_ulong2 v2[2]; +#endif +#if defined( __CL_ULONG4__) + __cl_ulong4 v4; +#endif +}cl_ulong4; + +/* cl_ulong3 is identical in size, alignment and behavior to cl_ulong4. See section 6.1.5. */ +typedef cl_ulong4 cl_ulong3; + +typedef union +{ + cl_ulong CL_ALIGNED(64) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_ulong x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_ulong s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_ulong4 lo, hi; }; +#endif +#if defined( __CL_ULONG2__) + __cl_ulong2 v2[4]; +#endif +#if defined( __CL_ULONG4__) + __cl_ulong4 v4[2]; +#endif +#if defined( __CL_ULONG8__ ) + __cl_ulong8 v8; +#endif +}cl_ulong8; + +typedef union +{ + cl_ulong CL_ALIGNED(128) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_ulong x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_ulong s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_ulong8 lo, hi; }; +#endif +#if defined( __CL_ULONG2__) + __cl_ulong2 v2[8]; +#endif +#if defined( __CL_ULONG4__) + __cl_ulong4 v4[4]; +#endif +#if defined( __CL_ULONG8__ ) + __cl_ulong8 v8[2]; +#endif +#if defined( __CL_ULONG16__ ) + __cl_ulong16 v16; +#endif +}cl_ulong16; + + +/* --- cl_floatn ---- */ + +typedef union +{ + cl_float CL_ALIGNED(8) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_float x, y; }; + __CL_ANON_STRUCT__ struct{ cl_float s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_float lo, hi; }; +#endif +#if defined( __CL_FLOAT2__) + __cl_float2 v2; +#endif +}cl_float2; + +typedef union +{ + cl_float CL_ALIGNED(16) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_float x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_float s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_float2 lo, hi; }; +#endif +#if defined( __CL_FLOAT2__) + __cl_float2 v2[2]; +#endif +#if defined( __CL_FLOAT4__) + __cl_float4 v4; +#endif +}cl_float4; + +/* cl_float3 is identical in size, alignment and behavior to cl_float4. See section 6.1.5. */ +typedef cl_float4 cl_float3; + +typedef union +{ + cl_float CL_ALIGNED(32) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_float x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_float s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_float4 lo, hi; }; +#endif +#if defined( __CL_FLOAT2__) + __cl_float2 v2[4]; +#endif +#if defined( __CL_FLOAT4__) + __cl_float4 v4[2]; +#endif +#if defined( __CL_FLOAT8__ ) + __cl_float8 v8; +#endif +}cl_float8; + +typedef union +{ + cl_float CL_ALIGNED(64) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_float x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_float s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_float8 lo, hi; }; +#endif +#if defined( __CL_FLOAT2__) + __cl_float2 v2[8]; +#endif +#if defined( __CL_FLOAT4__) + __cl_float4 v4[4]; +#endif +#if defined( __CL_FLOAT8__ ) + __cl_float8 v8[2]; +#endif +#if defined( __CL_FLOAT16__ ) + __cl_float16 v16; +#endif +}cl_float16; + +/* --- cl_doublen ---- */ + +typedef union +{ + cl_double CL_ALIGNED(16) s[2]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_double x, y; }; + __CL_ANON_STRUCT__ struct{ cl_double s0, s1; }; + __CL_ANON_STRUCT__ struct{ cl_double lo, hi; }; +#endif +#if defined( __CL_DOUBLE2__) + __cl_double2 v2; +#endif +}cl_double2; + +typedef union +{ + cl_double CL_ALIGNED(32) s[4]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_double x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_double s0, s1, s2, s3; }; + __CL_ANON_STRUCT__ struct{ cl_double2 lo, hi; }; +#endif +#if defined( __CL_DOUBLE2__) + __cl_double2 v2[2]; +#endif +#if defined( __CL_DOUBLE4__) + __cl_double4 v4; +#endif +}cl_double4; + +/* cl_double3 is identical in size, alignment and behavior to cl_double4. See section 6.1.5. */ +typedef cl_double4 cl_double3; + +typedef union +{ + cl_double CL_ALIGNED(64) s[8]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_double x, y, z, w; }; + __CL_ANON_STRUCT__ struct{ cl_double s0, s1, s2, s3, s4, s5, s6, s7; }; + __CL_ANON_STRUCT__ struct{ cl_double4 lo, hi; }; +#endif +#if defined( __CL_DOUBLE2__) + __cl_double2 v2[4]; +#endif +#if defined( __CL_DOUBLE4__) + __cl_double4 v4[2]; +#endif +#if defined( __CL_DOUBLE8__ ) + __cl_double8 v8; +#endif +}cl_double8; + +typedef union +{ + cl_double CL_ALIGNED(128) s[16]; +#if __CL_HAS_ANON_STRUCT__ + __CL_ANON_STRUCT__ struct{ cl_double x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; }; + __CL_ANON_STRUCT__ struct{ cl_double s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; }; + __CL_ANON_STRUCT__ struct{ cl_double8 lo, hi; }; +#endif +#if defined( __CL_DOUBLE2__) + __cl_double2 v2[8]; +#endif +#if defined( __CL_DOUBLE4__) + __cl_double4 v4[4]; +#endif +#if defined( __CL_DOUBLE8__ ) + __cl_double8 v8[2]; +#endif +#if defined( __CL_DOUBLE16__ ) + __cl_double16 v16; +#endif +}cl_double16; + +/* Macro to facilitate debugging + * Usage: + * Place CL_PROGRAM_STRING_DEBUG_INFO on the line before the first line of your source. + * The first line ends with: CL_PROGRAM_STRING_DEBUG_INFO \" + * Each line thereafter of OpenCL C source must end with: \n\ + * The last line ends in "; + * + * Example: + * + * const char *my_program = CL_PROGRAM_STRING_DEBUG_INFO "\ + * kernel void foo( int a, float * b ) \n\ + * { \n\ + * // my comment \n\ + * *b[ get_global_id(0)] = a; \n\ + * } \n\ + * "; + * + * This should correctly set up the line, (column) and file information for your source + * string so you can do source level debugging. + */ +#define __CL_STRINGIFY( _x ) # _x +#define _CL_STRINGIFY( _x ) __CL_STRINGIFY( _x ) +#define CL_PROGRAM_STRING_DEBUG_INFO "#line " _CL_STRINGIFY(__LINE__) " \"" __FILE__ "\" \n\n" + +#ifdef __cplusplus +} +#endif + +#undef __CL_HAS_ANON_STRUCT__ +#undef __CL_ANON_STRUCT__ +#if defined( _WIN32) && defined(_MSC_VER) + #if _MSC_VER >=1500 + #pragma warning( pop ) + #endif +#endif + +#endif /* __CL_PLATFORM_H */ diff --git a/benchmarks/new_opencl/include/CL/cl_va_api_media_sharing_intel.h b/benchmarks/new_opencl/include/CL/cl_va_api_media_sharing_intel.h new file mode 100644 index 00000000..934f3f52 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_va_api_media_sharing_intel.h @@ -0,0 +1,172 @@ +/********************************************************************************** + * Copyright (c) 2008-2019 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + **********************************************************************************/ +/*****************************************************************************\ + +Copyright (c) 2013-2019 Intel Corporation All Rights Reserved. + +THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE +MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +File Name: cl_va_api_media_sharing_intel.h + +Abstract: + +Notes: + +\*****************************************************************************/ + + +#ifndef __OPENCL_CL_VA_API_MEDIA_SHARING_INTEL_H +#define __OPENCL_CL_VA_API_MEDIA_SHARING_INTEL_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************** +* cl_intel_va_api_media_sharing extension * +*******************************************/ + +#define cl_intel_va_api_media_sharing 1 + +/* error codes */ +#define CL_INVALID_VA_API_MEDIA_ADAPTER_INTEL -1098 +#define CL_INVALID_VA_API_MEDIA_SURFACE_INTEL -1099 +#define CL_VA_API_MEDIA_SURFACE_ALREADY_ACQUIRED_INTEL -1100 +#define CL_VA_API_MEDIA_SURFACE_NOT_ACQUIRED_INTEL -1101 + +/* cl_va_api_device_source_intel */ +#define CL_VA_API_DISPLAY_INTEL 0x4094 + +/* cl_va_api_device_set_intel */ +#define CL_PREFERRED_DEVICES_FOR_VA_API_INTEL 0x4095 +#define CL_ALL_DEVICES_FOR_VA_API_INTEL 0x4096 + +/* cl_context_info */ +#define CL_CONTEXT_VA_API_DISPLAY_INTEL 0x4097 + +/* cl_mem_info */ +#define CL_MEM_VA_API_MEDIA_SURFACE_INTEL 0x4098 + +/* cl_image_info */ +#define CL_IMAGE_VA_API_PLANE_INTEL 0x4099 + +/* cl_command_type */ +#define CL_COMMAND_ACQUIRE_VA_API_MEDIA_SURFACES_INTEL 0x409A +#define CL_COMMAND_RELEASE_VA_API_MEDIA_SURFACES_INTEL 0x409B + +typedef cl_uint cl_va_api_device_source_intel; +typedef cl_uint cl_va_api_device_set_intel; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetDeviceIDsFromVA_APIMediaAdapterINTEL( + cl_platform_id platform, + cl_va_api_device_source_intel media_adapter_type, + void* media_adapter, + cl_va_api_device_set_intel media_adapter_set, + cl_uint num_entries, + cl_device_id* devices, + cl_uint* num_devices) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL * clGetDeviceIDsFromVA_APIMediaAdapterINTEL_fn)( + cl_platform_id platform, + cl_va_api_device_source_intel media_adapter_type, + void* media_adapter, + cl_va_api_device_set_intel media_adapter_set, + cl_uint num_entries, + cl_device_id* devices, + cl_uint* num_devices) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_mem CL_API_CALL +clCreateFromVA_APIMediaSurfaceINTEL( + cl_context context, + cl_mem_flags flags, + VASurfaceID* surface, + cl_uint plane, + cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_mem (CL_API_CALL * clCreateFromVA_APIMediaSurfaceINTEL_fn)( + cl_context context, + cl_mem_flags flags, + VASurfaceID* surface, + cl_uint plane, + cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueAcquireVA_APIMediaSurfacesINTEL( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem* mem_objects, + cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, + cl_event* event) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireVA_APIMediaSurfacesINTEL_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem* mem_objects, + cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, + cl_event* event) CL_EXT_SUFFIX__VERSION_1_2; + +extern CL_API_ENTRY cl_int CL_API_CALL +clEnqueueReleaseVA_APIMediaSurfacesINTEL( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem* mem_objects, + cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, + cl_event* event) CL_EXT_SUFFIX__VERSION_1_2; + +typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseVA_APIMediaSurfacesINTEL_fn)( + cl_command_queue command_queue, + cl_uint num_objects, + const cl_mem* mem_objects, + cl_uint num_events_in_wait_list, + const cl_event* event_wait_list, + cl_event* event) CL_EXT_SUFFIX__VERSION_1_2; + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_CL_VA_API_MEDIA_SHARING_INTEL_H */ + diff --git a/benchmarks/new_opencl/include/CL/cl_version.h b/benchmarks/new_opencl/include/CL/cl_version.h new file mode 100644 index 00000000..bb766cb9 --- /dev/null +++ b/benchmarks/new_opencl/include/CL/cl_version.h @@ -0,0 +1,86 @@ +/******************************************************************************* + * Copyright (c) 2018 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + ******************************************************************************/ + +#ifndef __CL_VERSION_H +#define __CL_VERSION_H + +/* Detect which version to target */ +#if !defined(CL_TARGET_OPENCL_VERSION) +#pragma message("cl_version.h: CL_TARGET_OPENCL_VERSION is not defined. Defaulting to 220 (OpenCL 2.2)") +#define CL_TARGET_OPENCL_VERSION 220 +#endif +#if CL_TARGET_OPENCL_VERSION != 100 && \ + CL_TARGET_OPENCL_VERSION != 110 && \ + CL_TARGET_OPENCL_VERSION != 120 && \ + CL_TARGET_OPENCL_VERSION != 200 && \ + CL_TARGET_OPENCL_VERSION != 210 && \ + CL_TARGET_OPENCL_VERSION != 220 +#pragma message("cl_version: CL_TARGET_OPENCL_VERSION is not a valid value (100, 110, 120, 200, 210, 220). Defaulting to 220 (OpenCL 2.2)") +#undef CL_TARGET_OPENCL_VERSION +#define CL_TARGET_OPENCL_VERSION 220 +#endif + + +/* OpenCL Version */ +#if CL_TARGET_OPENCL_VERSION >= 220 && !defined(CL_VERSION_2_2) +#define CL_VERSION_2_2 1 +#endif +#if CL_TARGET_OPENCL_VERSION >= 210 && !defined(CL_VERSION_2_1) +#define CL_VERSION_2_1 1 +#endif +#if CL_TARGET_OPENCL_VERSION >= 200 && !defined(CL_VERSION_2_0) +#define CL_VERSION_2_0 1 +#endif +#if CL_TARGET_OPENCL_VERSION >= 120 && !defined(CL_VERSION_1_2) +#define CL_VERSION_1_2 1 +#endif +#if CL_TARGET_OPENCL_VERSION >= 110 && !defined(CL_VERSION_1_1) +#define CL_VERSION_1_1 1 +#endif +#if CL_TARGET_OPENCL_VERSION >= 100 && !defined(CL_VERSION_1_0) +#define CL_VERSION_1_0 1 +#endif + +/* Allow deprecated APIs for older OpenCL versions. */ +#if CL_TARGET_OPENCL_VERSION <= 210 && !defined(CL_USE_DEPRECATED_OPENCL_2_1_APIS) +#define CL_USE_DEPRECATED_OPENCL_2_1_APIS +#endif +#if CL_TARGET_OPENCL_VERSION <= 200 && !defined(CL_USE_DEPRECATED_OPENCL_2_0_APIS) +#define CL_USE_DEPRECATED_OPENCL_2_0_APIS +#endif +#if CL_TARGET_OPENCL_VERSION <= 120 && !defined(CL_USE_DEPRECATED_OPENCL_1_2_APIS) +#define CL_USE_DEPRECATED_OPENCL_1_2_APIS +#endif +#if CL_TARGET_OPENCL_VERSION <= 110 && !defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS) +#define CL_USE_DEPRECATED_OPENCL_1_1_APIS +#endif +#if CL_TARGET_OPENCL_VERSION <= 100 && !defined(CL_USE_DEPRECATED_OPENCL_1_0_APIS) +#define CL_USE_DEPRECATED_OPENCL_1_0_APIS +#endif + +#endif /* __CL_VERSION_H */ diff --git a/benchmarks/new_opencl/include/CL/opencl.h b/benchmarks/new_opencl/include/CL/opencl.h new file mode 100644 index 00000000..143d1d2d --- /dev/null +++ b/benchmarks/new_opencl/include/CL/opencl.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2008-2015 The Khronos Group Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and/or associated documentation files (the + * "Materials"), to deal in the Materials without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Materials, and to + * permit persons to whom the Materials are furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Materials. + * + * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS + * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS + * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT + * https://www.khronos.org/registry/ + * + * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. + ******************************************************************************/ + +/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */ + +#ifndef __OPENCL_H +#define __OPENCL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#ifdef __cplusplus +} +#endif + +#endif /* __OPENCL_H */ diff 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+++ b/benchmarks/new_opencl/nearn/README.txt @@ -0,0 +1,33 @@ +The Nearest Neighbor application computes the nearest location to a specific +latitude and longitude for a number of hurricanes (data from: http://weather.unisys.com/hurricane/). + +The Makefile may need to be adjusted for different machines, but it was written for Mac OS X and +Linux with either NVIDIA or AMD OpenCL SDKs. + +The hurricane data is located in a number of data files that are copied into the working +directory by the Makefile. A separate text file lists the names of the data files that +will be used, and it is this text file that should be passed to the application (see usage, below). + +Nearest Neighbor Usage + +nearestNeighbor [filename] -r [int] -lat [float] -lng [float] [-hqt] [-p [int] -d [int]] + +example: +$ ./nearestNeighbor filelist.txt -r 5 -lat 30 -lng 90 + +filename the filename that lists the data input files +-r [int] the number of records to return (default: 10) +-lat [float] the latitude for nearest neighbors (default: 0) +-lng [float] the longitude for nearest neighbors (default: 0) + +-h, --help Display the help file +-q Quiet mode. Suppress all text output. +-t Print timing information. + +-p [int] Choose the platform (must choose both platform and device) +-d [int] Choose the device (must choose both platform and device) + + +Notes: 1. The filename is required as the first parameter. + 2. If you declare either the device or the platform, + you must declare both. diff --git a/benchmarks/new_opencl/nearn/cane4_0.db b/benchmarks/new_opencl/nearn/cane4_0.db new file mode 100755 index 00000000..26ddcbd2 --- /dev/null +++ b/benchmarks/new_opencl/nearn/cane4_0.db @@ -0,0 +1,10691 @@ +1992 3 22 0 7 ALBERTO 66.5 79.2 129 899 +1961 4 8 12 12 LESLIE 26.5 34.3 143 792 +1962 2 2 0 8 ERNESTO 35.9 33.6 93 336 +1991 4 26 12 24 WILLIAM 27.9 59.9 135 196 +1986 5 10 0 27 GORDON 34.1 334.3 55 803 +1962 8 24 12 10 GORDON 48.1 145.3 10 670 +1999 3 9 12 24 KIRK 52.7 335.6 98 219 +1998 9 23 0 6 WILLIAM 47.3 237.4 120 878 +1980 11 6 12 18 SANDY 15.8 84.2 153 47 +1951 1 17 12 17 SANDY 42.6 293.8 60 642 +1997 4 5 18 23 VALERIE 7.6 6.9 142 644 +1952 12 24 6 20 ISAAC 66.9 46.5 31 804 +1957 6 25 12 27 GORDON 37.1 86.6 24 792 +1952 9 26 0 4 ISAAC 12.5 11.1 89 307 +1979 6 21 0 22 TONY 55.6 259.2 84 71 +1962 10 4 12 11 LESLIE 51.7 110.4 64 161 +1952 12 22 0 15 VALERIE 14.2 74.6 46 792 +1985 3 19 0 20 HELENE 46.6 78.2 46 314 +1975 9 2 12 10 GORDON 64.6 88.5 114 331 +1981 3 6 6 18 VALERIE 12.1 257.0 100 376 +1957 8 4 12 22 NADINE 45.0 9.8 132 538 +1983 1 17 18 10 PATTY 17.9 177.8 83 202 +1997 10 8 0 10 KIRK 52.9 195.4 119 376 +2000 3 23 12 5 FLORENCE 69.3 256.9 35 87 +1981 2 11 6 26 OSCAR 14.8 24.5 85 421 +1964 9 6 6 5 KIRK 21.6 199.9 29 262 +1984 1 14 0 27 ALBERTO 37.3 94.5 28 655 +1985 9 23 6 4 LESLIE 49.5 276.5 117 462 +1960 10 16 0 2 HELENE 14.5 79.9 157 781 +1995 7 16 12 12 SANDY 29.1 135.3 57 70 +1988 8 13 18 24 HELENE 63.6 72.4 151 561 +2002 12 17 12 24 GORDON 21.3 342.0 54 124 +1962 7 21 6 22 LESLIE 35.5 163.9 43 16 +1955 1 10 18 9 JOYCE 49.3 162.1 44 461 +2002 9 21 0 12 ALBERTO 33.1 195.0 79 637 +1983 7 5 18 23 OSCAR 43.6 301.0 37 715 +1981 1 11 12 25 DEBBY 27.2 344.5 59 23 +1993 1 1 6 10 PATTY 24.5 27.8 63 468 +1963 3 18 18 8 HELENE 7.4 342.9 131 783 +2004 11 15 6 7 BERYL 48.2 164.4 82 195 +1992 9 15 12 28 GORDON 23.5 300.5 131 727 +1970 3 12 0 24 NADINE 19.5 117.1 155 269 +1956 7 19 6 9 BERYL 19.6 164.3 17 807 +1989 5 16 0 1 PATTY 57.8 21.6 46 96 +1951 1 17 18 23 BERYL 30.5 140.9 117 544 +1977 4 9 18 7 ALBERTO 15.5 193.1 163 151 +1989 8 6 12 19 LESLIE 63.3 327.5 92 629 +1962 11 19 18 5 WILLIAM 54.6 255.3 147 219 +1955 1 3 12 11 PATTY 52.7 289.4 26 884 +1962 4 7 0 2 ERNESTO 50.2 90.7 161 182 +1960 5 10 12 9 ISAAC 45.5 20.4 21 198 +1968 4 19 0 3 DEBBY 68.9 197.4 148 356 +1976 7 6 0 11 BERYL 55.9 115.0 37 42 +1986 5 22 0 17 MICHAEL 65.1 176.9 142 552 +1986 8 9 18 18 NADINE 25.9 213.1 31 189 +1993 4 1 6 21 SANDY 33.8 212.3 100 359 +1958 3 23 0 12 TONY 17.0 114.5 98 517 +1958 6 6 6 11 ERNESTO 65.4 33.0 78 813 +1950 6 2 0 26 FLORENCE 43.3 166.8 100 775 +1988 2 11 12 20 WILLIAM 41.6 177.4 152 312 +1992 2 26 0 9 KIRK 47.1 259.7 16 439 +1954 10 24 6 11 MICHAEL 18.6 351.6 70 320 +1998 2 2 18 15 ERNESTO 53.6 240.5 143 674 +1990 5 9 12 8 KIRK 45.4 35.1 68 801 +2002 2 6 6 20 FLORENCE 30.3 53.2 81 351 +1995 1 6 6 2 ISAAC 28.0 309.1 120 130 +1956 7 8 12 4 MICHAEL 27.0 10.2 98 5 +1976 10 4 6 20 FLORENCE 34.1 38.6 134 466 +1977 4 21 0 4 OSCAR 15.7 66.9 76 187 +1961 8 19 0 1 GORDON 20.2 241.1 92 46 +1969 4 10 6 22 WILLIAM 40.4 97.7 108 774 +1972 9 5 6 11 KIRK 26.2 284.5 163 370 +1959 2 4 18 23 ERNESTO 55.2 232.7 53 753 +1976 3 4 12 7 KIRK 15.5 4.0 127 187 +1951 9 12 18 7 VALERIE 54.1 163.7 102 407 +1980 3 22 6 14 GORDON 10.9 57.1 59 289 +1984 8 9 0 13 RAFAEL 45.0 200.2 147 302 +1974 6 9 18 27 ISAAC 32.7 176.5 62 501 +2004 4 2 0 10 JOYCE 18.9 65.4 109 823 +1982 4 17 18 7 TONY 14.9 150.2 129 288 +1980 11 20 0 11 GORDON 52.3 190.0 111 825 +1992 3 5 0 25 BERYL 31.6 355.5 14 273 +1954 2 2 18 8 JOYCE 36.8 113.0 67 618 +1987 5 23 18 19 CHRIS 41.4 316.2 10 748 +1951 9 21 18 2 KIRK 34.7 336.2 72 899 +1958 5 8 18 11 GORDON 10.8 29.7 134 765 +1976 9 10 12 18 WILLIAM 35.2 214.0 113 463 +1980 10 10 6 4 CHRIS 41.6 270.7 61 857 +1955 1 11 6 9 NADINE 55.6 175.4 113 780 +1971 8 27 6 22 ISAAC 13.1 50.9 49 388 +1952 10 16 18 10 RAFAEL 26.7 54.4 115 502 +1961 9 18 6 14 VALERIE 43.9 336.2 32 790 +1972 6 14 18 28 DEBBY 47.1 63.0 78 684 +1963 3 9 6 26 HELENE 67.2 326.7 91 283 +1999 6 16 18 5 OSCAR 29.7 144.3 161 243 +1974 6 20 12 20 ERNESTO 18.4 288.5 132 805 +1963 5 8 0 22 ISAAC 51.5 8.3 89 664 +1994 4 28 12 18 OSCAR 28.1 162.6 74 517 +2001 11 1 12 11 VALERIE 49.6 250.9 46 217 +1974 12 9 12 10 GORDON 37.2 350.1 53 868 +1965 1 10 12 22 TONY 60.8 45.6 82 77 +1985 10 1 18 9 ERNESTO 64.6 111.5 115 24 +1968 8 21 12 14 FLORENCE 48.2 162.3 114 659 +1966 7 27 18 10 OSCAR 53.8 46.8 111 826 +1972 10 6 18 11 BERYL 65.7 204.4 50 133 +1962 8 15 0 27 ERNESTO 36.5 82.5 113 148 +1994 10 14 0 19 WILLIAM 62.6 51.0 16 844 +1989 11 11 6 27 DEBBY 47.3 113.0 46 484 +1962 4 12 0 9 DEBBY 29.7 354.9 61 300 +1998 2 23 6 25 DEBBY 45.6 243.0 34 804 +1959 3 13 6 24 WILLIAM 27.3 37.3 160 488 +1960 5 27 18 10 CHRIS 34.3 64.3 56 238 +1956 7 13 0 27 NADINE 41.1 281.4 10 808 +1965 9 25 6 25 ALBERTO 32.5 131.8 123 183 +1997 4 4 18 22 JOYCE 38.8 338.1 106 297 +1968 1 15 6 23 BERYL 37.0 213.5 130 121 +1977 4 12 0 20 LESLIE 65.1 143.3 66 640 +1958 1 28 6 7 KIRK 37.2 117.6 51 145 +2000 2 26 12 4 SANDY 50.2 287.6 120 624 +1969 7 13 6 26 BERYL 27.2 20.1 101 326 +1985 3 1 12 12 CHRIS 27.2 244.7 152 93 +1973 12 1 0 7 DEBBY 19.9 61.4 104 570 +1986 4 7 0 25 JOYCE 46.6 351.9 64 504 +1994 1 1 6 9 ALBERTO 12.1 48.6 14 680 +1988 12 18 18 13 VALERIE 18.1 128.8 43 398 +1978 4 2 18 7 RAFAEL 41.7 192.7 107 766 +2002 7 6 12 10 HELENE 26.1 278.8 146 18 +1981 2 28 6 6 FLORENCE 28.7 135.5 119 814 +2002 3 17 12 19 DEBBY 32.6 162.6 154 771 +1975 3 20 18 7 HELENE 21.0 127.7 72 408 +1997 6 28 0 19 NADINE 21.8 23.5 137 471 +1975 9 10 0 22 DEBBY 57.6 192.2 46 762 +1972 5 23 18 14 SANDY 41.2 183.6 55 147 +1958 6 5 12 20 FLORENCE 44.9 110.8 20 781 +1990 10 25 6 28 MICHAEL 49.4 266.3 27 71 +2002 12 6 12 15 OSCAR 64.6 0.9 50 76 +1955 9 22 12 16 WILLIAM 19.0 226.7 137 467 +1957 9 8 18 27 RAFAEL 52.9 226.4 139 680 +1976 8 24 18 22 WILLIAM 18.3 171.6 20 809 +1997 6 2 0 9 HELENE 12.3 244.0 57 837 +1994 5 18 0 20 SANDY 15.4 276.7 60 624 +1992 2 4 12 19 OSCAR 61.9 134.2 12 166 +1975 7 9 18 10 LESLIE 21.0 332.5 38 873 +1978 4 21 18 23 MICHAEL 12.8 122.0 116 94 +1978 2 21 12 7 GORDON 46.5 267.5 105 242 +1952 12 18 6 2 RAFAEL 23.0 213.4 127 329 +1997 10 10 0 25 FLORENCE 9.8 40.9 98 747 +1983 11 26 12 4 WILLIAM 16.7 170.7 108 775 +1969 7 18 0 9 PATTY 45.5 8.1 130 4 +1976 12 9 12 10 WILLIAM 63.2 38.4 110 620 +1975 7 15 6 20 OSCAR 61.2 310.5 51 472 +1950 4 18 6 19 TONY 20.4 69.1 126 579 +1973 5 27 18 20 CHRIS 17.9 95.2 98 449 +1992 4 11 0 18 GORDON 55.6 235.4 77 69 +1953 9 15 12 22 MICHAEL 29.1 303.7 40 365 +1951 8 16 0 26 BERYL 52.1 183.2 85 723 +1958 11 2 6 17 KIRK 69.4 119.3 66 507 +1950 4 28 18 27 ALBERTO 56.6 13.3 118 800 +1969 3 11 18 22 WILLIAM 32.2 49.4 79 153 +1995 9 7 12 22 GORDON 49.2 202.6 64 822 +1996 8 20 18 15 MICHAEL 16.4 74.5 154 107 +1971 6 28 12 17 KIRK 69.6 242.9 61 649 +1952 1 17 12 13 ALBERTO 61.9 295.7 59 648 +2002 12 21 18 5 DEBBY 65.6 304.3 66 180 +1954 9 14 12 19 CHRIS 60.9 58.8 124 741 +2003 1 2 18 25 FLORENCE 35.2 138.8 155 452 +1989 5 27 12 27 ALBERTO 20.5 298.1 109 852 +1983 10 17 6 9 LESLIE 29.6 109.9 137 124 +1983 12 22 0 3 GORDON 59.3 54.2 159 288 +1983 6 21 18 14 NADINE 24.9 213.5 135 711 +1956 5 2 12 21 NADINE 16.9 192.0 144 883 +1989 7 25 6 18 MICHAEL 61.2 219.3 28 24 +1992 5 11 0 24 HELENE 32.7 274.0 119 445 +1957 12 22 18 28 PATTY 62.6 2.8 12 253 +1979 9 12 0 7 RAFAEL 51.1 176.6 80 696 +2002 7 11 0 4 ERNESTO 64.9 171.1 122 854 +1971 7 25 12 2 SANDY 14.1 262.9 36 182 +1958 8 14 0 23 ISAAC 42.2 239.4 30 214 +1965 1 28 6 16 CHRIS 26.9 281.5 101 178 +1973 3 21 18 6 KIRK 22.5 78.3 37 681 +1969 9 24 18 28 PATTY 20.1 351.5 43 128 +1950 10 6 0 26 NADINE 67.4 311.7 96 470 +1991 7 12 6 27 PATTY 26.8 154.6 162 347 +2004 7 21 0 3 ALBERTO 20.3 63.9 31 897 +1982 5 23 12 5 WILLIAM 65.6 333.4 43 511 +1993 6 2 18 7 BERYL 12.9 148.9 133 174 +1957 2 20 0 12 DEBBY 16.9 307.2 97 81 +1963 4 8 12 24 CHRIS 30.7 206.8 120 519 +1996 2 13 0 8 ALBERTO 50.8 300.0 137 425 +1996 6 22 18 5 WILLIAM 36.4 95.6 150 603 +1968 2 3 18 1 ISAAC 11.9 131.3 157 881 +1997 4 26 6 6 MICHAEL 59.9 286.7 36 326 +1984 3 20 0 14 PATTY 34.7 287.0 112 241 +1995 2 22 18 28 LESLIE 11.3 344.7 81 183 +1982 7 27 0 16 CHRIS 27.4 156.7 38 295 +1950 11 4 12 20 FLORENCE 37.5 111.1 116 334 +1974 1 13 6 2 HELENE 42.1 102.9 141 241 +1998 2 2 0 19 ISAAC 24.5 200.0 81 794 +1989 1 16 6 14 NADINE 42.9 313.5 98 632 +1964 6 20 12 28 WILLIAM 36.0 19.3 55 646 +1988 1 18 0 12 HELENE 35.5 197.4 109 876 +1967 2 5 6 10 OSCAR 65.8 196.7 28 801 +1985 5 3 18 6 VALERIE 41.3 12.3 103 815 +1995 3 9 6 21 BERYL 56.9 51.0 115 785 +2001 11 16 12 20 KIRK 66.7 343.0 115 820 +1965 9 7 12 16 PATTY 35.1 253.1 152 508 +1981 2 15 0 24 MICHAEL 52.1 216.5 86 444 +1958 3 16 18 13 OSCAR 16.3 181.3 13 402 +1982 11 25 12 17 DEBBY 34.4 110.2 87 423 +1972 12 8 0 5 GORDON 19.6 333.1 82 659 +1992 7 23 6 8 ERNESTO 13.9 316.1 152 388 +1981 12 2 12 9 VALERIE 58.0 151.1 23 781 +1958 1 10 6 8 LESLIE 15.1 2.0 141 753 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41.7 161 428 +2002 4 11 18 25 LESLIE 43.9 105.9 113 200 +2002 11 4 12 13 WILLIAM 56.0 65.1 155 758 +1987 10 7 18 1 MICHAEL 51.6 11.0 135 839 +1964 6 12 6 6 OSCAR 45.1 157.2 137 479 +1979 9 16 12 20 SANDY 56.5 4.1 76 795 +1950 11 23 12 13 GORDON 13.2 215.7 150 279 +1963 3 1 6 20 VALERIE 50.9 170.5 57 115 +1961 11 7 18 14 ALBERTO 35.5 101.8 124 712 +1998 2 8 6 15 VALERIE 20.3 280.9 124 393 +1994 2 9 6 2 ISAAC 48.0 45.4 122 324 +1969 7 26 0 27 ISAAC 25.4 350.9 120 732 +1967 5 5 0 6 FLORENCE 16.7 278.0 88 131 +1973 6 6 12 5 JOYCE 22.2 36.0 11 22 +1978 2 6 18 1 LESLIE 16.4 39.5 81 347 +1989 2 18 12 8 CHRIS 38.4 286.6 87 391 +1985 7 13 0 23 NADINE 62.0 316.1 19 654 +1985 2 17 12 13 NADINE 18.0 324.2 109 39 +1971 6 22 18 9 DEBBY 48.7 298.0 128 118 +1962 5 27 6 9 RAFAEL 26.0 66.5 70 134 +1959 10 12 18 9 PATTY 21.7 309.8 154 727 +1999 6 8 12 24 RAFAEL 8.2 188.7 86 88 +1974 11 6 6 19 BERYL 26.8 284.8 12 374 +1977 4 7 18 17 BERYL 42.9 289.4 139 847 +1968 5 2 18 24 GORDON 61.5 351.8 73 709 +1967 3 23 0 2 SANDY 34.3 334.1 158 514 +1984 4 9 12 26 ERNESTO 44.5 39.6 141 152 +1977 7 3 18 16 TONY 52.0 11.6 32 264 +1964 8 7 0 5 CHRIS 46.2 133.0 28 76 +1977 2 13 6 13 WILLIAM 36.4 53.7 52 157 +1953 4 19 18 19 GORDON 55.2 137.5 45 259 +1987 8 11 18 20 CHRIS 51.9 112.6 47 332 +1952 6 4 0 1 BERYL 24.9 143.4 95 23 +2003 12 8 18 22 LESLIE 56.5 77.1 125 654 +1955 6 14 18 2 JOYCE 69.8 222.1 66 150 +1975 9 3 6 13 VALERIE 56.7 249.6 26 134 +2002 10 6 12 18 SANDY 49.5 319.0 93 873 +1983 3 6 0 10 WILLIAM 37.5 241.2 13 409 +1986 4 21 12 16 WILLIAM 11.5 131.0 124 545 +1961 9 7 6 26 BERYL 70.0 348.9 30 317 +1982 6 23 6 18 MICHAEL 16.4 23.6 114 492 +1962 7 3 12 13 OSCAR 10.0 92.8 148 363 +1970 10 23 18 14 HELENE 59.0 40.8 38 807 +1951 7 18 6 22 RAFAEL 56.3 258.4 46 288 +1981 5 22 18 19 WILLIAM 31.2 7.4 41 463 +1987 1 26 18 3 SANDY 68.7 164.7 150 119 +1959 1 27 12 16 VALERIE 24.7 206.9 112 262 +1975 10 4 12 22 ALBERTO 47.1 311.2 78 461 +1991 4 17 6 28 FLORENCE 15.7 280.9 24 507 +1982 3 17 12 8 TONY 56.4 151.3 30 46 +1954 11 10 6 25 ALBERTO 33.0 152.7 103 613 +2001 9 11 12 24 KIRK 67.2 274.4 48 547 +1980 2 11 12 1 TONY 7.7 332.6 39 783 +1987 12 15 12 27 DEBBY 53.0 130.3 141 50 +1965 2 25 18 24 ISAAC 37.1 157.3 149 138 +1962 5 14 18 3 PATTY 69.6 83.7 151 331 +1974 2 13 0 7 FLORENCE 60.2 221.3 51 605 +1968 3 3 0 24 TONY 55.9 132.6 149 88 +1995 9 4 12 13 KIRK 55.4 154.6 94 396 +1979 10 23 18 13 LESLIE 52.4 57.5 163 616 +1983 3 16 12 10 TONY 48.9 50.4 64 747 +1979 11 6 6 1 HELENE 22.5 120.4 22 694 +1980 3 26 18 1 VALERIE 47.1 192.8 100 784 +1978 2 11 18 28 PATTY 40.9 95.8 29 197 +1969 9 20 12 13 VALERIE 59.3 296.4 27 451 +1961 5 24 0 15 DEBBY 64.9 113.8 154 2 +1963 9 9 12 24 LESLIE 40.2 171.5 24 859 +1999 2 22 6 15 DEBBY 15.3 348.2 150 893 +1984 9 13 6 19 SANDY 51.4 268.9 129 365 +1950 7 22 6 25 GORDON 48.5 304.5 39 234 +1987 10 3 18 18 VALERIE 17.9 130.8 16 433 +1981 8 26 0 7 ALBERTO 61.6 235.5 163 870 +2002 12 6 6 18 ALBERTO 53.8 136.1 12 281 +1982 3 6 18 12 ISAAC 66.6 245.1 138 683 +1954 1 1 12 16 CHRIS 27.3 289.6 127 666 +1966 7 10 0 9 ISAAC 18.6 125.8 66 372 +1994 10 11 6 16 BERYL 9.5 54.2 129 291 +1986 8 12 0 6 TONY 19.0 83.4 108 500 +1966 1 6 0 24 LESLIE 7.0 170.1 58 867 +1974 11 12 12 20 TONY 61.0 178.9 66 641 +1999 5 8 12 13 DEBBY 27.5 199.5 40 556 +1972 12 28 12 6 VALERIE 41.4 277.0 132 773 +1968 1 12 12 18 RAFAEL 41.4 258.3 53 602 +1983 12 5 0 28 ISAAC 57.8 78.4 132 259 +1952 5 20 18 21 OSCAR 43.9 128.7 45 379 +1976 8 15 18 6 KIRK 45.6 81.2 36 554 +1998 3 24 18 7 BERYL 35.6 346.2 115 46 +1998 11 9 12 7 JOYCE 66.8 156.2 28 524 +1997 9 2 18 23 BERYL 45.8 310.5 21 726 +1988 2 10 12 16 RAFAEL 38.9 40.5 96 426 +1990 11 11 12 10 JOYCE 36.5 221.0 112 316 +1974 2 16 12 27 ALBERTO 63.9 197.8 80 674 +1991 1 2 6 14 WILLIAM 63.2 140.5 72 685 +1995 7 11 0 6 PATTY 47.9 354.0 38 510 +1968 12 25 0 6 FLORENCE 32.3 165.9 64 474 +1956 3 16 6 4 JOYCE 48.5 151.0 141 442 +1995 11 22 0 2 KIRK 7.4 247.0 36 355 +2002 3 18 0 26 RAFAEL 65.0 269.9 90 309 +1950 4 24 0 18 PATTY 38.9 339.9 37 480 +1976 12 28 12 7 SANDY 63.9 3.0 31 618 +2003 2 26 18 15 PATTY 13.5 147.8 152 74 +1958 10 24 18 18 GORDON 62.7 52.9 94 438 +1986 9 21 18 8 VALERIE 13.9 78.5 70 658 +1996 6 22 18 25 KIRK 50.5 77.6 155 555 +1954 5 9 6 25 WILLIAM 19.5 17.6 13 342 +1965 9 28 18 20 TONY 12.6 349.9 118 9 +1974 6 19 0 7 MICHAEL 14.8 137.3 19 147 +1974 6 3 12 23 RAFAEL 15.8 352.1 30 443 +1972 8 21 6 3 ALBERTO 16.9 212.1 132 344 +1986 6 9 18 1 TONY 40.8 122.0 73 469 +1967 10 28 6 2 ALBERTO 27.1 169.9 111 821 +1952 2 11 18 23 KIRK 10.4 208.5 152 305 +1979 1 1 12 26 ISAAC 69.7 160.1 163 852 +1975 5 6 6 18 ISAAC 14.8 303.7 133 643 +1965 7 6 0 3 NADINE 68.5 321.7 96 288 +1969 3 28 6 14 MICHAEL 56.5 98.3 70 879 +1956 8 19 18 21 DEBBY 49.5 250.3 148 352 +1987 7 18 6 12 ISAAC 38.2 157.2 135 196 +2001 1 16 6 11 SANDY 63.9 308.1 41 748 +1956 8 17 6 27 GORDON 25.3 134.5 115 250 +1960 12 9 12 20 PATTY 24.9 295.6 137 429 +2004 2 19 12 25 BERYL 36.4 202.9 106 700 +1991 2 26 6 9 KIRK 37.4 101.6 118 541 +1972 2 8 6 24 BERYL 42.6 336.3 143 116 +1999 7 8 12 14 FLORENCE 44.1 258.0 35 425 +2000 6 22 0 5 MICHAEL 50.2 357.2 12 572 +1953 4 2 0 10 TONY 50.1 282.6 150 749 +1997 4 26 6 20 PATTY 9.8 51.5 80 540 +1988 11 8 6 8 CHRIS 26.2 107.8 40 32 +1992 1 18 0 14 CHRIS 64.3 146.6 130 183 +1982 1 6 0 5 LESLIE 17.0 155.7 70 748 +1995 7 12 6 6 OSCAR 68.6 309.1 127 88 +1973 7 2 6 21 HELENE 31.2 103.2 23 644 +1988 9 13 6 16 ISAAC 61.6 292.9 116 5 +1961 2 19 6 21 TONY 53.4 227.7 141 601 +1978 7 19 6 12 MICHAEL 44.6 179.4 76 426 +1950 6 9 0 14 HELENE 50.4 113.1 51 601 +1974 8 22 6 14 JOYCE 47.3 237.6 56 480 +1962 6 5 12 19 VALERIE 11.0 64.4 66 295 +1984 4 24 12 12 PATTY 15.0 230.2 22 389 +1989 3 5 0 16 KIRK 41.7 230.0 34 780 +1965 9 3 18 2 ISAAC 40.4 59.4 45 879 +1980 4 11 18 21 KIRK 31.7 348.8 41 751 +2003 6 22 18 27 ERNESTO 7.3 66.4 89 567 +1957 11 11 6 13 KIRK 12.7 0.1 95 46 +1956 5 22 0 19 OSCAR 11.1 86.2 127 40 +1957 8 13 6 9 MICHAEL 29.2 287.9 110 297 +2004 12 10 18 26 ALBERTO 28.6 103.0 70 291 +1975 6 12 12 24 HELENE 30.7 244.1 136 582 +1953 8 9 18 27 DEBBY 57.0 240.1 86 131 +1989 8 17 0 22 KIRK 43.5 21.0 161 722 +1986 4 1 0 3 ISAAC 45.1 15.7 107 517 +2002 4 17 6 2 CHRIS 58.2 259.7 59 770 +1989 6 1 18 5 JOYCE 19.0 205.3 50 185 +1994 11 26 0 15 CHRIS 46.3 57.4 156 309 +1981 12 10 0 22 RAFAEL 32.1 113.2 61 16 +1968 10 8 12 28 NADINE 65.5 9.8 92 779 +1968 11 5 18 21 LESLIE 46.9 306.2 90 63 +1953 8 4 0 19 JOYCE 43.8 200.8 35 703 +1957 7 16 12 23 OSCAR 66.8 41.7 139 707 +2001 7 3 12 21 ALBERTO 22.8 335.9 46 883 +1987 5 25 18 8 VALERIE 30.4 299.2 71 827 +1952 6 14 6 3 SANDY 20.0 71.3 103 889 +1979 6 18 18 27 WILLIAM 28.5 244.6 56 654 +1974 12 20 0 6 FLORENCE 23.8 59.6 132 486 +1986 11 25 6 2 KIRK 27.4 170.6 25 588 +1982 5 7 0 8 HELENE 15.8 292.5 131 164 +1986 6 17 18 19 ISAAC 15.9 287.6 18 644 +1974 6 28 6 1 PATTY 61.4 344.3 161 315 +1967 9 18 6 18 RAFAEL 19.6 25.6 145 185 +1982 9 24 12 11 VALERIE 23.3 190.0 108 572 +1966 4 19 12 3 ALBERTO 36.1 282.5 111 889 +1967 4 2 6 21 SANDY 65.9 285.8 132 359 +1961 4 5 0 25 VALERIE 55.0 262.4 97 711 +1989 4 13 12 3 WILLIAM 55.7 25.5 61 737 +1993 8 8 18 14 OSCAR 37.6 67.8 62 319 +1972 6 7 0 20 OSCAR 36.6 278.5 76 344 +2001 7 12 12 4 FLORENCE 33.6 175.3 26 628 +2000 3 2 12 1 JOYCE 58.5 298.6 41 360 +1960 1 22 0 17 ERNESTO 62.4 343.9 37 554 +1967 4 20 18 15 MICHAEL 54.5 230.3 152 189 +1959 10 18 0 25 LESLIE 44.3 29.4 122 651 +1994 9 25 12 17 SANDY 51.8 254.2 39 522 +1989 3 25 12 23 TONY 50.7 94.8 74 489 +1953 7 21 12 20 BERYL 66.2 193.2 145 263 +1955 1 4 12 5 FLORENCE 14.9 124.0 75 355 +1972 9 14 6 6 LESLIE 66.7 275.4 43 20 +1978 1 7 6 7 RAFAEL 23.3 153.5 95 463 +1969 5 6 18 26 DEBBY 8.6 77.2 82 698 +1950 10 16 18 12 BERYL 56.5 26.3 57 737 +1978 11 19 18 19 RAFAEL 38.8 314.1 163 791 +2000 10 10 12 1 DEBBY 67.3 61.2 120 852 +1973 6 14 0 12 FLORENCE 28.3 96.3 127 814 +2000 2 16 18 2 ERNESTO 24.3 198.1 108 156 +1970 10 28 12 26 NADINE 13.6 307.6 46 340 +1965 6 13 12 6 KIRK 16.3 268.5 131 833 +1978 8 4 12 4 ISAAC 38.0 151.8 42 579 +2000 1 19 0 17 LESLIE 11.9 25.0 61 497 +1981 2 12 0 18 RAFAEL 52.8 305.7 122 707 +1962 10 20 12 28 LESLIE 21.0 113.5 56 537 +1966 11 12 12 20 VALERIE 36.8 139.7 53 59 +1971 1 8 12 18 SANDY 27.1 311.4 141 702 +1995 7 5 12 11 CHRIS 51.2 205.1 124 452 +1984 11 15 6 26 HELENE 60.9 82.0 151 310 +2001 3 9 18 7 ERNESTO 49.8 168.9 161 108 +1987 3 18 12 2 RAFAEL 25.8 316.7 83 395 +1992 3 20 12 22 KIRK 46.6 138.0 91 117 +1962 4 26 18 14 RAFAEL 21.4 55.3 112 398 +1979 7 20 18 4 GORDON 22.3 138.0 139 320 +1974 8 23 6 21 VALERIE 57.8 152.9 71 819 +2002 9 19 0 6 JOYCE 62.0 323.1 53 896 +2003 6 17 18 16 CHRIS 36.7 149.9 38 431 +1994 7 17 12 7 JOYCE 40.6 201.4 117 394 +1965 8 2 18 10 JOYCE 62.5 128.2 142 295 +1959 12 17 12 18 LESLIE 28.1 33.3 25 487 +1957 7 21 18 27 SANDY 47.3 87.5 22 338 +1989 4 16 6 20 ALBERTO 22.7 203.1 50 668 +1963 12 18 12 9 NADINE 12.1 47.9 120 185 +1950 4 7 0 10 MICHAEL 18.2 299.4 72 289 +1974 2 5 6 27 NADINE 56.2 190.3 78 277 +1984 3 24 18 1 RAFAEL 9.1 132.2 33 529 +1997 8 1 12 26 ERNESTO 59.5 50.5 157 148 +1975 2 11 6 17 JOYCE 57.5 191.6 67 629 +1950 1 9 18 4 MICHAEL 25.8 53.9 18 885 +1964 11 21 0 23 JOYCE 11.3 238.2 63 430 +1955 8 15 12 26 DEBBY 31.3 314.9 117 134 +1950 12 3 0 13 WILLIAM 41.8 206.7 14 150 +1994 11 18 6 10 PATTY 11.0 46.9 144 169 +1952 5 26 12 9 RAFAEL 9.3 204.8 132 288 +1976 11 16 0 24 FLORENCE 62.9 356.6 81 245 +1964 7 24 6 13 LESLIE 17.4 329.4 20 205 +1954 8 23 6 15 WILLIAM 41.3 28.0 56 673 +1957 3 20 12 14 KIRK 49.1 158.5 57 549 +2001 4 14 0 8 WILLIAM 46.0 120.2 104 734 +2004 12 2 6 28 DEBBY 46.3 261.5 136 44 +1982 7 12 18 26 BERYL 59.8 2.3 48 357 +1951 2 7 12 6 HELENE 10.8 50.4 142 758 +1970 5 20 12 22 ALBERTO 66.8 213.9 105 402 +1981 5 11 18 19 CHRIS 18.9 146.3 28 389 +1977 1 3 0 23 OSCAR 24.1 302.7 147 373 +1991 4 18 12 22 DEBBY 26.9 104.0 83 287 +1991 7 20 12 21 PATTY 67.6 10.2 12 753 +1960 6 4 18 8 JOYCE 69.5 131.4 67 4 +1985 1 16 0 12 KIRK 18.7 344.1 155 139 +1955 8 18 18 10 HELENE 42.5 344.3 114 385 +1998 4 15 12 2 OSCAR 29.8 177.0 60 792 +1982 4 23 0 2 HELENE 14.7 176.1 12 377 +1952 11 2 18 19 KIRK 24.6 352.8 159 631 +1994 2 8 6 12 TONY 7.1 216.3 98 392 +1998 6 23 6 27 SANDY 66.3 107.3 112 669 +1979 5 27 12 4 CHRIS 9.7 294.3 38 217 +2002 10 7 18 10 HELENE 14.1 295.1 125 223 +1972 11 23 6 11 HELENE 27.4 199.4 108 860 +1992 2 20 18 7 CHRIS 13.8 127.6 26 518 +1975 2 1 0 19 HELENE 10.2 234.4 140 316 +1993 4 11 6 28 ISAAC 38.6 332.9 43 898 +1970 2 10 6 21 OSCAR 56.8 140.7 102 743 +1993 1 28 6 11 SANDY 23.8 156.3 85 640 +1996 5 21 12 14 ISAAC 19.4 283.7 31 662 +1980 7 11 12 23 NADINE 52.1 232.7 135 124 +1969 12 27 12 20 HELENE 12.3 112.3 58 737 +1972 6 8 6 21 ALBERTO 56.6 202.2 71 650 +1989 3 12 12 20 ISAAC 51.2 225.2 36 24 +1998 7 23 6 14 LESLIE 67.7 158.6 164 276 +2004 1 19 0 26 FLORENCE 7.5 353.6 116 740 +1977 10 22 6 19 JOYCE 51.0 130.2 32 167 +1964 4 9 18 18 LESLIE 36.8 346.1 72 711 +2001 2 9 12 12 ERNESTO 11.2 263.6 35 399 +1974 7 7 12 7 SANDY 11.6 34.2 119 195 +1989 9 18 6 24 SANDY 19.5 30.9 103 487 +2001 6 24 12 26 BERYL 22.3 323.7 109 119 +1990 2 25 18 28 BERYL 13.5 269.0 107 424 +1976 10 2 18 20 ALBERTO 27.2 1.3 27 438 +1995 12 4 12 19 DEBBY 57.5 118.2 11 672 +1971 7 8 6 19 RAFAEL 14.7 305.6 33 568 +1980 11 9 0 13 LESLIE 37.1 267.1 57 459 +1988 2 7 6 25 ERNESTO 41.8 291.8 21 693 +1975 3 23 6 25 FLORENCE 39.2 99.7 161 529 +1954 6 23 0 24 HELENE 63.2 171.6 138 271 +1955 12 23 12 17 ALBERTO 61.8 295.3 76 57 +1954 3 5 12 16 ALBERTO 47.9 103.0 92 260 +1960 6 6 6 27 PATTY 37.4 80.1 55 62 +1986 5 11 18 3 NADINE 49.3 213.3 123 496 +1953 9 3 6 18 SANDY 64.0 27.8 49 792 +1991 7 14 0 22 BERYL 31.3 171.5 120 344 +1978 3 16 12 20 KIRK 56.6 309.6 50 31 +1995 8 16 18 23 FLORENCE 66.6 220.2 30 855 +1962 9 7 0 2 BERYL 49.9 341.1 163 450 +1989 1 15 12 18 ERNESTO 52.8 61.2 105 530 +1987 7 27 18 8 TONY 57.6 1.7 63 389 +1994 11 8 0 22 MICHAEL 47.3 106.5 159 286 +1965 6 2 6 10 RAFAEL 55.7 175.5 94 806 +1966 8 21 0 13 OSCAR 11.9 186.6 24 162 +1954 10 9 12 19 BERYL 27.1 253.6 54 850 +1958 9 28 6 22 CHRIS 63.9 257.0 153 847 +1992 9 13 18 14 WILLIAM 19.7 169.4 33 226 +1953 10 19 12 23 VALERIE 13.9 35.6 64 184 +2000 10 8 12 18 TONY 39.5 160.9 39 312 +1991 8 24 0 21 ERNESTO 10.5 245.9 19 419 +1986 4 1 12 8 TONY 68.9 190.4 45 179 +1962 7 8 12 21 ERNESTO 19.6 239.9 82 281 +1973 8 20 12 16 HELENE 27.9 138.3 102 409 +1954 11 4 6 21 RAFAEL 36.2 199.6 102 255 +1968 4 9 12 17 PATTY 58.9 304.3 132 315 +1997 6 6 18 19 TONY 67.0 123.0 143 832 +1996 5 4 18 13 SANDY 24.5 344.7 30 5 +1991 1 23 6 24 ERNESTO 48.9 2.0 90 469 +1971 5 28 0 13 GORDON 46.1 137.0 53 70 +1959 8 8 6 20 TONY 18.7 73.1 66 102 +1973 11 12 6 10 WILLIAM 46.9 271.4 133 176 +1983 10 6 12 1 PATTY 11.2 97.2 93 224 +1976 9 1 12 25 RAFAEL 63.1 250.9 131 21 +1999 12 3 12 22 HELENE 41.6 212.9 67 444 +2000 4 22 12 16 FLORENCE 15.7 99.6 48 276 +1980 2 24 18 2 GORDON 66.2 29.9 69 28 +1973 10 11 6 14 JOYCE 27.1 331.8 144 316 +1982 11 7 12 1 SANDY 25.6 136.8 153 505 +1969 12 23 0 23 FLORENCE 61.8 72.7 10 443 +1950 12 14 6 3 GORDON 42.6 289.8 85 231 +1952 7 8 6 13 PATTY 51.8 265.2 153 251 +2004 2 20 0 5 GORDON 18.6 207.3 113 341 +1950 11 4 12 2 WILLIAM 12.0 125.9 68 701 +1969 8 19 0 17 KIRK 29.8 321.0 134 821 +1961 3 6 12 13 HELENE 51.2 88.5 23 81 +1954 12 8 18 9 BERYL 49.7 308.8 141 874 +1980 1 9 18 20 GORDON 45.8 223.2 84 509 +1981 12 17 18 7 PATTY 7.1 229.8 80 806 +1993 4 22 12 7 ALBERTO 22.1 295.3 67 548 +1995 9 7 6 3 NADINE 55.3 122.1 153 808 +1981 2 4 18 6 GORDON 9.1 249.3 52 39 +1986 4 12 6 1 SANDY 69.7 124.1 117 786 +1964 10 4 6 21 RAFAEL 60.0 26.6 132 691 +1991 3 17 18 25 VALERIE 34.7 41.6 135 871 +1967 1 5 6 21 VALERIE 34.4 67.1 151 743 +1992 6 22 6 7 BERYL 14.9 128.2 138 145 +1951 7 2 0 25 OSCAR 10.7 193.9 10 212 +1990 12 4 0 23 RAFAEL 9.1 113.5 163 375 +1951 1 9 0 26 BERYL 14.5 262.5 44 463 +1976 3 26 12 2 NADINE 38.2 39.4 98 677 +1990 12 16 18 10 VALERIE 13.7 72.5 121 871 +1997 12 19 6 7 VALERIE 44.4 352.9 89 648 +1991 1 28 6 15 FLORENCE 27.9 188.8 145 799 +2000 10 5 6 20 CHRIS 50.4 22.4 84 534 +1981 12 20 12 13 LESLIE 18.6 40.1 69 296 +1971 2 8 6 27 BERYL 35.4 305.4 57 106 +1989 5 1 12 12 ISAAC 56.0 70.1 65 514 +1972 12 1 18 25 ALBERTO 68.9 147.9 50 582 +1959 10 5 0 3 CHRIS 45.2 110.2 65 395 +1986 8 23 6 12 WILLIAM 60.2 250.6 161 850 +2000 9 23 6 8 HELENE 8.4 0.2 51 286 +1963 7 15 18 10 TONY 45.0 126.1 33 376 +1957 1 26 18 9 PATTY 35.6 269.2 72 316 +1970 12 17 18 7 LESLIE 50.9 57.8 161 752 +1996 12 5 6 21 OSCAR 47.3 112.1 114 86 +1980 2 1 6 21 WILLIAM 13.5 300.8 57 473 +1979 12 27 12 8 SANDY 22.9 4.9 131 718 +1952 12 3 12 15 JOYCE 62.6 276.0 146 475 +1956 10 23 12 1 OSCAR 65.3 154.9 148 279 +1981 4 1 18 19 TONY 16.0 225.8 52 471 +1969 11 18 0 23 HELENE 37.2 250.0 55 230 +1958 5 6 18 11 GORDON 65.0 350.8 159 84 +1968 4 24 12 8 ALBERTO 23.1 319.4 127 301 +1960 10 13 12 16 TONY 50.2 79.2 83 320 +1982 5 4 18 19 NADINE 57.9 1.8 85 752 +1950 7 10 18 2 HELENE 12.6 259.4 19 334 +1964 6 18 18 28 GORDON 9.3 334.9 78 465 +1972 12 5 12 15 ERNESTO 29.2 51.3 92 249 +1993 10 3 0 7 KIRK 15.9 289.6 21 795 +1955 6 12 6 13 ISAAC 67.2 142.6 25 556 +1964 2 7 12 9 VALERIE 34.2 28.1 142 718 +1950 10 19 0 2 SANDY 47.2 268.3 77 774 +1965 4 7 18 2 FLORENCE 23.3 132.6 164 710 +2003 3 13 6 21 WILLIAM 51.7 248.7 54 342 +1992 12 7 0 11 TONY 12.4 304.1 48 511 +2004 11 24 18 9 GORDON 36.4 133.2 159 303 +1995 6 25 12 23 RAFAEL 26.1 4.3 27 334 +1961 11 14 18 8 MICHAEL 67.9 237.0 108 223 +1991 3 12 12 1 WILLIAM 24.8 82.7 55 752 +2000 5 6 12 27 TONY 26.7 198.8 136 883 +2002 9 20 6 10 HELENE 47.2 321.8 74 718 +1978 12 17 12 1 RAFAEL 52.4 114.2 33 154 +1970 9 2 6 15 JOYCE 12.8 313.8 22 356 +1995 2 4 6 25 SANDY 13.5 262.3 79 348 +1969 3 16 18 27 VALERIE 66.5 326.3 159 106 +1972 3 15 0 11 VALERIE 35.8 24.4 39 880 +1994 6 6 0 17 CHRIS 25.0 5.1 128 418 +1956 8 15 18 2 JOYCE 17.5 231.7 75 99 +1994 11 14 12 27 BERYL 10.0 271.4 55 181 +1963 1 18 6 17 PATTY 32.3 107.3 61 476 +1986 5 12 12 5 FLORENCE 67.7 286.0 61 350 +1999 9 1 18 21 LESLIE 10.2 353.9 59 571 +2002 11 24 0 24 WILLIAM 19.6 322.5 74 262 +1953 4 6 6 18 FLORENCE 23.1 148.4 91 570 +1957 4 21 12 1 ERNESTO 47.4 121.2 36 800 +2004 3 1 6 26 GORDON 54.1 318.8 32 254 +1996 3 22 6 11 OSCAR 28.7 165.3 103 499 +1982 2 26 6 11 LESLIE 49.2 180.7 138 26 +1964 4 1 18 5 GORDON 35.7 244.6 43 252 +1960 12 14 12 24 ALBERTO 27.2 78.4 138 617 +1955 10 11 6 20 DEBBY 67.0 222.4 159 744 +1957 8 8 12 27 NADINE 33.3 135.1 148 638 +1982 9 26 0 16 ISAAC 10.0 179.3 81 182 +1952 2 13 6 10 ISAAC 15.5 336.6 54 822 +1974 7 8 0 20 CHRIS 18.1 233.0 94 178 +1982 6 11 0 18 LESLIE 30.2 118.3 85 397 +1963 10 15 0 4 FLORENCE 30.2 344.4 117 651 +1992 3 17 0 19 ERNESTO 52.9 258.8 95 883 +1971 4 14 0 18 ISAAC 38.6 244.2 29 473 +1991 6 14 12 12 ERNESTO 16.8 127.8 163 810 +1999 11 23 0 3 VALERIE 39.8 53.4 31 147 +1981 8 9 18 20 BERYL 35.0 1.1 25 363 +1951 7 16 6 21 CHRIS 10.1 122.4 112 677 +1956 11 16 6 8 DEBBY 42.6 172.3 103 488 +1968 12 2 18 25 BERYL 62.6 13.1 25 759 +1962 8 19 0 5 OSCAR 66.4 289.3 98 422 +1951 7 19 6 24 FLORENCE 22.0 44.8 107 400 +1978 9 3 0 10 VALERIE 50.0 218.0 99 829 +1994 9 7 12 13 DEBBY 19.3 342.3 140 210 +1967 1 2 6 12 GORDON 20.1 142.0 104 208 +1988 8 12 18 1 LESLIE 54.9 164.7 96 698 +1967 2 12 6 21 KIRK 15.5 182.6 130 829 +1993 12 25 12 16 WILLIAM 31.9 269.3 82 835 +1980 6 11 18 28 FLORENCE 43.2 237.8 36 861 +1974 3 3 6 3 ERNESTO 56.8 256.2 120 411 +2001 2 14 6 4 TONY 10.7 112.9 116 842 +1997 5 13 0 6 SANDY 59.3 43.8 134 535 +1992 8 21 0 23 VALERIE 43.0 218.2 130 676 +1991 8 17 6 7 OSCAR 41.4 337.2 53 713 +1998 12 14 18 4 BERYL 17.9 52.9 53 444 +1981 9 14 6 2 OSCAR 16.2 338.2 21 784 +1963 8 15 0 15 CHRIS 68.7 154.9 133 37 +1974 6 6 0 24 TONY 36.4 219.6 79 854 +1996 12 10 12 10 OSCAR 66.9 321.1 147 464 +1973 11 13 18 6 VALERIE 35.5 209.2 133 69 +1994 8 14 18 21 MICHAEL 36.3 189.9 102 288 +1988 7 22 12 24 FLORENCE 57.4 63.3 150 478 +1956 12 14 0 14 FLORENCE 68.6 338.2 164 319 +1996 9 17 6 8 FLORENCE 37.6 56.1 161 609 +1991 2 10 18 21 ERNESTO 44.8 154.4 163 881 +1988 10 5 6 9 ISAAC 38.5 334.0 35 479 +1988 3 17 6 10 JOYCE 68.0 4.1 73 793 +1959 9 9 6 24 ERNESTO 21.9 174.1 31 370 +1987 4 18 12 4 CHRIS 43.9 316.4 107 881 +1995 4 5 6 12 MICHAEL 57.5 99.1 12 502 +1965 12 1 6 23 LESLIE 32.0 15.0 48 85 +1954 4 21 18 14 ALBERTO 30.8 277.6 156 422 +1971 5 20 6 28 MICHAEL 43.3 90.7 99 358 +1960 3 23 12 24 CHRIS 10.6 344.0 113 108 +1996 6 7 18 14 SANDY 47.4 183.6 145 624 +1951 10 7 6 7 DEBBY 31.0 73.9 22 587 +1957 1 18 0 1 CHRIS 53.3 90.2 69 654 +1962 6 27 0 18 VALERIE 62.6 31.2 125 383 +1997 11 6 18 16 ALBERTO 25.2 28.1 131 594 +1972 11 4 18 6 LESLIE 27.6 13.4 160 309 +1958 10 24 18 9 PATTY 10.1 155.4 24 193 +2000 1 22 18 13 KIRK 33.5 318.2 152 161 +1966 7 19 12 6 CHRIS 28.0 272.5 90 356 +1971 11 17 18 18 LESLIE 58.7 261.3 120 163 +1990 12 2 6 8 TONY 18.9 159.5 136 651 +1976 1 28 0 16 ERNESTO 7.9 183.0 21 346 +1963 6 9 12 12 TONY 19.6 107.2 163 696 +1993 8 16 18 13 SANDY 54.2 238.7 143 660 +1970 1 2 0 13 JOYCE 46.2 298.2 48 255 +1953 7 4 6 10 WILLIAM 9.5 140.2 64 616 +1978 8 16 6 21 WILLIAM 33.8 47.4 105 147 +1965 3 24 6 25 ISAAC 50.7 321.4 93 844 +1953 9 27 6 18 SANDY 13.5 154.0 66 596 +1994 6 1 12 1 MICHAEL 28.6 104.7 19 486 +1995 5 16 0 22 RAFAEL 30.4 130.6 19 316 +1978 9 3 12 17 NADINE 38.2 135.0 125 300 +1961 5 19 0 2 WILLIAM 7.0 226.2 98 711 +1967 5 18 18 16 BERYL 38.0 8.6 93 117 +1976 12 14 0 14 VALERIE 48.9 154.3 22 465 +1992 8 1 18 23 VALERIE 58.5 310.4 140 567 +1987 5 10 6 19 MICHAEL 35.3 14.6 19 222 +1987 3 15 18 18 LESLIE 56.4 200.7 145 256 +1997 2 11 6 14 DEBBY 43.9 308.8 41 886 +1984 11 21 18 3 ISAAC 67.1 257.6 75 30 +1952 5 22 18 18 DEBBY 65.4 260.6 27 553 +1988 8 9 12 1 VALERIE 14.2 152.0 47 224 +1961 8 6 6 11 ERNESTO 55.6 156.4 69 775 +1956 3 19 18 21 CHRIS 22.6 143.1 81 25 +1960 11 25 18 4 OSCAR 11.5 155.1 18 455 +1988 9 4 6 5 SANDY 26.6 28.6 42 717 +1966 1 8 6 26 WILLIAM 62.1 174.9 153 202 +1950 3 10 18 28 MICHAEL 67.0 46.6 153 666 +1951 1 11 0 11 RAFAEL 59.9 64.6 126 372 +1951 3 3 18 26 WILLIAM 49.0 240.3 85 558 +1978 9 25 18 18 WILLIAM 8.4 198.9 91 538 +1961 7 2 0 11 WILLIAM 39.9 348.6 123 547 +1967 1 7 12 16 BERYL 7.3 217.0 104 557 +1981 10 7 0 2 DEBBY 9.0 45.1 138 295 +1995 5 28 18 24 SANDY 17.4 256.7 157 266 +1955 5 23 18 18 VALERIE 58.5 105.6 137 568 +1999 2 16 12 6 VALERIE 35.4 232.5 128 585 +1998 8 25 6 16 WILLIAM 25.2 287.5 131 754 +1990 12 20 18 15 HELENE 63.3 334.1 52 363 +1950 1 10 18 14 WILLIAM 22.4 38.3 156 180 +1969 10 28 12 28 NADINE 33.1 108.4 33 668 +1989 6 20 18 20 ERNESTO 10.5 301.9 21 318 +1985 12 3 12 8 FLORENCE 65.5 319.3 70 40 +1984 7 20 12 23 ERNESTO 9.7 36.1 101 433 +2001 6 5 0 22 NADINE 55.4 100.7 112 281 +1980 4 11 12 21 LESLIE 25.0 33.9 21 529 +1951 1 5 0 19 FLORENCE 7.4 38.8 110 317 +1961 5 1 18 15 FLORENCE 47.3 256.4 162 213 +2002 5 10 12 23 BERYL 30.7 188.6 130 750 +1961 7 12 6 21 DEBBY 64.5 253.3 126 559 +2001 2 12 6 20 OSCAR 21.7 280.0 119 771 +1984 4 21 0 11 ERNESTO 11.5 287.1 81 356 +1976 5 10 6 17 MICHAEL 7.5 55.3 163 478 +1963 6 6 12 26 JOYCE 61.4 151.9 41 299 +1967 1 24 12 8 GORDON 19.7 161.4 99 797 +1999 9 19 0 12 RAFAEL 66.5 226.5 123 247 +1975 4 17 12 22 KIRK 46.8 158.3 100 89 +1984 8 8 0 4 VALERIE 37.5 201.6 129 118 +1989 5 15 18 1 GORDON 15.2 282.5 164 617 +1953 7 21 6 24 LESLIE 9.6 101.7 164 528 +1997 8 22 0 20 MICHAEL 30.0 202.5 66 238 +1989 2 4 6 16 LESLIE 60.1 319.6 140 301 +1960 12 8 12 2 KIRK 16.9 112.6 139 476 +1972 9 9 0 6 ISAAC 46.4 45.9 53 157 +1962 4 25 12 19 RAFAEL 18.4 144.0 98 132 +1952 1 23 0 17 BERYL 40.0 159.0 77 374 +1999 1 14 12 3 ISAAC 14.4 251.9 91 83 +1995 2 23 18 12 ISAAC 19.7 144.7 100 804 +1955 4 16 18 16 TONY 69.4 30.8 53 204 +1988 6 28 12 25 SANDY 7.0 63.3 155 237 +1978 7 17 18 9 DEBBY 16.0 84.8 66 593 +1988 5 10 12 28 PATTY 12.1 178.9 65 4 +1959 10 17 18 1 GORDON 66.1 206.8 80 836 +1987 7 12 6 21 BERYL 36.5 123.2 121 556 +1989 1 2 0 6 RAFAEL 34.1 236.5 25 458 +1996 3 23 18 23 DEBBY 17.6 110.1 142 247 +2003 1 12 6 1 SANDY 45.2 319.0 156 780 +1998 5 4 12 6 MICHAEL 37.3 93.9 62 665 +1984 12 3 6 19 LESLIE 68.3 282.3 158 853 +1975 2 18 0 13 HELENE 68.7 245.9 94 638 +1987 7 11 18 14 RAFAEL 25.9 55.0 21 80 +1983 7 27 18 7 ERNESTO 57.6 5.1 44 435 +1961 10 4 18 25 MICHAEL 47.8 281.2 155 108 +1988 10 21 0 28 WILLIAM 26.3 238.1 50 374 +1969 6 3 18 19 HELENE 35.2 153.7 12 216 +1970 6 18 12 15 RAFAEL 49.2 166.8 148 154 +1995 9 25 6 24 TONY 39.9 314.1 40 356 +1998 2 25 18 16 FLORENCE 7.4 75.4 148 899 +1951 3 20 0 10 NADINE 52.6 320.4 110 771 +1952 3 4 6 28 OSCAR 13.4 167.8 162 366 +1999 5 1 6 1 ISAAC 51.4 182.0 106 190 +2000 1 17 0 27 ALBERTO 42.3 135.1 95 320 +1952 12 16 0 25 FLORENCE 59.1 211.0 49 797 +1994 3 20 0 23 BERYL 9.6 59.3 144 191 +1959 4 17 0 23 WILLIAM 17.4 269.5 164 117 +1992 7 23 6 18 ISAAC 26.6 212.6 70 265 +1997 7 24 6 14 JOYCE 47.8 72.0 141 291 +1981 1 23 6 21 BERYL 26.3 82.1 78 778 +1974 4 19 18 26 ALBERTO 61.6 268.4 61 62 +1985 11 19 18 8 JOYCE 50.2 250.6 118 746 +1963 7 15 0 28 TONY 26.3 15.1 17 28 +1970 11 2 12 23 JOYCE 37.8 340.6 54 861 +1976 3 21 18 9 OSCAR 52.2 297.3 95 678 +1986 10 14 12 18 WILLIAM 27.0 30.5 89 84 +1966 7 13 12 6 SANDY 27.9 286.1 118 194 +1951 11 27 18 7 DEBBY 51.9 3.3 58 252 +1988 4 13 6 16 PATTY 53.2 132.1 54 369 +1955 2 20 6 18 BERYL 40.0 339.3 147 399 +1975 3 26 12 18 KIRK 48.8 188.7 117 231 +1978 1 28 6 11 OSCAR 55.3 237.7 149 494 +1992 2 9 12 16 VALERIE 60.4 289.8 157 685 +1958 11 18 0 22 CHRIS 50.6 3.4 86 870 +1993 2 4 0 11 ERNESTO 27.8 52.4 144 13 +1999 5 12 18 20 LESLIE 10.4 324.6 77 463 +1994 3 5 6 10 PATTY 30.9 32.1 150 286 +1987 12 15 6 23 ALBERTO 65.5 310.6 129 335 +1985 11 3 0 9 RAFAEL 58.1 17.3 42 428 +1967 11 9 12 1 WILLIAM 7.2 146.4 129 387 +1979 4 2 18 7 WILLIAM 60.1 8.7 76 14 +1958 8 13 0 27 CHRIS 27.7 252.0 123 689 +1969 5 17 18 16 OSCAR 60.4 194.5 54 390 +1952 8 15 6 4 ISAAC 61.4 165.7 130 160 +1976 11 2 6 20 ERNESTO 53.8 253.5 76 828 +1950 4 4 0 7 OSCAR 23.8 134.2 16 755 +1954 3 5 6 7 FLORENCE 66.3 139.9 147 674 +1984 6 17 0 17 SANDY 11.5 92.3 164 171 +1978 12 5 0 2 BERYL 69.8 94.0 36 707 +1971 5 9 18 23 KIRK 44.1 100.8 144 216 +1999 7 1 0 18 SANDY 44.1 204.6 139 317 +1993 10 7 0 5 WILLIAM 49.4 88.4 106 811 +1981 7 17 12 22 BERYL 69.6 222.5 19 33 +1954 6 16 18 2 ERNESTO 44.6 351.6 64 898 +1992 4 4 18 19 VALERIE 47.8 172.4 80 727 +1954 11 13 0 21 OSCAR 21.9 2.5 72 267 +1965 11 20 18 1 BERYL 69.8 58.2 10 225 +1951 1 19 6 19 WILLIAM 10.6 181.4 56 256 +1998 2 24 0 3 HELENE 11.2 234.1 99 33 +1955 5 17 6 21 BERYL 11.0 92.3 13 368 +1963 2 12 6 23 ISAAC 17.0 142.5 108 247 +1990 9 8 18 1 HELENE 41.1 60.5 50 370 +1984 12 2 0 28 NADINE 51.4 118.1 92 490 +1988 1 23 0 26 DEBBY 62.0 49.4 138 343 +2004 5 7 12 6 MICHAEL 12.5 183.5 48 129 +1975 10 11 0 26 MICHAEL 36.2 20.8 98 563 +1963 5 5 6 11 VALERIE 38.7 114.2 121 25 +1996 9 6 12 26 ISAAC 60.3 348.2 72 143 +1964 8 5 6 4 ERNESTO 9.4 33.6 88 775 +1981 1 10 6 7 ERNESTO 14.5 119.3 124 403 +1953 2 9 18 4 LESLIE 32.9 53.3 41 89 +1988 10 24 12 3 TONY 26.7 250.1 106 457 +1959 1 17 12 5 RAFAEL 46.8 314.5 86 743 +2000 11 11 6 26 MICHAEL 20.7 208.9 74 455 +2002 6 19 12 25 FLORENCE 11.3 341.4 11 323 +1954 5 5 12 22 LESLIE 23.2 325.1 73 272 +1975 5 23 18 14 ALBERTO 17.3 16.4 163 556 +2001 6 26 0 18 TONY 63.1 102.9 28 886 +1960 11 12 18 23 KIRK 16.0 3.2 109 58 +1992 4 27 6 25 JOYCE 67.8 204.0 86 631 +1956 1 19 0 21 BERYL 18.3 68.8 37 708 +1975 5 15 18 12 DEBBY 36.8 72.9 104 871 +1954 11 9 18 14 ERNESTO 18.0 223.2 90 250 +1951 8 8 12 5 HELENE 66.5 36.5 88 691 +1993 3 12 12 6 NADINE 30.3 268.0 95 772 +1958 12 18 0 17 LESLIE 39.6 295.3 160 709 +1998 3 16 0 24 ISAAC 10.3 190.9 65 679 +1980 8 6 6 6 ISAAC 21.7 132.8 110 450 +1971 10 12 6 19 FLORENCE 13.0 53.2 65 169 +1954 12 1 18 18 SANDY 47.3 124.3 112 823 +1951 11 19 0 21 VALERIE 62.5 129.2 103 714 +1950 12 18 18 13 RAFAEL 11.4 222.0 96 641 +1972 11 2 6 19 TONY 47.8 254.4 111 708 +1963 1 21 0 28 CHRIS 12.5 143.0 129 828 +1994 4 6 18 1 ERNESTO 65.1 157.5 17 774 +1955 1 4 18 3 WILLIAM 9.7 189.8 55 776 +1986 10 5 0 13 MICHAEL 43.9 43.5 56 227 +1994 7 19 6 20 DEBBY 46.8 82.5 143 481 +1950 5 13 0 20 ERNESTO 53.3 188.1 67 280 +1962 8 4 0 21 BERYL 19.9 86.7 70 312 +1997 8 27 18 7 FLORENCE 25.6 346.3 135 128 +1964 10 8 18 6 CHRIS 30.1 256.3 112 551 +1986 6 10 6 20 DEBBY 19.8 33.3 118 551 +2004 4 25 0 28 SANDY 59.9 24.3 23 311 +2001 5 14 6 3 MICHAEL 34.0 33.4 124 836 +1982 2 13 0 1 RAFAEL 37.8 28.4 102 305 +1962 1 16 12 24 MICHAEL 11.2 308.4 113 207 +1986 12 27 18 17 LESLIE 46.8 121.6 61 47 +1979 7 12 12 10 ERNESTO 10.6 131.7 103 543 +1999 2 6 0 1 LESLIE 66.4 141.3 128 319 +1973 7 16 12 19 HELENE 65.3 253.6 41 550 +1962 2 17 0 21 ALBERTO 57.4 144.1 16 764 +1953 9 12 18 15 LESLIE 53.6 109.7 52 309 +1994 7 5 6 8 HELENE 11.9 60.2 17 198 +1992 1 8 0 22 CHRIS 32.2 4.9 113 282 +2004 5 1 18 23 GORDON 39.7 86.9 142 625 +1973 5 7 0 25 HELENE 39.3 219.3 62 328 +1988 5 27 12 20 ERNESTO 39.2 279.0 127 645 +1971 5 20 12 18 JOYCE 24.7 213.2 42 663 +1967 3 20 0 16 GORDON 65.8 90.3 97 522 +1979 4 15 6 25 ALBERTO 19.1 148.0 39 795 +1999 8 24 0 18 DEBBY 45.7 128.3 81 596 +1968 4 26 0 3 OSCAR 19.5 87.7 128 407 +1956 8 5 18 26 TONY 41.5 208.8 101 567 +1990 7 22 6 26 TONY 19.2 261.2 106 341 +1995 6 3 6 22 NADINE 54.3 333.5 93 828 +1951 2 27 12 16 RAFAEL 31.4 255.2 17 392 +1954 6 28 0 24 MICHAEL 68.0 27.8 162 696 +1990 9 12 12 26 OSCAR 17.0 338.5 110 569 +1995 1 5 0 19 RAFAEL 45.5 260.1 113 550 +1994 7 8 12 7 TONY 58.4 262.0 134 267 +2003 3 5 0 28 RAFAEL 33.4 225.8 72 121 +2004 9 14 6 21 OSCAR 54.5 353.8 91 653 +1997 4 23 0 26 CHRIS 55.2 49.9 91 76 +1973 6 13 18 28 JOYCE 28.5 232.4 136 57 +2000 12 5 6 23 SANDY 8.7 30.1 62 389 +1983 12 10 0 4 ERNESTO 26.7 208.7 151 90 +1965 11 17 6 9 WILLIAM 44.2 180.5 144 282 +1999 11 19 18 8 WILLIAM 18.0 336.0 140 61 +1981 1 25 6 13 PATTY 60.2 219.8 146 857 +1990 5 8 0 11 VALERIE 36.2 232.3 157 585 +1987 2 13 12 20 JOYCE 41.7 284.5 113 212 +1952 8 22 18 4 RAFAEL 51.4 123.6 53 629 +1985 4 7 6 18 BERYL 25.1 300.7 119 228 +1963 7 11 18 23 CHRIS 21.3 206.1 150 709 +1978 6 18 0 22 JOYCE 11.3 277.5 163 698 +1988 10 28 0 17 MICHAEL 30.3 143.5 61 355 +1981 8 25 18 2 LESLIE 50.0 286.8 63 499 +1996 9 8 6 26 VALERIE 64.8 186.2 157 47 +1990 5 12 18 20 PATTY 35.7 260.2 124 291 +1994 4 18 12 22 GORDON 12.2 168.8 101 133 +1957 12 2 0 15 SANDY 46.5 292.2 117 261 +1979 11 22 18 26 VALERIE 41.3 146.1 43 585 +2001 9 8 12 21 PATTY 24.1 259.7 142 379 +1975 3 17 6 26 BERYL 21.7 163.8 83 138 +1975 4 28 6 27 LESLIE 60.6 70.8 84 747 +1956 3 26 0 4 HELENE 32.5 233.7 95 556 +1952 4 11 6 16 JOYCE 66.7 192.3 67 76 +1952 9 13 0 6 RAFAEL 28.9 88.5 159 745 +1965 6 9 0 22 PATTY 23.1 150.0 109 374 +1979 6 24 18 5 VALERIE 46.2 300.3 161 290 +2002 6 20 6 18 JOYCE 60.3 120.3 77 603 +1987 11 21 6 21 PATTY 63.1 62.9 65 140 +1980 8 23 0 4 ERNESTO 31.5 137.4 20 699 +1977 2 10 18 1 LESLIE 25.7 204.7 16 435 +1982 9 1 12 24 ERNESTO 11.7 28.1 94 207 +2004 5 26 18 18 FLORENCE 17.1 139.0 143 10 +1954 10 1 12 2 CHRIS 11.1 50.4 33 183 +1964 12 23 18 25 NADINE 58.3 291.9 102 126 +1950 12 18 12 11 ISAAC 22.5 239.3 99 678 +1971 6 2 12 27 SANDY 45.9 268.4 81 758 +1952 3 1 6 27 NADINE 39.0 78.9 127 819 +1996 7 6 12 4 NADINE 7.9 184.4 93 500 +1972 9 18 18 4 PATTY 8.7 48.3 87 54 +1994 5 6 0 14 CHRIS 33.1 133.2 121 400 +1997 2 1 18 17 KIRK 23.6 206.0 65 270 +1953 10 3 12 12 CHRIS 48.6 270.2 34 787 +1996 11 18 12 23 WILLIAM 9.2 36.0 154 851 +1955 2 17 6 27 OSCAR 56.8 111.0 150 281 +1976 1 1 12 24 TONY 43.7 337.9 60 387 +1983 6 3 6 5 PATTY 21.8 8.1 87 312 +1968 12 14 18 5 JOYCE 52.3 319.6 148 584 +1983 2 26 12 1 FLORENCE 45.2 315.1 120 514 +1980 4 13 18 1 JOYCE 36.4 349.9 120 783 +1978 3 17 18 1 GORDON 42.5 84.6 14 440 +1954 10 15 12 27 NADINE 40.1 111.7 101 545 +1967 10 12 0 11 HELENE 28.8 323.2 119 475 +1951 9 17 12 6 ISAAC 51.2 150.0 24 563 +2001 10 7 0 11 ERNESTO 11.0 44.1 98 288 +1980 11 14 6 27 CHRIS 60.3 283.5 126 354 +1980 11 21 18 28 KIRK 65.6 153.1 10 451 +1998 1 11 18 26 VALERIE 22.8 270.3 102 146 +1977 6 23 18 4 FLORENCE 53.2 279.5 48 339 +2004 3 14 18 28 KIRK 16.4 50.7 99 873 +1951 5 21 12 10 ALBERTO 36.5 86.1 41 645 +1987 8 26 0 25 ERNESTO 16.1 167.9 90 138 +1957 12 23 0 1 CHRIS 34.7 178.1 60 619 +2002 10 19 0 13 RAFAEL 64.6 327.8 14 275 +1963 5 14 12 17 WILLIAM 20.6 224.5 161 444 +1987 4 12 0 1 ALBERTO 60.6 215.9 139 646 +1961 4 24 12 11 SANDY 27.4 350.2 156 252 +1965 1 26 0 28 ERNESTO 53.4 284.3 72 582 +1999 5 10 6 11 OSCAR 49.1 11.2 42 737 +1954 1 3 12 4 ALBERTO 16.3 275.3 90 730 +1987 9 12 6 13 SANDY 52.6 239.4 110 823 +1995 2 1 18 13 FLORENCE 28.1 108.3 31 615 +1980 5 23 0 5 PATTY 65.0 44.7 36 798 +1959 10 8 0 7 LESLIE 10.2 156.8 23 602 +1989 8 26 18 23 TONY 26.3 348.3 163 570 +1999 12 23 0 6 HELENE 42.1 279.3 81 516 +1959 9 12 6 17 NADINE 39.0 242.9 36 298 +1967 10 19 0 27 SANDY 15.2 315.2 69 782 +1976 11 8 18 21 VALERIE 8.2 111.7 30 683 +1981 12 12 0 4 TONY 15.4 193.1 154 329 +1953 10 10 18 4 CHRIS 67.6 190.7 53 420 +1959 7 23 0 13 ISAAC 24.0 333.6 45 124 +1960 3 3 0 28 LESLIE 32.0 92.3 116 589 +1974 12 27 0 13 GORDON 58.6 108.9 151 40 +1994 1 21 12 27 HELENE 17.5 109.1 130 710 +1992 5 16 0 4 OSCAR 28.3 101.1 18 323 +1984 6 13 6 21 MICHAEL 22.9 310.6 23 119 +1998 6 11 12 3 NADINE 10.0 343.3 109 429 +1970 8 2 18 4 ALBERTO 55.4 306.9 145 638 +1974 1 4 0 15 HELENE 35.6 91.0 21 206 +1996 8 4 18 20 BERYL 10.4 225.8 152 846 +1999 10 11 6 21 ERNESTO 16.2 340.1 164 119 +1986 8 5 12 9 OSCAR 51.0 257.8 106 390 +2004 7 10 12 28 ISAAC 60.6 101.2 51 390 +1992 9 27 0 24 VALERIE 67.2 33.8 59 753 +1962 5 4 18 12 DEBBY 46.0 282.8 157 130 +2004 7 13 0 2 JOYCE 65.3 292.3 128 376 +1989 4 14 18 16 VALERIE 13.6 345.0 111 760 +1982 4 16 12 3 PATTY 65.3 237.8 143 68 +1956 1 5 12 5 GORDON 48.7 302.1 70 3 +1998 4 27 6 11 TONY 40.1 20.6 104 688 +1984 10 10 6 15 WILLIAM 27.8 329.7 136 579 +2002 9 19 18 28 WILLIAM 27.6 312.6 68 254 +1984 12 10 18 2 SANDY 14.1 116.0 21 366 +1990 7 11 18 9 ALBERTO 24.4 292.9 49 103 +1982 7 12 12 16 FLORENCE 64.4 70.4 19 789 +1995 11 18 18 16 DEBBY 12.2 327.0 113 841 +1975 9 1 18 26 MICHAEL 33.8 155.2 101 680 +1983 3 5 18 16 ISAAC 64.5 302.1 150 819 +1985 8 19 0 7 NADINE 10.8 19.2 120 838 +2004 3 7 18 1 WILLIAM 62.1 1.6 36 501 +1957 1 25 12 19 VALERIE 20.8 335.3 117 375 +1973 5 1 12 3 ISAAC 30.5 258.4 79 215 +1969 11 11 18 22 GORDON 23.4 5.3 56 663 +1954 5 6 18 5 CHRIS 13.4 56.1 143 690 +1970 1 22 6 19 CHRIS 59.3 164.6 155 167 +1985 5 16 6 14 SANDY 37.8 327.6 66 197 +2000 2 4 12 13 DEBBY 21.3 218.4 147 409 +2004 12 22 0 7 OSCAR 53.3 40.7 160 279 +1986 9 23 0 24 CHRIS 39.5 285.6 76 311 +1990 1 6 12 15 TONY 14.1 190.2 113 42 +1950 9 25 0 27 FLORENCE 59.6 24.5 72 131 +1979 9 10 12 26 KIRK 38.9 57.5 40 472 +1965 7 13 0 27 PATTY 63.4 175.8 141 311 +1975 4 22 18 14 ISAAC 18.5 245.0 85 742 +1958 4 24 12 6 TONY 17.5 274.0 138 710 +1958 4 4 6 3 ISAAC 13.5 319.5 132 892 +1964 9 5 12 5 VALERIE 33.7 151.8 46 626 +1967 11 24 6 14 JOYCE 59.5 82.3 148 826 +1981 11 1 6 17 SANDY 32.1 343.8 69 573 +1969 2 3 0 14 WILLIAM 7.9 66.0 56 772 +1961 1 10 18 24 RAFAEL 64.2 160.2 63 374 +2002 1 10 18 3 LESLIE 38.9 93.5 164 644 +1958 2 16 18 12 KIRK 58.3 337.1 111 242 +1998 4 16 18 5 ERNESTO 66.7 300.0 155 857 +1954 4 3 0 18 GORDON 42.4 263.6 33 409 +1967 6 12 6 11 DEBBY 13.8 264.8 67 492 +1959 5 4 0 15 ALBERTO 34.1 183.9 59 574 +1995 4 21 12 8 FLORENCE 9.9 74.8 37 864 +1995 7 25 18 14 KIRK 40.2 2.4 108 589 +1999 6 1 12 22 FLORENCE 44.8 258.9 21 857 +1983 3 28 0 22 ALBERTO 32.2 234.9 39 130 +1952 9 10 6 8 ERNESTO 15.7 253.8 163 218 +1998 5 13 0 26 VALERIE 37.7 166.6 142 83 +1992 9 24 18 9 ALBERTO 67.7 63.5 94 463 +1965 8 13 0 23 BERYL 30.7 154.3 112 553 +2004 10 26 0 10 JOYCE 35.6 30.7 133 581 +1959 5 21 6 19 BERYL 47.6 179.6 55 439 +2001 8 15 0 2 BERYL 15.1 157.2 38 244 +2002 11 21 18 6 RAFAEL 68.8 213.1 121 789 +1958 6 23 18 6 GORDON 41.7 143.4 52 31 +1982 12 15 12 2 OSCAR 52.2 340.3 34 633 +1966 1 21 12 6 HELENE 25.3 50.7 122 251 +1953 7 6 6 28 SANDY 61.4 67.6 33 263 +1957 3 28 6 26 VALERIE 43.7 62.5 27 185 +1990 10 22 12 8 ERNESTO 69.3 357.8 52 466 +1968 6 1 18 5 OSCAR 27.4 43.0 149 52 +1974 10 25 6 22 CHRIS 47.5 85.9 73 298 +1983 7 26 0 2 TONY 50.9 327.1 139 259 +1979 12 13 0 18 HELENE 39.8 16.2 160 797 +1954 10 27 12 14 VALERIE 8.0 275.0 120 5 +1991 1 25 18 19 SANDY 13.6 91.3 163 686 +1959 6 17 0 27 NADINE 36.2 102.0 126 6 +1958 12 17 18 14 ALBERTO 32.2 23.3 67 410 +1959 7 15 18 13 ALBERTO 58.4 242.0 133 755 +2004 11 12 0 15 HELENE 65.4 313.3 103 778 +1974 9 24 6 14 NADINE 19.5 273.9 35 889 +1981 12 2 12 5 TONY 53.7 115.2 110 191 +1961 8 17 0 3 FLORENCE 48.4 33.5 89 2 +1972 6 22 6 8 HELENE 24.6 144.3 110 554 +1990 5 3 18 6 SANDY 24.6 45.0 155 567 +1965 3 20 0 16 DEBBY 26.6 30.3 138 77 +1976 11 26 0 27 KIRK 9.6 307.4 115 802 +1986 6 12 0 25 FLORENCE 65.6 228.2 39 249 +1963 4 18 12 23 HELENE 42.3 310.9 27 826 +1999 9 15 12 21 SANDY 8.3 218.2 95 155 +1959 9 28 6 8 VALERIE 21.1 332.9 114 85 +1997 11 19 6 8 DEBBY 17.0 233.5 162 584 +1958 1 28 6 1 WILLIAM 20.1 115.7 119 183 +1993 1 8 6 5 ALBERTO 58.9 141.7 128 278 +1954 3 8 18 1 FLORENCE 21.5 244.9 118 286 +1996 8 14 6 27 RAFAEL 20.3 74.7 42 214 +1979 9 5 0 9 BERYL 40.3 151.2 143 121 +1975 10 1 12 9 VALERIE 55.8 173.3 126 457 +1986 5 15 12 16 JOYCE 62.0 300.1 100 100 +1963 9 1 6 7 DEBBY 43.5 198.8 40 372 +1957 9 19 6 2 PATTY 8.5 271.8 122 129 +1953 10 10 12 7 ALBERTO 36.1 346.1 43 784 +1997 3 27 6 10 HELENE 52.0 58.0 72 616 +1998 1 18 12 15 WILLIAM 55.5 272.5 164 468 +1991 10 15 12 1 SANDY 49.1 93.0 95 126 +1987 6 11 12 25 TONY 25.1 92.4 89 198 +1968 4 23 18 1 GORDON 16.2 142.7 52 842 +1987 9 13 6 18 JOYCE 25.4 294.0 18 709 +1999 2 4 0 1 NADINE 57.3 352.6 66 727 +1973 6 28 18 20 MICHAEL 8.3 111.3 125 495 +2004 5 1 18 14 OSCAR 53.7 208.3 43 652 +1973 5 7 6 6 HELENE 14.1 342.1 91 211 +1989 11 28 6 9 SANDY 50.7 346.3 64 205 +1990 7 20 18 22 SANDY 35.1 169.0 24 878 +2000 6 9 6 13 PATTY 11.1 288.5 53 560 +1958 7 24 6 7 GORDON 8.1 212.9 98 464 +1987 2 9 0 8 RAFAEL 44.3 108.2 151 566 +1956 3 7 0 3 ERNESTO 26.4 277.6 44 420 +1961 7 11 18 8 TONY 39.7 137.1 76 200 +1950 5 22 12 4 ALBERTO 35.7 308.9 119 470 +1957 10 26 18 18 ALBERTO 31.5 352.0 87 502 +1971 5 21 6 20 VALERIE 61.1 148.1 138 798 +1963 2 19 12 8 CHRIS 45.0 268.2 14 145 +1964 3 16 0 20 WILLIAM 62.3 64.6 139 587 +1959 12 27 18 19 SANDY 31.6 54.5 125 543 +1953 3 9 6 9 ERNESTO 19.8 186.1 65 241 +1992 10 6 18 20 JOYCE 56.0 120.9 55 185 +1982 9 18 6 28 OSCAR 61.8 193.3 56 361 +1987 2 28 12 8 LESLIE 48.9 101.1 17 858 +1996 10 27 18 11 FLORENCE 32.0 353.2 41 296 +1953 7 14 6 12 ERNESTO 35.2 256.3 70 375 +1992 7 27 18 16 ALBERTO 24.4 183.7 83 779 +1991 8 4 18 9 MICHAEL 11.6 54.2 98 177 +1996 5 25 0 4 KIRK 12.5 258.4 139 868 +1954 6 5 12 22 VALERIE 26.4 226.9 80 634 +1966 8 3 18 17 MICHAEL 28.1 296.8 115 455 +1953 4 27 18 2 ISAAC 19.7 96.7 146 392 +1954 4 8 0 1 ERNESTO 51.7 247.1 100 785 +2000 9 18 0 13 WILLIAM 35.2 105.4 99 774 +1953 11 1 6 3 PATTY 49.8 51.0 159 92 +1997 12 26 6 25 GORDON 47.1 155.8 82 618 +1964 8 14 12 17 ERNESTO 36.8 139.5 20 869 +1958 11 26 18 12 ERNESTO 39.5 296.7 97 6 +1952 7 11 0 7 JOYCE 48.4 281.9 48 481 +1983 4 6 18 13 SANDY 57.7 126.3 146 68 +1960 10 20 12 7 WILLIAM 59.4 279.7 125 228 +1986 3 13 6 3 DEBBY 65.1 155.8 49 237 +1963 10 5 12 11 FLORENCE 8.0 120.7 11 576 +1951 9 6 6 15 LESLIE 32.8 290.3 36 22 +1956 11 17 6 14 ISAAC 52.1 302.9 31 64 +1956 8 4 18 1 MICHAEL 59.0 196.6 143 582 +2000 4 6 12 9 DEBBY 25.9 124.5 43 576 +1993 6 20 18 21 ALBERTO 67.5 187.5 70 7 +1981 8 24 12 8 FLORENCE 15.8 213.6 88 856 +2000 4 13 0 12 DEBBY 35.2 193.1 102 271 +1994 8 13 12 22 JOYCE 47.1 68.1 72 290 +1982 11 12 0 24 KIRK 65.0 294.5 126 682 +1952 7 7 18 7 ERNESTO 43.2 187.4 85 466 +1987 2 3 0 23 FLORENCE 57.4 247.6 147 685 +1985 1 15 18 10 OSCAR 9.6 213.0 73 161 +1961 11 15 18 21 ERNESTO 36.0 226.9 51 882 +1950 6 10 0 12 CHRIS 38.2 194.4 21 525 +1972 2 23 18 2 TONY 17.6 201.7 141 428 +2001 1 7 6 4 DEBBY 29.9 345.3 138 186 +1963 1 28 6 5 FLORENCE 67.9 262.8 23 470 +2002 10 22 12 13 ISAAC 52.1 344.0 159 831 +2001 11 23 6 12 ALBERTO 63.5 129.9 21 126 +1995 9 20 12 14 GORDON 23.0 42.9 111 304 +1995 9 7 6 5 RAFAEL 56.1 295.2 73 814 +1972 12 27 6 6 RAFAEL 20.4 88.8 10 614 +1989 10 11 12 7 TONY 43.0 10.4 131 540 +1978 11 16 6 6 WILLIAM 58.3 175.9 27 183 +1952 3 23 18 2 DEBBY 16.3 186.7 96 802 +1955 5 27 18 26 ALBERTO 17.8 336.4 131 896 +1994 10 10 12 8 WILLIAM 35.6 307.4 88 516 +1950 3 4 12 2 NADINE 51.3 329.1 114 446 +1972 3 3 12 22 OSCAR 38.6 76.2 66 67 +1987 11 26 18 2 MICHAEL 13.6 296.5 137 477 +1988 4 14 18 24 HELENE 53.4 253.8 34 36 +1993 11 11 18 11 WILLIAM 56.8 138.2 113 618 +1974 5 27 18 27 RAFAEL 36.9 264.5 28 47 +1985 3 26 6 19 ISAAC 49.7 2.2 71 766 +1966 3 1 12 15 PATTY 29.5 279.0 47 35 +2001 5 13 18 27 SANDY 69.6 106.2 90 92 +1969 1 26 12 24 KIRK 67.8 119.7 74 666 +1951 5 4 0 12 TONY 41.3 143.3 38 298 +1965 12 4 6 7 KIRK 62.1 345.8 17 605 +1953 3 19 18 16 CHRIS 48.3 157.7 139 106 +1984 6 9 12 18 OSCAR 22.5 214.6 158 342 +1997 8 19 12 15 FLORENCE 64.0 211.1 63 234 +1978 2 17 18 10 DEBBY 58.8 210.3 113 301 +1967 4 10 12 4 ISAAC 54.0 173.7 135 73 +1962 7 27 18 21 WILLIAM 41.8 178.5 133 358 +1992 6 23 0 8 RAFAEL 55.1 185.9 85 20 +1953 10 5 6 17 WILLIAM 14.9 6.4 93 560 +1979 2 26 0 28 FLORENCE 67.3 10.2 104 853 +1987 2 16 18 21 CHRIS 22.9 222.8 67 444 +1975 8 26 12 21 KIRK 40.1 46.0 17 444 +1978 8 13 18 17 MICHAEL 9.7 213.9 127 686 +1966 10 2 18 26 ERNESTO 13.8 44.6 53 664 +1960 9 9 12 21 OSCAR 61.7 146.2 129 344 +2001 7 7 0 11 VALERIE 15.1 152.7 157 583 +1981 4 7 6 21 OSCAR 20.5 198.5 102 836 +1953 11 19 18 2 CHRIS 39.6 327.7 96 795 +1975 4 17 0 20 MICHAEL 26.4 319.5 29 139 +1983 8 9 6 7 LESLIE 35.0 80.0 125 852 +1991 5 1 18 23 KIRK 53.7 231.3 145 384 +1977 2 17 12 11 MICHAEL 33.1 71.7 93 103 +1955 3 17 0 2 CHRIS 48.4 292.4 145 776 +1977 11 2 18 13 NADINE 29.4 348.9 122 574 +1993 11 7 12 25 GORDON 62.7 158.7 158 386 +1970 8 19 6 1 HELENE 64.1 307.1 155 280 +1983 11 12 12 22 CHRIS 43.4 46.9 96 547 +1963 6 22 6 4 GORDON 46.8 156.6 37 636 +1976 9 8 12 4 FLORENCE 67.9 112.8 26 417 +1984 5 13 0 7 CHRIS 53.5 152.9 144 733 +1975 1 16 6 7 TONY 27.0 188.2 78 666 +1962 3 24 18 12 CHRIS 40.5 75.8 78 217 +1958 9 2 18 9 KIRK 20.1 118.6 80 0 +1989 9 6 18 14 WILLIAM 33.9 261.1 67 334 +1985 12 4 18 13 RAFAEL 35.4 134.2 162 721 +2001 5 19 12 20 WILLIAM 63.5 153.6 148 134 +1953 6 19 0 27 NADINE 44.7 168.4 130 76 +1977 6 6 18 12 LESLIE 16.6 331.8 74 584 +1999 12 9 0 4 TONY 45.1 215.3 163 215 +1950 11 6 12 5 TONY 31.6 7.5 66 246 +1985 11 14 18 13 JOYCE 40.6 96.6 137 859 +1980 4 12 6 8 LESLIE 62.4 237.0 135 38 +1951 10 10 12 26 KIRK 14.6 201.2 35 514 +1976 10 23 0 6 BERYL 28.0 43.7 75 169 +1966 3 15 0 24 WILLIAM 35.8 184.3 139 692 +1966 7 12 6 1 TONY 68.2 2.3 45 636 +1977 12 26 6 11 GORDON 8.1 230.2 100 238 +1991 5 9 0 17 GORDON 68.6 137.3 117 143 +1981 2 4 12 24 TONY 29.0 149.1 143 95 +2004 4 17 12 12 RAFAEL 32.3 275.9 151 329 +1984 2 3 12 1 GORDON 14.1 232.0 19 132 +1994 10 24 0 18 BERYL 65.3 267.4 72 882 +1995 9 24 12 2 TONY 41.1 81.5 61 529 +1961 12 14 18 28 TONY 69.4 71.8 152 58 +2004 12 4 12 28 TONY 41.9 12.5 63 835 +1957 2 4 12 28 VALERIE 53.8 257.1 43 307 +1955 12 10 12 3 NADINE 13.6 2.0 44 430 +1953 4 27 0 16 PATTY 30.2 30.8 61 405 +1950 10 22 12 11 ISAAC 32.1 26.2 78 70 +1976 10 8 18 5 LESLIE 17.8 313.4 133 169 +1999 6 10 12 25 WILLIAM 17.5 274.8 70 623 +1967 12 3 12 3 SANDY 13.7 169.7 48 390 +1962 7 13 12 3 ALBERTO 9.4 323.6 11 679 +1998 5 11 0 2 KIRK 51.6 221.8 116 389 +1971 6 7 18 13 FLORENCE 42.3 161.4 136 719 +2002 4 2 12 1 NADINE 39.1 97.5 13 460 +1970 3 25 18 9 SANDY 29.5 285.3 99 675 +1966 6 26 18 3 LESLIE 25.9 76.3 130 720 +1962 7 25 6 15 ERNESTO 46.2 84.7 159 486 +2002 8 24 12 3 CHRIS 65.7 305.9 47 88 +1965 10 18 0 25 BERYL 9.9 85.6 157 26 +1961 2 10 12 3 KIRK 60.0 197.0 144 864 +1970 6 25 6 24 BERYL 49.6 20.7 12 233 +1960 12 8 18 17 HELENE 8.2 85.0 54 406 +1996 3 5 0 2 WILLIAM 10.6 22.4 139 176 +1959 12 8 6 10 SANDY 43.3 291.7 125 749 +1971 11 22 6 10 TONY 31.1 151.0 20 471 +1993 9 17 18 7 VALERIE 16.0 165.3 109 738 +1998 8 25 12 18 LESLIE 40.1 335.6 49 364 +2002 3 24 12 3 WILLIAM 46.8 17.7 135 193 +1958 9 13 0 15 HELENE 38.5 280.7 152 213 +1987 9 8 18 22 OSCAR 15.7 136.1 67 114 +1983 6 12 6 23 WILLIAM 11.9 252.8 53 490 +1982 12 18 0 7 WILLIAM 61.3 155.5 44 244 +1970 1 11 18 16 VALERIE 13.9 105.6 42 149 +1997 6 15 6 2 DEBBY 64.1 201.2 115 653 +1960 4 27 12 13 NADINE 35.7 195.6 162 334 +1982 4 12 18 21 MICHAEL 49.1 223.0 143 512 +1994 10 10 12 27 KIRK 42.1 127.5 110 79 +1990 12 22 18 10 DEBBY 59.0 150.7 31 82 +1985 10 28 6 26 MICHAEL 53.2 58.4 67 273 +1988 10 4 6 3 MICHAEL 45.6 295.6 147 248 +1967 1 26 12 9 OSCAR 50.7 25.9 88 204 +1998 9 17 18 16 BERYL 53.8 251.5 114 49 +1967 3 9 6 16 WILLIAM 30.0 62.0 29 75 +1961 4 11 18 3 CHRIS 65.0 164.3 137 501 +1993 7 15 0 2 WILLIAM 22.2 82.7 39 673 +1980 7 26 0 18 LESLIE 53.7 139.6 97 605 +1976 4 1 6 23 GORDON 8.6 124.8 115 693 +1962 1 14 12 15 ERNESTO 44.0 268.1 139 205 +1973 4 3 0 9 BERYL 28.0 25.9 78 767 +1967 3 27 6 27 ISAAC 60.3 328.1 139 572 +1956 9 25 12 26 NADINE 51.3 24.2 140 287 +1999 12 15 12 22 GORDON 15.6 171.9 111 64 +1971 6 7 18 6 SANDY 18.7 76.0 18 860 +1980 5 23 12 3 WILLIAM 10.9 17.5 63 553 +1987 3 20 0 3 TONY 42.6 99.3 75 192 +1958 12 24 0 16 PATTY 30.7 13.7 81 805 +1964 6 1 12 14 LESLIE 28.0 94.3 36 436 +1987 8 25 18 3 JOYCE 20.5 74.7 52 313 +1981 5 12 12 20 ERNESTO 30.6 335.8 51 450 +1966 11 23 12 17 MICHAEL 49.5 163.7 26 123 +1952 9 11 0 12 JOYCE 56.4 145.2 41 494 +1960 8 16 12 3 SANDY 47.2 61.8 102 778 +2000 5 27 6 4 WILLIAM 16.5 270.3 142 869 +1997 7 24 0 3 PATTY 25.9 271.9 18 844 +1993 10 19 12 25 TONY 69.0 195.1 87 234 +1960 6 12 18 16 CHRIS 61.5 22.1 78 49 +1961 3 9 0 13 BERYL 26.7 60.6 145 554 +1975 7 23 6 6 ERNESTO 48.4 202.2 78 436 +2004 11 17 12 3 VALERIE 68.7 219.8 164 847 +1970 10 9 18 28 PATTY 66.9 303.8 56 322 +1985 4 17 0 23 LESLIE 28.4 264.3 60 546 +1976 1 20 6 5 PATTY 63.0 87.5 164 505 +1950 2 11 0 6 ERNESTO 29.8 72.4 10 219 +2002 9 6 18 22 LESLIE 19.5 313.2 81 639 +1997 9 28 18 17 KIRK 25.7 256.1 45 149 +2000 2 10 6 8 CHRIS 41.9 242.6 135 727 +1983 9 11 18 27 FLORENCE 36.8 315.6 126 266 +1962 9 2 0 24 OSCAR 37.0 44.2 57 566 +1950 1 22 18 19 PATTY 31.1 352.3 116 222 +1970 4 15 0 1 VALERIE 12.9 99.3 36 328 +1983 8 1 18 7 HELENE 33.4 169.5 48 35 +1993 10 2 6 3 HELENE 32.6 15.3 30 5 +1983 8 27 0 3 ISAAC 9.7 59.1 160 29 +1992 8 25 12 26 MICHAEL 49.4 256.1 113 106 +1975 12 8 6 18 OSCAR 38.7 283.0 115 718 +1962 10 10 0 19 FLORENCE 26.9 140.9 83 131 +1952 1 22 0 23 DEBBY 55.3 61.4 62 130 +1979 4 19 12 26 GORDON 67.8 116.8 111 554 +1976 9 19 12 7 NADINE 28.8 86.0 90 203 +1977 9 19 6 7 ISAAC 48.0 330.7 132 403 +1973 4 23 18 17 CHRIS 49.3 81.9 158 427 +1968 12 22 12 2 JOYCE 13.4 322.0 130 338 +1997 6 24 12 27 KIRK 56.7 131.3 49 657 +1997 4 6 12 13 PATTY 55.9 144.2 12 184 +1994 7 22 12 23 BERYL 53.1 153.3 41 216 +1954 10 23 0 14 KIRK 49.9 153.6 143 599 +1971 10 9 6 5 LESLIE 60.4 198.0 36 325 +1957 11 16 0 7 VALERIE 64.4 12.4 96 117 +1984 1 24 6 4 DEBBY 38.6 133.4 145 527 +1986 10 19 18 25 CHRIS 62.5 145.7 91 519 +2003 5 10 18 4 TONY 10.3 311.6 151 58 +1960 11 22 6 15 KIRK 44.4 128.5 45 367 +1964 8 27 18 24 GORDON 55.3 297.6 163 74 +1966 10 4 6 13 ALBERTO 69.9 358.0 161 573 +1991 10 10 0 25 ISAAC 20.2 73.6 20 414 +1961 8 5 18 20 ALBERTO 16.3 189.4 27 678 +1999 4 1 0 9 GORDON 10.8 279.3 99 349 +1981 11 28 12 9 OSCAR 35.1 226.4 159 879 +1954 6 9 18 11 WILLIAM 12.2 280.7 77 234 +1957 11 9 18 26 CHRIS 34.2 317.7 30 421 +2000 8 10 6 1 WILLIAM 52.5 153.6 159 349 +1960 3 17 12 8 JOYCE 57.3 147.0 143 719 +1997 11 12 6 7 ISAAC 52.7 199.0 136 578 +2000 5 21 0 14 DEBBY 63.6 285.6 145 570 +1956 9 25 6 19 TONY 57.5 235.5 115 661 +1954 11 14 18 15 LESLIE 17.5 216.1 42 603 +2002 11 5 6 5 PATTY 29.3 12.8 75 6 +1976 9 21 0 13 NADINE 43.3 285.4 98 421 +2002 4 6 12 1 KIRK 47.3 6.5 138 340 +1952 5 3 0 17 CHRIS 49.5 14.1 40 574 +1980 8 1 12 2 KIRK 49.5 227.0 61 617 +1965 5 5 18 18 SANDY 44.4 295.8 43 681 +2004 6 24 12 17 KIRK 57.8 23.3 107 45 +1997 11 7 12 28 CHRIS 55.7 140.9 111 544 +1998 7 27 0 17 PATTY 49.8 99.9 122 897 +1964 11 6 6 15 WILLIAM 13.0 7.7 131 468 +1991 1 16 6 24 OSCAR 45.4 190.5 119 32 +1964 6 5 6 19 WILLIAM 42.8 47.0 36 654 +1970 4 22 18 8 VALERIE 44.1 237.1 103 75 +1986 9 15 6 12 LESLIE 30.8 341.7 110 301 +1973 11 18 18 14 SANDY 52.3 237.9 138 501 +1954 12 4 6 28 MICHAEL 46.0 288.3 37 89 +1985 8 8 18 10 KIRK 58.5 93.5 19 78 +1989 10 27 12 13 KIRK 28.8 325.7 133 572 +1992 5 6 12 28 ALBERTO 7.9 222.4 10 871 +1989 3 9 12 9 BERYL 39.8 103.0 90 2 +1954 3 21 18 21 HELENE 19.4 73.3 24 500 +1971 6 16 12 4 BERYL 60.5 311.7 50 96 +1981 9 18 18 13 KIRK 19.2 150.4 41 742 +1997 5 23 18 25 LESLIE 53.1 319.1 31 24 +1976 8 26 12 14 SANDY 64.2 259.5 15 361 +1998 7 16 6 9 GORDON 34.9 267.3 111 316 +1979 9 9 12 27 TONY 14.6 205.4 40 326 +1996 7 6 18 26 DEBBY 20.9 229.7 84 469 +1962 3 16 12 20 ISAAC 64.0 270.8 22 830 +1953 7 16 12 24 NADINE 14.5 262.5 126 386 +1963 1 24 6 16 LESLIE 27.7 345.8 41 499 +1975 4 17 6 11 NADINE 48.8 308.4 42 73 +1980 2 14 6 27 MICHAEL 15.1 273.3 90 280 +1961 10 8 18 3 VALERIE 37.2 215.5 85 157 +2003 8 1 18 2 GORDON 9.1 27.6 16 636 +1969 11 11 0 9 CHRIS 27.4 31.2 42 718 +1965 1 26 18 27 CHRIS 11.3 169.7 38 255 +1987 5 26 12 3 DEBBY 70.0 268.8 144 98 +1989 2 14 12 26 SANDY 24.7 332.5 13 19 +1977 9 4 6 21 RAFAEL 23.5 126.0 51 192 +1952 7 22 18 4 ALBERTO 26.1 112.0 53 245 +1951 2 26 18 4 JOYCE 59.5 209.7 136 241 +1958 10 4 12 8 WILLIAM 19.2 43.5 100 849 +1955 6 20 18 21 PATTY 37.5 64.0 84 409 +1971 10 2 18 16 PATTY 54.6 37.3 151 326 +1957 9 20 0 18 MICHAEL 38.1 80.0 61 877 +1970 12 5 18 21 GORDON 18.3 223.3 46 28 +1980 12 16 18 8 VALERIE 33.7 163.3 96 126 +2003 1 3 0 6 OSCAR 30.9 84.1 61 288 +1969 8 16 12 6 ALBERTO 7.8 41.4 161 121 +1985 4 4 18 25 VALERIE 31.7 159.4 26 748 +1950 7 8 0 17 CHRIS 63.1 97.7 56 519 +1984 7 21 18 9 MICHAEL 29.9 130.5 161 844 +1995 3 21 6 22 DEBBY 27.6 95.5 112 891 +1990 10 5 6 26 FLORENCE 48.7 57.2 66 51 +1952 4 6 12 28 BERYL 25.6 80.1 80 97 +1972 2 23 18 24 SANDY 49.7 312.2 112 218 +1978 12 6 12 5 JOYCE 16.9 206.5 30 203 +1966 4 22 0 20 PATTY 35.3 44.6 156 477 +1970 10 17 18 17 PATTY 51.6 91.7 107 835 +1952 9 18 18 3 ERNESTO 20.7 71.4 162 224 +1984 6 12 18 13 DEBBY 19.0 18.7 38 884 +1971 8 1 18 22 TONY 62.3 55.5 97 857 +1971 3 9 12 27 CHRIS 15.1 53.1 45 241 +1961 8 13 0 13 SANDY 48.7 99.9 72 115 +1969 4 16 18 15 LESLIE 11.1 7.6 150 47 +2002 4 19 12 6 BERYL 9.3 164.8 34 816 +2001 6 2 0 23 HELENE 55.7 63.8 34 719 +1957 3 20 12 24 MICHAEL 34.3 108.6 84 409 +1982 6 19 0 6 BERYL 22.1 178.4 39 883 +1983 4 22 6 10 KIRK 45.4 313.4 79 4 +1965 8 17 0 7 ERNESTO 48.1 95.2 85 37 +1991 12 26 12 22 OSCAR 8.3 298.3 105 361 +2004 7 13 18 19 TONY 14.0 240.0 149 775 +1993 4 27 0 27 ERNESTO 43.2 337.7 31 340 +1955 1 10 18 24 DEBBY 43.8 206.6 105 136 +1971 8 11 0 27 BERYL 50.4 193.9 34 57 +2003 6 14 12 20 GORDON 8.1 323.4 82 290 +1977 8 28 6 22 NADINE 52.9 152.2 161 864 +1956 6 24 12 28 ISAAC 21.6 270.9 28 303 +1962 3 19 18 3 BERYL 16.5 186.8 40 269 +1955 1 27 18 17 WILLIAM 65.3 266.4 81 615 +1997 10 25 12 27 HELENE 56.8 127.0 48 816 +1984 12 22 12 22 ISAAC 52.0 81.0 133 261 +1964 10 17 0 6 RAFAEL 33.4 296.7 129 738 +1990 9 5 12 21 RAFAEL 35.5 291.6 155 182 +1992 4 13 6 14 ISAAC 62.8 279.4 97 344 +1955 2 28 6 18 KIRK 12.8 181.3 142 670 +1997 6 25 6 18 LESLIE 32.2 153.7 46 244 +1995 9 23 0 11 RAFAEL 44.4 209.9 52 379 +1950 4 21 12 19 BERYL 45.5 347.4 157 750 +1982 5 24 0 28 DEBBY 13.6 217.5 66 472 +1991 9 16 0 9 GORDON 42.1 341.6 24 534 +1964 5 10 6 21 VALERIE 59.3 347.8 94 801 +1969 6 14 12 25 PATTY 46.3 96.4 144 218 +1976 10 20 6 2 NADINE 41.7 321.1 51 423 +1989 6 5 18 17 ERNESTO 63.3 133.5 113 871 +1998 1 26 12 3 NADINE 42.5 159.1 49 306 +1951 8 28 12 24 HELENE 50.0 149.4 55 757 +1987 9 23 12 10 ALBERTO 52.7 299.4 117 559 +1977 8 7 0 24 GORDON 33.8 314.5 69 410 +1950 11 4 0 17 WILLIAM 61.0 247.4 30 384 +1955 4 18 6 11 BERYL 13.6 248.5 133 555 +1996 10 15 0 4 SANDY 64.2 114.6 24 780 +2002 8 9 18 11 RAFAEL 45.5 43.7 79 604 +1979 12 6 6 27 WILLIAM 50.6 38.4 125 211 +1983 2 22 12 19 TONY 57.9 287.6 136 236 +1976 2 19 12 19 FLORENCE 11.5 75.4 39 711 +1983 11 16 18 2 ERNESTO 56.8 126.0 95 82 +1969 8 26 0 10 GORDON 60.6 161.4 60 837 +1954 7 10 12 2 BERYL 25.0 290.2 71 457 +1950 12 16 18 16 LESLIE 65.0 281.5 158 840 +2002 10 19 0 13 KIRK 54.1 50.1 13 898 +1988 5 11 6 17 BERYL 42.7 210.0 95 292 +1993 1 27 0 3 LESLIE 62.9 191.4 129 869 +2004 11 14 12 2 LESLIE 53.1 320.1 11 744 +1966 10 25 18 7 VALERIE 67.9 202.6 112 665 +1998 6 21 12 26 ALBERTO 59.1 330.2 34 399 +1973 7 22 0 6 HELENE 61.9 197.4 11 352 +1966 6 5 12 19 ALBERTO 62.6 246.5 72 791 +1985 5 11 12 2 GORDON 67.7 194.0 78 198 +2000 4 22 6 17 ERNESTO 65.3 67.6 65 730 +1972 5 26 0 9 ERNESTO 20.4 175.2 116 184 +1969 9 15 12 5 OSCAR 62.8 185.4 12 699 +1983 8 3 18 21 KIRK 52.4 98.5 25 880 +2000 2 1 6 3 ALBERTO 12.3 115.5 128 259 +1990 6 16 18 20 GORDON 20.5 20.6 62 528 +1989 9 16 6 4 ERNESTO 68.5 15.3 42 393 +1984 5 1 0 9 SANDY 49.2 187.1 13 858 +1981 6 18 0 19 FLORENCE 22.9 207.2 69 754 +1972 6 24 0 4 BERYL 26.6 56.3 113 231 +1976 9 16 18 9 HELENE 12.0 314.3 46 378 +2003 11 10 6 23 OSCAR 12.9 249.3 91 376 +1982 11 13 18 13 HELENE 15.2 317.3 12 645 +1991 5 11 6 27 SANDY 60.2 61.7 99 195 +1968 1 23 18 8 HELENE 33.4 194.7 155 853 +2002 7 26 12 17 GORDON 57.9 319.7 101 788 +1987 4 25 12 21 ERNESTO 26.3 339.9 44 697 +1964 9 22 12 13 VALERIE 41.9 320.6 114 792 +1985 4 15 18 18 SANDY 22.0 64.7 88 652 +1967 6 2 12 14 BERYL 29.9 314.9 85 162 +1955 2 20 12 19 FLORENCE 19.0 321.0 146 247 +1981 4 11 6 23 WILLIAM 39.7 60.2 81 777 +1955 9 1 18 1 ALBERTO 9.4 34.2 75 252 +1951 12 17 0 24 HELENE 40.2 237.5 84 597 +1990 9 21 0 20 TONY 65.8 305.8 132 866 +1988 1 13 6 13 PATTY 57.7 20.9 33 135 +2000 12 1 6 22 TONY 39.1 283.3 49 554 +1956 12 19 12 14 ALBERTO 60.3 111.4 146 149 +1970 4 20 12 19 ISAAC 23.0 195.6 104 834 +1954 10 21 0 1 RAFAEL 41.3 223.2 77 54 +1965 1 19 12 6 NADINE 17.2 69.1 115 677 +1973 8 27 12 22 ALBERTO 51.2 79.0 20 305 +1992 9 24 0 25 ALBERTO 46.3 7.9 37 685 +1987 11 21 6 9 BERYL 34.1 271.7 163 234 +1973 6 25 6 23 TONY 53.6 216.3 137 182 +2003 1 24 0 11 ISAAC 31.5 44.0 27 448 +1964 12 11 6 28 SANDY 40.4 93.1 26 129 +1955 9 7 18 3 VALERIE 44.0 153.0 150 546 +1997 6 26 12 24 CHRIS 24.5 235.8 114 664 +1965 12 13 6 7 VALERIE 38.0 314.2 28 397 +2004 8 21 0 20 ERNESTO 40.5 74.5 118 389 +1975 11 26 12 19 NADINE 59.9 114.0 64 399 +1973 6 8 0 6 SANDY 18.0 141.9 137 404 +1964 8 15 0 12 BERYL 17.2 295.2 58 342 +1973 3 20 6 18 ERNESTO 11.0 170.8 87 596 +2002 1 2 12 2 HELENE 34.2 174.4 143 557 +2002 6 11 6 4 RAFAEL 60.0 249.5 115 700 +1994 2 12 12 5 CHRIS 22.6 350.4 87 784 +1955 11 12 6 27 GORDON 25.8 4.1 138 831 +1974 2 20 6 25 OSCAR 56.8 142.5 28 393 +1952 2 7 12 14 PATTY 28.7 182.6 159 498 +2003 1 16 0 22 SANDY 65.1 208.8 85 122 +1990 11 15 18 28 CHRIS 16.3 51.0 68 839 +1989 11 24 0 5 OSCAR 43.7 349.1 145 34 +1973 2 15 6 13 ALBERTO 38.3 162.1 86 83 +1979 2 11 6 1 JOYCE 67.0 311.8 135 277 +1999 9 22 6 3 ALBERTO 41.4 121.7 16 551 +2003 3 15 0 14 FLORENCE 10.5 89.2 140 761 +1988 3 22 6 3 WILLIAM 15.3 116.4 59 4 +1997 3 26 12 9 WILLIAM 55.3 204.6 50 319 +1979 5 25 0 11 FLORENCE 31.0 300.0 69 378 +1960 4 5 18 4 GORDON 23.2 344.1 29 438 +1997 10 11 0 17 TONY 42.9 195.6 88 97 +1954 5 5 12 24 ISAAC 43.8 242.7 116 343 +1954 12 21 12 18 HELENE 29.3 79.5 101 569 +1980 3 10 0 26 WILLIAM 21.8 23.4 141 796 +1955 10 9 18 11 JOYCE 65.4 294.0 106 828 +1990 11 19 18 5 OSCAR 61.4 145.8 19 768 +1996 12 12 18 14 LESLIE 63.9 117.0 23 48 +1973 2 4 12 12 TONY 50.6 33.5 120 687 +1983 11 10 0 17 GORDON 12.6 287.8 63 642 +1994 7 27 18 22 ISAAC 22.8 320.9 15 606 +1965 9 21 18 2 VALERIE 24.5 270.4 99 856 +1952 1 16 18 25 CHRIS 29.8 252.7 13 25 +1995 5 3 0 8 KIRK 8.7 159.1 34 302 +1967 1 17 0 5 LESLIE 62.9 337.9 79 436 +1951 12 18 12 13 TONY 38.5 242.9 104 689 +1966 2 21 18 28 ISAAC 53.3 332.0 86 374 +1976 9 21 0 9 NADINE 25.5 105.1 115 581 +1979 12 24 12 10 HELENE 8.3 325.4 65 518 +1988 8 15 18 1 LESLIE 29.1 341.1 86 341 +1988 11 8 12 5 JOYCE 46.6 218.0 113 596 +1997 6 4 0 21 LESLIE 18.3 202.2 164 744 +1957 4 7 18 22 ALBERTO 68.8 300.2 94 615 +1955 12 16 18 3 RAFAEL 36.7 335.1 126 268 +1976 11 10 18 7 DEBBY 14.2 169.3 154 663 +1968 2 22 0 6 FLORENCE 30.9 228.7 164 475 +1988 8 23 0 2 WILLIAM 55.2 326.5 146 574 +1966 4 20 6 25 CHRIS 13.3 168.4 57 101 +1979 6 20 18 4 VALERIE 53.8 277.3 108 408 +1963 5 18 12 2 KIRK 58.2 222.0 52 136 +1950 4 11 18 6 ISAAC 60.7 73.2 15 728 +1980 9 17 12 26 VALERIE 62.2 41.0 96 370 +1961 12 8 18 16 DEBBY 15.4 242.9 123 643 +1954 10 15 12 2 CHRIS 42.6 45.3 131 446 +1999 9 3 0 25 VALERIE 44.9 175.7 51 486 +1989 8 9 12 21 LESLIE 50.7 16.1 162 195 +1989 8 16 12 28 TONY 7.8 72.5 125 262 +1970 11 7 12 17 ISAAC 46.4 290.5 51 533 +1994 1 12 18 17 RAFAEL 25.4 311.2 155 858 +1967 2 14 12 17 JOYCE 7.3 340.8 144 422 +1953 6 4 0 22 RAFAEL 12.2 122.0 131 139 +1996 1 17 12 28 TONY 39.4 325.2 162 861 +1968 10 9 0 28 DEBBY 67.3 58.2 120 119 +1975 4 6 12 24 ERNESTO 68.5 35.6 75 114 +1958 3 14 0 4 BERYL 11.0 291.9 14 162 +1965 10 22 12 12 LESLIE 48.9 327.3 25 290 +1979 8 6 6 22 DEBBY 34.8 64.0 104 224 +2003 6 27 18 28 JOYCE 44.3 72.0 23 564 +1992 3 8 6 22 RAFAEL 20.0 293.2 162 896 +1988 1 1 6 11 WILLIAM 60.6 226.1 82 343 +1966 12 23 6 19 OSCAR 48.3 114.8 135 189 +1970 3 17 0 5 SANDY 25.8 7.7 122 183 +1959 5 10 0 9 KIRK 40.9 314.4 66 189 +1978 11 23 6 15 KIRK 9.9 63.5 71 839 +2000 4 8 6 4 NADINE 20.1 155.1 25 269 +1950 9 22 0 23 JOYCE 56.4 340.5 161 50 +1995 11 2 12 6 GORDON 48.6 134.4 20 586 +1984 8 18 0 11 TONY 7.4 99.1 103 115 +1971 1 7 12 28 MICHAEL 69.2 261.2 128 492 +1974 12 22 18 13 VALERIE 12.5 31.7 154 73 +1976 5 26 12 4 ERNESTO 50.1 99.8 41 76 +1960 4 8 0 25 WILLIAM 59.2 26.8 41 752 +1963 7 19 12 2 ISAAC 23.1 283.8 149 608 +1999 2 21 12 14 OSCAR 13.0 186.1 45 778 +1990 8 21 18 7 HELENE 7.1 341.0 10 541 +1990 11 4 18 7 WILLIAM 57.6 68.7 158 337 +1962 1 28 6 11 KIRK 43.7 109.4 117 475 +1987 8 9 0 21 LESLIE 58.5 346.3 109 743 +1975 11 11 18 19 NADINE 7.6 189.0 54 762 +1978 10 20 0 2 ALBERTO 65.9 214.6 84 698 +1997 11 10 12 15 NADINE 25.1 182.1 114 220 +1958 11 22 0 23 SANDY 14.8 108.3 113 693 +1993 1 12 12 1 TONY 62.7 157.0 147 881 +1993 3 4 0 19 ALBERTO 33.0 176.5 84 464 +1981 1 18 0 10 ERNESTO 20.1 357.1 135 163 +1993 8 6 0 22 ALBERTO 34.2 175.2 41 205 +1975 8 24 18 5 BERYL 19.8 315.8 80 458 +1960 8 4 12 9 TONY 25.6 246.9 78 219 +1950 9 16 18 14 ERNESTO 56.5 74.5 69 814 +1970 5 20 18 26 ISAAC 39.0 31.4 88 899 +1955 6 5 12 28 JOYCE 24.0 132.4 98 227 +1984 1 22 6 13 NADINE 15.7 77.9 104 620 +1960 5 26 6 6 GORDON 16.3 54.7 73 193 +1981 6 14 12 10 ERNESTO 32.3 290.2 97 588 +1975 6 28 0 28 CHRIS 20.1 97.1 150 722 +1953 9 1 6 14 VALERIE 39.9 50.8 24 130 +1975 5 7 0 16 ALBERTO 43.8 273.3 43 52 +1997 11 3 6 21 BERYL 36.7 215.0 91 543 +1978 1 4 0 21 TONY 63.3 84.4 106 209 +1983 10 26 6 1 SANDY 48.9 60.1 160 209 +1960 3 14 0 19 OSCAR 43.2 185.3 58 131 +1992 9 5 18 13 RAFAEL 33.8 273.6 77 470 +1966 5 24 0 18 NADINE 60.5 96.3 71 306 +1967 4 1 0 27 NADINE 52.5 188.6 12 871 +1958 7 1 6 21 JOYCE 33.5 149.9 146 332 +1955 11 4 0 9 LESLIE 34.9 259.8 115 453 +1956 10 26 0 9 LESLIE 24.6 255.0 109 34 +1984 2 23 0 17 SANDY 61.2 312.9 39 569 +1995 3 3 12 14 TONY 67.2 93.6 88 217 +1988 11 3 12 18 ALBERTO 67.8 329.0 60 425 +1959 4 2 6 16 VALERIE 18.1 62.8 53 301 +1966 6 17 12 27 BERYL 61.4 75.6 40 74 +1995 7 26 18 25 ALBERTO 59.5 225.0 113 819 +2004 2 27 18 15 ALBERTO 7.5 299.3 132 447 +1954 10 27 12 23 ISAAC 38.1 126.4 12 230 +1987 12 21 6 14 RAFAEL 57.4 332.1 113 819 +1959 10 11 18 28 BERYL 24.4 307.4 56 843 +1972 12 20 18 6 MICHAEL 63.5 106.0 124 879 +1995 10 25 6 9 HELENE 40.5 164.1 50 489 +1962 8 14 18 13 ERNESTO 64.7 133.9 122 413 +1993 11 17 18 20 LESLIE 24.3 347.6 94 91 +1960 2 14 12 24 SANDY 54.1 11.4 152 54 +1965 9 8 6 20 KIRK 48.0 46.2 120 141 +1962 2 6 18 5 VALERIE 41.5 81.3 67 623 +1950 8 2 12 13 LESLIE 31.1 207.5 99 654 +1995 2 3 12 4 KIRK 35.4 14.4 69 647 +1996 5 8 18 24 OSCAR 51.3 1.8 14 238 +2002 4 25 0 20 KIRK 43.4 32.5 72 343 +1957 6 24 0 23 ALBERTO 61.6 192.7 80 461 +1975 3 3 12 14 ALBERTO 14.8 98.5 56 584 +1977 7 4 18 3 HELENE 53.5 24.9 68 548 +1979 4 26 6 10 ISAAC 17.0 354.8 23 118 +1988 6 6 12 3 NADINE 18.6 112.4 31 561 +1951 1 26 6 15 VALERIE 9.3 266.6 146 309 +1975 3 21 6 24 ERNESTO 43.3 194.6 29 352 +1973 7 19 18 5 SANDY 36.9 241.6 46 641 +1963 10 23 12 12 PATTY 63.8 115.7 45 754 +1998 5 4 18 13 LESLIE 64.3 43.1 132 393 +1975 4 25 18 9 KIRK 42.5 221.9 110 4 +1992 5 21 0 16 ERNESTO 42.8 319.2 152 829 +1985 3 19 12 13 SANDY 67.3 111.7 18 717 +1998 1 17 0 12 SANDY 17.0 2.3 135 736 +1981 7 21 0 9 NADINE 52.7 333.0 157 705 +1975 7 19 12 14 BERYL 27.0 344.8 121 426 +1991 2 15 0 11 LESLIE 66.7 176.6 53 717 +1972 3 7 6 10 RAFAEL 25.8 286.8 152 86 +2001 1 19 6 4 ALBERTO 63.6 270.5 105 182 +1985 5 15 18 2 PATTY 14.9 169.4 153 430 +1993 1 18 6 1 HELENE 33.8 225.0 40 705 +1969 8 13 6 13 ALBERTO 44.2 79.7 96 778 +1973 12 27 6 11 ALBERTO 68.9 40.5 61 172 +1997 5 20 0 11 BERYL 66.3 176.7 61 202 +1971 4 22 18 5 VALERIE 46.3 77.3 87 641 +1977 3 25 18 20 GORDON 46.7 10.7 74 678 +1983 4 14 6 21 NADINE 37.8 70.7 32 393 +1960 11 27 0 3 ISAAC 45.8 333.0 37 754 +1955 6 5 12 1 BERYL 64.8 35.0 41 442 +1951 10 25 0 19 DEBBY 19.8 284.5 80 34 +2001 7 1 18 4 MICHAEL 8.0 276.3 33 274 +1989 6 23 12 4 PATTY 69.1 252.6 113 46 +1958 6 7 18 26 JOYCE 19.9 219.6 117 40 +1953 2 7 0 4 ISAAC 12.2 129.5 73 258 +1976 11 15 0 7 TONY 39.3 133.6 61 572 +1984 10 26 6 24 CHRIS 20.6 139.9 33 30 +1969 10 23 0 11 BERYL 16.7 108.6 157 13 +1961 9 23 12 14 BERYL 64.6 225.5 111 322 +1954 5 9 6 8 HELENE 63.1 61.9 54 253 +1995 1 12 6 26 ERNESTO 38.4 339.3 24 523 +1999 7 17 6 27 MICHAEL 30.8 207.1 36 390 +1969 6 16 6 24 ERNESTO 69.3 345.9 123 595 +1980 9 4 18 17 RAFAEL 36.4 222.2 91 139 +1998 5 4 6 17 VALERIE 29.2 120.9 144 721 +1953 10 7 6 3 NADINE 36.9 21.3 38 710 +1984 11 13 18 26 TONY 37.2 104.1 89 32 +1969 12 7 0 11 BERYL 37.4 174.1 93 32 +1957 9 17 12 9 DEBBY 17.4 14.5 115 359 +1974 1 19 12 2 RAFAEL 45.5 308.0 13 56 +1979 3 15 6 7 CHRIS 14.6 315.2 77 367 +1960 11 3 0 16 FLORENCE 30.8 28.9 73 790 +1972 10 3 0 7 MICHAEL 58.8 222.6 38 558 +1968 8 10 0 26 HELENE 36.6 135.7 142 524 +1968 11 13 18 8 ALBERTO 54.6 330.6 37 302 +1978 12 23 12 15 GORDON 29.1 195.1 142 712 +1979 5 20 12 27 GORDON 47.8 90.5 132 347 +1985 3 10 12 27 FLORENCE 44.5 250.7 80 868 +1973 8 1 6 3 HELENE 55.1 274.1 161 418 +1962 9 5 12 24 SANDY 34.4 285.5 48 37 +1961 4 6 0 23 HELENE 27.1 183.0 163 161 +1986 8 10 6 21 CHRIS 66.7 191.6 103 447 +1986 3 13 0 14 ISAAC 56.1 347.3 92 425 +1956 5 19 12 18 ERNESTO 66.9 123.5 73 675 +1996 12 23 18 27 PATTY 60.5 283.2 31 146 +1974 5 10 12 16 PATTY 66.8 29.5 33 443 +1999 6 10 6 15 TONY 69.0 202.4 141 218 +1986 5 6 18 8 OSCAR 21.9 146.0 52 796 +1960 5 12 12 19 MICHAEL 21.4 145.4 107 843 +1952 4 6 18 11 WILLIAM 56.4 220.4 94 57 +1955 6 20 6 2 ERNESTO 66.4 29.0 82 127 +1952 5 4 6 4 LESLIE 8.9 286.8 146 586 +1978 1 11 12 16 NADINE 8.4 317.4 91 820 +1961 7 23 0 7 ISAAC 67.5 182.8 105 793 +1973 6 20 0 23 FLORENCE 42.5 139.6 48 741 +1965 6 9 18 21 WILLIAM 45.1 333.3 36 385 +1955 12 25 6 2 LESLIE 38.0 356.2 15 456 +1989 10 28 0 3 MICHAEL 45.3 183.7 141 453 +1996 9 6 12 11 JOYCE 49.3 84.1 125 402 +1987 5 8 18 22 NADINE 61.7 264.4 52 873 +1982 7 8 18 17 ERNESTO 8.5 326.4 67 246 +1997 10 4 0 6 KIRK 64.2 199.2 143 475 +1976 5 4 12 28 ERNESTO 37.1 331.4 127 139 +1986 11 24 12 5 LESLIE 31.8 81.9 93 66 +1961 8 25 18 6 SANDY 61.7 2.1 15 437 +2001 3 23 6 9 RAFAEL 62.8 137.9 80 818 +1977 2 3 12 23 BERYL 64.6 109.0 109 852 +1964 11 2 0 13 HELENE 8.3 160.0 17 50 +1991 10 9 6 22 OSCAR 25.4 280.8 66 648 +1958 1 5 0 26 TONY 52.0 84.4 86 314 +1992 6 17 6 14 TONY 50.0 97.1 11 574 +1998 6 25 18 7 CHRIS 62.4 207.7 15 668 +1986 9 17 12 27 NADINE 12.6 345.3 121 107 +1989 10 25 18 14 KIRK 32.0 77.0 133 785 +1998 2 2 0 19 BERYL 26.5 264.4 10 654 +1974 6 28 12 23 CHRIS 43.9 1.1 23 106 +1997 5 17 12 15 BERYL 25.3 311.6 97 897 +1986 1 21 12 26 FLORENCE 51.7 68.1 107 725 +1958 3 14 6 1 VALERIE 35.8 42.1 34 474 +1979 7 6 12 8 RAFAEL 66.2 65.8 14 723 +1971 4 22 18 23 GORDON 21.8 103.6 82 353 +1960 1 25 6 25 ISAAC 39.9 256.6 139 655 +1988 9 21 0 25 MICHAEL 25.0 281.1 150 620 +1976 12 7 0 13 LESLIE 60.6 244.9 63 795 +1961 12 27 0 17 GORDON 17.8 13.1 21 891 +1975 7 17 0 23 KIRK 56.7 25.7 114 591 +1977 11 22 18 17 MICHAEL 16.4 203.6 152 755 +1977 1 15 18 17 RAFAEL 32.4 87.1 66 538 +1986 8 8 6 18 VALERIE 24.6 321.8 46 615 +1999 1 28 0 6 ISAAC 7.7 72.9 11 165 +1998 7 9 18 5 JOYCE 15.1 337.0 15 687 +1961 1 7 6 18 DEBBY 53.9 260.8 64 285 +1971 4 23 6 7 VALERIE 55.8 157.7 44 132 +1981 12 19 18 9 DEBBY 27.6 120.9 80 495 +1954 1 27 6 22 TONY 21.4 203.6 110 299 +1950 1 14 6 7 GORDON 49.5 164.5 138 66 +1993 2 13 0 10 NADINE 23.2 156.7 87 301 +1998 10 23 6 19 RAFAEL 42.4 283.5 86 120 +1950 4 4 18 20 MICHAEL 47.0 47.9 71 240 +1977 9 7 6 11 PATTY 24.1 239.4 111 765 +1981 10 14 18 8 VALERIE 47.7 284.0 87 312 +1997 11 18 18 28 FLORENCE 30.8 335.7 83 825 +1958 8 5 18 5 JOYCE 53.1 341.5 162 180 +1995 4 6 6 23 MICHAEL 37.1 308.2 123 363 +1989 3 9 0 17 ISAAC 62.3 213.5 88 85 +1957 8 19 18 17 ISAAC 37.4 6.7 158 88 +1995 3 20 18 6 NADINE 10.4 345.6 60 499 +1982 6 21 6 4 ALBERTO 22.3 229.1 73 819 +2003 9 24 12 2 DEBBY 69.1 105.3 154 356 +1997 6 8 6 13 WILLIAM 69.5 96.3 65 372 +1969 4 10 18 8 TONY 64.3 66.6 162 707 +1998 4 16 12 18 SANDY 32.5 347.1 110 351 +1980 3 12 6 20 OSCAR 38.5 91.2 95 763 +1991 3 7 18 1 VALERIE 68.8 310.4 19 271 +1970 5 28 12 27 ALBERTO 20.7 298.3 107 525 +1983 11 5 6 10 JOYCE 63.4 315.3 161 122 +1951 8 18 0 9 BERYL 45.6 127.5 146 529 +1978 8 5 0 2 ALBERTO 51.0 346.2 156 203 +1991 10 10 18 20 DEBBY 11.1 9.5 94 809 +1957 9 25 0 20 JOYCE 67.3 255.6 71 406 +1983 12 2 0 22 LESLIE 27.0 75.9 138 606 +1957 8 24 6 14 DEBBY 17.5 321.2 139 616 +1950 10 10 18 7 JOYCE 9.2 155.9 57 872 +1973 6 12 0 15 DEBBY 31.1 252.9 32 174 +1966 8 14 18 7 NADINE 28.9 309.6 125 328 +1992 5 21 18 16 MICHAEL 26.9 144.0 157 561 +1959 12 28 6 2 VALERIE 64.2 36.1 158 457 +1975 11 6 12 28 JOYCE 39.6 266.6 121 572 +1999 8 9 18 8 JOYCE 12.1 354.6 75 21 +1973 2 21 6 14 CHRIS 63.4 182.9 74 785 +2003 8 26 0 7 BERYL 22.2 22.9 154 31 +1974 3 8 6 26 HELENE 18.6 342.1 73 819 +1992 9 27 0 1 DEBBY 20.0 156.7 149 209 +1993 12 21 6 13 DEBBY 12.1 118.5 23 225 +1984 6 7 18 17 HELENE 24.4 188.8 131 616 +1960 6 25 12 6 GORDON 28.4 189.8 22 603 +2003 8 13 6 4 ISAAC 38.0 327.6 72 197 +1961 10 13 6 7 DEBBY 60.3 161.4 65 598 +2003 7 21 0 22 ISAAC 26.6 351.4 23 544 +1976 7 9 0 11 JOYCE 29.2 119.3 18 743 +1960 10 25 18 20 HELENE 69.5 144.8 53 388 +1986 4 3 12 15 LESLIE 62.1 102.9 112 874 +1962 4 6 18 6 VALERIE 8.9 341.6 148 470 +2001 9 3 6 27 DEBBY 18.1 305.5 109 455 +1962 8 22 12 27 FLORENCE 22.8 337.6 29 306 +1978 4 6 12 11 CHRIS 32.0 218.4 84 655 +1977 5 15 6 13 LESLIE 9.7 158.5 106 73 +1971 5 15 12 15 OSCAR 17.2 213.5 102 879 +1957 10 25 12 12 ISAAC 50.1 55.9 49 703 +1993 7 10 6 13 KIRK 51.4 295.5 41 516 +1989 4 19 0 22 GORDON 43.0 283.4 81 243 +1958 4 20 12 12 KIRK 62.7 267.4 158 355 +1950 5 1 0 17 JOYCE 16.8 5.3 156 536 +1964 7 1 0 15 DEBBY 27.4 13.5 36 84 +1995 9 11 12 19 ISAAC 32.2 161.2 60 505 +1968 7 25 0 2 MICHAEL 46.1 268.4 68 484 +1983 7 19 0 13 MICHAEL 69.7 244.1 96 512 +1990 8 19 0 10 OSCAR 46.3 110.7 112 607 +1997 1 6 0 6 CHRIS 10.0 142.2 131 494 +1966 10 19 12 9 MICHAEL 34.0 172.9 113 427 +1956 7 11 18 6 TONY 18.5 349.2 124 802 +1952 8 7 12 7 KIRK 40.5 86.9 130 420 +1978 7 13 0 12 BERYL 39.7 187.6 96 852 +1984 6 28 0 6 FLORENCE 19.3 180.1 10 420 +1958 4 3 12 3 HELENE 39.5 36.4 60 299 +1989 5 4 0 23 ALBERTO 27.7 90.4 112 207 +1964 12 21 0 28 ERNESTO 56.8 203.7 135 809 +1982 8 18 6 8 TONY 19.5 176.9 75 736 +1980 1 15 18 25 NADINE 20.1 11.9 12 54 +1983 4 17 12 3 KIRK 62.5 68.6 11 215 +1966 5 8 18 20 NADINE 21.5 188.4 23 554 +1960 8 6 0 19 BERYL 43.6 213.2 100 549 +1997 3 13 6 15 KIRK 64.0 205.8 106 619 +1952 12 8 0 10 JOYCE 35.5 284.6 163 409 +2000 7 19 18 15 GORDON 39.8 328.4 153 483 +1976 5 16 0 28 ISAAC 50.8 184.9 128 435 +1996 10 19 0 6 JOYCE 37.5 350.3 79 878 +1993 10 6 12 7 KIRK 22.0 169.0 133 304 +1971 11 14 6 25 BERYL 36.4 215.0 132 173 +1961 1 7 6 1 LESLIE 49.7 164.4 140 519 +1998 3 19 12 16 ALBERTO 49.6 343.4 71 199 +1964 12 19 18 27 GORDON 44.6 97.1 101 826 +1981 6 5 18 27 ISAAC 66.9 108.1 17 647 +1954 12 26 0 24 RAFAEL 68.6 31.4 91 714 +1977 3 26 0 27 WILLIAM 55.4 9.1 94 189 +1982 2 6 0 26 TONY 42.0 144.5 151 365 +1974 7 4 18 16 ERNESTO 11.1 59.8 109 81 +1976 5 10 6 27 GORDON 67.0 204.6 50 772 +2003 10 23 0 22 CHRIS 64.7 131.4 131 166 +1985 11 21 18 6 CHRIS 13.1 38.7 139 537 +1977 3 24 6 15 FLORENCE 64.1 163.7 98 805 +1979 10 23 0 26 HELENE 49.8 302.4 132 475 +1975 10 11 0 20 FLORENCE 62.8 262.0 106 591 +1961 2 12 12 22 KIRK 21.6 204.0 60 345 +2003 2 11 18 17 HELENE 51.7 219.5 163 332 +2002 11 8 0 24 DEBBY 45.0 42.0 102 590 +1972 11 5 6 21 ISAAC 22.2 200.3 149 52 +1989 3 18 6 4 OSCAR 31.0 151.1 68 716 +1968 4 27 0 26 TONY 28.9 284.3 130 24 +1960 12 6 12 17 RAFAEL 24.3 109.3 61 655 +1956 1 27 0 2 JOYCE 67.0 250.9 146 778 +1963 5 18 0 24 OSCAR 21.9 118.3 125 784 +1965 6 2 6 17 SANDY 35.9 7.6 116 416 +1952 4 6 0 15 VALERIE 11.6 1.0 26 773 +1956 7 11 6 12 VALERIE 46.2 68.9 22 491 +1976 4 15 6 2 WILLIAM 58.3 258.8 61 818 +1950 9 9 18 25 RAFAEL 68.0 66.7 123 879 +1963 5 13 18 16 BERYL 48.7 152.5 59 275 +1950 4 14 6 22 WILLIAM 26.1 13.4 52 655 +1996 6 21 18 9 WILLIAM 54.5 111.7 150 275 +2002 7 5 0 27 KIRK 33.9 162.2 69 52 +1959 9 19 18 10 MICHAEL 67.8 176.1 63 677 +1988 3 19 12 3 TONY 7.1 332.1 46 374 +1962 10 6 18 19 TONY 37.2 308.5 34 279 +1958 5 8 0 9 LESLIE 15.9 33.3 115 35 +1973 10 24 6 20 LESLIE 19.9 171.0 96 703 +1989 6 10 0 27 MICHAEL 34.6 105.6 24 211 +1973 9 11 6 21 VALERIE 20.7 350.7 152 215 +1965 11 15 12 12 ALBERTO 58.5 318.4 56 205 +1994 5 4 6 11 TONY 52.7 211.1 11 159 +1994 1 21 6 25 KIRK 33.2 258.8 118 217 +1991 1 27 12 8 KIRK 64.6 177.6 35 117 +1976 1 20 0 28 OSCAR 58.1 318.3 54 704 +1975 11 26 6 14 WILLIAM 23.4 163.3 43 408 +1961 8 3 12 3 PATTY 51.5 331.5 116 560 +1976 9 9 12 17 HELENE 26.9 53.6 57 250 +1959 4 17 12 5 ALBERTO 46.8 133.9 10 514 +1970 2 23 12 17 RAFAEL 8.8 326.7 121 710 +1972 9 7 12 18 ERNESTO 66.2 332.6 157 290 +1960 11 11 0 4 WILLIAM 10.3 165.6 159 282 +1974 10 22 6 9 NADINE 31.3 209.3 24 448 +1983 2 7 18 27 ALBERTO 63.7 88.9 136 331 +1950 3 25 6 28 CHRIS 56.8 68.0 64 785 +1992 8 16 12 18 HELENE 45.7 111.0 20 331 +1958 5 16 12 17 NADINE 61.8 349.0 72 0 +1958 10 23 6 2 JOYCE 12.1 129.4 145 247 +1980 5 6 12 13 ERNESTO 61.8 61.1 74 127 +1996 8 8 6 14 BERYL 65.0 296.1 16 147 +1959 3 25 18 28 VALERIE 43.4 71.9 147 331 +1984 5 19 18 21 ERNESTO 69.1 238.7 77 647 +2003 3 14 6 11 HELENE 69.2 34.7 162 626 +1996 7 15 12 27 LESLIE 39.2 298.0 32 481 +1999 4 26 0 10 OSCAR 48.2 13.6 130 363 +1984 11 21 18 27 VALERIE 10.5 286.9 77 261 +1998 2 4 12 9 DEBBY 62.9 25.2 90 257 +2002 12 10 0 24 KIRK 15.7 151.8 10 747 +1968 2 18 12 2 ALBERTO 50.4 241.5 54 58 +1971 1 18 12 2 LESLIE 53.7 133.2 44 119 +1958 2 4 0 26 ERNESTO 30.4 231.0 132 778 +1997 8 22 18 2 GORDON 45.0 57.1 114 322 +1957 6 12 12 22 OSCAR 10.3 170.0 155 242 +2000 10 24 6 23 GORDON 47.5 101.3 33 315 +1988 9 4 18 23 ERNESTO 16.9 80.2 157 655 +1962 8 5 12 5 BERYL 59.3 281.9 155 602 +1965 9 15 18 18 KIRK 35.5 99.5 114 215 +1967 9 28 0 6 KIRK 32.0 313.8 32 473 +1983 9 6 6 4 GORDON 51.0 185.6 71 188 +1979 7 24 18 24 DEBBY 22.4 234.4 161 707 +1988 1 19 6 13 PATTY 32.7 203.7 151 254 +1956 8 24 12 26 PATTY 56.7 327.8 76 400 +1980 6 22 0 4 DEBBY 66.6 158.0 88 519 +1976 9 11 18 25 NADINE 19.5 101.8 57 138 +1955 8 23 12 9 RAFAEL 20.7 128.2 118 758 +1952 8 10 12 6 KIRK 59.2 18.6 132 207 +1969 8 19 18 26 WILLIAM 11.0 9.2 135 252 +1983 4 20 18 5 HELENE 17.0 104.4 81 783 +1961 11 6 18 11 BERYL 51.0 228.3 76 291 +1971 1 2 0 28 FLORENCE 28.8 1.2 63 521 +1962 1 17 0 19 ERNESTO 52.3 54.6 87 274 +2002 6 2 12 27 ALBERTO 52.0 136.1 152 623 +1980 9 16 18 13 BERYL 68.2 314.5 87 769 +1962 2 1 12 3 ALBERTO 69.3 253.0 104 315 +1964 8 8 12 7 BERYL 61.3 69.8 89 819 +1954 4 6 12 1 NADINE 47.9 171.5 76 643 +1963 11 3 0 13 DEBBY 53.1 346.8 95 816 +1957 2 21 6 27 MICHAEL 11.4 293.9 49 263 +1958 4 27 12 19 FLORENCE 23.0 28.0 115 106 +1954 6 17 6 28 CHRIS 15.4 101.9 76 696 +1971 3 15 0 13 ISAAC 23.4 187.6 54 779 +1966 11 14 0 7 FLORENCE 40.6 342.0 15 131 +1986 1 25 0 15 KIRK 13.0 182.7 40 465 +1968 9 28 6 23 PATTY 41.9 250.4 40 220 +1997 1 19 18 27 FLORENCE 62.8 130.2 87 654 +2004 2 27 6 24 ERNESTO 16.0 336.7 61 288 +1954 1 10 12 19 TONY 8.2 67.2 74 69 +1961 5 19 12 23 HELENE 22.0 216.6 140 675 +1983 11 15 12 28 WILLIAM 13.7 85.6 128 65 +1990 2 28 12 15 CHRIS 9.5 150.1 73 695 +1990 11 7 12 5 JOYCE 17.5 66.3 13 159 +1975 11 11 12 24 WILLIAM 39.2 261.2 46 399 +1971 2 28 18 24 CHRIS 69.6 204.6 72 207 +2002 11 17 12 15 FLORENCE 35.0 264.8 45 137 +1970 11 24 6 21 VALERIE 21.4 59.8 60 877 +1986 5 19 18 17 CHRIS 24.2 198.3 159 319 +1989 6 21 18 13 KIRK 10.2 176.3 50 63 +1985 12 15 12 20 JOYCE 8.4 132.8 125 436 +1962 5 23 0 23 RAFAEL 68.2 199.5 156 243 +1968 5 13 12 1 WILLIAM 27.5 145.3 148 372 +1973 10 8 18 12 SANDY 26.2 239.0 163 149 +1967 4 22 12 16 PATTY 39.5 30.5 148 836 +1998 4 22 6 15 LESLIE 49.9 189.8 155 840 +2001 2 16 6 7 MICHAEL 29.0 325.3 62 636 +1984 7 8 0 5 GORDON 64.1 170.4 18 86 +1969 7 13 12 16 LESLIE 54.1 83.8 87 301 +1968 9 24 6 12 KIRK 11.5 268.3 156 671 +1993 12 28 12 18 ALBERTO 60.9 72.0 65 862 +1975 3 1 12 8 NADINE 23.5 133.9 96 746 +1950 10 2 6 15 FLORENCE 10.2 84.8 111 865 +1985 7 4 0 24 NADINE 20.8 241.1 149 412 +1964 5 3 0 16 OSCAR 21.6 99.7 78 333 +1969 1 26 6 13 BERYL 45.2 63.9 57 325 +1992 9 16 6 28 TONY 12.4 46.5 150 87 +1963 9 10 0 2 HELENE 63.0 142.7 108 640 +1973 6 10 18 19 GORDON 59.7 123.9 160 731 +1992 9 13 18 12 TONY 66.6 210.9 90 687 +1969 8 22 0 6 RAFAEL 55.0 221.2 31 543 +1967 7 10 6 6 KIRK 29.5 180.0 145 851 +1973 4 13 18 27 SANDY 32.7 33.1 100 622 +1982 9 22 0 27 ALBERTO 27.7 125.3 128 491 +1973 2 9 0 22 WILLIAM 30.6 169.4 85 598 +1968 1 13 18 9 FLORENCE 43.9 31.8 28 846 +2001 4 27 0 13 OSCAR 32.0 118.3 84 629 +1995 6 4 18 2 LESLIE 52.8 50.4 68 814 +1992 10 6 6 6 TONY 56.4 169.4 52 385 +1991 5 26 0 16 OSCAR 48.1 57.9 64 633 +1978 1 22 0 19 TONY 34.5 348.8 78 847 +1984 1 8 12 26 HELENE 16.9 187.6 105 523 +1997 3 3 12 7 FLORENCE 68.1 78.2 56 4 +1986 3 21 18 11 VALERIE 13.9 59.9 135 710 +1961 1 12 0 25 TONY 26.7 228.1 123 177 +1998 6 18 6 11 DEBBY 57.3 214.1 110 722 +1954 9 18 6 10 ALBERTO 32.3 254.7 141 759 +1985 5 15 12 19 NADINE 14.2 294.3 45 548 +1992 8 8 18 10 NADINE 48.2 201.4 148 2 +1956 2 4 0 1 ERNESTO 45.2 349.3 99 111 +1957 6 13 0 18 ALBERTO 34.3 26.7 31 667 +1951 9 17 6 28 FLORENCE 23.1 338.5 46 56 +2001 5 17 6 10 WILLIAM 35.0 327.9 83 517 +1978 8 10 6 15 DEBBY 67.7 116.7 63 820 +1970 7 10 0 18 SANDY 62.8 104.6 149 415 +1968 11 12 18 24 NADINE 32.3 114.2 24 260 +1984 2 4 6 11 CHRIS 25.0 9.3 82 278 +1987 12 7 12 9 ERNESTO 23.0 296.6 107 645 +1999 11 12 6 20 WILLIAM 31.0 331.0 55 899 +1952 4 2 0 15 BERYL 13.5 45.1 31 295 +1966 4 19 18 21 RAFAEL 27.3 329.6 139 739 +1993 12 4 18 9 BERYL 60.3 21.3 139 863 +1968 7 6 18 16 HELENE 21.6 89.5 23 93 +1973 12 10 6 4 SANDY 51.8 171.9 75 217 +1961 5 1 12 5 FLORENCE 40.4 135.2 140 298 +1991 6 4 12 2 VALERIE 43.4 309.0 23 897 +1967 9 4 0 28 VALERIE 30.2 94.2 91 92 +1980 12 1 6 27 BERYL 23.2 48.1 85 342 +1971 2 26 18 15 KIRK 52.5 305.6 58 484 +1988 7 14 0 9 WILLIAM 25.8 141.8 45 317 +1989 7 9 6 14 WILLIAM 38.0 43.8 49 861 +1960 6 20 12 21 KIRK 38.0 241.7 155 255 +1986 1 18 12 26 ISAAC 30.6 125.0 50 863 +1963 2 26 18 18 VALERIE 47.7 289.4 109 391 +1980 12 24 18 7 SANDY 37.4 218.1 51 611 +1984 3 10 12 18 CHRIS 39.4 277.9 32 442 +1952 11 6 6 7 FLORENCE 15.6 254.5 152 339 +1961 10 25 0 17 CHRIS 8.6 154.8 71 80 +1959 12 23 6 19 SANDY 10.9 22.6 100 588 +1981 6 20 18 14 ALBERTO 53.8 111.4 87 407 +1965 8 24 6 1 JOYCE 25.9 111.3 160 619 +1991 11 4 0 12 BERYL 46.0 40.6 31 887 +1966 4 27 6 10 PATTY 20.3 187.7 95 121 +2000 11 7 18 10 TONY 28.1 237.1 91 31 +2003 10 22 0 14 HELENE 35.3 285.5 94 262 +1975 11 11 0 8 HELENE 20.2 106.0 131 330 +1955 3 7 0 17 ALBERTO 57.5 15.9 103 784 +2004 4 25 18 13 ALBERTO 39.2 214.7 103 379 +2000 2 1 6 6 MICHAEL 26.6 191.7 128 563 +1962 11 27 18 23 JOYCE 48.8 331.5 75 457 +1957 7 26 12 4 FLORENCE 21.7 91.8 103 122 +1996 5 9 12 27 CHRIS 54.4 7.0 159 307 +1965 10 17 18 26 SANDY 57.5 37.6 114 230 +1950 12 2 18 23 OSCAR 51.1 10.6 48 601 +1985 9 16 12 17 OSCAR 51.3 240.7 79 359 +1955 7 23 18 28 BERYL 52.6 19.9 138 113 +1979 4 19 18 22 WILLIAM 40.3 143.3 158 130 +1954 4 17 18 15 GORDON 16.0 68.7 139 739 +1981 11 14 12 22 ISAAC 19.6 137.2 95 662 +1997 11 10 0 11 VALERIE 44.9 38.1 152 512 +1976 9 3 0 21 HELENE 36.5 298.4 44 53 +1959 2 16 0 4 DEBBY 53.5 287.9 131 853 +1971 8 5 6 27 OSCAR 49.9 324.2 113 274 +1970 8 2 18 25 MICHAEL 31.5 313.5 98 552 +2001 6 22 0 14 SANDY 12.9 340.8 45 356 +1951 9 28 6 1 MICHAEL 43.4 341.2 163 885 +1983 11 9 6 11 MICHAEL 45.7 244.7 46 722 +1988 5 7 0 18 ISAAC 51.6 173.0 21 576 +1997 1 8 12 9 SANDY 41.3 254.6 33 136 +1958 7 12 18 14 CHRIS 14.9 8.1 160 611 +1973 4 4 0 3 SANDY 47.6 102.3 158 253 +1996 3 10 18 6 JOYCE 38.2 52.0 53 858 +2000 5 22 0 24 ALBERTO 24.9 356.7 62 189 +2000 6 10 0 26 RAFAEL 29.0 19.8 106 27 +1983 5 28 18 8 LESLIE 39.9 240.6 101 557 +1980 1 6 0 24 ISAAC 34.9 104.9 79 887 +1972 12 1 18 7 DEBBY 67.8 199.8 131 596 +1965 9 21 6 19 VALERIE 11.1 141.8 112 0 +1987 11 23 18 6 HELENE 38.6 280.1 142 666 +1982 2 15 0 3 WILLIAM 70.0 20.4 141 315 +1982 11 20 18 7 LESLIE 12.9 265.6 15 236 +1965 5 8 18 24 SANDY 22.9 274.6 54 237 +1971 12 12 0 13 WILLIAM 56.5 99.2 13 651 +1974 1 24 12 7 WILLIAM 58.4 164.4 91 341 +1987 10 12 6 5 BERYL 55.5 142.3 138 662 +1963 1 6 6 24 BERYL 57.3 89.2 129 97 +1952 5 18 18 6 VALERIE 55.2 342.5 52 378 +1984 9 24 0 23 RAFAEL 42.7 293.0 49 184 +1994 8 4 6 28 MICHAEL 55.8 2.8 162 750 +1993 12 15 12 7 CHRIS 63.6 33.9 88 559 +1999 12 18 0 11 BERYL 59.3 147.5 147 166 +1990 12 15 0 16 ERNESTO 28.5 26.7 153 199 +1999 8 8 12 24 ALBERTO 23.9 101.8 74 777 +1978 5 7 12 20 CHRIS 66.9 21.3 16 470 +1978 3 14 6 12 BERYL 26.5 326.8 152 85 +1970 2 13 12 24 ISAAC 43.1 134.3 93 851 +1997 1 20 0 24 FLORENCE 40.2 345.8 149 481 +1981 2 27 12 9 PATTY 65.2 176.1 121 414 +1991 7 21 0 9 DEBBY 17.5 128.7 107 828 +1973 6 17 18 18 ALBERTO 20.5 240.7 126 610 +1969 11 27 12 23 ISAAC 50.3 358.0 127 584 +1978 6 3 0 17 KIRK 60.2 285.1 41 754 +1982 5 4 18 11 RAFAEL 31.6 3.1 164 789 +1966 1 8 6 9 LESLIE 14.5 195.3 92 35 +1993 2 5 6 22 HELENE 37.3 39.4 63 668 +1964 5 23 18 14 ISAAC 27.7 124.4 86 386 +1968 9 23 6 24 ISAAC 38.9 155.2 87 185 +1960 8 9 18 23 WILLIAM 43.3 275.9 151 312 +1954 7 15 6 12 PATTY 53.9 284.8 43 194 +1952 3 18 18 27 RAFAEL 66.1 26.2 60 258 +1974 3 25 6 4 GORDON 41.5 320.8 107 651 +1970 3 9 0 8 BERYL 60.3 112.0 61 407 +1958 2 8 6 10 CHRIS 47.9 292.7 63 483 +1955 8 18 12 20 PATTY 49.3 77.0 92 869 +1954 5 4 6 24 WILLIAM 57.2 336.4 131 20 +1996 1 13 6 9 MICHAEL 48.0 188.6 47 63 +1950 12 13 18 26 DEBBY 60.2 276.6 75 261 +1955 1 2 18 13 JOYCE 22.9 318.0 103 899 +1964 12 15 6 26 KIRK 62.9 346.2 44 611 +2002 3 27 6 7 ALBERTO 47.3 287.0 142 554 +1984 11 9 12 27 FLORENCE 57.7 138.0 138 35 +2003 6 19 0 8 FLORENCE 8.1 242.6 29 805 +1980 8 25 12 4 LESLIE 40.1 102.7 68 552 +1979 7 24 12 10 MICHAEL 30.1 265.9 119 760 +1956 5 3 12 27 BERYL 55.1 93.9 125 377 +1967 11 4 6 24 MICHAEL 30.4 200.4 41 771 +1968 4 12 6 16 FLORENCE 15.1 252.2 92 407 +1982 2 2 18 10 KIRK 36.7 258.1 157 39 +1991 5 11 12 9 PATTY 70.0 351.5 91 51 +1955 11 11 6 27 KIRK 65.3 280.6 146 131 +1984 9 1 6 25 NADINE 67.0 97.3 96 143 +1956 8 13 12 21 HELENE 44.9 268.4 20 322 +1974 8 19 12 2 CHRIS 52.6 283.3 152 789 +1963 4 22 0 11 OSCAR 36.5 91.6 13 423 +2004 6 10 6 10 ERNESTO 58.1 303.9 34 757 +1994 3 28 0 10 WILLIAM 62.9 27.1 45 528 +1953 8 14 12 12 RAFAEL 52.9 76.0 71 632 +1986 10 19 12 28 OSCAR 57.3 309.0 79 126 +1999 9 14 6 9 DEBBY 43.6 239.6 115 534 +1965 11 3 18 6 BERYL 41.5 308.9 51 393 +1950 1 24 18 15 TONY 43.9 114.8 75 534 +1970 10 10 6 13 FLORENCE 16.0 2.5 138 345 +1995 1 26 0 28 VALERIE 35.9 191.7 41 481 +2001 6 17 0 28 RAFAEL 37.9 320.0 61 530 +1951 8 20 6 2 MICHAEL 54.2 234.3 59 379 +1951 2 20 6 19 ALBERTO 46.5 338.9 78 163 +1975 11 26 0 14 OSCAR 35.2 102.2 153 45 +1969 11 13 6 19 PATTY 66.1 24.6 151 8 +1952 10 1 12 21 RAFAEL 62.1 126.3 45 519 +1967 7 6 0 25 LESLIE 27.5 317.1 139 309 +1953 11 27 0 14 ERNESTO 9.2 4.3 36 751 +1963 1 27 12 13 ALBERTO 31.0 287.8 76 617 +1959 11 19 12 1 VALERIE 20.2 330.7 41 859 +1991 1 28 6 5 RAFAEL 58.2 268.3 38 498 +1961 10 16 12 28 ERNESTO 10.4 334.5 24 411 +1973 5 11 18 7 WILLIAM 51.2 81.3 10 326 +1987 8 28 18 7 LESLIE 20.7 175.1 144 695 +1967 6 22 18 4 RAFAEL 30.5 38.1 83 404 +1976 4 26 18 22 SANDY 54.6 234.4 91 240 +1998 3 21 12 8 VALERIE 68.1 111.5 131 646 +1995 1 4 12 1 RAFAEL 41.4 48.2 94 519 +1970 3 18 6 11 FLORENCE 56.1 157.0 70 196 +1954 4 4 18 7 WILLIAM 50.8 90.9 92 747 +1973 8 18 12 4 WILLIAM 25.2 134.8 130 778 +1990 6 23 12 12 ISAAC 40.5 122.9 97 670 +1976 6 2 12 27 BERYL 67.7 231.1 18 252 +1974 6 19 0 5 MICHAEL 68.8 105.6 121 567 +1980 8 27 12 2 HELENE 62.1 310.5 12 844 +1953 10 3 6 16 SANDY 13.8 90.1 90 824 +1955 4 19 12 13 OSCAR 63.6 336.4 26 795 +1987 10 25 18 12 PATTY 22.4 218.7 151 896 +1958 8 9 6 12 RAFAEL 58.8 166.0 99 443 +1995 6 22 6 21 SANDY 12.8 279.0 59 847 +1950 2 23 0 24 MICHAEL 19.4 346.2 31 226 +1959 4 17 0 12 DEBBY 43.7 165.3 63 413 +1984 12 4 12 28 KIRK 45.1 147.2 109 764 +1956 7 18 12 15 ISAAC 57.9 195.8 158 684 +1984 11 19 6 8 WILLIAM 65.7 59.0 61 23 +1974 3 23 12 3 WILLIAM 32.4 87.6 71 605 +1997 9 5 0 9 FLORENCE 58.6 168.5 14 269 +1953 8 5 6 2 ALBERTO 54.7 13.5 19 894 +1960 9 17 12 17 BERYL 27.8 330.4 77 156 +1986 8 25 6 15 OSCAR 56.2 158.8 125 689 +1960 9 5 18 19 CHRIS 46.6 87.6 161 53 +1952 12 20 6 4 SANDY 51.0 171.7 164 635 +1958 12 22 18 19 OSCAR 16.9 57.4 54 155 +1992 8 10 12 25 BERYL 42.8 219.6 45 2 +2000 6 18 12 11 OSCAR 20.6 114.6 60 806 +1981 5 9 0 26 HELENE 38.6 150.4 41 249 +1959 5 28 6 4 DEBBY 21.7 225.9 150 426 +1951 4 20 6 23 JOYCE 12.2 354.0 54 64 +1988 7 16 6 20 ERNESTO 11.9 98.5 157 124 +1959 2 25 18 2 WILLIAM 10.0 26.7 128 764 +1989 1 15 18 8 PATTY 39.9 232.8 119 425 +1960 1 26 18 19 TONY 25.7 2.4 115 757 +1998 12 5 6 16 HELENE 41.3 187.8 14 496 +1969 2 2 6 17 BERYL 66.3 19.9 51 745 +1983 1 20 18 13 ISAAC 13.4 106.3 17 687 +1988 2 23 18 17 OSCAR 28.7 252.2 16 342 +1975 5 5 18 21 HELENE 37.4 190.4 63 830 +1972 3 18 6 24 NADINE 63.1 153.0 109 866 +2003 9 15 6 9 SANDY 29.9 311.8 133 455 +1967 4 11 0 8 WILLIAM 67.8 191.4 76 10 +1982 3 13 12 18 NADINE 48.6 330.9 41 249 +1984 2 18 6 26 MICHAEL 31.2 89.2 84 711 +1974 4 16 12 20 TONY 7.8 271.3 57 876 +1976 6 17 12 28 BERYL 26.8 312.3 125 25 +1976 3 2 18 14 ERNESTO 9.5 328.3 132 539 +2002 5 27 12 10 ALBERTO 45.9 241.6 37 441 +1978 9 23 6 17 ERNESTO 41.2 0.3 54 404 +1962 3 18 0 21 LESLIE 14.4 253.7 98 190 +2003 4 22 18 26 HELENE 44.0 60.6 74 442 +1974 7 27 6 6 JOYCE 22.1 246.1 29 288 +1972 11 28 18 21 RAFAEL 34.0 69.0 49 332 +2003 3 4 0 5 DEBBY 15.4 215.0 99 630 +1982 6 9 18 12 JOYCE 20.0 88.6 156 580 +1979 12 7 6 19 FLORENCE 12.4 308.2 125 134 +1994 5 14 0 2 HELENE 64.8 32.4 10 725 +1983 9 16 6 11 RAFAEL 64.1 211.0 41 413 +1989 9 27 12 18 ISAAC 69.2 220.0 92 560 +1973 4 6 12 26 ISAAC 20.8 314.2 61 420 +2000 1 10 6 1 RAFAEL 19.6 50.7 147 726 +1990 3 4 18 25 GORDON 69.9 151.1 59 600 +1956 6 26 6 17 ERNESTO 35.4 342.0 162 184 +1964 12 13 18 17 FLORENCE 27.9 200.4 71 501 +1990 3 18 18 28 JOYCE 64.3 188.6 43 596 +1998 2 4 6 5 ERNESTO 35.9 174.1 124 642 +1975 1 19 18 25 PATTY 40.2 121.7 115 719 +1961 5 18 6 18 WILLIAM 7.1 116.4 79 550 +1990 5 26 6 22 HELENE 50.2 239.8 147 324 +1953 5 10 12 6 ERNESTO 9.8 95.4 85 402 +1958 5 5 6 6 KIRK 20.7 314.0 30 512 +1994 10 5 18 4 MICHAEL 49.0 262.7 22 529 +1972 5 4 18 12 ISAAC 43.6 199.5 114 292 +1995 8 5 6 9 CHRIS 60.4 216.8 141 795 +1953 8 21 12 16 FLORENCE 57.9 76.6 65 759 +1975 12 11 6 18 ISAAC 47.9 235.7 102 625 +2001 4 6 0 6 ISAAC 23.6 328.0 119 135 +1951 11 2 0 3 FLORENCE 49.0 47.3 56 714 +1995 3 7 6 12 GORDON 23.7 312.4 72 479 +1973 3 20 6 23 CHRIS 27.8 348.4 37 198 +1973 2 11 0 3 CHRIS 52.0 215.5 47 701 +1951 10 1 12 14 HELENE 14.4 214.8 42 508 +1999 9 7 18 2 SANDY 31.2 168.1 106 459 +1966 5 2 6 6 BERYL 51.1 159.0 164 847 +1982 2 6 6 3 ALBERTO 17.9 137.1 44 278 +1978 7 8 0 4 SANDY 67.2 329.1 27 203 +1968 4 17 6 27 ALBERTO 22.4 233.7 19 775 +1991 5 17 0 1 LESLIE 22.0 279.3 57 354 +1991 12 6 0 12 PATTY 28.3 262.1 16 42 +1964 6 8 6 16 ALBERTO 36.5 40.7 145 407 +1956 1 4 18 19 SANDY 12.5 40.7 100 241 +1995 6 25 0 14 CHRIS 57.2 225.8 11 44 +1997 7 23 18 15 GORDON 27.3 123.4 77 591 +1973 1 18 12 27 DEBBY 24.8 20.4 40 430 +1983 11 12 6 21 SANDY 33.9 94.8 80 387 +1973 7 15 6 28 VALERIE 58.1 276.6 73 79 +1968 1 22 6 28 ERNESTO 60.1 342.5 72 351 +1961 10 9 6 2 PATTY 49.0 290.3 22 337 +2003 9 21 18 23 ALBERTO 16.2 313.4 30 328 +1960 1 3 18 16 OSCAR 33.3 333.9 36 388 +1987 3 22 0 17 ISAAC 46.2 275.0 18 686 +1995 6 2 18 2 KIRK 7.9 222.5 142 813 +1994 4 6 12 14 MICHAEL 54.5 282.9 10 337 +1997 5 1 6 18 ALBERTO 37.6 357.4 114 594 +1959 2 13 6 11 TONY 57.1 336.9 118 129 +2001 8 13 12 4 DEBBY 11.0 3.2 120 416 +1963 9 28 0 18 HELENE 13.5 180.2 103 897 +1962 12 8 6 15 OSCAR 38.8 186.3 19 645 +1984 5 22 12 17 HELENE 32.9 239.2 141 646 +1978 6 7 12 9 ISAAC 12.4 340.3 140 444 +1971 5 13 0 4 CHRIS 13.8 230.5 34 58 +1966 7 18 6 21 CHRIS 12.0 157.9 47 358 +1962 6 20 0 16 SANDY 53.9 165.8 67 473 +1966 7 16 0 13 BERYL 23.4 29.9 154 518 +1977 7 27 6 5 FLORENCE 28.4 113.7 130 752 +1973 5 17 0 18 RAFAEL 28.0 115.2 53 171 +2002 11 21 6 3 SANDY 58.4 326.6 164 624 +1952 10 8 12 28 ISAAC 36.4 48.2 83 595 +1978 9 7 12 2 RAFAEL 42.8 131.6 73 171 +1967 9 5 0 6 KIRK 39.0 116.8 82 668 +1970 11 19 18 2 MICHAEL 61.8 344.1 59 123 +1959 2 8 0 8 TONY 22.9 235.7 94 87 +1997 4 10 18 24 DEBBY 37.6 246.8 48 877 +1992 7 7 6 4 ERNESTO 42.2 38.9 122 93 +1965 8 25 12 16 MICHAEL 37.0 246.0 59 37 +1970 6 11 6 16 MICHAEL 37.9 150.3 164 764 +1950 1 8 0 9 CHRIS 36.6 169.5 87 4 +1959 2 7 12 5 JOYCE 19.8 133.5 101 808 +1988 3 19 0 8 NADINE 12.8 323.5 18 199 +2002 7 26 18 16 VALERIE 7.6 114.2 20 555 +1978 6 13 18 28 LESLIE 18.0 105.9 90 316 +1958 9 10 18 5 RAFAEL 18.8 152.7 115 723 +1979 10 7 18 1 TONY 68.4 115.4 121 725 +1960 2 13 0 24 MICHAEL 9.2 47.9 109 765 +2001 7 24 6 11 NADINE 40.1 314.8 69 486 +1996 2 5 0 21 CHRIS 67.8 110.1 30 355 +1993 8 4 18 18 PATTY 18.6 329.9 99 236 +1999 12 8 12 3 GORDON 53.7 238.6 51 652 +1979 12 4 18 10 NADINE 41.9 66.0 93 171 +1971 1 14 12 20 CHRIS 28.5 288.6 125 382 +1962 2 21 0 19 KIRK 67.2 285.9 33 743 +1960 11 20 6 9 BERYL 19.0 340.3 131 214 +1964 3 26 12 9 HELENE 47.4 312.9 34 550 +1963 3 16 0 4 JOYCE 14.1 242.9 115 626 +2004 8 21 18 2 WILLIAM 51.2 344.6 138 195 +1981 8 21 12 21 WILLIAM 38.3 296.1 56 619 +1981 4 2 12 3 KIRK 66.1 213.9 71 161 +1972 9 2 18 8 ALBERTO 24.5 311.1 21 743 +1951 1 8 18 6 MICHAEL 22.6 221.0 16 772 +1963 12 28 18 21 BERYL 50.9 29.0 150 701 +1969 2 7 18 4 FLORENCE 48.8 318.6 77 207 +1984 6 17 18 17 RAFAEL 68.0 208.0 87 82 +1980 12 16 18 1 BERYL 11.1 58.3 144 247 +2002 4 3 12 6 FLORENCE 23.2 148.6 146 782 +1970 10 3 12 10 ISAAC 49.3 262.0 148 544 +1990 7 18 12 14 VALERIE 26.7 196.7 32 501 +1968 1 24 18 26 KIRK 23.3 238.5 160 639 +1967 1 18 12 13 BERYL 30.0 158.7 47 59 +1993 12 17 6 21 ERNESTO 48.5 152.0 59 132 +1967 4 22 18 4 NADINE 67.0 61.2 158 441 +1990 12 21 6 20 ALBERTO 58.0 153.3 158 245 +1963 12 8 12 13 LESLIE 32.7 143.1 107 302 +1966 8 25 6 20 KIRK 55.4 233.2 73 490 +1970 2 11 12 22 SANDY 21.8 4.2 44 370 +1968 7 4 12 26 HELENE 33.6 8.4 74 479 +1960 10 27 18 1 KIRK 68.0 262.5 44 665 +1953 4 3 0 15 OSCAR 39.0 204.4 76 353 +1959 5 12 12 5 OSCAR 64.7 228.0 11 98 +1972 3 20 18 22 PATTY 65.7 226.4 137 621 +1981 4 19 6 18 GORDON 21.1 332.4 38 642 +1972 9 16 12 1 ERNESTO 56.2 150.3 124 671 +1965 1 12 6 21 NADINE 66.2 259.5 57 492 +1966 7 28 6 21 KIRK 47.6 183.5 88 534 +1984 7 19 6 11 HELENE 13.2 126.5 101 174 +1965 10 8 18 11 JOYCE 20.5 252.4 163 352 +1989 10 21 6 5 NADINE 49.6 192.0 75 677 +1966 10 27 6 14 ERNESTO 53.8 206.9 118 612 +1967 8 14 6 6 CHRIS 19.1 130.8 22 873 +1973 3 9 18 13 PATTY 59.0 62.8 53 275 +1997 8 1 12 2 DEBBY 60.0 215.9 160 876 +1978 3 23 12 25 FLORENCE 54.6 19.0 15 155 +1963 8 19 18 11 NADINE 60.1 233.6 126 599 +1989 3 26 6 2 MICHAEL 62.0 107.7 10 279 +2001 2 16 0 14 LESLIE 34.3 234.6 24 146 +1997 8 21 12 22 TONY 66.8 90.6 76 383 +1982 2 27 18 18 PATTY 40.9 115.2 16 94 +1982 6 17 0 12 VALERIE 7.6 206.5 89 581 +1961 3 5 12 26 ERNESTO 15.9 219.5 127 122 +1989 8 1 6 22 TONY 52.2 314.7 46 733 +2001 8 6 0 19 RAFAEL 26.2 327.6 17 774 +1991 10 28 12 14 TONY 11.8 202.0 119 532 +1987 6 14 6 21 HELENE 47.2 106.5 52 544 +1963 6 3 18 15 CHRIS 24.8 302.1 34 773 +1959 8 20 12 21 SANDY 36.7 101.9 158 415 +1990 3 9 6 18 BERYL 57.5 114.9 141 72 +1982 4 25 12 12 BERYL 26.3 217.5 133 257 +1966 9 4 18 2 RAFAEL 29.7 127.4 46 894 +2002 3 19 6 15 SANDY 49.5 322.2 98 279 +1976 4 11 6 11 VALERIE 13.0 14.9 91 745 +2003 10 14 6 25 BERYL 42.5 251.0 151 3 +2003 12 25 12 2 PATTY 31.1 195.4 34 358 +1960 5 10 6 19 TONY 21.5 161.5 101 93 +1953 5 6 18 15 WILLIAM 24.4 184.1 31 144 +1960 2 22 18 2 ALBERTO 19.2 260.9 22 630 +1964 6 14 12 26 ERNESTO 60.8 217.7 86 687 +1970 3 20 18 15 ISAAC 62.0 329.3 160 581 +1961 10 24 6 28 DEBBY 13.5 125.8 139 569 +2001 12 10 12 2 BERYL 23.1 157.6 160 245 +1980 8 27 18 5 RAFAEL 20.3 118.9 22 272 +1952 2 18 0 18 NADINE 32.9 108.1 117 721 +1963 4 7 12 21 WILLIAM 50.2 130.7 11 314 +1975 11 8 6 18 HELENE 9.5 79.6 89 231 +1963 5 3 12 4 WILLIAM 27.2 26.9 64 454 +1986 8 11 18 21 NADINE 23.6 313.6 31 408 +1983 4 12 18 6 VALERIE 27.7 340.8 79 749 +1979 10 12 12 24 SANDY 67.8 354.6 12 35 +1955 7 1 12 12 OSCAR 14.5 195.6 29 178 +1961 10 18 12 14 CHRIS 41.9 254.0 133 668 +1961 12 2 6 15 BERYL 24.5 269.4 81 506 +1974 6 19 18 28 WILLIAM 60.4 265.8 89 261 +1994 1 15 18 20 ERNESTO 37.4 116.8 153 170 +1992 11 12 0 15 OSCAR 47.7 6.1 54 455 +2000 5 6 12 4 OSCAR 67.9 126.5 25 485 +1989 8 11 18 5 FLORENCE 23.1 167.4 50 390 +1994 9 3 18 26 ISAAC 46.1 260.9 111 725 +1989 11 11 0 25 BERYL 42.7 156.2 71 34 +1964 8 8 0 17 MICHAEL 68.6 96.8 10 63 +1989 2 1 6 22 MICHAEL 58.3 119.6 92 673 +1988 1 13 6 5 ERNESTO 69.4 212.1 26 84 +1969 11 17 12 8 GORDON 36.0 96.0 57 454 +2001 10 2 12 27 JOYCE 33.7 61.3 89 325 +1995 3 27 12 26 VALERIE 57.1 9.5 58 568 +1966 3 26 12 1 MICHAEL 50.5 91.3 163 879 +2000 1 9 0 17 BERYL 39.1 289.0 120 127 +1958 11 10 18 9 DEBBY 55.7 136.1 85 753 +1968 9 27 6 2 LESLIE 50.1 211.0 88 870 +1975 10 5 12 18 ERNESTO 61.8 327.1 17 578 +1970 6 5 12 26 TONY 56.4 22.0 23 265 +1986 9 14 12 14 GORDON 15.5 335.8 89 724 +1989 11 20 12 22 CHRIS 30.1 166.4 20 351 +1979 5 10 0 10 ERNESTO 64.2 47.3 62 886 +1991 2 20 18 11 CHRIS 24.4 95.0 62 71 +1974 5 15 6 25 NADINE 14.8 203.3 119 812 +1969 7 19 0 10 KIRK 17.1 7.5 156 801 +1992 9 8 18 24 ALBERTO 40.5 102.3 152 349 +1970 6 6 12 28 MICHAEL 54.6 345.0 85 621 +1997 11 23 6 25 HELENE 52.5 236.8 101 583 +1994 7 14 12 15 OSCAR 58.2 348.5 66 94 +2004 7 2 18 19 RAFAEL 60.7 218.4 153 834 +1997 6 9 12 24 JOYCE 31.3 115.6 138 529 +1959 12 28 12 1 JOYCE 25.0 32.6 79 387 +1974 11 25 0 17 WILLIAM 14.8 197.6 116 734 +1969 10 20 12 13 CHRIS 64.9 320.7 33 170 +1996 8 6 12 13 MICHAEL 30.9 165.4 20 733 +1981 7 5 18 22 KIRK 57.9 326.0 65 746 +2002 12 7 12 19 KIRK 56.8 141.5 129 12 +1956 3 19 6 4 OSCAR 17.7 49.4 68 424 +1981 8 14 6 13 NADINE 52.3 325.0 106 261 +1978 3 21 6 4 OSCAR 61.6 228.3 52 388 +1974 4 16 0 6 ALBERTO 44.3 212.3 114 829 +1983 1 6 6 10 BERYL 28.3 216.5 111 234 +2000 2 6 6 13 ALBERTO 7.4 7.1 63 882 +1950 4 24 6 26 ISAAC 32.2 165.3 61 138 +1952 3 2 12 13 ISAAC 62.8 162.4 89 235 +1996 12 1 6 28 KIRK 41.0 179.8 37 90 +1973 9 18 0 21 WILLIAM 18.2 239.2 113 856 +1963 4 18 0 6 VALERIE 41.0 82.8 159 713 +1979 6 6 18 9 DEBBY 27.5 130.4 41 714 +1950 2 7 0 6 RAFAEL 23.1 230.7 14 153 +1973 11 19 12 2 FLORENCE 11.1 41.9 130 453 +1982 10 13 6 21 ERNESTO 56.9 311.0 93 334 +1955 11 26 18 1 RAFAEL 29.2 176.8 125 864 +1967 7 28 0 4 ERNESTO 64.6 209.4 82 48 +2003 8 18 12 7 WILLIAM 58.8 286.5 102 134 +1994 10 27 6 25 VALERIE 32.9 214.1 30 171 +2000 9 22 18 19 BERYL 47.8 160.7 72 178 +1975 4 20 12 2 SANDY 66.8 344.0 141 770 +1993 8 21 0 9 CHRIS 65.5 3.7 26 365 +2003 7 1 0 7 LESLIE 58.0 165.9 98 275 +1963 1 8 0 28 FLORENCE 33.6 139.9 56 489 +1956 7 2 6 19 ISAAC 19.2 312.2 40 789 +1989 2 8 12 24 LESLIE 22.0 16.7 152 67 +1954 10 15 18 21 CHRIS 17.4 111.8 11 269 +1962 10 17 6 8 SANDY 12.6 8.8 75 8 +1978 9 11 12 10 OSCAR 24.4 277.1 65 685 +1963 9 12 6 24 SANDY 44.4 277.6 89 619 +1973 11 20 12 9 BERYL 49.7 263.3 31 292 +1964 11 13 12 12 OSCAR 18.6 236.5 79 407 +1951 2 2 6 9 VALERIE 49.0 267.6 152 851 +1988 12 2 6 25 VALERIE 23.4 80.6 128 755 +1992 8 17 18 28 ISAAC 21.2 320.4 99 156 +2004 4 4 0 24 NADINE 67.2 13.3 29 95 +2001 10 17 6 16 ALBERTO 16.7 222.0 53 142 +1968 4 20 18 16 MICHAEL 31.5 335.2 124 528 +1959 12 18 12 20 RAFAEL 20.7 347.5 102 469 +1983 8 16 6 12 JOYCE 22.3 341.5 143 307 +1967 10 20 12 16 NADINE 62.7 71.4 97 103 +1999 2 25 12 20 HELENE 67.9 155.6 125 93 +1966 12 12 6 3 VALERIE 49.1 210.5 46 57 +1997 2 24 18 18 SANDY 57.0 27.2 109 348 +1964 7 15 12 1 WILLIAM 35.9 296.5 53 890 +1969 9 27 12 17 PATTY 42.1 260.5 67 419 +1980 11 21 18 2 DEBBY 12.0 118.9 93 883 +1997 1 22 18 20 DEBBY 69.5 180.5 121 426 +1996 1 12 18 12 DEBBY 68.1 269.3 49 306 +1973 10 17 6 8 WILLIAM 57.9 297.9 109 816 +1965 12 16 6 20 RAFAEL 67.0 108.7 65 12 +1959 6 27 18 28 TONY 31.6 185.1 88 884 +1977 4 4 0 13 VALERIE 48.1 209.3 48 886 +1951 1 23 18 7 CHRIS 69.8 149.0 91 18 +1985 5 17 12 23 CHRIS 61.2 171.0 78 774 +1960 2 23 6 21 KIRK 21.1 42.5 23 137 +1964 11 2 12 21 JOYCE 47.7 78.7 84 891 +1957 2 9 6 20 LESLIE 62.5 95.7 62 752 +1964 7 8 18 14 BERYL 16.3 31.4 49 801 +1966 1 23 6 5 BERYL 25.5 212.0 84 101 +1954 2 27 12 12 FLORENCE 28.2 195.6 39 272 +1958 8 22 6 1 ISAAC 42.5 267.6 152 861 +1971 8 22 0 21 MICHAEL 33.6 298.9 65 80 +1958 9 21 0 15 SANDY 21.9 302.2 50 286 +1993 11 16 0 20 ALBERTO 18.4 8.4 147 72 +1992 7 28 18 27 CHRIS 21.7 13.9 143 523 +1997 9 14 0 24 GORDON 32.7 96.7 141 387 +1956 2 8 18 17 DEBBY 17.4 340.8 11 796 +1986 2 16 6 13 JOYCE 51.7 321.3 74 122 +1977 5 1 18 6 PATTY 62.6 4.2 139 73 +1973 11 13 18 2 TONY 16.3 17.3 135 343 +1954 11 26 0 24 RAFAEL 36.0 341.9 41 100 +1989 12 16 12 14 FLORENCE 64.8 286.9 146 233 +1978 6 23 0 21 RAFAEL 66.7 64.9 139 729 +1980 12 25 12 26 ALBERTO 37.6 97.9 32 722 +1968 2 13 0 18 VALERIE 49.6 54.9 115 708 +1988 3 18 6 12 RAFAEL 67.3 249.1 38 870 +2000 4 19 6 10 BERYL 12.2 95.6 103 126 +1979 11 18 12 22 DEBBY 53.1 4.4 150 885 +1996 5 5 12 23 RAFAEL 10.3 150.8 161 170 +1965 3 16 0 15 DEBBY 65.3 137.8 129 33 +1974 1 14 12 24 MICHAEL 63.9 267.9 135 529 +1962 11 21 6 10 BERYL 18.1 326.2 48 316 +2001 7 13 18 22 OSCAR 35.0 44.9 113 413 +1960 7 10 18 3 RAFAEL 9.3 137.9 18 882 +1982 3 27 12 14 WILLIAM 42.9 305.2 68 293 +1959 8 19 12 6 PATTY 49.8 179.2 153 309 +1982 11 13 6 4 DEBBY 25.3 18.3 55 467 +1976 5 28 12 12 ALBERTO 45.6 100.8 42 663 +1969 10 22 12 27 ALBERTO 38.2 144.3 72 319 +1957 11 19 6 12 TONY 8.7 159.8 93 732 +1990 5 20 6 15 FLORENCE 43.3 229.3 164 65 +1978 7 19 18 2 TONY 20.9 229.4 88 566 +1972 2 26 12 10 WILLIAM 67.7 284.5 127 128 +1953 6 6 12 23 VALERIE 9.9 153.3 92 675 +2004 9 12 12 2 FLORENCE 32.4 286.9 159 831 +1984 12 4 12 2 BERYL 53.3 268.8 119 487 +1950 8 10 0 18 WILLIAM 18.6 169.0 113 211 +1961 7 11 12 21 NADINE 16.1 150.9 12 532 +1976 5 6 6 28 OSCAR 54.5 353.8 18 536 +1960 11 1 12 18 RAFAEL 57.7 309.4 15 37 +1962 3 9 6 8 PATTY 19.7 82.9 161 441 +1995 1 21 12 10 FLORENCE 39.5 247.3 82 191 +1954 5 5 12 9 WILLIAM 37.1 16.5 143 305 +1968 1 26 0 27 KIRK 69.1 274.1 30 151 +2000 10 9 12 9 OSCAR 67.0 14.8 61 328 +1985 5 15 0 5 FLORENCE 14.4 164.7 152 797 +1999 4 3 12 6 VALERIE 15.4 8.4 77 211 +1952 5 18 12 27 LESLIE 26.2 237.4 151 85 +1972 7 16 6 22 ISAAC 18.7 21.2 83 566 +1983 11 4 18 22 HELENE 13.6 127.1 53 117 +1970 12 14 12 20 MICHAEL 42.0 326.7 158 6 +1986 2 5 12 26 OSCAR 63.1 229.6 94 432 +1965 9 12 12 8 SANDY 44.6 121.5 51 470 +1990 12 9 18 7 LESLIE 58.4 114.7 109 289 +1988 6 20 6 18 ERNESTO 27.0 59.4 143 96 +1974 10 14 18 7 SANDY 64.6 319.6 29 869 +1953 3 14 12 16 CHRIS 44.7 122.3 115 5 +1976 8 13 6 20 CHRIS 50.0 69.4 137 65 +1994 1 15 6 19 GORDON 51.3 8.6 57 292 +1996 2 22 12 9 ISAAC 52.7 3.9 38 439 +1969 7 15 6 6 LESLIE 66.0 251.7 84 607 +1978 5 3 18 13 TONY 37.9 75.7 63 9 +1957 9 10 0 5 CHRIS 26.7 138.7 131 477 +2003 6 22 18 22 RAFAEL 40.7 222.1 45 894 +1950 3 9 12 11 RAFAEL 52.6 160.8 28 26 +1966 7 10 12 20 FLORENCE 25.6 213.0 24 47 +1964 9 24 6 2 ISAAC 26.8 334.3 76 263 +1955 8 27 18 28 LESLIE 42.9 73.9 132 326 +1952 4 17 6 21 WILLIAM 61.9 98.0 158 787 +1977 12 22 18 20 VALERIE 59.9 58.7 90 271 +1964 1 1 0 24 OSCAR 35.8 347.4 112 463 +1975 12 12 18 28 WILLIAM 37.5 19.5 132 186 +1961 8 23 0 28 HELENE 28.7 347.6 117 372 +1970 3 3 6 14 RAFAEL 7.6 329.7 69 316 +1983 12 11 12 7 OSCAR 51.2 216.2 106 137 +1961 6 26 6 1 TONY 37.3 268.9 78 197 +1980 10 13 12 14 LESLIE 33.5 135.1 130 891 +2002 9 7 18 15 KIRK 8.1 104.3 103 470 +2003 9 26 0 9 ERNESTO 69.2 219.1 136 105 +1966 12 15 0 22 SANDY 47.1 339.7 115 428 +1996 11 7 0 2 OSCAR 31.5 325.7 39 786 +2003 7 9 6 21 SANDY 54.9 222.4 26 481 +1954 7 24 18 17 DEBBY 58.2 126.0 153 676 +1981 1 6 0 17 CHRIS 67.2 56.7 126 876 +1967 11 16 12 4 OSCAR 21.7 223.6 54 613 +1961 5 28 12 26 GORDON 37.6 347.6 19 94 +1978 11 9 6 13 LESLIE 15.1 209.7 68 374 +1962 5 28 6 8 BERYL 65.0 55.5 46 205 +1988 7 14 18 10 ERNESTO 68.1 71.4 40 55 +1985 6 14 6 8 ALBERTO 32.7 121.5 96 214 +1954 11 13 6 12 TONY 48.9 264.5 18 647 +1980 11 2 18 13 ERNESTO 27.6 270.6 17 549 +1969 4 21 6 7 NADINE 37.2 170.7 52 245 +1997 1 19 6 8 DEBBY 58.2 76.5 158 524 +1971 7 20 0 3 KIRK 15.2 250.4 123 116 +1951 6 5 18 18 CHRIS 37.8 44.5 41 237 +1985 11 18 6 5 RAFAEL 55.5 33.6 105 109 +2004 12 14 12 25 BERYL 24.0 201.4 27 66 +1998 1 27 18 11 DEBBY 39.6 257.8 67 411 +2001 10 22 12 18 LESLIE 69.8 108.4 40 878 +1983 6 4 6 25 VALERIE 69.5 23.4 11 481 +1983 6 12 6 20 BERYL 68.2 258.9 55 105 +1957 12 11 12 8 PATTY 34.4 109.9 65 311 +1987 4 18 6 10 ERNESTO 11.8 206.5 23 213 +1952 5 16 0 26 JOYCE 25.8 38.4 90 106 +1960 4 2 6 7 RAFAEL 13.9 116.0 134 218 +1969 8 6 6 21 DEBBY 49.5 99.2 122 754 +1969 12 16 0 5 BERYL 63.8 245.4 54 135 +1997 8 16 18 18 GORDON 10.8 45.9 126 632 +1990 9 26 12 4 MICHAEL 45.3 110.3 38 162 +1975 1 9 0 21 ERNESTO 41.0 300.0 61 23 +2001 8 16 18 4 MICHAEL 17.6 323.1 124 492 +1972 4 18 6 9 ERNESTO 42.3 171.2 57 699 +2002 4 2 0 8 PATTY 17.2 254.1 97 777 +1988 3 14 12 15 GORDON 16.3 349.2 157 91 +1997 6 27 12 17 HELENE 69.0 12.0 31 40 +1967 4 16 12 7 GORDON 23.2 121.3 110 418 +1990 4 28 18 4 DEBBY 38.5 97.9 50 84 +1989 6 11 12 20 HELENE 65.7 58.5 38 547 +1970 3 27 12 23 ALBERTO 23.9 316.3 25 442 +1974 8 9 6 4 BERYL 19.3 160.9 67 10 +1993 7 7 12 8 MICHAEL 55.6 258.0 148 565 +1959 2 4 0 22 MICHAEL 43.5 254.3 121 348 +1979 11 18 12 27 NADINE 60.8 316.8 131 442 +1993 12 25 6 23 ISAAC 56.7 135.6 129 308 +1959 4 1 18 11 OSCAR 43.0 151.7 72 210 +1973 2 7 18 4 TONY 59.6 231.4 123 841 +1954 3 6 12 5 MICHAEL 26.4 260.7 132 178 +1956 3 21 18 20 CHRIS 44.0 253.0 98 761 +1965 2 1 12 20 RAFAEL 10.0 250.8 19 279 +1989 1 19 12 16 ALBERTO 9.5 216.5 58 259 +1999 5 28 0 16 LESLIE 7.5 89.6 99 398 +1980 10 6 0 2 FLORENCE 35.6 56.8 73 813 +1993 4 21 18 17 OSCAR 10.8 186.3 101 502 +1959 10 10 18 28 VALERIE 33.7 247.3 104 809 +1968 10 5 18 28 ALBERTO 32.7 249.8 130 406 +1983 2 18 6 27 NADINE 43.6 138.9 13 185 +1967 5 4 12 20 WILLIAM 8.6 114.6 33 894 +1970 4 18 18 24 CHRIS 10.0 40.5 13 591 +1978 10 18 6 22 ALBERTO 59.7 175.0 160 806 +1999 6 7 6 13 MICHAEL 48.6 178.8 145 539 +1972 12 14 0 3 GORDON 41.3 293.0 113 770 +1999 1 19 18 7 PATTY 27.3 339.1 44 462 +1961 9 1 12 13 DEBBY 19.0 282.1 59 704 +2001 4 6 18 24 FLORENCE 48.3 233.3 70 281 +1950 2 7 12 10 FLORENCE 44.8 204.9 76 796 +1984 1 21 6 20 RAFAEL 16.1 309.5 68 703 +1950 4 11 6 16 SANDY 58.3 226.7 101 216 +1971 12 16 0 9 PATTY 33.7 83.7 48 644 +1987 4 11 6 22 WILLIAM 17.3 36.6 89 773 +1956 7 27 12 16 FLORENCE 52.9 116.8 155 785 +1987 8 6 6 13 GORDON 19.1 220.0 156 247 +1967 12 27 0 6 LESLIE 24.3 268.4 113 791 +1961 3 7 6 21 DEBBY 52.3 321.1 150 793 +1983 3 28 18 19 NADINE 57.8 25.3 148 399 +1988 4 5 18 20 LESLIE 54.1 209.0 50 775 +1975 9 20 18 28 TONY 61.0 165.4 109 209 +1970 12 14 0 21 RAFAEL 17.7 227.9 49 600 +1986 1 17 18 18 WILLIAM 39.1 44.5 78 809 +1980 5 4 12 17 ISAAC 60.5 351.7 84 351 +1967 4 11 0 4 ERNESTO 57.9 17.0 94 480 +2000 11 21 6 2 DEBBY 37.3 51.2 33 71 +1994 6 28 6 22 HELENE 61.4 82.8 26 794 +1958 3 7 12 4 ERNESTO 13.2 354.4 34 457 +1981 4 2 0 22 ISAAC 51.6 336.4 124 157 +1991 11 11 0 22 RAFAEL 42.9 219.8 52 428 +1992 1 24 12 27 MICHAEL 42.4 219.1 117 89 +1963 5 9 18 4 TONY 31.6 69.8 44 160 +2004 5 25 12 22 SANDY 16.6 269.4 87 896 +1971 5 1 12 17 TONY 22.0 207.2 56 544 +1979 7 3 0 26 CHRIS 40.7 20.4 105 65 +1951 5 13 0 27 PATTY 66.1 30.0 131 61 +1952 11 5 6 6 HELENE 54.4 347.5 17 122 +1958 9 25 0 14 LESLIE 20.9 163.1 58 760 +1968 12 26 6 24 MICHAEL 58.7 74.4 156 447 +1990 12 23 18 16 MICHAEL 63.4 211.6 29 154 +1964 11 2 0 5 OSCAR 32.1 130.6 141 208 +1998 6 21 18 25 NADINE 58.3 13.4 133 788 +1956 7 5 18 17 ALBERTO 30.7 16.1 127 282 +2000 9 12 0 18 SANDY 40.2 323.0 16 418 +1978 6 2 12 23 DEBBY 30.3 225.4 22 17 +1951 9 25 6 12 CHRIS 15.5 331.5 101 177 +1994 3 17 6 23 RAFAEL 8.5 344.4 139 202 +1984 2 4 0 17 WILLIAM 65.7 329.7 62 458 +1994 9 17 0 23 NADINE 44.3 225.6 124 428 +1952 12 9 0 17 NADINE 17.2 46.0 128 816 +2000 11 1 18 16 ISAAC 27.8 50.6 39 191 +1974 7 2 12 1 LESLIE 44.1 10.2 75 604 +1986 3 21 0 1 ALBERTO 20.8 221.5 164 10 +1951 9 4 12 26 FLORENCE 57.7 330.8 156 322 +1959 7 27 12 21 LESLIE 63.4 157.6 98 589 +1977 11 22 18 24 LESLIE 40.4 114.9 102 693 +1965 12 20 18 18 KIRK 40.4 15.2 162 877 +1983 2 23 0 14 JOYCE 49.9 103.1 162 816 +1993 12 1 12 5 KIRK 55.8 102.9 92 476 +1983 11 17 0 20 FLORENCE 21.3 172.4 77 301 +1959 8 15 18 14 RAFAEL 43.4 152.0 115 178 +1965 1 16 6 16 VALERIE 62.1 90.0 95 513 +1980 12 28 0 16 ALBERTO 18.5 120.1 140 741 +2004 1 1 6 21 ISAAC 46.8 30.9 117 369 +1990 7 20 12 1 NADINE 15.4 283.5 27 268 +1979 6 22 6 25 MICHAEL 57.0 29.0 70 867 +1960 2 20 12 9 GORDON 22.8 274.1 102 794 +1996 2 27 12 17 ERNESTO 26.8 251.9 98 112 +1962 9 28 6 4 HELENE 11.8 113.2 19 842 +1966 3 7 12 3 ISAAC 16.8 217.0 45 874 +1996 12 20 6 11 RAFAEL 20.0 91.5 17 89 +1994 3 14 12 14 CHRIS 20.4 270.6 110 416 +2004 12 12 0 27 GORDON 57.4 121.3 46 349 +1980 7 15 18 27 SANDY 20.0 89.6 111 463 +1950 7 5 18 14 ISAAC 27.1 284.4 128 305 +1984 2 26 6 3 RAFAEL 47.3 338.4 82 786 +1997 5 11 6 27 GORDON 32.4 242.7 87 135 +1984 2 20 12 8 CHRIS 61.6 352.6 69 846 +1953 1 4 12 26 JOYCE 46.3 177.8 60 401 +1958 4 5 6 4 JOYCE 52.6 119.1 50 582 +1983 9 12 12 25 GORDON 36.1 184.1 141 631 +1983 1 17 12 12 BERYL 19.6 73.8 10 189 +1997 4 17 12 3 MICHAEL 10.0 79.6 27 381 +1958 4 4 18 3 CHRIS 26.6 273.4 80 62 +1993 7 13 12 3 LESLIE 43.5 243.7 26 256 +1978 8 25 6 24 JOYCE 24.2 168.8 93 776 +1988 8 18 0 10 WILLIAM 36.4 95.7 31 717 +1965 5 27 12 17 HELENE 69.6 337.9 112 28 +1970 1 2 0 3 MICHAEL 50.9 131.2 138 274 +1989 6 18 6 12 HELENE 8.5 284.4 62 838 +1963 6 24 0 1 MICHAEL 37.4 189.7 147 127 +1982 12 3 6 6 ALBERTO 10.5 147.9 65 261 +1993 9 10 6 6 ALBERTO 29.9 84.6 141 114 +1980 6 6 6 4 FLORENCE 60.7 238.1 66 111 +1968 4 8 0 21 MICHAEL 69.4 46.8 14 609 +1993 8 3 6 18 RAFAEL 35.1 37.8 38 282 +1996 11 6 18 14 OSCAR 31.8 35.9 65 89 +2003 7 12 6 2 MICHAEL 42.4 330.6 85 175 +1955 11 1 18 12 TONY 40.1 177.4 17 566 +1976 10 15 6 11 SANDY 37.8 207.0 151 561 +1967 5 27 18 26 PATTY 49.9 336.2 70 205 +1966 10 17 12 21 PATTY 52.2 96.7 101 586 +1982 6 27 6 24 PATTY 61.8 146.9 135 318 +1972 6 12 18 25 PATTY 23.1 332.8 74 321 +1960 6 11 18 4 ERNESTO 7.9 235.3 68 608 +1975 10 5 6 11 ISAAC 7.9 271.0 26 37 +1975 3 20 6 15 LESLIE 35.6 139.3 132 288 +1980 12 26 12 13 SANDY 63.2 145.0 73 130 +2001 9 26 0 11 HELENE 38.6 229.6 146 779 +1995 4 6 12 5 VALERIE 59.3 42.7 135 58 +2003 11 4 12 15 NADINE 52.9 231.7 154 323 +1957 11 8 6 16 TONY 17.6 329.4 115 463 +1992 6 17 0 9 ALBERTO 58.6 40.5 64 680 +1978 3 26 18 24 HELENE 9.2 11.2 102 424 +1966 7 6 6 2 CHRIS 47.7 234.8 78 261 +1951 6 9 18 23 ISAAC 51.9 67.4 148 19 +1950 3 4 6 24 BERYL 30.3 195.4 72 364 +1985 3 3 12 16 KIRK 25.2 270.6 103 468 +1973 5 2 0 26 MICHAEL 10.4 282.8 142 442 +1999 1 12 12 3 ISAAC 16.2 165.5 93 547 +1980 11 12 18 15 TONY 20.7 277.8 113 517 +1954 8 15 0 18 JOYCE 46.5 313.7 49 827 +1995 1 9 6 18 HELENE 19.6 237.6 53 619 +1989 11 19 18 12 ALBERTO 36.5 353.6 63 866 +1960 7 4 0 28 KIRK 19.8 244.8 43 239 +1969 12 26 0 4 TONY 33.7 43.2 136 716 +1961 7 22 6 25 SANDY 33.5 298.8 69 331 +1951 9 14 12 13 KIRK 18.7 223.3 23 151 +1957 1 15 0 3 BERYL 14.6 96.4 153 586 +1950 5 19 18 8 NADINE 17.5 101.6 71 868 +2000 9 28 18 8 VALERIE 63.6 135.3 115 786 +1992 11 6 12 20 PATTY 22.9 11.0 58 301 +1978 5 26 6 24 VALERIE 21.1 222.7 140 555 +1965 1 13 0 17 MICHAEL 18.2 266.3 55 127 +2004 7 27 12 10 DEBBY 57.7 297.6 128 523 +1981 7 15 6 16 ERNESTO 21.1 48.5 51 652 +1995 11 1 18 10 NADINE 62.4 204.5 64 690 +1952 9 2 18 6 TONY 15.1 101.4 68 412 +1990 10 25 0 15 LESLIE 36.3 256.8 144 887 +1984 3 2 18 4 ALBERTO 67.0 145.2 43 294 +1980 2 6 12 2 DEBBY 11.3 299.7 60 665 +1973 8 3 12 28 ALBERTO 25.0 188.9 10 775 +1976 3 11 0 17 TONY 43.8 352.5 48 407 +1973 7 2 6 18 VALERIE 46.2 163.6 42 150 +1975 9 25 18 7 CHRIS 41.9 347.2 114 720 +1980 2 6 0 7 VALERIE 30.9 45.2 36 568 +1968 9 1 0 22 ISAAC 31.9 327.7 50 865 +1990 6 8 0 7 SANDY 22.1 137.0 130 593 +1959 8 7 6 21 RAFAEL 22.6 200.2 124 389 +1986 1 6 0 24 DEBBY 23.6 72.3 75 750 +1954 8 15 12 10 ERNESTO 61.4 208.8 39 602 +1969 7 21 12 5 NADINE 21.0 345.8 75 496 +2000 12 5 6 9 HELENE 13.7 317.4 86 660 +1952 2 8 12 24 ISAAC 53.5 65.5 84 523 +1986 5 10 0 6 RAFAEL 61.8 103.2 81 57 +1996 11 17 18 21 OSCAR 44.7 149.4 90 523 +1984 1 13 12 22 MICHAEL 30.7 288.3 36 661 +1978 1 28 12 21 ALBERTO 69.0 241.5 144 451 +1981 7 25 12 22 KIRK 32.9 219.1 92 728 +1953 4 4 12 23 NADINE 41.8 277.6 127 171 +1954 6 9 0 15 DEBBY 62.5 306.1 93 439 +1950 12 16 6 6 TONY 34.3 0.6 146 438 +1983 2 18 18 5 OSCAR 66.4 72.7 125 510 +1984 1 4 0 1 KIRK 16.3 27.0 83 110 +1997 2 26 18 11 ISAAC 33.9 256.5 13 588 +1999 5 14 18 23 LESLIE 45.6 11.5 141 79 +2001 8 2 18 6 ERNESTO 37.6 17.9 122 513 +1966 11 25 0 10 VALERIE 49.8 19.2 159 200 +1956 5 13 0 26 DEBBY 18.6 62.9 82 434 +1998 12 3 6 10 HELENE 26.6 146.6 150 490 +1977 8 19 6 26 OSCAR 25.0 3.0 124 686 +1978 10 10 18 3 HELENE 59.5 152.6 82 651 +1962 4 26 18 23 ERNESTO 56.8 350.8 154 535 +1956 10 19 6 28 SANDY 25.5 38.9 57 876 +1959 12 9 18 12 WILLIAM 20.0 321.0 13 526 +1959 10 9 6 17 JOYCE 19.5 41.5 135 276 +1997 11 15 6 28 VALERIE 46.4 330.9 96 665 +1990 8 24 12 20 CHRIS 59.8 215.2 29 237 +1985 12 3 12 11 OSCAR 43.0 130.6 128 237 +1993 12 3 12 17 CHRIS 69.7 69.3 86 348 +2000 6 11 18 12 JOYCE 51.5 172.0 104 502 +2004 10 20 6 27 FLORENCE 29.3 4.5 59 536 +1988 5 3 18 28 KIRK 65.2 136.3 12 235 +1971 7 9 18 6 FLORENCE 45.9 218.5 66 346 +1968 9 1 18 9 ALBERTO 57.1 85.8 149 29 +1987 11 28 6 4 ALBERTO 7.0 243.6 27 892 +1993 7 26 0 16 ERNESTO 59.8 298.2 151 331 +1957 1 19 12 27 NADINE 38.4 20.2 85 530 +1952 7 9 6 16 GORDON 34.8 249.9 115 351 +1982 11 18 0 19 FLORENCE 46.4 94.7 87 65 +1957 12 5 0 26 LESLIE 10.8 11.9 15 418 +1967 4 2 12 23 BERYL 61.0 125.8 13 237 +1995 12 1 18 17 ISAAC 33.0 184.7 82 133 +1970 8 10 6 22 CHRIS 31.3 72.6 45 593 +1989 9 6 12 24 NADINE 27.2 104.5 100 736 +1956 7 22 0 12 SANDY 51.6 52.6 14 452 +1975 7 5 0 1 BERYL 52.8 122.5 19 447 +1962 5 23 18 16 LESLIE 27.8 355.3 58 350 +1990 2 24 12 13 GORDON 59.5 104.3 57 276 +1967 1 16 12 15 VALERIE 20.1 173.6 45 767 +1977 6 27 0 23 HELENE 36.9 317.9 159 179 +1985 4 14 6 23 BERYL 24.2 131.2 63 398 +1966 9 13 18 5 WILLIAM 27.5 268.3 144 504 +1994 2 19 12 16 MICHAEL 49.0 48.8 128 136 +1974 11 13 6 4 NADINE 53.3 166.2 57 724 +1983 10 7 18 19 MICHAEL 21.8 183.1 18 240 +1955 5 5 18 23 WILLIAM 35.8 227.0 85 687 +1983 12 27 18 11 WILLIAM 15.7 21.6 130 567 +1972 6 13 12 24 LESLIE 13.8 245.1 26 205 +2002 7 6 6 7 ERNESTO 21.4 281.6 87 87 +1988 12 23 0 14 DEBBY 45.7 140.8 87 809 +1960 9 11 18 12 SANDY 32.3 218.5 141 322 +1953 2 16 0 16 HELENE 11.1 296.9 44 11 +1983 10 3 0 14 GORDON 43.5 275.5 36 598 +2003 5 28 6 23 GORDON 45.5 30.8 159 193 +1984 9 28 0 15 JOYCE 19.6 295.8 28 740 +1979 12 26 18 16 RAFAEL 33.4 203.0 151 548 +1952 11 26 18 5 KIRK 7.2 96.2 36 141 +1982 10 19 6 20 RAFAEL 16.9 285.4 48 382 +1959 2 28 12 7 MICHAEL 66.9 136.5 156 660 +2002 5 19 0 13 DEBBY 67.3 256.4 41 761 +1980 6 9 6 21 JOYCE 45.5 232.6 21 766 +1990 2 19 6 18 DEBBY 29.3 341.4 71 573 +1999 8 17 18 19 OSCAR 28.2 304.4 134 148 +2001 7 18 0 19 JOYCE 44.7 41.9 28 574 +1992 8 6 18 16 GORDON 17.1 61.4 27 793 +1965 12 19 0 13 KIRK 34.0 327.5 26 561 +2000 4 22 18 13 NADINE 60.8 35.6 60 520 +1977 3 18 6 11 DEBBY 36.4 296.2 149 660 +1952 9 25 12 19 CHRIS 20.4 133.0 50 784 +1963 10 28 18 9 ALBERTO 65.8 74.7 75 193 +1960 4 24 6 10 CHRIS 39.4 152.8 138 300 +1992 6 13 12 2 FLORENCE 54.8 215.8 113 642 +1972 12 18 0 21 RAFAEL 62.0 119.5 18 210 +1999 6 22 12 7 FLORENCE 67.6 90.8 114 453 +1962 10 2 0 19 BERYL 51.9 130.6 84 569 +1966 7 28 12 12 RAFAEL 55.7 219.1 100 806 +1990 8 7 0 19 PATTY 22.2 328.4 127 608 +1971 9 2 6 5 SANDY 18.8 46.8 145 224 +1987 12 20 18 17 TONY 9.8 155.4 63 594 +2000 4 8 12 24 VALERIE 51.5 152.5 93 414 +1978 7 24 12 16 BERYL 36.8 69.0 148 665 +1957 4 3 6 15 KIRK 53.3 211.6 102 206 +1993 9 19 12 13 ALBERTO 62.3 231.2 94 120 +1955 12 20 12 22 LESLIE 47.1 244.8 35 471 +1957 7 23 6 10 BERYL 17.0 96.4 40 860 +1962 12 4 6 23 ERNESTO 55.5 103.1 13 528 +1955 5 28 18 7 BERYL 52.8 81.8 16 718 +1960 7 12 0 13 HELENE 48.1 147.2 152 315 +1951 5 3 18 10 JOYCE 29.7 115.2 98 254 +1999 3 7 12 28 KIRK 56.2 122.1 47 834 +1986 12 16 12 24 CHRIS 25.1 195.9 75 418 +1985 2 16 6 28 ISAAC 18.4 353.1 19 852 +2001 7 12 6 2 NADINE 34.4 0.9 70 213 +1993 6 20 0 1 VALERIE 15.6 120.2 41 761 +1961 8 7 12 18 OSCAR 40.7 207.4 112 60 +1969 9 16 18 12 ALBERTO 9.9 169.5 33 193 +1984 11 1 12 17 TONY 16.0 179.7 133 341 +1998 3 10 6 18 SANDY 55.9 146.6 140 289 +1996 6 21 6 17 OSCAR 64.8 173.6 110 121 +1957 12 27 12 2 OSCAR 45.4 44.4 120 317 +1961 12 8 6 5 ERNESTO 63.1 198.0 94 589 +2001 2 27 12 9 WILLIAM 52.1 101.6 157 7 +2002 6 8 18 23 VALERIE 10.9 62.5 158 392 +1961 5 14 0 3 GORDON 42.7 7.5 81 186 +2000 7 6 18 20 LESLIE 20.5 269.7 96 531 +2002 6 12 12 9 HELENE 67.9 215.9 13 655 +1969 2 20 6 14 ISAAC 29.8 18.8 11 611 +2002 6 15 6 3 RAFAEL 60.5 155.2 124 637 +1974 6 6 12 10 GORDON 8.0 121.2 110 370 +1998 7 6 18 4 ERNESTO 37.5 331.8 120 267 +1960 6 5 6 2 BERYL 22.0 217.6 52 412 +1975 11 14 6 24 DEBBY 38.9 214.0 44 753 +2002 12 1 12 9 TONY 35.9 203.4 110 812 +1967 8 20 0 28 HELENE 20.4 297.6 35 720 +1973 5 11 0 11 BERYL 34.9 247.1 77 291 +1964 1 4 12 23 VALERIE 58.6 275.6 16 714 +1988 4 26 12 10 ALBERTO 34.2 356.0 159 712 +1999 9 17 0 18 BERYL 48.1 274.4 103 304 +2003 2 23 6 11 ALBERTO 29.7 76.9 139 665 +1979 2 25 12 23 SANDY 35.3 179.1 133 880 +1969 3 22 12 13 JOYCE 22.1 221.0 85 467 +1950 9 3 12 10 TONY 58.6 287.1 84 844 +1991 10 28 6 25 NADINE 67.7 245.9 17 874 +2003 6 5 12 19 ALBERTO 51.0 30.5 19 878 +1992 2 24 12 13 RAFAEL 60.9 261.1 38 575 +1998 10 5 12 16 WILLIAM 20.4 152.8 127 707 +1957 10 16 6 22 RAFAEL 54.0 231.3 22 744 +1954 7 11 0 24 MICHAEL 67.3 61.5 51 282 +2004 7 21 18 15 KIRK 16.3 167.2 40 131 +1956 9 18 18 20 HELENE 59.9 333.7 108 430 +2003 4 15 12 3 ERNESTO 20.6 0.9 54 105 +1990 7 5 12 16 RAFAEL 42.9 242.9 72 465 +1984 6 21 12 15 DEBBY 28.0 295.9 83 245 +1982 6 27 12 15 SANDY 52.9 136.4 35 292 +1969 8 12 18 15 JOYCE 22.4 24.5 81 372 +1956 6 3 0 25 NADINE 45.1 10.0 160 15 +1962 11 7 18 23 RAFAEL 69.9 352.9 107 218 +1982 5 4 6 10 BERYL 10.1 342.4 139 201 +2004 8 18 18 24 OSCAR 37.4 49.0 53 429 +1991 9 2 6 15 KIRK 68.9 119.4 58 210 +1952 8 25 18 4 RAFAEL 10.4 275.2 43 429 +1950 5 8 6 10 OSCAR 63.7 168.0 112 602 +1976 9 8 12 16 KIRK 38.8 117.0 64 308 +1959 5 23 18 23 NADINE 16.5 241.2 72 98 +1993 12 22 18 28 DEBBY 50.6 56.5 14 117 +1978 7 11 12 3 LESLIE 26.8 189.8 77 665 +1994 9 18 12 17 HELENE 22.4 92.1 80 793 +1970 5 15 12 10 RAFAEL 17.3 203.2 120 633 +1976 7 11 0 28 RAFAEL 48.9 150.3 145 382 +1996 3 19 18 25 OSCAR 46.0 151.6 119 378 +1981 10 6 12 4 BERYL 61.6 206.1 138 739 +1978 10 20 12 25 OSCAR 20.3 189.6 87 688 +1999 11 1 6 14 MICHAEL 51.1 82.6 105 815 +1950 8 24 12 6 TONY 44.1 17.7 36 551 +1958 5 18 6 12 SANDY 64.5 262.2 142 401 +1972 2 18 6 23 ERNESTO 15.5 223.6 163 664 +1991 9 18 6 10 ISAAC 39.7 111.1 93 121 +1977 1 21 0 19 OSCAR 29.1 268.4 71 404 +1970 5 2 12 28 OSCAR 60.8 250.2 124 285 +1972 1 5 18 19 OSCAR 16.6 86.9 67 666 +1980 12 5 0 18 LESLIE 7.1 122.6 26 627 +1996 7 18 12 7 SANDY 55.8 356.7 139 686 +1955 4 13 18 8 FLORENCE 25.4 343.7 116 418 +1951 12 20 12 22 ERNESTO 8.8 132.1 34 814 +2004 2 23 12 26 OSCAR 29.0 134.9 80 252 +2000 3 18 18 21 WILLIAM 39.1 212.2 40 891 +1968 2 7 18 1 TONY 37.8 219.4 141 883 +1959 6 17 12 7 MICHAEL 10.8 236.8 48 454 +1967 3 5 6 28 ALBERTO 68.9 258.2 40 538 +1959 11 9 6 23 SANDY 48.1 223.2 62 257 +1987 5 2 18 8 FLORENCE 9.9 285.1 116 602 +1969 10 13 0 1 CHRIS 62.4 166.6 19 766 +1961 6 23 18 2 WILLIAM 62.0 92.4 11 460 +1996 11 11 18 25 KIRK 38.1 339.4 85 36 +1955 2 25 18 5 TONY 13.8 99.0 124 303 +1982 6 9 6 12 ERNESTO 11.3 113.3 17 591 +1976 4 22 12 18 BERYL 35.8 280.1 119 582 +1953 3 24 6 15 PATTY 22.5 139.3 88 868 +1984 7 3 0 27 OSCAR 45.9 149.4 79 212 +1981 6 17 18 4 VALERIE 36.9 6.8 53 133 +1952 8 5 12 20 WILLIAM 63.3 56.9 114 258 +1965 2 28 0 15 SANDY 39.7 311.0 80 750 +1981 2 1 18 23 ERNESTO 16.2 242.4 52 842 +2002 10 8 12 3 DEBBY 69.3 146.0 13 255 +1977 4 12 12 24 HELENE 66.9 79.3 64 565 +1982 5 6 18 22 TONY 68.9 57.7 107 727 +1953 8 19 12 5 MICHAEL 23.1 322.5 139 355 +1984 11 13 12 9 MICHAEL 56.9 254.5 22 566 +1994 11 3 12 7 SANDY 24.3 5.0 42 132 +1961 1 16 0 2 GORDON 45.5 217.8 139 51 +1968 10 13 0 19 ALBERTO 12.1 148.9 86 681 +1985 3 13 0 14 VALERIE 65.8 308.6 126 631 +1956 2 12 18 25 GORDON 54.4 139.6 138 881 +2004 3 2 6 23 GORDON 67.5 177.8 19 402 +1976 8 17 18 4 JOYCE 13.5 232.9 40 219 +1956 9 20 18 19 SANDY 68.7 151.2 23 799 +1972 12 6 6 3 TONY 60.9 250.8 94 815 +1979 10 19 18 17 LESLIE 43.8 276.6 13 898 +1952 4 3 6 22 RAFAEL 26.2 153.1 128 153 +1995 2 1 12 22 JOYCE 24.6 58.6 92 140 +1954 9 9 18 14 DEBBY 69.3 62.0 151 752 +1967 1 2 18 19 NADINE 26.7 348.1 123 361 +1994 1 28 6 9 HELENE 67.0 33.2 126 78 +1977 5 17 0 9 ERNESTO 43.8 338.4 55 422 +1977 2 15 6 7 ISAAC 7.7 179.0 83 838 +1954 6 2 0 12 DEBBY 67.6 293.3 145 285 +1980 7 23 18 12 NADINE 40.1 51.7 127 537 +1995 4 13 18 18 KIRK 44.2 103.0 38 797 +1972 12 19 0 15 FLORENCE 56.1 150.5 66 381 +1973 2 2 0 1 TONY 41.8 78.6 159 619 +1986 6 17 6 21 NADINE 51.9 111.0 91 693 +1992 5 7 18 9 DEBBY 12.8 323.7 136 788 +1997 9 14 12 15 JOYCE 20.9 335.7 60 711 +1990 2 27 12 23 ISAAC 16.2 292.9 49 206 +1958 3 28 0 9 DEBBY 45.4 55.3 150 148 +1991 10 10 18 20 SANDY 24.8 321.5 107 659 +2001 4 27 0 10 ISAAC 22.2 280.9 130 695 +1952 3 9 6 28 WILLIAM 40.9 125.4 138 888 +1995 9 19 18 22 ERNESTO 41.2 72.6 164 455 +1996 8 2 18 22 RAFAEL 17.7 131.9 49 209 +1988 3 9 12 2 VALERIE 15.8 122.2 90 116 +1970 2 5 12 11 KIRK 55.8 259.9 24 864 +1967 4 18 0 18 KIRK 33.7 155.4 148 806 +1967 1 6 6 7 JOYCE 19.4 262.6 25 328 +1950 10 7 6 17 FLORENCE 63.2 217.4 154 729 +1974 1 5 12 6 MICHAEL 58.7 71.0 76 392 +1954 8 23 0 17 DEBBY 51.7 266.0 150 124 +1963 7 24 12 18 DEBBY 34.7 130.6 154 199 +1987 10 4 18 16 NADINE 7.8 229.0 57 476 +1997 12 7 12 19 ISAAC 69.2 332.0 52 17 +1973 8 1 6 19 FLORENCE 56.5 24.9 101 734 +1998 10 9 18 11 CHRIS 12.9 249.7 97 87 +1956 3 9 6 17 JOYCE 28.9 347.9 10 541 +1980 6 6 12 6 HELENE 40.9 285.6 66 519 +1990 5 18 0 3 WILLIAM 49.6 21.2 65 639 +1973 11 28 18 13 TONY 9.6 251.8 109 810 +2002 3 8 12 3 KIRK 34.8 120.6 153 686 +1998 1 5 18 9 PATTY 11.5 212.5 60 330 +2002 8 19 18 22 RAFAEL 26.3 354.3 160 876 +1988 10 6 6 21 DEBBY 56.6 309.1 153 293 +1951 10 26 6 23 VALERIE 58.6 330.6 74 805 +1991 9 12 6 6 BERYL 25.4 104.5 23 524 +2000 3 13 12 3 TONY 63.2 69.8 19 770 +2003 12 3 6 6 HELENE 43.4 243.1 16 679 +1994 5 2 6 16 DEBBY 36.1 163.9 107 77 +1970 6 28 18 15 VALERIE 66.4 355.2 101 370 +1961 4 28 12 2 ISAAC 15.6 75.8 120 520 +1956 9 20 18 22 JOYCE 27.4 290.2 19 776 +1967 3 4 12 11 GORDON 32.6 192.4 53 225 +1962 6 19 12 17 LESLIE 50.6 63.7 135 82 +2004 12 5 0 7 JOYCE 12.0 241.6 121 209 +1997 12 13 0 20 KIRK 37.4 152.9 111 106 +1953 5 26 12 7 SANDY 52.5 219.3 147 145 +1988 2 26 6 18 VALERIE 63.8 209.7 14 351 +1988 1 24 6 21 ISAAC 14.0 84.3 119 340 +1970 4 2 18 9 ERNESTO 32.3 128.0 45 173 +1966 6 16 12 16 KIRK 9.8 21.9 41 101 +2002 3 19 6 12 PATTY 34.6 107.1 160 105 +1959 9 3 0 19 ERNESTO 41.2 100.1 24 245 +1974 9 9 18 1 TONY 20.5 226.5 41 497 +1955 10 9 6 5 ALBERTO 67.1 45.5 118 166 +1999 10 16 0 10 LESLIE 40.7 136.0 129 638 +1950 3 10 18 26 BERYL 61.2 95.8 25 427 +1987 3 28 18 20 KIRK 42.8 317.2 102 531 +1962 11 27 0 25 DEBBY 44.2 128.0 94 760 +1960 1 3 6 5 ERNESTO 67.1 205.3 123 362 +1959 10 4 6 3 FLORENCE 35.1 185.8 28 227 +2003 5 9 0 13 PATTY 21.8 258.4 130 532 +1964 4 10 18 28 TONY 11.1 60.8 119 512 +1965 4 14 6 6 ALBERTO 37.6 214.9 129 86 +1959 1 10 0 4 ERNESTO 9.5 352.0 20 67 +1958 1 10 6 15 KIRK 20.8 134.4 108 58 +1958 2 26 12 26 TONY 41.1 316.0 161 141 +1950 10 17 12 16 WILLIAM 65.5 227.1 139 65 +1989 9 18 0 23 CHRIS 51.4 205.9 68 348 +1974 11 10 18 13 MICHAEL 10.4 267.4 35 526 +1991 12 9 12 15 WILLIAM 36.6 224.1 117 569 +1992 6 13 6 22 VALERIE 40.9 152.2 10 656 +1993 7 28 18 28 PATTY 7.8 242.5 14 386 +1967 4 5 18 20 DEBBY 15.1 71.2 110 428 +1966 8 24 6 14 KIRK 45.4 303.5 63 442 +1971 7 21 12 25 BERYL 55.6 339.8 83 342 +1986 9 20 12 17 KIRK 27.6 270.8 100 809 +1999 2 27 12 3 FLORENCE 49.8 233.4 94 30 +1959 9 12 6 21 ISAAC 68.0 265.1 110 411 +1976 10 21 6 8 DEBBY 20.5 332.7 161 635 +1993 6 25 12 20 BERYL 68.7 209.6 32 192 +1997 3 28 6 19 NADINE 28.5 352.6 68 549 +1975 12 8 0 14 PATTY 50.2 157.4 64 444 +1989 4 14 12 23 NADINE 10.3 4.5 160 828 +2000 6 20 12 3 PATTY 60.7 239.3 40 852 +1950 7 19 0 18 JOYCE 66.3 229.6 154 735 +1985 2 1 6 8 GORDON 16.6 255.3 40 545 +1989 9 20 0 4 NADINE 21.3 245.2 11 765 +1972 1 10 6 15 MICHAEL 66.9 86.9 68 477 +1994 12 1 6 25 DEBBY 8.9 78.3 89 421 +1999 12 17 12 7 TONY 39.1 169.1 36 53 +1981 10 15 18 15 TONY 50.8 146.3 145 744 +1989 1 15 6 15 JOYCE 43.3 187.2 17 321 +1978 8 12 0 1 ALBERTO 8.5 344.8 159 666 +1971 3 4 6 12 WILLIAM 35.1 7.0 36 91 +1999 7 9 12 17 NADINE 24.4 139.6 24 539 +2002 1 25 18 10 JOYCE 38.4 210.0 15 687 +1952 9 18 18 13 MICHAEL 32.8 221.8 76 875 +1994 2 10 12 9 CHRIS 25.2 310.8 159 821 +1959 12 28 12 21 MICHAEL 42.0 295.7 143 83 +1984 4 7 18 27 MICHAEL 13.2 90.7 26 58 +1954 9 14 0 14 NADINE 19.2 317.2 115 451 +1984 1 13 18 24 RAFAEL 56.6 258.6 112 610 +1995 10 4 18 10 JOYCE 28.8 50.7 40 719 +1959 4 9 6 2 SANDY 48.7 232.0 90 643 +2000 3 19 12 11 CHRIS 22.5 80.2 130 871 +1970 1 21 18 20 ISAAC 35.7 335.2 120 146 +1979 12 16 6 21 MICHAEL 29.1 266.0 26 587 +2001 9 20 6 12 LESLIE 8.3 133.2 40 780 +1962 11 23 18 5 MICHAEL 60.2 340.6 56 657 +1976 8 28 0 6 WILLIAM 64.0 168.6 141 744 +1965 8 25 6 24 KIRK 29.4 136.2 103 26 +1962 2 9 6 2 JOYCE 62.4 86.5 71 104 +1953 9 18 12 27 FLORENCE 70.0 324.1 137 826 +1975 3 4 6 27 HELENE 22.9 275.8 29 347 +1997 8 20 12 6 OSCAR 54.0 318.1 22 878 +1995 5 2 6 24 ALBERTO 66.5 17.6 151 521 +1994 11 13 0 3 GORDON 22.1 141.6 82 332 +1992 11 12 12 10 BERYL 24.7 249.5 20 760 +1968 4 23 12 27 DEBBY 37.5 161.2 118 234 +1972 8 5 18 19 CHRIS 62.8 46.2 158 827 +1996 5 3 6 11 OSCAR 54.8 250.4 99 324 +1958 3 26 18 18 ALBERTO 61.7 7.0 30 447 +1963 8 16 18 11 ERNESTO 10.4 298.9 33 736 +1968 9 10 12 20 SANDY 25.8 46.9 148 891 +1963 1 5 12 6 MICHAEL 18.7 82.5 72 440 +1956 10 19 12 27 CHRIS 16.3 3.8 56 280 +1960 12 24 18 4 RAFAEL 19.4 146.6 57 527 +2000 10 19 0 15 RAFAEL 27.6 32.5 35 456 +1965 11 19 12 23 LESLIE 7.7 28.7 107 113 +1950 9 7 12 7 MICHAEL 48.7 165.3 141 201 +1988 3 11 18 26 LESLIE 25.8 134.8 68 894 +2000 9 5 12 11 DEBBY 68.1 242.3 160 652 +1972 4 2 18 25 SANDY 30.6 114.7 54 213 +1968 9 21 0 19 NADINE 55.5 265.9 42 855 +1966 12 3 18 10 OSCAR 66.0 7.4 58 547 +2002 9 6 12 20 SANDY 12.8 66.2 16 692 +1962 11 19 12 22 MICHAEL 34.7 46.0 21 111 +2000 2 18 18 2 ALBERTO 54.8 310.9 77 337 +2004 11 21 0 7 KIRK 29.2 213.1 62 800 +1966 4 24 0 12 ERNESTO 64.1 193.8 139 7 +1972 6 28 0 6 HELENE 53.9 68.6 155 666 +1983 10 11 6 25 JOYCE 40.7 118.2 93 25 +1983 3 25 12 27 SANDY 35.7 152.7 137 326 +1959 10 26 12 16 FLORENCE 17.0 266.2 89 799 +1950 4 6 0 9 HELENE 47.3 90.1 53 836 +1989 10 14 12 26 WILLIAM 26.7 257.7 141 246 +1958 7 12 6 17 KIRK 13.7 10.1 39 844 +1961 6 26 0 4 TONY 16.0 302.6 110 367 +1972 4 20 12 25 ISAAC 7.6 54.9 20 691 +1983 2 6 0 8 NADINE 25.5 83.0 77 313 +2002 11 3 6 16 ALBERTO 62.8 116.5 20 152 +1955 9 25 18 12 KIRK 8.7 28.2 60 358 +1960 10 4 6 4 OSCAR 17.3 221.0 45 898 +2004 10 6 6 6 OSCAR 10.4 342.2 102 157 +1967 4 2 6 15 SANDY 63.1 40.1 136 81 +1952 7 21 18 4 LESLIE 59.4 46.2 56 404 +1962 1 19 12 15 ERNESTO 24.9 28.9 102 180 +1986 7 4 18 26 NADINE 59.6 81.3 96 804 +1971 6 10 6 21 HELENE 16.3 127.2 153 273 +1994 10 19 0 7 FLORENCE 16.0 179.0 134 563 +1988 1 5 0 22 CHRIS 45.0 112.2 33 858 +1996 11 15 18 6 ALBERTO 52.5 265.5 125 431 +1985 4 4 6 8 ALBERTO 19.3 42.3 60 619 +1961 3 4 0 28 CHRIS 69.9 14.2 136 891 +1980 1 23 6 19 HELENE 53.5 171.7 160 568 +1962 9 22 0 26 HELENE 47.1 53.7 117 36 +2001 2 9 12 14 CHRIS 11.9 188.2 68 158 +1982 1 9 12 17 MICHAEL 13.5 347.2 88 712 +1956 6 13 0 21 KIRK 58.8 195.2 65 890 +1969 12 1 6 28 VALERIE 28.5 277.2 152 11 +1956 3 22 6 23 MICHAEL 60.3 330.2 123 177 +1991 6 10 12 27 OSCAR 46.0 224.5 27 894 +1992 9 28 18 4 ALBERTO 21.9 327.0 59 446 +1959 10 28 12 24 RAFAEL 14.2 210.3 14 236 +1958 9 25 12 14 JOYCE 24.2 30.5 139 708 +1986 7 3 12 6 OSCAR 41.0 11.5 56 10 +1978 2 24 12 19 MICHAEL 12.0 211.6 93 501 +1978 12 7 0 19 RAFAEL 66.7 299.1 115 723 +1951 3 27 12 3 KIRK 54.9 214.8 129 780 +1962 5 14 18 4 SANDY 50.5 34.2 111 483 +1952 4 28 18 14 FLORENCE 26.0 69.2 83 510 +1986 1 10 18 25 DEBBY 58.6 299.4 34 242 +2001 8 18 12 18 DEBBY 18.9 307.5 107 56 +1975 9 10 0 1 RAFAEL 24.0 54.1 37 792 +1995 4 21 6 25 KIRK 12.3 156.6 144 424 +1958 1 4 6 13 CHRIS 42.7 83.3 130 357 +1965 9 4 12 25 NADINE 33.1 263.5 62 235 +1971 3 17 6 4 FLORENCE 46.0 84.9 138 13 +1951 8 7 12 11 WILLIAM 65.4 37.9 94 733 +1968 7 16 6 6 TONY 18.3 282.8 151 132 +1951 12 22 6 17 LESLIE 51.2 344.7 57 144 +1968 5 26 12 16 TONY 19.5 131.0 107 351 +1961 4 9 6 5 VALERIE 65.4 121.1 37 405 +1990 10 24 18 19 FLORENCE 65.1 117.2 99 98 +1983 7 4 18 17 MICHAEL 67.7 170.2 140 734 +1965 8 5 12 26 LESLIE 7.2 58.2 146 603 +1978 10 12 0 19 PATTY 55.4 283.5 69 368 +2000 2 10 12 4 GORDON 41.3 252.0 145 699 +1975 6 26 0 25 JOYCE 58.2 70.0 40 586 +1952 9 15 18 19 CHRIS 24.4 101.3 36 633 +1972 11 6 6 12 HELENE 65.0 38.5 157 468 +2003 8 11 0 11 HELENE 29.5 262.9 97 311 +1959 6 11 12 22 FLORENCE 58.9 270.4 98 669 +1980 4 6 0 1 PATTY 67.4 352.4 116 422 +1957 8 17 18 16 WILLIAM 48.9 25.3 83 52 +1960 11 22 6 20 MICHAEL 12.9 349.9 127 475 +1990 4 13 6 10 OSCAR 14.7 129.7 97 607 +1998 2 4 6 6 ALBERTO 63.9 149.4 155 116 +1953 6 7 12 14 JOYCE 42.0 181.0 152 225 +2002 4 18 12 9 TONY 31.6 195.4 72 118 +1999 7 8 0 10 OSCAR 30.3 106.9 74 39 +1994 2 2 18 28 GORDON 10.4 222.8 117 236 +1961 2 19 0 18 SANDY 57.2 296.0 77 666 +1984 1 20 6 24 DEBBY 67.2 50.6 54 511 +1953 4 6 6 22 NADINE 39.8 298.1 156 236 +1961 1 17 18 23 DEBBY 52.1 229.9 87 388 +1972 7 24 12 12 RAFAEL 30.8 56.4 92 193 +1964 8 7 18 24 RAFAEL 61.5 147.5 79 309 +1967 11 11 12 7 VALERIE 46.4 8.2 122 333 +1982 2 6 18 9 SANDY 7.6 231.2 94 174 +1950 5 9 0 5 VALERIE 46.3 276.0 90 65 +1950 8 19 6 26 OSCAR 62.8 98.0 18 682 +1959 4 1 12 23 MICHAEL 55.4 217.8 91 30 +1995 10 20 12 14 SANDY 31.1 304.8 151 31 +1994 1 28 6 13 CHRIS 41.5 46.4 49 852 +1997 8 4 12 10 BERYL 61.2 124.0 154 206 +1967 11 11 6 9 NADINE 59.9 131.3 10 97 +1977 9 14 6 16 RAFAEL 42.0 266.0 78 860 +1991 3 1 6 18 KIRK 25.9 329.1 108 354 +1966 8 6 18 8 FLORENCE 41.5 92.3 22 193 +1977 1 18 6 2 JOYCE 67.7 277.1 44 879 +1990 6 8 18 15 LESLIE 57.2 274.6 127 632 +1983 1 3 12 23 CHRIS 60.6 322.4 139 759 +1980 8 5 12 11 RAFAEL 16.6 239.8 24 338 +1989 8 23 18 15 NADINE 61.3 44.4 36 256 +1961 10 13 12 23 SANDY 56.1 63.3 149 379 +1996 4 19 0 25 LESLIE 64.4 134.4 154 790 +1988 2 18 0 11 LESLIE 65.3 291.9 119 537 +1978 2 10 18 4 LESLIE 63.3 198.1 64 187 +1950 3 7 12 15 PATTY 30.9 156.0 60 331 +1980 3 10 12 7 CHRIS 63.6 129.8 154 766 +1970 10 3 12 3 KIRK 18.3 158.2 146 587 +1952 3 17 0 8 OSCAR 54.3 91.3 159 442 +1955 6 11 12 19 SANDY 25.7 85.8 16 453 +1987 3 10 12 15 PATTY 58.4 270.5 92 308 +1961 3 16 12 28 VALERIE 13.3 186.2 128 600 +1976 2 20 0 9 PATTY 18.7 2.3 123 344 +1981 9 27 6 26 KIRK 23.2 250.7 36 533 +1971 11 1 18 9 VALERIE 39.6 209.9 70 69 +1951 3 28 6 22 WILLIAM 45.8 245.9 23 420 +1993 2 17 6 14 TONY 18.5 350.1 113 57 +2001 6 7 6 4 CHRIS 57.2 279.0 76 110 +1958 9 5 18 25 OSCAR 27.0 293.0 83 614 +1967 9 10 18 20 OSCAR 22.2 317.1 154 759 +1974 3 14 12 28 PATTY 40.8 242.2 136 800 +2002 3 17 12 7 SANDY 32.9 277.6 109 476 +1988 8 27 0 26 FLORENCE 51.4 112.6 102 671 +1982 7 12 0 4 MICHAEL 29.2 48.0 90 153 +1976 1 27 18 7 DEBBY 64.1 253.4 96 134 +1996 3 18 18 3 KIRK 52.4 178.8 143 287 +1951 8 17 18 17 GORDON 58.5 334.3 28 735 +1985 1 7 6 19 ALBERTO 50.8 5.7 67 333 +2002 9 28 12 11 NADINE 17.5 225.4 124 13 +1952 2 5 18 4 OSCAR 55.8 32.2 101 620 +2001 5 10 0 9 PATTY 57.9 104.1 127 712 +2004 12 27 12 3 ALBERTO 10.3 291.4 38 611 +1974 10 23 18 18 TONY 69.6 21.7 34 79 +1986 12 15 12 20 PATTY 62.9 1.6 78 133 +1985 8 3 12 8 ISAAC 11.1 259.7 15 140 +1989 9 28 12 6 VALERIE 58.4 17.6 52 752 +1985 10 18 18 6 ISAAC 7.4 78.9 129 588 +2004 5 10 18 13 OSCAR 60.4 57.5 139 762 +2002 12 24 6 12 FLORENCE 64.5 124.9 12 684 +1953 12 21 6 7 FLORENCE 36.5 240.9 19 360 +1964 7 25 6 2 MICHAEL 16.1 172.1 41 99 +1989 6 3 12 2 OSCAR 11.0 134.6 161 335 +1990 8 11 12 6 ERNESTO 19.7 199.4 164 124 +1976 6 27 6 5 SANDY 32.8 189.6 14 564 +1976 6 11 0 9 BERYL 20.3 124.9 97 165 +1970 5 15 6 24 ISAAC 43.4 120.5 112 838 +1992 2 11 6 17 NADINE 64.4 15.5 105 457 +1963 9 21 0 18 TONY 57.3 341.4 146 96 +2004 3 12 18 11 NADINE 53.2 235.2 143 677 +1950 12 2 6 24 WILLIAM 28.1 51.7 124 551 +1979 7 23 0 20 SANDY 69.0 215.4 84 183 +1981 9 12 6 8 ISAAC 38.9 182.5 112 763 +1983 11 12 12 17 JOYCE 53.7 198.9 50 137 +1973 6 22 18 14 DEBBY 29.8 240.1 89 31 +1966 9 23 12 16 ALBERTO 61.3 311.8 81 80 +1953 7 9 18 3 OSCAR 34.2 139.6 89 358 +1950 7 12 18 17 HELENE 57.1 57.4 62 796 +1973 6 5 12 15 ALBERTO 21.3 50.9 46 650 +1957 1 27 0 19 JOYCE 36.7 133.7 107 605 +1964 9 28 6 26 HELENE 63.2 272.8 87 275 +1968 4 7 18 10 VALERIE 11.0 327.7 66 868 +1997 3 10 18 1 DEBBY 25.6 240.3 160 531 +1978 7 8 12 25 DEBBY 36.1 296.2 107 849 +1984 12 22 18 27 HELENE 66.7 82.0 140 212 +1975 4 13 6 19 VALERIE 8.2 324.8 18 604 +2000 9 16 0 1 RAFAEL 46.6 152.1 162 478 +1987 5 16 6 5 CHRIS 56.6 134.7 116 136 +2000 3 6 18 7 VALERIE 17.3 236.5 117 153 +1963 2 28 18 1 TONY 37.1 350.1 16 512 +1968 5 13 6 19 NADINE 56.5 145.7 22 605 +1963 9 8 18 4 ISAAC 62.3 269.9 147 440 +1973 9 26 18 14 LESLIE 27.1 346.9 135 770 +1996 9 4 0 8 JOYCE 45.0 237.9 146 696 +1966 7 19 12 2 JOYCE 59.0 242.7 106 617 +1999 5 15 0 9 WILLIAM 51.2 304.6 17 483 +1985 3 6 18 4 MICHAEL 10.7 144.1 105 854 +1988 8 20 12 8 FLORENCE 39.5 256.1 88 40 +1982 10 11 12 7 ISAAC 31.5 232.2 47 253 +1967 7 16 6 1 MICHAEL 7.9 174.0 54 857 +1965 1 13 6 19 NADINE 31.7 106.8 115 835 +1955 8 16 6 18 JOYCE 10.7 317.1 58 817 +1973 11 24 18 5 PATTY 43.6 330.6 140 703 +1973 6 8 6 14 CHRIS 54.3 97.5 36 571 +1986 9 22 0 7 BERYL 68.3 94.7 23 594 +1998 4 20 12 22 CHRIS 59.8 36.0 40 828 +1997 9 22 0 9 RAFAEL 47.0 59.6 102 229 +1996 10 13 12 16 OSCAR 50.7 22.9 151 507 +1967 12 10 6 5 OSCAR 40.1 37.9 95 29 +1967 2 25 6 18 OSCAR 7.7 82.0 18 68 +1987 12 17 6 24 ALBERTO 37.3 148.3 111 90 +1958 5 2 0 28 ALBERTO 64.5 307.0 145 474 +1995 3 9 6 18 TONY 61.9 11.3 75 330 +1995 10 8 18 8 VALERIE 56.8 218.4 101 813 +1994 4 8 18 25 ALBERTO 61.1 92.2 64 777 +1964 1 2 0 11 ISAAC 17.2 264.0 106 311 +2004 5 23 6 16 DEBBY 25.6 84.6 55 132 +1985 8 2 18 10 JOYCE 27.7 176.6 124 566 +1999 3 22 6 16 ERNESTO 48.8 260.3 87 375 +1964 7 18 18 16 CHRIS 51.7 350.3 130 396 +1970 12 28 6 15 ERNESTO 45.5 282.3 143 456 +1965 1 11 18 20 DEBBY 45.0 24.4 85 39 +1989 5 7 12 26 WILLIAM 52.6 82.7 41 686 +1965 7 18 0 23 ISAAC 65.4 10.6 49 285 +1990 1 12 0 10 JOYCE 61.0 14.2 99 746 +1971 9 5 0 14 ALBERTO 54.9 166.5 114 9 +1966 2 20 18 4 GORDON 52.0 165.6 124 150 +1951 9 23 0 24 FLORENCE 17.4 257.9 122 47 +1980 6 21 6 22 GORDON 42.4 104.2 111 433 +1962 7 2 12 27 PATTY 31.8 66.9 73 65 +1951 4 17 6 19 FLORENCE 28.7 53.7 154 896 +1998 4 4 18 13 GORDON 62.1 247.2 33 345 +1992 6 20 18 25 HELENE 15.5 68.3 22 118 +1977 11 11 12 11 NADINE 68.3 255.4 101 168 +1998 1 3 12 28 ALBERTO 29.8 331.0 164 471 +1953 12 4 18 20 ERNESTO 56.9 3.3 22 689 +1981 1 22 18 15 ALBERTO 22.8 81.9 53 484 +1965 12 21 18 7 ISAAC 33.3 223.7 160 729 +1964 4 4 12 12 BERYL 31.0 16.1 77 162 +1953 7 28 0 8 BERYL 45.9 170.4 76 581 +1981 11 4 0 25 ERNESTO 21.6 185.1 96 506 +1988 7 22 12 13 OSCAR 7.5 18.3 161 453 +1999 12 22 6 28 LESLIE 17.4 262.3 52 794 +1972 9 3 6 10 FLORENCE 32.4 217.9 58 367 +1953 2 7 18 2 BERYL 68.0 331.4 51 203 +1960 1 10 0 3 OSCAR 7.6 315.9 53 758 +1998 6 6 6 12 GORDON 51.5 28.4 146 629 +1978 2 11 18 16 TONY 21.6 292.7 94 394 +2004 12 11 6 17 ISAAC 32.1 257.7 133 632 +1957 10 6 18 17 ALBERTO 26.1 324.9 19 201 +1985 1 23 18 13 RAFAEL 69.4 322.5 156 403 +1997 1 22 12 6 SANDY 49.8 258.9 75 282 +1969 10 3 12 13 ERNESTO 54.0 143.6 140 329 +1975 6 14 18 14 PATTY 9.6 340.4 75 664 +1956 7 14 18 7 VALERIE 31.5 77.0 127 175 +1975 1 28 6 7 PATTY 9.8 195.7 117 612 +1959 12 27 0 28 HELENE 32.1 235.8 52 511 +2000 10 10 6 6 KIRK 56.8 90.0 95 749 +1971 11 24 6 14 ERNESTO 60.3 346.0 31 95 +1961 4 24 18 25 CHRIS 63.8 226.0 138 158 +1987 10 25 6 6 CHRIS 25.8 119.2 95 559 +1956 10 11 18 26 NADINE 16.8 26.8 40 712 +2003 11 19 12 23 FLORENCE 18.7 357.6 41 836 +1964 9 4 6 7 CHRIS 52.9 61.6 77 854 +2003 5 15 18 7 OSCAR 34.3 234.4 147 830 +1952 7 3 18 3 NADINE 12.8 137.7 118 175 +1955 7 22 0 9 JOYCE 23.5 162.8 107 852 +1956 10 25 18 16 BERYL 10.9 192.4 134 722 +1956 7 21 6 23 CHRIS 51.8 227.7 79 453 +1972 12 22 6 13 CHRIS 34.9 269.9 25 708 +1979 4 12 6 28 MICHAEL 30.8 174.8 45 534 +2003 5 20 18 15 HELENE 60.9 307.4 22 220 +1967 2 20 12 12 HELENE 60.1 251.6 30 592 +1974 7 16 18 7 FLORENCE 10.9 148.0 45 378 +1977 2 4 18 8 ISAAC 65.8 55.9 117 135 +1961 10 24 12 12 VALERIE 66.9 17.4 59 661 +2002 3 11 12 7 NADINE 42.1 199.3 117 142 +1957 10 7 6 5 BERYL 7.5 323.9 143 450 +1957 7 21 6 6 MICHAEL 30.9 173.4 29 789 +1975 6 20 6 1 HELENE 16.0 263.8 75 365 +1957 1 23 12 17 GORDON 42.3 286.1 53 401 +1973 6 5 0 3 MICHAEL 61.8 2.5 82 743 +1955 6 14 12 8 OSCAR 23.4 268.3 91 794 +1987 7 5 6 23 JOYCE 47.2 75.7 60 127 +1984 3 20 18 11 HELENE 58.8 347.6 152 42 +1978 11 2 18 25 MICHAEL 37.4 295.7 98 791 +2001 9 20 12 28 TONY 30.0 38.6 121 408 +1994 2 17 6 21 ALBERTO 33.2 266.1 68 824 +1998 11 6 6 9 VALERIE 57.3 350.1 44 843 +1985 10 24 12 15 VALERIE 53.2 267.6 52 92 +1974 3 18 6 13 PATTY 50.5 332.8 159 516 +1969 8 26 12 16 KIRK 44.4 95.2 96 449 +1966 10 19 18 9 ALBERTO 41.3 93.2 111 835 +1971 5 5 18 4 CHRIS 62.6 137.3 31 640 +1981 11 5 6 8 CHRIS 52.9 226.5 48 529 +1953 7 19 6 24 BERYL 12.1 157.3 45 196 +1972 1 26 0 10 RAFAEL 16.5 307.1 129 659 +1972 7 15 0 12 OSCAR 44.3 160.0 20 199 +1979 5 27 12 18 ISAAC 27.9 284.8 31 777 +1999 1 17 0 26 CHRIS 8.2 212.1 86 754 +1984 12 24 18 12 FLORENCE 55.4 82.4 145 743 +1965 9 4 0 25 VALERIE 46.4 212.5 77 241 +1963 10 4 0 8 OSCAR 7.3 130.5 142 228 +2003 10 9 12 27 LESLIE 41.2 151.2 122 67 +1998 9 17 6 3 ISAAC 39.0 63.9 105 890 +1964 6 5 18 16 GORDON 16.7 45.5 159 133 +2000 12 13 12 2 VALERIE 68.0 95.1 20 97 +1978 10 22 18 28 FLORENCE 25.3 174.5 93 333 +1955 8 9 18 8 LESLIE 15.2 103.2 14 698 +1955 6 5 18 28 OSCAR 63.6 14.8 109 875 +2001 4 6 0 1 WILLIAM 57.6 257.1 30 320 +1955 6 10 0 11 NADINE 33.5 76.5 16 77 +2003 3 13 6 13 LESLIE 13.7 219.9 107 865 +1958 6 7 0 15 NADINE 64.1 9.7 116 405 +1979 4 12 6 22 TONY 64.7 179.8 51 591 +1961 6 23 6 24 CHRIS 54.1 191.7 31 453 +1992 12 12 6 6 GORDON 68.1 76.3 155 729 +1969 12 5 6 18 FLORENCE 65.0 57.5 126 792 +1951 2 19 0 22 ISAAC 11.7 219.3 26 30 +1965 9 16 6 22 WILLIAM 53.4 268.5 147 357 +1960 10 4 18 21 HELENE 60.0 148.7 37 132 +1963 3 5 0 8 DEBBY 68.9 5.9 36 551 +1958 12 11 12 15 KIRK 34.5 306.5 112 28 +1981 4 18 18 6 PATTY 32.1 324.7 43 703 +1984 9 4 12 15 ERNESTO 19.8 126.3 55 702 +1967 4 15 12 7 DEBBY 12.9 200.1 29 855 +2001 6 25 12 25 CHRIS 46.5 148.6 69 181 +1961 12 7 6 28 BERYL 32.4 102.0 163 679 +1977 11 23 12 7 TONY 54.3 115.6 19 393 +1983 8 19 18 17 MICHAEL 35.6 0.5 86 27 +1994 7 25 0 25 ERNESTO 30.0 149.4 13 53 +1982 2 13 0 5 PATTY 26.2 199.5 164 797 +1991 8 19 0 2 ALBERTO 26.7 350.5 117 240 +1988 10 18 18 5 KIRK 56.5 136.5 152 362 +2003 10 24 0 6 NADINE 50.3 326.8 128 351 +1977 3 9 6 15 TONY 57.3 221.7 91 171 +2002 11 15 12 28 SANDY 66.0 273.1 15 289 +1976 12 8 0 20 BERYL 50.6 223.2 57 237 +1967 3 5 12 2 ERNESTO 59.2 170.6 79 88 +1995 2 19 6 22 JOYCE 14.3 6.6 127 643 +1965 1 28 12 21 VALERIE 31.0 267.5 114 444 +1998 7 15 12 7 ERNESTO 41.8 185.3 125 784 +1951 5 12 12 15 TONY 61.2 301.2 100 852 +1985 8 20 6 4 ISAAC 41.2 30.3 47 65 +2004 3 6 0 8 BERYL 28.3 122.6 55 166 +1989 7 28 18 28 DEBBY 21.9 96.6 154 133 +1950 5 24 0 8 ISAAC 10.9 233.3 16 169 +1978 3 27 12 3 RAFAEL 38.9 266.0 38 720 +1977 4 26 0 6 PATTY 67.9 106.5 97 499 +1957 10 5 6 1 KIRK 59.4 184.6 93 454 +1971 7 20 18 10 DEBBY 48.2 209.8 144 389 +1979 2 1 6 10 WILLIAM 65.5 330.7 84 574 +2004 1 6 18 5 GORDON 23.5 157.4 105 330 +1953 3 11 0 12 GORDON 44.5 318.8 154 200 +1981 11 26 0 24 ISAAC 38.8 349.1 79 399 +1950 11 16 0 15 GORDON 41.2 316.3 59 388 +1968 5 5 0 10 WILLIAM 31.6 70.3 141 407 +1973 3 14 18 3 ERNESTO 42.3 353.0 130 298 +1982 8 26 0 17 GORDON 26.1 276.4 154 162 +1950 12 26 18 17 DEBBY 51.5 60.0 143 657 +1964 12 19 6 10 WILLIAM 49.1 122.9 39 322 +1994 3 1 12 24 PATTY 44.2 136.9 40 894 +1965 4 4 6 15 HELENE 69.9 160.0 90 293 +1963 5 15 12 18 MICHAEL 39.3 37.3 85 618 +1963 5 18 12 11 HELENE 53.0 153.0 88 540 +1987 1 5 18 14 SANDY 62.4 112.8 143 701 +1985 4 21 12 1 JOYCE 39.2 101.8 134 447 +1964 11 4 12 7 PATTY 48.8 244.7 143 411 +1976 3 20 0 26 ALBERTO 64.6 23.0 160 205 +2003 9 14 18 15 LESLIE 49.1 85.6 102 304 +1951 1 15 6 24 CHRIS 41.8 157.1 126 304 +1953 1 6 12 3 GORDON 27.0 45.8 156 696 +1953 2 28 6 3 ISAAC 40.0 61.5 115 816 +1993 3 16 18 11 SANDY 56.6 87.1 57 153 +1961 2 2 18 19 HELENE 69.8 275.8 142 451 +1953 4 6 0 4 GORDON 28.5 340.7 93 164 +1958 10 24 6 7 ISAAC 69.3 49.5 125 505 +1987 12 19 0 7 GORDON 8.9 318.9 155 15 +1969 10 3 12 26 LESLIE 21.7 16.1 157 648 +1994 1 6 12 4 PATTY 35.7 26.7 43 142 +1969 4 24 18 21 BERYL 50.1 228.5 60 99 +1963 11 8 0 17 TONY 22.1 7.8 147 456 +1994 2 20 18 28 ALBERTO 66.8 140.1 81 39 +1970 6 9 18 23 ISAAC 60.6 147.4 112 609 +1980 2 6 0 7 BERYL 69.0 130.4 136 588 +1973 2 23 12 19 FLORENCE 24.2 95.3 79 240 +1962 3 25 12 2 GORDON 48.4 270.7 79 296 +1954 11 2 0 19 FLORENCE 42.0 343.2 45 233 +2004 10 10 0 23 TONY 57.5 159.7 119 644 +2002 9 22 0 21 KIRK 55.6 104.7 19 626 +1984 9 13 12 3 KIRK 69.9 15.2 95 39 +1992 11 3 12 4 GORDON 42.5 218.6 61 583 +1957 7 12 6 21 JOYCE 8.2 151.3 159 225 +1997 11 28 12 24 JOYCE 43.1 223.6 10 83 +1959 11 17 6 3 VALERIE 17.5 220.6 20 736 +2002 6 16 6 10 FLORENCE 47.6 337.3 70 847 +1998 4 14 12 8 OSCAR 13.9 347.5 141 421 +1986 3 2 18 14 SANDY 64.0 7.0 83 848 +1996 8 4 0 5 NADINE 47.5 131.4 145 234 +1989 11 28 0 8 ALBERTO 36.4 174.3 83 42 +1959 7 22 0 14 RAFAEL 50.8 191.8 62 769 +1991 5 21 12 9 GORDON 33.1 67.1 75 439 +1963 1 19 12 8 OSCAR 63.6 324.9 38 727 +1981 9 26 6 1 OSCAR 22.8 169.3 65 387 +1955 3 18 0 11 LESLIE 17.8 321.2 13 650 +1969 4 27 0 14 PATTY 39.5 108.2 49 742 +1965 6 11 12 9 MICHAEL 27.7 114.7 41 269 +1954 4 14 0 13 PATTY 33.9 58.1 123 345 +1980 10 4 6 15 ISAAC 12.9 272.9 91 562 +1966 9 20 0 4 ERNESTO 45.2 335.9 126 375 +1984 12 18 18 1 GORDON 62.4 89.0 127 555 +1978 4 1 18 17 DEBBY 34.6 129.9 124 886 +1980 12 8 18 22 ALBERTO 66.0 159.3 156 311 +1995 5 3 6 20 GORDON 31.6 226.2 123 881 +1957 11 16 12 20 JOYCE 68.5 298.6 33 809 +1983 3 23 18 7 GORDON 22.8 147.6 25 861 +1955 8 14 18 8 KIRK 60.7 131.1 132 726 +1983 11 11 0 27 ERNESTO 35.8 169.6 16 605 +1952 5 1 12 6 SANDY 58.1 141.7 158 394 +1995 8 10 12 11 PATTY 29.2 90.0 92 62 +1984 8 25 12 28 ERNESTO 53.9 206.9 12 95 +1985 11 8 12 8 VALERIE 41.3 183.5 73 815 +1953 5 6 0 7 JOYCE 14.4 315.2 125 190 +1971 1 15 6 5 ERNESTO 35.5 288.6 98 777 +2003 4 28 0 6 PATTY 54.8 256.2 11 537 +1964 4 24 0 6 MICHAEL 23.9 61.0 26 796 +1967 12 17 18 21 BERYL 50.0 62.2 124 728 +1964 8 6 0 14 SANDY 12.2 345.0 136 0 +1992 9 14 0 25 TONY 53.3 337.6 122 483 +1988 9 11 12 16 RAFAEL 63.5 73.2 38 718 +1962 12 1 6 25 BERYL 9.8 355.0 127 454 +1965 1 23 6 2 VALERIE 16.2 84.1 108 213 +1969 3 20 0 7 TONY 18.1 314.4 116 640 +1957 9 1 12 4 PATTY 64.3 323.0 105 78 +1997 7 9 18 13 DEBBY 38.1 204.8 118 321 +1988 11 15 6 10 ISAAC 66.8 242.9 113 813 +1995 1 23 18 12 NADINE 23.6 354.4 87 154 +1977 5 6 0 16 KIRK 44.0 128.8 70 821 +1964 7 7 18 5 WILLIAM 63.5 311.9 155 546 +1978 1 20 0 19 ISAAC 25.3 82.2 43 278 +2000 11 7 6 7 SANDY 34.3 223.9 86 890 +1982 1 6 12 11 PATTY 48.6 352.5 79 302 +1994 5 24 6 21 FLORENCE 55.5 90.6 153 697 +1950 10 18 6 7 BERYL 34.3 330.9 148 583 +1961 10 17 0 10 CHRIS 51.9 263.8 73 853 +1991 9 16 0 6 BERYL 31.6 242.0 127 550 +1998 11 5 18 19 VALERIE 41.7 206.9 31 539 +1963 2 16 6 15 GORDON 32.7 20.6 162 669 +1978 6 7 18 8 OSCAR 67.1 27.6 162 201 +1976 7 1 18 13 TONY 38.8 255.2 55 314 +1978 4 15 18 2 MICHAEL 13.2 291.2 154 586 +1965 1 8 18 22 BERYL 47.0 220.2 126 771 +1995 2 12 18 13 CHRIS 33.0 169.3 71 736 +1972 12 22 0 8 RAFAEL 18.8 15.3 18 682 +2003 1 10 0 22 CHRIS 59.5 329.3 64 381 +2003 1 1 6 20 ALBERTO 15.5 272.4 49 309 +1991 11 6 0 21 ISAAC 13.6 322.3 71 501 +1973 9 18 12 19 SANDY 13.2 63.1 57 17 +1965 9 18 6 8 PATTY 16.0 270.1 156 636 +1967 7 19 0 23 MICHAEL 69.4 348.3 121 826 +1962 9 4 6 17 DEBBY 67.9 191.2 143 520 +1977 1 11 12 21 TONY 69.2 317.9 49 766 +1991 6 22 0 16 FLORENCE 25.8 60.5 69 503 +1965 3 19 18 18 HELENE 61.2 208.0 48 671 +1963 4 16 18 17 SANDY 52.4 350.7 129 528 +1998 7 20 12 1 WILLIAM 10.2 139.2 144 674 +1964 2 14 18 16 VALERIE 11.6 310.5 63 738 +1982 12 19 12 18 SANDY 45.6 296.3 131 576 +1997 6 12 6 14 FLORENCE 59.2 296.6 18 646 +1965 11 6 6 9 ERNESTO 17.0 248.5 56 799 +1995 2 13 0 15 KIRK 37.9 6.3 25 229 +1987 12 7 18 21 MICHAEL 13.2 157.3 26 851 +1967 9 14 18 19 LESLIE 12.7 278.5 11 496 +1982 7 12 12 22 SANDY 34.3 112.0 51 345 +1966 3 10 12 1 NADINE 60.4 60.4 16 780 +1975 3 23 6 21 ISAAC 36.6 53.7 65 659 +1960 12 10 6 9 SANDY 25.7 355.0 116 284 +2003 5 22 0 24 JOYCE 36.2 65.1 31 387 +1983 3 13 18 28 LESLIE 61.1 33.1 90 723 +1974 3 4 6 26 OSCAR 40.9 261.5 53 536 +1981 12 19 12 19 NADINE 28.8 330.4 151 559 +1961 3 27 6 22 CHRIS 12.8 165.7 41 225 +1952 7 5 6 21 NADINE 27.2 180.8 27 804 +1976 1 25 18 27 MICHAEL 20.6 160.5 118 215 +1998 10 27 6 14 VALERIE 29.1 251.1 53 237 +1955 9 14 0 1 CHRIS 16.2 240.9 151 238 +2003 9 11 18 22 CHRIS 57.9 342.9 63 477 +1965 12 28 6 22 SANDY 28.5 190.9 41 895 +1973 8 15 0 13 FLORENCE 59.8 134.0 18 821 +1963 4 25 18 9 NADINE 69.6 354.7 147 785 +1968 12 5 0 8 SANDY 57.7 134.0 75 239 +1963 2 10 12 22 VALERIE 23.7 218.5 27 728 +1977 10 5 6 6 ISAAC 56.2 155.8 19 644 +1993 4 5 6 5 ERNESTO 50.9 139.8 49 574 +1982 8 12 0 12 RAFAEL 62.0 158.4 109 709 +1998 5 13 18 28 BERYL 64.2 278.9 129 287 +1970 9 22 0 27 HELENE 32.1 4.5 157 692 +1961 11 9 6 16 NADINE 8.4 302.8 117 269 +1964 2 19 0 18 MICHAEL 29.3 147.2 138 795 +1988 5 2 6 19 HELENE 14.8 60.4 34 695 +1968 11 2 12 5 HELENE 31.3 19.1 10 720 +2002 5 1 0 21 GORDON 57.4 125.9 128 327 +1992 1 3 0 23 PATTY 63.6 326.0 137 748 +1969 4 3 6 14 ISAAC 46.0 166.3 23 508 +1957 1 11 6 14 RAFAEL 10.3 295.3 15 356 +1995 5 23 12 6 GORDON 55.8 320.8 154 19 +1951 11 12 0 1 KIRK 51.6 212.8 10 154 +1979 2 8 6 25 VALERIE 36.4 344.8 139 677 +1995 3 10 6 28 RAFAEL 21.9 0.1 54 149 +1985 8 2 0 11 CHRIS 60.3 279.3 56 424 +2001 8 11 12 12 ISAAC 62.4 302.4 79 175 +1976 8 15 18 24 ISAAC 60.1 193.2 76 279 +1992 3 25 12 16 NADINE 66.7 252.6 103 337 +1962 11 16 18 28 PATTY 69.5 338.3 100 715 +2003 5 23 18 2 DEBBY 25.5 186.9 126 883 +1995 2 13 0 23 FLORENCE 33.2 172.3 163 837 +1989 3 15 18 4 CHRIS 18.6 33.4 127 745 +1956 12 10 18 7 RAFAEL 33.9 10.8 46 784 +2003 12 17 0 9 WILLIAM 56.1 152.7 150 413 +1960 1 11 12 2 ERNESTO 55.4 58.0 51 169 +1996 2 27 18 9 GORDON 40.7 312.6 153 778 +2000 10 9 12 22 KIRK 48.9 202.7 89 459 +1969 7 4 0 20 JOYCE 31.5 261.8 64 300 +1983 8 28 0 8 NADINE 21.1 317.9 113 112 +1997 1 1 18 23 PATTY 10.3 39.3 137 596 +1988 5 13 12 25 WILLIAM 44.3 66.8 53 15 +1985 10 16 18 9 OSCAR 23.0 337.1 151 591 +1987 7 7 0 28 GORDON 47.2 125.3 70 713 +1964 8 13 6 22 WILLIAM 10.1 34.0 100 845 +1989 9 19 6 10 GORDON 8.2 327.8 18 561 +1977 6 24 6 19 CHRIS 18.6 120.1 116 661 +1977 3 27 12 3 RAFAEL 9.8 135.5 152 604 +1986 10 13 12 24 HELENE 7.5 1.3 113 437 +2001 11 22 18 10 DEBBY 68.0 81.6 126 688 +1994 8 24 18 10 TONY 38.4 58.9 46 636 +1961 3 20 0 22 RAFAEL 20.0 191.3 80 382 +2002 8 2 0 10 FLORENCE 36.2 105.9 45 42 +1999 5 16 18 21 GORDON 14.5 331.8 148 874 +2003 5 15 12 5 FLORENCE 27.7 120.5 43 541 +1972 7 16 0 26 CHRIS 20.5 320.9 55 753 +1984 7 24 12 17 CHRIS 27.4 195.0 80 34 +1969 5 9 6 3 BERYL 26.7 221.1 12 427 +1996 10 16 12 24 FLORENCE 65.1 168.0 84 472 +1982 8 10 12 28 RAFAEL 53.1 205.4 51 651 +1976 9 14 6 3 SANDY 65.1 273.3 41 132 +1993 3 5 6 2 GORDON 24.4 157.0 154 593 +1972 12 6 18 28 KIRK 55.5 203.3 73 457 +1985 9 3 6 20 FLORENCE 57.0 207.0 34 632 +1959 7 2 12 17 VALERIE 53.2 53.4 87 363 +1952 2 11 6 10 MICHAEL 53.3 200.3 129 845 +1993 2 10 6 19 SANDY 69.7 12.6 117 484 +1984 4 15 18 8 CHRIS 32.3 345.5 11 835 +1982 3 10 0 12 KIRK 31.7 349.1 32 620 +1986 2 15 0 25 ERNESTO 59.9 20.7 18 42 +1952 3 13 6 8 BERYL 62.2 278.9 53 853 +1955 12 8 18 27 NADINE 19.7 247.6 110 147 +1981 8 21 18 3 FLORENCE 43.2 109.0 154 153 +1965 8 12 12 25 RAFAEL 52.1 238.7 136 502 +1973 4 26 0 18 NADINE 35.1 335.2 37 834 +1963 10 25 12 15 VALERIE 21.2 48.4 29 270 +2002 6 28 0 9 SANDY 9.3 149.4 45 796 +1987 2 15 18 21 TONY 69.9 74.3 95 470 +2003 6 6 12 9 KIRK 38.2 302.4 69 249 +1958 3 7 18 26 PATTY 11.9 79.0 16 593 +1977 2 6 0 19 NADINE 63.1 239.1 134 389 +1987 9 1 18 12 HELENE 41.4 276.9 13 275 +1994 6 25 0 4 PATTY 11.4 93.8 48 419 +1974 6 18 18 10 WILLIAM 10.7 217.3 29 869 +1997 5 25 18 8 NADINE 62.7 163.3 32 598 +1956 5 14 6 12 GORDON 53.9 104.6 136 543 +1997 6 21 6 19 PATTY 55.1 296.6 43 360 +1998 10 23 18 1 ERNESTO 18.8 241.0 94 364 +1953 2 2 12 4 VALERIE 26.6 82.1 129 102 +1971 10 23 12 8 RAFAEL 32.4 161.5 164 301 +1988 6 10 12 9 ISAAC 53.7 185.0 63 617 +1992 5 21 12 2 VALERIE 41.7 241.7 15 228 +1974 4 17 6 28 MICHAEL 36.2 128.9 128 340 +2002 3 2 18 15 ISAAC 9.2 192.0 74 25 +2004 5 13 6 12 RAFAEL 14.2 348.1 31 243 +1972 11 25 6 6 CHRIS 9.0 150.9 160 48 +1964 12 25 6 9 ISAAC 58.0 59.2 110 90 +1974 5 2 18 7 FLORENCE 54.6 274.6 110 768 +1974 6 27 6 9 OSCAR 38.6 131.5 43 339 +1988 3 13 6 5 TONY 27.9 48.2 89 416 +1998 11 8 18 23 NADINE 50.6 226.7 77 804 +1995 9 7 12 15 KIRK 55.7 68.9 87 588 +1951 1 13 6 26 TONY 40.8 346.3 106 188 +1967 2 15 0 4 BERYL 26.1 27.6 93 544 +1977 10 1 6 19 LESLIE 17.5 15.4 82 578 +1986 2 9 0 14 VALERIE 60.8 93.3 158 474 +1978 10 20 6 13 BERYL 27.2 106.1 164 422 +1950 9 17 0 27 HELENE 14.8 351.1 104 638 +1999 10 24 0 21 ERNESTO 43.3 202.5 36 302 +1968 4 9 0 22 LESLIE 63.4 227.0 51 560 +1971 3 1 0 18 KIRK 19.1 334.0 156 599 +1992 5 20 6 14 PATTY 48.6 185.3 149 486 +1999 2 2 0 2 NADINE 18.5 121.1 32 12 +1994 9 19 6 15 VALERIE 46.6 92.2 52 405 +1976 11 8 12 22 ISAAC 64.6 227.7 82 40 +1986 10 6 6 3 CHRIS 53.1 48.5 57 372 +1962 3 19 18 6 BERYL 35.7 310.6 94 400 +1996 1 16 12 7 TONY 24.0 118.2 13 599 +1993 8 5 18 20 ALBERTO 66.8 86.2 85 629 +1981 12 17 6 28 ERNESTO 38.6 255.6 139 843 +1972 3 4 0 27 NADINE 44.9 249.5 138 720 +1954 12 27 6 10 NADINE 25.6 3.7 128 347 +1992 6 26 0 23 KIRK 7.8 317.7 120 193 +1987 11 26 6 22 ISAAC 7.8 209.7 140 256 +1994 12 24 0 3 FLORENCE 32.2 51.9 155 747 +1981 11 18 0 2 JOYCE 57.4 238.9 71 339 +1954 1 19 12 13 DEBBY 41.2 68.8 140 113 +2001 9 28 18 1 PATTY 29.4 151.1 98 828 +1961 4 3 12 7 MICHAEL 44.1 29.7 22 106 +1981 6 20 6 20 ALBERTO 34.0 194.9 62 520 +1988 3 26 12 3 TONY 56.9 56.7 17 828 +1974 6 27 18 14 LESLIE 24.0 25.1 21 650 +1981 5 7 0 19 ERNESTO 15.2 214.4 105 570 +1985 7 9 12 20 FLORENCE 47.9 241.4 122 27 +1966 7 24 6 8 DEBBY 69.7 116.4 46 788 +2003 9 26 18 23 ALBERTO 37.0 57.4 158 690 +1986 7 17 18 12 BERYL 41.0 313.8 72 62 +1958 10 7 6 11 OSCAR 42.0 336.4 23 224 +1960 12 11 6 13 ALBERTO 68.4 311.6 72 144 +1978 4 2 0 13 LESLIE 65.5 198.7 96 610 +1998 2 17 6 8 ERNESTO 57.9 231.3 106 593 +1972 8 20 0 16 KIRK 23.9 149.6 87 416 +1965 1 4 0 6 TONY 54.2 41.1 121 537 +1991 12 12 12 1 JOYCE 11.4 270.4 87 437 +1983 12 7 18 21 PATTY 21.7 81.9 55 28 +1979 7 25 0 26 LESLIE 65.5 263.8 110 237 +1995 9 9 0 24 GORDON 30.3 47.0 29 534 +1953 9 11 12 24 SANDY 67.1 328.1 124 806 +1986 7 13 0 11 LESLIE 31.6 245.4 81 476 +1965 8 3 12 20 DEBBY 60.1 146.9 66 151 +2000 7 22 6 9 LESLIE 48.5 85.5 157 551 +1967 3 9 6 12 WILLIAM 44.6 311.1 10 521 +2000 8 4 0 2 KIRK 42.4 13.0 159 327 +1957 7 16 0 2 GORDON 61.9 25.5 92 145 +2000 10 2 0 22 WILLIAM 45.3 160.5 107 868 +1966 6 23 18 27 NADINE 53.8 47.4 107 468 +2004 7 23 12 12 FLORENCE 20.5 291.6 76 92 +2000 11 26 12 12 ERNESTO 63.8 199.0 42 550 +1956 9 17 0 22 NADINE 24.4 249.3 55 268 +1951 8 7 0 8 HELENE 62.5 158.9 57 137 +1965 11 17 18 7 MICHAEL 45.8 171.1 60 429 +1972 1 24 18 16 SANDY 20.8 62.2 56 497 +1960 9 20 18 26 GORDON 9.4 34.4 41 169 +1968 7 21 18 25 KIRK 37.5 22.6 20 151 +1975 1 20 0 7 RAFAEL 7.7 331.0 105 320 +1958 11 17 18 19 NADINE 39.6 202.5 51 663 +1953 10 18 0 9 ERNESTO 20.2 304.7 34 84 +1988 4 16 0 24 NADINE 16.8 261.7 57 434 +1981 12 1 0 28 LESLIE 43.8 288.1 29 686 +2001 1 5 0 11 KIRK 16.2 123.6 11 480 +1988 6 13 6 15 PATTY 63.3 72.1 116 30 +1953 3 7 12 11 ALBERTO 61.6 200.3 21 301 +1971 3 26 18 27 FLORENCE 53.3 300.8 134 564 +1963 10 25 12 22 MICHAEL 47.7 232.9 78 560 +1950 5 10 18 18 PATTY 24.6 36.1 104 714 +1951 12 16 6 4 CHRIS 26.0 236.8 159 375 +1986 3 10 18 14 PATTY 58.5 173.8 26 30 +2004 3 15 18 8 LESLIE 44.6 142.9 88 279 +1990 3 4 0 5 ISAAC 51.9 217.6 71 24 +1992 10 7 18 7 OSCAR 56.5 254.3 52 489 +1954 10 13 0 7 FLORENCE 35.3 106.6 143 650 +1965 12 12 18 12 ERNESTO 46.6 197.8 40 307 +1960 10 25 0 2 ALBERTO 65.1 22.1 157 724 +1964 11 24 0 18 RAFAEL 15.0 104.9 70 153 +1951 5 15 18 28 CHRIS 24.2 154.7 153 737 +1958 5 27 12 27 MICHAEL 63.4 92.1 28 731 +1976 11 17 12 4 KIRK 51.7 311.4 56 740 +1998 5 11 6 4 ISAAC 31.8 172.4 151 38 +1957 8 23 18 18 RAFAEL 53.0 236.0 87 91 +1970 5 14 12 7 OSCAR 63.8 176.1 164 17 +1960 3 6 0 8 CHRIS 24.3 120.0 98 703 +1971 7 5 12 3 BERYL 57.7 78.3 43 251 +1955 12 3 18 28 RAFAEL 12.6 283.7 143 644 +1950 12 9 12 4 NADINE 69.1 155.0 80 752 +1975 7 28 12 2 SANDY 33.4 210.8 55 566 +1976 11 19 0 12 ISAAC 49.4 291.2 88 885 +1957 3 4 0 1 FLORENCE 40.8 16.7 34 739 +1981 11 19 6 19 PATTY 9.2 213.7 29 401 +1994 11 17 6 1 HELENE 22.9 192.6 16 164 +1967 7 19 18 6 RAFAEL 21.5 85.1 154 883 +1974 2 13 6 12 HELENE 61.1 122.0 47 292 +1994 4 26 6 1 HELENE 53.9 257.9 80 110 +1997 12 12 0 12 VALERIE 38.2 272.5 108 209 +1987 4 17 6 7 PATTY 54.0 288.4 101 516 +1980 4 3 12 24 FLORENCE 10.5 39.9 76 481 +1969 4 5 18 19 WILLIAM 37.7 183.4 94 195 +1969 2 28 12 25 VALERIE 7.0 159.6 35 726 +1997 6 18 6 26 ALBERTO 11.3 12.1 42 466 +1972 7 23 6 25 HELENE 46.2 178.4 24 120 +1951 5 6 12 10 PATTY 24.3 350.3 71 867 +1970 12 6 18 11 ERNESTO 55.8 337.2 60 37 +1966 12 25 12 12 SANDY 33.0 85.2 48 838 +2003 3 27 0 9 SANDY 46.6 117.4 146 729 +1966 10 20 6 2 DEBBY 30.3 258.5 140 217 +1977 6 8 6 26 BERYL 33.2 40.3 120 759 +1968 3 24 6 4 JOYCE 21.7 68.8 160 461 +1984 4 18 12 15 FLORENCE 7.1 223.3 106 606 +1987 11 13 12 5 ISAAC 39.2 151.7 21 820 +1962 2 4 12 28 ALBERTO 26.4 329.8 83 201 +1975 10 25 12 9 HELENE 10.4 158.8 164 842 +1957 4 12 6 20 LESLIE 55.6 157.7 147 178 +2004 1 10 12 14 GORDON 25.6 1.9 102 885 +2001 7 6 6 28 RAFAEL 9.8 324.0 51 1 +1983 2 24 0 14 TONY 42.9 12.0 39 652 +1963 8 20 0 8 WILLIAM 59.5 331.9 97 454 +1960 12 22 6 11 HELENE 66.4 288.9 66 427 +1987 10 24 18 6 CHRIS 41.7 251.2 144 368 +1985 10 16 18 17 LESLIE 32.8 132.8 68 361 +2002 3 17 6 13 OSCAR 65.6 115.5 64 830 +1991 5 7 0 8 OSCAR 66.0 102.1 22 492 +1966 10 28 6 12 ERNESTO 27.8 276.9 130 258 +1979 10 15 0 18 WILLIAM 17.7 236.0 133 666 +1954 5 11 18 28 VALERIE 8.5 136.8 30 602 +1971 2 18 6 8 VALERIE 61.4 2.2 87 679 +2002 9 16 12 22 PATTY 69.2 238.7 94 226 +1987 9 13 12 1 ALBERTO 42.4 318.8 81 795 +1998 12 10 6 25 VALERIE 45.6 122.6 149 493 +1973 4 23 6 7 ERNESTO 18.9 223.2 12 743 +2004 2 3 12 11 ERNESTO 17.4 15.4 84 706 +1979 9 23 12 21 CHRIS 9.2 189.5 30 143 +1951 3 26 6 6 CHRIS 23.5 176.3 117 813 +1979 12 15 18 23 DEBBY 37.8 175.9 122 649 +1981 12 25 12 22 ERNESTO 55.9 308.0 78 303 +1953 5 16 12 20 PATTY 21.6 351.1 153 833 +1984 6 23 0 13 MICHAEL 47.7 144.1 22 629 +1986 1 21 18 7 ERNESTO 63.4 215.8 67 192 +1984 4 6 12 25 ALBERTO 20.1 154.1 161 115 +1967 3 5 12 21 WILLIAM 25.9 214.6 96 551 +1958 1 2 12 3 PATTY 44.0 230.6 63 656 +1953 3 5 0 8 GORDON 40.8 10.3 35 198 +1976 1 20 0 10 PATTY 7.6 238.1 70 478 +1960 7 20 6 3 ALBERTO 28.9 93.1 129 527 +1972 12 2 18 23 LESLIE 12.5 224.0 158 875 +1974 6 10 12 18 VALERIE 31.0 45.6 66 262 +1967 1 3 0 19 VALERIE 29.1 151.5 128 359 +1977 1 26 0 10 ISAAC 49.0 32.8 143 573 +1972 2 4 0 14 TONY 11.3 291.3 118 125 +1981 11 17 18 7 GORDON 8.0 30.6 102 465 +1965 8 17 0 12 MICHAEL 26.4 289.5 67 156 +1986 12 23 18 5 ALBERTO 42.6 182.0 33 677 +1967 6 26 0 2 CHRIS 31.4 249.3 100 529 +1955 1 6 12 18 JOYCE 56.4 164.7 30 498 +1986 1 25 18 26 RAFAEL 22.4 173.1 26 777 +1996 11 19 6 17 BERYL 69.7 104.4 28 206 +1995 10 8 0 6 HELENE 18.7 205.0 45 593 +1978 7 15 6 21 OSCAR 47.8 328.7 118 826 +1987 5 7 6 13 KIRK 42.4 64.6 85 323 +1994 11 19 18 14 VALERIE 51.5 42.4 140 403 +1986 10 12 6 11 HELENE 25.5 206.7 79 146 +2001 5 18 6 16 ERNESTO 12.5 327.2 145 844 +1988 7 19 6 3 OSCAR 7.7 27.9 96 777 +1962 10 21 18 16 DEBBY 43.9 357.2 127 236 +1987 5 3 18 7 KIRK 44.0 186.9 71 548 +1953 7 2 18 22 HELENE 54.9 110.9 115 216 +1998 8 15 18 23 ISAAC 41.6 308.8 20 440 +1972 9 10 12 6 OSCAR 17.5 60.0 59 607 +1986 5 6 18 6 JOYCE 31.7 170.5 112 700 +1983 6 3 6 15 BERYL 54.4 301.1 87 876 +1970 5 2 0 28 VALERIE 33.0 64.3 14 835 +1977 1 24 12 26 WILLIAM 9.3 226.0 102 797 +1956 1 13 12 17 WILLIAM 33.5 76.3 29 161 +1958 4 24 18 25 CHRIS 42.1 272.4 94 98 +1952 9 28 12 5 TONY 58.9 270.4 77 150 +1985 12 6 0 20 RAFAEL 43.4 93.5 17 11 +1981 4 24 12 10 JOYCE 15.8 1.5 114 493 +2004 12 17 18 9 ERNESTO 55.6 113.8 74 748 +1954 6 2 12 19 JOYCE 56.4 177.5 53 579 +1982 4 1 0 8 TONY 41.6 149.7 17 263 +1985 1 26 0 19 WILLIAM 18.3 47.7 79 424 +1965 5 5 12 6 TONY 25.2 291.8 39 782 +1953 6 27 18 4 PATTY 24.2 219.1 99 563 +1974 1 28 12 7 ISAAC 22.7 244.0 18 787 +1957 11 27 6 28 HELENE 7.3 297.9 26 462 +1965 6 5 18 2 ALBERTO 38.8 79.2 154 658 +2000 3 26 6 9 LESLIE 57.7 128.9 26 87 +1985 3 7 0 28 FLORENCE 33.8 313.2 61 276 +1966 7 27 6 9 TONY 38.7 32.0 56 245 +2001 2 12 12 5 SANDY 44.8 327.2 156 405 +1959 12 27 0 3 VALERIE 54.8 233.9 67 813 +1975 6 22 12 22 DEBBY 68.8 9.9 129 684 +1977 9 6 18 21 MICHAEL 66.8 116.0 135 764 +1979 8 13 18 7 ERNESTO 69.7 181.9 151 340 +1951 3 9 18 26 OSCAR 45.4 53.7 92 63 +1977 12 13 12 15 FLORENCE 33.7 159.2 150 656 +1957 2 5 0 16 RAFAEL 22.6 40.5 117 179 +2001 7 28 18 16 VALERIE 14.4 191.3 76 396 +1959 1 17 18 1 ALBERTO 19.4 87.3 111 232 +1965 12 24 6 13 JOYCE 62.1 258.6 34 715 +1956 12 7 18 23 ISAAC 9.2 115.0 58 316 +1977 10 18 6 18 MICHAEL 56.7 120.9 19 63 +1988 6 1 18 10 ISAAC 56.1 253.2 75 717 +1978 1 14 0 5 WILLIAM 8.5 5.6 42 606 +1977 4 27 18 22 CHRIS 34.3 210.7 119 269 +1992 11 1 12 16 LESLIE 50.3 188.2 56 354 +1955 12 19 6 1 VALERIE 41.9 209.2 73 724 +1965 8 13 6 15 WILLIAM 60.2 113.7 50 446 +1971 12 6 12 9 TONY 26.9 187.5 13 591 +1971 11 22 0 28 ISAAC 39.4 91.2 20 359 +1972 8 25 0 23 NADINE 23.8 74.0 49 260 +2000 1 18 12 27 HELENE 61.6 165.9 135 689 +1974 9 26 12 6 KIRK 47.9 95.1 48 547 +1975 3 18 12 26 SANDY 54.2 301.0 133 179 +1999 6 28 0 9 RAFAEL 65.7 255.5 156 657 +1978 7 13 6 21 GORDON 37.1 161.9 78 667 +1954 12 21 6 23 ERNESTO 28.2 159.7 51 249 +1957 6 16 12 24 PATTY 16.9 53.8 138 649 +2000 11 21 0 13 SANDY 49.2 240.8 25 26 +1963 8 4 0 20 BERYL 40.3 133.8 41 128 +1960 1 25 0 24 DEBBY 15.3 357.0 161 703 +1990 11 13 0 7 LESLIE 47.2 157.1 38 636 +1954 3 27 12 16 SANDY 43.5 216.9 104 758 +1982 6 9 18 12 WILLIAM 14.7 192.8 102 664 +2004 8 26 6 22 NADINE 18.4 238.0 122 835 +1952 9 7 0 8 WILLIAM 49.1 332.3 89 885 +1950 1 6 0 16 ISAAC 24.6 20.4 115 421 +1999 11 4 0 23 OSCAR 8.0 184.4 117 379 +1982 12 7 0 19 BERYL 25.4 25.0 16 768 +1981 10 12 0 24 JOYCE 29.2 227.8 132 525 +1991 3 6 6 8 DEBBY 52.8 124.9 24 862 +2002 9 28 6 16 LESLIE 9.4 241.1 155 664 +1996 1 16 0 6 KIRK 10.3 177.1 131 679 +1955 5 22 0 1 TONY 21.6 118.2 158 191 +1980 7 4 18 7 TONY 56.0 47.4 14 88 +1995 9 19 18 27 ERNESTO 34.1 30.4 144 174 +1957 5 19 18 27 TONY 34.1 279.4 127 43 +1979 3 4 18 1 BERYL 41.5 289.3 138 17 +1962 3 16 0 27 PATTY 69.4 192.1 31 352 +1972 11 12 0 17 FLORENCE 60.0 318.3 69 392 +1979 7 26 0 4 ALBERTO 40.8 293.2 15 545 +1957 9 7 6 6 KIRK 64.0 105.1 62 213 +1955 2 6 12 9 TONY 57.8 250.0 159 837 +2000 5 19 0 10 WILLIAM 10.8 49.4 119 454 +1951 3 15 0 4 NADINE 44.7 192.5 68 92 +1999 12 27 0 24 VALERIE 58.8 352.4 21 85 +1982 7 27 6 16 FLORENCE 67.1 350.4 87 649 +1980 12 11 6 6 ISAAC 19.5 35.9 78 200 +1965 9 13 0 12 KIRK 19.5 317.3 81 526 +2003 8 1 6 26 VALERIE 14.1 281.2 39 710 +1996 10 26 0 22 WILLIAM 28.0 126.3 12 368 +1963 8 4 12 19 SANDY 49.8 147.6 110 636 +1995 9 7 6 18 ISAAC 21.8 61.2 53 201 +1954 6 23 12 8 WILLIAM 53.5 13.4 96 9 +1960 1 8 6 26 PATTY 29.1 270.0 81 275 +1987 10 16 6 7 BERYL 33.9 137.5 156 776 +1994 12 22 0 26 HELENE 68.6 73.6 25 470 +1965 10 23 0 2 OSCAR 22.8 87.1 43 79 +1998 8 19 12 21 ERNESTO 51.5 109.7 63 532 +1962 7 4 12 24 PATTY 46.0 41.1 87 584 +1991 9 28 18 7 HELENE 33.8 41.8 76 63 +1999 9 5 0 13 LESLIE 10.2 245.4 50 74 +1976 8 20 12 27 MICHAEL 56.8 28.5 69 154 +1961 11 3 6 16 WILLIAM 8.1 12.1 11 829 +1988 3 15 0 11 ALBERTO 38.6 347.3 135 551 +1964 6 5 18 8 GORDON 32.0 238.9 160 326 +2002 7 15 0 15 SANDY 30.6 323.1 69 723 +1958 3 1 18 6 GORDON 10.5 357.7 124 518 +1965 6 24 6 26 FLORENCE 16.0 165.5 92 845 +1989 8 1 18 12 WILLIAM 27.0 124.5 130 575 +1977 5 16 0 16 MICHAEL 7.5 120.2 97 14 +1963 8 28 18 2 HELENE 54.7 211.4 109 732 +1950 1 7 0 15 WILLIAM 43.4 255.1 145 562 +1964 8 21 12 26 MICHAEL 22.1 336.5 101 467 +1962 11 11 12 20 WILLIAM 43.8 13.8 26 554 +1986 9 18 18 12 OSCAR 61.4 144.9 22 742 +1984 9 4 18 17 JOYCE 36.8 194.8 95 70 +1975 4 24 18 17 ERNESTO 66.2 134.2 77 220 +1985 9 26 6 18 GORDON 47.0 308.1 46 418 +1969 8 13 6 25 ERNESTO 46.8 252.1 118 701 +1992 10 2 18 21 FLORENCE 61.9 115.6 124 3 +1993 9 18 0 20 CHRIS 56.6 257.3 142 413 +1954 8 14 0 2 ERNESTO 12.4 220.9 142 330 +1991 11 19 6 7 KIRK 69.4 308.8 80 335 +1986 12 26 6 3 WILLIAM 45.0 126.6 46 601 +1979 1 6 18 16 ISAAC 35.4 34.9 75 365 +1953 6 6 0 15 FLORENCE 49.2 331.2 159 791 +1992 2 10 12 10 ERNESTO 40.1 53.7 61 194 +1956 7 14 0 11 ALBERTO 57.0 93.2 52 857 +1966 2 12 6 7 WILLIAM 66.8 298.8 43 385 +1967 6 25 0 15 SANDY 58.6 228.7 17 858 +1971 6 12 6 8 ALBERTO 36.8 226.9 110 524 +1950 7 5 6 4 CHRIS 10.8 55.1 108 726 +1955 9 11 0 21 OSCAR 36.6 181.1 81 42 +1980 8 15 0 19 GORDON 58.9 2.4 72 357 +1957 7 11 12 22 WILLIAM 39.1 165.9 55 83 +1973 12 3 18 5 RAFAEL 42.5 272.3 135 700 +1997 9 12 12 9 KIRK 30.6 332.8 156 179 +2002 6 9 18 28 KIRK 52.3 350.7 13 864 +1956 12 24 18 16 NADINE 33.4 345.5 84 7 +1956 10 11 0 23 RAFAEL 52.7 134.9 73 151 +2000 6 19 0 24 NADINE 16.2 60.2 152 819 +1979 7 28 12 10 SANDY 61.8 231.5 152 436 +1981 4 4 0 16 JOYCE 18.9 89.2 160 190 +1954 10 2 18 10 TONY 9.2 322.5 62 231 +1999 6 15 18 3 RAFAEL 49.4 244.8 100 645 +1988 3 5 18 6 ERNESTO 62.5 141.7 50 367 +1961 10 17 0 20 ERNESTO 43.8 173.4 160 367 +1979 9 6 12 3 BERYL 50.5 154.9 59 295 +1962 3 24 12 2 VALERIE 11.4 233.8 150 734 +1988 4 8 6 26 GORDON 68.3 260.1 70 138 +1993 5 18 18 25 PATTY 13.1 335.9 87 806 +1988 8 14 12 25 TONY 45.9 243.4 102 518 +1977 8 1 0 9 OSCAR 60.1 301.7 100 861 +1984 3 10 18 4 ALBERTO 45.8 19.6 87 120 +1959 11 14 6 3 ALBERTO 36.9 278.1 161 511 +1953 11 17 12 23 GORDON 31.2 139.7 32 239 +1975 3 14 0 26 NADINE 34.7 244.6 31 443 +1994 12 19 18 16 BERYL 35.2 90.4 71 838 +1953 4 20 18 25 VALERIE 51.8 105.0 66 15 +1990 7 25 18 8 JOYCE 36.9 266.1 156 458 +1960 7 4 6 22 FLORENCE 14.3 271.0 16 565 +1991 8 23 6 20 BERYL 55.8 26.2 89 709 +1957 8 19 18 8 FLORENCE 25.1 302.2 57 298 +1980 11 4 0 14 GORDON 62.5 103.0 53 215 +1958 4 26 12 25 HELENE 13.6 99.9 156 0 +1976 5 18 0 21 GORDON 7.7 143.9 112 6 +1993 1 4 12 13 WILLIAM 10.7 153.5 98 173 +2002 7 14 18 8 TONY 56.7 351.4 52 38 +1974 2 14 0 11 NADINE 17.6 198.4 12 625 +1976 9 22 6 12 HELENE 62.0 222.6 121 669 +1989 12 5 12 16 GORDON 42.0 24.6 140 699 +1967 7 8 12 2 OSCAR 11.4 128.5 60 97 +1988 10 14 12 2 BERYL 13.5 90.8 93 315 +1970 10 3 0 28 PATTY 50.5 318.2 30 317 +1989 6 28 18 15 GORDON 25.8 245.8 143 685 +1984 10 4 12 14 GORDON 16.3 330.5 139 641 +1962 6 18 18 13 TONY 31.8 333.8 83 159 +2000 1 3 6 19 GORDON 51.4 140.6 14 253 +1990 2 20 0 26 JOYCE 21.1 172.2 98 843 +1964 12 13 0 28 GORDON 14.8 179.9 131 111 +2002 4 21 0 2 WILLIAM 36.2 50.5 161 753 +1995 9 22 0 11 NADINE 36.5 56.9 18 119 +2001 9 8 12 3 BERYL 7.4 310.6 161 585 +1958 6 17 6 23 NADINE 35.7 299.5 56 50 +1979 9 16 0 17 RAFAEL 44.4 36.8 52 22 +1995 10 6 0 16 WILLIAM 21.5 127.3 29 143 +1992 9 8 6 9 JOYCE 65.4 157.1 139 95 +1970 1 13 18 24 ISAAC 31.7 35.1 43 425 +1993 3 22 18 5 ALBERTO 28.0 171.3 64 107 +1997 4 8 0 19 BERYL 69.5 175.9 22 740 +1967 6 9 12 28 SANDY 66.6 166.6 37 390 +1967 1 2 12 14 SANDY 35.7 322.7 88 178 +1973 8 16 12 16 NADINE 67.8 51.9 83 691 +1987 2 22 6 6 RAFAEL 13.0 86.9 64 544 +1997 6 19 12 15 LESLIE 69.7 254.5 55 788 +1982 2 21 6 1 HELENE 27.5 209.2 114 92 +1953 4 18 12 13 WILLIAM 23.4 292.1 70 204 +1995 5 16 18 8 BERYL 40.5 260.8 96 410 +2004 8 6 0 18 HELENE 44.5 233.4 76 801 +1996 7 19 6 24 MICHAEL 34.4 242.5 45 397 +2004 4 12 0 15 DEBBY 19.2 293.6 78 642 +1982 1 16 18 19 DEBBY 9.2 149.6 36 704 +1956 4 22 12 8 DEBBY 62.5 273.6 84 692 +1955 2 12 12 18 OSCAR 44.9 33.5 148 65 +1961 7 3 0 14 SANDY 45.2 49.9 79 510 +1989 9 17 6 4 TONY 12.5 357.2 37 288 +1976 4 9 18 21 RAFAEL 27.4 1.6 92 146 +1964 1 24 6 27 ALBERTO 55.4 333.8 83 718 +1996 2 23 0 3 WILLIAM 64.2 262.3 96 188 +1994 6 5 0 20 ERNESTO 19.5 26.3 19 463 +1978 3 6 6 22 PATTY 58.0 67.8 160 781 +1964 9 13 18 14 KIRK 69.6 25.0 51 738 +1974 1 13 0 15 BERYL 45.8 106.9 155 702 +1955 5 2 6 27 WILLIAM 22.1 97.8 36 362 +1960 1 4 18 5 NADINE 37.0 353.4 11 387 +1984 1 15 6 6 DEBBY 58.8 103.6 22 865 +1992 5 19 6 8 PATTY 33.6 29.4 72 415 +1979 6 25 6 8 FLORENCE 69.8 15.3 152 727 +1968 1 20 6 13 FLORENCE 61.3 63.8 58 28 +2000 7 21 6 22 ALBERTO 16.5 1.3 77 37 +1991 5 2 18 20 DEBBY 63.8 46.1 120 322 +1958 1 7 18 9 CHRIS 56.7 92.1 124 40 +1955 6 7 6 15 LESLIE 58.0 351.4 10 444 +1956 7 10 18 8 DEBBY 28.6 267.6 74 547 +1961 9 19 18 9 TONY 60.9 243.5 75 277 +1999 1 22 0 8 DEBBY 39.9 318.3 54 626 +1977 7 16 6 27 TONY 26.1 216.2 36 820 +1988 1 9 18 6 TONY 56.1 45.7 28 401 +1983 5 11 0 23 ERNESTO 34.8 198.0 120 726 +1980 10 14 12 17 TONY 52.7 7.2 163 608 +1957 9 25 6 15 TONY 15.7 175.8 86 243 +1982 8 4 18 2 ISAAC 35.0 210.7 41 458 +1966 12 3 0 10 ISAAC 7.2 145.1 157 773 +1950 8 18 12 24 SANDY 38.9 222.2 144 613 +1997 3 17 0 22 WILLIAM 38.3 106.6 12 197 +1992 11 7 12 12 SANDY 57.0 129.8 139 422 +1985 2 5 12 20 PATTY 41.8 30.0 89 613 +1977 12 12 12 24 TONY 17.0 143.2 116 127 +1953 4 5 0 16 BERYL 66.8 9.4 112 260 +1965 11 6 0 27 SANDY 20.6 191.3 155 328 +1955 2 4 6 12 MICHAEL 32.3 231.5 152 558 +1996 3 12 0 22 SANDY 22.9 257.8 54 711 +1977 1 16 0 5 SANDY 40.4 201.0 150 114 +1977 4 27 12 16 SANDY 60.1 250.9 63 10 +1990 8 1 0 10 FLORENCE 69.8 178.1 153 255 +1999 11 22 18 15 VALERIE 62.0 245.5 64 78 +1960 2 9 12 10 ERNESTO 51.6 217.5 108 516 +1993 5 17 6 8 KIRK 59.0 345.1 153 537 +2003 9 20 0 13 TONY 68.3 102.7 15 617 +1953 8 7 6 8 MICHAEL 49.7 198.2 99 773 +1967 8 6 12 17 DEBBY 35.5 170.9 45 320 +1959 4 11 12 2 SANDY 24.6 33.8 61 228 +1994 10 7 12 8 GORDON 37.6 12.6 24 744 +1965 9 26 6 12 PATTY 29.1 191.2 71 351 +1980 12 19 12 5 LESLIE 35.5 310.2 94 731 +1961 4 6 18 9 ALBERTO 52.3 100.2 103 438 +1969 9 28 6 5 VALERIE 13.8 344.7 18 506 +1964 12 12 12 18 MICHAEL 58.4 263.8 38 601 +1977 8 3 0 14 ISAAC 16.1 305.2 96 237 +1986 8 24 12 27 PATTY 37.5 69.5 131 540 +1992 1 13 18 9 MICHAEL 43.7 345.8 42 496 +1973 12 26 18 2 KIRK 9.2 267.6 108 49 +1990 6 14 0 26 NADINE 26.3 344.1 72 288 +1950 7 6 0 17 BERYL 65.6 192.3 110 683 +2004 8 18 6 28 BERYL 38.3 224.1 164 535 +1988 1 15 18 26 ALBERTO 32.4 286.0 94 534 +1955 5 25 12 7 DEBBY 32.7 253.7 105 817 +1961 6 14 6 9 FLORENCE 25.8 347.2 23 591 +2002 2 6 0 15 OSCAR 51.9 204.3 65 207 +1971 10 1 18 24 TONY 49.1 83.9 123 144 +1977 2 24 18 20 VALERIE 38.5 333.5 96 649 +1976 10 24 6 1 GORDON 17.6 269.7 142 807 +1986 9 19 12 26 OSCAR 28.9 261.5 100 543 +1953 2 26 18 14 GORDON 17.8 66.7 160 556 +1959 4 19 6 16 TONY 57.3 153.4 138 752 +1970 2 13 0 12 SANDY 60.7 184.4 18 698 +1952 11 25 0 14 OSCAR 54.3 134.9 132 701 +1978 2 11 0 21 MICHAEL 34.5 201.9 57 618 +1974 10 26 0 14 FLORENCE 59.8 300.7 67 130 +1956 12 2 18 19 ERNESTO 42.0 252.5 143 712 +1988 10 6 0 3 VALERIE 58.8 137.2 87 877 +1952 6 7 18 12 OSCAR 38.4 223.1 133 65 +1981 2 2 6 25 RAFAEL 16.7 128.2 150 108 +1956 9 3 0 21 SANDY 30.0 17.1 71 837 +1984 12 11 18 10 FLORENCE 28.9 339.4 46 279 +1968 9 25 6 23 WILLIAM 45.9 22.8 55 723 +1969 9 7 6 8 BERYL 58.4 33.6 135 256 +1951 9 8 12 15 PATTY 12.0 313.9 158 625 +1983 12 17 12 3 SANDY 36.3 229.6 122 75 +1976 1 11 12 9 GORDON 28.6 63.2 147 719 +1999 11 21 18 13 NADINE 21.8 199.1 65 119 +1960 9 6 0 21 FLORENCE 67.1 145.0 16 96 +1981 2 28 6 24 BERYL 13.8 309.2 78 367 +1988 1 9 6 10 VALERIE 12.8 31.9 24 375 +1969 11 16 6 9 VALERIE 42.1 6.7 151 161 +1984 6 25 0 11 MICHAEL 17.1 139.5 138 65 +1957 8 8 12 18 MICHAEL 25.2 347.9 82 277 +1972 9 6 0 14 ALBERTO 28.1 206.1 34 446 +1991 8 9 0 16 TONY 50.3 9.3 157 248 +1984 12 23 0 9 ERNESTO 26.5 353.6 94 75 +1964 8 27 12 5 KIRK 22.1 147.9 164 432 +1991 4 24 18 21 SANDY 30.7 353.5 75 95 +1989 3 22 0 15 DEBBY 12.2 288.7 126 234 +1991 11 5 18 20 VALERIE 53.5 67.7 23 698 +1978 12 11 12 25 KIRK 67.6 341.0 138 563 +1965 11 20 18 28 PATTY 64.9 15.0 29 883 +1977 6 28 6 5 DEBBY 42.9 243.4 131 290 +1973 11 22 0 13 TONY 37.8 233.0 23 569 +1979 2 15 18 16 KIRK 68.7 316.6 150 284 +1969 11 8 6 16 GORDON 28.1 118.4 50 750 +1969 4 28 12 10 JOYCE 47.5 311.4 138 612 +1984 3 23 6 28 LESLIE 59.7 228.0 158 592 +1981 3 16 0 15 JOYCE 21.3 347.0 133 759 +2002 4 13 18 26 TONY 13.4 334.6 119 625 +1984 6 8 0 12 PATTY 46.1 5.8 58 0 +1965 9 19 18 8 CHRIS 48.5 5.0 66 187 +1951 12 2 0 17 PATTY 12.5 172.4 34 53 +1999 9 7 6 4 TONY 20.4 168.6 75 287 +2004 2 5 6 16 JOYCE 31.6 133.5 122 324 +1958 7 25 6 20 NADINE 12.9 228.7 36 547 +1982 1 12 12 25 SANDY 64.6 176.3 130 272 +1970 9 10 12 19 PATTY 28.9 79.1 138 380 +1965 10 16 12 16 MICHAEL 37.4 57.0 93 407 +1985 5 22 0 7 MICHAEL 66.9 317.8 50 531 +1965 9 1 12 7 MICHAEL 40.0 56.8 61 491 +1959 4 28 18 25 HELENE 62.5 230.3 162 808 +1954 4 1 6 26 CHRIS 39.7 277.1 48 542 +1954 7 3 18 8 NADINE 65.2 224.7 146 604 +1987 9 17 6 25 WILLIAM 45.3 259.2 136 392 +2004 3 18 0 4 PATTY 45.8 239.2 62 74 +1997 12 7 12 21 VALERIE 15.5 87.8 93 749 +1956 4 14 6 10 TONY 35.7 52.9 113 813 +1967 10 16 18 3 LESLIE 56.3 167.2 78 227 +1958 2 8 6 1 TONY 17.8 300.3 29 65 +1952 11 4 6 10 HELENE 17.3 318.8 36 344 +1998 10 21 0 2 FLORENCE 18.3 236.6 116 817 +1990 5 17 0 4 NADINE 64.4 294.8 92 51 +1954 10 1 0 23 NADINE 33.9 326.3 118 431 +1971 12 5 0 19 WILLIAM 41.0 314.7 126 69 +1980 12 25 0 12 WILLIAM 43.4 75.7 163 587 +1991 2 16 18 15 LESLIE 38.5 173.7 143 487 +1961 5 26 12 18 FLORENCE 9.4 164.9 152 245 +1992 1 15 0 17 KIRK 7.5 311.4 17 825 +1974 3 24 12 13 ALBERTO 15.1 146.3 81 763 +2001 3 16 6 18 VALERIE 20.9 345.1 93 375 +1997 5 2 18 23 KIRK 35.1 114.3 49 28 +1959 5 14 0 28 ISAAC 64.8 337.1 16 311 +1982 12 8 0 9 ALBERTO 39.1 316.9 163 514 +1973 12 23 12 24 MICHAEL 52.8 136.6 145 795 +1983 1 11 6 4 WILLIAM 9.9 203.6 123 353 +1972 6 9 18 3 HELENE 50.2 348.6 145 333 +1978 7 19 0 27 FLORENCE 35.1 69.9 18 862 +1958 3 12 0 23 LESLIE 30.7 187.0 86 751 +1956 12 24 18 28 WILLIAM 49.7 86.7 78 694 +1982 7 1 0 9 KIRK 22.4 165.7 22 283 +1957 10 5 18 16 HELENE 55.2 348.0 59 571 +1972 12 27 0 10 LESLIE 67.0 308.8 64 8 +1983 7 8 12 9 LESLIE 67.0 76.0 87 856 +1986 4 6 0 1 KIRK 33.6 230.5 140 757 +1996 9 13 18 8 RAFAEL 46.2 281.0 74 169 +2000 1 8 18 23 TONY 46.6 127.1 94 195 +1961 6 25 6 4 ERNESTO 40.2 285.9 156 184 +1994 11 13 18 18 ERNESTO 7.0 344.5 159 390 +1970 4 1 12 21 SANDY 10.3 244.0 140 219 +1986 3 3 18 22 FLORENCE 62.1 139.6 98 656 +1992 11 8 18 22 LESLIE 54.4 27.8 49 605 +1978 12 4 6 2 ERNESTO 47.5 342.9 65 357 +2002 11 1 18 19 JOYCE 34.1 244.4 48 581 +2000 4 10 12 11 RAFAEL 32.9 340.1 56 331 +1957 5 4 6 28 SANDY 14.3 56.5 164 95 +1954 10 2 0 17 JOYCE 58.3 44.3 105 68 +1957 4 12 18 27 WILLIAM 69.0 49.5 94 255 +1975 7 15 0 21 ERNESTO 50.0 267.0 64 486 +1952 6 16 6 4 MICHAEL 54.6 72.1 50 93 +2002 4 1 12 10 HELENE 9.8 333.7 65 588 +1976 6 9 18 14 GORDON 9.6 210.5 146 338 +1950 3 19 18 3 HELENE 31.8 143.0 58 410 +1950 6 4 6 14 PATTY 31.2 212.2 50 563 +1985 1 25 6 18 RAFAEL 67.1 52.6 100 354 +1993 10 13 6 26 BERYL 67.4 302.0 17 31 +1951 6 18 12 7 KIRK 32.5 357.2 130 505 +1951 6 12 18 15 ERNESTO 7.3 152.0 148 770 +1996 1 26 18 20 FLORENCE 21.1 304.1 107 709 +1984 5 23 18 23 JOYCE 68.4 161.5 19 351 +1959 4 3 0 26 SANDY 51.1 242.3 84 653 +1998 6 22 0 18 JOYCE 42.0 292.8 57 431 +1979 1 6 0 8 NADINE 39.9 68.9 96 635 +2003 5 28 6 17 CHRIS 55.8 275.3 128 241 +2001 12 15 6 15 OSCAR 64.4 238.5 33 777 +1958 9 4 6 23 OSCAR 12.6 137.5 55 618 +1986 11 5 6 3 FLORENCE 33.4 69.4 114 67 +1974 9 9 0 26 OSCAR 62.0 1.8 119 243 +1986 8 10 18 24 DEBBY 58.8 160.2 65 432 +1969 10 16 0 26 RAFAEL 10.0 277.4 123 764 +1992 11 18 6 19 SANDY 23.3 176.3 105 205 +1998 9 15 0 6 JOYCE 56.2 157.6 156 539 +1967 4 4 18 7 RAFAEL 30.4 39.4 142 468 +1998 5 17 6 19 BERYL 8.0 159.5 60 144 +1985 2 9 12 10 TONY 56.1 17.6 158 29 +1955 12 28 6 28 ERNESTO 23.2 307.6 114 457 +1951 8 27 18 16 GORDON 55.7 331.0 23 396 +1961 9 14 12 22 WILLIAM 38.5 330.0 69 135 +1997 5 19 0 2 GORDON 17.2 125.1 55 333 +1980 2 22 6 17 DEBBY 54.6 215.6 108 210 +1994 7 8 18 25 BERYL 18.7 103.9 90 383 +1960 12 14 0 27 VALERIE 69.9 55.8 159 480 +1969 5 21 0 24 OSCAR 11.7 342.1 107 729 +1988 4 19 0 12 OSCAR 31.9 329.8 20 5 +1953 8 23 12 10 MICHAEL 7.5 110.1 73 487 +1978 7 26 6 28 NADINE 65.2 140.6 84 822 +1990 10 21 18 10 HELENE 63.8 331.3 110 186 +1961 8 24 18 18 JOYCE 22.9 186.6 34 417 +1960 6 20 6 26 LESLIE 15.4 164.0 67 387 +2003 11 20 12 6 RAFAEL 60.9 300.6 52 809 +1994 2 20 6 14 KIRK 63.1 135.8 137 225 +1969 8 16 12 19 RAFAEL 15.8 147.8 42 844 +2002 7 26 6 26 VALERIE 58.5 332.6 100 707 +1966 9 3 0 7 KIRK 54.0 288.3 39 741 +1967 10 9 18 26 WILLIAM 22.8 58.2 73 677 +2000 3 19 18 1 RAFAEL 42.3 257.7 105 77 +1993 10 20 12 14 MICHAEL 10.6 303.9 127 317 +1986 2 4 12 11 RAFAEL 30.1 87.5 84 677 +1992 7 18 0 20 KIRK 53.8 117.4 126 849 +1979 6 8 18 10 NADINE 60.0 230.1 116 568 +1983 5 17 18 11 WILLIAM 58.0 52.6 123 149 +1970 10 9 18 3 SANDY 7.3 158.5 34 127 +1982 6 19 12 5 FLORENCE 47.4 94.4 31 714 +1996 8 26 6 10 ALBERTO 65.6 38.2 111 412 +1976 2 15 12 1 GORDON 24.2 222.8 76 473 +1960 6 9 18 1 SANDY 63.9 51.3 28 762 +1996 7 16 6 17 FLORENCE 26.9 161.1 91 777 +1955 8 15 0 4 ALBERTO 61.4 49.4 43 457 +2002 8 17 6 23 PATTY 22.4 240.9 113 802 +1996 12 27 0 16 KIRK 42.7 278.4 40 757 +1976 5 25 6 14 NADINE 41.6 291.6 129 651 +1976 6 25 12 5 LESLIE 53.9 8.1 17 689 +1986 5 21 6 17 DEBBY 25.8 195.2 58 832 +1986 5 6 12 5 PATTY 37.9 33.5 156 207 +1993 12 15 12 11 MICHAEL 18.0 138.6 124 678 +2004 1 23 18 12 GORDON 10.9 138.9 71 740 +1955 12 5 18 26 MICHAEL 28.0 44.6 76 456 +1990 1 18 0 25 NADINE 62.0 220.2 120 59 +1998 9 23 0 2 LESLIE 65.3 97.8 53 612 +1988 7 22 0 8 MICHAEL 48.4 177.5 91 710 +1981 1 7 12 6 VALERIE 59.2 0.3 158 739 +2004 6 5 12 6 ERNESTO 8.6 199.5 23 352 +1978 6 23 18 4 SANDY 60.7 94.8 105 373 +1963 1 23 0 21 VALERIE 43.6 44.9 94 9 +1981 9 26 6 5 DEBBY 28.9 72.3 118 773 +1956 11 24 0 22 RAFAEL 52.5 119.6 96 639 +1958 5 19 0 1 VALERIE 35.6 115.8 132 289 +1962 11 12 6 14 ISAAC 52.2 166.3 55 64 +1990 3 24 18 15 MICHAEL 66.7 57.7 110 323 +1960 4 16 12 11 MICHAEL 7.9 191.5 77 407 +1967 11 21 12 9 RAFAEL 10.8 113.6 110 418 +1971 7 13 6 8 FLORENCE 63.0 99.1 164 75 +1964 12 14 0 12 ISAAC 8.3 215.0 52 594 +1956 5 27 0 7 KIRK 17.7 19.1 93 480 +1991 10 26 6 21 ERNESTO 40.7 282.2 127 199 +1992 4 7 0 20 MICHAEL 22.4 154.3 119 826 +2004 10 6 0 16 HELENE 38.4 101.4 77 135 +1973 3 20 18 1 PATTY 66.5 256.3 20 57 +1956 1 22 6 5 WILLIAM 61.4 254.9 42 321 +1986 1 6 12 23 VALERIE 14.4 210.6 85 464 +1994 12 15 12 14 GORDON 62.5 10.7 136 724 +1977 8 13 18 17 MICHAEL 17.6 99.8 40 649 +1961 8 23 18 8 NADINE 24.0 302.5 51 175 +1983 9 19 6 14 NADINE 64.7 44.0 55 146 +1984 2 22 6 24 GORDON 56.3 92.9 83 633 +1954 6 21 12 24 FLORENCE 54.9 256.2 161 615 +1980 1 6 18 7 GORDON 8.3 149.2 73 494 +1979 8 26 0 21 ISAAC 33.6 162.8 154 243 +1956 9 1 6 17 ISAAC 19.3 196.7 33 24 +1980 12 28 18 3 VALERIE 50.6 129.2 53 267 +1971 7 28 12 9 DEBBY 24.1 100.8 128 750 +1957 2 14 6 24 ALBERTO 17.2 312.7 47 145 +1960 8 22 0 6 MICHAEL 18.4 356.1 113 796 +1959 11 24 6 1 CHRIS 59.5 354.2 148 437 +1950 3 16 12 4 CHRIS 55.3 356.4 55 293 +1960 4 21 18 2 BERYL 48.8 116.6 156 344 +1998 11 8 6 16 TONY 49.1 309.7 120 234 +1956 2 28 12 15 RAFAEL 44.8 263.7 142 280 +1981 8 26 12 3 MICHAEL 46.7 31.0 143 278 +1971 1 6 6 10 KIRK 29.4 95.2 84 399 +1996 3 2 6 20 WILLIAM 48.0 73.6 162 887 +1983 2 17 6 7 SANDY 65.0 30.6 85 203 +1984 10 12 6 24 ISAAC 62.2 238.7 156 551 +1967 5 25 0 16 ISAAC 55.3 350.4 151 747 +1981 12 20 18 25 BERYL 49.4 256.3 42 401 +1984 12 24 6 26 BERYL 52.3 87.1 116 372 +1995 5 11 6 9 DEBBY 23.9 191.2 72 677 +1986 5 14 12 3 TONY 61.8 4.6 68 367 +1958 9 9 12 14 VALERIE 53.1 203.8 126 665 +1960 8 20 0 11 HELENE 20.7 66.1 35 510 +1976 2 14 0 9 ERNESTO 51.0 292.4 84 123 +2001 10 22 12 7 MICHAEL 51.3 255.7 84 634 +1990 11 2 18 22 WILLIAM 31.5 148.2 114 768 +1984 12 18 12 24 ISAAC 47.0 204.6 160 152 +1987 8 23 18 23 FLORENCE 7.1 142.5 112 95 +1962 6 19 6 13 PATTY 20.0 153.1 117 552 +1973 10 2 6 26 LESLIE 42.9 281.6 97 517 +1966 11 23 6 25 LESLIE 18.7 65.2 18 352 +1971 1 10 6 8 ERNESTO 34.3 92.3 51 55 +1960 3 17 6 19 OSCAR 53.1 162.5 30 879 +1993 4 21 12 23 KIRK 66.0 343.2 138 114 +1951 9 17 6 4 HELENE 43.4 344.7 34 172 +1966 10 19 18 23 ISAAC 35.1 304.4 162 810 +1968 9 25 6 16 PATTY 33.6 224.8 102 279 +1979 10 13 12 18 FLORENCE 61.4 17.4 52 775 +2003 1 28 12 4 CHRIS 12.2 174.7 11 750 +1966 10 6 6 18 VALERIE 28.4 348.6 146 780 +1962 7 27 6 24 DEBBY 61.4 167.9 66 232 +1973 10 23 0 27 OSCAR 9.0 8.6 163 843 +2004 5 21 18 10 DEBBY 20.5 290.2 99 193 +1955 3 28 18 18 RAFAEL 40.9 316.3 74 734 +1964 2 15 0 25 ALBERTO 45.7 191.8 30 72 +1977 7 14 0 1 CHRIS 56.6 177.6 121 446 +1978 9 6 0 3 MICHAEL 9.1 199.3 138 641 +1971 8 3 12 11 CHRIS 51.2 182.1 50 404 +1968 12 15 18 5 WILLIAM 22.4 269.3 101 809 +1996 7 26 6 24 ERNESTO 48.6 82.2 70 558 +2004 3 4 12 18 DEBBY 22.1 151.7 86 791 +1954 4 28 12 11 ALBERTO 57.4 128.0 43 52 +1958 10 3 18 23 LESLIE 24.9 104.1 120 737 +2004 9 17 0 5 PATTY 37.7 342.5 39 484 +1950 6 19 12 12 ISAAC 23.1 307.0 120 57 +2002 4 2 0 17 SANDY 7.2 306.0 40 23 +2001 5 27 18 15 JOYCE 41.7 107.7 12 400 +1963 10 7 12 3 DEBBY 67.3 91.3 142 827 +1990 6 18 12 20 RAFAEL 64.7 283.9 119 245 +1973 12 6 0 18 SANDY 48.5 140.1 156 878 +1993 7 10 0 4 OSCAR 58.2 325.9 104 460 +1960 7 6 12 27 NADINE 60.4 341.4 113 200 +1953 2 2 0 28 SANDY 47.5 96.6 106 533 +1986 6 17 0 7 BERYL 11.7 256.0 81 45 +1968 1 3 12 18 NADINE 48.0 54.5 103 27 +1993 4 25 12 20 LESLIE 57.3 132.7 131 440 +1970 5 10 0 23 GORDON 69.9 115.5 154 882 +1984 2 12 0 21 VALERIE 48.1 100.0 57 807 +1977 2 22 12 22 TONY 42.1 124.5 121 798 +1956 12 4 18 8 NADINE 39.3 276.8 83 607 +1997 11 8 6 10 ERNESTO 23.0 254.9 129 575 +1966 8 14 18 4 NADINE 11.8 299.0 40 188 +1976 6 24 0 15 WILLIAM 60.0 217.2 55 261 +2000 6 8 12 20 FLORENCE 17.3 102.1 109 713 +1988 11 27 12 4 ALBERTO 53.1 34.4 124 460 +1990 6 21 18 24 NADINE 40.3 100.0 72 238 +1996 7 17 6 26 CHRIS 59.7 230.0 35 554 +1960 8 16 0 10 OSCAR 53.2 212.6 153 305 +1993 9 1 0 20 OSCAR 27.2 212.9 97 833 +1981 2 4 18 10 LESLIE 55.9 275.4 161 256 +1983 2 10 0 3 TONY 58.0 273.9 143 268 +1993 12 15 18 14 NADINE 32.4 201.1 47 403 +1995 10 27 12 7 RAFAEL 10.5 201.8 153 161 +1998 3 2 18 5 NADINE 37.0 342.0 100 686 +1961 8 12 18 4 OSCAR 61.2 107.3 104 527 +1966 7 21 18 7 LESLIE 44.3 220.5 160 550 +1995 11 19 6 5 NADINE 28.0 306.4 162 351 +1963 9 2 18 2 OSCAR 66.6 132.7 84 314 +1970 9 19 12 3 FLORENCE 50.2 174.5 109 668 +1951 7 19 0 26 WILLIAM 64.5 221.3 140 460 +1970 3 6 12 22 RAFAEL 8.2 112.5 49 14 +1960 12 13 6 3 GORDON 51.4 42.7 61 875 +1974 2 24 12 7 RAFAEL 39.0 27.0 142 787 +1951 1 21 0 16 KIRK 15.4 246.1 101 512 +1966 3 7 6 6 VALERIE 36.3 194.4 78 622 +1986 9 12 0 1 DEBBY 53.5 212.2 135 293 +1962 8 19 6 12 SANDY 68.5 212.0 119 319 +1957 8 16 18 24 MICHAEL 13.8 150.7 138 250 +1990 3 19 6 3 JOYCE 40.0 80.5 163 113 +1989 12 20 12 19 CHRIS 16.5 299.6 148 565 +2001 12 24 0 17 DEBBY 45.6 227.6 144 847 +1970 11 16 6 24 ALBERTO 45.6 44.7 137 94 +1979 7 25 0 12 ALBERTO 63.3 26.3 38 20 +1962 6 20 0 10 DEBBY 35.0 301.6 35 668 +1996 12 4 0 13 BERYL 31.3 357.8 44 82 +1988 6 5 18 7 HELENE 67.1 68.4 162 465 +1966 3 19 18 6 CHRIS 65.3 159.8 140 71 +1972 4 28 12 27 NADINE 66.0 92.1 160 755 +1993 1 14 0 8 SANDY 52.7 111.8 29 878 +1967 4 20 12 3 LESLIE 46.5 138.1 19 774 +1960 10 28 0 11 ISAAC 62.4 89.6 73 380 +1954 2 17 6 14 RAFAEL 7.3 92.0 39 825 +1972 6 27 0 23 OSCAR 31.5 175.5 110 58 +1992 11 10 18 16 FLORENCE 68.1 30.1 88 439 +1979 5 17 12 9 WILLIAM 28.7 247.6 11 92 +1978 3 23 0 8 KIRK 61.3 180.4 71 763 +1988 4 23 6 16 DEBBY 18.1 77.3 149 583 +1977 9 20 18 3 MICHAEL 57.1 267.7 132 784 +1991 2 3 18 5 ISAAC 28.7 298.3 121 853 +1968 7 24 6 28 HELENE 34.3 131.6 108 451 +1954 12 7 18 21 RAFAEL 31.1 30.6 40 606 +1954 1 19 12 25 TONY 37.4 81.1 104 724 +1995 10 26 0 25 CHRIS 68.1 270.5 12 553 +1955 7 1 12 5 FLORENCE 50.3 353.9 11 836 +1961 12 28 18 11 JOYCE 23.5 56.9 58 205 +1981 3 17 18 9 KIRK 27.1 213.7 92 613 +2004 1 27 18 24 KIRK 38.1 109.2 46 643 +1994 12 21 12 17 CHRIS 30.4 148.3 49 445 +1990 11 18 12 3 BERYL 42.7 80.5 157 831 +1973 1 13 6 27 RAFAEL 37.8 29.0 36 456 +1987 5 4 0 12 LESLIE 57.2 181.9 161 290 +2003 8 21 18 3 BERYL 55.1 297.3 22 863 +1961 1 27 0 22 NADINE 33.3 55.0 122 168 +1989 7 18 6 5 DEBBY 68.9 286.7 136 518 +1982 7 25 6 18 ISAAC 16.3 29.0 79 590 +1980 3 28 18 11 HELENE 60.5 338.2 149 511 +1955 8 7 0 15 WILLIAM 9.9 357.2 126 313 +1985 12 23 0 3 NADINE 12.0 336.4 32 372 +1967 7 4 6 11 ERNESTO 25.6 139.2 88 26 +1990 7 1 0 18 JOYCE 23.5 351.2 21 157 +1988 1 27 6 23 ERNESTO 33.5 302.3 107 262 +1951 12 10 0 19 WILLIAM 36.9 271.7 104 436 +2004 5 25 12 24 ERNESTO 53.1 229.4 110 328 +1957 3 10 18 24 MICHAEL 34.0 154.4 135 822 +1980 8 22 18 23 ISAAC 31.8 80.8 112 868 +1968 4 24 18 14 SANDY 58.7 301.7 116 812 +1983 11 21 6 15 ISAAC 41.9 20.1 42 62 +1992 6 8 12 6 TONY 34.1 148.6 164 243 +1980 6 9 12 2 SANDY 41.1 285.4 55 89 +1968 8 25 0 13 LESLIE 32.3 35.0 101 177 +1957 10 17 6 3 LESLIE 34.2 23.6 57 368 +2001 4 16 12 15 GORDON 55.9 277.8 28 797 +1964 5 20 6 18 ALBERTO 66.7 116.5 37 482 +1958 8 10 18 6 NADINE 57.4 206.4 33 720 +1985 6 4 12 5 OSCAR 59.5 62.1 101 79 +1951 2 17 6 16 PATTY 55.6 44.7 131 843 +1986 6 16 12 1 VALERIE 34.2 179.5 116 774 +1988 12 9 6 15 ISAAC 25.1 282.6 107 259 +1976 2 3 12 16 RAFAEL 55.3 269.6 106 525 +1950 4 7 18 18 VALERIE 66.7 111.2 99 156 +1978 6 9 0 3 ALBERTO 69.1 43.9 128 150 +1983 8 2 12 25 TONY 32.7 155.1 60 686 +1950 6 7 12 3 LESLIE 12.9 31.6 44 103 +1987 10 7 12 19 DEBBY 16.4 248.6 162 538 +1977 7 16 6 5 PATTY 24.1 321.5 20 76 +1973 10 15 12 28 ALBERTO 15.3 52.9 15 729 +1988 2 21 6 8 FLORENCE 32.7 46.2 20 517 +1999 12 7 0 10 SANDY 69.7 152.2 20 65 +1974 12 20 12 20 BERYL 38.0 194.2 145 209 +1980 3 16 12 5 PATTY 24.6 58.9 80 771 +1958 4 10 0 18 GORDON 24.8 157.1 114 500 +1991 7 19 18 14 BERYL 7.8 251.7 24 380 +1955 2 20 6 12 VALERIE 59.5 189.1 88 766 +1978 8 16 6 9 WILLIAM 34.5 34.6 135 862 +1994 7 2 6 3 PATTY 45.2 331.9 58 588 +2003 7 22 18 12 FLORENCE 67.5 169.7 132 235 +1998 8 22 0 12 ERNESTO 61.0 241.7 132 435 +1997 9 13 0 10 DEBBY 17.2 280.3 157 259 +1962 6 16 0 7 VALERIE 42.4 105.4 105 170 +1971 2 5 6 10 SANDY 33.6 357.4 68 136 +1977 11 13 12 21 GORDON 49.7 300.2 120 690 +1972 7 10 0 16 ISAAC 22.0 15.3 114 711 +1975 7 21 6 3 GORDON 64.0 345.1 76 883 +1986 6 22 0 23 VALERIE 28.6 45.7 108 388 +1970 3 13 6 21 SANDY 27.3 272.2 76 250 +1966 1 28 6 19 HELENE 28.3 170.4 141 263 +1995 11 15 12 15 LESLIE 68.8 144.7 157 892 +1971 5 23 6 9 NADINE 59.6 56.6 136 676 +1984 6 19 12 24 WILLIAM 57.3 165.0 144 417 +1982 9 20 12 4 LESLIE 20.0 327.4 90 375 +1999 6 7 0 21 BERYL 43.2 19.5 135 710 +1974 7 19 0 19 HELENE 46.0 350.6 36 476 +2000 5 5 18 2 PATTY 55.2 151.3 113 851 +1975 6 6 6 25 HELENE 18.4 247.5 96 505 +1952 3 6 12 28 GORDON 49.2 82.7 139 501 +1993 9 14 18 14 RAFAEL 32.4 197.5 164 275 +1994 5 28 0 27 RAFAEL 29.4 296.7 129 245 +1962 8 9 18 3 GORDON 62.7 286.6 151 871 +1989 1 8 18 5 SANDY 31.0 184.2 93 718 +2002 12 3 18 16 WILLIAM 69.1 93.5 97 345 +2000 6 8 6 12 BERYL 11.4 72.3 102 370 +1978 9 8 0 11 ERNESTO 43.6 274.8 136 527 +1998 12 2 18 17 JOYCE 58.1 76.0 94 851 +1965 1 7 18 20 NADINE 67.4 17.4 72 751 +1973 10 12 0 19 ISAAC 46.0 73.2 59 273 +1992 10 5 12 9 OSCAR 62.3 229.5 107 843 +1987 2 7 12 10 MICHAEL 53.3 72.5 142 732 +1960 3 11 0 27 ERNESTO 47.5 106.9 89 345 +1985 9 23 0 12 VALERIE 10.0 120.6 11 430 +1966 12 17 6 9 DEBBY 38.8 158.3 48 119 +1954 1 17 0 2 TONY 46.6 337.6 145 370 +1951 7 3 18 1 TONY 58.2 138.7 50 880 +1983 2 19 0 26 VALERIE 11.5 239.2 13 658 +1990 6 2 6 2 LESLIE 27.0 188.8 16 742 +2001 4 6 12 17 MICHAEL 51.8 21.1 12 202 +1987 8 12 18 27 HELENE 40.2 323.7 40 874 +1962 5 10 6 19 PATTY 65.6 211.5 61 80 +1993 7 9 12 24 KIRK 11.5 227.7 159 53 +1975 10 10 0 17 ALBERTO 44.5 74.5 58 13 +1996 4 3 18 24 BERYL 50.9 37.4 159 278 +1957 1 28 12 1 OSCAR 34.6 223.7 158 841 +1980 7 16 6 7 ISAAC 37.8 124.3 144 101 +1986 10 15 6 6 TONY 36.0 33.7 62 433 +1971 11 1 18 24 KIRK 32.7 345.6 150 677 +1954 1 5 6 13 FLORENCE 41.5 139.4 78 736 +1987 11 2 12 6 LESLIE 44.4 278.7 162 77 +1975 5 28 18 1 HELENE 54.8 296.0 86 778 +1972 3 13 12 28 DEBBY 24.0 138.3 120 319 +1950 3 12 12 19 FLORENCE 59.1 27.5 99 167 +1961 4 7 12 9 PATTY 28.0 312.5 45 403 +1968 6 1 18 14 SANDY 13.1 63.8 133 508 +1997 4 8 0 3 FLORENCE 35.7 73.6 88 193 +1956 11 26 18 25 DEBBY 28.6 238.5 154 513 +1975 7 3 18 21 KIRK 40.4 71.4 38 471 +1957 5 27 6 2 FLORENCE 48.1 10.5 71 34 +1981 4 28 12 7 GORDON 27.8 126.5 139 78 +1972 8 5 0 18 KIRK 27.2 346.3 102 111 +2004 6 1 0 21 DEBBY 30.8 351.8 110 657 +1966 6 26 0 15 FLORENCE 65.4 251.9 78 753 +1959 2 27 12 12 CHRIS 23.3 118.9 41 830 +1995 5 18 0 8 KIRK 20.6 272.1 129 758 +1954 8 21 12 15 CHRIS 43.0 282.7 123 277 +1984 2 7 6 24 VALERIE 44.9 314.7 150 867 +1989 11 1 0 2 ALBERTO 41.3 43.2 91 83 +1978 11 22 12 25 NADINE 60.1 84.3 19 289 +1980 8 7 18 13 WILLIAM 13.2 109.3 109 822 +1974 12 11 6 22 TONY 37.8 329.8 84 539 +1964 9 19 6 27 KIRK 63.1 216.0 78 374 +2000 7 19 6 22 ALBERTO 55.1 298.8 91 111 +2004 5 18 12 18 PATTY 29.8 51.6 137 483 +1994 4 21 12 21 ALBERTO 14.5 341.6 34 524 +1983 9 15 0 11 NADINE 55.1 48.3 158 95 +2001 5 24 12 16 KIRK 43.7 72.3 58 336 +1977 4 12 12 11 ALBERTO 13.9 292.7 112 634 +1951 8 24 6 1 TONY 64.5 76.2 59 729 +2004 3 2 0 13 VALERIE 54.7 198.8 20 724 +1972 1 25 0 18 ISAAC 65.3 326.6 153 40 +1972 6 10 6 18 KIRK 51.7 343.7 159 420 +1978 4 12 6 8 VALERIE 61.3 25.2 135 262 +1966 2 7 12 19 ERNESTO 19.0 210.3 138 110 +1953 9 17 6 20 OSCAR 66.9 223.1 143 692 +1956 9 28 12 15 ERNESTO 63.6 203.4 122 353 +2002 2 19 12 6 BERYL 48.4 168.5 58 107 +1992 10 10 0 6 ISAAC 42.3 173.2 135 885 +1992 7 19 12 21 OSCAR 15.1 22.4 17 760 +1977 5 12 18 9 ISAAC 62.9 118.8 72 101 +1953 12 9 12 8 SANDY 63.8 246.1 38 92 +1976 8 7 6 26 RAFAEL 64.0 318.4 130 802 +1957 2 10 18 5 VALERIE 40.3 230.1 31 265 +1972 7 28 18 9 WILLIAM 18.0 103.8 35 146 +1963 11 15 18 7 KIRK 63.9 291.8 57 702 +1983 7 10 6 9 BERYL 63.9 315.7 121 133 +1961 4 1 6 2 RAFAEL 31.0 277.7 44 801 +1953 5 28 0 8 OSCAR 15.9 355.3 130 291 +1958 2 24 0 27 VALERIE 43.2 257.8 94 174 +1986 5 18 12 3 KIRK 40.0 353.6 136 390 +2000 3 28 0 7 FLORENCE 12.2 161.9 123 681 +1985 8 9 6 7 BERYL 53.3 268.4 28 330 +1963 5 11 18 8 MICHAEL 14.4 214.0 132 543 +1950 8 5 6 27 DEBBY 61.6 97.7 139 763 +1980 1 22 18 18 FLORENCE 30.0 109.5 14 612 +1979 2 1 0 6 BERYL 34.4 254.0 19 18 +1983 5 13 18 8 LESLIE 45.8 118.8 64 201 +1950 7 27 12 3 WILLIAM 27.9 297.8 58 793 +1972 9 22 18 17 SANDY 49.3 329.5 80 186 +1977 1 14 18 25 NADINE 55.9 261.3 40 579 +1962 3 28 6 6 OSCAR 49.5 124.5 58 868 +1999 2 27 0 28 LESLIE 7.4 90.4 103 12 +1984 6 15 18 5 ERNESTO 55.4 211.9 157 120 +1987 2 6 12 17 CHRIS 44.3 178.5 60 446 +1967 6 25 18 18 OSCAR 44.8 2.2 82 463 +1994 6 22 18 28 LESLIE 50.4 109.1 153 13 +1961 2 19 0 18 KIRK 10.4 127.1 48 82 +2001 1 7 6 23 ALBERTO 24.0 344.5 143 730 +1994 9 20 12 22 RAFAEL 63.6 130.4 33 842 +1959 5 28 0 23 BERYL 27.4 124.3 106 618 +1951 8 9 0 14 JOYCE 50.9 220.7 133 267 +1950 5 10 6 11 NADINE 26.5 212.1 84 451 +1982 8 5 6 1 ALBERTO 54.6 335.5 106 696 +1995 4 7 0 26 BERYL 29.1 258.3 60 638 +1964 6 12 6 24 PATTY 8.5 258.6 101 624 +1976 11 14 18 24 ALBERTO 64.8 311.0 46 787 +1989 9 2 6 25 SANDY 10.4 143.9 133 176 +1956 3 18 18 7 MICHAEL 18.8 190.5 110 553 +2004 5 19 12 11 OSCAR 13.1 101.0 16 656 +1990 4 2 18 7 BERYL 50.0 247.5 81 383 +1994 10 23 0 7 GORDON 68.9 170.1 71 522 +1954 11 14 18 10 VALERIE 66.9 260.7 107 687 +1989 4 2 0 6 FLORENCE 44.2 71.1 82 793 +1982 5 4 6 17 RAFAEL 39.9 300.0 115 648 +1996 6 5 6 18 OSCAR 42.3 21.9 103 148 +1969 5 7 18 14 CHRIS 48.9 321.7 62 753 +2004 3 5 18 3 KIRK 44.1 148.8 90 874 +1973 2 27 6 12 BERYL 31.5 3.1 90 868 +1967 4 20 12 9 RAFAEL 54.2 37.9 85 443 +2004 3 12 18 26 GORDON 66.9 273.1 26 172 +1972 12 16 6 8 SANDY 60.4 121.2 117 893 +1980 6 23 0 9 ERNESTO 21.9 222.8 31 113 +1985 12 6 0 3 WILLIAM 16.3 300.9 154 233 +1997 5 10 0 6 VALERIE 52.6 10.4 20 752 +1953 6 4 6 21 KIRK 37.8 206.1 111 443 +1987 2 9 6 6 CHRIS 9.8 273.3 56 304 +1988 2 18 12 14 SANDY 62.5 323.0 134 561 +2000 6 25 0 10 MICHAEL 16.4 193.5 121 623 +1958 12 8 0 27 RAFAEL 37.7 76.6 114 865 +1961 6 28 12 8 HELENE 54.4 110.5 28 669 +1956 2 15 6 1 GORDON 53.7 351.5 33 409 +1956 8 27 18 27 ERNESTO 59.3 253.5 41 704 +1965 9 24 12 13 LESLIE 35.0 69.2 85 547 +1953 3 14 0 18 SANDY 68.7 14.0 127 441 +1979 12 6 12 28 DEBBY 25.9 313.7 102 399 +1975 9 16 12 19 JOYCE 18.8 310.7 128 728 +1967 11 21 12 3 GORDON 38.7 36.7 76 106 +1976 12 25 12 26 CHRIS 40.4 289.2 45 83 +1978 12 28 18 11 DEBBY 13.7 94.3 141 753 +1972 9 21 6 22 DEBBY 31.3 346.8 119 821 +1992 9 18 0 10 ALBERTO 20.6 77.3 155 589 +1998 2 20 12 5 MICHAEL 65.5 101.4 93 508 +1964 4 21 0 23 OSCAR 48.9 108.7 69 873 +1960 3 8 12 22 BERYL 36.6 339.8 135 382 +1992 3 18 0 6 CHRIS 51.5 96.1 20 790 +1953 4 16 0 28 GORDON 48.5 207.8 72 725 +1973 12 19 12 15 ERNESTO 32.1 237.5 39 464 +1962 1 10 12 14 BERYL 45.4 146.5 154 33 +1979 5 8 6 25 KIRK 45.5 340.9 155 744 +1951 9 21 0 23 DEBBY 17.3 75.0 98 894 +1982 12 13 6 12 ERNESTO 42.3 42.5 19 143 +1958 9 1 18 9 ALBERTO 57.9 23.9 93 179 +1951 2 20 0 19 SANDY 11.5 58.8 107 745 +1958 6 27 18 12 ALBERTO 32.6 308.5 73 564 +1952 3 18 0 2 PATTY 56.4 42.0 92 205 +1997 4 24 18 10 MICHAEL 22.6 317.2 35 170 +1996 11 19 0 6 VALERIE 44.0 226.0 86 168 +1952 4 10 0 2 HELENE 48.7 25.2 12 330 +1974 3 16 12 6 FLORENCE 18.3 110.3 123 499 +1950 2 12 6 16 NADINE 8.4 22.5 155 560 +1965 2 11 6 6 JOYCE 28.9 222.1 106 507 +1997 7 28 6 26 ISAAC 35.9 247.3 54 644 +1950 12 16 12 18 PATTY 10.6 252.1 48 833 +1974 8 26 18 3 ERNESTO 7.0 224.9 72 15 +1998 4 24 12 17 HELENE 31.7 139.0 122 865 +1978 6 12 6 7 VALERIE 45.1 143.8 103 807 +2001 1 13 6 2 HELENE 61.8 330.2 126 38 +2002 9 7 18 7 ERNESTO 12.2 300.1 26 784 +1991 3 12 18 11 BERYL 68.5 329.5 86 22 +1967 5 26 6 20 ERNESTO 68.0 116.0 125 321 +1980 8 13 6 16 GORDON 46.0 278.8 108 493 +1985 8 20 12 12 NADINE 59.6 276.5 113 666 +2000 11 6 0 5 MICHAEL 22.8 62.3 162 363 +2004 2 25 18 14 FLORENCE 7.2 72.6 82 167 +1982 1 21 0 3 CHRIS 13.2 311.7 53 301 +1976 5 1 0 18 VALERIE 64.8 60.0 71 290 +1982 3 9 0 15 KIRK 8.0 108.5 42 831 +2001 8 7 18 4 OSCAR 50.0 172.5 14 4 +1953 8 11 6 20 ISAAC 55.3 298.0 111 601 +1973 11 10 0 18 ERNESTO 18.2 134.1 39 399 +1973 5 20 12 9 ERNESTO 26.2 162.4 36 545 +1972 3 5 0 6 GORDON 35.0 343.3 14 439 +2000 1 16 0 22 GORDON 16.9 357.0 149 527 +1991 10 1 0 26 OSCAR 33.6 40.2 133 90 +1979 12 24 18 18 LESLIE 10.0 170.5 65 625 +1953 5 7 12 24 PATTY 56.6 43.0 148 256 +1961 11 11 0 1 CHRIS 34.2 60.1 115 266 +1963 7 28 6 8 OSCAR 31.1 306.1 14 575 +1972 7 9 6 8 KIRK 21.8 189.0 64 386 +1965 1 21 6 14 KIRK 63.7 319.4 31 434 +2003 7 10 12 24 ISAAC 9.7 110.8 75 19 +1997 8 27 6 8 PATTY 31.1 207.5 97 106 +1980 8 10 18 18 LESLIE 64.9 330.5 51 85 +1952 1 16 12 27 NADINE 15.6 5.8 157 712 +1986 6 24 6 17 LESLIE 54.0 87.3 157 577 +1953 6 9 18 13 PATTY 28.3 116.6 153 4 +1954 6 6 12 21 BERYL 21.6 43.7 35 884 +1966 2 21 6 14 PATTY 58.8 65.0 159 761 +1991 4 19 0 12 FLORENCE 53.3 293.5 15 751 +1966 2 25 18 28 MICHAEL 17.6 328.8 102 188 +1979 6 7 6 21 WILLIAM 69.6 139.5 13 726 +1973 11 24 6 21 HELENE 37.6 265.1 19 635 +1970 12 1 6 8 RAFAEL 52.1 137.8 30 877 +1987 11 8 18 7 PATTY 29.6 14.9 150 468 +1957 8 9 12 5 SANDY 65.4 20.7 152 257 +1986 10 17 12 21 KIRK 52.3 312.1 96 265 +1970 3 23 6 28 ALBERTO 20.7 20.4 124 860 +1954 7 28 18 9 CHRIS 32.4 122.8 62 289 +1996 9 6 0 4 ALBERTO 68.8 215.4 99 810 +1986 11 1 18 20 FLORENCE 56.0 61.7 125 851 +1999 8 21 18 21 VALERIE 31.5 190.5 129 216 +1986 8 5 18 3 LESLIE 60.4 198.4 107 268 +1999 6 9 12 9 MICHAEL 32.9 258.1 14 43 +2001 12 14 12 22 ERNESTO 12.5 300.7 141 256 +1965 6 14 6 28 KIRK 36.6 215.7 135 440 +1963 10 28 18 24 DEBBY 36.7 252.4 96 135 +1985 7 21 0 22 OSCAR 28.6 230.0 152 205 +1968 6 1 18 15 KIRK 9.2 236.4 69 181 +1954 5 7 18 8 LESLIE 46.1 89.5 135 64 +2004 10 19 12 3 DEBBY 63.2 239.1 24 601 +1957 6 25 12 21 GORDON 45.7 212.6 45 137 +1999 1 23 12 25 WILLIAM 19.5 210.5 110 67 +1999 2 2 12 2 MICHAEL 23.9 129.6 160 809 +1966 3 16 6 4 ERNESTO 30.0 15.0 58 501 +2001 3 10 6 16 ERNESTO 32.2 105.5 123 138 +1981 12 8 12 4 MICHAEL 47.2 320.3 35 167 +1979 10 5 6 23 CHRIS 38.6 348.9 143 485 +1963 5 24 6 6 ISAAC 17.6 262.7 123 634 +1993 5 25 0 4 ALBERTO 56.6 222.5 147 223 +1994 4 3 6 5 CHRIS 10.6 184.1 49 339 +1991 1 7 18 19 FLORENCE 29.8 234.6 101 113 +2004 2 13 0 5 DEBBY 28.2 20.7 34 596 +1982 5 25 6 10 MICHAEL 33.8 297.4 82 827 +2004 11 26 0 24 WILLIAM 44.5 332.9 17 829 +1958 12 26 18 21 WILLIAM 11.4 0.1 130 520 +1950 7 3 18 10 GORDON 11.6 317.7 107 624 +1993 5 16 0 3 TONY 37.0 347.2 105 318 +1992 2 19 18 6 GORDON 58.0 222.0 13 863 +1950 11 23 6 3 HELENE 68.4 186.2 58 84 +1972 1 27 0 16 GORDON 52.7 260.1 83 409 +2004 12 2 12 9 ERNESTO 66.4 94.2 13 708 +2000 1 8 18 13 KIRK 27.5 160.2 150 673 +1998 7 6 6 20 ALBERTO 20.1 138.9 65 660 +1990 3 14 6 11 CHRIS 15.5 164.4 132 100 +1990 12 13 6 22 PATTY 18.8 66.7 157 569 +1982 11 17 6 2 GORDON 15.0 11.0 30 382 +1962 9 7 18 10 GORDON 69.9 155.2 11 315 +1975 10 22 12 2 ERNESTO 64.1 123.3 37 316 +1956 7 18 12 3 WILLIAM 37.0 300.4 68 306 +1990 2 15 12 2 GORDON 49.4 211.9 51 23 +1953 12 19 18 5 GORDON 11.9 149.2 47 843 +1954 5 25 6 16 DEBBY 53.9 210.3 95 815 +1984 9 13 0 24 VALERIE 47.4 133.9 88 475 +1983 7 6 0 4 ERNESTO 31.7 20.1 18 9 +1995 10 3 0 28 FLORENCE 36.0 65.9 15 785 +1992 5 1 18 22 HELENE 26.0 101.7 23 396 +1997 2 17 0 6 JOYCE 59.0 328.8 101 617 +1953 11 12 12 3 TONY 53.7 85.4 152 286 +1956 9 4 18 2 HELENE 65.2 253.0 129 451 +1996 5 22 18 9 ALBERTO 40.0 120.1 47 844 +1988 6 3 6 26 VALERIE 68.0 100.3 161 825 +1975 7 5 12 27 MICHAEL 54.8 211.6 121 279 +1982 8 1 6 20 GORDON 32.5 206.2 33 801 +1996 10 17 12 26 TONY 9.8 212.8 125 380 +1962 10 28 12 21 BERYL 30.7 298.0 39 328 +1953 6 21 0 17 BERYL 20.7 321.7 27 348 +1960 2 19 18 25 BERYL 40.4 155.6 139 244 +1965 3 8 0 1 RAFAEL 12.7 45.5 79 78 +1972 6 10 18 7 OSCAR 56.4 325.5 143 268 +1978 2 8 18 28 LESLIE 41.6 356.0 87 202 +1961 1 7 0 27 FLORENCE 53.0 335.1 66 26 +2001 5 10 6 18 TONY 28.4 9.6 65 385 +1961 8 17 12 26 BERYL 40.7 188.9 15 350 +1956 3 12 6 2 HELENE 12.0 170.3 59 465 +1992 1 15 12 13 ISAAC 19.9 81.0 25 211 +1985 5 28 18 12 WILLIAM 58.2 219.2 66 334 +1987 7 13 0 20 NADINE 48.4 32.4 91 161 +1953 3 6 0 7 CHRIS 44.2 111.0 122 832 +1986 10 6 12 18 BERYL 59.5 9.0 114 614 +1977 5 12 6 10 NADINE 13.8 140.2 78 30 +1983 9 20 6 19 ERNESTO 43.4 162.4 65 430 +1967 12 17 12 21 JOYCE 58.4 123.6 92 500 +1977 10 9 12 22 MICHAEL 42.2 292.9 118 387 +1963 12 24 0 11 LESLIE 25.6 132.2 52 356 +2001 8 14 18 20 GORDON 48.5 181.2 53 346 +1992 12 12 0 12 HELENE 21.0 71.6 46 175 +1994 1 21 0 27 NADINE 42.7 207.9 126 538 +1988 7 27 18 22 MICHAEL 17.6 204.6 137 151 +2004 2 6 0 1 DEBBY 24.0 30.3 114 299 +1973 2 3 18 21 ALBERTO 24.5 6.3 155 348 +1963 8 14 0 1 CHRIS 44.5 195.8 160 613 +1992 9 18 6 9 RAFAEL 22.3 165.1 11 523 +1960 5 14 6 21 RAFAEL 58.3 147.8 52 491 +1986 9 8 18 18 HELENE 20.7 239.4 16 751 +1971 9 25 12 12 NADINE 39.8 320.5 109 768 +2001 2 5 6 25 NADINE 48.6 108.8 67 219 +1993 7 3 6 1 KIRK 30.5 188.1 103 833 +1994 11 8 0 21 PATTY 23.5 350.7 106 716 +1991 1 23 0 24 DEBBY 43.3 103.7 114 43 +1950 5 7 12 2 VALERIE 24.0 311.7 163 565 +1951 12 17 12 1 ALBERTO 55.1 241.6 88 31 +1997 4 10 0 6 FLORENCE 64.7 63.2 105 266 +2002 4 13 6 4 OSCAR 20.1 320.0 52 266 +1985 11 17 12 12 FLORENCE 18.5 66.4 89 807 +1960 10 13 18 11 LESLIE 52.3 137.9 100 586 +1972 4 9 18 11 VALERIE 64.1 112.2 76 470 +1956 5 28 0 19 JOYCE 18.3 115.0 123 788 +1984 11 8 18 9 VALERIE 20.3 339.9 136 337 +1988 8 3 0 10 PATTY 17.4 342.0 93 23 +1957 7 9 18 11 MICHAEL 59.0 28.7 148 322 +1965 4 25 6 18 RAFAEL 10.1 339.1 147 770 +1966 11 17 0 9 ALBERTO 53.8 99.7 130 463 +1950 10 10 6 28 PATTY 28.4 68.9 127 699 +1977 6 16 18 3 VALERIE 26.2 229.1 136 817 +1997 1 16 12 8 MICHAEL 64.0 28.4 118 893 +1951 9 16 12 26 CHRIS 69.3 324.5 39 160 +1969 1 26 6 19 MICHAEL 43.7 225.3 120 705 +1980 11 21 6 13 WILLIAM 54.6 63.8 20 130 +1974 2 22 12 7 RAFAEL 57.2 73.0 17 811 +1966 4 8 12 18 ALBERTO 64.6 311.2 29 631 +1953 2 1 6 28 BERYL 21.5 283.9 34 788 +1970 8 15 12 4 ERNESTO 39.0 337.8 100 543 +2001 3 1 0 18 ERNESTO 64.2 158.6 132 47 +1966 10 19 6 23 ERNESTO 67.1 85.8 37 38 +1956 11 11 0 20 NADINE 15.4 212.8 146 88 +2002 8 6 6 16 PATTY 9.6 139.7 122 815 +1992 11 3 12 27 HELENE 60.1 108.8 44 657 +1967 9 18 6 4 MICHAEL 60.3 152.7 107 560 +1953 4 28 0 11 LESLIE 8.1 11.2 20 581 +1974 12 27 18 6 BERYL 58.5 137.9 51 554 +1950 11 8 18 21 ERNESTO 49.8 314.4 19 262 +1952 7 21 12 9 GORDON 64.5 257.9 11 312 +2004 11 21 6 4 DEBBY 38.9 275.3 65 168 +2003 1 28 18 11 TONY 23.7 10.8 67 561 +1992 4 4 0 18 VALERIE 69.2 270.1 142 50 +1967 8 25 12 14 MICHAEL 53.9 299.2 90 827 +1987 7 10 0 13 FLORENCE 34.8 137.6 158 524 +1964 12 4 18 18 RAFAEL 28.2 29.2 12 215 +1999 6 25 18 15 HELENE 60.4 253.5 13 543 +1973 12 6 18 12 ISAAC 66.1 23.9 83 244 +1956 12 1 18 9 JOYCE 45.8 30.6 28 238 +1970 5 25 6 28 SANDY 22.1 14.0 113 312 +1951 12 13 12 7 VALERIE 27.5 112.1 14 78 +1961 9 14 12 11 SANDY 56.5 226.1 68 482 +1991 12 18 6 15 CHRIS 66.9 7.8 57 341 +1991 10 6 12 25 GORDON 58.3 94.9 73 738 +1991 1 28 12 22 KIRK 41.5 325.6 27 147 +1989 12 17 12 14 HELENE 43.8 231.6 87 63 +1972 12 18 0 18 DEBBY 36.1 260.3 124 247 +1985 1 21 6 7 ERNESTO 25.3 58.3 83 319 +1963 7 1 18 7 ISAAC 16.0 334.7 133 163 +1963 6 5 18 4 MICHAEL 68.0 228.8 138 306 +1989 6 27 0 15 TONY 30.6 7.5 107 233 +1960 12 1 0 12 LESLIE 54.9 213.7 143 254 +1966 8 22 0 24 JOYCE 55.2 243.3 122 626 +1959 1 1 6 8 FLORENCE 35.5 210.4 127 652 +1994 10 10 0 3 FLORENCE 46.5 153.9 147 284 +1976 2 18 12 15 ISAAC 54.1 30.8 91 93 +1988 9 11 6 23 TONY 59.8 265.5 108 847 +2000 8 14 6 4 LESLIE 38.3 334.7 134 312 +1997 1 14 12 9 PATTY 68.4 110.5 30 233 +1972 9 9 6 15 MICHAEL 41.5 175.6 29 883 +1996 9 6 0 7 KIRK 48.8 23.9 148 373 +1995 4 3 18 13 HELENE 44.8 110.4 112 507 +1962 8 18 0 14 DEBBY 41.6 169.5 155 548 +1956 10 3 12 12 GORDON 40.0 188.9 136 147 +1985 11 21 12 28 LESLIE 43.4 317.6 99 758 +1964 1 15 6 5 LESLIE 38.1 183.8 123 606 +1950 5 14 6 22 LESLIE 26.1 310.8 37 761 +1957 12 26 0 19 ALBERTO 58.8 334.2 61 510 +1959 2 1 12 10 TONY 19.3 281.7 45 646 +2004 7 3 0 24 ERNESTO 34.7 223.2 114 570 +1970 6 1 18 19 ALBERTO 8.5 186.1 22 667 +1997 12 9 0 10 ERNESTO 26.8 152.2 132 83 +1950 9 18 0 8 LESLIE 61.7 167.5 38 652 +1988 1 18 6 27 SANDY 21.1 70.7 70 541 +1998 9 17 18 21 OSCAR 33.9 8.2 40 325 +1964 12 6 6 6 CHRIS 43.3 305.2 68 827 +1971 7 18 0 11 VALERIE 12.1 262.1 159 423 +1995 3 1 18 11 TONY 35.1 256.4 41 805 +1975 10 23 18 17 LESLIE 22.4 175.9 116 452 +1982 4 18 6 6 DEBBY 40.8 173.6 13 58 +1953 2 9 6 4 NADINE 63.2 112.7 95 362 +1988 9 28 6 5 ISAAC 29.7 157.5 51 644 +1954 12 22 18 28 WILLIAM 31.3 55.2 103 470 +1975 1 16 0 5 HELENE 7.2 96.9 25 256 +1988 12 4 0 19 ISAAC 12.4 320.7 82 49 +1956 2 11 18 12 OSCAR 52.6 63.9 36 708 +1990 8 17 6 18 OSCAR 16.9 52.5 144 256 +2000 12 26 6 2 FLORENCE 53.9 84.0 48 106 +2004 10 8 0 11 VALERIE 38.2 317.0 62 829 +2004 11 24 6 16 PATTY 32.4 268.6 23 507 +1993 12 2 0 17 ALBERTO 53.0 105.6 136 65 +1970 2 5 12 22 MICHAEL 50.9 235.1 14 546 +1975 3 18 18 18 ERNESTO 44.7 183.3 103 374 +1955 5 16 0 23 RAFAEL 21.1 356.0 96 662 +1951 11 20 6 18 TONY 7.8 47.2 33 304 +1984 2 22 0 10 PATTY 19.2 131.2 10 369 +1960 6 6 12 11 KIRK 53.1 91.1 103 596 +1995 2 24 18 19 ERNESTO 15.6 109.5 67 785 +1955 5 9 18 6 BERYL 68.2 234.5 22 287 +1973 7 28 6 19 PATTY 33.0 252.2 116 184 +1957 3 26 12 4 BERYL 40.8 316.8 41 644 +1983 3 24 18 24 LESLIE 54.7 191.7 108 537 +2002 1 21 6 22 ISAAC 10.3 25.8 109 308 +1992 11 12 18 2 ALBERTO 69.8 241.2 82 394 +1976 7 13 6 9 JOYCE 28.4 102.5 28 7 +1978 6 24 18 12 BERYL 49.7 308.6 10 485 +1970 11 23 12 17 ISAAC 22.7 308.3 83 545 +1991 12 17 12 27 WILLIAM 49.9 192.6 71 882 +1997 5 27 18 11 OSCAR 63.2 227.1 143 691 +1951 6 2 6 7 HELENE 35.5 154.6 32 655 +1957 10 25 12 19 OSCAR 13.4 334.0 15 883 +2000 2 10 12 8 VALERIE 30.6 83.9 164 673 +1973 4 24 0 26 DEBBY 47.5 225.1 100 67 +1990 12 10 0 2 ERNESTO 20.4 26.3 91 746 +1972 8 27 6 6 CHRIS 21.3 270.7 66 191 +1979 2 25 12 18 DEBBY 7.2 168.0 76 271 +1977 6 20 18 2 OSCAR 7.6 149.0 11 278 +1963 12 12 0 2 OSCAR 55.1 17.1 72 832 +2003 12 14 12 23 DEBBY 56.9 153.6 34 121 +1991 7 17 18 22 ALBERTO 62.5 154.3 26 713 +1994 12 12 6 24 OSCAR 58.4 257.1 162 93 +1954 3 5 0 4 PATTY 53.4 238.9 125 345 +1956 2 14 12 23 OSCAR 24.8 15.3 61 118 +1962 3 14 18 9 LESLIE 16.5 157.5 78 502 +1952 10 13 12 24 DEBBY 36.0 78.8 126 136 +1998 8 13 0 15 MICHAEL 64.3 123.0 122 383 +1991 10 20 6 3 TONY 41.1 63.9 76 356 +2004 10 19 12 3 LESLIE 14.5 9.6 15 240 +1962 7 19 12 11 LESLIE 64.3 96.4 19 722 +1959 9 3 12 9 WILLIAM 10.6 16.9 52 884 +1954 5 24 0 7 NADINE 63.0 351.1 161 783 +1952 9 4 6 25 CHRIS 7.4 141.1 93 329 +1980 2 22 6 3 KIRK 39.4 179.2 157 253 +1960 9 7 18 27 TONY 32.8 225.9 128 77 +1982 6 15 0 16 HELENE 19.5 239.3 15 105 +1983 9 18 0 13 HELENE 60.9 67.0 88 5 +1986 2 17 6 17 SANDY 19.4 122.1 112 274 +1957 5 9 6 27 NADINE 49.9 300.1 29 853 +1995 5 21 0 4 FLORENCE 8.8 286.9 121 92 +1961 11 16 12 12 ALBERTO 52.4 220.5 155 348 +1962 7 24 6 23 FLORENCE 27.1 323.0 138 453 +1956 11 1 0 21 OSCAR 55.9 74.8 115 774 +1965 2 13 18 15 SANDY 38.5 135.7 129 463 +1976 10 12 12 16 HELENE 35.7 328.4 48 58 +1981 6 18 12 25 VALERIE 7.1 152.0 142 246 +1959 10 6 6 20 TONY 66.9 144.7 138 865 +1986 11 2 12 22 ALBERTO 42.7 231.9 102 743 +1988 8 14 6 28 DEBBY 35.0 292.4 142 367 +1994 1 4 18 9 KIRK 18.8 290.6 101 561 +1955 3 19 18 8 OSCAR 37.5 92.5 112 483 +1961 5 19 18 26 OSCAR 65.8 107.3 155 881 +1952 6 14 0 28 FLORENCE 8.7 239.2 154 877 +1969 2 2 12 6 BERYL 25.2 160.7 128 51 +1996 10 2 12 24 ISAAC 68.8 24.6 25 167 +1959 6 20 12 10 ALBERTO 18.4 108.3 154 747 +1956 3 24 6 18 MICHAEL 68.8 328.8 86 779 +1979 6 8 0 27 KIRK 37.5 317.8 10 272 +1957 10 12 18 15 FLORENCE 45.5 251.0 152 135 +1986 7 18 0 21 BERYL 44.0 283.1 21 490 +1972 6 22 6 1 PATTY 28.4 345.3 109 259 +1996 3 20 6 21 ISAAC 10.3 101.2 27 239 +1959 2 12 0 21 NADINE 42.6 241.2 139 729 +1969 1 27 0 17 PATTY 20.1 267.8 91 835 +1957 11 13 12 17 RAFAEL 14.7 74.4 39 802 +1961 4 4 18 19 SANDY 63.7 182.2 63 746 +1955 9 4 18 16 RAFAEL 26.5 221.4 164 444 +1999 11 10 12 4 PATTY 63.8 183.6 18 227 +1965 5 2 18 20 TONY 23.2 233.9 145 642 +1955 10 21 6 21 PATTY 19.1 202.3 154 499 +1959 11 17 6 7 DEBBY 25.0 201.9 162 656 +1994 2 24 18 3 ALBERTO 8.0 84.0 33 491 +1977 4 21 18 22 DEBBY 36.2 249.4 60 787 +1964 5 23 6 11 MICHAEL 42.5 160.1 125 632 +1973 1 17 0 19 ISAAC 57.6 187.9 116 246 +1970 9 21 18 20 HELENE 33.9 260.2 42 635 +1988 2 7 6 10 CHRIS 34.0 14.2 51 78 +1977 12 13 6 24 KIRK 58.3 103.2 93 324 +1956 1 1 0 18 JOYCE 21.4 306.5 103 535 +1997 3 7 12 9 SANDY 13.1 195.4 132 509 +1990 1 8 18 1 ERNESTO 59.9 194.7 22 789 +2003 9 14 12 19 ERNESTO 31.1 105.8 85 887 +1965 4 28 18 9 ERNESTO 63.4 334.0 144 341 +1988 10 27 0 17 WILLIAM 41.6 205.0 122 61 +1961 5 26 0 17 DEBBY 26.3 175.4 88 556 +1997 7 19 0 10 RAFAEL 31.7 255.8 100 253 +1962 9 11 12 4 HELENE 55.1 150.1 133 544 +2004 8 15 6 7 JOYCE 12.2 62.6 41 179 +1998 9 2 0 9 RAFAEL 67.1 139.2 30 166 +1971 6 26 6 4 ERNESTO 67.5 212.2 84 822 +1967 3 4 12 7 OSCAR 22.4 31.1 44 237 +2004 5 25 0 1 ERNESTO 68.5 213.9 16 302 +1960 8 8 6 8 HELENE 16.2 253.5 115 225 +1955 11 15 6 6 OSCAR 63.8 96.7 42 340 +1987 6 10 6 22 BERYL 32.9 215.5 92 776 +1968 7 12 12 6 OSCAR 25.8 197.3 85 556 +1961 2 23 12 10 CHRIS 65.6 105.5 115 300 +1955 12 12 0 22 MICHAEL 27.9 137.9 23 62 +1977 10 16 18 16 GORDON 10.9 149.1 78 476 +1973 7 15 12 19 PATTY 34.8 205.5 114 490 +1983 10 12 6 22 DEBBY 19.5 61.5 151 254 +1992 6 16 18 16 WILLIAM 11.8 33.0 135 171 +1952 9 9 0 11 ALBERTO 8.5 285.1 34 608 +1992 4 27 12 7 OSCAR 50.0 13.3 40 708 +2002 1 11 18 10 NADINE 47.9 29.8 153 269 +1976 1 13 18 3 DEBBY 24.2 21.6 19 209 +1970 2 24 18 5 VALERIE 10.9 164.3 56 326 +1952 5 28 6 8 WILLIAM 54.0 283.3 108 295 +2001 12 26 12 2 HELENE 33.4 269.2 133 699 +1986 4 15 0 6 KIRK 42.6 112.0 142 450 +1988 7 15 12 13 ERNESTO 59.8 324.0 161 425 +1985 9 26 0 16 PATTY 63.4 218.7 26 601 +2000 10 12 6 7 FLORENCE 50.6 121.3 19 781 +1954 5 21 12 20 PATTY 53.8 106.9 26 513 +1964 2 5 12 8 NADINE 68.1 6.7 12 526 +1961 6 3 18 4 WILLIAM 43.9 162.1 28 791 +1955 5 21 0 18 CHRIS 32.1 89.2 47 551 +2003 11 13 12 6 FLORENCE 68.2 345.8 146 542 +1967 11 17 18 28 RAFAEL 33.5 214.6 46 293 +1961 1 14 0 8 DEBBY 64.2 312.9 141 699 +2001 1 15 6 16 NADINE 60.3 234.8 20 226 +2003 9 1 18 28 DEBBY 50.4 265.3 97 534 +1965 1 16 0 12 WILLIAM 16.4 167.4 41 254 +1996 6 2 0 26 ALBERTO 60.8 8.3 162 597 +1972 10 26 18 28 DEBBY 67.3 194.9 47 821 +1961 3 27 12 4 VALERIE 60.1 332.1 88 67 +1996 4 16 12 10 PATTY 52.4 162.3 53 772 +1973 3 19 6 8 HELENE 36.2 308.8 12 838 +1995 9 12 0 19 OSCAR 70.0 55.7 63 432 +1987 5 6 12 7 RAFAEL 22.4 111.2 155 600 +1993 11 11 18 28 PATTY 62.7 268.8 143 784 +1954 1 3 18 24 HELENE 27.9 349.7 144 417 +1966 11 4 0 7 JOYCE 67.9 230.9 157 803 +1996 9 22 18 2 PATTY 42.2 201.1 95 122 +1966 1 20 0 6 GORDON 18.1 346.4 105 739 +1995 11 23 18 25 NADINE 27.9 80.9 52 219 +1961 8 25 6 14 DEBBY 16.1 148.5 143 143 +1989 2 21 6 15 RAFAEL 10.9 20.3 15 428 +1960 7 26 12 27 CHRIS 44.8 188.0 48 358 +1957 5 10 6 3 HELENE 57.3 321.5 93 883 +1957 12 25 18 19 LESLIE 30.0 142.4 139 132 +1982 10 5 18 7 BERYL 57.2 141.3 20 323 +1991 4 27 0 5 VALERIE 48.9 75.1 37 647 +1973 2 14 6 3 HELENE 26.0 108.1 136 556 +2003 3 27 6 18 WILLIAM 14.5 167.3 64 367 +1973 12 15 6 15 CHRIS 50.6 302.9 164 448 +1981 2 14 0 20 BERYL 49.3 250.4 35 834 +1968 3 27 18 26 HELENE 56.8 172.7 40 845 +1966 12 11 18 18 ALBERTO 28.3 160.4 17 342 +1993 6 26 0 21 ISAAC 49.6 298.6 123 665 +1990 6 28 12 19 ERNESTO 45.2 199.9 54 218 +1993 12 19 6 5 FLORENCE 49.7 323.2 36 687 +1975 7 19 0 23 OSCAR 61.8 116.2 76 628 +1987 4 20 0 17 SANDY 52.5 311.4 81 374 +1958 1 19 6 26 CHRIS 43.5 129.0 38 342 +1986 7 21 12 16 ISAAC 14.7 131.5 160 260 +1955 1 8 6 21 SANDY 9.9 183.6 127 634 +1960 2 24 18 13 HELENE 27.8 129.1 23 258 +1950 1 16 12 6 WILLIAM 65.1 151.5 53 257 +1980 7 25 18 17 BERYL 24.1 168.2 89 138 +1966 6 27 6 16 VALERIE 47.2 244.2 112 37 +1969 12 8 0 18 CHRIS 46.6 160.8 85 356 +1970 10 9 6 28 RAFAEL 30.8 88.1 55 175 +1982 10 3 6 20 JOYCE 38.4 262.5 65 356 +1952 6 13 0 1 ERNESTO 30.2 5.8 143 104 +1984 1 18 0 7 WILLIAM 40.7 246.1 112 619 +1971 5 11 18 7 BERYL 33.9 63.8 70 31 +1952 8 4 18 13 SANDY 28.9 240.8 75 6 +1954 5 23 18 10 SANDY 51.8 71.6 33 557 +1995 9 24 18 28 TONY 14.3 233.2 50 177 +1970 9 15 12 18 VALERIE 60.6 164.9 101 564 +1958 12 15 0 25 HELENE 38.7 11.2 123 438 +1958 2 28 18 28 OSCAR 20.8 311.7 13 322 +2004 8 19 18 26 WILLIAM 56.7 305.3 107 430 +1972 2 3 18 22 ISAAC 22.2 14.5 161 49 +2003 8 3 12 22 FLORENCE 7.8 25.3 44 221 +1992 10 5 18 4 ERNESTO 32.0 96.2 117 86 +1957 5 14 12 2 FLORENCE 50.6 281.8 51 612 +2001 11 4 12 26 CHRIS 11.5 76.2 75 41 +1961 7 10 18 22 PATTY 66.4 104.8 125 702 +1961 1 10 6 15 HELENE 67.0 342.9 73 129 +1988 10 9 0 17 ALBERTO 9.5 264.5 12 677 +1967 12 28 18 2 JOYCE 45.2 17.1 120 577 +1984 8 18 6 5 KIRK 68.6 15.8 39 190 +1968 6 26 0 9 JOYCE 58.5 204.6 119 559 +1981 9 24 18 3 RAFAEL 55.5 182.9 53 109 +2002 9 12 18 16 ISAAC 50.1 104.0 18 843 +1974 3 11 18 16 GORDON 41.2 299.3 43 147 +1972 7 28 18 12 VALERIE 35.3 250.4 43 463 +1983 2 15 12 16 RAFAEL 13.8 134.3 130 623 +1957 2 27 12 20 SANDY 65.8 262.1 55 774 +1962 3 12 0 15 GORDON 62.4 216.9 124 331 +1952 1 4 6 9 RAFAEL 17.8 171.2 49 579 +1972 10 22 12 6 NADINE 33.4 68.6 94 420 +1977 7 10 12 21 SANDY 9.9 3.5 118 369 +1954 7 16 6 14 NADINE 65.0 263.3 28 765 +1994 3 16 18 22 RAFAEL 63.0 167.7 156 279 +1979 3 25 18 27 VALERIE 37.6 159.3 132 772 +1979 3 10 6 25 TONY 11.0 182.8 87 123 +1989 10 4 12 8 DEBBY 38.0 59.8 68 601 +1981 5 23 18 1 KIRK 19.3 144.2 56 779 +1957 3 26 12 12 PATTY 56.6 128.4 61 883 +1971 4 21 0 22 OSCAR 16.1 38.3 123 824 +1998 12 19 12 20 ISAAC 57.2 292.3 38 187 +1954 8 23 0 4 BERYL 10.8 168.5 120 535 +1965 3 8 0 2 TONY 10.7 60.1 84 273 +1991 1 22 6 27 SANDY 58.3 287.8 108 501 +1976 11 26 18 3 JOYCE 46.6 30.7 74 657 +1981 7 11 18 18 GORDON 65.1 39.1 134 443 +1957 12 27 6 11 MICHAEL 66.4 193.3 84 833 +1950 10 8 12 24 ALBERTO 68.8 284.6 141 19 +1951 1 14 6 6 MICHAEL 17.0 106.8 88 622 +1968 2 14 18 26 ISAAC 29.2 80.0 15 293 +1999 10 3 12 16 ERNESTO 48.7 81.5 71 91 +1970 1 17 0 15 WILLIAM 17.8 167.6 101 258 +1983 10 19 12 14 NADINE 66.0 262.2 109 235 +1997 6 15 0 10 CHRIS 51.5 299.9 128 60 +1999 4 15 0 15 VALERIE 27.2 22.5 47 341 +1977 5 15 6 14 MICHAEL 54.4 19.9 154 240 +1960 5 6 6 21 RAFAEL 60.8 207.7 131 232 +1988 4 11 18 13 MICHAEL 23.3 71.4 107 116 +2002 3 26 0 22 VALERIE 47.0 190.3 142 839 +2003 1 16 12 12 NADINE 15.5 349.8 22 195 +1979 6 5 18 13 JOYCE 42.9 107.1 150 294 +1988 8 4 6 18 TONY 43.9 95.3 111 305 +1990 8 8 6 25 CHRIS 12.6 329.0 29 334 +1981 4 4 6 16 ALBERTO 25.5 318.4 98 482 +1983 4 1 6 7 TONY 55.1 215.6 23 245 +1979 4 19 12 5 HELENE 20.3 316.6 21 300 +1978 9 19 12 15 RAFAEL 27.6 114.5 77 678 +2001 2 7 18 23 MICHAEL 48.3 49.6 15 504 +1964 7 9 0 7 FLORENCE 15.8 196.9 42 221 +1953 2 8 18 7 SANDY 44.6 11.8 131 753 +1983 12 21 0 15 JOYCE 61.2 113.0 130 861 +1977 4 2 6 10 BERYL 68.9 273.0 129 26 +1973 3 11 12 19 LESLIE 54.2 170.1 122 758 +1983 7 17 0 4 OSCAR 15.1 54.9 123 539 +1985 5 13 6 18 RAFAEL 19.3 223.3 103 25 +2003 6 28 12 21 OSCAR 38.5 208.2 16 563 +1966 7 2 12 18 KIRK 12.1 345.0 66 405 +1988 3 23 12 24 ALBERTO 69.4 106.6 86 174 +1992 5 24 6 15 DEBBY 66.6 283.5 112 732 +1980 12 15 6 18 ISAAC 27.7 75.8 134 318 +1951 4 20 18 3 KIRK 30.6 125.8 76 705 +2003 6 12 6 4 NADINE 12.2 215.3 101 701 +1999 6 19 18 3 OSCAR 11.3 199.0 58 538 +2001 10 6 6 8 GORDON 61.8 261.8 36 755 +1972 12 5 12 23 RAFAEL 46.2 272.6 117 378 +1972 3 23 18 3 TONY 11.4 99.9 133 422 +1989 1 4 0 11 SANDY 11.9 210.9 86 558 +1995 11 25 12 28 BERYL 23.2 11.7 91 309 +1991 3 15 0 6 WILLIAM 24.5 96.7 89 139 +1995 3 13 0 10 ISAAC 13.2 339.5 66 592 +1985 11 6 0 22 FLORENCE 23.9 206.6 152 841 +1978 10 16 0 21 ERNESTO 45.3 259.9 57 357 +1977 4 9 18 20 ERNESTO 48.7 180.8 160 593 +1981 11 12 18 11 ERNESTO 28.0 293.9 19 351 +1963 3 4 0 15 WILLIAM 50.9 173.9 93 722 +1983 4 11 18 13 GORDON 44.1 301.8 100 803 +2001 3 11 0 6 HELENE 8.9 111.4 49 885 +1977 12 3 0 25 HELENE 57.9 92.0 80 462 +1997 9 18 0 4 DEBBY 33.6 166.0 91 600 +1980 8 19 12 26 NADINE 25.5 323.4 148 135 +1950 7 24 6 19 ERNESTO 18.0 163.5 28 686 +1959 10 4 18 27 ALBERTO 40.7 328.0 38 256 +1981 3 8 0 9 KIRK 35.3 45.9 140 495 +1965 8 6 6 9 DEBBY 31.4 235.4 111 870 +1964 11 8 6 20 LESLIE 61.2 342.2 82 476 +1991 5 9 6 4 PATTY 8.9 266.3 155 688 +1991 6 25 18 21 ERNESTO 47.2 356.5 128 94 +2001 1 7 18 18 NADINE 21.0 197.6 137 762 +1994 8 16 0 9 GORDON 12.9 294.9 108 78 +1973 2 5 18 19 DEBBY 57.2 212.2 72 193 +1992 12 12 6 7 WILLIAM 45.8 250.1 34 681 +2004 3 6 12 4 MICHAEL 16.6 23.8 21 825 +1963 4 22 0 28 HELENE 8.4 230.4 137 230 +2000 3 18 18 26 ISAAC 35.0 150.2 145 541 +1950 8 13 12 17 ALBERTO 9.9 80.9 80 885 +1989 4 4 6 5 BERYL 43.2 0.8 64 217 +1959 10 11 12 4 LESLIE 7.6 323.9 128 391 +1978 8 25 6 24 SANDY 37.1 116.8 119 108 +1952 11 27 0 12 MICHAEL 67.0 345.1 31 40 +1974 11 11 0 15 OSCAR 62.3 23.1 25 121 +1995 10 3 0 12 DEBBY 20.3 75.0 124 450 +1960 11 19 0 7 FLORENCE 67.6 47.5 148 253 +1955 3 7 18 26 SANDY 9.5 162.5 40 353 +1971 12 18 12 3 HELENE 32.8 353.1 43 337 +2004 11 24 18 3 OSCAR 27.8 62.6 71 453 +1957 9 24 0 23 JOYCE 27.5 5.6 103 43 +1969 1 17 18 12 PATTY 18.3 48.4 108 850 +1976 3 19 6 21 RAFAEL 47.8 5.9 124 548 +1985 2 14 6 13 LESLIE 61.5 101.3 107 412 +1997 8 4 12 15 MICHAEL 14.0 223.5 159 783 +1980 5 14 6 20 KIRK 65.3 265.6 119 729 +1970 2 22 0 15 TONY 45.4 249.9 159 102 +1961 3 3 18 21 DEBBY 14.9 14.1 33 139 +1954 10 15 12 21 ISAAC 10.2 105.3 92 655 +1994 5 28 6 5 HELENE 47.5 169.8 124 307 +1975 7 3 0 15 RAFAEL 32.2 148.0 161 720 +2000 9 21 12 26 OSCAR 25.9 174.9 58 840 +1956 8 14 0 21 NADINE 29.5 25.6 55 882 +1958 9 6 6 19 TONY 60.6 68.3 109 36 +1950 1 24 12 17 SANDY 7.3 54.7 11 294 +1988 7 3 0 1 PATTY 40.9 68.5 37 278 +1962 9 15 0 23 NADINE 40.5 15.9 84 305 +1993 11 12 0 23 NADINE 7.0 172.5 54 240 +1974 7 26 0 26 RAFAEL 45.4 86.9 159 178 +1993 8 8 18 19 GORDON 69.3 342.2 136 590 +1981 7 2 12 19 DEBBY 52.5 292.9 41 736 +1951 10 16 12 23 ALBERTO 50.6 11.3 77 575 +1963 4 24 12 4 WILLIAM 40.7 247.2 55 215 +2000 6 11 0 21 KIRK 13.9 160.0 80 131 +1966 7 28 12 7 SANDY 41.9 114.9 105 225 +1987 11 12 0 20 ALBERTO 49.0 194.5 97 452 +1957 2 12 18 1 WILLIAM 40.3 75.3 135 750 +2004 9 23 18 9 MICHAEL 49.0 141.3 103 259 +1976 7 25 12 9 NADINE 50.6 136.6 148 554 +1997 1 8 12 28 SANDY 8.4 308.3 41 122 +1997 8 2 18 24 CHRIS 51.7 88.8 106 570 +1956 6 17 6 12 ISAAC 60.0 206.5 35 437 +1961 10 14 12 9 OSCAR 44.5 138.2 22 443 +1980 3 13 0 26 ERNESTO 34.9 36.9 82 276 +1986 10 23 18 1 JOYCE 21.7 149.5 14 477 +1950 12 23 18 2 NADINE 14.6 120.6 57 145 +1956 2 7 6 21 DEBBY 22.1 335.5 157 225 +1969 6 3 0 17 BERYL 56.3 80.1 103 365 +1977 9 17 12 27 KIRK 9.0 165.0 102 579 +1964 3 17 18 7 HELENE 38.7 278.2 160 602 +1967 9 26 0 21 TONY 60.7 7.6 109 737 +1951 5 13 0 23 OSCAR 35.8 193.2 23 865 +1954 6 3 18 21 ALBERTO 66.1 327.0 162 216 +1971 3 19 12 25 VALERIE 46.0 189.2 31 530 +2002 5 11 0 5 WILLIAM 64.0 309.0 115 663 +1996 8 8 6 11 PATTY 58.6 312.3 60 271 +1965 5 17 12 1 MICHAEL 29.3 263.8 148 358 +1986 1 8 6 1 JOYCE 57.0 195.8 10 734 +1971 8 28 12 20 TONY 52.0 5.1 160 172 +1977 10 3 0 13 ALBERTO 12.2 4.5 76 220 +1972 4 10 6 4 PATTY 51.3 112.0 164 324 +1984 8 11 12 5 LESLIE 61.4 296.7 125 216 +1989 10 10 6 3 ERNESTO 45.8 155.5 101 690 +1955 10 2 12 1 VALERIE 32.4 253.1 90 790 +1974 8 26 0 24 HELENE 29.8 161.2 70 739 +1967 3 21 6 9 WILLIAM 68.1 337.9 106 144 +1962 12 16 0 17 HELENE 47.7 249.4 69 766 +1957 3 26 0 5 LESLIE 68.4 278.2 17 616 +1950 3 19 6 23 TONY 28.9 289.2 119 149 +1958 3 23 18 26 ERNESTO 30.8 152.4 43 466 +1997 9 5 0 4 KIRK 46.3 77.7 130 447 +1951 12 8 12 28 ALBERTO 56.6 84.6 23 92 +1975 12 1 0 6 MICHAEL 63.2 153.3 21 280 +2004 4 6 12 11 KIRK 30.2 326.9 92 217 +1966 6 13 18 20 ISAAC 59.0 243.7 142 63 +1991 8 26 6 26 WILLIAM 62.4 299.0 123 253 +1967 6 6 6 18 LESLIE 13.7 199.7 69 530 +1971 9 20 18 12 HELENE 17.6 115.7 139 856 +1951 12 19 12 24 VALERIE 16.2 265.0 123 93 +1962 11 4 12 7 KIRK 67.0 210.3 13 631 +1990 3 4 0 22 TONY 62.6 346.6 76 579 +1973 11 22 6 23 MICHAEL 66.6 245.4 137 665 +2004 10 14 6 2 FLORENCE 20.9 229.1 75 312 +1991 1 22 12 8 ALBERTO 63.0 243.9 22 284 +1969 10 2 18 24 OSCAR 65.6 218.1 162 524 +1958 4 11 12 12 SANDY 44.5 229.8 131 361 +1961 5 19 6 16 DEBBY 34.6 309.4 75 650 +1998 1 23 12 23 WILLIAM 43.7 271.7 158 223 +1973 4 5 0 24 ISAAC 22.7 213.5 124 167 +1999 10 7 0 8 NADINE 47.7 7.0 152 744 +2001 9 11 0 6 MICHAEL 23.1 22.9 131 385 +1983 2 5 12 1 KIRK 27.9 291.6 160 133 +1955 12 9 12 17 TONY 10.7 139.5 158 344 +1953 10 25 6 17 TONY 59.7 139.8 87 418 +1988 7 8 6 14 OSCAR 15.6 54.5 67 156 +1968 4 18 0 21 NADINE 33.5 52.2 71 708 +2004 11 28 18 10 PATTY 25.4 28.4 97 416 +1966 1 3 12 7 OSCAR 27.6 49.2 101 155 +1960 9 7 18 26 ISAAC 67.8 356.4 134 298 +1958 7 4 12 20 BERYL 8.2 247.1 31 855 +1994 6 20 18 18 SANDY 69.9 332.0 133 315 +1959 7 19 12 14 HELENE 43.4 336.3 140 769 +1995 6 26 6 26 MICHAEL 67.7 339.7 48 498 +1959 7 19 6 3 ALBERTO 27.2 319.2 83 53 +1967 4 11 0 20 FLORENCE 66.7 230.8 129 747 +2000 3 14 18 11 NADINE 38.2 356.6 126 34 +1969 3 16 0 17 CHRIS 69.1 277.2 104 516 +1995 12 25 12 23 JOYCE 52.4 127.5 65 201 +1964 6 6 0 18 HELENE 68.7 96.0 43 661 +1951 7 21 6 26 OSCAR 54.6 242.9 116 732 +2003 2 17 6 24 MICHAEL 59.8 23.0 16 263 +1952 7 1 0 8 WILLIAM 13.8 190.9 115 446 +1989 2 28 12 4 OSCAR 23.0 250.3 28 535 +1959 6 20 6 18 RAFAEL 54.7 180.7 43 840 +1987 11 12 18 20 CHRIS 24.3 162.3 135 499 +1964 12 10 18 3 ALBERTO 45.3 229.9 91 159 +1982 7 28 6 11 ERNESTO 13.5 124.7 143 541 +2004 6 6 18 26 FLORENCE 13.3 314.9 122 804 +1960 12 14 6 18 NADINE 31.5 162.0 130 479 +1979 9 21 12 25 ALBERTO 16.9 179.2 116 799 +1959 2 13 6 2 WILLIAM 50.0 208.6 67 65 +2000 4 4 12 28 WILLIAM 64.5 148.6 138 254 +1953 6 2 0 2 HELENE 41.5 89.9 155 743 +1953 3 13 18 13 OSCAR 58.1 275.6 90 166 +1961 2 19 6 20 GORDON 59.2 10.7 35 14 +1987 1 3 18 20 TONY 51.7 150.8 51 83 +1988 4 25 6 13 KIRK 20.6 5.8 43 708 +1982 9 10 6 11 OSCAR 13.0 219.4 73 575 +1951 9 27 0 12 WILLIAM 15.5 200.2 66 868 +1959 10 20 6 8 RAFAEL 13.2 102.4 134 474 +1988 2 10 6 20 NADINE 56.0 176.8 101 159 +1956 6 17 12 6 GORDON 52.7 100.4 42 639 +1993 12 8 6 14 OSCAR 19.3 61.9 39 340 +1952 1 14 6 19 OSCAR 41.9 242.1 125 649 +1959 10 19 18 24 MICHAEL 45.7 195.7 12 852 +1967 5 16 18 5 RAFAEL 44.5 221.7 131 85 +1982 11 23 0 16 JOYCE 56.0 298.3 65 345 +1951 2 26 12 7 FLORENCE 28.7 220.7 40 739 +1987 9 17 6 6 TONY 65.2 154.1 74 732 +2000 1 24 0 4 DEBBY 45.4 72.9 106 669 +1967 1 6 0 20 ERNESTO 36.6 239.5 120 879 +1951 10 6 12 3 MICHAEL 57.6 123.6 69 603 +2001 4 11 6 27 NADINE 13.8 196.1 164 63 +1983 9 5 12 9 GORDON 45.6 66.8 120 106 +1987 10 4 6 19 ALBERTO 12.7 297.7 40 149 +1984 9 19 12 20 TONY 23.5 281.4 80 891 +1965 5 10 18 12 JOYCE 7.3 42.1 153 76 +1978 12 2 0 26 MICHAEL 35.3 266.0 163 859 +1985 7 28 12 28 ERNESTO 14.9 309.6 28 106 +1992 1 12 6 22 MICHAEL 50.7 168.2 138 182 +1982 5 22 12 16 SANDY 68.0 3.3 88 89 +2003 2 21 12 13 FLORENCE 17.3 225.8 52 120 +1988 2 20 6 13 KIRK 22.3 189.2 94 497 +1992 7 28 6 15 BERYL 37.7 318.8 126 368 +1968 8 8 18 3 PATTY 60.9 13.4 111 273 +1990 4 13 12 12 JOYCE 44.6 13.3 70 810 +1989 11 12 6 21 TONY 61.2 280.8 141 549 +2004 9 5 12 28 ISAAC 51.2 181.2 89 482 +1992 1 14 6 15 BERYL 10.8 97.2 135 371 +1993 4 17 0 13 LESLIE 7.2 320.6 107 243 +1995 8 3 0 8 OSCAR 40.6 164.0 75 399 +1970 9 15 6 28 LESLIE 62.9 54.2 66 827 +1974 2 21 0 11 VALERIE 14.5 65.2 129 42 +1957 3 27 12 23 SANDY 45.9 68.4 145 367 +1952 10 17 12 14 BERYL 21.9 322.0 75 244 +1954 7 1 0 9 ISAAC 48.2 263.9 16 231 +1965 3 12 6 3 TONY 52.7 138.1 78 486 +1976 1 9 18 19 ALBERTO 25.1 256.4 70 780 +1979 7 23 6 24 MICHAEL 57.2 309.3 105 131 +2001 8 17 18 9 TONY 45.1 206.8 142 270 +1953 10 27 0 14 MICHAEL 68.2 12.4 134 176 +1997 11 21 18 2 ISAAC 19.2 117.8 143 137 +1984 10 12 18 4 JOYCE 19.8 27.8 108 106 +1957 5 27 12 13 CHRIS 32.6 202.1 100 727 +1975 9 1 18 20 RAFAEL 29.7 107.2 77 492 +1983 9 20 0 9 GORDON 59.9 205.8 140 35 +1955 8 27 18 15 WILLIAM 16.5 68.9 140 44 +1953 4 11 0 3 ALBERTO 51.3 24.2 95 792 +1962 2 19 12 7 HELENE 56.6 214.4 78 400 +1977 5 28 0 20 TONY 49.5 139.1 68 23 +1976 3 10 0 23 ALBERTO 32.1 225.8 12 747 +1976 2 19 0 22 NADINE 50.2 344.0 129 431 +1988 7 22 12 14 WILLIAM 56.5 6.8 121 294 +1955 6 12 0 1 ERNESTO 39.5 48.0 46 670 +1961 7 8 12 23 ERNESTO 29.6 184.3 81 121 +1984 9 11 6 4 NADINE 48.9 355.1 69 281 +1971 4 21 18 9 JOYCE 27.0 11.3 61 3 +1966 2 15 12 5 FLORENCE 39.9 309.0 154 744 +1979 11 4 12 15 HELENE 30.2 265.5 67 254 +1984 9 17 18 2 FLORENCE 8.3 199.6 56 301 +1966 9 15 12 19 OSCAR 27.4 285.9 13 13 +1970 7 15 6 15 GORDON 26.4 292.3 38 319 +1981 4 23 0 5 CHRIS 10.7 263.6 126 794 +1980 6 23 6 15 VALERIE 53.2 111.0 155 29 +1956 7 15 0 6 MICHAEL 45.9 294.1 69 38 +1973 7 28 18 20 BERYL 63.5 324.4 21 839 +1989 5 2 18 13 KIRK 64.9 192.3 159 467 +1986 6 8 0 27 RAFAEL 63.0 72.9 49 581 +1990 4 2 6 4 HELENE 11.5 79.2 20 427 +1950 3 15 18 14 HELENE 65.0 44.7 119 456 +1962 6 16 12 20 LESLIE 18.7 192.6 16 891 +1977 1 15 18 26 VALERIE 41.2 131.6 83 204 +1994 8 1 18 25 ALBERTO 10.6 321.7 129 516 +1983 8 8 0 1 FLORENCE 69.4 114.1 91 114 +1951 6 9 6 19 KIRK 53.9 43.6 33 794 +1987 10 20 12 5 ISAAC 56.1 159.3 121 21 +1972 4 14 12 26 BERYL 46.8 224.0 103 668 +1977 8 16 0 26 TONY 59.7 98.8 64 426 +1951 4 27 6 26 TONY 8.2 172.3 43 45 +2001 7 14 18 4 TONY 14.9 187.4 144 30 +1972 6 13 6 4 KIRK 17.8 303.0 157 162 +1987 4 15 0 13 JOYCE 68.8 262.6 92 554 +1978 8 5 6 2 JOYCE 34.0 61.9 67 564 +2001 10 24 12 28 HELENE 54.2 103.9 62 139 +1961 5 5 6 12 RAFAEL 47.0 247.5 33 848 +1988 5 25 0 5 JOYCE 42.9 271.3 80 770 +1967 6 6 12 1 GORDON 28.2 309.9 106 352 +1972 5 28 0 1 ISAAC 47.4 85.7 164 357 +1997 6 24 0 25 RAFAEL 40.9 257.3 36 506 +1969 3 14 12 4 FLORENCE 64.6 37.8 155 843 +1981 9 20 18 9 DEBBY 29.4 239.9 26 137 +1993 10 6 6 11 ERNESTO 30.8 221.7 156 200 +1969 12 14 12 9 KIRK 38.8 228.8 127 94 +1988 11 9 12 7 OSCAR 14.8 354.2 53 734 +2000 4 14 0 9 GORDON 38.2 181.3 83 662 +1980 5 9 6 18 LESLIE 22.1 202.2 133 94 +1972 6 17 0 7 HELENE 58.4 244.8 122 158 +1997 4 27 0 6 GORDON 30.8 50.4 41 269 +1979 3 21 0 12 DEBBY 45.3 297.7 146 238 +1993 10 1 0 18 ALBERTO 35.9 158.3 116 751 +1972 6 21 6 9 JOYCE 68.6 275.4 116 88 +1982 12 4 0 3 DEBBY 12.2 12.3 149 779 +1973 4 20 18 25 RAFAEL 38.7 214.9 136 216 +1987 2 13 18 25 MICHAEL 28.6 64.0 157 251 +1957 5 16 18 27 ERNESTO 48.6 85.6 132 847 +1987 2 2 0 1 OSCAR 16.6 290.8 106 632 +1974 6 2 18 5 MICHAEL 15.1 347.1 32 849 +1970 7 10 18 9 PATTY 36.8 256.3 118 880 +1971 1 7 0 17 VALERIE 33.1 163.7 38 794 +1972 12 16 0 5 FLORENCE 9.2 265.7 162 365 +1976 12 14 12 28 WILLIAM 24.6 199.6 39 258 +1994 4 21 18 26 SANDY 53.5 85.5 107 346 +1955 9 16 0 7 TONY 66.3 185.8 55 794 +1961 3 18 12 8 LESLIE 57.4 118.5 155 657 +1950 6 13 0 10 TONY 8.2 314.4 135 329 +2004 3 6 0 27 CHRIS 66.5 0.1 61 70 +2003 7 8 0 8 CHRIS 21.9 198.9 155 301 +1989 10 26 18 27 FLORENCE 53.5 216.5 154 326 +1964 3 10 0 11 NADINE 53.7 66.3 29 35 +1960 2 6 0 8 ERNESTO 8.6 191.0 75 583 +1954 11 12 0 13 FLORENCE 35.6 80.4 34 714 +1978 10 14 12 3 KIRK 24.8 329.1 54 172 +1966 2 4 0 16 RAFAEL 41.2 52.7 138 716 +1953 2 23 6 5 ERNESTO 25.3 18.9 14 124 +1995 2 12 12 13 ISAAC 19.1 58.4 24 607 +2004 4 20 0 18 ALBERTO 62.6 346.3 113 108 +1990 5 3 12 26 ERNESTO 16.5 178.7 92 224 +1951 11 1 6 8 ERNESTO 65.1 134.6 14 184 +1978 8 3 12 19 ISAAC 19.9 104.0 94 715 +1978 4 22 18 10 ISAAC 42.5 171.2 73 407 +1978 12 23 12 12 RAFAEL 43.5 192.3 85 131 +2000 2 18 6 15 ALBERTO 40.3 7.9 126 866 +1960 10 9 18 10 JOYCE 40.0 340.7 19 157 +1953 2 11 12 2 GORDON 18.1 1.3 155 65 +1997 12 16 6 10 LESLIE 34.4 222.8 161 688 +1964 4 18 6 25 JOYCE 37.7 151.1 66 22 +1995 5 28 6 4 VALERIE 21.1 54.9 136 721 +1953 1 16 12 13 BERYL 19.5 121.7 79 895 +1969 7 2 0 4 GORDON 44.9 183.5 82 748 +1985 7 28 12 5 BERYL 40.2 175.2 49 253 +1996 5 24 12 28 ISAAC 31.9 319.5 51 884 +1984 1 22 0 19 VALERIE 15.6 94.3 69 463 +1953 12 8 6 19 TONY 44.1 271.6 125 492 +1954 2 7 12 9 ISAAC 68.9 108.4 154 498 +1989 2 8 12 22 RAFAEL 30.3 233.6 67 387 +2001 10 17 12 20 MICHAEL 44.6 68.0 37 321 +1960 5 22 6 5 OSCAR 69.7 299.2 85 436 +1984 9 26 6 9 ERNESTO 34.5 132.1 41 513 +1988 12 19 6 24 NADINE 26.1 235.6 102 641 +2002 1 14 6 24 RAFAEL 25.6 51.2 68 152 +1978 2 15 6 27 OSCAR 43.6 81.5 19 697 +1994 2 18 12 14 BERYL 17.1 98.3 25 413 +1964 6 18 18 25 ALBERTO 40.3 117.2 104 361 +1978 3 20 6 28 RAFAEL 45.2 10.5 18 609 +1958 6 26 18 10 MICHAEL 7.6 277.2 76 323 +1950 3 11 18 20 WILLIAM 12.4 320.4 133 567 +1995 7 20 18 18 GORDON 56.5 126.1 117 535 +1960 3 21 12 13 VALERIE 69.2 128.2 22 829 +1982 6 5 6 2 FLORENCE 23.8 2.0 45 887 +1966 5 10 0 26 VALERIE 13.2 313.9 156 898 +1959 12 27 6 11 MICHAEL 19.8 349.9 31 581 +1956 3 2 12 3 SANDY 64.2 357.3 146 806 +1956 6 12 0 18 PATTY 29.1 39.9 47 267 +1991 10 20 12 9 OSCAR 9.5 250.8 34 416 +1990 6 18 18 1 LESLIE 57.8 255.9 58 716 +1977 10 1 18 22 KIRK 40.6 299.7 140 508 +1970 3 13 18 8 ISAAC 41.0 72.5 48 817 +2001 11 21 12 19 ISAAC 20.6 342.0 50 77 +1990 11 19 0 24 MICHAEL 50.4 357.6 86 719 +1977 1 25 6 10 ISAAC 37.1 105.7 111 865 +2003 5 11 6 24 HELENE 37.3 247.9 83 523 +1976 10 21 6 3 CHRIS 46.8 317.3 148 42 +1972 10 20 0 8 KIRK 28.2 252.0 72 25 +1953 1 10 6 13 JOYCE 7.4 220.6 65 828 +1997 12 12 6 4 PATTY 13.7 332.8 105 203 +1962 4 25 12 16 DEBBY 31.0 263.7 92 162 +1962 3 17 0 23 FLORENCE 51.7 238.9 42 93 +1993 5 15 12 20 WILLIAM 37.9 51.6 79 459 +1971 2 1 6 15 TONY 43.2 295.0 151 174 +1999 2 13 0 22 NADINE 11.3 6.1 34 263 +1952 1 8 18 19 ALBERTO 54.6 236.6 85 868 +1960 11 25 0 14 KIRK 62.2 350.1 94 56 +1971 9 17 0 9 ISAAC 22.5 121.6 80 313 +1996 7 8 12 6 ERNESTO 65.4 92.7 62 509 +1970 5 17 12 20 DEBBY 56.8 126.7 107 200 +1982 3 6 0 14 PATTY 39.3 41.2 40 672 +1970 6 19 0 1 HELENE 61.6 54.6 34 460 +1958 2 4 6 12 BERYL 50.8 336.7 150 137 +1967 3 11 18 8 FLORENCE 46.0 89.9 27 777 +1998 5 26 12 19 SANDY 38.3 351.5 110 280 +1993 8 10 0 3 SANDY 10.9 77.3 142 302 +1975 6 26 6 28 DEBBY 65.5 61.4 46 653 +1978 11 2 6 17 DEBBY 19.9 225.6 86 855 +1951 2 26 0 25 OSCAR 38.5 298.8 157 15 +1986 6 14 12 10 CHRIS 21.0 78.0 149 139 +1960 6 8 0 17 RAFAEL 34.5 283.8 20 56 +2000 4 1 12 20 FLORENCE 31.2 323.6 51 697 +1980 1 8 18 2 GORDON 20.2 96.6 44 404 +2002 12 26 0 20 ALBERTO 44.2 324.0 44 785 +2002 11 28 12 18 SANDY 62.3 152.6 37 305 +1992 5 11 6 27 DEBBY 19.0 214.3 90 313 +1960 11 24 18 12 VALERIE 19.5 202.7 158 68 +1968 9 26 18 27 BERYL 67.8 62.6 162 796 +1996 3 20 18 18 ERNESTO 59.8 46.1 155 91 +1981 7 10 12 7 ISAAC 67.4 135.4 39 832 +1962 1 4 6 28 ALBERTO 11.7 104.1 129 191 +1995 8 18 12 20 ISAAC 59.6 226.8 40 72 +1990 1 2 6 1 WILLIAM 34.8 119.6 27 472 +1988 2 17 12 3 HELENE 15.2 63.8 40 158 +1953 4 3 0 2 HELENE 45.8 166.1 83 625 +1988 3 25 0 28 FLORENCE 63.2 23.3 126 131 +1977 4 12 18 15 LESLIE 16.4 50.2 39 205 +1998 11 11 0 8 GORDON 52.1 62.5 29 61 +1959 7 9 18 24 LESLIE 48.4 206.7 153 312 +1995 10 14 0 26 PATTY 37.0 59.5 55 888 +1968 8 19 6 14 MICHAEL 40.3 77.5 49 226 +1966 5 19 18 19 HELENE 45.8 261.1 30 749 +1998 12 3 6 11 CHRIS 55.8 330.9 145 885 +1985 5 8 18 28 FLORENCE 46.3 107.8 150 847 +1970 11 25 12 12 GORDON 54.6 271.4 164 11 +1968 3 6 12 7 ISAAC 28.9 342.1 56 807 +1978 5 12 0 5 ERNESTO 53.0 40.6 77 148 +1963 9 20 18 18 MICHAEL 25.0 164.1 160 588 +1964 5 11 18 8 TONY 59.6 272.5 11 717 +1984 3 1 18 15 OSCAR 8.5 188.0 87 350 +1957 11 3 6 26 BERYL 7.6 36.3 68 55 +1984 6 22 0 23 ISAAC 67.6 222.0 39 365 +1985 1 27 18 12 TONY 35.9 312.0 29 473 +1990 5 18 18 25 ERNESTO 57.7 2.6 14 733 +1987 7 23 18 4 PATTY 29.6 116.7 164 391 +1979 8 3 0 28 PATTY 14.3 282.9 99 734 +2000 10 23 12 18 RAFAEL 69.7 52.5 126 252 +1968 11 19 6 14 BERYL 14.1 53.8 111 682 +1963 11 10 12 6 JOYCE 28.9 24.0 55 194 +1992 6 16 6 8 RAFAEL 64.4 208.2 131 387 +1967 10 10 6 25 KIRK 17.3 3.7 96 254 +1976 7 19 12 1 DEBBY 68.6 138.1 55 589 +1953 3 6 18 14 MICHAEL 44.1 284.5 24 120 +1955 2 1 18 4 ISAAC 45.6 250.1 119 56 +1997 4 21 18 12 LESLIE 37.6 172.2 153 802 +1952 6 3 0 6 KIRK 48.0 233.5 58 696 +1977 8 25 12 27 LESLIE 16.5 73.3 117 446 +1992 7 15 6 25 JOYCE 65.2 147.5 59 672 +1985 7 8 12 7 ERNESTO 16.1 340.9 158 86 +1999 7 22 6 26 JOYCE 21.9 156.3 139 830 +1972 4 20 12 21 BERYL 55.9 233.5 18 773 +1971 6 7 12 13 WILLIAM 51.0 330.7 83 441 +1991 11 24 0 9 SANDY 62.0 305.7 162 402 +1978 6 28 12 7 WILLIAM 35.4 18.6 134 784 +1995 5 27 0 4 MICHAEL 18.7 158.2 103 588 +1967 8 9 0 6 GORDON 30.1 278.9 83 834 +1954 7 28 6 9 VALERIE 31.8 231.5 145 346 +1986 10 8 6 22 KIRK 29.4 30.9 148 201 +1998 10 23 6 12 KIRK 69.8 173.0 155 390 +1964 3 7 12 23 VALERIE 10.7 71.5 110 180 +1950 8 13 0 18 HELENE 33.3 293.0 36 324 +1987 9 8 18 5 KIRK 27.2 195.0 58 724 +1987 6 8 12 22 CHRIS 57.4 65.5 78 341 +1976 9 5 18 13 SANDY 32.1 341.5 127 749 +2003 10 8 0 2 ERNESTO 52.7 343.6 139 526 +1983 1 16 0 3 NADINE 37.4 67.9 101 469 +1982 7 15 12 10 NADINE 34.3 298.1 10 615 +1969 1 12 0 9 OSCAR 28.3 198.5 116 583 +1955 3 24 0 8 SANDY 36.5 283.5 109 50 +1983 11 7 0 6 ALBERTO 56.6 344.3 78 351 +1987 7 9 18 13 JOYCE 56.4 181.1 98 374 +1961 6 11 12 18 ERNESTO 69.4 26.6 79 397 +2004 11 27 18 18 KIRK 67.8 127.5 96 101 +1970 11 1 12 17 GORDON 55.0 155.1 72 58 +1985 5 18 0 28 PATTY 29.1 347.3 108 884 +1992 3 1 18 14 RAFAEL 48.6 39.1 36 337 +1975 4 3 6 7 FLORENCE 63.4 158.0 81 570 +1966 2 23 0 6 TONY 56.5 103.6 49 882 +2001 9 19 6 17 DEBBY 62.2 155.4 30 859 +2000 6 15 12 23 KIRK 59.8 291.3 58 465 +1978 1 6 12 2 FLORENCE 43.2 195.0 52 581 +1962 10 6 6 28 CHRIS 44.4 218.3 42 246 +1995 5 6 0 8 MICHAEL 51.1 150.4 85 571 +1964 3 13 18 25 ALBERTO 18.2 36.6 94 207 +1969 11 18 6 6 ALBERTO 24.5 306.4 152 149 +1953 1 10 0 19 PATTY 30.7 81.7 31 586 +1954 10 19 6 4 ERNESTO 33.3 290.2 133 171 +1979 5 10 12 2 SANDY 53.2 151.5 142 494 +2000 11 12 12 14 JOYCE 15.7 348.9 85 745 +1998 5 3 6 7 ALBERTO 68.9 156.1 31 617 +1961 10 13 0 3 LESLIE 61.8 57.6 46 442 +1997 3 21 0 6 DEBBY 7.7 293.3 66 687 +1963 2 27 18 23 TONY 9.7 130.2 13 390 +2004 2 15 0 11 HELENE 37.4 312.1 100 164 +1980 3 13 0 14 LESLIE 23.9 129.8 121 42 +1995 4 18 0 16 WILLIAM 17.6 159.8 45 847 +1977 5 21 18 20 NADINE 13.4 296.8 163 108 +1986 6 9 6 12 KIRK 28.5 193.8 27 759 +1986 4 10 6 5 NADINE 12.9 170.1 21 695 +1964 9 18 0 5 WILLIAM 31.5 161.5 31 352 +1972 12 12 0 28 TONY 40.5 226.6 69 494 +1962 11 20 6 4 OSCAR 46.7 263.0 15 884 +1997 6 27 12 18 HELENE 7.6 172.8 59 44 +1960 2 5 0 14 MICHAEL 50.6 66.0 142 371 +2000 8 9 12 6 WILLIAM 59.8 290.5 91 548 +1964 5 3 12 7 SANDY 42.8 55.0 85 186 +1980 11 25 18 9 HELENE 49.9 325.1 138 768 +1951 11 4 18 7 ERNESTO 44.6 69.5 162 439 +1980 12 23 12 10 FLORENCE 16.5 301.0 54 424 +1967 4 7 0 16 FLORENCE 22.0 76.9 153 306 +1964 12 6 12 25 GORDON 57.9 318.1 106 152 +1993 2 18 6 16 RAFAEL 22.5 251.1 155 816 +1997 1 21 6 5 CHRIS 29.1 296.5 17 335 +1962 9 22 12 17 CHRIS 57.8 101.8 96 742 +1961 5 19 12 1 GORDON 38.4 76.9 31 195 +1969 7 25 0 4 JOYCE 63.2 106.2 19 848 +1971 1 3 0 5 ERNESTO 34.7 35.4 164 437 +1981 10 4 6 16 CHRIS 49.8 38.7 144 28 +1966 12 24 6 12 OSCAR 23.7 150.9 40 130 +1969 5 12 12 21 LESLIE 39.1 151.5 100 562 +1966 1 27 6 17 ALBERTO 49.2 66.6 70 838 +1994 8 8 0 28 PATTY 8.1 266.0 42 297 +1998 2 1 12 24 KIRK 18.4 242.3 54 212 +1985 7 14 0 3 OSCAR 40.2 78.0 72 622 +1985 11 26 12 12 RAFAEL 59.0 48.1 150 255 +1999 1 8 18 4 TONY 28.6 96.9 126 209 +1968 11 2 18 20 RAFAEL 22.6 160.4 13 736 +1964 7 23 12 18 RAFAEL 14.1 213.8 46 90 +1971 7 20 0 20 CHRIS 45.4 332.6 125 513 +1967 6 3 6 25 FLORENCE 61.7 307.4 159 0 +2004 10 21 12 7 WILLIAM 40.0 32.9 106 73 +1993 2 10 6 24 MICHAEL 48.9 180.1 126 702 +1985 11 17 12 2 HELENE 56.4 76.0 25 400 +1999 3 5 0 11 BERYL 31.7 23.8 77 460 +1953 1 17 12 22 ISAAC 69.5 163.5 45 713 +1950 5 26 12 4 MICHAEL 62.2 303.1 64 871 +1985 5 25 18 9 TONY 15.4 105.7 22 396 +1992 4 13 6 21 MICHAEL 64.9 137.3 57 362 +1995 9 21 18 3 MICHAEL 65.4 261.2 70 459 +1977 8 5 6 4 LESLIE 12.6 144.0 99 374 +1995 4 24 18 3 GORDON 22.8 320.1 82 848 +1975 8 10 6 11 PATTY 58.1 339.1 53 226 +1982 8 12 12 6 ERNESTO 38.4 282.1 130 150 +1956 4 16 18 22 NADINE 8.7 236.8 105 352 +1971 1 6 0 2 CHRIS 57.6 193.9 139 374 +1958 8 25 12 11 HELENE 65.8 298.0 114 89 +1988 7 1 6 27 PATTY 69.9 119.1 92 114 +1952 12 7 12 6 DEBBY 55.1 132.6 150 302 +1982 12 15 12 24 JOYCE 41.1 258.6 24 169 +1973 5 17 6 28 KIRK 13.2 333.6 30 184 +1993 4 25 18 25 RAFAEL 21.3 59.3 131 456 +1974 5 11 12 1 ALBERTO 36.2 75.1 75 52 +1986 6 17 0 28 ERNESTO 8.7 184.8 69 719 +1980 8 6 18 7 BERYL 8.1 80.2 22 390 +1951 1 11 0 13 GORDON 18.1 52.5 116 17 +1986 6 21 12 7 PATTY 60.5 212.0 57 395 +1993 12 22 18 14 RAFAEL 25.6 181.6 77 71 +1964 9 5 12 14 NADINE 42.2 85.2 79 865 +1977 2 2 6 13 SANDY 17.6 235.2 57 850 +1956 2 2 18 9 SANDY 11.7 279.3 29 218 +2000 3 4 0 6 CHRIS 12.2 33.9 144 15 +1953 1 17 6 19 VALERIE 57.2 179.2 48 146 +1969 10 27 12 18 LESLIE 7.5 29.9 152 820 +1986 4 24 6 22 PATTY 64.2 71.6 18 818 +1991 10 14 18 27 VALERIE 44.2 173.6 71 102 +2004 11 25 0 11 GORDON 29.5 345.2 74 778 +1992 7 13 12 21 ISAAC 17.4 354.8 36 54 +1979 12 18 6 20 TONY 17.6 122.7 58 764 +1990 5 13 12 5 WILLIAM 14.6 305.0 45 492 +1999 5 23 18 14 LESLIE 40.7 94.3 137 573 +1991 4 22 0 3 PATTY 51.8 312.2 151 270 +1967 12 1 12 21 RAFAEL 44.7 71.9 137 719 +2003 10 22 12 5 KIRK 55.2 113.8 47 694 +1964 8 19 0 25 HELENE 30.7 196.2 87 532 +1956 11 25 6 27 RAFAEL 11.3 161.1 109 381 +1992 8 4 6 17 VALERIE 21.5 140.3 150 102 +1966 2 9 12 17 BERYL 50.0 214.9 114 640 +1992 3 22 0 17 HELENE 57.1 256.3 23 660 +1969 8 27 6 17 LESLIE 62.1 139.6 46 83 +1954 12 13 6 11 HELENE 27.2 186.7 125 408 +1970 3 27 18 7 DEBBY 14.8 142.0 92 313 +1966 6 1 12 17 VALERIE 35.1 149.7 152 237 +1989 6 11 0 25 JOYCE 51.2 267.2 102 460 +1972 11 22 12 21 ISAAC 62.5 75.6 112 462 +1970 5 22 0 3 ALBERTO 8.8 287.8 66 135 +1953 1 8 6 4 CHRIS 59.5 156.5 94 145 +1951 8 18 0 20 RAFAEL 63.4 36.5 65 690 +1997 10 18 6 26 LESLIE 43.7 116.3 150 767 +1992 8 9 12 14 LESLIE 38.8 145.9 71 163 +1964 11 16 18 26 NADINE 46.3 226.1 85 302 +1973 1 12 18 9 WILLIAM 31.3 108.9 10 793 +1958 11 14 12 7 SANDY 24.2 239.3 72 269 +1953 12 9 0 15 WILLIAM 61.2 316.4 48 576 +1990 12 27 12 15 GORDON 44.9 90.8 16 330 +1951 6 1 12 10 ERNESTO 53.2 69.6 107 276 +1980 8 6 18 17 WILLIAM 34.2 73.4 157 511 +1961 12 21 18 17 MICHAEL 31.2 48.4 138 894 +1981 5 16 12 16 MICHAEL 50.9 326.0 160 303 +1999 10 14 12 4 WILLIAM 45.2 136.6 29 13 +2001 5 21 6 12 CHRIS 9.1 241.4 25 556 +1990 12 15 6 24 JOYCE 11.3 229.7 31 868 +1997 1 16 18 23 SANDY 33.6 10.1 43 553 +1988 9 14 12 27 RAFAEL 61.9 200.2 15 157 +1982 8 2 0 17 ALBERTO 23.6 117.7 111 315 +1961 11 27 6 3 GORDON 13.0 52.9 93 573 +1974 12 15 0 8 VALERIE 23.3 199.3 88 284 +1954 1 4 0 25 FLORENCE 60.0 247.2 157 289 +1995 7 17 12 23 KIRK 67.8 234.1 68 871 +1962 10 2 6 8 ISAAC 30.3 86.7 68 397 +1969 10 5 0 27 CHRIS 23.4 334.4 105 812 +1995 4 25 12 13 VALERIE 34.4 119.2 22 529 +1997 4 4 18 16 ALBERTO 25.7 339.6 12 434 +1983 2 17 18 23 ISAAC 15.0 197.5 117 235 +1985 8 9 12 7 DEBBY 65.1 354.7 149 762 +1950 2 23 0 6 GORDON 38.1 318.1 92 27 +2000 9 8 6 5 ERNESTO 7.9 297.9 137 763 +1961 3 1 12 5 CHRIS 41.2 154.2 76 143 +1955 4 22 12 18 VALERIE 62.6 119.0 141 671 +1954 5 5 0 21 SANDY 19.7 127.2 55 562 +1985 11 28 18 5 SANDY 31.0 143.4 158 556 +1959 6 24 6 10 RAFAEL 19.8 231.4 78 323 +1983 12 28 12 16 PATTY 37.0 261.3 99 152 +1978 3 11 12 27 ERNESTO 16.8 22.0 125 792 +1970 12 21 18 21 MICHAEL 58.7 90.5 141 111 +1953 1 9 18 13 LESLIE 23.3 33.5 64 375 +1996 5 17 12 19 ISAAC 40.3 85.1 80 325 +2004 2 28 0 4 MICHAEL 51.8 207.4 40 839 +1967 3 4 0 25 JOYCE 36.0 291.4 38 635 +1992 2 27 18 17 FLORENCE 42.1 137.4 136 28 +1975 1 21 12 4 BERYL 53.7 139.7 131 285 +1991 8 2 18 12 DEBBY 28.7 180.4 115 560 +1951 5 6 6 25 NADINE 38.3 337.6 149 193 +1988 3 4 12 7 MICHAEL 60.4 297.6 163 92 +1961 2 22 0 19 MICHAEL 10.1 252.1 49 822 +1997 3 9 0 9 MICHAEL 66.6 225.4 32 161 +1961 8 18 6 5 FLORENCE 45.9 158.6 31 668 +1955 2 19 12 15 HELENE 7.3 154.3 111 144 +1980 4 22 6 21 ALBERTO 51.9 318.8 128 573 +2003 11 18 12 26 ISAAC 49.0 305.7 109 857 +1994 6 4 0 23 GORDON 38.2 110.2 68 65 +1950 12 2 18 24 CHRIS 18.0 314.2 132 462 +1998 6 13 18 7 DEBBY 25.8 3.3 154 107 +1980 11 8 6 5 PATTY 18.8 12.9 99 123 +1989 12 4 6 18 WILLIAM 25.4 103.9 76 765 +1963 5 11 6 13 JOYCE 39.3 316.2 121 662 +1967 8 2 6 23 JOYCE 44.7 256.4 88 891 +1988 9 21 6 13 SANDY 44.2 37.8 60 553 +1956 3 14 12 24 WILLIAM 65.3 304.8 139 797 +1979 10 25 18 6 SANDY 7.6 122.1 19 778 +2001 11 3 6 24 ERNESTO 22.9 182.6 36 769 +1960 3 6 6 17 GORDON 67.9 9.7 154 629 +1985 8 9 12 20 JOYCE 64.3 351.7 48 298 +1980 7 7 18 2 GORDON 66.1 16.6 138 894 +1992 4 4 18 14 GORDON 43.5 189.0 126 418 +1982 8 26 6 10 ISAAC 8.1 31.8 108 625 +1994 4 18 0 9 HELENE 12.0 281.4 103 842 +1961 8 1 6 16 HELENE 19.0 231.7 61 148 +1980 6 16 12 4 VALERIE 69.3 283.9 48 89 +1991 8 26 18 6 LESLIE 33.2 9.6 95 147 +2002 1 17 0 15 MICHAEL 30.8 305.0 45 202 +1991 4 12 18 16 ISAAC 16.1 272.3 158 467 +1998 12 15 12 22 LESLIE 40.6 245.4 164 473 +1978 5 27 18 22 OSCAR 44.7 149.3 13 752 +1988 5 27 12 23 FLORENCE 33.1 301.6 48 401 +1967 10 13 18 28 ISAAC 44.3 285.0 82 149 +1995 12 17 12 12 TONY 22.5 27.6 110 318 +1956 1 24 0 17 RAFAEL 46.4 141.8 65 304 +1980 4 15 6 15 ALBERTO 20.8 57.3 56 878 +2000 5 19 6 10 KIRK 7.0 332.2 49 844 +1959 1 25 18 22 CHRIS 28.0 189.8 55 649 +1988 6 10 6 13 RAFAEL 20.3 264.9 76 23 +1961 4 10 6 23 OSCAR 17.4 86.6 116 257 +1958 4 21 6 10 ALBERTO 43.7 121.3 127 297 +1970 9 12 0 14 KIRK 20.1 113.6 62 463 +2003 7 13 6 22 ISAAC 47.3 325.1 89 621 +1958 11 5 18 27 DEBBY 10.0 293.4 59 650 +1973 9 6 18 11 SANDY 32.2 172.8 65 557 +1989 5 9 12 4 KIRK 62.9 145.6 13 73 +1968 6 6 12 18 LESLIE 54.1 302.4 102 32 +1951 2 12 0 25 RAFAEL 57.3 180.3 136 823 +1956 6 18 12 22 WILLIAM 14.2 213.4 147 372 +1989 2 24 18 12 OSCAR 24.7 63.6 52 480 +1985 2 20 0 5 JOYCE 58.7 191.7 51 508 +1996 9 16 12 5 TONY 36.2 118.8 95 123 +1972 1 23 18 12 ERNESTO 39.4 115.9 115 799 +1972 3 11 18 12 NADINE 61.7 143.6 53 487 +1954 3 22 18 25 HELENE 49.8 248.7 97 842 +1962 8 22 12 27 JOYCE 7.1 40.8 60 473 +1965 3 24 18 22 PATTY 32.7 8.2 75 104 +1968 6 5 0 3 ERNESTO 62.4 229.5 101 217 +1992 2 16 12 23 ISAAC 48.3 225.6 61 796 +1978 1 1 6 13 KIRK 43.9 109.5 13 833 +1995 2 3 6 18 CHRIS 65.0 77.6 72 849 +1966 11 4 18 9 KIRK 7.1 39.4 43 502 +1999 6 9 6 12 FLORENCE 18.3 301.1 112 54 +1977 11 27 18 1 GORDON 28.1 65.0 16 735 +1955 11 14 12 10 NADINE 68.7 219.4 53 576 +1957 1 15 6 6 SANDY 66.1 24.8 76 124 +1967 5 20 12 13 ERNESTO 27.3 106.8 154 653 +1996 9 10 18 26 ISAAC 43.6 70.6 131 287 +1987 12 25 0 14 BERYL 19.5 335.8 129 705 +1979 4 20 12 15 TONY 11.3 215.8 151 301 +1976 1 4 0 23 ALBERTO 13.6 53.8 136 22 +1978 5 23 12 13 FLORENCE 32.9 280.9 86 866 +2002 4 27 6 17 ERNESTO 20.3 140.9 69 321 +1959 12 21 6 28 SANDY 63.9 341.4 79 95 +1987 7 14 12 25 TONY 15.4 51.5 132 17 +2000 2 20 0 3 HELENE 56.3 49.7 68 773 +1962 11 6 0 13 GORDON 16.4 334.7 94 686 +1996 2 5 18 5 OSCAR 42.7 323.0 131 118 +1993 8 13 0 25 ALBERTO 12.1 270.5 148 872 +1991 9 20 0 10 KIRK 25.6 221.1 65 826 +1957 8 25 18 24 LESLIE 59.9 323.5 49 69 +1982 12 22 6 6 RAFAEL 62.3 146.4 60 715 +1958 12 23 12 28 WILLIAM 42.0 267.1 136 172 +1989 4 23 18 2 FLORENCE 49.5 59.8 95 609 +1951 5 14 6 26 DEBBY 50.7 137.2 161 52 +1969 12 19 6 24 BERYL 28.5 255.0 79 564 +1981 5 15 0 23 TONY 40.4 50.5 129 651 +1980 8 25 6 23 VALERIE 68.1 183.8 26 599 +1995 7 13 6 4 ISAAC 63.0 41.2 163 303 +1952 3 26 0 25 ISAAC 42.9 189.7 54 294 +1970 11 18 18 6 NADINE 44.0 160.2 74 595 +1961 8 4 6 9 VALERIE 29.6 247.3 15 350 +1951 10 23 6 21 HELENE 43.5 118.2 124 480 +1957 2 1 6 8 TONY 20.3 285.3 66 841 +2000 1 16 0 15 LESLIE 44.5 232.4 157 766 +1978 8 27 18 20 HELENE 28.4 74.3 78 58 +1960 8 14 12 15 PATTY 58.2 223.5 138 415 +1968 1 20 6 6 OSCAR 62.4 227.1 97 410 +1999 6 4 12 14 LESLIE 10.9 263.5 26 347 +1974 12 22 18 18 PATTY 59.2 205.4 90 93 +1995 1 28 0 19 PATTY 21.1 209.2 51 720 +1974 9 23 6 14 DEBBY 11.2 189.5 58 714 +1999 2 27 0 20 CHRIS 31.5 97.2 36 486 +1958 5 13 6 24 NADINE 66.7 32.8 31 821 +1966 7 17 12 9 FLORENCE 42.9 264.5 96 251 +1982 8 5 6 17 FLORENCE 60.4 172.7 39 29 +1994 2 26 18 26 TONY 39.0 334.5 83 220 +1962 2 14 12 5 KIRK 58.3 351.3 135 757 +1950 2 13 18 1 KIRK 69.6 35.6 82 358 +1992 7 22 18 15 RAFAEL 55.3 75.9 96 511 +1956 6 2 0 5 JOYCE 28.6 253.7 121 345 +1989 9 14 18 26 MICHAEL 22.9 174.7 150 808 +1975 9 2 0 21 PATTY 51.6 146.7 75 862 +1956 11 24 6 13 HELENE 60.8 250.7 18 460 +1970 8 6 6 27 BERYL 9.5 357.0 104 418 +1983 5 14 18 22 BERYL 59.3 345.7 109 551 +1992 7 14 6 7 KIRK 65.0 292.5 145 413 +1977 2 9 6 25 DEBBY 35.6 172.6 111 469 +1960 2 12 12 27 MICHAEL 62.5 12.4 55 426 +1988 5 20 0 3 MICHAEL 32.9 278.0 57 152 +1996 8 10 18 1 MICHAEL 50.0 228.8 49 284 +1961 3 22 6 18 CHRIS 28.7 246.0 107 362 +1969 2 22 6 8 ERNESTO 32.1 302.1 43 429 +1983 2 25 6 6 ISAAC 68.1 135.4 33 301 +2000 4 1 18 3 LESLIE 32.5 190.1 46 493 +1959 3 4 0 21 KIRK 45.6 200.7 25 79 +1998 11 6 12 27 DEBBY 53.1 189.4 163 95 +1972 12 4 12 11 DEBBY 8.9 269.0 28 86 +1990 1 18 6 10 RAFAEL 59.5 40.3 158 458 +1973 2 9 0 13 MICHAEL 46.7 34.1 38 382 +1962 3 17 12 18 FLORENCE 45.2 318.1 40 392 +1959 7 25 6 5 CHRIS 19.7 89.0 95 419 +1967 1 13 0 9 SANDY 8.2 64.5 84 93 +1980 12 11 18 27 TONY 33.3 336.9 43 707 +1965 4 16 0 19 WILLIAM 8.1 342.6 88 704 +1961 11 17 18 13 BERYL 21.6 290.4 113 600 +1967 9 15 6 9 OSCAR 28.8 37.4 158 111 +1980 3 15 12 11 FLORENCE 27.2 212.2 121 412 +1950 9 3 18 19 FLORENCE 32.5 59.5 118 131 +1977 3 14 0 2 ERNESTO 50.4 335.9 45 543 +1978 1 4 0 8 ISAAC 66.8 183.6 140 17 +1998 3 15 6 8 RAFAEL 37.9 46.7 65 167 +1997 8 16 12 3 RAFAEL 29.2 51.3 22 536 +1951 1 5 12 16 ALBERTO 63.5 291.6 147 865 +1968 12 17 6 26 ISAAC 7.7 311.3 89 317 +1953 6 16 12 7 KIRK 25.2 74.9 45 601 +1979 9 15 0 19 NADINE 40.0 344.9 48 854 +1984 5 13 0 9 NADINE 54.9 152.1 151 776 +2004 7 15 6 3 ISAAC 18.6 98.5 69 700 +1996 4 23 18 17 BERYL 55.8 153.5 31 453 +1970 3 19 6 4 JOYCE 58.6 10.7 128 250 +1997 3 20 18 13 KIRK 32.0 319.7 107 124 +1965 7 2 0 13 CHRIS 61.7 17.0 90 392 +1996 6 11 0 9 HELENE 28.0 344.1 105 464 +1970 2 8 6 20 DEBBY 42.5 321.5 108 319 +1978 4 2 18 11 HELENE 18.1 86.1 70 174 +1977 3 21 6 24 FLORENCE 62.1 87.1 52 563 +1989 1 14 0 20 MICHAEL 60.5 353.3 153 462 +1994 2 22 18 8 ALBERTO 26.1 236.9 92 850 +1960 3 20 0 8 KIRK 31.3 251.6 91 530 +1966 4 9 0 16 LESLIE 55.5 134.8 14 41 +2001 11 14 12 14 CHRIS 21.1 33.6 116 396 +2002 9 21 6 6 HELENE 47.9 111.0 66 194 +1960 4 4 12 27 RAFAEL 50.1 76.9 93 511 +1956 1 6 6 8 ISAAC 39.9 247.0 20 740 +1968 7 18 0 2 TONY 65.9 312.4 102 241 +1975 1 4 0 7 FLORENCE 10.8 155.7 129 350 +1969 9 5 12 10 JOYCE 57.3 156.9 53 498 +1985 5 1 6 3 LESLIE 45.5 225.4 36 463 +2002 6 22 18 7 ERNESTO 32.9 352.1 75 657 +1957 3 28 6 19 HELENE 17.6 65.7 139 260 +1951 2 25 0 4 OSCAR 13.8 160.9 107 108 +1982 6 15 0 4 ERNESTO 44.1 228.1 13 43 +1996 12 25 18 23 MICHAEL 45.6 39.2 123 768 +1960 11 28 18 23 ISAAC 34.0 77.9 155 710 +1987 10 3 0 6 ISAAC 12.8 18.7 110 568 +1973 2 19 0 21 RAFAEL 35.3 145.9 61 597 +2002 2 21 12 24 KIRK 14.3 285.8 76 682 +1991 4 18 18 12 ALBERTO 45.2 10.1 110 825 +1992 12 3 12 16 BERYL 43.2 40.8 64 763 +1966 5 15 6 16 TONY 49.6 133.7 109 444 +1979 3 27 6 25 KIRK 55.8 139.7 121 852 +1997 6 11 0 26 SANDY 54.9 193.4 40 382 +1990 10 23 6 7 LESLIE 51.8 45.6 112 568 +1956 3 8 12 23 NADINE 45.9 162.2 23 231 +1976 4 9 18 22 FLORENCE 17.5 331.1 41 626 +1992 2 22 18 22 ISAAC 36.3 289.6 46 889 +1966 1 9 12 2 ALBERTO 47.9 154.4 76 311 +1964 10 14 12 1 DEBBY 42.9 210.6 106 151 +1959 8 22 6 27 WILLIAM 53.8 98.9 31 260 +1964 10 18 0 11 TONY 54.6 239.7 10 436 +1983 1 9 0 11 CHRIS 50.9 324.5 13 674 +1990 10 6 6 17 NADINE 23.5 109.8 149 233 +1970 10 12 0 19 KIRK 33.7 15.8 157 777 +1994 8 15 6 9 CHRIS 53.2 265.8 28 273 +1966 7 28 6 10 OSCAR 28.1 240.9 44 573 +2003 12 6 0 1 ISAAC 17.9 241.1 33 489 +1971 8 5 6 17 CHRIS 68.5 277.1 121 404 +1981 12 7 0 18 RAFAEL 26.8 69.4 66 71 +1978 5 18 12 17 WILLIAM 17.9 83.3 129 719 +1966 8 18 0 13 TONY 66.2 40.7 73 821 +2002 1 16 12 20 ALBERTO 55.9 231.0 112 143 +1996 8 8 12 8 WILLIAM 31.0 218.9 141 549 +1971 11 24 0 17 HELENE 47.8 17.0 29 422 +1958 1 20 12 28 LESLIE 43.2 153.7 13 248 +1962 10 2 12 24 JOYCE 48.8 131.7 50 821 +1996 7 2 0 12 GORDON 56.4 113.4 53 806 +1967 7 25 0 19 CHRIS 67.4 211.9 149 600 +1969 6 13 12 24 OSCAR 35.1 133.0 119 797 +1988 8 21 18 21 FLORENCE 46.7 293.1 15 486 +1968 10 11 12 1 TONY 28.8 275.3 148 536 +1998 1 18 0 2 KIRK 15.3 94.3 142 633 +1957 2 14 18 7 FLORENCE 23.1 185.2 141 227 +1969 8 25 0 27 ALBERTO 69.1 332.7 107 201 +1978 12 27 0 22 JOYCE 61.0 15.9 14 77 +1956 3 21 12 23 HELENE 61.3 333.1 68 639 +1999 12 12 18 26 FLORENCE 27.4 280.0 44 833 +1989 6 7 6 16 DEBBY 51.9 142.9 94 616 +1961 12 14 6 26 JOYCE 17.9 28.7 71 807 +1956 12 17 0 23 SANDY 16.5 90.5 27 461 +1984 12 17 6 3 BERYL 21.8 9.7 54 354 +2003 9 10 0 13 PATTY 64.0 211.3 150 805 +1987 11 5 12 18 ERNESTO 39.8 202.7 91 574 +1951 11 9 18 22 OSCAR 51.0 75.8 85 765 +1995 8 3 12 28 NADINE 35.7 45.0 126 487 +1968 3 24 0 20 FLORENCE 58.1 321.3 51 412 +1970 3 8 0 2 VALERIE 23.2 44.0 79 426 +1966 10 11 6 22 LESLIE 33.0 353.9 68 382 +1986 1 28 0 4 ERNESTO 66.6 67.7 30 484 +1974 6 2 12 15 MICHAEL 44.3 215.9 38 666 +1962 9 20 6 25 GORDON 11.5 168.6 85 161 +1981 11 9 12 4 GORDON 54.3 125.8 66 151 +2001 1 6 0 3 ERNESTO 25.9 23.3 50 489 +1979 11 3 6 10 JOYCE 18.4 10.4 74 97 +1980 3 8 6 27 OSCAR 35.7 75.0 112 419 +1961 9 9 0 19 ISAAC 37.7 154.4 41 421 +1977 11 11 0 15 WILLIAM 8.7 283.2 55 177 +1984 8 7 6 26 KIRK 43.7 285.2 83 675 +1985 6 18 18 13 NADINE 59.9 161.7 152 633 +1968 1 16 18 6 OSCAR 47.8 266.5 81 897 +1972 1 6 0 10 BERYL 21.1 52.9 85 558 +1951 5 6 6 4 FLORENCE 19.2 346.1 33 302 +1982 11 13 0 26 MICHAEL 10.8 357.6 135 726 +1965 4 3 18 9 DEBBY 52.4 169.0 164 761 +1968 12 10 18 22 KIRK 9.1 52.6 125 631 +1959 7 16 18 22 JOYCE 54.3 24.7 46 367 +1955 7 18 12 21 PATTY 17.3 195.0 108 73 +1957 12 15 12 17 DEBBY 49.9 188.6 105 645 +1961 11 16 12 2 ISAAC 11.5 25.7 11 886 +1950 1 18 0 22 HELENE 51.5 344.3 143 34 +1995 3 10 18 23 RAFAEL 65.1 185.4 84 590 +1990 6 9 0 28 ISAAC 33.7 262.0 10 559 +1951 3 22 0 3 DEBBY 24.1 267.6 92 358 +1968 5 9 18 28 SANDY 7.3 271.9 142 804 +1982 2 21 6 2 PATTY 11.0 272.9 41 832 +2004 4 9 12 16 NADINE 67.7 280.5 24 827 +1976 4 19 6 6 OSCAR 51.8 170.5 15 539 +1996 3 12 18 8 NADINE 50.9 326.4 114 897 +2004 8 19 0 8 SANDY 37.7 90.9 114 672 +1969 7 18 6 28 TONY 63.7 133.5 40 424 +1986 9 18 0 21 CHRIS 22.6 244.4 157 648 +1977 4 28 12 6 JOYCE 12.8 302.1 92 685 +1952 6 3 18 1 TONY 20.2 41.4 79 291 +1967 6 8 12 10 VALERIE 19.3 65.0 36 475 +1958 5 24 18 16 LESLIE 59.2 354.2 117 857 +1985 8 25 6 9 BERYL 11.0 116.1 47 809 +2000 2 3 6 24 PATTY 8.6 201.7 124 144 +2002 6 7 18 17 OSCAR 65.9 127.0 128 438 +1982 2 4 0 21 SANDY 27.2 356.9 55 507 +1983 5 13 6 25 PATTY 53.3 289.3 35 553 +1982 4 25 0 8 SANDY 30.7 306.3 127 754 +1975 7 26 6 7 JOYCE 59.3 206.1 111 882 +1966 11 22 12 23 ISAAC 24.0 130.8 60 750 +1978 8 22 18 22 ISAAC 48.2 317.4 41 773 +1954 2 25 12 7 ISAAC 69.4 158.1 50 276 +1981 9 17 18 13 KIRK 62.8 327.9 12 198 +1988 3 10 0 22 BERYL 69.5 164.9 34 260 +1954 5 12 18 11 PATTY 56.9 84.2 35 361 +2000 1 15 12 20 GORDON 25.1 143.8 160 386 +1959 6 28 6 11 MICHAEL 37.9 308.7 141 266 +1989 4 22 0 20 OSCAR 12.7 355.6 152 738 +1978 5 11 0 15 NADINE 45.0 238.4 134 533 +1954 12 10 6 24 VALERIE 31.3 257.5 134 214 +1995 6 12 18 26 KIRK 54.5 208.8 75 52 +2000 3 22 18 12 MICHAEL 47.7 232.2 69 305 +1978 1 25 6 25 JOYCE 20.4 18.7 40 581 +1989 1 6 18 9 NADINE 24.6 170.0 70 227 +1985 6 24 6 11 CHRIS 58.9 89.2 113 858 +1962 11 3 12 14 MICHAEL 48.3 303.8 142 341 +1977 1 11 12 21 KIRK 13.4 140.7 133 762 +1996 11 12 18 25 SANDY 26.2 123.7 135 396 +1954 8 23 6 21 SANDY 58.5 265.8 61 15 +1993 10 27 0 15 DEBBY 39.4 140.9 53 320 +2001 4 18 12 11 ALBERTO 34.9 250.6 133 556 +1968 8 3 12 9 RAFAEL 16.7 312.3 66 854 +1955 1 15 6 27 HELENE 41.6 34.1 59 454 +1998 10 6 18 6 PATTY 9.6 14.2 66 204 +1970 4 14 6 7 CHRIS 32.8 107.3 64 230 +1988 2 20 12 1 VALERIE 56.8 130.5 160 34 +1976 11 19 18 21 NADINE 64.1 218.4 86 507 +1962 12 27 18 22 NADINE 51.8 84.3 102 808 +1961 12 13 0 22 PATTY 12.4 181.9 82 806 +1964 7 24 12 8 DEBBY 66.8 205.5 151 738 +1993 1 3 18 18 LESLIE 49.8 3.5 29 536 +1996 1 9 0 18 BERYL 39.4 101.5 160 125 +1970 4 17 12 16 GORDON 33.3 168.3 70 1 +1999 11 28 6 27 SANDY 26.5 81.3 159 127 +1995 5 7 12 19 LESLIE 26.3 180.3 107 179 +1960 2 3 18 12 RAFAEL 47.2 40.7 34 772 +1965 10 10 12 3 PATTY 56.5 34.3 129 660 +2003 5 24 0 28 JOYCE 44.3 248.9 125 376 +1964 3 3 18 18 NADINE 15.9 342.4 24 205 +1963 2 5 6 5 JOYCE 38.0 147.5 108 680 +1979 9 20 6 2 MICHAEL 53.4 210.2 33 428 +1991 7 7 18 7 PATTY 46.8 181.1 39 651 +1996 2 9 12 15 TONY 46.4 134.2 93 454 +1989 5 10 0 8 VALERIE 33.7 275.7 97 16 +1985 12 2 18 24 ERNESTO 62.6 108.0 78 467 +1977 9 23 0 23 RAFAEL 55.0 314.4 122 13 +1964 6 14 0 8 HELENE 43.4 73.6 61 354 +1994 11 23 18 14 ERNESTO 16.3 137.5 113 379 +1953 8 12 0 11 KIRK 47.6 126.3 63 628 +2002 5 13 18 7 JOYCE 54.5 283.0 116 655 +1974 11 21 12 12 BERYL 34.6 348.1 86 774 +1979 9 8 0 17 LESLIE 19.5 308.8 123 414 +1996 6 19 6 3 DEBBY 66.5 158.8 97 335 +2001 11 2 18 3 KIRK 58.9 178.2 21 348 +1971 6 1 0 2 HELENE 7.1 211.5 58 799 +1983 8 11 12 18 KIRK 27.1 159.5 31 23 +1985 2 22 18 7 CHRIS 15.5 65.0 22 25 +1955 11 27 12 3 MICHAEL 50.2 236.2 19 37 +1978 1 10 6 24 VALERIE 13.2 158.5 86 97 +2000 2 9 0 19 MICHAEL 43.4 339.2 53 640 +1973 3 13 6 11 ERNESTO 60.9 49.8 148 290 +1951 8 1 0 5 MICHAEL 56.5 309.4 150 77 +1968 7 16 12 7 ALBERTO 17.7 148.6 75 232 +1966 12 2 0 21 ERNESTO 38.0 151.2 69 159 +2004 11 17 18 16 PATTY 18.2 66.5 154 116 +1970 5 28 6 27 JOYCE 37.6 205.4 34 375 +1993 8 6 12 14 RAFAEL 64.0 45.8 160 616 +1983 5 25 0 21 ERNESTO 25.6 124.7 75 289 +1964 11 22 0 14 SANDY 11.0 22.8 102 506 +1987 1 20 0 18 JOYCE 53.6 204.9 89 0 +1967 2 17 12 2 TONY 29.8 339.9 15 273 +1974 6 22 12 19 BERYL 8.6 334.0 134 417 +1952 2 10 0 15 DEBBY 13.7 206.8 65 359 +1992 4 6 6 8 TONY 16.5 159.5 163 515 +1967 11 25 18 7 ALBERTO 21.9 293.0 41 341 +1998 3 24 6 3 RAFAEL 18.2 12.8 92 269 +1954 4 14 12 3 HELENE 30.1 248.1 73 600 +1977 11 3 6 25 VALERIE 43.8 124.0 71 864 +1958 2 9 12 4 KIRK 44.0 156.6 13 402 +1974 5 17 18 3 NADINE 29.9 338.9 49 73 +1966 12 9 12 21 SANDY 43.6 40.1 117 541 +1963 2 22 18 27 FLORENCE 60.1 207.1 45 467 +1955 6 24 6 11 ALBERTO 29.5 294.9 15 645 +1970 9 2 6 8 JOYCE 23.0 255.7 124 131 +1967 9 19 6 7 ERNESTO 56.5 309.0 46 371 +1961 7 19 6 21 HELENE 48.0 41.2 150 16 +1950 5 19 6 21 LESLIE 9.2 66.4 88 799 +1984 11 3 18 7 HELENE 15.0 356.3 33 572 +1984 12 5 12 12 MICHAEL 49.5 224.6 149 866 +1981 11 23 6 26 WILLIAM 40.2 230.0 51 369 +1951 5 2 0 6 RAFAEL 7.1 271.8 29 285 +1976 7 21 6 3 TONY 41.8 3.2 44 588 +1992 2 13 6 1 VALERIE 30.1 203.1 59 760 +2001 7 27 18 24 MICHAEL 48.4 258.9 47 774 +1967 9 19 12 23 CHRIS 35.6 296.9 158 360 +1973 2 22 0 22 FLORENCE 36.3 226.4 164 519 +2004 12 23 0 1 LESLIE 25.5 101.1 27 81 +1990 8 22 0 22 TONY 52.2 82.1 84 169 +1975 11 1 18 17 CHRIS 45.9 270.0 27 282 +1969 4 5 18 8 DEBBY 36.2 195.0 117 157 +1966 8 5 12 6 WILLIAM 17.4 349.4 63 857 +1998 12 23 6 25 TONY 66.2 325.2 67 257 +1997 10 9 0 16 PATTY 12.5 82.7 50 475 +1972 3 1 6 19 HELENE 20.3 97.2 134 723 +1988 10 1 6 13 MICHAEL 7.1 154.0 54 441 +1955 8 14 18 10 VALERIE 49.4 282.7 19 4 +1984 7 2 12 28 OSCAR 15.9 44.9 100 228 +1995 3 2 6 13 WILLIAM 66.3 54.7 134 444 +1969 8 3 6 15 ERNESTO 63.6 78.7 29 95 +1950 6 27 6 8 TONY 34.8 114.7 25 684 +1963 10 26 6 21 ALBERTO 60.8 333.9 160 136 +1991 4 14 0 2 ALBERTO 18.7 286.5 104 281 +1968 7 16 6 23 JOYCE 41.8 215.6 127 135 +1950 3 28 18 14 PATTY 17.3 108.0 10 221 +1999 11 25 18 26 MICHAEL 12.9 11.5 150 641 +1965 6 27 0 6 DEBBY 10.7 164.7 59 803 +1955 1 26 0 6 ERNESTO 12.6 202.0 155 435 +1968 11 22 18 11 DEBBY 30.0 202.2 116 283 +1995 5 15 0 4 WILLIAM 63.4 104.8 154 749 +1953 7 16 18 18 BERYL 50.3 266.4 54 518 +1972 1 14 0 19 WILLIAM 21.5 253.2 145 773 +1998 9 10 6 6 CHRIS 12.6 352.2 68 669 +1997 1 22 18 10 ERNESTO 68.4 239.5 60 743 +1979 7 9 6 12 CHRIS 64.4 90.9 122 153 +1994 12 4 6 18 HELENE 29.1 93.3 57 474 +2001 5 18 6 7 KIRK 64.7 24.0 87 201 +1980 7 10 12 27 DEBBY 59.9 62.2 17 455 +1991 3 8 6 14 ERNESTO 43.8 326.0 52 681 +1990 5 20 12 10 HELENE 41.0 214.5 113 132 +1958 9 24 12 24 SANDY 7.1 333.6 126 862 +1950 2 5 12 3 NADINE 23.3 220.2 64 594 +1988 4 6 0 9 TONY 26.7 210.6 16 434 +1968 12 10 18 21 BERYL 26.3 289.1 148 645 +1980 5 1 12 12 CHRIS 64.3 166.6 132 868 +1958 6 12 12 17 LESLIE 47.4 338.9 81 0 +1992 3 16 18 13 ALBERTO 36.7 65.7 51 608 +1958 10 6 6 12 CHRIS 50.5 103.5 26 7 +1969 9 18 12 11 LESLIE 44.9 223.2 135 193 +1955 11 5 0 20 ALBERTO 14.3 144.5 69 309 +1968 1 25 0 10 RAFAEL 61.0 357.4 43 659 +1962 8 22 0 13 OSCAR 25.1 53.8 60 348 +1961 12 18 6 6 MICHAEL 60.4 6.9 153 761 +1972 10 1 0 23 LESLIE 37.9 58.3 32 60 +1966 9 24 0 15 MICHAEL 15.1 208.1 98 627 +1972 3 14 12 26 RAFAEL 67.4 7.6 137 119 +1989 9 6 0 26 FLORENCE 65.1 206.0 157 79 +1994 9 17 0 11 CHRIS 66.9 259.8 129 258 +1985 10 12 12 9 DEBBY 41.3 106.5 10 129 +1982 6 26 18 22 SANDY 13.0 346.6 45 824 +1968 9 18 0 10 SANDY 25.8 249.3 155 793 +2003 7 7 12 2 ALBERTO 44.1 93.8 107 420 +1964 3 5 0 6 SANDY 53.2 328.9 22 641 +1950 7 17 12 24 CHRIS 66.3 234.5 56 715 +2000 11 28 0 24 VALERIE 56.2 21.2 97 606 +2002 12 14 0 6 HELENE 10.2 129.9 36 342 +2002 2 28 6 16 MICHAEL 57.8 328.0 39 24 +1984 1 15 0 14 GORDON 13.7 44.5 108 706 +1988 1 18 18 3 MICHAEL 27.1 302.4 50 179 +1967 3 16 6 19 LESLIE 66.4 244.8 32 801 +1969 4 27 6 15 MICHAEL 29.9 244.1 122 598 +1995 9 4 18 15 PATTY 61.5 60.7 17 840 +1997 5 22 6 13 OSCAR 8.6 125.0 47 840 +1971 3 4 12 4 FLORENCE 56.4 13.0 144 260 +1950 12 15 12 10 VALERIE 12.1 329.3 80 478 +1983 8 8 0 21 GORDON 58.4 333.9 43 76 +1997 5 11 18 16 CHRIS 63.5 152.1 13 48 +1982 6 20 18 10 WILLIAM 61.3 40.9 120 286 +1951 10 25 0 6 CHRIS 65.1 121.6 44 571 +1994 5 3 0 18 ISAAC 26.0 305.7 123 119 +1974 9 8 6 6 LESLIE 34.6 312.3 38 395 +1968 6 22 12 13 MICHAEL 18.0 280.2 142 491 +1968 6 23 12 13 VALERIE 10.6 281.0 74 461 +2002 12 3 18 16 ISAAC 12.5 272.0 41 580 +1990 7 3 18 3 SANDY 67.1 7.4 97 781 +1962 6 25 6 15 TONY 59.9 132.8 50 23 +1953 5 14 0 16 ALBERTO 52.8 183.2 142 89 +1996 2 5 18 22 LESLIE 26.1 70.4 127 132 +1988 2 4 6 6 KIRK 9.7 12.0 21 208 +1993 10 17 12 9 TONY 44.9 170.6 155 17 +1990 6 15 12 27 TONY 20.8 166.9 115 183 +1954 7 13 18 16 LESLIE 27.0 339.2 91 515 +1966 2 10 12 22 RAFAEL 16.0 207.4 64 446 +1957 3 11 6 25 HELENE 24.9 35.4 42 425 +1968 6 16 6 2 ERNESTO 64.2 49.2 57 170 +1989 6 25 18 12 WILLIAM 32.1 70.2 94 134 +1981 9 26 0 10 ISAAC 57.3 30.2 85 741 +1965 10 26 12 16 JOYCE 63.5 230.8 84 756 +1991 3 23 18 26 HELENE 60.2 120.4 62 267 +2002 10 23 12 14 NADINE 37.5 75.3 152 776 +1953 11 27 0 16 BERYL 12.4 240.7 44 120 +1962 10 5 18 5 RAFAEL 46.1 232.0 84 802 +1954 10 2 6 3 SANDY 59.5 234.6 153 79 +1975 8 4 12 19 GORDON 23.2 4.9 79 888 +1951 5 20 18 13 GORDON 9.0 347.2 144 603 +1962 11 18 0 3 OSCAR 10.3 350.3 90 616 +1993 6 16 6 4 GORDON 65.6 237.3 109 534 +1955 7 19 6 25 TONY 65.0 32.6 59 512 +1965 10 3 18 4 PATTY 11.1 249.9 68 98 +1962 12 13 12 12 WILLIAM 16.6 0.8 94 503 +1957 11 5 6 4 GORDON 55.9 244.2 29 730 +1992 1 15 0 20 NADINE 50.5 15.5 149 674 +1991 12 3 12 19 RAFAEL 47.7 226.1 159 653 +2000 10 15 6 10 VALERIE 41.0 268.9 145 69 +1978 7 27 0 10 JOYCE 48.9 76.9 76 79 +2000 12 9 18 17 MICHAEL 43.5 16.5 57 481 +1968 12 17 18 21 TONY 63.0 217.8 60 22 +1983 6 15 0 24 FLORENCE 52.9 192.8 141 25 +1992 6 25 18 17 BERYL 28.1 99.2 14 531 +1973 9 18 6 4 OSCAR 53.1 357.1 150 364 +2001 10 14 18 26 PATTY 30.7 30.3 121 558 +1975 9 16 18 18 LESLIE 46.3 17.6 144 406 +1970 10 10 6 20 OSCAR 69.4 291.6 161 642 +1999 9 15 12 5 KIRK 28.0 322.8 56 695 +1963 7 22 6 23 FLORENCE 36.3 31.4 89 364 +1976 2 26 6 25 CHRIS 33.8 166.3 96 519 +2000 3 20 6 14 DEBBY 50.4 153.2 64 383 +1974 2 10 12 27 DEBBY 68.3 242.5 77 2 +1968 4 12 0 6 NADINE 29.2 264.1 128 689 +1985 10 18 12 12 LESLIE 29.3 185.1 59 361 +1987 5 4 6 28 RAFAEL 15.0 313.1 96 332 +1964 5 25 0 3 BERYL 66.6 228.2 104 149 +1995 9 10 18 11 KIRK 47.0 37.8 121 551 +1974 3 17 12 13 ISAAC 21.0 117.2 16 71 +1962 3 20 12 13 LESLIE 19.5 138.8 62 364 +1991 6 27 0 22 MICHAEL 38.5 56.8 98 135 +1969 6 20 6 21 KIRK 66.8 272.8 94 118 +1997 2 24 0 19 ISAAC 43.7 113.9 151 398 +1978 10 19 6 21 MICHAEL 47.3 19.3 111 711 +1975 11 19 12 19 LESLIE 46.4 107.4 38 35 +1962 9 2 6 12 CHRIS 32.8 179.7 107 270 +1965 9 19 12 25 KIRK 40.0 328.3 110 392 +1961 7 25 0 23 DEBBY 68.7 130.9 134 491 +1964 11 26 12 5 OSCAR 20.7 291.6 54 77 +1969 7 2 6 2 RAFAEL 68.4 239.6 133 216 +1975 6 23 6 7 ERNESTO 32.2 352.8 28 400 +1993 7 20 0 10 DEBBY 7.6 180.7 76 96 +2002 7 2 18 16 DEBBY 17.6 49.7 151 393 +2002 7 17 0 10 KIRK 16.1 78.7 153 429 +2001 3 2 18 6 OSCAR 23.6 334.6 105 39 +2001 5 8 12 23 KIRK 53.0 213.8 140 312 +1971 3 25 12 3 ISAAC 53.7 327.0 51 857 +1951 5 24 12 13 FLORENCE 16.5 253.5 13 51 +1965 9 2 18 5 DEBBY 65.5 220.1 123 894 +1961 8 26 6 16 BERYL 69.0 181.7 68 439 +1959 9 11 0 25 RAFAEL 14.5 122.1 57 124 +1975 1 16 0 9 JOYCE 31.2 257.6 101 234 +1980 6 13 6 8 PATTY 62.6 46.2 151 312 +1952 8 26 12 17 NADINE 24.9 43.0 94 14 +1993 11 12 0 2 MICHAEL 41.0 218.6 33 179 +1978 6 23 12 5 TONY 32.4 244.3 153 520 +1996 1 24 0 7 ALBERTO 18.5 237.4 50 674 +1972 4 15 0 19 DEBBY 42.4 287.8 131 607 +1957 11 15 18 19 ISAAC 43.5 275.4 58 113 +1963 1 1 12 11 VALERIE 38.5 215.6 96 469 +1971 8 11 6 2 TONY 61.2 221.3 140 441 +1983 7 27 0 17 CHRIS 67.5 356.4 10 26 +1983 10 13 12 25 CHRIS 11.5 34.4 15 347 +1957 8 8 6 11 MICHAEL 53.7 60.7 97 409 +1985 10 8 6 28 GORDON 67.6 62.0 93 717 +1954 4 24 12 10 FLORENCE 35.5 86.7 163 88 +1990 1 28 0 2 FLORENCE 19.2 135.8 51 220 +1968 9 27 0 9 RAFAEL 16.7 6.8 100 575 +1996 4 27 12 21 JOYCE 57.8 35.7 32 137 +1985 1 1 12 17 JOYCE 28.1 206.4 70 804 +1959 3 1 6 21 WILLIAM 25.7 148.9 164 76 +1992 1 25 12 10 TONY 9.0 106.5 125 416 +1983 12 1 0 9 TONY 11.9 68.0 150 35 +1969 10 20 12 1 BERYL 55.1 65.9 129 503 +1991 1 6 12 20 ERNESTO 69.1 139.3 123 161 +1951 8 1 0 8 JOYCE 51.5 151.1 157 387 +1957 4 15 12 3 ALBERTO 36.9 233.4 93 878 +1984 3 18 6 22 KIRK 46.7 114.7 74 638 +1951 10 8 18 5 DEBBY 15.0 344.5 93 412 +1969 1 2 0 27 VALERIE 32.2 224.4 122 691 +1976 12 26 12 7 CHRIS 38.5 311.2 162 641 +1992 2 7 6 3 TONY 13.6 65.9 37 632 +1982 8 24 6 8 ERNESTO 36.4 330.9 103 348 +1957 1 24 12 1 ERNESTO 58.3 126.2 132 152 +1966 11 25 6 26 NADINE 16.8 189.3 43 542 +1966 3 25 12 21 GORDON 68.2 183.5 19 285 +2003 5 1 6 7 NADINE 28.3 231.2 107 217 +1970 2 14 0 15 OSCAR 25.9 145.6 145 409 +1997 4 3 6 10 RAFAEL 68.3 246.9 147 389 +1972 12 20 0 25 HELENE 51.6 31.1 71 823 +1969 2 2 12 5 HELENE 7.6 294.0 42 898 +1952 9 16 18 17 RAFAEL 43.8 183.0 72 320 +1977 10 23 0 25 SANDY 48.7 129.2 102 645 +1983 12 2 12 18 RAFAEL 9.1 207.5 142 215 +1967 2 9 0 1 JOYCE 65.1 322.4 106 362 +1979 3 24 0 11 JOYCE 26.5 135.1 135 72 +1965 12 3 6 28 NADINE 28.7 82.1 164 61 +1998 5 9 18 27 PATTY 28.1 56.6 136 309 +2000 7 6 18 26 PATTY 11.2 134.0 42 522 +1953 2 15 12 3 GORDON 7.1 90.5 128 252 +1975 10 10 12 15 LESLIE 31.0 101.2 48 672 +1975 7 24 18 1 ERNESTO 29.1 39.4 159 80 +1973 9 25 6 13 KIRK 11.3 216.4 140 434 +1980 3 26 18 28 SANDY 37.6 3.3 93 701 +1981 4 1 6 4 MICHAEL 13.6 143.8 104 602 +1987 5 19 6 12 OSCAR 60.5 213.0 46 307 +1975 3 15 0 11 CHRIS 37.2 177.9 126 459 +2001 12 2 0 1 FLORENCE 50.5 42.4 136 735 +1959 6 11 12 23 HELENE 36.0 155.1 131 453 +1978 1 24 18 11 OSCAR 50.6 111.5 86 237 +1989 9 11 18 2 VALERIE 68.2 162.3 150 20 +1981 12 22 12 24 ISAAC 48.5 37.9 159 449 +2003 4 19 6 23 FLORENCE 21.7 222.1 13 509 +1985 9 5 18 6 OSCAR 28.0 348.2 17 141 +1967 2 24 0 1 VALERIE 39.0 284.7 50 675 +1957 4 25 0 21 ERNESTO 17.6 183.6 11 495 +1969 10 4 12 23 LESLIE 43.4 340.2 121 498 +1950 1 3 0 9 GORDON 45.5 249.1 81 879 +1988 2 14 12 23 FLORENCE 50.5 54.8 91 102 +1970 12 13 0 7 JOYCE 34.9 161.3 46 623 +1978 5 28 18 9 NADINE 13.5 254.4 11 498 +1963 6 10 18 14 OSCAR 63.5 39.6 133 687 +1952 10 1 0 27 BERYL 28.4 339.0 156 306 +1983 10 8 6 27 KIRK 67.2 114.1 133 757 +1988 7 25 18 17 LESLIE 52.9 259.7 97 367 +1979 5 3 18 15 SANDY 60.3 302.6 27 708 +1975 1 15 0 5 OSCAR 59.3 283.8 20 890 +1983 12 4 12 7 OSCAR 24.1 51.9 126 732 +1975 12 16 0 25 ERNESTO 67.4 186.7 140 228 +1967 10 8 18 24 NADINE 35.6 314.1 135 106 +2002 2 1 18 19 ISAAC 50.2 217.4 73 29 +1982 9 26 12 27 DEBBY 41.5 234.2 120 862 +1955 5 8 12 21 ERNESTO 39.0 190.4 33 18 +1988 9 18 0 7 JOYCE 52.2 209.3 77 263 +1999 3 24 6 17 HELENE 69.3 166.7 70 375 +2001 7 26 6 16 ERNESTO 33.6 98.6 74 416 +1992 12 10 12 6 RAFAEL 20.1 5.1 14 208 +1987 10 20 12 16 MICHAEL 38.3 294.3 104 433 +1992 5 4 12 14 FLORENCE 19.0 20.2 156 633 +1998 8 18 6 25 PATTY 34.3 176.6 119 591 +1966 5 9 18 24 HELENE 61.8 148.8 122 435 +1999 10 14 12 18 ERNESTO 52.3 89.1 110 502 +1996 2 7 0 6 BERYL 25.2 46.6 29 317 +1958 6 13 18 22 ALBERTO 57.8 41.5 63 605 +1956 1 1 18 10 GORDON 12.9 74.0 82 346 +1964 9 28 18 25 WILLIAM 24.5 129.6 56 682 +1988 7 13 18 10 LESLIE 51.0 221.8 11 514 +1957 5 20 6 13 JOYCE 65.3 126.3 58 416 +1987 3 6 18 16 SANDY 62.0 216.0 117 77 +1954 10 9 0 10 VALERIE 13.1 216.1 88 680 +1979 6 27 6 13 FLORENCE 51.8 254.4 82 25 +1960 8 24 0 6 ISAAC 30.4 142.5 79 532 +1993 3 18 6 16 HELENE 58.0 171.7 126 269 +1996 9 25 12 8 PATTY 17.2 117.7 41 871 +1999 11 20 12 17 WILLIAM 64.5 162.8 129 270 +1965 2 11 6 7 BERYL 31.7 276.2 143 160 +1998 1 17 12 28 CHRIS 41.9 142.8 45 672 +1982 5 19 18 5 BERYL 40.8 271.8 14 209 +1950 6 9 6 1 CHRIS 31.9 347.2 125 501 +1957 10 17 18 15 HELENE 15.8 113.9 62 463 +1972 9 9 18 17 PATTY 63.6 163.2 114 483 +1958 11 25 18 17 OSCAR 59.3 328.6 146 266 +1992 6 10 12 12 WILLIAM 69.0 18.0 100 556 +1997 5 17 18 26 ALBERTO 49.7 108.4 57 624 +1988 8 12 12 25 BERYL 29.1 37.5 139 698 +1958 5 11 12 7 PATTY 34.1 261.8 131 142 +1950 4 26 6 2 GORDON 64.9 90.7 164 854 +2004 6 11 6 20 OSCAR 33.0 216.7 157 894 +1951 6 21 0 24 BERYL 46.1 12.6 28 717 +1955 3 8 6 12 ALBERTO 48.8 253.7 49 364 +2000 8 2 6 22 SANDY 56.6 343.2 23 688 +1988 3 21 0 14 HELENE 11.4 298.8 19 503 +1962 1 26 12 23 MICHAEL 32.3 274.8 89 786 +1992 1 11 0 9 JOYCE 58.5 59.9 64 267 +1971 11 4 12 12 NADINE 35.3 130.1 147 602 +1973 9 11 6 8 JOYCE 23.7 21.1 164 163 +1963 4 17 12 13 WILLIAM 8.9 171.1 164 79 +1991 4 12 0 3 MICHAEL 46.4 98.9 152 38 +1989 4 25 18 5 GORDON 39.3 354.7 60 54 +1960 1 9 18 9 NADINE 12.3 264.7 134 83 +1955 4 27 12 25 LESLIE 24.5 303.1 138 401 +1950 8 23 12 19 NADINE 14.6 71.1 119 65 +1961 5 26 12 3 ISAAC 8.0 295.5 81 522 +1967 2 3 12 11 KIRK 64.4 47.1 42 291 +2004 1 2 6 21 JOYCE 48.4 319.1 105 269 +2003 3 24 0 3 FLORENCE 24.8 132.7 151 42 +1980 3 17 0 25 HELENE 26.9 153.0 156 525 +2000 10 28 18 6 ERNESTO 10.2 87.6 63 685 +1985 11 25 18 27 SANDY 36.2 110.7 29 553 +1992 7 26 18 24 RAFAEL 10.5 112.4 42 2 +2002 5 15 18 24 NADINE 58.7 184.4 24 762 +1973 1 25 0 7 KIRK 8.5 148.8 160 151 +2004 2 16 12 26 LESLIE 58.9 23.4 82 218 +1950 11 14 0 28 MICHAEL 45.9 37.8 128 577 +1995 4 8 6 3 KIRK 68.4 275.9 83 811 +1996 8 2 12 18 JOYCE 11.9 256.2 37 355 +1968 6 23 18 25 KIRK 36.2 312.5 123 166 +1986 8 7 6 24 ERNESTO 32.3 305.7 144 505 +1967 5 8 0 15 ISAAC 66.9 25.2 53 607 +1971 12 10 12 4 HELENE 17.8 350.8 123 269 +1969 6 28 12 11 OSCAR 63.2 220.2 48 826 +1959 4 25 18 22 PATTY 55.4 329.8 152 644 +1986 7 12 6 26 MICHAEL 63.4 157.7 134 343 +1974 3 27 12 5 ALBERTO 15.3 74.0 80 849 +1963 3 5 0 6 TONY 9.7 203.5 120 42 +1951 2 11 6 16 PATTY 50.2 284.5 148 691 +1955 12 4 0 9 DEBBY 32.8 335.6 125 518 +1994 1 24 6 2 BERYL 44.2 282.2 116 81 +2004 1 12 0 28 SANDY 67.6 140.8 14 830 +1976 1 14 12 22 CHRIS 63.9 91.9 157 146 +1978 2 16 18 23 LESLIE 28.7 20.3 113 785 +1980 4 21 0 6 PATTY 58.2 271.6 82 893 +1976 7 11 0 23 OSCAR 56.8 62.8 69 801 +1971 4 22 18 7 KIRK 49.7 38.8 149 537 +1966 3 21 0 22 ISAAC 22.8 116.0 123 463 +1957 9 3 18 7 RAFAEL 25.2 203.0 100 98 +1989 3 20 12 8 RAFAEL 63.4 191.0 23 35 +1978 5 1 12 13 ISAAC 62.6 202.6 33 448 +1980 4 11 6 1 MICHAEL 10.5 354.0 135 185 +1962 9 17 0 9 RAFAEL 16.6 286.8 22 24 +1996 7 14 0 3 RAFAEL 46.2 180.7 149 512 +1959 8 20 0 15 HELENE 52.0 279.8 134 199 +1983 4 10 12 20 ALBERTO 16.7 128.1 144 590 +1956 10 26 0 25 BERYL 14.8 332.6 65 610 +1977 1 23 18 3 BERYL 63.7 42.5 42 793 +1980 11 16 12 15 BERYL 17.4 84.1 127 834 +1968 9 21 12 25 DEBBY 63.9 312.5 163 542 +1960 10 24 0 6 GORDON 49.4 190.8 60 730 +1963 2 5 18 3 ERNESTO 68.7 315.2 108 463 +1997 12 16 6 12 GORDON 30.0 148.7 106 195 +1999 11 27 0 16 PATTY 8.1 40.0 74 758 +1974 5 19 12 6 ERNESTO 65.8 252.6 76 95 +1959 8 9 0 2 JOYCE 38.6 247.0 152 483 +1992 10 16 12 5 TONY 11.0 184.8 86 439 +1968 7 19 6 7 RAFAEL 15.0 176.6 124 82 +1961 6 17 12 8 VALERIE 29.6 129.4 99 119 +1955 6 19 0 13 ERNESTO 67.8 84.8 113 443 +1953 7 8 0 20 HELENE 35.4 246.0 52 601 +1983 11 23 0 23 MICHAEL 23.5 329.3 14 584 +1956 10 2 0 8 CHRIS 21.7 137.5 49 549 +1957 10 16 6 24 ALBERTO 13.9 233.7 126 584 +1998 12 18 12 1 OSCAR 21.2 344.7 58 255 +1991 5 3 0 24 JOYCE 42.7 158.7 37 41 +1972 3 18 6 27 KIRK 7.7 221.8 164 764 +1953 7 13 0 19 WILLIAM 11.9 192.4 70 481 +1993 2 9 12 10 RAFAEL 36.0 30.4 137 537 +1970 12 7 6 22 MICHAEL 40.4 129.9 92 587 +1987 3 20 6 21 OSCAR 67.8 135.2 124 3 +1963 4 17 12 25 PATTY 60.2 21.8 59 422 +2001 12 12 6 2 CHRIS 47.2 45.8 59 872 +1954 8 9 6 19 SANDY 24.2 130.7 152 462 +1977 8 1 18 17 MICHAEL 26.7 58.1 44 555 +1953 10 12 6 6 MICHAEL 68.5 349.7 119 18 +1968 10 13 0 14 HELENE 22.7 109.9 61 643 +1984 8 17 18 5 HELENE 28.1 121.9 77 656 +1986 2 5 0 20 VALERIE 30.3 201.6 101 109 +1972 8 1 6 18 TONY 51.2 196.2 101 430 +2003 4 17 6 17 GORDON 16.4 9.9 86 84 +1987 9 21 18 4 CHRIS 13.6 308.2 127 701 +2001 1 1 12 26 ALBERTO 36.8 351.6 131 529 +1971 7 12 12 13 PATTY 20.3 27.6 41 444 +1966 5 7 0 26 NADINE 10.7 91.7 119 70 +1962 10 6 0 23 SANDY 18.7 149.9 43 129 +1958 10 27 18 21 KIRK 68.3 136.5 92 308 +1998 6 22 18 16 PATTY 69.0 174.8 43 285 +1995 4 2 12 21 PATTY 12.1 268.7 144 392 +1983 1 13 12 22 WILLIAM 28.6 266.0 66 441 +2000 10 12 0 9 NADINE 57.4 184.8 145 372 +1999 5 15 12 3 BERYL 66.7 134.6 115 604 +1950 4 13 6 28 PATTY 48.4 266.3 132 0 +1983 10 3 18 20 FLORENCE 60.2 304.7 41 556 +1983 2 23 12 9 OSCAR 11.6 73.9 128 416 +1962 5 22 12 2 CHRIS 36.1 143.6 71 374 +1969 3 12 6 1 OSCAR 22.0 193.0 141 212 +1954 2 1 18 12 DEBBY 19.7 106.6 138 111 +1989 12 24 6 5 ERNESTO 42.0 231.9 76 825 +1969 10 10 6 21 BERYL 59.1 208.6 102 748 +1960 1 6 12 21 OSCAR 68.0 298.6 128 172 +1970 8 12 6 23 LESLIE 53.7 6.6 37 572 +1980 12 27 18 14 LESLIE 57.6 46.5 150 383 +1955 7 14 12 1 LESLIE 21.9 184.7 40 866 +1967 12 6 12 15 JOYCE 62.3 307.4 37 635 +1990 3 10 12 12 KIRK 45.2 242.7 33 20 +1971 3 5 18 14 NADINE 8.9 199.0 117 198 +1957 1 23 18 26 MICHAEL 34.9 266.9 53 367 +1991 9 21 0 11 SANDY 64.7 140.3 145 639 +1996 12 3 6 7 WILLIAM 12.9 178.4 49 286 +1951 5 16 0 4 MICHAEL 53.7 84.9 102 228 +2003 6 23 18 2 PATTY 31.1 259.9 26 469 +1963 5 25 6 19 OSCAR 41.5 205.2 10 823 +1991 3 20 12 20 BERYL 19.7 350.6 120 754 +1986 6 2 0 7 KIRK 54.0 323.1 116 35 +1974 5 10 0 27 ALBERTO 8.0 156.1 15 549 +1972 9 6 12 11 DEBBY 34.8 154.7 26 18 +1988 2 10 0 28 MICHAEL 61.3 300.7 80 736 +2004 5 12 0 12 FLORENCE 69.5 187.6 122 483 +2004 9 24 12 2 HELENE 50.0 180.2 122 576 +1973 10 13 12 11 FLORENCE 18.2 36.5 20 293 +1990 2 7 6 5 NADINE 27.9 171.8 78 699 +1965 2 4 18 21 BERYL 26.7 49.9 70 208 +2000 11 25 18 13 MICHAEL 24.4 71.3 142 713 +1980 2 28 6 10 FLORENCE 16.5 311.5 162 641 +1968 10 23 6 14 BERYL 10.1 205.5 10 15 +2000 6 8 18 8 KIRK 15.8 164.6 73 451 +2001 8 15 6 28 ALBERTO 60.6 76.3 135 31 +1963 7 22 6 16 TONY 15.7 291.3 112 690 +1950 1 22 12 25 OSCAR 62.9 260.6 114 215 +1990 2 15 18 19 CHRIS 46.9 248.7 92 84 +1961 6 2 12 10 NADINE 40.6 171.4 50 694 +1951 7 15 12 3 RAFAEL 58.8 75.2 100 195 +1982 6 28 12 11 CHRIS 50.1 106.1 164 39 +1970 9 6 12 3 SANDY 66.3 8.3 134 262 +1996 6 18 0 5 DEBBY 9.6 239.2 119 771 +1981 12 9 12 8 TONY 20.6 254.1 89 2 +1955 10 16 6 25 PATTY 14.7 226.3 71 448 +1963 4 16 0 20 ERNESTO 36.9 265.2 123 22 +2002 3 19 18 22 JOYCE 65.7 53.7 29 821 +1953 11 21 0 19 HELENE 35.1 291.6 78 370 +1971 11 18 18 2 GORDON 41.5 262.4 130 158 +1973 10 5 0 11 LESLIE 33.7 206.2 153 633 +1975 7 16 18 7 OSCAR 9.4 335.4 141 181 +1957 7 6 6 14 WILLIAM 51.6 356.5 144 204 +1993 2 15 12 27 LESLIE 18.3 230.9 158 520 +1974 1 23 18 19 PATTY 34.0 302.9 23 22 +1995 12 27 0 7 RAFAEL 55.1 100.3 163 619 +1973 4 23 6 26 ERNESTO 48.4 14.3 92 395 +1977 4 23 12 6 DEBBY 8.7 125.1 73 583 +1993 5 18 12 4 MICHAEL 20.4 248.6 139 697 +2002 1 3 0 28 VALERIE 40.9 93.2 61 674 +1997 1 2 0 12 CHRIS 52.2 24.4 109 77 +1951 10 19 18 6 NADINE 65.5 155.6 118 356 +1965 6 27 6 23 FLORENCE 10.0 296.3 50 806 +1962 11 24 0 9 LESLIE 18.2 107.3 12 558 +1966 8 28 12 7 OSCAR 53.5 269.5 96 792 +1998 1 19 6 26 GORDON 16.0 211.4 140 775 +1955 10 19 18 6 ERNESTO 59.8 144.3 39 26 +1989 4 26 12 8 LESLIE 17.1 110.2 31 563 +1961 11 11 18 5 TONY 49.3 2.1 144 585 +1953 11 1 6 15 RAFAEL 55.2 38.0 99 711 +2003 12 22 6 4 ALBERTO 26.2 284.7 98 642 +1994 6 10 6 3 WILLIAM 53.9 169.7 62 627 +1979 8 3 12 21 RAFAEL 55.0 174.6 102 729 +1976 9 22 0 16 GORDON 11.2 119.3 77 895 +1999 12 27 18 27 MICHAEL 17.9 28.9 155 258 +2002 2 19 18 4 HELENE 46.0 273.7 76 126 +1994 6 7 18 22 RAFAEL 17.8 94.4 151 736 +1955 11 2 12 21 GORDON 13.9 20.2 74 261 +1983 6 24 0 12 JOYCE 27.0 141.2 114 29 +1995 1 26 6 22 KIRK 61.2 21.3 89 195 +1992 1 5 12 15 ERNESTO 36.1 142.8 124 165 +1975 10 16 6 26 ERNESTO 63.9 26.8 56 249 +1979 5 12 12 28 GORDON 48.4 348.8 67 461 +1951 3 5 0 11 ERNESTO 60.6 285.1 67 335 +1966 3 16 0 18 VALERIE 51.2 315.7 88 305 +1997 10 18 12 3 DEBBY 14.9 66.8 108 656 +1993 3 16 6 3 VALERIE 39.0 98.4 155 636 +1995 2 2 12 23 JOYCE 56.2 257.7 131 244 +1981 12 13 12 11 HELENE 30.5 355.4 48 17 +1977 4 13 0 23 DEBBY 35.1 147.2 12 740 +1993 2 27 18 7 ERNESTO 28.4 139.8 145 515 +1968 11 6 18 16 PATTY 24.4 354.0 98 370 +1983 10 22 18 15 JOYCE 12.6 71.1 147 583 +1956 10 14 0 2 NADINE 47.2 229.5 137 82 +1997 7 12 6 4 FLORENCE 49.1 285.8 159 339 +1987 12 16 6 5 KIRK 24.3 305.9 126 568 +2002 3 22 6 4 PATTY 36.3 4.0 112 804 +1995 6 10 6 14 RAFAEL 22.6 264.7 87 224 +1965 11 24 0 8 VALERIE 30.0 309.0 120 880 +2004 11 2 0 14 JOYCE 37.6 243.0 93 321 +1973 11 28 12 6 DEBBY 63.6 224.6 98 787 +1973 3 22 0 5 ALBERTO 11.4 79.2 18 234 +1971 10 28 0 11 CHRIS 44.7 238.8 87 28 +1964 3 19 12 20 ISAAC 61.2 287.2 62 83 +1954 4 28 18 13 FLORENCE 51.7 67.2 106 563 +1967 6 17 0 23 OSCAR 49.5 344.3 144 453 +1982 4 1 18 27 MICHAEL 8.7 222.2 123 274 +1976 2 3 18 23 MICHAEL 53.0 154.7 34 626 +1974 1 11 6 3 WILLIAM 25.2 129.1 157 769 +1951 8 2 6 6 CHRIS 31.1 138.9 24 401 +1972 6 18 0 17 MICHAEL 24.6 157.4 43 115 +1985 3 26 0 2 TONY 38.9 192.3 146 607 +1987 5 16 12 23 ALBERTO 53.4 282.4 17 470 +1971 11 10 12 11 DEBBY 9.8 244.3 54 165 +1969 9 10 0 24 KIRK 46.1 153.1 69 129 +1980 6 13 12 15 PATTY 28.3 110.8 114 728 +1981 5 12 0 20 HELENE 45.3 117.5 103 858 +1950 10 7 0 16 VALERIE 45.5 261.3 38 783 +1960 12 28 0 2 HELENE 49.3 171.1 10 752 +1999 8 11 12 23 KIRK 59.9 334.9 44 236 +1965 3 24 0 5 PATTY 49.8 26.9 17 506 +1985 1 4 0 26 RAFAEL 36.9 338.5 88 850 +1996 7 26 18 6 PATTY 58.4 287.3 153 676 +1987 4 20 0 10 PATTY 60.3 151.9 120 32 +1969 11 9 18 22 JOYCE 57.2 4.0 156 433 +1971 3 22 18 17 ERNESTO 44.1 141.2 84 773 +1967 4 7 0 18 MICHAEL 58.5 314.3 98 379 +1967 1 16 12 8 GORDON 34.8 2.6 92 681 +1977 11 14 6 5 NADINE 29.3 232.7 151 891 +1958 10 9 6 2 ISAAC 12.4 215.0 46 531 +1951 11 19 18 28 MICHAEL 66.4 57.0 91 223 +1956 12 5 12 16 BERYL 20.0 25.1 51 881 +1983 6 25 6 7 WILLIAM 10.8 356.8 64 887 +1982 6 5 6 24 ERNESTO 25.0 223.8 17 408 +2001 9 16 12 27 VALERIE 9.1 10.0 114 827 +1972 10 5 18 17 JOYCE 32.2 136.2 10 849 +1980 10 25 6 23 ERNESTO 15.3 112.5 30 840 +2003 4 9 12 4 NADINE 27.0 137.0 43 426 +1995 8 10 6 26 WILLIAM 46.4 321.2 31 309 +1967 9 19 0 10 ALBERTO 16.9 308.3 42 467 +1978 7 22 0 2 KIRK 9.3 156.3 53 582 +1990 9 16 6 12 NADINE 58.1 182.2 45 159 +1986 2 26 12 27 NADINE 37.6 180.9 11 705 +1972 7 22 0 7 ISAAC 17.4 87.0 68 39 +1987 12 25 12 4 ERNESTO 32.0 107.3 59 481 +1992 5 1 18 11 ISAAC 69.6 132.6 75 672 +1953 6 1 6 28 WILLIAM 44.7 126.3 19 879 +1989 7 28 12 13 FLORENCE 13.8 164.5 146 340 +2001 1 16 6 3 KIRK 46.3 179.6 53 755 +2001 7 11 12 8 SANDY 40.8 94.8 71 743 +1952 12 12 6 20 DEBBY 35.7 340.6 74 684 +1998 2 17 12 24 TONY 60.2 131.7 104 14 +1989 6 2 12 11 JOYCE 69.1 357.5 25 528 +2003 1 15 6 1 OSCAR 23.4 220.5 79 79 +1984 3 21 6 6 DEBBY 35.5 188.3 77 764 +1979 9 27 18 21 FLORENCE 68.0 262.1 120 157 +1980 10 9 0 7 JOYCE 16.5 57.3 124 420 +1976 3 14 12 28 VALERIE 38.6 112.5 152 832 +2000 10 24 12 4 VALERIE 52.9 21.0 133 102 +2004 12 24 18 28 TONY 24.5 262.4 101 303 +1989 2 2 12 7 ERNESTO 53.4 160.1 65 667 +1998 6 19 18 13 PATTY 17.8 298.9 102 361 +1951 3 26 12 16 TONY 20.9 223.7 154 200 +1993 6 21 12 24 NADINE 54.7 227.1 76 811 +1992 5 8 0 25 ALBERTO 51.4 38.8 72 624 +1983 3 14 0 2 ERNESTO 15.5 73.3 108 820 +1964 3 28 6 18 DEBBY 51.5 200.8 67 878 +1989 6 6 12 21 CHRIS 25.8 317.6 52 792 +1950 1 20 0 21 VALERIE 16.3 42.4 66 500 +1986 10 12 0 13 MICHAEL 64.6 174.2 64 0 +1976 3 24 6 10 KIRK 7.3 92.4 91 259 +1982 10 19 0 3 PATTY 38.4 339.9 75 840 +1998 5 15 12 5 GORDON 42.0 132.3 123 605 +1959 5 22 12 18 FLORENCE 38.4 13.5 153 581 +1977 11 18 6 15 ERNESTO 65.5 4.0 19 874 +1984 6 9 6 24 ERNESTO 45.6 286.1 124 155 +1959 8 11 0 3 BERYL 47.5 75.2 36 893 +1999 4 10 18 4 PATTY 37.4 356.8 90 797 +1964 9 13 18 13 KIRK 60.8 30.3 56 651 +1976 7 16 0 5 BERYL 54.7 91.1 24 12 +1965 12 17 6 22 RAFAEL 56.9 127.2 125 67 +1977 12 1 0 12 HELENE 37.2 9.9 61 695 +1976 10 6 6 1 ALBERTO 56.3 281.7 86 782 +1966 11 20 18 17 RAFAEL 9.5 69.4 153 482 +1976 7 16 12 14 JOYCE 57.1 129.7 75 789 +1978 4 13 6 25 ERNESTO 66.2 302.7 70 150 +1984 6 22 12 12 PATTY 43.4 225.5 87 340 +1958 3 22 0 17 MICHAEL 20.2 136.9 29 695 +1974 7 24 18 6 HELENE 29.8 76.7 113 816 +1987 3 3 18 27 TONY 44.9 177.2 86 29 +2000 11 3 18 16 LESLIE 57.7 225.0 106 616 +1983 1 9 6 23 JOYCE 51.3 204.3 44 522 +1973 5 16 18 18 ISAAC 39.1 298.9 43 205 +1964 8 14 18 5 LESLIE 28.8 336.5 122 51 +1986 8 14 12 23 ISAAC 36.7 18.8 163 788 +1982 10 19 18 22 GORDON 52.0 212.7 30 62 +1961 5 28 18 9 SANDY 50.7 72.1 46 807 +1966 9 25 18 5 PATTY 38.7 122.4 121 563 +1962 9 9 12 11 OSCAR 23.0 228.7 110 754 +1991 2 28 12 9 GORDON 47.3 213.9 33 311 +1958 5 16 0 11 RAFAEL 19.8 53.7 14 101 +1983 7 26 18 19 KIRK 49.3 133.0 145 815 +1978 5 5 12 27 MICHAEL 61.5 202.5 126 224 +2001 4 19 18 19 LESLIE 42.9 35.6 163 120 +1974 4 13 6 9 VALERIE 28.6 46.0 14 634 +1994 12 19 0 5 NADINE 18.8 61.7 41 623 +1960 4 8 18 26 SANDY 19.0 309.8 86 797 +1958 5 25 18 10 JOYCE 34.7 290.4 17 670 +1959 8 8 12 14 DEBBY 39.1 34.7 152 543 +1997 7 3 18 7 TONY 44.4 149.0 111 160 +1977 4 28 6 7 HELENE 57.0 321.5 42 879 +1981 9 7 18 14 FLORENCE 62.1 186.4 45 314 +1988 1 25 18 18 MICHAEL 65.8 51.2 52 419 +1996 7 4 18 14 TONY 66.5 56.5 49 196 +1956 9 21 12 6 ALBERTO 25.5 185.1 119 452 +2002 10 26 0 25 HELENE 29.4 323.9 119 358 +1952 1 25 0 26 ERNESTO 29.0 185.8 75 796 +1983 12 15 18 10 ERNESTO 47.0 64.6 44 228 +1975 2 16 0 17 ISAAC 55.2 81.2 144 727 +1962 3 20 0 15 TONY 17.0 185.3 112 566 +1956 9 3 12 25 PATTY 59.8 104.6 94 493 +1969 12 28 0 7 OSCAR 9.7 273.5 78 697 +1974 10 23 0 1 WILLIAM 14.4 153.2 82 823 +1970 3 4 6 9 ALBERTO 41.9 87.0 26 465 +1977 2 5 6 12 FLORENCE 50.4 291.2 98 717 +1993 7 20 12 28 ALBERTO 39.5 234.7 28 718 +1981 3 13 0 20 SANDY 62.1 208.8 78 784 +1971 9 20 0 6 TONY 64.4 60.5 50 143 +1976 6 16 12 19 TONY 49.8 310.9 156 709 +1975 7 4 0 17 ERNESTO 52.0 304.9 54 487 +1952 5 8 12 14 CHRIS 53.2 243.2 22 354 +1990 1 27 12 22 SANDY 65.8 162.7 164 372 +1997 11 12 12 3 VALERIE 8.0 53.4 91 534 +1977 9 9 18 18 TONY 16.1 78.8 145 690 +1955 1 12 12 24 DEBBY 62.6 326.5 64 422 +1988 5 11 0 18 ERNESTO 57.7 163.7 58 130 +1982 1 9 18 20 TONY 25.4 271.3 152 73 +1972 2 22 12 24 NADINE 13.9 177.8 95 384 +1986 2 22 0 21 KIRK 8.7 319.2 74 316 +1956 5 22 6 14 BERYL 38.4 244.8 67 361 +2004 12 24 12 18 RAFAEL 36.2 33.4 68 423 +2000 4 4 6 7 SANDY 40.2 40.7 148 276 +1967 3 21 12 10 CHRIS 16.0 221.3 40 195 +1987 3 12 12 3 BERYL 24.9 135.8 108 673 +1965 3 20 6 14 TONY 57.6 174.9 35 886 +1997 7 15 6 21 LESLIE 44.1 51.7 138 665 +1995 5 13 18 6 MICHAEL 37.0 350.8 66 63 +1955 12 14 12 22 GORDON 17.9 93.2 62 871 +1997 4 4 18 12 CHRIS 56.7 226.1 117 124 +1994 3 25 18 26 KIRK 45.3 144.1 142 63 +1958 5 17 18 16 MICHAEL 39.7 283.0 98 780 +1997 12 20 12 13 ERNESTO 63.3 29.7 134 564 +1978 12 4 18 19 BERYL 61.0 184.7 53 35 +1977 9 3 12 19 LESLIE 56.0 104.6 43 24 +1954 4 23 18 7 KIRK 33.1 149.6 51 204 +1980 2 15 12 9 BERYL 26.8 12.7 48 710 +1954 11 21 0 18 RAFAEL 65.6 231.6 66 865 +1963 5 2 12 4 ALBERTO 34.2 85.1 25 829 +1976 11 7 6 22 DEBBY 18.8 14.9 29 481 +1991 7 15 18 5 MICHAEL 65.9 257.2 29 407 +1983 11 2 18 16 GORDON 24.9 273.1 52 449 +1986 5 23 6 28 ALBERTO 26.1 304.4 69 130 +1999 11 21 0 5 BERYL 32.9 238.3 66 538 +1966 6 19 6 1 NADINE 44.9 176.1 98 540 +2001 2 4 12 24 DEBBY 67.4 167.2 150 143 +2003 3 22 18 23 JOYCE 68.9 278.3 114 258 +1975 8 4 0 20 LESLIE 58.6 49.3 18 106 +1977 4 19 0 9 FLORENCE 20.5 204.3 45 174 +1962 11 23 0 27 SANDY 17.0 216.2 159 870 +1979 8 15 0 16 KIRK 20.3 146.5 99 440 +1984 12 15 12 28 ISAAC 48.5 163.5 114 272 +1964 6 15 6 12 TONY 59.6 357.9 125 496 +2002 3 16 6 8 WILLIAM 43.1 352.5 157 473 +1991 4 8 0 23 LESLIE 11.7 302.0 10 813 +2004 10 6 6 11 GORDON 61.7 162.4 43 619 +1962 8 21 12 4 HELENE 17.4 98.6 32 257 +2004 12 19 6 15 MICHAEL 51.5 91.4 95 595 +1986 2 23 12 3 JOYCE 67.0 104.8 124 689 +1987 1 16 12 11 KIRK 13.2 320.0 80 431 +1987 3 6 12 4 GORDON 53.6 301.6 120 785 +1969 9 5 12 10 TONY 58.4 310.1 95 523 +1968 8 2 12 9 PATTY 48.7 243.1 102 810 +1977 3 12 18 3 GORDON 9.0 174.7 27 275 +1950 12 21 6 11 LESLIE 69.9 64.7 10 779 +1959 11 18 6 21 DEBBY 21.2 178.0 114 817 +1951 5 4 12 9 PATTY 37.8 109.8 136 747 +1958 4 15 18 26 MICHAEL 45.3 187.4 91 798 +1969 8 7 0 2 ISAAC 17.3 66.9 91 150 +1994 5 9 0 22 ALBERTO 22.8 112.5 135 779 +1982 3 19 18 10 PATTY 10.0 262.0 148 474 +1984 12 12 0 5 BERYL 69.7 42.6 64 347 +2001 4 10 0 7 RAFAEL 12.5 114.2 64 493 +1967 2 12 12 2 OSCAR 68.3 267.8 94 829 +1970 6 25 6 13 SANDY 43.0 211.5 103 533 +1978 2 26 18 12 HELENE 42.8 201.7 11 718 +1955 7 10 12 27 ERNESTO 66.3 28.2 98 278 +1973 11 16 12 12 WILLIAM 67.8 131.0 30 829 +1950 11 9 12 3 ALBERTO 60.3 12.9 152 694 +1966 10 15 0 14 JOYCE 48.2 106.2 145 553 +1997 2 13 6 18 KIRK 28.7 289.8 23 845 +1975 9 2 0 23 ISAAC 50.9 200.1 66 201 +1959 8 26 18 26 ERNESTO 33.0 138.1 35 657 +1984 4 20 6 11 DEBBY 26.5 20.1 40 676 +1992 6 22 18 11 NADINE 24.6 201.0 62 247 +1964 8 24 12 20 GORDON 40.3 284.3 155 214 +1952 7 14 0 19 ISAAC 52.3 185.3 55 84 +1962 6 12 6 13 PATTY 61.2 347.9 80 888 +1983 1 23 6 20 VALERIE 22.9 135.6 69 69 +1973 10 15 12 24 PATTY 19.1 84.0 25 612 +1969 4 11 0 8 TONY 19.8 277.9 44 14 +1985 9 12 18 17 ISAAC 66.5 180.7 96 757 +1951 10 24 0 3 GORDON 26.3 64.4 32 809 +1990 12 2 0 19 SANDY 42.7 177.7 156 666 +1991 6 28 0 8 FLORENCE 21.0 55.2 35 209 +1977 6 8 12 24 DEBBY 52.3 355.6 75 776 +1984 8 7 0 2 VALERIE 13.7 353.4 119 825 +1981 10 2 12 11 DEBBY 25.1 143.0 162 786 +1968 10 15 12 11 OSCAR 50.0 192.5 18 555 +1960 3 15 12 4 LESLIE 16.3 128.3 26 798 +1968 9 18 0 24 NADINE 41.5 118.0 16 317 +1962 10 22 12 11 CHRIS 54.2 50.8 70 576 +1983 6 23 12 18 SANDY 23.3 291.9 36 394 +1967 11 7 12 8 BERYL 8.8 321.8 57 267 +1975 11 19 18 23 ERNESTO 33.0 347.8 112 410 +1977 11 3 0 9 VALERIE 38.9 10.6 105 232 +1998 6 12 12 27 CHRIS 47.7 223.2 47 389 +1950 1 18 6 11 KIRK 27.6 18.6 19 18 +2003 2 2 0 2 SANDY 34.0 173.7 78 51 +1990 10 22 0 22 TONY 60.2 166.0 44 265 +2000 11 5 0 28 SANDY 41.1 91.0 86 227 +1984 8 6 0 3 ERNESTO 51.5 308.6 53 424 +1958 5 6 6 16 LESLIE 38.7 338.1 150 81 +1967 2 13 0 10 ALBERTO 12.8 328.3 137 137 +1995 10 21 0 15 LESLIE 37.1 185.4 111 491 +1983 10 2 18 13 TONY 62.2 52.4 96 381 +1985 8 27 18 24 ISAAC 14.6 268.5 48 426 +1989 6 28 18 7 NADINE 10.2 186.9 96 834 +1989 9 26 18 3 OSCAR 65.5 92.0 103 167 +1985 12 5 6 12 DEBBY 42.6 160.4 164 417 +1978 1 10 12 12 ERNESTO 54.2 59.6 111 307 +1995 6 15 18 24 PATTY 31.9 154.0 154 23 +2003 3 23 18 9 ALBERTO 34.8 64.7 160 59 +1990 1 17 18 11 ERNESTO 24.2 288.6 103 381 +1967 1 23 0 13 MICHAEL 43.5 341.6 25 655 +1950 10 25 6 19 DEBBY 18.9 164.0 13 709 +1956 2 24 18 22 ERNESTO 16.7 21.3 57 81 +1956 10 3 18 19 KIRK 64.8 180.9 136 170 +1986 9 4 6 9 LESLIE 59.0 206.6 128 477 +1965 3 16 0 11 GORDON 48.0 36.6 149 524 +1991 6 20 18 25 MICHAEL 56.1 87.5 140 108 +1958 2 11 18 16 TONY 39.6 74.3 144 284 +1963 2 15 0 2 HELENE 12.4 73.3 106 797 +1990 3 28 18 28 OSCAR 65.1 60.5 22 615 +1989 12 11 18 1 NADINE 10.1 172.8 76 215 +1975 4 17 18 5 DEBBY 35.6 43.4 57 483 +1975 8 27 18 13 CHRIS 65.0 18.3 61 888 +1977 8 27 18 22 ALBERTO 48.0 94.2 51 152 +1971 12 13 0 17 JOYCE 34.8 8.4 127 319 +1976 5 25 6 10 NADINE 57.9 138.2 35 5 +1960 2 17 0 17 ALBERTO 12.9 16.1 68 102 +1960 5 22 12 26 DEBBY 43.5 154.8 149 881 +1961 2 8 18 2 RAFAEL 39.9 98.5 94 87 +2004 6 1 12 6 MICHAEL 40.4 327.8 89 330 +1985 8 21 12 6 KIRK 40.7 98.1 126 855 +1963 8 13 12 1 WILLIAM 58.7 28.6 126 795 +1981 4 4 18 27 VALERIE 38.8 219.7 101 382 +1957 6 11 0 16 RAFAEL 26.2 42.0 85 183 +1995 12 24 12 10 WILLIAM 60.0 37.8 147 319 +1985 1 28 0 7 ISAAC 63.9 346.9 163 854 +1979 10 10 6 21 BERYL 63.8 89.9 126 508 +1968 10 28 18 19 ISAAC 58.8 307.2 38 449 +1986 9 19 12 22 ERNESTO 42.2 117.5 115 353 +1976 9 15 0 21 KIRK 51.8 305.3 102 889 +1983 10 3 6 24 BERYL 21.3 314.1 105 885 +1975 3 13 12 21 KIRK 56.9 302.0 25 177 +1963 12 5 18 28 ALBERTO 29.4 3.9 72 470 +1974 7 27 12 8 SANDY 17.8 64.3 52 331 +2000 4 26 6 7 VALERIE 41.7 220.9 148 501 +1957 7 8 0 2 VALERIE 68.1 224.7 136 259 +1956 1 5 18 1 KIRK 46.8 263.6 21 785 +1995 10 5 6 9 OSCAR 34.4 194.4 158 809 +1983 9 13 18 17 CHRIS 19.7 110.3 137 782 +1987 3 4 18 2 SANDY 17.1 147.2 37 364 +1952 4 2 18 17 RAFAEL 32.9 268.0 36 547 +1965 3 21 0 15 RAFAEL 57.0 228.9 148 347 +1968 10 12 0 14 ALBERTO 41.9 238.3 108 459 +1964 4 12 18 17 MICHAEL 68.9 255.8 27 431 +1950 7 5 12 18 ERNESTO 32.6 328.4 27 623 +1989 2 8 18 24 ERNESTO 21.5 354.0 145 766 +1975 3 2 0 26 MICHAEL 22.8 271.9 111 412 +1957 7 7 18 8 ISAAC 50.4 149.8 113 708 +1983 9 24 12 6 BERYL 65.3 356.6 119 870 +1969 6 12 18 2 DEBBY 61.0 15.5 52 644 +1989 4 1 12 18 DEBBY 27.5 135.8 151 612 +1975 10 26 0 13 HELENE 25.2 288.8 31 713 +1986 11 4 18 28 OSCAR 15.2 331.6 19 753 +1963 5 8 6 27 WILLIAM 27.3 105.3 63 77 +1984 6 21 12 20 VALERIE 33.9 333.6 105 372 +1952 8 2 6 19 LESLIE 15.8 348.6 51 894 +1981 4 9 12 7 ISAAC 39.6 131.7 119 610 +1980 6 24 18 16 OSCAR 41.6 253.5 156 624 +1999 2 5 0 19 CHRIS 9.6 329.9 13 363 +1962 9 8 0 17 ISAAC 66.7 118.8 136 45 +1957 11 15 12 28 BERYL 41.3 115.1 156 340 +1968 3 4 6 22 MICHAEL 64.1 331.8 104 477 +1953 10 13 12 20 MICHAEL 61.6 41.0 55 435 +1955 1 27 18 15 PATTY 16.3 57.6 136 438 +1951 6 5 6 9 KIRK 63.1 316.6 93 535 +1983 8 12 6 9 LESLIE 49.1 303.3 152 316 +1987 10 12 12 5 TONY 51.2 128.7 148 409 +1975 2 7 12 1 OSCAR 18.5 338.9 146 273 +1980 3 28 0 21 WILLIAM 58.5 73.8 160 779 +1990 8 17 18 8 DEBBY 54.1 187.9 14 343 +1961 7 5 0 5 JOYCE 39.9 30.3 62 188 +1969 5 27 6 28 GORDON 11.9 355.2 161 580 +1976 11 3 12 22 SANDY 33.1 95.5 37 177 +1994 8 21 18 13 TONY 25.2 182.1 143 363 +1991 6 11 0 15 JOYCE 42.5 154.7 74 727 +1985 1 13 18 6 ERNESTO 13.8 355.0 94 29 +2000 3 24 6 9 WILLIAM 55.6 30.8 137 394 +1962 4 20 6 23 PATTY 23.6 112.5 105 155 +1996 10 20 0 7 SANDY 47.4 353.7 96 849 +1984 7 5 6 18 LESLIE 40.2 182.9 100 89 +1967 4 10 0 21 GORDON 41.1 320.4 148 465 +1998 7 22 12 4 RAFAEL 57.6 27.6 103 890 +2000 1 12 6 20 VALERIE 58.2 112.2 142 732 +1975 1 13 18 20 TONY 65.9 325.8 71 14 +1953 11 26 6 7 JOYCE 7.1 160.5 103 393 +1988 8 10 18 8 MICHAEL 22.4 106.5 135 229 +1957 1 22 0 6 ISAAC 9.9 189.5 163 569 +1965 3 22 0 1 KIRK 27.5 232.3 160 633 +1985 4 18 12 13 TONY 59.4 37.2 84 422 +1989 1 25 0 13 RAFAEL 32.3 142.7 143 61 +1953 12 22 0 3 BERYL 55.4 340.5 33 540 +1961 5 22 6 6 FLORENCE 57.7 6.2 56 540 +1953 6 28 18 1 HELENE 31.1 337.0 149 663 +1959 5 10 6 5 CHRIS 33.8 277.0 69 868 +2004 11 8 12 7 HELENE 47.1 6.0 119 184 +1951 4 19 0 1 PATTY 48.8 281.7 125 313 +1969 10 2 12 17 JOYCE 24.2 25.4 153 867 +1955 5 25 6 27 WILLIAM 7.4 49.6 10 407 +1954 10 2 6 7 DEBBY 40.1 284.5 82 150 +1972 12 9 0 11 BERYL 35.6 63.5 138 147 +1988 3 2 12 19 SANDY 56.6 78.2 164 263 +1999 10 22 12 25 OSCAR 33.4 203.8 78 427 +1953 5 15 0 13 PATTY 30.8 118.2 124 196 +2002 1 19 0 20 DEBBY 56.7 242.6 111 698 +1995 12 23 12 1 DEBBY 24.3 320.0 129 30 +1966 11 26 6 23 MICHAEL 63.1 183.4 146 619 +1995 10 20 12 10 BERYL 26.7 254.5 91 4 +1950 7 12 18 3 BERYL 53.0 121.4 90 714 +1963 10 13 6 5 HELENE 50.1 315.2 151 828 +2001 1 19 6 4 ISAAC 28.6 224.5 81 780 +1996 9 7 12 20 WILLIAM 48.6 39.3 48 567 +1999 8 21 6 19 NADINE 8.3 282.9 43 712 +2004 4 9 6 9 NADINE 33.4 306.7 24 355 +1951 5 9 6 21 MICHAEL 67.4 102.5 109 808 +1985 5 1 6 25 TONY 14.1 296.7 162 472 +1961 10 19 12 6 MICHAEL 12.3 97.7 161 516 +1993 10 11 18 7 HELENE 12.7 138.7 11 854 +1958 3 14 6 5 BERYL 69.4 349.3 123 52 +1961 7 9 12 18 OSCAR 44.1 15.7 123 99 +1999 3 7 6 7 KIRK 32.4 41.0 98 77 +1975 6 4 6 25 SANDY 69.1 64.3 122 287 +1958 12 14 0 24 ERNESTO 16.2 235.9 70 519 +1980 11 11 12 24 GORDON 21.1 325.9 45 868 +2002 6 28 18 12 ALBERTO 26.9 173.9 61 658 +1978 6 13 6 28 NADINE 36.6 112.3 158 289 +1954 6 12 6 12 VALERIE 30.9 96.8 127 576 +1977 12 11 18 28 MICHAEL 60.3 11.7 106 625 +1958 9 10 18 12 WILLIAM 29.6 213.3 124 189 +1951 11 15 0 3 CHRIS 27.9 57.3 143 476 +1982 12 8 18 18 GORDON 63.2 254.7 29 633 +1954 8 19 18 28 MICHAEL 63.3 220.4 129 688 +1975 4 24 12 10 ERNESTO 68.6 193.5 102 664 +1963 12 12 18 6 NADINE 26.2 230.8 149 463 +1969 12 11 0 26 NADINE 13.4 90.5 122 353 +1954 9 5 18 27 BERYL 21.2 284.3 159 839 +1954 3 19 0 1 TONY 19.5 45.3 80 793 +2003 8 24 0 27 WILLIAM 40.7 86.0 15 598 +1966 7 6 18 22 ERNESTO 58.2 224.3 82 561 +1962 9 4 0 23 VALERIE 30.1 305.2 144 583 +1965 8 7 6 10 LESLIE 36.1 170.2 118 187 +1979 4 21 0 28 TONY 57.8 19.3 100 748 +1997 2 7 18 14 CHRIS 48.9 101.9 97 189 +1997 5 28 18 14 VALERIE 33.1 284.4 90 740 +1982 6 17 0 15 LESLIE 60.9 117.4 52 566 +1996 4 22 12 17 BERYL 51.7 121.3 161 894 +1991 7 15 0 13 GORDON 66.0 2.7 127 298 +1971 9 20 6 27 RAFAEL 16.0 212.9 62 190 +1983 3 16 12 17 ERNESTO 13.0 21.3 16 361 +1955 1 1 12 21 BERYL 11.9 33.8 52 570 +1987 5 12 6 22 ALBERTO 39.2 118.2 162 740 +1990 10 13 12 1 RAFAEL 20.0 28.7 58 756 +1990 3 5 12 23 PATTY 51.0 30.8 45 3 +1997 2 18 6 8 VALERIE 20.5 150.3 41 584 +1971 6 12 18 21 ISAAC 39.3 32.8 101 820 +1988 9 10 18 4 ERNESTO 48.9 210.2 111 235 +1969 4 16 12 2 TONY 23.4 10.7 77 402 +1951 7 1 0 11 HELENE 48.8 247.1 101 785 +2004 2 18 0 14 ERNESTO 28.2 170.2 16 783 +1972 2 27 6 28 LESLIE 50.8 119.2 17 425 +1997 10 9 12 15 VALERIE 58.3 283.9 115 2 +1950 2 15 6 16 NADINE 50.2 100.2 129 698 +1964 3 16 18 7 JOYCE 65.7 160.1 29 457 +1977 12 8 6 1 KIRK 68.9 173.2 36 67 +1990 10 10 6 25 ISAAC 34.5 301.2 134 533 +1997 12 25 12 13 WILLIAM 51.6 10.8 17 420 +1993 1 28 0 19 MICHAEL 23.3 178.2 100 870 +1955 3 8 6 26 WILLIAM 44.5 254.6 123 170 +1973 12 19 18 15 NADINE 39.2 171.8 109 290 +1968 12 20 6 25 LESLIE 22.6 24.0 84 730 +1979 12 1 18 23 ERNESTO 10.7 69.4 72 322 +1999 9 14 12 12 TONY 44.3 327.9 80 205 +1980 1 17 18 4 DEBBY 59.0 97.8 116 65 +1967 11 11 6 26 GORDON 65.0 356.4 145 431 +1965 3 27 18 22 JOYCE 51.8 55.5 147 259 +1995 5 9 18 2 MICHAEL 25.4 240.6 52 752 +1958 8 17 12 24 CHRIS 55.4 4.5 106 669 +1959 10 26 18 22 CHRIS 10.7 230.0 97 505 +1990 3 5 6 2 ALBERTO 7.6 265.8 10 270 +1962 9 21 18 17 ISAAC 13.8 17.1 116 119 +1998 2 22 0 24 NADINE 24.2 198.2 42 461 +2002 4 18 0 25 ERNESTO 22.1 265.8 33 867 +1978 8 12 6 25 BERYL 7.9 57.6 131 258 +2002 12 1 0 14 SANDY 51.1 16.6 164 762 +2003 7 15 0 22 RAFAEL 19.5 353.2 44 860 +1969 6 26 6 23 KIRK 25.8 166.0 47 548 +2002 8 27 0 15 TONY 26.7 43.4 38 228 +1984 9 26 6 12 VALERIE 58.9 56.2 160 206 +1975 12 1 6 28 BERYL 55.5 34.6 113 620 +1969 2 16 0 3 ALBERTO 44.9 205.5 127 811 +1955 6 17 0 13 ERNESTO 55.1 42.0 140 489 +1990 1 4 0 4 CHRIS 50.6 194.7 45 468 +1950 11 16 12 13 VALERIE 26.2 295.9 82 265 +1999 5 20 0 16 JOYCE 62.9 226.8 25 354 +1965 2 19 18 6 ISAAC 56.3 11.5 81 745 +1999 1 19 0 15 RAFAEL 55.2 83.0 68 254 +2002 6 1 12 10 PATTY 63.2 111.8 10 632 +1979 11 9 0 18 DEBBY 48.3 32.7 101 388 +1975 3 5 6 25 NADINE 49.1 246.9 54 238 +1959 12 22 0 15 NADINE 12.5 53.6 40 510 +1979 3 19 6 2 ISAAC 11.4 15.6 48 409 +1956 6 2 12 26 VALERIE 44.3 21.6 77 413 +1982 5 26 12 9 SANDY 34.0 58.1 101 577 +1990 4 6 18 6 MICHAEL 30.8 281.0 41 822 +1972 9 26 6 18 RAFAEL 55.3 214.6 68 505 +1990 1 5 12 8 LESLIE 57.6 328.0 140 521 +1951 7 9 0 9 HELENE 24.8 337.8 26 758 +1956 4 5 0 24 FLORENCE 69.4 67.1 113 372 +1951 7 3 0 8 HELENE 35.9 161.4 89 33 +1997 7 1 18 15 NADINE 64.8 284.7 101 155 +1970 1 17 18 11 ISAAC 33.2 75.9 48 717 +1950 12 21 12 13 ERNESTO 16.3 207.1 103 469 +1965 8 16 6 10 HELENE 37.3 21.8 147 111 +1994 12 22 0 10 VALERIE 25.8 201.6 100 530 +1968 8 5 6 12 WILLIAM 15.4 63.8 141 14 +1991 6 26 0 14 KIRK 62.9 177.5 44 708 +1953 11 27 6 5 WILLIAM 34.9 248.8 98 273 +1967 4 23 12 9 PATTY 55.7 81.1 17 638 +1955 5 12 12 6 OSCAR 23.8 236.1 147 819 +1966 5 3 6 17 DEBBY 40.4 61.8 149 738 +1992 1 26 6 19 BERYL 69.1 75.8 149 470 +1965 6 8 6 19 ISAAC 55.2 347.5 65 665 +1955 11 19 12 24 OSCAR 32.5 85.8 90 121 +1977 6 7 6 21 CHRIS 59.1 33.4 71 525 +1964 6 12 0 5 VALERIE 28.9 165.4 150 269 +1959 9 18 6 7 LESLIE 30.3 152.3 60 312 +1965 7 9 6 25 GORDON 56.9 254.6 37 346 +1997 9 4 18 13 KIRK 58.1 251.4 73 713 +1981 2 19 18 15 BERYL 11.9 231.7 69 299 +1978 6 28 18 5 BERYL 53.4 233.0 37 347 +1994 9 14 18 6 CHRIS 63.5 169.9 128 16 +1960 5 10 18 13 PATTY 67.1 289.9 63 613 +1998 12 27 18 9 NADINE 40.4 143.2 34 757 +2002 10 3 0 9 HELENE 36.4 89.3 144 731 +1982 6 22 12 20 TONY 14.5 23.8 159 521 +1980 5 3 0 8 HELENE 58.9 324.1 100 712 +2000 8 17 0 17 VALERIE 34.0 47.0 136 167 +2002 3 11 0 9 VALERIE 14.6 36.2 107 95 +1965 2 6 18 17 BERYL 10.7 351.3 72 35 +1956 3 14 12 20 DEBBY 33.1 127.1 109 395 +1964 1 16 6 5 OSCAR 45.4 291.1 153 390 +1984 10 1 6 9 CHRIS 51.0 351.5 126 312 +1981 3 24 6 20 ALBERTO 26.2 145.7 13 777 +1998 11 21 6 22 DEBBY 33.5 89.1 20 303 +1955 7 18 18 1 JOYCE 52.1 286.2 35 807 +1996 5 24 6 21 HELENE 63.3 15.1 124 840 +1980 10 21 6 22 FLORENCE 39.0 271.9 13 675 +1953 6 10 6 13 OSCAR 38.9 288.6 121 62 +1963 5 8 0 21 VALERIE 45.3 312.2 64 795 +1981 5 11 6 12 BERYL 16.1 324.2 106 514 +2004 2 7 6 6 CHRIS 7.0 268.8 74 868 +1996 12 7 12 1 HELENE 9.2 172.4 139 641 +2004 12 25 12 22 PATTY 47.5 290.0 16 723 +1954 9 10 12 16 NADINE 10.3 305.9 127 271 +1973 7 3 18 27 TONY 28.5 284.0 112 486 +1997 6 23 0 13 KIRK 59.4 243.3 22 442 +1973 11 10 12 7 CHRIS 27.9 253.5 62 225 +1955 12 9 12 5 FLORENCE 35.2 198.7 118 366 +1971 6 9 6 10 ERNESTO 54.4 200.0 148 252 +1989 2 25 6 2 FLORENCE 21.0 210.0 63 39 +1986 11 6 12 25 CHRIS 45.1 265.6 125 347 +1953 3 13 0 24 NADINE 45.5 65.7 21 462 +1987 2 14 12 1 KIRK 28.2 250.0 65 125 +1987 5 8 0 22 VALERIE 42.5 95.6 107 344 +1982 6 2 0 15 JOYCE 28.1 33.6 67 741 +1988 3 15 0 10 RAFAEL 27.0 351.0 15 886 +1975 5 7 0 28 TONY 65.9 69.5 51 209 +1974 6 8 12 18 ERNESTO 17.1 175.4 79 506 +1985 10 23 18 19 GORDON 23.7 119.7 103 226 +1961 12 6 6 21 TONY 36.8 346.7 123 53 +1970 12 18 12 1 MICHAEL 69.9 225.2 91 741 +1996 9 16 6 9 CHRIS 44.1 129.7 140 73 +1983 10 12 0 15 LESLIE 68.7 307.1 161 486 +1951 6 14 0 5 NADINE 52.5 78.6 48 584 +2000 12 28 0 12 TONY 13.9 260.6 118 446 +1960 11 14 0 14 FLORENCE 65.5 272.9 94 512 +1974 9 20 18 22 BERYL 61.9 279.9 106 849 +1973 2 9 6 19 SANDY 48.0 296.2 124 136 +2003 1 7 18 16 RAFAEL 58.8 217.2 90 550 +1977 6 3 18 20 OSCAR 36.6 183.4 28 813 +2001 2 15 18 19 HELENE 9.4 284.5 48 163 +2000 6 15 0 17 ERNESTO 30.9 84.3 78 60 +1963 1 1 6 18 BERYL 58.4 319.5 143 409 +1992 10 27 6 28 FLORENCE 7.7 194.9 83 400 +1977 5 19 18 9 KIRK 66.6 33.9 84 608 +1961 7 15 0 17 SANDY 9.2 328.4 104 687 +1965 1 22 0 12 TONY 7.1 285.4 16 235 +1994 12 18 0 16 FLORENCE 24.9 225.7 87 83 +1980 7 22 12 7 WILLIAM 58.3 120.3 21 255 +1965 11 5 12 18 PATTY 46.1 76.7 115 299 +1951 7 9 18 1 ERNESTO 8.8 91.2 68 582 +1957 2 5 0 21 LESLIE 33.0 153.0 109 593 +1959 3 8 6 6 PATTY 27.2 281.2 45 699 +1967 4 2 6 4 ISAAC 19.8 151.7 105 325 +1969 11 21 6 11 VALERIE 21.7 170.9 152 19 +1957 1 13 18 5 ALBERTO 49.2 230.7 37 272 +1964 3 20 12 2 VALERIE 58.8 231.9 53 791 +1986 7 19 12 26 NADINE 46.1 33.7 92 854 +1999 8 21 0 24 ERNESTO 54.0 333.8 63 138 +1976 10 25 0 14 KIRK 65.2 55.0 75 755 +1953 6 5 0 13 ALBERTO 60.4 214.7 60 383 +1953 12 4 12 28 HELENE 43.6 107.1 43 68 +1950 10 26 12 7 LESLIE 14.1 158.5 39 874 +1964 5 18 6 16 BERYL 14.5 199.0 72 635 +2000 8 10 6 25 BERYL 42.8 343.0 33 774 +1959 8 8 0 1 ALBERTO 65.3 294.7 63 373 +1982 5 14 6 21 DEBBY 65.7 44.0 114 648 +1982 5 13 0 19 KIRK 23.3 347.4 21 425 +1967 5 23 6 9 WILLIAM 13.9 311.4 62 418 +1988 12 5 0 22 ALBERTO 38.2 124.3 127 595 +1998 1 1 18 6 WILLIAM 26.7 321.9 96 241 +1985 8 19 6 12 ISAAC 11.9 50.5 128 90 +1985 12 17 0 12 FLORENCE 63.9 282.9 108 711 +1974 9 17 12 11 ISAAC 61.7 191.6 163 412 +1954 8 24 0 24 LESLIE 13.1 357.5 130 304 +1983 8 14 12 12 HELENE 65.0 147.8 136 883 +1977 3 7 0 2 TONY 35.3 337.2 32 657 +1966 3 1 12 17 FLORENCE 57.3 232.8 133 767 +1980 9 12 6 6 PATTY 56.7 62.6 42 473 +1998 1 2 12 12 WILLIAM 37.2 348.6 82 517 +1980 1 10 0 28 KIRK 51.0 14.7 147 549 +1994 2 11 18 24 MICHAEL 68.3 105.2 45 874 +1952 10 4 0 5 SANDY 46.8 78.9 37 577 +1953 12 6 18 22 ALBERTO 14.5 268.8 85 246 +1957 10 7 0 12 SANDY 21.4 345.2 47 353 +1996 6 7 6 25 CHRIS 31.2 330.5 40 27 +1997 3 9 18 22 LESLIE 56.7 84.4 117 485 +1963 5 9 0 23 GORDON 21.2 32.3 97 304 +1998 9 20 0 13 VALERIE 55.3 224.5 91 893 +1995 11 8 18 2 TONY 52.1 3.0 114 823 +1997 4 21 0 16 GORDON 43.2 193.9 48 599 +2004 7 5 12 12 FLORENCE 38.9 216.6 135 768 +1950 1 22 0 10 ERNESTO 26.0 100.1 129 617 +1992 3 4 12 4 BERYL 44.1 222.4 27 279 +1965 7 5 0 21 ALBERTO 60.2 78.6 68 133 +1952 4 23 6 1 WILLIAM 62.6 32.5 23 769 +1988 11 3 6 20 RAFAEL 12.7 27.3 30 451 +1977 5 3 6 2 CHRIS 25.6 143.7 97 761 +1977 10 17 18 1 SANDY 30.2 65.6 99 290 +1956 11 28 0 23 PATTY 16.7 92.1 143 809 +1954 11 7 12 12 FLORENCE 62.7 194.5 138 422 +1993 6 24 6 21 JOYCE 20.9 318.6 124 633 +1968 7 9 12 25 GORDON 12.7 148.7 73 798 +2003 7 15 6 3 RAFAEL 50.0 139.1 62 560 +1987 1 26 12 8 BERYL 69.2 247.7 77 170 +1999 3 20 6 13 ISAAC 35.6 190.9 32 251 +1983 6 16 0 17 HELENE 39.5 168.9 24 395 +1997 1 17 12 28 BERYL 27.6 96.5 127 850 +1960 12 15 12 26 CHRIS 39.4 156.5 162 580 +1984 7 28 0 20 HELENE 11.1 111.7 83 53 +1953 12 8 12 8 FLORENCE 23.5 251.3 75 568 +1968 12 11 6 12 RAFAEL 8.8 201.0 102 698 +1994 1 3 18 17 ALBERTO 25.4 335.0 61 676 +1969 12 17 12 22 JOYCE 61.3 304.3 18 646 +1982 7 10 0 28 KIRK 21.0 357.2 116 310 +1990 2 23 18 22 NADINE 46.3 204.1 76 293 +1981 7 25 6 8 JOYCE 7.4 353.9 141 302 +1972 1 24 0 14 PATTY 23.5 110.5 138 797 +1979 12 15 6 8 MICHAEL 42.9 257.6 47 706 +1958 8 13 18 21 VALERIE 45.0 344.7 38 552 +1963 5 13 0 6 ERNESTO 48.6 70.8 50 221 +1955 8 12 0 15 LESLIE 15.7 10.4 47 642 +1960 1 1 18 9 LESLIE 49.4 291.9 91 512 +1965 8 20 6 4 LESLIE 11.9 36.3 39 304 +1993 7 4 18 14 RAFAEL 24.7 254.4 88 234 +1995 4 12 0 15 NADINE 17.5 67.5 107 574 +1967 5 19 0 27 JOYCE 51.7 146.9 120 205 +1966 4 20 0 22 RAFAEL 68.8 105.7 151 33 +1985 7 7 6 14 FLORENCE 9.3 289.4 135 583 +1980 10 28 18 19 DEBBY 28.7 347.5 136 826 +1984 1 4 12 27 ALBERTO 30.4 114.0 164 240 +1973 1 1 0 22 GORDON 45.1 60.2 87 724 +1973 9 26 6 21 RAFAEL 20.7 190.3 12 104 +1956 7 13 12 14 WILLIAM 22.5 197.6 43 290 +1976 8 3 18 15 VALERIE 37.6 244.3 136 594 +1958 7 15 0 13 MICHAEL 66.5 315.6 102 776 +1982 6 9 12 26 NADINE 53.0 108.3 144 634 +1999 5 9 12 5 RAFAEL 29.0 212.0 31 269 +1999 1 22 18 25 NADINE 40.0 13.7 163 470 +1987 10 5 6 4 KIRK 63.4 284.5 18 225 +1977 11 25 18 6 FLORENCE 9.2 271.7 135 848 +1998 1 23 18 26 LESLIE 42.0 331.6 74 271 +1979 11 3 18 2 NADINE 9.0 61.0 128 555 +2002 7 21 18 5 FLORENCE 46.1 69.8 35 834 +1985 9 5 18 7 TONY 47.5 277.9 119 818 +1990 8 18 12 8 JOYCE 9.8 209.4 35 550 +1968 6 25 18 15 HELENE 25.0 254.0 58 100 +1963 7 26 6 16 ISAAC 24.2 332.0 134 103 +1953 4 19 0 2 NADINE 52.7 347.4 135 143 +1979 12 22 0 5 LESLIE 40.1 16.8 68 371 +1956 5 3 12 25 PATTY 40.7 136.9 161 733 +1981 11 5 12 26 FLORENCE 9.0 249.2 162 85 +1992 8 2 0 9 ERNESTO 33.5 52.1 40 566 +2003 3 26 12 23 ISAAC 8.3 112.6 44 755 +1997 7 23 12 21 KIRK 68.3 115.1 30 572 +1971 4 27 0 22 CHRIS 20.4 71.4 35 791 +1956 9 10 12 4 ISAAC 64.9 326.4 113 272 +1981 10 22 18 26 BERYL 27.3 163.2 78 822 +1995 2 14 12 1 SANDY 69.4 44.9 113 237 +1992 4 26 0 11 NADINE 34.8 310.5 20 121 +1968 2 9 0 20 ISAAC 58.5 324.5 126 892 +2001 4 20 18 11 CHRIS 62.6 128.8 17 830 +1998 1 18 0 19 ERNESTO 63.5 306.1 73 540 +2002 9 17 0 21 LESLIE 48.4 20.4 22 556 +2001 10 28 6 16 OSCAR 61.7 326.8 79 324 +1967 10 14 0 24 SANDY 61.6 152.4 127 104 +1995 1 10 12 21 ERNESTO 65.1 54.7 69 143 +1961 3 3 6 23 LESLIE 13.1 90.5 47 187 +1971 3 15 12 27 RAFAEL 62.8 41.5 156 43 +1955 11 10 12 17 VALERIE 27.6 45.6 101 572 +1950 3 23 12 6 PATTY 60.4 280.4 109 260 +1971 10 11 6 18 SANDY 54.9 112.0 93 245 +2000 8 1 18 4 ERNESTO 40.3 116.8 53 605 +1980 11 14 18 19 DEBBY 64.1 215.3 127 6 +1970 8 22 6 6 CHRIS 65.3 5.4 147 530 +1980 9 9 0 14 MICHAEL 17.0 279.4 71 409 +1964 6 14 0 12 PATTY 52.9 206.5 129 735 +1953 8 19 12 7 PATTY 49.0 84.4 140 757 +1986 6 9 6 18 HELENE 28.5 256.5 26 269 +1994 8 22 12 12 VALERIE 50.6 233.7 79 4 +1981 11 24 18 5 SANDY 69.2 34.9 59 433 +1978 3 26 0 3 VALERIE 48.3 238.5 152 837 +1955 6 9 12 22 BERYL 53.3 294.4 49 480 +1954 12 8 0 5 WILLIAM 19.3 209.1 79 132 +1994 5 7 18 28 PATTY 32.2 341.7 65 108 +1954 10 25 18 20 HELENE 30.9 285.0 51 519 +1982 9 26 18 11 ALBERTO 48.7 300.1 28 135 +1995 12 17 18 13 OSCAR 16.2 62.2 39 331 +1977 7 27 12 10 DEBBY 60.9 123.8 24 164 +1999 11 28 12 25 ISAAC 36.4 239.9 32 357 +1967 3 21 6 15 GORDON 43.4 31.7 33 506 +1988 2 19 12 9 LESLIE 28.1 67.9 103 411 +1961 2 8 0 4 VALERIE 45.5 147.2 148 113 +1984 2 8 6 1 LESLIE 23.0 272.5 69 524 +1968 9 23 12 27 WILLIAM 35.4 282.2 86 59 +1961 4 3 6 26 SANDY 15.7 218.8 58 628 +1962 6 21 6 8 OSCAR 35.4 155.1 138 297 +1986 10 20 18 14 HELENE 19.0 170.4 158 177 +1971 1 3 18 27 TONY 37.1 172.9 151 825 +1989 3 7 12 4 OSCAR 11.0 125.4 76 376 +1954 4 1 0 4 DEBBY 45.5 179.6 84 283 +1952 11 19 18 23 OSCAR 31.0 13.5 37 680 +1996 4 11 18 3 ISAAC 31.7 344.1 61 501 +1988 2 25 12 2 NADINE 24.0 285.1 25 591 +1959 2 13 12 13 SANDY 21.2 55.6 131 97 +1970 5 13 6 13 HELENE 34.0 248.5 27 833 +1965 5 17 18 4 VALERIE 48.5 31.1 38 335 +1988 6 12 6 27 FLORENCE 33.6 189.3 162 287 +1978 3 25 6 26 OSCAR 65.6 57.4 55 134 +1980 7 12 18 21 FLORENCE 44.8 237.5 47 69 +1997 11 4 6 25 BERYL 31.4 80.1 129 301 +1995 11 10 0 10 JOYCE 57.7 317.8 14 595 +1968 5 19 18 7 OSCAR 10.8 299.7 15 656 +1960 2 27 6 15 VALERIE 60.2 232.9 54 653 +1972 10 20 0 3 NADINE 18.2 19.3 69 31 +1986 2 3 18 14 DEBBY 9.3 14.8 54 206 +1998 4 5 12 28 JOYCE 24.2 5.0 116 630 +1990 2 13 6 20 SANDY 35.1 51.9 125 704 +1963 2 7 12 23 LESLIE 69.4 83.7 99 497 +1976 4 27 18 11 HELENE 55.5 175.1 164 360 +1974 6 16 18 25 CHRIS 44.6 56.9 66 472 +1951 1 6 6 25 WILLIAM 23.8 247.3 57 269 +1965 6 17 6 17 LESLIE 53.3 96.3 10 326 +1968 3 9 6 8 TONY 63.5 114.2 138 576 +1971 8 25 6 1 ERNESTO 55.2 177.1 149 117 +1951 7 10 12 28 PATTY 29.3 298.1 23 318 +1964 5 18 0 16 JOYCE 59.8 111.0 78 338 +1950 11 7 18 6 JOYCE 34.4 15.2 73 545 +1955 10 12 6 22 NADINE 41.1 88.7 89 741 +1975 4 16 6 6 WILLIAM 44.8 74.4 13 57 +1980 11 16 6 1 VALERIE 51.7 159.6 24 166 +1999 7 9 12 12 GORDON 49.9 321.0 84 647 +1969 11 15 0 28 CHRIS 33.7 275.8 130 489 +1994 12 13 12 17 CHRIS 16.8 290.7 118 385 +1955 6 16 18 21 PATTY 63.8 254.4 163 611 +2000 12 11 6 9 SANDY 49.4 13.4 163 206 +1951 6 11 0 28 OSCAR 64.0 241.2 153 285 +1996 6 7 12 18 MICHAEL 47.3 24.1 11 198 +1982 3 25 18 18 ERNESTO 69.4 64.1 49 93 +1977 10 18 6 27 DEBBY 48.9 144.9 84 26 +1981 5 4 6 25 KIRK 13.1 66.7 132 473 +1960 12 14 0 7 LESLIE 44.9 242.6 161 136 +1966 2 26 12 7 JOYCE 54.4 80.9 123 300 +1964 4 23 18 12 ISAAC 41.6 343.6 149 693 +1967 3 24 6 18 MICHAEL 55.3 30.3 75 386 +2001 11 16 18 15 TONY 30.4 127.9 30 29 +1978 9 19 6 22 SANDY 68.9 225.3 140 646 +1993 7 26 0 18 PATTY 43.6 301.2 135 135 +1987 11 24 12 13 ALBERTO 49.5 129.9 142 240 +1988 6 21 6 16 SANDY 56.6 354.2 65 261 +1962 8 9 6 18 TONY 54.2 299.8 154 693 +1950 7 24 12 28 LESLIE 10.7 77.7 18 875 +1969 2 16 0 23 BERYL 69.6 234.6 58 891 +1962 2 10 12 2 WILLIAM 58.8 11.3 37 674 +1989 1 15 18 16 NADINE 31.4 324.1 119 770 +1974 11 6 18 13 TONY 22.2 3.1 13 732 +1975 3 9 18 1 MICHAEL 58.5 356.6 99 550 +1995 7 19 18 8 PATTY 39.6 46.4 43 176 +1971 12 22 0 8 VALERIE 17.6 52.0 88 878 +1987 6 27 0 18 OSCAR 69.1 208.6 69 175 +1988 5 9 18 8 JOYCE 36.7 19.7 148 434 +1976 5 10 0 21 KIRK 64.1 115.9 40 346 +1956 2 3 18 27 NADINE 41.6 284.9 108 889 +1954 9 23 12 19 CHRIS 20.4 45.8 52 587 +1988 12 3 18 22 ISAAC 29.6 134.2 20 328 +1976 4 14 0 3 PATTY 67.7 178.8 140 368 +1966 12 17 6 5 LESLIE 27.2 32.8 147 677 +1954 1 3 12 25 FLORENCE 31.4 93.8 14 515 +2004 5 17 0 20 WILLIAM 20.1 176.8 155 270 +1970 8 18 18 6 RAFAEL 54.3 273.5 111 39 +1976 6 7 6 22 KIRK 38.3 160.3 152 764 +1955 2 10 6 3 RAFAEL 11.5 293.6 54 164 +1963 1 14 18 8 TONY 15.7 44.6 63 571 +1975 10 20 6 15 JOYCE 19.8 278.9 91 598 +1966 4 12 12 5 CHRIS 21.3 10.3 67 635 +1965 2 15 12 19 MICHAEL 37.1 339.2 118 59 +1971 3 1 0 6 JOYCE 48.5 353.0 29 218 +1965 1 15 6 13 RAFAEL 68.6 39.2 97 453 +1956 2 13 18 11 VALERIE 10.9 164.5 153 695 +2000 10 24 6 24 JOYCE 10.6 64.0 109 830 +1960 3 4 12 2 FLORENCE 58.9 58.9 158 487 +1983 11 26 12 10 VALERIE 47.9 93.4 64 564 +1951 5 5 6 11 SANDY 32.3 289.8 110 390 +1958 8 15 12 16 NADINE 31.2 58.0 31 409 +1999 4 9 0 26 TONY 40.9 337.6 130 427 +1982 1 5 0 12 RAFAEL 43.9 70.0 105 75 +1951 6 27 18 17 FLORENCE 28.6 15.4 32 120 +1992 8 1 12 13 ISAAC 33.6 133.6 43 141 +2004 10 27 12 19 FLORENCE 34.0 82.6 48 452 +1971 5 17 12 22 BERYL 7.8 25.7 150 543 +1974 7 15 0 13 MICHAEL 38.5 260.6 113 209 +1983 12 7 12 3 JOYCE 22.5 9.3 132 316 +2002 2 12 6 4 FLORENCE 11.5 356.8 144 87 +1968 9 7 12 9 ISAAC 62.4 6.8 56 385 +1972 9 11 0 20 GORDON 17.7 197.6 87 675 +1980 1 2 12 11 ISAAC 68.1 281.5 139 293 +1956 4 1 6 25 CHRIS 16.2 278.1 44 238 +1963 6 17 12 6 FLORENCE 62.1 15.7 56 106 +1996 4 25 0 15 LESLIE 20.0 147.7 97 807 +1985 1 1 12 13 SANDY 70.0 301.5 99 564 +1960 11 1 18 25 ISAAC 64.2 246.1 128 49 +1969 10 3 0 20 TONY 56.2 342.9 35 48 +1979 7 4 6 19 OSCAR 58.8 276.8 133 323 +1969 8 7 18 18 JOYCE 51.1 71.7 96 158 +1973 8 2 12 20 PATTY 21.4 48.4 107 831 +1996 12 22 6 26 WILLIAM 14.8 344.0 46 356 +1964 9 23 18 7 SANDY 23.9 100.2 150 440 +1953 2 22 6 24 RAFAEL 30.8 55.7 47 408 +1994 11 7 0 10 WILLIAM 8.6 233.1 83 633 +1971 11 27 6 10 ERNESTO 20.9 295.1 88 652 +1995 5 27 12 19 RAFAEL 19.4 141.1 164 780 +1951 1 26 12 20 OSCAR 52.9 33.8 67 490 +1987 3 21 18 21 TONY 18.9 141.4 12 449 +1964 12 22 6 9 DEBBY 38.7 27.1 111 69 +1995 5 2 12 23 TONY 51.3 170.2 36 344 +1959 12 8 18 18 CHRIS 47.9 58.7 158 344 +1965 12 16 0 15 WILLIAM 37.6 74.3 150 258 +2002 3 19 0 16 CHRIS 13.3 93.3 41 515 +1991 8 24 6 10 WILLIAM 20.1 193.9 14 801 +1965 3 2 0 22 MICHAEL 9.7 163.3 162 544 +2003 4 16 6 12 MICHAEL 8.5 203.2 39 467 +1984 11 24 18 27 ALBERTO 12.4 49.1 104 836 +1994 7 10 12 28 DEBBY 68.5 343.0 121 90 +1999 9 23 6 8 KIRK 47.2 202.9 148 301 +1985 11 24 18 4 ALBERTO 11.4 62.9 41 432 +1971 5 24 18 3 CHRIS 38.9 167.8 31 786 +1951 5 21 12 21 HELENE 9.9 348.3 28 335 +1974 1 28 6 6 MICHAEL 51.6 154.9 151 408 +1963 6 8 12 10 RAFAEL 46.4 217.8 100 540 +1996 10 26 18 25 GORDON 69.9 173.5 96 642 +1964 5 25 6 21 GORDON 43.0 288.3 105 803 +1970 8 28 18 1 ALBERTO 65.2 201.5 88 467 +1996 1 9 18 3 DEBBY 40.2 215.1 33 511 +1972 10 28 0 23 VALERIE 50.9 327.3 88 53 +1997 10 9 0 3 MICHAEL 46.0 86.6 50 201 +1962 10 24 12 16 KIRK 58.7 110.7 118 606 +1959 3 14 0 18 KIRK 34.5 256.4 113 310 +1974 7 3 12 20 RAFAEL 44.1 189.1 125 539 +1965 8 26 0 13 ERNESTO 20.7 121.5 156 558 +1953 3 5 18 12 JOYCE 28.1 107.2 23 304 +1997 9 12 12 7 WILLIAM 41.2 139.6 28 847 +1982 11 8 18 7 ALBERTO 42.2 110.3 88 489 +1955 11 17 12 8 TONY 9.2 251.0 89 703 +1955 1 23 6 3 SANDY 43.7 97.8 25 889 +1966 9 23 12 3 DEBBY 9.2 309.3 87 168 +1964 2 2 18 8 TONY 52.8 177.1 51 680 +1955 11 17 0 7 BERYL 40.4 79.4 106 182 +1960 1 2 18 17 CHRIS 14.0 127.0 93 323 +1951 12 21 18 12 TONY 10.3 315.9 26 487 +1980 8 7 6 7 ERNESTO 21.2 22.3 156 582 +1968 11 21 6 4 ERNESTO 53.3 65.9 43 95 +1986 7 1 0 14 SANDY 15.4 224.7 150 695 +1971 5 16 18 14 OSCAR 58.6 17.0 34 320 +1971 12 22 6 25 OSCAR 19.5 117.1 126 268 +1977 5 1 12 23 NADINE 14.0 5.1 149 343 +2000 8 14 6 18 MICHAEL 52.3 267.8 13 856 +1968 10 5 12 2 NADINE 21.0 321.3 20 587 +1978 4 3 6 9 PATTY 67.7 242.2 123 693 +1978 1 17 6 8 BERYL 28.5 109.8 137 627 +1960 9 27 12 4 BERYL 64.8 198.2 104 828 +1959 6 22 6 3 SANDY 59.8 17.5 19 390 +1996 7 21 0 16 TONY 15.3 57.8 73 388 +1976 10 28 12 2 PATTY 58.7 85.8 106 339 +1981 2 20 6 24 LESLIE 39.7 320.3 50 869 +1985 6 23 18 15 HELENE 52.2 86.7 128 607 +1963 10 19 0 5 VALERIE 59.5 241.1 67 398 +1985 5 9 12 25 ISAAC 58.8 61.9 160 390 +1993 9 15 0 24 ERNESTO 20.9 192.3 89 118 +1959 6 6 12 25 RAFAEL 35.8 78.7 17 146 +1979 6 28 18 20 ERNESTO 69.7 322.2 92 675 +1958 11 22 18 5 HELENE 9.5 350.8 71 49 +1985 4 22 18 21 ISAAC 32.5 176.5 112 451 +1999 2 6 0 2 ERNESTO 9.9 9.0 127 213 +1957 4 25 0 15 PATTY 46.0 259.8 119 178 +1950 4 19 6 24 ISAAC 19.0 68.7 91 33 +1964 9 17 12 5 CHRIS 33.9 82.6 161 258 +1955 6 22 18 8 ERNESTO 67.0 146.5 124 778 +1963 11 11 12 25 WILLIAM 10.1 340.2 37 827 +1972 3 24 12 3 VALERIE 28.0 22.5 99 735 +1958 2 8 0 26 TONY 12.1 165.4 123 27 +1972 7 14 6 11 PATTY 69.5 279.3 69 853 +1956 3 18 12 17 RAFAEL 18.1 333.2 140 306 +1991 12 11 18 8 VALERIE 46.1 34.6 44 436 +1994 8 20 18 15 FLORENCE 65.8 51.1 13 551 +1981 4 21 18 20 GORDON 19.1 47.5 69 753 +1962 3 16 12 15 FLORENCE 27.2 65.2 77 367 +1955 3 24 6 5 WILLIAM 65.0 236.1 14 571 +1958 12 15 0 4 JOYCE 22.4 147.1 35 293 +1986 8 17 18 22 ALBERTO 44.4 46.1 132 768 +2003 10 11 12 23 PATTY 26.0 313.9 150 739 +1989 12 11 6 25 ERNESTO 13.4 209.9 25 52 +1968 5 25 6 11 CHRIS 35.1 306.4 120 537 +2000 9 7 18 17 RAFAEL 42.9 22.5 136 556 +1951 6 11 0 25 PATTY 40.9 295.1 13 179 +1964 8 20 0 28 ALBERTO 50.3 143.8 39 427 +1973 2 26 0 27 BERYL 15.2 216.2 42 518 +1956 5 7 0 26 MICHAEL 49.3 229.6 163 574 +2002 2 14 0 10 PATTY 39.8 80.2 93 678 +1956 12 26 0 3 ALBERTO 26.3 333.7 78 203 +1985 6 3 18 5 WILLIAM 64.3 244.8 99 585 +1983 11 8 12 17 MICHAEL 38.8 193.8 75 487 +1981 5 21 6 5 WILLIAM 50.1 30.8 65 188 +1992 7 27 6 25 CHRIS 68.3 329.5 145 379 +1966 7 6 6 1 RAFAEL 16.3 251.4 138 4 +1995 2 14 18 28 LESLIE 32.2 307.4 25 664 +1991 5 15 12 23 LESLIE 43.1 69.7 56 290 +1978 12 15 12 8 ERNESTO 10.6 40.1 138 855 +1955 10 25 0 8 DEBBY 56.6 151.5 113 207 +1999 11 6 0 27 LESLIE 39.1 353.7 48 519 +1989 7 14 18 6 WILLIAM 54.9 245.0 26 743 +1982 12 10 6 15 ISAAC 20.3 268.2 24 70 +1969 8 16 12 8 CHRIS 52.3 352.7 164 46 +1976 4 9 12 23 LESLIE 49.0 205.5 53 741 +1983 9 7 18 4 HELENE 37.1 8.1 114 521 +1970 3 24 18 10 VALERIE 16.4 114.2 24 482 +1959 11 25 0 5 ERNESTO 8.4 28.7 120 603 +1999 1 10 12 6 RAFAEL 13.3 319.4 122 412 +1981 6 16 0 4 HELENE 37.7 136.1 150 742 +1987 12 11 6 16 TONY 30.2 139.2 34 458 +1991 3 11 12 14 LESLIE 41.2 163.2 147 230 +1986 8 3 6 18 TONY 57.5 110.9 129 762 +1978 6 22 0 23 SANDY 38.6 311.7 114 375 +1969 4 25 12 14 JOYCE 41.2 125.1 29 255 +1993 3 19 6 21 OSCAR 17.4 257.4 28 798 +1977 11 20 6 25 CHRIS 23.8 194.1 47 136 +1966 7 21 0 10 JOYCE 41.5 163.0 54 80 +1973 9 28 18 1 JOYCE 56.4 344.0 164 33 +1989 3 14 18 12 LESLIE 37.5 343.1 26 55 +2002 7 24 12 13 SANDY 64.5 245.0 87 468 +1970 10 26 18 3 JOYCE 16.9 57.5 78 313 +1952 5 12 12 17 PATTY 54.6 45.5 105 709 +1965 8 18 0 19 HELENE 39.7 293.4 128 187 +1969 4 15 12 1 ALBERTO 12.8 312.0 154 192 +2000 9 11 12 21 RAFAEL 17.3 124.1 124 760 +1955 5 20 12 19 HELENE 31.1 81.0 63 629 +1958 12 7 18 3 ERNESTO 62.9 83.1 131 545 +1976 9 10 6 17 TONY 57.0 112.9 50 320 +1968 1 3 0 4 WILLIAM 12.8 137.0 51 424 +1984 9 8 18 18 JOYCE 38.4 144.5 131 832 +1997 9 6 6 26 DEBBY 37.8 15.8 48 751 +1994 10 6 6 26 VALERIE 51.3 169.8 84 685 +1996 7 15 12 5 PATTY 9.0 144.3 40 601 +1954 4 22 18 12 VALERIE 35.7 309.2 28 328 +1986 2 8 12 16 ERNESTO 23.4 342.4 123 160 +2000 11 21 12 11 JOYCE 37.0 285.6 62 712 +1950 4 19 6 19 CHRIS 37.9 357.8 10 258 +1992 7 28 18 16 JOYCE 22.1 95.1 61 475 +1961 7 22 18 20 ISAAC 46.0 63.7 68 496 +1970 10 6 6 3 WILLIAM 18.8 30.8 110 281 +1973 5 18 12 13 SANDY 7.8 25.0 115 173 +1988 1 11 18 26 DEBBY 65.3 252.3 131 773 +1958 1 19 12 8 LESLIE 51.1 187.8 47 419 +1982 12 6 12 23 ERNESTO 27.1 52.4 83 203 +1973 3 19 12 23 SANDY 59.1 250.9 131 263 +1987 8 12 18 8 GORDON 16.6 202.4 79 407 +1959 11 16 18 1 HELENE 43.4 20.5 19 694 +1989 9 13 0 23 JOYCE 42.0 283.3 93 542 +1953 9 27 0 5 ALBERTO 26.0 183.6 27 515 +1972 4 7 0 13 NADINE 65.7 244.6 50 310 +1978 6 26 6 8 ALBERTO 13.4 187.6 152 487 +1955 7 6 12 13 MICHAEL 48.7 1.5 62 214 +1989 7 20 0 25 ALBERTO 67.4 335.9 125 45 +1953 3 5 12 17 HELENE 38.6 215.3 55 449 +1998 11 10 12 23 VALERIE 35.9 75.4 126 795 +1986 1 22 6 12 FLORENCE 16.4 20.7 12 599 +1978 10 23 12 13 OSCAR 66.1 320.5 101 104 +1952 3 15 0 26 ALBERTO 23.3 231.0 97 447 +1971 1 6 12 11 FLORENCE 45.4 234.2 19 374 +2001 5 20 12 1 TONY 56.6 324.4 81 745 +1969 5 15 0 21 PATTY 8.1 136.4 56 826 +1952 1 2 18 13 ERNESTO 19.0 120.4 163 370 +1990 2 8 12 27 RAFAEL 17.6 278.8 60 404 +1959 11 1 18 15 PATTY 54.2 287.9 77 563 +1995 5 8 0 22 CHRIS 61.8 165.7 56 429 +1983 7 9 18 26 BERYL 25.7 313.8 66 411 +1982 2 19 12 26 WILLIAM 26.7 291.5 92 827 +1956 11 4 6 22 TONY 22.5 116.7 139 65 +1979 4 10 0 1 ISAAC 12.6 120.0 80 579 +1950 12 3 0 13 JOYCE 44.7 94.5 48 593 +1954 6 2 0 17 BERYL 52.2 218.6 58 580 +1997 3 20 0 25 NADINE 62.2 71.1 46 81 +1997 8 28 18 15 ISAAC 64.4 69.4 74 808 +1958 8 16 6 26 ALBERTO 19.6 70.7 81 129 +2004 12 17 18 22 DEBBY 23.3 278.8 46 174 +1956 12 5 6 25 TONY 64.4 259.9 146 286 +1975 1 26 12 26 MICHAEL 48.3 252.0 74 842 +1962 5 19 0 12 ISAAC 37.8 160.7 34 460 +1953 8 10 6 4 NADINE 65.8 77.0 19 110 +1981 12 11 18 4 ISAAC 60.9 44.9 71 285 +1979 7 19 0 10 WILLIAM 37.9 55.7 70 306 +1971 7 12 18 28 WILLIAM 35.2 96.7 41 681 +1968 8 25 0 11 MICHAEL 20.5 145.0 73 308 +1954 5 26 0 15 ISAAC 52.3 319.6 130 618 +1999 7 9 18 15 ISAAC 38.9 343.3 15 91 +2001 12 27 0 21 KIRK 68.7 14.4 79 156 +1978 5 25 6 24 ERNESTO 67.3 352.1 70 713 +1952 5 11 18 2 GORDON 19.0 173.7 117 839 +1997 1 5 6 15 NADINE 16.6 196.5 112 57 +1995 3 22 6 19 OSCAR 65.8 100.7 62 315 +1975 12 23 12 18 ERNESTO 52.8 250.1 89 512 +1956 8 25 6 6 ALBERTO 16.1 100.3 150 159 +1977 12 21 18 20 WILLIAM 69.8 20.2 109 605 +1986 11 26 6 13 ISAAC 28.1 45.2 126 688 +1962 7 21 0 26 ERNESTO 28.7 142.5 142 611 +1952 9 7 0 6 JOYCE 27.8 1.2 128 793 +1954 11 1 6 8 MICHAEL 8.6 108.9 143 652 +1983 12 7 0 8 NADINE 48.2 276.4 153 765 +1967 5 6 12 7 WILLIAM 48.6 164.4 140 379 +1994 4 28 18 6 BERYL 61.6 182.6 121 369 +2001 5 13 6 18 TONY 68.7 217.7 134 54 +2000 4 3 6 28 HELENE 28.1 49.6 33 736 +1964 11 25 6 4 JOYCE 31.0 131.8 90 386 +1959 10 1 12 5 CHRIS 48.7 276.8 65 543 +1951 5 24 12 9 VALERIE 29.1 334.4 74 436 +1983 5 14 0 12 DEBBY 50.8 42.5 41 729 +1976 6 20 0 9 ERNESTO 33.7 15.2 110 507 +1961 12 16 12 15 MICHAEL 38.1 192.7 28 151 +1999 10 11 18 13 FLORENCE 50.5 258.4 147 461 +1957 9 13 0 8 ERNESTO 19.5 65.8 111 195 +1993 9 10 18 12 OSCAR 8.7 82.5 49 252 +1960 6 2 0 9 ISAAC 19.0 287.2 107 632 +1968 7 22 6 26 ISAAC 52.5 311.0 112 411 +1961 2 10 0 7 ALBERTO 20.0 247.2 13 611 +1997 11 14 6 21 PATTY 62.7 135.7 31 766 +1959 10 3 12 15 CHRIS 64.0 328.0 71 652 +1995 1 3 6 19 WILLIAM 64.0 232.4 61 366 +1965 9 2 6 8 JOYCE 61.8 199.4 28 813 +1959 1 5 6 12 JOYCE 60.6 250.1 163 419 +1994 11 14 6 5 ERNESTO 47.2 82.3 24 91 +1995 6 25 6 4 TONY 20.1 99.0 39 755 +1986 9 13 0 20 ERNESTO 56.9 357.7 112 565 +1971 3 10 0 4 DEBBY 58.0 279.4 44 216 +1958 11 18 0 14 HELENE 57.8 154.1 138 623 +1988 1 27 18 1 DEBBY 22.5 160.3 68 147 +1957 1 13 12 6 TONY 25.9 322.0 139 263 +1950 5 5 0 9 MICHAEL 42.2 331.8 68 549 +1994 12 22 18 14 GORDON 31.4 236.7 147 851 +1992 12 13 18 16 ALBERTO 14.4 345.9 147 574 +1951 4 18 0 13 HELENE 61.2 238.4 90 191 +1975 1 7 12 16 CHRIS 52.7 141.0 24 106 +1999 12 22 18 2 CHRIS 22.1 44.6 18 484 +1983 12 21 0 18 LESLIE 32.1 38.0 137 514 +1977 5 16 18 18 WILLIAM 7.0 76.7 11 48 +1973 1 10 0 4 SANDY 50.8 135.6 81 551 +1961 10 17 12 28 LESLIE 59.1 90.8 67 698 +1972 6 18 6 9 CHRIS 21.9 33.9 136 308 +1962 10 6 12 14 ERNESTO 45.5 214.3 125 623 +1968 7 9 12 6 MICHAEL 53.0 163.9 119 10 +1969 7 15 18 1 HELENE 28.9 64.3 127 349 +1990 4 7 12 18 GORDON 56.8 213.1 148 600 +1984 5 21 18 3 GORDON 60.3 65.4 41 599 +1970 7 21 18 19 VALERIE 43.8 272.7 163 363 +1994 10 6 12 4 OSCAR 54.2 170.5 76 692 +1977 3 9 0 7 ERNESTO 53.5 31.5 147 147 +1963 5 25 0 20 HELENE 63.7 332.5 108 647 +1996 7 25 6 18 SANDY 19.6 8.2 21 144 +1986 10 18 18 22 NADINE 67.5 70.2 77 605 +1959 7 20 6 3 VALERIE 33.1 81.9 72 711 +1993 4 22 18 14 GORDON 54.0 84.4 58 857 +1966 5 13 6 8 WILLIAM 68.0 93.6 53 92 +1952 11 6 6 28 BERYL 19.5 248.4 146 180 +1994 4 20 6 14 OSCAR 10.1 247.2 133 812 +1999 12 18 0 21 ERNESTO 29.6 327.5 129 180 +1964 7 13 12 12 LESLIE 40.1 79.8 141 776 +1969 8 25 0 11 VALERIE 20.9 146.4 122 868 +1967 10 21 12 11 CHRIS 46.5 116.6 153 691 +1959 12 4 12 17 PATTY 21.9 324.6 38 714 +1953 12 8 6 14 SANDY 32.1 17.9 101 599 +1962 3 22 0 10 HELENE 34.1 45.6 46 453 +1997 2 25 0 14 HELENE 54.0 143.5 100 288 +1996 6 22 0 25 WILLIAM 45.5 345.2 71 484 +1955 10 13 0 9 LESLIE 34.2 22.5 86 37 +1981 4 20 0 6 LESLIE 30.1 2.7 149 736 +1986 12 21 12 21 WILLIAM 16.7 292.8 138 63 +1978 5 28 0 19 CHRIS 57.6 141.6 77 604 +1957 2 8 18 12 LESLIE 62.1 103.0 78 166 +1976 3 10 18 17 NADINE 11.3 106.7 109 635 +1984 7 24 6 24 RAFAEL 53.1 114.0 88 179 +1971 9 26 6 4 ISAAC 27.2 271.6 15 635 +1986 3 5 6 13 VALERIE 21.8 13.5 125 858 +1953 1 17 18 22 KIRK 60.1 231.5 72 21 +1962 6 22 6 3 TONY 29.4 248.1 150 720 +1956 8 4 6 15 DEBBY 38.0 341.4 99 136 +1988 3 9 18 27 CHRIS 60.2 136.4 16 806 +1964 10 21 18 3 JOYCE 60.7 263.5 113 502 +1998 5 8 0 17 PATTY 31.0 241.6 160 92 +1987 9 5 18 15 DEBBY 51.8 28.1 10 652 +1995 8 13 6 11 GORDON 64.4 130.7 60 148 +2000 8 3 12 12 CHRIS 68.1 207.8 41 317 +1981 7 23 12 21 ISAAC 56.0 9.6 72 43 +1986 2 19 18 4 WILLIAM 25.7 16.8 73 224 +2002 2 3 18 9 CHRIS 67.3 60.7 115 810 +1964 9 21 12 15 ERNESTO 49.2 242.8 146 827 +1985 10 13 12 8 OSCAR 51.3 132.1 65 40 +1958 12 5 18 27 ERNESTO 32.3 197.2 100 528 +1966 3 2 0 11 OSCAR 51.2 159.6 125 174 +1998 4 7 18 21 FLORENCE 36.6 9.0 64 102 +1987 6 6 12 19 GORDON 44.3 349.5 148 137 +2004 11 14 12 14 CHRIS 32.0 76.5 27 774 +1960 11 7 0 23 MICHAEL 68.3 101.2 136 781 +1989 9 13 0 21 DEBBY 66.3 248.7 106 714 +1975 10 11 18 24 GORDON 39.2 135.1 35 421 +2002 2 1 6 22 CHRIS 25.1 306.2 95 590 +1980 5 5 6 24 ISAAC 46.0 344.8 111 793 +1987 7 1 12 15 OSCAR 42.3 127.9 147 854 +1983 8 25 0 19 OSCAR 22.3 355.4 164 838 +1997 5 28 6 14 JOYCE 7.4 74.8 114 116 +1982 6 1 0 6 NADINE 31.7 312.8 113 54 +1998 10 2 18 17 ALBERTO 16.3 195.0 136 19 +1952 9 24 18 28 ISAAC 41.9 265.8 65 196 +1980 9 17 6 3 LESLIE 35.1 113.1 128 369 +1992 1 1 6 15 VALERIE 60.2 347.8 79 141 +1973 11 20 0 23 ISAAC 15.7 124.6 107 793 +1995 4 17 6 21 ALBERTO 44.3 33.1 146 637 +1981 5 25 12 1 CHRIS 29.7 120.9 64 568 +1991 4 11 18 9 JOYCE 47.8 137.4 97 197 +1979 2 17 6 25 RAFAEL 11.7 8.7 149 849 +1963 2 4 0 21 RAFAEL 57.5 253.4 62 65 +1957 8 3 12 16 LESLIE 7.5 88.5 12 138 +1983 11 27 18 10 NADINE 53.0 340.8 85 278 +1995 1 24 12 24 RAFAEL 42.9 342.7 105 5 +2004 2 4 6 25 CHRIS 54.1 37.4 76 686 +1990 12 14 6 24 ERNESTO 45.2 36.5 87 797 +2004 6 23 18 20 NADINE 17.1 94.2 97 810 +2001 3 11 0 21 TONY 69.9 109.0 77 651 +1971 12 16 18 6 KIRK 35.1 103.2 81 314 +1974 7 14 6 19 HELENE 34.8 265.2 37 795 +1955 8 2 18 15 MICHAEL 33.6 178.5 14 585 +1951 12 17 12 10 CHRIS 26.5 185.6 19 341 +1973 6 23 6 19 NADINE 65.9 254.7 12 733 +1958 3 13 18 21 ISAAC 37.4 246.7 119 811 +1952 8 17 6 14 GORDON 49.9 280.5 121 605 +1970 3 23 18 13 TONY 27.8 54.2 127 313 +1984 7 10 12 12 WILLIAM 48.2 271.8 93 32 +1975 10 21 6 8 ALBERTO 55.7 238.8 149 312 +1983 1 24 18 26 GORDON 58.2 211.2 109 346 +1988 1 8 18 27 PATTY 50.7 99.0 144 742 +1988 2 15 12 6 JOYCE 36.4 162.3 120 451 +1972 4 21 12 5 HELENE 13.6 259.4 68 153 +1987 5 11 6 17 ERNESTO 56.6 196.7 28 503 +1983 9 16 12 26 PATTY 66.1 41.8 49 545 +1951 11 15 0 7 DEBBY 44.1 32.1 126 638 +1969 3 10 18 5 LESLIE 10.3 189.0 78 624 +1954 2 13 12 27 OSCAR 35.5 297.3 83 711 +1974 1 25 6 17 OSCAR 43.1 114.5 57 400 +1996 12 14 18 10 NADINE 8.9 232.6 119 528 +1981 12 28 0 1 JOYCE 68.9 291.8 96 335 +1984 10 18 6 20 OSCAR 54.3 97.0 161 221 +1987 8 28 12 8 HELENE 13.9 245.0 124 786 +1962 7 7 0 26 GORDON 43.4 357.0 58 260 +1950 7 8 12 23 OSCAR 7.6 61.1 66 673 +1997 5 20 18 23 VALERIE 46.9 168.6 11 553 +1992 8 1 18 8 ISAAC 22.2 29.6 140 593 +1975 1 21 18 12 MICHAEL 20.9 89.6 52 219 +1991 1 28 6 20 ERNESTO 49.6 131.1 157 101 +1985 2 3 0 25 RAFAEL 14.7 64.6 164 501 +1953 5 7 18 17 BERYL 11.4 276.6 99 893 +1999 3 28 12 22 PATTY 21.2 306.3 120 330 +1954 12 4 12 22 RAFAEL 10.8 0.5 92 320 +1978 11 19 6 17 BERYL 61.7 51.7 47 92 +2003 2 19 6 20 LESLIE 24.5 58.7 95 453 +1968 10 13 18 20 OSCAR 15.9 311.4 45 225 +1971 4 15 12 11 LESLIE 9.4 276.7 149 797 +1983 11 17 6 22 ERNESTO 53.0 185.7 14 62 +1965 9 14 0 19 ALBERTO 69.1 99.6 126 895 +1982 6 26 12 19 FLORENCE 59.0 112.1 62 496 +1983 9 21 18 20 LESLIE 69.0 112.6 44 334 +1982 12 24 18 27 ERNESTO 7.6 121.0 38 854 +2003 4 3 12 7 PATTY 35.8 196.8 124 143 +1973 1 17 18 13 LESLIE 21.2 321.9 69 7 +2003 4 19 0 19 PATTY 25.9 306.2 157 212 +1986 7 24 6 9 FLORENCE 46.3 284.4 35 626 +1968 2 5 18 11 DEBBY 53.6 209.6 100 542 +1974 6 21 6 19 ISAAC 21.0 138.6 53 614 +1967 5 19 12 17 OSCAR 27.6 158.8 157 168 +1980 10 12 0 11 SANDY 9.9 132.1 79 720 +1973 10 8 0 4 BERYL 60.7 223.5 136 832 +1991 10 24 0 22 TONY 44.5 291.9 18 809 +2000 10 20 18 13 BERYL 67.9 70.8 135 827 +1952 7 3 12 4 DEBBY 38.4 33.3 135 573 +1994 10 12 12 10 OSCAR 36.1 52.2 15 108 +1964 10 15 12 10 VALERIE 64.9 295.6 121 782 +1969 2 4 12 3 VALERIE 48.3 120.4 152 167 +1993 8 10 6 7 CHRIS 47.9 172.6 96 349 +1990 9 26 0 13 TONY 46.5 274.0 51 771 +1972 5 13 6 7 MICHAEL 59.0 176.0 85 237 +1978 6 10 18 10 HELENE 65.6 334.4 97 72 +1961 2 12 6 25 BERYL 12.6 356.9 85 715 +1978 1 27 0 18 GORDON 68.8 62.1 78 245 +1995 1 28 6 11 RAFAEL 63.3 271.1 47 111 +1995 2 23 12 15 ALBERTO 36.5 204.5 101 651 +1964 1 25 18 11 TONY 48.5 56.2 148 814 +1965 8 14 12 1 NADINE 13.8 257.6 123 545 +1961 3 5 6 19 TONY 32.0 101.7 128 817 +1997 11 5 6 27 RAFAEL 34.1 188.8 120 397 +1985 1 12 12 9 LESLIE 46.9 313.5 88 821 +1996 1 16 6 14 OSCAR 29.5 326.1 19 692 +1976 3 18 0 8 WILLIAM 46.7 119.7 14 545 +1976 4 5 0 19 ERNESTO 62.7 69.0 145 534 +1979 8 4 18 18 ALBERTO 25.7 36.2 68 71 +1951 4 22 12 13 BERYL 23.6 72.3 145 778 +1995 5 19 12 14 MICHAEL 15.3 302.7 157 95 +1972 10 6 6 27 ERNESTO 35.5 324.1 95 51 +1950 7 10 12 7 RAFAEL 33.0 256.8 88 525 +1956 2 5 18 26 ALBERTO 52.6 92.6 15 652 +1984 9 21 6 27 GORDON 51.2 34.1 164 138 +1971 8 15 6 11 ALBERTO 22.1 255.8 143 298 +1997 3 9 12 19 ALBERTO 30.7 95.5 110 667 +1979 12 20 6 17 RAFAEL 16.4 102.9 73 216 +1955 2 20 12 16 RAFAEL 66.9 238.6 18 82 +1997 2 20 12 13 FLORENCE 39.7 19.1 134 665 +1985 10 28 6 4 WILLIAM 51.6 100.1 15 222 +1969 3 22 18 7 BERYL 49.4 124.6 31 744 +1962 3 14 0 16 TONY 12.2 45.6 120 728 +1994 9 9 6 17 JOYCE 26.9 192.1 100 690 +2002 2 3 0 19 OSCAR 14.6 176.3 162 889 +1972 9 12 18 18 ISAAC 24.8 86.3 116 878 +1991 1 19 6 9 KIRK 52.4 292.2 120 496 +1964 7 11 18 13 HELENE 10.7 111.1 28 383 +1971 5 28 18 20 GORDON 27.4 54.2 86 548 +1987 6 2 12 7 JOYCE 25.2 195.0 117 412 +1990 7 20 0 22 CHRIS 32.7 37.4 159 696 +1974 8 18 12 7 FLORENCE 28.9 155.8 18 430 +1958 1 18 6 3 ISAAC 17.1 282.1 45 372 +1985 12 23 12 26 OSCAR 66.9 191.4 127 301 +1959 1 21 12 12 GORDON 23.2 318.5 66 96 +1972 9 2 0 14 OSCAR 69.1 285.2 162 102 +1990 9 19 6 5 BERYL 60.9 91.6 135 123 +1967 2 21 0 11 PATTY 13.1 223.5 105 220 +1992 9 8 0 3 ALBERTO 9.8 109.5 163 322 +1993 10 18 18 26 GORDON 22.0 241.5 123 333 +1960 4 2 0 17 BERYL 22.7 325.0 32 308 +1971 7 22 12 15 HELENE 8.3 75.1 63 506 +1951 9 13 12 28 KIRK 41.5 292.1 117 390 +1957 1 15 0 21 VALERIE 65.1 309.8 38 550 +1989 5 5 12 15 ALBERTO 56.1 47.3 113 862 +1996 9 3 6 22 ALBERTO 47.2 46.1 147 219 +2002 10 9 18 20 TONY 60.5 97.4 12 691 +1993 3 5 18 27 JOYCE 50.5 16.2 102 834 +1960 4 23 18 18 BERYL 37.4 137.8 163 704 +1998 2 5 0 23 BERYL 23.1 316.8 53 550 +1969 7 5 6 14 HELENE 39.1 155.7 50 57 +1993 1 11 12 16 DEBBY 28.1 269.9 73 529 +1955 12 21 0 12 VALERIE 10.0 138.6 109 521 +1966 4 1 12 14 LESLIE 32.8 214.9 34 838 +1985 3 22 12 21 KIRK 62.2 101.2 101 402 +1952 11 15 6 14 DEBBY 42.8 144.0 30 143 +1955 7 6 18 5 HELENE 38.0 253.9 30 895 +1972 3 16 12 15 FLORENCE 16.9 231.3 18 703 +1999 9 28 18 20 FLORENCE 8.7 129.1 67 781 +1968 2 1 18 8 DEBBY 7.8 162.3 149 506 +1990 7 15 12 22 ALBERTO 23.8 123.9 127 710 +2002 9 19 0 21 PATTY 23.3 334.1 104 114 +1993 3 17 0 13 RAFAEL 8.9 121.3 23 780 +1958 12 12 18 21 LESLIE 45.9 253.7 109 177 +1972 1 23 18 6 LESLIE 36.9 80.8 115 204 +2004 6 26 12 23 SANDY 14.5 286.0 151 843 +1952 11 3 0 14 MICHAEL 44.9 331.7 95 122 +1992 10 17 12 24 KIRK 33.1 132.0 25 845 +1997 12 8 12 18 OSCAR 20.2 192.1 105 815 +1961 8 25 6 4 KIRK 47.9 98.0 112 529 +1992 11 4 6 15 HELENE 64.1 99.9 60 893 +1981 11 6 18 6 FLORENCE 15.5 215.7 38 664 +1950 8 22 12 12 DEBBY 47.0 11.2 77 462 +1962 1 17 12 22 SANDY 52.8 112.6 88 396 +1958 4 3 6 3 PATTY 19.4 87.8 97 816 +1984 8 15 18 3 HELENE 69.0 265.2 45 346 +1953 12 2 0 13 NADINE 30.9 208.4 79 60 +2001 7 2 6 2 VALERIE 13.7 193.0 17 198 +1988 7 24 6 16 BERYL 65.0 171.1 161 33 +1975 11 10 6 10 ALBERTO 61.7 157.3 96 216 +1986 4 10 18 12 DEBBY 61.4 94.1 129 475 +1970 8 6 0 25 RAFAEL 22.8 111.9 88 842 +1988 10 24 0 8 RAFAEL 14.1 97.0 79 92 +1983 9 8 0 17 KIRK 33.9 176.8 41 114 +1957 7 22 6 6 HELENE 36.1 302.8 40 134 +1993 7 18 6 9 DEBBY 21.4 57.4 113 880 +1976 12 16 12 5 LESLIE 46.6 27.8 81 62 +1981 5 17 12 16 PATTY 35.1 23.6 40 579 +1970 7 16 0 16 ALBERTO 11.5 181.6 141 327 +2001 6 11 0 16 SANDY 47.5 335.3 162 842 +1993 5 26 0 14 WILLIAM 53.6 123.9 113 512 +1950 3 23 6 6 HELENE 33.2 308.0 37 395 +1983 5 10 6 16 DEBBY 45.8 354.1 94 696 +1974 12 23 0 19 WILLIAM 49.3 228.3 100 259 +1994 11 5 6 6 ERNESTO 21.4 303.1 147 696 +1975 4 28 12 21 LESLIE 37.1 113.0 159 264 +1977 8 1 12 10 OSCAR 69.7 59.6 82 690 +1975 2 7 0 24 KIRK 48.6 110.4 162 434 +1957 9 6 0 17 PATTY 52.1 215.9 10 252 +1983 6 24 0 12 BERYL 55.7 331.6 103 892 +1951 7 28 6 11 ERNESTO 32.7 50.7 81 473 +1954 6 19 18 3 BERYL 8.1 47.8 110 554 +1993 6 14 0 7 LESLIE 49.4 248.4 153 48 +2001 4 5 0 4 SANDY 15.4 69.9 40 601 +1961 8 24 0 12 RAFAEL 7.1 95.1 28 82 +1973 4 1 6 16 VALERIE 17.6 66.3 142 10 +2000 2 7 12 21 OSCAR 8.7 249.3 109 300 +2003 9 15 0 24 MICHAEL 48.0 129.9 112 344 +1978 9 12 0 7 VALERIE 7.1 111.3 14 40 +1997 11 14 18 18 TONY 51.2 323.6 52 186 +1958 6 22 0 13 RAFAEL 39.4 337.0 17 731 +1995 10 9 6 10 WILLIAM 51.0 163.9 14 123 +1994 2 22 0 24 KIRK 35.4 272.6 40 734 +1981 7 5 6 18 GORDON 20.2 173.7 66 581 +1976 9 1 6 24 FLORENCE 59.1 68.8 17 867 +1987 1 22 0 9 HELENE 42.3 143.4 139 6 +1996 7 10 0 12 ERNESTO 65.5 303.5 59 132 +1976 12 9 6 22 GORDON 44.0 301.3 13 645 +1977 2 11 18 24 ALBERTO 54.9 228.4 67 297 +1959 1 1 0 7 CHRIS 48.0 123.9 89 260 +1984 1 24 18 15 LESLIE 51.3 209.3 77 474 +1957 5 22 6 15 GORDON 61.2 197.4 97 139 +1975 2 19 6 7 RAFAEL 54.8 73.1 20 815 +1969 9 28 6 20 VALERIE 59.8 155.9 92 784 +1974 4 6 18 15 HELENE 27.0 70.8 162 654 +1953 8 7 0 1 OSCAR 22.6 288.7 127 66 +1977 8 17 6 13 NADINE 46.2 273.6 27 421 +1957 2 15 12 19 KIRK 35.7 251.8 100 523 +1985 1 27 0 19 VALERIE 52.5 119.6 17 458 +1990 2 17 12 9 BERYL 58.7 235.1 59 481 +1982 7 15 6 22 TONY 52.3 70.1 44 793 +2000 6 20 12 24 DEBBY 59.5 279.4 85 473 +1985 2 5 18 28 HELENE 63.8 237.1 115 412 +2002 4 28 18 19 ERNESTO 68.0 329.6 105 523 +1969 7 22 0 20 ERNESTO 57.6 91.9 79 274 +2002 3 8 12 2 ISAAC 17.9 323.4 66 584 +1957 3 16 0 3 WILLIAM 52.0 302.8 39 527 +1971 9 7 12 15 WILLIAM 35.2 125.4 30 40 +1999 10 11 0 8 LESLIE 68.3 122.0 127 891 +1976 12 22 6 24 BERYL 21.7 5.8 115 617 +1953 11 19 12 23 ALBERTO 33.7 264.5 139 50 +1990 6 27 6 21 SANDY 20.5 170.0 110 300 +1978 4 28 0 27 LESLIE 65.2 154.3 145 368 +1981 11 18 12 8 ALBERTO 65.7 355.3 84 832 +1975 6 18 6 24 DEBBY 54.7 281.3 13 353 +1954 2 11 18 9 KIRK 43.5 215.4 33 424 +1989 8 24 18 3 SANDY 36.3 145.6 149 788 +1981 7 2 18 12 MICHAEL 21.3 315.2 141 571 +1960 3 21 12 24 HELENE 38.4 222.6 123 216 +1952 2 4 12 2 RAFAEL 67.3 341.5 120 600 +1952 7 17 0 10 KIRK 26.3 173.2 121 589 +1996 12 1 6 22 SANDY 10.8 151.5 63 124 +1991 3 23 0 7 ISAAC 51.8 19.0 90 479 +1975 11 2 6 11 ISAAC 14.4 298.7 113 447 +1993 12 14 18 28 CHRIS 9.1 29.0 99 817 +1983 5 1 0 1 RAFAEL 19.6 54.0 135 516 +1981 12 1 6 14 ERNESTO 33.4 99.5 86 420 +1958 12 12 6 2 MICHAEL 13.7 82.0 39 343 +1982 7 20 6 24 BERYL 54.8 231.8 32 400 +1997 8 26 0 21 ISAAC 36.1 153.8 89 670 +1960 11 11 12 3 CHRIS 49.9 70.8 10 475 +1967 12 14 6 1 ALBERTO 69.0 249.4 133 207 +1975 6 26 12 3 RAFAEL 13.8 61.2 140 749 +1965 11 15 0 4 BERYL 34.0 273.7 21 415 +1975 10 8 18 9 HELENE 38.3 121.1 96 371 +1994 9 22 12 27 HELENE 17.4 47.6 17 394 +2000 6 21 0 22 TONY 9.2 72.4 23 132 +1960 3 23 6 26 GORDON 44.4 313.6 127 300 +1969 8 15 6 21 GORDON 10.2 126.4 83 608 +1995 3 6 18 7 OSCAR 64.5 228.9 43 358 +1960 12 4 0 5 RAFAEL 17.9 353.6 132 590 +1965 5 25 12 5 PATTY 16.3 305.1 55 79 +1989 3 9 12 20 ISAAC 40.4 92.8 100 166 +1981 4 18 18 23 SANDY 31.3 2.4 112 511 +1993 12 3 6 24 LESLIE 34.5 99.8 141 678 +1982 5 26 6 9 VALERIE 67.1 147.0 36 158 +1991 8 17 12 17 KIRK 32.2 351.6 77 308 +1972 6 15 18 15 VALERIE 14.6 78.4 117 586 +1986 12 9 12 13 MICHAEL 37.8 295.4 15 161 +1967 8 7 18 15 VALERIE 64.7 71.2 42 315 +1990 9 5 12 4 VALERIE 51.5 184.7 124 647 +1957 10 20 0 15 LESLIE 58.4 330.3 80 582 +1966 9 18 0 15 KIRK 20.0 258.8 89 244 +1951 11 15 12 24 LESLIE 55.4 247.3 40 291 +1965 2 13 6 18 NADINE 14.0 19.9 65 444 +1958 6 23 6 10 JOYCE 30.9 229.9 100 289 +1961 4 21 0 20 WILLIAM 55.5 301.2 163 214 +1993 10 28 18 15 VALERIE 67.7 318.9 16 99 +1962 7 4 12 15 SANDY 51.5 145.3 80 449 +1973 7 18 0 11 BERYL 32.4 324.4 116 286 +1986 7 22 6 16 KIRK 18.9 125.6 65 297 +1960 7 24 18 7 RAFAEL 54.4 51.9 164 441 +1959 8 22 0 14 KIRK 20.4 130.0 100 66 +1961 2 7 0 2 DEBBY 59.9 86.3 126 774 +1993 6 4 6 24 SANDY 32.8 313.0 120 309 +2003 3 10 18 15 NADINE 47.6 192.8 36 853 +1985 2 9 6 3 FLORENCE 37.1 345.6 33 598 +1973 5 18 6 21 WILLIAM 58.6 120.9 101 162 +1959 5 26 18 9 HELENE 49.9 344.3 128 108 +1988 10 10 6 16 HELENE 13.9 222.7 33 390 +1967 10 24 12 26 CHRIS 21.5 121.4 157 547 +2004 1 25 0 22 PATTY 20.4 179.1 148 118 +1995 2 8 12 15 HELENE 25.6 276.0 64 667 +1973 12 24 6 26 ERNESTO 62.1 33.5 80 861 +1954 4 22 6 10 LESLIE 42.7 49.3 156 461 +1952 1 15 12 21 WILLIAM 15.7 120.0 83 89 +2003 10 17 0 18 DEBBY 62.6 45.1 124 572 +1965 2 2 0 20 GORDON 65.7 9.4 149 181 +1982 1 9 6 6 MICHAEL 63.5 318.3 122 555 +1965 8 20 6 10 MICHAEL 63.0 134.7 143 477 +1950 12 14 0 27 ERNESTO 17.4 63.2 47 296 +1953 11 7 6 10 FLORENCE 30.6 229.4 30 524 +1967 12 27 18 18 HELENE 17.5 348.8 41 313 +2004 7 25 18 21 ERNESTO 18.7 316.5 115 352 +1963 5 21 12 21 JOYCE 61.3 150.4 102 822 +1975 2 23 18 27 PATTY 26.5 3.9 158 553 +1980 11 9 12 2 GORDON 15.6 30.5 80 373 +1962 2 27 0 19 ALBERTO 25.9 321.0 128 766 +1984 11 22 6 19 PATTY 47.1 294.9 48 891 +1997 12 20 12 10 GORDON 34.5 57.3 164 466 +1951 1 26 6 2 GORDON 33.8 45.2 42 139 +1955 9 26 18 23 TONY 50.7 10.3 46 706 +1989 3 4 0 17 KIRK 62.3 52.0 150 207 +1979 11 6 18 20 TONY 41.9 76.3 114 70 +1953 7 24 6 14 JOYCE 33.7 28.3 96 97 +1965 12 27 12 19 ISAAC 18.2 29.4 27 562 +2000 2 23 12 1 SANDY 16.9 30.7 12 345 +1995 6 19 12 28 ERNESTO 7.8 247.7 71 346 +1996 12 27 6 10 ISAAC 41.6 39.2 79 480 +1952 7 6 18 26 FLORENCE 44.0 114.6 151 783 +1990 1 20 12 6 ERNESTO 10.5 241.6 84 45 +1997 6 25 0 27 DEBBY 56.4 270.7 92 265 +1984 1 1 0 4 HELENE 37.5 227.5 104 235 +1960 12 24 12 15 JOYCE 52.8 215.8 138 416 +1964 7 10 12 20 NADINE 53.5 336.0 126 341 +1979 12 4 18 18 MICHAEL 66.9 66.3 53 252 +1978 3 3 18 3 HELENE 18.0 171.6 24 187 +2003 7 27 6 7 DEBBY 53.0 189.5 33 102 +1960 9 20 12 18 WILLIAM 44.6 96.4 87 635 +1998 6 4 6 18 CHRIS 34.6 162.5 35 154 +1989 12 22 6 18 VALERIE 35.8 138.2 135 526 +1973 2 22 6 10 JOYCE 33.9 333.0 75 805 +1999 1 22 12 19 JOYCE 47.7 132.1 162 527 +1972 5 5 12 20 ERNESTO 19.6 220.1 82 153 +1968 11 17 0 15 KIRK 11.2 58.1 159 515 +1991 3 15 18 25 ALBERTO 39.3 287.0 161 210 +1990 12 16 6 25 KIRK 38.9 183.5 111 162 +1956 3 3 0 18 WILLIAM 45.0 285.5 109 695 +1978 9 14 18 28 ISAAC 36.8 44.6 141 512 +1980 10 18 6 25 MICHAEL 37.8 65.6 53 420 +1989 5 28 12 7 SANDY 32.3 129.2 22 728 +1964 11 10 18 8 PATTY 18.0 104.1 56 360 +1987 9 26 6 7 ISAAC 63.2 200.5 45 536 +1958 5 7 18 27 ERNESTO 23.5 322.1 13 237 +1972 5 18 0 9 ALBERTO 39.1 351.4 129 233 +1994 11 3 12 16 ISAAC 51.5 344.8 76 499 +1992 9 9 12 18 JOYCE 46.1 65.0 145 621 +1984 11 21 18 16 KIRK 34.3 308.0 15 133 +1997 12 27 0 5 GORDON 22.9 17.6 154 580 +1960 8 3 6 21 NADINE 9.0 239.9 153 169 +1965 1 9 6 28 KIRK 59.8 30.4 150 493 +1955 11 11 6 6 OSCAR 32.8 12.9 125 488 +1952 11 1 6 2 ERNESTO 20.9 144.6 104 440 +1964 12 8 18 16 JOYCE 14.0 22.8 140 297 +1977 6 12 0 22 ALBERTO 40.5 349.6 112 551 +1994 9 4 12 3 BERYL 43.1 208.2 85 164 +1950 6 11 18 4 CHRIS 65.6 337.3 163 736 +1955 6 2 0 15 NADINE 35.4 165.0 146 761 +1998 1 3 0 22 WILLIAM 63.3 258.7 108 303 +2002 12 16 18 4 MICHAEL 54.2 270.6 101 618 +1957 3 3 0 14 JOYCE 46.8 130.7 89 453 +2002 7 6 18 10 DEBBY 33.0 160.1 48 371 +1983 4 11 0 21 OSCAR 68.0 121.2 48 709 +1954 11 3 12 11 HELENE 59.7 125.9 141 760 +1986 12 18 12 5 GORDON 32.3 5.0 101 577 +1991 5 3 0 15 SANDY 41.8 353.2 54 72 +1998 7 18 18 5 MICHAEL 65.0 297.8 129 57 +1972 2 11 6 10 JOYCE 27.9 222.3 52 410 +1998 7 3 6 11 ERNESTO 44.7 111.6 48 367 +1975 9 18 6 17 CHRIS 57.4 167.2 37 660 +1971 10 14 12 2 LESLIE 36.0 97.3 77 279 +1955 4 22 18 26 ISAAC 31.9 46.8 67 346 +1985 11 12 6 25 SANDY 54.8 269.9 38 792 +2001 9 14 18 20 ALBERTO 25.0 62.6 19 860 +1951 2 23 6 23 MICHAEL 7.1 282.5 71 648 +1962 3 18 0 13 HELENE 23.3 335.3 38 544 +1967 12 16 0 12 WILLIAM 36.7 207.7 95 765 +1981 11 14 18 6 JOYCE 36.6 126.2 119 856 +1961 12 3 18 6 BERYL 68.7 103.2 15 666 +1973 3 13 12 13 OSCAR 23.6 315.0 10 159 +1984 8 15 12 25 HELENE 34.8 259.0 61 520 +1969 9 8 0 3 JOYCE 44.8 166.7 45 120 +1982 12 17 0 9 PATTY 17.3 267.6 104 331 +1985 9 18 12 18 SANDY 30.8 98.1 46 612 +1997 6 14 18 5 OSCAR 49.6 97.2 106 829 +1991 12 4 18 22 ISAAC 28.7 343.0 141 434 +1997 9 5 18 2 RAFAEL 58.0 296.1 133 604 +1980 12 27 18 24 SANDY 48.0 45.0 159 689 +1964 9 22 0 28 FLORENCE 34.4 292.3 53 520 +1952 11 25 12 27 ERNESTO 43.7 231.0 14 638 +1959 12 22 12 24 FLORENCE 51.3 29.4 51 822 +1982 7 11 12 10 RAFAEL 67.2 209.8 98 105 +1954 12 7 6 12 FLORENCE 20.0 271.1 104 836 +1952 1 12 12 6 LESLIE 9.9 56.2 120 773 +1963 1 9 12 24 HELENE 11.9 20.7 101 116 +1997 3 2 0 4 LESLIE 67.1 111.2 85 346 +1999 6 24 12 17 GORDON 53.6 334.5 105 785 +1989 3 11 12 17 WILLIAM 7.7 134.7 25 523 +1968 9 10 18 1 MICHAEL 7.9 56.1 22 668 +1988 5 28 0 22 SANDY 51.5 203.1 44 323 +1980 5 28 6 9 JOYCE 19.1 212.0 125 743 +1960 11 26 0 3 GORDON 14.1 100.3 75 83 +1952 6 15 0 6 SANDY 55.3 330.1 50 116 +1991 12 2 6 1 DEBBY 36.6 312.7 41 58 +1953 1 28 18 9 VALERIE 22.4 247.9 37 582 +1989 6 17 6 25 WILLIAM 33.3 126.5 138 674 +1956 2 24 0 24 HELENE 16.7 324.9 152 448 +1955 10 18 12 15 JOYCE 12.9 334.8 104 136 +1980 6 12 6 21 HELENE 15.2 208.7 25 495 +1995 5 12 12 7 DEBBY 25.9 286.9 115 186 +1999 7 3 12 4 KIRK 20.5 282.7 71 332 +1951 9 9 0 24 ERNESTO 40.9 239.5 146 511 +1977 7 16 12 23 ALBERTO 39.8 251.8 43 470 +1952 1 22 6 23 ALBERTO 13.3 355.9 57 200 +1970 4 10 0 19 VALERIE 64.5 22.4 148 854 +1986 12 15 18 22 JOYCE 30.6 226.3 32 186 +1975 9 18 6 7 ALBERTO 59.2 129.7 35 317 +1995 10 23 0 17 TONY 45.3 113.1 156 361 +1992 3 20 0 2 CHRIS 7.9 205.8 31 33 +1960 4 7 18 22 GORDON 60.1 199.5 93 798 +2003 4 27 12 8 LESLIE 10.9 280.8 93 721 +1995 4 23 6 8 OSCAR 34.0 329.8 90 353 +1960 7 15 18 18 ERNESTO 10.0 233.8 34 115 +1956 11 11 12 6 RAFAEL 46.0 41.7 103 124 +1990 8 24 12 22 WILLIAM 59.4 302.8 43 13 +1967 3 10 6 23 KIRK 56.5 85.9 81 238 +1960 11 22 18 26 SANDY 17.3 59.9 37 470 +1979 7 18 0 21 WILLIAM 49.7 323.5 34 503 +1961 5 20 18 28 SANDY 11.8 276.7 78 37 +1953 4 6 18 7 DEBBY 22.9 14.0 20 633 +1993 9 24 12 24 TONY 66.4 29.6 123 786 +1958 7 23 6 11 HELENE 43.3 239.2 153 587 +1962 9 2 0 3 HELENE 18.4 271.9 41 32 +1966 11 2 18 15 ISAAC 16.7 282.4 90 26 +1957 9 26 18 16 KIRK 8.3 16.7 21 846 +1968 10 7 6 11 TONY 31.3 16.2 17 660 +1978 5 1 18 9 VALERIE 15.0 106.8 103 129 +1978 4 21 18 15 BERYL 35.3 71.0 28 334 +1952 1 14 6 11 VALERIE 68.1 116.7 123 180 +1999 8 7 12 23 OSCAR 35.1 187.0 88 568 +1972 6 8 12 26 MICHAEL 45.2 169.8 77 77 +1974 7 24 12 17 HELENE 33.0 248.1 36 734 +1961 3 24 6 26 KIRK 38.5 286.2 14 633 +2000 4 6 12 3 DEBBY 9.6 251.2 134 633 +1963 6 11 0 11 HELENE 41.4 320.0 85 144 +1981 2 17 6 11 ERNESTO 16.2 2.8 136 212 +1964 1 21 18 20 PATTY 41.6 275.1 116 579 +1958 4 25 12 5 CHRIS 9.8 118.6 156 306 +1981 9 21 12 5 CHRIS 41.1 340.3 66 467 +1985 8 24 18 19 BERYL 61.9 57.2 158 479 +1951 7 21 18 21 RAFAEL 33.2 244.0 39 659 +1986 2 7 6 13 VALERIE 44.6 208.7 83 391 +1955 6 2 18 9 KIRK 42.3 1.6 120 675 +1973 8 24 6 13 GORDON 61.7 48.5 66 212 +1980 1 16 0 26 LESLIE 60.8 199.2 111 467 +2003 9 6 0 16 SANDY 41.2 284.5 145 222 +2002 8 13 6 15 OSCAR 69.0 294.4 41 293 +1988 7 8 12 7 LESLIE 13.0 42.5 18 467 +1992 5 18 0 16 GORDON 21.0 142.7 126 160 +1958 5 27 18 26 WILLIAM 30.1 161.8 53 865 +2003 10 6 0 1 FLORENCE 53.7 196.8 12 601 +2000 1 2 12 12 FLORENCE 34.2 353.9 114 249 +1962 8 27 6 8 GORDON 17.1 140.6 130 826 +2000 11 1 0 12 HELENE 47.3 339.1 47 642 +1998 1 22 12 23 VALERIE 16.0 104.6 152 769 +1963 2 13 6 10 WILLIAM 22.0 293.7 43 272 +1995 7 16 6 26 BERYL 7.8 257.3 144 719 +1973 9 21 12 2 BERYL 49.1 21.4 140 760 +1983 5 17 18 17 PATTY 48.2 293.5 118 352 +1991 5 20 12 22 HELENE 38.0 115.1 153 543 +1960 11 20 12 18 NADINE 58.8 44.6 98 841 +1991 4 13 18 15 ALBERTO 41.8 153.5 118 654 +1984 7 13 6 1 FLORENCE 40.9 158.4 40 243 +1974 6 28 0 13 ERNESTO 23.9 233.7 94 195 +1998 1 27 12 20 MICHAEL 47.3 102.4 41 342 +1975 2 10 12 17 SANDY 38.0 354.1 87 57 +1994 6 23 0 27 FLORENCE 8.0 240.9 34 225 +1989 12 5 18 21 MICHAEL 22.7 4.1 164 826 +1972 6 3 18 7 FLORENCE 64.5 139.7 67 41 +1983 1 6 18 15 FLORENCE 39.2 70.3 77 190 +1999 10 11 0 17 ISAAC 13.8 210.9 113 108 +2001 6 6 18 12 ISAAC 33.9 279.8 52 829 +2001 8 26 12 5 DEBBY 45.5 2.9 124 150 +1991 10 9 18 15 MICHAEL 27.5 357.4 61 415 +1957 6 12 12 15 TONY 58.4 179.3 41 694 +1952 11 17 0 6 ISAAC 35.1 202.7 10 398 +1957 1 12 0 10 SANDY 67.0 245.5 110 3 +1954 4 11 12 17 FLORENCE 59.8 16.7 77 435 +1962 11 25 18 2 VALERIE 44.7 221.7 62 558 +1992 11 11 12 1 NADINE 13.9 342.2 31 109 +2002 8 5 12 4 CHRIS 59.9 59.7 164 38 +1974 9 17 18 2 NADINE 29.6 355.8 21 293 +1955 2 15 12 26 NADINE 69.9 258.4 45 884 +1957 9 12 0 3 LESLIE 27.2 355.7 102 138 +1988 10 21 18 18 KIRK 11.8 262.9 12 459 +1960 5 26 6 4 OSCAR 21.9 231.6 99 223 +1980 5 20 18 20 BERYL 11.8 279.8 86 262 +1999 9 10 0 4 VALERIE 56.0 64.4 142 757 +1994 7 12 12 7 OSCAR 20.2 160.2 52 767 +1979 9 9 6 23 CHRIS 68.2 113.4 148 756 +1963 10 9 12 27 OSCAR 60.1 189.2 113 109 +1960 4 6 0 21 NADINE 14.2 351.1 142 245 +1963 7 7 6 25 JOYCE 41.6 214.1 155 494 +1967 7 14 18 14 FLORENCE 31.7 25.8 30 823 +1962 5 9 6 13 BERYL 29.1 325.4 16 361 +1979 9 10 18 8 BERYL 7.7 196.2 84 248 +1950 4 22 6 6 FLORENCE 45.8 272.1 65 79 +1954 11 5 12 12 NADINE 34.7 65.5 151 6 +1950 8 14 18 7 CHRIS 10.7 283.9 136 168 +1979 4 8 6 14 ERNESTO 25.4 78.1 160 265 +1972 8 8 6 17 BERYL 25.8 203.7 30 263 +1970 9 21 18 13 HELENE 21.2 202.2 46 15 +1961 1 6 0 25 MICHAEL 39.2 127.5 65 711 +1998 12 13 18 21 ERNESTO 30.3 127.9 129 513 +1955 11 1 6 26 CHRIS 12.0 96.7 141 568 +1993 7 8 6 24 OSCAR 20.3 14.9 118 622 +1952 1 19 18 24 RAFAEL 52.6 36.9 135 289 +1959 12 10 12 2 PATTY 35.0 252.4 33 231 +1974 2 5 18 28 VALERIE 39.1 63.5 27 741 +1991 11 24 12 28 MICHAEL 48.2 41.1 73 30 +1991 12 26 18 2 CHRIS 43.4 240.0 127 646 +1954 4 5 6 13 NADINE 13.3 179.8 69 854 +1973 4 25 6 5 JOYCE 59.7 335.6 49 380 +1986 9 23 12 8 OSCAR 15.0 225.4 120 207 +2002 8 22 6 9 KIRK 36.6 332.3 139 801 +1952 9 5 12 26 RAFAEL 37.7 201.1 29 470 +1998 1 18 18 2 KIRK 48.4 274.0 72 489 +1958 12 18 0 20 SANDY 23.3 271.9 137 20 +1997 12 18 0 9 CHRIS 12.3 220.5 56 181 +1999 2 17 18 25 KIRK 28.2 33.6 13 294 +1980 7 22 0 25 GORDON 23.1 69.9 160 369 +1999 5 22 6 10 OSCAR 32.0 117.2 73 125 +2003 1 2 12 3 ERNESTO 27.8 290.7 59 592 +1953 5 26 6 22 GORDON 32.3 189.1 159 632 +1970 8 24 12 22 MICHAEL 24.2 110.9 101 481 +1966 3 9 18 13 SANDY 38.1 138.4 111 797 +1984 12 1 6 24 ISAAC 51.8 108.2 125 81 +1972 10 18 12 11 JOYCE 16.3 116.6 41 638 +2001 4 6 18 20 KIRK 22.1 8.0 38 80 +2000 1 20 12 14 CHRIS 23.9 122.4 109 356 +1954 7 22 18 26 ISAAC 67.4 252.7 152 367 +2004 2 21 6 4 HELENE 27.6 88.3 120 41 +1984 9 27 0 10 ERNESTO 32.3 141.7 87 105 +1989 3 27 12 22 HELENE 48.8 34.9 73 95 +1981 9 9 6 18 HELENE 33.2 154.4 50 566 +1963 8 21 12 25 ERNESTO 13.2 272.2 16 1 +1960 10 16 18 24 ALBERTO 58.7 78.5 149 396 +2002 12 4 0 9 ISAAC 63.9 280.3 111 475 +1995 5 14 6 18 NADINE 65.6 319.4 45 606 +1977 7 23 12 22 ERNESTO 30.5 343.3 98 87 +1951 12 19 18 6 NADINE 26.9 117.7 146 444 +1974 6 10 6 28 KIRK 13.9 105.3 12 453 +1983 7 23 0 17 LESLIE 20.7 254.4 145 351 +1970 6 26 6 14 ISAAC 66.7 134.9 10 437 +1988 8 4 18 18 OSCAR 38.6 112.4 73 182 +1973 8 16 18 18 WILLIAM 32.8 6.6 103 693 +1982 8 8 18 11 SANDY 50.1 106.6 42 283 +1996 7 18 12 5 PATTY 32.8 74.0 104 357 +1961 1 5 12 14 GORDON 55.9 108.0 147 618 +1989 10 1 18 1 LESLIE 56.1 286.3 128 748 +1958 11 23 0 7 NADINE 28.7 220.3 145 705 +1953 6 8 18 24 NADINE 19.7 173.1 98 6 +1989 8 7 0 4 TONY 9.3 100.2 71 100 +1957 1 25 0 27 JOYCE 36.3 291.9 37 75 +1962 11 13 18 26 VALERIE 19.1 227.8 91 106 +1976 12 27 6 7 HELENE 38.1 343.0 155 812 +1985 12 26 0 9 WILLIAM 28.5 206.9 15 713 +1965 3 19 18 22 CHRIS 16.6 295.5 79 94 +1957 4 9 18 19 SANDY 12.5 33.4 114 18 +1975 8 9 12 15 MICHAEL 19.5 93.9 12 832 +1986 1 13 6 1 BERYL 58.1 239.2 52 871 +1969 9 11 18 6 WILLIAM 36.1 344.4 85 867 +1990 9 10 6 26 ERNESTO 44.3 327.6 55 83 +1984 5 18 18 5 ERNESTO 64.2 162.9 108 275 +1974 10 19 12 23 SANDY 47.2 99.1 33 21 +1969 3 21 12 20 ERNESTO 24.0 202.7 16 354 +2002 1 28 18 13 FLORENCE 25.0 163.0 159 360 +1975 3 21 0 26 DEBBY 21.4 274.5 58 276 +1986 4 23 6 11 CHRIS 29.4 127.7 89 536 +1961 9 27 0 2 ALBERTO 13.0 203.0 149 363 +1999 11 24 18 13 GORDON 25.6 175.2 75 307 +1955 4 2 0 10 ALBERTO 36.0 215.9 88 828 +1983 9 10 0 25 KIRK 11.9 175.2 10 521 +1985 6 5 6 15 ALBERTO 58.8 269.5 147 409 +1978 3 10 0 6 SANDY 43.3 139.6 98 333 +1970 7 13 12 2 VALERIE 17.5 331.4 117 185 +1959 5 1 0 19 PATTY 14.9 71.9 24 334 +1964 12 26 0 5 FLORENCE 20.6 292.9 35 800 +1968 3 27 0 11 ERNESTO 33.6 255.1 148 235 +1964 1 27 6 11 OSCAR 26.6 150.5 34 793 +1961 3 7 12 25 FLORENCE 45.0 335.1 64 14 +1958 3 18 18 1 GORDON 54.6 46.6 59 2 +1955 1 24 18 17 KIRK 56.1 104.5 10 435 +1998 2 9 18 2 TONY 36.1 339.3 127 891 +2004 7 4 12 28 CHRIS 43.5 294.0 114 132 +1964 7 1 6 14 ERNESTO 31.0 62.9 41 253 +1986 9 10 6 19 OSCAR 38.9 352.1 153 653 +1983 11 5 6 14 OSCAR 54.9 56.2 129 313 +1992 7 11 6 28 ERNESTO 59.6 326.4 134 548 +1977 3 14 6 23 FLORENCE 51.7 26.8 47 187 +1990 6 25 6 20 KIRK 7.0 178.8 34 847 +1958 4 1 0 8 ISAAC 25.0 121.2 132 421 +1998 8 13 18 15 OSCAR 52.4 330.1 15 195 +1981 12 16 6 17 KIRK 48.1 170.4 17 419 +1980 1 14 12 27 HELENE 36.9 274.3 113 726 +1999 11 2 18 14 FLORENCE 58.3 349.8 27 238 +1982 2 26 18 27 JOYCE 15.4 89.4 162 659 +1983 7 16 6 22 BERYL 21.5 163.9 56 475 +1997 12 6 6 14 SANDY 14.8 182.3 162 640 +1968 2 10 6 22 BERYL 30.7 119.5 29 575 +1998 12 12 6 26 HELENE 52.8 4.8 124 192 +1975 1 1 6 25 WILLIAM 37.2 133.8 74 622 +1989 4 1 0 5 VALERIE 10.4 323.7 130 780 +1999 9 14 0 27 VALERIE 28.0 9.5 146 271 +2000 1 13 12 28 GORDON 36.7 42.7 63 86 +1991 2 11 6 28 HELENE 46.4 107.8 88 509 +1955 3 27 0 20 HELENE 46.8 21.2 134 296 +1951 5 11 6 14 BERYL 28.3 13.9 156 857 +1974 2 27 18 5 ERNESTO 69.9 225.7 84 478 +1979 9 24 0 25 PATTY 34.4 248.0 82 579 +1980 6 3 6 28 TONY 29.7 273.0 96 416 +1958 4 14 0 27 WILLIAM 34.5 234.7 106 515 +1985 2 7 6 9 TONY 54.8 164.2 83 507 +1954 8 20 12 4 WILLIAM 26.7 279.6 21 139 +1977 12 21 18 25 RAFAEL 40.2 237.6 164 55 +1980 3 28 6 11 JOYCE 26.6 203.4 81 647 +1955 1 28 18 20 RAFAEL 10.0 237.3 53 883 +1987 3 8 18 28 ALBERTO 56.2 63.1 29 213 +1993 10 22 12 13 VALERIE 56.2 291.5 20 282 +1965 4 7 0 19 LESLIE 20.0 298.2 12 163 +1982 6 11 18 9 CHRIS 31.8 266.2 137 60 +1999 12 3 6 1 ALBERTO 68.2 147.2 21 73 +1982 9 25 0 8 OSCAR 48.4 20.1 42 888 +1956 5 4 6 7 HELENE 56.3 136.1 11 36 +1999 7 22 12 17 FLORENCE 41.3 342.5 140 738 +1990 6 22 0 16 OSCAR 51.7 274.3 75 835 +1986 3 24 6 27 TONY 62.9 89.7 126 176 +1967 9 22 12 2 HELENE 23.0 33.1 130 342 +1975 2 11 18 26 FLORENCE 14.7 120.8 120 360 +1986 9 7 12 7 BERYL 16.9 275.0 126 564 +1956 2 6 6 8 RAFAEL 50.4 308.7 133 71 +1971 3 2 0 13 JOYCE 13.6 312.9 73 126 +1953 9 13 6 28 WILLIAM 28.3 96.5 68 753 +1982 4 7 18 6 RAFAEL 45.0 65.4 158 693 +1962 1 25 6 4 OSCAR 30.8 331.0 68 717 +1959 1 28 18 16 NADINE 45.1 213.6 58 670 +1956 6 23 18 10 FLORENCE 40.5 63.5 52 568 +1971 3 26 6 23 DEBBY 62.3 10.2 41 660 +1951 7 21 0 18 OSCAR 46.1 284.1 13 638 +1950 7 5 0 24 GORDON 21.3 187.8 131 180 +1988 6 8 12 24 JOYCE 37.6 54.3 91 157 +1992 11 5 12 4 VALERIE 68.6 89.0 118 6 +1957 11 1 0 13 PATTY 11.5 237.1 42 444 +1995 12 19 12 22 CHRIS 59.4 343.7 61 818 +1956 2 21 6 22 FLORENCE 54.8 333.6 88 619 +1991 10 18 0 14 HELENE 52.9 241.0 47 230 +1987 10 26 0 6 GORDON 45.6 199.3 10 28 +1964 4 5 18 24 DEBBY 55.2 66.6 11 839 +1955 9 27 18 28 RAFAEL 9.2 155.0 68 142 +1953 3 2 6 1 PATTY 56.3 83.6 45 416 +1969 4 12 6 12 BERYL 42.8 219.6 54 714 +1979 4 6 18 4 TONY 49.0 157.2 105 631 +1989 9 13 6 8 MICHAEL 67.2 133.8 116 286 +1964 5 13 18 8 TONY 8.7 109.8 35 784 +1988 2 18 18 5 NADINE 58.7 158.6 124 823 +1975 1 15 6 11 BERYL 36.0 80.8 131 873 +1956 12 19 0 19 KIRK 41.0 168.4 110 708 +1995 9 18 12 3 SANDY 19.0 298.0 21 894 +1954 7 14 0 28 ERNESTO 52.9 236.5 17 677 +2000 3 4 18 5 DEBBY 44.1 105.0 122 579 +1959 3 17 6 15 DEBBY 54.1 37.1 15 256 +1983 4 15 12 16 ALBERTO 16.6 265.8 109 45 +1999 10 24 6 23 ALBERTO 20.0 268.1 45 21 +1962 5 6 6 18 VALERIE 12.8 111.1 30 801 +2004 12 24 6 11 LESLIE 12.9 216.9 160 664 +1969 9 28 0 26 CHRIS 25.6 354.5 33 657 +1965 9 12 18 1 BERYL 31.3 288.6 154 457 +1961 12 4 12 6 GORDON 43.7 321.7 150 516 +1960 10 2 6 5 CHRIS 22.7 304.5 54 232 +1987 6 1 18 1 NADINE 43.4 341.2 90 550 +1987 11 27 6 8 JOYCE 21.2 79.5 34 28 +2001 9 27 12 22 TONY 24.2 85.0 163 440 +1992 6 6 6 25 GORDON 41.1 45.9 114 262 +1985 11 16 18 13 FLORENCE 31.3 310.3 66 230 +1991 8 1 0 7 OSCAR 33.4 204.5 50 894 +1996 1 6 12 11 ERNESTO 11.4 152.7 86 736 +1968 6 8 6 11 FLORENCE 22.9 348.5 124 496 +1961 9 4 12 16 MICHAEL 66.0 161.0 115 449 +1983 11 20 0 3 MICHAEL 59.6 309.2 108 512 +1982 7 8 6 18 ISAAC 12.7 245.2 68 710 +1982 5 5 18 19 WILLIAM 48.2 205.9 92 381 +1996 7 17 6 27 KIRK 33.3 20.4 75 699 +1955 1 22 6 6 RAFAEL 52.7 326.0 13 30 +1962 1 1 6 20 ALBERTO 63.5 17.8 68 471 +1955 6 9 0 14 RAFAEL 40.2 135.5 14 376 +1984 1 19 6 13 BERYL 49.6 77.2 51 698 +1982 6 22 0 9 VALERIE 49.0 354.3 129 427 +1951 10 24 0 11 FLORENCE 32.8 200.9 51 73 +1965 9 20 0 18 JOYCE 62.0 355.1 12 255 +1964 12 2 0 23 FLORENCE 65.7 175.1 22 655 +1988 6 19 18 25 SANDY 68.6 17.2 48 368 +1951 6 17 6 2 KIRK 34.2 271.7 124 113 +1998 1 21 12 24 NADINE 44.4 127.1 22 365 +1957 11 28 6 26 NADINE 49.2 54.1 54 99 +1963 9 16 0 11 NADINE 56.8 77.6 77 346 +1994 5 5 18 24 WILLIAM 20.2 278.0 109 461 +1976 4 17 18 9 LESLIE 15.3 140.7 27 203 +1988 3 28 18 1 KIRK 49.1 235.6 37 629 +1986 11 11 12 11 SANDY 13.5 200.5 118 821 +1959 2 7 0 27 ERNESTO 19.9 56.0 155 678 +1996 1 5 6 6 GORDON 63.5 70.9 63 167 +1987 7 19 12 23 NADINE 37.0 224.8 89 552 +1968 9 4 0 3 ISAAC 7.0 186.7 90 439 +1978 2 9 6 18 KIRK 21.7 95.1 142 887 +2000 9 2 12 22 FLORENCE 24.0 357.1 50 585 +1984 10 20 12 9 CHRIS 48.4 221.1 99 613 +1960 12 13 12 7 TONY 14.8 349.8 163 510 +1979 8 18 0 2 GORDON 64.4 26.9 102 366 +1990 1 21 18 19 RAFAEL 49.1 350.3 34 593 +1969 11 12 12 1 WILLIAM 68.6 17.3 159 140 +1982 8 18 0 25 ERNESTO 19.8 220.1 128 502 +1971 7 2 0 23 GORDON 38.3 271.8 128 552 +1994 3 6 0 17 CHRIS 19.9 290.5 63 310 +2004 3 6 6 22 GORDON 27.4 216.7 28 681 +1969 6 13 12 27 TONY 24.4 286.8 32 516 +1962 8 15 0 9 ALBERTO 31.6 55.7 37 404 +2002 7 4 12 8 TONY 32.9 174.4 89 6 +1986 7 10 12 10 NADINE 62.3 239.1 17 747 +1962 8 17 6 20 HELENE 15.1 111.6 133 388 +1988 2 3 0 26 RAFAEL 41.7 44.2 114 406 +1998 8 27 12 16 WILLIAM 23.1 329.9 128 84 +1956 10 12 6 11 MICHAEL 61.9 248.5 136 507 +1994 7 11 18 6 ISAAC 64.6 338.6 77 133 +1967 6 12 18 15 GORDON 39.1 329.8 14 269 +1950 6 21 12 6 GORDON 42.1 300.7 11 443 +1987 8 25 0 7 WILLIAM 25.9 263.2 94 131 +1965 3 3 6 26 ALBERTO 11.9 280.4 112 63 +1955 9 8 6 8 GORDON 33.0 95.5 14 271 +1978 12 8 12 24 VALERIE 57.8 87.3 159 566 +1971 7 21 0 23 SANDY 46.8 64.1 42 447 +1976 1 22 6 10 ALBERTO 48.5 337.9 145 681 +2000 8 4 18 28 ALBERTO 41.0 253.1 80 307 +1987 1 17 6 16 FLORENCE 69.4 145.7 36 741 +1957 1 9 12 1 HELENE 17.1 289.2 68 332 +2000 9 26 6 23 VALERIE 19.2 59.6 95 194 +1982 11 2 0 13 TONY 14.6 266.0 17 138 +1982 7 10 18 13 FLORENCE 42.7 170.8 23 6 +1999 11 15 18 8 DEBBY 17.6 294.8 148 811 +1963 2 5 0 15 ERNESTO 57.7 133.4 110 473 +2002 9 18 18 6 PATTY 24.6 84.4 164 97 +1994 10 26 12 24 MICHAEL 27.8 322.9 115 492 +1986 6 26 6 2 VALERIE 30.9 235.6 72 430 +2004 1 17 6 13 WILLIAM 8.9 210.3 68 729 +1976 9 1 0 7 DEBBY 55.8 334.5 131 189 +1963 7 6 0 23 MICHAEL 44.2 229.8 92 561 +1987 11 27 6 4 SANDY 38.9 111.2 100 479 +1990 11 15 12 5 LESLIE 56.2 124.6 127 715 +1986 3 26 12 21 TONY 53.7 29.1 77 82 +1993 8 16 0 10 KIRK 67.5 95.3 79 883 +1987 5 12 0 14 OSCAR 15.4 6.1 68 529 +1995 6 25 0 12 BERYL 20.9 182.4 30 417 +1951 4 13 0 26 ERNESTO 9.3 142.5 150 95 +1992 10 7 12 14 VALERIE 37.2 277.5 125 885 +1995 9 28 0 6 CHRIS 31.9 203.0 58 334 +1972 4 8 12 15 TONY 67.0 261.0 107 791 +1952 10 11 6 21 CHRIS 45.0 263.6 73 302 +1993 4 14 12 15 WILLIAM 37.2 252.3 161 863 +1960 2 12 18 6 FLORENCE 21.6 170.1 99 242 +1964 2 20 12 12 ISAAC 14.0 268.9 29 762 +1964 7 9 18 11 RAFAEL 17.5 10.5 69 7 +1978 2 14 0 26 PATTY 22.8 255.6 119 465 +1957 10 2 0 4 WILLIAM 63.1 129.6 149 556 +1973 5 24 6 10 ALBERTO 28.6 357.3 77 40 +1952 12 20 18 11 RAFAEL 60.2 350.0 14 291 +1957 1 26 12 4 MICHAEL 10.2 329.5 94 520 +1986 2 5 12 12 JOYCE 59.8 88.5 161 826 +1980 6 13 12 19 OSCAR 32.3 339.6 87 360 +1976 4 28 6 9 TONY 26.2 212.1 157 895 +1974 6 9 18 24 GORDON 54.0 35.8 100 168 +1977 9 4 6 24 SANDY 40.8 117.6 149 359 +2003 1 16 18 7 OSCAR 63.9 133.4 54 839 +2003 7 21 0 13 LESLIE 35.8 267.4 149 211 +1979 7 13 12 8 VALERIE 51.1 3.8 84 809 +1959 5 15 18 28 BERYL 28.8 135.7 13 441 +1979 4 22 0 15 LESLIE 14.7 241.7 46 240 +1953 3 7 12 1 HELENE 57.3 160.0 67 832 +1963 5 27 0 7 DEBBY 58.8 211.3 71 18 +1994 12 21 18 12 ALBERTO 47.7 199.4 149 571 +1994 4 27 18 25 ISAAC 61.6 49.4 89 308 +1958 11 12 6 3 ISAAC 67.8 11.4 31 390 +2004 7 22 12 20 FLORENCE 51.7 163.3 37 853 +1966 8 14 12 25 PATTY 61.0 189.0 79 478 +1994 3 3 0 22 FLORENCE 60.4 267.2 146 623 +1980 9 17 12 5 VALERIE 20.1 120.7 163 217 +1986 3 28 0 9 ISAAC 32.5 264.7 21 97 +1971 10 10 12 2 HELENE 60.8 11.8 131 741 +1961 2 24 18 12 BERYL 69.3 231.5 85 878 +1984 6 9 6 19 NADINE 19.9 244.0 56 493 +1973 4 13 6 18 OSCAR 63.3 175.7 43 162 +1965 11 26 12 10 DEBBY 63.9 20.0 122 46 +2004 2 16 12 14 JOYCE 20.6 119.7 43 614 +1951 5 2 12 11 ERNESTO 13.9 176.7 19 528 +1953 5 19 6 9 JOYCE 20.5 165.2 21 140 +1952 6 22 6 15 JOYCE 14.2 68.8 156 514 +1951 8 9 18 9 TONY 68.9 337.5 41 618 +1979 12 14 18 23 WILLIAM 8.9 148.5 77 890 +1954 4 15 6 1 KIRK 16.1 92.8 23 152 +1958 1 27 12 15 TONY 65.4 200.3 28 698 +1980 7 25 18 16 PATTY 49.7 228.7 66 76 +1958 9 11 6 21 RAFAEL 61.4 83.1 58 598 +2002 11 5 0 28 HELENE 26.3 44.4 27 768 +1970 9 25 18 9 WILLIAM 65.7 351.0 64 186 +1999 12 20 0 12 MICHAEL 19.8 48.5 32 395 +1961 3 7 12 18 ISAAC 69.7 253.7 56 769 +1993 9 27 18 3 JOYCE 48.2 219.2 99 26 +2003 3 11 12 22 SANDY 36.4 328.9 88 554 +1955 8 16 12 2 FLORENCE 31.9 90.1 110 742 +1962 7 3 0 4 KIRK 34.4 336.8 43 90 +1950 5 2 18 13 FLORENCE 42.2 5.3 140 842 +1995 11 5 0 28 OSCAR 16.6 54.8 111 151 +1956 9 5 18 26 JOYCE 24.6 109.5 160 256 +1959 10 26 6 22 JOYCE 48.6 51.3 145 279 +1984 5 4 6 13 PATTY 15.1 145.0 51 529 +1982 8 6 18 14 BERYL 32.7 46.1 108 543 +1950 6 10 6 26 CHRIS 14.9 60.1 27 327 +1984 10 19 0 22 DEBBY 26.3 345.4 102 888 +1983 12 26 12 28 CHRIS 18.0 298.2 121 634 +1960 7 18 0 22 MICHAEL 58.3 322.5 164 148 +2003 1 6 0 8 ISAAC 57.6 298.1 57 891 +1981 1 21 0 24 MICHAEL 21.5 178.8 162 854 +2000 1 12 18 22 DEBBY 22.9 35.6 35 673 +1955 11 10 6 8 VALERIE 68.4 236.8 18 479 +1996 7 17 0 22 ISAAC 62.6 325.5 54 322 +1976 6 13 6 11 NADINE 57.8 126.3 113 823 +1963 11 3 12 28 BERYL 32.0 230.4 158 389 +1988 7 5 6 9 KIRK 47.4 163.5 159 741 +1963 12 14 18 15 DEBBY 10.1 90.7 117 227 +1950 2 16 18 12 KIRK 69.9 233.6 27 50 +1955 10 3 12 6 OSCAR 33.9 18.2 27 132 +1993 12 25 18 5 PATTY 38.0 56.8 136 80 +1996 9 4 12 10 ALBERTO 26.5 173.5 148 859 +1950 8 20 18 13 ISAAC 66.2 52.2 162 783 +1985 9 20 18 23 VALERIE 58.9 97.1 70 368 +1964 9 18 6 7 PATTY 55.2 241.4 112 131 +1983 6 23 6 10 DEBBY 68.8 318.9 143 226 +1953 12 6 6 19 BERYL 20.7 58.4 40 340 +1995 3 25 6 7 RAFAEL 47.6 100.2 12 417 +1978 4 10 18 11 PATTY 49.4 115.9 80 473 +1963 8 4 12 26 RAFAEL 13.2 302.9 27 218 +1963 11 24 6 17 FLORENCE 56.1 19.0 144 779 +1955 4 16 18 11 LESLIE 16.2 228.5 87 517 +1982 11 22 6 18 FLORENCE 20.1 145.5 160 569 +1950 10 5 0 9 HELENE 43.9 82.5 14 756 +1965 8 3 18 27 FLORENCE 43.8 86.7 69 209 +1962 12 20 12 6 GORDON 57.1 107.4 144 491 +1956 1 4 6 23 OSCAR 33.6 116.9 104 327 +1961 11 23 6 22 ALBERTO 19.3 326.2 95 224 +1960 10 10 0 10 ERNESTO 49.5 44.6 15 108 +1989 11 23 6 22 SANDY 13.3 318.7 41 343 +2002 8 3 0 10 CHRIS 28.9 336.7 12 93 +1951 8 23 6 3 FLORENCE 30.9 162.7 56 67 +1999 8 11 12 7 ISAAC 59.3 37.8 142 894 +1966 8 14 18 17 MICHAEL 49.8 171.1 114 705 +1965 11 4 0 15 HELENE 36.0 234.0 115 196 +1992 11 13 0 11 CHRIS 43.0 171.4 48 255 +1992 2 4 18 20 SANDY 19.7 81.6 54 119 +2002 10 22 6 27 FLORENCE 66.0 268.5 109 223 +1977 10 5 0 22 BERYL 46.6 214.6 142 521 +1976 9 4 18 1 LESLIE 69.2 21.4 133 304 +1981 6 7 18 11 JOYCE 65.1 136.9 126 563 +1977 12 18 6 10 VALERIE 64.0 335.0 140 710 +2000 3 13 0 19 DEBBY 31.8 243.1 158 447 +1999 3 8 0 25 GORDON 21.9 231.5 85 431 +2000 5 23 0 19 OSCAR 25.5 251.6 63 518 +1978 2 28 0 4 DEBBY 19.6 155.9 43 629 +1981 3 2 12 16 FLORENCE 62.9 215.2 137 722 +1998 1 8 6 24 OSCAR 25.8 101.2 129 788 +1969 7 6 12 1 DEBBY 27.5 221.0 58 496 +1970 6 11 18 22 JOYCE 42.9 86.4 17 808 +1997 8 23 6 26 OSCAR 62.8 283.6 23 227 +1996 4 22 0 17 TONY 57.9 350.8 95 696 +1952 2 12 18 27 DEBBY 7.8 102.7 122 283 +1983 2 22 6 5 TONY 47.8 60.6 31 701 +2003 12 6 6 27 GORDON 10.0 19.3 155 45 +1985 3 16 6 9 VALERIE 56.0 257.7 159 577 +1957 2 17 18 28 PATTY 7.7 183.2 41 573 +1965 10 6 12 22 ALBERTO 65.1 13.7 13 859 +1951 4 7 18 1 CHRIS 21.1 193.6 99 282 +1961 3 21 18 28 PATTY 21.7 229.0 53 550 +1993 8 24 12 3 FLORENCE 65.9 356.8 124 265 +2000 12 13 6 5 SANDY 13.5 274.6 43 431 +1990 10 15 18 4 FLORENCE 64.8 108.4 159 236 +1988 3 21 12 3 LESLIE 9.2 204.2 123 123 +1972 5 21 6 24 GORDON 60.6 243.3 29 524 +1992 3 19 18 27 LESLIE 25.5 263.7 47 136 +1974 5 5 0 8 FLORENCE 23.6 288.6 153 890 +1973 11 13 6 21 KIRK 7.2 61.3 113 573 +1963 12 13 6 23 LESLIE 41.2 8.3 116 30 +1962 1 3 12 21 HELENE 23.5 66.3 94 782 +1984 4 1 0 5 KIRK 9.9 24.4 54 894 +1969 10 16 12 24 DEBBY 39.9 12.5 55 572 +1990 5 13 0 25 RAFAEL 44.6 218.0 76 513 +1969 3 22 18 13 WILLIAM 41.1 189.1 89 682 +1956 6 9 6 9 ALBERTO 23.4 343.3 10 858 +1989 11 24 12 6 OSCAR 54.7 35.9 49 127 +1992 3 28 6 12 VALERIE 29.8 95.0 61 238 +2002 4 5 12 23 HELENE 67.7 35.7 127 410 +1996 1 16 0 21 PATTY 20.4 333.2 134 520 +1967 7 1 6 11 CHRIS 62.0 303.4 20 815 +1976 1 2 0 1 NADINE 33.9 236.6 72 898 +1952 1 10 12 3 SANDY 68.2 219.6 108 81 +1997 6 16 0 18 OSCAR 52.7 140.0 13 768 +1968 4 22 6 2 GORDON 43.7 133.6 52 788 +1987 11 18 0 21 TONY 53.7 269.7 49 682 +1973 1 3 6 26 LESLIE 46.3 51.0 150 428 +1991 9 11 6 10 RAFAEL 10.9 285.0 24 574 +1950 12 23 0 12 DEBBY 24.8 148.7 70 403 +1981 11 16 18 6 ALBERTO 64.8 143.8 11 242 +1996 5 9 12 8 VALERIE 41.7 345.5 102 452 +1978 10 13 18 8 PATTY 57.3 154.1 141 61 +1985 6 27 18 8 DEBBY 34.2 204.5 139 687 +1957 2 18 0 8 RAFAEL 26.1 47.5 46 80 +1959 10 1 18 12 SANDY 54.2 208.0 116 219 +1995 12 11 18 17 CHRIS 65.1 29.7 21 369 +1992 2 6 6 12 ALBERTO 9.3 37.9 50 529 +1980 6 4 0 12 FLORENCE 45.7 139.8 119 772 +1992 12 25 18 8 MICHAEL 9.3 180.4 90 325 +1959 3 16 18 9 GORDON 27.5 41.5 13 412 +1988 6 6 18 24 WILLIAM 36.9 77.8 97 432 +1996 2 28 6 11 VALERIE 28.1 344.0 14 334 +1958 4 12 12 3 DEBBY 60.4 84.3 78 57 +1987 8 27 18 23 JOYCE 47.1 331.2 75 562 +2001 7 19 18 28 RAFAEL 31.6 128.2 62 838 +1958 3 12 0 15 KIRK 25.7 301.2 151 22 +1953 7 21 6 9 FLORENCE 56.7 153.4 149 649 +1998 12 23 12 17 TONY 49.8 115.3 21 529 +1969 6 26 18 5 VALERIE 43.1 44.9 66 818 +1966 8 9 12 18 CHRIS 33.5 20.8 121 400 +1951 7 4 12 7 FLORENCE 52.9 298.8 63 388 +1964 12 4 0 18 DEBBY 38.6 188.9 51 127 +1983 5 16 0 18 NADINE 23.4 193.7 44 310 +1976 12 13 18 21 PATTY 32.5 166.9 99 575 +1956 3 6 0 14 FLORENCE 59.2 59.5 50 163 +1996 6 8 18 6 MICHAEL 65.2 223.0 77 690 +2002 8 13 12 26 ISAAC 51.5 121.4 99 174 +1986 3 20 6 22 TONY 10.7 90.4 67 251 +1971 1 21 18 15 LESLIE 18.7 74.5 39 824 +1974 10 20 18 8 ISAAC 36.4 200.6 16 521 +1988 12 11 18 20 OSCAR 12.2 162.7 133 156 +1980 7 11 6 17 BERYL 63.0 273.9 46 366 +1966 11 17 12 16 SANDY 24.8 288.0 38 142 +1955 8 16 6 23 MICHAEL 9.2 310.4 46 810 +1979 3 28 0 3 BERYL 59.0 44.5 37 61 +1998 4 26 12 6 SANDY 60.2 26.7 117 686 +1988 4 20 12 24 GORDON 56.5 121.5 18 281 +1951 12 3 12 3 FLORENCE 7.3 214.7 92 373 +1995 6 22 12 2 VALERIE 18.2 203.9 48 130 +1981 6 7 18 14 VALERIE 8.4 247.6 114 549 +1965 3 8 0 19 NADINE 27.0 236.0 10 585 +1987 9 12 6 13 OSCAR 18.4 273.3 134 106 +1985 6 4 0 1 DEBBY 61.6 124.8 76 686 +1998 10 8 18 16 WILLIAM 69.1 160.4 65 474 +1969 6 15 6 12 FLORENCE 37.4 49.4 162 427 +1955 10 12 0 15 WILLIAM 25.1 74.2 110 696 +1957 11 6 12 11 CHRIS 8.8 307.2 152 864 +1952 1 9 0 15 ISAAC 60.9 172.8 163 396 +1954 11 22 18 1 SANDY 54.8 78.7 31 263 +1970 7 23 12 6 CHRIS 25.6 208.5 82 873 +1982 11 9 12 27 CHRIS 38.5 172.1 109 734 +1988 5 16 12 10 BERYL 67.5 338.1 117 37 +1977 8 12 0 24 DEBBY 28.0 150.6 131 730 +2002 4 20 18 27 NADINE 27.2 45.8 45 412 +1959 5 11 12 17 HELENE 32.8 114.8 153 517 +1964 5 25 18 6 ERNESTO 36.8 40.2 24 259 +1982 4 28 18 4 OSCAR 16.2 199.7 115 691 +1975 3 22 0 25 JOYCE 26.9 53.5 123 893 +1952 6 16 0 14 ERNESTO 13.8 296.7 93 583 +2001 2 22 0 12 JOYCE 32.1 113.7 67 819 +1992 3 20 18 5 NADINE 32.6 85.0 100 633 +1951 8 20 0 6 JOYCE 55.7 103.3 31 528 +1992 10 26 0 26 SANDY 22.4 221.4 19 289 +1969 1 6 12 4 PATTY 34.3 30.7 86 326 +1959 5 13 0 18 RAFAEL 41.0 118.4 34 166 +1966 4 20 6 24 ISAAC 52.2 37.1 71 6 +1951 9 19 12 20 OSCAR 21.0 119.1 113 589 +1952 11 5 0 5 CHRIS 69.1 133.3 136 14 +1957 10 4 18 7 HELENE 40.3 349.2 78 26 +1980 8 9 18 13 SANDY 27.5 299.7 139 337 +1983 12 19 12 13 TONY 62.3 274.6 155 332 +1986 7 13 18 28 NADINE 46.8 280.7 95 858 +2001 2 15 6 18 SANDY 68.9 151.4 163 290 +1969 9 4 6 25 SANDY 65.1 352.6 98 885 +1988 5 16 18 3 HELENE 55.4 274.5 50 32 +1960 12 26 18 5 ERNESTO 13.1 224.6 45 464 +1984 6 13 6 4 ALBERTO 12.6 218.4 153 892 +2002 5 16 6 16 RAFAEL 27.5 234.7 126 858 +1995 10 2 18 22 VALERIE 44.0 123.4 58 78 +1979 1 24 6 3 RAFAEL 33.3 279.8 148 498 +2003 5 28 6 4 HELENE 66.6 326.8 21 853 +1996 6 27 12 2 NADINE 46.6 354.8 42 407 +1985 7 17 6 4 NADINE 60.7 305.0 160 371 +1981 9 10 18 10 BERYL 29.0 332.5 119 49 +1952 12 26 18 11 LESLIE 16.5 255.1 81 804 +1975 2 7 12 9 ISAAC 10.9 302.4 106 732 +1950 3 25 0 25 OSCAR 54.4 80.6 24 720 +1954 9 26 18 3 SANDY 20.7 131.0 147 583 +1987 8 11 12 6 ALBERTO 70.0 119.2 97 826 +1953 9 14 0 25 ERNESTO 19.7 91.0 146 397 +1981 1 11 18 18 TONY 41.8 284.5 25 893 +1953 7 28 12 14 WILLIAM 28.3 71.0 29 862 +1987 1 25 18 26 CHRIS 15.0 57.6 16 463 +1960 9 25 18 2 ALBERTO 54.0 283.5 113 764 +1971 8 5 0 17 OSCAR 57.7 303.3 88 497 +1995 5 7 12 19 SANDY 16.5 91.1 99 24 +1958 2 23 6 10 NADINE 33.1 297.6 10 321 +1994 7 27 6 15 DEBBY 15.3 299.1 142 60 +1985 8 6 18 14 ISAAC 55.8 217.4 151 420 +1973 8 24 0 14 ALBERTO 7.3 239.2 72 755 +1986 2 19 18 27 FLORENCE 37.5 108.1 150 439 +1963 2 28 6 24 HELENE 18.3 71.9 149 548 +1997 10 3 0 10 BERYL 14.3 263.2 32 553 +1965 10 16 18 2 HELENE 51.0 296.5 75 66 +1969 4 14 0 4 FLORENCE 56.9 220.1 93 363 +1992 10 27 0 3 GORDON 30.4 85.4 19 47 +2002 1 4 6 27 LESLIE 40.6 147.3 75 27 +1988 1 14 12 8 MICHAEL 65.3 105.2 141 580 +1956 8 8 12 1 OSCAR 56.2 297.6 93 783 +1952 12 16 0 12 OSCAR 33.4 121.2 70 731 +1982 9 20 12 9 JOYCE 20.5 327.3 134 372 +1984 10 24 0 23 TONY 59.7 100.1 75 97 +1984 12 9 6 25 JOYCE 67.0 286.4 45 215 +1971 11 17 18 4 DEBBY 26.2 248.4 55 360 +1957 2 20 18 5 BERYL 17.2 277.6 36 869 +1981 3 7 12 11 JOYCE 65.8 12.8 115 7 +1989 6 2 0 20 BERYL 65.5 117.5 109 845 +1991 2 3 18 27 MICHAEL 59.4 215.3 33 397 +1996 1 8 6 27 OSCAR 44.3 276.3 164 717 +1966 5 3 12 24 GORDON 56.5 208.0 148 626 +1988 5 20 12 4 LESLIE 64.5 189.9 143 525 +1960 10 10 12 16 LESLIE 11.9 225.9 48 212 +1957 4 2 6 6 GORDON 65.5 250.1 27 143 +1996 7 4 6 23 RAFAEL 50.5 118.9 137 737 +1975 2 3 18 20 GORDON 52.2 113.6 122 202 +1951 3 19 12 6 TONY 56.9 119.0 88 229 +1979 8 28 18 17 MICHAEL 18.4 173.7 24 61 +1984 10 23 12 11 LESLIE 16.1 56.2 20 399 +1978 12 27 12 21 VALERIE 26.2 284.7 108 430 +1955 11 17 0 3 KIRK 52.7 191.0 88 86 +1951 7 3 12 26 ISAAC 64.7 352.0 14 644 +1967 10 27 12 4 CHRIS 22.0 344.5 164 816 +1990 1 20 12 1 VALERIE 12.5 312.9 94 817 +2002 5 26 12 6 MICHAEL 11.9 106.5 140 359 +2000 12 23 6 17 ERNESTO 11.9 241.5 17 381 +1995 11 14 12 25 GORDON 21.0 60.6 152 37 +1989 12 11 18 16 MICHAEL 38.6 163.7 27 231 +1969 6 23 18 15 SANDY 12.6 116.7 23 298 +2003 4 18 18 4 MICHAEL 68.1 297.6 151 152 +1956 6 24 12 7 WILLIAM 60.8 356.8 100 591 +1956 2 5 12 12 TONY 20.7 328.8 28 150 +1980 2 26 12 13 VALERIE 23.6 197.4 34 251 +1985 8 5 6 21 WILLIAM 22.5 101.9 89 644 +1983 5 27 12 7 KIRK 67.4 37.2 27 721 +1952 10 21 12 12 LESLIE 58.8 301.7 137 1 +1978 3 18 12 23 SANDY 44.6 276.0 12 183 +1997 2 27 12 24 ALBERTO 28.8 239.9 95 736 +1967 12 13 6 10 RAFAEL 20.1 114.9 155 102 +1994 5 10 6 26 OSCAR 40.8 263.4 36 146 +1953 8 27 0 11 FLORENCE 13.0 232.6 130 705 +1970 12 24 18 16 WILLIAM 66.1 62.5 33 374 +1978 1 13 0 4 MICHAEL 33.0 17.0 163 651 +1963 4 3 12 6 JOYCE 25.9 201.0 25 824 +1987 7 25 18 14 TONY 43.7 83.0 150 140 +1967 6 23 18 4 WILLIAM 18.7 26.5 61 865 +1994 7 22 0 17 FLORENCE 35.9 145.7 40 156 +1952 1 11 12 19 JOYCE 63.8 352.1 118 561 +1951 4 23 6 9 LESLIE 53.5 305.6 12 80 +1984 5 20 0 10 DEBBY 65.9 305.9 94 353 +1976 5 12 18 21 ISAAC 49.5 13.4 106 479 +1997 9 3 0 9 CHRIS 39.3 92.5 162 12 +1960 11 4 6 7 RAFAEL 68.6 328.9 54 501 +1968 11 23 6 10 KIRK 14.1 153.3 119 817 +1996 10 3 18 22 PATTY 20.3 122.9 110 412 +1963 3 16 18 9 ALBERTO 38.3 328.9 129 211 +1955 8 6 6 7 VALERIE 53.9 247.0 36 333 +1999 3 25 0 5 MICHAEL 35.8 82.7 22 206 +2004 4 1 12 23 NADINE 60.2 222.0 129 155 +1957 8 23 6 25 GORDON 52.1 49.5 108 475 +1969 7 12 6 3 NADINE 21.3 6.0 71 248 +1998 11 15 18 26 LESLIE 30.4 95.7 13 126 +2004 8 1 6 14 RAFAEL 56.8 108.3 115 490 +1982 5 9 18 17 OSCAR 26.1 3.6 71 45 +1992 1 9 12 3 LESLIE 29.7 299.6 110 21 +1976 8 14 12 24 TONY 54.9 298.6 84 278 +1970 5 25 12 15 JOYCE 21.5 324.4 48 220 +1954 1 18 18 1 FLORENCE 12.8 162.8 104 457 +1955 7 23 6 8 DEBBY 36.2 164.0 96 752 +2000 4 8 6 27 ALBERTO 10.5 178.7 18 236 +1993 5 12 18 22 ERNESTO 12.1 38.0 74 637 +1983 3 4 18 11 TONY 62.7 238.2 66 96 +1954 8 11 12 11 SANDY 19.8 323.8 99 740 +1985 12 18 0 15 KIRK 16.4 326.0 77 467 +1962 11 1 18 18 OSCAR 32.3 96.1 98 640 +1972 6 4 18 16 ALBERTO 12.8 62.5 20 228 +1951 12 4 0 1 VALERIE 22.1 207.0 96 269 +2001 12 18 6 13 ALBERTO 32.2 241.2 126 649 +1986 8 19 6 4 KIRK 16.5 339.8 47 55 +1964 12 4 6 17 NADINE 58.7 50.8 142 430 +1977 2 16 12 14 NADINE 65.8 257.5 104 29 +1980 3 17 0 3 SANDY 22.6 231.6 79 863 +1992 5 7 0 6 KIRK 45.1 259.2 31 672 +1971 7 18 6 13 OSCAR 62.8 173.3 130 259 +1961 2 12 6 1 LESLIE 51.6 157.1 102 106 +1967 10 21 18 3 NADINE 52.3 80.5 56 614 +2004 3 4 0 6 TONY 56.7 73.2 131 311 +2003 9 7 6 11 ALBERTO 50.8 215.2 83 280 +1972 9 11 6 2 JOYCE 67.6 53.1 161 390 +1958 4 2 18 15 FLORENCE 12.6 303.8 103 659 +2004 5 14 18 21 NADINE 49.6 30.9 102 455 +1955 5 24 6 28 WILLIAM 44.0 207.0 75 145 +1993 11 21 12 8 TONY 7.4 202.9 45 632 +1964 8 20 12 25 BERYL 10.6 22.0 76 784 +1997 1 17 0 5 KIRK 26.2 126.1 34 466 +1983 1 4 6 3 FLORENCE 58.6 216.8 41 566 +1989 12 8 12 5 KIRK 62.1 287.0 35 469 +1954 8 28 12 17 JOYCE 46.8 299.6 23 457 +1971 10 25 0 19 GORDON 44.6 36.9 54 780 +1973 6 23 18 25 CHRIS 27.3 330.2 16 19 +1989 7 6 6 6 VALERIE 25.9 229.7 16 655 +1968 10 16 18 4 ISAAC 33.7 120.2 105 214 +1983 5 27 0 25 WILLIAM 12.5 120.9 29 323 +1958 6 7 12 21 GORDON 53.7 183.6 62 818 +1995 4 16 18 10 BERYL 33.7 173.3 91 231 +1950 6 6 18 22 SANDY 28.6 96.2 93 514 +1965 6 22 12 3 CHRIS 31.9 29.3 162 108 +1997 6 8 6 10 BERYL 14.5 173.9 21 412 +1950 10 19 6 27 SANDY 15.4 256.9 37 886 +1958 8 14 0 27 JOYCE 41.3 69.8 89 727 +1987 4 6 0 14 ISAAC 7.5 84.0 135 711 +1995 5 21 12 6 OSCAR 34.1 277.9 70 750 +1970 12 19 18 28 VALERIE 57.7 159.2 141 733 +1986 3 2 0 11 WILLIAM 60.6 279.9 19 788 +2001 3 27 18 28 CHRIS 69.7 158.7 112 560 +1950 8 6 18 4 MICHAEL 10.2 299.6 133 795 +1997 7 4 0 26 ALBERTO 24.1 321.8 10 598 +1955 6 5 6 1 DEBBY 62.8 350.1 106 168 +1971 9 28 6 7 KIRK 40.9 276.9 83 293 +1969 6 27 18 21 DEBBY 39.8 85.1 137 396 +1979 8 21 18 10 LESLIE 60.4 176.0 48 259 +1975 4 4 0 28 ALBERTO 68.3 26.2 134 8 +1980 10 18 12 20 NADINE 39.8 76.5 144 31 +1977 6 22 0 4 WILLIAM 61.5 297.4 116 798 +1978 7 7 12 8 GORDON 64.8 80.7 43 153 +1980 8 12 12 7 GORDON 41.8 27.7 154 805 +1968 7 26 12 10 WILLIAM 56.2 284.0 102 799 +1994 4 14 6 24 OSCAR 68.7 172.3 131 170 +1988 7 25 18 6 ISAAC 53.2 25.0 69 277 +1992 11 13 18 17 BERYL 33.3 101.0 51 52 +1994 5 12 6 10 OSCAR 48.8 336.3 123 695 +1980 4 20 6 26 CHRIS 19.9 260.1 54 223 +1954 10 24 0 9 MICHAEL 58.7 14.9 95 510 +1982 2 2 6 9 SANDY 52.4 106.6 138 881 +1954 11 26 18 5 HELENE 33.6 215.1 50 681 +1957 9 2 12 20 PATTY 17.5 132.4 141 36 +1991 1 3 12 9 ALBERTO 64.1 234.2 40 612 +1978 7 13 6 16 LESLIE 21.2 318.9 133 791 +1950 3 18 12 25 BERYL 14.2 268.0 139 662 +1967 8 28 18 28 ERNESTO 23.2 107.6 28 264 +1960 3 21 6 18 TONY 50.9 190.0 75 165 +1960 2 8 6 16 HELENE 36.4 250.1 33 389 +1978 7 13 12 27 CHRIS 55.6 332.2 122 256 +1977 7 25 18 5 DEBBY 64.7 144.7 62 459 +1961 9 26 12 15 ALBERTO 59.2 47.5 98 288 +1994 8 16 18 2 JOYCE 27.6 108.4 67 855 +1972 3 28 6 7 DEBBY 20.8 14.8 105 22 +1977 12 18 18 16 FLORENCE 41.5 103.4 114 382 +1984 11 22 6 2 DEBBY 45.9 80.2 60 92 +2000 1 15 18 15 DEBBY 40.2 248.7 125 725 +1973 11 14 6 21 ISAAC 14.1 14.8 137 491 +1993 6 3 18 26 WILLIAM 8.6 74.3 43 349 +2004 6 10 12 21 OSCAR 37.5 226.3 129 130 +1979 3 3 0 12 TONY 65.0 76.7 89 701 +1980 12 23 12 6 GORDON 52.5 343.2 71 467 +1977 5 21 12 18 HELENE 32.4 210.2 59 487 +1980 5 5 12 7 ALBERTO 35.7 220.8 158 19 +1952 5 14 18 5 ISAAC 69.5 341.2 15 66 +1953 9 3 6 8 ERNESTO 27.2 312.5 31 888 +1975 9 23 12 11 OSCAR 17.5 272.3 113 727 +1976 9 13 6 24 WILLIAM 52.1 202.8 82 543 +1996 11 18 6 27 MICHAEL 49.9 293.1 149 251 +1953 4 6 0 23 VALERIE 40.2 337.9 124 178 +1987 11 8 18 1 NADINE 59.7 188.0 146 809 +1975 3 4 6 27 KIRK 64.7 177.6 17 725 +1972 1 16 18 24 MICHAEL 53.9 341.3 149 581 +1980 5 1 18 12 ALBERTO 15.8 228.3 90 454 +1999 11 15 0 28 JOYCE 43.8 186.3 143 798 +1953 1 1 0 21 LESLIE 26.8 334.7 62 669 +1984 2 26 18 2 DEBBY 68.4 159.1 100 772 +1964 12 9 0 9 JOYCE 69.3 56.2 30 515 +1958 11 9 18 1 OSCAR 8.1 11.1 28 608 +2001 5 7 12 21 SANDY 17.0 192.1 154 588 +2004 10 17 18 9 MICHAEL 32.6 151.1 51 247 +1969 1 7 18 7 DEBBY 34.0 212.7 57 638 +1995 9 21 18 19 JOYCE 48.6 29.3 160 823 +1976 10 25 0 5 GORDON 41.8 105.5 154 299 +1972 1 24 6 16 OSCAR 61.3 42.6 77 271 +1963 5 11 6 21 TONY 24.3 309.5 15 391 +1976 1 1 12 11 PATTY 49.3 285.5 153 840 +1962 2 23 12 9 BERYL 53.0 2.0 82 648 +2002 4 23 0 17 KIRK 42.5 128.7 80 10 +1996 3 8 12 20 BERYL 23.0 154.6 81 194 +1993 8 8 6 20 ISAAC 55.3 281.6 75 825 +1988 8 19 18 8 LESLIE 44.7 258.7 42 247 +1982 11 21 18 4 ISAAC 13.0 68.9 41 73 +2004 8 18 18 11 CHRIS 19.3 24.8 105 76 +1962 2 17 12 14 LESLIE 24.8 127.2 72 813 +1965 11 18 12 12 TONY 10.0 256.4 21 304 +1978 6 15 6 21 NADINE 44.5 308.6 20 613 +2004 10 1 18 4 JOYCE 53.6 112.2 133 7 +1993 9 17 12 1 RAFAEL 20.0 193.3 134 267 +1957 1 2 18 23 OSCAR 39.8 47.3 132 322 +1973 11 6 12 5 FLORENCE 55.4 338.2 111 218 +1958 7 20 12 4 CHRIS 17.3 73.5 151 259 +1968 12 12 0 21 FLORENCE 34.0 94.7 90 512 +1989 11 25 18 1 PATTY 16.8 47.4 45 240 +1957 5 16 18 21 PATTY 26.9 192.8 16 340 +1996 4 7 18 15 OSCAR 23.7 286.4 79 838 +1986 12 27 0 4 TONY 31.9 127.7 144 525 +1954 7 3 6 28 WILLIAM 44.4 292.5 145 296 +1958 5 20 6 25 GORDON 59.2 352.9 21 823 +1957 5 13 0 25 VALERIE 24.5 37.4 99 709 +1981 8 20 12 24 VALERIE 16.2 63.0 146 289 +1973 3 5 0 1 VALERIE 7.7 34.8 47 549 +1951 3 11 6 15 GORDON 30.4 300.8 89 855 +1962 1 2 0 11 FLORENCE 62.6 309.8 41 447 +1991 4 24 12 24 FLORENCE 48.0 213.3 17 799 +1973 10 3 18 8 FLORENCE 68.6 91.4 141 549 +1958 4 17 0 26 KIRK 15.8 204.4 37 133 +1986 6 20 12 20 FLORENCE 56.7 82.5 132 831 +1968 9 14 12 2 NADINE 22.8 127.9 139 194 +2004 2 6 0 1 HELENE 12.1 214.8 85 803 +1995 11 2 0 19 WILLIAM 10.3 15.4 85 108 +1976 3 7 6 19 FLORENCE 37.8 271.7 42 177 +1970 3 16 0 12 DEBBY 57.9 187.5 22 115 +1984 1 5 6 10 DEBBY 56.8 107.4 115 659 +1954 6 1 6 15 ISAAC 35.9 51.6 60 271 +1964 6 23 6 22 RAFAEL 44.9 168.5 146 711 +1976 11 21 6 7 LESLIE 60.1 100.3 55 760 +1979 6 15 6 23 TONY 20.6 27.1 77 594 +1995 2 15 18 6 SANDY 29.3 3.9 100 255 +1960 11 18 18 28 NADINE 56.1 74.4 93 755 +1993 6 23 0 21 BERYL 41.1 293.4 99 733 +1999 4 23 6 15 RAFAEL 17.1 74.2 74 105 +2004 10 7 6 24 OSCAR 23.0 195.8 10 221 +1959 5 11 0 22 LESLIE 7.7 130.4 111 676 +1997 11 28 12 28 TONY 17.3 341.8 77 334 +1973 11 13 12 22 BERYL 21.8 157.6 44 700 +1960 9 17 6 12 DEBBY 30.4 240.2 93 475 +1969 9 5 12 7 OSCAR 65.0 178.6 45 821 +1991 5 12 12 18 RAFAEL 49.6 240.8 43 49 +1994 5 21 6 26 PATTY 14.7 28.5 89 720 +1987 4 28 18 17 GORDON 40.0 158.3 81 357 +1984 1 2 0 24 TONY 13.0 285.7 12 69 +1998 7 26 6 11 KIRK 32.5 241.6 33 87 +1963 1 7 0 25 HELENE 48.6 345.9 48 612 +1970 9 22 12 27 JOYCE 32.7 126.4 141 271 +2004 9 5 18 26 ISAAC 59.4 334.2 45 37 +1967 8 24 12 27 CHRIS 63.8 116.3 137 0 +1978 11 22 18 15 HELENE 58.1 181.6 122 694 +1962 2 8 12 11 MICHAEL 11.0 271.8 76 855 +1988 2 9 18 18 ALBERTO 49.6 327.6 114 868 +2002 1 16 12 27 NADINE 45.4 26.6 96 404 +1960 7 25 12 18 ISAAC 30.6 307.7 117 352 +1983 9 16 18 2 SANDY 37.3 187.0 35 305 +1956 1 10 12 4 PATTY 42.7 133.8 60 192 +1970 5 4 18 15 FLORENCE 20.7 219.1 139 290 +1978 6 25 18 20 CHRIS 68.1 292.6 11 651 +2004 4 13 6 7 OSCAR 49.6 118.1 66 808 +1981 6 21 12 5 NADINE 35.9 84.5 138 283 +1958 6 19 0 28 BERYL 25.9 339.0 21 517 +1991 2 24 6 7 DEBBY 14.5 159.8 132 671 +1952 12 26 0 12 GORDON 68.0 283.9 98 667 +2004 5 26 0 21 RAFAEL 69.6 339.0 112 120 +1954 2 5 6 20 RAFAEL 64.6 52.8 19 553 +1950 3 2 18 9 GORDON 55.4 354.4 16 647 +1998 9 11 12 10 FLORENCE 29.1 265.2 103 674 +1983 7 2 0 5 SANDY 32.3 353.1 142 787 +2000 11 6 18 22 BERYL 23.4 304.1 45 137 +1952 11 21 12 22 GORDON 48.7 55.0 58 7 +1980 9 12 6 8 GORDON 38.3 227.9 69 118 +1997 3 5 12 20 OSCAR 20.4 7.7 145 386 +1958 9 10 6 23 BERYL 44.8 291.5 85 12 +1957 12 6 0 26 TONY 50.9 59.1 28 638 +1976 7 5 18 11 LESLIE 13.2 261.7 81 313 +2004 6 15 6 22 CHRIS 44.1 255.3 58 260 +1982 3 25 18 10 PATTY 45.9 157.8 121 375 +2001 9 11 0 17 BERYL 57.7 276.2 80 737 +1964 11 2 18 14 PATTY 58.4 251.4 114 412 +1971 6 4 0 27 VALERIE 56.5 288.5 10 66 +2004 11 23 0 15 NADINE 30.4 184.6 91 315 +1994 1 4 18 13 ALBERTO 16.2 210.0 29 518 +1963 7 23 18 21 DEBBY 34.4 155.0 131 110 +1987 7 25 12 6 JOYCE 9.3 97.6 104 326 +1950 4 2 18 23 TONY 29.8 308.0 40 687 +1962 1 13 12 14 BERYL 32.7 307.9 50 528 +1951 9 14 12 1 OSCAR 38.5 59.5 48 561 +1989 10 5 12 22 GORDON 15.9 117.1 103 184 +1982 2 6 12 18 MICHAEL 15.2 282.5 159 701 +1973 2 14 0 24 FLORENCE 69.2 264.5 102 95 +1996 12 12 0 2 VALERIE 17.0 102.1 34 831 +1987 2 19 18 6 JOYCE 48.2 2.5 19 260 +2000 8 19 0 2 OSCAR 43.3 118.2 129 787 +2001 1 8 6 7 FLORENCE 22.6 341.5 22 289 +1956 2 12 12 24 ERNESTO 65.3 152.2 36 266 +2001 9 25 12 4 ERNESTO 18.8 11.4 108 326 +1966 4 28 18 3 DEBBY 13.5 200.8 15 225 +1965 12 19 0 9 HELENE 14.1 33.8 26 674 +1991 9 25 12 19 JOYCE 15.7 315.4 53 817 +2004 9 21 12 16 BERYL 11.4 253.5 121 317 +1979 11 22 18 14 MICHAEL 28.7 256.2 24 470 +1965 11 21 6 2 RAFAEL 48.5 43.7 78 756 +2004 3 17 12 4 WILLIAM 15.9 136.3 30 652 +1965 6 13 6 24 ALBERTO 25.5 146.8 161 721 +1980 5 16 6 4 NADINE 28.7 103.6 121 796 +1998 10 25 0 27 HELENE 50.9 82.8 115 247 +2003 1 14 12 25 BERYL 27.8 40.9 152 415 +1972 1 15 12 19 JOYCE 57.0 117.6 48 511 +1999 2 7 12 23 ERNESTO 48.7 269.4 146 643 +1956 12 9 12 7 RAFAEL 60.4 225.0 101 290 +1983 2 23 0 21 KIRK 17.1 205.4 24 207 +1964 6 12 18 9 TONY 69.4 9.6 14 643 +1989 6 28 6 13 RAFAEL 66.0 52.3 99 698 +1958 9 17 12 22 RAFAEL 37.0 333.1 54 469 +1968 8 12 6 15 BERYL 42.3 206.3 27 425 +1974 6 10 12 8 SANDY 32.5 351.7 133 135 +1956 5 1 12 6 LESLIE 21.0 246.3 86 142 +2004 7 3 18 7 RAFAEL 42.1 260.3 58 443 +1956 6 17 0 23 RAFAEL 51.7 195.2 140 293 +1974 5 27 0 28 PATTY 66.3 136.4 112 64 +1977 9 4 0 2 RAFAEL 59.2 355.5 118 683 +1965 8 23 12 27 ALBERTO 16.7 226.0 40 853 +1999 3 8 0 19 TONY 18.0 130.2 38 97 +1981 8 2 6 24 LESLIE 69.6 46.9 82 39 +1988 9 27 18 2 ERNESTO 48.4 93.5 24 390 +1952 8 17 18 24 ALBERTO 63.5 228.2 52 737 +1979 1 28 0 3 HELENE 59.8 133.0 48 237 +1981 5 21 12 13 KIRK 58.0 119.9 23 518 +1999 5 1 18 15 DEBBY 52.2 316.1 101 606 +1960 7 27 0 9 RAFAEL 42.7 163.4 48 449 +1950 11 25 0 8 LESLIE 23.6 239.3 132 306 +2003 4 21 18 8 ERNESTO 49.2 2.7 54 842 +1990 5 18 6 19 WILLIAM 68.1 20.6 21 435 +1994 8 4 12 15 ALBERTO 47.8 228.8 56 163 +1989 10 11 12 18 CHRIS 62.2 148.2 161 312 +2002 10 25 0 5 ALBERTO 11.4 276.8 91 34 +1977 6 28 0 6 SANDY 43.7 338.4 27 597 +1957 4 16 12 9 MICHAEL 16.4 51.5 74 536 +1953 8 8 0 3 DEBBY 52.1 99.1 94 26 +1994 7 5 0 14 WILLIAM 10.1 145.2 156 347 +1954 2 12 12 21 DEBBY 47.1 123.7 14 513 +1975 7 28 12 28 PATTY 61.7 158.7 143 613 +1994 11 7 18 8 WILLIAM 53.9 282.8 43 419 +1986 12 20 6 13 ERNESTO 64.1 298.0 50 638 +1979 2 18 12 27 MICHAEL 49.6 237.4 77 10 +1997 10 21 6 1 KIRK 28.0 104.9 155 500 +1996 10 19 12 23 KIRK 22.6 142.9 75 579 +1968 7 23 12 1 JOYCE 59.0 224.8 62 562 +1981 4 1 12 16 RAFAEL 58.6 262.5 96 438 +1994 1 3 6 11 ERNESTO 24.1 10.2 117 796 +1966 5 23 0 3 WILLIAM 46.8 271.9 103 440 +1960 11 8 6 4 GORDON 18.0 241.0 19 354 +1990 6 4 18 4 VALERIE 58.7 199.0 68 401 +1997 9 2 6 12 ALBERTO 54.9 232.2 45 378 +1996 2 15 0 12 OSCAR 11.9 48.1 39 491 +1981 3 1 18 17 TONY 37.6 273.8 58 658 +1950 12 15 0 5 ALBERTO 13.5 218.1 16 405 +1996 5 13 18 26 GORDON 24.4 17.4 30 85 +1993 1 6 0 19 KIRK 46.5 162.8 127 226 +1977 4 20 18 12 OSCAR 54.8 141.4 99 130 +1969 2 21 6 1 WILLIAM 62.3 291.0 50 311 +1993 1 4 0 2 DEBBY 35.4 70.5 34 574 +1979 8 26 0 22 SANDY 33.4 56.5 113 144 +1957 10 3 0 6 FLORENCE 29.4 178.2 49 882 +1991 6 26 0 12 JOYCE 65.1 171.5 64 296 +1967 6 10 18 12 FLORENCE 19.5 348.1 75 75 +1952 10 7 12 12 NADINE 54.7 264.5 38 770 +1976 8 9 18 23 DEBBY 39.5 164.0 78 571 +1981 12 11 18 21 TONY 20.3 140.7 126 449 +1981 9 23 0 2 FLORENCE 54.0 64.9 123 588 +1978 5 18 6 26 SANDY 49.9 131.7 93 744 +1954 6 15 6 22 MICHAEL 41.1 258.7 120 679 +1962 6 21 18 12 BERYL 54.0 268.5 159 387 +1967 12 3 6 7 ERNESTO 40.0 46.8 81 27 +1973 7 3 18 5 ISAAC 40.2 142.8 161 238 +1977 9 24 12 10 VALERIE 51.3 193.5 64 515 +1962 10 10 18 1 JOYCE 42.8 339.1 30 555 +1955 3 25 6 17 TONY 42.2 209.7 127 471 +1983 1 19 0 17 DEBBY 33.1 305.6 41 647 +1964 7 5 12 8 BERYL 11.4 146.1 81 718 +1989 11 28 0 25 ALBERTO 35.2 334.0 76 569 +1985 1 19 12 14 SANDY 32.2 205.1 158 156 +1974 12 19 18 2 MICHAEL 52.1 69.4 53 847 +2001 1 8 0 27 DEBBY 38.2 173.8 72 352 +1952 10 5 18 8 CHRIS 54.5 236.1 132 655 +1988 11 17 18 28 ERNESTO 25.4 71.6 80 791 +1986 12 26 0 16 OSCAR 57.0 184.2 38 105 +1991 6 15 6 4 FLORENCE 37.6 270.2 78 895 +1972 7 13 18 21 LESLIE 55.0 41.2 132 620 +1997 6 14 18 15 RAFAEL 13.5 22.0 149 651 +1975 1 27 6 10 ALBERTO 35.1 213.7 26 239 +1977 11 13 18 23 HELENE 56.1 285.8 85 61 +1960 4 4 18 11 TONY 35.2 48.0 162 773 +1954 9 5 6 26 FLORENCE 46.0 171.6 40 639 +1970 11 3 12 16 SANDY 56.6 140.6 27 811 +1958 9 27 6 25 NADINE 34.6 215.4 77 8 +1992 10 5 0 3 CHRIS 50.4 91.9 62 661 +1951 4 13 18 27 FLORENCE 12.7 206.6 25 482 +2003 9 22 18 8 ALBERTO 12.8 26.6 111 460 +1972 10 7 0 4 ISAAC 45.9 96.2 18 306 +1995 1 3 6 6 NADINE 9.0 188.1 21 303 +1962 1 17 0 13 JOYCE 60.3 75.8 24 374 +1997 2 13 0 16 ALBERTO 67.8 157.5 114 430 +2002 1 28 6 14 JOYCE 54.5 60.2 68 101 +1990 12 13 12 3 FLORENCE 27.7 10.6 45 373 +1983 6 12 18 16 PATTY 42.8 309.2 93 820 +1962 7 28 6 16 JOYCE 7.7 230.7 69 68 +1989 9 7 6 21 ALBERTO 15.1 98.6 96 181 +1980 3 2 6 4 MICHAEL 32.3 186.6 91 85 +1983 5 21 6 28 WILLIAM 39.9 293.4 87 133 +1979 4 28 12 26 CHRIS 31.5 49.4 90 422 +1998 10 28 12 27 NADINE 35.9 221.5 121 461 +1971 5 21 6 25 NADINE 28.2 13.5 59 36 +1960 10 24 6 6 RAFAEL 51.3 95.4 15 257 +1991 8 8 6 7 RAFAEL 41.4 33.0 123 702 +1959 7 11 12 25 ISAAC 65.7 293.6 140 891 +1953 5 13 0 24 VALERIE 58.7 139.1 40 173 +1970 8 9 6 18 SANDY 18.7 113.5 77 633 +1987 7 17 0 17 KIRK 30.0 352.6 50 291 +1990 3 3 12 27 OSCAR 64.5 81.0 163 727 +1986 2 24 6 16 FLORENCE 18.6 214.9 85 824 +1956 2 2 12 13 GORDON 8.3 281.1 57 410 +1971 11 20 18 19 ISAAC 26.2 32.5 163 734 +1985 6 9 6 17 TONY 32.5 317.3 158 291 +1998 3 24 18 7 WILLIAM 16.2 130.5 125 55 +1962 3 6 0 17 SANDY 35.6 41.7 18 333 +1969 8 5 18 18 OSCAR 68.5 31.9 139 585 +1979 3 22 0 16 SANDY 45.3 123.8 52 855 +1959 11 8 12 1 KIRK 30.6 138.9 104 757 +1980 11 28 0 21 TONY 41.8 92.9 131 77 +1981 5 19 18 5 KIRK 20.9 341.4 38 453 +1994 7 11 12 19 LESLIE 53.2 141.1 57 763 +2004 9 20 6 12 HELENE 46.5 154.3 126 624 +1994 1 6 0 2 OSCAR 33.7 295.6 124 765 +1985 11 28 6 14 WILLIAM 51.6 128.5 26 361 +1987 10 25 0 3 WILLIAM 63.9 22.1 43 47 +1994 5 24 6 25 CHRIS 9.1 74.4 28 614 +1987 4 27 12 12 WILLIAM 63.3 135.5 138 31 +1981 12 22 18 6 NADINE 65.0 349.8 58 379 +2000 1 25 0 7 LESLIE 33.3 48.4 129 897 +1979 12 9 18 23 RAFAEL 8.1 66.7 24 632 +2000 1 9 6 23 CHRIS 52.3 266.0 77 479 +1980 6 18 12 7 PATTY 40.6 182.1 38 890 +1954 2 2 0 14 SANDY 68.6 160.6 159 898 +1954 10 2 18 11 VALERIE 59.2 227.6 104 776 +1975 4 5 12 11 ALBERTO 8.6 6.5 157 737 +1991 6 14 12 15 SANDY 11.8 25.5 30 178 +1950 7 21 18 4 GORDON 65.0 294.6 73 595 +1961 1 20 12 12 LESLIE 16.6 346.7 82 16 +1951 8 9 12 6 ISAAC 30.6 260.1 124 189 +1996 9 11 12 24 MICHAEL 44.6 350.4 160 873 +1990 5 11 18 18 CHRIS 58.3 78.5 46 553 +1974 8 5 6 13 TONY 42.8 18.6 97 765 +1961 3 28 18 12 PATTY 18.6 55.1 118 500 +1953 12 1 0 20 JOYCE 43.3 155.8 158 377 +1964 2 20 6 10 DEBBY 42.8 318.9 49 329 +1991 3 2 18 18 TONY 59.5 181.5 79 416 +1987 11 27 18 16 PATTY 60.4 158.2 132 95 +1999 3 18 12 28 ISAAC 42.8 252.0 10 263 +2003 12 16 18 3 KIRK 39.5 338.7 126 273 +2003 2 5 0 26 OSCAR 19.4 205.9 146 361 +2002 9 18 12 22 VALERIE 47.9 5.0 115 626 +1977 3 19 18 17 ERNESTO 57.1 35.6 156 397 +1999 7 4 6 4 RAFAEL 30.9 131.3 25 236 +1955 1 25 18 22 TONY 25.6 79.6 57 665 +1979 10 17 12 15 VALERIE 10.7 118.0 144 425 +1966 3 26 6 18 ALBERTO 21.3 57.3 13 776 +1988 11 19 12 27 WILLIAM 13.2 71.2 28 255 +2004 11 18 0 17 ALBERTO 47.1 84.9 124 296 +1962 1 6 6 18 GORDON 69.4 139.6 55 755 +1951 12 5 0 4 TONY 41.8 17.6 47 37 +1981 11 8 18 13 WILLIAM 52.7 341.2 54 51 +1985 9 18 0 17 RAFAEL 30.6 284.4 84 423 +1990 1 22 6 25 ALBERTO 52.1 203.1 138 301 +1963 1 16 6 18 WILLIAM 23.0 357.3 29 335 +1957 6 24 12 23 DEBBY 37.4 186.0 121 168 +1974 11 11 12 25 MICHAEL 16.6 57.9 88 677 +1996 2 7 6 15 ALBERTO 8.1 189.2 127 611 +1952 9 10 0 16 KIRK 23.8 273.9 41 599 +1996 8 12 6 16 NADINE 20.0 3.0 157 463 +1961 7 12 0 15 ERNESTO 57.7 38.1 122 314 +1959 8 20 0 22 JOYCE 16.5 14.9 71 113 +1963 3 11 6 27 CHRIS 54.9 26.9 20 345 +1991 6 8 0 7 JOYCE 53.8 81.5 14 830 +1953 7 14 12 26 JOYCE 22.7 205.8 161 805 +1984 11 8 18 19 FLORENCE 69.1 332.5 131 24 +1982 8 16 18 22 FLORENCE 64.8 267.8 102 866 +1988 7 24 0 28 OSCAR 25.6 284.1 105 50 +1980 1 8 0 5 OSCAR 26.6 281.2 107 496 +1957 11 10 18 14 SANDY 53.2 186.3 60 421 +1972 8 2 18 9 SANDY 57.3 65.5 106 665 +1960 11 12 0 19 PATTY 64.6 322.7 30 16 +1958 3 11 6 8 WILLIAM 16.1 145.5 63 571 +1978 4 2 12 28 GORDON 42.6 174.1 150 498 +1989 1 16 0 15 FLORENCE 39.9 59.8 96 56 +1992 5 4 12 9 KIRK 15.8 117.1 42 155 +1989 11 4 6 5 ALBERTO 9.2 207.5 21 646 +1955 8 16 18 3 KIRK 14.1 193.4 124 14 +1989 9 12 12 3 HELENE 47.7 155.8 71 790 +1992 10 25 18 1 JOYCE 9.1 291.5 137 721 +1957 1 18 12 28 ERNESTO 58.6 136.1 93 18 +1978 3 3 0 19 WILLIAM 45.8 68.4 50 580 +1961 11 3 6 19 LESLIE 27.0 195.1 132 50 +1950 11 1 0 15 CHRIS 17.1 327.4 21 677 +1979 9 24 18 16 FLORENCE 41.8 180.0 37 692 +1967 6 28 0 22 NADINE 21.0 171.1 62 325 +1966 5 15 18 17 PATTY 63.9 147.0 11 646 +2000 12 25 18 1 BERYL 50.4 184.9 35 498 +1962 4 24 18 27 PATTY 63.0 105.7 108 701 +1986 11 2 6 11 KIRK 67.1 239.0 53 764 +1982 6 10 18 1 DEBBY 9.4 12.8 139 408 +1955 4 28 12 26 VALERIE 28.8 54.9 44 44 +1954 12 24 12 7 PATTY 59.0 159.8 127 89 +1951 2 2 6 14 JOYCE 46.2 7.2 122 884 +1962 2 20 18 24 WILLIAM 40.7 323.9 156 768 +2001 12 10 6 28 RAFAEL 37.6 242.5 56 635 +1954 2 7 0 22 ERNESTO 63.9 277.3 58 840 +1971 11 19 18 22 CHRIS 67.9 17.8 35 448 +1989 9 8 18 9 PATTY 56.7 123.9 60 673 +1966 2 12 18 13 PATTY 68.7 299.5 47 792 +1997 2 18 0 19 LESLIE 13.3 332.4 163 290 +1950 7 28 12 8 ALBERTO 66.4 158.0 81 173 +1967 8 16 18 2 OSCAR 62.0 267.5 23 769 +1957 11 13 12 7 PATTY 63.3 37.3 71 533 +1953 6 23 18 21 MICHAEL 63.0 177.7 158 394 +1974 8 16 0 5 GORDON 39.1 259.0 59 808 +1995 11 1 18 3 MICHAEL 32.3 234.5 135 620 +2002 2 21 6 22 FLORENCE 30.3 155.1 77 680 +2003 9 1 6 7 GORDON 46.6 202.4 102 746 +1992 12 16 6 14 DEBBY 53.5 204.0 120 690 +1996 11 9 6 18 ALBERTO 33.6 82.8 46 382 +2003 7 23 0 25 JOYCE 56.3 330.6 115 569 +1972 4 3 18 18 ISAAC 66.7 343.8 124 345 +1964 7 26 6 12 DEBBY 57.7 339.3 85 593 +1951 2 7 0 12 JOYCE 53.4 0.6 164 827 +1970 10 15 0 28 KIRK 45.3 337.8 96 876 +1975 9 12 18 3 PATTY 15.2 340.5 88 507 +1967 4 18 6 12 KIRK 22.6 71.1 136 802 +1982 11 7 18 10 NADINE 59.0 137.7 125 734 +1962 1 1 6 8 JOYCE 62.4 43.3 162 741 +1973 12 6 12 19 SANDY 66.5 55.7 33 346 +1980 7 11 6 14 RAFAEL 22.7 189.5 68 720 +1999 2 22 12 24 SANDY 67.8 109.3 30 237 +1969 11 22 0 25 WILLIAM 17.8 104.5 116 676 +1979 3 12 18 10 OSCAR 69.3 297.3 13 896 +1994 9 20 18 6 HELENE 35.8 329.4 74 383 +1992 5 6 0 2 JOYCE 34.7 77.0 59 559 +1968 2 14 18 18 WILLIAM 63.0 38.7 18 75 +1994 3 16 18 12 ERNESTO 52.2 309.0 37 45 +1962 6 25 18 9 MICHAEL 44.8 157.3 23 541 +1956 3 16 0 26 PATTY 28.1 225.0 158 830 +1987 9 20 0 2 LESLIE 46.4 153.9 128 237 +1980 9 20 0 26 PATTY 69.8 35.1 119 889 +1985 8 28 18 15 TONY 61.0 32.0 11 418 +1992 4 21 6 18 ISAAC 68.2 324.8 148 379 +1958 8 27 12 20 FLORENCE 10.9 184.3 159 580 +1969 4 15 0 20 HELENE 21.9 64.1 56 341 +2004 11 4 6 25 CHRIS 35.6 290.8 70 559 +1953 6 16 18 8 MICHAEL 11.9 279.3 58 312 +1961 1 21 18 7 RAFAEL 55.3 89.9 38 7 +1985 9 19 12 20 FLORENCE 64.5 196.8 98 148 +2002 9 3 18 19 SANDY 25.9 207.7 44 208 +1971 2 19 18 2 TONY 69.5 27.8 138 780 +1970 11 10 0 19 OSCAR 24.7 305.6 103 887 +1988 8 14 6 15 GORDON 34.5 14.5 34 423 +1950 4 7 12 28 NADINE 66.4 72.4 106 143 +1965 12 8 6 26 JOYCE 67.4 52.6 77 300 +1985 8 24 12 3 FLORENCE 49.0 268.7 129 779 +1972 12 15 12 27 KIRK 17.1 190.2 10 578 +1986 10 8 12 28 ALBERTO 33.8 48.7 130 390 +1961 11 5 12 7 MICHAEL 37.5 346.7 116 274 +1961 1 6 12 18 OSCAR 64.5 127.2 94 363 +2000 10 23 0 4 JOYCE 11.2 109.3 70 703 +1952 5 4 18 17 BERYL 17.2 302.5 132 847 +1974 1 21 6 20 DEBBY 46.1 54.8 128 103 +1972 10 21 12 8 SANDY 49.8 134.5 87 440 +1955 5 23 6 1 JOYCE 64.8 208.7 54 621 +1951 7 21 0 25 ISAAC 57.6 49.0 125 756 +1960 11 28 18 12 PATTY 26.1 167.0 49 182 +1967 2 12 18 18 SANDY 56.2 296.7 157 45 +1957 1 7 6 13 CHRIS 52.8 14.6 79 496 +1966 4 24 0 27 MICHAEL 37.8 112.0 52 522 +1955 4 4 0 18 BERYL 60.9 298.1 48 733 +1989 10 6 12 14 MICHAEL 34.3 26.1 148 166 +1997 6 22 6 4 HELENE 51.0 171.9 97 124 +1978 12 27 18 12 ALBERTO 47.2 258.2 53 540 +1993 11 4 6 16 FLORENCE 33.8 102.9 66 391 +1971 6 7 18 21 TONY 43.4 208.2 20 503 +1988 6 9 6 19 FLORENCE 28.9 319.2 56 449 +1995 6 14 0 10 ISAAC 12.6 217.5 18 761 +1988 8 8 12 21 WILLIAM 33.4 96.5 161 85 +2001 2 22 12 2 MICHAEL 50.2 215.2 29 633 +1952 1 15 6 7 ERNESTO 38.7 274.1 98 307 +1978 8 7 6 13 GORDON 46.6 213.6 121 768 +1968 10 10 6 3 OSCAR 49.0 75.2 147 825 +1996 6 6 12 7 KIRK 8.4 24.9 144 406 +1982 1 27 0 20 SANDY 42.7 330.1 101 180 +1965 4 23 18 25 DEBBY 50.9 338.8 37 693 +1954 3 3 12 18 NADINE 13.9 160.9 80 119 +1961 4 28 12 14 GORDON 12.8 170.3 123 608 +1991 6 21 6 4 SANDY 63.3 228.6 27 29 +1978 11 5 0 2 ISAAC 49.7 235.2 49 686 +1983 8 1 0 5 TONY 49.8 40.5 137 225 +1968 4 10 12 9 ISAAC 22.4 255.1 125 483 +1991 1 21 0 20 ISAAC 43.9 121.9 101 32 +1951 10 8 12 11 FLORENCE 65.3 98.2 160 660 +1996 8 13 6 16 KIRK 42.1 154.9 112 437 +1963 5 2 0 3 FLORENCE 39.4 54.9 93 52 +1997 8 21 0 9 MICHAEL 57.8 328.4 64 269 +1978 9 16 0 2 RAFAEL 66.6 13.0 138 539 +1977 12 18 12 24 WILLIAM 47.5 304.3 164 92 +1981 9 9 0 22 LESLIE 19.3 357.6 16 42 +1990 3 1 12 10 SANDY 33.6 67.6 83 20 +1994 6 21 18 9 LESLIE 8.7 42.3 94 662 +1988 5 27 6 22 TONY 54.9 193.8 24 554 +1971 11 9 18 9 PATTY 28.1 91.1 68 789 +1999 3 12 0 19 ERNESTO 54.0 294.4 24 139 +1987 5 3 0 20 GORDON 42.4 163.3 30 161 +1989 2 5 18 18 PATTY 68.3 225.8 24 80 +1974 5 16 12 5 PATTY 38.1 125.5 41 431 +1955 11 25 6 9 JOYCE 50.8 308.8 132 675 +1996 2 5 0 5 ALBERTO 26.8 292.9 126 66 +1986 2 27 12 27 NADINE 30.6 119.8 157 296 +1992 3 11 6 7 SANDY 9.6 185.6 41 894 +1961 5 4 6 8 PATTY 54.5 72.0 21 790 +2001 2 13 18 15 ERNESTO 19.9 327.0 154 412 +1968 1 25 18 22 ALBERTO 67.7 93.2 80 693 +1993 7 12 12 13 PATTY 37.4 200.1 52 186 +1963 3 9 12 4 CHRIS 43.8 245.3 130 704 +1955 10 14 6 26 NADINE 69.9 138.0 29 35 +1966 7 28 0 4 VALERIE 27.4 214.7 114 611 +1956 12 1 0 14 VALERIE 59.2 249.3 35 210 +1963 5 7 6 10 GORDON 49.0 288.5 85 601 +1950 8 21 6 11 HELENE 67.7 142.2 76 438 +1996 2 24 18 28 GORDON 32.0 212.0 145 506 +1962 4 24 12 27 HELENE 30.6 39.1 96 593 +1987 1 10 12 6 VALERIE 12.9 22.9 40 533 +1980 12 16 6 28 CHRIS 14.8 1.6 20 279 +1973 5 19 6 1 CHRIS 24.3 309.9 95 368 +1962 8 16 18 7 BERYL 30.3 111.5 20 888 +1993 7 15 0 9 HELENE 14.2 223.1 121 303 +1960 12 13 18 4 JOYCE 33.5 255.7 81 846 +1999 8 17 12 12 RAFAEL 20.5 354.1 122 391 +1979 10 26 12 4 BERYL 26.2 192.1 150 147 +1975 12 16 6 16 NADINE 25.9 240.1 33 529 +1996 1 24 12 17 ERNESTO 48.5 329.2 40 546 +1976 9 23 6 19 HELENE 42.3 195.1 38 532 +1976 2 1 0 6 GORDON 45.9 260.3 29 715 +1992 10 4 12 21 WILLIAM 8.1 183.3 151 355 +1987 11 24 12 7 FLORENCE 24.9 180.2 152 619 +1995 8 5 0 9 ISAAC 29.4 336.1 104 212 +1983 3 18 6 22 WILLIAM 13.0 166.7 54 138 +2004 8 24 18 12 NADINE 19.6 353.3 139 487 +1992 10 28 12 4 GORDON 41.9 30.7 92 535 +1951 7 22 18 23 OSCAR 27.3 135.3 107 776 +1989 3 26 18 9 ERNESTO 57.4 248.8 75 879 +1955 5 4 6 17 ISAAC 33.2 64.0 67 480 +1997 12 25 6 12 NADINE 48.2 314.8 26 882 +1997 7 2 12 21 ERNESTO 21.0 276.7 64 246 +1976 5 25 18 11 ALBERTO 57.5 278.0 31 636 +1972 3 9 12 18 ALBERTO 69.5 136.7 85 63 +1951 1 7 6 2 HELENE 33.2 322.5 160 525 +1990 10 4 18 6 NADINE 22.3 275.8 31 51 +1955 8 16 12 14 DEBBY 25.4 78.1 56 551 +1963 10 15 0 26 MICHAEL 9.9 250.2 65 829 +1987 7 7 6 11 LESLIE 47.8 301.8 54 778 +2002 7 23 18 14 VALERIE 13.7 44.9 86 483 +1974 1 20 0 13 DEBBY 45.2 57.4 81 829 +1994 11 16 18 15 ERNESTO 66.3 354.3 138 419 +1953 9 27 12 6 MICHAEL 65.4 139.6 89 382 +1972 4 23 6 21 KIRK 17.0 41.5 85 373 +1976 7 9 0 14 RAFAEL 20.4 132.8 57 231 +1953 6 21 6 14 JOYCE 50.6 211.3 60 209 +1955 1 12 6 27 ALBERTO 50.0 292.3 23 620 +1989 2 10 18 5 VALERIE 19.2 354.8 51 855 +1973 6 8 12 4 FLORENCE 16.5 334.8 30 390 +1994 10 20 12 17 WILLIAM 60.5 151.0 103 798 +1986 3 11 18 10 TONY 35.8 243.6 72 44 +1959 5 18 6 21 PATTY 20.2 184.0 52 522 +1996 6 11 18 18 WILLIAM 7.9 96.5 84 377 +1989 12 4 6 18 CHRIS 12.5 76.1 21 124 +1954 5 25 6 8 KIRK 69.4 61.3 36 88 +1974 9 23 18 5 VALERIE 31.1 129.3 58 748 +1974 7 19 18 26 KIRK 22.2 293.0 155 142 +1953 5 3 6 6 ERNESTO 63.7 285.9 44 562 +1978 10 11 12 5 FLORENCE 66.6 168.1 90 827 +1966 2 8 12 17 GORDON 60.3 236.9 135 682 +2000 1 12 0 5 FLORENCE 50.6 206.9 23 137 +1955 10 9 18 11 GORDON 53.8 230.9 60 821 +1982 4 12 18 14 BERYL 55.0 212.4 48 43 +1965 8 12 0 21 LESLIE 48.8 206.4 117 824 +1974 1 7 6 15 ERNESTO 61.9 71.4 68 890 +1954 11 20 12 12 FLORENCE 34.7 79.5 110 192 +1977 6 10 0 20 VALERIE 20.0 9.0 129 737 +1977 9 15 6 10 SANDY 20.6 266.5 99 21 +1973 9 9 12 1 RAFAEL 51.1 20.3 70 791 +1986 3 8 0 13 RAFAEL 65.7 157.6 150 158 +2002 10 28 6 4 NADINE 52.2 156.4 159 582 +1971 11 13 12 26 ALBERTO 11.1 135.1 140 64 +1963 6 25 18 18 ALBERTO 16.2 245.1 45 778 +1977 6 5 12 12 ERNESTO 41.1 204.8 37 184 +1991 7 4 12 12 VALERIE 16.4 239.3 77 106 +1988 12 28 18 14 HELENE 30.2 111.8 150 490 +1976 9 1 6 10 SANDY 15.9 258.5 64 413 +1984 1 20 6 15 KIRK 13.5 208.9 109 341 +1962 1 15 0 16 GORDON 22.1 71.0 42 76 +1969 6 13 6 11 MICHAEL 38.8 100.6 90 756 +1996 9 8 18 16 CHRIS 64.0 274.8 41 881 +1998 9 16 0 28 RAFAEL 42.6 8.9 73 606 +1977 3 13 0 25 TONY 9.7 254.8 93 132 +1967 4 6 0 16 ERNESTO 12.9 75.7 145 334 +1999 1 26 0 25 BERYL 13.7 154.5 105 122 +1997 12 10 0 20 SANDY 61.9 47.0 50 886 +2003 8 16 12 14 ISAAC 60.6 294.4 36 216 +1965 9 16 6 24 RAFAEL 25.3 154.5 29 743 +1988 8 9 0 25 VALERIE 31.5 131.9 105 338 +1973 8 13 6 10 VALERIE 16.7 238.0 48 490 +1995 1 14 18 22 DEBBY 22.7 227.5 126 763 +1957 6 11 12 4 JOYCE 66.7 337.8 141 612 +1982 9 5 6 14 KIRK 37.7 332.9 146 261 +1981 10 24 18 17 ISAAC 58.4 245.0 116 511 +1956 10 17 6 27 SANDY 64.4 285.7 131 12 +1980 7 13 12 19 DEBBY 39.3 339.9 130 777 +1993 6 8 6 11 ISAAC 43.5 226.4 100 142 +1985 11 16 6 4 VALERIE 17.0 239.2 13 162 +1951 5 14 18 16 CHRIS 52.3 100.9 106 534 +1967 3 27 12 3 DEBBY 50.6 56.7 158 828 +1969 1 26 0 3 JOYCE 32.1 220.0 36 381 +1973 1 3 18 20 TONY 64.6 186.3 27 156 +1959 10 21 18 25 ISAAC 45.2 254.8 84 217 +1983 5 2 18 13 HELENE 23.5 63.7 161 148 +1988 5 7 0 13 GORDON 69.7 282.3 66 780 +1985 2 19 12 18 SANDY 27.2 218.8 131 624 +1983 8 12 12 19 ISAAC 11.3 102.5 122 511 +1997 6 23 0 3 OSCAR 33.0 45.3 42 786 +1968 8 19 18 16 SANDY 7.8 260.2 148 54 +1985 3 16 0 17 RAFAEL 48.4 93.4 161 88 +1978 3 19 12 14 KIRK 53.0 105.6 113 12 +1977 8 2 0 12 SANDY 14.3 291.6 19 303 +1966 12 5 18 21 OSCAR 56.9 131.3 106 840 +1957 5 21 0 15 ALBERTO 47.1 305.5 105 18 +1968 5 15 12 3 PATTY 53.5 292.2 94 555 +1992 10 1 12 15 TONY 18.8 251.0 78 262 +1996 11 17 0 1 JOYCE 22.3 299.6 49 49 +1984 12 21 12 26 MICHAEL 9.4 4.1 75 771 +1962 5 25 12 7 MICHAEL 55.8 162.3 21 96 +1988 8 28 12 17 HELENE 57.6 34.7 47 577 +2002 9 11 18 19 TONY 59.5 321.1 139 47 +1982 3 16 6 8 OSCAR 41.8 29.7 156 651 +1987 2 20 0 18 FLORENCE 44.5 97.5 108 719 +1976 3 20 6 2 WILLIAM 44.0 196.7 120 735 +1962 5 23 18 9 PATTY 66.3 335.4 18 578 +1988 12 19 0 12 SANDY 34.2 187.6 101 372 +1986 3 15 6 15 DEBBY 56.3 97.8 86 261 +1959 6 27 0 19 GORDON 47.6 262.4 77 881 +1969 7 5 6 22 NADINE 36.1 287.0 112 738 +1998 5 14 18 16 CHRIS 19.9 236.6 102 195 +1952 1 25 18 5 LESLIE 45.2 78.2 84 714 +1976 1 25 12 25 ERNESTO 13.1 78.1 63 843 +1952 2 26 6 20 ISAAC 42.4 31.6 128 143 +1990 10 13 18 7 JOYCE 39.2 253.2 159 323 +1979 7 25 12 12 LESLIE 29.2 130.6 13 645 +1968 10 7 0 14 KIRK 63.6 202.1 81 86 +1990 2 3 6 16 FLORENCE 56.4 73.6 17 887 +1980 1 4 0 11 NADINE 33.0 171.4 129 250 +1993 3 20 18 19 FLORENCE 44.7 4.0 57 320 +1991 3 22 0 24 HELENE 21.3 221.8 133 8 +1967 4 24 18 28 DEBBY 11.0 279.5 122 451 +1980 3 5 0 2 CHRIS 64.0 70.4 99 460 +1984 6 26 0 28 LESLIE 19.5 250.7 130 417 +1955 10 20 0 19 RAFAEL 27.5 38.6 154 843 +1967 6 22 12 20 KIRK 28.9 76.3 36 131 +1989 6 17 0 26 KIRK 31.2 346.1 16 684 +1976 12 26 12 27 HELENE 27.8 218.4 164 755 +1983 5 10 18 12 OSCAR 11.2 36.2 12 125 +1998 9 9 12 9 ISAAC 26.8 315.1 118 397 +1994 6 6 18 18 ALBERTO 34.4 15.5 159 695 +1963 11 22 12 19 HELENE 42.8 245.7 19 432 +1952 7 6 12 6 LESLIE 39.6 288.2 97 279 +1966 6 12 0 2 NADINE 43.1 356.0 17 367 +1981 1 14 18 12 ERNESTO 39.8 119.8 117 884 +1989 10 1 18 28 ERNESTO 45.6 183.4 96 254 +1997 5 26 0 1 HELENE 54.6 310.3 151 369 +1994 12 9 0 21 FLORENCE 66.7 193.4 93 534 +1995 11 15 12 12 HELENE 22.3 249.1 96 511 +1964 7 17 6 8 BERYL 65.8 155.1 19 899 +2001 7 13 0 4 WILLIAM 65.6 92.3 95 473 +1995 7 17 18 8 SANDY 38.8 325.7 105 512 +1961 11 18 12 2 ALBERTO 15.8 320.7 144 839 +1988 10 5 6 16 OSCAR 8.8 167.0 34 628 +1952 7 8 18 6 FLORENCE 64.1 357.0 151 61 +1954 9 12 18 28 VALERIE 31.2 129.8 143 166 +1974 3 7 12 2 FLORENCE 23.8 147.4 90 168 +1985 8 9 0 13 FLORENCE 30.5 77.2 153 18 +1988 9 1 18 24 LESLIE 26.9 108.7 121 123 +1994 5 28 18 11 BERYL 33.3 43.2 161 1 +2003 5 1 6 15 HELENE 12.2 348.2 63 645 +1971 11 14 0 26 TONY 41.8 16.6 155 846 +1954 6 9 12 9 NADINE 64.0 314.0 84 625 +1957 11 15 18 10 CHRIS 11.2 59.8 85 786 +1985 9 21 12 28 FLORENCE 43.8 173.0 152 119 +1962 10 15 6 5 PATTY 14.1 306.4 156 401 +1989 7 22 6 1 MICHAEL 30.5 246.9 63 86 +1982 1 3 6 1 HELENE 25.9 344.7 149 639 +1950 12 17 0 1 ERNESTO 49.3 301.7 50 320 +1970 5 23 18 5 ISAAC 28.2 49.5 54 24 +1996 5 8 18 27 ALBERTO 12.2 102.1 60 642 +1964 9 27 0 4 VALERIE 47.4 244.8 118 888 +1982 2 12 6 2 OSCAR 26.1 310.5 10 181 +2001 9 20 12 12 ALBERTO 14.5 162.8 92 1 +1981 12 2 12 15 ALBERTO 56.7 79.1 96 254 +1951 2 21 18 18 GORDON 9.1 178.0 73 805 +1970 4 5 18 27 LESLIE 59.8 339.6 163 789 +1993 11 18 18 17 OSCAR 30.3 225.2 110 396 +2002 5 10 12 8 ISAAC 10.6 44.9 39 182 +1956 6 20 18 23 BERYL 25.5 171.7 88 42 +1953 11 8 12 21 OSCAR 35.4 343.6 126 398 +1956 8 28 6 20 ERNESTO 23.6 113.6 119 335 +2001 12 9 18 18 ERNESTO 55.3 257.0 25 898 +2002 11 16 12 4 TONY 37.6 158.9 62 137 +1969 9 13 6 20 ISAAC 33.9 68.6 141 63 +1996 7 5 18 4 MICHAEL 48.9 310.6 34 329 +1977 11 26 12 7 SANDY 55.3 351.2 12 562 +1973 6 25 18 15 RAFAEL 55.2 309.1 76 506 +2003 5 6 12 2 KIRK 39.9 340.5 117 610 +1981 3 14 12 2 SANDY 62.7 155.2 28 850 +2004 2 26 6 1 CHRIS 45.5 75.0 22 9 +1957 2 27 18 11 MICHAEL 32.7 119.3 135 100 +1985 2 27 0 7 FLORENCE 10.7 251.9 144 678 +2003 3 19 0 20 MICHAEL 43.6 19.2 124 192 +1956 3 7 18 18 NADINE 7.8 266.2 39 194 +1995 10 16 18 22 ERNESTO 57.1 109.1 61 274 +1974 11 1 6 22 ERNESTO 58.9 212.0 152 49 +1952 12 12 6 2 RAFAEL 20.9 264.2 89 45 +2000 9 8 18 12 JOYCE 66.7 277.1 70 668 +1957 10 15 6 17 LESLIE 24.3 32.5 24 263 +1987 4 15 0 27 NADINE 68.5 264.9 87 592 +1987 3 20 0 4 GORDON 23.6 207.0 37 68 +1982 10 26 18 20 OSCAR 17.6 133.4 73 801 +1984 3 28 6 20 DEBBY 19.2 138.2 58 561 +1951 3 15 18 14 MICHAEL 56.0 134.4 138 117 +1976 5 21 6 10 BERYL 21.8 50.5 64 377 +1978 6 7 6 18 DEBBY 11.1 27.1 86 466 +1969 1 1 0 10 GORDON 16.5 191.3 86 4 +1963 7 19 0 1 HELENE 68.7 172.9 124 800 +1990 3 14 0 20 BERYL 60.7 303.5 57 546 +1966 11 14 0 4 FLORENCE 59.3 178.3 164 766 +2000 5 18 12 25 ALBERTO 19.1 218.4 43 85 +1976 2 3 12 4 TONY 29.5 301.6 49 481 +2004 9 27 0 7 ISAAC 56.4 260.9 111 232 +1989 7 8 18 26 ERNESTO 31.7 239.6 141 831 +1994 5 4 0 14 HELENE 60.3 228.3 159 719 +1996 8 22 0 24 ERNESTO 56.3 161.1 112 716 +2000 4 26 12 11 NADINE 9.7 195.4 124 230 +1963 6 3 6 26 MICHAEL 68.6 79.3 84 84 +1966 3 20 6 28 SANDY 12.1 185.7 46 823 +1981 11 20 6 12 FLORENCE 35.2 101.4 86 702 +1961 11 8 0 24 SANDY 47.9 225.4 146 506 +1986 2 1 18 13 VALERIE 24.4 229.4 76 610 +1964 5 7 18 19 ISAAC 16.8 341.2 87 453 +1999 3 12 6 3 RAFAEL 39.8 265.2 29 127 +1970 2 8 0 4 BERYL 36.5 31.9 22 47 +1959 10 17 6 19 RAFAEL 50.8 157.8 34 663 +1978 6 21 18 3 NADINE 9.2 191.2 119 472 +1970 7 1 0 12 PATTY 29.9 352.0 31 747 +1965 12 4 18 25 FLORENCE 25.0 272.2 157 768 +1961 12 20 18 22 JOYCE 17.3 298.5 132 121 +2004 8 13 0 28 FLORENCE 31.9 67.4 84 224 +1993 3 1 6 18 VALERIE 14.3 267.7 13 397 +1952 10 26 12 17 WILLIAM 36.4 155.7 162 868 +1994 5 2 18 23 OSCAR 8.7 330.8 161 685 +1986 8 13 18 13 VALERIE 50.0 25.2 48 583 +1969 10 8 6 25 PATTY 53.8 242.6 116 114 +1956 6 1 6 2 GORDON 37.4 252.6 17 50 +1990 10 19 18 24 ERNESTO 69.3 125.9 40 337 +1992 3 13 12 19 WILLIAM 67.9 286.1 114 841 +2000 3 27 6 5 NADINE 50.4 52.2 108 743 +1988 10 19 12 24 TONY 26.9 293.0 24 495 +1972 9 23 18 21 MICHAEL 42.9 86.9 96 12 +1986 4 21 12 17 TONY 8.7 134.0 123 212 +1990 3 2 12 19 ISAAC 45.3 5.5 110 277 +1997 5 26 6 16 RAFAEL 27.9 52.0 109 781 +1950 5 16 6 8 FLORENCE 35.9 289.3 32 43 +1961 9 24 0 9 GORDON 17.1 17.8 155 822 +2001 1 12 6 27 VALERIE 46.2 170.4 88 441 +2004 9 18 6 4 KIRK 12.6 57.9 14 825 +1953 2 11 12 9 MICHAEL 21.0 82.8 52 408 +1986 10 19 18 16 GORDON 11.6 82.9 89 29 +1993 6 17 18 6 LESLIE 9.3 112.5 27 640 +1981 3 13 12 18 WILLIAM 55.9 173.6 152 134 +1958 2 3 6 8 PATTY 11.7 78.4 22 170 +1982 1 11 6 11 CHRIS 49.9 217.4 67 541 +1993 7 12 0 12 CHRIS 37.6 34.0 136 481 +2003 2 19 0 20 ALBERTO 13.3 254.9 16 541 +1951 5 20 6 19 OSCAR 18.5 62.7 144 13 +1987 10 8 6 26 DEBBY 33.8 350.9 16 394 +1961 4 28 12 8 DEBBY 10.0 307.3 11 231 +1990 9 3 6 26 ISAAC 27.4 357.3 131 67 +2000 8 13 6 17 GORDON 25.3 220.5 149 267 +1992 2 13 6 24 LESLIE 36.4 136.2 24 788 +1958 6 1 6 20 SANDY 40.2 126.5 93 833 +2001 4 10 6 14 ERNESTO 55.2 104.9 141 83 +1971 5 22 12 28 PATTY 28.7 190.5 34 1 +1953 12 12 18 12 CHRIS 39.4 145.9 21 839 +1950 11 17 0 4 ERNESTO 16.8 227.1 14 26 +1959 7 2 0 21 PATTY 44.4 10.5 49 703 +1989 12 25 0 10 VALERIE 50.1 155.6 20 194 +1955 11 18 12 12 WILLIAM 24.0 200.4 79 420 +1959 7 21 12 27 LESLIE 62.9 262.6 51 503 +1965 5 2 18 12 KIRK 33.7 290.0 56 440 +1951 3 15 0 13 NADINE 26.8 90.5 50 172 +1993 12 6 12 26 CHRIS 22.9 18.0 88 746 +1964 2 17 12 24 LESLIE 37.2 219.9 44 83 +1950 5 23 12 25 DEBBY 29.8 284.8 83 435 +1977 8 12 6 11 RAFAEL 26.0 26.8 34 699 +1961 2 20 6 7 CHRIS 22.4 26.1 32 135 +1990 9 12 18 17 ALBERTO 54.1 152.5 15 482 +1950 1 23 6 21 VALERIE 34.1 209.1 60 699 +1966 12 2 0 7 KIRK 46.3 200.8 42 659 +1984 6 3 0 16 NADINE 50.9 132.4 53 600 +1959 3 15 6 6 NADINE 35.0 341.1 104 39 +1950 4 15 18 27 RAFAEL 26.6 281.1 57 286 +1992 5 8 0 5 FLORENCE 49.2 22.3 162 36 +1981 8 28 6 14 HELENE 64.6 147.8 112 25 +1978 11 15 18 8 ISAAC 48.4 24.6 158 624 +1966 12 2 0 7 ALBERTO 24.0 309.9 88 140 +1976 6 18 12 21 JOYCE 23.1 10.2 44 763 +1988 3 3 6 28 ALBERTO 34.8 249.6 108 427 +1990 5 7 12 25 JOYCE 52.7 352.7 28 44 +1998 9 17 12 6 MICHAEL 8.7 222.6 151 93 +1982 3 3 18 23 FLORENCE 16.9 81.5 100 203 +1957 7 19 0 19 HELENE 60.0 271.9 118 16 +1982 10 12 18 14 BERYL 37.8 286.7 103 736 +1998 2 15 0 23 DEBBY 57.7 326.1 68 503 +1952 7 20 18 7 ALBERTO 69.9 233.9 46 241 +2000 5 17 12 12 ISAAC 57.9 32.9 128 434 +1972 1 1 18 7 MICHAEL 60.2 332.3 86 254 +1959 7 27 18 22 FLORENCE 40.9 55.7 24 336 +1977 10 5 0 23 VALERIE 25.9 28.6 77 40 +1990 6 27 0 20 SANDY 56.3 58.6 47 208 +1983 12 22 12 17 ALBERTO 64.9 289.2 126 643 +1953 7 5 12 1 GORDON 22.9 207.8 160 804 +1976 3 24 0 20 ISAAC 64.7 34.6 36 444 +1960 6 17 12 21 MICHAEL 45.8 303.0 122 322 +1989 7 19 12 8 KIRK 58.8 209.9 162 712 +1971 9 13 18 2 CHRIS 26.0 289.2 95 729 +1968 12 3 18 10 KIRK 57.7 234.2 114 255 +2003 8 8 0 6 JOYCE 63.8 36.3 110 210 +1974 4 5 6 25 FLORENCE 63.9 102.1 59 405 +1984 3 25 18 16 SANDY 32.8 236.2 63 601 +1952 7 18 12 11 DEBBY 23.1 202.5 116 824 +1998 3 2 12 8 HELENE 11.7 23.0 163 339 +1976 12 26 6 17 ERNESTO 38.4 257.4 78 80 +1951 5 7 12 17 VALERIE 21.2 102.1 20 107 +1964 10 26 12 10 OSCAR 55.5 77.2 88 93 +1960 7 20 0 28 GORDON 55.0 81.5 18 140 +1964 6 11 6 18 MICHAEL 21.5 114.9 103 13 +1959 8 4 0 24 ERNESTO 42.4 199.2 21 356 +1960 8 10 0 3 ERNESTO 18.2 126.6 45 257 +1982 5 1 12 18 RAFAEL 45.7 23.5 27 756 +1990 2 23 0 15 ALBERTO 53.8 46.0 49 238 +1964 12 22 6 18 ISAAC 63.6 200.0 32 594 +1968 7 7 18 18 CHRIS 40.1 347.4 41 546 +1979 5 2 18 15 ALBERTO 23.4 263.9 116 564 +2002 12 1 0 12 KIRK 35.9 216.8 96 597 +1957 12 2 6 22 LESLIE 69.9 302.0 59 452 +1999 5 4 18 11 BERYL 31.7 39.2 146 70 +1993 8 19 12 20 PATTY 33.2 69.0 49 866 +1962 7 3 0 3 BERYL 33.2 231.6 38 583 +1974 7 13 12 23 TONY 43.2 342.7 164 139 +1987 11 21 6 28 DEBBY 20.9 182.4 140 747 +1981 3 19 18 15 GORDON 24.7 151.2 159 441 +1980 12 27 18 26 MICHAEL 50.2 240.2 112 249 +1992 12 16 6 5 PATTY 39.0 327.9 128 93 +2000 6 27 12 28 DEBBY 42.8 148.0 126 626 +1956 2 17 0 16 JOYCE 55.4 118.3 49 771 +1984 11 23 6 26 TONY 40.6 3.9 77 885 +1962 10 9 18 8 RAFAEL 35.0 145.2 82 427 +1964 4 12 18 25 GORDON 43.7 246.6 147 845 +1988 4 10 12 13 MICHAEL 16.5 248.8 110 591 +1962 9 21 6 7 ERNESTO 19.2 83.2 148 446 +1955 6 21 6 6 ALBERTO 45.6 221.8 34 504 +1954 5 12 18 9 TONY 54.5 345.7 154 861 +1992 9 1 12 25 BERYL 68.3 11.0 155 701 +1989 10 24 6 6 NADINE 27.4 189.6 110 897 +2004 10 16 12 25 WILLIAM 19.2 0.0 100 870 +1986 5 5 6 26 HELENE 64.9 139.0 14 249 +1988 9 22 18 10 DEBBY 15.9 2.2 81 304 +1989 2 18 0 1 LESLIE 8.1 190.0 57 662 +1989 5 13 12 11 MICHAEL 52.7 116.9 39 229 +1994 8 26 0 11 BERYL 65.2 252.3 124 776 +1969 3 7 0 9 ISAAC 43.5 223.5 62 383 +1992 8 16 18 17 WILLIAM 64.3 43.2 42 839 +1965 6 11 12 9 HELENE 54.2 42.4 129 788 +1959 3 11 12 6 OSCAR 38.9 144.7 97 234 +1954 10 19 18 16 NADINE 16.1 328.1 52 188 +1961 12 24 18 9 KIRK 54.8 106.0 76 271 +1980 2 5 12 19 PATTY 45.0 247.4 42 488 +1962 3 23 6 8 ALBERTO 33.1 239.6 97 57 +1975 6 27 12 12 FLORENCE 17.4 142.2 109 714 +2002 11 15 12 10 DEBBY 26.9 85.9 144 748 +1980 1 4 0 13 PATTY 7.9 147.5 56 388 +1969 9 9 12 2 ISAAC 29.4 130.6 162 417 +1950 9 12 12 22 WILLIAM 10.0 122.7 122 879 +1951 10 4 18 22 MICHAEL 66.6 294.1 12 375 +1976 10 7 12 12 FLORENCE 34.9 318.9 51 286 +1956 10 3 0 7 RAFAEL 14.0 8.2 137 857 +1969 1 25 18 17 HELENE 42.1 164.7 10 526 +1990 5 23 6 1 VALERIE 16.5 142.8 62 792 +1957 3 14 6 6 MICHAEL 29.5 255.6 74 573 +1996 4 16 18 1 OSCAR 24.2 118.5 81 172 +1997 3 23 18 1 BERYL 25.0 60.7 89 103 +1962 3 18 12 26 VALERIE 28.4 112.2 123 130 +1983 8 25 12 4 RAFAEL 67.9 355.1 52 690 +1997 12 4 18 4 NADINE 27.0 64.6 136 278 +2002 4 13 0 6 TONY 63.4 27.0 90 877 +1972 12 15 18 8 CHRIS 28.8 111.0 83 600 +1979 10 22 0 6 PATTY 11.0 165.8 84 857 +2003 8 1 18 23 PATTY 18.1 281.7 144 461 +1975 2 10 0 27 TONY 44.7 241.6 63 315 +1950 1 16 6 19 BERYL 58.6 227.9 132 577 +2002 8 19 12 26 HELENE 53.1 259.9 45 582 +1975 7 25 12 25 VALERIE 31.8 86.2 139 808 +1989 11 1 12 6 NADINE 33.4 283.6 40 599 +1964 1 17 18 1 ERNESTO 41.6 329.5 47 613 +1968 5 16 6 1 CHRIS 40.9 216.1 74 313 +1954 7 24 12 25 ISAAC 53.6 32.4 60 740 +1992 6 26 6 15 ISAAC 47.1 70.8 80 876 +2000 2 9 0 24 ERNESTO 53.5 274.5 63 296 +1969 12 17 6 17 ERNESTO 64.2 216.6 35 691 +1987 12 26 0 17 FLORENCE 28.2 354.3 135 761 +1964 6 14 12 15 JOYCE 7.1 146.9 94 239 +1956 11 20 12 10 ISAAC 58.4 318.5 136 213 +1956 2 18 6 14 KIRK 42.1 256.8 44 665 +1998 10 5 12 16 GORDON 44.6 37.3 98 680 +1984 2 1 12 1 ALBERTO 14.9 108.3 109 75 +2002 7 20 18 23 NADINE 65.0 195.4 73 586 +1972 6 21 6 14 GORDON 36.9 53.5 93 693 +1955 9 13 0 1 PATTY 28.6 197.0 134 273 +1980 2 24 0 27 PATTY 56.1 326.6 146 366 +2001 7 26 0 28 WILLIAM 21.5 344.3 86 878 +2001 11 20 12 23 HELENE 66.6 268.9 58 274 +1951 4 27 18 19 ERNESTO 64.1 175.4 67 573 +1958 4 16 12 19 FLORENCE 62.1 36.2 118 626 +1966 3 6 18 2 ALBERTO 44.0 188.5 161 474 +1996 1 24 6 11 BERYL 17.6 49.0 124 2 +1973 1 20 12 8 BERYL 17.9 59.9 126 190 +1957 7 27 0 23 NADINE 61.6 45.2 40 127 +1964 9 22 18 14 WILLIAM 52.8 45.8 61 0 +1961 4 27 6 18 TONY 66.9 50.9 118 474 +1974 12 21 6 6 ALBERTO 8.1 257.5 82 456 +2004 6 17 6 4 OSCAR 13.6 240.2 92 111 +1965 4 8 12 18 ISAAC 8.1 69.4 38 448 +1958 7 21 12 21 NADINE 69.3 11.8 30 136 +1975 11 16 0 7 ISAAC 39.8 354.3 43 52 +1997 12 6 12 17 MICHAEL 38.6 205.1 77 878 +1985 10 19 12 14 SANDY 48.9 187.8 122 871 +1980 8 24 18 15 LESLIE 27.0 185.1 35 794 +1965 6 7 0 20 BERYL 16.7 127.0 87 723 +1983 3 7 6 16 ISAAC 66.3 254.7 111 48 +1965 3 15 18 3 LESLIE 26.7 277.7 159 366 +1994 5 12 12 13 PATTY 37.0 241.9 137 344 +1980 10 5 0 26 ALBERTO 64.0 1.6 153 875 +1997 9 13 18 25 ERNESTO 67.7 64.3 129 858 +1983 4 27 6 3 HELENE 69.4 171.6 90 294 +1988 10 27 18 4 ALBERTO 67.6 153.4 61 393 +1963 9 14 18 2 RAFAEL 12.4 68.9 106 877 +1951 4 6 0 10 ISAAC 43.7 262.0 106 666 +1964 5 27 18 8 PATTY 9.8 12.0 109 685 +2002 10 23 0 18 JOYCE 58.4 258.7 111 301 +1973 5 21 0 14 KIRK 33.6 207.3 31 146 +1951 8 4 6 11 KIRK 15.0 63.9 27 692 +1976 11 6 12 6 BERYL 67.6 144.2 103 163 +1969 9 11 6 26 NADINE 48.2 188.5 10 370 +1971 11 3 6 13 HELENE 32.0 256.8 81 297 +1964 8 8 12 8 RAFAEL 29.4 50.2 75 223 +1967 12 18 0 15 ISAAC 54.5 79.1 142 419 +1957 7 2 18 6 HELENE 16.8 52.5 71 860 +1967 2 11 18 22 WILLIAM 10.6 191.5 50 187 +1994 8 24 18 24 TONY 35.8 275.7 135 608 +1956 2 26 0 6 OSCAR 20.2 57.7 97 712 +1997 5 18 6 9 CHRIS 63.7 345.9 154 128 +1984 6 14 18 25 KIRK 54.7 147.3 90 484 +1969 6 15 6 12 MICHAEL 7.5 275.7 10 829 +1969 6 26 6 14 NADINE 22.2 97.5 27 93 +1988 9 10 0 14 WILLIAM 45.8 258.7 162 726 +1997 4 2 0 22 WILLIAM 8.0 141.1 55 108 +1994 10 2 18 13 SANDY 37.5 97.1 154 444 +1971 6 1 6 8 ERNESTO 51.8 285.9 28 398 +1960 4 9 6 14 LESLIE 62.5 67.1 28 141 +1973 7 7 0 28 ERNESTO 23.1 334.6 122 803 +1955 7 3 0 15 NADINE 50.5 312.3 111 441 +1996 1 10 0 4 CHRIS 39.4 100.1 44 525 +1976 11 4 12 12 ALBERTO 68.1 48.9 34 239 +1952 11 1 0 7 WILLIAM 24.7 250.2 33 353 +1965 12 23 0 28 MICHAEL 23.1 205.5 32 156 +1972 7 24 0 15 HELENE 58.8 237.5 155 291 +1988 10 2 0 9 PATTY 55.5 260.3 63 497 +1963 10 4 0 19 ALBERTO 10.0 315.1 73 895 +1957 3 10 0 19 GORDON 49.0 231.1 156 553 +1977 7 21 12 27 SANDY 51.4 258.9 91 634 +1980 7 10 18 7 BERYL 29.3 350.2 149 276 +1967 10 21 6 19 KIRK 19.9 25.6 63 558 +1985 2 16 12 1 HELENE 10.4 177.2 125 493 +1978 4 19 0 7 ALBERTO 62.4 17.1 75 207 +1992 12 3 6 15 RAFAEL 17.0 134.4 102 292 +1969 11 11 18 5 VALERIE 18.4 266.7 145 304 +1953 7 28 12 20 BERYL 31.7 298.8 21 20 +1973 7 1 18 26 RAFAEL 51.5 312.2 32 584 +1974 1 23 12 15 TONY 68.5 275.3 122 56 +1965 5 14 12 9 ERNESTO 38.0 156.2 59 835 +2000 2 13 6 15 LESLIE 14.0 181.0 10 366 +1973 7 22 0 17 NADINE 29.2 327.7 69 583 +1988 6 19 0 21 WILLIAM 65.1 125.2 50 91 +1992 4 10 18 15 PATTY 10.9 46.1 100 96 +1984 8 17 12 22 VALERIE 15.0 155.6 104 585 +1979 5 22 12 24 KIRK 64.5 220.3 94 64 +1989 9 15 0 28 BERYL 48.5 191.9 113 128 +1991 2 5 6 18 BERYL 69.9 251.2 20 896 +1987 2 4 6 9 OSCAR 58.1 34.3 22 133 +1963 2 19 12 19 LESLIE 42.3 165.1 79 164 +2000 8 6 6 4 PATTY 47.2 196.8 73 222 +1953 5 11 6 1 ISAAC 52.6 49.8 49 583 +2003 2 27 12 1 NADINE 56.6 144.5 102 441 +1993 9 8 12 19 LESLIE 32.6 266.7 23 238 +1974 2 23 18 27 NADINE 63.6 25.4 15 569 +1988 6 3 12 10 CHRIS 23.7 341.7 40 555 +1980 5 18 18 16 LESLIE 9.5 47.0 127 200 +2003 9 14 0 7 OSCAR 19.7 355.0 75 419 +1966 5 18 18 20 LESLIE 11.4 73.6 152 549 +1998 9 12 6 16 TONY 20.8 37.0 161 483 +1972 2 2 12 19 VALERIE 47.4 199.3 53 586 +1954 10 14 6 13 NADINE 59.6 342.0 139 467 +1958 3 27 12 13 PATTY 26.6 177.9 50 841 +1997 4 2 0 27 PATTY 33.7 28.7 96 217 +1996 9 10 0 2 HELENE 30.5 326.3 144 392 +1975 12 1 18 3 HELENE 52.2 314.7 32 840 +1998 11 18 12 3 TONY 35.5 22.5 142 90 +1968 3 22 12 13 DEBBY 12.3 17.2 144 363 +1991 1 24 18 27 KIRK 49.7 192.0 120 184 +2000 10 3 6 10 RAFAEL 14.0 341.8 150 343 +1993 12 8 0 27 LESLIE 64.3 138.0 85 269 +2004 8 14 18 13 BERYL 32.2 208.7 48 53 +1956 3 9 12 11 LESLIE 23.0 125.1 49 3 +1986 3 16 6 2 TONY 30.5 96.3 29 858 +1978 7 20 0 25 CHRIS 11.0 305.9 115 306 +1991 3 8 6 11 NADINE 66.9 163.7 126 468 +1957 2 4 6 2 WILLIAM 36.4 326.8 126 220 +2002 9 16 18 23 GORDON 54.6 308.8 72 592 +1962 1 25 6 13 SANDY 13.2 184.0 62 125 +1950 8 27 18 18 WILLIAM 15.4 246.0 66 819 +1958 9 14 0 6 DEBBY 13.6 355.5 30 177 +1959 3 21 18 9 JOYCE 46.2 19.4 78 516 +1954 7 1 18 10 TONY 60.3 262.1 101 129 +1978 9 1 12 18 HELENE 23.2 355.3 61 419 +1951 1 20 12 15 MICHAEL 44.4 0.8 94 225 +1960 12 14 18 4 ERNESTO 61.4 107.9 117 519 +1952 6 17 6 13 ALBERTO 67.3 40.1 55 622 +1981 4 21 12 19 DEBBY 7.5 52.9 48 480 +1961 5 17 18 2 KIRK 52.5 96.2 60 273 +1954 2 9 12 26 KIRK 55.4 139.4 160 763 +1982 11 5 12 8 ALBERTO 46.0 151.6 101 716 +1962 4 16 12 2 RAFAEL 64.9 143.0 45 135 +2001 8 27 18 25 BERYL 23.1 22.7 47 149 +1978 8 7 12 3 WILLIAM 12.3 328.5 56 315 +1961 3 28 18 7 DEBBY 50.0 203.8 140 142 +1953 12 13 0 15 HELENE 62.6 299.2 152 771 +1992 2 1 6 28 WILLIAM 9.5 159.8 12 712 +1965 4 13 18 1 TONY 56.9 337.1 115 101 +1957 8 7 0 12 SANDY 29.2 327.1 136 108 +1968 8 22 0 16 KIRK 60.0 147.5 82 385 +1959 11 3 6 17 KIRK 40.0 19.6 98 394 +1961 1 13 12 25 TONY 14.6 166.2 12 526 +2004 5 8 18 10 MICHAEL 44.8 239.3 10 435 +1979 3 12 12 12 DEBBY 9.5 108.1 80 349 +1952 6 25 6 11 MICHAEL 36.8 39.9 112 610 +1979 9 10 12 28 FLORENCE 42.3 68.1 146 279 +1993 9 4 12 25 ALBERTO 20.2 141.6 39 257 +1994 1 6 6 16 TONY 29.4 260.5 130 273 +1994 4 1 12 18 FLORENCE 12.4 223.2 99 189 +1951 8 10 6 28 OSCAR 69.5 240.3 47 274 +1978 4 2 18 17 PATTY 44.4 202.1 120 307 +1960 4 10 12 12 LESLIE 48.2 197.7 19 72 +1992 1 20 6 1 LESLIE 23.7 301.9 102 143 +1988 5 7 0 10 GORDON 50.0 18.0 58 18 +1996 4 1 0 21 VALERIE 52.3 25.3 154 459 +1961 11 25 18 11 OSCAR 55.2 42.5 48 105 +2000 6 24 0 11 TONY 30.9 271.5 43 179 +1959 7 26 0 20 FLORENCE 68.1 189.3 142 690 +1980 1 4 18 14 LESLIE 31.8 121.4 103 559 +1976 6 9 18 28 TONY 65.4 16.8 124 483 +2003 4 23 0 15 JOYCE 28.8 283.6 125 14 +1995 7 18 18 11 GORDON 11.0 196.2 156 44 +1962 4 21 6 16 SANDY 11.9 178.8 57 311 +2003 2 13 6 27 CHRIS 37.7 91.4 113 106 +2001 6 5 0 1 NADINE 30.8 83.7 91 476 +2001 9 1 12 12 GORDON 67.1 1.9 52 51 +1983 1 8 18 17 DEBBY 59.2 300.9 114 668 +1951 6 15 6 23 GORDON 45.4 307.7 36 268 +1991 9 21 12 3 LESLIE 59.3 112.2 24 857 +1988 7 22 18 12 SANDY 36.4 250.2 25 78 +1963 6 24 0 8 GORDON 7.1 96.1 76 505 +2004 12 8 6 17 KIRK 14.7 130.8 89 881 +1996 12 21 12 26 NADINE 26.6 86.9 68 685 +1996 10 22 0 2 RAFAEL 38.2 126.8 113 647 +1978 3 28 12 3 NADINE 46.7 192.5 147 195 +1963 1 21 18 21 ERNESTO 59.2 127.6 148 247 +1953 5 10 12 10 FLORENCE 48.9 274.1 86 682 +1980 5 8 6 1 ERNESTO 21.7 221.9 107 448 +1961 5 3 12 6 LESLIE 49.6 238.8 138 79 +1968 10 1 0 23 TONY 32.4 250.5 69 273 +1962 3 7 6 24 NADINE 37.1 217.4 89 881 +1969 9 7 18 20 RAFAEL 27.8 314.1 31 418 +1972 12 28 18 18 DEBBY 19.5 213.2 94 786 +1997 10 3 6 25 TONY 69.4 257.5 66 248 +1972 3 28 18 6 SANDY 43.9 222.1 79 872 +1975 5 8 6 20 ERNESTO 21.8 166.5 72 604 +1981 2 23 0 23 FLORENCE 22.1 41.4 49 586 +1979 3 3 6 28 ALBERTO 29.7 151.3 120 296 +1986 6 18 18 24 SANDY 54.0 201.8 89 803 +1950 7 21 6 22 OSCAR 61.1 70.1 28 627 +1959 8 20 0 21 TONY 31.8 350.8 63 13 +2000 12 20 18 22 ERNESTO 52.8 219.7 55 784 +1980 7 2 0 13 GORDON 44.9 122.3 70 578 +2000 9 11 12 20 MICHAEL 23.6 76.6 157 401 +1988 8 19 12 11 HELENE 11.6 154.1 87 592 +1953 8 16 6 27 FLORENCE 37.6 59.3 144 406 +2004 4 20 12 22 TONY 66.2 56.1 79 6 +1959 1 10 18 25 BERYL 53.0 200.5 61 110 +1994 4 21 0 5 TONY 61.0 29.4 19 336 +1963 2 1 12 24 TONY 36.0 132.3 142 638 +1958 2 26 18 25 ALBERTO 59.4 243.3 137 404 +1992 12 16 0 9 DEBBY 25.3 119.2 146 444 +1972 2 24 0 16 NADINE 57.9 312.5 151 730 +1972 3 24 0 20 CHRIS 64.0 273.8 31 708 +1974 1 3 6 25 VALERIE 36.0 346.6 18 815 +1995 2 6 0 22 OSCAR 8.5 308.8 71 215 +1993 11 12 12 10 GORDON 56.9 231.6 85 75 +2004 12 14 18 20 LESLIE 62.6 311.3 133 302 +1951 4 17 6 6 KIRK 23.0 24.2 78 505 +1993 1 15 6 9 RAFAEL 40.0 164.9 90 442 +2001 7 24 12 18 RAFAEL 14.3 271.8 96 193 +1958 6 2 0 17 HELENE 42.4 307.7 37 215 +1973 2 4 6 23 FLORENCE 64.5 195.8 114 590 +1954 11 14 12 16 FLORENCE 29.7 185.2 98 539 +1992 1 27 12 28 ERNESTO 54.5 351.0 77 454 +2002 8 15 6 27 ERNESTO 20.4 335.7 147 300 +1988 2 4 12 14 KIRK 54.5 309.5 40 401 +1998 5 24 18 6 GORDON 21.9 347.1 113 385 +1953 10 2 0 7 CHRIS 31.7 83.8 127 883 +1969 2 16 18 14 PATTY 52.4 316.1 79 239 +1953 5 9 12 17 NADINE 29.9 51.7 53 830 +1988 5 20 12 21 CHRIS 42.0 316.6 55 869 +1957 6 14 0 1 RAFAEL 15.9 248.7 99 156 +1977 1 4 6 18 SANDY 21.8 353.4 11 80 +1997 5 23 6 18 HELENE 55.2 80.9 124 376 +1985 12 1 0 12 PATTY 9.4 276.6 129 555 +1976 9 25 12 28 HELENE 32.8 62.9 110 229 +1985 9 26 18 5 NADINE 37.1 316.8 100 351 +1960 1 9 18 5 DEBBY 17.9 62.8 118 61 +1973 1 18 18 17 CHRIS 39.2 18.6 115 504 +1980 4 20 18 20 BERYL 38.5 189.2 39 883 +1978 12 27 12 15 PATTY 45.9 277.8 102 460 +1962 6 25 0 28 GORDON 27.4 343.7 56 410 +1973 2 28 12 21 SANDY 30.8 265.8 11 69 +1977 11 19 12 28 ALBERTO 32.7 133.0 119 91 +1978 2 23 0 22 LESLIE 54.7 73.3 126 101 +1962 4 10 6 19 OSCAR 61.9 25.0 60 34 +1971 9 3 18 19 ERNESTO 43.3 94.2 27 593 +1969 8 2 6 19 OSCAR 33.6 150.5 16 560 +1982 9 5 18 26 OSCAR 7.6 69.0 106 670 +1989 10 15 18 11 FLORENCE 37.0 346.1 12 764 +1980 7 1 12 23 MICHAEL 19.3 331.1 66 864 +1996 1 25 6 6 CHRIS 12.4 114.8 135 710 +1974 5 14 12 7 FLORENCE 49.9 313.5 82 590 +1980 12 10 0 27 PATTY 16.1 280.7 53 769 +1971 2 10 18 4 ERNESTO 20.2 310.8 18 588 +1986 8 3 18 26 KIRK 67.0 229.8 54 753 +1978 3 3 12 3 DEBBY 38.3 181.4 37 768 +1994 8 12 0 11 FLORENCE 51.0 45.1 90 281 +1954 12 12 6 2 RAFAEL 22.8 86.9 126 535 +1979 1 17 12 14 PATTY 25.9 230.4 143 190 +1990 8 5 12 14 WILLIAM 10.8 355.6 29 426 +1953 12 23 6 24 RAFAEL 58.6 44.4 108 609 +1977 5 13 12 15 ALBERTO 27.9 190.9 69 779 +1997 11 16 0 25 OSCAR 44.2 196.3 130 150 +1950 7 19 0 7 MICHAEL 45.7 128.1 110 647 +1953 1 25 12 6 MICHAEL 23.6 91.7 128 5 +1966 5 23 18 14 MICHAEL 15.0 124.3 107 741 +1962 5 6 18 6 DEBBY 54.6 104.2 139 730 +1951 3 12 12 24 OSCAR 61.2 269.3 46 494 +1975 5 21 6 24 CHRIS 47.7 244.0 26 152 +1950 9 27 6 23 FLORENCE 44.3 95.6 38 821 +2002 11 26 18 22 ERNESTO 10.7 48.1 46 275 +1967 1 22 0 13 BERYL 41.8 246.4 59 549 +1988 1 6 0 15 RAFAEL 61.9 96.0 139 151 +1951 7 24 12 14 ERNESTO 32.8 190.3 46 320 +1995 1 18 18 12 CHRIS 44.5 131.4 141 569 +1980 8 15 12 2 DEBBY 67.7 153.4 155 654 +1960 11 6 6 21 GORDON 42.9 200.8 33 683 +1956 8 14 0 9 HELENE 31.3 132.8 117 807 +1965 6 23 6 2 WILLIAM 9.1 241.0 137 161 +1956 3 7 0 18 HELENE 68.1 45.5 114 501 +1975 6 11 18 10 FLORENCE 57.8 201.4 70 884 +1955 6 20 12 11 MICHAEL 39.0 249.2 89 294 +1960 8 25 0 1 WILLIAM 64.6 132.2 85 50 +1968 5 28 6 6 PATTY 46.7 96.2 37 400 +2002 2 20 6 28 FLORENCE 54.9 111.2 118 801 +1951 10 16 18 18 KIRK 61.4 208.9 27 841 +1956 4 9 0 5 ERNESTO 55.1 74.8 35 409 +1986 9 12 12 5 GORDON 38.8 297.3 155 265 +1997 5 10 18 21 CHRIS 57.7 248.8 48 882 +1955 7 20 18 27 NADINE 19.6 17.0 34 289 +1994 3 1 12 22 MICHAEL 13.0 330.2 15 611 +1974 8 2 0 21 CHRIS 13.2 207.2 81 391 +1966 6 12 18 2 ERNESTO 23.0 159.8 158 852 +1966 2 25 6 14 MICHAEL 18.1 72.7 74 670 +1976 12 1 12 18 ALBERTO 57.7 284.4 100 532 +1969 12 17 0 17 ISAAC 68.5 43.2 89 772 +1977 2 4 12 23 SANDY 67.3 218.2 36 711 +2004 7 28 0 16 FLORENCE 39.3 156.0 148 373 +1996 6 1 6 27 GORDON 65.2 274.5 58 80 +1977 9 16 12 5 JOYCE 35.5 85.1 120 146 +2004 11 27 0 27 VALERIE 13.9 285.7 78 635 +1995 3 1 6 23 FLORENCE 47.5 174.1 100 388 +1982 8 27 6 13 ALBERTO 9.6 352.3 88 604 +1997 2 25 12 21 PATTY 11.1 40.0 26 122 +1967 8 1 6 17 SANDY 46.0 318.1 45 492 +1988 3 24 18 17 MICHAEL 50.5 190.5 137 532 +1958 9 17 6 26 LESLIE 22.6 182.8 140 892 +1958 7 16 12 24 ERNESTO 24.9 303.5 63 569 +1999 12 3 6 13 FLORENCE 19.2 277.6 52 282 +1992 12 18 18 8 PATTY 49.2 288.2 124 107 +1981 10 20 12 4 MICHAEL 45.1 164.5 115 426 +1993 4 25 18 22 RAFAEL 29.4 83.5 32 210 +1957 8 27 6 10 BERYL 35.9 101.0 44 477 +1982 8 26 12 1 ISAAC 41.5 40.5 81 211 +1971 4 21 0 23 NADINE 68.9 162.5 68 780 +1971 2 15 18 19 ALBERTO 68.1 78.6 148 495 +1967 5 10 12 22 BERYL 21.2 116.5 80 28 +1999 1 20 18 13 VALERIE 52.2 265.5 124 471 +1993 3 17 18 24 TONY 57.6 78.9 89 413 +1982 8 24 6 5 WILLIAM 53.7 343.0 29 889 +1976 1 20 0 27 RAFAEL 62.5 89.4 144 854 +1957 6 15 0 10 LESLIE 27.4 206.7 140 23 +1998 11 21 12 19 BERYL 43.4 32.5 109 864 +1968 11 1 18 23 WILLIAM 11.5 30.0 35 254 +1989 8 27 6 4 GORDON 7.3 98.8 105 313 +2003 10 20 0 1 NADINE 34.9 99.3 77 433 +1974 10 8 0 9 DEBBY 9.5 286.2 23 227 +1955 2 20 18 3 WILLIAM 38.1 311.5 64 339 +1984 3 5 0 8 OSCAR 49.8 326.9 74 133 +1950 11 1 18 20 JOYCE 33.9 213.9 92 125 +1991 9 27 18 5 BERYL 43.1 276.9 136 418 +1965 12 14 12 22 VALERIE 54.3 236.2 142 555 +1981 7 13 0 10 LESLIE 41.3 206.7 117 348 +1995 3 10 18 22 WILLIAM 37.4 202.7 96 739 +1996 6 8 0 26 ISAAC 53.8 67.5 64 542 +1952 2 20 0 18 HELENE 68.1 334.0 23 899 +1993 7 3 18 1 DEBBY 56.7 98.2 97 349 +1973 9 13 18 28 FLORENCE 57.5 334.5 13 489 +1992 8 24 12 18 WILLIAM 30.3 310.9 105 823 +1954 6 24 18 12 CHRIS 18.0 46.1 24 63 +1997 2 27 0 27 LESLIE 32.6 267.4 20 566 +1992 4 18 0 15 TONY 7.5 318.4 76 467 +1992 7 17 12 24 GORDON 38.8 322.9 161 444 +1990 5 20 18 10 PATTY 30.1 86.1 132 574 +1973 3 5 6 9 RAFAEL 39.0 97.1 55 390 +1957 8 26 0 21 ERNESTO 38.4 86.6 145 438 +1961 3 22 6 18 NADINE 11.6 176.7 29 34 +1999 10 6 18 7 CHRIS 44.6 256.4 118 46 +1992 6 9 18 6 PATTY 64.6 120.5 145 549 +1959 7 28 0 19 NADINE 21.0 308.7 150 679 +1983 4 24 6 3 NADINE 9.0 313.8 151 258 +1968 1 17 12 3 JOYCE 63.9 203.5 130 579 +1958 12 3 12 28 ERNESTO 19.0 229.6 90 57 +2003 4 15 12 17 ALBERTO 51.4 78.4 90 88 +1968 8 6 0 14 DEBBY 17.3 172.4 143 123 +1950 12 18 6 1 NADINE 12.3 25.0 107 248 +1964 12 27 0 12 HELENE 30.0 333.4 48 867 +1969 8 23 0 6 ISAAC 69.9 2.3 57 460 +1973 4 11 12 13 FLORENCE 44.9 43.9 105 352 +1988 1 20 6 23 TONY 9.1 315.1 158 214 +2000 2 22 18 7 TONY 19.3 39.2 65 721 +1951 11 25 0 16 JOYCE 30.5 140.3 145 183 +2002 2 10 18 17 SANDY 54.2 197.0 101 811 +1958 8 20 0 18 TONY 58.6 168.7 71 884 +1978 3 4 18 15 TONY 13.0 112.4 81 610 +1985 9 3 12 15 CHRIS 59.5 87.3 14 547 +1959 1 25 0 4 MICHAEL 15.9 330.2 152 638 +1951 7 8 12 6 PATTY 58.2 53.3 26 545 +1954 8 20 12 25 KIRK 39.7 60.1 143 317 +1958 5 4 18 4 SANDY 30.9 186.2 39 103 +1951 3 8 12 2 OSCAR 22.1 234.1 62 645 +1958 11 2 18 8 PATTY 10.6 15.6 92 368 +1991 4 1 6 16 OSCAR 52.3 105.3 22 204 +1986 5 7 6 20 HELENE 60.6 111.4 159 704 +1970 5 16 6 25 NADINE 9.0 289.1 67 299 +2004 11 18 18 11 ALBERTO 33.2 80.0 69 741 +1979 12 6 12 28 GORDON 58.1 129.4 138 157 +1981 12 14 6 14 GORDON 57.9 113.2 77 52 +1997 8 4 12 2 SANDY 65.9 218.2 132 799 +1965 3 19 6 25 SANDY 18.9 86.5 64 775 +2001 1 17 6 7 PATTY 55.2 112.1 26 619 +1983 12 10 6 28 KIRK 16.6 104.1 124 16 +1984 1 11 0 9 ERNESTO 20.9 175.7 37 319 +1972 3 26 12 15 KIRK 35.4 262.4 62 171 +1995 5 20 0 16 BERYL 30.0 354.8 36 800 +1991 10 1 6 2 PATTY 31.9 278.0 44 222 +1956 9 10 0 16 LESLIE 27.6 70.2 13 345 +1983 10 3 18 28 BERYL 18.4 291.2 100 355 +1950 11 13 6 21 HELENE 34.9 257.0 155 179 +1993 2 12 6 13 NADINE 46.0 302.7 148 96 +1992 6 8 12 2 KIRK 24.7 108.1 18 539 +1997 12 4 0 28 HELENE 49.0 237.4 148 449 +1973 6 25 12 11 NADINE 58.7 0.2 160 57 +1973 12 25 0 10 TONY 38.0 43.4 117 559 +1987 9 18 6 19 LESLIE 65.9 337.1 162 788 +1993 9 28 6 22 FLORENCE 25.5 85.8 146 346 +1971 12 8 18 11 FLORENCE 12.6 185.8 76 348 +2002 10 5 6 1 RAFAEL 57.3 70.7 124 603 +1983 3 20 18 15 JOYCE 48.1 186.2 89 849 +1999 9 24 18 8 MICHAEL 15.9 341.3 130 184 +1959 2 15 18 22 NADINE 45.7 336.0 83 258 +1957 4 13 18 17 HELENE 9.9 159.1 112 169 +1973 12 17 0 3 PATTY 16.9 25.1 73 766 +1989 6 3 0 3 RAFAEL 23.1 210.5 22 288 +1993 7 10 6 26 PATTY 54.6 88.0 163 320 +1969 8 12 18 26 LESLIE 11.2 327.3 149 245 +1997 12 17 0 22 LESLIE 35.2 132.5 108 245 +1975 1 16 6 15 NADINE 8.0 27.3 56 602 +1964 5 21 6 21 TONY 13.1 43.9 54 862 +1973 9 12 12 14 ISAAC 69.1 193.6 51 643 +2001 12 20 12 20 HELENE 61.8 187.7 108 887 +2002 7 4 18 19 HELENE 66.1 189.9 151 136 +1998 3 26 0 27 VALERIE 29.8 26.9 66 326 +1984 4 21 6 21 NADINE 17.7 234.4 106 256 +1951 1 13 6 26 DEBBY 11.2 139.9 20 191 +1972 6 19 6 13 BERYL 17.8 189.1 119 771 +1955 8 19 0 11 ALBERTO 68.2 304.5 68 653 +1993 12 3 0 3 ERNESTO 20.3 158.7 84 324 +1976 5 28 6 8 ERNESTO 54.7 270.1 117 144 +1970 12 10 18 12 PATTY 29.4 41.4 152 551 +1989 10 5 6 8 PATTY 33.5 356.3 120 813 +1956 8 4 6 11 WILLIAM 40.3 315.3 98 552 +1970 10 8 18 28 LESLIE 60.0 157.4 109 626 +1971 9 12 12 18 RAFAEL 60.8 69.7 108 231 +1996 1 26 12 8 MICHAEL 28.5 88.8 68 422 +1987 11 28 12 18 HELENE 59.9 174.5 10 539 +1964 11 17 6 22 FLORENCE 16.0 165.4 122 203 +1997 4 5 12 21 SANDY 15.4 46.2 55 483 +2001 6 1 12 13 ERNESTO 64.4 266.8 67 863 +1976 8 23 6 10 DEBBY 14.1 165.6 46 474 +1953 4 26 12 3 HELENE 27.1 294.9 149 377 +1968 12 7 0 10 LESLIE 26.8 294.1 120 873 +1969 5 23 6 25 ERNESTO 51.6 86.5 133 478 +1983 9 10 0 4 HELENE 26.0 159.7 111 130 +1990 1 18 0 15 WILLIAM 55.0 43.8 40 353 +2002 4 22 12 25 FLORENCE 17.5 340.8 28 839 +1991 3 13 0 22 CHRIS 62.6 244.9 131 176 +1958 4 19 18 28 NADINE 35.8 38.7 89 440 +1981 12 1 18 21 CHRIS 7.2 22.0 61 768 +1982 4 7 12 1 KIRK 26.3 316.1 24 45 +1985 3 23 12 10 OSCAR 69.3 231.1 133 392 +1973 10 17 18 21 JOYCE 10.7 178.1 42 404 +1956 2 11 0 15 LESLIE 65.6 120.3 131 415 +1956 10 7 18 10 KIRK 35.7 84.1 20 898 +1961 2 27 0 12 TONY 13.8 147.3 93 773 +1954 3 6 18 2 DEBBY 20.3 31.0 116 526 +1959 5 4 0 13 NADINE 59.9 73.2 60 476 +2000 5 14 6 19 KIRK 48.7 77.8 153 669 +1987 6 15 18 7 GORDON 64.5 70.9 76 852 +1960 11 9 18 28 ISAAC 65.1 218.8 143 102 +1960 5 14 6 16 TONY 16.0 238.9 67 12 +1993 7 22 0 12 DEBBY 43.5 246.7 140 831 +1999 4 9 0 1 GORDON 23.5 316.2 50 65 +1989 11 23 12 16 ISAAC 54.2 54.0 94 333 +1973 5 23 6 10 PATTY 8.0 272.4 144 582 +1978 5 5 0 25 KIRK 13.0 141.6 89 8 +1970 3 1 6 3 ALBERTO 20.2 57.0 146 781 +1982 7 4 12 27 OSCAR 35.9 209.2 32 338 +2003 8 24 6 8 ISAAC 23.1 202.0 59 59 +1987 12 28 12 5 ALBERTO 34.3 349.4 143 493 +1997 7 7 6 3 KIRK 26.6 147.6 70 898 +1967 9 17 6 7 CHRIS 19.2 353.8 98 796 +1962 6 5 0 12 VALERIE 39.7 149.3 97 692 +1995 4 11 18 2 BERYL 58.0 249.6 153 291 +1985 9 28 12 17 PATTY 65.4 301.4 15 725 +1958 1 21 18 2 PATTY 17.2 305.6 51 368 +1963 11 18 18 9 FLORENCE 23.6 208.9 64 477 +1983 4 12 0 2 PATTY 19.4 278.6 95 483 +1962 10 13 0 7 VALERIE 36.6 128.9 12 260 +1967 7 4 12 25 FLORENCE 31.3 233.7 63 829 +1965 1 5 12 2 DEBBY 31.4 225.3 49 121 +1955 11 14 18 4 BERYL 9.8 127.9 60 275 +1981 12 19 18 19 MICHAEL 56.2 113.9 20 6 +1968 6 9 6 11 PATTY 66.1 176.1 154 592 +2002 9 14 12 24 WILLIAM 41.6 225.3 41 575 +1981 6 6 18 10 ISAAC 37.0 232.2 154 196 +1988 7 7 6 10 NADINE 66.5 268.7 25 553 +1967 10 17 6 23 HELENE 46.4 143.2 54 832 +1959 2 1 0 25 GORDON 60.7 23.7 118 8 +2002 1 22 0 4 NADINE 40.2 20.1 108 280 +1951 6 13 12 4 VALERIE 69.9 271.1 11 49 +1951 4 3 12 11 WILLIAM 49.3 55.5 10 624 +1990 6 16 18 7 TONY 43.6 74.6 47 873 +1989 7 7 12 13 NADINE 49.3 131.9 117 397 +1984 9 14 0 17 ISAAC 62.2 119.7 147 176 +1972 5 6 12 6 HELENE 43.0 3.2 117 619 +1970 4 20 6 6 MICHAEL 53.2 64.2 151 340 +1963 5 14 12 16 ISAAC 60.0 24.7 22 627 +1979 5 22 18 19 SANDY 38.7 165.2 147 780 +1955 5 9 18 17 FLORENCE 23.0 334.6 85 252 +1998 2 4 6 5 KIRK 31.4 47.9 23 419 +1956 12 20 12 6 VALERIE 20.8 143.4 80 318 +1976 11 20 0 20 JOYCE 61.2 241.3 73 867 +1993 10 21 12 28 SANDY 61.7 36.6 146 890 +1999 11 3 18 6 VALERIE 58.2 343.0 161 307 +2001 9 26 6 17 GORDON 45.6 228.8 102 17 +1995 5 4 18 2 RAFAEL 68.4 170.8 55 133 +1964 9 27 18 1 ERNESTO 11.3 333.4 27 3 +1971 10 8 0 4 SANDY 59.8 310.5 157 823 +1962 6 11 18 21 CHRIS 7.3 52.9 25 733 +1981 11 1 0 27 LESLIE 24.5 202.2 22 877 +1953 2 11 18 23 ALBERTO 20.6 200.4 11 237 +1997 6 2 6 21 ALBERTO 34.9 242.3 164 842 +1963 3 27 0 26 VALERIE 52.5 52.1 124 754 +1951 8 8 18 16 KIRK 39.0 173.4 125 793 +1992 7 12 18 1 GORDON 66.6 258.9 96 469 +1990 10 16 18 26 ISAAC 25.4 183.7 123 718 +1973 1 22 0 19 FLORENCE 47.8 198.4 30 165 +1975 8 1 18 20 RAFAEL 18.4 20.0 37 705 +1974 3 2 12 11 ERNESTO 22.3 191.8 137 275 +1988 9 1 0 19 KIRK 20.0 180.2 47 112 +1976 6 11 6 26 ISAAC 41.5 266.2 158 273 +1992 4 12 12 6 ERNESTO 31.4 78.2 125 156 +1973 4 26 0 6 CHRIS 55.2 290.7 122 401 +1987 3 14 6 4 PATTY 60.9 28.1 54 305 +1991 5 8 0 27 BERYL 45.8 302.6 91 745 +2004 7 8 0 25 ISAAC 63.1 337.9 35 560 +2002 3 18 18 28 FLORENCE 13.3 180.7 77 131 +1964 3 6 6 13 OSCAR 49.3 55.9 129 677 +1965 12 13 18 3 ISAAC 58.8 288.0 72 293 +1975 7 28 6 23 ALBERTO 23.7 29.4 69 96 +1982 12 26 6 11 RAFAEL 46.1 7.3 13 31 +1997 11 14 12 15 NADINE 61.9 292.1 118 510 +1991 1 14 18 10 DEBBY 44.1 221.2 34 863 +1996 5 19 0 20 NADINE 44.6 289.0 148 869 +1993 9 5 12 8 BERYL 17.7 288.3 122 217 +1999 5 27 0 17 FLORENCE 58.3 263.6 27 352 +1990 7 4 6 20 CHRIS 56.5 343.8 132 764 +1990 9 11 0 3 VALERIE 36.8 108.0 109 189 +1959 5 9 12 2 TONY 15.4 135.6 159 688 +1976 1 19 18 21 OSCAR 27.1 212.8 110 220 +2004 3 6 12 8 ERNESTO 7.9 196.1 89 268 +1996 9 21 0 3 RAFAEL 20.7 114.6 78 882 +1971 1 3 18 7 DEBBY 17.8 179.6 152 8 +1980 3 1 12 26 SANDY 65.4 334.3 63 141 +1973 1 3 6 12 ERNESTO 65.6 306.8 29 48 +1982 3 17 6 24 ALBERTO 30.4 277.8 28 90 +1989 11 11 6 5 PATTY 47.0 197.9 119 94 +1980 2 26 6 23 KIRK 67.3 112.8 163 805 +1951 5 12 12 18 BERYL 12.0 47.0 29 327 +1980 1 12 6 26 ALBERTO 27.7 331.7 161 516 +1964 4 7 12 11 SANDY 36.6 350.8 160 364 +1976 12 25 6 15 HELENE 58.4 293.8 49 624 +1968 5 9 6 2 HELENE 36.9 327.8 117 715 +1992 4 27 0 27 NADINE 63.7 179.8 75 110 +1958 8 11 12 28 GORDON 30.4 104.8 97 617 +1996 11 16 6 11 WILLIAM 32.5 218.6 144 701 +1955 10 15 12 15 TONY 32.0 206.0 74 444 +2002 7 16 18 6 DEBBY 45.6 225.3 12 27 +1973 3 28 6 25 ERNESTO 59.0 35.1 126 323 +1999 7 1 18 6 GORDON 28.6 157.2 14 868 +1990 10 26 18 2 SANDY 47.6 219.8 101 477 +1985 5 26 18 6 WILLIAM 18.1 169.6 95 763 +1992 7 20 12 22 SANDY 7.6 244.6 96 109 +1978 10 18 18 13 DEBBY 15.3 145.8 134 372 +2004 5 28 12 20 PATTY 47.4 183.5 143 254 +1984 9 18 6 4 HELENE 14.7 336.0 50 397 +1961 11 28 12 17 NADINE 50.9 258.4 108 405 +1959 6 5 6 3 VALERIE 53.6 12.0 82 857 +1965 11 8 0 27 PATTY 29.0 47.4 103 164 +1981 6 18 0 8 ALBERTO 65.6 121.3 119 365 +1964 8 1 12 24 DEBBY 45.3 327.4 51 625 +1968 9 4 0 2 PATTY 69.9 178.2 54 159 +1966 3 19 12 26 ERNESTO 38.2 317.9 76 524 +1959 5 7 18 24 OSCAR 11.0 352.3 43 763 +2003 5 20 12 18 VALERIE 34.3 282.7 124 251 +1994 3 14 12 23 WILLIAM 54.3 257.5 17 120 +1961 4 13 0 12 JOYCE 7.5 352.9 104 810 +1957 2 3 12 26 FLORENCE 7.7 329.4 148 77 +1975 12 20 0 21 CHRIS 69.6 90.9 34 539 +2000 4 6 12 8 NADINE 31.0 234.3 63 859 +1975 11 19 18 13 RAFAEL 57.3 284.4 87 191 +1981 6 19 6 8 HELENE 63.4 266.0 159 884 +2002 9 7 6 8 MICHAEL 33.1 233.2 31 21 +2001 3 22 0 2 NADINE 45.7 215.9 159 386 +2002 2 28 0 4 NADINE 53.5 59.7 87 694 +1991 1 18 12 24 BERYL 43.0 129.3 116 26 +1977 10 2 18 20 BERYL 21.4 334.0 75 621 +2001 3 8 18 21 ERNESTO 35.2 167.6 37 502 +1998 9 25 12 19 NADINE 29.8 317.4 77 434 +1974 7 9 0 16 HELENE 30.3 148.2 162 489 +1984 4 20 12 14 BERYL 10.2 108.5 148 326 +1951 5 4 12 23 NADINE 41.0 26.6 91 329 +1983 11 5 0 24 HELENE 35.6 93.6 63 410 +1968 1 25 18 26 TONY 11.4 274.6 35 786 +2000 11 28 18 24 VALERIE 48.9 324.8 86 25 +1995 4 28 18 16 JOYCE 53.3 276.6 76 661 +1999 5 17 6 6 ISAAC 8.4 244.7 161 379 +1981 6 2 6 26 ALBERTO 63.5 46.0 98 755 +1968 12 3 12 25 KIRK 28.7 206.1 114 49 +1980 11 28 6 22 ALBERTO 63.4 137.4 116 82 +1999 10 2 6 12 ERNESTO 39.6 330.5 129 846 +1990 3 16 18 19 MICHAEL 47.8 108.6 138 750 +1989 10 3 12 24 RAFAEL 47.8 30.0 160 409 +1962 8 27 0 7 JOYCE 31.4 338.8 133 138 +1956 6 7 6 15 NADINE 58.6 268.5 124 828 +1986 3 10 18 2 ERNESTO 60.3 312.2 98 266 +1967 3 4 6 14 CHRIS 9.4 47.3 44 135 +2004 2 7 6 16 WILLIAM 41.6 18.7 116 175 +1966 10 27 18 17 VALERIE 16.5 256.1 144 793 +2000 7 27 6 1 GORDON 50.0 334.5 49 549 +1992 5 15 18 8 NADINE 22.7 252.9 54 688 +1968 5 6 12 21 JOYCE 39.3 248.8 64 618 +1969 10 9 6 24 ERNESTO 28.4 231.8 61 731 +1991 4 7 0 24 GORDON 47.1 352.1 115 69 +1995 7 18 12 5 OSCAR 62.1 136.7 142 316 +2000 11 6 18 4 PATTY 12.1 182.9 94 876 +1970 4 2 6 21 ISAAC 14.8 115.1 57 39 +1993 9 23 18 14 CHRIS 25.6 93.4 161 886 +1967 12 14 12 24 NADINE 28.4 153.3 51 827 +1955 5 5 0 13 BERYL 62.6 143.9 34 168 +1988 11 22 18 24 ISAAC 12.2 274.7 37 120 +1974 11 17 18 23 VALERIE 43.1 121.4 105 275 +1969 4 12 0 6 ISAAC 58.3 316.1 115 83 +1963 2 17 18 25 KIRK 39.8 204.2 131 460 +1997 10 20 6 25 GORDON 40.8 220.5 45 767 +2004 11 17 12 9 GORDON 20.9 106.7 79 418 +1979 3 11 0 7 DEBBY 25.5 200.0 160 767 +2000 4 5 0 8 JOYCE 8.2 323.6 103 597 +1996 6 9 12 21 LESLIE 51.0 146.6 19 62 +1963 4 4 0 24 DEBBY 46.9 302.2 87 875 +1991 5 1 18 9 ERNESTO 24.4 325.6 33 265 +1980 5 24 18 17 GORDON 12.2 276.1 65 773 +1971 5 23 6 8 GORDON 7.3 137.6 23 44 +1951 9 2 6 5 SANDY 57.8 51.7 54 877 +1958 4 19 12 21 ISAAC 34.9 39.7 155 86 +1973 8 9 18 17 ALBERTO 21.4 330.0 68 137 +1956 4 1 12 21 BERYL 23.5 68.1 93 702 +1969 6 28 18 15 ALBERTO 31.9 186.2 123 654 +1950 2 27 18 11 TONY 39.3 187.0 73 578 +1974 5 8 6 22 ISAAC 45.5 299.7 50 461 +1979 6 25 18 20 ISAAC 31.0 83.2 135 505 +1967 9 1 0 6 BERYL 35.1 329.7 80 626 +1996 3 4 12 26 ALBERTO 14.7 1.1 119 392 +1961 8 6 6 16 DEBBY 56.0 42.0 157 47 +1955 2 9 12 24 MICHAEL 21.2 98.6 123 881 +1953 2 1 6 6 VALERIE 23.8 215.8 94 424 +1992 4 11 0 24 ERNESTO 49.6 203.1 154 892 +1986 8 3 12 13 NADINE 13.7 284.7 26 313 +1968 3 17 18 21 BERYL 59.0 208.4 114 183 +1952 12 8 18 15 TONY 37.4 178.0 45 97 +1966 8 14 6 12 VALERIE 50.7 314.0 145 128 +1969 5 16 6 15 CHRIS 33.1 138.2 35 624 +1964 11 18 18 17 CHRIS 22.5 9.4 122 746 +1964 6 28 6 2 NADINE 7.5 306.5 45 74 +1955 4 12 12 12 PATTY 37.9 195.9 128 849 +1951 10 15 18 5 MICHAEL 26.3 72.2 129 543 +2003 9 25 18 19 HELENE 33.9 112.8 79 441 +1968 5 27 0 5 ALBERTO 47.8 48.8 15 672 +1993 9 22 12 25 JOYCE 35.7 288.4 125 358 +2004 6 25 12 27 JOYCE 20.2 63.5 84 185 +1996 4 6 0 12 KIRK 41.9 246.7 53 120 +1986 11 5 0 28 ERNESTO 11.4 190.5 119 514 +2000 3 12 12 20 NADINE 10.2 12.0 61 692 +2004 4 28 12 5 PATTY 56.4 354.8 52 1 +1977 1 10 6 20 WILLIAM 55.3 236.3 136 729 +1995 2 6 6 7 WILLIAM 52.6 312.6 15 104 +1991 5 26 12 27 TONY 9.3 251.4 14 246 +1962 6 6 18 9 ISAAC 69.0 182.9 105 762 +1955 12 10 12 9 KIRK 46.3 67.8 27 781 +1952 4 22 12 25 VALERIE 24.2 240.2 97 868 +1996 7 13 6 25 OSCAR 34.2 272.7 158 526 +1999 9 27 12 10 TONY 65.3 304.4 18 45 +1988 8 20 0 14 RAFAEL 8.6 103.3 104 75 +1979 7 7 6 12 FLORENCE 9.3 236.0 26 417 +1992 6 7 0 19 CHRIS 59.6 332.9 61 186 +1955 9 17 18 26 DEBBY 15.0 32.2 16 257 +2004 2 1 12 12 RAFAEL 22.2 164.9 155 708 +2000 5 8 18 21 VALERIE 37.2 119.2 135 360 +1963 8 21 0 1 TONY 27.3 356.6 103 211 +1963 12 19 0 26 WILLIAM 17.0 233.5 99 417 +1975 12 3 12 6 BERYL 35.1 351.4 56 897 +1977 1 4 6 18 OSCAR 65.3 315.4 74 696 +1980 10 20 12 27 WILLIAM 52.3 247.3 81 210 +1961 11 10 6 10 DEBBY 48.5 89.6 77 849 +1995 2 6 0 26 ALBERTO 45.8 87.5 81 589 +1980 1 3 18 19 GORDON 32.7 67.7 103 510 +1966 3 22 12 21 OSCAR 40.2 269.3 86 792 +1964 7 19 0 3 SANDY 42.3 59.1 94 370 +1968 11 9 18 18 OSCAR 17.3 142.7 138 842 +1987 5 8 6 9 PATTY 41.1 349.0 47 194 +1978 9 24 12 9 NADINE 44.8 209.9 42 430 +2001 5 10 18 12 KIRK 17.1 333.2 51 660 +1978 4 19 12 16 VALERIE 65.4 36.9 29 680 +2002 10 16 18 19 GORDON 43.0 349.6 137 320 +1968 4 18 6 1 FLORENCE 41.3 247.3 147 314 +1966 5 26 0 9 TONY 50.0 301.1 101 658 +1951 12 14 12 23 OSCAR 53.9 181.8 103 83 +1952 12 26 12 8 FLORENCE 26.9 342.4 60 826 +1973 1 25 18 21 SANDY 22.9 330.7 88 248 +1992 3 10 12 19 NADINE 37.0 204.1 22 637 +1959 6 1 18 4 ISAAC 34.8 208.3 99 37 +1995 5 23 12 20 JOYCE 47.1 176.4 137 522 +1991 3 16 6 3 BERYL 63.3 224.3 51 259 +1966 8 7 18 13 LESLIE 52.2 330.0 156 872 +1955 10 19 6 21 NADINE 68.1 239.7 59 331 +1967 11 27 12 2 LESLIE 10.7 279.2 158 467 +1961 9 5 12 4 LESLIE 40.2 27.2 151 264 +1961 5 8 0 20 CHRIS 69.0 97.3 159 747 +2003 10 16 0 15 SANDY 27.4 298.1 19 487 +2001 1 25 6 10 VALERIE 38.2 350.8 143 325 +1963 8 3 6 1 DEBBY 41.6 169.5 65 493 +1993 5 13 18 9 ERNESTO 19.9 263.8 18 660 +1964 10 21 12 2 SANDY 35.2 147.7 43 51 +1980 11 13 6 6 ALBERTO 27.0 243.4 161 865 +1959 3 4 0 13 JOYCE 46.0 196.2 88 61 +1996 2 3 18 23 OSCAR 34.3 140.7 64 668 +1994 6 5 6 9 MICHAEL 68.1 200.6 100 682 +1957 11 24 6 24 SANDY 49.1 205.7 16 605 +2004 2 15 0 21 KIRK 13.9 282.2 60 802 +1951 12 16 12 6 WILLIAM 63.2 232.4 19 843 +2004 10 19 0 27 BERYL 23.8 51.7 81 519 +1981 1 23 18 13 BERYL 13.3 338.6 142 199 +1986 9 22 12 5 TONY 59.6 77.2 112 312 +1991 5 13 0 2 SANDY 10.5 84.1 154 344 +1975 8 14 18 5 HELENE 42.0 189.4 135 334 +1969 4 21 0 24 ERNESTO 49.1 31.0 22 464 +1960 1 23 0 23 RAFAEL 13.4 190.0 71 792 +1997 5 24 6 20 TONY 53.1 216.6 124 559 +1989 8 8 0 21 JOYCE 49.2 183.4 161 331 +1997 3 12 18 25 LESLIE 17.9 282.3 134 529 +1965 9 1 0 12 RAFAEL 21.9 22.2 74 194 +1967 10 20 0 1 LESLIE 57.2 186.1 40 530 +1977 4 23 12 24 FLORENCE 66.3 303.6 152 354 +1965 8 24 6 27 ERNESTO 14.5 233.4 44 270 +1990 11 7 6 10 NADINE 66.7 179.6 123 840 +1955 1 20 6 1 WILLIAM 56.1 275.6 160 389 +1963 2 12 0 25 SANDY 35.1 84.5 34 402 +1959 4 21 12 22 CHRIS 30.1 349.4 11 789 +1985 12 14 0 19 ISAAC 53.2 31.6 90 695 +1969 7 11 0 3 ERNESTO 57.7 161.4 104 227 +2000 6 3 18 8 SANDY 47.3 339.2 50 683 +1997 4 25 18 5 GORDON 11.1 271.1 31 317 +1957 7 22 18 17 TONY 8.4 263.9 102 200 +1995 4 21 0 18 JOYCE 54.4 254.4 63 345 +1956 11 18 18 19 TONY 8.8 351.5 82 359 +1955 3 14 18 23 RAFAEL 48.6 124.7 144 779 +2001 5 25 6 5 VALERIE 65.6 348.1 62 144 +1950 4 13 18 22 ERNESTO 25.9 187.0 72 864 +1992 2 22 12 22 WILLIAM 26.6 357.3 110 563 +1969 3 8 6 10 LESLIE 49.9 209.1 35 31 +1950 9 15 0 9 VALERIE 28.9 70.1 56 543 +1954 4 6 18 2 HELENE 48.7 277.5 84 484 +1982 7 27 6 25 HELENE 49.4 30.9 161 692 +1995 7 16 12 1 ERNESTO 65.9 206.6 19 373 +1982 12 25 18 21 JOYCE 49.9 197.6 109 47 +1955 6 26 12 28 MICHAEL 37.9 281.1 75 418 +2004 7 24 12 18 WILLIAM 14.5 192.8 149 691 +1971 1 24 0 23 SANDY 28.3 345.4 80 684 +1993 5 24 0 6 NADINE 60.2 99.1 66 584 +1964 11 7 18 7 OSCAR 22.7 164.4 35 216 +1978 3 17 12 11 LESLIE 22.6 26.0 135 896 +1953 1 1 12 22 DEBBY 15.6 98.3 62 22 +1975 5 18 6 19 CHRIS 67.3 92.2 10 160 +1958 6 18 18 28 LESLIE 69.2 85.7 116 584 +1974 8 4 12 28 NADINE 12.3 329.3 85 423 +1986 3 16 6 5 FLORENCE 55.4 74.8 96 77 +1996 9 21 6 1 OSCAR 45.5 205.8 136 79 +1950 2 10 18 9 KIRK 9.9 215.2 50 860 +2001 7 2 6 7 CHRIS 51.8 227.7 109 327 +1956 9 22 12 14 PATTY 12.6 227.5 65 735 +2002 6 27 0 20 CHRIS 67.1 143.7 112 131 +1980 7 28 18 25 MICHAEL 64.6 53.8 125 622 +1979 4 22 18 27 PATTY 27.8 177.2 137 453 +1984 12 24 0 9 RAFAEL 21.3 263.7 77 545 +1975 2 6 6 17 ERNESTO 63.4 22.3 54 353 +1976 12 21 18 8 MICHAEL 55.6 336.4 42 22 +1964 10 20 18 1 MICHAEL 21.4 272.9 63 336 +1993 2 2 18 28 OSCAR 20.5 215.8 145 56 +1957 4 24 6 16 CHRIS 56.2 339.8 115 571 +1994 3 24 6 13 OSCAR 40.7 50.9 64 89 +1955 10 2 12 18 WILLIAM 9.1 242.1 61 27 +1986 3 22 12 26 CHRIS 46.7 225.0 38 172 +1962 7 6 18 15 OSCAR 33.5 90.6 98 252 +1987 6 10 18 16 FLORENCE 41.2 162.3 152 395 +2004 7 23 6 12 ISAAC 24.5 199.7 110 55 +1959 12 8 12 1 NADINE 41.1 45.0 85 721 +1977 5 8 6 21 ALBERTO 40.0 301.9 157 26 +2002 9 15 18 8 OSCAR 29.5 140.6 24 44 +1952 9 16 6 28 ISAAC 45.2 336.2 89 586 +1955 9 4 6 12 VALERIE 54.7 199.8 18 394 +1999 12 22 12 14 JOYCE 59.6 355.0 17 510 +2002 12 5 6 2 OSCAR 67.7 167.0 45 603 +1994 12 5 0 1 DEBBY 27.3 304.1 83 69 +1972 3 7 0 5 RAFAEL 63.9 241.5 103 56 +1965 10 20 18 25 TONY 26.0 192.0 63 414 +1964 1 13 12 5 PATTY 14.9 198.6 25 307 +1993 10 16 0 9 HELENE 52.7 177.8 110 637 +2004 1 12 0 11 JOYCE 37.9 227.0 49 573 +1962 8 16 6 10 LESLIE 15.2 245.6 96 251 +1952 8 23 6 8 GORDON 27.3 337.0 68 734 +1950 1 15 0 16 SANDY 13.0 70.4 140 217 +1977 7 21 12 10 PATTY 32.2 174.9 119 557 +1982 1 16 18 7 ISAAC 61.2 257.2 111 220 +1988 7 23 6 28 ERNESTO 45.0 142.0 86 152 +1959 6 14 0 5 LESLIE 69.5 186.8 105 730 +1974 8 7 18 15 LESLIE 52.6 355.8 98 620 +2000 1 27 6 24 CHRIS 40.2 355.5 93 535 +2002 8 19 18 1 KIRK 20.5 263.4 81 545 +1999 11 10 18 9 KIRK 51.6 284.3 141 689 +1991 3 23 12 18 RAFAEL 55.6 187.6 119 327 +1962 5 19 12 1 HELENE 67.2 316.5 98 314 +2003 2 13 6 4 KIRK 43.3 288.3 15 84 +1962 11 13 12 15 FLORENCE 17.9 112.3 79 744 +1957 9 20 12 22 ALBERTO 53.9 302.1 115 309 +1982 12 1 18 12 BERYL 31.5 119.1 135 885 +1970 4 20 0 24 NADINE 58.7 87.5 86 440 +1975 2 25 18 2 PATTY 55.3 182.7 43 347 +1999 2 10 6 10 PATTY 14.0 191.2 62 460 +1965 4 20 0 16 CHRIS 14.8 61.6 12 187 +1970 9 2 6 6 HELENE 38.9 23.4 46 302 +1994 5 5 6 15 MICHAEL 49.8 107.3 95 332 +1969 4 17 18 16 LESLIE 33.1 352.2 94 89 +1958 2 10 0 27 WILLIAM 17.8 62.1 10 684 +1976 11 28 12 16 LESLIE 7.0 197.7 23 456 +1980 12 17 6 24 ISAAC 56.7 184.1 155 356 +1995 7 4 0 14 PATTY 28.0 165.5 140 444 +1982 7 19 12 17 KIRK 17.1 280.6 117 894 +1985 3 26 6 3 JOYCE 44.5 333.5 107 376 +1951 1 24 0 4 TONY 12.2 92.5 85 830 +1963 5 25 0 19 GORDON 8.8 344.9 125 633 +1980 5 6 18 21 MICHAEL 21.2 176.9 136 818 +1970 6 11 0 9 ALBERTO 53.9 201.7 134 224 +1963 2 18 6 26 WILLIAM 33.2 2.5 60 796 +1973 8 25 0 19 MICHAEL 57.3 124.5 52 111 +1982 3 18 18 26 WILLIAM 53.4 186.3 95 503 +1981 9 25 6 1 NADINE 45.4 99.1 69 781 +1986 10 10 6 3 PATTY 69.4 188.9 52 217 +1950 4 27 0 17 MICHAEL 51.1 322.8 111 501 +1976 5 8 18 3 ALBERTO 50.5 162.7 15 406 +1994 12 24 18 26 NADINE 53.0 110.4 133 463 +1964 8 9 18 20 ERNESTO 45.4 123.8 59 113 +1978 11 7 12 21 RAFAEL 55.7 331.3 82 160 +1980 1 25 6 28 LESLIE 34.8 347.5 65 126 +1994 3 6 18 15 HELENE 12.6 192.3 76 892 +1960 1 1 12 9 ERNESTO 64.5 3.4 123 330 +1962 10 17 12 11 VALERIE 57.6 203.6 52 81 +1985 6 19 0 28 MICHAEL 45.5 119.8 140 853 +2003 7 9 18 21 KIRK 13.1 92.0 153 31 +1960 6 6 12 20 GORDON 21.4 151.9 109 602 +1984 5 1 18 2 HELENE 52.8 156.0 123 162 +1954 6 14 12 7 KIRK 70.0 306.0 133 330 +1972 11 6 6 5 SANDY 49.6 61.6 135 691 +2002 7 17 6 4 LESLIE 60.2 150.4 37 437 +1968 9 7 6 5 MICHAEL 8.1 211.4 11 707 +1959 8 3 0 16 ERNESTO 24.9 168.8 13 573 +1998 8 18 18 4 ISAAC 28.0 166.3 38 228 +1967 3 23 12 13 ALBERTO 55.5 235.5 121 705 +1974 2 21 12 18 WILLIAM 7.4 317.3 24 358 +1971 1 24 12 11 KIRK 63.3 70.2 67 816 +1981 3 11 0 19 MICHAEL 37.2 86.6 79 99 +2003 1 10 0 27 PATTY 45.5 280.5 78 220 +2000 9 19 18 10 VALERIE 49.6 260.7 21 62 +1958 3 13 6 16 ERNESTO 26.4 39.7 108 635 +2001 1 3 6 10 NADINE 11.6 330.3 135 305 +1958 11 2 6 13 FLORENCE 19.8 23.6 92 63 +1962 9 13 6 10 ERNESTO 63.3 49.5 136 143 +1955 12 12 12 3 SANDY 34.2 95.4 149 793 +1958 10 13 6 9 VALERIE 14.1 229.9 44 205 +1972 6 2 18 5 JOYCE 57.0 126.3 117 588 +1991 5 25 12 6 HELENE 69.9 215.8 86 283 +1986 10 13 18 10 GORDON 13.3 217.5 97 371 +1969 6 26 12 12 LESLIE 51.0 101.7 108 860 +1960 12 20 0 8 DEBBY 38.9 312.1 61 178 +1969 2 10 0 28 ERNESTO 21.0 34.7 79 697 +1986 2 11 12 25 RAFAEL 28.2 276.1 24 83 +1952 11 2 6 7 KIRK 18.5 266.5 55 707 +1991 1 24 18 14 VALERIE 58.3 168.0 132 774 +1974 2 17 0 28 JOYCE 11.8 303.6 16 420 +1985 10 13 0 23 ALBERTO 66.3 226.9 127 489 +1999 5 15 6 16 ALBERTO 52.9 228.7 87 133 +1999 11 2 6 27 HELENE 20.3 284.4 34 810 +1967 6 18 12 17 WILLIAM 49.8 174.1 36 735 +1971 6 3 6 14 HELENE 38.7 343.4 134 738 +1962 12 5 18 9 ISAAC 13.7 329.2 123 435 +1966 4 4 18 1 DEBBY 29.1 59.8 125 474 +1954 11 16 12 15 DEBBY 13.7 150.2 19 660 +1953 2 23 12 25 JOYCE 35.2 162.2 24 793 +1970 6 1 6 16 BERYL 47.5 88.3 36 377 +1963 10 11 6 22 OSCAR 57.3 312.6 10 312 +1989 8 24 12 13 GORDON 8.7 153.9 153 602 +1983 7 25 6 10 SANDY 28.6 218.7 22 483 +1955 11 20 0 15 SANDY 25.0 163.4 132 185 +1995 5 22 12 8 OSCAR 44.2 27.8 125 603 +1961 11 10 0 28 BERYL 34.2 123.3 103 617 +1973 2 10 6 22 JOYCE 53.3 283.5 98 138 +1969 3 6 6 20 RAFAEL 43.9 193.9 60 499 +2003 2 27 12 21 JOYCE 7.7 299.5 95 233 +1959 9 26 12 9 PATTY 11.9 273.9 140 93 +1983 2 15 12 15 NADINE 15.2 133.7 51 585 +2001 9 14 12 26 OSCAR 37.4 44.0 50 620 +1975 9 25 0 11 ISAAC 30.1 258.0 131 93 +1995 10 27 6 10 HELENE 66.2 118.4 93 255 +1995 5 5 18 21 SANDY 63.0 259.1 145 229 +1975 6 23 0 10 PATTY 39.7 22.3 159 107 +1972 5 12 0 21 LESLIE 36.4 87.8 22 741 +1972 10 22 12 6 GORDON 62.7 263.0 34 244 +1954 1 2 6 12 ERNESTO 13.1 108.5 105 788 +1980 7 12 6 7 ALBERTO 50.7 95.1 41 584 +1992 7 4 18 16 PATTY 26.9 268.9 135 194 +1954 4 12 6 3 GORDON 8.8 20.0 31 193 +1961 7 19 6 2 ISAAC 24.3 311.1 113 338 +2003 9 17 12 17 KIRK 22.5 107.6 130 296 +1969 8 7 6 5 MICHAEL 29.0 46.4 110 33 +1976 7 24 12 25 ERNESTO 38.8 133.0 28 193 +1959 12 27 0 16 TONY 31.3 275.0 54 896 +1981 5 24 6 22 GORDON 52.7 146.7 151 134 +1993 11 7 18 7 BERYL 45.6 29.4 69 74 +1976 3 8 6 22 ISAAC 58.8 90.7 24 897 +1969 3 18 12 17 RAFAEL 23.5 314.1 85 175 +1980 10 13 12 8 NADINE 37.3 191.1 152 126 +1967 5 10 0 10 FLORENCE 53.9 356.3 117 478 +1965 4 22 12 14 DEBBY 22.3 225.0 44 847 +1954 3 18 6 22 ALBERTO 40.7 46.3 120 629 +1957 1 23 18 16 PATTY 44.9 174.2 96 585 +1994 4 18 6 6 MICHAEL 23.9 188.3 127 698 +1968 2 28 12 15 VALERIE 7.3 143.2 141 480 +1975 1 6 0 24 RAFAEL 53.3 81.0 154 640 +1967 4 14 12 14 HELENE 25.7 110.9 90 554 +1978 3 18 12 5 ERNESTO 21.9 306.4 135 40 +1984 8 26 12 7 KIRK 66.6 167.8 78 328 +2000 6 9 18 2 TONY 30.8 16.6 76 304 +1985 4 14 18 28 PATTY 59.1 321.7 124 755 +1981 1 23 18 24 ERNESTO 24.9 75.6 147 334 +1952 3 9 6 2 ALBERTO 26.0 106.9 113 624 +2001 12 28 12 21 NADINE 60.5 84.6 109 516 +1990 3 11 6 23 MICHAEL 58.9 197.2 100 47 +1979 12 8 6 11 JOYCE 8.0 45.2 88 271 +1981 3 24 6 26 LESLIE 15.8 46.4 154 458 +1980 6 27 0 26 PATTY 8.1 274.7 41 368 +1972 2 12 6 27 NADINE 41.3 82.8 90 511 +1960 3 13 6 22 KIRK 20.4 134.6 133 21 +1988 8 21 18 22 LESLIE 41.1 71.2 148 507 +1990 9 15 0 28 NADINE 19.2 321.8 161 474 +1952 3 7 12 25 LESLIE 21.6 305.3 141 803 +1970 8 19 6 22 TONY 37.9 107.3 74 875 +1951 7 24 18 11 RAFAEL 65.3 254.0 45 475 +1989 12 9 0 24 SANDY 46.5 63.7 112 448 +1988 11 20 0 10 BERYL 69.2 143.3 124 99 +1995 2 1 0 7 ISAAC 27.3 281.5 63 359 +1970 2 7 0 28 PATTY 52.4 219.8 117 851 +1963 1 28 18 20 MICHAEL 8.5 316.9 67 426 +2000 4 20 18 28 PATTY 64.9 73.6 111 872 +1965 9 25 6 21 RAFAEL 51.4 125.6 54 464 +1971 6 16 12 5 ALBERTO 45.4 308.6 148 785 +1972 10 25 6 6 GORDON 48.3 310.5 38 472 +1960 8 27 0 12 ALBERTO 27.8 67.8 131 262 +1959 12 19 0 23 BERYL 52.5 10.7 62 151 +1969 1 18 12 3 MICHAEL 31.8 27.0 140 134 +1963 10 12 12 9 SANDY 32.2 95.7 48 179 +1980 10 10 6 28 NADINE 62.1 229.7 64 665 +1969 6 23 6 2 OSCAR 64.6 356.5 37 785 +1999 10 21 18 17 BERYL 15.0 346.2 50 443 +1967 11 1 18 25 TONY 58.3 188.4 148 2 +2004 8 1 18 20 DEBBY 28.0 337.1 158 355 +1953 12 11 0 16 VALERIE 31.7 339.4 156 345 +1981 3 28 0 6 JOYCE 66.9 64.9 142 885 +1957 8 3 18 24 CHRIS 57.4 132.6 79 446 +1988 7 26 6 7 PATTY 61.0 267.8 74 99 +1993 4 20 0 23 PATTY 60.5 249.2 26 8 +1981 12 3 6 20 VALERIE 30.7 265.1 53 845 +1977 9 19 6 7 MICHAEL 25.0 21.8 87 777 +1997 6 8 12 14 ERNESTO 24.0 339.7 128 239 +1957 10 23 0 27 HELENE 46.9 39.4 112 634 +2004 3 7 18 10 KIRK 21.0 205.2 38 417 +1978 7 14 0 28 ERNESTO 48.2 241.1 54 631 +1969 7 17 6 11 KIRK 36.8 15.3 115 811 +1953 4 26 12 8 ERNESTO 19.1 148.9 20 283 +1982 1 5 6 11 PATTY 53.9 65.1 10 758 +1962 9 25 6 18 MICHAEL 68.0 131.1 18 185 +1982 3 22 0 8 MICHAEL 60.4 213.8 40 121 +1984 2 18 0 3 CHRIS 23.0 0.3 154 455 +1984 5 4 18 7 JOYCE 10.5 196.5 36 831 +1984 8 27 18 28 HELENE 13.2 321.6 89 839 +1978 4 15 18 3 VALERIE 31.1 326.0 151 469 +1975 7 16 0 9 LESLIE 30.3 197.7 22 116 +1965 4 25 12 2 PATTY 12.6 226.3 86 894 +1952 4 26 0 14 KIRK 65.5 314.2 21 66 +1954 5 11 0 27 LESLIE 29.8 53.1 120 450 +1953 3 1 12 19 FLORENCE 60.9 163.2 23 662 +1962 9 17 0 6 WILLIAM 15.3 64.5 74 540 +2004 2 12 0 12 GORDON 68.8 172.3 149 368 +1999 5 1 6 23 ERNESTO 14.5 54.6 163 785 +1979 5 14 18 22 TONY 36.4 209.5 70 282 +1979 8 12 6 7 ISAAC 10.8 152.7 63 646 +2000 5 20 6 17 HELENE 27.0 30.4 33 369 +1959 5 19 18 8 MICHAEL 12.3 55.4 65 287 +1964 1 7 0 2 KIRK 48.7 50.7 107 98 +1974 10 24 12 25 NADINE 57.6 215.9 144 416 diff --git a/benchmarks/new_opencl/nearn/cane4_1.db b/benchmarks/new_opencl/nearn/cane4_1.db new file mode 100755 index 00000000..c5c1b3c3 --- /dev/null +++ b/benchmarks/new_opencl/nearn/cane4_1.db @@ -0,0 +1,10691 @@ +1997 3 1 12 28 TONY 9.3 315.8 87 9 +1957 5 8 6 5 HELENE 23.1 61.6 105 876 +1954 3 22 6 18 MICHAEL 59.8 108.5 150 276 +1963 9 25 6 5 ERNESTO 18.0 180.0 77 202 +1978 12 2 18 13 FLORENCE 37.8 306.2 147 267 +1962 1 3 0 10 OSCAR 13.7 142.8 28 32 +1975 6 7 6 16 RAFAEL 40.1 147.9 126 493 +1967 9 20 18 27 SANDY 11.0 146.7 105 379 +1956 4 1 0 9 DEBBY 13.9 204.2 138 399 +1998 4 1 12 25 JOYCE 60.7 251.5 96 103 +1992 7 18 18 24 BERYL 35.0 232.2 22 210 +2000 6 26 12 17 ERNESTO 40.2 337.4 108 337 +1977 9 24 18 15 ERNESTO 65.0 336.9 46 733 +1987 11 9 6 26 SANDY 33.0 333.3 92 78 +1982 1 17 18 6 JOYCE 8.6 242.1 100 691 +1987 1 23 6 16 OSCAR 51.1 337.8 93 13 +1978 7 18 6 24 ERNESTO 65.1 143.8 37 745 +1964 11 17 0 15 GORDON 51.6 97.5 48 595 +1999 7 6 12 14 PATTY 69.0 44.1 65 330 +1959 1 17 18 20 OSCAR 46.5 354.7 70 258 +1975 3 1 18 8 JOYCE 47.5 204.0 142 187 +1974 5 4 12 6 FLORENCE 46.5 331.5 145 661 +1968 10 9 6 7 FLORENCE 57.4 155.4 65 212 +2004 1 16 12 24 SANDY 37.9 124.5 36 201 +2000 6 7 18 14 ISAAC 22.3 274.5 42 830 +1999 1 1 0 5 CHRIS 38.8 321.8 76 437 +1964 10 17 0 27 HELENE 56.2 286.9 119 771 +1986 9 10 18 9 WILLIAM 9.1 129.6 164 618 +1990 2 12 0 18 ALBERTO 35.7 157.1 73 845 +1966 1 26 0 21 WILLIAM 32.0 75.5 25 177 +1961 2 26 0 19 KIRK 56.3 265.5 86 669 +1976 8 23 18 14 KIRK 11.8 190.4 88 37 +1983 8 26 0 13 FLORENCE 22.6 11.3 134 72 +1976 2 2 0 7 PATTY 53.1 155.7 37 328 +1981 10 4 6 24 BERYL 66.5 187.6 20 163 +1970 4 19 6 23 SANDY 59.7 136.9 88 20 +1969 10 7 6 18 VALERIE 17.1 133.2 78 74 +1979 2 21 18 13 MICHAEL 49.7 232.9 77 160 +1993 2 17 6 1 CHRIS 41.2 223.0 10 555 +1989 1 6 6 5 JOYCE 29.0 171.2 75 473 +1994 7 5 6 8 NADINE 27.0 342.7 73 234 +1951 5 9 18 20 MICHAEL 38.1 295.3 10 892 +1971 8 13 0 4 RAFAEL 60.3 4.1 102 309 +1974 6 23 6 27 LESLIE 44.4 29.4 28 608 +1963 2 23 18 17 HELENE 13.2 96.8 50 435 +1987 9 15 6 2 KIRK 10.3 228.3 97 825 +1974 1 14 18 13 ISAAC 34.0 275.6 14 737 +1984 11 13 12 6 MICHAEL 66.5 203.7 50 876 +1955 6 5 0 27 MICHAEL 38.8 90.9 163 238 +1968 7 27 18 1 JOYCE 14.2 41.3 112 221 +1967 8 7 12 24 WILLIAM 17.1 195.8 24 579 +1996 6 24 12 20 CHRIS 55.5 185.8 47 309 +1987 9 4 0 21 GORDON 32.6 265.4 47 94 +1999 5 8 6 16 OSCAR 14.1 47.7 139 100 +1994 4 27 0 11 DEBBY 66.2 143.8 68 251 +1983 2 4 0 6 DEBBY 66.3 355.0 79 467 +2004 12 16 12 17 DEBBY 50.9 290.5 157 782 +1999 5 11 12 5 CHRIS 63.4 235.2 129 240 +1986 6 6 12 12 OSCAR 14.5 351.0 162 763 +2002 3 3 6 24 PATTY 27.2 23.3 161 234 +1987 4 4 18 17 KIRK 68.9 91.0 148 885 +1970 10 27 6 22 RAFAEL 17.5 223.1 77 242 +1969 1 17 12 3 DEBBY 9.2 160.8 157 640 +1995 3 19 18 8 RAFAEL 27.8 340.6 137 224 +1983 7 16 18 10 ERNESTO 21.1 132.1 136 602 +1972 9 18 18 24 LESLIE 13.6 75.6 112 708 +1995 6 14 12 9 BERYL 47.0 286.2 163 111 +1977 5 2 0 6 SANDY 46.0 303.5 57 33 +1972 1 6 0 27 DEBBY 24.2 50.7 81 34 +2001 2 3 18 3 VALERIE 68.4 91.8 44 307 +1965 7 8 18 19 OSCAR 18.8 219.2 18 133 +1998 3 24 12 1 ERNESTO 14.2 108.8 156 426 +2004 1 6 12 25 SANDY 50.1 227.5 100 866 +1960 3 12 18 1 ALBERTO 52.0 225.7 18 299 +1989 7 21 12 22 RAFAEL 48.2 197.1 18 18 +1980 6 1 18 18 LESLIE 25.1 159.4 156 225 +2004 11 6 0 15 LESLIE 49.9 280.5 146 55 +1992 5 10 18 7 KIRK 28.1 168.5 17 72 +2004 3 6 6 7 WILLIAM 14.4 176.2 121 870 +1953 9 20 6 21 FLORENCE 36.4 292.6 29 728 +1977 10 3 12 20 KIRK 54.8 181.3 83 740 +1968 11 13 18 27 OSCAR 9.6 108.4 84 152 +1997 9 23 0 28 VALERIE 57.8 162.4 136 67 +1989 5 27 0 9 ERNESTO 66.9 246.1 39 563 +1976 12 18 6 20 GORDON 44.0 325.5 164 120 +1962 12 8 12 12 ALBERTO 7.7 78.6 21 840 +1950 4 16 12 4 DEBBY 26.2 317.8 66 99 +1979 9 6 18 17 NADINE 10.6 125.4 163 542 +1971 11 5 18 7 NADINE 14.2 283.0 138 833 +1992 11 14 18 9 MICHAEL 14.6 319.2 143 459 +1992 3 19 6 25 TONY 57.4 291.5 77 551 +1968 4 28 18 3 KIRK 30.4 203.5 84 895 +1964 11 11 6 6 RAFAEL 28.1 141.2 15 627 +1989 10 24 18 9 VALERIE 45.3 305.5 56 63 +1969 7 9 6 5 LESLIE 67.2 3.7 83 265 +1955 4 22 18 7 SANDY 24.5 325.7 25 300 +1968 2 27 0 7 HELENE 46.9 265.2 103 299 +1968 11 18 0 14 NADINE 39.8 10.1 72 450 +1969 3 22 0 1 NADINE 8.2 163.3 163 703 +1992 4 17 12 28 ERNESTO 40.6 103.3 158 784 +1955 11 18 0 26 ISAAC 46.4 226.7 106 172 +1961 8 8 0 7 MICHAEL 24.7 249.8 19 354 +1984 11 24 6 26 RAFAEL 39.4 220.8 49 399 +1964 4 26 0 28 WILLIAM 16.3 165.5 19 77 +1986 4 7 12 8 ERNESTO 28.1 196.8 150 898 +1963 4 12 12 15 WILLIAM 43.5 266.8 66 571 +1979 4 15 12 28 WILLIAM 67.5 84.8 86 879 +1952 3 12 6 23 NADINE 47.4 94.8 96 718 +1996 4 21 0 27 ERNESTO 40.3 123.1 50 494 +1984 5 14 12 7 MICHAEL 58.0 53.0 19 660 +1990 3 3 12 26 PATTY 52.1 336.1 95 617 +1963 1 12 18 22 ISAAC 61.7 39.4 63 77 +2001 1 25 18 6 ISAAC 41.3 98.0 82 663 +2004 10 4 0 2 ERNESTO 62.6 232.5 22 721 +1996 7 22 18 22 MICHAEL 52.2 296.1 98 661 +1951 7 21 12 1 ERNESTO 30.5 146.6 34 751 +1953 11 26 0 15 RAFAEL 60.2 25.4 52 176 +1978 10 16 18 23 JOYCE 26.3 128.7 94 816 +2001 2 18 18 6 ERNESTO 23.0 23.1 39 860 +2000 5 11 6 9 KIRK 29.0 130.4 64 690 +1962 12 9 18 1 ISAAC 12.5 227.2 70 795 +1970 1 10 6 9 KIRK 35.9 60.3 47 300 +1972 9 20 12 18 JOYCE 68.7 0.3 50 478 +1974 11 24 18 19 LESLIE 59.9 194.0 115 424 +1999 1 7 18 8 PATTY 8.9 226.2 155 717 +1975 5 6 18 11 FLORENCE 8.5 326.1 16 401 +1958 11 8 6 6 TONY 20.6 110.3 129 481 +1967 3 27 6 10 DEBBY 39.1 60.9 61 508 +1967 7 13 18 27 DEBBY 46.1 187.0 86 347 +1984 4 8 18 20 TONY 22.9 55.1 31 246 +1954 12 9 6 12 ERNESTO 59.2 253.6 36 746 +2001 11 22 12 6 PATTY 13.3 229.2 55 200 +1969 2 1 6 20 FLORENCE 59.8 280.0 92 818 +1954 3 15 6 20 NADINE 32.7 321.6 56 376 +1953 9 8 6 14 HELENE 32.1 242.9 14 377 +1957 4 17 6 12 ALBERTO 32.5 87.8 54 510 +1976 7 24 6 8 TONY 68.5 294.4 32 36 +1977 6 10 18 4 KIRK 63.6 3.2 141 439 +1969 11 13 6 9 HELENE 42.5 104.0 69 365 +1977 3 9 18 24 LESLIE 17.6 236.8 145 581 +1956 6 11 6 12 MICHAEL 10.3 141.2 118 3 +1976 12 15 12 15 JOYCE 57.5 97.8 91 109 +1978 7 7 12 16 CHRIS 28.7 212.7 71 79 +1981 10 25 6 7 KIRK 61.7 264.8 153 608 +1978 4 28 18 24 JOYCE 65.1 116.9 52 283 +2002 3 28 6 20 BERYL 51.5 4.9 37 16 +1972 4 7 12 15 ERNESTO 25.8 82.3 41 389 +2000 5 6 0 7 TONY 33.3 6.3 70 109 +1959 1 4 12 14 FLORENCE 54.2 350.8 148 578 +1962 3 23 12 10 WILLIAM 69.4 22.9 131 776 +2004 6 13 18 13 FLORENCE 7.3 39.6 72 138 +1973 7 24 6 28 DEBBY 22.0 9.6 107 838 +2004 2 24 12 15 NADINE 57.7 9.7 85 199 +1982 3 21 0 7 ALBERTO 64.8 77.3 17 300 +1981 1 5 6 28 BERYL 11.4 188.5 120 792 +1979 6 16 18 13 OSCAR 30.9 102.1 59 854 +1962 3 14 12 13 SANDY 66.2 204.8 153 201 +1978 1 17 18 27 JOYCE 46.1 333.2 116 203 +1978 1 24 0 19 LESLIE 14.0 117.8 93 765 +1980 6 26 18 5 DEBBY 25.8 312.3 26 293 +1997 8 4 12 23 BERYL 22.2 53.2 154 695 +1957 11 4 6 10 OSCAR 28.3 259.5 69 284 +1971 6 26 6 3 CHRIS 43.8 36.5 69 523 +1983 2 23 0 23 CHRIS 30.4 3.1 31 761 +2002 4 8 0 20 DEBBY 22.7 298.9 79 788 +1969 7 10 18 17 TONY 45.3 186.9 66 597 +1974 12 4 6 11 NADINE 13.1 147.0 20 386 +1988 9 13 6 10 PATTY 56.0 23.6 52 575 +1979 2 24 12 18 MICHAEL 38.9 99.3 132 255 +1952 2 27 6 16 SANDY 32.6 274.0 132 651 +1973 5 16 18 20 GORDON 36.1 33.5 29 780 +1961 10 8 6 25 RAFAEL 50.6 58.0 100 743 +1975 3 17 18 11 WILLIAM 15.7 39.5 101 70 +2002 4 6 0 14 TONY 17.1 245.3 143 503 +1972 4 15 12 20 KIRK 64.3 154.8 115 286 +1993 8 9 0 14 GORDON 41.2 36.9 20 161 +1959 9 19 6 25 LESLIE 58.0 244.2 18 867 +1994 3 5 0 21 LESLIE 55.5 219.5 137 660 +1950 4 8 18 15 ISAAC 67.7 164.7 131 398 +1965 6 9 6 5 ERNESTO 34.9 26.4 164 504 +1965 3 3 18 1 BERYL 46.3 193.6 56 441 +2004 8 6 18 24 GORDON 22.9 340.4 110 408 +1992 10 21 18 2 LESLIE 65.0 270.3 77 182 +1954 10 2 0 13 NADINE 34.1 63.9 91 598 +1987 10 18 6 20 GORDON 59.7 175.6 98 828 +1952 1 27 18 7 SANDY 28.3 189.7 99 890 +1977 5 24 6 16 TONY 46.5 329.9 28 428 +1957 1 3 6 10 VALERIE 25.8 192.2 87 214 +1992 9 22 12 7 GORDON 65.6 124.2 84 516 +1954 1 2 6 2 PATTY 38.7 133.4 10 709 +1996 8 1 18 24 LESLIE 31.3 186.9 72 893 +1973 3 2 18 10 HELENE 58.6 201.4 91 256 +2003 12 1 18 12 ALBERTO 48.9 106.2 34 699 +1978 9 16 6 7 ISAAC 30.0 189.8 152 105 +1955 8 19 12 24 DEBBY 47.4 351.5 128 403 +1979 10 23 18 6 OSCAR 55.1 102.8 96 351 +1992 4 21 18 11 OSCAR 66.7 255.9 97 270 +1993 10 13 12 1 KIRK 29.8 37.8 54 121 +1986 7 14 0 13 LESLIE 67.0 119.4 138 167 +1968 5 25 12 20 PATTY 20.9 253.4 11 185 +1994 9 5 12 16 FLORENCE 42.6 115.2 103 626 +1982 11 15 18 6 DEBBY 39.0 71.4 124 650 +2000 3 16 18 19 LESLIE 65.1 277.0 29 191 +2004 11 27 12 19 VALERIE 32.4 325.5 88 612 +1984 2 5 0 1 FLORENCE 42.5 2.1 100 522 +1956 12 28 0 25 BERYL 21.7 338.5 52 870 +1965 3 23 6 26 RAFAEL 36.7 337.5 117 419 +1958 1 27 18 2 BERYL 49.3 14.0 119 608 +1962 6 5 0 23 ERNESTO 51.0 147.2 105 50 +1975 3 9 6 28 KIRK 17.5 96.4 146 580 +1987 11 7 0 16 JOYCE 25.9 117.2 132 775 +1980 10 16 6 19 FLORENCE 15.8 242.3 85 285 +1962 12 20 6 12 PATTY 43.1 36.2 120 586 +1970 5 6 0 14 SANDY 9.8 117.1 93 212 +1971 12 2 0 28 CHRIS 26.4 335.3 97 90 +2004 10 26 18 6 GORDON 42.0 144.1 127 131 +1975 1 18 18 12 SANDY 47.1 307.6 134 586 +1966 12 2 18 1 NADINE 59.1 0.4 119 663 +1996 9 13 12 7 VALERIE 28.3 271.2 22 472 +1978 8 7 6 13 WILLIAM 9.4 297.4 76 747 +1988 5 9 0 15 ISAAC 31.9 326.3 100 498 +1993 7 12 12 17 WILLIAM 30.2 30.6 24 138 +1970 1 23 0 2 MICHAEL 50.2 293.3 144 116 +1971 5 19 18 13 ALBERTO 35.5 85.9 49 681 +1970 3 9 12 12 HELENE 14.9 305.5 112 263 +1959 2 23 12 10 JOYCE 39.1 306.2 74 310 +1967 3 28 6 12 PATTY 16.8 127.6 35 797 +1991 7 10 6 19 PATTY 37.9 241.6 107 612 +1955 9 10 0 18 RAFAEL 29.2 125.9 106 430 +1978 1 6 12 24 HELENE 55.4 355.4 105 143 +1986 2 3 18 17 RAFAEL 8.0 279.9 161 892 +1989 5 22 0 15 OSCAR 40.0 98.5 36 259 +1956 2 12 18 3 MICHAEL 42.5 335.9 123 330 +1996 9 17 18 14 ERNESTO 47.8 18.9 160 145 +1959 2 5 0 10 RAFAEL 11.0 20.1 129 190 +1988 9 5 0 17 RAFAEL 8.5 280.9 42 35 +1974 7 26 18 12 TONY 18.8 336.8 96 475 +1992 5 3 18 12 WILLIAM 14.8 118.4 35 28 +1992 10 20 6 8 ALBERTO 58.8 265.0 18 471 +1966 12 11 0 20 NADINE 17.4 334.5 78 825 +1964 8 20 6 10 ISAAC 44.6 45.6 149 162 +1983 7 27 18 1 OSCAR 59.1 188.4 117 280 +1991 4 11 6 25 LESLIE 11.9 21.3 20 336 +2002 10 21 18 3 GORDON 15.7 39.8 16 613 +1992 11 13 12 11 HELENE 21.6 301.2 134 39 +1957 3 18 0 5 JOYCE 50.8 253.0 25 748 +1968 3 10 0 8 ALBERTO 30.3 347.5 81 21 +1962 11 28 6 20 PATTY 43.2 30.3 38 476 +1996 5 2 6 25 KIRK 52.0 298.5 157 471 +1950 10 21 12 28 OSCAR 66.9 344.4 69 21 +1995 11 18 0 13 OSCAR 32.4 219.6 110 797 +1964 6 26 6 12 BERYL 63.1 107.4 10 596 +1981 5 14 18 7 ALBERTO 42.2 215.0 65 694 +1996 9 23 18 28 WILLIAM 25.8 260.9 80 467 +1962 10 19 18 23 TONY 34.9 48.9 95 893 +1983 7 1 18 28 OSCAR 61.0 164.0 40 231 +1969 5 11 12 19 TONY 26.9 24.1 111 734 +1974 12 6 0 2 MICHAEL 31.7 83.4 158 360 +1960 11 22 6 19 FLORENCE 19.9 219.3 18 291 +1960 8 20 6 8 TONY 44.7 330.4 47 187 +1978 8 2 0 9 LESLIE 44.4 33.3 163 455 +1955 7 20 0 26 LESLIE 39.2 170.4 105 131 +1983 12 17 0 9 ISAAC 50.4 25.2 109 241 +1986 1 24 6 7 TONY 18.1 130.8 51 617 +1994 5 24 0 20 TONY 47.4 283.1 61 475 +1953 2 11 18 20 NADINE 32.6 127.6 133 361 +1963 9 14 6 12 GORDON 55.8 92.8 163 253 +1977 4 3 0 9 VALERIE 61.6 247.8 97 488 +1998 12 20 18 16 SANDY 59.7 279.2 53 386 +1958 5 2 12 19 FLORENCE 31.5 68.1 35 276 +2000 9 11 6 27 VALERIE 20.8 199.7 125 334 +1981 7 8 12 5 MICHAEL 61.0 75.8 27 488 +1996 6 1 12 27 ERNESTO 30.7 344.9 56 638 +1956 11 14 0 15 WILLIAM 44.5 321.1 18 734 +1961 10 27 0 27 KIRK 43.8 46.7 26 613 +1985 5 25 6 22 BERYL 58.4 216.7 98 513 +1976 2 24 6 24 TONY 45.5 196.9 154 99 +1986 8 16 6 21 DEBBY 58.7 132.6 75 183 +1981 3 10 6 24 SANDY 54.7 273.6 105 205 +1977 1 24 6 27 RAFAEL 40.0 234.6 18 646 +1999 10 24 0 21 PATTY 31.2 0.5 161 519 +1998 4 12 18 21 BERYL 20.0 272.8 53 83 +1990 12 17 0 8 CHRIS 27.8 97.9 109 701 +1986 11 21 12 16 SANDY 19.3 31.3 147 84 +1968 1 10 6 16 DEBBY 36.2 168.8 158 159 +1975 8 26 6 25 ISAAC 9.5 305.1 56 164 +1998 4 14 12 9 TONY 16.0 137.6 35 117 +1988 8 3 0 17 BERYL 22.6 249.1 71 452 +1992 6 12 6 20 RAFAEL 57.5 70.7 116 620 +1973 4 7 12 4 VALERIE 54.0 36.9 79 293 +1963 1 7 6 6 JOYCE 12.4 211.6 42 225 +1996 9 16 0 20 NADINE 31.0 218.3 42 139 +1985 5 24 0 23 TONY 26.1 128.9 17 862 +1966 6 4 6 2 SANDY 53.2 264.5 88 157 +1971 4 17 12 15 OSCAR 68.3 274.3 24 836 +1984 9 13 12 1 GORDON 57.0 84.7 74 555 +1952 1 22 18 27 HELENE 66.1 251.9 115 610 +1984 6 5 6 19 FLORENCE 23.0 234.3 151 568 +1961 3 17 0 10 ALBERTO 14.2 235.5 22 839 +1964 8 5 6 9 FLORENCE 31.5 86.3 18 242 +1973 11 3 18 25 PATTY 60.4 300.7 113 512 +1967 4 28 12 10 WILLIAM 50.4 316.5 81 84 +1962 11 4 0 3 OSCAR 57.9 352.5 154 767 +1961 8 19 0 23 LESLIE 67.1 19.3 97 806 +2004 11 9 6 16 JOYCE 19.1 174.3 62 124 +1955 8 6 0 18 FLORENCE 67.0 277.0 65 330 +1974 1 18 18 8 KIRK 32.7 61.9 142 327 +1970 9 12 0 2 WILLIAM 67.1 29.8 108 824 +1979 11 16 0 16 HELENE 12.0 130.7 129 374 +1964 11 7 6 5 VALERIE 19.0 242.5 160 486 +1972 1 14 6 7 GORDON 31.3 192.4 120 525 +2001 7 19 6 11 ALBERTO 52.2 161.0 134 494 +1995 9 6 18 16 HELENE 52.3 56.1 104 210 +1961 6 6 0 18 GORDON 65.6 14.1 135 104 +1963 10 20 6 20 JOYCE 42.3 0.8 164 672 +1990 11 3 0 17 PATTY 58.9 250.1 66 716 +1990 8 21 12 19 ALBERTO 9.8 282.2 162 523 +2004 7 26 12 23 DEBBY 40.1 88.6 130 524 +1955 3 19 0 27 JOYCE 11.2 161.2 90 142 +1979 11 8 18 1 MICHAEL 55.9 12.9 135 334 +1979 6 18 18 26 MICHAEL 26.2 139.7 104 674 +1978 4 17 12 20 LESLIE 51.7 193.6 44 847 +1976 9 10 6 1 PATTY 19.4 150.9 40 819 +1957 2 11 12 16 MICHAEL 11.1 228.6 19 40 +1956 8 19 6 8 DEBBY 48.0 284.3 27 532 +1953 3 27 0 4 JOYCE 36.1 75.7 92 896 +1952 9 2 0 5 TONY 20.3 126.9 116 371 +1986 12 13 12 2 ERNESTO 52.6 316.6 135 75 +1988 7 14 12 9 ALBERTO 19.9 107.7 91 130 +1961 1 13 6 23 FLORENCE 18.1 310.9 19 531 +1988 3 15 12 8 ERNESTO 69.9 296.8 112 72 +1989 1 25 12 16 ERNESTO 29.3 356.9 43 143 +1958 10 9 12 15 WILLIAM 10.2 243.2 111 76 +1968 10 21 6 9 MICHAEL 57.0 334.7 66 114 +1995 5 11 18 6 RAFAEL 15.3 210.3 134 326 +1965 5 28 18 1 KIRK 58.2 13.2 68 311 +1995 6 10 6 28 PATTY 26.2 79.7 121 482 +1962 5 16 6 28 CHRIS 55.5 200.0 38 513 +2000 1 20 18 2 GORDON 25.9 255.9 157 694 +1975 6 22 12 27 RAFAEL 45.4 55.4 126 886 +1993 12 4 18 7 VALERIE 52.4 332.9 94 385 +1981 10 26 0 18 MICHAEL 19.5 138.7 35 650 +1972 2 6 12 10 PATTY 17.9 77.6 52 615 +1970 3 2 6 3 KIRK 52.1 60.4 142 181 +1981 8 8 18 24 FLORENCE 30.9 27.1 53 519 +1991 2 23 6 3 RAFAEL 61.5 130.5 17 688 +2004 7 21 12 23 ALBERTO 42.0 351.4 42 442 +1960 10 9 0 5 ERNESTO 44.1 212.4 111 24 +1988 8 7 0 10 MICHAEL 69.4 150.3 150 778 +1955 5 24 18 8 MICHAEL 15.2 306.1 163 769 +1954 11 15 0 12 FLORENCE 42.0 203.9 21 836 +1952 6 8 0 7 TONY 14.6 73.1 48 142 +1955 8 13 6 6 NADINE 18.8 21.0 142 452 +1984 4 18 0 18 JOYCE 66.4 204.4 51 2 +1964 10 1 12 15 SANDY 50.8 194.5 152 355 +2000 3 15 6 7 BERYL 19.9 26.4 121 157 +1960 12 8 12 27 MICHAEL 36.4 247.4 153 117 +1961 6 25 6 23 VALERIE 43.2 291.0 69 0 +1997 7 24 18 23 JOYCE 69.5 4.0 150 447 +1958 11 13 6 19 WILLIAM 19.8 325.5 120 724 +1980 3 28 12 5 RAFAEL 36.7 100.7 28 692 +1984 8 1 18 28 LESLIE 7.1 54.5 77 398 +1996 5 13 6 12 JOYCE 63.4 99.1 19 513 +1971 4 2 6 2 ALBERTO 61.2 130.3 163 609 +1977 11 27 18 18 JOYCE 66.4 321.8 120 112 +1980 11 16 6 15 LESLIE 46.2 144.8 15 885 +1958 10 26 12 7 WILLIAM 24.6 168.5 28 855 +1972 12 21 18 22 JOYCE 50.7 136.9 116 762 +1998 11 5 0 3 HELENE 48.4 133.3 89 515 +1967 8 18 6 22 CHRIS 14.4 316.3 23 660 +1969 12 3 12 16 ERNESTO 38.6 82.8 26 346 +1996 5 9 12 3 KIRK 29.6 325.0 51 37 +1954 7 18 0 19 VALERIE 57.7 178.7 83 175 +1969 12 11 0 13 DEBBY 45.3 205.1 56 323 +1994 9 25 18 20 RAFAEL 58.0 353.1 16 134 +1953 7 27 0 26 DEBBY 41.1 328.8 89 624 +1973 8 6 6 7 WILLIAM 68.9 32.9 152 336 +1992 7 14 6 10 MICHAEL 21.4 156.8 117 615 +1982 5 5 18 19 TONY 7.7 214.3 87 67 +2000 12 10 0 8 FLORENCE 32.3 95.9 142 310 +1978 3 3 18 17 GORDON 58.8 77.3 138 853 +1957 10 11 0 18 ISAAC 60.0 2.6 153 659 +1977 7 18 18 5 PATTY 9.7 264.9 21 427 +1975 9 15 12 3 DEBBY 18.5 232.4 151 268 +1952 2 2 12 10 NADINE 37.8 80.5 85 206 +1969 5 1 6 13 KIRK 15.5 232.8 104 812 +1961 5 11 12 23 BERYL 16.4 199.2 58 870 +1981 10 7 6 13 ERNESTO 58.9 341.8 162 742 +1956 10 14 0 1 DEBBY 37.5 277.7 93 765 +1983 2 27 6 14 MICHAEL 13.2 124.6 69 890 +2003 11 6 0 11 BERYL 45.9 164.2 131 194 +2002 7 27 12 15 RAFAEL 19.8 196.7 26 127 +1974 4 16 6 26 NADINE 31.5 97.9 72 778 +1978 4 8 0 8 KIRK 11.3 73.0 56 757 +1968 6 16 0 20 FLORENCE 17.7 306.8 79 583 +1982 3 13 18 3 ISAAC 41.2 18.7 164 76 +1992 3 7 0 16 RAFAEL 64.7 288.1 123 383 +1985 5 26 0 27 LESLIE 43.4 338.0 28 248 +1995 8 13 6 25 HELENE 51.1 341.1 160 668 +1986 7 26 0 7 TONY 11.8 306.1 74 29 +1950 10 8 0 10 GORDON 28.0 177.2 41 745 +1972 10 11 6 10 PATTY 60.0 91.7 111 503 +1958 9 12 0 6 ISAAC 59.2 341.1 100 642 +1990 12 17 18 24 ERNESTO 24.5 53.3 139 134 +1976 4 11 12 19 NADINE 42.8 183.3 158 412 +1959 3 19 18 4 SANDY 11.6 146.8 12 687 +1993 7 8 18 25 BERYL 7.7 203.8 50 433 +1950 11 23 6 12 ISAAC 58.9 109.1 133 605 +1966 6 24 6 8 JOYCE 31.8 25.0 101 203 +1992 10 6 12 17 VALERIE 59.8 9.9 71 230 +1978 11 12 12 19 ISAAC 15.0 315.5 42 578 +1950 9 16 6 17 CHRIS 50.6 284.6 143 197 +1990 11 13 12 9 BERYL 56.8 48.9 36 12 +2001 12 20 12 26 RAFAEL 46.7 36.8 77 544 +1978 11 20 0 13 DEBBY 38.1 271.4 120 723 +1981 3 13 0 7 RAFAEL 55.5 71.4 76 196 +1974 12 22 18 24 JOYCE 30.6 89.9 80 593 +1972 9 17 0 26 CHRIS 25.1 284.4 67 867 +1984 4 13 18 12 GORDON 57.5 296.1 112 546 +1957 2 2 6 25 MICHAEL 19.6 54.0 72 213 +1960 1 24 6 9 CHRIS 42.9 257.9 162 44 +1997 12 27 12 4 ALBERTO 53.5 192.4 47 650 +1997 7 28 6 10 TONY 32.7 197.9 63 857 +1963 1 3 0 22 TONY 45.7 326.7 105 128 +1953 7 16 6 28 GORDON 11.6 211.4 105 183 +2000 8 22 6 22 SANDY 36.1 326.1 63 631 +2002 6 4 12 25 SANDY 48.0 18.3 127 128 +1968 6 17 12 10 PATTY 65.0 3.2 68 502 +1954 1 4 12 2 SANDY 42.8 49.6 55 330 +1955 9 23 18 26 LESLIE 22.4 119.5 148 326 +1961 2 28 18 20 LESLIE 14.9 327.2 122 702 +2000 3 18 12 4 KIRK 39.5 289.2 100 568 +1957 8 7 12 20 ALBERTO 57.6 201.6 39 279 +1957 10 3 12 10 RAFAEL 51.9 304.2 51 197 +1983 5 16 0 27 KIRK 50.8 269.9 90 198 +1994 3 23 6 3 CHRIS 41.3 341.7 97 328 +1957 2 7 6 24 OSCAR 34.7 316.1 75 176 +1984 1 1 0 24 OSCAR 61.9 92.3 69 362 +1997 11 26 6 17 WILLIAM 37.0 274.2 131 17 +1997 3 14 6 17 PATTY 42.8 6.3 48 637 +1996 12 15 0 12 GORDON 32.2 218.3 25 79 +2000 2 27 0 3 RAFAEL 7.5 6.5 103 812 +1992 5 22 12 23 RAFAEL 36.8 117.5 150 885 +1985 3 24 6 23 RAFAEL 16.8 282.7 104 502 +1986 6 4 6 17 GORDON 68.2 144.6 148 376 +1977 8 20 18 22 DEBBY 65.2 176.5 54 378 +1997 11 18 6 14 CHRIS 64.0 78.2 71 494 +1990 5 15 12 4 OSCAR 57.9 242.4 148 42 +1989 4 3 18 3 CHRIS 51.1 157.1 119 456 +1992 6 10 12 20 MICHAEL 62.1 38.9 10 779 +1996 5 24 0 18 KIRK 47.0 264.6 142 381 +1984 7 26 0 18 ALBERTO 34.4 205.5 103 459 +1953 12 15 12 18 MICHAEL 18.1 232.2 164 797 +1979 5 3 12 26 ISAAC 22.8 37.3 154 462 +1957 9 20 12 3 SANDY 21.1 3.0 159 542 +1986 8 9 18 20 VALERIE 57.7 274.1 83 252 +1993 1 4 18 13 SANDY 61.7 104.9 50 644 +1981 10 25 18 6 ALBERTO 67.6 295.8 76 621 +1995 10 1 12 21 ERNESTO 40.2 106.0 15 241 +1955 1 28 12 21 GORDON 52.2 9.9 134 242 +1952 9 16 18 19 BERYL 40.6 74.9 139 420 +1987 4 4 12 22 BERYL 7.2 124.8 122 650 +1955 11 18 0 7 BERYL 42.1 22.1 153 647 +2001 9 18 6 9 SANDY 45.2 178.5 111 583 +1997 1 9 6 16 GORDON 63.4 154.0 77 28 +1996 6 1 6 8 LESLIE 22.1 1.5 115 112 +1995 8 15 12 1 RAFAEL 57.3 44.8 29 861 +1995 12 20 18 13 MICHAEL 13.3 51.3 40 855 +1987 12 16 12 18 RAFAEL 65.9 308.2 117 192 +1977 3 16 6 12 TONY 32.7 74.6 62 299 +1977 11 9 18 26 RAFAEL 18.2 345.5 120 548 +1996 1 3 18 5 SANDY 16.2 33.4 68 740 +1979 3 18 18 25 NADINE 66.3 155.3 47 660 +1956 3 21 6 13 DEBBY 66.7 28.3 152 642 +1972 2 10 0 16 PATTY 31.0 42.0 98 62 +1972 11 19 6 6 WILLIAM 39.2 74.6 67 496 +1996 4 4 18 12 BERYL 18.0 70.4 99 485 +1983 5 10 12 3 DEBBY 8.8 238.5 94 323 +1955 9 4 6 28 PATTY 68.9 69.4 64 754 +2001 2 2 18 5 WILLIAM 46.5 155.8 66 272 +2002 3 10 0 10 HELENE 50.3 240.1 99 347 +1969 5 24 6 21 CHRIS 61.4 186.9 127 660 +1970 5 9 0 26 KIRK 60.7 117.8 114 462 +1963 7 2 0 26 DEBBY 64.0 137.3 66 333 +1985 6 28 6 7 HELENE 8.4 68.9 107 893 +2001 10 21 6 7 LESLIE 7.1 314.7 15 551 +1950 7 7 12 22 SANDY 50.3 10.9 29 579 +2002 9 1 12 15 HELENE 13.1 6.5 85 120 +1986 9 3 12 14 NADINE 55.2 342.0 111 153 +1994 10 4 18 1 GORDON 21.1 134.1 123 77 +1969 10 1 6 3 FLORENCE 11.4 209.2 138 450 +2003 2 6 6 21 OSCAR 39.3 260.6 115 657 +1965 2 25 12 1 CHRIS 26.7 69.6 91 653 +1977 3 8 0 19 WILLIAM 21.8 286.4 99 316 +1970 9 17 0 6 ISAAC 64.8 72.5 149 148 +1954 3 1 6 6 CHRIS 58.8 99.4 115 206 +1964 9 3 0 5 ERNESTO 25.3 169.9 144 277 +1998 2 7 0 19 KIRK 24.6 343.4 34 520 +1999 1 25 6 19 TONY 22.4 343.3 38 530 +1990 9 3 0 10 DEBBY 55.5 290.0 139 857 +1987 7 14 18 4 HELENE 20.0 78.9 88 694 +1986 3 17 18 17 DEBBY 28.8 41.1 66 604 +2003 8 26 0 15 RAFAEL 29.3 171.4 74 249 +1990 7 11 12 23 OSCAR 27.0 246.9 54 764 +1995 4 22 18 3 WILLIAM 41.7 167.4 164 64 +1957 1 24 12 28 LESLIE 34.5 65.4 139 593 +1963 4 2 18 24 SANDY 25.8 37.9 157 813 +1998 8 6 0 13 RAFAEL 38.7 179.9 46 720 +1977 11 18 0 12 HELENE 8.1 219.5 162 202 +1995 5 11 6 13 DEBBY 9.4 308.8 135 604 +1977 12 2 6 27 PATTY 68.6 74.2 101 410 +1964 5 21 6 19 PATTY 34.2 106.3 86 507 +2004 1 19 12 20 PATTY 17.8 196.8 88 126 +1992 10 5 18 16 OSCAR 28.7 305.6 158 389 +1977 3 7 12 8 PATTY 68.9 141.4 154 135 +1982 4 19 0 13 RAFAEL 52.3 168.9 25 736 +1974 7 22 6 13 ISAAC 36.4 152.2 44 101 +2003 1 16 18 20 ISAAC 20.0 217.3 50 303 +1969 4 21 0 11 ERNESTO 20.5 285.7 102 647 +1990 4 20 0 17 WILLIAM 34.4 255.0 127 769 +1966 11 14 0 16 WILLIAM 58.2 224.7 92 854 +1969 5 3 0 27 WILLIAM 50.2 345.9 60 47 +2000 10 8 6 3 GORDON 61.6 272.9 12 875 +1997 9 3 6 21 SANDY 27.4 350.4 48 584 +1960 11 25 6 25 MICHAEL 35.9 207.8 114 24 +1990 1 8 12 21 FLORENCE 21.1 201.4 129 544 +1999 3 7 0 2 VALERIE 16.5 294.9 118 519 +1996 9 12 6 4 RAFAEL 65.6 26.6 121 810 +1953 9 8 0 25 HELENE 34.0 18.5 109 49 +1970 11 21 6 23 NADINE 8.7 178.5 67 531 +1957 6 4 18 7 DEBBY 16.1 212.4 30 706 +1990 7 1 6 25 KIRK 15.0 46.5 74 442 +1996 9 1 12 12 ALBERTO 17.7 280.9 64 130 +1961 5 26 6 9 DEBBY 39.4 98.5 40 758 +1958 11 14 6 5 NADINE 39.3 163.3 39 365 +1959 4 26 18 13 ALBERTO 18.8 219.3 142 438 +1994 4 21 0 27 BERYL 27.2 3.1 30 358 +1991 12 18 18 19 NADINE 48.1 87.1 30 41 +1978 2 21 0 4 VALERIE 52.1 241.1 55 149 +1986 9 1 18 17 OSCAR 41.6 343.5 30 13 +1950 9 3 12 3 DEBBY 46.4 278.4 81 410 +2004 3 28 0 9 ALBERTO 39.4 215.5 102 393 +1958 7 7 12 25 GORDON 50.8 95.2 124 873 +1978 3 23 6 3 NADINE 33.0 349.8 132 453 +2001 1 28 6 27 DEBBY 16.6 330.4 50 294 +1958 11 28 18 28 PATTY 37.6 135.5 18 209 +1982 4 17 12 27 NADINE 64.5 146.2 42 400 +1974 6 26 12 11 OSCAR 21.2 154.0 113 349 +1974 2 4 0 12 HELENE 59.9 243.9 91 409 +1983 7 17 18 6 FLORENCE 56.9 278.0 134 695 +1992 4 17 6 11 SANDY 63.8 140.4 104 689 +1950 3 27 0 21 JOYCE 48.1 332.2 147 43 +1963 12 25 12 24 PATTY 42.6 11.4 98 872 +1978 12 20 6 6 ALBERTO 44.9 127.3 127 533 +2002 10 15 18 24 LESLIE 24.5 15.0 96 308 +1975 2 28 18 12 ALBERTO 51.9 206.3 116 353 +1995 10 17 18 23 MICHAEL 29.1 157.4 68 861 +1957 10 27 6 25 ALBERTO 25.4 34.5 137 125 +1966 5 16 6 19 WILLIAM 50.7 82.9 161 806 +1967 2 14 0 5 RAFAEL 28.7 87.4 158 337 +1952 3 16 18 20 PATTY 43.3 22.9 98 759 +1964 12 24 18 19 WILLIAM 66.5 298.5 128 248 +1967 8 22 12 8 BERYL 21.4 299.5 47 540 +1957 5 17 0 26 KIRK 40.6 224.6 45 407 +1968 1 9 18 27 TONY 35.8 144.8 86 877 +1986 7 14 0 2 ISAAC 25.4 113.9 112 614 +1980 2 3 6 17 NADINE 58.1 145.9 41 779 +1979 2 11 6 19 MICHAEL 18.3 336.6 163 464 +1986 10 22 6 14 SANDY 60.5 177.3 133 477 +1967 9 5 18 6 JOYCE 38.6 348.1 104 438 +1954 1 24 18 17 OSCAR 37.0 209.8 84 666 +1950 1 13 6 2 FLORENCE 47.7 286.0 32 32 +1974 9 10 12 25 SANDY 10.0 353.7 33 31 +1955 9 12 0 10 NADINE 36.0 346.4 91 837 +1955 3 5 6 3 OSCAR 8.3 136.5 158 471 +1957 11 13 6 10 ERNESTO 26.5 214.4 148 67 +1962 11 10 6 17 NADINE 60.1 283.0 20 77 +1990 1 6 0 3 ALBERTO 58.7 226.0 27 70 +1970 10 3 18 2 TONY 11.5 326.3 131 468 +1971 2 27 0 9 TONY 47.2 102.0 39 371 +1979 6 24 0 25 LESLIE 48.0 69.1 72 55 +1990 8 10 0 12 NADINE 66.2 341.1 42 130 +2003 11 1 0 7 BERYL 15.4 347.1 139 75 +1997 9 22 18 11 BERYL 33.4 108.3 146 635 +1988 12 16 6 15 KIRK 44.0 300.1 41 240 +1979 6 18 0 12 BERYL 62.8 147.1 112 17 +1987 8 4 12 11 RAFAEL 37.2 201.5 17 364 +1974 11 3 0 22 TONY 37.6 107.9 94 696 +1970 6 22 0 23 ISAAC 39.7 353.0 164 547 +1997 5 10 6 23 RAFAEL 61.0 240.5 83 147 +1995 1 14 0 11 SANDY 25.4 18.6 90 882 +1986 6 11 18 24 BERYL 62.9 303.4 27 271 +1950 5 20 6 4 BERYL 69.5 262.7 77 348 +1955 7 4 0 28 ISAAC 37.8 202.8 64 267 +1978 8 11 0 3 WILLIAM 59.0 124.0 81 849 +1989 3 9 18 16 PATTY 29.9 167.7 131 272 +1987 7 3 18 1 NADINE 10.8 184.9 150 36 +1978 7 2 0 21 MICHAEL 35.8 339.7 96 768 +1965 6 8 6 17 CHRIS 49.5 285.9 139 425 +1986 5 5 12 10 CHRIS 22.5 210.6 62 765 +1989 9 23 6 15 ALBERTO 20.3 32.9 18 97 +1984 1 13 6 9 BERYL 17.8 352.8 122 111 +1970 1 19 12 21 LESLIE 36.0 310.6 127 388 +1970 7 15 6 8 VALERIE 24.2 309.9 25 566 +1974 1 15 18 28 BERYL 57.3 296.2 55 605 +1986 6 18 0 4 GORDON 50.0 10.5 152 804 +2004 5 20 6 19 KIRK 58.0 96.3 134 567 +1961 9 9 6 22 RAFAEL 27.0 302.5 118 827 +1997 2 12 12 12 VALERIE 12.7 244.1 30 507 +1987 8 15 12 13 RAFAEL 31.0 326.4 35 534 +1987 2 3 0 17 HELENE 20.9 299.7 99 227 +1957 7 11 18 4 NADINE 67.0 13.4 19 81 +1975 11 15 6 13 CHRIS 9.0 63.1 19 26 +1986 9 25 18 20 OSCAR 44.5 148.0 67 737 +1964 1 4 18 25 DEBBY 19.9 11.1 76 13 +1958 2 22 0 15 CHRIS 30.1 89.2 49 802 +1992 3 25 0 3 KIRK 25.9 79.2 123 662 +1985 4 8 0 26 KIRK 10.5 206.6 30 488 +2003 3 2 0 5 BERYL 53.6 185.0 106 407 +1967 4 20 6 1 ALBERTO 33.4 167.0 53 60 +1963 2 25 6 13 RAFAEL 27.7 146.9 28 118 +1964 2 9 6 16 OSCAR 27.1 267.6 142 201 +2002 1 14 6 24 WILLIAM 32.0 230.5 63 579 +1998 2 22 18 13 SANDY 57.7 176.0 131 800 +1983 4 24 6 8 OSCAR 32.3 135.1 64 208 +1970 6 27 18 8 KIRK 14.4 255.0 71 824 +1999 6 23 18 24 WILLIAM 56.7 317.0 45 516 +2002 7 11 0 14 MICHAEL 53.2 234.5 29 431 +1976 4 4 6 19 MICHAEL 7.2 305.5 55 632 +1962 7 3 6 22 SANDY 51.2 140.7 148 97 +1998 9 16 12 7 HELENE 10.5 343.5 114 161 +1976 11 3 6 10 NADINE 33.8 160.6 55 169 +1961 9 2 6 24 VALERIE 32.0 221.9 102 67 +1972 5 16 12 22 MICHAEL 12.8 69.8 70 151 +1976 8 14 18 15 ISAAC 52.4 62.3 128 755 +1973 9 22 18 16 LESLIE 44.8 261.9 99 482 +1972 9 12 18 3 ISAAC 18.6 84.3 82 830 +1957 11 23 18 4 JOYCE 65.3 212.6 128 691 +1954 5 18 6 11 BERYL 24.0 80.3 125 749 +1977 10 12 18 25 DEBBY 31.1 16.4 97 334 +1980 5 25 0 9 MICHAEL 17.8 198.9 149 580 +1958 1 25 12 19 ISAAC 43.1 218.7 96 172 +1957 6 8 6 2 KIRK 35.8 46.1 132 606 +2002 3 15 12 28 FLORENCE 36.2 67.0 153 765 +1965 1 11 18 3 VALERIE 52.7 345.6 108 425 +1956 5 15 18 12 WILLIAM 17.0 336.9 82 82 +1951 10 22 6 10 SANDY 35.9 155.0 97 48 +1976 8 21 6 24 FLORENCE 13.3 346.9 18 494 +1964 9 23 0 12 GORDON 60.0 228.5 122 359 +1971 1 16 18 17 VALERIE 38.3 90.6 155 257 +1963 11 26 0 8 TONY 11.5 82.3 149 107 +2001 11 9 12 14 TONY 43.9 306.4 48 254 +2000 9 17 6 17 ERNESTO 47.5 219.8 50 136 +1971 8 6 18 20 ALBERTO 14.8 118.3 50 597 +1975 9 17 12 13 MICHAEL 9.1 262.6 93 842 +1952 7 8 6 2 LESLIE 8.6 202.6 94 100 +1960 6 1 0 12 ISAAC 44.2 270.7 137 899 +1951 10 11 6 18 OSCAR 60.4 94.0 144 763 +1984 8 28 0 7 KIRK 42.3 180.5 88 260 +1984 12 12 6 18 CHRIS 45.5 158.0 73 624 +2003 9 14 18 27 NADINE 47.3 314.2 138 524 +1970 3 7 6 3 NADINE 7.7 214.7 54 117 +1987 2 18 0 5 RAFAEL 23.5 114.8 124 452 +1983 11 7 12 17 ISAAC 69.5 188.6 37 424 +1977 3 6 12 28 NADINE 62.9 272.8 55 176 +1964 9 6 0 2 HELENE 8.8 212.1 80 36 +1981 4 18 12 25 ERNESTO 12.7 287.2 33 540 +1960 8 17 12 28 DEBBY 11.2 321.8 153 435 +1972 7 17 12 6 KIRK 23.5 331.4 114 468 +1956 6 15 18 1 ISAAC 67.5 54.6 59 638 +1979 11 16 12 15 PATTY 37.9 35.6 31 784 +1959 1 9 6 8 JOYCE 34.8 0.3 128 832 +1970 4 24 6 24 ERNESTO 18.3 348.2 45 44 +1978 3 8 18 5 LESLIE 13.6 235.2 160 532 +1987 6 19 12 26 LESLIE 42.6 218.4 38 673 +1969 10 17 18 13 RAFAEL 36.4 45.0 63 108 +1953 11 23 6 26 ISAAC 7.2 343.4 130 140 +1982 6 21 0 8 ERNESTO 47.1 310.6 121 346 +1993 9 3 0 28 ERNESTO 49.3 169.1 44 841 +1980 10 10 0 18 RAFAEL 44.8 145.7 121 292 +1998 1 26 0 22 JOYCE 22.5 356.4 32 229 +1954 6 21 12 25 PATTY 54.0 267.1 162 842 +1973 2 2 0 6 SANDY 20.4 112.9 127 406 +1981 6 4 12 7 GORDON 49.3 115.8 51 654 +1983 7 24 6 23 FLORENCE 47.6 342.8 38 288 +1955 12 28 12 2 ERNESTO 56.1 211.9 60 550 +1981 9 20 0 4 NADINE 35.2 54.7 54 558 +2003 4 8 6 5 GORDON 50.0 258.5 58 230 +1952 9 1 12 28 MICHAEL 9.4 170.4 10 440 +1950 6 28 6 12 CHRIS 57.4 128.7 91 159 +1987 6 14 0 22 RAFAEL 65.1 321.9 37 80 +1979 11 7 18 26 BERYL 14.1 219.4 79 676 +1968 3 15 0 25 MICHAEL 48.9 341.1 46 480 +1999 4 17 12 15 WILLIAM 62.0 60.8 121 717 +2000 1 28 12 23 OSCAR 17.6 42.1 134 641 +1962 12 26 12 4 SANDY 64.2 166.4 47 844 +1955 9 18 12 5 BERYL 49.3 249.8 18 476 +1961 6 5 12 7 FLORENCE 26.5 33.6 139 74 +1985 6 3 6 1 TONY 37.9 290.2 155 820 +1978 12 21 6 11 HELENE 69.1 102.2 85 394 +1961 2 20 0 2 LESLIE 24.0 111.2 110 20 +1999 3 11 0 17 PATTY 66.3 161.9 35 432 +1964 11 13 18 12 WILLIAM 19.5 73.9 140 548 +1959 7 18 12 15 JOYCE 16.7 139.8 37 241 +1985 7 22 18 27 ERNESTO 18.2 350.0 147 59 +1961 12 16 0 16 TONY 32.6 113.8 20 607 +1988 3 26 6 19 GORDON 38.1 141.3 103 388 +1998 8 3 18 3 KIRK 68.1 52.1 95 818 +1998 10 25 18 28 CHRIS 20.8 297.0 45 816 +1952 5 21 6 2 ISAAC 42.0 332.6 132 845 +1994 11 10 6 18 WILLIAM 35.8 100.0 163 830 +1957 10 11 6 23 RAFAEL 14.9 274.1 90 481 +1966 10 22 18 5 BERYL 30.3 187.8 38 244 +1997 5 16 12 1 RAFAEL 34.4 119.6 136 589 +1969 11 8 18 1 TONY 42.5 44.7 128 620 +1982 2 13 18 3 KIRK 67.7 33.3 159 613 +2001 5 14 0 28 SANDY 48.8 300.9 107 668 +1982 3 10 0 6 HELENE 8.8 75.2 88 217 +1986 4 4 18 27 NADINE 53.4 207.0 53 149 +1980 6 28 0 28 TONY 18.4 145.1 79 524 +1956 2 22 18 27 PATTY 22.0 267.1 115 885 +1968 1 13 6 27 ISAAC 64.5 153.4 108 376 +1977 5 1 12 15 CHRIS 37.5 95.5 64 511 +1956 8 12 0 12 TONY 17.5 68.0 40 305 +1996 6 17 18 4 BERYL 59.5 69.0 135 153 +1958 5 13 6 21 HELENE 40.2 148.5 138 102 +1987 7 21 0 17 VALERIE 25.2 276.6 22 868 +1996 2 7 0 2 DEBBY 46.4 201.6 66 863 +1994 3 1 18 10 OSCAR 36.0 252.4 87 42 +1953 10 1 6 12 DEBBY 16.0 163.4 94 429 +2004 7 11 12 9 SANDY 52.5 325.2 143 301 +1993 11 17 6 28 VALERIE 32.2 323.4 149 576 +1962 11 26 6 26 NADINE 50.2 263.8 135 155 +1971 2 13 6 28 OSCAR 15.3 17.2 63 678 +1999 11 7 18 7 OSCAR 59.5 139.4 141 855 +1982 5 16 6 14 FLORENCE 66.8 217.8 49 686 +1985 12 21 6 2 TONY 16.7 10.7 35 146 +1988 3 27 18 23 ALBERTO 39.2 208.6 65 897 +2000 4 25 0 17 PATTY 23.7 121.0 41 773 +1969 5 13 6 8 VALERIE 38.0 305.3 164 523 +1951 4 13 12 22 VALERIE 52.3 273.5 155 261 +1952 1 25 18 19 OSCAR 39.0 95.1 152 588 +1998 6 22 6 24 LESLIE 45.1 19.4 147 530 +1999 1 4 18 12 GORDON 66.2 295.1 101 199 +1971 12 28 0 1 WILLIAM 10.5 89.3 42 436 +2003 11 27 6 11 RAFAEL 24.1 191.2 107 754 +1961 6 23 0 28 ISAAC 45.1 114.3 93 585 +1967 3 18 0 25 JOYCE 57.8 314.0 85 159 +1963 5 5 6 27 DEBBY 44.1 50.3 145 849 +1970 3 16 18 2 MICHAEL 63.3 124.3 150 566 +1957 2 27 6 21 VALERIE 43.5 109.2 23 562 +1974 7 25 6 5 WILLIAM 25.7 171.4 49 290 +1982 6 28 0 8 MICHAEL 35.7 74.6 59 168 +1976 11 27 0 28 OSCAR 16.4 200.2 69 740 +1982 10 3 12 20 DEBBY 37.3 71.3 154 108 +1996 9 9 18 27 FLORENCE 9.1 205.6 50 698 +1958 11 17 0 13 LESLIE 68.2 51.0 40 844 +1963 5 22 0 4 NADINE 26.1 343.1 42 721 +1961 11 1 0 17 TONY 16.2 44.0 77 538 +1953 5 8 0 16 ERNESTO 9.6 339.7 21 402 +1959 11 26 12 19 TONY 47.3 289.2 161 117 +1969 4 7 0 28 KIRK 14.9 231.3 128 474 +1997 7 16 0 12 ISAAC 50.3 259.6 93 641 +1953 9 2 18 25 SANDY 63.1 179.2 151 456 +1995 3 3 0 13 GORDON 47.1 26.9 129 765 +1976 4 5 12 16 MICHAEL 53.0 109.1 32 253 +1975 11 17 0 26 WILLIAM 15.9 162.9 17 634 +1965 2 8 12 12 VALERIE 42.5 335.9 121 326 +2000 9 21 12 14 GORDON 19.5 33.7 103 380 +1999 10 7 12 14 RAFAEL 28.8 259.6 23 802 +1982 4 2 18 28 VALERIE 28.3 33.9 146 650 +1970 8 27 6 4 ALBERTO 53.7 168.6 37 653 +2002 8 19 0 7 CHRIS 58.3 53.6 93 513 +1965 3 18 18 13 HELENE 53.3 15.9 59 347 +1965 10 28 18 26 NADINE 34.5 204.4 151 511 +1984 3 2 18 27 BERYL 28.5 134.2 31 528 +1995 1 24 6 17 ALBERTO 14.2 82.9 150 622 +1969 5 22 6 16 TONY 14.8 97.2 123 77 +1979 5 2 0 6 HELENE 32.6 345.7 119 421 +1980 2 26 18 22 BERYL 33.9 334.5 41 775 +1961 1 9 6 14 HELENE 20.9 14.4 41 250 +1999 6 26 12 26 NADINE 47.9 304.9 143 825 +1975 8 24 0 18 GORDON 32.4 182.3 94 776 +1981 9 26 6 22 LESLIE 49.1 157.4 50 616 +1989 4 25 18 9 JOYCE 9.7 334.6 140 271 +1981 6 28 0 18 ALBERTO 34.4 343.9 122 666 +1995 4 25 18 13 FLORENCE 57.5 166.3 43 700 +1965 9 25 0 4 ERNESTO 24.7 55.0 77 212 +1984 7 19 6 5 TONY 52.9 312.1 118 890 +1998 3 15 6 26 ERNESTO 31.5 206.8 83 497 +1990 12 4 6 7 TONY 43.5 71.7 113 559 +1968 4 24 0 21 HELENE 11.6 55.7 13 81 +1992 12 1 6 1 OSCAR 40.6 245.3 159 217 +1997 3 20 12 11 GORDON 58.6 232.8 71 402 +1999 9 4 12 27 SANDY 59.3 72.6 52 332 +1999 3 13 12 9 DEBBY 16.8 157.4 41 694 +1995 12 24 18 21 JOYCE 40.1 320.0 37 639 +1991 9 21 6 8 VALERIE 38.2 337.4 118 481 +1983 6 25 12 16 WILLIAM 11.1 99.1 109 526 +1951 9 18 0 9 BERYL 8.5 254.5 46 277 +1980 5 1 6 6 BERYL 55.8 1.8 53 578 +1995 7 4 12 22 ALBERTO 58.6 81.5 83 91 +1999 9 14 6 13 WILLIAM 54.9 265.6 154 453 +1953 8 6 0 23 TONY 49.4 269.8 10 682 +1974 3 27 18 5 SANDY 56.7 298.4 70 684 +1974 9 5 18 24 MICHAEL 51.6 27.2 28 167 +1996 5 20 6 3 ISAAC 29.2 161.0 132 695 +1973 2 16 6 18 ALBERTO 52.3 166.8 116 667 +1973 9 17 0 18 ERNESTO 10.0 212.8 95 265 +1959 6 9 18 19 RAFAEL 48.8 124.4 13 229 +1955 11 7 12 21 JOYCE 63.1 210.4 58 511 +1960 5 21 12 28 HELENE 59.7 163.6 53 766 +1955 2 14 12 4 FLORENCE 46.3 250.9 157 616 +1998 6 4 18 12 MICHAEL 43.0 227.0 107 754 +1959 2 14 6 9 DEBBY 25.5 27.8 159 857 +1953 9 19 12 3 OSCAR 20.6 207.4 39 790 +1994 9 18 6 4 FLORENCE 12.5 221.7 29 516 +1983 9 11 12 10 WILLIAM 39.0 187.9 153 101 +1982 9 4 18 3 GORDON 64.9 11.8 49 308 +1976 5 5 0 26 NADINE 49.2 246.4 137 55 +1972 9 12 0 27 BERYL 39.0 43.0 156 628 +1994 7 13 18 9 NADINE 37.7 289.3 15 247 +1963 2 26 0 28 CHRIS 10.5 197.2 120 121 +1994 12 25 6 5 WILLIAM 10.8 264.7 69 248 +1985 1 6 18 4 BERYL 18.5 247.7 51 435 +2004 1 5 6 24 GORDON 51.2 332.8 148 720 +1960 9 7 0 26 SANDY 45.2 237.7 70 167 +1970 2 17 0 2 TONY 65.5 30.0 112 836 +1959 5 8 6 12 LESLIE 48.4 69.3 133 104 +1995 10 9 18 13 SANDY 32.5 22.9 157 370 +1971 2 7 6 5 HELENE 64.0 208.3 37 115 +1955 6 12 12 22 MICHAEL 50.6 27.8 155 49 +1957 4 11 12 7 PATTY 22.8 9.4 14 689 +1955 5 4 6 21 DEBBY 56.8 273.5 122 728 +1981 5 3 12 27 GORDON 13.4 104.9 97 260 +1960 3 11 18 25 PATTY 46.9 160.8 141 581 +1957 5 17 0 1 WILLIAM 43.3 208.2 59 892 +1959 7 17 0 21 ISAAC 9.0 316.5 101 776 +1970 11 3 0 18 OSCAR 60.5 351.3 84 769 +1982 9 3 6 8 ISAAC 60.2 168.7 147 516 +1986 8 12 6 27 TONY 34.7 318.0 164 448 +1967 3 20 12 1 KIRK 28.4 161.9 52 2 +1984 8 1 18 2 CHRIS 31.3 61.8 18 239 +1958 3 5 12 15 DEBBY 10.7 56.8 148 292 +1983 5 13 12 3 DEBBY 45.9 294.3 81 233 +1989 6 9 0 5 KIRK 44.0 316.8 136 156 +1958 1 28 12 26 ALBERTO 16.7 66.5 163 479 +1967 9 6 18 18 ISAAC 66.0 48.8 15 96 +1985 4 9 18 7 MICHAEL 22.4 100.4 83 331 +1993 5 13 12 8 JOYCE 41.3 83.7 11 428 +1985 4 5 6 17 JOYCE 46.6 77.4 90 545 +1991 4 2 18 26 VALERIE 34.7 40.8 52 359 +1984 4 14 0 18 VALERIE 38.0 176.3 34 706 +1961 10 4 18 28 WILLIAM 24.7 356.8 143 107 +1961 6 19 12 24 LESLIE 51.2 351.6 114 488 +1978 11 20 0 3 ERNESTO 38.3 287.4 53 214 +1985 8 15 0 11 MICHAEL 29.8 19.3 40 633 +1973 12 3 6 18 LESLIE 52.2 309.5 40 628 +1976 12 16 18 2 CHRIS 45.1 31.6 114 755 +1956 5 12 6 7 PATTY 19.2 50.3 69 25 +1979 5 26 6 18 FLORENCE 68.0 298.1 86 341 +2000 6 22 18 6 RAFAEL 9.0 309.6 50 779 +1981 10 1 12 2 ALBERTO 63.7 171.7 91 505 +1992 9 7 6 18 ERNESTO 62.9 103.9 70 216 +2003 9 10 12 26 OSCAR 25.8 291.7 147 714 +1953 1 13 0 14 HELENE 58.1 41.6 129 256 +1974 4 4 6 20 PATTY 67.3 143.1 111 854 +1977 4 2 0 26 CHRIS 24.9 237.6 42 376 +1968 5 3 6 1 GORDON 14.2 167.1 118 28 +1988 9 1 0 4 NADINE 63.3 248.5 123 323 +1970 1 15 6 16 ALBERTO 58.7 227.2 80 69 +1988 4 4 0 21 MICHAEL 11.4 269.5 68 384 +1987 2 15 6 18 ALBERTO 17.7 337.8 68 636 +1976 7 21 6 11 VALERIE 31.4 117.5 59 357 +1959 10 28 6 15 LESLIE 14.5 273.7 77 396 +1986 5 16 6 16 ERNESTO 53.2 293.8 100 233 +1986 1 11 6 15 KIRK 55.5 187.2 13 395 +1962 9 22 12 9 VALERIE 66.1 338.0 102 17 +1997 4 25 6 2 ISAAC 63.0 87.3 143 767 +1972 9 18 12 3 LESLIE 28.3 103.2 47 879 +1965 11 21 6 13 PATTY 45.5 183.7 87 807 +1993 12 5 12 22 LESLIE 23.2 123.5 23 153 +1989 2 16 6 9 CHRIS 30.9 237.5 24 298 +1974 1 22 0 20 FLORENCE 22.2 281.6 85 358 +1961 8 1 12 19 ALBERTO 46.8 181.9 137 414 +1981 11 23 18 4 VALERIE 50.9 87.2 145 88 +1999 11 13 6 23 MICHAEL 46.7 140.7 80 12 +1991 9 17 0 24 NADINE 50.9 4.7 134 279 +1963 3 27 12 5 NADINE 23.9 215.9 118 50 +1987 1 4 0 8 FLORENCE 66.0 249.0 57 74 +1968 10 12 6 23 PATTY 49.9 234.1 44 790 +1976 10 24 18 2 DEBBY 25.2 293.8 46 440 +1993 4 16 0 28 ALBERTO 32.3 279.0 125 458 +1960 4 7 0 11 NADINE 34.7 114.6 66 307 +2001 8 3 18 21 GORDON 52.4 228.2 67 223 +1954 8 4 0 26 KIRK 62.9 260.3 63 350 +1997 6 17 12 24 JOYCE 48.1 31.1 97 165 +1977 12 22 0 11 HELENE 53.5 257.5 47 90 +1990 1 10 6 1 SANDY 62.0 245.5 115 164 +1993 10 14 18 17 KIRK 28.1 351.5 51 639 +1994 10 2 0 5 JOYCE 36.7 297.0 17 225 +1999 6 11 6 2 TONY 23.7 80.9 19 447 +1994 3 1 6 12 OSCAR 35.3 126.1 57 742 +1961 3 24 12 14 OSCAR 59.7 195.5 105 178 +1991 12 2 6 27 ALBERTO 30.6 171.3 147 357 +2001 10 25 0 16 NADINE 38.1 173.2 138 199 +1951 8 5 0 9 OSCAR 54.8 129.5 15 412 +1977 10 24 6 19 CHRIS 50.6 12.6 58 775 +1997 12 9 18 10 LESLIE 25.0 67.8 164 611 +1977 3 24 6 19 MICHAEL 30.6 315.3 89 303 +1955 2 12 0 4 DEBBY 26.5 23.8 26 753 +1955 10 22 18 8 PATTY 26.3 347.1 32 770 +1993 11 21 18 16 PATTY 40.0 86.4 138 843 +1975 4 20 12 5 BERYL 34.6 200.3 80 4 +1964 4 4 0 22 PATTY 57.8 175.7 12 202 +1956 6 6 6 1 GORDON 37.4 128.5 139 184 +1993 8 5 18 4 DEBBY 67.8 219.7 88 424 +1962 8 28 12 23 SANDY 27.7 221.7 132 655 +2000 2 19 12 22 OSCAR 21.8 122.9 127 61 +1987 8 7 12 3 JOYCE 66.9 132.4 103 116 +1989 10 17 0 11 FLORENCE 62.6 54.5 93 708 +1994 5 13 12 20 RAFAEL 28.7 330.9 132 86 +1997 12 1 18 27 JOYCE 65.5 174.8 121 56 +1961 7 2 18 20 DEBBY 19.7 72.7 98 75 +1958 6 26 0 7 DEBBY 42.9 13.6 100 679 +1963 10 2 12 14 PATTY 30.3 228.6 162 525 +2003 12 6 18 24 TONY 16.1 155.7 105 422 +1980 2 2 6 9 CHRIS 13.1 38.6 139 853 +1986 10 20 0 21 ALBERTO 37.9 329.7 96 154 +1977 9 22 0 4 OSCAR 39.3 19.4 137 770 +1959 3 15 18 1 BERYL 42.9 83.0 104 818 +1988 8 19 12 3 ISAAC 50.0 13.3 61 528 +1985 7 21 12 2 BERYL 8.1 24.7 146 284 +2000 8 11 12 28 LESLIE 37.9 167.1 49 377 +1991 9 13 0 6 NADINE 54.9 116.1 139 135 +1979 6 4 18 5 SANDY 62.0 296.0 145 261 +1967 11 8 0 14 ALBERTO 30.8 7.9 30 580 +2000 5 15 0 6 JOYCE 15.9 61.5 147 843 +1990 3 24 0 24 ISAAC 9.2 312.6 29 725 +1950 4 2 12 18 VALERIE 69.1 283.4 49 483 +1994 5 24 12 13 PATTY 38.4 283.7 107 525 +1981 4 14 12 20 RAFAEL 39.8 241.9 63 627 +1965 3 16 18 7 ERNESTO 65.9 346.9 74 200 +1992 1 27 12 14 NADINE 33.2 233.7 93 518 +1989 10 25 0 27 TONY 28.4 154.1 101 440 +1975 9 5 12 11 SANDY 19.9 239.9 17 348 +1960 12 28 18 13 DEBBY 63.1 61.6 11 621 +1977 8 25 18 14 WILLIAM 46.3 81.9 71 293 +1975 8 13 6 24 RAFAEL 54.1 184.3 123 764 +1990 12 12 6 9 MICHAEL 57.5 59.1 73 51 +1996 8 3 6 20 TONY 65.7 319.8 117 95 +2001 5 19 18 18 OSCAR 20.4 244.0 98 645 +1952 5 15 12 16 WILLIAM 23.5 314.7 132 725 +1988 6 28 18 13 WILLIAM 65.2 96.8 53 52 +1954 8 17 12 2 VALERIE 65.0 311.2 29 644 +1991 7 18 18 7 RAFAEL 53.0 257.1 100 474 +1965 5 15 0 18 CHRIS 10.8 137.0 47 522 +2002 10 9 18 24 CHRIS 22.2 10.7 120 214 +1957 6 18 18 26 BERYL 15.7 141.7 151 733 +1968 1 1 6 5 DEBBY 37.1 22.0 157 231 +1967 11 21 6 16 ALBERTO 46.6 251.5 133 826 +1954 6 22 18 17 WILLIAM 59.3 96.3 118 505 +1999 5 12 18 9 HELENE 8.3 84.0 23 659 +1955 2 25 18 15 ALBERTO 46.9 329.8 140 697 +1950 9 10 18 10 HELENE 61.3 282.0 129 103 +1955 2 21 6 25 KIRK 52.7 254.5 141 370 +1979 8 20 6 7 VALERIE 33.9 254.9 146 873 +1961 10 6 12 2 KIRK 48.0 274.8 20 166 +1981 8 25 0 28 JOYCE 52.0 128.7 36 632 +1991 7 22 12 15 ISAAC 40.8 332.8 49 23 +1980 9 7 0 11 DEBBY 69.9 165.7 118 724 +1971 6 17 18 12 MICHAEL 34.6 331.9 29 429 +1999 9 14 0 18 NADINE 49.0 212.8 111 618 +1989 2 17 0 13 DEBBY 16.3 191.9 155 256 +1995 4 19 0 20 BERYL 35.8 0.3 108 199 +1950 5 24 12 22 MICHAEL 63.0 186.8 77 336 +1955 10 18 6 26 ALBERTO 56.1 324.7 85 475 +1987 8 8 0 15 DEBBY 60.3 64.4 122 225 +1977 4 23 6 21 FLORENCE 8.2 283.5 130 61 +1951 9 28 18 25 HELENE 61.7 191.0 25 851 +1960 11 1 6 25 MICHAEL 47.1 268.4 139 219 +1975 12 13 18 2 NADINE 58.9 210.0 75 599 +1975 10 15 18 12 NADINE 34.6 306.6 150 271 +1991 6 21 0 23 DEBBY 54.1 312.4 126 272 +1991 5 9 0 17 LESLIE 33.0 73.9 153 296 +1997 12 18 6 14 CHRIS 25.5 138.8 150 186 +1962 3 16 12 2 RAFAEL 24.6 326.0 131 332 +1973 8 7 0 18 BERYL 43.1 329.4 116 487 +1953 5 23 0 2 FLORENCE 64.9 56.0 151 428 +1970 5 11 12 4 VALERIE 33.5 26.7 148 749 +1954 7 2 6 28 KIRK 58.2 338.9 40 131 +2002 8 20 12 14 FLORENCE 31.8 116.4 55 385 +1994 1 24 12 18 ERNESTO 60.2 25.0 155 802 +1962 3 23 0 13 ERNESTO 64.0 63.5 61 730 +1980 12 2 18 4 OSCAR 59.6 9.9 94 53 +1980 1 7 18 26 DEBBY 36.2 182.8 118 454 +1986 4 10 18 3 KIRK 41.2 55.0 82 464 +1972 5 7 6 25 SANDY 67.0 42.9 40 219 +1990 1 15 12 12 OSCAR 34.9 208.5 25 776 +1991 2 13 0 13 RAFAEL 68.5 247.7 162 555 +1981 3 24 18 4 GORDON 29.6 99.1 114 471 +2001 3 17 6 25 RAFAEL 15.4 213.4 119 354 +1972 6 13 18 17 ERNESTO 63.6 341.4 31 294 +1993 3 22 0 27 NADINE 69.8 64.6 28 350 +2004 5 10 6 14 ERNESTO 25.2 138.6 125 850 +1989 9 24 18 11 ALBERTO 53.5 249.3 106 696 +1967 8 2 0 3 RAFAEL 64.4 136.9 131 161 +1981 7 8 18 6 ERNESTO 65.2 139.5 133 487 +1985 10 23 12 21 ERNESTO 33.2 168.3 129 35 +1987 9 6 0 4 ISAAC 29.5 342.0 37 159 +1985 7 14 18 24 SANDY 66.6 95.9 161 495 +1951 10 2 12 22 JOYCE 30.0 305.6 78 394 +1978 8 24 0 5 ALBERTO 66.2 231.2 53 536 +1995 4 10 6 4 GORDON 31.2 1.7 138 83 +1954 8 1 18 22 DEBBY 33.6 157.2 21 709 +2001 8 16 0 12 NADINE 41.3 261.4 43 562 +1989 7 27 18 24 GORDON 11.2 56.1 105 862 +1975 5 10 12 1 FLORENCE 53.1 26.2 33 243 +2004 6 14 6 12 BERYL 52.4 148.0 124 301 +1951 12 6 18 27 LESLIE 59.3 89.2 68 52 +1998 5 1 18 3 NADINE 29.4 56.9 97 817 +1979 1 16 6 15 GORDON 36.9 29.5 72 354 +2003 5 22 18 20 SANDY 10.1 257.3 99 546 +1985 10 3 6 2 OSCAR 14.1 354.6 131 574 +1950 2 24 6 10 JOYCE 42.9 321.8 153 118 +1973 11 5 18 22 SANDY 42.9 297.5 125 700 +1990 2 26 0 12 ISAAC 61.8 118.6 87 785 +1991 3 6 18 20 ALBERTO 39.7 285.9 85 737 +1983 5 3 0 17 JOYCE 52.2 172.7 20 361 +1989 1 24 0 7 SANDY 58.3 354.1 40 136 +1969 4 12 18 14 KIRK 9.1 221.9 160 295 +1989 11 17 6 21 MICHAEL 49.6 343.5 116 663 +1987 3 10 0 18 LESLIE 7.8 355.8 88 780 +1962 2 15 6 25 ERNESTO 7.7 311.4 72 47 +1983 7 20 12 21 FLORENCE 54.5 6.0 57 620 +1970 8 11 6 12 PATTY 68.2 294.7 94 456 +1995 11 4 0 16 NADINE 53.4 226.2 20 582 +1979 9 22 12 28 CHRIS 44.4 288.8 55 175 +1962 6 9 0 7 WILLIAM 22.7 161.1 91 312 +1987 11 25 6 5 VALERIE 15.3 172.3 64 559 +1973 5 10 12 17 HELENE 67.7 180.4 72 664 +1978 1 24 12 21 LESLIE 7.9 20.5 63 509 +1952 2 17 12 15 ERNESTO 47.4 156.6 36 466 +2001 9 11 12 16 MICHAEL 21.1 285.5 21 607 +2003 1 16 6 23 KIRK 12.1 128.6 73 340 +1988 1 9 18 12 NADINE 51.7 53.1 113 6 +2002 5 27 6 12 DEBBY 60.8 120.7 39 62 +2000 9 8 18 28 BERYL 67.1 357.8 55 764 +1982 9 24 6 1 ERNESTO 51.2 47.7 72 360 +1952 10 1 6 3 JOYCE 28.7 68.3 114 817 +2003 11 14 6 15 ALBERTO 22.5 324.3 54 53 +1975 9 9 0 10 LESLIE 46.7 66.4 84 180 +1971 3 8 6 22 DEBBY 36.0 153.5 55 851 +1994 1 16 18 15 PATTY 47.8 54.2 95 717 +1953 6 28 18 27 RAFAEL 48.5 106.1 26 489 +1966 5 23 12 4 ERNESTO 8.3 95.5 25 295 +1955 11 5 0 7 ISAAC 65.5 181.8 159 891 +1960 2 17 12 17 NADINE 67.8 166.1 86 777 +1975 1 28 6 13 SANDY 25.1 77.9 30 105 +1957 2 22 12 14 HELENE 49.4 69.0 109 497 +1952 2 23 18 21 SANDY 39.0 229.6 121 381 +1953 2 2 0 6 NADINE 49.9 95.0 12 591 +1993 12 7 18 22 TONY 36.4 187.2 12 605 +1961 8 25 0 16 MICHAEL 62.5 8.9 71 635 +1990 12 27 6 11 DEBBY 42.6 260.6 144 219 +1979 10 27 18 8 MICHAEL 46.8 343.7 40 122 +1958 6 4 18 12 RAFAEL 47.0 124.9 151 623 +1957 2 5 12 24 OSCAR 26.9 279.9 33 153 +1988 5 25 12 14 RAFAEL 41.8 288.2 117 184 +1964 10 12 12 7 KIRK 66.4 62.0 157 492 +1989 2 10 18 14 ISAAC 27.8 310.7 47 739 +1998 5 7 0 9 BERYL 67.8 99.1 56 647 +2000 10 14 18 19 FLORENCE 53.4 18.9 134 603 +1959 7 9 6 19 VALERIE 14.7 131.3 25 87 +1963 7 10 18 14 FLORENCE 53.7 148.1 109 768 +1999 2 13 18 23 MICHAEL 37.6 321.4 108 751 +1997 11 18 0 21 WILLIAM 39.0 57.7 71 326 +1959 10 23 6 17 HELENE 20.5 254.2 87 564 +2003 7 13 6 10 MICHAEL 56.5 259.0 51 308 +1995 8 8 18 5 TONY 12.6 323.9 59 695 +1998 12 25 12 26 PATTY 24.5 141.0 70 304 +1967 1 23 6 11 LESLIE 68.9 32.1 131 337 +1978 11 9 12 11 LESLIE 21.5 168.6 107 389 +1965 8 12 6 7 NADINE 36.5 246.3 113 504 +1994 7 6 12 4 GORDON 22.8 89.8 80 317 +1966 2 24 6 16 DEBBY 34.8 296.8 89 798 +1953 10 27 12 6 ALBERTO 64.7 70.5 113 707 +1978 12 10 18 12 BERYL 29.1 175.9 102 882 +1968 5 25 0 7 PATTY 31.8 5.7 27 666 +1981 8 5 0 19 ALBERTO 37.2 44.9 46 307 +1974 8 24 6 8 OSCAR 51.9 183.1 92 84 +1963 4 15 6 25 ERNESTO 38.1 56.3 99 860 +1984 12 4 6 9 OSCAR 15.9 191.7 85 288 +2001 5 28 18 25 HELENE 22.4 331.0 84 870 +1967 3 7 12 27 ISAAC 59.5 78.6 108 200 +1976 10 24 6 11 OSCAR 37.0 328.0 27 307 +1967 2 1 18 28 MICHAEL 47.7 173.3 152 147 +1981 2 7 6 12 BERYL 17.3 340.7 11 858 +1979 12 18 18 17 CHRIS 37.1 247.4 88 784 +1972 6 21 18 1 VALERIE 66.9 265.8 41 542 +1951 10 11 12 7 HELENE 66.4 7.6 135 131 +1980 4 24 18 19 CHRIS 38.5 114.5 125 208 +1987 6 7 6 2 TONY 70.0 30.8 56 32 +1979 4 7 6 2 CHRIS 45.6 296.8 137 809 +2003 11 10 12 3 DEBBY 40.5 174.7 25 116 +2004 2 25 0 4 TONY 15.6 329.1 100 702 +1978 3 6 18 14 OSCAR 51.9 320.2 141 389 +1953 6 18 6 27 NADINE 38.4 280.3 110 531 +1956 9 21 6 11 PATTY 60.7 330.3 60 225 +1995 4 14 0 14 HELENE 48.4 143.2 45 732 +1983 12 5 6 14 RAFAEL 35.2 267.6 80 248 +1989 11 16 12 21 CHRIS 45.8 326.9 48 159 +1987 7 1 18 22 KIRK 62.6 164.0 29 98 +1950 5 8 12 2 TONY 65.3 356.7 154 672 +1956 7 7 12 8 NADINE 18.9 80.1 66 499 +1966 8 26 6 11 MICHAEL 12.8 250.3 36 15 +1976 4 27 6 21 JOYCE 68.7 272.2 128 46 +2003 9 20 6 6 PATTY 10.9 44.0 15 172 +1968 2 12 6 13 CHRIS 17.1 183.3 62 728 +1995 6 21 12 2 HELENE 68.3 213.3 164 396 +1956 3 18 0 5 TONY 32.3 261.0 80 757 +1958 7 8 0 26 KIRK 66.3 25.5 161 772 +1973 11 9 12 26 DEBBY 59.9 93.7 75 513 +1976 1 10 6 17 VALERIE 16.8 77.2 11 506 +1982 9 23 12 26 VALERIE 25.8 339.7 100 449 +1995 3 25 12 3 ISAAC 45.6 296.6 89 756 +1957 7 1 6 4 GORDON 61.1 303.9 146 146 +1983 9 20 12 4 CHRIS 42.0 60.7 73 34 +1969 8 6 0 5 HELENE 8.4 148.8 121 162 +1977 7 6 18 13 TONY 9.9 96.8 53 769 +1953 10 19 12 26 WILLIAM 25.0 58.6 97 380 +1965 6 2 6 22 SANDY 50.9 22.7 26 826 +1984 12 10 6 9 VALERIE 52.7 323.4 30 532 +1955 7 26 6 1 NADINE 28.4 169.1 147 233 +2004 7 13 6 15 HELENE 46.8 49.5 105 481 +1967 9 9 12 6 ERNESTO 29.4 75.8 32 199 +1980 11 10 12 26 KIRK 20.7 261.6 110 386 +1989 11 4 18 27 WILLIAM 58.9 75.8 64 682 +1977 12 26 0 4 JOYCE 32.4 203.0 156 240 +1990 1 22 6 25 TONY 56.0 278.4 143 16 +1983 2 11 6 2 CHRIS 11.7 209.1 139 600 +1961 4 4 0 17 TONY 42.6 78.6 96 744 +1985 8 3 0 14 ERNESTO 47.6 143.6 152 257 +1972 2 17 12 19 BERYL 30.1 303.0 89 790 +1966 10 9 12 16 PATTY 12.2 215.2 87 612 +1999 8 14 12 19 ISAAC 42.0 163.5 77 335 +1951 9 19 6 18 FLORENCE 13.8 259.9 23 383 +1977 12 2 18 5 WILLIAM 45.2 299.4 104 601 +2000 10 10 12 1 WILLIAM 35.3 288.2 147 780 +1983 2 16 6 2 BERYL 60.2 357.8 35 519 +1966 6 7 0 20 ISAAC 28.0 133.3 23 769 +1996 8 10 18 19 NADINE 50.9 287.5 71 488 +1977 7 15 12 9 OSCAR 18.3 287.1 50 844 +1960 11 25 6 6 ALBERTO 33.8 113.3 119 160 +1985 10 9 0 24 DEBBY 41.9 205.1 34 601 +1979 10 15 6 26 RAFAEL 52.1 313.6 13 806 +2000 6 25 12 5 LESLIE 11.9 39.4 87 778 +1954 4 9 12 28 PATTY 15.6 56.7 157 335 +1982 2 18 6 4 MICHAEL 32.1 34.2 79 197 +2004 12 24 6 7 TONY 42.6 225.2 148 608 +1961 5 7 18 10 PATTY 42.7 145.4 125 170 +2000 3 26 18 20 SANDY 7.3 291.0 152 100 +1958 12 16 12 24 SANDY 35.8 202.3 85 21 +1977 11 15 6 26 VALERIE 19.1 13.5 86 586 +2000 9 21 12 17 OSCAR 41.4 272.8 122 345 +1961 6 11 18 2 FLORENCE 9.6 175.9 163 853 +1973 10 26 0 11 MICHAEL 57.5 204.5 70 434 +1950 4 8 18 7 JOYCE 62.5 317.4 75 308 +1985 6 25 0 14 JOYCE 9.6 353.0 31 273 +1989 5 20 12 11 NADINE 43.8 341.1 103 701 +1974 1 7 0 4 CHRIS 17.4 74.5 119 489 +2002 2 11 12 12 MICHAEL 20.4 80.2 19 322 +1985 6 3 0 9 CHRIS 69.1 152.2 55 734 +1972 11 27 12 12 PATTY 13.0 241.2 12 262 +1970 12 15 6 14 NADINE 51.5 93.1 109 637 +1991 1 8 18 25 ALBERTO 48.4 114.4 35 777 +1968 8 20 0 21 ISAAC 38.6 38.2 103 23 +1987 4 7 6 7 LESLIE 8.5 124.0 69 269 +2003 3 12 0 18 RAFAEL 13.2 320.3 27 263 +1966 2 26 18 14 PATTY 58.8 60.0 20 58 +1990 10 25 18 27 WILLIAM 68.1 128.1 62 290 +1989 8 21 12 1 TONY 11.9 204.9 14 309 +1979 5 4 18 6 FLORENCE 32.5 216.7 48 825 +1995 12 26 0 13 KIRK 68.3 349.9 86 34 +1965 5 8 6 11 TONY 65.6 22.3 110 381 +1974 10 9 12 12 ISAAC 33.9 60.7 119 334 +1998 9 15 0 20 MICHAEL 8.9 8.0 74 831 +1985 6 14 18 4 MICHAEL 20.3 51.1 160 422 +1955 12 25 12 25 BERYL 40.1 117.2 128 606 +1990 7 24 6 9 RAFAEL 17.4 182.6 112 525 +1970 3 8 12 12 RAFAEL 67.4 165.9 31 55 +1985 11 15 18 27 HELENE 41.7 328.8 105 820 +1953 2 23 0 24 OSCAR 23.9 208.2 78 365 +1957 10 1 0 19 SANDY 65.3 140.6 158 582 +1969 9 1 0 18 GORDON 45.8 265.1 11 464 +1966 9 12 0 25 SANDY 36.3 205.1 154 344 +1966 5 7 18 15 NADINE 16.6 148.5 151 89 +2000 7 9 18 14 HELENE 38.1 331.6 10 36 +2003 10 10 0 12 PATTY 30.9 346.2 39 205 +1996 7 8 0 16 ISAAC 46.4 30.6 152 605 +1980 2 2 6 1 ERNESTO 65.4 114.4 144 469 +1986 5 16 12 8 MICHAEL 16.9 144.8 80 150 +1950 5 8 6 19 GORDON 41.6 207.1 135 801 +1956 10 13 18 8 DEBBY 24.3 34.4 108 175 +1987 6 6 18 21 PATTY 9.4 42.3 32 466 +2004 7 22 18 23 GORDON 22.9 135.4 118 711 +1980 12 19 6 5 OSCAR 8.8 136.3 114 858 +1985 7 13 6 4 LESLIE 67.0 177.0 48 143 +1995 9 3 12 14 RAFAEL 64.2 294.1 110 548 +1961 12 26 12 13 DEBBY 61.7 165.8 143 730 +1989 12 4 6 25 TONY 58.3 56.4 88 195 +1954 4 10 12 24 OSCAR 61.8 209.8 100 204 +1997 4 15 0 13 LESLIE 11.2 282.3 57 892 +1984 10 28 18 28 VALERIE 11.0 342.2 118 679 +2003 7 3 0 11 WILLIAM 12.0 189.7 155 47 +2000 11 8 0 17 JOYCE 19.0 213.5 160 480 +1951 7 11 6 3 OSCAR 30.8 292.5 122 778 +2000 8 6 12 26 PATTY 36.3 99.1 64 816 +1961 2 26 18 6 GORDON 52.3 261.1 77 18 +1991 12 2 0 10 TONY 59.4 303.7 144 420 +1997 2 1 6 19 NADINE 54.1 174.3 84 667 +1972 5 14 12 3 LESLIE 51.7 163.5 103 236 +1953 10 22 0 7 ERNESTO 22.8 189.4 27 295 +1970 6 17 0 28 TONY 25.6 290.7 55 338 +1993 10 9 18 20 LESLIE 27.8 88.8 129 766 +1972 10 6 6 15 OSCAR 27.9 209.2 126 839 +1951 8 6 6 4 PATTY 28.8 200.0 104 731 +1994 7 20 6 27 NADINE 37.5 340.7 71 884 +1973 10 6 12 19 PATTY 68.8 305.8 79 0 +1966 4 25 6 15 ERNESTO 45.0 96.9 56 131 +1967 2 3 12 11 PATTY 26.5 38.0 153 70 +1991 2 23 12 1 TONY 67.2 302.7 81 812 +1967 4 9 12 24 MICHAEL 57.3 227.5 121 841 +1950 6 27 6 18 LESLIE 11.0 312.1 101 602 +1983 5 17 12 16 GORDON 36.4 142.8 91 630 +1968 5 15 0 16 ERNESTO 12.1 6.9 41 263 +1968 11 27 18 13 VALERIE 14.5 218.7 90 616 +1951 11 6 18 22 NADINE 66.9 198.3 135 487 +1976 6 16 12 5 PATTY 59.6 251.2 145 419 +1972 8 9 0 14 VALERIE 66.7 255.8 131 334 +1991 8 22 6 3 VALERIE 49.8 17.0 156 222 +1957 7 13 6 11 GORDON 44.8 214.8 103 829 +1979 4 20 0 1 JOYCE 67.5 281.5 158 266 +1979 9 9 18 25 ISAAC 20.1 119.4 152 837 +1987 12 24 18 4 GORDON 17.9 260.6 126 373 +2004 7 16 18 16 ISAAC 59.8 160.5 72 458 +1979 11 21 6 25 MICHAEL 48.8 251.4 137 769 +1972 7 9 18 18 TONY 10.5 254.1 136 789 +1974 9 2 0 27 DEBBY 38.3 119.4 23 675 +1984 9 3 18 15 MICHAEL 32.4 180.5 72 867 +2000 6 9 6 1 JOYCE 14.1 62.1 136 742 +1971 11 3 6 6 DEBBY 21.2 167.6 159 95 +1980 2 5 12 22 FLORENCE 12.6 271.2 71 826 +1956 10 17 6 18 RAFAEL 53.7 89.3 94 678 +1993 5 22 18 28 MICHAEL 50.9 50.8 22 181 +1952 7 15 0 12 DEBBY 8.7 155.0 28 451 +2003 5 26 18 27 RAFAEL 27.0 63.5 124 24 +1963 10 27 6 8 OSCAR 26.0 15.9 79 512 +1990 8 18 0 11 NADINE 68.7 151.4 69 213 +1984 6 18 18 13 WILLIAM 59.8 255.5 74 660 +1994 7 22 6 9 BERYL 21.9 192.7 91 524 +1977 7 9 0 16 JOYCE 55.1 246.0 110 366 +1970 12 9 18 14 FLORENCE 22.1 286.4 122 210 +1951 2 1 12 5 RAFAEL 50.3 248.7 93 417 +1973 4 8 6 23 BERYL 7.0 185.8 121 196 +1957 12 6 0 13 ISAAC 7.0 47.7 43 441 +1956 11 12 0 14 FLORENCE 28.5 242.9 48 650 +1989 2 4 18 21 RAFAEL 26.1 90.1 140 727 +2004 10 12 18 21 GORDON 26.5 28.4 76 98 +1996 10 4 6 7 SANDY 32.8 202.5 52 866 +1989 11 25 0 20 FLORENCE 41.6 231.7 68 497 +1991 1 17 6 8 LESLIE 58.6 97.7 29 500 +1977 1 20 6 24 RAFAEL 44.3 127.6 20 62 +2001 8 28 0 27 OSCAR 44.9 208.0 10 866 +1962 1 23 0 15 FLORENCE 16.3 347.4 16 662 +2004 12 8 0 8 TONY 17.6 83.6 125 725 +2001 10 9 12 16 CHRIS 31.6 338.5 144 615 +2004 11 6 6 10 VALERIE 46.3 177.9 44 782 +1957 5 26 6 2 SANDY 34.9 9.6 89 428 +1988 5 3 18 12 CHRIS 36.3 97.0 93 419 +1987 6 10 18 12 NADINE 62.7 198.3 25 836 +2000 1 6 18 11 BERYL 11.9 306.7 10 145 +1987 3 10 6 6 MICHAEL 67.2 100.6 37 143 +1975 2 2 18 28 MICHAEL 23.1 228.9 48 310 +1989 2 8 0 5 VALERIE 69.8 337.5 25 834 +1997 6 16 6 12 NADINE 52.2 193.5 154 759 +1951 11 22 6 11 JOYCE 29.2 220.2 46 48 +1994 6 4 0 13 TONY 49.3 264.0 109 864 +1986 9 9 0 11 ERNESTO 37.0 63.9 114 752 +1954 6 17 12 21 OSCAR 47.8 314.1 14 74 +1991 4 17 12 26 VALERIE 35.9 89.6 37 601 +2003 5 25 0 21 JOYCE 37.5 128.5 125 551 +1970 9 19 0 6 RAFAEL 27.7 45.9 91 602 +2003 4 25 0 7 TONY 70.0 168.0 115 750 +1951 1 18 12 22 ERNESTO 46.1 357.9 47 280 +1981 6 24 18 28 RAFAEL 52.7 352.7 128 636 +1991 8 6 6 26 ALBERTO 44.0 42.1 124 839 +2002 4 2 18 28 CHRIS 31.4 221.3 109 860 +1991 3 2 6 9 FLORENCE 10.3 304.5 28 59 +1970 6 16 12 24 LESLIE 13.6 213.3 164 24 +1961 8 2 18 27 BERYL 10.4 86.2 81 117 +1969 4 26 12 10 HELENE 12.5 60.1 130 891 +1981 9 23 0 12 VALERIE 58.6 254.2 87 218 +1953 2 20 6 3 NADINE 21.2 305.1 30 861 +1996 8 11 6 17 SANDY 51.9 278.3 125 505 +1999 9 28 6 20 VALERIE 33.4 167.2 19 51 +1987 11 23 12 26 FLORENCE 30.0 53.2 103 11 +1953 2 15 12 17 BERYL 40.4 26.4 34 493 +1988 10 5 0 24 OSCAR 12.7 285.8 40 1 +1957 5 9 6 27 OSCAR 22.5 269.5 117 717 +2001 6 7 6 1 DEBBY 53.4 200.4 22 808 +1954 7 19 18 5 SANDY 52.5 124.1 36 530 +1982 4 22 12 14 MICHAEL 49.7 311.7 61 655 +1958 10 7 12 25 TONY 13.9 17.4 83 48 +1987 5 19 0 13 JOYCE 39.0 181.9 90 427 +1985 9 25 0 11 NADINE 21.7 43.7 156 127 +1961 4 8 12 25 RAFAEL 65.5 93.7 56 783 +1975 11 18 0 27 CHRIS 17.5 193.3 57 831 +2000 12 11 6 18 BERYL 27.7 59.6 115 727 +1977 12 8 12 1 FLORENCE 34.1 106.3 25 172 +1984 10 24 0 1 ALBERTO 43.3 277.3 140 112 +2002 4 12 6 28 DEBBY 32.7 60.6 49 204 +1967 3 12 12 1 GORDON 69.1 49.7 78 347 +1968 9 6 0 11 FLORENCE 67.9 6.9 95 83 +1976 11 3 6 8 JOYCE 17.6 202.6 64 125 +1962 12 26 6 9 LESLIE 39.9 266.0 98 47 +1964 6 16 12 22 FLORENCE 14.7 191.5 148 814 +1996 5 14 18 21 ALBERTO 22.3 250.0 83 542 +1956 9 28 0 19 SANDY 60.7 180.9 136 615 +1973 2 26 18 26 ISAAC 15.4 9.7 133 400 +1968 11 3 18 12 PATTY 65.6 270.3 145 736 +2004 2 1 0 13 GORDON 50.5 214.1 138 753 +1985 7 18 0 6 ISAAC 57.9 54.8 152 873 +1997 1 28 12 18 PATTY 36.2 193.5 34 551 +1970 5 1 18 26 PATTY 27.9 310.6 30 563 +1971 6 8 18 13 SANDY 55.9 330.0 61 192 +1989 2 20 0 5 VALERIE 48.4 343.2 80 824 +1952 3 11 12 25 FLORENCE 10.3 21.5 114 777 +1951 5 18 6 1 ERNESTO 43.7 200.7 155 822 +1986 11 2 18 7 GORDON 11.0 44.2 55 346 +1989 11 28 12 3 DEBBY 20.1 245.1 18 324 +2002 12 3 18 12 VALERIE 47.0 109.3 136 29 +1956 8 25 6 14 JOYCE 47.9 216.9 34 321 +1985 5 15 0 10 PATTY 24.8 139.5 113 142 +2000 5 7 12 1 MICHAEL 50.0 52.5 85 137 +1962 8 20 12 6 ALBERTO 10.8 351.7 53 890 +1955 12 2 0 10 GORDON 32.1 102.8 160 160 +1985 7 28 12 10 GORDON 48.6 348.9 34 307 +1958 8 2 0 6 NADINE 38.1 149.1 42 560 +1960 7 18 0 12 GORDON 62.1 57.9 113 211 +2001 7 13 12 13 DEBBY 31.1 260.4 41 469 +1974 7 4 12 15 JOYCE 16.9 342.3 79 663 +2000 8 9 6 5 KIRK 52.1 111.0 108 570 +1968 9 10 6 9 KIRK 13.3 101.0 103 829 +1957 10 8 0 22 GORDON 40.5 205.5 22 477 +1989 2 26 6 7 RAFAEL 52.1 234.7 110 276 +1981 11 8 6 24 RAFAEL 66.4 20.7 152 251 +2004 5 25 18 13 ISAAC 28.1 37.9 23 137 +1960 2 1 6 11 SANDY 7.3 191.0 97 421 +1983 8 22 0 21 ISAAC 50.4 215.7 76 285 +1959 12 11 0 21 KIRK 42.7 23.7 149 808 +1986 12 1 18 13 VALERIE 31.9 263.3 99 570 +1981 7 14 0 27 HELENE 56.4 314.8 67 639 +1983 3 5 6 28 TONY 34.1 160.9 17 722 +1984 2 25 6 12 WILLIAM 14.6 135.3 139 232 +1969 5 5 12 20 JOYCE 63.3 224.4 40 214 +1951 10 24 18 3 JOYCE 7.5 199.4 145 444 +1950 11 16 12 19 TONY 66.9 215.6 65 817 +1976 9 17 6 19 BERYL 45.7 329.8 145 243 +1982 8 14 18 22 ISAAC 21.5 298.9 110 612 +2004 4 11 6 22 JOYCE 35.4 14.5 72 768 +1950 2 27 18 1 ISAAC 39.8 5.5 28 220 +1957 9 27 18 20 SANDY 44.3 87.6 31 427 +1961 12 4 6 10 SANDY 35.4 163.4 73 659 +1972 11 26 18 16 RAFAEL 60.9 220.0 127 861 +1965 12 9 6 6 ISAAC 46.7 338.7 76 381 +1953 5 18 0 25 BERYL 63.0 215.8 56 258 +1977 3 23 0 4 OSCAR 18.5 185.1 46 559 +1989 8 25 18 24 ISAAC 59.2 0.7 37 582 +1991 4 3 18 16 ISAAC 40.4 121.2 149 62 +1968 8 6 18 3 ERNESTO 46.9 258.9 115 823 +1974 3 20 18 9 JOYCE 56.6 180.0 45 481 +1951 5 23 6 1 JOYCE 38.4 73.3 149 857 +1952 5 15 6 16 WILLIAM 45.1 311.3 101 362 +1963 10 23 0 23 FLORENCE 38.7 115.9 42 214 +1996 6 1 12 3 ALBERTO 47.3 203.3 75 618 +2000 3 23 12 10 BERYL 68.0 185.8 141 253 +1986 7 26 6 10 JOYCE 21.6 54.9 137 894 +2000 10 11 6 8 FLORENCE 55.8 316.8 143 559 +1954 12 20 6 2 TONY 47.1 164.5 120 719 +2003 10 13 12 21 FLORENCE 26.0 40.3 133 195 +1997 3 4 6 24 GORDON 22.9 196.6 147 854 +2000 3 4 12 18 NADINE 40.7 278.2 18 894 +1995 3 6 0 18 FLORENCE 7.5 335.8 139 714 +1999 6 25 0 22 WILLIAM 29.0 218.3 12 319 +1988 2 28 0 19 SANDY 59.4 352.9 29 811 +1981 10 12 18 12 CHRIS 67.3 126.1 110 243 +2002 10 14 0 3 SANDY 58.0 235.8 54 276 +1977 11 7 6 11 FLORENCE 55.1 266.6 75 86 +1969 11 26 18 9 MICHAEL 61.1 148.0 55 695 +1990 11 16 6 1 GORDON 16.4 51.6 29 327 +1974 11 10 18 11 OSCAR 14.0 203.5 144 405 +1994 2 1 18 21 FLORENCE 57.3 166.2 95 409 +1978 4 9 12 12 LESLIE 64.7 243.2 71 534 +1985 6 26 12 21 KIRK 48.2 307.1 19 657 +1985 9 27 18 23 OSCAR 33.2 177.3 58 367 +1951 7 20 6 22 DEBBY 33.2 239.3 132 61 +2001 6 20 12 6 TONY 15.3 271.0 125 228 +1967 3 15 6 4 WILLIAM 7.9 299.6 82 18 +1987 3 17 0 8 TONY 66.2 214.7 81 335 +1956 2 20 0 4 DEBBY 14.4 340.0 122 659 +1977 2 17 12 26 LESLIE 69.1 286.6 140 899 +1961 2 16 6 14 FLORENCE 56.6 125.9 139 326 +1977 8 15 6 7 NADINE 44.3 337.6 53 794 +1985 3 27 18 8 TONY 42.9 285.7 91 397 +2003 12 21 12 16 JOYCE 58.5 39.3 107 69 +2004 2 2 0 14 HELENE 62.3 345.7 146 881 +2002 10 8 18 20 CHRIS 16.7 185.6 140 40 +1986 10 5 0 1 ERNESTO 49.9 78.1 129 795 +1962 12 20 18 5 RAFAEL 44.6 268.3 49 653 +1962 5 25 18 10 HELENE 13.0 116.5 60 747 +1954 6 11 0 5 GORDON 58.0 285.2 59 414 +1990 11 23 12 22 WILLIAM 60.5 293.8 96 152 +1956 2 20 18 6 PATTY 58.2 52.0 120 35 +1994 3 6 6 14 ERNESTO 30.8 322.9 10 326 +1974 12 2 18 28 RAFAEL 15.1 274.8 88 530 +1992 11 22 18 12 KIRK 36.8 352.8 96 855 +1975 4 25 12 13 GORDON 67.1 157.7 80 655 +1995 12 4 6 14 DEBBY 15.4 330.1 161 153 +1951 5 25 12 12 OSCAR 17.6 113.9 144 156 +2004 9 1 12 11 BERYL 64.3 10.0 54 804 +1977 7 27 12 27 LESLIE 10.5 270.1 70 295 +1978 8 14 0 6 KIRK 9.6 313.8 143 83 +1957 4 7 18 28 ERNESTO 38.1 212.4 79 550 +1964 10 14 12 10 RAFAEL 68.6 79.6 42 254 +1990 2 19 6 15 RAFAEL 54.3 269.2 157 619 +1961 3 15 0 17 ISAAC 46.4 113.3 15 502 +1964 4 16 18 27 GORDON 57.4 314.6 125 280 +1956 6 16 0 21 ISAAC 57.6 19.1 70 459 +1955 1 23 12 25 JOYCE 15.9 301.1 153 874 +2001 3 21 18 7 OSCAR 33.7 341.9 155 873 +1974 3 15 18 16 HELENE 37.0 171.9 140 759 +1995 5 22 0 25 BERYL 28.6 64.6 44 259 +1971 5 27 6 12 GORDON 34.1 273.1 57 854 +1970 10 20 12 23 JOYCE 26.0 355.4 89 523 +1984 11 5 6 10 ISAAC 54.5 137.4 130 860 +1992 9 13 12 13 BERYL 18.3 273.6 96 353 +1970 5 17 12 15 ERNESTO 62.4 176.1 126 143 +1966 9 28 12 11 BERYL 23.0 304.0 110 597 +1952 8 14 6 8 DEBBY 7.8 348.8 164 574 +1972 2 2 6 7 SANDY 38.5 87.6 96 379 +1967 2 17 6 5 LESLIE 12.1 117.2 129 222 +2003 10 2 0 21 HELENE 26.4 299.1 72 453 +1961 5 22 18 9 MICHAEL 53.6 1.8 24 422 +2001 2 17 12 6 OSCAR 29.9 334.7 21 861 +1969 10 1 12 19 OSCAR 52.5 7.4 98 229 +1979 3 27 12 3 FLORENCE 7.3 275.1 57 386 +1975 8 9 0 14 KIRK 8.0 322.8 37 698 +1959 10 19 0 7 FLORENCE 22.3 312.2 98 478 +1982 7 28 0 16 HELENE 38.1 100.4 114 751 +1985 8 4 18 14 NADINE 61.2 6.9 158 461 +1970 2 1 12 1 MICHAEL 30.8 327.5 33 644 +1986 12 19 6 16 KIRK 44.7 260.8 48 173 +1971 11 18 12 27 ALBERTO 36.9 331.9 131 626 +1951 12 7 18 21 DEBBY 64.5 182.9 75 221 +1963 5 15 18 12 GORDON 21.5 286.0 21 479 +1993 10 16 0 14 JOYCE 39.7 253.6 152 73 +1953 11 25 0 21 RAFAEL 9.8 346.6 156 379 +1976 5 19 0 15 GORDON 35.9 2.1 66 361 +1952 3 18 0 11 JOYCE 18.9 32.8 88 139 +1991 8 7 6 12 MICHAEL 57.1 347.9 121 647 +1982 2 17 12 28 ALBERTO 7.0 125.6 60 733 +2000 5 15 18 15 BERYL 19.6 39.3 99 658 +1991 2 25 0 1 ISAAC 46.5 25.7 22 330 +1989 9 13 18 14 CHRIS 26.2 178.3 93 234 +1980 1 6 12 18 OSCAR 18.3 106.4 10 696 +1972 4 27 6 8 MICHAEL 38.6 113.3 88 44 +1982 3 12 18 26 ISAAC 49.0 291.6 113 219 +1987 7 16 6 3 TONY 54.5 126.3 41 645 +1997 9 1 0 1 TONY 51.7 319.0 64 738 +1959 4 4 12 18 ISAAC 30.2 257.0 147 302 +1981 1 12 12 20 DEBBY 54.0 139.5 103 81 +1961 7 1 18 11 OSCAR 9.5 193.5 66 66 +1958 8 22 12 25 GORDON 9.3 271.9 117 624 +1967 2 18 6 22 SANDY 51.4 149.8 42 216 +1960 10 20 6 3 LESLIE 50.4 61.2 135 749 +1961 1 25 12 9 WILLIAM 8.6 167.4 21 260 +1990 9 16 6 4 HELENE 61.5 33.3 76 341 +1961 6 19 18 11 GORDON 56.2 329.8 52 169 +1952 2 26 6 6 CHRIS 68.4 34.1 110 735 +1950 12 27 18 12 ISAAC 23.7 60.2 101 254 +1986 1 7 0 6 TONY 33.7 311.8 62 10 +1951 7 20 12 8 ISAAC 26.3 152.6 80 72 +1976 11 6 0 18 HELENE 48.2 84.5 53 331 +1995 7 4 6 26 HELENE 49.3 124.2 163 414 +1991 5 6 6 9 DEBBY 63.1 155.7 82 562 +1981 3 24 18 27 MICHAEL 38.7 204.9 95 184 +1967 5 13 0 5 VALERIE 27.0 293.0 126 890 +1952 1 23 0 4 VALERIE 50.9 95.1 19 706 +1981 3 6 0 21 VALERIE 55.0 290.4 46 522 +2002 10 16 6 14 ISAAC 17.2 193.9 151 328 +2004 3 5 12 16 LESLIE 63.0 56.3 147 639 +1984 6 6 6 10 JOYCE 7.2 216.7 101 167 +1989 5 27 6 6 TONY 42.9 50.5 55 327 +1999 8 1 0 2 VALERIE 53.6 34.5 99 459 +1953 1 16 18 7 ALBERTO 68.4 265.5 17 693 +1993 1 10 18 15 ISAAC 26.2 282.4 65 473 +1988 1 18 18 10 KIRK 38.4 328.5 121 744 +1977 1 14 0 2 SANDY 37.4 264.8 135 106 +1955 7 23 18 22 LESLIE 66.2 257.0 115 231 +1985 8 15 6 13 VALERIE 8.7 58.3 77 414 +2003 12 3 18 15 MICHAEL 26.1 278.5 139 565 +1960 7 7 0 24 ERNESTO 8.2 332.8 105 586 +1981 7 25 12 2 ALBERTO 18.2 141.3 163 332 +1998 1 23 0 16 CHRIS 33.5 7.7 44 545 +1972 9 17 6 10 CHRIS 20.9 198.7 47 527 +1976 10 24 18 16 DEBBY 62.5 216.0 112 653 +1954 11 15 12 15 KIRK 47.8 148.5 92 792 +1997 2 20 12 6 KIRK 37.6 343.7 118 392 +1964 1 21 12 14 KIRK 48.6 247.5 60 105 +1981 12 11 12 27 NADINE 12.7 245.6 153 870 +1955 10 14 12 23 BERYL 19.5 239.0 83 648 +1970 4 3 18 5 ERNESTO 41.8 85.8 128 847 +1993 6 26 0 24 WILLIAM 13.2 145.0 74 87 +1997 3 26 6 22 RAFAEL 18.0 80.0 83 484 +1972 11 21 0 1 BERYL 43.8 187.9 161 680 +1972 10 9 12 22 ISAAC 30.1 116.0 125 423 +1965 10 22 18 26 HELENE 39.5 242.0 117 113 +1964 4 21 0 9 PATTY 66.5 36.2 89 381 +2002 2 25 6 5 ALBERTO 14.7 146.9 21 691 +1979 7 8 0 26 VALERIE 45.9 341.6 75 59 +2000 5 21 6 6 NADINE 49.6 43.8 98 329 +1975 4 22 6 25 ISAAC 45.1 108.3 30 356 +1973 7 13 18 13 VALERIE 29.1 223.8 153 866 +1981 9 4 12 24 WILLIAM 45.5 47.2 51 301 +1980 10 7 0 26 CHRIS 45.2 149.3 71 285 +1984 7 19 18 9 PATTY 7.2 295.4 25 694 +1997 1 10 0 27 CHRIS 50.9 126.8 142 879 +1985 6 14 0 3 SANDY 36.0 136.4 34 576 +1994 6 11 18 16 TONY 50.9 9.4 156 601 +1966 6 22 6 2 BERYL 61.2 261.1 26 473 +1960 3 2 18 19 JOYCE 42.5 10.8 112 665 +1983 11 24 6 18 ERNESTO 56.4 291.4 123 300 +1971 8 1 6 22 ISAAC 27.6 269.0 36 442 +1955 1 13 6 27 MICHAEL 66.6 347.2 72 4 +1964 8 6 0 24 FLORENCE 39.7 84.8 14 491 +2004 1 28 6 20 DEBBY 44.7 213.6 140 814 +1959 8 7 0 6 HELENE 43.3 38.6 48 618 +1972 3 24 12 28 NADINE 41.2 304.1 140 166 +1957 11 22 0 10 WILLIAM 13.4 178.1 68 777 +1981 3 16 6 1 ISAAC 65.3 38.5 40 405 +1958 5 7 18 6 KIRK 21.1 152.0 38 308 +1992 1 19 0 25 ALBERTO 12.9 249.9 159 335 +1963 5 16 0 28 MICHAEL 57.9 205.1 131 264 +1978 2 15 0 20 BERYL 50.0 334.1 61 764 +2001 7 24 12 8 MICHAEL 48.0 118.1 82 275 +1980 11 12 12 15 KIRK 53.0 211.9 11 519 +1957 8 11 12 23 WILLIAM 27.0 102.9 67 463 +1976 11 17 12 12 BERYL 57.0 342.3 29 276 +1978 9 12 12 22 JOYCE 22.4 250.1 82 120 +1972 6 27 18 20 ERNESTO 62.6 265.2 131 540 +1980 11 7 6 3 RAFAEL 48.0 213.1 24 633 +1951 2 21 12 14 PATTY 17.5 61.0 102 135 +1994 6 22 6 13 ERNESTO 50.1 323.8 47 182 +1979 11 12 12 9 NADINE 33.1 131.1 52 274 +2003 1 27 12 10 TONY 49.6 123.2 123 455 +1975 8 11 18 24 DEBBY 57.7 209.8 29 97 +2001 9 6 6 13 LESLIE 30.2 115.3 31 289 +1960 6 19 12 16 HELENE 54.9 166.8 44 387 +1952 8 26 18 4 NADINE 53.0 354.8 136 234 +1971 5 21 18 27 FLORENCE 55.9 178.5 27 286 +1956 10 6 0 2 JOYCE 37.4 346.9 145 309 +1958 3 2 6 4 HELENE 55.7 129.7 85 663 +1980 12 10 18 7 SANDY 30.0 142.7 33 751 +1959 11 11 18 5 ALBERTO 46.3 180.3 114 837 +1991 9 13 6 21 SANDY 69.9 258.6 77 232 +1968 11 11 6 10 CHRIS 64.8 91.4 149 411 +1951 12 19 12 18 VALERIE 52.9 352.8 45 368 +1973 7 27 6 12 GORDON 36.6 113.6 71 186 +1955 12 22 12 15 VALERIE 64.6 122.8 13 255 +1997 4 4 18 28 OSCAR 69.0 223.0 109 846 +1975 5 25 12 24 PATTY 42.6 51.7 82 745 +1951 8 12 18 28 OSCAR 52.7 153.5 39 618 +1961 11 6 6 1 ERNESTO 18.9 59.1 145 88 +1957 9 4 18 3 WILLIAM 13.3 14.0 29 775 +1987 1 26 12 11 PATTY 31.4 297.4 24 605 +1997 3 11 18 23 NADINE 66.7 338.3 21 181 +1997 7 13 0 23 BERYL 7.0 185.2 79 297 +1973 2 7 12 12 FLORENCE 23.2 8.6 51 328 +1975 6 4 12 13 TONY 15.7 330.6 140 260 +1989 10 3 12 19 ERNESTO 49.0 147.6 127 82 +1969 1 12 0 15 JOYCE 44.1 14.0 145 110 +1982 1 20 12 1 MICHAEL 15.7 13.4 49 431 +1998 2 23 12 8 WILLIAM 30.2 228.3 47 584 +1991 3 11 6 14 LESLIE 32.0 45.2 17 795 +1993 8 11 0 9 BERYL 10.4 41.5 157 152 +1960 10 3 18 9 CHRIS 56.7 141.6 47 707 +1996 2 25 0 17 RAFAEL 16.4 273.3 69 451 +1962 12 27 6 18 OSCAR 9.7 104.2 159 97 +1968 9 2 6 27 VALERIE 57.0 267.9 25 5 +1973 7 21 0 20 WILLIAM 45.9 169.4 128 316 +1986 4 11 12 16 LESLIE 8.9 346.9 105 326 +1974 5 19 6 25 TONY 50.4 318.1 156 799 +1967 11 24 6 13 OSCAR 11.7 54.7 80 804 +1962 9 4 18 6 ISAAC 49.5 71.9 74 283 +1969 3 2 6 17 ERNESTO 34.7 9.8 60 329 +1984 2 13 12 22 BERYL 58.0 272.0 107 311 +1991 3 22 18 7 CHRIS 34.9 0.9 98 279 +1985 7 18 18 7 JOYCE 57.5 288.6 13 379 +1999 1 12 18 26 ISAAC 19.2 207.9 57 671 +1972 3 28 12 23 OSCAR 57.4 226.7 131 520 +1977 2 9 12 23 CHRIS 30.1 114.4 57 415 +1977 11 9 6 26 RAFAEL 54.9 259.4 87 161 +1996 6 18 12 13 NADINE 14.2 66.4 65 692 +1957 4 21 0 17 CHRIS 8.9 340.3 116 443 +1984 3 22 18 7 SANDY 8.5 62.6 149 543 +1979 4 8 12 27 GORDON 65.4 351.2 137 373 +1967 12 22 6 16 JOYCE 64.4 117.3 27 168 +1997 8 11 6 2 NADINE 21.1 20.6 125 224 +1965 2 4 18 9 ERNESTO 17.1 84.5 70 605 +1988 10 17 12 27 LESLIE 28.6 233.2 158 724 +1994 7 10 12 6 WILLIAM 34.7 128.6 120 566 +2002 7 19 12 25 BERYL 27.7 357.5 52 222 +1968 11 8 12 28 ALBERTO 46.1 139.3 134 244 +1994 8 24 18 18 MICHAEL 69.8 288.2 65 84 +1981 4 15 6 12 CHRIS 18.7 250.5 11 84 +1970 5 24 12 2 LESLIE 39.3 21.0 92 621 +2002 11 12 0 27 TONY 7.1 176.4 61 478 +1987 2 26 6 8 MICHAEL 57.2 285.4 97 44 +1986 5 19 12 16 WILLIAM 41.4 28.0 138 431 +1993 4 24 0 15 VALERIE 39.5 44.4 17 309 +1968 5 17 0 6 TONY 50.1 326.3 148 865 +1982 5 25 18 23 NADINE 61.0 101.4 54 721 +1953 11 28 6 14 ERNESTO 56.1 83.4 135 252 +1976 4 8 18 27 ALBERTO 12.9 198.0 152 762 +1992 2 27 0 12 PATTY 50.2 60.2 138 345 +1982 6 12 18 17 TONY 32.9 320.8 78 788 +1983 11 24 6 28 ERNESTO 41.6 59.9 51 706 +1973 2 25 18 11 ALBERTO 63.6 238.5 13 525 +1993 5 27 0 3 ALBERTO 64.4 61.1 107 517 +1964 2 18 6 24 OSCAR 29.2 261.5 127 117 +1983 7 24 12 15 ERNESTO 34.5 252.0 49 698 +1969 7 11 18 3 ISAAC 25.7 338.2 88 857 +1954 1 24 18 20 ISAAC 36.7 352.5 158 230 +1982 4 16 12 22 VALERIE 9.3 339.9 70 865 +1958 10 10 6 16 NADINE 22.1 66.9 154 105 +1999 3 27 18 14 RAFAEL 66.5 32.4 67 253 +1980 8 9 6 15 ISAAC 49.6 49.6 80 650 +1987 11 13 18 13 GORDON 18.6 98.6 67 53 +1999 10 27 0 23 NADINE 23.3 32.9 131 159 +1971 2 22 12 9 PATTY 24.8 0.3 107 230 +2001 11 11 18 9 BERYL 18.2 280.8 148 760 +1992 4 10 0 18 FLORENCE 17.6 119.4 41 241 +1988 4 12 18 5 GORDON 15.1 259.6 134 767 +1958 8 5 12 22 JOYCE 11.4 162.7 129 857 +1974 1 14 6 21 KIRK 61.8 2.1 54 784 +1971 2 9 12 9 SANDY 44.2 155.6 24 247 +1987 3 17 18 28 CHRIS 58.2 171.4 36 181 +1993 5 2 12 19 GORDON 42.0 233.0 155 318 +1967 11 4 12 25 WILLIAM 42.8 243.1 67 108 +1989 11 17 18 21 ISAAC 28.7 157.9 137 339 +1990 11 10 6 2 ALBERTO 14.5 132.8 148 277 +1965 7 21 18 20 TONY 32.6 47.9 108 457 +1979 3 20 12 13 DEBBY 22.3 11.0 18 527 +2001 8 14 6 3 FLORENCE 35.6 165.3 16 131 +1996 1 2 18 17 HELENE 20.6 14.4 92 676 +1970 1 16 12 24 BERYL 64.5 37.7 51 321 +1976 5 19 18 12 MICHAEL 9.0 305.0 127 54 +1976 7 4 12 23 JOYCE 44.7 278.6 73 218 +1990 6 15 0 24 LESLIE 32.0 135.9 109 600 +1955 9 19 0 20 CHRIS 17.2 163.6 90 371 +1988 6 19 6 20 MICHAEL 39.7 24.9 65 647 +1990 8 27 18 28 JOYCE 33.1 58.3 29 159 +1971 12 1 12 25 VALERIE 30.3 11.8 68 282 +1953 1 12 12 3 OSCAR 68.7 281.2 107 458 +1978 5 8 6 19 KIRK 16.1 161.4 159 123 +1988 11 11 12 23 TONY 14.0 193.0 150 444 +1974 4 14 18 28 ALBERTO 66.3 69.2 72 7 +1996 6 27 18 11 WILLIAM 50.5 75.8 147 283 +1953 1 8 6 25 NADINE 20.5 57.1 80 108 +2004 5 13 0 9 MICHAEL 20.5 241.4 73 489 +1992 6 3 12 14 SANDY 59.5 112.9 31 106 +1988 11 16 18 2 HELENE 14.7 151.5 18 791 +1966 9 5 6 11 FLORENCE 24.6 17.3 71 546 +1982 3 7 18 12 NADINE 23.4 348.2 78 407 +1977 10 8 12 2 PATTY 8.7 317.6 73 623 +1964 11 6 12 7 WILLIAM 54.4 268.2 157 123 +1991 2 9 6 7 ISAAC 22.0 203.0 129 8 +1967 7 4 6 21 LESLIE 61.8 74.9 135 421 +1956 10 10 18 22 OSCAR 23.0 4.2 67 316 +1966 6 19 18 1 JOYCE 37.1 93.2 91 698 +2003 2 5 6 24 MICHAEL 20.6 64.0 51 395 +1956 9 20 6 16 OSCAR 21.3 69.9 76 557 +1990 3 11 6 17 DEBBY 46.4 189.3 24 880 +1992 3 19 6 26 BERYL 28.5 317.7 153 700 +2001 1 13 0 9 ALBERTO 60.6 52.0 123 594 +2001 5 6 0 16 JOYCE 19.1 325.7 73 588 +1983 1 25 0 25 NADINE 18.1 20.6 150 295 +1962 11 12 12 7 MICHAEL 43.3 272.0 106 563 +1991 3 10 6 18 ISAAC 50.8 324.4 54 734 +1977 3 26 18 17 PATTY 41.9 171.7 106 9 +1990 1 24 6 2 ERNESTO 18.9 9.3 152 85 +1962 8 27 6 2 LESLIE 23.2 240.3 74 786 +1998 3 20 6 16 MICHAEL 31.0 102.5 159 124 +1951 10 9 12 8 TONY 11.0 214.9 107 217 +1992 11 16 18 23 TONY 33.2 112.5 59 253 +1957 2 27 6 24 MICHAEL 58.9 25.6 125 116 +2000 9 11 18 6 FLORENCE 28.6 291.3 43 425 +1957 3 15 6 3 VALERIE 43.2 12.0 10 376 +1963 4 7 6 1 BERYL 18.1 326.0 134 508 +1980 11 7 18 26 BERYL 9.3 256.2 118 209 +1965 9 11 18 13 OSCAR 53.9 21.9 40 395 +1982 11 10 12 14 HELENE 7.8 103.1 114 22 +1952 2 8 18 28 WILLIAM 9.8 260.3 99 461 +1997 10 14 6 15 LESLIE 23.7 355.4 130 863 +1971 4 13 12 13 ALBERTO 46.7 248.8 105 765 +1973 10 12 0 1 NADINE 12.9 296.7 38 784 +1973 5 20 18 27 DEBBY 69.4 143.4 118 624 +1984 11 10 12 18 ISAAC 51.0 140.4 112 564 +1958 8 3 12 27 CHRIS 14.4 145.8 77 781 +2003 11 18 6 22 GORDON 30.1 42.9 132 734 +1969 4 4 6 3 MICHAEL 68.0 29.7 44 351 +1978 3 21 6 21 TONY 17.1 48.4 132 428 +1986 4 2 12 27 SANDY 21.7 281.0 131 794 +1999 10 1 12 9 CHRIS 7.6 102.5 14 346 +2000 11 13 0 6 FLORENCE 68.9 222.3 11 840 +1975 7 28 18 7 RAFAEL 44.1 332.2 71 696 +1975 9 20 18 19 LESLIE 13.2 337.0 134 794 +1962 10 22 12 8 LESLIE 24.4 332.8 18 196 +1979 11 17 0 4 VALERIE 10.6 183.6 26 786 +1992 11 23 18 5 KIRK 47.1 331.1 146 356 +1982 6 12 0 24 ISAAC 54.0 148.0 122 654 +1957 2 16 18 22 CHRIS 56.2 93.1 100 841 +1986 8 2 0 19 PATTY 41.1 312.9 89 745 +1970 5 17 18 14 CHRIS 27.9 201.2 84 570 +1953 7 23 6 19 SANDY 51.0 122.6 91 250 +1957 8 3 12 12 TONY 54.3 292.0 152 76 +2002 6 2 6 11 FLORENCE 51.6 87.8 139 703 +2004 6 14 12 22 TONY 45.2 3.1 50 135 +1978 11 12 18 6 VALERIE 62.6 160.6 57 118 +1953 12 22 0 2 FLORENCE 30.8 336.8 134 791 +1981 7 13 0 18 VALERIE 20.7 9.7 59 710 +2001 12 5 6 1 CHRIS 49.7 156.9 150 195 +1957 7 19 18 28 HELENE 57.7 221.5 92 540 +1994 9 6 12 16 NADINE 39.9 77.2 137 793 +1952 9 13 6 6 JOYCE 35.6 256.2 138 41 +1959 4 19 12 18 ERNESTO 52.3 41.0 14 446 +1966 9 23 18 2 ALBERTO 29.1 112.9 105 785 +1956 3 20 18 2 FLORENCE 42.4 255.0 162 584 +1988 7 23 6 7 HELENE 20.4 234.3 107 635 +1950 5 25 6 11 KIRK 44.3 322.7 61 250 +1955 11 12 0 22 LESLIE 12.3 244.3 55 134 +1983 12 15 18 22 SANDY 22.9 289.0 58 800 +1953 7 16 6 25 VALERIE 55.2 254.2 106 461 +1987 7 20 6 18 RAFAEL 41.0 238.8 80 247 +1960 8 6 12 18 OSCAR 26.0 246.2 26 748 +1963 3 22 0 25 FLORENCE 30.2 284.7 97 167 +1954 2 13 6 4 FLORENCE 44.2 0.1 78 769 +1974 5 8 18 4 VALERIE 59.0 162.1 155 112 +1975 5 14 12 1 DEBBY 19.5 229.7 89 242 +1994 3 14 18 1 VALERIE 30.9 31.9 123 98 +1998 11 2 18 20 GORDON 23.7 80.2 73 169 +1964 1 10 12 11 JOYCE 34.9 124.5 151 252 +1964 9 5 6 5 WILLIAM 24.7 23.8 29 753 +1993 6 6 12 15 JOYCE 61.9 141.4 114 617 +1959 9 27 18 28 NADINE 20.3 61.3 150 15 +1982 10 11 0 23 GORDON 16.4 248.6 53 752 +1965 1 2 6 9 ERNESTO 27.2 287.8 101 592 +1971 2 17 12 18 LESLIE 45.6 355.3 119 593 +1973 9 5 18 3 BERYL 21.1 278.7 107 899 +1955 8 15 6 25 HELENE 8.3 75.3 42 270 +1987 5 19 18 14 NADINE 61.7 100.3 31 588 +1999 9 25 6 21 JOYCE 21.1 289.8 12 621 +1997 12 2 18 2 MICHAEL 52.4 308.8 77 105 +1956 1 28 18 14 NADINE 11.4 270.1 27 284 +1962 9 26 18 23 JOYCE 13.2 152.4 126 72 +1985 3 14 12 11 CHRIS 45.2 222.8 137 827 +1997 12 4 0 24 WILLIAM 27.6 68.6 85 98 +1973 10 12 18 24 NADINE 31.8 267.8 142 87 +1957 8 27 6 20 VALERIE 14.0 92.4 81 116 +1961 9 14 18 27 KIRK 12.9 103.8 47 318 +1992 3 16 6 12 JOYCE 58.4 194.3 153 249 +2002 10 21 0 10 ERNESTO 16.9 80.5 66 346 +1999 11 23 18 4 PATTY 34.7 207.8 138 479 +1991 9 18 0 19 PATTY 55.4 328.7 50 527 +1966 4 13 6 18 FLORENCE 51.9 280.7 101 589 +1956 10 13 12 6 ALBERTO 38.9 108.9 106 390 +1959 11 14 12 16 VALERIE 29.5 260.0 97 605 +1960 6 19 0 23 LESLIE 38.6 40.3 102 582 +1971 1 27 6 15 MICHAEL 59.6 80.5 95 204 +1967 4 13 0 6 KIRK 43.1 233.5 140 313 +1988 9 19 18 14 TONY 51.8 103.3 37 424 +1969 11 27 12 24 FLORENCE 49.5 356.8 37 703 +1975 1 27 18 5 ERNESTO 10.3 225.6 55 330 +1987 7 17 12 2 JOYCE 23.8 100.4 23 217 +1963 12 17 18 14 CHRIS 21.4 230.2 146 144 +1986 11 24 0 23 FLORENCE 10.5 43.7 125 292 +1959 1 12 0 6 RAFAEL 68.3 83.4 49 417 +1974 4 8 12 9 GORDON 10.9 57.9 107 873 +1966 6 9 6 13 WILLIAM 24.3 35.7 35 162 +1965 5 5 6 7 JOYCE 47.9 109.0 60 847 +1994 3 23 6 9 MICHAEL 26.1 165.2 164 461 +1987 7 9 6 4 FLORENCE 30.4 319.2 108 254 +1976 10 23 18 20 DEBBY 36.0 187.0 69 827 +1965 9 23 18 19 PATTY 52.3 102.7 67 195 +2002 7 2 18 10 LESLIE 36.0 299.8 35 848 +1979 5 10 0 26 OSCAR 17.5 321.5 73 849 +1991 7 28 0 11 KIRK 45.3 35.4 148 105 +1986 11 3 12 18 RAFAEL 27.5 329.0 45 612 +1965 4 8 18 6 RAFAEL 46.7 134.7 103 349 +1991 9 20 0 14 CHRIS 20.6 268.5 133 859 +1978 11 15 18 7 JOYCE 36.3 352.1 80 861 +2004 10 11 6 17 ALBERTO 62.8 195.8 70 64 +1968 12 7 18 12 ALBERTO 25.7 311.4 53 469 +1966 2 4 12 13 GORDON 60.3 162.2 85 777 +1961 8 19 18 13 RAFAEL 65.9 236.5 158 595 +1961 1 15 18 6 LESLIE 28.2 348.2 42 518 +1970 5 2 18 10 JOYCE 64.4 140.6 26 769 +1968 10 16 18 4 VALERIE 24.3 165.5 99 750 +1997 3 3 0 26 ALBERTO 8.6 262.3 84 465 +1995 1 12 6 12 TONY 9.9 29.8 158 272 +1986 10 27 12 8 SANDY 11.2 24.5 147 135 +1959 4 25 12 11 RAFAEL 34.9 294.0 120 500 +1963 2 8 0 11 CHRIS 10.0 241.9 115 138 +1963 8 20 0 7 CHRIS 47.4 299.9 73 865 +1957 8 12 0 3 KIRK 23.9 168.0 118 587 +1971 6 4 0 9 WILLIAM 40.3 87.7 16 707 +2003 8 9 0 16 LESLIE 42.1 7.3 135 770 +1950 1 12 0 24 MICHAEL 11.7 294.9 15 274 +1991 11 6 0 16 CHRIS 38.1 189.1 89 626 +1974 10 18 0 3 JOYCE 7.4 186.8 117 512 +2004 5 9 6 15 JOYCE 52.9 31.7 126 543 +1951 11 24 18 8 LESLIE 27.5 355.8 146 803 +1965 2 14 18 16 ISAAC 20.4 205.4 140 461 +1978 3 20 0 23 ALBERTO 34.1 254.7 93 223 +1950 9 4 0 7 BERYL 22.0 302.4 49 251 +2001 1 1 12 1 NADINE 55.0 317.9 56 323 +1952 10 27 12 13 VALERIE 22.4 7.1 31 275 +1951 1 10 18 22 NADINE 33.9 28.9 160 427 +1975 8 1 12 27 ERNESTO 32.6 17.0 110 800 +1988 12 1 12 21 DEBBY 28.5 174.2 120 629 +1983 9 6 18 23 JOYCE 31.2 281.3 141 26 +1953 5 7 6 6 NADINE 68.8 125.4 162 375 +1995 12 3 12 27 LESLIE 42.7 204.7 157 43 +1973 2 28 0 9 TONY 23.7 140.4 137 643 +1979 2 26 0 24 JOYCE 15.6 13.3 64 23 +1994 7 11 18 7 GORDON 21.3 338.4 67 150 +2001 11 28 0 16 SANDY 69.9 285.4 156 766 +1984 4 28 6 14 JOYCE 44.2 34.2 31 867 +1985 1 23 12 22 CHRIS 28.4 79.5 27 56 +1974 9 20 6 6 KIRK 42.0 274.1 133 79 +1977 3 3 12 26 TONY 50.6 113.9 101 251 +1974 4 12 18 23 HELENE 41.9 73.5 88 284 +2002 11 6 0 10 JOYCE 45.5 68.3 145 589 +1987 8 19 0 28 KIRK 23.7 40.8 84 207 +1990 10 24 6 1 RAFAEL 17.9 195.3 57 277 +1983 2 25 6 11 HELENE 30.6 198.1 40 601 +1950 9 16 18 23 NADINE 24.7 190.8 70 734 +1957 7 25 18 13 JOYCE 20.4 263.7 59 637 +1952 3 27 6 20 FLORENCE 19.8 153.9 129 497 +1996 1 22 6 7 JOYCE 13.0 301.6 63 592 +1963 10 2 0 18 OSCAR 59.5 190.5 160 822 +2001 5 5 18 23 ISAAC 56.6 97.3 123 677 +1952 10 20 12 13 ALBERTO 15.9 161.3 154 595 +1995 11 20 18 19 KIRK 27.1 85.9 67 851 +1954 2 25 18 12 TONY 34.6 241.1 38 623 +1957 12 25 12 8 TONY 53.7 35.4 153 146 +1976 4 1 12 18 HELENE 35.7 62.7 155 225 +1950 1 4 12 5 BERYL 17.0 271.8 42 478 +1975 9 2 12 21 JOYCE 14.2 331.5 118 360 +1967 11 2 18 4 KIRK 16.1 252.6 55 266 +1962 8 16 18 1 PATTY 53.5 88.5 110 503 +2001 10 2 12 14 TONY 43.5 293.0 93 779 +1984 7 7 0 8 HELENE 58.8 18.6 73 47 +1993 1 3 18 28 ISAAC 45.5 234.9 45 801 +1954 5 4 0 9 NADINE 45.4 101.6 85 846 +1999 6 22 18 16 VALERIE 13.7 281.1 16 44 +2003 9 24 18 20 RAFAEL 15.9 150.7 71 544 +1988 8 4 12 25 BERYL 44.3 150.9 101 645 +1982 6 22 18 18 OSCAR 53.6 162.7 17 623 +1964 12 20 18 7 SANDY 15.4 114.3 28 570 +1968 6 12 12 8 TONY 7.1 265.0 58 237 +1953 10 27 0 17 PATTY 22.6 205.8 40 187 +1951 2 10 6 13 ISAAC 15.6 313.8 137 354 +1989 11 8 6 4 WILLIAM 9.6 183.0 155 837 +1955 1 25 18 9 ERNESTO 47.5 288.9 65 624 +1955 5 25 6 12 SANDY 51.3 147.7 96 864 +1976 6 13 6 7 GORDON 40.6 119.1 49 593 +1954 8 9 6 17 RAFAEL 7.5 323.5 130 197 +1992 12 15 6 3 ISAAC 37.0 86.4 22 412 +1968 2 14 0 5 OSCAR 9.7 235.7 53 565 +1971 10 25 6 23 JOYCE 51.3 19.2 120 18 +2004 10 17 12 8 ISAAC 24.7 104.9 140 637 +1981 1 16 0 16 MICHAEL 24.3 247.7 60 22 +2001 2 13 6 6 ISAAC 56.1 35.3 63 812 +2002 12 23 12 17 DEBBY 23.0 357.1 59 112 +1999 9 15 0 2 WILLIAM 22.4 201.9 113 445 +2000 12 16 0 3 NADINE 34.1 307.7 82 27 +1956 7 18 18 9 ERNESTO 17.0 222.9 58 817 +1966 1 21 18 4 ISAAC 20.4 345.0 91 701 +1963 11 22 12 1 RAFAEL 56.4 328.7 44 694 +1951 11 9 12 1 FLORENCE 13.8 64.1 41 782 +1991 5 13 0 8 JOYCE 27.5 333.3 60 178 +1967 10 2 6 1 RAFAEL 59.9 231.7 162 801 +1990 2 26 0 26 OSCAR 48.5 317.8 128 640 +1986 6 16 18 25 BERYL 26.2 243.7 17 617 +1984 6 16 18 14 SANDY 7.4 33.7 48 743 +1963 7 6 0 6 DEBBY 35.7 235.9 76 638 +1996 1 23 0 20 ALBERTO 35.0 35.6 136 94 +1952 10 3 18 1 DEBBY 39.5 224.7 112 438 +1957 2 2 6 14 MICHAEL 35.8 235.5 152 728 +1983 7 6 12 20 OSCAR 17.3 163.3 31 891 +1994 7 11 6 6 BERYL 42.0 173.4 92 128 +1960 7 18 12 21 BERYL 19.2 280.8 83 292 +1985 12 6 18 27 NADINE 31.8 121.7 57 428 +1993 7 23 18 24 OSCAR 44.2 91.5 162 707 +1965 1 17 18 8 HELENE 42.3 341.2 59 825 +1952 6 20 0 7 VALERIE 56.8 341.4 144 100 +1998 1 1 18 22 SANDY 67.2 276.6 32 749 +1998 6 26 6 10 TONY 64.0 35.9 19 536 +2004 4 27 12 22 TONY 36.9 19.6 32 408 +1998 3 25 0 26 CHRIS 45.1 316.4 17 597 +1953 9 9 0 3 BERYL 47.0 279.7 45 507 +1981 5 9 6 21 SANDY 22.4 206.2 128 556 +1965 1 5 0 12 GORDON 17.8 153.3 127 699 +1988 8 19 6 19 MICHAEL 7.9 78.5 152 720 +1996 3 23 18 16 MICHAEL 50.4 41.4 140 181 +1953 2 12 12 19 ISAAC 12.4 78.3 95 700 +1998 5 4 0 10 BERYL 45.2 50.7 74 561 +1989 12 26 12 19 JOYCE 17.6 341.4 52 396 +1953 7 19 18 7 PATTY 33.1 125.5 158 252 +1981 9 14 0 28 MICHAEL 35.2 67.3 96 192 +2003 10 8 6 8 CHRIS 68.3 332.9 133 449 +1975 3 16 6 2 NADINE 64.6 326.5 143 510 +1997 11 23 12 10 ALBERTO 36.7 355.8 22 888 +1956 11 14 18 23 ALBERTO 65.3 207.8 79 848 +1956 3 20 6 5 VALERIE 34.9 213.7 32 122 +1955 10 16 12 27 PATTY 19.1 173.9 18 425 +1973 4 22 18 24 MICHAEL 61.7 182.4 82 112 +1967 6 22 18 11 CHRIS 12.1 357.7 46 839 +1989 1 23 0 24 WILLIAM 9.6 88.9 88 275 +1975 10 17 0 1 OSCAR 47.8 130.8 162 723 +1997 8 11 0 5 KIRK 33.7 248.3 50 211 +1985 1 20 18 27 MICHAEL 62.3 305.3 147 467 +1985 5 6 12 24 RAFAEL 33.2 69.0 97 398 +1953 7 21 0 6 JOYCE 31.8 85.1 93 533 +1974 7 25 18 26 LESLIE 37.6 310.4 36 899 +1958 8 14 18 28 TONY 16.1 130.8 143 303 +1986 12 17 0 6 CHRIS 15.7 304.1 92 144 +1957 7 28 18 18 OSCAR 54.1 199.3 120 532 +1996 5 13 12 12 OSCAR 56.5 160.2 114 516 +2000 12 14 0 10 BERYL 68.2 2.3 32 630 +1982 2 18 12 2 KIRK 55.4 222.3 68 431 +2002 7 12 6 9 KIRK 57.3 177.2 102 713 +1979 12 26 6 16 JOYCE 57.5 107.6 17 839 +1959 3 21 18 6 DEBBY 40.2 150.7 106 254 +1976 6 5 12 25 ALBERTO 26.7 344.4 73 349 +2000 5 14 6 25 MICHAEL 17.1 44.8 56 503 +1967 3 4 0 9 WILLIAM 41.7 315.1 21 317 +1982 4 18 0 12 TONY 56.5 139.6 70 556 +1960 10 1 6 3 GORDON 68.0 239.1 83 229 +1967 7 1 0 14 GORDON 33.3 232.8 148 763 +1964 9 24 6 8 HELENE 10.8 335.2 113 560 +1980 9 5 12 13 JOYCE 30.7 142.1 109 136 +1976 3 8 0 6 MICHAEL 25.8 167.2 103 346 +1986 11 21 0 20 NADINE 61.8 352.9 89 589 +1966 4 14 18 12 FLORENCE 48.8 1.4 144 536 +1982 1 28 6 8 FLORENCE 48.7 242.1 124 33 +1965 8 27 0 28 KIRK 67.3 98.6 50 579 +1964 11 23 18 9 RAFAEL 18.3 156.3 48 681 +1997 7 24 6 19 PATTY 68.3 351.1 49 240 +1954 1 1 12 20 HELENE 14.9 331.6 122 82 +1971 7 9 0 7 CHRIS 50.4 351.5 147 316 +1971 7 11 0 28 TONY 69.9 286.9 23 465 +1985 1 13 12 24 VALERIE 57.6 225.4 92 803 +1968 9 1 6 6 MICHAEL 55.9 43.6 132 500 +1970 11 2 18 5 CHRIS 34.8 292.5 46 300 +1952 5 14 18 17 LESLIE 27.4 37.0 89 789 +1957 3 3 0 2 JOYCE 12.1 152.8 57 514 +1992 2 28 18 6 WILLIAM 62.4 322.1 104 479 +1988 3 8 18 18 JOYCE 42.3 156.8 124 287 +1993 5 27 0 23 JOYCE 51.3 257.7 35 878 +1963 7 23 12 16 HELENE 44.7 288.1 38 25 +1958 12 13 12 6 KIRK 42.4 58.4 55 182 +1957 10 7 0 11 SANDY 54.3 136.9 37 743 +1984 6 23 18 22 WILLIAM 63.8 262.9 31 17 +1978 5 10 0 17 GORDON 15.9 252.9 113 312 +1967 10 27 18 3 KIRK 35.6 197.8 27 708 +1968 1 18 12 2 WILLIAM 38.1 153.4 37 141 +1997 5 21 18 10 VALERIE 10.9 84.2 83 883 +1995 12 5 0 17 JOYCE 29.5 33.2 13 574 +1967 2 17 0 27 TONY 31.2 96.6 43 624 +1952 8 25 0 23 GORDON 65.4 207.5 87 728 +1955 1 8 12 8 BERYL 15.3 264.4 92 652 +1954 12 9 6 9 KIRK 67.3 55.6 34 417 +1979 9 25 12 9 OSCAR 50.1 324.6 111 195 +1994 9 22 18 22 DEBBY 15.0 106.1 37 222 +1988 12 27 0 18 TONY 30.0 89.8 113 39 +1999 5 1 12 22 VALERIE 68.5 264.2 129 557 +1998 11 3 6 3 TONY 49.5 163.0 125 369 +1995 9 2 0 15 ISAAC 18.5 247.4 83 120 +1961 2 27 18 21 ISAAC 31.9 334.8 150 545 +2003 6 13 12 16 LESLIE 57.9 333.8 17 454 +1969 6 19 12 25 JOYCE 67.2 336.2 56 63 +1993 12 3 18 6 OSCAR 46.7 342.9 63 784 +1982 6 6 18 14 KIRK 38.1 341.8 124 300 +1992 1 12 18 21 MICHAEL 53.4 129.5 46 430 +1979 10 11 6 19 ISAAC 30.8 319.9 40 882 +1994 2 3 0 10 ERNESTO 43.4 24.2 91 501 +1950 5 19 12 6 SANDY 22.2 351.4 163 811 +1962 8 25 6 6 TONY 49.1 234.4 30 91 +1951 3 2 18 26 JOYCE 25.6 79.9 54 404 +1951 3 2 18 15 ALBERTO 33.5 211.6 53 601 +1986 12 24 12 27 RAFAEL 67.2 197.1 89 300 +1969 10 8 6 13 CHRIS 47.5 337.1 55 733 +1960 1 28 12 12 TONY 28.7 322.7 67 604 +2002 9 6 12 4 GORDON 54.8 191.9 127 739 +1965 6 2 18 17 TONY 66.1 26.6 53 543 +1952 2 12 6 8 ALBERTO 14.2 125.7 148 224 +1974 5 23 0 24 JOYCE 20.4 123.3 29 819 +1977 3 3 0 3 SANDY 20.0 32.3 67 196 +1986 9 28 6 5 WILLIAM 20.6 303.7 27 496 +1957 10 7 6 19 NADINE 35.5 36.5 154 572 +1972 4 2 12 15 PATTY 47.7 50.8 16 472 +1983 2 2 12 10 VALERIE 31.7 235.8 157 167 +1998 1 27 18 7 DEBBY 66.5 173.0 139 284 +1977 12 3 18 13 WILLIAM 45.9 163.8 111 764 +1966 8 4 6 13 JOYCE 16.5 85.3 25 273 +1962 12 13 18 24 TONY 61.2 37.3 136 298 +1988 10 5 12 15 CHRIS 46.1 5.8 60 107 +1957 6 25 18 18 CHRIS 44.7 171.2 160 570 +1984 1 14 0 27 JOYCE 63.4 195.0 99 123 +1979 11 27 12 21 HELENE 66.4 70.9 34 293 +1975 5 28 12 2 KIRK 29.9 145.5 150 447 +1977 12 14 6 15 ALBERTO 67.3 189.4 159 851 +1966 6 1 6 9 ALBERTO 8.6 16.6 57 134 +2002 7 19 0 21 SANDY 57.0 143.6 80 665 +1954 12 19 6 27 TONY 52.1 168.0 111 587 +1989 11 3 6 20 WILLIAM 69.5 128.7 116 66 +1994 10 13 0 11 HELENE 45.3 272.3 147 440 +1972 2 28 18 26 MICHAEL 10.0 261.6 40 85 +1970 3 24 12 16 JOYCE 43.4 128.2 109 748 +1983 6 1 12 13 WILLIAM 37.3 107.1 30 227 +1996 12 22 18 16 NADINE 65.8 90.1 147 293 +1990 7 23 12 23 OSCAR 18.4 24.3 29 588 +1986 3 6 6 5 CHRIS 31.8 21.6 12 788 +1993 6 17 18 1 ERNESTO 65.9 301.6 109 882 +2004 6 25 6 25 OSCAR 63.9 104.6 58 747 +2003 10 18 12 3 ERNESTO 13.8 335.8 164 763 +2001 7 8 18 2 OSCAR 30.4 67.4 40 135 +1988 5 12 0 24 JOYCE 43.9 203.1 90 771 +1965 2 27 6 28 GORDON 46.3 209.4 71 620 +1954 9 7 18 19 NADINE 9.6 113.3 62 405 +1987 7 26 0 15 KIRK 15.5 315.7 81 276 +1967 6 1 12 17 KIRK 57.4 257.1 151 837 +1984 12 26 12 7 SANDY 22.2 135.5 80 773 +1955 10 15 12 1 VALERIE 29.7 133.3 156 745 +2001 4 15 6 8 JOYCE 7.2 8.6 126 480 +1974 11 14 18 28 PATTY 8.6 278.4 23 60 +1965 1 20 18 28 ISAAC 62.3 337.3 109 318 +2000 5 15 0 28 NADINE 62.0 45.6 32 446 +2002 8 15 12 6 ALBERTO 11.8 32.8 117 219 +1981 12 9 12 7 RAFAEL 23.1 309.2 133 385 +1959 6 13 18 25 PATTY 7.5 198.9 149 815 +1984 7 20 18 13 WILLIAM 16.1 104.2 23 294 +1969 2 23 12 13 CHRIS 14.0 326.3 120 280 +1956 5 23 0 24 OSCAR 50.6 97.9 114 235 +1981 9 23 6 28 OSCAR 36.5 227.8 152 639 +1952 6 20 6 21 ALBERTO 57.7 2.6 135 513 +1997 4 8 6 11 TONY 64.3 91.5 137 725 +1965 8 14 0 26 LESLIE 60.8 282.4 102 136 +1976 3 12 0 27 DEBBY 13.7 228.7 13 413 +1983 10 21 0 28 PATTY 23.2 217.6 100 249 +1998 10 20 6 21 LESLIE 14.9 355.5 102 555 +1966 10 24 12 27 TONY 63.4 328.5 130 784 +1952 7 9 18 25 DEBBY 48.4 236.1 155 599 +1960 8 22 0 21 JOYCE 43.4 165.8 41 876 +1951 11 6 18 11 ALBERTO 29.9 216.6 17 192 +2004 9 10 18 25 KIRK 48.6 2.6 155 495 +1983 4 8 12 27 OSCAR 35.4 185.3 45 683 +1954 8 5 6 11 GORDON 59.4 225.6 111 169 +1977 6 13 18 22 HELENE 49.4 264.0 98 266 +1960 11 20 6 14 HELENE 50.4 114.4 18 760 +1976 9 25 18 7 WILLIAM 61.9 98.5 24 446 +1994 2 9 6 16 CHRIS 40.2 126.2 125 751 +1970 6 10 18 11 CHRIS 29.4 290.5 28 526 +1982 2 22 18 19 BERYL 24.8 101.0 104 475 +2003 1 16 18 15 BERYL 40.1 61.3 14 148 +1972 10 25 18 22 DEBBY 22.9 219.8 152 680 +1993 8 9 12 1 RAFAEL 16.7 209.6 14 343 +1987 11 27 12 18 NADINE 61.7 189.6 144 550 +1953 9 27 0 11 OSCAR 23.8 40.2 72 248 +1964 12 15 12 17 CHRIS 29.2 201.4 102 218 +1968 9 24 6 24 RAFAEL 27.6 243.7 82 829 +1973 8 18 12 8 KIRK 52.0 333.7 32 427 +1997 10 24 0 13 JOYCE 25.1 15.0 19 865 +2000 9 24 18 11 ERNESTO 29.5 157.1 164 96 +1980 9 18 0 18 SANDY 57.6 214.4 146 226 +1957 7 3 18 9 FLORENCE 66.4 9.0 29 898 +1991 12 7 18 14 GORDON 32.1 209.0 24 205 +2003 4 2 0 3 ALBERTO 15.0 122.9 24 316 +1994 4 1 6 17 LESLIE 64.4 194.6 61 856 +1966 11 24 6 8 VALERIE 22.7 137.3 161 883 +1983 10 19 12 4 FLORENCE 46.1 309.0 159 200 +1999 5 12 18 2 CHRIS 58.6 267.2 92 586 +1995 11 1 12 16 PATTY 59.0 322.7 158 807 +1987 6 24 12 8 JOYCE 43.2 346.6 63 141 +1995 8 20 6 2 HELENE 32.4 197.1 92 840 +1959 8 14 0 28 OSCAR 29.4 269.7 82 28 +1958 6 1 0 8 RAFAEL 32.3 67.0 145 780 +1968 4 28 6 24 LESLIE 48.7 9.8 40 130 +1975 11 20 6 18 RAFAEL 13.0 292.2 148 227 +1978 3 13 6 12 ISAAC 66.2 190.3 82 122 +1970 4 26 0 11 NADINE 27.1 22.4 145 92 +1968 7 2 0 5 ALBERTO 53.7 310.4 65 212 +1973 3 24 12 12 VALERIE 58.3 157.3 160 894 +1983 4 1 18 10 PATTY 63.8 6.6 16 231 +1966 10 19 18 10 MICHAEL 9.7 11.2 92 428 +1980 4 18 12 1 RAFAEL 58.2 24.8 66 89 +1985 5 8 0 5 ERNESTO 41.3 264.9 116 804 +1990 10 22 0 28 ISAAC 65.8 85.1 67 191 +1987 2 25 0 7 MICHAEL 22.4 176.5 150 509 +1950 4 9 0 17 ISAAC 60.7 297.6 53 250 +1959 6 14 0 4 HELENE 68.5 43.8 69 378 +1951 9 27 0 13 CHRIS 66.4 288.0 154 781 +1986 3 5 12 24 RAFAEL 21.9 67.0 147 212 +1954 4 20 18 11 LESLIE 20.5 193.7 69 810 +1961 3 17 12 24 MICHAEL 50.3 356.9 119 247 +1959 6 28 6 11 SANDY 33.7 162.5 139 460 +1992 11 2 0 18 NADINE 26.0 329.4 15 149 +1999 8 4 0 15 HELENE 22.8 229.2 81 47 +1951 11 2 18 20 ISAAC 7.4 194.0 62 377 +1997 8 16 6 26 RAFAEL 50.1 84.9 52 541 +1968 5 12 12 7 BERYL 16.1 293.8 130 324 +1973 10 11 12 19 BERYL 66.3 93.4 81 16 +1996 9 19 6 15 LESLIE 49.8 69.0 58 510 +1964 5 3 18 16 TONY 49.3 124.1 125 592 +1966 1 26 0 8 WILLIAM 35.3 102.1 47 738 +1995 7 15 12 17 JOYCE 40.1 128.7 135 351 +1981 9 14 6 7 PATTY 54.6 273.0 114 760 +1966 12 28 18 19 MICHAEL 52.9 63.6 107 510 +1987 3 9 18 14 HELENE 63.2 345.8 11 891 +1958 7 7 12 21 HELENE 39.9 337.4 73 747 +1999 4 16 12 16 VALERIE 19.6 233.3 58 152 +1984 2 5 12 6 MICHAEL 39.6 39.0 40 268 +1966 3 16 18 5 JOYCE 48.6 196.2 151 851 +1994 3 27 6 15 GORDON 60.6 91.8 164 218 +1995 9 21 18 1 RAFAEL 35.4 230.3 146 282 +1999 8 28 0 5 JOYCE 64.5 0.9 28 86 +1975 11 15 12 5 CHRIS 47.0 0.7 68 456 +1966 8 20 18 3 VALERIE 32.9 152.2 76 316 +1991 2 28 12 23 CHRIS 40.3 277.7 156 749 +1958 12 11 12 28 ALBERTO 16.2 273.5 154 511 +1950 9 26 12 10 WILLIAM 16.2 187.7 53 782 +1992 2 19 12 5 NADINE 17.1 177.4 66 719 +1981 5 16 6 27 CHRIS 54.3 178.4 79 275 +1966 11 19 18 1 TONY 60.4 151.6 148 885 +1962 3 8 18 17 SANDY 63.5 140.6 22 526 +1954 6 28 12 7 HELENE 33.2 138.3 80 704 +1986 12 22 0 20 SANDY 13.9 144.5 114 122 +2004 2 15 12 3 FLORENCE 10.1 129.7 68 758 +2002 10 21 6 14 OSCAR 11.4 256.1 127 609 +1970 4 9 6 13 ISAAC 29.2 281.7 52 282 +1995 5 13 18 24 VALERIE 29.0 283.1 98 51 +1978 1 17 12 3 LESLIE 58.0 218.8 74 28 +1957 2 15 6 28 DEBBY 10.1 283.4 23 577 +1957 5 27 6 27 HELENE 40.6 46.3 90 255 +1982 1 1 12 9 VALERIE 51.6 117.8 67 70 +1971 8 6 18 3 SANDY 46.6 176.0 101 662 +1976 8 17 18 4 DEBBY 65.4 106.2 57 746 +1970 6 21 0 26 VALERIE 58.5 206.9 90 201 +1971 8 20 0 27 HELENE 33.8 197.4 110 444 +1984 12 1 12 14 JOYCE 53.2 308.4 29 185 +1992 9 2 12 25 KIRK 13.8 193.6 141 529 +1989 11 27 6 2 LESLIE 37.6 216.2 119 139 +1992 4 18 0 16 FLORENCE 27.2 100.6 147 572 +1985 4 2 12 6 VALERIE 69.3 254.5 68 641 +1958 4 7 18 10 ERNESTO 15.8 158.2 147 15 +1951 5 2 0 28 LESLIE 46.3 319.2 50 479 +1985 1 1 18 12 CHRIS 59.3 6.0 125 3 +1961 8 18 18 8 KIRK 18.7 143.9 22 574 +1989 5 5 18 10 ERNESTO 57.1 279.6 147 408 +1971 12 5 0 18 PATTY 38.4 135.2 24 755 +1993 6 15 12 18 ALBERTO 55.1 212.7 36 375 +1961 4 1 12 11 HELENE 58.1 326.0 128 668 +1982 12 10 12 4 GORDON 58.2 230.7 147 463 +1987 3 18 0 7 WILLIAM 19.2 64.0 124 248 +1990 4 9 12 19 SANDY 9.3 160.4 143 222 +2000 10 14 12 26 BERYL 29.7 185.0 105 587 +1996 11 15 0 7 VALERIE 68.7 217.4 37 101 +1954 6 15 12 22 PATTY 21.7 267.5 14 712 +1975 5 12 0 3 ISAAC 21.7 140.3 122 562 +1961 1 4 6 10 KIRK 22.4 16.0 134 725 +1959 5 19 12 26 VALERIE 50.7 219.9 137 279 +1988 2 8 0 28 LESLIE 69.8 80.0 64 497 +1981 3 11 0 20 ALBERTO 66.2 329.2 40 899 +1966 5 5 6 26 CHRIS 64.9 124.1 74 855 +1963 8 14 0 2 ERNESTO 21.8 298.9 162 413 +1953 1 9 12 4 GORDON 50.1 236.5 90 471 +1992 11 17 0 28 ISAAC 16.9 20.0 59 90 +1992 1 25 12 12 MICHAEL 28.7 39.2 42 670 +1969 3 27 0 9 LESLIE 55.6 46.3 104 201 +1978 8 25 18 5 ERNESTO 40.1 53.1 88 806 +1995 4 23 0 20 ERNESTO 62.7 104.5 27 102 +1993 11 23 18 12 DEBBY 53.7 3.5 87 165 +1953 10 11 0 8 CHRIS 48.8 326.2 19 879 +1990 8 2 12 21 ALBERTO 27.3 146.7 32 461 +1984 10 15 12 28 ALBERTO 18.4 94.1 149 343 +1974 12 9 12 25 ERNESTO 39.4 295.2 144 811 +2003 5 9 12 15 HELENE 29.1 90.5 56 701 +1972 1 10 0 15 JOYCE 44.3 341.6 74 830 +1966 10 16 0 13 SANDY 29.9 36.8 94 533 +2002 6 21 18 16 BERYL 7.2 310.0 104 851 +1986 5 21 12 13 RAFAEL 21.6 282.4 131 460 +1960 9 13 0 21 VALERIE 34.9 298.9 106 531 +1978 7 16 18 25 NADINE 61.4 134.4 115 729 +1989 8 15 12 7 LESLIE 32.7 241.9 23 420 +1964 5 22 6 18 SANDY 29.7 232.8 145 529 +1967 11 15 6 18 JOYCE 34.4 128.3 14 106 +1999 4 6 12 11 VALERIE 13.0 71.8 47 35 +1969 7 27 18 8 PATTY 43.6 181.4 137 152 +1992 3 16 18 11 KIRK 47.8 62.4 34 782 +1997 7 27 6 27 ERNESTO 36.1 306.4 70 417 +1955 5 2 18 15 WILLIAM 33.7 104.3 11 606 +1959 2 13 0 24 WILLIAM 9.7 144.6 74 321 +1980 5 7 18 19 PATTY 32.3 20.8 162 216 +1979 11 14 18 2 CHRIS 66.4 252.9 136 369 +1956 5 9 0 6 ALBERTO 52.6 238.2 24 183 +1991 7 10 18 9 DEBBY 64.0 221.4 146 651 +1995 6 1 18 16 NADINE 15.6 116.4 16 187 +1960 12 22 12 4 PATTY 42.2 75.4 59 317 +1994 12 14 0 17 WILLIAM 40.0 150.5 53 38 +1987 7 8 18 12 BERYL 64.4 333.5 116 300 +1988 10 1 18 5 CHRIS 15.7 170.1 62 648 +1963 7 26 6 2 OSCAR 40.7 324.4 152 40 +1962 2 18 6 13 ERNESTO 31.2 81.9 20 143 +1996 11 23 12 1 GORDON 54.8 211.8 104 349 +1966 1 21 18 20 ISAAC 34.9 89.7 132 244 +1984 3 19 6 1 GORDON 23.0 102.6 48 118 +1951 9 18 0 5 SANDY 26.3 171.4 124 820 +1975 5 1 18 26 JOYCE 12.1 7.4 23 800 +1976 1 24 18 28 TONY 60.9 180.3 11 408 +1957 2 4 6 7 VALERIE 34.8 97.3 51 738 +1964 4 10 12 26 TONY 15.8 83.7 81 777 +1993 4 18 12 3 CHRIS 32.5 170.7 77 356 +1983 10 18 18 8 OSCAR 57.9 187.6 137 450 +2002 4 18 6 22 TONY 68.7 106.6 55 272 +1997 1 3 12 11 DEBBY 29.9 141.7 133 831 +1986 3 22 18 25 CHRIS 43.1 354.3 34 559 +1980 12 23 0 15 LESLIE 14.9 230.8 51 226 +1971 11 24 0 10 VALERIE 49.4 122.7 103 634 +1984 12 23 6 3 WILLIAM 44.8 190.1 56 696 +2002 5 7 12 12 SANDY 27.3 24.6 41 742 +1981 1 6 12 6 GORDON 34.2 334.3 151 264 +1975 3 25 6 6 RAFAEL 46.6 254.0 66 78 +1994 2 23 18 6 FLORENCE 49.0 233.9 68 896 +2002 9 17 18 4 SANDY 44.1 15.0 114 430 +2001 9 10 18 9 LESLIE 18.4 101.7 118 721 +1972 3 27 12 1 MICHAEL 14.5 180.6 139 153 +2003 2 19 12 26 WILLIAM 35.7 211.1 140 697 +2002 10 20 12 26 ISAAC 8.5 115.8 158 804 +1993 1 14 12 7 SANDY 55.5 35.9 115 760 +1965 6 6 18 11 FLORENCE 37.9 73.0 119 806 +1962 4 7 0 10 ALBERTO 14.3 98.5 96 131 +1989 3 11 0 1 ALBERTO 50.7 331.1 132 80 +1972 11 2 18 27 LESLIE 37.8 95.6 76 678 +1955 5 5 6 11 DEBBY 8.6 83.0 88 362 +1974 12 13 0 14 CHRIS 47.9 47.2 128 27 +1957 1 24 0 18 CHRIS 38.8 327.3 10 482 +1996 5 22 0 4 OSCAR 20.4 109.4 111 668 +1997 12 20 12 6 HELENE 44.2 336.2 11 679 +1996 9 18 18 28 RAFAEL 20.7 179.7 77 668 +1996 9 27 12 12 ERNESTO 23.7 281.7 125 848 +1989 2 14 12 11 RAFAEL 63.0 330.4 150 389 +1958 12 11 6 11 SANDY 19.4 343.8 62 508 +1975 10 2 18 28 PATTY 54.8 126.3 126 453 +2000 8 20 6 4 LESLIE 48.7 343.1 61 739 +1999 3 24 12 23 OSCAR 33.1 177.5 12 882 +1963 2 22 18 3 ISAAC 11.4 306.3 133 457 +1983 5 21 12 18 FLORENCE 25.9 240.7 88 366 +1991 3 1 12 19 TONY 35.5 127.5 128 857 +1994 12 20 6 8 PATTY 28.6 160.1 69 207 +1991 6 18 0 3 BERYL 50.5 121.5 146 854 +1972 12 14 18 9 BERYL 16.0 220.0 132 395 +1993 4 25 18 11 BERYL 28.8 33.3 21 779 +1967 11 13 18 13 WILLIAM 13.0 12.1 22 886 +1956 5 26 18 20 OSCAR 17.6 56.6 29 852 +1952 10 8 0 9 SANDY 41.4 297.5 79 865 +1997 2 11 0 13 HELENE 10.8 149.5 112 49 +1953 3 10 0 11 PATTY 53.4 142.9 48 563 +1969 10 12 0 14 ISAAC 48.7 271.4 110 637 +1992 3 2 18 11 GORDON 15.3 277.3 10 349 +1963 11 8 6 12 ERNESTO 64.5 202.8 119 267 +2001 2 4 0 6 ERNESTO 31.4 177.1 39 628 +1963 10 26 18 16 BERYL 65.0 341.8 105 768 +1974 7 27 18 19 NADINE 42.5 302.3 31 135 +1958 3 7 12 10 TONY 42.7 349.8 163 848 +2002 7 14 18 7 ISAAC 35.0 164.6 91 424 +1960 6 2 6 8 HELENE 56.8 163.0 110 14 +1993 2 13 18 14 LESLIE 36.7 325.1 127 805 +1972 10 21 18 27 VALERIE 57.8 110.2 47 415 +1991 1 5 6 24 MICHAEL 53.9 346.3 68 289 +1968 5 17 18 6 LESLIE 59.2 209.6 10 354 +1990 3 24 18 24 VALERIE 42.7 272.1 155 281 +1968 9 8 12 4 FLORENCE 55.5 126.5 68 542 +1968 1 5 12 5 VALERIE 17.6 154.7 28 112 +1964 6 12 0 28 FLORENCE 35.5 12.8 76 379 +1998 7 28 6 27 JOYCE 39.7 158.0 25 339 +1970 8 16 18 19 LESLIE 51.7 84.2 138 90 +1971 4 24 12 1 DEBBY 16.5 70.8 101 783 +1997 7 5 18 15 TONY 42.8 100.8 93 672 +1997 11 6 12 22 RAFAEL 7.2 111.2 103 361 +1981 9 27 6 2 HELENE 49.2 342.3 64 448 +1950 9 10 6 11 TONY 26.4 159.4 141 840 +1966 5 8 12 4 MICHAEL 28.0 227.1 26 519 +1978 3 14 0 23 VALERIE 13.7 323.6 114 477 +2004 6 12 6 17 FLORENCE 65.8 247.1 112 502 +1999 3 23 18 8 FLORENCE 23.6 308.6 144 864 +1968 10 27 6 4 JOYCE 12.5 13.1 90 352 +1975 12 6 6 12 OSCAR 43.4 275.6 12 771 +1979 12 1 0 4 JOYCE 59.1 226.4 117 517 +1964 9 19 0 3 NADINE 21.2 167.6 121 655 +1978 5 5 12 11 KIRK 11.7 224.0 54 696 +1978 2 18 6 25 BERYL 47.8 159.5 160 318 +1982 7 15 6 25 PATTY 57.0 104.0 55 486 +1987 12 27 18 13 DEBBY 14.7 246.1 30 208 +1969 11 22 12 28 DEBBY 30.8 328.1 60 336 +1956 3 28 6 3 KIRK 34.0 314.4 101 856 +1958 3 20 0 3 MICHAEL 58.2 222.2 116 105 +1986 5 19 0 16 JOYCE 7.2 334.3 159 605 +2001 9 26 6 23 GORDON 23.2 125.2 100 478 +1965 8 16 18 18 NADINE 49.1 198.1 107 707 +1970 3 28 12 28 ISAAC 9.4 99.9 98 251 +1955 1 23 6 10 PATTY 20.4 222.6 91 285 +1981 11 27 12 26 RAFAEL 56.8 256.6 50 665 +1984 2 3 18 19 LESLIE 62.6 336.8 109 141 +1950 8 25 12 7 BERYL 17.6 187.4 50 788 +2003 12 22 0 8 JOYCE 39.6 351.3 147 31 +2004 7 27 0 20 CHRIS 47.1 324.5 92 848 +1967 3 9 12 25 TONY 49.2 233.3 75 185 +1973 9 11 0 13 SANDY 68.1 182.4 136 339 +1966 11 21 18 8 RAFAEL 50.4 244.2 49 752 +1966 1 19 0 1 RAFAEL 65.3 301.5 90 894 +1963 4 19 12 26 JOYCE 66.3 299.3 163 832 +1997 3 4 0 19 FLORENCE 43.9 22.3 114 692 +1977 4 20 12 8 OSCAR 10.8 247.1 133 320 +2004 1 4 12 18 LESLIE 40.6 207.6 154 137 +1957 4 28 12 23 VALERIE 63.2 236.1 88 307 +1968 6 17 0 12 GORDON 23.5 167.0 67 380 +1964 3 2 18 21 OSCAR 10.9 208.2 110 369 +1973 3 13 6 13 GORDON 44.7 276.4 132 501 +1964 6 23 12 6 GORDON 67.8 242.6 51 777 +1974 3 16 6 23 SANDY 14.7 130.7 116 518 +1996 2 20 6 19 LESLIE 11.7 252.2 48 635 +1974 3 13 0 2 ISAAC 21.0 85.6 40 537 +1998 5 1 18 28 TONY 10.9 240.6 16 305 +1962 8 12 18 21 SANDY 15.3 55.1 122 526 +1955 10 12 0 26 BERYL 46.1 285.6 79 712 +1976 3 20 6 16 NADINE 42.2 94.0 92 734 +2003 12 7 6 11 ERNESTO 12.8 253.6 140 241 +1950 9 28 6 19 CHRIS 41.4 88.3 61 506 +1992 2 4 12 27 ISAAC 64.0 34.0 67 788 +1989 1 4 6 24 WILLIAM 63.5 11.6 91 491 +2001 12 5 18 21 ALBERTO 26.0 340.6 40 686 +1955 11 2 12 22 NADINE 68.8 82.5 34 614 +1983 7 2 6 12 NADINE 8.2 350.0 47 313 +1992 2 2 0 10 VALERIE 58.1 274.7 85 71 +1982 8 11 0 22 PATTY 39.4 258.1 93 459 +1987 11 8 0 12 HELENE 43.4 24.1 153 97 +1951 10 4 0 18 BERYL 15.3 226.2 92 3 +1971 7 16 6 23 CHRIS 22.8 309.5 68 98 +2003 11 6 18 2 TONY 11.3 311.2 30 811 +1968 9 3 6 28 ALBERTO 23.8 121.3 133 147 +1978 3 13 18 4 CHRIS 23.6 50.1 22 137 +1974 4 18 0 24 BERYL 18.6 150.6 46 205 +1957 12 26 6 7 MICHAEL 25.0 157.7 152 472 +1979 1 20 12 19 VALERIE 69.5 314.4 147 203 +1985 1 2 12 18 JOYCE 61.4 7.5 135 109 +1971 4 1 6 5 JOYCE 43.7 307.8 11 41 +1975 10 7 12 27 KIRK 67.5 89.5 68 757 +1964 8 11 6 5 JOYCE 28.4 274.8 140 316 +1962 5 27 6 2 WILLIAM 53.5 44.4 10 815 +1986 11 14 0 25 NADINE 12.1 230.7 149 97 +1981 2 26 0 25 JOYCE 46.7 77.7 23 868 +1950 3 28 18 8 OSCAR 32.7 282.1 122 874 +1965 5 17 0 21 NADINE 43.7 105.5 164 341 +1985 6 25 12 1 ISAAC 27.6 57.1 19 772 +1996 9 13 6 16 ERNESTO 67.6 140.4 92 380 +2004 2 21 0 25 KIRK 24.1 239.9 48 403 +2000 12 11 18 18 NADINE 65.3 223.0 108 291 +1993 5 3 18 5 ALBERTO 48.9 309.8 161 763 +1988 11 10 0 17 TONY 30.1 219.2 101 230 +1950 5 26 18 12 PATTY 41.5 84.6 118 882 +1987 1 26 12 9 NADINE 16.3 41.6 23 547 +1964 5 22 6 19 DEBBY 62.6 127.2 83 285 +1977 3 20 6 16 JOYCE 34.9 167.8 140 841 +1973 2 3 6 9 CHRIS 61.3 348.3 30 766 +1979 6 12 6 15 NADINE 44.7 30.2 106 317 +1958 2 13 0 7 BERYL 15.4 270.8 43 746 +2000 3 7 18 9 OSCAR 60.0 308.9 13 44 +2000 12 19 18 25 CHRIS 51.0 262.7 136 416 +1960 5 17 18 25 OSCAR 59.1 144.1 151 252 +2002 10 17 12 28 HELENE 12.8 328.7 73 137 +1983 4 1 18 13 OSCAR 45.4 229.2 28 764 +1988 6 17 0 17 TONY 54.7 209.2 137 184 +1994 6 5 18 18 DEBBY 28.2 186.7 33 582 +1994 5 4 18 24 JOYCE 28.0 332.3 148 457 +2003 6 14 18 12 JOYCE 25.7 231.5 13 870 +1956 7 22 6 3 KIRK 26.7 281.5 49 798 +2001 5 11 18 24 RAFAEL 40.7 162.4 138 19 +1991 1 2 12 5 FLORENCE 55.1 15.0 107 343 +1976 8 2 18 19 MICHAEL 10.8 36.6 116 29 +1981 8 4 0 22 ISAAC 68.2 216.0 100 768 +1971 11 8 6 13 DEBBY 10.9 183.6 131 227 +1955 7 5 18 27 SANDY 28.3 41.6 112 216 +2001 10 19 0 19 PATTY 27.2 301.6 131 573 +1984 1 3 18 23 FLORENCE 60.7 66.3 78 130 +1982 3 1 6 6 BERYL 31.3 254.5 125 822 +1987 10 22 6 14 WILLIAM 25.4 96.7 52 690 +1963 10 26 12 17 MICHAEL 35.8 124.3 57 318 +2004 3 20 0 27 VALERIE 26.5 7.4 52 278 +1997 6 2 0 22 ISAAC 50.0 127.1 38 770 +1967 12 14 18 26 NADINE 26.7 13.2 50 733 +1989 4 16 6 12 DEBBY 45.3 42.7 109 396 +1979 7 9 18 11 ISAAC 60.5 300.6 103 391 +1976 6 17 18 6 WILLIAM 8.2 150.4 132 107 +2001 7 7 18 5 BERYL 31.0 194.1 44 751 +2002 6 17 0 12 KIRK 9.7 257.6 97 686 +1987 11 20 0 19 ISAAC 28.8 342.4 11 152 +1958 11 14 6 6 TONY 60.8 208.0 13 683 +1971 3 7 6 2 TONY 14.0 112.3 139 776 +1957 3 28 18 9 ERNESTO 15.6 310.7 136 325 +1969 7 22 12 7 RAFAEL 65.0 9.1 111 500 +1983 3 3 12 9 PATTY 51.6 350.9 86 602 +1966 11 24 0 16 OSCAR 11.1 215.5 83 805 +1983 3 4 12 23 MICHAEL 48.8 186.7 85 520 +1971 11 21 12 13 FLORENCE 36.8 81.8 135 845 +1992 10 12 6 1 SANDY 18.5 189.9 135 853 +1979 12 7 6 5 LESLIE 43.3 192.0 160 188 +1958 5 1 12 9 MICHAEL 45.4 47.8 144 73 +1990 12 9 12 14 ERNESTO 51.8 351.5 56 77 +1983 7 26 0 1 BERYL 32.6 76.6 143 861 +1954 4 12 6 27 SANDY 14.1 211.0 38 744 +1993 8 27 12 18 TONY 25.8 260.4 163 508 +1968 2 22 6 2 KIRK 8.3 70.8 42 354 +2004 3 8 0 6 WILLIAM 61.7 307.8 39 880 +1950 4 23 6 21 FLORENCE 31.4 135.2 63 442 +1957 6 1 0 12 GORDON 55.3 281.4 52 298 +1995 5 26 0 20 NADINE 46.7 355.6 124 429 +1992 12 23 18 20 TONY 54.2 251.6 47 12 +1954 7 22 12 1 SANDY 22.2 62.7 133 869 +1961 8 6 0 7 SANDY 38.2 68.2 32 865 +1998 11 25 6 5 ISAAC 67.4 235.2 130 103 +1989 9 22 12 26 MICHAEL 31.7 344.0 86 358 +1969 10 4 0 13 ERNESTO 52.6 287.0 23 758 +1976 3 21 6 2 DEBBY 62.1 21.8 157 325 +1959 11 6 12 3 TONY 28.1 201.2 99 660 +1974 7 13 0 21 NADINE 42.6 169.5 35 716 +1979 10 2 12 1 PATTY 20.9 182.9 159 476 +1954 9 26 12 24 JOYCE 12.0 346.5 57 569 +1994 10 17 12 21 ALBERTO 43.1 184.2 57 286 +2003 1 9 18 25 FLORENCE 50.8 268.0 161 317 +1975 4 16 18 18 VALERIE 32.3 239.7 128 27 +1955 2 27 18 19 JOYCE 9.1 81.1 63 292 +1974 3 28 0 24 ISAAC 39.3 225.2 76 276 +1981 3 13 0 8 MICHAEL 64.6 50.3 31 482 +1960 5 14 6 2 NADINE 27.0 72.6 155 669 +1994 10 1 18 2 OSCAR 50.0 232.1 71 351 +1966 8 20 12 2 FLORENCE 69.6 294.4 33 636 +1952 3 21 12 4 OSCAR 69.6 55.2 69 506 +1967 3 21 12 23 ALBERTO 16.2 310.2 108 816 +1965 7 20 12 20 ALBERTO 68.0 282.0 102 754 +1995 11 26 18 7 GORDON 32.7 217.1 135 841 +1955 1 26 0 23 VALERIE 21.7 89.4 106 248 +1974 8 28 18 10 ERNESTO 35.0 177.9 74 297 +1983 10 14 12 16 OSCAR 34.8 320.7 130 542 +1952 1 17 0 25 ERNESTO 12.5 16.4 87 461 +1966 9 6 0 7 CHRIS 8.2 201.0 49 37 +1955 3 18 0 3 PATTY 20.0 354.1 95 134 +1976 6 7 0 26 VALERIE 26.1 157.1 55 168 +2001 1 18 12 17 GORDON 15.8 127.0 40 342 +1964 3 12 6 10 PATTY 15.9 116.0 155 255 +1963 7 10 6 10 HELENE 60.7 116.7 48 120 +1984 3 17 18 24 GORDON 18.4 11.7 74 474 +2002 3 16 0 17 MICHAEL 29.4 177.4 81 376 +1982 6 3 6 21 FLORENCE 47.8 88.5 84 163 +1998 8 21 18 17 ISAAC 54.7 241.8 41 729 +2001 10 25 0 11 ERNESTO 66.1 240.9 120 894 +1956 3 23 0 17 SANDY 33.3 104.8 101 452 +1961 11 14 0 28 TONY 28.9 219.0 124 842 +2002 3 22 6 22 TONY 16.5 251.0 103 40 +1955 3 3 12 19 FLORENCE 29.1 196.3 88 813 +1984 3 27 12 16 VALERIE 68.3 212.6 111 640 +1991 11 7 18 9 BERYL 29.7 272.8 156 372 +2002 3 6 18 2 MICHAEL 62.1 28.4 20 784 +1996 4 11 12 25 ALBERTO 42.6 195.8 50 63 +1962 7 22 18 9 TONY 43.3 73.6 115 829 +1989 11 26 0 10 HELENE 61.1 82.3 57 343 +2000 10 19 12 18 ERNESTO 58.8 183.6 58 139 +1981 5 21 0 14 MICHAEL 40.2 83.5 122 1 +1954 5 15 0 7 TONY 38.3 324.1 128 779 +1967 3 21 12 14 PATTY 62.6 89.9 41 274 +1960 1 23 12 24 HELENE 16.8 111.0 37 238 +1950 10 28 0 20 KIRK 63.7 319.5 37 763 +1963 6 10 12 11 SANDY 37.6 335.8 51 452 +1998 12 26 6 18 WILLIAM 15.7 75.6 78 414 +2002 8 25 18 12 NADINE 35.5 273.1 60 396 +1966 3 14 6 18 GORDON 27.9 299.5 29 238 +1971 3 2 0 10 VALERIE 17.0 229.2 22 460 +1956 6 22 6 26 LESLIE 15.2 306.6 110 307 +2002 9 10 6 28 DEBBY 69.5 39.9 52 424 +1973 8 28 18 4 CHRIS 11.5 107.2 74 324 +2001 11 14 12 18 RAFAEL 31.1 11.6 48 264 +2001 3 5 18 16 GORDON 26.6 14.6 61 15 +1971 2 3 0 27 ISAAC 58.0 264.9 49 17 +1967 12 16 18 3 ERNESTO 39.1 34.7 109 172 +1964 10 11 0 2 ALBERTO 32.8 25.1 23 399 +1973 8 23 0 2 FLORENCE 68.6 355.0 101 845 +1977 4 16 18 23 NADINE 66.7 200.4 99 115 +2004 2 18 6 3 CHRIS 69.6 236.7 49 245 +1960 4 6 12 21 SANDY 54.1 346.9 57 734 +1971 1 6 6 22 JOYCE 52.4 291.4 125 739 +2003 5 22 12 9 SANDY 19.5 329.8 164 767 +2004 6 22 12 13 KIRK 68.5 329.3 54 649 +1960 5 16 12 18 ERNESTO 49.3 263.2 150 75 +2004 10 11 6 7 SANDY 31.8 132.0 159 218 +1969 7 22 0 9 BERYL 14.5 253.1 63 506 +1975 5 11 12 4 PATTY 18.0 306.3 95 46 +1989 9 19 12 7 ALBERTO 45.3 301.5 155 791 +2000 6 5 18 10 DEBBY 44.2 321.1 70 331 +1994 8 2 18 20 PATTY 9.8 6.4 60 690 +1998 6 26 0 19 HELENE 9.2 324.2 20 815 +1997 9 21 6 5 MICHAEL 16.4 278.8 31 773 +1993 9 21 12 26 WILLIAM 7.8 190.6 43 196 +1974 10 21 6 17 CHRIS 17.6 235.9 57 815 +1998 1 19 6 14 CHRIS 37.5 31.7 12 462 +1968 8 9 6 10 JOYCE 30.1 45.3 30 635 +1984 8 6 0 17 GORDON 41.6 179.8 67 6 +1986 5 27 0 23 KIRK 51.4 139.9 129 328 +2001 6 26 6 15 RAFAEL 18.1 45.0 143 844 +1975 7 1 0 13 NADINE 46.8 145.4 142 848 +1968 4 7 0 3 TONY 31.5 210.8 31 189 +1973 8 5 6 22 WILLIAM 11.3 41.1 84 610 +1997 5 26 0 2 SANDY 44.2 352.9 12 131 +1992 8 20 12 26 BERYL 12.0 186.8 106 422 +1960 11 20 0 16 HELENE 64.5 193.8 156 330 +1963 8 14 6 15 FLORENCE 24.0 135.0 74 651 +1978 1 7 12 16 ERNESTO 8.1 213.1 34 480 +1998 1 24 0 28 ALBERTO 18.8 47.2 142 711 +1996 11 6 12 23 ISAAC 56.9 278.8 94 241 +1995 11 20 0 22 OSCAR 29.7 141.2 41 349 +1973 9 6 18 25 KIRK 41.9 50.1 55 92 +1982 4 13 0 20 ALBERTO 10.5 28.4 10 861 +1980 11 7 0 3 GORDON 22.3 11.7 95 695 +1999 10 19 0 22 JOYCE 15.2 133.4 144 214 +1961 1 13 0 14 LESLIE 40.8 326.8 104 582 +1977 10 7 6 16 SANDY 11.8 61.1 134 858 +1987 11 22 12 4 DEBBY 21.3 77.5 40 450 +1996 1 11 12 12 PATTY 68.9 81.7 14 563 +1953 9 1 6 24 JOYCE 37.7 228.6 43 519 +1969 1 22 12 1 JOYCE 48.6 284.7 144 899 +1970 6 18 6 13 BERYL 43.6 185.5 103 396 +1968 1 27 18 22 TONY 18.4 344.4 30 798 +1976 3 17 18 7 ALBERTO 13.7 146.8 120 6 +1968 3 19 12 28 SANDY 63.4 11.0 111 233 +1995 4 5 0 11 ERNESTO 66.9 162.6 64 662 +1954 5 15 6 6 SANDY 41.7 286.6 70 613 +1989 4 20 6 5 LESLIE 62.1 245.1 88 657 +2002 2 8 12 17 GORDON 27.0 355.2 40 102 +1988 8 10 6 10 ERNESTO 39.1 103.6 52 185 +1957 4 17 0 24 ERNESTO 50.3 294.6 119 72 +1966 4 12 18 27 VALERIE 45.8 115.5 89 72 +1974 5 20 12 22 FLORENCE 32.6 269.6 147 438 +1979 4 12 18 1 GORDON 33.1 0.7 108 638 +1967 1 16 12 24 CHRIS 34.1 183.5 31 358 +1953 3 17 6 15 WILLIAM 8.1 242.0 137 766 +1982 2 2 6 5 LESLIE 67.0 205.0 11 34 +1983 1 27 12 19 CHRIS 47.5 323.4 30 93 +1964 2 24 6 17 BERYL 33.8 175.3 131 233 +1994 6 26 18 13 VALERIE 24.8 102.6 157 116 +2003 12 17 12 13 BERYL 20.9 49.0 120 572 +1970 2 14 0 23 DEBBY 13.6 235.0 82 521 +1964 11 19 18 6 ALBERTO 39.2 182.1 73 733 +2001 8 2 12 19 JOYCE 33.1 148.0 101 290 +1974 4 6 12 26 FLORENCE 41.3 137.8 44 830 +1983 3 16 18 7 ISAAC 33.2 16.2 147 885 +1958 10 19 18 1 PATTY 39.6 203.1 140 416 +1991 9 8 12 10 MICHAEL 40.5 225.3 144 509 +1988 8 15 12 25 MICHAEL 47.4 354.7 67 314 +1960 6 17 0 21 RAFAEL 43.0 95.2 145 706 +1970 10 11 0 2 RAFAEL 13.9 222.7 70 888 +2002 3 9 0 28 PATTY 16.1 232.6 86 36 +1984 3 2 6 15 HELENE 56.2 32.5 60 768 +1993 6 26 0 6 MICHAEL 33.1 30.8 153 573 +1972 6 27 18 25 NADINE 61.7 218.4 91 821 +1964 5 9 6 3 TONY 37.7 103.2 115 474 +1955 3 9 0 4 TONY 48.0 310.7 149 864 +1966 10 17 12 3 RAFAEL 13.8 149.2 24 160 +1984 4 23 6 14 NADINE 58.6 254.8 100 93 +1990 5 13 12 9 GORDON 36.2 235.6 49 734 +2001 3 20 6 3 ALBERTO 52.4 116.7 107 117 +1996 11 25 6 27 ALBERTO 65.4 120.0 122 104 +1996 6 25 0 13 HELENE 46.9 312.7 156 200 +1988 6 28 12 9 HELENE 23.6 299.8 96 851 +1999 1 4 12 28 FLORENCE 16.4 100.6 76 340 +1989 8 12 0 5 WILLIAM 39.9 118.0 142 734 +1989 10 18 18 17 HELENE 60.5 260.4 27 613 +1968 8 26 0 10 LESLIE 33.6 93.8 94 601 +1974 9 21 6 20 ISAAC 63.4 91.3 136 855 +1998 3 19 6 9 DEBBY 33.6 312.3 54 812 +1977 5 24 18 12 OSCAR 29.0 199.6 116 718 +1970 8 5 12 20 LESLIE 56.3 275.5 152 195 +1976 12 12 12 8 FLORENCE 53.7 181.6 72 742 +1971 3 2 0 17 FLORENCE 7.6 72.7 35 812 +1995 9 3 12 13 ALBERTO 43.6 329.9 56 45 +1989 2 8 12 12 GORDON 39.0 143.8 156 47 +1952 12 3 0 6 HELENE 52.9 86.0 87 845 +1959 8 22 12 12 JOYCE 32.9 14.5 144 41 +1981 2 15 12 28 JOYCE 24.9 181.3 64 779 +1963 7 24 0 18 BERYL 59.6 11.1 86 441 +1954 1 16 6 11 ISAAC 37.1 25.0 57 340 +2001 1 7 6 13 KIRK 31.3 265.2 114 152 +1993 11 11 18 26 RAFAEL 57.9 127.3 138 9 +1993 2 4 0 23 KIRK 60.8 203.2 113 331 +1988 7 16 18 15 ERNESTO 30.1 109.8 79 470 +1955 3 4 0 15 RAFAEL 64.5 252.1 43 892 +1976 3 18 12 14 GORDON 34.3 114.1 24 580 +2000 2 9 6 28 PATTY 63.8 159.4 88 655 +1995 4 25 12 5 VALERIE 50.3 165.8 38 602 +1953 1 25 12 17 JOYCE 7.6 222.8 156 297 +1967 11 27 12 22 DEBBY 67.3 117.6 47 604 +1986 10 1 6 25 NADINE 17.8 174.3 88 51 +1968 9 24 12 4 NADINE 64.9 157.5 49 852 +1966 12 26 12 5 TONY 46.2 125.2 148 778 +2003 6 27 18 25 ISAAC 42.3 70.5 132 163 +1969 12 8 12 27 CHRIS 22.8 22.8 20 181 +1992 9 2 12 27 TONY 37.1 52.3 60 400 +1954 5 6 18 26 MICHAEL 12.5 60.5 131 238 +1964 11 20 0 3 NADINE 46.9 134.1 116 244 +1963 7 12 6 18 VALERIE 48.9 211.1 20 851 +1956 6 8 6 4 HELENE 42.1 56.8 89 683 +1961 4 23 12 27 SANDY 45.6 57.8 51 652 +1983 4 20 6 19 LESLIE 17.1 187.7 154 850 +1993 8 5 12 7 OSCAR 32.0 252.1 112 628 +1996 11 21 18 5 JOYCE 31.9 302.1 60 710 +1970 6 22 0 17 HELENE 9.5 343.8 136 647 +1960 3 22 0 11 TONY 46.1 271.8 13 296 +1982 7 1 6 14 DEBBY 36.6 188.5 113 862 +1984 9 22 0 11 GORDON 64.7 342.5 130 243 +1982 1 3 0 22 NADINE 50.3 291.0 152 51 +1971 5 6 18 18 ERNESTO 28.3 191.6 109 642 +1957 12 19 6 24 KIRK 44.6 12.1 133 887 +1978 6 7 6 11 JOYCE 31.0 140.5 119 787 +1988 6 17 6 21 RAFAEL 52.9 120.3 44 239 +1962 8 25 12 10 MICHAEL 24.7 160.7 118 808 +1966 8 5 18 6 FLORENCE 63.3 244.7 163 20 +1967 9 10 18 7 LESLIE 20.6 36.6 103 68 +1958 6 5 12 5 JOYCE 38.8 9.2 57 799 +1951 1 27 12 24 RAFAEL 36.9 132.2 32 334 +1963 6 20 6 13 PATTY 48.0 198.1 79 84 +1995 3 11 6 22 GORDON 36.1 354.7 98 100 +1980 8 24 12 11 NADINE 31.3 199.8 65 295 +1992 11 9 18 9 VALERIE 46.9 241.4 13 162 +1966 7 2 12 26 JOYCE 27.3 357.7 49 651 +1998 11 24 12 19 PATTY 46.0 187.7 50 655 +1985 5 8 6 3 SANDY 60.5 55.5 43 372 +1963 2 28 18 19 ALBERTO 50.1 130.3 109 862 +1958 10 5 12 27 RAFAEL 34.3 324.5 50 70 +1973 5 11 6 25 LESLIE 21.1 220.6 64 136 +1968 2 19 12 8 BERYL 49.9 300.6 127 805 +1963 11 1 12 5 TONY 69.4 200.4 54 713 +1985 10 9 12 7 NADINE 36.0 259.6 143 318 +1983 1 25 0 10 WILLIAM 57.0 347.8 125 527 +1998 10 11 12 5 ERNESTO 12.0 94.0 105 802 +1965 10 12 6 10 GORDON 57.3 71.3 69 712 +1956 2 24 6 8 NADINE 35.0 196.3 31 94 +1975 4 12 0 3 FLORENCE 57.5 92.0 144 20 +1984 11 16 12 15 VALERIE 35.9 199.9 139 784 +1960 10 26 6 21 OSCAR 46.8 293.2 61 134 +1963 7 27 12 28 ALBERTO 42.8 250.0 66 889 +1951 9 2 12 16 DEBBY 56.9 349.1 11 471 +1967 11 13 18 10 OSCAR 14.8 81.3 151 610 +1984 11 2 18 5 NADINE 26.2 5.2 110 122 +1955 3 17 12 3 ALBERTO 23.3 146.5 110 131 +1967 8 25 6 12 TONY 32.6 127.9 87 89 +1975 11 12 0 24 SANDY 33.4 63.5 74 863 +1984 4 6 0 10 ALBERTO 62.1 144.1 82 181 +1980 2 25 0 23 NADINE 53.0 103.9 94 377 +1955 2 20 6 21 VALERIE 13.5 261.2 144 500 +1960 12 25 18 3 LESLIE 62.3 26.1 163 508 +2000 9 4 6 14 FLORENCE 14.6 219.0 87 872 +1991 12 24 12 27 VALERIE 45.9 350.1 149 208 +2004 12 11 6 1 ISAAC 59.6 118.3 140 309 +2003 9 19 0 15 FLORENCE 61.2 102.4 111 582 +1981 10 26 6 25 OSCAR 22.1 190.8 137 836 +1995 4 10 18 21 MICHAEL 9.3 122.0 23 122 +1954 2 28 18 10 BERYL 18.6 295.8 53 95 +1954 7 16 18 3 FLORENCE 65.5 63.4 112 139 +1974 6 13 18 1 ALBERTO 45.7 353.9 37 322 +1995 4 19 6 10 RAFAEL 32.5 234.8 146 56 +1953 12 6 18 28 FLORENCE 27.6 56.6 78 872 +1991 8 24 0 16 KIRK 69.3 320.5 71 233 +1979 12 3 18 4 BERYL 65.8 224.0 35 572 +1952 2 16 18 28 NADINE 25.1 22.0 30 59 +1955 3 5 18 16 ALBERTO 16.8 332.9 135 761 +1981 7 6 0 24 ERNESTO 10.4 76.6 124 800 +1993 5 23 0 11 ERNESTO 52.6 15.1 28 855 +1980 1 8 0 8 JOYCE 33.8 231.6 36 236 +1955 5 19 12 4 NADINE 69.1 81.6 47 385 +1968 1 3 12 24 LESLIE 40.2 37.2 116 542 +1962 4 22 6 22 RAFAEL 51.9 158.2 119 28 +1979 5 21 18 14 GORDON 23.2 72.7 74 872 +1999 8 18 0 4 LESLIE 45.9 176.2 90 503 +1991 2 28 0 22 ALBERTO 41.3 239.5 41 675 +1987 5 16 6 12 SANDY 27.5 12.4 148 159 +1993 9 19 0 28 PATTY 37.1 6.7 149 225 +1985 5 15 6 14 NADINE 24.5 23.5 57 322 +1978 6 16 0 9 FLORENCE 38.8 37.5 25 644 +1956 10 1 0 1 VALERIE 12.5 66.4 50 817 +1977 9 12 12 20 MICHAEL 65.4 260.6 104 648 +1978 12 11 12 18 PATTY 62.4 347.6 114 273 +1995 1 14 18 13 PATTY 56.8 244.9 115 145 +1985 7 18 18 27 PATTY 12.3 195.5 18 624 +1964 12 19 12 7 PATTY 15.1 90.9 84 792 +2004 5 9 0 9 WILLIAM 11.5 28.0 157 821 +1961 6 5 18 27 GORDON 61.2 357.0 73 19 +1961 6 16 6 11 LESLIE 61.8 337.6 46 731 +2004 4 23 18 27 RAFAEL 22.7 227.2 155 327 +1955 1 3 18 23 WILLIAM 60.9 57.9 45 267 +1975 8 1 0 2 TONY 40.0 81.8 92 144 +1958 5 7 12 2 DEBBY 61.9 196.0 84 825 +1957 2 6 18 16 LESLIE 68.3 315.3 27 418 +1956 8 15 18 5 ISAAC 39.7 112.9 126 887 +1966 9 7 18 24 ISAAC 31.7 107.5 43 566 +1976 9 12 6 25 NADINE 39.6 83.8 72 855 +1957 4 14 6 1 VALERIE 36.8 137.7 17 860 +1998 6 19 18 16 WILLIAM 14.1 70.2 24 868 +1962 8 7 18 25 PATTY 39.5 88.4 139 230 +1969 11 12 6 6 VALERIE 7.4 210.4 145 767 +1957 4 23 6 13 VALERIE 9.8 137.0 105 641 +2003 4 22 0 12 SANDY 62.6 17.1 103 418 +2003 8 4 0 8 NADINE 29.8 345.9 75 783 +1963 11 13 0 15 JOYCE 45.4 275.6 150 354 +1981 3 2 18 13 DEBBY 35.2 333.3 119 681 +1994 9 10 6 15 HELENE 16.8 310.4 30 542 +1965 1 3 18 16 GORDON 29.1 117.4 131 205 +1995 12 18 18 17 NADINE 21.0 145.3 56 381 +1981 4 3 18 24 BERYL 11.7 80.4 58 720 +1984 10 27 0 1 GORDON 60.6 322.2 50 94 +1984 1 9 0 26 TONY 36.8 357.9 160 341 +1960 3 22 0 23 RAFAEL 50.7 167.3 108 317 +2001 11 24 0 10 SANDY 43.1 228.8 29 413 +1986 12 19 18 15 TONY 31.5 202.0 106 470 +1964 8 5 18 7 BERYL 56.5 300.5 76 353 +2002 4 4 18 27 SANDY 41.7 338.3 74 618 +1975 4 22 0 5 FLORENCE 26.5 53.7 156 233 +1976 10 26 0 5 ALBERTO 63.3 89.7 43 712 +1973 8 25 6 10 SANDY 52.5 286.6 135 322 +2003 6 4 0 5 DEBBY 50.4 303.4 20 609 +1968 8 22 18 28 PATTY 56.4 174.3 103 740 +1999 11 15 0 12 PATTY 53.1 166.4 92 442 +2004 4 8 12 23 OSCAR 26.1 252.3 127 563 +2004 7 1 18 22 ISAAC 13.7 111.3 163 581 +1978 6 14 18 27 MICHAEL 22.3 328.0 51 848 +1971 7 21 12 16 ALBERTO 64.0 241.4 124 454 +1982 3 18 18 16 GORDON 28.9 147.7 66 355 +1996 3 8 6 24 BERYL 16.6 186.1 144 148 +1979 11 13 6 2 FLORENCE 20.5 27.4 125 624 +1968 10 1 6 28 ALBERTO 11.8 232.2 57 410 +1978 7 17 18 28 CHRIS 54.0 185.7 113 368 +1987 6 7 18 22 GORDON 8.0 41.1 121 728 +1980 1 28 12 14 ERNESTO 54.4 356.6 128 1 +2004 10 6 0 1 ISAAC 67.1 344.2 121 709 +1989 1 12 0 21 WILLIAM 31.0 293.2 97 856 +1976 8 17 12 24 OSCAR 46.5 54.0 46 52 +1988 5 20 0 4 BERYL 49.1 222.0 111 561 +1980 7 10 18 27 OSCAR 46.2 72.9 106 502 +1992 4 23 12 5 GORDON 36.3 315.2 48 634 +1984 11 9 18 8 ISAAC 51.5 133.8 137 201 +1990 3 24 18 23 ISAAC 8.4 201.7 30 43 +1967 11 13 12 9 ISAAC 29.9 156.2 116 625 +1967 4 21 12 13 RAFAEL 67.3 247.6 108 508 +1981 3 2 6 7 ERNESTO 10.5 169.6 75 891 +1991 6 23 0 11 LESLIE 29.6 328.5 14 676 +1961 11 7 12 2 VALERIE 51.4 141.5 77 512 +1995 3 18 18 16 MICHAEL 63.8 141.0 23 208 +1997 7 6 12 1 PATTY 17.2 103.8 11 114 +1970 3 19 6 26 MICHAEL 17.1 332.0 137 432 +1959 12 13 12 9 DEBBY 47.2 357.4 75 491 +1966 7 21 6 8 ISAAC 57.8 147.2 106 651 +1998 1 9 6 28 RAFAEL 67.8 298.3 39 140 +2001 9 15 12 9 BERYL 46.3 130.7 115 159 +1984 1 3 12 15 ALBERTO 14.2 6.7 64 277 +1958 2 21 12 16 BERYL 20.2 191.0 83 314 +1962 10 11 18 27 DEBBY 65.3 250.8 98 118 +1968 7 17 0 20 VALERIE 42.3 24.5 54 41 +1965 12 17 0 16 ALBERTO 30.8 126.5 18 300 +1995 8 12 6 1 DEBBY 23.4 322.7 117 650 +2001 12 5 12 25 ISAAC 15.2 209.4 101 39 +1974 3 2 12 8 VALERIE 57.6 263.2 62 409 +1959 1 4 6 17 ALBERTO 24.4 332.3 31 416 +1971 10 24 18 6 RAFAEL 60.9 274.2 14 43 +1969 6 13 12 16 TONY 37.3 176.4 113 78 +1993 7 15 6 22 RAFAEL 65.2 101.6 130 550 +1980 2 16 18 17 LESLIE 42.3 202.4 29 675 +1959 1 18 12 20 HELENE 55.3 116.4 118 763 +1969 9 1 18 18 HELENE 55.2 17.6 54 377 +2000 10 24 0 17 ALBERTO 57.5 227.6 16 414 +1997 11 12 0 17 DEBBY 35.8 311.7 51 542 +1979 4 11 0 2 LESLIE 16.0 314.2 33 202 +1951 9 11 12 26 LESLIE 23.5 266.6 101 634 +1950 11 25 12 15 OSCAR 59.2 95.5 23 298 +1954 3 20 6 24 OSCAR 49.1 209.2 150 190 +1985 3 18 6 3 RAFAEL 65.6 327.8 121 285 +1967 6 19 0 4 ISAAC 22.9 236.0 14 800 +1964 12 20 18 11 NADINE 31.4 34.3 159 492 +1983 3 8 18 4 MICHAEL 19.9 231.1 92 32 +1955 9 3 12 7 SANDY 30.4 45.8 105 107 +1960 11 21 0 14 SANDY 67.9 307.6 38 648 +1995 9 2 0 15 ISAAC 37.1 227.0 113 485 +1953 6 2 0 16 HELENE 63.7 63.8 138 773 +2002 10 15 18 9 SANDY 58.8 335.3 140 370 +1977 4 14 12 22 MICHAEL 29.3 221.0 14 575 +1983 1 13 12 21 FLORENCE 33.3 268.7 134 458 +1999 1 22 0 21 SANDY 55.1 119.6 36 28 +1951 3 2 18 8 TONY 21.8 202.3 19 178 +1974 7 13 18 9 WILLIAM 35.5 111.6 91 342 +1975 11 19 18 27 BERYL 41.1 254.9 59 281 +1963 4 8 6 16 WILLIAM 47.7 355.9 157 237 +1996 6 18 18 22 BERYL 40.9 107.0 148 350 +1957 9 8 12 18 MICHAEL 57.4 103.3 119 346 +1958 7 15 12 11 HELENE 24.2 95.1 131 312 +2002 10 14 18 22 NADINE 53.1 24.1 72 220 +2001 4 5 6 27 KIRK 56.9 228.6 103 691 +1976 7 12 18 24 KIRK 45.4 271.8 69 882 +1958 4 16 12 10 PATTY 10.4 254.3 10 256 +1996 8 9 6 14 LESLIE 15.1 205.9 149 816 +1990 9 3 0 15 TONY 53.3 357.4 40 204 +1953 6 3 12 9 JOYCE 31.6 251.4 38 254 +1993 4 12 18 16 OSCAR 27.0 324.5 93 698 +1990 2 12 18 12 GORDON 53.8 206.8 80 256 +1969 8 2 6 7 CHRIS 20.8 201.7 66 150 +1975 11 9 6 8 WILLIAM 40.0 261.1 47 672 +1951 8 8 12 26 HELENE 39.1 78.0 84 254 +1971 2 27 18 24 MICHAEL 32.8 33.0 121 556 +1951 10 13 12 13 GORDON 48.7 248.3 28 491 +2003 9 13 6 21 HELENE 65.4 227.7 129 890 +1953 7 4 0 17 ERNESTO 22.1 134.6 151 399 +2004 3 14 12 1 DEBBY 22.4 168.5 147 143 +1990 6 17 0 12 LESLIE 62.2 100.3 77 606 +1994 7 21 6 27 RAFAEL 16.6 164.8 91 146 +1995 6 25 12 28 TONY 57.7 352.1 23 327 +1959 7 14 0 13 OSCAR 14.7 254.1 20 889 +2003 12 8 6 10 VALERIE 26.3 76.8 51 604 +1975 6 13 12 23 NADINE 66.5 43.0 61 826 +1992 5 6 6 20 SANDY 54.2 292.1 143 69 +1951 8 19 6 20 JOYCE 23.3 302.3 128 29 +1956 3 6 18 6 PATTY 13.2 226.5 106 461 +1954 9 8 18 26 RAFAEL 13.1 189.0 100 70 +1993 5 25 12 14 SANDY 25.6 228.2 54 427 +1979 12 20 12 23 BERYL 66.5 133.4 67 742 +1964 11 25 0 21 RAFAEL 53.8 301.8 29 716 +1998 3 19 6 28 OSCAR 56.2 56.0 111 614 +1984 5 5 12 20 ALBERTO 53.6 23.7 68 296 +1988 9 21 0 8 FLORENCE 55.9 96.5 77 181 +1959 9 9 18 10 WILLIAM 54.5 134.0 75 485 +1978 3 8 12 16 LESLIE 23.4 123.4 117 580 +1951 7 11 0 2 CHRIS 44.6 224.5 42 659 +1960 10 15 6 15 LESLIE 35.5 339.2 153 348 +2000 5 18 0 12 LESLIE 14.5 92.6 23 693 +1954 11 19 0 25 TONY 56.9 173.2 24 557 +1978 9 11 6 23 OSCAR 64.9 147.5 38 628 +1999 12 22 6 3 BERYL 49.7 217.0 139 389 +1958 12 26 18 2 ALBERTO 14.4 353.2 100 421 +1979 10 16 0 9 LESLIE 19.3 20.4 160 366 +1986 5 3 18 10 LESLIE 23.3 336.4 147 267 +1969 9 1 18 16 MICHAEL 27.9 302.2 83 692 +1994 3 2 0 8 OSCAR 32.4 200.0 152 5 +1989 3 27 12 4 LESLIE 55.8 133.4 16 554 +2001 4 1 6 27 LESLIE 33.1 329.0 18 399 +1967 7 14 18 21 LESLIE 14.1 24.6 34 720 +1979 4 24 0 1 VALERIE 37.2 25.2 30 787 +1985 6 15 0 9 MICHAEL 45.2 268.2 155 656 +1959 4 17 18 27 NADINE 16.3 29.4 119 418 +1967 7 8 12 6 GORDON 45.8 323.9 35 408 +1963 2 12 12 19 CHRIS 57.6 51.5 129 563 +1979 9 27 18 28 CHRIS 37.3 153.6 33 682 +1957 12 20 18 20 VALERIE 30.4 145.1 10 249 +1959 12 19 6 7 NADINE 20.9 168.9 82 697 +1951 10 14 12 23 GORDON 48.3 269.1 62 758 +1994 9 21 0 23 MICHAEL 12.7 119.8 78 733 +1999 10 23 0 1 PATTY 18.9 179.7 30 210 +1972 5 9 12 17 KIRK 16.1 267.2 139 331 +1964 1 11 18 12 PATTY 33.1 192.1 66 800 +1958 9 2 0 4 GORDON 44.8 158.8 140 166 +1997 6 9 0 14 MICHAEL 65.5 335.6 44 654 +1992 3 13 6 6 BERYL 19.1 268.2 144 585 +1998 10 17 12 1 JOYCE 29.2 295.7 18 815 +1951 1 26 18 15 MICHAEL 53.8 223.7 64 102 +1989 4 18 12 15 PATTY 20.7 57.6 98 41 +1986 7 10 6 4 RAFAEL 7.8 63.5 153 715 +1968 6 20 6 16 CHRIS 59.7 32.0 27 718 +1961 10 21 12 5 SANDY 42.2 99.1 81 243 +1969 3 4 12 9 CHRIS 12.0 86.6 64 331 +1999 5 24 12 10 JOYCE 53.0 253.5 135 46 +1952 4 15 12 12 MICHAEL 45.4 351.0 123 119 +1959 10 20 12 24 LESLIE 17.2 348.5 26 161 +1986 9 24 18 22 MICHAEL 61.1 181.0 77 821 +1972 12 23 18 28 BERYL 68.5 19.8 32 830 +1999 3 20 6 8 TONY 32.3 62.8 16 797 +1959 9 6 12 13 TONY 9.8 44.2 61 577 +1981 2 20 6 19 PATTY 7.5 335.9 155 16 +1974 12 17 12 2 NADINE 24.0 74.1 23 832 +1994 4 5 18 1 CHRIS 58.9 258.4 100 470 +2004 12 10 0 27 ALBERTO 25.0 171.5 119 543 +1971 4 14 6 14 FLORENCE 68.1 136.6 50 280 +1965 3 19 12 15 MICHAEL 9.6 334.8 49 80 +2001 10 14 6 23 FLORENCE 11.8 250.4 158 677 +1994 10 24 12 24 DEBBY 7.5 109.5 126 126 +1987 12 28 6 26 NADINE 46.1 314.0 154 316 +1962 12 12 6 5 LESLIE 21.3 107.5 13 546 +1990 1 24 12 22 ALBERTO 19.4 16.9 35 821 +1952 5 23 18 20 VALERIE 48.2 56.5 12 16 +1950 4 20 6 26 WILLIAM 49.2 13.6 128 322 +1955 12 15 0 12 RAFAEL 25.2 72.7 88 328 +1968 1 25 6 4 TONY 61.6 346.4 135 66 +1968 2 15 18 28 DEBBY 39.4 260.0 61 704 +1995 3 22 6 19 SANDY 36.8 1.8 104 4 +1984 8 17 12 22 ISAAC 29.8 91.5 22 146 +1957 9 11 6 1 CHRIS 49.2 274.1 127 698 +1958 8 19 6 21 SANDY 24.6 241.3 76 116 +2004 6 13 12 9 MICHAEL 24.3 299.5 135 596 +2004 9 18 6 4 KIRK 58.8 34.5 124 670 +1977 2 17 6 11 SANDY 22.5 51.3 104 837 +1975 2 23 0 17 GORDON 48.5 88.6 67 363 +1964 11 3 12 13 BERYL 51.3 53.9 99 85 +1962 2 16 12 20 WILLIAM 49.0 57.2 42 562 +1954 2 24 12 12 JOYCE 65.8 88.1 82 80 +1974 3 19 0 8 CHRIS 18.6 225.9 17 58 +1984 7 12 12 21 NADINE 55.2 197.2 87 428 +1991 6 25 12 21 VALERIE 37.4 192.1 30 35 +1991 4 28 0 17 OSCAR 44.2 246.3 131 313 +1990 9 20 18 5 ISAAC 28.0 180.0 109 742 +1972 11 4 12 27 ERNESTO 43.1 64.5 30 12 +1968 8 6 0 18 TONY 49.4 74.3 92 664 +1998 11 3 12 19 ISAAC 33.0 14.6 142 418 +2003 10 7 0 15 SANDY 20.7 103.1 157 842 +1987 4 6 12 24 SANDY 54.6 32.1 145 832 +1958 11 26 0 18 KIRK 9.3 341.7 150 735 +1974 12 22 0 9 PATTY 26.9 120.6 106 650 +1996 5 23 0 22 ALBERTO 65.8 284.1 71 143 +1996 6 6 18 27 HELENE 18.0 167.3 49 419 +1957 12 15 12 11 GORDON 65.6 307.7 129 428 +1970 7 15 0 9 LESLIE 24.3 255.9 74 455 +1977 8 9 0 24 SANDY 67.9 296.5 145 722 +2002 6 3 18 24 GORDON 49.5 309.9 117 665 +2003 1 20 18 18 ALBERTO 67.1 328.4 43 407 +1994 11 11 18 4 HELENE 16.9 266.8 20 655 +1971 12 17 0 26 RAFAEL 15.3 206.8 85 659 +1967 9 15 12 15 MICHAEL 17.1 306.3 48 18 +1968 6 3 0 22 BERYL 11.4 7.4 92 330 +1998 7 27 18 21 FLORENCE 55.3 251.8 155 647 +1953 6 2 0 26 DEBBY 57.3 171.2 126 176 +2003 9 25 12 5 GORDON 7.0 233.1 30 123 +1984 1 6 0 26 KIRK 36.7 356.2 13 636 +1973 2 26 6 22 BERYL 40.3 204.1 39 871 +1983 11 26 6 6 VALERIE 29.7 357.0 56 664 +1988 6 16 0 15 GORDON 31.2 161.0 37 360 +1963 8 24 12 2 TONY 22.1 20.6 65 711 +1964 9 28 18 14 ISAAC 51.0 353.4 129 499 +2002 1 9 6 10 RAFAEL 25.6 331.3 12 50 +1987 9 6 18 19 BERYL 19.5 175.3 118 702 +1995 11 26 18 6 ALBERTO 13.3 13.9 62 278 +1999 8 28 12 21 TONY 40.6 6.8 18 412 +1959 7 12 6 12 PATTY 61.5 156.0 86 764 +1995 9 9 18 4 NADINE 16.9 166.9 85 436 +1951 4 18 12 11 JOYCE 29.9 331.4 21 430 +1959 12 9 12 6 TONY 68.7 17.4 63 432 +1987 10 5 18 3 ALBERTO 35.8 276.9 96 356 +1983 5 15 0 19 ISAAC 45.2 41.3 146 458 +1980 10 6 6 5 GORDON 25.2 225.1 13 80 +1959 3 27 6 28 SANDY 51.3 329.9 45 285 +1958 1 27 12 8 PATTY 41.1 177.7 102 231 +1978 10 11 18 23 JOYCE 69.8 342.0 76 79 +1973 9 24 6 21 ERNESTO 21.0 50.7 26 463 +1950 4 7 6 21 TONY 31.4 244.0 29 525 +1959 2 16 0 8 ERNESTO 53.6 178.1 90 374 +1979 5 20 0 10 BERYL 24.8 333.2 152 886 +1954 3 1 0 6 FLORENCE 54.7 210.5 71 635 +1995 10 9 6 9 PATTY 20.0 289.7 148 796 +1962 8 5 18 10 BERYL 25.7 220.3 48 661 +1985 12 3 0 13 LESLIE 33.3 298.9 149 734 +1956 4 19 6 15 LESLIE 38.2 4.2 164 283 +1978 12 22 0 18 LESLIE 65.8 335.5 13 695 +1959 9 6 12 1 KIRK 33.8 258.4 36 406 +1997 7 10 0 2 ISAAC 38.9 185.2 126 144 +1955 8 14 18 8 SANDY 24.9 345.3 119 867 +2004 8 19 6 28 LESLIE 20.1 93.2 32 466 +1981 1 21 0 10 KIRK 63.4 235.1 153 401 +1951 5 22 18 21 DEBBY 59.1 239.2 76 22 +1962 10 28 12 2 SANDY 65.8 220.2 58 18 +1981 7 5 0 25 ERNESTO 9.6 41.1 132 781 +2002 12 3 0 2 FLORENCE 47.9 275.9 16 55 +1966 9 18 12 25 ISAAC 18.1 285.2 104 830 +2004 5 8 18 15 WILLIAM 52.0 341.5 56 736 +1996 11 10 6 21 GORDON 32.3 193.8 124 253 +1997 4 9 6 4 GORDON 63.7 141.6 91 133 +1961 5 26 6 16 JOYCE 29.2 265.6 97 539 +1997 1 2 0 14 KIRK 29.0 6.6 63 615 +1980 7 5 6 25 FLORENCE 63.1 125.1 27 612 +1960 1 8 0 12 TONY 34.4 295.5 162 772 +1980 10 6 6 8 SANDY 49.9 72.3 140 634 +2001 7 10 18 19 KIRK 42.8 75.3 129 816 +1951 12 27 12 25 ERNESTO 7.4 318.1 128 666 +1975 5 4 12 23 SANDY 39.3 122.5 47 406 +1969 11 10 18 26 CHRIS 41.5 342.2 92 389 +1994 1 20 6 9 DEBBY 52.8 283.2 110 653 +1956 8 18 12 25 PATTY 40.0 54.5 15 528 +1990 1 21 18 19 SANDY 59.3 40.6 112 347 +1954 11 12 6 14 LESLIE 41.6 153.7 151 205 +1970 10 5 6 28 NADINE 38.3 202.3 21 116 +1957 7 6 12 14 MICHAEL 28.1 113.0 23 722 +1973 11 10 18 6 PATTY 54.3 3.0 62 781 +1961 12 16 0 22 HELENE 13.7 137.2 75 200 +1998 8 1 12 9 DEBBY 64.0 265.7 109 712 +1987 8 6 12 21 NADINE 39.8 134.5 17 515 +1962 8 9 18 22 WILLIAM 10.5 238.7 66 290 +1967 10 1 18 24 NADINE 21.5 31.4 144 481 +1968 5 17 12 16 RAFAEL 43.8 226.4 122 71 +1987 7 6 12 18 BERYL 59.1 49.9 14 55 +2001 9 7 0 13 NADINE 68.9 17.9 103 515 +1956 12 19 18 6 SANDY 44.8 117.7 64 652 +2000 8 3 12 16 BERYL 28.3 110.1 123 351 +1973 6 12 6 16 OSCAR 7.4 144.3 87 801 +2003 11 23 18 8 ALBERTO 58.4 78.1 32 232 +1955 1 3 12 8 OSCAR 66.3 250.4 51 505 +1951 8 14 12 7 BERYL 67.7 125.0 19 538 +1991 6 13 0 27 KIRK 57.2 142.7 141 163 +1971 3 26 12 20 DEBBY 69.2 353.8 36 718 +1989 7 1 12 1 LESLIE 58.3 307.2 61 441 +1961 8 17 0 7 SANDY 7.3 297.7 158 734 +1956 1 20 0 15 DEBBY 40.6 303.3 11 699 +2003 4 8 18 4 SANDY 31.5 278.4 139 644 +2000 12 7 6 24 ISAAC 8.9 131.9 92 581 +1962 3 6 0 21 ISAAC 18.6 179.2 56 170 +1982 6 3 18 3 FLORENCE 57.5 118.3 151 272 +1987 3 1 12 14 JOYCE 10.1 12.5 41 822 +1951 10 24 0 8 ERNESTO 56.0 111.9 83 72 +1993 7 9 12 28 ALBERTO 33.2 220.1 125 665 +1972 6 12 0 11 TONY 60.7 79.7 152 661 +1989 10 22 0 27 BERYL 38.2 243.8 13 423 +1953 6 19 18 28 PATTY 38.0 2.4 12 294 +1954 10 26 12 5 BERYL 8.1 80.1 44 216 +1961 7 17 6 4 GORDON 57.4 89.8 152 135 +1963 11 14 12 23 NADINE 10.5 89.4 33 169 +1984 1 24 0 1 OSCAR 56.4 336.5 16 691 +1981 8 22 12 22 ISAAC 26.8 209.8 15 632 +1968 2 4 18 28 DEBBY 26.5 162.7 155 264 +1959 7 7 12 16 ERNESTO 12.7 284.8 137 21 +1957 3 17 18 1 HELENE 29.1 305.0 50 756 +1974 10 19 12 6 HELENE 57.5 46.0 144 233 +1965 11 4 18 14 VALERIE 48.4 268.6 148 26 +1987 3 26 18 21 SANDY 34.2 176.4 19 45 +1980 9 24 0 23 BERYL 30.4 176.3 23 843 +1951 10 19 18 7 LESLIE 44.3 20.2 87 683 +1963 11 3 6 13 DEBBY 15.8 354.2 137 122 +1964 4 24 18 5 KIRK 68.6 357.3 152 691 +1981 2 20 18 1 ERNESTO 59.2 301.6 57 573 +1973 1 11 0 18 NADINE 65.6 89.8 24 191 +1986 2 13 6 26 VALERIE 49.5 163.1 160 637 +2000 5 3 0 18 KIRK 27.1 88.3 66 498 +1990 4 10 12 1 HELENE 51.5 138.2 147 162 +1987 12 5 18 20 CHRIS 66.1 71.8 150 52 +1954 4 14 0 24 JOYCE 51.0 255.7 71 677 +2001 7 6 18 1 ALBERTO 14.2 20.8 148 334 +1951 2 25 18 17 PATTY 68.0 180.6 56 53 +1958 2 17 18 5 KIRK 18.2 237.1 144 851 +1971 4 14 18 1 FLORENCE 49.1 304.3 133 858 +2004 7 19 18 11 WILLIAM 25.7 347.3 137 695 +1990 8 19 6 26 OSCAR 65.4 31.3 116 820 +1956 8 13 12 6 HELENE 16.8 240.5 86 281 +2004 11 6 18 4 DEBBY 10.6 292.7 32 893 +1974 5 24 6 15 ALBERTO 31.8 72.7 143 41 +1981 5 16 0 7 ISAAC 30.5 171.9 118 418 +1977 1 17 0 2 ISAAC 14.5 11.1 135 525 +1999 1 19 12 15 WILLIAM 18.9 138.9 161 72 +2002 5 20 6 12 SANDY 33.5 126.0 159 137 +1975 9 13 12 26 TONY 15.7 282.4 62 358 +2001 5 26 6 7 BERYL 68.6 233.9 35 752 +1957 3 20 12 7 ALBERTO 68.1 169.3 70 14 +1961 11 2 18 12 HELENE 25.2 352.6 154 148 +1962 7 14 6 4 OSCAR 21.3 273.8 105 279 +1952 3 9 18 27 SANDY 34.2 81.6 155 500 +1983 10 28 0 8 LESLIE 59.5 272.9 95 626 +1958 2 4 12 3 KIRK 53.6 290.3 17 270 +1950 2 12 6 22 PATTY 30.2 302.9 16 628 +1997 1 20 18 15 PATTY 31.3 282.5 85 118 +1983 3 11 18 12 BERYL 61.1 129.0 40 832 +1998 7 12 6 20 RAFAEL 39.2 133.3 138 314 +1962 2 18 18 22 PATTY 22.1 269.7 103 673 +1955 1 9 12 18 JOYCE 35.0 171.2 27 626 +1955 1 11 0 5 HELENE 21.4 288.7 51 660 +1969 5 21 0 18 ISAAC 50.8 23.3 130 21 +1971 9 24 12 11 RAFAEL 32.3 270.9 150 250 +1972 11 26 12 11 KIRK 33.8 182.6 81 661 +1998 4 1 0 14 TONY 60.6 168.4 36 72 +1964 11 24 0 25 LESLIE 60.3 334.4 42 354 +1963 4 16 18 2 HELENE 69.4 162.4 109 241 +1974 1 26 0 10 HELENE 37.0 58.0 145 205 +1953 11 1 12 3 OSCAR 65.9 53.9 111 811 +1999 5 2 6 5 SANDY 22.9 281.4 161 726 +1974 1 10 18 24 MICHAEL 33.7 198.6 26 754 +1952 6 24 0 6 BERYL 15.2 317.4 18 227 +1996 8 27 12 3 OSCAR 12.0 190.0 111 717 +1958 6 4 18 3 FLORENCE 67.4 60.5 14 753 +1983 2 9 12 3 LESLIE 34.7 146.3 92 526 +1968 3 20 0 9 HELENE 59.3 15.4 102 775 +1957 10 5 0 6 VALERIE 24.5 104.4 119 672 +2002 6 17 18 7 ISAAC 26.2 254.3 110 645 +1958 4 22 12 5 ISAAC 44.4 251.9 32 663 +2004 10 21 6 28 VALERIE 48.2 179.8 12 327 +1982 8 8 0 1 GORDON 7.5 187.2 137 227 +1996 5 20 0 14 OSCAR 21.7 65.2 76 472 +1971 3 16 18 20 JOYCE 33.7 293.1 145 287 +1963 9 17 12 27 RAFAEL 11.4 221.1 104 552 +1960 4 25 6 15 JOYCE 37.1 2.0 46 470 +1980 8 10 6 14 CHRIS 51.1 262.6 34 322 +1955 12 15 0 13 NADINE 9.4 76.3 21 29 +1969 1 3 18 14 VALERIE 48.9 311.0 121 258 +1989 9 27 12 14 GORDON 57.2 302.1 127 626 +1976 3 28 0 15 RAFAEL 68.8 345.7 71 558 +1983 5 21 18 20 CHRIS 20.0 152.5 132 517 +1966 1 7 12 8 BERYL 24.9 60.2 110 700 +2004 4 21 6 24 FLORENCE 62.7 299.4 38 42 +1952 3 5 0 11 KIRK 52.5 92.1 144 80 +1986 5 10 6 9 JOYCE 41.8 251.8 139 618 +1990 6 4 0 10 VALERIE 35.6 62.6 55 480 +1985 3 7 18 15 FLORENCE 16.6 265.2 143 383 +2003 6 28 18 16 DEBBY 52.3 145.3 126 728 +1991 12 15 12 15 DEBBY 25.1 122.0 64 164 +1981 9 10 12 22 PATTY 56.7 153.3 54 548 +1959 4 25 6 8 RAFAEL 17.3 280.3 20 431 +1998 1 17 6 2 LESLIE 43.0 242.3 134 863 +2003 9 2 6 6 BERYL 9.6 334.1 78 721 +2004 12 10 18 12 FLORENCE 26.1 349.0 52 35 +1953 7 13 12 26 VALERIE 59.6 117.4 72 497 +1952 12 22 0 26 ALBERTO 13.3 94.8 138 393 +1961 7 21 0 22 VALERIE 66.7 247.1 97 40 +1996 11 1 12 6 MICHAEL 54.6 345.3 153 598 +1962 3 27 0 2 MICHAEL 7.2 265.5 138 648 +1958 3 7 12 15 BERYL 26.0 108.2 136 377 +1979 10 6 12 2 JOYCE 58.2 70.5 63 822 +2002 11 14 18 2 ISAAC 66.9 320.4 55 764 +1951 6 10 18 13 VALERIE 16.5 159.1 112 754 +1957 12 7 6 18 KIRK 8.3 31.9 80 310 +1983 8 20 12 18 SANDY 26.7 181.8 115 760 +2002 6 2 0 28 HELENE 45.8 286.7 135 422 +1952 9 20 12 25 RAFAEL 50.7 46.1 15 107 +1952 2 9 6 14 ALBERTO 18.7 247.1 73 168 +1973 1 9 0 7 DEBBY 56.1 1.5 31 833 +1990 10 10 12 17 ISAAC 62.3 65.5 53 179 +1994 1 9 18 3 SANDY 33.3 287.0 139 508 +1994 9 23 18 22 MICHAEL 64.8 36.7 138 556 +1980 2 19 18 8 GORDON 21.6 117.1 78 756 +1994 9 11 12 1 VALERIE 56.5 280.6 105 117 +1967 2 15 18 28 FLORENCE 65.6 351.4 132 526 +1960 8 25 6 6 WILLIAM 57.4 78.6 133 608 +1993 10 23 18 11 ISAAC 42.8 7.8 47 602 +1962 10 24 18 20 ISAAC 67.2 255.1 147 368 +1983 3 11 12 27 DEBBY 11.9 189.5 56 229 +2001 6 23 18 25 MICHAEL 10.7 252.9 144 28 +1957 5 4 0 19 PATTY 8.8 195.5 24 169 +1950 10 27 18 7 CHRIS 30.5 321.0 71 473 +1980 7 14 12 20 OSCAR 68.6 202.5 78 318 +1995 2 3 6 20 OSCAR 49.9 354.4 124 837 +1980 3 4 6 18 GORDON 8.7 100.1 137 382 +1965 9 27 0 7 HELENE 13.2 188.6 10 343 +1975 9 8 0 26 GORDON 21.2 130.3 98 389 +1962 11 25 18 10 PATTY 45.5 55.8 150 419 +1973 12 21 12 5 DEBBY 43.6 170.1 156 464 +1986 9 11 12 14 VALERIE 20.9 159.5 109 617 +2001 6 19 12 14 OSCAR 22.2 0.3 37 851 +1993 9 22 12 22 LESLIE 55.0 145.5 87 650 +2004 10 4 6 18 OSCAR 41.6 39.3 144 34 +1983 3 15 12 5 HELENE 26.7 288.6 64 721 +1965 10 17 0 19 SANDY 30.7 48.3 158 805 +1954 5 16 18 17 LESLIE 34.4 6.9 97 346 +1959 4 16 18 18 RAFAEL 14.0 241.9 40 281 +1976 11 2 18 9 KIRK 44.1 353.4 152 879 +1994 3 28 6 26 ISAAC 30.0 26.3 51 338 +2002 10 15 0 27 BERYL 22.1 189.6 78 57 +1966 10 20 6 22 VALERIE 17.2 43.2 124 451 +1996 1 9 12 16 CHRIS 52.2 91.7 50 867 +1968 10 18 18 1 PATTY 28.2 295.6 13 488 +1980 4 25 0 4 ERNESTO 46.9 170.2 81 253 +1979 8 13 6 26 VALERIE 27.5 183.1 32 893 +1978 7 28 18 15 FLORENCE 63.5 289.2 22 673 +1957 6 19 0 21 GORDON 14.0 82.2 85 737 +1959 4 13 12 26 PATTY 38.5 221.9 113 451 +1957 9 25 12 18 ISAAC 13.9 128.1 86 635 +1989 5 8 12 2 MICHAEL 58.1 240.3 79 69 +1987 2 19 18 16 BERYL 69.9 165.1 123 572 +1980 2 20 12 3 VALERIE 36.2 238.5 31 376 +1965 6 12 18 2 BERYL 35.2 205.5 144 441 +1990 3 6 6 25 CHRIS 29.7 172.6 128 162 +1972 9 11 12 10 PATTY 53.3 211.4 16 99 +1975 4 4 18 7 ISAAC 22.7 230.8 44 573 +1951 9 10 0 10 VALERIE 8.8 159.1 56 642 +1971 11 15 12 13 MICHAEL 18.3 141.3 140 575 +1974 3 9 18 28 KIRK 45.4 132.9 145 679 +1999 4 10 18 28 BERYL 58.6 271.5 33 423 +2004 4 14 12 28 ALBERTO 57.0 43.4 37 384 +1983 9 9 12 15 JOYCE 12.7 164.6 155 731 +1960 1 24 18 21 LESLIE 58.1 90.2 93 107 +2003 3 2 0 21 PATTY 63.1 208.2 137 168 +2002 5 25 12 19 NADINE 56.8 91.2 53 100 +1982 12 23 18 24 NADINE 14.4 5.1 62 665 +2003 12 7 18 5 GORDON 54.0 204.3 10 659 +1955 10 2 6 3 KIRK 51.9 243.5 67 457 +1991 3 28 18 7 KIRK 38.2 47.8 146 13 +1977 2 12 18 21 OSCAR 25.3 70.9 34 151 +1973 6 25 18 5 CHRIS 9.7 226.1 95 652 +2003 7 4 12 25 DEBBY 19.2 282.2 84 674 +2003 6 17 12 26 MICHAEL 69.7 183.5 126 45 +1982 2 5 18 14 VALERIE 54.4 57.5 151 448 +1958 9 16 18 28 LESLIE 15.7 180.0 159 349 +1975 4 4 18 25 BERYL 29.5 211.0 81 135 +1951 2 3 12 13 HELENE 59.0 27.3 130 654 +1966 12 4 0 22 CHRIS 50.5 189.1 40 885 +2000 5 28 0 26 ALBERTO 65.8 321.4 150 109 +1993 9 8 0 6 FLORENCE 63.0 343.5 64 100 +1953 3 1 0 16 PATTY 35.0 212.8 140 678 +1954 9 3 6 10 TONY 49.0 202.2 102 665 +1956 5 24 6 3 NADINE 40.1 157.6 86 138 +1954 7 23 12 20 CHRIS 52.8 249.1 17 136 +1970 9 11 12 11 PATTY 51.3 7.9 20 11 +1981 11 21 12 17 BERYL 48.3 339.4 48 454 +1966 2 27 6 21 SANDY 11.0 81.1 82 781 +1986 10 14 6 9 NADINE 40.5 40.5 161 93 +1984 11 4 6 26 CHRIS 20.7 296.7 124 650 +1971 3 17 18 19 BERYL 64.4 290.1 115 122 +1960 5 27 0 10 LESLIE 15.0 280.4 80 820 +1990 12 28 18 1 ALBERTO 59.7 282.0 82 324 +1983 2 15 6 23 BERYL 28.9 25.7 134 400 +1998 8 19 0 8 SANDY 54.7 339.5 159 361 +2004 5 23 12 19 MICHAEL 53.8 106.4 28 782 +1960 7 21 12 25 ISAAC 35.7 39.0 94 693 +2004 8 14 18 8 ERNESTO 14.0 5.0 75 55 +1952 12 21 12 17 FLORENCE 20.0 273.6 86 898 +1966 8 21 6 8 KIRK 29.6 216.0 53 730 +1988 11 7 12 3 LESLIE 17.5 317.9 87 895 +1997 5 7 18 6 ERNESTO 47.3 20.6 106 437 +1956 2 24 0 26 HELENE 42.3 271.9 137 557 +1963 8 3 18 22 FLORENCE 53.1 79.9 15 22 +1961 12 1 6 21 CHRIS 31.8 238.2 108 366 +2003 5 21 12 17 DEBBY 42.8 272.9 36 354 +1958 6 26 0 22 ISAAC 34.0 238.2 108 502 +1992 5 5 12 15 DEBBY 20.2 149.3 28 530 +1988 8 19 12 26 OSCAR 55.8 215.6 103 93 +1982 4 14 12 6 BERYL 58.6 107.9 129 109 +1978 10 19 0 6 PATTY 27.6 277.3 12 390 +1957 3 12 12 17 VALERIE 47.5 108.5 120 700 +1950 9 16 12 18 CHRIS 43.0 179.9 110 46 +1993 2 19 0 3 OSCAR 51.0 80.1 84 862 +1959 2 20 18 7 JOYCE 68.6 160.6 31 31 +1980 12 23 18 10 MICHAEL 51.6 3.4 158 17 +2000 11 3 12 1 VALERIE 37.2 124.1 11 720 +1973 9 14 0 7 VALERIE 30.7 29.6 36 282 +1984 3 19 18 3 JOYCE 50.6 48.6 134 96 +1955 3 2 6 3 VALERIE 46.7 94.8 160 476 +1993 8 14 6 25 FLORENCE 24.4 148.2 117 3 +1976 12 18 18 7 FLORENCE 17.1 172.3 73 754 +1969 4 15 6 22 JOYCE 39.7 297.9 127 586 +1961 2 11 12 19 DEBBY 10.2 114.4 76 738 +1997 2 4 6 11 VALERIE 8.7 206.9 33 754 +1995 6 28 12 22 KIRK 44.0 261.2 19 594 +2004 10 20 0 5 KIRK 56.3 287.2 114 508 +1966 7 7 0 26 TONY 63.5 219.0 84 56 +2000 2 15 18 8 OSCAR 23.1 218.3 81 376 +1952 10 14 12 20 DEBBY 62.1 10.6 67 491 +1999 6 18 6 15 VALERIE 65.1 207.4 133 178 +1986 7 6 18 15 DEBBY 16.6 196.1 89 221 +2002 1 17 18 2 VALERIE 57.9 62.6 79 347 +1986 6 14 6 21 LESLIE 53.1 300.2 77 710 +1951 10 27 0 11 PATTY 53.1 106.7 90 841 +1988 3 17 12 15 NADINE 54.5 135.7 31 74 +1987 7 18 0 9 TONY 26.3 338.4 19 71 +1997 8 19 6 2 KIRK 57.4 61.5 137 46 +1965 3 16 6 25 CHRIS 10.9 342.1 121 544 +1953 7 3 18 20 PATTY 37.4 85.8 139 245 +2001 12 1 12 7 ISAAC 35.7 251.2 126 687 +1994 2 16 0 6 TONY 27.8 215.1 144 688 +1985 7 17 12 8 NADINE 61.5 77.2 71 377 +1962 5 16 18 24 WILLIAM 59.8 77.5 15 380 +1991 5 22 6 4 FLORENCE 25.6 49.4 60 307 +1958 3 2 12 2 WILLIAM 28.1 255.9 123 396 +1960 11 4 18 20 OSCAR 28.7 344.4 66 299 +1996 4 5 6 14 FLORENCE 64.6 22.8 21 200 +1950 6 14 18 4 FLORENCE 28.0 352.5 91 560 +1979 11 20 12 3 DEBBY 60.1 329.7 33 252 +1965 6 25 0 15 WILLIAM 33.3 50.9 14 622 +1956 7 6 0 13 JOYCE 69.7 266.8 94 136 +1977 2 13 18 20 RAFAEL 51.8 18.7 19 16 +1973 1 5 0 27 FLORENCE 23.8 253.7 12 646 +1950 2 17 6 2 GORDON 8.5 112.1 90 857 +1953 5 7 12 17 PATTY 59.6 263.4 162 705 +1964 1 23 0 24 GORDON 29.8 33.7 101 826 +1990 7 16 12 2 LESLIE 25.4 348.4 148 665 +1994 3 8 18 23 RAFAEL 46.8 335.7 67 84 +1998 9 24 0 16 OSCAR 47.5 100.9 134 787 +1975 6 25 18 4 FLORENCE 49.9 164.1 10 480 +1975 9 22 6 20 FLORENCE 31.1 302.0 27 378 +1979 6 6 18 25 SANDY 64.5 286.9 84 231 +1991 10 12 12 25 KIRK 47.0 23.9 26 610 +2004 8 5 12 5 JOYCE 9.4 196.6 64 128 +1975 8 19 18 28 VALERIE 44.8 301.3 52 630 +1951 4 7 0 28 DEBBY 51.0 119.6 63 263 +1975 1 5 6 6 WILLIAM 55.1 140.2 90 171 +1987 8 26 6 10 ISAAC 11.6 37.8 62 268 +1957 3 7 0 25 RAFAEL 24.7 164.0 35 115 +1955 12 8 0 12 NADINE 11.0 202.1 90 264 +1966 7 28 18 5 CHRIS 15.1 92.1 64 881 +1991 6 19 6 26 PATTY 48.6 38.4 102 531 +1964 9 11 12 17 BERYL 64.7 206.8 74 460 +1975 3 10 0 28 CHRIS 14.2 241.2 135 806 +1965 10 28 6 14 KIRK 22.3 324.6 33 760 +1950 5 8 0 6 ALBERTO 28.0 68.2 153 751 +1983 7 27 12 18 HELENE 34.3 188.3 100 565 +1977 8 26 18 15 ERNESTO 68.6 58.2 42 246 +1996 3 8 6 4 ISAAC 61.3 214.1 152 707 +1998 3 14 12 14 JOYCE 44.3 332.6 30 602 +1973 4 13 6 19 BERYL 40.9 322.6 124 407 +1962 1 25 0 28 MICHAEL 63.9 257.3 118 842 +2003 3 4 6 8 JOYCE 46.0 293.2 164 639 +1969 4 11 6 26 LESLIE 51.1 209.5 86 154 +1957 4 9 0 21 NADINE 25.4 110.8 47 101 +1971 3 5 12 7 PATTY 57.3 320.8 135 474 +1982 7 26 6 4 MICHAEL 14.6 114.8 107 452 +1992 11 22 6 17 DEBBY 8.8 169.6 136 757 +1970 5 5 0 5 TONY 46.7 255.2 24 470 +1975 5 14 6 5 WILLIAM 45.4 16.7 141 218 +2002 12 11 12 27 DEBBY 16.9 163.1 50 221 +1995 10 4 0 22 GORDON 29.4 265.8 23 103 +1973 1 4 12 4 ALBERTO 15.7 39.9 158 102 +1972 12 21 0 11 ALBERTO 58.0 281.8 115 482 +1951 8 18 0 4 ISAAC 21.4 321.9 93 664 +1963 10 27 12 16 HELENE 37.0 137.6 124 719 +1995 6 8 6 27 ERNESTO 40.2 342.4 38 97 +1956 11 25 12 9 WILLIAM 60.9 32.5 147 9 +1974 6 1 18 14 PATTY 50.0 115.7 32 847 +1996 11 10 12 27 CHRIS 7.3 100.2 158 262 +1976 12 26 12 28 GORDON 20.5 281.4 61 165 +1992 4 7 6 25 JOYCE 29.9 71.8 162 45 +1990 8 26 0 11 WILLIAM 58.7 18.3 56 201 +1974 2 16 12 19 MICHAEL 50.8 118.2 143 99 +1958 5 21 6 11 ALBERTO 69.3 54.2 15 461 +1995 8 9 0 20 WILLIAM 57.4 313.5 154 245 +1952 3 28 18 9 WILLIAM 7.6 164.6 87 726 +1998 8 4 0 12 HELENE 27.7 316.5 64 85 +1993 1 12 6 18 FLORENCE 52.1 96.0 18 881 +1972 11 24 6 1 ISAAC 56.9 240.8 21 713 +1972 4 12 6 1 LESLIE 29.4 47.5 154 478 +2002 11 24 6 5 WILLIAM 44.6 112.8 157 859 +1989 4 14 18 19 TONY 27.8 54.9 147 466 +1997 1 21 12 11 WILLIAM 46.4 287.2 54 527 +1985 10 14 12 19 MICHAEL 57.2 236.8 17 663 +1990 1 9 18 21 BERYL 33.0 256.4 82 340 +1990 4 7 6 19 ERNESTO 67.4 192.9 42 701 +1994 10 9 18 8 MICHAEL 22.4 337.8 86 859 +2000 9 17 18 26 ALBERTO 33.8 98.7 104 777 +1997 10 24 12 28 BERYL 61.9 94.6 129 867 +1968 5 12 12 11 KIRK 40.3 2.8 95 787 +1958 2 4 0 24 GORDON 12.3 3.0 13 727 +1954 1 26 18 16 TONY 44.3 73.6 51 77 +1982 8 17 6 22 VALERIE 18.6 182.3 54 587 +1990 6 7 0 19 KIRK 43.3 77.5 68 167 +2002 12 26 18 22 WILLIAM 26.0 49.4 89 379 +1973 8 15 18 24 OSCAR 38.5 296.8 80 886 +1957 7 8 0 24 VALERIE 9.2 356.4 61 545 +1960 3 10 6 16 TONY 54.1 270.3 88 365 +1990 10 21 6 20 ALBERTO 47.3 43.0 122 515 +2004 5 23 18 18 SANDY 47.3 240.0 131 78 +1992 2 10 18 13 ERNESTO 32.9 221.6 86 428 +1969 2 21 0 4 LESLIE 52.2 243.9 116 638 +1976 6 11 6 16 OSCAR 17.9 229.6 38 509 +1986 1 3 18 26 ERNESTO 25.4 245.5 110 813 +1969 9 28 12 11 TONY 17.0 166.6 102 757 +1984 7 22 0 17 FLORENCE 68.4 317.3 11 119 +2003 9 9 12 1 FLORENCE 49.1 277.6 103 56 +1999 12 2 12 10 KIRK 32.5 188.5 163 10 +1992 6 24 18 22 FLORENCE 9.8 168.8 15 0 +1996 4 18 6 22 JOYCE 59.2 225.8 73 240 +1991 7 13 18 4 SANDY 68.5 122.8 45 783 +1968 12 6 6 3 BERYL 69.1 6.5 25 542 +1953 8 20 6 22 GORDON 58.5 190.3 157 564 +1988 9 2 0 18 ERNESTO 21.5 20.7 138 368 +1984 9 26 18 15 MICHAEL 36.6 337.3 87 361 +1990 11 5 18 13 JOYCE 15.8 202.7 100 335 +1991 12 22 6 26 FLORENCE 55.7 58.8 61 630 +1998 2 11 12 26 RAFAEL 43.4 28.6 24 486 +1973 11 10 0 19 DEBBY 7.6 328.5 163 265 +1950 4 22 12 19 WILLIAM 69.0 272.1 11 463 +2003 10 24 0 25 DEBBY 28.3 16.2 151 591 +1970 10 9 12 7 VALERIE 24.5 154.3 107 572 +1967 7 14 0 18 SANDY 15.2 337.9 32 237 +1974 4 20 12 13 MICHAEL 45.7 55.2 119 433 +1972 8 22 18 9 DEBBY 50.6 130.6 112 507 +1959 2 8 6 25 MICHAEL 23.7 315.7 149 27 +1976 6 10 12 27 NADINE 68.9 43.4 111 731 +1971 10 14 18 11 GORDON 41.3 19.9 97 657 +1961 2 12 6 4 GORDON 32.5 344.1 161 239 +1982 10 11 12 24 GORDON 39.3 192.0 103 275 +2002 6 22 18 12 RAFAEL 10.5 354.9 82 569 +1974 9 17 0 11 KIRK 38.0 163.8 95 106 +1992 1 23 18 8 KIRK 55.9 163.4 27 138 +1993 7 21 12 19 GORDON 19.2 167.4 96 253 +1992 7 2 12 21 CHRIS 21.7 162.2 107 179 +1999 12 5 18 28 TONY 42.6 105.7 73 154 +1989 7 5 0 3 LESLIE 12.5 294.8 17 866 +1980 8 20 12 7 OSCAR 7.5 313.3 26 334 +1971 1 22 18 7 ISAAC 57.3 307.7 44 132 +1991 9 2 18 24 HELENE 68.2 281.4 80 442 +1993 2 10 18 28 JOYCE 47.2 222.1 91 870 +1970 8 11 0 17 ERNESTO 22.8 356.4 155 469 +1978 6 7 0 3 GORDON 47.9 124.8 19 815 +1961 12 15 18 3 FLORENCE 30.1 131.1 98 308 +1997 2 18 18 15 GORDON 28.3 295.3 120 549 +1979 3 25 6 26 MICHAEL 64.0 59.3 59 284 +1959 10 18 18 5 TONY 45.9 261.2 86 233 +1985 5 13 12 4 ALBERTO 32.2 79.7 157 815 +1997 2 20 18 17 ALBERTO 18.9 198.8 103 424 +1981 11 15 6 23 DEBBY 60.8 323.3 135 390 +1956 3 19 18 3 HELENE 67.4 114.2 98 777 +1954 10 22 0 6 BERYL 27.0 270.2 142 856 +1953 3 22 0 21 WILLIAM 37.3 183.8 42 617 +1970 12 9 0 21 FLORENCE 22.6 264.9 108 158 +1954 11 6 0 6 BERYL 40.8 316.2 46 173 +1981 7 8 6 27 CHRIS 58.5 337.3 77 119 +1961 8 13 12 10 BERYL 29.5 296.7 121 526 +1984 12 2 0 6 WILLIAM 63.9 346.1 96 781 +1972 1 8 18 12 OSCAR 56.2 16.4 137 69 +1957 5 9 12 11 CHRIS 23.4 234.3 92 784 +1997 9 1 0 9 BERYL 8.2 5.1 161 644 +1953 4 10 6 16 ERNESTO 13.4 207.9 160 99 +1981 11 14 18 8 ISAAC 65.1 273.4 155 116 +1956 3 26 12 11 DEBBY 69.0 347.4 119 288 +2001 7 9 12 17 ISAAC 8.0 57.0 85 837 +1996 1 15 6 24 SANDY 14.2 287.4 17 759 +1950 11 23 6 7 GORDON 66.4 194.3 74 368 +1996 1 6 12 3 CHRIS 12.0 301.2 117 641 +1955 8 22 6 11 SANDY 52.5 352.7 127 781 +1968 9 10 0 6 RAFAEL 28.9 303.9 40 298 +1987 12 27 0 1 DEBBY 7.5 152.0 107 894 +1961 2 13 6 12 MICHAEL 34.3 137.1 102 384 +1959 4 7 12 21 VALERIE 63.7 267.2 84 757 +1957 4 10 18 15 BERYL 30.3 43.9 40 110 +1969 2 18 18 21 KIRK 54.3 319.6 71 159 +1958 7 23 12 10 MICHAEL 14.8 248.6 93 578 +1961 7 4 18 16 DEBBY 46.5 118.4 21 259 +1999 12 27 18 15 BERYL 7.4 293.5 101 752 +1966 2 2 6 28 CHRIS 69.7 58.6 85 815 +1956 1 20 12 13 HELENE 9.1 136.7 44 396 +2001 11 16 18 28 HELENE 9.3 32.2 106 57 +1971 11 21 18 1 LESLIE 56.7 237.2 97 323 +1991 1 8 0 17 DEBBY 8.8 163.3 164 881 +1994 5 11 18 7 SANDY 52.2 76.3 149 243 +1964 1 12 0 23 VALERIE 45.7 111.6 41 19 +1978 1 25 18 5 GORDON 67.3 9.1 12 587 +1971 3 18 6 28 GORDON 59.4 180.0 140 72 +2002 4 5 6 23 ERNESTO 24.4 135.3 15 65 +1950 5 8 0 24 ISAAC 42.3 44.3 50 29 +1985 5 14 0 21 CHRIS 26.0 297.7 85 483 +1957 2 21 18 15 ALBERTO 11.7 344.5 109 379 +1999 5 18 6 10 OSCAR 27.6 277.5 83 489 +1997 10 16 18 7 PATTY 19.2 240.5 63 291 +1985 1 1 18 28 CHRIS 12.2 103.1 82 370 +1977 8 27 12 1 PATTY 68.2 269.2 91 33 +1987 4 19 12 7 BERYL 13.6 235.5 77 181 +1985 7 5 0 15 PATTY 33.0 174.1 161 480 +1973 1 3 6 23 FLORENCE 10.5 268.0 101 296 +1975 9 6 0 23 PATTY 16.9 172.7 29 252 +1997 12 28 6 8 HELENE 14.8 246.5 51 351 +1976 11 12 6 8 GORDON 66.3 271.1 115 145 +1996 4 6 6 9 GORDON 25.9 53.0 132 448 +1971 1 19 12 25 JOYCE 57.6 70.6 67 80 +1963 6 7 12 28 FLORENCE 42.7 25.6 10 859 +1972 11 25 0 16 VALERIE 26.9 52.9 32 844 +1967 10 27 6 15 VALERIE 67.3 259.4 84 290 +1969 9 18 12 22 WILLIAM 42.7 57.3 78 518 +1956 9 17 6 16 PATTY 57.8 151.2 148 824 +1999 4 15 6 20 ALBERTO 48.2 106.8 41 643 +1966 7 12 0 21 ISAAC 15.7 336.0 150 303 +1950 10 5 0 26 PATTY 44.5 93.2 138 632 +2003 12 28 18 5 BERYL 48.1 90.7 61 83 +1955 2 14 12 5 KIRK 48.7 341.9 32 182 +1978 5 14 6 3 PATTY 69.7 241.8 82 841 +1976 11 27 18 17 HELENE 7.3 349.1 162 209 +1973 11 13 6 8 HELENE 44.4 324.7 142 66 +1991 6 19 18 27 DEBBY 60.8 263.0 141 167 +1968 4 11 6 11 HELENE 58.8 24.3 73 624 +1950 3 12 18 20 GORDON 15.5 292.7 133 646 +1974 3 26 18 2 DEBBY 36.7 42.4 94 484 +1953 1 7 0 4 LESLIE 36.6 246.8 35 307 +1954 11 10 12 19 VALERIE 30.7 35.8 30 790 +1993 6 15 12 7 ALBERTO 58.1 160.1 32 835 +1994 2 6 18 9 LESLIE 51.6 314.5 102 494 +1960 7 2 0 5 NADINE 46.7 320.3 100 862 +1959 11 28 0 16 ERNESTO 17.8 186.1 148 211 +1983 5 6 18 13 ALBERTO 52.9 288.2 17 848 +1995 6 6 6 18 VALERIE 58.2 132.2 25 485 +1993 7 21 12 15 MICHAEL 34.3 255.8 131 577 +1964 2 13 12 25 TONY 62.7 118.3 146 326 +1969 11 5 6 18 ISAAC 29.2 158.9 156 347 +1999 6 13 12 13 CHRIS 41.5 273.7 96 353 +1972 7 12 0 3 ALBERTO 69.7 298.5 122 250 +1956 3 4 6 2 ERNESTO 36.6 191.5 129 97 +1977 4 16 6 4 ISAAC 55.3 168.5 58 700 +1988 5 14 0 15 BERYL 33.8 148.6 17 567 +2004 9 26 12 21 RAFAEL 49.9 259.8 122 806 +1978 5 10 6 15 OSCAR 43.1 48.9 105 162 +1969 2 18 6 4 TONY 37.3 265.3 49 849 +1987 8 26 12 28 KIRK 61.9 267.4 13 614 +1964 1 13 6 19 VALERIE 37.9 5.8 160 748 +2003 9 26 0 3 RAFAEL 58.9 210.5 46 103 +1998 4 18 6 25 ISAAC 28.3 200.6 35 707 +1985 11 13 0 12 PATTY 12.6 143.3 12 821 +1994 4 7 0 27 MICHAEL 14.9 127.3 124 704 +1966 6 6 12 6 KIRK 66.9 100.5 78 189 +1952 11 23 0 1 GORDON 31.4 147.3 95 377 +2001 8 2 0 1 PATTY 44.7 169.3 66 744 +2000 10 14 18 15 WILLIAM 24.4 154.1 60 280 +1973 7 25 12 23 BERYL 67.0 356.8 144 724 +1981 11 27 12 1 MICHAEL 38.3 129.2 115 622 +1952 6 14 6 5 HELENE 63.7 241.9 25 221 +1979 1 1 18 21 PATTY 48.9 17.7 77 557 +1969 12 3 0 24 OSCAR 43.6 185.3 76 621 +1971 5 22 0 15 NADINE 39.1 315.6 161 399 +1967 5 3 6 27 ALBERTO 68.4 29.3 110 762 +1991 1 7 6 13 VALERIE 14.4 88.9 116 511 +1969 8 17 6 26 MICHAEL 65.8 121.8 113 199 +1980 7 22 12 12 PATTY 19.5 154.7 62 616 +2000 1 10 18 17 ISAAC 45.0 270.6 95 688 +1971 10 15 6 13 GORDON 52.3 291.0 15 486 +1997 10 23 12 13 VALERIE 41.1 1.9 61 583 +1955 2 2 6 17 ALBERTO 54.5 188.6 60 551 +1988 6 11 0 11 NADINE 33.1 155.5 56 21 +1976 1 9 18 1 VALERIE 53.4 306.3 73 320 +1952 3 25 18 3 JOYCE 49.6 116.4 25 272 +1997 7 17 12 28 FLORENCE 10.6 325.1 148 375 +1967 5 28 18 13 BERYL 69.4 6.1 163 212 +1959 8 24 12 25 RAFAEL 57.6 221.7 105 653 +1981 8 21 6 21 NADINE 50.0 287.8 75 191 +1979 11 1 12 3 ISAAC 9.8 24.6 131 196 +1951 5 2 12 8 ISAAC 35.3 344.7 92 232 +2001 12 12 12 7 WILLIAM 36.2 290.0 144 891 +1974 3 14 18 21 LESLIE 13.3 252.0 82 598 +1957 4 8 6 16 OSCAR 45.2 161.8 89 835 +1991 4 22 0 14 NADINE 64.1 346.4 115 232 +1998 5 23 6 21 JOYCE 65.1 95.3 69 49 +1998 8 12 12 1 KIRK 47.0 23.2 76 813 +1985 7 23 0 7 JOYCE 22.8 326.5 114 627 +2000 11 13 12 14 WILLIAM 39.3 239.0 66 214 +1961 7 14 18 6 ERNESTO 38.1 97.0 123 185 +1985 8 11 18 23 NADINE 24.0 86.6 119 709 +1996 10 9 0 13 SANDY 40.0 192.7 61 639 +1959 3 22 18 5 JOYCE 39.7 242.1 47 20 +1982 11 16 0 9 ISAAC 22.8 329.3 36 513 +1964 1 22 0 5 WILLIAM 59.0 314.0 110 194 +1951 5 12 12 3 MICHAEL 33.3 105.4 99 462 +1966 1 13 18 14 KIRK 20.2 58.1 159 275 +1972 1 13 18 2 VALERIE 67.6 248.1 13 422 +1989 6 2 12 19 FLORENCE 44.4 355.9 14 813 +1988 4 9 0 25 CHRIS 26.7 152.5 16 177 +1988 11 15 18 4 LESLIE 30.3 96.9 28 444 +1963 6 1 12 10 WILLIAM 23.5 67.0 142 206 +1980 4 4 0 28 RAFAEL 12.8 204.9 119 9 +1995 9 13 0 16 WILLIAM 50.1 349.0 23 201 +1957 11 25 6 15 ALBERTO 19.3 226.0 104 379 +1995 9 18 0 10 WILLIAM 22.4 307.8 151 502 +1967 1 5 18 6 RAFAEL 19.1 258.3 162 144 +1995 6 27 6 28 HELENE 53.2 163.6 161 626 +1967 9 6 6 23 DEBBY 69.3 33.4 87 302 +2004 7 16 6 8 SANDY 41.8 204.2 118 174 +1951 11 1 0 5 ISAAC 47.3 334.4 132 92 +1976 3 11 6 27 VALERIE 14.3 22.9 164 125 +2003 12 14 18 7 RAFAEL 69.9 224.7 135 842 +1987 9 5 12 9 NADINE 27.1 130.0 39 692 +1972 5 14 18 8 GORDON 43.2 2.1 91 496 +1983 9 2 18 18 ALBERTO 66.4 52.2 105 792 +1991 10 25 18 11 PATTY 29.2 109.3 88 401 +1968 7 22 6 28 HELENE 39.0 92.0 164 517 +2003 10 14 12 12 JOYCE 29.4 225.8 39 95 +2002 12 15 6 25 MICHAEL 31.1 26.0 144 769 +1967 7 27 18 14 PATTY 31.2 18.5 21 885 +1981 10 15 12 24 FLORENCE 27.9 3.1 153 205 +1980 7 6 6 14 FLORENCE 57.2 88.5 156 66 +1959 12 15 6 21 VALERIE 23.6 285.1 70 373 +2001 7 1 0 18 JOYCE 33.5 110.6 54 579 +1968 6 24 6 11 SANDY 61.2 333.7 151 769 +1982 1 12 18 2 ERNESTO 34.8 244.3 101 723 +1953 6 25 12 4 JOYCE 55.4 124.5 79 895 +1959 9 21 18 18 CHRIS 56.8 44.6 37 575 +1959 6 12 12 18 VALERIE 7.4 194.0 55 699 +1968 9 20 6 13 MICHAEL 26.6 256.0 32 801 +1994 3 16 6 11 LESLIE 33.6 324.3 134 132 +1996 10 18 6 24 GORDON 48.9 207.7 52 242 +1984 3 1 18 4 JOYCE 37.7 30.7 38 702 +1982 12 5 18 11 TONY 59.3 31.6 151 545 +1966 3 6 18 15 ALBERTO 48.3 34.9 23 549 +1983 2 27 0 18 SANDY 47.6 14.7 33 194 +1964 2 28 18 15 LESLIE 30.5 281.9 78 201 +1967 6 20 18 24 CHRIS 54.5 61.7 150 151 +1964 2 2 0 8 ALBERTO 14.2 269.6 143 743 +1989 10 5 12 4 RAFAEL 59.5 257.1 43 829 +1960 10 17 0 17 VALERIE 16.1 123.2 149 205 +1973 11 23 6 13 MICHAEL 40.9 349.4 33 8 +1995 5 22 12 7 HELENE 28.2 285.5 143 403 +2002 5 4 6 9 BERYL 18.0 41.2 121 453 +1955 3 17 6 19 VALERIE 63.8 208.7 15 59 +1974 5 17 0 16 OSCAR 61.9 297.6 60 889 +1973 7 19 12 27 JOYCE 44.1 213.4 19 284 +1987 6 20 6 9 PATTY 19.2 350.4 49 383 +1959 5 3 12 11 FLORENCE 26.8 298.3 60 451 +1972 2 26 12 10 BERYL 46.9 310.1 110 130 +1990 12 20 6 24 GORDON 20.2 134.8 95 766 +1953 6 10 12 20 HELENE 30.6 134.2 51 129 +1955 6 8 12 23 PATTY 16.7 3.4 164 80 +1993 7 13 18 19 CHRIS 22.6 7.0 25 307 +1965 9 28 0 12 RAFAEL 9.5 160.5 158 221 +1988 2 10 6 5 OSCAR 36.6 355.3 129 211 +1989 12 8 6 2 FLORENCE 8.3 309.9 69 676 +1994 9 20 18 22 ERNESTO 26.6 11.4 24 605 +1962 2 9 0 28 ALBERTO 64.1 309.8 73 490 +1951 10 17 6 9 MICHAEL 26.8 328.3 48 751 +1973 5 26 18 22 MICHAEL 38.1 311.8 59 36 +1973 1 10 6 16 JOYCE 62.8 310.5 59 220 +1968 7 6 0 17 RAFAEL 64.6 41.8 85 578 +2003 7 28 6 25 GORDON 18.2 350.2 161 195 +1958 2 27 6 2 PATTY 23.8 107.8 79 137 +1951 8 20 12 16 KIRK 14.3 339.9 140 207 +1991 4 28 0 23 ISAAC 36.3 154.8 140 776 +1989 4 12 18 20 WILLIAM 53.7 244.5 133 369 +1969 8 2 0 8 JOYCE 68.1 20.1 10 57 +1964 1 10 18 11 GORDON 37.2 14.8 107 189 +1974 12 10 18 16 MICHAEL 18.4 65.6 75 610 +1952 10 15 0 17 DEBBY 48.6 346.1 57 132 +1990 8 21 12 22 LESLIE 12.0 159.7 134 790 +1980 12 28 18 7 BERYL 49.2 113.3 69 849 +2001 5 11 18 11 WILLIAM 34.6 39.6 149 487 +1987 10 15 18 10 ALBERTO 63.0 328.3 96 810 +1982 3 10 6 18 ISAAC 43.2 185.0 64 848 +1964 11 20 6 4 KIRK 23.5 175.2 117 555 +1969 8 13 18 1 SANDY 28.9 27.7 65 548 +1967 2 8 6 15 PATTY 17.5 346.8 95 451 +1963 5 27 12 4 TONY 61.9 254.0 39 76 +1962 7 25 6 17 ALBERTO 17.8 227.2 156 654 +1956 3 21 0 3 TONY 21.7 135.9 143 352 +1971 10 23 12 16 BERYL 20.2 125.2 58 529 +1983 2 6 6 7 VALERIE 49.1 216.3 121 762 +1955 10 26 6 20 FLORENCE 57.6 242.0 117 10 +1990 12 12 18 19 PATTY 59.7 69.4 35 70 +2003 12 5 6 24 SANDY 11.7 115.0 53 523 +1962 6 26 6 25 FLORENCE 9.4 206.9 11 282 +2001 2 27 0 8 ERNESTO 19.4 147.0 22 17 +1953 9 21 0 6 PATTY 10.1 199.2 56 705 +1959 4 24 12 6 WILLIAM 41.7 163.3 133 597 +1969 6 6 18 9 BERYL 9.6 48.1 137 303 +1992 12 15 6 24 NADINE 49.2 33.9 76 431 +2003 4 10 12 19 WILLIAM 41.9 354.6 140 194 +2003 3 11 6 11 DEBBY 42.7 178.1 114 878 +1997 2 20 18 11 FLORENCE 60.9 347.9 135 855 +1962 10 7 12 6 KIRK 43.1 24.3 120 820 +1999 6 19 0 17 ALBERTO 40.2 342.5 121 768 +1959 8 12 0 15 NADINE 39.2 166.1 71 627 +1956 1 24 6 28 MICHAEL 12.0 340.1 139 138 +1990 7 25 0 4 JOYCE 26.8 68.7 155 83 +1974 4 26 18 2 RAFAEL 12.6 191.0 78 297 +1950 9 27 6 5 RAFAEL 57.7 73.0 151 92 +1988 9 8 12 13 VALERIE 19.0 79.6 88 270 +1952 9 8 18 28 NADINE 40.7 165.2 131 333 +1966 3 13 12 19 RAFAEL 24.2 175.4 145 235 +1984 8 2 0 26 JOYCE 61.5 335.5 32 566 +1987 6 17 0 17 RAFAEL 18.7 86.7 144 604 +1959 2 13 18 28 WILLIAM 34.5 63.4 18 747 +1993 7 14 18 17 ISAAC 9.7 301.3 17 459 +1979 5 1 18 11 GORDON 24.3 93.8 101 212 +1984 6 19 0 14 KIRK 39.0 149.4 109 619 +2003 2 19 12 12 ALBERTO 65.9 2.7 52 532 +1992 1 27 12 22 CHRIS 12.0 185.2 64 619 +1963 5 21 12 1 HELENE 44.9 331.7 132 65 +1959 11 23 18 1 FLORENCE 36.4 129.4 74 808 +1971 12 21 0 1 ERNESTO 47.0 44.9 54 29 +2002 3 13 0 19 WILLIAM 64.1 165.3 69 848 +1981 11 27 6 25 OSCAR 43.7 7.4 26 393 +1970 11 17 12 14 FLORENCE 66.8 276.1 157 596 +1981 11 17 18 18 TONY 7.6 19.1 15 422 +2003 6 26 6 11 DEBBY 31.5 106.9 97 847 +1997 6 28 12 17 RAFAEL 36.4 117.8 43 71 +1985 12 27 18 9 VALERIE 32.6 8.7 137 607 +1957 6 24 0 1 JOYCE 49.4 52.2 60 122 +1972 9 11 18 19 OSCAR 58.0 248.7 142 541 +1957 9 18 0 23 TONY 58.8 234.6 104 12 +1969 12 5 6 18 FLORENCE 17.9 7.5 44 484 +2004 8 25 18 13 ISAAC 20.7 225.5 148 553 +1998 11 18 6 5 JOYCE 9.4 8.1 77 269 +1958 4 8 6 17 HELENE 65.6 18.0 128 112 +1988 3 17 18 20 LESLIE 40.8 194.6 141 794 +1992 5 19 12 11 NADINE 19.0 318.8 131 258 +1969 8 18 0 21 OSCAR 52.3 145.4 131 349 +1980 8 2 12 21 ALBERTO 18.0 235.2 158 769 +1981 8 28 18 27 HELENE 34.6 223.6 135 329 +2001 3 11 0 3 FLORENCE 31.0 95.9 121 785 +1969 10 1 6 24 ISAAC 24.3 306.7 91 686 +1970 10 16 0 17 ISAAC 23.2 351.4 84 265 +1954 8 5 12 11 LESLIE 44.3 85.3 134 209 +1967 9 6 0 11 FLORENCE 23.2 256.2 12 290 +1993 5 13 12 13 BERYL 19.7 124.5 56 772 +1966 9 21 6 13 RAFAEL 58.8 256.3 136 617 +1983 5 28 18 11 WILLIAM 45.5 104.0 138 262 +1989 11 1 18 19 LESLIE 23.4 239.3 62 174 +1986 7 8 0 19 DEBBY 51.9 172.1 62 390 +1993 12 24 0 5 CHRIS 29.8 327.3 54 835 +1979 12 2 6 20 DEBBY 69.2 118.2 110 620 +1973 4 12 18 9 ERNESTO 33.2 210.8 41 281 +1996 9 23 6 20 ERNESTO 32.2 51.4 105 193 +1999 1 19 0 20 DEBBY 42.5 316.8 129 596 +1954 8 15 12 6 LESLIE 11.4 310.4 142 204 +2003 7 16 0 20 RAFAEL 48.4 163.9 81 500 +1972 2 23 0 2 TONY 34.4 303.9 46 888 +1993 8 10 18 25 MICHAEL 40.3 129.3 49 276 +1980 10 1 0 2 CHRIS 61.1 252.4 50 547 +1986 4 22 0 2 LESLIE 54.0 35.2 76 206 +1985 11 22 6 13 HELENE 20.1 203.2 163 872 +1971 4 7 6 14 CHRIS 34.1 98.8 63 29 +1987 1 26 6 18 CHRIS 66.3 280.4 29 223 +1950 10 11 6 24 GORDON 8.6 111.4 115 635 +1963 12 15 6 5 GORDON 13.5 273.2 25 39 +1984 1 10 18 9 GORDON 57.2 240.0 116 476 +1983 2 11 0 22 GORDON 42.1 106.4 120 861 +1953 6 14 0 6 MICHAEL 18.1 2.6 34 118 +1982 8 14 12 20 HELENE 64.0 65.6 125 786 +1992 10 1 18 23 JOYCE 37.6 291.4 125 690 +1959 8 25 6 24 FLORENCE 48.3 182.8 70 456 +1953 5 15 12 26 ISAAC 61.3 329.4 139 523 +1964 8 28 12 5 KIRK 67.2 33.1 29 899 +1991 4 28 18 21 ISAAC 46.3 125.6 13 871 +1972 1 28 12 7 ALBERTO 48.3 63.7 27 893 +1992 6 21 0 23 CHRIS 10.6 154.0 104 695 +1969 4 13 0 17 SANDY 9.0 254.5 127 750 +1957 9 18 6 13 BERYL 26.7 248.6 143 414 +1953 9 24 12 27 KIRK 25.1 310.1 52 846 +1976 2 4 12 4 ERNESTO 31.7 326.6 107 467 +1957 9 21 6 15 KIRK 9.5 171.7 19 563 +1987 1 25 6 7 LESLIE 68.0 30.7 142 554 +1996 1 19 0 15 BERYL 9.5 229.3 98 146 +1959 5 4 6 20 TONY 16.6 258.6 149 173 +1960 3 2 0 18 SANDY 45.9 276.5 75 767 +1993 6 19 18 5 WILLIAM 51.2 101.2 104 526 +1965 2 28 0 6 NADINE 47.7 60.1 88 461 +1959 10 28 0 2 PATTY 50.7 219.7 130 484 +1980 9 9 18 13 CHRIS 54.7 223.3 114 269 +1992 5 25 18 8 VALERIE 37.6 222.9 30 581 +2004 3 10 6 28 KIRK 35.4 65.8 73 290 +1958 10 17 18 7 TONY 52.5 116.3 152 723 +1983 5 11 18 20 RAFAEL 47.8 69.5 151 67 +1979 8 20 0 21 TONY 67.7 311.5 61 329 +1970 4 27 12 28 JOYCE 45.5 36.8 154 218 +1954 2 24 6 23 ERNESTO 46.9 272.6 128 560 +1953 12 1 6 22 GORDON 54.1 56.7 64 557 +1981 8 24 12 8 RAFAEL 21.6 45.9 124 536 +1979 2 14 0 21 OSCAR 19.3 133.6 22 530 +1977 2 19 18 23 JOYCE 39.7 56.9 110 577 +1953 1 11 12 12 ALBERTO 65.2 149.6 157 677 +1998 12 24 12 9 SANDY 52.2 214.1 93 82 +1985 9 21 0 5 VALERIE 34.5 163.0 110 831 +1997 10 11 0 9 LESLIE 15.9 71.2 105 53 +1981 4 15 0 3 RAFAEL 11.2 9.6 79 575 +1952 11 25 0 23 BERYL 9.2 262.7 57 480 +1961 1 6 0 19 MICHAEL 50.3 320.1 48 702 +1955 9 11 12 28 VALERIE 42.4 101.9 129 867 +1977 11 14 12 13 KIRK 61.9 272.1 156 874 +1999 7 17 0 20 LESLIE 23.4 197.7 54 70 +1954 6 26 0 20 DEBBY 25.8 77.8 105 339 +2004 10 28 6 18 WILLIAM 32.7 78.3 164 605 +1983 2 4 12 14 GORDON 34.1 137.8 113 724 +1979 5 14 6 10 CHRIS 59.8 162.2 133 275 +1987 8 10 18 9 VALERIE 19.4 77.2 127 342 +1997 10 4 0 24 VALERIE 12.7 34.0 57 836 +1995 5 11 6 10 DEBBY 23.3 1.7 130 185 +1985 2 21 18 22 HELENE 21.4 209.4 153 630 +2000 11 1 18 1 ISAAC 54.5 228.4 86 313 +1966 2 12 12 12 PATTY 35.1 222.9 134 193 +1952 6 3 0 27 JOYCE 55.2 91.8 39 245 +1961 2 26 0 1 RAFAEL 24.6 212.9 101 305 +1951 11 11 0 19 SANDY 21.9 88.1 135 758 +2000 4 9 0 23 KIRK 36.0 271.2 121 403 +1992 12 8 12 9 NADINE 68.7 134.3 139 338 +1962 7 22 6 27 MICHAEL 50.6 72.8 105 679 +1986 4 6 18 6 ERNESTO 14.2 332.6 120 810 +1980 5 19 0 27 PATTY 31.2 277.6 156 60 +1950 12 6 6 27 PATTY 35.8 264.3 123 635 +1982 10 10 18 8 PATTY 50.3 63.9 135 179 +1980 2 20 0 13 HELENE 68.6 75.1 72 425 +1974 4 17 18 14 ISAAC 24.4 352.2 108 467 +1957 11 11 6 19 LESLIE 18.5 134.2 87 210 +2003 3 9 12 25 VALERIE 19.9 73.0 140 471 +1951 11 10 18 15 ALBERTO 18.9 27.7 109 885 +1988 10 19 18 22 OSCAR 37.8 202.3 141 394 +1981 4 16 18 28 ISAAC 29.0 317.5 70 55 +1995 6 15 6 14 KIRK 34.0 309.5 141 504 +1998 1 9 18 3 RAFAEL 31.2 86.2 50 514 +1994 7 6 0 27 NADINE 52.8 76.6 86 390 +1950 8 6 18 1 ERNESTO 69.9 278.1 47 122 +1977 2 3 6 10 OSCAR 66.0 261.3 137 737 +1950 9 5 0 11 SANDY 63.7 110.0 24 680 +1983 5 26 18 21 ISAAC 7.9 74.1 58 603 +1986 1 12 18 9 VALERIE 13.6 24.3 65 538 +2001 8 2 12 8 CHRIS 64.3 199.8 132 559 +1953 7 27 12 23 MICHAEL 18.5 255.0 125 895 +1954 7 8 18 28 DEBBY 15.6 81.0 20 99 +1980 6 26 0 5 ERNESTO 41.8 33.0 29 110 +1998 8 6 12 16 KIRK 62.7 73.6 150 837 +1967 9 15 6 4 DEBBY 53.3 39.7 61 60 +1992 2 21 0 15 HELENE 46.4 194.3 93 834 +1981 7 14 0 4 PATTY 11.9 326.5 60 679 +1954 4 9 6 9 HELENE 61.6 79.0 68 729 +2001 11 9 18 19 FLORENCE 64.6 45.2 118 775 +1992 2 21 6 26 KIRK 54.4 199.2 160 794 +1970 9 7 12 3 DEBBY 21.8 60.3 90 126 +1972 7 12 0 1 BERYL 38.9 235.0 106 566 +1998 9 13 18 19 ALBERTO 20.7 176.1 55 490 +1968 9 6 12 5 WILLIAM 40.0 231.6 164 341 +1975 10 4 0 25 FLORENCE 8.7 199.2 33 321 +1997 12 12 18 4 ALBERTO 58.9 89.4 46 427 +1989 4 21 12 23 HELENE 19.5 252.8 146 223 +1998 12 2 6 23 ISAAC 23.6 149.9 92 618 +1961 6 3 0 12 ALBERTO 12.3 106.7 13 474 +1958 7 1 18 14 RAFAEL 47.1 201.3 65 67 +1954 8 16 12 18 SANDY 68.6 222.1 97 315 +1983 10 13 18 13 VALERIE 11.0 330.9 90 5 +1956 7 13 0 18 SANDY 35.6 280.3 36 650 +1989 11 17 12 6 BERYL 15.2 58.7 86 61 +1954 7 15 0 9 ISAAC 66.6 129.0 27 213 +1988 4 15 0 27 SANDY 14.9 337.4 31 432 +1982 1 1 12 22 ERNESTO 63.3 292.2 10 642 +1979 9 7 18 11 ERNESTO 10.8 3.2 142 168 +1955 9 25 12 3 OSCAR 28.4 27.8 27 340 +1957 10 23 6 7 CHRIS 42.6 20.8 60 750 +1990 1 17 6 20 LESLIE 19.2 254.2 139 401 +1971 3 22 0 1 PATTY 42.2 14.2 149 538 +1977 6 8 12 28 FLORENCE 51.1 332.0 118 310 +1988 3 13 12 25 OSCAR 26.1 132.2 37 27 +1971 10 7 18 1 GORDON 29.8 294.9 66 595 +1970 3 11 18 4 PATTY 39.4 347.1 161 633 +1964 10 23 6 3 BERYL 19.0 76.7 139 512 +1986 3 12 12 4 DEBBY 28.4 120.6 17 625 +2004 8 22 0 26 OSCAR 40.0 185.0 128 398 +2002 9 25 18 16 FLORENCE 8.3 291.7 42 538 +1982 10 14 0 19 LESLIE 37.6 119.4 37 174 +1953 8 7 12 16 ERNESTO 18.9 71.9 140 302 +1951 5 20 6 27 CHRIS 59.1 54.1 161 558 +2003 12 24 6 23 RAFAEL 26.1 145.3 121 200 +1969 5 26 18 6 KIRK 11.0 124.2 106 80 +1973 5 14 12 10 ISAAC 30.7 298.0 144 381 +1952 2 2 12 24 TONY 11.4 250.2 30 485 +1995 8 5 0 16 WILLIAM 56.6 193.2 77 627 +1968 1 1 18 21 ISAAC 8.7 27.5 22 198 +1950 4 6 18 12 GORDON 30.4 2.2 153 757 +1952 2 28 18 28 JOYCE 61.5 213.1 69 440 +1958 1 7 0 27 ALBERTO 38.9 91.8 100 344 +1957 1 14 12 2 FLORENCE 21.0 47.0 115 587 +1958 10 21 6 1 ERNESTO 17.3 64.3 27 535 +1953 12 13 18 12 ERNESTO 44.5 24.3 45 678 +1963 9 14 18 23 WILLIAM 46.7 46.6 63 666 +1973 7 27 18 14 WILLIAM 30.8 310.1 160 633 +1976 2 24 18 23 BERYL 63.9 334.8 144 270 +2002 9 23 6 16 ERNESTO 27.9 201.2 136 870 +2002 9 18 12 7 BERYL 52.9 141.1 45 45 +1950 2 16 18 4 RAFAEL 49.9 10.2 31 515 +2002 7 6 6 1 NADINE 46.1 122.6 10 829 +1985 7 23 12 14 HELENE 56.8 297.6 16 42 +1953 6 14 18 10 CHRIS 40.2 59.0 110 747 +1961 10 12 0 14 PATTY 40.9 79.0 94 414 +1965 12 12 0 15 MICHAEL 27.4 125.8 31 864 +1955 11 18 18 26 NADINE 33.3 281.9 155 409 +1954 12 10 6 19 VALERIE 20.7 27.4 125 633 +1954 3 11 0 18 GORDON 30.1 120.1 75 5 +1950 11 13 0 9 JOYCE 11.6 28.5 123 380 +1994 1 1 12 8 ALBERTO 24.7 135.7 22 827 +1965 6 1 6 28 DEBBY 40.2 153.5 55 411 +1968 10 28 18 24 MICHAEL 26.2 151.6 119 16 +1993 2 1 6 4 GORDON 14.2 2.6 93 673 +1984 10 22 6 1 DEBBY 20.2 74.6 83 674 +2000 6 9 6 26 ISAAC 25.0 20.7 41 614 +1982 10 3 0 7 SANDY 59.3 191.7 129 81 +1995 10 24 18 18 MICHAEL 40.9 313.3 152 306 +1950 5 19 6 23 DEBBY 22.0 139.3 78 883 +1998 2 12 0 9 ISAAC 37.1 49.0 96 277 +1985 10 8 6 23 MICHAEL 50.3 236.5 28 116 +1999 7 25 18 5 WILLIAM 21.2 188.2 135 842 +1968 9 16 12 26 RAFAEL 36.8 330.3 18 807 +1952 11 21 18 25 ALBERTO 51.7 0.0 132 282 +1992 2 26 12 8 DEBBY 37.9 183.4 122 414 +1990 11 12 0 21 RAFAEL 69.2 139.1 138 13 +1959 4 17 6 20 OSCAR 32.8 143.7 72 238 +1976 4 7 18 5 ISAAC 15.3 331.3 30 239 +1968 1 1 0 9 GORDON 20.9 80.2 82 451 +1991 6 28 12 11 MICHAEL 49.5 99.9 65 21 +1982 1 2 18 18 NADINE 34.4 100.5 147 846 +1996 10 6 18 8 HELENE 25.0 349.6 164 818 +1958 2 11 12 1 HELENE 44.9 100.0 107 367 +1966 3 20 6 6 NADINE 25.7 153.1 158 588 +1962 4 3 12 22 RAFAEL 11.7 61.6 128 393 +1975 4 23 18 13 ISAAC 24.1 94.0 149 800 +1979 4 18 18 17 VALERIE 24.0 312.0 134 585 +1976 7 8 12 18 NADINE 11.9 335.2 17 159 +2004 5 12 12 12 PATTY 49.2 65.8 137 307 +1963 12 19 6 17 SANDY 31.0 355.6 141 642 +1952 8 9 0 1 PATTY 49.6 28.6 110 97 +1994 10 7 6 22 LESLIE 58.4 163.7 133 586 +1994 2 16 18 24 ISAAC 34.1 122.8 114 198 +1998 10 27 18 21 TONY 27.1 141.1 117 506 +1961 10 13 18 24 GORDON 17.1 110.8 45 44 +1954 4 26 6 2 WILLIAM 15.1 246.5 53 756 +1982 6 24 18 21 MICHAEL 69.5 195.3 155 40 +1958 3 11 0 7 RAFAEL 21.2 156.4 19 667 +1973 12 2 0 2 LESLIE 22.5 310.9 86 64 +1986 4 11 6 9 JOYCE 63.9 181.8 64 180 +1977 10 11 0 24 BERYL 55.8 263.0 101 602 +1986 4 7 0 4 TONY 26.5 118.9 16 496 +1979 3 26 0 26 SANDY 69.0 219.2 38 338 +1974 1 10 0 11 TONY 45.5 330.4 46 279 +1962 3 12 6 6 TONY 36.8 15.0 56 619 +1972 1 24 0 23 OSCAR 56.8 328.3 74 782 +1969 2 13 6 15 VALERIE 67.4 316.2 162 678 +1987 8 7 0 23 KIRK 40.2 348.7 59 596 +1973 11 2 12 8 KIRK 65.0 158.5 74 534 +2002 10 3 12 10 NADINE 29.2 30.6 26 644 +1956 1 28 12 23 DEBBY 65.0 119.4 73 104 +2001 11 1 0 23 FLORENCE 41.3 68.2 13 683 +1975 8 24 6 23 RAFAEL 34.8 212.5 92 98 +1997 8 16 0 20 TONY 57.3 212.7 101 242 +1995 2 28 18 15 ALBERTO 38.8 155.8 125 319 +1966 9 15 12 18 FLORENCE 41.5 108.3 111 638 +1957 9 10 6 1 DEBBY 30.2 139.6 22 479 +1997 8 18 12 7 DEBBY 58.9 6.9 133 445 +1954 1 14 6 9 LESLIE 8.4 7.5 60 269 +1999 12 15 12 11 ALBERTO 12.5 150.1 93 776 +1977 12 10 18 16 WILLIAM 11.4 334.4 120 556 +1953 8 22 6 5 CHRIS 55.4 273.4 97 49 +1981 1 17 12 7 ALBERTO 41.0 323.6 49 325 +1967 9 4 0 15 GORDON 45.5 67.0 87 303 +1985 10 4 6 27 OSCAR 67.0 94.4 89 856 +1979 9 26 18 25 MICHAEL 43.3 230.4 41 592 +1963 1 27 12 10 ERNESTO 55.6 173.5 59 761 +1985 5 13 0 20 ALBERTO 15.8 217.0 145 553 +1989 9 14 12 12 GORDON 69.3 231.9 32 162 +1974 10 27 6 3 GORDON 54.2 77.8 103 146 +1952 7 28 6 5 RAFAEL 42.8 323.4 161 83 +1981 2 14 6 19 ERNESTO 27.4 193.4 76 273 +1964 6 19 18 1 ERNESTO 19.6 133.6 113 397 +1954 8 27 0 7 ISAAC 48.3 21.0 79 847 +1960 3 1 12 25 PATTY 52.8 181.5 76 199 +1965 7 12 12 12 CHRIS 35.5 323.6 120 589 +1993 1 28 18 14 FLORENCE 36.5 230.9 162 316 +1962 12 22 0 14 LESLIE 69.8 83.7 120 130 +1958 4 24 6 6 HELENE 60.6 230.7 151 302 +2004 10 15 18 21 KIRK 10.6 28.6 26 81 +1981 1 12 6 15 VALERIE 64.3 125.5 136 764 +1965 8 12 18 17 DEBBY 7.8 21.3 47 499 +1959 4 10 6 1 OSCAR 62.3 221.1 112 597 +1983 3 3 6 14 PATTY 32.8 105.7 119 379 +1964 4 4 0 8 GORDON 16.7 243.3 105 201 +1972 1 4 12 20 BERYL 69.4 230.3 106 593 +2001 4 14 0 24 CHRIS 58.4 343.1 112 506 +1960 2 19 12 15 BERYL 24.3 134.3 32 211 +1992 5 5 0 19 BERYL 58.9 247.5 107 492 +1954 9 5 6 24 OSCAR 9.8 16.8 100 144 +1978 6 3 6 8 KIRK 33.4 204.4 69 312 +1993 10 8 18 25 ERNESTO 47.4 81.7 135 538 +1977 5 27 18 2 ALBERTO 15.0 157.7 64 824 +1970 4 12 12 12 HELENE 8.4 260.1 26 529 +1993 4 17 0 8 SANDY 58.0 324.8 21 514 +2003 8 17 18 22 FLORENCE 67.5 217.2 40 155 +1978 6 9 18 16 BERYL 32.1 312.4 81 515 +1963 4 16 6 10 ALBERTO 55.2 302.7 22 564 +1978 7 10 18 23 SANDY 8.4 174.7 98 601 +1959 8 26 0 24 NADINE 42.9 157.6 93 542 +1957 5 14 0 8 NADINE 18.8 120.1 65 820 +1967 5 6 6 15 BERYL 45.4 350.9 42 447 +1996 6 4 0 1 KIRK 59.0 44.5 75 416 +1990 8 12 12 22 FLORENCE 19.1 149.4 104 843 +1964 10 18 0 10 BERYL 29.3 59.0 96 485 +1989 7 9 0 15 ISAAC 61.2 226.7 93 580 +1960 1 9 6 9 CHRIS 29.7 93.1 135 845 +1951 6 18 18 25 CHRIS 39.6 259.7 148 682 +1969 2 25 12 22 VALERIE 64.8 355.3 70 453 +1963 9 7 0 19 GORDON 68.1 10.6 118 848 +1977 1 22 18 5 KIRK 61.0 183.5 152 764 +2004 9 7 0 3 MICHAEL 49.6 357.7 69 139 +1983 2 17 18 1 DEBBY 40.1 21.9 23 132 +1992 4 1 12 14 WILLIAM 48.2 176.7 22 8 +1985 3 25 12 27 ALBERTO 35.5 271.9 152 765 +1957 5 22 6 17 KIRK 55.6 121.2 15 304 +1957 12 5 6 25 MICHAEL 37.3 71.4 135 717 +1953 3 20 18 1 KIRK 32.4 255.5 160 188 +1956 8 20 0 25 OSCAR 39.1 53.3 65 571 +2001 3 6 18 4 VALERIE 11.5 123.1 53 355 +2003 5 21 18 3 RAFAEL 37.4 14.8 151 103 +1996 4 15 6 4 SANDY 51.9 102.0 76 832 +1970 1 10 12 9 LESLIE 37.6 274.1 71 216 +1965 10 4 18 16 KIRK 39.2 83.9 146 100 +1956 1 24 0 19 NADINE 51.7 300.4 86 694 +1986 5 19 12 6 VALERIE 62.7 334.5 124 825 +1954 12 16 0 16 VALERIE 45.5 176.2 143 452 +1995 9 26 0 8 ISAAC 17.9 146.1 33 257 +1957 12 28 18 5 DEBBY 50.8 343.0 19 855 +1974 4 15 0 11 TONY 41.4 235.0 52 61 +1960 1 1 6 26 OSCAR 24.9 270.1 144 352 +1979 8 12 12 28 ERNESTO 7.3 89.7 100 867 +1988 6 9 12 15 TONY 57.9 286.0 15 2 +1974 7 21 0 9 LESLIE 23.6 205.8 36 464 +1991 3 22 12 22 HELENE 12.8 247.3 129 705 +1965 4 5 0 16 ERNESTO 43.6 37.5 111 223 +1951 5 7 12 17 ISAAC 59.2 245.1 145 142 +1987 11 21 12 13 PATTY 23.4 67.1 154 6 +1992 6 3 0 4 RAFAEL 67.0 126.4 118 566 +1997 7 13 18 19 BERYL 16.9 284.3 148 178 +1974 9 26 6 25 LESLIE 58.3 127.0 164 44 +1968 2 2 12 12 BERYL 66.5 96.1 115 748 +1990 2 19 12 19 BERYL 16.5 236.8 65 398 +1975 1 25 12 19 ALBERTO 38.6 238.4 157 277 +1964 5 15 12 21 ALBERTO 16.7 272.7 74 721 +1987 9 10 0 6 ISAAC 50.5 174.3 33 236 +1972 5 19 18 1 ALBERTO 42.5 268.0 18 438 +1988 6 4 12 26 DEBBY 37.9 210.6 110 616 +1982 4 28 6 27 SANDY 55.6 157.8 15 289 +1971 3 15 12 22 TONY 19.7 247.0 63 187 +1998 12 16 0 8 KIRK 64.1 137.6 54 93 +1963 1 1 6 13 PATTY 44.4 307.9 126 602 +1965 5 4 12 4 SANDY 49.8 213.2 66 637 +1972 3 8 18 15 TONY 62.3 310.6 141 226 +1980 2 4 0 11 ERNESTO 11.5 237.0 26 526 +2001 12 1 6 4 SANDY 24.0 74.7 59 482 +1985 4 1 12 17 HELENE 13.1 7.8 133 115 +1963 7 27 12 25 LESLIE 23.9 128.8 103 142 +2002 9 22 18 14 DEBBY 20.6 17.6 144 807 +1990 4 19 12 4 JOYCE 36.6 165.0 51 37 +1995 6 22 6 26 VALERIE 28.3 48.1 72 112 +1991 9 26 0 15 HELENE 59.1 197.1 66 855 +1956 1 14 6 8 GORDON 17.6 251.2 141 300 +2002 8 21 0 21 LESLIE 27.7 298.8 61 102 +1953 5 7 0 7 NADINE 49.0 277.6 80 304 +1953 10 4 12 5 MICHAEL 28.6 78.1 149 283 +2000 10 17 12 27 JOYCE 38.6 274.3 45 120 +1965 4 19 6 25 NADINE 58.9 350.9 151 474 +1988 5 9 12 4 NADINE 12.7 107.4 137 469 +1999 6 18 12 17 SANDY 8.1 334.1 23 273 +1954 9 21 6 26 ERNESTO 59.2 352.5 47 453 +1999 10 23 0 20 OSCAR 9.2 112.0 158 132 +1990 6 18 0 23 JOYCE 8.9 248.3 110 541 +1986 4 4 12 28 CHRIS 50.8 202.8 156 392 +1963 12 20 18 11 ERNESTO 18.7 20.1 54 461 +1950 1 19 0 11 VALERIE 23.4 204.9 71 299 +2001 8 25 0 9 DEBBY 18.9 290.9 29 270 +1967 8 21 18 13 BERYL 28.2 4.8 22 20 +1990 6 23 6 7 ISAAC 7.5 267.0 124 670 +1973 6 15 6 2 CHRIS 50.3 18.4 65 362 +1964 3 3 0 26 ALBERTO 8.1 79.1 85 245 +1987 8 8 18 4 SANDY 56.7 120.2 92 707 +1992 3 6 0 14 FLORENCE 55.6 174.3 15 369 +1960 2 20 12 13 GORDON 18.3 62.6 151 452 +1971 8 10 6 4 DEBBY 61.3 115.6 120 419 +1958 6 19 0 2 SANDY 69.0 33.7 58 28 +1970 2 11 12 17 OSCAR 59.4 120.1 102 295 +1978 1 22 0 26 VALERIE 65.9 331.9 50 174 +1972 7 27 0 15 JOYCE 67.2 204.3 39 130 +1952 2 18 18 6 NADINE 53.6 131.0 14 786 +1959 9 11 6 19 CHRIS 10.6 93.6 60 559 +2000 11 5 0 18 RAFAEL 57.1 194.1 105 825 +1956 6 22 6 6 JOYCE 48.0 134.7 24 428 +1973 11 19 12 25 HELENE 28.7 195.9 130 276 +1984 2 1 6 2 MICHAEL 59.2 7.6 98 334 +1997 3 5 0 25 MICHAEL 11.1 114.8 145 756 +1972 6 12 18 11 SANDY 66.0 147.6 68 556 +2002 7 23 0 7 WILLIAM 12.1 157.2 10 16 +1978 5 6 12 16 NADINE 58.5 248.9 51 80 +1995 10 8 18 10 KIRK 33.7 34.6 56 728 +1979 1 10 12 20 ERNESTO 64.5 176.6 93 57 +1979 10 16 12 23 HELENE 66.1 211.0 52 615 +1974 5 20 0 11 PATTY 55.4 314.6 28 391 +1983 5 17 6 9 FLORENCE 9.1 1.9 142 546 +1953 3 17 0 25 OSCAR 12.0 143.9 140 35 +1954 4 21 0 17 PATTY 47.7 119.3 137 695 +1974 11 16 6 9 OSCAR 32.5 160.9 119 125 +1997 7 16 12 10 HELENE 33.0 239.2 10 685 +1986 5 14 18 17 OSCAR 14.6 248.6 140 540 +1956 8 23 0 11 MICHAEL 28.5 98.6 159 869 +1985 3 15 0 9 SANDY 39.8 224.7 45 440 +1982 10 19 0 15 MICHAEL 61.4 64.6 45 823 +1964 5 3 0 26 OSCAR 61.5 353.5 154 565 +2004 7 22 18 5 ERNESTO 61.9 261.8 117 840 +1996 9 15 18 12 RAFAEL 18.3 156.9 112 519 +1950 9 1 6 1 SANDY 47.6 154.7 11 379 +1987 12 12 12 13 WILLIAM 31.9 338.2 24 207 +1960 2 27 0 19 NADINE 23.3 96.1 95 778 +1999 6 27 12 14 VALERIE 69.2 353.7 82 453 +1982 2 22 6 19 NADINE 43.8 203.6 39 679 +1980 4 10 18 12 HELENE 23.2 162.6 61 661 +1951 12 8 18 1 BERYL 45.0 144.8 64 30 +1974 8 27 18 20 NADINE 21.2 113.7 30 172 +1973 5 4 18 5 ALBERTO 49.4 130.8 10 396 +2001 11 10 12 8 KIRK 56.5 55.9 95 542 +1974 3 15 12 7 PATTY 26.7 315.0 69 186 +1991 6 25 18 2 PATTY 67.5 164.8 122 875 +1977 8 21 12 10 JOYCE 56.3 237.4 93 553 +1951 3 23 6 5 TONY 41.1 100.7 33 157 +2000 10 26 6 14 PATTY 12.3 321.7 119 240 +1956 9 23 6 19 ALBERTO 17.4 175.1 111 117 +1973 7 2 12 2 TONY 25.9 35.2 64 514 +1955 2 24 0 4 PATTY 26.0 217.8 26 273 +1965 9 24 18 21 GORDON 31.4 268.5 151 50 +1988 6 2 12 15 FLORENCE 65.2 191.5 142 766 +1973 10 12 12 6 ISAAC 56.6 299.6 151 833 +1999 7 4 12 1 FLORENCE 66.0 303.3 104 60 +1999 4 17 6 28 GORDON 42.1 244.1 101 803 +1964 9 15 0 16 SANDY 14.2 286.3 33 446 +1990 7 20 18 20 WILLIAM 15.6 166.5 75 105 +1988 12 1 6 22 NADINE 48.8 266.5 71 727 +1953 8 1 6 1 OSCAR 8.2 303.2 82 480 +1970 4 19 18 27 ERNESTO 41.8 75.5 42 618 +1972 1 24 12 15 ALBERTO 60.3 230.5 163 836 +1955 10 2 6 9 DEBBY 63.3 153.5 19 736 +1988 3 23 18 8 RAFAEL 21.1 258.0 46 796 +1963 5 18 12 23 MICHAEL 44.7 158.3 89 393 +1958 9 4 18 25 FLORENCE 19.2 261.6 69 610 +1998 4 20 0 9 BERYL 38.7 349.9 126 769 +1995 11 12 0 22 ERNESTO 12.1 124.3 76 723 +1958 6 6 0 19 VALERIE 53.4 142.3 75 642 +1984 9 5 18 22 SANDY 46.9 70.0 148 227 +1985 12 11 0 13 HELENE 22.1 207.6 67 771 +1996 8 5 6 6 WILLIAM 63.3 51.1 54 230 +1955 11 17 6 18 JOYCE 11.6 315.6 117 709 +1981 7 3 6 11 ALBERTO 37.5 95.1 154 208 +2001 12 3 12 23 CHRIS 48.1 184.7 97 731 +1973 5 11 0 21 DEBBY 66.6 167.5 81 126 +2004 3 9 18 4 NADINE 48.0 126.4 134 825 +2002 9 20 0 10 NADINE 20.1 71.1 15 811 +1952 12 8 18 24 RAFAEL 58.7 167.2 110 362 +1988 7 4 18 17 BERYL 67.6 87.9 13 241 +1971 6 2 0 4 TONY 27.7 193.1 154 485 +1994 8 21 12 1 JOYCE 15.0 85.3 137 849 +1969 12 16 12 23 NADINE 51.3 106.1 146 246 +1979 9 14 6 27 KIRK 26.5 58.9 100 374 +1989 5 11 12 5 ISAAC 64.6 271.7 121 496 +1965 2 5 12 7 FLORENCE 63.0 82.7 30 499 +1980 5 5 12 20 GORDON 14.3 24.4 85 304 +1974 11 28 12 22 RAFAEL 57.1 131.1 25 251 +1951 3 22 18 20 ERNESTO 56.5 310.3 78 575 +1986 10 16 12 5 LESLIE 29.7 207.8 34 154 +1988 1 19 18 3 KIRK 7.1 107.7 90 651 +1959 11 15 18 13 KIRK 39.9 160.0 48 869 +1979 1 11 6 26 DEBBY 31.1 211.7 57 711 +1950 11 25 12 11 CHRIS 14.1 288.2 107 843 +2000 4 27 6 14 CHRIS 49.7 193.5 140 97 +1950 12 1 12 6 OSCAR 12.7 31.5 151 755 +1987 9 18 6 9 WILLIAM 45.2 309.5 37 27 +2003 5 6 6 18 ALBERTO 35.5 267.8 73 468 +2001 12 17 0 15 GORDON 20.6 337.6 77 283 +1986 4 4 0 14 KIRK 12.3 115.8 164 842 +1954 8 2 0 3 LESLIE 52.0 130.8 97 432 +1983 1 22 18 6 ERNESTO 67.1 215.1 19 104 +1974 3 21 12 15 ERNESTO 36.8 68.1 67 807 +1994 4 25 0 9 SANDY 16.6 347.3 69 874 +1971 2 23 6 23 OSCAR 37.1 232.3 103 570 +1991 12 18 18 23 ERNESTO 25.0 112.5 36 748 +1997 9 14 0 3 DEBBY 41.4 202.8 17 664 +1953 7 1 12 1 ALBERTO 24.4 270.4 66 752 +1994 4 9 18 6 ERNESTO 19.2 265.7 69 261 +1977 5 6 18 2 BERYL 58.0 13.6 51 637 +1980 8 4 6 26 ALBERTO 48.2 51.0 115 698 +1968 4 11 6 8 JOYCE 62.4 167.4 82 856 +1951 12 1 18 28 JOYCE 39.1 265.4 117 862 +1957 10 12 6 8 MICHAEL 57.7 307.1 81 809 +1960 5 14 6 17 NADINE 32.5 120.2 10 755 +1962 4 26 0 24 OSCAR 35.8 262.3 83 165 +1977 10 3 12 8 TONY 68.0 131.3 30 521 +1992 12 1 6 25 BERYL 7.1 236.3 117 385 +1997 12 6 0 18 ALBERTO 19.8 231.3 162 58 +1963 12 16 6 24 LESLIE 41.4 239.2 14 852 +2001 4 21 0 5 HELENE 39.7 256.6 83 589 +2004 5 4 0 21 FLORENCE 29.8 92.7 129 782 +1951 10 16 12 1 JOYCE 10.2 230.1 60 77 +1985 10 8 12 20 ALBERTO 27.6 70.1 22 386 +1951 1 3 6 15 ISAAC 10.8 258.0 121 454 +1961 1 10 0 27 TONY 38.4 179.5 134 885 +1991 8 2 6 20 JOYCE 26.6 200.2 22 884 +1950 12 6 18 2 VALERIE 54.8 192.3 59 470 +1971 12 16 0 5 SANDY 56.2 26.0 25 337 +1963 4 8 0 22 KIRK 29.8 202.8 141 279 +1956 5 26 6 15 KIRK 19.3 160.7 102 879 +1956 12 11 0 23 OSCAR 57.5 92.6 33 243 +1983 1 3 12 15 PATTY 51.3 183.3 136 451 +1997 12 18 0 15 NADINE 58.8 22.9 24 729 +1992 4 22 18 21 KIRK 17.8 311.8 94 879 +1984 10 19 18 9 FLORENCE 51.6 34.9 28 888 +1983 7 18 6 1 HELENE 68.5 149.1 156 609 +1980 5 3 12 22 FLORENCE 11.6 145.2 19 472 +1979 3 7 0 19 HELENE 53.0 46.7 28 688 +1985 6 15 6 10 GORDON 42.6 213.7 141 536 +1980 2 17 12 10 CHRIS 29.1 98.8 134 549 +2002 6 11 12 20 WILLIAM 32.8 165.7 62 496 +1958 7 26 18 28 OSCAR 36.8 298.4 163 407 +1966 4 15 12 13 OSCAR 44.2 149.4 29 846 +1967 5 26 12 6 ALBERTO 49.8 326.2 75 863 +1967 9 27 18 25 SANDY 20.9 24.4 62 319 +1988 11 27 12 5 JOYCE 69.6 184.0 144 389 +1964 9 20 0 21 ERNESTO 47.3 131.1 144 131 +1953 11 24 18 20 JOYCE 56.5 346.8 64 76 +1984 6 12 18 25 RAFAEL 36.0 140.5 96 662 +1956 12 5 18 26 KIRK 53.7 19.3 146 758 +1996 7 21 0 27 BERYL 60.1 312.3 141 830 +1980 3 27 18 19 VALERIE 16.2 175.8 29 882 +1983 12 1 6 26 ERNESTO 32.0 63.6 86 341 +2002 10 8 6 2 OSCAR 31.1 93.1 162 734 +1970 11 1 6 1 LESLIE 64.8 252.1 109 390 +1986 11 4 18 2 GORDON 10.5 306.8 123 199 +2004 6 18 0 24 DEBBY 62.5 137.8 34 21 +1990 4 20 0 7 DEBBY 69.2 158.3 138 381 +1983 11 6 6 15 GORDON 56.4 108.0 81 40 +1980 7 23 6 1 OSCAR 57.2 27.0 35 879 +1995 11 23 18 16 HELENE 9.8 193.3 99 535 +1991 12 11 12 26 HELENE 40.8 298.1 78 524 +1974 11 25 0 24 KIRK 16.2 178.6 109 882 +1956 8 21 12 14 KIRK 9.1 30.1 43 352 +1982 4 15 12 17 MICHAEL 48.7 345.3 91 279 +1953 12 3 12 17 NADINE 9.7 257.8 159 644 +1975 3 16 12 23 ALBERTO 10.3 311.9 64 140 +1964 7 20 6 11 JOYCE 54.5 250.1 48 162 +1960 6 5 12 22 VALERIE 37.9 336.2 52 284 +1965 10 6 6 10 TONY 20.5 275.6 162 61 +1956 8 20 6 2 TONY 13.4 225.1 161 350 +1988 9 28 12 3 RAFAEL 32.3 277.1 144 804 +1950 6 16 0 3 NADINE 66.4 0.0 103 591 +1985 12 4 12 24 ERNESTO 17.6 350.1 71 404 +1950 8 28 12 12 OSCAR 69.9 351.4 90 371 +1968 4 10 12 13 ERNESTO 27.0 103.3 145 526 +1980 10 26 6 11 MICHAEL 20.7 345.9 156 321 +1962 11 26 12 1 HELENE 30.1 127.3 26 102 +1988 2 25 6 4 RAFAEL 17.4 192.4 45 612 +1968 5 18 0 13 ERNESTO 7.8 19.1 126 575 +1965 9 25 12 28 JOYCE 26.5 189.5 91 260 +1956 7 3 18 28 SANDY 46.6 211.7 72 450 +1987 7 8 18 18 DEBBY 20.1 172.7 134 585 +1969 2 8 6 2 CHRIS 48.7 88.2 118 395 +1989 9 22 18 25 VALERIE 47.8 313.7 97 758 +1974 4 17 0 24 SANDY 65.2 11.2 90 675 +1961 10 26 18 10 NADINE 18.7 159.8 44 588 +1956 11 2 18 15 MICHAEL 45.1 225.4 134 420 +1970 4 15 18 17 KIRK 32.0 147.3 101 212 +2002 10 7 12 22 NADINE 15.3 210.9 80 181 +1960 6 2 12 23 TONY 39.5 173.7 27 509 +1969 11 9 6 3 DEBBY 37.7 353.0 11 274 +2000 11 19 12 23 PATTY 21.7 71.0 59 493 +1956 8 6 6 4 PATTY 39.3 128.0 13 254 +1974 6 5 12 26 KIRK 28.8 118.3 115 300 +1954 4 24 12 13 ERNESTO 19.4 37.0 150 367 +1957 12 18 12 19 JOYCE 27.6 301.1 61 534 +1969 8 20 18 22 FLORENCE 27.4 203.0 76 826 +1989 12 14 18 17 RAFAEL 64.2 180.0 41 647 +1967 7 12 6 8 BERYL 44.7 186.7 71 610 +1963 5 20 0 12 OSCAR 36.6 129.7 85 379 +1957 10 11 18 6 TONY 40.3 224.1 22 454 +1950 11 3 18 19 WILLIAM 49.6 98.5 160 518 +1974 12 26 18 4 HELENE 37.9 8.4 73 135 +1985 3 17 18 16 OSCAR 39.6 197.8 123 131 +1958 3 16 6 23 CHRIS 7.1 317.0 144 231 +1965 1 10 18 2 VALERIE 52.9 10.8 20 615 +1967 8 6 6 24 DEBBY 48.7 216.2 127 607 +1997 2 14 0 15 GORDON 25.8 255.4 159 360 +1950 5 7 12 19 KIRK 35.6 94.9 84 681 +1967 5 4 12 1 RAFAEL 40.9 329.3 160 77 +1952 2 9 6 15 WILLIAM 42.2 228.7 45 232 +1995 10 11 6 10 VALERIE 9.8 249.9 29 643 +1967 4 1 12 3 FLORENCE 67.4 245.5 157 710 +2000 3 16 18 22 WILLIAM 43.2 258.6 64 649 +2001 12 9 18 21 DEBBY 64.0 344.4 116 558 +1971 1 7 0 20 GORDON 58.2 225.3 136 402 +2004 7 23 0 25 ISAAC 27.0 83.6 137 246 +1976 2 6 18 9 NADINE 17.9 113.6 131 191 +1991 1 16 6 11 GORDON 54.5 331.8 58 785 +2003 4 26 6 5 RAFAEL 45.5 50.6 163 130 +1996 4 25 18 28 ALBERTO 59.9 108.7 147 356 +1956 8 19 12 25 SANDY 38.3 169.6 73 727 +2002 10 11 0 3 CHRIS 48.1 267.0 131 189 +1996 5 1 18 3 HELENE 56.9 248.3 47 523 +1991 11 4 12 16 HELENE 66.8 355.5 145 97 +1976 1 9 6 11 GORDON 27.7 256.5 163 305 +1990 2 21 6 8 ERNESTO 40.8 184.5 136 504 +1963 10 6 0 22 CHRIS 14.9 351.8 110 525 +1989 9 9 12 12 SANDY 13.7 146.6 151 163 +1966 12 10 12 27 KIRK 35.7 265.4 25 768 +1971 2 5 12 19 FLORENCE 60.9 242.6 69 29 +1970 4 20 12 27 ERNESTO 7.5 309.5 20 592 +1976 2 16 0 14 NADINE 12.2 24.8 110 562 +1992 3 1 18 11 KIRK 11.8 337.6 89 506 +1952 2 23 0 5 SANDY 49.8 47.4 72 332 +1967 10 18 18 18 TONY 40.3 339.7 112 471 +1998 8 5 12 25 KIRK 13.5 292.4 55 408 +1958 1 3 18 13 VALERIE 33.2 143.5 73 646 +1984 12 2 6 18 JOYCE 41.7 197.5 28 387 +1955 7 7 0 9 WILLIAM 43.3 152.2 69 346 +1978 12 26 18 4 MICHAEL 22.7 353.0 138 840 +1962 3 9 12 24 OSCAR 50.9 228.0 162 716 +1958 8 26 0 7 OSCAR 15.2 215.7 27 231 +1992 5 7 6 12 PATTY 62.4 293.9 89 196 +1973 4 16 18 20 TONY 64.6 248.3 69 552 +1991 10 9 0 1 FLORENCE 12.8 115.0 37 399 +1989 6 26 18 7 DEBBY 40.8 121.7 91 53 +1992 4 20 18 5 FLORENCE 50.8 178.9 52 295 +1989 2 11 12 8 MICHAEL 58.9 253.7 18 233 +1974 12 15 12 3 ISAAC 27.2 41.8 56 565 +1990 11 3 12 3 ISAAC 41.4 333.3 36 748 +1957 8 1 0 11 WILLIAM 28.7 276.0 75 461 +2003 10 1 18 4 ALBERTO 28.3 268.9 23 160 +1994 12 13 0 28 HELENE 12.4 254.3 153 600 +1967 7 16 18 3 ISAAC 14.0 254.9 37 373 +1987 4 2 12 27 OSCAR 61.3 68.9 52 393 +1969 2 11 0 26 BERYL 66.7 279.6 93 583 +2001 3 28 18 28 JOYCE 13.0 176.7 26 786 +1983 5 24 18 16 OSCAR 8.9 325.5 95 451 +1995 4 26 18 4 FLORENCE 52.7 233.0 79 195 +1989 6 28 0 12 VALERIE 63.4 325.6 88 805 +1980 2 27 0 9 KIRK 37.4 107.7 146 175 +1971 9 5 18 27 BERYL 17.1 252.4 41 393 +1995 1 7 0 15 RAFAEL 59.8 279.8 163 215 +2003 5 26 18 17 TONY 39.5 303.8 157 817 +1993 9 8 6 14 ERNESTO 51.1 146.8 40 588 +1983 10 22 6 17 DEBBY 68.6 90.7 47 686 +1989 11 26 18 26 BERYL 23.4 190.9 51 860 +1953 12 9 18 21 SANDY 44.5 73.8 116 557 +1953 5 11 12 11 DEBBY 45.7 264.8 124 805 +1957 6 22 18 18 WILLIAM 57.4 324.9 69 70 +1978 3 25 0 17 FLORENCE 36.6 203.8 142 359 +1980 8 6 12 2 HELENE 15.1 237.9 44 485 +1964 1 17 6 20 ISAAC 52.2 37.3 37 745 +1950 12 10 6 4 JOYCE 53.5 235.9 25 192 +1974 7 3 18 8 NADINE 21.9 197.3 79 510 +1999 4 5 18 12 DEBBY 7.2 332.1 157 209 +1959 11 14 0 28 DEBBY 15.1 252.5 48 137 +1958 7 20 12 11 BERYL 7.5 349.6 162 42 +1981 5 3 6 23 CHRIS 23.4 108.2 82 557 +1967 4 9 12 11 CHRIS 59.1 230.8 79 682 +1952 8 8 6 21 ALBERTO 62.9 297.9 151 573 +1963 1 9 0 5 GORDON 67.5 315.1 122 137 +1959 2 11 6 8 BERYL 36.4 295.6 46 273 +1960 7 26 6 1 WILLIAM 37.4 333.9 109 407 +1976 4 16 6 22 GORDON 55.1 352.9 47 637 +1971 7 4 0 18 KIRK 22.0 81.8 161 503 +1980 3 6 6 14 GORDON 67.6 337.5 17 636 +1981 1 7 12 18 DEBBY 14.7 12.7 87 125 +1969 11 28 18 6 ISAAC 54.1 79.2 33 254 +1980 5 10 18 12 GORDON 25.0 132.9 93 56 +1982 5 17 18 16 TONY 66.8 37.8 163 772 +1965 10 8 0 27 TONY 56.6 79.8 79 34 +2004 9 14 0 7 MICHAEL 13.6 346.5 100 57 +1963 3 13 6 19 TONY 31.9 92.6 56 266 +1967 4 13 12 19 CHRIS 33.0 240.8 102 120 +2001 6 3 6 19 ALBERTO 56.4 320.6 103 724 +1994 11 22 18 19 ERNESTO 21.3 117.1 154 767 +2004 8 5 6 9 OSCAR 51.9 196.3 29 525 +1952 5 14 12 28 JOYCE 11.3 341.4 139 0 +1951 11 14 12 5 DEBBY 33.4 254.3 91 557 +1950 8 9 6 9 GORDON 36.0 53.3 49 73 +1988 2 24 0 18 RAFAEL 51.4 205.0 27 555 +1998 12 8 18 10 KIRK 59.1 280.2 56 828 +1975 1 5 0 5 OSCAR 44.4 141.3 36 158 +1954 9 5 12 19 BERYL 7.2 236.9 89 737 +1987 10 6 6 19 TONY 63.5 129.7 156 563 +1998 2 3 12 14 DEBBY 67.8 23.1 65 259 +1981 10 1 12 27 ALBERTO 57.7 306.6 63 232 +1979 10 17 18 19 OSCAR 23.4 154.9 136 644 +1977 10 6 18 19 JOYCE 30.5 321.0 15 53 +1965 3 13 12 5 HELENE 66.0 145.1 30 679 +1973 11 4 12 28 MICHAEL 42.9 244.3 23 344 +2004 8 25 0 4 BERYL 32.1 33.2 91 625 +1985 5 2 12 12 CHRIS 43.2 72.8 71 815 +1978 1 5 18 21 NADINE 53.4 336.0 29 563 +1984 1 19 18 14 DEBBY 22.1 156.0 82 160 +1975 4 9 18 5 DEBBY 27.0 134.8 106 591 +2004 2 6 12 13 NADINE 15.2 177.5 149 93 +1977 2 25 6 16 NADINE 32.6 243.9 47 125 +1983 4 8 12 6 SANDY 23.0 304.0 144 6 +1957 12 22 6 8 GORDON 35.9 94.5 162 159 +1961 4 26 6 22 CHRIS 31.1 301.8 55 110 +1981 2 22 6 5 RAFAEL 14.8 217.5 53 474 +1989 3 23 18 13 HELENE 38.3 293.1 133 181 +1970 9 15 12 3 FLORENCE 8.6 268.4 149 640 +1969 10 7 0 11 ALBERTO 48.0 123.3 12 732 +1955 7 25 0 10 OSCAR 39.3 246.5 28 80 +1958 9 6 12 14 ERNESTO 32.9 68.3 106 178 +1983 6 28 6 15 CHRIS 45.2 55.6 98 182 +2001 2 9 12 14 ALBERTO 13.3 214.5 21 750 +2000 1 17 12 14 TONY 46.0 340.1 148 786 +1982 3 22 6 13 SANDY 42.1 225.3 129 682 +1997 1 3 6 16 ALBERTO 54.9 352.1 14 137 +1986 1 17 18 22 PATTY 23.1 335.7 47 279 +1976 11 4 0 4 ISAAC 30.3 215.9 134 24 +1950 10 10 6 14 VALERIE 20.7 309.2 65 86 +1995 1 12 18 7 FLORENCE 51.7 96.7 81 287 +1950 4 24 18 24 FLORENCE 11.6 287.0 104 234 +1958 8 19 6 15 KIRK 38.7 337.1 24 127 +1977 12 13 0 17 TONY 29.7 181.9 113 859 +1977 9 16 0 13 RAFAEL 42.4 199.2 153 750 +1985 3 13 0 21 BERYL 13.9 101.9 121 258 +1988 8 1 18 18 VALERIE 52.8 180.9 74 131 +1955 11 5 6 8 KIRK 37.8 254.1 72 365 +2000 2 6 18 6 HELENE 34.8 307.2 127 67 +1964 4 8 12 25 LESLIE 31.8 291.7 163 809 +1998 7 16 0 6 TONY 57.3 234.7 143 371 +1957 12 9 12 21 DEBBY 39.3 114.5 91 240 +1963 4 7 0 9 TONY 62.1 345.3 74 769 +1992 9 9 0 20 JOYCE 49.4 7.6 32 521 +1957 3 2 6 19 NADINE 23.4 334.5 76 514 +1978 8 15 6 25 ERNESTO 10.3 2.6 137 245 +1963 2 25 6 14 ERNESTO 7.5 210.5 10 179 +1951 5 13 12 17 ISAAC 62.5 294.7 78 2 +1963 10 16 12 28 ALBERTO 29.7 142.5 133 219 +1966 3 18 12 3 VALERIE 57.2 146.8 107 797 +1997 5 28 12 28 CHRIS 51.9 191.7 101 646 +1978 1 2 12 24 BERYL 27.0 165.6 100 266 +1995 9 5 18 18 GORDON 19.0 210.9 122 399 +1968 12 15 0 28 GORDON 31.3 111.5 39 691 +1958 4 13 18 7 OSCAR 60.0 219.1 148 892 +1997 4 23 12 23 SANDY 45.2 5.3 114 452 +1990 10 20 18 17 RAFAEL 27.6 225.1 119 743 +1995 2 20 0 20 VALERIE 20.3 114.4 127 829 +1957 1 13 6 21 SANDY 32.9 297.6 107 586 +1974 1 15 18 27 TONY 29.9 74.7 155 587 +1982 1 20 18 27 BERYL 66.7 320.2 87 666 +1997 9 10 12 6 FLORENCE 59.9 348.4 121 151 +1969 9 23 6 6 RAFAEL 42.8 12.3 19 812 +1975 10 12 18 22 NADINE 21.8 237.1 27 268 +1985 9 12 18 3 NADINE 52.2 297.5 82 362 +1987 1 17 6 5 ALBERTO 38.5 312.8 59 324 +1990 3 11 12 14 PATTY 40.1 126.6 38 348 +1963 3 17 18 28 ERNESTO 16.3 121.6 133 465 +1965 2 7 12 10 ERNESTO 12.0 148.7 75 83 +1975 9 17 0 18 ERNESTO 37.4 112.3 63 150 +1982 1 1 12 15 ISAAC 7.2 23.3 141 626 +1973 2 12 18 2 HELENE 15.3 8.3 20 407 +1975 5 16 6 5 OSCAR 44.8 219.6 51 43 +1966 7 14 0 17 MICHAEL 36.0 276.4 26 751 +1970 11 24 6 2 NADINE 9.4 34.3 121 163 +1986 8 9 18 12 GORDON 11.0 134.5 128 370 +1972 3 8 12 25 VALERIE 43.6 4.6 103 539 +1972 3 23 6 3 ISAAC 28.9 188.5 30 465 +1968 10 9 18 1 HELENE 51.4 101.7 161 85 +1998 5 13 18 25 LESLIE 41.3 127.7 69 697 +1975 10 10 12 23 VALERIE 32.6 234.1 27 529 +1963 10 18 18 19 WILLIAM 39.3 72.8 108 808 +2001 1 1 12 26 NADINE 58.8 112.2 25 157 +1958 11 13 0 6 ERNESTO 50.7 134.8 99 51 +1960 1 27 18 6 ALBERTO 40.4 283.2 58 306 +1960 10 24 18 14 ISAAC 20.5 303.9 19 501 +2002 8 22 0 23 DEBBY 10.3 152.2 24 313 +2002 9 22 0 12 PATTY 50.3 173.5 94 829 +1975 4 7 18 4 PATTY 9.8 260.1 146 410 +1957 4 5 12 14 GORDON 42.5 88.2 161 220 +2004 1 9 12 19 MICHAEL 9.9 234.2 133 13 +1992 5 26 12 2 VALERIE 54.1 69.0 12 154 +1956 9 23 12 26 PATTY 8.7 137.7 131 29 +1987 7 12 18 5 KIRK 37.6 182.7 31 89 +1982 7 17 18 24 HELENE 57.8 24.4 97 475 +1998 1 28 12 15 ALBERTO 28.5 73.5 126 643 +1970 4 11 12 9 HELENE 55.3 89.8 91 4 +1980 8 9 0 27 GORDON 13.1 181.5 91 830 +1958 1 14 18 16 KIRK 37.6 187.4 109 543 +1992 1 7 0 5 FLORENCE 31.8 17.2 157 382 +1976 6 8 18 28 BERYL 25.7 61.6 143 402 +1988 5 17 12 14 GORDON 63.1 260.2 115 536 +1969 10 20 0 11 ALBERTO 56.4 91.3 82 22 +1959 4 22 0 19 JOYCE 11.0 320.3 70 709 +1995 10 26 18 6 GORDON 39.5 226.1 36 154 +1961 4 10 18 6 ALBERTO 45.9 194.4 45 585 +1968 6 27 12 13 FLORENCE 58.4 269.7 61 776 +1987 3 6 18 25 KIRK 37.7 72.2 147 411 +1971 6 14 0 13 WILLIAM 53.7 245.3 24 446 +1966 1 18 6 2 CHRIS 13.2 106.8 12 434 +1973 11 8 0 2 GORDON 47.5 287.1 143 551 +1975 6 19 12 26 KIRK 57.7 147.3 144 873 +1987 10 23 0 25 VALERIE 49.5 169.8 133 334 +1957 10 23 18 11 OSCAR 25.1 235.5 29 333 +1972 7 13 18 5 MICHAEL 59.8 346.8 135 798 +1963 9 5 12 19 FLORENCE 8.8 36.4 45 852 +1994 1 8 0 18 MICHAEL 57.3 289.9 68 331 +1984 6 18 6 1 ISAAC 31.9 129.6 55 545 +1958 8 16 18 7 OSCAR 17.8 111.2 130 463 +1968 8 17 18 6 ALBERTO 16.5 91.8 146 59 +1997 5 1 12 16 BERYL 57.6 188.7 123 64 +1957 9 4 6 28 JOYCE 62.0 3.9 71 266 +1983 11 26 6 14 RAFAEL 40.4 32.8 114 885 +1962 2 11 12 1 VALERIE 47.3 100.7 75 57 +1972 7 26 0 4 VALERIE 24.6 221.3 124 484 +1994 5 25 18 25 MICHAEL 8.7 298.3 33 352 +1967 1 6 18 3 LESLIE 29.6 123.5 163 33 +1966 8 24 12 27 DEBBY 14.5 4.6 163 327 +1950 5 8 6 16 WILLIAM 53.7 111.4 106 175 +1985 9 21 18 7 SANDY 30.3 138.9 29 311 +2001 6 24 0 1 OSCAR 8.9 5.3 49 446 +1994 10 12 6 21 CHRIS 60.6 94.2 90 592 +1968 11 18 18 7 ISAAC 12.8 194.1 83 782 +1987 5 17 12 15 ALBERTO 33.4 257.4 136 870 +1978 4 13 6 5 NADINE 28.7 95.7 38 811 +1977 5 4 6 14 LESLIE 10.5 235.6 89 794 +1984 9 9 12 9 ISAAC 49.8 294.7 156 787 +1981 2 3 0 13 DEBBY 9.3 98.6 135 309 +1984 6 6 6 6 SANDY 59.8 172.3 78 424 +1996 9 16 0 17 SANDY 26.6 248.0 94 463 +1964 11 20 6 9 ERNESTO 28.9 323.4 17 58 +1994 3 1 6 2 DEBBY 37.4 18.2 103 373 +1993 8 21 12 13 VALERIE 29.0 266.7 17 807 +1995 7 6 12 7 NADINE 24.9 270.5 28 675 +1983 6 7 12 14 HELENE 48.7 1.0 91 125 +1969 6 24 12 11 BERYL 60.3 342.3 50 834 +1965 2 18 0 11 PATTY 30.5 221.2 85 399 +2000 10 12 18 25 RAFAEL 56.8 289.7 154 277 +1965 8 17 12 26 FLORENCE 46.3 93.6 92 69 +1988 3 18 18 8 TONY 27.6 154.9 19 425 +1969 9 6 0 8 OSCAR 37.8 146.9 16 107 +1995 4 15 12 14 WILLIAM 20.5 265.3 149 474 +1964 6 8 6 4 ISAAC 56.2 98.0 115 24 +1997 10 22 0 24 BERYL 18.5 209.7 75 376 +1957 10 8 6 11 RAFAEL 67.6 257.4 14 110 +1959 4 10 18 20 BERYL 52.8 180.2 104 117 +1992 2 4 0 20 ALBERTO 15.2 179.6 125 824 +2002 7 12 6 2 OSCAR 30.3 320.5 139 731 +1977 8 21 18 13 CHRIS 14.3 26.2 112 839 +2000 10 1 12 22 BERYL 39.6 260.6 157 751 +1978 12 25 12 8 SANDY 48.0 127.7 53 91 +1964 2 9 0 14 LESLIE 37.3 213.5 135 682 +1958 10 22 6 12 FLORENCE 37.2 324.4 42 104 +2004 5 14 0 6 LESLIE 50.1 88.1 159 691 +1977 1 10 6 13 HELENE 34.9 122.2 159 817 +1973 9 15 18 22 HELENE 38.9 173.0 19 890 +1956 2 25 0 9 FLORENCE 19.3 170.4 122 286 +1976 7 10 18 4 MICHAEL 67.9 87.2 156 438 +1967 2 21 0 27 OSCAR 14.6 74.3 89 899 +1976 1 24 12 14 ALBERTO 18.7 291.2 112 887 +1986 8 6 0 6 ERNESTO 31.7 7.8 162 299 +1963 1 12 12 8 HELENE 64.3 218.7 86 217 +1973 12 1 12 13 BERYL 63.8 108.1 127 611 +1976 2 9 18 25 NADINE 25.3 184.7 13 678 +1999 5 19 0 22 CHRIS 50.4 286.0 87 880 +1970 7 16 18 18 JOYCE 26.1 69.4 12 631 +1999 5 20 0 14 JOYCE 48.3 112.7 34 7 +1956 9 11 0 27 SANDY 12.1 70.5 51 815 +1964 7 11 0 19 NADINE 12.6 214.9 156 165 +1987 2 24 18 22 OSCAR 36.2 239.6 89 527 +1951 11 12 18 18 NADINE 64.8 181.1 75 135 +1964 3 16 12 7 KIRK 57.8 26.8 77 29 +1995 6 16 6 11 TONY 27.0 317.9 20 368 +1951 3 3 0 16 OSCAR 16.1 3.3 84 725 +1999 9 10 6 4 NADINE 47.3 255.8 39 16 +1950 5 28 18 5 TONY 27.3 95.0 93 892 +1950 1 26 18 20 SANDY 50.7 271.2 14 688 +1956 2 28 18 28 ERNESTO 21.7 54.6 105 588 +1966 4 21 6 2 PATTY 13.1 352.0 137 863 +1953 5 28 12 3 KIRK 55.1 286.8 147 134 +1983 10 26 6 5 MICHAEL 25.6 1.7 155 477 +1992 1 19 12 20 VALERIE 16.2 340.6 35 144 +2003 9 9 0 3 HELENE 44.7 357.0 105 664 +1953 8 14 0 6 TONY 28.4 145.7 162 522 +1965 3 3 18 3 FLORENCE 60.6 119.8 156 685 +1993 4 6 12 4 HELENE 54.3 3.2 154 66 +1976 2 22 12 5 WILLIAM 39.4 152.7 64 402 +1957 5 28 12 9 LESLIE 46.0 147.7 130 251 +1992 1 12 18 20 TONY 47.6 46.3 154 376 +1965 7 2 0 14 WILLIAM 38.4 200.3 144 262 +1962 2 10 6 26 HELENE 29.4 13.7 155 414 +2002 2 2 12 8 BERYL 12.2 294.2 123 201 +1985 12 21 18 14 BERYL 48.8 113.7 108 844 +1980 6 13 6 14 ERNESTO 14.6 45.3 160 140 +1951 5 1 12 13 CHRIS 10.4 224.8 59 550 +1981 10 6 6 21 TONY 26.8 0.1 148 829 +1994 4 21 18 20 KIRK 53.6 233.3 144 271 +2004 1 1 6 9 VALERIE 67.5 241.2 93 30 +2001 5 21 18 15 VALERIE 54.2 87.5 25 578 +1969 8 17 12 28 GORDON 50.9 217.8 27 445 +1987 2 16 18 27 ISAAC 42.2 268.6 31 865 +1992 10 10 0 23 DEBBY 22.1 334.5 41 595 +1980 7 24 6 20 TONY 23.9 197.4 154 735 +1986 2 14 12 11 LESLIE 21.7 109.5 120 550 +2000 8 13 6 20 ALBERTO 28.3 188.8 138 846 +1994 8 24 6 6 SANDY 66.2 120.9 96 354 +1979 2 15 18 7 DEBBY 62.1 300.3 72 657 +1978 6 2 0 22 OSCAR 11.9 265.5 105 226 +1951 8 8 0 10 HELENE 30.8 141.9 44 481 +1989 11 13 18 1 NADINE 7.4 255.1 63 568 +1984 6 6 6 19 NADINE 54.3 77.3 37 628 +1974 3 27 18 17 FLORENCE 60.3 47.1 159 473 +1990 5 16 6 2 NADINE 34.1 3.7 42 33 +1972 10 1 0 1 ALBERTO 20.6 164.6 25 282 +1987 12 20 18 20 WILLIAM 45.1 104.5 99 896 +1967 12 22 6 2 MICHAEL 26.0 202.7 106 52 +1961 9 21 12 20 HELENE 38.0 112.6 139 170 +1990 11 8 0 19 WILLIAM 19.7 12.0 10 307 +1973 2 19 6 14 ISAAC 7.4 59.0 21 17 +2002 12 4 0 3 ALBERTO 8.3 222.7 58 488 +1963 2 2 6 8 LESLIE 40.9 315.3 127 262 +1978 11 8 6 5 BERYL 68.2 334.2 128 343 +1950 12 28 0 22 ERNESTO 41.2 346.9 156 57 +1964 2 13 18 4 ERNESTO 19.9 229.2 157 39 +1954 8 17 18 6 OSCAR 40.4 157.5 61 486 +1986 5 12 0 27 LESLIE 43.2 182.4 94 793 +1950 6 9 6 11 SANDY 9.6 266.3 126 326 +1973 11 14 0 4 GORDON 42.1 339.5 12 559 +1956 11 20 0 13 HELENE 69.6 65.0 102 734 +1958 1 28 0 6 ERNESTO 8.7 207.8 157 765 +1997 5 19 6 27 NADINE 55.1 282.7 52 150 +1954 12 26 12 18 WILLIAM 46.0 135.3 50 319 +1975 4 28 6 19 OSCAR 22.3 14.4 54 402 +1990 6 8 18 1 WILLIAM 38.1 203.1 142 348 +1951 6 14 6 10 TONY 9.1 329.6 133 108 +1959 12 12 0 1 JOYCE 16.8 346.3 47 753 +1997 2 24 6 16 DEBBY 30.6 245.1 122 530 +1950 9 27 18 20 GORDON 40.8 239.4 62 243 +2002 12 25 12 14 RAFAEL 54.9 4.7 46 588 +1952 2 8 18 21 WILLIAM 32.7 127.4 64 794 +2004 9 27 18 23 ERNESTO 62.5 299.2 137 430 +1991 5 6 18 12 ALBERTO 28.0 10.4 158 191 +1990 7 2 0 27 NADINE 60.9 318.3 147 420 +1950 2 20 18 13 NADINE 29.0 199.2 44 684 +2003 5 11 12 7 FLORENCE 57.5 35.6 30 248 +1992 11 19 12 7 WILLIAM 64.2 7.8 157 173 +1956 7 21 0 17 OSCAR 45.2 210.2 73 64 +1955 8 21 18 26 JOYCE 58.6 265.6 74 684 +1974 6 2 18 11 PATTY 29.2 29.7 72 676 +1977 2 13 0 25 NADINE 41.8 125.6 140 138 +1994 12 16 12 10 WILLIAM 18.8 21.4 88 241 +1972 12 3 0 9 TONY 18.8 355.8 71 369 +1997 9 27 18 22 ISAAC 61.4 46.1 68 631 +1963 3 3 6 14 OSCAR 8.0 240.5 144 113 +1997 2 9 6 26 ERNESTO 42.1 100.4 134 53 +1964 4 28 12 16 KIRK 7.4 5.0 31 502 +1964 6 9 12 7 VALERIE 68.5 341.9 15 396 +1996 7 5 12 12 KIRK 32.7 104.6 40 133 +1978 9 4 0 17 HELENE 49.6 84.3 112 284 +1994 8 20 18 27 FLORENCE 61.9 101.7 90 125 +1967 12 21 0 7 WILLIAM 22.9 288.6 119 835 +1956 6 2 6 5 RAFAEL 34.4 78.4 85 306 +1991 9 23 6 13 ALBERTO 15.6 92.9 24 31 +1965 10 13 18 7 BERYL 18.6 295.6 155 75 +1981 8 21 0 24 ISAAC 13.9 330.6 117 508 +1978 7 11 18 1 BERYL 69.4 348.9 115 704 +1976 4 10 0 8 ERNESTO 32.7 253.3 69 113 +2002 3 5 0 12 MICHAEL 47.9 208.9 48 822 +1970 8 5 12 18 MICHAEL 9.5 72.3 136 463 +1972 12 4 0 28 ALBERTO 40.1 114.0 162 349 +1967 8 20 18 26 OSCAR 29.7 213.3 19 140 +1961 12 28 18 24 ALBERTO 21.8 169.2 149 316 +1980 11 16 12 16 BERYL 69.7 299.7 73 514 +1986 2 13 6 23 PATTY 55.6 147.5 21 234 +1969 7 20 18 17 HELENE 48.1 287.9 71 99 +1963 10 4 6 8 OSCAR 24.2 242.3 145 162 +1964 5 20 18 1 MICHAEL 31.0 44.2 127 70 +1997 11 27 6 21 VALERIE 47.5 238.7 18 434 +1972 3 8 12 3 OSCAR 63.6 119.0 113 54 +1958 11 14 12 8 NADINE 69.6 72.6 160 186 +1989 10 28 12 26 SANDY 50.0 196.4 124 847 +1987 4 6 18 4 FLORENCE 24.5 89.1 69 132 +1978 10 6 6 13 WILLIAM 26.3 18.9 70 261 +1993 2 5 12 22 WILLIAM 48.8 129.5 60 181 +2004 9 5 18 4 WILLIAM 53.7 239.7 48 799 +2003 5 12 18 21 HELENE 68.7 6.2 37 839 +1972 9 2 0 8 SANDY 65.3 97.9 102 323 +1971 4 19 18 8 HELENE 63.2 191.3 31 311 +1951 6 25 0 7 JOYCE 49.3 56.3 21 439 +1966 8 25 0 22 RAFAEL 67.2 350.5 118 294 +1966 8 9 12 26 CHRIS 28.5 253.3 149 881 +2000 9 7 12 2 DEBBY 44.9 49.2 18 92 +1979 1 18 0 14 ALBERTO 30.7 67.6 36 634 +1999 6 11 0 12 RAFAEL 16.8 311.3 84 800 +1952 2 10 18 28 NADINE 53.1 73.9 68 613 +1966 8 7 12 14 RAFAEL 28.3 162.6 157 637 +1977 4 11 6 20 FLORENCE 14.1 219.3 108 547 +2002 2 13 6 22 VALERIE 27.7 98.8 105 569 +1954 3 4 0 15 JOYCE 62.6 229.7 91 464 +1953 4 1 12 27 MICHAEL 7.5 8.8 143 641 +1971 1 13 12 10 RAFAEL 18.1 356.7 111 514 +1988 2 24 6 11 WILLIAM 67.0 92.9 124 275 +1999 12 16 0 25 OSCAR 43.3 148.5 52 219 +1989 5 27 6 28 SANDY 66.2 253.6 106 49 +1990 12 26 0 26 SANDY 7.1 53.4 55 396 +1959 1 15 12 3 SANDY 50.6 193.4 87 158 +1952 4 18 18 23 BERYL 7.8 133.2 119 834 +1974 9 13 6 28 CHRIS 45.0 250.2 118 256 +2000 3 20 12 22 ISAAC 55.5 111.6 86 69 +1957 2 7 6 24 ISAAC 32.7 316.6 134 587 +1950 9 19 0 13 PATTY 54.3 155.1 24 818 +1960 10 9 12 20 ALBERTO 51.9 74.0 59 594 +1982 5 16 12 21 BERYL 8.0 271.6 139 59 +1998 12 4 6 20 BERYL 18.1 342.5 92 457 +1977 1 13 18 3 LESLIE 25.5 265.1 140 89 +2001 10 25 12 2 ALBERTO 54.5 147.5 11 556 +2000 4 28 18 8 GORDON 55.5 54.3 88 663 +1989 2 4 12 3 ALBERTO 61.7 173.0 81 605 +1970 7 3 18 28 OSCAR 17.9 342.2 131 247 +1954 1 4 18 10 CHRIS 63.7 46.2 91 826 +1998 4 20 0 20 JOYCE 18.0 191.7 82 260 +1987 9 2 6 8 KIRK 57.9 135.3 134 406 +1979 5 1 18 27 ALBERTO 10.1 212.2 78 663 +1992 9 25 12 20 RAFAEL 36.0 13.5 14 636 +1982 8 28 12 20 RAFAEL 18.5 213.9 119 452 +1950 1 16 6 14 FLORENCE 49.3 112.6 27 221 +1999 11 7 12 14 DEBBY 47.0 299.9 76 726 +1994 5 18 0 2 ISAAC 19.1 284.6 38 653 +1959 6 15 18 6 VALERIE 60.9 140.7 50 501 +1978 12 24 6 1 BERYL 39.3 10.2 109 569 +1993 4 1 6 11 LESLIE 38.1 128.8 61 451 +1957 3 11 18 26 ISAAC 10.1 319.5 73 34 +1990 2 14 18 23 RAFAEL 35.0 342.0 87 449 +1958 1 25 0 6 NADINE 15.1 88.8 10 293 +1958 12 18 12 4 JOYCE 43.3 23.5 17 57 +1957 8 6 0 6 CHRIS 15.7 129.7 19 468 +1995 9 21 18 19 LESLIE 39.4 142.8 111 198 +1995 9 6 18 14 TONY 14.5 161.6 89 652 +1962 12 4 0 9 JOYCE 28.5 97.7 118 889 +1966 1 25 6 23 SANDY 49.5 103.8 55 470 +1951 2 22 18 28 VALERIE 15.9 243.4 107 143 +1982 9 20 6 5 NADINE 19.0 228.6 77 264 +2002 9 3 0 14 CHRIS 41.3 186.3 14 864 +1971 12 25 12 2 LESLIE 19.0 45.7 64 406 +1979 5 18 6 24 ALBERTO 28.0 179.3 51 72 +1986 3 22 12 15 HELENE 36.3 216.5 101 437 +1982 11 18 6 16 ISAAC 51.9 280.3 23 377 +1984 5 12 12 12 SANDY 46.6 0.9 81 842 +1959 3 1 0 10 RAFAEL 12.8 50.9 109 225 +1954 3 20 18 24 ERNESTO 21.2 110.5 52 777 +1988 4 27 12 20 OSCAR 19.5 251.7 45 768 +1960 3 26 18 22 HELENE 9.2 252.8 59 761 +1989 2 24 18 1 MICHAEL 13.1 24.8 119 47 +1993 11 15 18 16 KIRK 58.4 288.8 127 209 +1960 12 8 18 23 SANDY 62.7 155.6 59 430 +1983 3 21 0 21 LESLIE 13.9 49.6 140 130 +1990 7 23 0 8 RAFAEL 46.7 68.6 33 794 +1964 12 6 18 3 PATTY 52.6 285.0 21 857 +1950 6 22 18 8 WILLIAM 45.2 80.0 94 160 +1973 10 1 12 4 GORDON 39.0 326.6 92 305 +1995 7 28 18 9 FLORENCE 18.3 7.0 96 34 +1969 9 2 12 21 HELENE 23.0 4.1 77 801 +1982 1 27 6 7 JOYCE 45.4 223.2 123 665 +1957 4 9 18 9 SANDY 16.4 167.0 103 795 +1954 12 13 18 11 ISAAC 63.1 306.4 150 230 +1997 10 10 18 16 LESLIE 64.1 309.0 67 351 +2001 6 26 12 9 DEBBY 22.4 320.5 10 330 +1983 9 17 12 8 WILLIAM 8.9 216.5 157 244 +1957 9 12 0 26 JOYCE 58.8 155.5 19 348 +2000 9 6 12 15 DEBBY 48.0 293.2 124 169 +1981 11 15 0 25 MICHAEL 69.7 259.2 157 756 +1974 11 26 6 16 SANDY 34.0 220.5 32 807 +1992 4 12 6 21 ALBERTO 31.8 182.9 98 620 +1952 4 15 18 12 JOYCE 46.6 126.9 135 369 +1991 1 3 6 11 NADINE 23.2 82.5 101 92 +1988 6 1 12 10 PATTY 51.9 54.0 57 34 +1989 12 20 12 13 TONY 55.7 87.8 160 48 +1968 2 19 18 22 RAFAEL 51.0 36.5 106 579 +1975 12 9 12 24 HELENE 65.0 282.3 144 536 +1988 11 13 12 16 ERNESTO 50.6 311.8 160 288 +1957 1 20 18 17 TONY 45.5 152.2 126 558 +1961 2 23 18 17 SANDY 56.7 128.2 69 138 +1956 1 13 6 25 WILLIAM 27.2 353.5 155 49 +1967 4 17 18 19 LESLIE 49.0 146.6 27 350 +1977 1 28 12 9 ALBERTO 43.7 188.4 125 166 +1995 11 17 12 8 WILLIAM 39.2 261.2 30 237 +1998 4 16 0 27 OSCAR 19.7 288.1 52 329 +1961 1 28 6 13 KIRK 64.7 90.0 12 364 +1991 8 17 0 25 ISAAC 66.7 38.2 78 496 +1969 10 15 6 12 JOYCE 65.8 64.4 100 690 +1980 5 8 12 25 TONY 56.5 161.0 77 6 +1998 11 9 18 8 NADINE 38.3 184.9 66 536 +1963 11 12 18 1 DEBBY 49.9 149.0 138 796 +1994 7 26 18 6 ALBERTO 34.1 159.5 118 704 +2002 3 4 6 18 ALBERTO 50.4 138.5 122 794 +1964 4 16 0 22 OSCAR 40.0 337.7 16 215 +1972 3 15 6 13 KIRK 69.8 39.7 43 536 +1977 5 3 18 9 SANDY 47.9 73.8 128 140 +1962 6 6 12 4 OSCAR 52.4 300.1 159 324 +1994 7 22 12 20 FLORENCE 16.5 122.0 27 32 +1986 7 17 18 16 GORDON 52.0 297.0 99 61 +1971 8 17 12 3 VALERIE 17.6 106.1 114 283 +1990 3 5 12 16 ISAAC 68.0 262.9 86 853 +1963 2 2 12 10 WILLIAM 33.0 12.5 21 612 +1977 2 23 6 9 ERNESTO 28.3 64.2 128 575 +2000 1 19 12 16 NADINE 51.8 249.9 140 427 +1967 9 16 18 17 ERNESTO 15.4 212.7 80 103 +1975 11 11 0 16 RAFAEL 30.9 49.4 30 144 +1992 11 1 0 20 ALBERTO 36.1 170.0 94 710 +1979 9 16 12 11 BERYL 60.2 237.2 70 638 +1979 7 23 6 6 KIRK 21.0 82.4 99 29 +1956 9 23 6 23 BERYL 43.0 172.5 42 244 +1963 3 23 18 7 ISAAC 23.2 229.1 128 716 +1957 7 25 6 1 HELENE 67.7 2.5 62 899 +1980 6 22 6 20 SANDY 21.6 35.4 160 783 +1994 12 15 12 16 DEBBY 66.7 334.0 17 386 +1968 4 27 18 1 NADINE 7.3 204.1 118 624 +1982 2 16 18 1 KIRK 29.1 214.0 64 455 +1957 1 11 12 8 FLORENCE 38.5 333.5 125 417 +2004 5 17 12 17 BERYL 43.0 313.2 94 789 +1950 6 9 12 15 OSCAR 11.4 171.8 91 438 +1989 6 5 18 20 GORDON 47.8 231.2 113 517 +1969 5 13 6 2 OSCAR 23.3 207.1 129 257 +1950 9 25 0 21 ISAAC 10.0 178.7 122 197 +1961 2 3 6 18 RAFAEL 22.4 229.6 155 898 +2001 5 19 18 15 BERYL 47.0 34.5 94 516 +1986 10 19 6 8 HELENE 10.0 24.5 63 289 +1988 11 7 12 10 MICHAEL 53.4 184.5 31 6 +1979 3 11 18 16 ERNESTO 30.3 23.5 46 374 +1975 8 6 0 9 NADINE 9.5 269.0 87 377 +1969 6 7 18 17 SANDY 41.1 241.8 83 813 +1991 2 20 0 3 ALBERTO 40.8 116.0 32 494 +2000 8 1 6 11 WILLIAM 12.1 305.5 55 565 +1955 10 13 12 10 DEBBY 11.5 223.1 140 109 +1961 9 8 0 5 RAFAEL 65.8 154.6 141 658 +1998 11 8 0 8 RAFAEL 38.0 308.2 32 653 +1999 1 16 12 8 MICHAEL 10.5 4.3 139 770 +1987 5 1 18 8 NADINE 32.2 89.0 90 269 +1968 4 25 18 5 GORDON 40.8 286.9 88 53 +1976 1 19 0 19 KIRK 38.2 12.9 128 296 +1972 2 19 6 2 ERNESTO 26.2 268.4 73 49 +1950 6 5 18 10 ISAAC 7.4 72.7 55 885 +1992 7 27 18 10 BERYL 61.4 338.6 134 582 +1987 4 11 18 22 KIRK 56.8 127.5 139 73 +1996 6 9 6 17 MICHAEL 30.3 221.0 27 399 +1950 3 16 0 9 NADINE 33.9 182.0 16 656 +1999 12 19 18 13 SANDY 55.7 193.1 26 613 +1988 12 6 12 21 FLORENCE 67.8 202.9 23 67 +1952 12 15 18 9 LESLIE 25.6 117.9 27 149 +1956 12 2 18 12 GORDON 29.0 21.4 159 106 +1974 5 11 0 17 ERNESTO 65.0 63.0 126 367 +1988 9 28 0 4 ISAAC 32.8 122.0 158 889 +1983 5 10 12 15 OSCAR 32.2 226.0 31 532 +1978 3 18 6 13 HELENE 68.3 64.3 144 293 +1972 5 19 0 8 MICHAEL 62.9 46.9 26 436 +1989 6 21 6 25 DEBBY 67.1 296.7 57 158 +1980 8 10 6 24 NADINE 56.4 58.1 48 415 +1950 4 16 6 2 BERYL 49.7 174.9 106 666 +1998 9 9 18 19 ALBERTO 64.5 342.1 130 162 +1972 7 13 12 7 ISAAC 29.2 355.3 96 894 +1978 4 13 18 14 WILLIAM 65.1 36.9 144 767 +1960 7 22 18 13 DEBBY 61.0 254.4 50 485 +1978 7 27 0 28 GORDON 30.8 7.5 32 592 +1977 7 19 18 8 HELENE 38.1 160.0 139 181 +1992 9 16 12 18 MICHAEL 68.4 302.8 60 82 +1953 7 4 0 5 NADINE 22.2 145.3 119 577 +1983 9 22 0 12 NADINE 50.3 74.6 138 325 +1992 12 6 0 9 JOYCE 17.1 131.2 56 503 +1950 4 23 12 23 BERYL 21.4 54.8 27 375 +1954 1 11 0 22 ALBERTO 45.8 76.9 35 18 +2004 10 1 12 19 NADINE 45.9 7.9 144 767 +1976 8 10 6 16 WILLIAM 32.0 9.7 72 180 +1984 9 20 18 15 MICHAEL 34.5 327.8 19 585 +2004 10 5 0 2 HELENE 69.5 252.9 21 567 +1961 12 8 18 26 MICHAEL 69.5 211.8 30 833 +1969 4 8 6 9 NADINE 43.7 49.5 152 672 +1987 1 3 18 14 OSCAR 61.0 239.1 19 729 +1952 1 20 18 20 PATTY 11.5 40.9 132 796 +1951 1 1 6 3 LESLIE 48.3 141.2 68 567 +1966 8 17 0 13 KIRK 38.3 203.4 34 820 +1977 9 13 6 28 PATTY 39.8 308.0 36 828 +1963 10 27 6 6 DEBBY 9.1 307.7 15 514 +1953 11 15 12 4 CHRIS 26.7 34.4 127 113 +1992 1 16 18 15 SANDY 30.2 267.6 34 100 +1973 8 22 6 8 BERYL 37.7 225.5 104 180 +1986 11 6 12 22 WILLIAM 38.5 243.9 66 769 +1966 1 8 18 23 MICHAEL 15.8 356.0 10 529 +1958 4 7 6 26 ALBERTO 36.0 33.3 93 348 +1992 3 19 6 22 JOYCE 53.3 298.7 63 362 +1973 1 25 12 2 DEBBY 49.1 154.1 156 235 +1967 10 5 12 13 MICHAEL 23.7 144.9 94 515 +1962 2 5 0 8 LESLIE 62.7 306.0 132 731 +2003 10 26 0 3 PATTY 36.8 71.8 157 161 +1952 2 24 12 19 ALBERTO 67.5 203.1 102 899 +1965 2 4 6 17 BERYL 23.4 266.4 82 432 +1987 7 21 12 4 SANDY 17.0 332.6 58 170 +1961 11 5 0 24 TONY 14.4 215.0 71 713 +1997 5 16 6 18 LESLIE 9.0 236.7 140 399 +2004 10 7 0 24 VALERIE 50.1 73.3 84 96 +1965 12 28 18 10 ALBERTO 51.6 204.0 37 136 +1986 11 28 6 20 FLORENCE 51.6 113.5 112 393 +1961 12 26 12 23 MICHAEL 55.2 50.5 21 489 +1965 5 26 12 9 KIRK 59.0 164.3 72 827 +1981 3 8 18 1 DEBBY 57.2 337.1 126 205 +1978 2 14 12 16 KIRK 68.2 118.4 150 134 +1958 5 20 12 14 ERNESTO 12.5 81.5 133 367 +1995 12 13 0 6 HELENE 29.8 135.0 33 287 +1962 6 7 12 27 HELENE 8.4 42.4 116 569 +1992 10 10 18 23 HELENE 38.2 229.2 73 24 +1956 7 1 12 10 WILLIAM 63.1 245.9 102 117 +1952 5 7 0 13 SANDY 47.1 289.0 53 300 +1967 3 9 12 6 BERYL 51.7 99.3 49 48 +1961 11 14 0 11 KIRK 66.2 130.5 149 158 +1968 8 3 12 15 JOYCE 19.5 42.0 131 510 +1989 2 5 18 12 LESLIE 25.8 299.5 88 585 +1988 10 12 0 18 HELENE 61.1 8.7 39 874 +1982 12 4 0 27 NADINE 38.2 266.3 34 366 +1957 3 7 18 24 DEBBY 41.5 29.5 27 152 +1961 9 19 0 2 JOYCE 24.1 231.5 71 151 +1999 5 27 12 20 NADINE 46.2 113.1 33 722 +1984 3 12 18 10 DEBBY 47.1 92.9 124 627 +1999 5 5 6 19 OSCAR 10.8 274.5 64 393 +1950 9 9 18 3 MICHAEL 12.1 98.8 95 365 +1998 2 27 0 24 ALBERTO 39.4 212.7 120 214 +1959 6 1 0 5 LESLIE 31.0 254.3 37 46 +1998 5 17 18 25 MICHAEL 9.8 225.3 17 775 +1981 7 27 6 15 BERYL 67.7 158.6 44 316 +1985 10 13 6 27 VALERIE 30.5 113.9 105 687 +1961 5 11 12 27 VALERIE 45.0 326.3 36 284 +1990 2 9 12 18 PATTY 27.2 34.0 58 263 +1977 9 25 0 21 KIRK 62.7 60.2 130 162 +1954 3 11 6 26 FLORENCE 17.0 136.8 105 885 +1989 2 5 0 16 LESLIE 51.8 170.3 94 272 +1953 10 4 6 8 CHRIS 50.6 186.1 26 720 +1989 5 21 0 23 FLORENCE 19.6 295.4 59 251 +1999 1 5 12 5 MICHAEL 55.9 263.6 84 686 +1990 6 9 6 8 SANDY 49.2 344.1 67 630 +1991 3 4 18 21 ISAAC 68.4 135.6 112 817 +1971 11 27 12 5 NADINE 44.2 354.7 24 677 +1996 2 13 6 19 BERYL 61.2 102.5 106 710 +1967 11 13 0 13 ALBERTO 29.3 149.6 52 407 +1999 4 23 18 2 SANDY 41.5 19.1 61 601 +1979 3 4 18 2 KIRK 40.1 143.0 146 350 +1987 12 15 12 25 HELENE 23.6 244.7 142 529 +1962 5 8 12 9 ISAAC 47.0 221.2 17 286 +1979 12 4 0 6 DEBBY 32.6 70.7 105 844 +1987 1 6 12 25 ALBERTO 22.5 338.0 24 126 +1997 1 24 18 3 WILLIAM 42.1 43.2 105 5 +1951 12 18 12 9 ALBERTO 17.0 68.6 157 44 +1980 9 7 18 1 ERNESTO 8.2 91.8 65 705 +1976 11 15 6 28 OSCAR 52.3 105.7 108 581 +1989 12 4 18 8 BERYL 38.7 0.8 157 80 +1993 7 27 0 28 TONY 34.7 32.8 140 685 +1961 1 24 18 12 OSCAR 15.6 174.3 156 61 +1951 3 20 6 25 ISAAC 30.2 54.6 69 334 +1971 3 8 6 19 LESLIE 45.6 67.3 98 268 +2001 5 28 18 6 KIRK 62.5 282.1 72 408 +1993 5 18 12 21 KIRK 20.8 124.7 37 418 +1977 9 19 6 23 ISAAC 54.4 318.3 75 571 +2003 11 2 18 3 FLORENCE 25.8 105.1 107 599 +1961 12 4 12 3 OSCAR 18.9 168.8 106 258 +1964 2 14 0 19 GORDON 66.3 47.8 156 519 +1971 8 22 18 16 GORDON 61.2 174.3 134 702 +1965 9 6 12 25 OSCAR 13.9 301.7 87 91 +1997 6 5 6 26 FLORENCE 53.5 161.6 16 314 +1985 1 8 12 23 VALERIE 60.5 145.2 101 327 +1966 7 26 0 8 HELENE 40.2 63.8 150 781 +1981 10 7 0 12 SANDY 40.0 125.4 48 833 +1977 2 10 0 12 ALBERTO 8.9 357.5 129 68 +1988 10 12 18 10 VALERIE 14.8 39.9 58 369 +1960 9 20 6 19 HELENE 32.0 259.9 35 648 +2004 9 11 6 2 PATTY 57.6 114.0 63 387 +2000 12 18 18 23 CHRIS 10.8 71.0 138 350 +1992 5 11 18 2 MICHAEL 17.1 264.4 116 899 +1957 9 16 6 3 MICHAEL 8.8 100.3 125 440 +1970 7 13 6 14 MICHAEL 42.7 286.2 73 891 +1968 4 17 12 3 HELENE 67.9 108.0 13 669 +1974 7 18 12 13 CHRIS 68.0 68.8 147 431 +1970 8 28 18 2 GORDON 60.4 38.6 85 640 +1995 1 22 12 2 WILLIAM 65.8 232.2 35 430 +1967 6 13 12 25 NADINE 40.9 235.0 97 481 +1955 8 23 12 8 ALBERTO 64.9 202.1 146 423 +1953 8 17 12 8 LESLIE 39.0 315.4 66 419 +1973 4 1 0 17 LESLIE 69.9 70.6 49 135 +1968 10 22 0 3 BERYL 38.5 335.8 122 143 +1978 1 19 12 10 MICHAEL 15.2 261.8 82 851 +1983 5 16 18 21 RAFAEL 55.9 209.6 155 413 +1961 4 12 0 8 SANDY 28.3 263.8 54 49 +1975 2 20 0 4 ISAAC 8.4 205.0 149 643 +1960 5 27 18 1 BERYL 11.5 114.1 157 847 +1974 1 25 6 26 MICHAEL 39.5 131.4 111 380 +1959 8 3 18 10 BERYL 18.2 48.8 144 840 +1959 5 10 12 20 JOYCE 13.6 284.4 162 852 +1998 2 20 12 20 FLORENCE 55.1 165.6 125 451 +1999 11 17 0 20 MICHAEL 51.1 283.8 19 661 +1992 5 3 18 15 TONY 15.2 275.7 47 438 +1973 1 7 12 22 ISAAC 18.0 304.3 112 632 +1959 10 10 0 24 KIRK 62.1 323.7 156 115 +1951 3 28 0 9 OSCAR 62.2 257.7 120 134 +1958 4 24 18 2 DEBBY 68.8 328.8 119 377 +1991 1 14 18 5 LESLIE 43.9 312.4 163 390 +1957 8 8 0 13 DEBBY 30.9 247.3 63 286 +1961 3 6 6 16 TONY 51.0 223.1 53 577 +1999 5 7 18 23 GORDON 46.6 33.9 46 287 +1950 9 28 18 8 KIRK 66.7 202.1 88 676 +1996 6 26 6 18 NADINE 64.4 222.8 137 400 +1982 11 18 18 16 ERNESTO 57.0 125.3 142 502 +1983 2 21 0 4 OSCAR 25.0 331.9 39 278 +1994 3 5 18 16 MICHAEL 57.1 242.4 120 239 +1987 7 9 18 21 ERNESTO 42.4 305.1 48 416 +1987 10 20 18 28 NADINE 26.0 314.6 45 341 +1977 3 18 18 20 PATTY 30.5 83.4 145 764 +1969 2 13 18 4 JOYCE 24.5 243.3 61 822 +1991 11 27 6 5 NADINE 11.6 32.5 126 599 +1976 6 24 0 13 KIRK 51.9 355.5 90 338 +1972 3 13 6 2 NADINE 22.6 342.1 100 802 +1965 9 7 0 17 VALERIE 49.3 0.5 90 302 +1972 11 14 18 4 SANDY 51.4 219.2 99 234 +1999 8 20 6 14 PATTY 32.3 126.3 134 388 +1995 2 22 6 16 JOYCE 15.3 103.2 114 896 +1976 6 26 0 4 PATTY 35.3 93.7 101 653 +1984 3 3 18 25 BERYL 54.8 207.2 43 512 +1998 4 5 6 12 PATTY 10.1 31.9 86 753 +1970 11 8 12 17 GORDON 45.4 211.0 37 592 +1978 6 12 18 3 ISAAC 30.8 139.7 27 661 +1981 9 17 6 24 BERYL 63.2 238.7 86 238 +1960 9 2 0 7 LESLIE 27.1 309.7 135 571 +1958 3 23 18 23 SANDY 36.1 134.6 80 605 +1961 3 4 12 21 FLORENCE 21.0 261.1 66 401 +1968 5 14 12 8 OSCAR 51.4 297.5 85 321 +1954 2 1 18 23 ALBERTO 26.2 40.7 69 166 +1981 1 19 12 11 ISAAC 52.7 119.6 147 473 +1956 1 15 6 9 ALBERTO 63.1 103.5 39 363 +1988 3 14 6 22 ERNESTO 46.5 315.3 130 384 +1961 4 25 0 9 DEBBY 67.0 249.2 126 603 +1962 3 6 0 13 WILLIAM 15.3 203.7 155 810 +1983 12 8 18 14 VALERIE 68.1 285.8 113 165 +1966 3 21 0 27 DEBBY 36.6 129.5 17 226 +1988 2 6 6 7 RAFAEL 31.8 308.8 94 881 +1966 10 18 12 25 GORDON 24.5 28.5 130 686 +1976 7 16 0 25 CHRIS 32.0 197.2 56 413 +1978 3 5 6 14 LESLIE 12.9 252.7 66 185 +1960 12 4 12 28 JOYCE 52.7 6.8 144 80 +2003 6 9 0 25 VALERIE 34.2 180.4 60 469 +1958 5 16 6 13 FLORENCE 46.1 113.1 149 842 +1972 5 17 12 25 CHRIS 26.7 35.7 57 680 +1968 7 26 12 8 ISAAC 68.5 237.9 23 684 +1996 4 3 6 17 MICHAEL 29.6 227.9 154 679 +1966 12 1 6 27 OSCAR 16.3 276.0 56 799 +1992 6 24 6 25 CHRIS 40.9 225.6 35 195 +1987 9 2 12 16 KIRK 15.4 106.0 40 252 +1992 5 17 18 24 JOYCE 67.9 330.4 151 644 +1987 7 8 0 27 ERNESTO 51.1 320.3 97 591 +1961 1 6 6 23 ALBERTO 42.0 1.0 48 591 +1970 3 25 0 28 NADINE 24.7 186.6 41 246 +1950 8 11 0 21 DEBBY 9.0 53.7 13 879 +1960 2 13 6 16 TONY 15.0 348.0 40 315 +2004 10 20 12 11 DEBBY 59.8 107.4 50 759 +1968 12 7 6 5 BERYL 25.6 204.4 159 507 +1960 4 12 6 9 ISAAC 25.2 199.6 138 663 +1954 3 15 18 6 RAFAEL 46.6 334.6 146 156 +1954 11 18 18 3 SANDY 66.4 29.9 129 759 +1968 10 15 0 1 JOYCE 8.3 268.9 119 447 +1973 10 1 12 7 ALBERTO 48.3 48.9 59 174 +1973 9 15 12 8 FLORENCE 55.5 204.7 129 797 +1969 2 10 12 11 RAFAEL 25.2 55.7 25 604 +1955 11 23 18 2 KIRK 13.2 336.8 82 187 +1968 1 17 0 1 SANDY 9.8 11.1 58 385 +1969 8 3 18 13 TONY 64.5 332.8 88 413 +2000 4 11 6 28 JOYCE 30.9 18.5 139 816 +1979 1 1 6 15 GORDON 59.2 57.1 63 241 +2004 8 25 18 13 FLORENCE 22.6 66.2 47 141 +1973 11 13 0 20 GORDON 27.8 223.7 141 413 +1958 7 26 6 24 BERYL 57.2 236.8 152 124 +1955 8 11 18 3 HELENE 11.5 293.4 51 578 +1973 7 12 0 28 OSCAR 62.1 0.1 138 824 +1985 11 28 0 10 SANDY 7.4 173.3 117 47 +1965 4 22 12 26 RAFAEL 12.2 261.0 30 65 +1951 9 9 18 9 WILLIAM 44.7 25.5 44 464 +1959 3 4 0 22 VALERIE 45.0 255.4 85 214 +1958 12 1 18 20 BERYL 64.7 111.2 28 823 +1977 5 21 0 27 SANDY 32.7 87.2 125 116 +1983 3 9 0 8 HELENE 32.0 63.2 105 850 +1971 5 9 6 10 MICHAEL 27.8 275.3 71 139 +2001 1 14 6 25 MICHAEL 46.1 199.1 71 628 +1958 2 6 0 25 JOYCE 38.3 207.0 48 389 +1984 10 17 12 11 SANDY 19.6 132.0 159 675 +1962 7 15 12 24 KIRK 45.1 297.8 24 695 +1950 8 3 6 3 SANDY 42.0 145.9 19 221 +1989 11 10 0 5 ERNESTO 60.8 26.6 82 279 +1968 8 25 18 24 VALERIE 58.8 239.2 96 381 +1978 12 9 6 7 RAFAEL 31.8 302.6 37 347 +1959 5 18 6 3 BERYL 9.5 275.7 87 816 +1967 9 13 6 21 VALERIE 17.9 356.0 94 179 +1956 4 7 6 7 CHRIS 28.9 352.2 94 189 +1959 7 12 0 28 LESLIE 28.3 144.0 113 113 +1986 9 9 18 8 BERYL 24.1 46.1 148 70 +1982 9 23 12 6 MICHAEL 61.8 212.2 134 278 +1967 2 8 0 23 ISAAC 12.6 223.8 79 108 +1977 3 11 18 8 CHRIS 14.7 102.4 152 335 +1984 1 5 18 15 ALBERTO 58.2 45.5 55 471 +1989 9 25 12 20 WILLIAM 17.8 324.4 28 718 +1951 5 10 6 25 ERNESTO 52.6 288.9 12 572 +1961 2 15 18 22 DEBBY 65.3 19.6 72 352 +1967 4 16 6 14 BERYL 25.5 81.3 142 765 +2002 12 27 0 25 SANDY 56.6 19.2 86 736 +2001 12 15 6 26 TONY 56.0 14.8 125 531 +1978 1 21 18 5 PATTY 20.7 197.5 117 333 +1971 7 23 6 22 ALBERTO 37.9 294.6 17 739 +1997 2 16 6 19 WILLIAM 35.9 44.9 143 516 +1978 4 7 0 27 VALERIE 58.2 117.7 43 776 +2002 7 19 0 15 ERNESTO 69.2 314.5 67 176 +1959 1 25 0 10 WILLIAM 18.5 286.5 87 597 +2003 2 18 18 9 FLORENCE 43.1 208.7 81 23 +1965 8 25 0 12 ISAAC 41.7 313.4 32 384 +1999 1 21 12 17 NADINE 69.6 193.5 72 206 +1988 7 10 12 13 DEBBY 54.1 38.6 158 447 +1950 8 19 6 25 JOYCE 45.2 190.7 159 422 +1979 9 15 0 25 MICHAEL 13.0 249.3 125 223 +1952 3 19 18 25 JOYCE 13.1 254.6 143 776 +1965 1 21 0 27 VALERIE 10.7 240.2 94 286 +1955 12 18 0 11 KIRK 23.2 146.9 41 9 +1970 8 12 18 25 OSCAR 61.3 102.2 115 717 +1973 1 27 18 13 MICHAEL 39.9 82.7 16 512 +2003 6 2 6 24 FLORENCE 29.6 342.9 94 866 +1997 11 9 12 19 CHRIS 65.1 30.9 128 754 +1975 10 28 12 25 RAFAEL 64.3 166.8 53 653 +1981 6 21 0 3 SANDY 54.9 292.5 10 158 +1999 12 26 12 13 FLORENCE 21.5 263.9 50 721 +1996 5 23 6 28 WILLIAM 61.8 38.3 41 4 +1968 8 3 6 18 FLORENCE 61.9 309.1 109 693 +1996 8 6 12 15 MICHAEL 26.0 343.7 72 91 +1999 3 1 6 2 LESLIE 15.2 153.0 141 383 +1979 7 1 0 12 TONY 51.0 49.5 111 166 +1967 7 5 12 26 VALERIE 60.7 144.7 92 515 +1958 1 3 6 13 HELENE 20.5 104.4 128 507 +1989 3 8 0 18 ISAAC 34.7 270.3 76 169 +1992 1 18 0 7 GORDON 26.7 127.8 164 788 +1979 9 20 18 18 FLORENCE 21.7 295.1 134 627 +1974 6 16 12 13 ERNESTO 57.2 305.1 154 13 +1994 6 13 0 4 OSCAR 41.7 356.7 96 622 +1956 8 9 0 21 FLORENCE 37.1 77.4 124 221 +1953 9 4 0 26 HELENE 22.8 56.2 109 73 +1992 11 20 12 18 GORDON 29.5 1.2 155 219 +1965 5 23 6 20 ISAAC 20.1 25.9 158 577 +1997 8 20 6 18 OSCAR 13.2 9.6 92 816 +1986 3 22 12 12 GORDON 17.8 248.9 106 10 +1953 1 12 12 18 CHRIS 53.8 100.7 79 49 +1950 8 10 12 18 TONY 52.2 51.5 58 33 +1966 4 6 0 24 BERYL 28.7 180.6 29 700 +1958 7 25 6 21 GORDON 17.2 222.1 133 470 +1954 5 15 0 16 SANDY 50.0 73.3 23 74 +1985 4 21 18 25 ISAAC 37.4 38.4 31 602 +1975 3 27 6 19 DEBBY 31.3 255.3 120 35 +1962 12 13 0 2 ERNESTO 28.7 196.6 85 604 +2003 6 26 0 14 JOYCE 60.0 128.8 158 384 +1992 6 6 0 27 NADINE 9.1 242.6 60 571 +1974 8 7 0 7 PATTY 28.1 151.3 27 22 +1988 9 17 0 10 BERYL 33.7 308.3 101 662 +2004 5 27 18 28 VALERIE 35.5 299.2 157 619 +1981 12 12 12 6 ERNESTO 37.5 106.1 32 1 +2004 1 4 18 28 RAFAEL 22.2 55.8 114 12 +1987 12 9 18 25 SANDY 49.7 67.1 155 552 +1974 9 20 12 22 CHRIS 65.1 115.7 49 874 +1963 3 23 0 15 ALBERTO 53.8 305.1 26 869 +1975 6 19 18 16 PATTY 22.4 136.8 25 740 +1999 4 22 0 11 OSCAR 28.5 212.9 154 714 +1994 4 4 0 13 PATTY 68.7 220.7 160 587 +1986 1 13 6 23 MICHAEL 60.8 293.5 132 813 +1976 2 8 18 19 BERYL 17.9 87.1 98 390 +1992 4 16 18 1 ISAAC 58.8 239.6 149 738 +1987 5 26 6 19 OSCAR 53.0 12.3 74 648 +1998 8 2 6 13 BERYL 44.4 330.6 125 58 +1954 3 18 6 21 PATTY 7.6 87.9 29 867 +1992 11 10 0 13 ISAAC 33.6 84.2 39 679 +1962 10 28 0 20 JOYCE 61.6 282.9 73 549 +1951 7 24 6 8 ALBERTO 18.8 207.4 148 193 +1994 4 6 18 10 PATTY 48.9 173.2 82 819 +1961 2 9 0 14 KIRK 25.6 327.0 81 545 +1995 11 28 6 25 GORDON 17.6 210.4 90 877 +1998 4 13 6 14 NADINE 39.6 51.2 54 554 +1962 8 16 12 17 LESLIE 34.6 287.7 156 592 +1974 4 26 18 3 OSCAR 27.2 232.3 17 259 +1960 5 21 12 18 VALERIE 47.4 50.6 151 324 +1961 7 17 18 14 GORDON 56.8 44.0 58 166 +1985 2 27 6 3 HELENE 68.9 291.5 119 564 +1972 2 10 12 9 DEBBY 36.1 42.3 99 547 +1986 12 21 6 13 OSCAR 62.2 301.8 154 695 +1960 11 16 18 11 FLORENCE 64.1 18.9 148 170 +1963 7 28 18 6 KIRK 61.7 22.1 116 527 +2003 9 24 18 3 JOYCE 50.6 56.6 148 5 +1989 6 10 0 3 SANDY 11.0 86.2 50 332 +1956 1 7 18 19 OSCAR 43.3 322.4 55 500 +1987 8 20 0 18 PATTY 10.1 114.1 101 220 +1978 12 16 12 10 WILLIAM 67.6 246.0 162 163 +2003 9 5 6 11 ERNESTO 50.4 214.4 139 557 +1973 7 22 0 14 FLORENCE 50.5 41.6 141 727 +1988 9 10 6 18 VALERIE 26.9 350.7 77 270 +1980 12 7 0 21 TONY 54.0 194.4 119 529 +1997 5 7 18 21 VALERIE 27.6 147.3 150 886 +2004 2 19 18 10 ALBERTO 21.3 85.2 104 163 +1991 1 23 12 9 TONY 61.3 59.0 60 105 +1971 3 6 18 23 ISAAC 68.5 220.9 102 6 +1973 10 5 6 17 FLORENCE 7.2 235.1 80 423 +1973 8 13 6 5 DEBBY 18.3 23.4 161 241 +1994 3 19 18 6 LESLIE 56.6 237.6 75 863 +1984 3 14 12 10 RAFAEL 31.1 17.5 63 240 +1992 5 11 12 25 CHRIS 64.6 28.8 36 288 +1993 7 21 0 20 HELENE 34.7 22.8 115 97 +1980 4 28 6 2 WILLIAM 49.0 30.1 116 142 +1980 3 17 12 26 PATTY 59.3 12.2 60 496 +1957 7 4 18 24 ALBERTO 40.7 87.4 79 228 +1992 8 17 18 3 CHRIS 52.7 165.0 46 82 +1988 11 13 0 1 KIRK 13.0 349.7 40 477 +1993 5 3 18 9 FLORENCE 46.8 289.7 114 161 +1975 11 4 6 9 HELENE 23.7 61.6 45 781 +1953 6 26 0 18 MICHAEL 63.9 118.6 20 568 +2000 9 6 12 10 NADINE 25.6 45.3 134 21 +1972 2 19 0 2 ALBERTO 33.5 238.3 43 497 +1958 7 27 18 2 WILLIAM 45.7 349.9 18 152 +1952 12 18 0 28 CHRIS 56.6 141.7 129 804 +1997 5 21 18 28 FLORENCE 34.9 333.0 109 656 +1981 9 2 6 6 FLORENCE 19.3 314.8 145 487 +1977 10 22 6 26 HELENE 43.0 332.8 60 328 +1974 4 3 12 11 VALERIE 64.5 254.3 19 209 +1964 4 14 6 23 ALBERTO 65.0 255.4 64 152 +1972 7 28 18 25 ALBERTO 26.4 13.1 111 519 +1964 1 8 12 13 LESLIE 63.1 304.6 112 310 +1968 12 27 6 19 KIRK 24.8 254.3 58 346 +1979 3 11 0 9 HELENE 50.3 299.8 129 463 +1970 4 13 12 5 TONY 32.7 220.6 20 520 +1985 10 6 6 23 RAFAEL 9.2 229.5 95 427 +1950 1 21 0 15 FLORENCE 62.0 143.1 28 783 +1951 9 14 12 9 SANDY 38.8 243.6 157 741 +1974 12 8 18 2 HELENE 42.5 123.8 161 807 +1981 11 1 6 24 RAFAEL 69.4 76.4 127 440 +2001 8 12 12 19 LESLIE 67.9 155.4 105 468 +2002 12 7 0 27 PATTY 34.4 25.0 101 98 +1974 7 25 6 5 ALBERTO 41.3 334.3 155 662 +2003 11 18 18 10 BERYL 49.1 78.7 147 804 +1997 6 9 6 27 OSCAR 49.7 293.2 61 861 +1974 10 2 0 19 ALBERTO 26.3 2.8 105 232 +1993 2 2 0 24 CHRIS 10.1 286.8 56 414 +1957 10 9 0 17 ERNESTO 15.4 83.3 37 75 +1989 1 22 12 1 NADINE 67.2 159.4 81 448 +1963 5 18 6 14 OSCAR 57.9 300.6 85 244 +1994 4 18 6 19 FLORENCE 31.6 325.9 128 428 +1950 7 24 12 10 WILLIAM 18.8 342.7 128 627 +1967 8 13 12 20 SANDY 31.9 116.3 103 614 +1974 9 9 12 23 KIRK 55.6 11.0 114 735 +1970 8 7 12 3 ALBERTO 51.9 167.5 48 297 +1953 5 1 18 13 LESLIE 32.8 237.9 123 279 +1987 9 3 6 3 RAFAEL 45.8 34.3 111 440 +1979 7 21 12 13 SANDY 58.9 59.4 127 191 +1981 9 20 12 11 GORDON 55.8 145.4 131 39 +2001 11 22 12 25 GORDON 46.6 200.1 62 737 +1963 11 13 0 6 HELENE 41.0 135.6 81 373 +1995 10 2 6 10 GORDON 37.4 303.7 66 697 +1952 6 23 6 13 ISAAC 38.3 79.1 127 17 +1982 7 12 0 14 CHRIS 69.0 234.7 131 666 +1989 5 4 18 23 CHRIS 69.3 11.4 125 720 +1973 7 3 0 13 CHRIS 29.8 223.4 86 496 +1953 5 27 18 24 LESLIE 16.5 259.9 130 63 +1986 1 7 12 24 ALBERTO 56.7 326.7 43 885 +1986 2 28 18 6 RAFAEL 23.2 85.4 71 676 +1996 2 2 0 14 DEBBY 26.4 350.7 88 665 +1990 1 2 6 25 ALBERTO 49.3 342.3 64 51 +2000 5 28 0 23 MICHAEL 13.1 90.6 107 425 +1985 5 14 6 15 CHRIS 53.6 153.6 120 347 +1978 3 25 0 20 ERNESTO 36.5 62.5 12 122 +1956 3 24 12 9 BERYL 53.1 206.9 21 783 +1991 1 7 0 13 JOYCE 17.3 16.4 136 75 +1972 8 21 0 3 JOYCE 19.2 268.6 153 380 +1988 12 8 6 18 MICHAEL 55.5 256.5 151 373 +1958 11 12 0 11 JOYCE 29.4 35.3 66 144 +1974 9 14 12 14 KIRK 32.2 48.9 84 293 +1953 9 24 12 12 KIRK 50.4 210.9 47 106 +1967 4 22 18 8 PATTY 50.7 76.3 91 377 +1966 2 21 0 20 ALBERTO 30.0 4.2 129 603 +1987 4 20 12 15 MICHAEL 20.5 210.6 121 778 +1955 2 8 6 14 ISAAC 47.7 94.6 52 735 +1983 9 25 18 21 MICHAEL 38.6 93.7 113 257 +1999 6 25 18 7 JOYCE 57.4 356.4 150 170 +1965 8 13 0 26 PATTY 43.1 198.6 155 67 +1990 6 10 18 20 OSCAR 31.0 313.8 114 385 +1978 4 18 0 21 LESLIE 30.1 8.9 18 830 +1967 4 27 18 24 CHRIS 25.2 240.6 116 489 +1953 11 26 0 3 OSCAR 57.5 3.9 107 315 +1957 9 7 6 3 ERNESTO 58.9 21.6 132 896 +1992 12 24 0 4 TONY 43.8 235.2 145 205 +1989 4 20 6 11 OSCAR 13.5 165.3 160 111 +1956 7 7 12 12 ALBERTO 54.9 71.7 107 294 +1980 5 15 6 24 JOYCE 42.3 274.8 138 172 +1997 4 20 6 19 CHRIS 27.0 209.7 16 572 +1951 12 19 6 21 RAFAEL 18.0 278.5 84 63 +2002 11 17 18 9 DEBBY 9.5 205.0 112 685 +1987 6 6 12 28 DEBBY 40.2 292.4 34 730 +1992 10 22 6 20 DEBBY 28.3 298.2 29 474 +1959 8 11 18 27 BERYL 42.5 161.6 31 259 +1983 10 9 12 15 FLORENCE 66.9 86.2 33 159 +1950 9 24 0 18 ISAAC 48.3 292.4 130 669 +1970 1 6 18 27 HELENE 22.9 69.9 97 211 +1993 5 20 12 19 JOYCE 59.9 334.3 126 165 +1989 12 23 12 1 ALBERTO 17.7 288.8 34 60 +1996 2 15 6 8 LESLIE 19.8 343.2 156 261 +1968 1 22 18 14 ERNESTO 57.8 15.5 75 725 +1961 12 2 12 5 OSCAR 21.4 75.0 141 409 +1970 2 11 18 18 RAFAEL 57.7 125.9 145 407 +1952 8 5 18 26 VALERIE 35.0 324.1 156 476 +1987 11 1 0 25 DEBBY 41.0 112.1 148 531 +2004 8 16 12 13 LESLIE 15.2 349.7 74 210 +1962 12 4 12 22 GORDON 39.3 103.5 116 369 +1974 7 2 6 3 GORDON 48.7 103.4 47 63 +1982 10 11 0 4 JOYCE 67.4 161.2 23 280 +1973 2 6 18 28 RAFAEL 52.8 254.5 111 350 +1955 9 2 12 10 PATTY 26.6 129.9 27 702 +1992 4 16 12 7 ISAAC 35.3 303.8 142 778 +1995 8 9 12 6 FLORENCE 49.1 200.7 136 885 +1952 4 18 12 27 WILLIAM 41.8 41.0 43 111 +1972 4 11 0 24 JOYCE 25.9 172.9 122 489 +1977 2 25 12 24 LESLIE 44.6 259.9 118 855 +2003 10 10 12 6 JOYCE 63.6 211.7 72 433 +1955 2 19 6 1 ALBERTO 29.4 257.4 139 70 +1984 8 14 6 4 LESLIE 33.8 249.7 89 252 +1951 5 8 12 21 KIRK 70.0 77.5 117 255 +1957 1 14 18 4 GORDON 33.6 28.1 70 559 +1968 3 5 0 5 BERYL 61.4 329.7 138 548 +1979 11 14 6 4 TONY 26.3 28.9 29 171 +1991 6 12 0 13 FLORENCE 40.1 190.2 11 118 +1983 11 24 12 27 JOYCE 45.4 212.5 94 568 +1979 4 12 0 14 HELENE 35.1 157.3 158 99 +1950 3 21 6 15 CHRIS 62.5 54.8 27 739 +1976 11 28 12 3 VALERIE 20.7 244.5 48 98 +1959 3 16 18 14 DEBBY 20.9 257.9 65 373 +1988 10 3 12 5 OSCAR 67.0 16.5 80 430 +1982 10 21 12 16 VALERIE 59.3 331.7 138 658 +1954 6 8 6 6 ERNESTO 67.5 353.2 142 433 +1996 10 16 18 19 DEBBY 7.2 16.4 90 27 +1970 12 27 0 24 VALERIE 64.6 70.8 78 291 +1989 9 10 0 18 ISAAC 15.4 78.0 35 673 +1988 1 22 18 10 FLORENCE 53.2 297.8 74 134 +1985 1 23 12 11 RAFAEL 53.3 322.6 126 665 +1985 7 6 0 3 PATTY 41.3 192.7 45 497 +2000 3 14 12 11 RAFAEL 29.2 264.1 138 320 +1969 12 22 18 11 JOYCE 69.0 231.6 87 710 +1970 10 12 6 6 LESLIE 53.8 234.6 162 385 +1993 8 5 0 27 JOYCE 53.5 264.3 44 490 +1969 9 14 18 22 GORDON 56.7 52.0 109 699 +1978 6 9 18 14 ERNESTO 23.2 226.7 14 193 +1976 1 19 12 15 BERYL 42.6 297.8 10 733 +1953 3 16 6 19 ALBERTO 18.3 324.1 24 657 +1984 7 17 12 11 JOYCE 25.8 304.9 144 731 +1952 3 22 0 5 VALERIE 44.9 74.9 79 806 +1970 6 10 0 15 ERNESTO 58.0 111.4 88 175 +1960 1 20 18 3 PATTY 66.5 264.0 79 370 +1973 2 14 6 27 HELENE 47.2 285.9 126 14 +1982 10 9 12 4 WILLIAM 12.5 116.5 49 532 +1993 8 21 18 7 CHRIS 58.6 49.9 144 108 +1994 12 27 6 25 JOYCE 20.0 122.1 66 518 +1962 9 5 18 2 ERNESTO 15.8 82.2 22 94 +1998 8 22 6 20 PATTY 62.7 90.9 142 305 +2001 5 27 18 1 JOYCE 9.7 181.5 37 342 +1955 4 1 12 12 LESLIE 19.7 13.5 70 176 +2004 5 2 18 25 MICHAEL 15.2 249.1 20 391 +1979 3 25 0 16 CHRIS 37.2 199.3 148 74 +1955 2 22 18 15 BERYL 48.5 51.6 84 317 +1956 5 27 12 15 ISAAC 51.5 56.6 60 220 +2003 1 23 0 25 GORDON 10.8 211.9 58 714 +1988 5 20 6 17 JOYCE 20.6 27.1 64 345 +1988 3 3 18 20 TONY 28.8 75.0 68 176 +1989 5 10 18 5 CHRIS 34.3 126.8 89 878 +1972 1 19 12 18 JOYCE 10.5 66.3 133 537 +1979 12 23 6 1 ISAAC 68.1 81.9 143 707 +1969 10 16 12 19 ERNESTO 34.4 230.8 14 407 +1986 4 28 0 22 GORDON 46.3 135.5 155 174 +1980 5 15 12 23 CHRIS 43.9 292.1 24 254 +1992 3 4 0 14 PATTY 33.0 129.3 68 644 +1999 3 19 12 11 CHRIS 67.4 331.4 38 131 +1994 5 3 6 14 CHRIS 44.2 286.6 146 376 +1990 3 5 6 1 JOYCE 21.8 335.9 107 645 +1957 11 4 6 2 VALERIE 42.7 61.2 41 748 +1974 3 16 6 25 BERYL 60.8 168.8 44 228 +1977 9 25 6 20 HELENE 65.8 103.2 94 770 +1970 10 9 18 17 GORDON 11.2 119.6 130 450 +1997 7 1 0 4 LESLIE 38.1 30.4 94 484 +1976 6 12 6 3 SANDY 21.9 123.7 118 61 +2003 9 17 6 19 WILLIAM 54.4 211.0 122 82 +1963 7 28 0 24 ISAAC 57.8 31.7 41 369 +1958 4 21 0 16 KIRK 38.6 292.0 113 804 +1989 7 24 0 19 ISAAC 33.9 142.8 161 307 +1984 10 22 18 10 ISAAC 29.2 34.1 42 127 +1999 7 14 0 25 ALBERTO 17.1 77.6 143 149 +1992 6 16 6 16 VALERIE 64.0 14.8 97 619 +1971 7 20 12 28 PATTY 45.3 355.3 10 271 +1962 6 26 18 22 SANDY 42.7 176.1 20 395 +1963 8 27 12 21 ERNESTO 54.1 205.8 139 746 +1966 8 16 0 23 SANDY 37.9 199.9 106 414 +1978 3 13 0 11 WILLIAM 32.0 104.1 80 619 +1960 4 19 12 21 RAFAEL 53.8 278.7 74 68 +2000 6 11 0 23 PATTY 62.3 20.0 20 297 +1984 3 21 6 6 LESLIE 30.7 348.7 90 392 +2001 3 7 0 10 JOYCE 48.1 61.5 16 415 +1980 8 14 12 24 JOYCE 59.2 238.5 100 3 +1951 5 20 6 27 VALERIE 14.4 237.8 66 556 +1976 3 25 6 6 ERNESTO 49.8 184.5 11 411 +1978 3 10 0 10 ISAAC 37.7 45.3 20 795 +2004 1 17 0 24 BERYL 37.8 76.0 148 32 +1989 5 6 18 7 WILLIAM 7.7 222.7 112 515 +1983 2 26 12 21 PATTY 61.4 271.2 143 879 +1988 12 3 6 9 KIRK 62.3 328.4 138 49 +2003 9 26 12 13 MICHAEL 10.4 127.3 106 572 +1988 2 10 12 15 DEBBY 39.5 34.4 63 859 +1981 1 7 18 1 ISAAC 40.0 51.0 121 301 +1966 5 11 0 8 JOYCE 18.1 159.5 37 709 +1981 2 3 18 9 GORDON 68.0 291.7 114 461 +1985 10 14 6 12 NADINE 63.5 212.9 86 196 +1958 4 15 6 6 HELENE 36.4 145.6 60 743 +1998 9 5 0 5 FLORENCE 60.9 347.0 111 668 +1987 9 1 18 21 FLORENCE 53.5 71.5 111 708 +1973 8 7 12 10 GORDON 44.7 247.7 95 788 +1983 6 18 18 1 ISAAC 43.4 187.8 50 483 +1957 7 15 12 16 FLORENCE 61.6 262.1 14 735 +1982 8 28 18 21 GORDON 25.7 81.9 120 511 +1968 7 11 12 19 ALBERTO 50.5 39.7 25 470 +1965 3 6 12 24 DEBBY 62.6 112.3 137 526 +1961 11 6 12 3 CHRIS 33.2 45.7 76 215 +1980 3 25 0 24 ERNESTO 49.5 269.6 107 94 +1973 11 2 6 27 ALBERTO 33.2 33.3 22 224 +1978 11 27 6 7 GORDON 50.7 67.9 108 420 +1985 12 19 0 17 FLORENCE 66.6 291.1 76 187 +1972 2 18 0 19 FLORENCE 47.0 317.2 79 217 +1969 4 14 6 8 HELENE 17.2 211.3 154 301 +1955 3 6 0 22 DEBBY 64.6 319.6 163 533 +1967 9 4 0 27 FLORENCE 9.8 207.5 96 504 +1980 10 26 18 6 WILLIAM 43.0 96.1 120 181 +1966 9 14 12 1 OSCAR 58.3 243.0 13 735 +1970 9 3 6 17 HELENE 36.8 335.3 147 449 +1954 2 18 0 11 ERNESTO 46.0 234.9 69 158 +1967 1 9 12 15 ALBERTO 36.3 246.0 90 223 +1951 11 22 6 2 ERNESTO 15.8 190.1 157 793 +1970 5 20 0 9 WILLIAM 37.8 258.0 102 414 +1965 6 26 6 18 SANDY 43.1 290.3 70 701 +1955 12 4 12 4 GORDON 36.6 108.2 32 30 +1963 1 16 6 28 KIRK 39.4 24.7 88 114 +1971 4 10 6 14 KIRK 60.0 78.7 113 477 +1970 7 20 18 9 TONY 13.9 74.5 128 331 +1985 6 17 0 22 OSCAR 56.3 130.9 87 816 +1953 12 2 0 23 RAFAEL 8.2 320.3 85 58 +1980 12 8 12 9 OSCAR 14.1 142.0 57 357 +1952 8 25 18 4 BERYL 58.3 238.6 112 326 +1999 1 5 12 14 VALERIE 38.1 161.0 23 829 +2004 7 26 6 21 VALERIE 21.0 256.8 58 7 +2000 1 6 18 9 ISAAC 36.5 56.0 48 56 +1961 9 27 0 1 DEBBY 35.1 169.3 45 565 +1975 7 11 0 21 VALERIE 46.0 32.1 114 247 +1972 8 9 18 14 LESLIE 58.1 355.1 64 279 +2000 3 22 6 2 OSCAR 64.9 228.0 128 867 +1978 6 4 6 19 TONY 21.3 337.2 28 370 +1991 5 15 18 3 FLORENCE 19.1 144.2 151 599 +1968 7 21 0 12 PATTY 11.9 111.7 88 393 +1971 1 13 6 13 PATTY 63.7 180.7 160 216 +1980 4 23 18 24 WILLIAM 24.3 293.2 58 636 +1987 6 23 18 5 WILLIAM 65.7 257.4 112 458 +1956 3 15 0 9 PATTY 31.0 105.0 130 201 +1983 8 27 12 11 HELENE 55.8 219.7 59 849 +1969 6 3 18 3 NADINE 36.6 243.2 118 3 +1989 5 25 18 11 OSCAR 21.3 55.5 152 615 +1974 8 10 18 20 ISAAC 20.7 133.1 62 597 +1976 2 10 18 17 ALBERTO 14.9 209.4 104 120 +1979 3 16 6 22 ISAAC 45.4 100.1 120 336 +1992 7 14 12 6 BERYL 26.2 260.5 150 562 +1979 7 14 0 22 OSCAR 48.3 235.5 46 246 +1968 7 18 6 20 RAFAEL 67.5 340.3 106 835 +1999 5 22 6 19 OSCAR 37.0 308.1 132 757 +1954 7 7 6 11 VALERIE 21.3 68.7 41 469 +1975 7 16 18 21 PATTY 44.1 306.5 79 570 +1972 6 16 6 11 KIRK 16.9 82.0 43 292 +1970 9 24 12 10 VALERIE 43.4 348.8 42 122 +1951 9 15 6 4 SANDY 10.6 233.5 10 836 +1990 8 3 6 28 KIRK 30.2 138.2 26 828 +1958 5 3 18 3 VALERIE 30.5 210.2 22 315 +1950 2 13 12 8 SANDY 25.7 99.3 18 660 +2001 11 25 6 8 LESLIE 55.3 298.6 106 316 +1965 11 17 0 28 GORDON 38.3 213.3 126 590 +1957 8 22 12 9 KIRK 34.4 293.3 163 302 +1957 3 8 12 27 NADINE 64.8 264.7 111 305 +1961 10 26 0 2 ISAAC 42.9 216.7 17 2 +1960 3 26 18 10 HELENE 16.4 241.5 127 745 +1962 2 8 0 21 HELENE 22.7 323.6 130 104 +1993 5 27 18 20 VALERIE 66.0 62.3 133 245 +2004 10 19 18 28 VALERIE 41.6 307.9 88 439 +1984 11 14 0 9 CHRIS 24.8 74.2 133 810 +1950 6 7 6 12 TONY 53.3 157.7 15 642 +1959 11 27 6 11 ALBERTO 45.4 157.4 107 793 +1978 6 8 18 4 KIRK 55.5 219.8 144 360 +1998 8 28 18 21 OSCAR 19.8 76.6 66 254 +1958 6 3 0 4 DEBBY 64.7 280.0 72 35 +1989 1 20 6 12 CHRIS 25.6 298.7 163 360 +1972 5 24 12 5 ISAAC 26.7 277.9 55 813 +1985 6 2 12 26 DEBBY 49.0 274.3 92 203 +1970 1 11 12 26 CHRIS 67.1 97.0 36 806 +1964 4 27 18 15 BERYL 36.4 216.2 138 460 +1989 6 6 6 12 KIRK 67.1 196.7 11 221 +1958 6 17 12 8 TONY 40.4 83.5 114 556 +1950 6 18 18 24 OSCAR 63.0 272.7 119 57 +1962 11 7 0 2 LESLIE 49.5 12.2 10 758 +1975 10 8 12 5 RAFAEL 56.0 28.2 86 725 +1965 8 22 6 16 JOYCE 57.0 332.7 27 575 +1995 7 22 0 21 TONY 66.3 315.7 117 0 +1970 1 26 0 16 JOYCE 45.3 228.7 104 515 +2000 8 4 0 12 SANDY 62.6 278.8 23 42 +1985 4 19 12 17 MICHAEL 44.9 17.6 48 797 +1960 4 5 0 11 ISAAC 7.5 73.3 19 23 +1969 12 25 6 17 ISAAC 14.1 74.9 114 240 +1990 5 20 0 21 PATTY 52.4 332.0 109 335 +1975 10 20 6 5 DEBBY 65.0 82.7 99 611 +1986 10 11 6 28 JOYCE 58.7 259.8 92 101 +1997 5 14 18 14 HELENE 14.9 265.1 135 644 +1957 2 21 18 15 WILLIAM 22.8 306.9 101 589 +1951 4 24 12 25 ALBERTO 50.3 244.6 164 263 +1970 1 4 12 3 NADINE 33.5 137.0 99 607 +1983 8 4 12 25 WILLIAM 42.7 45.1 10 695 +1968 11 22 18 11 SANDY 68.2 248.9 133 846 +1992 3 5 18 2 LESLIE 57.4 59.1 133 717 +2001 12 7 6 12 FLORENCE 31.8 219.9 24 738 +1960 4 4 6 26 SANDY 11.5 168.7 105 103 +1966 6 5 18 24 ALBERTO 34.1 103.6 148 542 +1954 11 11 0 17 FLORENCE 16.6 289.0 66 550 +1963 2 22 18 1 OSCAR 50.2 75.7 26 797 +1995 2 15 0 9 VALERIE 50.5 165.3 160 207 +1960 4 9 6 5 MICHAEL 24.6 247.3 114 108 +1998 3 3 12 9 VALERIE 29.6 254.8 108 433 +1983 2 7 12 11 MICHAEL 36.0 132.2 40 534 +1996 3 21 0 4 SANDY 63.3 299.2 160 423 +1984 7 10 12 1 WILLIAM 57.5 227.2 127 123 +1988 4 5 12 23 OSCAR 38.2 181.3 131 824 +1969 5 25 0 3 KIRK 27.1 128.6 68 452 +1991 10 12 12 3 ERNESTO 47.9 67.0 100 406 +1951 9 14 6 10 PATTY 53.4 15.0 70 371 +1961 6 24 0 15 HELENE 57.2 116.5 75 824 +1987 3 3 12 9 VALERIE 63.1 189.8 137 348 +1963 8 19 0 6 KIRK 12.4 73.7 123 444 +1992 11 16 18 8 ERNESTO 48.7 133.3 27 887 +1967 12 25 18 10 FLORENCE 48.8 306.0 79 782 +1972 4 20 18 27 SANDY 65.0 61.5 64 98 +1953 10 4 18 12 NADINE 45.7 166.1 43 477 +1986 12 22 12 9 ISAAC 21.8 7.8 143 19 +1991 5 27 0 7 DEBBY 55.0 338.2 21 377 +1964 12 10 0 27 DEBBY 54.4 354.4 45 516 +1956 10 7 6 18 JOYCE 56.4 251.0 113 466 +1977 10 25 12 28 HELENE 58.6 150.5 107 266 +1963 5 26 12 20 RAFAEL 63.9 240.4 151 563 +1966 7 6 0 23 WILLIAM 51.7 266.0 144 49 +1951 4 13 18 13 NADINE 47.7 53.5 119 735 +1992 4 12 18 9 DEBBY 67.8 349.3 25 685 +2002 3 28 6 1 TONY 11.9 34.8 61 567 +1981 6 6 6 25 BERYL 19.6 325.9 81 565 +1950 3 22 12 19 PATTY 35.3 15.0 105 369 +1965 11 1 0 9 KIRK 49.8 176.4 163 800 +1956 4 10 18 15 HELENE 26.9 324.1 71 188 +1957 4 3 0 15 LESLIE 14.6 86.5 95 636 +1953 7 27 12 8 OSCAR 41.3 292.0 93 786 +2004 6 1 12 8 RAFAEL 30.4 109.9 153 749 +1959 2 26 18 12 CHRIS 65.6 237.7 162 70 +1961 6 16 0 6 WILLIAM 64.9 272.0 40 65 +1987 11 22 12 5 OSCAR 13.2 331.0 116 598 +1970 4 16 0 26 FLORENCE 27.8 163.8 152 844 +1956 10 10 0 1 ALBERTO 13.4 13.5 59 595 +1954 2 24 12 19 BERYL 26.3 291.5 84 142 +2001 8 5 6 2 GORDON 43.9 169.6 105 367 +1954 11 7 18 6 BERYL 21.5 163.9 118 223 +1985 9 28 6 20 WILLIAM 36.5 209.4 43 180 +1990 8 12 0 3 ERNESTO 38.5 177.7 52 462 +1964 6 16 12 8 TONY 61.2 313.2 152 514 +1964 8 20 0 12 GORDON 10.7 269.6 26 515 +1996 5 11 0 11 VALERIE 9.7 157.6 109 120 +1971 3 24 0 24 BERYL 15.3 324.8 158 361 +1983 9 23 6 13 CHRIS 58.6 217.0 90 25 +1994 11 21 18 2 MICHAEL 9.4 300.2 23 591 +2003 7 25 0 1 BERYL 59.3 189.8 115 553 +1956 7 13 12 13 TONY 26.9 40.8 159 251 +1985 3 10 6 1 LESLIE 24.2 288.1 31 879 +1961 4 20 12 16 VALERIE 38.3 325.2 41 763 +1999 4 23 6 20 TONY 53.4 9.6 151 679 +1951 8 14 0 17 PATTY 43.7 121.6 32 206 +1955 4 20 18 28 CHRIS 7.1 340.4 60 705 +1993 12 26 6 21 PATTY 57.6 348.2 115 882 +1969 3 1 0 10 DEBBY 66.9 177.4 64 66 +1981 4 17 18 21 RAFAEL 46.5 228.1 84 847 +1982 12 14 18 18 ERNESTO 12.4 287.6 60 548 +2001 11 7 6 1 LESLIE 48.0 341.1 139 229 +1981 1 28 12 22 ERNESTO 45.0 24.5 163 771 +1998 1 15 12 7 RAFAEL 21.1 48.0 60 308 +1954 6 10 6 11 PATTY 38.5 267.3 136 818 +1971 11 10 12 18 FLORENCE 69.5 229.5 85 765 +1981 11 18 12 28 TONY 40.0 182.2 153 278 +1970 7 25 6 9 GORDON 39.0 204.7 31 495 +1986 6 1 18 18 RAFAEL 49.8 267.6 90 308 +1963 2 19 18 1 BERYL 18.4 244.2 157 372 +2001 3 5 0 24 ERNESTO 62.5 36.1 142 50 +1958 3 19 0 28 ALBERTO 12.5 85.5 158 166 +1959 1 4 0 22 TONY 52.5 166.3 32 463 +1972 1 28 6 13 CHRIS 66.3 301.0 20 759 +1981 4 19 18 14 JOYCE 39.5 199.1 36 530 +1991 8 7 6 13 PATTY 54.8 32.2 58 590 +2000 1 22 6 6 BERYL 29.7 329.9 33 848 +1972 8 27 6 12 SANDY 54.1 184.3 109 828 +1950 4 21 12 8 TONY 31.7 280.4 64 508 +1972 4 4 0 19 MICHAEL 46.2 58.8 38 227 +2001 1 4 0 27 DEBBY 7.7 146.1 146 203 +2003 9 1 6 6 OSCAR 64.2 13.5 57 855 +2002 12 7 6 3 MICHAEL 20.1 33.4 108 46 +1973 7 21 6 23 GORDON 41.8 31.4 111 891 +1987 4 22 0 24 BERYL 27.3 55.7 78 829 +2002 2 28 0 5 PATTY 51.6 185.1 159 361 +1978 1 23 6 22 CHRIS 35.1 237.5 56 722 +1987 4 19 6 14 LESLIE 53.8 28.3 99 841 +1974 10 11 6 9 CHRIS 69.0 33.1 61 534 +1988 7 15 6 13 DEBBY 23.5 72.2 121 199 +1983 6 11 12 23 CHRIS 8.7 76.7 102 763 +1958 5 16 0 6 HELENE 52.1 62.9 96 348 +1967 4 8 12 14 VALERIE 24.3 234.7 21 546 +1969 4 12 18 6 PATTY 60.0 32.6 127 97 +1993 4 21 18 18 RAFAEL 66.9 302.1 17 231 +2001 1 3 6 17 VALERIE 22.9 294.4 93 859 +1957 6 20 18 4 BERYL 17.9 275.9 15 480 +1965 1 6 18 8 ERNESTO 60.2 346.9 114 468 +1968 1 14 6 12 ISAAC 62.3 290.9 158 289 +1980 3 20 6 4 FLORENCE 29.8 200.3 92 607 +2001 6 12 18 23 DEBBY 19.6 15.6 105 876 +1999 11 23 18 26 NADINE 55.7 344.5 23 573 +1970 3 2 18 6 CHRIS 65.9 272.9 59 744 +1976 3 18 0 19 ISAAC 20.7 319.9 96 614 +1960 7 18 18 18 TONY 62.2 9.0 23 58 +1953 8 22 6 6 ERNESTO 13.6 170.8 107 280 +1968 1 9 12 19 BERYL 16.6 93.0 46 70 +1986 5 12 6 28 PATTY 54.1 254.6 126 647 +1973 5 13 12 15 OSCAR 9.4 115.0 38 39 +1981 2 24 12 23 LESLIE 11.3 291.6 14 10 +1962 7 9 6 24 JOYCE 12.0 323.5 92 657 +1988 10 9 12 17 ERNESTO 37.2 154.8 15 233 +1981 10 24 18 18 VALERIE 8.6 15.2 21 552 +1992 10 5 6 7 SANDY 39.3 123.2 83 311 +1988 7 5 18 12 WILLIAM 38.0 234.0 117 886 +1997 2 3 0 28 DEBBY 21.4 267.1 31 843 +1951 11 7 12 22 MICHAEL 26.7 275.5 48 697 +1981 7 1 18 23 ALBERTO 49.1 254.1 34 128 +1988 4 26 6 1 GORDON 49.6 334.2 116 80 +1989 3 11 12 28 TONY 28.5 119.1 26 733 +1963 12 4 0 4 NADINE 38.1 142.3 24 392 +1952 9 20 0 27 TONY 8.4 274.5 146 841 +1967 10 4 12 10 GORDON 47.1 189.9 129 158 +1982 2 3 0 15 DEBBY 67.6 209.0 70 457 +1973 6 22 6 25 BERYL 39.1 158.2 41 134 +1999 7 20 0 10 LESLIE 27.3 247.7 19 403 +1965 2 9 12 5 JOYCE 65.2 296.8 138 647 +1986 8 24 0 9 OSCAR 38.0 34.8 82 413 +1958 10 4 12 3 VALERIE 69.3 310.7 136 710 +2000 1 27 6 2 DEBBY 7.3 319.8 111 886 +1976 9 13 6 27 ERNESTO 12.6 186.9 156 782 +1960 9 21 0 7 PATTY 23.6 215.7 41 119 +1993 8 5 0 11 GORDON 23.5 19.5 52 121 +2001 12 17 6 21 HELENE 9.1 172.3 30 104 +1979 6 22 12 10 PATTY 43.5 143.1 107 689 +1952 4 14 18 15 ALBERTO 23.8 86.4 100 853 +1957 8 8 12 24 ALBERTO 39.8 207.0 132 728 +2003 1 22 18 3 ERNESTO 14.3 157.5 131 223 +1981 12 23 18 25 BERYL 13.6 338.8 106 33 +1980 5 7 6 9 FLORENCE 7.0 275.0 20 340 +1995 4 20 12 18 CHRIS 30.2 32.7 40 464 +1977 5 13 0 13 DEBBY 42.4 353.8 132 565 +2003 5 6 12 8 KIRK 58.6 76.1 116 77 +1975 8 26 18 28 TONY 23.3 98.2 156 172 +2003 1 11 18 1 LESLIE 18.0 340.3 40 585 +2001 11 5 12 12 NADINE 59.6 245.9 112 308 +2001 7 22 6 15 SANDY 20.7 113.2 115 255 +1971 12 17 0 26 BERYL 67.6 182.9 40 885 +1995 6 21 0 7 ISAAC 44.7 46.6 49 618 +1963 7 22 6 20 SANDY 28.0 195.1 70 312 +1998 11 24 18 24 WILLIAM 44.8 267.5 11 629 +1972 1 21 12 23 TONY 28.5 284.0 161 454 +1971 2 24 6 27 BERYL 16.6 26.2 67 213 +1962 11 21 6 24 GORDON 53.1 66.8 55 806 +1965 9 18 6 7 VALERIE 16.2 39.8 147 609 +1973 3 9 0 24 BERYL 60.4 300.2 132 7 +1964 1 10 12 11 CHRIS 8.6 61.4 151 896 +1954 10 21 18 17 ERNESTO 44.8 252.9 86 615 +1989 2 13 12 4 VALERIE 57.5 248.8 93 676 +1997 10 26 6 16 PATTY 29.2 42.4 140 564 +1986 7 28 0 19 LESLIE 50.7 355.9 70 694 +1999 5 21 6 16 PATTY 20.8 345.0 44 493 +1993 3 1 12 1 BERYL 57.2 216.6 135 178 +1998 10 23 18 22 RAFAEL 54.4 351.7 82 612 +1960 9 13 6 12 HELENE 32.2 203.7 59 32 +2001 7 9 0 25 VALERIE 28.8 96.9 84 416 +1951 6 9 6 28 VALERIE 16.1 352.1 150 141 +1985 2 27 12 28 BERYL 67.4 96.0 42 853 +1950 10 2 18 26 DEBBY 41.7 48.2 138 421 +1985 10 28 0 28 NADINE 57.1 285.0 128 238 +1953 12 10 18 23 ALBERTO 34.2 241.8 132 766 +1953 1 20 0 25 LESLIE 18.0 263.2 101 46 +1986 1 5 6 2 ERNESTO 7.3 188.1 31 626 +2001 7 21 6 1 FLORENCE 53.0 186.3 71 82 +1960 9 5 6 10 ALBERTO 12.9 39.7 83 308 +1959 1 5 6 26 NADINE 23.2 225.5 103 453 +1983 3 20 0 22 KIRK 67.8 155.1 24 576 +1955 12 24 6 4 FLORENCE 64.2 165.4 153 126 +1985 5 12 6 25 DEBBY 47.6 271.1 60 538 +1961 5 6 18 24 LESLIE 67.5 311.9 107 500 +2004 9 18 0 15 GORDON 32.0 161.6 74 223 +1963 8 5 6 26 TONY 35.7 244.7 159 117 +1950 1 23 0 8 TONY 56.8 199.0 112 527 +1985 7 7 18 5 KIRK 59.0 236.7 127 383 +1971 7 5 12 20 LESLIE 66.1 300.4 79 65 +1968 8 17 18 25 RAFAEL 59.6 208.2 30 458 +1952 2 19 12 25 GORDON 25.1 226.8 115 634 +1967 7 1 6 1 TONY 54.0 344.7 120 746 +2000 12 4 6 13 ERNESTO 31.2 320.2 87 296 +1966 4 21 0 10 HELENE 47.5 342.2 113 434 +1968 8 21 0 7 VALERIE 54.0 254.7 153 781 +1975 6 14 0 20 ALBERTO 68.6 223.7 153 276 +1973 5 9 12 28 OSCAR 56.1 29.8 164 323 +1961 12 22 6 18 VALERIE 10.9 271.3 75 116 +1978 2 22 18 10 ISAAC 22.6 36.1 10 81 +1964 4 15 18 16 MICHAEL 31.6 145.4 73 492 +1987 5 14 0 9 ISAAC 44.8 205.4 50 220 +1985 9 27 12 13 HELENE 43.9 211.6 28 568 +1956 9 14 0 16 VALERIE 9.0 139.8 137 280 +1988 11 1 12 24 LESLIE 48.6 206.8 38 49 +1978 9 16 18 15 PATTY 38.8 261.2 120 440 +1974 10 20 18 27 OSCAR 57.8 134.2 65 619 +1957 8 11 6 17 LESLIE 42.0 62.2 142 134 +1967 3 15 18 28 ERNESTO 10.6 98.7 128 642 +1957 11 13 0 11 OSCAR 9.6 340.3 32 885 +1980 11 9 12 28 TONY 39.5 235.1 61 216 +1969 10 1 12 21 LESLIE 44.0 333.6 19 848 +1953 6 28 12 9 GORDON 61.6 237.5 80 448 +1979 9 11 18 24 PATTY 41.4 141.3 61 102 +1981 1 4 0 18 MICHAEL 49.8 84.5 159 218 +1958 10 1 18 25 LESLIE 31.1 230.2 78 168 +1986 10 14 18 1 DEBBY 60.4 189.5 48 690 +1956 8 14 18 3 NADINE 28.3 351.6 51 456 +1962 7 23 6 5 SANDY 19.7 229.9 150 157 +2004 4 21 6 1 NADINE 11.0 168.4 55 648 +1993 2 1 12 27 DEBBY 19.8 198.4 38 54 +1959 7 10 6 14 LESLIE 44.1 68.2 49 198 +1987 6 24 6 18 TONY 20.5 330.5 110 890 +1969 12 6 0 1 KIRK 38.2 330.8 19 681 +1997 2 19 6 21 TONY 51.4 8.0 38 806 +1973 8 6 18 2 WILLIAM 40.3 228.5 43 26 +1986 3 20 6 22 DEBBY 36.4 228.8 103 530 +2004 5 19 6 4 OSCAR 11.8 12.1 139 255 +1968 11 8 12 18 OSCAR 8.5 46.7 129 542 +1954 10 3 12 2 HELENE 25.4 345.4 146 335 +1970 6 14 0 15 LESLIE 69.0 82.0 41 658 +1956 5 9 6 24 ERNESTO 40.9 91.9 33 279 +1953 8 21 0 11 RAFAEL 41.1 169.0 151 650 +1976 9 5 12 7 VALERIE 12.8 25.1 52 723 +1950 9 4 12 23 VALERIE 51.9 285.6 153 27 +1957 6 1 6 18 TONY 46.8 74.9 66 119 +1968 3 19 18 4 NADINE 65.1 232.5 119 626 +1986 5 1 18 19 CHRIS 41.9 8.9 104 590 +1956 2 6 0 2 VALERIE 66.3 198.4 35 857 +1990 10 15 6 23 TONY 63.0 303.1 39 476 +1950 12 16 18 11 KIRK 65.5 83.5 31 198 +1978 2 28 0 19 ALBERTO 37.3 86.0 90 478 +1988 4 16 12 24 JOYCE 68.5 99.5 151 82 +1958 10 25 18 13 NADINE 23.9 35.7 52 681 +1984 12 14 18 8 TONY 37.3 278.0 73 80 +1960 8 14 6 14 ERNESTO 52.6 319.9 95 119 +1962 9 26 0 6 BERYL 49.5 205.6 109 534 +1979 7 6 6 25 ALBERTO 9.1 246.1 162 567 +1986 6 27 0 1 ISAAC 21.9 115.4 153 511 +1971 8 17 18 2 ISAAC 47.0 255.7 110 15 +1954 8 13 0 15 ISAAC 43.5 214.0 123 221 +1952 11 7 6 16 PATTY 43.2 47.8 135 40 +1977 1 19 18 8 HELENE 35.3 76.4 155 502 +1990 7 13 12 1 MICHAEL 49.5 344.0 96 508 +1976 10 4 6 2 SANDY 63.6 97.9 35 178 +1959 12 9 0 27 FLORENCE 42.2 278.5 93 576 +1958 11 13 12 17 GORDON 9.5 16.9 61 587 +1957 6 22 18 1 SANDY 15.1 301.2 161 4 +1972 3 17 0 6 WILLIAM 24.3 62.9 44 434 +1957 4 22 6 26 ERNESTO 65.7 83.6 101 350 +1976 4 19 6 22 RAFAEL 35.5 259.4 128 134 +1967 11 10 18 24 OSCAR 9.2 55.9 151 859 +1963 8 14 0 17 DEBBY 29.4 52.5 160 79 +1986 11 14 6 8 NADINE 36.2 323.0 10 535 +1977 6 14 0 28 VALERIE 33.3 328.3 36 551 +1990 10 8 6 7 MICHAEL 54.0 318.5 149 173 +1967 9 15 0 26 DEBBY 65.3 184.8 36 10 +1995 1 5 18 21 ALBERTO 27.6 143.3 159 247 +1994 10 23 18 19 BERYL 51.1 118.6 116 643 +1974 8 24 12 9 OSCAR 32.2 191.7 121 596 +1988 2 20 6 3 LESLIE 57.2 343.5 36 419 +1954 12 19 18 26 LESLIE 35.4 326.8 113 608 +1974 1 13 0 14 MICHAEL 49.2 289.5 36 708 +1986 9 16 0 12 FLORENCE 24.8 273.6 140 154 +1980 6 5 18 19 WILLIAM 60.4 196.1 55 26 +1953 12 25 6 7 WILLIAM 57.3 334.7 18 591 +1963 3 9 18 5 KIRK 29.0 59.0 17 515 +1994 6 23 12 2 CHRIS 62.0 294.5 53 71 +1974 7 2 0 12 WILLIAM 39.8 272.6 111 98 +2000 12 23 0 14 ERNESTO 7.3 136.6 164 875 +1987 3 16 0 15 WILLIAM 59.8 96.0 111 346 +1982 3 1 6 10 HELENE 25.6 64.3 114 593 +1984 5 21 0 23 BERYL 35.6 109.9 71 242 +1999 5 25 18 21 OSCAR 27.3 51.1 164 26 +1999 10 8 18 16 RAFAEL 40.9 255.6 63 493 +1981 11 28 6 26 OSCAR 64.9 213.6 145 765 +1977 3 18 18 9 FLORENCE 8.5 86.6 128 696 +1991 3 27 0 27 SANDY 14.5 24.5 139 795 +1995 9 25 12 28 RAFAEL 59.3 131.7 125 60 +1962 4 12 0 5 BERYL 28.8 232.0 160 103 +1971 3 12 6 16 VALERIE 19.2 244.5 83 327 +2001 10 10 12 19 RAFAEL 28.5 156.5 78 291 +1976 4 13 0 27 SANDY 62.1 255.7 77 414 +1997 4 7 12 6 JOYCE 11.6 278.2 96 552 +1963 12 4 0 14 GORDON 57.1 231.6 78 247 +1957 4 25 0 18 JOYCE 61.0 202.7 71 235 +1981 8 16 18 23 NADINE 47.4 16.7 11 277 +1957 5 6 12 4 LESLIE 60.4 99.0 43 843 +1978 11 23 0 16 ALBERTO 42.5 137.2 32 497 +2003 1 2 18 16 KIRK 40.7 184.0 41 653 +1988 6 26 6 20 DEBBY 21.0 203.2 145 403 +2002 9 9 6 16 DEBBY 22.4 23.9 44 124 +1974 6 18 12 3 NADINE 56.0 335.3 138 452 +1953 12 14 6 14 HELENE 12.8 176.0 103 418 +1982 9 21 6 8 RAFAEL 59.8 270.2 142 408 +1996 7 3 0 28 ERNESTO 21.7 130.8 69 62 +1992 6 23 18 22 KIRK 43.0 49.3 37 207 +1999 6 12 0 9 FLORENCE 61.7 261.2 52 776 +1976 1 21 6 23 MICHAEL 46.2 231.2 23 37 +1983 8 12 0 22 MICHAEL 40.9 266.6 107 128 +1995 10 17 12 13 RAFAEL 50.8 171.4 160 189 +1997 11 21 0 1 LESLIE 41.6 195.8 118 342 +1984 6 19 18 21 NADINE 13.0 197.1 40 827 +1959 7 26 12 18 DEBBY 39.8 160.4 67 246 +1970 1 24 18 14 OSCAR 24.5 168.4 93 434 +1981 3 4 6 3 TONY 40.8 184.6 130 207 +2000 12 3 0 4 JOYCE 63.3 191.2 59 806 +1984 12 15 6 4 DEBBY 63.6 50.5 95 898 +1952 11 16 0 1 BERYL 68.9 156.9 109 297 +1981 5 20 0 23 RAFAEL 55.7 97.9 31 806 +1981 10 4 12 28 RAFAEL 11.6 93.3 82 559 +1995 10 6 0 27 LESLIE 31.2 2.3 137 232 +2004 4 14 18 13 WILLIAM 25.8 296.5 94 296 +1957 3 6 6 14 CHRIS 43.5 214.7 17 666 +1965 6 24 12 2 HELENE 44.2 262.6 142 476 +1978 4 24 0 16 DEBBY 12.9 109.4 30 64 +1986 11 21 6 5 TONY 20.4 110.2 34 494 +1959 10 1 18 19 HELENE 20.9 320.3 134 244 +1984 8 6 18 18 FLORENCE 36.0 321.9 141 829 +1996 11 2 0 6 TONY 50.3 301.3 99 779 +1953 9 10 0 5 VALERIE 43.7 219.9 162 580 +1966 1 15 6 9 CHRIS 27.0 177.5 56 789 +1964 10 11 12 28 BERYL 34.7 161.2 77 423 +1991 4 20 12 13 FLORENCE 25.1 281.8 129 387 +1981 1 8 0 10 ISAAC 39.5 346.3 97 771 +1982 6 27 6 17 FLORENCE 24.1 141.0 114 380 +1997 12 13 12 12 DEBBY 57.3 24.4 81 87 +1962 7 26 18 22 WILLIAM 9.0 17.4 123 713 +1958 5 5 18 13 NADINE 51.5 50.8 82 607 +1997 8 24 6 21 JOYCE 17.8 350.0 19 743 +1958 7 4 18 9 KIRK 65.3 332.2 102 472 +1984 11 12 18 8 MICHAEL 21.2 14.5 67 608 +1965 12 13 0 13 TONY 44.2 126.4 162 358 +1997 12 2 12 13 BERYL 56.0 297.0 160 301 +2002 11 20 12 21 BERYL 19.7 4.1 159 49 +1960 4 28 6 3 SANDY 61.6 276.1 111 61 +1969 7 5 0 20 PATTY 14.5 289.6 139 798 +1990 11 6 12 6 LESLIE 65.9 296.4 163 310 +1995 10 24 6 28 VALERIE 8.1 307.3 58 400 +1995 7 7 18 23 DEBBY 34.8 129.4 99 60 +1994 11 5 18 14 PATTY 41.4 193.0 76 242 +1984 6 20 6 8 HELENE 33.8 331.8 118 576 +1998 7 17 0 10 ERNESTO 39.3 8.2 22 843 +1986 5 26 18 2 RAFAEL 59.5 283.8 64 589 +1986 9 11 6 24 ISAAC 13.1 262.8 22 415 +1999 3 4 18 8 OSCAR 36.5 216.4 143 344 +1985 12 22 12 9 LESLIE 64.6 276.6 70 419 +1950 12 17 18 26 PATTY 53.9 231.2 59 218 +1990 6 26 12 2 ALBERTO 25.5 227.5 59 407 +1950 5 8 18 3 CHRIS 55.5 341.8 164 284 +1999 7 28 18 8 VALERIE 45.2 194.4 116 151 +1991 4 11 6 19 PATTY 61.8 225.0 92 226 +2000 1 7 18 12 MICHAEL 52.7 31.7 47 547 +1980 9 11 12 4 DEBBY 33.3 260.7 42 288 +1968 4 15 12 8 JOYCE 7.1 17.0 95 832 +1981 11 8 18 2 ISAAC 54.1 232.8 151 45 +1985 2 7 6 25 ERNESTO 12.6 273.9 161 328 +1969 6 16 0 4 WILLIAM 49.1 210.1 130 157 +2002 12 24 0 28 HELENE 9.9 273.2 36 716 +1956 10 16 12 6 HELENE 10.6 355.2 111 468 +1962 7 27 12 7 PATTY 43.3 31.2 120 735 +2001 2 6 6 21 DEBBY 12.3 190.7 69 235 +1974 6 5 6 27 DEBBY 38.2 237.9 46 113 +1991 8 10 18 27 JOYCE 67.4 20.7 32 815 +1982 7 9 12 23 CHRIS 47.8 79.7 110 388 +1952 1 22 12 16 KIRK 46.9 324.9 98 102 +1957 5 7 6 24 SANDY 21.4 43.9 116 247 +1956 9 22 12 18 WILLIAM 63.7 244.1 142 232 +1987 12 4 0 13 PATTY 51.7 327.0 98 336 +1972 2 17 12 3 ALBERTO 47.0 255.6 102 696 +1963 9 18 0 1 MICHAEL 64.0 265.3 118 427 +1997 3 12 6 4 NADINE 48.4 293.9 156 348 +1959 4 24 0 15 KIRK 50.1 56.3 32 370 +1952 3 11 0 14 TONY 47.3 274.6 151 384 +1966 12 5 0 14 ERNESTO 8.3 65.3 33 80 +1957 8 23 18 13 PATTY 37.1 212.3 139 535 +1995 11 17 12 10 CHRIS 68.7 191.3 25 167 +1980 2 18 6 22 FLORENCE 20.2 291.6 117 347 +1954 5 2 6 8 PATTY 20.5 206.7 132 252 +1983 10 25 0 20 RAFAEL 42.1 307.4 162 616 +1997 11 20 18 10 JOYCE 64.1 352.8 130 589 +2004 4 27 18 28 VALERIE 42.9 80.4 46 845 +1963 6 5 0 14 CHRIS 48.3 127.5 138 260 +1976 1 2 0 6 HELENE 48.7 249.9 89 394 +1968 8 25 0 8 BERYL 37.9 279.7 95 325 +1962 1 4 12 17 SANDY 48.5 141.7 68 306 +1999 5 16 18 21 HELENE 34.3 99.6 118 450 +1971 12 15 0 10 RAFAEL 64.3 63.8 109 291 +1975 5 11 6 13 WILLIAM 68.0 152.9 152 52 +1973 2 15 12 20 SANDY 38.3 110.5 73 659 +1954 5 20 6 25 DEBBY 47.5 33.0 84 338 +1966 3 8 18 2 TONY 64.5 165.2 140 646 +1982 4 11 0 4 KIRK 12.7 216.2 50 42 +1962 3 24 12 26 ALBERTO 30.8 274.3 156 269 +1959 8 10 12 26 VALERIE 17.2 61.4 132 698 +1971 7 12 12 2 KIRK 25.7 201.8 57 860 +2003 6 25 12 26 LESLIE 53.3 309.8 41 505 +1980 3 25 12 22 GORDON 53.7 309.8 132 431 +1953 12 22 0 20 CHRIS 8.3 261.4 96 540 +1981 11 1 0 7 LESLIE 52.1 296.0 137 58 +1980 10 12 12 17 FLORENCE 44.5 233.3 60 249 +2001 2 7 12 7 VALERIE 69.6 100.5 69 215 +1980 10 18 18 12 ISAAC 22.4 142.1 53 51 +1990 3 25 18 17 VALERIE 28.4 172.4 38 577 +1953 10 1 6 2 KIRK 16.1 264.7 82 225 +1958 4 1 6 16 PATTY 54.8 304.6 81 753 +1995 10 22 0 9 NADINE 56.9 147.9 121 894 +1960 12 6 0 5 LESLIE 68.4 292.7 44 257 +2002 10 11 0 19 VALERIE 24.9 217.1 58 59 +1998 5 5 12 19 SANDY 35.5 346.7 86 282 +1999 2 3 12 23 SANDY 8.5 254.6 54 638 +1984 4 19 18 18 RAFAEL 34.5 308.8 97 612 +1967 6 1 0 24 CHRIS 11.6 17.5 121 827 +1965 2 6 0 8 NADINE 29.1 24.7 136 559 +1953 2 7 0 6 LESLIE 40.7 130.9 55 83 +1968 4 8 6 21 ISAAC 58.9 250.9 47 413 +1997 12 1 0 5 FLORENCE 30.8 158.1 20 333 +1982 9 22 6 1 VALERIE 38.9 100.5 130 436 +1965 4 9 18 27 NADINE 66.5 326.5 148 484 +1951 5 12 6 19 PATTY 68.6 83.4 130 719 +1955 7 1 0 7 DEBBY 14.3 104.4 25 840 +1961 12 5 6 22 BERYL 62.8 183.3 99 612 +1998 2 24 18 17 NADINE 28.1 43.0 162 600 +1954 7 24 0 27 PATTY 25.6 273.9 158 146 +1975 3 1 0 20 VALERIE 57.0 299.2 12 140 +1994 1 22 12 12 VALERIE 18.8 28.1 106 631 +1951 12 11 12 25 HELENE 59.6 177.9 86 132 +1967 8 20 12 15 DEBBY 45.3 63.1 137 573 +1971 9 23 12 15 GORDON 45.6 23.3 139 656 +1983 10 24 0 11 CHRIS 59.6 159.9 108 847 +1982 7 7 6 14 VALERIE 15.7 11.8 95 873 +1996 8 1 6 16 VALERIE 14.1 246.0 139 553 +1970 11 19 18 6 VALERIE 39.7 209.8 146 521 +1950 10 1 12 15 HELENE 16.9 134.2 150 617 +1969 7 25 6 11 LESLIE 26.4 285.6 21 862 +1975 2 17 6 19 VALERIE 12.5 192.5 70 331 +1978 5 24 18 21 SANDY 11.6 2.1 159 892 +1998 6 9 0 6 TONY 29.6 60.8 72 294 +1974 7 25 12 25 HELENE 17.0 331.0 17 428 +1993 10 4 12 22 PATTY 27.2 80.8 76 101 +1997 12 25 6 22 JOYCE 60.6 266.7 141 239 +1953 7 5 0 23 JOYCE 8.4 287.0 117 555 +1999 7 17 12 21 NADINE 36.3 151.1 133 641 +1998 7 17 18 27 JOYCE 40.2 189.8 33 737 +1987 8 24 6 11 ISAAC 45.5 75.3 101 725 +1953 11 27 6 15 ISAAC 50.4 285.7 64 817 +1983 12 1 12 27 GORDON 21.2 189.9 22 212 +1985 1 17 12 10 SANDY 44.4 105.1 57 419 +1953 2 14 0 20 WILLIAM 52.4 254.8 19 356 +1996 12 11 12 22 TONY 27.8 207.6 29 382 +1955 4 13 12 1 OSCAR 34.7 29.8 46 53 +1979 1 24 0 3 SANDY 28.5 69.5 145 849 +1972 4 4 6 18 TONY 10.5 251.9 52 252 +1954 12 23 6 7 BERYL 38.3 345.3 142 879 +1951 6 7 6 21 JOYCE 12.5 300.7 145 388 +1956 1 24 6 1 JOYCE 20.7 201.7 130 801 +1975 7 2 0 21 RAFAEL 34.1 159.1 106 720 +1975 9 1 0 3 DEBBY 27.2 178.1 88 642 +2001 2 23 18 9 OSCAR 55.0 115.6 145 785 +2000 5 11 0 8 BERYL 46.9 79.5 98 751 +1983 3 24 6 2 BERYL 50.1 301.5 143 533 +1974 11 2 6 9 ERNESTO 49.1 190.8 121 541 +1971 2 3 18 14 MICHAEL 19.0 258.0 89 211 +1958 5 14 12 11 FLORENCE 40.6 54.5 63 700 +1956 10 6 6 18 OSCAR 34.1 355.7 160 313 +1964 1 6 18 11 PATTY 26.9 314.6 45 436 +1952 1 7 12 6 BERYL 25.3 136.8 124 836 +1998 2 8 12 19 WILLIAM 55.2 233.8 141 599 +1965 3 15 0 3 TONY 25.1 320.8 97 657 +1987 6 27 18 6 ERNESTO 17.7 79.9 72 879 +1953 5 24 6 17 KIRK 64.7 41.4 131 88 +1956 9 17 12 16 HELENE 49.6 276.4 108 833 +1965 8 21 18 23 PATTY 68.7 28.6 109 815 +1996 4 6 12 27 ISAAC 62.5 134.2 93 344 +1955 12 21 12 10 JOYCE 58.8 150.1 47 590 +1964 1 8 0 11 ERNESTO 42.7 245.4 97 251 +1965 1 8 6 8 PATTY 32.2 275.5 77 174 +1958 11 6 12 15 GORDON 54.9 154.6 70 182 +1973 3 3 18 20 KIRK 20.9 282.7 132 124 +1994 12 22 6 2 WILLIAM 61.8 119.1 89 777 +1980 3 6 6 27 ISAAC 68.0 256.0 121 146 +1980 2 15 12 24 LESLIE 40.5 148.1 74 27 +2000 9 28 0 11 OSCAR 8.3 315.9 150 514 +2003 8 27 12 10 TONY 29.9 89.4 160 286 +1974 3 10 0 7 NADINE 26.9 328.9 117 760 +1998 5 16 18 15 NADINE 46.1 85.5 61 388 +1957 12 7 6 26 TONY 35.3 170.0 47 363 +2000 11 11 6 14 JOYCE 12.8 0.7 149 467 +1952 5 21 0 1 WILLIAM 59.4 283.3 127 573 +1995 11 5 18 4 WILLIAM 15.9 13.5 148 46 +1952 2 16 6 24 BERYL 24.1 198.0 10 387 +1979 5 25 0 15 DEBBY 68.3 305.6 45 304 +1960 10 15 12 11 WILLIAM 26.8 41.7 145 482 +1986 2 11 6 11 ALBERTO 32.3 126.4 102 176 +1958 6 25 0 15 TONY 38.5 259.4 41 115 +1980 2 3 18 6 OSCAR 66.9 167.5 120 309 +1962 9 5 18 5 NADINE 11.1 189.8 86 455 +1988 10 3 0 12 TONY 60.9 213.5 124 278 +1982 12 22 18 15 JOYCE 65.3 135.6 121 165 +1976 3 22 12 23 RAFAEL 66.2 49.7 94 298 +1995 2 3 6 28 CHRIS 28.0 156.6 140 126 +1997 4 15 12 22 TONY 16.7 36.0 97 168 +1999 12 11 12 16 RAFAEL 53.7 59.1 28 424 +2003 12 12 18 8 VALERIE 17.1 41.6 30 62 +1998 7 22 12 28 RAFAEL 53.3 173.1 123 784 +1978 5 1 12 28 ERNESTO 64.7 170.6 41 187 +1961 7 21 12 23 SANDY 10.2 265.0 150 327 +1952 4 18 0 17 ALBERTO 32.8 14.7 52 681 +2004 8 20 6 22 NADINE 12.2 246.0 156 644 +1977 9 19 0 11 PATTY 8.3 319.0 22 647 +1966 12 21 0 21 OSCAR 58.4 129.3 154 217 +1954 1 16 18 18 NADINE 10.4 319.3 136 225 +1974 5 28 18 10 ISAAC 26.6 290.7 75 348 +1987 10 22 18 23 GORDON 63.1 88.3 42 145 +1959 10 23 6 20 VALERIE 10.2 51.0 62 675 +1973 3 4 18 14 DEBBY 52.7 122.1 88 534 +1973 4 18 6 27 VALERIE 69.8 125.2 72 366 +1964 10 23 12 28 NADINE 26.3 144.1 78 813 +1998 9 26 0 21 LESLIE 68.5 222.3 121 663 +1972 3 28 6 8 OSCAR 39.6 68.4 144 525 +1965 7 28 0 27 PATTY 69.8 258.1 110 673 +1984 5 19 0 25 JOYCE 7.2 189.3 20 770 +1957 8 14 18 27 PATTY 44.3 63.5 139 394 +1982 9 25 6 24 KIRK 42.1 354.9 118 214 +1966 12 9 6 27 ERNESTO 35.6 103.8 11 597 +1964 3 17 12 15 DEBBY 55.6 355.7 76 875 +1984 3 23 0 11 ISAAC 31.5 198.3 103 672 +1989 11 4 18 28 WILLIAM 66.0 100.3 127 530 +1960 8 18 18 20 ERNESTO 68.9 263.2 112 270 +1962 10 23 6 13 KIRK 47.4 100.1 102 213 +1964 8 20 12 17 JOYCE 35.0 118.9 139 345 +1967 9 12 18 10 LESLIE 24.3 164.2 73 94 +1964 7 7 18 4 DEBBY 66.5 79.2 91 845 +1991 2 5 0 13 TONY 54.5 17.6 23 820 +1983 2 17 18 10 DEBBY 15.9 308.2 59 843 +1986 2 22 18 25 GORDON 23.8 305.2 97 735 +1970 5 8 18 13 FLORENCE 18.6 200.9 98 461 +1995 8 27 6 13 GORDON 63.6 112.3 132 400 +1981 6 16 0 2 FLORENCE 43.4 143.8 109 862 +1969 8 21 12 28 NADINE 27.6 249.0 39 801 +1972 8 20 0 15 JOYCE 42.5 145.5 80 522 +1959 11 16 18 14 ALBERTO 39.7 123.6 131 686 +1998 1 8 18 18 RAFAEL 25.5 17.2 123 127 +1967 8 7 0 28 SANDY 63.0 138.8 154 127 +1999 6 23 6 23 SANDY 27.6 9.5 59 225 +1988 9 28 12 1 TONY 13.0 205.2 27 816 +2002 12 14 18 14 CHRIS 22.4 32.5 34 484 +1962 5 18 0 20 VALERIE 64.2 160.0 148 585 +1989 5 6 12 5 FLORENCE 13.8 254.3 88 397 +1950 7 6 0 4 FLORENCE 27.6 163.6 65 500 +1985 6 21 0 6 CHRIS 54.1 233.6 127 812 +1963 5 14 0 5 CHRIS 19.5 223.4 144 843 +1958 1 4 6 23 CHRIS 49.2 24.4 79 145 +1970 12 16 6 7 DEBBY 51.5 220.3 106 525 +1980 9 16 12 7 VALERIE 9.2 348.0 38 848 +1977 3 26 18 13 HELENE 11.4 234.9 64 789 +1999 1 16 6 7 DEBBY 54.0 109.0 123 352 +1995 2 4 12 10 LESLIE 59.5 13.3 82 85 +1970 2 24 12 10 VALERIE 39.6 348.4 23 500 +1959 1 10 12 23 GORDON 11.1 116.6 30 591 +1974 8 5 12 5 FLORENCE 30.7 2.6 114 175 +1980 9 25 0 8 JOYCE 28.2 347.9 90 225 +1974 6 12 6 20 RAFAEL 17.1 111.0 45 499 +1968 10 20 0 1 RAFAEL 62.1 83.2 78 160 +1982 7 4 12 5 PATTY 13.2 216.1 112 261 +1983 2 22 12 11 TONY 43.0 91.2 163 249 +1990 8 24 12 27 VALERIE 20.9 88.2 71 360 +1950 7 17 12 14 LESLIE 20.8 115.3 16 235 +1972 10 8 6 19 ISAAC 19.2 352.6 146 281 +1979 9 19 0 23 OSCAR 52.8 339.7 148 449 +1968 4 6 12 5 GORDON 66.4 67.5 71 595 +1975 6 16 18 21 LESLIE 63.4 179.9 21 848 +1964 1 3 18 22 TONY 26.8 111.6 72 454 +1984 3 24 18 5 RAFAEL 49.0 95.2 44 527 +1957 10 16 0 20 ISAAC 28.6 251.9 124 332 +1967 11 11 12 4 DEBBY 38.2 211.4 52 213 +1953 9 15 18 27 KIRK 48.8 264.7 119 163 +1998 11 23 0 25 MICHAEL 41.4 29.0 84 742 +2003 4 28 18 7 SANDY 18.0 278.6 85 798 +1986 9 24 12 19 HELENE 8.7 43.8 84 775 +1974 4 13 18 7 SANDY 64.3 186.1 110 272 +2000 9 16 12 17 FLORENCE 51.6 67.7 115 267 +1970 12 27 0 20 SANDY 8.1 189.0 29 245 +2001 6 14 12 27 LESLIE 63.8 19.2 153 657 +1953 11 5 0 27 WILLIAM 12.9 46.6 113 47 +1997 8 9 6 16 ISAAC 17.4 199.1 73 556 +1956 4 25 18 21 KIRK 46.3 72.9 142 415 +1974 7 23 6 21 VALERIE 25.7 351.0 91 676 +1988 3 3 12 4 CHRIS 60.0 208.4 72 206 +1967 1 2 6 25 FLORENCE 42.2 269.3 149 323 +1976 9 10 6 6 ISAAC 61.4 51.5 29 558 +1968 8 11 6 19 BERYL 54.8 356.9 32 310 +1973 4 5 0 27 KIRK 35.2 180.2 36 234 +1995 6 17 0 2 SANDY 56.5 287.5 85 387 +1974 6 10 0 11 NADINE 48.0 40.9 137 886 +1988 8 18 0 9 RAFAEL 39.5 50.5 31 312 +1999 12 5 6 12 TONY 29.8 61.1 41 769 +1957 6 1 18 26 HELENE 33.3 62.0 105 48 +1978 7 14 12 22 CHRIS 10.9 273.1 93 504 +1969 7 3 18 4 PATTY 8.9 37.0 91 123 +1984 7 1 6 18 ALBERTO 11.1 191.9 133 148 +1972 1 22 6 16 BERYL 63.4 125.5 103 452 +2001 12 7 0 25 TONY 24.6 168.3 100 139 +1993 6 24 18 4 CHRIS 18.6 308.0 78 785 +1972 4 6 0 25 MICHAEL 46.1 310.0 163 772 +1990 6 11 0 17 ALBERTO 45.7 94.3 117 446 +1997 3 19 18 3 PATTY 27.0 199.8 32 251 +1980 7 17 6 6 HELENE 48.9 35.7 83 419 +1957 8 17 18 19 MICHAEL 28.7 14.3 25 340 +1966 1 27 12 19 DEBBY 38.0 269.1 30 790 +1957 4 15 12 7 NADINE 60.9 9.8 133 332 +1994 9 20 18 17 BERYL 24.4 10.4 80 664 +1996 11 13 18 12 FLORENCE 30.2 123.2 117 459 +1992 12 24 18 26 NADINE 27.3 234.2 92 654 +1986 7 22 18 21 HELENE 9.1 96.4 116 84 +1976 3 8 18 23 KIRK 33.5 308.7 80 313 +1990 6 21 12 1 GORDON 51.8 3.8 55 634 +1989 5 21 6 6 WILLIAM 22.4 207.7 122 661 +1998 11 10 6 5 JOYCE 11.3 241.9 71 505 +1973 8 3 18 3 ISAAC 55.7 261.4 54 720 +2000 11 20 12 7 NADINE 45.9 140.5 130 264 +1976 4 9 6 27 ISAAC 53.6 180.5 18 672 +1959 10 16 6 3 VALERIE 38.8 96.0 15 400 +1972 11 25 0 4 BERYL 59.1 305.3 71 357 +1984 7 26 12 3 JOYCE 36.1 330.5 82 876 +1996 12 26 0 25 HELENE 39.4 301.4 82 798 +1954 5 18 6 14 LESLIE 19.5 325.4 46 365 +1997 12 10 18 6 HELENE 26.5 325.2 67 183 +1968 6 28 0 27 GORDON 33.5 194.9 150 861 +1967 4 24 18 24 TONY 64.9 100.8 24 707 +1961 8 20 0 1 TONY 66.5 211.5 92 664 +1967 5 5 18 17 FLORENCE 59.9 276.2 123 64 +1970 1 13 0 7 NADINE 63.2 251.4 92 699 +1956 5 17 6 9 TONY 68.0 185.4 14 331 +1999 11 28 12 27 JOYCE 57.8 116.5 143 14 +1994 6 23 12 25 NADINE 10.9 169.0 28 879 +2001 11 7 18 28 WILLIAM 25.6 31.8 50 829 +1993 11 26 6 26 LESLIE 22.4 201.5 125 280 +1980 12 21 0 25 ALBERTO 35.3 93.8 82 14 +1992 2 24 12 8 ISAAC 11.4 308.1 99 685 +1995 1 14 12 7 VALERIE 24.7 313.0 111 107 +1976 1 12 12 23 GORDON 60.8 354.4 113 175 +1998 11 28 12 20 VALERIE 40.8 58.0 144 435 +1953 12 4 18 18 VALERIE 11.9 101.9 45 489 +1969 1 20 6 8 NADINE 48.5 275.3 109 468 +1968 1 11 12 6 RAFAEL 60.5 21.4 140 651 +1994 1 1 12 19 CHRIS 10.4 279.6 74 415 +1992 3 9 12 3 WILLIAM 34.9 344.0 149 530 +2000 8 9 0 28 BERYL 44.8 91.6 73 721 +1992 6 18 12 9 KIRK 24.6 180.5 57 42 +1959 4 27 18 16 KIRK 51.3 298.3 84 398 +1972 11 6 18 11 OSCAR 55.3 102.9 46 300 +1987 10 15 18 4 RAFAEL 35.7 345.0 144 161 +1966 2 25 12 20 DEBBY 53.7 341.9 63 191 +1999 7 9 18 17 KIRK 56.4 321.3 121 568 +1983 6 26 18 14 GORDON 44.7 235.8 86 618 +1995 11 26 6 4 GORDON 33.3 102.2 81 810 +1980 11 10 12 6 FLORENCE 7.5 5.2 107 130 +2004 12 20 6 21 BERYL 36.7 270.0 149 79 +1982 11 11 18 21 KIRK 69.8 341.2 62 232 +2000 3 24 0 3 SANDY 15.9 336.6 32 180 +1970 11 9 18 12 LESLIE 40.5 352.7 37 12 +1968 1 10 12 28 PATTY 59.7 224.9 84 326 +1980 6 12 12 12 RAFAEL 8.2 57.6 95 646 +1959 10 12 0 12 HELENE 7.0 5.3 17 578 +1998 3 5 18 12 KIRK 14.7 66.3 53 135 +1968 12 3 0 26 JOYCE 25.6 88.9 143 801 +1995 10 16 18 20 FLORENCE 33.7 48.9 119 708 +1986 3 19 0 20 LESLIE 31.4 287.2 78 231 +1966 9 17 6 27 HELENE 59.2 35.3 78 698 +1960 4 25 6 6 FLORENCE 40.8 286.5 139 27 +1985 1 24 18 19 BERYL 56.6 22.2 104 158 +1965 3 26 0 9 KIRK 23.0 214.2 102 807 +1980 7 13 0 10 JOYCE 60.9 84.0 13 312 +1970 9 27 0 23 PATTY 8.2 331.8 96 627 +2002 2 8 6 13 HELENE 31.4 245.3 88 401 +1978 6 21 0 21 CHRIS 53.6 224.2 147 456 +1984 3 24 18 26 KIRK 22.4 38.6 160 372 +1967 6 6 12 15 CHRIS 66.9 70.9 46 72 +1971 3 16 18 18 BERYL 38.5 21.9 82 758 +1986 3 23 6 1 DEBBY 38.2 347.3 114 591 +1974 4 13 12 15 HELENE 19.7 108.8 17 878 +1968 7 20 12 10 SANDY 31.1 234.6 38 226 +1978 11 26 18 6 PATTY 51.7 185.6 31 471 +1997 10 12 12 24 MICHAEL 52.1 249.5 138 820 +1952 7 12 12 26 FLORENCE 54.1 289.9 34 78 +1971 7 11 0 7 OSCAR 38.7 314.4 144 289 +1988 10 2 18 6 GORDON 49.0 145.2 35 215 +1977 8 8 18 25 VALERIE 9.1 263.0 12 319 +1966 12 15 18 22 ISAAC 36.0 215.7 109 562 +1991 10 4 6 9 ALBERTO 28.5 314.6 23 445 +1995 7 9 18 15 DEBBY 32.4 313.6 127 356 +1979 7 19 12 12 DEBBY 29.1 168.3 64 208 +1993 6 19 6 6 MICHAEL 49.5 241.7 116 484 +1991 1 12 12 13 ISAAC 10.1 354.6 57 160 +1969 8 20 18 16 TONY 8.0 138.7 16 551 +1987 5 3 12 4 SANDY 57.6 196.2 129 468 +1960 11 26 0 4 DEBBY 66.7 148.6 10 607 +1997 6 20 12 24 CHRIS 69.2 214.3 13 307 +1998 4 18 18 10 ALBERTO 32.0 168.9 20 67 +1950 9 14 6 21 ALBERTO 24.2 243.1 154 888 +1991 12 24 0 27 KIRK 59.2 336.2 134 189 +1998 4 19 18 21 VALERIE 66.4 69.9 29 179 +1997 1 20 0 20 ALBERTO 14.0 20.6 55 426 +1985 1 24 6 22 ERNESTO 55.6 122.4 58 123 +1956 10 22 12 14 HELENE 35.6 306.8 50 504 +1994 9 28 6 4 WILLIAM 67.9 133.5 160 413 +1973 12 14 18 1 RAFAEL 15.8 4.5 120 11 +2002 3 28 0 19 RAFAEL 28.8 203.7 89 215 +1951 8 24 18 14 PATTY 25.3 355.7 75 783 +1985 5 19 6 24 MICHAEL 24.6 193.1 141 283 +1966 9 7 18 25 TONY 30.3 306.0 126 342 +1988 4 9 0 13 ISAAC 21.1 268.0 88 469 +1962 5 18 18 25 DEBBY 40.8 44.0 73 514 +2001 10 15 6 11 FLORENCE 17.4 180.1 58 252 +1962 12 8 0 3 NADINE 20.1 54.5 24 364 +1961 11 9 6 13 HELENE 54.3 204.7 156 350 +1954 10 2 12 27 PATTY 12.2 96.7 15 266 +1963 4 23 12 7 NADINE 30.6 164.8 123 616 +1979 8 5 18 17 OSCAR 62.3 9.8 46 281 +1984 1 11 0 28 DEBBY 70.0 160.7 28 428 +1964 2 7 0 25 SANDY 24.1 88.1 40 725 +1992 12 1 12 19 WILLIAM 48.6 92.4 14 353 +1962 3 7 18 8 SANDY 42.5 348.5 11 51 +1953 12 23 18 5 ALBERTO 13.7 221.9 120 266 +1976 11 25 18 13 GORDON 41.1 289.1 128 41 +2000 8 25 12 9 FLORENCE 48.9 146.1 62 363 +1954 6 3 12 6 ISAAC 21.2 22.1 86 570 +1953 4 4 12 14 OSCAR 50.6 170.9 119 758 +1960 1 2 0 16 KIRK 11.6 228.7 158 25 +1971 6 21 6 11 KIRK 42.0 132.8 71 435 +1999 4 17 6 23 PATTY 17.6 195.6 94 130 +1979 9 17 18 27 BERYL 20.4 234.6 109 788 +1952 6 15 12 17 WILLIAM 28.5 216.9 113 609 +1992 4 26 6 9 OSCAR 24.7 87.4 142 197 +1979 11 3 18 28 CHRIS 32.1 162.5 48 502 +1977 4 26 18 2 WILLIAM 25.7 170.0 73 837 +2002 8 17 18 20 ALBERTO 59.2 282.6 43 708 +1975 3 16 6 16 ISAAC 51.3 234.2 55 801 +1965 4 4 0 25 SANDY 7.1 150.4 107 857 +1980 5 18 18 12 FLORENCE 14.0 155.0 68 581 +2000 5 10 0 22 ALBERTO 62.8 75.8 114 616 +1980 6 1 6 15 GORDON 63.1 352.2 120 499 +1956 1 14 6 4 HELENE 31.9 215.2 99 423 +2002 1 8 0 22 GORDON 61.5 141.4 16 272 +1957 5 18 6 5 PATTY 40.4 271.9 134 726 +1991 9 19 0 1 CHRIS 37.8 100.1 163 403 +1951 3 4 0 24 VALERIE 36.0 308.8 116 742 +1992 6 10 18 28 SANDY 66.2 236.8 102 331 +1982 3 25 18 26 MICHAEL 7.9 105.7 118 428 +1991 6 2 6 8 GORDON 19.3 186.2 92 235 +2002 2 22 12 18 RAFAEL 9.8 303.2 114 750 +1954 9 15 6 27 HELENE 62.8 98.3 163 135 +1973 4 7 6 17 KIRK 15.2 30.1 150 503 +1969 11 3 12 17 CHRIS 36.8 302.9 105 691 +1965 3 14 12 26 DEBBY 60.7 269.0 106 399 +1997 12 8 18 21 SANDY 61.2 55.6 73 759 +1957 4 24 6 23 LESLIE 19.2 120.9 142 43 +1988 8 10 6 27 KIRK 22.3 259.2 95 295 +2004 7 21 18 24 FLORENCE 41.4 257.5 38 491 +1998 3 12 0 12 ERNESTO 16.0 19.0 97 499 +1996 5 7 6 1 DEBBY 55.2 29.7 20 818 +1975 3 11 0 5 MICHAEL 40.4 180.6 10 685 +2000 2 12 6 19 CHRIS 14.1 290.0 22 810 +1989 6 7 0 18 NADINE 35.0 107.4 143 121 +1983 6 3 18 13 BERYL 57.6 247.2 111 859 +1953 4 15 18 19 ISAAC 25.2 262.6 55 457 +1991 6 23 18 3 PATTY 42.2 10.6 158 476 +1958 8 19 0 11 KIRK 66.5 170.1 162 767 +1987 6 3 0 10 RAFAEL 25.2 330.9 81 89 +1975 8 25 18 7 LESLIE 15.5 190.4 73 72 +1994 1 13 18 23 GORDON 40.8 257.6 97 10 +1975 6 18 18 2 PATTY 29.1 230.6 133 226 +1976 11 17 12 13 FLORENCE 35.7 190.8 161 48 +1978 4 3 0 4 DEBBY 47.6 201.0 53 187 +1957 9 4 0 10 MICHAEL 30.4 223.5 157 185 +1961 11 4 12 18 JOYCE 28.5 120.7 155 608 +1982 3 25 0 6 WILLIAM 58.1 51.4 151 314 +1950 1 13 18 7 FLORENCE 20.2 165.4 49 110 +1987 7 15 6 20 PATTY 36.6 60.6 153 546 +1987 2 4 18 6 ISAAC 43.3 203.1 53 79 +1962 7 23 12 18 RAFAEL 65.6 239.2 68 608 +1973 5 18 12 2 CHRIS 25.2 40.1 22 781 +2001 9 9 12 14 ALBERTO 24.3 166.2 122 121 +1986 3 20 18 14 DEBBY 22.0 152.5 51 188 +1956 7 20 12 11 NADINE 18.5 16.0 62 199 +2001 8 7 6 27 SANDY 50.5 227.4 25 314 +1981 7 7 18 15 GORDON 62.5 216.0 134 457 +1986 8 9 18 7 GORDON 27.4 225.4 11 339 +1982 9 1 0 28 NADINE 67.0 66.3 80 608 +1955 4 26 18 27 MICHAEL 36.7 192.4 59 222 +1953 9 11 0 6 TONY 36.7 346.8 147 363 +1976 1 20 6 22 GORDON 19.5 276.9 63 76 +1958 7 8 0 24 RAFAEL 40.2 209.2 90 566 +1954 2 8 6 26 ALBERTO 38.6 152.3 65 673 +1952 11 8 6 10 PATTY 42.0 250.5 13 661 +1973 5 12 18 18 ALBERTO 42.6 119.8 143 64 +1991 5 25 0 2 NADINE 49.3 277.9 83 49 +1996 8 27 18 17 MICHAEL 61.8 72.1 43 517 +1963 3 24 6 7 HELENE 53.0 337.5 107 776 +1957 10 13 6 10 MICHAEL 46.2 60.4 15 570 +1997 4 12 6 28 FLORENCE 49.0 296.5 118 640 +1997 12 28 12 17 PATTY 64.3 308.1 101 425 +1981 7 5 18 16 FLORENCE 16.1 25.7 130 676 +1986 4 3 18 13 JOYCE 10.7 174.5 75 348 +1950 2 16 12 21 RAFAEL 15.6 117.0 63 249 +1956 3 6 12 4 JOYCE 28.1 212.4 61 511 +1993 4 28 6 3 KIRK 67.1 258.3 40 366 +1961 10 17 6 18 MICHAEL 69.0 273.5 97 523 +1956 5 12 6 14 ERNESTO 12.7 280.2 77 136 +2004 3 1 18 8 VALERIE 52.7 295.9 124 248 +1998 12 16 12 8 ALBERTO 49.8 168.3 123 813 +1976 1 24 12 28 FLORENCE 22.0 151.4 21 692 +1990 3 16 18 21 DEBBY 28.3 275.1 19 502 +1954 12 21 18 1 TONY 50.2 137.2 127 11 +1995 1 24 0 23 OSCAR 23.9 243.1 15 601 +1959 10 25 18 13 RAFAEL 58.1 243.1 48 409 +1982 11 10 0 23 KIRK 8.0 245.1 41 489 +1985 7 24 0 28 PATTY 27.9 9.0 51 234 +1976 9 27 6 27 SANDY 62.0 103.8 10 385 +1959 12 11 6 27 MICHAEL 14.6 18.9 142 729 +1987 7 25 18 5 ISAAC 20.8 22.6 149 194 +2001 4 2 18 11 ERNESTO 8.8 235.0 150 893 +2003 8 15 0 5 KIRK 67.5 116.3 128 860 +1983 12 21 6 24 WILLIAM 62.3 271.0 55 810 +2001 4 15 0 3 WILLIAM 11.2 294.5 78 102 +1963 10 1 12 15 KIRK 45.4 326.4 51 683 +1969 12 23 6 8 NADINE 46.4 271.4 68 103 +1997 2 20 0 14 PATTY 58.5 126.1 114 462 +2001 5 3 0 9 MICHAEL 56.6 340.3 123 873 +1961 11 6 0 6 ERNESTO 33.4 5.9 55 208 +1982 7 4 6 2 VALERIE 67.2 273.7 55 877 +1989 1 7 12 23 TONY 44.9 269.7 163 412 +1952 9 16 6 15 OSCAR 23.2 272.0 113 94 +1991 8 5 12 2 DEBBY 32.7 200.9 14 180 +1972 3 22 0 12 WILLIAM 55.2 316.5 100 260 +1987 6 16 18 22 LESLIE 53.4 192.1 12 223 +1972 4 9 6 17 WILLIAM 55.9 180.4 132 645 +1965 12 16 12 27 KIRK 21.8 148.8 142 89 +2001 2 9 12 3 HELENE 24.4 236.9 120 620 +1975 8 23 0 14 OSCAR 44.7 94.8 153 850 +1997 6 4 0 27 ISAAC 59.5 251.2 17 550 +1964 4 28 12 26 MICHAEL 28.1 349.6 94 551 +1985 6 17 12 19 HELENE 24.5 203.4 76 536 +1972 8 15 6 10 WILLIAM 37.0 8.6 46 352 +2002 8 20 12 25 VALERIE 47.6 74.1 71 506 +1969 10 5 18 1 ALBERTO 67.2 241.5 77 470 +1968 12 10 0 7 KIRK 8.1 314.5 61 734 +1990 4 2 12 22 CHRIS 46.6 304.0 93 827 +1951 3 18 0 21 VALERIE 52.3 5.5 29 499 +1972 11 8 0 10 DEBBY 15.8 338.9 155 94 +1975 4 10 0 8 KIRK 33.2 1.8 70 451 +1960 5 26 18 21 NADINE 52.8 308.0 32 615 +1978 11 28 18 3 JOYCE 14.7 2.6 20 656 +1954 12 19 12 12 PATTY 22.5 204.3 95 149 +1977 8 21 0 17 HELENE 59.2 128.8 160 844 +1988 8 9 0 10 DEBBY 52.5 245.9 88 587 +1994 9 5 12 20 LESLIE 53.1 290.9 134 460 +1996 1 20 6 19 HELENE 69.1 348.7 87 374 +1981 3 15 12 1 CHRIS 55.0 81.3 146 224 +1993 1 22 12 4 RAFAEL 19.7 131.6 109 654 +1968 6 17 0 28 PATTY 29.7 34.9 47 384 +1994 9 11 18 27 HELENE 53.8 26.7 157 38 +1970 7 25 18 1 WILLIAM 11.2 297.4 15 680 +1976 8 26 18 17 JOYCE 38.8 221.7 160 435 +1979 1 25 12 22 RAFAEL 38.1 317.2 49 741 +1951 1 27 6 2 LESLIE 44.2 118.4 19 191 +1967 3 26 6 28 KIRK 49.7 301.6 28 372 +1955 6 2 6 18 DEBBY 14.5 315.0 115 390 +1960 2 8 12 9 NADINE 7.1 69.4 126 800 +1951 3 4 6 16 NADINE 28.6 147.7 88 759 +1994 12 10 0 12 RAFAEL 65.2 131.7 161 241 +1983 11 18 6 9 GORDON 15.1 357.5 12 873 +1950 5 25 18 20 CHRIS 52.8 38.6 24 311 +1989 9 19 6 3 VALERIE 34.3 353.9 132 682 +1964 1 5 0 26 TONY 63.3 353.4 28 610 +1986 5 5 18 16 BERYL 67.0 207.0 158 609 +1967 11 20 12 15 HELENE 30.8 329.0 76 888 +1984 12 24 12 22 NADINE 44.2 265.3 20 128 +1951 2 3 18 11 RAFAEL 12.4 69.0 164 490 +2000 6 24 18 10 GORDON 32.5 257.7 11 588 +1975 4 17 0 10 SANDY 33.7 127.4 159 743 +1954 9 11 6 20 GORDON 42.1 2.4 105 645 +1955 4 22 12 2 VALERIE 20.1 267.2 101 512 +1972 11 18 18 14 JOYCE 50.8 63.5 54 768 +1984 3 21 6 9 LESLIE 30.8 231.5 110 548 +1979 8 14 0 19 DEBBY 45.8 171.2 89 22 +1963 4 25 6 5 ERNESTO 40.2 73.3 57 689 +1985 3 12 6 19 CHRIS 47.8 215.4 155 133 +1972 12 26 18 2 ALBERTO 63.7 14.7 110 389 +2000 12 19 6 26 TONY 64.2 63.2 127 498 +2000 3 18 0 14 FLORENCE 57.2 301.5 148 89 +1994 4 11 6 21 WILLIAM 24.8 39.4 75 529 +1961 12 1 6 13 VALERIE 63.8 5.9 83 128 +1962 9 4 0 12 PATTY 63.3 342.9 150 404 +1950 11 13 12 12 WILLIAM 35.1 22.7 77 328 +1986 11 19 0 11 FLORENCE 50.2 239.1 162 136 +1976 1 16 0 16 TONY 38.6 184.0 85 229 +1966 9 15 6 9 ALBERTO 27.7 108.0 153 297 +1992 2 5 12 17 RAFAEL 61.6 183.8 57 286 +1997 1 1 0 9 JOYCE 67.7 173.3 26 153 +1980 4 7 0 24 MICHAEL 41.8 264.7 93 752 +1995 5 5 6 23 FLORENCE 60.9 298.3 73 248 +1965 2 18 12 18 ERNESTO 20.4 88.4 151 734 +1971 4 15 0 26 LESLIE 24.5 45.8 80 343 +1958 4 8 0 28 RAFAEL 43.0 13.8 50 484 +1954 2 27 12 15 DEBBY 21.7 356.6 154 161 +1990 11 25 6 27 LESLIE 38.4 94.8 122 479 +2000 3 25 12 16 SANDY 61.2 310.1 17 786 +1990 3 14 6 2 SANDY 57.1 288.4 70 228 +1972 1 24 0 13 TONY 69.2 44.4 152 423 +1994 12 12 12 17 LESLIE 60.6 309.2 35 461 +2002 3 11 18 14 ERNESTO 30.7 299.8 119 325 +1963 10 1 0 25 KIRK 68.5 91.7 69 531 +1978 6 26 18 3 ALBERTO 8.4 226.4 164 103 +1972 7 26 6 9 VALERIE 19.6 289.4 146 856 +1966 1 23 18 23 VALERIE 19.0 122.6 72 238 +1982 6 11 6 28 WILLIAM 13.3 344.6 103 883 +1970 1 16 0 20 RAFAEL 68.4 222.4 94 526 +1967 9 25 6 8 TONY 51.2 138.2 67 230 +1954 2 6 6 20 OSCAR 36.4 276.6 122 653 +1986 9 25 18 27 NADINE 20.3 339.1 91 241 +1972 10 17 12 28 RAFAEL 50.7 126.0 70 221 +1995 12 2 18 15 GORDON 46.5 255.2 132 232 +2004 12 25 18 3 WILLIAM 67.0 59.4 52 270 +1973 10 1 18 8 ISAAC 61.5 18.0 47 185 +1957 8 16 6 20 SANDY 45.0 116.1 96 54 +1968 6 25 6 27 DEBBY 16.8 325.0 75 208 +1997 11 17 12 21 GORDON 15.4 247.9 70 41 +1973 11 3 18 16 RAFAEL 68.6 256.0 156 43 +1970 8 19 18 4 OSCAR 11.0 228.0 94 851 +1985 6 28 18 1 RAFAEL 51.7 286.3 146 833 +2002 12 27 18 21 PATTY 7.9 264.7 131 628 +1967 1 24 18 12 ALBERTO 67.4 227.2 140 383 +1987 2 15 18 9 JOYCE 61.4 207.2 145 423 +1971 2 13 0 10 LESLIE 18.5 283.4 111 460 +1976 4 7 0 9 RAFAEL 27.6 60.7 107 677 +1985 5 13 0 19 TONY 12.3 283.2 162 81 +1986 12 4 12 28 GORDON 40.8 39.7 32 631 +1990 2 5 0 7 OSCAR 48.4 14.6 78 830 +1957 9 26 18 5 PATTY 26.3 251.4 96 459 +1984 2 25 12 11 FLORENCE 67.8 46.6 17 893 +1965 7 10 6 20 OSCAR 69.1 93.1 151 809 +1972 7 3 0 18 LESLIE 68.4 172.0 46 353 +1967 4 19 18 17 TONY 19.0 80.4 97 362 +1957 6 6 0 23 ERNESTO 62.0 285.7 116 222 +1970 6 23 0 25 JOYCE 18.5 305.0 76 731 +1994 5 17 12 2 CHRIS 55.0 249.2 28 297 +1951 6 1 6 2 GORDON 9.5 314.4 17 412 +1959 5 10 0 17 HELENE 11.7 69.0 132 838 +1972 8 3 6 10 HELENE 67.1 211.0 93 163 +2004 11 7 6 1 GORDON 7.3 59.5 74 42 +1971 10 23 12 2 PATTY 49.2 15.7 158 746 +1969 3 8 12 17 FLORENCE 42.2 67.2 21 797 +1972 1 11 12 12 JOYCE 60.2 146.5 40 535 +1962 7 18 6 9 GORDON 33.1 313.9 26 795 +1975 6 22 12 6 TONY 16.0 357.1 66 610 +1960 10 7 0 25 TONY 21.8 3.5 14 550 +1981 6 11 6 25 GORDON 7.1 182.9 23 707 +1956 1 26 0 19 WILLIAM 11.4 39.4 109 687 +1978 9 8 12 6 PATTY 54.6 321.4 109 739 +1955 2 14 12 19 NADINE 47.1 10.5 127 276 +1969 8 5 0 1 CHRIS 11.9 36.5 27 503 +1963 3 8 18 22 MICHAEL 53.9 208.2 106 515 +1991 2 11 0 10 SANDY 30.1 177.6 51 405 +1963 7 7 0 6 WILLIAM 37.9 59.7 129 708 +2003 1 26 18 18 JOYCE 53.2 54.6 40 71 +2002 1 2 0 22 ERNESTO 43.4 27.2 120 800 +1982 1 3 18 24 ALBERTO 56.2 122.8 33 169 +1991 4 26 18 24 CHRIS 48.0 207.3 132 31 +1993 2 12 18 10 RAFAEL 7.8 188.7 159 531 +1969 5 10 12 2 OSCAR 66.3 105.8 15 517 +1985 4 20 18 23 ISAAC 61.7 90.0 68 392 +1987 2 27 6 4 FLORENCE 58.2 13.9 60 132 +1964 12 23 12 25 HELENE 49.8 322.7 130 273 +1976 1 24 0 23 LESLIE 58.1 278.9 147 445 +1966 1 19 6 19 ISAAC 42.5 241.1 133 641 +1953 5 9 12 19 BERYL 50.3 336.6 13 500 +1979 2 24 12 1 BERYL 64.8 76.1 27 478 +1964 2 14 18 11 RAFAEL 44.7 328.5 38 805 +1956 9 9 6 28 DEBBY 49.8 45.3 103 217 +1963 9 28 6 14 DEBBY 64.7 178.9 160 30 +1965 9 25 12 18 PATTY 50.4 353.1 129 656 +1979 12 20 6 18 VALERIE 53.5 34.6 34 229 +1969 7 5 12 12 ERNESTO 60.3 43.3 150 440 +1995 9 25 18 20 NADINE 61.7 189.5 106 666 +1997 9 25 12 3 OSCAR 22.7 178.8 57 753 +1951 11 1 12 16 ERNESTO 43.9 239.2 147 829 +2002 8 17 18 26 BERYL 64.0 341.2 45 708 +1965 1 21 18 5 LESLIE 51.5 140.4 34 760 +1986 1 18 0 1 JOYCE 21.5 193.0 79 823 +1992 7 19 6 9 CHRIS 25.2 278.7 101 416 +1964 11 8 18 4 WILLIAM 48.0 125.1 61 105 +1968 5 28 0 15 ERNESTO 30.1 251.5 58 873 +1992 5 12 12 10 FLORENCE 59.5 222.9 158 201 +2003 4 13 6 25 NADINE 36.3 71.3 21 670 +1988 8 13 12 10 OSCAR 10.2 253.5 139 876 +1971 1 21 6 4 PATTY 21.8 126.3 52 618 +1970 7 14 6 12 SANDY 10.2 142.5 117 865 +1996 12 17 6 7 FLORENCE 60.6 82.7 153 181 +1957 1 8 18 12 OSCAR 67.3 125.9 82 64 +2001 5 22 0 20 OSCAR 45.6 265.1 157 125 +1958 12 27 0 25 KIRK 40.3 192.3 93 19 +1975 10 25 6 13 BERYL 51.0 312.0 150 81 +1953 10 20 6 11 KIRK 53.6 229.9 112 609 +1952 12 15 6 13 NADINE 50.9 66.1 30 32 +1986 7 2 0 22 FLORENCE 68.1 5.6 40 717 +1997 8 27 18 25 PATTY 52.8 235.8 156 291 +1958 11 16 6 19 ALBERTO 65.7 240.7 145 567 +1998 11 16 18 15 WILLIAM 32.9 83.1 129 71 +1986 5 17 12 24 JOYCE 44.1 313.8 45 350 +1957 9 19 18 8 KIRK 34.5 125.1 148 179 +1962 1 5 6 20 OSCAR 57.1 179.0 19 538 +1999 8 8 6 28 LESLIE 23.7 81.1 105 736 +1951 6 20 12 20 ISAAC 22.3 66.8 120 62 +1961 11 18 0 19 VALERIE 41.2 217.5 101 837 +1980 10 10 0 12 VALERIE 41.8 193.8 76 744 +1985 5 14 0 10 HELENE 46.9 128.9 74 339 +1954 7 20 18 21 OSCAR 57.8 354.0 133 538 +1988 8 16 18 19 MICHAEL 45.4 233.2 92 95 +1969 8 10 18 12 HELENE 58.0 4.1 43 362 +1971 2 10 12 15 MICHAEL 8.5 227.5 147 490 +1970 3 15 18 12 GORDON 58.8 189.0 118 294 +1976 1 12 12 3 PATTY 64.0 160.3 65 775 +1973 6 28 12 18 LESLIE 25.1 34.9 160 643 +1981 4 10 6 28 SANDY 51.0 315.4 69 277 +1963 3 11 12 14 HELENE 20.0 295.8 25 368 +2002 12 8 18 27 SANDY 31.2 158.4 19 647 +1997 10 7 12 17 OSCAR 64.2 100.3 37 763 +1950 3 16 18 23 DEBBY 7.1 40.4 88 638 +1986 11 8 18 23 ALBERTO 38.5 349.0 63 698 +1994 11 25 12 9 JOYCE 26.0 177.1 96 365 +2001 8 23 12 7 CHRIS 60.1 237.8 26 827 +1993 1 14 18 17 NADINE 35.7 215.9 75 79 +1967 12 12 12 4 KIRK 50.6 270.2 116 876 +1992 8 19 6 24 SANDY 15.5 288.1 130 268 +1999 1 10 6 15 MICHAEL 63.4 255.4 66 326 +1975 3 4 0 21 OSCAR 36.0 140.8 54 69 +1990 4 17 18 2 ALBERTO 50.8 241.5 108 257 +1970 3 3 18 18 NADINE 30.6 231.8 61 440 +1956 9 18 6 24 FLORENCE 37.0 193.3 15 432 +1961 1 13 6 26 BERYL 65.7 285.0 118 577 +1966 6 26 0 11 OSCAR 60.0 232.4 67 203 +1966 7 6 0 6 WILLIAM 51.9 259.1 101 152 +1968 11 14 18 3 PATTY 61.0 200.8 101 313 +1976 9 16 12 18 CHRIS 8.1 248.1 115 253 +2001 8 9 6 25 GORDON 36.8 234.2 104 8 +1960 7 8 6 17 KIRK 53.4 273.0 140 108 +1987 3 28 0 3 ALBERTO 60.1 266.5 104 508 +2001 11 16 6 1 CHRIS 66.4 298.7 69 788 +2004 12 11 18 1 GORDON 64.6 197.8 102 559 +1958 12 28 6 10 OSCAR 27.8 276.3 16 814 +1954 5 26 12 26 ISAAC 45.3 344.5 38 817 +1954 10 14 0 9 DEBBY 32.2 133.3 72 139 +1962 4 28 0 17 GORDON 24.6 267.6 122 823 +1989 9 22 6 17 GORDON 54.2 348.2 38 732 +1963 11 10 18 5 NADINE 29.1 335.9 43 451 +1972 5 11 6 8 FLORENCE 18.7 284.5 97 504 +1984 8 21 18 23 ISAAC 63.7 308.4 121 198 +1997 7 14 0 5 MICHAEL 56.1 224.1 119 503 +1968 6 24 12 19 PATTY 23.4 301.2 13 774 +1969 6 15 0 15 LESLIE 9.3 221.3 22 885 +1998 12 26 18 22 RAFAEL 57.4 319.0 68 745 +1969 12 16 12 7 SANDY 12.8 47.5 75 39 +1960 11 8 12 3 ERNESTO 64.1 65.9 127 834 +1996 7 18 18 25 HELENE 30.0 12.9 54 860 +1970 6 17 0 12 LESLIE 63.0 242.5 131 152 +1968 3 14 18 20 NADINE 24.5 40.1 32 152 +2000 3 8 18 2 VALERIE 28.9 231.0 139 469 +1978 2 18 12 21 KIRK 66.6 28.6 17 369 +1958 7 12 6 18 ERNESTO 7.8 29.3 82 556 +1988 7 22 18 10 PATTY 41.0 40.5 68 761 +1976 6 8 0 10 TONY 63.7 106.6 32 424 +1984 3 28 0 5 CHRIS 54.1 105.7 113 665 +1969 3 11 12 25 SANDY 16.0 242.3 57 4 +1996 8 28 0 28 RAFAEL 12.3 350.2 41 878 +1972 3 5 0 10 GORDON 59.8 269.8 121 843 +1994 8 10 18 10 PATTY 24.8 64.9 46 694 +1955 1 4 18 25 KIRK 67.3 233.5 58 860 +1983 12 23 12 27 FLORENCE 17.8 200.0 149 752 +1984 2 4 6 20 ALBERTO 58.9 114.6 92 808 +1984 6 2 12 24 DEBBY 32.2 341.1 23 292 +1965 3 20 12 11 OSCAR 30.2 114.8 94 741 +1961 11 14 6 5 ERNESTO 45.7 131.8 48 318 +1983 8 21 12 1 ERNESTO 67.7 104.0 140 645 +1985 12 19 0 6 RAFAEL 51.7 242.2 127 643 +1956 5 27 18 7 FLORENCE 25.2 357.7 30 727 +1953 3 28 0 24 DEBBY 10.0 276.4 17 153 +1980 3 12 12 18 VALERIE 55.4 320.7 40 660 +1952 10 11 18 15 CHRIS 59.6 281.9 80 513 +1964 10 27 12 26 OSCAR 52.6 162.6 36 651 +1958 2 21 12 10 PATTY 65.4 108.0 154 135 +1998 4 12 6 6 NADINE 55.9 56.4 75 513 +1969 11 3 18 9 LESLIE 60.9 35.3 113 592 +1964 7 10 6 28 TONY 47.8 269.6 59 278 +1965 12 19 18 13 LESLIE 59.7 163.9 137 7 +1987 12 1 0 24 ALBERTO 62.4 100.0 108 489 +1965 6 17 0 18 WILLIAM 28.1 315.2 134 563 +1956 6 1 6 9 TONY 63.9 78.2 30 379 +1981 4 15 18 1 BERYL 38.9 64.9 66 42 +1981 11 11 0 12 SANDY 59.4 269.2 40 692 +2000 3 23 6 12 JOYCE 29.1 225.9 19 592 +1950 4 28 18 12 VALERIE 29.7 289.2 34 316 +1950 8 18 6 8 KIRK 13.4 21.3 61 153 +1957 4 6 18 19 ERNESTO 55.9 296.6 96 684 +1970 6 9 18 9 DEBBY 61.3 115.1 62 507 +1967 2 24 0 22 ISAAC 33.1 202.2 150 323 +1999 1 1 0 8 VALERIE 45.5 297.3 76 897 +1976 12 1 0 4 JOYCE 50.8 11.3 35 226 +1957 9 8 0 16 JOYCE 7.2 204.6 64 831 +2001 5 25 0 5 CHRIS 35.3 67.1 57 202 +1953 5 9 18 3 ISAAC 68.4 216.0 104 153 +1969 7 5 6 23 VALERIE 19.0 322.6 155 200 +1997 1 6 18 7 VALERIE 60.0 68.0 49 777 +1994 2 20 12 8 MICHAEL 10.4 293.8 42 231 +1977 11 1 0 4 PATTY 48.5 226.9 103 804 +1988 5 9 18 3 JOYCE 52.0 103.2 135 380 +1979 9 10 18 6 ALBERTO 55.5 107.3 55 540 +1988 8 1 0 6 PATTY 39.7 145.5 57 365 +1955 7 24 12 3 LESLIE 35.0 322.5 74 549 +2004 8 12 0 7 SANDY 24.8 70.8 50 549 +1967 1 1 18 10 ISAAC 23.1 282.9 90 739 +1980 4 13 6 12 TONY 19.5 225.7 123 405 +1965 1 2 12 6 WILLIAM 61.2 70.7 159 669 +1995 10 16 12 15 SANDY 29.0 103.8 153 615 +1974 3 18 6 12 ERNESTO 11.1 304.7 65 553 +1962 9 15 6 5 DEBBY 7.7 50.0 114 410 +1992 11 2 6 1 ERNESTO 53.0 353.0 92 346 +1954 7 1 18 23 KIRK 10.8 39.5 142 81 +1993 3 17 12 1 OSCAR 22.8 195.1 42 783 +1978 9 6 6 11 FLORENCE 59.2 137.0 149 598 +1966 9 18 0 8 SANDY 13.7 65.9 82 316 +1998 6 7 12 24 PATTY 7.5 121.4 73 765 +1988 2 27 0 1 RAFAEL 44.5 181.8 114 434 +1971 7 25 18 5 ERNESTO 56.5 159.9 96 608 +1977 5 6 18 8 RAFAEL 18.1 97.5 100 414 +2003 7 23 6 14 HELENE 29.9 109.5 161 37 +1956 5 18 0 15 OSCAR 39.8 69.2 91 742 +1987 8 19 18 11 FLORENCE 7.8 180.1 105 261 +1981 10 7 18 25 DEBBY 33.6 95.7 72 357 +1986 2 8 18 4 PATTY 13.1 86.2 100 291 +1990 7 16 18 10 WILLIAM 41.4 188.9 109 630 +1992 4 15 6 17 OSCAR 52.6 272.1 60 359 +1958 11 17 0 8 GORDON 26.3 40.4 22 204 +1974 11 20 6 11 VALERIE 67.4 307.7 163 501 +1962 5 7 6 23 NADINE 35.1 11.1 74 4 +1957 6 3 18 28 SANDY 10.2 330.4 26 280 +1977 5 10 12 4 DEBBY 36.8 87.9 86 754 +1991 7 13 12 24 CHRIS 23.7 235.4 149 774 +1993 4 6 0 27 CHRIS 38.3 136.9 64 309 +2002 5 27 0 11 GORDON 31.9 90.9 57 677 +1955 6 6 18 19 JOYCE 23.2 176.3 152 542 +1953 9 14 18 27 HELENE 17.7 234.6 157 33 +1995 5 25 6 15 ALBERTO 53.1 261.4 115 202 +1990 8 23 6 7 TONY 63.6 80.0 119 216 +1971 8 8 6 23 DEBBY 46.0 200.4 12 132 +1980 11 16 0 27 DEBBY 41.9 31.2 33 5 +1994 10 25 6 26 DEBBY 22.4 162.9 74 357 +1953 8 7 0 26 RAFAEL 16.8 67.9 120 182 +1969 6 27 18 7 ERNESTO 45.1 338.6 60 358 +1952 12 3 18 24 LESLIE 41.3 262.2 121 779 +1978 7 27 18 14 ISAAC 22.2 166.0 156 652 +2002 11 22 18 24 BERYL 41.8 231.8 51 741 +2003 12 11 0 26 NADINE 39.5 210.4 151 615 +2000 11 2 6 11 SANDY 15.5 32.7 156 115 +1959 3 12 18 2 WILLIAM 39.4 33.3 148 287 +1993 9 17 0 3 GORDON 24.6 118.6 138 342 +1992 10 28 18 1 WILLIAM 24.6 162.0 102 11 +1989 5 24 12 20 MICHAEL 7.4 210.9 143 662 +1958 11 25 18 24 VALERIE 13.2 38.3 116 488 +1984 4 14 6 10 JOYCE 64.8 24.4 118 177 +1960 10 24 12 11 TONY 52.6 125.7 27 806 +1969 6 1 0 2 ALBERTO 18.1 88.6 16 370 +1986 3 25 12 10 GORDON 16.2 61.6 39 47 +1997 4 6 12 25 TONY 43.0 47.3 16 504 +1971 9 26 12 26 WILLIAM 36.2 329.3 151 66 +1992 7 3 6 10 SANDY 14.2 349.9 158 339 +1966 8 4 12 1 RAFAEL 16.0 357.8 163 672 +1973 8 2 6 24 DEBBY 35.3 327.2 21 652 +1994 2 13 0 15 LESLIE 36.3 255.8 127 283 +2003 11 13 0 27 FLORENCE 20.0 351.2 72 107 +2002 11 3 12 12 BERYL 55.4 34.7 42 846 +1980 6 21 6 28 DEBBY 27.8 105.0 21 583 +1960 7 6 0 18 SANDY 12.4 297.9 118 1 +1995 5 19 0 23 ISAAC 60.3 40.5 40 560 +1963 6 18 0 7 VALERIE 36.5 239.4 107 566 +2004 6 27 6 24 MICHAEL 65.7 160.1 128 278 +1964 8 4 0 27 ALBERTO 26.3 184.4 143 356 +1971 5 15 6 25 ERNESTO 50.7 222.7 48 421 +2004 1 6 6 6 SANDY 19.6 12.5 157 198 +1988 11 27 6 20 FLORENCE 35.6 281.6 47 859 +1961 8 9 18 17 NADINE 50.6 92.7 47 691 +1989 3 17 12 21 MICHAEL 8.5 4.3 129 287 +1988 2 24 6 10 WILLIAM 24.2 221.4 103 571 +1997 2 2 6 3 HELENE 60.6 30.0 153 850 +2001 5 22 18 24 ERNESTO 28.6 201.2 125 112 +1966 3 11 0 4 PATTY 41.4 253.7 63 726 +1995 12 16 6 17 VALERIE 40.5 318.2 86 181 +2004 5 11 12 15 JOYCE 63.5 355.1 110 14 +2001 3 28 18 12 ERNESTO 9.6 173.9 105 137 +1989 9 17 6 18 ISAAC 33.2 92.7 108 792 +1964 10 4 0 3 HELENE 42.7 27.6 120 548 +1976 11 24 6 23 ALBERTO 61.2 263.6 94 36 +1993 1 17 12 10 NADINE 33.8 42.8 134 847 +1995 2 26 12 24 RAFAEL 33.7 30.0 28 130 +1964 7 7 0 5 SANDY 55.0 300.4 92 157 +1958 11 8 0 1 WILLIAM 17.0 280.1 26 679 +1953 6 20 12 15 TONY 22.3 2.4 33 538 +1959 4 4 18 17 NADINE 10.2 252.2 83 828 +1969 5 7 12 22 VALERIE 42.9 251.4 19 529 +1992 7 9 12 2 TONY 60.5 203.1 30 487 +1990 4 13 6 16 DEBBY 57.5 355.3 138 482 +1986 1 23 0 26 ALBERTO 33.9 62.5 71 316 +2001 8 25 6 12 KIRK 35.0 249.1 38 154 +2001 9 16 18 9 NADINE 11.3 53.0 48 448 +2001 5 6 12 3 ISAAC 53.5 103.5 21 674 +1969 7 16 12 23 SANDY 13.7 19.6 52 765 +1999 1 3 6 17 ALBERTO 27.1 24.4 26 87 +1972 12 28 12 7 ERNESTO 46.9 3.1 47 609 +1996 12 10 6 24 SANDY 69.8 255.1 38 29 +1967 1 25 12 8 RAFAEL 23.5 239.5 118 483 +1972 9 1 0 4 VALERIE 21.8 83.8 137 200 +1963 9 15 6 10 DEBBY 67.4 321.8 126 356 +1984 6 15 12 3 ERNESTO 48.1 97.8 12 333 +1997 7 10 6 26 LESLIE 22.1 268.1 43 827 +1982 1 15 12 12 ALBERTO 48.0 124.2 92 146 +1956 12 2 0 5 KIRK 66.0 129.0 95 25 +1982 5 15 18 17 JOYCE 39.1 135.3 48 604 +1970 3 17 18 8 JOYCE 26.4 268.5 164 753 +1987 12 6 18 2 FLORENCE 47.8 137.0 62 443 +1955 4 9 6 28 GORDON 51.5 106.4 120 490 +1960 3 9 0 6 SANDY 24.2 287.9 162 466 +1964 10 28 6 17 LESLIE 61.6 199.6 75 662 +1954 4 2 0 22 KIRK 10.2 205.1 133 286 +2001 11 28 6 9 FLORENCE 58.7 50.2 100 44 +1991 10 5 6 11 SANDY 62.6 245.2 130 31 +1956 3 25 0 13 CHRIS 63.7 131.2 79 463 +1972 9 7 6 3 HELENE 8.3 325.6 160 573 +1977 11 6 12 16 MICHAEL 20.1 119.7 107 795 +1968 3 4 6 24 ERNESTO 61.9 72.8 120 899 +1954 5 25 18 15 OSCAR 59.0 313.8 140 460 +1970 11 12 18 4 RAFAEL 60.5 329.3 34 24 +2004 11 14 18 14 HELENE 61.6 79.5 87 633 +1988 3 1 12 21 RAFAEL 40.5 109.9 133 846 +1959 12 12 12 18 LESLIE 66.3 220.1 79 589 +1962 3 3 6 10 BERYL 50.3 221.0 21 446 +2002 3 19 0 25 HELENE 12.4 253.1 31 211 +1953 3 12 0 26 ISAAC 7.2 328.4 76 739 +2002 9 26 0 5 PATTY 61.6 169.8 107 300 +1990 1 26 6 16 MICHAEL 61.9 193.2 60 104 +1971 1 1 6 16 TONY 48.5 76.9 164 746 +1989 2 8 6 11 DEBBY 8.5 27.5 27 184 +1956 8 16 18 23 JOYCE 69.8 112.6 96 18 +1951 11 5 0 4 ISAAC 52.3 219.1 121 59 +1953 1 26 6 24 VALERIE 68.8 55.5 105 810 +1996 3 4 12 19 CHRIS 10.8 98.7 158 84 +1980 8 26 6 23 GORDON 15.7 179.3 100 568 +1990 5 21 12 18 SANDY 7.1 98.1 144 686 +1962 11 11 12 20 OSCAR 40.3 30.4 11 496 +1964 1 19 6 11 ISAAC 67.0 314.0 90 821 +1952 12 27 0 23 WILLIAM 12.3 213.5 60 138 +1971 9 18 18 8 GORDON 51.4 73.5 65 816 +1954 7 22 12 8 ALBERTO 43.8 281.4 14 597 +1980 4 10 6 21 RAFAEL 65.7 163.9 137 587 +1994 12 7 18 26 ISAAC 47.9 269.4 142 640 +1957 6 17 18 4 TONY 28.5 205.3 118 763 +1950 4 25 6 16 JOYCE 64.2 287.0 120 353 +2000 8 13 12 4 ISAAC 27.4 238.0 39 874 +1964 7 5 12 5 OSCAR 60.6 45.6 46 730 +1958 8 28 12 6 ISAAC 21.1 34.4 68 413 +1951 5 5 0 4 OSCAR 53.6 233.7 131 869 +1954 7 20 12 9 LESLIE 69.0 145.2 75 735 +1992 9 19 12 21 RAFAEL 46.5 32.9 30 19 +1962 4 23 18 23 KIRK 25.4 24.3 60 872 +1981 5 4 0 5 FLORENCE 60.2 122.9 27 304 +1968 2 14 6 14 PATTY 64.3 8.5 121 700 +1961 5 19 6 21 NADINE 60.6 45.8 144 173 +1951 8 10 6 6 FLORENCE 48.6 223.4 83 60 +1970 8 21 0 11 KIRK 36.9 353.9 36 495 +1962 11 8 6 4 BERYL 20.1 278.7 105 95 +2003 5 18 12 16 GORDON 20.7 134.1 20 466 +1956 11 14 0 21 VALERIE 25.0 168.3 71 279 +1974 6 9 0 22 HELENE 27.7 312.3 130 101 +1965 1 8 12 11 WILLIAM 24.7 56.1 87 407 +2001 9 8 12 12 CHRIS 51.3 150.5 14 743 +1995 7 28 12 4 NADINE 48.6 150.9 97 247 +1989 8 8 6 1 KIRK 67.5 234.7 131 679 +1978 8 10 0 10 GORDON 15.9 283.5 113 628 +1954 4 27 18 26 JOYCE 14.0 5.8 132 65 +1992 3 17 6 3 ALBERTO 20.7 7.1 68 891 +1996 8 9 6 15 ALBERTO 44.0 153.0 24 456 +1971 4 22 12 17 TONY 63.1 89.2 44 764 +2003 12 25 0 25 FLORENCE 29.3 97.3 164 721 +1992 1 3 12 1 NADINE 42.5 78.1 85 498 +1997 1 5 0 18 ISAAC 12.6 35.1 38 94 +1986 3 12 0 19 TONY 22.9 294.4 139 86 +1979 8 21 6 8 CHRIS 29.4 227.2 86 814 +1989 8 15 18 28 CHRIS 61.4 38.4 121 250 +1980 6 16 0 6 KIRK 27.9 80.3 23 65 +1977 6 16 6 21 DEBBY 63.7 23.5 103 444 +1961 4 17 18 25 ERNESTO 64.4 230.1 131 451 +1993 5 1 18 16 BERYL 37.0 258.8 51 159 +1960 6 14 18 4 MICHAEL 70.0 222.0 112 387 +1951 8 2 12 5 ISAAC 13.8 321.9 144 483 +1950 9 11 12 9 DEBBY 33.9 270.9 104 219 +1968 2 3 6 6 CHRIS 11.3 347.4 31 424 +1960 11 14 18 1 KIRK 17.1 45.5 146 242 +1968 3 21 6 6 KIRK 43.7 14.0 146 692 +1991 5 10 12 10 ERNESTO 43.3 333.8 103 399 +1997 4 8 6 5 WILLIAM 8.6 243.4 30 300 +1993 7 24 6 1 BERYL 15.1 235.5 131 52 +1984 8 14 18 11 GORDON 43.4 85.0 61 848 +1978 8 14 6 12 KIRK 8.8 322.9 40 417 +1977 4 13 12 2 RAFAEL 23.5 322.8 32 510 +1973 9 13 6 7 ISAAC 43.2 274.7 110 273 +1994 12 11 12 1 TONY 43.8 11.5 41 637 +1961 5 3 0 9 DEBBY 23.1 131.0 80 849 +1970 1 11 0 8 ALBERTO 42.4 31.1 106 399 +2002 11 28 0 18 HELENE 64.3 347.5 119 581 +1964 4 11 12 14 HELENE 59.4 27.2 74 93 +2002 5 19 6 25 ALBERTO 8.5 189.9 110 60 +1973 2 22 12 6 BERYL 56.4 229.8 32 10 +1997 7 5 6 9 OSCAR 36.1 329.4 31 383 +2004 10 12 0 18 RAFAEL 40.3 163.5 42 606 +1998 1 27 0 24 OSCAR 45.5 259.2 88 444 +1954 10 27 0 22 ERNESTO 20.0 103.6 76 240 +1973 3 19 0 28 DEBBY 42.7 47.0 146 286 +1957 1 18 12 8 LESLIE 34.6 332.4 48 383 +2001 5 3 12 24 MICHAEL 67.4 323.8 57 886 +1972 11 2 0 28 GORDON 36.2 150.3 87 431 +1998 7 8 12 23 WILLIAM 36.1 345.4 144 480 +1950 12 16 18 21 LESLIE 51.7 192.8 78 271 +1951 8 6 12 24 KIRK 32.3 105.4 27 310 +1974 7 12 12 19 TONY 41.7 272.1 75 839 +1988 7 17 18 10 HELENE 26.5 25.0 77 523 +1975 11 23 6 27 CHRIS 55.5 264.7 162 164 +1971 1 3 6 26 ALBERTO 46.0 269.8 82 742 +1953 12 18 6 13 ERNESTO 33.5 218.0 108 191 +1959 4 3 6 19 JOYCE 61.2 104.8 107 189 +1996 10 23 18 26 HELENE 21.3 310.1 78 518 +1994 6 13 12 1 GORDON 64.9 217.3 154 197 +1952 2 10 0 17 NADINE 39.0 34.3 15 482 +1994 5 25 6 12 BERYL 41.4 343.6 80 366 +1992 10 14 18 6 BERYL 55.0 245.5 12 224 +1987 8 7 6 4 CHRIS 26.2 124.9 45 580 +1957 4 22 12 5 LESLIE 64.5 127.6 41 464 +1954 5 15 18 23 PATTY 10.9 170.7 135 597 +1959 5 12 12 1 OSCAR 45.1 34.8 126 642 +1975 12 8 0 9 OSCAR 49.2 111.6 156 478 +1962 7 26 6 8 NADINE 55.6 51.2 60 551 +1984 7 1 18 3 OSCAR 14.8 290.4 44 399 +1952 10 24 18 1 DEBBY 31.7 326.2 51 231 +1997 7 6 0 21 ALBERTO 18.2 315.7 99 178 +1972 12 23 12 9 PATTY 45.1 204.1 96 716 +1962 2 20 12 5 PATTY 13.7 314.6 125 278 +1972 3 25 18 23 ERNESTO 18.6 344.2 19 740 +1976 7 25 12 16 NADINE 43.9 166.4 26 876 +1996 3 3 18 6 NADINE 26.1 230.9 60 12 +1975 3 24 18 26 KIRK 52.9 176.9 47 9 +1985 5 8 18 7 PATTY 42.9 245.5 55 750 +2003 2 8 18 12 BERYL 12.0 171.8 133 355 +1962 9 11 6 12 VALERIE 49.4 238.7 74 690 +1973 5 2 12 2 ISAAC 59.8 65.7 115 892 +1954 7 7 0 22 ISAAC 50.3 303.2 75 310 +2001 2 1 6 24 ERNESTO 44.2 120.4 126 322 +1988 3 14 18 10 JOYCE 19.5 338.2 161 131 +1961 7 13 6 13 ALBERTO 54.9 351.4 126 78 +1996 7 11 0 4 PATTY 41.8 140.1 163 7 +2003 8 19 6 2 PATTY 44.3 70.1 71 512 +1954 4 27 6 20 GORDON 16.3 9.3 145 339 +1981 3 1 18 14 OSCAR 8.5 17.1 146 149 +1991 11 21 18 15 RAFAEL 37.0 215.3 14 598 +1964 7 6 12 16 RAFAEL 21.5 13.6 143 776 +1971 8 26 6 1 SANDY 25.6 108.1 104 715 +1968 7 21 6 5 DEBBY 63.6 14.2 128 264 +1972 4 10 6 14 SANDY 7.1 313.0 26 756 +1978 2 12 12 24 OSCAR 23.8 52.7 142 5 +1986 12 21 0 1 DEBBY 42.7 34.8 92 679 +1951 7 6 18 18 SANDY 56.1 78.9 158 818 +1976 3 28 6 16 ISAAC 49.0 37.5 65 722 +1955 11 14 18 16 OSCAR 34.4 122.6 50 161 +1993 1 25 18 8 SANDY 51.4 299.8 105 714 +1964 9 26 6 16 OSCAR 12.3 2.6 25 33 +1964 8 28 6 8 DEBBY 69.7 39.3 64 808 +1967 6 18 0 3 LESLIE 36.1 173.5 153 99 +1976 6 13 6 26 CHRIS 11.1 149.8 77 746 +1972 8 11 0 24 SANDY 36.4 121.2 49 153 +1995 12 19 0 4 OSCAR 56.4 148.4 89 184 +1957 12 28 18 7 GORDON 25.2 151.7 156 342 +1991 6 27 6 16 CHRIS 45.6 200.5 128 505 +1954 3 1 0 14 ISAAC 45.9 208.4 45 186 +1998 10 24 6 10 WILLIAM 23.7 296.2 39 649 +1983 11 5 12 20 KIRK 28.8 232.8 121 744 +1968 5 22 6 24 PATTY 30.6 276.1 140 156 +1975 4 8 12 1 WILLIAM 45.0 62.6 153 585 +1960 11 23 12 19 CHRIS 51.8 353.8 58 742 +1977 9 25 12 9 MICHAEL 59.3 125.8 93 891 +1965 6 1 0 13 NADINE 58.9 146.1 58 630 +1989 9 2 6 12 MICHAEL 13.0 230.2 129 314 +1951 1 23 18 11 ALBERTO 63.3 323.9 130 874 +1986 3 3 12 27 LESLIE 16.8 44.7 161 447 +1985 7 19 12 4 DEBBY 51.0 323.5 123 409 +1998 11 22 6 18 WILLIAM 39.4 207.0 74 671 +1976 2 17 6 16 FLORENCE 60.9 3.2 54 272 +1994 11 16 6 19 ISAAC 41.5 218.3 88 205 +1994 12 5 18 1 FLORENCE 40.3 317.0 130 660 +1977 1 24 6 15 KIRK 23.5 95.6 42 49 +1982 2 12 0 18 DEBBY 39.3 252.4 38 430 +1975 2 5 18 12 NADINE 67.1 18.9 74 370 +1977 7 20 0 12 MICHAEL 56.8 193.0 103 303 +1987 5 16 12 19 RAFAEL 54.8 337.1 71 846 +1950 12 3 6 28 CHRIS 38.3 49.5 160 857 +1997 6 21 6 23 LESLIE 12.1 135.3 52 481 +1956 9 6 12 6 SANDY 10.1 188.8 58 11 +1997 4 12 18 2 PATTY 19.7 325.2 37 173 +1967 12 4 18 21 JOYCE 49.2 96.3 88 853 +1987 3 5 18 10 HELENE 48.0 78.5 158 556 +1973 4 14 0 13 CHRIS 60.6 159.3 93 711 +1959 12 27 0 10 GORDON 9.1 104.7 95 631 +1991 11 20 0 25 LESLIE 68.4 69.8 131 725 +1959 11 2 18 24 OSCAR 49.9 342.8 137 519 +1990 7 16 12 21 MICHAEL 62.4 335.7 21 418 +1963 7 16 0 24 DEBBY 51.5 128.2 54 2 +1996 10 19 0 7 ERNESTO 28.2 59.5 128 25 +1966 6 28 0 15 GORDON 7.9 189.2 158 470 +2001 3 7 18 9 KIRK 60.5 278.9 119 436 +2004 12 7 18 19 LESLIE 21.3 58.9 70 482 +1978 8 19 6 13 LESLIE 57.6 335.9 162 105 +1979 7 13 6 2 BERYL 13.1 260.4 153 824 +1974 4 14 12 24 OSCAR 49.0 293.0 122 477 +1958 10 3 18 7 FLORENCE 18.3 339.7 113 830 +1995 4 27 6 12 NADINE 13.9 173.2 74 154 +1965 6 28 18 25 FLORENCE 60.6 303.4 124 664 +1980 10 22 18 3 ISAAC 30.1 90.4 110 778 +1965 10 21 0 25 OSCAR 19.2 227.7 29 789 +1952 8 20 18 23 TONY 55.7 272.5 66 580 +1959 11 6 12 3 NADINE 19.7 30.0 32 102 +2003 2 9 12 16 PATTY 12.1 227.1 18 260 +1950 9 26 6 5 GORDON 23.7 200.8 65 778 +1971 7 22 6 3 HELENE 56.1 242.2 159 429 +1995 5 15 18 16 JOYCE 62.5 242.6 71 859 +1998 6 28 12 25 PATTY 40.6 241.6 50 553 +1970 9 20 0 20 WILLIAM 43.9 28.8 92 723 +1983 5 22 0 18 ALBERTO 37.8 117.6 54 579 +1984 2 12 12 20 ISAAC 58.7 64.2 37 588 +1968 1 18 18 20 FLORENCE 22.9 113.2 105 232 +1982 10 4 0 13 TONY 12.0 289.3 93 605 +2003 6 16 0 21 VALERIE 7.0 145.6 110 77 +1957 9 19 18 1 ALBERTO 55.8 328.1 52 10 +2001 1 22 18 20 VALERIE 66.6 229.6 31 57 +1978 4 2 12 9 RAFAEL 7.7 258.4 34 412 +1971 11 2 0 9 HELENE 8.0 260.4 126 702 +1981 11 10 0 23 LESLIE 9.8 123.3 50 147 +1981 2 25 12 4 MICHAEL 58.5 268.4 84 442 +2001 1 18 0 13 MICHAEL 64.0 51.3 140 443 +1977 3 3 12 22 ERNESTO 32.8 247.6 29 16 +1959 6 10 18 13 SANDY 42.0 102.3 142 784 +1963 5 1 18 12 FLORENCE 61.9 155.6 138 869 +1983 6 10 12 4 DEBBY 8.9 324.6 43 525 +1973 9 12 18 16 NADINE 47.9 177.2 120 352 +1986 3 7 0 16 ISAAC 58.7 27.9 133 94 +2000 1 19 12 8 HELENE 38.6 96.7 86 549 +1956 10 10 0 10 PATTY 24.2 299.3 37 26 +1965 1 19 0 19 CHRIS 29.7 106.1 51 327 +1993 11 11 0 2 VALERIE 69.6 344.4 43 221 +1966 10 20 18 25 OSCAR 27.6 234.7 76 176 +1975 8 14 18 9 DEBBY 67.4 178.3 152 447 +1990 9 9 0 24 SANDY 26.6 74.9 74 598 +1989 8 8 6 23 LESLIE 22.7 316.7 55 798 +1955 12 26 6 20 ALBERTO 45.2 122.9 114 440 +1976 3 24 0 4 ERNESTO 54.0 175.2 55 592 +1985 7 2 0 2 ERNESTO 18.5 37.8 26 120 +1989 12 9 0 21 SANDY 27.3 334.7 31 893 +1963 6 17 18 8 OSCAR 26.7 159.8 75 41 +1965 12 6 18 24 NADINE 53.2 194.2 51 590 +1991 3 5 12 23 ISAAC 15.8 100.0 29 188 +1988 10 18 0 7 SANDY 19.9 75.8 17 784 +1956 5 4 6 17 SANDY 54.9 196.0 12 138 +1952 2 26 18 26 PATTY 18.8 83.6 68 751 +1982 5 25 0 20 VALERIE 29.1 354.7 122 96 +1997 7 25 6 27 ERNESTO 63.6 91.9 115 817 +1961 5 28 12 14 TONY 62.7 279.2 22 714 +1960 9 1 6 16 PATTY 32.1 94.7 77 744 +2004 5 11 18 26 BERYL 65.3 37.0 34 512 +1962 10 5 6 27 KIRK 29.4 283.2 73 203 +1991 8 20 6 13 OSCAR 50.8 77.4 91 690 +1980 4 17 12 15 OSCAR 31.4 26.4 140 443 +2000 10 24 12 18 RAFAEL 41.8 241.4 123 448 +1982 5 13 18 1 LESLIE 33.9 42.1 110 80 +1962 1 14 6 12 HELENE 56.5 343.9 56 660 +2001 2 18 18 14 CHRIS 35.7 333.1 106 511 +1992 4 3 0 2 KIRK 12.5 286.0 27 671 +1961 9 22 0 28 KIRK 18.8 246.8 129 360 +1995 3 4 18 23 VALERIE 48.3 84.5 59 565 +1982 7 24 0 9 BERYL 33.2 267.5 52 338 +1971 6 27 6 19 OSCAR 68.9 145.1 138 1 +1975 2 11 6 22 ERNESTO 56.5 13.7 41 293 +1958 2 18 0 11 ALBERTO 63.9 357.1 148 605 +2004 3 5 6 3 ERNESTO 18.8 258.5 117 609 +2004 1 20 6 15 KIRK 54.6 31.0 72 371 +1962 8 25 0 17 BERYL 24.1 54.0 104 266 +1964 12 11 6 17 SANDY 35.2 139.8 111 853 +1951 12 18 0 15 PATTY 55.8 309.9 42 394 +1962 3 5 6 14 WILLIAM 59.8 237.6 94 35 +1976 8 8 18 2 KIRK 19.7 229.9 13 462 +1955 4 19 12 11 BERYL 35.6 145.5 112 238 +2002 1 13 0 26 KIRK 65.9 109.6 99 624 +1989 3 21 18 26 TONY 67.0 70.9 73 237 +1960 8 1 18 17 JOYCE 34.1 133.5 150 542 +1979 10 13 6 14 DEBBY 48.3 134.5 16 629 +1987 11 4 0 18 TONY 50.8 292.9 77 18 +2002 12 4 18 6 WILLIAM 61.3 332.4 136 599 +1954 3 9 6 21 CHRIS 50.3 88.8 93 824 +1987 8 16 12 1 VALERIE 40.3 25.4 135 386 +1977 9 6 6 8 ISAAC 52.6 90.4 59 13 +1979 12 4 18 1 FLORENCE 62.0 328.9 64 268 +1983 11 24 12 14 DEBBY 21.4 332.0 128 301 +2002 8 22 6 16 SANDY 57.1 278.2 135 721 +1999 12 2 12 15 GORDON 8.6 274.5 43 104 +1991 8 6 12 26 JOYCE 20.6 344.1 89 630 +1971 6 11 18 19 DEBBY 55.4 138.1 56 380 +1961 5 5 0 3 FLORENCE 67.8 161.5 56 754 +2000 10 21 18 23 OSCAR 43.3 222.3 54 646 +1959 4 19 0 10 KIRK 17.5 147.9 143 851 +1989 7 27 18 20 FLORENCE 12.8 312.3 130 482 +1979 9 15 12 24 ISAAC 53.5 85.8 117 558 +1957 7 10 6 11 ISAAC 49.3 64.4 156 501 +1967 3 10 6 10 SANDY 56.5 203.0 97 20 +2001 7 6 6 7 HELENE 12.8 259.0 143 55 +1982 4 5 12 27 NADINE 55.6 61.8 134 332 +1975 5 16 12 11 LESLIE 32.0 37.9 129 417 +2003 5 24 0 22 MICHAEL 51.3 84.9 62 484 +1982 1 8 0 22 RAFAEL 64.6 189.4 120 763 +1999 9 23 6 1 VALERIE 45.7 142.5 127 579 +1997 8 1 12 12 ALBERTO 54.1 340.7 80 170 +1956 10 26 18 11 BERYL 60.7 144.5 133 212 +2004 8 9 6 26 JOYCE 58.1 308.7 39 117 +1986 3 22 6 5 ALBERTO 64.1 47.9 125 797 +2001 2 14 0 23 HELENE 43.2 136.4 129 249 +1993 11 24 18 8 RAFAEL 20.7 295.8 119 134 +1969 2 10 18 7 KIRK 9.0 309.2 142 591 +2000 1 26 0 26 FLORENCE 54.3 32.4 130 385 +1992 2 10 6 24 CHRIS 55.9 189.0 49 641 +1973 8 9 0 26 ERNESTO 34.2 61.2 128 844 +1987 7 22 12 8 FLORENCE 21.6 99.8 100 770 +1981 7 6 12 23 BERYL 54.1 7.9 131 592 +1998 3 26 12 4 RAFAEL 33.7 39.6 41 752 +2003 11 3 0 3 CHRIS 67.6 340.1 58 855 +1995 9 14 12 17 ALBERTO 21.9 293.0 139 89 +1960 4 18 18 19 ALBERTO 16.2 48.3 83 284 +1983 12 23 0 7 ISAAC 16.1 330.5 41 810 +1969 7 6 12 23 PATTY 18.9 105.1 89 795 +1963 12 28 18 6 ISAAC 8.0 79.6 57 109 +1995 6 12 6 19 BERYL 27.7 318.6 78 398 +1973 8 20 18 13 DEBBY 60.4 290.7 35 820 +1954 5 18 6 22 HELENE 59.4 303.5 157 791 +1955 11 10 6 11 TONY 69.2 252.8 79 797 +1958 4 7 0 23 FLORENCE 47.3 289.8 105 592 +1963 10 14 12 16 BERYL 54.8 276.5 130 564 +1996 5 26 18 11 ERNESTO 12.4 344.0 157 219 +2003 9 21 6 26 GORDON 38.5 295.8 109 538 +1985 10 2 6 12 BERYL 69.8 130.6 93 52 +1975 7 9 12 26 GORDON 49.5 172.3 33 678 +1989 7 13 18 10 LESLIE 30.2 188.6 89 642 +1955 7 13 12 2 ISAAC 13.1 239.2 98 106 +1957 12 15 0 10 ERNESTO 17.6 312.6 66 849 +1976 6 6 12 12 MICHAEL 22.6 349.1 134 710 +1958 2 22 0 6 PATTY 38.0 9.4 139 566 +1964 5 24 0 4 ISAAC 14.3 44.4 151 251 +2003 11 24 12 20 FLORENCE 47.6 191.9 15 768 +1963 11 2 6 28 BERYL 7.3 75.2 100 98 +1997 1 6 6 20 KIRK 38.5 18.2 121 67 +1968 9 15 6 3 WILLIAM 10.7 115.5 35 310 +1975 3 13 6 13 TONY 43.5 123.8 56 78 +1971 3 19 18 23 SANDY 37.4 57.3 57 151 +1972 1 14 6 20 TONY 64.4 182.2 16 770 +1991 8 8 6 24 DEBBY 53.8 266.7 142 698 +2002 2 24 6 19 TONY 25.9 187.3 56 64 +1952 1 27 6 16 OSCAR 15.7 277.5 55 640 +1985 4 8 0 14 LESLIE 12.6 178.9 65 860 +1995 7 21 0 5 CHRIS 23.6 337.4 88 524 +1983 4 19 12 23 WILLIAM 54.4 189.1 72 718 +1953 3 3 0 25 ALBERTO 53.6 13.0 142 650 +1971 12 25 12 7 ISAAC 35.0 105.3 114 177 +1973 1 20 0 6 MICHAEL 15.9 24.0 50 492 +1993 2 20 18 10 MICHAEL 30.6 194.9 133 432 +1960 1 1 0 3 FLORENCE 12.9 125.3 126 835 +1990 9 4 0 22 GORDON 35.8 124.7 36 506 +1969 3 6 0 5 TONY 68.4 227.0 28 429 +1954 12 11 0 5 MICHAEL 32.9 201.2 60 422 +1953 1 14 12 13 TONY 58.1 19.2 88 513 +1953 1 23 12 14 OSCAR 32.5 46.8 45 460 +1978 4 21 18 14 MICHAEL 45.6 43.1 45 301 +1987 1 1 12 22 WILLIAM 65.5 168.0 143 502 +1986 12 19 12 10 ISAAC 54.6 77.3 112 354 +1969 6 13 6 9 GORDON 11.0 165.9 75 807 +1985 4 21 18 2 BERYL 58.9 292.6 117 279 +1969 2 12 12 10 JOYCE 21.9 243.4 164 887 +1957 1 13 18 12 RAFAEL 65.4 123.0 14 97 +2003 12 14 0 24 PATTY 54.6 131.2 82 194 +1981 4 28 0 17 ALBERTO 12.3 119.0 52 265 +1978 9 1 0 28 TONY 24.1 193.8 135 232 +1995 10 26 0 21 JOYCE 65.0 5.2 17 440 +1980 5 19 12 1 BERYL 49.4 201.3 103 84 +1979 10 18 18 25 TONY 23.5 262.1 51 328 +1988 4 11 0 18 VALERIE 69.8 334.2 109 632 +1969 12 21 0 19 FLORENCE 14.4 309.3 48 218 +1984 7 22 18 12 LESLIE 21.0 204.4 80 666 +1960 4 28 6 15 HELENE 14.4 34.8 96 32 +1951 2 25 18 3 HELENE 45.2 104.7 28 101 +1999 10 25 0 4 SANDY 33.3 349.0 72 721 +1992 12 27 18 18 ISAAC 35.7 346.8 75 154 +1978 3 21 6 22 FLORENCE 11.5 300.9 53 485 +1952 5 18 12 11 ISAAC 50.6 203.3 98 300 +1961 6 19 12 18 RAFAEL 40.9 294.3 135 363 +1990 6 17 0 9 GORDON 63.5 262.9 28 364 +1950 6 12 6 9 SANDY 21.1 268.9 118 40 +1961 6 18 12 27 HELENE 59.3 310.3 116 768 +1976 2 12 12 21 ALBERTO 12.4 172.8 110 626 +1957 9 13 0 16 LESLIE 35.6 234.9 41 61 +2002 7 6 6 5 KIRK 53.1 119.6 55 755 +1959 9 22 6 14 NADINE 50.6 286.8 83 132 +1961 5 12 18 7 NADINE 61.2 268.9 106 815 +1979 11 4 18 9 JOYCE 58.1 330.2 31 632 +1956 4 28 6 24 PATTY 22.5 356.7 123 486 +1986 9 22 18 19 WILLIAM 52.5 160.8 144 784 +1978 5 3 12 22 ALBERTO 31.7 35.0 28 84 +1999 6 17 6 2 VALERIE 12.1 199.1 48 869 +1983 8 8 6 13 ALBERTO 35.2 285.9 74 438 +2000 9 5 18 6 WILLIAM 47.7 141.6 39 554 +1988 7 25 12 23 ISAAC 42.9 352.7 10 793 +2003 4 10 6 24 JOYCE 22.5 13.9 160 0 +1979 8 20 6 27 VALERIE 14.4 173.7 39 251 +1989 7 20 12 18 GORDON 9.6 4.7 64 475 +1980 11 5 12 24 NADINE 28.9 355.6 44 377 +1975 10 6 6 10 VALERIE 44.6 26.1 107 811 +1963 6 21 6 11 OSCAR 17.9 65.2 84 64 +2000 4 4 18 22 CHRIS 21.5 263.4 53 811 +1962 1 3 0 13 RAFAEL 50.8 276.6 116 676 +1966 5 22 12 9 TONY 49.4 274.8 70 661 +1966 6 12 0 8 RAFAEL 45.8 350.9 30 662 +1989 1 5 0 28 JOYCE 11.1 60.8 145 572 +1962 10 6 18 28 SANDY 21.6 171.7 90 302 +1986 6 28 0 3 GORDON 44.1 304.2 117 247 +1991 1 4 18 7 MICHAEL 56.5 322.5 154 807 +1997 2 10 12 2 MICHAEL 33.2 114.8 18 127 +1964 11 12 18 18 CHRIS 40.9 168.2 38 18 +1950 3 12 0 4 LESLIE 32.8 193.2 56 695 +2003 5 7 6 8 JOYCE 56.3 14.1 149 569 +1991 12 10 0 6 GORDON 64.1 158.8 49 706 +1952 5 21 18 22 ALBERTO 13.1 263.6 94 233 +1966 8 20 18 7 WILLIAM 42.2 206.3 148 409 +1982 9 23 18 19 NADINE 21.4 76.6 41 41 +1976 3 8 0 4 RAFAEL 35.4 11.4 122 592 +1987 2 19 12 23 VALERIE 55.6 134.5 27 123 +1953 1 24 12 11 ALBERTO 68.4 137.0 123 841 +1952 4 17 18 13 BERYL 55.3 305.0 134 805 +2001 2 6 6 24 BERYL 61.0 226.7 61 51 +1962 4 1 6 11 DEBBY 18.8 170.9 122 74 +1976 6 2 18 3 GORDON 51.5 321.9 45 298 +1977 2 17 12 2 JOYCE 9.8 328.2 111 52 +1997 2 25 12 21 MICHAEL 16.3 292.3 73 398 +2004 2 19 18 12 BERYL 14.9 348.1 152 38 +1961 10 28 18 28 LESLIE 50.3 223.7 83 487 +1982 12 17 12 6 VALERIE 10.2 60.8 52 362 +1977 7 16 12 20 WILLIAM 38.9 165.4 162 204 +2003 9 17 0 25 VALERIE 61.6 286.8 130 116 +1974 3 26 18 6 CHRIS 25.8 12.5 162 671 +1993 11 21 6 26 TONY 7.4 324.4 69 124 +1988 3 27 0 3 CHRIS 68.7 231.4 152 338 +1957 9 22 18 18 SANDY 61.6 109.4 119 590 +1950 10 18 18 28 JOYCE 49.8 247.6 142 611 +1983 2 3 12 27 LESLIE 59.8 251.7 57 782 +1988 5 16 12 20 MICHAEL 42.4 173.1 74 375 +1990 5 25 18 19 FLORENCE 30.7 20.9 111 532 +1990 7 11 18 6 ERNESTO 64.8 294.6 163 188 +1996 3 23 12 5 CHRIS 11.0 126.8 103 598 +1995 8 6 0 21 GORDON 9.6 41.3 92 558 +1987 7 14 0 19 RAFAEL 16.8 82.5 27 84 +1989 10 18 18 12 TONY 62.9 203.3 122 413 +1958 8 28 18 23 ALBERTO 53.5 288.3 29 804 +2002 7 7 6 25 HELENE 16.8 231.9 23 730 +1952 8 9 6 3 RAFAEL 69.0 235.1 34 707 +1967 3 18 18 26 BERYL 35.6 73.0 128 226 +1986 9 18 18 27 KIRK 31.0 160.7 128 857 +1992 4 18 6 9 JOYCE 67.0 245.0 117 76 +1962 10 27 18 28 FLORENCE 34.7 303.2 28 616 +1962 6 16 18 24 BERYL 27.2 214.3 149 267 +1973 1 26 18 3 GORDON 30.5 90.5 98 651 +1996 5 4 6 15 VALERIE 52.3 5.8 15 398 +2002 12 26 12 18 VALERIE 37.8 211.9 150 36 +1966 8 13 0 26 ISAAC 66.2 357.8 146 617 +1981 3 13 0 27 OSCAR 68.8 153.4 144 462 +1972 10 4 6 4 OSCAR 45.2 261.4 47 402 +1964 9 24 18 4 CHRIS 57.8 91.4 148 285 +1978 7 12 0 14 GORDON 67.4 280.2 71 351 +1968 9 8 12 18 ISAAC 62.3 43.4 96 358 +1972 7 3 18 27 VALERIE 36.9 250.2 118 401 +1957 6 23 0 24 BERYL 26.3 44.4 144 222 +1982 3 5 0 2 KIRK 15.3 43.4 113 546 +1971 6 28 12 2 NADINE 42.7 264.3 64 369 +1977 1 22 12 15 OSCAR 56.3 116.9 104 58 +1958 12 20 6 4 BERYL 43.1 51.6 156 58 +1965 9 19 18 10 PATTY 48.5 185.3 38 817 +1953 7 14 0 20 OSCAR 14.0 339.2 89 760 +1960 3 7 18 14 CHRIS 45.3 149.4 60 488 +2003 2 17 6 15 JOYCE 23.6 136.4 147 135 +1992 2 21 18 28 ALBERTO 34.7 249.7 119 270 +1997 10 4 0 14 JOYCE 67.1 69.4 17 311 +2003 5 3 18 25 LESLIE 27.1 330.1 126 58 +1962 3 12 18 14 TONY 32.3 353.3 106 694 +1991 1 15 12 10 RAFAEL 35.4 123.2 112 527 +1969 11 7 18 11 ISAAC 11.1 303.1 54 440 +1979 6 4 12 19 TONY 44.6 340.5 34 291 +2001 8 28 0 19 WILLIAM 58.2 7.7 17 843 +1971 12 24 18 4 DEBBY 12.1 209.7 107 219 +1988 11 16 12 10 WILLIAM 17.1 313.6 27 418 +2003 12 14 0 18 GORDON 65.2 226.6 81 173 +1976 8 10 18 15 NADINE 21.9 346.5 147 723 +1962 3 6 6 12 CHRIS 55.8 307.6 32 445 +2003 10 27 6 20 OSCAR 24.5 171.5 90 203 +1985 8 27 12 13 DEBBY 29.3 241.7 110 364 +1995 4 23 12 25 HELENE 58.8 307.7 69 405 +1973 5 15 6 21 WILLIAM 31.7 156.9 134 450 +1986 8 26 18 3 CHRIS 58.2 138.5 114 600 +2000 12 5 0 13 GORDON 59.8 293.7 51 277 +2003 2 27 0 1 DEBBY 38.1 256.0 17 350 +1973 1 4 6 7 OSCAR 68.4 7.7 75 142 +2004 10 7 0 26 DEBBY 59.0 98.9 55 652 +1957 8 3 0 4 VALERIE 38.3 327.0 39 760 +1951 8 2 6 6 VALERIE 26.9 211.0 69 492 +1966 11 20 0 22 CHRIS 13.0 306.8 74 565 +1961 4 26 0 21 MICHAEL 15.8 194.1 30 608 +1982 9 17 12 18 LESLIE 22.1 159.6 17 116 +1989 7 27 18 18 LESLIE 42.0 275.7 144 159 +2003 12 16 0 2 LESLIE 25.2 256.8 118 485 +1983 1 27 0 26 CHRIS 66.4 152.4 99 848 +1993 4 20 6 2 LESLIE 69.6 309.3 129 10 +1983 8 7 6 20 CHRIS 55.4 350.2 103 410 +1998 11 17 0 10 WILLIAM 29.2 221.6 114 691 +1984 7 27 12 16 JOYCE 68.7 84.4 11 39 +1993 1 1 0 7 KIRK 33.9 302.8 126 102 +1973 12 7 18 23 RAFAEL 63.6 352.6 95 125 +1987 4 26 6 7 BERYL 11.5 25.6 56 845 +1955 2 13 18 17 ALBERTO 63.8 231.7 138 2 +1957 12 26 6 24 KIRK 35.8 222.6 114 321 +1988 10 8 0 27 DEBBY 10.2 346.2 164 356 +1998 3 19 6 23 VALERIE 41.3 126.2 74 217 +1954 1 10 18 12 OSCAR 26.4 188.5 122 782 +1975 11 5 12 21 ALBERTO 62.3 273.8 146 525 +1963 8 23 18 9 VALERIE 40.0 126.0 113 575 +1990 1 9 0 24 ERNESTO 18.4 269.7 65 252 +1982 11 3 18 4 CHRIS 36.5 58.7 33 578 +1997 4 12 0 10 HELENE 37.0 133.8 159 439 +1996 10 1 0 9 CHRIS 30.1 126.7 102 813 +1991 5 1 18 13 OSCAR 35.3 224.6 137 775 +1958 9 17 0 17 FLORENCE 25.5 45.9 36 771 +1980 11 12 12 18 BERYL 59.2 135.1 18 143 +1973 9 4 0 27 ALBERTO 47.4 126.5 111 329 +1969 12 15 12 24 KIRK 16.8 149.3 20 788 +1958 1 8 18 16 PATTY 49.9 324.5 111 784 +1978 3 20 18 3 RAFAEL 31.7 314.7 100 305 +1967 5 5 12 18 KIRK 22.4 293.8 65 764 +1983 8 11 12 3 BERYL 21.2 121.5 160 657 +1957 12 6 18 27 ISAAC 15.1 0.5 49 297 +1977 6 3 12 20 OSCAR 10.6 340.9 161 92 +1970 10 13 6 20 ISAAC 67.4 309.8 40 373 +1963 6 7 0 10 PATTY 43.9 119.7 86 854 +1966 1 23 18 7 ISAAC 14.6 165.8 89 488 +1986 5 26 18 21 CHRIS 43.1 107.8 26 296 +1973 2 16 0 25 HELENE 55.6 159.8 133 375 +1973 6 25 6 22 GORDON 38.1 198.7 65 783 +1960 2 28 0 14 ISAAC 48.4 69.9 21 62 +1977 1 5 18 18 NADINE 45.3 306.0 37 891 +1985 2 9 18 17 VALERIE 62.7 2.1 44 195 +1979 4 2 18 9 BERYL 18.7 182.4 126 213 +1978 8 3 6 14 KIRK 60.9 284.1 28 627 +1952 8 10 0 17 OSCAR 30.2 201.8 57 855 +1969 3 9 6 24 ALBERTO 54.8 27.0 44 717 +1958 12 24 0 25 ALBERTO 60.4 347.9 82 864 +2001 3 11 18 17 HELENE 33.5 203.1 126 396 +1958 5 14 18 21 TONY 11.4 265.4 54 75 +1953 3 6 0 8 KIRK 63.1 134.9 137 534 +1977 1 12 12 7 MICHAEL 64.9 245.3 66 493 +1995 3 25 18 28 WILLIAM 63.9 171.7 55 20 +1996 2 8 0 12 LESLIE 37.5 271.0 43 448 +1979 11 23 18 27 ALBERTO 47.3 184.3 73 321 +1984 12 18 6 19 MICHAEL 44.7 160.3 157 122 +1979 12 4 0 22 HELENE 8.1 258.5 51 554 +1976 9 9 0 10 ALBERTO 21.5 94.5 63 450 +1965 9 4 12 11 ISAAC 17.2 49.4 70 724 +1993 11 1 12 9 ALBERTO 53.1 239.7 88 180 +1960 12 6 18 18 OSCAR 8.4 234.1 112 42 +1981 4 4 0 11 JOYCE 11.8 310.3 10 391 +2003 11 18 12 12 BERYL 45.1 335.4 97 681 +2000 11 7 18 27 ERNESTO 54.4 12.5 26 474 +1981 8 26 18 9 MICHAEL 57.8 129.0 16 752 +2004 1 26 18 13 GORDON 36.5 160.4 62 758 +2003 4 2 18 16 TONY 56.4 20.3 75 300 +1995 1 20 12 1 FLORENCE 13.3 132.2 143 42 +1989 7 18 12 9 OSCAR 63.5 0.9 156 721 +1951 8 21 12 11 KIRK 23.2 329.7 38 435 +2001 5 24 6 17 LESLIE 42.5 128.8 73 852 +1959 2 5 6 12 WILLIAM 63.4 344.7 32 84 +2002 11 24 6 21 SANDY 37.5 228.4 115 790 +1960 10 14 6 22 TONY 31.0 166.6 42 689 +1986 6 20 12 25 VALERIE 64.3 31.8 98 726 +2003 9 23 6 1 ISAAC 28.7 298.1 12 14 +1963 2 12 6 16 ISAAC 65.1 94.9 94 898 +1957 10 5 12 4 ISAAC 29.7 290.8 157 769 +1980 9 20 12 26 SANDY 64.2 164.1 46 419 +1967 4 16 18 25 PATTY 21.4 119.4 67 194 +1978 8 17 12 26 JOYCE 57.4 106.7 154 413 +1986 1 18 6 8 KIRK 45.5 170.1 38 37 +1976 1 7 6 23 RAFAEL 68.7 100.3 75 281 +1954 7 28 0 26 FLORENCE 50.7 346.9 32 620 +1974 4 9 6 4 NADINE 23.0 83.5 103 570 +1965 6 27 6 2 ISAAC 65.5 280.6 118 449 +1995 8 12 12 19 PATTY 33.3 175.9 119 465 +2000 11 11 0 15 WILLIAM 47.8 307.0 158 35 +1950 7 13 12 8 ALBERTO 64.8 165.5 92 188 +1989 2 16 12 24 CHRIS 38.2 63.0 151 619 +2001 4 3 6 1 PATTY 64.6 300.4 58 55 +1984 5 13 0 24 MICHAEL 66.2 264.4 85 651 +1971 1 12 18 15 TONY 30.8 29.8 114 355 +1987 7 6 12 28 ALBERTO 32.4 3.8 53 706 +1987 4 2 12 7 NADINE 30.1 279.1 108 601 +1990 8 23 0 8 FLORENCE 56.4 213.1 140 340 +1970 3 15 12 18 BERYL 52.6 136.3 160 762 +1969 4 24 0 10 MICHAEL 29.3 233.4 110 582 +1961 11 13 6 28 ERNESTO 29.7 1.7 78 748 +1978 3 8 6 9 SANDY 11.3 114.8 146 833 +1988 12 5 12 20 PATTY 26.4 157.8 161 781 +1999 6 13 6 14 NADINE 25.6 71.5 155 503 +1964 12 17 18 11 VALERIE 42.1 215.2 156 893 +1968 4 1 6 9 ALBERTO 57.8 151.7 111 367 +1957 3 10 18 4 SANDY 28.3 28.3 72 534 +1979 6 12 12 15 VALERIE 15.8 189.7 118 546 +1980 9 1 6 7 CHRIS 66.5 310.7 150 542 +1987 8 9 12 27 KIRK 10.7 178.7 122 480 +1963 10 27 18 26 LESLIE 67.9 133.5 113 707 +1960 6 22 0 8 OSCAR 63.1 52.4 110 828 +1985 1 17 12 25 KIRK 63.1 97.8 149 896 +1970 6 26 12 16 TONY 55.0 176.3 150 771 +1953 5 9 18 27 CHRIS 19.3 221.1 86 617 +1956 3 11 6 12 MICHAEL 16.1 354.1 154 595 +1995 12 9 6 7 OSCAR 58.2 84.1 39 148 +1956 12 23 12 16 PATTY 50.4 161.0 110 260 +1983 6 17 6 21 NADINE 52.2 105.8 101 164 +1966 8 9 6 21 GORDON 68.3 103.5 58 494 +1954 1 13 0 27 OSCAR 27.0 44.6 99 208 +1959 6 14 18 4 BERYL 64.0 356.7 108 72 +1978 11 11 12 7 GORDON 19.5 353.0 99 433 +1995 6 9 18 2 VALERIE 65.1 188.9 84 717 +1964 11 4 6 27 ERNESTO 33.9 81.3 65 692 +1962 12 10 12 1 WILLIAM 69.8 176.5 138 270 +1978 7 18 12 16 BERYL 24.6 161.9 94 885 +1981 1 11 18 18 KIRK 26.8 208.7 40 896 +1958 11 9 0 15 JOYCE 10.3 233.8 108 97 +2004 8 3 18 6 HELENE 24.6 19.6 41 354 +1964 11 3 0 20 RAFAEL 50.2 120.1 44 722 +1959 3 5 6 27 RAFAEL 58.8 17.7 42 576 +1982 12 25 6 6 NADINE 49.6 57.7 48 261 +1992 2 1 18 19 TONY 31.1 35.2 42 417 +2003 1 21 0 25 ERNESTO 57.4 220.4 150 887 +1961 3 25 6 5 OSCAR 14.2 177.6 151 341 +1996 1 23 12 7 FLORENCE 62.2 49.8 32 66 +1970 2 20 6 7 ERNESTO 10.6 351.5 87 895 +1981 11 4 12 14 SANDY 16.6 38.2 155 436 +1982 4 25 0 4 WILLIAM 14.1 105.9 162 339 +1981 2 10 12 12 SANDY 66.4 248.1 98 187 +1958 12 25 6 25 WILLIAM 45.6 228.8 123 129 +1990 10 1 12 11 JOYCE 65.5 26.4 26 857 +1970 1 28 6 21 LESLIE 10.5 70.1 93 91 +1996 2 15 12 28 OSCAR 12.9 300.9 51 304 +1965 9 1 18 16 WILLIAM 55.8 107.6 33 47 +1989 5 15 12 18 VALERIE 21.5 112.7 111 519 +1995 12 12 12 16 ALBERTO 37.2 313.6 163 54 +1969 1 9 6 22 GORDON 20.2 308.7 90 45 +1974 2 4 6 9 FLORENCE 47.0 221.2 150 232 +1980 3 21 6 2 CHRIS 31.1 30.4 85 193 +1961 5 27 18 12 PATTY 46.2 117.2 123 431 +1995 12 21 18 20 WILLIAM 52.3 68.5 81 43 +1955 3 7 6 3 LESLIE 57.5 126.4 38 406 +1956 1 4 12 21 ISAAC 56.3 4.3 81 15 +1999 10 26 0 19 OSCAR 22.1 154.9 102 252 +1987 7 2 6 12 RAFAEL 47.5 86.5 15 646 +1995 2 9 0 20 SANDY 60.3 149.3 23 661 +1990 1 12 18 22 CHRIS 20.7 243.1 40 352 +1984 6 19 6 13 ERNESTO 51.1 77.2 93 751 +1961 9 9 18 22 KIRK 13.4 126.9 30 192 +1952 7 21 0 20 PATTY 65.1 200.4 136 792 +1980 7 17 18 2 PATTY 25.5 343.3 119 246 +1971 7 14 18 11 DEBBY 44.1 261.1 41 664 +1965 6 24 12 4 VALERIE 53.6 227.6 137 6 +1973 10 13 0 1 CHRIS 15.6 60.9 92 234 +1996 9 24 18 9 NADINE 52.0 115.3 149 388 +1987 8 28 12 19 CHRIS 36.9 8.3 53 134 +1981 8 20 18 16 ERNESTO 58.4 74.9 13 572 +1994 6 19 6 13 TONY 8.4 143.2 53 169 +2001 6 27 0 19 ISAAC 48.9 15.0 82 693 +1961 12 20 12 8 WILLIAM 60.7 51.7 49 249 +1961 4 23 18 12 FLORENCE 59.4 261.6 51 154 +1985 6 9 0 8 KIRK 32.1 180.3 40 728 +1950 12 1 6 13 ERNESTO 11.9 340.0 37 424 +2004 1 22 18 4 WILLIAM 45.1 282.5 61 296 +1977 3 23 18 7 GORDON 33.5 31.5 39 77 +2000 12 23 6 17 GORDON 37.0 352.2 108 257 +1967 4 27 12 21 NADINE 27.6 178.3 152 399 +1981 2 27 0 5 HELENE 43.4 325.8 156 825 +1950 11 14 0 10 FLORENCE 43.8 277.5 40 23 +1983 9 11 18 5 WILLIAM 44.0 7.4 29 745 +1979 7 11 0 3 JOYCE 23.3 270.4 56 803 +1971 3 7 6 7 DEBBY 27.6 113.4 50 108 +1952 7 20 6 7 DEBBY 53.2 31.1 108 3 +1991 11 28 12 5 BERYL 30.0 22.3 15 857 +1991 9 3 12 12 PATTY 39.4 148.3 161 850 +1953 3 19 12 3 FLORENCE 38.8 255.1 146 193 +1966 2 21 0 5 OSCAR 48.2 91.8 39 290 +1966 4 18 6 13 LESLIE 29.0 203.0 89 309 +1987 3 4 6 28 ALBERTO 24.7 109.4 116 514 +1992 7 2 12 10 FLORENCE 14.6 7.5 114 393 +1989 3 20 0 16 GORDON 47.6 81.8 143 584 +1981 5 18 12 20 HELENE 13.9 342.8 14 701 +1996 9 20 0 11 CHRIS 52.2 282.1 109 336 +1990 7 21 6 8 KIRK 17.7 148.9 72 769 +1980 12 24 12 17 ISAAC 29.6 204.2 123 862 +1963 11 3 12 28 FLORENCE 40.0 256.9 24 879 +1958 7 28 6 22 NADINE 57.5 45.9 105 161 +1986 1 22 12 28 FLORENCE 39.6 328.6 129 120 +1970 9 4 6 3 ALBERTO 47.4 36.7 94 523 +1958 11 2 18 18 DEBBY 53.0 272.8 147 793 +1961 10 22 0 20 VALERIE 37.3 78.5 17 635 +1950 2 18 12 10 DEBBY 9.5 117.6 113 732 +1964 3 4 12 1 ALBERTO 44.6 181.4 123 452 +1976 2 8 6 10 ISAAC 69.1 203.4 105 26 +1950 5 10 6 20 RAFAEL 44.2 221.1 65 446 +1969 2 3 6 23 OSCAR 29.9 345.3 145 586 +1965 6 5 6 16 SANDY 52.3 130.6 123 151 +1958 8 23 6 12 BERYL 48.3 226.4 139 212 +1954 6 13 12 26 BERYL 43.3 192.2 77 381 +1953 12 27 0 28 LESLIE 11.5 57.9 111 530 +1969 12 22 0 9 ERNESTO 32.8 84.6 13 560 +1987 1 11 0 17 RAFAEL 57.5 283.0 100 540 +1975 8 28 0 14 LESLIE 43.4 300.0 63 86 +1974 12 25 0 9 CHRIS 57.9 301.9 145 216 +2000 8 21 0 28 SANDY 11.1 140.6 149 565 +1960 11 17 0 27 ALBERTO 21.9 93.3 163 403 +1985 8 13 6 10 KIRK 14.1 275.5 30 508 +1997 10 8 18 5 WILLIAM 17.7 271.4 137 811 +1972 5 3 0 24 ERNESTO 45.3 185.0 47 467 +1952 5 1 12 19 GORDON 21.6 80.4 148 426 +1977 10 5 12 20 WILLIAM 14.4 252.9 77 345 +1962 4 11 18 15 LESLIE 53.8 229.0 39 71 +1987 2 21 6 20 TONY 45.9 338.7 146 645 +1966 8 10 18 3 HELENE 38.7 166.8 102 310 +1992 10 15 6 12 NADINE 35.5 131.0 65 457 +1957 7 22 18 18 TONY 11.9 336.1 116 28 +1960 3 5 12 3 JOYCE 68.4 162.3 103 199 +1998 1 22 12 22 JOYCE 33.6 38.4 23 163 +1954 10 26 6 23 LESLIE 24.9 205.8 158 115 +1974 3 23 12 14 DEBBY 22.4 140.8 28 803 +1954 3 2 12 11 SANDY 10.3 271.8 130 537 +2001 5 26 18 23 ISAAC 49.1 80.6 84 871 +1981 4 10 6 19 NADINE 58.9 107.2 126 641 +2002 6 4 0 17 PATTY 63.5 213.1 158 579 +1964 9 16 6 10 DEBBY 65.3 135.2 135 197 +2000 8 24 6 2 DEBBY 36.8 99.1 22 127 +1975 6 26 0 5 NADINE 51.0 4.0 90 709 +1994 6 6 18 15 ISAAC 63.7 15.0 28 380 +2004 1 15 6 22 HELENE 12.6 24.1 44 499 +1952 2 19 6 1 OSCAR 8.0 326.3 144 274 +1979 8 24 6 7 FLORENCE 46.5 194.4 93 114 +1974 4 19 0 18 GORDON 24.6 188.1 46 4 +1963 7 21 0 26 ERNESTO 22.4 243.8 152 580 +1990 4 5 18 8 JOYCE 54.9 29.5 130 375 +1999 5 11 18 6 LESLIE 19.5 134.1 84 57 +1960 2 7 0 4 TONY 44.7 67.7 70 19 +1959 11 1 0 22 LESLIE 61.3 46.0 42 606 +1975 9 17 18 1 RAFAEL 10.2 253.0 151 108 +1969 3 27 12 16 JOYCE 55.6 333.8 156 434 +1996 7 28 18 4 GORDON 60.6 283.9 62 639 +1973 4 14 12 7 VALERIE 9.3 128.7 81 225 +1980 10 28 0 8 OSCAR 16.1 292.1 98 403 +1970 12 27 18 22 RAFAEL 55.8 168.0 17 743 +1983 8 13 12 16 GORDON 16.4 152.2 118 77 +2002 9 19 6 15 HELENE 49.0 252.6 76 612 +1958 9 24 6 5 ISAAC 63.6 21.3 29 658 +1986 4 5 18 27 MICHAEL 8.7 145.0 143 328 +1960 11 8 0 7 BERYL 32.5 357.7 161 546 +1951 8 7 12 17 DEBBY 66.7 18.5 28 415 +2004 5 8 6 23 ALBERTO 69.9 251.3 21 213 +1969 2 12 18 26 FLORENCE 49.7 38.4 138 822 +1993 8 16 6 21 MICHAEL 47.3 211.3 155 430 +1972 6 23 18 22 KIRK 68.3 21.9 150 274 +1979 12 27 6 7 RAFAEL 17.3 317.0 158 837 +1951 2 8 12 10 TONY 50.6 178.7 162 685 +1988 5 17 18 8 RAFAEL 19.9 285.8 69 552 +1951 3 8 12 18 CHRIS 63.1 76.3 126 23 +1971 11 1 6 17 RAFAEL 69.2 320.7 53 451 +1965 3 14 18 23 BERYL 49.0 347.5 82 92 +1975 5 5 6 7 MICHAEL 24.2 120.1 76 469 +1968 1 8 0 17 FLORENCE 41.4 335.1 66 277 +1971 6 5 6 17 HELENE 20.5 31.3 17 68 +1950 2 21 6 15 TONY 33.8 167.0 42 694 +1985 8 5 12 1 NADINE 40.4 286.3 51 130 +1963 10 7 18 8 DEBBY 28.9 278.4 53 818 +1988 3 2 12 21 GORDON 61.0 206.0 150 159 +1971 5 3 0 21 SANDY 10.7 298.8 62 189 +1994 8 2 0 11 VALERIE 28.2 34.2 25 176 +1982 11 15 18 23 VALERIE 37.9 37.4 39 179 +1982 9 25 0 18 MICHAEL 46.3 272.4 90 883 +1979 5 3 0 9 ERNESTO 18.8 15.2 157 0 +1976 11 5 6 23 LESLIE 66.2 327.2 69 214 +1995 12 20 12 15 PATTY 46.5 29.3 147 358 +2000 12 3 0 19 NADINE 38.1 199.0 33 246 +1998 2 20 18 7 FLORENCE 50.9 62.0 41 465 +1954 3 16 0 6 ALBERTO 47.3 32.8 17 516 +2000 1 18 12 17 ERNESTO 37.9 44.8 152 142 +1998 9 22 18 18 VALERIE 64.7 35.0 47 867 +1952 11 28 0 27 CHRIS 56.0 221.4 125 803 +1981 5 11 0 1 NADINE 42.7 88.7 20 537 +1963 4 2 0 8 BERYL 7.4 217.7 81 230 +1981 10 4 0 24 ISAAC 57.0 131.7 32 99 +1957 6 1 6 9 HELENE 17.9 215.9 118 214 +1972 3 28 6 5 ISAAC 8.3 261.0 91 256 +1960 5 12 0 15 JOYCE 58.1 341.0 18 396 +1955 5 16 12 25 WILLIAM 11.7 50.1 93 552 +1965 8 22 0 19 JOYCE 58.3 79.0 27 240 +1953 7 21 12 19 WILLIAM 43.0 23.7 18 521 +1964 12 1 18 3 HELENE 28.7 319.7 106 113 +1998 7 1 6 12 PATTY 15.6 15.0 130 268 +1987 8 6 18 25 FLORENCE 36.6 89.3 67 881 +1992 8 11 0 28 MICHAEL 47.4 80.5 85 829 +1954 9 8 0 7 KIRK 31.6 16.9 55 523 +1957 10 24 0 7 RAFAEL 40.9 235.7 137 289 +1960 10 16 0 21 HELENE 24.7 178.0 137 432 +1956 7 2 12 12 OSCAR 25.0 68.3 107 884 +1968 2 4 0 1 ALBERTO 27.5 68.6 163 472 +1981 5 7 6 26 WILLIAM 10.2 142.9 97 797 +2004 10 18 6 22 KIRK 12.5 126.2 77 122 +1973 7 5 18 16 SANDY 45.3 290.6 27 841 +1961 5 23 18 15 SANDY 33.6 350.5 160 668 +1957 2 9 0 10 TONY 57.2 92.8 158 247 +1991 3 25 12 16 ALBERTO 28.0 309.7 40 233 +1956 12 24 6 13 DEBBY 47.4 100.3 21 549 +1955 5 27 18 24 SANDY 67.3 96.6 129 663 +1978 11 13 0 20 NADINE 21.5 339.5 152 431 +1967 12 11 0 26 HELENE 50.5 303.8 33 360 +1983 2 2 6 28 ALBERTO 8.0 268.2 29 669 +1994 12 3 18 22 CHRIS 54.2 143.0 154 137 +1990 5 22 12 25 LESLIE 23.8 131.7 115 25 +1951 9 23 6 6 CHRIS 15.0 357.4 72 256 +2001 5 18 12 2 PATTY 23.4 147.8 143 419 +1957 12 2 18 24 NADINE 35.7 276.6 47 625 +1961 3 19 6 24 GORDON 46.2 87.3 96 228 +1956 5 12 6 10 TONY 43.2 239.7 76 386 +1988 4 14 12 11 JOYCE 48.0 15.0 78 823 +1953 11 17 0 1 ERNESTO 61.5 150.4 129 162 +1997 6 18 18 16 ERNESTO 60.6 258.8 161 574 +1978 3 11 18 8 SANDY 40.4 241.6 163 253 +1976 3 17 0 23 OSCAR 8.0 241.2 20 84 +1997 8 6 0 15 ALBERTO 57.5 116.7 63 153 +1962 1 23 0 4 NADINE 32.6 185.5 47 775 +1962 10 26 12 17 NADINE 66.5 42.7 122 544 +2000 7 28 6 7 RAFAEL 42.7 355.2 156 89 +1956 12 21 6 1 SANDY 65.9 140.8 123 324 +1959 8 14 6 7 RAFAEL 31.5 256.6 63 178 +1952 11 1 18 24 SANDY 49.2 48.7 151 85 +1983 5 4 18 22 WILLIAM 69.2 140.2 23 789 +1959 5 16 12 18 LESLIE 62.0 165.4 24 136 +1971 4 17 18 5 BERYL 50.6 145.4 53 30 +1953 4 4 6 1 TONY 27.6 46.9 68 808 +1950 11 20 0 12 NADINE 40.0 246.6 135 854 +1971 9 6 12 4 SANDY 37.4 331.6 26 639 +1979 10 15 6 7 MICHAEL 64.6 237.7 19 716 +1953 12 10 6 5 DEBBY 42.0 152.2 136 262 +1985 2 17 0 6 ERNESTO 19.5 74.4 115 50 +2004 3 16 12 7 TONY 53.4 342.7 12 408 +1968 10 27 0 7 DEBBY 19.4 107.1 18 120 +1980 12 13 6 22 KIRK 68.5 337.9 15 214 +1987 11 12 0 15 HELENE 37.6 169.4 62 201 +1992 6 1 0 8 ALBERTO 66.7 355.2 41 221 +1957 5 24 12 12 NADINE 19.1 8.8 23 184 +1980 1 25 6 20 ALBERTO 30.3 343.8 47 32 +1990 6 22 12 27 PATTY 30.1 339.5 160 426 +1995 11 22 6 15 MICHAEL 57.1 135.6 80 224 +1991 8 22 12 7 NADINE 43.1 214.5 60 604 +1967 4 10 6 27 SANDY 21.8 32.6 65 52 +1970 1 4 12 3 WILLIAM 64.4 16.0 121 765 +1988 10 7 18 22 SANDY 63.4 178.9 65 862 +2003 6 4 12 6 FLORENCE 49.9 256.9 100 173 +1988 4 26 6 3 WILLIAM 37.0 139.4 111 114 +1986 8 15 12 21 CHRIS 28.4 15.5 104 418 +1970 6 18 0 24 RAFAEL 62.9 23.0 16 35 +1999 1 27 18 25 LESLIE 45.5 106.7 105 392 +1981 9 18 6 9 SANDY 53.1 231.9 45 525 +1955 9 15 12 12 KIRK 31.8 209.4 155 234 +1957 6 5 12 2 VALERIE 15.0 178.5 81 637 +2000 11 20 6 23 PATTY 27.1 93.8 24 506 +1991 9 24 18 13 HELENE 20.1 122.0 79 334 +1959 7 8 6 11 NADINE 63.8 192.5 56 174 +1975 1 28 18 6 GORDON 57.6 26.0 153 811 +1951 3 10 0 24 LESLIE 40.1 227.1 20 297 +1981 1 4 18 15 LESLIE 60.0 206.4 116 227 +1964 9 14 6 17 HELENE 25.9 239.6 127 437 +1986 3 2 12 24 TONY 47.5 220.0 130 90 +1970 1 18 12 2 MICHAEL 64.2 52.9 70 544 +1954 3 9 18 25 JOYCE 56.6 26.6 26 710 +1980 1 18 6 15 NADINE 54.1 224.9 142 805 +1981 10 3 6 13 FLORENCE 20.5 133.0 123 102 +1988 1 6 6 19 OSCAR 57.7 151.7 81 292 +1981 4 3 18 13 FLORENCE 34.4 87.0 53 416 +1967 5 3 6 15 NADINE 36.3 13.8 64 569 +1983 1 13 0 25 FLORENCE 41.1 66.0 130 492 +1959 5 14 12 20 PATTY 35.5 16.4 34 206 +1992 9 19 12 26 SANDY 13.1 20.8 95 333 +1989 12 22 12 19 CHRIS 50.4 249.1 152 536 +1960 5 16 0 25 HELENE 66.2 239.9 91 748 +1971 1 4 6 8 LESLIE 55.2 316.8 150 504 +1950 8 9 0 8 MICHAEL 24.9 285.6 47 542 +1953 2 2 12 27 BERYL 42.6 57.4 99 779 +1957 6 6 18 1 HELENE 20.3 322.5 45 269 +1973 6 14 12 2 TONY 12.9 286.1 54 728 +1982 5 19 0 23 GORDON 22.9 73.0 29 344 +2000 6 5 6 1 JOYCE 55.9 280.6 112 631 +1991 9 9 12 23 FLORENCE 7.1 37.4 50 277 +1993 4 28 12 21 CHRIS 32.0 342.0 112 38 +2003 1 1 6 25 DEBBY 7.4 260.5 96 163 +1960 7 19 12 16 GORDON 8.1 217.0 18 510 +1950 12 23 6 6 SANDY 15.4 174.6 64 477 +1974 3 11 0 27 VALERIE 19.5 45.8 161 406 +1978 11 9 12 10 KIRK 17.7 92.8 147 77 +1986 3 19 0 19 ALBERTO 27.4 78.0 35 732 +1951 7 26 0 9 FLORENCE 47.9 211.7 29 888 +1963 1 22 0 12 NADINE 15.5 317.4 51 847 +1986 5 18 0 16 LESLIE 7.5 173.7 48 861 +1999 7 11 12 26 HELENE 35.2 355.4 150 764 +1986 3 4 0 23 OSCAR 67.0 256.8 22 805 +1972 7 22 6 1 JOYCE 66.3 308.5 69 795 +1993 5 9 12 1 LESLIE 13.0 150.0 152 494 +1956 3 24 18 15 OSCAR 54.8 178.8 81 714 +1995 10 18 6 19 GORDON 68.2 287.4 156 792 +1968 2 24 12 28 FLORENCE 50.9 319.9 24 272 +1959 6 3 12 16 RAFAEL 67.3 318.7 101 604 +1967 8 25 6 9 MICHAEL 55.4 343.8 60 374 +1986 10 4 6 6 SANDY 10.3 242.5 40 155 +1960 9 9 12 20 WILLIAM 57.2 98.5 62 178 +1962 7 17 0 28 LESLIE 44.0 323.9 26 808 +1972 5 26 0 28 ISAAC 13.5 17.8 128 516 +1960 2 21 6 13 TONY 46.8 352.5 43 163 +2001 8 7 0 2 GORDON 17.5 348.2 138 225 +1998 2 18 12 6 MICHAEL 27.5 264.3 142 348 +1970 5 6 6 5 RAFAEL 44.2 57.2 159 550 +1999 6 9 12 15 KIRK 59.0 23.3 115 817 +1991 5 10 0 4 VALERIE 64.3 135.9 32 423 +1964 4 9 0 11 HELENE 22.6 352.4 39 800 +1968 6 13 0 19 SANDY 34.9 298.2 135 542 +1999 11 7 6 16 BERYL 30.3 57.3 11 665 +1965 6 21 6 13 ISAAC 33.3 118.9 118 280 +1979 12 27 12 3 PATTY 48.3 286.7 50 73 +1959 4 12 18 1 ISAAC 33.9 187.1 163 211 +1983 4 6 18 10 ISAAC 41.5 348.9 156 97 +1988 9 22 18 20 NADINE 59.0 280.5 45 771 +1950 11 19 0 7 JOYCE 10.8 2.7 96 139 +1964 12 1 12 25 RAFAEL 11.9 222.5 164 519 +1953 7 10 12 26 KIRK 63.1 329.5 113 43 +1964 3 8 12 27 JOYCE 15.8 77.0 97 126 +1962 8 17 12 4 HELENE 44.1 84.2 36 801 +1959 8 5 12 4 TONY 68.4 354.1 148 847 +1993 11 26 12 21 SANDY 18.1 172.8 113 891 +2003 10 20 18 17 SANDY 57.8 332.8 50 768 +1997 3 16 0 12 NADINE 14.2 26.5 141 127 +1992 8 22 6 26 DEBBY 43.8 59.4 46 59 +1964 2 18 6 27 RAFAEL 24.6 117.1 90 714 +1956 5 7 12 17 RAFAEL 13.0 342.7 118 841 +1993 8 27 0 19 TONY 15.1 145.9 30 429 +1978 2 15 6 18 WILLIAM 64.2 236.4 49 625 +1986 6 11 18 1 JOYCE 32.2 354.2 57 802 +1957 2 10 0 11 ALBERTO 68.7 322.3 141 555 +1955 10 17 0 24 HELENE 45.6 303.6 89 13 +1972 3 23 0 18 WILLIAM 21.2 187.1 22 347 +2000 4 9 0 28 LESLIE 13.8 334.5 54 525 +1983 12 28 6 20 WILLIAM 55.9 17.4 153 589 +1996 8 24 6 8 CHRIS 20.4 251.1 93 32 +2001 7 4 0 7 OSCAR 65.5 209.9 60 596 +1954 4 28 12 20 ERNESTO 24.4 262.8 47 362 +1994 10 24 12 14 FLORENCE 14.6 129.9 24 154 +2000 11 10 0 4 CHRIS 36.9 8.3 126 764 +1967 4 20 6 18 CHRIS 45.2 199.5 16 646 +1955 7 27 0 21 ALBERTO 20.6 167.0 102 279 +1969 4 18 6 3 RAFAEL 62.9 70.3 118 90 +1998 3 5 6 26 NADINE 29.2 196.1 139 98 +1973 5 26 0 16 HELENE 61.4 11.5 52 694 +1976 10 16 18 15 DEBBY 25.8 21.7 76 142 +1985 1 21 18 23 ALBERTO 33.9 102.0 63 201 +1979 6 22 18 11 OSCAR 34.1 27.8 41 125 +1957 2 8 0 3 ISAAC 51.5 272.0 111 693 +1959 9 4 0 25 ISAAC 47.8 87.7 48 217 +1997 6 27 18 19 CHRIS 39.6 105.5 22 757 +2002 6 25 18 13 PATTY 29.4 107.4 98 71 +1986 2 16 0 25 HELENE 33.9 282.1 62 206 +1957 9 12 12 17 NADINE 11.1 166.3 35 579 +1968 4 18 18 4 MICHAEL 16.1 355.7 139 597 +1987 8 3 6 5 GORDON 31.7 342.9 97 367 +1974 2 28 12 15 KIRK 15.3 53.8 125 581 +1954 12 15 6 18 WILLIAM 63.6 217.7 71 803 +1969 7 27 6 17 JOYCE 29.7 109.0 97 231 +1984 1 5 12 12 SANDY 8.9 332.4 154 197 +1951 3 4 0 16 ERNESTO 47.5 228.0 24 312 +1964 3 22 6 26 HELENE 61.4 286.6 47 124 +1978 5 16 12 27 ISAAC 20.6 279.1 80 312 +1988 3 7 0 24 LESLIE 65.2 251.3 19 724 +1975 2 28 12 23 PATTY 51.3 216.7 96 682 +1960 6 26 6 4 OSCAR 35.3 172.6 36 793 +1969 9 18 18 22 SANDY 23.5 247.2 151 134 +1999 4 23 18 1 WILLIAM 21.7 262.4 114 710 +1982 4 10 12 4 HELENE 28.4 117.9 69 122 +1964 8 26 12 11 PATTY 20.1 325.0 38 325 +1974 4 6 12 15 VALERIE 14.1 12.1 68 534 +1995 10 27 0 27 MICHAEL 34.9 33.3 78 3 +1972 9 26 0 12 ALBERTO 64.2 125.2 112 263 +1980 7 23 0 13 DEBBY 65.6 88.7 103 458 +1980 2 4 18 26 WILLIAM 8.7 160.4 92 657 +1959 2 21 12 9 SANDY 39.7 290.1 104 788 +1969 10 24 18 3 HELENE 21.9 295.6 35 477 +1976 6 26 6 6 NADINE 67.4 242.8 115 579 +1980 12 14 6 12 ALBERTO 66.8 54.2 148 644 +1978 7 9 6 19 WILLIAM 36.9 212.9 53 345 +1987 5 25 18 20 JOYCE 40.4 254.8 31 823 +1967 11 14 12 27 TONY 63.5 118.6 14 30 +1993 1 7 6 4 VALERIE 63.5 186.0 50 795 +1972 10 20 0 25 GORDON 26.1 312.7 76 800 +1965 1 9 12 23 PATTY 64.2 39.2 43 421 +1968 5 18 12 24 GORDON 25.4 179.2 43 557 +1982 11 19 12 27 ERNESTO 12.5 25.2 140 503 +1963 7 28 6 1 RAFAEL 69.7 296.8 34 599 +1982 8 19 0 20 RAFAEL 51.1 7.4 113 557 +1962 6 18 6 20 TONY 62.5 121.5 125 593 +1984 8 5 0 28 MICHAEL 28.1 198.0 153 556 +1959 6 13 6 18 KIRK 34.1 68.2 81 43 +1965 5 16 18 5 OSCAR 66.6 335.3 29 598 +1962 8 14 0 9 KIRK 14.7 199.3 160 286 +1997 2 8 0 25 HELENE 49.7 208.2 151 618 +2004 6 27 12 7 ERNESTO 19.9 241.6 97 217 +1961 3 16 12 12 ALBERTO 24.3 239.9 46 639 +1955 3 26 6 2 KIRK 59.4 35.0 112 806 +1993 7 13 12 24 CHRIS 51.3 25.2 122 702 +1957 5 2 6 21 VALERIE 36.4 181.5 92 776 +1989 4 24 0 18 GORDON 55.7 285.6 116 22 +1980 8 20 0 11 SANDY 19.2 273.9 43 115 +1982 6 6 18 28 KIRK 66.2 354.0 71 257 +1959 4 11 18 23 RAFAEL 50.8 93.2 27 43 +1975 6 15 18 2 PATTY 19.7 242.4 88 19 +1980 5 7 0 24 BERYL 48.3 319.9 52 295 +1988 5 23 18 2 FLORENCE 45.3 257.4 47 322 +1981 7 13 18 18 HELENE 17.0 225.6 16 805 +1971 5 1 6 21 ERNESTO 37.1 269.0 102 404 +1994 8 14 0 20 SANDY 7.1 17.7 58 892 +1971 2 15 6 19 NADINE 20.1 249.3 155 261 +1979 8 20 6 10 LESLIE 67.4 139.2 145 338 +1996 1 6 12 28 KIRK 64.8 335.8 43 335 +1967 4 25 18 27 JOYCE 62.0 214.5 120 135 +1989 3 1 12 21 HELENE 37.2 25.8 43 420 +1988 4 8 18 5 OSCAR 31.7 190.6 148 404 +1951 2 21 18 25 OSCAR 54.2 325.8 134 707 +1977 7 23 6 13 CHRIS 55.2 303.6 46 827 +1961 12 19 12 10 PATTY 62.8 313.5 22 341 +1951 10 6 0 17 ISAAC 49.0 182.7 99 752 +1977 7 11 0 27 ALBERTO 30.5 184.4 92 304 +1962 7 28 12 26 OSCAR 51.9 157.1 47 819 +1952 2 5 0 28 GORDON 43.4 218.2 51 150 +1972 2 25 6 12 JOYCE 45.9 25.5 31 496 +1986 8 11 0 25 TONY 8.8 30.0 107 681 +1998 9 23 6 20 CHRIS 57.0 151.4 154 373 +1994 5 19 0 17 ALBERTO 20.1 173.8 79 217 +1987 3 18 6 27 OSCAR 37.5 130.9 43 645 +1959 10 16 18 22 FLORENCE 35.9 258.6 31 366 +1968 4 25 0 7 ERNESTO 40.3 194.4 109 582 +1995 3 22 18 20 ISAAC 61.4 133.2 14 457 +1998 1 20 6 3 JOYCE 28.9 289.9 133 303 +1970 9 5 6 8 WILLIAM 25.5 161.7 153 349 +1954 5 27 18 25 OSCAR 22.4 252.6 82 380 +1993 8 22 12 7 VALERIE 55.6 91.9 22 235 +1967 10 8 18 23 ALBERTO 15.3 197.1 134 491 +1967 9 2 12 1 GORDON 9.2 350.7 24 94 +1963 2 19 12 16 VALERIE 7.9 313.4 65 571 +1997 1 1 18 15 ERNESTO 25.9 157.1 64 41 +2003 7 24 0 14 RAFAEL 16.6 74.4 152 248 +1997 5 22 12 2 TONY 19.8 257.8 149 359 +1982 7 10 0 19 NADINE 69.5 239.9 96 848 +1998 7 26 0 28 BERYL 11.3 44.7 153 234 +1978 2 28 18 12 DEBBY 39.2 332.4 77 608 +1965 1 16 18 22 NADINE 68.8 334.3 120 19 +1994 7 1 6 13 LESLIE 47.7 331.2 28 588 +1955 1 3 6 21 TONY 11.8 255.3 164 514 +1974 5 21 18 6 TONY 13.1 30.8 143 264 +1988 12 20 0 11 ALBERTO 51.6 327.2 54 769 +1980 5 19 18 18 ERNESTO 31.4 312.4 63 119 +1977 3 10 0 22 KIRK 53.9 271.2 15 641 +1961 1 3 12 27 BERYL 52.9 313.0 164 491 +1998 7 12 12 5 OSCAR 31.9 225.9 137 390 +1981 2 19 12 18 FLORENCE 47.4 312.4 134 280 +1987 6 9 0 24 HELENE 35.4 126.6 163 754 +1990 11 15 18 21 MICHAEL 46.0 178.2 148 86 +1986 9 17 18 19 DEBBY 29.7 4.7 75 385 +1977 2 1 12 25 OSCAR 45.9 81.0 28 491 +1988 7 3 18 26 PATTY 34.6 158.8 32 884 +1955 9 2 6 20 DEBBY 28.8 168.5 53 372 +1953 12 7 0 27 JOYCE 34.6 195.4 59 358 +1975 10 25 18 23 VALERIE 9.5 351.2 33 640 +1969 11 17 0 26 KIRK 15.7 221.7 20 251 +1954 4 5 12 10 OSCAR 11.8 231.0 22 96 +1996 9 14 12 14 DEBBY 67.1 246.1 40 504 +2001 2 19 6 8 NADINE 21.4 142.2 129 629 +1981 7 4 18 23 TONY 13.0 317.6 98 684 +1959 8 10 0 19 BERYL 11.7 193.2 131 462 +1967 6 7 0 23 HELENE 54.6 212.8 50 796 +1968 12 12 0 9 GORDON 47.3 200.3 47 566 +1983 3 1 0 25 NADINE 50.2 125.5 119 552 +1987 4 13 0 17 RAFAEL 64.1 246.7 89 332 +1992 6 23 0 28 ISAAC 33.7 56.9 15 275 +1985 7 8 6 8 FLORENCE 33.8 320.0 86 763 +1951 2 1 12 26 KIRK 63.0 173.3 106 512 +1971 5 17 0 8 WILLIAM 40.4 127.4 29 24 +1955 10 18 12 7 PATTY 17.3 118.4 29 471 +1964 6 26 0 11 HELENE 68.7 207.6 95 723 +1995 3 3 6 26 CHRIS 14.4 69.8 162 281 +1991 1 19 18 7 BERYL 54.7 303.3 143 159 +1963 10 20 12 27 MICHAEL 57.0 45.1 102 410 +2003 6 27 0 25 VALERIE 30.7 123.9 68 531 +1993 11 21 6 11 TONY 67.2 159.0 127 297 +1992 8 4 18 23 FLORENCE 48.2 264.1 17 708 +1994 2 2 6 21 ALBERTO 66.6 236.6 160 538 +1993 8 27 6 28 HELENE 60.6 148.5 84 207 +1975 11 15 0 11 ALBERTO 14.6 115.5 85 491 +2003 12 25 18 13 MICHAEL 19.1 217.3 150 60 +1988 12 14 6 1 ALBERTO 47.8 311.9 38 439 +1973 10 10 0 20 ISAAC 45.9 249.3 143 88 +1976 8 24 12 4 GORDON 13.2 124.9 11 475 +1973 7 12 18 18 HELENE 68.5 76.0 131 848 +1989 7 19 18 2 RAFAEL 31.2 328.1 142 671 +1997 9 5 0 21 VALERIE 42.9 150.8 74 378 +1967 9 21 18 17 RAFAEL 32.8 347.9 38 434 +1973 6 10 12 28 FLORENCE 41.0 309.4 41 647 +1992 9 6 0 3 PATTY 41.4 96.0 74 896 +1956 9 12 18 23 ALBERTO 54.6 267.5 73 167 +1972 10 25 6 24 BERYL 53.8 131.4 124 667 +1986 3 21 6 6 PATTY 38.3 233.3 72 827 +1971 4 8 12 7 ERNESTO 43.4 99.9 29 854 +1956 6 10 18 16 GORDON 24.8 235.8 37 408 +1998 3 8 6 27 JOYCE 38.2 34.2 162 7 +1965 9 16 6 2 VALERIE 17.9 42.4 17 621 +1982 1 22 6 28 GORDON 8.6 48.3 140 187 +1981 9 1 12 21 HELENE 14.0 181.4 109 736 +1961 4 20 0 26 VALERIE 14.8 7.3 85 629 +1989 11 1 12 12 LESLIE 61.5 71.2 27 785 +2000 4 16 18 25 WILLIAM 45.3 140.6 133 835 +1994 12 28 0 23 HELENE 62.9 198.6 115 841 +1962 3 11 0 20 BERYL 40.3 30.6 98 212 +1960 6 10 18 16 JOYCE 33.0 158.1 141 200 +1985 5 24 0 11 JOYCE 65.0 17.1 38 67 +1970 5 27 0 18 MICHAEL 44.7 280.3 70 770 +1960 8 13 12 6 RAFAEL 51.9 254.7 127 546 +1961 5 21 12 4 CHRIS 20.6 86.7 81 491 +1964 12 26 18 2 SANDY 39.5 18.8 115 51 +1950 11 10 6 13 CHRIS 66.9 156.4 72 315 +1995 12 16 0 24 RAFAEL 14.6 2.7 146 563 +1966 2 1 6 24 ALBERTO 58.5 167.7 88 747 +1959 3 16 12 11 ISAAC 8.9 314.1 24 588 +1979 9 5 6 18 DEBBY 51.2 128.9 160 641 +1962 3 19 0 1 OSCAR 55.4 203.8 63 790 +1971 11 11 0 19 KIRK 29.0 151.1 13 824 +1974 11 21 18 4 PATTY 7.4 289.3 134 801 +1974 4 25 18 15 VALERIE 48.6 170.9 15 729 +1963 10 11 12 15 RAFAEL 49.2 277.7 143 702 +1955 11 27 12 14 HELENE 33.9 196.4 86 480 +1958 11 26 12 27 CHRIS 13.8 250.4 118 494 +1974 6 6 12 25 DEBBY 30.8 279.0 140 843 +1953 11 22 0 7 VALERIE 53.9 148.7 135 207 +1973 5 21 6 3 FLORENCE 39.0 351.4 90 297 +1964 9 7 12 1 OSCAR 40.0 166.1 80 894 +1971 11 5 6 28 HELENE 34.2 12.7 121 550 +1976 1 28 12 6 NADINE 52.4 25.6 109 143 +1987 11 10 0 6 KIRK 29.4 39.2 12 353 +1994 1 6 18 6 RAFAEL 60.5 142.8 139 564 +2004 6 7 18 20 KIRK 15.0 55.7 37 22 +1997 6 6 6 16 HELENE 43.1 135.9 91 475 +1959 7 6 0 16 HELENE 60.2 161.6 61 395 +1988 3 19 6 23 ERNESTO 23.0 17.7 129 107 +2004 3 22 18 19 TONY 65.8 128.3 109 32 +2000 4 16 12 10 CHRIS 47.1 265.0 138 131 +1952 12 26 6 13 RAFAEL 65.3 354.9 118 478 +1955 9 22 18 17 OSCAR 38.5 182.1 61 518 +1997 11 5 12 14 HELENE 10.8 117.0 81 523 +1999 1 23 0 26 JOYCE 21.4 116.7 35 129 +2003 12 17 6 3 MICHAEL 27.5 49.3 52 388 +1950 3 20 6 14 FLORENCE 47.4 123.2 153 12 +1999 12 21 18 23 TONY 37.8 105.2 47 333 +1954 4 25 0 27 SANDY 46.9 266.9 133 361 +1991 12 15 18 27 BERYL 21.1 318.0 39 201 +1999 10 17 18 10 ALBERTO 28.9 329.2 94 757 +1965 9 14 18 18 TONY 53.3 67.0 122 596 +1965 5 18 6 22 WILLIAM 36.7 15.5 26 428 +1988 10 4 6 23 OSCAR 24.2 195.8 156 292 +1961 11 2 12 6 GORDON 17.1 288.2 86 883 +1991 1 14 6 4 SANDY 60.7 197.3 72 834 +1964 6 12 18 2 VALERIE 34.0 170.6 108 700 +1978 6 17 12 14 CHRIS 50.1 303.9 134 534 +1962 11 8 0 4 CHRIS 24.8 0.7 86 193 +1974 11 3 0 5 ALBERTO 66.3 235.4 86 612 +1990 12 5 12 2 MICHAEL 49.0 46.6 71 669 +1983 1 13 12 22 SANDY 13.3 347.8 117 649 +1950 5 2 18 14 CHRIS 35.1 303.8 21 39 +1998 5 14 12 9 MICHAEL 7.5 75.2 151 32 +1999 6 25 6 24 TONY 23.8 170.4 86 526 +1998 3 4 18 14 GORDON 19.1 122.2 128 454 +1999 9 2 6 1 JOYCE 18.3 17.2 96 778 +1969 12 7 12 16 OSCAR 14.3 16.9 19 820 +2002 8 6 0 15 VALERIE 42.7 207.2 137 238 +1968 1 19 6 23 DEBBY 44.9 152.9 46 317 +1957 4 7 0 8 PATTY 12.1 290.5 147 552 +1995 5 6 6 9 KIRK 19.4 88.3 33 339 +1958 8 24 12 1 OSCAR 18.7 228.4 125 593 +1955 8 15 18 26 CHRIS 44.1 94.8 140 172 +2001 6 8 12 19 HELENE 15.5 143.2 96 338 +1989 1 1 6 12 JOYCE 59.4 347.5 10 576 +1955 9 6 18 10 RAFAEL 27.8 130.9 65 342 +1989 3 25 18 23 TONY 54.6 73.3 106 492 +1973 1 2 0 1 PATTY 23.9 357.5 161 86 +1965 8 10 12 7 PATTY 56.6 22.1 33 603 +1989 5 1 18 10 NADINE 14.6 158.0 82 864 +1958 8 9 18 2 JOYCE 45.9 7.8 130 477 +1964 10 14 12 15 JOYCE 69.7 90.3 109 158 +1966 8 25 0 9 MICHAEL 55.7 70.4 164 407 +1964 8 2 12 27 BERYL 48.7 139.2 14 217 +1956 3 18 12 9 FLORENCE 21.0 314.3 58 88 +1981 1 8 12 5 CHRIS 34.9 291.6 25 345 +1965 11 18 18 17 RAFAEL 9.8 305.2 36 865 +1970 2 10 12 11 KIRK 25.2 140.5 79 531 +1991 6 4 6 4 JOYCE 55.4 142.1 38 720 +1973 1 27 18 18 FLORENCE 60.3 351.1 66 753 +1979 1 16 12 6 ALBERTO 10.7 332.2 126 372 +1981 5 25 12 1 JOYCE 45.2 175.8 83 313 +1973 11 1 12 17 PATTY 53.9 54.1 150 231 +1990 1 28 18 26 OSCAR 36.9 315.0 82 724 +1992 8 27 12 4 SANDY 21.8 305.8 83 715 +1986 8 25 18 3 BERYL 69.8 17.3 95 324 +1979 3 28 12 2 FLORENCE 67.6 127.7 44 46 +2004 10 1 0 13 JOYCE 65.7 8.8 17 300 +1963 9 22 12 23 FLORENCE 17.0 235.2 121 244 +1998 9 5 12 10 TONY 69.9 227.9 77 644 +2002 10 19 12 22 KIRK 43.5 340.3 72 446 +1978 9 24 18 19 NADINE 55.4 152.3 95 791 +1955 12 18 12 16 GORDON 44.2 198.9 129 753 +1955 10 2 0 18 HELENE 56.5 312.1 153 56 +1957 6 22 6 26 LESLIE 37.8 89.0 55 26 +1977 2 6 0 11 DEBBY 35.6 325.0 21 693 +1955 5 8 0 19 RAFAEL 50.4 233.4 96 330 +1996 3 20 18 16 DEBBY 14.9 195.6 73 601 +1982 6 12 18 5 ALBERTO 37.8 157.0 110 260 +1957 7 6 0 5 BERYL 26.7 351.3 94 720 +1982 3 12 18 6 CHRIS 18.0 238.5 51 440 +1968 12 27 0 27 PATTY 12.9 117.4 47 731 +1970 10 1 6 16 FLORENCE 19.7 350.4 100 835 +2004 9 12 12 13 NADINE 66.6 346.4 100 631 +2001 3 22 6 28 OSCAR 55.9 101.4 18 368 +1969 2 5 18 10 TONY 15.3 181.3 87 115 +1957 6 23 18 4 ISAAC 20.0 55.1 133 558 +1991 3 19 0 23 KIRK 51.3 310.9 89 805 +1955 1 10 12 22 VALERIE 10.2 15.1 59 728 +1954 3 26 18 15 LESLIE 64.3 51.9 34 119 +1980 10 19 12 3 PATTY 52.5 221.5 89 109 +1984 7 6 18 27 SANDY 15.1 336.8 108 274 +1995 9 12 12 1 TONY 33.2 295.7 98 247 +1978 6 14 12 11 NADINE 65.6 183.2 23 345 +1972 11 24 12 20 FLORENCE 12.3 31.5 72 753 +1974 12 25 6 24 JOYCE 55.3 34.3 135 512 +1992 9 9 6 6 ISAAC 35.7 208.3 121 609 +1959 3 14 6 19 RAFAEL 17.9 77.6 134 834 +1981 12 5 6 17 CHRIS 51.7 208.3 38 577 +1984 4 6 0 10 FLORENCE 31.8 32.0 133 35 +1970 1 14 6 11 VALERIE 26.1 166.6 149 183 +1986 10 11 0 9 FLORENCE 14.3 195.5 100 558 +1992 12 12 18 23 GORDON 37.5 252.9 138 387 +1979 7 2 12 2 HELENE 24.9 120.2 50 574 +1968 9 9 18 28 FLORENCE 27.8 41.3 114 180 +1986 8 14 6 12 DEBBY 41.0 183.5 146 107 +1961 7 5 0 22 OSCAR 9.9 158.3 54 493 +1988 12 11 6 4 CHRIS 24.0 216.5 45 886 +1953 11 18 18 21 PATTY 37.0 107.0 78 501 +1979 9 12 0 7 ALBERTO 16.0 2.1 83 283 +1981 10 5 6 20 MICHAEL 12.1 94.0 138 524 +1959 8 11 12 23 BERYL 58.9 236.5 117 322 +2001 2 9 0 18 SANDY 45.4 287.9 141 160 +1950 6 11 12 23 GORDON 14.2 48.7 45 241 +2001 7 18 12 10 CHRIS 13.9 306.6 87 760 +1957 6 9 12 17 LESLIE 51.9 250.9 43 74 +1998 3 3 12 8 JOYCE 12.2 229.0 69 133 +1975 8 16 18 25 ISAAC 41.2 280.0 22 526 +1997 11 25 12 15 NADINE 48.1 328.9 88 322 +1973 4 4 0 8 GORDON 69.2 267.9 118 362 +1962 4 16 18 4 KIRK 14.6 175.4 52 867 +1985 5 26 18 8 CHRIS 34.8 15.0 98 71 +1984 11 8 0 20 DEBBY 30.3 150.4 90 561 +1960 10 11 6 11 ERNESTO 42.0 241.2 100 338 +1963 1 19 0 9 WILLIAM 56.4 303.4 11 313 +1967 6 19 0 11 ISAAC 28.7 179.9 138 417 +1958 6 1 6 21 PATTY 13.9 92.5 62 707 +1987 5 7 18 25 JOYCE 48.5 324.1 132 12 +1993 1 24 18 5 LESLIE 58.7 181.4 109 845 +2000 9 26 6 8 LESLIE 14.9 212.5 151 162 +1982 4 22 6 2 LESLIE 63.7 114.2 40 113 +1952 9 5 12 9 PATTY 18.3 55.9 26 276 +1968 5 9 12 27 MICHAEL 49.1 107.7 134 509 +2004 4 23 12 1 WILLIAM 56.2 259.7 69 168 +1980 5 4 0 10 WILLIAM 65.0 31.8 52 649 +1975 8 15 0 14 NADINE 15.1 173.2 47 828 +1953 8 6 12 23 TONY 47.9 57.5 24 491 +1950 8 13 18 17 VALERIE 66.3 150.7 118 859 +1971 8 15 12 12 WILLIAM 46.9 202.6 68 596 +1965 8 7 12 13 CHRIS 32.1 78.2 31 728 +1988 6 22 18 4 PATTY 49.6 271.9 157 520 +1970 7 11 6 14 RAFAEL 64.4 200.9 117 346 +1979 11 4 6 5 ERNESTO 32.5 89.6 66 376 +1964 7 19 12 19 NADINE 63.5 76.2 148 338 +1997 1 1 12 17 NADINE 35.8 22.0 95 8 +1952 8 13 6 26 ERNESTO 56.3 128.9 152 112 +2000 7 19 18 24 HELENE 63.6 38.4 161 48 +1996 2 14 18 26 CHRIS 23.4 2.2 106 483 +1963 5 22 6 25 WILLIAM 38.5 312.9 153 569 +1978 11 13 6 5 FLORENCE 65.2 301.6 59 676 +1982 6 11 6 5 RAFAEL 35.7 54.2 96 684 +1951 12 4 0 20 DEBBY 53.8 65.2 29 859 +1991 11 19 18 26 ISAAC 41.2 43.4 82 621 +1954 10 22 12 8 DEBBY 43.7 70.5 119 886 +1969 12 3 6 7 WILLIAM 53.4 75.7 13 547 +1988 5 16 18 11 ALBERTO 45.5 321.6 26 168 +1993 6 22 0 4 ERNESTO 69.9 220.8 149 320 +1968 1 19 0 3 FLORENCE 48.9 280.5 149 862 +1965 6 23 0 25 NADINE 7.5 180.9 64 77 +1956 12 24 18 12 BERYL 45.3 233.8 112 845 +1952 11 15 12 10 TONY 56.8 198.0 69 652 +1996 5 27 0 23 LESLIE 19.4 311.8 136 322 +1985 7 14 18 6 MICHAEL 53.1 250.9 97 755 +1991 2 20 18 12 ERNESTO 30.7 42.2 43 792 +1967 5 20 0 26 RAFAEL 56.6 125.0 147 337 +1988 3 21 12 7 ERNESTO 64.9 4.8 72 325 +1996 8 8 6 13 VALERIE 55.9 317.7 127 314 +2001 1 25 0 28 BERYL 15.5 136.9 50 878 +1955 11 20 12 24 ERNESTO 68.6 305.1 112 446 +1980 2 24 0 28 LESLIE 12.4 309.0 61 608 +1996 9 16 12 23 NADINE 46.9 167.8 49 58 +1958 8 9 18 2 FLORENCE 69.0 43.1 111 520 +1961 9 3 18 17 BERYL 7.3 239.2 150 799 +1972 1 17 12 28 ERNESTO 60.6 199.5 22 720 +1969 7 26 6 20 CHRIS 29.3 7.2 101 339 +1975 9 22 6 20 FLORENCE 43.6 254.7 21 780 +1973 6 14 0 3 VALERIE 30.3 31.2 158 340 +1986 5 23 0 28 FLORENCE 33.8 156.5 152 245 +1954 11 5 12 8 FLORENCE 18.0 114.0 117 228 +1991 9 27 18 11 LESLIE 13.3 3.4 158 657 +1958 5 10 12 6 DEBBY 54.1 176.6 129 483 +1994 11 16 18 15 ERNESTO 57.6 10.9 27 266 +1950 3 23 6 21 PATTY 44.3 316.2 133 519 +1994 7 2 12 19 MICHAEL 22.0 220.9 141 538 +1991 12 19 6 18 VALERIE 35.4 140.7 136 380 +1957 2 21 6 10 KIRK 38.0 237.4 36 147 +1966 8 24 0 26 OSCAR 25.6 333.1 52 46 +1984 7 17 18 21 ISAAC 9.1 352.7 45 329 +1954 2 21 12 20 JOYCE 15.9 249.1 99 706 +1961 8 1 0 5 ISAAC 68.9 159.0 10 734 +1988 6 26 12 25 PATTY 10.1 154.8 104 423 +1976 3 16 18 28 RAFAEL 24.3 300.8 13 342 +1989 10 11 0 8 OSCAR 23.1 200.7 164 694 +1977 7 9 12 27 PATTY 14.6 117.6 117 327 +1958 7 14 6 25 SANDY 23.7 31.1 156 440 +1954 1 2 0 9 RAFAEL 53.6 159.7 77 425 +1962 10 27 0 19 LESLIE 22.8 124.6 82 708 +1999 12 20 6 2 NADINE 22.2 300.2 124 230 +1957 4 17 18 3 LESLIE 55.7 149.0 60 611 +1999 11 22 0 19 DEBBY 16.1 61.3 67 196 +1962 7 24 18 7 RAFAEL 35.6 264.6 114 805 +2001 2 1 18 25 CHRIS 17.3 329.5 18 643 +1976 11 3 12 15 RAFAEL 43.6 255.5 132 183 +1966 9 14 0 11 JOYCE 67.9 292.1 56 520 +1959 10 17 6 25 LESLIE 59.6 125.5 49 65 +1999 10 22 18 8 ERNESTO 41.1 320.5 23 234 +2000 2 11 18 27 ISAAC 9.8 353.3 73 390 +1975 5 7 0 4 ERNESTO 60.1 253.7 83 120 +1956 4 18 18 5 JOYCE 50.3 131.7 90 517 +1957 10 13 12 1 FLORENCE 42.0 213.6 112 806 +1961 1 8 0 12 OSCAR 51.0 57.9 67 875 +2002 8 27 12 4 PATTY 64.3 9.2 86 750 +1981 7 4 12 13 DEBBY 9.7 127.7 63 848 +1987 8 19 0 9 ALBERTO 29.2 133.3 132 427 +1992 2 4 0 25 GORDON 12.1 353.0 135 799 +2002 8 22 0 16 SANDY 54.3 109.0 161 835 +1990 8 28 18 6 DEBBY 7.5 87.4 76 190 +1954 11 2 6 24 CHRIS 50.3 112.8 89 98 +1984 5 11 0 12 CHRIS 23.3 23.7 51 427 +1993 9 24 6 14 OSCAR 9.5 319.0 52 536 +2001 9 8 12 22 BERYL 38.3 232.1 158 21 +1988 4 13 12 27 FLORENCE 67.1 266.3 42 411 +1964 7 19 0 15 LESLIE 43.0 208.5 158 700 +1991 2 8 18 21 RAFAEL 44.4 130.3 76 16 +1951 12 23 12 24 VALERIE 32.8 295.1 153 234 +1972 12 13 6 23 WILLIAM 65.2 171.8 25 463 +1960 5 16 6 27 MICHAEL 10.8 71.1 100 857 +1959 7 4 6 20 WILLIAM 47.4 141.3 104 299 +1976 6 20 0 26 SANDY 43.3 49.3 154 41 +1985 4 4 12 28 ALBERTO 27.5 141.0 119 437 +1958 9 28 6 17 FLORENCE 48.4 306.6 73 381 +1989 5 11 18 27 TONY 11.8 282.9 36 845 +1957 1 27 12 19 HELENE 16.5 234.9 49 272 +1990 2 22 12 15 LESLIE 58.3 206.0 36 840 +1961 2 20 0 26 MICHAEL 38.6 118.5 90 347 +1979 12 3 18 16 TONY 59.2 180.3 34 898 +1996 5 4 0 19 GORDON 12.2 189.6 164 554 +1984 10 20 6 1 LESLIE 15.6 312.1 162 321 +1984 10 23 0 14 HELENE 56.6 236.3 133 224 +2003 5 9 18 1 ALBERTO 40.8 280.3 17 445 +1993 2 25 0 20 GORDON 47.5 78.3 45 830 +1969 8 14 6 22 WILLIAM 17.6 305.2 69 281 +1972 4 6 6 28 OSCAR 29.0 150.6 131 556 +1953 4 9 12 28 DEBBY 31.5 121.2 11 344 +1988 1 20 0 27 OSCAR 19.1 138.1 90 35 +1978 12 22 12 3 SANDY 34.8 10.1 66 458 +1982 4 25 12 22 ERNESTO 47.0 299.2 139 513 +1977 6 25 0 8 ISAAC 47.7 170.3 75 462 +1976 10 19 12 24 WILLIAM 45.0 129.3 72 388 +1989 3 5 12 13 VALERIE 14.6 137.8 76 65 +1954 4 7 6 16 WILLIAM 51.7 64.7 85 681 +1984 2 3 6 10 MICHAEL 68.9 160.2 32 352 +1973 11 8 0 8 HELENE 35.4 332.7 121 221 +1984 6 21 12 20 VALERIE 66.3 62.7 73 443 +1994 1 24 0 20 DEBBY 41.0 230.8 37 891 +1964 9 1 0 28 HELENE 55.3 303.4 138 662 +1965 7 16 12 5 DEBBY 30.0 52.6 24 769 +1999 1 8 0 24 HELENE 11.0 74.1 29 689 +1954 5 22 6 12 CHRIS 15.5 104.7 155 222 +1957 12 23 18 26 JOYCE 57.2 284.2 111 289 +2002 9 4 0 8 KIRK 20.9 162.8 96 777 +1991 2 17 6 25 NADINE 13.8 207.5 124 58 +1995 11 20 6 23 PATTY 32.4 217.3 115 587 +1998 8 21 18 8 HELENE 57.4 81.8 32 256 +1999 12 22 0 18 DEBBY 53.5 182.4 82 731 +1984 2 21 6 24 GORDON 14.2 159.7 101 860 +1980 12 7 6 25 TONY 33.0 40.2 154 447 +1968 4 28 12 26 ERNESTO 17.8 46.7 143 38 +1997 8 3 18 12 TONY 64.6 86.5 78 605 +1960 1 17 12 12 TONY 40.9 330.0 49 204 +1976 5 24 6 6 CHRIS 66.2 126.5 28 253 +1960 11 20 12 1 JOYCE 29.8 334.4 128 274 +1993 10 4 0 3 MICHAEL 32.2 188.1 84 619 +1954 5 7 0 26 BERYL 60.1 118.8 58 140 +1963 10 6 6 10 NADINE 57.2 28.2 91 336 +1977 3 25 12 11 OSCAR 57.2 276.8 164 488 +1963 2 28 6 27 SANDY 44.3 177.8 96 884 +1967 5 7 12 23 ALBERTO 53.2 311.1 132 121 +1957 10 2 18 18 PATTY 35.6 152.3 85 40 +1972 9 6 18 20 FLORENCE 52.0 41.8 62 361 +1957 4 21 6 11 HELENE 7.8 112.7 162 807 +1998 9 10 18 24 WILLIAM 52.7 212.9 49 736 +1986 2 16 12 28 RAFAEL 40.1 69.0 125 802 +1972 11 22 12 26 TONY 65.3 25.7 41 218 +1979 9 2 12 6 BERYL 37.6 100.1 113 44 +1973 10 23 18 18 MICHAEL 30.9 19.9 15 853 +1958 1 12 0 3 LESLIE 48.3 166.1 89 233 +1989 2 26 18 28 LESLIE 11.7 47.9 111 306 +1954 12 16 12 19 GORDON 16.7 326.4 110 836 +1977 12 13 12 3 WILLIAM 45.5 211.4 161 154 +1982 12 25 12 17 WILLIAM 62.2 131.9 31 556 +1995 8 9 18 2 VALERIE 59.4 281.9 43 590 +1998 3 28 6 28 PATTY 58.5 346.7 156 134 +1979 3 21 18 14 CHRIS 45.4 248.0 91 502 +2001 5 26 18 24 LESLIE 61.0 349.8 99 49 +2004 2 18 6 22 NADINE 65.5 308.0 142 608 +1952 11 19 6 15 DEBBY 45.5 204.2 23 580 +1971 12 26 12 12 FLORENCE 28.3 272.7 147 82 +2001 5 2 18 9 JOYCE 51.4 113.5 71 677 +1988 3 24 12 4 MICHAEL 22.9 159.9 21 355 +1981 9 15 12 18 SANDY 38.4 41.0 22 230 +1980 8 24 6 6 BERYL 11.1 316.1 20 763 +1969 11 27 6 18 HELENE 56.6 98.3 63 385 +1982 3 28 18 13 WILLIAM 34.4 239.2 87 784 +2001 12 23 18 25 GORDON 42.4 285.6 108 459 +1984 1 23 6 28 HELENE 36.7 111.3 38 23 +1971 6 23 0 8 DEBBY 28.8 138.5 51 210 +1992 1 2 18 14 DEBBY 30.2 165.6 90 520 +1989 4 9 0 26 FLORENCE 59.8 149.9 154 508 +1991 8 24 18 15 TONY 7.8 271.0 51 439 +1991 3 6 6 20 HELENE 13.2 336.1 37 357 +1958 6 25 0 25 MICHAEL 15.7 184.3 66 637 +1990 12 18 12 19 LESLIE 61.2 214.5 138 99 +1952 10 13 0 25 SANDY 66.4 325.2 13 227 +1971 8 14 18 15 LESLIE 27.8 278.0 146 387 +1990 11 14 18 21 NADINE 37.7 40.8 77 794 +1968 4 1 6 14 SANDY 30.4 64.6 140 696 +1954 3 24 0 25 RAFAEL 10.4 92.8 99 283 +1987 11 12 18 14 KIRK 33.1 355.2 124 772 +2003 5 7 12 3 TONY 40.3 256.8 126 178 +1952 2 18 6 27 HELENE 51.1 48.2 94 808 +1970 4 4 0 9 MICHAEL 26.3 45.2 140 229 +1961 3 24 6 26 DEBBY 50.3 314.9 140 212 +1994 3 12 18 7 CHRIS 62.6 336.2 33 49 +1978 12 19 6 15 CHRIS 39.7 266.8 25 273 +1985 10 26 6 26 TONY 33.8 142.9 132 190 +1978 6 18 18 21 GORDON 29.4 10.5 143 568 +1964 2 2 18 23 JOYCE 59.2 308.7 155 834 +1972 4 13 0 25 TONY 11.5 90.5 14 272 +1965 11 22 12 25 OSCAR 47.9 291.7 110 851 +1959 4 9 0 14 VALERIE 27.2 138.9 35 318 +1971 9 6 6 25 WILLIAM 64.7 281.1 150 713 +1982 5 10 18 25 LESLIE 57.5 333.1 102 564 +1959 11 14 0 5 NADINE 31.9 300.0 136 584 +1987 12 25 6 3 PATTY 48.8 128.6 132 871 +1976 12 16 18 15 CHRIS 12.7 341.8 23 25 +1957 8 24 18 24 FLORENCE 41.9 273.6 85 431 +1978 3 24 0 26 ISAAC 33.3 352.6 117 213 +1978 4 22 12 9 NADINE 26.9 245.0 132 548 +1972 4 3 6 28 WILLIAM 46.5 62.2 74 41 +1992 8 27 6 2 FLORENCE 20.1 214.2 63 614 +1953 9 4 18 27 HELENE 25.4 180.6 35 205 +2004 12 23 18 4 MICHAEL 30.0 54.1 28 683 +1957 3 27 0 19 LESLIE 9.5 329.0 94 397 +1974 7 16 18 28 SANDY 68.5 311.0 81 705 +1964 8 20 18 28 MICHAEL 57.1 97.5 16 551 +1979 12 20 6 22 KIRK 47.5 62.8 152 739 +1994 2 27 18 12 ISAAC 29.8 2.8 55 371 +1994 11 9 0 23 CHRIS 33.5 257.9 13 38 +1985 2 8 0 24 RAFAEL 7.2 299.9 67 508 +1982 2 18 0 6 MICHAEL 11.1 298.8 127 197 +1964 6 23 12 4 VALERIE 28.2 163.1 109 186 +1983 5 4 6 4 SANDY 64.8 326.7 149 753 +1958 3 23 6 15 JOYCE 62.4 309.7 103 264 +1951 3 21 6 27 WILLIAM 49.3 73.8 43 648 +1964 6 8 12 4 SANDY 36.9 316.0 127 845 +1965 7 6 18 20 LESLIE 40.1 77.0 10 568 +2002 4 7 12 3 BERYL 61.4 49.2 24 14 +1972 3 14 18 9 LESLIE 28.5 211.6 79 199 +1958 5 18 12 9 TONY 55.3 80.6 13 374 +1987 12 28 6 14 ERNESTO 41.3 109.0 68 87 +1962 5 2 6 22 PATTY 38.0 71.0 145 451 +1953 3 14 12 27 ERNESTO 47.7 120.6 138 781 +1990 3 10 0 20 TONY 35.0 55.1 37 478 +1983 4 1 18 14 MICHAEL 29.4 58.7 164 37 +1983 6 27 0 10 PATTY 64.7 41.7 126 554 +1963 3 17 6 9 ALBERTO 69.8 112.9 149 779 +1960 10 3 18 14 VALERIE 17.7 177.5 11 778 +1986 8 13 6 15 PATTY 34.2 121.8 39 885 +1970 4 26 6 24 BERYL 56.6 257.8 146 46 +1986 7 13 0 5 ALBERTO 9.1 335.7 16 580 +1953 1 11 6 9 PATTY 55.4 221.8 98 420 +1982 11 4 6 14 ERNESTO 35.4 96.6 13 93 +1972 11 21 18 13 JOYCE 30.4 274.0 71 733 +1956 6 6 0 21 JOYCE 40.2 208.1 133 409 +2000 1 27 12 21 DEBBY 59.6 267.5 44 249 +1984 12 27 6 26 LESLIE 48.1 262.8 85 454 +1968 10 23 6 6 MICHAEL 24.2 276.3 28 768 +1992 6 18 0 6 RAFAEL 12.3 57.0 111 514 +1972 5 24 18 25 RAFAEL 38.6 99.9 150 15 +1956 3 19 0 24 MICHAEL 47.2 90.9 114 339 +1966 2 25 6 2 JOYCE 25.8 314.2 22 346 +1953 5 13 0 10 KIRK 37.4 133.2 74 204 +1958 10 23 0 11 SANDY 67.0 166.6 28 692 +2000 11 4 18 6 NADINE 16.4 224.2 35 11 +1966 7 13 12 13 ERNESTO 56.4 178.2 53 716 +1969 6 11 0 9 PATTY 9.5 348.5 106 401 +1978 3 13 18 25 LESLIE 23.7 242.5 35 298 +1984 10 5 6 23 HELENE 20.6 43.8 132 899 +1992 6 5 6 1 ISAAC 10.6 45.6 156 308 +1977 11 2 6 21 KIRK 35.9 244.2 25 496 +1972 3 17 12 3 RAFAEL 54.6 6.4 128 790 +1952 8 9 18 23 OSCAR 38.1 337.6 33 295 +1953 12 12 0 20 HELENE 69.4 213.9 62 699 +1982 8 28 0 14 CHRIS 17.1 305.4 148 182 +1996 12 16 12 12 GORDON 42.5 141.4 127 669 +1958 6 20 6 23 PATTY 25.3 163.6 164 853 +1960 12 15 18 14 GORDON 14.5 27.9 125 296 +1985 1 26 6 21 NADINE 50.8 108.3 37 686 +1961 4 12 6 28 LESLIE 61.6 80.5 37 332 +1962 9 21 18 2 PATTY 63.1 27.7 97 419 +1989 4 9 0 2 TONY 29.3 175.6 32 312 +1993 8 28 18 28 PATTY 15.1 129.3 14 650 +2003 2 24 12 4 ERNESTO 43.2 72.1 95 809 +1976 6 1 0 20 JOYCE 61.3 183.4 17 495 +1971 12 18 12 4 BERYL 11.4 80.9 110 827 +1951 6 19 0 24 NADINE 31.4 128.9 80 717 +1996 12 22 6 16 VALERIE 19.0 54.3 156 267 +1989 8 26 0 12 LESLIE 18.8 82.6 105 205 +1974 11 9 0 20 BERYL 44.0 178.7 27 461 +1967 8 2 0 22 KIRK 64.6 189.1 108 203 +1958 1 28 0 26 WILLIAM 54.2 185.1 51 177 +2002 6 3 18 18 NADINE 38.1 83.1 37 394 +1987 2 24 6 11 KIRK 37.4 22.5 138 353 +2001 6 13 0 19 MICHAEL 44.2 1.1 131 350 +1981 3 12 12 1 JOYCE 61.4 303.8 156 525 +1953 1 17 18 13 WILLIAM 11.0 37.7 93 679 +1951 10 7 6 6 MICHAEL 42.6 143.2 20 139 +1984 10 19 18 10 ALBERTO 63.0 212.2 57 554 +1979 5 6 6 6 DEBBY 8.1 128.9 56 735 +1991 10 26 18 16 RAFAEL 23.8 200.5 162 309 +1952 3 6 6 4 ALBERTO 33.4 110.2 115 831 +1953 3 25 0 2 ERNESTO 30.9 247.8 163 362 +2003 4 3 18 24 LESLIE 41.5 245.1 61 358 +1951 11 14 6 20 SANDY 9.5 102.3 101 798 +1981 9 24 6 26 FLORENCE 59.4 317.1 41 878 +1987 4 21 6 1 LESLIE 15.9 254.8 87 297 +1973 1 16 18 9 VALERIE 16.6 173.9 73 86 +1961 4 27 0 25 JOYCE 42.0 216.6 111 760 +1973 3 1 0 20 VALERIE 62.6 283.3 56 669 +1951 4 9 12 1 WILLIAM 16.8 146.4 73 251 +1970 4 6 18 7 LESLIE 44.4 191.9 62 214 +1996 8 5 6 13 ERNESTO 37.1 19.2 97 761 +1975 2 11 6 24 NADINE 38.3 230.2 10 317 +1994 7 15 12 23 NADINE 33.1 307.9 122 267 +1996 8 18 0 11 MICHAEL 22.6 143.9 22 34 +2001 3 18 0 12 DEBBY 22.7 256.3 22 185 +2000 1 17 12 14 VALERIE 10.7 66.6 16 198 +2002 10 24 0 1 TONY 57.1 237.3 48 519 +1970 9 10 12 5 CHRIS 66.8 357.7 76 455 +1951 7 8 0 10 ALBERTO 27.2 27.3 105 338 +1977 10 1 18 22 KIRK 17.2 248.6 34 372 +1971 4 24 6 27 PATTY 50.9 260.5 138 156 +1990 6 15 6 12 VALERIE 39.3 64.4 60 519 +1968 4 5 18 11 ALBERTO 20.8 22.7 149 549 +1986 1 24 6 21 ALBERTO 41.7 161.6 46 146 +1966 10 25 12 2 ISAAC 58.2 113.3 19 96 +2001 9 15 18 19 KIRK 68.9 167.7 94 35 +1978 12 25 6 23 NADINE 38.4 149.0 136 69 +1957 4 27 18 5 HELENE 20.6 214.2 93 837 +2004 6 23 18 26 LESLIE 54.2 111.5 47 669 +1971 4 21 0 16 ERNESTO 11.1 113.5 103 261 +1950 7 20 0 21 ALBERTO 32.9 311.8 126 759 +1999 6 27 12 13 LESLIE 64.3 52.7 87 857 +1967 2 19 18 13 WILLIAM 23.5 238.7 116 132 +1985 12 13 6 23 SANDY 11.0 336.1 161 64 +2003 3 26 0 11 MICHAEL 16.2 285.9 48 483 +2001 9 26 6 28 ALBERTO 59.9 32.7 68 244 +1994 1 22 0 27 MICHAEL 61.7 43.8 19 369 +1967 2 27 12 22 KIRK 67.7 5.4 97 97 +1957 9 13 6 22 ISAAC 28.3 168.3 82 638 +1966 7 15 18 13 VALERIE 69.0 170.3 54 397 +1950 5 16 6 17 PATTY 56.1 219.0 142 735 +2000 3 13 12 3 FLORENCE 45.5 156.1 59 248 +1981 6 17 12 1 ISAAC 40.9 181.7 59 371 +1984 9 27 12 19 RAFAEL 48.0 293.3 112 323 +2000 1 26 12 17 JOYCE 61.6 158.7 129 68 +1960 8 5 12 2 RAFAEL 64.4 95.8 130 144 +1970 9 26 0 2 PATTY 39.1 249.1 153 317 +1972 6 12 0 9 KIRK 38.0 162.0 78 223 +1987 3 13 18 23 JOYCE 23.7 11.8 63 784 +1952 7 16 6 12 TONY 42.9 288.4 77 151 +2000 12 23 12 12 VALERIE 16.1 351.2 135 220 +1973 8 22 18 24 PATTY 24.1 203.3 155 237 +1951 8 9 18 6 FLORENCE 13.3 291.4 132 223 +2002 6 25 0 24 NADINE 28.9 353.5 156 534 +1973 7 22 18 6 TONY 18.7 168.2 140 543 +1987 8 5 0 24 OSCAR 69.3 112.5 18 649 +1957 8 21 12 26 HELENE 22.1 262.5 113 707 +1970 6 6 12 3 ISAAC 56.5 299.1 13 520 +1997 6 23 0 9 TONY 32.9 216.4 95 413 +1975 6 16 18 8 GORDON 55.9 178.3 135 588 +1970 11 12 0 28 LESLIE 13.3 225.3 86 311 +1990 11 24 0 21 NADINE 12.2 182.8 159 113 +1975 3 1 0 11 ERNESTO 56.1 339.3 52 246 +1978 2 5 0 1 CHRIS 17.5 290.4 116 784 +1998 2 18 6 23 CHRIS 13.5 171.1 35 202 +1995 1 4 12 4 MICHAEL 17.3 223.4 81 50 +1999 9 19 12 11 ALBERTO 31.1 266.5 131 542 +1961 1 15 18 11 CHRIS 15.7 283.1 108 9 +1984 9 14 12 21 PATTY 59.4 216.7 127 104 +1991 3 15 12 14 OSCAR 15.9 243.2 65 815 +1979 11 14 6 24 PATTY 64.3 24.7 37 645 +1971 2 20 0 1 KIRK 69.9 34.9 108 352 +1998 1 18 0 19 NADINE 50.2 61.5 30 260 +1987 3 12 6 7 SANDY 10.1 20.1 91 310 +1956 6 5 0 24 CHRIS 18.8 303.7 65 290 +1989 11 17 6 27 PATTY 62.6 219.8 14 585 +1995 4 23 0 22 ERNESTO 22.3 247.8 14 503 +2004 5 14 12 19 VALERIE 27.5 318.8 144 252 +2003 7 25 0 4 ALBERTO 39.1 42.6 14 186 +1967 5 10 6 16 VALERIE 56.2 58.5 126 844 +2003 1 8 0 5 ALBERTO 43.3 188.6 44 353 +1996 4 7 12 27 FLORENCE 54.0 214.4 139 411 +1991 7 2 6 5 CHRIS 26.4 317.1 128 110 +1991 12 28 18 24 PATTY 17.0 58.5 18 322 +1985 8 28 6 13 DEBBY 65.6 269.5 102 124 +1952 11 7 6 12 HELENE 59.8 194.9 72 355 +1952 8 9 0 6 BERYL 46.5 266.8 49 475 +1995 2 11 12 20 VALERIE 18.4 33.9 57 472 +1992 5 21 6 8 PATTY 56.4 194.1 44 883 +1958 3 6 18 24 ALBERTO 29.9 32.0 126 602 +1993 3 18 6 7 TONY 25.4 181.5 68 538 +1965 7 23 12 25 TONY 50.2 357.8 94 47 +1959 4 26 12 25 VALERIE 48.0 7.3 83 385 +1962 7 26 18 12 PATTY 45.9 217.1 20 729 +2001 3 15 6 13 WILLIAM 30.3 240.3 24 238 +1966 12 3 6 6 ISAAC 27.4 203.6 75 184 +1979 8 20 0 8 VALERIE 44.2 236.5 135 426 +1975 11 24 6 20 HELENE 47.8 323.7 150 871 +1956 5 22 6 25 ERNESTO 35.9 182.9 21 125 +1971 7 19 12 11 SANDY 23.9 190.0 63 609 +2003 4 11 18 13 HELENE 16.3 317.4 36 669 +2001 9 14 0 9 MICHAEL 59.2 181.8 55 309 +1983 5 20 18 21 ALBERTO 49.4 202.3 12 542 +1979 9 16 0 5 WILLIAM 25.5 160.3 75 122 +1967 8 12 18 16 HELENE 61.4 69.1 156 360 +1974 12 27 6 3 TONY 10.0 335.1 10 145 +2000 1 20 18 16 TONY 37.4 4.7 156 860 +1993 12 9 18 8 SANDY 27.8 52.2 37 269 +1998 3 24 18 26 MICHAEL 44.4 212.9 77 33 +1969 4 26 6 5 SANDY 51.2 86.6 137 213 +2001 8 16 12 22 BERYL 9.1 307.7 18 294 +1992 4 6 12 28 ISAAC 31.8 101.3 163 797 +1990 10 10 12 11 HELENE 24.0 78.8 121 65 +1969 1 1 18 8 VALERIE 66.5 139.6 12 726 +1980 9 6 12 14 NADINE 14.6 205.4 104 294 +1952 4 21 12 28 GORDON 55.5 156.7 68 417 +1954 2 25 12 5 RAFAEL 25.7 225.7 50 394 +1986 4 8 18 6 SANDY 63.4 104.5 136 241 +1971 6 7 6 22 MICHAEL 52.2 64.1 108 208 +1992 9 2 6 3 ISAAC 34.3 224.7 16 821 +1981 12 13 0 6 WILLIAM 23.9 338.6 116 745 +1983 5 3 18 20 PATTY 63.8 310.7 72 220 +1997 8 3 0 27 ISAAC 23.1 262.4 102 415 +1960 3 13 0 8 JOYCE 11.5 258.4 152 385 +1994 9 21 0 17 NADINE 7.6 220.4 116 44 +1967 3 5 0 17 FLORENCE 58.7 325.3 42 462 +1991 12 9 0 17 WILLIAM 62.8 295.1 132 681 +1962 8 23 0 11 JOYCE 31.3 279.3 60 158 +2002 9 4 6 5 SANDY 10.7 190.1 140 680 +1990 6 7 18 8 ISAAC 45.2 11.3 59 515 +1979 2 16 18 23 MICHAEL 60.9 338.7 124 384 +2001 6 8 6 23 VALERIE 48.5 203.5 60 730 +2000 5 3 12 12 NADINE 50.3 276.7 63 314 +1967 3 11 18 4 VALERIE 51.3 251.4 105 315 +1980 3 12 0 2 SANDY 7.1 1.2 107 38 +1951 10 9 18 14 NADINE 27.8 324.0 25 398 +1996 9 15 0 28 BERYL 67.6 257.8 90 203 +1984 3 2 18 28 OSCAR 55.4 73.2 113 857 +1952 8 27 12 20 RAFAEL 29.4 51.2 129 642 +1967 2 8 0 24 OSCAR 44.6 234.8 124 505 +1973 10 28 12 24 CHRIS 63.0 109.6 73 172 +1988 10 11 18 14 LESLIE 11.9 333.4 68 676 +1988 5 24 12 2 CHRIS 59.1 155.7 59 478 +1988 7 25 6 8 LESLIE 21.1 214.1 52 303 +1998 5 8 0 13 ERNESTO 19.6 168.3 51 693 +1979 2 18 6 9 NADINE 61.7 103.6 105 717 +1962 7 9 0 22 MICHAEL 39.9 217.9 153 711 +1978 1 21 18 28 VALERIE 29.1 292.5 146 556 +1997 8 13 12 16 LESLIE 21.0 145.2 74 84 +1961 1 21 6 20 MICHAEL 15.1 102.9 90 43 +1995 6 6 18 11 JOYCE 52.7 325.3 94 690 +1985 5 16 18 12 BERYL 37.6 95.7 149 828 +1982 1 24 18 26 LESLIE 62.5 38.9 72 768 +1979 1 8 18 24 ALBERTO 39.7 7.0 20 360 +1950 12 11 12 27 WILLIAM 60.3 297.0 26 667 +1950 1 13 0 5 DEBBY 24.3 293.7 84 412 +1953 10 13 6 15 TONY 69.1 51.9 78 45 +1975 6 24 18 16 WILLIAM 62.4 155.3 161 430 +1990 4 15 6 8 NADINE 13.0 203.7 84 129 +1994 4 13 6 24 MICHAEL 64.1 129.5 142 314 +1983 6 21 0 13 OSCAR 20.2 81.2 113 896 +1974 12 6 12 22 TONY 56.0 320.8 87 253 +1975 7 18 6 25 PATTY 35.1 2.1 10 858 +1955 11 20 18 8 NADINE 61.0 71.6 64 776 +1976 12 12 12 4 GORDON 63.5 48.2 12 714 +1990 3 27 18 19 PATTY 66.2 188.5 131 220 +1979 12 19 6 8 LESLIE 47.0 352.2 116 201 +2004 1 15 12 18 PATTY 23.0 9.2 131 702 +1987 9 23 6 26 ALBERTO 9.4 49.5 41 828 +1996 6 16 6 23 HELENE 37.0 313.3 69 754 +1977 7 18 12 26 TONY 51.1 152.3 155 322 +1987 2 14 6 22 DEBBY 59.5 120.0 120 29 +1993 10 13 18 27 ERNESTO 60.6 232.8 131 653 +2000 8 9 18 22 BERYL 30.3 213.7 43 235 +1997 6 8 12 24 SANDY 60.6 212.7 70 325 +1994 2 11 0 13 OSCAR 60.8 242.9 144 657 +1950 1 24 18 16 WILLIAM 36.0 128.2 43 507 +1950 8 25 12 19 CHRIS 35.7 215.0 77 894 +1979 2 27 12 28 RAFAEL 61.3 235.8 36 184 +1998 12 24 12 18 JOYCE 67.9 123.7 47 841 +1999 11 17 6 4 CHRIS 15.8 251.6 158 473 +1985 3 7 0 26 PATTY 69.7 251.1 56 528 +1987 9 26 12 7 GORDON 12.4 32.7 48 157 +1960 3 7 6 24 NADINE 64.0 244.9 60 185 +1951 11 14 18 27 KIRK 42.3 81.9 67 37 +1977 3 12 0 15 VALERIE 29.9 35.6 133 115 +1966 3 22 12 24 NADINE 60.9 321.3 91 743 +1952 8 1 12 26 PATTY 31.6 258.2 40 148 +1950 2 28 0 15 KIRK 36.6 109.9 147 541 +1974 6 2 0 7 RAFAEL 33.6 32.7 13 177 +1979 9 25 12 12 KIRK 29.1 265.5 102 427 +1969 7 16 12 3 KIRK 51.0 354.7 115 160 +1964 11 11 0 3 LESLIE 10.9 222.9 131 353 +1956 12 21 12 1 LESLIE 37.7 324.7 42 245 +1981 3 11 18 11 GORDON 25.7 6.3 122 437 +2001 1 24 12 3 PATTY 55.4 41.8 89 79 +1950 7 9 12 11 ISAAC 23.1 111.8 27 859 +1971 7 3 0 21 DEBBY 38.4 49.3 83 31 +1966 6 23 0 18 PATTY 11.0 31.1 43 347 +1974 6 7 6 12 JOYCE 43.5 39.3 69 776 +1951 4 1 6 5 ISAAC 34.9 142.1 12 257 +1977 1 23 0 25 BERYL 24.6 356.3 87 713 +1962 2 15 12 1 FLORENCE 33.6 352.2 128 422 +1956 6 8 12 17 LESLIE 13.4 143.7 102 569 +1992 11 10 0 21 NADINE 40.2 122.8 59 376 +1998 1 20 6 8 OSCAR 51.9 255.5 25 233 +1972 8 20 6 14 OSCAR 55.1 158.5 80 896 +1967 11 8 12 18 LESLIE 52.4 156.8 60 759 +1955 7 21 18 22 ALBERTO 63.5 331.4 90 485 +1966 2 2 6 14 TONY 67.5 15.3 31 605 +1979 9 22 6 15 SANDY 7.9 251.1 81 355 +1966 4 25 6 28 VALERIE 61.0 302.0 155 493 +1980 12 5 0 9 PATTY 46.7 93.8 115 553 +1983 4 23 18 6 DEBBY 61.1 199.8 129 732 +1981 2 9 12 17 TONY 26.5 8.8 125 670 +1995 11 28 6 25 GORDON 46.9 93.5 82 698 +1960 1 25 18 12 TONY 47.5 133.5 69 674 +2004 11 4 0 23 ALBERTO 24.5 304.3 66 342 +1998 4 2 18 5 HELENE 33.5 291.7 50 131 +1974 9 17 18 16 FLORENCE 58.9 208.6 74 408 +1966 12 1 12 13 DEBBY 27.5 40.0 149 773 +1972 5 16 0 19 VALERIE 49.3 245.0 62 119 +1981 6 18 12 18 FLORENCE 56.2 118.6 136 74 +1970 10 18 12 4 ALBERTO 47.3 58.3 12 798 +1958 9 15 12 25 NADINE 41.0 98.1 152 460 +1988 3 3 18 14 KIRK 64.8 326.1 103 747 +1989 4 1 18 18 HELENE 32.7 269.1 58 538 +1967 8 19 18 2 ALBERTO 54.8 123.1 21 429 +1950 4 4 18 19 FLORENCE 28.9 31.7 39 877 +2004 2 13 6 17 OSCAR 49.7 289.4 13 242 +1972 11 2 18 28 ALBERTO 28.5 195.5 160 207 +1995 10 9 18 9 LESLIE 16.2 31.2 93 761 +1984 2 19 18 28 ALBERTO 11.6 26.2 157 59 +1970 7 11 18 18 RAFAEL 48.3 92.2 77 539 +1967 5 12 6 9 FLORENCE 8.6 61.6 34 714 +1977 9 10 12 28 WILLIAM 31.6 271.0 62 851 +1985 7 21 18 10 FLORENCE 14.6 174.5 30 364 +1968 5 8 12 2 CHRIS 59.8 18.9 157 558 +1965 11 28 18 23 DEBBY 12.3 163.7 136 363 +1963 2 17 12 20 KIRK 8.5 106.8 155 827 +1977 11 27 18 14 OSCAR 62.6 60.1 95 328 +1972 6 13 0 24 MICHAEL 55.9 122.1 65 136 +1953 12 8 0 27 BERYL 62.8 144.0 16 380 +1991 11 28 18 27 JOYCE 37.7 242.7 149 326 +1963 6 5 18 18 MICHAEL 50.1 220.4 128 538 +1960 7 5 12 9 SANDY 15.0 132.3 69 143 +1990 6 21 6 2 MICHAEL 27.5 102.7 35 397 +2000 4 16 18 14 HELENE 10.3 246.6 20 16 +1994 1 14 0 10 HELENE 37.9 93.6 145 152 +1995 5 5 12 12 ISAAC 8.5 161.2 33 156 +1977 8 10 6 6 ALBERTO 43.7 38.2 22 721 +1961 6 2 0 2 VALERIE 60.9 120.9 123 825 +1958 3 9 0 14 ERNESTO 53.3 159.6 10 51 +1976 9 13 6 19 JOYCE 24.0 108.5 76 285 +1968 2 2 6 11 FLORENCE 47.4 302.9 145 675 +1963 10 18 12 20 SANDY 26.3 168.4 123 430 +1953 6 11 0 19 ISAAC 43.7 127.4 127 681 +1982 10 14 6 25 JOYCE 55.4 164.0 71 735 +1963 2 25 6 28 PATTY 56.7 208.6 112 190 +1950 3 16 18 27 JOYCE 63.7 277.1 73 683 +1957 8 26 18 2 MICHAEL 50.7 92.4 80 578 +1986 9 7 6 3 FLORENCE 64.1 63.2 39 787 +1973 2 1 12 28 BERYL 9.5 345.9 137 548 +1977 2 11 12 1 TONY 62.2 246.1 133 384 +1952 10 27 12 28 NADINE 56.9 265.6 30 848 +1993 12 13 0 19 LESLIE 39.9 184.7 71 736 +1950 2 14 18 12 LESLIE 45.8 278.2 100 279 +1970 4 11 18 26 BERYL 59.8 332.9 97 852 +1956 7 15 18 25 ISAAC 33.1 353.1 162 215 +1953 6 24 6 12 ISAAC 47.3 353.1 41 2 +1993 5 25 18 24 GORDON 7.6 246.5 14 745 +1994 5 15 18 2 CHRIS 34.4 36.1 59 776 +1964 12 10 6 11 CHRIS 16.2 308.4 131 381 +1969 7 24 18 25 HELENE 53.0 183.8 84 82 +2003 11 13 18 17 SANDY 58.4 89.2 57 477 +1950 10 17 0 27 ISAAC 51.8 346.8 21 254 +1968 6 7 18 25 PATTY 61.5 333.8 87 155 +1973 9 16 0 6 DEBBY 62.5 16.3 155 876 +1965 7 2 18 28 ISAAC 12.7 343.9 132 743 +1983 3 26 0 21 HELENE 69.2 227.7 54 856 +1996 12 21 18 22 PATTY 48.7 263.0 26 73 +1979 9 4 12 12 PATTY 43.9 161.3 136 725 +1968 2 8 6 21 ISAAC 65.2 86.2 132 638 +1987 8 6 18 9 ISAAC 8.1 261.1 140 71 +1965 3 4 6 14 DEBBY 61.7 191.1 143 830 +1963 6 28 18 23 RAFAEL 35.2 92.8 100 175 +1964 1 11 6 21 BERYL 48.1 40.2 122 807 +1977 8 23 6 2 FLORENCE 46.6 100.5 14 229 +1967 4 6 0 2 SANDY 8.4 157.3 12 749 +2004 5 14 0 20 VALERIE 15.8 30.9 72 195 +1965 1 23 6 8 HELENE 65.8 270.9 55 858 +2004 12 22 6 22 NADINE 32.2 117.6 44 120 +1952 3 5 0 16 ALBERTO 55.3 5.5 102 296 +1952 11 18 18 3 WILLIAM 40.1 23.5 80 686 +1991 10 9 0 10 GORDON 62.3 29.5 21 68 +1981 1 4 18 7 ERNESTO 50.6 125.9 39 175 +1976 11 26 18 13 MICHAEL 45.9 264.5 136 791 +1991 6 4 12 7 ERNESTO 41.3 36.4 91 738 +1964 9 12 12 2 HELENE 40.9 1.9 27 398 +1987 5 11 6 27 CHRIS 14.6 342.5 48 590 +1958 9 12 0 6 RAFAEL 32.5 125.8 84 540 +2004 6 8 12 21 ERNESTO 43.4 85.7 84 885 +2001 3 22 6 16 MICHAEL 42.3 306.9 88 732 +1952 11 23 0 17 KIRK 66.1 249.5 79 344 +1976 1 9 6 23 HELENE 35.0 44.4 19 59 +1952 9 27 6 3 DEBBY 61.9 333.6 67 749 +1962 6 23 0 6 FLORENCE 20.0 271.4 140 28 +1981 9 28 12 5 GORDON 23.2 264.7 136 626 +1972 9 19 18 4 GORDON 12.9 64.4 60 857 +1960 10 13 6 19 NADINE 35.8 199.8 135 497 +1978 12 21 0 27 ALBERTO 63.3 176.5 149 731 +1959 8 25 0 14 ALBERTO 57.4 142.3 148 572 +2002 12 21 6 24 CHRIS 48.2 241.2 91 840 +1983 12 17 12 26 VALERIE 12.6 287.4 36 229 +1961 4 27 6 26 SANDY 64.6 57.3 70 654 +1956 5 15 12 8 OSCAR 60.7 356.8 131 391 +1985 5 22 12 3 HELENE 23.6 228.4 92 644 +1992 8 22 0 22 WILLIAM 50.9 207.1 32 202 +1994 2 24 12 21 PATTY 50.2 205.1 114 509 +2002 4 22 0 21 RAFAEL 10.2 266.4 150 683 +1959 9 17 0 6 JOYCE 29.1 141.8 95 197 +1987 2 13 18 1 ERNESTO 55.1 112.1 39 664 +2001 12 19 18 14 ALBERTO 46.7 195.5 131 60 +1971 9 26 0 3 FLORENCE 27.6 190.9 153 219 +1968 11 10 12 9 ISAAC 51.9 268.9 61 861 +1953 7 15 18 22 NADINE 45.8 334.8 84 418 +1967 2 17 6 23 PATTY 46.6 347.6 92 537 +1955 6 12 12 18 ERNESTO 34.9 186.2 58 899 +2004 10 3 6 15 LESLIE 39.3 181.1 101 665 +1967 11 3 18 8 KIRK 63.2 347.1 164 475 +1967 7 25 6 5 LESLIE 20.7 44.2 16 641 +1983 7 27 0 11 CHRIS 49.4 238.7 47 861 +1995 6 4 6 10 VALERIE 22.8 317.8 80 237 +1975 12 15 6 23 NADINE 11.0 356.2 28 618 +1961 1 8 12 5 ERNESTO 14.7 321.5 141 187 +1984 7 1 12 4 KIRK 59.9 219.9 38 723 +1974 1 7 18 9 OSCAR 61.0 70.8 91 546 +2000 7 27 12 5 PATTY 63.0 335.5 15 848 +1990 7 19 6 21 SANDY 41.9 317.9 106 533 +1964 12 7 18 1 SANDY 59.2 188.7 120 143 +1963 6 1 0 8 LESLIE 54.3 98.9 31 366 +1951 2 18 0 2 PATTY 25.3 169.8 34 587 +1972 11 6 12 10 PATTY 49.5 160.2 106 41 +1966 5 25 0 19 LESLIE 34.5 328.9 149 523 +1955 8 6 18 19 OSCAR 26.9 38.7 17 257 +1987 7 26 18 17 ALBERTO 8.2 268.4 151 551 +1993 3 5 0 15 SANDY 34.0 57.8 147 47 +1988 9 19 0 16 FLORENCE 65.2 119.4 37 282 +1964 12 13 0 17 GORDON 35.3 23.0 10 208 +1959 8 11 12 9 DEBBY 67.2 274.7 86 415 +2004 4 24 0 7 MICHAEL 21.0 336.5 45 730 +1986 5 2 0 9 ISAAC 69.6 114.0 163 547 +1954 11 17 12 7 HELENE 59.2 264.4 80 242 +1981 1 8 12 16 NADINE 59.6 21.2 132 333 +1952 6 12 0 21 CHRIS 54.5 311.9 82 627 +1955 4 13 6 17 SANDY 54.0 219.0 95 544 +1964 4 3 6 9 ISAAC 23.7 125.3 91 565 +1970 7 16 6 11 ERNESTO 28.3 157.7 52 480 +1956 12 21 18 27 HELENE 12.2 302.3 21 650 +1969 2 9 12 11 LESLIE 66.7 163.4 127 460 +1968 6 16 18 14 HELENE 41.6 317.9 144 97 +1979 8 4 0 6 RAFAEL 23.6 10.8 31 89 +1953 5 17 0 12 TONY 28.3 343.9 157 875 +1972 2 19 18 13 NADINE 50.7 32.7 13 237 +1982 3 25 18 3 PATTY 48.3 65.7 45 297 +1960 9 25 12 9 NADINE 40.5 163.8 127 467 +1952 4 7 12 3 MICHAEL 45.4 48.6 65 818 +1969 12 12 12 9 MICHAEL 22.9 50.3 154 844 +1957 6 24 0 26 DEBBY 18.7 225.8 48 487 +1999 1 12 0 28 DEBBY 26.5 297.1 140 225 +1981 6 7 6 1 NADINE 40.1 329.7 122 476 +1971 1 7 0 23 SANDY 54.2 93.3 57 474 +1962 3 27 12 1 ERNESTO 25.7 65.7 33 765 +2004 9 7 18 26 VALERIE 26.4 116.7 104 382 +1975 1 10 18 27 GORDON 30.9 338.2 124 410 +1976 1 24 12 11 HELENE 60.6 157.9 145 136 +1998 9 2 12 3 VALERIE 61.1 199.8 20 360 +1951 5 20 18 1 TONY 61.4 64.9 16 751 +2002 5 26 12 7 TONY 50.0 100.0 152 473 +1960 12 21 18 5 NADINE 15.2 30.1 53 770 +1999 4 25 12 17 ERNESTO 15.4 82.4 114 670 +1996 6 28 6 6 ERNESTO 29.8 110.3 124 569 +1954 9 28 18 3 VALERIE 11.8 101.1 84 367 +1993 5 12 6 12 KIRK 32.6 310.9 69 435 +1991 3 22 6 6 VALERIE 55.9 87.7 123 778 +1996 3 27 6 9 GORDON 14.0 190.9 69 57 +1980 12 4 12 3 JOYCE 55.3 12.0 28 473 +1953 2 8 6 27 KIRK 57.5 147.0 79 470 +1961 2 21 6 6 SANDY 58.4 48.8 149 88 +1986 6 19 0 9 FLORENCE 54.2 187.4 153 22 +1980 8 19 12 26 GORDON 33.9 58.8 41 577 +1992 10 28 12 12 SANDY 9.9 208.3 151 277 +1977 9 16 12 21 WILLIAM 18.4 251.4 114 312 +2000 9 14 6 10 NADINE 23.4 241.2 20 41 +1968 2 9 6 22 ALBERTO 22.1 286.3 16 61 +2002 11 26 0 1 PATTY 10.0 60.7 102 717 +1996 10 3 0 28 SANDY 15.3 80.2 164 820 +1984 9 9 12 19 VALERIE 47.7 6.1 124 560 +1951 6 10 6 13 RAFAEL 64.1 29.6 18 828 +1980 4 22 6 18 LESLIE 66.9 1.2 12 898 +1951 8 19 18 17 ALBERTO 26.3 146.8 30 284 +1998 10 23 6 28 FLORENCE 32.5 178.7 124 705 +1961 2 25 6 7 PATTY 62.4 220.8 12 332 +1978 2 18 18 18 ERNESTO 19.4 147.8 33 220 +1996 9 7 18 19 WILLIAM 31.2 220.1 137 357 +1979 5 16 6 6 HELENE 61.6 87.6 160 467 +1979 12 13 18 14 DEBBY 8.6 267.5 95 213 +1987 10 22 6 27 MICHAEL 21.2 144.8 147 275 +1951 11 13 18 26 NADINE 18.4 303.2 86 681 +1962 10 18 0 3 BERYL 17.9 120.4 112 276 +1991 12 17 0 13 NADINE 48.8 115.7 142 200 +1964 8 12 18 14 CHRIS 56.4 274.5 132 720 +1988 10 10 12 14 ISAAC 62.0 188.2 17 262 +2002 8 17 18 16 NADINE 10.4 178.2 77 70 +1968 4 10 18 6 HELENE 40.3 114.7 59 775 +1976 6 23 6 25 SANDY 66.3 159.5 56 780 +1965 11 25 12 26 ISAAC 36.8 292.3 81 140 +1963 5 14 18 5 DEBBY 43.6 137.4 109 125 +1961 5 6 18 1 ERNESTO 63.4 251.3 74 574 +1968 8 21 6 13 BERYL 53.9 130.3 125 697 +1968 1 13 18 5 MICHAEL 23.8 179.2 37 457 +1950 6 3 18 21 LESLIE 43.6 223.2 52 758 +1971 6 9 12 20 KIRK 43.4 327.1 103 538 +1989 2 1 12 24 SANDY 39.8 331.9 25 211 +1995 6 11 6 12 DEBBY 7.3 73.3 93 714 +1954 12 20 12 20 WILLIAM 58.2 223.0 139 477 +1958 6 11 6 15 OSCAR 65.5 183.3 80 526 +1968 7 24 6 2 BERYL 56.2 144.6 43 869 +1964 8 6 6 25 JOYCE 63.1 272.9 104 730 +1989 10 9 6 25 FLORENCE 63.7 201.4 30 294 +1973 5 9 0 4 BERYL 14.0 46.0 101 359 +1953 7 26 6 27 ALBERTO 16.6 146.8 12 299 +1995 10 2 6 10 ISAAC 33.3 17.4 23 433 +1993 10 1 12 5 TONY 56.7 104.8 72 784 +1957 4 9 18 4 CHRIS 40.1 123.8 67 88 +1974 6 20 12 22 OSCAR 48.7 197.7 80 857 +1953 1 27 6 4 KIRK 68.2 56.7 120 208 +1995 6 16 12 9 PATTY 29.3 291.9 53 774 +1967 8 24 12 28 NADINE 23.2 48.9 37 234 +1954 2 19 18 4 SANDY 24.9 72.6 81 642 +1979 7 17 6 20 WILLIAM 26.9 27.7 163 418 +1994 2 2 18 4 ISAAC 17.3 258.5 73 237 +1966 6 4 12 21 KIRK 28.8 189.6 133 805 +1978 5 10 0 11 RAFAEL 63.8 147.0 94 164 +2004 12 27 18 15 MICHAEL 38.3 113.1 102 445 +1983 5 21 6 26 WILLIAM 47.2 9.7 98 447 +1976 5 7 6 8 OSCAR 45.0 343.2 66 441 +1988 4 28 6 16 RAFAEL 67.7 128.4 107 889 +1993 3 15 0 2 KIRK 59.6 216.1 160 747 +1968 12 16 12 16 KIRK 43.0 348.4 158 577 +1982 3 17 18 18 ALBERTO 26.6 40.1 99 584 +1969 10 6 12 24 FLORENCE 51.6 272.2 156 2 +1984 6 2 12 25 RAFAEL 48.4 336.3 123 753 +1971 11 19 18 6 SANDY 51.6 308.4 85 715 +1991 1 27 6 6 WILLIAM 27.5 170.6 89 412 +1984 12 9 18 20 ERNESTO 57.1 251.8 47 782 +1966 2 10 12 22 TONY 68.3 99.3 39 713 +1985 10 23 12 19 VALERIE 66.5 209.8 54 620 +1999 7 24 12 14 DEBBY 8.9 89.6 114 277 +1963 7 22 6 15 GORDON 21.8 283.7 155 703 +1987 11 14 18 6 GORDON 40.3 210.2 49 721 +1985 6 17 0 20 ALBERTO 60.4 45.1 36 393 +1985 1 15 18 21 RAFAEL 11.0 223.4 74 220 +1988 3 23 12 18 PATTY 66.3 121.6 154 448 +1979 9 10 18 24 ALBERTO 13.4 307.9 150 632 +1956 9 20 18 21 KIRK 13.0 111.1 61 48 +1980 8 3 12 23 ERNESTO 27.4 345.2 93 64 +1981 7 22 18 10 VALERIE 14.3 138.6 134 546 +1974 12 21 18 14 WILLIAM 60.1 251.1 142 669 +2001 7 8 0 3 HELENE 15.5 179.6 128 797 +1993 1 3 12 23 NADINE 34.9 298.4 108 699 +1976 5 22 6 7 KIRK 30.4 326.8 79 778 +1975 2 13 18 3 ISAAC 42.4 95.9 152 403 +1955 3 10 0 4 FLORENCE 14.4 289.9 164 119 +1981 3 1 12 13 CHRIS 65.8 192.1 99 225 +1955 4 12 0 18 MICHAEL 20.4 140.1 142 522 +2003 7 12 0 8 MICHAEL 54.6 278.5 108 281 +2001 2 10 0 12 VALERIE 17.9 77.0 21 460 +1978 7 20 18 12 ERNESTO 14.6 299.3 63 384 +1980 10 11 0 14 OSCAR 53.1 350.2 77 655 +1953 1 26 6 17 JOYCE 59.1 24.4 106 74 +1992 3 13 0 16 LESLIE 13.7 103.5 146 629 +2004 9 21 18 7 OSCAR 62.9 93.8 45 895 +1966 3 22 12 20 FLORENCE 10.3 212.8 10 884 +1984 1 24 12 21 RAFAEL 12.2 176.4 131 848 +1989 9 1 6 1 OSCAR 53.4 162.0 67 767 +1967 12 11 0 8 OSCAR 45.0 114.4 12 358 +1974 8 1 18 27 NADINE 36.5 130.5 66 286 +1970 2 7 18 24 DEBBY 56.1 357.4 142 355 +1995 7 18 0 2 NADINE 26.3 152.6 142 10 +1963 9 27 12 28 FLORENCE 15.2 164.9 155 399 +1974 2 27 12 23 HELENE 45.0 47.8 32 520 +1954 3 20 18 5 JOYCE 43.7 155.3 23 268 +1956 1 21 18 19 FLORENCE 16.5 188.6 19 370 +1995 2 15 0 9 SANDY 69.9 182.6 76 813 +1994 9 11 6 13 HELENE 67.1 237.9 34 196 +1959 9 10 6 5 CHRIS 66.6 203.8 151 635 +1953 3 27 6 26 JOYCE 18.8 168.0 67 42 +1994 1 5 18 18 PATTY 48.4 12.7 28 186 +1993 11 21 6 21 PATTY 12.0 43.9 38 353 +1974 5 19 12 17 OSCAR 18.9 12.0 123 554 +1962 4 17 0 13 KIRK 57.2 218.3 95 482 +1953 8 16 0 26 PATTY 56.6 339.4 71 265 +1978 4 28 6 21 VALERIE 16.1 297.7 14 639 +1962 7 18 12 22 DEBBY 43.3 93.7 137 92 +1977 11 23 18 19 SANDY 18.6 187.5 102 765 +1987 9 12 12 5 FLORENCE 40.7 98.6 142 505 +2001 8 4 6 8 WILLIAM 16.9 19.1 149 465 +1953 1 12 12 20 RAFAEL 11.3 47.8 94 112 +2004 6 9 6 8 PATTY 26.2 10.0 65 717 +1961 9 18 6 20 BERYL 37.8 307.3 122 400 +1999 2 16 6 1 ERNESTO 15.1 151.3 132 156 +1967 2 15 12 28 SANDY 62.2 112.4 32 632 +1952 3 1 18 9 WILLIAM 19.5 40.3 69 460 +1988 8 6 18 26 ISAAC 38.6 69.5 156 133 +1995 4 24 12 25 JOYCE 51.5 270.6 104 156 +1978 2 3 12 8 OSCAR 38.0 192.6 72 285 +1960 1 15 12 2 MICHAEL 47.9 32.5 105 802 +1984 5 14 6 24 SANDY 65.9 101.8 119 855 +2002 8 1 0 4 CHRIS 51.7 103.1 44 830 +1987 2 19 0 16 VALERIE 58.5 6.5 59 580 +1979 3 6 6 26 ISAAC 45.9 50.8 44 72 +2002 7 17 18 7 CHRIS 34.6 71.1 108 514 +1973 3 6 0 15 SANDY 53.3 98.4 141 733 +2003 7 4 18 16 PATTY 68.7 199.6 50 281 +2003 6 22 0 10 SANDY 37.4 105.6 152 793 +1968 9 22 12 23 FLORENCE 14.2 339.0 85 184 +1961 5 2 12 24 RAFAEL 45.3 76.5 120 315 +2003 1 13 0 17 BERYL 10.0 221.0 103 575 +2003 4 5 18 3 ERNESTO 43.6 316.7 26 648 +1995 7 6 0 7 RAFAEL 50.2 98.9 57 386 +1994 6 17 6 14 HELENE 42.1 176.4 159 762 +1987 7 24 6 24 TONY 12.6 354.3 152 770 +1992 1 22 18 24 NADINE 56.9 318.7 102 703 +1984 5 19 12 13 LESLIE 34.3 112.4 16 491 +1996 12 4 6 18 ALBERTO 26.5 322.8 57 307 +1969 3 20 18 21 BERYL 69.6 38.0 157 328 +1971 2 26 12 6 NADINE 49.9 312.6 131 171 +1999 4 22 0 13 NADINE 34.8 275.9 42 127 +1954 3 27 12 7 RAFAEL 27.9 210.6 81 85 +1959 4 9 12 17 LESLIE 13.7 73.7 90 739 +1966 6 13 0 21 RAFAEL 35.8 282.3 97 145 +1996 1 26 6 9 HELENE 7.7 106.0 118 411 +1992 2 17 12 1 ERNESTO 35.9 22.0 22 670 +1961 9 13 6 14 ISAAC 27.8 143.2 10 426 +1978 2 23 18 17 DEBBY 11.6 292.6 51 138 +1960 3 28 6 5 NADINE 28.3 213.4 58 337 +1958 2 20 18 22 ALBERTO 63.0 201.5 27 411 +1998 3 19 18 1 PATTY 51.0 134.3 56 260 +1950 6 4 0 18 HELENE 37.3 174.1 27 409 +1996 7 6 6 27 RAFAEL 20.9 235.1 164 399 +1950 5 4 12 18 ERNESTO 47.2 112.8 11 199 +1991 8 6 0 12 BERYL 29.5 173.4 12 343 +1992 4 11 12 11 WILLIAM 16.1 35.0 106 303 +1980 5 6 0 19 CHRIS 33.6 110.9 47 849 +1994 12 23 6 26 CHRIS 40.7 128.1 74 398 +1986 2 23 12 16 HELENE 56.8 83.0 53 139 +1999 6 10 18 7 PATTY 18.0 256.2 90 43 +1970 10 25 12 21 LESLIE 54.2 127.3 73 48 +1978 5 27 6 19 TONY 36.7 245.1 121 296 +1990 7 7 12 1 BERYL 25.6 337.4 151 160 +1977 7 22 18 22 KIRK 22.1 152.9 62 306 +1971 7 2 18 16 FLORENCE 32.8 91.5 162 697 +1991 12 20 0 26 PATTY 28.9 0.8 119 740 +1991 7 14 6 13 NADINE 11.3 314.4 164 878 +1969 2 22 0 12 DEBBY 52.2 232.4 104 595 +2003 9 11 18 6 DEBBY 40.3 152.0 27 543 +1990 3 19 18 19 OSCAR 19.8 205.7 103 141 +1967 7 10 0 27 RAFAEL 62.4 79.5 70 218 +1977 11 5 0 20 NADINE 13.4 353.5 145 247 +1970 6 13 18 13 SANDY 37.9 61.2 39 457 +1961 6 6 18 15 HELENE 30.6 272.0 102 334 +1965 1 15 6 11 FLORENCE 64.8 241.0 126 620 +1986 9 24 0 3 DEBBY 36.8 307.2 76 549 +1991 10 10 6 20 TONY 67.6 20.1 164 121 +1990 6 2 0 15 FLORENCE 45.1 344.8 155 376 +1991 7 13 0 26 VALERIE 40.7 234.2 93 721 +1957 10 25 0 24 LESLIE 48.4 251.8 23 225 +1959 2 9 12 10 OSCAR 15.8 278.4 46 683 +1992 6 28 6 1 GORDON 65.4 54.3 107 117 +1963 12 21 18 10 ALBERTO 14.3 265.6 37 166 +1959 10 10 18 25 NADINE 65.0 269.7 110 525 +1987 7 24 6 17 ALBERTO 58.0 200.7 23 730 +1959 12 8 6 25 DEBBY 32.6 330.7 16 288 +1968 12 24 6 23 NADINE 19.6 221.3 45 830 +1953 6 27 0 1 HELENE 67.7 187.4 38 861 +1958 5 27 6 22 OSCAR 8.0 292.2 52 252 +1956 3 27 12 1 HELENE 58.7 109.0 125 103 +1972 12 20 12 26 SANDY 10.6 56.2 28 857 +1961 7 4 0 28 FLORENCE 11.8 262.8 53 304 +1995 12 2 12 3 ALBERTO 9.6 213.7 46 151 +1964 7 6 0 17 WILLIAM 47.0 79.5 142 607 +1995 11 8 18 14 PATTY 58.2 115.0 41 184 +1967 12 1 0 16 HELENE 21.2 238.1 153 132 +1983 3 7 6 20 RAFAEL 42.4 73.5 110 276 +2003 5 5 0 26 LESLIE 53.3 104.8 79 598 +1963 3 22 18 28 PATTY 22.0 319.6 93 586 +1964 12 25 6 28 SANDY 39.2 146.2 87 39 +1964 8 3 18 1 OSCAR 58.2 186.1 164 175 +1963 10 9 0 24 WILLIAM 60.9 196.3 95 125 +2002 10 15 12 4 KIRK 28.8 309.1 52 35 +2004 6 7 12 5 SANDY 38.7 64.7 49 769 +2000 4 24 18 27 ISAAC 11.3 290.3 53 643 +2004 7 20 18 7 MICHAEL 30.6 349.5 36 11 +1981 2 9 18 4 ALBERTO 51.8 311.6 95 149 +1986 6 21 18 9 GORDON 17.4 295.8 90 310 +1990 10 19 18 19 TONY 11.3 180.4 22 490 +2004 1 4 18 25 MICHAEL 11.3 210.0 57 760 +1959 11 13 6 24 TONY 51.3 79.2 74 261 +1981 3 26 6 10 FLORENCE 54.8 24.3 144 668 +1970 5 1 12 17 JOYCE 32.2 300.2 113 717 +1957 7 10 6 20 WILLIAM 28.0 278.0 157 663 +1980 8 28 18 15 VALERIE 21.1 95.5 159 635 +1991 6 26 12 5 KIRK 21.6 144.0 13 610 +1962 2 9 18 22 MICHAEL 47.1 63.0 76 498 +1988 9 3 18 9 RAFAEL 27.3 178.2 98 218 +1971 12 21 18 21 KIRK 26.7 103.3 160 290 +1954 7 19 12 17 OSCAR 25.6 348.1 33 663 +1976 8 21 6 20 FLORENCE 53.7 61.6 75 887 +1997 6 10 0 20 FLORENCE 59.8 90.7 11 804 +1993 2 1 12 8 MICHAEL 63.1 115.9 133 815 +1962 8 24 18 20 NADINE 39.2 65.7 64 176 +1959 2 23 6 7 FLORENCE 38.5 34.8 97 563 +1957 10 27 12 27 BERYL 14.2 58.3 101 279 +1962 10 7 6 18 MICHAEL 60.2 184.3 108 789 +1976 10 24 18 4 DEBBY 68.9 40.1 60 54 +2004 10 13 12 14 MICHAEL 64.0 133.2 18 572 +1950 5 8 18 13 RAFAEL 64.0 218.6 156 564 +1984 9 27 12 14 NADINE 63.0 253.3 147 480 +1975 12 11 18 12 ISAAC 7.9 12.6 58 0 +1963 1 4 12 13 OSCAR 49.7 24.9 29 759 +1986 10 3 6 3 OSCAR 45.9 155.8 88 422 +1970 1 4 0 20 SANDY 45.5 320.0 149 159 +1972 9 23 0 21 KIRK 54.3 72.2 85 63 +1960 10 6 18 9 ERNESTO 15.8 144.6 30 897 +1996 3 7 18 27 CHRIS 34.9 279.4 46 125 +1985 12 25 0 13 KIRK 31.0 22.5 80 853 +1973 11 22 6 16 MICHAEL 34.2 44.2 71 19 +1969 11 24 12 4 HELENE 44.0 313.0 95 172 +1982 4 14 18 8 TONY 64.4 62.8 11 387 +1974 2 12 6 7 FLORENCE 9.0 220.4 16 23 +1976 1 19 18 25 DEBBY 52.6 156.9 107 868 +1981 12 15 6 2 SANDY 29.8 192.4 106 424 +1953 7 20 12 27 TONY 34.3 239.6 91 341 +1965 12 21 6 12 FLORENCE 68.8 65.7 146 762 +1970 12 13 12 20 DEBBY 50.7 323.3 153 307 +1999 1 17 0 16 JOYCE 7.3 68.6 11 872 +1977 3 10 6 26 ISAAC 49.5 81.9 32 230 +1992 7 25 18 6 TONY 30.4 142.5 118 843 +1952 2 4 0 27 BERYL 16.3 58.8 54 463 +1985 7 1 18 10 HELENE 63.3 116.4 110 767 +1981 9 16 6 16 OSCAR 13.2 72.6 35 154 +1984 11 13 18 8 FLORENCE 23.8 50.5 103 890 +1954 10 18 12 16 ALBERTO 56.7 220.7 138 219 +1986 8 11 6 5 WILLIAM 18.8 105.5 46 242 +1980 12 27 12 20 ERNESTO 32.4 35.8 147 83 +1950 11 17 12 16 ISAAC 39.3 132.3 151 662 +1981 5 24 18 12 WILLIAM 58.8 329.9 26 718 +1951 9 13 12 15 LESLIE 63.4 227.5 10 158 +1972 10 6 6 22 HELENE 35.3 325.0 76 429 +1993 4 16 6 16 OSCAR 62.9 225.5 108 854 +1985 10 19 18 27 LESLIE 48.5 342.9 70 439 +1989 7 22 18 26 WILLIAM 18.9 355.5 100 756 +1982 8 11 12 27 BERYL 50.5 293.8 164 721 +2003 1 4 12 28 NADINE 10.9 122.7 148 629 +1957 4 9 12 12 VALERIE 27.9 323.4 74 698 +1979 12 14 18 19 CHRIS 60.4 323.6 158 2 +1965 11 19 12 2 ALBERTO 60.4 171.9 32 884 +1970 12 2 0 1 GORDON 49.9 36.9 29 174 +1984 12 17 12 15 RAFAEL 42.7 139.9 43 45 +1967 10 16 6 2 GORDON 37.3 101.8 129 331 +1950 9 27 0 16 SANDY 20.0 110.2 163 198 +1953 1 23 0 8 GORDON 10.7 156.8 55 819 +1980 11 18 18 18 HELENE 33.1 265.6 17 590 +1961 6 1 12 5 ISAAC 50.0 7.5 26 434 +1986 3 27 6 3 TONY 33.5 315.3 29 99 +1993 10 21 6 27 CHRIS 15.0 293.2 162 248 +1972 3 10 18 6 TONY 46.1 250.4 55 722 +1983 12 2 0 3 PATTY 12.1 347.3 50 815 +1995 10 16 6 18 TONY 60.0 133.8 79 573 +1991 2 3 0 26 BERYL 7.4 312.3 160 498 +1956 3 7 6 15 TONY 32.5 289.9 155 290 +2001 8 20 0 6 RAFAEL 60.0 271.8 129 686 +1975 2 6 18 23 SANDY 7.6 201.4 67 205 +1954 5 2 0 1 LESLIE 18.2 322.9 161 43 +1961 6 18 12 25 PATTY 60.7 251.0 25 39 +1988 6 7 12 1 MICHAEL 48.7 284.7 74 482 +1955 3 4 12 21 FLORENCE 34.7 79.1 51 773 +1960 1 14 6 19 HELENE 62.0 336.1 117 482 +1984 5 19 18 14 WILLIAM 22.1 3.8 28 767 +1989 11 10 6 23 BERYL 61.1 120.0 142 440 +1999 4 14 18 2 WILLIAM 68.3 3.6 69 71 +1956 11 18 0 24 ERNESTO 37.9 62.4 86 890 +1980 3 24 18 3 SANDY 61.4 37.2 79 550 +2003 9 25 0 16 ISAAC 51.1 222.7 74 839 +1959 6 19 6 7 HELENE 66.7 78.3 117 739 +1986 4 27 12 5 WILLIAM 17.4 293.7 96 0 +1953 10 26 12 2 TONY 16.1 241.2 73 785 +1953 1 10 12 12 TONY 51.2 127.3 111 571 +1978 11 11 6 12 LESLIE 61.7 74.5 44 667 +2004 11 3 0 18 LESLIE 8.9 263.9 45 526 +1957 3 23 12 2 TONY 26.8 292.3 67 62 +2003 10 21 12 13 FLORENCE 12.1 114.3 110 460 +1952 3 16 12 13 JOYCE 40.6 202.5 110 711 +1978 7 14 0 27 JOYCE 36.3 90.0 115 243 +1987 10 5 6 22 GORDON 34.1 188.7 135 105 +1980 3 1 12 1 HELENE 57.3 349.9 29 353 +1953 6 16 18 17 TONY 24.8 279.1 105 254 +1986 11 24 6 7 JOYCE 20.7 198.3 89 256 +1993 4 24 12 4 LESLIE 24.0 93.5 98 803 +1955 1 7 0 24 GORDON 15.1 107.6 74 159 +2003 11 3 18 5 WILLIAM 10.8 281.8 11 502 +1961 7 7 0 2 TONY 8.6 59.4 29 496 +2001 12 4 12 1 HELENE 40.6 250.7 52 775 +1989 11 19 18 25 TONY 40.7 292.2 76 868 +2002 9 17 6 23 HELENE 39.1 230.1 105 16 +2002 4 17 18 16 VALERIE 23.1 42.9 89 645 +1980 1 15 0 5 SANDY 39.1 139.1 121 10 +1962 9 10 6 10 ISAAC 36.0 176.8 58 573 +2000 9 21 6 26 DEBBY 62.7 253.5 38 487 +1959 11 25 12 16 RAFAEL 66.9 89.3 68 160 +1985 1 19 18 19 HELENE 54.8 7.4 101 700 +1973 10 28 6 6 DEBBY 28.1 338.4 123 599 +1976 4 24 18 10 ERNESTO 37.5 155.7 70 375 +1960 6 7 0 10 PATTY 51.5 9.6 56 24 +1972 7 6 6 21 ALBERTO 58.9 47.3 128 161 +1983 4 24 18 2 HELENE 24.3 300.7 38 80 +1969 4 17 6 4 NADINE 61.8 8.1 105 616 +1983 8 5 12 20 OSCAR 51.7 50.8 47 637 +1988 7 20 12 19 FLORENCE 69.7 187.7 96 352 +1999 8 14 18 2 LESLIE 11.9 159.9 123 82 +1992 2 23 0 4 NADINE 68.8 258.8 46 378 +1990 8 20 18 18 NADINE 36.4 201.7 152 125 +1964 8 22 0 4 NADINE 8.2 124.1 142 187 +1969 3 27 12 23 MICHAEL 66.9 254.4 102 463 +1976 8 21 0 9 OSCAR 30.5 17.2 79 503 +1987 4 12 6 12 KIRK 24.4 105.6 97 44 +1993 10 1 6 10 PATTY 19.2 275.4 81 355 +1967 4 1 0 10 SANDY 34.6 136.1 56 807 +1993 8 26 18 15 OSCAR 68.7 25.0 58 673 +1974 7 4 12 24 SANDY 59.5 134.8 77 881 +1998 7 24 12 9 ISAAC 35.9 179.3 40 672 +1958 5 14 6 28 FLORENCE 27.7 87.3 23 116 +1991 12 13 12 13 NADINE 60.6 102.5 29 738 +1951 12 13 6 16 GORDON 31.0 177.1 46 701 +1960 8 1 18 17 MICHAEL 25.7 4.4 77 857 +1956 4 1 6 10 VALERIE 60.3 217.7 126 344 +1971 9 1 18 12 CHRIS 30.3 293.4 65 226 +1974 4 25 12 15 SANDY 10.6 10.3 149 170 +1992 3 8 6 3 CHRIS 56.9 3.7 10 774 +1990 3 23 6 7 TONY 36.8 197.3 121 315 +1970 2 2 6 5 CHRIS 56.6 269.2 78 887 +1992 8 24 0 22 PATTY 55.8 126.4 85 846 +2003 7 11 0 3 KIRK 9.7 89.1 105 53 +1992 1 11 6 4 CHRIS 52.6 241.7 44 733 +1975 9 7 6 26 JOYCE 53.3 4.8 130 170 +1993 4 19 0 5 NADINE 27.5 135.1 144 159 +1982 7 21 18 7 JOYCE 55.6 239.8 63 646 +1965 6 27 0 21 VALERIE 17.5 162.8 164 30 +1970 10 15 18 10 HELENE 60.6 202.7 146 448 +1970 10 13 6 9 TONY 69.8 243.2 116 375 +1950 5 3 18 10 LESLIE 64.5 269.9 163 837 +1971 8 15 0 27 RAFAEL 46.0 271.4 69 857 +1957 12 27 18 15 VALERIE 37.6 226.1 111 622 +1985 8 20 12 3 LESLIE 25.6 136.8 109 106 +1968 11 17 12 16 CHRIS 19.9 345.7 144 213 +1951 1 17 18 22 LESLIE 22.6 225.1 95 891 +1973 7 16 6 25 JOYCE 57.6 288.8 100 114 +1974 5 26 6 20 WILLIAM 25.4 7.2 89 409 +1984 10 10 6 23 MICHAEL 57.4 111.8 57 251 +1982 12 10 18 15 PATTY 63.1 98.2 111 457 +1952 1 4 0 4 MICHAEL 25.9 79.3 132 87 +1998 2 3 12 26 OSCAR 57.2 75.8 42 391 +1951 11 20 0 5 GORDON 52.6 266.2 31 809 +1962 4 9 6 19 FLORENCE 62.0 321.7 44 680 +1971 7 27 6 2 HELENE 28.0 348.0 21 93 +1990 5 27 18 26 CHRIS 61.6 207.6 70 389 +1997 11 23 6 9 OSCAR 26.6 166.4 36 266 +2003 2 10 6 21 ALBERTO 14.1 66.4 152 65 +1986 1 23 0 10 CHRIS 69.7 204.4 90 390 +1985 6 23 12 2 ERNESTO 44.0 93.0 16 301 +1975 9 11 12 22 KIRK 48.7 59.1 74 776 +1982 8 4 6 20 JOYCE 47.2 159.5 44 302 +1993 5 28 12 14 ERNESTO 44.7 24.9 150 367 +1971 1 3 0 11 RAFAEL 52.3 234.8 65 847 +1951 2 17 0 4 ISAAC 64.8 117.4 77 677 +1978 7 9 12 4 TONY 50.5 301.2 54 400 +1970 1 26 0 13 TONY 51.5 284.4 15 408 +1996 4 14 12 3 LESLIE 22.8 40.1 120 393 +1954 2 10 6 6 NADINE 20.6 208.1 64 750 +1955 1 11 12 16 LESLIE 11.7 342.6 83 192 +1969 7 23 6 14 NADINE 36.4 104.0 71 105 +1982 5 19 18 28 BERYL 46.5 67.8 11 826 +1997 9 28 12 24 VALERIE 9.8 69.6 68 259 +1973 3 1 18 15 FLORENCE 21.7 88.6 103 571 +1962 2 24 0 26 VALERIE 35.3 242.5 135 462 +1954 6 1 12 19 LESLIE 65.3 28.8 78 680 +1957 7 24 6 13 LESLIE 16.2 1.3 141 705 +1985 6 3 0 8 TONY 33.2 96.0 26 341 +1993 1 16 6 27 ISAAC 32.8 88.0 112 787 +2002 2 18 12 2 WILLIAM 12.8 199.0 28 351 +1964 3 8 6 2 HELENE 53.9 270.0 108 728 +1967 7 24 0 28 MICHAEL 50.9 336.4 13 819 +1991 5 28 0 26 VALERIE 44.9 241.3 66 783 +1998 12 12 18 1 ERNESTO 31.1 343.2 161 486 +1991 1 9 6 1 RAFAEL 65.6 105.6 51 826 +1972 8 23 0 23 ISAAC 37.6 232.7 73 638 +1993 10 5 18 1 NADINE 12.0 98.8 95 466 +1991 5 23 0 9 TONY 51.2 162.3 98 516 +1952 6 1 18 13 HELENE 64.2 22.8 156 16 +1951 5 24 6 19 WILLIAM 59.5 193.1 144 483 +1964 12 27 12 1 BERYL 62.1 346.5 109 446 +1958 2 10 6 24 DEBBY 57.0 54.2 57 486 +1966 7 16 18 5 JOYCE 54.7 247.4 15 344 +2003 7 18 18 10 VALERIE 31.1 138.4 143 389 +1991 7 28 12 3 TONY 57.7 75.2 154 633 +1977 8 7 18 17 GORDON 20.0 312.4 143 386 +1988 2 6 18 8 ERNESTO 44.5 357.5 97 190 +1999 10 1 0 17 ALBERTO 25.8 286.4 74 348 +1991 3 6 12 19 ISAAC 55.6 86.4 39 398 +1988 12 17 12 5 RAFAEL 42.2 257.6 154 414 +2000 9 11 12 9 MICHAEL 67.9 127.8 129 269 +1963 6 9 0 12 VALERIE 59.6 348.8 30 590 +1977 10 26 0 10 TONY 29.3 288.2 132 517 +1999 12 16 0 4 DEBBY 52.7 108.8 73 125 +1953 4 24 6 6 KIRK 20.3 304.1 152 822 +1950 2 22 6 18 VALERIE 46.3 155.4 150 349 +1969 12 23 0 17 ERNESTO 19.1 138.0 85 355 +1959 2 27 0 18 NADINE 69.7 267.7 34 197 +1954 10 4 12 23 WILLIAM 18.2 127.3 94 94 +1962 2 7 12 6 BERYL 27.0 86.9 88 498 +2002 4 25 6 23 TONY 64.5 170.4 60 354 +1971 10 16 6 7 SANDY 23.2 209.1 80 666 +1982 4 4 6 8 PATTY 40.4 115.0 72 789 +1993 10 13 12 20 RAFAEL 61.8 181.8 122 261 +2001 9 17 0 26 JOYCE 50.6 99.8 80 316 +1993 12 14 12 16 LESLIE 26.9 174.9 79 735 +1977 10 27 6 2 WILLIAM 30.7 129.1 125 348 +1990 1 20 12 27 ISAAC 26.9 334.1 78 717 +1991 5 12 18 13 KIRK 42.0 108.1 94 601 +1973 8 6 18 28 HELENE 56.4 334.6 156 17 +2001 2 27 0 18 WILLIAM 60.4 344.8 73 319 +1982 11 19 0 17 VALERIE 46.8 78.7 36 353 +1977 1 6 18 4 HELENE 68.1 72.7 72 751 +1970 12 20 0 13 VALERIE 12.2 323.9 33 665 +1971 6 2 6 25 GORDON 35.3 129.7 134 728 +2001 10 18 12 25 ERNESTO 68.5 256.7 90 483 +2000 9 4 0 6 ALBERTO 27.1 73.7 81 209 +1959 2 11 6 6 GORDON 55.3 342.5 151 532 +2003 10 18 6 19 LESLIE 23.8 325.9 63 325 +1982 11 23 6 25 GORDON 26.2 17.2 106 186 +1980 1 1 0 12 LESLIE 36.5 271.5 26 779 +1979 4 25 0 15 HELENE 62.4 59.4 35 428 +1980 10 5 6 19 LESLIE 56.6 312.1 125 634 +1987 7 17 6 1 ERNESTO 69.6 334.8 88 240 +1961 10 11 12 9 CHRIS 50.9 55.6 152 377 +1999 9 17 18 13 SANDY 65.8 99.6 146 577 +1995 6 18 12 19 PATTY 42.3 211.7 62 872 +1984 9 21 12 16 ALBERTO 46.0 117.4 81 837 +1984 10 18 18 27 BERYL 55.2 160.8 93 336 +1970 1 6 18 15 GORDON 17.6 334.1 83 283 +1981 3 16 6 23 WILLIAM 18.5 269.1 154 710 +2000 12 26 0 25 OSCAR 62.1 63.9 45 749 +1962 7 7 6 6 MICHAEL 15.9 95.3 52 749 +1974 2 26 6 10 WILLIAM 69.8 151.7 21 152 +1979 12 17 6 18 GORDON 28.8 327.3 139 326 +1958 12 4 6 15 MICHAEL 26.9 321.0 48 572 +1969 12 28 0 24 ERNESTO 7.8 308.9 151 167 +2002 7 26 0 7 FLORENCE 22.3 187.4 51 361 +1969 4 1 6 28 MICHAEL 48.9 220.1 117 552 +1981 1 15 12 21 DEBBY 46.9 95.1 53 638 +1958 10 11 6 27 DEBBY 8.2 335.0 56 854 +1967 5 3 0 18 BERYL 56.8 352.1 102 790 +1991 9 10 18 23 LESLIE 43.5 211.1 159 759 +1969 12 12 0 3 KIRK 57.7 335.2 162 491 +1984 2 1 0 8 ISAAC 27.8 78.5 163 255 +1963 8 12 0 11 NADINE 11.4 208.6 78 778 +1995 12 17 12 28 WILLIAM 11.2 101.5 155 754 +1964 6 10 12 5 ALBERTO 69.8 80.5 116 760 +1960 1 9 12 4 FLORENCE 53.2 84.8 50 99 +1955 11 6 6 25 NADINE 48.8 37.2 99 885 +1974 1 10 18 18 PATTY 66.4 214.9 69 309 +1993 6 1 6 18 LESLIE 54.9 54.1 62 72 +1960 1 23 18 10 SANDY 41.6 324.8 132 703 +1953 9 10 12 25 LESLIE 36.9 113.2 115 500 +1967 7 25 12 17 FLORENCE 47.2 148.1 133 841 +1997 11 28 0 17 ALBERTO 26.7 247.4 53 67 +2001 2 13 6 1 HELENE 67.2 146.0 139 377 +1994 11 25 18 24 OSCAR 35.6 307.5 84 575 +1977 9 4 12 25 KIRK 63.5 116.5 81 91 +1996 11 22 12 13 TONY 10.0 281.6 73 494 +1972 11 28 0 11 NADINE 61.8 54.0 121 281 +1986 6 13 18 5 WILLIAM 12.4 127.5 129 539 +1991 11 27 0 19 VALERIE 50.3 9.5 159 405 +1951 8 7 18 12 PATTY 9.5 221.0 64 767 +1990 7 13 18 10 VALERIE 29.2 281.5 129 879 +1979 5 3 6 23 JOYCE 45.9 147.4 58 132 +1961 5 21 0 9 HELENE 39.8 8.8 50 71 +1999 8 22 0 5 KIRK 61.8 294.1 112 278 +1974 6 20 6 14 NADINE 26.5 125.2 114 143 +1955 4 25 0 19 TONY 44.6 187.5 67 855 +1996 1 11 6 11 TONY 24.2 69.8 17 828 +1950 11 20 12 5 DEBBY 60.6 290.1 149 348 +1955 8 14 0 6 OSCAR 30.8 121.2 34 769 +1995 7 17 12 2 ISAAC 14.8 184.5 96 710 +1967 4 2 18 18 CHRIS 31.1 356.8 144 345 +1971 8 20 18 2 ISAAC 10.8 233.0 133 870 +1956 11 19 12 9 GORDON 63.0 136.5 149 681 +1986 10 4 0 20 RAFAEL 47.4 35.7 13 262 +2000 7 24 0 28 LESLIE 68.5 186.2 100 76 +1959 4 3 12 22 CHRIS 53.6 13.4 144 268 +1950 7 12 12 8 KIRK 33.3 98.8 17 551 +1960 7 19 12 17 ALBERTO 33.2 161.4 60 133 +1953 8 15 12 14 OSCAR 69.1 109.0 75 365 +1992 7 21 0 3 HELENE 12.7 44.1 161 866 +1969 1 17 6 2 WILLIAM 16.3 123.1 124 440 +1982 9 20 6 19 GORDON 60.8 190.4 98 372 +1958 10 1 18 16 ERNESTO 69.2 148.3 33 428 +1999 6 7 0 2 DEBBY 54.3 133.1 160 406 +2000 1 17 12 3 VALERIE 41.8 128.5 145 875 +1989 9 5 12 15 VALERIE 53.7 116.0 57 409 +1994 6 11 0 6 FLORENCE 29.5 90.9 145 374 +1974 6 19 12 12 HELENE 35.2 13.6 36 323 +2004 5 12 6 6 WILLIAM 8.6 140.6 149 37 +1975 12 27 12 27 NADINE 34.4 6.5 52 729 +1990 4 5 6 10 HELENE 12.1 45.1 30 574 +1966 6 21 12 11 NADINE 25.0 63.2 145 303 +1970 3 7 0 2 MICHAEL 55.6 134.0 54 444 +1971 11 11 0 2 OSCAR 31.8 62.8 107 593 +1959 3 18 6 20 SANDY 34.8 66.0 152 198 +1981 9 24 12 18 RAFAEL 58.5 272.4 86 844 +1997 9 1 18 4 FLORENCE 67.9 104.7 149 52 +2004 2 23 12 21 DEBBY 41.4 240.3 51 286 +1950 8 27 12 24 OSCAR 11.3 253.9 163 310 +1972 9 3 6 7 FLORENCE 12.4 154.3 106 265 +1959 6 5 0 17 CHRIS 22.4 285.8 14 873 +1960 6 22 0 1 ISAAC 25.2 94.6 58 612 +2002 9 15 0 4 WILLIAM 39.9 136.5 115 476 +1992 7 18 6 4 OSCAR 47.8 53.1 70 853 +1987 11 11 18 8 CHRIS 19.9 323.7 154 368 +1996 8 13 0 14 LESLIE 24.1 16.3 137 238 +1966 4 19 18 16 LESLIE 25.0 160.6 38 443 +1976 7 11 6 16 ALBERTO 7.5 36.8 75 77 +1963 6 26 0 8 TONY 51.8 192.2 56 237 +1969 7 14 18 26 TONY 45.7 192.6 33 814 +1987 2 15 6 20 RAFAEL 51.5 68.8 13 607 +1950 1 6 6 26 FLORENCE 43.4 290.1 23 137 +1988 10 8 18 22 DEBBY 28.9 315.0 52 688 +1962 2 18 6 2 SANDY 19.6 128.0 155 177 +1957 12 9 0 12 NADINE 59.7 79.0 161 785 +1952 8 17 0 23 SANDY 48.8 239.2 19 478 +1963 3 2 6 9 DEBBY 43.9 253.2 55 584 +1961 11 28 12 16 SANDY 36.7 101.6 66 836 +1950 1 9 0 19 SANDY 58.4 156.6 58 532 +1973 8 26 12 27 ISAAC 44.0 37.6 125 682 +1978 11 18 6 26 CHRIS 57.8 201.7 113 371 +1979 11 23 18 27 GORDON 13.7 5.1 71 517 +1986 9 7 6 15 MICHAEL 55.3 180.8 71 508 +1961 2 5 18 12 ISAAC 35.5 5.9 23 377 +1955 5 2 18 2 ISAAC 18.4 309.6 37 786 +1989 1 9 12 7 SANDY 26.6 8.9 16 609 +1958 7 16 18 20 ISAAC 13.7 42.6 162 17 +2003 5 9 0 28 BERYL 36.5 309.5 38 583 +1966 12 13 6 18 DEBBY 49.9 168.1 106 646 +1954 5 11 6 3 CHRIS 10.1 247.0 136 417 +1959 9 1 12 24 FLORENCE 53.5 324.5 100 242 +1994 6 12 0 27 NADINE 24.4 89.1 75 297 +1961 4 1 18 20 VALERIE 38.7 215.7 16 726 +1950 4 5 18 1 SANDY 14.2 296.8 51 66 +1963 1 14 18 17 VALERIE 56.0 21.4 35 556 +1961 3 20 12 4 WILLIAM 56.6 68.1 119 856 +1987 12 7 18 5 PATTY 30.0 314.5 77 8 +1966 12 3 0 24 ISAAC 59.6 96.0 140 280 +1970 1 28 6 5 OSCAR 19.4 144.4 158 132 +1965 4 13 6 10 PATTY 69.9 141.6 58 341 +1985 11 4 18 15 WILLIAM 42.0 102.1 114 853 +1958 6 17 0 2 WILLIAM 37.2 228.6 41 376 +1962 5 18 6 1 WILLIAM 67.4 56.4 164 74 +1974 3 2 12 10 GORDON 60.2 95.3 119 40 +1976 7 11 6 4 JOYCE 33.8 284.6 147 594 +1974 11 9 6 4 BERYL 27.0 302.2 49 25 +1986 11 11 6 6 ALBERTO 59.6 16.5 52 450 +2002 7 18 0 1 GORDON 58.7 187.9 121 118 +1968 6 8 6 11 WILLIAM 39.0 96.4 17 458 +1976 5 3 0 17 KIRK 63.7 113.7 130 585 +1966 9 6 18 20 MICHAEL 17.4 234.5 154 782 +1987 5 3 0 11 WILLIAM 53.4 162.7 87 533 +1984 2 24 0 13 ERNESTO 53.9 22.9 164 269 +1962 2 26 6 19 ALBERTO 33.1 207.1 138 25 +1974 4 6 18 12 RAFAEL 19.6 175.0 72 586 +1992 8 24 0 19 MICHAEL 30.3 237.1 161 345 +1960 1 12 6 3 FLORENCE 62.4 84.1 77 443 +1955 5 19 12 8 BERYL 57.3 232.3 10 162 +1975 11 6 12 22 VALERIE 57.3 137.7 57 53 +1965 9 11 18 25 HELENE 10.1 154.0 94 506 +1961 1 8 6 25 ALBERTO 50.9 172.8 112 628 +1969 1 12 12 3 NADINE 54.3 356.5 33 280 +1965 8 22 18 16 PATTY 42.1 131.0 24 840 +1953 5 15 12 2 RAFAEL 50.1 357.9 138 585 +1970 10 12 18 20 KIRK 17.1 328.4 91 686 +1969 5 11 0 9 TONY 10.4 242.5 163 49 +1992 6 2 6 4 NADINE 20.9 239.0 87 424 +1981 1 9 18 5 GORDON 60.9 17.6 93 579 +1980 7 8 0 18 FLORENCE 41.6 178.0 154 242 +1991 11 8 0 17 OSCAR 43.2 264.9 105 328 +1973 7 2 0 15 GORDON 30.6 2.0 13 190 +1980 9 2 0 13 CHRIS 37.5 31.9 66 579 +1957 8 1 6 13 WILLIAM 63.9 105.4 152 777 +1968 1 24 18 28 RAFAEL 18.8 288.9 78 190 +1986 3 14 18 13 JOYCE 64.4 159.7 80 284 +1969 2 10 18 9 VALERIE 47.4 326.5 40 170 +1992 9 7 12 19 CHRIS 21.5 123.9 118 225 +2004 4 28 6 11 WILLIAM 12.2 147.4 130 819 +1974 2 27 12 13 CHRIS 34.0 29.7 93 471 +1988 1 2 18 10 BERYL 8.9 350.8 118 16 +1970 2 8 6 16 RAFAEL 58.0 344.7 54 562 +1961 3 20 6 26 MICHAEL 20.8 281.4 135 832 +1968 12 4 12 24 SANDY 50.3 288.7 115 411 +1983 8 3 0 3 JOYCE 19.1 97.0 57 243 +1989 4 27 0 26 ISAAC 43.1 170.4 108 855 +1968 12 2 0 14 BERYL 11.2 146.8 55 72 +1971 12 11 0 7 CHRIS 54.9 247.6 69 414 +1954 2 9 12 22 GORDON 50.7 250.0 53 270 +1984 11 23 0 1 OSCAR 19.2 202.1 81 744 +1981 8 20 12 13 ERNESTO 27.9 122.1 48 690 +1950 3 4 12 13 CHRIS 39.9 79.1 104 648 +1982 9 24 18 28 FLORENCE 14.3 189.7 138 570 +2003 8 17 12 21 NADINE 8.0 313.6 20 239 +1957 10 7 6 16 ISAAC 33.7 167.4 81 180 +1982 7 18 0 22 KIRK 24.8 258.6 54 374 +1964 11 17 12 11 VALERIE 54.1 346.7 131 9 +1960 2 11 12 10 LESLIE 66.1 191.0 82 881 +1971 3 13 6 1 MICHAEL 66.4 16.0 86 405 +1998 1 18 18 13 CHRIS 44.4 319.2 118 200 +1961 11 21 0 10 FLORENCE 19.2 12.9 113 103 +1966 11 12 12 23 TONY 63.6 30.3 108 566 +1954 9 21 6 4 VALERIE 32.8 225.6 75 767 +1967 11 20 6 16 OSCAR 30.0 137.3 52 354 +1997 10 23 18 27 NADINE 51.1 174.1 106 353 +1976 1 6 12 19 FLORENCE 53.0 100.6 82 639 +1995 4 19 12 4 BERYL 39.2 180.2 42 302 +1973 5 15 6 19 BERYL 16.2 66.7 96 367 +1958 12 5 12 13 OSCAR 56.7 65.9 125 370 +1964 1 7 18 3 NADINE 33.5 63.9 37 371 +1985 11 11 0 8 KIRK 9.6 113.7 53 751 +1950 7 6 12 23 ISAAC 52.2 278.3 103 241 +1997 2 24 6 17 DEBBY 44.5 1.7 33 268 +1984 1 26 12 21 BERYL 46.1 5.6 89 553 +1969 8 23 18 26 HELENE 15.1 180.0 73 848 +1999 3 25 12 22 ALBERTO 26.2 74.7 82 402 +1982 12 3 6 3 MICHAEL 30.2 248.2 128 313 +1954 6 23 18 25 OSCAR 61.4 79.5 25 60 +2001 4 6 18 4 OSCAR 69.5 79.6 105 633 +1977 5 8 6 26 CHRIS 53.3 102.6 27 411 +1954 7 10 0 27 SANDY 67.9 322.4 80 867 +1997 4 9 0 24 OSCAR 60.2 87.6 66 814 +1963 5 8 0 6 RAFAEL 22.8 227.8 51 535 +1972 9 3 12 3 VALERIE 63.5 239.4 60 507 +1993 6 16 6 23 ALBERTO 67.7 355.3 56 630 +1997 9 9 12 26 BERYL 56.2 95.7 78 805 +1956 4 2 12 2 RAFAEL 49.0 334.5 53 897 +1954 10 10 18 13 MICHAEL 66.3 179.5 109 568 +1991 9 4 0 12 KIRK 39.8 34.4 20 325 +1967 3 7 12 12 HELENE 50.0 34.3 67 386 +1986 10 20 12 23 JOYCE 57.6 184.5 75 609 +1953 3 28 12 22 TONY 34.7 247.6 118 400 +1993 4 6 0 25 SANDY 40.0 38.6 130 453 +1993 1 13 6 3 VALERIE 53.5 318.4 159 835 +1969 6 9 12 28 NADINE 12.1 325.9 68 203 +1989 10 3 0 27 HELENE 21.1 249.7 34 527 +1984 11 28 6 24 GORDON 50.1 318.6 139 510 +1982 11 25 0 7 GORDON 44.1 245.5 111 326 +1971 3 13 18 1 BERYL 10.3 69.7 83 605 +1978 9 22 0 14 OSCAR 60.6 40.2 76 845 +1955 6 18 0 4 TONY 28.7 169.3 43 877 +2002 3 13 18 4 OSCAR 52.3 225.8 126 58 +1958 5 18 6 7 KIRK 50.0 267.2 117 56 +2003 3 26 18 10 TONY 59.0 37.9 47 602 +1950 4 28 12 10 ERNESTO 51.2 114.6 18 163 +1959 7 15 12 15 MICHAEL 43.4 157.1 155 442 +1963 12 10 18 13 MICHAEL 37.6 304.3 108 515 +2004 2 20 6 24 NADINE 54.3 352.7 131 424 +1960 3 13 12 26 RAFAEL 27.3 156.4 90 75 +1972 4 2 18 4 CHRIS 37.9 135.5 44 178 +1977 3 12 18 14 LESLIE 53.7 139.1 134 798 +1963 3 25 6 12 SANDY 33.8 91.4 84 664 +1985 12 18 6 22 LESLIE 42.0 28.0 101 411 +1999 10 19 18 26 LESLIE 23.5 11.9 70 361 +1960 1 22 6 2 RAFAEL 61.9 292.4 120 713 +1983 6 1 18 2 GORDON 67.7 147.0 119 12 +1953 6 1 6 28 LESLIE 16.5 207.2 15 82 +2001 8 27 12 23 WILLIAM 38.9 121.4 76 34 +1976 7 3 6 8 ISAAC 14.1 328.9 92 785 +1958 8 18 18 16 PATTY 63.1 160.8 48 553 +1965 7 18 6 2 GORDON 51.3 190.0 124 595 +1996 10 15 6 24 NADINE 55.3 249.8 51 524 +1959 2 2 6 18 JOYCE 42.6 323.9 71 751 +1976 12 3 6 2 MICHAEL 11.9 21.4 86 878 +2002 4 28 12 8 FLORENCE 40.3 221.0 87 438 +1997 11 21 6 3 KIRK 17.7 150.9 62 463 +1979 11 16 18 25 PATTY 44.8 349.8 45 411 +1999 4 14 12 20 WILLIAM 63.1 338.8 96 622 +1993 8 3 6 14 TONY 18.9 148.4 72 722 +1958 12 25 18 1 WILLIAM 53.6 277.6 54 354 +1953 5 13 6 5 TONY 44.3 145.5 68 301 +1957 11 11 0 10 RAFAEL 58.6 288.4 25 123 +1962 11 1 6 2 MICHAEL 22.9 122.3 51 80 +1954 4 9 18 2 KIRK 61.9 2.3 56 685 +1974 2 3 6 9 ALBERTO 69.0 300.5 57 106 +1988 8 1 0 28 SANDY 58.4 327.3 116 216 +1981 4 16 18 23 VALERIE 66.9 215.2 69 399 +1978 11 27 12 15 FLORENCE 64.7 43.6 149 753 +1982 5 9 0 19 GORDON 21.4 177.3 117 65 +1950 3 7 0 2 SANDY 64.7 246.5 153 705 +1968 3 5 6 16 WILLIAM 24.3 232.3 134 842 +2001 1 20 6 28 VALERIE 37.0 0.1 28 228 +1996 10 28 0 28 ERNESTO 32.4 38.8 101 755 +1983 8 21 6 3 PATTY 54.7 185.9 89 888 +1956 2 18 6 3 RAFAEL 33.6 179.1 14 306 +2004 3 22 12 21 ALBERTO 55.5 12.9 101 882 +1970 6 24 18 20 HELENE 60.8 186.1 103 808 +2001 10 10 12 15 ERNESTO 60.9 180.4 65 628 +1960 6 6 18 20 RAFAEL 28.6 208.8 117 112 +1999 2 3 18 27 PATTY 35.4 112.6 162 182 +1993 4 4 18 13 MICHAEL 11.4 192.2 19 264 +1990 12 11 6 9 NADINE 60.1 215.2 101 315 +1966 10 22 12 27 BERYL 13.4 262.5 114 852 +1994 5 24 0 7 JOYCE 8.3 249.2 58 377 +1992 11 23 12 19 ISAAC 19.6 76.9 118 666 +1951 1 12 18 21 GORDON 32.3 188.7 145 170 +1996 5 18 12 15 HELENE 55.5 94.9 55 566 +1973 1 19 6 28 CHRIS 60.5 185.8 109 510 +1962 11 15 0 14 ERNESTO 30.5 34.9 90 836 +1970 12 16 12 14 GORDON 51.8 161.9 118 828 +1996 8 12 6 4 WILLIAM 55.4 165.3 126 132 +1985 10 20 6 6 LESLIE 34.9 283.9 98 436 +1963 2 7 0 20 CHRIS 13.6 27.8 68 36 +1987 1 23 18 15 HELENE 7.8 318.5 77 271 +1984 9 7 6 26 FLORENCE 19.9 226.8 136 39 +1955 9 4 12 5 RAFAEL 20.8 92.5 54 106 +1966 9 17 18 4 PATTY 54.8 81.2 75 277 +1957 5 6 18 21 ISAAC 25.0 161.8 139 137 +1952 6 11 12 6 VALERIE 64.4 302.2 106 897 +2004 10 19 18 10 JOYCE 29.1 250.7 49 342 +1994 8 4 0 6 RAFAEL 49.3 41.4 60 424 +2001 12 8 18 5 JOYCE 63.8 357.1 36 796 +1974 1 18 12 26 RAFAEL 69.7 13.4 58 427 +1999 2 19 0 22 NADINE 9.5 207.0 161 459 +1962 11 4 6 22 HELENE 10.7 141.9 42 108 +1968 6 25 18 1 LESLIE 31.9 98.1 163 371 +1990 12 6 0 1 RAFAEL 28.6 148.6 28 831 +2003 7 22 6 18 PATTY 7.3 307.9 78 431 +1974 5 6 6 5 DEBBY 48.3 241.7 89 787 +1965 7 27 18 26 PATTY 34.5 186.7 121 865 +1997 4 5 6 15 RAFAEL 13.6 14.2 85 875 +1976 3 21 6 8 RAFAEL 18.2 78.7 121 110 +1968 3 11 6 19 BERYL 61.2 289.2 70 465 +1994 6 3 0 4 GORDON 21.2 214.9 31 153 +1963 1 19 12 24 ISAAC 40.9 199.4 17 645 +1966 4 6 6 15 WILLIAM 65.7 174.5 72 807 +1953 8 22 12 27 RAFAEL 55.0 244.8 45 603 +1978 4 20 12 11 ISAAC 30.3 75.3 116 598 +1957 8 7 0 4 HELENE 44.4 169.4 50 699 +1996 9 9 0 27 GORDON 61.4 198.2 83 520 +1953 12 13 12 26 GORDON 10.2 272.2 94 891 +1986 1 27 6 14 WILLIAM 38.8 1.0 76 746 +1965 2 8 12 5 DEBBY 8.2 184.6 134 823 +1982 5 5 6 19 VALERIE 66.9 69.3 122 362 +1988 5 13 12 13 LESLIE 48.9 189.9 70 459 +1950 5 23 0 12 JOYCE 17.3 97.1 13 453 +1990 2 1 6 25 GORDON 27.2 57.3 125 776 +1972 7 9 6 18 TONY 30.3 344.6 84 370 +1998 3 7 0 10 GORDON 32.9 142.3 89 441 +1975 12 9 6 24 OSCAR 47.6 51.5 90 221 +1986 12 9 6 27 KIRK 25.2 30.3 78 540 +1957 11 14 6 13 VALERIE 55.0 355.3 118 422 +1973 1 8 18 10 HELENE 48.4 353.6 83 76 +1966 10 25 18 15 RAFAEL 64.6 183.6 126 503 +1985 3 22 0 9 RAFAEL 19.7 124.0 120 869 +1983 11 2 12 28 BERYL 23.3 352.6 122 298 +1990 2 2 6 27 FLORENCE 10.3 345.0 84 167 +1985 7 4 18 18 NADINE 43.4 70.9 76 727 +1990 10 19 6 12 KIRK 17.4 128.1 115 324 +1989 5 16 12 28 MICHAEL 53.9 287.7 114 826 +1951 3 25 12 18 LESLIE 47.3 343.1 65 344 +1951 9 3 18 6 TONY 46.3 138.3 92 653 +1992 6 24 0 19 JOYCE 23.1 37.6 65 128 +1998 1 28 18 17 WILLIAM 41.6 135.3 33 856 +1979 6 18 12 17 MICHAEL 24.1 187.7 17 531 +1990 10 8 0 13 BERYL 60.9 75.7 153 695 +1995 9 14 6 3 NADINE 29.3 347.6 151 615 +1996 6 3 0 25 SANDY 9.0 110.0 82 839 +1958 10 6 0 10 SANDY 13.1 234.4 44 373 +1953 4 4 6 7 OSCAR 46.0 185.5 149 6 +1961 5 28 0 23 CHRIS 23.3 329.7 95 586 +1955 4 27 0 28 DEBBY 59.3 114.9 157 632 +1966 1 18 18 1 ERNESTO 52.4 262.4 129 740 +1979 1 21 6 25 CHRIS 26.7 348.8 46 210 +1991 5 25 18 26 NADINE 60.4 298.8 12 352 +1962 3 14 0 15 LESLIE 53.2 274.1 107 418 +1957 9 1 12 15 RAFAEL 66.4 236.2 140 459 +1956 2 7 0 26 VALERIE 35.8 70.3 153 88 +1984 12 8 6 17 BERYL 57.6 279.1 132 617 +1955 8 13 0 20 VALERIE 11.0 169.5 104 620 +1963 12 4 18 5 WILLIAM 15.8 111.3 56 405 +1978 4 6 0 7 MICHAEL 25.9 127.8 117 598 +1970 8 11 12 26 FLORENCE 69.6 119.7 90 753 +2002 5 22 6 4 WILLIAM 19.3 285.4 31 75 +1951 11 4 18 9 DEBBY 41.0 205.8 53 108 +1962 5 23 12 3 VALERIE 39.6 103.9 21 618 +1983 6 28 18 2 RAFAEL 58.7 272.3 126 82 +1980 10 23 0 18 ISAAC 38.9 78.1 15 854 +1997 8 17 6 25 OSCAR 34.8 175.5 116 20 +1991 12 26 6 22 ALBERTO 33.0 65.1 35 820 +2000 1 19 12 11 HELENE 34.9 119.7 25 185 +1996 1 28 12 4 ALBERTO 10.3 202.1 47 729 +1990 3 21 6 12 GORDON 25.8 277.0 113 530 +1966 4 11 12 21 ALBERTO 8.2 268.7 56 827 +1958 5 17 0 18 LESLIE 68.9 233.3 26 40 +1973 2 22 12 25 HELENE 55.2 322.7 40 200 +2003 12 4 12 12 WILLIAM 31.0 59.7 33 174 +1964 5 6 12 27 MICHAEL 32.8 44.6 134 262 +1985 4 28 0 3 DEBBY 26.6 190.9 71 165 +1993 5 17 6 19 PATTY 32.6 269.5 33 10 +1980 5 23 18 25 VALERIE 14.1 74.3 159 254 +1968 6 3 0 26 KIRK 8.5 312.6 160 240 +1978 10 13 0 22 FLORENCE 63.5 119.1 29 521 +1965 3 15 6 23 GORDON 56.9 52.4 120 313 +1954 3 19 6 17 RAFAEL 31.8 193.5 146 486 +1957 7 13 6 16 ALBERTO 55.9 193.7 16 37 +1993 2 27 0 12 RAFAEL 22.2 305.9 124 133 +1956 3 27 12 1 ERNESTO 49.0 335.3 54 792 +1959 12 5 12 1 JOYCE 65.3 7.0 140 151 +1965 10 11 12 22 CHRIS 66.9 211.3 144 298 +1959 5 27 6 14 BERYL 40.3 122.5 96 378 +1998 6 15 0 3 GORDON 40.4 76.6 67 43 +1957 1 18 12 15 TONY 51.1 132.3 128 201 +1964 9 18 0 2 ERNESTO 18.4 269.4 79 74 +1963 10 6 0 16 HELENE 46.8 48.7 98 668 +1978 4 3 12 6 FLORENCE 32.9 189.8 71 303 +1967 6 9 12 19 GORDON 35.5 82.0 124 674 +1974 9 19 12 26 ISAAC 42.7 155.2 154 137 +2002 1 25 0 18 ALBERTO 29.4 340.9 108 874 +1982 8 15 0 5 SANDY 23.7 193.9 88 41 +1963 1 13 0 26 HELENE 17.2 313.5 148 266 +1990 8 15 6 15 GORDON 35.5 162.7 39 256 +1978 4 25 0 24 LESLIE 61.5 195.7 73 812 +1986 3 1 0 17 NADINE 42.5 37.5 123 166 +1952 2 11 12 12 CHRIS 19.5 285.1 27 701 +1990 7 10 0 20 FLORENCE 61.2 153.7 36 777 +1994 9 22 6 10 ALBERTO 29.2 36.3 106 455 +1982 1 8 6 8 OSCAR 10.6 193.8 98 561 +1975 7 12 18 16 RAFAEL 43.6 31.1 74 835 +1997 11 19 6 13 LESLIE 15.3 342.8 115 503 +1986 9 24 0 5 ERNESTO 40.3 137.0 65 302 +1972 3 28 12 17 FLORENCE 25.7 348.0 52 181 +1966 3 6 0 2 WILLIAM 50.8 168.9 141 210 +1977 2 10 6 14 SANDY 28.8 28.0 64 642 +1996 7 12 12 3 LESLIE 35.5 159.0 116 314 +1972 6 27 6 8 ISAAC 17.9 233.2 23 176 +1974 8 11 6 7 HELENE 15.5 226.6 158 590 +1998 3 9 6 11 TONY 51.6 54.0 27 447 +1986 8 14 12 5 MICHAEL 69.8 33.9 94 703 +1961 10 4 18 5 SANDY 67.6 146.8 76 774 +1972 3 5 0 8 HELENE 25.8 332.3 140 578 +1958 9 7 18 13 ERNESTO 55.5 268.8 150 660 +1987 10 10 0 16 ALBERTO 31.0 30.8 135 349 +1971 1 25 0 26 JOYCE 25.3 204.8 64 646 +1992 3 23 0 2 CHRIS 28.5 336.2 144 689 +1986 2 3 0 5 RAFAEL 13.3 59.0 65 509 +1998 5 2 12 13 OSCAR 23.0 241.2 20 628 +1970 1 22 6 15 MICHAEL 62.5 188.4 120 400 +1994 6 23 18 8 SANDY 64.9 290.1 154 868 +1995 7 25 6 5 BERYL 24.9 155.3 38 409 +1981 1 2 12 18 PATTY 65.9 129.6 96 278 +1985 10 11 12 28 KIRK 36.0 85.7 68 254 +1970 8 19 12 22 OSCAR 43.7 152.1 16 513 +1961 2 24 6 11 NADINE 29.9 11.5 111 496 +1953 11 14 18 10 RAFAEL 62.4 262.4 140 348 +1963 2 20 12 7 SANDY 56.5 157.0 155 513 +1962 7 26 0 1 ALBERTO 24.6 144.5 154 823 +1987 6 28 0 13 HELENE 67.8 139.3 50 491 +1977 6 1 0 1 NADINE 37.7 86.5 53 116 +1989 2 22 6 12 ISAAC 31.3 85.3 46 884 +1970 11 24 12 23 CHRIS 39.2 14.5 110 658 +1976 6 23 18 24 OSCAR 21.4 137.7 125 578 +2004 10 13 12 18 SANDY 42.7 292.0 136 279 +1993 10 8 0 7 BERYL 42.2 300.1 122 699 +2001 10 27 6 27 FLORENCE 55.6 113.8 43 200 +1961 3 14 12 4 KIRK 16.5 320.8 80 344 +1981 9 27 18 25 WILLIAM 45.3 239.5 26 511 +2004 1 21 12 9 DEBBY 70.0 53.3 92 181 +1997 3 15 12 8 LESLIE 20.8 258.1 104 776 +1956 2 28 12 27 JOYCE 25.1 12.2 40 265 +1979 6 20 12 9 OSCAR 64.4 197.7 110 66 +1980 3 5 12 1 JOYCE 55.6 291.3 95 401 +1954 10 3 12 20 WILLIAM 18.7 206.4 104 431 +1950 7 25 12 25 ISAAC 17.0 258.8 127 374 +1956 3 20 18 17 LESLIE 44.3 27.4 87 716 +1962 5 13 18 16 LESLIE 17.6 182.5 45 244 +1951 7 7 18 16 FLORENCE 27.8 205.7 65 25 +1968 11 21 6 18 ERNESTO 47.8 235.4 61 297 +1976 7 1 0 1 OSCAR 11.1 157.5 136 382 +2004 8 26 18 17 PATTY 32.1 86.1 62 521 +1991 8 12 18 10 WILLIAM 12.2 178.8 136 602 +1967 7 1 6 3 ALBERTO 57.0 231.2 53 165 +1964 12 2 18 21 KIRK 55.2 65.7 57 32 +1955 1 6 6 17 NADINE 16.5 89.1 161 275 +1979 11 20 18 20 MICHAEL 15.8 119.7 86 581 +1968 3 12 0 11 MICHAEL 61.3 188.3 92 776 +1969 4 19 6 9 GORDON 42.8 206.3 126 591 +1977 3 22 12 17 KIRK 24.6 93.0 27 287 +1965 12 10 12 17 KIRK 45.6 104.0 164 544 +1971 6 12 18 5 WILLIAM 26.1 67.3 88 796 +1962 5 7 12 28 KIRK 7.1 87.2 158 436 +1966 8 5 6 9 BERYL 46.5 111.3 69 260 +1992 5 2 6 16 GORDON 18.7 47.9 103 368 +1996 10 27 18 2 DEBBY 10.7 235.5 91 849 +1994 5 2 6 13 ISAAC 68.4 72.1 75 775 +1952 5 25 6 16 JOYCE 26.1 259.9 87 458 +1961 5 21 18 13 DEBBY 11.8 316.7 129 411 +2001 8 14 6 27 LESLIE 42.1 338.3 120 759 +2004 10 26 12 14 BERYL 11.5 299.4 105 195 +1999 4 26 12 9 WILLIAM 56.8 93.8 82 889 +1991 12 4 12 21 KIRK 32.6 168.0 30 1 +1995 1 6 6 26 ALBERTO 45.5 214.6 25 255 +1954 5 1 0 15 ERNESTO 29.6 152.5 139 78 +1982 4 12 12 18 MICHAEL 16.5 1.9 159 388 +1996 9 2 18 7 LESLIE 26.2 150.3 117 730 +1961 9 7 18 13 PATTY 37.9 99.3 56 61 +1958 10 1 12 7 TONY 67.6 50.3 30 602 +1952 4 18 6 3 FLORENCE 49.3 42.5 132 80 +1985 5 16 12 18 MICHAEL 57.8 305.1 158 635 +1977 1 18 18 9 WILLIAM 24.9 128.6 88 316 +1954 6 25 0 16 BERYL 48.0 237.3 103 488 +1961 12 21 6 15 BERYL 21.3 100.0 109 547 +1995 11 21 18 11 CHRIS 12.3 44.1 103 335 +1997 4 10 12 16 RAFAEL 44.5 170.1 47 194 +1990 9 24 0 15 MICHAEL 39.8 292.5 34 520 +1972 6 27 18 1 FLORENCE 56.5 118.2 116 96 +1965 8 16 12 7 FLORENCE 22.7 292.2 11 194 +1950 5 6 12 18 JOYCE 43.5 199.2 43 232 +1971 2 4 18 6 JOYCE 8.3 323.8 42 734 +1983 6 3 18 14 WILLIAM 18.8 337.8 65 380 +1998 12 17 0 21 GORDON 8.1 340.6 24 354 +1952 2 6 18 4 ISAAC 58.4 277.8 91 865 +1998 3 3 0 18 BERYL 19.9 283.4 49 182 +1950 4 26 0 27 PATTY 28.7 2.6 141 627 +1996 7 22 0 26 SANDY 12.8 49.2 109 490 +1979 4 5 0 17 MICHAEL 70.0 339.6 46 460 +1986 2 11 12 17 HELENE 29.2 269.9 11 190 +1997 4 1 12 28 HELENE 16.4 39.8 78 695 +2003 1 7 0 20 ERNESTO 16.9 207.5 62 156 +1967 9 2 12 24 KIRK 11.5 41.8 110 578 +1983 9 21 18 21 CHRIS 49.6 72.1 127 885 +1963 1 19 12 28 KIRK 54.9 170.7 85 341 +1963 12 27 12 21 DEBBY 54.4 278.4 122 878 +1963 8 11 12 25 BERYL 26.2 70.6 10 365 +2000 9 7 12 9 FLORENCE 14.5 28.8 81 453 +1955 8 27 12 5 CHRIS 52.9 213.7 117 45 +1982 4 17 18 14 ALBERTO 68.4 62.8 56 786 +1970 8 10 0 18 ISAAC 60.5 160.5 138 247 +1996 8 16 18 11 JOYCE 68.3 53.1 26 191 +1995 7 1 6 1 ISAAC 16.5 323.0 132 144 +1979 2 10 12 9 LESLIE 41.8 51.9 62 545 +1963 6 13 6 23 LESLIE 53.0 101.9 54 308 +1959 2 17 18 22 PATTY 62.9 319.7 134 889 +1969 10 3 0 7 WILLIAM 7.0 334.6 103 778 +1980 4 20 12 4 ISAAC 65.7 184.1 104 639 +1990 4 10 18 24 DEBBY 11.1 280.9 76 197 +1983 2 12 12 8 BERYL 48.6 75.1 10 412 +1996 4 21 12 22 SANDY 34.9 257.7 89 162 +1977 1 7 12 24 HELENE 26.0 210.6 32 643 +1980 4 2 6 3 ISAAC 47.3 252.7 135 322 +2000 10 27 6 17 WILLIAM 31.0 193.8 52 308 +1986 9 22 0 27 ISAAC 39.0 191.8 74 869 +1972 2 16 12 16 NADINE 55.0 299.6 149 257 +1993 2 17 6 16 MICHAEL 37.0 288.5 151 245 +1981 1 12 18 13 ERNESTO 37.3 72.9 74 171 +1959 6 5 6 5 DEBBY 59.7 323.3 86 123 +1954 12 28 18 4 FLORENCE 49.7 47.4 55 756 +1970 12 15 12 1 LESLIE 59.2 89.8 98 785 +1993 8 18 18 2 KIRK 48.9 212.7 64 165 +1964 6 13 0 25 BERYL 23.0 156.3 32 662 +1952 12 3 18 25 JOYCE 63.8 326.1 68 307 +1952 10 10 6 23 KIRK 11.7 9.8 128 504 +1966 7 20 18 10 NADINE 36.9 1.6 129 468 +1958 7 17 0 24 PATTY 40.8 322.6 67 434 +1997 7 13 18 22 OSCAR 7.2 39.8 107 762 +1998 3 26 12 22 FLORENCE 60.2 321.8 84 560 +1981 11 24 6 12 TONY 61.4 116.0 107 370 +1996 10 21 0 12 ERNESTO 39.8 123.4 56 300 +1961 2 12 6 4 GORDON 65.8 209.5 147 132 +1991 1 8 6 9 WILLIAM 47.8 117.0 44 617 +1966 10 8 6 26 CHRIS 15.5 290.2 10 383 +1969 4 25 0 20 TONY 51.9 160.9 114 306 +1987 12 9 0 4 GORDON 8.1 32.2 121 321 +1975 12 18 18 1 RAFAEL 59.7 220.6 46 529 +1998 2 17 12 19 WILLIAM 9.0 302.6 131 291 +1961 3 25 0 20 VALERIE 8.9 178.0 23 734 +1962 6 27 18 21 HELENE 19.6 158.4 77 874 +1952 1 27 12 22 NADINE 44.7 223.9 150 669 +1983 7 1 12 17 WILLIAM 46.2 204.3 153 76 +1984 7 6 18 1 BERYL 52.5 121.5 67 794 +1976 10 4 0 20 CHRIS 53.9 179.0 112 554 +1966 8 13 0 28 CHRIS 48.7 270.8 90 484 +1974 7 7 0 11 SANDY 57.4 182.7 123 883 +1992 4 24 18 17 CHRIS 11.1 113.1 61 688 +1958 6 15 0 20 WILLIAM 67.3 124.4 74 134 +1976 5 20 12 10 PATTY 39.5 152.2 153 448 +2000 3 26 0 5 WILLIAM 13.1 218.6 10 681 +1965 7 24 12 14 ISAAC 7.4 209.7 128 746 +2001 12 1 6 9 GORDON 10.1 72.8 74 360 +1958 1 14 12 24 MICHAEL 34.0 328.8 62 697 +1970 8 18 12 16 WILLIAM 48.4 125.8 148 781 +2002 4 1 18 2 VALERIE 69.0 30.1 44 20 +1955 5 2 12 4 OSCAR 23.7 349.4 43 223 +1967 1 4 6 26 ISAAC 19.6 118.8 133 325 +1992 12 16 18 8 BERYL 28.4 239.6 58 474 +1985 9 12 0 6 VALERIE 38.3 354.5 94 899 +1968 9 1 18 8 WILLIAM 11.9 302.3 15 762 +1988 10 5 12 3 GORDON 24.4 151.1 152 222 +1953 10 28 18 1 RAFAEL 15.1 8.1 112 509 +1965 1 25 6 17 HELENE 32.4 123.4 116 753 +1965 10 5 0 6 FLORENCE 41.7 220.4 133 248 +1989 6 24 12 17 LESLIE 59.6 266.8 38 166 +2000 11 22 6 6 DEBBY 32.8 6.2 160 525 +2002 5 4 6 28 VALERIE 50.2 302.4 77 654 +1968 9 6 6 13 HELENE 53.7 321.7 156 576 +1950 6 18 0 12 RAFAEL 62.5 357.4 15 502 +1986 11 14 0 4 ISAAC 68.3 315.3 35 75 +1979 8 13 18 22 GORDON 31.2 120.3 143 259 +1991 11 1 0 15 ALBERTO 35.7 134.4 162 739 +1986 9 18 6 17 SANDY 58.3 278.8 109 209 +1985 5 27 0 18 ERNESTO 15.3 41.6 87 51 +1953 9 1 6 25 KIRK 68.6 201.7 108 721 +2003 2 18 6 3 RAFAEL 56.3 95.1 110 791 +1966 6 26 0 18 ERNESTO 36.2 105.9 146 128 +1979 12 8 12 17 ALBERTO 32.6 194.5 155 694 +1961 6 25 18 23 SANDY 48.3 92.3 60 313 +1965 7 24 12 15 ALBERTO 38.1 59.7 42 789 +1958 5 15 6 17 ERNESTO 34.3 255.6 151 849 +1993 5 11 12 21 KIRK 62.5 356.9 162 400 +1962 11 24 6 4 TONY 17.7 352.5 73 557 +1951 1 4 6 5 BERYL 55.6 64.1 50 38 +2004 6 1 0 12 FLORENCE 53.1 113.3 78 359 +1961 5 8 6 14 WILLIAM 48.0 202.6 69 681 +1974 8 13 6 21 SANDY 11.0 166.2 93 622 +1953 7 19 0 11 TONY 36.5 294.0 41 524 +1993 3 17 12 20 TONY 24.3 170.5 66 389 +1990 11 24 18 19 BERYL 35.9 43.7 42 30 +2004 6 18 12 16 TONY 26.9 341.2 103 602 +1970 4 14 0 12 KIRK 48.0 173.5 49 665 +1984 2 24 6 17 TONY 15.8 39.4 68 875 +1953 10 13 0 9 WILLIAM 17.2 274.5 66 627 +1990 3 12 18 27 DEBBY 17.3 231.4 13 172 +1964 5 12 6 13 HELENE 51.2 284.2 50 782 +1978 8 11 6 24 VALERIE 15.2 275.3 123 775 +1980 7 12 6 26 ERNESTO 35.2 94.7 64 612 +1954 5 6 0 5 DEBBY 56.3 354.2 37 125 +1951 3 1 6 26 VALERIE 21.2 20.6 13 405 +1963 6 1 6 18 LESLIE 14.1 108.5 63 281 +1951 8 19 0 9 VALERIE 57.4 341.9 74 317 +1956 8 5 18 1 ALBERTO 28.9 147.4 128 642 +1981 5 3 12 1 RAFAEL 51.3 45.5 92 449 +1990 8 15 12 9 FLORENCE 52.0 34.9 135 472 +1956 7 10 0 4 NADINE 49.0 36.5 35 148 +1953 7 27 18 28 WILLIAM 36.7 221.0 55 587 +1978 4 23 6 23 MICHAEL 56.8 29.8 154 262 +1957 8 12 18 5 JOYCE 22.6 201.0 104 532 +1981 4 15 12 3 RAFAEL 49.7 339.4 53 319 +2001 10 9 0 17 RAFAEL 26.7 134.7 21 424 +1976 4 4 6 26 MICHAEL 60.4 326.9 144 458 +1962 2 2 12 22 TONY 62.0 301.1 150 835 +1986 2 8 12 12 WILLIAM 33.2 17.4 121 650 +1966 6 28 18 25 FLORENCE 46.0 329.8 25 708 +1990 1 4 18 2 HELENE 56.3 100.3 89 221 +2000 2 2 6 16 FLORENCE 19.9 315.1 25 587 +1965 11 22 18 10 TONY 9.3 61.1 75 874 +1999 1 15 18 27 NADINE 61.0 29.3 49 32 +1988 4 11 12 18 RAFAEL 26.4 127.9 148 739 +1969 10 2 0 5 ISAAC 35.5 87.6 12 189 +1996 5 17 6 15 WILLIAM 43.2 356.6 140 476 +1994 1 7 0 24 FLORENCE 59.0 227.1 136 713 +1999 5 11 6 6 RAFAEL 48.1 315.2 156 433 +1971 5 7 6 5 NADINE 34.3 229.2 10 508 +1977 2 11 18 22 ERNESTO 62.5 259.9 14 866 +1998 1 20 6 12 MICHAEL 55.4 293.6 82 67 +1951 9 2 12 4 WILLIAM 40.3 355.6 15 851 +1972 11 16 18 18 RAFAEL 15.9 225.4 26 340 +1978 11 19 12 15 ALBERTO 8.6 355.0 18 128 +1956 6 7 0 3 MICHAEL 8.7 95.2 92 738 +1978 1 27 18 14 KIRK 21.7 283.1 95 415 +1969 8 24 6 10 VALERIE 17.7 154.2 43 492 +1962 4 14 0 10 ERNESTO 39.0 167.7 66 338 +1996 4 23 0 2 CHRIS 53.9 285.8 95 188 +1997 2 17 6 10 WILLIAM 31.6 35.5 120 484 +1977 3 21 0 8 VALERIE 33.2 279.0 107 727 +1978 10 2 18 5 VALERIE 18.7 145.7 93 642 +1959 8 11 0 15 VALERIE 59.3 248.7 16 667 +1954 1 14 12 18 BERYL 61.5 329.4 45 505 +1998 10 13 18 14 TONY 10.6 202.2 116 770 +1977 5 1 12 10 HELENE 11.2 258.1 57 567 +1960 9 18 18 4 KIRK 55.8 139.9 23 208 +1957 3 24 18 15 VALERIE 37.1 174.8 15 75 +1988 8 1 12 15 DEBBY 33.0 259.8 121 634 +1989 5 5 18 10 PATTY 42.2 271.1 111 449 +1961 9 22 18 19 JOYCE 48.0 85.8 71 847 +1959 2 17 0 8 RAFAEL 30.4 46.5 133 158 +1976 4 15 18 3 GORDON 63.6 169.4 96 795 +1977 1 10 12 27 ERNESTO 53.6 353.7 116 613 +1952 4 18 12 27 FLORENCE 52.0 222.3 36 66 +1953 7 27 0 21 ERNESTO 21.4 11.2 48 15 +1970 1 28 18 7 DEBBY 66.9 234.1 162 156 +1990 10 23 6 28 RAFAEL 45.4 224.1 83 230 +1960 8 28 18 1 BERYL 65.4 21.1 159 365 +1988 5 25 18 10 GORDON 51.2 85.6 57 151 +1971 9 18 12 19 BERYL 23.9 201.6 131 855 +1969 8 22 12 18 CHRIS 16.3 28.8 85 7 +1969 9 19 6 14 ALBERTO 37.0 75.4 127 794 +1968 10 8 6 23 CHRIS 18.8 123.9 141 824 +1971 11 4 6 22 BERYL 61.4 55.6 98 850 +1986 9 1 12 10 OSCAR 59.3 16.5 15 752 +1981 3 10 6 1 BERYL 34.5 222.4 20 644 +2000 11 20 12 10 TONY 27.2 127.3 163 824 +2002 3 1 6 6 SANDY 30.7 193.7 78 235 +1961 8 23 12 9 JOYCE 14.4 213.8 132 851 +1957 6 16 18 23 TONY 16.5 165.3 80 744 +1979 8 16 18 19 FLORENCE 62.3 105.9 34 867 +1959 3 14 12 12 WILLIAM 25.5 228.1 53 780 +1996 2 26 0 10 DEBBY 57.6 189.8 125 761 +1977 8 4 18 1 ERNESTO 53.5 109.1 137 108 +1957 9 8 18 17 WILLIAM 48.1 357.5 122 856 +1971 10 26 18 13 GORDON 17.7 278.1 53 866 +1992 8 12 6 12 NADINE 25.4 302.2 58 30 +2001 3 8 12 24 TONY 39.7 345.9 133 310 +1966 9 11 0 2 CHRIS 58.6 309.3 150 736 +1954 9 17 18 23 BERYL 10.4 26.4 63 493 +1979 6 18 18 1 JOYCE 60.7 145.1 138 446 +1995 10 8 18 16 JOYCE 54.5 126.9 92 780 +1971 5 26 12 18 ISAAC 51.3 335.3 68 518 +1979 11 13 18 23 PATTY 43.7 86.7 92 171 +1964 4 11 12 9 KIRK 38.5 171.6 144 554 +1995 10 13 12 27 RAFAEL 16.3 80.7 29 414 +1999 11 27 18 16 DEBBY 36.2 23.2 14 673 +1963 8 6 18 24 GORDON 67.9 3.8 161 207 +1977 7 1 0 3 ISAAC 31.4 274.6 87 713 +1962 1 13 0 2 KIRK 55.5 135.7 58 408 +1967 12 21 0 5 ISAAC 68.5 322.8 99 15 +1973 3 14 6 28 JOYCE 62.4 66.4 58 263 +1996 2 7 12 13 BERYL 66.4 159.2 88 448 +1957 4 21 12 7 ALBERTO 29.9 12.1 157 210 +1967 7 5 18 15 PATTY 51.3 342.6 113 453 +1967 4 17 6 19 OSCAR 27.5 295.6 106 77 +1988 8 12 18 14 DEBBY 23.0 181.7 161 887 +1958 4 27 12 21 OSCAR 32.8 51.1 59 265 +2004 12 26 12 21 JOYCE 29.9 34.5 69 227 +1966 11 6 0 21 BERYL 29.8 308.1 32 744 +2004 12 11 0 11 CHRIS 12.8 178.8 118 32 +1999 1 23 6 1 HELENE 52.1 321.4 134 590 +1972 7 13 0 13 OSCAR 40.4 65.5 120 525 +1963 9 28 18 16 ERNESTO 15.1 344.8 78 284 +1967 2 8 12 8 FLORENCE 27.4 43.1 155 607 +1973 4 6 18 26 DEBBY 46.2 237.5 98 206 +1976 8 2 0 5 NADINE 37.4 248.9 37 185 +2004 8 4 6 12 BERYL 42.8 221.8 75 82 +1987 7 28 18 3 GORDON 14.6 36.0 109 34 +1965 1 12 12 1 JOYCE 36.9 323.3 130 836 +1989 4 20 6 17 PATTY 59.1 209.5 153 686 +1965 7 25 18 18 NADINE 65.3 15.0 159 475 +1991 11 2 18 2 GORDON 49.9 20.6 62 331 +1978 12 21 12 27 DEBBY 67.0 11.7 23 540 +1981 4 7 0 8 PATTY 35.0 164.5 47 765 +1983 8 7 12 2 SANDY 65.8 52.3 21 734 +1953 8 3 6 21 FLORENCE 32.9 95.0 13 543 +2004 5 22 6 26 KIRK 9.3 221.1 49 750 +1988 6 8 12 11 MICHAEL 25.3 195.1 142 758 +1980 4 16 18 27 RAFAEL 59.6 156.1 157 681 +1983 3 15 12 24 CHRIS 62.6 333.4 47 249 +1996 1 27 18 16 ERNESTO 36.6 78.9 112 461 +1997 10 5 6 14 OSCAR 29.5 35.9 103 134 +2004 7 8 12 3 PATTY 17.9 327.0 147 47 +1958 10 27 18 15 ALBERTO 34.6 148.4 49 527 +1957 3 15 6 28 HELENE 61.0 344.8 100 309 +1957 4 2 12 18 LESLIE 33.0 291.4 116 209 +1968 11 8 6 28 VALERIE 22.1 337.1 146 432 +1987 11 19 12 23 NADINE 18.3 273.9 39 410 +2004 4 9 6 23 ISAAC 9.0 286.5 28 75 +1992 1 25 6 9 LESLIE 65.9 275.4 64 703 +1978 1 28 18 22 TONY 44.7 201.9 50 500 +1974 7 11 0 4 SANDY 14.9 122.7 135 274 +1986 8 10 12 15 ERNESTO 34.1 45.4 38 152 +1988 9 28 0 27 RAFAEL 49.6 67.2 62 189 +1984 6 10 12 25 OSCAR 52.3 1.7 137 332 +1995 7 21 0 20 JOYCE 45.1 221.9 78 14 +2004 12 9 6 2 CHRIS 11.1 162.9 48 729 +1997 8 12 18 6 OSCAR 31.5 123.0 71 792 +1950 3 11 6 15 SANDY 38.2 38.6 52 561 +1991 9 24 18 4 MICHAEL 11.8 348.4 120 3 +1991 8 21 0 23 WILLIAM 45.5 202.0 47 202 +1974 10 28 0 22 JOYCE 48.1 192.1 140 170 +1989 9 8 6 8 HELENE 57.1 182.7 131 512 +2004 5 21 18 24 ISAAC 64.3 146.8 36 471 +1975 11 16 6 24 DEBBY 34.9 309.6 152 810 +1978 2 2 18 23 SANDY 43.4 143.0 69 103 +1971 6 28 18 26 LESLIE 43.7 260.6 39 202 +1998 1 14 0 7 ERNESTO 50.0 4.8 110 712 +1993 10 22 18 9 FLORENCE 42.8 328.5 47 216 +2002 3 13 6 5 WILLIAM 69.3 153.1 126 75 +2002 12 7 0 28 ISAAC 17.6 1.8 70 317 +1977 6 18 12 20 VALERIE 33.2 253.3 59 175 +1987 3 13 0 15 ERNESTO 65.4 22.5 79 279 +2001 1 15 12 23 SANDY 31.8 47.2 41 40 +1975 2 15 0 16 DEBBY 23.0 49.3 141 97 +1997 2 14 6 19 WILLIAM 65.1 318.4 41 118 +1999 9 5 18 2 GORDON 15.2 175.7 55 756 +1991 7 28 18 19 JOYCE 8.3 65.7 80 521 +1950 9 26 18 3 TONY 50.1 141.3 138 880 +1989 1 23 12 28 JOYCE 55.0 250.5 17 562 +1975 4 17 12 26 TONY 30.3 46.5 77 574 +1960 5 20 12 3 GORDON 48.1 258.1 148 663 +1979 12 19 12 6 VALERIE 57.9 118.9 63 102 +1979 2 3 0 15 NADINE 18.8 255.8 45 543 +1999 2 3 18 2 TONY 39.9 81.6 47 652 +1986 6 21 12 11 PATTY 56.2 49.0 105 641 +1971 3 23 6 21 VALERIE 57.0 154.5 29 756 +1951 5 16 6 2 HELENE 61.9 257.0 90 552 +1985 11 24 18 26 TONY 27.2 134.9 103 840 +1985 11 28 18 6 KIRK 22.5 114.4 78 603 +1955 11 24 12 5 KIRK 56.8 179.3 152 352 +1977 12 18 18 19 WILLIAM 11.6 188.3 100 865 +1967 9 2 18 16 TONY 35.5 184.4 162 232 +1961 12 21 12 25 ERNESTO 49.3 291.9 156 355 +1997 12 15 12 28 ISAAC 49.3 28.5 74 627 +1996 2 6 18 12 KIRK 33.5 135.4 66 513 +1950 3 14 0 14 CHRIS 56.1 330.6 137 559 +1977 11 4 6 24 GORDON 41.1 30.7 113 391 +1988 6 9 0 10 GORDON 61.1 280.9 148 67 +1989 4 8 6 26 ALBERTO 64.9 353.3 80 634 +1996 8 9 12 25 BERYL 20.2 201.5 143 212 +1978 7 1 0 11 MICHAEL 38.6 104.9 18 609 +1975 1 16 12 9 ISAAC 49.6 157.4 50 525 +1979 11 2 6 9 LESLIE 25.0 348.6 81 94 +1958 7 10 12 5 MICHAEL 49.2 178.4 115 300 +1963 8 24 6 12 VALERIE 35.5 90.9 106 447 +1968 5 14 18 11 WILLIAM 21.3 292.8 116 70 +1988 3 23 18 10 ISAAC 15.0 62.0 48 391 +1985 7 18 6 27 SANDY 58.1 185.2 94 253 +1987 10 27 0 1 CHRIS 54.2 201.9 164 672 +1955 3 15 12 26 NADINE 11.1 149.8 21 249 +1988 3 7 6 5 DEBBY 55.6 120.6 106 20 +1954 2 4 6 19 VALERIE 39.7 280.1 110 481 +1957 12 23 0 15 KIRK 41.5 118.7 105 23 +1979 5 14 12 10 JOYCE 21.8 195.3 32 507 +1997 12 28 18 16 KIRK 35.0 170.6 63 126 +1965 2 3 6 18 NADINE 54.8 74.4 115 494 +1983 10 26 12 11 ERNESTO 62.3 295.3 56 12 +1975 10 13 12 12 MICHAEL 26.4 56.8 47 99 +1996 12 28 18 5 SANDY 16.2 27.8 76 373 +1965 11 28 18 23 ALBERTO 18.2 4.9 137 212 +1954 3 7 12 14 SANDY 38.5 312.3 19 708 +1972 10 15 12 1 WILLIAM 46.5 325.6 135 391 +1972 9 20 18 25 ALBERTO 31.4 196.5 125 73 +1951 2 11 12 20 KIRK 37.6 89.1 110 836 +1952 2 27 6 21 DEBBY 52.0 261.5 111 292 +1958 1 2 6 6 HELENE 35.4 208.3 136 45 +1991 1 20 12 18 ERNESTO 58.1 167.2 44 249 +1966 7 25 18 7 OSCAR 63.0 108.2 55 859 +2000 9 12 12 26 FLORENCE 11.7 238.8 16 37 +1973 2 3 6 11 KIRK 59.7 155.1 21 685 +1957 4 22 12 4 JOYCE 10.4 269.6 84 345 +1986 7 6 6 6 MICHAEL 51.8 336.5 55 548 +2003 9 2 6 7 GORDON 26.3 79.1 33 645 +1991 11 14 12 11 FLORENCE 51.6 131.1 67 398 +1977 9 20 18 18 MICHAEL 54.0 314.4 21 871 +1990 12 10 0 16 TONY 31.9 44.4 71 842 +1993 9 19 18 18 DEBBY 18.6 9.6 159 92 +1962 2 25 12 23 NADINE 37.2 5.7 10 574 +1963 4 13 0 3 HELENE 24.3 103.6 92 562 +1981 10 21 18 27 NADINE 12.8 216.5 54 566 +1990 4 9 18 18 BERYL 22.3 23.9 100 271 +1992 10 4 0 23 KIRK 49.6 73.0 26 787 +1998 6 24 6 21 WILLIAM 59.7 174.7 82 305 +1952 11 12 18 17 OSCAR 66.2 75.1 10 606 +1964 4 9 12 7 MICHAEL 20.0 279.0 115 563 +1974 10 25 6 22 HELENE 61.5 140.4 66 738 +1982 2 11 18 1 LESLIE 54.6 118.6 138 520 +1983 5 4 18 25 SANDY 7.8 133.4 158 530 +1974 10 10 0 24 RAFAEL 29.2 51.3 159 173 +1967 5 4 12 3 ISAAC 51.1 145.7 60 95 +1984 8 22 0 7 RAFAEL 36.3 36.4 103 635 +1962 5 19 6 10 KIRK 27.2 295.2 107 247 +1974 8 22 18 10 WILLIAM 50.3 211.2 70 419 +1984 3 9 0 23 HELENE 16.6 23.6 39 650 +1981 3 1 0 13 SANDY 24.8 260.7 150 681 +1992 12 9 18 12 ERNESTO 39.9 16.7 20 860 +1992 7 3 6 25 ISAAC 8.4 26.6 79 640 +1980 7 18 6 27 PATTY 41.4 191.3 111 641 +1973 8 17 0 23 MICHAEL 40.6 261.3 154 254 +1952 7 22 0 3 TONY 38.6 93.7 95 22 +1960 3 11 6 2 WILLIAM 48.4 173.4 37 51 +1987 1 6 18 8 NADINE 63.5 225.7 83 681 +1971 8 2 18 22 ERNESTO 51.5 356.2 44 101 +1958 6 13 18 13 ISAAC 38.0 97.9 161 684 +1982 2 12 0 9 FLORENCE 59.7 57.4 42 379 +1988 8 13 0 8 RAFAEL 49.6 129.5 19 233 +1988 4 3 18 25 HELENE 66.8 60.6 24 812 +1976 3 25 6 10 LESLIE 53.0 240.6 80 897 +1952 11 27 6 24 RAFAEL 58.1 252.8 73 130 +1956 12 4 0 26 WILLIAM 31.9 121.0 35 823 +1990 12 25 6 1 RAFAEL 37.7 25.6 118 503 +1968 10 13 6 7 TONY 7.2 350.4 36 218 +1964 8 16 0 21 ISAAC 28.3 230.6 29 30 +1963 9 16 6 13 ERNESTO 31.3 111.5 49 609 +1995 8 12 12 26 PATTY 50.5 189.4 98 137 +1957 9 22 0 25 FLORENCE 41.8 35.1 106 739 +1960 5 16 18 2 ERNESTO 41.8 259.9 61 36 +1967 7 21 12 3 SANDY 13.2 280.6 11 104 +2001 9 4 18 8 PATTY 54.3 282.0 137 737 +1965 8 25 0 12 FLORENCE 55.7 219.6 74 823 +1963 2 25 0 3 NADINE 35.7 284.5 81 569 +1961 9 26 12 6 MICHAEL 20.9 103.4 149 662 +1998 12 15 18 12 KIRK 61.5 122.5 53 28 +1996 2 8 0 22 ALBERTO 39.0 324.6 10 694 +1984 11 9 12 3 SANDY 56.9 126.7 87 497 +1991 8 18 6 8 ISAAC 29.7 175.8 26 205 +1990 11 2 12 9 BERYL 23.5 167.8 30 629 +2000 2 23 6 13 NADINE 22.7 182.3 22 813 +1967 4 23 12 13 JOYCE 41.8 210.6 68 557 +1952 9 25 0 13 TONY 63.1 130.5 64 287 +1990 1 28 6 10 CHRIS 12.8 288.6 132 480 +1957 5 23 0 18 DEBBY 49.1 342.8 18 211 +1983 12 4 0 12 ISAAC 55.3 355.9 118 166 +1969 8 14 18 5 MICHAEL 30.1 3.1 121 364 +1963 1 7 18 26 PATTY 45.0 34.9 54 315 +1959 8 27 12 27 VALERIE 48.2 7.2 52 221 +1982 8 25 0 18 VALERIE 22.6 82.2 144 838 +1992 8 26 0 9 TONY 31.3 75.1 105 795 +1953 1 17 0 27 ISAAC 40.2 7.7 141 469 +1966 6 12 12 17 JOYCE 57.3 327.8 93 739 +1992 9 17 0 6 CHRIS 54.5 125.8 114 111 +1973 8 28 18 10 CHRIS 18.7 212.2 55 148 +1959 11 6 12 25 OSCAR 14.7 133.9 104 831 +1957 12 9 18 20 CHRIS 10.5 128.0 139 113 +1976 6 1 0 1 DEBBY 41.6 185.0 32 8 +1973 3 20 6 5 WILLIAM 56.6 29.0 104 690 +1969 12 21 12 6 RAFAEL 51.3 323.8 105 784 +2004 4 28 12 14 MICHAEL 63.0 285.3 121 327 +1975 2 2 0 10 LESLIE 32.2 254.6 34 615 +1968 1 13 0 13 MICHAEL 61.9 167.0 91 534 +1997 7 4 0 13 GORDON 38.7 354.0 130 647 +1954 12 27 6 14 HELENE 26.5 188.1 52 156 +1982 7 28 6 14 FLORENCE 25.9 306.7 137 526 +1995 6 12 6 7 ALBERTO 44.3 45.5 161 32 +1988 5 11 12 2 HELENE 46.2 194.6 151 388 +1973 6 3 18 8 CHRIS 19.4 75.8 98 780 +1989 5 23 18 12 LESLIE 8.0 75.6 34 450 +1970 8 24 6 18 ERNESTO 56.4 267.4 144 193 +1955 12 20 6 1 PATTY 49.4 5.9 28 190 +1956 5 20 12 3 MICHAEL 36.7 205.0 160 743 +1995 5 19 6 9 MICHAEL 52.1 334.0 147 283 +1963 2 25 0 21 OSCAR 60.8 253.0 121 434 +1961 12 5 18 8 GORDON 68.1 321.3 93 811 +1975 12 8 0 2 MICHAEL 45.2 165.2 18 565 +1981 9 19 0 22 PATTY 14.7 31.4 132 608 +1987 10 28 6 3 BERYL 30.2 328.2 22 695 +1975 8 2 0 4 TONY 34.1 189.2 42 741 +1972 11 8 12 9 TONY 57.2 236.9 37 412 +1976 8 12 18 12 KIRK 9.7 104.1 18 450 +1953 8 10 18 4 PATTY 42.7 297.9 20 55 +1978 7 18 0 16 NADINE 65.9 127.0 114 423 +1953 4 2 6 4 MICHAEL 15.2 277.0 75 822 +1997 8 16 6 28 HELENE 45.6 208.1 52 192 +1980 6 1 12 26 OSCAR 31.9 111.6 18 495 +1985 2 7 0 19 LESLIE 18.8 111.2 160 260 +1995 3 6 0 21 HELENE 18.6 254.5 94 121 +1955 11 3 0 10 KIRK 25.2 31.6 135 512 +1955 5 9 0 14 GORDON 10.7 32.1 144 824 +1958 10 27 6 6 BERYL 12.3 44.9 105 571 +2004 3 14 12 5 WILLIAM 66.4 286.0 33 874 +1974 10 20 0 13 JOYCE 24.8 107.4 30 274 +1995 9 2 0 18 GORDON 8.1 102.6 158 347 +1962 6 16 6 9 PATTY 49.5 161.9 42 341 +1979 10 23 18 25 CHRIS 32.0 86.3 51 313 +1983 4 20 6 17 JOYCE 44.6 334.8 37 204 +1972 3 17 0 1 LESLIE 53.1 255.6 97 723 +1968 1 15 18 16 CHRIS 66.7 239.6 130 301 +1983 9 23 12 1 LESLIE 9.8 291.0 94 419 +1959 5 19 18 24 MICHAEL 30.2 163.4 74 680 +1983 11 8 0 3 MICHAEL 10.7 125.9 114 535 +1950 7 15 12 2 ALBERTO 34.9 71.3 21 652 +1978 5 3 6 14 KIRK 37.8 221.0 70 821 +1975 4 15 18 19 LESLIE 66.2 107.8 63 772 +1977 3 11 0 23 ALBERTO 53.1 23.8 16 316 +1952 1 6 6 26 ERNESTO 55.8 216.6 102 160 +1953 7 24 6 16 TONY 12.0 32.1 138 40 +1990 11 23 12 26 CHRIS 51.5 318.6 95 375 +1979 1 16 6 9 ERNESTO 43.4 167.1 29 668 +1985 3 2 18 7 ISAAC 49.4 307.6 31 574 +1967 6 11 6 10 OSCAR 31.8 23.6 137 172 +1959 8 15 0 28 WILLIAM 25.6 111.0 40 898 +1985 7 16 6 21 ALBERTO 45.0 68.5 17 265 +1955 11 7 0 19 LESLIE 61.4 44.0 121 682 +1963 10 23 12 7 HELENE 27.2 143.2 91 724 +1959 9 17 12 6 LESLIE 65.0 29.4 128 761 +1951 4 27 0 19 ERNESTO 63.7 242.0 108 79 +1964 3 19 0 3 SANDY 63.1 242.0 116 112 +2004 4 19 6 10 NADINE 52.8 261.4 158 27 +1999 10 28 6 22 SANDY 23.2 346.0 18 174 +1979 12 8 18 16 ALBERTO 37.6 244.8 55 524 +1995 11 16 0 24 OSCAR 10.5 72.0 48 616 +1962 3 23 6 6 ISAAC 37.2 65.7 153 847 +1950 6 5 0 8 GORDON 39.0 137.3 158 765 +1990 4 6 0 23 KIRK 20.0 176.6 143 743 +1956 9 14 12 12 KIRK 9.9 353.0 94 682 +1971 7 26 18 26 JOYCE 48.1 3.4 71 521 +1959 1 26 18 19 CHRIS 53.0 197.3 127 776 +1972 6 2 6 20 OSCAR 27.3 88.0 132 522 +1996 9 10 18 18 JOYCE 22.1 217.1 17 107 +1981 4 18 6 19 BERYL 40.7 215.0 26 866 +1960 5 28 18 18 ISAAC 28.7 275.9 96 144 +1998 11 28 6 17 ALBERTO 28.3 236.2 139 138 +1985 3 19 6 22 TONY 12.9 218.5 101 485 +1987 12 3 0 23 HELENE 64.0 285.8 127 745 +1956 5 18 0 14 WILLIAM 54.1 329.8 137 808 +1980 5 12 0 27 RAFAEL 35.8 151.4 164 555 +1987 4 11 6 8 CHRIS 27.1 21.6 62 695 +1983 2 20 0 19 MICHAEL 38.8 304.4 123 186 +1977 2 6 18 2 CHRIS 23.1 161.7 56 898 +1977 9 18 18 24 DEBBY 30.4 252.2 47 752 +1984 3 16 6 11 KIRK 8.1 328.1 85 133 +1986 3 6 0 11 GORDON 46.4 31.1 152 442 +1971 11 24 12 5 GORDON 59.4 352.4 51 84 +1968 3 2 6 24 SANDY 62.4 180.4 74 597 +1966 7 18 12 19 WILLIAM 37.5 264.7 58 548 +1993 1 18 6 27 TONY 30.4 159.7 108 782 +1982 9 2 12 21 ERNESTO 33.8 131.1 68 529 +1984 2 20 12 10 KIRK 21.1 186.1 160 427 +1987 1 8 18 12 PATTY 46.2 308.9 63 380 +1990 4 24 12 21 LESLIE 62.0 320.1 56 223 +1978 11 4 0 26 ISAAC 47.6 183.3 128 152 +1995 10 16 18 5 RAFAEL 46.6 167.1 124 195 +1993 6 26 6 1 HELENE 63.0 355.7 131 592 +2004 12 27 18 2 PATTY 59.3 98.0 108 428 +1961 11 16 6 10 ERNESTO 22.4 81.5 43 335 +1992 7 20 6 15 ALBERTO 40.4 174.4 83 843 +1994 3 16 12 22 ALBERTO 26.5 179.7 79 548 +1962 5 26 12 6 LESLIE 23.4 45.1 164 384 +1982 2 13 18 14 WILLIAM 54.0 291.5 129 490 +1976 12 14 12 21 CHRIS 28.8 151.8 115 174 +1991 8 14 0 21 OSCAR 33.7 301.5 30 780 +1997 3 20 6 4 ERNESTO 38.2 155.5 41 523 +2003 5 16 0 13 OSCAR 21.0 253.3 46 623 +1950 5 21 0 9 ISAAC 8.0 297.7 39 741 +1984 5 4 12 26 SANDY 43.9 306.5 114 832 +1982 7 12 6 23 ISAAC 43.9 259.8 52 619 +1961 6 24 6 9 LESLIE 25.9 329.8 82 230 +1958 1 27 18 22 PATTY 30.6 316.0 79 255 +1975 9 8 6 6 KIRK 28.4 213.5 146 41 +1985 2 22 6 24 VALERIE 13.7 28.1 161 206 +1959 1 6 12 16 PATTY 7.8 307.9 36 6 +2002 11 16 12 7 ALBERTO 50.8 311.4 112 822 +1989 1 16 6 8 RAFAEL 66.1 70.2 67 707 +1995 4 5 18 1 OSCAR 53.8 178.7 121 279 +1996 4 7 12 9 LESLIE 58.9 61.8 138 214 +1975 7 3 18 23 SANDY 40.3 7.7 96 8 +1992 5 2 6 22 DEBBY 21.9 146.5 142 292 +1955 11 10 18 3 OSCAR 64.8 345.3 129 332 +1958 8 1 18 19 NADINE 55.5 311.1 137 689 +1954 8 18 6 18 HELENE 17.6 76.1 20 228 +1970 4 19 18 15 CHRIS 21.3 344.1 157 456 +2002 5 4 12 1 CHRIS 23.4 290.2 18 675 +1958 2 26 18 16 HELENE 52.0 80.2 136 548 +1974 5 3 18 13 MICHAEL 53.8 355.4 107 112 +1954 4 19 18 13 HELENE 42.5 356.6 39 730 +1958 4 4 6 9 ALBERTO 46.1 275.8 46 873 +1953 4 16 18 7 ISAAC 67.9 309.6 147 143 +1974 9 17 6 1 DEBBY 55.5 206.1 42 835 +1957 7 17 0 7 VALERIE 49.1 103.4 52 137 +1968 12 13 0 9 ALBERTO 59.1 339.5 158 339 +1966 12 20 6 26 WILLIAM 43.1 357.4 141 391 +1996 10 6 0 15 VALERIE 19.4 49.3 82 369 +1958 11 5 18 26 JOYCE 66.4 297.1 84 449 +1980 3 18 18 24 WILLIAM 41.0 247.8 59 565 +1976 10 9 12 20 ALBERTO 26.5 80.8 69 418 +1958 7 7 0 17 MICHAEL 69.1 189.7 145 674 +1985 12 6 0 19 FLORENCE 55.5 280.3 99 821 +2002 2 17 0 2 ALBERTO 54.0 139.3 105 549 +1965 7 24 0 2 LESLIE 48.0 338.9 94 457 +1991 4 25 18 25 DEBBY 18.9 237.5 47 384 +2000 4 14 6 25 NADINE 59.3 211.4 11 182 +1978 2 5 0 6 ERNESTO 66.6 278.5 68 417 +1994 6 2 12 2 OSCAR 24.9 208.8 41 838 +2000 7 13 0 13 BERYL 47.8 322.9 63 625 +1967 11 28 6 1 BERYL 27.4 213.0 59 14 +1985 9 5 0 5 PATTY 58.4 37.2 109 277 +1968 12 3 12 15 RAFAEL 38.8 188.9 94 94 +1969 10 7 18 10 NADINE 26.9 52.1 62 813 +2001 10 1 6 17 JOYCE 18.6 51.1 116 321 +1992 12 25 18 22 MICHAEL 52.8 341.7 160 214 +1969 9 26 0 26 ALBERTO 51.2 304.0 73 314 +1988 3 17 12 8 HELENE 30.3 151.0 132 2 +1991 10 6 0 2 TONY 28.7 68.2 96 345 +1968 12 20 0 14 KIRK 54.6 183.5 66 464 +1954 2 21 0 26 LESLIE 48.7 173.6 158 174 +1980 11 21 0 18 JOYCE 47.7 165.3 65 659 +1957 12 16 6 3 WILLIAM 16.4 332.7 91 147 +1988 10 8 6 22 LESLIE 43.6 27.5 144 726 +1999 7 3 18 20 RAFAEL 38.6 22.9 118 364 +1959 10 19 6 7 KIRK 58.0 291.4 26 630 +2000 1 20 6 17 KIRK 46.8 305.0 158 202 +1950 5 11 18 11 DEBBY 57.9 8.0 84 290 +1967 11 26 18 11 PATTY 63.6 204.7 35 495 +1972 7 26 0 5 BERYL 35.8 164.6 47 614 +1960 4 27 18 13 ALBERTO 13.5 180.5 160 696 +1971 7 26 0 20 GORDON 56.6 124.5 83 314 +1970 9 20 0 2 ISAAC 61.2 352.9 74 178 +1978 3 4 12 18 WILLIAM 55.9 122.3 50 877 +2002 3 14 12 19 WILLIAM 68.6 309.0 14 267 +1974 1 1 0 6 PATTY 44.6 128.4 53 819 +1993 11 23 18 11 BERYL 68.4 295.2 68 494 +1950 9 13 18 28 CHRIS 48.9 131.8 106 560 +1983 4 19 0 14 PATTY 40.7 178.9 95 571 +1972 11 2 18 5 RAFAEL 25.2 152.5 146 886 +1980 7 28 0 2 OSCAR 41.7 182.7 117 877 +1994 5 5 6 15 TONY 17.7 164.3 94 181 +1984 4 7 12 6 ALBERTO 45.1 130.7 37 845 +1957 1 10 6 4 OSCAR 10.0 17.4 82 175 +1992 11 7 6 13 LESLIE 64.8 31.9 71 493 +1991 12 12 18 12 MICHAEL 34.2 172.6 20 817 +1972 9 10 18 24 DEBBY 54.4 287.1 10 585 +1981 5 26 0 2 ISAAC 27.6 248.8 34 721 +1969 12 10 12 1 TONY 68.8 103.2 25 383 +1955 6 28 6 27 ALBERTO 62.7 42.4 84 887 +2003 10 23 6 27 DEBBY 51.8 318.1 117 764 +1991 12 8 12 13 ERNESTO 64.4 203.4 15 726 +1954 12 26 0 23 GORDON 25.6 25.5 124 169 +1992 1 4 18 9 NADINE 28.3 339.9 61 355 +1955 4 9 0 17 JOYCE 8.5 234.0 106 803 +2001 4 17 0 26 FLORENCE 18.4 223.3 134 35 +1995 11 16 0 18 ALBERTO 44.9 270.1 92 745 +1959 2 21 12 26 ISAAC 52.9 350.9 11 591 +1953 2 8 18 12 CHRIS 62.3 223.4 98 706 +1958 4 14 18 12 VALERIE 19.6 151.1 53 43 +1959 4 27 12 10 ISAAC 19.1 155.9 31 690 +1985 9 19 6 19 CHRIS 68.7 109.2 130 884 +1988 10 25 12 23 FLORENCE 29.5 280.3 90 707 +1997 7 6 18 21 TONY 58.5 331.2 55 858 +1987 5 16 18 6 ISAAC 57.7 130.3 81 672 +1962 1 15 0 8 LESLIE 11.3 211.6 151 897 +1981 2 22 0 5 RAFAEL 42.1 200.4 125 367 +1975 5 10 0 25 RAFAEL 15.6 35.6 59 704 +1986 12 21 6 14 TONY 52.5 187.8 121 889 +2000 12 28 0 22 SANDY 28.1 159.7 148 721 +2002 4 9 12 18 BERYL 26.6 263.2 78 824 +1974 2 11 0 26 VALERIE 25.1 129.4 91 764 +1954 11 20 12 11 PATTY 20.3 129.9 78 798 +1999 1 20 0 8 CHRIS 9.0 276.7 24 9 +1999 12 20 6 21 NADINE 34.1 176.3 48 478 +2002 9 7 18 18 WILLIAM 26.8 257.8 38 246 +1983 11 9 18 21 WILLIAM 14.4 64.8 121 762 +1952 5 5 6 25 KIRK 18.8 105.3 37 278 +1950 3 5 6 20 TONY 35.3 309.4 148 76 +1990 10 7 0 13 ALBERTO 57.1 40.4 23 859 +1958 12 18 12 18 RAFAEL 41.2 125.9 103 648 +1957 8 23 6 4 KIRK 46.2 174.3 145 465 +2001 6 20 0 6 BERYL 15.9 320.4 110 367 +1979 1 27 6 5 GORDON 50.5 354.7 151 793 +1997 10 8 0 10 DEBBY 20.7 67.1 71 140 +1996 12 15 6 5 FLORENCE 17.0 47.3 77 526 +1978 9 1 18 25 SANDY 49.7 40.3 107 319 +1999 7 8 12 4 KIRK 8.5 16.3 154 519 +1985 8 20 18 11 VALERIE 66.6 297.9 21 82 +1994 5 7 0 26 ALBERTO 35.6 324.6 66 441 +1993 5 8 0 9 FLORENCE 41.7 39.2 135 860 +1975 4 21 12 22 TONY 14.7 176.5 46 341 +1955 9 21 0 24 ALBERTO 36.4 342.1 72 174 +2003 10 26 18 25 TONY 53.9 314.5 27 260 +1953 8 1 18 2 TONY 47.2 3.7 58 836 +1959 9 19 0 13 VALERIE 37.5 59.7 10 230 +1954 6 20 6 2 OSCAR 32.8 215.6 138 466 +1967 12 23 18 24 GORDON 30.3 274.8 82 530 +1995 6 14 18 14 PATTY 15.9 230.2 111 313 +1985 12 2 18 10 ISAAC 40.6 179.8 158 39 +2001 2 22 18 20 HELENE 55.0 19.0 45 434 +1997 9 4 12 21 VALERIE 51.7 280.5 99 205 +1968 8 5 6 7 CHRIS 28.0 274.9 51 887 +1982 9 16 6 23 ISAAC 14.6 69.9 80 424 +1996 2 15 0 19 TONY 64.6 93.5 40 841 +1981 6 6 6 27 VALERIE 17.9 131.5 82 754 +1960 1 15 12 24 HELENE 46.1 185.6 84 108 +1977 6 17 18 5 TONY 35.8 170.4 145 108 +1960 3 7 6 14 ALBERTO 60.9 146.8 70 101 +1969 1 5 12 1 RAFAEL 49.1 43.1 67 461 +1968 6 23 6 24 LESLIE 46.9 262.7 115 188 +2002 2 17 6 15 BERYL 28.8 168.7 25 790 +1950 1 20 0 15 HELENE 58.5 5.1 128 97 +1961 6 15 18 10 ISAAC 45.3 307.2 139 339 +1977 8 3 18 27 TONY 35.9 25.9 84 594 +1998 12 21 18 25 ISAAC 22.1 54.0 26 649 +1970 5 14 18 24 FLORENCE 16.3 174.3 62 694 +1967 11 28 18 5 CHRIS 31.5 114.7 62 424 +1976 5 10 6 7 OSCAR 30.1 22.1 156 701 +1984 6 19 6 2 ALBERTO 23.1 27.6 158 533 +1981 10 4 6 19 LESLIE 41.8 80.8 149 818 +1984 11 8 18 14 ERNESTO 61.5 8.0 49 413 +1992 9 3 18 8 ISAAC 32.9 95.8 102 217 +1998 3 17 18 18 GORDON 56.0 17.7 110 379 +1978 7 2 18 6 CHRIS 28.1 139.5 59 53 +1994 8 22 6 20 ERNESTO 28.3 172.7 115 534 +1978 5 9 0 22 HELENE 57.0 268.3 32 673 +1959 10 5 18 10 VALERIE 53.5 126.2 44 81 +1985 12 21 0 7 RAFAEL 50.4 99.2 114 393 +1969 1 19 0 13 VALERIE 63.4 256.1 27 5 +2003 7 5 12 1 VALERIE 28.3 84.9 59 890 +2004 6 16 12 13 HELENE 56.9 204.9 145 833 +1989 3 16 0 17 DEBBY 31.2 214.4 38 420 +1957 2 4 6 10 RAFAEL 34.9 26.3 50 532 +1973 11 2 0 1 VALERIE 58.6 86.6 15 392 +2004 2 25 12 19 CHRIS 59.2 254.4 128 645 +1961 6 27 6 17 LESLIE 58.7 137.7 71 883 +1988 3 20 6 12 PATTY 65.8 328.9 15 794 +1977 4 11 6 10 ISAAC 11.6 188.1 96 204 +1979 10 18 6 1 ISAAC 17.1 106.1 49 632 +1984 6 15 0 8 VALERIE 32.5 37.1 12 102 +1964 9 17 18 5 RAFAEL 48.3 47.1 131 250 +1979 4 24 18 20 CHRIS 15.2 321.6 67 475 +1963 6 8 6 11 HELENE 29.8 33.8 88 277 +1985 10 28 12 15 PATTY 64.8 142.4 142 425 +2002 5 13 6 10 VALERIE 51.8 139.4 20 899 +1983 12 9 12 16 RAFAEL 42.6 286.9 145 496 +1994 7 14 18 2 BERYL 17.6 138.3 27 147 +1984 6 22 12 26 WILLIAM 35.1 177.5 148 174 +1975 1 11 6 12 CHRIS 22.7 74.1 32 464 +1957 6 4 18 19 TONY 15.7 200.7 26 67 +1981 3 27 18 21 MICHAEL 49.4 252.8 164 609 +1971 11 11 18 19 VALERIE 7.7 327.0 123 197 +1981 3 18 6 23 JOYCE 8.6 247.3 10 49 +1993 3 1 18 7 ERNESTO 30.9 311.3 66 137 +1959 10 9 0 16 TONY 67.9 19.4 113 31 +1987 1 10 12 3 GORDON 18.1 99.9 87 551 +1972 5 23 12 8 BERYL 35.4 287.7 107 745 +1992 10 28 6 21 KIRK 18.2 137.2 155 73 +1981 3 6 6 22 RAFAEL 33.0 34.0 115 487 +1954 7 8 6 15 SANDY 12.4 44.9 58 792 +1986 12 6 0 10 ERNESTO 43.5 282.6 101 227 +1974 9 25 12 9 SANDY 39.1 297.5 49 280 +1962 5 15 0 11 OSCAR 21.6 118.4 127 154 +1975 9 9 6 28 ISAAC 28.4 346.6 42 120 +1959 10 1 6 15 ISAAC 15.1 175.2 88 611 +1998 7 3 0 5 RAFAEL 18.7 342.2 53 305 +1961 1 7 12 1 BERYL 14.4 328.2 157 634 +1996 3 24 6 10 LESLIE 24.7 113.9 20 843 +1996 5 14 12 11 MICHAEL 51.7 121.9 124 297 +1963 1 6 0 27 ALBERTO 34.7 324.9 126 173 +1956 8 7 12 7 HELENE 32.8 54.7 95 814 +1979 2 16 0 16 GORDON 19.4 226.5 131 540 +1954 3 23 12 1 HELENE 11.4 295.5 96 339 +1964 3 19 12 22 SANDY 49.8 279.7 40 380 +1980 12 20 18 19 ISAAC 54.2 72.1 88 14 +1962 12 11 6 26 ISAAC 58.7 317.0 88 455 +1992 4 12 0 4 ERNESTO 69.5 159.2 33 562 +1950 9 15 6 28 PATTY 65.4 304.1 17 542 +1999 5 19 18 28 ISAAC 9.3 10.5 65 51 +1994 7 1 6 27 ERNESTO 56.0 37.0 133 552 +1978 6 12 0 20 PATTY 39.0 330.2 42 271 +1958 2 19 0 15 DEBBY 15.1 7.3 55 117 +1967 2 15 18 16 CHRIS 37.4 217.1 46 700 +1994 6 17 12 10 KIRK 25.7 84.5 55 19 +1973 11 4 18 11 OSCAR 32.1 255.7 148 826 +2000 11 22 0 10 PATTY 66.4 325.9 124 590 +1980 5 9 6 25 JOYCE 61.4 254.3 125 118 +1998 2 15 0 20 OSCAR 12.2 82.8 137 285 +1953 11 18 12 24 JOYCE 43.4 246.7 137 677 +1976 6 11 12 1 WILLIAM 42.2 233.3 25 71 +1993 1 10 6 13 TONY 19.4 153.6 81 457 +1960 12 14 0 24 ALBERTO 17.8 281.2 65 423 +1950 10 6 6 2 ALBERTO 38.4 86.1 85 426 +1955 6 12 12 18 ERNESTO 9.2 226.7 143 24 +1960 8 23 6 24 KIRK 12.7 100.2 95 889 +1993 4 4 12 9 GORDON 55.4 141.7 66 125 +1997 7 19 12 11 VALERIE 60.3 78.5 72 567 +1984 6 17 12 4 DEBBY 55.1 181.6 72 790 +1963 3 16 0 23 HELENE 20.5 264.6 163 598 +1981 5 15 0 17 ISAAC 13.4 38.7 21 55 +1979 5 7 18 28 NADINE 42.1 110.1 162 629 +1968 5 10 12 17 GORDON 45.3 331.1 125 671 +1986 12 26 6 7 VALERIE 7.0 23.6 91 42 +1990 4 26 12 24 PATTY 19.9 307.6 17 97 +1999 12 2 12 26 CHRIS 24.3 50.8 104 154 +1977 6 23 0 17 NADINE 14.5 198.1 24 451 +1990 10 18 12 14 FLORENCE 44.6 230.7 136 181 +2004 4 17 18 6 VALERIE 44.6 97.9 46 85 +1964 9 22 0 17 FLORENCE 61.7 326.8 133 321 +1998 11 14 6 24 KIRK 28.4 262.2 49 860 +1967 3 3 18 14 RAFAEL 39.1 207.5 38 421 +1953 10 11 12 18 VALERIE 32.6 66.5 73 33 +1963 3 8 18 13 RAFAEL 32.7 87.8 142 199 +1971 12 25 0 3 JOYCE 55.8 15.4 93 56 +1972 11 24 18 9 ERNESTO 65.8 42.0 75 313 +2003 9 9 0 3 DEBBY 37.4 316.1 38 360 +1991 4 17 6 4 GORDON 45.5 27.5 24 245 +2000 4 3 18 8 BERYL 49.6 118.9 124 628 +2004 11 22 6 27 HELENE 7.8 144.6 140 378 +1992 7 3 0 4 ERNESTO 38.1 290.1 21 627 +1988 3 10 0 11 ISAAC 7.5 222.1 60 832 +1957 4 17 0 25 VALERIE 9.8 271.4 73 194 +1983 7 1 6 14 TONY 30.6 86.7 74 242 +1977 10 5 0 20 FLORENCE 57.6 290.1 137 22 +1985 4 19 6 28 JOYCE 30.9 227.9 26 310 +1981 11 11 12 18 FLORENCE 52.9 305.5 150 462 +1989 9 20 6 26 JOYCE 24.8 13.5 127 538 +1979 4 7 12 8 KIRK 11.5 278.9 110 711 +1971 4 24 18 17 SANDY 22.1 243.1 114 764 +1971 8 12 6 14 HELENE 34.3 167.3 72 736 +1958 10 10 6 4 LESLIE 42.0 28.2 59 144 +1950 10 8 12 16 NADINE 49.1 14.5 28 696 +1977 11 3 6 14 DEBBY 52.5 164.0 39 123 +1955 2 8 0 17 KIRK 45.4 32.6 86 379 +1970 12 21 0 18 ISAAC 69.1 356.0 71 490 +1991 1 7 12 17 RAFAEL 63.1 103.1 72 124 +1952 1 8 0 8 RAFAEL 7.1 265.7 109 324 +1964 3 26 6 10 VALERIE 42.5 252.0 85 212 +1975 3 21 18 8 OSCAR 54.6 346.3 34 575 +1959 9 1 12 21 BERYL 13.3 262.2 54 809 +1963 1 21 0 23 ALBERTO 56.4 123.7 149 431 +2002 6 3 12 28 LESLIE 48.3 20.6 50 587 +1976 3 24 0 11 FLORENCE 67.4 144.7 139 194 +1972 1 5 12 22 LESLIE 36.3 335.2 74 102 +1950 5 1 0 11 JOYCE 12.2 27.6 119 701 +1994 10 5 18 27 ALBERTO 8.6 131.8 129 392 +1991 9 25 18 12 DEBBY 59.7 66.3 116 804 +1992 2 4 6 25 ALBERTO 63.6 316.3 22 726 +2003 8 20 6 10 ALBERTO 41.4 196.2 43 726 +1990 6 20 6 20 GORDON 27.0 307.8 150 391 +1956 7 26 0 10 PATTY 67.1 128.4 161 147 +1985 11 17 18 24 CHRIS 36.0 291.6 11 441 +1951 7 20 6 13 MICHAEL 43.6 135.1 163 374 +1996 9 3 18 19 HELENE 69.7 274.8 122 220 +1991 1 20 18 22 SANDY 19.6 293.0 109 70 +2000 11 11 18 13 FLORENCE 24.3 315.6 15 718 +1985 11 6 12 21 LESLIE 38.9 67.2 137 50 +1985 3 7 18 14 WILLIAM 32.6 220.3 115 634 +1971 1 12 12 4 MICHAEL 48.8 105.9 46 789 +1983 3 24 18 21 BERYL 42.7 54.9 38 696 +1952 6 4 12 9 OSCAR 39.7 68.6 115 577 +1988 3 24 18 13 HELENE 54.5 329.6 94 613 +1978 9 27 12 6 NADINE 52.7 235.6 90 824 +1967 5 8 12 25 DEBBY 46.2 70.0 51 544 +1965 3 16 18 7 LESLIE 49.4 332.1 40 423 +1977 8 22 6 22 BERYL 19.7 225.2 146 281 +1978 11 17 12 14 RAFAEL 8.8 75.0 139 66 +1992 3 25 12 6 ALBERTO 69.9 82.7 141 789 +1963 5 27 6 10 RAFAEL 29.9 309.5 105 308 +1969 8 12 6 14 OSCAR 36.5 226.1 78 291 +1953 7 19 6 26 GORDON 58.7 326.9 148 303 +1972 10 27 6 21 JOYCE 18.5 4.7 89 36 +1987 12 6 18 8 NADINE 7.5 317.6 91 240 +1962 10 14 0 14 CHRIS 65.7 1.2 107 498 +2002 10 20 18 23 JOYCE 16.8 195.6 63 825 +2001 6 3 6 15 OSCAR 56.5 267.5 59 63 +1967 10 19 6 27 TONY 22.6 171.0 69 565 +1981 10 9 12 2 OSCAR 27.5 330.8 157 867 +1977 4 21 18 19 DEBBY 9.0 28.2 24 41 +1988 3 17 12 1 PATTY 27.7 197.9 57 16 +1970 12 25 18 18 DEBBY 41.7 126.3 86 546 +1997 2 1 12 18 RAFAEL 46.6 353.2 17 670 +1997 2 12 0 26 BERYL 34.4 157.3 135 40 +1993 11 24 12 6 HELENE 45.5 286.9 163 472 +1988 4 21 12 3 FLORENCE 56.6 335.1 149 329 +1960 10 6 12 27 OSCAR 36.9 346.2 104 53 +1988 12 23 6 25 BERYL 60.7 98.1 78 395 +1960 3 16 12 3 JOYCE 60.7 175.8 103 523 +1995 10 17 12 7 NADINE 34.9 165.5 44 169 +1996 3 15 18 8 GORDON 53.0 251.1 155 93 +1997 5 27 12 22 RAFAEL 19.1 232.3 87 892 +1999 11 5 6 12 SANDY 64.5 232.8 98 104 +1978 1 27 0 19 VALERIE 57.1 52.8 16 461 +1985 3 18 12 21 DEBBY 52.6 2.4 23 1 +1956 5 17 6 26 ALBERTO 67.3 212.6 148 108 +1977 10 20 18 1 HELENE 27.1 341.9 24 579 +1951 3 8 0 22 ISAAC 52.1 263.1 46 550 +1967 6 6 12 14 ALBERTO 46.2 228.7 62 898 +1990 10 16 12 4 ISAAC 33.1 99.9 13 374 +1953 1 1 6 15 FLORENCE 28.6 294.1 135 457 +1989 1 7 0 11 OSCAR 53.1 3.6 103 518 +1968 1 5 12 21 WILLIAM 68.0 9.8 121 474 +1985 7 25 0 9 CHRIS 24.2 351.9 35 624 +1964 7 22 6 13 NADINE 58.5 43.9 68 814 +2001 2 12 12 6 PATTY 21.0 354.1 127 672 +1951 1 15 0 1 VALERIE 22.6 288.0 27 416 +1994 7 15 0 7 MICHAEL 15.1 99.1 23 833 +1973 5 19 12 10 GORDON 46.9 326.8 159 500 +1978 9 15 12 14 LESLIE 30.7 8.8 148 750 +1957 11 25 12 16 SANDY 66.8 334.8 92 326 +1954 7 19 12 4 DEBBY 61.1 352.8 133 347 +1978 7 4 18 27 ALBERTO 13.2 323.5 79 280 +1965 2 19 12 28 MICHAEL 32.9 168.4 121 336 +1968 11 11 12 25 ERNESTO 62.8 238.0 86 870 +1985 12 19 12 10 TONY 38.5 116.1 28 69 +1954 1 27 18 7 OSCAR 7.2 226.4 88 704 +1951 7 8 18 12 ALBERTO 66.3 147.2 45 154 +1957 9 13 18 21 RAFAEL 60.8 41.4 162 520 +1985 6 3 6 19 WILLIAM 7.7 55.8 58 708 +1978 6 8 0 9 FLORENCE 41.7 223.7 79 557 +1952 9 5 6 4 HELENE 43.9 343.2 138 645 +1953 9 15 18 26 CHRIS 34.3 239.7 146 72 +2001 11 6 6 22 BERYL 31.2 175.4 81 437 +1958 3 6 6 3 TONY 18.4 69.2 71 217 +1953 4 10 18 15 DEBBY 68.3 14.7 59 249 +1956 11 7 12 2 ALBERTO 55.8 222.9 163 488 +1966 3 13 0 24 ISAAC 45.7 288.8 112 862 +1952 1 14 6 9 OSCAR 61.7 172.2 119 811 +2003 12 15 12 13 TONY 16.5 95.6 130 326 +1996 7 22 18 1 CHRIS 18.7 189.9 131 659 +1975 1 10 6 2 ALBERTO 21.5 148.7 111 705 +1952 6 27 0 20 LESLIE 54.6 352.0 164 525 +1961 8 19 6 10 JOYCE 47.5 245.1 43 314 +1981 8 12 18 23 RAFAEL 12.3 303.5 135 142 +1956 6 22 12 1 OSCAR 64.5 295.2 131 195 +1977 1 12 18 10 FLORENCE 52.7 4.0 100 806 +1996 12 26 6 10 JOYCE 28.1 162.6 126 117 +1980 4 8 6 6 ISAAC 63.3 171.6 160 540 +1967 2 21 6 14 ERNESTO 39.2 118.9 40 395 +1953 6 18 6 7 SANDY 37.8 165.1 125 2 +1998 8 19 18 23 TONY 33.6 309.4 96 492 +1971 10 1 12 3 RAFAEL 9.4 283.2 47 274 +1983 6 21 12 28 MICHAEL 20.7 264.1 48 144 +1978 4 21 0 16 DEBBY 39.4 170.8 20 772 +1988 5 11 12 12 RAFAEL 63.6 151.1 119 406 +1964 12 27 6 15 ISAAC 19.9 308.3 82 407 +1965 12 16 6 21 OSCAR 14.1 117.6 112 216 +1950 3 2 6 8 PATTY 15.4 114.6 25 76 +1975 7 4 12 17 JOYCE 28.2 18.5 160 634 +1962 6 3 18 17 ERNESTO 59.3 130.7 134 141 +1958 11 1 12 17 CHRIS 64.8 354.5 107 222 +1987 8 18 18 9 ERNESTO 13.8 324.3 89 822 +1988 1 5 12 26 MICHAEL 23.1 26.5 22 122 +1979 3 21 6 14 DEBBY 25.5 306.8 73 176 +1966 11 19 18 11 RAFAEL 53.9 226.7 82 201 +1990 4 11 0 15 SANDY 15.4 251.0 127 221 +1968 4 16 0 16 SANDY 21.2 80.9 119 604 +1961 7 27 18 22 CHRIS 28.9 232.5 85 439 +2000 10 10 18 24 VALERIE 39.2 339.5 164 47 +1982 10 9 12 25 ISAAC 47.4 355.6 112 588 +1973 7 4 12 25 ERNESTO 36.0 165.4 46 58 +1963 9 19 12 4 MICHAEL 12.7 113.4 36 227 +1960 12 20 6 9 ALBERTO 43.1 246.5 46 348 +1961 7 21 6 21 LESLIE 18.9 192.9 24 279 +1987 8 7 12 22 FLORENCE 47.4 3.8 53 579 +1967 2 6 12 14 SANDY 54.0 267.6 29 628 +1970 4 20 18 6 ALBERTO 51.3 77.9 164 878 +1958 10 22 0 7 FLORENCE 10.7 298.9 40 363 +1984 7 19 6 2 DEBBY 66.3 191.3 127 106 +1955 8 4 18 26 SANDY 65.2 79.5 144 29 +1987 6 18 6 18 LESLIE 41.0 34.8 66 840 +2004 9 26 6 2 GORDON 20.2 139.5 20 578 +1978 8 25 0 10 LESLIE 28.2 35.8 138 136 +1954 2 27 6 8 ERNESTO 45.6 140.2 129 803 +1962 5 23 6 28 BERYL 8.8 105.6 21 520 +1967 6 25 0 5 ISAAC 10.3 290.4 59 665 +2004 7 17 18 25 BERYL 14.8 267.9 122 249 +1997 9 18 6 8 NADINE 60.8 45.9 148 687 +1967 1 7 12 28 SANDY 20.6 63.8 153 81 +1968 6 19 12 19 DEBBY 52.1 105.0 124 631 +1997 11 25 12 9 BERYL 49.3 357.7 138 828 +1968 2 20 0 6 CHRIS 16.4 245.4 131 869 +1961 9 5 18 26 RAFAEL 48.8 71.6 144 735 +1993 1 19 0 22 MICHAEL 49.6 171.6 34 786 +1995 12 9 6 24 SANDY 46.5 206.8 50 529 +1973 6 18 12 13 GORDON 41.7 286.4 50 225 +1982 9 15 6 5 FLORENCE 9.0 260.1 44 689 +1952 6 20 0 25 JOYCE 63.3 262.0 64 770 +1955 8 23 18 12 NADINE 28.5 34.6 32 39 +1963 8 22 0 23 HELENE 53.9 188.3 151 766 +2004 8 3 0 3 DEBBY 43.0 37.3 12 379 +1991 11 23 6 10 HELENE 35.1 164.2 82 701 +1960 1 28 6 5 WILLIAM 13.0 308.1 97 879 +2001 11 9 6 28 DEBBY 41.1 163.1 60 552 +1986 5 16 0 7 BERYL 43.6 318.7 135 847 +1984 7 2 12 17 WILLIAM 11.0 88.5 63 341 +1974 1 4 12 8 DEBBY 51.8 305.6 113 361 +1997 4 23 18 5 RAFAEL 42.1 117.9 11 351 +1963 5 3 18 7 ERNESTO 43.2 286.5 78 298 +1955 3 16 12 26 FLORENCE 42.4 307.8 119 249 +1953 9 15 0 13 GORDON 28.6 232.7 31 776 +1959 9 10 12 9 MICHAEL 55.2 151.8 53 252 +1972 1 3 12 14 MICHAEL 47.6 180.6 73 356 +1959 8 21 12 6 ISAAC 46.1 68.2 153 408 +1990 1 4 6 9 VALERIE 16.0 64.1 126 849 +1952 8 8 0 10 HELENE 53.1 154.0 27 706 +1982 12 4 0 8 GORDON 59.0 125.9 148 187 +1971 12 1 18 28 FLORENCE 46.5 22.7 113 757 +1983 12 28 0 5 DEBBY 42.0 250.6 78 625 +1987 10 27 0 2 WILLIAM 57.6 308.3 31 727 +1980 1 12 0 9 ALBERTO 21.7 240.7 34 158 +1991 2 3 6 28 ERNESTO 61.0 193.9 135 306 +1995 8 7 12 24 OSCAR 61.3 253.5 116 123 +1952 5 11 6 2 TONY 48.0 67.5 40 758 +1970 2 8 12 23 KIRK 18.1 305.3 136 458 +1995 5 26 0 5 MICHAEL 11.1 104.0 124 113 +1991 12 15 12 10 JOYCE 37.2 97.3 101 611 +1986 9 1 12 19 HELENE 46.8 0.3 89 71 +1989 8 27 12 22 JOYCE 44.1 20.5 113 59 +2002 5 2 12 21 JOYCE 54.1 329.7 94 852 +1974 3 8 18 25 LESLIE 43.5 304.9 144 191 +1977 8 12 12 9 SANDY 39.9 56.5 59 34 +1996 3 3 12 21 BERYL 34.4 72.5 106 830 +1998 11 17 12 15 JOYCE 42.7 216.5 155 303 +1964 10 6 12 17 KIRK 36.7 298.4 78 140 +1971 6 22 6 11 JOYCE 59.8 155.7 127 6 +1998 12 5 6 17 KIRK 26.3 179.4 61 54 +1988 3 8 18 5 FLORENCE 68.5 333.9 102 849 +1956 8 21 12 20 OSCAR 63.6 131.0 127 829 +1984 1 1 6 10 OSCAR 58.4 189.0 61 360 +1994 4 16 18 17 NADINE 37.4 129.1 118 402 +1966 1 21 0 17 SANDY 50.7 207.3 30 701 +1960 2 18 0 17 SANDY 24.3 22.8 116 244 +1981 10 11 12 3 NADINE 43.5 163.6 10 60 +2001 5 1 18 19 BERYL 18.0 50.2 137 844 +1992 7 25 18 11 RAFAEL 52.5 163.2 117 844 +1988 2 23 0 18 VALERIE 56.0 44.0 28 750 +1994 10 17 18 24 WILLIAM 29.2 289.4 161 511 +1963 9 18 6 27 VALERIE 12.5 281.2 96 856 +1975 11 7 0 24 ALBERTO 21.0 150.4 62 80 +1976 9 23 18 8 PATTY 64.3 310.1 148 558 +1967 7 26 6 27 OSCAR 65.0 104.7 55 585 +2001 10 24 18 2 LESLIE 11.4 340.0 45 243 +1964 1 12 12 21 JOYCE 59.4 18.2 158 400 +1960 2 3 18 1 SANDY 12.8 44.0 154 31 +1999 6 11 18 23 FLORENCE 52.9 49.3 134 525 +1988 7 25 0 25 NADINE 49.1 202.8 67 161 +1976 1 17 12 20 MICHAEL 15.4 195.5 97 749 +1966 12 14 12 18 OSCAR 57.9 48.5 100 866 +1955 4 12 18 27 GORDON 18.4 285.9 94 314 +2003 11 1 6 12 BERYL 53.7 112.7 107 601 +1994 10 25 12 26 DEBBY 26.0 187.7 139 383 +1952 5 18 6 9 PATTY 26.4 286.4 162 547 +1979 4 8 0 13 MICHAEL 53.6 283.1 74 284 +1989 11 9 12 26 HELENE 38.7 303.3 85 380 +1992 8 12 6 11 HELENE 55.7 153.1 85 319 +1979 9 8 6 15 TONY 38.4 317.7 155 616 +1999 7 12 0 2 ISAAC 14.8 44.5 67 704 +1955 2 19 6 2 TONY 8.6 69.5 44 547 +1958 2 27 18 11 DEBBY 45.9 324.4 164 575 +1989 4 11 18 19 SANDY 41.4 219.8 86 76 +1997 3 17 18 27 OSCAR 7.6 334.8 121 532 +2003 2 20 12 17 FLORENCE 36.8 131.9 52 355 +1989 9 17 6 27 ISAAC 14.9 314.7 61 394 +1967 2 22 0 11 FLORENCE 19.8 70.1 144 320 +1982 8 11 0 16 ALBERTO 45.5 240.0 140 293 +1956 5 2 12 14 ALBERTO 7.2 200.4 102 484 +1989 1 4 6 25 RAFAEL 44.4 348.7 51 476 +1983 7 18 12 22 OSCAR 53.1 98.5 148 829 +2002 2 10 18 8 ERNESTO 32.0 176.2 37 56 +1964 11 4 6 18 VALERIE 39.1 53.1 42 73 +1953 2 21 12 19 OSCAR 32.4 276.8 136 169 +1979 8 18 12 20 VALERIE 18.6 113.6 55 749 +1998 2 18 12 17 ERNESTO 54.5 299.0 141 279 +2000 10 24 18 19 ERNESTO 10.1 246.8 147 633 +1959 1 9 12 14 KIRK 23.3 118.6 131 882 +1960 7 22 0 15 BERYL 24.7 305.8 156 457 +1981 7 5 12 20 GORDON 16.5 158.4 27 87 +1957 5 17 18 2 ISAAC 37.7 95.2 108 115 diff --git a/benchmarks/new_opencl/nearn/cane4_2.db b/benchmarks/new_opencl/nearn/cane4_2.db new file mode 100755 index 00000000..767876a2 --- /dev/null +++ b/benchmarks/new_opencl/nearn/cane4_2.db @@ -0,0 +1,10691 @@ +1951 3 8 6 5 ISAAC 9.6 104.8 21 322 +1958 3 9 6 26 FLORENCE 46.3 127.4 92 627 +1961 1 25 12 9 HELENE 30.8 126.3 163 42 +1956 11 21 0 15 JOYCE 68.0 320.5 21 433 +1973 11 18 18 3 SANDY 64.0 2.6 128 102 +1950 6 4 0 25 FLORENCE 21.6 46.2 163 330 +1977 3 28 0 22 MICHAEL 26.2 24.0 72 228 +1967 11 9 12 10 SANDY 58.6 333.0 32 232 +1990 11 16 18 22 ERNESTO 66.0 203.9 141 270 +1974 7 25 18 21 VALERIE 44.7 39.4 99 20 +1969 8 8 6 5 HELENE 69.7 43.0 159 515 +1985 12 21 0 12 PATTY 23.1 293.2 111 375 +2001 1 24 12 21 VALERIE 26.1 15.9 10 141 +1975 2 24 18 6 DEBBY 25.5 114.3 78 387 +1971 4 17 12 2 KIRK 44.3 122.8 92 320 +1992 9 7 12 27 GORDON 38.7 54.3 139 860 +1988 1 1 0 7 SANDY 38.6 88.4 46 149 +1973 1 3 18 25 OSCAR 34.0 27.2 114 715 +1981 12 27 6 3 ISAAC 34.0 290.9 163 122 +1967 3 24 18 2 DEBBY 47.8 104.6 21 566 +1955 9 4 0 2 OSCAR 29.2 157.0 132 777 +1994 8 17 6 2 SANDY 59.9 74.4 43 630 +1995 5 20 12 3 FLORENCE 19.2 269.2 42 757 +1956 9 6 12 22 GORDON 19.8 111.1 28 680 +1972 11 2 12 1 GORDON 9.4 300.4 87 47 +1992 11 25 12 11 WILLIAM 66.1 286.5 26 332 +1953 11 15 18 3 TONY 66.0 348.8 60 817 +1998 8 10 12 7 SANDY 59.1 274.7 120 560 +1970 4 2 12 1 NADINE 11.0 25.9 138 325 +1986 5 18 18 18 ISAAC 52.1 52.1 60 401 +1985 3 23 0 12 FLORENCE 39.9 114.2 110 634 +1985 4 8 6 20 NADINE 26.9 174.1 116 342 +1974 10 6 6 19 HELENE 60.6 64.7 66 503 +1971 1 23 6 11 JOYCE 63.1 270.9 98 830 +1979 6 1 0 25 MICHAEL 40.0 344.6 33 552 +1957 8 9 6 9 MICHAEL 27.5 327.3 12 867 +1952 2 5 6 6 MICHAEL 41.4 230.2 30 24 +1950 7 9 12 22 BERYL 49.2 222.3 162 589 +1973 1 10 0 8 KIRK 34.5 231.0 10 361 +1983 2 2 18 9 VALERIE 54.5 318.6 35 82 +1971 6 5 6 21 GORDON 31.1 2.1 86 471 +1989 9 9 12 17 RAFAEL 42.1 350.5 120 245 +1960 8 10 18 4 VALERIE 19.4 50.0 73 549 +1958 1 13 6 25 FLORENCE 11.7 230.6 27 161 +1959 12 22 0 12 WILLIAM 53.9 222.6 27 391 +1985 7 1 0 28 KIRK 64.1 160.9 144 470 +1954 8 17 12 13 OSCAR 13.0 65.9 132 371 +1988 3 14 6 18 ERNESTO 31.0 14.7 120 443 +1998 6 21 6 11 PATTY 48.0 268.1 28 350 +1954 11 27 0 20 VALERIE 26.4 74.6 163 709 +1958 2 14 12 19 PATTY 44.2 180.7 142 97 +1971 2 2 18 14 GORDON 46.2 293.3 95 110 +1987 9 27 12 21 LESLIE 33.4 240.3 14 362 +1979 7 4 6 17 CHRIS 28.1 291.2 130 822 +1974 6 9 18 21 ALBERTO 58.3 56.8 48 694 +1982 12 26 12 25 KIRK 13.6 89.6 87 47 +1995 6 9 12 2 KIRK 57.2 33.8 111 41 +1993 6 20 0 13 ISAAC 50.1 97.9 45 793 +2003 6 21 0 18 OSCAR 33.2 153.6 69 162 +1984 5 16 12 14 ERNESTO 15.5 110.2 119 116 +1991 10 27 18 22 OSCAR 35.5 332.5 141 809 +1986 3 8 6 20 LESLIE 67.8 280.6 140 825 +2004 7 13 6 10 RAFAEL 35.5 314.4 103 589 +1954 3 28 6 12 JOYCE 35.5 210.8 91 815 +1960 12 12 12 18 HELENE 30.6 26.2 116 66 +1950 1 18 12 24 JOYCE 23.8 115.6 125 512 +1950 10 20 12 4 ISAAC 10.3 56.0 51 191 +2001 11 18 18 26 RAFAEL 9.1 292.5 88 87 +1954 7 25 18 6 PATTY 15.2 227.2 37 370 +1988 11 25 6 4 CHRIS 45.5 248.2 119 251 +1972 8 8 18 15 GORDON 69.8 155.4 62 436 +1957 7 12 18 2 FLORENCE 32.8 325.9 108 62 +1999 6 2 18 28 OSCAR 45.8 10.1 134 796 +1961 12 25 12 14 LESLIE 30.7 26.6 11 105 +1986 12 22 6 14 LESLIE 26.5 300.7 36 177 +1966 2 24 12 8 NADINE 19.7 4.1 162 208 +1957 12 3 12 10 ERNESTO 10.3 323.2 122 664 +1963 6 28 0 23 SANDY 16.5 321.1 122 703 +1997 8 26 18 27 TONY 54.0 197.4 87 778 +1970 6 22 18 15 NADINE 14.6 135.1 16 129 +1975 3 20 6 4 HELENE 35.6 47.5 67 894 +1954 11 23 0 8 MICHAEL 47.3 41.4 83 271 +1957 4 8 12 15 JOYCE 57.6 216.0 56 778 +1987 6 11 12 27 RAFAEL 15.4 19.8 35 638 +1988 2 10 0 2 MICHAEL 50.7 27.8 98 742 +1976 6 19 6 25 OSCAR 62.6 118.2 79 810 +1996 11 13 6 21 GORDON 43.7 158.0 85 297 +1991 7 5 6 22 NADINE 59.9 245.5 148 115 +1966 6 3 0 20 GORDON 24.8 81.1 65 386 +1956 11 2 12 8 ERNESTO 23.0 22.1 97 220 +1999 2 25 0 11 KIRK 36.2 76.4 155 395 +1981 1 5 12 28 BERYL 21.4 96.9 140 425 +1971 11 19 0 11 ISAAC 46.4 29.6 43 315 +1998 8 2 18 10 TONY 54.2 0.9 151 467 +1967 10 18 0 11 TONY 10.8 303.5 133 701 +1978 9 21 12 9 ALBERTO 30.1 178.6 117 449 +1960 5 24 12 16 OSCAR 32.8 318.2 35 27 +1988 3 28 12 11 SANDY 17.1 269.7 107 275 +1989 7 20 0 26 HELENE 59.5 208.7 131 465 +1965 9 23 0 16 RAFAEL 19.7 297.2 153 884 +1992 2 20 0 2 JOYCE 37.7 188.8 46 240 +1962 12 17 12 25 ISAAC 16.3 105.6 81 550 +1954 9 26 12 11 WILLIAM 30.2 338.2 46 261 +1988 5 27 18 8 BERYL 58.5 308.4 127 516 +1987 3 25 6 4 OSCAR 16.8 2.6 48 651 +1972 9 4 0 26 BERYL 9.7 356.7 82 447 +1974 2 12 0 1 RAFAEL 16.0 102.1 60 291 +1975 12 4 6 25 RAFAEL 67.7 193.4 136 18 +1984 2 25 12 17 WILLIAM 14.8 314.0 46 879 +1988 1 15 18 1 LESLIE 19.6 214.4 61 884 +1963 3 9 6 18 SANDY 68.7 291.1 115 490 +1966 5 11 6 22 NADINE 47.3 227.4 72 456 +1992 12 10 6 19 MICHAEL 8.8 233.4 34 378 +1989 12 22 0 1 FLORENCE 16.2 89.3 27 233 +1985 6 3 18 17 LESLIE 46.2 112.8 161 632 +1999 4 7 0 14 WILLIAM 17.6 201.6 138 725 +1960 6 28 12 7 OSCAR 28.1 126.3 164 680 +1999 12 22 12 24 VALERIE 12.2 3.1 97 50 +1951 9 3 12 9 JOYCE 63.3 342.0 21 33 +1985 2 11 18 27 FLORENCE 47.3 350.6 140 674 +1967 11 5 0 7 ISAAC 54.0 285.8 147 511 +1977 3 27 6 26 KIRK 20.4 35.1 43 287 +1991 3 19 12 11 BERYL 56.8 99.4 154 655 +1996 10 12 18 11 DEBBY 49.7 324.1 152 125 +1993 5 17 12 6 JOYCE 13.8 321.9 80 583 +1962 1 6 18 26 OSCAR 8.8 180.8 121 530 +1971 9 15 0 18 VALERIE 46.9 273.6 61 602 +1953 8 13 12 12 LESLIE 25.6 262.4 39 834 +1992 5 20 6 20 ALBERTO 18.1 4.3 154 462 +1982 10 6 18 4 CHRIS 10.9 244.1 114 873 +2002 5 16 12 3 ERNESTO 29.6 191.6 117 404 +1952 10 5 6 12 OSCAR 43.2 279.5 23 677 +1957 12 14 0 26 RAFAEL 26.6 128.6 138 42 +2004 11 27 0 3 ERNESTO 50.2 207.6 15 536 +1978 3 6 12 27 OSCAR 56.6 162.0 159 546 +1991 12 18 0 18 CHRIS 53.0 213.0 139 471 +1991 5 10 12 1 FLORENCE 30.8 201.6 137 846 +1980 7 28 0 7 PATTY 41.8 166.0 96 157 +1982 11 13 0 25 ISAAC 46.3 304.6 145 260 +1953 3 18 6 3 VALERIE 8.9 18.2 24 293 +1993 12 17 12 4 ALBERTO 37.8 76.7 137 686 +1991 6 8 0 19 NADINE 44.3 56.2 32 880 +1964 4 2 6 14 TONY 27.4 24.0 102 593 +1968 3 5 18 11 ISAAC 8.0 282.3 30 846 +1958 3 6 12 21 LESLIE 46.2 251.5 137 515 +2003 7 20 6 5 WILLIAM 66.9 305.2 97 17 +1961 7 20 6 28 ALBERTO 44.8 208.1 45 56 +1989 2 20 0 7 GORDON 49.7 69.8 19 613 +1989 9 4 18 28 SANDY 64.6 312.4 65 602 +1967 1 15 6 1 VALERIE 26.7 8.3 23 816 +1964 11 18 12 25 FLORENCE 54.6 145.6 20 282 +1998 4 11 6 24 DEBBY 33.3 225.3 99 584 +1962 1 20 0 14 VALERIE 32.1 165.0 138 456 +1961 10 24 18 21 FLORENCE 9.6 64.0 24 176 +2000 9 1 18 10 ALBERTO 40.9 340.1 19 772 +1972 12 11 0 13 HELENE 18.0 204.8 87 476 +1986 7 20 18 19 CHRIS 42.2 132.3 122 169 +1951 10 22 0 21 KIRK 45.6 298.7 10 620 +2003 10 6 18 18 TONY 43.2 10.0 24 725 +1977 6 25 18 26 HELENE 36.1 337.9 133 827 +1988 5 1 12 16 SANDY 52.0 326.8 127 540 +1973 9 8 18 28 JOYCE 58.2 205.3 127 12 +1953 10 16 12 8 SANDY 54.8 15.9 39 722 +1962 10 8 6 22 OSCAR 66.3 326.8 103 707 +1998 7 22 12 28 WILLIAM 21.0 169.6 81 646 +1978 3 20 0 5 ERNESTO 22.7 346.6 79 553 +1995 11 7 12 12 CHRIS 28.6 241.4 149 732 +1987 5 19 18 27 GORDON 11.5 317.5 115 498 +2004 8 26 0 18 ALBERTO 32.3 191.6 56 148 +1980 7 20 0 9 BERYL 59.6 144.9 105 198 +1977 2 7 0 8 WILLIAM 62.4 156.1 66 735 +1993 9 3 18 8 VALERIE 36.8 120.0 78 505 +2001 1 2 12 20 DEBBY 24.4 79.0 118 657 +2003 5 21 0 8 KIRK 45.1 13.7 47 654 +1961 1 2 6 3 JOYCE 19.1 158.1 62 459 +1990 9 14 12 1 ISAAC 64.1 143.8 70 723 +1950 11 9 6 25 DEBBY 27.1 149.7 132 55 +1965 5 13 0 17 TONY 27.8 89.0 122 260 +1983 6 28 0 25 LESLIE 30.6 72.1 72 512 +2002 7 18 12 24 CHRIS 57.0 333.0 34 71 +1981 5 20 12 18 RAFAEL 16.2 206.3 110 562 +2004 7 9 0 15 MICHAEL 63.6 344.6 67 341 +1962 4 17 0 18 KIRK 68.4 2.0 72 878 +1957 1 17 18 7 MICHAEL 69.7 108.8 127 828 +1999 9 17 0 23 OSCAR 39.8 242.8 86 765 +2003 8 5 12 12 BERYL 27.0 175.0 65 25 +1976 10 12 12 9 RAFAEL 19.7 332.1 122 144 +1966 12 16 6 9 LESLIE 69.8 340.9 109 409 +1955 2 22 18 27 CHRIS 37.4 46.8 30 218 +1999 5 9 6 28 PATTY 40.6 215.8 121 506 +1981 12 13 12 19 WILLIAM 29.5 285.6 160 305 +1971 4 25 6 12 OSCAR 14.6 56.6 53 478 +1963 9 15 0 22 DEBBY 8.5 260.6 22 833 +1987 5 5 18 22 GORDON 68.3 87.7 63 854 +1994 1 21 6 5 BERYL 45.4 188.0 130 201 +2001 2 4 18 8 MICHAEL 26.8 303.8 101 508 +1982 12 5 18 17 WILLIAM 19.2 260.9 30 726 +1965 9 6 6 22 OSCAR 21.9 331.2 94 321 +1985 6 9 0 18 HELENE 12.9 36.9 17 486 +1960 11 14 0 25 KIRK 32.7 315.9 40 91 +1998 7 14 12 1 WILLIAM 69.9 135.7 80 392 +1974 10 3 6 7 VALERIE 49.8 56.3 149 332 +1998 9 27 18 6 GORDON 49.6 271.3 157 567 +1955 9 17 0 25 CHRIS 10.0 197.0 163 1 +1978 8 11 6 4 DEBBY 23.5 158.0 133 757 +1979 10 4 0 17 JOYCE 42.1 19.3 36 379 +1961 3 3 12 9 DEBBY 68.1 63.2 37 8 +1997 2 22 6 22 MICHAEL 29.3 168.4 15 790 +1983 2 9 0 9 OSCAR 27.7 165.3 115 712 +1987 11 14 12 28 PATTY 39.1 263.3 46 574 +1957 8 13 12 25 RAFAEL 12.0 269.8 51 715 +1956 1 16 6 19 DEBBY 13.5 240.9 76 367 +1988 12 9 6 8 DEBBY 48.9 333.4 116 361 +2000 10 27 12 23 ISAAC 52.0 130.2 131 126 +1974 8 6 18 7 VALERIE 63.8 186.4 101 765 +1999 7 25 6 23 BERYL 19.7 316.0 63 8 +1985 1 5 0 6 VALERIE 24.7 79.9 141 819 +1970 2 17 6 1 PATTY 10.5 127.1 139 519 +1954 8 8 6 25 BERYL 41.7 308.1 90 299 +1980 5 4 6 14 MICHAEL 46.4 97.3 107 799 +2001 12 12 6 26 CHRIS 38.8 176.9 163 888 +1959 12 6 18 23 OSCAR 46.7 61.9 160 856 +1982 1 13 18 6 RAFAEL 68.5 180.3 117 577 +2000 11 14 12 15 OSCAR 51.8 231.0 30 756 +1986 10 28 18 8 OSCAR 55.6 227.8 41 101 +1978 5 11 12 23 NADINE 24.5 282.0 18 181 +1993 7 6 12 7 JOYCE 32.6 99.7 96 364 +1951 5 20 0 25 ISAAC 61.3 100.4 15 94 +1998 12 16 0 13 ALBERTO 48.7 168.3 75 218 +1963 3 9 0 25 JOYCE 16.6 4.1 122 866 +1998 8 21 6 8 HELENE 18.4 132.7 101 692 +1958 11 2 0 26 ERNESTO 41.0 356.6 161 422 +1987 11 8 18 27 SANDY 62.8 21.7 82 34 +1953 8 11 12 6 CHRIS 40.4 161.0 75 891 +2002 6 28 12 10 TONY 34.1 148.4 120 804 +1951 11 16 18 17 VALERIE 52.9 27.7 61 415 +1962 5 14 0 25 ISAAC 30.6 279.7 118 390 +1963 7 5 12 2 MICHAEL 41.0 271.2 29 572 +1969 2 12 6 18 DEBBY 24.5 119.6 151 705 +1995 1 27 12 16 NADINE 20.8 307.8 142 468 +1982 12 2 0 22 DEBBY 31.6 259.5 62 348 +1989 4 22 6 5 ERNESTO 38.1 44.5 93 826 +2003 8 10 0 24 LESLIE 14.1 273.4 143 486 +1988 2 20 12 14 ERNESTO 26.8 145.3 143 593 +1999 1 20 0 14 OSCAR 46.2 330.3 49 401 +1958 3 19 18 1 PATTY 66.8 162.4 92 813 +2001 2 19 0 10 HELENE 55.2 9.3 85 494 +1956 3 17 6 3 CHRIS 66.5 244.1 53 229 +1951 1 2 0 26 RAFAEL 20.2 61.3 47 362 +1981 10 11 6 3 FLORENCE 69.5 8.4 10 450 +1996 9 23 12 26 BERYL 36.8 344.1 156 173 +1999 3 14 0 3 PATTY 49.5 25.9 78 405 +1956 12 19 18 24 WILLIAM 55.0 290.7 110 85 +1977 10 23 6 10 KIRK 45.0 348.9 137 738 +1999 9 2 0 14 NADINE 42.1 87.0 135 315 +1958 3 13 0 27 WILLIAM 41.5 352.8 34 509 +1978 11 27 12 23 GORDON 7.7 22.3 75 206 +1969 6 11 18 26 WILLIAM 26.5 305.0 93 718 +1982 3 22 6 18 DEBBY 12.3 162.5 89 540 +1966 8 1 12 14 ISAAC 36.7 129.2 153 26 +1959 3 28 6 10 CHRIS 41.2 85.6 138 227 +1965 8 27 0 6 DEBBY 21.2 31.6 87 836 +1969 5 21 12 28 DEBBY 58.7 168.6 29 416 +1997 6 4 0 27 GORDON 37.9 95.4 142 272 +1996 5 15 12 6 FLORENCE 18.1 177.5 38 798 +1951 9 19 6 8 OSCAR 35.3 169.9 47 100 +1961 3 1 18 13 TONY 69.8 284.1 97 857 +1985 12 8 0 15 ALBERTO 12.4 216.5 143 498 +1982 9 17 12 14 BERYL 29.6 184.2 101 350 +1971 8 6 18 9 PATTY 42.0 18.5 47 224 +1978 8 15 0 9 TONY 58.6 297.0 85 210 +1978 3 20 0 22 KIRK 24.2 226.9 76 707 +1997 8 21 6 27 WILLIAM 37.3 166.8 11 333 +1969 4 23 12 11 HELENE 65.0 221.5 57 578 +1985 1 22 12 6 FLORENCE 61.4 139.4 103 837 +1986 7 3 12 19 HELENE 34.7 350.0 50 105 +1971 6 11 6 6 MICHAEL 32.3 198.4 155 785 +1993 8 10 0 21 KIRK 39.9 336.0 110 678 +1985 9 2 6 3 TONY 44.9 82.3 33 543 +1999 5 13 18 14 LESLIE 11.3 340.8 127 162 +1965 12 6 0 8 RAFAEL 58.9 288.7 114 753 +1994 1 21 18 1 LESLIE 28.5 0.3 75 521 +1962 1 20 18 2 ISAAC 14.9 201.9 11 64 +1988 12 10 18 24 ALBERTO 28.8 156.8 34 61 +1971 3 18 6 10 CHRIS 10.3 144.5 93 814 +1974 1 28 6 24 JOYCE 18.4 3.6 24 258 +1997 5 7 18 22 ISAAC 47.4 180.9 51 778 +1963 7 10 12 6 BERYL 66.7 226.1 133 487 +1979 12 1 12 14 RAFAEL 57.1 220.5 58 569 +1964 8 12 12 21 OSCAR 55.2 317.4 95 530 +1971 8 20 0 27 PATTY 62.3 288.0 74 254 +1957 6 23 0 13 SANDY 13.5 210.2 155 552 +1998 9 18 12 14 NADINE 49.9 84.1 43 483 +2002 11 21 12 23 SANDY 58.5 357.1 119 62 +1951 5 13 18 15 GORDON 29.7 46.5 12 137 +1978 6 27 12 18 KIRK 12.9 114.2 144 116 +1951 9 7 18 15 BERYL 21.8 29.8 95 427 +1963 12 3 6 17 RAFAEL 54.7 235.4 155 312 +1978 5 12 0 23 GORDON 19.4 12.3 142 606 +1968 10 13 6 27 ISAAC 29.1 44.9 110 752 +1980 1 22 6 22 PATTY 47.9 227.7 124 663 +2003 12 28 0 19 KIRK 29.1 336.4 138 346 +1966 5 15 18 12 OSCAR 47.0 260.8 134 289 +2003 4 16 18 9 JOYCE 51.0 95.1 158 815 +1955 3 14 6 26 ISAAC 61.2 287.4 105 548 +1977 11 14 12 23 PATTY 40.2 123.9 137 11 +1997 6 24 6 28 ALBERTO 17.1 219.8 162 78 +1982 6 15 18 12 MICHAEL 33.8 33.4 131 762 +1953 11 15 18 25 JOYCE 17.9 176.3 85 234 +1998 8 19 12 13 BERYL 51.4 241.5 114 544 +1971 2 26 0 11 FLORENCE 23.3 78.8 124 410 +1964 1 12 18 7 GORDON 10.4 115.3 54 517 +1994 2 9 6 25 TONY 41.4 192.7 70 720 +1957 11 28 0 23 VALERIE 14.3 37.6 100 535 +2001 9 11 6 21 ERNESTO 23.7 127.0 83 655 +1987 3 9 12 17 FLORENCE 37.1 119.8 30 665 +1971 6 6 0 24 HELENE 40.6 318.5 54 737 +1982 7 14 0 18 ALBERTO 36.3 147.6 73 678 +1958 11 21 18 17 VALERIE 12.5 328.8 116 255 +1985 1 23 12 7 FLORENCE 59.6 246.9 91 773 +1957 11 15 6 2 JOYCE 56.9 118.3 137 121 +1996 6 25 12 15 VALERIE 31.9 18.6 28 238 +1975 10 18 12 14 TONY 33.3 247.9 139 851 +1958 2 1 0 5 KIRK 34.3 162.8 81 216 +2002 4 13 18 23 ISAAC 50.4 141.6 142 737 +1971 2 15 18 8 VALERIE 28.7 41.3 138 353 +1957 10 13 12 4 KIRK 56.7 269.9 68 695 +2003 7 16 6 2 LESLIE 39.6 99.3 64 682 +1987 6 15 6 5 VALERIE 62.3 49.5 119 339 +1970 5 6 12 16 HELENE 12.9 174.8 29 321 +1963 5 25 6 9 PATTY 34.4 288.8 122 192 +1982 8 1 18 27 LESLIE 37.8 6.4 68 706 +1982 8 28 12 25 BERYL 21.4 267.1 86 749 +1970 9 6 18 23 DEBBY 27.0 84.0 155 24 +1990 1 24 18 8 OSCAR 52.4 322.3 120 764 +1995 11 19 12 19 RAFAEL 40.8 104.4 97 888 +1994 4 7 0 23 PATTY 20.3 42.6 86 763 +1950 9 13 0 14 ALBERTO 10.2 16.6 156 572 +1984 1 19 0 2 TONY 53.2 78.7 11 648 +1992 12 1 18 16 TONY 40.6 195.6 147 28 +1975 5 8 0 24 SANDY 54.4 102.2 134 373 +1956 2 22 18 17 OSCAR 69.8 266.8 93 771 +2003 6 11 12 21 SANDY 38.2 133.4 83 362 +1968 1 24 12 24 SANDY 22.8 214.6 105 534 +1968 9 11 6 17 SANDY 37.7 267.9 37 613 +1963 9 17 0 7 NADINE 7.5 75.3 19 358 +2000 12 23 6 17 OSCAR 26.3 62.8 141 422 +1998 4 14 18 11 LESLIE 27.0 155.7 106 534 +1985 8 23 18 19 FLORENCE 13.9 286.1 154 260 +1961 10 23 0 20 VALERIE 15.2 353.0 12 407 +1993 10 4 18 23 NADINE 31.6 293.9 62 29 +1956 7 7 6 15 ERNESTO 65.1 259.2 156 108 +2003 8 10 6 5 ISAAC 53.9 301.2 75 202 +1956 8 17 12 28 MICHAEL 11.1 294.2 58 518 +1997 4 23 12 28 PATTY 19.3 292.8 28 866 +1956 11 7 12 11 WILLIAM 45.5 198.8 136 327 +1988 7 20 18 4 BERYL 54.8 216.2 162 115 +1980 10 13 6 19 VALERIE 66.2 168.1 44 74 +1998 3 8 12 28 SANDY 40.2 350.7 143 343 +1965 3 4 6 11 ERNESTO 7.8 355.2 30 781 +1970 7 23 18 17 HELENE 10.5 211.4 34 154 +1982 12 8 0 16 OSCAR 55.1 310.7 147 96 +1953 11 26 0 15 DEBBY 36.5 216.4 43 606 +1952 6 26 18 11 PATTY 55.1 320.9 37 829 +1976 10 15 18 17 DEBBY 22.0 149.4 102 292 +1974 1 26 6 9 CHRIS 68.3 6.5 92 669 +1955 6 20 12 11 OSCAR 65.8 63.0 111 411 +1995 6 1 18 22 RAFAEL 11.0 26.7 161 322 +1998 7 12 18 13 BERYL 28.4 260.9 62 887 +1994 8 15 18 14 BERYL 38.4 184.9 96 112 +1993 9 26 18 21 PATTY 10.3 168.9 54 206 +1988 10 7 0 18 PATTY 47.0 102.0 163 737 +1963 7 13 6 18 KIRK 45.5 316.5 100 670 +2002 12 17 0 21 PATTY 60.3 340.7 63 167 +1971 1 14 12 3 TONY 25.3 16.2 157 817 +2000 5 8 18 4 FLORENCE 23.2 34.8 123 700 +1996 12 18 6 16 MICHAEL 69.1 352.2 96 629 +1973 5 15 18 21 WILLIAM 41.3 58.1 114 281 +1998 8 7 0 14 NADINE 19.7 294.6 51 513 +1971 7 4 12 5 FLORENCE 43.9 51.4 91 179 +1967 5 9 6 24 HELENE 58.8 326.4 90 637 +1982 1 18 6 26 NADINE 16.0 227.8 152 414 +1990 11 23 18 20 ISAAC 62.7 357.9 151 569 +1952 10 13 6 10 KIRK 21.9 142.5 72 65 +1985 5 23 0 2 GORDON 46.6 119.1 19 799 +2003 5 10 18 4 CHRIS 30.7 264.1 48 588 +1979 12 17 6 20 FLORENCE 33.2 240.0 28 379 +1999 2 18 12 10 DEBBY 36.8 217.8 109 602 +1978 4 2 12 17 GORDON 65.4 23.4 149 468 +1984 10 19 12 11 FLORENCE 56.2 287.0 55 583 +1982 8 27 6 3 WILLIAM 57.3 217.8 23 741 +1956 10 28 0 5 VALERIE 23.1 20.7 63 660 +1950 10 2 0 21 ALBERTO 19.5 83.9 140 173 +1997 1 15 0 18 CHRIS 40.3 291.3 23 451 +1979 9 5 0 15 TONY 24.0 110.1 18 16 +1997 8 28 0 6 OSCAR 64.1 60.2 141 165 +1951 2 14 6 15 TONY 16.1 41.9 112 595 +1960 6 8 0 8 WILLIAM 18.0 349.7 77 756 +1989 8 1 0 8 WILLIAM 55.2 64.6 41 528 +1988 8 5 0 5 BERYL 21.7 122.8 80 757 +1985 2 3 12 6 WILLIAM 9.0 171.3 139 90 +1969 3 12 6 5 RAFAEL 22.0 49.7 132 261 +1969 11 27 0 1 MICHAEL 44.0 315.6 79 252 +2003 12 14 18 15 PATTY 41.6 32.7 93 356 +1960 2 12 12 3 TONY 15.4 158.0 75 757 +1986 11 9 0 27 HELENE 61.7 230.2 51 111 +1977 3 10 6 19 LESLIE 43.0 189.9 100 400 +1997 7 1 0 21 MICHAEL 65.8 281.2 157 625 +1981 6 16 12 12 SANDY 57.6 214.3 42 860 +1983 7 12 0 28 ALBERTO 44.0 69.9 138 843 +1967 12 21 6 1 BERYL 21.7 331.5 134 732 +2003 3 5 18 6 RAFAEL 21.1 64.1 75 589 +1977 2 1 18 19 JOYCE 20.2 190.4 57 554 +1986 12 6 6 21 ALBERTO 60.6 196.7 62 689 +1959 4 2 0 10 RAFAEL 41.5 11.8 110 533 +1992 9 6 12 20 VALERIE 12.5 273.1 43 541 +1960 2 11 0 3 VALERIE 37.5 291.0 14 362 +1976 8 17 0 2 MICHAEL 57.2 319.7 132 388 +1954 6 23 6 8 ALBERTO 33.6 311.3 72 869 +1977 2 7 18 6 WILLIAM 20.5 84.9 102 59 +1973 5 5 0 24 OSCAR 10.2 53.1 154 300 +1979 4 20 18 21 OSCAR 43.4 170.9 37 53 +1972 1 9 0 19 JOYCE 48.5 159.8 113 274 +2003 2 15 6 24 WILLIAM 67.0 36.5 59 706 +1978 5 10 6 4 WILLIAM 8.8 285.0 36 465 +1964 9 11 6 9 JOYCE 23.1 98.9 91 795 +1956 12 8 18 2 SANDY 28.0 203.1 86 495 +1951 6 9 0 16 ALBERTO 34.6 8.8 125 202 +1970 6 7 12 4 ALBERTO 35.5 345.6 36 452 +1964 1 23 0 3 ALBERTO 35.3 350.0 30 161 +1995 3 27 0 6 ALBERTO 60.1 243.9 24 236 +2000 1 21 0 27 ALBERTO 14.9 54.3 91 285 +1974 6 22 6 2 DEBBY 30.6 273.6 35 261 +1957 6 26 6 3 DEBBY 23.1 252.8 121 442 +1979 1 9 18 28 KIRK 38.2 20.5 35 625 +1999 3 5 12 11 NADINE 61.8 129.9 127 697 +1986 2 25 18 20 LESLIE 26.4 48.8 111 540 +1955 12 28 6 21 JOYCE 49.2 203.9 92 23 +1987 4 22 6 16 LESLIE 35.5 24.6 112 881 +1990 9 6 18 7 HELENE 15.6 125.4 19 487 +1952 12 7 12 27 JOYCE 46.7 142.9 85 133 +1979 4 21 6 7 CHRIS 63.1 121.1 108 609 +1981 5 1 0 4 BERYL 35.7 240.5 107 106 +1963 1 7 12 8 VALERIE 38.0 67.5 163 525 +1972 2 8 12 10 ISAAC 39.6 68.1 27 803 +1962 2 9 18 16 BERYL 64.6 183.1 80 486 +1969 9 9 18 1 NADINE 29.7 13.3 30 170 +1976 1 13 0 28 GORDON 8.2 250.0 65 535 +2001 5 23 12 6 RAFAEL 27.7 21.7 69 880 +1962 1 28 6 5 ALBERTO 19.9 295.4 151 561 +1994 12 25 18 11 PATTY 58.3 305.8 156 4 +1990 8 10 12 1 SANDY 68.7 93.9 125 705 +1982 7 22 0 16 ISAAC 61.6 37.4 68 530 +1980 4 24 18 16 GORDON 28.4 35.1 19 386 +1996 12 20 12 14 NADINE 63.5 342.9 122 547 +1987 7 18 6 28 ISAAC 22.1 211.5 47 384 +1979 6 19 6 18 BERYL 64.6 123.5 61 818 +1980 10 7 0 3 ISAAC 44.5 229.8 123 876 +1966 4 21 18 14 RAFAEL 40.4 38.9 12 833 +1986 3 25 6 22 MICHAEL 36.5 124.7 152 644 +1955 1 12 12 21 TONY 16.0 221.9 149 753 +1976 5 19 6 10 OSCAR 24.7 62.8 135 621 +1995 2 27 6 24 ERNESTO 61.4 203.1 91 155 +1954 5 18 0 28 HELENE 49.2 14.1 29 431 +2001 4 20 6 15 CHRIS 65.1 242.5 107 5 +1991 9 22 12 2 NADINE 48.0 109.5 91 626 +1978 9 7 12 21 ALBERTO 23.0 99.8 141 229 +1997 3 7 0 7 KIRK 68.8 276.5 35 747 +1952 7 23 0 5 ERNESTO 30.2 206.0 92 570 +1992 2 21 0 23 ERNESTO 63.1 231.6 124 700 +1963 2 11 18 4 ERNESTO 60.9 60.9 147 549 +2003 8 3 18 6 ISAAC 56.1 172.6 136 804 +1976 8 1 12 23 CHRIS 58.0 137.8 30 388 +1957 10 21 18 22 SANDY 42.4 262.4 18 221 +1989 12 8 12 9 RAFAEL 8.4 244.4 84 719 +2002 5 7 6 9 BERYL 29.9 318.7 52 243 +1999 3 15 18 21 NADINE 67.9 99.5 85 179 +1983 5 25 12 20 WILLIAM 43.3 349.5 123 887 +1998 6 7 18 12 MICHAEL 15.4 328.4 41 166 +1973 3 27 6 20 ISAAC 19.3 23.4 17 846 +1968 2 14 12 2 OSCAR 17.4 321.7 71 848 +1967 4 3 18 17 NADINE 42.0 234.4 13 581 +1986 4 27 12 21 LESLIE 9.2 89.0 120 224 +2003 7 19 0 23 DEBBY 57.2 268.7 108 351 +1959 8 10 6 12 MICHAEL 52.6 252.0 31 483 +1964 6 3 12 12 PATTY 17.7 283.0 121 860 +1954 7 20 12 2 OSCAR 38.2 247.5 146 228 +1979 2 11 6 11 NADINE 24.8 344.2 76 675 +1981 8 10 6 20 OSCAR 62.8 306.4 41 71 +2004 11 17 18 1 KIRK 49.2 25.6 161 885 +1985 9 28 0 1 FLORENCE 21.8 127.8 145 638 +1985 2 2 12 7 HELENE 57.2 204.1 152 588 +1984 1 7 18 26 OSCAR 61.2 80.0 149 586 +1972 10 10 18 27 ISAAC 35.8 225.7 84 13 +1979 4 11 12 14 BERYL 45.1 233.1 70 152 +1979 1 7 6 5 CHRIS 37.3 320.1 111 90 +1950 6 6 12 9 LESLIE 42.1 341.5 121 790 +1994 3 20 0 8 PATTY 7.6 51.6 90 524 +1952 4 21 12 14 HELENE 24.5 185.6 86 169 +1993 6 23 6 16 TONY 59.7 162.0 87 591 +1959 6 10 0 20 DEBBY 64.8 54.1 158 197 +1982 2 6 12 16 LESLIE 52.9 316.2 11 632 +1973 12 13 18 6 WILLIAM 38.3 270.3 159 145 +1954 4 8 0 1 NADINE 13.8 346.1 125 123 +2003 7 3 6 20 KIRK 48.1 269.7 43 878 +1969 10 9 6 13 CHRIS 48.7 50.0 34 717 +1987 10 15 0 28 HELENE 12.4 55.4 71 163 +1974 4 11 0 26 NADINE 34.6 53.9 122 278 +1956 9 11 12 26 CHRIS 54.0 334.3 150 252 +1992 3 1 18 16 OSCAR 17.0 252.3 84 271 +1978 3 1 12 1 OSCAR 45.4 227.6 116 307 +1975 5 10 12 7 ISAAC 19.9 119.8 22 709 +1960 9 13 18 22 OSCAR 14.5 301.4 91 678 +1951 6 8 12 25 OSCAR 40.2 123.5 89 442 +1960 4 13 18 27 WILLIAM 29.4 48.0 153 720 +1960 7 3 6 18 PATTY 27.6 285.9 147 679 +1979 9 18 6 19 ERNESTO 10.9 147.4 46 47 +1954 12 23 6 24 BERYL 50.9 237.2 87 788 +1956 11 15 6 10 WILLIAM 55.9 98.7 104 588 +1974 5 9 6 9 ALBERTO 41.3 74.3 88 813 +1959 10 25 0 22 KIRK 7.1 271.0 124 683 +1963 6 23 12 5 HELENE 20.4 308.6 120 30 +1982 7 14 6 6 SANDY 39.8 38.1 56 743 +1981 7 15 0 18 HELENE 50.1 10.6 153 108 +1990 10 6 12 5 DEBBY 28.6 325.8 35 159 +1987 3 2 6 2 MICHAEL 41.2 289.9 18 858 +2000 11 8 12 8 NADINE 44.1 64.8 15 56 +1989 10 12 0 23 OSCAR 17.3 136.4 114 419 +1969 3 11 6 6 ALBERTO 51.2 25.3 145 534 +2003 6 9 6 6 VALERIE 41.7 82.4 36 348 +1993 5 14 18 5 RAFAEL 15.0 122.8 107 107 +1967 1 4 0 12 ISAAC 52.3 134.3 13 795 +1974 9 28 6 7 ERNESTO 16.4 215.5 61 472 +1965 1 1 6 25 WILLIAM 30.1 141.9 33 645 +1991 8 23 12 6 JOYCE 53.0 185.9 108 75 +1996 1 23 18 9 FLORENCE 67.6 186.1 153 828 +1995 5 18 12 25 VALERIE 64.8 353.0 15 234 +1975 5 16 12 26 NADINE 26.1 326.9 149 614 +2001 1 22 18 8 TONY 28.2 206.3 136 42 +1951 2 27 18 23 VALERIE 15.2 176.4 20 147 +1972 4 5 12 16 ERNESTO 16.1 104.4 49 108 +1971 10 21 6 7 GORDON 9.3 143.9 114 201 +1975 11 13 6 28 SANDY 20.7 138.3 131 801 +1950 10 12 6 4 KIRK 52.6 215.8 33 1 +1995 9 18 12 23 ISAAC 34.2 245.8 108 731 +1990 4 15 0 1 OSCAR 14.6 22.3 107 544 +1970 9 28 6 18 VALERIE 28.2 213.3 15 413 +1954 12 16 6 28 OSCAR 42.5 276.0 54 869 +1952 4 15 6 21 HELENE 26.5 109.4 29 150 +1951 4 4 18 4 HELENE 9.7 200.6 139 89 +1976 2 11 18 12 NADINE 59.2 216.5 32 172 +1972 4 24 6 1 VALERIE 52.1 181.1 145 86 +1978 9 7 0 9 NADINE 66.3 143.3 150 565 +1970 12 2 0 3 FLORENCE 11.4 207.9 110 147 +2000 9 4 18 21 GORDON 43.1 119.1 118 351 +1950 9 3 6 5 JOYCE 30.8 71.6 58 573 +1978 3 1 12 8 ISAAC 36.2 227.6 69 101 +2001 5 9 12 1 WILLIAM 20.2 133.6 106 72 +1992 5 18 12 17 BERYL 12.6 149.1 53 576 +1958 9 8 18 5 ALBERTO 30.8 337.9 26 263 +1977 4 17 18 15 OSCAR 63.3 54.3 158 499 +1965 1 24 18 2 RAFAEL 63.8 309.8 160 390 +1987 11 14 0 11 PATTY 15.5 140.4 137 776 +1956 9 3 0 13 RAFAEL 31.8 7.8 64 412 +1956 2 20 6 9 JOYCE 64.4 211.0 18 25 +1985 11 28 12 19 KIRK 47.4 354.1 81 284 +1997 9 23 18 28 MICHAEL 19.9 192.2 108 210 +1984 9 5 12 18 CHRIS 31.9 149.2 35 192 +1969 10 21 12 11 FLORENCE 55.2 26.1 155 297 +1997 3 9 18 18 KIRK 38.4 344.0 105 569 +1969 2 19 12 12 KIRK 58.2 7.7 89 613 +1973 6 1 12 19 ERNESTO 21.2 273.0 14 873 +1956 12 10 0 26 TONY 19.3 153.2 114 625 +1972 4 15 6 27 OSCAR 68.9 33.1 53 541 +1969 10 21 0 21 ISAAC 12.9 150.1 66 431 +1967 4 3 0 8 VALERIE 16.9 180.4 117 705 +1960 6 1 6 8 WILLIAM 68.6 149.0 73 179 +1966 7 24 0 26 WILLIAM 26.4 69.5 151 255 +1964 7 17 18 27 WILLIAM 15.8 172.2 162 419 +1995 1 8 0 17 HELENE 68.6 54.3 159 463 +1953 6 4 12 28 GORDON 19.4 286.0 156 743 +1961 3 8 6 15 CHRIS 65.4 301.7 156 41 +1958 4 4 12 2 DEBBY 7.4 313.0 134 298 +1992 9 18 6 3 JOYCE 28.8 244.0 18 49 +2002 6 14 12 14 WILLIAM 68.9 108.4 108 257 +1952 9 7 0 5 ERNESTO 34.8 255.4 85 360 +1962 10 28 12 14 ERNESTO 50.0 341.5 15 166 +1975 5 12 6 9 CHRIS 32.5 280.2 109 646 +1990 8 10 18 3 RAFAEL 22.6 193.1 57 68 +1967 8 7 18 4 OSCAR 47.3 35.5 120 127 +1986 12 9 0 17 NADINE 45.5 44.8 109 566 +1965 8 21 6 27 HELENE 34.0 355.8 78 138 +2004 6 7 0 3 ERNESTO 8.6 123.2 144 15 +1952 12 25 0 12 JOYCE 27.5 120.9 23 626 +2004 4 4 18 23 NADINE 51.1 312.9 120 590 +1993 9 4 18 16 CHRIS 52.3 161.9 43 487 +1984 4 9 0 24 ALBERTO 57.3 273.0 71 121 +1971 1 18 6 18 MICHAEL 10.1 269.5 110 553 +1979 3 18 12 13 GORDON 25.3 73.0 57 200 +1995 11 8 18 5 PATTY 65.4 0.6 151 187 +1971 2 5 0 20 HELENE 43.1 244.3 136 762 +1966 10 27 0 11 VALERIE 60.8 305.8 103 501 +1962 3 6 18 28 FLORENCE 56.0 208.3 17 475 +1966 3 6 0 17 DEBBY 42.3 170.5 34 601 +1998 10 13 0 9 LESLIE 9.5 56.9 80 899 +1984 3 5 12 25 TONY 38.6 252.9 120 289 +1994 2 10 18 27 DEBBY 66.2 62.7 39 175 +1951 8 1 12 3 TONY 21.9 345.8 44 888 +1955 5 23 0 24 OSCAR 61.2 220.3 26 452 +1987 7 26 12 11 MICHAEL 52.0 271.3 145 821 +1967 12 3 12 18 FLORENCE 27.6 274.9 64 667 +1956 6 24 18 4 KIRK 50.0 340.9 73 786 +2002 11 24 18 20 LESLIE 33.9 263.1 61 354 +1974 3 7 0 11 RAFAEL 35.3 8.8 18 780 +1955 12 8 0 25 DEBBY 26.5 286.5 27 793 +1999 6 4 0 17 OSCAR 54.4 313.1 149 324 +1969 4 5 0 14 PATTY 21.7 84.4 95 410 +1984 5 24 6 2 ISAAC 44.2 94.1 17 460 +1957 11 20 18 24 TONY 54.4 350.6 137 663 +1958 11 10 6 22 NADINE 10.6 24.6 41 240 +1960 5 21 6 23 SANDY 19.8 1.1 154 338 +1951 6 6 12 17 FLORENCE 12.5 92.8 22 831 +1995 4 5 18 27 MICHAEL 65.2 297.6 119 443 +1952 7 4 0 28 CHRIS 46.1 253.4 159 163 +1952 4 15 6 6 ALBERTO 47.6 186.2 89 380 +1976 10 24 0 26 ISAAC 10.9 37.7 91 174 +1967 3 15 18 19 PATTY 26.1 150.1 85 856 +1969 9 7 6 10 BERYL 29.3 153.0 106 451 +1969 4 27 0 2 ALBERTO 11.9 341.4 93 649 +2002 8 3 18 1 PATTY 15.3 283.5 65 598 +1969 7 3 0 8 ERNESTO 66.7 263.0 74 130 +2001 9 24 6 18 JOYCE 19.4 25.1 72 391 +1991 1 3 0 26 WILLIAM 14.0 244.2 89 425 +2000 12 15 12 1 DEBBY 45.4 53.0 40 10 +1976 8 17 18 1 MICHAEL 65.8 127.7 125 578 +1955 6 15 12 14 LESLIE 64.2 40.1 58 593 +2002 7 1 12 11 TONY 54.5 105.2 43 503 +1968 12 19 12 1 LESLIE 41.0 191.7 103 875 +1957 2 11 6 24 BERYL 49.5 22.0 87 433 +1968 5 13 12 22 RAFAEL 66.0 171.4 93 361 +1995 7 18 6 2 LESLIE 9.4 294.2 81 292 +1956 9 2 12 11 NADINE 21.1 194.8 38 635 +2003 1 22 12 9 FLORENCE 13.8 224.8 161 713 +1984 7 12 0 10 CHRIS 14.2 222.2 105 580 +1961 12 14 6 4 OSCAR 9.5 239.6 143 137 +1955 3 26 0 4 LESLIE 22.2 210.5 158 17 +1998 3 11 0 13 ISAAC 59.7 266.8 39 415 +1994 5 12 0 22 MICHAEL 15.1 129.7 134 164 +1988 1 27 6 14 ERNESTO 29.8 287.9 42 567 +1957 10 15 6 28 DEBBY 26.2 150.3 79 696 +1968 12 26 18 10 NADINE 59.5 151.4 127 596 +1997 2 17 12 7 FLORENCE 68.9 71.1 75 56 +1992 10 24 6 6 FLORENCE 32.5 123.9 107 198 +1973 12 9 12 6 KIRK 50.4 163.9 95 783 +1984 5 7 18 18 MICHAEL 15.4 281.7 36 54 +1956 8 15 6 11 ALBERTO 31.0 91.2 106 154 +1964 2 7 6 8 HELENE 45.1 85.3 140 142 +1971 2 15 18 21 VALERIE 60.8 248.3 135 688 +1974 3 22 18 8 LESLIE 29.7 80.4 138 224 +1992 1 15 0 3 ERNESTO 14.8 351.4 43 689 +1987 10 23 12 10 FLORENCE 36.7 167.4 66 854 +1984 8 14 0 19 OSCAR 26.7 121.5 98 552 +1953 9 5 12 26 TONY 65.7 131.7 108 522 +1967 3 26 18 27 TONY 12.5 338.1 143 292 +1964 3 6 12 1 MICHAEL 35.6 120.9 155 441 +1951 9 23 18 19 PATTY 48.9 312.0 46 298 +1985 3 21 18 14 ALBERTO 43.8 130.2 110 368 +1965 7 23 0 13 LESLIE 35.9 356.1 14 212 +1954 5 7 6 15 RAFAEL 36.6 148.1 110 859 +1959 8 10 18 25 SANDY 32.3 303.1 157 644 +1978 11 16 6 7 ALBERTO 33.2 209.9 15 400 +1987 12 5 12 8 CHRIS 45.7 56.9 164 154 +2001 9 28 0 7 FLORENCE 59.8 42.7 153 884 +1962 10 12 12 22 LESLIE 12.9 45.5 46 330 +1967 2 13 0 21 DEBBY 49.1 352.4 59 640 +1954 5 10 0 8 OSCAR 55.2 299.6 69 251 +2004 5 13 12 3 ERNESTO 39.4 35.1 75 69 +1969 3 26 6 16 RAFAEL 20.6 98.0 135 70 +1960 6 3 0 18 PATTY 64.5 279.0 126 178 +1961 5 22 6 19 CHRIS 18.6 79.4 111 262 +1988 4 20 0 26 FLORENCE 31.5 192.1 46 99 +1984 5 5 0 9 RAFAEL 12.1 114.7 131 366 +1953 4 16 18 24 FLORENCE 56.2 142.4 71 486 +1965 11 7 0 15 BERYL 29.2 208.8 15 588 +1969 1 14 0 5 NADINE 13.8 282.9 38 201 +1960 3 18 0 24 MICHAEL 63.1 106.3 86 699 +1972 6 2 0 2 TONY 35.0 74.9 43 680 +1962 1 22 12 28 BERYL 47.9 9.9 79 706 +1953 3 25 18 4 SANDY 53.4 310.3 48 71 +1960 10 5 0 24 PATTY 24.8 144.1 118 513 +1953 10 9 12 27 RAFAEL 54.8 212.0 50 297 +1989 12 21 0 4 ERNESTO 64.2 3.1 95 96 +1991 2 9 6 8 PATTY 50.1 215.7 50 826 +1966 1 12 6 22 ERNESTO 52.8 104.4 147 127 +1962 8 16 0 1 CHRIS 27.0 154.3 71 495 +1982 11 2 12 10 SANDY 24.1 297.1 86 398 +1979 8 10 0 6 FLORENCE 26.0 50.3 148 108 +1975 7 24 12 16 DEBBY 10.0 52.2 86 517 +1968 2 10 0 26 JOYCE 68.3 91.3 85 299 +1996 7 8 12 22 ERNESTO 35.0 178.8 29 845 +1996 3 28 0 9 BERYL 32.4 223.6 160 458 +1992 11 28 18 16 ERNESTO 49.5 111.3 102 880 +2004 2 12 6 3 TONY 48.4 266.5 119 30 +1977 6 14 18 25 LESLIE 69.7 233.9 107 602 +1993 1 16 6 7 CHRIS 44.7 62.0 93 105 +1996 1 8 0 23 OSCAR 36.9 61.9 50 692 +1965 5 15 6 6 HELENE 28.8 27.5 44 783 +1965 11 21 12 13 ERNESTO 32.4 45.3 136 413 +1955 6 7 6 15 GORDON 31.3 196.7 18 291 +1997 5 23 6 3 NADINE 22.5 133.8 40 93 +1950 1 28 12 20 WILLIAM 26.3 57.3 64 453 +1960 8 25 6 23 WILLIAM 16.1 219.3 144 67 +1980 1 11 12 18 KIRK 28.4 133.1 33 607 +1990 8 17 12 14 WILLIAM 45.5 39.2 101 507 +1976 3 3 12 14 BERYL 44.4 283.7 44 590 +1975 12 28 12 26 VALERIE 26.7 159.9 138 70 +1962 7 3 0 19 TONY 62.6 271.1 46 596 +1969 4 19 0 15 WILLIAM 64.0 117.8 84 778 +1958 9 7 6 26 RAFAEL 31.9 258.7 131 842 +1963 4 3 6 2 BERYL 60.2 148.8 27 257 +1986 8 3 12 18 KIRK 31.8 3.9 57 742 +1994 2 23 0 4 ISAAC 19.4 233.5 24 334 +1988 4 11 12 11 DEBBY 30.1 12.9 133 660 +1963 6 10 18 12 TONY 68.3 257.1 157 204 +1957 11 14 18 27 GORDON 21.7 320.8 12 300 +1986 1 16 6 3 JOYCE 43.9 319.2 125 885 +2001 6 13 0 22 FLORENCE 52.4 348.5 150 776 +1970 12 24 0 12 GORDON 25.9 90.9 160 758 +2000 6 12 12 25 NADINE 29.9 30.4 140 457 +2002 9 13 12 12 TONY 19.1 56.2 107 843 +1994 11 2 12 12 BERYL 37.7 156.2 136 362 +1988 11 6 18 3 SANDY 40.6 195.8 67 624 +1972 3 14 12 5 ERNESTO 52.1 337.2 48 876 +1950 5 9 12 16 FLORENCE 62.3 34.9 110 246 +1978 6 25 18 3 BERYL 62.4 245.1 43 867 +2001 5 5 18 9 ISAAC 43.5 324.7 136 267 +1998 12 22 12 18 CHRIS 35.7 36.8 17 710 +1956 6 19 6 14 GORDON 70.0 215.3 31 309 +1952 7 2 0 7 JOYCE 52.2 98.1 74 5 +1996 4 5 0 22 PATTY 41.9 209.5 126 504 +1969 1 16 6 1 FLORENCE 21.5 215.2 55 643 +1974 10 24 0 12 JOYCE 7.8 315.9 143 366 +1972 2 6 12 10 DEBBY 68.0 321.5 101 169 +2004 2 23 6 26 SANDY 10.7 347.2 21 724 +1977 5 16 12 26 SANDY 8.4 217.8 78 668 +1990 11 11 18 9 DEBBY 21.7 43.0 153 612 +1950 7 7 0 23 OSCAR 42.5 256.5 62 74 +1984 6 28 12 15 VALERIE 8.8 140.7 33 844 +1955 8 2 0 27 OSCAR 61.5 357.8 38 415 +1983 8 27 18 16 MICHAEL 31.3 184.5 28 194 +1957 9 19 18 6 RAFAEL 51.1 187.1 15 375 +1961 9 10 6 23 NADINE 40.3 324.1 100 529 +1991 11 25 18 8 RAFAEL 46.3 245.4 33 350 +1963 10 14 18 3 TONY 30.0 194.4 140 227 +1993 2 1 0 17 PATTY 49.3 214.7 50 43 +1989 2 14 0 18 ALBERTO 55.8 250.9 95 42 +1951 10 26 0 9 HELENE 19.8 222.7 36 522 +1966 2 7 6 20 NADINE 48.2 180.5 152 631 +2000 9 28 18 20 NADINE 11.3 216.9 29 439 +1974 11 19 12 6 WILLIAM 43.4 161.1 24 250 +1985 12 6 6 1 MICHAEL 38.5 170.8 89 71 +1962 2 11 0 9 HELENE 64.5 137.6 64 713 +1986 8 24 6 6 ISAAC 40.1 160.2 109 107 +1967 8 16 0 24 WILLIAM 63.4 126.5 121 680 +1995 5 10 18 2 VALERIE 52.3 82.3 62 264 +2000 6 18 6 27 CHRIS 38.1 173.2 23 734 +1956 8 16 12 26 VALERIE 23.0 316.2 19 565 +1992 10 26 6 10 SANDY 21.6 159.3 134 813 +1973 3 8 6 3 PATTY 48.5 33.5 84 127 +1953 5 21 0 25 DEBBY 39.4 101.6 54 848 +1959 3 14 18 21 CHRIS 68.4 79.7 136 303 +1985 4 4 0 11 SANDY 69.7 308.4 78 810 +1993 12 26 0 26 SANDY 54.0 39.8 78 452 +1958 11 15 12 7 MICHAEL 42.7 345.4 113 95 +1967 12 9 0 8 TONY 18.7 55.3 132 30 +2000 1 5 0 3 KIRK 34.7 96.8 128 534 +1950 7 19 12 12 RAFAEL 37.0 308.7 135 181 +1989 9 2 0 21 RAFAEL 40.7 182.7 90 656 +2003 3 7 6 6 SANDY 29.2 199.1 65 652 +2004 6 22 18 11 JOYCE 31.6 40.9 18 824 +1982 2 14 12 2 ERNESTO 40.1 304.1 76 709 +1952 8 28 0 22 TONY 41.7 318.5 91 199 +1981 12 18 6 22 KIRK 55.1 215.6 78 586 +1995 6 25 6 15 DEBBY 37.5 270.8 149 309 +1976 7 13 12 13 ALBERTO 56.7 187.2 34 654 +2002 6 1 18 4 NADINE 53.5 337.8 117 119 +1976 10 25 12 16 NADINE 40.6 261.5 47 205 +1962 2 20 12 25 ISAAC 22.1 242.7 15 255 +1982 7 13 6 24 HELENE 28.7 266.0 160 766 +1983 8 13 0 3 ISAAC 13.5 259.2 12 549 +1990 4 12 0 5 WILLIAM 47.4 234.5 160 374 +1982 8 12 6 1 MICHAEL 39.5 180.8 104 516 +1984 7 9 6 20 BERYL 35.2 154.4 37 39 +1996 1 1 6 17 ERNESTO 39.3 232.0 95 541 +1973 8 6 18 15 HELENE 18.2 261.9 155 822 +1979 10 3 12 4 ISAAC 17.8 53.0 77 308 +1970 3 7 6 1 OSCAR 66.0 79.2 30 871 +1994 10 18 18 11 MICHAEL 11.3 156.4 15 377 +1987 1 12 18 18 PATTY 55.6 162.4 36 553 +1964 9 12 0 25 WILLIAM 61.9 158.7 124 548 +1988 11 22 0 3 FLORENCE 39.6 333.9 41 167 +2003 1 1 0 10 JOYCE 8.9 206.9 13 722 +1972 10 8 12 16 GORDON 46.1 53.1 61 547 +1994 7 2 12 8 BERYL 18.5 120.0 64 160 +2002 9 22 12 5 DEBBY 28.2 342.1 76 323 +1963 2 13 18 10 GORDON 52.1 297.7 57 51 +1984 11 11 6 21 DEBBY 26.1 117.4 128 701 +1957 7 2 6 22 DEBBY 23.4 260.0 52 255 +1982 7 15 0 8 NADINE 41.2 61.2 163 169 +1983 2 2 18 12 CHRIS 44.5 302.1 15 26 +1983 2 7 0 6 JOYCE 40.1 30.2 139 883 +1986 7 10 12 1 NADINE 54.1 75.9 139 641 +1966 7 18 0 1 OSCAR 33.4 142.5 16 790 +1983 8 17 6 14 ERNESTO 11.6 356.9 154 358 +1990 10 13 18 15 BERYL 29.6 305.2 58 469 +1956 12 21 6 12 FLORENCE 38.2 311.8 108 177 +1966 8 4 6 5 ISAAC 42.3 171.3 99 635 +1997 7 10 18 17 PATTY 48.5 114.8 116 457 +1954 7 23 6 27 TONY 33.7 278.9 81 524 +1974 4 28 18 16 LESLIE 10.2 303.9 55 532 +1998 7 26 0 16 RAFAEL 61.0 339.0 146 693 +1979 9 20 6 22 RAFAEL 10.3 338.1 76 225 +1955 7 15 6 19 PATTY 64.4 237.0 105 153 +1961 12 15 12 20 FLORENCE 14.2 106.3 29 869 +1972 1 14 0 26 ERNESTO 15.0 330.2 36 708 +1996 7 21 6 6 CHRIS 8.1 178.1 61 64 +1994 12 18 0 16 ERNESTO 8.9 76.1 42 565 +1994 4 10 0 16 CHRIS 59.2 28.9 79 338 +1984 3 4 18 27 MICHAEL 10.2 36.9 155 5 +1952 4 11 18 7 MICHAEL 39.6 280.1 25 767 +1966 2 27 0 27 MICHAEL 49.6 84.2 112 606 +1990 8 1 12 20 GORDON 59.8 334.3 109 40 +1979 12 21 12 6 RAFAEL 20.0 141.2 76 29 +1982 9 11 18 26 ISAAC 8.4 83.3 83 280 +1978 3 20 12 17 CHRIS 18.7 92.8 56 741 +1965 2 23 18 2 KIRK 25.1 311.9 137 337 +1965 9 3 18 3 LESLIE 8.7 80.7 47 860 +1958 1 3 0 12 DEBBY 25.5 120.5 141 581 +1962 1 22 12 8 ERNESTO 16.3 283.0 126 699 +1954 2 15 0 5 DEBBY 21.9 186.4 158 327 +1998 2 19 6 17 RAFAEL 64.6 177.1 49 697 +1965 4 27 12 26 LESLIE 57.0 56.9 24 320 +2001 10 1 0 5 ERNESTO 24.3 93.1 113 301 +2004 3 25 0 3 CHRIS 64.2 64.3 37 837 +1977 12 22 0 12 BERYL 20.1 231.8 25 887 +1989 11 25 18 20 KIRK 14.3 13.9 21 748 +1994 1 24 6 1 RAFAEL 53.0 130.7 51 683 +1952 9 23 0 6 VALERIE 23.9 305.3 57 774 +1987 7 26 6 20 VALERIE 10.7 304.5 83 133 +2003 8 22 6 7 GORDON 19.7 201.7 98 647 +1959 5 19 12 25 ALBERTO 52.2 296.8 123 297 +1968 2 2 12 7 VALERIE 68.9 243.2 141 652 +1997 10 25 18 17 NADINE 61.7 332.7 149 716 +1958 12 9 12 10 MICHAEL 28.0 256.9 42 380 +1956 2 8 6 26 GORDON 29.5 324.5 132 346 +1989 5 14 12 25 MICHAEL 61.5 10.4 96 319 +1969 7 27 6 21 PATTY 18.4 177.3 10 470 +1991 12 14 18 5 LESLIE 39.9 307.8 142 559 +1973 5 20 6 4 RAFAEL 50.1 64.1 15 792 +1981 6 13 0 11 PATTY 50.0 137.5 91 745 +1978 10 1 18 1 BERYL 7.8 75.1 73 708 +1979 5 7 0 24 CHRIS 38.8 278.3 14 466 +1964 1 19 0 25 ALBERTO 46.9 47.6 19 3 +1974 10 2 0 12 LESLIE 58.9 13.2 103 140 +1977 2 15 6 15 HELENE 24.3 156.0 102 385 +2002 5 14 18 19 TONY 65.2 329.6 22 585 +1980 6 9 6 9 PATTY 63.9 103.1 21 200 +1951 10 15 0 8 OSCAR 13.3 53.6 149 359 +2002 9 26 18 1 DEBBY 56.1 80.0 25 220 +1998 12 18 18 24 BERYL 30.0 82.3 73 896 +1966 4 24 12 26 LESLIE 13.3 54.9 77 350 +1977 4 28 6 13 ERNESTO 9.6 244.5 46 395 +1976 5 7 12 6 WILLIAM 22.2 32.8 72 173 +1967 4 2 12 7 NADINE 27.2 67.8 89 116 +1980 7 3 6 14 HELENE 60.6 333.3 132 596 +1988 3 15 18 13 NADINE 38.4 280.7 70 484 +1979 11 9 6 2 SANDY 55.0 64.0 61 248 +1951 8 24 6 11 WILLIAM 24.1 232.9 105 58 +2000 1 22 6 19 WILLIAM 45.8 21.6 132 850 +2000 6 25 12 21 OSCAR 42.2 90.0 43 869 +1979 9 27 18 17 OSCAR 8.6 146.8 118 696 +1959 7 1 18 17 BERYL 53.7 288.6 89 490 +1984 6 2 0 8 VALERIE 16.3 319.2 156 269 +1969 2 17 0 21 WILLIAM 29.9 207.1 31 75 +1995 8 28 18 14 WILLIAM 17.7 214.8 78 857 +1975 9 14 0 1 ERNESTO 34.6 251.9 142 699 +1997 11 11 0 15 ALBERTO 23.6 152.4 77 75 +1964 1 23 12 3 HELENE 53.1 273.1 85 477 +1966 3 4 6 16 RAFAEL 68.4 268.1 141 577 +1952 6 5 0 17 DEBBY 26.9 215.7 107 421 +1970 2 8 0 19 DEBBY 17.0 267.1 33 882 +1988 6 28 0 25 NADINE 48.8 255.0 92 379 +1955 7 28 18 21 HELENE 49.2 99.8 108 449 +1950 3 6 18 4 VALERIE 61.2 346.7 83 852 +1953 2 7 6 20 FLORENCE 50.7 123.1 73 87 +1950 5 24 6 17 VALERIE 36.7 47.3 42 672 +1979 3 1 12 4 MICHAEL 50.8 348.7 152 469 +2000 4 18 0 3 VALERIE 59.6 98.3 120 320 +1979 12 21 12 12 RAFAEL 38.8 120.7 119 578 +1954 4 21 12 8 JOYCE 19.4 152.1 150 532 +2001 5 13 6 11 WILLIAM 63.4 129.9 106 352 +1960 10 27 0 25 BERYL 7.3 172.8 157 301 +1982 7 7 18 20 CHRIS 68.1 140.6 40 389 +1989 7 22 18 1 LESLIE 14.8 26.8 107 216 +1995 10 13 18 8 ALBERTO 32.7 349.2 125 141 +2003 5 18 18 2 TONY 36.7 101.0 104 189 +1998 10 20 6 16 ISAAC 63.7 15.6 155 6 +1955 5 20 18 15 JOYCE 32.1 80.3 86 25 +1995 4 1 12 2 GORDON 23.5 22.9 19 47 +1953 10 9 0 5 TONY 21.2 197.5 22 550 +1998 9 10 12 15 CHRIS 50.0 198.4 106 665 +1986 9 16 18 8 NADINE 55.8 144.7 32 8 +1953 11 6 6 5 DEBBY 30.7 66.6 103 552 +1987 2 4 6 10 KIRK 28.7 187.1 113 230 +1953 7 15 0 13 VALERIE 30.4 193.3 149 29 +1975 12 9 12 1 DEBBY 28.0 322.9 57 331 +1989 7 5 0 28 RAFAEL 26.8 311.8 118 758 +1961 8 25 6 14 KIRK 50.4 248.1 32 752 +1983 6 15 6 15 OSCAR 59.9 58.9 115 687 +2001 12 4 12 9 ISAAC 38.7 258.5 35 551 +1969 5 24 6 15 VALERIE 13.5 135.2 136 577 +2004 5 2 12 2 NADINE 58.9 150.1 53 12 +1977 1 22 6 5 VALERIE 58.8 210.6 151 509 +1993 1 12 0 9 RAFAEL 21.2 289.2 145 876 +1981 6 27 0 7 LESLIE 26.1 86.3 125 231 +1979 11 1 12 26 LESLIE 19.2 123.2 68 815 +1959 2 2 0 25 PATTY 68.3 196.2 99 580 +1997 6 10 0 23 OSCAR 66.4 291.4 70 767 +1973 5 7 6 24 VALERIE 66.9 341.9 76 107 +1990 9 21 6 20 HELENE 19.5 153.1 20 592 +1989 1 7 0 16 RAFAEL 24.9 158.2 37 43 +1986 9 8 6 18 KIRK 25.3 183.8 135 523 +1954 7 25 18 6 ALBERTO 68.8 41.5 70 216 +1978 8 19 6 5 ALBERTO 27.6 352.8 81 151 +1964 10 20 6 11 NADINE 63.1 147.2 25 684 +1981 2 13 12 4 ISAAC 23.0 115.8 24 367 +1957 6 7 6 21 TONY 20.6 31.5 164 801 +1989 1 1 0 25 PATTY 13.6 124.1 41 447 +1983 4 4 6 6 WILLIAM 59.7 305.9 81 865 +1965 12 24 18 12 TONY 53.8 163.5 68 779 +2004 10 6 0 7 PATTY 18.3 187.3 62 170 +1971 2 8 6 16 SANDY 39.1 127.0 144 511 +1957 5 25 0 10 ERNESTO 41.3 347.9 26 583 +1960 6 12 6 14 PATTY 15.5 262.3 126 184 +1987 2 21 18 5 CHRIS 22.0 281.7 30 336 +1993 7 6 6 4 CHRIS 52.6 66.1 85 45 +1999 12 23 18 3 TONY 16.8 254.4 114 174 +1951 9 17 12 4 ERNESTO 57.5 172.8 129 187 +1955 5 19 0 16 KIRK 41.5 130.6 126 296 +1992 2 2 18 10 PATTY 11.0 278.4 114 245 +1968 10 1 0 11 ISAAC 12.1 25.6 130 83 +1958 4 6 12 12 MICHAEL 36.6 241.6 68 694 +1998 10 23 6 28 ALBERTO 49.4 138.2 111 748 +1966 4 6 6 2 CHRIS 60.1 151.0 127 741 +1997 11 22 12 23 RAFAEL 41.9 142.4 69 597 +1952 9 18 6 8 NADINE 52.2 19.1 144 16 +1950 4 15 18 26 WILLIAM 55.8 312.2 142 735 +1955 6 9 0 1 CHRIS 64.2 222.1 103 737 +1956 2 23 12 12 ALBERTO 42.8 325.0 161 217 +1953 6 28 18 3 NADINE 68.7 266.9 134 742 +1986 3 6 18 1 HELENE 69.1 284.7 85 657 +1978 10 7 0 27 KIRK 10.2 2.8 110 22 +1997 4 24 18 26 VALERIE 33.9 353.4 152 46 +1994 10 10 6 13 RAFAEL 43.2 94.8 147 522 +1987 6 4 0 19 SANDY 66.9 197.8 14 700 +1960 8 27 12 26 FLORENCE 28.7 85.3 74 693 +1983 12 3 12 21 JOYCE 26.3 148.3 73 226 +1973 4 6 18 13 SANDY 65.9 264.7 138 743 +1981 1 28 12 11 DEBBY 38.5 115.1 140 644 +1982 7 13 0 15 LESLIE 64.1 154.2 85 744 +1985 2 7 0 12 ISAAC 59.5 114.7 41 489 +1958 4 2 12 10 BERYL 27.2 281.7 44 308 +1969 5 23 18 1 JOYCE 21.6 317.6 148 340 +2001 7 5 12 22 OSCAR 9.9 22.5 28 347 +1974 4 22 6 27 TONY 12.5 145.8 100 751 +1975 10 11 0 12 GORDON 35.5 93.8 146 776 +1958 2 1 18 2 KIRK 30.5 245.0 142 51 +1961 8 1 12 3 CHRIS 11.6 80.8 141 553 +1959 8 5 0 5 ALBERTO 49.9 291.9 33 668 +1955 3 18 18 26 FLORENCE 63.7 180.9 47 433 +1986 12 28 12 16 ERNESTO 20.0 306.1 93 264 +1963 9 26 6 5 MICHAEL 41.4 320.7 161 616 +1958 8 13 6 27 HELENE 52.4 13.4 24 872 +1981 1 13 18 26 KIRK 42.5 133.1 111 792 +1999 12 15 0 19 HELENE 13.3 14.0 61 541 +1994 2 12 18 16 PATTY 48.7 198.7 64 765 +1984 2 26 18 27 CHRIS 44.1 1.8 81 795 +1976 9 6 6 5 LESLIE 18.0 153.8 90 76 +1960 10 3 12 10 NADINE 9.2 353.7 41 264 +1961 8 25 0 13 PATTY 37.7 338.5 143 580 +2001 6 3 12 12 BERYL 22.9 35.3 95 410 +1998 9 28 12 6 RAFAEL 14.1 80.5 26 43 +1988 8 18 12 17 DEBBY 34.5 239.6 93 805 +1993 6 7 6 15 KIRK 29.9 354.7 107 7 +1999 1 24 6 19 MICHAEL 20.9 253.3 84 95 +1984 7 28 12 15 SANDY 41.9 1.0 50 829 +1989 12 13 18 11 VALERIE 15.1 143.1 123 280 +1953 6 10 0 15 ISAAC 46.1 314.4 122 133 +1982 2 12 0 12 ALBERTO 38.1 102.2 50 216 +1955 10 17 0 24 RAFAEL 20.8 135.7 59 38 +1998 6 22 0 21 ISAAC 62.6 65.5 76 52 +1977 7 13 6 12 RAFAEL 69.7 27.2 47 412 +1981 2 10 18 11 CHRIS 7.7 232.5 163 852 +1971 2 18 18 18 OSCAR 15.4 272.2 51 331 +1976 1 9 6 3 DEBBY 51.8 247.5 10 622 +1990 8 3 12 27 JOYCE 50.5 3.0 136 36 +1995 1 2 6 1 ERNESTO 61.1 62.6 104 626 +1994 4 21 12 11 LESLIE 47.0 198.4 149 762 +1977 5 20 18 8 HELENE 48.7 101.8 138 643 +1988 2 1 6 18 TONY 34.2 292.5 43 650 +1998 11 3 6 17 WILLIAM 8.1 182.4 113 51 +1959 7 20 0 20 PATTY 54.4 93.6 18 523 +2002 5 28 12 4 SANDY 10.3 293.4 33 123 +1999 5 20 0 4 MICHAEL 27.7 199.0 42 60 +1987 6 17 6 18 JOYCE 42.9 270.4 140 150 +1971 2 23 18 5 HELENE 10.8 145.9 164 194 +1951 12 4 18 27 DEBBY 33.5 197.5 149 574 +1966 3 17 0 10 ERNESTO 26.4 150.3 139 58 +2002 3 10 18 28 MICHAEL 12.5 70.5 64 706 +1982 10 20 6 2 LESLIE 35.1 272.7 162 794 +1967 3 4 18 8 WILLIAM 49.1 254.2 150 714 +1972 8 25 18 28 HELENE 15.5 36.2 84 717 +1976 6 6 18 6 MICHAEL 56.9 17.6 150 630 +1951 3 14 18 5 OSCAR 19.4 41.1 90 497 +1986 2 18 0 23 NADINE 64.6 227.5 145 448 +1951 11 27 18 4 ERNESTO 35.0 219.7 20 894 +1994 6 3 18 24 BERYL 64.1 84.1 76 176 +1974 7 14 18 22 HELENE 28.2 302.1 159 95 +1964 3 24 18 10 SANDY 63.4 5.8 145 682 +1977 7 19 18 16 PATTY 57.3 92.9 81 393 +1989 6 3 18 28 ALBERTO 17.7 199.3 66 226 +1953 9 26 18 12 ALBERTO 69.3 154.0 111 776 +1997 11 28 6 20 CHRIS 29.4 283.3 36 504 +2003 4 10 0 1 ISAAC 36.4 197.4 64 60 +1966 5 13 6 13 MICHAEL 66.4 146.1 128 221 +1995 10 17 12 7 SANDY 9.8 17.3 104 837 +1966 8 10 6 12 BERYL 50.9 69.4 126 885 +1964 10 11 0 15 GORDON 54.8 299.9 137 729 +1951 1 15 0 13 WILLIAM 12.5 346.1 136 374 +1992 9 22 0 20 SANDY 13.7 86.2 57 556 +1962 11 4 0 1 SANDY 33.0 3.6 40 702 +1950 5 8 6 4 NADINE 68.3 256.9 84 29 +1985 2 15 18 14 KIRK 65.3 337.7 145 137 +1996 5 17 12 1 BERYL 33.5 342.6 97 631 +1982 7 15 12 7 WILLIAM 22.9 163.2 104 336 +1980 8 11 12 7 KIRK 33.7 352.1 142 730 +1999 2 13 18 25 LESLIE 59.6 258.3 81 869 +1967 11 9 12 9 ERNESTO 41.7 201.0 15 653 +1987 3 17 0 15 GORDON 59.0 324.3 87 626 +1974 1 11 6 6 KIRK 16.9 102.7 135 444 +1999 3 25 6 4 WILLIAM 22.2 59.8 22 139 +1996 1 25 6 8 ERNESTO 11.6 21.9 100 459 +1960 7 1 18 2 CHRIS 26.3 7.4 133 376 +1966 12 3 18 10 DEBBY 20.8 85.0 150 884 +1966 9 19 12 10 KIRK 10.8 257.1 143 258 +1950 11 19 12 7 ERNESTO 35.8 302.4 39 175 +1953 11 8 6 10 LESLIE 13.4 188.0 94 518 +1970 2 19 18 23 BERYL 34.8 254.5 25 406 +1987 8 20 12 24 ALBERTO 47.4 313.0 10 447 +1957 7 18 12 6 ALBERTO 48.0 176.6 70 684 +1953 5 27 6 17 FLORENCE 37.2 32.7 162 529 +1975 12 26 18 1 CHRIS 33.8 138.2 90 534 +1973 8 14 12 23 VALERIE 14.2 48.9 68 216 +1966 8 12 6 26 LESLIE 52.8 44.8 154 376 +1981 9 14 18 28 CHRIS 8.1 176.1 155 542 +1954 4 22 18 20 MICHAEL 17.1 41.7 119 333 +1963 12 9 18 1 KIRK 30.4 239.0 161 581 +1962 9 9 12 4 DEBBY 26.9 18.6 97 863 +1975 1 7 12 19 OSCAR 30.3 118.8 83 54 +1995 6 22 18 11 DEBBY 22.3 208.1 10 83 +1996 8 2 6 22 ERNESTO 41.0 210.7 135 284 +1954 10 27 0 13 WILLIAM 32.6 187.6 57 403 +2001 9 28 0 17 ALBERTO 69.3 287.9 136 650 +1969 7 23 0 26 PATTY 28.1 65.5 143 301 +1995 12 7 0 24 ALBERTO 33.7 10.2 18 250 +2004 1 20 6 13 SANDY 23.8 262.7 67 425 +1955 5 18 0 1 ERNESTO 41.8 336.9 50 471 +1970 8 4 6 15 WILLIAM 8.0 202.9 149 452 +1964 7 4 0 5 HELENE 38.5 91.8 65 683 +2003 9 8 0 5 ISAAC 38.9 18.1 101 256 +1979 12 7 18 3 LESLIE 49.3 326.8 68 292 +1963 6 16 6 25 RAFAEL 33.1 329.8 95 843 +1961 9 11 6 20 ISAAC 55.9 86.5 92 860 +1957 5 4 12 20 ALBERTO 34.1 70.9 68 585 +1964 1 2 18 13 MICHAEL 11.6 160.1 164 213 +1985 11 16 12 16 LESLIE 56.6 120.9 81 492 +1971 2 14 6 12 SANDY 43.7 86.2 101 84 +1966 3 4 0 25 ERNESTO 57.6 234.9 65 705 +1979 9 19 0 23 KIRK 69.2 81.1 24 890 +1987 4 19 18 28 ALBERTO 12.6 266.7 77 608 +1975 3 9 6 19 HELENE 43.4 123.4 49 841 +1979 8 18 12 6 HELENE 12.7 285.9 98 337 +1965 7 19 6 22 GORDON 16.3 176.9 26 9 +1964 2 4 0 23 DEBBY 43.9 70.1 63 495 +1982 5 4 12 8 OSCAR 61.8 13.9 27 170 +1995 12 12 0 7 DEBBY 19.4 128.6 37 436 +1998 1 27 6 20 VALERIE 63.2 265.8 114 396 +1986 9 25 18 23 WILLIAM 56.8 219.3 91 315 +1959 5 23 0 14 RAFAEL 16.4 80.8 131 201 +2003 6 21 6 18 RAFAEL 32.2 230.4 65 260 +1979 10 13 12 3 LESLIE 32.1 108.3 102 717 +1991 10 2 18 16 CHRIS 45.3 190.0 14 505 +2001 4 26 6 22 GORDON 15.1 72.1 78 472 +1990 10 2 6 26 ISAAC 9.2 4.7 32 226 +1969 4 10 6 1 OSCAR 26.4 161.1 85 251 +1994 3 10 6 13 MICHAEL 30.1 272.2 48 736 +1959 7 20 18 6 HELENE 55.6 166.9 149 604 +1994 11 4 12 18 WILLIAM 64.8 326.6 83 115 +1955 5 22 12 20 NADINE 48.6 190.6 18 164 +1994 8 8 18 7 ALBERTO 25.4 37.6 59 66 +1971 8 19 6 22 ERNESTO 38.5 160.6 145 539 +1959 6 20 0 3 OSCAR 8.0 63.5 110 35 +1956 12 11 18 23 ALBERTO 59.7 196.3 67 244 +1976 4 18 6 9 ERNESTO 19.3 325.8 153 643 +1959 8 16 12 8 WILLIAM 30.2 26.0 126 136 +1950 11 14 6 27 TONY 50.2 98.7 96 779 +1960 1 26 18 9 MICHAEL 39.0 232.5 37 87 +1988 1 13 12 28 PATTY 23.2 130.4 43 690 +1953 8 26 6 14 FLORENCE 21.1 212.9 120 50 +1974 5 20 12 11 TONY 34.3 38.6 115 281 +1962 12 3 18 24 LESLIE 62.9 130.2 148 606 +1975 1 10 18 19 VALERIE 52.9 174.2 78 222 +1985 9 10 0 27 HELENE 64.9 35.5 85 848 +1993 8 23 6 16 JOYCE 58.5 98.6 104 424 +1994 1 9 6 1 ERNESTO 11.5 202.2 132 546 +1963 8 17 0 27 KIRK 47.9 245.3 144 648 +1994 12 1 18 8 FLORENCE 41.4 1.8 156 263 +1950 9 18 18 14 PATTY 39.8 86.9 46 357 +1968 5 21 6 20 GORDON 31.3 239.8 27 574 +1960 3 11 6 6 HELENE 35.9 328.2 62 497 +1981 6 17 0 20 JOYCE 68.3 314.9 62 287 +1999 11 28 0 18 VALERIE 29.8 172.8 140 489 +1999 6 7 6 13 ISAAC 16.1 318.6 151 37 +1996 9 5 12 14 DEBBY 24.2 79.3 148 336 +1976 11 16 12 17 FLORENCE 34.6 229.3 25 693 +1982 9 4 12 23 ERNESTO 60.5 174.6 100 523 +1967 2 19 0 2 FLORENCE 48.0 110.9 93 540 +1961 7 22 12 9 ERNESTO 44.5 257.9 131 406 +1982 10 24 18 6 BERYL 66.5 31.3 145 617 +1968 9 22 18 5 TONY 62.3 248.2 108 98 +1990 3 7 0 18 HELENE 36.2 134.6 164 279 +1954 5 3 18 18 CHRIS 12.8 45.3 153 325 +1986 4 19 18 18 BERYL 11.4 136.0 124 521 +1990 2 25 12 7 SANDY 19.8 141.6 163 706 +1950 3 19 12 9 OSCAR 68.8 73.8 79 34 +1951 2 1 18 18 JOYCE 23.1 256.1 157 418 +2000 11 6 0 3 JOYCE 25.2 73.1 29 453 +1999 10 15 0 24 ERNESTO 18.2 114.8 143 769 +1974 4 28 12 13 NADINE 14.5 72.3 123 857 +1951 6 17 12 27 KIRK 55.8 309.9 156 666 +2002 1 5 6 5 GORDON 64.4 83.0 146 573 +1960 7 17 0 13 ERNESTO 59.2 281.5 76 321 +2002 12 23 18 27 NADINE 30.5 166.9 10 780 +1973 11 24 6 21 NADINE 66.4 50.2 59 78 +2004 5 20 6 3 WILLIAM 62.9 208.2 63 20 +1964 3 16 6 25 OSCAR 32.3 33.5 135 674 +1994 9 5 18 12 NADINE 69.6 330.1 118 414 +1955 9 26 0 10 JOYCE 19.5 257.5 163 317 +1970 11 10 0 16 FLORENCE 26.5 175.8 58 874 +1978 5 20 12 13 CHRIS 45.9 21.0 141 559 +1963 4 11 6 8 SANDY 39.4 70.9 61 707 +1977 8 16 0 23 FLORENCE 22.3 266.5 130 366 +1953 7 25 12 21 FLORENCE 10.2 173.8 30 602 +1965 12 16 6 19 ERNESTO 49.3 299.0 78 554 +1955 4 19 18 6 BERYL 67.8 313.7 87 459 +1983 10 24 0 13 FLORENCE 21.2 261.3 81 665 +1971 1 21 18 8 WILLIAM 41.8 113.1 17 861 +2003 3 3 0 13 HELENE 33.2 23.4 87 747 +1965 5 14 6 19 HELENE 57.8 39.6 78 84 +1960 12 22 12 24 JOYCE 63.6 264.9 86 180 +1970 12 14 18 18 SANDY 28.8 118.6 11 370 +1952 7 25 12 6 DEBBY 62.8 290.4 145 367 +1964 3 21 12 21 PATTY 40.5 351.0 152 177 +1951 2 2 18 2 WILLIAM 52.8 78.6 72 657 +1961 4 2 12 28 MICHAEL 54.4 321.3 42 609 +1978 6 2 12 13 TONY 21.4 94.4 153 787 +1977 9 27 12 2 TONY 63.1 303.2 82 304 +1966 9 14 6 3 ERNESTO 57.9 77.5 158 266 +1969 8 2 18 13 LESLIE 51.2 163.0 84 397 +1986 6 10 0 22 SANDY 40.1 198.6 154 435 +1956 7 25 0 3 FLORENCE 49.9 295.7 49 463 +1996 6 7 0 18 JOYCE 31.4 11.7 11 234 +1971 3 1 18 13 NADINE 38.3 287.3 59 711 +1963 7 20 6 11 OSCAR 15.7 212.6 30 728 +1988 9 17 0 8 JOYCE 12.6 105.0 122 712 +1978 5 8 12 15 ALBERTO 62.5 49.0 156 872 +1990 3 12 6 26 KIRK 44.1 307.7 34 172 +1970 7 3 12 26 CHRIS 19.5 346.5 133 898 +1991 4 4 18 25 WILLIAM 28.2 54.6 156 159 +1990 9 12 12 11 LESLIE 54.2 14.5 108 287 +1982 7 10 6 9 LESLIE 66.6 299.6 65 545 +1976 2 25 6 1 ISAAC 11.7 196.3 74 54 +1973 2 8 12 3 DEBBY 19.1 296.4 142 24 +1998 4 27 12 27 DEBBY 22.6 214.1 129 884 +1990 4 17 18 5 OSCAR 64.8 164.5 16 518 +1981 4 10 18 26 ISAAC 38.1 34.4 22 314 +1983 6 28 6 6 RAFAEL 10.1 147.7 140 725 +1979 6 22 0 3 WILLIAM 26.7 158.0 12 208 +1959 1 7 6 19 BERYL 42.4 166.2 73 393 +1999 2 27 12 28 PATTY 11.1 203.1 72 301 +1975 7 11 18 27 PATTY 9.7 29.2 82 226 +1982 8 2 12 3 BERYL 58.7 29.8 150 198 +1953 10 7 18 8 OSCAR 17.4 150.0 130 618 +1996 12 22 6 2 DEBBY 7.5 329.9 17 261 +1968 1 13 12 22 NADINE 12.6 228.0 144 790 +1960 1 7 6 12 DEBBY 67.3 65.5 157 98 +1987 7 9 6 8 WILLIAM 44.8 65.9 128 542 +1998 3 12 0 26 HELENE 64.8 284.1 86 771 +1969 8 10 0 17 HELENE 68.0 272.0 49 250 +1974 10 13 6 1 CHRIS 9.8 107.7 44 640 +1959 10 11 12 3 OSCAR 25.6 59.4 63 510 +1998 10 13 6 25 TONY 15.4 8.1 125 769 +1982 5 27 6 4 ISAAC 14.9 259.5 126 176 +1982 11 7 18 14 FLORENCE 62.1 149.1 10 69 +1979 2 26 6 6 ALBERTO 15.9 333.6 69 498 +1968 10 13 12 6 CHRIS 8.0 175.4 30 729 +1993 1 18 12 7 CHRIS 28.1 111.8 157 422 +1951 10 6 18 11 DEBBY 38.5 349.7 36 660 +1977 9 5 12 21 KIRK 58.2 181.4 134 217 +1995 5 17 6 14 TONY 20.9 113.1 120 319 +2000 7 3 12 17 GORDON 46.2 295.2 90 400 +1972 6 14 6 23 KIRK 19.8 301.2 29 131 +1975 1 13 18 26 ERNESTO 9.5 157.4 131 427 +1955 6 27 18 16 LESLIE 68.9 166.7 46 594 +1984 9 2 18 28 NADINE 58.1 147.4 111 206 +2004 7 20 18 7 ALBERTO 60.0 134.2 96 378 +1957 4 8 0 25 TONY 13.8 41.7 84 544 +1961 9 18 6 16 SANDY 12.7 153.5 163 401 +1950 1 4 18 9 KIRK 40.1 295.4 38 791 +1987 11 18 12 2 RAFAEL 69.7 38.2 100 85 +1953 4 1 6 7 BERYL 15.5 170.8 57 478 +1956 4 27 0 24 NADINE 59.6 87.7 130 125 +1965 6 16 6 19 PATTY 60.6 208.7 107 884 +1972 5 4 0 15 RAFAEL 20.5 190.2 11 51 +1960 1 28 12 13 LESLIE 55.5 119.7 36 369 +1979 1 2 12 20 ERNESTO 40.2 225.8 90 70 +1997 2 27 0 27 RAFAEL 60.9 32.7 36 631 +1998 6 27 6 20 TONY 36.4 155.8 99 683 +1968 2 5 12 21 ISAAC 32.2 27.2 162 881 +1977 1 27 18 1 LESLIE 41.7 84.4 155 361 +1982 6 10 0 18 GORDON 10.1 195.2 136 809 +1953 8 14 6 18 ISAAC 69.6 122.4 72 550 +1954 1 21 18 2 ISAAC 14.8 111.7 125 716 +1963 10 21 0 1 ALBERTO 38.5 50.1 122 199 +1953 8 19 18 13 PATTY 19.8 232.5 40 190 +1967 11 17 0 5 SANDY 33.5 279.2 109 651 +1982 9 3 12 20 NADINE 47.3 287.0 108 205 +1953 11 27 0 21 TONY 32.2 319.1 37 550 +1964 6 2 18 27 TONY 20.1 121.0 88 712 +1991 10 25 18 14 JOYCE 50.5 28.8 86 182 +1954 7 24 0 25 PATTY 45.4 142.2 53 42 +2000 3 13 18 27 VALERIE 17.1 260.8 57 335 +1963 2 12 18 25 VALERIE 31.8 66.6 152 379 +1959 9 20 0 20 FLORENCE 37.5 123.2 23 695 +1977 10 17 12 26 ISAAC 24.4 164.7 95 554 +1986 11 25 18 16 ALBERTO 21.0 337.4 147 499 +2003 7 10 6 15 FLORENCE 38.9 11.1 10 754 +1972 2 25 0 10 NADINE 50.4 268.0 70 23 +1970 8 3 6 13 DEBBY 9.6 28.9 152 826 +1952 4 1 12 10 WILLIAM 29.7 81.3 56 650 +1994 3 25 18 6 RAFAEL 30.8 64.0 28 437 +1964 6 7 6 24 PATTY 60.7 326.2 120 601 +1950 1 21 0 19 FLORENCE 35.9 315.5 107 276 +2002 3 5 6 27 PATTY 53.2 296.8 87 806 +2001 5 28 6 9 BERYL 15.2 161.1 158 733 +1960 12 19 12 3 ALBERTO 7.7 146.2 135 782 +1985 12 22 12 5 BERYL 29.9 125.8 133 611 +2000 1 23 0 23 OSCAR 37.3 87.4 92 12 +1962 11 12 6 21 LESLIE 51.3 306.0 163 708 +1990 11 6 12 10 HELENE 50.2 31.8 104 457 +1961 5 4 0 5 LESLIE 63.4 30.8 92 693 +1951 7 22 0 16 DEBBY 61.7 337.3 35 126 +2000 8 9 18 4 MICHAEL 48.2 208.2 133 4 +1957 10 2 12 6 WILLIAM 32.8 151.8 46 510 +2002 10 18 0 27 GORDON 65.0 188.4 63 269 +1983 2 19 12 14 VALERIE 51.8 131.5 14 454 +1978 6 16 18 6 JOYCE 42.0 123.5 106 23 +2004 5 14 0 28 FLORENCE 23.6 8.6 124 273 +1985 11 25 6 11 KIRK 49.1 20.5 146 752 +1985 9 18 6 25 TONY 25.4 344.9 113 429 +1953 9 16 6 5 CHRIS 12.5 283.6 158 576 +1987 3 12 12 14 CHRIS 57.4 330.4 95 874 +1998 5 21 0 19 VALERIE 35.0 342.4 43 296 +1992 3 26 6 25 TONY 60.2 219.1 84 82 +1978 9 9 18 16 RAFAEL 24.9 349.8 104 77 +1966 11 6 6 23 WILLIAM 64.9 102.1 78 780 +1980 9 1 18 13 FLORENCE 27.3 34.1 134 877 +1986 7 15 18 5 WILLIAM 39.7 278.0 158 631 +2004 2 10 18 21 LESLIE 7.4 330.0 51 524 +1954 8 18 6 1 KIRK 38.8 295.3 130 481 +1974 10 28 0 24 TONY 62.1 36.4 138 765 +1991 7 24 0 8 FLORENCE 36.1 70.7 51 304 +1998 3 22 6 4 PATTY 22.6 193.3 139 95 +1966 7 19 6 27 KIRK 55.7 233.4 66 878 +1952 11 25 18 12 LESLIE 9.4 348.9 164 833 +1972 12 1 12 18 OSCAR 45.3 141.1 116 763 +1959 7 14 18 13 ALBERTO 62.7 210.0 62 769 +1950 6 9 12 23 RAFAEL 58.0 95.0 105 505 +1953 6 12 6 6 ERNESTO 42.8 54.2 113 712 +1989 2 28 18 15 LESLIE 45.5 197.4 139 781 +1953 10 16 12 22 LESLIE 68.3 48.3 133 893 +1971 1 19 6 19 FLORENCE 15.3 289.1 82 25 +1953 1 9 6 6 DEBBY 18.5 235.0 149 331 +1983 1 18 6 3 PATTY 41.9 336.5 75 526 +2001 6 12 18 7 FLORENCE 44.8 23.2 117 497 +1987 2 13 0 8 DEBBY 52.2 148.3 152 433 +1996 10 17 0 11 PATTY 25.3 253.6 92 476 +1966 8 10 0 25 RAFAEL 18.4 165.3 148 408 +1975 6 26 12 27 CHRIS 13.6 300.0 96 130 +1994 3 6 6 25 DEBBY 10.3 231.0 80 306 +1958 12 5 12 22 DEBBY 26.0 327.7 31 873 +1994 12 21 18 23 BERYL 36.1 5.9 148 413 +1989 9 3 18 7 SANDY 44.6 238.9 18 823 +1955 2 5 18 26 OSCAR 57.1 119.1 63 285 +2001 9 28 0 4 WILLIAM 8.0 184.6 18 88 +1988 2 5 6 8 DEBBY 66.4 53.6 103 556 +1966 11 5 0 27 KIRK 48.2 211.2 120 438 +1971 9 16 12 4 PATTY 17.6 162.4 161 667 +2001 10 11 0 7 KIRK 22.8 291.9 23 48 +1969 3 23 12 13 NADINE 10.3 100.9 116 860 +1979 6 15 18 9 ALBERTO 14.3 77.6 42 506 +1990 6 19 12 10 TONY 38.0 101.8 107 649 +1955 5 2 6 25 PATTY 60.7 297.8 138 889 +1985 6 4 6 15 BERYL 28.9 316.5 105 499 +1961 12 9 6 4 NADINE 34.4 311.2 50 311 +1954 10 15 18 2 GORDON 47.8 58.4 42 192 +1953 9 8 12 10 HELENE 22.2 63.8 146 346 +1961 1 15 0 28 WILLIAM 56.7 92.5 93 545 +1980 3 21 18 27 MICHAEL 53.5 72.7 71 666 +1961 4 28 18 2 JOYCE 17.0 52.1 37 866 +1963 6 17 12 3 PATTY 32.6 284.1 86 754 +1959 4 26 0 16 VALERIE 51.2 38.2 44 840 +1964 5 3 12 13 MICHAEL 22.3 270.8 12 325 +1955 6 2 12 5 ALBERTO 47.5 109.0 152 843 +1979 4 27 18 2 PATTY 24.5 169.4 164 761 +1992 9 25 6 6 JOYCE 50.2 101.7 153 367 +1995 2 1 0 16 GORDON 55.3 160.6 163 126 +1953 8 4 12 18 SANDY 49.2 16.2 56 81 +1969 1 17 6 21 NADINE 51.6 280.0 73 858 +1968 4 3 12 17 OSCAR 53.6 242.5 31 479 +1961 1 1 18 5 ERNESTO 40.8 96.9 18 738 +2003 2 19 0 3 MICHAEL 34.4 119.8 126 181 +1961 12 24 6 8 MICHAEL 66.7 273.8 12 767 +1990 8 19 6 24 FLORENCE 15.4 144.7 160 339 +1969 12 4 12 16 OSCAR 58.0 348.6 33 49 +1997 5 13 0 21 ERNESTO 53.8 338.1 93 185 +1957 12 19 12 6 RAFAEL 47.7 312.8 129 86 +1998 4 13 6 11 OSCAR 56.3 248.5 69 168 +1961 5 8 0 15 OSCAR 9.6 141.6 120 164 +1991 8 23 12 12 SANDY 49.4 280.1 118 864 +1962 11 16 0 22 OSCAR 18.3 323.7 71 766 +1980 1 23 18 17 SANDY 59.4 111.1 15 854 +1962 11 2 12 11 DEBBY 68.5 52.8 75 79 +1998 1 7 6 14 GORDON 52.3 280.3 160 710 +2001 12 23 0 26 KIRK 26.1 282.7 89 785 +1953 12 13 12 18 ERNESTO 34.3 235.0 104 609 +1950 3 15 0 20 MICHAEL 31.9 307.1 145 731 +1952 8 10 0 15 BERYL 27.4 234.5 117 141 +1989 8 1 0 4 OSCAR 17.2 84.8 113 837 +1977 9 15 18 6 BERYL 32.4 95.0 61 768 +1998 12 19 6 5 FLORENCE 8.5 130.3 47 486 +1967 8 12 0 15 SANDY 30.0 125.4 61 694 +1976 10 9 18 9 SANDY 60.0 46.9 106 551 +1960 9 25 0 7 MICHAEL 37.9 340.5 61 507 +2004 7 28 18 26 NADINE 42.8 37.5 140 179 +1953 11 28 18 9 HELENE 14.4 135.6 14 719 +1976 1 17 0 26 BERYL 50.3 86.8 75 164 +1979 2 4 18 20 CHRIS 30.9 139.5 67 761 +1987 7 4 0 5 KIRK 38.0 67.7 69 107 +1968 5 12 12 4 WILLIAM 21.0 79.6 57 606 +1977 6 11 6 4 TONY 9.4 172.2 51 432 +1981 11 18 6 14 WILLIAM 11.6 118.4 12 525 +1984 3 22 6 17 NADINE 65.7 95.4 164 629 +1990 10 8 0 21 RAFAEL 60.8 92.9 22 389 +1984 7 4 12 10 FLORENCE 19.3 219.1 40 42 +1961 6 28 12 12 GORDON 15.4 31.2 13 47 +1989 6 20 6 28 MICHAEL 50.7 102.7 29 472 +1959 3 28 12 4 HELENE 54.0 19.2 79 589 +1960 7 22 18 22 LESLIE 39.1 303.8 26 610 +1962 10 27 0 12 FLORENCE 7.3 356.9 10 857 +1974 2 10 12 1 OSCAR 23.3 135.3 111 186 +1987 4 9 0 9 PATTY 29.4 323.7 141 192 +1994 12 24 18 24 KIRK 11.9 326.8 16 579 +1971 10 5 12 26 CHRIS 20.0 309.2 49 208 +1982 7 11 6 28 HELENE 53.7 323.8 164 364 +1953 4 5 0 1 ISAAC 41.6 293.9 25 200 +1998 4 24 18 17 ISAAC 20.1 114.7 50 375 +1989 4 12 0 5 DEBBY 15.9 223.9 16 41 +1999 11 2 18 15 FLORENCE 53.1 321.6 141 231 +1970 2 4 6 12 SANDY 65.1 303.6 156 477 +1952 1 1 12 2 WILLIAM 41.3 151.9 74 895 +1953 10 14 18 17 SANDY 26.8 104.6 100 355 +1952 3 10 0 14 GORDON 39.9 298.7 75 802 +1970 4 28 12 12 MICHAEL 69.5 59.5 21 605 +1984 11 7 12 25 PATTY 25.7 108.3 90 519 +1979 11 26 0 1 PATTY 21.5 136.4 161 248 +1997 6 17 18 2 ISAAC 65.9 321.8 145 525 +1988 8 18 12 7 ISAAC 28.2 41.2 154 135 +1986 1 25 6 14 DEBBY 40.8 239.6 158 34 +1973 9 22 12 8 CHRIS 42.3 182.0 91 281 +1985 1 20 6 28 ALBERTO 45.3 45.3 82 255 +1984 8 27 0 2 TONY 62.5 183.9 18 805 +1971 9 13 12 26 LESLIE 51.9 294.6 149 682 +1989 1 15 12 9 RAFAEL 16.3 168.9 125 321 +1967 8 4 18 24 ISAAC 67.7 46.2 137 825 +1980 10 22 6 9 ISAAC 22.2 148.6 14 750 +1984 6 15 12 10 FLORENCE 28.2 326.5 115 101 +1958 3 12 12 7 MICHAEL 60.7 171.6 38 250 +1950 3 12 0 21 KIRK 15.5 203.9 45 430 +1999 2 10 12 20 LESLIE 17.6 19.2 95 48 +1986 12 18 0 28 WILLIAM 9.4 91.8 21 815 +1998 1 11 12 22 CHRIS 45.3 79.6 55 300 +1987 3 19 18 25 MICHAEL 68.3 32.1 107 716 +1952 7 2 0 17 TONY 66.9 53.7 37 348 +1982 2 18 18 9 MICHAEL 12.1 48.3 25 894 +2002 6 11 0 11 DEBBY 55.7 234.3 137 69 +1983 9 4 18 19 CHRIS 36.7 281.2 51 169 +1961 9 16 12 27 ALBERTO 55.5 123.5 17 47 +2002 7 8 6 20 CHRIS 68.4 275.3 25 317 +1975 8 7 12 8 OSCAR 18.0 295.4 65 422 +1991 8 5 0 19 KIRK 33.0 41.0 27 291 +1990 8 8 0 14 NADINE 42.9 240.6 32 597 +1957 12 2 18 14 CHRIS 14.5 5.2 34 722 +1960 8 6 18 6 NADINE 12.2 20.9 81 875 +1960 2 26 18 27 PATTY 42.7 104.3 93 185 +1962 10 25 6 15 TONY 29.0 331.5 148 240 +1960 12 28 6 6 HELENE 48.2 124.8 67 594 +1984 2 21 12 28 WILLIAM 28.7 278.3 154 132 +1950 3 15 18 20 HELENE 61.6 99.7 91 250 +1962 10 25 12 11 VALERIE 31.8 203.4 155 666 +1954 12 1 18 12 ISAAC 53.8 309.9 68 737 +1977 2 5 12 17 NADINE 41.8 13.3 70 364 +1971 3 6 6 16 NADINE 69.5 71.4 126 410 +1961 1 26 0 3 VALERIE 7.7 51.3 139 629 +1959 2 17 18 27 MICHAEL 40.1 109.8 114 814 +1988 3 11 0 23 GORDON 41.2 292.0 151 548 +1959 4 8 6 21 GORDON 48.1 156.5 99 34 +1978 2 24 12 7 VALERIE 18.0 147.6 39 125 +1961 11 23 0 4 JOYCE 68.5 294.6 108 599 +1952 7 14 18 26 FLORENCE 25.8 233.2 159 539 +2001 8 15 6 19 CHRIS 65.3 160.1 22 831 +1989 5 19 12 5 LESLIE 39.9 228.3 10 205 +1967 1 15 18 18 NADINE 55.9 38.5 24 339 +2004 11 28 6 15 GORDON 39.0 65.5 107 135 +1970 2 7 6 24 JOYCE 54.6 95.2 132 815 +1995 3 3 12 3 RAFAEL 8.5 241.3 39 84 +1969 7 19 12 1 SANDY 57.1 93.8 59 822 +1990 9 25 18 26 ALBERTO 18.7 261.3 135 873 +1974 6 2 6 14 KIRK 24.5 111.8 69 177 +1983 10 19 0 18 ISAAC 12.9 125.8 73 586 +1977 5 25 12 21 TONY 24.1 29.0 94 44 +1964 7 17 6 2 KIRK 8.0 152.8 153 138 +1964 1 6 12 28 BERYL 67.0 239.4 30 143 +1970 12 12 0 5 TONY 7.4 160.9 144 215 +1984 9 14 6 26 RAFAEL 30.4 196.6 16 607 +1984 6 6 12 3 BERYL 12.5 182.5 124 617 +1973 6 26 0 3 KIRK 19.3 193.8 139 296 +1952 4 3 0 24 ISAAC 16.0 229.3 136 791 +2003 10 17 12 15 SANDY 29.1 146.9 137 465 +1953 4 9 12 5 DEBBY 31.0 155.0 160 738 +1952 10 9 6 18 JOYCE 15.8 281.5 124 128 +1994 1 5 0 13 JOYCE 20.0 193.3 95 52 +1993 10 10 0 19 ERNESTO 45.6 221.2 110 53 +1973 6 17 0 3 PATTY 63.9 261.6 80 173 +1966 11 22 18 8 GORDON 11.0 194.0 24 227 +1985 5 2 12 19 DEBBY 31.5 307.0 83 656 +1990 10 21 6 10 TONY 43.5 105.6 141 558 +1974 1 24 6 21 PATTY 15.6 17.7 129 619 +1989 2 13 12 14 VALERIE 18.2 68.4 92 279 +1977 7 17 18 23 OSCAR 11.4 77.5 162 561 +1964 10 14 18 8 FLORENCE 35.4 282.3 64 453 +1975 8 12 18 19 OSCAR 9.5 135.0 129 270 +1994 7 2 6 24 WILLIAM 35.7 354.0 137 250 +1996 4 17 18 19 FLORENCE 36.7 46.2 71 802 +2002 9 1 6 20 RAFAEL 39.3 11.4 26 539 +1980 7 25 12 27 KIRK 40.7 302.3 99 158 +1998 5 1 12 20 OSCAR 46.3 82.0 139 197 +1956 7 5 0 25 LESLIE 12.2 8.9 41 20 +1965 11 10 6 4 TONY 9.6 22.9 23 760 +1980 12 22 18 12 OSCAR 12.1 204.8 83 590 +1987 5 26 18 9 KIRK 52.4 322.7 149 1 +1952 6 28 6 26 CHRIS 47.9 42.2 95 401 +1959 3 15 0 12 DEBBY 32.3 251.3 93 4 +1950 7 14 6 19 BERYL 54.9 159.2 74 26 +1988 7 22 12 14 KIRK 50.7 261.6 145 880 +2000 6 9 0 1 KIRK 61.5 302.5 31 71 +1969 12 23 18 1 FLORENCE 53.0 118.3 122 279 +1988 7 3 18 4 BERYL 66.2 342.8 151 762 +2000 9 3 12 18 ISAAC 37.0 57.3 120 634 +1963 8 23 6 3 GORDON 7.0 201.0 38 586 +1952 3 7 6 18 JOYCE 16.2 88.3 10 608 +1986 4 20 12 20 ERNESTO 62.3 316.1 146 558 +2000 6 3 12 8 GORDON 36.4 262.8 141 56 +1991 9 8 0 27 DEBBY 56.9 305.2 89 848 +1985 6 8 6 8 RAFAEL 61.2 143.9 38 644 +1950 3 20 0 23 VALERIE 12.3 340.6 15 419 +1970 6 15 12 5 MICHAEL 32.9 232.7 91 579 +1995 2 23 18 12 BERYL 15.9 62.6 102 580 +1964 7 1 0 7 ISAAC 20.0 180.6 36 98 +1965 6 4 0 12 FLORENCE 51.4 139.7 149 642 +1956 2 12 0 14 MICHAEL 66.0 10.5 115 676 +1991 4 1 0 13 SANDY 50.0 213.8 131 302 +1963 5 13 18 23 NADINE 37.7 335.6 45 548 +1989 2 10 18 24 TONY 50.1 253.5 57 201 +1959 6 23 0 24 JOYCE 67.5 134.8 10 280 +1969 8 5 6 20 CHRIS 37.3 224.2 28 589 +1998 11 16 6 11 CHRIS 43.0 128.2 124 17 +1997 12 14 6 11 DEBBY 17.0 249.8 29 134 +1959 7 3 12 26 RAFAEL 8.8 316.4 23 450 +1965 1 6 6 10 JOYCE 33.3 38.7 71 571 +2001 8 28 12 15 MICHAEL 15.5 176.7 24 743 +1956 12 25 6 18 SANDY 41.8 17.2 86 248 +1980 10 21 12 10 TONY 37.9 159.9 148 567 +1990 9 5 18 25 ERNESTO 20.7 285.7 27 864 +1967 2 6 0 22 SANDY 38.8 45.5 20 527 +1973 8 1 18 21 FLORENCE 55.3 350.6 93 600 +1993 3 14 6 6 MICHAEL 31.1 116.5 46 289 +1974 4 18 6 17 JOYCE 27.0 256.6 103 142 +1982 4 20 18 10 JOYCE 63.7 282.4 142 217 +1963 4 13 18 4 PATTY 57.2 20.2 101 762 +1991 4 13 18 4 MICHAEL 44.2 196.4 107 830 +1952 7 19 0 15 GORDON 54.7 297.2 80 434 +2002 3 17 18 25 KIRK 43.5 255.7 78 147 +1983 4 11 0 13 OSCAR 46.2 8.5 35 385 +1954 2 16 12 23 BERYL 42.2 228.0 104 483 +1996 12 18 0 14 KIRK 38.6 57.1 144 593 +1990 4 17 0 20 CHRIS 18.3 77.7 109 767 +1987 2 11 0 7 KIRK 66.6 118.8 59 501 +1996 12 11 18 2 VALERIE 68.7 20.3 152 281 +1994 10 17 12 10 ALBERTO 14.2 168.8 51 785 +1950 11 5 0 23 LESLIE 64.0 112.4 14 641 +1998 2 5 12 3 KIRK 13.7 226.7 59 54 +1957 7 5 18 7 JOYCE 15.0 59.7 127 579 +1976 10 13 6 7 KIRK 9.0 258.7 76 40 +1993 9 12 12 1 ISAAC 17.4 312.6 81 297 +1954 6 21 6 7 ISAAC 56.3 321.3 155 339 +1995 5 6 0 7 ALBERTO 31.8 234.1 120 794 +1995 12 25 6 25 LESLIE 38.9 16.3 61 785 +1966 7 18 18 24 TONY 66.3 186.7 55 257 +1986 2 26 12 1 VALERIE 63.7 244.1 70 212 +1974 8 6 0 26 HELENE 37.1 272.0 139 515 +1999 9 13 18 28 JOYCE 15.8 80.8 119 334 +1986 12 26 12 17 OSCAR 37.5 287.1 36 806 +2001 1 7 18 4 MICHAEL 18.0 251.6 132 76 +1982 9 13 18 11 ALBERTO 42.4 146.8 80 299 +1987 7 22 12 11 LESLIE 45.4 337.7 66 240 +1982 7 13 0 14 ALBERTO 41.1 277.5 160 481 +1990 7 3 12 2 FLORENCE 34.9 355.7 91 745 +2000 5 18 0 28 BERYL 50.1 129.7 107 400 +1970 3 18 18 20 PATTY 45.0 300.7 143 69 +1960 4 20 18 7 HELENE 48.7 195.2 114 194 +1981 8 17 6 28 DEBBY 66.7 3.5 129 212 +1998 1 5 6 12 SANDY 41.9 69.3 59 132 +1993 3 3 18 28 HELENE 66.2 9.6 71 699 +1986 6 3 12 1 ALBERTO 8.6 87.8 124 800 +1999 1 4 12 14 DEBBY 13.7 131.1 55 327 +1981 3 2 0 14 TONY 49.9 211.8 164 701 +2004 11 7 0 2 WILLIAM 44.6 90.1 20 557 +2001 6 23 6 10 ISAAC 58.9 91.5 51 714 +1984 2 21 18 15 LESLIE 23.7 301.4 87 296 +1970 8 2 0 16 LESLIE 33.0 236.1 115 532 +1965 4 23 6 10 SANDY 9.4 278.0 17 123 +1982 8 18 18 24 WILLIAM 54.4 336.9 16 597 +1986 10 4 0 23 DEBBY 14.8 105.8 70 806 +1953 11 10 18 3 PATTY 67.8 185.7 74 122 +1998 6 22 6 27 ERNESTO 33.3 110.7 115 176 +1963 10 7 6 17 HELENE 30.5 224.8 34 440 +1958 6 24 0 2 JOYCE 10.6 20.4 26 333 +1972 8 26 0 6 LESLIE 24.3 132.9 123 848 +1993 6 19 6 23 VALERIE 25.9 9.5 32 66 +1957 3 27 0 28 DEBBY 61.4 79.6 141 412 +1964 10 9 6 20 RAFAEL 31.4 17.3 117 873 +1953 11 17 12 4 ISAAC 59.7 332.8 153 413 +1985 12 18 6 19 VALERIE 18.7 81.4 138 262 +1953 11 10 18 3 WILLIAM 50.8 271.7 127 690 +1956 10 16 6 1 ALBERTO 17.4 353.4 85 21 +1996 11 14 6 1 NADINE 8.5 266.7 94 163 +1971 8 11 0 4 JOYCE 32.2 2.0 18 105 +1985 11 13 6 3 ISAAC 32.2 85.0 71 390 +1980 6 19 12 2 DEBBY 49.6 120.9 104 331 +1999 7 23 18 8 JOYCE 10.6 44.7 93 467 +1970 11 4 18 23 NADINE 10.5 354.9 115 847 +1959 9 27 12 4 HELENE 24.1 224.6 87 175 +2001 2 22 12 22 ISAAC 19.6 240.5 73 368 +2001 3 9 18 3 ERNESTO 17.9 8.8 71 406 +1981 12 21 18 15 GORDON 53.9 180.9 33 867 +1999 12 9 12 24 BERYL 18.3 161.3 31 741 +1956 12 21 18 26 NADINE 67.7 147.8 115 387 +1952 8 20 0 24 PATTY 31.0 270.9 79 112 +1985 8 10 18 26 KIRK 63.1 243.5 15 358 +1954 6 19 0 27 HELENE 64.2 237.1 70 468 +1959 8 8 6 20 ALBERTO 24.7 309.1 102 156 +1959 4 19 0 9 CHRIS 47.0 291.0 39 578 +2003 8 20 6 15 NADINE 57.9 175.5 28 690 +1963 9 26 6 11 CHRIS 62.4 42.4 77 204 +1978 6 5 12 15 TONY 38.7 114.6 68 0 +1957 1 24 12 26 GORDON 65.6 357.5 136 437 +1965 2 24 12 9 VALERIE 39.6 67.5 91 641 +1991 10 11 0 21 DEBBY 41.9 327.2 137 786 +1957 10 21 6 24 JOYCE 7.3 147.1 84 761 +1996 6 25 18 9 LESLIE 20.0 93.3 110 842 +1954 12 6 6 8 WILLIAM 48.3 138.4 59 891 +1979 7 13 0 14 LESLIE 40.4 321.8 154 757 +1980 10 4 0 9 FLORENCE 60.6 281.9 79 556 +1980 1 3 18 25 DEBBY 39.5 356.4 18 521 +1981 7 4 18 1 RAFAEL 67.9 334.0 43 514 +1992 1 27 12 9 GORDON 49.3 268.0 91 96 +1990 1 21 18 24 ERNESTO 14.8 98.7 61 94 +1989 6 17 6 14 WILLIAM 45.4 273.6 49 883 +1996 7 7 12 28 OSCAR 40.3 219.1 11 542 +1956 12 13 6 12 BERYL 47.5 40.8 41 735 +1989 5 2 12 23 NADINE 58.6 32.7 93 371 +1964 2 19 12 9 VALERIE 23.2 155.6 73 534 +1994 8 18 0 12 TONY 53.7 157.7 68 735 +1966 10 12 18 13 GORDON 70.0 321.8 154 292 +1981 12 16 18 25 JOYCE 17.8 171.5 60 414 +1993 3 17 6 9 FLORENCE 50.0 82.9 75 513 +1983 5 17 12 10 KIRK 69.3 43.7 107 693 +1972 11 8 6 18 WILLIAM 15.9 22.1 101 236 +1955 8 12 18 17 SANDY 37.8 215.0 137 651 +2000 7 13 6 1 VALERIE 16.7 322.3 17 889 +1990 11 7 0 22 CHRIS 58.9 236.7 138 568 +1955 9 11 0 22 WILLIAM 19.1 261.6 108 5 +1982 1 24 6 23 ISAAC 12.9 157.5 32 557 +1971 5 22 0 25 JOYCE 38.5 288.5 46 67 +2004 10 13 18 18 SANDY 25.1 333.0 120 117 +1989 2 1 6 6 NADINE 43.5 342.0 147 555 +1968 7 3 18 18 SANDY 21.6 270.5 24 423 +1958 9 26 0 5 HELENE 10.3 163.4 138 762 +1975 9 28 0 13 BERYL 35.7 250.6 141 209 +1993 7 6 0 10 NADINE 10.0 300.7 161 248 +1986 2 2 6 8 WILLIAM 36.4 202.6 129 148 +1993 1 22 0 10 VALERIE 23.5 114.9 132 361 +1981 7 1 12 27 TONY 54.2 117.6 130 669 +2004 11 10 0 6 CHRIS 9.9 72.0 61 831 +1971 11 8 0 6 GORDON 7.5 21.3 61 635 +2004 9 15 18 13 MICHAEL 38.1 14.5 112 581 +1980 11 19 12 21 BERYL 23.9 77.8 67 662 +1952 7 23 0 5 PATTY 47.8 74.7 89 213 +1981 11 22 18 25 TONY 23.4 8.2 89 677 +1992 8 10 12 25 JOYCE 44.4 288.1 161 112 +1989 11 3 18 13 WILLIAM 39.1 93.1 52 585 +1951 11 10 6 1 CHRIS 46.2 201.2 164 375 +1993 9 3 6 24 SANDY 10.9 43.2 16 15 +1966 11 27 0 17 LESLIE 51.3 290.2 47 254 +1973 9 16 12 24 BERYL 13.0 59.4 48 827 +1971 5 6 18 28 CHRIS 16.2 98.2 133 26 +1960 10 4 0 1 CHRIS 49.5 201.9 86 697 +1994 11 11 6 2 JOYCE 37.7 74.9 128 796 +1981 5 27 18 10 SANDY 52.7 96.3 47 699 +1951 8 11 0 10 LESLIE 52.6 294.4 63 776 +1989 1 10 0 18 GORDON 59.6 274.9 81 560 +1973 8 24 12 9 ALBERTO 63.2 312.5 45 492 +1989 12 16 12 23 TONY 32.1 13.3 143 428 +1962 3 12 6 21 SANDY 12.7 145.4 132 35 +1952 9 15 12 9 ISAAC 44.9 154.1 49 170 +1966 10 5 18 18 BERYL 49.2 192.3 144 177 +1968 7 10 18 23 PATTY 54.2 247.4 18 557 +1956 4 7 6 18 MICHAEL 21.5 18.1 101 416 +1969 2 21 18 5 NADINE 67.4 61.8 85 341 +1955 10 17 18 18 NADINE 23.8 352.7 46 789 +1953 12 20 12 20 MICHAEL 65.7 123.5 148 485 +1952 1 1 12 3 TONY 57.6 300.3 50 853 +1979 12 17 6 7 DEBBY 19.4 278.3 112 373 +1958 2 20 12 24 MICHAEL 11.3 28.3 73 470 +1988 1 3 18 12 BERYL 62.4 298.8 42 202 +1961 4 9 12 6 LESLIE 32.9 43.9 146 60 +1998 1 24 12 17 DEBBY 26.1 243.4 22 699 +1989 8 20 0 8 SANDY 53.9 297.1 85 320 +1994 11 8 18 18 OSCAR 38.2 166.5 120 69 +2003 11 13 6 14 ALBERTO 18.2 128.8 21 597 +1955 12 18 18 10 HELENE 47.5 133.7 42 342 +1980 7 18 18 21 VALERIE 49.7 48.2 58 291 +1993 9 16 6 13 KIRK 25.2 145.3 20 88 +1968 7 17 0 21 SANDY 24.0 82.7 86 837 +1965 3 28 6 11 NADINE 47.8 144.5 160 40 +2002 7 16 12 7 ERNESTO 8.4 64.6 15 436 +1982 4 20 12 20 SANDY 39.1 24.0 34 346 +1956 8 13 12 11 CHRIS 8.7 136.2 74 648 +1984 4 3 18 7 PATTY 63.2 181.3 132 202 +1997 10 21 0 8 MICHAEL 67.1 16.3 137 556 +1996 10 15 0 8 KIRK 51.5 30.7 46 849 +1964 11 14 6 14 PATTY 32.8 24.6 100 647 +1959 10 6 0 1 VALERIE 32.2 268.5 21 149 +1955 3 24 0 6 HELENE 31.4 281.0 19 549 +1950 12 8 6 3 TONY 68.2 62.1 109 160 +1998 9 27 0 8 HELENE 63.2 24.3 55 775 +1982 8 27 12 23 RAFAEL 53.4 79.7 153 395 +1970 11 12 6 17 TONY 60.7 334.7 42 871 +1968 1 18 6 18 FLORENCE 20.5 190.4 35 264 +1976 10 13 18 28 KIRK 45.4 169.9 18 267 +1987 3 6 12 14 HELENE 68.1 79.5 51 122 +1995 12 15 0 19 ERNESTO 19.5 37.6 108 21 +1968 4 6 0 18 KIRK 45.8 135.5 26 671 +1981 4 24 12 6 KIRK 36.4 204.9 118 671 +1979 4 16 6 13 ISAAC 20.5 127.0 117 72 +1977 6 20 0 19 BERYL 46.9 202.1 156 497 +1978 4 17 6 20 RAFAEL 65.1 125.8 92 27 +2001 12 5 6 28 ALBERTO 35.0 198.4 117 634 +1990 3 15 12 18 FLORENCE 57.9 342.4 40 791 +1953 7 19 12 27 DEBBY 14.2 137.0 64 653 +1989 1 16 0 6 PATTY 55.1 255.8 36 396 +1957 5 27 18 21 ISAAC 18.6 297.2 125 541 +1963 9 19 12 15 PATTY 40.8 138.4 28 529 +1964 3 17 18 12 ALBERTO 66.2 244.9 143 778 +1962 4 3 6 17 LESLIE 41.5 81.3 155 187 +1956 6 22 6 20 DEBBY 69.9 4.6 37 638 +1991 6 5 12 16 HELENE 39.6 270.9 101 829 +1996 9 26 6 9 SANDY 46.1 179.6 66 717 +1960 9 13 6 16 SANDY 46.1 125.8 54 330 +1958 4 4 0 15 ERNESTO 64.6 153.9 92 833 +1963 6 23 0 28 RAFAEL 40.8 211.9 143 746 +1961 6 15 18 21 PATTY 34.1 171.3 21 249 +1983 7 17 0 26 WILLIAM 63.3 274.0 113 333 +1964 7 7 12 13 SANDY 14.6 124.6 60 111 +1987 1 12 12 26 BERYL 10.8 123.6 163 424 +2001 2 22 18 5 SANDY 18.9 326.3 63 844 +1964 12 9 12 27 TONY 31.5 352.4 82 423 +1991 3 16 0 7 MICHAEL 9.2 289.8 104 440 +1953 7 16 0 22 KIRK 45.7 138.5 116 554 +1954 12 16 6 5 RAFAEL 69.0 173.2 69 671 +1958 6 4 12 20 LESLIE 25.5 226.8 132 597 +1972 4 18 18 12 PATTY 41.9 215.9 162 711 +1979 6 25 6 22 MICHAEL 48.3 351.5 23 6 +1987 8 13 6 22 WILLIAM 30.6 222.0 135 589 +2003 6 25 18 20 ERNESTO 66.8 125.9 149 578 +1959 1 18 18 21 MICHAEL 34.9 22.8 127 211 +1966 1 24 18 28 DEBBY 52.2 204.6 83 575 +1996 5 3 6 4 KIRK 50.3 59.9 31 495 +1978 10 25 12 4 TONY 49.4 194.5 14 361 +1954 4 21 6 5 ISAAC 47.0 173.3 52 754 +1974 6 7 0 3 VALERIE 26.8 173.5 31 590 +2004 8 19 18 17 FLORENCE 20.3 298.0 103 624 +1999 3 18 18 2 PATTY 18.1 30.9 130 295 +1957 4 10 6 19 ERNESTO 16.2 357.1 139 334 +1992 1 24 12 23 ERNESTO 58.9 229.9 111 33 +1982 7 9 18 7 RAFAEL 55.0 96.2 41 569 +1998 5 26 0 2 JOYCE 9.0 141.7 132 27 +1968 10 18 6 22 DEBBY 52.7 154.4 141 179 +1997 7 28 0 23 RAFAEL 36.5 187.7 15 523 +1961 11 15 0 8 LESLIE 27.9 35.9 108 630 +1967 2 19 12 21 PATTY 11.8 72.5 34 754 +1954 9 23 18 7 HELENE 52.1 300.0 14 249 +1991 5 23 18 13 SANDY 31.4 41.6 139 255 +2004 7 10 12 28 VALERIE 47.6 160.0 50 810 +1979 8 24 18 5 LESLIE 9.3 101.7 19 286 +1964 3 25 18 11 FLORENCE 66.4 46.1 73 223 +1988 11 26 12 2 ISAAC 62.1 193.6 116 182 +1985 10 9 12 25 OSCAR 17.3 19.3 96 574 +2001 10 15 12 9 GORDON 48.5 343.9 108 404 +1962 1 4 12 5 RAFAEL 10.5 289.0 128 326 +1972 7 3 0 28 ALBERTO 43.1 188.2 102 478 +1967 5 9 6 20 RAFAEL 32.1 321.3 41 833 +1996 6 15 18 10 HELENE 50.5 255.8 104 58 +1991 6 16 12 7 VALERIE 27.6 324.1 99 385 +1962 5 22 18 14 LESLIE 58.7 307.0 67 865 +1982 12 25 12 24 PATTY 45.4 106.5 161 55 +1977 7 16 0 24 OSCAR 46.6 65.7 29 890 +1987 3 2 6 22 CHRIS 41.8 348.1 96 513 +2001 4 14 12 20 ISAAC 14.8 209.1 31 165 +1967 3 19 18 5 JOYCE 38.7 133.9 94 290 +1954 6 16 0 16 HELENE 39.9 73.5 145 272 +1983 9 22 18 1 ISAAC 28.0 321.5 162 892 +1991 9 2 0 16 DEBBY 34.7 223.6 80 864 +1960 12 10 6 15 FLORENCE 11.8 88.9 44 581 +1965 5 20 18 24 ISAAC 70.0 205.7 133 256 +1978 1 10 12 23 VALERIE 19.5 88.6 26 325 +1970 5 2 6 23 ERNESTO 51.3 26.6 79 349 +1954 6 20 0 15 BERYL 52.6 174.0 36 236 +1990 5 22 0 17 RAFAEL 21.2 148.5 123 410 +1951 8 10 12 26 LESLIE 10.6 236.2 87 719 +1953 6 19 12 1 JOYCE 13.9 130.7 73 800 +1971 11 5 0 6 NADINE 11.1 281.7 117 282 +1965 3 11 18 10 ERNESTO 28.4 310.7 97 108 +1979 8 27 0 4 PATTY 35.7 6.2 79 743 +1970 6 9 0 10 HELENE 39.7 11.1 123 511 +1967 9 18 6 10 BERYL 9.4 312.4 135 379 +1988 3 23 6 16 ISAAC 51.6 245.3 163 688 +1961 11 8 0 16 VALERIE 58.1 168.4 59 651 +1989 7 26 12 15 LESLIE 29.6 81.5 150 41 +2002 11 4 6 19 LESLIE 66.6 184.3 117 632 +1985 2 5 6 6 KIRK 64.2 239.2 158 157 +2003 5 15 12 1 TONY 15.5 202.3 18 40 +2000 5 6 6 26 SANDY 14.2 202.9 105 181 +1995 6 6 12 7 TONY 40.1 143.7 20 127 +1967 1 11 6 3 CHRIS 61.3 244.7 112 419 +1966 3 7 12 21 SANDY 37.1 344.4 93 482 +1958 5 18 12 19 HELENE 10.2 345.0 29 473 +1984 8 9 18 3 JOYCE 12.0 270.4 132 148 +2000 10 11 0 19 OSCAR 57.9 9.8 133 605 +1997 3 22 6 15 RAFAEL 62.0 186.5 129 552 +2003 10 17 0 23 KIRK 53.2 147.1 156 557 +1954 10 16 0 18 ISAAC 9.1 221.4 24 11 +1990 3 7 0 22 LESLIE 10.9 133.6 144 581 +1962 6 25 6 8 WILLIAM 23.5 129.4 34 700 +1970 4 13 12 7 HELENE 46.0 319.2 107 512 +1995 9 26 0 13 LESLIE 42.2 331.3 153 514 +1986 11 4 18 25 NADINE 32.7 148.3 56 678 +2003 5 7 18 17 VALERIE 14.4 242.4 49 366 +1958 11 13 6 21 ALBERTO 69.7 354.9 56 798 +1982 4 21 0 4 CHRIS 37.0 118.2 59 104 +1988 4 10 0 4 GORDON 41.9 134.7 76 552 +1997 4 9 0 8 SANDY 50.5 195.8 123 651 +1984 11 4 12 16 VALERIE 28.5 127.7 102 217 +1954 5 8 6 12 ALBERTO 23.9 172.2 93 297 +1955 8 5 12 3 DEBBY 22.7 251.3 92 238 +1956 5 8 0 4 JOYCE 16.4 146.7 150 593 +1982 4 19 0 11 TONY 67.0 12.7 155 812 +1998 4 9 6 12 NADINE 51.4 40.3 22 285 +1987 4 2 12 16 BERYL 45.0 240.1 125 456 +1970 8 6 18 18 BERYL 68.1 271.6 94 114 +1985 2 5 6 9 PATTY 23.0 203.7 67 88 +1965 7 23 6 9 LESLIE 51.9 325.1 45 489 +1955 4 10 6 28 TONY 17.1 79.2 82 679 +1978 6 17 0 22 KIRK 47.3 41.0 126 897 +1989 4 7 12 23 LESLIE 28.6 44.3 76 851 +1989 7 10 12 12 BERYL 12.7 38.5 92 417 +1986 8 18 12 3 HELENE 37.4 204.3 27 821 +1962 12 19 0 13 NADINE 28.1 1.7 39 570 +1982 4 13 0 26 KIRK 55.1 228.7 120 476 +1981 6 3 6 4 LESLIE 35.4 67.2 162 773 +1960 7 1 18 27 CHRIS 26.6 89.5 52 819 +1993 10 10 12 1 NADINE 7.6 57.3 59 650 +1955 7 26 0 11 BERYL 50.6 229.2 112 716 +1959 8 11 6 18 JOYCE 10.7 338.2 160 427 +2003 2 3 0 15 FLORENCE 30.9 124.5 159 526 +1951 11 1 0 21 DEBBY 50.4 50.0 132 19 +2002 7 1 18 5 PATTY 30.7 116.6 146 898 +1976 8 4 12 23 OSCAR 52.0 1.3 37 349 +1968 3 10 6 18 ISAAC 67.7 229.8 29 1 +1974 8 14 18 20 GORDON 44.7 311.9 83 551 +2001 4 18 12 8 CHRIS 60.6 311.9 39 803 +1994 12 26 6 12 DEBBY 25.8 43.8 57 852 +2000 5 22 12 18 VALERIE 67.6 349.1 23 478 +1973 8 14 18 21 ERNESTO 49.7 184.9 135 347 +1988 8 23 12 19 ISAAC 13.7 52.0 111 37 +1969 9 23 12 28 VALERIE 69.3 201.2 92 669 +1960 12 10 12 28 GORDON 34.6 115.6 75 247 +1993 10 8 0 26 MICHAEL 20.9 26.7 67 518 +1983 1 16 12 27 CHRIS 53.9 318.3 13 223 +1985 10 8 18 14 VALERIE 29.8 192.8 160 437 +1996 3 26 18 14 RAFAEL 27.4 118.1 148 502 +1976 6 12 6 2 WILLIAM 64.5 35.4 57 252 +1956 3 10 12 26 JOYCE 13.4 22.2 98 269 +1998 10 21 6 23 ERNESTO 61.2 77.9 132 288 +1965 9 1 0 20 ERNESTO 34.5 200.0 57 675 +1986 3 6 18 16 NADINE 33.8 251.2 102 345 +2004 10 21 12 25 TONY 25.3 178.0 80 135 +1991 10 14 6 15 WILLIAM 36.3 255.9 109 218 +1972 2 7 12 23 ERNESTO 25.5 45.9 37 393 +1960 10 16 18 25 SANDY 34.6 290.4 123 140 +1959 3 23 18 5 MICHAEL 16.6 349.6 18 57 +1994 10 7 0 2 RAFAEL 64.3 135.8 163 803 +1959 4 12 18 28 ISAAC 62.6 326.9 95 258 +1981 9 2 18 17 VALERIE 29.6 93.6 55 102 +1973 9 11 0 6 RAFAEL 32.1 167.4 103 168 +1983 1 1 0 27 JOYCE 44.8 113.0 29 699 +1989 7 11 0 15 NADINE 28.9 244.0 57 399 +1982 3 6 6 18 KIRK 22.3 290.1 69 892 +1952 11 11 0 11 ERNESTO 61.3 104.6 164 112 +1970 2 8 6 7 ISAAC 39.3 289.2 18 174 +1962 1 22 12 14 GORDON 68.3 350.1 144 502 +1953 10 17 18 8 NADINE 58.4 10.4 50 98 +1980 2 16 18 15 RAFAEL 25.9 6.7 141 203 +1960 7 22 0 12 ALBERTO 20.7 49.0 10 104 +1960 9 8 12 28 FLORENCE 49.9 237.7 108 375 +1975 6 6 18 17 JOYCE 31.6 230.0 139 711 +1996 3 21 6 18 ISAAC 52.2 208.8 11 807 +1951 2 10 12 10 WILLIAM 55.6 175.1 156 407 +1986 10 16 0 22 OSCAR 27.2 239.9 50 331 +1992 5 3 0 6 MICHAEL 21.5 193.1 161 234 +1953 2 26 6 21 OSCAR 61.9 172.5 86 461 +1973 2 4 18 2 JOYCE 56.7 107.5 163 182 +1952 6 1 12 26 ERNESTO 66.6 118.5 85 898 +1997 5 16 6 16 ISAAC 65.3 208.8 151 572 +1967 4 26 0 13 PATTY 26.3 172.3 14 21 +1988 10 2 12 8 MICHAEL 21.1 168.8 84 481 +1957 12 16 18 10 VALERIE 48.1 29.6 36 116 +2003 4 26 0 4 VALERIE 53.0 10.6 113 109 +1997 10 18 12 14 WILLIAM 10.6 222.5 73 403 +1962 6 24 12 15 ISAAC 38.3 353.4 69 450 +1988 9 26 18 7 KIRK 63.2 343.3 161 417 +1965 9 20 18 19 TONY 42.3 241.6 84 481 +1952 10 13 18 13 MICHAEL 19.3 286.1 117 217 +1983 3 8 0 25 ISAAC 16.2 288.0 72 338 +1999 7 16 6 16 SANDY 68.5 55.8 153 296 +2004 6 6 18 20 HELENE 23.0 234.8 62 481 +1988 2 7 0 10 PATTY 57.4 109.5 78 165 +1968 12 18 0 6 RAFAEL 37.2 281.1 92 781 +1991 7 14 0 11 PATTY 39.9 48.4 126 539 +1972 6 8 0 12 FLORENCE 10.0 224.6 160 312 +2002 12 19 0 10 ERNESTO 39.1 29.2 11 45 +1954 4 13 6 4 TONY 42.6 49.4 29 878 +1993 5 15 12 19 KIRK 66.9 183.7 84 638 +1996 12 28 0 15 ALBERTO 67.4 87.1 124 294 +1998 9 21 18 1 OSCAR 58.8 111.7 77 505 +1966 12 8 12 13 PATTY 22.8 216.5 69 506 +1971 11 13 18 13 OSCAR 43.1 89.1 59 543 +1998 6 7 0 26 KIRK 66.4 21.5 44 407 +1950 3 17 12 10 JOYCE 27.1 174.5 158 532 +1975 12 5 18 18 WILLIAM 60.5 281.8 133 626 +1950 10 22 0 19 SANDY 55.7 127.4 116 758 +1957 5 1 6 26 ALBERTO 24.9 206.4 133 313 +1975 3 5 12 23 FLORENCE 55.1 65.9 115 628 +1960 7 25 12 19 GORDON 37.3 125.2 81 188 +1956 4 10 6 25 MICHAEL 35.0 331.0 20 398 +1951 5 22 6 3 OSCAR 64.1 214.3 18 413 +1992 2 18 0 7 PATTY 52.2 277.8 31 42 +1954 9 24 18 12 ALBERTO 48.7 247.1 21 65 +1961 10 13 6 19 KIRK 40.3 262.1 68 256 +1970 10 9 18 8 OSCAR 57.6 141.4 145 892 +1990 5 24 12 28 BERYL 49.5 66.4 147 767 +1966 5 27 18 16 ERNESTO 7.4 291.4 102 483 +1995 10 11 6 18 MICHAEL 34.7 48.8 34 125 +1959 4 27 6 27 DEBBY 50.0 5.9 112 633 +1977 2 27 6 10 ISAAC 8.4 47.4 43 360 +1995 10 10 12 15 RAFAEL 12.4 118.7 135 426 +1951 10 2 0 21 KIRK 60.4 177.8 43 338 +1966 12 20 0 14 OSCAR 32.0 229.1 147 638 +1958 7 2 18 21 SANDY 69.9 273.0 28 436 +1978 12 15 18 19 BERYL 8.0 144.4 85 886 +1999 1 4 18 7 FLORENCE 47.8 347.0 35 41 +1976 2 21 6 1 TONY 9.0 148.4 160 812 +1979 1 21 12 6 WILLIAM 41.2 240.0 99 853 +1970 1 23 0 12 KIRK 31.2 332.8 14 68 +1954 7 28 12 7 VALERIE 10.2 260.6 22 427 +1952 3 24 6 2 LESLIE 17.4 77.8 45 474 +2004 6 23 0 24 BERYL 47.6 236.5 154 704 +1980 8 5 0 11 NADINE 58.0 338.1 14 406 +1984 9 27 6 3 MICHAEL 35.8 41.5 140 414 +2003 7 14 18 3 FLORENCE 18.2 106.9 99 760 +1993 8 9 18 23 GORDON 53.9 106.6 142 96 +1998 5 27 6 15 TONY 27.7 64.6 151 169 +1966 8 2 6 28 MICHAEL 27.6 5.2 113 887 +1988 4 16 6 12 JOYCE 66.3 353.3 50 505 +1963 2 22 6 3 DEBBY 36.0 1.8 73 770 +1976 5 14 18 27 ALBERTO 42.0 248.4 115 405 +1987 4 7 6 27 TONY 65.9 136.1 143 642 +1968 10 25 12 6 VALERIE 40.1 95.0 58 49 +1986 10 23 18 4 ERNESTO 16.9 59.4 92 765 +1967 9 11 18 21 PATTY 44.6 54.5 101 155 +1962 12 23 0 18 ALBERTO 39.2 264.8 24 493 +2001 3 27 0 22 BERYL 11.4 228.0 108 177 +1951 9 17 18 27 MICHAEL 9.3 77.6 23 514 +1993 1 25 12 13 PATTY 63.3 4.2 137 858 +1997 11 27 0 7 ERNESTO 47.1 43.5 18 579 +1954 1 7 6 17 RAFAEL 12.5 50.6 30 612 +1989 4 14 18 26 PATTY 56.3 283.4 163 601 +1962 2 17 6 8 PATTY 31.2 186.9 64 766 +1959 5 28 0 22 MICHAEL 10.1 338.0 99 618 +2002 8 24 12 3 FLORENCE 56.8 348.0 64 28 +1979 10 20 6 13 CHRIS 12.6 138.2 27 369 +2003 5 9 12 14 NADINE 41.6 36.3 98 209 +1951 12 28 0 16 ISAAC 50.8 146.4 84 308 +1957 5 25 12 24 FLORENCE 49.3 43.6 105 497 +1966 3 18 6 19 TONY 29.6 341.0 133 483 +1951 2 2 12 25 VALERIE 16.8 239.5 68 468 +1999 5 13 6 1 VALERIE 34.0 43.3 131 583 +1995 8 17 0 10 FLORENCE 51.8 88.4 160 286 +1961 12 1 18 11 ALBERTO 36.0 108.7 76 642 +1950 9 7 0 21 BERYL 66.5 92.2 34 196 +1972 8 28 12 5 MICHAEL 55.4 109.5 107 525 +1952 2 6 0 15 ERNESTO 17.9 231.9 147 691 +1974 9 28 12 24 TONY 37.8 187.1 157 743 +1953 2 6 0 22 HELENE 46.7 202.8 30 274 +1951 3 16 6 7 LESLIE 52.3 174.6 95 531 +1979 11 7 18 24 PATTY 13.6 348.9 19 6 +1963 11 14 0 27 OSCAR 17.4 41.7 134 477 +1999 7 8 18 19 ISAAC 37.7 355.0 149 232 +1956 2 25 6 14 LESLIE 19.8 103.5 154 501 +1962 8 27 0 6 FLORENCE 39.1 278.1 49 769 +2001 2 12 12 23 HELENE 53.4 12.9 34 212 +2001 12 26 0 4 GORDON 51.1 131.6 137 391 +1982 8 8 12 2 BERYL 47.4 349.2 95 870 +1951 12 6 12 20 DEBBY 35.3 170.7 12 407 +1973 10 5 18 21 NADINE 31.0 355.5 114 490 +1995 6 17 12 8 MICHAEL 45.6 102.1 35 335 +1992 1 12 12 21 RAFAEL 56.7 51.0 45 196 +1975 11 1 12 28 JOYCE 15.6 353.6 41 590 +2004 2 3 12 4 OSCAR 22.1 232.1 151 852 +1958 7 19 18 25 WILLIAM 18.6 49.8 35 76 +1988 4 24 0 21 JOYCE 41.7 343.9 16 752 +1964 12 11 6 21 ERNESTO 11.2 302.9 95 440 +1964 6 10 18 9 KIRK 61.0 274.1 134 512 +1968 1 4 0 25 KIRK 37.6 49.2 73 847 +2000 4 27 0 12 ISAAC 33.9 318.3 132 99 +1958 8 1 18 19 FLORENCE 32.7 170.7 114 382 +1952 10 8 6 8 OSCAR 20.0 173.7 88 456 +1994 6 2 12 25 DEBBY 62.0 58.9 100 626 +1985 2 16 12 1 VALERIE 65.8 342.1 58 80 +1955 5 1 12 8 GORDON 21.5 350.7 92 666 +1954 12 2 6 26 KIRK 52.0 8.5 92 232 +1989 9 24 12 9 VALERIE 9.2 117.4 72 547 +2004 7 11 6 11 KIRK 40.2 220.7 124 669 +1952 8 28 18 18 DEBBY 47.2 198.7 18 22 +1983 5 25 6 28 GORDON 28.1 142.7 107 404 +2002 3 24 18 7 SANDY 8.0 279.8 15 59 +1964 5 11 6 24 ISAAC 13.4 319.2 93 544 +1988 4 11 12 15 ALBERTO 68.3 271.2 121 573 +2001 11 15 6 19 BERYL 60.5 119.6 91 370 +1950 6 25 0 10 NADINE 43.7 304.6 107 857 +1989 10 24 12 3 HELENE 24.8 199.6 15 681 +1990 9 7 18 20 WILLIAM 53.5 60.2 99 363 +1962 1 24 18 11 WILLIAM 24.4 341.8 152 689 +1956 5 9 12 26 BERYL 65.7 292.1 41 748 +1956 11 16 6 12 VALERIE 60.1 172.2 19 41 +1971 12 8 0 3 ISAAC 43.6 15.8 22 149 +1991 9 27 12 11 HELENE 67.3 149.7 51 216 +1975 7 9 12 15 BERYL 19.7 158.7 114 324 +2004 11 19 6 1 GORDON 13.0 20.5 15 700 +1996 8 11 6 13 WILLIAM 51.7 59.1 124 681 +1963 3 25 0 2 TONY 9.9 204.2 30 210 +2001 4 9 12 25 PATTY 31.6 74.8 152 344 +2002 7 18 0 21 NADINE 55.1 100.7 132 247 +1987 3 7 6 2 ALBERTO 56.7 240.9 154 506 +1985 8 11 6 25 OSCAR 50.8 235.8 138 326 +1972 12 13 6 2 GORDON 35.8 336.5 98 677 +1960 5 24 0 9 VALERIE 26.6 182.7 114 426 +1959 1 24 0 7 BERYL 56.1 167.5 162 378 +1996 7 7 6 6 OSCAR 39.1 2.0 88 104 +1977 6 19 12 18 GORDON 65.7 322.0 106 415 +1984 8 1 12 7 JOYCE 25.4 97.0 130 742 +1976 3 6 18 24 KIRK 47.5 112.0 43 580 +1984 4 17 12 12 WILLIAM 46.1 258.0 13 39 +1964 9 6 0 24 NADINE 46.0 271.5 55 886 +1958 2 27 18 11 LESLIE 23.9 136.5 71 783 +2004 1 12 12 11 GORDON 52.1 158.8 107 822 +1954 12 25 12 28 PATTY 48.4 83.5 138 809 +1972 2 27 0 22 KIRK 57.9 295.0 55 127 +1964 2 2 0 24 LESLIE 24.8 318.6 111 689 +1988 7 1 18 15 NADINE 56.5 24.2 18 633 +1974 11 28 6 14 BERYL 31.5 86.2 115 568 +1978 10 28 12 16 GORDON 49.6 263.8 131 25 +1951 9 16 18 28 CHRIS 25.9 215.3 111 162 +1970 3 6 0 1 SANDY 44.4 303.4 144 293 +1974 7 6 18 15 NADINE 63.6 249.5 77 640 +1964 7 17 18 3 TONY 7.4 151.4 64 571 +1992 8 12 6 28 HELENE 29.2 61.1 66 879 +1983 7 10 0 2 BERYL 69.5 310.5 44 682 +2004 9 18 6 12 RAFAEL 64.1 63.9 74 406 +1958 10 2 18 21 MICHAEL 37.8 13.4 115 19 +1956 2 23 6 3 WILLIAM 19.8 111.9 43 544 +1958 10 23 0 26 KIRK 62.1 323.3 117 528 +1967 9 1 6 9 NADINE 62.9 105.0 49 132 +1970 4 26 6 17 DEBBY 69.4 264.5 155 257 +1988 9 13 6 2 GORDON 65.5 148.8 147 90 +2001 4 9 18 23 TONY 17.4 126.1 129 690 +1956 5 28 18 28 OSCAR 55.0 55.9 49 794 +1976 4 16 6 1 SANDY 16.0 279.0 142 274 +1999 6 21 0 11 PATTY 57.3 145.8 15 599 +1954 10 5 18 19 CHRIS 8.1 305.1 115 309 +1979 2 23 12 1 KIRK 42.5 70.2 120 502 +2002 11 1 0 8 CHRIS 35.8 24.7 54 80 +1968 6 22 12 14 SANDY 62.9 189.6 70 644 +1993 10 8 6 19 ALBERTO 64.1 210.9 148 352 +1983 7 22 18 26 PATTY 48.2 297.8 73 393 +2000 8 21 18 5 VALERIE 39.2 230.9 147 73 +1993 8 17 6 28 ERNESTO 34.8 69.1 151 238 +1990 4 17 0 13 RAFAEL 44.2 43.0 13 123 +1979 7 2 0 21 TONY 43.7 57.5 151 866 +1993 7 7 6 14 KIRK 40.8 113.1 120 253 +1985 7 22 12 20 HELENE 34.5 216.5 69 694 +1973 12 4 12 22 VALERIE 51.7 13.5 91 644 +1963 3 2 0 11 BERYL 65.2 105.9 145 725 +1971 7 19 12 18 NADINE 57.0 221.0 84 145 +1987 11 19 18 13 MICHAEL 50.1 198.7 103 722 +1997 3 8 6 14 LESLIE 51.6 190.0 139 598 +1976 6 3 6 2 LESLIE 62.7 314.9 36 290 +1959 5 11 12 18 OSCAR 21.1 242.6 14 229 +1965 2 24 6 3 LESLIE 27.8 14.8 92 897 +1994 1 11 6 6 ERNESTO 50.8 193.0 116 65 +1986 3 4 18 3 MICHAEL 41.6 253.5 38 310 +1961 3 23 18 9 WILLIAM 33.6 157.5 158 500 +1984 8 17 12 22 OSCAR 41.1 164.4 96 675 +1967 2 18 0 2 VALERIE 21.3 54.3 75 771 +1960 8 11 18 14 LESLIE 9.5 215.9 145 146 +1994 2 8 12 28 FLORENCE 26.9 202.1 163 581 +1957 7 2 0 23 PATTY 31.4 51.9 74 264 +1999 1 17 6 16 DEBBY 7.5 274.8 11 478 +1980 5 15 6 27 HELENE 28.1 48.8 138 706 +2003 9 8 12 18 LESLIE 56.8 238.6 37 575 +1987 2 21 18 9 ALBERTO 17.3 103.8 139 665 +1950 6 26 6 26 RAFAEL 9.4 210.0 14 591 +1989 11 13 12 14 ALBERTO 22.5 72.4 36 416 +1969 10 22 6 1 LESLIE 29.9 210.5 40 247 +2001 2 16 0 25 MICHAEL 30.2 304.3 158 537 +1957 4 8 18 2 BERYL 15.7 309.5 149 653 +1954 9 12 18 17 TONY 8.2 201.7 130 363 +1960 12 14 0 17 BERYL 21.4 111.8 26 335 +1954 2 15 6 10 HELENE 64.5 103.8 75 556 +1960 4 28 12 2 JOYCE 46.8 268.2 138 158 +1974 12 22 18 13 OSCAR 62.0 288.5 26 437 +2001 2 9 18 4 RAFAEL 42.7 79.6 12 318 +1963 8 24 18 15 HELENE 14.4 62.5 52 584 +1963 5 22 6 22 OSCAR 54.2 143.8 121 701 +1968 9 5 6 7 TONY 23.4 300.2 114 726 +1984 8 3 12 2 VALERIE 48.8 327.6 148 242 +1988 7 8 12 17 ISAAC 57.4 161.4 128 390 +1963 9 6 6 15 RAFAEL 66.5 31.5 64 501 +1960 3 24 18 12 OSCAR 49.7 95.8 129 41 +1974 1 23 18 12 NADINE 26.6 184.7 28 10 +1964 1 28 12 19 JOYCE 49.5 273.2 49 172 +1959 9 25 12 25 ISAAC 16.6 115.0 79 417 +1955 4 14 6 7 VALERIE 21.5 203.3 145 389 +1989 6 6 0 13 BERYL 41.3 294.4 117 396 +1978 1 4 0 11 BERYL 53.6 21.3 97 79 +2004 2 25 0 17 VALERIE 7.7 86.4 86 684 +1979 12 22 12 1 ALBERTO 39.5 279.1 17 867 +2001 8 4 6 19 NADINE 67.5 137.0 73 785 +1966 11 21 18 21 CHRIS 66.6 163.2 16 739 +1966 5 22 0 11 KIRK 65.1 118.1 105 257 +1982 9 10 18 14 GORDON 54.1 139.7 143 836 +1952 1 8 0 10 NADINE 57.1 184.5 108 610 +1971 4 25 6 10 GORDON 44.7 218.1 164 878 +1979 9 12 0 3 CHRIS 19.7 177.3 58 732 +1971 7 1 0 23 PATTY 38.6 18.7 146 228 +1969 6 17 0 17 FLORENCE 57.0 238.9 33 858 +1992 3 2 0 23 HELENE 30.4 193.0 99 612 +1975 2 10 12 6 PATTY 64.6 214.8 50 157 +1950 3 15 12 4 BERYL 8.2 173.3 87 117 +1963 1 8 18 26 JOYCE 48.9 231.1 127 556 +1958 7 25 0 1 HELENE 49.6 47.0 75 695 +1954 9 12 18 22 VALERIE 49.5 135.9 157 224 +1974 5 6 18 13 MICHAEL 66.2 231.9 23 755 +1990 10 23 0 17 TONY 51.1 305.0 55 56 +1960 8 12 6 3 JOYCE 8.5 101.9 81 885 +1975 3 26 18 15 PATTY 12.9 340.8 17 87 +1960 4 28 12 22 CHRIS 43.7 282.6 146 153 +1988 2 21 18 13 TONY 58.5 1.0 60 702 +1979 3 22 12 11 BERYL 23.1 16.7 118 489 +1981 3 9 12 28 ALBERTO 69.4 148.5 83 534 +1972 2 24 12 20 RAFAEL 11.3 168.8 38 871 +1982 10 21 18 15 BERYL 13.4 170.8 57 369 +1982 3 20 18 26 ALBERTO 41.2 82.9 37 431 +1974 2 19 0 20 CHRIS 18.8 256.2 43 386 +1954 3 8 6 8 BERYL 18.1 251.2 51 523 +1980 7 23 12 28 LESLIE 21.8 58.4 123 620 +1956 10 11 12 22 DEBBY 38.1 200.9 73 461 +1964 6 26 0 24 FLORENCE 44.1 63.0 32 802 +1992 1 2 0 24 OSCAR 24.3 191.5 47 238 +1995 12 7 6 24 ERNESTO 29.9 25.8 59 380 +1954 1 22 0 14 NADINE 50.9 38.0 147 559 +2001 7 13 0 26 DEBBY 43.9 305.1 98 58 +1996 12 9 18 8 ERNESTO 21.1 80.6 131 491 +1966 12 2 18 12 WILLIAM 35.2 225.8 83 599 +1963 11 24 12 16 VALERIE 49.7 186.6 124 35 +1979 12 12 0 12 ISAAC 36.9 19.3 114 627 +1996 10 23 6 13 PATTY 31.5 127.5 126 158 +1966 4 8 6 9 FLORENCE 30.0 139.1 99 505 +1983 8 13 0 9 NADINE 56.5 75.6 56 865 +2002 3 18 12 27 SANDY 41.1 266.6 60 450 +1951 2 21 18 19 CHRIS 22.9 110.8 146 194 +1999 6 15 6 7 SANDY 10.8 16.3 52 344 +1993 4 4 6 28 MICHAEL 52.2 141.1 157 683 +1985 10 22 6 23 FLORENCE 47.9 219.7 90 584 +2002 4 18 0 24 MICHAEL 39.2 319.3 72 294 +1951 7 16 0 26 SANDY 7.7 137.7 65 771 +1993 7 6 12 5 ALBERTO 26.3 322.9 26 299 +1950 5 22 12 12 NADINE 41.7 240.1 60 204 +1982 6 5 6 27 ALBERTO 19.6 102.2 103 345 +1995 11 9 0 18 TONY 13.8 171.1 29 719 +1985 9 22 0 1 ALBERTO 40.5 208.0 55 895 +1955 8 19 18 14 FLORENCE 60.8 227.3 123 666 +1999 5 20 18 6 BERYL 26.9 350.8 93 806 +2002 11 20 6 20 LESLIE 29.2 179.6 130 310 +2003 7 7 12 15 FLORENCE 23.6 211.6 43 328 +1986 1 23 0 21 BERYL 52.1 239.2 113 550 +1971 8 25 6 19 ISAAC 8.8 66.1 103 346 +1959 8 2 18 12 MICHAEL 51.3 340.0 137 856 +1969 8 25 12 10 ISAAC 22.6 119.0 131 499 +1972 10 16 18 8 HELENE 53.3 318.6 51 195 +1990 11 5 6 13 SANDY 69.2 234.9 61 346 +2003 12 8 12 17 ISAAC 56.8 303.3 83 422 +1989 10 7 6 9 ALBERTO 48.7 259.8 159 564 +1968 6 4 12 28 TONY 39.0 114.7 66 245 +1976 4 10 6 9 SANDY 41.9 106.0 54 870 +1985 8 14 12 13 SANDY 9.4 288.7 117 446 +2001 8 19 18 20 HELENE 57.4 117.7 46 627 +1984 10 2 0 23 DEBBY 50.3 13.2 121 163 +1951 6 6 18 11 PATTY 66.9 178.1 30 103 +1967 6 16 12 24 OSCAR 47.5 308.5 34 516 +1991 12 10 12 4 HELENE 68.9 257.5 156 712 +1972 4 10 18 15 PATTY 67.9 352.1 160 439 +2003 3 1 6 2 MICHAEL 53.5 304.8 85 463 +1962 1 16 6 20 RAFAEL 37.5 263.5 104 667 +1976 2 10 6 4 DEBBY 20.5 245.7 16 564 +1987 9 13 6 20 ERNESTO 8.6 71.6 97 134 +2001 10 26 12 4 GORDON 67.7 303.3 77 864 +1962 2 3 18 22 MICHAEL 51.1 243.1 163 469 +1974 10 21 0 14 KIRK 22.6 194.0 127 80 +1997 12 10 6 7 TONY 49.7 284.7 151 121 +1991 9 13 12 20 ISAAC 37.8 1.6 89 266 +2000 1 13 0 1 DEBBY 43.8 70.5 84 758 +1961 1 21 0 16 LESLIE 51.2 111.8 42 516 +1993 2 2 12 1 CHRIS 43.5 20.8 57 206 +1977 12 16 18 18 ERNESTO 51.8 174.6 160 685 +1968 7 22 6 25 PATTY 19.9 70.9 96 128 +1961 9 24 12 14 OSCAR 18.9 166.4 136 151 +1969 5 1 0 7 HELENE 50.1 297.9 153 727 +1987 1 26 18 16 JOYCE 8.6 181.2 36 655 +1997 4 8 0 20 TONY 12.2 44.4 70 613 +1967 5 28 18 21 LESLIE 61.3 158.0 67 69 +1992 11 10 12 19 CHRIS 30.5 52.9 42 341 +1992 4 28 6 15 MICHAEL 59.6 356.6 90 506 +1987 1 2 6 1 FLORENCE 55.3 254.3 161 764 +1961 10 9 6 11 ALBERTO 45.4 289.1 34 585 +1958 4 4 12 25 NADINE 24.8 177.3 34 506 +1996 5 4 6 9 DEBBY 22.6 335.6 60 123 +1988 11 4 12 13 JOYCE 45.1 204.3 38 125 +2003 9 25 6 15 NADINE 42.9 145.2 115 465 +1985 4 1 18 6 BERYL 60.2 245.7 149 839 +1981 2 13 18 13 OSCAR 35.3 303.7 39 821 +1986 10 15 0 1 SANDY 38.0 86.3 129 897 +1965 10 10 6 20 ISAAC 15.3 213.1 104 569 +1981 7 7 18 28 LESLIE 45.9 353.3 69 22 +1988 12 6 18 6 GORDON 31.5 79.0 54 743 +1966 3 22 18 16 JOYCE 19.8 237.8 74 108 +1962 3 14 0 14 WILLIAM 45.3 342.2 146 455 +1982 10 19 18 25 OSCAR 36.4 99.8 146 308 +1966 10 16 0 25 LESLIE 57.9 346.5 109 57 +2002 9 19 12 12 GORDON 30.5 314.9 57 748 +1958 8 11 6 20 FLORENCE 62.1 215.3 30 441 +1951 7 12 12 25 RAFAEL 59.8 218.2 130 46 +1998 1 17 12 9 KIRK 17.5 28.8 70 300 +1994 7 23 6 28 ALBERTO 54.0 13.9 162 295 +1972 1 17 12 24 BERYL 15.7 247.7 74 648 +1990 2 5 12 15 FLORENCE 16.3 185.5 109 643 +1985 3 22 6 9 JOYCE 49.7 138.7 11 529 +1996 4 6 18 13 CHRIS 29.2 252.0 143 763 +1981 10 6 18 23 JOYCE 52.8 322.2 51 864 +1972 10 10 18 18 CHRIS 44.6 9.9 63 679 +1979 4 10 12 3 TONY 13.0 310.5 35 612 +1983 1 4 0 4 BERYL 13.2 109.0 61 2 +2002 4 28 6 10 LESLIE 46.2 148.3 130 584 +1996 11 19 0 6 BERYL 26.0 118.6 69 115 +1973 8 13 6 10 GORDON 49.3 231.3 71 692 +1955 3 27 6 13 KIRK 56.4 62.1 112 283 +1957 8 14 0 24 RAFAEL 65.3 7.1 77 165 +1984 5 13 12 16 JOYCE 18.3 303.1 78 83 +1987 5 19 12 1 KIRK 56.0 228.8 22 624 +1979 12 24 12 28 FLORENCE 30.7 350.1 109 19 +1975 11 9 6 27 MICHAEL 54.0 198.0 20 531 +1999 7 24 0 10 HELENE 54.2 334.7 118 405 +1953 3 16 18 27 TONY 11.2 233.7 159 704 +1994 10 19 6 28 ISAAC 30.9 317.5 140 550 +1980 8 15 0 11 MICHAEL 7.1 96.4 41 80 +1991 9 17 12 28 LESLIE 13.2 325.8 126 189 +1964 7 5 6 6 JOYCE 39.1 190.7 93 4 +1990 6 23 0 8 WILLIAM 14.9 178.5 33 19 +1980 10 21 12 23 OSCAR 37.2 94.7 141 517 +1961 7 21 0 8 TONY 67.6 223.5 53 420 +1968 2 25 18 10 ALBERTO 16.5 41.4 11 377 +2002 9 20 0 17 GORDON 37.0 232.7 101 387 +1984 9 9 12 20 LESLIE 40.2 109.7 129 719 +1974 6 6 0 16 RAFAEL 63.6 57.8 15 167 +1964 7 26 0 16 LESLIE 46.3 134.3 22 164 +1966 1 20 6 27 WILLIAM 54.2 254.7 60 258 +2002 5 19 18 14 MICHAEL 14.1 316.4 35 444 +1976 5 13 6 5 HELENE 67.5 306.0 95 410 +1986 11 2 0 13 BERYL 39.4 20.4 26 146 +1955 7 24 18 27 OSCAR 33.4 82.5 38 100 +1962 10 13 12 10 VALERIE 14.9 118.3 109 844 +1983 5 1 6 13 LESLIE 37.5 203.5 117 341 +1961 6 17 18 21 HELENE 24.4 209.9 104 430 +1951 2 10 12 19 CHRIS 21.0 130.2 11 160 +1968 9 28 12 11 GORDON 30.1 96.0 122 315 +1966 12 23 12 16 WILLIAM 63.0 272.4 109 742 +1995 2 18 6 25 WILLIAM 35.3 279.7 80 116 +1958 5 10 6 9 HELENE 21.4 28.9 104 812 +1966 12 6 6 18 OSCAR 45.6 338.8 119 462 +1958 5 22 18 6 DEBBY 29.0 335.1 85 251 +1958 2 21 6 20 ISAAC 29.6 233.9 43 380 +1991 9 15 12 9 MICHAEL 51.3 279.2 153 811 +1962 8 4 0 4 JOYCE 33.1 147.3 66 852 +1981 12 13 12 15 BERYL 51.5 115.5 50 317 +1971 11 19 18 25 PATTY 23.1 54.6 86 718 +1970 2 15 12 14 KIRK 48.5 296.4 86 10 +1956 6 14 0 11 HELENE 40.4 136.1 27 260 +1969 9 11 6 14 MICHAEL 36.7 340.8 72 781 +2003 11 27 12 13 OSCAR 56.1 154.9 88 244 +1994 9 9 18 17 HELENE 45.0 19.5 68 688 +1970 11 12 12 25 KIRK 27.8 12.2 110 58 +1978 9 27 6 15 BERYL 53.7 68.3 128 98 +1957 2 21 18 28 CHRIS 47.0 102.6 55 258 +1989 3 13 0 24 OSCAR 28.7 165.2 136 771 +1997 9 13 0 23 WILLIAM 27.6 208.2 77 721 +1992 1 11 6 16 SANDY 12.4 290.1 19 674 +1996 8 13 6 5 JOYCE 62.8 265.4 51 737 +1954 5 4 6 23 VALERIE 47.4 185.4 88 860 +1985 6 18 18 22 SANDY 45.3 251.4 17 237 +1995 9 20 0 22 NADINE 20.5 45.8 51 68 +2004 4 26 12 8 GORDON 57.3 88.0 73 830 +1992 10 9 18 28 ALBERTO 10.4 13.0 156 20 +1995 6 25 18 15 DEBBY 43.8 63.9 142 151 +1996 9 24 18 13 FLORENCE 55.3 191.0 159 272 +1955 10 8 0 18 OSCAR 55.2 348.4 42 618 +1975 1 2 6 5 CHRIS 8.9 348.9 141 124 +1965 5 22 0 19 HELENE 59.1 65.1 91 456 +1959 1 19 12 14 HELENE 42.7 132.7 29 889 +1960 5 25 6 4 TONY 11.1 250.5 116 538 +2004 7 14 0 27 GORDON 31.9 151.2 150 862 +1981 12 26 18 18 VALERIE 42.7 259.5 75 149 +1955 11 4 0 18 GORDON 10.7 196.6 80 830 +1983 11 4 0 21 LESLIE 9.0 67.2 56 251 +1987 7 23 18 27 BERYL 22.6 190.0 125 769 +2004 5 4 12 4 PATTY 67.3 221.7 138 280 +1981 11 28 18 24 SANDY 53.9 93.2 11 189 +1992 2 9 18 22 PATTY 65.1 145.0 125 898 +1952 11 22 6 3 VALERIE 22.7 81.4 60 418 +1950 3 8 0 16 KIRK 24.9 67.3 52 102 +1950 7 22 18 8 ALBERTO 50.9 284.0 75 39 +1962 5 25 0 9 DEBBY 44.2 10.1 18 285 +1965 9 4 18 15 OSCAR 46.5 221.5 155 770 +1978 1 12 6 1 TONY 51.5 304.9 61 482 +1971 8 17 18 26 FLORENCE 46.3 205.4 21 194 +1973 8 10 6 22 PATTY 64.7 210.1 41 152 +1975 1 21 18 22 OSCAR 48.0 314.0 88 597 +1950 3 9 0 28 ERNESTO 24.4 105.6 71 122 +1993 2 8 18 9 JOYCE 28.8 183.0 130 347 +1962 6 14 0 4 BERYL 63.3 325.8 58 140 +1958 12 18 0 8 VALERIE 68.8 259.9 115 223 +1991 1 9 18 20 HELENE 30.0 14.1 86 773 +1966 7 27 0 16 VALERIE 11.5 328.0 62 869 +1998 7 8 0 5 NADINE 38.0 256.4 35 40 +1964 7 25 12 19 LESLIE 32.6 72.3 111 214 +1991 7 26 18 13 VALERIE 16.3 294.2 122 662 +1996 5 24 6 21 SANDY 68.2 100.7 116 710 +1999 8 24 0 10 ERNESTO 63.8 283.5 45 384 +1979 12 2 12 16 BERYL 64.9 40.2 134 387 +1979 12 13 18 18 SANDY 65.2 157.7 35 228 +2002 11 4 6 22 RAFAEL 29.2 186.4 121 751 +1951 10 5 18 22 ALBERTO 17.9 339.6 74 318 +2000 1 22 0 10 VALERIE 12.0 299.8 60 220 +1997 7 7 6 17 ERNESTO 7.0 27.5 161 460 +1984 7 4 0 25 TONY 30.3 180.8 71 623 +1969 12 27 0 8 OSCAR 36.2 222.8 52 333 +1988 6 27 18 3 ERNESTO 39.9 206.4 22 180 +1994 4 22 18 16 DEBBY 67.4 334.4 107 89 +1961 5 6 18 8 GORDON 44.4 4.5 141 46 +1996 7 27 0 10 ISAAC 8.1 338.8 26 125 +1950 8 22 18 4 ALBERTO 49.4 209.7 130 28 +1974 10 17 6 28 PATTY 10.0 201.1 147 491 +1971 12 18 12 1 BERYL 36.7 148.5 64 866 +1951 11 5 18 5 FLORENCE 63.6 128.4 37 577 +1983 2 5 0 16 CHRIS 16.1 310.6 128 738 +1976 2 9 12 3 LESLIE 10.3 341.2 119 299 +1985 7 14 18 18 ERNESTO 10.3 341.9 53 596 +1978 8 24 6 4 ISAAC 40.8 331.5 160 577 +1981 2 25 18 14 TONY 51.3 295.2 33 570 +1984 2 7 0 2 GORDON 34.2 339.7 20 401 +1981 9 1 0 25 OSCAR 61.6 280.4 119 255 +1972 12 6 12 4 SANDY 38.3 157.3 18 560 +1973 12 17 18 24 ALBERTO 59.9 137.9 100 625 +1956 12 15 18 10 CHRIS 47.5 317.1 156 876 +1995 1 7 0 28 HELENE 11.7 233.8 70 808 +1991 9 18 12 1 HELENE 43.8 32.8 22 51 +1992 7 14 6 18 PATTY 58.3 107.7 33 761 +1973 3 7 12 15 JOYCE 19.5 126.3 104 494 +1978 6 8 6 24 WILLIAM 16.4 297.3 96 498 +1978 6 5 18 18 SANDY 68.4 255.0 59 730 +1965 3 2 12 7 PATTY 27.2 70.6 111 315 +1961 7 8 18 20 KIRK 36.2 75.5 145 754 +1980 2 13 18 5 ISAAC 68.5 328.7 66 133 +1986 12 15 6 12 FLORENCE 14.8 37.9 122 483 +1971 11 17 0 21 MICHAEL 69.3 7.5 66 183 +1976 5 16 0 16 WILLIAM 23.1 144.7 74 29 +1997 2 7 0 2 CHRIS 49.5 311.0 76 742 +1984 3 6 0 17 DEBBY 46.1 140.0 83 280 +1974 5 21 18 9 BERYL 20.0 0.4 93 531 +1972 6 28 0 14 MICHAEL 44.1 289.7 109 197 +1976 3 28 6 22 JOYCE 41.6 340.2 115 154 +1976 4 28 6 7 SANDY 44.4 313.1 42 330 +1972 4 10 6 4 BERYL 35.1 334.7 79 572 +1961 12 8 12 13 RAFAEL 15.5 338.9 68 474 +1971 9 16 6 1 ISAAC 13.1 313.4 21 791 +1974 4 24 18 18 GORDON 50.5 135.4 98 640 +1999 4 12 0 3 OSCAR 48.7 324.0 70 188 +1972 3 1 6 12 FLORENCE 8.8 26.9 51 578 +1950 2 12 18 8 ISAAC 10.3 272.5 64 485 +1980 2 16 0 20 NADINE 25.7 246.8 145 751 +1984 2 4 12 13 MICHAEL 36.7 347.7 163 10 +1964 11 22 6 13 ALBERTO 63.7 200.7 154 181 +1972 11 22 18 23 ERNESTO 17.3 186.2 63 277 +1953 3 26 12 26 ISAAC 57.0 30.7 115 54 +1973 8 8 6 1 ISAAC 43.9 296.0 146 369 +1968 2 6 18 8 DEBBY 59.6 119.0 41 166 +1985 7 19 18 10 FLORENCE 35.8 294.8 71 814 +1977 8 22 18 27 PATTY 66.5 329.9 156 789 +1951 5 17 6 26 DEBBY 43.8 195.0 29 49 +2002 7 14 0 3 ERNESTO 51.8 85.1 114 647 +1957 10 9 6 7 ERNESTO 64.0 154.1 95 33 +1967 12 4 0 22 OSCAR 66.6 254.0 144 152 +1958 10 12 6 26 GORDON 46.4 78.3 75 228 +1976 2 24 12 8 FLORENCE 26.6 41.6 96 362 +1962 5 10 12 3 JOYCE 8.9 26.1 65 797 +1976 1 3 0 10 CHRIS 52.9 98.9 66 581 +1996 9 2 18 4 ALBERTO 64.0 271.6 143 679 +1954 12 23 18 25 DEBBY 10.8 99.1 71 742 +1958 4 6 12 11 RAFAEL 9.6 75.1 17 196 +1983 11 16 12 10 GORDON 34.0 53.0 162 207 +1965 12 6 12 3 TONY 39.0 19.0 85 793 +1973 12 19 6 1 JOYCE 20.2 251.0 85 297 +1995 5 5 12 21 WILLIAM 8.3 216.4 125 644 +1952 5 27 12 3 ISAAC 56.8 357.3 43 21 +2003 9 19 18 22 FLORENCE 46.4 96.7 89 290 +1996 2 8 12 9 ALBERTO 23.3 39.4 70 357 +1982 5 28 18 3 PATTY 20.4 231.5 106 396 +1991 2 10 18 27 FLORENCE 26.8 133.2 153 109 +1965 11 5 6 11 DEBBY 48.1 50.4 113 576 +1997 10 22 0 5 GORDON 10.6 283.0 104 146 +1951 10 10 18 22 HELENE 40.0 80.0 85 666 +1971 5 4 0 12 FLORENCE 14.0 176.5 84 616 +2001 1 7 0 14 VALERIE 29.4 338.6 135 449 +1987 7 2 6 8 DEBBY 19.4 83.4 156 882 +1999 3 11 12 17 DEBBY 13.6 350.5 124 459 +2000 1 3 18 5 LESLIE 32.3 135.9 123 648 +1991 4 23 0 27 OSCAR 7.1 64.3 72 159 +1976 6 25 12 18 SANDY 64.2 292.5 12 522 +1994 9 21 6 27 WILLIAM 23.2 255.6 95 790 +1990 7 3 12 9 DEBBY 59.6 38.1 20 687 +1994 9 9 0 1 CHRIS 67.7 191.9 30 489 +1963 3 1 18 7 VALERIE 18.6 342.0 67 514 +1985 1 3 12 26 ISAAC 58.6 237.7 152 134 +1966 12 27 6 20 RAFAEL 65.4 13.5 39 31 +1980 11 22 6 3 TONY 68.8 19.8 63 170 +1968 4 15 6 2 HELENE 16.2 77.0 90 509 +2001 3 13 6 2 MICHAEL 34.7 304.7 70 70 +1951 2 21 18 25 ERNESTO 56.8 262.7 92 461 +1989 12 9 12 25 SANDY 53.1 35.6 12 318 +1989 12 27 6 6 VALERIE 15.7 165.1 73 789 +1994 2 26 6 18 JOYCE 49.1 195.7 141 161 +1954 3 19 0 23 BERYL 42.4 227.6 96 492 +1974 12 8 12 19 HELENE 53.2 205.8 49 657 +1956 5 15 18 4 ISAAC 65.0 199.4 91 293 +1961 5 1 12 2 MICHAEL 56.2 313.7 53 358 +1977 9 18 18 22 HELENE 67.7 79.0 116 425 +1998 1 8 18 24 VALERIE 24.9 263.0 121 537 +1953 3 20 6 25 VALERIE 8.1 130.6 157 626 +1955 9 15 6 7 VALERIE 42.6 130.5 148 81 +1999 2 9 18 3 FLORENCE 10.4 335.8 62 179 +1963 9 16 0 17 MICHAEL 49.5 266.5 164 573 +1982 9 4 0 27 HELENE 24.9 91.9 52 824 +1968 1 21 6 1 KIRK 22.3 281.8 139 665 +1981 4 18 0 8 ISAAC 41.3 294.8 140 808 +2004 8 25 6 21 MICHAEL 10.8 2.3 110 240 +1964 12 5 18 7 ALBERTO 35.5 325.8 130 371 +1979 6 13 12 14 GORDON 45.3 251.5 61 889 +1978 9 21 12 2 WILLIAM 41.3 179.6 123 161 +1951 1 14 12 19 NADINE 58.7 160.9 164 91 +1985 3 9 6 26 WILLIAM 32.0 97.3 142 652 +2003 1 5 6 12 GORDON 64.6 140.5 120 255 +1974 11 26 0 13 PATTY 46.1 202.8 161 21 +2004 4 10 12 19 DEBBY 67.8 77.9 143 562 +1984 8 5 18 16 NADINE 62.7 115.7 34 895 +1983 9 24 12 25 OSCAR 57.6 223.2 136 153 +1984 9 6 18 8 LESLIE 13.4 20.7 13 229 +1969 9 3 12 13 ERNESTO 60.5 153.0 70 364 +2001 9 9 0 22 DEBBY 14.6 91.8 114 624 +1989 12 27 18 2 TONY 44.5 303.0 93 424 +1953 2 3 18 18 RAFAEL 59.8 325.0 121 176 +1996 4 27 12 11 ISAAC 56.5 44.3 58 703 +1989 1 13 6 25 ALBERTO 56.4 251.1 61 702 +1989 6 9 6 6 MICHAEL 38.5 66.9 82 132 +1979 12 13 0 14 LESLIE 26.9 310.5 133 872 +1993 2 12 6 2 KIRK 15.8 181.1 140 856 +1957 2 3 6 18 JOYCE 42.7 290.2 32 115 +1950 9 14 12 13 BERYL 7.7 261.9 66 448 +1950 3 20 18 24 KIRK 52.3 274.7 91 481 +1973 5 6 6 7 LESLIE 69.9 329.9 45 637 +1971 3 19 12 17 OSCAR 34.6 37.2 96 866 +1991 3 1 6 4 LESLIE 67.8 298.9 63 870 +1976 6 4 6 4 KIRK 13.0 244.7 138 124 +1975 8 6 12 22 OSCAR 23.8 273.1 123 350 +1984 10 10 0 1 JOYCE 20.5 167.3 44 830 +1984 10 9 0 20 LESLIE 39.5 175.7 94 102 +1996 1 16 6 22 LESLIE 40.9 347.1 50 67 +1970 2 9 12 12 GORDON 63.6 104.4 149 3 +1997 12 14 18 10 RAFAEL 18.2 244.1 79 613 +1972 8 28 6 9 LESLIE 27.9 224.0 126 265 +1964 6 25 6 11 RAFAEL 46.6 196.9 104 163 +1985 1 7 12 17 VALERIE 29.5 230.9 105 382 +1992 2 23 12 24 WILLIAM 28.0 3.8 149 627 +1970 2 28 0 19 PATTY 61.8 54.2 82 730 +1960 12 2 18 15 WILLIAM 68.1 231.2 108 62 +1978 8 3 0 11 ALBERTO 10.6 293.3 27 122 +1958 9 27 12 8 ISAAC 27.9 330.2 37 790 +1955 1 25 18 1 ALBERTO 33.6 289.2 42 829 +1980 3 22 12 17 ALBERTO 48.0 188.7 143 737 +1981 7 14 0 13 PATTY 16.1 117.9 107 849 +1999 7 21 18 11 MICHAEL 41.2 171.2 46 389 +1990 11 2 18 2 PATTY 7.1 273.8 11 302 +1998 9 11 18 13 MICHAEL 69.7 150.4 135 682 +1962 5 12 0 24 ISAAC 34.3 4.8 63 77 +1999 12 15 18 18 PATTY 63.1 96.3 29 592 +1976 4 17 12 9 OSCAR 20.2 40.9 87 891 +1971 2 3 6 13 VALERIE 49.1 354.9 19 529 +1961 10 17 0 26 RAFAEL 68.8 81.4 67 11 +1968 3 7 18 23 GORDON 69.1 182.3 18 448 +1988 9 22 12 17 PATTY 13.9 345.1 34 664 +1988 5 20 12 21 CHRIS 13.5 31.4 133 318 +1974 11 3 12 28 VALERIE 57.9 181.5 65 832 +1972 3 25 6 22 MICHAEL 17.0 205.5 115 94 +1991 12 15 6 28 NADINE 60.4 115.3 43 202 +1972 6 8 0 25 ERNESTO 62.8 30.5 111 482 +1985 1 7 18 18 FLORENCE 26.2 234.3 48 415 +1967 5 21 0 19 ALBERTO 46.0 168.5 135 753 +1991 9 28 6 10 BERYL 36.3 296.6 148 300 +1991 1 12 18 12 BERYL 44.8 209.7 134 67 +1965 5 11 18 27 ERNESTO 21.5 317.9 119 714 +1964 1 26 0 27 OSCAR 34.7 124.2 10 695 +1988 5 17 6 8 BERYL 65.3 113.0 155 535 +1963 11 12 6 15 ERNESTO 68.0 26.3 14 739 +1993 12 1 6 20 ISAAC 38.6 277.0 147 641 +1952 5 24 12 23 RAFAEL 35.4 168.3 157 522 +2003 11 14 6 12 ERNESTO 46.6 114.5 91 735 +1996 2 7 0 27 CHRIS 65.4 248.7 141 600 +1950 9 19 12 18 DEBBY 46.4 306.7 52 553 +2001 5 2 18 18 TONY 51.1 336.2 92 846 +1990 9 22 12 26 WILLIAM 45.4 33.0 64 740 +1962 2 7 18 7 TONY 19.2 136.4 115 347 +1962 11 23 6 24 WILLIAM 39.5 6.7 159 631 +1961 8 3 18 17 MICHAEL 17.9 122.7 153 511 +1957 6 5 12 5 ERNESTO 44.2 338.2 81 314 +1990 10 18 0 22 DEBBY 61.6 13.5 124 761 +1984 6 23 12 24 VALERIE 57.7 224.6 137 856 +1984 9 18 0 17 ERNESTO 21.4 183.0 128 526 +2003 11 4 12 10 RAFAEL 43.1 253.9 82 633 +1991 8 18 12 5 OSCAR 35.5 211.5 45 219 +1990 1 14 0 12 MICHAEL 36.8 321.0 80 487 +1956 7 15 18 10 MICHAEL 37.0 113.6 90 375 +1963 12 26 0 12 OSCAR 7.9 140.0 106 382 +1969 1 19 0 27 FLORENCE 30.0 235.5 65 328 +1973 9 20 6 18 LESLIE 62.4 236.6 87 381 +1963 4 9 6 25 CHRIS 30.3 139.3 138 697 +1984 6 26 12 16 KIRK 30.8 110.7 51 270 +1998 12 13 0 2 TONY 11.7 250.9 134 43 +2003 4 10 18 2 LESLIE 14.7 24.4 141 720 +1985 6 14 12 16 ERNESTO 34.0 203.4 132 420 +1987 3 23 12 9 RAFAEL 17.2 131.4 64 826 +1960 12 23 12 17 HELENE 13.2 80.3 161 473 +1951 4 11 12 17 DEBBY 53.6 260.2 71 462 +1991 1 3 0 3 ERNESTO 18.3 204.3 119 272 +1980 5 26 12 8 OSCAR 45.8 66.7 27 412 +1960 1 21 0 22 JOYCE 23.9 144.0 79 241 +2004 11 10 6 19 ALBERTO 56.4 136.0 24 887 +1975 10 15 0 24 KIRK 64.7 55.9 156 320 +1989 8 5 18 8 KIRK 15.9 140.5 67 488 +1966 11 4 6 2 SANDY 15.3 209.7 102 344 +1957 6 11 6 27 GORDON 38.6 101.7 131 510 +1971 6 16 6 24 WILLIAM 30.9 89.1 117 500 +1973 11 17 6 13 VALERIE 19.2 136.2 148 524 +1995 5 7 12 19 FLORENCE 8.8 320.9 45 368 +1973 4 26 18 28 OSCAR 29.7 55.4 70 173 +1967 4 15 18 12 ALBERTO 18.3 271.1 48 279 +1989 7 28 0 7 ALBERTO 32.5 196.1 120 319 +1971 7 28 6 11 ALBERTO 17.8 12.2 135 172 +1963 2 12 18 23 CHRIS 47.6 294.0 38 829 +1977 4 13 12 1 ALBERTO 53.2 147.6 52 87 +1996 2 27 18 27 BERYL 8.5 103.4 101 255 +1964 2 18 6 27 NADINE 12.2 144.2 46 583 +1970 10 5 18 28 DEBBY 23.6 325.3 33 173 +1979 8 10 6 6 FLORENCE 52.9 119.1 27 784 +1988 1 26 18 25 LESLIE 24.9 252.9 20 761 +1996 9 19 0 22 WILLIAM 42.3 26.4 136 632 +1988 8 13 6 14 BERYL 50.3 222.1 124 374 +1990 5 5 6 27 SANDY 42.0 181.2 50 100 +1955 11 22 12 14 BERYL 18.4 122.7 149 205 +1969 1 28 6 20 ERNESTO 51.9 42.1 40 495 +1973 6 23 6 22 ALBERTO 63.1 74.9 30 194 +1952 6 8 18 16 MICHAEL 38.0 253.3 161 838 +1973 8 17 0 28 HELENE 55.4 348.5 89 165 +1984 6 11 6 25 CHRIS 55.1 128.2 135 61 +1990 8 9 0 16 ALBERTO 27.9 293.2 54 519 +1998 12 18 6 18 TONY 26.8 323.7 59 117 +1958 2 10 6 21 SANDY 57.1 263.3 134 694 +2001 4 14 12 14 ERNESTO 41.3 114.1 148 693 +1999 10 15 0 23 DEBBY 33.0 4.3 20 126 +1950 1 28 12 8 HELENE 55.4 143.1 22 612 +2003 5 15 18 19 DEBBY 58.3 237.0 67 685 +1962 11 11 12 2 TONY 8.1 107.1 111 744 +1970 7 22 0 9 PATTY 65.1 165.5 150 512 +1980 11 18 18 17 JOYCE 19.8 32.9 71 353 +1961 7 14 6 7 SANDY 39.6 138.4 52 460 +1996 4 28 6 23 GORDON 64.4 97.9 51 532 +1953 8 17 0 4 ISAAC 59.1 12.6 158 755 +1955 6 7 12 28 WILLIAM 23.0 80.9 38 387 +1972 2 27 18 8 MICHAEL 50.0 240.2 100 703 +1962 6 27 6 13 VALERIE 57.6 131.2 29 362 +1957 7 6 0 1 JOYCE 19.4 220.4 62 697 +1969 3 1 6 2 ISAAC 30.0 213.2 16 742 +1954 1 25 18 3 FLORENCE 9.3 124.7 81 255 +1952 6 8 18 23 ISAAC 68.7 347.0 147 237 +1984 10 20 18 21 SANDY 45.2 210.1 76 489 +1971 3 12 18 10 ISAAC 27.3 42.1 42 736 +1962 12 24 18 5 RAFAEL 68.1 257.0 48 46 +1991 3 15 0 8 OSCAR 24.8 256.0 155 538 +2004 11 9 18 8 TONY 20.3 329.4 151 734 +1994 12 21 6 27 PATTY 24.6 267.4 27 730 +1991 3 3 6 20 SANDY 66.2 325.5 162 291 +1953 8 19 18 19 GORDON 30.3 25.7 101 214 +1988 4 11 6 14 JOYCE 16.4 356.2 60 445 +1988 2 6 12 18 SANDY 25.3 3.1 141 91 +1956 9 18 18 14 ERNESTO 53.7 64.8 20 761 +1989 10 3 6 11 VALERIE 52.4 192.9 115 811 +1996 2 3 12 10 OSCAR 8.8 119.4 72 214 +1988 7 19 0 23 MICHAEL 25.9 337.8 67 831 +1994 6 14 18 22 WILLIAM 70.0 300.6 123 771 +2001 4 5 18 28 ERNESTO 39.3 277.2 101 881 +1962 2 27 6 10 NADINE 37.0 257.8 161 584 +1957 10 12 6 11 CHRIS 12.7 174.8 120 331 +1995 3 16 6 28 WILLIAM 36.4 330.3 96 454 +2003 3 13 6 5 ISAAC 37.1 337.8 25 38 +1966 10 28 18 20 GORDON 65.8 54.1 105 37 +1955 10 5 6 23 HELENE 7.8 105.7 63 835 +1965 9 19 6 15 WILLIAM 10.0 344.8 30 443 +1955 3 6 0 12 VALERIE 58.7 159.5 136 176 +1962 9 22 12 16 HELENE 58.4 258.4 38 294 +2002 7 11 0 14 NADINE 9.3 32.9 67 259 +1997 9 24 12 14 VALERIE 18.9 260.7 15 168 +1998 6 18 12 2 VALERIE 7.7 273.3 24 540 +1988 9 4 6 6 VALERIE 68.5 2.6 131 183 +2003 2 5 6 25 ISAAC 64.4 75.0 54 557 +1955 7 27 12 14 CHRIS 60.1 93.0 91 785 +1950 4 7 6 12 TONY 32.3 123.7 54 612 +1982 7 8 18 9 DEBBY 27.6 32.3 40 387 +1967 4 22 18 21 CHRIS 28.8 90.1 27 543 +1999 6 16 0 10 WILLIAM 67.0 292.7 15 287 +1981 10 15 12 14 FLORENCE 31.5 111.9 16 184 +1981 4 24 18 2 ISAAC 35.2 303.3 117 502 +1984 7 20 6 2 BERYL 49.0 61.5 46 98 +1974 9 15 12 12 TONY 41.2 144.2 91 642 +1975 6 5 18 8 GORDON 49.2 138.9 111 513 +1984 9 18 12 24 JOYCE 16.4 38.2 21 891 +1993 4 18 6 18 TONY 30.4 340.7 60 108 +1995 1 11 6 6 BERYL 57.8 106.0 87 406 +1966 6 6 0 26 OSCAR 56.8 95.9 14 395 +1984 4 27 0 7 WILLIAM 38.4 1.3 85 658 +1951 1 5 0 13 VALERIE 45.4 284.9 20 667 +1988 8 26 18 20 KIRK 60.0 115.8 43 498 +1992 5 7 18 16 NADINE 32.9 211.2 152 251 +1953 9 4 18 25 HELENE 67.9 86.6 98 422 +1990 9 22 18 10 JOYCE 54.0 254.0 129 889 +1973 4 7 12 21 ISAAC 58.7 305.0 22 397 +1987 1 24 18 12 GORDON 16.1 172.5 126 843 +1960 9 24 12 1 FLORENCE 13.1 55.3 78 101 +1977 4 4 18 18 WILLIAM 43.6 9.8 122 136 +1962 8 25 18 23 CHRIS 60.2 61.9 117 587 +1960 10 7 0 28 LESLIE 9.0 183.5 37 752 +1955 2 19 18 13 ERNESTO 50.0 245.7 60 721 +1966 4 16 12 5 OSCAR 57.9 333.1 61 637 +1990 10 20 18 7 GORDON 53.8 253.0 143 625 +1983 3 12 6 27 NADINE 67.6 177.0 156 323 +1992 5 3 0 13 NADINE 38.0 319.5 26 481 +2001 8 6 6 15 ERNESTO 39.7 302.2 96 240 +1951 9 18 18 19 ALBERTO 58.2 337.5 59 383 +1983 3 16 12 19 FLORENCE 45.1 350.6 23 364 +2002 2 2 12 4 TONY 13.1 199.5 23 802 +1968 11 8 18 16 NADINE 17.7 38.2 87 488 +1991 4 7 18 20 SANDY 30.9 94.2 16 613 +1997 9 6 18 5 NADINE 44.4 97.9 22 706 +1986 6 5 12 4 CHRIS 35.6 321.9 91 802 +1954 5 2 0 2 ISAAC 60.8 331.8 31 299 +1959 11 28 18 19 DEBBY 52.9 223.0 77 163 +1962 9 9 0 17 JOYCE 8.3 134.7 64 185 +2003 12 15 0 27 PATTY 20.1 42.1 61 755 +1952 7 27 12 16 OSCAR 60.7 15.8 142 328 +1990 3 15 6 26 OSCAR 32.3 351.9 33 158 +1953 8 9 18 28 ALBERTO 66.0 270.6 95 292 +1961 9 1 18 3 LESLIE 21.5 1.8 69 389 +2002 8 9 6 17 ALBERTO 46.2 233.2 30 698 +1950 10 12 12 6 ALBERTO 55.3 172.6 66 688 +1984 9 5 18 7 NADINE 22.1 192.4 93 4 +1953 8 20 12 12 DEBBY 41.1 327.5 147 60 +1950 9 19 0 8 CHRIS 10.8 77.3 54 813 +1959 6 22 12 2 SANDY 37.7 3.8 41 600 +1960 5 17 18 24 WILLIAM 18.1 197.2 108 198 +1990 10 14 0 19 TONY 9.8 26.3 53 21 +1999 9 15 6 15 TONY 36.3 186.5 112 357 +1979 9 3 0 11 CHRIS 39.9 190.0 17 787 +2000 5 15 12 23 BERYL 55.5 170.1 47 46 +1979 9 17 12 11 GORDON 56.9 1.6 152 839 +1954 2 19 12 1 JOYCE 22.2 216.3 109 383 +1974 5 14 0 11 VALERIE 13.2 177.3 131 779 +1998 12 15 0 26 BERYL 14.5 41.3 58 150 +1981 4 9 18 20 HELENE 37.9 303.2 24 823 +1987 10 22 12 4 PATTY 61.5 336.2 138 338 +1966 7 2 6 5 OSCAR 24.7 237.8 80 520 +1990 1 4 12 4 PATTY 29.8 269.3 162 386 +1978 12 25 18 28 GORDON 9.4 305.8 127 370 +2004 5 10 12 9 TONY 36.6 21.3 84 846 +2003 1 27 0 7 RAFAEL 12.2 194.5 90 863 +1993 3 19 0 21 MICHAEL 68.4 104.9 149 162 +1954 12 28 6 14 VALERIE 40.4 278.2 112 260 +1972 3 14 12 14 TONY 67.4 88.7 97 692 +1954 3 23 0 2 CHRIS 11.1 241.2 103 786 +2003 4 6 18 10 ALBERTO 8.0 198.9 117 47 +1994 5 20 18 24 FLORENCE 69.1 3.6 159 110 +1970 10 6 6 24 OSCAR 34.0 131.3 36 434 +1999 1 7 12 10 FLORENCE 46.1 351.7 63 512 +1979 1 3 12 7 ERNESTO 68.8 303.1 29 680 +1976 4 14 6 28 OSCAR 42.2 199.0 48 118 +1978 1 20 0 23 WILLIAM 59.6 58.7 129 731 +1995 7 22 18 18 ALBERTO 66.1 244.4 54 859 +1976 10 16 18 8 ALBERTO 14.9 212.4 115 328 +1967 12 24 6 18 BERYL 42.9 151.5 21 400 +1986 8 14 18 5 PATTY 60.6 299.7 162 244 +1975 12 28 12 25 ALBERTO 45.0 266.8 25 538 +1998 8 19 18 26 FLORENCE 68.3 189.8 89 277 +1993 6 9 6 12 BERYL 59.0 335.0 88 600 +1976 10 18 18 28 ISAAC 61.3 211.2 151 460 +1973 10 17 6 7 VALERIE 14.2 260.8 61 852 +1994 7 20 6 24 HELENE 33.6 260.7 37 730 +1957 7 2 12 18 TONY 34.4 96.3 56 891 +1980 11 27 6 6 WILLIAM 20.3 127.8 13 868 +1959 9 11 6 12 PATTY 48.6 233.6 136 682 +1978 3 13 18 9 JOYCE 18.0 73.4 142 598 +1986 9 8 0 26 GORDON 27.3 124.2 30 21 +2002 8 16 0 4 HELENE 61.6 341.8 126 505 +1956 1 3 12 6 SANDY 32.4 338.3 50 893 +1985 9 22 0 8 GORDON 24.6 323.2 159 412 +1961 1 16 0 16 ALBERTO 62.6 111.5 22 178 +1986 4 11 0 16 BERYL 25.7 23.1 89 42 +1963 3 5 6 19 ALBERTO 42.3 41.0 109 2 +1966 3 23 18 22 RAFAEL 34.7 235.6 30 404 +1966 7 19 6 14 KIRK 64.2 260.3 151 168 +1956 4 19 12 9 WILLIAM 69.8 90.1 48 795 +1965 3 13 6 19 JOYCE 56.4 246.6 14 661 +1952 3 3 6 27 BERYL 42.1 219.5 17 95 +1991 4 18 6 11 WILLIAM 12.8 191.7 125 357 +2000 5 3 12 1 PATTY 24.0 24.5 137 816 +1983 6 27 6 14 DEBBY 25.0 117.6 29 647 +2004 6 26 12 15 NADINE 34.8 328.6 136 384 +1976 4 20 0 17 KIRK 12.7 319.6 157 34 +1989 8 27 6 10 VALERIE 60.1 160.8 106 415 +1981 7 25 6 5 HELENE 36.6 348.1 29 87 +1980 4 6 12 14 CHRIS 7.2 209.8 73 348 +1965 11 25 6 4 KIRK 26.1 219.7 130 874 +1963 9 21 12 14 WILLIAM 65.3 213.0 163 67 +1984 5 10 12 15 LESLIE 56.1 334.2 128 505 +1979 2 27 18 27 GORDON 31.2 134.4 33 493 +1950 7 17 18 1 NADINE 61.1 71.9 43 587 +1973 4 24 6 11 HELENE 25.6 333.8 132 811 +1951 2 26 0 16 RAFAEL 54.1 0.4 155 644 +1954 11 28 18 6 JOYCE 32.2 350.2 105 558 +1989 5 8 18 9 NADINE 9.8 30.8 79 668 +1973 4 13 12 18 HELENE 63.1 130.8 119 819 +1952 11 25 18 9 DEBBY 7.0 193.1 156 18 +1983 6 4 0 2 ISAAC 20.1 274.1 153 605 +2001 2 10 12 9 KIRK 11.5 273.4 17 736 +1998 12 11 6 13 HELENE 57.5 97.3 102 11 +1953 4 28 12 17 JOYCE 31.5 89.2 147 335 +1963 2 15 12 16 NADINE 26.5 213.5 43 611 +1968 11 24 12 1 JOYCE 51.9 332.5 120 810 +1996 2 15 6 20 ISAAC 42.7 270.5 146 665 +1995 10 21 6 11 PATTY 34.1 180.3 62 658 +1988 4 22 0 16 ISAAC 67.6 28.7 79 299 +1955 11 18 6 13 SANDY 65.1 122.9 163 444 +1992 2 8 0 2 LESLIE 42.3 281.6 157 279 +2000 3 1 18 20 PATTY 15.2 299.5 116 790 +1961 2 13 12 1 SANDY 9.7 7.3 95 734 +1979 5 15 6 5 MICHAEL 48.2 82.3 112 892 +2000 3 27 6 19 DEBBY 50.8 80.2 130 6 +1953 8 17 12 18 MICHAEL 39.2 65.2 90 631 +1998 10 8 6 7 DEBBY 48.2 166.8 78 594 +1995 12 13 12 28 VALERIE 12.6 119.3 112 478 +1998 11 2 18 13 HELENE 64.0 172.2 101 36 +1967 4 11 18 27 MICHAEL 10.0 71.3 128 4 +1967 2 4 0 28 CHRIS 39.2 305.2 36 751 +1950 9 9 18 19 FLORENCE 26.1 195.8 98 503 +1999 3 10 6 17 HELENE 13.2 201.4 90 594 +1984 12 6 6 3 PATTY 61.3 240.2 66 370 +2003 4 8 6 18 ISAAC 51.9 53.7 105 639 +2000 2 4 18 11 VALERIE 25.7 75.3 75 677 +1980 10 10 18 19 ISAAC 9.4 185.8 58 596 +1999 4 11 0 26 GORDON 50.5 3.9 131 253 +1968 8 26 12 3 OSCAR 30.3 355.6 76 518 +1953 6 13 18 19 RAFAEL 16.9 190.2 70 80 +1961 3 22 18 6 FLORENCE 62.9 253.1 42 136 +1987 3 18 18 15 SANDY 59.1 285.7 27 125 +1990 7 1 12 22 NADINE 9.6 238.7 143 83 +2000 6 25 0 16 DEBBY 41.1 192.5 39 243 +2003 11 3 18 4 NADINE 44.0 233.1 67 28 +1968 1 2 12 21 BERYL 46.7 31.0 107 147 +1965 4 22 6 9 HELENE 13.4 309.3 143 637 +1985 8 9 6 13 TONY 52.4 113.7 98 563 +1977 6 19 6 16 WILLIAM 68.3 128.1 107 561 +1969 6 2 12 20 MICHAEL 47.1 225.1 37 4 +1999 1 6 6 8 JOYCE 42.9 190.9 42 837 +1985 8 26 6 10 ERNESTO 24.6 351.2 32 502 +1965 1 9 18 1 OSCAR 51.5 133.3 132 191 +1979 10 5 12 13 MICHAEL 36.6 27.4 88 254 +1963 10 1 18 18 NADINE 23.3 341.6 56 709 +1983 3 28 0 3 ERNESTO 11.9 266.9 75 117 +1982 2 19 18 16 WILLIAM 15.6 285.3 117 692 +1993 5 5 0 11 JOYCE 59.9 326.4 86 433 +1998 8 9 6 20 WILLIAM 14.6 15.1 115 478 +1981 7 2 6 2 BERYL 36.7 126.1 119 678 +1950 11 11 0 28 LESLIE 66.3 237.1 27 384 +1991 8 10 6 24 ISAAC 23.8 328.5 26 741 +1992 12 19 0 22 GORDON 50.8 107.9 88 369 +1988 4 6 0 1 HELENE 43.5 201.5 14 120 +1992 1 11 0 25 VALERIE 57.4 6.3 11 705 +1999 12 28 0 8 TONY 18.0 141.8 41 234 +1976 11 14 6 9 HELENE 59.5 283.7 63 550 +1972 8 19 0 20 PATTY 28.7 270.8 130 721 +1999 9 24 0 19 MICHAEL 45.2 308.9 144 212 +1964 3 6 12 19 TONY 50.3 339.4 137 344 +1951 10 3 0 7 KIRK 51.8 266.3 85 15 +2004 9 19 12 20 ISAAC 15.7 133.4 123 463 +1997 8 19 18 15 OSCAR 48.0 65.3 95 745 +1952 11 19 12 20 MICHAEL 69.3 67.9 112 539 +1964 8 8 12 20 RAFAEL 28.7 130.2 128 148 +1974 4 14 6 25 HELENE 18.2 15.4 16 26 +1996 5 25 18 28 PATTY 49.8 223.9 148 346 +1954 2 8 12 15 CHRIS 17.4 290.8 122 802 +1959 1 20 6 26 SANDY 48.3 131.7 123 691 +2002 12 21 12 10 PATTY 57.0 159.3 16 31 +1962 8 28 0 20 BERYL 41.5 240.5 110 771 +1991 2 25 0 17 SANDY 60.7 157.6 35 512 +1987 8 7 0 27 BERYL 67.4 93.2 122 820 +1997 1 9 12 23 LESLIE 36.1 19.3 164 287 +1969 12 4 6 3 VALERIE 54.2 189.3 114 43 +1991 9 13 12 12 WILLIAM 26.7 54.4 155 392 +1964 7 4 0 12 ERNESTO 42.8 277.7 16 220 +1992 4 10 12 19 ISAAC 67.5 159.4 88 78 +1990 10 2 12 25 ERNESTO 35.8 114.3 22 219 +1979 1 5 6 4 MICHAEL 46.3 312.2 74 843 +1979 5 12 6 11 PATTY 35.2 354.6 31 94 +1983 11 20 0 28 ERNESTO 14.1 61.1 70 180 +1951 1 22 6 28 ERNESTO 59.0 71.3 88 57 +1984 6 4 18 15 BERYL 46.4 255.9 96 100 +1970 2 28 18 17 ISAAC 30.7 333.9 25 270 +1972 4 19 18 16 RAFAEL 57.0 39.1 89 99 +2003 10 5 6 12 TONY 40.1 241.2 58 259 +1953 4 14 12 1 JOYCE 39.4 165.7 154 730 +1985 1 3 0 22 JOYCE 51.3 29.2 56 50 +1984 1 12 0 6 GORDON 8.2 3.5 66 667 +1981 5 20 0 24 PATTY 62.5 153.5 111 460 +1972 10 26 18 9 OSCAR 19.3 236.3 135 585 +1972 3 15 18 4 FLORENCE 41.8 290.2 144 393 +1957 5 24 18 2 TONY 54.6 32.5 104 562 +1994 10 21 18 11 TONY 53.2 252.0 56 609 +1994 10 6 18 11 PATTY 23.3 20.8 46 620 +1964 9 26 12 9 BERYL 41.9 254.7 157 277 +1956 1 13 12 1 ERNESTO 24.2 291.1 49 598 +1990 6 25 6 14 VALERIE 14.7 282.4 100 491 +1985 2 12 12 7 ERNESTO 13.1 83.2 88 479 +1966 1 1 6 21 ISAAC 23.7 261.0 70 548 +1988 11 6 0 26 HELENE 29.8 214.5 76 337 +2002 6 5 18 13 BERYL 12.4 231.5 12 661 +1994 7 14 18 6 JOYCE 22.9 118.7 50 169 +2003 3 3 6 5 ISAAC 25.8 234.1 30 546 +1984 11 5 0 18 TONY 27.7 309.7 92 247 +1978 6 23 6 7 SANDY 54.7 189.9 56 599 +1969 8 16 18 14 HELENE 32.2 190.2 30 159 +2000 7 14 18 25 PATTY 66.2 286.3 123 842 +1992 5 23 0 10 MICHAEL 50.7 85.5 75 897 +2001 11 26 0 1 DEBBY 15.6 268.8 159 324 +1952 12 10 0 4 CHRIS 50.4 48.7 152 577 +1963 12 16 0 10 TONY 7.0 36.3 128 735 +1965 8 26 0 17 OSCAR 53.9 9.8 34 800 +1994 7 9 12 7 RAFAEL 40.9 243.3 90 616 +1958 1 5 0 3 FLORENCE 65.6 10.6 139 666 +1961 5 7 18 12 PATTY 69.1 251.0 52 455 +1996 3 11 12 21 BERYL 33.1 103.0 34 203 +1961 7 19 6 23 VALERIE 14.1 86.3 101 473 +1999 5 23 6 4 HELENE 49.3 131.9 141 819 +1963 1 26 0 8 LESLIE 39.2 0.7 133 428 +1962 11 26 12 13 BERYL 54.3 234.4 86 469 +1989 3 17 18 5 VALERIE 66.1 70.3 120 766 +1985 3 9 12 17 WILLIAM 44.4 111.7 73 530 +1976 8 28 0 26 ERNESTO 69.3 261.0 124 583 +1969 5 23 18 13 PATTY 66.6 155.3 73 652 +2002 7 17 6 24 GORDON 18.9 298.1 112 304 +1952 1 26 12 3 PATTY 21.3 326.3 53 595 +1997 8 21 0 1 DEBBY 43.2 8.6 76 93 +1967 10 19 12 4 ISAAC 69.5 138.2 105 339 +1977 8 11 6 11 ALBERTO 62.0 247.1 115 159 +1977 12 24 6 16 ERNESTO 34.5 269.4 104 357 +1961 1 21 12 17 ERNESTO 27.3 292.2 72 599 +1957 9 27 12 13 RAFAEL 41.3 134.9 57 331 +1995 4 24 12 17 DEBBY 57.9 267.0 147 150 +1954 6 18 6 5 NADINE 8.4 351.9 100 89 +2001 3 5 18 23 VALERIE 59.3 223.2 56 189 +1980 12 20 0 27 DEBBY 7.9 26.1 76 152 +1993 5 12 6 3 ALBERTO 13.5 31.0 101 92 +1957 3 24 6 13 ISAAC 57.3 287.3 46 361 +1999 1 1 12 12 TONY 12.0 116.8 81 810 +1999 3 4 6 22 PATTY 7.4 152.2 77 270 +1986 1 21 18 19 KIRK 26.2 93.6 100 675 +1967 5 7 12 23 NADINE 36.5 245.0 39 594 +1970 4 20 6 5 DEBBY 21.8 326.8 69 708 +1960 12 17 12 25 NADINE 66.0 127.5 47 805 +1982 9 3 0 5 SANDY 49.9 178.2 152 428 +1989 10 9 12 26 RAFAEL 13.3 282.6 23 315 +2002 1 18 0 17 DEBBY 39.8 221.6 63 326 +1960 3 3 6 6 MICHAEL 46.0 160.4 113 145 +1993 6 6 12 9 HELENE 39.6 134.7 99 772 +1952 1 16 6 22 LESLIE 13.8 243.7 67 558 +1952 1 20 6 18 OSCAR 42.5 345.8 144 528 +1987 6 3 0 28 RAFAEL 17.1 195.8 47 298 +1975 8 17 12 21 BERYL 31.3 71.8 55 428 +1978 5 14 6 1 ERNESTO 39.0 129.6 81 197 +1972 1 5 0 28 HELENE 59.0 295.4 75 215 +1994 8 4 0 28 TONY 48.4 157.1 127 173 +1953 3 6 18 2 GORDON 55.0 145.0 143 484 +1974 1 25 18 19 ISAAC 66.8 77.3 140 422 +1980 6 23 0 15 ERNESTO 66.5 284.2 148 32 +1991 1 22 0 22 CHRIS 32.7 18.7 83 141 +1972 8 26 18 22 BERYL 50.8 112.1 51 449 +1981 10 6 12 8 NADINE 21.1 202.4 69 75 +1970 7 5 0 20 SANDY 22.6 351.2 150 38 +1982 12 8 12 27 MICHAEL 63.4 141.4 130 420 +1996 3 24 0 2 TONY 23.6 108.1 73 175 +1970 4 23 12 6 ALBERTO 16.1 19.3 109 473 +1993 11 20 0 15 DEBBY 16.1 17.6 22 890 +1978 4 10 6 24 DEBBY 68.8 291.9 61 80 +1969 11 18 6 3 FLORENCE 16.5 150.2 20 485 +1974 6 26 18 2 ALBERTO 18.4 345.8 110 36 +1961 8 1 6 14 NADINE 21.3 57.9 53 259 +1967 7 25 12 17 NADINE 33.3 294.9 155 563 +1977 3 6 0 26 CHRIS 7.6 231.1 93 244 +1980 2 24 0 9 WILLIAM 21.0 288.3 47 774 +1979 6 5 18 10 NADINE 50.3 326.0 105 605 +1994 1 5 0 18 MICHAEL 56.0 37.5 48 470 +2002 10 19 6 1 NADINE 26.2 101.2 126 442 +1958 11 15 12 19 LESLIE 36.2 267.0 99 40 +1951 12 14 0 20 MICHAEL 37.1 168.8 35 432 +1975 1 18 6 6 SANDY 30.9 150.9 111 158 +1978 1 18 0 8 TONY 16.3 28.3 145 271 +1950 2 19 6 26 LESLIE 44.8 89.1 100 620 +1962 12 4 0 19 WILLIAM 12.6 16.9 123 203 +1984 8 18 6 2 BERYL 48.9 209.4 99 498 +1983 2 1 6 25 RAFAEL 11.5 25.9 11 477 +1962 5 13 12 13 NADINE 9.3 5.5 82 512 +2004 12 8 0 15 DEBBY 31.2 119.5 16 399 +1959 12 25 18 14 CHRIS 35.3 315.4 121 241 +1995 12 4 18 4 PATTY 57.4 318.0 62 302 +1983 11 7 6 14 KIRK 39.0 85.3 10 748 +1975 5 8 12 6 VALERIE 9.7 338.6 127 723 +1961 6 7 6 1 BERYL 62.7 209.3 19 524 +1997 12 14 6 9 RAFAEL 54.5 124.9 133 447 +1952 1 22 18 28 WILLIAM 65.7 344.3 37 57 +1955 9 20 0 15 VALERIE 64.3 279.3 41 641 +1978 12 16 12 26 RAFAEL 59.8 261.5 128 446 +1970 10 2 12 26 MICHAEL 26.1 56.3 159 28 +1969 5 21 12 8 ISAAC 13.2 39.7 154 234 +1957 11 22 0 22 KIRK 69.7 13.2 79 638 +1982 10 14 0 9 JOYCE 43.1 207.0 102 540 +1972 3 8 12 9 JOYCE 66.2 209.1 84 280 +1981 10 25 18 6 TONY 31.7 1.3 98 91 +1997 8 25 6 12 ERNESTO 22.7 52.8 82 357 +1975 12 8 6 18 GORDON 26.7 302.0 141 111 +1993 5 23 18 16 GORDON 16.9 180.7 164 387 +1959 7 5 6 5 FLORENCE 11.4 322.3 41 820 +2004 9 20 6 23 ALBERTO 19.6 154.7 160 885 +1992 8 13 6 14 GORDON 10.8 295.6 88 791 +1991 3 2 12 9 LESLIE 9.3 222.2 142 154 +1996 6 17 12 22 JOYCE 26.1 249.4 138 517 +1952 1 28 12 6 JOYCE 55.6 354.8 119 210 +1982 11 2 18 17 FLORENCE 34.0 335.2 20 72 +2001 6 11 6 17 OSCAR 37.4 86.8 101 679 +2004 5 26 18 7 VALERIE 22.6 275.6 99 664 +1972 10 9 18 4 MICHAEL 9.6 206.7 69 785 +1986 10 14 0 12 OSCAR 67.2 291.9 46 694 +1989 10 16 6 9 RAFAEL 12.4 156.6 47 543 +1950 7 17 6 4 TONY 56.4 108.8 66 87 +1960 7 8 12 8 TONY 19.8 85.9 131 489 +1990 9 26 18 19 ALBERTO 44.2 340.6 136 605 +1994 8 27 12 27 RAFAEL 23.6 106.6 77 213 +1968 1 23 6 5 CHRIS 12.5 349.0 112 15 +1964 9 11 6 24 SANDY 41.5 164.0 126 356 +1988 5 10 18 9 PATTY 25.7 214.3 126 446 +1964 8 5 6 7 NADINE 56.2 50.9 34 521 +1975 5 27 12 26 TONY 65.8 181.7 61 837 +1981 7 3 18 15 DEBBY 56.0 353.5 64 853 +2003 5 24 12 16 NADINE 20.0 94.7 151 3 +1980 6 18 18 22 CHRIS 51.9 309.5 117 575 +1969 12 10 6 6 SANDY 18.4 296.1 151 777 +1974 7 2 6 20 WILLIAM 25.0 178.9 74 853 +1953 2 21 0 24 FLORENCE 32.8 56.0 88 895 +2001 6 17 0 23 OSCAR 54.2 66.1 123 122 +1972 7 12 12 28 TONY 28.6 265.5 23 392 +1966 12 23 18 9 HELENE 62.3 17.3 60 884 +1967 9 10 6 4 VALERIE 38.5 128.6 94 222 +1978 12 22 0 8 FLORENCE 50.9 297.3 65 543 +1955 8 11 0 23 DEBBY 37.3 101.9 159 356 +1995 7 22 0 26 RAFAEL 40.2 138.9 158 404 +1956 10 26 18 24 GORDON 35.0 156.7 106 44 +1998 12 27 18 14 MICHAEL 57.3 59.7 43 509 +1969 11 26 18 19 HELENE 42.5 23.4 13 714 +1981 5 26 6 14 RAFAEL 9.9 315.8 110 537 +1978 4 25 0 1 DEBBY 44.4 137.2 15 845 +1974 2 16 18 22 TONY 68.2 131.0 38 566 +1998 8 15 12 11 VALERIE 47.3 232.1 85 744 +1999 9 28 18 3 TONY 23.0 206.7 124 148 +1973 9 5 6 4 OSCAR 64.5 188.0 12 35 +1967 1 23 12 1 ERNESTO 41.1 249.0 78 580 +1994 2 12 12 5 JOYCE 21.6 10.8 11 693 +1960 2 17 12 3 LESLIE 9.1 243.8 135 402 +1987 3 4 18 10 DEBBY 11.2 92.7 153 189 +1984 7 18 6 26 FLORENCE 25.3 306.6 25 162 +1974 2 12 6 2 RAFAEL 42.1 301.8 130 466 +1994 10 16 12 4 RAFAEL 9.5 255.5 97 422 +1998 8 13 0 15 TONY 38.2 114.0 35 171 +1953 4 3 12 6 RAFAEL 65.8 271.9 160 504 +1975 10 19 0 11 FLORENCE 32.8 96.0 27 687 +1951 6 2 0 20 MICHAEL 13.1 194.5 88 661 +1992 4 10 12 17 ERNESTO 61.3 308.7 33 603 +2004 11 2 0 2 ERNESTO 10.6 269.7 70 552 +1984 3 1 12 28 VALERIE 64.9 48.0 147 294 +1989 9 26 0 26 ALBERTO 65.2 338.9 46 305 +1959 1 25 12 11 SANDY 36.1 100.7 122 170 +1971 4 19 12 21 ISAAC 28.4 317.2 67 798 +1975 1 27 18 14 SANDY 21.6 169.4 22 169 +2004 7 23 18 9 OSCAR 64.3 114.0 29 196 +1958 8 21 12 26 OSCAR 10.8 332.4 118 569 +1985 10 28 12 7 CHRIS 20.7 45.6 150 449 +1973 1 3 12 1 FLORENCE 66.7 78.2 56 466 +1955 5 4 18 1 LESLIE 12.3 24.6 77 746 +1995 9 6 6 22 FLORENCE 17.8 334.5 104 760 +1954 10 22 12 8 NADINE 9.0 289.1 83 569 +1976 8 20 18 4 PATTY 7.7 74.5 62 565 +1966 9 6 18 22 JOYCE 18.8 281.7 156 160 +1954 7 24 12 6 SANDY 38.8 334.6 50 827 +1990 11 24 12 22 BERYL 69.2 286.4 25 357 +1986 5 1 12 25 GORDON 42.4 245.3 159 77 +1988 3 6 18 6 WILLIAM 69.0 193.7 50 781 +1992 3 3 6 20 OSCAR 29.8 262.5 158 379 +1995 3 5 18 13 RAFAEL 43.9 282.9 148 691 +1971 2 20 18 11 ERNESTO 49.0 243.6 112 558 +1956 1 28 18 19 ALBERTO 44.5 251.3 41 398 +2004 7 2 6 21 WILLIAM 41.8 179.4 19 819 +1987 12 12 18 26 PATTY 42.4 123.1 129 307 +1963 7 11 12 10 DEBBY 8.1 6.3 71 215 +1995 6 8 12 5 TONY 47.3 51.5 74 534 +1952 11 8 18 21 DEBBY 38.8 10.8 116 823 +1953 7 4 18 21 SANDY 49.3 180.4 107 505 +1952 7 11 0 8 GORDON 62.2 105.5 71 825 +1958 5 2 0 18 CHRIS 19.8 226.4 51 358 +2002 9 9 18 7 ISAAC 29.9 48.2 42 125 +1972 1 24 6 23 WILLIAM 54.1 67.6 15 315 +1988 10 2 12 17 DEBBY 11.9 172.8 94 666 +1968 2 24 18 20 TONY 59.2 196.8 18 556 +1958 5 14 12 13 LESLIE 20.4 211.6 26 547 +1962 8 22 12 21 DEBBY 51.4 330.3 74 128 +1999 10 25 18 2 ERNESTO 29.0 7.8 100 557 +1983 3 18 12 22 BERYL 67.0 253.8 124 472 +2002 3 2 12 27 JOYCE 12.2 197.4 24 768 +1952 8 27 6 9 WILLIAM 50.5 296.3 134 321 +1997 3 2 18 22 KIRK 50.9 211.4 142 712 +1999 11 9 12 5 ALBERTO 66.3 287.5 49 539 +1952 8 8 18 12 LESLIE 44.8 151.4 144 668 +1998 7 11 12 8 ERNESTO 37.7 55.1 107 146 +2002 7 3 0 27 JOYCE 27.5 202.2 107 158 +1999 9 22 12 15 PATTY 26.7 37.9 125 626 +1965 11 14 6 9 ALBERTO 21.8 218.0 73 14 +1982 7 20 18 22 NADINE 57.7 74.9 21 866 +1958 3 25 12 4 RAFAEL 49.7 77.4 71 72 +1975 5 27 18 22 ERNESTO 41.9 81.8 160 532 +1993 11 2 0 9 NADINE 7.5 8.0 70 814 +1956 7 2 18 4 DEBBY 36.2 139.1 31 767 +2001 8 2 6 1 ERNESTO 63.7 172.0 97 212 +1975 8 9 18 7 RAFAEL 21.8 255.9 159 131 +1992 2 10 6 20 OSCAR 28.8 112.1 93 530 +1999 4 19 18 7 GORDON 35.6 155.2 148 869 +1980 3 25 0 5 TONY 49.2 51.9 96 10 +1960 10 8 12 23 ERNESTO 40.3 110.0 122 463 +1960 12 11 6 24 DEBBY 45.8 296.6 22 562 +1958 9 19 0 6 GORDON 32.3 64.9 20 362 +1960 8 8 0 6 CHRIS 60.1 251.4 21 434 +1993 8 3 18 14 DEBBY 20.5 308.9 67 875 +1975 1 13 0 27 KIRK 41.8 232.3 115 88 +1975 3 28 6 25 FLORENCE 64.6 343.0 45 144 +1973 4 27 12 13 DEBBY 16.8 175.3 124 635 +1988 8 26 0 19 NADINE 12.7 180.9 164 831 +1962 5 10 12 22 NADINE 26.8 164.6 30 842 +1958 5 27 18 27 ALBERTO 7.2 134.5 21 828 +1974 12 21 12 28 LESLIE 8.7 105.5 26 574 +1972 5 27 18 26 RAFAEL 43.9 177.2 41 35 +2004 6 3 18 26 ISAAC 27.2 5.1 137 824 +1955 6 28 6 24 TONY 43.4 342.2 23 877 +2000 1 18 0 28 PATTY 26.6 177.0 118 225 +2003 1 27 6 24 OSCAR 38.8 173.4 128 10 +2000 6 4 0 28 ERNESTO 29.7 139.7 60 398 +1994 10 24 18 7 OSCAR 38.5 154.5 121 135 +1951 5 8 0 2 CHRIS 14.2 242.5 23 45 +1986 5 28 18 4 JOYCE 58.2 6.1 32 276 +1957 2 7 6 25 ALBERTO 9.8 292.1 21 671 +2001 4 13 18 18 HELENE 46.3 20.6 34 5 +1981 6 8 12 15 ISAAC 11.7 326.3 24 552 +1959 6 26 0 22 CHRIS 59.8 58.3 125 627 +1966 6 1 6 21 OSCAR 65.7 33.6 130 236 +2004 1 28 6 18 DEBBY 68.8 209.0 139 806 +1974 1 5 0 17 HELENE 54.3 286.3 27 350 +1951 7 15 0 16 JOYCE 53.2 154.7 108 14 +1976 1 15 6 28 ALBERTO 64.7 108.8 115 250 +1952 1 18 12 12 ISAAC 34.6 306.8 92 102 +1996 12 27 12 28 GORDON 57.8 356.2 118 132 +1997 8 2 18 3 MICHAEL 59.6 163.4 130 667 +1962 9 6 12 27 VALERIE 50.6 180.4 130 283 +1974 12 20 18 15 SANDY 17.3 67.3 57 505 +1995 9 17 18 16 LESLIE 68.3 121.1 23 379 +1972 6 1 0 24 BERYL 32.1 186.3 103 204 +1968 10 12 6 7 BERYL 20.2 58.8 32 814 +1961 5 18 0 21 FLORENCE 52.2 83.5 45 654 +1971 6 2 6 13 KIRK 41.2 184.9 15 883 +1981 8 10 12 15 LESLIE 65.7 345.0 153 684 +1960 11 10 12 19 NADINE 8.8 336.8 73 269 +1981 2 25 6 3 MICHAEL 25.0 148.0 82 642 +1974 9 1 6 22 SANDY 64.3 119.3 111 328 +1999 3 14 12 9 PATTY 11.7 93.9 141 636 +1969 6 7 0 28 NADINE 68.5 78.9 148 783 +1978 3 8 18 6 TONY 34.6 9.8 84 871 +2003 2 17 18 10 SANDY 7.9 109.9 19 494 +2000 8 11 6 7 HELENE 12.1 355.6 19 539 +1969 4 3 18 1 PATTY 42.5 248.7 42 231 +1979 9 5 18 6 ISAAC 66.7 134.0 148 259 +1967 6 4 0 5 FLORENCE 46.9 213.1 122 275 +1996 11 22 0 22 BERYL 7.4 248.4 158 807 +1958 12 12 0 23 HELENE 55.5 223.0 163 605 +1984 5 18 6 22 RAFAEL 36.0 63.4 47 641 +1963 3 16 18 14 BERYL 68.8 47.8 139 562 +1999 10 24 0 21 BERYL 67.2 194.5 83 313 +1980 10 10 0 17 GORDON 51.2 1.7 72 716 +1987 8 3 0 11 PATTY 25.6 103.4 67 570 +1956 8 2 6 8 OSCAR 23.6 219.4 16 643 +1966 9 21 18 21 PATTY 33.1 178.2 158 866 +1977 8 8 18 17 LESLIE 34.6 106.9 40 831 +1971 1 7 12 9 KIRK 68.9 178.6 39 315 +1973 3 9 12 13 JOYCE 30.0 110.5 11 112 +1977 10 18 18 28 GORDON 33.4 297.9 20 287 +1989 8 24 6 17 KIRK 65.7 332.0 64 549 +1953 9 11 6 4 ISAAC 27.6 160.5 18 404 +1986 6 16 6 19 CHRIS 12.5 67.4 158 220 +2004 4 15 18 16 HELENE 41.5 99.2 18 211 +1975 9 19 12 19 ERNESTO 58.6 271.3 55 251 +1959 10 21 6 2 CHRIS 28.0 258.9 18 833 +1993 5 3 12 28 MICHAEL 38.6 315.7 143 887 +1985 3 12 6 4 SANDY 39.0 110.6 32 39 +1981 5 24 12 5 PATTY 14.2 315.1 128 786 +1969 8 8 0 8 GORDON 25.8 258.5 66 744 +1971 2 18 12 20 NADINE 35.7 61.8 140 629 +1989 3 22 18 5 HELENE 40.3 286.9 71 745 +1998 9 13 18 9 CHRIS 14.9 266.9 41 97 +1996 12 14 12 13 SANDY 31.5 297.2 101 813 +1961 9 18 12 13 WILLIAM 47.7 66.6 118 126 +1994 10 7 18 22 SANDY 32.3 30.1 48 524 +2001 1 6 12 1 OSCAR 53.6 137.7 75 301 +2001 6 1 6 14 BERYL 20.8 213.6 20 749 +2001 8 20 18 2 PATTY 41.1 292.9 71 96 +1956 4 13 12 9 JOYCE 12.2 250.9 149 377 +1966 10 21 12 16 JOYCE 49.4 173.6 57 606 +1982 10 5 12 2 JOYCE 22.2 124.0 19 844 +1965 1 4 12 5 LESLIE 14.1 155.2 26 745 +1969 8 12 12 15 TONY 54.7 102.3 30 199 +1979 11 3 0 6 KIRK 21.9 80.4 19 230 +1985 6 2 6 5 JOYCE 12.0 221.6 103 183 +1955 2 28 6 6 ERNESTO 16.7 340.4 36 862 +1963 11 6 18 14 OSCAR 53.6 354.8 157 888 +1971 10 19 6 20 GORDON 32.7 344.8 130 181 +1979 5 12 18 11 LESLIE 14.4 177.9 20 681 +1994 2 11 6 21 RAFAEL 46.0 145.8 59 306 +2001 7 6 18 19 DEBBY 69.2 224.4 141 223 +1989 6 23 6 4 VALERIE 36.8 34.5 74 198 +1990 5 28 6 18 ERNESTO 35.5 131.6 148 722 +1995 10 28 12 22 GORDON 31.7 142.0 26 507 +1986 12 1 18 13 VALERIE 51.4 119.8 105 296 +1957 1 22 6 22 FLORENCE 21.0 214.6 97 631 +1981 11 20 6 6 ERNESTO 62.8 325.1 162 464 +1968 9 20 0 14 LESLIE 9.4 324.9 88 641 +1977 1 17 0 23 CHRIS 40.0 133.4 95 353 +2004 3 28 12 25 CHRIS 63.6 327.4 13 486 +1978 2 26 6 23 DEBBY 8.0 200.7 17 312 +1952 2 1 0 13 ALBERTO 34.0 168.1 154 816 +1979 9 6 18 15 DEBBY 45.6 60.9 125 365 +1967 7 3 18 14 SANDY 67.1 291.9 90 897 +1976 12 26 18 24 OSCAR 61.9 23.8 114 413 +1960 12 13 0 27 VALERIE 33.6 87.1 122 88 +1954 4 3 0 17 ERNESTO 19.8 231.2 90 35 +1968 6 25 6 26 FLORENCE 57.9 272.2 112 383 +1951 6 20 12 14 HELENE 37.1 26.8 117 594 +1953 2 5 6 13 ERNESTO 31.8 63.4 67 876 +2000 6 13 18 25 HELENE 42.9 303.1 136 418 +1995 2 11 6 27 JOYCE 57.1 272.8 100 352 +1993 7 2 6 28 MICHAEL 40.7 291.3 127 477 +1993 4 25 18 17 GORDON 23.8 211.6 154 742 +1972 9 3 12 21 CHRIS 14.4 95.6 102 278 +1994 10 5 6 3 FLORENCE 63.3 122.6 152 380 +2002 5 25 0 17 BERYL 67.0 7.7 48 26 +1969 1 9 0 13 NADINE 50.9 149.9 19 207 +1987 4 24 6 22 RAFAEL 55.5 317.0 38 107 +1969 6 11 0 15 PATTY 56.4 194.3 115 64 +1996 8 13 0 16 JOYCE 58.9 230.4 146 597 +1970 8 21 0 26 TONY 8.1 320.6 31 355 +1958 12 28 12 7 CHRIS 28.9 241.4 131 310 +1986 2 15 18 5 FLORENCE 30.6 147.9 142 516 +1954 11 10 0 25 KIRK 52.7 57.9 102 792 +1967 1 14 6 15 FLORENCE 47.6 88.0 149 208 +1996 11 2 18 20 GORDON 57.6 161.3 48 258 +1973 4 10 0 19 FLORENCE 58.7 21.0 61 141 +1954 9 4 6 22 CHRIS 46.9 265.8 140 6 +1978 6 15 18 7 OSCAR 61.5 65.1 160 343 +2004 3 4 18 21 RAFAEL 48.0 2.3 74 621 +1966 4 12 18 10 NADINE 49.7 305.5 47 367 +1998 1 17 18 24 HELENE 24.6 149.0 147 731 +1972 5 1 18 12 OSCAR 63.3 125.9 133 523 +1982 9 11 0 16 SANDY 65.1 196.3 145 53 +1951 3 14 0 1 OSCAR 57.1 46.8 56 448 +1988 11 8 0 15 FLORENCE 39.9 316.0 63 205 +1974 6 11 6 2 CHRIS 56.6 347.9 122 213 +1986 3 17 0 24 ERNESTO 62.7 163.6 53 651 +1981 11 21 0 9 ALBERTO 54.2 198.4 32 49 +1968 8 12 18 20 DEBBY 33.4 218.1 78 167 +1952 1 14 6 1 DEBBY 57.8 21.0 37 181 +1951 4 14 18 24 BERYL 29.3 319.1 25 688 +2001 11 8 0 25 MICHAEL 63.3 169.8 72 27 +1954 6 14 6 26 FLORENCE 25.6 176.0 161 738 +1995 8 5 18 23 KIRK 11.6 300.9 24 116 +1955 8 5 6 8 JOYCE 33.3 58.9 73 507 +1964 1 1 18 5 TONY 63.8 99.9 13 269 +1959 10 9 12 2 TONY 23.6 199.2 85 310 +1969 10 15 6 16 ISAAC 37.4 53.8 43 211 +1970 12 14 18 13 ALBERTO 25.4 230.0 24 785 +1994 9 21 0 3 WILLIAM 57.2 91.5 61 702 +1959 9 2 18 18 FLORENCE 32.2 137.9 18 652 +1976 11 8 6 25 RAFAEL 26.1 312.2 160 147 +1987 6 2 18 7 ERNESTO 65.3 169.8 89 558 +1966 4 21 12 15 MICHAEL 46.1 76.4 145 788 +1952 4 27 12 27 LESLIE 37.4 195.6 100 207 +1960 5 2 0 12 MICHAEL 28.8 97.7 143 735 +1974 4 11 6 9 MICHAEL 14.8 293.8 65 161 +1986 7 9 6 14 BERYL 53.5 351.1 97 450 +1953 3 13 0 26 BERYL 40.1 193.8 43 200 +1967 7 3 0 15 NADINE 9.9 294.6 19 719 +1961 4 12 0 25 KIRK 49.4 313.1 88 639 +1984 7 6 12 8 CHRIS 15.2 139.4 98 205 +1963 3 12 12 25 HELENE 32.8 55.2 85 69 +1974 4 9 0 10 ERNESTO 9.4 249.9 27 561 +1960 8 6 12 21 TONY 54.5 106.4 126 536 +1951 4 2 18 12 JOYCE 69.6 340.0 84 866 +1972 3 18 12 20 JOYCE 16.5 264.8 141 446 +1984 8 23 12 11 ALBERTO 35.1 169.2 132 38 +1998 4 21 12 21 SANDY 62.2 357.1 103 860 +1987 2 26 18 7 ISAAC 25.7 310.7 11 170 +1957 2 18 0 2 CHRIS 39.2 3.9 46 335 +1992 6 12 18 12 VALERIE 30.1 313.1 44 153 +1955 11 19 12 3 FLORENCE 45.6 216.7 145 479 +1983 4 23 0 19 VALERIE 66.2 218.8 10 856 +1978 5 5 0 22 BERYL 10.6 182.8 96 625 +1957 10 1 18 7 WILLIAM 43.7 289.6 16 194 +1963 9 24 0 12 BERYL 15.5 58.0 89 544 +1970 7 20 0 11 WILLIAM 65.9 107.3 95 800 +1968 3 9 6 24 OSCAR 42.1 64.2 107 847 +1982 5 24 6 2 HELENE 24.9 320.3 32 669 +1961 4 17 18 26 MICHAEL 42.8 263.3 10 280 +1960 1 8 0 11 ISAAC 35.6 140.0 102 864 +2002 5 11 12 18 FLORENCE 11.2 276.8 75 53 +1968 11 1 0 3 DEBBY 53.0 35.3 155 15 +1998 3 5 12 15 HELENE 38.5 126.1 155 283 +1981 7 16 12 7 FLORENCE 10.9 68.2 81 538 +1984 7 17 12 16 RAFAEL 39.8 53.8 145 363 +2001 4 22 12 25 LESLIE 59.5 321.3 10 41 +1950 2 11 18 26 ERNESTO 57.5 226.7 119 865 +1970 12 28 12 14 PATTY 59.3 154.6 105 392 +1974 10 16 12 10 SANDY 24.6 64.0 109 826 +1974 5 6 18 11 OSCAR 63.8 286.6 13 888 +1987 9 18 0 12 VALERIE 7.4 42.2 31 267 +1994 9 28 0 19 WILLIAM 49.3 269.9 155 153 +1973 7 2 12 2 GORDON 35.5 345.0 74 154 +1960 7 21 12 14 JOYCE 39.4 100.7 28 404 +1950 5 4 18 22 VALERIE 30.8 269.4 23 508 +1980 9 15 18 9 NADINE 16.8 241.1 138 87 +1981 6 21 6 3 ERNESTO 55.5 18.5 116 179 +1950 11 8 0 4 HELENE 63.5 294.2 148 106 +1976 6 28 0 4 MICHAEL 32.6 317.1 39 217 +1968 10 9 12 7 HELENE 26.4 255.6 121 315 +1955 6 28 6 25 ERNESTO 16.2 315.6 140 254 +1988 10 18 0 25 OSCAR 7.3 152.8 105 520 +1993 2 25 12 19 NADINE 67.1 345.3 134 125 +2004 7 20 12 22 GORDON 53.2 131.0 84 632 +1977 9 22 6 18 GORDON 19.3 39.4 34 815 +1994 5 17 18 18 ALBERTO 14.6 191.0 116 119 +1994 8 6 6 26 RAFAEL 35.3 56.7 148 93 +1959 9 7 0 19 PATTY 57.8 27.8 64 70 +2004 8 23 0 15 LESLIE 44.5 258.5 89 818 +1960 3 19 6 5 RAFAEL 58.3 166.7 37 422 +1991 3 19 18 11 PATTY 23.3 32.8 40 799 +1996 2 4 6 19 TONY 25.6 176.5 123 674 +1968 7 21 18 4 LESLIE 64.3 67.3 113 427 +1962 10 1 12 6 JOYCE 65.7 328.9 14 652 +1972 12 4 12 6 NADINE 48.8 32.6 147 25 +1963 1 22 0 9 BERYL 17.0 58.6 149 495 +1973 9 10 18 25 LESLIE 61.0 325.1 141 840 +2002 3 1 6 4 RAFAEL 55.0 164.3 56 130 +1950 11 9 12 27 PATTY 66.2 212.0 29 440 +2004 11 6 12 23 VALERIE 52.1 88.2 122 241 +1978 9 8 0 16 CHRIS 67.8 31.8 156 783 +1971 9 15 12 7 KIRK 68.2 15.3 110 665 +1961 12 3 6 15 HELENE 61.2 50.1 77 339 +1993 7 28 6 25 ISAAC 45.3 42.0 118 764 +1981 12 15 6 11 MICHAEL 51.8 143.8 137 543 +1955 9 23 0 23 ERNESTO 15.7 240.3 81 572 +1995 4 8 18 14 BERYL 47.3 228.9 19 441 +1958 12 19 6 1 OSCAR 15.2 127.3 41 11 +1972 10 14 0 21 GORDON 22.8 65.8 96 688 +1979 6 25 12 28 KIRK 65.0 314.4 47 212 +1993 5 26 0 28 HELENE 50.6 155.9 135 355 +1983 2 22 6 14 ISAAC 65.7 108.3 153 252 +1991 2 8 18 20 HELENE 67.7 168.5 64 459 +1980 2 12 6 3 ISAAC 61.9 118.6 70 729 +1968 7 6 12 20 GORDON 63.6 119.6 147 576 +1974 5 23 12 14 RAFAEL 34.1 244.6 72 354 +1982 7 3 18 9 PATTY 47.7 136.7 49 428 +1973 3 11 18 24 VALERIE 40.5 6.0 141 840 +1988 5 1 12 22 VALERIE 67.4 301.3 43 675 +1999 1 2 6 27 DEBBY 56.5 198.0 114 851 +1965 1 17 12 23 SANDY 49.6 155.1 122 764 +2003 11 26 12 5 HELENE 51.8 141.5 142 196 +1991 9 5 0 5 KIRK 39.3 18.5 21 90 +1984 8 11 12 26 ALBERTO 68.3 87.6 151 890 +1967 2 28 12 22 BERYL 68.3 254.0 119 335 +1958 7 10 18 26 KIRK 21.0 185.4 135 210 +1961 5 8 6 17 TONY 38.6 136.7 53 29 +1990 1 4 0 12 PATTY 54.1 46.4 59 753 +1968 12 2 18 8 NADINE 45.8 74.7 20 328 +1991 8 9 6 2 HELENE 15.3 309.8 147 454 +1958 10 17 0 7 JOYCE 59.6 19.5 36 657 +1995 7 13 12 12 SANDY 60.1 265.9 27 808 +1992 12 8 6 26 HELENE 42.4 323.6 107 705 +1950 12 2 0 23 DEBBY 19.0 19.8 133 279 +1979 6 20 0 21 MICHAEL 22.2 23.1 28 873 +1972 9 11 0 13 BERYL 27.0 341.3 45 753 +1988 9 26 18 10 CHRIS 27.1 234.9 42 302 +1989 3 10 6 3 OSCAR 14.5 281.5 157 45 +1973 5 17 18 7 HELENE 28.8 325.2 43 672 +1967 9 11 0 27 LESLIE 33.8 11.6 108 593 +1957 7 25 12 16 FLORENCE 14.8 15.9 108 325 +1970 8 13 18 10 ISAAC 19.9 252.7 117 504 +1984 12 25 6 28 TONY 24.9 55.7 28 602 +2001 7 14 0 11 MICHAEL 40.8 228.3 22 413 +1964 5 10 12 11 TONY 34.6 227.2 134 689 +1977 5 6 12 20 HELENE 51.1 6.5 17 704 +1981 12 22 12 6 KIRK 7.6 334.6 59 608 +1986 3 9 6 18 MICHAEL 14.6 57.5 47 430 +1987 9 3 6 23 KIRK 24.5 234.6 78 327 +1953 4 21 18 21 TONY 68.9 349.0 114 148 +1978 4 2 6 19 TONY 9.6 148.0 125 190 +1987 2 8 18 13 PATTY 69.9 265.3 160 813 +1978 8 26 12 11 DEBBY 26.8 61.4 43 644 +1954 5 19 0 15 BERYL 31.7 20.6 55 718 +1976 2 16 0 14 RAFAEL 47.2 36.5 17 581 +1973 9 22 18 8 VALERIE 65.2 277.1 88 397 +1997 2 21 6 28 PATTY 21.4 312.4 60 109 +1962 6 11 6 17 KIRK 58.9 163.5 149 80 +1975 2 8 12 24 ISAAC 24.0 324.6 66 555 +1966 12 26 0 20 NADINE 10.2 85.9 126 262 +1967 3 5 6 23 GORDON 29.3 198.4 62 551 +1973 12 2 18 25 ISAAC 37.0 64.9 16 131 +1968 6 18 12 1 VALERIE 69.2 346.9 162 604 +1960 8 26 18 21 LESLIE 13.5 8.5 104 176 +1997 10 25 18 26 CHRIS 52.0 218.4 115 845 +1968 1 22 12 25 PATTY 17.8 92.6 12 798 +1979 9 10 12 4 GORDON 51.2 84.7 115 227 +1978 6 18 12 5 ISAAC 55.3 191.3 82 510 +1981 11 18 12 19 ISAAC 46.2 186.5 127 148 +1988 5 20 0 20 DEBBY 41.9 158.7 116 683 +1987 4 12 0 13 MICHAEL 28.9 120.9 148 171 +1982 7 20 0 4 WILLIAM 65.9 43.6 65 528 +1950 10 6 18 7 GORDON 27.1 260.6 156 304 +1994 7 21 0 23 KIRK 68.1 166.5 89 71 +1972 6 26 6 21 ERNESTO 67.7 11.0 126 801 +1972 3 19 0 4 KIRK 29.5 249.7 108 335 +2000 4 9 12 3 BERYL 53.5 249.4 123 316 +1976 5 26 0 24 JOYCE 58.2 335.5 157 366 +1993 12 15 18 16 ALBERTO 32.5 331.4 37 51 +1989 1 2 0 28 CHRIS 34.0 117.6 87 46 +1952 11 2 6 27 FLORENCE 44.9 99.9 95 202 +1981 12 20 6 11 OSCAR 9.8 117.1 66 110 +2000 5 11 6 2 LESLIE 20.2 227.4 61 391 +1979 2 5 6 28 WILLIAM 41.0 150.5 136 378 +1986 7 18 0 5 FLORENCE 11.0 142.8 22 718 +1978 7 7 0 24 ISAAC 20.1 219.8 109 480 +1981 6 25 6 21 ERNESTO 53.4 141.4 131 447 +1982 1 1 6 26 ERNESTO 26.9 219.7 105 68 +1984 8 5 6 20 DEBBY 36.9 195.7 102 63 +1950 1 25 12 9 DEBBY 34.3 89.7 62 876 +1962 6 17 6 15 BERYL 58.6 157.2 13 511 +1990 11 20 18 17 MICHAEL 22.3 331.4 158 478 +1993 3 12 0 16 RAFAEL 51.1 323.0 96 412 +1968 12 7 18 26 VALERIE 39.4 154.0 156 796 +1977 11 28 0 5 JOYCE 53.3 132.1 70 594 +1952 6 15 0 22 FLORENCE 53.0 234.9 76 723 +1981 12 1 12 22 NADINE 49.6 68.1 23 703 +2002 8 1 6 26 NADINE 67.2 161.4 111 621 +1978 5 19 18 28 JOYCE 42.4 289.4 101 592 +1955 2 18 12 20 GORDON 16.1 305.0 128 246 +1973 11 15 18 4 FLORENCE 10.7 110.1 56 26 +1971 10 4 6 17 DEBBY 58.3 27.8 65 643 +1990 3 10 12 5 TONY 48.5 308.2 91 649 +1984 11 1 18 2 SANDY 15.8 310.3 85 780 +1996 2 12 6 9 WILLIAM 39.8 219.3 99 91 +1975 8 28 18 2 MICHAEL 13.0 346.7 61 533 +1952 3 17 0 23 GORDON 41.9 255.2 128 605 +1958 11 7 0 20 SANDY 26.9 53.5 89 289 +1959 2 24 0 27 MICHAEL 56.9 6.8 13 420 +1962 3 5 12 26 OSCAR 68.6 315.9 159 675 +1999 2 13 12 25 FLORENCE 58.2 231.1 23 463 +1968 6 10 0 27 ISAAC 68.7 357.2 37 751 +2003 6 6 6 24 RAFAEL 16.3 316.7 48 376 +1950 12 1 12 6 ALBERTO 66.9 192.0 66 343 +1975 8 11 0 4 LESLIE 50.2 353.9 123 53 +1964 10 12 18 18 VALERIE 49.7 302.7 14 663 +1984 6 15 12 1 MICHAEL 41.5 316.5 59 99 +1971 3 16 12 23 FLORENCE 33.7 22.9 79 216 +1996 9 23 18 6 PATTY 69.1 323.1 161 540 +1962 7 20 6 4 ISAAC 34.6 240.1 40 866 +1953 1 24 18 27 BERYL 32.0 116.5 128 761 +1952 5 16 12 21 CHRIS 38.6 236.2 152 569 +1982 7 17 18 23 DEBBY 38.9 312.8 76 193 +1997 9 21 0 14 KIRK 48.0 345.2 138 704 +2001 6 10 6 20 WILLIAM 31.8 40.1 146 92 +1954 4 28 18 21 OSCAR 38.0 197.6 96 594 +1975 6 4 18 26 VALERIE 39.6 11.9 129 26 +1987 5 2 18 24 CHRIS 40.6 218.1 112 582 +1965 9 11 0 22 VALERIE 22.1 313.2 10 496 +1960 5 22 18 18 ALBERTO 32.5 127.5 120 559 +2003 7 12 0 2 HELENE 25.3 192.5 140 757 +1984 1 4 18 3 PATTY 37.5 76.5 93 458 +1994 8 5 18 3 MICHAEL 49.2 224.4 114 365 +1976 1 11 6 18 JOYCE 30.3 47.4 155 149 +1981 2 24 12 11 GORDON 44.0 114.8 65 790 +1965 5 8 0 7 WILLIAM 33.4 350.3 116 209 +1998 1 8 6 23 KIRK 31.7 103.2 131 619 +1966 12 18 12 1 FLORENCE 50.1 334.9 85 636 +1975 10 5 18 25 MICHAEL 35.8 223.7 125 783 +1971 12 20 6 1 LESLIE 44.9 182.6 25 568 +1969 10 5 12 17 JOYCE 58.8 280.6 68 881 +1980 5 17 0 17 RAFAEL 61.7 11.0 122 96 +1989 10 23 0 19 DEBBY 48.7 84.2 57 172 +2000 7 1 6 18 FLORENCE 44.2 282.2 107 237 +1982 9 26 12 28 WILLIAM 32.6 224.8 39 551 +1975 1 6 18 18 NADINE 21.4 243.7 96 512 +1986 10 26 6 20 WILLIAM 54.9 308.5 78 137 +1954 2 9 18 27 BERYL 55.7 30.1 112 846 +1973 6 9 18 2 CHRIS 44.2 44.2 32 799 +1972 10 9 6 9 WILLIAM 67.7 109.4 79 767 +1957 5 26 0 16 FLORENCE 15.1 249.9 160 424 +1990 11 23 6 24 GORDON 32.7 108.7 51 123 +2003 12 7 12 3 NADINE 14.8 326.1 132 339 +1991 5 3 18 7 FLORENCE 61.0 143.3 128 242 +2001 5 14 12 5 ISAAC 46.1 133.0 51 738 +1950 9 25 18 20 PATTY 54.5 146.7 86 192 +1955 8 4 0 6 FLORENCE 22.7 177.6 44 56 +1963 6 6 0 22 JOYCE 38.7 112.2 138 219 +1992 7 28 0 28 RAFAEL 61.5 31.8 44 514 +1978 11 13 18 27 WILLIAM 30.4 293.7 138 78 +1966 3 16 6 18 DEBBY 26.5 333.2 70 240 +1999 10 25 12 22 KIRK 52.1 73.0 71 365 +1972 1 4 12 6 WILLIAM 10.3 104.9 108 118 +1977 8 22 0 15 BERYL 51.7 346.2 35 132 +2002 4 10 6 25 ISAAC 18.1 39.4 92 200 +1998 10 10 0 18 TONY 17.3 81.1 41 261 +1975 10 6 0 12 HELENE 17.7 329.8 123 332 +1971 9 18 18 6 DEBBY 69.9 282.6 132 319 +1986 5 28 18 9 ALBERTO 20.9 159.5 25 720 +1981 11 14 12 28 ERNESTO 7.5 51.0 13 761 +1988 6 19 18 11 ALBERTO 53.4 3.8 115 169 +1979 4 24 0 10 OSCAR 46.1 249.6 152 435 +1965 5 23 6 4 LESLIE 54.4 184.7 61 760 +1974 12 16 12 18 ERNESTO 29.8 208.3 11 553 +2001 5 6 0 19 HELENE 64.7 99.5 143 763 +2002 12 16 6 24 NADINE 60.3 320.4 90 148 +1963 11 21 6 6 LESLIE 21.5 236.4 65 831 +1973 1 24 18 15 BERYL 62.4 273.9 104 414 +1954 8 4 0 28 LESLIE 50.4 41.9 31 128 +1971 2 15 0 19 FLORENCE 11.2 259.0 64 242 +1973 9 27 6 15 CHRIS 38.1 43.5 88 726 +1964 4 24 0 20 DEBBY 55.9 125.1 26 125 +1956 4 28 12 11 PATTY 25.7 9.3 158 399 +1953 11 23 6 26 DEBBY 10.4 45.9 157 141 +1955 7 13 6 25 PATTY 64.7 58.1 145 18 +2001 5 3 0 20 ISAAC 45.6 46.2 125 239 +1955 12 10 6 27 ISAAC 68.9 70.2 58 721 +1973 8 28 18 10 VALERIE 30.6 270.1 31 259 +1953 4 14 12 10 ALBERTO 23.2 55.9 60 121 +1968 12 14 12 7 ISAAC 65.6 130.4 23 259 +1982 6 5 18 25 OSCAR 10.4 44.2 108 349 +1997 2 2 12 21 KIRK 48.8 66.2 87 876 +1973 3 10 12 26 BERYL 62.7 190.7 38 31 +1950 10 8 12 25 CHRIS 12.4 253.6 29 703 +1952 3 26 12 1 WILLIAM 62.1 107.0 114 820 +1967 8 8 0 10 JOYCE 16.6 209.4 93 295 +1987 1 28 0 21 CHRIS 42.4 88.4 102 500 +1980 5 5 0 9 VALERIE 23.6 192.8 154 247 +1969 10 23 6 28 KIRK 8.4 85.8 75 583 +1999 6 20 12 23 VALERIE 37.7 182.0 115 702 +1991 9 13 0 1 ERNESTO 23.5 15.9 91 667 +1988 5 4 18 21 ALBERTO 61.1 171.1 150 599 +1979 8 28 6 4 BERYL 12.8 243.8 135 620 +1986 5 27 12 6 LESLIE 40.4 236.8 136 82 +1996 3 5 18 1 RAFAEL 69.0 266.3 54 619 +1960 10 9 0 19 KIRK 21.5 235.9 71 866 +1995 6 8 12 19 FLORENCE 42.0 279.0 71 790 +1979 2 23 6 23 FLORENCE 14.0 59.6 53 7 +1978 8 5 12 18 OSCAR 42.8 324.9 20 90 +1996 10 3 18 14 ALBERTO 60.5 141.7 96 780 +1981 4 24 0 20 HELENE 54.3 296.0 72 446 +1953 11 21 18 18 ALBERTO 30.5 2.6 51 147 +1996 9 7 6 5 MICHAEL 56.1 346.0 136 680 +1993 3 22 18 26 JOYCE 66.8 82.6 140 187 +1950 5 8 6 16 OSCAR 8.8 100.2 65 410 +1958 3 26 6 28 KIRK 32.7 128.4 161 471 +1968 12 20 0 14 KIRK 52.7 133.8 87 305 +1950 4 5 18 15 JOYCE 37.7 104.2 12 671 +1951 11 17 12 6 MICHAEL 18.0 82.2 85 54 +1989 1 8 0 4 PATTY 57.5 133.1 88 359 +1984 3 3 18 18 ALBERTO 8.6 71.7 85 695 +2001 11 12 0 28 SANDY 37.7 92.7 41 355 +1972 3 21 0 17 PATTY 59.0 194.0 83 367 +1986 1 22 12 19 LESLIE 52.5 183.3 94 586 +1974 6 24 0 12 RAFAEL 60.5 69.0 110 671 +1951 6 23 6 24 KIRK 29.1 130.8 135 719 +1983 5 14 12 2 JOYCE 43.4 64.5 79 205 +1970 5 8 0 21 ERNESTO 32.5 300.3 81 238 +1974 11 15 18 9 LESLIE 40.2 36.7 110 583 +2003 6 1 12 13 ALBERTO 19.2 17.8 94 821 +2002 9 14 6 27 CHRIS 28.8 244.0 84 212 +1960 3 8 6 18 KIRK 68.7 31.2 72 293 +1991 3 27 18 17 CHRIS 21.1 199.0 155 686 +1971 9 24 18 7 FLORENCE 37.4 231.4 77 407 +1964 9 1 18 17 JOYCE 29.4 38.2 148 847 +1958 2 15 18 16 JOYCE 40.4 70.4 93 18 +1955 6 25 12 21 GORDON 63.8 56.1 146 312 +1987 12 7 0 23 JOYCE 59.1 37.1 112 572 +1962 7 23 6 24 GORDON 40.7 62.3 87 514 +1986 7 17 0 13 FLORENCE 30.3 231.3 65 732 +1976 1 18 18 19 KIRK 9.5 148.6 97 703 +1960 8 27 0 20 OSCAR 27.2 32.2 78 346 +1995 1 21 18 8 MICHAEL 38.7 113.0 123 592 +1987 1 8 12 3 RAFAEL 31.9 180.9 94 174 +1973 5 14 12 28 LESLIE 56.8 237.2 16 48 +2001 7 6 0 24 DEBBY 65.0 41.9 30 709 +1977 6 19 6 2 NADINE 54.4 272.8 157 247 +1963 2 28 12 7 BERYL 62.5 139.1 156 132 +1981 2 7 6 10 TONY 25.3 293.8 43 889 +1950 4 3 6 5 TONY 10.3 351.8 80 301 +2001 3 23 0 27 HELENE 9.8 36.1 105 741 +1950 10 22 0 4 DEBBY 7.4 97.7 44 417 +2001 3 7 12 23 ALBERTO 65.5 237.3 11 707 +1979 8 5 6 15 CHRIS 59.9 32.8 74 751 +2000 10 21 12 18 KIRK 60.7 82.8 90 295 +1983 2 17 6 15 SANDY 17.7 285.8 92 391 +1976 11 27 0 15 JOYCE 51.7 279.3 110 268 +1968 1 28 12 6 KIRK 69.3 323.0 128 240 +1987 8 8 12 9 CHRIS 57.7 94.3 93 624 +1976 5 12 6 9 WILLIAM 25.6 212.1 53 85 +1968 3 4 18 21 DEBBY 37.3 268.3 160 880 +1997 9 5 6 5 FLORENCE 15.5 7.1 22 186 +1965 9 13 0 18 SANDY 9.5 214.6 112 440 +1987 7 2 12 22 WILLIAM 61.4 295.6 61 729 +1990 3 17 12 27 GORDON 43.8 344.4 87 653 +1985 1 24 12 17 OSCAR 11.8 221.2 160 577 +1962 9 6 6 24 RAFAEL 28.1 69.4 136 636 +1965 7 23 12 23 DEBBY 32.3 259.0 152 49 +1973 2 9 0 10 HELENE 31.7 203.6 109 552 +1996 11 25 18 14 WILLIAM 43.0 80.3 21 399 +1997 6 16 18 9 LESLIE 34.7 247.6 53 132 +1989 3 22 18 21 TONY 14.8 328.8 73 867 +1985 9 28 18 22 MICHAEL 49.0 178.9 94 695 +1950 5 21 12 2 PATTY 15.6 323.8 42 855 +1977 11 26 18 27 HELENE 48.1 296.5 45 648 +1983 10 13 6 4 ERNESTO 68.1 11.0 150 505 +2002 4 6 0 24 FLORENCE 64.0 329.6 23 867 +1964 6 1 12 8 MICHAEL 9.5 101.1 122 200 +1974 7 19 6 11 OSCAR 9.2 97.4 10 694 +1975 4 11 6 13 CHRIS 55.0 51.0 13 342 +1972 12 4 6 2 JOYCE 26.7 50.4 129 367 +1955 12 19 12 28 GORDON 17.4 69.0 113 405 +2000 1 13 18 26 VALERIE 24.9 243.0 63 655 +1988 8 23 18 15 RAFAEL 41.1 336.7 51 125 +1974 9 5 0 12 RAFAEL 65.9 27.0 105 298 +1960 5 24 6 6 ERNESTO 39.3 280.3 39 626 +1984 7 1 12 16 CHRIS 39.7 53.7 124 690 +1953 4 7 12 2 PATTY 52.0 213.2 138 743 +1972 6 16 0 4 ISAAC 38.2 232.5 45 357 +1984 11 9 6 24 ISAAC 16.2 156.2 22 403 +1970 7 4 0 10 RAFAEL 9.8 262.7 97 162 +2004 4 7 0 15 ERNESTO 43.8 121.4 18 606 +1983 6 15 12 20 VALERIE 39.7 34.3 156 543 +1975 3 21 0 26 GORDON 14.2 170.7 41 678 +1986 3 7 0 17 JOYCE 12.5 237.3 155 465 +1987 2 4 12 15 ISAAC 58.1 157.4 43 890 +1989 4 11 12 4 KIRK 8.9 241.1 53 890 +1978 11 16 6 15 NADINE 12.4 51.0 57 625 +1972 2 14 6 15 FLORENCE 28.9 191.1 31 708 +1972 5 10 12 16 PATTY 26.2 310.4 74 706 +1962 7 26 6 24 MICHAEL 19.6 347.7 145 777 +1966 5 19 18 15 GORDON 17.3 251.7 64 500 +1964 3 28 12 22 NADINE 69.2 149.5 153 701 +1951 9 5 12 1 CHRIS 47.4 315.3 84 767 +1996 3 7 0 4 PATTY 49.2 357.6 43 47 +1970 10 27 6 4 HELENE 41.5 355.9 150 676 +1994 2 4 0 4 CHRIS 39.7 150.1 103 443 +1977 4 22 12 24 WILLIAM 67.7 39.8 88 723 +1986 2 19 18 25 HELENE 16.1 113.1 68 364 +1951 4 16 18 18 TONY 59.8 264.9 63 331 +2003 3 7 12 7 BERYL 52.6 211.8 105 391 +1994 12 7 18 2 MICHAEL 23.6 68.4 27 687 +1982 12 6 6 21 VALERIE 34.0 51.1 133 177 +1998 2 16 18 9 TONY 62.4 355.2 149 136 +1960 11 10 6 14 ERNESTO 57.5 49.9 135 193 +1991 8 25 12 19 OSCAR 34.4 170.5 133 710 +1950 8 18 6 16 VALERIE 17.9 86.8 115 448 +1965 8 19 12 21 MICHAEL 55.7 172.5 45 246 +1994 1 13 12 12 RAFAEL 34.6 58.9 96 376 +1970 4 19 6 23 NADINE 11.1 55.5 91 566 +1969 7 2 0 11 MICHAEL 27.5 292.1 10 145 +1990 3 15 6 9 GORDON 51.8 272.6 117 106 +1956 6 19 18 5 SANDY 11.5 328.9 58 592 +1988 8 11 18 12 VALERIE 27.3 281.7 163 842 +1971 12 26 18 8 HELENE 45.4 346.1 68 278 +2001 7 7 12 21 KIRK 31.0 98.4 48 197 +1975 1 6 6 12 LESLIE 24.6 213.1 80 628 +1999 5 14 18 17 HELENE 24.4 356.9 66 8 +1956 1 26 0 18 JOYCE 31.6 230.9 60 569 +1957 11 5 12 27 LESLIE 57.5 335.5 158 308 +1981 2 9 12 17 BERYL 47.7 288.0 28 120 +1962 4 14 18 10 FLORENCE 32.1 352.4 145 228 +1961 11 13 0 23 ERNESTO 38.2 163.3 84 437 +1998 6 1 18 2 OSCAR 65.1 298.2 77 287 +1974 8 2 18 13 RAFAEL 30.7 332.0 94 830 +1953 6 16 6 18 OSCAR 23.3 324.1 125 531 +1978 12 3 18 21 WILLIAM 14.4 245.1 108 531 +1951 5 13 6 25 NADINE 59.7 348.2 15 640 +1991 8 22 18 23 ERNESTO 42.6 40.6 88 369 +2000 1 11 18 25 FLORENCE 43.1 61.7 87 651 +1955 4 4 18 15 KIRK 14.5 251.6 81 373 +1979 5 21 12 6 CHRIS 61.3 343.6 98 559 +1986 1 10 18 4 FLORENCE 26.9 278.1 114 375 +2001 8 27 6 25 JOYCE 10.8 292.8 73 261 +1976 3 8 0 25 ALBERTO 37.2 74.5 84 787 +2000 3 25 18 9 ALBERTO 32.1 113.1 102 879 +1961 10 22 0 9 MICHAEL 35.9 63.6 106 287 +1952 7 4 6 28 NADINE 69.6 16.8 62 878 +1969 4 16 0 24 HELENE 43.8 165.2 76 59 +1967 10 25 0 15 VALERIE 22.6 6.9 138 372 +1983 6 27 0 2 DEBBY 29.5 334.3 50 557 +1952 10 25 12 15 ALBERTO 36.8 277.5 120 611 +1975 11 20 6 17 PATTY 16.0 226.9 69 238 +1979 9 5 0 15 MICHAEL 61.5 137.1 129 833 +1985 10 9 6 28 OSCAR 39.0 115.3 159 510 +1975 3 1 0 2 NADINE 23.0 131.9 140 589 +1959 1 24 18 26 WILLIAM 31.9 272.4 20 676 +1973 5 9 12 21 CHRIS 48.4 157.9 19 300 +1950 10 12 18 28 GORDON 13.3 335.0 31 843 +1963 9 1 18 14 RAFAEL 7.1 305.7 50 371 +1952 2 24 18 7 LESLIE 53.2 111.0 76 495 +1966 8 8 12 12 DEBBY 60.5 164.2 155 535 +1991 10 27 6 9 OSCAR 58.0 42.8 27 479 +1954 9 26 12 11 PATTY 18.4 98.7 101 777 +1983 8 28 0 26 SANDY 50.9 4.8 150 194 +1975 9 20 6 16 FLORENCE 32.4 10.1 58 238 +1953 10 18 0 14 HELENE 66.4 8.1 31 783 +1988 9 6 0 7 TONY 27.3 231.5 154 464 +1975 6 15 12 28 NADINE 55.3 114.6 33 224 +2000 11 21 18 8 MICHAEL 54.3 95.6 70 23 +1981 5 24 6 15 RAFAEL 16.6 53.4 33 257 +1954 11 11 0 1 WILLIAM 7.6 19.6 88 837 +2004 7 19 6 7 HELENE 26.6 54.8 135 334 +1983 11 23 6 11 SANDY 12.7 84.9 55 55 +1997 4 13 6 28 MICHAEL 20.1 157.9 36 137 +1999 7 17 0 3 FLORENCE 31.1 258.7 94 700 +1996 11 8 18 8 VALERIE 61.2 356.2 152 846 +2003 2 15 18 19 GORDON 30.3 156.1 52 692 +1979 2 24 12 23 CHRIS 62.9 321.4 126 328 +2003 8 24 18 23 ALBERTO 50.4 182.0 148 78 +1960 2 25 6 14 KIRK 19.7 165.0 146 435 +1970 4 6 6 6 JOYCE 13.7 248.4 54 320 +1982 4 7 18 7 ALBERTO 55.9 101.8 101 45 +1975 1 20 12 9 FLORENCE 42.5 86.1 126 483 +1951 11 6 0 24 LESLIE 12.5 348.6 82 896 +1961 7 15 0 24 ERNESTO 40.5 324.8 133 97 +1988 12 22 12 27 KIRK 61.0 306.8 80 255 +1973 5 6 0 15 NADINE 69.3 320.5 39 444 +1978 10 9 0 3 DEBBY 33.6 350.9 21 668 +1994 11 17 0 27 PATTY 67.7 227.7 108 114 +1985 7 2 0 6 BERYL 55.7 25.2 133 285 +1990 10 12 12 16 HELENE 26.7 322.1 139 32 +1956 9 9 12 14 MICHAEL 46.7 249.5 64 272 +1972 3 22 12 8 HELENE 7.4 355.8 142 702 +1988 6 15 18 25 TONY 21.3 278.3 137 255 +1950 5 18 6 27 FLORENCE 54.9 351.5 41 529 +1972 7 25 18 5 WILLIAM 12.2 87.9 70 415 +1991 5 7 18 13 MICHAEL 14.6 297.1 100 361 +1953 1 7 0 4 DEBBY 58.7 87.1 127 19 +1950 12 9 0 24 GORDON 19.1 100.1 131 466 +1951 8 9 18 16 TONY 44.8 266.2 105 95 +1985 9 11 12 19 KIRK 32.3 17.1 159 302 +1970 3 12 6 4 LESLIE 42.9 134.9 45 893 +1961 3 28 18 13 PATTY 29.6 335.9 125 571 +1977 3 3 0 9 RAFAEL 57.4 0.2 78 278 +1958 4 18 12 28 DEBBY 57.6 232.1 73 847 +1958 10 7 6 22 FLORENCE 57.5 10.0 58 650 +1988 5 2 12 3 CHRIS 69.7 87.2 23 496 +1974 5 16 0 28 FLORENCE 36.9 53.8 30 300 +1975 2 15 0 13 ERNESTO 41.0 287.5 91 759 +1966 11 2 12 8 OSCAR 68.2 211.4 78 182 +1968 1 10 18 18 VALERIE 32.0 241.8 53 787 +1958 6 28 0 10 CHRIS 21.0 157.9 159 263 +2000 5 13 12 8 JOYCE 29.8 233.3 73 834 +1990 4 2 6 2 OSCAR 23.1 88.8 154 707 +1973 12 19 6 9 ERNESTO 63.9 174.8 79 719 +1966 2 24 12 15 ERNESTO 68.8 118.0 137 878 +1973 4 24 6 16 VALERIE 8.0 75.7 108 823 +1978 8 27 18 25 PATTY 13.7 150.2 24 646 +1979 10 15 6 20 MICHAEL 43.7 209.8 100 123 +1985 1 21 6 24 MICHAEL 34.6 175.2 87 55 +1970 9 1 6 19 BERYL 14.6 277.9 40 549 +1953 4 20 6 14 JOYCE 33.5 111.6 77 30 +1969 1 25 18 23 CHRIS 52.7 234.3 79 580 +1998 12 12 6 10 OSCAR 15.9 61.9 130 623 +1970 10 3 18 23 WILLIAM 34.4 135.3 135 202 +1989 5 6 6 4 ALBERTO 19.5 269.2 52 78 +2004 3 22 0 8 VALERIE 9.1 89.7 88 673 +1975 6 12 0 27 RAFAEL 62.7 88.2 73 633 +1956 1 13 18 1 RAFAEL 27.9 268.8 155 570 +1982 8 19 0 2 CHRIS 61.8 128.6 27 41 +1963 2 23 0 22 PATTY 48.8 93.9 46 657 +1979 6 2 6 17 RAFAEL 10.5 268.2 14 854 +1999 1 21 6 26 ERNESTO 12.1 191.5 105 562 +1986 11 19 18 25 KIRK 30.1 128.8 161 518 +2004 1 5 18 11 NADINE 38.7 191.9 160 652 +1997 2 12 12 19 BERYL 35.5 35.6 60 322 +1957 12 18 6 6 JOYCE 67.1 345.2 16 525 +1967 12 27 12 18 SANDY 41.9 279.4 29 35 +1982 1 20 18 24 LESLIE 43.4 114.7 70 311 +1953 1 11 0 9 ISAAC 65.2 184.9 135 305 +1976 10 4 6 12 OSCAR 37.8 102.9 61 799 +1978 1 10 0 16 MICHAEL 62.9 101.6 115 610 +1998 6 27 18 1 MICHAEL 41.9 335.7 71 784 +1968 10 14 0 18 ISAAC 64.0 157.6 45 344 +1990 12 9 18 6 WILLIAM 25.8 255.7 36 313 +1994 2 13 6 10 VALERIE 49.0 142.1 127 851 +1989 5 15 0 2 MICHAEL 51.1 16.3 45 623 +1958 5 25 6 4 DEBBY 10.1 123.7 128 146 +1951 4 17 12 11 JOYCE 29.3 256.1 146 551 +1989 11 27 0 28 ISAAC 12.5 62.5 123 384 +1960 8 28 0 3 HELENE 41.5 333.6 71 385 +1983 10 8 12 26 LESLIE 21.2 241.4 44 490 +2000 11 27 0 23 RAFAEL 69.1 338.5 36 397 +1995 2 4 0 25 CHRIS 45.0 25.7 90 126 +2004 5 6 6 17 NADINE 39.3 219.5 99 753 +1980 6 7 18 6 NADINE 45.3 85.3 111 213 +1983 4 15 6 12 MICHAEL 51.6 21.1 28 569 +1972 2 2 0 12 VALERIE 63.8 195.1 103 344 +1975 7 26 12 3 WILLIAM 12.5 332.3 69 413 +1960 7 27 0 8 TONY 35.0 28.4 153 397 +1998 3 17 0 3 RAFAEL 37.8 271.2 64 55 +1986 5 26 12 7 LESLIE 28.0 11.3 43 372 +1951 7 22 6 10 WILLIAM 59.0 216.2 103 123 +1991 7 19 18 16 ISAAC 58.6 231.0 123 673 +1999 11 23 0 22 JOYCE 7.3 78.3 105 41 +1969 8 24 0 2 WILLIAM 60.4 109.1 93 431 +1969 5 28 0 1 OSCAR 32.0 138.9 143 669 +2004 1 2 12 11 OSCAR 17.0 229.6 117 494 +1957 3 10 0 25 RAFAEL 55.5 222.4 143 660 +1994 11 20 0 10 PATTY 57.0 261.6 155 717 +1986 3 17 6 22 SANDY 44.8 316.0 98 453 +1975 7 19 0 22 JOYCE 29.3 32.3 79 202 +1972 7 2 6 9 JOYCE 24.3 231.4 115 803 +1993 1 14 18 18 DEBBY 25.5 147.6 41 696 +1988 4 22 6 3 ALBERTO 12.6 263.0 102 180 +1969 1 9 12 23 TONY 68.3 43.6 32 131 +1969 4 2 12 3 LESLIE 7.6 14.1 44 549 +2001 1 22 6 10 ALBERTO 51.9 201.8 155 293 +1950 1 22 18 20 KIRK 55.6 292.2 21 702 +1953 11 18 6 10 PATTY 19.0 241.4 144 550 +1957 9 5 12 26 SANDY 12.0 168.5 31 519 +1993 2 26 6 25 NADINE 31.0 163.9 143 616 +1967 4 7 18 28 RAFAEL 25.2 223.9 136 18 +1976 9 26 6 22 RAFAEL 66.2 62.0 145 741 +2003 12 9 6 17 HELENE 8.9 149.8 108 692 +1967 12 8 6 10 WILLIAM 51.7 113.4 138 756 +1967 6 16 0 7 RAFAEL 58.8 188.4 12 830 +1963 9 13 0 20 MICHAEL 32.5 1.9 134 35 +1998 10 27 18 6 CHRIS 39.8 197.9 164 490 +1988 8 4 0 14 KIRK 65.6 58.0 23 125 +1953 3 26 12 7 TONY 33.6 25.9 43 685 +1982 5 15 6 12 ERNESTO 53.7 8.1 47 301 +1973 8 19 6 11 MICHAEL 59.3 254.5 105 505 +1970 12 16 6 23 ERNESTO 12.4 348.7 135 879 +1986 2 17 6 13 VALERIE 20.2 49.4 22 345 +1984 9 25 0 20 HELENE 51.6 3.2 83 143 +1987 6 13 0 27 ALBERTO 42.4 351.4 108 559 +1956 1 8 0 11 RAFAEL 39.9 143.2 93 460 +1976 9 11 6 25 TONY 24.5 54.3 137 393 +1966 6 6 12 22 RAFAEL 41.4 43.8 151 253 +1965 4 1 18 14 PATTY 20.5 276.6 129 813 +1996 3 10 6 28 ALBERTO 66.3 184.0 51 896 +1994 10 3 0 27 GORDON 15.1 92.1 136 871 +1955 3 21 12 9 JOYCE 38.9 149.4 44 496 +1994 6 10 18 9 ISAAC 11.8 217.0 153 252 +1970 1 1 18 7 NADINE 46.0 279.9 92 885 +1982 11 5 18 12 VALERIE 16.3 302.0 92 541 +1996 6 16 18 15 PATTY 27.2 300.9 23 340 +1988 7 17 0 22 HELENE 25.1 206.6 37 511 +1958 2 19 12 3 JOYCE 39.6 32.7 131 447 +1991 11 7 18 23 PATTY 50.0 161.9 49 429 +1978 3 21 12 4 ERNESTO 61.8 288.3 46 218 +1979 7 15 18 6 PATTY 22.2 157.2 75 605 +2003 1 19 12 24 SANDY 10.9 352.1 35 452 +1950 1 9 18 20 FLORENCE 63.2 243.3 75 122 +1995 9 9 0 26 SANDY 33.5 5.9 32 492 +1959 6 13 12 17 HELENE 37.0 85.4 51 258 +1970 4 2 18 4 VALERIE 30.3 201.3 117 325 +1996 6 22 18 25 BERYL 24.3 138.8 163 804 +1973 12 16 6 23 KIRK 44.6 91.7 95 252 +1973 1 12 18 22 CHRIS 39.2 332.4 65 288 +1976 6 4 0 6 OSCAR 41.6 351.1 95 322 +1955 2 27 18 7 FLORENCE 8.6 268.8 27 108 +1990 3 20 6 20 WILLIAM 52.0 203.9 128 564 +1985 2 21 0 15 RAFAEL 38.6 4.1 100 584 +1963 7 3 6 13 FLORENCE 50.2 171.2 93 421 +1956 6 18 12 7 MICHAEL 29.8 105.4 85 493 +1961 11 10 12 28 ISAAC 37.8 318.0 130 610 +1966 10 9 6 27 PATTY 69.9 199.1 22 600 +2004 8 24 18 19 FLORENCE 20.0 12.7 36 521 +1978 7 9 18 7 JOYCE 13.0 151.6 20 232 +1997 9 2 0 28 LESLIE 24.8 106.8 140 518 +1962 1 17 6 18 GORDON 37.0 40.5 113 308 +1966 5 27 0 24 FLORENCE 14.6 317.2 140 864 +1974 6 1 18 26 OSCAR 11.9 316.6 150 117 +1967 8 13 6 11 SANDY 46.1 289.3 62 110 +1994 1 21 6 3 VALERIE 15.4 181.5 38 316 +1984 3 1 12 10 BERYL 30.8 132.5 118 638 +1973 8 28 18 16 PATTY 14.3 34.2 35 286 +1966 4 28 12 3 NADINE 42.1 284.8 20 467 +1977 8 16 18 12 SANDY 68.4 296.2 65 567 +1975 8 8 0 10 LESLIE 7.4 260.2 25 266 +1999 1 28 18 23 ISAAC 36.0 213.5 102 420 +2003 3 28 6 8 VALERIE 59.5 113.8 24 706 +1969 4 23 12 13 BERYL 9.0 138.6 73 574 +1977 11 20 12 8 BERYL 34.2 72.6 42 861 +1954 4 22 6 5 ISAAC 67.4 65.3 93 465 +1966 1 16 6 20 FLORENCE 43.7 30.7 19 385 +1963 3 3 18 18 OSCAR 68.1 304.5 112 336 +2003 2 11 6 19 GORDON 66.6 115.9 137 229 +1967 12 19 18 6 GORDON 52.6 286.1 69 329 +1968 8 23 6 22 DEBBY 55.4 237.5 55 883 +1954 11 11 12 13 FLORENCE 55.4 129.1 69 526 +1971 3 9 18 3 JOYCE 47.3 21.2 47 471 +1955 10 2 18 17 ISAAC 30.9 49.2 41 451 +1996 12 18 18 2 ISAAC 68.9 67.3 70 151 +1958 12 27 6 6 FLORENCE 48.5 20.4 129 123 +1966 1 9 6 5 SANDY 56.4 296.2 59 633 +1980 7 26 12 4 OSCAR 26.1 73.7 110 368 +1966 10 8 0 4 WILLIAM 41.8 177.4 38 433 +1997 3 20 0 5 LESLIE 49.5 262.4 58 493 +1960 7 14 6 11 RAFAEL 54.3 57.6 75 242 +1981 7 16 12 15 DEBBY 44.6 152.2 162 264 +1962 12 15 0 6 JOYCE 22.1 247.0 53 146 +1982 10 6 0 6 NADINE 8.9 305.3 50 669 +1976 12 20 18 2 DEBBY 57.4 2.8 57 37 +1964 9 1 0 8 NADINE 20.9 139.8 76 274 +1995 3 1 0 5 BERYL 38.5 102.0 50 152 +1979 12 12 18 14 ERNESTO 57.3 59.5 128 18 +1973 12 10 18 3 LESLIE 8.4 53.6 93 87 +1976 1 23 12 6 FLORENCE 61.4 290.9 127 69 +1984 4 19 18 17 MICHAEL 39.1 72.1 154 705 +1997 3 25 18 13 MICHAEL 58.1 29.1 90 677 +1970 8 6 12 26 TONY 57.8 295.0 17 804 +1991 12 27 0 19 RAFAEL 23.0 81.4 19 22 +1978 4 22 0 8 FLORENCE 69.1 157.2 15 235 +1996 9 22 6 23 ISAAC 53.5 149.7 30 351 +1969 7 14 0 17 DEBBY 40.8 183.6 37 149 +1951 10 19 12 28 WILLIAM 23.5 328.6 70 301 +1981 9 18 12 25 ISAAC 23.0 329.1 40 665 +1971 5 14 18 4 ALBERTO 55.6 39.5 120 55 +1994 1 25 0 8 WILLIAM 41.6 266.3 36 208 +1989 5 19 12 25 CHRIS 49.3 179.1 12 153 +1995 7 2 12 2 OSCAR 16.7 185.3 78 776 +1996 8 13 6 7 ISAAC 58.8 145.2 130 839 +2000 9 18 12 1 ERNESTO 57.6 272.0 119 257 +1980 3 1 12 28 ERNESTO 39.8 336.5 160 188 +1990 11 12 18 7 KIRK 7.5 66.7 138 584 +1971 4 20 12 1 BERYL 44.1 332.5 28 726 +2001 10 7 0 12 BERYL 48.6 240.1 14 640 +1981 10 20 18 2 VALERIE 37.5 185.2 46 271 +1962 10 17 12 14 HELENE 52.6 74.1 150 423 +1950 6 15 6 21 TONY 39.8 219.8 41 416 +1962 8 28 18 8 KIRK 23.4 202.2 13 175 +2000 7 24 6 22 PATTY 16.8 179.4 81 825 +1986 8 6 18 21 ALBERTO 32.3 222.5 63 491 +1990 12 23 6 22 LESLIE 10.0 14.4 88 467 +1961 10 4 6 9 MICHAEL 51.5 328.4 129 128 +1971 4 6 6 15 NADINE 63.5 221.7 14 254 +1985 7 2 6 27 GORDON 28.9 39.8 34 503 +1978 11 24 0 19 KIRK 33.4 251.4 111 533 +1958 6 27 6 26 FLORENCE 26.9 44.7 15 209 +1999 3 24 12 11 HELENE 22.5 267.6 114 291 +1985 3 7 18 5 MICHAEL 68.2 196.7 38 29 +2000 10 2 0 7 RAFAEL 29.9 324.9 147 412 +1986 1 7 6 21 KIRK 45.7 264.4 52 847 +1974 8 12 0 2 TONY 53.5 288.4 47 176 +1954 6 22 0 23 JOYCE 51.5 270.1 107 144 +1971 8 6 6 10 VALERIE 44.7 248.7 11 761 +1989 9 14 12 8 RAFAEL 18.0 68.3 82 717 +1982 11 8 18 10 MICHAEL 63.6 344.3 38 712 +2000 5 27 6 25 VALERIE 60.7 238.2 95 471 +1963 10 22 18 22 CHRIS 8.7 355.6 55 190 +1971 9 15 6 22 SANDY 68.3 267.2 40 263 +1977 8 20 0 16 ALBERTO 16.7 166.5 130 881 +1961 5 6 6 5 CHRIS 44.1 71.7 131 82 +1988 7 26 18 10 OSCAR 41.6 180.1 122 535 +1973 7 4 0 20 OSCAR 43.2 234.4 22 842 +1998 5 10 12 7 HELENE 21.7 303.0 113 429 +1955 10 24 12 12 MICHAEL 8.7 117.3 61 342 +1989 10 14 6 17 SANDY 22.0 154.3 68 96 +1957 4 28 18 10 WILLIAM 53.1 179.1 148 694 +1973 4 22 0 13 SANDY 56.4 339.8 105 267 +1989 9 5 12 27 SANDY 45.8 205.4 19 480 +1992 3 4 18 11 GORDON 26.4 109.7 93 241 +1986 10 21 18 9 NADINE 10.4 25.5 138 543 +1952 7 13 12 13 HELENE 65.8 57.2 138 437 +1970 3 25 0 22 MICHAEL 28.9 124.4 101 708 +1976 5 2 12 16 DEBBY 64.8 270.5 79 570 +1985 11 8 18 13 ALBERTO 17.3 226.8 14 727 +1980 9 25 6 18 BERYL 54.7 29.6 40 509 +1995 7 20 0 21 PATTY 18.2 240.8 131 274 +1985 12 10 0 5 ISAAC 22.7 302.1 123 705 +1962 12 5 18 7 CHRIS 49.7 281.2 64 96 +1961 1 21 12 11 OSCAR 44.1 352.5 28 279 +1990 6 9 18 22 TONY 18.1 351.8 67 683 +1964 2 13 6 10 HELENE 32.8 27.7 54 615 +1972 4 5 12 14 HELENE 19.1 91.2 124 0 +1953 4 7 6 20 MICHAEL 35.5 61.0 55 478 +1950 8 4 12 9 PATTY 24.3 292.8 77 385 +1955 1 6 18 2 LESLIE 11.0 56.4 144 878 +2000 3 20 18 16 ISAAC 42.4 276.6 146 484 +1957 2 17 18 28 HELENE 43.5 332.2 38 72 +1966 8 22 18 18 LESLIE 38.9 223.9 37 792 +1994 9 22 6 6 FLORENCE 27.4 161.5 146 604 +1965 8 21 12 6 MICHAEL 24.0 19.7 86 304 +1986 12 4 0 12 ALBERTO 28.1 290.4 70 679 +1962 1 20 12 18 TONY 65.6 250.1 59 691 +1973 3 14 12 3 OSCAR 54.9 147.9 98 289 +1983 2 3 6 3 RAFAEL 24.9 112.6 60 274 +1999 10 24 0 22 PATTY 29.8 318.4 145 884 +1954 6 5 0 12 PATTY 23.8 162.8 132 188 +1984 8 13 0 12 GORDON 43.6 274.8 52 693 +1979 11 3 18 15 PATTY 56.8 52.8 118 777 +1956 4 20 18 16 TONY 10.8 188.0 155 681 +1981 11 24 18 9 VALERIE 45.1 86.4 74 386 +1979 9 25 12 1 RAFAEL 14.7 331.9 48 448 +1982 5 4 0 5 PATTY 8.9 255.8 56 405 +1990 12 23 18 11 KIRK 47.2 10.9 54 464 +1999 2 19 6 25 GORDON 9.1 3.0 138 558 +1988 5 14 6 6 TONY 62.2 41.5 158 862 +1950 9 17 0 19 OSCAR 65.8 320.3 128 219 +2004 1 26 18 2 WILLIAM 11.8 234.7 129 885 +1985 5 26 18 21 VALERIE 7.4 68.3 24 478 +1958 2 9 6 24 OSCAR 20.4 244.9 99 771 +1961 7 13 12 18 OSCAR 14.1 136.1 10 487 +1971 6 20 0 11 LESLIE 28.2 61.4 68 868 +1959 8 22 0 2 FLORENCE 20.0 17.4 68 628 +1988 1 18 6 5 GORDON 46.3 70.3 124 701 +1964 9 7 0 12 GORDON 61.9 17.3 133 294 +1956 1 23 12 17 VALERIE 54.6 294.6 89 532 +2001 12 18 0 16 PATTY 60.7 6.8 130 805 +1953 5 22 12 15 FLORENCE 7.6 300.5 156 314 +1988 2 5 12 26 BERYL 21.4 249.9 55 770 +1979 9 14 18 20 HELENE 40.2 234.7 104 626 +1961 12 28 12 10 OSCAR 59.2 313.6 60 597 +2003 1 17 0 12 LESLIE 57.2 345.8 36 478 +1979 10 12 18 8 PATTY 21.2 348.8 36 214 +1984 10 6 12 6 GORDON 9.4 165.1 14 830 +1959 9 24 6 17 VALERIE 7.2 279.9 163 348 +1963 5 16 0 10 OSCAR 57.4 139.2 129 246 +1981 5 21 12 8 NADINE 34.9 88.0 125 147 +1955 3 23 6 13 MICHAEL 66.8 0.6 103 695 +1980 4 3 6 28 RAFAEL 29.7 113.0 87 680 +1994 10 2 6 6 RAFAEL 58.5 128.2 61 366 +1991 12 12 12 16 LESLIE 18.9 105.2 143 551 +1999 8 14 0 28 VALERIE 26.0 245.6 100 384 +1986 5 26 0 8 OSCAR 25.4 272.3 28 313 +1962 4 21 6 8 DEBBY 26.4 193.6 109 435 +2001 1 10 12 23 TONY 61.0 330.5 114 87 +1952 8 28 0 5 ERNESTO 38.9 64.2 87 596 +1983 12 28 6 9 GORDON 51.4 97.0 69 630 +1959 2 28 12 1 GORDON 7.2 180.7 86 83 +1969 6 2 12 27 HELENE 61.2 92.0 71 507 +1968 10 20 6 15 TONY 60.1 74.0 80 683 +1980 4 23 0 8 DEBBY 33.4 253.9 98 589 +1952 6 26 18 27 FLORENCE 19.5 213.6 12 669 +1958 1 14 18 19 BERYL 12.5 167.4 37 13 +1951 5 23 12 6 GORDON 51.4 170.7 127 400 +1996 5 21 18 11 TONY 39.3 116.3 159 503 +1966 2 28 12 24 PATTY 8.7 209.7 112 306 +1975 6 24 0 15 LESLIE 53.2 268.0 136 227 +2000 12 19 6 10 MICHAEL 47.4 256.8 149 865 +1999 7 16 6 4 TONY 55.9 345.4 158 832 +1954 11 3 0 15 WILLIAM 51.8 207.4 15 148 +2000 10 23 18 14 PATTY 32.4 302.2 60 119 +1980 12 18 12 23 LESLIE 22.7 167.0 15 327 +1998 1 3 0 22 HELENE 24.7 345.2 121 10 +1952 8 13 0 28 ALBERTO 68.6 94.0 35 893 +1972 8 11 0 9 KIRK 36.4 226.5 103 686 +1973 7 14 12 22 KIRK 33.3 148.2 81 173 +1957 11 26 0 28 RAFAEL 8.5 168.3 63 258 +1981 11 28 0 28 KIRK 60.5 297.2 133 840 +1998 8 3 6 21 MICHAEL 39.3 111.2 27 675 +1994 11 19 0 2 WILLIAM 52.3 187.8 115 18 +1974 4 28 0 3 TONY 60.5 168.7 32 320 +1957 1 26 0 8 CHRIS 11.1 354.7 15 74 +2001 8 28 6 1 VALERIE 56.7 101.2 140 157 +1952 8 2 0 8 DEBBY 12.9 133.3 31 426 +2002 7 25 6 12 ALBERTO 52.5 145.1 161 533 +1993 7 4 6 17 RAFAEL 43.0 285.8 115 744 +1983 7 1 12 1 PATTY 41.2 166.7 78 637 +1996 7 16 18 18 FLORENCE 52.6 355.3 24 520 +1979 4 9 18 12 DEBBY 19.2 169.5 156 408 +1997 10 18 6 6 ALBERTO 19.8 269.3 59 292 +1966 12 16 18 16 MICHAEL 52.0 338.7 46 807 +1981 5 7 0 1 ERNESTO 39.4 217.6 153 369 +1978 9 1 6 27 CHRIS 14.7 276.4 160 65 +1997 1 27 6 4 LESLIE 17.3 307.8 146 623 +1962 10 4 6 16 HELENE 36.9 171.9 22 736 +1989 6 7 18 15 TONY 40.7 47.3 26 682 +1959 7 24 0 6 VALERIE 13.1 77.9 16 765 +1976 2 12 6 25 PATTY 51.0 173.8 38 769 +1964 2 18 6 1 FLORENCE 55.9 64.9 115 421 +1954 9 4 0 4 TONY 68.2 146.5 115 744 +1973 7 3 12 15 LESLIE 8.3 292.4 128 812 +1961 7 14 18 2 RAFAEL 7.9 53.3 159 62 +1953 7 19 18 19 LESLIE 31.1 155.1 72 771 +1986 5 21 6 10 JOYCE 22.3 314.2 101 189 +1983 8 26 0 15 CHRIS 18.0 53.8 132 790 +2003 4 28 6 14 OSCAR 24.5 21.9 16 636 +1983 1 1 18 12 NADINE 66.2 2.5 23 713 +1957 5 11 12 10 RAFAEL 10.9 191.9 33 250 +1983 12 5 12 5 ALBERTO 37.2 322.1 79 261 +1970 11 7 6 24 FLORENCE 30.4 181.8 62 740 +1995 1 26 0 20 MICHAEL 7.4 93.3 95 7 +1977 1 16 18 28 HELENE 30.6 239.0 56 195 +1971 11 10 6 12 TONY 7.1 341.2 95 65 +1999 1 8 0 3 ERNESTO 43.4 172.9 158 168 +1983 9 15 0 12 KIRK 8.4 257.9 27 792 +1967 4 26 0 10 LESLIE 30.9 295.8 60 793 +1976 4 2 12 7 RAFAEL 29.5 282.9 19 219 +2004 4 9 0 21 GORDON 35.8 147.5 130 530 +1987 2 5 18 19 ALBERTO 50.1 343.0 141 816 +2000 9 28 12 9 ISAAC 23.3 316.0 112 881 +1994 12 22 0 18 VALERIE 36.3 338.7 12 689 +1969 11 22 0 1 ISAAC 22.7 195.1 85 499 +1965 6 16 18 27 NADINE 60.9 144.7 163 203 +1966 4 9 6 14 MICHAEL 50.1 231.1 139 203 +1966 10 18 6 22 VALERIE 11.5 298.8 68 880 +1985 3 2 0 1 BERYL 54.5 221.8 97 59 +1960 6 23 0 13 RAFAEL 66.0 21.1 34 456 +1992 5 4 6 16 DEBBY 9.3 132.7 39 616 +1972 1 7 18 21 HELENE 52.9 261.9 54 492 +1973 10 23 18 28 CHRIS 49.2 310.6 63 649 +1964 10 12 0 26 HELENE 57.8 227.5 135 789 +1950 10 23 0 11 ERNESTO 18.2 69.1 94 696 +1951 5 23 18 16 BERYL 15.6 23.7 22 308 +1961 1 24 6 4 VALERIE 22.7 198.9 29 36 +1973 6 3 0 9 TONY 19.1 176.8 93 69 +1953 2 10 18 25 VALERIE 31.6 231.4 88 73 +1953 8 26 12 24 LESLIE 21.7 112.9 99 604 +1998 5 3 6 15 RAFAEL 46.5 59.9 155 788 +1955 5 13 12 3 JOYCE 17.7 295.5 116 17 +1976 7 13 18 28 HELENE 9.1 159.4 160 230 +1967 7 17 0 19 GORDON 28.9 306.9 26 25 +1981 2 28 0 7 GORDON 25.4 351.2 32 532 +1957 10 23 0 8 SANDY 7.8 223.0 61 367 +1951 5 11 18 5 MICHAEL 66.1 346.1 86 236 +1972 5 19 18 26 WILLIAM 22.2 159.9 142 181 +1977 4 26 6 23 MICHAEL 18.2 187.3 11 161 +1999 2 17 6 5 RAFAEL 28.0 315.8 106 168 +1979 11 19 6 17 NADINE 20.3 157.3 121 661 +1960 7 12 6 5 RAFAEL 28.8 324.3 14 563 +1975 7 14 12 15 HELENE 46.6 293.4 129 342 +1965 11 24 18 14 NADINE 28.3 279.4 54 27 +1982 3 24 18 27 OSCAR 8.6 195.1 21 203 +1971 3 22 6 16 CHRIS 24.4 277.6 35 392 +1964 5 23 12 13 WILLIAM 16.0 190.7 22 822 +1984 4 8 6 4 NADINE 38.7 225.5 112 517 +2000 7 14 12 9 ALBERTO 16.7 160.4 93 668 +1987 12 26 0 28 ALBERTO 13.3 205.2 110 180 +1955 11 15 12 13 BERYL 42.2 154.5 88 625 +1958 6 1 6 20 RAFAEL 48.8 277.9 107 8 +1996 10 21 12 16 ALBERTO 45.1 289.6 115 771 +1950 11 8 18 15 OSCAR 11.6 7.7 148 670 +1971 8 2 0 19 TONY 17.4 218.2 147 247 +1966 10 8 0 11 PATTY 24.5 234.3 134 342 +1963 2 19 6 15 BERYL 10.6 202.7 65 680 +1983 10 13 0 3 BERYL 19.3 44.4 106 526 +1979 9 8 6 20 ERNESTO 22.7 114.5 43 306 +1988 2 12 18 11 CHRIS 38.7 88.7 63 160 +1959 11 24 18 23 VALERIE 35.7 39.0 153 735 +1975 10 17 0 28 TONY 15.6 351.3 85 805 +1963 7 28 0 23 BERYL 50.6 348.9 71 582 +1962 6 23 18 14 KIRK 62.0 76.2 112 519 +1977 4 12 18 6 JOYCE 29.5 156.9 25 851 +1950 10 25 18 26 MICHAEL 33.4 60.1 60 864 +1961 2 26 12 24 ERNESTO 44.5 259.2 49 815 +1997 9 8 18 21 FLORENCE 32.9 326.3 28 401 +1998 8 11 12 4 ERNESTO 43.2 163.2 20 706 +1976 10 15 12 11 OSCAR 28.7 235.2 71 697 +2004 2 5 0 17 CHRIS 45.3 328.3 117 289 +2001 8 23 0 19 CHRIS 48.8 126.8 101 890 +1967 8 15 18 1 JOYCE 31.2 257.9 128 603 +1981 3 24 6 7 LESLIE 35.7 90.3 49 222 +1971 8 7 18 13 FLORENCE 39.5 65.6 97 547 +1950 3 12 6 16 CHRIS 12.7 262.4 95 21 +1995 3 14 0 4 BERYL 29.4 161.7 17 897 +1976 9 1 0 17 FLORENCE 22.5 177.2 46 338 +1995 5 22 12 1 ISAAC 11.6 321.9 23 471 +1996 5 11 12 26 PATTY 55.5 82.3 82 672 +1960 8 27 6 23 SANDY 7.9 286.2 151 839 +1999 4 13 6 28 FLORENCE 41.6 104.7 144 99 +1952 4 23 18 12 DEBBY 38.0 236.7 73 866 +1960 6 1 12 14 NADINE 35.5 173.3 130 330 +1981 1 28 6 11 VALERIE 18.3 257.3 156 832 +1967 12 21 18 26 ALBERTO 32.0 221.5 160 400 +1961 10 8 12 7 LESLIE 27.5 13.8 25 665 +1953 8 3 18 26 RAFAEL 53.5 132.7 87 237 +2000 11 19 0 6 OSCAR 27.9 311.3 91 541 +1997 4 24 18 16 HELENE 24.6 140.9 137 250 +1981 4 12 6 20 HELENE 60.8 246.6 148 459 +2000 11 28 12 23 FLORENCE 28.0 169.6 78 788 +1956 8 19 0 19 PATTY 69.0 10.9 19 533 +1986 3 18 18 24 KIRK 17.0 188.8 105 87 +1987 8 26 18 15 ALBERTO 34.6 299.0 51 892 +1992 2 24 12 11 NADINE 16.8 22.7 65 83 +1957 5 14 0 22 FLORENCE 30.9 279.3 53 415 +1962 4 6 12 22 ALBERTO 48.6 90.1 158 191 +2001 9 15 6 14 HELENE 30.7 163.1 48 451 +1974 4 4 0 21 KIRK 37.5 224.7 120 115 +1985 2 26 0 8 JOYCE 36.2 124.8 120 303 +1956 6 16 0 8 BERYL 24.0 175.5 32 423 +1959 12 28 18 20 TONY 65.4 179.5 19 459 +1959 12 16 0 2 WILLIAM 41.7 181.2 48 489 +1967 9 17 12 24 GORDON 27.2 78.2 92 446 +1956 6 22 12 26 CHRIS 8.2 57.2 22 482 +1975 7 28 12 6 GORDON 38.0 76.5 25 319 +2004 8 28 6 5 KIRK 28.0 13.0 73 525 +1979 12 18 18 8 DEBBY 54.8 247.4 55 532 +2003 2 16 6 9 LESLIE 31.1 244.3 14 452 +1978 11 12 12 20 JOYCE 15.6 355.4 151 351 +1954 2 16 0 23 KIRK 47.3 296.1 101 730 +1964 9 25 6 5 FLORENCE 61.2 228.3 54 533 +1975 6 7 0 23 NADINE 69.2 218.7 151 822 +1978 9 21 6 13 LESLIE 62.0 0.2 34 80 +1975 4 23 12 20 WILLIAM 65.5 58.6 59 634 +1983 4 3 0 26 WILLIAM 60.1 58.7 24 899 +1980 9 9 18 12 LESLIE 34.7 6.6 37 230 +1984 1 3 6 27 NADINE 50.2 335.0 130 86 +2002 3 27 12 2 MICHAEL 35.5 119.9 22 594 +2000 3 10 18 24 SANDY 49.3 235.5 92 293 +2000 7 21 12 1 PATTY 40.0 284.5 92 591 +1970 5 12 0 11 TONY 67.0 284.4 114 843 +1993 1 17 12 8 HELENE 42.9 258.3 116 104 +2004 9 5 12 15 TONY 26.7 350.2 16 12 +1987 12 12 12 17 CHRIS 66.5 242.7 52 357 +1987 5 27 18 9 NADINE 39.7 184.3 59 768 +1958 4 13 0 12 GORDON 42.7 74.4 126 608 +1987 2 28 0 7 CHRIS 66.7 75.8 93 665 +1966 10 7 0 25 KIRK 49.5 196.4 31 367 +1996 9 6 18 25 WILLIAM 65.7 237.8 12 124 +1978 2 23 0 23 FLORENCE 16.9 350.2 57 869 +1957 11 8 0 16 NADINE 52.7 80.2 107 411 +1986 1 7 18 4 CHRIS 48.3 19.6 151 317 +1958 2 6 6 14 VALERIE 62.4 354.5 113 456 +1970 7 3 12 28 PATTY 40.0 330.0 47 235 +1993 12 27 0 5 FLORENCE 69.3 305.2 105 280 +1978 12 23 6 14 GORDON 11.7 163.2 92 315 +1978 10 17 12 17 LESLIE 51.6 189.1 81 283 +1959 3 4 18 22 LESLIE 68.6 155.0 69 805 +1995 6 23 18 17 DEBBY 28.8 157.9 20 291 +1971 3 14 6 22 CHRIS 8.8 295.1 160 342 +1954 2 21 6 8 WILLIAM 13.8 40.9 46 321 +1968 5 21 12 27 WILLIAM 66.3 17.2 109 432 +1962 6 6 12 21 ISAAC 60.3 305.1 128 199 +1970 1 27 0 2 KIRK 38.7 122.3 159 550 +1970 5 19 6 11 ALBERTO 37.4 154.4 93 340 +1950 10 18 0 14 GORDON 69.0 262.7 96 157 +1989 11 11 6 12 CHRIS 35.3 194.6 45 739 +1992 4 19 0 10 NADINE 9.9 185.8 142 863 +1982 3 1 12 25 BERYL 53.5 95.3 106 842 +2004 3 16 12 25 FLORENCE 18.7 166.2 39 57 +1979 3 13 6 1 ISAAC 24.3 233.6 92 805 +1986 1 24 0 22 TONY 68.4 182.2 75 784 +1962 4 26 12 28 NADINE 21.1 128.5 15 632 +1991 10 8 0 7 ERNESTO 67.9 173.1 131 873 +1969 11 5 18 21 WILLIAM 57.9 162.2 73 565 +1981 2 22 18 18 SANDY 70.0 185.9 112 353 +1998 3 2 6 12 ERNESTO 53.9 65.6 115 595 +1987 7 19 18 28 WILLIAM 46.0 100.9 40 525 +1970 9 18 18 16 ISAAC 13.9 46.6 162 239 +1984 10 23 12 25 KIRK 68.4 138.0 159 465 +1993 3 24 18 21 LESLIE 33.1 122.0 57 311 +1965 5 1 12 15 BERYL 15.2 218.2 158 796 +1989 3 22 12 19 OSCAR 48.2 4.0 66 12 +1951 5 9 12 2 ALBERTO 55.8 38.4 137 471 +1990 9 9 6 5 RAFAEL 21.4 130.3 130 832 +1993 2 22 12 16 LESLIE 57.3 245.6 82 274 +1971 10 23 18 25 TONY 60.3 8.3 18 140 +1970 1 9 12 12 JOYCE 50.3 255.4 140 274 +1981 10 4 18 13 LESLIE 8.3 100.5 44 452 +1981 6 6 18 5 VALERIE 62.6 357.9 143 392 +1970 5 14 0 13 JOYCE 31.9 278.4 78 826 +1969 7 11 0 23 ERNESTO 13.4 214.6 135 759 +1978 1 24 18 1 GORDON 56.3 285.7 76 250 +1971 5 1 18 19 GORDON 56.9 347.0 77 413 +1991 3 24 18 8 ERNESTO 12.7 312.4 21 532 +1964 1 19 0 2 ALBERTO 50.8 64.2 33 602 +1958 9 13 12 21 TONY 20.1 212.3 96 560 +1983 12 10 18 17 KIRK 38.1 192.6 73 595 +1999 6 26 12 8 RAFAEL 56.3 65.6 119 899 +1953 5 21 0 16 ALBERTO 19.0 244.7 93 512 +1990 11 24 12 25 HELENE 50.3 335.1 107 830 +1963 10 17 6 4 BERYL 7.8 281.5 70 73 +1974 1 8 12 19 JOYCE 56.0 145.2 153 195 +1959 6 18 0 4 DEBBY 66.5 81.2 20 502 +1964 9 18 12 6 HELENE 34.3 109.0 37 755 +1996 6 14 18 17 VALERIE 29.5 58.5 95 257 +1980 5 8 12 17 ISAAC 59.9 354.7 152 327 +1987 2 12 0 1 WILLIAM 42.2 67.4 77 43 +1986 7 9 18 4 LESLIE 55.3 143.0 108 110 +1980 9 24 18 15 FLORENCE 25.2 27.1 138 123 +1969 9 12 0 9 KIRK 9.5 115.0 130 72 +2001 1 14 0 1 MICHAEL 46.2 307.6 27 395 +1977 1 25 12 27 FLORENCE 28.2 63.1 76 817 +1991 3 15 0 11 BERYL 13.2 110.5 148 866 +1984 1 25 18 7 MICHAEL 60.4 143.1 150 371 +1957 2 3 0 3 GORDON 66.3 177.0 11 370 +1974 2 16 0 3 BERYL 10.4 336.2 129 446 +1998 4 28 0 26 MICHAEL 54.1 19.3 20 875 +1997 4 17 0 11 JOYCE 39.8 146.2 36 600 +2002 3 18 6 22 ALBERTO 35.1 17.5 100 578 +1980 10 8 18 28 GORDON 11.4 184.3 42 502 +1992 7 23 6 4 OSCAR 56.0 321.9 26 798 +1995 7 11 12 6 NADINE 14.6 138.3 151 476 +1982 2 20 6 13 DEBBY 43.6 195.5 22 808 +1983 4 6 12 3 SANDY 47.3 118.7 92 479 +2003 8 11 12 21 LESLIE 28.8 57.1 40 563 +1969 4 23 12 2 RAFAEL 33.8 320.1 128 57 +1956 1 26 12 20 RAFAEL 46.8 327.5 125 271 +1995 7 25 0 1 FLORENCE 48.4 186.5 99 780 +1999 2 11 18 14 GORDON 44.9 89.3 87 414 +1961 9 8 0 25 MICHAEL 62.7 325.3 18 61 +1973 1 15 6 14 GORDON 64.0 230.4 131 636 +1991 7 14 12 17 RAFAEL 53.0 231.6 160 281 +1995 9 19 0 24 ISAAC 63.5 205.9 124 145 +1952 6 16 18 10 VALERIE 45.3 190.5 10 516 +1966 9 18 18 17 RAFAEL 67.9 282.4 45 501 +2002 7 17 12 10 RAFAEL 19.3 259.9 67 411 +1981 9 28 0 1 LESLIE 47.9 218.5 157 787 +1997 6 28 6 13 JOYCE 10.7 145.3 70 679 +1976 9 18 0 27 DEBBY 55.4 162.7 106 218 +1970 3 1 18 8 DEBBY 15.1 137.8 14 295 +1980 3 11 12 21 TONY 8.5 95.4 74 286 +1966 7 21 12 1 PATTY 11.3 137.8 39 865 +1974 4 24 12 14 MICHAEL 11.4 147.9 145 289 +1983 3 21 18 25 LESLIE 28.1 221.5 53 730 +1998 9 16 12 19 FLORENCE 47.8 72.1 66 169 +1964 5 28 12 13 MICHAEL 30.6 267.0 109 214 +1957 1 16 6 14 FLORENCE 19.1 323.1 58 553 +1950 4 11 18 22 FLORENCE 22.1 173.3 85 418 +1993 6 23 0 3 BERYL 37.7 233.2 93 474 +1973 12 13 18 19 ALBERTO 51.1 101.2 18 253 +1995 10 25 0 26 MICHAEL 12.1 297.1 94 657 +1951 12 20 12 21 MICHAEL 12.7 349.2 113 23 +2002 4 6 6 10 CHRIS 54.5 68.0 129 488 +1986 12 9 18 5 JOYCE 17.3 296.7 15 416 +1986 10 26 18 19 SANDY 41.3 102.4 70 833 +1987 5 27 6 20 WILLIAM 61.8 84.3 96 98 +1997 7 21 18 18 ERNESTO 65.9 279.2 43 3 +1999 1 13 6 24 FLORENCE 37.2 158.5 46 353 +1984 8 25 12 26 LESLIE 8.5 266.0 61 297 +1994 8 13 6 28 ALBERTO 43.8 19.1 108 249 +1976 1 7 6 1 FLORENCE 48.3 15.9 96 77 +1988 11 14 12 12 TONY 46.7 278.9 108 791 +1960 7 5 18 16 ISAAC 26.8 25.9 99 322 +1969 7 15 6 3 ERNESTO 53.5 6.1 142 297 +1950 11 26 6 23 ALBERTO 51.2 246.9 150 523 +1981 8 14 18 26 BERYL 58.1 168.0 124 661 +1954 12 18 12 28 ALBERTO 30.5 200.7 77 176 +1981 2 9 12 19 VALERIE 18.9 174.1 14 863 +1987 6 23 12 1 BERYL 32.5 234.7 32 361 +1990 10 2 6 3 VALERIE 55.0 103.1 14 305 +1980 1 6 0 8 HELENE 55.1 52.8 142 746 +1999 8 11 18 24 OSCAR 59.7 90.2 143 536 +1970 3 21 18 17 KIRK 20.0 28.7 139 679 +1999 4 14 6 6 PATTY 65.8 310.6 57 227 +1964 12 18 0 1 SANDY 25.6 253.9 79 744 +1982 4 27 0 10 DEBBY 32.0 148.2 33 270 +1952 10 6 6 28 ERNESTO 24.4 148.7 99 139 +1951 11 8 18 8 HELENE 45.2 5.2 122 171 +1974 9 16 18 17 WILLIAM 54.9 296.2 14 477 +1997 9 7 0 27 FLORENCE 67.0 185.7 160 742 +1970 12 7 12 18 DEBBY 60.9 189.9 127 743 +1968 2 10 18 20 LESLIE 30.9 331.7 120 891 +1957 10 17 12 25 KIRK 60.0 238.7 90 541 +1954 4 26 6 5 FLORENCE 68.3 236.3 48 97 +1966 6 4 0 25 DEBBY 46.9 246.7 132 782 +1995 8 28 6 24 CHRIS 65.3 311.1 40 73 +1961 5 7 18 15 VALERIE 68.3 235.6 86 757 +1968 11 2 18 11 JOYCE 31.8 121.8 75 134 +1982 8 1 18 25 CHRIS 54.8 45.2 160 821 +1954 11 4 18 27 LESLIE 69.6 328.3 56 554 +1966 9 6 12 22 ISAAC 40.1 61.3 105 485 +1954 5 7 12 4 MICHAEL 34.9 1.0 81 791 +1974 3 15 6 17 SANDY 31.8 161.7 39 175 +1977 10 20 18 27 WILLIAM 65.2 98.9 70 217 +1954 9 16 18 4 NADINE 8.6 304.1 149 50 +1953 7 10 0 19 SANDY 13.7 82.1 16 358 +1980 12 24 18 23 TONY 20.8 205.0 158 407 +1976 11 21 6 1 MICHAEL 49.0 350.4 14 331 +1994 2 8 0 8 MICHAEL 35.5 58.1 96 300 +1992 8 1 0 16 HELENE 52.8 331.0 164 126 +1952 9 26 12 22 BERYL 9.1 41.1 154 428 +1961 8 17 12 26 FLORENCE 40.5 77.5 116 730 +1959 11 13 12 6 MICHAEL 40.2 80.2 78 102 +1969 4 12 12 17 GORDON 54.7 214.9 147 777 +1994 11 24 6 26 ERNESTO 43.6 232.5 94 13 +1998 8 14 6 6 ALBERTO 30.9 306.2 83 727 +1992 11 4 0 6 ERNESTO 48.0 236.1 94 834 +1958 6 8 18 6 PATTY 68.5 167.4 40 134 +1955 2 21 18 17 CHRIS 16.6 33.2 159 432 +1986 2 9 0 15 ALBERTO 10.8 253.3 56 548 +1976 9 10 6 23 OSCAR 26.7 81.3 27 101 +1976 12 18 18 6 KIRK 24.2 309.8 107 699 +1998 9 21 6 10 PATTY 10.7 61.4 122 167 +2000 2 22 0 14 OSCAR 25.2 162.0 157 683 +1981 6 9 6 15 PATTY 35.1 312.2 135 591 +1970 12 25 12 3 BERYL 63.4 250.7 124 89 +1978 5 4 0 24 ALBERTO 36.6 278.7 102 156 +1966 5 2 0 6 FLORENCE 65.5 274.8 22 169 +1950 11 11 18 14 MICHAEL 64.3 54.3 132 487 +1973 5 7 18 9 PATTY 47.9 147.2 115 542 +1998 12 6 12 9 CHRIS 33.0 332.3 55 118 +1955 3 6 18 19 DEBBY 55.0 355.0 119 858 +2001 4 6 18 25 HELENE 65.3 52.5 150 580 +1960 11 28 6 25 LESLIE 30.9 219.8 161 806 +1955 5 14 0 1 JOYCE 46.8 180.0 110 187 +1968 9 16 18 28 SANDY 50.1 160.5 42 536 +2004 2 19 18 23 ERNESTO 52.6 186.2 86 832 +1992 3 4 12 18 ALBERTO 57.9 11.7 34 388 +1990 5 1 18 27 ERNESTO 50.0 42.3 147 524 +1969 3 22 12 9 ISAAC 24.3 174.5 25 829 +1973 1 23 18 14 VALERIE 21.1 89.3 135 881 +1982 1 20 18 19 BERYL 37.9 288.8 140 775 +1971 9 7 12 19 LESLIE 25.2 62.8 157 170 +1955 8 8 0 16 OSCAR 58.5 65.9 97 865 +1950 4 18 0 17 ISAAC 16.5 196.7 41 270 +1953 10 27 18 13 OSCAR 29.9 260.3 134 425 +1956 9 26 18 22 LESLIE 58.4 21.0 13 248 +1987 4 20 6 14 SANDY 66.3 120.4 71 562 +1996 5 13 12 1 VALERIE 7.5 70.5 31 163 +1965 4 28 6 2 FLORENCE 69.3 220.6 35 896 +2004 4 17 0 6 LESLIE 49.4 149.4 101 323 +1964 1 27 18 1 HELENE 51.1 302.4 18 721 +1974 5 8 18 26 VALERIE 41.5 211.8 46 336 +1969 7 3 6 6 FLORENCE 33.9 81.7 76 27 +1959 9 6 18 18 NADINE 48.0 211.1 57 444 +1983 1 4 12 16 GORDON 51.8 45.8 36 551 +1985 3 22 18 1 ALBERTO 29.6 289.3 96 652 +1964 9 7 18 9 JOYCE 30.4 199.5 104 618 +1956 6 20 18 27 NADINE 9.8 31.0 58 84 +1964 2 5 12 6 OSCAR 29.3 9.5 38 495 +1978 4 24 0 11 BERYL 47.9 94.3 15 424 +1980 7 24 18 27 KIRK 14.3 245.3 45 813 +1957 11 23 12 28 SANDY 50.2 189.1 81 304 +1988 3 25 18 25 OSCAR 52.6 119.0 91 17 +1978 2 4 6 1 DEBBY 18.9 88.1 74 215 +1987 7 16 18 16 ISAAC 52.5 148.5 138 160 +1980 1 5 18 4 ERNESTO 49.1 268.2 42 344 +1975 9 12 18 21 CHRIS 57.0 9.8 135 574 +1967 6 7 0 26 DEBBY 37.2 87.0 140 822 +2002 3 16 18 27 HELENE 27.6 347.6 145 225 +1986 11 4 18 4 KIRK 65.8 291.3 94 462 +1959 10 1 0 23 NADINE 13.5 209.1 135 117 +1974 2 2 18 1 ISAAC 39.6 197.6 46 570 +1986 9 19 6 25 NADINE 26.8 137.8 158 129 +1983 2 7 0 7 ERNESTO 9.8 170.2 17 253 +1954 6 10 12 25 ERNESTO 40.7 191.4 82 701 +1952 3 8 0 27 TONY 18.1 337.2 64 69 +1996 5 15 18 3 PATTY 8.9 314.8 138 556 +1956 6 10 0 13 NADINE 31.3 137.5 84 691 +1962 7 3 12 23 PATTY 18.8 321.1 124 347 +1965 2 6 6 4 WILLIAM 36.3 331.1 158 136 +1990 5 18 18 19 WILLIAM 52.2 31.0 133 315 +1961 9 1 12 19 ALBERTO 55.1 250.2 130 881 +1986 12 12 0 11 DEBBY 21.7 222.1 90 872 +2002 2 14 12 18 TONY 44.4 245.3 106 604 +1956 7 21 6 18 MICHAEL 20.0 283.8 85 567 +1996 8 21 6 18 SANDY 59.0 25.4 148 330 +1963 3 10 6 22 JOYCE 19.6 17.2 50 312 +1953 1 19 0 19 ALBERTO 28.4 220.5 53 721 +1956 8 12 0 22 ISAAC 18.3 294.4 36 455 +1981 9 24 0 7 VALERIE 42.7 94.2 85 392 +1961 1 6 0 25 JOYCE 22.9 16.4 85 615 +1958 10 22 12 6 MICHAEL 59.7 1.0 29 130 +1973 8 8 0 8 DEBBY 58.4 162.0 67 361 +1952 6 25 12 11 NADINE 17.4 138.7 27 489 +1997 10 20 18 22 FLORENCE 50.0 37.5 83 104 +1985 12 9 12 9 GORDON 14.7 329.5 144 623 +1994 5 6 18 27 GORDON 39.5 342.8 22 876 +1974 10 24 18 23 JOYCE 35.5 254.7 112 799 +1954 3 24 6 14 MICHAEL 24.4 216.8 45 248 +1957 12 14 12 20 PATTY 56.8 65.4 16 549 +1964 2 6 18 18 ISAAC 65.6 4.8 19 551 +1960 12 28 12 11 NADINE 48.1 58.8 54 533 +1997 8 4 0 18 VALERIE 27.3 201.0 21 422 +1992 9 24 6 15 TONY 19.5 11.6 126 91 +1954 11 22 6 11 SANDY 18.3 12.8 99 121 +1986 11 16 12 11 DEBBY 55.0 97.5 70 47 +1981 5 2 12 25 ISAAC 33.4 175.1 60 722 +1960 12 19 0 13 VALERIE 14.7 243.1 59 847 +2002 6 5 18 1 ALBERTO 10.3 259.9 18 240 +1996 9 28 18 19 RAFAEL 69.6 3.8 156 591 +1987 8 18 18 9 OSCAR 46.7 285.2 52 195 +1970 12 26 6 7 OSCAR 14.6 105.5 37 579 +1951 12 26 0 28 OSCAR 27.2 281.7 38 203 +1974 3 19 12 9 RAFAEL 66.2 205.7 119 165 +1964 2 1 0 7 KIRK 45.5 119.8 150 560 +1992 8 6 18 13 BERYL 13.6 99.4 134 560 +1966 7 3 18 18 SANDY 43.4 36.6 122 170 +1985 4 15 0 25 LESLIE 28.4 62.6 15 712 +1987 8 16 18 25 OSCAR 40.8 25.1 33 556 +1955 10 9 0 3 OSCAR 13.1 169.8 145 752 +1950 8 6 18 26 DEBBY 36.0 303.0 68 29 +1997 9 11 12 11 BERYL 46.0 22.8 144 623 +1978 3 17 12 4 VALERIE 37.3 223.1 159 395 +1988 5 1 6 12 ISAAC 41.1 52.4 23 144 +1993 1 12 6 11 FLORENCE 69.2 323.6 101 137 +1964 2 8 0 13 CHRIS 59.0 38.3 29 608 +1958 2 4 18 3 JOYCE 47.6 240.5 144 47 +1967 9 21 0 13 LESLIE 12.4 324.6 139 428 +1996 12 21 0 20 JOYCE 19.9 213.3 68 834 +1987 9 10 0 17 HELENE 21.8 217.8 38 789 +1990 4 10 12 24 TONY 42.1 286.6 113 156 +1985 5 10 6 9 PATTY 67.5 190.6 75 214 +1996 1 21 12 28 NADINE 63.0 260.9 106 166 +1967 4 10 12 11 OSCAR 48.3 48.8 160 378 +1978 8 7 12 28 VALERIE 49.2 14.1 47 594 +1954 3 9 12 11 HELENE 39.5 181.4 141 189 +2001 1 26 6 8 RAFAEL 10.0 97.4 94 784 +2000 3 14 12 16 PATTY 18.5 185.1 55 660 +1962 7 25 0 9 CHRIS 33.6 236.5 17 185 +1965 6 9 6 3 NADINE 50.1 182.0 157 752 +1973 10 9 0 27 MICHAEL 43.7 138.9 88 61 +1999 10 26 0 25 CHRIS 15.4 349.1 45 822 +1985 5 5 6 4 ISAAC 50.9 253.5 144 109 +1994 11 5 0 15 OSCAR 10.7 172.0 148 521 +1950 2 3 0 7 OSCAR 29.4 187.8 39 589 +1976 10 16 18 11 VALERIE 52.9 279.8 139 713 +1961 4 14 0 22 TONY 20.3 28.6 160 392 +1965 4 20 18 7 ISAAC 25.0 137.9 49 542 +1973 10 5 18 10 ISAAC 66.2 225.1 100 266 +1981 4 28 0 28 NADINE 21.3 264.3 101 586 +1960 1 13 6 8 GORDON 39.3 46.0 153 519 +2001 11 5 12 20 MICHAEL 51.0 348.5 124 187 +1975 10 21 6 22 PATTY 56.3 52.2 70 259 +1987 9 3 0 4 LESLIE 17.2 128.1 22 37 +1987 5 11 6 21 PATTY 11.2 207.2 24 186 +1950 7 2 12 20 CHRIS 33.4 253.1 116 177 +1953 2 27 18 14 SANDY 68.4 245.2 73 409 +1987 1 19 18 14 CHRIS 32.6 5.1 71 782 +1997 11 4 6 23 LESLIE 16.8 232.5 137 780 +1976 11 23 18 14 TONY 67.9 306.2 135 59 +1950 1 18 0 12 OSCAR 45.1 148.2 20 522 +1992 8 9 6 20 RAFAEL 41.0 110.8 29 749 +2004 7 13 0 14 ISAAC 31.4 222.7 146 807 +2002 1 15 12 23 JOYCE 66.1 323.9 39 425 +2003 5 3 18 1 SANDY 39.5 101.9 105 807 +1957 6 6 0 19 SANDY 33.4 345.1 63 538 +1974 4 24 6 25 TONY 15.1 185.5 92 323 +1981 7 7 6 20 JOYCE 12.6 128.5 122 632 +1962 3 13 0 4 RAFAEL 10.9 251.6 87 415 +1952 6 16 18 19 GORDON 14.9 244.1 152 683 +1971 9 27 18 14 RAFAEL 11.8 39.6 43 714 +1989 5 17 12 22 NADINE 43.4 273.1 67 99 +1976 4 6 12 24 VALERIE 65.3 1.8 49 558 +1994 11 5 18 23 MICHAEL 10.7 344.5 121 272 +1978 9 22 18 14 MICHAEL 42.0 155.5 43 628 +1970 11 26 12 14 JOYCE 32.3 351.9 48 73 +1957 6 3 12 7 NADINE 31.2 313.6 55 66 +1961 2 6 12 10 LESLIE 62.5 314.5 32 125 +1997 2 3 18 7 WILLIAM 60.5 189.7 115 814 +1991 2 3 6 26 CHRIS 63.8 154.6 38 80 +1976 9 27 0 17 MICHAEL 55.9 24.4 11 578 +1994 9 16 12 28 BERYL 44.5 76.2 160 661 +1988 12 25 6 17 OSCAR 42.7 284.0 66 301 +1955 2 10 18 10 WILLIAM 68.2 236.6 76 101 +1976 2 8 0 4 HELENE 46.0 356.1 35 314 +1996 6 2 18 6 ALBERTO 35.2 328.5 116 239 +2003 9 7 6 22 GORDON 69.1 321.2 17 393 +1987 7 8 18 12 KIRK 52.8 275.5 44 586 +1985 11 24 6 21 WILLIAM 47.1 35.9 134 872 +1978 8 9 0 18 PATTY 23.0 237.3 75 206 +1971 7 13 6 14 BERYL 21.5 276.6 152 268 +1978 7 24 0 2 PATTY 46.4 124.8 130 801 +1978 7 9 6 16 KIRK 47.6 104.2 74 417 +1960 6 2 12 17 PATTY 64.1 324.9 134 479 +2004 4 5 12 21 LESLIE 18.1 336.0 62 247 +1973 3 4 6 27 DEBBY 63.8 258.3 37 462 +1957 5 17 6 3 RAFAEL 29.7 306.7 18 850 +1988 2 13 6 6 FLORENCE 26.0 181.1 67 780 +1972 10 5 6 1 LESLIE 20.4 355.0 161 677 +1985 6 22 6 18 WILLIAM 58.7 149.7 68 750 +1990 5 1 0 12 BERYL 15.7 282.9 152 504 +2002 5 1 18 9 VALERIE 47.5 351.3 136 47 +1979 10 15 12 25 JOYCE 27.8 32.1 144 89 +1983 12 12 18 20 ALBERTO 16.1 105.5 147 164 +1957 3 9 12 17 SANDY 12.1 288.9 79 659 +1953 10 23 18 6 ALBERTO 59.9 176.7 28 563 +1951 9 3 12 13 HELENE 67.5 85.2 50 851 +2004 1 6 12 20 HELENE 66.6 307.0 121 816 +1988 4 10 0 15 NADINE 15.9 242.0 38 83 +2003 11 25 12 14 HELENE 54.8 59.0 164 86 +1953 6 3 0 13 KIRK 15.9 298.6 15 710 +2003 10 9 12 5 GORDON 14.6 212.1 29 23 +1964 11 17 18 18 OSCAR 28.4 129.4 147 37 +1990 8 27 0 14 HELENE 9.8 135.3 36 701 +1961 6 25 6 23 TONY 28.7 194.7 114 377 +1978 9 17 12 28 ERNESTO 46.8 309.8 83 486 +1995 4 4 0 15 SANDY 59.7 24.9 27 102 +1988 5 2 18 18 ALBERTO 68.4 198.5 149 791 +1962 10 28 6 17 NADINE 14.2 105.6 98 830 +1977 5 24 12 3 RAFAEL 34.6 334.3 121 832 +1965 7 12 12 4 DEBBY 65.1 306.4 32 562 +1986 4 13 0 23 PATTY 46.1 55.6 64 665 +2004 11 15 18 17 HELENE 52.9 213.9 62 280 +1982 11 20 0 12 SANDY 20.3 153.6 45 427 +1972 8 4 6 26 OSCAR 12.8 232.3 31 192 +1999 8 24 6 10 MICHAEL 17.3 81.7 148 864 +1963 8 1 6 19 CHRIS 30.1 140.4 14 661 +1956 4 11 6 4 HELENE 11.9 278.1 138 852 +1956 4 17 12 1 DEBBY 13.3 51.9 42 513 +1952 6 18 0 14 VALERIE 12.7 259.7 146 797 +1981 7 25 6 24 FLORENCE 40.3 294.8 65 172 +1980 1 13 6 4 GORDON 26.6 113.0 21 502 +1968 9 26 0 24 FLORENCE 39.5 123.9 35 418 +1957 5 18 18 6 CHRIS 51.0 32.0 86 18 +1984 7 26 12 3 ERNESTO 42.2 218.4 31 339 +1971 2 10 6 20 LESLIE 14.5 348.5 94 721 +1994 10 1 18 26 VALERIE 68.9 183.3 30 631 +1974 9 25 12 27 FLORENCE 58.1 258.0 155 713 +1978 2 28 0 11 VALERIE 22.4 144.3 60 591 +1956 11 22 12 1 LESLIE 8.8 280.6 82 364 +1968 3 9 0 18 ERNESTO 14.3 153.0 71 578 +1957 3 26 18 20 LESLIE 62.7 43.9 112 441 +1961 10 5 18 16 PATTY 40.7 146.6 18 803 +2001 4 5 12 5 GORDON 40.9 68.5 21 518 +1975 11 7 6 3 GORDON 38.6 216.6 117 433 +1998 12 28 12 24 KIRK 8.8 80.0 47 232 +1999 6 10 0 4 HELENE 42.2 244.7 86 466 +1954 5 11 6 4 ALBERTO 53.3 69.9 108 776 +2004 11 2 18 28 BERYL 49.9 342.1 124 369 +1983 1 14 12 14 ISAAC 59.4 278.7 134 45 +1969 8 24 12 26 TONY 45.8 344.3 43 581 +1991 7 16 0 24 OSCAR 23.2 195.6 112 735 +1996 2 16 12 17 PATTY 11.5 91.7 31 548 +2004 12 13 6 24 FLORENCE 19.6 262.1 71 759 +2004 11 2 0 21 MICHAEL 38.4 156.8 102 138 +1997 4 9 6 15 TONY 35.2 350.0 64 243 +1953 9 20 6 7 ISAAC 14.3 216.2 141 698 +1959 8 20 0 18 SANDY 46.9 200.1 38 156 +1992 12 2 0 10 GORDON 42.5 329.3 110 769 +1950 8 23 6 1 ISAAC 32.1 37.0 163 11 +1967 7 12 0 3 FLORENCE 20.4 229.3 62 624 +1973 7 22 18 10 ISAAC 49.5 15.6 27 439 +1980 10 11 18 9 OSCAR 48.9 42.8 150 426 +1963 11 26 6 8 RAFAEL 61.7 72.7 152 276 +1984 4 25 6 27 GORDON 33.1 265.7 161 603 +1996 3 18 12 25 TONY 47.0 45.9 107 672 +1972 5 28 0 28 DEBBY 26.0 93.9 49 63 +1952 1 16 6 4 HELENE 67.3 187.2 80 870 +1958 12 5 6 14 LESLIE 55.8 218.3 56 699 +1963 11 22 18 8 GORDON 66.9 346.2 39 895 +1957 4 25 12 10 FLORENCE 56.8 167.7 86 208 +1997 1 15 6 18 PATTY 54.6 323.8 127 426 +1954 1 9 12 7 JOYCE 26.0 126.9 103 607 +1986 7 18 0 8 KIRK 42.0 196.3 152 865 +1998 12 17 18 10 ALBERTO 13.7 201.0 156 625 +1980 3 26 18 25 SANDY 16.5 343.9 30 521 +1957 12 22 0 3 SANDY 27.2 340.9 28 123 +1954 8 19 0 26 CHRIS 43.3 148.9 81 750 +1965 6 25 18 26 SANDY 63.4 84.1 162 712 +1977 8 7 18 19 WILLIAM 17.8 335.1 143 796 +1956 9 12 18 24 PATTY 48.7 152.1 27 463 +1981 12 25 18 18 PATTY 37.8 66.0 145 327 +1986 1 11 18 15 HELENE 60.9 133.6 141 536 +1988 8 2 12 6 ISAAC 53.6 230.9 22 233 +1973 9 16 18 14 NADINE 44.3 85.5 79 287 +1952 6 23 18 13 NADINE 27.6 331.0 36 169 +1950 4 20 6 1 GORDON 68.4 235.6 45 871 +1951 2 26 12 22 CHRIS 39.2 8.1 25 808 +1978 10 10 18 11 FLORENCE 60.4 31.5 32 531 +1982 3 3 12 8 RAFAEL 10.9 188.1 34 407 +1970 1 19 0 25 RAFAEL 60.1 136.5 136 76 +1971 11 28 0 27 JOYCE 11.1 35.7 36 336 +1965 6 5 6 12 NADINE 32.1 42.3 130 216 +1994 2 16 12 24 CHRIS 66.7 334.0 77 418 +1977 10 22 6 5 SANDY 27.8 15.4 14 614 +1964 7 7 6 14 PATTY 31.4 56.2 127 856 +1997 2 2 18 3 DEBBY 20.0 184.7 132 292 +1974 5 12 18 23 CHRIS 46.0 6.8 25 460 +1954 10 26 18 22 LESLIE 41.7 228.4 130 113 +1986 1 8 18 28 PATTY 18.9 347.0 102 841 +1994 12 9 6 24 ISAAC 64.0 175.5 70 411 +1968 6 4 12 19 MICHAEL 26.3 50.6 47 605 +1953 8 9 6 6 NADINE 36.2 238.1 25 761 +1966 8 21 6 19 FLORENCE 42.5 285.6 113 485 +1973 1 19 0 4 LESLIE 50.8 205.2 18 411 +1993 11 20 12 10 NADINE 48.1 27.1 100 299 +1963 4 3 6 20 SANDY 57.7 39.3 14 467 +2004 11 25 6 25 ERNESTO 66.4 77.2 76 223 +1994 8 17 12 4 OSCAR 9.3 185.1 32 894 +1999 6 19 12 24 MICHAEL 54.5 297.4 134 297 +1974 6 10 18 2 ISAAC 37.2 63.2 15 326 +1966 8 24 6 28 CHRIS 25.3 131.9 12 174 +1979 3 2 6 17 GORDON 19.5 323.2 39 704 +1960 3 19 0 22 WILLIAM 8.6 128.3 158 337 +1998 8 24 18 21 ISAAC 26.1 294.5 10 826 +1964 10 20 0 10 SANDY 58.9 310.2 59 607 +1999 9 23 6 15 RAFAEL 50.4 273.5 135 622 +1952 4 8 0 12 LESLIE 40.2 122.3 82 575 +1962 2 14 0 17 OSCAR 31.6 240.2 33 496 +1992 7 27 12 17 MICHAEL 53.5 111.7 35 234 +1959 1 20 18 3 ALBERTO 68.9 202.0 119 458 +1956 12 6 0 10 ERNESTO 46.3 118.0 25 732 +1995 12 11 18 11 ERNESTO 50.9 351.9 146 511 +1963 9 12 12 5 GORDON 9.6 129.7 136 150 +1993 8 9 6 20 MICHAEL 9.1 113.9 103 181 +1953 8 21 12 28 CHRIS 13.9 179.5 93 707 +1959 11 22 6 12 HELENE 41.6 47.6 113 682 +1978 9 17 12 25 BERYL 7.3 203.0 40 840 +1993 10 17 6 23 ERNESTO 37.3 354.1 163 603 +1953 3 5 0 19 NADINE 10.5 113.5 88 607 +1968 3 21 6 23 RAFAEL 67.2 262.0 119 771 +1975 12 22 6 9 ERNESTO 9.5 135.4 30 317 +1951 4 19 18 3 ALBERTO 50.7 1.1 132 866 +1964 7 20 18 9 DEBBY 14.8 258.7 81 725 +1956 9 3 18 26 VALERIE 35.6 81.9 108 865 +1964 9 25 18 23 DEBBY 18.7 52.7 159 514 +1964 3 9 12 27 WILLIAM 14.0 79.5 133 268 +1960 11 15 6 10 RAFAEL 12.4 204.4 80 194 +1999 9 4 0 25 BERYL 61.1 90.8 67 858 +1994 4 6 6 9 ERNESTO 34.8 37.7 103 566 +2001 10 16 0 5 CHRIS 15.4 113.1 85 363 +1954 11 18 0 6 BERYL 25.2 114.9 117 665 +1961 10 8 0 10 NADINE 16.8 129.9 26 531 +1972 9 11 18 2 BERYL 48.1 241.8 45 0 +1997 2 24 12 2 LESLIE 17.1 118.6 91 814 +1956 12 24 0 22 ALBERTO 45.1 307.4 145 662 +2002 9 5 6 6 ISAAC 26.7 273.7 69 536 +1988 10 17 0 4 KIRK 20.3 198.5 99 857 +1996 4 4 18 6 ALBERTO 43.7 33.3 93 166 +1999 3 6 18 16 CHRIS 57.6 80.6 145 571 +1993 5 20 18 3 OSCAR 65.1 317.8 140 812 +1983 3 16 18 17 VALERIE 27.1 139.9 114 730 +1983 7 5 12 2 GORDON 10.9 339.2 121 705 +1990 2 23 18 10 DEBBY 16.3 286.9 52 128 +1990 12 9 12 15 FLORENCE 33.6 333.2 10 546 +1967 5 15 18 6 JOYCE 53.2 237.2 49 637 +1967 9 9 6 16 GORDON 38.5 111.2 132 88 +1970 11 13 6 8 JOYCE 33.0 27.9 54 52 +1963 4 2 18 19 FLORENCE 7.6 167.6 118 602 +1975 2 10 0 15 MICHAEL 56.3 87.1 37 308 +1978 7 8 12 25 RAFAEL 15.1 37.3 56 459 +1971 1 16 6 1 PATTY 26.1 133.7 155 687 +1977 8 3 6 20 KIRK 21.0 164.9 136 752 +1956 1 1 18 21 FLORENCE 68.0 29.3 95 792 +1999 1 24 12 22 TONY 28.6 323.5 100 520 +1959 2 12 6 14 KIRK 38.1 329.4 34 757 +1969 6 4 0 3 ALBERTO 44.4 295.3 56 405 +1994 8 20 12 19 VALERIE 31.4 355.6 45 41 +1955 2 1 0 7 OSCAR 29.8 90.9 46 470 +1954 12 11 18 3 ERNESTO 19.0 254.0 28 9 +1984 8 9 6 10 CHRIS 45.8 330.6 143 889 +1965 10 17 12 3 ALBERTO 66.1 216.3 132 188 +1958 3 24 0 26 RAFAEL 43.7 189.8 59 441 +1964 4 14 6 23 MICHAEL 63.1 299.6 90 309 +1954 8 20 18 6 MICHAEL 59.9 281.2 81 588 +1993 6 17 12 20 SANDY 18.3 144.3 151 107 +1976 3 16 12 18 PATTY 37.9 49.2 161 478 +1956 6 19 18 17 JOYCE 44.4 349.7 28 195 +1951 12 22 6 5 ALBERTO 39.9 122.9 26 377 +1963 5 4 12 28 KIRK 31.9 189.0 56 447 +1986 6 22 0 14 BERYL 51.8 343.5 90 13 +1971 11 13 12 3 RAFAEL 23.4 294.5 122 831 +1959 8 27 18 23 TONY 30.2 136.5 131 67 +2004 12 1 18 13 OSCAR 16.1 203.8 39 251 +1972 5 4 12 28 SANDY 14.6 108.0 51 534 +1979 11 10 12 19 VALERIE 17.5 139.3 141 567 +1954 5 11 12 10 BERYL 51.5 343.0 71 103 +1974 7 12 12 23 LESLIE 58.9 272.2 49 734 +1960 4 7 6 6 OSCAR 20.9 56.2 13 200 +1992 3 28 6 16 DEBBY 47.5 152.1 16 33 +1963 8 9 12 9 RAFAEL 48.9 172.3 81 741 +1959 12 28 18 19 DEBBY 16.5 74.4 39 718 +1988 1 28 6 8 CHRIS 10.7 23.0 67 699 +1974 8 14 0 11 DEBBY 58.0 183.9 42 357 +1975 7 18 18 22 MICHAEL 24.1 116.9 81 197 +1957 3 27 12 9 OSCAR 29.0 211.1 125 39 +2001 2 8 12 27 SANDY 63.7 24.1 109 745 +1998 1 26 0 10 OSCAR 64.2 150.7 10 216 +1992 2 13 12 5 BERYL 12.1 261.0 90 656 +1979 9 13 18 17 HELENE 51.6 203.4 88 181 +1971 9 15 18 21 LESLIE 65.5 84.1 36 452 +1988 7 23 18 20 RAFAEL 15.5 248.0 77 819 +1997 7 7 12 9 VALERIE 31.4 86.9 32 300 +1968 8 3 0 13 GORDON 68.6 178.7 109 387 +1962 12 2 0 8 KIRK 34.1 195.1 12 249 +1974 11 26 18 5 JOYCE 64.6 348.2 66 376 +2003 1 10 18 23 SANDY 36.2 23.2 55 664 +1981 5 14 18 7 NADINE 22.4 241.1 139 379 +1978 4 28 18 10 ALBERTO 10.3 355.4 55 234 +1954 11 27 0 15 ERNESTO 31.4 27.7 81 145 +1998 12 19 12 2 DEBBY 46.1 184.9 126 459 +1978 5 12 0 6 RAFAEL 69.7 206.1 106 252 +1997 1 1 6 7 SANDY 58.1 278.4 108 88 +1977 5 1 12 14 JOYCE 12.7 314.4 134 714 +1958 4 3 12 8 FLORENCE 20.6 187.8 161 265 +1960 11 7 18 21 SANDY 35.6 137.0 88 341 +1955 12 28 6 24 FLORENCE 50.8 325.0 107 75 +1976 4 6 0 6 VALERIE 69.0 261.9 119 651 +1983 2 16 0 18 MICHAEL 26.9 268.9 63 880 +1986 11 12 6 8 FLORENCE 55.9 254.1 145 458 +1971 2 5 18 10 ISAAC 36.7 346.9 22 857 +1998 12 16 0 25 PATTY 64.0 261.0 62 352 +1963 5 5 6 8 PATTY 35.2 245.7 47 734 +1969 1 28 12 7 OSCAR 67.4 158.3 137 633 +1962 2 20 12 2 DEBBY 15.4 301.9 118 306 +1979 6 17 18 26 WILLIAM 36.3 156.4 19 424 +1968 1 14 18 16 SANDY 38.8 32.9 32 173 +1997 10 24 0 28 SANDY 47.5 347.0 107 880 +1957 3 24 18 1 ALBERTO 8.3 266.8 44 520 +1968 10 22 0 9 JOYCE 15.6 305.9 13 148 +1997 6 6 6 21 HELENE 14.7 296.5 107 76 +1973 12 27 0 16 VALERIE 23.2 325.4 123 570 +1959 9 5 12 14 ALBERTO 49.6 351.1 74 651 +1994 10 9 6 14 KIRK 27.2 10.0 92 819 +1970 7 3 6 12 MICHAEL 15.4 163.8 48 446 +1990 3 14 6 10 SANDY 27.3 14.5 14 215 +2004 1 13 6 25 FLORENCE 18.8 186.7 31 363 +1999 4 17 0 7 BERYL 35.4 296.7 43 867 +1988 6 11 0 7 LESLIE 29.2 50.5 45 6 +1950 10 22 12 12 BERYL 26.6 95.6 79 828 +1973 2 9 0 7 JOYCE 13.6 272.4 103 653 +1981 1 18 6 10 WILLIAM 69.9 309.5 135 514 +1980 5 13 0 7 LESLIE 13.6 152.1 115 786 +1953 10 23 0 16 HELENE 62.1 190.0 122 776 +1980 5 20 18 10 PATTY 56.3 267.9 89 416 +1975 2 22 18 18 RAFAEL 45.5 100.9 85 395 +1991 5 3 6 27 OSCAR 63.7 151.2 108 232 +2003 3 25 18 28 ISAAC 54.5 267.3 16 779 +1960 4 23 18 16 JOYCE 58.7 197.1 83 119 +1989 12 22 18 24 KIRK 67.8 66.7 130 551 +1987 1 10 6 2 LESLIE 10.2 53.3 114 774 +1966 10 12 0 19 DEBBY 68.3 204.5 92 163 +2002 9 18 12 24 OSCAR 62.2 182.4 16 95 +1966 5 4 6 15 RAFAEL 12.1 289.0 145 490 +1997 9 10 18 21 HELENE 56.5 297.4 148 594 +1980 6 18 0 12 MICHAEL 14.7 273.2 72 51 +1970 6 21 6 24 NADINE 10.7 219.5 99 209 +1955 9 24 12 16 WILLIAM 69.1 304.5 74 256 +1956 9 26 6 20 RAFAEL 45.0 355.7 33 265 +2002 7 16 0 28 KIRK 36.0 207.1 62 248 +1993 11 18 6 2 PATTY 59.1 55.4 164 158 +1991 4 8 0 6 DEBBY 20.1 264.7 102 744 +1954 11 16 18 5 LESLIE 56.6 347.2 61 532 +1969 1 6 12 16 NADINE 19.0 189.1 114 460 +1973 9 9 18 6 RAFAEL 10.6 259.2 100 831 +1982 2 25 6 11 BERYL 11.7 116.5 33 333 +1959 10 20 6 27 VALERIE 38.2 82.2 20 763 +1992 3 15 0 17 PATTY 44.8 58.0 35 868 +1957 3 3 0 1 OSCAR 35.6 212.8 126 610 +2003 9 3 6 18 KIRK 48.0 128.3 13 881 +1976 12 17 0 23 LESLIE 16.5 284.0 96 103 +1997 4 18 0 13 CHRIS 46.5 51.1 159 559 +2001 7 19 18 25 LESLIE 58.4 104.6 19 119 +1961 12 24 18 18 LESLIE 7.8 347.4 157 372 +1963 9 9 12 26 LESLIE 57.1 21.7 106 316 +1965 5 24 6 10 NADINE 53.0 303.6 88 746 +1994 9 12 0 13 NADINE 52.1 122.3 74 483 +1980 10 25 6 21 OSCAR 59.2 148.8 32 557 +1976 12 4 18 4 PATTY 53.0 315.1 60 761 +1979 9 3 0 17 FLORENCE 16.0 180.0 118 659 +1955 12 17 0 24 KIRK 50.8 97.7 162 790 +1971 6 3 18 19 ISAAC 48.2 210.7 130 34 +1996 12 25 12 24 ERNESTO 66.3 220.8 78 645 +1964 1 20 0 22 CHRIS 62.3 203.5 40 435 +1994 7 4 12 17 SANDY 51.5 22.4 124 333 +1999 3 1 6 21 LESLIE 36.2 4.9 102 475 +1997 8 7 12 17 BERYL 21.1 118.4 18 262 +2002 7 19 6 20 HELENE 19.0 298.7 82 690 +1988 10 24 0 8 OSCAR 63.0 11.5 44 600 +1995 12 9 6 4 OSCAR 35.3 98.8 113 883 +1985 7 14 18 14 HELENE 34.1 268.1 101 53 +1961 11 2 18 21 SANDY 21.8 348.5 119 413 +2002 8 8 12 22 SANDY 26.1 207.2 140 602 +1984 3 22 6 23 MICHAEL 19.8 275.4 53 547 +1980 6 27 0 5 JOYCE 68.0 288.2 143 603 +1986 6 14 0 5 JOYCE 56.7 352.4 129 374 +2000 9 25 18 28 OSCAR 29.3 38.2 66 163 +2004 1 18 12 5 PATTY 70.0 136.3 111 463 +1951 7 16 0 15 CHRIS 61.7 150.2 116 824 +1990 2 27 12 11 HELENE 44.8 288.5 92 829 +1952 6 21 6 12 VALERIE 29.4 62.8 146 320 +1987 10 11 0 28 WILLIAM 68.2 57.1 142 272 +2003 7 7 18 1 CHRIS 64.2 260.0 17 300 +1971 2 12 18 25 VALERIE 12.7 184.6 94 464 +1980 6 8 18 9 CHRIS 23.3 6.8 46 366 +1979 4 14 6 9 JOYCE 7.8 146.5 160 323 +1966 8 12 0 21 SANDY 47.1 356.5 38 730 +1987 10 18 6 16 SANDY 10.0 46.6 123 378 +2001 12 8 0 25 ERNESTO 28.7 212.5 10 439 +2001 2 22 6 26 TONY 60.2 229.2 87 660 +1980 10 22 12 11 DEBBY 57.2 172.4 79 847 +2001 5 8 12 8 HELENE 31.4 142.2 114 111 +1995 8 28 18 21 OSCAR 49.3 259.7 136 321 +1965 4 18 12 13 NADINE 66.5 23.3 43 624 +1954 1 28 18 8 CHRIS 43.6 68.9 63 210 +1962 6 27 12 19 ISAAC 53.5 248.2 161 812 +1995 11 17 18 8 LESLIE 43.6 249.2 11 274 +1984 3 28 0 25 HELENE 21.3 141.6 119 763 +1971 11 26 18 23 WILLIAM 23.9 336.5 126 103 +2000 5 24 12 4 SANDY 9.9 190.2 10 446 +1979 9 11 6 15 ERNESTO 48.6 117.9 125 157 +1958 12 19 0 16 BERYL 30.4 128.2 124 293 +1971 5 23 0 20 LESLIE 15.7 112.6 80 178 +1993 7 23 6 17 ERNESTO 16.6 19.4 127 676 +1985 2 15 6 13 GORDON 67.8 58.5 115 433 +1991 7 2 18 28 HELENE 8.3 146.5 100 248 +1983 11 14 18 8 GORDON 43.2 278.9 140 36 +1985 2 7 6 10 OSCAR 47.9 265.9 149 827 +1960 11 26 6 7 DEBBY 46.9 97.1 63 522 +1969 7 10 12 8 TONY 36.1 78.1 26 131 +1987 10 25 12 18 RAFAEL 58.3 113.4 67 341 +1950 3 18 6 26 SANDY 63.9 2.4 58 801 +1970 6 20 18 23 OSCAR 9.0 27.8 163 568 +1981 12 8 18 10 NADINE 55.0 187.9 16 66 +1954 2 3 18 7 DEBBY 18.0 48.9 105 544 +1976 3 17 6 27 BERYL 21.3 10.8 102 692 +1981 11 25 0 1 ALBERTO 18.6 329.4 97 801 +2000 10 10 0 26 TONY 58.4 139.5 83 817 +1966 6 13 12 2 OSCAR 24.8 72.7 132 228 +1974 1 3 18 15 KIRK 15.6 350.7 127 601 +2002 6 17 12 15 LESLIE 46.4 260.4 72 118 +1995 8 12 12 27 MICHAEL 42.7 293.2 146 887 +1959 2 24 0 20 NADINE 21.7 84.0 75 364 +1965 10 20 12 22 CHRIS 20.6 45.6 59 397 +2000 9 28 0 6 PATTY 33.7 291.0 147 329 +1989 1 5 6 19 RAFAEL 52.8 332.5 58 259 +1951 6 27 0 25 SANDY 26.5 152.3 72 109 +1956 9 4 0 8 ALBERTO 60.3 185.7 140 395 +1958 3 23 0 16 OSCAR 22.1 315.9 114 222 +1996 7 27 6 13 OSCAR 62.0 84.4 92 585 +1959 12 9 18 10 MICHAEL 60.6 22.9 98 833 +1961 4 10 12 26 ISAAC 52.1 108.1 80 824 +1991 2 19 18 24 HELENE 9.8 47.5 112 500 +1998 8 21 18 13 RAFAEL 51.4 45.7 91 276 +1969 1 19 12 4 ISAAC 60.8 59.2 15 854 +1963 1 16 0 26 ALBERTO 30.0 284.2 42 508 +1994 10 23 0 11 ISAAC 51.7 128.9 15 201 +1978 3 10 18 19 GORDON 15.4 245.5 135 555 +1990 12 26 6 17 LESLIE 49.9 336.4 145 427 +1972 2 25 0 9 PATTY 56.0 75.7 42 552 +1972 6 12 12 11 LESLIE 41.0 37.8 54 313 +1987 4 11 12 20 SANDY 17.4 127.3 73 615 +1989 9 5 12 28 KIRK 19.8 183.4 17 244 +1958 4 21 0 26 KIRK 50.4 153.5 101 812 +1987 3 11 12 28 JOYCE 25.2 178.7 96 411 +1972 8 24 18 9 LESLIE 69.0 180.3 21 6 +2000 7 10 6 7 BERYL 25.8 258.7 152 791 +1971 5 15 0 22 GORDON 41.7 5.7 12 64 +1983 6 8 6 25 SANDY 58.8 167.6 130 639 +1982 5 1 12 13 WILLIAM 39.7 270.7 135 340 +1980 8 4 18 15 NADINE 48.1 150.6 132 678 +2002 4 3 18 4 KIRK 32.8 320.8 16 320 +1955 9 1 0 24 KIRK 9.8 170.7 92 542 +1991 6 10 12 8 TONY 35.0 184.6 68 679 +1965 5 9 18 28 TONY 47.1 203.9 82 195 +1971 9 27 6 16 CHRIS 66.1 141.2 153 808 +1951 6 23 18 25 DEBBY 51.9 265.9 60 294 +1963 3 7 12 12 BERYL 29.3 31.4 109 679 +1986 5 15 0 2 FLORENCE 59.6 355.7 133 173 +1960 2 21 0 25 RAFAEL 41.6 119.2 87 628 +1960 3 9 18 10 CHRIS 55.1 128.4 138 755 +1970 9 24 12 8 PATTY 42.4 234.7 23 824 +1988 8 16 6 1 HELENE 23.8 188.7 113 755 +1953 7 28 6 16 MICHAEL 30.9 106.2 14 831 +1956 12 12 18 8 ISAAC 10.8 356.5 29 592 +1976 2 10 12 16 PATTY 21.2 209.1 40 527 +1959 2 28 0 3 NADINE 38.8 223.5 162 685 +1981 4 21 18 19 MICHAEL 32.3 75.1 136 97 +1960 6 13 6 7 JOYCE 23.7 28.5 26 476 +1993 8 10 0 23 OSCAR 38.8 100.7 76 519 +1996 6 6 12 23 GORDON 66.3 108.1 157 25 +1993 3 9 12 27 WILLIAM 21.5 210.9 98 88 +1989 10 3 0 11 RAFAEL 59.0 266.6 105 886 +1998 2 19 0 6 TONY 30.6 293.4 20 243 +1983 10 25 18 25 HELENE 61.8 150.9 17 804 +1965 9 1 0 21 JOYCE 53.1 139.9 20 744 +1997 12 14 6 25 RAFAEL 61.2 191.2 29 313 +2000 8 22 18 13 ISAAC 67.3 20.9 142 358 +1973 1 25 6 17 KIRK 39.7 253.4 136 45 +1957 4 23 6 25 LESLIE 68.6 92.7 120 397 +1996 10 15 0 6 SANDY 20.5 293.3 91 380 +1961 3 5 18 19 PATTY 31.4 27.8 45 265 +1995 11 20 6 28 CHRIS 52.1 183.9 106 346 +1982 10 14 18 5 WILLIAM 16.2 246.2 23 338 +1961 8 25 18 7 ALBERTO 50.2 76.6 94 769 +1968 10 7 6 22 ERNESTO 66.3 301.5 120 486 +1978 4 21 6 19 ALBERTO 57.0 207.7 123 115 +1972 6 11 6 22 ISAAC 28.4 191.4 101 500 +2002 2 26 12 10 CHRIS 66.8 206.4 18 51 +1975 4 16 6 16 PATTY 68.4 52.6 128 389 +1981 6 7 18 26 MICHAEL 46.7 254.0 152 214 +1970 2 22 18 27 JOYCE 40.5 94.1 20 319 +2002 12 14 6 3 ISAAC 58.9 303.1 124 183 +1995 9 6 18 6 CHRIS 43.8 328.4 148 614 +1950 6 9 0 11 SANDY 58.2 123.7 150 437 +1988 1 8 18 6 PATTY 22.6 232.4 54 814 +1999 6 15 12 13 ERNESTO 54.9 186.3 40 764 +1987 9 13 0 11 CHRIS 18.1 71.9 38 314 +1950 7 7 0 19 WILLIAM 53.6 220.4 39 826 +1985 5 3 18 2 KIRK 17.5 235.5 34 693 +1950 12 6 12 12 ERNESTO 56.3 188.6 95 784 +1968 7 18 6 12 ERNESTO 20.9 200.4 45 821 +1994 9 25 18 5 PATTY 7.7 336.4 115 517 +1983 12 6 0 19 HELENE 56.9 129.8 15 354 +1993 11 8 6 9 ERNESTO 47.6 137.5 41 743 +1989 8 1 18 1 GORDON 53.8 142.7 59 608 +1993 7 23 12 8 MICHAEL 59.5 81.2 151 555 +1972 6 8 12 13 GORDON 53.1 229.1 134 237 +1979 11 20 12 1 SANDY 66.6 144.5 70 742 +1980 12 16 6 24 OSCAR 26.3 79.7 56 439 +1966 10 10 0 15 GORDON 34.1 303.1 44 122 +1958 8 18 0 9 ISAAC 17.9 204.7 70 309 +1982 6 8 6 22 BERYL 27.9 284.3 155 174 +1960 8 25 18 5 MICHAEL 16.6 180.3 130 797 +1960 4 4 0 5 OSCAR 56.0 26.5 118 46 +1955 2 19 6 21 SANDY 16.0 124.6 23 854 +1984 10 21 12 13 SANDY 14.6 107.5 92 597 +1962 1 9 12 7 TONY 17.7 42.0 105 646 +1962 9 21 6 2 ALBERTO 47.1 80.3 143 686 +1969 4 5 12 19 GORDON 39.2 91.4 19 501 +1974 12 9 18 3 SANDY 43.1 149.3 97 642 +1951 10 17 0 13 ALBERTO 29.4 274.8 91 434 +1956 4 23 0 8 ISAAC 65.5 286.4 82 574 +1983 6 7 12 24 LESLIE 52.6 173.9 45 577 +1955 2 12 12 24 ALBERTO 11.3 247.0 157 388 +1961 10 1 0 11 ERNESTO 66.2 159.3 128 809 +1963 12 16 12 5 VALERIE 20.6 326.7 55 406 +1969 10 23 12 10 ERNESTO 55.0 264.4 129 51 +2004 9 8 6 18 ISAAC 8.0 224.7 78 296 +1971 1 27 6 15 CHRIS 36.4 76.9 49 449 +1999 6 4 6 1 HELENE 52.2 115.5 71 483 +1997 12 6 6 25 SANDY 64.3 208.9 116 428 +1999 7 9 18 21 ALBERTO 30.8 121.2 16 811 +2002 6 4 12 13 RAFAEL 42.6 211.6 153 471 +1959 4 19 18 4 DEBBY 56.4 298.6 99 544 +1976 4 17 0 20 LESLIE 11.1 105.3 50 828 +1978 1 26 18 12 ISAAC 17.8 154.3 115 82 +1968 11 1 12 7 KIRK 7.4 271.5 108 356 +1977 5 1 0 12 MICHAEL 18.4 27.4 42 858 +1955 11 7 18 20 FLORENCE 23.5 79.3 145 165 +1977 11 6 6 18 SANDY 54.2 205.3 112 408 +1984 12 9 0 14 VALERIE 27.3 3.0 67 296 +1965 2 6 6 16 JOYCE 8.9 184.6 13 701 +1994 3 21 6 2 DEBBY 29.4 174.4 15 243 +1958 6 26 12 11 TONY 46.9 336.0 30 294 +1969 4 22 6 19 BERYL 68.8 276.4 41 157 +1989 7 24 0 1 RAFAEL 54.5 280.3 84 62 +1990 10 2 6 26 JOYCE 54.5 91.9 87 103 +1999 10 19 6 9 GORDON 24.1 55.4 23 882 +1984 6 20 0 10 KIRK 29.3 122.1 48 721 +1956 4 12 18 24 GORDON 11.9 160.1 118 264 +1956 2 18 6 8 HELENE 45.8 278.9 142 721 +1971 3 2 12 15 JOYCE 47.9 181.4 52 744 +1965 7 22 12 12 JOYCE 48.5 103.7 162 248 +1987 5 20 12 12 SANDY 22.9 180.9 133 768 +1959 8 6 18 24 RAFAEL 19.1 106.3 103 701 +1977 2 17 12 9 FLORENCE 51.2 35.5 118 388 +1996 2 22 18 19 PATTY 56.3 136.3 10 231 +1982 9 13 0 3 VALERIE 53.8 216.3 149 652 +2001 9 4 0 7 RAFAEL 19.4 270.2 55 125 +1981 8 3 6 9 LESLIE 64.8 125.5 41 813 +1957 4 21 18 18 CHRIS 62.7 317.8 143 201 +1996 9 22 18 2 GORDON 37.1 250.2 36 673 +1991 6 12 18 2 MICHAEL 14.0 140.1 154 638 +1990 9 15 12 21 GORDON 9.1 187.2 73 285 +1965 12 9 18 14 FLORENCE 41.1 9.1 23 711 +1983 3 21 0 28 VALERIE 17.6 147.0 130 781 +1991 6 6 18 3 SANDY 29.5 42.7 78 298 +1952 1 21 12 8 WILLIAM 50.9 187.1 106 566 +1968 3 22 18 16 OSCAR 10.1 107.7 17 541 +1985 4 15 18 28 OSCAR 61.3 354.4 138 557 +1977 5 25 12 19 NADINE 25.3 330.4 119 677 +1952 12 5 12 25 KIRK 29.9 187.3 106 265 +1996 4 2 18 17 HELENE 37.0 175.8 49 331 +2003 6 24 18 27 DEBBY 39.3 259.0 159 485 +1969 9 1 0 20 ERNESTO 19.5 257.1 22 857 +1967 5 21 0 7 NADINE 7.7 95.4 94 376 +1971 4 15 6 17 GORDON 20.9 157.7 16 46 +1967 10 3 18 1 OSCAR 30.8 118.7 44 596 +1952 12 28 18 19 TONY 11.1 38.3 65 786 +1953 12 18 12 7 TONY 36.3 223.2 94 457 +1997 6 2 12 11 WILLIAM 34.7 192.8 151 806 +1958 10 14 12 27 RAFAEL 13.9 234.3 107 658 +1955 6 28 18 4 BERYL 28.9 226.2 14 146 +1995 8 10 18 22 OSCAR 43.4 97.7 19 24 +1961 8 11 18 5 KIRK 28.5 145.6 31 791 +1964 10 27 0 7 SANDY 14.8 139.6 150 564 +1968 6 6 6 17 KIRK 15.9 317.7 85 855 +1999 2 10 6 11 GORDON 52.0 182.3 42 97 +1961 1 27 12 16 VALERIE 57.1 89.5 123 587 +1978 10 24 0 17 KIRK 37.7 5.2 121 93 +1993 3 8 0 26 DEBBY 16.8 307.8 67 272 +1954 1 16 6 25 RAFAEL 11.0 340.1 12 588 +1995 1 11 0 13 NADINE 59.3 347.9 162 200 +1991 9 16 12 13 HELENE 47.5 254.0 83 289 +1989 8 18 12 15 GORDON 23.8 312.3 26 850 +1984 11 26 0 19 DEBBY 33.8 88.2 41 156 +1964 6 27 12 17 VALERIE 39.3 71.3 15 862 +1982 8 23 0 17 HELENE 66.5 218.2 88 507 +1989 12 28 0 16 OSCAR 37.6 235.2 108 887 +2002 6 22 18 22 LESLIE 49.5 357.6 66 817 +1975 8 20 12 12 FLORENCE 38.8 217.4 157 108 +1985 10 21 0 17 GORDON 55.1 319.0 80 208 +1976 12 17 18 15 ISAAC 53.9 272.7 26 640 +1982 8 28 18 8 WILLIAM 37.9 313.0 151 96 +1955 1 1 0 14 KIRK 19.5 176.9 141 484 +1994 7 21 12 7 BERYL 43.7 31.9 58 448 +1960 3 18 12 10 VALERIE 20.4 250.3 118 799 +1995 4 15 18 17 GORDON 12.1 11.9 20 577 +1991 12 7 0 26 RAFAEL 69.6 270.3 85 521 +1970 8 1 12 10 TONY 24.0 357.7 161 465 +1967 2 8 18 18 TONY 61.0 205.2 23 464 +2001 1 7 0 6 MICHAEL 14.8 316.9 56 407 +1979 9 11 12 1 ERNESTO 57.2 178.2 127 9 +1989 6 26 12 25 ERNESTO 59.1 335.0 68 118 +1979 8 28 6 2 HELENE 17.6 242.4 68 419 +2004 8 21 18 19 ERNESTO 25.2 248.2 106 6 +1950 10 16 12 15 MICHAEL 22.8 208.2 129 354 +1955 9 13 0 20 ISAAC 68.8 73.5 127 110 +1993 10 20 6 15 JOYCE 31.3 208.4 118 442 +1962 4 25 6 8 NADINE 8.3 95.8 118 898 +1977 4 12 12 23 KIRK 42.2 349.6 124 875 +1955 4 25 18 8 BERYL 47.7 246.2 81 753 +1958 8 7 0 27 OSCAR 29.2 288.3 21 856 +1953 5 27 12 1 CHRIS 7.5 331.0 57 812 +1985 2 1 18 8 FLORENCE 68.6 288.5 113 262 +1970 7 9 18 4 LESLIE 36.0 302.5 74 609 +2003 6 25 12 16 WILLIAM 16.4 348.2 140 275 +1971 6 4 18 9 JOYCE 29.6 169.9 59 717 +1976 6 11 12 16 ISAAC 26.5 307.9 43 150 +1990 9 20 18 24 NADINE 11.0 86.1 106 200 +1990 7 18 18 9 KIRK 53.1 301.7 79 755 +1982 11 28 18 27 ALBERTO 18.7 187.3 133 268 +1953 8 3 18 11 ISAAC 62.6 50.6 60 878 +1966 5 12 18 7 HELENE 9.9 1.6 97 571 +1993 12 13 18 20 PATTY 65.6 8.8 99 18 +1988 11 11 0 16 FLORENCE 33.7 19.0 15 172 +1996 8 16 12 13 KIRK 39.9 107.7 116 695 +1955 7 27 18 1 DEBBY 21.8 58.4 73 369 +1956 5 5 0 27 NADINE 28.4 341.2 110 629 +2000 7 13 0 9 WILLIAM 58.0 34.4 24 672 +1957 5 4 0 18 ERNESTO 46.6 264.1 90 348 +1968 2 11 0 2 NADINE 60.0 95.9 47 781 +1989 9 5 18 18 CHRIS 25.9 293.6 59 276 +1955 1 8 12 19 TONY 26.9 132.1 113 577 +1983 3 24 6 25 FLORENCE 31.3 145.5 37 430 +1961 8 14 18 11 NADINE 23.2 281.6 60 379 +1983 12 1 18 17 JOYCE 61.5 333.9 133 107 +1959 4 28 6 22 MICHAEL 60.0 313.9 150 655 +1983 2 6 12 1 CHRIS 65.6 266.3 60 310 +1991 3 8 12 22 TONY 21.1 52.2 144 341 +1996 3 12 18 16 GORDON 31.9 12.3 157 46 +1971 9 5 0 27 WILLIAM 43.0 230.6 36 897 +1990 9 8 12 17 ISAAC 21.8 147.7 162 774 +2000 6 8 12 18 TONY 48.6 70.8 36 256 +1953 12 18 18 2 RAFAEL 41.9 57.0 44 480 +1959 7 28 0 14 DEBBY 18.7 159.0 137 455 +2001 2 28 12 7 ALBERTO 66.1 216.1 114 891 +1990 5 27 18 5 LESLIE 62.3 172.7 25 80 +1985 9 15 12 3 TONY 46.7 117.0 164 133 +1982 1 27 6 13 MICHAEL 49.9 315.7 120 467 +1972 6 21 12 8 JOYCE 41.5 212.5 34 8 +1982 3 20 12 16 KIRK 65.2 340.4 35 32 +1979 1 20 18 28 LESLIE 29.7 69.7 77 455 +1956 8 27 12 20 OSCAR 26.2 147.0 43 160 +1965 8 28 6 14 NADINE 51.3 65.1 77 695 +1996 8 11 12 11 HELENE 19.8 140.8 117 329 +1990 11 7 0 1 NADINE 32.9 209.2 40 806 +1985 9 28 12 2 LESLIE 56.8 154.3 142 854 +2003 1 25 0 9 DEBBY 11.5 228.9 130 50 +1974 8 5 12 27 LESLIE 44.9 235.2 65 433 +1971 5 14 0 20 MICHAEL 47.7 274.0 136 217 +1995 7 28 6 26 NADINE 61.1 213.2 36 823 +1990 11 1 12 11 HELENE 55.1 321.8 123 550 +1999 2 24 12 5 BERYL 23.7 38.6 30 660 +2001 4 4 6 27 PATTY 52.8 96.4 34 464 +1971 3 24 0 23 PATTY 13.3 309.7 31 511 +1953 5 27 6 12 NADINE 36.0 168.1 125 331 +1952 3 5 18 12 FLORENCE 61.1 245.4 111 575 +1969 1 28 0 27 SANDY 13.1 265.8 12 520 +1950 5 20 0 18 MICHAEL 24.3 154.6 32 522 +1991 10 11 18 1 BERYL 10.5 105.7 21 746 +1971 3 28 18 1 MICHAEL 8.7 161.4 143 112 +1966 3 3 6 10 BERYL 48.5 65.1 96 377 +1991 6 8 6 11 DEBBY 36.2 309.4 111 735 +1969 7 15 0 6 ALBERTO 31.8 252.8 83 782 +1956 6 2 12 24 LESLIE 10.0 343.9 54 423 +1957 9 13 18 28 WILLIAM 33.4 204.4 19 363 +1999 1 28 18 23 OSCAR 61.1 189.5 134 108 +1977 11 26 18 6 FLORENCE 60.4 153.5 93 106 +1971 3 3 0 15 TONY 67.3 312.9 90 180 +1971 2 12 0 12 OSCAR 57.0 81.4 105 464 +1986 1 18 18 8 TONY 22.6 347.1 145 266 +2001 7 12 18 13 BERYL 67.4 312.7 96 119 +1957 2 10 0 12 ERNESTO 20.9 99.5 67 335 +1971 1 14 18 13 VALERIE 67.7 137.6 29 38 +1962 9 10 18 24 HELENE 39.1 174.9 33 625 +1981 5 18 12 11 HELENE 64.1 88.6 69 548 +1985 3 19 18 15 RAFAEL 62.8 5.7 114 735 +1978 7 12 18 23 HELENE 16.1 305.0 114 250 +1968 10 5 12 5 PATTY 36.0 173.0 31 365 +1992 12 11 18 11 CHRIS 43.4 42.5 34 439 +1965 11 21 18 20 BERYL 24.3 70.6 113 886 +1966 6 9 6 23 CHRIS 63.7 296.4 162 2 +1968 11 26 18 4 ISAAC 33.4 202.2 45 536 +1962 1 22 6 11 FLORENCE 23.7 123.0 121 447 +2004 9 26 6 10 KIRK 28.6 84.5 68 827 +1968 5 20 18 12 ERNESTO 66.0 251.0 12 788 +1984 3 6 12 26 SANDY 29.6 141.0 103 524 +1956 7 13 0 7 SANDY 54.8 159.5 60 686 +1980 5 5 18 6 FLORENCE 42.4 143.6 79 354 +2004 10 12 18 28 WILLIAM 45.3 298.3 11 530 +2002 8 1 6 10 HELENE 39.3 23.8 100 326 +1995 1 13 18 26 WILLIAM 59.0 72.4 23 528 +1951 4 12 12 7 JOYCE 36.4 194.5 96 379 +1991 9 10 18 24 LESLIE 57.1 89.8 104 668 +1973 2 9 12 15 SANDY 53.3 81.1 154 49 +1983 5 11 12 2 RAFAEL 67.7 320.2 77 795 +1976 1 10 6 23 ALBERTO 68.6 321.9 84 673 +1996 9 10 0 18 BERYL 16.2 162.1 82 409 +1957 3 17 18 27 WILLIAM 68.7 224.0 141 146 +1983 3 7 0 20 GORDON 24.3 112.3 29 793 +1993 12 24 0 16 WILLIAM 51.1 188.6 144 560 +1953 6 13 0 14 WILLIAM 65.4 317.4 36 435 +1998 2 5 0 9 CHRIS 58.0 7.2 53 784 +1990 10 20 0 28 JOYCE 38.6 109.1 120 897 +1974 12 9 12 20 PATTY 59.4 210.6 15 676 +1964 7 5 18 5 ISAAC 33.6 60.9 148 887 +1995 11 24 6 8 GORDON 18.0 41.9 153 802 +1990 9 23 12 2 DEBBY 8.2 327.5 28 521 +1953 4 16 12 28 ERNESTO 67.8 211.0 17 649 +2002 4 24 0 6 ALBERTO 67.2 297.6 154 484 +1962 8 9 12 19 PATTY 22.4 85.2 104 622 +1975 1 16 6 3 ISAAC 47.7 174.4 93 185 +1978 4 25 18 25 OSCAR 23.2 119.1 67 147 +1981 11 28 0 14 GORDON 51.0 270.3 96 368 +2002 1 24 12 11 VALERIE 68.1 260.5 107 767 +1997 11 25 12 8 OSCAR 31.1 113.7 145 554 +1964 3 7 0 12 HELENE 43.9 270.1 150 543 +1999 8 3 6 4 HELENE 22.3 33.7 76 262 +1993 9 14 6 6 ALBERTO 43.8 61.1 38 242 +1994 12 9 12 15 KIRK 69.7 122.5 152 45 +1999 8 19 18 1 SANDY 29.0 239.8 105 654 +1981 9 14 12 11 TONY 51.2 117.1 34 398 +1992 5 20 18 4 DEBBY 14.9 304.8 128 478 +1986 12 26 6 7 RAFAEL 49.3 52.4 123 832 +1968 10 17 6 27 PATTY 13.8 55.0 57 626 +1980 7 14 18 13 ISAAC 25.5 175.4 86 769 +1973 1 4 12 26 VALERIE 33.6 202.1 140 62 +1971 8 1 18 2 SANDY 26.0 172.6 138 412 +1989 7 5 12 10 KIRK 57.6 226.0 20 759 +2004 3 23 12 14 BERYL 63.7 47.9 60 399 +1967 12 6 12 7 RAFAEL 67.6 21.5 150 126 +1995 4 21 18 7 WILLIAM 25.8 16.7 142 395 +1971 7 26 6 20 JOYCE 53.6 334.9 154 260 +1999 4 22 12 19 DEBBY 7.2 144.5 161 2 +1963 10 4 18 23 JOYCE 48.3 292.6 132 799 +1968 11 13 6 25 TONY 7.3 219.3 149 90 +1953 4 18 12 28 SANDY 46.4 203.3 57 15 +1992 10 25 6 18 ALBERTO 48.8 213.3 109 589 +1965 11 27 6 5 TONY 16.1 97.3 81 27 +1977 3 4 6 3 OSCAR 15.9 55.9 10 293 +1968 7 2 6 4 KIRK 19.8 163.3 164 786 +1950 1 26 6 2 WILLIAM 15.0 185.4 93 467 +1957 12 4 0 17 WILLIAM 38.8 73.2 87 50 +1968 6 11 18 19 LESLIE 20.2 338.2 107 337 +1994 1 16 12 12 TONY 38.2 169.8 94 702 +1978 3 15 6 10 OSCAR 29.6 125.1 58 331 +1950 1 28 12 20 OSCAR 53.6 196.7 105 691 +1981 12 9 12 5 GORDON 67.6 59.9 83 249 +1982 7 9 0 5 HELENE 59.8 10.1 138 703 +1997 12 12 12 26 FLORENCE 29.7 354.3 74 53 +1961 5 4 12 15 LESLIE 67.6 261.2 14 893 +1988 7 12 18 26 RAFAEL 62.2 305.0 47 527 +1992 5 22 18 15 DEBBY 27.2 289.3 148 843 +1963 4 18 0 16 CHRIS 15.1 250.0 54 478 +1996 9 6 0 23 CHRIS 20.0 291.0 97 193 +1952 4 15 12 8 MICHAEL 34.1 67.8 54 64 +1990 4 7 18 28 ERNESTO 28.7 281.1 49 515 +1966 3 28 6 16 ALBERTO 18.7 174.8 53 841 +1965 6 12 0 25 FLORENCE 48.6 133.9 46 539 +1959 11 26 0 13 BERYL 12.7 6.0 83 434 +1958 12 7 0 17 KIRK 53.6 350.7 87 486 +1993 6 25 6 9 OSCAR 15.3 317.6 142 280 +1950 12 7 6 7 HELENE 29.9 149.3 103 510 +1994 4 19 6 5 DEBBY 21.6 227.2 70 423 +1980 11 8 6 21 SANDY 62.7 140.7 53 541 +1996 11 10 0 24 HELENE 53.7 307.0 105 529 +1967 9 24 12 17 ISAAC 11.8 60.5 81 892 +1982 10 11 12 26 ERNESTO 41.0 57.3 36 478 +1969 7 2 0 19 HELENE 56.3 85.8 77 41 +2002 1 17 12 5 VALERIE 19.6 319.8 12 651 +1984 2 20 0 26 GORDON 62.0 175.4 73 363 +1978 8 8 12 5 PATTY 60.5 254.9 99 630 +1969 4 7 6 21 KIRK 53.4 265.3 99 579 +2002 6 24 18 22 BERYL 44.7 197.4 111 215 +1995 4 15 6 28 ISAAC 11.5 295.0 73 50 +2000 12 1 0 15 DEBBY 67.9 133.6 25 744 +2001 6 7 18 16 ALBERTO 24.2 143.3 143 728 +1954 5 8 12 7 DEBBY 26.6 116.6 39 728 +2004 2 10 6 9 HELENE 56.2 50.5 95 553 +1989 2 8 18 19 PATTY 13.4 53.7 53 230 +1989 1 16 18 1 OSCAR 58.4 75.9 142 523 +1982 3 12 18 6 ISAAC 37.2 200.8 135 62 +1971 6 4 12 21 CHRIS 52.9 273.2 116 783 +1967 12 3 0 25 DEBBY 35.5 53.5 129 310 +1990 1 18 12 4 VALERIE 63.0 341.1 144 413 +1983 10 19 6 22 CHRIS 42.0 303.2 109 749 +1997 4 3 18 28 KIRK 17.6 26.5 126 754 +2003 4 5 0 15 OSCAR 66.4 265.2 152 152 +1984 8 8 12 28 GORDON 41.1 2.4 155 577 +1995 12 27 18 15 BERYL 15.0 54.9 55 363 +1970 3 25 12 26 MICHAEL 60.1 188.8 85 385 +1984 6 11 0 4 VALERIE 27.3 204.2 144 161 +1995 2 7 12 20 SANDY 49.0 222.2 25 896 +1981 9 15 6 16 SANDY 17.0 334.1 93 160 +1986 7 21 18 27 GORDON 49.9 78.4 160 745 +1953 11 13 6 24 HELENE 32.1 230.3 49 77 +1990 12 27 18 5 VALERIE 56.5 302.6 63 898 +1978 4 23 12 15 ALBERTO 43.4 288.0 135 837 +1980 3 17 6 19 ALBERTO 17.8 172.8 67 224 +1995 1 21 18 1 RAFAEL 30.6 259.4 129 97 +1981 12 23 6 12 MICHAEL 42.3 76.8 116 244 +1967 2 2 0 3 OSCAR 30.4 329.6 113 361 +1958 11 27 0 19 TONY 16.9 58.2 50 499 +1975 7 26 6 27 SANDY 46.4 60.5 144 120 +1958 12 26 6 5 OSCAR 38.4 64.4 155 514 +1997 1 1 12 25 KIRK 63.2 34.2 80 364 +1953 11 24 6 10 NADINE 42.2 39.1 105 818 +1972 10 16 0 23 SANDY 43.2 175.3 10 657 +1954 5 22 6 4 DEBBY 12.9 178.1 17 381 +1970 2 15 0 25 ALBERTO 65.3 218.6 75 813 +1975 3 22 6 6 RAFAEL 24.9 62.4 33 899 +1971 9 6 12 26 ALBERTO 7.7 213.9 82 495 +1990 4 4 6 22 ALBERTO 53.6 145.1 157 199 +2004 1 4 0 4 TONY 52.5 343.7 128 362 +1961 7 15 6 17 KIRK 40.4 194.5 52 639 +1992 12 24 18 24 PATTY 55.7 95.8 140 240 +1997 11 18 6 16 ERNESTO 22.7 235.3 62 71 +1954 11 28 18 10 KIRK 62.2 337.0 158 535 +1992 6 11 18 24 CHRIS 55.9 234.1 145 487 +1961 12 21 6 22 GORDON 10.1 248.2 72 617 +1975 8 25 18 25 MICHAEL 61.0 24.8 60 875 +1997 7 10 18 25 ISAAC 7.6 142.1 147 881 +1953 8 8 12 24 FLORENCE 23.3 79.7 97 807 +2001 12 27 18 1 RAFAEL 50.6 199.4 35 203 +1951 9 14 0 8 RAFAEL 19.6 348.9 18 603 +1970 7 22 18 19 SANDY 45.5 332.4 14 26 +1965 7 14 12 18 CHRIS 23.8 250.8 76 669 +1959 1 15 18 13 CHRIS 18.9 302.9 30 60 +1974 4 26 6 22 SANDY 30.4 184.0 22 517 +1981 4 12 12 19 HELENE 69.7 133.1 131 258 +2004 8 12 0 24 SANDY 13.8 23.5 63 260 +1998 1 16 18 10 KIRK 30.0 192.3 24 542 +1979 11 28 12 8 ISAAC 66.9 172.9 40 475 +1991 4 7 12 26 HELENE 15.8 210.2 149 839 +1991 2 28 12 10 DEBBY 57.2 326.1 138 771 +1962 2 6 0 9 CHRIS 60.7 146.0 145 823 +1991 4 18 12 6 HELENE 19.7 65.8 81 296 +1978 11 3 12 11 LESLIE 30.4 22.7 105 576 +1969 4 25 0 14 ISAAC 22.1 254.0 48 170 +1963 9 18 12 2 TONY 34.3 142.5 92 296 +1963 9 4 0 12 MICHAEL 22.4 98.3 88 608 +1986 9 14 18 6 HELENE 38.0 357.7 53 318 +1951 1 19 0 2 WILLIAM 20.5 178.2 30 479 +1980 10 1 6 3 PATTY 31.4 355.5 18 34 +1994 1 3 6 27 DEBBY 37.4 319.4 105 868 +1976 6 2 12 14 GORDON 39.8 332.1 32 854 +1971 8 11 18 15 NADINE 15.6 223.7 26 103 +1964 8 13 18 26 BERYL 17.7 117.8 86 854 +1993 3 23 18 20 RAFAEL 45.4 61.4 56 133 +2002 12 20 6 4 PATTY 69.1 350.0 40 195 +1978 2 8 18 23 NADINE 37.8 125.3 13 538 +1964 11 9 18 11 JOYCE 12.4 204.4 30 843 +1967 2 14 18 23 MICHAEL 32.4 10.3 52 130 +1988 1 4 6 21 HELENE 18.8 351.5 123 609 +1952 4 12 6 11 WILLIAM 62.9 196.9 39 462 +1966 11 3 0 1 VALERIE 41.7 74.7 61 748 +1992 5 17 6 5 LESLIE 22.0 272.2 119 628 +1990 7 21 12 20 RAFAEL 52.8 31.4 97 785 +1993 8 28 18 18 KIRK 9.2 201.4 108 463 +2003 12 5 12 10 CHRIS 54.0 290.8 138 628 +1969 10 21 18 13 BERYL 53.2 295.1 154 560 +1975 7 25 12 20 ERNESTO 30.0 298.5 114 102 +1961 1 26 6 24 LESLIE 65.2 113.8 151 551 +1950 5 23 6 1 HELENE 36.6 333.4 118 162 +1954 4 18 18 7 GORDON 52.3 355.4 99 843 +1991 11 21 0 12 DEBBY 35.1 307.4 17 685 +1973 2 13 12 8 FLORENCE 44.9 27.8 120 891 +2003 4 27 6 18 BERYL 19.2 309.9 24 612 +1977 6 27 18 16 OSCAR 49.1 258.8 146 305 +1990 7 24 0 5 KIRK 29.3 213.2 143 57 +1958 12 12 12 28 MICHAEL 56.4 210.3 13 554 +2001 1 9 0 2 CHRIS 68.6 155.4 50 644 +1956 10 3 0 8 PATTY 36.9 52.2 51 171 +1973 11 13 18 20 JOYCE 63.9 139.2 142 258 +2000 7 16 18 3 SANDY 27.0 303.9 112 460 +1952 5 26 12 17 ALBERTO 25.9 49.8 81 463 +1996 3 9 18 9 KIRK 34.9 32.7 84 367 +2000 2 27 12 23 ISAAC 12.2 185.7 112 781 +1995 9 7 0 11 PATTY 61.3 226.1 148 432 +1969 7 25 12 4 ISAAC 9.3 290.8 143 590 +1993 5 8 6 5 CHRIS 65.7 201.8 119 647 +1951 10 21 18 14 KIRK 8.1 204.7 39 125 +1998 8 10 12 12 OSCAR 30.0 177.7 102 12 +1962 4 10 18 21 HELENE 64.7 295.7 160 30 +1996 3 27 0 15 KIRK 28.1 267.8 106 742 +1980 5 11 6 25 FLORENCE 55.5 62.8 105 238 +1951 8 10 18 7 OSCAR 46.9 338.8 18 561 +1952 7 23 18 10 ERNESTO 39.7 274.3 161 638 +1995 1 5 6 16 DEBBY 57.5 357.1 97 19 +1982 10 16 18 10 CHRIS 68.8 47.4 14 236 +1984 6 7 12 1 CHRIS 54.0 354.0 102 33 +2002 8 19 18 1 BERYL 54.6 218.3 15 61 +1987 10 2 6 13 PATTY 38.5 208.1 163 162 +1982 7 6 0 28 JOYCE 66.6 195.3 146 257 +1970 1 20 18 27 ALBERTO 41.2 283.7 105 773 +1967 8 14 0 24 WILLIAM 32.8 328.7 86 425 +1984 5 8 18 21 ALBERTO 20.5 293.1 142 619 +1981 11 12 6 1 ALBERTO 30.3 55.5 113 852 +1954 11 23 6 27 ERNESTO 64.5 132.1 144 356 +1981 1 13 0 28 FLORENCE 13.3 335.1 58 841 +1989 7 8 6 11 VALERIE 31.8 120.6 119 63 +1964 3 28 0 22 GORDON 40.9 59.0 23 842 +2000 9 6 0 28 TONY 57.3 236.2 152 142 +1974 12 25 18 20 MICHAEL 15.4 244.9 108 871 +1973 1 25 0 17 PATTY 42.8 25.2 32 557 +1954 1 2 6 26 BERYL 69.6 338.7 12 361 +1994 3 14 18 13 BERYL 28.4 196.5 153 749 +1964 12 25 6 8 CHRIS 17.2 59.0 31 765 +1968 7 14 18 20 TONY 41.7 299.8 157 647 +1961 6 13 18 4 PATTY 48.6 345.0 122 124 +1975 7 6 6 26 ISAAC 69.6 232.4 76 725 +2001 4 13 0 2 CHRIS 62.2 156.9 116 319 +1973 7 3 0 24 BERYL 12.3 284.6 17 109 +1967 4 17 18 24 SANDY 58.3 215.7 113 234 +1957 4 2 18 3 LESLIE 64.8 50.2 158 569 +1967 4 2 0 9 GORDON 22.3 178.2 24 259 +1977 5 8 6 14 NADINE 38.8 122.9 118 784 +1982 8 3 18 17 NADINE 29.5 204.1 136 12 +1988 12 23 18 18 ISAAC 18.2 283.6 24 780 +1952 2 25 0 26 BERYL 39.2 255.3 107 596 +1958 6 5 0 24 MICHAEL 34.6 344.7 130 533 +1965 9 23 0 24 ALBERTO 58.7 177.9 45 527 +2002 3 26 6 23 LESLIE 8.4 207.7 40 682 +1984 9 13 18 20 VALERIE 34.1 268.5 29 549 +1972 10 23 6 27 DEBBY 13.1 248.6 113 468 +1981 11 16 18 16 CHRIS 62.0 190.1 117 81 +2002 8 10 12 23 ISAAC 23.3 348.2 130 890 +1952 9 11 6 3 VALERIE 49.5 157.1 90 805 +1999 7 16 0 17 ALBERTO 69.9 116.4 101 587 +1981 3 2 6 26 TONY 27.4 30.9 60 156 +1960 11 6 18 7 JOYCE 59.2 158.6 146 392 +1980 4 5 12 15 WILLIAM 57.7 105.1 27 410 +1964 2 18 12 4 SANDY 19.7 318.3 95 658 +1964 2 12 6 6 MICHAEL 63.4 36.3 149 334 +1968 11 26 6 9 SANDY 43.3 221.5 72 139 +1961 1 9 12 13 HELENE 24.1 269.1 113 92 +1953 5 16 6 23 PATTY 61.3 238.4 106 843 +1992 11 24 18 7 DEBBY 33.5 84.9 162 366 +1972 5 17 18 6 VALERIE 61.0 349.3 151 701 +1990 12 4 12 9 PATTY 66.6 222.1 84 775 +1985 2 9 6 16 NADINE 69.5 38.8 42 729 +1965 7 4 12 18 VALERIE 34.4 181.6 60 675 +1988 8 8 12 9 LESLIE 8.1 123.6 81 619 +1960 12 11 0 23 FLORENCE 10.6 136.0 56 220 +1985 7 5 18 18 PATTY 46.9 292.3 71 406 +1992 3 18 0 16 SANDY 19.5 21.7 57 526 +1988 2 24 12 7 VALERIE 33.5 64.8 152 822 +1956 10 18 0 5 KIRK 49.7 60.2 132 607 +1996 2 19 18 8 RAFAEL 13.4 6.8 96 118 +2000 3 6 18 17 FLORENCE 7.1 241.4 52 489 +1988 9 27 0 1 ALBERTO 65.5 297.1 75 532 +1965 2 11 0 18 ALBERTO 39.1 258.2 42 580 +1971 5 3 6 27 CHRIS 30.7 89.8 87 741 +1982 6 26 12 23 PATTY 58.0 333.8 82 227 +1981 10 16 12 22 HELENE 64.5 226.7 76 876 +2001 2 11 18 20 ALBERTO 30.9 27.4 59 351 +1988 6 27 18 3 ERNESTO 16.9 101.7 156 878 +1958 7 16 6 20 NADINE 41.9 205.7 53 118 +1994 5 4 0 22 PATTY 23.4 7.9 99 801 +1966 5 11 18 22 WILLIAM 31.9 185.3 64 842 +1958 7 1 18 14 DEBBY 27.3 245.4 86 226 +1978 8 22 12 10 TONY 52.9 7.2 43 860 +1960 5 1 6 3 OSCAR 16.8 109.4 54 488 +1994 3 17 6 23 FLORENCE 59.0 20.6 38 853 +1995 3 1 0 25 BERYL 46.6 157.9 110 245 +1992 9 7 12 13 ISAAC 34.7 45.0 21 787 +1964 3 1 0 16 CHRIS 12.2 270.0 96 258 +1968 11 21 12 8 LESLIE 67.8 78.7 123 600 +1975 1 6 12 8 HELENE 65.1 7.4 40 256 +1987 1 22 18 22 ISAAC 39.7 126.8 154 871 +1963 8 19 18 26 ISAAC 46.0 199.5 75 222 +1976 6 7 0 20 DEBBY 67.2 12.3 140 3 +1972 11 21 0 13 ERNESTO 14.2 209.7 112 836 +1979 6 7 18 14 BERYL 48.3 123.8 82 83 +1989 3 5 18 13 ERNESTO 56.7 320.3 14 618 +1970 1 14 12 6 CHRIS 8.6 63.8 113 661 +1961 12 19 12 4 DEBBY 14.2 148.8 31 174 +1981 12 28 0 12 PATTY 24.3 151.3 47 897 +1975 12 4 6 1 WILLIAM 52.6 338.7 155 435 +1953 6 5 12 3 ERNESTO 46.6 198.2 60 555 +1956 7 3 12 19 LESLIE 59.5 104.2 143 602 +1993 5 2 18 21 NADINE 44.2 31.9 106 297 +1997 4 22 0 23 HELENE 9.5 304.1 31 262 +1976 4 19 18 7 SANDY 55.7 85.9 145 428 +1952 7 21 18 6 HELENE 36.4 184.8 17 384 +1988 7 19 0 9 LESLIE 66.7 127.5 55 71 +1992 11 25 18 6 KIRK 53.6 215.5 47 488 +1974 7 23 0 22 KIRK 51.4 254.5 52 414 +1972 8 12 12 16 JOYCE 45.6 314.7 113 743 +1958 1 10 12 21 JOYCE 36.3 103.1 71 350 +1969 1 20 12 4 OSCAR 39.3 265.9 133 498 +1998 5 6 6 16 FLORENCE 34.6 349.7 128 75 +1952 7 2 12 20 HELENE 55.1 234.6 109 723 +1989 7 8 0 15 PATTY 67.2 322.2 15 805 +1985 3 20 6 1 NADINE 9.7 192.4 41 853 +1981 6 5 18 22 ALBERTO 28.3 81.5 65 771 +1985 11 21 12 15 CHRIS 11.6 272.9 59 501 +1954 3 23 6 13 HELENE 12.1 7.8 146 701 +2002 9 20 12 15 ISAAC 46.4 164.1 65 234 +1972 6 16 18 5 CHRIS 34.3 117.2 124 124 +1999 7 4 6 26 LESLIE 24.4 327.8 15 428 +1963 6 27 0 11 HELENE 68.8 214.7 15 713 +1964 10 1 12 17 GORDON 21.1 283.8 57 520 +1970 5 3 0 11 VALERIE 32.2 261.2 88 37 +1999 2 11 12 12 JOYCE 45.3 186.5 129 160 +1981 4 26 0 26 FLORENCE 25.9 184.5 41 186 +1964 12 17 6 27 DEBBY 59.1 138.5 77 704 +1972 11 27 0 19 HELENE 40.6 115.6 90 248 +1996 5 4 12 5 NADINE 46.7 162.7 126 316 +1963 3 25 6 17 LESLIE 68.0 119.7 42 379 +1980 10 19 12 12 TONY 31.7 176.7 93 574 +1970 2 9 18 19 JOYCE 18.8 78.8 131 626 +1955 10 7 0 13 JOYCE 23.0 23.2 80 280 +1975 4 27 0 6 DEBBY 64.8 341.3 27 877 +1979 1 21 0 9 HELENE 38.7 273.6 38 754 +1981 7 14 6 28 ERNESTO 36.2 322.3 103 767 +1996 1 6 0 8 CHRIS 54.2 171.6 160 493 +1995 4 1 0 4 CHRIS 22.2 211.2 14 464 +1990 11 15 6 2 FLORENCE 37.6 124.0 10 391 +1997 10 25 6 1 MICHAEL 50.6 136.1 77 604 +2001 7 8 0 23 FLORENCE 29.0 238.3 75 343 +2001 12 7 18 2 WILLIAM 30.9 39.8 159 215 +1989 5 3 6 12 SANDY 49.7 296.6 24 638 +1953 7 12 12 18 FLORENCE 26.6 251.7 47 690 +1971 6 28 12 1 LESLIE 11.3 56.2 138 889 +1963 3 12 12 16 PATTY 62.3 112.1 67 389 +1968 9 9 6 21 OSCAR 46.1 244.2 39 212 +2004 11 21 18 19 CHRIS 26.9 2.9 59 175 +2003 11 16 6 22 ALBERTO 55.1 233.2 24 93 +1992 12 5 12 4 GORDON 30.4 16.4 155 738 +1957 12 20 6 8 MICHAEL 38.7 58.2 133 737 +2000 2 4 6 1 TONY 55.7 241.0 69 873 +1999 3 14 6 21 OSCAR 48.4 238.5 66 335 +1964 7 9 0 27 BERYL 37.2 218.0 26 248 +1978 4 3 12 11 JOYCE 24.0 220.1 123 260 +1974 1 22 12 19 ERNESTO 10.5 146.1 101 500 +1975 5 23 6 26 RAFAEL 11.0 309.4 83 244 +1954 4 16 6 22 JOYCE 61.9 310.3 116 462 +1957 3 2 0 17 FLORENCE 37.1 177.0 133 4 +1954 8 2 18 15 OSCAR 62.7 44.0 137 597 +1959 3 13 12 10 WILLIAM 40.5 320.1 142 252 +1963 5 19 6 20 MICHAEL 56.3 114.5 113 546 +1951 12 11 0 22 TONY 67.3 266.8 99 477 +1950 4 2 0 14 JOYCE 31.7 183.9 65 749 +1972 10 15 18 1 ISAAC 44.5 199.7 120 494 +1968 4 27 12 2 MICHAEL 41.5 170.0 66 662 +1995 11 18 18 1 DEBBY 42.9 42.6 32 451 +1975 5 8 6 20 JOYCE 63.1 97.5 11 477 +1957 1 3 0 18 BERYL 66.6 26.8 80 462 +1983 4 19 12 18 DEBBY 33.7 320.5 152 292 +1991 12 26 6 11 KIRK 28.5 287.1 88 614 +1992 12 6 12 19 FLORENCE 44.9 237.1 105 184 +1991 7 11 0 28 BERYL 9.7 269.2 66 127 +1991 1 14 0 9 ISAAC 17.6 270.5 82 272 +1965 1 20 18 24 CHRIS 57.4 50.6 46 30 +1999 12 28 12 5 ALBERTO 50.7 127.6 157 501 +1993 4 7 18 28 GORDON 68.3 236.4 54 670 +1976 12 14 6 15 ERNESTO 10.2 39.3 104 591 +1992 7 16 0 21 BERYL 58.8 332.0 23 41 +1999 1 6 0 27 LESLIE 25.4 226.9 81 386 +1971 2 18 12 8 JOYCE 33.0 315.5 116 496 +1963 12 6 12 12 NADINE 40.9 226.5 106 468 +1965 5 10 12 17 PATTY 61.2 281.0 153 883 +1960 5 2 18 26 PATTY 15.6 339.4 70 514 +1994 11 25 0 24 TONY 63.2 10.6 17 222 +1987 10 23 12 20 OSCAR 56.1 334.3 135 697 +1984 5 19 12 6 BERYL 25.1 211.3 145 231 +1993 2 5 6 24 FLORENCE 28.0 281.2 134 232 +1990 7 24 6 22 WILLIAM 29.7 7.3 146 294 +1955 4 22 6 20 CHRIS 39.5 254.2 49 362 +1982 7 24 12 21 SANDY 59.4 85.3 113 883 +1972 6 12 18 11 CHRIS 11.6 341.7 62 324 +1952 9 23 18 14 MICHAEL 49.5 32.0 116 148 +1968 4 6 6 14 ISAAC 39.6 350.5 15 536 +1955 10 8 18 1 DEBBY 60.8 134.6 87 105 +1980 9 28 18 14 OSCAR 36.6 279.8 17 477 +1969 8 2 18 8 JOYCE 31.1 9.4 96 389 +1951 12 23 18 6 NADINE 62.2 76.3 66 763 +1990 9 1 0 6 ALBERTO 62.8 137.6 96 468 +1998 6 22 0 5 WILLIAM 46.2 59.7 38 486 +1981 9 16 18 17 FLORENCE 26.6 4.3 98 57 +1958 3 4 12 17 CHRIS 49.6 303.3 147 15 +1952 1 28 12 12 WILLIAM 49.1 220.8 42 386 +1962 10 8 0 24 ALBERTO 20.6 336.2 101 166 +1978 5 6 6 9 ISAAC 30.6 281.9 50 579 +1969 10 20 0 11 ALBERTO 39.5 92.9 103 896 +1970 1 17 6 14 WILLIAM 40.0 158.8 55 167 +2003 3 14 18 15 LESLIE 59.5 63.8 96 41 +1980 4 24 6 18 LESLIE 25.9 103.9 110 756 +1979 5 9 12 13 GORDON 46.9 4.4 131 99 +1987 7 8 12 21 ISAAC 22.4 51.9 44 732 +1980 9 28 0 7 VALERIE 60.2 261.0 153 64 +1952 9 18 0 7 NADINE 52.2 285.1 143 0 +1993 9 10 6 12 WILLIAM 10.1 227.5 107 883 +1997 11 25 6 24 VALERIE 40.8 330.9 56 843 +1965 7 14 18 9 NADINE 47.1 255.1 109 756 +1997 11 22 12 4 TONY 66.1 188.6 38 731 +1960 7 7 12 10 BERYL 58.8 309.9 104 376 +1957 3 4 6 12 NADINE 36.5 273.5 57 316 +1988 12 13 0 17 JOYCE 48.4 266.1 95 801 +1975 6 18 18 20 LESLIE 12.1 225.9 46 898 +1965 6 3 18 8 RAFAEL 68.1 83.4 150 352 +1990 9 19 12 8 ISAAC 54.8 187.4 32 470 +1967 11 5 6 25 CHRIS 20.7 139.5 135 256 +1974 11 25 12 19 PATTY 56.6 195.5 126 772 +1965 2 20 6 3 WILLIAM 37.2 346.6 153 836 +1967 9 16 0 15 TONY 28.6 179.1 156 13 +1999 9 3 0 13 PATTY 52.3 268.6 16 708 +1999 3 24 12 3 BERYL 37.3 144.4 135 670 +1959 4 19 6 25 WILLIAM 9.7 102.0 162 258 +1956 12 1 18 28 DEBBY 39.9 176.6 59 724 +1965 3 15 18 16 RAFAEL 43.3 339.1 132 675 +1972 3 15 12 4 VALERIE 37.3 217.4 160 176 +1970 1 19 18 12 SANDY 47.2 215.5 61 711 +1993 11 2 0 10 VALERIE 32.9 185.6 128 314 +1982 5 12 6 25 PATTY 25.2 314.6 132 83 +1985 12 2 0 10 WILLIAM 23.3 152.5 105 593 +1969 8 16 0 2 OSCAR 25.9 355.3 129 528 +1954 5 2 12 12 TONY 38.4 68.6 31 533 +1956 9 21 0 22 KIRK 30.9 286.4 29 559 +1962 9 10 0 3 HELENE 61.5 136.0 50 155 +1976 12 16 12 10 NADINE 21.5 229.3 29 698 +1953 8 25 6 13 ERNESTO 8.8 8.8 121 341 +1996 1 14 0 14 ERNESTO 11.6 57.9 146 101 +1958 7 7 0 19 OSCAR 67.1 335.5 155 535 +1990 11 28 18 21 TONY 57.7 228.2 63 178 +1998 6 10 6 5 RAFAEL 8.2 119.1 137 787 +1965 7 17 18 14 ALBERTO 15.1 263.5 23 53 +1972 1 23 12 7 KIRK 16.7 272.3 128 760 +1999 7 17 18 24 ALBERTO 8.0 338.5 61 843 +1958 10 26 12 4 WILLIAM 60.3 180.5 142 612 +1989 9 4 6 27 GORDON 60.0 154.3 75 341 +1994 10 18 0 9 NADINE 46.4 229.1 88 345 +1975 1 19 0 22 JOYCE 40.2 97.9 132 413 +1983 3 6 12 17 PATTY 46.2 92.8 152 442 +2003 11 1 12 4 MICHAEL 36.2 267.4 89 862 +1998 4 26 18 8 RAFAEL 14.8 229.0 120 147 +1968 6 14 6 11 NADINE 13.0 118.3 134 601 +1998 6 24 12 8 WILLIAM 35.1 75.8 22 200 +1981 1 16 6 20 JOYCE 69.7 264.3 119 52 +2002 3 9 18 15 SANDY 28.2 285.7 92 531 +1970 7 16 18 8 JOYCE 12.9 51.5 122 326 +1954 1 25 0 10 WILLIAM 29.1 221.6 149 416 +1957 11 28 12 27 LESLIE 33.4 39.7 141 134 +1984 11 25 12 9 KIRK 65.8 334.2 21 733 +1959 1 21 0 22 HELENE 9.6 341.5 122 641 +1970 5 6 0 5 HELENE 39.3 320.7 47 586 +1993 2 22 18 18 NADINE 60.3 220.8 97 829 +1985 10 18 6 26 GORDON 33.1 181.1 89 116 +1951 2 8 18 17 PATTY 60.1 324.4 20 244 +1965 11 21 18 8 PATTY 26.8 295.9 123 192 +1954 2 4 0 7 PATTY 45.0 84.6 110 202 +1968 9 2 18 24 HELENE 35.6 352.2 135 881 +2002 10 3 0 23 ISAAC 9.9 110.5 17 744 +1954 8 8 18 27 KIRK 24.6 30.4 10 145 +1958 2 21 6 13 SANDY 14.5 163.8 80 69 +1967 3 25 12 6 LESLIE 11.3 214.2 107 273 +1967 5 5 6 4 OSCAR 66.7 17.5 113 855 +1959 10 6 18 22 ISAAC 39.9 76.7 84 182 +1958 8 25 18 13 BERYL 55.2 248.7 46 470 +2003 4 21 6 6 HELENE 9.4 39.7 54 143 +1974 10 14 0 11 RAFAEL 31.7 244.6 104 581 +1966 2 21 0 22 SANDY 49.1 130.5 161 513 +2000 6 20 0 15 LESLIE 68.7 156.7 142 478 +1954 2 22 12 5 OSCAR 13.4 318.8 82 521 +1982 1 18 0 3 OSCAR 10.2 29.0 51 809 +1960 9 24 6 1 RAFAEL 43.0 154.1 81 820 +1973 7 7 18 3 WILLIAM 18.2 270.6 29 171 +1958 2 21 6 15 BERYL 61.7 287.7 24 265 +1998 8 7 0 16 TONY 58.0 104.9 20 702 +1981 11 22 0 4 MICHAEL 17.5 239.8 23 511 +1990 7 18 6 21 RAFAEL 27.6 86.7 48 615 +1972 3 23 18 27 GORDON 19.2 229.6 163 237 +1996 11 28 0 18 GORDON 68.4 316.4 135 310 +1982 7 28 6 20 FLORENCE 26.5 219.1 156 221 +1984 12 16 0 19 PATTY 29.4 224.8 94 365 +1972 1 4 12 10 HELENE 27.8 223.7 38 872 +1986 2 11 0 1 ERNESTO 42.4 305.2 90 841 +1982 8 16 18 9 ALBERTO 37.0 73.8 142 62 +1985 7 21 0 19 JOYCE 7.1 181.6 131 85 +1975 7 13 6 4 PATTY 33.4 88.0 58 890 +1985 8 15 18 5 WILLIAM 52.0 110.5 126 473 +1962 9 9 18 16 ALBERTO 66.0 198.7 13 126 +1966 1 14 6 15 BERYL 26.0 349.4 87 455 +1957 5 15 0 2 ERNESTO 8.6 73.4 25 862 +1984 1 28 0 18 MICHAEL 54.9 153.8 79 899 +1980 10 4 12 20 DEBBY 25.0 252.1 43 720 +1968 6 12 6 8 RAFAEL 14.1 316.2 17 851 +1978 1 17 0 4 HELENE 45.3 97.5 53 258 +1963 2 20 0 14 GORDON 21.9 319.5 153 872 +1966 8 2 6 2 ISAAC 57.0 208.8 17 850 +1950 1 1 12 5 ERNESTO 8.4 62.2 134 319 +1952 8 23 0 12 KIRK 8.5 75.7 22 454 +1992 8 3 12 24 PATTY 11.7 79.8 25 531 +1991 9 18 0 25 ERNESTO 9.0 243.1 42 846 +1993 8 20 12 1 OSCAR 57.7 133.3 68 600 +1988 6 11 6 23 FLORENCE 17.0 221.0 66 483 +1950 12 11 6 22 ALBERTO 25.2 165.0 92 792 +1955 1 12 12 8 GORDON 27.5 106.5 78 76 +1989 12 17 12 19 LESLIE 13.8 260.6 115 243 +2000 10 26 0 13 JOYCE 64.5 266.3 83 419 +1970 3 21 18 8 FLORENCE 51.9 298.1 32 96 +1980 11 2 12 19 PATTY 21.7 186.8 21 477 +1985 12 19 18 8 GORDON 46.9 10.1 43 343 +1974 9 10 6 17 PATTY 45.0 127.2 60 275 +2000 8 22 12 10 LESLIE 49.6 200.9 43 287 +1955 8 13 18 15 KIRK 39.7 184.8 75 840 +1957 4 24 18 15 RAFAEL 37.3 132.7 103 1 +1998 9 11 0 3 FLORENCE 17.9 91.6 46 587 +1952 8 1 0 4 KIRK 23.8 330.1 163 28 +1979 5 8 0 17 ALBERTO 54.6 53.0 40 47 +1998 2 14 18 22 OSCAR 43.7 19.8 112 193 +1959 6 16 18 25 TONY 36.2 172.8 124 832 +1967 4 26 6 20 CHRIS 19.9 93.9 42 76 +2003 8 2 6 23 ALBERTO 10.2 259.1 164 39 +1976 3 9 12 10 DEBBY 61.2 137.3 94 885 +1957 1 7 6 19 GORDON 41.6 232.6 17 292 +1994 11 28 18 16 RAFAEL 18.1 229.8 102 246 +1970 8 21 12 28 SANDY 53.5 55.9 90 849 +1985 4 28 18 26 ISAAC 41.2 138.8 90 640 +1984 3 14 12 2 HELENE 11.9 58.9 149 395 +1989 1 1 12 7 OSCAR 37.4 357.5 67 466 +2004 10 28 6 13 TONY 27.1 102.2 135 515 +1954 12 23 6 13 PATTY 43.5 33.7 154 230 +1966 6 14 6 1 HELENE 32.6 123.1 163 509 +2002 1 19 0 24 DEBBY 64.3 103.7 95 881 +1985 6 25 0 3 GORDON 12.6 72.4 90 84 +1950 7 26 6 18 JOYCE 24.9 113.3 52 774 +2004 1 15 0 23 RAFAEL 50.6 291.1 96 57 +1957 7 20 0 19 BERYL 38.7 23.8 31 476 +1968 3 17 0 13 CHRIS 29.9 70.0 134 886 +1958 5 26 12 10 ISAAC 32.4 316.1 93 528 +1984 2 15 0 7 ERNESTO 65.0 64.7 12 412 +1976 6 8 0 27 ISAAC 64.0 336.6 11 436 +2000 12 2 12 7 ERNESTO 15.6 298.3 126 115 +1988 12 11 0 1 OSCAR 63.3 128.7 19 748 +1995 12 14 6 16 RAFAEL 70.0 46.0 22 375 +1974 1 11 12 23 ALBERTO 39.3 56.6 34 60 +1982 3 22 12 27 ISAAC 38.9 41.4 59 212 +1957 11 28 12 18 CHRIS 52.3 19.0 67 7 +1954 10 6 0 5 BERYL 67.2 114.8 99 746 +1950 11 20 6 3 FLORENCE 44.0 127.6 141 884 +1977 4 15 0 15 ISAAC 7.7 246.3 16 221 +1950 4 6 18 18 RAFAEL 12.9 84.8 65 633 +1976 6 18 0 27 SANDY 30.7 284.4 39 44 +1976 1 23 12 6 KIRK 17.0 292.4 11 533 +1961 10 24 0 23 GORDON 43.9 65.2 123 621 +1965 10 7 18 9 OSCAR 62.6 164.9 35 77 +1971 1 14 6 2 DEBBY 35.2 188.6 144 348 +1965 12 17 18 22 HELENE 50.2 92.5 66 50 +1953 9 13 12 10 TONY 32.8 50.6 53 301 +1961 12 21 18 14 DEBBY 64.9 78.9 124 799 +1983 6 3 18 5 OSCAR 18.5 80.8 147 625 +1976 9 17 12 22 OSCAR 19.2 246.4 144 650 +1963 9 20 0 5 RAFAEL 58.7 181.2 30 569 +1974 10 16 6 23 JOYCE 65.7 215.9 130 254 +1989 6 1 0 26 PATTY 68.5 277.2 29 878 +1968 7 4 18 9 PATTY 32.7 301.8 79 160 +1981 5 9 6 12 NADINE 28.2 25.3 67 768 +2002 3 4 6 17 GORDON 37.9 125.6 54 225 +1990 2 19 0 22 BERYL 51.1 148.4 129 608 +1981 10 4 12 25 VALERIE 62.4 34.8 32 150 +1997 6 14 6 13 DEBBY 12.9 152.6 54 709 +1952 1 3 6 25 JOYCE 14.0 247.2 71 761 +2004 4 2 12 14 TONY 19.4 87.8 163 775 +1992 11 15 0 11 JOYCE 49.3 294.8 11 74 +1969 10 18 0 26 OSCAR 15.4 212.1 46 747 +1955 1 14 0 18 ERNESTO 26.9 315.7 39 77 +1954 11 21 12 26 JOYCE 65.2 219.8 34 311 +1971 2 9 12 4 GORDON 10.9 154.8 44 241 +1994 12 28 18 22 BERYL 20.8 49.1 80 540 +1978 5 14 18 11 BERYL 27.2 217.6 26 562 +1964 8 15 18 23 FLORENCE 52.4 338.3 17 875 +1985 12 6 18 10 ISAAC 68.4 270.1 101 538 +1950 10 10 6 9 TONY 27.8 43.4 152 691 +1980 7 23 12 19 PATTY 49.6 337.0 130 345 +1981 1 25 0 26 BERYL 55.0 72.9 87 192 +1958 4 4 12 2 VALERIE 67.7 121.8 35 229 +1971 11 12 12 18 FLORENCE 41.4 253.3 130 626 +2002 4 18 18 16 HELENE 46.9 356.2 162 6 +1983 10 21 12 10 BERYL 57.7 139.4 109 764 +1975 9 26 6 13 ISAAC 39.4 154.6 157 525 +1980 6 14 6 4 NADINE 46.3 219.5 37 643 +1971 6 7 18 5 NADINE 50.4 259.9 44 716 +1957 5 4 6 5 MICHAEL 22.5 49.3 143 107 +1991 3 10 12 7 RAFAEL 17.6 267.6 140 520 +1969 5 9 6 2 LESLIE 24.7 116.3 12 559 +2000 10 21 12 6 WILLIAM 58.0 204.4 126 804 +1979 5 23 6 16 TONY 49.2 281.9 27 673 +1965 9 23 12 6 VALERIE 48.6 297.9 69 190 +1997 9 17 18 20 FLORENCE 65.5 70.5 23 419 +1998 12 18 18 5 OSCAR 12.2 102.3 47 874 +1960 12 23 0 25 SANDY 46.7 230.0 75 465 +1950 12 19 12 21 JOYCE 38.3 311.7 133 464 +2003 5 21 18 16 VALERIE 67.9 313.2 117 209 +1985 6 8 18 5 VALERIE 37.7 75.0 29 247 +1995 12 5 18 27 RAFAEL 45.1 228.2 89 199 +1987 11 26 12 3 ISAAC 25.3 75.9 31 638 +1997 1 26 6 25 OSCAR 41.8 21.0 20 464 +1991 4 19 6 11 ALBERTO 11.8 269.6 140 408 +1982 7 1 0 6 DEBBY 60.2 232.6 134 896 +1991 3 5 18 28 MICHAEL 64.9 73.0 139 697 +1976 8 6 12 2 ERNESTO 38.4 294.4 117 455 +1954 7 28 12 14 GORDON 69.6 281.6 85 815 +2003 11 24 0 25 RAFAEL 53.6 100.6 21 86 +1998 3 19 18 5 RAFAEL 37.3 227.0 116 57 +2004 11 24 18 25 NADINE 36.6 13.9 50 659 +1979 8 17 18 10 ERNESTO 50.6 176.2 79 278 +1973 6 18 6 20 NADINE 65.4 10.1 143 476 +1980 1 7 18 14 NADINE 28.9 79.8 15 284 +1988 10 28 6 22 KIRK 47.4 80.9 126 729 +1978 7 13 12 13 TONY 35.7 132.2 25 756 +1972 6 25 6 1 OSCAR 49.6 4.8 135 779 +1989 9 6 18 21 VALERIE 23.5 160.2 47 416 +1994 8 25 12 21 CHRIS 60.6 94.0 108 493 +1992 9 14 6 9 OSCAR 38.7 77.5 141 566 +1967 7 5 18 21 MICHAEL 33.5 350.7 137 724 +1963 2 10 6 5 GORDON 13.5 38.1 13 416 +1990 2 19 12 24 DEBBY 43.7 326.1 137 266 +1959 11 3 12 12 DEBBY 7.2 300.6 10 162 +1989 3 10 18 19 SANDY 64.7 224.2 39 639 +1989 7 27 6 16 VALERIE 43.1 57.8 55 170 +1978 6 2 6 25 TONY 12.7 312.6 93 830 +1988 12 26 18 3 WILLIAM 61.9 322.3 51 551 +1993 6 25 6 12 ISAAC 64.0 182.8 157 225 +1981 3 22 18 11 TONY 48.7 272.6 59 282 +1950 8 19 6 21 MICHAEL 18.9 235.7 81 636 +1974 8 15 6 22 LESLIE 11.7 41.9 61 529 +1979 1 8 18 15 FLORENCE 7.1 242.8 60 566 +2003 9 9 6 26 RAFAEL 55.9 85.9 91 824 +1991 1 5 18 28 GORDON 20.7 13.3 74 893 +1961 5 5 6 25 JOYCE 26.8 245.8 53 720 +1974 7 11 0 10 SANDY 40.1 349.2 56 564 +1991 5 24 0 5 RAFAEL 16.9 68.6 119 310 +1965 9 15 0 26 WILLIAM 55.8 115.1 51 46 +1969 3 20 0 8 OSCAR 17.6 193.8 164 559 +1990 2 7 0 3 ISAAC 31.7 309.8 141 696 +1993 6 7 0 5 WILLIAM 53.1 7.2 77 588 +1973 6 1 0 26 HELENE 39.8 212.0 143 591 +1980 4 11 0 12 TONY 55.3 125.1 31 467 +1997 3 24 0 12 OSCAR 12.5 48.2 57 165 +1996 12 10 0 18 RAFAEL 55.1 303.6 164 8 +1979 1 16 0 4 ISAAC 41.1 219.3 89 408 +1990 7 25 6 3 HELENE 8.4 122.5 42 193 +1959 7 13 18 13 WILLIAM 47.9 225.9 154 106 +2000 1 20 18 28 ERNESTO 9.7 279.3 134 65 +1985 10 21 6 18 ERNESTO 37.2 259.9 154 566 +2004 12 24 0 8 JOYCE 31.2 274.2 122 803 +1951 2 17 12 2 MICHAEL 20.9 211.7 81 56 +1967 11 9 0 9 TONY 36.4 93.8 38 850 +1952 2 21 6 12 ERNESTO 26.0 298.2 108 783 +1978 8 15 12 8 OSCAR 33.0 59.4 82 644 +1951 12 3 12 13 RAFAEL 55.0 241.5 29 692 +1966 5 15 0 22 ERNESTO 46.0 240.0 135 621 +1958 1 19 12 16 ISAAC 55.2 173.7 135 840 +1980 11 18 12 28 RAFAEL 8.2 2.5 19 89 +1973 1 6 12 19 HELENE 56.7 200.2 109 247 +1984 11 27 6 7 JOYCE 7.2 145.5 44 192 +1952 2 2 18 11 ALBERTO 58.9 198.5 58 600 +1968 12 18 12 10 ERNESTO 46.6 119.2 116 545 +1956 9 6 18 28 NADINE 21.7 112.5 155 102 +1994 3 2 6 26 OSCAR 64.1 323.4 146 722 +1965 3 25 18 7 SANDY 56.3 346.3 142 615 +1979 8 6 0 17 CHRIS 58.2 246.0 66 430 +1991 10 2 12 25 OSCAR 22.5 249.2 154 875 +1973 8 24 6 10 JOYCE 55.2 161.2 131 555 +1976 6 26 18 6 ISAAC 7.7 182.3 25 674 +1988 2 23 12 27 NADINE 54.8 118.5 43 129 +1964 7 24 18 13 LESLIE 52.7 107.0 64 207 +1976 3 2 18 2 HELENE 28.4 173.0 28 542 +1979 4 19 0 1 PATTY 37.3 223.9 66 721 +1958 11 4 0 3 JOYCE 7.5 203.1 26 740 +1997 8 16 18 23 WILLIAM 59.9 82.9 78 384 +1959 6 21 18 19 NADINE 53.9 311.5 66 469 +1971 8 10 0 4 RAFAEL 33.9 11.6 147 421 +2004 4 1 6 3 ALBERTO 51.4 46.8 141 498 +1969 10 27 6 19 ERNESTO 69.7 299.9 113 452 +1989 12 12 12 28 ERNESTO 24.0 305.3 72 434 +1992 3 12 12 13 ALBERTO 29.0 1.6 71 403 +2003 2 19 6 10 LESLIE 37.8 288.3 109 824 +1999 2 21 6 18 KIRK 36.5 156.5 162 772 +1967 3 7 12 6 WILLIAM 66.3 151.5 21 796 +1955 2 21 6 27 OSCAR 62.1 201.0 19 328 +1996 8 25 0 10 RAFAEL 31.6 302.3 143 461 +1994 12 28 18 11 HELENE 29.2 87.6 72 657 +1998 10 25 6 27 JOYCE 62.9 252.3 131 582 +1983 7 14 0 2 KIRK 11.5 215.9 134 732 +2004 6 20 6 17 BERYL 24.5 247.0 90 826 +2002 9 17 0 27 LESLIE 51.4 15.1 60 786 +1991 12 5 18 12 HELENE 10.9 347.2 29 767 +1995 7 6 6 2 DEBBY 36.6 299.2 116 83 +1993 9 17 0 4 WILLIAM 60.8 141.5 134 772 +1968 1 23 0 16 BERYL 59.5 346.8 10 765 +1960 3 15 12 15 NADINE 67.2 19.6 10 335 +1964 5 17 6 12 CHRIS 20.9 54.7 123 157 +1962 12 26 12 13 HELENE 15.5 275.4 159 176 +2004 7 22 0 21 RAFAEL 19.7 259.4 56 170 +1967 11 27 18 7 TONY 66.6 27.9 125 762 +2000 10 9 12 15 WILLIAM 44.9 272.6 97 210 +1959 7 3 12 10 VALERIE 33.4 272.6 87 612 +1973 6 18 6 16 FLORENCE 22.8 79.8 45 863 +1969 6 3 12 18 NADINE 61.4 257.7 40 21 +1967 7 20 6 1 HELENE 55.7 112.8 90 485 +1976 10 14 18 25 WILLIAM 35.3 150.0 64 454 +1971 9 7 12 12 VALERIE 53.5 30.1 107 590 +1996 6 15 12 8 DEBBY 68.4 142.8 64 585 +1983 8 6 12 9 BERYL 18.1 233.0 61 724 +1972 12 19 0 19 SANDY 59.9 343.8 154 58 +1992 4 5 0 9 SANDY 50.4 355.0 41 607 +1988 12 15 18 18 WILLIAM 18.5 350.7 161 144 +1971 2 6 18 22 FLORENCE 12.2 326.1 97 4 +1994 10 2 6 9 NADINE 11.9 159.6 118 104 +1990 7 12 18 5 ALBERTO 44.5 157.2 139 592 +1975 1 21 12 23 ALBERTO 45.3 158.6 57 210 +1987 3 22 12 6 FLORENCE 53.9 120.4 49 726 +1986 7 3 12 12 GORDON 59.4 307.7 124 555 +1969 10 28 12 1 NADINE 65.6 181.8 57 805 +1963 8 21 0 17 DEBBY 23.0 208.8 56 19 +1975 12 17 12 26 CHRIS 62.8 270.9 69 732 +1974 12 12 12 2 SANDY 49.7 157.4 153 679 +1968 2 11 12 14 ISAAC 38.2 46.9 77 280 +1998 4 14 12 17 TONY 20.3 341.2 162 561 +1986 5 17 12 4 HELENE 65.5 21.3 142 507 +1981 5 22 12 19 VALERIE 19.7 61.5 82 874 +1972 1 14 12 7 SANDY 38.9 356.8 120 689 +1963 1 26 6 1 BERYL 8.5 76.0 78 530 +1958 8 26 12 3 TONY 11.0 21.6 140 57 +1972 8 22 6 16 GORDON 26.1 141.0 85 292 +1998 6 4 18 4 TONY 8.3 90.7 125 459 +1968 3 17 6 16 DEBBY 17.5 272.3 30 131 +1998 2 24 18 13 LESLIE 14.1 10.0 112 685 +1954 6 14 0 17 ALBERTO 58.9 39.6 28 772 +1952 6 3 0 1 RAFAEL 35.4 98.1 110 250 +1975 12 23 0 3 MICHAEL 48.4 313.6 135 19 +1975 3 26 12 7 MICHAEL 8.9 123.0 65 821 +1985 12 14 18 15 WILLIAM 61.4 200.2 126 190 +1961 12 17 6 6 HELENE 39.1 344.6 145 66 +1998 9 26 12 13 LESLIE 64.8 327.0 84 465 +1955 8 3 12 17 WILLIAM 67.0 110.3 129 740 +1979 5 16 18 11 SANDY 35.2 256.6 74 229 +1983 11 28 12 8 ALBERTO 15.5 234.7 125 476 +1964 10 15 18 2 GORDON 24.3 313.2 103 897 +1974 7 1 18 14 WILLIAM 26.0 18.9 53 808 +1956 6 27 18 7 TONY 38.0 73.2 97 41 +1962 5 18 18 15 HELENE 9.2 255.8 102 40 +1993 9 17 0 16 ERNESTO 14.7 229.7 83 781 +1964 2 5 0 8 WILLIAM 50.3 184.6 105 476 +1998 1 6 18 10 PATTY 45.1 57.7 136 880 +1970 1 16 12 11 BERYL 34.4 28.4 82 574 +1986 5 15 18 15 JOYCE 63.7 3.5 41 174 +1977 3 28 0 3 ERNESTO 29.3 42.8 37 446 +1956 9 18 18 25 HELENE 59.9 74.6 164 835 +1969 10 6 12 27 DEBBY 32.7 143.1 106 4 +1963 12 14 18 28 ALBERTO 38.6 19.1 86 557 +1954 10 20 0 25 ALBERTO 60.0 333.3 141 307 +1953 2 22 12 10 FLORENCE 16.6 64.8 112 61 +1987 7 14 12 22 RAFAEL 49.9 165.8 90 78 +1974 6 12 0 19 ISAAC 55.8 304.8 134 605 +1959 4 23 6 7 KIRK 57.8 308.0 66 577 +1984 11 4 6 14 GORDON 37.8 56.5 59 725 +1972 8 1 18 1 KIRK 21.4 22.4 120 646 +1976 4 15 0 4 SANDY 69.3 156.3 18 363 +1962 5 4 0 24 LESLIE 48.2 200.9 91 10 +1970 2 11 12 28 TONY 30.7 98.8 152 617 +1950 11 17 6 8 WILLIAM 47.0 309.1 49 796 +1992 12 26 0 18 RAFAEL 35.9 252.0 41 54 +1968 12 19 12 7 GORDON 26.3 156.0 78 297 +1970 7 15 12 18 BERYL 28.3 66.1 104 37 +1979 11 1 6 16 WILLIAM 42.8 185.5 151 159 +1992 3 17 12 27 BERYL 47.0 102.2 31 17 +1976 2 9 12 6 RAFAEL 24.3 218.0 156 26 +1959 4 14 0 22 ISAAC 39.2 167.7 122 204 +1997 1 5 18 3 MICHAEL 42.3 183.7 61 88 +1975 12 24 18 12 WILLIAM 30.8 301.4 57 572 +1951 2 20 0 26 OSCAR 30.4 144.1 80 523 +1986 8 13 12 5 DEBBY 9.2 262.8 100 701 +1994 7 12 0 10 ALBERTO 61.3 145.3 117 446 +1980 8 11 0 16 NADINE 38.1 153.5 107 631 +2001 7 1 6 9 VALERIE 31.3 197.9 46 184 +1954 8 4 0 4 NADINE 55.9 104.3 91 546 +1999 8 25 0 20 GORDON 10.3 306.8 106 727 +1965 11 10 0 5 GORDON 7.3 43.7 85 466 +1985 2 19 6 7 BERYL 15.7 299.4 21 348 +1971 4 23 12 21 FLORENCE 38.0 0.2 148 25 +1977 11 21 0 7 SANDY 31.0 320.5 107 466 +1980 3 22 0 27 ERNESTO 55.9 26.7 97 220 +1974 1 3 12 23 TONY 23.3 8.7 88 277 +1961 4 19 12 21 KIRK 41.6 76.8 92 298 +1993 6 12 0 17 ERNESTO 38.3 91.1 123 630 +1952 4 19 6 27 LESLIE 62.6 356.2 25 514 +1958 8 15 12 19 FLORENCE 63.5 251.3 32 679 +1985 11 26 12 21 KIRK 18.5 338.7 148 554 +1950 11 27 12 27 WILLIAM 27.2 326.7 106 806 +1989 11 5 0 7 MICHAEL 7.6 171.5 146 784 +1956 3 28 18 5 TONY 9.3 345.1 51 507 +1994 9 21 6 24 HELENE 49.7 65.2 135 19 +2004 5 24 6 26 HELENE 40.0 220.0 148 185 +1991 1 27 0 25 LESLIE 57.2 62.2 100 273 +1998 3 7 18 27 ISAAC 50.6 98.7 69 879 +1962 11 4 0 15 ERNESTO 58.4 133.8 164 649 +1990 5 23 12 13 HELENE 43.7 77.8 21 526 +1977 4 3 18 5 LESLIE 17.7 75.5 151 207 +1951 6 1 0 25 HELENE 67.7 87.4 23 613 +1987 4 24 6 6 GORDON 43.2 157.4 42 564 +1982 12 1 6 13 VALERIE 64.3 185.6 36 261 +1967 11 18 12 11 RAFAEL 39.7 189.2 152 220 +1967 1 27 18 18 CHRIS 63.1 249.3 152 354 +1953 7 22 0 11 MICHAEL 59.8 353.6 66 502 +1999 10 27 18 18 LESLIE 64.6 343.1 47 264 +1962 1 26 6 16 FLORENCE 47.3 351.8 157 451 +1959 2 27 12 21 WILLIAM 20.3 205.8 94 490 +1960 7 24 0 28 JOYCE 32.2 163.1 136 163 +1985 9 23 6 6 SANDY 49.7 8.3 60 66 +1978 11 23 12 9 ISAAC 23.0 5.0 53 862 +1965 6 10 12 15 SANDY 49.6 99.1 155 320 +1974 8 17 18 10 ALBERTO 19.5 14.1 65 796 +1994 6 18 18 10 OSCAR 24.7 157.4 104 777 +1969 9 4 0 12 LESLIE 39.8 193.9 124 742 +1961 3 26 0 7 SANDY 29.3 11.9 120 40 +1963 7 17 0 22 OSCAR 27.0 251.1 122 682 +1963 11 28 6 4 ISAAC 64.6 99.9 41 283 +1984 8 10 12 22 SANDY 58.2 271.3 85 894 +1982 12 5 6 1 VALERIE 16.8 131.9 92 344 +1985 1 20 12 6 ISAAC 38.4 308.4 35 807 +1966 9 18 18 28 DEBBY 25.8 213.3 39 819 +1963 6 4 12 5 KIRK 29.5 169.5 109 766 +1999 6 2 12 5 CHRIS 19.8 89.3 161 698 +1960 9 24 12 11 JOYCE 19.4 342.9 69 762 +1976 5 21 12 19 VALERIE 40.3 245.4 129 230 +1988 4 13 0 7 FLORENCE 65.5 80.2 160 789 +1967 10 13 0 23 PATTY 52.7 22.3 77 256 +1981 11 11 0 1 SANDY 65.9 250.1 25 17 +1960 4 7 0 17 RAFAEL 41.8 81.4 77 605 +1978 3 21 6 10 BERYL 25.7 181.7 148 873 +1989 12 16 12 19 ISAAC 31.4 244.5 74 528 +1997 9 8 12 23 WILLIAM 28.8 246.3 109 581 +1972 1 14 18 21 ISAAC 61.1 204.4 138 230 +1992 10 27 0 15 TONY 64.1 286.3 92 456 +1980 5 10 12 13 ALBERTO 26.1 187.2 107 9 +1994 12 22 12 12 ERNESTO 39.7 248.5 159 91 +1965 10 26 12 26 MICHAEL 49.0 343.8 32 789 +1973 9 21 6 5 WILLIAM 66.1 34.0 157 680 +1991 5 28 0 3 MICHAEL 34.3 246.9 91 337 +1960 7 1 18 23 ERNESTO 46.7 145.9 99 565 +1992 6 8 18 6 NADINE 8.1 322.0 127 293 +1965 5 24 18 9 KIRK 20.9 212.9 58 804 +1980 2 3 0 22 JOYCE 27.0 293.9 79 680 +2001 4 22 6 15 ISAAC 63.6 276.7 75 866 +1950 5 9 0 2 OSCAR 69.9 104.0 16 283 +1984 10 12 0 6 FLORENCE 59.5 185.7 45 595 +1986 5 17 18 23 KIRK 47.2 41.7 57 348 +1995 3 17 18 14 ISAAC 42.9 206.1 10 358 +1963 8 19 6 14 PATTY 36.5 29.9 138 871 +2000 11 1 0 12 WILLIAM 58.0 7.7 48 140 +1959 12 4 0 26 PATTY 10.4 298.9 86 421 +1963 8 20 12 25 PATTY 32.9 141.5 93 121 +1982 2 23 12 23 RAFAEL 13.9 105.9 131 760 +1997 10 22 18 27 GORDON 62.0 113.8 107 283 +1991 5 1 6 23 KIRK 43.2 237.4 146 85 +1952 6 16 18 28 DEBBY 9.4 196.3 93 404 +1995 3 17 12 11 GORDON 17.4 342.0 23 304 +1976 10 14 18 14 RAFAEL 62.5 105.0 99 552 +1969 8 27 18 8 WILLIAM 35.2 176.7 113 437 +1986 8 8 18 19 OSCAR 45.3 65.5 161 740 +1975 10 3 12 17 VALERIE 14.6 348.3 105 41 +1960 4 17 18 3 JOYCE 22.3 213.1 147 295 +1962 8 26 0 16 HELENE 7.2 81.1 76 183 +1957 9 5 18 18 KIRK 22.2 64.2 48 625 +1973 11 2 6 3 HELENE 13.7 205.1 81 371 +1978 2 28 0 25 OSCAR 54.1 127.5 140 475 +1952 7 18 6 8 JOYCE 8.3 348.1 95 768 +1971 9 8 18 27 MICHAEL 27.9 354.8 43 132 +2002 7 3 0 23 OSCAR 49.5 345.9 76 124 +1990 6 16 12 25 MICHAEL 18.5 352.7 150 354 +1952 7 26 6 5 GORDON 38.4 1.9 40 53 +1983 10 15 0 7 KIRK 64.4 267.8 89 790 +1966 3 23 18 4 RAFAEL 54.2 335.4 162 581 +1976 9 16 18 17 NADINE 55.6 61.7 35 229 +1992 4 12 0 24 BERYL 60.9 259.4 75 69 +1956 9 26 0 1 FLORENCE 59.2 91.6 57 391 +1977 12 15 12 18 ALBERTO 46.0 303.9 148 420 +1952 10 8 0 3 ALBERTO 42.9 162.0 159 442 +1953 7 3 6 3 RAFAEL 27.3 34.5 99 793 +1977 3 10 12 2 BERYL 59.8 178.7 14 536 +1970 2 10 12 4 ISAAC 16.5 106.1 93 398 +1984 1 28 6 12 MICHAEL 10.9 99.4 162 802 +1957 6 15 12 24 BERYL 55.3 163.8 111 211 +1993 3 9 6 7 OSCAR 27.3 109.9 32 799 +1969 12 4 18 28 HELENE 25.3 299.6 20 170 +2000 2 10 12 5 VALERIE 11.8 332.0 53 755 +1976 8 7 0 4 KIRK 59.9 100.1 128 777 +1976 2 14 0 18 VALERIE 34.6 175.3 130 473 +1952 12 4 12 21 LESLIE 30.0 204.3 64 445 +1987 6 3 0 25 KIRK 41.0 66.4 153 317 +1999 12 26 0 27 KIRK 33.2 348.5 121 43 +1955 1 25 12 8 ALBERTO 33.2 66.1 144 316 +1980 4 3 6 23 HELENE 56.2 211.6 155 401 +1994 7 14 12 12 HELENE 37.3 250.7 40 403 +1969 7 18 0 21 MICHAEL 57.5 197.2 129 543 +1986 10 1 6 6 BERYL 38.4 44.7 75 375 +1989 12 16 0 14 TONY 20.2 245.9 14 239 +1988 2 14 0 25 HELENE 7.5 264.2 58 581 +1993 6 7 12 22 TONY 45.7 48.9 73 109 +1952 2 11 0 18 MICHAEL 30.5 156.1 45 864 +1968 6 27 6 10 PATTY 40.4 185.8 94 808 +1979 8 23 6 4 GORDON 42.9 122.2 60 10 +1996 10 3 18 7 NADINE 69.8 174.3 22 198 +1993 7 26 18 8 ALBERTO 60.2 304.9 61 893 +1994 4 23 6 16 ALBERTO 7.7 211.6 98 512 +1973 2 24 12 1 ISAAC 64.3 211.9 78 296 +1977 3 25 12 25 BERYL 29.1 74.3 21 171 +2004 11 2 0 5 FLORENCE 13.3 48.7 25 508 +1958 4 17 18 14 CHRIS 21.0 294.8 81 826 +1998 1 8 12 19 OSCAR 37.7 135.4 84 539 +1964 6 2 18 5 HELENE 26.7 276.5 34 329 +1963 10 15 6 15 PATTY 9.7 266.4 43 713 +1996 1 7 18 13 FLORENCE 65.4 306.6 128 604 +1961 6 15 0 6 VALERIE 28.0 141.9 84 603 +1961 10 20 6 1 ERNESTO 58.0 4.2 27 870 +1971 7 21 18 11 JOYCE 28.4 27.6 129 748 +1975 6 25 6 14 HELENE 53.9 236.7 122 0 +1998 3 17 18 7 TONY 20.6 22.6 28 368 +1958 8 12 12 17 PATTY 54.0 288.4 46 653 +1972 12 17 6 19 MICHAEL 68.1 139.4 76 630 +1987 4 16 18 26 WILLIAM 69.8 35.8 83 392 +2000 10 2 12 1 HELENE 18.8 178.5 32 277 +1974 10 17 0 15 CHRIS 10.1 206.9 73 115 +1995 11 25 6 2 KIRK 45.9 186.6 86 337 +1966 5 4 0 8 GORDON 56.7 254.0 158 582 +1998 3 2 18 20 PATTY 24.4 112.8 58 735 +1962 12 23 12 10 HELENE 32.9 193.3 45 138 +2004 8 19 0 18 LESLIE 14.4 198.9 132 636 +1977 8 10 6 22 WILLIAM 58.6 194.6 97 587 +1955 9 18 0 15 BERYL 14.1 205.7 143 576 +1960 1 11 0 5 CHRIS 44.1 279.7 24 303 +1972 10 23 12 9 TONY 28.9 173.1 23 137 +1971 2 12 12 23 HELENE 30.1 134.4 82 90 +1962 12 3 6 2 PATTY 35.2 194.9 91 336 +1991 10 15 0 1 TONY 47.0 169.5 102 835 +1963 6 27 6 15 DEBBY 35.5 338.1 162 665 +1979 3 28 6 13 WILLIAM 55.7 112.3 57 773 +1980 11 21 0 16 SANDY 53.2 107.2 159 825 +1983 7 12 18 16 KIRK 14.2 42.5 32 508 +1960 3 23 18 11 VALERIE 54.4 150.5 99 241 +1967 11 19 18 1 MICHAEL 44.3 91.7 36 890 +1975 8 23 6 28 OSCAR 57.7 195.0 72 380 +1957 11 10 6 12 KIRK 22.1 222.0 76 137 +1952 11 1 0 3 ISAAC 55.5 86.1 74 174 +1965 2 21 18 18 RAFAEL 19.3 103.9 156 96 +1979 8 16 6 20 VALERIE 41.7 8.3 20 174 +1979 1 26 6 11 VALERIE 53.3 246.2 14 219 +1983 2 16 18 14 CHRIS 13.6 351.7 27 227 +1953 7 9 0 22 TONY 54.3 318.5 152 504 +1976 5 4 18 20 TONY 28.9 342.4 50 403 +1961 9 22 12 16 NADINE 15.8 242.6 30 651 +1996 3 24 0 27 TONY 33.2 28.9 157 288 +1985 9 2 12 27 JOYCE 44.3 192.6 25 817 +2002 4 21 6 21 DEBBY 58.8 141.2 27 881 +1980 9 20 6 24 ISAAC 8.3 23.8 42 711 +1953 1 20 12 20 WILLIAM 19.4 269.2 132 190 +1979 5 18 18 21 VALERIE 54.7 344.5 108 168 +1976 3 9 12 10 WILLIAM 29.5 131.5 115 538 +1971 4 22 0 16 CHRIS 30.0 210.6 156 704 +1985 9 6 0 21 VALERIE 35.4 335.9 38 242 +1981 5 24 6 9 RAFAEL 34.0 345.6 56 618 +1998 10 23 12 5 TONY 24.8 204.3 90 334 +1982 8 8 18 28 PATTY 50.5 154.6 65 782 +2003 4 6 18 13 WILLIAM 37.5 355.2 58 681 +1967 7 26 0 19 ERNESTO 33.1 232.6 14 759 +1997 9 18 6 17 ERNESTO 12.4 168.7 76 25 +1957 2 8 18 22 WILLIAM 55.3 35.6 63 167 +1955 10 20 12 23 DEBBY 49.1 248.4 148 127 +1962 2 24 0 7 OSCAR 37.7 292.9 121 89 +1959 4 1 6 6 OSCAR 44.3 240.6 129 618 +1982 11 20 6 10 RAFAEL 43.1 226.2 21 441 +1960 4 2 12 25 SANDY 61.7 301.9 147 596 +1975 2 24 12 2 CHRIS 59.1 159.4 96 368 +1997 5 27 18 17 MICHAEL 44.1 275.2 81 887 +1961 9 12 0 21 SANDY 68.4 188.0 159 373 +1961 10 2 0 18 ALBERTO 14.6 274.1 116 318 +2001 1 5 12 6 ISAAC 8.5 304.3 162 70 +1965 9 25 0 9 VALERIE 32.4 197.7 142 192 +1987 11 6 12 9 BERYL 7.5 164.3 57 256 +1966 11 15 0 24 FLORENCE 11.2 353.2 75 738 +1964 2 20 18 9 DEBBY 63.2 175.9 72 491 +1967 1 7 6 2 VALERIE 29.1 58.9 67 285 +1985 3 21 18 2 MICHAEL 24.3 267.8 137 265 +1992 6 23 0 7 TONY 47.6 4.2 105 323 +1951 1 19 0 25 ERNESTO 44.1 27.5 163 378 +1978 2 25 6 27 DEBBY 10.0 221.5 108 429 +1975 9 3 6 7 PATTY 57.8 60.4 70 164 +1981 6 27 12 15 RAFAEL 36.0 118.5 124 214 +1990 4 10 12 26 KIRK 13.3 25.2 84 308 +1952 3 13 12 26 HELENE 63.6 286.9 163 261 +1988 7 13 18 1 VALERIE 31.5 152.7 148 681 +1997 10 6 12 8 CHRIS 27.3 324.6 13 591 +1993 11 15 12 8 GORDON 28.0 100.7 77 638 +1986 5 11 18 12 GORDON 20.8 122.0 124 584 +1992 12 22 18 27 KIRK 36.5 55.6 150 835 +1998 7 11 0 6 ERNESTO 22.3 114.2 75 147 +2003 6 24 12 24 FLORENCE 43.0 334.2 73 558 +2004 8 24 0 25 FLORENCE 34.5 275.3 116 299 +1986 5 5 12 2 DEBBY 56.3 27.5 67 400 +1961 7 2 6 23 ERNESTO 32.6 12.7 126 64 +1955 12 3 18 21 LESLIE 49.4 14.0 51 94 +1989 4 8 0 13 TONY 63.7 3.0 115 183 +1960 11 23 18 2 JOYCE 63.3 288.2 81 137 +1997 10 20 18 25 SANDY 30.9 145.8 68 563 +1956 5 26 6 11 SANDY 10.0 54.6 160 548 +1988 1 16 0 19 BERYL 27.2 300.5 158 208 +1980 10 20 0 7 CHRIS 20.1 211.6 134 613 +1965 8 16 18 10 FLORENCE 26.8 57.9 22 209 +2002 11 19 6 27 HELENE 25.7 319.2 81 182 +1997 9 25 12 14 ISAAC 32.5 165.5 91 337 +1963 2 27 6 21 HELENE 13.0 39.1 148 835 +1956 9 12 12 2 KIRK 14.9 213.3 37 892 +1966 10 7 0 21 BERYL 56.7 196.4 32 144 +1967 11 23 18 20 NADINE 67.6 119.7 151 518 +1961 10 15 0 11 SANDY 58.2 310.6 131 742 +1985 2 17 12 14 JOYCE 33.0 28.6 21 425 +1956 3 21 18 5 CHRIS 25.7 4.6 132 673 +1975 2 5 12 24 NADINE 69.7 160.4 18 895 +1988 2 23 12 26 LESLIE 49.6 109.6 32 407 +1986 8 25 18 24 CHRIS 64.8 176.0 38 61 +1960 4 7 18 12 HELENE 49.0 285.7 22 491 +1950 6 19 6 1 RAFAEL 42.5 51.9 99 299 +1966 1 8 6 13 FLORENCE 25.3 240.4 64 600 +1995 11 4 18 12 WILLIAM 64.1 282.8 104 374 +1983 12 20 18 10 NADINE 58.0 15.3 100 624 +1965 9 14 18 22 WILLIAM 64.0 90.9 64 879 +1982 5 21 12 25 VALERIE 49.0 2.7 20 243 +1989 11 8 18 24 FLORENCE 37.9 15.8 35 615 +1970 6 23 18 25 JOYCE 12.1 38.9 150 660 +1956 8 21 0 12 ALBERTO 22.1 13.4 144 445 +1956 1 8 12 18 BERYL 52.5 259.2 135 3 +1974 6 13 18 17 ISAAC 29.2 341.2 87 484 +1974 3 12 0 23 FLORENCE 42.3 321.1 161 394 +1983 2 26 6 9 FLORENCE 64.4 251.3 11 561 +1972 6 24 0 25 ALBERTO 25.9 18.1 123 134 +1956 9 21 6 1 DEBBY 65.3 88.3 78 299 +1998 9 3 12 13 ALBERTO 67.1 114.9 43 247 +1998 6 11 18 18 MICHAEL 22.6 117.3 47 53 +1978 11 5 6 4 PATTY 20.4 3.8 156 540 +1971 10 12 12 28 GORDON 13.9 278.5 134 341 +1951 5 20 6 23 BERYL 53.8 216.3 128 772 +1965 8 25 12 27 NADINE 36.8 336.0 161 720 +1993 7 16 6 14 PATTY 56.7 33.9 65 39 +1989 7 13 0 2 ERNESTO 30.1 194.8 139 836 +1974 9 23 0 18 MICHAEL 22.2 0.1 70 222 +1984 12 17 12 18 FLORENCE 57.3 144.9 12 719 +2002 3 24 18 28 ISAAC 37.6 329.9 160 123 +1960 9 10 0 28 JOYCE 67.4 340.1 118 1 +1959 6 11 0 16 VALERIE 35.6 172.2 158 149 +1964 1 21 12 10 ISAAC 56.2 91.9 124 119 +1993 5 24 0 8 VALERIE 21.3 207.8 149 615 +1981 5 21 12 8 GORDON 64.4 164.6 53 450 +1972 8 4 12 6 BERYL 20.6 180.4 60 525 +1972 5 23 18 5 JOYCE 19.0 113.1 54 167 +1982 12 4 18 3 ISAAC 35.0 148.9 113 641 +1984 10 12 0 27 HELENE 61.7 205.1 27 129 +1972 8 15 6 2 ALBERTO 68.8 351.5 61 451 +1961 8 22 0 1 ERNESTO 25.1 48.7 33 717 +1950 8 28 18 19 ALBERTO 68.8 179.3 101 124 +1991 7 4 12 14 RAFAEL 47.7 121.5 141 541 +1992 9 28 12 22 KIRK 66.2 8.7 80 170 +1962 4 23 6 19 BERYL 33.7 280.0 18 471 +1996 11 2 0 10 NADINE 59.2 230.7 15 898 +1966 10 6 18 12 MICHAEL 48.8 287.5 126 329 +1972 12 5 12 25 TONY 38.4 257.3 52 748 +1992 5 6 18 22 GORDON 60.4 159.3 112 144 +2002 9 3 12 13 HELENE 31.2 328.2 129 708 +1977 12 27 18 15 WILLIAM 42.4 41.8 162 482 +1988 3 2 6 10 DEBBY 18.3 309.0 25 420 +1956 6 5 0 1 MICHAEL 21.2 355.7 133 228 +1979 1 2 6 2 ALBERTO 52.4 37.7 122 802 +2002 10 24 0 22 GORDON 57.9 73.3 43 75 +1993 3 9 0 14 WILLIAM 61.0 34.4 151 493 +1974 6 7 6 11 ALBERTO 30.0 302.9 66 95 +1967 12 26 18 21 LESLIE 19.3 189.6 104 851 +2000 3 5 12 1 OSCAR 45.5 350.4 59 706 +1995 5 2 12 16 ERNESTO 39.2 281.2 128 835 +1952 1 7 18 28 PATTY 52.8 347.5 66 683 +1983 8 20 12 22 ISAAC 31.1 5.0 89 131 +1993 5 19 6 20 FLORENCE 25.9 245.5 134 400 +1966 6 22 12 1 BERYL 31.3 77.1 100 26 +1960 5 12 0 26 FLORENCE 67.9 59.9 27 194 +1971 9 23 0 20 OSCAR 13.8 281.3 70 115 +1991 6 18 0 10 PATTY 42.9 0.8 90 78 +1993 2 2 18 5 HELENE 40.4 85.8 107 144 +1997 12 11 6 5 DEBBY 30.6 85.6 142 736 +1963 3 10 18 13 SANDY 39.0 236.1 96 148 +1987 2 8 0 10 GORDON 38.8 227.0 77 102 +1991 11 14 6 21 WILLIAM 29.8 319.1 149 323 +1995 7 16 18 13 RAFAEL 59.3 79.6 47 214 +1977 2 7 18 1 ALBERTO 28.7 131.7 122 817 +1973 7 28 12 10 ALBERTO 48.6 113.3 149 520 +1967 11 4 6 2 VALERIE 16.0 60.8 145 473 +1998 12 28 12 22 ERNESTO 32.0 103.9 131 467 +1958 10 24 18 27 DEBBY 56.5 96.0 63 506 +1994 1 18 12 27 GORDON 25.4 324.4 42 343 +1954 9 5 0 23 LESLIE 38.9 153.1 104 607 +1996 5 18 0 11 MICHAEL 34.9 303.5 164 711 +1964 7 15 0 6 FLORENCE 31.7 239.7 60 150 +2002 8 21 6 18 NADINE 49.9 209.4 130 623 +1979 1 17 6 12 NADINE 29.2 227.3 93 639 +1959 7 8 12 24 ERNESTO 7.9 78.0 14 119 +1953 10 13 12 12 ERNESTO 32.7 187.7 12 293 +2000 5 12 12 4 TONY 37.5 289.0 127 91 +1962 9 11 6 13 VALERIE 60.6 37.4 57 44 +1956 1 24 18 23 GORDON 64.7 196.7 51 731 +2004 2 10 0 10 BERYL 21.2 149.1 114 481 +1974 10 7 12 22 OSCAR 62.2 74.7 109 24 +1993 7 15 12 26 NADINE 35.7 70.3 106 646 +1979 6 19 12 24 ISAAC 15.1 255.6 72 691 +1954 7 27 6 26 ALBERTO 48.2 98.0 33 247 +1974 3 25 18 22 FLORENCE 66.1 18.5 161 775 +1973 12 1 6 10 GORDON 20.7 118.1 155 631 +1999 5 19 0 21 KIRK 39.1 42.0 56 767 +1994 5 10 12 1 TONY 55.4 219.4 140 90 +1977 3 16 6 21 PATTY 69.3 229.0 154 294 +1973 8 6 0 4 CHRIS 27.8 125.2 156 255 +1987 3 28 0 9 ERNESTO 69.3 151.0 15 307 +1988 5 27 12 24 MICHAEL 26.0 185.5 82 280 +1962 11 14 0 17 CHRIS 17.8 109.8 20 628 +1981 6 12 18 20 VALERIE 67.4 277.2 129 171 +1987 6 6 0 3 ISAAC 18.8 266.3 60 570 +1988 11 18 12 26 MICHAEL 40.5 131.7 156 321 +1987 8 21 0 17 SANDY 55.2 111.6 56 794 +1998 8 10 6 13 ALBERTO 20.1 304.8 136 892 +1988 9 14 12 23 ISAAC 10.0 145.7 100 821 +1969 2 21 6 22 NADINE 33.1 154.3 55 566 +1965 7 3 12 19 JOYCE 31.2 124.2 140 210 +1960 1 14 18 4 SANDY 31.6 311.7 143 646 +1969 10 12 6 14 JOYCE 24.8 188.8 52 454 +1962 11 22 12 23 RAFAEL 10.5 90.9 137 214 +1969 4 4 12 28 ISAAC 49.7 116.8 52 323 +1963 7 9 12 25 RAFAEL 41.1 327.2 41 591 +1989 9 24 18 2 SANDY 58.2 121.7 63 272 +1965 2 15 18 22 VALERIE 38.5 34.2 103 812 +1995 2 18 18 24 DEBBY 51.7 89.2 49 190 +1980 5 6 12 5 NADINE 7.3 68.6 107 323 +1973 11 3 12 21 SANDY 41.6 277.4 117 732 +1987 4 1 12 2 WILLIAM 69.7 247.8 115 31 +1992 7 21 6 12 HELENE 33.3 292.4 105 814 +1967 3 9 0 15 DEBBY 40.0 315.3 47 736 +1955 11 19 0 8 VALERIE 9.9 169.5 62 326 +1983 2 13 18 1 FLORENCE 16.5 96.4 156 377 +1987 9 13 6 26 ERNESTO 10.9 292.9 13 391 +1951 6 27 6 18 TONY 52.5 219.4 18 71 +1984 7 24 12 12 SANDY 41.6 48.8 137 671 +1970 2 14 6 10 BERYL 46.1 43.8 119 788 +1951 4 27 0 19 HELENE 60.6 112.4 126 112 +1979 8 26 18 23 ALBERTO 18.8 223.2 156 834 +1975 7 2 12 26 JOYCE 23.0 101.1 34 618 +1996 3 25 18 5 PATTY 61.4 13.9 135 369 +1957 1 18 18 13 TONY 64.4 119.5 43 423 +1998 12 22 12 20 VALERIE 23.3 282.7 151 278 +1974 6 21 18 27 PATTY 52.9 15.9 133 169 +1987 5 28 18 12 WILLIAM 42.4 287.4 58 446 +1977 10 6 6 18 TONY 66.0 287.0 51 263 +2003 7 4 12 18 FLORENCE 30.3 170.8 149 785 +1984 12 4 6 24 ISAAC 35.1 7.3 22 386 +1979 9 21 0 5 TONY 60.5 82.2 134 737 +1950 11 9 18 5 NADINE 39.6 229.5 159 220 +1958 5 23 6 22 CHRIS 57.1 326.3 28 558 +1959 10 12 12 21 VALERIE 42.7 308.6 149 365 +1968 5 17 12 25 GORDON 23.5 95.5 70 706 +1974 9 9 12 17 NADINE 33.3 313.1 33 863 +1951 2 1 18 10 WILLIAM 28.8 33.4 76 879 +1990 4 20 6 25 KIRK 67.6 245.7 121 353 +1959 7 1 6 23 MICHAEL 34.5 166.2 158 647 +1999 9 14 0 1 OSCAR 58.5 188.1 57 34 +1995 3 7 0 19 BERYL 51.9 355.2 104 553 +1963 7 19 6 24 TONY 7.7 36.5 64 66 +1998 8 8 12 27 LESLIE 7.2 89.5 141 705 +1959 5 26 12 19 VALERIE 7.2 195.7 148 440 +1957 3 9 18 5 FLORENCE 45.3 108.1 76 74 +1992 3 1 6 10 KIRK 27.7 305.1 55 678 +2002 8 16 12 7 WILLIAM 32.1 276.2 55 328 +1968 1 17 0 14 LESLIE 62.3 167.0 146 34 +1982 3 12 6 14 KIRK 7.9 282.1 107 64 +1957 5 20 6 21 PATTY 50.7 204.0 87 68 +1953 11 28 12 6 GORDON 34.2 164.0 32 856 +1986 1 16 6 8 LESLIE 67.2 353.1 84 373 +1964 9 22 12 19 GORDON 50.3 152.0 148 773 +1990 7 1 0 27 RAFAEL 65.7 102.6 76 5 +2004 1 11 0 23 KIRK 65.5 240.9 138 778 +1973 2 11 18 8 GORDON 26.1 23.5 113 551 +1993 9 9 0 4 MICHAEL 66.4 315.9 128 49 +1985 6 20 18 12 OSCAR 34.2 206.9 148 535 +1950 11 8 6 15 NADINE 7.7 262.1 130 548 +1955 3 4 18 22 PATTY 41.4 13.1 133 179 +1954 11 27 12 15 JOYCE 44.7 144.4 107 836 +1964 12 10 6 9 BERYL 30.6 113.1 133 681 +1971 10 19 12 22 ALBERTO 20.8 225.9 139 727 +1957 4 26 6 9 OSCAR 46.9 0.5 131 372 +1950 9 2 0 22 HELENE 63.2 12.3 94 359 +1965 1 27 12 28 BERYL 66.6 154.4 108 260 +1950 7 11 0 10 LESLIE 34.0 65.2 124 714 +2000 4 23 0 11 GORDON 45.3 31.8 149 588 +1985 1 12 12 12 PATTY 29.9 310.5 110 508 +1958 1 19 18 14 VALERIE 33.1 49.7 48 645 +1978 1 13 12 7 PATTY 21.7 316.4 97 582 +1970 3 10 6 20 WILLIAM 20.3 83.1 39 670 +1996 3 15 12 28 KIRK 54.5 223.0 162 553 +1999 11 26 0 1 LESLIE 53.7 28.3 63 745 +1962 2 27 12 21 OSCAR 57.2 195.3 44 360 +1974 5 14 6 8 GORDON 7.2 346.6 32 714 +1996 9 26 12 25 DEBBY 40.2 215.0 89 326 +1958 5 14 18 4 ALBERTO 35.0 164.1 125 598 +1987 9 12 12 28 OSCAR 37.0 176.6 24 54 +1993 3 21 12 1 VALERIE 39.4 31.1 78 806 +1960 9 16 18 26 SANDY 52.0 207.4 150 705 +1971 2 1 0 4 ISAAC 69.5 324.9 107 333 +2002 12 16 12 6 JOYCE 10.6 142.2 16 269 +1954 8 24 18 25 GORDON 62.8 228.1 34 623 +1993 3 24 18 22 FLORENCE 17.7 184.2 107 157 +1967 3 17 0 27 OSCAR 58.0 265.3 22 410 +1952 4 22 18 8 FLORENCE 49.7 293.1 154 352 +1981 7 9 18 23 CHRIS 60.2 41.4 32 159 +1957 8 28 0 16 KIRK 40.9 249.6 83 141 +1984 6 12 12 4 WILLIAM 49.7 322.8 27 590 +1975 7 8 18 7 ALBERTO 15.5 352.9 139 179 +1953 4 19 12 19 DEBBY 14.8 354.9 81 26 +1990 8 17 0 7 DEBBY 51.4 12.5 103 634 +2002 3 12 12 25 CHRIS 55.4 305.7 26 85 +1953 10 12 0 5 ERNESTO 45.6 184.9 19 644 +1979 3 18 0 12 RAFAEL 27.1 256.9 53 750 +1994 7 28 12 28 ALBERTO 50.2 49.4 37 563 +1960 7 16 0 14 VALERIE 31.8 75.3 69 616 +1961 6 15 0 24 TONY 49.7 171.8 113 64 +1960 6 22 12 17 PATTY 20.9 294.6 71 749 +1965 11 19 0 5 TONY 55.2 63.9 88 29 +1973 2 20 0 4 DEBBY 48.4 313.6 96 305 +1980 8 20 18 4 DEBBY 39.2 44.9 18 352 +1954 1 3 0 13 BERYL 70.0 226.3 98 561 +2004 12 25 18 5 HELENE 26.6 185.9 139 876 +1955 7 24 6 18 TONY 24.2 65.1 68 663 +1972 7 11 12 16 PATTY 41.9 137.5 50 852 +1964 5 20 18 1 DEBBY 59.2 134.8 46 609 +1986 5 2 6 13 OSCAR 61.6 228.7 145 483 +1993 2 8 18 22 RAFAEL 68.1 121.4 34 699 +1982 7 25 6 14 KIRK 10.4 116.0 58 280 +1989 10 5 12 21 RAFAEL 45.2 77.8 137 565 +1961 3 9 12 25 ALBERTO 11.6 297.2 105 110 +1952 1 10 6 9 GORDON 62.0 337.6 78 599 +1992 2 8 18 7 GORDON 24.0 288.5 101 269 +1975 6 3 0 4 ERNESTO 16.5 246.6 104 417 +1968 9 12 0 2 GORDON 53.8 117.4 139 75 +1982 5 2 12 21 BERYL 21.3 184.6 109 210 +1990 12 24 6 23 RAFAEL 60.3 337.7 153 603 +1967 4 17 18 7 DEBBY 67.8 100.7 47 220 +1995 5 17 18 14 ERNESTO 28.3 20.9 34 630 +1954 7 7 18 21 CHRIS 21.3 100.9 86 550 +2002 2 3 12 22 KIRK 49.0 254.3 132 745 +1975 12 5 0 4 GORDON 23.8 210.9 37 27 +1989 12 26 18 3 CHRIS 40.2 310.3 86 833 +1962 3 12 18 6 OSCAR 33.3 140.1 158 571 +2003 10 10 18 11 KIRK 22.4 357.2 52 499 +1994 10 13 18 6 VALERIE 46.7 133.4 94 598 +1961 12 13 6 13 SANDY 36.4 294.2 89 31 +2003 6 1 6 6 BERYL 27.6 57.3 154 258 +1953 1 7 6 18 FLORENCE 42.3 133.8 36 781 +1956 6 6 18 28 WILLIAM 35.9 10.0 72 83 +2000 6 4 0 23 FLORENCE 27.9 283.9 90 88 +1956 12 4 18 24 ALBERTO 48.9 306.7 158 695 +1977 1 27 6 19 FLORENCE 19.0 140.9 133 858 +1978 4 10 18 25 NADINE 20.1 197.1 50 310 +1960 4 5 6 2 KIRK 58.5 308.8 57 560 +1971 11 14 6 24 ERNESTO 68.0 212.5 49 514 +1972 10 22 0 28 SANDY 14.3 159.5 83 220 +1983 12 25 18 14 VALERIE 13.8 60.5 43 623 +1961 4 22 12 4 ALBERTO 53.2 74.3 51 527 +1959 9 13 6 28 JOYCE 7.4 284.9 44 67 +1985 9 15 12 27 SANDY 41.1 38.9 68 308 +1956 1 13 12 11 ERNESTO 54.7 215.5 72 869 +1962 3 19 18 8 BERYL 43.2 341.9 120 825 +1996 7 20 12 26 SANDY 26.4 75.3 60 894 +1957 7 11 12 25 HELENE 37.4 132.6 67 718 +1986 8 13 12 8 WILLIAM 58.1 238.7 156 343 +2000 3 27 6 2 DEBBY 36.9 208.2 47 42 +1959 4 13 0 21 ERNESTO 65.3 45.3 96 763 +1995 6 13 6 1 ISAAC 61.0 293.6 126 180 +1989 10 23 0 12 NADINE 55.4 263.3 32 137 +1966 3 18 18 21 JOYCE 61.8 6.3 22 0 +1988 1 7 12 20 ISAAC 44.6 354.6 37 169 +1982 6 22 6 1 HELENE 34.6 188.9 95 817 +2004 10 9 18 4 DEBBY 8.5 100.4 37 544 +1959 4 15 0 1 WILLIAM 55.5 198.9 98 806 +1954 12 7 6 27 SANDY 25.2 0.1 24 578 +1981 8 5 12 2 JOYCE 61.1 294.3 29 460 +1996 1 12 18 27 SANDY 26.6 253.7 136 373 +1965 11 23 0 25 JOYCE 7.1 114.2 81 27 +1988 12 27 18 24 HELENE 21.7 157.5 49 247 +1963 10 11 12 10 CHRIS 26.4 308.1 148 228 +1982 9 11 12 8 TONY 68.4 0.3 29 501 +1964 10 27 6 21 FLORENCE 62.3 247.0 159 567 +1970 10 19 12 12 PATTY 17.8 3.4 156 280 +1955 12 7 12 12 JOYCE 22.9 92.4 86 714 +1986 7 11 12 14 MICHAEL 63.8 318.2 136 899 +2002 10 12 6 19 PATTY 28.8 256.5 130 663 +1997 10 8 12 4 VALERIE 68.8 182.6 108 619 +1997 7 12 12 11 GORDON 67.5 90.3 72 136 +1980 9 8 12 4 TONY 16.5 296.2 34 510 +1957 11 22 18 9 RAFAEL 46.0 158.5 27 226 +1984 12 25 0 1 TONY 69.7 317.0 25 423 +1958 7 19 0 20 ISAAC 32.7 152.6 143 530 +1973 3 26 6 4 GORDON 17.8 139.5 86 577 +1978 4 4 18 1 BERYL 13.2 94.0 101 497 +1957 12 27 18 7 BERYL 22.5 225.8 108 7 +1969 10 6 6 14 BERYL 41.1 37.9 150 499 +1957 8 21 18 13 ALBERTO 22.6 133.9 56 132 +1952 3 4 18 21 LESLIE 37.8 317.5 119 719 +1999 2 9 12 7 FLORENCE 23.7 195.0 60 265 +1967 12 8 6 18 SANDY 28.8 143.8 77 506 +1991 4 12 12 20 VALERIE 54.3 94.2 23 665 +1965 2 25 0 7 DEBBY 51.3 266.5 101 579 +1991 9 14 12 13 ISAAC 7.2 275.4 85 712 +1962 2 23 18 8 NADINE 21.8 129.7 38 230 +1953 6 9 6 27 VALERIE 43.2 207.5 55 255 +1986 2 14 6 13 KIRK 50.9 242.7 129 78 +1975 12 2 12 25 GORDON 10.2 214.7 76 776 +1973 7 4 12 13 RAFAEL 21.9 93.0 84 241 +1952 8 11 12 9 TONY 35.4 283.1 92 793 +1966 7 25 0 7 TONY 66.3 285.9 107 655 +1951 7 28 12 6 ERNESTO 22.7 320.4 132 444 +2004 9 24 0 15 ISAAC 44.6 109.2 15 153 +1997 9 20 12 13 CHRIS 23.0 210.1 117 656 +1958 3 6 18 17 MICHAEL 67.2 80.5 117 480 +1992 9 21 18 6 KIRK 39.4 160.6 96 129 +1960 2 23 12 19 RAFAEL 32.5 86.0 113 895 +1963 8 7 18 27 ISAAC 66.7 87.7 136 71 +1995 3 28 0 27 TONY 56.1 163.4 25 242 +1957 12 24 18 24 ISAAC 68.5 224.7 116 797 +1962 12 20 0 20 VALERIE 40.8 273.8 43 505 +1964 4 24 6 11 KIRK 32.6 322.8 59 869 +1975 2 3 18 19 SANDY 47.8 41.3 126 172 +1983 10 4 0 17 HELENE 15.7 261.0 141 535 +1970 7 15 12 5 NADINE 39.2 173.6 67 203 +1977 10 18 6 22 ERNESTO 21.2 154.9 114 637 +2003 12 20 18 8 BERYL 26.6 8.9 124 172 +1981 1 6 6 14 JOYCE 63.8 192.4 127 167 +1970 4 6 6 17 SANDY 64.2 26.2 93 853 +1995 12 25 18 25 ALBERTO 37.7 236.4 81 194 +1975 8 20 0 14 HELENE 54.8 218.6 98 448 +2000 3 15 18 20 PATTY 55.8 11.4 148 615 +1987 3 8 12 3 VALERIE 27.4 100.6 24 293 +1966 2 8 0 15 FLORENCE 64.7 205.9 112 436 +1988 1 16 12 18 DEBBY 39.4 166.1 63 382 +1969 9 8 12 16 NADINE 38.5 235.0 122 319 +1957 6 8 18 1 CHRIS 41.1 334.3 15 463 +1981 3 10 6 28 VALERIE 61.9 292.1 108 110 +1984 4 6 0 20 VALERIE 48.6 172.9 70 83 +1982 2 3 12 25 RAFAEL 50.3 192.1 42 753 +1990 8 15 18 7 BERYL 15.3 94.0 13 88 +2003 10 27 18 4 ERNESTO 39.8 48.0 39 88 +1977 9 7 18 8 ALBERTO 40.0 185.0 115 476 +1962 2 10 12 1 RAFAEL 15.3 42.5 115 103 +1980 10 16 0 3 FLORENCE 44.0 194.2 25 9 +1958 11 2 12 6 ISAAC 44.1 173.7 76 237 +1959 12 7 18 5 GORDON 51.8 270.0 94 165 +1950 2 4 12 25 NADINE 25.8 350.0 122 224 +1972 7 3 12 7 SANDY 36.3 110.5 158 482 +1993 3 4 12 21 DEBBY 60.3 304.0 108 116 +1962 6 26 12 22 FLORENCE 8.9 237.2 87 425 +1950 8 27 6 22 ALBERTO 41.1 40.7 132 649 +2000 2 18 12 24 TONY 45.8 49.9 155 895 +1964 5 6 0 5 SANDY 66.1 350.9 51 389 +1964 1 22 12 11 MICHAEL 25.9 216.4 132 296 +1979 11 12 12 3 OSCAR 21.4 36.9 155 537 +1954 11 9 18 18 ALBERTO 37.0 253.4 40 271 +1965 5 13 12 9 LESLIE 68.0 209.6 57 863 +1965 9 4 12 11 NADINE 61.4 300.4 29 443 +2003 6 27 12 17 LESLIE 28.9 353.4 53 820 +1986 4 6 6 17 FLORENCE 34.2 350.5 137 890 +1984 9 4 12 17 TONY 21.4 227.4 36 33 +1952 10 8 18 23 DEBBY 30.4 252.3 115 611 +1952 6 10 0 3 BERYL 67.6 327.6 128 103 +1974 12 6 12 16 RAFAEL 34.7 299.3 81 208 +1958 7 8 0 28 JOYCE 38.9 181.9 107 91 +1994 7 18 12 13 PATTY 45.4 295.5 147 241 +1975 3 21 0 17 RAFAEL 12.0 192.4 148 317 +1956 5 1 0 2 NADINE 47.1 151.1 22 439 +1989 8 25 0 3 OSCAR 11.9 254.0 135 633 +1958 3 27 18 22 FLORENCE 62.3 237.0 127 441 +1971 8 18 0 25 ERNESTO 54.3 111.7 83 741 +1970 2 27 18 8 DEBBY 57.3 103.0 122 123 +1964 5 4 18 2 CHRIS 66.6 357.5 63 471 +1983 8 7 6 7 OSCAR 61.1 153.2 121 494 +1951 2 27 6 13 ALBERTO 25.5 171.3 157 780 +1969 12 20 18 27 CHRIS 43.9 46.5 46 336 +1997 4 18 12 24 JOYCE 38.0 67.0 143 367 +1996 8 7 0 20 SANDY 54.8 280.7 77 350 +1964 9 11 6 6 NADINE 35.6 14.7 104 457 +1959 7 12 0 21 MICHAEL 55.4 236.2 153 605 +1956 7 9 6 3 KIRK 58.6 193.4 71 898 +1964 12 15 12 15 ERNESTO 28.9 226.3 86 807 +1984 7 9 0 4 KIRK 20.3 324.4 119 410 +1958 11 20 6 24 KIRK 19.4 330.2 154 215 +1986 7 19 6 6 BERYL 57.1 83.0 75 428 +1968 2 14 12 24 JOYCE 52.1 287.8 86 441 +1963 8 6 6 10 NADINE 16.7 247.8 46 526 +1985 2 2 6 22 RAFAEL 68.2 314.3 32 370 +1958 4 10 18 15 TONY 27.2 238.1 76 250 +1982 1 15 12 3 GORDON 26.0 178.4 96 697 +1974 2 14 6 12 RAFAEL 53.8 119.8 87 89 +2003 12 1 12 5 SANDY 51.8 274.0 46 683 +1980 8 19 6 14 DEBBY 56.4 289.8 95 174 +1955 10 23 18 3 FLORENCE 21.6 193.5 34 450 +1960 10 24 12 8 ALBERTO 40.9 57.7 147 603 +1978 5 4 0 9 DEBBY 8.6 19.5 156 257 +2004 4 17 0 9 BERYL 30.8 145.2 102 463 +1999 2 12 0 1 FLORENCE 7.7 27.3 38 229 +1973 12 14 18 20 NADINE 43.5 109.6 87 388 +2000 9 11 12 6 FLORENCE 9.8 127.6 92 175 +1994 1 5 18 20 TONY 47.7 8.3 11 135 +2002 12 22 0 1 ISAAC 34.5 333.9 119 412 +1982 8 13 18 5 BERYL 36.0 173.4 42 564 +1979 2 28 18 23 BERYL 17.9 122.8 105 258 +1960 1 15 18 28 LESLIE 9.0 99.7 45 404 +1982 2 3 12 13 GORDON 38.4 149.5 94 216 +1959 3 8 12 19 GORDON 35.3 193.0 13 59 +1982 7 19 12 3 NADINE 65.5 207.1 81 859 +1980 6 27 12 20 FLORENCE 52.4 89.3 160 198 +1996 4 5 6 15 DEBBY 53.8 258.2 42 135 +2002 3 4 18 24 VALERIE 21.3 110.2 163 893 +1978 6 14 12 12 NADINE 60.9 216.3 14 460 +2003 7 14 18 2 CHRIS 20.9 200.2 59 761 +1962 5 6 6 14 LESLIE 35.8 351.9 136 112 +1995 2 1 6 23 LESLIE 27.7 233.3 84 578 +1973 8 17 6 17 ERNESTO 22.3 42.5 110 67 +1993 9 27 6 21 KIRK 44.0 331.8 101 891 +1995 2 25 6 20 PATTY 40.0 276.9 136 192 +1963 2 25 0 14 ALBERTO 19.3 301.1 60 45 +1968 12 21 18 21 ERNESTO 17.6 61.2 129 372 +1999 10 18 0 22 DEBBY 10.7 167.6 92 446 +1981 7 20 12 28 ERNESTO 7.5 46.1 147 140 +1958 3 18 0 22 FLORENCE 61.7 141.6 63 832 +1973 11 4 18 15 DEBBY 8.3 198.5 40 600 +1961 7 18 6 10 OSCAR 28.7 329.5 41 821 +1958 7 11 0 5 KIRK 42.3 356.4 44 184 +1981 7 1 18 11 VALERIE 12.3 193.5 60 618 +1978 6 4 6 21 HELENE 18.5 197.3 99 171 +1996 3 14 12 8 ERNESTO 50.1 240.9 86 166 +1966 2 10 18 22 BERYL 63.5 308.8 125 474 +1994 11 12 6 3 MICHAEL 37.7 25.7 70 606 +1990 9 5 18 9 VALERIE 39.2 289.5 136 736 +1986 9 8 12 18 MICHAEL 44.5 125.7 85 264 +2001 7 20 0 28 KIRK 39.5 101.1 107 657 +2000 5 20 0 23 OSCAR 49.8 135.4 34 351 +1971 5 8 6 25 GORDON 26.8 172.6 10 422 +1962 6 22 12 13 BERYL 43.6 203.2 112 70 +1974 8 25 6 5 GORDON 21.9 232.3 72 409 +1992 12 11 12 4 MICHAEL 12.5 11.1 39 210 +1961 2 1 0 21 SANDY 50.7 210.5 112 390 +1997 11 15 18 26 DEBBY 50.8 138.3 140 666 +1988 5 7 0 27 VALERIE 35.6 253.0 126 878 +2003 7 11 18 21 LESLIE 39.9 202.2 114 443 +1968 7 2 6 1 GORDON 11.7 358.0 159 587 +1960 3 7 6 2 RAFAEL 13.5 188.9 20 640 +1957 11 24 0 6 GORDON 39.6 173.6 36 592 +1973 8 24 18 26 BERYL 30.7 310.3 153 107 +1996 1 14 18 15 FLORENCE 67.9 274.9 66 885 +1953 8 1 0 9 NADINE 52.4 178.5 155 529 +1985 4 18 6 21 RAFAEL 38.1 11.0 20 363 +1976 6 12 18 13 TONY 66.9 265.9 74 415 +2001 10 1 12 25 ERNESTO 22.5 352.6 57 680 +1960 9 28 18 6 TONY 68.0 288.5 92 575 +1990 12 1 6 25 LESLIE 26.9 140.9 146 422 +1966 4 11 6 4 KIRK 67.1 45.8 163 424 +1950 5 10 0 23 ALBERTO 56.2 284.1 19 248 +1986 2 10 12 27 TONY 32.2 102.9 69 667 +1962 7 26 0 4 ERNESTO 56.3 230.1 14 140 +1952 4 10 12 7 OSCAR 35.5 270.1 115 142 +1974 2 2 0 28 OSCAR 27.0 345.3 158 276 +2004 6 1 6 15 CHRIS 32.9 350.7 82 607 +1993 5 10 6 17 ISAAC 37.5 49.2 27 414 +1986 2 12 0 7 SANDY 33.3 188.9 59 683 +1974 12 12 12 3 ISAAC 52.1 232.6 155 382 +1968 12 20 18 4 ISAAC 60.5 218.0 143 875 +1973 3 1 6 8 MICHAEL 63.9 177.5 80 651 +1957 8 19 0 27 ERNESTO 32.3 243.2 111 421 +1970 5 24 12 18 GORDON 26.3 92.6 38 367 +1985 11 5 6 23 ALBERTO 60.9 336.0 57 212 +1996 3 15 18 24 OSCAR 15.5 22.4 21 157 +1981 2 24 12 7 MICHAEL 55.7 280.8 162 470 +1976 4 6 12 27 SANDY 49.8 319.0 125 554 +1999 8 8 6 23 HELENE 56.6 170.7 25 434 +1976 12 9 18 22 ERNESTO 57.9 69.4 137 13 +2002 6 10 18 18 KIRK 7.9 267.1 150 254 +1961 4 15 0 26 WILLIAM 44.8 201.3 11 760 +1974 6 10 6 13 ALBERTO 63.2 127.7 35 583 +1969 10 22 0 7 CHRIS 20.0 306.3 58 137 +1988 9 15 0 24 PATTY 58.6 199.6 60 528 +1953 11 5 0 4 ERNESTO 38.6 5.1 40 11 +1982 12 26 12 8 OSCAR 48.2 113.9 135 507 +1986 9 2 18 19 DEBBY 53.3 161.3 94 650 +1978 1 27 6 5 SANDY 26.2 233.3 91 549 +1957 6 6 18 8 NADINE 34.7 79.4 59 548 +1974 3 6 18 27 MICHAEL 16.4 196.1 13 882 +2001 8 18 18 5 ALBERTO 39.2 209.1 164 358 +1951 3 14 18 10 BERYL 66.7 267.5 67 675 +1977 10 10 0 21 LESLIE 48.0 155.9 115 547 +1972 10 20 6 23 PATTY 10.0 141.8 45 658 +2004 8 9 6 28 JOYCE 64.7 162.3 153 10 +1959 10 1 12 22 ERNESTO 33.0 232.1 108 788 +1984 4 1 6 24 ERNESTO 58.4 101.2 42 566 +1976 9 9 12 15 FLORENCE 28.4 302.5 136 826 +2000 1 22 6 26 FLORENCE 39.3 261.6 134 253 +1985 7 9 6 2 HELENE 50.4 244.3 16 863 +1963 5 21 18 26 DEBBY 26.0 333.6 123 553 +1995 7 19 12 9 HELENE 31.8 115.9 66 780 +1974 3 11 0 23 MICHAEL 42.3 145.2 19 242 +1963 7 7 6 22 GORDON 19.8 306.6 155 196 +1953 9 15 6 9 WILLIAM 20.8 278.7 60 82 +1962 11 1 12 14 HELENE 39.1 231.5 54 269 +1952 8 24 12 21 JOYCE 13.7 65.6 115 73 +1977 10 25 12 25 TONY 42.1 197.0 42 468 +1976 6 12 6 1 GORDON 33.6 74.7 138 244 +1956 11 4 18 28 BERYL 49.0 249.8 130 644 +1996 6 10 18 3 GORDON 27.0 78.9 42 638 +1978 5 1 18 11 NADINE 47.7 239.5 18 36 +1987 1 19 6 14 BERYL 26.0 253.9 126 569 +1965 2 2 12 5 GORDON 24.7 266.4 73 268 +1951 8 22 12 27 GORDON 15.2 333.1 19 15 +1984 7 2 6 5 NADINE 22.7 81.7 80 133 +1972 1 2 0 2 DEBBY 29.1 134.8 64 883 +1955 11 16 0 15 CHRIS 57.1 140.0 12 74 +1990 6 28 6 1 PATTY 47.3 192.8 99 523 +1962 5 21 12 19 OSCAR 23.0 256.6 130 124 +1986 2 22 12 7 LESLIE 28.4 257.7 44 425 +1980 12 9 18 4 MICHAEL 42.7 355.1 153 797 +1982 1 15 6 25 FLORENCE 40.6 144.9 112 854 +1950 3 10 0 23 ISAAC 15.0 64.9 162 847 +1962 6 9 18 13 WILLIAM 11.7 233.9 58 175 +1976 7 12 12 10 ALBERTO 54.4 108.1 111 326 +1964 2 6 18 12 MICHAEL 41.3 332.9 150 806 +1995 12 15 12 27 LESLIE 39.0 98.5 29 169 +1964 8 2 12 10 DEBBY 21.8 358.0 116 102 +1974 3 22 0 22 VALERIE 40.1 324.7 20 606 +1990 8 7 0 17 ALBERTO 59.4 319.0 121 261 +1996 2 15 18 4 GORDON 30.7 9.5 37 584 +1955 6 17 18 3 BERYL 52.8 308.2 99 296 +1957 4 28 0 11 FLORENCE 32.0 43.5 108 669 +1976 5 20 0 20 NADINE 46.1 31.4 74 285 +1975 4 12 18 16 BERYL 64.2 65.5 94 207 +1992 1 7 0 5 SANDY 19.1 185.9 79 748 +1959 3 23 0 4 SANDY 41.2 89.0 83 187 +1978 5 27 0 8 LESLIE 24.1 105.4 120 605 +1967 3 19 0 19 JOYCE 29.3 318.9 135 894 +1985 3 21 18 25 ISAAC 51.7 91.3 80 292 +1968 7 7 12 5 TONY 36.7 286.6 126 276 +1998 12 9 6 7 TONY 34.8 110.0 60 379 +1955 3 11 6 3 VALERIE 54.0 156.9 65 892 +1979 2 5 6 17 WILLIAM 13.1 152.0 31 413 +1982 3 11 18 18 SANDY 24.9 130.6 140 362 +1975 2 26 12 2 BERYL 13.3 224.9 131 536 +1994 9 11 6 15 VALERIE 66.9 88.9 163 774 +1998 12 20 12 5 DEBBY 24.6 259.9 108 260 +1994 1 6 0 8 PATTY 57.6 251.4 44 421 +1992 11 24 6 27 ALBERTO 9.2 146.6 148 412 +1952 5 4 0 10 JOYCE 39.3 232.0 11 241 +2001 6 28 0 25 KIRK 66.0 188.1 97 847 +1973 1 25 6 24 DEBBY 53.6 333.2 43 885 +1994 6 23 0 8 DEBBY 28.4 235.2 29 629 +1998 11 23 18 8 TONY 40.9 342.9 107 727 +2001 9 4 6 10 GORDON 56.1 5.2 48 8 +1959 2 2 12 18 JOYCE 43.8 165.2 50 638 +1955 9 12 6 19 LESLIE 19.5 289.4 95 730 +1988 12 3 18 4 SANDY 19.5 257.8 153 564 +1953 2 25 12 16 PATTY 44.5 85.2 79 617 +1971 10 6 6 13 JOYCE 58.8 89.9 146 481 +2002 7 18 0 20 JOYCE 22.2 156.2 115 499 +1972 9 20 12 16 LESLIE 52.0 227.3 85 681 +1953 2 21 6 21 JOYCE 16.0 192.8 51 851 +1992 3 9 18 4 DEBBY 35.2 72.7 132 359 +1970 2 8 0 20 RAFAEL 9.0 4.3 99 298 +1972 12 8 18 19 BERYL 23.7 247.4 132 559 +1967 3 15 18 17 LESLIE 65.8 307.8 136 852 +1954 5 24 6 23 FLORENCE 18.1 100.5 42 101 +1951 8 27 0 15 MICHAEL 65.4 336.1 104 129 +1999 12 21 6 2 MICHAEL 53.1 315.6 16 761 +1975 10 28 12 18 CHRIS 14.2 263.0 35 26 +1955 5 24 0 26 ALBERTO 56.4 155.5 91 804 +1985 10 13 18 26 ISAAC 57.4 337.1 148 288 +1997 8 18 18 2 WILLIAM 11.1 303.8 30 641 +2001 10 12 0 3 BERYL 58.2 21.9 140 153 +1985 12 3 0 8 NADINE 68.5 140.3 34 123 +2004 9 20 0 10 ALBERTO 13.9 255.2 156 840 +2002 11 7 12 3 FLORENCE 24.5 319.1 64 178 +1993 1 2 12 15 SANDY 40.1 108.1 109 361 +1975 2 20 12 27 RAFAEL 63.1 151.5 13 141 +1995 4 9 6 18 PATTY 52.1 327.4 43 791 +2003 6 20 6 15 FLORENCE 11.5 298.8 112 306 +1962 5 4 6 10 RAFAEL 45.8 194.2 53 75 +1962 4 21 0 21 GORDON 49.2 52.5 50 300 +1994 5 21 12 26 VALERIE 15.0 308.9 95 340 +1950 11 20 6 22 OSCAR 37.4 84.6 106 551 +1994 4 5 18 19 FLORENCE 36.0 131.5 97 657 +1993 3 17 0 15 TONY 67.2 231.5 137 260 +1968 3 9 0 11 KIRK 60.6 90.6 157 98 +1987 11 10 12 26 FLORENCE 66.3 109.8 83 583 +1983 12 13 0 27 VALERIE 30.2 74.4 21 14 +1991 5 19 12 5 BERYL 32.1 332.2 109 648 +1979 10 8 6 2 NADINE 60.3 253.7 137 639 +1953 8 20 12 14 LESLIE 16.0 157.9 140 291 +1979 10 15 12 23 ISAAC 54.5 173.2 117 458 +1951 10 5 0 2 GORDON 25.8 318.1 107 703 +1964 8 23 6 3 WILLIAM 58.5 320.5 142 526 +1951 11 2 0 20 DEBBY 52.6 309.5 131 304 +1984 2 21 12 24 KIRK 28.6 210.7 70 349 +1994 7 4 12 6 HELENE 44.4 249.9 36 216 +1997 3 23 18 13 GORDON 16.9 267.7 21 244 +1953 9 17 12 5 LESLIE 13.3 8.0 44 789 +1967 11 6 12 9 RAFAEL 57.4 191.2 141 707 +2004 9 8 6 14 ERNESTO 38.7 27.6 161 335 +1954 6 14 18 24 NADINE 50.6 191.0 153 661 +1964 1 23 6 5 SANDY 16.5 9.1 45 664 +1988 7 21 6 21 SANDY 56.4 222.6 92 252 +2003 12 17 6 14 NADINE 26.8 157.9 164 412 +1962 10 5 6 26 WILLIAM 29.3 224.5 17 588 +1982 7 13 6 25 MICHAEL 31.9 346.7 45 351 +2003 8 24 0 28 SANDY 35.3 347.4 67 863 +1950 6 4 18 8 OSCAR 14.1 324.3 96 454 +1971 8 8 6 22 LESLIE 18.1 202.4 33 515 +1999 4 26 6 5 NADINE 55.2 38.5 67 473 +2003 7 18 12 7 HELENE 29.0 183.7 86 854 +2000 5 5 0 25 OSCAR 26.1 50.7 29 798 +1996 7 10 0 18 VALERIE 21.3 300.5 145 432 +1966 6 15 12 14 TONY 12.2 227.2 139 285 +2003 11 6 12 24 SANDY 48.6 184.8 154 862 +1969 1 28 18 3 ALBERTO 22.2 52.9 32 41 +1952 8 8 18 17 RAFAEL 22.5 17.2 136 162 +1958 9 1 0 14 SANDY 25.3 83.5 143 205 +1973 10 22 12 27 WILLIAM 49.2 6.4 128 810 +1994 10 20 12 27 GORDON 61.6 127.9 96 376 +1993 10 16 18 12 KIRK 29.3 13.6 121 884 +1954 3 14 18 18 KIRK 48.6 8.5 146 449 +1986 9 4 18 6 GORDON 30.2 316.4 110 719 +1995 11 5 0 5 TONY 32.6 4.1 67 215 +1971 3 12 6 8 ISAAC 63.5 340.2 46 656 +1965 2 23 0 25 MICHAEL 25.9 314.5 58 766 +1968 9 1 12 18 CHRIS 66.7 248.3 66 117 +1963 9 5 6 11 FLORENCE 37.3 4.8 139 836 +1983 8 8 6 5 TONY 18.1 156.7 61 292 +1998 4 13 12 8 GORDON 21.3 125.8 34 717 +1998 6 25 18 6 NADINE 63.7 1.9 87 259 +1969 1 28 18 5 ALBERTO 34.8 198.5 84 0 +1987 11 23 6 8 RAFAEL 29.5 104.2 155 885 +1989 5 2 12 11 ALBERTO 27.7 34.1 65 362 +1999 1 27 18 1 FLORENCE 61.7 305.3 11 190 +1995 6 9 0 1 NADINE 41.9 231.8 151 811 +1964 1 3 18 18 VALERIE 20.4 298.9 154 144 +1967 8 23 0 26 CHRIS 7.2 106.0 27 899 +1962 1 15 12 27 PATTY 56.3 72.0 108 574 +1984 8 23 18 8 CHRIS 49.8 171.0 14 463 +1979 1 22 6 4 PATTY 37.8 204.6 69 706 +1999 6 26 18 22 HELENE 27.4 139.1 84 550 +1998 12 16 0 18 FLORENCE 27.4 20.3 96 159 +1984 5 21 6 28 NADINE 31.7 304.7 62 857 +1960 8 10 0 28 HELENE 68.6 193.7 139 582 +1984 7 10 6 4 TONY 39.0 220.0 38 501 +1955 3 20 0 17 BERYL 17.3 340.4 113 307 +1956 4 13 6 26 FLORENCE 55.1 10.1 163 380 +1969 6 26 6 23 RAFAEL 8.6 92.4 120 2 +2003 4 20 18 14 PATTY 50.9 219.6 104 516 +1986 10 20 6 7 ISAAC 39.9 118.9 100 850 +1955 5 21 0 3 ERNESTO 55.1 183.8 70 474 +1984 3 5 0 13 ERNESTO 61.0 110.0 82 834 +1951 9 11 18 24 WILLIAM 33.3 268.8 153 718 +1992 12 8 0 25 FLORENCE 39.2 197.1 88 81 +2003 7 28 6 3 GORDON 49.7 243.0 32 213 +1998 6 23 6 7 DEBBY 30.1 202.0 74 738 +1973 1 8 12 3 TONY 42.0 173.4 118 754 +1981 8 28 18 22 ERNESTO 39.5 291.7 50 884 +1955 4 22 6 23 NADINE 9.4 137.8 51 609 +2000 3 22 0 26 SANDY 56.4 29.7 55 722 +1982 11 25 18 23 ISAAC 40.5 224.1 13 266 +1989 11 22 12 3 RAFAEL 33.8 5.5 38 798 +1974 9 17 18 7 PATTY 44.6 356.6 137 382 +2004 2 16 12 23 NADINE 11.1 276.8 87 342 +1986 9 18 18 18 JOYCE 24.6 116.2 148 246 +1995 5 14 0 15 WILLIAM 30.9 61.4 10 271 +1956 5 26 6 7 BERYL 56.9 247.2 66 594 +1997 1 22 0 3 DEBBY 61.5 33.9 64 603 +1958 6 17 6 21 NADINE 61.6 78.3 152 582 +1994 2 18 18 14 SANDY 26.1 286.0 52 850 +1977 4 5 0 28 ISAAC 67.4 109.0 52 752 +1954 1 1 0 22 FLORENCE 53.9 187.9 18 704 +1988 10 3 0 21 ALBERTO 14.5 231.3 55 406 +1977 1 9 0 5 DEBBY 50.8 190.9 76 45 +1955 1 2 12 5 KIRK 39.7 32.1 10 230 +1971 7 26 18 9 HELENE 29.3 171.4 30 134 +1973 2 8 6 3 ERNESTO 8.6 6.6 53 876 +1994 11 9 18 7 RAFAEL 13.1 5.0 124 742 +1970 3 20 12 1 WILLIAM 35.6 245.7 159 20 +2000 3 10 0 27 MICHAEL 9.9 157.3 65 161 +1979 6 17 0 21 RAFAEL 55.2 352.0 129 248 +1951 3 18 18 18 LESLIE 29.4 20.3 121 345 +2004 6 18 0 3 ALBERTO 32.9 263.4 16 317 +1998 3 23 18 5 LESLIE 55.2 351.3 143 712 +1990 4 14 0 13 WILLIAM 16.1 336.2 122 114 +1962 1 15 0 23 CHRIS 47.8 341.8 11 393 +1961 9 3 18 6 MICHAEL 19.8 194.6 144 94 +1987 5 1 18 23 HELENE 62.3 300.7 31 160 +1968 7 14 0 10 RAFAEL 57.1 113.9 12 608 +1952 5 4 6 22 GORDON 50.3 40.3 75 456 +1997 3 14 18 15 VALERIE 16.5 107.0 102 333 +1986 3 23 12 11 JOYCE 24.5 43.2 123 596 +1958 6 1 18 1 ERNESTO 8.7 289.0 124 633 +1976 6 19 12 27 HELENE 56.1 210.9 156 760 +1983 12 6 18 10 LESLIE 26.7 177.5 75 672 +1980 3 15 18 28 JOYCE 11.8 272.2 82 350 +1972 11 5 6 25 ERNESTO 8.9 13.9 57 128 +1961 12 8 0 4 ALBERTO 15.0 195.6 29 126 +1976 12 8 12 14 TONY 14.1 51.3 132 341 +2001 3 7 0 26 FLORENCE 43.8 80.0 154 757 +1972 12 22 18 2 DEBBY 40.0 5.4 128 488 +1994 12 21 6 21 ERNESTO 31.1 304.2 58 405 +1961 10 4 0 18 MICHAEL 44.6 26.8 98 802 +1996 7 18 6 28 HELENE 45.9 4.7 99 66 +1996 9 24 0 14 LESLIE 16.7 286.1 98 367 +1965 7 5 12 25 DEBBY 54.2 302.7 106 379 +1953 7 28 18 22 CHRIS 61.9 78.0 128 177 +1962 7 26 0 3 LESLIE 27.7 189.8 25 260 +1983 2 20 6 16 VALERIE 25.4 66.8 29 851 +1956 10 21 18 12 VALERIE 39.6 315.9 76 841 +1959 9 25 12 24 HELENE 23.8 245.6 103 650 +1994 11 19 18 14 MICHAEL 56.9 69.3 147 34 +1961 2 8 12 3 OSCAR 48.3 60.8 83 424 +1988 3 13 6 21 ISAAC 42.3 338.2 146 665 +1957 3 23 18 5 HELENE 12.3 318.9 117 30 +1991 1 5 12 4 RAFAEL 34.7 62.3 114 382 +1982 10 24 6 4 HELENE 45.2 87.9 72 385 +1955 6 17 0 19 BERYL 23.0 127.5 121 141 +2002 10 23 6 5 BERYL 35.7 211.8 104 217 +1972 10 25 0 19 ISAAC 36.6 242.8 23 567 +2004 9 24 6 4 GORDON 19.1 344.9 40 516 +1998 7 27 6 26 CHRIS 50.5 37.1 82 139 +1963 6 2 18 4 WILLIAM 66.8 292.2 13 803 +1950 6 21 0 22 JOYCE 60.6 195.7 102 186 +1986 6 14 0 9 WILLIAM 8.1 90.2 151 713 +1966 9 20 6 18 LESLIE 63.9 268.2 52 862 +1952 11 20 0 25 JOYCE 17.9 246.7 149 568 +1961 5 12 18 2 GORDON 69.3 121.0 27 527 +1966 12 13 18 17 TONY 68.2 78.2 47 180 +1954 3 21 18 3 NADINE 49.4 328.9 151 361 +1974 3 9 12 15 OSCAR 39.5 179.6 66 143 +1955 9 19 18 22 CHRIS 44.8 239.3 71 687 +1951 11 8 0 6 VALERIE 18.6 270.1 72 202 +2003 6 27 0 11 ERNESTO 10.6 116.4 109 799 +1979 2 24 6 10 ERNESTO 9.4 324.0 38 274 +1961 12 5 6 17 ISAAC 24.8 11.4 101 792 +1958 5 27 12 19 GORDON 27.0 11.2 97 402 +1962 8 17 0 12 ISAAC 47.2 172.7 124 341 +1959 5 11 6 6 TONY 66.1 14.3 65 678 +1953 9 17 0 22 VALERIE 17.5 173.5 69 694 +1955 5 15 0 5 DEBBY 58.0 343.1 126 824 +2003 12 18 0 19 GORDON 27.9 205.0 61 458 +1992 5 20 12 7 CHRIS 65.2 189.1 79 701 +1979 5 2 0 25 KIRK 29.7 286.3 129 296 +1972 5 15 18 8 PATTY 12.9 259.3 57 54 +1975 5 5 0 23 DEBBY 37.8 270.8 17 576 +1954 1 22 0 11 TONY 23.9 236.7 147 37 +2000 11 17 6 12 DEBBY 29.8 45.9 62 95 +1970 8 20 18 23 FLORENCE 39.6 128.5 132 860 +1974 6 18 6 12 KIRK 65.9 273.8 82 722 +2002 11 17 0 15 PATTY 23.1 250.6 105 168 +1956 10 6 18 7 TONY 35.7 84.3 122 66 +1995 2 16 6 20 KIRK 37.1 301.9 137 599 +1963 3 26 0 25 KIRK 25.1 252.1 64 411 +1954 6 21 12 27 OSCAR 69.7 78.2 39 43 +1960 5 19 18 5 LESLIE 61.1 318.9 48 67 +1996 5 1 18 15 GORDON 18.0 132.4 10 240 +2002 5 5 12 24 SANDY 33.0 68.3 75 898 +1974 4 22 12 24 LESLIE 21.1 153.7 23 612 +1951 1 7 12 12 LESLIE 69.1 148.8 127 53 +1953 9 28 12 9 WILLIAM 28.5 118.7 131 777 +1965 1 24 6 15 OSCAR 55.9 339.6 47 316 +1963 3 2 18 6 DEBBY 37.6 256.0 45 452 +1984 10 5 6 4 MICHAEL 36.1 349.9 104 249 +1994 6 27 0 5 JOYCE 31.3 200.7 34 417 +1951 1 19 12 1 HELENE 65.2 83.1 65 235 +2000 8 19 6 3 ERNESTO 35.6 69.5 20 295 +1951 11 17 12 25 OSCAR 62.6 238.4 57 768 +2000 7 8 0 22 HELENE 67.2 251.8 53 773 +1994 11 12 12 3 GORDON 65.7 235.2 122 719 +1978 4 22 6 26 GORDON 9.8 128.5 133 843 +1986 9 15 6 10 WILLIAM 25.9 218.2 130 563 +2002 12 1 12 13 TONY 34.2 198.5 163 415 +1982 2 18 6 3 ERNESTO 54.4 159.6 147 844 +1986 12 6 12 22 BERYL 52.8 259.8 127 579 +1971 4 10 18 18 LESLIE 53.1 193.6 21 247 +1958 12 8 6 15 FLORENCE 45.6 194.9 13 153 +1985 9 17 6 7 HELENE 42.5 171.4 56 290 +1991 6 16 18 18 HELENE 28.9 186.2 11 554 +1951 4 28 12 27 MICHAEL 23.9 214.5 84 780 +2001 4 24 18 22 GORDON 65.9 75.9 145 265 +1951 10 2 6 4 ERNESTO 25.2 48.1 31 180 +1976 12 26 18 12 FLORENCE 46.5 151.9 62 205 +1973 11 5 6 19 WILLIAM 55.0 186.2 41 811 +1976 10 17 18 13 NADINE 37.3 16.9 75 331 +1961 10 22 6 9 ALBERTO 45.2 67.1 131 298 +1973 10 11 6 17 PATTY 31.6 83.3 164 561 +1974 10 4 6 15 SANDY 52.2 97.0 147 501 +1973 12 24 18 18 JOYCE 35.7 277.4 160 859 +1972 6 22 18 7 KIRK 63.6 197.8 31 293 +1991 11 10 6 9 CHRIS 29.2 5.9 78 355 +1998 12 7 0 15 ERNESTO 24.0 49.4 29 889 +1977 10 26 6 14 PATTY 57.3 32.6 64 740 +2000 10 8 0 24 JOYCE 30.4 329.4 38 832 +1978 12 2 18 8 WILLIAM 63.1 301.9 127 584 +2000 7 23 0 8 LESLIE 16.9 15.5 74 404 +1990 7 5 18 24 GORDON 49.6 304.1 152 698 +1960 5 17 0 11 ISAAC 27.4 88.3 42 1 +1952 11 12 6 26 WILLIAM 9.7 259.8 127 191 +1989 2 3 18 10 KIRK 9.2 335.6 106 359 +1994 5 6 18 12 LESLIE 48.2 157.8 17 223 +1987 2 3 0 3 VALERIE 46.0 43.5 66 370 +1978 9 5 0 11 LESLIE 19.5 335.7 70 842 +1980 7 18 12 22 DEBBY 23.7 81.0 147 8 +1996 5 28 0 7 RAFAEL 43.7 143.1 126 773 +1973 10 17 12 16 GORDON 34.3 6.8 119 721 +1985 1 11 18 28 WILLIAM 24.9 196.5 42 138 +1963 7 24 0 2 JOYCE 53.6 244.0 15 337 +1950 11 18 18 12 VALERIE 60.5 194.3 51 747 +1968 1 7 18 16 RAFAEL 60.2 146.9 34 185 +1963 8 25 6 13 KIRK 7.1 98.9 136 555 +1980 9 26 0 4 SANDY 52.7 260.2 16 778 +1999 4 16 0 6 LESLIE 64.4 173.9 41 184 +2003 8 5 18 20 KIRK 61.6 171.2 38 322 +1989 7 13 0 1 ERNESTO 39.1 205.4 136 578 +1979 10 7 6 4 ISAAC 57.5 227.4 135 840 +1979 2 4 0 18 BERYL 56.7 97.5 111 149 +2001 3 11 18 24 ALBERTO 41.0 226.6 59 151 +1975 1 18 18 7 DEBBY 20.2 20.6 48 757 +1969 3 21 18 7 SANDY 52.0 164.3 92 277 +1977 5 12 6 28 KIRK 61.4 128.0 127 284 +1983 6 16 6 5 NADINE 23.0 291.6 25 99 +1973 3 16 6 5 ERNESTO 51.7 229.5 56 357 +1954 3 3 12 1 VALERIE 25.3 76.8 15 845 +1956 6 20 18 26 WILLIAM 35.1 209.4 21 619 +1986 2 26 0 4 NADINE 45.9 208.1 31 278 +1976 9 28 0 20 FLORENCE 56.3 241.4 120 544 +1980 11 1 0 20 ISAAC 54.1 231.2 119 350 +1998 9 26 12 21 HELENE 45.0 321.1 71 346 +1983 6 16 0 22 PATTY 20.2 266.2 12 144 +1990 4 15 12 9 LESLIE 34.3 228.7 125 610 +1956 1 15 6 4 ERNESTO 66.4 61.5 28 77 +1996 1 25 6 2 NADINE 16.9 139.1 114 635 +1961 12 21 18 23 ISAAC 41.5 70.5 49 327 +1979 1 21 12 3 KIRK 53.0 235.2 124 254 +2001 11 15 12 23 HELENE 25.0 210.1 59 866 +1972 6 14 12 27 PATTY 67.3 34.9 164 456 +1958 8 21 18 15 LESLIE 52.6 135.3 154 90 +1981 10 3 18 4 BERYL 45.8 165.4 22 505 +2003 1 11 18 11 ERNESTO 35.8 234.5 109 323 +1971 1 13 0 24 LESLIE 25.2 227.3 39 748 +1989 12 6 0 27 LESLIE 15.6 226.7 142 106 +1959 3 15 6 22 SANDY 15.1 9.3 40 108 +1999 5 16 12 21 CHRIS 28.0 208.8 33 535 +1953 8 7 18 4 TONY 41.0 43.8 113 612 +1962 3 23 18 4 BERYL 29.5 86.2 110 352 +1991 9 11 0 12 TONY 37.1 255.0 135 798 +1972 8 23 12 17 FLORENCE 31.9 220.4 16 645 +2001 10 22 12 13 MICHAEL 13.4 279.4 40 346 +1968 1 1 0 27 SANDY 38.4 161.3 13 189 +1995 7 8 18 8 ERNESTO 53.4 314.2 116 202 +1978 2 4 18 18 BERYL 55.6 20.8 18 179 +1960 9 9 18 18 CHRIS 40.3 326.9 99 141 +1963 6 2 12 23 DEBBY 22.2 25.2 99 258 +1990 7 21 0 12 MICHAEL 63.0 239.3 156 160 +1979 3 4 6 26 VALERIE 23.1 348.8 44 264 +1966 9 12 6 8 SANDY 12.4 161.2 138 150 +1962 7 1 6 22 ISAAC 29.1 44.4 34 537 +1981 6 28 18 2 LESLIE 45.5 76.7 81 446 +1981 2 18 12 6 JOYCE 9.2 208.9 47 135 +1994 12 25 18 13 ERNESTO 51.7 324.6 81 209 +1978 10 23 6 9 KIRK 19.1 325.3 106 791 +1989 12 8 12 2 VALERIE 10.3 68.3 144 776 +1988 10 15 6 6 SANDY 42.0 277.1 151 834 +1971 8 27 6 20 DEBBY 43.9 110.7 124 25 +1969 4 6 0 14 HELENE 32.9 256.2 102 807 +1958 6 8 0 14 SANDY 56.6 84.0 120 54 +1971 12 7 6 19 KIRK 52.4 150.3 111 51 +1994 8 18 18 15 DEBBY 29.0 33.5 146 334 +1998 1 28 0 5 FLORENCE 61.9 123.8 93 347 +1960 1 7 18 25 ALBERTO 34.0 199.6 114 161 +1951 8 23 12 2 ALBERTO 42.5 256.2 121 160 +1962 11 3 18 4 JOYCE 37.4 237.4 113 877 +1958 2 7 0 10 MICHAEL 49.9 300.7 20 571 +1957 5 3 0 5 KIRK 14.6 310.5 138 752 +1973 9 9 0 5 ALBERTO 69.3 88.9 116 470 +1968 1 17 0 9 ISAAC 48.5 92.2 66 401 +1966 11 28 0 14 HELENE 61.2 149.9 106 385 +1993 12 4 0 7 DEBBY 53.1 209.7 148 281 +1973 9 11 12 15 DEBBY 32.8 92.7 94 752 +1960 8 22 6 16 BERYL 13.7 247.7 101 396 +2003 10 9 18 16 ALBERTO 11.3 151.6 144 315 +2004 4 2 12 11 WILLIAM 26.3 70.6 66 370 +1988 10 6 18 24 DEBBY 35.4 231.5 44 488 +2000 11 14 6 22 TONY 61.8 283.6 22 93 +1991 2 8 18 21 RAFAEL 48.6 138.0 161 323 +1999 8 1 18 12 MICHAEL 45.9 211.1 97 229 +1982 10 7 0 20 LESLIE 43.2 294.7 60 150 +1975 6 20 0 24 FLORENCE 11.6 239.8 68 338 +1976 2 3 0 22 TONY 51.0 308.4 15 299 +1975 10 24 12 15 BERYL 41.4 306.4 66 895 +1957 2 6 18 10 TONY 39.5 304.1 111 729 +1953 5 21 18 4 ERNESTO 9.0 161.0 140 594 +1969 8 10 6 12 RAFAEL 11.2 11.5 64 250 +1989 1 9 6 25 ERNESTO 44.5 206.4 132 758 +1999 7 23 12 9 VALERIE 61.8 9.2 82 602 +1965 9 10 12 20 FLORENCE 55.6 70.6 18 49 +1995 6 21 6 21 KIRK 52.9 187.9 121 874 +1997 9 25 6 23 SANDY 16.4 222.9 22 767 +1991 2 12 6 2 LESLIE 7.1 238.0 14 626 +1970 8 25 0 13 ALBERTO 63.8 7.1 151 423 +1977 3 15 6 8 WILLIAM 52.1 60.4 112 377 +1992 1 1 0 28 GORDON 51.1 284.3 129 225 +1963 9 4 0 27 SANDY 45.6 282.3 34 844 +1978 2 13 0 22 NADINE 29.3 109.2 95 850 +1967 10 21 18 13 SANDY 52.9 30.7 124 344 +1996 5 17 12 10 JOYCE 19.4 79.0 40 284 +1994 1 12 0 11 KIRK 42.6 111.8 55 296 +1983 6 1 0 17 CHRIS 55.8 76.2 78 614 +1976 7 13 0 9 PATTY 26.1 123.0 164 548 +1984 9 22 0 12 ALBERTO 41.1 147.7 136 559 +1971 10 14 6 18 GORDON 31.6 17.3 54 776 +1964 4 26 0 3 MICHAEL 69.9 186.0 94 762 +1999 9 3 18 1 HELENE 60.6 198.6 78 197 +1986 3 21 6 27 DEBBY 35.5 104.7 149 308 +1974 6 28 6 21 PATTY 53.7 331.0 104 67 +1985 4 18 0 20 ISAAC 17.4 264.6 163 640 +1969 1 21 0 12 CHRIS 16.0 42.7 23 138 +1979 2 24 12 4 LESLIE 29.0 92.8 150 441 +1967 11 12 6 9 KIRK 40.7 140.2 52 794 +1955 5 16 12 13 DEBBY 62.0 325.7 108 118 +1961 9 23 0 8 TONY 48.3 324.3 44 476 +1971 7 16 6 25 FLORENCE 23.9 176.1 66 178 +1991 11 7 0 19 BERYL 47.3 303.9 120 101 +1952 4 16 18 13 LESLIE 36.6 201.2 142 662 +1982 9 23 12 8 NADINE 62.2 84.7 109 840 +1985 8 26 12 1 JOYCE 48.5 35.4 44 541 +1954 7 1 18 13 RAFAEL 8.7 98.6 122 71 +1978 9 16 12 21 HELENE 35.7 43.3 114 220 +1959 10 16 12 1 HELENE 62.3 34.3 19 456 +1957 12 2 0 15 OSCAR 25.1 225.9 85 233 +2003 7 7 18 23 DEBBY 12.4 228.4 100 782 +1973 2 17 0 6 CHRIS 7.2 215.0 59 827 +1975 10 26 6 22 TONY 32.7 117.3 114 765 +1994 11 6 18 26 WILLIAM 30.0 272.2 127 545 +1964 8 15 18 14 OSCAR 43.4 345.2 126 694 +1992 9 20 18 18 TONY 32.2 183.5 158 66 +1995 7 16 6 16 PATTY 50.1 44.1 142 226 +1970 3 16 18 26 DEBBY 51.1 153.9 11 86 +1965 11 21 0 1 GORDON 10.8 85.1 58 726 +1956 6 9 18 16 NADINE 33.5 89.2 110 284 +1986 10 23 18 10 NADINE 69.6 277.6 85 405 +1967 3 11 18 9 FLORENCE 35.7 338.0 148 13 +1964 5 14 6 13 PATTY 41.5 324.6 34 711 +1992 3 13 18 21 OSCAR 63.7 345.0 51 135 +2003 9 7 6 19 BERYL 11.4 312.4 137 537 +1999 7 16 12 15 WILLIAM 14.8 96.1 12 407 +1957 5 20 6 24 ALBERTO 45.9 86.4 72 172 +1996 6 13 18 13 CHRIS 15.2 76.3 148 350 +1968 2 3 12 4 ERNESTO 15.6 311.2 55 30 +1957 1 1 0 19 MICHAEL 32.3 132.4 53 420 +2003 6 22 18 10 SANDY 51.7 129.0 120 530 +2000 4 13 6 28 SANDY 10.0 259.9 11 406 +1958 4 8 12 1 JOYCE 59.9 112.1 35 643 +1979 4 4 18 12 KIRK 9.8 351.1 25 445 +1964 10 19 0 5 MICHAEL 41.6 71.7 107 820 +1965 11 4 0 7 DEBBY 13.5 19.1 34 152 +1954 9 2 12 23 PATTY 17.6 36.9 138 332 +1966 3 27 12 17 GORDON 48.2 185.4 77 75 +1988 11 24 6 6 RAFAEL 33.7 204.8 150 300 +1984 9 24 18 27 HELENE 69.6 31.8 104 157 +1964 6 28 6 3 TONY 66.0 251.5 81 166 +1991 5 2 0 28 CHRIS 43.3 70.2 22 305 +1980 5 3 0 19 OSCAR 33.1 300.4 27 660 +1956 6 23 0 10 JOYCE 8.8 50.7 63 541 +1975 10 4 0 14 HELENE 35.7 53.1 18 7 +1977 4 15 12 17 NADINE 28.0 80.8 161 486 +1995 12 10 6 24 GORDON 10.4 302.6 145 784 +1969 8 14 18 3 ERNESTO 61.6 319.2 66 293 +1964 1 14 6 15 TONY 17.3 290.1 120 255 +1972 9 9 0 15 ALBERTO 31.2 34.3 101 567 +1990 4 7 6 18 WILLIAM 64.8 186.6 56 322 +1969 10 8 6 23 ERNESTO 42.5 235.2 60 352 +1970 2 26 12 15 SANDY 51.0 213.9 164 794 +1966 12 20 12 24 ALBERTO 61.4 267.8 37 397 +1998 10 18 12 6 RAFAEL 40.3 127.3 150 805 +2001 6 5 6 21 FLORENCE 18.3 229.4 109 202 +1987 11 3 0 14 SANDY 33.6 90.3 28 41 +1985 7 20 0 6 NADINE 21.5 121.4 10 222 +1984 3 6 6 22 ALBERTO 14.6 308.6 54 250 +1956 10 21 0 25 LESLIE 25.2 62.4 116 603 +1969 1 17 12 3 ERNESTO 62.7 355.0 44 19 +1961 9 3 0 26 PATTY 23.0 340.3 10 826 +1979 3 1 0 28 WILLIAM 55.6 47.1 80 238 +1953 6 19 6 3 OSCAR 59.1 158.5 152 510 +1999 9 20 6 3 VALERIE 37.3 257.6 36 702 +1955 8 19 18 11 DEBBY 30.6 151.0 96 759 +1988 4 10 0 2 MICHAEL 54.0 321.4 161 429 +1973 7 14 12 24 ERNESTO 51.5 294.0 40 639 +1950 3 25 18 23 KIRK 37.1 182.2 147 859 +1999 12 21 18 14 WILLIAM 22.1 113.8 57 44 +1983 11 8 0 1 PATTY 8.2 343.6 85 837 +1991 9 15 0 25 CHRIS 10.8 33.2 53 784 +1975 12 17 6 22 CHRIS 14.3 9.3 136 288 +2000 12 27 0 20 MICHAEL 35.4 12.2 157 220 +1996 11 16 18 3 BERYL 36.5 195.8 78 338 +1973 1 11 0 2 DEBBY 46.0 180.6 117 781 +1998 12 20 18 3 ERNESTO 55.7 61.2 38 465 +1989 1 16 6 1 ISAAC 20.8 335.8 55 424 +1991 11 19 18 2 ISAAC 7.6 167.1 76 841 +1971 3 12 0 21 PATTY 31.1 115.6 162 169 +1984 7 3 12 9 CHRIS 9.9 65.5 118 506 +2002 2 23 18 14 ISAAC 35.3 109.5 162 568 +1984 5 26 12 2 JOYCE 44.5 277.8 57 61 +2003 6 19 12 27 WILLIAM 62.9 222.3 119 798 +1960 8 5 0 24 ERNESTO 27.3 195.4 91 744 +1951 2 5 12 23 CHRIS 46.0 233.2 61 715 +1990 6 10 6 17 CHRIS 21.4 232.2 66 802 +1961 6 15 12 15 JOYCE 8.9 288.1 142 877 +1965 5 17 18 7 JOYCE 27.7 214.8 106 875 +1992 5 1 6 5 JOYCE 66.9 144.1 97 124 +1957 12 3 6 26 GORDON 36.8 165.9 74 641 +1969 1 1 12 13 HELENE 67.5 116.1 129 740 +1988 5 20 0 19 HELENE 23.2 215.8 33 277 +1969 2 1 0 8 RAFAEL 59.7 9.8 50 395 +1980 7 11 12 16 JOYCE 7.5 187.9 73 685 +2003 10 27 12 4 HELENE 58.6 223.2 94 357 +1995 12 1 12 9 CHRIS 10.3 165.3 126 458 +1970 5 16 12 23 FLORENCE 21.7 3.7 115 816 +1961 12 18 18 4 ALBERTO 39.7 278.0 93 394 +1977 8 18 0 24 ISAAC 64.4 274.5 38 808 +1966 10 19 12 23 LESLIE 8.6 245.8 87 433 +1968 9 20 6 2 HELENE 28.8 77.7 162 803 +1973 2 19 6 8 DEBBY 48.7 100.4 34 3 +1976 3 12 18 15 FLORENCE 67.1 234.1 51 721 +1955 4 16 18 17 GORDON 34.1 196.5 12 71 +1985 3 20 0 26 CHRIS 47.5 340.2 60 683 +1964 7 18 12 14 LESLIE 48.3 76.5 12 344 +2001 12 21 6 1 CHRIS 49.0 284.8 76 620 +1987 1 8 18 4 LESLIE 39.9 179.4 147 844 +1960 12 7 18 27 MICHAEL 59.9 162.5 150 634 +1969 3 3 18 15 WILLIAM 47.2 299.6 43 562 +1956 10 12 12 1 WILLIAM 15.8 99.1 86 201 +1994 4 14 12 20 LESLIE 34.1 67.8 118 187 +1965 7 8 6 5 GORDON 11.4 20.3 79 413 +1955 8 18 6 25 HELENE 21.6 194.2 157 207 +1990 11 4 0 26 WILLIAM 63.6 166.8 93 692 +1989 4 28 12 26 RAFAEL 7.6 298.3 162 792 +1959 12 8 0 20 MICHAEL 31.1 187.5 81 408 +1997 10 20 12 28 GORDON 45.9 184.5 39 783 +1988 3 28 18 27 DEBBY 20.9 188.4 20 817 +1976 4 12 12 7 FLORENCE 42.8 194.5 69 170 +2004 7 28 12 13 SANDY 14.3 220.1 143 470 +1963 6 25 18 21 TONY 56.1 188.3 100 57 +2004 1 18 0 27 SANDY 50.4 60.4 40 103 +1975 12 19 18 25 CHRIS 61.5 250.6 108 66 +1984 9 27 18 9 NADINE 47.6 152.6 104 322 +1961 12 26 6 21 DEBBY 48.3 231.2 78 109 +1985 4 26 12 22 JOYCE 19.9 137.2 146 477 +1999 7 7 18 5 JOYCE 36.6 85.3 44 588 +1969 12 16 6 7 CHRIS 67.6 29.1 148 806 +1958 5 1 12 15 ERNESTO 42.0 146.0 49 304 +1958 2 23 6 25 KIRK 45.6 25.5 24 295 +1971 9 18 0 5 DEBBY 41.9 188.6 109 883 +1992 11 1 6 1 HELENE 18.9 325.9 97 581 +1977 8 11 18 17 MICHAEL 40.9 53.0 147 733 +1978 6 3 0 25 HELENE 58.0 206.7 63 332 +2001 8 15 6 7 KIRK 59.3 212.7 38 872 +1996 10 11 6 22 CHRIS 62.4 194.8 150 498 +1971 10 28 18 25 MICHAEL 58.4 202.0 162 134 +1957 4 19 12 5 GORDON 67.1 145.8 136 812 +1976 12 26 18 5 TONY 30.4 131.0 61 580 +1975 2 17 6 15 FLORENCE 35.4 74.1 27 828 +1995 1 10 18 2 ALBERTO 55.5 120.9 135 410 +1966 12 25 12 13 PATTY 38.5 349.2 133 201 +1990 4 15 18 26 FLORENCE 53.7 201.6 103 210 +1957 8 17 6 8 FLORENCE 65.3 64.4 58 350 +1985 3 20 6 17 FLORENCE 15.8 295.3 110 879 +1975 11 13 12 16 GORDON 35.3 300.1 66 636 +1968 5 11 6 9 NADINE 30.4 212.2 18 176 +1954 6 12 12 7 TONY 31.0 92.8 84 515 +2002 6 27 18 26 HELENE 26.0 263.0 120 55 +1972 5 22 18 12 BERYL 33.8 45.2 56 703 +1961 9 3 0 27 WILLIAM 32.3 144.7 76 786 +1984 5 27 0 6 RAFAEL 44.5 114.6 100 467 +1975 9 4 6 19 KIRK 17.5 6.4 75 120 +1985 7 26 18 5 NADINE 24.9 199.6 104 887 +1986 1 21 0 17 RAFAEL 17.1 264.6 77 171 +1994 11 22 18 27 WILLIAM 43.6 64.1 129 366 +1985 7 24 18 15 TONY 40.8 216.3 41 228 +2003 3 5 18 3 FLORENCE 45.2 6.3 98 486 +1967 3 8 12 16 FLORENCE 7.7 79.3 87 563 +1981 4 18 18 18 HELENE 32.9 196.4 67 176 +1959 3 1 0 11 VALERIE 29.1 41.7 72 492 +1996 5 6 12 20 PATTY 63.9 159.7 76 58 +1997 9 16 12 12 TONY 68.7 269.9 46 684 +2004 8 3 18 9 ISAAC 45.3 337.7 17 507 +1976 11 22 0 26 JOYCE 21.5 333.2 80 103 +1978 2 20 12 1 ALBERTO 36.5 74.1 120 575 +1958 9 21 18 2 CHRIS 8.0 136.1 15 332 +1952 7 6 12 5 KIRK 33.0 321.2 73 557 +2002 5 8 12 10 WILLIAM 29.7 131.4 157 876 +1965 6 21 0 6 PATTY 31.4 137.3 121 231 +1987 11 12 18 23 TONY 35.4 270.4 49 751 +1963 10 1 12 3 ERNESTO 63.9 71.7 123 166 +1974 6 2 18 12 LESLIE 9.9 155.8 69 596 +1988 1 27 12 4 WILLIAM 16.2 81.4 13 517 +1975 5 11 12 24 ALBERTO 66.5 186.2 127 439 +1990 9 17 12 11 LESLIE 39.1 329.1 94 511 +1961 10 6 6 23 MICHAEL 11.3 36.1 38 70 +1984 10 18 0 28 CHRIS 59.3 198.5 83 630 +2003 12 5 12 28 TONY 19.3 256.9 127 279 +2003 2 3 0 10 KIRK 69.3 257.6 135 552 +1991 5 1 0 17 CHRIS 53.2 219.4 55 584 +1979 4 11 12 15 RAFAEL 40.5 73.7 122 687 +1999 6 25 6 18 DEBBY 14.3 87.8 53 789 +1991 4 1 0 18 OSCAR 49.8 163.9 35 223 +1985 8 19 6 20 KIRK 66.4 195.7 54 240 +1955 8 6 12 22 CHRIS 63.8 318.7 37 846 +1962 3 26 18 10 FLORENCE 28.9 201.7 153 758 +1967 6 15 12 10 HELENE 9.0 248.8 153 631 +2003 10 4 12 26 LESLIE 22.6 308.5 89 55 +1984 3 17 0 12 GORDON 23.7 35.8 122 748 +1992 12 28 6 8 FLORENCE 64.8 203.5 33 502 +2003 4 3 18 21 SANDY 28.0 219.0 96 443 +1970 1 26 18 25 NADINE 66.2 41.1 138 700 +1994 11 14 18 11 NADINE 49.9 297.9 143 244 +1985 1 26 12 7 ALBERTO 20.3 313.5 21 55 +1997 6 12 6 12 PATTY 34.2 13.7 40 49 +1966 12 16 18 17 OSCAR 45.0 89.8 107 55 +1996 7 7 12 2 GORDON 38.6 307.0 21 412 +1974 12 27 6 23 GORDON 59.1 39.8 116 351 +1986 1 10 0 21 ERNESTO 64.2 54.0 51 874 +1993 1 4 6 19 BERYL 45.7 10.5 35 711 +1977 1 6 12 19 MICHAEL 67.8 48.6 17 286 +1958 2 11 12 11 NADINE 48.7 26.0 23 235 +1962 11 9 0 3 WILLIAM 11.3 76.0 95 605 +1972 1 11 0 27 HELENE 52.7 259.7 84 491 +1950 10 16 0 13 ALBERTO 45.3 140.0 15 260 +1960 9 18 0 10 HELENE 12.6 72.3 36 455 +1984 4 15 0 1 CHRIS 11.6 170.0 48 738 +1990 11 11 6 23 ALBERTO 25.3 92.8 42 597 +1991 1 17 0 1 ERNESTO 52.2 327.7 62 728 +1986 1 4 18 8 ALBERTO 48.3 126.3 145 142 +1987 2 15 18 22 RAFAEL 24.1 342.9 158 118 +1980 10 6 6 16 MICHAEL 33.7 27.9 161 836 +1990 7 7 12 19 CHRIS 28.3 313.1 87 88 +1968 10 18 12 27 GORDON 16.0 104.3 155 559 +1974 3 1 6 19 MICHAEL 13.8 220.7 69 568 +1976 12 15 6 23 KIRK 68.3 34.1 130 259 +1985 3 12 12 9 ERNESTO 45.6 28.0 96 604 +1952 3 1 0 23 KIRK 66.5 170.9 148 432 +1964 12 12 12 16 TONY 19.1 1.0 62 259 +1966 6 23 12 8 NADINE 45.8 299.6 155 899 +1956 7 24 18 2 OSCAR 47.5 182.7 161 115 +1973 12 13 18 17 JOYCE 53.8 254.7 10 533 +1955 10 7 0 17 DEBBY 12.3 120.5 29 803 +1974 12 8 18 3 KIRK 28.4 296.5 58 300 +2002 12 10 6 13 WILLIAM 48.8 103.6 139 633 +1984 4 7 6 23 ALBERTO 22.8 254.7 50 376 +1971 7 16 6 1 FLORENCE 39.2 254.7 58 596 +1994 3 28 0 19 ISAAC 57.0 31.4 91 81 +1951 5 23 6 5 VALERIE 49.9 196.2 39 40 +1956 10 1 6 1 ERNESTO 7.6 123.4 53 277 +1952 6 4 18 11 BERYL 20.6 187.0 70 808 +1978 4 18 0 5 OSCAR 17.4 123.0 110 121 +1974 8 17 0 20 WILLIAM 55.1 241.8 33 191 +1952 3 17 18 17 WILLIAM 29.8 126.8 85 534 +1991 10 28 18 26 FLORENCE 62.4 58.5 60 623 +1994 1 20 12 22 FLORENCE 8.1 160.1 40 548 +1953 5 22 18 26 WILLIAM 39.9 342.0 120 320 +1980 3 3 6 8 ALBERTO 43.8 321.6 50 550 +1952 1 24 6 28 PATTY 19.0 247.1 87 272 +1992 9 8 12 21 MICHAEL 16.0 34.9 95 769 +1973 3 6 18 27 CHRIS 37.5 194.8 149 371 +1977 2 16 18 25 JOYCE 59.0 44.0 10 258 +1977 2 8 6 15 TONY 45.5 126.5 104 246 +1978 9 18 6 13 LESLIE 23.5 182.9 106 594 +1984 11 19 6 25 GORDON 14.2 210.5 17 440 +1970 5 5 0 13 MICHAEL 20.9 23.6 154 211 +1966 11 27 18 27 CHRIS 69.0 203.8 163 799 +1969 10 8 18 9 PATTY 38.0 130.4 58 532 +1966 5 6 6 20 ERNESTO 39.2 146.1 35 644 +1983 9 6 12 21 JOYCE 31.4 1.5 76 169 +1988 4 11 6 23 ALBERTO 68.7 70.5 145 467 +1969 6 8 0 13 MICHAEL 64.5 181.6 155 363 +1985 5 2 18 22 ISAAC 47.3 337.1 77 867 +1958 1 1 18 20 ALBERTO 56.6 331.5 158 599 +2001 4 23 18 15 ERNESTO 46.2 312.3 158 209 +1983 8 16 12 3 BERYL 21.4 191.4 82 802 +1966 8 17 12 2 CHRIS 38.0 344.4 35 792 +2004 1 13 6 25 LESLIE 37.9 131.4 30 277 +1981 11 4 18 5 GORDON 27.7 294.6 110 159 +2003 4 10 0 24 FLORENCE 19.1 280.3 160 746 +1989 12 28 18 22 VALERIE 38.6 109.5 158 481 +2004 8 6 12 27 VALERIE 15.1 32.3 80 854 +1976 5 7 12 2 OSCAR 10.6 258.3 134 380 +1959 7 7 6 23 ALBERTO 31.9 235.8 23 217 +1973 2 5 6 28 OSCAR 49.7 130.3 137 741 +1997 4 11 12 16 JOYCE 68.0 283.2 73 815 +1953 3 2 18 22 LESLIE 64.8 351.2 154 17 +1957 9 14 0 18 ALBERTO 63.8 162.6 24 505 +1982 3 13 6 7 CHRIS 59.4 353.5 133 887 +1966 10 20 18 11 TONY 15.0 62.5 101 469 +1995 1 3 18 1 ERNESTO 62.3 115.5 126 342 +1969 6 5 12 20 KIRK 50.1 15.2 33 645 +1974 10 25 0 23 SANDY 51.1 175.3 96 600 +1974 9 13 0 26 GORDON 54.3 192.3 128 425 +1982 1 19 0 1 WILLIAM 33.4 324.3 121 762 +1955 6 3 0 1 DEBBY 62.9 281.1 28 138 +1975 4 16 18 6 JOYCE 32.7 47.7 22 172 +2000 4 25 12 22 SANDY 21.2 292.2 55 143 +1992 10 25 6 18 PATTY 44.0 346.7 12 57 +1975 4 8 6 7 LESLIE 18.5 241.4 14 882 +1966 5 4 6 24 GORDON 11.0 66.4 147 768 +1952 12 19 6 7 CHRIS 55.6 211.7 103 246 +1994 6 4 0 20 KIRK 29.7 205.7 135 382 +1987 11 23 6 11 HELENE 65.4 191.0 109 588 +2002 8 20 0 26 DEBBY 59.0 215.3 154 100 +1961 12 27 12 22 PATTY 31.0 145.9 141 705 +1971 12 26 18 4 PATTY 23.9 212.3 155 53 +1999 3 15 0 4 BERYL 66.1 32.4 67 840 +1957 11 9 12 18 TONY 53.8 258.6 109 105 +1974 6 14 18 17 TONY 62.2 347.8 49 490 +1979 10 10 0 13 HELENE 8.4 320.5 130 317 +1987 3 20 6 4 ISAAC 52.4 242.0 119 383 +1994 10 4 6 8 ISAAC 21.7 322.5 77 760 +1955 6 12 12 18 WILLIAM 64.5 13.8 85 78 +1976 5 21 18 21 JOYCE 54.2 19.8 75 9 +1965 3 23 6 7 MICHAEL 25.6 346.5 18 329 +1999 4 3 6 3 KIRK 61.8 74.0 104 495 +1985 2 2 12 4 ISAAC 35.6 55.2 91 800 +1986 7 2 0 15 DEBBY 24.4 179.3 80 729 +1975 7 13 12 15 CHRIS 26.4 305.5 83 750 +1952 4 7 0 5 ISAAC 21.4 5.7 72 831 +1962 7 13 6 6 FLORENCE 9.7 38.5 131 50 +1982 6 13 18 1 TONY 9.1 254.8 55 569 +1968 3 26 18 28 VALERIE 69.8 152.2 26 685 +1988 9 19 6 24 OSCAR 69.4 194.3 75 814 +1955 1 1 6 17 PATTY 14.3 183.2 46 77 +1960 6 7 6 5 VALERIE 41.6 144.9 158 363 +1985 2 24 0 9 JOYCE 39.3 26.0 35 222 +1967 1 22 18 4 BERYL 8.0 40.4 69 836 +1960 2 10 12 7 LESLIE 50.6 122.0 22 264 +1965 7 14 6 2 FLORENCE 8.0 45.6 121 871 +1994 10 13 0 24 RAFAEL 34.1 18.6 115 846 +1958 11 24 0 16 DEBBY 18.7 224.9 93 347 +1974 12 18 6 13 JOYCE 18.4 218.8 53 892 +1965 1 6 12 26 RAFAEL 19.0 123.4 88 90 +1998 7 9 6 17 VALERIE 44.1 353.7 16 756 +1954 7 5 6 3 LESLIE 64.7 129.2 156 203 +1963 9 9 0 13 JOYCE 54.0 56.9 14 580 +1971 7 22 12 21 NADINE 18.2 316.5 47 837 +1982 5 27 6 20 CHRIS 68.5 306.3 98 490 +2001 7 19 18 14 LESLIE 28.6 2.0 84 806 +1996 2 12 18 25 CHRIS 16.3 87.9 19 596 +1964 3 1 6 12 OSCAR 43.8 81.6 69 802 +1952 5 15 0 13 GORDON 40.1 284.6 138 558 +1962 1 11 0 11 FLORENCE 12.4 143.8 64 576 +1997 12 11 12 6 KIRK 68.1 151.1 119 52 +1975 4 18 12 17 TONY 14.0 11.2 73 755 +1984 2 17 18 23 MICHAEL 49.3 44.8 32 580 +1980 6 25 6 25 ERNESTO 49.2 103.4 26 496 +2001 7 4 0 5 BERYL 62.7 20.7 21 26 +1982 9 18 6 27 SANDY 68.4 169.0 55 50 +1964 6 15 6 20 VALERIE 15.9 320.5 104 634 +1998 2 25 6 6 OSCAR 47.6 300.5 151 774 +1958 12 11 0 13 RAFAEL 26.1 90.9 38 331 +1969 6 3 0 7 GORDON 17.6 330.6 92 503 +1983 8 20 0 13 FLORENCE 16.7 231.2 38 248 +1973 6 27 18 20 RAFAEL 48.2 178.1 76 510 +1974 5 18 18 28 MICHAEL 53.4 261.5 122 249 +2003 2 12 6 19 TONY 62.3 247.5 45 810 +1955 3 20 12 4 NADINE 12.5 49.4 43 104 +2004 2 16 0 19 JOYCE 63.9 302.4 160 638 +1991 2 12 6 10 ISAAC 13.4 93.6 85 240 +1988 2 9 18 8 PATTY 38.1 70.5 139 158 +1985 6 23 12 26 ISAAC 17.9 296.4 55 245 +1999 4 21 18 10 ISAAC 38.9 116.6 136 278 +1977 12 14 0 8 VALERIE 67.0 165.9 75 879 +1997 4 11 18 23 MICHAEL 42.6 294.2 83 40 +1983 12 21 0 13 RAFAEL 40.2 341.5 145 390 +1996 4 4 6 25 ISAAC 42.8 253.5 164 623 +1986 1 16 0 1 ALBERTO 18.0 264.9 65 194 +1998 9 19 12 28 HELENE 51.1 312.1 112 146 +1992 8 11 12 15 ERNESTO 60.9 130.7 26 138 +1997 4 5 6 16 ISAAC 56.6 302.4 19 121 +1969 3 17 6 22 FLORENCE 20.9 255.8 143 337 +1986 8 21 12 8 VALERIE 13.7 203.3 10 803 +1959 7 23 12 8 MICHAEL 63.7 59.8 29 191 +1996 1 19 12 8 KIRK 40.3 186.7 155 218 +1952 4 9 18 13 RAFAEL 56.6 180.8 152 850 +1960 12 18 6 8 MICHAEL 30.8 122.2 144 341 +2002 5 1 0 25 FLORENCE 66.7 91.5 153 430 +1953 7 11 6 28 MICHAEL 33.0 328.9 14 459 +1965 10 15 0 20 VALERIE 30.6 203.2 122 292 +1988 1 1 6 16 LESLIE 18.0 162.0 44 582 +1994 4 2 0 5 GORDON 26.4 338.4 87 678 +1963 8 12 0 21 WILLIAM 31.0 196.8 92 17 +1981 6 1 0 24 GORDON 50.7 147.5 43 703 +2003 7 6 18 21 RAFAEL 52.8 250.8 23 651 +2004 1 12 0 26 VALERIE 22.8 219.5 88 226 +1967 5 10 6 24 NADINE 19.7 117.8 157 591 +1985 12 28 0 1 DEBBY 21.8 182.4 10 49 +1952 4 4 18 6 ERNESTO 33.7 143.6 106 484 +1965 1 9 12 19 WILLIAM 41.2 224.1 95 98 +1995 3 17 6 2 ERNESTO 66.7 117.5 82 158 +1959 6 6 6 17 PATTY 38.5 116.6 32 410 +1977 1 15 12 18 OSCAR 11.9 0.2 33 493 +1970 3 23 0 10 BERYL 31.2 171.0 113 840 +2002 5 5 0 19 BERYL 29.6 214.2 86 619 +1984 11 10 12 15 GORDON 67.6 315.0 18 612 +2004 12 6 18 4 HELENE 40.1 142.9 142 287 +1979 7 3 0 24 CHRIS 44.8 331.3 161 176 +1980 5 14 6 6 BERYL 33.8 145.8 161 540 +1995 4 8 0 23 DEBBY 49.5 211.3 57 853 +1969 8 20 12 1 TONY 35.9 273.1 65 217 +2003 2 19 12 26 MICHAEL 48.4 343.1 132 815 +1977 4 27 18 25 ALBERTO 18.0 313.6 101 153 +1961 6 8 12 9 NADINE 9.7 235.0 11 585 +1992 11 18 0 2 VALERIE 18.5 73.5 20 690 +1987 10 24 0 9 CHRIS 58.2 15.0 136 399 +1956 5 1 18 2 LESLIE 9.7 254.5 154 519 +1983 12 2 6 5 GORDON 65.7 146.9 137 201 +1989 7 5 18 19 GORDON 28.0 325.6 113 834 +1960 9 11 18 23 SANDY 23.0 307.1 129 721 +1998 6 6 18 8 OSCAR 42.5 267.0 144 286 +1958 1 17 12 19 ERNESTO 35.5 211.5 43 23 +1967 3 25 6 3 MICHAEL 66.3 191.0 30 820 +1994 6 16 12 2 KIRK 64.6 118.9 17 405 +1955 11 18 12 21 OSCAR 58.3 312.2 93 808 +1978 2 18 6 27 JOYCE 9.6 3.3 115 340 +1974 9 28 6 14 NADINE 43.3 85.1 34 183 +1957 7 25 12 13 GORDON 14.1 3.0 37 398 +2000 5 8 6 14 ERNESTO 69.5 324.6 19 375 +1991 1 14 6 25 DEBBY 69.7 118.0 86 889 +1983 2 8 6 3 JOYCE 20.0 106.5 114 496 +1971 9 21 12 26 VALERIE 15.4 315.4 139 835 +1967 7 24 12 25 RAFAEL 54.4 285.0 150 49 +1992 10 2 18 16 VALERIE 8.4 75.6 49 513 +1967 1 18 6 24 GORDON 34.1 259.6 74 605 +1950 4 6 0 3 DEBBY 64.1 172.7 94 95 +1981 3 20 6 11 ALBERTO 50.1 298.2 33 541 +2004 7 6 18 3 GORDON 49.8 214.0 137 177 +1997 9 9 0 23 RAFAEL 46.6 177.8 20 579 +1992 9 4 18 17 ISAAC 60.6 172.6 98 550 +1982 6 18 12 15 PATTY 19.3 136.6 84 826 +1985 4 20 0 12 KIRK 13.0 165.5 140 157 +1959 1 28 0 19 KIRK 62.2 33.7 101 176 +1984 3 16 18 19 VALERIE 7.2 178.6 57 593 +1965 1 26 18 24 ISAAC 16.1 105.0 144 560 +2003 6 2 12 17 WILLIAM 12.2 53.6 154 821 +2003 12 28 6 5 ISAAC 21.2 277.3 119 424 +1971 6 8 18 10 KIRK 29.3 281.3 111 51 +1980 6 23 6 3 KIRK 9.2 265.4 12 383 +1957 7 10 18 27 BERYL 23.7 174.2 109 75 +1968 8 10 18 9 TONY 7.8 10.1 95 844 +1985 7 3 18 24 CHRIS 55.8 334.7 94 174 +2004 12 10 0 2 OSCAR 16.3 199.1 154 372 +1980 11 27 18 27 LESLIE 51.6 218.3 36 123 +1977 2 26 0 22 VALERIE 26.2 73.1 26 498 +1962 7 17 18 15 WILLIAM 61.3 269.2 91 877 +1983 7 21 0 9 PATTY 7.1 9.2 72 284 +1997 7 27 18 6 SANDY 59.7 255.8 80 233 +1984 5 6 6 3 ALBERTO 43.0 55.2 54 173 +1962 7 2 18 3 DEBBY 8.2 121.1 33 729 +1979 6 15 12 27 JOYCE 60.5 70.0 128 622 +1980 9 6 6 19 NADINE 60.4 107.4 67 108 +1989 11 25 6 1 HELENE 22.7 89.6 131 227 +1997 1 1 0 26 WILLIAM 62.7 231.9 145 444 +1999 10 4 6 11 FLORENCE 43.6 205.4 51 675 +1954 5 7 12 18 MICHAEL 36.4 296.8 106 225 +1966 10 15 6 6 RAFAEL 42.5 230.3 131 620 +1972 11 21 6 13 MICHAEL 54.9 173.2 83 46 +1964 7 21 12 9 KIRK 29.3 317.7 133 356 +1989 2 5 0 2 NADINE 17.2 20.5 86 508 +1952 5 27 18 4 NADINE 42.6 190.6 143 604 +1984 9 28 12 18 JOYCE 11.0 109.4 19 507 +1992 4 23 6 16 VALERIE 33.5 94.6 29 446 +2004 2 9 12 4 BERYL 68.0 200.5 21 810 +1950 8 18 18 11 ALBERTO 36.9 224.7 36 712 +1966 12 26 0 4 RAFAEL 20.8 302.9 96 341 +1981 2 13 18 11 GORDON 43.7 144.8 89 883 +1969 10 7 0 6 MICHAEL 32.0 132.1 83 57 +1973 3 3 6 1 VALERIE 55.2 306.6 44 873 +1961 1 6 0 28 RAFAEL 66.8 129.0 154 846 +1975 5 10 18 11 LESLIE 64.9 314.0 134 239 +1950 1 23 18 19 PATTY 52.8 154.9 35 709 +1986 10 6 12 19 ERNESTO 33.2 257.3 112 643 +1965 9 21 0 16 WILLIAM 8.9 249.4 154 852 +1980 9 23 6 7 RAFAEL 43.3 109.9 93 867 +1964 7 16 12 17 OSCAR 45.7 350.9 59 109 +1993 7 23 6 5 JOYCE 22.3 308.7 141 560 +1972 9 17 0 5 FLORENCE 45.0 186.6 42 188 +1963 6 3 12 16 WILLIAM 16.9 153.5 153 863 +2000 10 23 12 25 JOYCE 62.1 63.3 106 455 +2002 3 13 6 2 NADINE 34.8 69.4 76 805 +1989 5 9 0 27 BERYL 16.3 313.7 149 285 +2004 12 9 6 3 BERYL 42.2 319.2 124 550 +1992 4 13 12 12 HELENE 34.7 332.6 18 214 +1967 10 21 0 24 MICHAEL 21.0 332.4 14 642 +1973 7 15 12 16 TONY 57.2 28.5 28 121 +1950 3 27 0 14 FLORENCE 34.3 279.4 13 448 +2000 12 17 18 25 ISAAC 27.4 274.2 19 843 +2001 8 16 0 25 OSCAR 46.8 89.8 115 73 +1967 8 11 6 11 KIRK 8.4 132.7 34 235 +2001 10 21 0 10 VALERIE 68.5 0.4 43 38 +1955 11 8 18 15 MICHAEL 64.7 167.9 143 505 +1998 7 23 0 21 PATTY 7.4 45.0 64 769 +2004 8 17 0 14 FLORENCE 14.1 200.2 164 837 +1989 4 9 6 14 PATTY 21.9 16.1 132 358 +1969 7 15 0 22 LESLIE 41.7 269.5 141 214 +1981 11 8 0 25 BERYL 47.3 310.4 25 167 +1972 12 7 0 13 JOYCE 38.9 41.4 118 604 +1964 10 4 6 4 TONY 63.7 89.0 21 746 +1951 4 9 18 1 ALBERTO 56.6 257.7 99 476 +1961 11 1 12 12 KIRK 28.5 166.6 23 365 +1992 10 19 18 25 OSCAR 8.7 305.9 107 819 +2002 5 19 6 18 ERNESTO 36.6 327.7 156 326 +1992 3 3 6 9 ALBERTO 41.8 146.8 16 272 +1954 3 14 0 20 KIRK 19.6 12.8 97 292 +1963 9 13 12 19 VALERIE 61.0 11.9 67 426 +1963 11 9 6 16 VALERIE 58.9 187.5 30 202 +1991 2 21 0 28 RAFAEL 11.4 41.6 34 570 +1983 2 24 6 20 KIRK 24.9 304.7 83 172 +1999 1 26 18 8 DEBBY 38.4 54.9 119 647 +1991 5 19 0 2 RAFAEL 15.1 339.2 117 723 +1968 11 25 6 26 HELENE 24.9 106.6 87 41 +1994 4 3 0 22 SANDY 26.3 285.9 90 692 +1958 10 2 0 8 ERNESTO 25.4 61.0 78 331 +1994 3 18 0 13 CHRIS 48.2 232.7 111 847 +1982 2 19 6 4 NADINE 57.7 6.4 140 890 +1987 3 27 18 10 ERNESTO 28.2 13.6 142 201 +1973 5 26 18 9 LESLIE 62.9 287.0 134 50 +1958 1 15 0 7 HELENE 39.8 202.7 20 501 +1984 9 21 0 12 NADINE 18.4 172.8 90 624 +1970 8 15 6 9 OSCAR 53.5 123.5 144 235 +1986 6 23 18 7 DEBBY 58.1 127.5 59 133 +1956 12 19 0 23 FLORENCE 24.1 353.0 89 314 +1995 1 6 0 27 BERYL 68.0 349.2 102 427 +1959 5 18 0 6 OSCAR 36.7 178.7 53 745 +1970 8 18 0 14 KIRK 67.9 134.9 22 376 +1992 10 6 6 4 GORDON 65.5 300.2 144 815 +1974 9 22 18 16 LESLIE 21.4 81.4 100 736 +1966 9 18 6 24 KIRK 9.8 142.4 96 395 +1964 9 10 18 11 MICHAEL 41.0 317.1 86 707 +1950 6 5 18 7 OSCAR 48.3 288.2 88 209 +1992 10 17 0 17 WILLIAM 54.7 267.9 25 363 +1998 12 14 18 8 MICHAEL 50.6 182.9 137 339 +1963 2 17 12 15 WILLIAM 18.0 338.5 80 253 +1971 10 3 12 14 KIRK 38.3 214.8 75 693 +1977 11 9 12 25 KIRK 32.3 73.4 65 518 +1956 8 25 6 25 HELENE 18.2 14.9 135 66 +1956 5 24 12 3 DEBBY 48.8 135.8 117 497 +1974 4 19 0 1 NADINE 35.5 269.6 130 569 +1964 10 27 12 27 ERNESTO 28.2 301.1 133 348 +1995 8 21 18 23 KIRK 25.1 183.3 145 93 +1970 11 8 18 22 SANDY 66.4 213.5 102 494 +1985 3 5 12 11 JOYCE 21.7 262.8 100 355 +1982 10 27 6 1 SANDY 48.8 147.6 118 318 +1980 2 11 18 9 DEBBY 16.8 110.4 119 224 +1966 2 14 18 28 MICHAEL 55.8 178.3 148 678 +1983 11 9 0 1 ISAAC 38.0 113.6 55 295 +1988 8 21 18 10 PATTY 62.7 314.5 109 747 +1988 9 3 18 26 DEBBY 24.3 31.1 51 233 +1988 3 1 18 16 BERYL 67.2 213.0 13 419 +1959 11 20 18 3 MICHAEL 48.7 144.6 71 663 +1951 2 16 0 25 DEBBY 15.0 23.3 18 60 +1992 6 9 18 21 MICHAEL 19.8 62.9 86 87 +1971 5 8 6 18 HELENE 23.3 54.3 98 360 +1953 8 1 0 18 OSCAR 19.9 226.6 51 481 +1958 1 1 18 19 RAFAEL 8.6 68.3 107 172 +1972 5 22 0 16 MICHAEL 44.3 119.5 55 846 +1995 7 21 18 12 CHRIS 24.4 26.8 141 717 +1970 5 4 6 26 MICHAEL 12.3 180.6 126 798 +1983 6 5 12 2 KIRK 44.1 292.3 23 887 +1997 5 10 6 10 ISAAC 13.8 13.2 164 236 +1988 6 3 12 24 PATTY 33.9 134.0 159 294 +1985 3 24 18 28 ISAAC 44.0 315.0 108 68 +1978 3 13 12 9 LESLIE 27.2 100.8 116 29 +1983 4 26 6 12 KIRK 21.5 346.1 63 429 +1982 8 13 6 28 NADINE 53.7 315.0 147 134 +1955 4 11 0 24 RAFAEL 28.9 306.7 40 143 +1977 1 10 0 15 FLORENCE 69.7 46.0 112 53 +1975 7 21 0 9 JOYCE 11.1 301.5 89 327 +2004 12 3 12 27 RAFAEL 25.7 30.0 160 361 +1961 8 10 0 26 VALERIE 44.0 255.1 111 425 +1995 12 24 6 17 LESLIE 20.1 236.7 61 335 +1983 8 21 6 4 JOYCE 53.9 333.7 86 390 +1998 11 19 18 9 TONY 12.6 19.1 88 685 +1973 9 1 6 12 RAFAEL 34.1 171.9 17 196 +1990 1 6 12 9 LESLIE 14.4 91.7 83 437 +1994 4 16 12 15 JOYCE 67.9 200.7 101 705 +1956 9 15 18 9 LESLIE 45.2 173.8 66 273 +1998 2 13 6 5 ERNESTO 62.7 36.4 130 552 +1985 7 8 12 19 LESLIE 36.6 89.3 151 27 +1980 5 14 18 10 KIRK 11.5 100.7 49 374 +1953 5 16 12 10 KIRK 69.8 208.8 122 63 +1973 3 24 6 1 WILLIAM 41.7 267.9 66 801 +1957 12 15 6 14 TONY 23.3 293.3 31 159 +1978 12 9 0 14 CHRIS 57.2 243.2 129 678 +1994 7 14 12 21 FLORENCE 12.4 165.5 147 748 +1972 4 22 0 2 BERYL 35.6 42.5 106 474 +1956 10 10 18 21 BERYL 67.0 332.5 111 600 +1982 12 28 6 22 WILLIAM 15.2 120.8 16 819 +1972 7 25 0 14 WILLIAM 33.5 178.0 134 347 +1988 9 18 18 4 ALBERTO 16.4 113.6 116 482 +1968 4 3 6 6 HELENE 23.4 284.3 144 517 +1976 9 26 12 21 GORDON 20.4 112.8 56 891 +1972 2 17 12 9 OSCAR 10.8 357.0 34 287 +1978 5 1 0 26 RAFAEL 36.8 237.7 26 431 +1957 8 27 18 23 CHRIS 23.8 288.9 142 614 +1976 2 26 18 16 FLORENCE 14.3 192.8 94 47 +1989 10 17 0 28 DEBBY 58.4 2.7 35 520 +1965 8 15 0 23 RAFAEL 47.4 114.3 117 479 +1989 2 20 0 8 NADINE 46.9 355.1 81 207 +2000 1 22 0 23 PATTY 40.6 129.9 119 356 +1971 1 1 6 13 RAFAEL 54.6 46.8 150 467 +1966 7 1 12 22 PATTY 46.1 294.3 145 454 +1978 12 4 6 27 MICHAEL 20.7 129.0 109 136 +1960 7 12 0 19 RAFAEL 42.6 149.2 123 597 +1961 4 21 6 22 KIRK 16.8 136.0 45 485 +1999 1 10 12 19 RAFAEL 16.7 12.5 163 202 +1954 8 3 18 16 NADINE 66.4 182.5 120 810 +1987 1 12 0 19 WILLIAM 30.5 83.2 28 205 +1957 11 12 0 9 VALERIE 42.5 325.2 151 772 +1979 8 25 12 28 BERYL 31.7 266.0 133 135 +1975 10 1 6 25 ERNESTO 26.6 305.0 95 42 +1996 12 15 12 13 FLORENCE 8.3 62.2 127 188 +1962 6 25 18 26 WILLIAM 9.7 325.0 90 181 +1998 9 19 0 11 DEBBY 50.4 66.7 90 99 +1982 12 10 18 18 LESLIE 49.7 204.2 28 673 +1959 7 2 0 14 HELENE 20.3 253.3 28 421 +2001 10 20 6 23 VALERIE 26.0 169.2 74 264 +1974 8 2 0 3 TONY 26.1 145.4 149 156 +1957 4 28 6 24 GORDON 47.8 62.2 110 770 +1981 1 8 6 23 DEBBY 69.5 16.5 126 360 +2002 2 14 18 22 ALBERTO 35.1 254.6 68 894 +1972 8 9 6 6 FLORENCE 46.5 243.4 35 491 +1963 3 15 6 17 KIRK 59.7 267.9 117 16 +1965 3 5 6 14 JOYCE 26.6 110.9 102 110 +1971 9 22 6 1 DEBBY 23.0 80.4 61 732 +1976 3 9 0 7 ALBERTO 46.6 142.4 10 703 +1975 1 23 12 1 RAFAEL 57.4 139.8 160 503 +1988 10 23 0 21 NADINE 11.5 279.9 29 735 +1984 4 21 12 5 SANDY 32.4 344.5 67 54 +1959 6 27 18 8 MICHAEL 31.4 222.1 122 301 +1993 4 3 6 25 MICHAEL 69.6 35.1 121 19 +1993 2 2 0 7 OSCAR 26.9 297.9 28 194 +1972 8 2 0 13 SANDY 69.2 83.4 96 48 +1950 11 18 18 12 GORDON 31.5 316.8 91 124 +1971 10 14 6 2 DEBBY 57.3 291.9 142 605 +1955 3 2 0 14 MICHAEL 11.6 135.2 42 896 +1978 5 3 18 9 TONY 13.1 0.7 124 111 +1990 1 21 0 1 OSCAR 13.7 329.2 142 349 +1967 2 3 6 19 ALBERTO 54.5 157.8 19 744 +2000 11 28 18 20 CHRIS 10.6 257.2 110 868 +1962 4 2 0 18 DEBBY 57.5 83.0 102 137 +1967 10 9 18 7 BERYL 20.3 212.5 87 733 +1973 7 25 6 10 CHRIS 35.6 320.6 138 123 +1966 1 22 18 21 SANDY 53.8 174.5 75 428 +1975 11 17 12 5 PATTY 66.3 109.1 130 110 +1965 4 22 0 10 DEBBY 10.7 18.5 98 157 +1951 1 22 0 22 ALBERTO 56.3 154.4 159 346 +1952 7 4 6 27 ALBERTO 23.8 108.0 107 471 +1999 12 5 6 17 RAFAEL 67.2 357.9 57 822 +1978 9 28 6 10 SANDY 44.2 113.4 135 295 +1975 6 4 12 11 ALBERTO 33.9 202.3 133 587 +1990 10 2 0 1 ISAAC 64.0 298.1 126 533 +2002 12 19 6 3 JOYCE 52.2 302.3 76 116 +1955 6 11 6 4 FLORENCE 14.5 249.8 43 784 +1975 5 8 12 19 ALBERTO 49.9 313.5 162 845 +1993 1 1 6 21 WILLIAM 26.6 158.7 26 389 +1955 4 19 6 10 SANDY 58.6 114.2 121 466 +1990 6 17 0 1 OSCAR 47.1 27.4 77 601 +1966 6 8 0 9 BERYL 31.0 124.2 158 323 +1986 1 15 18 9 ALBERTO 32.4 263.2 97 353 +1999 11 13 18 9 HELENE 27.0 87.7 27 794 +1953 12 9 6 3 HELENE 39.0 347.4 116 151 +1994 12 5 6 26 GORDON 14.0 42.1 96 248 +1960 12 27 6 16 ISAAC 57.0 271.8 90 109 +1997 10 8 6 21 CHRIS 13.9 267.0 59 753 +1970 12 25 12 27 JOYCE 69.7 213.7 126 330 +1971 11 26 18 18 CHRIS 40.3 108.0 102 242 +1993 9 11 6 2 NADINE 28.9 175.2 106 549 +1994 2 20 6 26 CHRIS 51.2 247.0 46 425 +1950 7 5 0 24 JOYCE 69.9 59.4 82 290 +1979 5 15 18 4 MICHAEL 30.8 130.5 97 527 +1975 4 14 18 9 HELENE 59.7 191.2 82 556 +1961 2 14 18 11 OSCAR 47.3 131.2 27 703 +1965 4 26 18 16 GORDON 37.1 48.3 158 344 +1998 12 24 0 9 ERNESTO 30.5 48.9 61 776 +1964 8 20 0 8 ISAAC 47.5 140.4 144 839 +1982 6 19 6 22 TONY 10.4 305.2 119 727 +1964 11 27 0 25 RAFAEL 65.4 74.6 108 585 +1987 2 18 6 18 ISAAC 16.9 214.2 128 379 +1952 10 5 6 18 NADINE 27.8 63.5 39 363 +1959 2 5 6 10 NADINE 34.1 64.5 141 144 +1970 4 23 12 27 VALERIE 48.8 127.6 57 780 +1974 12 1 12 3 RAFAEL 8.7 184.0 153 354 +1995 9 25 6 9 GORDON 20.1 32.1 30 132 +1992 10 10 0 24 KIRK 18.7 78.5 117 44 +1981 6 5 12 11 HELENE 51.2 16.9 41 894 +1978 7 3 6 27 LESLIE 65.0 214.0 42 5 +1977 2 20 0 23 TONY 63.9 94.2 53 270 +1967 2 24 0 10 LESLIE 36.3 75.5 161 797 +1976 4 21 6 27 KIRK 46.8 39.9 34 567 +1966 1 7 12 2 VALERIE 27.2 54.4 143 109 +1980 3 2 18 16 SANDY 20.6 4.5 29 309 +1975 2 14 12 16 FLORENCE 43.3 224.7 36 559 +1952 12 28 0 24 PATTY 60.9 105.7 44 573 +1973 3 28 6 15 TONY 51.3 157.3 50 467 +1961 1 5 0 17 MICHAEL 40.7 194.7 86 865 +1971 4 17 18 3 MICHAEL 32.9 308.3 12 87 +1967 9 19 0 16 CHRIS 44.8 90.6 70 329 +1951 1 26 6 28 BERYL 44.2 29.6 121 884 +1952 4 14 12 27 BERYL 30.8 21.2 157 710 +1954 8 28 0 8 TONY 16.3 235.6 49 620 +1971 10 13 18 9 WILLIAM 34.7 27.6 43 558 +1982 5 2 12 13 WILLIAM 54.7 109.8 55 240 +1995 7 18 6 18 ISAAC 37.3 247.9 158 449 +1973 1 15 6 13 TONY 57.5 348.6 28 390 +1952 11 23 18 23 CHRIS 48.6 247.1 25 90 +1993 6 5 12 24 KIRK 22.1 342.7 55 895 +1973 7 27 12 20 MICHAEL 42.5 36.2 88 892 +1992 10 23 18 19 HELENE 7.4 236.6 136 151 +1992 5 2 12 22 ISAAC 44.9 346.2 155 74 +2000 4 9 6 19 ERNESTO 32.5 296.1 101 896 +1970 1 4 12 11 ISAAC 39.6 314.8 138 550 +1967 9 4 6 17 JOYCE 53.6 103.5 18 560 +1993 7 5 18 3 VALERIE 11.6 352.8 52 386 +1957 2 21 0 9 OSCAR 50.1 354.2 30 412 +1955 1 20 6 25 ERNESTO 46.9 235.8 28 745 +1994 1 23 12 21 DEBBY 33.6 21.6 14 60 +1958 8 12 0 13 BERYL 64.0 87.6 158 245 +1972 11 7 18 28 HELENE 13.2 35.4 108 399 +1989 12 24 0 5 ISAAC 67.9 340.9 66 707 +1957 9 20 6 16 PATTY 60.1 190.7 141 173 +2004 8 27 12 7 WILLIAM 34.1 85.3 97 669 +2000 5 14 12 17 CHRIS 68.4 347.9 53 32 +1967 5 13 12 2 FLORENCE 60.9 297.7 103 539 +1985 12 23 0 12 NADINE 14.0 104.3 41 814 +1977 2 27 0 26 OSCAR 42.1 163.3 67 610 +1979 8 19 6 26 BERYL 31.8 197.3 22 642 +1965 11 13 18 6 ERNESTO 12.2 344.0 131 248 +1987 7 6 6 4 RAFAEL 22.9 98.5 149 285 +1993 5 22 0 8 CHRIS 51.1 309.6 97 34 +1997 9 23 12 8 NADINE 44.2 251.3 32 600 +1985 4 16 0 17 WILLIAM 50.4 228.0 159 17 +1986 8 18 12 19 ERNESTO 39.3 60.0 42 100 +1987 10 8 0 14 ISAAC 16.3 169.3 136 24 +1995 4 6 0 15 JOYCE 44.3 160.8 118 596 +1951 12 3 0 7 HELENE 30.5 221.3 49 228 +1952 2 22 18 9 NADINE 17.7 265.5 91 577 +1967 2 26 12 21 CHRIS 20.1 129.1 101 813 +1981 10 14 6 14 CHRIS 13.7 123.8 60 763 +1989 9 15 6 18 GORDON 39.5 162.1 40 338 +1956 8 4 18 13 ERNESTO 54.1 123.0 145 471 +1975 10 5 18 25 TONY 48.5 90.9 141 199 +1982 4 2 18 13 PATTY 10.6 100.1 67 388 +1995 5 27 12 27 TONY 42.3 228.1 24 612 +1999 1 20 6 13 VALERIE 27.5 289.1 59 527 +1981 4 17 18 25 WILLIAM 26.2 325.0 58 207 +1999 10 18 0 4 MICHAEL 39.4 315.6 161 743 +1963 2 10 18 24 NADINE 42.8 190.9 143 703 +1997 5 17 18 7 JOYCE 21.8 54.6 80 565 +1982 11 9 12 7 ALBERTO 42.5 158.6 146 278 +1951 2 1 0 17 ALBERTO 43.8 2.0 139 44 +1985 10 7 12 22 CHRIS 66.1 267.3 158 537 +1997 4 1 0 3 RAFAEL 32.8 199.9 139 851 +1959 9 11 18 25 ALBERTO 65.0 55.6 81 722 +1967 4 23 6 9 JOYCE 60.2 218.5 38 618 +1992 4 4 0 15 VALERIE 34.6 122.7 88 113 +1991 6 15 18 4 LESLIE 30.1 321.4 95 417 +1967 7 7 0 6 ALBERTO 25.2 347.5 148 573 +1971 10 25 12 7 DEBBY 36.8 220.7 149 469 +1985 9 24 0 21 KIRK 17.5 340.7 41 113 +1975 5 12 18 11 GORDON 24.9 190.3 149 688 +1955 11 4 0 20 MICHAEL 19.0 60.2 41 290 +1968 12 15 18 24 GORDON 66.3 211.0 105 93 +1951 7 22 12 3 MICHAEL 57.8 336.7 136 269 +1969 12 9 6 25 ERNESTO 8.8 248.7 151 9 +1988 7 12 6 2 WILLIAM 45.1 303.0 147 333 +1984 2 3 12 11 NADINE 16.5 226.8 125 458 +2004 4 10 0 26 RAFAEL 56.6 47.5 16 534 +1974 11 20 0 11 DEBBY 11.7 13.9 98 113 +1967 8 8 6 8 FLORENCE 63.3 340.4 97 303 +1981 7 6 0 15 FLORENCE 66.4 183.4 130 133 +1950 11 16 12 15 LESLIE 54.8 10.1 135 9 +1969 2 7 0 22 ISAAC 8.2 31.2 89 260 +1986 3 13 0 28 LESLIE 60.3 219.2 35 289 +1970 5 4 12 24 SANDY 45.9 63.8 124 432 +1988 9 2 18 1 MICHAEL 19.1 322.3 51 71 +1952 1 27 12 5 ERNESTO 48.8 346.9 92 121 +1960 2 7 18 16 SANDY 36.1 191.8 74 792 +1987 4 23 12 11 GORDON 29.3 226.5 106 525 +1991 5 14 6 8 SANDY 27.6 74.3 42 596 +1993 12 6 0 21 OSCAR 12.5 6.2 145 690 +1995 4 8 18 16 PATTY 17.6 273.8 32 570 +2001 6 11 0 3 KIRK 16.9 124.9 37 672 +1999 3 23 12 1 NADINE 9.9 8.5 130 709 +2002 7 16 18 4 ISAAC 13.3 306.4 121 4 +1989 1 12 0 26 ALBERTO 16.0 172.7 38 124 +1966 8 24 6 12 RAFAEL 24.5 325.2 42 70 +1989 4 6 6 3 RAFAEL 26.9 121.5 19 782 +1953 9 19 12 4 OSCAR 45.0 194.7 108 347 +1994 10 10 18 3 VALERIE 7.4 171.0 54 676 +1998 10 24 6 3 ISAAC 13.7 235.6 106 450 +1978 7 20 18 5 JOYCE 63.3 227.8 150 685 +1985 11 20 6 22 TONY 27.6 63.7 118 629 +1964 4 18 18 27 NADINE 39.1 128.9 85 619 +1992 8 8 6 12 TONY 54.1 259.2 11 763 +1956 6 22 18 3 ERNESTO 12.9 334.1 35 86 +1986 11 28 0 7 CHRIS 64.8 160.7 162 235 +1985 10 27 0 28 HELENE 47.7 216.1 70 36 +1962 3 23 0 5 SANDY 33.3 279.4 78 668 +1981 7 22 12 18 RAFAEL 39.1 189.1 141 380 +1953 11 13 0 7 TONY 15.6 159.1 106 805 +1992 3 4 0 21 ERNESTO 26.1 191.3 61 84 +1989 4 1 6 12 VALERIE 49.3 130.6 38 280 +1954 10 28 6 21 NADINE 42.1 167.5 59 385 +1967 7 16 12 20 GORDON 43.2 167.3 128 106 +1986 12 28 0 10 CHRIS 11.4 274.6 99 276 +1967 3 28 0 12 FLORENCE 41.9 310.2 152 27 +1979 1 12 6 16 NADINE 67.1 152.8 149 150 +1987 4 25 12 16 MICHAEL 23.2 289.3 101 833 +2003 2 8 18 19 BERYL 8.5 116.0 50 231 +1996 5 14 0 15 HELENE 15.1 282.2 101 209 +1981 3 5 18 13 FLORENCE 49.8 271.0 33 607 +1972 7 27 0 9 OSCAR 20.6 55.5 152 821 +1979 11 3 12 1 LESLIE 56.6 295.2 22 535 +1954 9 3 6 1 PATTY 12.8 131.6 161 760 +1986 5 21 0 18 SANDY 55.9 330.8 28 114 +1976 4 24 0 24 LESLIE 30.1 354.7 22 796 +1974 5 9 12 27 DEBBY 10.9 293.4 125 407 +1984 3 5 0 19 FLORENCE 69.4 47.7 126 634 +1979 11 22 12 25 BERYL 46.3 227.1 54 183 +1984 9 28 12 7 ERNESTO 46.6 108.3 130 145 +1964 9 9 0 7 VALERIE 54.2 312.8 106 390 +1985 6 10 6 26 MICHAEL 60.6 229.9 114 257 +1979 1 3 18 3 ERNESTO 61.6 268.4 28 894 +2001 3 11 18 7 GORDON 50.4 314.2 130 899 +1989 2 21 6 18 HELENE 21.8 211.0 136 734 +1954 6 27 6 22 ALBERTO 46.9 216.7 14 634 +1953 7 14 18 14 ISAAC 7.4 196.2 140 819 +1991 8 26 18 25 LESLIE 13.4 61.9 128 517 +1956 10 12 12 27 OSCAR 63.6 46.4 147 408 +1967 10 4 6 25 FLORENCE 31.6 247.6 64 35 +1982 2 13 0 2 PATTY 21.1 95.9 75 633 +1998 11 5 12 13 OSCAR 15.3 207.9 79 549 +1957 6 6 6 16 MICHAEL 47.8 203.3 91 122 +1960 9 10 6 21 SANDY 40.7 127.6 156 17 +1965 2 14 18 28 CHRIS 8.4 150.7 87 629 +1956 11 14 12 27 VALERIE 29.1 171.2 59 125 +1967 12 15 6 15 JOYCE 68.2 340.3 137 166 +1988 12 4 18 18 PATTY 44.1 70.9 51 555 +1967 10 24 18 8 LESLIE 21.0 326.3 35 38 +1952 7 3 12 27 GORDON 26.8 317.8 80 50 +1958 12 17 12 14 WILLIAM 34.3 331.6 148 446 +1959 5 2 12 16 DEBBY 63.0 160.0 10 725 +1957 3 5 12 19 PATTY 56.0 214.4 14 240 +1975 9 9 6 26 GORDON 15.8 316.0 48 619 +1993 12 28 0 27 MICHAEL 69.1 87.4 62 478 +1985 6 11 0 27 NADINE 31.7 58.3 94 787 +1954 1 28 18 13 ERNESTO 67.7 106.3 38 230 +1992 8 3 12 23 GORDON 9.4 81.4 75 867 +2004 12 28 12 4 VALERIE 19.1 292.8 163 452 +1957 2 6 12 12 SANDY 21.2 214.7 117 852 +2003 2 16 18 13 OSCAR 31.6 256.4 70 14 +1984 6 14 6 27 HELENE 47.8 7.3 54 372 +1998 8 4 12 2 HELENE 8.9 159.3 113 682 +1977 1 24 18 22 LESLIE 68.7 16.8 137 218 +1957 1 8 18 7 CHRIS 13.3 266.7 76 630 +1963 1 26 0 19 ALBERTO 40.9 146.1 21 750 +1981 1 17 18 19 KIRK 36.5 286.1 83 775 +1980 12 11 18 2 ERNESTO 47.0 85.9 152 501 +1958 7 1 18 16 TONY 41.7 211.8 59 173 +1989 5 19 12 14 HELENE 45.2 240.4 85 378 +1961 8 27 12 3 KIRK 53.6 0.9 104 163 +1964 1 26 12 3 FLORENCE 16.4 321.7 17 424 +1951 3 13 18 10 ISAAC 30.8 124.6 102 860 +1961 10 9 6 26 OSCAR 41.6 332.3 33 438 +1984 3 27 6 28 OSCAR 62.5 140.5 87 391 +1969 12 4 12 28 OSCAR 59.3 9.5 159 344 +1976 11 22 18 21 BERYL 54.9 277.3 161 129 +1961 5 4 6 15 SANDY 30.4 117.2 57 544 +1964 7 17 0 25 HELENE 61.7 237.7 64 293 +1957 8 20 18 4 SANDY 9.8 337.3 67 881 +1976 12 16 12 16 PATTY 38.1 211.0 103 529 +1998 11 1 12 17 KIRK 51.2 122.5 46 325 +2002 6 12 0 5 BERYL 31.0 155.8 115 689 +1959 10 3 0 21 ISAAC 48.8 208.7 16 690 +1971 3 17 18 26 PATTY 59.9 192.2 102 411 +1993 6 17 12 10 CHRIS 19.5 75.1 10 565 +1970 12 3 18 27 FLORENCE 36.5 278.5 28 561 +1992 7 5 12 22 KIRK 51.8 109.3 50 54 +1994 5 4 18 14 HELENE 62.5 86.4 109 334 +1982 12 22 0 18 GORDON 31.3 33.2 50 398 +1960 4 9 18 26 LESLIE 25.7 169.2 97 598 +1996 11 6 18 2 LESLIE 38.0 33.6 142 398 +1982 5 28 0 7 OSCAR 64.6 78.0 42 314 +1950 3 13 6 25 FLORENCE 36.2 258.8 17 641 +1953 8 3 0 3 VALERIE 54.7 342.5 131 391 +2003 4 9 0 27 PATTY 8.2 355.6 48 671 +1984 3 14 6 16 KIRK 61.0 216.8 42 576 +1952 10 17 6 24 VALERIE 68.0 276.4 95 798 +1970 3 5 0 6 GORDON 16.9 45.0 97 184 +1982 10 15 6 10 VALERIE 18.5 56.2 106 622 +1988 9 14 18 26 LESLIE 25.4 194.5 133 447 +1994 6 2 6 2 CHRIS 17.6 77.1 11 247 +1996 1 10 0 15 VALERIE 64.5 204.2 158 847 +1982 10 2 12 15 PATTY 8.4 212.7 127 401 +2002 10 7 6 3 ERNESTO 52.7 141.7 83 667 +1974 2 25 6 25 FLORENCE 40.2 107.2 111 811 +1980 4 18 0 3 OSCAR 59.8 174.3 151 176 +2003 12 24 12 17 ALBERTO 60.2 138.6 56 117 +1994 9 14 12 2 LESLIE 55.0 74.1 154 225 +1980 4 4 0 28 DEBBY 36.0 297.0 82 873 +1950 8 22 18 21 GORDON 37.7 142.9 92 467 +1989 9 2 18 3 ERNESTO 34.1 143.8 93 500 +1968 6 9 12 2 MICHAEL 35.3 74.0 16 161 +1998 5 11 0 7 BERYL 36.9 71.1 42 895 +1978 6 17 0 21 HELENE 13.0 44.8 87 668 +1958 8 17 6 20 NADINE 50.0 1.8 38 439 +1953 10 2 0 26 JOYCE 25.4 56.8 33 821 +1982 3 23 18 28 VALERIE 37.6 157.9 52 488 +1954 9 11 6 10 HELENE 19.4 142.2 18 26 +1988 2 27 6 2 RAFAEL 37.0 347.4 54 481 +1989 10 5 0 18 KIRK 28.0 51.8 145 699 +1961 12 28 12 14 TONY 34.5 129.9 63 458 +1952 11 25 0 20 PATTY 22.7 117.1 94 120 +1958 8 6 0 26 GORDON 61.1 216.3 81 137 +1987 3 13 6 18 BERYL 42.0 353.0 124 670 +1952 10 5 6 7 RAFAEL 16.6 110.5 24 363 +1995 2 20 18 25 ISAAC 26.9 165.6 32 129 +1984 9 18 18 9 ALBERTO 22.9 350.3 156 732 +1968 9 15 12 16 OSCAR 14.3 113.9 100 194 +1987 6 19 6 7 DEBBY 11.0 91.2 148 100 +1951 11 19 12 17 ALBERTO 43.6 226.6 123 565 +1965 6 8 12 3 LESLIE 21.1 282.4 145 844 +1952 5 11 6 20 KIRK 34.4 326.2 123 158 +1998 10 20 0 7 RAFAEL 39.2 14.0 84 65 +2003 7 18 18 18 MICHAEL 53.9 54.5 135 166 +1974 5 19 0 5 MICHAEL 17.3 268.2 152 64 +1963 12 13 18 13 FLORENCE 34.0 44.4 79 385 +1998 5 5 12 3 VALERIE 41.5 56.5 162 444 +1997 1 18 0 7 DEBBY 58.1 268.8 18 558 +1972 2 16 18 19 OSCAR 57.8 321.3 81 579 +1955 8 1 0 22 WILLIAM 24.3 249.5 16 263 +1969 6 14 18 27 CHRIS 42.6 125.7 101 213 +2002 7 11 12 4 TONY 39.8 171.1 135 111 +1963 9 8 18 7 KIRK 65.0 125.8 32 75 +1986 4 22 0 5 ISAAC 48.9 276.6 17 375 +1985 5 7 18 3 RAFAEL 25.0 69.5 58 689 +1975 3 6 12 27 OSCAR 62.8 269.9 11 691 +1985 10 17 0 6 TONY 64.3 311.6 17 525 +2003 2 23 18 12 ERNESTO 43.6 226.9 92 634 +1998 4 23 0 19 ERNESTO 59.2 197.5 154 669 +1951 11 5 12 1 PATTY 10.7 341.4 49 316 +1988 10 5 0 12 TONY 41.2 327.6 49 163 +1973 10 19 12 25 JOYCE 33.3 271.5 138 708 +1975 5 10 0 27 SANDY 50.5 312.0 87 178 +1995 1 12 18 1 GORDON 38.3 294.5 125 730 +1984 9 26 6 28 BERYL 34.9 339.8 148 181 +1956 3 19 18 19 MICHAEL 23.8 356.4 86 636 +2002 4 16 0 9 TONY 57.3 327.0 76 636 +2001 10 3 6 8 VALERIE 28.0 353.9 96 254 +1986 5 7 6 6 ISAAC 65.8 265.0 159 773 +2001 10 12 12 18 PATTY 39.7 273.0 57 39 +2001 1 8 6 26 RAFAEL 9.6 175.8 107 322 +1982 1 22 6 14 MICHAEL 21.9 6.7 19 587 +1995 4 28 6 28 OSCAR 44.3 3.7 159 550 +1953 10 9 18 19 SANDY 43.3 347.3 78 885 +1966 4 5 6 18 JOYCE 24.5 270.9 61 715 +1984 6 21 12 26 TONY 39.9 311.4 14 642 +1975 4 21 18 7 RAFAEL 40.1 247.9 78 225 +1973 5 21 6 18 KIRK 52.3 102.2 32 91 +1979 6 27 18 7 BERYL 62.0 260.5 74 546 +1958 5 9 6 25 KIRK 47.2 150.3 133 841 +1977 4 9 6 9 WILLIAM 57.8 156.4 39 188 +1986 8 19 18 2 HELENE 54.2 345.6 75 11 +2004 8 10 18 18 ALBERTO 43.6 14.2 141 86 +1963 11 7 0 6 JOYCE 28.8 324.4 24 653 +1988 7 21 0 21 WILLIAM 66.3 109.3 157 253 +1980 7 10 12 8 PATTY 23.6 131.9 139 394 +1953 10 7 18 8 BERYL 18.0 276.6 80 601 +1995 9 5 0 5 RAFAEL 28.7 336.2 161 111 +1990 5 5 18 12 ISAAC 28.5 183.3 133 617 +1972 7 2 12 20 ISAAC 44.3 197.0 94 798 +1967 7 24 12 18 JOYCE 49.9 328.6 76 557 +1999 4 20 18 23 NADINE 45.4 128.1 62 475 +1979 11 4 12 3 NADINE 55.4 121.0 87 494 +1958 12 6 18 9 JOYCE 15.3 174.9 104 41 +1959 3 26 6 5 WILLIAM 58.8 75.9 132 573 +1955 4 13 0 27 GORDON 29.4 257.7 147 225 +1958 1 25 12 17 ISAAC 63.1 82.9 79 829 +1988 4 22 0 28 ALBERTO 38.9 199.2 23 381 +1952 2 22 6 23 KIRK 59.7 231.2 49 797 +1954 5 19 6 10 GORDON 61.8 299.2 85 120 +1969 1 23 12 15 PATTY 10.9 42.9 92 636 +1987 7 23 18 21 WILLIAM 58.9 272.7 21 359 +1987 1 23 6 12 DEBBY 52.1 109.9 74 44 +1975 10 7 12 12 FLORENCE 40.1 254.3 64 632 +1958 2 6 6 17 ISAAC 54.9 257.9 104 371 +1972 1 19 6 16 BERYL 61.0 18.0 28 188 +1990 4 6 6 20 MICHAEL 62.3 66.3 60 820 +1966 12 2 12 27 ERNESTO 56.7 14.6 105 615 +1992 8 28 0 12 OSCAR 59.8 246.2 159 375 +1976 5 18 0 20 MICHAEL 30.6 180.8 139 238 +1973 7 8 12 3 LESLIE 51.8 111.7 129 552 +1952 6 14 6 11 SANDY 13.5 289.2 65 6 +2004 4 2 12 18 ERNESTO 35.3 110.1 148 798 +1977 11 24 18 12 VALERIE 64.2 235.5 110 372 +1991 2 27 18 20 LESLIE 26.5 262.1 163 517 +1967 2 25 6 26 SANDY 48.3 81.5 155 738 +1980 7 3 6 12 OSCAR 66.8 328.0 75 296 +1977 5 3 0 27 JOYCE 14.2 98.7 16 769 +1962 4 1 12 15 VALERIE 52.9 41.4 88 308 +1967 1 5 18 20 PATTY 46.8 118.2 144 589 +2002 11 21 6 4 MICHAEL 25.1 109.6 149 42 +1954 5 9 12 12 RAFAEL 13.5 215.3 136 486 +1965 2 7 18 21 GORDON 30.0 185.1 40 508 +1975 10 27 0 17 OSCAR 36.4 270.0 39 122 +1955 2 1 0 5 HELENE 35.4 285.8 71 683 +1984 10 6 6 2 RAFAEL 62.0 147.5 97 341 +1996 5 15 6 19 FLORENCE 26.4 49.5 137 35 +1992 10 9 12 11 OSCAR 32.9 253.3 36 667 +1966 2 2 0 6 ERNESTO 36.5 219.6 80 369 +1959 6 17 0 2 ALBERTO 16.2 312.6 74 191 +1992 4 6 6 15 KIRK 62.5 96.9 27 807 +1978 7 15 18 3 MICHAEL 16.8 282.7 145 778 +1977 4 3 0 24 WILLIAM 43.2 129.7 139 85 +1966 6 19 18 7 CHRIS 50.4 242.9 140 238 +1992 4 11 6 24 BERYL 58.6 137.9 138 432 +1981 3 4 0 15 MICHAEL 52.1 147.4 134 279 +1966 11 23 18 20 BERYL 26.4 200.1 88 223 +1987 12 3 18 17 ERNESTO 67.5 239.9 159 278 +2003 9 15 0 1 VALERIE 7.4 129.4 142 406 +1993 8 23 18 19 ISAAC 48.5 49.0 144 886 +1994 11 21 12 10 MICHAEL 28.3 238.6 22 362 +1964 5 25 18 7 KIRK 67.0 358.0 65 895 +2002 11 12 0 12 KIRK 69.4 99.6 29 282 +1970 9 4 12 7 GORDON 65.7 308.0 103 441 +1971 11 27 0 18 DEBBY 14.2 331.9 48 404 +1954 7 23 12 9 CHRIS 59.4 256.7 110 436 +1968 9 11 18 22 ALBERTO 10.7 242.7 21 38 +1959 12 2 12 11 RAFAEL 65.7 349.3 28 487 +1979 12 1 12 20 GORDON 9.8 302.7 39 753 +1977 11 18 0 18 SANDY 43.5 222.3 46 623 +1977 9 28 18 15 LESLIE 23.1 205.0 49 604 +1955 12 24 18 9 HELENE 11.0 322.9 114 433 +1978 7 9 18 6 FLORENCE 50.6 206.1 155 616 +1952 1 23 18 17 SANDY 42.4 338.6 133 387 +2004 4 24 6 26 BERYL 13.9 237.8 99 106 +1988 9 25 18 18 MICHAEL 39.0 174.5 10 674 +1961 8 23 0 12 HELENE 47.6 158.1 145 453 +1956 12 26 12 3 SANDY 40.2 328.4 132 197 +1966 12 22 6 10 JOYCE 23.1 203.0 131 499 +1985 3 4 18 9 RAFAEL 68.6 158.9 108 402 +1977 4 3 6 21 GORDON 47.6 344.4 90 29 +1969 10 25 12 16 BERYL 30.4 229.5 153 37 +1981 3 7 6 5 FLORENCE 26.5 115.5 20 741 +1956 11 6 18 12 SANDY 30.2 187.6 83 558 +1985 5 5 12 14 SANDY 9.3 238.8 14 748 +1973 9 27 0 15 WILLIAM 12.8 198.9 131 339 +1994 1 17 0 2 WILLIAM 19.9 356.2 116 67 +1994 12 19 18 26 NADINE 63.1 80.9 96 352 +1966 4 6 6 27 FLORENCE 42.0 277.1 48 835 +1961 10 6 6 12 ERNESTO 37.7 324.9 74 774 +1960 3 4 18 14 WILLIAM 22.4 60.1 53 350 +1971 12 23 12 4 OSCAR 63.2 175.9 140 714 +1978 2 14 0 1 JOYCE 25.8 84.9 75 159 +1956 12 18 6 16 JOYCE 65.2 266.7 21 754 +1963 9 13 12 11 TONY 13.0 217.6 121 9 +1953 5 7 6 26 CHRIS 50.8 21.1 131 728 +1970 9 9 18 27 ISAAC 35.8 319.3 111 849 +1969 2 12 0 20 GORDON 47.8 253.1 135 158 +1963 8 18 0 2 HELENE 40.8 53.2 55 475 +1963 12 5 18 26 RAFAEL 21.8 265.7 104 877 +1995 2 4 18 10 OSCAR 60.1 291.2 141 14 +1954 1 9 0 26 KIRK 16.7 59.7 12 502 +1973 5 2 12 1 ALBERTO 62.7 306.3 109 327 +1953 3 3 6 2 PATTY 48.9 214.3 115 471 +1954 9 21 18 25 SANDY 35.1 164.5 16 61 +2002 7 8 12 25 OSCAR 36.0 106.1 125 255 +1989 10 21 18 3 ERNESTO 67.1 143.3 50 230 +2002 10 4 18 9 HELENE 37.1 132.5 80 664 +1984 8 1 6 8 JOYCE 56.4 287.1 144 841 +1968 7 10 18 18 DEBBY 60.7 255.5 124 427 +2001 11 17 12 18 GORDON 40.4 180.7 148 777 +1992 8 2 18 17 MICHAEL 60.6 344.8 81 733 +1991 8 25 12 8 HELENE 23.2 19.6 111 823 +1976 8 16 12 6 WILLIAM 43.2 32.2 102 732 +1967 5 27 12 3 VALERIE 31.1 95.0 42 66 +1983 1 5 0 19 ISAAC 62.5 294.9 64 389 +2002 8 24 0 8 CHRIS 19.4 62.6 80 666 +1997 11 16 12 15 RAFAEL 21.2 300.0 53 416 +1986 12 3 12 7 DEBBY 21.5 351.1 48 845 +1974 12 19 12 12 ERNESTO 14.9 222.7 98 422 +1975 3 8 0 4 ISAAC 68.3 21.9 125 769 +1958 5 4 18 20 FLORENCE 25.1 277.1 83 776 +1958 6 3 6 21 DEBBY 45.6 31.6 63 301 +1993 11 12 6 2 CHRIS 68.0 130.8 114 651 +1973 11 18 18 1 BERYL 58.4 45.6 96 127 +1972 2 14 18 5 KIRK 27.2 342.6 36 527 +1992 10 15 12 23 TONY 22.0 52.4 51 139 +1979 8 21 0 2 VALERIE 49.9 127.1 140 375 +1993 3 6 18 14 ALBERTO 15.6 229.4 146 807 +1962 9 13 0 12 SANDY 24.0 325.6 112 701 +1973 2 13 0 12 RAFAEL 41.3 238.7 105 509 +2003 6 5 18 27 OSCAR 54.2 292.1 25 822 +1983 12 28 12 23 SANDY 30.3 132.9 125 237 +1967 12 2 6 10 ALBERTO 56.6 147.3 29 512 +1994 2 25 0 1 KIRK 41.8 61.4 106 165 +1988 6 1 18 6 HELENE 19.1 107.2 132 864 +1971 7 16 18 18 RAFAEL 64.1 251.3 121 11 +2002 2 28 12 27 DEBBY 56.2 250.1 115 263 +1977 4 15 6 26 ALBERTO 32.3 216.5 141 682 +1967 1 22 6 4 DEBBY 44.5 39.1 141 215 +1983 8 11 18 7 LESLIE 48.6 203.4 15 166 +1964 5 1 18 13 NADINE 47.1 278.5 105 730 +1953 9 21 18 20 DEBBY 29.6 184.1 61 431 +1970 10 9 18 19 DEBBY 34.0 262.8 77 631 +2000 5 10 12 23 CHRIS 25.6 325.3 119 428 +1973 10 9 12 3 KIRK 47.0 259.3 125 159 +1954 9 28 12 6 CHRIS 46.8 63.3 121 242 +1986 4 11 0 20 JOYCE 46.0 147.7 116 333 +1974 1 14 12 18 SANDY 31.1 8.5 134 170 +1991 8 16 18 15 NADINE 39.9 9.9 41 248 +1996 12 6 6 9 ERNESTO 46.6 17.0 78 133 +1978 5 7 6 26 WILLIAM 37.8 280.6 152 178 +1977 9 12 6 5 FLORENCE 57.3 33.0 85 345 +1965 10 3 0 6 MICHAEL 58.8 265.0 105 431 +1979 6 9 0 28 OSCAR 34.8 210.9 90 756 +1997 11 18 18 18 RAFAEL 23.9 275.8 50 650 +1963 7 12 18 22 WILLIAM 41.9 141.3 52 475 +1969 12 7 12 22 SANDY 24.7 205.0 26 274 +1984 9 15 6 20 ERNESTO 20.8 183.3 140 30 +1961 11 5 0 2 VALERIE 59.6 185.7 81 42 +1951 2 15 6 10 GORDON 34.3 147.5 104 808 +1951 10 21 12 4 GORDON 25.6 316.3 133 816 +1984 12 17 18 9 JOYCE 26.3 35.9 85 436 +1957 7 18 12 25 PATTY 9.4 336.8 18 576 +1955 8 17 6 21 ALBERTO 52.3 53.5 156 607 +1975 11 13 18 14 NADINE 55.0 304.0 133 169 +1991 3 23 6 10 FLORENCE 42.2 339.0 11 632 +1981 4 27 0 25 KIRK 12.4 309.3 157 482 +1984 9 13 0 2 CHRIS 68.6 139.9 29 154 +1990 6 23 6 24 HELENE 10.4 205.1 140 419 +1976 6 17 6 10 WILLIAM 62.4 178.8 47 261 +1954 8 21 0 19 FLORENCE 44.0 103.6 152 712 +1961 2 22 0 14 SANDY 30.7 53.1 114 840 +1971 2 22 0 10 ALBERTO 59.7 188.7 52 60 +2001 8 8 18 6 FLORENCE 37.8 355.3 147 18 +1996 12 4 6 16 ALBERTO 14.9 307.4 129 756 +1950 5 25 0 27 ERNESTO 60.6 12.6 93 641 +1958 7 16 6 27 SANDY 20.2 207.1 71 112 +1967 5 28 18 5 HELENE 67.3 229.5 133 585 +1972 9 17 0 25 FLORENCE 29.9 49.6 131 243 +1963 6 5 0 13 DEBBY 53.6 85.8 123 23 +1984 4 19 12 20 GORDON 32.8 259.1 128 589 +1990 1 19 18 13 SANDY 27.7 10.2 82 428 +1987 2 14 12 26 PATTY 37.4 256.3 26 787 +1965 2 19 6 10 BERYL 66.5 163.7 75 450 +1952 7 2 6 10 ERNESTO 57.2 52.1 164 336 +1996 12 17 0 8 DEBBY 53.6 46.7 122 797 +1970 9 18 6 26 FLORENCE 56.5 248.7 17 303 +1957 5 24 0 11 LESLIE 58.8 109.6 131 52 +1988 10 16 0 24 TONY 38.2 216.8 15 397 +2000 8 12 6 20 OSCAR 62.5 305.6 55 336 +1972 3 7 12 16 ISAAC 63.9 353.0 134 733 +2000 11 9 18 26 ALBERTO 13.6 57.7 98 826 +1973 6 13 12 14 SANDY 61.7 28.9 13 348 +1957 1 12 12 23 SANDY 11.5 33.8 43 570 +1964 9 27 12 20 ALBERTO 68.6 123.0 66 670 +1979 6 14 18 15 HELENE 52.9 151.1 44 41 +1975 4 6 18 3 KIRK 68.5 207.8 112 828 +1958 9 10 6 5 GORDON 69.5 71.8 12 631 +1968 2 7 18 16 KIRK 42.2 254.0 37 632 +1971 4 27 18 24 HELENE 46.6 123.2 154 70 +1974 5 14 12 2 WILLIAM 44.4 240.5 91 443 +2000 5 6 0 26 PATTY 51.0 25.7 100 44 +1994 8 13 12 13 CHRIS 41.3 206.3 133 789 +1993 11 23 0 27 TONY 56.9 76.5 149 600 +1968 7 25 18 10 ALBERTO 10.6 347.4 30 471 +1990 8 6 6 25 FLORENCE 46.5 341.5 31 753 +1989 5 18 12 17 ALBERTO 20.9 26.5 154 793 +1994 7 16 0 15 LESLIE 69.0 206.7 158 622 +1989 11 8 6 12 HELENE 24.9 127.7 111 596 +1960 4 4 12 18 NADINE 45.7 0.4 141 182 +1990 4 2 18 9 RAFAEL 48.1 346.1 96 791 +1974 10 15 0 21 CHRIS 42.2 8.9 66 387 +1984 2 23 0 9 DEBBY 41.8 132.3 81 896 +1959 8 3 12 9 BERYL 19.1 120.7 121 522 +1993 9 2 12 12 JOYCE 56.4 277.0 87 679 +1992 4 17 0 5 HELENE 63.1 120.3 37 600 +1984 2 10 6 10 VALERIE 9.0 26.3 85 877 +1989 5 22 12 13 MICHAEL 66.0 205.6 86 789 +1970 2 16 18 21 BERYL 33.8 161.5 11 502 +1961 10 24 0 15 ALBERTO 60.2 121.0 87 123 +1992 1 8 18 6 KIRK 26.7 116.1 142 818 +1964 5 10 0 14 BERYL 47.8 115.9 26 241 +1976 3 7 0 2 ALBERTO 19.6 161.0 46 895 +1951 11 12 6 15 RAFAEL 28.2 287.8 127 368 +1987 6 21 12 5 GORDON 62.1 132.3 59 375 +1998 1 7 6 27 SANDY 62.5 351.6 93 89 +1982 6 24 18 11 DEBBY 41.3 245.3 123 531 +1957 8 17 6 11 GORDON 43.3 307.5 114 380 +1975 5 14 18 17 WILLIAM 47.4 239.6 19 399 +1997 7 1 6 18 SANDY 66.4 173.2 62 801 +1951 12 4 0 12 RAFAEL 15.0 121.2 78 895 +1983 3 23 18 19 MICHAEL 67.0 97.7 106 188 +1957 12 18 18 17 NADINE 31.6 1.6 77 442 +1980 9 6 12 11 FLORENCE 63.2 290.9 76 468 +1954 8 14 18 27 OSCAR 57.6 297.0 38 578 +1986 2 27 6 18 PATTY 59.3 294.5 61 253 +1988 4 2 12 24 ALBERTO 14.6 262.3 21 515 +1969 12 6 6 5 JOYCE 7.9 119.1 24 345 +1987 7 6 12 12 VALERIE 61.9 1.6 42 886 +1991 6 27 12 10 GORDON 63.6 160.0 137 840 +1970 2 27 0 23 NADINE 33.7 48.0 144 183 +1955 4 12 12 4 ISAAC 8.0 33.3 163 729 +1987 6 14 18 13 RAFAEL 64.2 206.8 106 54 +1950 2 13 0 13 NADINE 22.0 189.9 42 183 +1989 2 21 0 24 OSCAR 48.3 170.4 66 198 +1995 7 19 12 14 SANDY 50.4 275.0 17 68 +1988 5 8 6 20 HELENE 45.7 236.2 102 724 +1985 3 4 18 6 SANDY 57.0 56.5 49 773 +1974 7 27 18 12 HELENE 35.6 33.1 28 491 +1957 6 28 12 3 PATTY 47.8 177.1 147 688 +1994 12 5 18 27 VALERIE 10.6 189.5 131 442 +1960 4 28 0 3 LESLIE 17.9 312.6 38 128 +1976 2 20 12 27 PATTY 52.3 18.5 125 366 +1999 1 8 0 15 VALERIE 14.8 271.6 109 145 +1964 8 18 0 7 DEBBY 38.0 154.6 55 847 +1955 4 17 0 19 KIRK 46.5 205.7 53 648 +1977 10 20 0 4 MICHAEL 38.9 77.1 158 729 +1975 6 28 12 17 DEBBY 25.4 243.4 136 118 +1996 11 14 0 21 TONY 32.2 349.8 38 36 +2002 1 26 12 23 JOYCE 41.8 283.7 80 403 +1992 9 20 18 19 LESLIE 45.6 172.1 143 526 +1954 7 17 18 23 ISAAC 23.0 191.3 57 837 +1970 5 27 18 13 CHRIS 15.8 163.5 132 84 +1986 8 22 0 6 VALERIE 51.3 76.6 120 288 +1981 8 7 6 5 CHRIS 61.0 101.9 65 103 +1998 4 24 18 14 TONY 64.5 27.2 99 6 +1980 7 11 12 10 BERYL 7.8 316.3 112 0 +1982 7 2 18 8 ALBERTO 57.3 114.6 29 741 +1950 3 2 0 8 WILLIAM 16.1 325.0 90 559 +1951 8 7 12 1 ISAAC 41.5 237.7 143 736 +1960 12 25 0 26 ISAAC 31.7 318.8 62 417 +1957 9 5 12 18 LESLIE 33.9 19.3 130 353 +1960 4 3 18 20 TONY 25.9 273.8 42 666 +1963 11 3 12 14 HELENE 27.2 137.9 81 592 +1998 5 28 18 9 GORDON 31.0 152.6 80 495 +1961 6 23 6 6 TONY 12.1 172.9 152 273 +1989 9 3 6 25 BERYL 20.3 354.6 80 368 +1985 7 12 6 17 ERNESTO 16.8 348.1 95 132 +1973 3 2 12 5 CHRIS 43.9 143.2 108 414 +1972 5 5 12 2 ALBERTO 43.3 94.0 98 372 +1999 9 6 6 24 VALERIE 39.8 64.4 159 142 +1957 11 12 12 21 ERNESTO 27.8 210.5 53 815 +1971 4 10 12 14 FLORENCE 22.3 51.0 49 621 +2001 12 7 12 11 TONY 67.2 12.3 123 612 +1979 6 7 0 18 BERYL 39.0 54.5 18 523 +1977 6 13 0 27 JOYCE 11.6 227.9 162 660 +1962 2 24 6 22 KIRK 59.1 255.1 48 550 +1977 11 3 0 4 RAFAEL 59.4 4.0 116 556 +1970 11 8 18 15 VALERIE 42.3 153.7 148 871 +1951 4 23 18 19 FLORENCE 19.0 68.3 42 239 +1956 5 5 18 16 FLORENCE 62.1 270.5 164 426 +1956 8 15 0 22 PATTY 18.2 235.9 160 857 +1968 4 15 0 28 OSCAR 64.2 280.5 94 818 +1963 1 20 12 28 SANDY 48.8 68.4 123 339 +1971 3 19 12 9 NADINE 20.5 213.9 95 811 +1968 5 20 12 6 GORDON 35.4 345.0 27 534 +2004 10 17 0 21 OSCAR 8.8 321.6 86 305 +1970 10 2 6 3 GORDON 28.6 6.4 88 243 +1994 10 3 12 18 GORDON 28.3 314.5 89 277 +1997 8 25 6 10 RAFAEL 42.7 219.3 106 337 +1979 4 25 18 8 OSCAR 61.9 42.2 116 171 +1954 2 28 18 4 VALERIE 57.0 198.3 121 75 +2000 8 7 12 12 TONY 46.5 7.1 127 608 +1969 2 27 18 18 ALBERTO 39.1 204.2 81 227 +1977 9 15 18 2 LESLIE 39.3 303.6 33 706 +1974 2 27 18 2 ALBERTO 23.1 198.8 133 343 +1961 4 28 18 17 ERNESTO 63.0 148.5 13 863 +1984 7 4 18 8 PATTY 18.6 215.1 141 292 +1956 8 10 12 17 WILLIAM 67.0 15.7 164 185 +1980 2 3 6 11 DEBBY 45.2 265.7 40 640 +2001 1 14 6 16 ISAAC 43.6 318.6 65 536 +1984 1 20 6 5 OSCAR 33.2 187.0 75 422 +1956 3 14 6 19 DEBBY 37.3 240.7 10 847 +2000 7 8 18 26 LESLIE 11.6 208.8 56 586 +1979 3 23 6 28 DEBBY 43.6 187.2 28 871 +2000 6 1 6 8 NADINE 18.3 172.6 74 337 +1976 1 19 0 8 CHRIS 28.2 251.2 60 3 +1992 9 3 0 6 ERNESTO 7.2 274.2 72 880 +1953 9 15 6 9 KIRK 13.9 30.4 79 775 +1997 9 16 12 26 GORDON 46.1 317.9 127 202 +2003 6 14 18 2 BERYL 46.2 16.9 159 140 +1959 7 23 12 28 FLORENCE 48.6 345.3 123 586 +2000 2 15 12 5 BERYL 24.8 156.2 128 665 +1975 10 13 18 11 PATTY 59.2 184.4 75 618 +1992 4 25 18 21 WILLIAM 36.8 163.2 116 221 +1953 2 13 0 28 JOYCE 36.4 11.9 155 302 +1983 1 11 0 7 RAFAEL 36.8 187.3 150 256 +1992 3 23 18 23 WILLIAM 55.9 86.7 44 675 +1977 4 26 18 9 NADINE 52.0 11.2 51 297 +1951 5 19 12 7 CHRIS 47.9 9.8 41 235 +2002 8 13 18 13 ISAAC 46.6 121.0 126 381 +1950 9 24 6 8 VALERIE 8.1 149.8 12 823 +1962 12 28 6 24 CHRIS 57.0 242.3 45 198 +1971 9 11 0 9 DEBBY 19.1 319.6 111 520 +1970 12 11 0 9 DEBBY 60.6 74.8 23 25 +1961 4 21 18 17 TONY 12.5 285.8 74 109 +2002 5 25 18 18 OSCAR 35.5 301.4 98 691 +1994 12 5 18 11 OSCAR 61.2 50.1 30 138 +1979 6 2 0 27 RAFAEL 7.4 232.7 116 474 +1998 4 27 0 11 RAFAEL 20.8 76.0 156 636 +1983 5 17 6 14 NADINE 45.8 83.3 94 67 +1997 6 8 6 11 GORDON 50.4 332.4 68 384 +1999 5 20 0 18 OSCAR 53.0 186.8 138 663 +1992 6 4 6 3 CHRIS 49.9 125.9 113 326 +1974 11 3 18 24 NADINE 69.8 215.4 36 860 +1974 12 5 0 1 OSCAR 34.4 48.9 87 526 +1978 10 17 0 25 VALERIE 51.8 306.2 66 82 +2002 5 25 12 8 ISAAC 55.6 333.9 93 867 +1960 5 24 6 12 HELENE 54.1 75.7 33 657 +1983 4 7 12 28 GORDON 63.2 206.3 89 11 +1966 7 17 18 26 TONY 7.3 240.7 84 225 +1999 7 2 12 22 CHRIS 41.3 310.1 82 556 +1983 4 7 6 16 BERYL 52.2 41.9 93 254 +1971 9 1 0 14 CHRIS 52.9 15.9 105 367 +1991 4 1 0 22 HELENE 49.1 136.6 163 385 +1990 4 10 18 17 PATTY 7.7 257.0 62 173 +1962 10 13 18 28 JOYCE 46.4 254.9 95 161 +1963 5 16 18 8 SANDY 26.3 299.1 21 490 +1980 4 26 6 14 WILLIAM 51.6 49.6 27 797 +1991 6 9 18 17 ALBERTO 27.5 119.3 122 784 +1973 11 23 18 21 RAFAEL 52.4 356.1 102 387 +1963 11 16 0 22 SANDY 23.5 277.1 16 647 +1965 1 22 18 13 KIRK 8.6 276.5 60 724 +1952 10 26 12 28 JOYCE 51.7 204.9 19 727 +1988 12 9 12 9 NADINE 63.1 87.0 96 4 +1984 6 19 6 23 JOYCE 67.9 223.0 13 551 +1972 8 6 6 5 PATTY 28.8 168.5 93 231 +1951 9 26 6 24 LESLIE 32.3 34.7 128 50 +1967 7 14 12 13 PATTY 14.1 22.7 88 823 +1984 3 7 6 12 SANDY 24.2 272.8 99 315 +1975 8 28 6 12 SANDY 31.9 302.7 19 659 +2000 11 7 12 23 ERNESTO 39.5 71.9 95 852 +1959 12 21 6 22 BERYL 9.3 313.0 16 573 +1996 3 4 18 12 VALERIE 10.8 266.0 30 420 +1978 4 2 6 16 RAFAEL 45.3 162.2 89 395 +1979 6 26 12 10 RAFAEL 66.6 311.5 156 222 +1976 12 7 18 8 ISAAC 61.7 125.6 87 399 +1988 8 4 12 10 DEBBY 12.7 101.3 59 551 +1964 4 2 18 2 MICHAEL 34.3 289.1 125 260 +1954 10 17 18 23 ERNESTO 32.0 294.3 72 421 +1970 11 28 12 7 OSCAR 48.5 308.6 74 571 +1980 3 27 6 7 DEBBY 38.3 53.5 122 475 +2000 3 10 18 24 KIRK 37.6 276.5 91 318 +1989 1 13 12 20 PATTY 48.7 176.1 45 894 +1966 12 24 6 2 DEBBY 34.3 298.9 42 610 +1984 12 3 0 28 TONY 17.6 58.2 50 601 +1980 7 5 6 27 BERYL 27.8 260.2 70 805 +2003 12 14 6 26 SANDY 46.9 52.6 125 655 +1994 5 27 6 25 ERNESTO 18.6 48.3 93 724 +1972 10 22 0 4 MICHAEL 34.1 101.7 35 532 +1991 3 22 0 16 RAFAEL 55.6 313.0 139 883 +1986 10 5 18 17 TONY 56.8 211.4 54 246 +1988 7 5 0 27 TONY 27.7 30.0 155 461 +1996 2 24 12 12 PATTY 54.3 74.6 11 336 +1998 9 17 12 26 OSCAR 16.1 209.3 136 517 +1975 11 8 12 28 OSCAR 61.7 63.8 126 838 +1974 7 20 12 9 DEBBY 45.2 256.7 101 709 +1979 8 12 0 21 CHRIS 47.7 97.6 56 210 +1971 8 21 6 27 WILLIAM 56.9 190.1 60 400 +1986 11 8 18 10 MICHAEL 34.5 96.9 141 665 +1960 8 19 18 9 DEBBY 46.3 272.2 65 76 +1967 5 18 18 9 ISAAC 29.2 284.3 112 415 +1984 12 22 6 4 PATTY 26.1 31.4 36 767 +2003 9 19 6 15 LESLIE 37.3 106.0 136 595 +2003 10 12 0 5 NADINE 48.6 275.7 37 80 +1990 4 9 0 5 HELENE 61.1 45.0 163 198 +1966 10 5 0 9 BERYL 36.4 104.4 70 878 +2004 12 28 12 1 NADINE 53.6 110.1 143 660 +1988 10 12 6 24 NADINE 12.4 68.8 98 200 +2001 5 28 18 12 PATTY 37.2 343.9 104 461 +1990 11 24 6 10 LESLIE 40.0 223.9 52 496 +1974 9 25 0 4 JOYCE 46.6 337.5 23 305 +1976 11 18 12 16 VALERIE 7.5 262.8 136 587 +2001 4 27 6 21 KIRK 49.0 131.2 69 522 +1987 9 8 0 28 VALERIE 27.6 289.2 129 304 +1981 12 9 12 7 DEBBY 63.0 22.4 156 278 +1970 5 22 12 11 FLORENCE 19.5 65.9 37 212 +1957 12 10 18 27 JOYCE 12.1 244.6 33 579 +1971 6 14 0 6 JOYCE 14.6 120.3 110 783 +2000 8 9 12 15 NADINE 23.1 21.0 108 868 +2000 5 7 6 13 MICHAEL 18.0 334.9 83 237 +1998 6 15 12 18 FLORENCE 36.8 193.0 78 662 +1995 12 20 12 24 GORDON 69.0 124.0 52 315 +1959 7 3 18 28 TONY 36.5 264.1 88 420 +1989 1 7 18 26 MICHAEL 61.8 250.3 154 249 +1980 11 10 18 12 CHRIS 26.8 28.5 55 108 +1991 4 26 0 27 OSCAR 36.6 268.8 119 621 +1953 10 12 18 2 WILLIAM 17.0 56.8 41 259 +1995 3 7 0 24 JOYCE 11.5 143.4 33 17 +1981 9 7 6 12 ERNESTO 51.0 208.7 120 418 +1981 1 28 6 3 CHRIS 59.6 249.9 62 896 +1977 12 2 6 9 SANDY 29.6 54.6 13 825 +1996 11 10 0 17 GORDON 37.4 314.6 58 564 +1971 11 15 12 2 ERNESTO 53.7 59.4 94 556 +1984 4 27 18 21 ISAAC 65.9 258.5 89 208 +1983 8 14 6 10 MICHAEL 13.7 326.2 61 107 +1991 7 23 18 2 JOYCE 61.1 339.5 158 819 +1970 6 9 12 12 DEBBY 12.7 354.9 10 293 +1992 9 8 12 12 OSCAR 66.4 336.8 57 778 +1985 9 5 12 14 ERNESTO 57.4 287.8 102 406 +1997 2 5 18 15 FLORENCE 31.9 250.0 13 46 +1979 2 10 12 17 JOYCE 33.8 267.1 15 8 +1984 8 13 12 5 MICHAEL 61.0 50.0 146 442 +1975 11 9 0 15 MICHAEL 34.8 229.1 156 698 +1991 4 26 6 13 JOYCE 13.8 130.6 19 306 +1962 7 22 12 5 RAFAEL 24.6 100.9 157 428 +1998 1 21 18 5 TONY 30.6 187.9 139 469 +1964 3 25 18 2 CHRIS 23.9 156.5 104 456 +1969 6 26 6 19 WILLIAM 8.0 5.9 140 372 +1964 4 28 6 7 SANDY 69.6 248.6 10 663 +1990 6 26 6 21 CHRIS 31.2 109.2 40 885 +1977 6 9 12 11 PATTY 7.8 144.7 18 808 +1992 2 25 12 9 VALERIE 24.5 128.2 156 544 +1978 2 21 0 13 PATTY 54.6 200.4 52 48 +1990 4 27 18 1 ERNESTO 15.0 257.1 84 811 +1999 5 10 12 4 ERNESTO 55.5 73.2 62 249 +1974 10 21 6 16 RAFAEL 23.3 178.7 60 620 +1980 11 26 6 18 VALERIE 17.5 188.5 63 760 +1961 6 9 12 9 RAFAEL 16.1 92.9 121 521 +1955 8 10 12 25 DEBBY 14.2 21.8 163 243 +1953 12 4 0 14 HELENE 36.9 155.3 17 159 +1978 2 24 0 10 ALBERTO 60.6 98.6 89 784 +2001 6 19 0 2 MICHAEL 37.5 95.9 24 526 +1995 7 17 12 12 KIRK 13.3 232.7 62 56 +2002 8 20 18 27 TONY 62.4 308.3 19 607 +1983 1 21 0 23 SANDY 29.7 110.5 109 523 +1994 3 9 18 28 DEBBY 47.0 23.6 104 583 +1958 1 9 12 23 GORDON 26.1 142.0 141 143 +1966 6 14 0 17 VALERIE 47.6 187.3 160 818 +1953 11 25 12 14 WILLIAM 67.2 344.3 123 896 +1956 2 27 6 13 ERNESTO 66.0 282.5 25 510 +1975 5 3 6 1 JOYCE 52.9 36.9 74 161 +1977 5 19 0 11 TONY 39.1 259.3 156 295 +1960 12 5 12 26 BERYL 64.0 335.4 116 497 +2001 10 27 6 22 ALBERTO 55.0 76.0 67 436 +1965 5 23 12 24 VALERIE 10.9 49.7 21 178 +1962 10 26 0 16 ERNESTO 12.9 33.3 95 497 +1953 12 13 0 5 TONY 40.5 295.0 29 695 +1953 9 7 6 27 ALBERTO 23.8 212.4 57 551 +1992 8 12 18 25 CHRIS 46.4 302.5 84 120 +1980 7 1 0 2 ISAAC 38.0 260.9 81 544 +1993 4 14 0 25 ERNESTO 17.4 336.1 40 434 +1979 7 1 0 16 FLORENCE 60.3 74.7 158 414 +1976 4 5 0 14 LESLIE 29.4 96.2 124 850 +1977 7 27 12 2 LESLIE 42.7 165.1 35 406 +1997 7 6 12 27 HELENE 57.4 131.4 47 438 +1967 3 20 12 8 VALERIE 51.1 167.1 123 557 +1997 6 11 12 14 JOYCE 33.7 146.2 51 736 +1981 7 26 0 24 HELENE 31.4 59.2 44 804 +1958 11 5 18 18 DEBBY 48.9 137.4 135 876 +1969 9 9 0 23 OSCAR 31.4 162.0 124 819 +1992 9 23 12 15 DEBBY 36.5 298.7 17 140 +1982 2 22 18 16 OSCAR 36.8 330.6 14 702 +1981 4 1 12 15 LESLIE 58.4 140.1 135 665 +1998 10 8 18 5 ALBERTO 42.2 97.4 69 596 +1997 9 15 6 21 BERYL 47.4 52.7 156 678 +1994 11 15 0 8 JOYCE 55.7 307.8 143 21 +1957 2 10 6 14 JOYCE 13.7 11.7 60 133 +1978 7 20 6 15 CHRIS 43.7 102.5 162 513 +1973 5 2 18 21 JOYCE 40.9 3.2 131 22 +1970 12 21 0 8 RAFAEL 18.3 122.9 33 124 +1987 10 24 0 16 NADINE 60.8 33.5 100 220 +2004 5 1 18 23 DEBBY 14.3 7.6 62 456 +1973 12 13 18 22 ERNESTO 62.3 187.3 156 258 +1973 9 13 6 3 HELENE 28.9 211.3 79 711 +1998 2 5 6 24 ERNESTO 51.3 137.6 142 446 +1962 8 1 6 15 CHRIS 29.7 207.4 161 493 +1984 4 7 6 18 TONY 30.6 20.4 110 237 +1972 4 3 18 1 VALERIE 11.3 159.4 34 164 +1964 5 9 18 17 HELENE 36.5 270.3 46 27 +1990 4 18 18 20 MICHAEL 31.8 303.2 81 735 +2001 10 3 12 24 OSCAR 34.4 187.1 119 560 +1950 9 2 18 4 ISAAC 36.8 96.7 16 506 +1982 12 28 12 22 JOYCE 10.7 319.2 59 388 +1983 7 9 12 21 ALBERTO 27.4 141.1 109 766 +1956 8 26 6 27 KIRK 37.0 43.7 91 68 +1973 2 3 0 2 TONY 63.8 60.4 153 773 +1961 6 7 18 21 DEBBY 22.9 92.4 120 740 +1996 5 27 6 8 HELENE 19.2 254.6 83 463 +1976 1 16 18 26 KIRK 50.0 231.0 153 355 +2001 10 16 0 20 WILLIAM 19.8 106.7 138 12 +1993 2 11 12 7 BERYL 69.9 73.5 84 830 +1954 10 8 12 9 WILLIAM 19.1 236.6 72 744 +1988 11 11 6 2 ALBERTO 19.3 53.8 46 789 +1983 2 11 18 12 MICHAEL 42.8 245.6 29 811 +1982 12 10 6 17 FLORENCE 22.5 44.4 144 771 +1955 5 25 18 13 JOYCE 62.2 129.9 25 408 +1993 11 19 0 16 JOYCE 50.7 142.0 153 266 +1961 6 16 18 25 ISAAC 68.4 70.9 53 858 +1961 6 24 12 8 WILLIAM 29.9 78.6 92 349 +2001 2 17 18 15 ISAAC 8.8 228.6 102 735 +1950 5 25 6 11 PATTY 58.8 89.4 131 741 +1986 6 26 0 19 RAFAEL 28.0 3.1 58 114 +1986 12 2 6 1 BERYL 62.8 304.8 61 683 +1955 12 4 12 18 WILLIAM 55.9 218.2 56 268 +1990 7 16 18 13 MICHAEL 49.8 115.3 160 403 +1952 2 3 18 6 GORDON 16.9 311.6 19 683 +1998 1 4 6 2 GORDON 67.8 101.9 80 469 +1959 2 5 0 24 MICHAEL 54.8 128.3 84 871 +1955 12 11 12 13 GORDON 18.8 27.4 116 721 +1988 2 15 6 14 BERYL 46.4 293.4 127 574 +1958 12 25 12 18 ISAAC 38.4 276.4 30 408 +2002 11 4 12 8 BERYL 49.6 5.1 117 125 +1997 12 12 12 8 GORDON 42.4 345.1 140 75 +1953 9 6 18 5 LESLIE 49.9 203.7 132 728 +2001 10 8 6 7 VALERIE 15.8 299.4 160 434 +2004 2 14 6 4 MICHAEL 69.8 71.8 21 27 +1990 6 27 6 1 BERYL 35.0 5.2 135 407 +1998 10 6 18 11 JOYCE 18.8 303.9 160 882 +1997 5 25 6 15 DEBBY 18.5 301.3 87 360 +1998 3 3 0 27 ERNESTO 26.7 182.2 62 668 +2004 11 16 18 18 WILLIAM 46.5 243.7 29 738 +2002 6 14 18 10 FLORENCE 64.9 21.3 33 866 +1952 10 17 0 11 FLORENCE 58.8 200.8 149 445 +1987 7 21 12 9 JOYCE 48.5 42.4 144 111 +2004 12 1 12 22 OSCAR 65.4 164.2 103 792 +1994 10 7 18 6 RAFAEL 67.1 14.4 118 574 +1967 8 16 6 25 MICHAEL 41.6 250.6 76 495 +1999 7 4 18 16 VALERIE 63.4 228.1 69 337 +2002 12 14 0 17 BERYL 59.0 288.8 136 723 +1961 9 11 18 10 WILLIAM 56.5 123.5 138 318 +2003 7 10 0 17 ISAAC 65.1 82.8 21 182 +1971 10 2 0 15 WILLIAM 56.5 350.4 48 507 +1961 1 2 6 11 NADINE 32.5 215.4 112 586 +1951 9 25 12 24 HELENE 56.6 174.9 42 502 +1973 2 26 6 28 DEBBY 7.6 2.7 35 654 +1961 12 21 18 17 NADINE 45.0 40.6 67 367 +1958 3 25 0 5 PATTY 13.9 154.1 164 537 +1960 11 28 0 17 HELENE 12.6 63.8 74 197 +1979 10 2 12 24 ALBERTO 60.1 49.4 146 622 +1985 4 15 6 16 BERYL 67.0 175.2 150 5 +1956 6 20 0 5 WILLIAM 8.5 137.8 48 876 +2004 6 4 18 11 ERNESTO 17.6 124.8 69 382 +1998 1 2 0 6 MICHAEL 23.5 102.2 139 690 +1955 12 13 6 26 GORDON 28.2 347.4 96 763 +1979 12 21 12 11 JOYCE 45.2 267.5 34 531 +2004 11 13 6 11 MICHAEL 34.0 0.2 69 250 +1994 1 14 12 10 MICHAEL 34.0 242.7 149 32 +1961 9 21 6 23 CHRIS 16.9 291.2 19 677 +1963 3 21 12 28 GORDON 38.1 338.1 11 521 +1961 1 19 12 7 ALBERTO 65.9 175.8 53 747 +1980 8 1 12 20 RAFAEL 48.9 39.1 117 672 +1968 3 25 18 12 ISAAC 54.7 313.7 63 658 +1989 4 13 6 11 SANDY 33.1 78.3 88 273 +1950 1 10 12 5 CHRIS 10.2 108.0 75 846 +1999 4 22 6 19 ALBERTO 68.3 344.2 10 752 +1991 5 27 0 3 ALBERTO 66.4 108.8 140 154 +1951 12 22 6 15 KIRK 45.9 90.3 133 346 +1977 10 25 12 5 BERYL 60.4 222.3 114 466 +1991 6 25 6 21 RAFAEL 44.2 126.3 90 686 +1955 1 19 6 2 KIRK 42.9 244.3 137 429 +2003 7 21 12 16 NADINE 55.9 54.3 49 276 +1957 3 4 12 4 BERYL 31.4 16.1 99 605 +1963 1 3 12 12 ERNESTO 52.1 262.8 32 263 +1960 9 15 18 26 RAFAEL 10.7 214.9 117 171 +1989 10 12 18 20 ALBERTO 12.8 124.4 141 523 +1952 11 13 18 10 RAFAEL 59.5 275.4 90 650 +1968 11 15 12 26 TONY 38.4 81.1 46 176 +1970 8 2 0 14 MICHAEL 14.2 4.3 134 395 +1975 12 24 6 9 LESLIE 14.4 9.7 87 460 +1955 3 17 12 12 ALBERTO 23.9 2.6 130 831 +1955 8 1 18 8 CHRIS 20.8 263.6 106 147 +1986 6 6 18 12 ALBERTO 62.3 83.8 85 732 +1998 7 20 12 4 PATTY 21.7 123.2 138 146 +1957 11 11 0 21 MICHAEL 15.9 93.4 148 657 +1962 11 15 0 11 ISAAC 51.6 246.4 156 383 +1990 6 24 12 4 BERYL 23.9 11.2 10 37 +1998 5 22 6 18 ERNESTO 8.3 117.1 29 729 +1960 3 28 6 23 ISAAC 32.3 271.5 66 308 +1983 10 25 18 21 SANDY 40.7 234.9 15 151 +1984 8 25 6 20 DEBBY 52.7 312.7 56 522 +1994 3 4 18 19 GORDON 27.8 312.8 31 529 +1968 8 2 18 14 GORDON 68.2 345.2 164 8 +1957 5 5 6 16 WILLIAM 10.6 247.6 22 839 +1952 12 12 12 7 NADINE 55.5 75.7 141 299 +1967 10 4 18 5 RAFAEL 11.3 173.6 87 692 +1963 2 2 18 12 BERYL 58.4 16.9 66 306 +1970 4 7 6 1 LESLIE 23.4 199.9 54 253 +1985 6 7 0 6 DEBBY 29.8 329.8 65 205 +1982 11 15 12 12 TONY 56.0 300.5 163 526 +1963 1 25 6 24 CHRIS 21.2 266.8 53 757 +1980 4 22 18 22 MICHAEL 63.4 295.7 121 566 +1971 4 18 18 7 HELENE 61.1 107.8 87 96 +1987 10 4 0 7 ISAAC 41.5 269.3 69 386 +1952 7 11 18 10 FLORENCE 41.8 135.4 74 177 +2000 11 15 12 24 ISAAC 69.2 172.9 76 140 +2003 6 28 6 17 ISAAC 62.9 348.3 57 537 +1980 9 20 0 20 MICHAEL 54.7 64.8 24 474 +1985 5 10 18 15 OSCAR 11.5 67.0 107 382 +1996 7 27 6 24 DEBBY 12.8 37.9 89 89 +1972 12 10 6 28 OSCAR 32.7 173.7 140 201 +1967 3 24 18 9 LESLIE 36.9 59.3 123 87 +1957 9 5 12 27 CHRIS 66.6 250.5 87 271 +1966 6 4 12 22 NADINE 17.6 330.3 82 57 +1958 5 11 0 16 PATTY 17.3 334.6 124 147 +1950 2 13 6 18 LESLIE 13.8 38.0 142 28 +1973 11 16 18 14 TONY 41.8 40.5 53 85 +1971 6 22 12 13 NADINE 14.4 238.4 153 289 +1994 3 22 12 27 KIRK 25.3 82.6 155 264 +1991 8 27 12 10 ERNESTO 39.1 43.8 64 825 +1976 4 6 6 6 FLORENCE 24.9 311.7 76 363 +1953 3 4 18 21 OSCAR 23.5 58.2 126 368 +1994 4 24 12 2 PATTY 29.7 267.6 61 642 +1982 7 19 0 16 ISAAC 54.7 245.3 143 552 +1976 2 22 0 11 NADINE 15.4 44.9 142 621 +1969 1 16 12 2 NADINE 48.7 97.5 89 416 +1989 9 16 0 8 FLORENCE 48.3 291.6 90 518 +1960 3 14 6 11 RAFAEL 62.7 172.0 29 480 +1981 4 14 6 15 SANDY 33.8 30.9 159 162 +1968 3 8 12 4 TONY 65.1 254.8 11 674 +1987 2 27 0 27 LESLIE 42.3 56.7 120 466 +1957 5 13 12 10 ISAAC 18.3 199.0 115 717 +1965 10 3 6 4 CHRIS 56.0 193.5 43 312 +1958 9 15 18 6 HELENE 7.5 306.0 104 831 +1976 12 24 12 11 DEBBY 61.3 146.4 111 45 +1989 9 25 18 23 JOYCE 61.2 12.6 10 669 +1966 10 23 12 19 MICHAEL 19.3 122.9 18 703 +1997 9 15 18 26 NADINE 57.6 263.5 41 477 +1975 5 19 0 27 VALERIE 29.8 109.4 31 49 +1958 10 9 12 10 CHRIS 7.3 93.1 22 698 +1990 2 14 12 19 MICHAEL 12.1 301.3 157 633 +1981 10 15 12 10 PATTY 22.5 171.6 139 896 +1979 4 4 18 8 FLORENCE 13.5 274.3 39 272 +1977 8 11 0 25 WILLIAM 34.2 14.2 93 28 +1997 10 16 0 26 HELENE 35.9 121.0 98 712 +1967 12 16 12 26 PATTY 47.8 21.0 130 487 +1987 12 28 6 28 VALERIE 45.9 105.1 155 510 +1983 7 22 18 23 ISAAC 31.6 285.6 95 471 +2003 4 26 6 25 OSCAR 67.9 43.6 149 310 +1975 2 28 6 6 NADINE 27.2 356.4 62 808 +1973 3 11 6 5 BERYL 17.6 335.1 66 491 +1953 5 3 6 4 CHRIS 57.8 231.3 141 333 +1984 10 9 0 7 JOYCE 51.2 20.0 22 209 +1967 7 21 6 1 DEBBY 19.2 231.4 113 7 +1950 11 7 6 21 FLORENCE 67.5 312.6 153 102 +1991 1 1 18 28 MICHAEL 16.3 65.0 150 169 +1970 1 23 18 24 PATTY 68.8 221.1 46 235 +1972 6 23 6 25 ISAAC 7.0 198.5 53 509 +1961 11 19 18 7 MICHAEL 49.6 267.8 134 421 +1964 5 15 12 10 TONY 16.7 131.6 23 363 +2001 11 19 0 23 ISAAC 40.8 109.3 26 176 +1978 12 19 18 2 ALBERTO 64.4 199.8 92 154 +1954 6 17 18 23 ERNESTO 58.7 258.7 11 20 +1967 11 5 6 23 WILLIAM 67.3 64.2 92 363 +2004 8 17 6 14 VALERIE 27.7 279.7 83 131 +1970 4 25 12 24 KIRK 57.6 193.2 53 330 +1974 11 3 18 7 SANDY 50.8 306.3 93 713 +1961 5 12 0 10 ERNESTO 35.5 342.8 15 530 +1967 2 22 0 16 ALBERTO 55.9 115.4 158 127 +1952 6 15 6 25 LESLIE 25.5 65.4 20 360 +1997 1 18 0 9 RAFAEL 29.6 81.2 66 644 +1950 1 17 18 1 ERNESTO 50.2 75.0 46 897 +2001 7 22 18 1 ALBERTO 60.6 249.5 151 165 +1999 9 3 18 8 SANDY 17.8 189.8 93 532 +1993 4 7 6 21 SANDY 36.1 72.9 51 620 +1975 4 27 6 18 HELENE 42.0 78.6 159 492 +1985 7 2 18 20 GORDON 20.9 273.2 79 749 +1954 3 6 18 23 SANDY 53.0 265.0 66 325 +1954 3 21 18 24 ERNESTO 57.3 27.4 92 640 +1988 7 28 18 24 WILLIAM 62.2 39.2 56 395 +1983 2 15 12 8 BERYL 12.5 77.0 16 467 +1993 4 3 12 13 JOYCE 68.2 253.6 17 538 +2004 7 10 12 17 MICHAEL 38.9 53.8 34 558 +1966 8 1 12 3 BERYL 15.8 116.5 38 368 +1984 1 7 0 19 WILLIAM 32.0 115.8 58 455 +1985 7 22 6 22 CHRIS 29.5 48.5 16 462 +1955 3 18 0 7 ERNESTO 62.6 80.1 84 242 +1996 11 21 12 2 ALBERTO 36.3 55.5 109 464 +1975 2 4 18 26 LESLIE 19.2 25.9 25 729 +1987 3 14 12 6 MICHAEL 40.0 126.2 76 728 +1988 10 28 6 4 DEBBY 27.2 39.8 37 38 +1996 1 21 0 8 ISAAC 20.3 239.0 69 766 +1965 1 28 12 18 GORDON 67.6 3.2 144 191 +1996 11 11 18 4 CHRIS 60.8 304.6 13 531 +1979 12 6 0 27 LESLIE 64.5 135.2 49 623 +1973 10 27 18 20 PATTY 30.2 131.1 21 420 +1970 3 25 6 13 WILLIAM 49.9 338.2 85 890 +1996 4 1 0 14 ERNESTO 45.5 39.2 32 828 +1983 4 6 12 8 KIRK 39.8 293.0 76 544 +1980 12 2 0 6 CHRIS 26.9 37.6 128 230 +1978 1 20 18 23 ALBERTO 39.4 19.5 111 18 +1997 8 8 12 22 LESLIE 54.1 10.5 46 317 +1973 2 22 18 13 NADINE 38.8 265.7 28 151 +1991 6 7 0 19 LESLIE 67.8 120.2 12 400 +1974 5 2 12 1 OSCAR 21.5 206.2 93 224 +1986 3 24 18 20 GORDON 68.5 232.2 147 216 +1968 11 9 18 25 DEBBY 44.7 9.4 83 615 +1992 5 21 6 22 PATTY 12.7 243.9 149 402 +1952 10 15 0 8 FLORENCE 66.8 316.6 22 656 +2001 12 12 12 17 BERYL 24.2 221.0 42 273 +1997 8 9 12 28 KIRK 29.9 114.6 83 803 +1963 10 4 0 7 GORDON 46.1 160.8 147 50 +1964 11 11 0 25 WILLIAM 11.4 237.1 66 86 +1961 2 28 12 24 TONY 15.6 136.5 68 400 +1983 9 27 12 5 LESLIE 47.5 75.6 155 357 +1976 8 9 6 2 ISAAC 13.3 352.2 37 529 +1993 3 9 12 28 ALBERTO 18.6 154.4 87 380 +1975 2 14 6 17 HELENE 35.2 253.5 48 310 +1974 1 18 6 24 FLORENCE 32.6 127.0 15 416 +1981 5 25 6 18 VALERIE 37.3 143.9 87 175 +1996 1 10 12 19 RAFAEL 8.6 101.4 156 137 +1990 9 25 6 19 NADINE 52.5 244.5 67 603 +1966 8 9 12 3 ERNESTO 29.5 52.6 153 56 +1998 2 14 12 24 DEBBY 31.4 231.4 60 193 +1951 4 21 18 18 OSCAR 21.9 2.4 64 146 +1975 10 10 12 25 FLORENCE 61.9 158.4 117 895 +1974 2 8 6 6 WILLIAM 42.0 50.3 98 594 +1967 1 24 6 24 PATTY 12.5 125.4 43 851 +1993 9 5 18 9 KIRK 56.9 214.9 86 385 +1961 3 16 0 26 BERYL 27.1 244.8 156 701 +2001 7 13 18 24 VALERIE 24.0 51.4 156 407 +2004 2 6 6 17 WILLIAM 24.6 114.1 100 201 +2004 6 8 6 23 HELENE 16.2 55.6 103 580 +1976 12 12 0 19 BERYL 37.3 165.3 114 79 +1992 3 20 12 24 BERYL 31.2 146.1 100 790 +1996 6 9 12 1 HELENE 67.1 129.6 141 815 +1983 1 27 0 25 ERNESTO 66.5 188.7 76 387 +1958 1 3 6 28 ISAAC 67.3 289.4 60 807 +1986 3 13 12 1 ISAAC 67.8 57.3 49 381 +2003 5 13 6 4 FLORENCE 46.5 112.8 125 335 +1990 5 5 18 5 PATTY 26.6 323.7 90 33 +1961 11 7 0 22 GORDON 22.6 120.7 68 435 +2003 6 16 18 13 ERNESTO 14.7 258.8 12 705 +2001 12 8 12 10 ALBERTO 33.0 305.1 58 207 +1966 12 3 12 18 ERNESTO 20.1 296.4 34 124 +1969 6 22 0 9 VALERIE 55.7 357.7 61 110 +1958 5 24 6 3 NADINE 7.6 160.6 66 14 +1997 12 19 6 8 CHRIS 61.4 154.6 152 710 +1977 10 17 12 3 PATTY 37.1 24.4 21 806 +1957 1 28 6 15 RAFAEL 42.3 21.3 71 156 +1987 11 17 6 26 HELENE 49.8 315.3 114 591 +1975 1 14 18 17 BERYL 22.4 238.0 109 855 +2002 3 20 18 5 WILLIAM 21.8 209.0 75 742 +1966 8 1 6 11 RAFAEL 30.8 203.6 23 193 +1959 4 4 0 1 NADINE 64.7 210.7 124 104 +1977 3 28 0 3 NADINE 68.9 259.4 160 4 +1957 2 19 0 24 MICHAEL 68.6 39.9 45 447 +1968 12 27 18 23 PATTY 54.5 1.5 122 862 +1955 12 5 18 15 ALBERTO 13.9 89.8 79 717 +1953 1 1 18 2 FLORENCE 64.3 313.2 105 257 +1968 5 23 12 4 WILLIAM 18.3 223.0 129 213 +1968 11 16 12 8 GORDON 44.4 16.9 156 28 +1978 3 1 12 9 VALERIE 7.6 200.1 70 475 +1963 9 25 0 2 FLORENCE 14.7 12.3 145 13 +1950 1 14 12 8 ERNESTO 36.6 213.0 48 515 +2003 5 7 18 23 SANDY 19.0 31.3 76 100 +1996 11 11 0 16 ALBERTO 68.0 346.9 144 882 +2003 8 21 0 18 CHRIS 31.3 17.7 73 139 +1951 12 3 18 19 LESLIE 13.2 328.0 62 364 +1971 8 28 12 27 RAFAEL 62.2 43.4 120 80 +1966 3 6 12 25 MICHAEL 66.5 38.9 25 454 +1982 11 7 18 12 LESLIE 63.0 160.4 62 689 +1960 1 1 6 10 ERNESTO 32.3 335.7 117 577 +1980 7 22 18 3 FLORENCE 62.1 216.9 132 157 +1975 4 17 12 6 NADINE 32.9 199.7 29 14 +1966 2 13 18 17 FLORENCE 32.2 30.3 121 402 +1955 5 12 6 5 VALERIE 64.4 124.5 112 891 +1966 10 19 0 17 KIRK 36.9 323.0 63 332 +1983 7 4 0 26 ISAAC 34.6 17.8 73 871 +2001 1 4 0 4 ERNESTO 35.4 312.0 15 442 +1962 3 1 6 22 MICHAEL 49.9 22.6 158 633 +1972 2 14 12 4 NADINE 32.1 301.2 78 751 +1978 3 27 6 21 FLORENCE 61.6 277.3 141 120 +1988 8 15 12 1 VALERIE 60.0 271.6 95 708 +1993 3 7 0 24 DEBBY 49.1 24.5 78 342 +1974 7 21 12 27 RAFAEL 36.6 159.0 101 666 +1956 4 6 6 9 LESLIE 58.6 181.0 150 832 +1985 9 11 12 14 WILLIAM 35.6 9.2 10 558 +1996 5 15 6 17 SANDY 13.5 126.4 109 221 +2000 5 11 12 5 PATTY 13.8 331.1 137 664 +1991 12 28 6 8 PATTY 7.3 39.4 31 361 +1976 7 15 18 7 GORDON 67.5 313.1 141 70 +1965 6 7 0 19 JOYCE 11.6 70.5 121 571 +1983 12 3 12 2 CHRIS 65.3 316.8 99 778 +1975 9 16 0 7 VALERIE 9.6 211.1 111 317 +1994 6 2 12 6 FLORENCE 27.5 59.9 139 874 +1977 8 23 6 10 JOYCE 46.2 191.9 22 416 +1961 8 25 0 13 BERYL 68.7 321.8 139 354 +1976 7 5 6 22 KIRK 44.5 238.7 10 101 +2001 12 19 0 14 OSCAR 32.1 106.9 16 583 +1963 12 18 12 23 FLORENCE 45.4 220.0 158 597 +1977 3 25 6 4 BERYL 42.5 108.8 148 772 +1984 2 23 12 10 ERNESTO 24.8 143.8 110 525 +1990 9 28 6 6 BERYL 21.2 322.7 76 455 +1966 8 10 0 5 OSCAR 14.2 50.2 152 349 +1952 1 4 12 8 WILLIAM 62.6 274.3 124 877 +1965 9 9 12 11 CHRIS 67.8 116.9 144 213 +1969 2 26 6 9 VALERIE 69.4 77.5 10 536 +2001 1 18 6 16 JOYCE 33.8 68.3 142 561 +1958 9 18 6 19 WILLIAM 51.2 222.7 155 304 +1977 8 7 6 10 LESLIE 34.3 193.2 152 490 +1959 12 15 18 11 DEBBY 58.4 129.2 59 795 +1996 7 16 0 26 TONY 9.9 120.0 10 223 +1983 5 7 6 27 CHRIS 69.9 197.2 126 855 +1987 4 15 18 10 MICHAEL 30.7 68.0 66 366 +1952 8 28 0 15 MICHAEL 23.2 324.3 92 384 +1979 5 9 0 26 TONY 9.3 268.2 107 672 +2001 7 27 6 13 CHRIS 34.6 211.6 116 497 +1966 10 10 18 4 VALERIE 48.4 118.1 54 52 +2002 4 17 6 22 GORDON 48.1 42.0 123 742 +1975 8 17 18 23 PATTY 55.0 344.2 87 183 +1962 3 14 18 26 GORDON 14.4 149.4 33 761 +2004 7 12 0 10 RAFAEL 35.8 7.1 117 201 +1960 1 18 12 3 TONY 7.1 241.9 132 307 +1995 9 16 12 20 JOYCE 38.2 334.3 136 499 +1992 2 16 6 14 LESLIE 34.1 311.5 78 205 +1960 3 28 6 5 MICHAEL 65.3 187.1 18 797 +1954 2 16 6 17 WILLIAM 7.8 225.6 154 688 +1992 12 16 6 24 BERYL 25.5 8.8 135 134 +1969 9 15 0 24 KIRK 15.5 55.9 27 334 +2002 8 22 6 27 PATTY 33.2 237.8 137 84 +1955 6 24 12 12 KIRK 58.9 131.8 121 502 +1995 5 17 0 1 SANDY 9.9 204.6 82 857 +1958 5 3 6 9 LESLIE 58.0 229.1 145 600 +2001 12 23 0 6 HELENE 38.2 23.5 80 589 +1988 3 17 6 2 DEBBY 32.4 138.4 134 528 +2003 6 18 12 7 JOYCE 25.4 94.7 81 92 +1973 12 21 18 3 KIRK 17.4 216.1 51 27 +1965 2 25 0 7 ALBERTO 27.3 32.3 98 459 +1952 9 27 0 19 GORDON 54.3 251.9 74 40 +1955 2 10 12 3 BERYL 55.1 212.3 82 840 +1960 1 28 6 3 CHRIS 30.8 345.9 12 7 +2003 4 16 18 16 TONY 9.9 246.0 36 514 +1984 11 18 18 17 PATTY 54.2 246.9 99 310 +1972 12 18 18 15 FLORENCE 60.2 278.9 59 656 +1963 2 16 12 7 LESLIE 70.0 251.8 44 43 +1980 2 21 6 28 SANDY 33.3 93.0 143 472 +1956 12 20 12 14 HELENE 16.3 141.9 61 733 +1999 6 9 12 24 ALBERTO 27.1 84.0 146 18 +1980 10 9 18 15 WILLIAM 31.9 336.1 21 410 +1960 10 2 0 16 SANDY 37.3 71.4 114 866 +1979 4 28 0 18 ISAAC 53.8 34.9 135 269 +1999 3 18 0 14 HELENE 64.6 308.1 102 717 +1981 5 25 6 8 RAFAEL 57.5 261.0 57 865 +1956 8 5 12 15 ALBERTO 11.2 253.5 126 222 +1955 2 17 18 22 OSCAR 34.7 1.0 43 510 +1998 4 19 6 2 LESLIE 39.3 12.9 42 68 +1975 7 16 18 11 GORDON 27.7 103.6 125 440 +1996 12 16 18 12 WILLIAM 31.1 237.5 25 847 +1992 6 21 18 22 FLORENCE 57.3 351.8 61 119 +1960 9 20 0 11 ALBERTO 9.2 66.6 107 780 +2003 3 6 0 14 SANDY 25.0 83.5 112 826 +1956 3 26 18 18 ISAAC 41.4 146.0 157 191 +1975 8 10 18 4 CHRIS 49.8 196.2 57 41 +2001 6 16 6 5 KIRK 27.1 353.8 152 68 +1972 4 11 12 14 LESLIE 26.7 18.5 139 216 +1999 12 11 0 24 WILLIAM 11.0 79.1 134 41 +2001 4 8 6 13 CHRIS 19.2 253.6 70 112 +1956 1 17 12 7 SANDY 21.9 25.0 115 442 +1970 12 11 6 4 MICHAEL 43.2 330.8 124 334 +1975 6 24 0 2 FLORENCE 12.5 307.0 102 536 +1967 4 27 0 20 BERYL 9.4 59.5 74 618 +2001 7 21 6 8 KIRK 9.2 126.0 37 669 +1988 10 17 12 20 ERNESTO 37.6 340.1 71 739 +1950 5 15 18 22 CHRIS 66.6 88.4 87 243 +1971 6 24 6 17 ERNESTO 17.5 353.2 12 244 +1988 6 10 6 7 LESLIE 26.3 242.7 51 175 +1984 5 20 12 23 RAFAEL 55.9 245.0 142 395 +1971 3 12 12 18 TONY 59.7 12.7 35 874 +1954 8 1 0 19 VALERIE 42.6 341.0 16 516 +1994 12 24 18 1 VALERIE 69.9 216.0 42 575 +1981 4 26 0 8 ISAAC 68.0 90.1 155 6 +1961 1 7 18 19 JOYCE 65.9 106.9 157 724 +1973 4 19 6 2 SANDY 12.6 215.7 31 68 +1954 12 6 12 10 GORDON 60.3 52.7 131 184 +1950 3 28 0 22 TONY 25.2 200.6 108 589 +1992 11 23 6 1 LESLIE 68.6 216.7 63 127 +1978 3 7 12 6 ERNESTO 61.3 322.5 157 335 +1988 11 17 12 13 HELENE 18.0 193.1 63 343 +1976 9 27 12 19 FLORENCE 30.9 281.3 135 674 +1996 5 17 12 11 FLORENCE 22.2 207.4 139 136 +2001 12 10 12 25 PATTY 30.1 203.5 65 610 +2001 10 6 0 18 DEBBY 44.3 127.6 113 477 +1961 6 15 18 7 KIRK 24.5 349.1 154 709 +1990 3 19 18 7 JOYCE 68.3 249.2 97 453 +1955 8 15 0 7 NADINE 32.5 311.0 163 157 +1993 10 28 18 18 KIRK 23.3 332.0 31 495 +1989 7 5 0 22 KIRK 18.1 176.9 39 470 +2002 12 9 6 16 OSCAR 15.3 217.1 66 112 +1954 10 23 6 5 WILLIAM 17.9 89.3 52 138 +1994 12 25 12 24 TONY 47.1 278.6 53 733 +1960 1 16 12 19 RAFAEL 60.8 57.0 24 780 +1955 1 6 6 18 ALBERTO 62.6 252.3 139 489 +1988 2 23 0 11 VALERIE 11.7 212.7 58 38 +1987 6 6 6 11 WILLIAM 34.2 125.5 20 854 +1992 7 6 0 15 JOYCE 25.2 178.3 90 356 +2003 12 22 18 13 RAFAEL 58.7 40.6 77 344 +1967 12 14 6 27 ERNESTO 43.7 82.8 88 288 +1971 6 17 6 17 RAFAEL 34.0 164.8 100 136 +1960 5 22 6 28 RAFAEL 47.7 221.9 61 355 +1982 6 28 6 15 ISAAC 10.9 76.7 163 656 +1980 8 28 18 15 LESLIE 21.3 114.8 28 870 +2004 5 26 6 24 ERNESTO 28.9 41.6 19 869 +1996 5 23 0 7 SANDY 42.3 234.3 149 512 +1957 1 19 0 10 FLORENCE 11.4 265.3 94 149 +1997 11 20 12 7 SANDY 51.9 155.8 72 553 +1984 3 11 18 3 GORDON 19.1 79.8 122 65 +1972 8 15 0 4 GORDON 9.0 136.2 45 717 +1959 4 12 18 22 KIRK 45.4 245.6 75 118 +1973 10 27 12 8 JOYCE 23.3 105.0 55 434 +1972 1 5 18 26 HELENE 30.2 230.4 118 629 +1979 3 24 0 2 BERYL 37.3 150.2 61 161 +1986 10 17 18 27 HELENE 61.3 147.2 112 301 +1963 12 11 12 23 CHRIS 61.0 129.1 136 219 +1992 10 24 6 18 FLORENCE 40.0 247.0 99 440 +1958 11 20 6 1 LESLIE 42.6 338.5 55 775 +2000 9 11 6 20 GORDON 60.0 326.5 132 787 +1982 2 2 12 21 BERYL 31.8 205.7 114 763 +2002 9 11 18 2 GORDON 23.5 91.4 151 402 +1979 4 1 18 27 ERNESTO 45.6 195.7 141 517 +1986 9 7 6 14 BERYL 26.3 261.7 23 378 +1959 7 24 6 24 DEBBY 69.9 41.4 144 735 +1968 8 7 0 24 VALERIE 29.7 18.8 124 97 +1965 3 19 12 9 ALBERTO 37.3 128.7 33 463 +1954 11 13 18 23 ALBERTO 47.2 307.3 96 154 +1960 9 11 6 21 JOYCE 20.4 96.3 120 826 +1976 1 21 18 26 NADINE 13.0 300.8 46 636 +1967 11 19 12 24 MICHAEL 9.4 351.8 57 461 +1960 6 7 0 19 FLORENCE 39.1 108.7 160 311 +1973 1 15 6 8 CHRIS 65.0 209.1 80 183 +1998 1 5 12 7 ISAAC 53.4 132.6 74 366 +1967 5 5 0 13 HELENE 36.0 143.4 52 528 +1979 2 11 18 10 RAFAEL 26.1 352.3 56 736 +1965 12 18 0 13 FLORENCE 29.8 87.7 132 311 +1970 12 11 6 18 HELENE 57.9 200.5 56 693 +1963 6 5 18 12 LESLIE 47.7 144.5 83 488 +1994 4 28 18 11 VALERIE 69.9 240.9 126 771 +2003 1 8 0 24 MICHAEL 21.0 154.5 16 532 +1995 4 17 12 21 ISAAC 7.5 166.4 154 458 +1979 11 6 18 5 GORDON 61.0 287.1 12 312 +1966 6 22 6 8 RAFAEL 68.1 71.4 18 727 +1997 2 20 6 16 FLORENCE 10.6 333.6 17 789 +1988 2 18 12 24 HELENE 62.9 201.3 149 22 +1982 6 28 0 19 OSCAR 16.9 307.4 83 215 +1968 6 4 18 19 TONY 60.3 300.2 115 651 +2002 2 28 18 18 OSCAR 22.3 301.1 130 431 +1999 2 24 6 9 ALBERTO 57.6 4.5 90 61 +1992 12 26 18 26 GORDON 66.5 253.4 10 38 +1955 2 9 12 14 GORDON 11.9 266.3 68 680 +1965 10 4 6 6 ALBERTO 60.1 22.6 49 377 +1982 8 16 18 6 BERYL 66.5 171.7 91 98 +1995 12 7 6 21 RAFAEL 69.6 226.3 50 30 +1995 7 7 6 10 PATTY 60.8 23.9 42 854 +2003 6 14 12 24 WILLIAM 37.9 67.7 101 645 +1976 4 13 12 16 NADINE 69.1 154.1 103 747 +1999 10 16 18 12 VALERIE 35.4 211.5 108 622 +1999 5 20 6 12 TONY 62.8 27.2 133 723 +1999 9 9 12 20 SANDY 44.1 316.6 73 19 +1973 10 13 12 13 JOYCE 60.1 222.2 87 124 +1954 10 26 18 13 WILLIAM 38.2 356.5 38 381 +1971 10 19 6 11 LESLIE 44.1 332.4 33 284 +1984 12 13 6 24 VALERIE 12.5 147.7 153 256 +1950 6 9 12 16 PATTY 44.3 284.7 90 598 +1990 11 28 6 28 SANDY 14.6 252.9 73 881 +1998 12 25 18 19 SANDY 28.1 323.1 22 783 +1962 2 8 0 28 SANDY 47.5 213.3 37 506 +1977 11 27 12 21 HELENE 58.2 297.0 56 288 +1953 4 16 6 4 PATTY 12.5 189.9 117 344 +1965 2 10 0 8 LESLIE 28.0 156.0 13 57 +1964 2 22 12 14 VALERIE 45.0 125.3 46 118 +1953 6 6 12 6 DEBBY 60.6 44.5 20 719 +1989 1 4 18 13 FLORENCE 21.8 136.4 110 667 +1995 5 7 6 14 RAFAEL 65.2 196.7 38 173 +1954 5 12 6 5 ISAAC 14.2 225.8 133 281 +1981 12 25 18 5 ISAAC 47.1 354.7 45 307 +1968 9 11 0 18 MICHAEL 63.1 308.7 73 621 +1998 8 13 12 19 VALERIE 22.2 295.7 135 134 +1982 1 21 18 14 HELENE 23.7 308.5 154 513 +1990 11 20 12 15 RAFAEL 16.4 192.7 25 495 +2001 1 23 18 9 GORDON 55.2 202.3 115 566 +1975 5 8 12 14 LESLIE 13.1 89.3 142 114 +1952 1 6 6 20 KIRK 35.4 201.9 114 83 +1965 9 2 12 23 JOYCE 48.6 290.0 58 739 +1974 11 7 0 22 ERNESTO 11.5 163.9 108 366 +1951 8 24 12 18 ALBERTO 33.5 61.6 59 37 +1981 11 22 18 27 TONY 44.4 318.0 93 755 +1982 11 14 0 3 KIRK 42.3 301.2 68 420 +1972 10 4 18 1 ERNESTO 17.7 135.9 103 589 +1995 8 25 12 5 WILLIAM 22.6 11.9 54 359 +1988 4 5 18 25 ISAAC 17.5 47.9 19 374 +1998 8 8 18 13 ALBERTO 50.5 233.1 59 803 +1988 6 16 6 18 WILLIAM 22.4 61.6 146 255 +1998 9 9 18 1 CHRIS 53.2 41.0 36 687 +1996 1 1 18 6 JOYCE 34.1 271.8 109 518 +1994 8 4 6 2 SANDY 12.3 115.0 78 640 +1971 7 2 18 12 CHRIS 30.0 21.8 43 834 +1950 2 20 0 20 CHRIS 23.1 37.5 18 666 +1987 12 22 18 24 RAFAEL 14.7 131.8 163 724 +1998 10 20 18 17 FLORENCE 39.4 78.3 139 663 +1984 11 14 0 22 OSCAR 48.8 250.7 105 202 +1971 11 14 18 11 HELENE 38.0 251.0 147 821 +1987 1 5 6 18 ALBERTO 17.6 90.9 48 371 +1993 5 7 0 21 BERYL 8.2 268.0 92 893 +1966 10 22 0 21 OSCAR 38.6 25.1 162 162 +1956 9 28 18 7 LESLIE 61.7 220.4 32 796 +1953 11 23 0 14 NADINE 16.1 202.2 89 818 +1955 12 17 6 21 BERYL 52.8 258.5 20 51 +1986 7 20 12 20 MICHAEL 34.6 19.4 127 858 +1952 4 16 18 3 NADINE 16.7 74.5 33 40 +1960 12 11 18 22 HELENE 65.7 289.0 113 828 +1993 10 13 6 23 HELENE 49.3 142.4 123 759 +1966 2 14 0 28 VALERIE 66.1 32.2 119 313 +1974 8 26 12 13 HELENE 40.4 189.2 116 599 +1977 1 11 0 28 KIRK 12.7 272.9 76 6 +1995 9 9 12 23 BERYL 33.9 80.1 32 300 +1977 8 13 12 11 WILLIAM 65.3 339.6 80 253 +1980 3 9 18 20 ERNESTO 11.0 216.0 112 322 +1960 7 27 12 20 BERYL 40.0 2.0 39 397 +1983 4 8 6 24 KIRK 29.1 255.5 118 354 +1997 10 8 12 3 NADINE 37.4 145.1 49 32 +1956 3 6 6 17 SANDY 60.2 131.3 108 358 +1977 12 19 12 14 HELENE 36.3 8.8 52 585 +1988 8 27 0 11 ALBERTO 46.1 175.0 86 272 +1995 10 9 0 11 LESLIE 48.3 174.9 12 109 +1973 2 22 0 18 TONY 41.7 83.0 101 578 +1998 2 20 0 3 TONY 46.4 290.9 115 309 +1983 10 15 6 2 VALERIE 54.0 252.0 66 785 +1958 9 14 18 24 TONY 16.9 51.4 108 385 +1975 12 10 0 4 PATTY 9.5 142.6 115 679 +1998 5 3 12 25 DEBBY 57.2 245.8 141 748 +1982 10 21 6 22 CHRIS 53.5 183.3 139 738 +1973 6 16 12 6 DEBBY 35.0 124.4 10 112 +1955 2 13 18 26 FLORENCE 23.3 125.8 35 10 +1974 9 27 12 9 RAFAEL 32.8 81.9 65 593 +1979 10 2 6 7 NADINE 26.3 92.4 156 109 +1984 8 18 18 24 GORDON 55.4 316.0 78 636 +1982 11 2 6 7 GORDON 65.5 284.6 139 464 +1958 2 25 12 20 TONY 43.9 15.3 97 822 +1978 7 18 18 14 MICHAEL 60.9 347.7 61 244 +1966 11 4 18 10 DEBBY 53.4 216.3 153 832 +1992 5 10 6 6 HELENE 48.2 76.7 32 673 +2000 5 25 12 2 CHRIS 30.1 136.3 57 39 +1969 5 27 0 28 ISAAC 12.0 88.5 115 113 +1970 8 28 0 25 WILLIAM 59.2 262.9 149 769 +1967 10 12 6 11 BERYL 61.7 46.2 140 759 +1954 8 26 12 14 WILLIAM 13.8 291.3 56 11 +1975 3 25 18 1 GORDON 57.0 48.4 82 646 +1970 5 13 6 16 JOYCE 26.9 252.6 59 807 +1975 9 21 6 4 FLORENCE 35.5 349.8 32 236 +1964 4 4 6 12 ERNESTO 9.9 205.1 59 807 +1981 4 10 6 10 ISAAC 25.4 148.5 21 513 +1997 9 13 0 22 HELENE 32.3 301.2 35 392 +2004 3 14 12 11 KIRK 44.0 234.6 91 47 +1972 3 19 6 15 ALBERTO 33.7 158.1 38 760 +1993 1 3 12 21 LESLIE 31.5 179.9 161 558 +1969 2 20 0 16 SANDY 67.5 172.6 54 863 +1961 4 27 12 23 PATTY 26.6 105.1 108 803 +1972 1 6 0 20 FLORENCE 39.2 33.1 11 691 +2004 3 3 0 4 LESLIE 56.3 68.5 66 704 +1959 12 25 18 8 NADINE 18.5 151.2 57 681 +1963 4 20 6 22 JOYCE 62.0 19.1 116 423 +1960 2 19 18 24 BERYL 55.1 200.7 57 801 +1956 10 18 12 22 GORDON 21.2 36.1 100 565 +1995 6 27 18 17 VALERIE 16.9 59.3 103 180 +1965 12 16 6 16 MICHAEL 16.9 204.2 155 5 +1997 3 18 6 1 WILLIAM 50.2 239.4 131 803 +1992 11 25 12 28 GORDON 13.3 314.6 83 499 +1972 3 24 0 7 SANDY 62.9 323.6 93 288 +1999 8 25 0 14 RAFAEL 40.4 69.0 141 490 +1986 4 25 6 14 DEBBY 9.2 171.6 39 201 +1984 5 9 0 16 KIRK 38.1 132.3 10 653 +2001 6 16 0 22 RAFAEL 50.7 148.2 104 553 +1988 12 12 12 27 CHRIS 67.1 340.4 138 718 +1969 12 11 18 12 WILLIAM 30.5 191.0 115 330 +2002 11 13 0 14 JOYCE 13.6 95.6 79 570 +1967 6 14 12 17 DEBBY 14.7 19.5 57 430 +1992 4 16 12 24 SANDY 58.8 116.5 78 539 +1980 11 20 0 5 OSCAR 57.2 176.4 153 518 +1956 10 6 12 5 DEBBY 29.3 300.8 115 15 +1994 10 12 6 7 PATTY 36.9 282.4 43 162 +1951 7 19 12 6 WILLIAM 58.6 223.2 141 873 +1976 1 8 12 25 TONY 32.3 142.1 111 14 +1967 7 26 0 2 VALERIE 66.9 189.0 162 608 +2002 2 18 6 8 TONY 12.2 261.2 158 34 +1977 7 27 6 16 RAFAEL 37.6 259.8 104 83 +1962 12 18 6 5 DEBBY 11.7 144.8 159 449 +1987 12 16 6 21 GORDON 27.5 273.3 41 224 +1999 2 6 12 23 SANDY 55.4 50.2 76 454 +1964 11 15 12 10 MICHAEL 19.1 130.7 161 34 +1977 11 15 18 9 NADINE 19.2 279.2 123 611 +2003 2 28 6 12 ALBERTO 50.6 114.0 88 404 +1974 7 6 12 18 WILLIAM 11.4 225.8 83 399 +1994 6 5 0 19 WILLIAM 11.7 332.5 47 388 +1983 8 4 0 21 RAFAEL 66.6 339.1 126 384 +1960 9 24 6 28 NADINE 42.9 217.9 164 241 +2003 10 4 0 12 ERNESTO 66.8 171.0 61 482 +1967 3 20 6 21 ERNESTO 38.8 27.3 66 798 +1956 9 25 6 6 JOYCE 50.0 51.1 156 54 +1998 7 20 18 7 ALBERTO 31.3 170.4 103 142 +1981 3 6 18 20 ALBERTO 38.7 217.8 86 650 +1966 3 4 12 21 ISAAC 63.1 279.1 83 93 +1974 4 9 12 2 CHRIS 47.3 207.2 145 566 +1985 11 4 0 1 PATTY 61.7 184.6 134 649 +1954 3 8 12 15 DEBBY 53.1 356.1 74 693 +1987 2 23 0 8 FLORENCE 16.0 35.0 95 18 +1977 3 2 0 13 LESLIE 44.0 10.6 82 548 +1981 11 7 6 19 JOYCE 39.3 200.7 108 175 +1993 2 3 12 7 ISAAC 40.7 273.8 142 687 +1987 9 4 18 2 ISAAC 52.1 98.2 36 550 +1978 10 14 18 18 ALBERTO 45.7 139.6 143 31 +1979 4 23 6 10 PATTY 39.1 147.6 116 278 +1986 1 13 12 26 WILLIAM 60.9 302.5 81 842 +1989 8 24 12 17 RAFAEL 51.4 122.7 149 567 +1970 8 14 12 16 ALBERTO 48.4 68.8 138 899 +1969 12 17 6 13 MICHAEL 55.8 217.7 149 51 +1971 10 26 0 1 CHRIS 31.4 147.9 104 343 +1981 8 13 12 17 NADINE 8.5 253.1 21 816 +1958 2 14 0 16 KIRK 10.6 128.8 51 694 +1988 1 4 0 10 PATTY 28.3 300.6 18 186 +1982 5 28 18 19 JOYCE 32.4 206.6 87 14 +2000 8 20 18 25 VALERIE 68.4 182.6 83 106 +1996 12 12 12 4 VALERIE 41.2 330.4 129 852 +1991 1 17 0 2 SANDY 18.8 335.1 58 679 +1984 5 13 6 18 CHRIS 44.1 236.7 28 579 +1966 9 2 18 5 TONY 16.0 199.2 22 576 +1964 12 12 18 9 VALERIE 23.1 316.0 137 718 +1997 11 9 18 22 BERYL 62.3 267.8 146 263 +1999 1 18 12 24 OSCAR 9.6 210.4 112 750 +1959 5 21 18 8 GORDON 57.6 33.8 21 846 +1989 8 13 6 19 ERNESTO 67.6 196.3 22 584 +1972 2 8 12 20 GORDON 58.1 31.9 51 368 +1992 8 19 6 10 GORDON 61.4 164.1 103 745 +1961 5 23 0 6 ISAAC 66.0 196.5 97 173 +2000 1 4 12 25 ERNESTO 59.2 159.5 26 208 +1975 9 3 18 25 ALBERTO 45.0 136.2 70 615 +1959 10 14 6 9 OSCAR 21.7 94.5 25 225 +1995 6 14 6 23 ALBERTO 19.0 282.7 124 114 +2003 3 27 18 13 RAFAEL 14.7 348.1 105 116 +1977 4 2 6 22 FLORENCE 70.0 18.8 35 752 +1957 2 4 18 14 KIRK 36.8 265.2 74 819 +1980 2 7 18 18 WILLIAM 57.3 208.5 130 828 +1986 5 24 0 4 VALERIE 66.7 299.9 64 238 +1996 7 6 6 7 TONY 13.5 314.8 153 105 +1968 10 15 0 16 LESLIE 34.1 347.2 47 265 +1997 6 18 6 14 WILLIAM 21.1 263.7 28 530 +1976 9 13 0 16 CHRIS 62.2 145.3 133 390 +1996 7 24 12 7 ALBERTO 47.1 241.3 47 399 +1953 1 11 6 14 GORDON 15.2 179.0 89 878 +1999 3 20 0 22 DEBBY 38.9 320.2 80 334 +1951 4 14 12 4 LESLIE 65.9 321.1 89 442 +1967 3 16 0 3 MICHAEL 21.9 46.7 20 535 +1983 10 2 18 15 ALBERTO 11.8 302.5 94 772 +1977 4 2 0 11 LESLIE 46.5 28.0 61 13 +1953 3 1 18 24 BERYL 32.3 144.9 74 346 +1962 12 10 12 6 WILLIAM 29.7 335.6 110 32 +1964 5 1 18 6 ISAAC 50.6 228.3 67 81 +2004 2 25 18 23 CHRIS 46.1 322.7 114 662 +1973 2 8 12 14 ERNESTO 32.6 206.5 112 442 +1959 10 2 0 23 KIRK 22.9 203.3 38 543 +1956 3 4 0 6 PATTY 26.4 182.3 85 299 +1994 8 2 12 6 DEBBY 22.0 41.3 105 337 +1997 11 20 6 13 WILLIAM 28.5 108.7 63 439 +1990 7 26 18 28 PATTY 24.8 53.6 158 682 +1998 3 3 6 24 BERYL 46.2 145.7 157 154 +1979 11 3 0 2 VALERIE 34.7 274.8 145 647 +1984 10 28 0 2 TONY 45.4 296.8 124 600 +1994 12 1 12 2 LESLIE 51.5 163.9 150 77 +1997 9 28 0 14 GORDON 25.3 234.3 95 519 +1964 9 23 6 15 LESLIE 53.8 114.1 118 640 +1967 9 4 12 3 ALBERTO 13.7 111.4 38 65 +1987 2 7 12 13 PATTY 48.2 138.5 82 598 +1955 7 13 12 28 CHRIS 67.0 343.5 120 852 +1994 12 11 0 18 SANDY 53.9 194.3 20 158 +1972 3 12 18 11 TONY 41.1 177.8 59 170 +1958 7 25 0 20 CHRIS 48.8 91.9 61 161 +2002 3 7 12 15 SANDY 19.0 214.5 134 607 +1973 10 10 18 11 HELENE 54.0 7.0 132 102 +1974 6 12 12 28 KIRK 42.9 136.8 27 868 +1986 10 10 0 18 NADINE 34.7 44.9 163 73 +1997 6 7 0 12 WILLIAM 50.3 96.9 13 659 +1954 4 23 0 17 FLORENCE 12.2 53.2 63 94 +1951 1 20 12 14 LESLIE 54.3 184.8 36 736 +2004 11 3 0 25 LESLIE 19.5 180.0 77 109 +1953 4 23 18 3 NADINE 39.1 109.5 70 224 +1983 1 12 18 10 VALERIE 58.9 110.3 22 400 +1956 7 7 0 22 LESLIE 50.7 222.3 65 330 +1977 12 9 12 20 ALBERTO 31.8 182.0 135 682 +1968 6 25 0 19 ALBERTO 64.2 155.7 36 362 +1953 5 26 12 21 HELENE 58.4 186.3 160 265 +1986 10 4 6 4 OSCAR 20.5 323.9 157 60 +1982 4 3 18 18 HELENE 68.9 309.6 41 337 +1975 3 2 18 20 DEBBY 20.8 264.5 11 39 +1951 2 7 6 13 FLORENCE 20.6 174.9 138 281 +1987 7 13 0 9 NADINE 22.0 63.4 33 504 +1975 5 9 12 4 LESLIE 26.9 218.4 145 887 +1972 2 18 0 21 MICHAEL 38.7 85.9 156 778 +1952 3 4 6 2 PATTY 40.7 244.9 49 220 +1956 7 4 6 22 BERYL 60.2 200.8 12 424 +1998 3 4 12 28 ALBERTO 34.0 235.7 29 582 +1951 6 26 0 15 GORDON 37.0 356.3 156 817 +1978 11 3 12 8 NADINE 19.1 13.4 15 249 +1995 7 5 12 22 VALERIE 55.2 354.4 56 569 +1975 6 15 6 25 DEBBY 52.8 98.7 43 65 +1969 7 18 12 24 NADINE 64.6 137.0 110 443 +1987 1 9 18 23 PATTY 26.7 252.7 77 506 +1983 1 5 0 6 HELENE 51.0 66.9 120 137 +1960 9 3 0 17 MICHAEL 48.1 333.6 18 271 +1975 10 24 12 21 ISAAC 13.0 162.2 102 397 +1961 10 9 12 1 FLORENCE 68.7 37.6 78 750 +1998 8 12 0 12 SANDY 14.2 248.1 85 402 +2000 7 17 12 20 TONY 68.7 30.1 150 29 +1976 11 5 12 21 BERYL 36.8 198.8 67 487 +1968 3 27 12 10 CHRIS 54.1 159.1 86 58 +1962 11 26 6 3 MICHAEL 69.1 283.2 46 433 +1995 11 9 18 3 CHRIS 24.4 140.3 33 107 +1952 6 15 0 27 RAFAEL 29.9 52.9 67 212 +1995 7 24 0 21 GORDON 64.5 75.2 35 25 +1951 9 24 0 26 SANDY 13.2 0.4 114 800 +1953 5 16 0 20 CHRIS 15.5 9.9 103 826 +1990 2 22 0 12 RAFAEL 7.6 354.0 12 137 +1980 9 8 18 19 BERYL 49.5 223.5 76 697 +1985 10 20 0 11 SANDY 56.9 341.3 143 195 +1988 6 25 0 11 TONY 30.7 354.5 51 152 +1950 8 1 0 16 ISAAC 36.9 290.1 125 180 +1985 2 1 18 14 ALBERTO 47.5 25.6 62 124 +1986 8 25 18 14 RAFAEL 55.2 253.9 69 374 +1952 11 17 18 20 DEBBY 64.9 17.1 136 96 +1967 12 10 6 19 BERYL 24.1 80.7 158 751 +1950 2 12 0 10 SANDY 38.8 10.2 40 425 +1995 10 4 0 2 SANDY 28.6 144.0 64 558 +1982 5 14 18 7 HELENE 28.0 237.2 59 608 +1977 6 11 0 20 MICHAEL 63.0 23.8 61 543 +1956 5 1 12 15 VALERIE 23.3 26.5 23 662 +1975 6 6 0 17 ERNESTO 57.8 13.7 156 408 +1954 1 12 0 10 KIRK 39.4 163.0 24 125 +1999 4 13 18 2 ERNESTO 26.5 316.7 54 696 +1997 3 3 18 6 CHRIS 30.4 126.4 35 719 +1959 5 20 6 13 MICHAEL 37.7 108.9 122 473 +1976 5 19 0 24 OSCAR 43.5 42.3 163 43 +1972 1 20 12 12 TONY 36.8 59.0 61 651 +1960 9 8 12 15 ERNESTO 58.0 260.6 141 761 +1963 5 20 18 8 RAFAEL 16.7 208.7 20 700 +2003 1 22 0 22 GORDON 64.5 106.8 102 687 +1981 5 23 18 10 LESLIE 7.2 232.0 54 716 +2000 10 25 0 27 FLORENCE 38.1 298.6 131 427 +1997 5 19 12 20 ALBERTO 40.2 49.7 110 576 +1958 1 8 12 5 MICHAEL 66.4 189.5 71 377 +1979 10 14 18 4 TONY 56.6 155.9 116 148 +1963 6 1 12 22 ISAAC 40.1 266.1 46 640 +1998 12 18 18 19 KIRK 24.0 111.6 65 475 +1984 5 9 18 1 ALBERTO 26.9 44.4 91 131 +1962 5 18 18 11 VALERIE 16.0 281.8 118 575 +1995 10 24 12 28 ALBERTO 42.2 160.8 13 558 +1990 5 11 0 5 SANDY 65.7 353.7 88 461 +1969 10 24 12 3 WILLIAM 43.0 314.1 117 265 +1966 12 11 0 10 SANDY 36.5 318.7 107 476 +1972 3 4 0 7 NADINE 19.4 191.0 130 428 +2003 1 26 18 22 DEBBY 48.7 67.9 26 564 +1966 8 16 12 9 ALBERTO 55.0 44.0 94 214 +1969 11 18 6 28 BERYL 42.3 31.5 62 776 +1972 1 1 6 16 FLORENCE 34.6 185.6 126 371 +1961 8 20 12 25 OSCAR 23.1 82.4 21 609 +1995 2 14 0 1 HELENE 51.1 62.5 72 29 +1970 9 12 0 9 DEBBY 55.1 209.3 27 411 +1958 1 7 0 14 BERYL 48.4 120.3 39 96 +1952 5 19 12 2 WILLIAM 39.3 129.5 132 297 +1958 2 4 12 8 ERNESTO 35.0 221.2 50 428 +1999 9 8 18 12 TONY 57.3 206.7 84 723 +1955 7 18 18 2 HELENE 43.2 47.0 51 779 +1972 6 26 6 15 DEBBY 36.5 118.4 94 703 +1996 4 19 0 1 RAFAEL 45.5 286.0 75 492 +2002 10 2 18 13 VALERIE 35.6 92.1 64 268 +1999 5 2 0 22 ERNESTO 39.3 118.3 38 108 +1991 4 7 6 1 ISAAC 60.3 116.3 137 876 +1993 7 19 0 27 DEBBY 39.7 267.8 130 430 +1985 8 11 12 6 JOYCE 46.5 218.0 127 177 +1990 2 18 18 8 RAFAEL 60.5 276.9 108 32 +1983 8 20 0 21 LESLIE 10.7 294.0 34 147 +1990 1 23 0 17 ALBERTO 49.9 66.6 109 640 +1993 8 11 0 1 SANDY 46.7 291.6 133 420 +1965 10 20 6 3 ISAAC 36.0 248.6 154 241 +1973 11 14 12 21 TONY 21.3 107.4 19 368 +1963 5 8 0 18 PATTY 30.7 33.0 142 677 +2000 7 27 0 14 ERNESTO 15.5 88.4 119 661 +1975 1 9 12 6 NADINE 65.4 202.3 160 169 +1950 4 2 18 27 CHRIS 31.2 30.6 44 291 +1957 1 12 6 8 JOYCE 69.3 329.0 37 218 +1972 4 13 12 25 KIRK 69.1 230.0 96 332 +1962 8 4 12 19 VALERIE 56.5 124.9 110 105 +1984 4 4 18 18 WILLIAM 47.5 165.5 84 347 +1982 5 28 18 6 ALBERTO 33.7 318.1 69 324 +2004 5 28 18 6 ERNESTO 16.7 136.5 125 768 +1999 4 16 18 18 RAFAEL 62.2 121.2 103 94 +1977 1 28 12 28 PATTY 13.0 65.5 94 680 +1985 8 27 18 4 SANDY 56.8 355.3 152 832 +1978 9 7 6 15 CHRIS 43.9 243.8 93 450 +1955 5 3 6 10 KIRK 14.0 239.1 14 690 +1963 10 6 12 21 FLORENCE 22.2 264.1 130 222 +1973 11 2 18 26 DEBBY 47.9 121.9 147 592 +1961 6 24 18 2 WILLIAM 35.6 340.8 136 115 +1955 6 8 18 27 FLORENCE 12.1 245.4 16 881 +2000 7 1 6 22 MICHAEL 12.4 182.6 73 239 +1954 12 13 0 3 MICHAEL 33.3 304.3 114 722 +1994 3 5 18 14 OSCAR 44.7 0.2 142 284 +1985 6 14 0 7 MICHAEL 10.8 137.9 86 176 +1970 11 22 18 26 MICHAEL 49.3 62.4 153 13 +1958 2 13 6 3 MICHAEL 41.0 315.1 155 683 +1973 1 12 12 5 RAFAEL 39.7 177.4 73 390 +1987 10 24 12 12 FLORENCE 63.0 300.1 28 566 +1967 4 27 0 3 BERYL 10.3 103.1 158 200 +1979 1 12 12 25 ISAAC 26.0 107.9 116 38 +1998 4 9 18 3 CHRIS 64.3 62.7 153 728 +1970 2 4 18 5 SANDY 55.8 70.5 18 756 +1989 2 7 0 21 FLORENCE 36.5 187.4 20 159 +1973 2 25 18 26 HELENE 51.4 97.4 118 340 +2001 8 27 18 10 CHRIS 16.7 221.4 51 108 +1955 3 20 12 22 CHRIS 19.5 117.9 145 673 +1980 6 19 0 13 ERNESTO 55.8 131.5 110 218 +1983 3 10 0 10 KIRK 8.9 314.9 150 591 +2004 7 2 6 6 RAFAEL 57.7 219.1 44 689 +1961 6 21 18 20 NADINE 35.9 5.0 42 226 +1998 9 17 6 8 ERNESTO 49.8 19.1 81 352 +1961 2 2 12 3 BERYL 12.6 178.5 75 396 +1956 3 17 12 10 LESLIE 31.9 140.3 13 719 +1974 6 26 0 19 BERYL 41.4 207.4 29 111 +1972 5 17 6 28 GORDON 7.9 336.6 33 755 +1964 5 12 6 17 ERNESTO 50.8 37.2 109 347 +1988 10 24 18 4 WILLIAM 29.4 331.6 26 748 +1969 6 6 0 19 GORDON 14.5 127.7 107 173 +2001 6 20 18 27 ISAAC 41.8 298.3 63 493 +1996 10 1 18 21 FLORENCE 35.5 170.2 104 421 +1972 11 17 18 22 KIRK 49.3 298.1 32 584 +1996 7 5 12 21 ALBERTO 39.7 37.9 27 533 +1956 11 16 18 16 VALERIE 50.6 341.7 36 554 +1957 11 22 0 19 GORDON 9.7 46.2 153 738 +1958 6 18 6 22 PATTY 33.1 221.2 63 296 +1951 11 11 6 12 ALBERTO 17.4 324.2 139 289 +1970 2 21 0 23 VALERIE 49.1 50.3 160 743 +1982 4 18 18 6 GORDON 69.4 17.4 110 500 +1993 11 6 6 20 ERNESTO 36.7 317.8 78 506 +1951 4 22 12 12 BERYL 22.4 296.2 17 313 +1961 2 12 18 16 TONY 31.5 52.8 138 548 +1986 6 14 6 4 PATTY 36.6 141.6 117 460 +1977 11 11 12 2 KIRK 24.9 294.3 142 47 +1994 2 18 6 14 FLORENCE 22.2 169.6 69 808 +1967 1 24 12 1 MICHAEL 69.1 207.1 128 134 +2003 10 18 18 21 ALBERTO 63.3 334.3 51 41 +1992 9 9 12 19 SANDY 58.4 323.1 34 589 +2001 8 21 18 25 TONY 25.3 136.3 95 750 +1990 3 28 18 23 VALERIE 25.4 255.6 119 740 +1950 2 12 18 16 VALERIE 50.7 29.7 81 259 +1972 6 4 18 25 SANDY 17.9 273.0 134 882 +1971 11 15 18 20 LESLIE 26.1 153.0 98 568 +1963 1 13 12 18 VALERIE 59.9 173.5 38 489 +1980 4 20 12 1 TONY 35.6 317.5 21 778 +1971 10 28 0 28 LESLIE 37.7 73.8 138 324 +1967 2 28 6 7 LESLIE 55.3 348.7 92 400 +1996 1 27 12 4 NADINE 29.3 287.2 126 304 +1962 11 15 6 19 ALBERTO 59.6 190.7 90 214 +1950 12 7 12 6 NADINE 45.6 45.8 32 172 +1983 3 23 12 26 ALBERTO 62.1 316.1 152 693 +1995 3 9 0 8 BERYL 9.1 155.9 98 712 +1976 12 17 18 9 VALERIE 28.3 218.9 20 5 +1958 8 9 6 22 WILLIAM 62.1 175.9 140 59 +1956 4 1 12 12 LESLIE 41.3 101.9 51 600 +1961 6 23 12 24 JOYCE 13.2 4.1 56 443 +1958 11 9 6 18 RAFAEL 59.6 93.0 99 743 +1984 10 10 0 2 MICHAEL 18.5 351.0 26 402 +1967 10 22 18 11 FLORENCE 8.3 25.4 156 676 +1993 9 21 18 18 OSCAR 14.6 79.0 86 441 +1959 12 17 0 14 BERYL 9.2 149.7 34 805 +1970 12 6 0 10 BERYL 23.3 12.1 40 791 +1997 11 14 6 2 CHRIS 34.5 336.8 113 492 +1952 7 23 0 3 KIRK 55.7 109.1 47 161 +1981 6 2 12 27 CHRIS 38.7 85.9 113 132 +1973 7 4 0 2 TONY 25.1 273.6 60 536 +1986 2 20 12 9 JOYCE 49.2 48.2 151 555 +2004 9 23 6 12 DEBBY 34.6 112.1 101 846 +1984 7 9 6 10 BERYL 26.3 158.6 40 140 +1973 11 14 6 24 BERYL 33.9 17.0 23 451 +1988 8 5 0 21 OSCAR 29.6 160.7 152 581 +1962 8 22 18 21 BERYL 63.9 291.7 142 312 +1994 11 2 6 17 OSCAR 23.2 305.9 74 795 +1960 8 5 18 27 VALERIE 27.7 239.9 150 494 +2002 12 24 12 12 RAFAEL 20.2 175.1 130 591 +2001 10 12 12 15 PATTY 28.2 263.0 152 232 +1957 9 22 6 18 TONY 16.9 177.9 147 267 +2001 7 12 12 23 GORDON 13.5 289.2 79 284 +1978 7 2 12 5 RAFAEL 57.8 20.1 64 892 +1990 2 27 0 25 KIRK 61.7 121.0 96 527 +1982 12 14 18 5 SANDY 49.9 32.1 108 720 +1970 10 26 6 10 ALBERTO 8.8 294.5 78 832 +1990 6 17 12 24 SANDY 60.9 229.6 75 517 +1958 9 18 18 10 NADINE 36.4 107.4 112 83 +1997 8 6 0 11 CHRIS 66.6 52.4 61 391 +1980 4 9 0 14 ALBERTO 43.8 320.6 28 693 +1990 5 14 6 6 CHRIS 31.4 222.8 24 656 +1987 11 5 0 12 VALERIE 16.0 103.4 142 762 +1966 10 24 0 17 SANDY 55.3 161.5 24 384 +1950 6 6 0 3 MICHAEL 31.6 179.1 141 192 +1957 2 12 6 17 PATTY 44.3 17.7 50 531 +1958 6 28 0 21 BERYL 68.4 243.7 155 367 +2001 11 18 6 28 NADINE 61.7 196.7 12 96 +1967 4 17 6 15 WILLIAM 38.1 334.1 18 280 +1990 9 23 12 23 VALERIE 27.2 249.5 61 274 +1988 1 18 18 18 OSCAR 20.1 175.1 79 463 +1951 3 19 0 7 DEBBY 17.9 339.1 54 833 +1983 9 16 12 8 KIRK 63.2 96.5 10 863 +1998 3 8 6 7 ISAAC 43.7 296.2 46 524 +1954 3 5 0 6 VALERIE 8.5 200.8 18 333 +1975 5 1 0 19 ISAAC 16.0 332.5 17 650 +1951 12 4 6 15 JOYCE 67.1 99.7 109 588 +1999 9 17 6 1 DEBBY 62.8 43.4 126 118 +1971 11 17 6 10 HELENE 66.6 215.0 11 745 +2001 12 5 12 5 SANDY 48.6 179.2 136 339 +1976 5 10 12 4 ISAAC 11.4 287.0 51 752 +1988 9 13 0 20 ERNESTO 31.8 229.6 29 329 +1995 12 26 6 23 ALBERTO 31.2 215.2 59 551 +1985 8 24 0 28 OSCAR 29.1 171.4 110 876 +1958 6 16 0 16 FLORENCE 70.0 227.5 53 694 +1954 7 24 6 5 CHRIS 34.0 297.5 162 788 +1951 12 13 12 21 CHRIS 18.8 128.9 44 773 +1984 2 7 6 1 SANDY 60.9 299.1 142 851 +1996 5 15 6 9 VALERIE 61.6 176.8 35 293 +1987 11 13 6 21 TONY 14.5 221.8 65 57 +2000 4 24 0 19 ALBERTO 66.4 174.9 43 646 +1956 7 16 18 13 PATTY 49.3 129.6 23 578 +1989 12 13 12 5 HELENE 57.8 104.2 54 14 +1958 3 9 18 5 JOYCE 33.2 198.7 148 819 +1972 4 27 6 5 RAFAEL 13.2 110.9 47 182 +1960 11 28 0 25 WILLIAM 34.7 159.9 114 863 +2002 2 3 12 3 JOYCE 39.6 50.7 162 388 +1988 12 10 0 4 NADINE 65.9 124.8 154 814 +1950 3 3 18 6 PATTY 55.5 357.9 147 565 +2002 9 28 12 12 TONY 37.6 132.0 154 144 +1961 10 13 6 20 RAFAEL 47.9 280.7 106 364 +1967 5 6 12 14 HELENE 51.1 114.7 93 655 +1956 8 26 12 11 HELENE 49.8 227.3 149 480 +1976 6 15 6 27 HELENE 39.8 312.9 12 693 +1987 9 17 12 27 WILLIAM 58.1 336.7 66 298 +1971 6 4 0 9 FLORENCE 12.5 240.3 130 28 +1964 11 3 18 21 PATTY 58.3 339.3 116 577 +1952 8 14 6 8 NADINE 22.0 244.8 33 268 +1973 4 8 6 15 GORDON 53.7 323.7 91 642 +1999 9 14 12 25 NADINE 30.4 38.1 23 833 +1950 6 28 18 8 TONY 29.9 18.8 90 264 +1990 10 3 18 18 BERYL 10.5 137.6 107 231 +1966 10 6 18 19 LESLIE 58.2 277.5 159 268 +1965 9 8 0 24 LESLIE 37.9 161.4 162 496 +1980 3 25 0 13 FLORENCE 10.3 148.3 128 418 +1993 5 8 6 13 WILLIAM 8.3 336.0 11 104 +1967 7 14 12 14 HELENE 36.8 323.4 60 608 +1967 2 22 12 11 LESLIE 60.1 118.4 28 406 +1963 1 1 6 18 PATTY 26.6 53.3 108 150 +1967 6 25 18 14 DEBBY 67.9 253.9 29 449 +1968 6 8 6 25 CHRIS 51.0 339.7 40 268 +1956 11 25 18 5 DEBBY 49.5 48.7 75 105 +1990 3 17 18 23 BERYL 38.0 102.6 14 442 +1991 10 20 6 10 CHRIS 40.9 87.8 86 331 +2002 6 8 0 19 ALBERTO 62.5 356.5 133 487 +1958 10 25 0 6 LESLIE 57.7 151.3 66 733 +1996 4 22 6 25 LESLIE 33.4 76.0 69 380 +1992 10 27 18 19 MICHAEL 9.9 192.0 91 650 +1984 4 7 18 9 LESLIE 28.3 64.9 15 435 +1989 9 20 18 1 KIRK 22.7 98.0 35 92 +1963 12 21 6 6 HELENE 33.6 102.3 19 544 +1955 2 16 18 12 VALERIE 46.7 240.9 114 374 +1986 9 6 18 10 MICHAEL 14.5 300.7 14 11 +1999 11 14 0 24 LESLIE 50.1 253.5 110 78 +1971 5 24 6 11 TONY 33.1 120.5 51 681 +1991 6 4 6 6 MICHAEL 8.5 350.1 38 687 +1957 12 20 18 16 DEBBY 45.4 38.5 134 480 +1964 11 16 6 15 LESLIE 27.6 331.5 14 780 +1999 8 7 6 5 ERNESTO 34.8 17.2 21 582 +2002 9 12 18 10 DEBBY 47.7 318.3 79 786 +1991 3 21 0 5 DEBBY 56.3 95.8 29 874 +1972 7 23 6 10 MICHAEL 30.5 299.8 30 799 +1959 9 18 6 20 RAFAEL 22.7 3.4 141 447 +1996 1 4 18 3 WILLIAM 51.7 357.1 91 724 +1989 3 16 12 6 FLORENCE 17.2 115.7 149 108 +1982 11 12 12 3 JOYCE 69.4 129.6 10 693 +1954 6 19 6 25 JOYCE 45.5 65.8 158 276 +1956 5 19 12 15 JOYCE 40.4 251.1 11 401 +1994 3 22 18 20 OSCAR 52.6 259.0 126 218 +1988 8 24 18 21 JOYCE 66.8 214.6 139 277 +1953 10 24 12 11 NADINE 40.0 81.5 85 588 +1980 4 26 0 4 TONY 33.2 124.0 108 547 +1996 11 13 18 1 WILLIAM 28.3 180.3 62 58 +1992 9 22 0 2 JOYCE 51.7 29.6 69 510 +1952 2 3 0 8 JOYCE 11.2 335.3 129 299 +1953 8 27 12 27 MICHAEL 62.2 248.5 37 315 +1987 2 3 12 12 VALERIE 44.9 167.3 155 222 +1982 5 27 18 13 PATTY 24.8 64.3 37 662 +1970 3 20 6 9 SANDY 63.8 306.2 112 443 +1965 10 17 0 17 LESLIE 53.3 77.2 163 889 +1988 2 17 18 26 CHRIS 68.2 43.8 51 647 +1962 12 3 0 11 ISAAC 56.4 223.6 114 565 +1998 11 1 12 8 ALBERTO 55.8 48.8 59 645 +1992 3 11 0 27 ERNESTO 8.7 135.3 36 485 +1978 4 26 12 8 HELENE 55.0 326.8 161 301 +1962 11 8 18 7 MICHAEL 45.7 1.3 132 544 +1991 12 15 6 6 CHRIS 53.5 154.3 100 387 +1973 5 8 18 1 JOYCE 64.9 56.9 58 387 +2000 12 15 0 26 ERNESTO 35.6 49.9 95 210 +1962 9 1 6 1 OSCAR 24.0 354.7 65 194 +1965 5 27 12 9 ISAAC 40.6 43.8 43 397 +1991 5 2 18 8 HELENE 49.5 259.7 40 87 +1983 6 9 6 6 GORDON 43.0 111.4 106 205 +1950 12 17 6 8 HELENE 31.5 283.2 122 842 +1972 10 19 6 23 KIRK 60.6 291.5 131 888 +1980 7 8 12 20 DEBBY 16.2 284.1 36 279 +1988 6 9 12 18 ERNESTO 35.5 19.0 123 799 +1979 9 6 6 14 NADINE 31.3 189.0 107 285 +1999 6 7 12 25 FLORENCE 25.8 75.8 24 116 +1994 4 12 12 3 VALERIE 35.2 293.7 153 561 +1978 7 21 18 28 TONY 12.8 186.7 59 647 +2000 1 7 18 26 ERNESTO 20.0 317.6 106 353 +1987 6 18 6 1 ISAAC 7.0 281.2 132 234 +1965 7 12 12 18 BERYL 40.2 248.9 54 79 +1951 1 14 18 20 ERNESTO 28.6 293.5 147 683 +1957 8 6 18 6 TONY 22.1 132.9 80 365 +1986 5 28 12 4 MICHAEL 66.0 112.3 58 603 +1956 9 13 18 27 BERYL 36.7 213.3 32 386 +1982 11 12 12 4 ALBERTO 27.1 86.3 74 374 +1999 3 2 18 2 OSCAR 63.7 52.5 94 518 +1979 4 25 6 12 MICHAEL 61.3 108.2 23 777 +1978 12 13 0 7 PATTY 31.5 162.4 74 691 +1988 5 6 6 4 SANDY 50.4 99.8 24 804 +1963 6 2 12 17 BERYL 50.0 294.6 110 503 +1953 2 25 18 14 SANDY 34.9 173.9 54 696 +1960 3 25 18 27 CHRIS 33.9 152.6 133 290 +1992 1 2 12 25 PATTY 20.9 179.0 15 543 +2000 11 2 6 3 NADINE 36.4 240.8 56 308 +1986 11 27 0 4 TONY 48.7 335.2 67 372 +1966 6 10 6 8 JOYCE 17.4 111.4 61 261 +1973 2 10 0 11 BERYL 61.0 75.1 37 408 +1987 1 10 6 17 RAFAEL 20.2 310.8 51 241 +1975 3 28 18 17 TONY 44.9 274.2 126 234 +1988 7 20 12 18 ERNESTO 30.4 297.5 131 410 +1959 11 23 18 1 ALBERTO 45.9 37.3 104 423 +1968 12 21 18 26 TONY 26.1 280.9 73 637 +1965 12 25 18 25 JOYCE 33.2 184.1 31 179 +1967 2 12 18 22 KIRK 34.4 115.1 129 18 +1973 2 13 6 11 LESLIE 30.7 274.0 153 656 +1950 10 3 6 10 FLORENCE 53.6 194.8 158 650 +1980 4 19 12 11 ALBERTO 16.4 157.3 94 145 +1971 11 26 18 1 CHRIS 33.2 259.0 82 302 +1961 1 13 6 8 HELENE 47.8 108.8 45 155 +1960 4 27 12 18 SANDY 45.4 197.5 59 438 +1970 7 6 12 12 ERNESTO 52.5 49.2 120 872 +1992 5 25 12 2 SANDY 67.0 310.1 28 271 +1966 12 3 0 28 SANDY 13.7 113.5 100 790 +1977 9 23 6 22 JOYCE 30.2 43.6 139 729 +1980 4 11 12 12 JOYCE 62.9 190.2 102 352 +1990 10 21 18 9 LESLIE 24.6 1.5 62 864 +1992 9 24 18 22 BERYL 7.1 156.6 72 647 +1987 5 18 0 9 OSCAR 67.0 96.6 43 849 +1972 11 11 0 23 NADINE 8.9 12.7 77 410 +1972 7 12 6 10 VALERIE 58.8 57.6 23 239 +1987 7 13 6 4 SANDY 13.0 254.8 76 236 +1963 5 16 6 17 SANDY 51.7 279.1 13 216 +1963 7 10 6 12 PATTY 39.0 33.9 49 536 +1957 11 4 12 7 RAFAEL 15.7 15.2 109 627 +1979 8 13 12 2 LESLIE 63.8 220.5 49 719 +1986 5 27 0 22 NADINE 30.4 41.4 107 364 +1971 12 20 12 10 ALBERTO 53.4 40.8 148 467 +1999 2 27 18 11 HELENE 55.1 337.2 65 856 +1951 11 10 6 23 VALERIE 51.2 336.3 54 621 +2002 9 22 6 2 FLORENCE 43.7 185.5 89 639 +1988 10 10 0 15 OSCAR 11.4 331.3 102 784 +1975 4 22 0 20 DEBBY 22.6 57.2 64 539 +1998 1 20 0 24 GORDON 57.3 317.0 38 582 +1966 6 9 6 4 NADINE 31.0 332.4 144 93 +1961 9 13 6 20 RAFAEL 61.2 271.5 143 702 +1979 8 8 18 13 WILLIAM 9.6 179.9 155 641 +1997 12 5 12 19 DEBBY 37.7 193.2 33 591 +1950 1 14 18 1 RAFAEL 29.5 71.4 70 819 +1969 5 16 12 27 ALBERTO 36.9 114.5 41 94 +1997 6 5 6 6 VALERIE 31.0 117.1 21 383 +1977 6 3 12 11 OSCAR 12.8 155.6 65 632 +1996 12 4 12 15 DEBBY 44.4 116.5 115 231 +1952 11 5 18 5 GORDON 23.2 330.9 145 280 +1968 7 23 18 4 KIRK 27.0 140.6 135 409 +1950 4 22 6 20 KIRK 39.7 335.0 164 518 +1968 1 2 18 6 KIRK 60.3 291.4 98 744 +1957 11 27 18 6 JOYCE 13.0 241.5 107 812 +1995 6 12 18 11 LESLIE 17.1 72.9 109 703 +1972 4 16 18 2 TONY 20.8 112.5 19 537 +1957 3 26 0 17 PATTY 66.7 198.7 137 670 +1996 4 27 18 3 OSCAR 51.0 293.7 58 878 +1992 8 5 0 17 ISAAC 55.9 33.8 44 359 +1985 5 6 12 25 JOYCE 8.3 317.9 44 283 +2000 9 1 12 23 OSCAR 40.3 146.6 32 563 +1967 9 11 6 9 RAFAEL 29.4 242.2 93 462 +1964 9 24 0 4 ERNESTO 50.0 56.4 16 54 +1963 11 17 12 3 HELENE 35.5 343.2 96 755 +1955 2 10 18 28 GORDON 24.1 294.4 42 569 +1991 4 7 12 4 VALERIE 43.7 228.0 20 885 +1993 10 18 18 10 BERYL 14.4 52.8 82 311 +1953 12 18 0 5 PATTY 47.4 339.7 70 458 +1973 1 10 18 10 JOYCE 62.1 351.1 131 804 +1955 9 19 0 1 NADINE 25.6 250.5 136 464 +1999 1 19 6 28 KIRK 17.7 293.6 26 352 +1970 4 15 6 10 JOYCE 8.4 173.6 60 855 +1988 10 3 0 15 TONY 65.1 148.8 114 764 +2003 9 12 0 26 NADINE 50.7 337.5 33 102 +1979 6 24 6 1 ERNESTO 15.2 29.0 65 617 +1979 6 14 18 9 KIRK 48.3 315.9 12 520 +1986 4 20 12 19 GORDON 36.3 250.3 84 724 +1996 6 2 0 17 GORDON 13.8 200.3 80 146 +1998 7 1 0 26 CHRIS 11.7 189.2 32 695 +1975 5 8 12 12 GORDON 40.5 161.6 103 709 +2002 3 9 0 26 LESLIE 10.4 7.7 138 186 +1953 4 21 6 16 PATTY 59.2 182.4 31 327 +1975 4 9 6 16 NADINE 42.9 144.8 30 243 +1958 12 7 18 22 JOYCE 67.9 72.8 109 543 +1960 1 22 6 12 LESLIE 66.2 90.0 46 771 +1982 3 8 18 26 VALERIE 22.2 205.7 160 564 +1955 4 23 12 13 DEBBY 46.5 212.3 108 709 +1982 12 21 0 28 SANDY 13.8 45.4 64 892 +1983 4 13 6 1 HELENE 13.6 152.4 101 126 +1969 7 17 0 26 JOYCE 58.0 101.8 39 185 +1991 5 18 12 28 CHRIS 28.6 356.3 139 472 +1998 6 27 18 2 GORDON 26.7 147.5 47 3 +1975 7 1 6 2 DEBBY 14.6 160.0 125 805 +1961 9 28 12 16 FLORENCE 20.0 45.8 94 580 +1975 1 5 6 19 LESLIE 59.6 129.2 68 488 +1969 3 21 6 19 SANDY 30.8 109.5 10 110 +1992 1 11 18 6 ISAAC 20.5 209.8 39 815 +1956 8 26 0 13 WILLIAM 38.7 237.3 10 401 +1951 12 5 18 26 CHRIS 38.8 244.8 44 767 +2002 1 13 6 17 TONY 65.8 11.7 45 897 +1984 11 21 12 25 PATTY 7.6 12.2 77 226 +1972 9 16 0 28 TONY 38.1 44.9 95 764 +1977 10 18 18 21 RAFAEL 49.5 131.9 63 501 +1988 6 10 12 2 ISAAC 27.0 274.6 81 239 +2002 11 7 0 18 KIRK 13.6 68.8 133 160 +1971 3 12 0 8 HELENE 23.4 305.1 27 848 +1978 5 9 12 21 ALBERTO 32.9 158.2 80 331 +1970 5 19 12 22 GORDON 8.2 6.0 136 102 +1986 12 1 12 26 BERYL 13.7 202.7 21 277 +2004 1 14 0 24 PATTY 11.2 16.8 56 416 +2001 10 6 6 12 TONY 28.0 197.2 47 35 +1959 3 20 0 18 ISAAC 55.8 179.7 93 613 +1996 11 23 18 17 WILLIAM 43.9 301.0 20 374 +2003 5 13 0 5 FLORENCE 40.2 49.6 14 320 +1970 3 24 6 26 ALBERTO 30.4 148.6 109 473 +1968 2 25 12 23 CHRIS 62.1 212.0 64 281 +1972 10 19 6 8 SANDY 48.1 147.9 51 839 +1976 8 14 12 9 PATTY 42.8 176.0 124 79 +1973 4 25 6 9 FLORENCE 65.1 8.8 121 390 +1999 9 10 6 13 ISAAC 57.6 226.8 137 774 +1958 9 23 12 5 BERYL 24.3 343.8 124 15 +1986 12 15 6 9 JOYCE 69.6 250.7 131 414 +1991 5 2 6 23 KIRK 60.7 32.2 133 430 +1965 11 7 0 24 ALBERTO 65.4 179.1 103 831 +1952 2 15 6 7 ERNESTO 58.0 21.3 147 889 +1969 2 5 6 28 WILLIAM 11.2 81.0 108 598 +1958 10 13 6 16 ISAAC 57.3 84.3 158 290 +1958 1 4 6 10 PATTY 48.2 340.8 46 861 +1990 10 3 0 25 WILLIAM 54.0 272.8 147 503 +1984 12 6 6 6 TONY 60.2 267.6 146 394 +1972 7 3 6 26 CHRIS 8.4 139.4 60 193 +1965 5 24 0 8 VALERIE 45.3 309.4 86 555 +2003 1 11 18 7 TONY 48.5 16.2 160 430 +1985 10 5 12 23 BERYL 63.6 62.0 45 649 +1976 10 22 18 11 NADINE 57.3 334.9 76 432 +1957 6 6 12 27 ALBERTO 40.3 177.4 112 276 +1995 5 7 6 8 VALERIE 51.6 344.4 157 772 +1968 6 1 6 10 HELENE 29.4 271.1 61 291 +2004 11 7 0 24 TONY 12.3 126.9 93 741 +1960 2 11 12 6 ALBERTO 48.1 147.0 69 524 +1958 7 25 6 18 PATTY 46.8 84.0 25 547 +1988 6 10 18 21 SANDY 34.2 4.3 24 577 +1994 6 6 18 22 KIRK 50.7 199.8 15 180 +1980 7 9 12 17 TONY 65.5 340.6 88 274 +1964 3 15 18 2 KIRK 45.0 82.2 20 563 +1968 10 16 12 10 MICHAEL 35.0 43.7 151 703 +2004 12 2 12 11 SANDY 24.4 16.3 147 61 +1952 1 3 6 15 PATTY 64.8 214.3 154 281 +1956 3 21 18 19 TONY 65.8 325.4 37 668 +1970 2 6 12 17 TONY 65.7 15.4 15 323 +1978 5 25 6 20 GORDON 65.6 22.9 47 556 +1956 7 16 18 11 DEBBY 27.8 301.1 120 97 +1956 10 13 12 12 CHRIS 8.4 156.3 101 848 +1966 5 5 6 5 GORDON 59.2 72.6 78 332 +1963 8 26 12 20 BERYL 19.1 317.9 155 40 +1999 6 17 6 16 WILLIAM 17.8 48.8 23 586 +1966 9 12 12 6 RAFAEL 52.3 111.4 35 499 +1990 8 24 0 28 CHRIS 67.6 223.7 12 415 +1998 10 10 0 11 BERYL 67.0 120.4 89 445 +1996 1 16 6 17 TONY 54.6 21.4 89 164 +1969 2 25 6 6 MICHAEL 57.3 202.8 77 32 +1969 2 12 12 24 BERYL 46.8 269.9 46 54 +2003 10 19 12 22 ALBERTO 23.5 41.6 125 741 +1969 2 25 6 3 JOYCE 10.0 303.8 15 108 +1981 6 2 0 21 TONY 15.1 294.1 89 377 +1992 7 25 12 2 JOYCE 9.2 353.8 29 672 +1992 9 17 6 7 VALERIE 47.2 90.0 135 827 +1985 7 17 6 7 ERNESTO 69.8 80.7 27 764 +1992 7 6 0 18 ERNESTO 24.7 320.3 18 702 +1994 8 27 6 3 PATTY 44.8 13.9 45 792 +1998 11 2 0 13 GORDON 58.2 166.5 58 887 +1972 7 1 0 11 ISAAC 51.4 46.8 25 532 +1959 12 4 6 1 JOYCE 42.3 101.1 10 533 +1977 3 4 0 20 PATTY 8.8 122.8 25 243 +1954 7 20 6 12 SANDY 69.7 240.1 94 473 +1960 3 8 0 2 SANDY 64.3 339.3 100 782 +1955 9 10 18 13 HELENE 39.7 224.1 59 327 +1950 2 28 18 2 FLORENCE 22.0 260.0 34 559 +1983 6 4 18 11 ISAAC 44.6 177.6 163 111 +1955 10 16 0 4 MICHAEL 50.2 265.7 15 770 +1957 3 16 6 22 ALBERTO 55.7 285.0 92 759 +1965 4 12 12 23 SANDY 14.5 196.8 75 503 +1994 8 26 6 19 GORDON 23.7 259.1 27 130 +1979 4 9 18 24 JOYCE 45.2 257.7 16 207 +1954 11 14 6 27 GORDON 60.2 355.7 136 369 +1951 8 27 12 14 CHRIS 46.2 154.4 44 328 +1996 5 19 0 3 SANDY 60.6 1.3 79 879 +2001 9 15 0 3 CHRIS 56.5 308.3 58 298 +1981 10 10 12 23 KIRK 9.5 314.0 78 618 +1972 9 2 0 14 HELENE 34.6 98.1 69 38 +2001 1 18 0 2 SANDY 62.5 308.5 143 714 +1972 11 21 0 28 TONY 60.3 118.5 126 343 +1971 4 10 0 2 NADINE 16.8 210.9 100 713 +1988 3 24 18 3 RAFAEL 10.5 258.9 30 693 +1960 9 17 6 16 CHRIS 33.6 254.7 41 715 +2002 8 4 0 28 OSCAR 41.7 6.8 123 284 +2001 4 15 18 17 ALBERTO 38.8 191.3 114 407 +2000 1 23 12 26 HELENE 40.8 259.5 52 653 +1974 5 20 18 6 ERNESTO 30.4 184.8 128 432 +1960 11 1 0 24 GORDON 65.7 255.2 149 734 +1970 3 13 12 16 TONY 19.1 336.0 129 688 +1975 3 11 18 28 ISAAC 60.2 148.7 95 305 +1953 1 6 6 27 KIRK 37.9 285.6 40 12 +1965 9 12 12 3 KIRK 33.9 350.2 64 547 +1954 2 17 12 22 SANDY 29.7 249.9 133 480 +1996 4 12 0 21 MICHAEL 62.1 204.6 82 322 +1995 5 13 6 18 HELENE 38.9 333.5 110 321 +1955 3 24 18 28 MICHAEL 20.3 190.6 133 242 +1989 11 22 12 18 OSCAR 36.9 230.5 46 793 +1962 6 19 18 3 TONY 38.1 21.8 72 506 +1980 12 1 18 3 MICHAEL 55.5 98.2 115 274 +1980 9 6 12 26 KIRK 34.4 211.7 18 269 +1991 5 11 12 20 NADINE 46.2 135.1 132 411 +1950 10 5 0 5 VALERIE 22.9 259.7 62 752 +1981 10 22 18 7 WILLIAM 31.6 243.8 108 564 +2002 4 26 12 9 RAFAEL 19.5 108.1 54 439 +1976 3 27 0 2 MICHAEL 59.5 6.9 13 603 +1995 7 5 6 10 ALBERTO 28.9 2.7 140 427 +1978 3 16 12 21 LESLIE 12.0 353.8 68 422 +2001 7 12 18 17 GORDON 52.7 66.9 30 771 +1993 3 22 18 1 LESLIE 60.8 236.2 100 337 +1966 4 11 6 3 OSCAR 13.2 338.1 23 866 +1961 10 2 12 16 LESLIE 48.9 76.5 123 52 +1950 7 25 6 13 ISAAC 44.8 253.7 25 695 +1995 10 5 18 5 GORDON 64.0 258.0 49 312 +1988 8 10 0 27 NADINE 58.2 43.1 22 339 +1950 4 17 6 9 VALERIE 66.8 61.3 69 500 +1991 2 17 6 13 PATTY 59.7 165.7 30 724 +1995 7 28 18 16 PATTY 44.9 4.0 85 624 +1963 11 15 0 8 MICHAEL 37.0 208.6 71 68 +2003 12 21 0 27 RAFAEL 21.0 261.5 77 27 +1978 9 7 0 20 PATTY 39.0 105.9 71 564 +1951 6 17 6 11 SANDY 14.3 66.8 143 14 +2000 9 5 12 17 VALERIE 56.1 198.4 24 861 +1986 1 19 6 4 LESLIE 40.1 6.1 34 510 +1982 7 16 12 8 MICHAEL 61.1 58.1 158 504 +1969 3 1 0 15 MICHAEL 10.6 326.3 163 351 +1995 9 28 18 23 RAFAEL 14.9 28.1 160 342 +1984 12 13 0 9 JOYCE 7.1 34.4 149 690 +1980 8 13 0 4 TONY 62.1 204.4 24 810 +1995 7 7 12 3 ERNESTO 49.9 175.5 64 105 +1982 7 8 12 11 DEBBY 43.0 258.9 90 47 +1970 4 18 6 19 OSCAR 24.0 199.2 18 666 +1980 2 1 0 7 WILLIAM 67.7 271.6 141 156 +1991 5 27 6 3 MICHAEL 31.3 310.0 163 843 +1970 4 2 18 21 ISAAC 20.6 68.7 147 178 +1959 9 24 12 1 BERYL 59.0 263.9 44 493 +1965 5 1 12 27 SANDY 61.8 43.2 151 200 +1963 6 28 6 28 GORDON 45.1 329.1 81 376 +1953 8 14 12 1 ERNESTO 48.8 254.9 23 446 +1992 11 1 0 6 OSCAR 64.5 330.5 110 337 +1952 1 5 12 4 CHRIS 64.9 315.9 149 677 +1950 8 20 0 20 RAFAEL 13.6 12.3 133 655 +1978 9 10 6 16 WILLIAM 15.7 161.6 114 265 +1987 7 24 12 2 SANDY 11.9 200.3 139 254 +1992 10 27 6 25 HELENE 47.7 156.4 27 285 +1989 4 12 6 23 WILLIAM 50.3 53.7 134 555 +1989 7 17 12 26 LESLIE 57.6 187.3 105 279 +1973 12 20 12 18 PATTY 55.7 89.4 46 234 +1973 4 18 0 25 KIRK 22.1 57.0 33 691 +1971 8 9 12 7 GORDON 21.8 161.5 145 354 +1975 6 28 0 17 ALBERTO 52.0 10.0 119 116 +1973 8 2 0 12 DEBBY 19.1 63.9 137 793 +1952 6 13 18 3 VALERIE 49.0 94.4 44 326 +1971 5 7 6 17 ALBERTO 68.3 21.9 136 101 +1986 4 20 12 11 BERYL 69.0 212.5 124 306 +1984 11 26 18 28 OSCAR 51.2 136.1 134 828 +1963 1 16 18 20 BERYL 45.4 197.1 133 360 +1983 5 17 12 17 TONY 16.4 274.4 37 121 +1998 11 23 6 22 ERNESTO 61.8 177.0 146 435 +1955 11 10 0 6 MICHAEL 29.9 50.7 107 534 +1978 11 17 0 5 ALBERTO 43.4 324.4 123 724 +1996 2 24 18 22 VALERIE 34.3 139.2 92 636 +1989 6 16 18 3 PATTY 68.2 273.5 11 423 +1974 6 14 0 6 TONY 46.8 282.5 107 755 +1966 3 13 18 27 LESLIE 42.6 244.6 65 169 +1976 12 18 12 26 TONY 58.1 230.0 21 755 +1988 5 25 12 20 TONY 9.9 102.1 23 360 +1999 8 16 6 14 WILLIAM 48.4 219.9 37 478 +1984 5 18 12 28 NADINE 53.2 98.2 141 32 +1952 11 9 0 17 OSCAR 64.4 136.8 10 260 +1969 6 25 18 17 HELENE 24.9 171.8 150 222 +2002 10 10 18 28 FLORENCE 67.2 134.1 14 604 +1957 7 12 6 4 ALBERTO 38.9 218.6 77 92 +1995 10 14 18 24 MICHAEL 56.2 255.8 128 168 +1976 4 26 6 7 KIRK 67.9 203.3 61 20 +1991 12 14 18 9 KIRK 68.4 320.1 49 897 +1982 3 3 6 21 RAFAEL 53.9 266.8 152 225 +1966 12 7 12 25 HELENE 59.7 87.4 107 751 +1963 2 17 12 23 ISAAC 50.9 211.7 85 163 +1961 6 1 18 1 ISAAC 19.7 334.5 74 442 +1950 10 22 6 17 DEBBY 44.0 14.4 24 682 +1996 6 22 6 23 BERYL 36.4 111.0 145 358 +1983 3 24 6 25 ISAAC 45.2 43.9 81 571 +1998 4 24 0 17 SANDY 45.2 256.8 19 217 +2004 9 9 18 18 JOYCE 66.5 18.7 75 348 +1957 10 3 18 7 ERNESTO 34.4 338.6 113 765 +2003 9 16 12 28 DEBBY 19.9 303.9 95 892 +2004 1 1 6 22 FLORENCE 51.6 224.9 105 178 +1964 11 20 0 21 FLORENCE 42.1 157.6 64 824 +1971 6 13 18 1 OSCAR 42.9 188.1 27 585 +2000 12 23 12 23 ISAAC 55.9 241.3 111 481 +1992 5 14 6 26 ERNESTO 45.7 174.5 102 212 +1967 12 22 12 3 ERNESTO 36.7 176.8 89 356 +1984 7 15 6 11 TONY 50.2 269.8 153 718 +1995 11 4 0 21 VALERIE 64.4 334.8 24 684 +1984 1 10 0 15 KIRK 13.7 272.6 148 484 +1960 8 23 6 8 ALBERTO 20.5 110.3 65 9 +1987 2 24 18 28 JOYCE 57.9 204.2 66 138 +1976 4 17 12 7 DEBBY 22.1 39.3 95 95 +1952 5 11 0 3 RAFAEL 59.0 135.9 160 835 +1986 12 25 0 9 ISAAC 30.2 261.1 88 176 +1994 11 20 18 4 MICHAEL 49.4 267.8 50 714 +1971 8 3 12 17 BERYL 32.3 223.1 10 269 +1972 12 11 12 11 ALBERTO 43.6 226.7 69 335 +1985 12 6 0 24 MICHAEL 14.9 331.6 49 251 +1996 7 5 12 13 OSCAR 60.3 178.3 90 723 +1955 10 6 0 3 NADINE 41.2 57.5 147 712 +1992 5 20 0 9 OSCAR 48.8 250.1 23 15 +1962 5 1 6 28 LESLIE 13.1 224.4 71 106 +1980 8 21 0 21 KIRK 56.6 61.1 34 596 +1968 11 15 12 27 KIRK 17.2 57.8 25 754 +1953 2 18 0 27 JOYCE 44.4 103.2 111 781 +2001 12 24 6 24 ALBERTO 41.6 331.8 47 889 +1981 8 5 6 22 VALERIE 37.4 107.3 129 808 +1956 1 23 18 12 OSCAR 27.9 112.5 114 491 +1994 5 24 18 13 TONY 8.1 2.5 35 761 +1962 3 12 12 11 ISAAC 54.4 165.1 127 697 +1991 9 7 6 24 VALERIE 20.5 232.5 28 70 +1953 1 21 6 21 LESLIE 28.6 287.5 84 27 +2000 3 21 0 4 OSCAR 43.9 79.5 93 763 +1964 2 12 18 26 HELENE 24.7 74.6 52 499 +1955 6 1 6 23 JOYCE 18.5 9.7 50 606 +1990 11 11 18 14 KIRK 40.7 164.6 31 861 +2002 3 16 12 20 ERNESTO 26.8 8.7 65 409 +1971 10 7 6 18 LESLIE 9.7 175.6 98 138 +1973 12 10 6 2 LESLIE 33.8 275.0 35 600 +1994 6 1 6 8 CHRIS 32.0 267.9 97 867 +1972 3 17 0 1 RAFAEL 47.0 55.6 142 650 +1998 9 8 18 2 TONY 47.9 229.7 16 618 +1984 5 9 12 10 ERNESTO 38.7 269.3 19 525 +1985 9 11 0 21 NADINE 45.4 185.4 19 865 +1973 11 26 18 15 CHRIS 14.9 318.9 135 805 +1973 10 18 12 8 GORDON 44.1 46.3 58 158 +2003 1 26 0 14 HELENE 56.8 61.4 67 459 +1954 2 22 12 7 KIRK 51.1 83.3 103 838 +1979 5 25 12 3 KIRK 22.7 268.0 137 415 +1977 6 9 6 21 MICHAEL 30.6 260.1 37 327 +1981 9 3 18 2 VALERIE 26.0 223.4 49 285 +1977 12 25 18 18 TONY 41.3 95.0 46 889 +1996 8 28 18 2 BERYL 15.7 335.3 43 706 +1957 12 16 12 18 NADINE 15.3 230.6 134 875 +1966 6 5 6 21 ALBERTO 65.6 161.9 135 128 +1972 12 7 18 8 PATTY 25.9 270.8 146 231 +1958 6 19 12 2 GORDON 9.9 302.0 13 533 +2000 7 28 0 17 HELENE 14.3 116.6 136 136 +1982 9 3 18 22 CHRIS 11.5 184.6 26 630 +1964 5 13 12 11 CHRIS 7.2 345.9 95 885 +1963 8 5 0 3 TONY 47.7 22.1 150 135 +2003 3 14 12 4 CHRIS 27.7 291.3 126 731 +1984 6 23 6 16 OSCAR 59.6 8.6 20 678 +1991 12 15 18 6 VALERIE 15.3 211.1 80 778 +1977 11 3 6 8 WILLIAM 25.9 25.9 112 40 +1973 4 24 18 23 WILLIAM 65.9 219.1 54 339 +2002 6 15 0 17 KIRK 27.7 233.4 24 618 +1983 6 10 6 20 CHRIS 67.2 281.9 37 691 +1952 1 8 6 5 OSCAR 59.1 104.8 163 283 +1959 4 28 12 20 FLORENCE 41.2 232.4 68 154 +1974 6 1 18 15 RAFAEL 30.6 222.1 27 718 +1963 4 28 12 22 TONY 42.5 177.6 125 226 +1975 11 18 0 20 BERYL 65.7 283.3 40 25 +1966 1 16 18 27 LESLIE 10.9 45.4 33 431 +1974 2 8 6 22 NADINE 54.6 336.6 23 96 +1990 10 15 12 28 PATTY 55.9 14.9 39 842 +1951 11 13 18 8 GORDON 56.3 337.4 81 83 +1999 12 15 0 1 TONY 41.1 104.3 135 833 +1991 2 7 6 5 ISAAC 40.7 210.9 156 691 +1994 7 6 12 1 WILLIAM 45.4 163.3 163 167 +1958 8 20 12 10 KIRK 40.9 187.6 149 257 +2001 9 12 0 10 ALBERTO 45.1 40.4 117 398 +1994 7 22 18 2 RAFAEL 30.7 10.0 21 2 +1968 5 22 0 7 RAFAEL 48.7 88.4 99 559 +1985 3 26 12 3 RAFAEL 19.4 37.1 139 485 +1977 10 24 18 12 WILLIAM 61.8 244.2 57 810 +1987 8 22 6 5 LESLIE 21.5 167.7 135 316 +1979 7 20 12 8 RAFAEL 28.9 123.2 74 330 +1954 11 25 12 1 BERYL 18.0 283.0 37 690 +1978 10 11 12 24 FLORENCE 68.5 16.9 33 157 +1958 5 24 12 27 SANDY 15.4 273.0 105 738 +1978 12 19 6 9 FLORENCE 7.3 312.2 93 819 +1996 3 6 18 9 SANDY 10.9 94.4 136 832 +1985 2 2 18 19 RAFAEL 46.0 58.8 155 175 +1955 4 13 18 21 GORDON 14.6 211.8 13 447 +1997 7 23 0 16 PATTY 26.8 162.4 11 367 +1968 6 6 0 6 TONY 38.3 167.4 64 600 +1956 8 7 18 16 OSCAR 22.2 210.3 138 697 +1980 12 18 18 14 KIRK 8.2 288.5 146 451 +1972 3 1 18 18 SANDY 46.2 111.7 82 514 +2003 3 25 18 23 KIRK 32.0 204.3 17 156 +1957 8 24 18 20 BERYL 28.1 52.3 10 517 +1990 3 24 12 4 ALBERTO 58.1 230.3 77 664 +1994 4 3 12 1 BERYL 50.6 324.5 37 621 +1972 5 17 18 4 OSCAR 31.5 131.2 119 892 +1982 6 10 6 3 ALBERTO 13.3 240.4 69 420 +1961 12 19 6 17 MICHAEL 30.8 340.7 161 736 +1990 1 19 18 13 ALBERTO 55.4 156.4 160 466 +1965 8 1 6 28 ISAAC 18.0 129.7 32 24 +1989 8 25 6 23 CHRIS 12.1 88.1 28 516 +1966 1 9 12 22 ISAAC 66.9 21.0 144 605 +1957 3 28 0 16 DEBBY 45.3 208.3 141 577 +1986 10 15 0 2 ERNESTO 67.5 245.6 149 896 +1993 3 8 0 4 OSCAR 28.9 324.1 21 385 +1999 10 2 18 2 DEBBY 15.0 115.1 80 668 +1977 3 12 18 8 RAFAEL 39.6 180.9 30 319 +1999 1 24 12 10 TONY 13.5 34.1 97 194 +1972 5 24 6 7 KIRK 7.2 61.1 78 74 +1967 3 17 12 19 DEBBY 26.0 264.3 160 175 +1988 8 22 0 24 DEBBY 45.8 174.1 125 896 +1981 12 24 6 13 ALBERTO 34.9 20.1 40 122 +1985 10 13 0 10 ALBERTO 38.8 161.0 112 454 +1961 11 20 0 17 ISAAC 8.1 21.7 78 633 +1985 8 24 18 24 PATTY 39.8 342.0 52 201 +1986 10 7 18 19 PATTY 20.1 347.8 136 209 +2002 11 12 0 28 CHRIS 35.5 187.7 72 790 +1989 7 4 6 24 FLORENCE 48.0 20.1 16 544 +1977 2 26 0 15 KIRK 49.2 255.1 79 364 +1958 9 11 18 6 ALBERTO 23.0 56.6 64 572 +1980 12 17 18 9 OSCAR 66.1 122.4 74 884 +1963 10 23 6 27 WILLIAM 40.7 30.0 115 529 +1989 1 9 18 17 RAFAEL 55.0 241.4 20 235 +1961 1 3 12 18 WILLIAM 23.0 248.2 159 190 +1964 1 10 0 25 WILLIAM 49.1 160.9 68 320 +1958 6 23 6 21 ISAAC 59.9 4.7 52 815 +1995 6 13 6 10 HELENE 48.7 153.5 20 556 +1991 1 8 6 11 NADINE 33.1 56.3 17 414 +1967 10 28 0 5 GORDON 19.2 304.7 78 44 +2002 10 15 18 7 ERNESTO 39.0 27.8 79 603 +1981 11 21 6 22 FLORENCE 22.1 213.4 137 611 +1953 1 5 12 17 ISAAC 30.3 283.7 144 874 +1993 3 18 12 25 ISAAC 64.2 275.0 84 545 +1977 12 18 12 23 ERNESTO 18.3 131.2 153 705 +1966 12 6 12 24 TONY 38.5 310.5 73 698 +1984 9 26 0 18 HELENE 36.8 151.4 139 739 +1954 8 14 0 1 MICHAEL 62.2 30.3 38 832 +2004 11 21 12 13 MICHAEL 18.7 347.3 118 252 +1990 3 18 6 13 CHRIS 26.3 240.0 155 879 +1994 7 4 18 11 FLORENCE 40.4 51.0 114 360 +1979 6 5 6 13 PATTY 18.0 349.1 148 711 +1988 6 4 6 7 FLORENCE 31.0 350.6 34 364 +1983 7 3 0 15 CHRIS 23.0 142.9 97 172 +1952 1 9 6 8 RAFAEL 28.2 191.0 77 888 +1962 5 18 12 9 JOYCE 56.0 225.4 56 473 +1985 11 6 6 20 SANDY 18.7 333.4 70 546 +1969 3 1 12 23 KIRK 44.9 305.9 31 311 +1995 1 17 18 14 BERYL 53.7 147.6 124 262 +1984 1 16 0 19 RAFAEL 11.0 26.1 53 834 +1964 7 14 6 11 HELENE 7.8 180.1 95 851 +1972 10 6 6 7 GORDON 42.9 67.1 135 507 +1991 12 10 0 11 ISAAC 60.7 120.5 146 630 +1969 2 17 0 14 ERNESTO 66.9 142.7 39 884 +1969 12 5 12 23 BERYL 52.5 167.3 22 629 +1976 7 22 6 27 GORDON 55.2 141.6 37 212 +1982 4 15 12 13 PATTY 35.4 345.9 108 575 +1989 7 22 6 15 CHRIS 46.9 240.6 47 180 +1995 4 9 0 23 SANDY 18.3 318.0 72 232 +1995 7 23 12 18 RAFAEL 38.9 69.5 139 127 +1957 4 19 6 28 ALBERTO 52.0 219.1 65 303 +1952 6 2 18 5 PATTY 30.8 310.2 130 797 +1964 5 1 12 16 NADINE 65.8 1.0 51 848 +1975 6 13 0 1 JOYCE 9.8 195.2 157 507 +1971 6 2 18 4 RAFAEL 13.7 21.3 154 860 +2001 2 23 18 6 JOYCE 30.5 221.4 50 515 +1978 10 19 0 15 ALBERTO 60.8 123.3 70 869 +1967 5 18 12 18 JOYCE 9.8 167.7 64 315 +1959 10 16 0 25 DEBBY 8.8 47.3 33 780 +1964 6 14 18 14 NADINE 27.9 286.7 152 327 +1987 11 27 18 11 ISAAC 44.4 173.6 140 206 +1977 5 20 0 14 NADINE 9.1 242.3 94 783 +1972 7 11 12 20 FLORENCE 62.3 233.2 131 527 +1965 8 8 12 2 ALBERTO 63.5 204.8 129 269 +1966 9 5 12 22 PATTY 49.4 274.7 37 544 +2000 9 22 18 13 CHRIS 33.3 44.8 22 15 +1968 4 12 12 23 MICHAEL 55.6 73.3 15 681 +1971 12 15 18 20 SANDY 17.3 109.1 82 338 +1975 1 8 6 20 ALBERTO 65.4 343.6 120 771 +1977 5 23 18 5 GORDON 57.6 37.9 156 211 +1996 3 18 6 28 PATTY 14.7 175.2 55 590 +1953 6 8 6 19 LESLIE 59.7 55.7 143 220 +1995 7 4 12 21 TONY 36.9 177.8 35 328 +1998 5 4 0 7 BERYL 26.0 121.3 31 255 +1970 4 10 0 15 PATTY 60.4 3.2 133 701 +1969 6 18 18 5 TONY 19.4 352.4 109 696 +2002 8 15 6 1 GORDON 54.1 39.8 93 163 +1964 7 2 12 27 ISAAC 33.1 66.1 43 658 +1966 9 8 12 25 ERNESTO 48.7 151.4 72 540 +1995 10 26 18 24 GORDON 21.7 208.8 41 636 +1984 6 22 18 3 TONY 65.6 316.3 92 810 +1965 11 15 6 4 ERNESTO 58.7 268.0 21 130 +1987 5 3 0 21 WILLIAM 42.5 84.6 68 748 +1980 4 11 18 17 HELENE 18.1 91.7 102 352 +1965 10 19 6 17 KIRK 69.4 146.6 117 605 +1954 5 27 6 4 FLORENCE 49.1 10.5 99 527 +1987 1 14 18 12 BERYL 55.6 125.0 22 7 +1953 8 3 18 22 ALBERTO 52.9 184.1 13 637 +1991 8 10 0 24 KIRK 48.3 257.9 110 803 +1958 10 25 6 20 OSCAR 7.8 0.5 57 540 +1985 10 5 0 8 JOYCE 27.8 253.0 19 736 +1975 2 22 6 11 FLORENCE 35.5 84.0 76 535 +1963 12 10 18 20 ALBERTO 20.8 335.1 49 746 +1963 11 25 12 25 VALERIE 20.5 17.1 132 94 +1987 1 16 12 26 KIRK 40.7 355.6 153 80 +1989 1 13 18 24 FLORENCE 19.6 191.0 84 115 +1975 3 7 18 7 BERYL 60.6 150.2 90 480 +1982 8 7 12 10 ISAAC 66.4 203.4 80 446 +1990 11 24 18 8 NADINE 20.8 95.8 17 223 +1986 12 28 6 16 GORDON 33.2 203.9 74 51 +1955 10 17 6 13 ALBERTO 15.9 9.2 72 138 +1968 11 26 18 3 VALERIE 31.8 214.7 66 429 +1965 4 11 6 7 SANDY 64.3 100.5 61 299 +2004 1 12 0 24 LESLIE 65.7 41.5 39 67 +1984 3 9 12 17 FLORENCE 48.8 211.8 21 27 +1973 9 12 6 18 VALERIE 66.6 223.4 40 864 +1978 7 7 0 7 RAFAEL 68.2 91.8 53 393 +1970 2 13 0 4 LESLIE 69.1 17.7 147 566 +1951 9 22 0 17 VALERIE 21.7 102.1 131 492 +1977 7 20 12 7 RAFAEL 35.4 217.8 51 268 +1999 1 7 12 24 FLORENCE 47.9 289.0 109 549 +1990 5 17 0 8 CHRIS 20.4 112.5 164 332 +1970 4 26 0 24 FLORENCE 63.7 207.5 143 666 +1991 4 22 6 6 ERNESTO 33.4 85.7 88 425 +1976 1 23 6 8 OSCAR 50.4 122.9 106 527 +1983 5 16 0 7 BERYL 25.4 139.9 79 771 +1953 8 7 18 19 DEBBY 13.4 72.2 20 221 +1973 9 13 0 20 FLORENCE 41.7 210.4 10 686 +1977 1 18 12 5 CHRIS 64.8 186.6 97 750 +1967 2 25 0 28 RAFAEL 52.5 54.2 139 661 +2001 11 15 12 2 DEBBY 59.0 347.7 88 39 +1985 7 26 12 23 LESLIE 69.9 95.6 123 734 +2000 2 18 12 16 HELENE 47.6 195.6 162 694 +1976 5 17 18 26 SANDY 31.8 335.6 47 233 +1992 8 18 12 1 DEBBY 19.3 162.2 30 598 +1965 2 20 18 8 TONY 19.3 253.9 33 156 +1951 11 9 12 7 SANDY 39.0 84.9 34 427 +1971 10 4 18 8 KIRK 36.6 88.2 102 721 +1980 2 10 18 24 JOYCE 68.7 296.6 10 356 +1996 8 7 6 4 OSCAR 44.0 33.0 16 366 +1991 6 23 18 11 GORDON 38.1 117.1 73 446 +1959 5 1 18 25 BERYL 28.8 107.9 33 194 +1961 2 3 18 10 FLORENCE 19.0 346.6 12 568 +1956 6 3 0 15 JOYCE 48.3 332.2 105 876 +1950 12 13 6 22 PATTY 67.1 192.7 39 727 +1987 10 14 6 14 RAFAEL 41.3 92.8 111 569 +1968 2 10 0 5 ALBERTO 29.8 106.9 79 449 +1999 4 4 0 2 CHRIS 14.6 229.9 144 434 +1997 12 21 0 17 NADINE 68.2 163.6 79 9 +1985 9 4 18 22 ALBERTO 66.6 311.8 120 360 +1953 3 25 0 7 NADINE 42.0 79.7 46 401 +1993 7 10 18 14 DEBBY 31.9 65.3 113 542 +1998 8 10 12 4 ISAAC 60.5 157.2 55 464 +1980 1 25 0 11 SANDY 18.5 120.6 64 609 +1951 12 26 6 8 BERYL 23.4 9.7 161 818 +1953 3 9 6 25 OSCAR 30.2 70.1 144 201 +1959 6 14 18 1 NADINE 31.3 328.4 42 239 +1971 5 10 6 1 PATTY 60.1 285.2 96 187 +1991 8 28 6 2 ERNESTO 31.1 266.5 14 448 +1984 2 25 6 3 HELENE 68.5 162.6 44 101 +1952 5 26 18 25 NADINE 34.3 215.3 60 852 +2003 11 2 6 2 LESLIE 66.7 165.6 158 461 +1993 8 2 12 6 SANDY 47.2 189.6 125 99 +1995 11 11 18 5 PATTY 60.9 10.1 157 570 +1974 8 9 12 5 CHRIS 19.8 176.5 115 576 +1951 1 22 18 18 ISAAC 11.2 3.5 36 155 +1978 10 5 0 24 VALERIE 45.7 56.4 113 201 +1989 6 16 18 19 DEBBY 36.0 67.2 14 490 +1984 1 5 6 22 TONY 59.5 41.5 47 842 +1998 11 6 12 17 CHRIS 43.4 267.0 87 389 +1966 9 13 0 22 BERYL 18.7 63.2 153 574 +1982 9 12 6 17 BERYL 18.1 122.3 32 694 +1954 1 1 6 24 NADINE 60.5 215.2 48 490 +1983 7 6 12 11 VALERIE 68.1 44.5 160 709 +2004 5 8 6 17 ALBERTO 20.8 111.9 67 324 +1969 4 24 12 19 ERNESTO 37.4 145.2 41 763 +2002 10 28 12 18 VALERIE 57.8 17.8 34 424 +1960 1 12 0 21 LESLIE 47.5 237.8 62 837 +2000 4 9 6 5 MICHAEL 42.0 51.2 101 640 +1989 1 1 12 28 CHRIS 42.1 71.4 155 601 +1983 5 11 0 14 GORDON 29.5 189.1 35 572 +1987 3 11 12 18 ISAAC 33.2 60.9 17 727 +1951 2 15 6 20 ISAAC 56.7 184.1 42 67 +1966 10 25 0 24 GORDON 15.3 351.4 56 237 +2004 1 10 12 11 JOYCE 34.5 304.2 118 897 +1954 2 2 6 19 ISAAC 62.5 213.0 38 38 +1995 5 18 6 20 TONY 10.5 260.4 108 193 +1996 7 16 12 3 SANDY 24.9 185.4 76 541 +1977 3 21 0 12 FLORENCE 41.0 58.7 67 775 +1955 2 9 0 14 HELENE 14.2 310.3 28 301 +2003 4 15 6 25 CHRIS 65.5 354.1 132 785 +1986 12 15 18 27 GORDON 15.9 280.3 43 695 +1999 6 9 12 10 OSCAR 20.8 106.2 88 152 +1984 12 26 18 12 ERNESTO 62.1 38.7 82 781 +1980 5 6 12 12 NADINE 65.3 306.6 135 43 +1999 1 15 12 6 OSCAR 36.6 354.2 100 373 +1974 11 28 6 7 ISAAC 10.6 132.9 110 701 +1968 3 17 12 5 ERNESTO 48.3 251.7 152 802 +2004 1 9 0 9 RAFAEL 60.9 236.0 20 506 +1993 4 2 0 11 NADINE 60.6 98.3 17 257 +1979 8 1 6 11 JOYCE 21.2 323.2 163 769 +1998 10 1 12 7 ISAAC 42.2 84.9 26 602 +1982 10 26 0 16 TONY 32.6 306.6 130 408 +2004 8 14 0 4 GORDON 12.6 137.8 70 241 +1970 2 14 18 28 VALERIE 26.2 30.2 47 402 +1960 6 6 0 3 KIRK 38.5 326.6 100 460 +1982 5 14 12 3 GORDON 14.0 98.6 148 841 +1975 4 25 0 24 BERYL 8.0 323.9 45 427 +1998 4 6 0 14 WILLIAM 56.7 209.6 159 5 +1953 3 16 12 20 HELENE 66.5 238.3 43 75 +1981 3 14 6 2 CHRIS 44.6 72.4 13 683 +1961 11 28 18 5 TONY 39.8 85.6 88 668 +1963 10 5 12 2 PATTY 67.1 223.3 146 861 +1967 12 7 18 17 MICHAEL 50.6 119.8 53 279 +1957 2 8 6 7 OSCAR 68.5 99.8 98 268 +1953 4 27 12 22 TONY 24.4 33.2 63 760 +1957 10 6 6 28 DEBBY 32.9 110.0 115 105 +2003 7 13 6 21 CHRIS 48.1 315.2 37 182 +1997 10 18 18 4 CHRIS 60.1 3.0 123 304 +1969 9 4 6 2 MICHAEL 69.5 169.8 47 483 +1998 10 28 6 6 ALBERTO 35.2 178.0 121 682 +1959 9 1 12 25 WILLIAM 60.7 102.5 30 433 +1977 2 17 6 25 ALBERTO 44.0 103.0 29 782 +2003 3 16 18 20 OSCAR 23.9 104.1 20 692 +1957 11 4 6 17 ERNESTO 15.3 54.7 62 256 +1952 2 17 18 6 NADINE 14.2 14.4 31 672 +2001 4 22 6 1 DEBBY 34.0 356.9 103 114 +1950 1 14 18 23 MICHAEL 43.3 246.6 130 15 +1957 11 10 18 28 NADINE 24.5 341.5 106 210 +1982 1 20 18 14 VALERIE 29.0 184.7 158 737 +1965 1 2 6 5 SANDY 51.0 156.0 45 679 +1961 5 25 6 9 VALERIE 66.4 319.0 97 216 +1977 6 26 18 5 DEBBY 14.1 164.5 15 482 +1993 6 9 18 20 NADINE 27.4 122.1 70 423 +1999 5 25 18 4 ALBERTO 27.1 71.3 133 237 +1995 1 18 6 7 DEBBY 8.8 63.1 69 170 +1965 3 2 0 5 BERYL 26.1 6.8 72 337 +1991 1 14 6 3 RAFAEL 12.2 24.2 117 874 +1968 7 5 6 11 RAFAEL 68.3 289.0 159 847 +2000 1 25 6 9 FLORENCE 50.8 131.1 107 543 +1968 12 6 0 7 WILLIAM 50.9 30.1 54 337 +1998 5 14 12 10 RAFAEL 27.1 209.7 21 483 +1960 8 7 0 23 KIRK 17.6 172.3 72 628 +1965 9 17 18 28 NADINE 49.4 192.4 80 479 +1996 10 17 18 20 ERNESTO 65.0 85.6 108 875 +1985 12 18 12 1 WILLIAM 47.6 290.1 154 767 +1956 10 14 12 28 WILLIAM 25.0 243.0 96 122 +1990 2 21 0 15 TONY 59.3 234.8 70 614 +1978 8 12 6 23 SANDY 63.2 245.4 15 552 +1962 4 4 0 10 BERYL 43.3 222.8 152 542 +1971 6 6 6 11 BERYL 69.1 54.9 21 734 +2001 1 6 0 2 BERYL 14.0 314.0 131 642 +1960 11 15 12 10 SANDY 18.8 62.6 40 431 +1996 1 7 18 20 TONY 11.4 331.9 56 661 +1976 11 13 12 7 OSCAR 48.2 101.1 27 868 +1967 3 9 12 13 SANDY 21.2 244.6 140 817 +1967 1 13 12 20 ALBERTO 32.3 100.0 112 675 +1988 7 24 18 10 RAFAEL 48.1 131.3 77 479 +1969 8 3 0 28 WILLIAM 24.1 171.1 50 597 +1959 5 22 6 21 NADINE 49.4 286.5 161 107 +1993 5 3 18 17 FLORENCE 53.2 249.6 157 574 +1977 1 5 0 6 LESLIE 42.9 117.0 32 828 +1977 3 6 6 2 DEBBY 61.2 73.2 39 781 +1962 5 9 12 26 KIRK 20.5 196.1 20 848 +1986 2 10 6 4 JOYCE 38.2 202.4 52 500 +1975 8 14 0 27 JOYCE 18.1 256.4 136 828 +1952 4 21 18 16 ERNESTO 18.4 347.9 20 360 +1991 11 3 18 18 FLORENCE 18.3 81.5 101 623 +1985 8 10 6 26 KIRK 14.9 356.0 145 863 +1959 12 28 12 13 ISAAC 40.0 211.7 83 80 +1984 11 5 0 8 TONY 69.8 126.5 101 741 +1965 6 8 6 15 ISAAC 64.8 231.8 21 103 +2003 10 20 18 20 RAFAEL 60.8 295.1 143 104 +1960 10 27 12 23 ISAAC 9.9 323.6 34 509 +2004 9 26 6 1 ERNESTO 10.8 311.2 70 344 +1952 5 23 0 17 GORDON 66.3 288.2 76 424 +1987 12 8 0 14 HELENE 54.5 283.3 103 428 +1979 9 14 0 17 SANDY 64.3 99.3 144 325 +1983 8 16 12 23 JOYCE 37.0 301.7 157 767 +1956 5 15 18 24 ALBERTO 62.2 95.9 92 511 +1972 5 7 18 12 DEBBY 47.5 199.6 100 169 +1979 4 13 0 25 GORDON 33.5 170.5 126 319 +1967 4 15 0 21 KIRK 59.6 307.2 41 828 +1959 3 17 6 11 DEBBY 61.1 267.4 65 749 +1969 1 11 18 26 GORDON 20.9 101.1 56 421 +1952 10 20 12 8 CHRIS 7.5 279.1 21 746 +1957 6 28 6 18 TONY 8.5 32.2 100 853 +1993 6 16 0 19 GORDON 63.3 157.4 143 78 +1971 2 16 12 25 ERNESTO 7.9 195.5 37 552 +1967 2 1 18 27 ALBERTO 39.0 130.7 115 198 +1987 4 23 0 14 LESLIE 47.8 173.2 130 797 +1970 2 22 12 13 TONY 67.5 104.5 23 446 +1969 4 12 6 20 MICHAEL 61.5 264.2 86 809 +1961 12 10 18 2 BERYL 25.0 278.4 145 524 +1984 5 17 6 7 HELENE 22.9 177.3 32 748 +1951 1 14 6 19 ERNESTO 35.7 291.5 156 730 +1959 12 3 12 14 OSCAR 38.2 192.3 123 746 +1974 12 10 12 12 ALBERTO 43.2 236.8 40 73 +1982 8 14 18 3 LESLIE 32.3 300.7 135 545 +1951 10 16 6 4 ISAAC 16.4 37.0 38 601 +1956 7 10 12 15 PATTY 9.1 126.5 144 215 +1979 2 16 12 19 OSCAR 18.7 63.1 133 98 +1979 1 20 0 23 WILLIAM 54.2 62.6 80 358 +1966 11 23 6 12 MICHAEL 61.6 231.8 119 205 +1973 3 13 0 10 SANDY 9.7 55.8 114 651 +1992 6 17 0 13 KIRK 9.4 8.6 118 325 +1951 7 7 0 26 WILLIAM 9.2 338.2 31 243 +1959 7 3 18 1 HELENE 59.8 113.7 19 668 +1956 11 22 6 23 CHRIS 39.1 49.3 48 374 +1953 11 26 18 28 MICHAEL 62.9 213.5 97 748 +1961 7 9 18 2 OSCAR 20.2 157.8 41 118 +1959 4 23 0 16 ERNESTO 45.8 310.7 116 472 +1997 8 14 0 1 SANDY 65.6 234.8 157 81 +1956 11 18 6 11 MICHAEL 68.0 320.4 70 428 +2000 12 25 0 28 KIRK 59.2 159.2 144 12 +1965 10 21 0 3 ERNESTO 56.6 219.8 44 163 +1953 6 17 6 16 ISAAC 62.2 204.5 91 96 +1984 5 13 6 7 SANDY 8.3 87.8 129 833 +1953 5 3 6 24 FLORENCE 68.9 119.3 88 872 +1951 11 16 12 8 DEBBY 17.0 288.0 11 645 +1972 5 28 18 11 HELENE 36.3 168.4 109 109 +2000 9 10 0 2 VALERIE 7.4 7.0 139 536 +1997 7 26 12 22 FLORENCE 44.5 231.9 21 471 +1994 5 10 6 24 LESLIE 23.3 94.2 160 515 +1961 11 10 18 7 ERNESTO 32.1 24.2 80 561 +1997 11 27 12 9 TONY 33.3 193.2 82 546 +1990 5 28 12 17 SANDY 62.7 55.4 59 393 +1987 11 7 6 28 PATTY 28.0 251.6 146 171 +1981 10 3 18 13 OSCAR 13.9 133.3 31 340 +1974 9 24 0 20 ERNESTO 66.5 257.1 42 684 +1997 10 26 18 19 OSCAR 23.6 108.7 36 186 +1988 7 11 0 28 HELENE 61.9 110.0 62 261 +2004 7 11 18 27 NADINE 67.2 317.7 23 819 +1970 5 7 0 18 LESLIE 62.2 6.4 147 649 +1959 11 10 0 22 DEBBY 10.6 95.0 141 15 +1997 11 18 0 20 BERYL 46.8 84.2 162 577 +1955 12 4 18 8 FLORENCE 10.0 197.1 68 437 +1957 8 13 6 23 PATTY 20.9 49.9 130 76 +2003 7 22 6 21 KIRK 47.0 21.6 79 200 +1963 3 11 18 25 SANDY 27.3 214.8 49 57 +1982 11 8 6 9 ISAAC 9.6 90.4 50 840 +1956 11 3 6 6 RAFAEL 61.8 260.7 135 370 +1999 10 15 6 11 BERYL 21.7 47.9 103 95 +1974 1 6 18 11 DEBBY 67.4 143.0 142 600 +2003 5 18 0 5 JOYCE 68.9 47.5 28 141 +1953 12 28 0 1 RAFAEL 13.5 36.3 42 312 +1972 11 27 6 5 ERNESTO 17.9 237.1 57 437 +1979 5 25 0 9 JOYCE 12.1 45.0 131 68 +1981 10 9 0 27 LESLIE 10.1 102.4 30 836 +1961 4 15 6 12 CHRIS 67.4 322.9 33 241 +1976 11 7 0 20 JOYCE 7.6 3.2 79 131 +1950 3 12 18 26 VALERIE 56.6 208.5 136 659 +1956 9 28 18 16 FLORENCE 10.2 147.5 65 466 +1961 12 28 0 9 JOYCE 52.6 58.6 81 685 +1956 3 22 12 6 FLORENCE 46.4 233.3 37 118 +2001 5 14 0 20 ALBERTO 26.6 279.7 89 39 +1957 2 11 18 16 PATTY 24.9 55.9 104 104 +1954 10 1 0 23 ISAAC 23.1 262.4 24 307 +1953 4 10 12 2 ERNESTO 51.0 191.0 143 883 +1976 1 25 6 3 MICHAEL 10.9 182.4 121 92 +1975 10 21 12 5 BERYL 35.1 194.8 116 37 +1980 1 10 6 25 LESLIE 26.9 8.3 157 128 +2000 9 21 18 27 TONY 47.1 137.7 148 497 +1994 12 22 6 10 ALBERTO 27.3 133.7 96 235 +1999 12 22 18 9 MICHAEL 61.8 343.7 127 467 +1967 4 1 0 12 ALBERTO 48.2 298.8 11 667 +1975 8 7 0 8 HELENE 62.4 261.6 13 397 +1959 7 23 18 23 NADINE 8.8 105.4 101 281 +1962 3 22 18 26 TONY 39.4 214.3 99 789 +1983 8 26 18 5 ERNESTO 57.0 189.9 50 853 +1966 9 23 6 3 BERYL 41.8 321.5 20 422 +1974 2 26 6 10 OSCAR 33.9 69.8 15 719 +1964 7 11 0 17 LESLIE 48.6 265.4 13 630 +1994 5 18 18 5 JOYCE 9.4 1.0 160 678 +1984 5 19 12 13 OSCAR 29.8 285.3 53 111 +1988 3 13 12 14 ALBERTO 34.4 128.4 96 563 +1970 2 23 18 17 WILLIAM 24.7 177.3 59 772 +1958 11 10 18 15 SANDY 24.1 54.0 36 179 +1974 1 27 18 19 ISAAC 24.8 308.6 62 490 +1964 5 18 18 13 ERNESTO 26.2 89.8 43 727 +1955 6 1 6 5 MICHAEL 25.8 163.5 76 857 +1997 2 14 18 3 LESLIE 60.8 135.9 111 773 +1982 2 26 12 19 MICHAEL 38.8 135.4 56 753 +1975 1 7 0 20 GORDON 10.8 111.7 48 665 +1985 1 4 6 20 JOYCE 37.2 89.2 103 707 +1959 9 26 0 27 NADINE 17.7 341.5 153 568 +1964 6 24 0 2 ERNESTO 53.0 122.6 66 881 +1997 5 22 12 4 VALERIE 49.8 353.9 10 239 +1954 9 23 6 21 KIRK 29.2 257.5 156 84 +1969 1 22 6 25 ERNESTO 36.2 271.3 10 758 +1954 7 13 6 26 WILLIAM 58.0 153.7 140 575 +1973 6 6 12 27 GORDON 27.4 333.0 140 184 +1965 1 11 6 28 MICHAEL 11.7 222.1 12 709 +1999 1 28 6 27 WILLIAM 22.3 220.4 76 90 +1995 12 20 12 19 ERNESTO 56.2 111.7 45 260 +1985 7 21 12 10 BERYL 19.7 13.3 12 367 +1966 10 6 12 20 WILLIAM 12.6 343.2 68 247 +1999 10 13 6 7 SANDY 56.1 125.5 35 334 +1963 4 3 18 7 JOYCE 37.4 147.7 26 830 +1972 5 20 18 20 HELENE 8.9 38.8 101 482 +1984 8 23 18 14 CHRIS 68.7 64.1 111 79 +1951 7 25 12 28 GORDON 34.3 71.8 106 235 +1955 1 20 12 16 HELENE 51.4 8.6 96 345 +2000 4 6 6 24 JOYCE 36.4 123.0 95 874 +1962 1 21 18 5 OSCAR 63.4 61.5 156 672 +1957 11 23 6 14 ISAAC 24.3 199.8 129 859 +1972 7 6 6 23 ALBERTO 62.8 313.7 75 806 +1950 4 14 6 9 OSCAR 52.5 266.2 61 253 +1978 11 20 0 3 KIRK 18.6 44.7 73 458 +2001 1 9 12 13 LESLIE 60.1 152.6 21 852 +1961 5 7 0 5 NADINE 29.5 107.8 102 205 +2004 9 26 12 9 ISAAC 65.4 165.7 85 111 +2000 9 4 18 10 CHRIS 52.8 356.0 22 274 +1956 9 12 12 22 NADINE 47.0 244.1 101 652 +1960 4 18 12 13 TONY 41.7 290.9 111 354 +1959 4 28 0 22 BERYL 65.5 211.9 19 274 +1964 6 7 6 11 WILLIAM 63.3 51.7 82 367 +2000 7 8 18 12 TONY 20.8 239.4 93 602 +1998 4 19 18 9 DEBBY 30.0 281.4 36 744 +1972 12 19 18 14 HELENE 40.0 34.3 151 407 +1965 5 14 0 5 BERYL 44.7 278.0 157 698 +2000 9 25 12 13 KIRK 41.6 24.3 109 359 +1991 6 12 18 20 ERNESTO 22.2 200.2 103 263 +1965 6 14 0 23 HELENE 23.3 217.8 119 671 +1988 11 16 18 3 CHRIS 39.6 204.5 46 591 +1991 7 18 18 11 LESLIE 8.6 74.5 98 172 +1980 7 19 12 10 ALBERTO 39.5 157.5 111 744 +1975 12 26 0 22 MICHAEL 48.2 57.1 125 737 +1950 12 10 18 3 FLORENCE 7.4 248.9 83 29 +1977 3 8 12 8 VALERIE 25.5 169.1 155 729 +2004 7 4 18 20 ISAAC 29.8 137.8 39 665 +1951 11 16 0 4 GORDON 58.5 281.6 118 100 +1989 9 21 18 12 ERNESTO 31.6 316.3 121 309 +1976 12 10 12 7 DEBBY 68.4 66.1 102 537 +2003 8 26 18 16 SANDY 43.8 5.8 20 882 +1998 4 26 6 23 ISAAC 32.7 299.8 109 661 +1992 9 4 6 16 ALBERTO 7.1 112.6 51 723 +2001 5 19 18 12 DEBBY 65.7 124.6 153 474 +1976 6 17 12 1 CHRIS 51.2 199.9 32 145 +1978 4 23 6 12 GORDON 60.5 145.0 162 582 +1954 12 2 0 23 OSCAR 24.4 24.1 100 686 +1987 12 27 12 4 MICHAEL 16.5 293.0 92 140 +1950 11 4 18 27 ISAAC 53.7 289.1 52 717 +1964 3 23 6 2 NADINE 66.5 217.7 140 428 +1976 12 5 12 5 ISAAC 24.9 52.9 109 618 +1995 11 18 6 14 OSCAR 57.3 72.6 81 723 +1952 11 26 6 21 FLORENCE 49.8 156.8 89 409 +1954 6 3 0 4 ISAAC 46.7 57.3 70 466 +1996 2 16 12 4 ISAAC 19.5 98.3 158 61 +1954 6 7 6 8 BERYL 54.3 18.9 26 477 +1978 7 15 18 11 CHRIS 64.9 284.2 140 69 +1993 11 9 0 2 JOYCE 47.5 134.6 135 163 +1956 9 7 12 17 ISAAC 62.4 16.1 123 515 +1984 1 6 12 15 JOYCE 19.5 138.1 21 813 +1986 3 11 18 2 BERYL 9.5 151.3 128 486 +1978 9 26 0 15 ERNESTO 32.9 126.4 55 122 +1958 4 16 12 16 VALERIE 68.6 73.3 12 569 +1996 1 23 0 27 OSCAR 15.2 260.6 129 805 +2001 1 24 18 10 HELENE 40.1 202.9 104 125 +1986 6 16 6 16 HELENE 23.7 47.0 40 763 +1984 2 6 6 18 ERNESTO 54.9 117.7 45 444 +1985 9 4 18 25 PATTY 61.8 67.3 77 54 +1981 10 6 12 18 DEBBY 61.5 170.0 72 546 +1988 1 27 0 15 ISAAC 26.5 239.1 102 798 +1951 3 9 0 11 GORDON 19.7 194.5 78 253 +1975 4 7 6 7 RAFAEL 55.4 112.6 92 10 +1950 10 18 6 14 VALERIE 43.5 124.7 47 802 +2001 3 2 12 15 LESLIE 48.9 86.6 18 225 +1990 12 6 12 19 VALERIE 15.0 334.7 23 763 +1978 4 15 6 23 GORDON 37.4 189.8 147 369 +1989 12 4 12 10 RAFAEL 64.6 155.0 149 364 +1950 12 15 0 26 BERYL 58.3 292.5 131 319 +1986 11 25 12 20 MICHAEL 55.4 349.2 78 432 +1973 2 17 12 22 MICHAEL 42.1 295.5 21 38 +1953 9 28 12 19 ALBERTO 28.0 112.7 52 391 +1987 11 11 0 1 WILLIAM 27.0 56.6 65 34 +1969 10 26 18 19 BERYL 14.5 311.5 142 159 +1992 1 5 18 10 DEBBY 52.6 135.9 63 529 +1969 4 27 0 20 MICHAEL 18.0 274.3 57 20 +1994 4 13 12 5 ISAAC 37.1 347.8 67 624 +1983 9 20 18 17 GORDON 52.3 0.3 155 580 +1965 6 27 12 10 KIRK 28.7 214.4 29 898 +1957 3 10 6 18 TONY 16.2 147.3 66 639 +1971 8 12 18 15 RAFAEL 17.7 305.0 60 549 +1974 1 28 18 20 OSCAR 14.3 240.2 135 687 +1957 6 3 12 3 ALBERTO 53.3 124.7 57 190 +1974 8 18 18 13 HELENE 64.3 352.9 64 149 +1969 6 28 0 13 TONY 30.1 6.7 151 127 +1951 7 17 12 15 MICHAEL 49.1 255.9 63 19 +1991 9 8 6 20 TONY 37.7 70.7 34 304 +1958 11 23 12 12 FLORENCE 14.1 196.0 37 107 +1980 1 2 0 22 MICHAEL 28.9 322.3 22 577 +1999 2 12 6 13 JOYCE 38.1 168.2 142 323 +1985 5 22 0 26 FLORENCE 66.1 162.0 160 378 +1969 2 4 0 9 LESLIE 61.4 65.6 101 727 +1961 1 25 18 21 PATTY 46.7 18.3 13 502 +1967 8 21 0 8 ALBERTO 18.3 286.6 106 444 +1962 8 11 12 1 WILLIAM 43.1 69.6 159 66 +1989 1 6 12 17 ALBERTO 62.7 252.1 50 151 +1981 4 2 0 1 SANDY 65.0 219.6 91 197 +1990 11 25 6 21 ALBERTO 49.4 185.4 47 575 +1995 12 4 6 21 HELENE 18.0 166.2 50 403 +1977 1 19 12 19 FLORENCE 37.4 42.4 82 326 +2001 3 5 6 27 ALBERTO 53.9 239.3 114 859 +2003 3 15 6 1 KIRK 63.4 10.6 158 212 +1963 7 19 6 3 BERYL 25.5 61.8 29 474 +1967 8 27 12 11 MICHAEL 64.0 298.6 93 446 +2002 8 28 0 15 JOYCE 35.6 179.4 140 127 +1969 4 21 0 16 FLORENCE 51.6 242.1 86 596 +1981 11 15 6 11 CHRIS 20.4 136.1 103 779 +1963 2 5 18 13 ERNESTO 13.6 198.9 130 217 +2002 3 5 0 3 PATTY 21.3 55.1 129 142 +1951 8 11 0 24 HELENE 22.6 338.9 84 344 +1952 7 1 6 10 ISAAC 69.5 337.4 98 86 +1986 1 25 18 19 JOYCE 43.9 69.7 52 774 +1962 2 24 18 13 ISAAC 19.1 267.1 103 307 +1989 1 3 0 16 ISAAC 63.3 302.7 70 744 +1961 5 27 0 1 WILLIAM 19.1 353.3 43 542 +1966 10 22 12 17 FLORENCE 7.4 164.4 84 173 +2004 8 1 18 26 KIRK 32.0 259.4 124 247 +1969 6 23 0 20 JOYCE 23.0 311.2 53 113 +1996 3 23 6 11 JOYCE 51.6 132.1 83 707 +2003 8 19 6 6 MICHAEL 26.2 304.4 123 169 +1995 8 14 18 4 ISAAC 46.7 219.9 76 743 +1975 10 3 6 17 PATTY 67.5 144.7 49 310 +1953 4 23 12 10 WILLIAM 45.2 229.0 19 638 +1993 12 17 0 19 BERYL 68.2 347.6 138 833 +1954 3 21 18 17 PATTY 42.8 127.7 67 812 +2000 6 17 12 11 ERNESTO 51.4 139.7 105 243 +1992 1 9 12 2 ISAAC 18.1 99.7 23 476 +1954 10 25 12 2 JOYCE 19.3 353.7 30 381 +1963 9 23 12 7 ERNESTO 33.7 91.8 94 421 +1978 5 2 18 13 ALBERTO 20.6 331.2 41 888 +1998 8 6 0 23 OSCAR 32.0 59.3 60 791 +1972 8 11 18 6 HELENE 45.7 70.7 114 776 +1969 4 28 12 27 ISAAC 20.9 191.2 143 453 +1968 2 17 18 7 SANDY 9.8 299.4 143 683 +1959 3 13 0 13 TONY 23.8 37.8 20 285 +1999 6 25 18 6 MICHAEL 12.8 299.6 17 191 +1982 1 22 0 18 HELENE 37.3 150.8 133 336 +1991 12 13 12 23 CHRIS 68.2 317.3 157 760 +1988 6 20 0 15 TONY 31.6 146.4 63 491 +1987 10 14 18 14 BERYL 43.0 1.6 44 333 +1993 3 8 0 27 ISAAC 17.1 272.7 148 824 +1990 5 19 0 1 ERNESTO 22.7 17.2 68 154 +1957 6 28 0 13 LESLIE 43.9 124.8 92 178 +1988 8 16 18 9 ERNESTO 69.0 90.7 108 712 +1998 2 16 18 3 HELENE 46.1 128.0 108 62 +1968 10 21 18 11 CHRIS 9.2 158.1 60 142 +1967 4 5 12 10 NADINE 44.9 141.1 35 874 +1962 1 6 0 18 FLORENCE 14.6 152.3 159 828 +1971 7 28 12 16 NADINE 68.9 321.9 58 342 +1976 8 6 12 10 LESLIE 14.5 84.2 17 378 +1965 10 3 0 16 HELENE 9.4 284.1 93 648 +1986 12 6 0 24 TONY 47.4 338.1 149 577 +1995 5 22 0 6 TONY 25.9 129.0 64 605 +1952 2 22 0 14 ERNESTO 44.3 261.6 127 866 +1955 11 9 18 3 KIRK 28.5 262.4 157 686 +1997 10 15 0 15 FLORENCE 60.3 357.4 83 660 +1968 6 17 12 28 DEBBY 24.2 223.0 164 567 +1992 11 26 12 5 JOYCE 60.8 185.3 124 231 +1993 6 13 0 10 JOYCE 16.3 31.4 67 322 +1952 9 9 12 18 DEBBY 54.8 176.2 57 69 +1971 11 1 0 6 OSCAR 19.2 5.2 137 386 +1957 12 7 6 21 LESLIE 61.9 279.0 138 555 +1977 9 3 12 8 FLORENCE 12.1 153.7 133 376 +1995 6 23 0 26 KIRK 7.7 32.1 42 832 +1956 4 18 18 28 GORDON 33.6 187.6 36 648 +1952 12 16 0 27 FLORENCE 48.5 137.8 133 232 +1986 12 23 18 1 ERNESTO 10.5 5.3 127 356 +1969 5 10 12 14 VALERIE 38.5 199.4 148 10 +1993 12 12 12 7 HELENE 47.8 178.4 83 656 +2001 12 11 0 1 ALBERTO 11.5 56.7 95 313 +1983 8 8 6 26 GORDON 41.8 312.9 57 256 +1975 3 2 0 12 VALERIE 20.0 283.0 101 265 +1996 3 8 18 20 GORDON 22.1 5.8 108 456 +1952 1 22 0 16 NADINE 13.2 179.9 142 102 +1963 4 5 12 19 SANDY 62.3 294.3 41 243 +1972 9 20 6 12 TONY 43.6 311.0 66 188 +1950 10 4 18 3 ISAAC 66.6 202.3 56 98 +1965 7 12 18 18 ISAAC 62.0 249.9 18 159 +1980 6 13 0 25 LESLIE 61.3 125.1 151 66 +1984 1 23 6 26 RAFAEL 14.0 198.0 139 701 +2001 2 1 12 12 JOYCE 40.2 75.4 77 526 +1980 3 15 18 14 GORDON 29.5 158.0 117 640 +1950 1 21 6 20 WILLIAM 46.7 3.0 17 252 +1968 11 15 0 17 KIRK 38.9 147.0 92 375 +1950 2 2 6 2 NADINE 56.6 225.5 83 197 +1998 4 28 18 2 KIRK 16.7 327.1 117 411 +1974 11 17 12 3 ISAAC 57.9 125.4 36 627 +1954 8 3 12 1 KIRK 33.5 228.0 23 247 +1956 9 16 12 7 NADINE 22.9 163.2 102 171 +1968 12 25 18 7 PATTY 69.3 285.6 65 338 +1970 8 1 0 7 ISAAC 12.2 65.8 81 471 +1969 1 7 12 27 KIRK 24.9 129.7 77 649 +1950 5 24 12 21 DEBBY 58.7 297.5 81 809 +1974 3 7 12 25 NADINE 26.9 88.8 93 472 +1984 9 24 18 27 TONY 54.1 128.2 83 651 +1981 2 15 18 22 PATTY 38.9 127.4 146 479 +1954 3 17 18 16 ERNESTO 40.6 58.0 91 166 +1998 4 10 18 12 HELENE 56.7 215.3 21 220 +1976 5 19 0 20 RAFAEL 16.5 325.8 63 120 +1992 11 24 6 2 ALBERTO 54.5 182.3 72 417 +1955 7 26 6 23 ISAAC 38.2 274.8 84 863 +1950 11 25 18 18 ALBERTO 50.6 180.1 145 867 +1981 9 13 18 26 HELENE 14.0 327.5 103 118 +1960 3 14 6 19 NADINE 57.8 67.6 116 577 +1972 3 5 12 9 ERNESTO 54.0 344.5 164 407 +1990 2 27 12 19 ERNESTO 54.8 216.6 110 184 +1976 7 9 12 8 VALERIE 9.5 79.9 67 701 +1969 9 24 18 23 KIRK 50.0 206.3 67 679 +1980 1 20 12 15 TONY 10.5 71.5 54 878 +1953 12 19 12 4 MICHAEL 25.8 221.4 141 655 +2003 3 17 18 16 FLORENCE 41.3 245.7 159 69 +2002 10 3 0 12 SANDY 13.4 129.7 21 312 +1963 12 13 18 23 ALBERTO 16.3 285.9 138 562 +1960 11 27 6 24 WILLIAM 58.3 88.2 53 625 +2003 9 23 0 22 LESLIE 34.2 288.0 124 152 +1980 11 2 0 17 RAFAEL 40.4 273.8 88 374 +1997 12 11 0 17 VALERIE 14.2 7.5 22 641 +1950 10 18 0 19 HELENE 11.4 118.1 60 511 +1951 12 26 6 21 CHRIS 47.5 78.1 113 841 +1994 10 22 0 7 KIRK 35.3 168.2 104 228 +1958 9 25 6 26 KIRK 45.9 117.4 94 39 +1953 8 27 0 2 FLORENCE 68.9 3.9 126 293 +1956 5 27 12 11 LESLIE 41.8 17.5 127 892 +1983 12 5 6 6 ALBERTO 52.2 124.1 28 297 +1968 7 20 6 9 TONY 55.7 339.4 53 452 +1995 9 14 12 15 OSCAR 38.0 124.1 86 609 +1991 12 11 18 12 FLORENCE 48.4 179.4 156 665 +1951 9 18 12 9 PATTY 33.3 192.3 86 781 +2000 9 19 0 27 MICHAEL 9.7 194.7 155 635 +1971 5 24 6 24 HELENE 62.4 45.7 103 5 +1981 1 6 0 12 SANDY 20.1 152.1 153 617 +1954 6 19 0 14 LESLIE 30.4 243.8 61 675 +1983 5 20 0 28 TONY 27.6 163.6 95 716 +1974 4 1 0 20 LESLIE 39.4 226.9 162 545 +1995 7 23 12 17 RAFAEL 30.1 61.6 35 803 +1994 3 25 12 10 RAFAEL 24.7 186.1 156 193 +2000 9 13 12 16 FLORENCE 43.5 65.1 60 577 +1972 10 14 6 22 KIRK 34.3 306.3 15 770 +1985 11 2 6 6 WILLIAM 23.4 318.4 133 303 +1992 10 6 12 24 ALBERTO 9.1 276.4 42 343 +1976 11 18 18 19 DEBBY 20.5 280.9 112 161 +1971 9 13 12 27 WILLIAM 25.5 187.1 139 894 +1981 2 8 18 23 KIRK 68.8 267.3 88 770 +1976 7 28 12 5 ALBERTO 48.5 352.6 159 605 +1963 12 25 18 16 HELENE 55.3 317.0 91 809 +1961 7 15 12 28 GORDON 31.3 144.7 88 177 +1999 7 25 0 14 NADINE 52.2 289.7 97 212 +1993 12 9 18 1 MICHAEL 33.8 0.2 141 161 +1970 11 15 6 7 FLORENCE 12.3 259.1 21 692 +1968 7 14 0 21 ISAAC 53.8 275.4 10 514 +1950 4 22 12 18 ALBERTO 57.4 248.9 16 132 +1956 2 22 6 20 DEBBY 45.4 354.1 121 489 +1954 12 14 12 5 CHRIS 54.1 310.1 141 50 +1997 10 9 18 27 CHRIS 29.0 268.4 13 263 +1964 3 18 18 13 WILLIAM 48.4 86.3 152 480 +1975 5 9 18 27 WILLIAM 52.5 101.4 32 121 +1953 12 2 0 1 DEBBY 61.3 336.8 110 576 +1966 12 27 6 14 KIRK 15.3 332.4 18 645 +1953 6 26 12 24 NADINE 17.4 188.1 10 108 +1981 8 13 12 5 PATTY 25.6 120.4 131 732 +1956 10 5 6 11 HELENE 57.5 52.8 65 381 +1966 1 21 0 5 OSCAR 68.0 214.4 53 604 +1974 5 15 12 26 HELENE 29.3 291.4 145 845 +1956 5 4 6 5 JOYCE 51.2 221.0 120 136 +1984 5 20 18 6 GORDON 41.1 23.6 77 43 +1981 9 12 18 12 DEBBY 48.5 144.3 14 570 +1953 6 19 0 8 CHRIS 63.8 262.4 29 315 +1979 10 1 12 8 LESLIE 64.7 211.5 19 354 +1979 11 21 0 27 ALBERTO 43.0 317.0 71 455 +1972 12 23 6 8 DEBBY 39.1 182.0 33 83 +1958 1 19 12 14 WILLIAM 41.5 171.9 55 621 +1996 7 17 18 8 CHRIS 55.5 275.0 144 572 +1961 4 9 0 24 OSCAR 61.4 21.0 101 284 +1951 1 4 12 21 SANDY 37.4 64.1 27 193 +1976 2 23 18 2 CHRIS 42.3 330.7 127 451 +1963 3 23 12 9 OSCAR 41.9 69.5 64 347 +2001 6 8 18 5 KIRK 40.0 340.9 143 620 diff --git a/benchmarks/new_opencl/nearn/cane4_3.db b/benchmarks/new_opencl/nearn/cane4_3.db new file mode 100755 index 00000000..0f9c701f --- /dev/null +++ b/benchmarks/new_opencl/nearn/cane4_3.db @@ -0,0 +1,10691 @@ +1992 5 9 0 14 ISAAC 11.4 327.9 31 382 +1993 4 10 6 12 FLORENCE 58.4 282.7 119 684 +1985 5 9 6 4 LESLIE 20.7 339.8 15 210 +1969 6 27 12 25 NADINE 48.7 59.2 101 506 +2004 11 17 12 9 LESLIE 61.9 274.2 137 895 +1966 3 23 6 25 SANDY 34.9 8.1 82 566 +1992 2 13 12 3 ALBERTO 59.8 22.3 31 870 +1964 9 10 0 4 VALERIE 32.8 352.2 81 47 +1960 9 7 0 23 MICHAEL 11.8 318.0 10 90 +1983 4 1 6 25 TONY 22.0 93.6 133 153 +2000 6 21 18 8 MICHAEL 11.5 141.8 121 163 +1975 5 4 18 4 GORDON 62.9 271.2 25 773 +1978 12 18 6 16 KIRK 24.8 65.1 57 210 +1985 7 9 0 4 LESLIE 46.8 162.2 36 866 +1958 8 25 12 2 TONY 58.6 115.8 87 402 +1968 5 16 12 15 FLORENCE 49.3 309.9 85 648 +1954 3 4 6 18 HELENE 50.8 26.0 55 282 +1953 4 24 18 8 WILLIAM 10.3 145.4 55 543 +1955 11 2 6 16 ISAAC 33.6 48.5 95 499 +1950 4 22 12 8 CHRIS 57.1 162.5 132 663 +1961 12 7 6 17 BERYL 41.3 271.9 73 192 +1962 3 7 0 7 ISAAC 58.0 130.6 25 643 +2004 3 11 6 6 ISAAC 32.3 208.7 66 456 +1971 7 16 12 21 MICHAEL 40.1 8.2 131 876 +2001 6 9 12 22 GORDON 18.5 7.0 94 473 +1993 1 19 6 23 OSCAR 54.4 37.4 123 511 +1972 2 11 12 2 NADINE 26.6 276.2 28 847 +1994 1 3 12 5 ERNESTO 24.0 225.6 118 56 +1997 8 9 12 5 ISAAC 43.2 245.3 109 261 +1985 11 21 12 22 ISAAC 13.7 18.5 127 591 +1952 11 1 12 17 RAFAEL 61.7 66.6 78 434 +1989 12 16 0 11 PATTY 40.0 116.2 34 249 +1993 3 22 18 22 DEBBY 45.3 271.9 98 625 +1967 8 26 0 27 FLORENCE 44.2 51.7 112 624 +1966 10 7 18 8 GORDON 37.9 199.5 161 402 +1953 9 2 12 20 FLORENCE 26.8 291.3 163 719 +1967 8 23 0 17 JOYCE 11.7 97.4 26 550 +1986 9 14 18 7 HELENE 63.9 298.6 107 295 +1974 10 17 12 2 OSCAR 20.6 119.0 127 876 +2000 2 25 6 5 MICHAEL 58.2 72.3 63 18 +1982 12 23 6 22 DEBBY 8.6 72.4 131 722 +2001 10 15 0 26 HELENE 39.1 263.9 19 681 +1955 4 5 0 9 JOYCE 38.9 355.0 22 826 +1956 11 13 0 23 LESLIE 10.5 111.4 90 443 +2002 5 23 6 22 PATTY 13.9 298.2 26 490 +1980 8 20 6 21 MICHAEL 38.7 102.2 75 133 +1996 8 9 0 13 VALERIE 62.6 123.9 140 490 +1951 6 8 18 5 HELENE 51.2 75.8 46 275 +1991 9 20 0 4 DEBBY 30.5 235.7 68 383 +1951 11 20 18 5 JOYCE 31.3 28.8 154 838 +1963 12 28 18 13 HELENE 40.5 123.4 101 40 +1969 11 8 6 1 GORDON 58.5 336.2 103 29 +1955 3 19 0 3 CHRIS 54.1 272.4 37 722 +1976 5 1 18 16 BERYL 41.6 110.7 84 500 +1993 4 11 6 8 PATTY 50.5 293.7 116 159 +1960 4 14 12 10 JOYCE 19.5 21.4 37 606 +1975 2 28 12 17 VALERIE 45.8 284.4 83 25 +1996 12 11 0 17 NADINE 22.7 225.2 14 800 +1970 4 12 12 21 HELENE 22.6 126.0 164 678 +1984 1 28 0 25 SANDY 52.5 54.7 160 668 +1963 9 21 12 13 NADINE 14.4 138.2 38 50 +2000 6 22 6 14 PATTY 33.8 124.0 127 819 +1991 9 4 18 13 OSCAR 53.1 254.7 30 148 +1957 6 13 18 23 RAFAEL 49.9 347.7 140 176 +1987 10 12 6 21 SANDY 41.6 164.8 15 895 +1987 6 28 0 25 LESLIE 63.9 104.3 146 517 +1953 4 15 6 23 VALERIE 65.5 190.0 64 461 +1972 4 21 6 13 ERNESTO 16.6 335.8 140 619 +1969 3 10 18 20 DEBBY 33.9 109.3 103 327 +1956 9 5 18 26 DEBBY 23.5 100.6 163 846 +1951 9 8 18 20 RAFAEL 19.6 176.5 128 557 +1964 4 19 18 14 BERYL 13.0 60.7 53 351 +1956 4 11 0 18 NADINE 33.1 81.6 94 883 +1962 8 24 0 16 CHRIS 33.2 141.6 123 682 +1982 4 10 18 27 FLORENCE 65.8 229.9 40 76 +1952 12 14 18 6 WILLIAM 22.8 289.2 138 508 +1951 5 27 0 1 WILLIAM 12.3 5.8 79 727 +1950 7 16 6 23 ERNESTO 69.7 241.7 25 465 +1950 4 5 6 25 WILLIAM 17.3 92.7 96 568 +1951 6 18 18 21 NADINE 26.6 57.7 149 750 +1955 2 21 12 17 ALBERTO 23.7 146.7 120 256 +1991 11 20 0 11 ISAAC 39.6 65.8 21 407 +1981 3 2 18 10 FLORENCE 36.7 303.9 23 251 +1970 5 8 12 13 JOYCE 67.0 78.6 61 848 +2003 5 21 12 19 TONY 51.1 238.4 131 415 +1990 2 16 18 27 BERYL 55.8 213.9 50 329 +1957 1 5 18 18 VALERIE 46.2 202.6 140 302 +1957 12 4 18 15 SANDY 42.7 297.4 119 888 +2003 12 25 18 25 PATTY 8.1 15.0 23 305 +1961 5 18 0 14 CHRIS 24.4 33.1 33 737 +1996 8 20 18 9 MICHAEL 16.5 211.1 51 435 +1952 10 25 12 7 WILLIAM 55.7 53.4 125 758 +1997 2 13 0 4 PATTY 9.7 161.8 87 540 +1962 9 23 6 5 DEBBY 29.9 281.7 62 559 +1953 10 7 0 7 PATTY 9.5 136.5 27 258 +1961 7 20 12 8 DEBBY 58.4 323.9 154 885 +1950 5 22 12 22 PATTY 28.8 102.6 20 455 +2001 7 19 18 2 TONY 47.5 340.4 46 820 +1969 2 10 12 27 TONY 49.9 302.7 150 98 +1955 8 7 0 24 TONY 42.5 340.9 88 521 +1968 6 14 6 19 OSCAR 52.9 143.9 23 891 +1974 11 3 18 28 RAFAEL 60.0 249.8 10 414 +1988 8 8 12 6 GORDON 16.1 228.6 160 731 +1958 9 8 12 23 NADINE 14.4 130.1 125 867 +2003 11 24 6 19 CHRIS 50.8 260.0 156 160 +1983 6 11 12 3 MICHAEL 59.1 331.3 10 199 +1963 3 14 12 14 WILLIAM 17.5 170.5 48 578 +1966 2 3 12 21 DEBBY 26.3 26.3 81 662 +1976 7 10 12 3 PATTY 64.8 24.4 137 601 +1957 5 26 6 21 ISAAC 45.6 210.0 88 783 +1957 9 22 6 17 LESLIE 22.6 87.7 86 86 +1975 9 3 0 20 TONY 32.6 249.7 65 21 +1962 5 22 0 18 OSCAR 23.4 45.3 140 607 +1983 9 13 6 10 KIRK 30.4 352.5 47 511 +1969 5 7 18 8 KIRK 63.4 207.7 27 692 +1985 8 16 6 24 SANDY 23.8 33.1 42 536 +1986 5 19 6 23 SANDY 68.5 212.3 65 759 +1994 6 24 0 28 LESLIE 67.9 290.2 73 381 +1996 9 6 12 10 LESLIE 22.6 335.7 38 853 +1976 4 3 0 15 BERYL 9.2 239.5 127 542 +1961 2 25 18 2 HELENE 44.8 323.2 17 848 +1986 5 20 0 10 GORDON 23.8 220.2 145 84 +1969 2 20 6 21 NADINE 37.4 120.5 87 249 +1981 6 14 6 12 BERYL 69.7 170.7 94 353 +1988 8 19 6 16 RAFAEL 47.4 242.7 103 438 +1973 10 16 6 26 LESLIE 42.1 200.9 86 801 +1999 12 7 18 13 KIRK 42.4 74.9 44 273 +1952 3 23 6 28 LESLIE 56.9 287.8 49 334 +1954 12 27 6 4 OSCAR 60.4 24.7 14 706 +1977 8 14 12 15 ALBERTO 31.9 103.6 80 132 +1966 7 25 12 26 DEBBY 22.0 255.4 142 528 +1982 10 28 0 23 FLORENCE 59.8 61.3 90 891 +1977 4 13 18 1 JOYCE 20.6 170.9 29 195 +2003 10 1 12 5 TONY 29.6 20.8 113 571 +1996 9 6 6 4 GORDON 10.5 349.7 154 862 +1964 5 20 12 1 GORDON 10.2 192.3 35 848 +1971 4 15 12 14 FLORENCE 43.5 306.5 153 284 +1994 9 6 12 26 MICHAEL 61.4 78.4 152 214 +1953 11 12 18 17 RAFAEL 65.1 293.0 76 536 +1965 6 27 18 8 HELENE 62.5 181.2 15 862 +1952 11 5 6 10 CHRIS 59.5 275.0 133 562 +1986 1 5 0 19 TONY 41.0 15.8 41 269 +1977 9 2 6 6 CHRIS 44.7 64.0 39 26 +2001 5 20 12 24 MICHAEL 17.9 209.2 56 13 +1983 3 28 18 25 ERNESTO 32.7 204.2 121 218 +1993 11 19 6 19 KIRK 31.3 188.3 94 671 +1979 1 17 0 2 ERNESTO 65.5 122.4 98 324 +1969 11 26 6 16 JOYCE 49.2 261.9 156 655 +1976 4 18 12 3 RAFAEL 54.2 351.6 26 647 +1986 3 11 0 20 NADINE 48.4 14.9 13 845 +1971 6 17 12 8 BERYL 59.3 287.7 103 845 +1974 10 14 0 5 ISAAC 27.6 125.7 42 518 +1956 3 3 18 21 KIRK 48.4 28.4 131 807 +1960 9 21 0 19 RAFAEL 13.9 111.5 152 829 +1975 6 15 12 11 NADINE 15.8 221.5 104 385 +1966 5 7 12 9 FLORENCE 68.0 69.4 87 639 +1968 11 9 0 2 ERNESTO 11.6 252.7 117 341 +1966 4 18 18 15 VALERIE 56.2 178.5 18 533 +1968 5 15 0 4 SANDY 63.5 211.4 159 422 +1996 8 4 18 19 HELENE 9.9 21.2 67 391 +1983 2 16 12 16 GORDON 44.5 166.9 159 701 +2000 12 16 12 11 VALERIE 34.1 183.5 35 158 +1980 12 8 18 18 VALERIE 37.5 262.3 94 248 +2001 10 12 12 11 JOYCE 68.5 275.1 107 60 +1958 10 16 18 18 ALBERTO 58.5 176.1 131 343 +1975 9 7 0 11 ERNESTO 57.3 114.7 122 139 +1983 5 27 18 4 ISAAC 32.9 26.5 89 377 +1997 8 5 18 20 RAFAEL 31.7 225.7 78 527 +1981 7 14 0 6 BERYL 64.4 201.0 46 62 +1990 2 2 0 20 TONY 39.7 98.0 110 605 +1966 10 12 6 22 PATTY 21.7 292.9 102 606 +2001 1 26 12 26 ALBERTO 69.6 74.2 36 7 +1979 8 21 12 10 ISAAC 17.0 111.1 141 74 +1976 11 4 6 21 RAFAEL 21.4 286.8 115 281 +1954 8 7 18 10 NADINE 43.1 269.8 51 285 +1988 12 11 18 27 ISAAC 21.9 32.9 140 883 +1971 5 20 12 18 TONY 9.3 24.8 94 303 +1982 8 13 12 15 ISAAC 24.4 22.2 163 798 +1954 7 23 18 8 ISAAC 41.2 171.8 23 312 +1971 9 14 12 19 OSCAR 51.9 322.3 112 850 +1977 7 7 12 4 KIRK 14.7 238.5 56 448 +1991 7 18 6 21 PATTY 33.5 189.8 144 260 +1971 1 18 0 27 ERNESTO 30.3 240.6 45 441 +1953 5 22 18 4 KIRK 51.4 116.2 157 754 +1965 2 16 0 5 OSCAR 21.6 202.6 79 601 +1986 7 3 18 15 BERYL 66.7 98.3 129 29 +1976 9 12 0 22 ISAAC 52.9 317.1 128 891 +1957 1 24 12 18 BERYL 7.5 239.5 37 7 +1995 6 22 0 3 KIRK 15.2 234.9 59 612 +1975 7 5 12 16 LESLIE 50.1 148.4 63 381 +1991 9 28 0 22 WILLIAM 16.3 121.5 84 179 +1982 3 19 6 24 RAFAEL 24.4 252.4 104 715 +2003 6 3 6 22 LESLIE 25.3 297.9 94 580 +1952 8 17 12 13 ALBERTO 54.4 282.7 162 513 +1982 1 16 6 2 ISAAC 63.6 218.1 85 429 +1975 6 18 12 27 VALERIE 31.4 182.2 145 688 +1954 11 20 6 27 RAFAEL 53.7 89.6 71 884 +1956 11 24 0 22 CHRIS 19.5 150.5 102 494 +1984 11 27 18 18 LESLIE 57.0 154.0 136 600 +2002 8 20 0 9 MICHAEL 48.4 36.8 25 344 +1955 6 13 12 24 OSCAR 24.9 218.0 41 214 +1991 10 15 0 9 GORDON 10.2 266.5 122 850 +1950 12 3 18 24 FLORENCE 35.2 26.0 109 586 +1963 2 25 0 25 DEBBY 14.3 332.0 56 868 +2003 1 23 18 13 VALERIE 24.9 208.2 124 891 +1956 7 2 12 23 SANDY 39.8 317.5 131 248 +1970 5 24 18 3 MICHAEL 19.1 110.6 110 350 +1959 5 16 6 14 FLORENCE 68.1 344.0 151 619 +1951 4 1 0 26 DEBBY 38.8 48.7 84 228 +1998 3 8 0 4 WILLIAM 20.9 355.0 47 479 +1997 8 8 6 15 KIRK 23.7 299.9 100 26 +1953 11 3 18 6 NADINE 66.8 280.7 129 64 +1987 6 22 12 16 LESLIE 44.7 43.2 78 629 +1964 9 4 12 13 DEBBY 39.4 344.0 119 858 +1983 5 6 6 24 PATTY 38.1 29.4 161 776 +1967 7 8 6 3 ISAAC 30.9 77.3 81 583 +1961 11 22 0 10 WILLIAM 22.4 4.4 17 5 +1955 6 5 0 9 WILLIAM 14.1 231.0 18 113 +2002 2 6 18 19 HELENE 59.5 129.0 162 267 +1968 9 22 0 16 ISAAC 45.4 203.9 105 751 +1952 12 22 18 1 LESLIE 60.7 269.6 142 279 +1986 11 26 12 7 ALBERTO 66.1 309.9 24 842 +1998 8 1 18 22 RAFAEL 44.7 50.4 12 758 +1980 3 23 0 25 JOYCE 37.0 220.1 141 391 +1974 10 8 0 1 LESLIE 45.4 103.6 40 677 +1968 7 7 6 3 KIRK 8.5 319.4 46 561 +1967 11 23 0 28 SANDY 53.9 255.2 125 487 +1995 5 24 18 8 WILLIAM 43.9 234.8 71 648 +1996 11 10 18 1 TONY 19.8 353.9 13 505 +1997 9 2 0 16 CHRIS 52.1 100.0 56 382 +1950 7 1 0 5 OSCAR 66.6 197.4 146 218 +1985 8 11 18 23 ERNESTO 49.6 72.2 129 407 +1955 9 15 12 20 FLORENCE 66.0 126.1 117 443 +1960 3 26 6 5 ISAAC 35.6 242.3 45 553 +1980 6 18 6 27 FLORENCE 21.7 13.1 70 464 +1969 6 3 12 19 ERNESTO 61.6 220.4 112 263 +1959 6 10 0 12 ISAAC 66.6 307.7 152 581 +1987 6 1 6 25 DEBBY 22.4 328.9 163 892 +1958 8 7 12 26 BERYL 8.4 122.4 110 761 +1956 2 6 18 5 JOYCE 69.7 129.9 137 372 +1968 4 1 0 20 CHRIS 69.3 233.4 106 30 +1958 8 7 6 11 TONY 64.1 173.4 94 487 +1986 8 16 6 5 MICHAEL 31.6 210.9 53 896 +2003 8 20 0 19 SANDY 13.2 105.6 48 407 +1968 3 10 12 2 KIRK 10.5 278.5 42 378 +1964 10 25 12 15 ISAAC 24.8 42.3 85 877 +1968 8 8 0 17 RAFAEL 22.0 194.3 70 446 +1953 11 6 18 20 WILLIAM 27.6 310.2 133 828 +1961 11 10 18 1 SANDY 30.4 219.6 86 53 +1962 12 1 12 13 FLORENCE 50.5 12.9 140 561 +2000 6 15 0 4 WILLIAM 36.9 34.4 149 464 +2004 9 4 6 5 OSCAR 31.4 5.7 122 399 +1958 2 17 6 19 ALBERTO 49.7 234.2 70 765 +1990 7 23 18 20 JOYCE 24.9 82.8 106 622 +1999 3 13 6 2 GORDON 45.5 236.6 80 408 +2001 1 18 0 7 BERYL 16.8 107.3 63 228 +1961 1 8 0 8 PATTY 17.7 268.9 62 387 +1988 5 24 12 23 RAFAEL 67.3 191.0 108 531 +1963 6 9 0 22 ALBERTO 23.0 296.4 157 317 +1958 10 4 6 13 KIRK 16.4 125.2 119 713 +1994 9 22 6 21 NADINE 43.4 133.8 140 776 +1999 9 3 0 1 RAFAEL 11.5 84.7 149 486 +1970 2 11 18 2 GORDON 26.6 80.6 44 189 +1997 11 21 18 19 FLORENCE 38.5 282.5 16 772 +1997 7 24 0 16 HELENE 63.1 96.3 122 815 +1996 4 17 6 11 OSCAR 28.6 32.8 127 26 +1977 5 16 12 18 FLORENCE 15.7 139.1 137 256 +1973 8 24 0 28 GORDON 44.2 141.7 119 743 +1986 4 2 6 6 HELENE 55.9 128.4 63 640 +1967 6 17 0 8 WILLIAM 20.3 41.7 111 347 +1951 2 24 18 18 PATTY 28.8 11.9 32 100 +1965 5 5 6 20 ISAAC 49.2 196.9 87 827 +1982 3 21 6 7 RAFAEL 67.7 58.5 21 153 +1986 11 8 12 20 BERYL 23.4 46.0 11 406 +2000 2 21 12 27 FLORENCE 50.4 187.3 150 293 +1954 3 26 0 3 DEBBY 16.9 165.3 68 66 +1952 12 1 0 11 HELENE 59.9 73.3 42 607 +1951 6 9 18 4 SANDY 8.8 338.4 24 474 +2000 6 9 18 7 SANDY 10.1 105.9 116 605 +1957 10 11 18 21 GORDON 25.8 111.7 136 78 +2002 5 18 6 8 GORDON 56.2 161.8 62 637 +1975 8 17 12 14 ERNESTO 34.4 205.9 99 821 +1969 1 2 18 4 BERYL 45.4 285.6 131 236 +1972 9 15 18 24 WILLIAM 22.9 119.7 42 844 +1990 10 12 12 1 GORDON 10.9 89.9 103 608 +1984 2 17 6 21 JOYCE 40.4 138.7 64 700 +1982 2 24 18 28 ALBERTO 46.6 46.4 44 898 +1974 2 15 0 26 OSCAR 66.4 106.6 60 584 +2002 9 18 12 1 TONY 41.3 255.1 33 2 +1971 11 23 18 13 HELENE 52.5 5.9 57 542 +1973 2 13 12 7 DEBBY 22.5 327.2 143 452 +1999 8 21 12 5 HELENE 11.5 228.2 79 815 +1999 8 3 6 16 JOYCE 53.4 219.0 15 701 +1955 4 18 12 24 RAFAEL 11.8 356.9 101 706 +1977 1 25 6 4 NADINE 54.9 253.6 108 716 +1997 8 22 0 8 PATTY 43.7 234.3 55 860 +1980 10 15 18 21 RAFAEL 26.4 20.4 96 38 +1958 4 26 6 23 BERYL 21.8 222.4 115 811 +1959 10 10 6 1 TONY 35.6 284.0 154 862 +1993 8 21 18 7 CHRIS 69.8 173.8 160 57 +2004 10 13 0 17 WILLIAM 15.8 273.3 68 518 +1985 8 21 18 7 FLORENCE 40.6 279.6 73 807 +1979 9 2 6 7 OSCAR 31.6 127.3 81 767 +1960 6 25 0 23 ERNESTO 51.7 133.7 45 251 +1959 8 23 6 17 ALBERTO 8.9 251.2 84 559 +2001 10 10 12 21 VALERIE 66.7 297.2 19 447 +1952 7 15 12 18 TONY 24.2 157.2 32 139 +1988 11 26 12 28 RAFAEL 53.1 144.5 46 870 +1989 7 27 18 25 DEBBY 41.9 182.8 146 709 +1962 5 23 18 21 ERNESTO 14.7 56.9 156 274 +1977 9 21 18 28 WILLIAM 34.7 3.7 82 651 +1970 1 4 12 17 DEBBY 34.0 330.9 142 142 +1992 8 16 6 13 KIRK 7.8 324.2 85 394 +2002 2 9 18 18 WILLIAM 8.1 141.3 17 238 +1982 1 12 12 23 NADINE 16.9 133.0 91 699 +2002 1 21 18 25 ALBERTO 30.9 35.8 65 210 +1958 3 14 0 13 PATTY 47.9 23.3 103 211 +1951 11 13 0 26 KIRK 61.3 118.7 154 458 +1980 4 3 0 14 SANDY 68.2 77.2 84 465 +1996 4 11 18 17 JOYCE 37.1 129.3 64 536 +1971 1 16 12 8 DEBBY 26.1 178.9 90 309 +1966 7 26 12 23 KIRK 62.5 13.5 123 329 +1989 10 28 6 28 ERNESTO 22.3 61.7 115 360 +1986 10 8 12 13 WILLIAM 27.9 72.0 82 486 +1978 11 18 0 17 CHRIS 30.2 155.1 59 56 +1997 9 1 12 6 NADINE 67.6 185.7 110 763 +1950 1 1 18 18 LESLIE 15.3 15.8 116 885 +1969 6 16 0 15 RAFAEL 41.2 165.9 21 836 +1980 4 19 6 6 GORDON 50.9 231.9 27 728 +1983 10 1 0 25 KIRK 17.8 141.2 22 475 +1992 9 11 18 13 BERYL 34.3 343.4 106 632 +1963 12 21 18 28 FLORENCE 11.8 356.8 61 586 +1964 6 15 6 23 VALERIE 43.7 353.7 35 554 +1962 1 13 6 23 MICHAEL 30.9 53.6 92 451 +2001 2 14 0 18 CHRIS 15.9 305.5 103 364 +1961 11 15 0 10 BERYL 42.7 322.7 134 786 +1950 11 26 12 17 VALERIE 53.8 250.6 145 357 +2004 3 19 0 28 SANDY 34.3 323.5 161 134 +1961 5 3 18 27 OSCAR 48.2 271.1 20 662 +1996 9 10 12 19 KIRK 40.7 263.6 119 514 +1987 7 21 18 22 NADINE 61.9 210.8 32 369 +1974 7 23 0 14 JOYCE 58.4 229.3 84 627 +1976 10 6 12 16 WILLIAM 21.1 7.7 34 351 +1978 10 28 12 18 MICHAEL 11.3 305.0 58 834 +1985 2 2 18 21 DEBBY 47.9 71.0 28 80 +1957 4 10 0 26 ISAAC 67.2 296.4 149 151 +1963 8 28 0 21 NADINE 45.2 140.1 160 160 +1983 6 17 18 2 TONY 12.7 40.2 149 847 +1965 1 9 0 4 HELENE 54.7 275.8 120 627 +1962 9 11 6 21 GORDON 50.0 76.2 85 744 +1966 11 13 18 8 ERNESTO 26.2 266.4 70 193 +1990 9 24 12 19 ALBERTO 25.5 164.1 151 554 +2001 11 27 0 25 BERYL 20.8 59.7 111 482 +1979 8 8 0 20 DEBBY 11.4 33.5 35 866 +1974 8 22 0 28 JOYCE 35.8 4.5 136 640 +1996 2 26 6 2 WILLIAM 65.5 309.3 11 192 +1955 6 11 12 7 ALBERTO 29.6 90.6 134 346 +1964 9 12 18 10 WILLIAM 11.2 355.6 138 474 +1963 5 7 18 4 JOYCE 35.4 0.4 25 112 +1951 9 2 18 6 RAFAEL 54.1 284.8 110 111 +2004 1 27 6 1 NADINE 54.6 321.0 141 278 +1963 1 1 12 11 VALERIE 69.6 276.7 18 398 +1995 9 12 18 25 RAFAEL 7.1 163.6 76 216 +2002 7 7 12 9 NADINE 29.9 342.6 130 354 +1957 9 10 12 9 HELENE 61.8 102.4 32 708 +1992 8 6 12 13 OSCAR 55.2 6.5 68 135 +1980 6 20 6 23 ISAAC 38.4 29.8 86 37 +1998 7 8 6 6 BERYL 39.2 137.9 64 227 +1998 4 19 6 9 CHRIS 34.5 161.3 78 379 +1957 10 28 12 19 ISAAC 16.0 245.4 164 104 +1982 6 25 12 5 SANDY 53.2 101.1 37 677 +1997 2 18 0 14 ALBERTO 20.1 344.5 115 298 +1996 8 6 0 10 ERNESTO 63.9 152.2 162 811 +1970 8 11 18 12 OSCAR 35.2 243.6 69 506 +1971 12 12 6 16 ERNESTO 44.2 92.5 90 399 +1975 10 28 18 27 ISAAC 38.1 145.9 161 740 +1958 2 12 6 20 FLORENCE 60.3 168.6 27 121 +2003 1 22 0 9 ALBERTO 28.2 27.6 116 250 +1990 8 24 6 25 WILLIAM 48.5 254.0 77 199 +1958 10 20 18 17 ISAAC 38.4 316.7 102 340 +1968 7 14 18 22 WILLIAM 66.5 35.3 13 625 +1979 2 10 0 19 MICHAEL 53.7 42.0 96 557 +1982 7 21 0 17 ALBERTO 45.3 114.9 112 581 +1997 10 16 6 11 VALERIE 35.9 23.9 127 101 +1985 7 1 0 27 ERNESTO 68.9 329.1 38 897 +1960 4 7 6 19 ERNESTO 25.5 37.5 36 25 +1955 7 4 12 27 ERNESTO 43.9 330.5 156 58 +1990 9 5 0 11 OSCAR 45.4 148.4 55 308 +1984 11 4 6 9 HELENE 18.0 225.1 141 388 +1992 3 19 0 27 MICHAEL 22.3 87.5 80 183 +1978 8 11 6 3 DEBBY 15.5 157.4 114 733 +2001 4 17 6 18 HELENE 60.5 252.7 59 231 +1998 2 13 0 13 NADINE 12.3 33.7 100 599 +1950 10 28 12 3 BERYL 23.8 238.8 118 845 +1957 8 4 12 27 WILLIAM 45.4 32.3 36 686 +1983 11 14 6 26 RAFAEL 52.0 355.7 110 173 +1989 8 3 0 19 DEBBY 63.1 250.8 33 763 +1968 1 6 0 19 ERNESTO 28.2 298.5 10 867 +1970 9 22 0 9 HELENE 12.3 188.3 109 46 +2004 8 28 6 13 MICHAEL 32.6 308.8 133 729 +1952 1 28 18 5 DEBBY 12.2 353.0 14 311 +1973 1 20 0 21 RAFAEL 15.9 10.0 69 819 +1960 8 6 12 5 JOYCE 14.7 6.7 147 196 +1956 11 3 0 26 WILLIAM 33.6 169.7 164 733 +1967 1 19 18 10 SANDY 7.5 323.8 48 640 +1953 11 6 18 13 JOYCE 18.2 163.0 162 238 +2003 3 24 0 18 MICHAEL 54.3 267.5 129 746 +1997 11 16 18 11 CHRIS 14.3 322.6 88 177 +2003 2 28 18 16 NADINE 44.5 277.4 40 176 +1952 2 6 18 5 DEBBY 12.9 58.7 79 868 +1964 8 7 0 21 NADINE 65.5 354.8 51 319 +2002 5 3 6 18 NADINE 46.0 47.1 109 867 +1959 1 17 6 22 WILLIAM 19.1 83.3 24 876 +1984 2 12 18 18 TONY 8.1 329.5 116 432 +1985 2 17 12 1 ALBERTO 51.2 88.2 108 535 +1984 11 9 6 15 KIRK 55.9 270.3 52 663 +1999 4 19 12 13 KIRK 45.3 6.4 129 184 +1960 7 20 18 17 VALERIE 33.6 258.2 131 668 +1954 8 19 6 1 MICHAEL 44.7 209.8 138 593 +1986 12 9 12 27 VALERIE 49.2 260.8 13 224 +1980 10 2 12 5 PATTY 55.5 305.7 58 147 +1968 11 11 6 15 NADINE 16.0 245.3 57 485 +1968 1 17 0 18 TONY 23.9 290.5 32 264 +1952 12 9 6 1 RAFAEL 22.4 290.7 158 546 +1957 8 23 12 3 KIRK 15.9 266.7 53 857 +2004 8 20 6 26 RAFAEL 51.8 353.0 77 178 +1979 7 18 6 6 FLORENCE 55.9 89.8 32 511 +1968 2 22 18 9 RAFAEL 8.3 74.6 17 133 +1959 10 14 0 13 WILLIAM 13.3 344.5 67 121 +2000 10 3 18 12 BERYL 13.2 308.9 51 370 +1967 10 21 0 1 BERYL 26.8 157.1 35 829 +1989 11 27 0 7 ISAAC 66.5 207.0 49 411 +1969 10 14 12 5 FLORENCE 9.5 300.6 109 771 +1962 3 15 18 9 DEBBY 8.2 333.8 99 265 +1984 8 2 12 28 RAFAEL 33.8 179.8 13 10 +1982 8 3 18 26 DEBBY 26.3 335.0 56 729 +1983 7 3 6 21 PATTY 7.8 139.8 128 519 +1958 8 24 12 27 LESLIE 20.4 205.5 159 562 +1977 8 21 12 24 HELENE 18.1 300.4 128 676 +1972 5 16 12 1 BERYL 43.7 153.7 113 437 +1958 12 20 12 22 MICHAEL 68.3 340.5 126 596 +1995 6 22 18 13 RAFAEL 66.7 91.7 75 48 +1955 6 26 6 14 ERNESTO 51.4 321.2 87 416 +1986 7 12 18 16 SANDY 34.8 354.8 17 302 +1979 9 18 18 24 FLORENCE 17.1 315.7 157 644 +1959 6 24 18 8 ALBERTO 65.9 39.7 107 138 +2004 10 21 12 19 JOYCE 46.8 114.0 89 596 +1972 4 15 12 20 WILLIAM 10.9 308.7 29 226 +1972 11 9 12 6 SANDY 41.4 122.8 97 718 +1999 9 16 18 11 WILLIAM 25.2 243.4 157 651 +1981 4 23 6 7 GORDON 57.1 129.2 117 516 +1982 9 2 12 14 CHRIS 14.5 61.3 137 543 +1953 10 6 18 15 ALBERTO 31.5 55.5 120 483 +1983 10 6 0 9 NADINE 16.4 97.5 142 230 +1951 1 14 18 25 TONY 24.4 105.3 141 422 +1988 5 28 18 6 ISAAC 30.2 180.3 34 186 +1954 8 10 12 26 MICHAEL 33.5 98.7 68 274 +1978 5 14 0 1 LESLIE 28.8 262.5 40 445 +1974 6 17 0 2 OSCAR 59.9 154.6 68 683 +1960 2 11 18 28 MICHAEL 14.3 189.5 45 505 +1973 7 1 18 28 KIRK 62.8 263.7 15 588 +1980 12 23 12 8 VALERIE 28.4 324.5 93 747 +1972 1 12 6 19 JOYCE 9.8 51.2 56 320 +1958 9 2 0 18 DEBBY 66.8 346.8 16 337 +1977 1 22 0 17 HELENE 23.7 98.1 72 342 +1987 6 12 0 1 SANDY 51.1 306.8 55 565 +1960 2 2 18 24 DEBBY 33.5 318.4 18 580 +1951 1 1 6 4 MICHAEL 62.1 25.9 37 659 +1999 5 1 12 27 ERNESTO 18.0 234.2 120 345 +1960 7 6 6 24 OSCAR 21.0 125.8 22 520 +1954 10 24 18 17 LESLIE 18.7 118.6 16 420 +1955 1 25 18 18 LESLIE 52.4 101.2 79 616 +1987 5 26 0 7 ERNESTO 50.9 199.3 100 47 +1964 9 27 18 21 ALBERTO 65.5 97.5 19 201 +1995 10 24 18 12 VALERIE 52.8 331.2 148 241 +1982 8 20 18 15 BERYL 11.8 295.6 76 617 +1982 12 23 18 24 GORDON 15.9 50.3 52 524 +1962 10 23 12 27 WILLIAM 68.2 238.1 64 574 +1961 12 27 6 17 KIRK 59.1 45.8 54 273 +1951 11 12 6 11 BERYL 46.6 334.7 108 184 +1957 7 19 0 18 BERYL 7.3 139.8 67 291 +1995 6 27 6 28 WILLIAM 40.3 51.7 34 573 +1996 2 3 18 2 RAFAEL 63.2 118.1 153 803 +1998 6 21 6 27 HELENE 67.1 82.8 156 739 +1983 10 12 18 27 LESLIE 22.2 319.5 16 810 +1980 12 12 6 18 NADINE 69.3 284.5 103 357 +1966 5 20 6 28 SANDY 29.6 97.7 57 77 +1992 7 25 0 5 ERNESTO 18.2 20.7 81 228 +1957 7 20 6 8 OSCAR 33.9 214.2 125 151 +1992 10 7 12 6 CHRIS 21.4 61.8 51 342 +1975 3 22 12 4 SANDY 54.7 46.3 120 440 +1999 11 21 12 9 LESLIE 33.4 300.3 37 19 +1983 6 20 0 22 MICHAEL 21.1 153.0 78 173 +1990 6 12 18 19 VALERIE 57.1 134.8 83 842 +1995 4 6 12 4 DEBBY 45.9 243.4 40 302 +1993 6 8 12 18 VALERIE 37.4 291.5 23 238 +1980 10 23 0 5 VALERIE 11.2 325.5 124 102 +1961 6 25 0 23 ALBERTO 45.4 280.7 54 481 +1954 6 21 0 25 ALBERTO 20.3 88.3 124 589 +1971 7 26 0 3 PATTY 20.7 117.2 72 296 +1962 6 8 12 24 DEBBY 69.7 69.1 111 127 +1985 12 7 18 13 DEBBY 45.6 234.7 98 470 +1992 8 16 18 15 WILLIAM 68.5 316.4 136 770 +1991 10 11 18 1 BERYL 53.1 61.7 85 31 +1950 11 4 18 24 KIRK 19.2 301.4 120 565 +1986 1 14 6 4 ERNESTO 50.0 94.9 67 124 +1959 3 16 0 21 LESLIE 59.6 355.9 141 603 +1974 5 13 6 26 PATTY 42.8 104.4 83 233 +1972 1 14 12 18 OSCAR 19.7 291.9 57 223 +1959 2 4 18 17 JOYCE 29.8 36.8 87 344 +1977 3 21 12 19 PATTY 59.9 113.6 78 438 +1972 3 10 12 21 PATTY 60.7 251.4 84 221 +2000 11 16 6 18 CHRIS 44.3 274.3 95 724 +1994 9 17 18 11 WILLIAM 22.3 209.0 100 558 +1988 5 23 18 13 VALERIE 36.2 273.5 76 714 +1975 6 25 6 27 FLORENCE 23.7 167.2 15 875 +1983 1 25 12 28 ALBERTO 44.0 328.5 32 527 +1953 1 23 12 16 SANDY 16.1 348.0 69 637 +1956 9 14 0 7 CHRIS 50.0 30.4 133 359 +1962 11 9 0 10 PATTY 68.1 42.7 90 352 +1975 7 3 12 28 TONY 11.0 354.8 28 252 +1965 6 16 6 6 SANDY 35.2 217.5 116 452 +1962 8 11 12 21 LESLIE 18.7 241.0 147 389 +1957 3 12 6 27 DEBBY 39.3 214.1 64 691 +1975 1 27 6 26 TONY 67.6 59.6 28 225 +1952 8 18 0 20 PATTY 29.5 236.9 60 600 +1992 9 28 0 2 VALERIE 49.9 32.7 131 581 +1993 10 1 6 10 LESLIE 33.6 16.5 149 160 +1957 11 3 12 3 ALBERTO 31.4 297.4 160 331 +1968 8 23 6 18 WILLIAM 53.2 298.6 38 569 +2002 10 6 6 26 DEBBY 47.0 238.0 151 306 +1965 6 7 12 12 OSCAR 31.2 72.4 47 635 +1966 10 2 18 14 WILLIAM 15.0 308.4 82 189 +1956 2 11 0 5 PATTY 60.4 205.3 116 842 +1980 5 12 6 8 RAFAEL 20.7 183.2 143 200 +1978 10 3 12 8 MICHAEL 41.1 135.6 142 787 +1998 7 17 12 20 TONY 62.5 49.8 142 847 +2004 2 2 12 4 LESLIE 8.8 113.3 126 339 +1957 7 7 12 17 FLORENCE 29.7 58.8 10 311 +1966 12 22 6 4 NADINE 52.3 119.0 91 777 +1992 3 7 12 28 MICHAEL 41.0 136.9 33 82 +1977 7 15 12 25 PATTY 9.5 105.9 87 86 +1988 7 1 12 8 PATTY 17.2 21.2 149 762 +1958 11 14 6 15 MICHAEL 57.0 205.5 24 591 +1966 4 2 0 15 DEBBY 60.4 38.8 127 629 +1992 1 17 18 27 ISAAC 56.8 11.4 37 282 +1967 6 11 18 20 PATTY 29.4 190.0 123 870 +1957 5 13 6 8 ISAAC 64.2 97.1 50 596 +1973 1 18 18 11 OSCAR 26.6 24.1 133 415 +1972 6 1 6 14 ISAAC 38.7 219.9 156 492 +1979 6 5 18 9 MICHAEL 41.7 352.5 121 361 +1950 10 4 18 2 KIRK 16.4 228.8 102 591 +1980 8 13 6 1 ERNESTO 31.0 339.4 21 191 +1988 8 12 12 20 ERNESTO 44.9 81.5 84 876 +1993 6 19 18 1 RAFAEL 24.2 209.4 59 873 +1973 7 28 18 17 OSCAR 66.1 357.3 120 730 +1998 7 2 18 2 SANDY 11.9 348.5 89 576 +1993 4 17 12 18 TONY 19.3 221.8 17 627 +1970 9 12 6 10 LESLIE 11.4 230.9 95 457 +2002 10 7 18 12 MICHAEL 45.3 34.4 44 867 +1987 6 14 0 9 OSCAR 69.5 323.5 58 40 +1978 11 7 6 20 HELENE 15.2 46.2 146 859 +1983 6 8 6 2 ALBERTO 48.6 187.0 13 351 +1953 6 10 0 5 NADINE 13.8 32.9 30 89 +1957 9 21 12 9 OSCAR 16.8 283.9 84 792 +1954 7 11 6 18 OSCAR 26.5 214.3 50 112 +2003 9 18 0 28 SANDY 18.5 17.2 61 232 +1997 9 1 18 18 OSCAR 23.0 0.5 14 781 +1959 11 4 6 4 JOYCE 63.1 48.1 30 369 +1961 11 15 12 21 ALBERTO 29.2 266.4 134 727 +1966 3 20 0 4 OSCAR 27.8 125.2 44 738 +1950 9 8 6 12 HELENE 13.9 275.5 137 687 +2000 4 27 6 7 KIRK 37.0 101.5 149 586 +1980 4 16 0 8 LESLIE 69.2 355.2 23 464 +1976 8 4 6 25 WILLIAM 57.2 351.1 108 133 +1968 2 16 18 22 VALERIE 9.0 222.1 37 76 +2004 9 11 12 27 KIRK 53.3 267.5 136 826 +1998 4 6 6 7 ERNESTO 20.0 356.0 106 304 +1993 3 3 0 8 KIRK 19.4 302.9 45 619 +1965 11 17 18 13 SANDY 13.2 113.3 77 39 +1976 11 2 18 2 ERNESTO 12.3 317.9 40 824 +2000 11 17 12 22 ALBERTO 45.1 325.7 95 653 +1956 7 20 6 18 RAFAEL 17.6 325.3 160 362 +1964 9 4 6 23 MICHAEL 66.6 11.8 95 308 +1972 7 19 18 12 BERYL 50.7 90.3 75 759 +1984 9 6 0 11 JOYCE 27.7 352.1 157 652 +1995 11 5 12 1 RAFAEL 44.7 296.2 45 519 +2001 6 11 18 6 HELENE 22.2 47.9 73 77 +1962 8 17 0 27 HELENE 17.6 161.0 106 211 +1961 7 13 12 28 WILLIAM 42.4 40.0 102 523 +2004 12 20 12 20 ISAAC 27.1 182.0 94 297 +1954 3 23 0 24 HELENE 13.5 23.2 118 164 +1974 7 18 12 4 SANDY 19.4 308.1 97 443 +1972 4 17 18 28 SANDY 7.0 182.5 130 767 +1954 12 22 12 24 RAFAEL 31.8 230.6 12 303 +1962 8 6 0 25 OSCAR 25.0 349.9 41 504 +1993 12 26 6 6 NADINE 41.5 165.3 34 20 +1950 12 20 0 23 BERYL 51.4 51.7 44 849 +1995 8 2 0 7 DEBBY 64.8 127.8 27 748 +1998 6 8 0 16 HELENE 60.7 336.6 76 21 +1966 12 5 12 26 BERYL 47.3 90.9 58 697 +1970 1 21 18 23 VALERIE 64.0 92.7 16 41 +1980 2 21 0 21 OSCAR 9.3 333.6 128 872 +1990 11 17 18 7 VALERIE 50.7 238.8 72 554 +1996 6 16 0 20 KIRK 24.9 89.8 29 362 +1983 12 16 18 14 ERNESTO 54.5 241.9 20 160 +1956 11 11 0 28 GORDON 15.2 27.9 34 328 +2004 7 27 0 8 JOYCE 26.9 105.4 90 892 +1977 7 11 12 19 CHRIS 38.3 324.5 98 101 +1961 1 11 6 23 OSCAR 60.9 133.4 78 744 +1997 7 8 18 1 MICHAEL 49.5 197.7 76 583 +1977 5 5 0 14 KIRK 38.7 344.3 37 80 +1996 6 13 18 6 ALBERTO 9.1 124.0 89 655 +2004 1 17 12 16 RAFAEL 61.2 61.1 116 824 +1964 12 14 12 20 RAFAEL 12.7 31.4 11 698 +1970 1 4 18 4 SANDY 39.5 80.4 42 259 +1951 6 10 0 24 TONY 38.9 334.9 111 537 +1960 4 20 18 2 MICHAEL 23.6 88.2 150 328 +1980 7 6 12 22 HELENE 18.3 257.8 73 556 +1996 11 8 0 20 OSCAR 18.1 37.4 97 641 +1977 4 23 6 25 NADINE 46.5 210.9 164 785 +1988 2 28 0 25 NADINE 41.1 165.3 128 339 +1982 4 13 0 12 PATTY 16.6 290.9 65 509 +1986 3 12 6 9 FLORENCE 39.8 114.6 139 568 +1959 4 3 18 20 DEBBY 50.0 228.3 44 770 +1975 9 19 6 28 FLORENCE 34.1 157.5 19 689 +1986 6 28 0 20 HELENE 38.3 43.2 47 600 +1989 2 28 6 13 KIRK 59.4 111.2 108 599 +1974 1 4 6 6 FLORENCE 65.5 266.2 147 726 +1952 11 18 0 10 CHRIS 26.0 212.7 118 62 +1991 1 8 12 26 JOYCE 38.1 261.0 140 522 +1978 1 12 6 14 SANDY 31.7 281.6 138 117 +1989 11 6 18 11 DEBBY 40.3 7.0 72 771 +1965 10 17 0 15 CHRIS 43.4 90.1 140 699 +1969 5 13 12 14 JOYCE 49.9 292.8 28 210 +1996 11 4 0 28 BERYL 47.7 285.0 146 61 +1963 9 23 18 3 NADINE 47.3 318.9 103 25 +1970 4 8 6 1 LESLIE 60.4 302.7 38 838 +1994 3 5 0 23 DEBBY 10.1 312.0 71 5 +2003 11 7 18 14 JOYCE 53.7 344.8 59 410 +1972 5 25 12 19 RAFAEL 25.5 286.9 74 140 +1954 7 4 0 3 PATTY 35.6 248.6 138 866 +1985 2 18 0 6 TONY 15.1 197.1 155 424 +1979 3 16 0 27 FLORENCE 68.1 297.3 20 815 +1964 11 6 18 27 KIRK 36.1 51.4 74 360 +1960 5 10 6 12 NADINE 66.5 190.4 121 768 +1979 11 6 6 11 ALBERTO 24.0 263.0 20 811 +1991 10 25 18 4 RAFAEL 59.3 113.5 97 396 +1957 5 7 12 14 LESLIE 25.3 68.6 62 277 +1989 4 15 12 10 ALBERTO 48.5 226.0 56 622 +1950 2 13 0 27 PATTY 31.8 234.2 143 849 +2003 1 19 6 1 ALBERTO 20.1 316.3 80 850 +1965 3 12 6 4 ISAAC 8.9 95.6 82 363 +1997 5 11 0 8 DEBBY 36.2 5.2 14 15 +1979 7 2 12 23 TONY 40.5 243.8 10 835 +1960 7 26 6 27 BERYL 27.5 330.4 153 563 +1997 9 14 6 18 LESLIE 9.4 107.2 21 61 +1955 9 19 12 25 ISAAC 44.2 115.4 135 661 +1986 7 16 18 6 TONY 38.2 136.5 161 431 +1986 5 10 0 14 FLORENCE 23.3 272.2 160 406 +1973 4 3 0 14 VALERIE 48.1 102.1 37 744 +1978 8 12 0 16 ISAAC 20.1 114.4 150 850 +1998 8 27 6 13 DEBBY 54.1 91.6 162 380 +2002 12 26 0 17 TONY 34.2 172.1 147 99 +1962 10 25 0 22 CHRIS 58.3 339.2 111 465 +1955 5 24 18 19 WILLIAM 29.2 248.5 24 464 +1985 6 27 12 26 JOYCE 9.7 294.0 52 199 +1983 9 20 6 18 OSCAR 7.6 326.3 92 795 +1996 6 24 18 27 SANDY 63.6 304.7 16 163 +1957 8 6 0 18 OSCAR 16.7 257.8 39 740 +1990 11 7 18 17 HELENE 42.2 44.7 155 126 +2001 11 11 0 2 HELENE 47.5 121.7 99 697 +1983 9 23 18 19 KIRK 47.0 85.5 54 887 +1952 7 15 0 16 HELENE 25.3 211.8 161 888 +1998 10 25 0 6 ALBERTO 63.6 21.3 97 275 +1989 8 1 0 26 KIRK 22.9 18.5 34 254 +1984 1 12 18 18 VALERIE 9.5 256.4 23 875 +1973 3 25 12 23 PATTY 54.5 298.4 44 625 +1986 8 19 6 11 NADINE 20.1 289.2 36 70 +1964 5 8 6 21 TONY 42.0 109.7 124 69 +1989 1 5 12 15 JOYCE 48.7 149.2 137 733 +1954 10 24 18 12 GORDON 32.2 91.5 72 411 +1954 10 17 6 4 CHRIS 68.4 180.1 24 6 +2002 7 8 12 4 ERNESTO 68.7 20.2 118 394 +1975 2 6 12 11 NADINE 36.6 295.1 51 142 +2004 4 28 6 27 ERNESTO 31.6 140.7 138 463 +1987 8 2 18 15 CHRIS 40.7 297.7 63 669 +1972 5 21 18 3 SANDY 63.5 310.3 57 222 +2000 10 24 12 26 PATTY 33.8 156.2 107 536 +1969 4 18 18 18 ERNESTO 40.1 295.0 123 11 +2004 10 20 6 14 HELENE 35.1 170.8 122 139 +1985 8 6 18 14 HELENE 32.5 318.6 100 527 +1964 5 26 12 2 TONY 59.9 329.5 73 744 +1994 12 13 6 11 SANDY 50.3 10.4 116 698 +1973 10 12 18 7 DEBBY 27.2 142.1 41 117 +1987 1 9 0 7 KIRK 8.9 233.7 61 685 +1962 11 17 12 17 FLORENCE 25.8 132.8 47 810 +1984 7 3 0 7 WILLIAM 53.8 239.6 32 687 +1957 8 9 6 21 BERYL 37.3 225.4 20 659 +1970 6 13 12 22 KIRK 57.8 157.7 31 49 +1963 4 25 6 14 DEBBY 68.4 104.3 18 430 +2000 5 21 12 4 WILLIAM 33.9 166.3 105 595 +1961 5 13 6 28 RAFAEL 69.6 59.7 12 542 +1958 6 3 0 15 BERYL 52.4 3.7 126 30 +1992 5 9 12 7 BERYL 52.1 125.1 62 342 +1975 10 6 18 24 LESLIE 58.4 275.7 135 422 +1950 4 16 12 23 VALERIE 36.3 36.7 104 5 +1970 2 11 18 27 OSCAR 28.0 85.1 42 193 +2003 3 27 6 27 JOYCE 51.6 298.9 14 733 +1984 9 12 12 5 PATTY 9.6 261.8 133 852 +2002 3 10 18 26 VALERIE 16.6 28.3 110 270 +1979 8 25 0 18 FLORENCE 65.1 139.2 97 676 +1980 8 1 12 25 SANDY 22.6 165.0 19 616 +1981 7 8 0 26 MICHAEL 52.6 106.6 117 71 +2004 4 9 12 21 VALERIE 37.6 250.4 141 155 +1964 1 6 6 20 DEBBY 14.2 334.5 12 695 +1956 12 14 6 15 TONY 37.6 241.5 135 899 +1993 6 1 12 28 KIRK 20.0 259.4 50 62 +2000 2 15 0 27 PATTY 43.2 286.0 150 121 +1952 8 7 0 9 BERYL 7.4 182.9 99 617 +1973 5 21 6 28 ALBERTO 49.8 168.0 18 555 +1995 2 10 0 7 PATTY 49.8 61.2 19 783 +2000 9 8 12 25 NADINE 38.9 164.6 95 149 +1970 1 15 6 23 WILLIAM 26.7 154.0 84 0 +1983 10 1 6 13 VALERIE 8.2 324.1 124 548 +2001 6 7 0 14 RAFAEL 31.7 344.3 88 637 +1992 7 26 12 28 HELENE 28.8 38.6 135 662 +1971 11 27 12 11 MICHAEL 8.1 145.1 90 678 +1988 2 20 12 26 ALBERTO 31.5 248.3 18 50 +1953 6 20 18 1 CHRIS 53.1 223.0 85 278 +1951 12 15 0 9 MICHAEL 12.1 148.5 84 245 +1958 2 3 6 6 KIRK 17.0 39.7 158 287 +1954 7 14 12 6 HELENE 51.0 170.4 160 98 +1992 4 23 12 14 HELENE 57.1 349.9 128 742 +1964 9 17 18 19 ISAAC 58.1 247.0 114 480 +1961 5 25 0 8 TONY 57.8 292.7 106 670 +1954 8 23 18 7 DEBBY 64.2 141.1 65 297 +1957 8 7 18 3 RAFAEL 38.2 185.6 137 220 +1964 4 6 6 17 CHRIS 14.7 104.3 103 218 +1964 3 13 18 13 GORDON 48.7 140.5 46 707 +1970 7 16 6 19 BERYL 61.9 257.3 147 691 +1979 9 13 6 26 MICHAEL 27.1 307.4 64 143 +1993 3 27 12 21 GORDON 23.8 209.4 75 857 +1955 1 5 18 24 ISAAC 27.8 120.6 52 834 +1970 1 17 18 17 HELENE 55.6 303.1 79 684 +1980 6 21 0 22 CHRIS 32.2 340.0 12 130 +2000 1 11 12 16 VALERIE 58.6 257.2 83 108 +2003 9 23 6 21 DEBBY 35.6 51.1 93 132 +1968 5 23 18 22 OSCAR 34.6 258.3 164 835 +1971 11 3 6 20 HELENE 31.3 298.3 148 628 +1994 9 3 0 19 GORDON 21.0 289.8 156 358 +1990 11 15 18 18 ALBERTO 39.7 160.4 152 289 +1953 3 3 0 3 WILLIAM 22.5 199.7 111 763 +1964 2 26 6 17 RAFAEL 60.6 203.1 46 663 +1963 11 7 0 27 CHRIS 60.5 292.5 156 580 +1953 1 24 12 13 OSCAR 27.3 94.5 86 665 +1976 7 26 18 25 LESLIE 23.4 4.3 105 165 +1968 5 13 12 6 ALBERTO 57.2 264.7 156 772 +1971 11 13 12 22 CHRIS 45.3 118.9 52 788 +1993 10 15 18 11 RAFAEL 17.7 303.7 75 326 +1979 9 6 18 11 GORDON 36.1 106.0 35 826 +2004 9 6 18 5 NADINE 62.0 198.7 73 672 +1989 1 4 0 21 FLORENCE 10.0 249.4 130 287 +1973 7 23 12 19 HELENE 28.5 336.6 19 669 +1993 8 15 0 6 TONY 25.9 318.2 135 814 +1970 1 10 12 25 HELENE 58.2 11.7 56 645 +1967 10 11 0 20 LESLIE 13.3 24.9 100 27 +2002 4 13 18 16 SANDY 21.1 249.4 61 309 +1952 10 24 12 22 LESLIE 45.5 274.9 102 383 +1999 12 2 18 23 MICHAEL 52.3 196.6 100 433 +1998 2 11 0 1 LESLIE 12.2 301.7 134 344 +1973 7 18 0 5 OSCAR 52.9 337.3 149 188 +1968 4 25 12 6 SANDY 56.3 78.0 88 708 +1978 12 17 18 12 ERNESTO 56.9 64.2 131 808 +1964 9 19 0 2 PATTY 18.9 236.0 118 599 +1981 11 25 0 25 SANDY 15.9 329.0 146 404 +1975 3 4 12 11 BERYL 35.4 199.6 107 128 +1970 10 22 6 6 ISAAC 34.5 189.4 100 823 +1979 2 1 12 26 ERNESTO 49.3 167.0 32 652 +1981 6 26 0 11 OSCAR 59.1 329.3 164 40 +1984 4 2 12 12 ERNESTO 21.4 315.0 80 244 +1978 1 21 18 7 CHRIS 35.4 72.1 150 182 +1973 1 9 18 16 ERNESTO 52.9 224.1 44 401 +1985 10 3 0 24 ERNESTO 14.0 131.5 158 743 +1986 11 19 18 20 FLORENCE 25.0 224.1 10 857 +1974 2 28 0 19 ERNESTO 47.0 150.3 36 643 +1960 6 4 6 18 VALERIE 68.6 189.9 151 512 +1953 2 28 6 4 GORDON 69.1 109.6 15 753 +1953 11 22 6 18 FLORENCE 13.4 345.0 118 728 +1976 3 1 18 25 JOYCE 35.4 57.4 19 776 +1984 5 21 0 10 WILLIAM 66.1 299.3 137 88 +1965 12 11 12 20 GORDON 57.3 237.9 77 783 +2001 10 24 18 6 ALBERTO 48.7 251.3 24 618 +1981 8 13 0 10 MICHAEL 17.7 147.7 36 210 +1985 5 5 12 28 ISAAC 40.5 111.9 14 56 +1962 5 3 18 5 HELENE 33.7 315.7 27 28 +1997 3 14 0 1 TONY 55.9 52.5 114 435 +1964 4 9 6 9 JOYCE 42.9 168.8 141 130 +1998 3 17 0 21 DEBBY 58.7 264.0 59 732 +1996 10 20 6 6 ALBERTO 37.4 170.7 20 508 +1954 6 23 0 6 HELENE 17.1 275.7 98 826 +1967 7 17 18 24 NADINE 42.6 92.2 33 549 +1981 6 24 0 3 GORDON 33.2 266.0 118 793 +1977 7 15 12 14 BERYL 27.3 346.4 41 277 +1964 1 3 18 12 HELENE 11.4 151.6 94 199 +1975 8 8 12 22 LESLIE 63.3 13.1 163 726 +1963 10 20 0 18 VALERIE 11.4 276.6 71 543 +1984 12 23 0 8 NADINE 61.2 186.1 96 677 +1961 12 24 12 10 BERYL 53.4 116.7 137 210 +1962 2 15 0 17 TONY 43.3 339.5 52 644 +1970 11 23 12 13 CHRIS 36.6 115.4 47 547 +1989 10 7 12 14 VALERIE 11.6 307.2 87 383 +1960 11 12 12 12 PATTY 35.1 227.9 102 285 +1985 5 8 0 19 ERNESTO 66.5 244.2 94 217 +1954 12 20 18 23 GORDON 59.9 8.5 117 459 +1953 6 10 6 11 WILLIAM 61.2 212.6 67 28 +1975 6 6 0 28 NADINE 29.6 297.7 72 814 +1983 9 18 18 15 OSCAR 10.7 124.0 41 42 +1990 10 24 0 24 LESLIE 27.1 178.5 59 253 +1967 11 21 6 24 CHRIS 8.0 252.7 145 484 +1963 2 7 6 7 LESLIE 54.7 275.9 70 782 +1974 3 6 12 13 ERNESTO 20.8 105.2 68 95 +1980 12 19 18 9 KIRK 46.5 138.1 39 256 +1965 2 17 18 21 BERYL 23.0 89.9 65 439 +1963 2 22 18 1 WILLIAM 67.3 210.7 52 340 +1967 5 13 18 12 HELENE 62.5 195.5 153 795 +1969 8 24 0 2 ALBERTO 14.2 162.7 52 278 +1983 8 20 12 9 SANDY 30.1 226.3 105 635 +1995 12 7 0 11 ALBERTO 62.5 101.5 137 220 +1958 5 23 6 26 HELENE 52.8 304.4 51 54 +2002 10 8 6 5 MICHAEL 11.2 112.5 128 253 +1997 9 9 6 11 FLORENCE 43.8 88.9 123 486 +1984 2 15 6 28 OSCAR 58.4 87.2 139 201 +1992 11 23 6 18 GORDON 64.6 147.4 138 733 +1958 4 3 0 16 PATTY 12.6 243.0 85 384 +1974 4 18 12 16 JOYCE 22.3 223.0 45 246 +1967 11 15 6 18 RAFAEL 36.3 352.2 31 37 +2002 3 16 18 23 PATTY 18.7 258.1 103 885 +1963 9 28 6 7 GORDON 29.2 140.0 50 281 +1954 4 27 12 25 SANDY 14.1 197.9 99 215 +1976 1 3 18 22 WILLIAM 37.7 208.3 159 710 +2001 10 3 12 23 WILLIAM 58.3 141.1 127 279 +1974 2 10 6 28 NADINE 48.7 245.8 75 668 +1953 8 21 12 27 JOYCE 47.8 89.1 36 41 +1991 6 5 12 4 ERNESTO 22.2 349.8 148 606 +1960 5 24 0 12 BERYL 34.4 98.2 98 24 +1990 2 21 12 18 BERYL 11.8 286.5 149 223 +1955 8 11 6 19 WILLIAM 28.6 42.3 94 522 +1953 10 21 18 23 BERYL 52.6 48.2 116 759 +1981 3 12 12 23 RAFAEL 50.2 164.6 97 883 +1965 6 12 0 28 WILLIAM 40.3 18.0 54 630 +1994 12 20 0 20 WILLIAM 32.0 285.1 67 139 +1959 10 21 0 2 NADINE 59.0 116.5 81 134 +1951 1 3 12 11 ISAAC 18.3 305.5 162 268 +1972 2 14 18 4 BERYL 9.4 83.9 34 740 +1965 7 3 18 21 WILLIAM 19.7 149.2 61 12 +1970 9 6 12 21 WILLIAM 53.1 155.2 27 631 +1964 2 23 0 13 TONY 44.0 303.9 64 439 +2000 9 25 6 13 RAFAEL 25.4 160.1 10 304 +1990 11 23 0 27 VALERIE 45.9 264.0 138 361 +1975 6 3 6 9 MICHAEL 37.0 342.8 25 254 +1961 4 16 6 10 CHRIS 55.8 141.0 21 564 +1973 3 5 6 17 CHRIS 12.4 88.2 42 22 +1964 9 15 0 2 LESLIE 21.0 160.6 156 784 +1972 5 15 18 17 VALERIE 69.1 178.9 120 96 +1974 1 7 18 14 BERYL 32.0 285.7 79 756 +1996 12 16 6 18 DEBBY 46.2 355.4 163 259 +1967 7 28 6 15 OSCAR 44.8 279.6 100 366 +1982 6 3 6 21 FLORENCE 11.7 300.8 88 619 +1967 7 22 12 19 MICHAEL 18.4 269.1 45 208 +1997 12 25 12 24 RAFAEL 67.5 266.1 164 565 +1975 10 9 0 23 SANDY 42.4 312.9 41 158 +1994 10 7 6 15 BERYL 15.0 135.2 24 822 +1953 2 28 6 17 CHRIS 36.7 247.3 135 469 +1960 10 8 0 15 ISAAC 15.2 116.3 66 802 +1965 10 26 0 11 ERNESTO 63.7 48.6 122 220 +1956 12 12 0 27 MICHAEL 7.2 301.4 60 5 +2000 7 24 0 21 DEBBY 20.5 297.0 81 782 +2000 1 18 12 15 GORDON 16.6 270.6 52 656 +1957 5 16 12 10 ISAAC 24.7 325.8 112 601 +2001 12 8 0 20 ERNESTO 10.2 271.1 105 744 +1959 12 12 0 2 OSCAR 28.8 178.8 139 715 +1965 3 25 6 6 RAFAEL 54.3 217.1 122 518 +1982 2 5 0 18 BERYL 24.2 113.9 146 304 +1960 2 13 18 26 DEBBY 40.6 343.0 95 223 +1972 5 26 18 27 MICHAEL 16.1 90.7 70 713 +1969 9 2 0 24 WILLIAM 52.5 20.8 38 543 +1963 12 17 12 19 MICHAEL 45.6 187.7 153 169 +1954 3 14 12 12 BERYL 29.7 220.6 63 206 +1964 3 7 0 12 NADINE 26.3 285.0 82 499 +1995 12 6 6 27 LESLIE 42.8 117.6 100 747 +1950 7 9 0 28 ISAAC 59.5 1.1 83 562 +1951 6 19 6 10 VALERIE 16.7 35.9 115 1 +1991 12 22 12 8 GORDON 61.4 144.3 36 362 +1992 5 28 12 14 TONY 41.3 340.5 100 111 +2002 3 19 12 13 WILLIAM 35.4 207.6 162 714 +1962 12 13 0 13 HELENE 42.0 146.4 103 424 +1974 8 2 0 23 OSCAR 8.1 107.7 64 153 +1961 4 21 0 2 ALBERTO 58.2 63.5 156 349 +1988 1 18 18 27 WILLIAM 13.1 168.8 148 764 +1959 5 6 6 7 CHRIS 66.9 332.1 104 97 +1991 8 20 12 19 ERNESTO 59.8 68.4 39 688 +1977 11 6 6 24 GORDON 60.5 344.0 32 193 +1959 3 6 18 22 CHRIS 52.1 27.7 20 599 +1957 12 8 0 25 GORDON 7.7 220.2 133 419 +2001 3 19 12 22 BERYL 23.6 119.6 61 568 +1984 12 7 12 15 NADINE 45.9 316.7 144 458 +1960 1 22 18 19 LESLIE 24.0 271.7 37 18 +1969 7 27 12 19 FLORENCE 48.0 174.6 45 26 +1969 5 7 6 22 PATTY 18.1 221.9 135 569 +1992 4 11 0 1 NADINE 53.7 346.9 148 767 +1960 8 24 6 17 KIRK 44.8 190.8 37 207 +1994 5 13 0 2 ERNESTO 40.3 75.1 119 239 +1957 5 18 12 13 GORDON 48.5 39.8 124 41 +1975 4 5 18 11 KIRK 26.4 150.9 149 63 +1959 9 9 12 20 RAFAEL 22.8 224.4 52 30 +1954 9 1 6 1 ALBERTO 34.3 283.2 110 281 +1965 5 5 12 4 FLORENCE 49.1 63.7 98 291 +1974 6 13 12 28 ALBERTO 17.5 221.5 128 607 +1991 9 9 6 20 FLORENCE 54.1 329.9 52 180 +1955 5 19 12 23 OSCAR 40.1 117.5 73 831 +1980 3 16 18 1 ERNESTO 27.5 208.2 131 271 +1985 6 4 6 5 KIRK 41.2 9.5 158 623 +1973 10 11 12 19 LESLIE 64.3 240.4 37 674 +1989 8 13 6 11 JOYCE 36.2 3.9 20 615 +1981 2 27 12 11 BERYL 43.2 148.5 105 410 +1970 6 14 12 26 RAFAEL 44.7 226.2 135 644 +1977 6 7 18 18 NADINE 52.4 75.5 13 297 +1975 6 27 18 22 JOYCE 39.2 248.3 22 4 +2002 6 3 18 27 OSCAR 31.9 185.8 139 456 +1958 8 7 6 12 CHRIS 38.7 30.1 160 193 +1960 4 24 0 2 HELENE 50.7 136.1 135 646 +1988 5 12 6 14 WILLIAM 35.1 199.8 18 622 +1962 5 22 12 5 JOYCE 53.9 211.0 58 319 +1975 4 10 12 15 ISAAC 33.0 317.5 127 237 +1990 7 22 12 23 DEBBY 64.8 146.8 161 527 +1958 4 18 12 23 OSCAR 64.2 122.9 71 142 +1993 7 11 6 7 WILLIAM 53.8 348.8 148 392 +1995 10 22 0 8 PATTY 65.6 354.7 137 191 +1984 3 12 6 2 SANDY 36.5 184.2 29 190 +1957 2 17 18 9 HELENE 9.5 339.7 25 216 +1996 10 20 18 2 RAFAEL 68.0 275.4 129 548 +2001 4 8 0 10 ALBERTO 28.5 158.8 103 568 +1996 3 15 18 16 SANDY 55.1 47.2 92 147 +1961 12 26 18 1 ALBERTO 67.0 250.2 59 457 +1965 7 28 6 26 FLORENCE 28.1 201.2 140 143 +1986 3 22 12 6 CHRIS 63.3 221.9 105 13 +1982 6 10 0 21 JOYCE 49.9 246.3 164 729 +1991 2 9 6 18 TONY 62.4 134.7 28 719 +1970 7 6 0 18 OSCAR 12.5 101.1 83 855 +1961 7 17 6 8 VALERIE 27.7 156.9 87 590 +1988 12 21 0 25 GORDON 18.3 2.8 21 249 +1953 7 12 6 7 JOYCE 7.1 332.0 139 170 +1974 11 24 6 13 DEBBY 14.6 148.4 74 269 +1992 3 10 6 11 LESLIE 27.5 54.1 132 362 +1976 8 10 6 13 DEBBY 41.8 335.1 87 723 +1991 1 23 0 21 ISAAC 48.6 38.0 20 869 +1963 9 11 18 19 NADINE 33.2 315.2 142 587 +2003 5 5 12 15 KIRK 53.4 10.2 63 698 +2004 11 4 18 13 NADINE 10.2 355.9 33 235 +1959 2 8 12 20 TONY 11.9 312.4 65 314 +1953 4 21 6 20 NADINE 69.5 92.6 82 332 +1964 8 5 0 2 BERYL 61.1 349.8 131 620 +1953 12 24 0 13 KIRK 36.1 288.3 69 260 +2000 8 1 0 26 DEBBY 39.1 354.3 150 43 +1986 10 7 12 9 KIRK 55.5 80.0 44 827 +1993 9 8 0 8 KIRK 63.9 217.4 119 620 +2003 2 18 6 3 BERYL 40.7 217.6 56 447 +1959 2 17 6 21 VALERIE 41.1 5.4 52 60 +1962 8 24 12 20 WILLIAM 9.3 12.1 68 219 +1991 12 24 6 19 LESLIE 21.7 143.7 158 303 +1989 12 3 12 24 MICHAEL 19.4 41.7 164 353 +1986 9 28 12 9 DEBBY 31.9 2.2 105 732 +1996 12 6 0 9 WILLIAM 57.8 258.7 123 705 +2002 11 28 6 1 OSCAR 28.5 182.8 62 840 +1981 10 11 18 22 DEBBY 41.9 17.7 114 73 +1952 7 27 12 1 ISAAC 53.5 297.6 109 173 +1967 1 8 18 3 BERYL 64.2 52.2 27 281 +1979 12 1 6 5 LESLIE 21.9 311.2 156 654 +1996 6 7 0 16 SANDY 21.3 81.5 53 423 +1967 3 16 6 1 ERNESTO 17.6 265.1 135 593 +1958 4 10 18 1 SANDY 45.8 266.9 65 163 +1991 9 19 6 14 NADINE 23.0 28.9 117 766 +1986 10 8 12 25 KIRK 60.8 122.2 28 156 +1952 10 4 18 6 VALERIE 63.5 16.2 89 712 +1952 3 19 18 11 RAFAEL 59.7 10.8 109 414 +1956 2 17 6 3 BERYL 59.7 100.3 77 707 +1976 9 1 0 10 WILLIAM 60.9 202.4 110 742 +1979 3 27 12 24 DEBBY 8.0 115.6 41 895 +1989 7 14 18 19 LESLIE 60.8 100.9 121 259 +1954 10 22 0 12 LESLIE 40.6 282.4 34 731 +1953 10 24 12 23 NADINE 24.7 144.3 105 360 +1966 9 25 18 19 JOYCE 69.7 136.9 101 101 +1983 6 5 6 11 NADINE 47.1 197.9 105 849 +1991 1 13 18 24 BERYL 44.4 276.1 23 620 +1956 10 23 18 5 VALERIE 49.5 288.3 161 488 +1995 8 9 12 25 ALBERTO 60.8 320.2 24 585 +1968 5 14 18 18 MICHAEL 66.3 139.2 81 161 +1993 12 27 18 25 GORDON 28.2 162.4 82 304 +1964 9 26 0 8 BERYL 50.9 200.7 40 103 +1955 11 2 18 12 ALBERTO 55.5 236.9 15 27 +1958 1 23 12 5 MICHAEL 54.1 304.6 162 568 +1983 4 13 18 2 MICHAEL 26.7 318.6 76 198 +1986 7 28 6 5 LESLIE 47.5 158.3 155 504 +1989 9 24 18 4 RAFAEL 63.5 147.6 95 894 +2002 2 7 12 22 HELENE 12.4 141.2 39 567 +1996 11 19 18 22 JOYCE 64.4 310.4 94 747 +1997 4 9 6 8 ALBERTO 19.8 239.6 33 302 +1986 11 7 6 18 RAFAEL 25.2 173.2 164 642 +2004 8 23 18 6 CHRIS 38.1 233.0 30 744 +1983 11 16 18 28 DEBBY 51.9 136.4 90 768 +1960 4 13 0 15 ISAAC 30.5 85.2 160 476 +1953 11 15 0 6 OSCAR 39.7 62.5 95 874 +1977 8 28 12 19 ERNESTO 34.1 351.3 120 35 +1966 8 17 6 9 PATTY 59.7 282.7 100 87 +1978 4 27 18 11 KIRK 40.6 91.9 71 441 +1979 6 19 18 21 OSCAR 45.7 227.7 98 701 +2001 3 13 6 11 WILLIAM 59.3 224.7 76 304 +1965 3 7 18 28 SANDY 68.7 149.6 149 279 +1992 4 14 12 7 KIRK 41.5 343.0 31 697 +1970 11 5 12 22 HELENE 64.9 190.4 51 343 +1989 1 1 6 15 DEBBY 20.5 73.2 60 207 +1964 3 28 18 7 KIRK 50.6 205.2 125 272 +1972 9 21 12 2 BERYL 31.4 224.2 30 6 +1966 10 7 0 16 LESLIE 9.7 118.2 125 752 +1960 3 4 12 24 DEBBY 62.6 200.6 86 777 +1993 1 1 18 2 MICHAEL 10.1 331.6 126 110 +1999 12 14 6 23 ISAAC 68.2 212.7 94 181 +2003 7 3 6 14 PATTY 16.5 291.8 117 262 +1963 10 8 18 25 GORDON 13.0 59.8 134 341 +2000 8 7 0 17 LESLIE 45.6 127.1 60 474 +1993 9 8 6 24 ERNESTO 20.6 5.3 112 44 +1985 4 9 6 7 BERYL 7.5 271.9 143 837 +1995 4 28 0 7 VALERIE 28.8 112.5 68 449 +1986 5 5 0 16 OSCAR 22.6 221.4 87 420 +1975 11 18 12 8 ERNESTO 8.6 117.9 24 388 +1956 3 8 12 21 HELENE 30.4 336.9 150 659 +1989 5 6 18 5 HELENE 50.9 219.6 40 226 +1954 5 17 0 4 DEBBY 50.8 333.3 156 393 +1990 7 23 12 10 NADINE 19.7 35.4 105 823 +1983 10 2 18 26 WILLIAM 64.4 0.6 69 54 +2003 8 15 18 7 CHRIS 53.6 122.9 77 164 +1987 6 24 0 26 PATTY 53.0 80.2 36 427 +1977 7 3 6 21 ALBERTO 63.6 107.1 111 168 +1975 6 10 0 25 BERYL 43.7 100.6 51 295 +1989 5 17 12 2 ALBERTO 28.9 276.2 53 620 +1970 2 11 18 4 OSCAR 39.1 109.8 56 93 +1991 3 27 18 6 ALBERTO 28.8 179.0 146 597 +1984 7 2 0 15 OSCAR 62.7 197.5 71 876 +1966 12 18 18 12 HELENE 12.0 224.6 75 266 +1964 2 13 6 13 ISAAC 40.7 238.6 150 428 +1956 9 21 0 8 JOYCE 67.4 341.7 66 74 +1990 3 12 0 5 NADINE 42.1 320.4 84 768 +2001 10 9 6 1 ERNESTO 29.3 6.3 145 464 +1962 12 15 6 21 ERNESTO 24.7 151.5 10 598 +1994 3 17 6 13 HELENE 42.9 80.0 81 616 +1960 10 13 6 16 WILLIAM 61.0 127.3 114 535 +1988 6 16 0 13 BERYL 41.9 339.6 66 709 +1950 12 17 6 5 HELENE 45.9 196.4 76 299 +1990 1 25 0 8 WILLIAM 19.5 24.6 23 36 +1991 2 6 0 5 PATTY 24.9 312.6 91 682 +1972 6 28 12 8 GORDON 31.1 329.1 100 753 +1970 10 16 0 9 ISAAC 50.8 172.2 45 740 +1991 3 10 12 21 FLORENCE 43.7 223.9 159 148 +1950 6 14 12 24 HELENE 19.8 319.4 70 751 +1982 9 24 6 23 JOYCE 52.4 173.8 45 361 +1972 6 3 6 22 SANDY 37.9 337.2 128 498 +1991 5 22 18 24 JOYCE 33.6 236.9 79 696 +1997 8 15 12 3 MICHAEL 49.5 307.4 147 746 +1981 1 9 12 4 ERNESTO 65.7 34.3 88 131 +1958 7 13 6 1 OSCAR 8.9 101.5 124 748 +1978 11 3 0 16 FLORENCE 44.0 193.8 82 536 +1980 3 13 18 1 CHRIS 53.9 51.7 78 541 +1965 11 27 12 11 ISAAC 63.2 143.1 93 894 +1983 6 10 18 20 PATTY 14.0 351.7 111 329 +1968 6 9 18 9 ISAAC 67.1 118.4 156 798 +1989 11 21 12 27 VALERIE 60.0 308.1 160 559 +1960 7 7 12 23 ISAAC 44.3 253.5 110 441 +1978 5 27 6 16 OSCAR 9.9 19.4 85 146 +1998 7 3 18 9 ISAAC 28.2 331.4 139 629 +1960 1 15 12 17 ISAAC 60.9 272.5 40 177 +1976 4 5 12 24 NADINE 14.7 21.1 81 627 +1953 6 22 12 19 OSCAR 56.9 54.2 22 758 +1969 9 16 12 14 MICHAEL 33.8 19.9 109 637 +1972 7 13 0 13 DEBBY 20.3 346.8 70 458 +1989 2 3 6 4 JOYCE 15.4 142.6 41 349 +1966 7 26 12 27 ERNESTO 57.6 349.7 74 89 +1951 3 1 12 24 PATTY 24.0 229.8 62 595 +1952 11 23 12 2 PATTY 11.6 44.1 95 336 +1978 5 12 12 8 RAFAEL 41.8 133.9 85 536 +1988 1 28 6 15 OSCAR 68.0 231.6 164 222 +1973 3 25 12 28 RAFAEL 38.1 302.1 144 640 +2003 2 2 6 10 LESLIE 49.7 126.0 30 39 +1964 10 9 0 13 ERNESTO 62.2 96.0 154 115 +1955 9 12 18 11 GORDON 67.7 201.5 37 170 +2001 3 6 18 28 GORDON 15.5 45.5 122 627 +2001 2 7 6 9 RAFAEL 40.9 183.0 28 198 +1958 7 17 12 28 TONY 35.1 208.1 64 601 +1983 7 13 18 10 WILLIAM 13.5 136.4 147 532 +1997 5 24 0 1 HELENE 23.2 350.5 78 55 +1981 12 17 12 14 ERNESTO 45.1 154.2 138 83 +1954 3 18 18 28 GORDON 57.8 137.6 112 514 +1962 3 16 6 6 FLORENCE 64.5 21.8 131 735 +1957 3 13 12 15 OSCAR 9.0 277.5 60 570 +2002 8 15 12 27 VALERIE 64.8 196.7 17 250 +1999 5 28 12 5 FLORENCE 8.6 290.4 71 394 +2002 9 8 12 17 NADINE 27.7 77.4 147 635 +1975 11 23 6 18 DEBBY 51.1 352.1 18 526 +1986 3 11 6 13 VALERIE 25.9 162.0 85 161 +1989 8 7 12 23 BERYL 44.8 265.0 160 32 +1992 5 28 6 11 OSCAR 65.2 46.7 148 347 +1983 12 15 6 27 FLORENCE 13.2 279.3 42 497 +1971 4 5 0 17 ISAAC 49.8 337.8 35 755 +1954 9 27 12 12 DEBBY 63.4 126.6 63 492 +1989 3 20 18 7 KIRK 58.7 21.0 36 228 +1975 9 20 18 28 ISAAC 55.2 54.2 10 751 +1976 3 22 12 2 RAFAEL 57.4 193.4 33 757 +1990 3 18 6 20 WILLIAM 21.8 196.7 67 24 +1963 9 28 0 23 ALBERTO 42.3 320.3 51 163 +1996 11 26 0 28 BERYL 49.3 60.9 58 867 +1951 8 6 0 17 VALERIE 27.3 357.5 57 441 +1994 8 8 6 4 TONY 46.0 79.6 76 844 +1958 12 26 18 7 CHRIS 37.6 180.5 59 6 +1994 11 15 18 10 SANDY 17.1 219.9 118 137 +1958 2 15 6 12 FLORENCE 38.9 4.0 54 117 +1989 10 4 0 26 PATTY 34.5 223.1 12 696 +1976 1 13 6 1 FLORENCE 32.1 19.4 147 834 +1955 11 13 12 22 TONY 8.6 73.5 54 317 +1994 2 27 0 3 FLORENCE 29.0 128.6 111 535 +1993 1 20 12 25 MICHAEL 51.6 22.2 44 755 +1950 3 15 12 11 JOYCE 31.6 113.3 44 859 +1995 9 2 12 15 KIRK 50.3 300.6 41 500 +1987 8 21 12 4 NADINE 50.4 105.6 67 411 +1969 5 27 12 15 CHRIS 54.5 244.2 12 480 +1985 5 18 12 9 BERYL 65.9 349.0 92 123 +2001 2 18 18 18 SANDY 20.9 31.5 123 417 +1967 10 3 12 12 WILLIAM 16.8 156.8 125 183 +1996 7 16 0 26 ERNESTO 63.7 321.7 153 816 +2004 6 3 12 28 PATTY 33.1 156.7 27 562 +1967 4 20 12 28 OSCAR 9.6 45.0 60 806 +1999 7 10 12 20 WILLIAM 61.4 306.0 94 800 +1986 12 7 6 5 ERNESTO 31.4 262.2 61 321 +1985 12 9 12 12 FLORENCE 42.5 164.4 40 641 +1983 5 20 12 22 GORDON 20.5 76.7 63 655 +1968 8 16 6 7 JOYCE 55.0 345.0 21 515 +1999 3 19 6 5 GORDON 59.3 311.7 78 228 +1995 6 20 0 6 LESLIE 13.5 137.6 124 145 +1979 2 26 18 13 CHRIS 34.8 301.4 58 201 +1974 8 3 18 27 SANDY 26.5 350.8 115 668 +1961 1 2 12 11 RAFAEL 42.4 246.1 91 744 +2002 5 8 6 6 VALERIE 34.9 91.3 156 401 +1950 4 26 6 3 PATTY 35.9 166.3 135 20 +1966 7 19 12 7 SANDY 20.7 202.8 39 678 +1983 2 24 6 27 VALERIE 29.0 53.8 21 821 +1959 8 7 0 26 RAFAEL 8.8 96.2 91 741 +1975 8 12 0 14 KIRK 69.7 157.8 19 302 +1993 8 8 6 13 OSCAR 8.7 234.2 138 781 +1959 9 16 18 12 PATTY 63.3 257.8 49 528 +1965 2 24 6 3 RAFAEL 10.0 27.1 142 387 +1970 12 22 18 21 OSCAR 15.8 60.5 31 516 +1973 2 4 12 21 HELENE 64.3 327.9 161 349 +1957 3 14 0 13 VALERIE 41.3 340.8 56 850 +1972 7 4 6 2 TONY 14.2 282.9 17 297 +1956 11 12 6 16 JOYCE 7.5 282.1 54 484 +1956 12 16 6 17 KIRK 40.7 91.6 100 372 +1987 5 14 12 21 VALERIE 51.9 157.1 160 262 +1969 12 4 0 5 GORDON 9.5 113.8 84 671 +1961 12 1 18 6 NADINE 53.8 250.2 83 523 +1993 4 23 6 14 OSCAR 21.6 76.7 16 290 +1979 2 6 6 9 PATTY 29.7 304.8 40 773 +1992 12 28 6 13 ALBERTO 45.8 123.8 78 825 +1952 7 15 12 14 BERYL 12.2 223.1 92 654 +1991 9 19 12 17 MICHAEL 49.0 269.2 99 609 +1961 4 24 12 10 ISAAC 23.4 210.6 43 285 +1977 10 13 18 11 VALERIE 48.9 32.3 11 344 +1952 4 8 18 27 WILLIAM 7.1 222.3 125 223 +1952 8 6 6 22 CHRIS 29.0 27.5 142 589 +1970 1 3 0 1 CHRIS 10.1 138.0 105 615 +1976 2 5 0 25 VALERIE 46.2 312.6 96 899 +1951 6 27 12 6 RAFAEL 31.6 129.2 131 381 +1953 11 4 6 23 NADINE 13.4 165.2 29 157 +1986 10 27 12 16 NADINE 46.3 220.3 144 323 +1988 2 1 12 20 ERNESTO 19.8 20.6 80 326 +1982 11 12 18 19 GORDON 18.9 90.4 65 45 +1981 4 17 6 20 DEBBY 68.7 312.7 84 433 +1983 4 2 6 2 SANDY 29.9 219.3 29 815 +1969 9 3 18 23 ISAAC 19.2 208.0 113 681 +1951 11 11 18 11 MICHAEL 39.4 157.4 140 314 +1999 10 19 12 6 NADINE 17.4 310.2 90 256 +1966 6 19 6 26 NADINE 53.6 215.1 43 349 +1993 8 18 0 3 TONY 34.1 112.1 108 893 +1998 5 20 6 1 KIRK 18.1 118.3 151 122 +2004 7 6 18 24 ISAAC 33.6 351.2 131 97 +1962 10 21 6 23 HELENE 7.6 252.7 40 306 +2004 8 14 12 28 MICHAEL 32.1 142.9 67 495 +1962 11 3 18 13 ISAAC 25.9 147.9 80 519 +1977 11 5 12 5 TONY 11.4 348.9 163 405 +1963 4 21 18 21 BERYL 49.1 310.9 87 185 +1987 2 27 18 11 LESLIE 41.2 103.9 109 363 +1962 5 22 18 27 LESLIE 17.0 70.6 114 580 +2001 5 6 18 26 TONY 45.3 351.2 22 793 +1963 9 19 18 8 KIRK 34.8 346.6 31 712 +1970 1 18 0 18 RAFAEL 43.6 36.1 109 167 +1950 7 15 18 10 FLORENCE 47.5 176.0 64 866 +1954 8 12 18 8 KIRK 41.7 256.0 88 772 +1952 6 17 6 5 SANDY 49.9 23.8 91 582 +1952 5 8 12 8 TONY 49.2 299.8 55 894 +1971 3 7 12 16 DEBBY 31.6 41.0 94 436 +1977 1 26 12 20 VALERIE 68.2 65.2 126 157 +1998 9 6 6 21 FLORENCE 68.0 357.2 128 542 +1967 4 5 12 6 VALERIE 27.4 56.1 105 520 +1960 5 15 12 16 BERYL 24.8 212.0 126 850 +2003 4 10 6 7 HELENE 19.6 0.9 52 870 +2000 1 1 0 28 PATTY 56.7 335.8 139 797 +1977 2 12 18 2 NADINE 50.6 190.1 102 44 +1993 8 8 0 12 BERYL 30.0 137.8 55 272 +1984 1 17 6 16 PATTY 44.6 83.7 155 141 +1975 1 1 12 15 ALBERTO 19.1 317.5 32 819 +1955 10 15 18 9 JOYCE 21.2 69.5 33 674 +1951 9 10 12 7 DEBBY 37.2 170.7 73 470 +1962 7 14 18 16 WILLIAM 69.9 269.4 74 178 +2000 2 27 12 19 CHRIS 61.5 63.6 129 391 +1950 12 22 6 7 ALBERTO 22.7 223.9 105 26 +1978 4 21 12 20 FLORENCE 31.9 229.0 110 305 +1968 9 3 0 23 WILLIAM 31.1 204.0 112 899 +1993 10 22 0 15 ALBERTO 17.9 197.4 145 117 +1964 11 12 6 14 LESLIE 66.2 48.9 92 810 +1957 9 19 0 22 FLORENCE 69.8 82.7 21 618 +1990 7 10 6 14 JOYCE 39.9 44.7 105 269 +1950 3 27 12 4 HELENE 48.6 111.5 83 28 +1992 3 28 6 28 GORDON 51.2 158.8 153 57 +1963 2 1 18 24 ISAAC 66.2 11.6 16 34 +2004 4 6 6 18 LESLIE 46.3 157.9 102 228 +1962 5 4 18 25 WILLIAM 42.7 42.2 134 99 +1989 9 4 0 4 ISAAC 7.0 247.4 59 498 +1954 1 6 6 6 TONY 58.1 322.9 36 402 +1974 5 19 18 26 SANDY 24.9 211.3 164 44 +1970 3 14 0 11 GORDON 67.6 78.7 147 701 +1971 1 19 0 1 KIRK 29.2 53.7 90 786 +1969 5 14 18 27 WILLIAM 69.7 296.1 28 140 +1993 2 2 18 18 DEBBY 33.1 152.4 123 44 +1967 8 17 12 9 PATTY 31.0 205.5 79 513 +1988 5 19 18 17 DEBBY 39.3 61.4 109 51 +1956 9 8 6 16 CHRIS 59.7 301.1 44 863 +1965 7 19 18 21 LESLIE 43.4 196.3 131 708 +1965 1 13 0 2 LESLIE 57.5 134.4 56 496 +1984 10 25 6 15 SANDY 46.2 142.8 130 764 +1986 2 3 12 17 TONY 8.3 123.1 81 501 +1962 8 8 18 2 ISAAC 30.7 174.2 141 294 +1953 2 22 12 24 NADINE 40.0 202.8 63 700 +1999 7 8 18 6 HELENE 7.5 52.0 111 735 +1950 4 23 12 11 ALBERTO 50.3 86.9 31 799 +1988 1 2 0 2 CHRIS 66.8 70.4 107 563 +1981 8 20 18 8 DEBBY 58.8 52.3 126 320 +2003 10 25 0 8 RAFAEL 20.5 301.7 114 664 +1951 5 1 18 13 OSCAR 31.8 125.7 87 682 +1966 1 5 18 6 LESLIE 18.5 317.4 118 280 +1982 1 16 12 14 PATTY 29.8 202.9 23 788 +1996 1 19 12 20 RAFAEL 40.9 233.8 151 84 +1950 5 26 6 1 OSCAR 68.1 33.5 55 700 +2000 4 23 0 27 PATTY 33.1 34.7 12 231 +1990 12 16 6 8 BERYL 44.5 253.3 97 500 +1991 12 20 6 5 WILLIAM 26.1 129.0 13 850 +1958 2 16 12 1 CHRIS 57.9 8.1 164 624 +1981 6 5 0 18 JOYCE 47.8 260.7 130 264 +1972 6 22 6 9 BERYL 43.3 173.2 87 203 +1955 3 26 0 4 DEBBY 9.5 220.1 56 639 +1955 9 7 12 24 MICHAEL 38.5 335.6 20 791 +1960 5 23 6 24 ERNESTO 56.1 85.3 114 657 +1970 1 22 12 5 FLORENCE 44.0 31.0 72 184 +1985 1 13 12 5 OSCAR 51.3 20.0 93 549 +1993 5 13 0 16 RAFAEL 27.9 189.9 110 80 +1955 3 15 0 15 HELENE 24.8 175.3 106 207 +1986 5 22 0 28 ERNESTO 46.9 201.4 58 860 +2000 4 4 0 10 HELENE 55.1 297.4 113 419 +2002 1 17 12 14 NADINE 33.7 332.9 63 10 +1998 3 13 6 4 ERNESTO 26.4 195.4 21 754 +1975 6 19 12 9 KIRK 24.7 131.0 102 656 +1974 3 25 12 10 SANDY 12.6 170.5 18 562 +1964 10 11 18 15 RAFAEL 54.0 197.6 29 189 +1971 11 1 0 8 FLORENCE 61.2 30.6 66 261 +1951 11 28 18 4 RAFAEL 41.4 203.4 127 609 +1958 11 8 0 27 KIRK 9.0 98.1 127 353 +1959 4 22 18 20 DEBBY 58.8 117.9 39 764 +1965 5 15 6 8 BERYL 21.5 141.7 156 787 +2001 1 20 18 3 TONY 45.4 78.8 23 513 +1987 11 14 12 15 KIRK 28.6 107.0 119 284 +1986 8 11 6 25 OSCAR 50.3 74.0 77 95 +1997 7 1 0 17 LESLIE 21.7 189.3 53 613 +2002 12 26 0 17 HELENE 35.0 213.7 60 810 +1979 7 9 6 23 BERYL 67.7 244.3 133 684 +1957 8 7 6 8 SANDY 36.0 167.1 77 785 +1953 9 26 0 12 OSCAR 60.4 83.2 38 475 +1957 1 1 0 21 SANDY 16.0 343.9 84 84 +1961 8 24 6 4 RAFAEL 66.0 121.5 140 498 +1969 2 18 18 25 VALERIE 57.7 315.4 101 441 +1959 9 5 12 20 VALERIE 61.1 79.4 97 82 +1996 12 6 0 16 OSCAR 57.7 117.2 102 665 +1950 3 10 6 6 MICHAEL 7.2 20.3 78 629 +1998 1 13 12 7 RAFAEL 49.8 33.3 89 364 +2004 4 22 18 11 RAFAEL 37.4 205.2 156 353 +1981 8 4 6 19 GORDON 54.5 48.9 63 443 +1991 9 20 6 14 RAFAEL 26.6 242.6 161 337 +1964 7 13 18 13 CHRIS 69.6 186.5 82 510 +1952 1 25 0 28 FLORENCE 57.5 301.2 140 645 +1964 11 1 0 26 FLORENCE 56.6 95.0 57 189 +1988 8 10 12 28 CHRIS 47.0 18.7 63 709 +1971 4 22 18 14 OSCAR 46.4 290.1 68 53 +1956 6 11 18 12 HELENE 32.9 171.7 16 308 +1982 8 20 12 21 FLORENCE 14.9 1.7 46 851 +2000 5 3 18 9 CHRIS 46.8 349.0 27 759 +1970 3 9 6 16 ERNESTO 28.7 234.1 122 802 +2001 5 7 0 9 WILLIAM 33.0 342.7 16 842 +1955 11 10 0 22 JOYCE 37.4 319.4 17 784 +1985 4 28 0 28 PATTY 21.0 286.0 56 872 +1986 9 12 6 3 PATTY 25.0 72.0 154 596 +1963 6 10 12 9 VALERIE 31.2 308.3 103 5 +2001 10 12 6 8 JOYCE 69.4 153.7 47 347 +1967 5 10 0 26 JOYCE 8.1 118.5 143 280 +1997 9 15 0 23 HELENE 24.4 116.7 10 885 +1981 6 12 12 22 OSCAR 52.4 147.3 161 657 +1965 9 4 6 11 DEBBY 48.6 18.3 108 398 +1970 8 7 12 1 WILLIAM 21.9 96.3 151 877 +1963 6 1 6 9 SANDY 58.5 137.1 29 469 +1986 1 23 18 13 VALERIE 10.5 332.2 100 226 +1989 6 4 12 24 LESLIE 8.9 55.3 91 661 +1970 2 27 6 16 WILLIAM 47.8 18.3 142 298 +1970 11 3 12 19 OSCAR 10.9 261.4 161 892 +1996 10 23 0 18 BERYL 54.9 172.4 87 94 +2002 9 1 18 10 ALBERTO 37.7 35.2 146 125 +1989 8 10 0 15 WILLIAM 65.2 135.4 163 330 +2004 11 26 12 19 WILLIAM 19.3 55.0 148 263 +1952 12 9 0 23 ISAAC 54.2 330.5 142 145 +1984 6 11 0 25 WILLIAM 65.6 36.7 152 620 +1967 6 28 0 14 SANDY 53.1 18.6 16 634 +1958 10 8 12 25 BERYL 26.1 178.7 138 342 +1951 10 22 0 26 LESLIE 22.0 102.5 24 262 +1998 4 13 12 21 DEBBY 52.8 36.1 68 625 +1981 7 17 18 1 ALBERTO 11.0 267.5 111 158 +1967 4 22 12 1 NADINE 10.0 94.6 114 336 +1983 10 17 0 15 JOYCE 21.1 29.3 69 365 +1977 4 24 18 22 TONY 59.2 29.8 110 849 +2001 10 28 6 26 BERYL 24.3 85.8 82 111 +1982 8 7 12 2 ERNESTO 11.5 41.7 13 292 +1976 2 20 0 9 ERNESTO 23.6 77.6 90 3 +1956 12 13 6 18 OSCAR 18.0 116.6 67 291 +1967 4 16 6 10 DEBBY 49.7 287.3 90 371 +1998 4 13 18 4 SANDY 55.0 24.3 111 535 +1968 9 15 18 11 BERYL 9.7 104.7 12 391 +1973 12 17 12 25 ERNESTO 60.5 9.5 155 620 +2001 11 1 18 6 DEBBY 65.3 345.9 151 311 +1987 8 1 6 6 OSCAR 54.7 316.6 141 628 +1996 2 23 0 4 LESLIE 60.5 311.2 112 242 +1999 11 5 12 7 DEBBY 31.1 200.6 62 853 +1957 4 11 18 5 OSCAR 45.8 36.9 142 233 +1993 12 27 6 13 PATTY 25.7 87.5 49 90 +1980 5 24 6 27 RAFAEL 47.5 187.8 66 357 +1968 5 13 18 15 VALERIE 7.3 314.5 152 314 +1950 9 8 0 16 MICHAEL 25.3 79.8 108 577 +1987 8 7 0 13 PATTY 30.3 123.8 131 245 +1992 3 13 18 14 VALERIE 35.5 249.4 60 564 +1994 4 9 12 10 BERYL 40.3 77.2 34 37 +1984 3 27 18 9 KIRK 44.4 13.3 34 186 +1995 6 1 18 23 VALERIE 55.9 177.7 117 182 +1978 12 3 12 14 RAFAEL 39.0 168.5 159 46 +1992 9 23 18 14 ISAAC 37.9 325.3 91 645 +1992 11 15 0 15 SANDY 24.3 240.3 25 67 +1969 6 13 12 8 FLORENCE 11.9 88.8 66 226 +1977 10 10 18 20 CHRIS 47.6 14.5 130 496 +1971 1 12 18 9 ERNESTO 61.6 35.5 159 322 +1982 7 8 18 14 LESLIE 53.6 245.2 44 884 +2000 2 3 0 5 TONY 32.9 210.5 94 32 +1992 5 6 0 23 SANDY 30.8 174.8 141 343 +2003 2 5 18 16 TONY 10.9 79.0 129 3 +1988 4 2 6 8 KIRK 64.6 169.1 50 705 +1951 1 7 0 3 BERYL 62.4 317.2 121 867 +1970 11 14 0 8 DEBBY 42.6 160.3 90 449 +1952 8 3 18 10 JOYCE 16.7 117.9 52 589 +1966 3 7 6 3 ALBERTO 19.3 224.1 162 411 +1973 3 5 18 20 LESLIE 46.9 138.3 154 734 +1984 12 14 0 19 ERNESTO 21.2 173.1 107 641 +1997 5 9 6 14 ERNESTO 57.1 88.7 35 893 +1998 6 26 18 9 FLORENCE 18.5 298.3 135 76 +1958 9 9 18 13 OSCAR 20.6 279.4 96 782 +1962 9 1 12 22 PATTY 14.1 261.5 127 531 +1954 8 17 18 11 VALERIE 40.1 198.2 106 218 +1968 10 25 6 19 NADINE 21.0 23.4 77 816 +1994 6 28 0 15 LESLIE 65.3 70.0 28 787 +1987 2 14 6 5 TONY 67.2 346.9 100 812 +1976 2 20 6 18 ISAAC 39.0 313.7 135 799 +1970 11 26 0 27 ERNESTO 32.2 232.1 37 632 +1994 6 22 6 6 PATTY 41.1 286.0 38 432 +1988 11 4 6 20 VALERIE 30.6 334.2 148 151 +1963 4 17 6 25 JOYCE 31.2 347.8 139 488 +1967 10 13 0 6 JOYCE 53.2 125.7 147 607 +1985 1 26 12 7 TONY 59.5 27.7 139 491 +1980 10 15 18 21 ISAAC 30.5 288.1 75 384 +1962 11 7 0 19 TONY 18.5 202.0 85 471 +1979 1 27 0 15 BERYL 44.8 90.2 98 868 +1985 5 6 12 12 ALBERTO 52.5 273.5 113 259 +1983 4 25 18 4 DEBBY 42.6 82.0 118 613 +1993 2 20 18 20 ISAAC 44.6 99.4 154 703 +1982 3 16 0 7 PATTY 48.2 292.4 26 493 +1983 2 11 12 7 ISAAC 24.3 226.1 52 359 +1995 6 2 6 14 SANDY 25.8 272.5 116 815 +2002 5 24 0 16 JOYCE 40.1 89.7 68 574 +1967 4 25 18 27 PATTY 20.9 272.7 59 80 +1960 3 9 12 14 VALERIE 54.8 127.2 90 296 +1970 7 27 6 23 VALERIE 56.0 89.0 99 372 +1980 3 21 18 23 JOYCE 45.2 319.0 148 665 +1978 7 18 12 27 MICHAEL 58.4 254.9 43 30 +1998 10 13 6 14 ISAAC 34.2 107.8 136 141 +2002 2 1 12 18 BERYL 20.1 93.0 68 219 +1955 3 16 12 28 KIRK 36.1 193.1 31 892 +2002 3 11 0 12 GORDON 43.9 42.8 128 673 +1952 5 8 0 10 CHRIS 40.1 32.5 41 669 +1978 2 21 18 11 WILLIAM 64.7 235.6 86 742 +1987 1 26 6 18 GORDON 53.4 62.3 107 851 +1987 1 7 18 15 WILLIAM 19.0 97.1 157 507 +1970 5 23 6 10 ISAAC 34.0 205.5 102 718 +2001 2 16 6 28 PATTY 11.7 300.4 158 11 +1989 2 26 0 16 JOYCE 24.9 189.1 126 489 +2003 8 4 18 1 CHRIS 47.2 23.2 26 271 +1956 6 5 12 22 WILLIAM 43.0 62.5 107 321 +1956 12 19 6 21 RAFAEL 55.5 304.4 52 592 +1999 11 8 12 8 TONY 50.4 140.0 24 466 +1968 9 7 0 19 HELENE 26.9 7.0 19 513 +1996 4 16 6 17 FLORENCE 59.3 211.9 13 82 +1968 4 24 18 25 RAFAEL 53.7 194.0 78 149 +1964 8 6 0 4 PATTY 64.5 225.5 69 493 +1980 8 13 0 22 SANDY 36.8 88.4 20 561 +1996 8 12 18 20 CHRIS 47.3 167.5 78 252 +1974 4 1 0 21 DEBBY 60.6 135.3 148 250 +1982 2 14 18 20 TONY 38.7 315.3 139 168 +1955 1 19 18 7 CHRIS 40.2 112.3 15 266 +1955 12 25 0 14 ISAAC 53.3 187.7 75 842 +1997 5 8 18 1 BERYL 59.7 255.3 130 885 +1988 10 12 0 27 FLORENCE 37.4 200.3 136 293 +1974 4 2 18 11 ISAAC 7.3 35.8 129 145 +1959 1 12 18 11 OSCAR 23.8 196.7 142 364 +1996 11 17 6 13 OSCAR 48.1 80.5 13 498 +1952 7 12 12 24 NADINE 51.8 147.9 51 141 +2001 1 21 6 13 GORDON 51.8 86.3 162 574 +1981 2 4 12 11 NADINE 9.4 38.5 48 206 +1977 6 18 12 13 HELENE 55.1 172.3 164 620 +1980 10 22 6 15 TONY 60.2 253.7 155 867 +1950 9 28 12 13 TONY 13.2 104.4 43 154 +1955 5 18 12 25 NADINE 27.8 90.3 85 9 +2001 2 3 12 25 WILLIAM 12.0 26.3 20 622 +1970 7 15 0 20 JOYCE 69.4 274.4 43 600 +1994 8 24 0 24 FLORENCE 69.4 286.0 117 606 +1991 4 3 12 25 PATTY 38.6 76.9 31 893 +1956 5 24 12 21 PATTY 58.7 344.5 68 393 +1995 11 2 0 10 HELENE 69.9 33.2 21 471 +1976 10 1 12 25 GORDON 64.1 64.8 157 490 +1986 5 8 18 15 FLORENCE 8.2 347.2 10 593 +1951 7 16 6 15 JOYCE 28.2 157.5 79 301 +1985 1 5 0 15 JOYCE 59.6 248.9 104 320 +1984 5 9 12 24 CHRIS 50.2 317.9 112 138 +2001 7 1 18 27 DEBBY 50.5 282.0 14 663 +1955 1 16 6 7 ERNESTO 24.4 125.9 151 146 +1954 4 16 12 18 PATTY 59.5 175.2 142 370 +1965 12 16 12 1 WILLIAM 40.7 8.0 73 402 +1995 10 24 0 27 TONY 42.2 224.2 25 687 +1983 8 12 18 28 DEBBY 60.1 34.9 50 12 +1982 6 16 6 8 PATTY 14.7 202.4 14 871 +1992 11 5 0 13 WILLIAM 28.2 178.9 33 561 +1990 4 11 0 28 ISAAC 57.1 51.1 151 674 +1979 1 11 0 12 CHRIS 31.3 65.8 53 115 +1952 6 4 0 12 LESLIE 8.1 323.2 89 408 +1999 10 25 12 26 ISAAC 15.9 122.7 83 285 +2000 6 4 18 26 RAFAEL 51.9 327.6 98 757 +1989 3 9 0 3 TONY 19.8 19.7 72 63 +1983 4 25 6 23 DEBBY 38.7 186.3 156 337 +2001 1 25 18 27 CHRIS 7.0 332.0 49 741 +1952 8 15 18 14 TONY 12.7 26.0 14 18 +1951 8 13 6 6 GORDON 49.6 172.4 164 693 +1973 12 8 6 21 BERYL 54.2 303.3 117 130 +1978 11 23 12 6 ALBERTO 19.4 212.2 126 59 +1957 10 23 6 4 OSCAR 7.5 176.2 19 828 +1978 3 2 0 16 CHRIS 38.8 98.8 23 189 +1988 8 12 6 17 GORDON 60.8 357.8 155 567 +1993 8 2 0 1 CHRIS 24.7 234.6 163 875 +1973 10 4 0 6 OSCAR 12.3 149.9 85 845 +1951 8 9 18 3 TONY 62.1 255.8 42 648 +1979 5 16 6 27 HELENE 66.7 56.3 73 582 +1992 1 11 18 23 HELENE 24.8 21.7 109 110 +1997 9 26 0 21 LESLIE 63.7 270.3 45 742 +1977 8 25 18 16 LESLIE 27.7 117.8 23 873 +1991 9 8 18 13 PATTY 37.5 351.7 16 313 +1999 10 27 18 5 SANDY 16.7 121.2 153 836 +2000 12 3 6 15 JOYCE 21.9 349.6 54 363 +1953 4 1 0 19 HELENE 62.9 280.8 24 355 +1982 11 27 12 10 BERYL 32.3 311.7 160 737 +1993 7 25 12 9 FLORENCE 50.5 229.7 145 315 +1988 9 25 12 4 OSCAR 30.4 317.9 164 448 +1994 6 28 12 10 MICHAEL 46.1 352.6 104 336 +2001 5 20 18 11 VALERIE 50.1 222.1 114 22 +1988 1 7 18 20 ALBERTO 33.9 32.2 115 235 +1975 1 9 12 16 OSCAR 57.9 198.6 24 112 +1992 11 19 18 10 CHRIS 52.6 168.1 79 53 +1964 6 5 12 21 CHRIS 28.8 292.1 154 392 +1998 7 2 18 21 WILLIAM 45.7 215.4 134 85 +1968 9 27 6 9 GORDON 18.0 198.2 140 252 +1984 2 15 18 20 ISAAC 13.1 223.6 108 871 +1987 3 1 6 16 LESLIE 48.7 226.3 116 424 +1957 11 21 0 5 VALERIE 36.7 38.3 15 519 +1973 3 16 0 28 JOYCE 25.1 253.6 14 647 +1984 8 22 18 1 VALERIE 8.5 75.9 121 591 +1952 6 4 18 1 GORDON 50.6 260.0 160 163 +1996 5 13 18 21 NADINE 20.7 171.6 51 689 +1968 6 10 18 5 OSCAR 25.1 221.9 137 871 +2004 3 25 0 25 RAFAEL 65.7 260.9 109 418 +1962 1 22 12 9 VALERIE 34.1 124.7 70 416 +1960 12 21 6 14 DEBBY 47.3 103.8 147 577 +1956 10 13 0 14 BERYL 14.4 85.3 31 563 +1983 6 13 12 6 JOYCE 26.5 337.7 70 160 +2004 2 18 18 15 JOYCE 44.1 237.0 69 149 +2002 4 25 18 24 ALBERTO 52.2 45.2 71 156 +1958 12 21 6 15 MICHAEL 37.7 48.0 34 195 +2004 8 5 6 20 CHRIS 42.7 248.4 90 747 +1957 5 10 0 16 LESLIE 29.3 292.8 54 222 +1966 9 11 12 8 BERYL 69.9 140.2 120 379 +2003 8 15 18 15 MICHAEL 68.8 283.6 36 796 +1975 9 14 6 9 HELENE 28.9 137.8 159 264 +1984 7 9 12 5 TONY 47.5 32.5 21 811 +1995 2 23 6 22 BERYL 15.3 18.4 104 34 +1975 3 13 0 16 TONY 42.8 224.4 128 102 +1961 2 6 12 22 OSCAR 66.5 26.0 161 474 +1952 9 22 18 8 MICHAEL 7.4 145.2 20 854 +2001 1 1 0 9 RAFAEL 10.3 310.5 70 833 +2001 6 24 18 25 OSCAR 52.1 14.9 21 422 +1951 8 18 12 26 LESLIE 9.9 50.5 19 585 +1954 10 12 6 25 ALBERTO 21.6 194.1 154 588 +1991 1 27 12 16 JOYCE 20.3 137.3 114 513 +1982 11 5 12 16 ISAAC 59.5 273.0 18 550 +1954 4 2 6 10 DEBBY 11.9 24.6 47 615 +1950 7 19 18 8 JOYCE 48.4 172.3 85 530 +1967 3 27 12 21 GORDON 36.4 314.9 11 767 +1987 8 5 6 28 FLORENCE 30.1 173.3 148 792 +1969 8 6 6 21 KIRK 63.5 132.6 157 126 +1970 5 20 18 3 NADINE 9.1 218.0 112 36 +1968 1 9 12 12 LESLIE 44.9 170.3 71 347 +1955 12 5 18 26 NADINE 43.1 230.0 138 411 +1976 4 27 18 14 LESLIE 18.0 228.8 49 166 +1986 12 25 6 8 KIRK 55.6 24.1 89 141 +1996 1 23 12 18 ISAAC 19.6 54.2 10 735 +1959 12 23 0 24 BERYL 20.6 213.9 30 448 +1987 1 21 18 2 CHRIS 54.7 336.4 114 455 +1980 3 4 18 15 FLORENCE 58.5 321.5 152 180 +1961 2 7 6 5 KIRK 27.6 269.1 122 578 +1995 11 26 12 1 TONY 42.2 14.7 17 182 +1951 5 3 0 18 KIRK 28.5 7.8 66 7 +1992 4 23 6 18 ERNESTO 61.6 6.5 135 610 +1970 10 17 18 23 SANDY 50.4 338.1 133 756 +1976 10 14 0 20 LESLIE 51.8 162.2 88 211 +1985 8 5 18 1 DEBBY 36.6 351.2 142 88 +1986 4 18 12 23 FLORENCE 69.9 168.6 67 64 +1965 3 8 6 12 SANDY 62.2 140.8 139 318 +1982 6 18 12 24 WILLIAM 28.7 329.2 89 504 +1994 5 20 18 20 SANDY 66.8 257.2 82 105 +1979 12 10 0 9 PATTY 7.3 222.5 40 85 +1993 11 5 18 19 GORDON 11.1 197.3 142 353 +2002 1 8 18 28 CHRIS 20.5 3.7 95 26 +1957 12 8 6 23 CHRIS 37.4 159.0 71 376 +1989 4 7 6 19 OSCAR 27.8 330.0 153 406 +1958 1 4 0 11 JOYCE 43.9 0.3 145 73 +1962 5 22 18 19 ISAAC 67.6 65.3 10 715 +1986 2 17 0 7 PATTY 51.7 80.1 108 195 +1954 9 9 0 11 MICHAEL 37.0 83.1 20 86 +1999 4 13 6 26 KIRK 47.7 276.5 70 246 +1968 2 8 6 16 GORDON 50.1 260.6 49 158 +1979 7 3 18 1 NADINE 27.9 194.7 24 777 +1957 11 24 0 15 MICHAEL 49.7 73.6 116 426 +1952 5 4 12 5 SANDY 32.1 74.5 134 159 +1998 9 24 18 18 ISAAC 29.2 105.3 75 81 +1962 8 21 0 25 CHRIS 56.6 150.9 101 833 +2002 1 2 6 7 VALERIE 56.8 210.7 101 417 +1962 11 23 18 2 BERYL 34.2 20.3 11 70 +2003 10 20 12 12 VALERIE 40.1 143.1 95 665 +1986 3 4 0 23 LESLIE 17.3 1.7 51 152 +1985 8 16 0 25 CHRIS 11.5 194.5 59 821 +1986 5 8 0 22 FLORENCE 17.4 248.9 25 738 +1977 12 25 6 4 WILLIAM 19.6 159.0 86 130 +1964 9 25 0 15 CHRIS 39.6 276.8 52 19 +2001 6 1 12 27 CHRIS 21.9 200.3 12 9 +2004 11 23 6 28 PATTY 7.2 241.5 91 719 +1983 8 12 18 1 HELENE 61.3 17.9 106 533 +1983 7 26 18 28 RAFAEL 21.5 357.1 86 412 +1951 7 10 0 7 DEBBY 59.0 48.9 106 146 +1962 1 14 0 19 MICHAEL 50.9 165.4 147 216 +1980 11 19 18 14 OSCAR 30.9 286.7 90 378 +1978 4 6 0 11 ISAAC 59.0 1.0 56 734 +1971 10 14 0 18 WILLIAM 66.8 308.5 124 371 +1991 6 8 6 14 KIRK 56.7 195.6 135 897 +1977 12 5 0 4 JOYCE 8.3 7.5 27 486 +1968 1 18 12 12 HELENE 16.3 58.2 141 161 +1963 10 25 0 8 HELENE 67.4 79.6 19 603 +1985 12 11 6 20 TONY 55.7 15.1 71 360 +1950 4 25 18 18 DEBBY 47.3 275.2 74 194 +1957 12 27 6 21 DEBBY 7.3 233.0 40 213 +1970 2 21 6 19 LESLIE 10.7 191.4 81 562 +2002 10 25 18 27 ERNESTO 27.7 167.1 56 761 +1968 6 14 6 16 KIRK 12.8 101.7 72 843 +1955 10 1 6 20 FLORENCE 13.1 324.0 61 469 +1959 5 10 12 10 RAFAEL 68.6 173.8 12 866 +1980 9 14 6 24 JOYCE 59.0 281.4 70 860 +1982 8 24 6 19 SANDY 58.9 110.9 135 851 +1998 5 25 12 13 JOYCE 59.5 42.4 94 681 +1998 2 21 18 15 TONY 28.1 115.7 110 405 +1998 4 17 0 4 MICHAEL 55.9 315.8 93 62 +1996 9 11 0 23 PATTY 25.0 33.8 62 443 +1998 4 12 12 12 JOYCE 55.0 136.1 146 831 +1980 9 26 18 12 PATTY 40.2 170.1 131 340 +1997 11 9 6 5 RAFAEL 51.9 281.5 83 558 +2001 1 19 0 25 OSCAR 39.9 277.7 46 214 +1998 7 24 6 18 FLORENCE 51.8 47.3 132 819 +1982 3 15 18 19 GORDON 16.6 310.6 60 456 +1990 12 19 12 26 MICHAEL 67.2 133.5 64 699 +1980 3 9 18 24 ALBERTO 29.7 52.8 162 371 +1995 5 27 6 1 VALERIE 58.1 107.7 61 478 +1956 3 11 6 19 JOYCE 66.8 351.2 83 120 +1968 10 12 12 7 LESLIE 52.4 219.2 100 667 +1979 11 12 12 7 RAFAEL 32.4 239.0 94 384 +1951 3 12 12 3 VALERIE 40.0 216.9 105 736 +1975 5 5 18 25 JOYCE 42.8 134.3 93 324 +1983 8 11 0 22 CHRIS 53.0 333.4 83 813 +1965 11 23 18 24 PATTY 27.0 315.1 161 305 +1954 2 7 12 19 LESLIE 40.8 254.4 13 805 +1989 11 24 0 11 PATTY 46.4 295.1 86 645 +1981 10 1 12 26 ALBERTO 44.7 116.3 163 498 +1952 11 4 0 12 KIRK 39.8 160.1 18 132 +1973 8 12 12 24 TONY 9.3 280.7 53 795 +1997 12 17 18 22 FLORENCE 8.6 205.0 158 258 +1953 9 4 12 18 MICHAEL 56.8 336.0 41 127 +1970 1 13 6 9 ERNESTO 35.6 256.8 154 403 +1989 9 26 18 25 WILLIAM 20.9 279.4 42 276 +1983 7 4 6 4 PATTY 47.2 162.7 96 661 +1977 12 9 6 1 DEBBY 19.1 207.7 75 91 +1976 11 13 0 4 ISAAC 39.5 82.3 159 577 +1979 6 12 0 15 BERYL 42.4 290.9 153 362 +1989 5 5 18 15 OSCAR 64.2 61.1 135 722 +1988 8 27 6 24 SANDY 16.2 49.6 23 711 +1968 12 25 18 22 DEBBY 63.2 187.1 85 713 +1961 1 25 12 4 HELENE 38.1 87.4 76 646 +1958 8 25 18 27 CHRIS 55.6 270.8 139 659 +1966 12 2 12 14 ERNESTO 31.5 148.2 38 629 +1980 7 21 12 2 HELENE 33.8 280.8 42 766 +1951 6 6 12 17 BERYL 66.6 261.6 72 840 +1990 1 4 18 25 PATTY 58.0 217.9 54 104 +1980 8 16 12 1 ISAAC 30.5 158.9 51 608 +1973 1 4 6 8 MICHAEL 52.7 113.6 123 181 +1951 5 22 0 22 TONY 37.9 7.0 135 239 +1995 3 24 12 22 CHRIS 52.1 308.2 83 877 +1987 6 19 0 22 WILLIAM 14.6 131.4 162 362 +1980 9 26 12 13 BERYL 60.0 69.3 115 330 +1989 9 6 18 19 ALBERTO 64.7 330.1 100 628 +1957 4 28 12 15 TONY 8.5 169.0 131 646 +2002 5 2 12 17 HELENE 15.1 252.2 15 588 +1964 3 23 12 22 GORDON 8.4 84.0 33 508 +1971 5 14 12 23 HELENE 8.2 332.4 136 224 +1970 3 27 12 2 ISAAC 33.8 85.7 67 858 +2001 11 20 12 16 ISAAC 25.1 133.2 101 201 +1998 4 9 6 6 SANDY 60.7 156.6 47 113 +1984 10 7 0 19 ALBERTO 16.3 255.3 43 859 +1980 8 27 18 1 HELENE 13.9 55.1 62 268 +2000 1 26 12 5 FLORENCE 37.9 266.0 96 4 +1980 10 7 12 16 ALBERTO 65.3 280.4 148 178 +2000 4 28 18 5 ERNESTO 63.2 228.5 35 566 +1995 8 7 0 9 WILLIAM 21.9 101.8 32 38 +1979 2 14 12 6 MICHAEL 9.5 330.4 17 72 +1956 9 11 18 23 FLORENCE 51.1 169.6 152 253 +1953 5 12 0 3 ERNESTO 19.4 7.2 102 866 +1960 2 16 0 18 OSCAR 23.7 223.0 44 354 +1977 3 3 6 11 ALBERTO 52.0 52.1 94 500 +1996 2 4 18 5 NADINE 8.3 287.4 129 86 +1980 9 21 6 3 CHRIS 16.2 240.6 99 446 +1970 2 26 18 20 PATTY 33.3 267.9 103 637 +2004 10 3 0 23 WILLIAM 64.0 135.8 47 149 +1984 9 9 6 24 WILLIAM 19.2 343.6 103 620 +1986 8 17 6 23 BERYL 68.4 121.9 32 223 +1987 2 3 12 13 GORDON 66.9 176.0 22 210 +1958 2 19 0 10 NADINE 31.9 5.5 22 651 +2000 6 26 6 6 MICHAEL 47.2 119.0 127 496 +1950 3 11 0 10 RAFAEL 55.3 86.2 53 147 +1996 9 18 12 14 TONY 49.1 96.5 10 206 +1971 4 15 12 3 CHRIS 57.3 47.8 118 720 +1952 10 18 18 6 LESLIE 51.1 260.4 33 459 +1954 8 1 18 23 MICHAEL 35.6 291.9 39 381 +1955 5 13 0 26 KIRK 43.7 128.9 120 737 +1992 12 28 6 20 PATTY 62.6 23.9 11 97 +1959 8 18 18 4 ISAAC 38.4 206.5 63 253 +1968 9 16 18 27 HELENE 66.2 337.6 16 586 +1955 11 9 18 7 ALBERTO 52.2 219.8 54 20 +1953 6 1 12 6 ISAAC 10.4 340.5 79 770 +1987 8 8 6 24 ISAAC 44.2 39.5 119 42 +1953 4 21 18 7 SANDY 57.9 123.9 75 325 +1970 6 26 0 4 KIRK 18.4 144.8 41 223 +1987 11 23 18 28 ALBERTO 45.9 102.4 23 710 +1950 9 27 18 9 KIRK 41.5 31.5 46 404 +1974 3 18 18 25 PATTY 36.4 290.2 116 597 +1980 8 28 12 14 TONY 52.5 12.0 55 432 +1961 12 17 6 18 NADINE 53.4 189.5 60 153 +2000 6 14 12 23 ISAAC 31.8 55.0 149 476 +1996 8 5 18 4 OSCAR 15.5 321.9 76 340 +1965 3 9 0 15 NADINE 8.9 117.4 53 285 +2003 12 6 6 26 BERYL 55.2 129.1 85 790 +1959 7 26 6 19 CHRIS 20.4 110.3 79 686 +1956 4 5 0 15 TONY 56.2 216.8 77 848 +1968 1 17 12 19 BERYL 43.9 347.5 76 555 +2000 12 21 6 10 ISAAC 46.1 203.7 50 792 +1961 8 10 6 3 TONY 59.2 209.0 135 277 +1996 2 18 12 8 TONY 28.1 92.1 49 280 +1993 5 15 6 21 FLORENCE 54.8 78.0 125 602 +1982 3 28 6 24 OSCAR 61.8 190.7 104 444 +1955 8 13 12 22 HELENE 33.2 23.1 84 437 +1985 5 5 18 8 HELENE 31.7 21.0 42 90 +1975 6 7 6 3 ISAAC 38.6 320.7 23 777 +1976 2 24 18 22 KIRK 26.8 120.7 30 61 +1951 11 23 6 16 NADINE 69.2 82.8 141 628 +1983 11 27 18 20 NADINE 27.5 46.0 91 200 +1980 6 3 0 12 TONY 47.1 109.5 163 397 +1953 12 6 18 14 PATTY 52.7 226.9 35 659 +1973 5 1 12 4 KIRK 41.6 130.3 113 405 +1958 11 23 6 11 FLORENCE 37.4 220.5 122 106 +1963 4 7 6 22 LESLIE 17.5 330.2 22 833 +1967 3 23 18 20 SANDY 23.8 280.2 17 104 +1994 4 5 0 11 JOYCE 55.5 162.8 104 3 +1996 7 24 6 7 CHRIS 11.8 226.8 79 127 +1976 3 27 12 10 DEBBY 41.5 222.1 90 672 +1987 5 25 0 14 FLORENCE 29.7 274.0 129 574 +2002 4 11 6 9 KIRK 52.6 241.8 19 872 +1986 7 26 0 10 WILLIAM 18.5 112.8 23 315 +1955 3 16 18 14 PATTY 47.6 96.4 130 576 +1961 1 22 18 13 SANDY 24.0 257.2 40 309 +1953 5 21 6 6 SANDY 48.8 296.4 87 799 +2001 3 22 6 11 OSCAR 32.3 165.6 143 117 +1968 3 1 18 3 DEBBY 60.7 210.0 74 196 +1986 9 26 18 17 CHRIS 38.5 250.4 25 891 +1982 5 15 18 24 DEBBY 36.9 306.3 66 833 +1955 4 19 12 13 HELENE 11.3 113.9 41 398 +1958 8 4 18 21 DEBBY 28.7 332.6 159 49 +1952 2 21 18 26 NADINE 28.5 49.9 18 257 +1965 11 23 6 28 ISAAC 52.0 240.9 81 854 +2004 3 9 18 3 NADINE 68.4 259.7 83 343 +1958 11 13 0 1 RAFAEL 42.5 306.4 56 505 +1968 6 23 6 17 PATTY 14.0 163.4 13 716 +1961 1 16 12 13 WILLIAM 52.8 101.2 36 623 +1954 1 1 12 17 DEBBY 37.4 9.6 28 800 +1951 6 22 12 10 NADINE 19.4 86.2 163 355 +1966 5 19 6 6 ERNESTO 23.9 131.7 142 70 +1999 1 14 12 7 RAFAEL 44.4 73.9 156 268 +1959 1 19 0 18 VALERIE 27.6 174.2 76 623 +1979 3 2 0 16 SANDY 8.2 64.9 49 212 +1959 12 24 6 28 RAFAEL 46.8 160.3 93 874 +2003 10 23 18 16 FLORENCE 47.6 46.8 63 593 +1974 4 1 0 24 SANDY 30.3 115.0 146 192 +1997 9 18 0 5 ISAAC 45.0 265.2 76 452 +1985 5 2 12 14 TONY 9.8 104.4 116 701 +1978 1 23 6 25 DEBBY 16.7 327.4 29 538 +1964 8 1 18 8 ISAAC 55.7 302.1 157 635 +1988 2 19 12 9 RAFAEL 15.5 5.4 99 291 +1975 12 4 0 2 NADINE 9.0 2.9 66 742 +1973 2 26 12 11 ISAAC 23.3 75.0 113 548 +1957 4 10 6 6 KIRK 64.9 10.7 138 180 +2001 4 8 6 6 TONY 27.1 207.3 106 161 +1967 1 12 18 9 ISAAC 47.4 75.0 30 574 +1963 8 7 18 23 ERNESTO 56.2 308.1 162 487 +1982 1 2 0 2 RAFAEL 10.2 93.4 87 169 +1976 5 24 6 18 FLORENCE 16.9 245.6 117 107 +1978 6 20 18 5 ISAAC 27.1 27.1 127 778 +1970 1 16 6 26 PATTY 14.0 237.5 48 484 +1969 10 12 0 24 HELENE 38.0 124.5 162 719 +1991 6 5 6 22 FLORENCE 23.1 292.5 32 879 +1990 9 21 0 18 KIRK 45.8 296.1 121 885 +1985 8 6 18 10 JOYCE 49.3 126.9 146 811 +1961 10 25 0 25 SANDY 62.1 290.6 91 867 +1988 4 16 18 8 FLORENCE 27.3 288.3 140 631 +1989 7 13 6 14 NADINE 54.0 0.7 79 388 +1961 7 2 0 2 ALBERTO 44.3 122.9 117 493 +1999 8 2 18 6 ERNESTO 55.6 287.6 143 624 +1966 10 3 6 2 BERYL 8.5 23.3 134 636 +1973 3 4 6 1 MICHAEL 38.3 154.9 20 845 +2003 8 7 0 7 ALBERTO 63.2 343.9 121 574 +1952 7 7 12 14 DEBBY 25.4 310.9 55 796 +1969 12 19 18 4 VALERIE 58.7 99.8 74 139 +1962 5 4 18 4 CHRIS 46.5 286.5 141 220 +1966 5 21 6 23 DEBBY 49.6 100.2 138 780 +2004 1 9 18 28 GORDON 67.5 315.3 111 340 +1970 6 8 0 10 GORDON 58.8 146.0 124 506 +1970 1 20 12 17 OSCAR 9.0 323.6 162 438 +1997 9 24 6 11 FLORENCE 43.4 97.1 121 66 +1989 10 21 0 23 VALERIE 41.7 175.9 140 467 +2003 12 6 0 19 FLORENCE 31.5 313.3 120 746 +1980 1 11 12 1 ERNESTO 65.0 245.5 91 135 +2001 1 23 18 26 ALBERTO 26.5 181.5 133 533 +1990 5 20 12 27 LESLIE 8.6 306.0 90 58 +1970 8 4 18 4 KIRK 65.5 14.9 73 162 +2004 5 9 0 5 NADINE 66.8 235.0 118 153 +1983 3 18 0 2 ERNESTO 13.6 266.5 101 262 +1987 7 22 12 8 NADINE 50.6 303.1 153 760 +1951 7 16 0 24 MICHAEL 10.6 52.8 152 597 +1977 1 2 0 18 LESLIE 42.9 115.4 26 890 +1952 9 3 12 13 RAFAEL 45.3 321.0 135 576 +1974 1 11 18 16 RAFAEL 11.8 178.4 96 321 +1968 5 21 12 20 SANDY 69.5 321.9 107 137 +2003 11 21 6 16 WILLIAM 10.7 313.1 118 498 +1968 11 24 6 25 TONY 12.3 265.8 59 712 +1992 2 23 0 28 TONY 16.9 218.5 95 36 +1959 4 27 0 24 JOYCE 68.0 2.1 54 14 +1995 6 26 0 5 MICHAEL 56.8 233.6 21 174 +1952 7 22 12 13 JOYCE 66.9 51.3 145 213 +1978 5 18 18 16 HELENE 50.5 12.8 150 832 +1999 5 13 18 12 LESLIE 46.1 68.4 62 430 +1983 3 4 12 4 MICHAEL 34.8 139.8 79 576 +2001 1 27 6 19 BERYL 58.9 74.0 82 449 +2004 11 11 18 6 MICHAEL 54.6 219.3 44 892 +2001 9 6 12 2 VALERIE 25.3 215.3 69 455 +1995 1 23 18 26 WILLIAM 57.7 6.4 43 135 +2004 9 26 12 1 NADINE 33.7 75.0 88 758 +1960 10 5 6 11 OSCAR 37.6 278.6 67 120 +1964 5 20 0 24 CHRIS 50.8 327.2 161 6 +1959 3 8 18 3 NADINE 34.1 66.5 90 194 +1965 2 3 18 13 VALERIE 20.8 84.2 149 89 +1995 7 6 6 20 PATTY 55.7 236.1 157 356 +1977 7 8 12 21 LESLIE 16.7 134.0 157 184 +1962 8 27 18 14 MICHAEL 38.7 60.4 101 731 +1991 1 1 0 8 LESLIE 54.3 37.9 33 807 +2003 8 21 18 15 LESLIE 52.3 139.7 86 784 +1954 7 6 18 8 ISAAC 41.7 45.8 36 370 +1998 12 15 6 20 RAFAEL 15.4 24.9 105 642 +1968 1 2 6 26 NADINE 13.8 79.7 36 744 +1979 2 27 0 16 ALBERTO 67.7 67.9 104 166 +1961 1 21 12 11 BERYL 23.7 189.7 153 574 +1977 4 8 6 15 KIRK 66.1 248.9 146 759 +1977 4 2 12 13 MICHAEL 25.4 223.2 43 267 +1992 1 24 12 22 RAFAEL 28.7 278.1 16 879 +1987 4 4 12 12 OSCAR 48.4 288.1 99 350 +1981 10 5 12 15 SANDY 56.9 6.6 111 341 +2000 4 27 12 28 GORDON 48.0 14.9 122 563 +1987 3 22 12 2 KIRK 44.9 92.4 155 70 +1953 2 6 12 11 WILLIAM 27.2 24.7 148 505 +1999 9 4 18 26 ALBERTO 15.6 23.4 116 146 +2002 9 1 12 15 OSCAR 66.8 256.5 100 444 +1959 11 6 18 2 RAFAEL 61.8 344.3 65 113 +1964 10 23 0 13 ALBERTO 44.2 263.0 56 452 +1982 5 9 6 27 NADINE 27.9 231.4 95 778 +2004 12 19 18 12 RAFAEL 31.1 204.5 11 551 +1969 10 14 0 13 ERNESTO 55.6 10.9 163 220 +1957 12 20 6 19 PATTY 20.6 17.0 158 861 +2002 10 4 12 2 FLORENCE 57.5 49.2 10 279 +1984 8 15 18 21 ISAAC 35.0 138.9 77 856 +1958 2 2 18 13 NADINE 53.2 143.7 58 552 +1955 5 20 0 24 MICHAEL 20.5 286.5 14 788 +1971 4 21 0 16 TONY 20.4 71.7 133 147 +1958 4 4 18 28 FLORENCE 16.4 310.6 112 773 +1986 9 10 6 7 WILLIAM 56.2 112.1 95 359 +1960 1 12 18 7 ISAAC 60.3 50.4 14 617 +2002 11 23 12 10 MICHAEL 64.6 65.0 26 626 +1967 5 11 6 11 GORDON 30.1 168.5 25 473 +1970 1 12 6 28 PATTY 48.0 45.9 63 536 +1991 2 19 18 19 ISAAC 69.4 234.3 148 626 +1955 5 1 18 4 NADINE 61.8 282.6 23 729 +1955 2 2 6 27 RAFAEL 62.2 250.7 15 394 +1978 2 22 0 5 JOYCE 33.8 151.2 53 765 +1976 10 8 0 6 OSCAR 56.3 133.4 65 841 +1963 10 8 12 10 VALERIE 53.9 43.5 77 277 +1985 5 8 6 13 ISAAC 20.4 73.9 37 831 +1999 12 11 12 6 NADINE 67.2 83.2 50 724 +1991 6 14 18 16 DEBBY 60.4 197.4 15 819 +1992 11 26 6 12 RAFAEL 45.4 267.1 92 327 +1996 1 23 0 12 JOYCE 41.1 86.5 28 844 +1956 11 8 0 15 NADINE 8.9 331.2 122 780 +1978 9 3 6 8 SANDY 52.2 259.8 86 78 +1989 1 5 6 7 NADINE 11.7 326.8 97 163 +1964 4 10 0 21 BERYL 20.2 260.2 51 737 +1969 2 9 0 24 GORDON 11.4 162.6 152 382 +1966 8 22 6 24 ERNESTO 44.3 242.1 82 292 +1980 1 21 6 3 HELENE 53.3 68.5 76 445 +1967 3 26 18 14 LESLIE 14.7 111.0 97 773 +1976 1 9 12 7 HELENE 52.2 102.6 39 406 +1951 6 3 18 17 FLORENCE 44.0 39.9 121 716 +1980 8 3 18 18 VALERIE 10.5 68.5 157 840 +1972 2 14 6 22 DEBBY 47.2 226.8 122 298 +1956 3 19 18 6 CHRIS 49.6 172.1 33 377 +1981 4 26 12 5 NADINE 22.5 239.8 65 758 +1968 12 1 12 6 NADINE 42.7 92.3 53 765 +1994 12 13 18 22 TONY 33.0 87.2 26 829 +1954 2 24 18 18 HELENE 25.8 122.7 120 588 +1977 4 26 6 3 DEBBY 42.0 230.5 58 558 +1977 5 16 6 3 HELENE 35.4 194.1 50 733 +1971 3 7 0 9 OSCAR 64.2 345.0 33 395 +1970 9 1 12 28 ALBERTO 12.6 16.5 151 283 +1977 9 28 18 3 BERYL 22.0 27.4 119 658 +1952 9 4 12 6 MICHAEL 15.5 165.4 110 296 +1952 7 1 6 15 RAFAEL 15.5 39.3 45 627 +1989 10 16 6 22 LESLIE 60.9 259.6 54 36 +1966 10 28 0 15 BERYL 9.8 293.4 54 125 +1977 6 3 18 2 CHRIS 65.5 318.6 155 305 +1987 5 28 6 15 WILLIAM 32.4 262.9 62 630 +1975 12 26 6 1 LESLIE 34.2 236.9 71 355 +1984 4 13 12 14 GORDON 20.8 90.2 95 68 +1999 2 15 6 15 OSCAR 10.1 60.0 127 299 +1992 8 6 0 28 HELENE 27.1 337.9 155 127 +1997 9 7 18 11 FLORENCE 42.3 301.4 100 678 +1968 10 11 6 14 FLORENCE 8.6 77.9 149 95 +1959 9 26 0 5 CHRIS 53.1 91.2 117 308 +1985 6 9 18 4 VALERIE 59.8 54.4 31 180 +1964 11 28 18 4 JOYCE 41.0 53.2 70 107 +1977 7 6 12 16 VALERIE 67.4 29.3 39 518 +1994 4 16 12 15 ISAAC 28.6 113.1 73 414 +1953 4 21 0 19 PATTY 7.0 212.6 44 360 +1999 11 4 12 1 KIRK 62.5 322.2 164 514 +2003 1 1 18 22 NADINE 52.1 196.5 37 150 +1953 12 6 0 5 KIRK 36.1 146.3 76 848 +1992 2 25 0 1 PATTY 32.7 204.2 135 132 +2003 5 23 6 6 ALBERTO 47.0 180.5 75 208 +1998 1 12 12 12 JOYCE 30.7 67.4 149 329 +1959 7 26 0 6 ISAAC 51.1 204.9 64 433 +1991 7 15 0 23 ERNESTO 52.2 213.9 134 850 +1978 2 23 12 5 SANDY 25.3 49.7 86 516 +1986 10 3 12 21 VALERIE 10.5 300.5 87 473 +1995 10 10 18 3 RAFAEL 37.4 165.6 149 409 +1954 2 15 6 28 KIRK 44.4 63.7 142 621 +1968 4 6 12 22 GORDON 62.7 35.0 134 557 +1976 12 9 12 16 LESLIE 58.8 229.2 153 330 +2001 12 8 18 4 ERNESTO 27.5 26.5 13 876 +1974 6 11 18 27 PATTY 59.6 75.3 138 622 +1956 5 24 18 6 CHRIS 20.3 13.8 66 72 +1975 11 28 12 5 TONY 16.1 309.4 80 767 +1987 6 23 18 27 LESLIE 36.6 325.6 70 753 +2002 11 21 18 24 NADINE 32.4 134.1 67 169 +1975 9 26 0 22 TONY 61.8 138.0 46 557 +1968 2 8 6 11 ALBERTO 22.8 244.6 98 118 +2004 9 22 6 27 PATTY 17.2 272.4 21 93 +2002 11 23 18 17 NADINE 47.4 157.9 156 258 +1991 7 28 12 10 FLORENCE 20.4 41.7 115 662 +1957 5 28 6 5 BERYL 8.2 75.3 137 568 +1998 2 19 6 9 TONY 47.8 189.6 114 442 +1967 3 4 6 8 BERYL 52.4 118.7 116 822 +1969 12 28 0 4 GORDON 68.9 311.1 155 329 +1986 7 14 12 10 BERYL 62.0 337.7 12 713 +1959 9 6 0 8 ISAAC 63.4 24.8 27 810 +1996 8 12 18 19 DEBBY 49.7 327.2 132 486 +1986 2 10 18 21 TONY 38.2 327.5 18 784 +1978 5 13 18 11 DEBBY 25.9 329.5 119 553 +1963 1 1 0 23 ALBERTO 47.1 22.2 145 342 +1973 3 13 12 25 SANDY 8.8 171.8 135 157 +2001 1 19 6 22 NADINE 8.5 175.4 50 323 +1967 11 20 6 6 VALERIE 21.0 94.4 126 760 +1994 11 21 6 21 ISAAC 34.9 96.8 149 749 +1993 6 22 0 28 FLORENCE 45.6 63.3 108 532 +1980 8 11 0 12 DEBBY 36.3 263.6 90 852 +1963 11 23 6 4 GORDON 24.2 221.7 97 419 +1987 6 22 6 16 FLORENCE 60.5 146.5 121 119 +1999 8 17 0 5 HELENE 29.5 223.6 128 656 +1974 1 11 0 5 WILLIAM 67.5 258.4 88 232 +1997 5 20 12 20 BERYL 14.6 162.9 149 242 +1979 2 4 12 21 SANDY 21.9 264.4 139 132 +1979 6 11 6 11 VALERIE 27.8 224.2 157 192 +1952 8 13 12 18 JOYCE 55.0 123.3 125 191 +1991 4 2 0 21 GORDON 44.9 250.8 22 855 +1971 4 16 0 16 CHRIS 34.2 357.9 49 182 +1963 2 1 6 22 NADINE 67.9 34.0 150 841 +2004 7 3 6 18 RAFAEL 39.3 155.9 160 10 +1953 10 2 18 6 SANDY 34.5 90.9 130 673 +1984 10 7 18 7 LESLIE 67.9 162.5 158 535 +1977 5 1 6 8 LESLIE 21.8 264.5 66 224 +1964 6 20 0 12 GORDON 59.8 339.4 162 599 +1955 11 11 0 10 PATTY 12.2 150.5 22 66 +1951 2 28 0 15 TONY 59.1 16.8 141 228 +1950 8 11 6 3 DEBBY 58.1 148.0 116 888 +1951 10 20 0 19 TONY 35.1 119.0 22 216 +1984 2 11 0 14 PATTY 27.8 228.7 97 387 +1972 11 5 12 6 RAFAEL 46.5 199.2 56 725 +1989 6 14 0 19 GORDON 58.9 280.6 158 671 +2002 4 13 0 19 RAFAEL 43.0 351.6 43 282 +1973 11 22 18 5 HELENE 28.4 265.4 16 271 +1978 8 6 6 10 RAFAEL 50.5 139.9 57 473 +1993 1 19 6 24 SANDY 31.0 277.0 95 9 +1992 4 9 18 14 RAFAEL 41.9 334.4 115 804 +1955 11 22 18 25 OSCAR 57.3 126.5 10 661 +1972 1 21 12 10 JOYCE 26.7 329.3 29 332 +1975 1 17 12 17 SANDY 23.8 156.8 104 228 +1980 4 17 18 15 NADINE 56.5 357.1 68 51 +1980 1 7 18 21 NADINE 45.9 330.5 156 333 +1992 9 10 0 24 HELENE 18.8 184.9 164 382 +1956 12 26 18 4 FLORENCE 46.5 277.4 95 283 +1997 2 8 0 17 VALERIE 18.2 207.5 36 400 +1962 7 1 0 23 GORDON 41.1 130.2 139 466 +1958 6 14 12 10 ISAAC 68.4 125.3 76 386 +1955 12 12 0 7 MICHAEL 62.5 270.0 126 661 +1973 6 18 18 27 FLORENCE 60.4 51.9 17 870 +1959 5 12 0 26 ERNESTO 52.7 117.2 150 377 +2002 1 12 0 18 LESLIE 18.5 323.9 54 761 +1975 7 19 18 25 BERYL 65.2 22.0 123 287 +1969 6 12 0 19 KIRK 9.2 72.9 50 149 +1962 5 8 12 19 VALERIE 56.8 304.2 162 795 +1973 1 19 12 17 FLORENCE 52.7 26.6 55 248 +1985 11 28 0 20 LESLIE 67.4 115.4 88 850 +1976 10 19 0 12 BERYL 67.1 250.8 91 219 +1980 12 13 0 21 KIRK 49.2 243.7 105 619 +1997 12 18 12 13 OSCAR 26.9 139.2 142 235 +1982 11 19 18 9 PATTY 28.7 161.2 132 147 +1955 4 28 18 4 KIRK 66.4 87.7 148 412 +1998 10 27 6 17 OSCAR 45.3 118.4 77 740 +1994 8 19 12 19 CHRIS 20.4 61.9 133 548 +1952 7 24 0 15 OSCAR 24.4 211.1 51 758 +1993 11 12 0 14 CHRIS 27.9 96.9 94 262 +1994 12 4 6 24 SANDY 42.3 356.7 30 40 +1996 6 9 12 5 VALERIE 36.8 52.9 142 669 +1997 7 2 0 6 GORDON 19.3 250.7 72 145 +1969 2 19 0 15 OSCAR 38.1 326.7 89 493 +1951 7 11 18 11 WILLIAM 31.9 21.4 112 58 +1979 10 21 12 12 GORDON 16.0 258.7 74 314 +1991 4 22 6 21 LESLIE 10.6 164.8 136 710 +1960 1 18 6 6 ERNESTO 66.2 227.8 116 521 +1997 5 15 18 7 PATTY 29.2 242.0 64 564 +1987 4 25 6 13 JOYCE 68.4 257.1 49 797 +1963 2 8 12 6 ALBERTO 12.4 248.9 108 494 +2003 5 15 6 19 GORDON 46.3 344.0 34 62 +1975 12 19 0 13 JOYCE 55.3 3.5 70 223 +1993 10 12 0 24 CHRIS 8.5 245.6 20 46 +1980 1 10 12 10 JOYCE 68.5 176.6 33 328 +1966 5 18 0 22 KIRK 47.4 315.5 114 212 +1989 4 10 6 21 ISAAC 16.9 109.7 132 93 +1984 11 24 12 18 DEBBY 67.1 283.9 124 672 +1995 1 6 0 28 DEBBY 58.1 47.7 158 389 +1958 7 10 0 3 ALBERTO 42.0 324.4 13 805 +1960 5 18 12 25 MICHAEL 17.9 282.3 98 53 +1994 12 3 12 9 ISAAC 44.5 227.0 154 101 +1955 10 22 0 19 RAFAEL 58.0 348.0 75 519 +1997 2 27 18 25 LESLIE 56.2 242.1 149 240 +1960 12 22 6 5 FLORENCE 35.6 237.7 95 153 +1994 10 23 6 25 VALERIE 9.6 172.9 57 794 +1954 9 16 6 27 NADINE 25.2 272.6 130 362 +1957 9 15 18 28 TONY 60.3 254.5 54 536 +1954 4 19 6 24 FLORENCE 37.3 89.4 76 141 +1983 8 11 18 23 NADINE 59.9 328.5 106 567 +1997 8 25 12 18 FLORENCE 44.7 254.1 22 873 +1974 7 2 12 21 TONY 13.9 250.6 94 665 +1982 11 9 18 27 FLORENCE 44.7 71.8 118 471 +1997 11 1 6 8 ERNESTO 41.8 2.4 50 509 +1967 2 27 6 24 MICHAEL 63.2 313.6 157 891 +2000 6 4 12 25 TONY 42.9 296.6 95 623 +1973 7 23 0 3 JOYCE 31.1 124.5 84 187 +1959 10 15 0 9 SANDY 8.8 259.8 46 413 +1969 2 13 6 27 TONY 18.3 85.6 115 137 +1972 5 20 12 21 WILLIAM 9.7 303.7 88 235 +1958 7 1 0 6 MICHAEL 12.2 159.2 135 403 +1988 1 19 12 28 HELENE 69.8 69.3 117 306 +1981 6 26 0 21 TONY 57.6 49.0 81 856 +1974 7 27 6 14 VALERIE 31.1 148.9 63 286 +1999 6 28 6 13 FLORENCE 15.3 328.2 80 60 +1951 1 17 6 25 LESLIE 40.8 99.4 76 36 +1989 6 9 0 25 RAFAEL 10.2 286.8 129 396 +1970 8 25 6 25 SANDY 46.4 120.0 90 525 +1976 5 26 12 13 VALERIE 68.9 203.6 69 495 +1968 10 4 12 20 PATTY 66.1 19.8 136 479 +1990 11 9 0 13 NADINE 51.9 299.3 66 291 +1966 6 26 0 17 ERNESTO 46.9 148.4 102 827 +1988 7 12 6 22 HELENE 25.1 139.7 59 511 +1983 3 20 12 6 SANDY 29.9 80.4 102 274 +1970 6 10 12 20 ISAAC 22.5 192.6 10 853 +1957 3 26 6 12 RAFAEL 49.2 167.9 75 614 +2002 7 8 12 2 FLORENCE 52.9 308.1 113 769 +1961 8 20 18 2 SANDY 31.7 280.6 54 467 +1988 9 18 6 5 CHRIS 66.0 153.2 73 470 +1966 1 14 12 15 ERNESTO 19.9 210.0 17 363 +1969 6 3 0 24 NADINE 29.3 242.2 42 186 +2004 6 4 0 1 LESLIE 14.1 98.5 37 704 +1997 6 2 18 5 KIRK 28.3 320.8 134 159 +1974 8 8 6 20 NADINE 63.5 52.5 155 594 +1959 5 15 12 28 GORDON 29.7 341.1 137 525 +1950 12 6 12 12 JOYCE 7.1 80.3 121 208 +1982 3 27 0 14 DEBBY 17.2 109.4 140 865 +1967 7 3 12 3 MICHAEL 54.7 267.0 144 865 +1973 6 8 18 8 WILLIAM 8.7 166.7 21 845 +1998 5 20 0 6 KIRK 38.0 117.5 129 188 +1965 4 18 18 5 CHRIS 48.6 101.0 90 85 +1963 5 3 6 19 ALBERTO 14.8 107.1 62 2 +1956 2 16 12 13 VALERIE 14.3 286.9 34 58 +1973 2 21 12 25 DEBBY 68.0 266.5 20 728 +1999 2 22 18 12 ISAAC 57.4 214.0 111 23 +1962 2 6 6 14 FLORENCE 15.2 118.0 93 787 +1972 3 17 0 16 ERNESTO 14.2 292.4 81 44 +1973 10 17 12 7 BERYL 42.1 317.8 132 406 +1955 11 28 6 19 NADINE 10.7 218.8 78 399 +1952 7 10 6 1 WILLIAM 42.8 97.4 49 41 +1999 9 19 12 4 BERYL 67.3 260.8 106 214 +1992 1 8 6 6 HELENE 12.1 236.0 77 658 +1960 9 26 12 6 JOYCE 17.1 343.6 80 823 +1961 5 13 18 12 ERNESTO 42.4 117.2 162 165 +1981 3 12 12 8 OSCAR 31.7 248.3 124 39 +1994 12 3 6 14 BERYL 23.1 161.8 56 254 +1950 9 20 18 2 DEBBY 47.8 126.0 69 646 +1986 1 1 18 11 FLORENCE 55.0 6.5 98 557 +1998 6 18 12 18 MICHAEL 47.1 131.1 111 170 +1989 10 28 18 2 RAFAEL 17.1 286.4 49 406 +1959 6 19 18 7 ALBERTO 30.9 26.3 31 158 +1955 10 16 18 10 PATTY 17.7 298.8 128 495 +1961 6 22 0 16 ISAAC 24.0 326.2 83 622 +1981 6 13 6 20 BERYL 60.3 289.4 17 822 +1973 7 12 6 28 GORDON 53.7 71.2 94 384 +2003 8 27 12 22 PATTY 53.8 285.4 12 786 +1982 12 5 6 23 LESLIE 59.5 313.9 158 699 +2002 12 12 0 2 CHRIS 19.0 1.4 26 596 +1957 10 23 6 15 ALBERTO 35.7 18.7 40 534 +1961 4 21 0 15 OSCAR 34.9 282.3 55 144 +1972 4 24 0 15 ERNESTO 65.6 307.7 157 547 +1986 9 27 0 24 ISAAC 57.5 159.4 104 68 +1992 4 26 0 14 HELENE 8.4 336.1 12 804 +1968 4 1 6 15 SANDY 43.0 6.8 25 788 +1950 6 21 12 13 HELENE 40.2 33.5 23 868 +1989 4 19 6 16 MICHAEL 29.0 7.3 130 203 +1953 1 22 18 7 ERNESTO 18.6 245.8 147 729 +1983 8 25 12 23 SANDY 64.8 162.0 12 413 +1954 2 21 18 8 BERYL 44.3 281.5 123 826 +1998 8 26 18 19 ERNESTO 14.9 299.4 154 179 +1997 2 22 12 27 JOYCE 69.2 211.5 114 796 +1999 2 2 18 5 BERYL 34.1 347.8 99 504 +1950 4 18 6 13 ERNESTO 9.9 86.1 40 836 +1957 7 5 12 23 LESLIE 44.3 296.8 89 200 +1979 3 20 18 1 HELENE 54.8 92.9 135 356 +1977 6 25 0 8 OSCAR 56.4 247.9 132 443 +2003 2 10 6 6 JOYCE 38.6 212.9 114 612 +1995 11 5 12 4 ISAAC 56.8 43.6 14 362 +1972 4 7 6 9 HELENE 11.7 241.3 136 624 +1995 2 1 6 23 FLORENCE 36.9 303.4 61 489 +1952 9 23 18 11 OSCAR 17.8 69.4 88 412 +1951 6 6 0 24 LESLIE 29.4 65.8 17 347 +1994 9 20 6 19 OSCAR 30.9 204.0 71 247 +1975 3 23 0 7 GORDON 24.5 67.6 129 18 +2000 8 8 0 13 JOYCE 37.2 225.7 105 743 +1987 11 23 12 4 MICHAEL 31.9 331.0 88 804 +1985 10 28 0 16 KIRK 8.8 107.2 143 517 +2004 10 22 0 5 GORDON 11.2 312.6 136 431 +1969 1 20 18 20 OSCAR 47.5 238.7 87 407 +1980 9 10 6 23 RAFAEL 37.7 297.9 34 775 +1988 6 1 6 3 PATTY 56.6 256.1 154 394 +1964 2 12 18 16 DEBBY 33.5 93.2 142 639 +1972 5 2 12 21 JOYCE 9.9 111.0 30 58 +1997 8 26 12 28 WILLIAM 43.7 263.7 93 97 +1985 5 17 6 9 LESLIE 40.2 9.5 36 841 +1954 7 12 18 25 WILLIAM 60.2 217.2 24 620 +1966 12 3 0 7 KIRK 15.7 60.7 31 489 +1973 5 21 6 18 PATTY 64.7 173.1 162 699 +1966 3 8 6 14 GORDON 59.8 286.0 115 523 +2004 11 19 0 13 NADINE 38.4 19.3 134 295 +1950 12 25 12 26 VALERIE 23.6 34.0 149 561 +1972 12 19 0 4 LESLIE 64.3 135.2 62 58 +2000 2 3 0 19 NADINE 24.6 30.8 108 343 +1952 1 5 6 10 GORDON 33.7 116.0 80 763 +2002 5 15 6 22 ERNESTO 11.7 290.0 113 129 +1968 9 27 18 13 OSCAR 44.6 294.4 33 183 +2000 11 9 0 8 ISAAC 19.9 168.5 109 386 +1952 1 11 18 15 ERNESTO 44.6 318.1 153 40 +1969 9 23 18 15 TONY 49.9 328.2 84 780 +1958 12 20 18 10 KIRK 55.8 271.8 117 55 +1977 7 22 18 3 KIRK 47.0 241.5 61 561 +1975 5 17 6 16 FLORENCE 24.0 268.3 138 87 +2001 12 18 12 20 VALERIE 40.2 29.9 52 475 +1998 11 15 0 13 PATTY 22.0 339.5 98 244 +1978 12 3 18 16 GORDON 31.6 186.7 134 393 +2001 4 21 0 15 CHRIS 35.7 116.8 84 112 +1985 7 14 0 9 FLORENCE 32.0 110.5 146 270 +1953 3 27 0 11 PATTY 34.9 80.0 83 210 +1990 7 3 18 9 GORDON 25.1 98.4 65 180 +1983 8 18 18 10 ALBERTO 67.5 133.3 25 10 +1997 9 12 6 19 ALBERTO 62.7 201.5 132 760 +1955 6 8 0 11 PATTY 21.0 208.6 159 656 +1985 1 28 6 1 OSCAR 17.1 272.9 41 268 +1959 8 27 0 26 MICHAEL 63.6 74.5 135 550 +1950 10 23 6 27 BERYL 16.0 265.9 19 598 +1974 6 28 0 9 ISAAC 43.1 27.5 149 98 +1969 9 16 12 25 DEBBY 27.4 67.7 20 751 +1970 1 12 6 9 KIRK 24.0 200.9 126 214 +1968 1 3 12 16 HELENE 41.7 205.3 18 627 +1971 8 23 12 19 PATTY 41.4 312.3 49 874 +1967 2 22 0 17 ISAAC 39.9 336.2 63 815 +1971 1 1 18 2 WILLIAM 18.4 2.8 41 436 +1974 7 7 0 1 LESLIE 44.0 232.1 68 106 +1987 2 20 0 11 BERYL 16.4 153.5 106 764 +1953 10 3 0 27 ISAAC 45.8 175.4 140 149 +1962 5 24 6 21 FLORENCE 7.7 4.9 80 826 +1964 4 18 0 3 PATTY 48.6 222.1 53 390 +1976 10 7 6 9 MICHAEL 56.8 325.8 44 19 +1966 2 16 0 8 PATTY 33.2 96.3 95 680 +1991 1 1 18 7 PATTY 7.9 192.5 162 107 +1982 4 12 12 22 FLORENCE 62.8 121.5 143 849 +1983 2 26 18 18 GORDON 45.8 8.4 99 265 +1979 5 17 0 4 HELENE 38.8 55.7 136 360 +1964 4 3 0 25 ISAAC 49.8 45.8 148 154 +2001 6 3 18 10 BERYL 43.8 41.2 150 604 +1978 7 16 0 17 JOYCE 64.5 27.1 79 315 +1951 12 22 18 27 PATTY 37.5 123.8 98 0 +1990 10 4 6 6 JOYCE 36.6 186.6 147 56 +1973 7 4 0 18 VALERIE 40.6 23.6 138 687 +1998 5 18 6 25 ALBERTO 59.9 34.2 163 174 +1985 1 21 0 18 WILLIAM 11.4 56.4 19 77 +1977 6 18 12 11 ISAAC 31.2 302.4 152 264 +1980 1 10 12 18 WILLIAM 61.8 331.7 101 96 +1960 12 7 18 8 ALBERTO 32.1 255.7 157 419 +1954 9 9 12 12 HELENE 59.1 156.5 13 51 +1986 1 26 6 26 OSCAR 38.9 282.3 55 625 +1967 12 2 6 17 RAFAEL 28.3 131.1 44 340 +1986 11 27 0 7 KIRK 16.4 292.4 149 651 +1962 8 16 12 24 ALBERTO 31.8 18.8 131 189 +1999 5 20 12 1 GORDON 52.8 319.1 111 667 +1978 4 1 6 13 OSCAR 51.6 121.3 132 588 +1970 10 12 6 7 RAFAEL 61.2 302.6 73 775 +1990 12 15 12 21 PATTY 39.1 23.1 121 353 +1984 9 15 6 12 VALERIE 40.2 324.4 136 248 +1961 1 28 6 15 LESLIE 20.4 115.0 89 555 +1980 3 15 6 28 RAFAEL 34.6 317.5 130 205 +1984 6 22 18 11 ALBERTO 21.6 322.5 19 126 +1950 12 1 6 18 KIRK 17.5 143.5 49 650 +1997 10 10 12 26 GORDON 43.0 225.5 58 605 +1965 1 27 0 3 LESLIE 36.4 293.7 151 389 +1977 8 11 12 23 CHRIS 36.3 44.7 32 139 +1966 4 27 18 1 BERYL 60.0 344.4 55 50 +1953 11 20 12 13 CHRIS 14.4 225.0 63 662 +1957 8 9 0 3 ISAAC 50.3 58.8 83 780 +1985 6 5 6 28 HELENE 7.5 222.5 17 467 +2004 7 24 0 1 ISAAC 56.3 59.6 67 355 +1951 4 6 0 2 JOYCE 29.3 121.8 118 490 +1988 1 28 0 12 SANDY 29.5 115.3 74 365 +1984 2 21 0 24 JOYCE 20.7 164.5 87 647 +1974 8 26 6 1 FLORENCE 8.5 177.4 11 412 +1997 2 4 18 20 WILLIAM 32.0 281.5 39 323 +1952 11 23 12 8 MICHAEL 68.1 224.8 155 417 +2001 11 20 6 2 NADINE 61.8 122.4 92 161 +1989 9 12 18 10 CHRIS 56.5 233.6 129 88 +2001 1 10 12 7 DEBBY 13.8 143.1 158 776 +1988 3 13 6 24 ERNESTO 60.3 66.0 60 636 +1962 10 2 6 15 ALBERTO 10.1 214.5 74 782 +1996 5 22 12 15 OSCAR 65.3 91.3 74 554 +1988 5 27 0 23 ALBERTO 65.0 190.3 53 532 +1987 9 13 6 15 ERNESTO 15.4 94.1 87 788 +1957 11 7 6 25 DEBBY 49.4 163.4 108 207 +1950 12 22 6 17 NADINE 67.2 92.9 58 826 +2000 12 1 6 25 TONY 59.0 309.7 66 346 +1982 12 9 6 5 PATTY 20.7 287.2 81 74 +1989 2 25 6 28 BERYL 36.1 175.7 159 835 +1975 5 23 0 25 ISAAC 22.5 332.4 102 13 +2001 6 17 12 11 SANDY 61.1 263.7 159 772 +1982 4 15 18 8 WILLIAM 10.1 104.4 16 494 +1954 2 23 12 4 PATTY 49.6 142.4 32 310 +1984 8 22 6 1 ERNESTO 27.5 184.5 128 339 +1979 10 10 18 7 CHRIS 19.3 289.6 49 120 +1986 11 18 12 10 KIRK 39.5 99.0 124 487 +1980 8 20 18 24 MICHAEL 58.5 153.0 55 438 +2002 3 3 6 18 SANDY 61.9 138.6 109 96 +1981 12 6 12 9 BERYL 10.1 120.5 145 134 +1955 5 12 18 5 NADINE 62.8 45.4 53 175 +1997 8 20 12 14 WILLIAM 44.1 204.4 122 197 +2000 12 17 6 1 PATTY 63.3 72.2 117 895 +1963 10 20 18 21 ALBERTO 31.4 160.7 83 853 +1955 6 14 18 18 SANDY 10.6 191.2 152 347 +1965 12 28 0 2 CHRIS 16.8 106.4 98 652 +1963 1 26 0 14 NADINE 25.9 285.9 60 226 +1950 11 11 6 7 ERNESTO 47.7 344.7 55 699 +1967 1 15 18 20 LESLIE 64.7 326.3 13 745 +1954 10 26 12 17 NADINE 55.5 92.2 80 188 +1993 10 26 18 2 BERYL 69.2 342.2 136 246 +1997 1 14 12 22 RAFAEL 37.0 44.6 38 382 +1976 3 17 12 6 DEBBY 47.8 329.3 87 667 +1950 2 9 0 23 NADINE 40.7 339.7 113 382 +1967 12 18 18 25 OSCAR 35.0 352.5 151 381 +2000 11 28 18 27 LESLIE 53.3 12.9 150 509 +1996 8 22 0 24 CHRIS 12.0 101.3 21 395 +2004 1 13 6 2 HELENE 18.7 137.3 161 899 +1951 10 24 12 13 OSCAR 33.2 188.8 83 445 +1952 6 10 0 10 FLORENCE 41.4 320.9 136 554 +1960 11 10 0 21 WILLIAM 52.4 318.4 76 882 +1980 10 18 0 10 VALERIE 66.7 123.4 111 214 +1967 8 22 0 28 JOYCE 29.3 125.9 37 656 +1991 6 21 12 16 OSCAR 23.9 197.1 10 816 +1950 11 28 12 26 LESLIE 26.6 201.1 68 240 +1968 11 15 12 3 WILLIAM 44.5 325.4 116 704 +1987 9 1 18 14 RAFAEL 50.2 241.9 79 880 +1986 10 21 12 16 NADINE 7.4 97.3 79 93 +1951 4 12 6 15 SANDY 25.4 81.4 14 768 +1951 3 23 6 22 ERNESTO 16.8 238.2 62 232 +1959 7 7 12 7 RAFAEL 68.2 131.9 118 733 +1976 5 20 12 26 GORDON 14.3 253.9 153 848 +1976 4 11 6 2 ALBERTO 53.0 126.2 127 254 +1997 7 17 12 3 RAFAEL 30.6 357.6 67 729 +1965 11 10 18 1 HELENE 59.2 265.9 75 850 +1958 11 27 6 3 RAFAEL 30.1 169.5 72 561 +2002 11 15 18 1 NADINE 41.0 312.5 20 444 +1986 5 14 6 11 RAFAEL 56.9 241.7 122 399 +1979 6 1 18 26 HELENE 27.6 301.6 73 97 +1992 6 19 6 24 ERNESTO 46.4 82.8 64 712 +1973 1 17 12 4 ALBERTO 14.5 50.4 160 295 +1984 3 18 6 6 PATTY 53.8 30.0 37 82 +1992 10 2 6 21 PATTY 29.6 356.8 16 229 +1971 7 5 0 28 PATTY 65.6 329.4 29 600 +1967 1 7 12 10 PATTY 23.0 249.4 147 700 +1965 8 15 18 25 MICHAEL 61.0 272.7 75 616 +1995 12 1 6 17 NADINE 64.1 172.2 44 603 +1955 8 17 12 18 JOYCE 41.6 18.5 50 465 +1968 2 13 18 19 RAFAEL 12.6 257.7 14 283 +1964 4 8 12 25 FLORENCE 25.8 344.9 111 225 +1987 11 20 0 23 SANDY 56.4 96.5 63 400 +1982 8 17 18 7 VALERIE 18.8 19.5 105 637 +1996 4 24 18 2 SANDY 20.9 354.8 40 505 +1968 10 3 12 23 OSCAR 35.1 135.5 13 27 +2003 6 18 6 8 DEBBY 42.7 199.8 104 510 +1993 11 8 0 11 KIRK 32.4 285.9 133 247 +1963 4 19 12 15 TONY 19.7 200.7 41 310 +1957 10 25 12 3 RAFAEL 59.1 317.0 48 366 +1981 2 9 0 1 RAFAEL 21.1 309.9 12 19 +1973 5 26 12 19 ERNESTO 52.2 121.2 25 843 +1991 4 4 12 28 HELENE 9.8 52.0 164 336 +1956 4 18 18 14 BERYL 46.2 168.9 79 803 +1983 12 19 0 28 WILLIAM 33.2 57.7 88 646 +1991 2 6 18 7 HELENE 8.7 327.7 159 704 +1985 11 10 12 27 BERYL 31.3 211.9 38 159 +2003 3 18 0 22 NADINE 58.4 80.3 70 56 +1960 1 10 12 14 DEBBY 67.8 37.4 107 5 +1997 8 24 0 4 HELENE 51.9 58.0 105 284 +1969 3 6 0 15 ISAAC 17.5 59.1 156 642 +1999 4 19 12 20 DEBBY 18.7 271.1 154 635 +1954 1 12 18 6 VALERIE 35.9 291.7 53 23 +2004 1 18 12 27 JOYCE 35.0 274.5 133 599 +1993 1 17 12 4 PATTY 35.3 223.5 103 706 +1969 2 22 6 27 OSCAR 51.5 137.0 103 24 +2003 8 26 12 27 WILLIAM 57.4 139.1 74 412 +1974 2 12 0 6 SANDY 44.2 255.7 121 449 +1993 11 9 18 17 WILLIAM 20.7 125.8 57 795 +2002 12 5 18 22 RAFAEL 60.6 125.5 123 482 +1970 12 4 0 5 WILLIAM 12.9 24.7 44 336 +1994 12 27 6 13 FLORENCE 36.5 334.4 147 291 +2001 6 8 12 22 ERNESTO 27.1 188.0 102 407 +1961 4 22 12 21 JOYCE 24.7 193.5 90 141 +1990 4 16 12 5 ERNESTO 50.3 250.1 124 811 +1976 6 14 6 15 NADINE 52.9 20.4 120 838 +1991 5 20 0 13 ALBERTO 26.6 240.3 150 436 +1986 2 7 12 15 FLORENCE 33.3 20.3 157 446 +1953 10 15 18 12 SANDY 23.5 160.0 161 837 +1987 4 22 12 28 RAFAEL 25.9 355.5 124 800 +1973 8 21 0 3 OSCAR 19.5 178.6 43 333 +1950 10 8 12 3 RAFAEL 48.9 278.9 81 647 +1974 1 4 18 14 GORDON 62.7 284.6 136 790 +1993 10 3 12 23 ERNESTO 56.3 132.3 70 144 +1971 3 9 6 12 SANDY 49.0 148.4 149 184 +2001 12 26 6 3 TONY 33.6 116.0 110 503 +2002 9 4 6 5 VALERIE 30.2 201.0 41 608 +1959 12 2 6 8 BERYL 16.8 240.9 158 658 +2003 3 9 18 25 MICHAEL 7.5 301.7 66 613 +1962 6 23 6 3 BERYL 41.4 210.3 51 640 +2000 5 17 6 20 ERNESTO 42.3 260.6 14 128 +1959 7 16 12 13 VALERIE 16.0 330.0 145 386 +1997 11 16 0 26 PATTY 9.8 18.3 27 865 +1957 7 19 18 27 ISAAC 16.1 55.2 157 1 +1975 11 18 18 25 OSCAR 30.4 61.4 36 354 +1969 5 17 6 5 CHRIS 7.9 44.9 58 488 +1995 8 5 6 3 GORDON 56.4 2.1 45 76 +1967 12 5 0 9 ERNESTO 52.7 314.9 139 301 +1991 1 17 0 22 ISAAC 38.4 278.9 126 221 +1992 10 7 18 11 JOYCE 18.0 238.1 99 175 +1971 12 12 6 15 ALBERTO 22.4 132.6 110 45 +1956 7 23 0 12 SANDY 35.2 340.1 116 368 +1985 10 2 12 26 BERYL 15.3 82.7 149 796 +1996 1 14 6 20 PATTY 33.3 169.8 157 209 +1974 4 8 0 8 JOYCE 28.8 146.3 132 767 +1996 10 1 18 18 MICHAEL 33.8 215.5 143 58 +1961 2 16 6 3 KIRK 17.9 124.9 33 527 +1973 11 2 6 17 ISAAC 62.2 69.9 134 373 +2000 1 20 18 22 GORDON 48.5 141.9 135 342 +1958 10 27 12 28 GORDON 36.2 307.3 21 886 +1977 12 12 0 16 DEBBY 41.7 108.9 99 61 +1952 12 15 6 17 CHRIS 34.1 84.0 70 268 +1998 6 7 18 21 ERNESTO 28.1 304.6 97 672 +1965 2 20 0 26 RAFAEL 57.2 247.0 147 225 +1962 1 20 6 23 BERYL 57.1 43.6 132 333 +1965 5 3 12 9 FLORENCE 12.6 306.3 63 529 +1962 12 6 18 15 ERNESTO 8.3 150.6 81 489 +1990 11 26 6 19 FLORENCE 7.8 120.5 67 620 +1960 6 2 18 4 ISAAC 32.8 58.5 31 780 +2004 5 16 12 9 NADINE 44.8 311.9 56 367 +1988 8 9 0 12 WILLIAM 30.7 342.4 84 43 +1986 7 2 18 12 VALERIE 15.1 180.0 55 834 +1966 5 6 12 21 ALBERTO 43.8 277.1 136 192 +1960 1 16 6 15 HELENE 29.6 350.1 33 258 +2002 3 10 6 5 CHRIS 45.9 112.5 44 318 +1968 7 15 0 21 KIRK 29.7 198.1 146 569 +1980 1 9 12 7 RAFAEL 48.1 353.8 68 557 +1997 11 16 6 4 HELENE 16.8 128.4 118 359 +1959 12 17 12 15 VALERIE 68.7 47.3 148 437 +1994 6 24 18 8 CHRIS 66.4 112.2 146 812 +1987 8 11 18 10 CHRIS 55.9 34.5 62 210 +1974 2 6 6 22 LESLIE 36.3 303.7 101 438 +1994 1 22 0 21 GORDON 67.6 10.5 84 489 +1967 11 7 0 1 FLORENCE 52.5 68.0 50 123 +1964 12 15 6 26 KIRK 39.7 337.1 140 874 +2004 7 8 12 2 JOYCE 32.1 141.7 146 729 +2001 4 13 0 28 OSCAR 67.7 351.7 128 652 +1974 6 6 0 14 OSCAR 51.1 18.8 129 801 +1958 9 23 6 15 WILLIAM 31.4 223.0 158 194 +1958 12 11 12 1 DEBBY 12.8 39.5 32 598 +1991 11 2 12 13 CHRIS 20.8 119.6 53 745 +1956 2 26 0 17 MICHAEL 54.3 154.5 45 756 +1977 12 9 12 11 DEBBY 24.7 122.3 37 618 +1967 10 24 18 28 JOYCE 24.5 96.7 87 246 +1990 4 10 12 13 BERYL 29.6 21.5 50 167 +1986 9 19 6 3 FLORENCE 36.7 9.2 60 828 +1983 7 5 12 17 RAFAEL 34.8 184.0 14 29 +1959 1 12 0 24 LESLIE 66.0 4.9 157 524 +1968 8 28 12 3 TONY 34.4 157.2 159 515 +1963 9 3 6 26 VALERIE 13.3 189.7 164 818 +1968 4 9 18 18 NADINE 47.9 289.2 115 493 +1959 12 17 18 23 ISAAC 36.3 263.9 163 74 +1984 4 20 12 10 WILLIAM 18.5 323.1 131 344 +1964 9 3 18 24 LESLIE 66.4 276.0 112 85 +1961 5 5 12 13 MICHAEL 54.6 46.1 131 558 +1955 8 21 12 28 HELENE 27.1 27.4 27 180 +1972 8 12 18 24 LESLIE 8.9 274.6 85 617 +1967 12 14 12 23 TONY 48.1 122.4 14 30 +1985 2 18 18 3 WILLIAM 60.0 357.2 116 182 +1979 2 12 18 15 VALERIE 55.0 316.1 25 611 +1961 8 13 18 25 HELENE 55.2 191.3 32 339 +1998 1 2 12 11 ISAAC 29.6 198.8 21 314 +1982 2 16 6 16 DEBBY 29.4 3.6 37 185 +1956 10 4 12 13 TONY 57.6 7.2 121 286 +1954 10 4 12 10 KIRK 36.8 353.0 160 269 +1965 1 22 18 18 HELENE 21.7 102.0 132 633 +1966 7 9 12 23 RAFAEL 33.7 195.2 156 768 +2000 3 11 12 11 GORDON 51.5 157.1 78 626 +1962 4 9 12 23 PATTY 7.5 229.0 49 513 +1956 5 18 6 25 RAFAEL 10.0 33.0 17 420 +1975 4 16 12 12 ISAAC 50.3 265.1 18 451 +1966 4 2 6 24 PATTY 16.2 27.4 123 322 +2002 12 12 12 23 FLORENCE 32.5 197.5 164 321 +1990 6 14 0 15 CHRIS 41.5 173.3 54 175 +1983 10 25 18 6 FLORENCE 16.8 302.0 120 541 +1962 10 25 0 4 ISAAC 32.4 202.9 108 121 +1965 4 10 18 25 TONY 60.2 234.7 30 502 +1955 4 16 0 4 ERNESTO 18.5 142.6 37 355 +1988 9 11 0 4 OSCAR 21.0 118.7 155 364 +1998 5 7 18 19 JOYCE 58.0 192.5 82 2 +1978 6 13 0 19 ERNESTO 20.5 230.6 108 267 +1993 7 23 12 2 VALERIE 40.8 137.0 19 791 +1962 4 12 12 1 LESLIE 49.2 130.8 157 562 +1972 8 3 0 17 DEBBY 62.3 76.7 32 157 +1950 1 10 18 21 MICHAEL 15.1 53.8 152 483 +1962 8 11 0 21 BERYL 24.0 293.2 74 821 +2002 10 9 18 1 HELENE 21.0 102.6 89 354 +2004 6 16 0 11 KIRK 58.1 179.2 133 422 +2001 7 24 6 19 NADINE 64.5 354.6 90 858 +1969 7 18 18 1 ISAAC 55.8 148.4 157 531 +2002 6 11 0 12 TONY 17.3 232.0 122 530 +1988 4 20 18 3 KIRK 26.4 356.3 51 526 +1977 4 25 12 5 BERYL 29.7 93.5 33 59 +1962 9 3 0 22 RAFAEL 20.8 168.2 155 204 +1993 9 28 6 15 BERYL 64.2 62.9 112 60 +1989 1 4 6 17 WILLIAM 8.2 162.8 83 879 +1979 1 27 18 27 WILLIAM 18.9 339.3 20 619 +1971 6 1 0 25 ALBERTO 9.7 319.4 116 539 +1964 12 9 18 2 TONY 9.8 102.9 100 272 +1979 7 17 18 9 HELENE 22.8 301.2 47 271 +1985 5 18 6 9 OSCAR 49.7 205.6 153 93 +1953 7 9 6 4 DEBBY 43.9 124.2 55 681 +1989 12 22 12 2 ALBERTO 18.5 251.4 73 37 +1976 5 27 18 22 MICHAEL 7.8 33.5 45 72 +1965 3 19 18 21 NADINE 62.2 225.9 60 835 +1966 1 3 0 28 OSCAR 8.4 158.1 142 500 +1990 8 9 18 25 FLORENCE 65.9 260.3 144 472 +1962 8 13 12 17 ALBERTO 39.2 282.1 13 577 +1996 1 10 18 5 SANDY 27.5 85.8 152 15 +1994 3 7 12 17 MICHAEL 23.6 180.5 138 44 +1974 5 20 18 12 DEBBY 40.5 237.2 147 371 +1971 4 7 6 20 VALERIE 67.4 317.4 67 708 +1986 11 2 0 18 LESLIE 57.4 156.4 82 447 +1959 3 8 6 4 ISAAC 59.4 227.1 79 872 +1986 7 2 0 26 HELENE 38.0 325.2 119 885 +1993 7 12 6 11 GORDON 41.6 132.0 139 322 +2001 4 28 18 7 TONY 35.6 10.6 11 285 +1951 8 8 6 5 DEBBY 20.6 282.3 158 288 +1994 7 18 12 2 GORDON 55.1 164.4 121 816 +1966 2 20 6 15 TONY 39.6 215.2 36 13 +1991 1 15 6 7 VALERIE 40.1 184.6 106 267 +1994 8 7 18 24 HELENE 34.3 82.7 134 546 +1996 2 7 18 8 ALBERTO 46.0 290.5 34 770 +1958 9 12 12 8 KIRK 24.1 173.7 16 397 +1995 9 19 0 16 VALERIE 28.8 214.7 112 353 +1982 7 28 6 10 WILLIAM 20.5 303.3 155 530 +1974 7 11 6 23 VALERIE 66.8 24.2 24 222 +1957 9 16 18 26 RAFAEL 27.1 188.3 83 792 +1950 11 26 6 1 RAFAEL 20.2 273.1 93 641 +1961 5 24 18 13 ALBERTO 32.2 238.2 75 217 +1987 2 16 18 14 KIRK 33.8 272.4 93 864 +1957 9 17 12 3 NADINE 35.9 212.1 43 190 +1985 12 13 18 20 CHRIS 52.2 47.6 76 134 +1956 8 3 18 9 LESLIE 28.8 261.9 153 818 +1950 1 26 0 8 JOYCE 45.2 86.4 14 205 +1958 7 11 6 28 KIRK 10.2 207.5 158 182 +1979 6 26 0 27 FLORENCE 52.6 160.6 30 193 +1981 1 16 0 16 ERNESTO 42.6 175.3 33 6 +1954 12 17 18 17 ALBERTO 57.5 65.7 121 377 +1956 8 11 12 7 ERNESTO 36.9 111.1 112 842 +1956 10 13 0 10 PATTY 19.2 329.3 69 255 +1973 7 21 0 25 GORDON 7.8 234.9 45 198 +1954 12 7 12 15 BERYL 67.9 265.0 122 253 +1990 6 16 18 5 ISAAC 57.3 239.3 12 44 +1987 5 13 6 1 ERNESTO 8.4 10.2 161 393 +1987 10 17 6 26 ERNESTO 27.5 266.8 34 385 +1985 1 23 12 5 HELENE 49.7 142.4 32 212 +1995 7 24 0 14 JOYCE 38.0 271.6 78 275 +2002 6 26 6 11 SANDY 65.3 3.9 75 347 +2004 6 17 6 28 KIRK 51.2 77.8 125 642 +1955 8 13 18 6 JOYCE 32.5 228.6 29 770 +1957 9 8 6 14 VALERIE 34.0 315.6 120 599 +1990 2 21 18 28 ERNESTO 51.2 339.0 112 363 +1990 8 13 0 11 DEBBY 21.5 47.1 76 420 +1966 2 11 0 6 MICHAEL 40.0 277.5 15 730 +1997 10 24 0 15 RAFAEL 19.1 259.1 112 857 +1991 11 27 12 18 VALERIE 26.7 95.5 119 302 +1950 3 15 18 23 HELENE 56.3 243.9 151 45 +1956 1 25 0 21 KIRK 54.6 42.9 58 547 +1997 10 2 0 11 DEBBY 34.4 252.7 161 532 +1997 7 21 12 8 OSCAR 46.8 266.2 18 250 +1968 11 15 12 14 BERYL 9.2 15.9 162 779 +1973 8 22 6 9 WILLIAM 56.8 357.2 100 736 +1988 5 2 6 17 HELENE 62.4 275.2 133 53 +1981 2 10 18 21 GORDON 67.9 275.6 112 217 +1973 8 17 18 10 KIRK 18.4 289.0 157 466 +1986 11 15 12 13 PATTY 47.3 306.6 50 743 +1977 8 28 18 8 VALERIE 37.6 252.0 17 600 +2004 10 2 18 27 DEBBY 34.9 323.3 91 253 +1993 7 16 18 27 KIRK 38.6 62.0 107 183 +1996 10 22 6 6 DEBBY 63.3 254.4 92 386 +1967 8 24 18 19 TONY 23.2 260.8 161 99 +2001 10 1 12 8 HELENE 29.3 127.2 146 107 +1973 5 3 6 8 KIRK 30.9 265.3 153 17 +1959 1 22 12 8 KIRK 12.8 245.8 104 540 +2002 7 14 18 14 DEBBY 33.8 324.5 140 56 +1997 11 6 18 22 SANDY 49.2 4.9 161 450 +1977 7 25 18 4 ISAAC 44.7 280.8 88 521 +1997 6 20 6 18 HELENE 26.1 188.8 49 170 +1969 6 10 18 11 TONY 60.4 233.0 123 375 +1961 11 24 18 8 VALERIE 67.0 88.9 61 674 +1960 12 24 12 3 OSCAR 58.1 303.6 45 519 +1969 9 8 18 27 KIRK 20.8 283.4 145 688 +1982 11 10 6 2 ERNESTO 10.6 8.3 81 13 +2004 6 9 18 11 KIRK 23.4 324.1 144 346 +1961 11 13 12 16 RAFAEL 9.6 292.8 160 65 +1961 9 1 6 11 TONY 66.4 156.3 62 332 +1986 4 2 12 15 CHRIS 41.9 67.0 155 563 +1958 4 20 18 12 HELENE 11.1 18.5 32 190 +2002 5 28 6 20 TONY 52.4 315.8 59 49 +1973 8 13 0 17 RAFAEL 40.8 325.7 97 100 +1996 12 22 12 9 JOYCE 50.1 140.9 49 795 +1970 2 1 18 21 OSCAR 20.5 293.0 121 31 +2003 12 16 0 18 DEBBY 62.3 334.7 67 756 +1950 11 24 12 27 SANDY 26.1 245.8 140 315 +1950 11 21 0 13 OSCAR 35.9 114.9 72 197 +1997 12 10 6 5 WILLIAM 53.6 302.1 75 242 +1998 6 13 12 28 JOYCE 11.9 92.8 57 224 +1992 10 16 12 25 RAFAEL 25.5 163.6 72 370 +1984 8 17 0 25 TONY 69.9 305.6 146 161 +1990 4 7 6 6 SANDY 13.4 175.7 160 5 +1974 3 23 6 20 CHRIS 69.8 284.2 59 460 +1981 2 28 6 17 WILLIAM 59.8 282.7 152 669 +1990 2 22 0 27 VALERIE 40.1 46.1 128 690 +1966 4 2 6 4 PATTY 12.6 117.1 12 258 +1963 10 12 0 14 VALERIE 39.9 301.5 145 542 +1955 12 5 12 21 PATTY 60.7 176.0 97 323 +1988 8 6 12 24 TONY 41.2 322.5 27 232 +1955 11 22 12 26 PATTY 28.8 40.0 12 186 +1980 12 12 6 5 NADINE 17.7 347.0 51 83 +1996 5 27 6 25 SANDY 34.5 36.2 35 602 +2004 9 12 12 26 BERYL 12.5 123.8 20 145 +1958 8 15 0 9 GORDON 61.5 53.6 68 709 +1975 6 21 6 12 OSCAR 13.7 187.1 127 218 +1968 7 13 6 15 GORDON 59.7 70.2 107 890 +1956 3 6 18 9 PATTY 69.2 140.3 94 565 +1991 6 10 12 20 SANDY 13.0 351.1 128 791 +1988 7 15 6 7 NADINE 14.9 239.1 147 820 +1977 4 2 6 8 NADINE 67.9 50.6 16 183 +1966 7 3 0 11 ERNESTO 38.2 326.6 67 750 +1990 7 14 12 20 TONY 12.9 79.7 129 238 +1971 6 8 12 21 RAFAEL 28.0 246.6 21 638 +1963 7 9 6 17 PATTY 63.7 168.8 142 3 +1974 3 6 18 10 MICHAEL 63.7 236.1 72 673 +1996 3 9 12 6 ALBERTO 15.6 251.7 88 657 +1954 11 9 0 8 PATTY 12.8 303.1 134 644 +1963 6 5 0 27 LESLIE 36.6 198.0 161 745 +1962 1 1 12 22 CHRIS 8.3 292.9 161 77 +1992 9 1 18 25 CHRIS 69.0 296.6 108 798 +1975 3 12 6 1 DEBBY 61.6 116.0 44 891 +1961 3 24 0 2 NADINE 43.9 148.0 75 428 +1994 1 10 6 8 CHRIS 15.0 140.5 134 492 +1987 9 6 18 11 ERNESTO 66.0 161.2 147 855 +1979 10 21 6 28 PATTY 57.0 285.2 113 460 +1977 2 2 6 13 CHRIS 27.2 152.9 158 61 +1995 11 26 0 5 FLORENCE 29.0 137.5 111 762 +1988 6 3 6 1 JOYCE 48.9 137.7 144 738 +1983 5 20 0 20 SANDY 68.0 132.3 45 614 +1979 6 21 0 1 BERYL 11.2 0.4 98 636 +1998 1 10 12 20 GORDON 15.3 336.6 117 23 +1978 7 10 12 1 PATTY 34.5 242.4 21 873 +1967 4 11 0 17 ERNESTO 14.6 179.6 121 232 +1965 5 22 0 1 MICHAEL 28.3 160.1 68 317 +1993 5 23 6 14 ISAAC 25.2 24.2 103 843 +1965 10 5 12 7 FLORENCE 56.7 5.2 94 9 +1962 4 23 18 21 DEBBY 31.8 223.4 152 266 +1958 6 28 18 3 KIRK 57.1 247.6 42 667 +1999 12 22 0 4 NADINE 41.1 3.8 150 820 +1996 10 6 12 4 RAFAEL 69.9 174.3 74 720 +1950 11 12 0 22 ISAAC 22.3 177.9 148 707 +1983 12 26 0 8 TONY 15.3 331.7 100 210 +1997 11 7 0 10 VALERIE 45.3 311.5 153 412 +1953 4 6 18 4 VALERIE 64.4 185.1 16 736 +1980 6 21 0 8 NADINE 49.6 242.1 85 897 +2003 8 26 6 15 FLORENCE 55.1 2.4 127 791 +1973 4 17 6 3 SANDY 19.3 94.7 21 410 +1992 2 25 18 22 GORDON 25.1 185.6 136 536 +1960 10 15 12 8 SANDY 69.5 182.5 19 40 +1975 4 24 6 13 FLORENCE 19.5 273.9 100 768 +1993 1 7 18 14 OSCAR 26.0 174.0 17 138 +1952 1 3 12 19 MICHAEL 53.7 279.9 90 827 +1968 3 24 12 23 HELENE 28.6 91.8 73 800 +1971 8 9 12 13 WILLIAM 62.1 113.9 83 510 +1964 11 12 12 24 ALBERTO 35.0 13.4 36 831 +2003 9 28 18 6 CHRIS 69.1 231.5 27 454 +1996 3 12 12 2 RAFAEL 40.5 296.4 79 804 +1955 1 12 18 18 ISAAC 40.8 229.0 10 301 +1986 4 18 6 28 FLORENCE 22.9 332.1 130 791 +1957 10 21 6 6 OSCAR 45.8 298.0 119 327 +1987 11 1 6 16 VALERIE 19.4 42.7 99 427 +1984 5 23 12 4 CHRIS 23.3 310.7 123 582 +1991 12 23 12 16 PATTY 67.2 54.0 114 799 +1992 10 23 18 2 WILLIAM 31.8 326.8 36 375 +1960 10 24 0 15 BERYL 36.0 131.1 115 659 +1981 4 4 6 22 FLORENCE 64.3 164.8 76 696 +1976 3 26 12 11 VALERIE 62.1 210.5 116 68 +1997 1 16 0 1 ERNESTO 49.5 340.0 82 784 +1968 7 6 12 18 RAFAEL 33.1 4.4 122 781 +1985 11 24 18 27 KIRK 7.7 3.7 103 537 +1984 2 3 6 25 JOYCE 37.2 15.5 82 636 +1979 2 12 12 26 CHRIS 31.9 26.9 31 376 +1987 9 16 0 24 OSCAR 19.1 255.1 102 775 +1991 2 24 0 1 ISAAC 64.8 316.3 57 315 +1951 5 18 18 7 MICHAEL 22.8 33.9 85 422 +1967 3 24 18 27 OSCAR 44.9 185.4 137 291 +1967 8 12 6 8 LESLIE 43.2 55.8 145 883 +1981 7 22 18 25 NADINE 11.0 279.1 10 703 +1989 10 6 18 19 JOYCE 30.9 83.9 93 530 +1994 3 6 18 17 OSCAR 30.3 152.6 41 894 +1961 3 12 18 16 CHRIS 44.8 336.6 70 406 +1996 1 12 12 2 RAFAEL 67.3 56.3 125 672 +1988 6 10 0 25 BERYL 43.9 214.4 137 327 +1962 4 10 0 28 LESLIE 42.1 153.6 79 188 +1965 6 1 18 24 FLORENCE 39.6 87.2 37 864 +1968 9 3 18 6 BERYL 52.7 185.9 149 718 +1955 9 2 12 23 ALBERTO 66.4 351.5 77 707 +1993 10 1 0 3 TONY 16.7 346.9 64 131 +2002 5 18 12 17 ALBERTO 38.6 106.2 105 672 +2001 12 19 18 19 FLORENCE 61.0 214.6 31 802 +1969 9 21 18 24 WILLIAM 36.2 266.6 152 790 +1964 10 2 0 16 MICHAEL 67.4 205.9 155 15 +1995 2 7 12 25 SANDY 68.8 306.8 152 161 +1973 4 28 6 15 RAFAEL 60.5 211.2 113 792 +1964 7 9 18 14 TONY 16.8 274.2 127 153 +1997 6 27 6 19 ALBERTO 54.0 216.8 106 344 +1984 6 22 12 26 BERYL 36.4 40.5 129 57 +1990 11 21 12 12 HELENE 65.9 8.8 29 329 +1952 4 23 12 17 PATTY 68.6 256.8 13 224 +1964 3 4 12 21 GORDON 15.3 318.5 79 148 +1954 8 8 12 25 MICHAEL 62.3 106.8 33 435 +1978 11 21 6 7 ERNESTO 54.1 176.0 32 842 +1966 6 5 0 9 ALBERTO 11.6 225.0 13 820 +1950 7 22 6 13 KIRK 69.1 181.0 160 681 +1981 3 19 12 8 PATTY 65.2 72.6 141 314 +1984 8 8 6 23 OSCAR 20.2 58.8 111 601 +1954 6 5 12 19 ISAAC 36.9 58.0 121 91 +2004 7 3 0 4 ERNESTO 10.6 326.7 155 802 +1994 9 12 0 20 OSCAR 28.7 262.7 55 892 +1981 4 27 18 2 RAFAEL 69.3 277.7 66 233 +1981 10 3 18 16 SANDY 62.4 34.3 35 113 +1968 8 24 18 10 FLORENCE 46.9 316.4 66 347 +1967 6 27 12 27 BERYL 36.7 349.9 163 686 +1981 6 17 6 7 JOYCE 38.5 160.1 71 495 +1950 10 20 18 19 NADINE 66.3 66.6 35 250 +1995 2 24 6 20 VALERIE 61.2 239.6 88 519 +1971 8 7 6 13 GORDON 66.8 266.0 19 235 +1953 11 8 18 16 JOYCE 27.0 94.1 162 82 +1960 8 26 6 20 CHRIS 43.8 240.6 140 621 +2002 1 23 18 18 PATTY 53.5 174.7 11 464 +1994 9 23 6 26 FLORENCE 16.9 16.2 59 687 +1958 9 26 12 27 KIRK 24.3 137.3 92 310 +1960 12 27 0 22 OSCAR 18.4 188.5 111 731 +1952 6 2 0 27 VALERIE 48.5 265.6 23 883 +1978 7 5 18 24 WILLIAM 55.8 108.6 53 402 +1974 8 27 0 14 KIRK 13.1 12.2 52 100 +1977 1 9 18 10 ERNESTO 41.7 182.3 41 892 +1952 5 24 0 22 NADINE 28.2 175.5 125 18 +1971 7 3 18 12 MICHAEL 19.5 249.9 140 372 +1993 8 16 12 7 LESLIE 65.3 170.3 105 383 +1995 10 23 0 3 FLORENCE 65.0 129.5 163 391 +1975 3 13 18 7 BERYL 21.0 88.3 34 34 +1973 10 25 6 23 MICHAEL 49.8 345.4 140 205 +2001 2 10 18 27 VALERIE 19.5 68.6 117 544 +1970 5 1 18 19 ERNESTO 68.6 236.6 17 450 +1965 4 9 18 27 VALERIE 43.5 242.4 131 546 +1955 3 17 0 14 LESLIE 64.8 321.1 130 615 +1951 2 5 0 16 LESLIE 16.7 213.7 129 353 +1979 12 11 12 18 KIRK 15.1 258.0 13 614 +1997 2 24 12 15 VALERIE 13.5 282.2 26 763 +1990 7 15 0 3 TONY 54.5 126.2 49 882 +2001 4 14 0 13 TONY 42.0 240.8 39 189 +1995 6 9 6 28 LESLIE 15.3 90.8 141 36 +1979 8 5 6 8 GORDON 7.0 147.2 156 263 +1951 10 1 0 8 BERYL 60.0 52.9 74 781 +1962 4 27 18 3 JOYCE 29.3 127.1 85 638 +1997 8 9 12 8 SANDY 8.4 88.9 18 131 +1953 4 21 0 2 GORDON 60.6 51.9 144 207 +2002 5 19 18 28 OSCAR 34.1 241.1 141 509 +2002 2 3 18 20 LESLIE 46.9 52.3 58 53 +1995 3 16 12 27 KIRK 68.6 52.8 22 671 +2004 7 19 0 12 GORDON 14.1 264.3 117 731 +1970 2 13 0 1 VALERIE 15.3 211.8 14 386 +2000 10 25 0 18 RAFAEL 61.7 352.5 114 776 +1972 5 12 0 25 NADINE 44.5 175.1 97 603 +1966 2 18 18 2 GORDON 12.5 72.0 18 558 +1954 1 27 0 23 DEBBY 22.1 144.7 127 882 +1983 2 7 0 1 LESLIE 64.9 263.1 128 0 +1986 10 14 12 16 SANDY 14.7 0.4 79 68 +1960 1 11 12 8 DEBBY 20.3 75.8 103 269 +2003 1 14 18 1 JOYCE 14.1 148.4 111 85 +1976 2 13 6 9 FLORENCE 22.6 46.0 127 11 +2002 8 12 12 27 PATTY 29.5 102.1 101 480 +1972 10 15 0 3 VALERIE 53.4 175.4 50 87 +1970 4 12 0 12 LESLIE 47.7 164.1 163 524 +1971 10 27 12 27 OSCAR 69.0 272.7 43 744 +1978 2 25 12 23 KIRK 62.5 81.9 86 16 +1961 10 8 6 1 HELENE 45.1 58.2 150 676 +1962 9 21 12 26 FLORENCE 42.3 333.7 148 867 +1993 12 10 6 20 RAFAEL 54.8 198.0 42 197 +1972 9 21 0 21 ERNESTO 66.2 163.5 24 378 +1958 9 27 6 19 ISAAC 7.7 43.5 97 330 +1994 7 14 18 24 RAFAEL 27.6 295.3 121 853 +1990 2 18 12 2 GORDON 40.1 203.9 42 585 +1978 7 21 6 12 GORDON 14.9 199.3 54 622 +1994 9 12 12 2 HELENE 14.5 157.7 43 370 +1976 2 8 12 21 NADINE 19.8 255.0 58 466 +1989 5 8 0 6 MICHAEL 48.8 84.6 103 13 +2000 1 16 12 26 RAFAEL 8.3 222.7 77 614 +1992 12 25 18 20 TONY 53.5 334.8 145 133 +1952 1 21 6 6 KIRK 37.4 123.6 134 722 +1976 7 20 0 14 ISAAC 8.9 151.9 33 668 +1982 4 6 18 10 BERYL 58.9 159.8 32 516 +1983 2 16 18 19 OSCAR 18.6 249.4 49 396 +1980 11 27 0 10 KIRK 45.9 19.9 94 348 +1983 5 11 0 14 CHRIS 28.2 10.0 57 353 +1998 2 22 0 27 TONY 64.7 296.0 82 897 +1965 6 2 12 20 OSCAR 69.1 305.7 159 247 +1963 2 19 6 10 MICHAEL 57.7 40.2 114 708 +1962 3 22 12 6 OSCAR 61.7 326.1 20 619 +1970 3 13 0 4 WILLIAM 62.8 223.5 39 882 +1997 3 21 6 7 MICHAEL 61.3 289.4 77 830 +1988 12 24 12 13 BERYL 18.1 284.9 32 487 +1965 7 11 18 24 BERYL 62.6 202.8 53 627 +1981 11 28 12 2 JOYCE 34.3 41.5 42 702 +1988 8 2 6 13 VALERIE 63.6 198.7 29 5 +1963 1 25 6 23 FLORENCE 21.8 2.6 121 819 +1995 3 16 0 26 ISAAC 48.2 274.0 161 592 +1961 2 23 6 25 LESLIE 59.0 82.9 32 431 +1985 4 11 0 28 OSCAR 16.6 208.7 144 283 +1960 1 27 18 16 ISAAC 47.6 46.3 126 61 +1998 2 11 12 5 TONY 57.9 307.5 159 360 +1957 4 27 12 7 JOYCE 49.0 318.4 78 247 +1977 4 26 18 26 CHRIS 57.1 142.7 33 66 +1994 8 9 6 16 JOYCE 52.8 6.4 137 788 +1998 3 3 6 27 PATTY 59.6 336.0 37 143 +1961 2 3 6 9 FLORENCE 63.1 112.5 50 449 +1973 9 9 6 6 ERNESTO 55.1 6.7 46 6 +1995 1 5 0 4 GORDON 39.6 240.6 119 675 +1962 7 17 18 2 GORDON 30.2 79.7 31 292 +1999 5 7 18 13 RAFAEL 53.8 275.0 28 697 +1972 3 4 6 1 HELENE 66.3 114.1 12 129 +1974 6 27 6 28 SANDY 20.4 128.7 102 440 +1987 11 7 18 21 LESLIE 10.1 42.3 77 716 +1980 8 14 6 24 WILLIAM 24.0 305.7 162 814 +1973 10 5 0 5 ISAAC 11.1 179.9 86 83 +1993 1 19 0 4 HELENE 68.5 49.7 97 180 +1983 9 27 12 25 VALERIE 47.9 309.5 108 31 +1979 7 18 0 14 GORDON 8.2 142.6 33 633 +1954 3 19 0 1 GORDON 32.9 201.6 45 152 +1968 2 14 0 14 FLORENCE 60.6 18.4 37 657 +1995 7 16 0 9 ALBERTO 35.2 81.2 45 867 +1983 6 19 18 22 FLORENCE 12.6 302.3 21 657 +1997 8 12 18 5 ERNESTO 43.2 356.7 55 689 +1969 2 22 0 2 JOYCE 68.4 121.8 65 868 +2004 7 23 12 3 FLORENCE 18.7 86.7 77 340 +1982 1 28 6 1 FLORENCE 59.8 315.5 121 352 +2000 1 9 0 7 GORDON 32.7 66.9 152 117 +1956 2 7 0 9 ERNESTO 13.3 266.6 162 390 +1977 6 8 6 1 PATTY 62.4 29.3 17 265 +1990 6 10 0 13 DEBBY 16.6 315.7 41 767 +1999 2 9 18 14 WILLIAM 53.0 166.0 115 776 +1975 10 19 0 20 KIRK 58.8 27.2 119 701 +1964 6 14 0 13 KIRK 54.0 273.7 15 860 +1984 8 13 18 9 PATTY 8.4 30.1 85 93 +1996 7 10 12 5 VALERIE 66.5 87.4 145 420 +1958 3 22 6 15 CHRIS 69.1 159.8 132 157 +2003 6 11 0 8 CHRIS 10.6 58.6 103 361 +2000 4 27 0 28 ISAAC 26.9 164.7 160 481 +1979 5 4 6 10 ERNESTO 62.5 80.3 138 781 +1967 9 11 0 24 TONY 30.5 21.6 164 724 +2001 8 19 12 26 LESLIE 64.2 200.3 123 526 +1967 2 22 6 11 BERYL 64.6 349.2 122 148 +1966 4 9 0 3 BERYL 36.8 145.1 153 144 +1994 1 18 18 20 OSCAR 30.6 57.4 117 55 +1991 2 14 6 27 DEBBY 41.0 312.5 153 609 +1996 11 28 0 1 VALERIE 67.6 244.0 129 16 +1974 9 27 12 24 NADINE 8.6 176.8 37 97 +1989 4 11 6 2 WILLIAM 49.0 266.2 13 582 +1955 12 7 18 6 MICHAEL 49.3 119.0 102 701 +1972 10 5 0 25 KIRK 22.1 354.4 83 893 +1993 3 17 12 8 BERYL 58.5 198.1 129 771 +1971 4 22 6 1 DEBBY 21.6 207.1 131 479 +1979 1 7 0 9 JOYCE 63.8 328.9 49 68 +1956 4 6 18 10 DEBBY 35.3 95.9 146 534 +1950 5 9 6 27 MICHAEL 43.4 172.8 123 464 +2002 10 2 12 12 DEBBY 14.9 49.0 150 216 +1976 7 18 18 16 PATTY 44.9 283.7 26 129 +1992 11 9 6 6 VALERIE 13.1 334.6 157 631 +1982 4 24 0 27 LESLIE 68.0 189.6 11 760 +1976 1 10 18 6 CHRIS 14.7 349.9 78 295 +1983 2 11 0 12 OSCAR 52.3 72.8 10 392 +2000 7 9 6 13 MICHAEL 69.5 9.7 64 605 +2001 10 20 18 11 KIRK 51.0 198.9 93 123 +1963 2 6 6 4 HELENE 46.9 319.9 55 65 +1990 7 15 6 2 ERNESTO 63.4 113.3 72 1 +1963 12 8 0 16 JOYCE 19.2 224.5 99 581 +1981 6 17 6 8 TONY 47.4 246.8 59 469 +1991 12 8 12 18 TONY 34.9 186.2 90 396 +2004 3 3 6 12 ISAAC 27.0 39.2 80 102 +1992 4 15 0 21 JOYCE 31.6 321.3 81 280 +1998 9 27 12 7 KIRK 34.3 32.3 40 369 +1992 9 5 6 24 JOYCE 47.8 234.4 151 12 +1950 5 25 6 25 GORDON 43.5 104.9 49 872 +1992 7 11 12 23 ISAAC 41.1 327.8 161 836 +1964 11 12 18 21 VALERIE 46.1 224.6 37 434 +1997 6 21 18 10 CHRIS 21.2 274.8 76 269 +1977 7 3 18 22 FLORENCE 15.4 154.0 118 322 +1957 5 25 12 5 SANDY 55.5 305.0 136 707 +1996 10 17 0 16 DEBBY 12.3 244.0 127 368 +1963 2 6 12 16 HELENE 27.0 126.9 13 718 +1957 4 13 18 2 TONY 65.9 137.7 156 347 +1964 6 26 6 25 RAFAEL 45.8 167.5 84 431 +1977 5 4 6 18 ISAAC 52.2 37.5 92 474 +1999 5 2 12 7 HELENE 13.6 41.8 26 462 +1970 12 15 0 18 ISAAC 44.7 27.4 89 347 +1995 3 3 0 27 WILLIAM 7.4 342.5 148 886 +1992 9 28 6 23 JOYCE 61.5 246.8 32 665 +1991 2 7 6 20 RAFAEL 47.5 348.1 160 396 +1993 11 26 12 2 DEBBY 21.8 94.1 66 30 +1979 7 2 12 13 DEBBY 53.0 263.1 99 432 +1998 2 20 18 8 JOYCE 26.0 81.6 66 138 +1994 8 1 12 8 DEBBY 57.0 141.4 21 346 +1972 11 11 12 25 MICHAEL 58.7 234.0 124 159 +1982 2 17 12 7 LESLIE 40.2 304.4 47 274 +1988 1 28 6 3 BERYL 58.5 90.7 17 112 +1997 10 7 0 16 LESLIE 37.7 104.5 153 878 +1989 5 20 6 18 TONY 68.0 211.0 13 624 +1987 7 8 0 21 PATTY 46.1 80.1 108 710 +1952 5 28 12 25 KIRK 67.3 227.4 63 628 +2001 7 23 18 17 DEBBY 17.9 197.6 106 339 +1953 11 25 18 10 ISAAC 40.6 125.2 138 193 +1955 6 25 6 2 ALBERTO 43.8 118.5 78 510 +1955 6 20 0 13 JOYCE 21.3 7.0 21 379 +1983 6 7 12 2 OSCAR 70.0 168.0 68 101 +1951 12 13 6 16 VALERIE 43.3 113.9 30 580 +1981 1 6 6 1 PATTY 39.6 236.7 78 459 +1974 9 11 6 25 ISAAC 32.6 304.7 130 533 +1973 6 2 0 9 BERYL 7.2 338.8 84 463 +1979 1 9 0 3 DEBBY 43.1 98.7 64 132 +1980 12 1 0 15 MICHAEL 63.0 78.3 106 258 +1953 5 14 18 11 FLORENCE 25.7 275.8 116 399 +1951 5 11 0 27 WILLIAM 64.3 282.2 97 252 +1968 2 1 18 5 GORDON 30.2 156.8 148 582 +1953 12 8 0 27 ISAAC 47.5 356.2 127 791 +1980 3 16 12 28 RAFAEL 45.9 56.9 39 313 +2001 2 27 18 25 ERNESTO 15.0 161.1 107 897 +1973 8 16 6 2 GORDON 41.1 228.0 28 495 +1962 2 28 12 25 VALERIE 64.1 49.3 23 445 +1957 8 25 0 28 BERYL 30.0 208.3 109 449 +1958 6 3 18 1 HELENE 21.1 134.7 54 810 +1976 1 14 12 27 PATTY 13.8 11.4 43 793 +1999 11 26 0 20 HELENE 40.7 297.2 104 223 +1976 12 6 12 2 PATTY 49.4 243.7 41 211 +1953 12 20 12 3 JOYCE 62.8 115.8 116 52 +1996 12 20 6 19 PATTY 57.2 175.0 69 93 +1983 11 28 0 1 JOYCE 26.6 106.5 76 316 +1991 10 8 12 10 BERYL 48.9 257.1 147 727 +1967 5 19 12 26 HELENE 26.6 339.7 106 553 +1999 8 14 18 3 CHRIS 41.3 11.2 92 719 +1979 6 3 6 8 OSCAR 64.6 301.8 22 593 +1990 4 10 18 19 ERNESTO 20.0 114.1 80 782 +1969 12 19 18 7 SANDY 10.3 97.5 19 120 +1973 10 22 18 17 DEBBY 43.1 333.9 39 411 +1982 6 23 12 3 LESLIE 48.4 120.5 164 86 +1962 2 14 0 14 TONY 54.3 262.1 126 526 +1972 1 25 0 14 MICHAEL 61.5 314.3 86 392 +1962 11 9 18 2 KIRK 61.3 60.9 117 326 +1981 1 8 12 7 GORDON 19.4 177.8 12 208 +1964 1 16 18 14 LESLIE 66.8 91.7 65 336 +1951 3 26 0 18 TONY 54.3 24.5 32 640 +1976 4 14 18 16 ISAAC 51.6 232.8 69 407 +1975 11 17 6 15 MICHAEL 23.8 28.1 154 455 +1984 1 5 12 22 GORDON 23.0 168.1 110 449 +1951 4 14 18 26 MICHAEL 28.9 90.6 135 609 +1955 8 28 6 7 KIRK 13.1 97.9 101 686 +1992 8 8 6 4 PATTY 61.9 158.4 24 751 +1953 12 23 6 11 PATTY 41.3 284.3 57 468 +1974 3 28 18 23 ALBERTO 35.3 171.4 61 826 +1961 9 28 6 24 HELENE 16.6 226.8 159 800 +1979 11 18 6 16 BERYL 10.7 19.2 163 515 +2004 8 21 0 12 SANDY 46.5 194.1 153 53 +1995 6 20 12 13 FLORENCE 11.1 48.3 64 512 +1955 6 19 18 14 OSCAR 16.5 138.6 114 346 +1988 1 22 12 3 ALBERTO 67.4 356.4 112 346 +1972 8 14 6 24 BERYL 10.4 173.9 57 359 +1995 4 2 6 3 WILLIAM 53.5 320.0 72 305 +1962 5 25 0 20 HELENE 7.2 76.0 54 359 +1986 12 18 12 15 MICHAEL 35.4 83.0 68 183 +1975 3 7 0 24 NADINE 9.4 203.8 157 174 +1991 5 19 18 17 DEBBY 48.4 15.9 31 285 +1999 5 16 18 27 KIRK 44.0 173.0 143 47 +1978 6 25 18 16 JOYCE 60.9 176.1 118 215 +1958 6 1 18 14 WILLIAM 32.6 39.1 26 9 +1993 10 5 12 3 MICHAEL 42.3 119.5 107 332 +1982 9 12 18 13 LESLIE 10.8 2.6 112 55 +1964 6 27 0 2 BERYL 11.9 150.5 31 652 +1993 1 28 6 7 WILLIAM 55.5 7.9 143 625 +1997 9 15 0 27 RAFAEL 16.0 190.1 99 146 +1994 9 22 18 22 DEBBY 36.7 179.3 134 18 +1981 2 22 6 27 FLORENCE 32.4 91.1 78 713 +1959 4 25 0 25 CHRIS 40.3 103.8 61 824 +1993 2 2 18 17 GORDON 46.3 9.1 127 347 +1965 8 4 0 17 ISAAC 49.6 80.5 103 898 +1988 8 9 18 24 CHRIS 38.5 146.1 14 182 +1992 12 11 12 18 ALBERTO 67.9 194.5 56 391 +1986 12 8 18 17 TONY 40.2 224.5 44 11 +1971 11 19 6 11 SANDY 26.2 149.8 103 568 +1967 1 3 12 22 BERYL 40.9 197.4 73 263 +1968 5 4 6 11 PATTY 43.3 188.2 74 715 +1963 2 15 18 11 KIRK 11.8 218.5 130 258 +1996 3 1 12 16 DEBBY 45.4 156.0 57 52 +1989 4 6 0 7 TONY 68.1 274.0 164 98 +1964 3 17 18 5 BERYL 20.5 319.5 161 458 +1985 5 19 12 26 TONY 67.2 339.3 164 10 +1973 10 13 0 16 DEBBY 58.3 244.5 145 381 +1989 11 1 18 24 CHRIS 15.3 234.2 78 48 +1989 2 14 0 2 HELENE 41.5 155.6 99 700 +1959 6 7 6 25 SANDY 32.9 297.9 147 33 +1984 7 25 0 27 SANDY 25.7 181.8 164 825 +1958 5 7 12 24 DEBBY 63.0 175.7 95 230 +1956 5 24 12 4 GORDON 43.2 343.5 47 607 +1971 5 7 6 23 PATTY 13.6 235.6 36 696 +1977 4 13 18 17 ALBERTO 42.3 285.5 44 200 +2001 11 18 6 26 SANDY 23.0 106.8 142 556 +1985 12 28 0 5 DEBBY 27.2 211.1 33 872 +1976 3 6 18 23 PATTY 14.1 334.1 47 455 +1970 4 24 0 6 ISAAC 23.9 133.4 156 20 +1975 1 3 12 25 PATTY 29.0 285.2 107 863 +1962 5 9 6 6 MICHAEL 56.5 118.4 46 91 +1961 8 13 18 7 RAFAEL 30.6 285.3 80 645 +1961 11 12 6 6 FLORENCE 53.4 9.5 164 526 +2001 12 14 12 28 RAFAEL 67.1 265.3 42 25 +1984 11 11 18 17 JOYCE 47.9 273.7 37 749 +1965 3 3 6 16 KIRK 46.2 70.7 82 827 +1995 8 28 18 1 DEBBY 66.7 326.0 160 188 +1976 11 2 18 19 GORDON 45.9 91.2 164 873 +1950 12 21 18 13 ALBERTO 27.3 19.8 12 745 +1952 1 1 0 4 NADINE 46.7 323.3 75 881 +1975 12 25 12 26 LESLIE 35.0 49.3 56 679 +1963 3 21 12 24 KIRK 20.3 180.1 138 875 +1997 4 11 6 18 NADINE 43.0 6.3 97 385 +1953 11 11 12 15 JOYCE 12.1 237.1 81 43 +1972 11 19 12 11 GORDON 25.0 74.6 102 841 +1976 12 4 6 18 SANDY 51.2 249.4 21 847 +1982 8 7 6 2 NADINE 45.3 46.9 154 584 +1996 11 5 0 27 HELENE 50.0 173.1 80 801 +1960 7 14 0 28 WILLIAM 35.7 242.6 132 15 +1980 4 11 0 14 ISAAC 19.7 128.1 108 778 +1955 11 14 6 20 WILLIAM 33.4 330.0 65 707 +1961 10 17 0 27 WILLIAM 65.9 74.0 20 523 +1961 7 1 6 28 KIRK 52.8 319.7 103 518 +1997 4 9 12 11 ALBERTO 13.6 83.0 109 134 +1997 2 27 6 28 WILLIAM 63.8 325.1 61 160 +2001 9 18 6 2 GORDON 29.8 299.0 22 728 +1954 8 6 12 26 GORDON 20.7 79.2 139 122 +1994 12 10 18 8 BERYL 30.1 234.8 135 699 +1991 10 19 6 14 RAFAEL 51.2 326.4 34 13 +1952 11 23 0 9 JOYCE 45.2 327.7 104 331 +1953 3 9 18 16 HELENE 66.8 247.6 48 705 +1972 7 26 6 14 NADINE 42.0 307.4 140 261 +1986 1 9 0 12 TONY 35.7 74.8 14 799 +1952 8 10 6 9 FLORENCE 13.7 227.3 106 736 +1984 2 7 18 11 CHRIS 21.4 256.9 39 568 +2003 8 2 12 23 LESLIE 11.9 4.9 29 432 +2003 4 7 0 15 GORDON 62.9 68.3 163 20 +1952 8 28 0 21 ISAAC 35.8 106.4 25 292 +1983 7 25 18 26 SANDY 51.8 344.9 66 786 +1997 7 11 6 2 ALBERTO 53.4 125.8 33 193 +1951 10 28 12 7 PATTY 34.4 117.1 127 528 +1992 12 19 6 9 ERNESTO 38.4 135.7 138 568 +1986 2 26 0 3 ERNESTO 63.5 61.1 131 561 +1991 8 3 0 11 ISAAC 18.5 350.5 44 513 +1967 12 21 18 2 RAFAEL 30.6 327.9 115 196 +1983 11 23 18 12 RAFAEL 8.9 66.4 40 96 +1968 7 23 0 7 BERYL 45.1 179.0 163 590 +1994 5 15 18 10 WILLIAM 60.4 84.9 131 821 +1983 9 11 12 16 TONY 31.7 338.7 77 232 +1985 6 11 0 11 VALERIE 67.6 112.2 135 401 +1957 11 23 12 20 TONY 19.8 35.4 136 154 +2001 2 6 0 27 CHRIS 27.9 149.5 43 252 +1957 4 17 18 20 HELENE 40.7 339.1 129 72 +1954 10 1 0 28 SANDY 40.3 224.0 14 470 +1971 11 4 6 7 TONY 21.3 9.6 93 726 +1959 5 27 6 16 ALBERTO 21.0 257.0 35 495 +1969 9 17 6 12 JOYCE 64.3 188.0 113 202 +1961 11 8 6 25 VALERIE 58.2 168.2 85 351 +2000 5 25 12 27 BERYL 48.7 280.2 148 413 +1974 2 2 0 12 SANDY 22.4 332.4 119 820 +1989 4 18 12 26 ALBERTO 18.3 259.5 133 237 +1980 3 18 12 25 NADINE 61.5 100.9 96 207 +1987 1 18 18 27 GORDON 61.3 276.9 78 270 +1960 5 26 12 11 PATTY 54.2 284.1 31 277 +1976 4 10 0 9 CHRIS 62.2 60.1 92 509 +1986 6 14 18 18 TONY 37.3 81.0 130 218 +1961 4 25 0 10 SANDY 28.0 313.7 17 587 +1985 3 15 0 20 MICHAEL 47.4 130.9 103 378 +1962 11 4 12 1 CHRIS 36.2 246.5 138 227 +1962 3 13 0 6 LESLIE 57.2 84.6 32 800 +1996 12 7 6 23 MICHAEL 28.5 333.2 134 641 +1954 8 22 18 21 SANDY 68.1 69.9 96 100 +2000 5 16 6 14 NADINE 35.4 19.2 134 891 +1972 12 8 18 11 ALBERTO 43.7 212.8 99 694 +1974 9 23 12 27 FLORENCE 22.4 115.3 126 304 +1986 7 8 0 27 BERYL 44.2 212.5 159 820 +1981 1 28 18 7 JOYCE 59.2 233.2 39 868 +1970 3 20 12 21 HELENE 13.7 7.5 38 397 +1967 1 10 18 12 VALERIE 42.8 218.6 18 860 +1974 10 10 12 22 OSCAR 38.2 17.8 92 887 +1957 6 28 6 27 RAFAEL 66.8 295.0 130 211 +1990 10 4 18 5 LESLIE 58.2 75.4 73 790 +1994 2 20 18 11 PATTY 19.2 240.8 37 589 +1992 4 21 12 20 KIRK 32.1 87.2 123 180 +1973 3 14 6 15 ALBERTO 49.8 355.6 129 383 +1989 2 13 18 16 MICHAEL 37.9 137.6 148 564 +1969 3 25 6 16 KIRK 15.9 91.6 110 863 +1981 6 2 18 17 RAFAEL 46.4 26.5 150 292 +1978 8 11 6 28 RAFAEL 36.6 168.1 142 631 +1998 9 16 6 8 VALERIE 52.2 225.9 61 525 +1962 5 26 12 16 VALERIE 56.8 10.6 125 136 +1962 7 10 18 13 OSCAR 19.0 229.4 55 60 +2001 7 14 12 9 BERYL 13.8 302.7 64 13 +1989 7 26 12 19 OSCAR 50.0 44.9 44 752 +1994 3 18 6 4 VALERIE 57.3 77.7 78 482 +2001 8 25 0 5 ERNESTO 49.8 344.6 112 652 +1997 4 13 6 12 SANDY 46.3 308.1 163 841 +1986 7 3 18 18 KIRK 24.2 351.6 20 53 +2002 5 24 18 16 CHRIS 67.2 4.7 49 689 +1974 7 10 6 13 MICHAEL 13.2 208.6 47 678 +1990 7 2 0 8 LESLIE 19.9 268.7 129 739 +1996 7 16 12 10 DEBBY 43.7 175.9 116 602 +1952 2 13 18 12 KIRK 36.2 53.8 111 378 +1960 5 23 18 26 WILLIAM 46.0 313.3 43 40 +1999 8 6 12 21 RAFAEL 55.9 353.3 59 672 +2003 1 28 0 20 TONY 46.6 242.1 122 843 +1962 8 1 0 9 MICHAEL 51.0 135.3 158 232 +1966 5 12 0 22 HELENE 43.8 357.0 111 390 +2001 6 16 0 7 HELENE 42.8 237.6 129 651 +1965 10 14 18 12 JOYCE 26.0 129.4 130 194 +1962 3 18 0 3 LESLIE 56.4 101.9 109 155 +1956 8 16 6 4 HELENE 26.1 292.5 106 35 +1983 11 2 0 2 SANDY 65.9 240.5 98 424 +1980 6 12 6 4 VALERIE 28.1 162.3 49 637 +1966 12 25 12 9 LESLIE 25.5 330.0 82 825 +1996 10 17 6 14 DEBBY 21.5 216.4 135 776 +1976 3 10 6 18 FLORENCE 40.6 97.4 93 347 +1988 1 15 6 9 JOYCE 13.5 327.6 88 868 +1976 2 5 12 14 KIRK 35.2 164.5 51 429 +1967 10 26 18 12 FLORENCE 65.1 218.5 34 640 +1965 2 12 6 25 PATTY 15.1 146.0 57 874 +1988 4 28 0 12 OSCAR 22.6 182.2 126 422 +1983 9 3 18 18 MICHAEL 62.7 157.0 30 533 +1968 8 16 18 2 GORDON 63.7 308.0 108 822 +1978 7 22 0 10 FLORENCE 25.3 215.5 136 877 +1956 5 22 18 20 TONY 40.7 27.5 22 434 +1950 4 16 18 5 HELENE 66.7 267.8 142 748 +1966 2 22 0 3 FLORENCE 65.2 19.9 160 248 +1997 4 20 12 8 ERNESTO 63.8 334.4 26 188 +1973 8 15 0 14 ERNESTO 13.4 6.5 109 332 +1969 5 12 18 19 SANDY 20.1 5.1 101 612 +1957 4 20 0 28 ALBERTO 59.1 112.8 81 441 +1973 10 4 12 23 ERNESTO 33.6 7.4 156 392 +1965 1 24 6 28 HELENE 33.4 178.7 72 280 +1972 10 1 6 25 HELENE 34.3 354.1 114 216 +1953 3 22 0 5 WILLIAM 60.3 104.0 154 434 +1981 3 2 6 27 ALBERTO 20.1 351.0 58 599 +2000 7 17 6 8 WILLIAM 35.7 313.5 88 81 +1992 6 18 18 26 TONY 16.0 72.9 54 450 +1997 10 6 18 28 ERNESTO 33.7 185.9 46 26 +1981 1 25 18 16 MICHAEL 61.8 299.9 148 188 +1953 10 27 6 25 ISAAC 49.1 264.4 101 289 +1988 11 16 12 9 VALERIE 67.4 147.8 67 846 +1954 10 8 6 4 GORDON 54.4 143.0 158 273 +2001 9 19 18 26 RAFAEL 12.5 128.8 17 824 +1954 11 6 6 23 DEBBY 40.6 95.9 54 842 +1996 3 22 12 22 ALBERTO 19.0 328.1 68 679 +1987 10 11 18 6 CHRIS 49.7 156.3 153 120 +1960 6 18 12 13 LESLIE 69.7 138.0 126 834 +1956 5 13 6 7 OSCAR 39.7 323.4 68 88 +1954 5 5 6 22 JOYCE 15.3 15.5 82 396 +2001 7 3 12 5 LESLIE 27.3 168.5 66 678 +1988 6 16 6 13 LESLIE 35.7 329.6 52 158 +1982 11 20 0 9 VALERIE 53.1 138.5 115 328 +1959 5 4 12 14 VALERIE 61.5 322.7 103 594 +1951 4 19 6 22 SANDY 51.2 222.4 96 269 +1997 7 23 0 5 SANDY 39.8 302.6 102 715 +1983 5 27 12 13 BERYL 36.9 12.8 53 840 +1990 9 19 6 24 MICHAEL 9.6 106.6 15 10 +1992 12 6 6 7 FLORENCE 47.7 260.2 52 102 +1994 2 3 0 12 MICHAEL 67.6 121.6 56 178 +1958 9 10 0 10 NADINE 41.0 217.3 150 674 +1973 6 21 18 17 WILLIAM 13.4 262.5 158 481 +1977 4 27 12 18 PATTY 18.3 200.8 25 198 +1951 12 3 12 8 OSCAR 50.8 101.7 123 777 +1959 7 4 18 10 PATTY 62.9 149.8 52 366 +1951 11 15 18 21 OSCAR 55.3 344.9 146 542 +1977 2 20 6 22 PATTY 25.7 311.0 74 555 +1991 8 20 6 3 NADINE 9.9 189.8 134 224 +1954 3 24 0 27 FLORENCE 38.1 315.3 22 518 +1963 12 18 12 10 KIRK 55.6 213.2 45 350 +1974 8 20 0 11 ERNESTO 68.0 245.3 19 361 +1974 10 25 0 11 DEBBY 8.7 109.9 16 604 +1964 7 3 0 15 FLORENCE 68.2 110.0 105 187 +1993 5 16 6 20 LESLIE 55.3 88.6 104 310 +1981 11 18 6 4 ERNESTO 53.9 114.4 107 678 +1964 2 2 0 12 ALBERTO 46.8 3.3 146 636 +1968 1 4 6 4 DEBBY 11.6 327.3 143 180 +2003 6 5 0 26 PATTY 45.2 97.5 26 276 +1955 12 22 12 7 BERYL 34.4 209.2 100 238 +1987 8 1 12 21 ISAAC 55.9 134.6 17 153 +1953 11 18 18 11 TONY 36.4 289.3 115 11 +1955 9 3 18 15 SANDY 14.6 167.2 155 870 +1992 5 3 0 20 GORDON 63.1 210.8 48 647 +1955 10 15 12 10 HELENE 32.8 328.5 24 610 +1961 2 14 12 4 RAFAEL 24.3 121.4 11 626 +1970 11 13 6 18 RAFAEL 22.8 353.9 31 472 +1973 6 26 12 21 PATTY 28.8 193.8 58 746 +1954 5 6 18 24 JOYCE 44.3 147.6 134 193 +1990 5 12 18 20 MICHAEL 21.7 111.8 111 190 +1978 1 8 6 7 RAFAEL 39.1 346.6 87 411 +1985 7 11 12 21 ISAAC 7.6 339.7 78 666 +1963 4 13 0 17 TONY 18.5 42.5 52 438 +1957 8 21 6 1 LESLIE 22.1 158.4 21 472 +1990 9 18 6 15 FLORENCE 63.0 317.1 163 503 +1967 4 19 0 21 GORDON 61.1 153.5 98 742 +2000 7 2 0 14 NADINE 10.1 112.1 129 20 +1997 8 14 12 19 TONY 32.7 343.8 84 490 +1953 5 28 18 16 RAFAEL 19.0 212.1 128 25 +1993 2 9 12 20 VALERIE 42.9 0.7 163 165 +1958 10 20 0 18 KIRK 44.2 37.5 129 193 +1951 3 18 0 21 DEBBY 56.0 307.3 40 874 +2003 10 17 18 2 WILLIAM 39.1 72.1 51 719 +1970 2 2 12 12 PATTY 18.5 87.1 101 346 +1969 5 19 0 2 JOYCE 34.3 282.7 113 135 +1989 7 11 12 7 PATTY 44.1 11.2 145 714 +1957 12 10 18 4 DEBBY 21.0 311.7 157 357 +1980 5 12 12 21 FLORENCE 43.3 59.0 93 566 +1951 8 21 6 2 DEBBY 15.6 102.1 84 336 +1952 8 14 0 7 WILLIAM 39.3 237.3 111 559 +1969 8 16 12 24 ERNESTO 18.8 302.8 147 761 +2004 11 17 12 12 NADINE 35.9 57.5 55 768 +1997 10 4 0 10 RAFAEL 67.0 37.5 123 894 +1968 2 20 18 15 SANDY 49.3 254.5 46 516 +1961 8 5 6 11 DEBBY 17.4 45.7 49 350 +1998 9 11 0 23 JOYCE 29.6 79.7 90 567 +1962 3 7 6 9 NADINE 60.1 263.3 118 186 +1975 8 27 12 24 MICHAEL 35.5 348.4 146 69 +1967 9 16 18 27 ISAAC 35.1 271.8 26 99 +2003 2 20 0 19 GORDON 67.0 247.8 159 151 +1981 6 8 6 1 OSCAR 11.0 326.9 23 895 +1954 8 19 0 24 DEBBY 48.5 233.9 123 433 +1973 7 1 12 19 OSCAR 16.6 218.5 19 238 +1957 12 1 12 1 DEBBY 57.7 186.3 143 308 +1978 11 5 0 17 ERNESTO 53.1 334.6 18 596 +1970 8 21 0 13 CHRIS 32.8 35.0 109 298 +1989 6 9 6 25 PATTY 59.4 160.9 123 105 +1999 11 17 18 24 HELENE 65.9 332.3 89 574 +1960 5 5 18 17 VALERIE 51.9 149.7 15 281 +1970 9 19 0 14 VALERIE 45.0 283.8 160 880 +1957 3 6 12 23 BERYL 49.7 141.3 76 631 +1990 10 21 18 19 ERNESTO 35.7 353.9 121 552 +1970 1 8 0 3 PATTY 64.9 238.9 119 886 +1955 11 3 6 9 ERNESTO 53.6 46.6 126 65 +1991 3 4 18 11 FLORENCE 7.6 143.3 82 501 +1965 11 21 6 6 ALBERTO 66.2 52.1 120 712 +1956 9 3 6 6 DEBBY 50.8 60.2 101 228 +1950 4 2 18 11 BERYL 43.0 339.8 39 634 +1992 8 26 18 5 CHRIS 60.2 212.3 102 601 +1958 11 11 6 20 MICHAEL 8.2 328.6 74 376 +1990 4 9 18 21 WILLIAM 58.3 10.0 46 884 +1986 7 12 0 6 BERYL 21.9 277.3 37 845 +1994 11 13 0 22 TONY 18.8 226.7 39 646 +1973 9 10 6 20 KIRK 34.2 298.1 99 135 +1999 1 27 12 5 PATTY 18.3 243.3 63 270 +1957 9 6 6 6 LESLIE 57.9 44.7 152 791 +1951 3 27 6 17 CHRIS 13.8 186.7 30 58 +1963 8 18 18 4 ERNESTO 38.6 181.7 88 395 +1962 11 3 6 15 DEBBY 36.6 207.3 21 817 +1979 4 27 18 3 JOYCE 38.8 168.9 79 147 +1993 9 10 6 15 FLORENCE 18.6 22.2 145 240 +1952 7 27 12 7 ALBERTO 12.2 313.0 85 871 +1976 8 28 18 7 HELENE 51.8 205.3 125 310 +1998 1 19 18 12 CHRIS 39.9 134.7 152 88 +2000 2 8 18 27 ALBERTO 60.3 54.7 81 743 +2000 7 22 0 3 RAFAEL 38.1 240.5 162 97 +2003 10 10 6 11 GORDON 50.4 154.4 16 866 +1963 3 11 12 8 HELENE 65.6 236.1 19 498 +2001 7 1 12 27 ERNESTO 30.2 313.9 61 341 +1955 9 11 18 18 HELENE 8.3 318.8 26 292 +1970 6 1 6 5 NADINE 54.9 202.7 92 32 +1962 10 22 6 22 CHRIS 42.6 149.9 87 374 +1951 5 1 0 28 HELENE 37.8 42.3 164 258 +1990 3 11 12 19 TONY 68.0 267.0 20 274 +2004 12 7 6 21 RAFAEL 66.6 315.3 18 201 +1961 5 3 18 5 DEBBY 48.4 280.6 93 236 +1975 5 25 12 4 OSCAR 50.9 336.0 82 637 +1987 8 10 12 16 WILLIAM 62.4 235.5 35 865 +1997 5 14 0 5 ISAAC 33.0 141.5 22 759 +1953 12 11 18 3 OSCAR 62.9 56.2 161 253 +1977 12 26 6 9 FLORENCE 40.0 357.6 115 403 +1965 7 21 18 8 JOYCE 59.1 341.6 123 751 +1997 7 15 12 2 VALERIE 48.4 214.4 20 322 +1981 6 1 0 3 RAFAEL 32.3 237.8 16 300 +1957 1 15 18 10 VALERIE 11.5 44.5 125 19 +1969 8 13 6 17 ALBERTO 63.7 254.3 35 466 +1967 9 1 0 17 WILLIAM 65.0 108.9 78 119 +1969 5 9 6 18 SANDY 12.4 15.3 78 663 +1977 3 1 6 12 SANDY 58.7 296.5 72 222 +1991 3 9 0 26 DEBBY 14.3 0.6 142 43 +1992 8 25 6 5 OSCAR 7.9 18.0 62 136 +1963 2 23 6 22 NADINE 13.1 195.5 54 280 +1956 11 10 12 2 HELENE 58.2 290.5 22 818 +1952 7 12 18 5 BERYL 43.3 127.1 34 388 +1968 8 9 6 23 SANDY 63.4 56.5 21 475 +1998 12 20 0 14 CHRIS 48.0 299.4 66 267 +1951 6 7 12 24 KIRK 19.5 53.5 158 519 +1975 10 7 0 21 CHRIS 62.5 302.5 163 627 +1971 2 23 0 20 BERYL 52.9 50.1 64 201 +1991 9 12 12 24 LESLIE 65.3 148.7 44 305 +1959 3 20 0 10 CHRIS 42.5 41.3 127 534 +1994 2 13 6 4 SANDY 21.6 233.5 74 752 +1950 4 27 6 20 PATTY 60.8 224.9 140 263 +1972 3 26 18 21 KIRK 35.5 105.0 80 412 +1953 8 9 0 26 CHRIS 65.4 348.2 128 185 +2003 7 11 6 17 FLORENCE 51.8 254.5 69 527 +1990 5 11 12 6 NADINE 67.9 298.6 148 587 +2000 11 10 0 14 MICHAEL 37.9 126.2 67 14 +1975 2 3 12 24 ERNESTO 22.9 181.3 63 435 +1986 7 16 6 3 ALBERTO 68.4 248.5 14 227 +1970 2 28 0 1 KIRK 7.5 36.2 110 597 +1989 9 23 0 21 VALERIE 57.7 320.6 80 498 +1965 9 3 6 22 TONY 36.6 129.1 46 660 +1979 6 1 18 19 ERNESTO 38.0 306.9 86 492 +1991 9 25 6 15 FLORENCE 26.3 53.8 27 510 +1971 1 2 0 9 LESLIE 11.3 79.0 74 92 +1964 6 26 0 13 ISAAC 66.8 304.5 36 569 +1994 3 23 12 18 DEBBY 13.9 139.8 14 782 +1981 4 8 6 1 BERYL 19.9 309.9 80 129 +1982 7 27 0 20 RAFAEL 23.3 107.1 113 104 +1971 1 11 12 7 JOYCE 57.6 41.3 75 399 +1988 9 13 6 24 BERYL 45.1 3.4 78 94 +1983 2 11 18 18 FLORENCE 22.9 194.0 77 752 +1950 10 14 6 2 JOYCE 39.8 282.1 68 727 +2001 5 24 6 25 JOYCE 13.2 111.9 112 278 +1965 4 25 0 10 MICHAEL 63.5 270.3 153 731 +1979 10 1 12 7 KIRK 34.7 252.6 35 290 +1993 5 27 12 7 DEBBY 61.9 168.4 58 843 +2000 7 11 0 13 MICHAEL 7.7 66.0 161 314 +1997 10 16 18 6 ALBERTO 44.8 357.4 150 467 +1978 9 21 0 22 DEBBY 25.6 227.6 33 15 +1994 7 22 18 2 CHRIS 68.5 162.4 152 660 +1955 7 11 12 27 HELENE 21.0 80.1 150 584 +1978 12 8 12 5 TONY 31.0 211.4 70 323 +1994 6 6 18 23 SANDY 18.7 275.5 130 627 +1968 12 16 12 14 VALERIE 22.2 304.9 73 374 +1995 9 11 12 1 LESLIE 42.1 36.5 119 684 +1964 5 16 18 2 CHRIS 35.7 265.3 90 298 +1992 2 23 0 27 MICHAEL 21.9 163.0 37 597 +1973 11 19 18 1 TONY 35.6 214.0 59 416 +2000 8 6 6 22 DEBBY 61.8 259.1 60 343 +1988 10 11 18 11 MICHAEL 47.3 33.1 125 326 +1984 3 5 18 10 ERNESTO 45.4 70.6 161 214 +1979 4 6 6 13 BERYL 13.0 315.6 67 131 +1962 2 4 0 16 KIRK 38.3 208.6 64 714 +1981 7 1 18 3 HELENE 65.4 220.7 20 419 +1998 12 22 0 3 LESLIE 10.9 248.4 47 160 +1993 4 1 6 2 OSCAR 50.2 185.6 79 479 +1973 2 6 6 4 TONY 43.1 81.0 89 62 +1997 6 16 6 1 ISAAC 45.3 213.7 107 532 +2001 5 5 6 8 GORDON 31.7 236.3 136 216 +1978 4 27 0 1 LESLIE 54.2 239.5 115 869 +1999 12 11 0 5 SANDY 41.8 1.0 124 219 +1962 2 18 0 15 DEBBY 66.4 243.2 39 640 +1994 3 6 0 28 MICHAEL 68.1 304.0 146 370 +1964 11 7 18 3 JOYCE 44.7 220.2 160 38 +1979 8 26 0 3 MICHAEL 32.7 122.5 94 866 +1972 11 28 12 10 VALERIE 37.0 118.9 75 517 +1993 11 28 6 15 MICHAEL 51.4 166.5 25 192 +1952 11 21 18 16 TONY 40.2 325.2 88 132 +1982 2 14 18 16 NADINE 45.3 156.5 35 660 +1994 1 28 0 5 MICHAEL 15.4 302.5 148 471 +1998 10 8 0 22 CHRIS 54.8 86.1 125 453 +1953 5 3 6 13 CHRIS 32.6 68.4 150 164 +1984 7 6 12 7 FLORENCE 9.1 24.1 75 799 +2001 10 10 18 12 MICHAEL 67.8 64.5 36 698 +2000 9 21 12 22 LESLIE 52.2 166.8 98 226 +1958 11 19 0 4 JOYCE 26.7 66.4 118 676 +1994 12 19 0 11 MICHAEL 7.5 163.9 23 870 +1994 1 2 0 13 ERNESTO 18.5 351.9 16 872 +1978 2 1 0 7 BERYL 51.4 338.4 58 896 +1967 3 9 6 21 SANDY 57.1 273.4 60 611 +1968 11 22 0 16 NADINE 7.1 237.1 15 203 +1990 5 20 12 24 CHRIS 27.7 5.5 142 309 +1994 12 2 0 25 VALERIE 22.2 269.0 91 631 +1963 5 15 12 22 TONY 50.9 287.5 25 86 +2004 10 5 0 5 FLORENCE 44.7 185.0 19 575 +1961 7 15 12 8 PATTY 37.8 17.4 35 72 +1993 4 25 6 12 OSCAR 35.7 52.7 162 476 +1982 12 10 18 6 RAFAEL 51.6 37.2 31 201 +1997 9 26 12 13 CHRIS 58.4 59.9 20 391 +1973 5 2 6 5 LESLIE 16.6 259.7 28 265 +1952 6 18 0 2 ALBERTO 44.9 157.2 101 573 +1950 5 25 12 20 CHRIS 68.1 217.8 97 869 +1986 12 2 12 3 VALERIE 35.2 233.9 112 758 +1967 7 24 12 1 ISAAC 13.0 106.9 68 733 +1954 3 18 12 17 ALBERTO 38.5 33.7 50 549 +2002 5 23 6 1 JOYCE 55.0 335.8 37 210 +2004 8 22 12 24 FLORENCE 66.9 130.4 154 500 +1967 10 4 18 26 CHRIS 69.9 132.9 75 241 +2004 2 15 0 21 ERNESTO 33.4 263.5 131 496 +1971 6 25 6 2 TONY 32.0 93.6 12 476 +1950 6 2 12 17 SANDY 68.2 194.2 149 372 +1979 9 1 0 20 ISAAC 56.7 33.7 118 861 +1985 8 15 6 13 ERNESTO 15.6 183.0 45 104 +1994 7 7 12 25 LESLIE 55.5 59.3 97 441 +1989 5 26 6 22 NADINE 44.0 58.6 106 326 +1950 7 8 18 10 CHRIS 62.1 327.8 133 457 +1959 12 2 0 15 PATTY 36.6 303.8 64 122 +1987 7 23 0 4 SANDY 37.7 234.0 145 778 +1996 6 2 12 8 MICHAEL 64.2 280.9 25 554 +1996 9 27 18 20 HELENE 7.4 249.2 131 888 +1984 8 3 0 26 BERYL 11.8 92.4 138 361 +1983 4 13 6 4 MICHAEL 45.2 55.5 156 551 +1976 2 5 6 2 WILLIAM 69.1 321.8 53 30 +1980 11 17 12 26 SANDY 16.0 202.1 112 542 +1978 9 28 12 7 MICHAEL 60.6 224.5 10 689 +1979 2 10 6 26 DEBBY 51.8 182.6 20 408 +1984 1 7 12 9 PATTY 58.8 46.8 135 800 +1991 8 24 12 26 ALBERTO 34.0 162.4 154 174 +1968 8 5 0 16 MICHAEL 65.5 29.6 98 681 +1999 5 14 18 12 LESLIE 37.4 256.9 72 36 +1967 1 18 12 10 RAFAEL 49.8 249.8 144 622 +1997 11 22 12 18 DEBBY 16.6 252.3 25 201 +1971 6 28 12 13 HELENE 43.7 257.5 131 840 +1994 2 3 18 3 WILLIAM 56.0 229.1 104 484 +1976 1 27 12 18 RAFAEL 35.7 343.2 15 714 +1955 1 17 6 17 NADINE 63.5 23.7 124 781 +1964 2 1 0 17 BERYL 36.9 7.8 130 418 +1963 8 16 0 27 TONY 30.4 44.9 16 222 +1957 7 15 18 27 GORDON 19.2 275.6 139 823 +1975 8 21 18 23 ISAAC 66.5 284.0 21 806 +1999 5 7 0 16 TONY 68.5 266.7 63 892 +1967 12 8 0 25 SANDY 46.1 36.7 96 206 +1980 3 28 0 15 HELENE 11.4 37.9 118 596 +1950 7 8 18 19 ISAAC 46.1 354.0 83 398 +1969 5 20 0 26 ALBERTO 34.9 256.5 79 276 +1996 4 22 0 21 ISAAC 24.2 300.1 74 10 +1983 8 15 0 22 GORDON 60.9 8.0 162 228 +1960 2 11 0 4 HELENE 67.0 105.7 148 859 +1982 1 28 18 25 ALBERTO 53.8 132.2 155 167 +1956 2 2 12 8 ERNESTO 47.8 218.9 14 31 +1998 3 27 18 24 SANDY 8.4 111.0 104 466 +1998 8 17 18 28 JOYCE 40.2 181.5 67 492 +1992 4 27 12 17 RAFAEL 62.0 39.3 22 665 +1954 4 8 0 6 PATTY 57.4 222.7 127 7 +1989 8 22 18 8 VALERIE 45.2 109.5 134 305 +1962 3 15 18 7 MICHAEL 23.2 319.0 57 895 +1968 5 22 0 20 RAFAEL 23.4 35.6 140 760 +1985 6 3 18 8 CHRIS 32.2 230.6 58 86 +1990 12 16 0 20 PATTY 43.6 119.7 73 568 +1963 8 10 18 13 HELENE 51.5 235.6 112 766 +1982 6 16 0 5 SANDY 50.4 132.1 57 409 +1974 2 21 0 26 SANDY 46.5 298.7 63 552 +1968 4 23 18 22 KIRK 44.0 60.9 117 809 +1976 8 20 6 10 FLORENCE 35.8 103.6 129 725 +1984 1 17 18 11 VALERIE 20.5 42.9 98 107 +1984 4 1 6 5 ALBERTO 46.2 139.6 71 194 +1995 5 20 18 12 LESLIE 15.3 150.2 129 26 +1998 2 25 12 20 PATTY 66.6 329.8 143 533 +2000 11 22 6 17 PATTY 56.1 19.0 45 410 +1975 3 17 12 12 LESLIE 44.1 14.3 84 895 +1990 4 19 12 23 RAFAEL 33.7 341.7 10 873 +2001 3 22 18 22 PATTY 17.7 42.3 109 529 +1993 6 9 0 10 LESLIE 43.7 340.0 71 103 +1972 10 14 12 15 ALBERTO 46.0 36.5 32 463 +1980 5 11 12 11 HELENE 67.3 264.7 77 545 +1991 7 17 12 17 PATTY 8.3 172.5 12 280 +1994 5 16 0 14 WILLIAM 67.2 82.9 84 500 +1950 8 23 12 8 MICHAEL 38.8 242.8 45 872 +1966 12 23 18 14 DEBBY 52.1 224.0 98 151 +1994 4 5 18 15 BERYL 39.1 330.8 45 335 +1984 11 24 18 23 ERNESTO 47.6 138.1 114 109 +1988 3 21 6 2 VALERIE 49.9 140.0 31 521 +1972 1 26 6 14 PATTY 24.9 82.5 53 128 +1961 12 13 0 9 NADINE 16.8 274.0 54 81 +1963 7 28 0 8 VALERIE 29.1 260.9 148 482 +1953 11 11 18 23 OSCAR 56.5 355.6 154 441 +1964 1 2 18 11 DEBBY 66.8 179.3 19 304 +1974 9 13 6 19 ISAAC 57.0 315.7 90 523 +1987 4 10 0 16 FLORENCE 55.0 193.5 74 775 +1994 10 19 18 14 WILLIAM 32.6 129.2 125 247 +1967 2 23 18 24 PATTY 23.9 140.9 138 91 +2004 6 10 6 21 PATTY 62.5 312.9 24 35 +1971 3 22 0 19 ALBERTO 68.4 101.2 39 860 +1962 7 7 0 15 LESLIE 62.3 154.6 163 791 +1961 10 3 0 24 ALBERTO 49.5 134.3 133 368 +1960 12 18 6 18 VALERIE 63.2 143.9 30 214 +1952 9 14 0 17 ALBERTO 28.9 26.7 133 838 +1955 4 2 0 25 SANDY 21.9 303.7 99 820 +1975 8 18 12 4 LESLIE 60.2 289.9 97 618 +2004 1 1 6 2 ALBERTO 13.3 106.7 131 582 +1995 4 16 0 25 LESLIE 27.1 154.7 86 764 +1992 2 6 0 19 PATTY 58.0 44.9 25 363 +2004 1 10 6 17 JOYCE 39.9 217.5 122 135 +1964 10 7 0 16 KIRK 63.5 4.6 66 350 +1979 2 8 6 5 ALBERTO 65.3 275.7 132 673 +1987 12 19 0 22 FLORENCE 31.1 295.1 100 688 +1982 6 3 12 27 RAFAEL 68.4 135.6 29 577 +1987 11 17 6 20 DEBBY 27.1 180.9 125 176 +1962 10 6 12 21 VALERIE 35.5 233.2 95 321 +1953 6 11 12 22 TONY 32.3 258.1 106 857 +1952 7 23 6 9 JOYCE 45.3 291.9 108 337 +1982 10 8 18 14 FLORENCE 52.9 141.7 154 611 +1960 8 18 0 27 KIRK 19.6 11.9 117 351 +1977 9 21 12 20 OSCAR 9.0 26.5 29 645 +1988 4 3 0 19 BERYL 17.9 139.2 104 219 +1968 8 2 0 4 BERYL 61.1 209.0 63 571 +1998 2 4 12 25 ERNESTO 21.2 121.1 119 735 +1985 8 1 0 5 SANDY 45.8 228.9 20 567 +2003 1 24 6 16 NADINE 15.7 91.4 116 375 +1989 3 12 18 8 JOYCE 28.7 230.4 38 202 +1987 8 24 0 21 SANDY 8.7 291.0 31 843 +2001 9 13 18 17 SANDY 12.0 229.6 128 9 +1951 9 1 18 12 BERYL 64.6 339.6 63 95 +1989 4 26 12 11 MICHAEL 45.3 170.2 132 40 +1997 10 7 18 8 ISAAC 44.6 348.1 20 459 +1974 2 20 18 12 GORDON 12.1 13.6 28 583 +1995 6 19 18 9 WILLIAM 36.1 229.8 160 520 +1966 7 21 6 3 VALERIE 54.5 287.8 21 416 +1956 5 2 18 20 ERNESTO 48.9 128.5 161 42 +1969 11 1 12 20 NADINE 69.7 333.8 91 382 +1974 7 17 12 10 JOYCE 16.3 54.0 33 649 +1961 3 25 12 12 ALBERTO 23.6 49.7 155 828 +1987 1 22 6 3 JOYCE 29.2 138.6 137 714 +1981 9 18 18 1 ALBERTO 57.6 326.1 161 577 +1989 7 10 6 27 ERNESTO 65.5 313.7 69 265 +1952 8 18 12 28 TONY 39.2 61.5 108 155 +1977 10 24 0 23 MICHAEL 45.3 219.5 74 873 +1956 7 10 12 14 KIRK 16.0 65.9 99 148 +1960 6 25 18 3 KIRK 69.3 83.7 137 748 +1984 4 28 18 7 DEBBY 16.2 280.4 73 847 +1966 9 15 0 10 HELENE 44.8 30.9 99 255 +1959 12 12 18 7 TONY 31.8 61.7 115 314 +1982 11 16 18 13 DEBBY 57.9 293.1 141 588 +1967 10 26 6 23 DEBBY 56.9 327.1 38 195 +1951 10 18 0 4 KIRK 46.0 23.8 156 2 +2003 8 15 0 2 PATTY 33.8 131.6 148 725 +1969 5 26 12 13 ERNESTO 52.7 185.3 62 44 +1975 7 22 18 13 ISAAC 53.5 253.6 90 850 +1968 3 1 6 10 CHRIS 38.1 4.9 116 372 +1958 6 13 0 1 ISAAC 51.4 197.2 90 27 +1961 4 9 12 27 OSCAR 15.7 122.3 52 1 +1954 10 8 6 6 VALERIE 32.0 141.8 151 287 +2004 11 26 12 1 MICHAEL 12.7 158.2 53 708 +1986 8 6 0 5 JOYCE 22.6 106.5 155 49 +1951 12 18 18 2 ISAAC 29.7 352.6 42 329 +1980 4 15 6 14 VALERIE 51.8 10.1 99 513 +2002 4 19 6 17 BERYL 20.0 102.6 26 421 +1973 6 2 18 14 PATTY 38.1 301.2 120 714 +1999 8 28 18 18 TONY 32.4 342.2 23 709 +1993 8 2 0 4 CHRIS 55.1 293.6 13 447 +1959 5 4 18 19 ISAAC 25.8 299.0 138 749 +1974 6 5 12 13 CHRIS 14.4 112.7 132 463 +1993 4 25 12 15 RAFAEL 25.1 291.9 82 156 +1988 9 22 6 26 NADINE 25.5 304.7 118 188 +1950 2 14 0 6 TONY 50.7 177.8 82 411 +1965 2 23 12 26 NADINE 56.4 281.5 18 758 +1991 4 22 12 8 VALERIE 53.6 71.3 45 461 +1954 8 28 18 12 ISAAC 20.3 90.2 53 233 +1963 10 17 12 26 GORDON 35.0 29.0 82 783 +1951 10 28 18 14 PATTY 61.2 318.3 144 774 +2001 1 15 12 6 HELENE 9.3 101.2 122 60 +1970 2 1 12 28 ERNESTO 66.5 332.8 152 402 +1984 4 26 12 23 ALBERTO 34.7 58.3 72 37 +2003 12 25 18 1 DEBBY 54.8 30.2 19 177 +1997 2 21 18 10 SANDY 31.3 112.9 112 724 +1977 8 26 18 14 ALBERTO 18.9 96.9 129 72 +1957 5 7 0 17 CHRIS 20.0 34.9 151 780 +1964 5 10 18 16 KIRK 13.0 77.5 145 92 +1989 11 15 18 12 PATTY 31.4 132.7 80 138 +1989 1 10 6 23 FLORENCE 66.2 54.9 88 155 +1977 12 26 6 14 GORDON 61.4 103.2 47 228 +1955 11 3 6 12 WILLIAM 19.4 76.6 137 254 +1963 6 7 6 17 FLORENCE 17.3 29.9 124 622 +1983 7 27 0 15 HELENE 47.0 270.1 145 518 +1991 6 13 18 23 HELENE 39.0 253.0 56 394 +1959 5 1 18 14 RAFAEL 49.3 130.6 65 684 +1995 7 10 18 2 SANDY 39.4 37.6 81 801 +1966 1 13 0 25 KIRK 21.6 40.2 60 573 +1980 9 15 6 13 VALERIE 15.5 19.7 131 554 +1950 1 27 6 3 CHRIS 20.7 181.3 100 546 +1973 11 25 0 1 VALERIE 23.2 136.6 76 38 +1998 12 28 18 11 FLORENCE 11.8 135.4 15 265 +1971 4 18 12 27 SANDY 29.6 95.9 26 251 +1986 8 4 6 19 NADINE 34.8 287.0 157 589 +1980 11 1 0 2 ISAAC 10.4 294.2 12 190 +1972 1 4 12 21 ALBERTO 28.3 168.9 120 502 +1973 6 20 0 9 CHRIS 69.8 57.0 55 575 +1984 4 2 12 11 NADINE 31.1 239.9 33 606 +1963 7 26 6 24 DEBBY 13.1 165.5 87 355 +1992 2 2 6 27 SANDY 64.3 39.0 69 340 +1955 1 19 6 9 ALBERTO 52.1 216.5 48 195 +1998 10 4 12 21 SANDY 68.0 306.5 59 26 +1972 10 8 0 28 OSCAR 9.0 69.8 138 75 +1978 11 5 6 28 ISAAC 57.7 97.3 10 832 +1968 7 28 12 22 DEBBY 66.7 199.3 164 604 +1970 2 19 12 17 CHRIS 33.6 326.0 135 459 +1979 11 6 12 18 RAFAEL 61.5 60.2 37 498 +1976 2 10 18 26 OSCAR 28.7 4.6 19 166 +1972 8 24 0 13 JOYCE 48.1 39.9 87 696 +1970 5 16 18 19 SANDY 59.1 228.6 122 191 +1996 7 5 18 5 LESLIE 11.9 234.8 17 254 +1992 8 19 12 1 MICHAEL 51.6 100.6 13 519 +1993 9 16 0 4 FLORENCE 58.0 37.3 54 157 +1994 5 6 0 22 CHRIS 9.4 243.5 51 475 +1972 1 3 6 27 FLORENCE 61.7 241.5 47 504 +1964 2 16 0 2 NADINE 8.7 160.4 128 291 +1996 12 15 18 1 GORDON 13.6 136.2 77 294 +1989 4 19 18 12 ISAAC 14.9 72.6 49 29 +1997 9 22 12 8 DEBBY 25.4 170.3 16 896 +1972 9 26 0 14 ERNESTO 45.3 180.7 31 677 +1982 2 20 0 17 SANDY 10.6 286.0 69 230 +2003 5 18 0 25 ISAAC 56.2 229.1 97 173 +1984 3 13 18 24 PATTY 41.8 180.7 141 684 +1956 2 26 0 17 MICHAEL 29.4 128.1 135 517 +1964 5 18 12 10 CHRIS 42.1 22.9 64 451 +1996 2 27 18 6 LESLIE 18.5 93.3 18 416 +1961 11 21 6 11 FLORENCE 48.6 199.8 146 95 +1982 10 14 12 18 RAFAEL 46.3 337.9 28 713 +1994 7 1 6 27 NADINE 22.9 189.1 50 193 +1964 3 6 0 18 ALBERTO 62.3 211.8 127 778 +1956 11 23 12 11 OSCAR 55.3 28.5 164 213 +1978 4 21 18 2 SANDY 8.2 202.7 61 295 +1961 9 19 18 10 CHRIS 21.3 58.9 77 884 +1994 1 14 12 13 DEBBY 33.7 124.2 92 224 +1990 8 21 6 25 VALERIE 62.8 32.5 25 203 +1955 11 3 6 23 NADINE 62.9 346.1 67 272 +1957 5 1 0 24 FLORENCE 28.8 284.4 42 111 +1960 10 22 0 22 WILLIAM 42.7 16.2 73 538 +1993 7 1 12 22 RAFAEL 64.4 311.0 127 880 +1972 3 12 6 4 CHRIS 9.7 199.4 103 174 +1998 5 27 18 26 JOYCE 53.9 176.1 38 719 +1981 8 14 0 3 DEBBY 66.5 206.8 118 777 +1988 11 19 12 24 NADINE 63.6 293.5 42 177 +1956 12 25 0 11 WILLIAM 61.1 74.6 44 451 +1986 4 9 18 8 KIRK 42.2 240.4 73 699 +1983 3 2 12 26 LESLIE 56.7 24.1 128 332 +1963 5 14 6 6 HELENE 14.3 92.9 29 254 +1952 11 3 12 15 ALBERTO 30.0 332.6 88 300 +1977 4 13 12 23 DEBBY 51.1 140.5 12 321 +1952 9 28 12 5 NADINE 30.9 73.1 10 505 +2003 10 11 0 20 VALERIE 22.3 75.3 148 803 +1981 5 19 6 1 JOYCE 23.2 206.9 143 722 +1983 11 5 18 17 ISAAC 40.9 333.9 91 592 +1957 4 13 12 28 GORDON 33.9 244.2 155 635 +1990 2 24 6 8 OSCAR 58.3 7.2 98 539 +1966 7 10 12 10 LESLIE 31.7 330.3 76 882 +1980 3 15 18 23 ERNESTO 25.9 271.1 84 409 +1954 2 21 6 10 KIRK 58.4 8.7 100 58 +1973 7 21 18 5 NADINE 55.9 275.5 85 93 +1961 3 22 6 4 RAFAEL 12.7 64.2 134 601 +1969 3 15 6 12 TONY 29.8 48.9 139 692 +1974 4 6 18 8 OSCAR 30.7 339.4 123 370 +1975 8 8 6 10 HELENE 30.3 131.3 71 590 +1980 7 23 12 22 LESLIE 28.1 316.1 140 307 +2003 3 11 6 21 LESLIE 58.3 343.6 117 235 +1996 5 26 0 5 KIRK 34.0 114.1 34 515 +1979 1 26 6 2 ALBERTO 66.6 115.9 63 441 +1992 5 19 12 1 ERNESTO 58.6 328.3 77 772 +1995 5 16 0 14 ERNESTO 19.4 263.8 16 86 +1982 10 2 6 28 TONY 47.5 272.6 120 266 +1982 9 8 0 12 PATTY 57.8 119.1 114 115 +2003 3 15 18 24 KIRK 30.6 77.8 104 135 +1962 1 12 18 13 SANDY 45.0 89.6 108 258 +1970 3 24 0 12 GORDON 59.2 23.1 92 319 +1962 2 20 18 5 RAFAEL 13.2 282.4 145 69 +1961 11 11 18 17 VALERIE 27.6 168.8 55 557 +1977 6 2 6 19 KIRK 51.5 102.6 153 546 +1997 12 28 0 13 PATTY 62.7 2.1 87 10 +1950 5 5 6 2 SANDY 20.2 108.6 41 51 +1997 2 26 12 5 OSCAR 57.6 153.0 21 793 +1977 11 15 6 19 CHRIS 40.9 134.2 10 227 +1958 9 11 18 12 ISAAC 12.8 197.1 17 268 +1956 12 21 12 11 MICHAEL 12.2 18.2 156 82 +1965 6 8 6 6 VALERIE 11.9 257.3 160 244 +1999 5 9 0 20 MICHAEL 8.0 296.7 100 148 +1999 7 19 12 4 KIRK 22.2 236.8 62 503 +1962 12 11 6 14 LESLIE 62.7 33.6 153 561 +1982 11 10 18 11 NADINE 10.1 240.4 22 677 +1997 7 9 0 10 OSCAR 57.9 203.7 94 24 +1997 5 15 0 11 JOYCE 15.4 236.5 141 573 +1990 10 6 0 28 NADINE 47.7 292.6 99 444 +2000 1 10 0 2 RAFAEL 43.8 276.4 162 262 +1968 6 22 12 4 NADINE 45.3 44.2 97 27 +1987 9 17 18 27 FLORENCE 46.7 153.1 115 119 +1984 2 16 6 2 JOYCE 66.9 56.9 21 739 +1956 4 22 18 21 JOYCE 22.9 38.2 31 727 +2001 1 16 12 6 BERYL 19.5 43.8 121 682 +1955 3 16 18 7 SANDY 59.7 280.0 51 381 +1964 8 3 6 12 HELENE 66.5 177.1 85 536 +1950 9 23 18 25 DEBBY 55.2 23.2 38 765 +1970 11 19 0 4 MICHAEL 65.6 156.9 35 469 +1991 9 6 12 8 KIRK 52.5 351.5 70 356 +1993 4 13 0 24 SANDY 53.3 316.3 34 61 +2002 10 13 0 10 BERYL 49.6 57.0 11 725 +1968 7 4 6 27 JOYCE 60.5 353.4 18 591 +1950 3 22 12 2 KIRK 68.4 333.4 37 667 +1972 1 13 12 3 WILLIAM 55.5 219.5 155 44 +1965 3 21 12 12 MICHAEL 31.7 70.3 90 884 +1995 10 24 6 2 JOYCE 37.6 121.6 83 502 +1968 9 7 6 28 GORDON 11.9 249.0 33 884 +1977 7 16 0 26 CHRIS 8.2 17.8 16 92 +1984 10 28 12 22 DEBBY 37.7 220.6 24 567 +2003 12 6 12 21 LESLIE 14.6 172.5 164 417 +1954 2 2 12 10 HELENE 54.9 351.0 59 290 +1952 10 12 12 8 FLORENCE 36.9 262.2 115 776 +1968 1 2 6 11 GORDON 19.2 50.3 18 613 +1958 6 2 18 16 JOYCE 30.2 320.8 138 799 +1972 1 21 6 8 JOYCE 29.3 41.1 46 225 +1976 4 27 12 7 SANDY 27.6 62.4 131 405 +1997 6 11 18 26 SANDY 44.2 252.4 128 255 +1985 5 4 0 7 VALERIE 22.9 320.0 114 90 +1972 6 8 12 7 DEBBY 45.1 248.3 103 89 +1951 11 8 18 6 FLORENCE 61.8 132.6 70 456 +1979 8 13 12 19 NADINE 58.2 356.2 76 862 +1956 1 24 12 19 HELENE 38.3 347.6 14 366 +1974 3 9 12 9 VALERIE 21.9 333.3 152 303 +1959 2 10 6 5 JOYCE 29.4 104.1 142 193 +1964 8 23 18 22 WILLIAM 41.7 18.6 86 401 +1954 10 1 12 1 RAFAEL 31.7 108.7 77 830 +1981 8 21 18 26 TONY 67.3 51.4 156 552 +1989 12 6 6 22 WILLIAM 12.9 269.5 54 678 +1995 6 25 6 9 TONY 8.6 52.9 65 244 +1975 2 20 12 9 HELENE 18.2 26.5 82 630 +1951 4 13 0 6 NADINE 9.0 77.9 157 766 +1974 1 4 0 20 ISAAC 27.8 90.3 55 542 +1995 7 23 6 18 PATTY 16.7 163.6 140 17 +2000 4 14 0 15 WILLIAM 31.1 97.1 61 815 +1993 10 18 0 13 MICHAEL 36.1 202.8 83 578 +1971 6 11 0 25 LESLIE 50.1 253.7 100 653 +1991 7 6 6 1 GORDON 45.9 224.3 149 71 +1968 2 1 0 11 BERYL 59.1 127.3 11 263 +1956 10 3 18 25 HELENE 42.9 351.8 154 643 +1993 9 27 6 19 WILLIAM 12.4 18.4 49 229 +2004 10 5 6 27 ERNESTO 24.2 12.8 91 282 +1975 8 18 18 9 WILLIAM 50.3 91.5 133 296 +1990 6 23 0 3 VALERIE 27.4 251.2 29 849 +1967 3 25 0 10 ISAAC 26.6 114.5 144 598 +1981 4 7 12 1 NADINE 11.2 82.3 129 554 +1951 1 8 6 23 NADINE 32.7 241.3 156 244 +1993 9 18 0 17 GORDON 67.4 243.1 39 366 +1991 7 17 0 28 VALERIE 12.8 132.9 136 570 +1968 11 4 12 3 CHRIS 55.8 149.4 29 874 +2003 1 12 0 2 TONY 10.8 276.2 142 877 +1972 1 28 12 3 WILLIAM 54.6 61.9 98 631 +1954 8 5 12 12 OSCAR 13.9 285.5 71 454 +1995 5 8 6 23 ISAAC 20.4 57.2 162 319 +1969 4 10 18 20 ALBERTO 21.4 170.4 138 291 +1995 8 18 0 24 VALERIE 17.6 129.9 94 594 +1955 4 23 18 14 ISAAC 55.5 345.0 37 463 +1952 1 8 0 28 OSCAR 31.5 356.9 152 475 +1963 6 27 0 8 ERNESTO 18.2 37.5 139 310 +1950 7 2 12 15 TONY 16.2 132.4 36 443 +1980 4 2 12 25 DEBBY 58.7 164.6 146 497 +1986 5 7 12 22 ALBERTO 30.6 106.1 139 34 +1999 7 6 12 15 BERYL 37.3 337.0 29 435 +1995 12 14 6 28 DEBBY 36.5 271.6 101 585 +1988 9 25 12 15 ALBERTO 25.9 192.7 83 11 +1996 8 8 6 23 MICHAEL 33.1 218.5 116 51 +1980 1 1 0 9 ERNESTO 41.9 49.5 81 877 +1964 2 7 0 12 DEBBY 12.4 254.6 60 98 +1996 4 28 18 9 NADINE 8.4 97.2 106 301 +1958 7 4 6 4 SANDY 59.3 219.0 18 892 +1950 11 3 6 17 TONY 10.3 195.1 135 276 +1989 6 2 0 13 OSCAR 22.7 125.0 76 471 +1985 7 7 0 3 VALERIE 45.7 345.7 85 791 +2000 8 11 18 18 VALERIE 30.9 48.1 21 423 +1968 6 6 12 18 JOYCE 13.5 153.9 36 845 +1975 3 22 6 6 VALERIE 54.5 343.8 129 898 +1989 12 8 12 12 HELENE 11.5 329.8 36 782 +2001 9 20 18 21 VALERIE 16.5 221.5 144 61 +2000 12 23 0 11 ERNESTO 54.3 207.8 119 620 +1987 11 18 12 6 WILLIAM 53.4 268.8 162 849 +1995 2 28 0 15 ERNESTO 41.7 265.3 60 80 +1983 1 11 12 2 KIRK 40.4 14.0 37 347 +1951 6 14 0 2 MICHAEL 23.4 200.5 145 361 +1957 5 7 18 24 NADINE 68.5 354.6 12 97 +1997 11 1 18 2 LESLIE 7.3 71.8 131 550 +1968 7 25 0 3 WILLIAM 29.1 23.2 16 462 +1996 12 28 18 22 KIRK 36.6 304.0 94 542 +1974 6 24 18 18 PATTY 58.9 300.2 155 352 +1963 12 17 0 8 LESLIE 26.5 33.5 158 844 +1992 8 23 12 13 OSCAR 34.1 131.2 17 774 +1959 3 26 18 25 TONY 15.1 227.2 73 318 +1995 8 21 18 10 LESLIE 48.6 191.1 26 173 +1981 10 28 18 2 CHRIS 23.3 307.6 48 433 +1991 1 7 6 13 MICHAEL 11.5 291.1 68 732 +1955 3 20 0 20 WILLIAM 28.3 100.8 91 849 +1985 12 12 6 11 DEBBY 60.7 323.1 153 279 +2002 2 24 0 26 VALERIE 55.6 344.4 157 436 +1958 10 10 18 23 GORDON 10.0 265.7 162 387 +1978 3 21 18 21 ERNESTO 22.5 317.0 155 589 +1987 6 14 6 22 JOYCE 46.7 328.8 12 372 +1984 5 15 12 9 PATTY 42.9 254.8 59 20 +1989 10 2 18 12 PATTY 56.5 134.7 146 821 +1960 3 2 6 5 PATTY 23.4 137.3 107 405 +1996 11 22 12 21 PATTY 66.6 70.4 79 213 +1951 9 22 18 18 SANDY 53.7 2.3 157 385 +1958 7 15 12 15 RAFAEL 35.7 274.2 119 848 +2004 11 9 0 7 FLORENCE 32.9 324.7 39 193 +1951 5 14 12 14 SANDY 37.7 125.3 86 43 +1991 6 5 0 24 VALERIE 21.4 46.0 120 867 +1984 11 18 6 22 CHRIS 50.2 196.5 144 651 +1965 9 15 0 22 ERNESTO 39.9 37.4 28 152 +2002 12 22 18 9 ALBERTO 63.6 347.2 101 610 +1973 11 2 18 28 LESLIE 62.9 82.0 70 680 +1963 6 22 18 14 HELENE 18.0 106.1 160 775 +1984 7 26 0 27 SANDY 29.2 175.4 73 494 +2001 7 13 6 8 FLORENCE 67.0 137.0 78 552 +1975 8 9 6 9 VALERIE 13.3 107.2 111 439 +1954 12 3 0 21 JOYCE 47.3 61.6 150 627 +1975 11 17 0 2 ISAAC 11.6 285.8 107 744 +1994 1 17 0 14 LESLIE 44.2 240.3 21 440 +1971 11 12 18 9 TONY 44.4 193.8 105 410 +1988 2 7 6 3 MICHAEL 9.3 295.1 48 68 +2004 2 4 12 16 KIRK 36.3 125.7 78 73 +1988 5 11 12 19 LESLIE 11.6 315.5 35 307 +1966 8 17 0 9 DEBBY 36.7 290.7 45 811 +1963 11 19 0 12 LESLIE 26.0 356.0 123 430 +2003 7 23 0 6 VALERIE 61.4 201.9 89 367 +1972 7 27 12 3 FLORENCE 26.7 151.2 37 60 +2003 12 1 6 8 PATTY 11.9 109.5 42 638 +2004 3 5 6 27 HELENE 54.1 84.2 130 787 +1977 10 5 12 23 WILLIAM 17.6 295.6 118 672 +1999 9 23 18 20 RAFAEL 7.1 38.7 75 58 +1979 9 24 18 20 ALBERTO 19.7 152.6 88 670 +1956 11 22 12 22 HELENE 60.4 287.0 112 801 +1962 4 12 12 1 DEBBY 63.1 44.8 141 653 +1960 2 18 18 25 WILLIAM 38.9 238.2 75 300 +1978 2 8 0 23 PATTY 21.2 71.3 154 874 +1984 11 6 0 11 LESLIE 68.0 60.5 75 366 +1964 8 25 12 23 KIRK 55.8 7.5 164 803 +1980 6 20 6 23 ALBERTO 63.2 187.4 92 842 +1989 11 24 18 26 WILLIAM 65.9 349.8 128 802 +1977 6 27 12 23 FLORENCE 13.3 255.7 79 105 +1957 7 3 0 7 BERYL 14.0 308.0 36 779 +1995 5 9 12 18 ERNESTO 32.5 332.1 164 50 +1996 2 13 18 18 SANDY 55.5 99.7 106 444 +1950 2 12 18 16 RAFAEL 63.3 189.0 42 659 +1950 1 15 6 7 ALBERTO 62.6 90.5 132 837 +1955 11 13 6 22 FLORENCE 21.2 212.5 138 16 +1969 10 3 6 9 ALBERTO 34.5 210.2 131 612 +1976 12 3 6 8 HELENE 11.5 180.7 88 23 +1954 7 12 12 8 FLORENCE 35.5 292.0 146 595 +2004 5 26 0 23 FLORENCE 42.3 9.4 12 614 +1993 8 7 18 18 MICHAEL 55.8 309.3 54 557 +1971 12 28 18 8 ERNESTO 66.1 291.7 35 133 +1961 2 6 18 24 KIRK 44.7 316.4 152 774 +1996 8 14 0 14 GORDON 47.1 357.3 135 516 +2003 12 14 12 16 SANDY 27.5 173.6 145 86 +1956 5 15 18 20 WILLIAM 32.8 1.5 141 850 +1973 12 24 6 4 SANDY 61.3 211.4 47 355 +1962 10 23 18 11 VALERIE 28.0 131.5 159 812 +1966 2 11 18 4 NADINE 29.7 239.8 20 863 +1965 10 11 6 8 JOYCE 13.2 145.5 81 899 +1997 4 1 0 23 KIRK 30.1 167.6 158 620 +1971 11 4 18 20 VALERIE 34.0 86.8 31 547 +1981 3 15 6 25 HELENE 44.7 229.8 33 838 +1985 10 15 18 2 KIRK 13.2 108.6 112 180 +1999 4 6 18 16 GORDON 26.5 118.0 42 305 +1968 2 18 6 3 PATTY 46.2 287.4 68 36 +1976 11 2 0 10 DEBBY 40.0 267.7 28 624 +1975 2 5 6 23 OSCAR 26.0 47.7 49 243 +1956 12 28 12 2 ALBERTO 52.1 349.1 79 128 +1977 3 21 18 28 ERNESTO 53.8 53.1 122 337 +1952 1 14 6 2 ALBERTO 43.9 311.2 151 666 +1979 5 28 6 13 ERNESTO 63.9 292.5 93 846 +1977 1 27 18 9 NADINE 25.2 326.1 122 753 +1975 7 5 0 3 SANDY 50.2 166.6 22 174 +1989 11 25 0 1 VALERIE 7.5 205.9 145 745 +1995 5 10 0 23 BERYL 33.7 151.5 32 260 +1982 2 1 6 7 ALBERTO 57.0 65.6 29 723 +1954 4 20 12 17 RAFAEL 28.5 47.7 85 638 +1984 2 1 6 11 TONY 69.2 229.3 108 474 +2000 8 11 12 7 ISAAC 60.5 141.2 35 895 +1985 1 20 18 22 KIRK 49.7 108.1 145 182 +1956 9 1 18 11 HELENE 42.4 305.0 28 173 +1962 5 5 12 18 DEBBY 59.3 98.1 38 55 +1972 7 10 18 28 SANDY 40.8 276.9 155 542 +1960 9 16 6 17 FLORENCE 33.2 255.9 147 838 +1980 1 4 18 21 TONY 61.0 82.7 164 769 +1967 6 6 0 21 MICHAEL 44.1 230.7 63 745 +1962 8 2 0 11 LESLIE 49.0 135.8 82 112 +2003 2 5 0 13 ISAAC 20.4 325.0 21 221 +1956 3 4 18 9 NADINE 45.7 268.7 161 17 +1965 3 17 0 14 ERNESTO 8.3 0.3 160 680 +1953 7 25 6 22 MICHAEL 57.2 145.0 113 535 +1975 9 11 18 6 HELENE 48.2 44.3 42 501 +2001 4 21 0 21 VALERIE 27.9 278.8 48 195 +1959 12 16 0 13 GORDON 39.6 3.2 152 820 +1965 10 24 18 19 FLORENCE 25.3 333.3 36 469 +1989 4 2 18 5 SANDY 55.0 257.4 64 618 +1953 2 16 0 20 LESLIE 54.8 234.9 108 376 +1998 6 24 18 22 SANDY 57.1 234.8 121 616 +2002 10 23 12 8 FLORENCE 51.1 123.6 25 432 +1963 11 19 12 19 GORDON 68.7 120.3 114 134 +1986 10 5 0 4 LESLIE 24.3 323.1 54 871 +1964 8 25 0 12 ERNESTO 10.2 216.5 20 442 +1969 10 8 18 20 OSCAR 44.0 302.3 164 539 +1992 12 9 18 7 WILLIAM 33.2 119.0 107 526 +1956 2 19 0 21 ISAAC 28.8 274.5 12 885 +1996 11 13 0 17 ALBERTO 44.6 281.7 163 505 +1984 3 6 6 25 LESLIE 15.9 17.1 131 603 +1965 4 6 0 9 VALERIE 54.0 235.8 45 553 +1967 10 26 0 22 PATTY 68.8 39.0 160 679 +1994 2 13 0 4 TONY 20.3 71.8 108 860 +1973 11 6 6 5 OSCAR 13.0 338.7 144 797 +1957 5 3 0 16 OSCAR 32.6 341.7 84 24 +1965 12 26 18 24 PATTY 52.9 49.2 127 657 +1962 11 28 18 15 ALBERTO 64.7 198.9 116 673 +1956 12 6 0 23 NADINE 27.2 178.8 44 371 +1994 10 15 6 3 DEBBY 21.1 173.6 39 319 +1979 1 8 12 28 SANDY 11.6 307.7 38 820 +1985 3 7 6 21 VALERIE 15.1 4.4 147 344 +2001 6 2 18 4 TONY 47.3 263.1 121 684 +1994 11 7 6 27 SANDY 30.2 67.5 88 641 +1951 11 15 12 15 DEBBY 35.3 33.2 93 648 +2004 10 5 12 8 SANDY 8.8 239.8 53 511 +1958 3 4 6 11 SANDY 35.3 103.0 106 53 +1995 12 10 12 28 CHRIS 41.8 308.4 79 389 +1988 5 5 18 13 CHRIS 35.9 184.9 11 140 +1999 10 28 12 19 VALERIE 32.7 265.2 103 602 +1957 8 19 0 23 OSCAR 33.3 107.5 121 588 +1970 7 17 0 13 BERYL 31.0 119.1 60 753 +1997 6 25 18 24 VALERIE 67.3 116.0 100 359 +1997 11 5 12 16 NADINE 14.7 39.9 46 697 +1994 6 21 6 5 VALERIE 18.7 123.1 158 694 +1997 5 8 6 9 ISAAC 43.0 46.8 29 361 +1988 5 23 12 24 PATTY 19.2 37.8 20 664 +1999 9 17 6 16 GORDON 52.6 355.5 69 31 +1958 3 27 12 24 BERYL 27.1 140.8 32 883 +1966 2 24 0 2 OSCAR 9.5 337.5 77 60 +1963 9 24 12 5 TONY 34.9 176.6 104 441 +1989 7 14 0 13 KIRK 19.4 321.1 52 616 +1985 6 20 6 18 SANDY 23.7 186.8 129 228 +1992 5 9 18 2 BERYL 11.4 15.2 114 478 +1964 6 28 0 13 DEBBY 30.2 261.5 160 174 +1986 3 27 0 4 NADINE 61.9 303.1 123 198 +1985 1 16 12 11 MICHAEL 29.9 289.3 58 195 +1997 8 5 0 24 HELENE 37.3 320.9 108 339 +1957 2 16 6 15 NADINE 64.3 345.1 48 533 +1972 6 5 18 9 VALERIE 54.6 155.2 10 626 +1971 6 23 0 14 PATTY 67.1 139.8 50 377 +1966 7 25 0 14 MICHAEL 31.1 80.7 86 322 +1960 9 22 0 8 ERNESTO 68.7 353.6 128 78 +1996 5 17 12 19 GORDON 28.0 129.8 128 611 +1972 10 26 0 28 ISAAC 27.9 267.1 82 522 +1951 9 23 12 26 VALERIE 46.8 105.2 88 693 +1954 6 26 6 14 CHRIS 25.0 289.1 88 232 +1994 6 14 12 22 ISAAC 36.5 282.8 52 719 +1958 1 8 6 22 LESLIE 69.4 310.6 67 376 +1968 10 24 12 7 FLORENCE 66.7 299.3 130 705 +1980 2 12 18 6 CHRIS 47.6 233.4 129 208 +1974 5 26 6 9 JOYCE 33.0 34.4 159 450 +1970 10 9 6 9 FLORENCE 61.7 168.1 43 51 +1965 9 8 0 2 NADINE 23.0 20.4 19 640 +1969 11 13 0 3 VALERIE 54.0 176.2 150 112 +1969 1 11 12 22 FLORENCE 64.2 134.7 159 49 +1981 3 10 6 9 BERYL 47.8 332.5 133 782 +1993 3 11 0 2 SANDY 22.8 68.6 47 277 +1983 3 8 18 16 GORDON 65.8 214.3 126 584 +1983 11 9 6 20 WILLIAM 29.7 108.2 24 328 +1973 10 14 12 22 FLORENCE 41.1 339.1 163 134 +1962 2 11 6 24 CHRIS 54.1 193.3 45 137 +1969 3 2 18 5 WILLIAM 61.7 169.5 10 736 +1984 2 13 12 10 BERYL 67.5 73.5 10 781 +2003 5 14 0 10 HELENE 19.9 175.3 59 190 +2003 10 2 12 27 GORDON 40.2 70.6 80 401 +2004 4 20 6 19 ALBERTO 41.6 196.3 120 115 +2004 6 18 0 20 BERYL 37.8 59.5 66 133 +1954 9 19 12 12 WILLIAM 67.5 43.7 46 149 +1981 2 11 12 10 ISAAC 48.5 172.1 132 19 +1998 12 19 0 23 GORDON 7.1 288.6 85 95 +1980 6 18 18 20 DEBBY 46.0 42.4 149 387 +2000 3 20 6 9 SANDY 61.7 333.5 47 1 +1981 3 27 18 23 BERYL 41.5 300.9 75 481 +1959 11 22 18 6 ALBERTO 54.3 305.9 87 705 +1968 2 15 6 10 OSCAR 50.9 133.0 134 112 +1987 11 23 18 11 ERNESTO 23.5 286.8 122 139 +1968 11 7 6 5 SANDY 56.9 64.7 44 745 +1950 4 3 18 9 SANDY 29.0 312.9 20 127 +1969 7 23 12 9 PATTY 34.8 21.9 115 416 +1959 10 8 0 12 SANDY 32.6 241.9 75 311 +1960 7 6 12 8 ALBERTO 7.2 297.6 66 726 +1963 1 28 0 9 TONY 35.7 295.4 53 442 +1997 10 19 12 6 MICHAEL 11.4 161.8 46 254 +1993 2 6 18 6 TONY 36.3 347.7 103 660 +1958 12 9 6 23 CHRIS 17.4 283.2 125 742 +2004 10 22 6 5 DEBBY 20.6 255.7 20 364 +1974 12 3 18 20 GORDON 61.3 253.4 148 62 +1977 2 20 6 19 ERNESTO 57.4 270.8 137 128 +1953 9 15 6 22 MICHAEL 39.2 156.3 102 178 +1984 5 12 18 8 NADINE 21.6 345.0 17 118 +1989 12 19 18 1 VALERIE 44.8 210.5 159 689 +1997 9 11 18 4 KIRK 47.1 343.3 50 314 +1982 11 22 12 24 BERYL 10.4 239.0 15 433 +1967 6 16 18 28 BERYL 26.3 352.7 159 225 +1953 2 4 6 11 TONY 30.2 73.3 135 602 +1997 9 6 0 20 GORDON 55.8 230.3 78 471 +1962 3 8 0 3 ERNESTO 39.5 130.8 44 514 +1975 3 4 6 28 VALERIE 26.6 160.5 138 669 +1989 8 24 0 24 OSCAR 63.5 325.8 71 557 +1953 11 15 12 8 CHRIS 12.9 330.5 38 557 +1976 2 1 0 6 HELENE 35.4 24.8 64 557 +1970 1 20 6 28 CHRIS 11.4 313.1 34 434 +1971 4 3 18 15 WILLIAM 62.8 51.4 65 546 +1967 6 20 6 3 SANDY 38.8 189.9 109 176 +1953 6 15 6 3 DEBBY 13.2 267.4 57 635 +1974 3 28 12 12 VALERIE 34.6 85.2 145 739 +1975 10 17 12 28 FLORENCE 54.6 233.7 16 277 +1968 10 17 18 11 HELENE 64.7 134.4 112 59 +1967 12 14 12 13 RAFAEL 50.2 218.7 128 381 +1963 2 27 18 27 DEBBY 61.7 221.0 163 243 +1999 6 4 12 16 HELENE 45.5 131.6 79 501 +1997 2 27 12 28 WILLIAM 44.7 251.5 128 281 +1977 3 22 12 23 BERYL 26.1 189.5 67 285 +1982 2 27 0 21 RAFAEL 40.0 77.6 72 74 +1986 10 3 6 15 ALBERTO 23.0 63.2 144 501 +1984 4 23 0 5 ERNESTO 28.3 162.0 107 182 +1989 6 20 0 3 DEBBY 34.3 154.0 124 405 +1951 12 10 0 7 VALERIE 54.3 35.5 49 165 +1951 12 9 12 15 NADINE 40.9 191.2 97 899 +1961 3 8 0 19 NADINE 28.3 175.1 13 581 +1978 2 3 18 1 TONY 17.4 309.5 108 269 +2001 1 22 12 25 FLORENCE 46.7 100.4 152 761 +1982 9 21 6 4 JOYCE 40.3 153.4 89 837 +1971 5 11 0 6 ISAAC 39.7 102.7 65 231 +1968 8 10 12 9 MICHAEL 47.0 258.8 30 91 +1999 4 9 0 5 VALERIE 36.7 91.7 29 518 +2001 1 6 6 16 JOYCE 59.5 177.9 103 265 +1962 1 5 0 8 VALERIE 48.6 2.0 111 655 +2001 6 10 12 27 VALERIE 21.3 258.1 148 88 +1999 10 28 0 27 PATTY 12.5 84.9 19 643 +1970 4 15 6 17 RAFAEL 58.1 8.0 74 353 +1966 4 3 12 26 PATTY 42.6 275.4 39 591 +2000 4 23 6 2 TONY 24.7 159.6 119 341 +1963 9 19 6 3 CHRIS 27.4 283.4 89 562 +1969 10 11 6 28 GORDON 25.9 252.1 23 103 +1994 12 27 12 7 OSCAR 28.6 25.9 36 165 +1963 8 3 6 5 VALERIE 23.4 234.4 159 477 +1985 6 19 18 9 NADINE 64.8 77.7 105 577 +1995 9 10 18 15 RAFAEL 54.0 70.3 11 422 +1974 7 15 12 17 OSCAR 58.4 296.3 49 589 +1979 4 19 0 18 ERNESTO 38.5 160.3 101 253 +1985 9 24 0 16 BERYL 27.1 25.2 60 277 +1983 1 3 18 2 VALERIE 22.9 212.2 161 179 +1979 10 25 0 14 OSCAR 52.8 73.0 149 488 +1957 6 15 6 2 HELENE 36.8 309.4 43 828 +2004 1 12 12 12 TONY 65.2 278.8 52 369 +1970 2 5 0 11 RAFAEL 15.7 252.0 113 721 +1964 6 26 0 3 MICHAEL 57.0 143.1 20 368 +1974 11 25 0 2 OSCAR 57.9 146.9 110 440 +1979 1 23 12 3 PATTY 68.2 41.2 21 43 +1999 10 18 18 3 SANDY 19.9 330.1 12 785 +1958 8 10 18 26 ERNESTO 20.4 185.9 11 892 +1995 5 9 18 2 VALERIE 20.0 195.0 34 820 +1986 6 26 18 1 SANDY 23.1 282.6 77 715 +1971 12 26 6 22 ISAAC 42.9 232.0 91 271 +1976 2 23 18 3 LESLIE 66.9 345.5 14 473 +2001 1 23 12 19 PATTY 15.7 40.6 38 223 +1954 4 7 12 17 MICHAEL 48.3 52.2 58 124 +1981 2 13 0 15 CHRIS 23.9 282.9 64 782 +1968 6 20 6 12 CHRIS 59.1 131.4 122 98 +1968 9 17 0 16 ERNESTO 29.0 54.8 114 436 +1980 2 15 6 19 MICHAEL 62.7 179.0 69 131 +1955 7 8 12 13 BERYL 22.9 323.9 69 733 +1976 8 9 0 9 DEBBY 7.1 123.4 76 499 +1984 6 21 6 21 TONY 63.9 342.0 53 200 +1952 11 19 12 3 KIRK 46.4 69.5 17 137 +1970 9 28 18 8 SANDY 27.1 321.4 35 163 +1994 7 8 0 14 BERYL 43.5 270.1 152 467 +1980 3 12 6 22 HELENE 30.5 327.8 134 791 +1953 7 25 12 21 WILLIAM 64.4 338.6 123 129 +1958 3 3 18 22 BERYL 32.7 268.0 67 46 +1979 7 3 0 9 FLORENCE 21.0 131.7 139 784 +1951 8 10 6 1 VALERIE 52.2 266.3 106 845 +1952 6 20 18 8 MICHAEL 64.5 118.2 105 856 +1982 3 12 0 22 DEBBY 24.5 305.3 143 797 +1950 2 26 0 23 OSCAR 49.5 267.4 103 460 +1976 9 9 12 24 RAFAEL 44.1 256.2 69 683 +1994 1 23 0 6 RAFAEL 69.3 31.4 154 797 +1980 11 22 0 7 ISAAC 15.6 121.1 122 877 +1974 11 6 12 9 CHRIS 17.4 261.5 35 458 +1962 11 19 0 22 MICHAEL 18.6 15.3 140 35 +1969 10 17 6 3 KIRK 11.5 350.3 139 486 +1963 4 6 6 8 HELENE 63.7 209.3 33 404 +1962 4 9 12 19 SANDY 29.6 198.4 62 517 +1951 7 17 0 6 TONY 23.9 51.7 45 432 +1954 8 26 0 22 NADINE 29.4 313.0 108 656 +2002 6 11 6 12 FLORENCE 34.9 215.9 150 605 +1960 8 16 0 24 CHRIS 15.1 3.1 37 94 +1998 6 9 18 24 HELENE 42.4 232.7 128 653 +1954 9 16 12 11 OSCAR 59.3 330.5 102 79 +1980 8 16 12 3 KIRK 52.9 227.2 56 540 +1993 3 18 0 25 RAFAEL 37.3 298.8 11 83 +1974 10 2 6 20 OSCAR 55.7 247.3 134 465 +1967 9 9 18 6 CHRIS 39.3 68.9 150 294 +1971 6 2 6 10 VALERIE 22.9 285.0 134 547 +1993 4 28 0 27 PATTY 9.5 184.7 31 64 +1955 5 12 18 2 ISAAC 27.8 102.6 21 605 +1997 1 13 0 22 JOYCE 8.7 263.8 66 861 +1980 4 19 18 14 RAFAEL 42.7 155.4 32 492 +2004 7 11 12 21 PATTY 32.1 235.6 73 343 +2001 12 26 12 15 VALERIE 41.0 275.1 19 128 +1959 7 15 0 26 JOYCE 14.2 205.9 92 29 +1998 9 23 6 5 WILLIAM 37.8 58.3 67 236 +1950 5 24 6 23 LESLIE 51.2 339.3 38 316 +1989 4 28 6 2 HELENE 15.7 287.0 32 817 +1982 11 21 6 16 GORDON 24.4 57.3 36 188 +1988 12 16 6 16 RAFAEL 54.0 38.7 14 312 +1998 3 26 12 12 PATTY 14.4 206.0 132 60 +1979 5 18 12 17 ISAAC 35.8 169.6 76 818 +1950 5 10 18 2 ERNESTO 11.5 292.2 154 891 +1960 9 22 0 21 ISAAC 25.0 60.0 61 212 +1994 9 26 0 3 LESLIE 37.5 98.5 21 709 +1985 1 20 12 21 WILLIAM 37.8 231.5 134 297 +1959 5 18 12 7 ERNESTO 27.0 16.7 105 182 +1974 8 2 18 8 WILLIAM 65.0 231.2 156 871 +1955 5 12 6 3 WILLIAM 46.9 224.2 56 892 +1972 9 21 0 5 TONY 42.2 180.0 97 642 +1996 4 9 6 12 SANDY 8.7 268.7 11 246 +2000 1 20 6 25 DEBBY 18.1 10.8 47 506 +1987 4 18 0 16 SANDY 64.7 44.6 123 455 +1980 5 16 12 1 BERYL 20.3 185.7 50 225 +1970 10 2 18 20 FLORENCE 30.2 207.5 106 364 +1963 1 15 18 4 JOYCE 66.6 118.7 23 407 +1965 2 19 0 6 SANDY 68.6 305.0 37 190 +1965 8 24 6 15 CHRIS 44.6 158.8 65 859 +1957 9 9 0 28 KIRK 52.8 353.6 46 542 +1965 1 26 18 4 MICHAEL 11.3 106.7 18 449 +1984 2 28 0 10 WILLIAM 7.7 161.9 99 144 +1969 12 27 12 14 FLORENCE 43.6 120.5 54 405 +1961 10 1 18 10 WILLIAM 67.9 336.0 64 223 +1980 11 19 0 19 BERYL 44.9 76.0 156 547 +1974 10 28 12 3 JOYCE 44.3 112.0 146 57 +1952 3 8 6 10 RAFAEL 55.8 234.4 130 394 +1997 6 21 18 5 ERNESTO 9.4 252.8 25 424 +1992 8 4 0 7 FLORENCE 65.3 349.7 119 720 +1956 8 18 18 14 PATTY 26.3 195.2 114 80 +1986 12 26 6 22 VALERIE 18.6 205.7 73 882 +1958 9 5 12 14 PATTY 46.2 102.4 144 575 +1959 11 19 6 21 CHRIS 50.4 299.7 63 600 +2003 10 10 12 7 BERYL 68.9 257.5 91 141 +1968 6 15 6 18 ERNESTO 39.0 264.5 156 812 +1965 9 28 6 27 LESLIE 65.7 55.7 97 731 +1997 4 17 6 28 ALBERTO 41.3 203.9 121 394 +1961 8 25 18 23 SANDY 17.6 102.5 16 203 +1955 7 25 0 21 WILLIAM 50.5 324.4 19 773 +1977 11 24 0 20 ISAAC 69.8 237.6 146 271 +1971 6 24 18 26 JOYCE 45.0 102.8 142 547 +2003 12 6 18 24 WILLIAM 26.9 6.5 106 59 +1971 7 2 18 22 NADINE 13.7 108.8 138 293 +1985 7 18 6 21 JOYCE 58.8 310.1 100 412 +1980 3 16 18 26 JOYCE 18.5 4.7 51 469 +1996 5 2 6 7 MICHAEL 56.7 311.7 124 655 +1971 7 6 6 20 PATTY 60.9 137.7 31 446 +1976 4 26 18 15 TONY 13.8 250.4 27 90 +1952 9 16 12 8 PATTY 46.9 333.6 130 743 +1968 7 14 18 27 ERNESTO 11.9 248.2 118 145 +1978 5 2 12 27 GORDON 43.1 126.6 123 690 +1989 1 23 6 8 GORDON 13.6 127.5 17 39 +1976 7 4 18 10 MICHAEL 65.0 351.3 148 33 +2004 4 15 12 24 ALBERTO 62.3 117.4 26 21 +1983 12 27 12 22 ISAAC 32.0 163.9 57 546 +2003 7 10 18 5 PATTY 45.9 166.1 42 166 +1957 12 24 0 18 NADINE 29.9 303.0 33 11 +1970 12 7 0 17 GORDON 13.9 18.0 143 718 +1960 8 19 6 18 BERYL 12.5 262.5 40 301 +1954 7 5 18 15 VALERIE 11.3 265.4 54 289 +1953 12 22 18 15 WILLIAM 8.4 105.0 23 428 +1988 11 9 6 10 NADINE 38.6 270.1 117 452 +1978 6 2 12 7 SANDY 33.1 41.8 99 792 +1952 6 10 18 14 MICHAEL 33.9 223.1 155 56 +1986 4 4 12 16 ALBERTO 50.6 243.7 61 698 +1990 11 22 0 4 RAFAEL 23.9 127.8 155 143 +1956 3 15 6 11 NADINE 65.0 148.3 110 517 +1958 12 22 18 25 WILLIAM 57.9 123.6 105 718 +1962 1 18 0 23 BERYL 69.0 145.3 122 757 +1975 9 28 12 18 VALERIE 43.0 235.6 55 319 +1957 2 15 0 4 TONY 62.6 59.6 54 7 +1984 11 1 18 21 FLORENCE 27.4 170.6 142 107 +2004 2 1 6 2 PATTY 56.5 43.4 82 609 +1953 9 16 6 17 OSCAR 38.6 65.5 26 405 +1997 4 6 6 27 ISAAC 32.2 166.2 51 225 +1986 7 9 18 22 MICHAEL 32.5 243.8 120 631 +1982 4 24 18 5 RAFAEL 57.2 171.2 53 383 +1960 10 12 0 11 ALBERTO 64.6 334.5 144 837 +1963 7 23 18 27 KIRK 64.9 322.0 147 132 +1999 8 1 0 9 ERNESTO 19.6 127.8 154 487 +1994 10 16 0 20 VALERIE 10.7 192.1 25 222 +1952 5 11 18 18 WILLIAM 55.7 0.1 99 300 +2004 4 21 12 6 ALBERTO 55.9 205.2 104 856 +1975 11 8 12 22 BERYL 31.3 245.4 49 162 +1993 5 7 18 25 NADINE 43.4 15.4 58 739 +1954 9 25 0 22 LESLIE 49.1 14.7 111 702 +1962 10 20 18 12 FLORENCE 62.3 288.2 67 432 +1959 1 14 0 4 BERYL 35.5 332.0 37 694 +1974 12 6 12 9 HELENE 29.8 327.5 33 674 +1975 12 13 18 25 TONY 63.8 9.6 144 684 +2001 12 3 12 28 RAFAEL 62.0 356.6 105 220 +1999 9 11 12 12 DEBBY 7.5 111.2 118 591 +1981 6 7 12 27 CHRIS 21.8 198.9 111 811 +1976 7 21 6 25 ALBERTO 50.7 104.9 100 195 +1994 11 7 6 24 DEBBY 37.0 260.9 58 146 +1963 6 15 0 7 FLORENCE 14.6 86.5 80 458 +2000 10 11 0 5 GORDON 8.5 40.9 51 721 +1989 5 27 12 16 SANDY 8.9 214.9 30 424 +1984 4 20 6 21 LESLIE 44.9 214.0 69 664 +1992 2 8 0 4 VALERIE 33.7 301.2 137 350 +1992 4 14 18 10 ISAAC 49.5 312.6 42 120 +1982 5 2 18 19 SANDY 43.0 180.0 155 510 +1989 2 3 6 13 CHRIS 68.5 100.2 94 305 +1962 12 2 12 3 WILLIAM 14.6 27.8 114 185 +1966 8 21 6 3 OSCAR 43.6 173.5 114 557 +1974 1 7 12 6 OSCAR 62.1 212.0 35 500 +1966 5 2 18 9 RAFAEL 54.4 141.1 120 707 +1991 11 15 6 25 ERNESTO 15.2 149.9 129 360 +1987 6 12 12 7 LESLIE 68.8 269.3 110 545 +1993 10 25 12 3 FLORENCE 55.5 294.0 156 490 +2002 4 17 12 1 JOYCE 17.5 272.4 27 749 +1973 6 28 12 22 BERYL 44.0 4.0 45 868 +1962 11 4 6 27 GORDON 69.2 310.3 45 410 +1960 10 12 0 15 ALBERTO 41.3 336.9 21 739 +1984 11 7 0 19 RAFAEL 12.5 261.8 112 396 +1977 12 14 0 8 NADINE 9.8 214.9 152 405 +1977 2 2 12 11 HELENE 35.8 258.1 57 556 +1988 9 11 0 12 TONY 25.7 91.4 29 296 +1992 2 1 6 24 WILLIAM 9.2 228.5 96 500 +1956 7 13 0 7 NADINE 38.2 337.4 18 823 +1957 1 18 12 3 ERNESTO 57.3 225.1 26 492 +1978 4 28 12 3 RAFAEL 56.4 309.7 158 729 +1987 11 26 12 7 WILLIAM 28.9 192.8 154 668 +1970 9 22 12 28 RAFAEL 57.1 292.3 86 204 +1985 6 14 12 13 VALERIE 46.4 349.3 94 271 +1978 10 8 6 12 VALERIE 7.4 311.6 30 773 +1951 3 13 18 6 RAFAEL 45.2 5.1 68 431 +1996 10 23 6 18 CHRIS 16.9 70.2 73 731 +1974 3 5 12 10 MICHAEL 37.4 18.5 58 851 +1987 5 28 12 26 LESLIE 48.2 126.0 160 760 +1958 9 13 12 17 SANDY 50.5 79.3 116 368 +1968 12 27 0 4 OSCAR 30.4 8.2 25 833 +1981 10 20 18 5 VALERIE 65.7 31.0 105 618 +1975 7 4 0 5 GORDON 45.3 205.7 106 432 +1953 7 15 12 15 LESLIE 46.3 238.2 60 47 +1953 11 10 18 26 NADINE 13.8 240.1 150 388 +1957 3 27 0 26 KIRK 12.3 335.5 114 285 +1950 11 17 12 10 MICHAEL 43.6 220.5 149 698 +1971 11 1 6 11 BERYL 51.2 10.3 91 182 +1999 6 15 12 1 VALERIE 22.7 223.7 94 884 +1973 1 20 12 20 CHRIS 54.9 35.8 129 617 +1999 3 23 18 10 SANDY 36.5 217.6 122 149 +2002 7 14 12 19 OSCAR 31.8 299.9 13 358 +1963 8 15 6 12 RAFAEL 65.0 207.0 73 742 +1974 7 16 12 14 CHRIS 63.6 86.9 68 450 +1964 3 23 18 1 TONY 47.6 328.3 13 371 +1959 8 22 6 21 WILLIAM 33.5 244.2 45 445 +1953 7 27 6 27 SANDY 13.7 171.4 95 219 +1981 3 2 18 3 PATTY 43.5 182.3 134 593 +1984 7 7 18 6 ISAAC 24.5 148.1 118 367 +1957 7 22 12 25 ALBERTO 60.2 80.7 155 171 +1981 1 26 6 9 PATTY 58.3 40.5 11 623 +1977 7 6 18 14 FLORENCE 38.7 95.2 17 857 +1989 5 1 6 16 HELENE 36.5 129.7 74 39 +1991 4 15 0 4 SANDY 39.4 101.6 18 572 +1969 12 21 6 7 WILLIAM 27.8 134.6 158 247 +1966 6 16 6 15 FLORENCE 11.5 121.7 36 819 +1993 4 10 12 21 WILLIAM 30.9 192.0 101 303 +1984 9 23 12 21 ISAAC 43.3 349.1 93 310 +1991 4 27 6 27 ISAAC 48.6 49.0 24 625 +1982 8 2 0 19 JOYCE 29.0 67.1 91 135 +1974 6 22 18 11 MICHAEL 14.5 214.7 30 874 +1963 3 13 18 17 LESLIE 42.1 256.4 159 822 +2002 8 7 0 14 BERYL 16.4 230.0 16 361 +1961 3 14 12 14 RAFAEL 24.0 264.4 57 674 +1952 11 6 12 5 CHRIS 33.5 133.0 10 346 +2002 7 16 12 20 VALERIE 7.7 193.9 84 463 +1987 5 7 12 22 WILLIAM 66.9 221.0 81 23 +1955 2 9 0 12 TONY 15.6 193.0 129 560 +1994 2 14 12 7 ISAAC 23.8 249.6 30 358 +1985 7 6 12 1 HELENE 23.7 173.9 71 506 +1956 11 7 0 21 ALBERTO 31.5 75.4 40 68 +1999 10 24 0 21 MICHAEL 42.4 214.3 158 90 +1961 8 7 0 17 BERYL 44.8 302.6 16 364 +1961 2 26 12 16 TONY 70.0 62.1 67 866 +1977 1 3 0 4 SANDY 18.5 329.8 109 464 +1955 4 5 18 8 BERYL 55.6 303.4 55 866 +1975 9 6 0 18 FLORENCE 23.5 184.9 90 59 +1971 10 17 6 2 LESLIE 26.0 217.6 91 27 +1970 3 24 12 16 ALBERTO 26.1 121.6 162 482 +1972 9 9 6 6 NADINE 43.5 259.0 156 625 +1977 1 22 0 19 SANDY 8.9 36.0 11 134 +1987 4 21 0 26 SANDY 8.1 343.7 96 562 +1950 12 10 12 17 TONY 39.1 347.1 30 195 +1980 6 17 0 24 ISAAC 46.3 344.2 31 451 +1956 3 10 12 18 DEBBY 9.2 14.8 155 892 +1986 9 18 18 10 ERNESTO 48.2 275.9 137 159 +1981 3 11 18 2 KIRK 53.4 35.5 11 492 +1964 9 24 6 11 RAFAEL 14.5 83.4 62 574 +2001 2 10 0 8 WILLIAM 25.7 255.2 28 353 +1953 7 8 12 20 MICHAEL 56.7 315.1 34 733 +1993 11 10 18 21 TONY 27.9 170.0 17 636 +1968 12 9 0 1 VALERIE 25.2 166.9 58 541 +1956 4 6 12 10 FLORENCE 19.4 0.6 13 312 +1971 2 2 18 2 PATTY 10.9 15.3 68 801 +1984 11 5 18 23 MICHAEL 45.6 333.5 79 766 +1999 9 7 6 2 RAFAEL 42.2 287.6 47 792 +1974 4 15 6 28 HELENE 57.0 340.4 74 24 +1974 12 23 6 6 ERNESTO 49.2 299.0 72 515 +1953 9 12 0 12 ISAAC 57.6 275.6 139 896 +2001 7 25 0 10 FLORENCE 39.5 25.1 31 12 +1956 12 19 12 19 BERYL 19.6 258.3 77 669 +2002 4 21 0 14 FLORENCE 49.7 196.8 146 536 +1975 5 15 18 23 WILLIAM 59.1 7.1 15 387 +1957 4 6 12 9 NADINE 25.0 19.2 96 728 +1957 9 21 6 18 TONY 26.5 111.4 89 446 +1977 10 10 12 20 MICHAEL 21.3 304.5 143 98 +1997 5 3 6 16 JOYCE 50.5 69.5 116 362 +1954 10 9 6 6 MICHAEL 31.3 92.1 120 457 +1963 2 6 0 4 KIRK 22.6 147.6 161 582 +1967 6 22 0 8 KIRK 46.9 196.6 129 747 +1961 6 10 6 18 JOYCE 50.1 124.6 52 410 +1954 4 9 6 21 TONY 17.0 105.2 97 88 +1999 2 2 0 4 FLORENCE 51.9 182.7 148 293 +1972 8 22 6 20 TONY 56.6 250.2 56 652 +1988 8 23 0 25 LESLIE 30.3 142.8 34 709 +1966 8 25 12 13 BERYL 36.1 163.0 104 748 +1984 5 27 6 25 GORDON 49.1 149.0 137 865 +2003 4 17 18 26 KIRK 51.8 328.2 152 786 +1961 1 3 12 14 OSCAR 27.3 278.0 107 31 +1991 6 3 18 10 CHRIS 33.6 195.1 122 770 +2002 11 6 6 28 SANDY 58.9 61.6 119 896 +1965 11 27 0 11 HELENE 22.1 116.9 100 49 +1956 9 21 6 5 MICHAEL 63.5 154.0 44 278 +1978 6 12 12 24 SANDY 27.3 149.9 113 539 +1957 6 17 18 4 CHRIS 55.0 227.9 31 96 +1964 5 9 12 18 GORDON 60.7 187.1 161 730 +1967 6 20 0 11 LESLIE 31.6 143.1 72 708 +1953 3 21 12 12 TONY 65.6 106.6 30 893 +2002 1 7 18 9 RAFAEL 32.4 120.1 27 61 +1973 4 12 6 27 NADINE 56.6 89.2 73 766 +1979 11 1 18 22 WILLIAM 47.8 283.5 14 645 +1965 2 18 12 11 BERYL 9.3 351.9 55 318 +1951 3 12 6 17 VALERIE 39.2 165.0 31 339 +1961 11 9 12 25 NADINE 62.6 139.8 127 163 +1987 6 7 0 20 LESLIE 50.4 176.4 52 300 +1972 4 11 18 12 NADINE 27.0 170.3 122 74 +1962 7 15 0 23 TONY 51.3 57.7 109 292 +1999 3 23 18 9 WILLIAM 40.5 258.8 151 859 +1995 9 25 0 23 NADINE 17.8 312.1 114 259 +1993 1 7 18 7 MICHAEL 32.7 173.2 16 461 +1966 5 24 12 27 TONY 35.7 157.6 11 395 +1952 4 25 6 25 CHRIS 69.1 144.5 36 384 +1992 5 14 12 14 NADINE 13.1 209.6 120 677 +1956 9 7 6 19 KIRK 13.1 101.5 68 437 +1959 5 4 0 3 BERYL 9.0 313.5 49 473 +1955 2 10 18 25 SANDY 48.5 46.2 55 46 +1998 2 18 18 27 VALERIE 39.2 285.1 132 220 +1981 11 24 12 21 TONY 25.9 83.0 95 98 +1951 10 7 0 13 GORDON 67.2 286.7 137 691 +1995 2 5 18 1 MICHAEL 42.0 279.7 78 415 +1965 2 1 6 11 KIRK 45.1 191.7 145 485 +1963 1 23 6 17 NADINE 28.3 198.2 44 468 +1973 1 13 6 3 NADINE 63.5 345.8 47 481 +1968 8 8 6 21 WILLIAM 64.6 200.6 55 386 +2002 11 25 0 19 SANDY 35.6 53.3 49 828 +1952 2 19 12 22 ERNESTO 66.7 198.3 45 245 +1979 3 27 12 8 ALBERTO 11.2 226.5 19 800 +1953 8 12 0 1 WILLIAM 49.6 211.3 57 718 +2001 5 9 0 28 NADINE 63.1 190.9 71 593 +1977 4 9 6 5 OSCAR 68.9 278.8 93 358 +1958 9 22 12 8 HELENE 35.8 297.3 71 308 +1969 2 25 18 25 ALBERTO 8.3 137.1 13 357 +1964 12 26 6 21 PATTY 48.6 20.0 82 528 +1971 12 4 0 1 ISAAC 20.9 218.0 147 28 +1979 5 1 18 13 ALBERTO 32.7 27.7 112 705 +1966 2 7 0 7 LESLIE 21.8 62.9 163 637 +1966 6 27 18 14 SANDY 11.2 233.9 90 120 +1961 5 16 18 23 TONY 24.6 193.2 22 407 +1985 8 1 0 24 GORDON 51.0 33.5 44 531 +1986 11 16 12 16 BERYL 44.5 86.0 24 93 +1988 6 4 18 1 ERNESTO 58.6 76.7 41 215 +1959 1 27 6 17 MICHAEL 15.4 47.4 126 794 +1985 7 17 0 17 MICHAEL 53.6 98.6 123 466 +1969 9 27 12 28 ISAAC 47.9 252.2 118 106 +1996 9 21 0 8 MICHAEL 21.4 101.6 125 359 +2001 4 14 12 5 ERNESTO 26.9 253.9 117 179 +1975 6 15 12 10 ERNESTO 29.9 288.2 155 253 +1970 11 14 6 10 NADINE 64.5 255.2 74 617 +1956 9 24 6 24 GORDON 64.9 309.6 106 830 +1987 4 18 12 1 SANDY 36.1 330.9 67 679 +1974 9 25 0 28 ISAAC 61.1 346.7 144 659 +1982 2 16 12 28 GORDON 52.6 331.8 159 345 +1990 5 8 18 18 LESLIE 18.7 83.1 63 446 +1950 3 7 12 5 TONY 55.0 89.1 157 765 +1960 12 17 0 26 NADINE 29.5 112.5 155 859 +2003 1 20 6 8 ERNESTO 13.3 244.3 95 82 +1965 1 12 18 14 OSCAR 66.5 178.5 38 547 +1950 2 14 6 26 DEBBY 11.1 142.7 77 699 +1986 2 13 18 8 BERYL 56.3 327.6 69 117 +1996 6 14 6 23 GORDON 30.0 217.6 139 889 +1950 12 14 6 21 JOYCE 15.9 333.1 10 154 +1966 2 24 18 19 SANDY 51.3 287.8 91 831 +1989 12 25 18 14 NADINE 29.4 86.1 122 22 +1975 6 23 18 10 ERNESTO 17.0 143.5 84 553 +1984 1 23 12 26 ERNESTO 47.9 163.0 28 602 +1952 9 10 6 14 WILLIAM 15.5 205.7 50 432 +1956 10 6 18 19 PATTY 55.7 355.2 35 79 +2002 11 25 6 24 VALERIE 66.0 154.5 150 605 +1996 4 10 12 10 WILLIAM 30.7 216.1 79 796 +1973 1 16 18 28 NADINE 68.8 292.8 118 789 +1965 8 8 12 5 OSCAR 53.3 357.9 127 652 +1962 5 11 18 25 HELENE 32.3 113.5 55 866 +1976 7 18 0 9 ERNESTO 39.2 206.3 72 477 +2004 12 13 18 21 RAFAEL 20.1 177.0 126 706 +1977 9 16 18 28 ERNESTO 65.7 192.0 129 735 +1950 8 22 0 17 FLORENCE 10.4 143.3 156 57 +1993 5 12 6 23 RAFAEL 59.4 84.9 27 763 +1951 5 14 6 11 NADINE 9.0 220.3 150 795 +1973 8 9 6 17 SANDY 69.1 65.7 75 583 +1957 10 7 12 1 WILLIAM 52.8 5.0 22 207 +1971 2 26 0 28 JOYCE 30.3 350.4 119 227 +1958 4 12 6 26 LESLIE 66.0 183.9 138 373 +1982 5 17 6 4 MICHAEL 63.3 22.8 24 473 +1987 6 25 0 5 RAFAEL 30.5 120.9 26 657 +1998 3 6 0 14 FLORENCE 52.5 313.9 81 734 +2001 7 8 6 21 FLORENCE 66.4 155.1 86 774 +1990 2 19 12 8 PATTY 19.5 66.2 117 611 +1983 8 1 18 26 KIRK 33.8 230.0 158 393 +1957 4 4 12 14 TONY 15.1 22.2 113 721 +1951 3 3 0 12 GORDON 39.4 139.0 99 536 +1966 4 13 12 4 TONY 36.5 338.3 124 229 +2002 10 9 6 9 NADINE 63.6 222.5 104 731 +1989 11 27 18 3 ALBERTO 42.4 267.9 70 714 +1964 1 7 0 27 CHRIS 65.3 263.9 90 17 +1981 5 8 6 18 RAFAEL 62.8 335.9 23 367 +1992 5 27 18 5 DEBBY 24.3 210.4 86 615 +1958 11 13 0 9 SANDY 24.1 101.5 58 428 +1983 7 27 0 2 VALERIE 53.5 247.7 158 487 +1992 10 13 12 6 ALBERTO 27.1 153.2 114 612 +1990 6 22 0 6 BERYL 41.8 83.6 135 731 +1963 12 5 6 6 HELENE 28.1 257.8 107 10 +1969 2 3 6 12 MICHAEL 47.7 65.9 38 837 +2000 5 26 12 27 FLORENCE 13.7 251.8 133 750 +1989 10 22 18 23 ERNESTO 9.5 179.8 162 226 +2003 6 14 12 28 MICHAEL 13.9 169.8 103 167 +1980 9 4 0 7 VALERIE 17.6 298.9 87 736 +1976 1 28 0 9 SANDY 35.4 345.3 23 373 +1979 8 6 6 21 SANDY 15.3 143.1 30 523 +1997 10 27 18 17 ISAAC 46.2 335.3 159 249 +1954 12 4 0 4 RAFAEL 66.0 65.2 53 839 +1973 11 27 0 23 TONY 20.5 73.1 46 754 +1977 2 20 18 9 LESLIE 62.7 15.0 135 143 +2004 8 24 18 3 ALBERTO 36.2 132.1 11 340 +1968 9 25 18 10 VALERIE 63.7 108.1 130 408 +1982 1 27 12 9 HELENE 20.4 318.1 45 702 +1974 11 20 12 24 GORDON 32.5 124.9 27 198 +1957 10 3 6 14 CHRIS 36.8 1.2 63 737 +1959 3 6 6 20 KIRK 39.0 75.3 76 707 +1969 6 5 0 25 ALBERTO 68.2 91.0 100 618 +1966 5 6 18 9 WILLIAM 8.4 133.9 121 836 +1954 4 4 18 7 JOYCE 23.5 202.2 86 346 +1958 10 5 18 23 NADINE 53.0 105.2 111 720 +1976 1 14 12 8 ISAAC 64.9 47.7 111 154 +1979 4 21 12 26 DEBBY 10.5 57.5 50 431 +1983 5 8 18 16 NADINE 23.9 23.6 11 202 +1969 10 13 0 8 ERNESTO 15.1 340.0 27 127 +2000 6 7 18 11 ALBERTO 55.7 107.4 11 0 +1988 12 25 18 5 LESLIE 16.1 63.2 132 340 +1989 1 8 6 28 BERYL 68.3 78.7 11 392 +1982 4 22 0 6 SANDY 37.6 115.2 132 81 +1955 6 27 6 15 GORDON 50.2 182.2 157 255 +1961 12 5 0 10 VALERIE 68.2 295.7 26 330 +1965 7 8 6 8 RAFAEL 10.9 264.2 103 278 +1950 8 25 6 5 ALBERTO 35.0 318.9 109 544 +1957 11 14 18 13 WILLIAM 62.6 0.1 88 59 +1993 12 4 18 5 MICHAEL 29.9 319.8 137 827 +1999 7 19 0 7 HELENE 52.5 117.6 22 191 +1951 1 3 0 5 BERYL 17.7 236.3 38 218 +1974 9 4 6 23 CHRIS 59.0 235.6 37 541 +1996 8 7 12 13 HELENE 56.6 58.2 51 786 +1994 4 11 6 7 BERYL 52.3 276.6 144 270 +1955 4 23 12 3 PATTY 12.0 79.4 59 773 +1967 6 2 6 26 CHRIS 15.8 121.1 115 627 +1978 9 8 12 3 KIRK 37.7 64.3 11 78 +1955 12 21 6 21 RAFAEL 18.7 255.9 48 867 +1970 1 8 18 10 BERYL 38.2 179.2 155 252 +1971 12 14 18 3 MICHAEL 15.5 128.5 50 856 +1970 12 13 18 12 DEBBY 48.3 248.8 100 294 +1996 11 2 0 25 HELENE 22.2 224.3 81 660 +1986 9 24 18 3 KIRK 50.8 312.6 14 261 +1990 3 4 0 21 PATTY 62.1 0.2 145 486 +1956 9 2 12 15 LESLIE 32.0 80.2 63 886 +1999 5 16 12 20 SANDY 38.7 105.7 106 78 +1983 7 22 0 27 RAFAEL 55.3 252.7 65 544 +1976 3 15 18 13 WILLIAM 26.4 214.4 145 658 +2000 8 14 6 19 GORDON 49.8 158.3 134 522 +1953 4 1 0 20 MICHAEL 51.4 29.5 53 567 +1985 3 8 18 24 JOYCE 59.3 63.7 43 875 +1981 3 13 0 28 MICHAEL 25.9 80.8 75 783 +1966 6 14 18 25 SANDY 13.1 311.8 71 708 +1984 7 23 6 10 HELENE 17.3 120.3 152 655 +1983 6 5 12 9 JOYCE 24.1 321.4 89 415 +1958 6 13 18 4 RAFAEL 33.5 302.3 102 667 +2004 10 26 0 19 GORDON 54.4 322.9 122 448 +1970 10 22 0 25 KIRK 45.6 328.8 124 405 +1973 5 21 12 27 SANDY 15.1 4.8 100 40 +1990 10 14 12 2 GORDON 9.9 282.0 49 469 +1988 3 17 12 11 WILLIAM 32.7 218.5 71 432 +1981 11 18 6 2 MICHAEL 39.7 170.8 55 641 +1977 1 28 0 8 WILLIAM 26.7 203.3 143 407 +1953 1 10 6 12 NADINE 25.7 212.3 34 401 +1964 7 2 6 6 ALBERTO 50.8 348.9 157 818 +1960 3 18 6 4 KIRK 40.5 83.7 152 143 +1994 9 3 18 20 ERNESTO 61.8 131.7 39 14 +1966 9 8 12 23 PATTY 58.0 155.9 70 33 +1976 10 8 0 11 NADINE 27.2 3.4 60 258 +1993 10 28 6 27 MICHAEL 7.6 317.4 162 620 +1995 10 20 18 20 CHRIS 26.5 100.0 70 31 +1950 5 5 12 11 MICHAEL 25.2 258.9 18 608 +1964 11 8 12 26 SANDY 9.5 209.3 21 377 +1978 4 26 6 8 SANDY 21.8 31.8 36 413 +1967 10 16 0 6 ISAAC 57.0 252.7 89 81 +1952 8 25 6 14 PATTY 43.2 124.9 49 833 +1966 9 4 6 26 BERYL 12.1 280.0 71 546 +1993 4 18 18 8 SANDY 14.0 349.1 88 574 +1969 6 1 12 18 GORDON 24.9 220.8 51 165 +1965 3 13 18 4 RAFAEL 22.2 168.8 141 525 +1996 3 9 12 9 NADINE 25.4 299.4 95 342 +1951 11 2 6 14 JOYCE 21.3 201.1 118 266 +1978 8 21 18 7 HELENE 13.5 250.5 134 544 +1985 6 13 6 11 OSCAR 23.0 228.3 72 179 +1953 3 19 0 21 GORDON 62.0 315.4 157 745 +1961 2 5 0 19 PATTY 8.8 355.1 27 815 +1972 5 15 12 13 ISAAC 8.4 156.3 164 24 +1988 2 18 12 12 ERNESTO 19.0 325.6 163 614 +2000 12 2 12 21 NADINE 48.6 133.3 12 102 +1961 4 1 18 3 KIRK 38.1 287.7 25 127 +1971 12 23 12 8 RAFAEL 9.0 101.7 47 37 +1961 12 22 0 20 HELENE 53.4 10.8 57 828 +1956 1 2 0 2 NADINE 45.8 300.7 16 724 +1979 4 1 6 10 KIRK 54.9 281.6 129 709 +1975 12 8 12 14 FLORENCE 34.2 62.7 123 66 +1965 11 3 12 21 HELENE 28.0 287.3 89 430 +1986 2 15 6 6 TONY 46.3 107.7 20 675 +2002 12 22 12 28 FLORENCE 20.0 169.2 67 743 +1985 10 1 6 16 RAFAEL 8.0 75.3 123 408 +1957 12 19 6 25 NADINE 65.1 145.9 114 116 +1975 1 26 6 11 ALBERTO 24.9 283.3 146 636 +1994 3 8 6 8 GORDON 63.3 241.9 144 731 +1977 1 22 18 10 OSCAR 41.5 307.0 159 4 +1965 10 3 18 2 GORDON 48.2 166.7 23 40 +2004 8 28 12 28 NADINE 21.3 297.2 139 40 +1970 1 25 12 10 ISAAC 30.0 69.5 108 183 +1985 2 12 18 17 PATTY 48.8 270.1 102 867 +1974 3 10 0 18 JOYCE 39.2 217.5 113 26 +1963 11 6 12 23 RAFAEL 68.3 7.3 71 647 +2000 4 11 6 10 HELENE 44.4 241.0 114 767 +1992 11 10 0 28 DEBBY 11.1 87.0 121 406 +1982 5 20 12 1 VALERIE 43.1 196.8 101 399 +1987 4 18 6 9 NADINE 54.4 3.1 87 524 +1970 8 13 18 20 MICHAEL 38.6 327.9 80 479 +2002 2 26 6 22 OSCAR 54.8 130.8 93 783 +1982 4 23 12 14 OSCAR 32.0 17.5 53 844 +2003 3 3 6 12 JOYCE 31.3 140.0 138 879 +1962 5 5 18 15 CHRIS 61.4 101.4 42 250 +1953 8 13 6 27 KIRK 24.7 67.8 26 34 +1971 10 26 18 12 ISAAC 13.2 127.0 139 255 +1998 3 27 12 12 JOYCE 56.4 245.7 74 155 +1970 10 24 6 17 WILLIAM 11.7 216.6 22 673 +1967 5 2 18 16 ISAAC 8.3 216.1 132 301 +1981 7 25 0 16 SANDY 50.3 295.0 35 417 +1964 6 3 12 6 MICHAEL 9.3 271.2 146 546 +1975 5 7 18 18 PATTY 17.7 351.9 11 482 +1994 5 23 0 17 FLORENCE 23.0 183.9 10 466 +1970 2 14 18 14 BERYL 58.1 330.8 152 105 +1974 10 22 18 26 BERYL 18.6 340.2 103 314 +1995 4 11 6 28 WILLIAM 48.2 47.5 129 534 +1955 4 8 0 24 BERYL 67.6 333.2 161 138 +2002 10 1 12 6 PATTY 25.8 251.5 85 677 +1957 6 9 18 23 KIRK 12.8 348.0 134 685 +1973 2 2 6 28 LESLIE 30.4 189.1 103 294 +1980 10 24 18 16 CHRIS 26.2 259.6 59 609 +1962 2 9 0 3 SANDY 40.4 77.9 116 500 +1962 1 21 0 9 HELENE 23.1 347.3 132 722 +1957 11 17 12 19 CHRIS 32.6 224.1 151 700 +1981 3 27 6 1 TONY 44.9 254.1 55 222 +1973 2 17 12 4 GORDON 65.5 236.8 106 178 +1994 10 12 18 10 JOYCE 53.0 166.4 88 542 +1975 10 18 18 4 FLORENCE 51.6 4.6 99 151 +1963 3 11 0 16 VALERIE 9.3 332.9 141 809 +1974 1 28 6 7 ERNESTO 42.6 218.8 160 156 +2004 12 12 0 14 BERYL 45.0 279.8 62 278 +1962 4 16 6 10 RAFAEL 61.8 190.9 136 654 +1986 9 21 6 22 ALBERTO 42.2 66.0 57 662 +1968 10 4 0 4 SANDY 19.0 164.0 85 153 +1964 5 10 12 7 ALBERTO 53.6 304.1 50 371 +1953 3 25 18 3 OSCAR 51.5 261.1 25 215 +1954 7 16 0 21 TONY 11.5 61.5 146 895 +2000 9 7 12 17 OSCAR 18.4 114.2 155 323 +1978 5 27 0 25 BERYL 46.4 74.9 83 344 +1966 7 27 0 1 RAFAEL 28.5 282.8 114 282 +1999 1 18 0 20 WILLIAM 42.3 198.5 144 596 +1995 7 14 0 14 SANDY 20.3 300.6 43 560 +1999 5 9 12 7 LESLIE 41.5 85.7 63 862 +1986 7 23 12 9 SANDY 11.1 97.0 16 245 +1962 9 10 18 15 KIRK 14.6 97.5 146 321 +1984 1 24 12 3 SANDY 26.6 161.1 132 587 +1970 2 20 0 14 ERNESTO 32.1 23.8 135 793 +2003 3 8 0 19 HELENE 58.1 233.0 30 166 +1990 5 4 6 12 ALBERTO 39.3 28.0 113 823 +1996 3 24 18 18 ALBERTO 14.6 107.9 75 765 +1970 5 15 0 6 KIRK 55.1 296.2 144 406 +1991 10 3 6 3 RAFAEL 10.3 52.9 23 777 +1991 7 21 6 20 TONY 51.8 331.9 50 504 +1974 6 12 6 16 JOYCE 25.0 213.7 147 95 +1996 9 2 0 1 PATTY 28.5 157.7 105 748 +2000 2 4 0 7 TONY 15.5 56.3 119 51 +1954 11 26 12 5 FLORENCE 10.3 221.5 15 605 +1953 11 8 18 21 DEBBY 58.9 162.5 30 422 +1964 4 9 12 4 DEBBY 29.4 126.0 108 173 +2001 8 2 18 7 ERNESTO 22.6 120.9 48 825 +1967 5 7 18 24 MICHAEL 68.9 313.8 59 63 +1952 9 8 12 7 MICHAEL 49.1 268.0 93 15 +1968 2 8 18 15 ERNESTO 19.0 71.9 32 199 +1980 2 1 18 16 PATTY 59.6 178.1 59 259 +1990 2 21 12 23 RAFAEL 35.9 132.8 131 756 +1975 6 10 0 21 HELENE 14.9 224.5 34 681 +1966 1 10 0 22 LESLIE 21.4 207.4 80 321 +1987 4 15 6 1 VALERIE 61.6 30.3 110 844 +1965 9 4 12 28 ALBERTO 63.0 28.1 54 152 +1974 3 8 12 18 PATTY 67.6 199.0 159 753 +1977 4 7 6 27 ERNESTO 65.9 211.4 56 135 +1986 8 15 6 8 LESLIE 13.6 31.1 124 132 +1996 10 5 18 8 OSCAR 27.0 249.0 87 508 +1965 5 2 12 6 ISAAC 18.4 40.2 38 231 +1969 8 23 18 21 JOYCE 60.5 254.1 51 279 +1989 12 21 0 15 KIRK 16.9 23.5 156 544 +1973 2 1 18 10 SANDY 25.4 184.3 102 0 +1964 9 4 18 25 KIRK 44.2 246.2 43 706 +1972 9 9 6 3 WILLIAM 49.8 99.7 106 574 +1966 11 25 18 8 HELENE 65.7 271.1 83 670 +1971 2 6 0 9 JOYCE 49.2 60.9 111 78 +1984 3 20 0 4 WILLIAM 45.6 170.5 66 633 +1999 11 28 6 10 GORDON 8.2 115.0 11 815 +1981 8 11 6 15 OSCAR 40.0 52.7 148 164 +1991 12 7 0 2 KIRK 53.1 94.3 62 687 +1998 10 9 6 26 KIRK 37.5 343.5 119 3 +1959 11 8 6 26 PATTY 36.3 255.9 22 344 +1950 6 14 12 23 VALERIE 26.5 160.8 72 813 +2001 3 24 6 1 HELENE 61.0 73.7 97 368 +1998 3 5 12 7 ISAAC 15.1 347.2 57 620 +1971 7 14 0 26 GORDON 26.0 195.2 153 609 +1989 3 10 12 6 ALBERTO 28.6 353.9 44 631 +1973 7 18 0 28 KIRK 63.6 152.5 162 701 +1996 2 3 6 15 WILLIAM 61.3 326.2 138 748 +1993 6 2 0 25 ALBERTO 69.8 255.4 156 326 +1982 11 26 18 20 PATTY 51.5 113.0 78 304 +1968 3 2 12 3 PATTY 55.2 294.3 118 810 +1964 1 17 18 2 JOYCE 43.1 83.3 14 269 +1982 5 5 0 13 ISAAC 34.9 343.5 68 85 +1992 10 11 6 17 KIRK 24.1 202.8 15 363 +1994 1 20 0 23 NADINE 55.6 133.7 89 143 +1962 3 24 12 26 CHRIS 7.1 163.9 134 247 +1958 5 21 12 16 DEBBY 65.1 252.5 116 726 +2004 12 8 0 21 JOYCE 8.7 291.3 130 796 +1952 1 5 0 27 NADINE 14.6 209.9 37 497 +1951 3 24 18 25 DEBBY 61.5 34.7 65 796 +1999 1 4 6 12 GORDON 40.2 287.4 115 167 +1991 4 22 6 4 CHRIS 39.4 174.4 18 336 +1991 3 21 12 28 RAFAEL 64.3 351.9 77 664 +1993 10 1 0 20 MICHAEL 56.2 97.5 117 550 +1953 12 21 6 26 VALERIE 48.2 336.2 48 203 +1959 2 22 0 16 JOYCE 18.6 349.2 38 524 +1951 10 17 18 22 ERNESTO 43.6 296.5 68 453 +1990 3 14 0 21 JOYCE 27.3 128.7 141 539 +1974 4 27 6 24 HELENE 64.1 290.7 39 887 +2003 9 15 18 4 VALERIE 54.8 189.3 102 469 +1953 3 17 6 28 KIRK 34.9 28.9 142 401 +2003 12 25 6 2 GORDON 15.2 353.5 154 86 +1999 5 18 18 27 ALBERTO 35.4 30.8 144 221 +1961 2 10 6 16 WILLIAM 59.3 193.8 122 726 +1963 5 19 18 12 JOYCE 61.2 40.3 81 800 +1972 1 25 6 21 RAFAEL 29.9 167.9 48 741 +1985 11 16 12 1 WILLIAM 49.7 175.8 123 398 +1986 6 16 12 1 ALBERTO 41.5 125.5 55 451 +2004 3 23 0 14 DEBBY 43.6 207.0 94 188 +1975 3 13 18 9 SANDY 16.2 132.4 107 826 +1964 10 5 12 28 FLORENCE 41.2 112.6 31 555 +1984 1 27 6 2 WILLIAM 25.9 276.2 136 882 +2002 10 12 0 18 MICHAEL 9.4 194.6 124 246 +1962 4 5 0 7 MICHAEL 27.7 170.1 60 701 +1956 2 8 0 4 MICHAEL 16.7 235.8 18 110 +1953 12 20 12 2 MICHAEL 60.6 341.9 32 331 +2002 1 16 0 12 ISAAC 28.3 171.6 134 592 +1993 2 6 6 24 ALBERTO 62.5 329.6 148 814 +1994 1 27 6 2 NADINE 22.6 184.0 121 590 +1964 7 21 0 16 JOYCE 58.9 209.4 145 834 +2003 12 17 0 19 ALBERTO 20.7 197.3 54 410 +1980 4 8 18 12 ERNESTO 38.7 350.0 48 566 +1972 7 10 18 12 CHRIS 47.9 274.3 164 790 +1986 5 21 0 6 ISAAC 36.8 225.0 99 642 +1952 4 17 6 26 WILLIAM 10.1 259.0 94 387 +1966 2 22 12 15 ISAAC 57.4 297.1 19 617 +1951 8 15 18 2 BERYL 43.7 356.7 154 591 +1955 10 5 18 2 NADINE 31.3 351.1 126 228 +1997 10 26 12 23 GORDON 16.9 23.1 38 875 +1982 1 28 18 10 ALBERTO 26.0 345.9 160 347 +1955 12 23 6 3 CHRIS 59.3 272.9 148 679 +1956 3 19 12 20 ALBERTO 40.4 92.5 127 546 +1981 8 8 12 3 JOYCE 33.1 4.5 100 533 +1958 10 15 12 13 DEBBY 27.0 31.9 33 618 +1969 4 8 0 16 LESLIE 55.0 258.5 44 576 +2004 4 8 18 3 DEBBY 52.4 292.7 164 624 +1996 1 14 12 12 RAFAEL 14.3 175.2 124 2 +1996 7 23 6 9 KIRK 63.7 143.0 126 241 +1994 10 22 0 4 NADINE 68.8 177.0 13 459 +2004 3 8 0 19 TONY 48.9 95.2 135 61 +1955 9 11 6 25 JOYCE 24.2 206.5 88 811 +1997 9 23 0 19 PATTY 7.9 176.0 103 101 +1969 6 15 18 23 FLORENCE 16.3 113.7 71 305 +1999 4 22 12 24 DEBBY 50.9 92.9 30 484 +1987 12 24 12 26 OSCAR 12.8 297.9 134 702 +1982 3 19 0 22 GORDON 7.8 116.8 106 386 +2003 12 18 12 4 ERNESTO 28.9 8.0 111 269 +1964 10 9 18 28 RAFAEL 50.3 193.9 24 622 +1992 4 3 0 11 ALBERTO 53.4 274.9 133 153 +2000 1 21 6 6 DEBBY 12.6 73.1 137 462 +1961 10 25 12 25 ALBERTO 42.1 333.5 145 536 +1983 6 20 6 22 CHRIS 65.0 116.7 111 878 +1951 2 28 0 5 RAFAEL 51.0 240.0 114 136 +2004 2 19 6 25 JOYCE 31.8 75.6 82 206 +1978 11 17 6 2 SANDY 25.2 9.8 91 429 +1995 1 16 6 3 JOYCE 55.3 251.3 48 70 +1964 10 26 6 11 OSCAR 66.6 89.5 162 645 +1958 1 20 6 3 VALERIE 29.9 18.2 137 225 +1987 4 28 18 7 TONY 38.8 77.8 157 463 +1964 9 27 18 5 DEBBY 29.4 148.1 132 45 +1956 5 10 0 27 JOYCE 15.8 281.4 39 232 +1965 6 19 6 24 OSCAR 23.2 328.7 83 275 +1990 7 12 18 10 MICHAEL 35.4 15.1 95 631 +1977 9 24 6 17 HELENE 39.7 153.1 123 831 +1993 10 19 0 20 PATTY 23.3 348.4 107 331 +1962 4 15 6 13 HELENE 15.0 331.0 144 778 +1957 2 11 6 2 RAFAEL 15.8 329.8 60 5 +2004 12 10 0 3 CHRIS 47.6 103.5 109 251 +1994 4 11 6 19 PATTY 56.5 286.8 70 817 +1973 1 25 18 19 SANDY 21.0 351.1 76 589 +1997 5 4 0 11 ALBERTO 9.9 139.6 147 375 +1963 6 11 6 8 CHRIS 49.8 135.3 137 626 +2004 12 27 12 9 WILLIAM 36.8 109.2 85 857 +1958 1 3 6 7 ISAAC 47.5 242.6 93 289 +1981 11 23 6 18 LESLIE 35.6 11.4 14 137 +1962 6 20 18 20 HELENE 14.3 7.7 145 587 +1992 1 18 12 7 TONY 15.1 293.5 17 728 +1950 1 25 0 6 SANDY 68.7 45.5 95 454 +1990 11 6 12 26 RAFAEL 25.1 239.1 153 255 +1989 4 8 18 14 RAFAEL 52.0 72.1 129 766 +1967 8 1 0 5 JOYCE 47.9 299.4 32 864 +1969 3 14 6 2 HELENE 10.3 119.0 119 526 +1963 4 12 6 7 CHRIS 18.4 47.0 127 896 +1977 10 11 0 25 BERYL 48.5 69.8 57 766 +1998 10 24 18 26 BERYL 10.2 328.7 75 32 +1982 3 12 6 26 BERYL 60.5 303.3 35 243 +1959 7 4 0 17 LESLIE 52.9 30.0 82 11 +1972 5 10 12 25 VALERIE 49.2 240.1 160 99 +1983 1 5 12 5 DEBBY 39.1 108.6 54 320 +2000 6 20 6 19 SANDY 69.8 218.0 35 418 +1991 11 8 18 28 WILLIAM 7.3 186.6 61 742 +1965 2 18 6 10 PATTY 43.4 257.9 17 335 +2000 4 2 18 1 HELENE 7.5 55.9 98 898 +1952 1 9 0 24 PATTY 66.8 209.2 44 618 +1970 11 24 0 3 DEBBY 27.0 160.1 114 53 +1998 4 4 0 21 WILLIAM 63.3 302.0 164 519 +1956 6 24 18 10 ISAAC 43.5 161.0 158 12 +1957 1 1 12 2 HELENE 12.8 256.9 23 146 +1952 2 25 18 25 TONY 32.5 187.9 84 650 +1980 8 15 6 21 ALBERTO 8.8 168.3 127 429 +1987 9 16 12 3 CHRIS 19.9 228.6 103 48 +1951 9 7 6 23 JOYCE 67.2 94.1 104 888 +1994 2 7 6 20 SANDY 43.6 58.9 150 761 +2004 7 7 0 28 GORDON 52.3 237.0 115 166 +1957 10 16 18 16 NADINE 46.0 241.5 13 262 +1998 1 23 12 7 JOYCE 48.8 4.9 57 394 +1985 1 7 6 24 WILLIAM 55.2 28.6 121 515 +1963 6 9 0 24 HELENE 49.8 88.2 97 533 +1960 6 5 18 24 PATTY 55.9 99.5 94 230 +1970 9 14 18 12 JOYCE 32.5 238.9 50 491 +1960 4 27 18 1 LESLIE 69.5 261.9 67 844 +1993 11 13 18 23 VALERIE 53.5 181.0 15 677 +1961 4 6 12 27 OSCAR 39.1 69.6 131 774 +1981 8 24 6 5 RAFAEL 62.9 23.6 24 777 +1961 2 23 12 21 WILLIAM 24.2 44.9 77 264 +1989 4 17 6 8 SANDY 30.9 347.0 37 610 +1991 4 27 12 6 OSCAR 44.4 291.6 134 212 +1996 4 11 6 14 TONY 20.1 306.6 36 42 +1958 9 19 18 4 LESLIE 13.9 242.4 74 555 +2000 8 21 12 25 KIRK 30.6 349.3 68 448 +1991 4 2 12 18 ISAAC 63.3 355.7 147 538 +1990 4 17 0 25 TONY 69.0 331.1 88 39 +2003 7 23 0 4 ISAAC 15.3 192.4 76 403 +1993 3 10 18 21 CHRIS 49.6 158.1 65 582 +1957 8 10 0 24 GORDON 38.9 350.8 87 823 +1982 1 3 18 11 DEBBY 40.9 218.0 92 166 +1984 11 17 12 8 TONY 11.2 96.2 130 638 +2004 4 3 18 9 ISAAC 45.8 140.0 40 312 +1955 9 19 6 1 LESLIE 24.6 300.0 39 552 +1959 11 17 6 1 VALERIE 34.4 146.0 36 440 +1989 1 10 12 5 WILLIAM 8.1 98.7 18 255 +1990 8 16 12 28 WILLIAM 44.2 207.4 158 491 +1956 12 27 18 1 DEBBY 68.8 246.0 76 44 +1989 5 21 6 26 MICHAEL 53.4 96.9 90 15 +1998 7 2 0 26 ALBERTO 40.9 249.5 60 688 +1977 4 21 18 16 ALBERTO 8.2 302.1 152 168 +2004 1 3 0 21 WILLIAM 16.6 123.0 120 342 +1985 1 24 0 15 OSCAR 27.1 72.8 49 569 +1981 12 1 0 27 HELENE 57.4 328.6 25 416 +1987 2 14 6 10 VALERIE 9.5 165.2 128 771 +1964 7 25 18 15 ISAAC 47.0 294.6 121 53 +1951 6 20 6 24 FLORENCE 66.4 207.4 10 365 +1974 5 12 6 19 ALBERTO 44.8 47.3 51 153 +1960 3 2 18 8 FLORENCE 28.0 50.7 48 438 +1986 7 23 6 13 DEBBY 62.4 81.1 115 405 +1967 8 5 6 21 ERNESTO 15.4 40.4 68 563 +1998 8 20 18 24 WILLIAM 48.3 201.3 126 678 +1978 8 11 6 13 ERNESTO 51.7 147.5 30 731 +1957 6 21 0 5 RAFAEL 40.1 251.7 143 786 +2002 10 15 0 5 NADINE 28.0 197.2 101 656 +1977 2 7 0 24 VALERIE 23.0 313.7 96 404 +1969 4 2 12 11 BERYL 10.0 308.8 54 586 +1957 12 25 12 28 GORDON 14.7 304.7 142 895 +1974 2 15 12 22 JOYCE 45.8 179.0 28 787 +1965 4 13 12 7 VALERIE 59.0 30.3 90 604 +1963 3 21 18 12 ALBERTO 54.2 270.7 108 119 +1951 4 21 18 16 RAFAEL 10.6 86.9 137 145 +1957 3 15 6 20 ERNESTO 7.9 27.9 28 264 +1983 9 4 6 18 FLORENCE 65.9 175.1 39 454 +1974 1 15 12 24 LESLIE 30.3 98.1 34 837 +1991 3 25 6 28 TONY 24.1 262.6 80 851 +1990 2 7 0 15 VALERIE 67.8 85.4 22 560 +1966 1 17 18 19 GORDON 13.0 241.7 41 27 +1968 7 2 6 12 HELENE 17.0 124.9 44 428 +1982 8 23 6 1 TONY 49.4 87.0 17 221 +1998 3 24 18 28 PATTY 25.5 225.8 30 592 +1975 1 1 18 21 RAFAEL 69.6 240.7 154 617 +1992 7 27 0 1 OSCAR 37.2 311.3 89 460 +1990 2 7 12 5 ERNESTO 32.8 60.9 95 614 +1989 2 3 0 20 DEBBY 60.4 296.5 94 858 +1959 8 15 6 17 LESLIE 23.5 274.4 102 647 +1963 2 1 0 17 PATTY 32.5 162.7 68 690 +1975 11 28 18 27 ALBERTO 9.0 346.0 76 827 +1953 5 17 0 9 MICHAEL 63.4 57.5 21 367 +1950 2 12 18 28 GORDON 20.5 134.6 118 52 +1959 9 14 0 9 ALBERTO 30.9 30.0 75 40 +1990 2 11 12 25 CHRIS 69.3 62.5 92 793 +1971 3 2 18 16 ISAAC 34.9 144.1 110 437 +1982 5 16 0 21 TONY 39.9 186.3 89 114 +1957 11 13 6 28 PATTY 69.7 245.4 163 810 +1957 3 27 18 16 PATTY 58.0 47.2 94 828 +1995 1 28 12 4 ERNESTO 51.2 188.5 42 50 +1950 10 7 6 17 MICHAEL 50.5 276.2 92 319 +1966 12 12 6 27 RAFAEL 24.6 59.3 132 786 +2002 7 5 12 28 ERNESTO 11.5 132.9 142 804 +1977 4 8 6 10 LESLIE 28.3 327.2 92 423 +1985 6 19 12 2 TONY 65.5 42.1 42 718 +1952 1 16 6 12 ISAAC 66.3 123.9 25 827 +1956 11 7 0 15 JOYCE 62.0 101.1 57 208 +1987 6 18 6 23 CHRIS 29.8 92.1 22 147 +1954 12 20 12 25 ERNESTO 60.1 228.0 49 782 +1969 9 4 0 20 ALBERTO 54.0 50.2 105 715 +1964 2 15 12 13 DEBBY 68.7 104.3 145 651 +1957 6 8 12 25 WILLIAM 42.6 30.5 27 191 +1964 4 13 18 9 JOYCE 47.5 28.0 47 296 +1981 12 22 18 17 VALERIE 15.3 110.9 40 130 +1995 10 5 0 21 PATTY 45.1 336.4 125 886 +1953 6 14 18 23 JOYCE 10.0 263.4 156 561 +1952 9 17 0 26 MICHAEL 66.7 221.0 113 687 +1970 2 19 0 26 DEBBY 33.8 89.8 132 49 +1966 9 17 18 18 GORDON 59.1 26.7 94 295 +1988 12 10 6 8 BERYL 69.0 162.9 102 826 +1953 6 3 18 6 PATTY 40.1 196.9 110 748 +1975 7 9 12 20 NADINE 42.0 64.5 63 643 +2001 4 25 12 2 PATTY 69.6 181.9 148 76 +1992 6 24 18 3 LESLIE 44.5 34.2 27 3 +1971 2 18 0 16 NADINE 27.6 155.1 130 673 +1970 4 11 6 26 MICHAEL 19.3 160.7 85 386 +1957 2 16 18 2 TONY 11.0 312.1 43 503 +1982 1 17 0 16 PATTY 49.7 16.8 127 748 +1976 2 15 12 3 JOYCE 64.0 218.3 94 823 +1994 4 9 18 8 VALERIE 23.4 79.5 121 32 +1958 9 3 6 13 GORDON 37.9 252.8 62 848 +2003 10 15 12 18 KIRK 49.3 112.0 131 204 +1986 7 21 18 26 RAFAEL 60.6 16.1 82 820 +2000 10 7 0 22 OSCAR 64.5 73.8 153 154 +2000 5 12 18 2 ERNESTO 30.5 282.7 78 873 +1975 10 22 18 12 ERNESTO 38.2 343.5 157 112 +1977 12 6 12 11 HELENE 53.3 330.4 131 633 +1977 11 5 12 22 TONY 13.9 127.9 13 442 +1988 3 17 6 25 FLORENCE 54.9 249.3 106 119 +1984 12 23 12 24 MICHAEL 46.5 249.3 121 232 +1975 8 18 6 13 RAFAEL 36.0 71.3 123 51 +1959 3 21 12 25 WILLIAM 14.1 154.0 147 353 +1998 2 15 0 25 BERYL 23.7 299.5 159 70 +1981 7 26 6 19 DEBBY 43.6 285.5 80 256 +1969 12 4 6 28 LESLIE 58.4 143.1 41 318 +1992 6 13 6 19 WILLIAM 34.7 221.2 69 499 +1992 2 4 6 26 CHRIS 13.3 332.5 100 172 +1992 2 21 12 3 HELENE 32.1 236.9 103 576 +1988 11 10 0 3 FLORENCE 23.7 232.3 145 409 +1955 6 15 0 26 ALBERTO 11.9 3.3 93 35 +1981 1 26 0 1 WILLIAM 35.0 66.1 16 84 +1956 8 13 0 27 KIRK 60.5 22.5 159 819 +1982 4 22 0 21 ISAAC 23.0 259.2 61 541 +1993 8 9 0 21 ERNESTO 63.0 45.6 57 442 +1954 3 21 18 14 WILLIAM 25.1 257.5 146 635 +1990 10 11 18 16 DEBBY 55.2 333.4 43 8 +1972 7 13 6 12 FLORENCE 35.0 345.1 27 300 +1985 12 26 12 17 BERYL 32.9 302.5 164 307 +1995 7 9 18 9 DEBBY 22.7 10.6 47 100 +1968 10 26 0 6 GORDON 9.2 119.3 81 505 +1984 12 16 6 12 TONY 18.3 247.5 63 755 +1997 11 17 0 3 SANDY 40.6 238.8 164 249 +1974 12 26 18 10 VALERIE 65.6 313.3 63 390 +1997 6 18 18 3 VALERIE 34.9 231.9 28 115 +1980 3 27 12 4 CHRIS 41.6 95.6 149 106 +1989 10 10 18 2 WILLIAM 32.9 18.6 107 848 +2004 7 27 18 9 ISAAC 65.9 262.4 32 561 +1971 4 28 0 1 MICHAEL 20.3 159.4 143 598 +1992 3 28 12 13 JOYCE 9.9 19.1 20 646 +2000 2 9 0 27 VALERIE 14.0 7.4 60 420 +1977 1 26 12 24 KIRK 68.6 187.8 106 644 +1956 2 3 6 20 OSCAR 27.4 175.5 17 280 +1995 4 14 18 1 GORDON 30.0 93.9 116 686 +1968 10 7 6 18 TONY 38.4 164.4 118 217 +1963 11 27 6 27 RAFAEL 57.6 341.7 80 356 +1970 12 10 6 24 VALERIE 17.0 276.1 99 20 +1952 4 10 6 3 LESLIE 49.9 115.6 61 249 +1964 2 19 6 17 VALERIE 34.6 296.5 79 830 +1980 4 20 12 10 GORDON 52.1 314.8 114 662 +1970 1 6 18 7 HELENE 15.8 78.4 38 383 +1981 6 10 0 21 JOYCE 8.0 152.4 107 293 +1992 2 18 12 22 KIRK 56.7 153.4 126 457 +1965 6 25 6 21 CHRIS 38.3 172.1 104 98 +1974 2 11 18 16 KIRK 12.9 326.3 45 631 +1967 10 21 12 12 FLORENCE 59.9 355.2 36 447 +1950 9 15 18 11 ERNESTO 34.6 329.0 161 33 +1951 5 8 18 26 SANDY 66.4 40.9 118 547 +1992 11 26 18 23 BERYL 60.7 302.4 152 670 +1951 6 4 0 14 KIRK 48.4 329.5 154 164 +1974 2 2 0 17 ISAAC 48.5 326.5 102 897 +1966 12 9 6 21 BERYL 37.9 74.1 53 426 +1996 9 14 12 18 KIRK 45.3 264.9 77 672 +1955 9 26 12 25 RAFAEL 43.8 108.7 149 512 +1971 6 11 18 5 GORDON 19.2 245.5 98 642 +1984 4 1 12 24 ISAAC 37.1 264.5 53 346 +1971 4 24 6 8 ALBERTO 34.7 251.0 123 391 +1973 12 19 0 26 HELENE 44.4 197.4 138 822 +1980 10 25 12 2 TONY 21.4 212.5 47 343 +1977 5 14 6 20 FLORENCE 13.1 188.3 129 767 +2004 3 8 6 2 LESLIE 28.8 168.1 14 683 +1955 2 18 6 6 CHRIS 51.6 207.0 20 759 +2001 6 10 18 5 SANDY 11.0 284.7 143 443 +1988 4 10 6 24 HELENE 30.9 188.0 84 139 +2001 12 28 6 14 GORDON 11.0 180.7 51 188 +1957 2 4 0 16 KIRK 58.9 314.0 105 410 +2003 4 27 0 5 FLORENCE 59.4 135.7 32 837 +1962 7 13 12 1 JOYCE 38.4 10.6 103 627 +1999 11 27 18 24 NADINE 67.4 249.8 105 677 +1998 2 28 0 16 TONY 41.3 42.5 148 620 +1961 8 3 18 18 HELENE 44.5 277.3 74 146 +1964 12 21 18 20 ISAAC 23.2 234.9 65 586 +1987 1 16 6 10 JOYCE 69.6 246.9 27 199 +1984 4 18 18 21 PATTY 40.1 158.1 114 37 +1988 8 9 6 16 HELENE 25.1 38.7 156 506 +2003 1 28 6 28 SANDY 46.2 121.1 135 79 +1951 9 7 18 10 JOYCE 23.6 208.6 96 264 +1985 6 10 6 25 JOYCE 45.2 137.2 136 687 +1979 9 3 0 11 LESLIE 23.3 167.4 139 762 +1969 3 12 0 4 GORDON 36.1 356.2 39 815 +1985 12 11 0 18 DEBBY 7.5 0.7 93 501 +1997 8 1 18 23 MICHAEL 13.6 341.4 136 80 +1974 6 25 0 7 MICHAEL 61.8 264.2 44 541 +1969 3 25 12 16 BERYL 42.4 127.6 108 601 +1989 12 12 0 1 ISAAC 64.1 2.3 130 624 +1960 7 16 6 17 RAFAEL 16.2 152.2 72 224 +1970 9 3 12 5 ALBERTO 14.1 49.9 130 827 +1978 8 19 6 20 DEBBY 29.0 189.2 15 643 +1998 1 28 0 16 RAFAEL 25.3 303.5 64 213 +1988 9 4 6 8 MICHAEL 53.6 315.0 150 352 +1952 3 22 18 1 BERYL 13.0 252.0 150 181 +1991 6 28 18 4 HELENE 56.0 230.4 101 264 +1987 12 12 12 22 GORDON 66.8 304.4 146 354 +1965 11 15 6 5 BERYL 48.1 175.2 153 383 +1994 6 21 12 25 KIRK 55.3 314.5 163 451 +1998 4 21 18 28 CHRIS 46.3 301.5 133 527 +1979 10 26 6 20 BERYL 21.2 113.9 21 811 +1989 11 6 6 1 DEBBY 57.7 135.1 18 837 +1968 6 28 6 1 PATTY 33.8 1.5 71 695 +1977 3 21 12 28 HELENE 60.6 171.9 162 759 +1950 6 25 12 3 TONY 21.7 269.0 126 521 +1970 2 23 0 11 BERYL 63.1 349.8 155 534 +1995 6 22 18 17 DEBBY 43.1 342.8 48 272 +1992 4 22 18 14 OSCAR 48.4 198.1 106 574 +1981 6 21 18 9 ERNESTO 35.6 114.4 72 132 +1993 6 10 6 8 GORDON 21.2 116.6 14 477 +1990 1 4 6 28 OSCAR 20.9 148.4 71 243 +1972 4 16 0 10 DEBBY 62.5 254.5 17 288 +1971 9 14 18 4 ISAAC 17.9 170.8 98 521 +1982 11 5 0 15 FLORENCE 64.8 234.1 54 870 +1986 7 4 12 21 NADINE 47.2 284.2 12 145 +1957 8 19 0 28 MICHAEL 17.9 125.3 113 606 +1989 8 17 18 7 ALBERTO 64.6 96.4 57 697 +2000 8 13 0 24 VALERIE 33.0 100.3 66 793 +1980 11 6 0 4 KIRK 16.2 289.1 23 871 +1989 4 12 6 13 ALBERTO 61.6 272.2 116 579 +1986 4 4 18 4 SANDY 15.5 248.8 59 41 +1957 4 25 6 11 GORDON 34.1 59.4 111 757 +1955 2 24 0 9 NADINE 27.7 81.3 40 264 +1952 2 10 6 16 CHRIS 45.0 61.6 137 771 +1988 11 15 12 11 GORDON 35.7 336.0 63 671 +1958 11 9 6 10 PATTY 35.6 65.6 155 18 +1985 9 11 12 7 ERNESTO 67.6 285.7 85 23 +1981 9 22 0 16 JOYCE 69.8 23.7 18 540 +1956 8 22 0 11 MICHAEL 65.8 160.5 51 109 +1950 9 9 6 9 MICHAEL 40.3 69.9 69 781 +1991 10 6 6 6 ISAAC 40.5 28.7 125 560 +2001 7 25 18 28 JOYCE 68.9 28.2 126 458 +1989 9 24 18 19 LESLIE 69.5 331.4 32 664 +2000 3 28 6 14 KIRK 13.6 245.7 106 569 +1957 3 21 12 3 JOYCE 12.6 9.5 17 687 +1977 4 20 0 25 RAFAEL 58.4 143.1 96 208 +1950 4 23 0 6 HELENE 21.0 35.2 104 744 +1963 8 17 0 15 JOYCE 43.1 78.4 121 338 +1970 1 2 18 17 HELENE 29.6 351.9 34 162 +1972 2 12 12 20 DEBBY 52.6 155.8 160 852 +1958 3 8 18 11 RAFAEL 34.8 333.8 103 651 +1989 9 27 12 14 TONY 21.3 79.0 71 45 +1967 10 4 0 24 KIRK 40.5 12.1 131 178 +1963 5 9 12 24 ISAAC 45.1 253.3 161 538 +1992 8 5 18 1 OSCAR 55.4 21.5 70 832 +1960 9 2 12 5 MICHAEL 69.1 123.9 105 28 +1983 3 9 0 22 MICHAEL 10.1 210.1 120 174 +1982 2 22 18 18 SANDY 19.0 110.1 37 172 +1975 7 28 12 21 NADINE 48.5 118.2 125 659 +1955 7 22 18 14 HELENE 27.9 226.6 69 487 +1957 8 7 18 5 BERYL 68.1 328.3 57 366 +1965 8 22 12 2 PATTY 64.7 327.5 88 557 +1988 3 18 12 1 RAFAEL 9.3 266.9 68 840 +1993 6 27 18 13 HELENE 31.8 322.4 83 447 +2001 4 19 18 15 PATTY 43.6 114.4 96 182 +1956 7 22 12 8 JOYCE 29.9 109.2 83 857 +1984 1 10 12 24 NADINE 69.1 151.7 21 77 +1997 12 4 6 21 PATTY 42.0 126.1 142 809 +1961 12 13 6 5 JOYCE 32.7 287.4 148 666 +1956 4 18 18 20 VALERIE 62.0 332.8 126 551 +1982 3 26 0 24 RAFAEL 12.4 349.2 103 101 +1958 5 22 0 2 TONY 69.5 44.0 11 53 +2000 5 8 6 12 BERYL 23.9 301.9 79 876 +1952 12 13 0 2 KIRK 12.7 148.6 161 211 +1972 1 21 0 28 GORDON 16.2 246.5 40 807 +1995 12 10 0 21 DEBBY 65.1 52.2 74 528 +1999 3 15 12 5 BERYL 23.6 99.2 130 245 +1951 8 4 18 9 BERYL 32.0 221.9 80 221 +1959 10 10 6 4 OSCAR 42.3 28.2 111 756 +1960 3 19 12 5 ERNESTO 33.6 106.2 161 140 +1997 5 9 6 4 ALBERTO 53.1 351.0 140 861 +1951 9 9 12 16 JOYCE 12.8 142.7 17 382 +1955 2 2 6 4 ALBERTO 10.8 52.5 48 314 +1961 3 9 12 15 NADINE 27.5 119.8 99 170 +1965 2 15 12 27 LESLIE 24.4 293.4 148 208 +1955 4 16 18 18 NADINE 48.7 42.8 106 424 +1971 3 10 18 23 ALBERTO 59.1 76.6 80 478 +1965 2 3 12 16 JOYCE 27.5 180.7 101 275 +1979 1 21 18 2 TONY 11.6 120.9 63 652 +1999 10 19 6 2 KIRK 40.6 338.0 111 215 +1984 3 12 12 9 GORDON 23.3 326.2 45 719 +1963 10 1 0 19 MICHAEL 41.6 268.8 121 163 +1999 4 2 0 10 ERNESTO 58.3 118.0 27 704 +1952 7 7 0 21 SANDY 51.2 131.1 154 388 +1971 3 16 18 21 BERYL 54.0 70.3 126 635 +1959 6 6 6 18 DEBBY 39.3 29.5 17 407 +1959 8 19 12 9 MICHAEL 30.4 249.7 143 3 +1951 7 9 12 19 KIRK 28.2 79.0 124 832 +1959 8 20 18 17 GORDON 53.7 28.9 34 454 +2003 9 16 0 2 WILLIAM 48.5 284.2 21 660 +1973 3 21 6 10 BERYL 58.6 55.8 132 57 +2004 3 19 18 20 JOYCE 17.0 179.8 98 706 +1990 4 21 12 12 MICHAEL 33.7 146.8 29 275 +1965 2 13 18 19 WILLIAM 49.7 220.0 130 169 +1991 12 2 0 9 CHRIS 38.2 177.6 98 132 +1972 7 11 0 11 JOYCE 8.0 270.2 111 836 +1950 12 20 12 2 MICHAEL 55.8 181.9 71 161 +1966 12 11 18 10 WILLIAM 69.6 336.3 74 814 +1958 5 11 6 20 BERYL 30.6 152.0 80 17 +2000 9 26 18 26 PATTY 20.1 33.0 162 514 +1951 8 3 12 2 TONY 12.9 321.5 115 526 +1962 4 18 12 1 LESLIE 23.9 85.1 95 296 +1966 8 17 0 7 FLORENCE 36.4 9.5 139 837 +1950 3 6 18 22 ERNESTO 54.7 208.0 27 674 +1995 3 13 0 24 MICHAEL 28.2 268.0 136 664 +1953 9 21 6 6 DEBBY 65.3 118.3 57 469 +1958 3 22 0 2 RAFAEL 48.6 50.5 151 693 +1960 5 4 18 22 HELENE 50.3 305.7 20 675 +1990 11 5 6 6 ALBERTO 69.4 337.3 114 656 +1961 12 23 12 27 GORDON 17.8 325.1 127 327 +1957 6 15 6 5 VALERIE 8.3 162.8 90 861 +1976 7 22 0 3 SANDY 12.5 175.5 60 239 +2004 2 15 12 8 WILLIAM 50.7 280.2 46 807 +1971 5 9 6 17 OSCAR 50.9 17.6 77 788 +1991 8 16 18 3 MICHAEL 61.2 165.7 136 749 +1993 6 9 0 17 PATTY 58.8 226.2 48 840 +1953 10 19 0 2 FLORENCE 22.9 204.4 129 6 +2000 9 9 6 17 LESLIE 52.8 234.5 72 235 +1990 10 1 12 1 HELENE 60.2 32.3 118 257 +1983 1 1 12 9 WILLIAM 10.1 306.8 130 262 +1981 9 9 0 27 SANDY 31.2 17.6 35 404 +1991 3 28 18 25 OSCAR 30.1 24.4 133 624 +1992 6 13 0 19 GORDON 28.9 3.8 105 32 +1986 9 2 6 25 CHRIS 8.6 305.5 113 447 +1953 11 6 0 19 ISAAC 21.1 72.3 143 498 +1967 4 28 18 19 CHRIS 69.9 350.7 133 41 +1955 2 5 18 27 FLORENCE 39.1 91.5 96 776 +1995 3 21 12 11 VALERIE 68.6 256.3 154 654 +1969 2 10 0 22 PATTY 27.4 341.2 141 57 +1963 5 8 12 13 JOYCE 36.0 127.3 11 809 +1999 11 26 0 27 MICHAEL 56.1 39.4 89 538 +1988 1 9 6 11 KIRK 36.0 176.4 127 786 +1994 1 25 18 24 DEBBY 36.1 85.1 44 869 +1987 2 24 12 13 NADINE 20.8 82.6 132 80 +1955 6 24 6 8 ISAAC 30.3 170.7 22 859 +2002 3 23 0 17 BERYL 58.4 350.2 17 435 +1969 12 14 6 5 OSCAR 57.0 307.3 90 561 +1986 4 1 6 8 RAFAEL 40.2 224.3 17 728 +1968 7 10 18 1 BERYL 23.1 258.7 96 672 +1980 7 17 6 20 DEBBY 9.6 141.0 63 651 +1964 7 8 0 7 TONY 59.3 22.1 49 842 +1973 2 14 18 21 SANDY 58.0 193.8 97 888 +1986 4 1 0 26 FLORENCE 45.8 286.2 35 654 +1999 11 10 18 26 LESLIE 31.2 56.6 103 305 +1980 3 14 12 19 PATTY 65.9 120.0 40 830 +1950 6 24 0 8 BERYL 54.2 253.2 64 444 +1974 6 21 18 5 VALERIE 21.9 133.0 63 575 +2000 8 22 0 2 SANDY 46.2 78.2 116 755 +1966 12 21 0 15 GORDON 18.6 99.8 94 758 +1966 1 1 6 18 ALBERTO 29.8 21.4 48 625 +1950 3 11 12 24 ISAAC 43.2 257.2 115 102 +1963 6 8 18 7 NADINE 68.8 64.0 87 572 +1995 12 9 6 10 TONY 27.8 232.7 63 361 +1987 3 22 0 12 JOYCE 9.9 19.0 89 698 +1962 2 24 18 23 FLORENCE 23.6 345.4 164 518 +1986 7 13 6 8 BERYL 22.0 51.3 139 682 +1967 6 24 12 11 TONY 44.7 266.5 54 214 +1963 5 19 12 4 ERNESTO 27.0 351.9 89 692 +1990 10 4 6 18 FLORENCE 65.3 30.5 108 159 +1950 2 14 18 13 MICHAEL 28.9 1.1 146 431 +1963 2 26 18 19 RAFAEL 41.4 232.6 163 483 +1951 5 3 12 20 DEBBY 67.2 258.3 18 161 +2001 3 8 6 11 FLORENCE 13.3 240.4 75 462 +1966 11 27 6 21 DEBBY 52.2 102.5 111 379 +1961 6 26 18 24 OSCAR 50.6 269.2 124 511 +1967 7 16 18 16 NADINE 48.0 178.0 39 576 +1984 8 11 18 7 CHRIS 14.0 129.4 53 371 +1972 9 17 0 4 BERYL 9.5 128.5 98 891 +1958 11 6 0 15 WILLIAM 15.0 24.1 136 870 +1968 5 28 6 17 HELENE 21.6 355.9 39 514 +1952 11 5 12 13 SANDY 26.5 336.2 35 164 +1981 6 11 18 1 OSCAR 15.8 175.8 85 527 +1961 3 12 0 7 PATTY 42.7 247.7 26 497 +1990 9 19 12 28 WILLIAM 27.1 27.9 55 867 +1996 1 18 12 22 CHRIS 57.5 146.5 21 264 +1953 3 6 0 2 KIRK 35.8 313.5 131 362 +1975 6 14 12 10 JOYCE 34.9 213.9 80 388 +1988 10 8 0 3 NADINE 37.2 342.1 135 89 +1983 1 14 0 5 JOYCE 22.3 313.6 151 534 +1978 11 8 12 10 GORDON 36.7 158.7 102 667 +1994 4 10 18 6 RAFAEL 20.8 138.3 140 96 +2003 6 12 18 26 BERYL 49.4 313.7 29 588 +1952 10 28 0 3 MICHAEL 42.3 337.5 41 338 +1951 3 17 0 1 WILLIAM 34.5 274.5 53 702 +1990 11 11 18 8 MICHAEL 63.2 334.7 158 364 +1959 8 27 12 21 JOYCE 23.9 38.0 18 834 +1964 9 13 0 5 BERYL 58.8 3.2 64 51 +1994 1 7 0 23 JOYCE 66.3 156.1 151 358 +1977 2 3 6 3 KIRK 53.1 28.9 12 783 +1956 6 1 18 11 DEBBY 55.5 250.1 21 579 +2002 10 3 6 5 NADINE 54.6 12.8 163 831 +2000 4 2 12 19 FLORENCE 7.1 201.0 145 548 +2003 5 18 12 2 DEBBY 17.2 132.9 79 122 +1988 10 26 12 16 JOYCE 53.2 134.2 60 754 +1958 6 17 6 19 CHRIS 65.0 333.0 111 227 +2003 4 8 18 23 TONY 19.4 229.5 74 82 +1975 9 5 6 28 ERNESTO 61.1 10.4 39 349 +1970 7 6 0 18 MICHAEL 40.9 34.3 78 576 +1991 3 9 18 18 VALERIE 14.7 26.5 112 393 +1963 3 5 6 23 CHRIS 67.4 138.3 149 623 +1993 8 25 0 2 ALBERTO 48.2 283.0 112 820 +1957 10 6 6 12 RAFAEL 20.1 192.9 91 716 +1994 5 25 0 16 DEBBY 53.7 339.2 164 448 +1978 6 7 0 22 HELENE 11.2 251.0 163 191 +1967 8 13 18 23 MICHAEL 31.6 259.5 159 643 +2002 1 13 12 13 JOYCE 66.2 283.7 117 461 +1979 6 18 18 28 MICHAEL 28.7 229.7 62 327 +1950 8 9 6 28 SANDY 14.0 21.2 127 650 +1987 9 28 12 18 ISAAC 42.4 42.4 51 625 +1986 11 23 0 26 PATTY 46.1 253.1 119 304 +1999 10 24 12 23 ALBERTO 32.7 20.7 50 441 +1964 8 18 18 25 ISAAC 24.9 14.3 150 161 +1987 11 22 12 6 TONY 55.0 181.1 22 550 +2000 1 12 6 16 OSCAR 56.4 343.1 38 883 +1983 8 18 6 23 KIRK 18.6 282.9 70 683 +1992 8 26 6 9 MICHAEL 11.7 9.7 63 437 +1963 11 22 6 15 LESLIE 31.5 145.1 62 877 +1966 9 5 0 5 NADINE 38.0 7.3 75 704 +1953 4 3 0 19 NADINE 30.6 61.6 53 885 +1959 11 2 6 9 LESLIE 43.9 162.4 16 662 +1953 3 17 18 8 GORDON 38.5 51.0 73 448 +1978 3 18 12 25 GORDON 39.5 316.0 18 522 +1997 8 1 0 15 KIRK 68.5 85.8 31 288 +2003 8 26 0 21 LESLIE 33.6 187.3 67 554 +1990 9 17 12 2 VALERIE 8.3 277.3 87 273 +1956 7 16 6 14 ISAAC 14.1 119.9 139 147 +1973 1 3 18 11 RAFAEL 28.4 248.9 73 365 +1986 7 17 6 24 WILLIAM 14.9 99.7 78 524 +1991 2 16 0 21 RAFAEL 31.0 139.4 39 5 +1964 6 14 12 20 OSCAR 30.4 160.0 30 825 +1994 10 21 18 4 ISAAC 50.3 134.3 89 770 +2001 6 13 18 17 LESLIE 35.4 180.6 132 529 +1994 4 3 12 27 PATTY 33.1 302.3 106 741 +1993 1 15 18 11 HELENE 49.0 165.3 61 41 +1987 12 12 0 26 DEBBY 52.4 228.8 14 813 +1999 5 28 12 9 HELENE 60.1 329.8 121 248 +1992 12 8 18 10 CHRIS 14.2 150.0 148 170 +1993 10 22 12 2 ALBERTO 35.7 226.8 103 287 +1993 7 9 6 25 CHRIS 26.5 0.6 158 873 +1999 4 10 18 4 DEBBY 28.6 60.3 65 427 +1978 6 25 18 25 TONY 14.4 350.6 132 174 +1968 4 22 0 17 DEBBY 16.6 268.8 54 681 +1964 3 26 12 18 ALBERTO 8.5 226.3 158 177 +1996 7 26 0 2 NADINE 24.4 208.0 120 207 +1980 12 26 0 19 ISAAC 7.1 272.9 135 233 +1965 12 12 12 6 KIRK 64.4 284.1 141 451 +1960 3 13 18 22 VALERIE 46.0 149.5 158 171 +1996 3 15 12 14 ERNESTO 13.8 80.9 69 559 +1958 10 8 0 11 RAFAEL 24.9 114.3 130 690 +1958 6 23 6 5 FLORENCE 48.0 51.6 144 714 +1971 8 15 0 19 KIRK 65.6 319.3 110 164 +1987 12 20 6 23 OSCAR 31.5 126.0 149 127 +1970 2 22 6 21 SANDY 54.3 260.6 10 426 +1991 10 15 18 13 ISAAC 14.6 203.7 76 371 +1957 11 7 12 4 RAFAEL 20.9 217.9 142 431 +1985 9 10 18 22 LESLIE 32.7 344.9 138 184 +1995 10 18 0 12 NADINE 19.0 234.0 25 797 +1975 2 10 18 28 HELENE 27.7 271.8 142 459 +1985 1 23 12 1 CHRIS 66.0 331.7 56 248 +1983 9 23 12 23 HELENE 51.4 336.5 131 896 +1952 12 19 0 11 FLORENCE 45.7 18.6 16 897 +1995 2 17 12 3 VALERIE 46.4 286.5 159 526 +1960 10 21 0 15 CHRIS 23.1 106.8 135 794 +1970 4 19 18 9 NADINE 39.2 64.2 19 704 +1967 6 8 12 11 DEBBY 7.5 307.3 97 691 +1995 6 16 18 9 ALBERTO 15.7 77.8 88 392 +1986 12 22 18 1 DEBBY 48.5 252.8 95 224 +1991 1 11 0 10 TONY 16.9 301.3 99 441 +1969 5 17 12 5 NADINE 26.3 161.9 64 445 +2004 1 16 18 8 NADINE 22.0 18.9 154 747 +1989 2 28 12 21 JOYCE 23.7 183.9 38 57 +1987 11 15 18 7 ALBERTO 44.0 213.0 23 859 +1962 6 10 0 15 JOYCE 69.6 259.7 34 521 +2003 1 5 12 12 BERYL 65.2 215.0 47 329 +1969 1 12 0 5 GORDON 43.1 108.7 15 864 +1970 7 21 12 18 NADINE 33.9 18.6 74 877 +1989 4 11 18 18 MICHAEL 39.8 119.8 105 895 +2003 7 14 18 4 CHRIS 8.0 52.1 57 343 +1957 8 26 18 8 LESLIE 66.0 243.3 51 598 +1977 8 14 0 8 WILLIAM 37.3 166.7 19 582 +1995 8 27 12 27 FLORENCE 34.9 224.9 119 143 +1957 4 16 6 19 TONY 29.1 147.8 14 317 +1981 8 10 18 5 ISAAC 35.6 200.4 79 770 +1965 4 23 12 27 VALERIE 19.1 209.1 99 241 +1964 1 18 0 2 FLORENCE 12.4 240.0 151 520 +1962 12 21 18 16 DEBBY 12.1 148.7 108 852 +1967 1 12 0 26 FLORENCE 8.1 148.1 132 618 +1954 9 17 0 24 ERNESTO 62.9 184.3 163 73 +1988 1 27 6 17 GORDON 45.5 132.9 28 343 +1975 7 7 12 1 FLORENCE 23.7 48.4 12 541 +2002 9 9 6 10 NADINE 63.0 234.5 89 598 +2004 1 7 0 7 DEBBY 39.1 277.6 145 341 +1989 10 18 12 19 ERNESTO 53.7 308.7 24 119 +1982 5 9 0 26 TONY 23.8 235.0 70 505 +1989 1 22 0 7 DEBBY 27.7 48.4 24 890 +1985 1 12 18 17 GORDON 22.3 340.0 115 375 +1997 9 20 6 26 WILLIAM 43.0 1.7 74 357 +2001 12 12 12 27 LESLIE 41.7 220.4 155 61 +1976 6 16 12 17 ERNESTO 18.5 186.5 135 739 +1987 7 9 18 11 VALERIE 32.0 62.1 109 186 +1996 5 27 0 4 JOYCE 10.5 205.5 53 717 +1998 8 20 6 20 LESLIE 41.6 297.7 64 592 +1989 11 6 12 19 MICHAEL 60.0 152.2 93 328 +1979 5 5 0 6 OSCAR 12.0 297.5 38 820 +1980 3 11 12 24 VALERIE 24.4 308.3 18 196 +1997 5 7 0 27 ERNESTO 26.9 318.9 112 169 +1974 9 6 18 14 RAFAEL 11.7 191.6 133 93 +1951 3 27 18 6 WILLIAM 8.7 74.9 152 836 +1960 5 15 12 13 ERNESTO 49.2 18.2 35 357 +1980 1 24 12 15 MICHAEL 24.5 81.4 152 358 +1969 11 4 6 13 PATTY 18.0 288.3 111 460 +1982 9 8 0 15 LESLIE 17.2 79.2 60 91 +1954 12 23 12 22 NADINE 64.0 2.1 89 632 +1994 9 27 18 5 ISAAC 12.0 157.6 37 485 +1975 2 28 0 15 TONY 29.0 65.7 33 4 +1994 2 14 18 2 LESLIE 16.6 305.8 33 787 +1982 11 24 12 6 OSCAR 33.1 180.8 88 603 +2001 4 7 12 9 DEBBY 31.8 240.3 74 33 +2000 2 6 12 11 DEBBY 67.3 204.0 49 632 +1985 5 17 18 4 JOYCE 41.4 297.5 143 11 +1969 8 8 0 28 KIRK 31.2 271.1 17 569 +1996 10 28 12 26 VALERIE 27.8 16.1 16 695 +1975 7 10 6 28 DEBBY 36.4 181.4 34 692 +2002 5 8 0 16 MICHAEL 57.7 75.7 87 538 +1956 8 4 6 27 GORDON 37.4 317.0 78 860 +1960 8 8 0 28 WILLIAM 30.0 50.0 86 296 +1980 4 24 0 13 BERYL 49.0 55.1 15 285 +1955 9 27 12 14 RAFAEL 27.8 47.8 41 406 +1996 10 15 0 13 NADINE 45.0 118.0 143 691 +1971 7 2 18 20 CHRIS 43.4 10.3 156 282 +1993 9 11 12 19 DEBBY 47.3 64.6 117 752 +1983 7 13 0 11 BERYL 50.1 87.8 69 5 +1951 12 2 6 7 NADINE 49.6 83.1 131 249 +1991 8 19 6 6 TONY 69.1 352.2 80 21 +2003 8 12 12 1 ALBERTO 18.5 88.1 111 602 +1990 7 12 18 21 WILLIAM 44.5 21.5 11 199 +1966 8 3 6 22 OSCAR 24.4 184.3 32 34 +1979 9 16 0 13 CHRIS 62.7 269.3 13 159 +1952 4 25 12 11 DEBBY 46.8 264.5 154 255 +1992 2 18 0 8 OSCAR 64.9 211.3 66 458 +1978 2 15 12 28 VALERIE 60.3 314.9 60 43 +1977 8 21 12 23 ERNESTO 58.5 81.0 38 524 +1992 3 8 6 12 BERYL 56.3 11.0 134 207 +1951 6 24 18 24 CHRIS 69.5 130.9 129 275 +1971 9 4 18 11 CHRIS 35.5 336.9 96 286 +1953 4 17 6 26 BERYL 65.7 287.2 123 405 +1980 5 18 12 12 RAFAEL 31.4 137.1 31 806 +1974 12 5 18 23 CHRIS 48.3 4.1 82 749 +1951 11 5 18 20 NADINE 36.1 185.5 107 806 +1954 6 24 0 27 GORDON 37.4 219.6 95 837 +1961 5 6 18 14 LESLIE 52.4 75.6 16 876 +1987 7 18 18 12 OSCAR 62.8 106.5 70 164 +1987 10 28 18 17 LESLIE 36.0 351.8 56 467 +1959 7 27 18 11 ERNESTO 28.3 86.1 27 681 +1991 11 1 0 4 VALERIE 66.2 19.2 78 781 +1950 1 1 12 24 ALBERTO 48.0 246.3 130 123 +1973 12 10 6 21 PATTY 34.7 118.7 42 780 +1961 3 1 0 10 CHRIS 66.0 172.2 14 515 +1999 9 4 6 16 JOYCE 14.7 332.8 159 310 +1987 6 17 18 9 DEBBY 51.4 336.1 111 533 +1992 5 3 18 23 MICHAEL 54.6 43.0 41 266 +1970 4 1 12 25 DEBBY 62.2 239.3 64 525 +1955 11 13 12 15 MICHAEL 45.2 210.4 114 172 +1999 3 4 12 20 GORDON 52.0 342.7 40 342 +1995 8 27 12 24 TONY 23.5 123.5 104 889 +1976 5 3 6 19 MICHAEL 65.0 264.8 108 8 +2004 6 21 6 23 ALBERTO 35.0 292.0 55 53 +1982 6 8 12 6 SANDY 51.8 107.6 14 721 +1991 7 12 6 20 CHRIS 12.8 305.9 57 819 +1958 11 19 6 25 LESLIE 57.8 179.8 40 726 +1994 1 11 0 15 RAFAEL 35.7 261.0 151 353 +1975 5 28 12 18 OSCAR 27.7 8.5 161 488 +1981 5 12 18 2 MICHAEL 29.9 35.8 61 57 +1968 12 1 12 1 SANDY 52.5 316.9 25 445 +1987 1 11 0 8 LESLIE 31.0 62.7 10 81 +1979 8 8 18 12 KIRK 64.6 209.0 116 527 +1951 1 13 0 11 VALERIE 66.9 73.2 60 230 +1989 9 21 6 9 ALBERTO 10.9 22.8 21 511 +1983 8 8 6 4 FLORENCE 20.8 351.5 116 783 +1981 6 27 0 18 MICHAEL 65.0 231.1 36 5 +1989 6 17 0 23 MICHAEL 42.9 62.9 105 873 +1994 12 18 0 17 GORDON 19.9 149.6 33 630 +1950 6 17 18 5 DEBBY 63.0 59.1 17 358 +2003 12 15 12 3 BERYL 18.3 335.9 77 796 +1974 5 6 12 11 MICHAEL 18.1 64.1 160 368 +1977 9 21 18 18 CHRIS 10.1 144.3 87 774 +1976 12 8 18 24 BERYL 29.3 150.6 68 266 +1994 1 28 6 18 ISAAC 61.3 155.2 104 725 +1959 9 27 12 9 FLORENCE 14.9 266.0 60 240 +2000 12 2 0 21 SANDY 26.6 26.2 69 741 +1968 8 2 0 18 FLORENCE 43.2 109.9 87 685 +1963 3 22 12 15 MICHAEL 52.2 244.9 133 256 +1978 1 13 0 6 MICHAEL 61.8 335.0 10 574 +1972 4 10 6 11 DEBBY 31.7 62.6 14 376 +1986 6 26 6 26 LESLIE 56.6 31.1 139 840 +1996 11 27 0 18 DEBBY 52.6 59.3 33 806 +1957 9 23 6 1 OSCAR 66.5 108.5 124 783 +1993 12 14 6 25 GORDON 60.1 261.3 149 814 +2004 12 19 0 28 BERYL 7.1 116.1 26 804 +2002 2 10 12 9 RAFAEL 18.2 82.7 13 678 +1959 6 19 12 22 MICHAEL 48.1 101.0 158 745 +1987 12 28 18 8 RAFAEL 46.2 15.9 68 857 +1982 9 17 6 16 SANDY 10.9 254.2 112 81 +1991 9 28 18 24 CHRIS 39.3 68.5 11 79 +2004 5 20 0 1 RAFAEL 34.3 314.4 117 626 +1976 4 28 6 2 WILLIAM 63.8 6.3 66 321 +1998 6 8 12 14 BERYL 7.3 150.0 22 480 +2004 10 28 12 20 KIRK 29.4 141.9 87 232 +1974 1 8 0 15 MICHAEL 60.4 46.5 53 751 +1995 10 12 12 28 MICHAEL 15.3 230.4 156 355 +1975 5 20 0 8 TONY 27.2 197.5 133 400 +1951 11 14 12 20 ISAAC 58.4 336.0 47 637 +1966 6 16 0 24 ISAAC 12.2 126.9 40 248 +1977 3 6 6 23 BERYL 14.1 232.6 142 672 +2002 4 14 6 12 NADINE 68.1 111.3 138 861 +1993 3 3 12 10 OSCAR 9.0 238.3 102 176 +1960 9 12 6 28 RAFAEL 20.0 300.7 43 623 +1974 10 3 0 19 TONY 68.3 162.8 90 457 +1981 9 4 0 28 JOYCE 36.9 232.4 115 597 +1964 4 16 6 22 MICHAEL 24.5 107.3 23 314 +1981 2 15 6 13 NADINE 7.5 34.3 107 791 +1989 1 20 12 1 JOYCE 54.2 161.0 17 601 +1989 9 2 6 5 KIRK 18.5 282.7 86 578 +2004 5 1 6 7 FLORENCE 45.1 239.7 80 500 +1984 8 27 18 19 HELENE 26.0 286.7 149 690 +1997 12 12 0 1 ERNESTO 67.3 233.5 162 303 +1977 11 14 6 26 NADINE 30.1 43.3 133 821 +1985 5 26 18 18 DEBBY 68.8 205.9 133 385 +1974 6 24 12 24 JOYCE 49.3 8.6 156 17 +1995 9 27 18 1 NADINE 56.5 188.7 98 203 +1993 6 3 0 2 OSCAR 18.1 336.2 125 846 +1988 11 12 12 6 VALERIE 24.3 291.9 158 527 +1953 9 17 18 11 MICHAEL 41.3 285.0 121 686 +2003 3 13 6 12 LESLIE 58.9 197.2 60 228 +1996 7 10 0 17 LESLIE 11.5 178.8 85 884 +1990 3 2 0 20 SANDY 32.0 178.2 119 39 +1990 7 25 6 17 HELENE 63.4 74.2 141 738 +1961 5 4 18 4 RAFAEL 44.7 68.0 129 217 +2004 1 16 12 7 ERNESTO 34.2 305.0 60 865 +1965 9 7 0 1 RAFAEL 52.1 188.7 40 720 +1988 4 23 18 8 TONY 53.4 51.8 13 20 +1974 10 18 18 25 JOYCE 69.0 230.3 129 700 +1997 1 18 18 27 HELENE 38.7 242.9 92 691 +1955 1 25 0 14 ERNESTO 12.8 73.2 104 121 +2000 5 4 6 8 MICHAEL 46.7 177.1 89 652 +1977 6 21 18 8 CHRIS 8.1 149.0 73 521 +1972 12 22 12 13 BERYL 68.1 166.6 53 431 +1982 8 10 6 22 ALBERTO 15.4 308.2 106 279 +1959 6 22 0 20 HELENE 45.2 4.8 35 463 +1962 4 9 18 2 JOYCE 7.0 166.7 59 876 +1987 12 9 18 17 LESLIE 50.1 227.4 32 881 +1988 3 27 6 10 DEBBY 44.2 172.9 41 874 +1995 11 12 12 20 ALBERTO 53.2 16.0 101 4 +1968 5 17 0 5 WILLIAM 60.4 286.4 93 297 +1959 6 18 6 7 VALERIE 28.5 179.3 62 894 +1958 8 1 18 3 BERYL 34.4 124.0 143 171 +1950 8 23 6 7 LESLIE 65.2 165.7 117 525 +1982 1 16 18 4 JOYCE 35.1 283.3 125 309 +1962 2 23 18 6 LESLIE 39.4 278.7 138 213 +1980 4 5 12 7 LESLIE 54.5 18.4 124 425 +1964 7 12 12 9 KIRK 19.0 261.8 136 436 +1954 6 28 18 26 FLORENCE 62.0 343.6 138 321 +1962 6 25 0 5 ALBERTO 17.6 12.8 41 4 +1972 1 5 6 10 PATTY 34.6 278.1 72 137 +1951 1 21 0 2 HELENE 63.0 49.5 32 347 +1972 1 23 18 5 NADINE 8.8 253.6 102 12 +1951 6 2 12 19 ERNESTO 27.3 250.7 77 355 +1970 9 19 0 11 CHRIS 67.5 357.1 35 894 +1969 4 25 18 11 LESLIE 16.6 9.3 124 259 +1998 2 11 6 17 TONY 32.2 55.3 98 299 +2003 7 5 12 28 DEBBY 41.6 299.1 83 393 +1960 8 10 12 17 TONY 15.6 286.1 106 845 +1971 2 28 6 10 TONY 16.5 251.3 123 71 +1986 6 24 6 7 ERNESTO 17.5 231.1 126 881 +1985 7 13 0 6 LESLIE 14.0 238.9 69 15 +1951 12 6 6 10 TONY 36.6 69.8 85 441 +1953 8 13 18 9 ALBERTO 35.8 91.6 159 132 +1970 3 18 6 3 MICHAEL 41.5 43.5 22 860 +1968 7 12 18 19 DEBBY 38.4 223.2 129 91 +1966 1 24 0 11 PATTY 57.3 95.2 160 640 +1995 11 5 18 1 HELENE 39.2 141.7 35 567 +1969 8 12 6 8 FLORENCE 19.8 355.9 92 429 +1986 5 22 0 10 OSCAR 67.5 21.1 152 45 +1981 1 22 0 28 VALERIE 39.6 313.0 97 638 +1975 7 23 18 6 OSCAR 20.6 22.2 143 895 +1981 4 13 12 1 VALERIE 35.1 336.5 32 697 +2000 3 19 18 1 ERNESTO 44.9 284.6 31 675 +1965 1 15 18 27 TONY 46.7 327.7 20 133 +1977 1 17 12 1 WILLIAM 67.1 79.6 72 441 +1964 1 11 18 12 NADINE 15.2 164.1 147 261 +1981 10 17 0 25 HELENE 24.5 326.5 134 327 +1956 10 28 18 23 GORDON 53.8 223.9 80 523 +1951 1 12 18 25 FLORENCE 18.0 40.6 70 500 +1994 1 25 6 7 BERYL 11.1 167.1 140 369 +1972 12 17 12 11 MICHAEL 61.5 272.8 49 27 +1971 6 3 0 27 ISAAC 44.1 349.1 149 100 +1990 6 5 18 2 JOYCE 53.9 184.0 49 200 +1955 3 12 12 8 CHRIS 50.4 252.4 72 252 +1998 8 9 6 5 RAFAEL 23.1 41.2 143 300 +1956 4 13 18 25 GORDON 25.9 7.0 151 183 +1986 7 22 6 6 VALERIE 37.6 29.6 105 51 +1950 5 27 18 3 PATTY 43.2 162.8 95 196 +1994 10 24 6 20 GORDON 20.7 239.4 158 561 +1984 9 27 0 19 MICHAEL 17.9 216.5 62 320 +2001 1 15 18 16 LESLIE 36.4 31.3 137 316 +1957 6 8 18 24 ALBERTO 40.1 328.0 136 9 +1999 5 23 12 7 GORDON 25.7 285.6 135 42 +1952 12 12 6 7 HELENE 9.4 250.9 126 169 +1967 1 26 12 28 MICHAEL 29.7 313.1 152 333 +1994 8 16 0 28 ERNESTO 68.9 191.4 135 173 +1992 8 11 0 9 KIRK 44.7 229.8 87 598 +1988 3 2 0 5 NADINE 36.6 223.4 58 773 +1962 4 18 18 10 RAFAEL 30.3 182.2 28 898 +1986 1 23 6 19 VALERIE 19.4 23.6 112 191 +1985 6 17 6 2 MICHAEL 8.5 8.9 160 9 +1956 1 1 18 28 DEBBY 32.4 87.2 123 798 +1974 2 14 0 7 ERNESTO 28.2 192.3 11 547 +1984 9 26 6 28 TONY 23.1 320.6 133 545 +1990 7 22 12 24 ALBERTO 10.5 52.8 23 90 +1974 5 16 0 1 VALERIE 12.6 317.0 100 86 +1974 9 24 0 28 GORDON 64.2 98.4 17 341 +1957 8 26 12 26 PATTY 69.8 61.2 22 583 +1970 5 8 0 22 VALERIE 8.0 167.3 104 556 +1962 2 18 12 9 RAFAEL 55.4 330.4 151 689 +1989 1 6 12 13 FLORENCE 27.9 119.7 54 406 +1993 12 6 18 5 DEBBY 50.9 3.8 110 39 +1982 4 7 12 1 NADINE 35.6 313.7 99 535 +1964 12 5 12 25 TONY 63.1 356.0 152 14 +1950 5 16 12 18 ISAAC 41.9 161.4 103 781 +1998 9 18 6 5 ALBERTO 60.3 103.0 61 583 +1995 10 22 0 12 TONY 23.6 229.3 17 828 +1953 8 12 6 24 TONY 67.7 105.6 26 532 +1954 8 15 6 1 ISAAC 7.7 201.6 139 566 +1976 11 2 0 1 DEBBY 36.5 133.8 90 160 +1952 9 26 18 13 RAFAEL 53.0 148.4 88 300 +1975 10 5 18 4 FLORENCE 39.8 16.2 76 202 +1972 7 15 6 3 GORDON 37.0 161.0 138 529 +1971 4 17 18 21 NADINE 63.2 29.6 140 726 +1954 5 4 12 4 NADINE 39.3 224.7 97 764 +2004 3 6 0 6 DEBBY 37.8 99.4 75 566 +1962 9 7 12 9 ISAAC 35.3 313.5 86 592 +1969 5 17 6 8 RAFAEL 64.9 27.0 131 861 +1969 1 7 12 6 FLORENCE 46.3 29.6 20 351 +1997 8 21 6 3 ALBERTO 16.6 183.7 47 602 +1964 10 2 12 5 OSCAR 56.6 20.5 85 474 +1970 9 15 12 27 DEBBY 26.7 64.6 108 214 +1983 9 17 0 11 OSCAR 60.8 107.6 48 5 +1981 2 3 6 23 PATTY 50.5 129.6 56 196 +1981 7 7 12 17 TONY 62.4 285.5 109 475 +2001 1 21 12 17 ISAAC 16.0 308.4 134 606 +1973 1 13 0 19 PATTY 51.2 53.3 163 500 +1983 1 14 6 6 ALBERTO 55.8 193.8 156 567 +1971 10 12 18 27 DEBBY 62.8 151.5 109 227 +2004 7 17 12 6 LESLIE 19.7 175.4 99 184 +1995 11 8 12 15 SANDY 58.6 242.7 159 784 +1951 11 27 18 5 NADINE 52.3 52.5 67 31 +1968 1 5 0 9 WILLIAM 20.8 195.4 95 106 +1978 3 4 18 27 KIRK 56.2 130.5 73 430 +1969 10 22 0 5 CHRIS 63.5 52.7 146 366 +1970 12 2 6 16 ALBERTO 48.0 144.4 153 547 +2003 9 8 0 3 WILLIAM 35.5 1.9 144 403 +1968 10 14 0 10 GORDON 53.2 72.4 40 337 +1951 7 19 18 18 JOYCE 36.1 343.7 80 510 +1977 3 3 18 15 LESLIE 62.5 222.3 94 1 +1977 8 5 0 21 HELENE 29.6 110.9 128 7 +1961 2 27 18 23 ERNESTO 15.8 317.2 152 567 +2004 12 4 18 24 PATTY 18.7 163.7 152 623 +1963 9 3 12 9 TONY 59.7 249.1 89 648 +1972 9 3 18 16 ISAAC 52.1 48.2 72 457 +1958 4 8 0 25 TONY 48.1 127.9 14 817 +1969 1 2 18 25 OSCAR 24.5 324.1 35 360 +1967 6 15 12 23 MICHAEL 60.7 98.0 121 375 +2003 11 21 6 28 WILLIAM 56.1 105.2 23 844 +1989 4 28 6 17 ERNESTO 50.3 164.1 131 345 +1969 11 9 18 10 ALBERTO 58.9 168.1 43 806 +2002 2 28 6 26 CHRIS 52.6 314.5 91 730 +1965 8 27 0 12 GORDON 40.0 87.3 141 872 +2003 2 3 0 5 OSCAR 22.4 49.9 29 614 +1958 10 5 12 7 ALBERTO 40.7 135.0 94 273 +1973 7 13 12 13 KIRK 29.1 200.6 131 224 +1999 10 20 12 3 HELENE 18.1 264.9 85 862 +1952 11 7 6 1 SANDY 68.9 277.3 15 849 +1951 9 4 6 13 FLORENCE 18.4 192.7 146 133 +1956 6 17 0 7 HELENE 34.6 323.8 95 144 +1975 6 12 6 5 MICHAEL 33.0 227.8 66 613 +1982 4 8 6 1 ISAAC 40.0 308.5 44 702 +1953 7 28 18 12 BERYL 23.6 308.5 47 884 +1962 3 2 0 8 PATTY 14.3 268.4 67 402 +2001 5 19 0 23 LESLIE 27.5 79.2 152 790 +1960 9 18 0 27 NADINE 46.7 303.5 105 254 +2004 1 21 12 6 RAFAEL 69.2 215.2 107 601 +1956 4 4 0 2 ERNESTO 44.5 60.6 86 639 +1956 2 2 6 27 BERYL 17.7 24.8 41 237 +1996 10 4 6 1 BERYL 61.5 254.7 96 109 +1983 12 15 18 28 HELENE 38.4 92.6 131 354 +1986 6 17 12 10 LESLIE 67.8 78.3 68 638 +1985 11 16 18 1 ISAAC 32.2 300.7 113 607 +1983 5 17 6 4 FLORENCE 53.5 318.5 116 797 +1978 9 9 12 16 FLORENCE 67.3 8.8 75 691 +1984 3 27 0 18 VALERIE 19.7 292.4 24 839 +1988 8 17 18 28 KIRK 49.4 0.7 81 851 +1974 6 7 12 22 ERNESTO 13.4 12.7 108 447 +1996 3 15 18 28 NADINE 25.7 301.5 92 432 +1965 6 28 0 14 DEBBY 64.0 71.0 41 551 +1959 6 22 0 13 ISAAC 66.6 62.8 59 105 +1981 7 4 6 14 PATTY 27.3 277.8 22 78 +1992 9 12 18 2 BERYL 9.3 314.5 48 616 +1966 3 5 18 25 GORDON 20.5 308.7 88 107 +1983 11 12 12 12 LESLIE 66.3 234.6 95 369 +1987 12 21 18 16 GORDON 47.0 306.5 107 126 +1963 8 6 12 24 NADINE 7.3 236.8 96 591 +1970 11 20 0 3 WILLIAM 56.9 132.4 129 122 +1997 9 23 0 13 SANDY 12.2 43.0 146 808 +1958 8 25 6 28 ISAAC 17.1 354.5 116 231 +1960 7 13 12 26 NADINE 24.1 243.1 86 253 +1959 10 10 18 9 PATTY 19.5 158.1 126 225 +1969 9 26 12 5 HELENE 69.3 148.7 162 113 +1967 10 13 18 24 MICHAEL 70.0 264.7 48 121 +1980 2 4 12 2 FLORENCE 53.7 100.0 80 718 +1968 2 3 0 20 ERNESTO 36.2 245.8 105 280 +1980 2 12 12 24 MICHAEL 52.1 266.5 149 287 +2002 11 11 18 8 BERYL 24.7 148.6 75 251 +1990 5 17 0 19 VALERIE 59.7 235.0 89 382 +1978 6 14 18 12 KIRK 60.9 231.3 74 841 +1951 1 9 18 8 ISAAC 30.8 135.6 29 354 +1994 12 3 18 23 LESLIE 32.3 309.1 71 108 +1957 1 4 18 22 CHRIS 8.6 50.1 112 573 +1970 6 21 18 24 MICHAEL 68.4 327.9 150 92 +1958 8 16 0 27 MICHAEL 45.2 187.5 22 58 +1972 9 15 18 21 VALERIE 64.5 52.6 108 506 +1959 9 26 6 12 LESLIE 60.2 87.3 145 689 +1977 11 26 12 2 LESLIE 22.5 293.4 29 389 +1952 12 2 18 5 RAFAEL 67.6 110.3 111 175 +1990 7 10 12 27 FLORENCE 62.1 303.3 30 219 +1977 11 7 18 11 WILLIAM 30.2 30.6 22 556 +1985 1 17 18 24 HELENE 51.5 183.8 29 641 +2004 5 5 6 15 VALERIE 66.0 80.9 88 882 +1979 2 2 18 4 NADINE 44.2 220.4 34 35 +1997 10 18 6 2 HELENE 46.7 232.5 60 808 +1962 12 17 6 7 JOYCE 54.5 137.1 20 61 +1967 8 28 6 16 SANDY 29.1 156.4 110 284 +1973 5 10 6 28 LESLIE 65.5 346.9 155 30 +1973 3 28 18 24 RAFAEL 16.1 29.0 148 206 +1953 12 20 0 21 MICHAEL 67.1 81.1 69 529 +1975 6 10 12 4 CHRIS 52.1 62.0 44 149 +1961 2 15 0 22 TONY 51.2 351.2 24 172 +1975 7 28 0 25 VALERIE 63.5 265.4 39 424 +1987 5 6 18 12 KIRK 48.0 299.4 40 580 +1973 9 3 12 6 WILLIAM 47.2 349.7 25 267 +2001 2 18 18 12 TONY 27.4 9.9 12 116 +1987 2 6 12 21 KIRK 21.5 251.7 16 244 +1992 9 9 6 15 SANDY 50.7 27.6 108 341 +1994 8 7 6 6 PATTY 27.5 339.8 22 717 +1964 6 9 6 19 LESLIE 38.2 287.5 95 335 +1967 12 20 0 2 CHRIS 13.6 48.8 39 431 +1984 6 5 0 1 ALBERTO 24.6 294.8 111 191 +1993 3 28 0 14 CHRIS 46.4 286.7 38 338 +1995 7 24 6 3 BERYL 47.9 283.5 78 736 +1995 12 8 0 18 MICHAEL 65.9 34.9 99 359 +1951 1 12 0 9 JOYCE 46.2 305.9 163 479 +1993 1 18 0 13 FLORENCE 52.8 352.5 45 295 +2000 4 8 0 6 NADINE 63.2 190.6 150 108 +1955 1 12 18 19 BERYL 36.5 132.2 77 827 +1952 12 8 6 19 ERNESTO 38.4 278.2 111 43 +1981 5 22 6 12 JOYCE 58.4 121.2 148 762 +1981 8 26 6 16 NADINE 44.0 241.0 51 489 +1960 6 18 0 6 TONY 17.7 97.4 116 742 +1952 9 16 18 14 WILLIAM 13.6 211.7 30 106 +1994 11 6 6 6 ISAAC 58.0 136.9 68 411 +1993 1 22 6 18 LESLIE 51.3 267.5 30 362 +1970 11 19 6 18 GORDON 8.8 69.7 70 523 +1957 8 12 18 16 PATTY 10.5 158.7 96 837 +1966 12 4 12 26 FLORENCE 58.2 60.9 154 595 +1980 1 24 18 1 TONY 58.3 241.9 79 311 +1978 9 22 0 14 RAFAEL 30.4 49.0 26 653 +1977 1 21 18 11 WILLIAM 11.2 33.4 28 729 +1952 5 8 6 10 WILLIAM 23.7 67.2 147 642 +1987 5 25 6 10 ALBERTO 42.1 160.4 126 154 +1965 6 11 6 12 WILLIAM 24.8 217.2 145 790 +1973 4 21 0 1 LESLIE 47.2 273.2 64 505 +1964 7 20 0 26 KIRK 52.7 196.0 14 865 +1985 2 7 12 20 GORDON 40.5 24.9 99 828 +1980 6 16 0 2 OSCAR 12.2 315.6 106 395 +1998 1 21 0 18 ERNESTO 61.5 340.1 129 27 +1966 3 10 6 1 SANDY 54.2 65.2 148 418 +2003 6 4 6 27 WILLIAM 43.3 95.1 142 338 +1989 3 10 0 20 ALBERTO 55.2 171.6 61 17 +1972 1 27 0 22 SANDY 8.1 270.8 163 694 +1950 8 7 18 5 WILLIAM 10.2 155.9 163 396 +1968 8 5 18 16 CHRIS 12.3 128.7 99 467 +1985 6 1 6 20 RAFAEL 10.9 250.5 68 698 +1950 10 19 6 21 ALBERTO 52.5 125.4 153 400 +1955 4 15 12 15 GORDON 66.7 71.6 52 658 +1960 5 4 18 15 CHRIS 41.3 2.7 43 393 +1961 1 20 12 10 TONY 55.9 278.1 40 110 +1986 11 7 6 9 ERNESTO 21.8 233.5 18 41 +1967 4 12 12 23 ALBERTO 13.9 232.5 158 276 +1974 10 18 0 19 CHRIS 47.1 5.2 147 824 +1958 6 11 18 5 DEBBY 40.0 166.4 67 297 +1997 7 14 6 22 FLORENCE 7.5 30.1 61 214 +2000 5 28 0 26 ISAAC 26.9 34.4 128 546 +1990 11 17 0 27 JOYCE 47.4 190.2 106 11 +1998 5 9 12 8 ALBERTO 14.4 316.1 85 767 +2000 1 18 18 23 ISAAC 28.9 108.9 135 746 +1955 5 13 18 7 SANDY 40.0 317.8 143 335 +1988 7 20 6 7 JOYCE 48.1 191.5 45 341 +1995 8 17 0 25 TONY 10.3 98.4 117 327 +1972 7 12 6 13 FLORENCE 62.7 9.2 136 429 +1956 3 5 6 9 NADINE 56.5 148.5 75 689 +1985 8 7 18 18 SANDY 64.1 157.8 14 394 +1985 1 15 6 12 HELENE 33.8 197.0 85 46 +1978 5 8 6 15 FLORENCE 51.1 180.9 39 52 +1968 3 16 6 12 LESLIE 13.3 241.5 86 106 +1966 6 24 12 17 ALBERTO 61.5 128.0 126 163 +1964 1 21 12 9 ERNESTO 28.6 72.2 65 721 +1960 1 11 18 26 PATTY 38.1 286.2 20 747 +2000 10 21 12 26 WILLIAM 28.7 90.1 162 726 +1971 5 3 6 10 KIRK 60.6 161.4 107 736 +1972 10 11 0 22 GORDON 26.6 189.2 147 732 +1985 3 17 18 5 LESLIE 41.4 347.0 36 849 +1963 3 3 18 20 NADINE 10.7 232.5 136 318 +1986 2 21 18 9 FLORENCE 58.1 283.8 29 79 +1987 4 2 12 13 DEBBY 39.9 333.5 22 746 +1991 8 28 6 6 BERYL 59.6 275.7 11 854 +1978 8 9 18 8 ALBERTO 61.0 231.7 73 525 +1967 11 2 0 5 TONY 19.1 336.0 105 661 +1968 1 28 18 13 FLORENCE 7.6 41.1 57 878 +1970 3 8 18 27 KIRK 66.1 281.3 39 333 +1982 6 23 12 11 RAFAEL 62.8 67.0 124 372 +1975 1 5 6 10 WILLIAM 57.2 21.9 101 341 +1972 8 14 18 22 HELENE 57.4 46.7 123 104 +1993 5 21 12 4 RAFAEL 31.0 107.3 95 604 +1957 6 13 12 28 GORDON 57.4 354.4 15 707 +1966 5 19 18 4 WILLIAM 23.2 26.2 20 827 +1961 10 25 18 8 TONY 27.0 61.3 65 638 +1963 1 28 6 9 VALERIE 25.1 234.0 123 499 +1952 5 5 12 13 FLORENCE 45.6 292.0 16 567 +1957 11 19 12 14 ALBERTO 15.2 310.4 48 111 +1957 2 9 0 5 LESLIE 41.4 243.5 120 5 +1972 12 13 12 17 FLORENCE 50.0 309.6 13 366 +1985 12 11 0 9 MICHAEL 34.8 332.0 75 189 +1964 4 13 12 15 JOYCE 33.2 91.0 84 245 +1959 8 26 18 24 GORDON 67.1 203.5 137 767 +1991 10 4 6 2 SANDY 43.9 354.2 137 380 +1990 12 5 12 19 GORDON 44.7 136.7 76 205 +1984 7 15 0 12 JOYCE 62.6 142.9 109 381 +1979 11 4 6 6 KIRK 12.7 288.3 32 277 +1960 1 7 18 2 VALERIE 60.0 269.6 10 92 +1957 7 20 12 11 CHRIS 41.5 265.1 138 367 +1976 5 26 6 16 MICHAEL 53.4 156.0 47 819 +1974 8 6 18 14 PATTY 64.0 80.8 138 856 +1972 5 6 18 8 ALBERTO 12.6 22.7 40 719 +1986 9 28 18 1 TONY 16.5 151.0 160 646 +1954 7 21 6 25 WILLIAM 14.1 99.0 84 764 +1969 12 2 6 7 TONY 53.9 234.5 30 569 +1997 7 17 12 2 BERYL 28.7 56.8 22 525 +1975 11 8 18 17 GORDON 62.1 209.6 67 9 +1969 9 6 6 4 ERNESTO 36.7 129.9 82 788 +2001 9 26 6 18 BERYL 42.1 43.3 110 689 +1959 2 20 0 22 MICHAEL 7.9 337.7 28 98 +1980 2 4 18 12 BERYL 59.4 133.9 47 232 +2003 3 20 0 28 GORDON 56.1 76.9 120 623 +1971 11 26 18 14 GORDON 22.3 7.4 159 664 +1990 4 17 18 9 KIRK 48.4 335.1 46 558 +1996 9 12 6 22 DEBBY 22.9 335.5 64 194 +1952 3 24 0 4 BERYL 25.6 203.5 28 831 +2003 2 19 0 8 CHRIS 36.3 81.2 138 571 +1986 4 21 12 26 DEBBY 69.6 249.6 72 854 +1963 9 22 18 2 GORDON 60.0 116.0 72 499 +1999 9 6 12 19 GORDON 7.6 243.9 25 645 +1985 7 2 12 28 ALBERTO 68.8 65.3 115 782 +1969 9 5 0 5 SANDY 68.9 324.0 58 769 +1958 2 25 18 28 SANDY 29.3 356.5 159 551 +1969 5 27 0 10 ERNESTO 25.7 342.6 99 352 +1963 5 22 0 5 CHRIS 62.1 125.5 50 372 +1958 1 11 18 18 CHRIS 29.8 176.0 161 807 +1992 7 13 0 14 DEBBY 12.3 147.3 55 389 +1970 6 18 18 7 KIRK 44.4 39.9 65 394 +1969 3 15 18 19 ERNESTO 61.9 331.6 43 682 +1960 7 10 12 4 CHRIS 30.0 94.0 36 688 +1989 8 3 18 14 GORDON 12.5 15.0 36 251 +1980 12 7 18 27 SANDY 17.8 215.1 12 714 +1961 9 20 12 26 HELENE 48.2 49.0 116 556 +1991 9 19 0 13 ALBERTO 69.2 111.0 13 93 +1987 9 17 6 20 HELENE 7.3 44.6 94 895 +1985 2 28 12 3 ISAAC 66.3 65.9 65 253 +1974 11 25 18 17 RAFAEL 16.9 52.4 42 549 +1970 9 10 6 13 VALERIE 22.9 65.3 116 700 +1976 4 7 12 13 WILLIAM 65.3 97.3 135 319 +1992 6 23 0 24 KIRK 54.9 33.6 139 443 +1996 4 15 0 28 SANDY 31.4 209.9 147 111 +1971 3 5 12 27 CHRIS 49.6 146.3 143 789 +1964 11 12 12 26 DEBBY 58.4 62.8 105 281 +1991 2 22 18 16 OSCAR 21.9 86.9 152 796 +1989 11 2 12 19 MICHAEL 57.3 277.0 145 172 +1960 6 5 0 15 RAFAEL 56.1 306.1 31 417 +1955 12 1 18 19 FLORENCE 41.1 342.3 141 648 +1989 2 26 12 21 ERNESTO 15.9 50.5 110 788 +1956 8 23 12 14 JOYCE 40.5 109.5 123 761 +1971 7 5 12 12 GORDON 60.5 38.5 90 818 +1966 3 26 0 22 SANDY 39.6 249.5 52 540 +1977 4 4 6 23 TONY 68.8 120.8 134 212 +1994 5 11 12 1 FLORENCE 66.6 154.7 132 234 +1999 7 12 0 14 JOYCE 47.9 355.0 155 4 +1950 9 28 12 8 MICHAEL 46.6 38.7 145 488 +2003 7 7 18 16 LESLIE 65.0 100.0 152 656 +1997 2 25 6 18 NADINE 51.6 306.1 105 550 +1989 5 26 6 9 NADINE 26.0 129.1 47 756 +1981 8 22 18 16 ERNESTO 13.8 10.1 69 607 +1957 7 23 6 20 MICHAEL 65.1 310.4 102 296 +1967 12 16 0 16 VALERIE 25.6 204.4 163 812 +1996 12 4 12 8 CHRIS 34.5 150.5 61 625 +1986 11 7 0 19 OSCAR 67.9 50.8 69 413 +1953 12 10 12 2 KIRK 39.1 81.6 56 694 +1953 1 5 12 13 TONY 62.0 229.6 138 476 +1957 6 23 0 18 MICHAEL 44.5 310.9 28 709 +1956 11 11 6 28 HELENE 69.4 172.5 56 458 +1971 11 28 6 13 MICHAEL 20.6 214.1 124 241 +1988 12 5 0 27 WILLIAM 39.3 173.8 110 126 +1967 3 23 18 19 VALERIE 45.8 155.8 122 832 +2002 2 7 6 26 LESLIE 13.1 91.9 145 321 +1994 11 19 12 15 PATTY 22.9 174.5 80 828 +1950 6 16 18 27 HELENE 70.0 70.2 10 805 +1980 7 23 6 2 VALERIE 63.2 248.9 159 500 +1957 3 25 12 6 NADINE 14.9 97.9 102 208 +1966 5 8 6 19 VALERIE 40.3 45.7 116 874 +1978 12 11 18 16 NADINE 69.3 207.8 51 164 +1979 2 11 6 8 WILLIAM 28.0 273.4 68 733 +1967 2 14 6 19 PATTY 35.6 183.0 128 420 +1961 11 13 6 15 GORDON 27.2 146.9 91 899 +1992 6 17 12 2 CHRIS 47.5 317.2 120 869 +1970 6 18 18 24 ERNESTO 8.3 109.4 160 359 +1994 6 2 6 2 LESLIE 17.5 56.4 64 743 +1953 4 1 12 17 OSCAR 21.1 294.3 87 435 +1998 5 22 6 20 BERYL 35.4 176.8 95 836 +1968 12 13 6 17 MICHAEL 64.4 116.8 161 778 +1961 10 10 0 6 TONY 11.7 1.6 159 474 +1985 1 12 0 3 KIRK 65.3 268.0 66 438 +1994 5 2 18 23 KIRK 44.7 142.6 80 173 +1992 10 12 0 27 ALBERTO 42.6 76.0 155 0 +1962 10 3 6 3 DEBBY 38.0 322.9 116 16 +1976 12 3 0 3 JOYCE 40.8 114.0 126 120 +2002 2 10 0 12 KIRK 47.6 95.2 140 82 +1981 5 6 0 18 HELENE 24.7 233.0 106 68 +1993 12 4 6 20 WILLIAM 44.1 262.8 95 495 +1965 8 8 0 8 PATTY 26.6 268.5 13 534 +2003 10 16 6 25 BERYL 7.1 260.3 38 887 +1958 8 14 18 7 SANDY 27.1 299.1 108 834 +1950 7 24 12 18 NADINE 11.7 174.5 17 112 +1969 11 17 6 12 GORDON 65.6 176.3 144 258 +1957 10 22 6 4 FLORENCE 15.4 290.7 31 180 +1993 9 17 18 21 TONY 35.1 139.0 90 631 +1989 8 19 0 18 WILLIAM 63.9 160.7 116 173 +1987 5 12 12 24 LESLIE 50.5 357.9 66 176 +1969 9 2 18 21 LESLIE 10.9 141.4 45 652 +1992 8 8 12 4 RAFAEL 27.2 296.7 65 491 +1979 5 18 6 15 KIRK 38.4 208.0 66 499 +1963 12 24 12 4 WILLIAM 29.0 194.7 108 119 +1991 7 27 0 14 CHRIS 46.9 227.0 62 762 +1964 7 21 18 14 BERYL 50.6 6.6 94 147 +1994 1 27 12 6 RAFAEL 22.1 22.8 14 411 +1965 7 7 12 16 NADINE 57.7 45.2 122 686 +1980 5 7 6 23 GORDON 67.9 32.8 62 537 +1965 8 27 6 23 HELENE 69.5 302.4 21 226 +1972 11 26 18 11 BERYL 14.1 260.9 151 498 +1987 9 19 18 24 HELENE 11.3 213.7 114 749 +1952 1 19 12 1 BERYL 12.0 299.7 156 877 +1962 12 22 12 24 RAFAEL 25.7 86.4 90 653 +1973 11 24 18 6 BERYL 32.5 25.6 75 267 +1964 8 2 12 17 MICHAEL 42.8 79.7 161 854 +1996 1 21 0 4 LESLIE 56.4 89.4 86 338 +1985 3 4 6 22 ERNESTO 12.1 199.4 42 806 +1952 2 17 0 19 DEBBY 57.0 113.0 126 336 +2004 10 4 12 26 ERNESTO 26.1 199.6 139 220 +1980 10 13 0 20 VALERIE 31.9 202.0 25 446 +1983 9 19 18 16 PATTY 47.5 343.2 121 832 +1952 1 16 12 21 SANDY 24.3 270.7 84 505 +1986 7 15 12 22 NADINE 34.6 146.9 48 835 +1952 2 20 18 16 CHRIS 47.3 264.2 117 779 +1967 1 19 6 4 TONY 68.2 351.9 55 538 +1997 4 2 6 10 BERYL 22.5 11.4 164 217 +1977 12 8 0 11 KIRK 47.6 296.0 132 572 +1990 5 14 6 6 CHRIS 29.9 38.3 32 234 +1981 4 16 12 4 RAFAEL 20.1 307.4 99 89 +1996 2 15 0 28 MICHAEL 25.9 83.3 58 742 +1993 5 6 18 22 FLORENCE 11.8 118.4 71 267 +1999 9 5 0 28 KIRK 49.0 136.9 32 369 +1990 8 18 6 25 PATTY 68.1 78.3 26 700 +1976 8 19 6 20 GORDON 58.3 336.9 101 391 +1972 6 7 0 22 CHRIS 64.2 208.8 32 817 +1980 8 5 18 5 ERNESTO 35.5 303.3 157 304 +1952 1 17 6 25 ISAAC 42.6 226.6 20 591 +1966 6 10 6 25 SANDY 24.0 52.7 121 757 +1973 9 16 6 19 JOYCE 48.0 118.4 34 791 +1960 11 22 6 18 MICHAEL 59.3 105.7 161 501 +1993 11 15 18 6 ISAAC 24.0 131.0 27 381 +1994 10 25 0 16 CHRIS 56.8 251.9 51 301 +1964 9 24 18 15 VALERIE 45.3 10.1 84 895 +1963 2 21 6 13 OSCAR 66.8 322.1 109 536 +1959 7 19 18 8 LESLIE 11.3 196.6 61 284 +1972 5 6 6 12 RAFAEL 14.1 334.4 42 239 +1964 9 18 6 8 CHRIS 59.1 99.2 110 638 +1955 8 20 18 20 NADINE 19.0 254.4 160 427 +1996 9 18 0 6 RAFAEL 42.5 14.5 64 339 +1972 9 7 0 12 DEBBY 18.8 117.2 21 430 +1983 1 2 12 25 WILLIAM 30.1 7.3 122 131 +1972 3 10 12 16 ALBERTO 22.6 24.1 15 235 +1956 1 9 18 20 VALERIE 11.7 197.9 111 217 +1996 5 17 6 24 GORDON 19.9 271.2 57 857 +1993 1 7 6 20 WILLIAM 10.8 132.9 141 447 +1982 4 9 18 18 HELENE 23.9 271.1 39 422 +1982 7 24 6 8 ISAAC 66.5 68.0 16 817 +1981 2 5 18 19 TONY 41.9 24.6 80 290 +2003 5 4 6 17 ALBERTO 37.0 247.5 141 546 +1985 4 23 0 4 LESLIE 42.5 148.8 36 115 +1999 5 24 18 4 HELENE 48.8 55.2 145 391 +1989 6 12 0 21 CHRIS 24.9 161.4 111 554 +1953 4 6 0 5 SANDY 28.3 131.1 25 126 +1995 1 16 0 22 KIRK 55.8 288.0 76 49 +1985 6 16 18 7 CHRIS 24.2 135.9 155 380 +1990 5 12 6 4 RAFAEL 18.1 333.5 61 376 +1989 10 11 6 1 VALERIE 68.6 167.5 123 441 +1997 11 3 6 6 ALBERTO 37.4 202.8 72 423 +1997 9 25 12 8 KIRK 7.1 238.6 75 230 +1965 3 20 6 17 ISAAC 50.3 131.7 126 274 +1983 2 18 6 27 SANDY 47.0 120.7 79 241 +1979 7 1 0 4 NADINE 19.8 121.1 41 543 +1970 7 26 6 16 PATTY 22.3 49.3 25 627 +1971 7 6 0 4 TONY 49.4 307.1 28 323 +1995 9 10 6 6 TONY 60.3 338.8 38 233 +1953 12 2 18 16 KIRK 16.8 93.5 84 5 +1993 12 27 0 2 GORDON 38.7 146.0 58 117 +1984 10 4 18 12 ISAAC 45.3 288.1 75 325 +1970 12 4 18 4 CHRIS 42.0 320.0 136 468 +1988 9 25 12 22 DEBBY 28.5 242.3 148 721 +1980 3 3 0 22 PATTY 54.2 104.4 72 778 +1959 10 7 6 21 GORDON 17.8 218.8 31 593 +1985 2 24 6 13 SANDY 59.9 52.0 73 660 +2001 2 3 12 23 RAFAEL 12.8 267.4 50 609 +1996 11 25 12 17 JOYCE 67.4 114.4 106 662 +1990 3 18 12 12 BERYL 11.3 178.8 10 557 +1963 3 26 12 10 SANDY 19.3 178.4 46 844 +1956 10 16 12 5 ERNESTO 31.9 314.3 28 211 +2000 8 19 12 12 ALBERTO 33.1 166.6 75 59 +1990 10 23 12 2 FLORENCE 35.7 44.7 159 54 +1957 2 6 6 24 PATTY 38.5 335.3 18 488 +1995 1 25 6 5 BERYL 14.6 330.5 61 841 +1974 4 15 6 18 LESLIE 29.2 119.8 38 363 +1969 8 19 18 3 MICHAEL 38.2 221.7 122 311 +1990 7 10 12 6 TONY 42.9 289.5 97 370 +1957 5 21 0 25 PATTY 42.8 281.2 161 849 +1977 1 8 18 17 FLORENCE 67.9 100.6 16 761 +1963 6 2 6 4 NADINE 22.4 254.6 40 314 +1983 7 1 18 28 BERYL 52.0 357.7 14 602 +1980 1 14 6 4 LESLIE 32.7 349.3 153 346 +1975 10 3 18 27 NADINE 34.9 142.5 37 155 +1957 2 16 18 6 MICHAEL 60.0 332.6 16 865 +1960 10 22 0 13 ISAAC 67.4 266.0 40 542 +1953 2 5 12 3 ISAAC 53.3 25.7 90 756 +1960 2 7 0 16 LESLIE 9.4 232.4 58 222 +1961 5 20 18 22 PATTY 17.9 228.2 102 586 +1984 9 19 12 10 ISAAC 60.6 292.6 107 846 +1981 11 7 18 18 MICHAEL 39.4 309.6 161 788 +1990 9 21 18 27 PATTY 41.4 152.1 139 659 +2001 8 11 18 28 RAFAEL 50.6 210.3 52 874 +1954 3 11 18 27 ISAAC 46.1 297.2 18 32 +1961 8 23 18 3 GORDON 63.1 157.3 44 377 +1961 5 27 0 25 FLORENCE 11.1 128.8 140 219 +1974 7 18 12 23 WILLIAM 15.7 341.3 60 700 +1994 2 12 0 3 RAFAEL 67.3 221.2 139 239 +1989 1 4 12 5 HELENE 57.6 37.3 103 623 +1999 11 3 12 3 TONY 8.7 85.8 79 569 +1989 12 4 18 4 ALBERTO 9.4 173.3 53 13 +1984 10 19 12 20 DEBBY 33.5 200.4 144 566 +1953 10 9 0 24 BERYL 69.6 105.2 47 164 +1977 11 26 0 18 GORDON 28.6 352.1 34 161 +1982 6 19 12 1 BERYL 68.3 60.5 47 418 +1979 12 11 0 1 VALERIE 9.9 28.8 64 133 +1978 9 8 6 17 TONY 37.1 90.3 133 492 +2004 9 7 0 22 BERYL 9.2 106.5 21 494 +1995 9 18 6 11 PATTY 16.8 277.7 81 31 +1991 5 14 0 6 FLORENCE 16.8 112.2 88 35 +1996 9 27 6 13 MICHAEL 33.8 348.1 28 292 +1991 7 10 18 16 ALBERTO 19.5 183.9 66 572 +1980 6 4 0 5 ISAAC 26.0 312.7 53 850 +1986 8 13 6 13 ERNESTO 59.7 350.1 89 729 +1975 7 18 6 24 CHRIS 19.7 259.9 126 580 +1976 5 28 0 18 ERNESTO 31.5 32.5 38 274 +1987 9 15 6 7 CHRIS 15.4 282.7 65 551 +1982 3 13 6 28 JOYCE 53.3 193.4 112 179 +1970 4 13 12 23 JOYCE 65.5 334.6 74 389 +1952 10 10 6 6 KIRK 33.5 54.1 131 47 +1959 11 21 0 7 RAFAEL 38.1 117.9 107 539 +1996 5 6 0 20 MICHAEL 20.8 350.9 163 829 +1970 8 1 6 21 SANDY 25.2 313.5 59 389 +1986 8 16 18 20 DEBBY 41.2 206.7 95 695 +1966 12 5 0 22 JOYCE 19.3 197.2 150 305 +1996 8 26 12 1 WILLIAM 32.7 334.3 77 35 +1974 2 25 12 18 MICHAEL 42.9 65.4 107 30 +1955 7 1 6 21 NADINE 18.2 179.2 45 823 +1989 10 19 6 25 OSCAR 67.1 326.6 37 400 +1975 8 6 0 10 JOYCE 24.5 12.2 33 189 +2000 1 9 6 13 DEBBY 37.2 313.4 14 755 +1989 7 22 18 12 JOYCE 68.6 95.6 69 670 +1985 1 4 12 16 CHRIS 58.5 222.9 141 802 +1962 9 15 6 25 SANDY 30.3 47.0 12 65 +1993 3 24 6 7 FLORENCE 31.9 129.2 103 173 +2003 11 4 18 23 NADINE 29.6 117.9 16 83 +1969 10 12 6 12 HELENE 55.5 283.8 101 156 +1995 1 1 0 5 WILLIAM 32.6 202.6 77 720 +1997 6 14 6 21 ALBERTO 44.3 310.2 63 795 +1989 5 23 0 22 ERNESTO 15.7 247.3 10 123 +1974 10 5 12 22 DEBBY 47.3 331.6 101 229 +1996 6 6 12 14 FLORENCE 63.2 241.2 67 472 +1994 2 1 6 27 FLORENCE 27.6 126.0 164 6 +1960 1 7 6 5 FLORENCE 29.5 6.6 163 454 +1951 8 19 12 19 SANDY 32.3 283.1 113 351 +1971 6 23 6 2 LESLIE 27.6 230.5 110 769 +1985 2 1 6 10 LESLIE 13.0 6.4 74 467 +1999 5 28 12 16 BERYL 59.2 277.0 10 724 +1970 12 22 0 6 MICHAEL 51.3 101.8 82 58 +1998 6 15 18 24 SANDY 47.6 336.3 99 868 +1990 12 24 6 12 WILLIAM 12.2 46.3 79 739 +1954 6 18 0 12 RAFAEL 10.5 117.7 87 344 +1969 5 9 0 11 NADINE 39.2 139.4 139 705 +2001 9 25 6 24 PATTY 7.8 232.7 34 305 +1980 9 8 12 1 KIRK 36.6 286.1 139 550 +1993 6 12 6 13 JOYCE 59.2 106.0 122 349 +1967 5 12 6 19 ALBERTO 63.0 199.8 122 105 +1977 4 2 12 22 WILLIAM 69.8 72.8 160 275 +1956 6 7 0 9 GORDON 41.8 304.8 139 348 +1965 8 28 12 10 FLORENCE 37.1 135.4 142 664 +1995 3 18 0 16 ISAAC 38.1 221.7 50 393 +1983 8 25 12 1 PATTY 23.6 191.5 118 770 +1977 8 10 12 1 LESLIE 39.2 321.8 154 744 +1986 11 22 6 20 GORDON 10.5 109.4 63 767 +1992 4 17 6 22 ALBERTO 30.9 174.5 135 828 +1991 5 15 18 25 PATTY 16.5 132.9 140 518 +2001 12 2 18 3 GORDON 39.5 47.7 51 775 +1976 7 24 18 19 CHRIS 40.4 27.1 53 422 +1972 4 19 0 21 GORDON 58.0 135.3 146 517 +1994 4 24 18 3 JOYCE 54.3 74.6 62 454 +1993 1 4 18 15 NADINE 33.2 62.8 50 767 +1954 8 1 18 7 WILLIAM 21.3 185.5 100 445 +1962 6 24 18 23 ALBERTO 15.1 194.0 60 286 +1979 2 23 12 18 ERNESTO 59.4 2.5 63 212 +1972 10 17 6 27 FLORENCE 42.2 68.5 35 426 +1978 11 19 12 16 PATTY 63.2 247.9 27 868 +1978 8 6 0 6 LESLIE 36.3 305.8 143 581 +1999 12 15 6 10 MICHAEL 47.4 177.7 131 532 +1951 12 1 18 27 HELENE 53.3 95.4 103 486 +1988 7 2 6 5 OSCAR 29.3 284.0 82 575 +1989 11 11 18 10 CHRIS 63.0 37.1 123 582 +1995 1 4 18 10 TONY 34.6 63.9 164 203 +1993 11 5 18 11 HELENE 61.1 89.5 129 374 +1978 9 16 0 5 KIRK 16.8 325.1 14 686 +1991 12 6 6 24 GORDON 55.9 133.9 55 681 +1985 2 10 18 15 ISAAC 62.2 143.4 16 281 +1961 7 12 12 20 ERNESTO 59.5 118.7 37 451 +1978 11 5 6 7 ERNESTO 29.0 285.2 136 87 +1985 7 7 18 24 VALERIE 46.0 204.0 136 519 +1970 4 21 6 10 BERYL 41.7 237.9 64 356 +1963 8 18 6 28 NADINE 47.9 230.0 32 842 +1956 1 8 18 9 GORDON 45.5 343.0 142 894 +2000 9 27 18 22 PATTY 55.1 140.1 110 82 +1989 4 8 6 3 WILLIAM 54.8 161.7 128 584 +1964 1 18 12 4 ISAAC 50.0 40.9 140 549 +1980 9 24 0 1 SANDY 49.9 29.1 116 71 +1971 1 6 0 20 LESLIE 63.2 60.0 136 174 +1971 12 20 12 3 FLORENCE 49.1 313.9 125 168 +1953 8 3 12 26 ISAAC 57.1 252.7 56 445 +1950 10 2 6 16 NADINE 28.1 207.4 64 666 +1969 8 23 6 11 GORDON 23.4 314.0 151 732 +1972 9 26 6 28 CHRIS 60.3 194.3 59 863 +1956 8 1 18 18 TONY 62.5 223.8 58 866 +1961 3 2 12 15 ERNESTO 69.2 107.9 22 199 +1958 5 18 18 1 HELENE 30.7 123.7 141 9 +1987 2 13 18 14 OSCAR 61.2 190.5 130 122 +1968 7 4 6 23 CHRIS 38.9 160.8 46 102 +1987 4 28 6 24 HELENE 15.3 154.6 154 606 +1984 11 20 0 22 JOYCE 12.9 12.8 118 522 +1985 10 16 12 3 BERYL 45.2 27.1 102 718 +1997 1 10 18 12 TONY 13.9 125.7 91 570 +1998 4 18 18 27 RAFAEL 28.5 38.0 51 693 +1977 9 26 0 25 ERNESTO 67.3 100.1 85 779 +1998 3 20 18 7 LESLIE 47.9 49.4 47 309 +1951 6 20 12 15 LESLIE 36.6 330.0 103 812 +1998 12 15 0 24 GORDON 29.7 278.3 154 865 +1997 7 23 18 26 DEBBY 23.3 299.7 31 210 +1998 4 18 18 13 LESLIE 49.7 302.5 43 239 +1979 2 10 0 17 TONY 7.8 210.2 24 433 +1961 4 15 6 8 HELENE 8.2 269.7 33 485 +1953 11 14 12 21 SANDY 50.9 153.5 144 264 +1996 1 21 6 20 DEBBY 27.7 272.1 98 654 +1990 6 18 0 18 ERNESTO 54.2 3.8 16 133 +1986 5 20 6 24 ALBERTO 36.5 230.5 161 433 +1998 1 7 12 3 JOYCE 9.6 143.7 102 595 +1950 8 19 12 27 ERNESTO 47.3 160.3 150 195 +1987 11 4 18 12 CHRIS 63.1 207.5 155 891 +1979 3 14 6 28 OSCAR 37.5 288.5 37 717 +1960 4 26 0 19 TONY 62.9 228.4 159 299 +1961 5 11 6 9 OSCAR 58.5 99.4 25 601 +1955 7 14 18 18 GORDON 39.4 129.2 56 870 +1996 1 7 18 20 ERNESTO 50.9 234.4 161 650 +1964 10 23 6 24 ISAAC 14.3 23.0 159 410 +1993 1 12 0 3 ISAAC 58.5 301.9 63 94 +1960 4 10 18 21 JOYCE 60.3 103.9 120 527 +1978 9 8 0 17 DEBBY 55.1 218.1 70 742 +1950 3 12 6 3 GORDON 37.1 164.8 123 820 +1967 10 1 12 13 GORDON 28.5 257.8 59 605 +1974 8 23 0 26 ALBERTO 13.2 167.5 39 395 +1978 4 4 12 17 ISAAC 26.2 74.6 104 684 +1983 12 25 6 5 OSCAR 18.5 177.5 129 148 +1994 4 15 0 2 ERNESTO 68.7 237.8 134 101 +2002 2 13 12 20 LESLIE 41.6 174.6 47 616 +1955 9 14 12 10 ERNESTO 32.2 271.2 51 783 +1985 6 12 18 17 VALERIE 54.3 14.6 37 818 +1963 9 2 12 28 MICHAEL 66.4 246.8 113 555 +1991 11 9 18 4 DEBBY 60.7 236.2 39 398 +1981 2 10 6 23 DEBBY 52.8 139.8 58 395 +1954 6 14 12 6 VALERIE 38.1 258.8 96 259 +1965 6 10 0 24 SANDY 15.8 275.8 103 241 +1980 8 26 18 21 CHRIS 33.0 341.4 20 691 +1969 4 3 12 9 RAFAEL 26.4 27.7 37 614 +1961 11 13 0 8 ERNESTO 38.1 8.8 13 30 +1985 12 11 0 4 FLORENCE 59.6 310.5 30 327 +2004 5 19 12 7 PATTY 25.9 192.7 123 683 +1992 9 6 12 20 LESLIE 57.1 166.7 95 41 +1996 7 15 6 21 HELENE 12.5 118.7 146 283 +1951 4 23 18 16 ERNESTO 12.7 150.0 77 285 +1954 8 24 6 3 GORDON 66.5 243.1 92 317 +1986 6 18 12 28 FLORENCE 34.2 93.5 38 106 +1968 2 23 6 26 RAFAEL 41.9 223.4 61 285 +1962 1 26 6 14 TONY 58.1 350.1 164 320 +1962 11 8 18 6 PATTY 12.4 242.5 160 43 +1991 2 28 18 4 HELENE 42.5 246.0 140 771 +1954 1 27 6 13 GORDON 23.1 15.6 109 598 +1972 3 8 0 11 ISAAC 68.0 352.2 104 341 +1950 6 14 6 16 WILLIAM 32.9 236.2 100 786 +1957 10 24 12 14 JOYCE 64.5 231.0 50 617 +1999 3 20 18 26 ERNESTO 14.3 14.5 27 705 +1999 12 6 12 19 TONY 30.6 33.8 11 324 +1985 11 8 12 15 MICHAEL 56.4 47.5 30 698 +1985 12 9 12 26 CHRIS 20.1 260.5 123 132 +2001 1 1 6 17 ISAAC 7.5 40.0 61 6 +1985 3 10 6 10 DEBBY 43.6 351.2 161 721 +1958 8 3 6 13 LESLIE 48.8 216.5 60 338 +1963 11 11 0 13 VALERIE 13.8 188.1 111 495 +1993 9 5 18 17 OSCAR 17.5 151.6 21 644 +1987 10 16 18 15 OSCAR 7.1 250.9 75 298 +1995 1 11 12 13 WILLIAM 28.4 165.7 62 367 +1964 1 11 6 12 ERNESTO 19.9 9.0 163 757 +1992 5 8 12 28 TONY 58.7 280.0 41 282 +1977 11 11 0 5 VALERIE 25.9 95.9 160 134 +1997 6 24 12 19 LESLIE 16.1 307.3 56 806 +1959 5 26 0 7 FLORENCE 48.3 97.2 126 121 +2003 8 21 12 2 OSCAR 7.2 291.9 38 619 +1960 11 2 6 1 RAFAEL 55.6 183.5 150 99 +1978 3 27 6 4 FLORENCE 10.6 267.8 87 55 +2003 3 13 0 7 KIRK 41.5 243.7 105 313 +1982 3 9 0 8 DEBBY 30.8 85.1 118 204 +1986 8 24 6 6 ISAAC 58.6 200.2 148 44 +1969 12 25 0 17 BERYL 8.9 14.7 101 48 +1951 11 12 12 25 WILLIAM 11.0 323.1 75 744 +1998 11 21 0 12 BERYL 10.9 278.8 102 72 +1961 1 20 18 23 ALBERTO 43.5 207.5 44 273 +1962 1 23 12 7 GORDON 21.3 188.5 134 597 +1980 9 13 18 26 RAFAEL 39.8 93.7 97 785 +1981 8 5 18 7 DEBBY 34.7 100.2 138 865 +1997 6 6 6 25 CHRIS 27.5 238.8 52 503 +1977 12 24 6 28 BERYL 30.3 270.7 124 480 +1965 1 6 18 4 FLORENCE 49.1 119.5 150 498 +2002 6 7 12 4 VALERIE 60.0 99.4 75 368 +1956 9 10 12 4 JOYCE 45.5 103.2 86 60 +1995 9 23 6 15 TONY 18.1 267.4 138 829 +1989 12 19 18 25 LESLIE 38.9 286.4 105 820 +1951 3 21 18 22 TONY 14.3 175.7 37 607 +1991 6 3 18 27 WILLIAM 51.7 350.4 71 414 +1956 8 16 18 1 BERYL 29.8 285.6 69 486 +1957 1 16 6 6 DEBBY 8.8 340.7 16 0 +1995 12 26 18 11 LESLIE 52.2 182.3 61 152 +1999 7 19 6 23 HELENE 21.7 150.4 132 320 +1992 8 4 18 3 TONY 19.9 124.5 49 852 +1975 6 25 12 23 SANDY 39.2 86.1 42 760 +1979 9 19 12 17 SANDY 54.4 225.8 93 307 +1985 1 19 12 22 OSCAR 30.4 42.3 28 525 +1972 10 13 6 19 ALBERTO 29.4 49.6 53 273 +1992 10 7 12 12 DEBBY 60.9 35.6 131 548 +2002 12 1 0 22 PATTY 58.1 121.4 87 209 +1981 7 15 12 3 JOYCE 61.3 211.1 134 226 +1978 9 26 18 25 PATTY 14.5 155.6 44 735 +1995 3 12 0 16 BERYL 42.4 294.8 119 49 +1953 8 18 6 25 WILLIAM 8.6 283.4 86 171 +1951 12 6 6 19 GORDON 16.1 55.2 98 280 +1968 11 10 12 27 VALERIE 31.4 304.7 146 316 +1960 6 18 18 28 NADINE 63.2 329.9 49 346 +1997 2 23 18 13 LESLIE 39.1 26.2 11 646 +1989 10 27 12 6 MICHAEL 58.8 98.0 103 824 +1958 7 16 18 22 RAFAEL 54.9 61.1 62 709 +1989 3 2 12 28 LESLIE 31.1 28.1 130 465 +1955 6 7 6 14 CHRIS 35.9 61.4 91 661 +1991 7 9 12 22 FLORENCE 54.6 118.0 58 164 +1959 12 18 6 23 KIRK 52.4 259.3 20 430 +1959 5 24 6 18 OSCAR 35.5 250.6 30 3 +1979 5 12 18 14 BERYL 52.7 200.3 47 590 +1951 6 5 6 6 CHRIS 9.6 190.2 77 605 +1955 4 21 6 27 BERYL 26.4 124.1 131 97 +1953 11 16 6 7 TONY 65.6 336.9 126 880 +1952 5 8 18 16 HELENE 37.9 286.3 139 374 +2000 6 28 12 18 ALBERTO 54.8 69.1 11 871 +1995 12 11 12 20 OSCAR 64.9 258.5 133 309 +1998 8 17 12 17 GORDON 29.2 9.0 60 572 +1960 8 23 18 10 LESLIE 12.3 57.4 12 876 +1966 7 11 6 21 NADINE 64.8 107.5 21 543 +1975 7 6 12 15 LESLIE 14.4 15.8 22 581 +1981 4 27 0 25 BERYL 62.7 9.1 115 757 +2004 12 13 12 11 OSCAR 40.7 250.8 16 423 +1989 4 25 18 17 ERNESTO 49.3 252.4 36 804 +1954 8 17 12 22 DEBBY 61.5 241.8 26 185 +1987 6 24 12 13 ISAAC 31.9 57.7 97 671 +1966 11 15 12 10 PATTY 47.5 249.0 58 489 +1988 4 11 12 20 CHRIS 61.2 200.4 114 450 +1972 10 18 12 12 CHRIS 17.9 354.9 86 819 +1963 10 6 0 25 SANDY 27.1 299.3 113 268 +1983 6 19 18 14 ALBERTO 67.9 173.2 117 690 +1966 5 4 6 17 JOYCE 57.6 128.4 98 484 +1968 12 12 0 16 LESLIE 31.5 308.9 123 183 +1956 1 20 0 27 JOYCE 56.3 157.1 41 871 +1958 3 8 6 1 ERNESTO 40.6 151.8 56 526 +1964 6 27 12 13 ISAAC 28.3 297.9 138 36 +1960 6 22 12 20 SANDY 52.5 305.4 131 338 +1991 7 3 6 7 NADINE 26.7 50.5 43 776 +1953 4 11 6 1 VALERIE 27.7 5.9 112 752 +1965 12 2 12 9 OSCAR 26.3 47.4 47 371 +1971 7 7 6 1 CHRIS 51.2 149.9 102 515 +1979 7 3 0 9 MICHAEL 22.7 124.2 82 144 +2002 1 27 6 23 MICHAEL 43.7 224.1 46 516 +1980 3 21 12 14 WILLIAM 39.1 208.0 106 635 +1973 3 25 0 5 LESLIE 31.2 222.5 14 250 +1994 8 3 6 28 RAFAEL 60.4 66.0 59 894 +1957 3 12 18 23 FLORENCE 40.3 267.2 63 607 +2002 5 9 18 5 BERYL 54.0 198.2 70 365 +1964 12 25 12 14 ALBERTO 29.6 103.1 137 270 +1993 11 18 18 6 JOYCE 38.2 71.3 69 889 +1986 6 27 0 5 FLORENCE 14.9 173.0 140 437 +1978 2 19 12 2 ERNESTO 35.7 198.4 20 358 +1991 11 19 18 18 FLORENCE 15.4 221.4 105 867 +1995 11 27 6 9 PATTY 30.3 10.1 102 689 +1970 7 27 18 28 TONY 32.2 47.4 71 6 +1992 9 11 0 3 DEBBY 46.0 128.9 133 780 +1990 5 28 6 22 KIRK 14.3 188.0 46 874 +1976 4 4 6 16 WILLIAM 34.6 304.3 101 503 +1973 2 24 18 12 CHRIS 48.0 146.5 87 211 +1951 1 3 6 3 RAFAEL 30.4 231.0 136 31 +1960 3 5 18 13 ERNESTO 59.4 276.1 89 89 +1962 7 14 6 22 LESLIE 56.6 5.2 24 113 +1999 2 12 0 13 FLORENCE 45.5 224.0 55 176 +1977 10 13 18 20 TONY 46.4 99.9 160 138 +1996 1 11 12 28 ERNESTO 18.5 337.3 154 393 +1988 5 1 6 17 WILLIAM 55.0 251.8 32 794 +1956 9 2 12 14 BERYL 14.4 189.7 46 53 +1988 11 5 0 14 VALERIE 57.5 251.0 34 844 +2003 1 26 18 26 MICHAEL 21.0 345.9 83 762 +1959 1 20 6 4 JOYCE 58.5 44.4 46 553 +1988 4 12 18 1 BERYL 39.9 53.0 81 147 +1977 5 18 0 16 TONY 30.4 309.4 147 517 +1999 6 12 0 17 VALERIE 49.8 271.2 61 862 +1969 7 19 0 21 SANDY 29.7 343.9 38 652 +1997 7 16 12 9 SANDY 20.5 254.7 33 20 +1982 4 12 12 21 NADINE 65.9 188.6 146 72 +1984 6 20 6 2 WILLIAM 35.0 185.0 139 425 +1997 9 3 18 12 GORDON 46.8 294.1 47 78 +1973 8 17 18 27 BERYL 22.7 116.2 105 294 +1992 9 17 12 21 OSCAR 42.0 140.3 79 589 +1994 2 7 12 8 LESLIE 21.6 142.8 140 58 +1953 3 9 0 9 ERNESTO 32.2 54.6 109 643 +1995 8 7 12 1 CHRIS 61.9 308.1 14 646 +1996 9 26 18 22 GORDON 18.1 71.6 162 662 +1988 1 28 18 8 ISAAC 28.4 226.1 126 342 +1983 3 28 0 1 SANDY 24.8 171.3 131 852 +1980 5 26 0 19 WILLIAM 51.2 304.4 164 193 +1974 1 6 12 5 SANDY 12.0 47.0 138 89 +1959 9 13 12 24 HELENE 62.3 347.2 33 857 +1950 8 13 0 18 SANDY 44.4 354.4 19 475 +1967 2 2 18 10 ERNESTO 16.1 69.3 151 662 +1979 3 20 6 18 ALBERTO 46.5 330.6 127 65 +1990 3 24 0 18 ERNESTO 23.7 224.6 110 485 +1994 11 23 12 11 NADINE 31.2 139.0 53 557 +1965 6 22 6 25 MICHAEL 11.3 77.3 123 140 +1999 11 12 6 16 HELENE 42.1 159.8 163 701 +1993 10 22 18 6 ISAAC 49.1 328.9 80 377 +1986 4 28 6 10 BERYL 11.5 267.2 44 12 +1975 10 3 0 27 JOYCE 47.3 135.7 142 526 +1966 10 2 18 19 TONY 51.8 144.2 136 249 +1962 9 8 18 13 FLORENCE 15.9 223.7 131 622 +1978 9 8 12 4 NADINE 68.6 315.6 140 131 +1984 1 9 12 5 KIRK 65.5 249.3 127 319 +1972 9 18 0 26 JOYCE 66.1 84.6 97 683 +1986 6 9 12 27 TONY 41.6 239.2 17 557 +1997 4 28 0 26 DEBBY 49.7 176.2 37 302 +1987 1 13 6 14 GORDON 32.9 112.1 10 820 +1965 4 14 18 3 SANDY 27.9 238.2 126 369 +1985 1 16 6 26 FLORENCE 19.8 31.5 36 759 +1974 6 19 18 23 BERYL 31.7 1.7 133 461 +1979 1 9 12 18 TONY 18.9 66.4 132 574 +1963 12 26 12 16 DEBBY 8.2 184.1 129 656 +1984 3 9 6 12 LESLIE 35.9 168.9 46 769 +1981 12 20 0 23 GORDON 55.7 228.0 12 57 +1960 6 22 18 13 ALBERTO 34.3 26.3 90 462 +1986 8 20 0 7 FLORENCE 19.4 238.7 64 624 +1965 4 3 12 19 LESLIE 22.0 90.0 136 809 +1960 10 9 18 2 ERNESTO 25.8 41.3 92 717 +1961 9 20 6 26 JOYCE 50.0 210.8 68 130 +1986 5 14 18 25 ERNESTO 43.5 201.9 53 606 +1985 2 1 0 10 KIRK 52.4 156.0 147 379 +1980 9 10 6 25 JOYCE 10.3 188.8 133 510 +1965 4 4 12 24 DEBBY 28.5 78.5 110 470 +1975 4 24 0 25 BERYL 59.5 41.4 68 549 +1974 4 13 6 1 ERNESTO 54.5 50.4 134 505 +1997 1 11 18 1 ERNESTO 42.8 38.8 143 250 +2003 12 24 18 18 NADINE 67.9 143.4 55 782 +2000 3 4 12 2 SANDY 32.3 83.7 67 647 +1981 2 11 18 7 OSCAR 25.2 237.1 116 378 +1967 1 20 0 27 LESLIE 36.0 97.2 92 544 +2001 2 18 0 8 KIRK 52.3 274.6 83 340 +1961 1 17 6 25 OSCAR 15.3 260.5 97 742 +1975 3 18 18 17 BERYL 14.2 199.1 107 178 +1952 6 7 0 28 ISAAC 18.6 2.0 146 621 +1993 5 6 6 8 VALERIE 43.9 243.7 153 188 +1985 7 10 12 11 JOYCE 47.8 350.9 62 599 +1976 9 3 0 6 TONY 49.6 53.2 68 30 +1984 9 23 18 2 JOYCE 19.7 138.4 156 545 +1982 11 22 18 5 MICHAEL 43.8 127.6 158 415 +1998 5 2 12 16 WILLIAM 23.7 119.6 70 674 +1968 5 7 6 10 SANDY 42.5 322.8 67 378 +1981 3 6 12 20 TONY 48.0 177.4 85 584 +1974 1 7 6 8 OSCAR 14.6 144.0 90 137 +1966 7 3 6 6 ERNESTO 40.1 334.9 30 559 +1971 10 18 18 20 ISAAC 12.0 212.9 112 213 +1990 6 8 12 20 WILLIAM 33.9 18.6 143 866 +1984 1 25 0 2 BERYL 14.6 141.4 101 796 +1991 6 21 0 4 OSCAR 22.5 114.8 27 373 +1972 3 5 18 24 GORDON 27.9 342.9 15 277 +1985 11 22 12 28 JOYCE 42.5 119.2 11 792 +1976 1 13 12 1 JOYCE 37.8 135.9 44 64 +2003 5 24 18 23 ERNESTO 7.3 255.4 126 548 +1993 6 15 12 5 FLORENCE 41.1 219.6 110 597 +1968 10 10 18 26 KIRK 20.8 68.2 144 702 +2004 6 23 12 20 ISAAC 30.3 37.6 135 401 +1995 10 10 18 21 TONY 33.4 108.3 49 465 +1987 6 15 12 5 ALBERTO 15.9 287.9 30 582 +1985 4 19 0 21 PATTY 66.2 201.7 109 611 +2004 12 27 6 26 HELENE 43.5 88.9 64 768 +1985 8 23 12 11 OSCAR 63.2 157.8 47 161 +1957 11 9 18 9 KIRK 70.0 88.6 91 500 +1952 6 16 0 23 KIRK 17.2 334.4 40 614 +1996 4 28 12 3 ISAAC 37.3 72.2 134 346 +1952 8 12 6 25 NADINE 40.3 239.3 54 150 +2002 6 16 18 1 GORDON 15.1 242.3 161 632 +1957 12 19 0 8 MICHAEL 19.7 229.3 48 63 +1996 2 12 18 27 WILLIAM 40.2 23.9 17 77 +1973 6 24 12 19 ERNESTO 34.2 83.7 14 40 +1987 11 27 0 1 HELENE 63.4 313.4 111 497 +1956 2 22 12 7 ERNESTO 66.8 274.1 31 320 +1967 12 12 18 26 ALBERTO 38.0 37.2 153 801 +1968 10 10 18 16 RAFAEL 64.4 269.4 104 823 +1985 4 2 0 7 KIRK 40.6 177.4 108 666 +1968 11 17 0 17 LESLIE 65.8 267.5 62 630 +1989 4 4 0 1 VALERIE 58.0 183.2 127 491 +1951 9 19 0 17 DEBBY 49.9 25.8 125 563 +1956 9 8 6 23 MICHAEL 12.2 307.8 98 333 +1977 1 9 12 6 CHRIS 62.6 144.1 110 584 +1987 4 24 18 12 PATTY 49.4 234.7 70 368 +1961 3 5 0 2 DEBBY 31.6 99.7 76 606 +1991 10 11 12 6 PATTY 13.3 242.8 87 797 +1993 4 15 6 18 LESLIE 57.2 15.6 20 544 +1992 4 16 0 2 SANDY 20.6 191.4 159 106 +1981 10 16 0 23 RAFAEL 62.9 328.9 95 889 +1981 6 22 18 12 SANDY 37.3 253.5 94 575 +1972 9 28 18 25 PATTY 67.3 184.1 27 61 +1987 5 16 6 17 PATTY 23.7 77.1 78 686 +1979 11 13 18 26 RAFAEL 13.8 310.3 113 18 +2000 4 26 6 28 JOYCE 38.3 56.9 96 376 +2002 4 25 18 8 KIRK 42.4 132.5 140 519 +1996 12 7 18 17 VALERIE 11.4 55.3 63 266 +1975 4 24 18 22 JOYCE 7.1 262.0 71 483 +1972 11 1 12 22 PATTY 17.6 159.6 43 552 +1971 8 28 12 15 ALBERTO 9.8 4.0 27 317 +1997 10 11 0 14 ISAAC 20.7 149.0 81 306 +1996 1 13 18 24 ERNESTO 61.2 199.1 48 795 +1981 2 14 18 17 ERNESTO 54.6 119.5 52 528 +1961 8 3 6 19 ISAAC 27.5 332.0 74 545 +1950 9 25 12 11 OSCAR 15.5 221.4 24 674 +1954 9 11 18 27 DEBBY 28.8 12.3 91 597 +1966 1 20 6 24 BERYL 16.5 80.5 154 38 +1987 9 9 6 15 OSCAR 14.1 93.3 59 731 +2001 3 27 18 21 NADINE 17.9 207.5 140 594 +1977 9 20 18 4 ALBERTO 47.1 321.7 76 580 +1992 4 12 18 13 FLORENCE 35.3 312.3 147 372 +1982 1 21 18 24 KIRK 53.1 344.4 93 474 +1989 11 6 18 25 CHRIS 36.5 154.3 158 388 +2002 8 2 0 1 GORDON 35.5 101.4 33 620 +1988 10 19 6 14 WILLIAM 42.3 342.8 39 506 +1996 7 1 6 26 DEBBY 15.9 138.7 21 85 +1955 2 26 12 7 ERNESTO 24.6 96.6 21 67 +1999 7 28 18 8 KIRK 32.9 140.3 97 517 +1979 1 19 12 8 KIRK 40.6 61.4 106 59 +1962 11 14 0 20 ALBERTO 9.4 64.9 96 89 +1957 9 27 6 14 LESLIE 42.9 244.9 162 259 +1962 10 21 6 7 MICHAEL 39.5 217.6 151 360 +1981 1 6 0 11 OSCAR 18.4 167.8 159 322 +1969 7 27 0 12 DEBBY 58.2 25.3 20 512 +1974 7 9 18 25 PATTY 29.7 167.8 53 107 +1987 2 15 12 22 PATTY 45.6 31.1 81 148 +1971 5 1 0 9 NADINE 10.9 24.8 77 457 +1982 11 20 18 16 GORDON 64.6 65.7 12 768 +1986 1 26 0 12 NADINE 55.7 107.7 88 175 +1993 8 6 0 9 ISAAC 50.4 101.1 18 396 +1951 8 18 12 5 HELENE 46.7 80.8 105 387 +1999 6 14 12 4 CHRIS 50.8 224.2 149 502 +1994 12 17 18 25 FLORENCE 47.5 213.6 53 637 +1976 9 10 6 2 JOYCE 42.6 301.9 50 678 +1956 12 18 18 26 OSCAR 18.6 301.8 53 807 +1978 12 15 0 17 WILLIAM 22.8 64.5 21 393 +1953 11 18 6 16 CHRIS 22.0 182.6 52 55 +1987 1 28 18 7 GORDON 19.9 185.7 107 653 +2001 5 23 18 4 FLORENCE 25.8 12.7 17 241 +1983 10 21 12 27 KIRK 63.8 321.4 98 253 +1966 4 23 0 16 LESLIE 23.4 226.0 55 540 +2004 7 14 6 1 JOYCE 47.2 172.5 37 750 +1995 10 21 0 15 NADINE 22.9 266.6 75 55 +1995 11 11 6 26 HELENE 48.2 216.0 63 842 +1973 12 8 6 22 SANDY 43.5 297.7 155 689 +1986 10 15 12 10 PATTY 39.5 181.2 152 350 +1982 8 27 12 6 KIRK 51.1 316.8 142 899 +1981 1 27 6 5 KIRK 56.4 297.8 37 524 +2000 4 10 0 16 WILLIAM 47.5 237.9 162 257 +2004 3 16 6 23 BERYL 51.5 121.0 157 312 +1996 8 11 0 20 RAFAEL 32.2 238.2 127 773 +2002 9 9 6 1 GORDON 17.5 128.6 162 43 +1966 6 8 0 17 PATTY 19.1 76.5 127 464 +1982 6 27 6 27 ALBERTO 35.6 19.4 41 254 +1986 4 22 6 5 BERYL 39.4 176.0 31 303 +1956 3 5 6 22 PATTY 58.3 344.4 115 736 +2003 12 25 12 3 LESLIE 67.1 16.6 81 497 +1993 2 11 18 10 SANDY 32.2 105.4 107 396 +1951 10 25 6 6 FLORENCE 24.2 217.2 30 851 +1995 10 4 0 20 VALERIE 11.3 109.4 107 567 +1959 9 10 18 11 NADINE 8.0 312.0 31 864 +1996 9 16 12 27 PATTY 43.4 95.5 150 505 +1953 11 13 12 7 NADINE 56.5 139.1 74 470 +1964 1 16 18 5 MICHAEL 26.9 70.3 87 336 +1989 3 26 0 16 DEBBY 38.2 253.8 38 559 +1994 1 14 0 16 MICHAEL 17.3 227.7 97 619 +1961 4 26 12 7 VALERIE 59.7 140.3 17 584 +1999 4 25 0 26 MICHAEL 40.2 260.3 140 175 +1995 2 4 12 16 GORDON 60.2 282.3 151 645 +1971 12 11 12 16 CHRIS 20.7 258.4 42 285 +1967 2 5 12 3 ERNESTO 67.8 46.4 34 824 +1968 7 20 12 22 SANDY 41.0 18.3 24 339 +1984 4 18 12 14 ISAAC 67.6 245.7 34 565 +1961 8 8 18 9 ERNESTO 25.7 129.3 45 330 +1956 11 2 0 25 NADINE 39.7 221.2 30 55 +1995 6 23 18 22 WILLIAM 27.2 39.9 98 619 +1965 12 24 18 15 GORDON 46.4 114.0 44 283 +1986 11 3 18 20 PATTY 44.3 76.9 46 857 +1961 7 14 0 23 RAFAEL 42.7 261.2 100 37 +1991 7 4 18 2 HELENE 31.5 34.6 17 268 +1975 6 8 18 23 LESLIE 69.7 345.7 87 797 +1979 7 11 6 5 ERNESTO 9.7 82.6 67 597 +1987 6 14 6 27 DEBBY 20.8 65.3 160 140 +1973 2 24 0 4 SANDY 37.5 317.9 42 138 +1951 10 11 12 5 NADINE 24.2 48.9 46 700 +1970 7 3 12 7 JOYCE 16.3 130.1 79 263 +2004 3 17 12 7 SANDY 22.5 70.6 23 824 +1950 6 2 6 11 NADINE 60.4 337.5 26 39 +1999 11 20 18 17 GORDON 20.7 303.7 148 739 +1982 7 4 18 9 JOYCE 31.1 348.7 18 128 +1963 8 4 0 24 ALBERTO 60.1 128.9 139 694 +1986 5 15 12 13 PATTY 33.5 139.9 100 232 +1982 6 20 0 18 LESLIE 58.1 287.6 92 458 +1978 5 13 6 7 KIRK 37.1 303.0 101 478 +1976 5 18 12 21 JOYCE 33.3 285.4 22 473 +1983 7 2 6 3 ISAAC 46.7 300.4 17 672 +1960 2 21 6 19 KIRK 68.8 65.8 102 499 +1974 6 2 12 23 GORDON 7.8 98.4 101 260 +1968 3 22 6 3 ERNESTO 15.6 308.9 78 574 +1971 2 24 0 11 WILLIAM 52.7 221.0 96 718 +1995 12 19 12 17 RAFAEL 15.3 198.2 54 769 +1976 6 3 12 20 MICHAEL 50.3 175.5 128 499 +2000 5 13 12 14 HELENE 39.1 345.2 33 439 +1996 3 11 12 23 ISAAC 38.8 333.3 99 115 +1996 1 8 12 5 OSCAR 55.1 202.4 36 13 +1983 7 7 6 26 ERNESTO 25.1 123.8 28 699 +1953 11 4 0 24 SANDY 68.3 250.0 60 695 +1989 5 11 12 28 KIRK 11.1 3.5 28 312 +1983 12 2 6 27 TONY 40.9 12.6 98 821 +1999 2 26 6 1 CHRIS 62.6 162.6 45 259 +1969 5 26 12 15 ERNESTO 18.1 61.3 163 625 +1955 6 17 18 18 OSCAR 11.4 350.8 34 312 +2003 1 27 12 16 NADINE 22.1 116.0 103 602 +1964 11 14 12 27 RAFAEL 64.9 283.4 140 832 +1971 7 8 12 21 TONY 38.0 216.5 156 347 +2001 8 2 0 15 VALERIE 20.8 308.2 127 6 +1963 8 14 6 4 SANDY 58.9 178.3 48 158 +1972 12 6 6 1 BERYL 41.0 69.8 160 295 +1969 9 21 0 25 ALBERTO 68.6 101.3 112 298 +1958 11 17 6 20 NADINE 69.1 228.7 45 828 +1997 7 21 0 14 CHRIS 61.6 149.5 23 134 +1956 12 14 6 12 JOYCE 34.7 279.2 144 606 +1963 5 11 6 2 FLORENCE 18.2 256.2 157 887 +1966 12 13 6 7 ISAAC 25.6 229.3 118 704 +1958 11 20 6 8 GORDON 8.7 158.1 120 302 +1992 4 27 0 14 FLORENCE 16.1 146.6 35 293 +1982 6 15 18 22 KIRK 18.2 93.1 74 70 +1978 12 15 18 6 FLORENCE 26.0 90.9 77 337 +1963 8 19 6 5 GORDON 37.7 281.7 87 870 +1988 9 18 0 12 WILLIAM 50.7 89.9 65 128 +2001 12 16 6 8 OSCAR 60.5 322.7 44 166 +2002 3 17 18 20 PATTY 55.0 116.6 158 445 +1967 3 9 12 7 KIRK 54.0 85.5 143 129 +1952 8 16 0 21 KIRK 24.7 24.4 156 57 +1950 11 26 12 21 BERYL 63.8 17.4 40 197 +1995 6 2 18 24 ALBERTO 25.3 252.9 80 312 +1993 4 15 6 7 GORDON 56.0 144.2 20 9 +1994 2 13 18 14 VALERIE 61.5 179.1 78 31 +1950 8 17 0 12 VALERIE 64.9 114.1 87 731 +1960 4 11 6 23 MICHAEL 47.1 49.5 100 46 +1950 4 11 6 18 ISAAC 25.9 86.5 114 592 +1977 10 8 6 1 ALBERTO 21.8 182.3 11 593 +1978 6 17 18 17 SANDY 63.9 6.3 98 815 +1981 11 13 6 11 LESLIE 64.1 333.0 152 795 +1981 10 1 12 5 BERYL 20.0 30.0 79 543 +1958 3 22 18 11 HELENE 37.7 282.7 58 356 +1956 1 13 0 13 OSCAR 65.9 194.8 73 606 +1951 2 9 6 5 ALBERTO 24.5 8.6 101 710 +1977 5 5 18 16 FLORENCE 50.4 206.7 100 81 +1979 8 26 18 11 VALERIE 27.9 140.8 50 460 +1975 10 26 18 8 FLORENCE 26.1 100.6 162 762 +1963 7 27 12 7 OSCAR 63.1 226.1 110 513 +1962 4 18 18 6 SANDY 57.5 17.6 87 442 +1963 10 23 12 16 DEBBY 48.9 246.9 134 510 +1986 12 13 0 9 VALERIE 16.7 143.9 65 366 +2004 3 3 18 20 LESLIE 12.2 292.7 13 787 +1990 6 18 12 20 PATTY 55.2 50.1 140 256 +1966 11 1 18 9 RAFAEL 42.6 149.8 36 9 +1978 6 5 12 19 GORDON 24.0 8.1 17 321 +1957 3 3 0 19 VALERIE 44.8 255.4 103 581 +1951 11 10 6 27 WILLIAM 12.8 356.6 115 128 +1961 2 9 6 21 NADINE 40.8 339.0 57 723 +1968 2 17 12 7 MICHAEL 64.1 96.0 87 472 +1958 3 22 6 14 ISAAC 53.8 9.9 64 533 +1992 2 26 6 23 ISAAC 56.8 191.4 91 285 +1954 11 13 18 12 VALERIE 37.1 340.0 65 195 +1999 1 21 6 23 WILLIAM 48.6 351.3 66 477 +1978 1 6 0 17 OSCAR 66.1 271.9 83 148 +1952 12 23 0 4 PATTY 41.4 84.9 34 512 +1965 5 12 0 12 PATTY 37.5 81.8 125 879 +1988 11 5 18 16 WILLIAM 46.5 259.0 148 814 +1959 1 3 6 21 FLORENCE 25.6 222.0 18 115 +1952 9 24 0 8 BERYL 24.9 318.8 52 769 +1951 12 23 12 18 LESLIE 60.4 184.8 40 776 +1998 9 14 6 3 NADINE 64.0 170.0 14 326 +1997 4 24 6 28 ERNESTO 63.0 261.1 87 668 +1970 6 18 6 16 JOYCE 65.6 10.4 102 734 +1999 2 6 6 22 CHRIS 27.0 172.4 22 312 +1963 10 4 12 7 SANDY 46.5 119.9 56 444 +1958 6 13 0 13 SANDY 56.0 337.5 66 632 +1955 4 22 12 12 CHRIS 26.3 116.8 18 798 +1997 3 11 12 3 WILLIAM 37.6 226.5 93 268 +1968 11 27 0 19 HELENE 7.1 201.9 112 624 +1955 9 23 0 18 ALBERTO 16.4 162.1 44 215 +1992 11 22 18 21 MICHAEL 46.4 304.2 56 825 +1954 2 18 0 20 HELENE 23.0 353.7 54 888 +1955 4 7 0 1 ALBERTO 47.9 12.2 81 812 +1954 11 26 0 17 BERYL 23.6 234.4 137 771 +1986 12 3 0 22 ERNESTO 24.6 299.1 150 417 +1999 6 10 0 3 GORDON 30.7 94.3 127 238 +1999 1 14 0 7 MICHAEL 32.5 327.9 86 364 +1989 4 2 12 18 PATTY 45.1 338.6 91 550 +1955 3 2 18 21 PATTY 22.2 157.3 118 280 +2001 9 28 18 3 RAFAEL 35.8 228.9 55 208 +1997 5 18 0 6 HELENE 48.6 131.9 163 9 +1988 7 2 12 22 SANDY 16.9 39.3 37 389 +1999 8 17 18 13 VALERIE 47.3 110.7 57 463 +1967 7 9 0 14 PATTY 17.3 211.7 132 276 +1968 3 17 0 16 OSCAR 54.9 175.0 54 75 +1996 11 8 12 19 ERNESTO 45.0 43.3 52 522 +1951 5 5 6 4 ERNESTO 26.6 170.3 103 370 +1951 8 27 6 6 JOYCE 31.7 263.7 163 117 +1988 9 28 18 7 MICHAEL 26.4 124.6 116 193 +1954 8 2 6 2 SANDY 39.8 349.5 55 11 +1959 9 1 6 12 SANDY 53.6 78.8 124 426 +1995 7 16 12 13 OSCAR 62.2 316.1 124 618 +1992 11 10 0 20 DEBBY 24.8 244.8 152 626 +1999 2 24 0 4 GORDON 59.6 102.3 66 302 +1993 9 1 18 21 JOYCE 46.5 332.5 18 494 +1961 8 24 18 16 PATTY 26.4 37.5 42 298 +1997 8 26 18 22 ISAAC 29.9 174.8 53 842 +1988 2 23 0 25 TONY 9.3 85.3 13 821 +1996 11 17 12 4 GORDON 50.1 219.4 161 344 +1971 9 13 6 18 NADINE 48.3 355.8 98 765 +1963 6 3 6 11 RAFAEL 36.9 28.1 24 159 +1999 6 16 18 23 RAFAEL 32.2 326.7 94 700 +1954 12 24 6 10 SANDY 33.8 261.9 155 717 +1953 10 20 18 21 ALBERTO 21.4 145.6 36 699 +1958 3 18 18 23 OSCAR 60.5 102.6 21 398 +1964 2 20 18 26 NADINE 23.9 188.6 27 640 +2001 10 1 6 28 DEBBY 60.4 252.3 111 768 +2004 11 20 18 21 GORDON 51.6 138.3 26 333 +2001 4 26 18 8 MICHAEL 47.7 64.1 137 897 +1985 10 10 12 12 HELENE 19.8 42.9 30 610 +2000 12 11 0 1 TONY 34.2 349.9 43 192 +1967 4 1 6 16 CHRIS 17.2 237.7 35 512 +1957 9 15 18 2 BERYL 58.4 163.0 68 599 +1977 8 11 18 27 DEBBY 37.9 124.0 78 156 +1960 7 8 6 23 HELENE 31.8 217.2 59 674 +1963 2 1 18 26 SANDY 30.1 120.5 41 10 +1994 3 5 18 10 WILLIAM 10.8 169.2 82 247 +1971 2 8 0 26 WILLIAM 41.1 211.2 46 844 +1985 5 21 6 22 ALBERTO 15.8 245.0 109 522 +1981 6 28 18 1 NADINE 48.9 79.3 93 573 +1978 4 20 18 3 KIRK 52.3 68.0 76 621 +1957 4 6 12 7 OSCAR 58.1 193.8 20 689 +1973 4 25 12 6 RAFAEL 35.6 61.2 40 293 +1960 5 9 18 28 JOYCE 41.4 34.8 35 809 +1999 1 11 12 5 VALERIE 53.3 122.3 105 227 +2004 9 2 18 15 GORDON 28.0 343.2 59 829 +1973 1 7 18 2 ISAAC 17.2 125.1 90 423 +1982 12 27 12 20 RAFAEL 17.0 227.6 161 673 +1974 8 3 12 5 PATTY 15.8 257.9 24 603 +1986 1 14 18 7 LESLIE 59.5 141.7 80 888 +1984 4 4 0 7 HELENE 32.6 255.3 40 766 +2004 12 8 12 10 GORDON 57.9 197.7 60 481 +1962 7 24 12 8 VALERIE 11.6 269.8 56 253 +1957 10 13 12 6 HELENE 50.4 102.6 17 849 +1993 3 7 6 14 ISAAC 40.6 270.9 45 316 +1980 8 25 6 15 TONY 15.5 11.9 22 234 +2000 1 21 18 8 MICHAEL 26.9 205.1 23 304 +1972 5 19 6 19 PATTY 66.7 188.8 61 640 +1960 5 19 12 12 DEBBY 16.3 287.6 158 703 +1980 12 5 6 10 MICHAEL 49.9 37.6 82 841 +1962 1 26 0 6 TONY 21.2 59.9 141 95 +1977 6 3 6 16 KIRK 7.8 165.3 21 389 +1956 1 4 18 9 BERYL 40.1 22.3 28 443 +1989 7 22 0 5 PATTY 47.9 295.7 139 114 +1955 8 20 6 12 VALERIE 44.5 267.8 121 131 +1958 3 26 6 5 GORDON 23.9 114.0 116 169 +1951 10 12 12 4 ERNESTO 9.1 123.1 26 425 +1981 6 13 6 11 KIRK 37.4 274.5 104 813 +1991 1 15 6 26 ERNESTO 50.4 114.3 70 325 +1950 7 3 12 11 DEBBY 60.3 165.8 52 132 +1981 2 19 6 7 OSCAR 21.6 5.0 34 295 +1957 2 28 18 16 RAFAEL 61.1 44.2 104 194 +1954 10 27 0 17 OSCAR 17.9 180.7 130 90 +1996 2 21 6 11 ERNESTO 13.2 195.9 17 444 +1970 4 17 12 11 HELENE 9.6 245.1 42 743 +1995 3 25 18 25 HELENE 48.1 348.4 121 714 +1956 11 10 18 27 NADINE 39.3 220.8 48 374 +1959 1 16 12 12 RAFAEL 62.9 66.9 125 315 +1964 5 8 6 27 HELENE 52.7 8.8 35 378 +1963 8 28 6 16 DEBBY 15.5 326.7 92 453 +1976 2 25 6 24 RAFAEL 67.2 116.7 66 756 +1978 1 6 6 13 KIRK 22.6 255.7 24 682 +1956 2 13 12 16 ISAAC 19.9 304.8 134 363 +1993 12 8 0 11 GORDON 41.2 26.6 61 613 +1982 9 19 6 3 RAFAEL 48.9 62.7 32 826 +1990 2 13 0 10 CHRIS 36.2 164.0 126 476 +1972 5 17 0 26 LESLIE 51.7 254.4 117 843 +2004 2 23 18 18 ISAAC 32.3 281.7 115 698 +1980 5 3 12 20 LESLIE 11.0 303.3 70 623 +1964 12 15 18 12 RAFAEL 55.6 252.9 129 821 +1999 8 19 6 5 ALBERTO 49.7 162.4 18 585 +1981 10 21 0 8 VALERIE 55.4 244.8 99 373 +2002 5 9 12 26 ALBERTO 25.7 174.9 162 371 +2003 2 28 12 4 FLORENCE 36.0 227.9 19 782 +1991 11 26 0 21 KIRK 54.1 83.2 16 200 +1960 8 6 18 21 VALERIE 16.2 254.0 103 792 +1959 8 27 18 20 BERYL 68.8 58.6 115 838 +1981 4 17 6 22 LESLIE 47.0 202.8 42 311 +1954 5 12 18 7 VALERIE 35.5 83.1 157 344 +2001 8 11 0 2 OSCAR 12.6 167.3 130 205 +1982 2 24 6 1 NADINE 10.9 158.8 162 28 +1978 7 16 18 8 SANDY 32.6 123.2 155 353 +1969 10 1 6 13 NADINE 21.1 323.5 114 790 +1992 12 14 6 8 ALBERTO 26.8 347.6 24 345 +1960 1 19 6 27 LESLIE 19.0 121.7 23 561 +1974 5 9 18 19 TONY 62.0 321.2 109 330 +1972 6 28 18 7 JOYCE 21.4 226.6 36 470 +1976 8 28 6 10 HELENE 13.5 51.1 26 52 +2001 1 3 6 27 NADINE 65.8 79.5 50 65 +1995 9 14 6 16 HELENE 9.1 49.8 50 314 +1996 7 18 6 10 WILLIAM 63.8 18.7 120 110 +1969 4 8 0 14 HELENE 24.9 139.0 73 639 +1986 9 23 18 8 MICHAEL 63.2 264.2 33 365 +2000 7 21 18 14 JOYCE 69.4 109.4 74 732 +1974 1 4 18 12 ERNESTO 18.9 49.7 23 594 +1990 2 6 12 13 SANDY 57.1 271.0 44 233 +1989 8 12 0 25 LESLIE 51.5 308.2 49 365 +1990 1 18 12 9 BERYL 41.5 308.3 73 270 +2001 10 10 12 10 GORDON 42.7 266.3 48 414 +1986 5 7 12 21 MICHAEL 37.5 103.4 27 265 +1959 6 17 0 19 OSCAR 19.5 336.1 90 855 +2001 2 23 0 25 RAFAEL 26.0 269.4 146 257 +1977 11 21 12 24 LESLIE 28.3 190.5 33 736 +1965 8 9 18 23 RAFAEL 15.9 152.6 149 580 +2001 1 14 12 18 CHRIS 63.9 132.1 76 290 +1968 10 16 12 22 HELENE 39.3 16.8 32 3 +1977 8 28 12 21 JOYCE 35.5 194.3 156 297 +1960 8 5 12 20 RAFAEL 35.7 264.1 62 343 +1970 9 6 6 24 OSCAR 67.5 117.3 92 557 +1980 4 12 6 24 RAFAEL 57.7 62.8 79 273 +1968 11 2 6 19 HELENE 13.7 53.8 34 491 +1996 6 1 6 18 BERYL 43.7 223.5 36 98 +1961 2 18 18 4 ALBERTO 30.5 91.0 91 667 +1995 2 11 0 11 GORDON 60.8 165.3 140 888 +1988 10 27 18 16 FLORENCE 9.6 257.5 132 145 +2002 4 17 18 25 BERYL 32.2 332.0 84 620 +2000 9 23 12 24 ERNESTO 50.5 50.0 118 569 +1974 6 18 18 13 LESLIE 31.3 204.8 101 491 +1960 6 9 12 2 LESLIE 30.5 139.0 81 204 +1960 3 1 18 12 OSCAR 69.0 292.4 58 192 +1965 4 8 0 12 TONY 55.3 255.5 154 892 +1997 1 10 6 25 NADINE 58.2 330.8 70 381 +1966 10 22 0 24 TONY 59.8 8.3 11 216 +1951 5 25 6 24 SANDY 55.9 186.3 141 530 +1956 2 4 6 20 WILLIAM 66.4 287.0 119 104 +1964 10 18 6 18 KIRK 52.9 2.2 75 429 +1977 8 17 6 7 RAFAEL 45.3 50.4 41 441 +1983 5 9 12 17 HELENE 12.6 23.3 16 103 +1956 3 16 6 8 OSCAR 13.7 324.7 102 498 +1975 7 9 12 17 MICHAEL 29.9 65.7 51 723 +2002 12 12 6 1 HELENE 49.9 42.0 32 471 +2000 4 6 0 4 PATTY 25.6 75.7 150 364 +1990 9 19 0 20 ERNESTO 38.1 188.7 154 642 +1962 10 14 18 14 VALERIE 63.0 43.2 108 756 +1999 12 28 0 23 MICHAEL 11.1 82.5 70 879 +1980 3 28 12 21 VALERIE 26.8 247.2 42 606 +1981 6 24 0 5 CHRIS 67.8 248.1 93 98 +1956 2 22 18 20 MICHAEL 10.9 102.5 73 258 +1952 3 7 18 9 HELENE 48.2 350.5 45 431 +1976 4 5 6 19 BERYL 67.5 172.8 84 141 +1998 3 1 12 17 CHRIS 23.2 229.9 66 405 +1962 7 1 18 20 NADINE 24.1 262.3 128 504 +1979 10 10 6 3 MICHAEL 49.6 13.5 120 199 +1986 7 6 12 6 PATTY 7.2 95.4 103 370 +2003 9 28 0 24 DEBBY 68.5 118.3 149 420 +1998 3 16 12 22 FLORENCE 24.2 152.6 21 287 +1995 10 23 18 5 TONY 13.3 246.0 18 187 +1982 1 15 0 2 WILLIAM 11.5 204.9 97 26 +1981 4 26 12 27 CHRIS 19.6 273.5 156 416 +1984 4 24 0 5 ISAAC 26.3 112.5 52 260 +2004 9 13 0 9 FLORENCE 48.5 17.1 59 291 +1996 8 18 6 28 WILLIAM 61.3 200.4 45 435 +1987 11 22 6 4 KIRK 60.1 58.5 56 392 +2004 6 17 0 21 FLORENCE 65.1 318.1 147 541 +1957 4 24 18 28 GORDON 55.0 296.5 23 771 +1987 1 15 0 2 NADINE 35.9 236.5 145 870 +1975 5 17 12 27 DEBBY 43.6 352.3 147 61 +1974 4 12 0 12 KIRK 43.7 196.9 158 43 +1987 9 4 12 15 SANDY 10.3 308.5 152 738 +2003 12 26 6 2 WILLIAM 15.8 338.1 32 573 +2003 7 5 18 2 VALERIE 9.3 34.7 91 810 +1962 5 17 18 2 BERYL 52.0 85.6 102 92 +1979 10 27 18 17 WILLIAM 18.3 9.8 130 296 +1962 4 10 18 7 OSCAR 28.8 157.8 130 899 +1981 2 21 0 8 FLORENCE 55.8 208.2 79 228 +1973 8 26 0 8 RAFAEL 7.5 63.1 105 271 +1996 9 20 0 26 ERNESTO 20.9 337.0 144 283 +1994 9 21 12 1 KIRK 15.2 19.7 60 470 +1956 6 14 6 12 HELENE 27.7 126.4 87 349 +1964 3 25 18 18 CHRIS 46.8 212.1 134 280 +1985 8 14 6 3 PATTY 58.9 182.3 86 405 +1953 10 12 6 26 ALBERTO 10.1 316.4 72 33 +1995 6 6 18 17 VALERIE 53.2 271.0 31 104 +1995 11 24 6 16 WILLIAM 69.5 291.5 60 646 +1998 9 7 0 20 JOYCE 27.4 210.8 152 474 +1983 2 1 18 27 ERNESTO 31.0 158.1 20 297 +1991 5 11 0 11 WILLIAM 68.0 127.5 107 422 +1992 9 13 18 23 NADINE 53.2 79.8 33 798 +1982 11 28 0 18 DEBBY 29.6 307.3 64 176 +1988 3 15 12 19 VALERIE 11.5 243.8 76 539 +1975 5 24 18 24 WILLIAM 69.9 137.2 97 760 +1982 7 9 12 3 JOYCE 47.6 196.0 92 524 +1983 9 20 18 27 FLORENCE 68.0 282.9 16 249 +1971 2 19 12 18 OSCAR 10.8 34.0 58 152 +1993 12 26 12 1 ERNESTO 32.3 235.4 83 67 +2003 5 1 18 2 RAFAEL 28.3 64.1 64 700 +1977 11 3 0 6 ALBERTO 62.7 225.6 117 27 +1990 4 15 18 26 LESLIE 53.1 49.8 63 257 +1984 6 14 12 13 BERYL 58.0 274.3 10 244 +2001 1 10 18 10 HELENE 51.9 96.5 146 618 +1970 5 21 18 20 BERYL 38.5 12.5 46 299 +1987 7 15 6 4 WILLIAM 41.2 231.9 130 119 +1956 5 27 0 18 TONY 54.2 331.0 90 592 +1965 6 20 12 8 SANDY 68.8 130.0 21 881 +1964 4 17 12 19 ERNESTO 14.9 328.1 35 279 +1964 6 9 12 4 CHRIS 63.9 272.0 130 505 +1954 7 19 18 26 DEBBY 63.0 70.1 152 450 +1974 5 5 0 1 ALBERTO 60.0 254.7 148 355 +1989 10 15 18 15 DEBBY 9.8 157.6 122 806 +1998 11 17 0 15 OSCAR 56.2 184.2 42 204 +1952 10 13 12 22 JOYCE 30.6 38.1 63 510 +1976 12 11 6 27 SANDY 65.8 113.8 157 709 +2002 2 15 18 14 RAFAEL 23.7 52.6 17 709 +1960 9 25 18 21 WILLIAM 37.1 154.6 25 472 +1992 7 19 18 11 OSCAR 43.2 114.7 141 151 +1996 5 27 6 1 CHRIS 47.5 50.2 67 141 +1969 1 22 0 20 WILLIAM 26.0 77.8 118 479 +1983 12 18 6 2 CHRIS 23.9 6.4 30 687 +1950 4 23 18 24 ISAAC 55.6 253.2 150 884 +1959 3 25 18 18 MICHAEL 9.1 35.1 83 851 +1965 6 23 0 4 VALERIE 47.7 48.7 31 53 +1981 3 19 18 25 BERYL 44.3 187.4 98 772 +1976 8 13 0 12 ISAAC 11.1 48.9 109 41 +2001 12 9 6 2 RAFAEL 48.7 306.0 144 645 +1963 12 16 0 24 GORDON 53.3 355.7 79 326 +1969 1 12 18 6 OSCAR 41.8 131.8 133 804 +1972 6 24 18 27 TONY 54.0 67.8 39 200 +1982 5 27 18 2 SANDY 46.6 210.2 142 197 +1980 8 3 18 13 GORDON 14.1 328.0 80 104 +1966 12 28 12 19 ALBERTO 69.3 18.3 63 417 +1976 3 8 0 28 WILLIAM 38.6 186.1 47 148 +1998 10 20 18 28 MICHAEL 44.7 57.7 88 687 +1991 7 2 12 16 SANDY 35.8 193.9 22 560 +1954 7 28 6 19 HELENE 61.4 254.3 11 9 +1991 12 7 0 7 ISAAC 38.6 85.5 64 634 +1978 3 14 0 14 ERNESTO 65.4 115.7 42 54 +1969 5 19 12 14 JOYCE 7.9 206.8 141 458 +1982 9 4 12 6 KIRK 26.6 48.4 148 146 +1975 6 21 12 6 ALBERTO 28.3 303.3 29 581 +1953 1 14 0 23 ALBERTO 61.8 122.5 92 475 +1975 8 20 0 1 ISAAC 20.1 168.2 98 599 +1983 7 9 6 18 VALERIE 27.4 100.1 45 718 +1953 9 8 18 15 VALERIE 48.3 171.6 67 470 +2003 2 6 0 17 VALERIE 39.1 290.6 39 803 +1950 9 5 6 21 HELENE 20.9 282.7 123 20 +1959 12 16 18 14 CHRIS 22.2 107.0 104 351 +1977 9 22 0 5 DEBBY 26.4 184.8 112 612 +1994 6 6 12 17 JOYCE 28.0 286.4 72 647 +1974 6 4 18 13 ERNESTO 30.2 182.4 34 196 +2000 2 25 18 17 WILLIAM 49.0 17.7 42 691 +1996 11 5 6 13 TONY 59.9 176.1 15 730 +1981 7 21 0 7 DEBBY 61.6 312.0 107 95 +1985 2 5 12 23 MICHAEL 48.9 155.3 106 233 +1970 9 10 6 1 PATTY 24.5 173.4 121 537 +1997 7 4 12 20 ALBERTO 46.5 254.3 58 336 +1980 6 2 6 19 PATTY 32.4 284.5 14 49 +1980 2 23 18 18 OSCAR 16.1 121.7 82 116 +1957 12 27 18 2 OSCAR 52.7 137.9 121 94 +1959 10 20 6 14 TONY 40.1 204.4 40 648 +2001 9 1 6 17 JOYCE 26.1 93.9 149 818 +1976 4 5 12 25 ISAAC 45.8 162.3 68 53 +1962 10 19 18 18 CHRIS 12.9 265.5 90 743 +2004 6 26 12 6 BERYL 47.3 127.1 69 753 +1953 8 11 0 8 FLORENCE 29.2 135.6 52 795 +1954 6 1 12 25 BERYL 25.8 160.9 142 370 +2002 10 3 6 7 LESLIE 39.5 241.9 115 320 +1978 9 8 12 10 BERYL 14.5 121.1 68 248 +1984 12 6 6 19 LESLIE 12.6 30.5 40 140 +1956 2 11 0 14 DEBBY 57.9 169.8 112 470 +1991 1 3 6 27 ERNESTO 37.5 244.5 145 894 +1966 9 17 18 19 GORDON 41.1 132.1 150 273 +1963 7 19 0 19 ERNESTO 53.6 164.6 102 240 +1955 12 24 12 23 HELENE 62.7 330.7 112 214 +1987 2 16 18 28 CHRIS 21.9 64.3 51 438 +1969 11 12 18 4 CHRIS 44.0 204.4 71 199 +1966 12 15 18 4 WILLIAM 54.5 325.1 78 661 +1979 10 4 12 1 SANDY 33.6 164.6 44 688 +2002 8 6 6 23 ERNESTO 51.9 200.8 86 604 +1982 2 19 18 10 ALBERTO 8.7 123.1 21 549 +1976 3 3 18 14 GORDON 35.5 148.0 17 562 +2001 12 4 12 10 DEBBY 43.9 140.8 24 134 +1984 8 26 12 20 SANDY 62.4 319.6 113 314 +1972 8 5 18 17 LESLIE 17.2 6.5 67 759 +1976 2 27 6 27 ERNESTO 53.0 268.8 57 531 +1964 9 5 6 26 DEBBY 54.2 152.0 129 752 +1993 3 3 12 4 OSCAR 49.7 33.4 84 357 +1951 10 24 6 7 GORDON 8.0 314.4 128 673 +1977 12 7 12 28 JOYCE 25.7 164.7 97 575 +1950 7 1 6 23 CHRIS 60.8 137.1 145 226 +2002 1 5 6 1 NADINE 38.0 337.7 36 458 +1985 3 13 18 20 RAFAEL 50.2 295.9 73 849 +1997 9 1 0 2 MICHAEL 17.3 314.4 153 16 +1965 12 11 6 17 ISAAC 51.7 233.1 47 580 +1974 10 26 0 24 JOYCE 35.9 191.1 119 376 +1958 7 28 6 17 GORDON 47.9 273.2 146 600 +1996 1 28 18 25 BERYL 58.1 338.0 99 558 +1973 7 23 12 20 RAFAEL 7.6 270.4 75 637 +1971 7 1 12 23 ISAAC 49.5 226.7 142 408 +2000 9 14 12 1 BERYL 58.9 132.2 68 199 +1981 2 4 12 9 BERYL 55.3 216.0 137 145 +1993 11 11 0 1 RAFAEL 33.2 259.2 10 603 +1990 8 16 6 3 DEBBY 41.2 37.1 86 431 +1981 11 7 0 23 BERYL 54.7 285.7 131 21 +1968 8 13 12 19 NADINE 67.1 35.8 122 752 +1990 2 13 12 11 RAFAEL 25.4 298.8 51 244 +1990 9 7 18 1 RAFAEL 32.8 254.8 49 394 +1978 4 2 6 13 GORDON 42.6 69.8 11 673 +1992 4 5 18 16 BERYL 16.3 49.9 93 888 +1992 7 8 6 4 ALBERTO 49.2 33.0 133 732 +2002 9 20 6 19 NADINE 21.3 208.7 151 55 +1985 6 14 0 23 LESLIE 46.6 9.3 39 132 +1964 9 7 6 10 HELENE 11.7 84.5 160 272 +1992 7 16 0 1 BERYL 58.9 164.8 156 572 +1984 7 13 6 7 CHRIS 19.2 85.5 71 414 +1978 10 6 0 10 BERYL 61.8 195.7 84 567 +1985 7 13 0 4 CHRIS 40.2 252.5 120 886 +1989 4 10 18 20 JOYCE 47.5 86.0 102 847 +1995 11 13 0 28 RAFAEL 10.6 276.4 140 364 +1959 11 9 12 28 BERYL 46.0 144.1 45 611 +1971 4 13 0 27 JOYCE 63.4 130.5 137 583 +1976 5 25 18 17 CHRIS 63.1 238.8 72 256 +1985 3 18 6 16 RAFAEL 17.7 313.6 13 692 +1966 11 12 18 27 TONY 37.9 17.9 145 516 +1951 3 4 12 6 RAFAEL 38.1 122.2 96 10 +1958 12 9 18 17 BERYL 12.3 294.1 155 870 +1977 7 28 12 26 MICHAEL 61.5 61.7 71 486 +1993 4 13 0 11 TONY 64.4 39.7 157 415 +1974 12 4 6 11 TONY 15.2 84.6 14 601 +1964 2 25 12 23 GORDON 11.1 8.2 117 99 +1954 2 16 18 20 DEBBY 35.1 211.5 87 21 +1964 1 15 0 16 LESLIE 64.6 72.7 34 856 +2002 7 5 0 12 ISAAC 48.9 273.0 149 128 +2003 11 9 6 9 LESLIE 20.1 344.6 44 153 +1999 7 10 6 25 BERYL 50.6 51.7 142 821 +1979 11 14 12 10 TONY 39.9 357.2 93 555 +1973 7 1 12 8 VALERIE 47.7 178.8 80 266 +1975 5 11 6 19 ALBERTO 42.4 152.7 17 605 +1988 8 5 12 19 VALERIE 49.6 212.1 121 334 +1979 10 17 6 6 PATTY 11.7 127.1 64 169 +1968 1 13 18 12 ISAAC 48.8 97.5 55 251 +1986 8 23 12 26 ISAAC 47.0 107.1 95 546 +1972 5 24 18 26 ALBERTO 58.9 29.4 104 408 +1972 12 12 18 24 VALERIE 40.5 231.7 154 496 +1975 11 12 12 4 BERYL 44.1 318.0 25 713 +1972 3 7 18 12 NADINE 33.2 239.5 119 544 +1961 1 21 12 2 VALERIE 55.1 254.2 42 783 +2001 3 7 6 8 DEBBY 9.6 221.6 44 252 +1987 5 7 18 20 OSCAR 37.1 339.1 62 336 +1999 7 4 12 5 WILLIAM 59.8 87.7 139 346 +1992 11 8 6 20 TONY 32.3 132.8 89 748 +1952 10 27 6 6 ALBERTO 62.4 99.7 17 861 +1987 8 24 12 8 WILLIAM 40.2 176.2 138 723 +1963 2 5 0 22 KIRK 40.9 30.1 143 47 +1959 8 15 18 21 HELENE 11.0 9.6 122 151 +1979 6 7 12 6 OSCAR 62.5 177.6 73 540 +1977 7 9 6 26 WILLIAM 48.8 116.9 130 100 +1961 1 28 18 5 JOYCE 33.0 284.7 147 723 +1999 6 22 6 7 WILLIAM 65.6 29.7 84 619 +1978 5 11 18 12 BERYL 26.6 185.4 101 45 +1962 5 4 6 25 ALBERTO 50.9 84.8 96 387 +1968 6 1 12 24 PATTY 45.8 205.6 12 151 +1968 10 7 18 13 CHRIS 63.9 180.0 161 532 +1993 3 15 0 1 ERNESTO 37.1 257.6 32 306 +1977 6 6 12 22 PATTY 17.1 29.6 77 407 +1992 3 28 18 23 WILLIAM 65.6 102.1 135 130 +1979 5 28 12 9 WILLIAM 25.4 25.9 115 516 +1974 4 24 18 3 ALBERTO 47.5 72.9 144 160 +1961 2 3 0 23 JOYCE 49.3 218.1 150 464 +1965 1 20 18 10 DEBBY 63.6 115.0 59 734 +1982 9 1 6 23 MICHAEL 53.3 10.9 40 861 +1955 3 23 18 28 GORDON 9.2 188.7 49 727 +1983 6 26 12 24 FLORENCE 65.9 320.6 14 820 +1973 3 9 0 19 FLORENCE 37.1 266.4 27 837 +1985 5 12 0 12 GORDON 50.9 34.4 87 765 +1953 6 13 0 2 KIRK 44.7 264.3 72 344 +1955 10 14 12 6 LESLIE 50.5 273.5 42 2 +1970 4 1 12 24 MICHAEL 29.6 229.0 141 287 +2004 12 23 6 8 OSCAR 29.3 298.8 164 293 +1958 7 18 0 2 RAFAEL 44.0 253.4 108 291 +1967 11 10 0 7 DEBBY 16.7 344.9 52 306 +1955 9 23 0 16 FLORENCE 27.1 118.3 79 583 +1977 9 21 18 23 GORDON 18.7 144.0 91 72 +1960 2 26 6 12 MICHAEL 37.9 99.4 58 348 +1959 11 18 0 2 RAFAEL 62.8 151.5 33 581 +1964 7 28 6 6 NADINE 39.7 268.2 91 258 +1983 8 3 0 17 JOYCE 12.3 233.1 72 542 +1951 10 4 0 6 HELENE 52.2 177.6 128 730 +2001 9 23 0 28 MICHAEL 30.2 144.3 101 94 +1971 9 17 0 7 RAFAEL 30.1 298.2 39 325 +1951 11 15 18 12 OSCAR 41.3 61.0 88 164 +1998 5 27 0 6 HELENE 30.8 5.4 131 4 +1956 7 5 6 9 VALERIE 36.2 205.8 50 558 +1985 7 17 18 19 RAFAEL 18.0 28.5 152 855 +1963 7 28 6 2 ISAAC 21.1 286.3 105 818 +1959 4 17 0 2 PATTY 45.5 220.7 56 130 +1950 11 7 18 17 OSCAR 50.4 240.0 90 218 +1961 11 18 0 28 VALERIE 58.1 247.6 34 678 +2003 5 26 0 16 NADINE 56.6 93.4 78 231 +1992 3 4 18 26 OSCAR 39.6 52.3 82 41 +1969 2 3 0 21 ERNESTO 40.7 63.1 32 22 +1973 5 27 18 5 CHRIS 32.7 282.4 84 113 +1976 12 1 6 6 BERYL 69.9 22.2 149 441 +1999 4 3 18 20 WILLIAM 65.8 19.6 145 440 +1969 7 8 0 26 PATTY 53.8 334.8 30 569 +1959 1 2 6 6 HELENE 39.2 94.9 144 213 +1951 2 22 18 1 CHRIS 53.1 115.7 47 852 +1955 12 9 18 13 HELENE 65.5 4.2 69 32 +1977 5 26 12 25 OSCAR 15.9 233.8 82 856 +2002 10 10 6 12 ALBERTO 31.1 51.7 149 370 +1957 6 4 18 8 MICHAEL 45.4 157.2 91 381 +1952 1 17 12 2 NADINE 23.3 328.3 54 616 +1985 12 15 18 10 ERNESTO 17.2 229.6 27 132 +1985 5 12 12 5 TONY 30.9 281.4 51 446 +2000 4 3 18 19 NADINE 43.1 258.7 81 167 +1970 12 26 18 24 HELENE 39.0 12.5 65 415 +1954 6 27 0 2 FLORENCE 40.0 274.8 20 300 +1956 2 12 12 12 HELENE 11.9 99.8 131 841 +1950 8 18 0 15 FLORENCE 53.2 335.1 138 834 +1990 10 27 12 23 ISAAC 51.1 126.3 40 817 +1981 6 18 6 21 DEBBY 26.3 262.0 90 734 +1981 2 20 6 7 FLORENCE 52.3 327.0 29 356 +1975 11 11 0 16 KIRK 27.1 312.2 27 500 +1970 3 27 18 6 MICHAEL 39.2 25.6 141 291 +1976 6 6 6 20 CHRIS 69.4 301.3 40 327 +1977 3 27 12 21 PATTY 51.8 112.3 49 309 +1958 10 7 18 15 ISAAC 62.6 126.3 97 493 +1957 4 27 6 20 FLORENCE 42.6 199.6 148 717 +1957 8 26 0 5 WILLIAM 50.1 39.0 57 848 +1971 6 1 18 26 VALERIE 34.3 211.0 114 860 +1971 6 18 12 21 VALERIE 26.0 304.4 11 657 +1988 12 16 0 4 ALBERTO 26.0 286.1 162 52 +1972 12 4 18 22 MICHAEL 18.0 302.0 150 18 +1993 5 19 18 10 BERYL 53.1 66.2 65 194 +1979 4 15 18 24 OSCAR 31.0 331.3 46 831 +1983 10 22 6 23 SANDY 17.8 206.5 128 159 +2000 8 7 0 8 CHRIS 35.5 56.2 62 111 +1973 4 6 0 23 VALERIE 65.4 2.1 55 706 +1971 11 3 0 13 LESLIE 63.9 85.3 105 736 +1979 9 17 12 9 JOYCE 60.9 275.7 94 785 +2000 7 7 12 11 ERNESTO 46.4 328.6 142 656 +1998 10 3 12 19 FLORENCE 64.1 38.2 105 417 +1961 2 5 12 2 FLORENCE 48.7 217.5 29 667 +1966 3 1 18 14 OSCAR 38.0 13.6 56 221 +1988 9 19 18 12 WILLIAM 8.3 115.5 14 284 +1978 6 25 0 12 VALERIE 52.2 22.6 157 734 +1996 7 25 6 5 DEBBY 46.5 69.7 136 37 +1999 12 25 18 17 GORDON 36.6 26.5 58 709 +1974 1 25 12 21 PATTY 37.2 42.4 26 24 +1993 8 5 18 14 PATTY 11.1 26.9 50 458 +1952 8 7 0 7 GORDON 42.8 186.2 11 162 +1963 3 10 0 11 MICHAEL 22.4 273.9 22 466 +1953 1 12 12 18 WILLIAM 64.6 343.8 19 60 +1975 6 9 12 20 WILLIAM 36.1 212.8 107 238 +1959 9 24 12 21 LESLIE 13.5 199.5 42 16 +1985 11 16 18 14 WILLIAM 41.4 353.0 19 448 +1960 10 20 6 20 FLORENCE 60.8 253.1 59 831 +1994 7 24 6 7 ISAAC 56.3 270.5 93 785 +1988 12 15 6 11 SANDY 30.8 275.8 112 467 +1993 10 24 12 9 DEBBY 15.7 131.7 51 645 +2003 11 22 18 12 ERNESTO 40.2 132.9 48 818 +2002 11 19 0 23 VALERIE 44.1 51.8 42 294 +1952 7 17 18 9 OSCAR 46.9 144.4 126 482 +1979 3 3 18 5 VALERIE 45.8 177.0 133 259 +1969 10 6 6 17 ERNESTO 12.0 94.3 151 100 +1965 4 12 18 14 HELENE 13.8 221.2 160 440 +1954 5 2 18 21 OSCAR 42.6 203.5 37 357 +1952 6 17 12 18 SANDY 33.7 232.5 157 363 +1952 7 8 18 6 GORDON 18.9 214.9 70 319 +2004 9 8 6 5 NADINE 29.0 331.7 130 372 +1956 5 19 0 3 LESLIE 54.7 227.7 62 866 +2004 6 2 12 23 NADINE 45.5 338.4 112 256 +1970 8 24 6 3 PATTY 59.3 355.0 114 818 +1965 4 18 6 14 DEBBY 62.7 320.4 16 823 +1989 10 19 6 3 OSCAR 46.7 137.2 145 239 +1999 5 4 0 9 ISAAC 64.9 1.0 134 259 +1994 11 17 18 12 BERYL 64.8 103.8 133 31 +1984 4 24 0 12 RAFAEL 15.5 211.4 160 130 +1956 12 27 6 16 HELENE 12.5 258.7 142 470 +1970 9 15 12 26 MICHAEL 15.8 141.6 72 142 +1956 1 7 0 1 VALERIE 14.9 116.4 68 698 +1997 2 21 18 12 VALERIE 24.3 269.0 51 388 +1978 9 13 18 2 WILLIAM 38.1 113.1 106 397 +1964 3 21 6 19 LESLIE 54.9 178.9 24 81 +1964 9 10 6 25 JOYCE 28.3 205.6 32 782 +1951 10 11 18 2 RAFAEL 68.2 278.4 128 823 +1980 6 11 12 18 LESLIE 20.7 138.7 95 774 +1950 7 8 12 13 ISAAC 62.0 331.5 118 484 +1995 10 25 12 10 MICHAEL 55.7 120.0 68 760 +1980 12 4 18 17 CHRIS 32.9 221.2 140 663 +1967 2 26 18 22 NADINE 9.9 1.8 117 604 +1977 8 6 6 16 GORDON 48.1 83.3 66 729 +2003 3 4 0 28 TONY 43.9 317.8 14 138 +1956 2 26 6 2 MICHAEL 7.6 140.8 28 577 +1987 10 14 6 10 TONY 34.4 123.1 121 662 +1996 6 10 18 22 SANDY 69.9 41.3 99 312 +1986 2 8 0 9 ISAAC 60.4 166.0 81 302 +1979 12 13 0 14 HELENE 59.8 324.7 21 298 +2002 10 18 6 17 KIRK 52.2 125.1 115 731 +1955 2 4 6 17 ERNESTO 9.1 88.3 59 369 +1976 8 6 18 23 MICHAEL 9.2 213.6 73 897 +1967 5 9 0 22 ERNESTO 9.6 13.9 31 93 +1953 8 6 0 16 FLORENCE 53.4 225.1 143 843 +1955 4 1 18 3 KIRK 30.5 70.4 121 195 +1972 9 15 12 12 JOYCE 13.3 91.1 73 33 +1951 2 8 0 16 MICHAEL 65.5 257.5 49 327 +1997 7 20 18 17 LESLIE 53.7 333.2 34 358 +1992 4 3 0 9 VALERIE 64.4 126.6 140 634 +1974 8 9 18 15 BERYL 21.4 14.9 27 88 +1978 7 10 0 16 PATTY 49.0 119.3 53 629 +1975 1 26 0 2 GORDON 45.0 35.0 73 134 +1954 7 15 0 25 OSCAR 27.6 172.9 120 311 +1969 9 27 0 21 PATTY 23.1 313.2 107 383 +1964 10 20 12 21 FLORENCE 49.8 185.9 132 401 +1994 5 20 0 2 MICHAEL 48.6 130.6 109 77 +1972 11 20 0 9 KIRK 37.2 308.4 37 820 +1993 11 25 6 10 WILLIAM 65.5 210.6 136 177 +1967 9 23 18 7 CHRIS 13.0 116.1 81 801 +1958 8 17 12 26 VALERIE 61.9 315.0 95 706 +1959 3 28 12 21 VALERIE 42.7 82.6 35 46 +1968 3 16 0 10 DEBBY 26.3 199.1 137 576 +1997 8 3 6 18 ALBERTO 42.1 284.1 128 65 +1982 2 13 18 19 ISAAC 35.2 330.6 93 397 +1956 5 14 18 7 VALERIE 50.9 258.7 107 703 +1952 9 28 0 27 VALERIE 50.1 145.6 156 120 +1990 10 27 18 19 ALBERTO 39.6 186.8 135 556 +1998 9 20 12 7 NADINE 16.5 246.3 79 194 +1950 5 12 18 15 DEBBY 37.8 255.6 66 791 +1999 7 18 6 1 ERNESTO 52.5 154.4 78 841 +2003 6 8 6 7 PATTY 63.5 247.8 113 25 +1978 2 11 18 20 MICHAEL 61.5 235.6 140 129 +1987 1 15 0 18 ALBERTO 11.4 184.6 88 340 +1959 4 24 12 23 MICHAEL 39.2 253.2 42 838 +1981 3 17 12 3 JOYCE 68.5 330.3 123 701 +1969 5 25 6 14 FLORENCE 46.2 249.0 123 540 +1992 6 14 12 27 SANDY 64.7 245.9 76 53 +1977 11 10 0 21 WILLIAM 55.7 45.8 99 38 +1995 6 7 0 2 JOYCE 62.0 337.7 51 31 +2003 11 12 12 4 OSCAR 65.8 19.9 62 615 +1976 7 3 12 25 CHRIS 46.9 163.8 39 348 +1989 11 1 18 9 MICHAEL 15.7 277.4 38 712 +1999 1 13 6 5 DEBBY 11.4 303.6 71 776 +1978 12 7 18 14 WILLIAM 23.6 292.4 160 158 +1971 6 14 0 27 HELENE 43.6 153.2 121 358 +1980 12 8 6 2 ALBERTO 49.4 144.2 134 364 +1978 6 4 12 27 JOYCE 19.6 19.9 27 753 +1967 6 27 0 7 VALERIE 29.4 230.9 10 177 +1977 8 8 18 8 VALERIE 34.5 136.5 90 56 +1990 2 6 0 23 OSCAR 36.2 138.3 116 14 +1991 1 20 6 15 VALERIE 35.1 188.4 14 671 +1993 11 15 6 26 HELENE 20.1 25.4 124 378 +1951 5 12 12 25 KIRK 20.2 262.9 119 172 +1954 1 13 6 27 RAFAEL 58.6 69.9 120 847 +1985 10 2 0 5 FLORENCE 40.3 354.8 67 828 +1989 2 26 6 13 MICHAEL 13.1 183.5 76 558 +1960 3 16 12 14 JOYCE 22.9 169.8 121 456 +1954 2 27 18 16 LESLIE 16.8 86.1 93 516 +1978 3 26 12 9 ALBERTO 60.4 342.9 121 399 +1970 6 18 12 9 JOYCE 14.9 192.1 135 567 +2003 6 11 18 14 ISAAC 69.3 274.5 156 272 +1980 8 10 18 12 ALBERTO 65.5 43.4 160 437 +1951 10 17 18 3 HELENE 22.6 105.6 89 888 +1958 6 17 12 11 MICHAEL 7.9 282.7 89 665 +1967 1 11 6 4 OSCAR 51.5 357.4 48 21 +1982 4 16 6 9 LESLIE 24.6 309.4 14 299 +1975 12 24 18 8 CHRIS 16.2 338.3 142 429 +1983 12 24 0 4 ERNESTO 9.2 94.0 59 288 +1973 9 19 12 8 BERYL 32.0 83.1 156 322 +1955 1 18 0 16 WILLIAM 24.8 171.8 34 784 +1992 12 6 6 9 ALBERTO 51.4 166.2 20 399 +2004 1 4 12 2 VALERIE 14.9 110.2 53 627 +1996 5 5 0 6 CHRIS 45.4 150.4 100 740 +1970 11 22 0 23 BERYL 33.9 130.3 130 565 +1979 9 21 12 19 LESLIE 21.6 176.6 44 557 +2000 6 17 18 27 SANDY 65.6 33.8 128 281 +1967 7 11 0 6 MICHAEL 28.0 125.9 141 89 +1991 5 7 12 11 ERNESTO 52.2 144.5 22 42 +1962 8 21 0 16 ISAAC 63.7 158.7 76 583 +1984 7 8 6 21 HELENE 60.0 92.2 159 493 +1992 9 11 18 25 DEBBY 43.2 216.8 66 690 +1988 7 10 18 26 SANDY 26.4 315.3 146 188 +1951 3 3 12 23 HELENE 48.7 251.3 136 411 +1960 6 25 18 28 WILLIAM 32.5 251.8 112 504 +1995 2 1 0 12 DEBBY 33.7 107.6 129 77 +2001 2 16 0 4 FLORENCE 18.0 187.2 127 352 +2001 10 17 18 9 WILLIAM 12.1 324.7 57 524 +1984 2 4 18 16 NADINE 66.8 307.2 50 602 +1997 2 8 0 21 WILLIAM 9.2 288.5 159 765 +2000 9 11 0 9 KIRK 33.6 306.6 89 71 +1986 10 9 0 2 HELENE 65.3 240.0 161 91 +1951 7 17 6 7 MICHAEL 28.5 319.4 118 22 +1969 11 24 18 14 OSCAR 39.1 131.6 58 430 +1951 6 16 0 15 ISAAC 33.8 347.6 68 125 +1997 11 16 12 19 BERYL 43.1 51.3 100 325 +2003 7 12 0 26 JOYCE 57.4 81.5 69 621 +1981 3 17 12 15 VALERIE 54.5 26.2 91 388 +1989 7 6 0 18 BERYL 12.5 268.5 136 601 +1998 12 21 6 2 KIRK 44.9 332.8 110 514 +1999 2 26 12 5 KIRK 63.8 45.5 88 10 +1978 3 4 12 23 PATTY 58.1 232.4 37 391 +1960 6 4 12 26 LESLIE 29.8 65.6 103 491 +1983 11 25 12 4 TONY 23.2 167.5 110 826 +1995 7 8 12 7 ISAAC 39.2 223.8 134 828 +1960 12 18 6 11 OSCAR 35.5 103.7 70 742 +1984 4 24 12 4 ISAAC 15.5 216.0 68 122 +1955 7 7 0 16 DEBBY 11.8 192.0 95 478 +1984 1 19 0 22 OSCAR 67.6 129.5 38 194 +1987 4 21 0 24 JOYCE 50.6 221.7 42 434 +2000 9 20 12 10 GORDON 19.0 144.2 158 88 +1967 6 25 12 24 ERNESTO 52.0 67.4 132 490 +1987 2 11 0 23 BERYL 19.5 200.6 125 31 +1971 4 18 18 7 MICHAEL 43.2 96.3 94 361 +1993 12 28 12 1 MICHAEL 58.9 301.5 14 1 +1961 5 22 12 15 FLORENCE 40.7 286.0 18 197 +1984 6 20 6 1 SANDY 14.8 280.0 140 822 +1980 6 4 12 4 WILLIAM 18.8 342.1 41 860 +1952 11 16 18 18 KIRK 48.4 162.1 104 239 +1993 12 15 0 1 KIRK 17.7 109.7 22 201 +1972 7 13 6 11 TONY 13.4 170.7 141 209 +1961 11 6 6 10 BERYL 32.2 189.1 83 722 +1985 6 19 0 20 FLORENCE 54.5 78.5 145 845 +1972 5 4 0 18 ERNESTO 27.6 197.9 95 16 +1989 2 5 18 20 ISAAC 8.4 215.6 23 208 +1996 12 27 12 5 KIRK 33.8 139.5 141 239 +2004 10 12 12 25 MICHAEL 43.6 201.5 38 688 +1983 3 19 18 2 LESLIE 39.3 63.9 90 328 +1966 2 5 0 17 SANDY 10.4 35.7 16 834 +1999 6 17 18 17 GORDON 67.0 201.8 114 360 +1971 2 25 12 8 DEBBY 59.0 249.0 51 120 +2002 5 17 18 3 RAFAEL 26.5 101.8 87 791 +1959 4 6 6 2 HELENE 19.9 207.8 142 372 +1991 12 2 6 10 ISAAC 63.7 105.3 104 658 +1989 1 27 18 11 JOYCE 21.5 325.8 124 358 +1972 8 18 0 14 VALERIE 32.5 338.5 146 196 +1954 11 12 0 1 ISAAC 36.7 163.6 49 305 +1967 10 18 18 1 TONY 61.0 47.4 24 772 +1985 4 24 0 22 LESLIE 18.0 109.3 56 377 +1952 4 22 6 13 GORDON 22.1 307.7 12 225 +2000 4 14 12 19 OSCAR 63.2 226.9 134 625 +1960 2 3 12 14 ALBERTO 64.4 323.5 157 635 +1978 5 19 6 25 KIRK 64.0 289.4 80 190 +1957 10 27 0 20 CHRIS 58.9 287.3 43 886 +1957 10 11 18 2 GORDON 68.2 250.8 101 548 +1981 1 16 0 9 GORDON 51.0 216.5 97 261 +1984 6 6 6 25 LESLIE 12.4 114.4 15 201 +1987 10 15 12 11 BERYL 19.9 11.9 160 65 +1980 5 18 6 10 TONY 15.9 320.6 21 562 +1964 2 23 0 24 CHRIS 43.3 72.0 12 529 +1969 6 8 12 16 JOYCE 50.1 120.9 53 243 +1967 3 5 18 24 NADINE 34.4 356.9 128 363 +1984 2 6 0 19 OSCAR 23.1 74.1 157 289 +1971 1 28 6 9 RAFAEL 69.9 315.6 60 624 +1992 6 24 0 18 SANDY 61.0 48.8 118 482 +1966 6 26 18 7 LESLIE 66.6 54.9 75 454 +1952 4 24 12 18 OSCAR 66.6 134.5 32 150 +1982 1 22 0 14 JOYCE 12.8 263.8 120 779 +1964 6 5 18 21 FLORENCE 14.6 282.6 47 519 +1997 11 17 18 9 DEBBY 9.2 350.8 100 363 +1998 11 14 0 2 HELENE 22.6 123.6 138 283 +1992 11 1 12 19 KIRK 11.0 195.1 20 79 +1962 7 16 6 9 RAFAEL 65.6 55.7 91 526 +1999 5 25 12 9 JOYCE 39.7 333.5 71 301 +1986 12 23 6 6 WILLIAM 14.0 292.5 113 277 +1979 12 17 18 21 PATTY 49.4 231.0 140 697 +1994 1 6 6 19 ISAAC 34.6 292.6 146 112 +1976 3 18 18 11 JOYCE 36.8 194.1 45 731 +1951 6 12 12 20 OSCAR 40.0 227.1 57 71 +1968 10 13 6 27 KIRK 39.9 350.7 154 510 +2002 2 8 0 7 KIRK 51.0 300.4 55 295 +1970 5 26 6 13 CHRIS 23.2 229.6 140 51 +1977 3 25 18 18 PATTY 47.7 208.8 80 308 +1988 4 12 0 2 TONY 11.4 323.9 15 466 +1998 1 2 12 22 PATTY 29.9 87.3 115 94 +1954 2 10 6 15 VALERIE 43.9 341.9 104 493 +2004 8 19 18 1 ERNESTO 48.8 197.7 132 834 +2004 6 15 12 21 JOYCE 44.4 73.4 84 726 +1987 11 17 6 28 NADINE 66.1 224.1 41 566 +1954 3 28 0 6 JOYCE 33.1 340.9 61 224 +1982 7 13 12 24 ISAAC 12.5 99.8 48 655 +1950 10 21 18 3 WILLIAM 16.6 60.3 78 117 +1988 4 21 0 17 NADINE 54.2 2.8 159 175 +2002 3 2 6 24 BERYL 36.1 353.8 137 392 +2004 5 14 12 6 LESLIE 19.4 31.2 109 294 +1987 4 22 12 9 KIRK 38.9 310.2 18 589 +1972 9 26 0 18 OSCAR 47.3 108.0 164 562 +1968 3 21 6 3 KIRK 53.2 113.3 31 645 +1973 2 16 12 25 VALERIE 63.9 298.3 78 243 +1964 5 20 12 7 HELENE 36.4 295.7 46 501 +1987 2 3 0 7 PATTY 32.2 171.7 34 440 +1979 4 4 6 25 NADINE 31.4 26.9 100 354 +2001 6 16 18 7 BERYL 49.6 207.5 157 297 +2000 11 12 6 3 CHRIS 59.3 85.3 91 791 +1968 3 10 0 27 BERYL 31.3 71.2 14 370 +1974 8 8 18 19 PATTY 60.4 171.8 97 342 +1959 11 4 12 23 SANDY 39.9 87.9 49 529 +1986 9 5 6 3 NADINE 43.2 311.2 90 183 +1955 2 8 18 26 SANDY 21.3 102.9 101 513 +1980 10 20 0 17 VALERIE 66.2 212.8 140 16 +1967 3 23 6 1 OSCAR 16.2 343.5 12 52 +1951 5 14 18 17 HELENE 61.2 109.9 101 601 +1980 4 28 0 26 GORDON 30.9 250.7 78 621 +1961 8 18 0 24 PATTY 30.1 182.5 158 60 +1994 11 2 18 19 NADINE 12.7 63.0 34 391 +1977 5 2 18 11 GORDON 19.6 22.0 103 517 +1969 2 22 6 4 LESLIE 67.0 14.2 106 392 +1987 5 4 12 21 VALERIE 68.4 305.5 13 525 +1956 3 22 6 4 ERNESTO 16.5 58.4 105 481 +1984 11 15 6 21 SANDY 59.8 82.1 58 219 +1989 10 3 12 25 PATTY 13.1 214.2 151 65 +1966 11 6 0 14 GORDON 33.9 106.9 21 352 +1951 11 1 18 28 WILLIAM 54.4 66.7 82 772 +1953 2 28 12 11 HELENE 64.5 208.8 89 270 +1976 2 19 12 9 DEBBY 65.7 174.4 127 873 +1977 8 21 18 8 WILLIAM 38.9 164.3 146 632 +2004 7 9 6 7 WILLIAM 14.7 1.2 74 49 +1989 7 23 0 2 RAFAEL 36.2 171.7 129 413 +1973 3 14 6 1 WILLIAM 64.6 323.8 49 124 +1963 7 10 12 1 GORDON 53.5 102.9 39 435 +1989 2 20 6 8 GORDON 30.3 57.2 87 300 +2000 1 2 0 6 PATTY 62.2 79.9 109 387 +1984 4 15 0 13 BERYL 22.6 86.3 115 869 +1992 7 20 18 2 RAFAEL 20.5 26.2 137 191 +1970 5 22 0 18 MICHAEL 17.9 108.5 143 552 +1976 3 12 6 9 HELENE 32.4 114.5 129 464 +1958 12 17 6 9 ALBERTO 43.9 348.2 132 745 +1974 11 12 12 9 HELENE 59.1 286.5 97 16 +1975 3 6 0 28 BERYL 66.7 184.5 55 261 +1960 4 20 0 17 FLORENCE 50.5 350.7 150 828 +1974 11 13 12 21 ALBERTO 63.2 171.2 16 278 +1995 6 26 6 26 WILLIAM 66.2 178.8 72 408 +1993 3 28 18 4 KIRK 8.6 76.2 133 66 +1976 8 4 18 12 CHRIS 30.5 158.8 112 488 +1966 1 14 18 6 KIRK 62.2 209.7 112 44 +1955 8 11 0 27 WILLIAM 62.9 127.5 24 588 +1995 8 25 6 14 JOYCE 16.0 81.9 153 499 +1995 12 16 18 10 ISAAC 40.0 168.9 112 324 +1970 2 8 0 8 NADINE 61.3 349.1 163 421 +1953 4 22 18 7 MICHAEL 64.1 124.7 10 413 +1960 7 6 18 20 FLORENCE 17.0 24.9 67 433 +1960 5 27 12 9 KIRK 45.4 38.7 12 30 +1967 5 19 12 27 ERNESTO 60.3 108.8 133 886 +1967 11 10 18 13 ALBERTO 10.2 302.0 58 177 +2003 2 16 0 19 TONY 56.4 252.7 125 176 +1966 11 21 18 15 GORDON 20.2 228.9 60 629 +1957 3 5 18 22 VALERIE 56.0 150.3 160 842 +1984 4 28 18 16 PATTY 43.5 247.9 145 382 +2000 10 10 18 25 HELENE 13.3 198.5 134 235 +2002 8 21 18 20 BERYL 44.6 199.2 93 179 +1990 9 16 6 13 VALERIE 52.8 217.2 42 169 +1977 10 17 18 19 PATTY 30.0 287.2 51 764 +1974 6 2 18 19 JOYCE 58.0 7.4 21 717 +1992 10 20 12 15 JOYCE 50.4 156.1 92 284 +1967 10 14 18 21 VALERIE 56.0 215.6 64 637 +1953 10 18 12 11 CHRIS 31.0 183.6 80 225 +1978 1 13 12 28 ISAAC 39.9 336.6 42 717 +1955 4 26 6 1 PATTY 69.2 337.0 69 719 +1977 4 16 6 7 OSCAR 37.6 237.6 46 668 +1955 1 18 12 1 SANDY 54.8 233.4 82 833 +1968 2 11 6 13 GORDON 16.9 76.3 40 800 +2003 6 4 6 5 FLORENCE 7.9 324.5 97 892 +1965 9 16 12 22 ALBERTO 63.3 282.1 145 364 +1983 1 23 12 25 WILLIAM 66.2 97.0 65 691 +1963 1 11 6 8 CHRIS 19.3 93.8 54 840 +1971 10 3 18 8 TONY 11.2 335.4 100 301 +1977 12 26 18 6 BERYL 52.8 119.9 93 415 +1987 11 12 18 20 PATTY 67.2 287.8 84 698 +1979 7 2 18 17 OSCAR 56.7 26.2 60 279 +1950 7 26 6 3 MICHAEL 51.3 97.9 96 346 +1950 5 2 6 19 BERYL 56.7 257.9 57 417 +1976 5 23 6 27 RAFAEL 52.8 205.0 130 802 +1978 2 21 18 25 PATTY 21.3 129.5 120 71 +1977 7 21 12 4 KIRK 55.7 162.4 80 623 +1994 2 4 18 12 OSCAR 11.0 183.1 62 221 +1985 12 24 18 26 OSCAR 28.9 53.1 95 780 +1986 10 24 18 8 LESLIE 39.0 185.2 43 240 +1983 8 11 12 21 KIRK 9.3 47.7 51 392 +1954 1 16 18 12 SANDY 10.8 228.6 93 78 +1988 5 2 0 23 TONY 17.6 82.1 70 882 +1955 7 13 6 26 FLORENCE 59.1 274.0 144 853 +1957 3 17 6 14 LESLIE 14.2 280.5 141 120 +1961 1 1 6 19 FLORENCE 65.2 156.1 156 633 +1978 9 14 12 7 RAFAEL 16.9 47.6 52 254 +1971 9 3 0 5 ISAAC 8.4 206.7 85 841 +1984 4 15 18 27 OSCAR 42.5 167.9 84 359 +1952 10 20 12 14 NADINE 47.4 35.6 33 54 +2002 2 22 0 27 GORDON 17.3 167.5 145 680 +1962 5 8 6 15 OSCAR 63.0 262.0 10 295 +1995 11 28 12 3 LESLIE 51.4 194.3 123 226 +1964 3 16 6 22 KIRK 65.1 187.0 127 641 +1970 7 9 12 23 HELENE 67.3 199.0 62 310 +1984 1 7 0 3 LESLIE 33.0 195.2 79 290 +1988 8 5 18 8 ISAAC 9.4 261.6 30 203 +1967 1 10 0 6 LESLIE 21.4 82.9 19 892 +1958 12 27 6 17 ISAAC 34.7 232.8 164 583 +1955 10 12 18 7 VALERIE 41.3 264.5 81 100 +1989 5 6 0 18 TONY 68.5 334.8 128 335 +1983 7 20 18 10 NADINE 22.8 340.9 84 687 +1992 5 14 12 1 TONY 53.6 215.5 27 249 +1990 11 3 6 25 ERNESTO 39.9 305.8 125 336 +1994 2 5 0 28 KIRK 36.8 137.2 150 507 +1967 1 25 12 25 HELENE 34.2 208.4 74 108 +1957 2 21 12 14 WILLIAM 26.3 95.7 138 850 +2004 12 26 0 28 ERNESTO 55.4 221.9 160 891 +1969 5 23 6 19 SANDY 40.4 67.6 51 660 +1963 3 6 0 21 FLORENCE 28.0 155.7 14 48 +1984 5 24 12 13 CHRIS 37.3 268.5 136 115 +1956 10 9 6 24 GORDON 65.6 4.5 55 770 +1973 11 21 6 19 LESLIE 16.9 282.0 17 730 +1981 5 16 6 28 PATTY 69.8 75.9 105 790 +1955 12 11 12 26 OSCAR 7.1 41.8 164 41 +1952 5 15 0 1 SANDY 41.8 53.4 128 72 +1994 7 6 0 3 KIRK 35.0 357.7 92 875 +1960 7 17 6 24 MICHAEL 60.0 117.8 122 211 +1962 10 21 0 12 LESLIE 56.7 50.7 50 91 +1964 7 15 12 27 OSCAR 61.7 108.9 103 225 +1959 10 4 18 27 JOYCE 8.4 225.9 155 606 +1975 12 10 12 22 SANDY 11.5 47.6 123 21 +1981 1 3 6 11 ISAAC 13.7 31.5 87 207 +1984 6 2 18 25 VALERIE 40.7 68.7 103 847 +2002 3 5 12 3 LESLIE 25.0 204.3 147 34 +1990 5 22 18 11 LESLIE 23.8 62.1 119 880 +1958 11 16 0 14 PATTY 23.9 292.2 86 508 +1978 12 2 0 6 TONY 60.6 136.5 26 502 +1975 1 2 18 25 KIRK 12.4 49.5 116 258 +1974 3 23 6 15 VALERIE 35.7 26.7 128 889 +1983 7 9 12 7 OSCAR 11.5 63.7 18 823 +1982 8 18 6 7 NADINE 32.7 53.3 47 505 +1969 8 21 0 11 PATTY 19.5 69.9 53 575 +1977 5 1 18 11 VALERIE 43.8 107.0 139 121 +1979 12 19 18 18 GORDON 55.2 132.4 135 188 +1969 3 10 6 5 DEBBY 20.3 40.8 154 538 +2002 4 17 18 12 WILLIAM 43.1 118.3 138 457 +1977 5 7 6 6 HELENE 37.2 248.6 31 314 +1980 11 16 12 27 GORDON 64.3 129.1 149 578 +1959 3 14 6 26 RAFAEL 40.0 140.8 130 577 +1956 7 15 18 26 JOYCE 41.0 58.9 158 672 +1957 7 3 0 8 VALERIE 29.6 36.0 63 676 +1994 10 17 0 20 WILLIAM 27.7 199.8 151 764 +1961 1 13 18 2 ALBERTO 60.8 30.8 18 360 +1991 1 2 6 25 VALERIE 67.4 31.1 108 752 +1967 11 25 6 12 BERYL 12.0 203.2 129 525 +1969 8 8 0 11 ERNESTO 23.6 212.5 33 22 +1965 3 23 12 12 CHRIS 13.2 25.6 37 16 +1977 6 25 0 16 FLORENCE 60.5 72.0 82 561 +1978 9 27 6 2 ISAAC 34.4 211.0 149 129 +1970 11 8 18 1 RAFAEL 32.8 183.7 109 334 +1981 12 18 18 21 CHRIS 21.3 172.4 90 726 +1983 2 25 0 16 FLORENCE 23.7 63.8 144 24 +1996 4 22 12 24 NADINE 36.4 157.6 77 371 +1970 5 24 12 16 ISAAC 51.3 165.1 55 396 +1959 1 2 6 18 HELENE 65.2 89.5 155 852 +1993 11 17 6 4 HELENE 31.6 50.0 138 746 +1974 3 24 0 8 BERYL 68.4 309.2 76 730 +1961 7 7 6 18 DEBBY 34.0 154.1 87 277 +1961 1 19 18 17 FLORENCE 63.5 133.3 149 510 +1989 10 19 0 16 HELENE 34.9 104.4 65 211 +2001 11 7 0 12 PATTY 64.4 277.6 67 643 +1960 10 23 18 19 FLORENCE 35.7 309.3 64 275 +2000 4 19 12 5 SANDY 25.0 199.5 159 36 +1963 12 25 6 27 WILLIAM 25.9 105.3 87 899 +1962 7 28 6 27 MICHAEL 61.4 227.1 110 835 +1957 6 1 12 6 WILLIAM 27.3 339.4 93 11 +1995 10 11 0 17 ISAAC 66.4 48.5 40 40 +1967 12 6 12 26 JOYCE 63.3 260.2 102 547 +1990 5 15 0 21 SANDY 64.8 249.2 152 657 +1979 12 24 18 3 ISAAC 29.9 151.6 79 439 +2004 5 19 0 19 GORDON 25.6 1.0 21 812 +1956 7 4 12 25 GORDON 46.0 291.2 43 505 +2001 9 4 18 6 WILLIAM 47.8 187.4 78 197 +2003 11 23 18 13 ISAAC 13.0 244.5 32 402 +2001 11 9 6 2 CHRIS 26.8 181.5 159 415 +1997 9 7 18 13 FLORENCE 50.3 124.4 135 720 +1970 11 6 12 26 WILLIAM 31.2 143.0 126 492 +1958 5 4 18 3 SANDY 66.7 223.6 131 149 +1955 12 22 18 15 BERYL 12.7 254.6 39 852 +1957 5 13 0 21 ISAAC 18.7 294.3 123 148 +1987 4 16 18 4 NADINE 22.3 77.3 129 527 +1954 1 13 0 10 WILLIAM 48.8 72.2 124 496 +1983 9 19 0 6 NADINE 14.3 212.5 48 394 +2001 8 21 18 26 BERYL 24.2 299.2 108 751 +1997 9 7 12 2 PATTY 7.9 152.1 161 791 +1995 4 3 18 20 GORDON 8.8 270.7 133 825 +1982 11 18 0 6 CHRIS 69.7 51.9 37 414 +1968 6 10 0 27 MICHAEL 49.5 295.0 88 887 +1999 1 18 12 23 ALBERTO 68.8 304.4 47 549 +1957 8 25 18 5 GORDON 15.3 297.2 37 110 +1964 8 10 18 21 PATTY 10.2 100.0 99 359 +1986 5 4 6 17 WILLIAM 29.9 309.8 96 756 +1970 3 20 6 22 SANDY 54.6 267.2 59 302 +1954 4 9 12 16 LESLIE 54.4 353.0 145 465 +1978 6 12 0 9 SANDY 28.5 113.5 61 180 +1950 6 14 18 19 BERYL 14.8 15.5 11 897 +1958 11 3 18 23 FLORENCE 21.8 295.6 151 417 +1965 8 8 0 23 JOYCE 9.1 35.2 161 49 +1997 12 1 6 18 ERNESTO 48.8 101.5 118 113 +1967 1 13 12 17 MICHAEL 38.2 222.0 10 516 +1995 7 13 18 5 BERYL 12.2 6.7 120 419 +1997 9 23 0 25 DEBBY 15.9 31.2 163 374 +1995 1 16 0 24 PATTY 53.9 153.9 93 899 +1961 4 8 6 21 GORDON 36.5 284.1 25 25 +1997 5 19 12 23 CHRIS 23.0 5.0 37 365 +1950 3 10 18 28 BERYL 37.8 289.8 16 443 +1972 5 2 12 4 LESLIE 27.8 219.1 151 133 +1993 7 11 18 14 VALERIE 69.2 259.7 89 448 +1962 9 23 6 26 JOYCE 65.6 179.4 100 822 +2004 6 15 18 8 MICHAEL 47.0 182.9 40 248 +1968 8 7 18 18 ALBERTO 7.9 319.9 31 877 +1966 9 5 18 6 BERYL 57.1 2.6 16 155 +1979 3 16 18 2 MICHAEL 57.4 185.0 78 547 +1973 6 10 0 12 NADINE 17.7 291.2 11 130 +1967 12 25 0 20 BERYL 24.4 78.3 145 770 +1951 3 18 18 24 NADINE 34.0 237.9 100 92 +1959 9 24 12 7 GORDON 21.3 185.2 15 88 +1980 10 13 18 9 PATTY 65.5 257.3 96 136 +1953 1 5 0 9 KIRK 22.4 132.9 43 710 +1979 12 17 18 1 LESLIE 68.2 197.4 119 388 +1986 9 27 6 20 ISAAC 54.5 347.8 50 439 +1972 1 9 6 5 NADINE 44.2 99.0 115 475 +1985 6 20 0 18 ERNESTO 12.4 72.4 97 490 +2004 12 21 6 13 ISAAC 21.5 341.4 78 628 +2002 2 7 0 13 ALBERTO 63.6 117.5 122 550 +1988 7 7 18 26 WILLIAM 58.8 131.5 116 751 +1992 6 18 0 8 TONY 25.8 41.2 121 501 +1997 12 8 0 27 ERNESTO 52.9 313.5 164 632 +1956 11 12 18 1 SANDY 14.1 141.9 126 452 +1952 7 17 0 10 FLORENCE 33.2 356.6 46 426 +1983 3 5 6 7 ISAAC 13.6 346.5 69 300 +1960 10 18 18 26 CHRIS 49.8 151.6 71 522 +1962 12 19 0 5 CHRIS 54.5 58.8 142 862 +1977 3 22 6 8 LESLIE 37.3 15.2 38 367 +1971 12 1 18 4 PATTY 59.9 323.7 120 849 +1990 12 9 6 27 DEBBY 38.8 341.0 110 681 +1989 3 23 18 11 SANDY 50.1 156.7 99 809 +1991 6 2 0 18 MICHAEL 68.5 63.8 89 207 +1988 1 27 0 14 ALBERTO 54.7 37.7 69 723 +1962 5 8 0 11 KIRK 44.2 208.0 106 750 +1958 5 21 12 15 PATTY 55.5 22.8 155 694 +1999 6 18 18 14 WILLIAM 17.0 127.9 24 737 +1964 11 15 12 7 MICHAEL 52.3 84.4 46 698 +1987 8 15 6 20 KIRK 32.8 26.2 49 305 +1956 11 2 12 8 LESLIE 67.3 146.4 65 246 +1995 7 19 18 20 JOYCE 66.3 159.3 52 674 +1984 10 12 12 6 RAFAEL 60.7 77.2 136 409 +1995 4 18 0 14 HELENE 19.9 134.4 107 481 +1985 1 6 0 13 GORDON 64.0 340.7 79 653 +1962 2 15 18 27 RAFAEL 14.5 309.3 42 798 +1969 5 6 0 18 FLORENCE 58.4 4.6 139 324 +1993 1 27 12 3 KIRK 60.5 238.1 14 291 +1972 11 14 6 21 ISAAC 22.4 213.2 22 456 +2002 4 7 0 3 LESLIE 34.4 249.4 88 209 +1981 10 10 18 24 PATTY 21.8 284.9 42 650 +1986 12 16 6 25 JOYCE 40.9 96.3 160 34 +1987 10 11 18 25 MICHAEL 28.2 253.5 69 625 +1985 5 9 18 20 BERYL 56.0 218.5 139 204 +1972 9 10 6 9 PATTY 54.1 125.1 66 356 +1974 4 12 18 10 SANDY 43.5 185.9 92 716 +1994 3 18 12 27 NADINE 32.7 26.0 12 536 +1992 10 21 6 27 JOYCE 23.7 105.3 142 116 +2003 8 23 12 4 VALERIE 46.4 21.8 99 395 +1980 6 20 12 26 WILLIAM 61.9 0.9 61 392 +1963 9 1 12 1 TONY 43.6 318.7 122 846 +1996 6 8 0 1 CHRIS 54.8 25.2 25 108 +1956 1 28 12 9 HELENE 19.6 357.8 12 403 +1960 8 6 6 4 VALERIE 60.2 72.7 53 614 +1986 2 26 18 17 MICHAEL 18.3 103.8 102 423 +1992 6 23 0 9 FLORENCE 17.2 16.3 23 605 +1984 11 20 18 21 OSCAR 15.0 7.8 66 359 +1959 1 9 12 8 GORDON 42.9 278.0 47 303 +1951 6 7 12 3 NADINE 48.2 20.1 98 120 +1962 2 6 18 9 HELENE 16.5 3.7 65 628 +2000 3 1 6 11 ALBERTO 19.7 98.5 144 140 +1962 12 9 0 19 RAFAEL 42.4 4.0 23 648 +1981 6 20 18 17 ISAAC 43.7 45.4 77 37 +1998 12 28 0 19 ISAAC 56.8 233.0 28 529 +2001 11 17 18 13 JOYCE 54.4 300.0 81 865 +1987 2 20 18 2 GORDON 38.9 301.7 134 351 +1983 4 26 12 17 MICHAEL 26.1 314.2 42 230 +1961 12 5 0 23 GORDON 37.7 2.9 84 621 +1976 3 17 18 7 LESLIE 55.9 47.7 67 459 +1993 5 7 12 5 SANDY 57.5 96.3 78 543 +1999 10 22 18 2 ALBERTO 53.8 1.5 118 739 +1971 6 9 18 3 TONY 61.9 318.7 137 177 +1974 5 22 18 13 ISAAC 39.3 226.9 163 139 +1967 8 23 18 21 CHRIS 44.7 34.9 112 668 +1972 11 23 0 4 ERNESTO 54.3 273.0 18 274 +1986 12 15 6 23 ISAAC 18.6 89.4 22 427 +1973 4 5 0 27 TONY 44.9 174.3 32 830 +1965 11 13 12 17 FLORENCE 24.0 223.0 97 266 +1953 9 20 18 11 PATTY 31.4 43.9 55 605 +1976 11 3 6 13 LESLIE 22.0 266.5 32 647 +1986 5 23 0 28 FLORENCE 58.6 43.8 15 378 +1952 1 20 6 4 LESLIE 65.7 242.7 30 203 +1986 2 25 18 17 HELENE 68.8 86.3 110 319 +1959 12 27 18 10 GORDON 16.6 65.7 101 468 +1964 7 2 18 7 KIRK 8.6 111.7 42 450 +1980 5 3 6 1 DEBBY 20.0 141.0 90 383 +1996 1 23 6 1 SANDY 50.4 110.6 97 138 +1979 6 14 0 16 WILLIAM 68.7 27.0 160 436 +1998 8 5 6 16 RAFAEL 46.7 339.3 90 431 +1975 6 20 0 12 TONY 52.7 280.3 12 524 +1963 9 6 18 21 ISAAC 10.3 349.1 128 146 +1954 7 10 6 9 FLORENCE 33.3 46.5 111 689 +1985 1 4 18 2 NADINE 59.7 263.7 66 682 +1981 1 3 18 28 LESLIE 21.4 313.6 158 354 +1971 5 4 6 21 JOYCE 40.5 33.6 14 166 +1985 3 28 6 23 SANDY 69.1 55.3 92 571 +1993 3 6 12 13 PATTY 63.4 312.8 134 352 +1950 12 20 0 10 RAFAEL 53.3 12.4 85 106 +1976 1 26 0 22 RAFAEL 26.6 25.1 155 785 +1985 1 10 6 28 JOYCE 61.6 236.1 88 209 +1959 6 7 18 24 NADINE 21.3 4.3 157 721 +1952 1 4 12 9 DEBBY 27.8 285.2 40 638 +1985 10 2 18 7 GORDON 40.6 291.5 26 156 +1959 8 5 12 23 ISAAC 7.5 181.8 89 745 +1982 11 4 12 20 DEBBY 31.2 41.4 61 645 +1951 6 4 18 17 PATTY 17.3 196.3 120 815 +1965 12 24 12 15 OSCAR 60.2 300.3 48 367 +1979 8 18 18 14 RAFAEL 41.0 20.9 66 116 +1959 6 19 12 6 OSCAR 46.5 159.2 73 616 +1951 12 14 6 15 BERYL 36.7 345.7 144 92 +2003 8 20 6 28 FLORENCE 20.1 1.9 67 458 +1964 9 25 12 13 VALERIE 62.5 342.1 144 470 +2000 9 21 18 23 FLORENCE 50.2 79.0 96 69 +1968 2 27 0 25 ALBERTO 44.8 9.3 52 601 +1962 11 7 0 27 GORDON 12.0 97.2 108 240 +2000 1 24 12 23 ERNESTO 36.8 323.4 160 642 +1964 10 4 18 21 DEBBY 31.9 70.0 85 364 +1985 7 2 12 14 LESLIE 53.4 256.9 69 128 +1969 5 27 18 6 TONY 68.6 157.5 54 13 +1988 9 7 12 20 CHRIS 15.3 311.0 144 502 +1977 12 21 18 26 MICHAEL 29.1 214.9 122 706 +1956 7 19 18 4 LESLIE 59.5 99.0 156 244 +1974 4 5 12 27 WILLIAM 35.8 167.1 82 506 +1952 4 17 6 26 FLORENCE 12.7 144.5 123 883 +1952 4 7 0 14 VALERIE 35.5 338.2 70 601 +1996 9 14 18 13 VALERIE 33.9 196.8 156 45 +1950 10 6 0 3 ALBERTO 21.8 224.8 138 20 +1976 6 3 0 22 TONY 15.4 346.0 117 96 +1976 8 18 12 18 RAFAEL 63.0 311.0 117 838 +1950 5 23 18 7 TONY 59.6 196.1 155 733 +1961 5 2 0 15 OSCAR 10.2 67.4 136 364 +1974 12 25 0 25 ERNESTO 47.5 113.2 25 599 +1959 4 27 18 17 ALBERTO 38.3 230.2 73 381 +1963 10 23 0 15 SANDY 51.1 65.2 129 393 +1959 1 27 18 13 LESLIE 21.4 137.9 75 694 +1988 5 4 6 27 VALERIE 17.9 149.4 24 679 +1966 6 6 12 3 KIRK 36.9 109.1 151 579 +1953 10 20 12 10 GORDON 22.5 141.8 84 154 +1994 4 15 0 16 RAFAEL 37.6 153.4 127 757 +1952 8 14 12 18 MICHAEL 60.7 223.8 51 251 +1980 10 12 0 10 FLORENCE 43.3 183.9 143 862 +1964 1 15 12 6 FLORENCE 33.3 242.9 95 682 +1982 10 5 18 11 RAFAEL 44.4 291.8 58 24 +2002 6 5 0 14 NADINE 43.6 344.0 70 859 +1979 10 16 12 3 TONY 64.3 207.5 44 658 +1975 9 6 6 22 LESLIE 48.2 5.4 18 190 +1985 5 14 6 14 VALERIE 57.0 50.1 91 782 +1974 3 6 12 28 CHRIS 16.4 53.0 135 750 +1960 9 17 12 15 BERYL 17.3 29.6 50 412 +1990 9 12 0 9 OSCAR 25.6 353.9 106 770 +1988 1 12 0 18 KIRK 38.2 279.5 79 881 +1999 1 8 6 3 LESLIE 23.7 171.8 99 687 +1990 6 6 6 2 JOYCE 44.8 286.4 48 12 +2003 5 11 0 8 JOYCE 23.9 53.1 118 101 +1955 10 21 18 15 JOYCE 7.3 208.8 22 710 +2003 11 28 0 18 NADINE 67.1 167.0 129 357 +1976 6 20 6 7 WILLIAM 22.1 131.9 57 401 +1959 6 27 12 6 SANDY 44.1 37.4 141 876 +1992 1 19 18 16 PATTY 11.8 130.8 102 825 +1963 6 13 6 25 FLORENCE 32.5 115.7 111 416 +1986 6 12 6 10 RAFAEL 19.3 115.2 138 794 +1992 12 4 18 12 FLORENCE 36.5 271.6 107 555 +1966 10 11 12 23 FLORENCE 52.4 132.7 157 562 +1956 7 14 0 10 GORDON 57.5 323.7 33 874 +2002 3 25 12 8 DEBBY 44.5 103.3 142 489 +1964 12 18 18 23 OSCAR 41.5 80.4 73 526 +1982 7 25 0 1 TONY 60.2 19.6 104 16 +1997 3 19 6 19 HELENE 50.7 240.9 24 68 +1954 1 4 18 11 NADINE 68.5 130.7 134 226 +1966 4 14 6 23 CHRIS 8.1 220.5 34 478 +1986 4 16 18 4 CHRIS 38.2 111.5 118 265 +1990 7 2 0 28 ISAAC 36.6 157.1 107 884 +1986 6 17 12 25 NADINE 57.4 118.8 39 888 +1988 2 19 6 5 ERNESTO 47.7 335.1 24 616 +1954 6 9 18 14 FLORENCE 14.9 80.9 21 402 +1960 6 1 6 1 MICHAEL 34.6 225.6 12 783 +1955 11 10 18 19 BERYL 55.9 138.8 160 719 +1986 4 6 12 23 RAFAEL 57.5 165.2 157 251 +1979 2 3 12 5 JOYCE 40.2 207.9 145 513 +1954 9 26 6 25 OSCAR 15.2 28.7 27 318 +1976 3 10 12 4 GORDON 10.4 70.2 82 78 +1958 6 21 6 1 NADINE 55.8 120.3 113 742 +1960 9 27 6 6 CHRIS 59.4 24.7 88 130 +1987 10 25 6 2 VALERIE 34.5 102.0 23 570 +1983 7 10 18 19 RAFAEL 42.2 227.7 154 11 +1966 9 13 12 18 OSCAR 27.9 173.5 66 178 +1975 1 2 0 13 RAFAEL 26.2 268.3 75 362 +1974 7 27 18 19 VALERIE 8.8 14.4 40 531 +1977 8 4 12 17 RAFAEL 38.8 193.7 90 435 +1994 9 14 0 5 TONY 49.6 258.2 140 582 +1978 11 1 6 13 RAFAEL 22.6 307.5 148 87 +1953 2 21 18 1 GORDON 17.7 158.2 60 482 +1977 11 24 12 8 VALERIE 37.4 306.2 162 703 +1998 9 14 18 13 JOYCE 57.1 59.3 155 431 +1985 10 4 12 10 WILLIAM 16.2 323.1 48 600 +1981 6 19 12 6 JOYCE 26.8 90.5 99 567 +1972 11 20 18 14 DEBBY 61.2 197.3 11 588 +1993 5 24 6 21 TONY 24.0 192.9 56 806 +1956 1 20 6 20 FLORENCE 17.3 76.1 32 827 +1990 1 26 0 2 FLORENCE 9.3 325.1 157 366 +1976 1 3 0 26 PATTY 65.5 348.7 61 597 +2000 5 25 0 4 OSCAR 44.2 128.7 116 203 +1975 7 25 18 11 FLORENCE 61.0 19.8 24 232 +1992 12 4 18 2 VALERIE 27.0 16.8 110 500 +1992 3 1 0 15 GORDON 29.8 319.2 114 409 +1950 5 12 0 20 JOYCE 36.2 250.5 130 361 +1995 8 12 0 8 ALBERTO 68.9 284.1 68 174 +1974 9 3 12 8 PATTY 56.1 289.6 146 269 +1968 7 18 18 7 TONY 52.8 116.8 127 348 +1992 4 2 6 21 NADINE 26.2 5.2 103 751 +1961 1 17 6 15 ISAAC 53.4 297.8 92 105 +1971 9 4 6 9 MICHAEL 61.9 271.6 59 401 +1989 12 24 6 22 HELENE 21.2 156.9 44 518 +1963 6 1 6 22 ERNESTO 36.4 347.1 75 433 +1958 6 23 6 1 OSCAR 37.2 304.9 17 802 +1967 9 16 12 2 MICHAEL 26.4 128.8 14 769 +1967 12 13 12 19 ERNESTO 66.7 295.7 124 258 +1982 7 17 18 21 RAFAEL 8.2 209.7 64 510 +1980 2 6 18 14 FLORENCE 55.2 69.5 120 195 +1966 12 26 12 6 VALERIE 33.7 225.0 75 512 +1969 6 8 12 3 LESLIE 18.4 220.6 106 898 +1958 7 13 0 16 SANDY 44.8 216.6 88 597 +1960 4 22 12 5 VALERIE 65.5 74.8 35 520 +1963 9 18 6 3 KIRK 48.8 96.3 67 47 +1956 9 12 6 13 TONY 24.0 25.1 149 569 +1995 8 19 18 17 KIRK 39.2 181.7 102 189 +1951 11 19 0 15 ISAAC 16.7 161.7 99 415 +1958 9 15 12 17 WILLIAM 52.4 225.4 71 386 +1960 2 20 18 27 FLORENCE 15.1 299.8 17 527 +2000 2 16 0 5 ISAAC 30.7 274.2 163 472 +1957 11 15 6 24 VALERIE 62.0 111.5 49 875 +1971 7 25 12 17 MICHAEL 50.9 311.2 126 387 +1959 10 9 6 7 RAFAEL 43.1 163.9 75 780 +1984 4 1 6 23 DEBBY 52.2 149.8 71 281 +1994 1 16 6 14 RAFAEL 48.4 248.0 137 444 +1991 2 27 0 18 JOYCE 20.7 170.7 88 476 +1959 7 25 0 3 ERNESTO 12.5 103.4 137 297 +1964 8 28 18 4 KIRK 66.3 100.4 63 297 +1956 9 19 12 26 BERYL 57.9 236.6 43 836 +1993 8 10 6 9 SANDY 16.8 11.9 25 566 +1971 5 14 6 2 BERYL 12.9 319.8 74 75 +1982 7 5 12 22 SANDY 51.4 207.0 142 537 +1972 4 12 18 22 MICHAEL 56.2 246.8 95 10 +1956 2 16 6 22 LESLIE 53.1 219.8 97 434 +1979 2 14 18 6 MICHAEL 23.9 312.1 126 97 +1955 7 12 6 14 WILLIAM 16.7 213.6 81 300 +1995 12 6 12 8 MICHAEL 61.2 268.0 119 215 +1996 10 10 18 14 JOYCE 40.6 239.8 18 652 +1960 6 2 12 5 FLORENCE 25.1 305.5 105 170 +1962 9 9 18 23 WILLIAM 37.6 95.6 32 158 +1988 10 25 0 15 SANDY 24.5 104.0 80 836 +1963 3 18 6 8 MICHAEL 18.8 32.9 112 300 +1972 2 18 12 10 TONY 61.3 71.1 160 377 +1964 4 15 18 7 ERNESTO 65.0 40.8 24 263 +1965 3 16 0 3 KIRK 25.8 253.1 16 520 +1996 10 27 6 2 GORDON 16.1 266.5 40 666 +1974 3 12 12 28 NADINE 51.7 205.5 48 725 +1955 6 8 6 7 LESLIE 52.7 183.8 83 178 +1960 1 16 12 2 BERYL 47.9 17.3 87 580 +1971 7 18 18 27 OSCAR 24.3 33.1 78 197 +2003 8 10 6 17 RAFAEL 41.9 286.8 28 261 +1982 5 21 12 16 NADINE 20.1 93.8 99 449 +1958 9 2 0 13 FLORENCE 41.5 84.0 125 238 +1967 5 12 12 12 CHRIS 49.4 59.2 26 462 +1967 1 11 18 8 SANDY 64.7 318.2 70 754 +2004 6 3 6 24 MICHAEL 8.6 147.9 151 138 +1992 7 3 6 26 ISAAC 27.6 330.1 105 323 +1991 1 12 12 2 DEBBY 41.7 102.6 20 820 +1983 7 10 0 26 DEBBY 62.1 173.7 27 221 +1986 4 3 12 2 DEBBY 35.2 275.1 149 577 +1981 4 27 6 22 DEBBY 36.7 6.4 59 679 +2003 3 19 18 16 MICHAEL 62.0 326.2 25 127 +1957 11 26 6 20 LESLIE 30.4 284.6 47 313 +1959 12 17 18 15 KIRK 7.9 329.5 61 636 +1958 11 3 12 10 FLORENCE 26.7 50.3 11 379 +1955 12 13 18 5 RAFAEL 55.4 139.3 107 208 +1985 8 19 0 2 TONY 19.8 311.5 60 512 +1956 1 17 6 12 FLORENCE 40.0 128.7 97 412 +1964 10 10 0 7 DEBBY 42.6 153.0 68 542 +1978 8 24 12 23 CHRIS 26.1 338.0 119 90 +1965 9 25 0 6 KIRK 55.9 90.5 89 580 +1982 8 23 6 15 PATTY 65.9 231.8 95 61 +1974 6 9 6 21 PATTY 59.3 286.0 147 185 +1959 5 6 12 11 TONY 30.2 316.4 144 678 +2002 8 8 0 16 JOYCE 61.7 341.9 159 199 +1953 2 8 6 9 ISAAC 48.2 178.1 91 236 +1981 10 19 0 19 BERYL 38.7 59.2 49 728 +1986 9 10 18 18 SANDY 14.8 176.4 115 716 +1990 4 25 12 12 SANDY 69.3 232.3 112 891 +1980 11 7 6 13 ISAAC 24.4 28.4 76 888 +1969 10 23 18 7 HELENE 29.3 101.5 28 672 +1971 1 5 18 6 CHRIS 38.8 24.6 98 266 +1964 4 11 6 19 MICHAEL 33.7 261.6 94 368 +1976 12 23 0 28 NADINE 9.0 173.0 147 37 +1961 9 3 18 26 TONY 28.4 13.4 11 774 +1972 8 4 6 8 SANDY 57.9 176.1 59 70 +1993 7 5 18 12 TONY 45.3 355.4 63 896 +1985 1 14 6 12 DEBBY 51.2 262.3 111 358 +1952 7 21 0 19 KIRK 31.5 38.1 140 839 +1990 6 12 0 24 WILLIAM 47.2 147.3 54 785 +1981 11 17 18 9 TONY 41.4 296.8 126 798 +1986 5 5 18 7 MICHAEL 16.2 98.5 126 321 +1967 5 19 6 18 RAFAEL 14.2 247.8 152 607 +1959 11 10 0 12 OSCAR 12.9 139.2 54 538 +1966 1 26 18 7 HELENE 13.3 233.2 78 574 +1990 6 17 18 8 ERNESTO 68.4 293.6 161 118 +1973 11 21 18 22 ALBERTO 29.7 352.6 105 681 +1979 2 4 0 25 PATTY 40.1 93.1 95 26 +1964 6 7 0 14 ERNESTO 36.5 23.7 78 600 +1956 6 23 0 24 LESLIE 18.8 235.8 25 3 +1970 3 12 6 11 ERNESTO 56.5 218.9 76 401 +1954 7 23 12 7 CHRIS 26.9 39.5 11 711 +1955 1 7 18 25 MICHAEL 44.8 354.1 22 666 +1975 4 2 0 9 OSCAR 13.7 75.9 121 389 +1960 10 13 12 3 HELENE 51.8 228.4 153 281 +1974 12 8 6 22 TONY 10.7 342.9 89 670 +1985 9 3 18 25 HELENE 51.2 135.1 157 123 +1963 8 5 6 20 ERNESTO 7.3 286.5 36 253 +2002 5 7 18 13 FLORENCE 19.8 278.4 122 813 +1985 1 17 0 10 OSCAR 16.4 68.1 108 5 +1951 3 18 6 17 PATTY 54.1 322.5 64 334 +1960 3 23 6 6 TONY 21.4 235.4 160 872 +1952 2 16 18 6 NADINE 65.5 337.5 53 422 +1953 2 16 6 14 VALERIE 65.1 48.1 130 315 +1989 7 25 18 14 DEBBY 44.6 95.5 38 480 +1991 4 7 18 25 VALERIE 42.4 100.9 122 355 +1958 10 15 18 4 KIRK 16.1 6.6 14 610 +1955 4 6 0 19 CHRIS 19.7 130.5 94 803 +1980 10 4 6 23 NADINE 69.7 35.6 42 16 +1973 9 17 6 24 DEBBY 11.1 236.4 50 32 +1968 9 9 12 7 DEBBY 24.0 286.3 129 538 +1954 8 10 12 2 ALBERTO 24.2 204.4 100 415 +1986 3 13 18 19 RAFAEL 53.3 109.9 43 199 +1986 1 6 18 25 JOYCE 27.2 210.7 143 700 +1957 10 23 18 21 ISAAC 24.2 159.6 92 121 +1964 1 19 0 21 MICHAEL 45.6 298.0 87 407 +1977 1 5 12 1 FLORENCE 40.1 332.5 23 796 +1980 9 11 0 16 ISAAC 52.5 283.7 87 447 +1981 2 7 0 11 GORDON 37.6 247.6 162 529 +1979 8 17 18 8 CHRIS 14.9 145.1 44 734 +1992 8 21 0 8 PATTY 69.9 185.1 71 509 +1996 6 4 0 5 GORDON 68.8 257.3 45 350 +1952 6 28 0 4 JOYCE 40.7 284.4 25 659 +1970 4 25 18 26 MICHAEL 69.0 32.4 55 827 +1982 7 7 18 22 FLORENCE 30.5 337.1 39 240 +1985 9 21 12 7 WILLIAM 66.8 22.1 144 727 +1986 3 28 6 12 VALERIE 69.0 194.7 151 95 +1962 2 6 0 19 TONY 14.5 315.7 29 809 +1953 6 8 12 15 SANDY 54.5 237.6 90 242 +1963 4 11 0 15 ISAAC 16.2 326.8 34 312 +1971 10 22 0 2 HELENE 62.1 218.6 163 448 +1961 7 27 6 20 GORDON 47.3 148.9 105 242 +1977 5 24 6 2 SANDY 40.1 196.1 130 98 +1969 4 20 12 25 HELENE 43.9 5.4 63 29 +1957 9 7 12 11 GORDON 8.8 339.6 112 893 +1982 12 24 18 15 PATTY 38.9 58.7 127 413 +1996 8 16 12 12 HELENE 41.1 247.0 53 29 +1977 12 23 18 20 GORDON 19.2 332.3 159 78 +2002 12 26 6 9 LESLIE 48.1 104.0 71 444 +1954 10 2 0 11 KIRK 35.7 285.8 129 562 +1994 11 13 6 3 ISAAC 34.4 187.8 87 313 +1979 2 6 12 28 CHRIS 62.5 187.9 122 212 +1971 3 3 18 28 MICHAEL 34.0 169.4 136 125 +1986 9 16 6 22 SANDY 56.3 58.8 93 827 +1951 9 8 6 28 MICHAEL 59.5 80.7 27 449 +1980 8 14 18 22 ALBERTO 21.3 20.0 16 780 +1996 1 28 18 21 VALERIE 29.6 166.2 163 560 +2000 2 20 0 26 VALERIE 44.1 349.0 41 862 +1990 5 4 6 28 ERNESTO 62.8 228.9 141 14 +1950 4 19 6 22 SANDY 60.0 34.1 81 277 +1974 7 23 6 22 ISAAC 28.8 236.8 21 761 +1954 10 4 18 10 RAFAEL 21.8 320.3 101 597 +1963 5 6 12 25 RAFAEL 25.8 175.3 85 820 +1956 3 25 6 2 DEBBY 54.9 91.0 116 223 +1998 12 6 18 4 WILLIAM 56.0 190.9 37 320 +1956 5 26 6 26 PATTY 68.9 170.4 116 123 +1952 2 10 0 17 KIRK 56.4 54.3 116 761 +1953 7 24 12 17 PATTY 16.7 132.1 103 833 +1993 11 15 12 17 ALBERTO 10.6 275.0 82 366 +1960 12 14 18 17 WILLIAM 21.6 128.7 13 498 +1979 1 25 0 13 WILLIAM 37.2 230.5 142 682 +1953 2 18 18 16 RAFAEL 67.6 175.3 71 115 +1985 9 27 6 5 ERNESTO 21.3 89.3 12 739 +1995 10 25 12 22 FLORENCE 19.5 87.1 78 420 +1958 5 26 6 28 WILLIAM 31.7 198.6 70 836 +1977 11 21 0 7 SANDY 46.1 64.8 127 43 +1966 10 23 6 28 TONY 56.0 116.6 70 855 +1999 12 11 0 2 JOYCE 53.3 268.8 123 446 +1990 8 5 18 9 NADINE 48.0 138.9 74 449 +1995 5 16 6 24 WILLIAM 53.4 330.6 76 226 +1973 12 10 0 25 VALERIE 69.0 64.2 42 548 +1979 1 17 0 2 ALBERTO 31.4 241.0 54 661 +1976 12 5 18 19 HELENE 51.7 7.9 138 785 +1975 9 24 12 15 NADINE 53.5 48.3 112 833 +1950 12 24 0 25 ISAAC 34.6 37.6 151 367 +1990 3 14 6 17 BERYL 41.9 151.9 72 341 +1960 1 19 12 16 RAFAEL 43.6 276.1 121 542 +1989 7 9 6 12 MICHAEL 38.3 40.3 49 449 +1996 1 1 6 7 ALBERTO 45.1 15.8 64 232 +1974 2 10 12 12 MICHAEL 61.7 227.5 124 75 +1951 10 7 18 1 RAFAEL 12.9 7.1 102 577 +1954 7 18 18 24 VALERIE 14.2 210.7 132 391 +1956 10 3 6 19 NADINE 38.2 148.5 46 208 +1962 8 27 12 24 OSCAR 45.6 116.7 15 92 +1966 12 24 6 25 WILLIAM 50.5 212.7 150 320 +1995 1 6 12 28 GORDON 12.5 218.2 155 543 +1963 4 9 0 9 PATTY 18.7 342.7 151 436 +1984 7 11 18 14 JOYCE 14.5 333.1 30 868 +1964 1 15 6 19 TONY 18.9 86.6 111 16 +2002 6 22 6 26 HELENE 38.1 278.9 71 565 +1994 5 21 12 1 TONY 36.7 146.3 60 320 +1989 8 27 18 13 HELENE 23.9 147.3 90 486 +1997 5 8 18 21 LESLIE 57.2 88.2 53 700 +1950 11 11 12 20 TONY 36.9 103.3 148 299 +2004 9 2 6 2 BERYL 10.4 222.8 43 68 +1960 9 22 12 7 BERYL 27.7 79.3 55 783 +1959 7 14 6 15 LESLIE 45.5 288.4 15 591 +1976 3 4 12 14 DEBBY 9.8 5.9 48 189 +2000 10 24 0 7 BERYL 60.7 246.8 142 155 +1994 10 14 6 3 NADINE 67.2 253.9 25 700 +1991 5 25 12 21 FLORENCE 69.9 157.5 115 813 +1996 6 1 12 7 TONY 13.5 338.3 103 584 +1986 3 9 18 3 TONY 60.8 7.1 31 531 +2003 8 10 0 27 OSCAR 10.0 12.0 11 786 +1990 4 28 6 10 RAFAEL 25.6 322.1 51 148 +1970 4 22 18 4 PATTY 17.6 90.7 125 143 +1999 3 4 18 17 VALERIE 40.6 136.5 128 325 +1969 3 3 0 1 CHRIS 60.9 188.3 88 865 +1979 4 18 18 12 RAFAEL 25.1 335.8 142 801 +1991 4 6 12 21 VALERIE 13.0 153.3 62 335 +1965 7 9 18 13 ISAAC 7.9 41.9 150 846 +1960 10 21 6 28 FLORENCE 21.8 6.0 83 377 +1950 5 12 0 15 HELENE 57.7 18.1 38 292 +1983 11 25 18 1 NADINE 60.8 52.5 50 299 +1964 8 26 18 8 DEBBY 26.5 267.6 94 71 +1960 9 8 12 1 FLORENCE 28.9 126.4 132 544 +1982 1 17 12 6 MICHAEL 57.8 183.0 81 747 +1974 1 12 0 26 LESLIE 31.8 130.3 146 173 +1977 4 10 0 27 MICHAEL 25.1 201.4 148 151 +1993 8 12 12 14 RAFAEL 25.2 307.2 79 708 +1997 2 12 6 1 OSCAR 14.2 95.1 54 561 +1997 3 6 12 15 BERYL 16.6 167.9 106 647 +1969 4 9 12 25 LESLIE 33.4 345.2 140 291 +1953 6 25 0 10 LESLIE 13.8 250.2 43 630 +1955 7 19 18 28 FLORENCE 50.6 239.0 99 580 +1968 3 15 12 12 DEBBY 63.1 326.9 125 420 +2001 11 7 0 22 FLORENCE 37.6 61.0 53 137 +1989 1 4 12 27 LESLIE 32.9 81.0 90 400 +1960 11 1 0 9 GORDON 20.3 59.2 111 360 +1972 5 20 0 7 RAFAEL 53.5 298.0 110 707 +1977 5 14 0 14 LESLIE 20.1 89.6 63 91 +1981 3 21 18 14 NADINE 24.5 272.1 13 828 +1978 5 5 12 21 SANDY 48.6 173.8 38 816 +1994 8 7 18 16 BERYL 8.9 249.9 92 720 +1979 4 12 18 19 PATTY 29.3 196.0 99 894 +2000 9 10 12 20 CHRIS 35.9 343.9 117 322 +2004 9 11 6 16 FLORENCE 40.6 164.6 86 546 +2003 1 23 12 1 NADINE 62.1 206.5 115 59 +1970 8 27 12 9 NADINE 21.8 200.6 74 616 +2004 9 13 18 14 WILLIAM 11.6 108.0 163 485 +2003 4 1 0 26 TONY 54.0 173.3 76 101 +1953 7 24 6 5 WILLIAM 38.5 249.3 57 178 +1993 2 16 18 10 MICHAEL 38.0 146.3 51 765 +1988 9 22 0 22 JOYCE 62.6 200.7 133 349 +2002 2 18 18 24 MICHAEL 8.4 72.6 141 659 +1997 10 2 18 10 ERNESTO 54.1 109.3 144 268 +1964 10 16 0 15 JOYCE 62.1 158.2 83 796 +1961 10 15 6 11 KIRK 21.8 92.7 94 629 +2003 9 2 18 23 RAFAEL 29.6 9.0 83 769 +1991 1 22 12 23 HELENE 66.9 142.5 51 112 +1962 4 2 18 1 JOYCE 41.7 36.6 85 396 +1987 12 19 12 6 ALBERTO 34.9 342.3 41 223 +1975 4 9 18 28 OSCAR 11.5 10.1 59 446 +1975 6 24 0 4 VALERIE 54.4 253.5 16 415 +1955 2 3 18 2 CHRIS 20.4 128.4 28 273 +1953 6 20 0 27 FLORENCE 51.5 71.4 54 733 +2001 6 25 6 21 JOYCE 19.4 144.7 51 500 +1980 10 11 18 13 JOYCE 54.1 249.5 140 499 +1997 5 20 6 27 MICHAEL 39.7 354.0 101 838 +1978 5 26 12 7 SANDY 13.5 334.8 110 632 +1972 9 15 6 16 OSCAR 62.8 217.9 40 759 +1983 11 18 12 9 ALBERTO 18.4 221.0 24 107 +1965 8 12 6 5 DEBBY 11.8 222.0 89 842 +1961 11 10 12 27 ISAAC 69.2 89.3 96 843 +1988 3 15 18 24 KIRK 13.4 119.3 121 787 +1989 1 5 12 5 HELENE 61.2 166.9 96 463 +1984 5 23 6 19 TONY 63.6 273.4 45 641 +1968 3 10 12 28 ALBERTO 45.0 179.4 139 336 +1997 1 6 0 2 LESLIE 16.7 105.6 126 732 +1985 1 6 12 4 GORDON 38.4 188.0 52 70 +1989 6 5 18 23 SANDY 60.6 213.1 82 143 +1959 2 19 18 23 LESLIE 62.8 135.6 87 102 +1976 4 25 0 9 CHRIS 8.2 216.6 44 867 +1964 4 6 6 25 BERYL 43.8 188.9 157 646 +1950 10 17 6 18 ERNESTO 29.4 156.4 53 264 +2004 11 13 0 6 BERYL 16.9 11.1 138 215 +1973 12 2 18 15 OSCAR 20.0 121.7 83 361 +2002 2 9 18 6 RAFAEL 15.7 179.1 73 546 +1973 5 24 18 25 ERNESTO 60.2 177.4 69 107 +1965 8 28 6 5 DEBBY 39.0 241.0 101 279 +1951 10 5 18 26 HELENE 34.2 309.1 27 665 +1970 3 21 0 14 ALBERTO 51.0 331.6 64 814 +1999 3 6 0 5 KIRK 58.4 16.5 108 250 +1954 3 12 18 20 GORDON 22.4 66.9 104 492 +1976 10 16 6 4 MICHAEL 55.0 15.1 56 725 +2003 11 7 0 19 VALERIE 13.2 199.3 12 236 +1969 10 11 0 7 OSCAR 55.8 253.7 12 580 +1974 12 14 18 21 GORDON 32.4 191.1 111 780 +1967 6 5 12 4 ERNESTO 17.6 25.4 148 20 +1952 1 7 6 12 FLORENCE 9.3 326.9 67 858 +1954 5 2 0 8 LESLIE 8.5 298.5 149 89 +2002 6 23 12 7 WILLIAM 66.5 289.7 104 434 +1976 6 13 6 9 PATTY 23.4 125.5 14 580 +1962 4 5 0 20 TONY 65.8 257.7 60 555 +1975 10 14 6 3 DEBBY 11.0 231.2 81 479 +1982 8 23 6 1 RAFAEL 62.4 52.6 61 212 +1955 1 13 12 17 KIRK 31.4 273.8 19 891 +1960 5 22 18 21 DEBBY 41.6 166.1 94 872 +1991 1 11 18 3 HELENE 20.1 25.2 121 753 +1954 4 13 0 3 LESLIE 32.2 347.8 89 170 +1953 10 8 12 12 FLORENCE 54.8 159.7 124 115 +1970 10 24 12 10 ALBERTO 60.2 94.1 97 223 +1959 2 27 12 7 ERNESTO 31.7 68.4 116 353 +1959 11 4 12 15 JOYCE 46.8 135.3 53 434 +1979 2 4 12 2 BERYL 21.2 175.9 31 67 +1979 6 13 12 21 PATTY 51.5 148.9 56 364 +1986 3 25 0 8 SANDY 64.7 284.5 17 879 +1981 10 26 12 5 GORDON 12.0 93.3 128 531 +1962 2 26 0 16 FLORENCE 23.0 59.6 72 206 +1952 1 4 6 11 BERYL 49.8 221.7 66 476 +1954 1 9 18 7 ALBERTO 61.9 266.8 133 292 +2004 7 23 18 28 RAFAEL 45.1 26.6 148 782 +1993 8 7 12 26 GORDON 23.0 190.6 60 66 +1958 12 28 12 19 DEBBY 36.5 327.2 158 199 +1978 5 18 6 17 TONY 16.8 23.7 59 621 +1952 1 3 6 16 GORDON 17.3 144.1 127 708 +1972 11 24 0 4 GORDON 67.6 78.2 51 438 +1985 9 23 18 10 FLORENCE 13.2 170.9 142 496 +1987 5 18 0 5 LESLIE 41.7 168.3 148 599 +1987 12 19 0 24 HELENE 48.6 259.1 132 208 +1958 4 24 6 3 SANDY 61.2 76.5 143 432 +1968 10 22 0 14 JOYCE 54.2 23.4 100 640 +1964 10 1 18 7 PATTY 37.4 102.9 71 261 +2004 1 2 0 12 GORDON 65.9 160.0 105 212 +1954 7 4 0 16 GORDON 59.9 83.1 160 469 +1975 4 21 12 20 ALBERTO 53.4 178.5 114 227 +2000 12 23 6 13 LESLIE 41.4 191.4 39 678 +1954 1 7 12 13 VALERIE 49.2 77.1 13 584 +1988 2 4 18 26 MICHAEL 40.6 12.0 30 805 +1957 8 17 0 24 SANDY 18.9 74.5 138 660 +1971 8 17 0 20 KIRK 55.0 257.5 92 825 +1993 12 6 12 12 JOYCE 58.0 301.9 11 357 +1999 3 4 18 24 DEBBY 44.5 42.6 108 569 +1992 9 8 12 9 RAFAEL 38.8 193.7 17 274 +1985 3 3 0 27 ALBERTO 63.6 109.9 115 264 +2004 10 8 12 26 TONY 66.7 292.8 25 270 +1959 3 16 18 16 CHRIS 34.0 335.9 128 51 +1963 5 10 18 1 CHRIS 34.8 301.6 116 808 +1958 6 2 18 1 NADINE 48.9 248.4 155 133 +2002 1 20 6 5 TONY 13.3 206.9 46 86 +1968 11 19 12 18 GORDON 22.9 182.6 26 810 +1997 3 23 12 4 NADINE 49.2 34.2 134 266 +1966 1 10 18 26 KIRK 13.6 140.0 58 492 +1977 7 7 18 23 FLORENCE 68.7 246.4 94 869 +1988 6 9 18 5 NADINE 59.8 151.1 137 541 +1960 12 7 12 9 ERNESTO 44.5 276.6 115 562 +1993 10 14 18 6 HELENE 16.7 75.1 36 623 +1963 1 26 18 5 FLORENCE 24.3 214.2 35 510 +2000 12 16 0 21 ISAAC 37.1 21.5 66 338 +1993 1 2 0 5 ISAAC 7.3 350.2 104 476 +1973 9 25 18 24 JOYCE 44.7 115.8 153 133 +1987 6 6 6 10 WILLIAM 9.8 223.5 59 777 +1989 8 7 12 25 NADINE 31.6 344.6 35 205 +1950 2 13 6 27 MICHAEL 62.0 259.4 149 382 +1981 1 13 6 19 WILLIAM 41.2 60.9 136 603 +1987 9 5 6 15 FLORENCE 32.9 163.7 138 440 +1991 6 8 0 10 FLORENCE 55.1 214.4 85 874 +1974 7 6 0 8 DEBBY 60.7 171.3 74 725 +1965 7 9 6 11 PATTY 7.5 223.5 75 662 +1982 8 12 18 18 CHRIS 22.0 346.3 57 743 +1999 4 22 6 20 LESLIE 11.0 141.5 49 649 +1965 5 15 18 13 OSCAR 30.8 116.3 154 720 +2000 2 16 18 5 CHRIS 24.8 207.7 102 398 +1952 10 1 6 25 BERYL 45.5 158.6 93 217 +1991 3 10 18 27 TONY 54.6 227.8 29 645 +1958 1 28 6 9 BERYL 46.6 2.9 74 264 +1991 2 11 0 23 LESLIE 64.1 247.5 19 511 +1986 2 6 0 28 ALBERTO 38.7 108.8 70 82 +1982 2 5 18 10 FLORENCE 56.7 311.6 21 611 +1984 10 23 6 28 OSCAR 25.0 329.9 91 217 +2004 8 15 12 1 DEBBY 22.5 302.3 160 307 +1978 4 9 6 1 MICHAEL 66.4 224.9 79 33 +1986 4 28 6 10 JOYCE 50.9 231.5 73 581 +1962 9 2 0 22 HELENE 8.6 64.6 144 628 +1978 5 18 12 12 CHRIS 62.9 289.1 34 765 +1985 12 27 12 13 RAFAEL 58.7 120.9 45 359 +1991 4 13 12 12 TONY 24.5 103.4 76 863 +2002 11 3 18 2 RAFAEL 9.9 181.4 120 163 +1989 1 3 18 22 HELENE 28.1 338.0 154 339 +1950 12 7 6 20 MICHAEL 56.4 331.0 51 668 +1994 12 11 6 19 GORDON 59.2 101.5 54 164 +2000 1 24 0 24 GORDON 19.0 125.9 55 483 +1964 8 19 0 11 JOYCE 29.2 43.2 76 703 +1973 12 24 6 7 HELENE 34.9 338.8 33 513 +2001 2 15 18 27 NADINE 24.4 43.3 46 721 +1952 10 27 18 9 KIRK 10.3 39.8 25 529 +1985 1 16 6 1 WILLIAM 13.0 136.3 54 224 +1956 7 6 0 4 FLORENCE 65.0 209.5 134 264 +1993 1 19 18 23 MICHAEL 59.0 64.7 24 587 +1993 3 28 12 27 FLORENCE 62.0 62.4 136 409 +2001 7 8 6 15 KIRK 28.0 49.6 49 84 +1998 2 3 0 21 FLORENCE 60.7 187.1 86 854 +1993 1 6 0 9 HELENE 22.2 235.3 21 629 +1992 12 24 18 4 ALBERTO 32.4 1.0 50 125 +1988 8 14 12 7 HELENE 12.8 330.2 84 508 +1968 10 26 18 3 RAFAEL 48.6 329.3 67 266 +1988 4 8 12 26 OSCAR 24.7 85.4 69 129 +1989 4 2 0 26 LESLIE 47.7 222.9 71 777 +1994 9 18 6 13 DEBBY 51.1 51.8 113 70 +1971 7 7 6 8 TONY 56.9 159.0 99 548 +1968 1 26 18 27 HELENE 57.8 248.7 81 336 +1961 11 6 0 2 RAFAEL 16.0 7.0 76 332 +1976 8 9 0 28 ALBERTO 11.9 350.9 51 683 +1984 11 20 12 25 ERNESTO 55.9 33.1 47 416 +1977 2 5 6 22 DEBBY 61.4 252.1 144 455 +1973 11 24 12 24 SANDY 36.4 120.7 22 708 +1957 4 4 6 16 LESLIE 47.4 197.5 91 204 +1994 6 26 18 27 ISAAC 24.9 4.0 136 732 +1972 4 11 18 28 SANDY 25.9 197.1 60 356 +1975 6 19 18 4 SANDY 61.6 251.2 115 149 +1999 9 18 6 19 WILLIAM 64.1 172.9 38 874 +1984 2 8 12 12 ALBERTO 20.8 323.3 113 374 +1950 4 21 12 5 VALERIE 66.9 206.1 146 93 +1977 7 28 18 27 ALBERTO 26.8 169.4 29 9 +1955 9 22 12 2 LESLIE 22.8 93.7 26 891 +1970 3 28 12 12 ALBERTO 64.8 175.0 75 885 +1983 8 1 0 1 OSCAR 15.7 161.4 44 828 +1955 7 14 12 25 BERYL 44.3 59.3 139 612 +1975 9 5 0 3 CHRIS 21.4 134.5 125 790 +1954 3 14 18 13 LESLIE 46.7 346.0 121 849 +1971 3 5 12 12 NADINE 61.4 330.7 10 641 +2004 7 11 18 25 ISAAC 35.4 165.4 11 685 +1958 9 8 6 2 OSCAR 38.6 42.7 61 81 +1977 3 14 18 26 MICHAEL 15.2 289.9 92 29 +1950 7 27 12 13 JOYCE 51.2 29.9 159 253 +1964 1 28 6 16 TONY 16.0 325.4 46 450 +1992 1 13 18 28 PATTY 18.4 173.8 117 35 +1979 3 25 6 18 RAFAEL 65.9 254.7 136 198 +1955 4 7 12 4 NADINE 51.5 271.6 151 218 +1967 5 27 12 4 MICHAEL 18.2 144.2 26 481 +1958 10 15 12 8 PATTY 49.1 101.4 86 70 +1957 7 20 0 20 SANDY 19.2 113.3 15 859 +2001 10 21 12 27 LESLIE 38.6 191.4 58 760 +1988 1 24 0 23 TONY 24.5 21.2 89 474 +1964 6 8 18 23 KIRK 68.9 294.1 74 810 +2003 10 13 18 16 FLORENCE 49.3 324.8 131 127 +1964 11 11 18 8 OSCAR 13.5 47.5 69 313 +1986 2 14 18 25 LESLIE 22.0 41.2 57 520 +1957 2 13 18 1 KIRK 43.0 328.5 113 673 +1985 1 17 12 6 SANDY 38.5 74.0 101 339 +1976 7 23 12 21 RAFAEL 33.4 267.0 164 286 +1978 6 11 0 23 OSCAR 29.1 236.1 147 43 +1977 5 1 18 18 SANDY 28.2 212.1 80 150 +1997 11 27 12 25 JOYCE 7.2 152.9 141 301 +1969 8 19 18 9 CHRIS 38.3 218.9 163 140 +1968 6 7 0 3 LESLIE 31.6 129.7 67 502 +1950 1 25 0 20 SANDY 11.5 284.6 130 831 +1953 6 12 6 24 JOYCE 60.7 159.1 93 57 +1966 10 9 0 27 JOYCE 43.6 307.8 61 792 +2002 11 12 0 7 ALBERTO 61.4 273.2 49 14 +1976 4 17 18 3 WILLIAM 12.5 350.5 98 23 +1959 8 16 12 22 MICHAEL 36.1 315.1 122 401 +1975 11 15 18 21 LESLIE 42.5 213.3 164 170 +1973 9 8 6 2 NADINE 28.9 195.6 153 648 +1971 9 16 18 19 JOYCE 23.1 314.8 11 476 +1954 3 1 18 25 OSCAR 51.1 40.6 62 754 +1997 12 2 18 24 GORDON 67.8 12.3 147 344 +1989 1 15 12 25 OSCAR 33.9 120.1 63 498 +1953 10 21 0 6 WILLIAM 40.0 304.2 95 406 +1983 6 11 0 2 BERYL 49.4 138.5 19 674 +1998 9 19 0 21 ERNESTO 25.4 66.3 14 832 +1960 2 3 0 9 LESLIE 22.8 189.7 31 598 +1999 7 2 0 2 VALERIE 67.0 245.7 162 491 +1971 4 15 0 11 JOYCE 9.0 67.5 21 340 +2004 12 19 12 13 ISAAC 64.9 304.9 26 488 +1970 1 1 18 17 MICHAEL 33.5 188.4 20 550 +1952 2 28 12 4 HELENE 69.9 277.1 11 43 +1990 5 22 12 22 PATTY 43.2 239.3 99 375 +1959 3 18 18 16 GORDON 15.9 334.9 150 127 +1975 2 13 0 2 WILLIAM 44.5 82.8 52 73 +1996 3 12 0 14 BERYL 27.5 74.8 99 261 +1965 5 19 18 2 LESLIE 64.0 233.5 135 705 +1974 2 11 18 27 KIRK 32.4 283.2 126 394 +1954 7 19 6 15 FLORENCE 52.3 103.3 132 610 +2001 4 21 12 15 VALERIE 38.0 320.3 27 100 +1956 5 28 6 25 GORDON 51.8 129.5 121 778 +1951 7 20 18 11 PATTY 51.4 311.6 18 405 +1963 3 23 12 8 OSCAR 38.7 302.8 149 74 +1952 8 2 12 13 BERYL 58.9 235.4 73 218 +1954 1 20 18 3 FLORENCE 26.4 102.7 48 239 +1968 11 12 12 28 KIRK 40.3 279.6 121 419 +1990 6 3 18 18 MICHAEL 40.4 62.4 121 110 +1985 5 20 12 27 GORDON 59.5 129.1 146 64 +2003 11 20 18 9 FLORENCE 53.8 235.6 45 631 +1993 10 1 6 23 JOYCE 30.1 349.5 98 872 +1963 10 15 12 11 PATTY 39.4 73.6 100 430 +2004 2 11 18 7 WILLIAM 21.8 172.5 116 422 +1963 12 27 6 22 HELENE 33.0 174.8 140 396 +1995 5 8 6 7 MICHAEL 53.3 154.0 27 312 +1955 3 4 0 18 SANDY 51.1 70.8 43 187 +1974 9 19 0 25 JOYCE 23.0 202.9 136 739 +1960 9 4 18 26 HELENE 26.5 92.7 26 495 +1954 4 22 18 13 GORDON 20.7 284.8 151 881 +1993 4 6 6 28 CHRIS 9.3 204.4 112 115 +1977 7 14 6 13 SANDY 68.2 78.3 91 634 +1982 4 25 12 5 HELENE 8.8 138.7 141 225 +1990 8 11 0 20 WILLIAM 53.8 300.4 158 644 +1979 2 7 6 20 KIRK 35.0 283.8 135 857 +2002 8 23 0 8 HELENE 9.4 102.3 26 291 +1955 7 10 6 20 BERYL 46.8 56.3 75 681 +1971 5 19 18 12 GORDON 36.8 321.1 99 696 +1970 8 15 0 19 NADINE 31.6 291.2 161 219 +1971 3 7 6 14 FLORENCE 32.9 304.4 123 258 +1951 1 4 0 8 OSCAR 15.9 232.9 65 78 +1967 1 27 18 26 HELENE 36.3 134.5 149 422 +1955 8 6 6 13 ERNESTO 62.5 176.7 56 380 +1987 8 17 0 19 HELENE 44.8 46.9 97 89 +1963 1 6 18 6 BERYL 52.1 226.7 106 612 +1991 10 24 0 1 MICHAEL 64.8 162.8 123 336 +1977 3 24 6 4 ALBERTO 32.5 81.3 118 374 +1994 4 19 6 15 JOYCE 61.6 235.1 158 705 +1976 10 22 12 22 RAFAEL 52.5 81.2 36 626 +1982 2 13 0 22 LESLIE 49.4 45.5 129 339 +1986 6 21 12 28 FLORENCE 59.2 281.8 145 245 +1982 4 20 0 14 VALERIE 18.1 163.9 128 632 +1975 7 3 12 4 VALERIE 26.7 151.3 113 106 +1968 2 2 18 10 HELENE 67.4 298.8 52 175 +2002 2 27 6 14 HELENE 22.8 344.2 22 67 +1981 7 12 6 5 HELENE 9.9 286.4 53 551 +1972 9 10 12 21 ISAAC 46.6 199.5 101 810 +1979 5 13 6 13 ISAAC 21.6 160.5 120 272 +1960 4 10 12 26 SANDY 47.5 53.2 125 589 +1954 1 16 18 8 CHRIS 37.6 243.4 102 305 +1954 8 24 18 19 FLORENCE 66.2 183.0 85 795 +1976 12 9 18 14 CHRIS 32.4 349.5 131 635 +1979 12 5 12 6 ALBERTO 58.6 91.8 99 624 +1967 3 20 6 28 RAFAEL 47.6 117.3 106 85 +1996 1 1 0 4 MICHAEL 25.8 6.2 29 439 +2000 4 20 18 15 ISAAC 58.6 103.3 122 708 +1992 3 5 12 4 MICHAEL 36.1 36.6 51 443 +1968 8 1 6 19 DEBBY 38.6 244.5 31 260 +1961 6 6 18 16 MICHAEL 13.2 290.8 163 361 +1956 8 22 0 15 DEBBY 30.6 72.7 125 662 +1968 3 15 0 7 KIRK 23.8 210.1 45 205 +2001 5 16 0 21 BERYL 55.8 23.0 54 461 +1971 8 7 6 20 ALBERTO 20.0 16.3 131 129 +1953 4 11 0 22 MICHAEL 14.5 146.7 145 514 +1989 2 11 18 9 KIRK 10.2 196.8 48 893 +2001 6 23 0 11 SANDY 11.2 309.3 46 809 +1968 7 21 0 24 KIRK 37.6 249.6 93 69 +1983 3 6 12 5 VALERIE 25.4 338.8 133 114 +1971 9 16 6 17 RAFAEL 12.6 345.4 126 552 +1989 6 9 0 20 LESLIE 57.7 115.2 42 245 +1971 9 25 6 6 TONY 40.3 241.6 125 39 +1990 8 14 0 23 BERYL 15.5 323.2 46 80 +1956 11 16 0 10 ERNESTO 47.9 222.7 160 894 +1967 5 14 0 12 RAFAEL 67.8 166.6 128 272 +1993 7 7 12 27 CHRIS 67.3 5.0 29 547 +1965 8 10 18 17 JOYCE 36.7 143.9 82 444 +1959 5 19 18 22 RAFAEL 11.5 295.7 97 576 +1957 1 6 18 15 KIRK 67.2 137.0 13 158 +1977 7 4 18 18 LESLIE 29.2 331.2 81 826 +2003 3 18 12 17 KIRK 45.8 6.5 149 276 +1963 1 3 6 17 OSCAR 25.2 223.7 14 379 +1991 5 19 0 2 MICHAEL 22.0 325.9 110 519 +2002 4 26 0 4 WILLIAM 21.5 101.1 29 711 +1991 8 13 18 11 HELENE 27.5 17.5 56 830 +1997 10 6 18 2 MICHAEL 49.5 7.5 141 445 +1972 4 8 12 19 FLORENCE 26.5 6.6 120 736 +1993 5 6 0 17 SANDY 16.1 120.4 40 201 +1997 4 9 18 17 TONY 53.9 227.2 157 161 +1975 12 17 0 26 SANDY 66.2 269.3 161 536 +1951 12 18 12 15 OSCAR 22.6 143.4 113 57 +1958 4 9 12 7 VALERIE 55.6 66.2 130 419 +1952 7 9 12 5 VALERIE 56.0 319.0 18 402 +1953 12 23 12 12 NADINE 34.8 152.3 140 370 +1975 5 8 0 9 DEBBY 28.7 321.3 82 439 +1969 1 17 18 21 JOYCE 28.8 201.9 87 434 +1952 7 17 0 14 WILLIAM 66.4 220.4 137 62 +1997 12 27 12 3 ERNESTO 25.2 116.0 117 848 +1981 4 14 6 12 KIRK 59.0 336.8 74 216 +1957 8 4 18 22 LESLIE 18.9 210.2 163 580 +1956 6 28 0 12 ISAAC 36.5 310.9 83 331 +1976 2 16 6 5 GORDON 33.5 278.1 40 551 +1997 11 5 6 10 GORDON 59.6 25.5 135 156 +1960 2 26 12 20 RAFAEL 47.1 4.8 63 852 +1990 1 7 12 17 BERYL 28.5 136.6 71 770 +1956 12 12 18 17 ERNESTO 28.3 89.7 22 325 +1974 8 16 18 21 GORDON 40.5 272.7 22 418 +1961 4 19 0 26 NADINE 14.4 67.5 39 52 +1990 10 11 18 2 ALBERTO 35.9 170.6 164 102 +1978 12 23 18 5 OSCAR 66.6 278.4 84 589 +2003 4 26 18 14 ISAAC 41.4 193.8 93 54 +1973 2 24 0 25 KIRK 10.0 193.5 50 866 +1982 3 3 6 11 VALERIE 15.2 344.0 144 680 +1968 2 3 0 28 OSCAR 40.3 145.8 67 478 +1957 12 4 12 5 TONY 67.5 38.2 113 756 +1993 7 11 6 23 BERYL 44.9 24.7 164 415 +1960 6 5 6 12 NADINE 39.6 335.2 95 899 +1954 10 14 0 21 SANDY 29.7 258.1 152 568 +1962 9 6 12 20 BERYL 12.3 300.0 14 31 +1959 12 16 12 26 FLORENCE 24.8 240.7 135 342 +1999 6 21 0 28 LESLIE 55.3 229.9 14 602 +1995 3 10 12 21 ERNESTO 30.0 332.3 80 94 +1982 11 3 18 25 TONY 67.2 51.6 102 883 +1995 1 13 18 15 GORDON 27.8 210.3 91 314 +1988 12 14 6 12 FLORENCE 19.0 65.6 101 172 +1989 9 16 18 6 VALERIE 20.8 324.9 38 336 +1983 7 25 6 14 KIRK 22.7 69.0 132 724 +1977 6 21 12 3 ALBERTO 60.9 138.1 25 630 +2003 4 24 12 14 HELENE 56.9 86.5 66 91 +1997 11 21 0 12 ERNESTO 48.9 294.7 75 131 +1994 6 6 6 19 ISAAC 10.5 59.1 153 558 +1950 3 24 6 14 HELENE 58.3 275.0 129 126 +1958 3 28 0 12 GORDON 38.9 338.5 124 99 +1982 6 26 18 1 ISAAC 8.2 343.1 45 196 +1993 9 14 0 17 RAFAEL 11.2 13.9 81 632 +1970 8 25 6 20 RAFAEL 68.0 186.0 35 598 +1984 10 6 12 15 GORDON 38.0 19.8 40 890 +1977 11 27 0 17 DEBBY 14.9 203.5 42 356 +1997 4 18 0 22 OSCAR 33.9 182.5 48 752 +2004 1 13 18 1 BERYL 41.2 350.7 116 859 +1987 8 25 12 4 LESLIE 27.0 119.5 40 624 +1972 12 16 12 8 NADINE 10.0 261.4 11 285 +1966 5 17 6 20 JOYCE 67.8 352.8 59 641 +1967 9 26 18 8 LESLIE 37.8 251.6 138 576 +1983 2 5 6 17 JOYCE 61.6 270.7 138 688 +1983 2 9 18 23 DEBBY 10.0 109.9 137 619 +1977 6 27 0 5 ALBERTO 67.0 133.8 101 305 +1990 8 25 6 26 NADINE 45.2 36.1 24 228 +1993 2 15 0 8 RAFAEL 47.2 54.6 98 450 +1955 4 24 0 5 VALERIE 63.8 254.2 109 629 +2003 9 21 6 11 NADINE 43.0 336.0 65 210 +1970 12 9 12 22 PATTY 52.3 270.0 26 579 +1986 6 10 0 24 GORDON 66.6 114.7 19 179 +1957 1 23 12 13 BERYL 24.5 4.5 47 67 +1952 7 16 18 23 BERYL 38.4 115.6 37 36 +1953 8 24 0 2 NADINE 36.2 153.0 72 543 +1987 3 12 12 11 KIRK 54.9 311.4 151 425 +1968 1 8 6 24 TONY 47.7 107.1 71 34 +1967 11 23 12 8 LESLIE 37.9 203.0 149 612 +1990 4 20 6 1 HELENE 7.3 88.5 112 104 +1984 5 4 0 18 RAFAEL 69.4 100.3 62 519 +1956 5 4 12 10 ISAAC 17.3 161.6 104 63 +1993 7 9 18 21 ISAAC 18.8 86.5 28 175 +1957 11 20 0 28 ALBERTO 16.5 105.4 160 408 +1960 10 15 12 4 RAFAEL 68.6 250.2 72 488 +1959 4 28 12 26 OSCAR 60.8 204.2 30 597 +1964 6 17 12 12 FLORENCE 38.0 37.1 121 446 +1978 8 17 12 10 LESLIE 37.0 334.1 74 273 +1970 1 8 18 17 ALBERTO 22.7 329.5 44 709 +1950 8 28 18 9 WILLIAM 39.6 181.2 78 360 +1974 12 10 12 10 RAFAEL 66.7 160.4 127 785 +1960 12 25 0 5 CHRIS 42.2 77.6 154 325 +1974 9 21 6 18 DEBBY 53.9 246.6 139 118 +1983 6 10 0 4 VALERIE 28.4 174.9 58 2 +1987 5 11 6 14 WILLIAM 50.1 62.1 100 690 +2004 10 18 0 5 ERNESTO 48.2 318.8 155 83 +2003 6 19 6 19 HELENE 50.7 313.6 71 435 +1958 2 11 12 21 VALERIE 50.0 237.4 64 860 +1950 2 25 6 13 WILLIAM 48.4 207.2 21 859 +1962 8 6 6 10 WILLIAM 32.0 344.7 67 750 +1995 11 26 18 9 ALBERTO 8.2 88.0 95 763 +1965 7 19 0 14 NADINE 36.0 53.2 75 42 +1999 10 22 0 4 JOYCE 61.0 31.3 143 713 +1950 11 15 18 27 MICHAEL 31.9 124.1 14 43 +1966 3 13 18 16 WILLIAM 22.2 199.4 157 430 +1996 12 3 18 28 SANDY 43.7 225.2 118 761 +1985 9 28 6 1 VALERIE 23.3 229.6 116 26 +1954 9 25 6 20 ALBERTO 66.8 339.2 25 100 +1981 7 24 12 9 HELENE 37.6 34.6 132 771 +1992 1 2 12 2 BERYL 56.7 337.8 24 619 +1988 4 22 18 2 MICHAEL 50.8 126.3 95 749 +1950 6 17 18 28 RAFAEL 30.3 158.4 151 317 +1994 11 17 18 4 FLORENCE 67.4 172.0 51 389 +1953 6 17 12 25 RAFAEL 69.2 147.7 57 818 +2002 4 18 18 12 WILLIAM 42.7 193.2 63 209 +1981 8 12 12 7 KIRK 58.7 173.6 49 349 +1969 10 19 0 5 TONY 15.8 92.7 151 829 +2001 8 12 6 22 MICHAEL 21.5 92.0 137 35 +1989 1 20 18 16 LESLIE 25.8 308.9 139 330 +1992 9 22 0 10 NADINE 24.1 315.5 86 616 +1994 8 28 12 17 BERYL 25.2 312.4 22 211 +1986 6 9 18 17 FLORENCE 41.3 256.6 144 867 +1986 8 21 0 13 WILLIAM 49.7 18.0 76 581 +1990 5 12 18 17 RAFAEL 41.3 138.4 101 690 +1998 2 18 0 24 ERNESTO 36.7 45.1 131 351 +1956 3 5 12 18 BERYL 48.6 98.8 114 121 +1968 4 11 6 12 MICHAEL 22.6 88.3 94 216 +1975 5 18 18 12 ISAAC 37.8 230.1 47 774 +1960 7 12 18 2 FLORENCE 60.6 347.5 61 106 +1959 7 23 12 8 GORDON 29.3 249.9 13 658 +1993 10 28 12 17 SANDY 46.9 3.9 104 804 +1978 12 6 12 27 LESLIE 19.4 273.1 126 660 +1972 2 12 0 18 WILLIAM 17.4 264.2 25 236 +1975 3 17 18 10 JOYCE 38.8 64.3 39 573 +1985 11 6 0 18 ISAAC 36.1 52.3 38 151 +1965 3 11 12 13 BERYL 60.3 211.5 37 347 +1959 3 4 0 3 TONY 45.3 190.6 94 485 +1952 12 25 6 24 DEBBY 31.6 101.5 89 305 +2003 8 25 18 7 FLORENCE 13.8 149.4 129 835 +1968 11 6 0 10 TONY 39.6 13.6 139 142 +1966 11 20 12 2 DEBBY 46.8 184.4 90 728 +1990 6 1 18 24 WILLIAM 11.6 65.6 10 140 +1967 6 1 18 16 OSCAR 50.8 187.8 61 502 +1972 2 6 18 2 WILLIAM 26.4 336.4 139 863 +1968 3 11 0 15 MICHAEL 32.5 51.1 64 407 +1981 9 20 0 10 ERNESTO 29.9 73.2 162 140 +1954 5 25 18 13 WILLIAM 54.8 245.8 14 371 +1961 6 15 12 14 DEBBY 30.6 113.2 100 678 +1977 7 16 12 18 NADINE 31.2 129.0 149 856 +1958 10 10 18 27 LESLIE 28.2 39.4 23 216 +1992 10 2 18 3 GORDON 33.1 156.7 147 857 +1986 8 6 0 7 KIRK 41.6 182.0 21 812 +1998 2 11 12 15 LESLIE 29.3 357.3 104 382 +1965 1 24 6 2 ISAAC 58.7 62.0 142 364 +1999 3 13 18 13 ISAAC 43.5 88.0 149 407 +1993 2 17 18 14 HELENE 46.1 94.8 125 721 +1954 8 27 12 20 JOYCE 13.2 15.1 157 143 +1980 12 11 0 1 KIRK 27.4 69.8 80 590 +1970 5 6 18 17 KIRK 9.0 328.1 67 851 +2004 3 13 12 14 BERYL 61.2 46.6 38 187 +2004 5 16 6 4 HELENE 31.5 100.8 160 582 +1956 2 20 12 17 DEBBY 21.0 242.5 18 177 +1976 7 23 18 2 MICHAEL 43.7 244.2 151 702 +1970 8 1 6 17 LESLIE 9.3 85.0 147 763 +1975 2 7 6 16 FLORENCE 28.6 207.2 70 79 +2000 7 5 6 12 NADINE 46.9 348.9 62 382 +1997 1 17 6 28 BERYL 46.6 8.9 51 169 +1981 5 10 0 21 ERNESTO 67.0 188.6 12 30 +1959 5 22 12 9 NADINE 58.3 242.2 161 409 +1961 10 19 18 17 SANDY 15.7 155.7 140 756 +1956 12 4 0 20 ERNESTO 35.2 23.9 112 545 +1976 2 1 18 19 LESLIE 47.5 29.6 77 85 +2000 5 14 6 26 HELENE 27.6 238.6 30 216 +1958 11 4 12 23 CHRIS 35.6 127.6 110 812 +1967 3 5 6 6 KIRK 8.4 301.9 118 889 +1981 11 13 6 16 FLORENCE 30.0 309.1 89 869 +1997 4 1 6 12 GORDON 29.4 332.3 43 733 +2003 11 21 0 15 ALBERTO 20.1 109.0 61 378 +1996 9 15 6 21 ERNESTO 66.0 318.8 86 575 +1966 12 19 6 6 GORDON 69.2 127.7 151 99 +1986 5 22 18 11 CHRIS 59.4 7.4 141 218 +1956 1 15 6 12 FLORENCE 69.7 114.4 95 73 +1964 8 28 18 7 WILLIAM 50.1 315.6 51 419 +1965 11 9 12 22 ALBERTO 59.6 116.4 124 141 +1997 10 10 18 1 LESLIE 43.1 174.8 80 474 +1993 8 9 12 12 WILLIAM 54.9 95.6 159 769 +2002 10 20 12 9 DEBBY 51.5 88.8 145 461 +1988 3 8 12 6 LESLIE 54.2 90.5 69 327 +1979 6 12 12 7 HELENE 48.0 8.3 94 202 +1957 4 10 18 13 PATTY 9.7 231.6 43 574 +1987 2 24 6 4 KIRK 21.5 354.3 40 270 +1976 5 21 12 28 LESLIE 53.6 54.2 77 624 +1956 5 7 6 17 PATTY 18.5 300.1 122 687 +1967 7 14 6 26 JOYCE 43.0 27.2 117 636 +1973 8 7 6 1 DEBBY 60.7 59.5 92 363 +2004 5 12 6 4 NADINE 15.3 119.3 100 32 +1992 7 3 0 3 SANDY 7.9 291.4 18 549 +1962 6 15 0 1 SANDY 27.6 298.0 108 795 +1972 1 12 18 26 OSCAR 17.8 301.1 117 362 +1989 11 2 0 18 WILLIAM 38.9 55.1 38 552 +1963 11 27 18 26 TONY 34.6 261.5 112 107 +1966 5 12 12 22 VALERIE 28.8 288.6 56 243 +1992 3 3 18 2 FLORENCE 50.6 271.3 152 861 +1986 2 23 0 12 OSCAR 51.0 219.7 49 280 +1987 10 26 12 24 HELENE 39.9 255.5 31 717 +1996 3 26 0 8 DEBBY 39.5 124.3 52 529 +1991 7 16 6 6 ISAAC 42.7 217.1 149 240 +1976 9 8 0 17 BERYL 17.4 185.3 132 899 +1994 2 6 12 26 FLORENCE 9.4 37.5 87 236 +2002 12 26 0 3 GORDON 62.3 263.7 68 749 +1997 12 14 0 27 ISAAC 8.8 93.0 11 80 +1957 12 5 0 15 WILLIAM 20.8 180.6 108 454 +1969 6 25 18 5 JOYCE 23.5 6.6 57 136 +1972 12 19 18 5 PATTY 34.8 140.4 48 738 +1983 6 20 6 4 LESLIE 8.7 285.5 24 609 +1958 11 15 6 5 SANDY 33.7 120.4 32 854 +1959 4 20 6 20 FLORENCE 43.8 73.1 61 101 +1982 9 12 6 17 FLORENCE 63.6 138.6 147 858 +1993 10 3 6 5 SANDY 23.1 49.5 148 265 +1989 4 6 0 7 RAFAEL 12.4 277.1 142 407 +1973 8 7 18 13 RAFAEL 15.5 174.0 43 799 +1978 1 9 18 28 RAFAEL 28.0 158.7 49 533 +1951 11 28 0 3 PATTY 42.9 68.2 28 70 +1967 8 15 12 12 FLORENCE 69.5 31.0 30 630 +1952 6 9 18 28 KIRK 24.0 276.8 74 390 +1966 2 2 12 16 CHRIS 9.1 305.9 160 126 +1980 10 21 6 8 ISAAC 46.4 220.6 146 810 +1980 1 7 6 13 KIRK 55.9 24.3 39 823 +1997 3 27 18 9 VALERIE 68.3 184.0 46 807 +1985 7 24 6 23 JOYCE 19.5 2.5 104 262 +1957 12 11 12 21 BERYL 32.8 261.8 40 658 +1961 7 17 12 1 LESLIE 49.3 157.5 106 519 +1977 9 19 6 15 FLORENCE 67.9 156.7 55 754 +1976 4 12 12 20 SANDY 42.0 202.1 119 243 +1952 9 7 6 25 VALERIE 23.3 10.3 21 282 +1998 8 23 18 21 WILLIAM 9.0 148.0 76 275 +1982 9 21 0 22 ALBERTO 56.3 123.2 51 587 +1970 7 22 6 22 GORDON 43.5 304.6 82 508 +1984 5 3 12 2 ISAAC 25.5 260.6 126 647 +1959 7 9 18 12 VALERIE 63.6 117.6 50 316 +1975 2 8 6 28 CHRIS 23.2 154.0 160 786 +1996 2 6 0 24 OSCAR 42.3 222.9 146 38 +1956 6 7 0 2 MICHAEL 61.0 61.5 120 420 +1992 10 26 12 1 ERNESTO 10.9 179.4 58 474 +1989 6 2 6 26 ISAAC 7.7 120.6 120 167 +1998 8 19 12 8 GORDON 54.5 112.1 86 579 +2000 12 6 0 22 JOYCE 57.7 322.8 96 585 +1965 8 4 12 26 VALERIE 49.0 71.1 134 445 +1984 12 26 0 20 WILLIAM 21.9 253.1 22 744 +2002 1 8 18 9 MICHAEL 53.7 110.0 75 560 +1998 10 12 0 14 FLORENCE 59.4 357.9 95 239 +1965 10 25 6 22 GORDON 43.4 269.6 22 297 +2002 6 11 0 10 VALERIE 35.0 232.5 52 407 +2003 2 10 18 4 ALBERTO 13.4 211.4 79 71 +1973 10 12 6 3 BERYL 60.3 314.7 147 242 +1960 9 27 0 1 OSCAR 29.6 67.8 98 222 +1994 3 1 12 10 PATTY 54.7 193.2 27 611 +1973 2 23 0 3 PATTY 50.9 146.0 123 362 +1954 12 12 6 13 BERYL 30.5 251.1 93 522 +1996 4 8 6 13 WILLIAM 50.1 263.9 129 814 +1953 4 3 12 12 VALERIE 49.2 124.8 30 310 +1986 8 12 0 9 FLORENCE 51.3 73.8 160 81 +1995 3 26 18 2 RAFAEL 42.5 144.5 155 896 +1973 8 11 6 28 BERYL 57.5 227.3 71 113 +1979 9 2 6 7 JOYCE 13.1 200.1 18 731 +1997 8 13 6 24 PATTY 32.0 220.7 105 45 +1950 8 8 12 3 HELENE 51.6 306.5 59 806 +1988 12 9 12 23 JOYCE 56.7 299.2 134 380 +1958 7 3 12 27 OSCAR 37.2 73.2 61 415 +2000 5 3 0 9 KIRK 60.4 176.5 68 40 +1983 4 21 12 5 BERYL 42.7 79.4 164 525 +1964 4 9 12 3 WILLIAM 43.7 73.9 16 738 +1967 1 19 6 16 WILLIAM 10.4 278.8 101 881 +1956 9 22 12 1 JOYCE 10.0 7.4 99 889 +1990 3 8 18 7 TONY 8.5 192.4 130 747 +2002 10 4 6 4 MICHAEL 65.9 179.3 18 289 +2004 10 24 0 10 NADINE 24.7 329.1 33 87 +1950 9 6 6 9 ISAAC 47.5 180.7 56 658 +1954 6 21 18 18 VALERIE 61.1 8.5 132 260 +1979 12 16 0 13 LESLIE 23.6 247.5 85 219 +1961 4 26 0 9 WILLIAM 34.2 289.2 28 15 +1955 3 26 18 23 LESLIE 33.9 232.7 61 890 +1974 10 4 0 7 OSCAR 8.0 229.6 127 469 +1976 12 24 12 19 GORDON 7.1 61.3 149 186 +1964 9 8 18 28 OSCAR 69.1 252.9 117 744 +1980 12 21 6 9 BERYL 36.7 201.2 135 281 +1964 4 25 12 2 LESLIE 29.7 62.5 156 193 +1958 1 26 18 6 CHRIS 18.1 18.9 145 476 +2004 9 10 18 11 ISAAC 28.8 57.3 42 664 +1981 9 12 0 13 KIRK 55.2 228.0 25 690 +1991 4 4 18 23 SANDY 57.9 86.2 130 536 +1970 6 19 18 7 NADINE 20.0 10.7 132 187 +1969 10 21 6 12 KIRK 50.6 140.1 24 571 +1978 10 6 12 23 JOYCE 44.3 53.6 132 225 +1969 3 2 6 14 MICHAEL 18.2 52.6 135 205 +2000 3 4 12 10 SANDY 23.7 308.4 132 185 +1990 4 1 0 21 NADINE 59.5 243.6 41 634 +1996 10 9 18 11 VALERIE 15.4 50.7 97 217 +1995 5 28 18 7 BERYL 56.2 150.1 156 410 +1992 9 22 0 12 ISAAC 21.1 32.5 115 180 +1985 4 5 6 28 KIRK 47.8 249.4 53 429 +1959 5 21 18 10 JOYCE 32.1 84.3 10 735 +1996 3 20 12 22 HELENE 49.0 288.8 39 73 +1956 7 15 6 5 DEBBY 42.3 40.7 84 71 +1978 10 24 12 12 RAFAEL 63.6 314.2 21 639 +1972 12 10 12 19 ISAAC 27.0 121.1 109 735 +1979 5 6 12 28 MICHAEL 67.7 267.8 117 66 +1972 7 14 12 4 JOYCE 35.8 84.0 144 404 +1978 2 14 12 15 LESLIE 45.1 250.3 147 697 +1988 2 8 18 3 ALBERTO 55.0 301.8 151 652 +1950 4 13 18 18 VALERIE 57.6 14.6 159 121 +1953 5 28 12 11 GORDON 58.0 242.0 88 575 +1959 8 11 12 7 VALERIE 69.7 148.2 153 332 +1983 4 5 18 21 KIRK 37.3 185.7 73 109 +1957 10 9 12 16 SANDY 27.3 264.3 109 638 +1958 7 23 6 10 GORDON 64.5 40.4 104 332 +1973 10 4 0 9 LESLIE 56.7 320.5 150 249 +2003 7 3 18 18 LESLIE 10.0 60.4 28 766 +1972 8 5 6 26 LESLIE 54.2 258.3 97 746 +1993 5 5 18 6 VALERIE 30.6 150.9 157 444 +1968 7 13 12 3 GORDON 14.5 82.4 152 111 +1981 10 15 18 18 KIRK 45.2 38.6 95 694 +1961 12 27 0 28 LESLIE 64.1 196.1 21 694 +1953 7 6 6 19 WILLIAM 48.2 326.8 58 60 +1992 8 20 18 5 NADINE 45.8 207.0 51 760 +2002 11 1 18 15 PATTY 34.9 333.6 102 812 +1978 8 8 18 18 ALBERTO 53.7 335.4 28 330 +2003 2 21 0 6 BERYL 42.6 22.9 51 550 +1995 5 13 6 28 TONY 36.4 349.8 129 611 +1977 7 24 0 25 TONY 52.0 271.7 33 374 +1951 1 3 0 6 ERNESTO 21.3 110.5 104 845 +1970 9 22 18 26 WILLIAM 14.5 310.0 33 886 +2003 8 15 12 3 GORDON 27.0 236.2 117 400 +1995 7 18 12 18 LESLIE 29.2 171.8 106 554 +1983 8 24 0 14 OSCAR 29.2 312.0 22 329 +1952 5 1 6 4 FLORENCE 63.0 175.7 96 842 +1965 11 17 0 9 BERYL 31.6 21.2 25 698 +1991 2 13 6 19 TONY 20.6 240.0 147 372 +1965 5 9 18 8 JOYCE 27.7 77.3 86 365 +1952 3 24 6 25 HELENE 29.4 343.2 160 622 +1991 8 12 6 19 LESLIE 41.6 303.6 129 330 +1993 9 26 18 22 JOYCE 55.6 75.3 121 784 +1997 10 19 6 14 VALERIE 19.5 253.5 48 423 +1965 10 12 0 17 BERYL 18.4 276.4 88 356 +1968 10 6 6 10 ALBERTO 37.4 108.5 143 538 +1990 1 9 18 16 DEBBY 42.3 173.1 26 553 +1968 1 3 18 9 VALERIE 36.3 322.4 106 765 +1988 1 17 0 8 ISAAC 22.3 132.7 131 395 +1977 9 9 12 11 CHRIS 50.2 56.0 162 581 +1963 11 24 6 20 BERYL 37.8 238.3 97 14 +1991 9 28 18 11 RAFAEL 21.8 106.6 141 15 +1995 7 11 0 13 CHRIS 24.7 210.3 34 535 +1981 5 14 12 15 HELENE 52.9 144.8 93 115 +1981 7 16 6 13 OSCAR 37.0 357.9 42 103 +1950 7 17 0 9 MICHAEL 28.5 329.0 62 480 +1976 8 18 6 12 GORDON 47.6 348.1 156 347 +2004 9 24 0 20 MICHAEL 17.7 198.4 83 118 +1976 3 11 6 7 OSCAR 23.0 33.4 78 170 +1979 1 15 6 28 GORDON 15.5 61.9 115 406 +1996 12 2 6 4 BERYL 47.7 142.3 24 712 +1973 1 24 6 11 BERYL 19.2 33.7 130 590 +2002 12 19 18 20 TONY 24.0 90.7 104 151 +1993 11 6 0 16 CHRIS 18.7 177.4 34 682 +1981 2 16 18 19 FLORENCE 17.3 292.3 52 777 +1996 7 28 6 21 DEBBY 46.1 138.4 24 675 +1976 12 24 6 8 DEBBY 35.2 216.5 27 192 +1964 4 20 18 19 KIRK 55.6 19.4 137 59 +1969 3 23 6 5 SANDY 66.6 249.2 90 274 +1967 2 18 12 1 KIRK 69.2 179.5 86 100 +1991 1 8 6 4 OSCAR 61.4 8.2 47 762 +1997 6 17 18 25 OSCAR 28.7 97.0 125 380 +2002 7 22 12 25 WILLIAM 24.6 241.2 56 856 +1993 2 13 6 21 LESLIE 42.4 158.7 164 390 +1960 9 16 12 12 RAFAEL 58.4 175.1 148 130 +1959 10 22 6 12 ERNESTO 44.1 133.2 41 675 +1983 11 28 0 2 BERYL 23.4 237.5 139 614 +1992 4 23 12 15 BERYL 46.0 231.6 79 592 +1985 9 27 12 2 KIRK 10.2 286.7 142 192 +1994 3 16 12 21 HELENE 54.8 30.5 13 895 +1991 1 6 0 10 RAFAEL 13.5 293.8 140 627 +1996 9 23 12 2 MICHAEL 63.5 114.9 11 184 +1995 8 10 18 3 BERYL 27.2 269.0 123 842 +1989 11 15 12 14 TONY 23.0 277.4 36 342 +1987 2 19 6 7 VALERIE 25.4 93.2 96 559 +1958 11 13 18 2 HELENE 56.2 86.9 156 161 +1995 6 3 12 5 TONY 27.4 49.0 134 501 +1980 6 11 6 28 SANDY 9.1 220.5 59 113 +1977 12 4 6 4 PATTY 31.7 194.0 154 361 +1995 7 24 6 2 WILLIAM 20.9 271.7 85 155 +1952 11 6 12 15 TONY 62.4 65.5 115 762 +1959 5 4 18 2 MICHAEL 64.3 78.8 78 489 +1986 5 11 6 14 PATTY 32.6 8.2 156 344 +1963 11 28 0 14 PATTY 41.5 216.0 96 486 +1975 9 23 18 25 JOYCE 66.7 133.0 48 566 +1956 5 22 0 11 VALERIE 14.9 25.6 65 887 +1987 4 4 6 2 BERYL 41.7 274.1 152 604 +1963 9 7 18 4 PATTY 51.4 225.2 15 423 +1976 11 28 18 19 BERYL 59.2 110.6 134 691 +1987 8 4 6 5 VALERIE 37.1 262.3 162 207 +1951 11 21 12 14 HELENE 65.8 67.8 101 31 +1987 2 3 12 12 JOYCE 15.5 97.5 60 354 +1951 12 1 0 12 ERNESTO 57.9 86.2 69 97 +1969 1 5 18 18 CHRIS 11.7 334.3 46 219 +1963 5 24 6 18 CHRIS 44.9 185.5 95 660 +1983 5 13 12 24 HELENE 13.4 133.6 87 836 +1953 8 23 18 17 CHRIS 65.3 246.9 138 315 +1987 4 25 0 28 GORDON 57.6 265.7 119 448 +1987 11 11 6 19 ERNESTO 61.9 119.4 132 221 +1975 3 26 18 24 OSCAR 34.2 235.0 77 344 +1980 3 17 0 19 JOYCE 34.8 223.2 129 379 +1992 5 13 18 1 PATTY 42.4 316.6 93 749 +1950 9 13 0 27 ERNESTO 29.9 37.1 86 439 +1981 4 13 0 15 WILLIAM 48.8 227.8 130 364 +1975 4 7 6 2 RAFAEL 42.2 165.0 75 18 +2003 9 1 12 21 SANDY 36.0 140.3 15 388 +1970 1 17 6 28 JOYCE 39.7 251.7 138 184 +1954 8 5 12 3 TONY 69.8 46.5 96 220 +1969 9 25 0 24 DEBBY 11.5 177.1 154 84 +1987 3 20 0 14 MICHAEL 64.7 49.5 18 438 +1951 3 3 0 19 RAFAEL 66.7 7.5 32 752 +1972 3 25 18 20 MICHAEL 37.3 186.9 122 410 +1963 9 3 12 5 PATTY 65.7 26.9 123 564 +1961 10 17 0 15 GORDON 61.5 245.0 145 139 +1958 7 8 18 18 ISAAC 51.8 280.5 120 5 +1988 4 22 6 23 TONY 61.4 165.5 157 597 +2002 2 2 12 22 DEBBY 21.8 150.8 118 580 +1966 9 1 6 28 VALERIE 47.8 333.4 37 661 +1990 5 3 6 22 DEBBY 59.6 232.6 97 765 +2003 1 6 6 26 JOYCE 26.5 42.4 16 491 +1987 3 6 0 27 OSCAR 38.4 344.8 91 94 +1950 8 19 12 15 ERNESTO 46.5 10.7 107 831 +1966 9 11 12 3 LESLIE 57.3 282.2 160 607 +2001 11 28 0 18 JOYCE 46.8 346.3 157 283 +2003 3 17 0 17 RAFAEL 27.9 122.2 156 766 +1963 3 15 0 3 JOYCE 28.9 323.0 27 870 +1972 10 19 0 7 ALBERTO 42.7 19.1 114 687 +1987 2 10 18 28 PATTY 46.6 18.0 131 390 +1967 12 13 0 11 ALBERTO 64.7 318.4 18 358 +1974 11 15 12 19 HELENE 22.0 36.4 60 211 +1998 12 3 6 20 OSCAR 69.2 141.3 128 879 +1968 7 6 18 25 ALBERTO 19.3 151.9 21 571 +1985 7 26 0 22 FLORENCE 24.8 311.4 117 328 +1997 8 8 6 5 BERYL 20.7 209.5 108 337 +2004 9 21 12 17 TONY 28.2 274.5 133 83 +1951 12 18 6 22 NADINE 16.7 188.7 155 464 +1952 7 13 12 20 FLORENCE 30.0 167.5 57 260 +1983 12 1 12 15 MICHAEL 60.1 175.8 86 213 +2000 11 7 6 4 TONY 54.6 91.1 148 27 +1983 6 16 0 6 ALBERTO 57.6 214.1 59 302 +1980 10 14 18 14 ALBERTO 31.9 211.9 88 222 +1992 9 15 18 26 DEBBY 51.3 270.9 57 603 +1962 11 1 18 7 BERYL 27.4 13.4 92 866 +1958 7 8 12 26 VALERIE 17.8 126.7 86 151 +1998 8 18 12 17 TONY 14.2 155.6 103 147 +1954 8 26 6 15 ERNESTO 24.9 182.0 134 614 +1960 10 8 18 21 FLORENCE 49.5 1.0 81 275 +1954 12 15 6 5 WILLIAM 26.8 239.1 111 461 +2001 3 8 12 22 OSCAR 50.4 326.7 20 180 +2004 4 6 6 12 PATTY 56.4 15.2 18 511 +1987 9 17 6 23 JOYCE 63.5 319.1 48 342 +1996 2 9 6 25 KIRK 59.1 82.6 76 256 +1959 1 16 6 11 KIRK 51.1 207.3 10 62 +1987 1 6 6 3 RAFAEL 13.7 276.6 161 673 +1968 11 5 0 5 HELENE 27.0 142.9 116 622 +1975 5 19 12 26 PATTY 25.5 68.5 111 118 +2004 10 27 6 25 NADINE 38.1 276.9 115 13 +1982 6 28 12 13 MICHAEL 22.4 243.0 151 352 +1956 2 2 6 15 OSCAR 50.2 226.2 140 536 +1992 3 21 6 21 WILLIAM 42.3 177.5 93 250 +1964 9 18 18 11 NADINE 59.0 43.6 84 657 +1955 2 13 18 8 BERYL 17.3 333.0 26 474 +1992 3 9 6 13 ALBERTO 30.9 314.0 105 74 +1965 12 15 6 5 ALBERTO 26.1 335.0 153 775 +1972 7 3 12 27 ISAAC 12.3 191.7 17 645 +1974 8 27 12 12 OSCAR 52.2 223.3 24 129 +1996 3 18 12 15 TONY 18.6 234.7 27 204 +2001 2 27 0 24 ERNESTO 9.5 263.4 48 336 +1969 9 15 18 20 NADINE 23.6 260.6 55 38 +1956 9 13 0 5 KIRK 7.3 26.4 63 413 +1985 5 15 12 4 CHRIS 69.2 147.0 122 302 +1980 1 8 18 19 BERYL 63.9 251.1 150 319 +1966 5 27 12 20 FLORENCE 14.3 170.1 113 488 +1988 5 6 12 2 BERYL 66.6 119.3 47 491 +1964 11 28 12 5 GORDON 11.1 90.8 159 553 +1954 2 22 6 28 WILLIAM 64.1 2.1 27 165 +1971 3 23 0 3 ALBERTO 13.3 220.2 93 472 +1989 3 25 0 3 SANDY 59.0 276.0 137 23 +1959 1 8 12 23 LESLIE 29.1 343.5 36 30 +1950 3 28 0 10 JOYCE 40.8 265.9 34 131 +1984 9 11 18 8 WILLIAM 21.2 338.4 122 200 +1959 1 7 12 23 BERYL 47.6 154.5 36 887 +1999 3 26 6 28 BERYL 45.6 80.5 100 891 +2004 10 9 12 12 ISAAC 63.6 320.4 123 358 +1952 6 1 12 26 PATTY 26.1 349.6 152 472 +1950 3 16 18 18 BERYL 57.2 115.3 144 595 +1974 10 22 18 19 VALERIE 27.3 36.4 120 781 +1999 11 11 12 22 FLORENCE 19.4 265.0 11 680 +1968 6 18 18 13 CHRIS 51.2 159.3 72 327 +1975 9 7 12 28 VALERIE 35.9 147.7 66 27 +1987 9 28 12 23 SANDY 26.9 60.9 47 416 +1979 5 16 0 21 CHRIS 23.4 168.2 79 777 +1958 2 6 12 9 SANDY 64.8 296.4 19 462 +2004 12 6 0 11 PATTY 13.2 269.5 96 748 +1967 10 16 6 16 OSCAR 60.6 0.8 135 26 +1996 9 22 18 14 NADINE 42.7 333.8 35 511 +1977 8 5 6 4 LESLIE 56.7 293.8 118 802 +1972 2 4 18 14 HELENE 60.9 233.0 59 532 +1998 7 14 6 22 MICHAEL 65.4 120.9 47 530 +1954 11 17 0 28 KIRK 41.4 56.8 25 370 +1991 1 28 12 11 DEBBY 8.3 12.8 32 63 +1991 8 12 12 16 DEBBY 7.1 168.7 11 725 +1982 5 6 18 23 OSCAR 67.2 304.1 40 498 +1988 12 5 12 4 NADINE 12.9 294.1 39 785 +1950 5 23 18 17 ISAAC 45.4 147.2 99 105 +1990 9 20 18 22 ALBERTO 46.9 352.4 55 1 +1986 5 5 0 18 NADINE 65.5 175.2 132 413 +2001 2 2 6 4 HELENE 61.0 70.8 78 309 +1970 3 7 18 5 SANDY 12.4 20.9 43 71 +1961 12 17 12 15 RAFAEL 30.4 300.6 99 609 +1957 10 27 6 15 OSCAR 37.7 297.3 29 173 +1999 5 3 6 10 WILLIAM 52.7 215.9 132 249 +1985 10 7 18 15 ERNESTO 64.3 282.1 127 332 +1981 8 5 18 10 SANDY 55.0 147.1 30 88 +1995 6 7 6 18 SANDY 15.0 314.4 107 362 +1987 4 26 0 15 OSCAR 13.5 35.7 39 518 +2000 4 15 18 2 PATTY 68.6 298.1 114 586 +1962 1 18 6 7 MICHAEL 9.4 120.4 12 864 +1953 11 25 6 28 BERYL 44.1 278.4 21 180 +1956 10 25 12 7 RAFAEL 23.2 228.2 119 712 +1950 10 5 18 19 DEBBY 42.8 195.7 102 138 +2001 3 26 12 9 MICHAEL 52.5 126.1 97 359 +1955 5 27 6 2 FLORENCE 68.5 6.8 126 35 +1988 1 26 18 25 OSCAR 19.9 287.0 109 851 +1981 12 10 18 14 DEBBY 21.7 219.3 109 162 +1988 9 20 0 19 PATTY 28.0 204.6 47 332 +1972 3 20 18 2 VALERIE 57.7 103.0 56 682 +1985 1 12 6 6 ISAAC 67.1 63.0 117 663 +1992 10 14 12 10 ALBERTO 30.5 13.1 77 892 +2004 4 9 18 7 LESLIE 9.8 11.1 117 404 +2004 11 18 18 5 OSCAR 38.8 95.1 86 497 +1965 5 12 6 15 PATTY 29.2 285.8 102 381 +2004 11 28 18 7 BERYL 42.4 46.6 68 524 +2001 8 12 12 20 DEBBY 62.1 277.5 32 3 +1972 8 17 6 17 GORDON 39.5 152.3 161 897 +1966 3 14 18 7 BERYL 24.2 350.9 144 319 +1981 7 9 6 21 WILLIAM 11.8 49.0 96 405 +1990 6 6 18 7 CHRIS 37.4 287.7 64 422 +1970 8 28 18 3 MICHAEL 12.8 206.6 131 20 +1967 4 19 6 20 ALBERTO 29.3 200.3 143 28 +1964 8 18 0 21 KIRK 31.1 222.2 84 343 +2002 3 10 18 2 JOYCE 48.3 316.9 83 848 +1970 5 17 0 1 FLORENCE 59.8 78.5 67 754 +1956 7 11 12 4 LESLIE 65.5 291.6 50 496 +1955 1 10 0 22 NADINE 21.0 262.9 57 512 +1971 4 14 6 25 NADINE 19.8 253.0 93 55 +1986 11 23 12 10 WILLIAM 18.0 128.3 124 85 +1955 11 26 0 12 OSCAR 16.3 262.5 71 272 +1971 9 4 18 7 VALERIE 8.1 190.6 80 608 +1981 6 2 0 9 WILLIAM 48.5 312.3 37 513 +1985 9 20 18 19 OSCAR 45.2 134.0 146 389 +1979 7 19 6 16 GORDON 23.8 308.4 164 511 +1958 5 28 0 24 DEBBY 54.8 263.2 81 221 +1996 1 11 18 16 LESLIE 52.4 229.7 54 680 +1985 8 20 18 15 BERYL 11.5 254.4 39 317 +1962 6 20 0 10 OSCAR 45.0 167.8 118 568 +1952 7 10 18 26 BERYL 53.6 143.8 18 889 +1958 1 6 18 19 DEBBY 58.3 40.3 60 264 +1967 1 22 6 13 BERYL 27.7 60.5 109 394 +1969 6 13 12 1 MICHAEL 16.1 17.3 62 613 +1962 9 12 6 17 VALERIE 12.7 258.2 46 358 +1983 8 21 12 15 PATTY 49.3 230.0 40 732 +2002 1 13 12 22 TONY 52.4 34.8 129 296 +1982 4 5 12 11 MICHAEL 65.9 110.3 11 532 +1980 11 19 18 15 WILLIAM 13.9 40.4 153 843 +1988 7 1 0 6 BERYL 24.0 231.4 114 96 +1980 9 5 6 18 PATTY 50.7 58.7 18 186 +1990 9 5 18 9 HELENE 64.1 189.0 157 163 +1989 9 1 12 13 PATTY 65.3 131.6 138 830 +1977 11 12 0 10 VALERIE 38.6 12.8 73 152 +2004 6 9 0 1 KIRK 35.6 328.5 38 568 +1961 11 17 6 2 SANDY 29.0 52.2 136 656 +1991 6 16 18 25 PATTY 65.1 261.2 67 463 +1953 3 22 18 11 GORDON 49.7 121.6 79 440 +1954 5 7 18 9 DEBBY 39.8 358.0 104 309 +1950 11 16 12 11 SANDY 36.0 125.0 125 19 +1976 2 7 18 26 DEBBY 55.4 211.7 55 651 +2003 8 20 18 26 ERNESTO 63.4 140.8 22 886 +1976 6 13 18 25 CHRIS 53.7 14.2 107 7 +1975 1 9 18 11 WILLIAM 64.7 130.5 112 414 +1977 4 8 0 19 FLORENCE 14.8 20.9 88 684 +2003 11 26 12 8 ALBERTO 37.0 169.1 68 647 +1990 10 16 18 8 TONY 52.6 335.5 13 471 +1958 8 25 12 27 DEBBY 19.6 339.9 21 660 +1980 2 12 12 3 CHRIS 17.5 137.4 72 647 +1995 2 11 18 22 KIRK 31.9 219.6 154 623 +1970 10 22 18 22 GORDON 14.4 194.1 85 13 +2003 6 15 6 6 SANDY 61.6 53.2 64 580 +1973 9 24 12 12 ERNESTO 53.9 230.3 11 51 +1965 1 10 18 17 HELENE 22.1 94.3 94 483 +1979 7 27 18 2 SANDY 38.0 69.4 145 580 +1977 3 14 18 7 FLORENCE 49.4 116.4 34 130 +1983 8 12 0 26 PATTY 30.5 356.7 66 641 +1979 10 20 18 9 VALERIE 13.8 270.8 108 448 +1970 3 24 0 7 ISAAC 19.8 17.9 36 158 +1970 12 9 0 6 TONY 26.4 63.7 50 679 +2000 3 24 18 20 RAFAEL 49.0 308.0 111 383 +1957 4 19 12 25 GORDON 15.7 208.0 91 198 +1968 6 26 12 11 ERNESTO 52.8 239.5 143 194 +1996 8 20 6 15 ISAAC 55.0 181.9 107 831 +1974 12 4 6 6 ISAAC 55.5 283.1 67 127 +1961 5 16 0 18 SANDY 21.0 297.4 11 411 +1961 7 16 0 22 FLORENCE 67.8 177.2 14 510 +1972 3 12 0 16 VALERIE 44.7 14.1 11 680 +2004 1 18 6 6 FLORENCE 56.1 188.2 114 259 +1987 4 22 0 28 VALERIE 36.6 317.0 134 194 +2000 2 16 12 5 LESLIE 61.3 22.4 46 390 +1966 12 14 12 20 CHRIS 68.9 56.3 79 215 +1967 9 2 6 7 ISAAC 13.1 216.1 115 536 +1990 10 18 18 10 OSCAR 42.1 12.8 109 485 +1994 1 20 12 15 GORDON 25.2 226.2 122 656 +1967 2 2 12 28 WILLIAM 21.6 28.3 11 875 +1998 6 17 0 16 CHRIS 29.9 228.6 105 361 +1979 7 11 6 17 OSCAR 17.7 127.4 19 136 +1964 7 26 12 19 HELENE 26.1 53.3 35 151 +1981 12 2 12 1 RAFAEL 43.8 241.3 123 252 +2003 10 27 12 9 MICHAEL 39.9 212.6 154 454 +1995 12 16 6 25 KIRK 46.8 31.8 66 823 +1970 7 8 12 1 RAFAEL 56.9 97.7 57 241 +1990 7 13 18 7 KIRK 35.2 45.1 103 729 +1993 11 11 18 25 LESLIE 36.0 33.4 105 411 +1966 5 6 12 17 OSCAR 35.2 129.9 120 878 +1988 8 11 18 5 DEBBY 18.0 81.3 141 295 +1963 4 3 18 26 HELENE 20.2 43.6 129 528 +1993 1 12 0 9 BERYL 60.2 42.6 129 416 +1987 7 18 0 9 CHRIS 59.1 348.2 137 593 +1976 6 20 0 2 HELENE 43.4 327.8 44 149 +1972 12 17 0 17 VALERIE 53.1 191.7 109 880 +1950 1 25 18 22 CHRIS 63.1 134.0 149 869 +1983 6 4 6 21 LESLIE 9.5 326.7 95 396 +1951 11 6 18 17 ISAAC 48.8 200.0 23 175 +1971 3 5 18 2 FLORENCE 40.4 17.9 75 168 +1992 10 13 0 4 SANDY 43.8 335.4 15 159 +1951 7 15 6 23 MICHAEL 14.6 234.8 115 412 +1951 5 2 12 8 FLORENCE 58.8 233.1 78 600 +2001 4 25 18 25 LESLIE 70.0 35.0 112 763 +1963 9 17 0 14 CHRIS 28.5 19.4 66 819 +1992 8 7 18 27 FLORENCE 16.8 249.9 67 666 +1988 5 18 0 15 HELENE 22.4 154.5 66 563 +1971 6 8 12 4 JOYCE 7.6 134.7 63 318 +1961 12 13 18 20 SANDY 16.4 262.5 99 592 +1992 10 1 18 1 OSCAR 55.7 132.0 143 100 +1977 8 14 12 24 JOYCE 25.7 309.6 27 484 +1962 7 6 0 14 DEBBY 33.4 166.1 64 720 +1967 6 9 12 16 OSCAR 55.9 341.2 17 533 +1955 1 7 12 2 WILLIAM 40.6 62.2 148 791 +1979 4 11 18 20 SANDY 60.0 87.3 20 332 +1978 9 10 18 5 FLORENCE 15.8 256.4 112 159 +1959 11 11 0 27 HELENE 18.0 72.1 56 295 +1976 1 15 12 4 GORDON 48.0 296.6 86 516 +1994 5 6 18 7 SANDY 57.5 274.3 68 526 +1951 5 1 6 6 TONY 24.6 306.3 54 536 +1966 5 10 18 17 ALBERTO 59.8 257.0 106 727 +1993 4 9 12 25 ISAAC 57.8 38.1 12 610 +1981 4 2 6 27 SANDY 49.8 70.3 147 678 +1962 12 17 0 5 PATTY 43.6 240.6 158 344 +1969 5 19 6 10 NADINE 65.9 252.5 70 347 +1971 2 9 6 4 MICHAEL 65.0 129.0 152 696 +1985 8 3 6 20 DEBBY 33.9 25.3 86 232 +1957 1 11 6 25 ALBERTO 64.6 332.9 127 142 +2003 4 10 12 7 PATTY 57.3 16.8 104 855 +1966 6 12 12 22 NADINE 24.2 258.8 115 128 +1990 11 16 0 16 TONY 8.3 23.6 32 492 +1962 6 24 0 27 PATTY 58.5 316.6 63 713 +1982 3 4 0 8 TONY 38.5 180.6 147 435 +1958 5 28 18 24 PATTY 26.1 141.4 15 101 +1968 12 23 12 27 OSCAR 13.8 287.8 15 24 +1994 7 26 0 22 DEBBY 22.4 14.8 28 518 +2004 7 14 18 22 RAFAEL 32.9 232.6 75 702 +1980 1 4 12 11 KIRK 42.0 1.1 135 504 +1981 2 25 0 13 WILLIAM 41.9 341.9 23 198 +1976 9 2 6 20 ERNESTO 56.7 23.5 133 892 +1950 11 23 12 22 HELENE 8.8 328.0 115 546 +1975 7 20 18 11 OSCAR 11.0 189.3 61 487 +1973 8 21 12 23 VALERIE 64.0 93.9 157 211 +1956 8 19 0 27 JOYCE 20.8 5.8 53 811 +1971 10 12 0 21 PATTY 42.9 195.7 123 337 +1951 6 11 0 14 MICHAEL 27.4 277.9 163 283 +1975 6 4 6 20 HELENE 33.6 146.6 45 649 +1950 3 23 12 14 KIRK 37.6 18.2 74 743 +2003 12 7 6 1 OSCAR 26.9 151.3 67 706 +1966 3 26 0 18 FLORENCE 27.9 79.2 98 721 +1975 2 6 12 28 SANDY 56.2 136.7 141 412 +1995 6 18 0 19 RAFAEL 50.8 316.4 31 450 +1975 3 23 0 18 ALBERTO 52.4 112.2 154 485 +1977 2 17 18 26 CHRIS 66.5 290.1 69 580 +2001 2 23 0 2 CHRIS 10.5 138.5 20 883 +1990 9 6 0 16 MICHAEL 37.6 347.7 116 506 +1986 7 10 6 16 VALERIE 18.3 221.9 70 735 +1995 9 2 6 26 GORDON 14.1 271.4 27 596 +2003 5 11 0 23 RAFAEL 62.0 214.3 161 553 +1987 1 17 6 9 OSCAR 9.8 321.8 84 872 +1951 3 23 18 25 LESLIE 7.2 181.5 119 183 +1952 6 17 0 26 SANDY 15.0 127.2 32 207 +1979 10 16 18 20 LESLIE 38.3 344.0 90 448 +1969 4 24 0 13 CHRIS 38.7 3.8 112 820 +1997 2 14 0 12 RAFAEL 19.7 132.8 37 663 +1962 3 9 0 17 MICHAEL 33.5 347.7 14 315 +1982 3 7 0 2 LESLIE 64.5 152.8 37 529 +1954 12 25 0 4 BERYL 47.6 25.0 31 50 +1998 4 19 12 19 LESLIE 58.5 266.0 97 449 +1973 2 25 18 24 ERNESTO 41.1 133.5 64 498 +1971 12 23 12 20 ALBERTO 58.5 53.4 112 143 +1989 12 20 0 20 BERYL 40.6 355.0 129 271 +2002 12 15 6 28 TONY 64.7 150.7 41 565 +1994 11 12 0 1 ISAAC 69.3 97.1 105 862 +1960 7 3 12 17 RAFAEL 25.3 338.5 128 548 +1990 12 4 0 6 NADINE 21.9 261.7 156 383 +2001 2 21 0 9 RAFAEL 18.4 134.6 144 882 +1998 6 21 18 2 WILLIAM 23.0 329.7 128 61 +1973 1 3 18 5 JOYCE 56.4 315.9 124 557 +1992 10 17 6 23 ISAAC 17.6 48.6 161 887 +1984 9 27 0 16 MICHAEL 63.7 297.1 12 573 +1961 6 20 18 28 MICHAEL 21.8 262.3 39 52 +1967 1 11 18 21 ALBERTO 36.4 307.1 127 795 +1951 11 7 12 14 KIRK 60.5 152.2 16 837 +1956 5 17 12 6 HELENE 20.4 100.5 121 760 +1979 1 22 18 2 WILLIAM 42.9 242.9 36 153 +1989 6 22 18 13 HELENE 69.7 122.7 139 49 +1950 5 4 6 26 VALERIE 8.8 96.3 40 211 +1986 6 22 12 15 KIRK 66.3 169.2 24 171 +1971 5 8 0 22 NADINE 54.8 268.7 43 135 +1954 9 20 0 28 ISAAC 25.8 164.5 149 346 +1975 11 27 18 8 MICHAEL 64.7 75.7 19 254 +1995 2 9 6 19 BERYL 38.2 239.1 46 239 +1998 10 21 18 27 LESLIE 40.2 211.1 41 380 +1993 4 13 12 14 ERNESTO 19.9 253.7 68 540 +1972 11 2 12 27 ALBERTO 33.0 317.9 157 517 +2003 8 12 12 12 ISAAC 45.5 126.1 44 739 +1951 3 9 0 19 FLORENCE 34.3 344.7 50 703 +1961 6 5 18 23 CHRIS 23.6 244.8 145 463 +1954 4 28 6 15 WILLIAM 23.6 237.5 67 209 +1967 5 11 18 26 ERNESTO 28.5 59.2 121 341 +2004 1 9 6 13 ALBERTO 43.0 303.9 78 675 +1995 10 20 6 3 TONY 15.5 156.9 157 150 +2000 4 4 12 15 ISAAC 29.9 161.8 142 295 +1960 5 19 12 1 ERNESTO 25.5 314.4 52 611 +1978 6 1 6 15 ALBERTO 34.6 33.3 61 683 +1971 8 11 6 20 JOYCE 24.7 173.8 74 599 +1965 1 2 12 2 JOYCE 47.7 276.6 80 404 +2004 12 3 0 3 LESLIE 66.4 218.7 132 619 +1990 6 5 0 13 JOYCE 66.3 99.7 51 9 +1985 7 12 18 21 RAFAEL 63.2 315.6 99 869 +1959 1 13 0 27 ISAAC 27.0 20.2 96 50 +1965 12 21 12 25 ERNESTO 64.8 140.8 18 722 +1958 6 15 6 20 MICHAEL 36.2 172.0 89 476 +1958 11 5 6 6 VALERIE 15.7 50.4 114 302 +1990 2 5 12 8 ALBERTO 48.7 342.5 123 569 +1998 1 4 18 8 DEBBY 44.9 50.0 59 321 +1955 12 2 6 8 WILLIAM 63.8 280.6 150 720 +1995 11 14 18 26 PATTY 20.8 316.1 62 235 +2004 6 27 6 9 VALERIE 42.1 7.6 90 220 +1993 6 4 0 10 DEBBY 48.4 237.5 42 253 +1962 10 4 12 9 VALERIE 53.3 152.1 108 130 +1994 11 19 18 20 RAFAEL 54.4 22.3 65 113 +1990 1 28 0 23 WILLIAM 29.9 145.4 23 521 +1978 9 8 18 25 WILLIAM 14.6 263.0 100 720 +1953 3 24 18 10 JOYCE 13.3 285.9 133 897 +1966 8 22 0 28 LESLIE 18.9 318.9 79 896 +1964 7 8 6 11 HELENE 36.8 77.5 45 860 +1954 9 7 18 24 RAFAEL 66.1 83.2 74 883 +1961 5 1 6 14 PATTY 42.3 273.2 159 37 +1989 9 4 0 7 MICHAEL 36.1 228.5 56 579 +1966 3 7 18 5 ERNESTO 23.6 226.2 112 433 +1970 4 23 12 13 ISAAC 56.9 283.1 88 175 +1951 8 23 12 23 RAFAEL 43.9 78.7 148 442 +1985 5 24 0 8 ISAAC 37.9 23.5 121 217 +1984 4 11 18 11 OSCAR 13.8 41.1 137 410 +1979 8 13 18 28 LESLIE 44.0 325.3 88 646 +2003 2 17 18 23 MICHAEL 19.6 313.4 146 9 +1971 10 18 18 18 ALBERTO 26.5 157.5 150 674 +1985 7 18 18 28 JOYCE 24.1 270.4 45 804 +1999 7 28 0 10 FLORENCE 43.1 285.5 155 360 +1961 5 7 12 15 RAFAEL 31.6 128.8 68 385 +1960 7 20 18 28 RAFAEL 34.3 289.1 97 508 +1985 11 17 0 3 ISAAC 10.0 12.4 82 182 +1972 12 9 0 9 BERYL 15.9 151.2 161 170 +1970 1 7 6 4 FLORENCE 12.4 331.2 59 587 +1950 2 13 12 17 ERNESTO 63.4 288.3 63 74 +1988 2 5 12 11 NADINE 17.2 25.1 14 457 +1998 9 6 0 27 HELENE 12.7 91.3 44 279 +1974 8 14 12 10 LESLIE 32.9 147.8 140 124 +1998 8 26 18 28 GORDON 37.9 134.0 113 41 +1967 10 14 12 26 ALBERTO 9.2 221.5 148 544 +1967 8 9 6 24 LESLIE 43.0 350.3 85 713 +1978 9 24 6 2 MICHAEL 59.3 251.2 59 550 +1954 2 12 18 5 JOYCE 24.4 122.3 141 620 +1993 2 6 12 20 LESLIE 18.1 11.1 128 490 +1981 1 12 0 17 GORDON 32.3 136.6 69 584 +1971 5 28 0 17 PATTY 14.2 243.0 17 421 +1952 2 23 18 1 WILLIAM 25.2 350.0 43 561 +1981 3 26 0 25 BERYL 18.0 175.5 159 622 +1997 5 19 6 22 CHRIS 11.9 21.7 70 805 +2004 8 9 0 17 RAFAEL 60.0 290.9 147 295 +1965 1 24 12 13 GORDON 62.2 193.3 129 8 +1956 3 12 18 7 JOYCE 58.6 106.7 83 613 +1959 1 10 0 24 TONY 46.6 340.2 45 522 +2003 7 19 0 25 SANDY 67.0 219.6 97 883 +1970 3 3 0 17 CHRIS 52.1 129.1 55 65 +1998 1 22 18 19 FLORENCE 40.3 61.2 66 345 +1989 8 16 18 27 NADINE 13.9 213.3 103 359 +1993 9 25 18 12 FLORENCE 24.1 142.3 85 213 +1994 7 21 6 23 ERNESTO 10.8 357.1 21 870 +1963 4 17 6 5 NADINE 66.1 184.5 62 211 +1962 7 21 6 24 CHRIS 7.7 166.1 18 364 +1979 5 21 12 2 SANDY 15.3 195.2 32 83 +1954 1 2 0 22 TONY 29.5 217.3 146 388 +1988 3 13 6 26 PATTY 7.7 298.9 120 11 +1983 6 4 12 19 OSCAR 37.8 192.8 80 581 +1988 2 21 18 26 NADINE 52.5 147.1 105 292 +1983 12 17 0 2 VALERIE 63.7 301.1 21 205 +1988 12 16 12 7 SANDY 12.6 330.2 84 31 +1962 8 9 0 24 ERNESTO 33.2 31.7 54 395 +1988 9 4 6 24 FLORENCE 22.9 318.7 54 843 +1967 7 4 0 2 JOYCE 58.1 44.2 88 41 +1997 3 11 18 4 KIRK 40.5 45.8 104 330 +1972 5 8 18 10 ISAAC 59.2 36.7 158 446 +1987 8 9 12 12 HELENE 20.7 80.2 14 459 +1996 12 25 0 2 NADINE 10.2 322.3 65 747 +1988 5 15 6 15 CHRIS 49.1 143.9 60 833 +1973 9 23 6 19 LESLIE 19.7 203.1 110 164 +1999 6 28 12 20 WILLIAM 40.9 66.4 74 112 +1995 4 12 0 15 GORDON 67.1 30.2 107 770 +1994 11 2 12 28 CHRIS 43.8 84.9 114 23 +1967 5 4 12 25 RAFAEL 38.6 299.6 75 109 +1987 1 22 12 24 TONY 35.6 248.8 52 667 +1961 7 8 6 21 CHRIS 37.1 59.5 47 805 +1960 9 25 12 6 KIRK 45.7 69.2 110 411 +2001 2 26 18 12 LESLIE 54.7 158.7 41 664 +1989 7 9 18 15 ERNESTO 56.4 159.0 112 547 +1975 1 15 0 18 TONY 32.3 2.2 18 319 +1977 7 8 18 20 VALERIE 65.6 225.7 153 814 +1967 7 25 18 1 OSCAR 21.8 273.5 130 82 +1965 2 24 18 19 VALERIE 68.9 236.3 108 844 +2000 5 23 18 1 WILLIAM 45.7 256.0 79 490 +1987 12 16 12 16 HELENE 23.0 155.2 29 887 +1977 9 25 18 16 KIRK 22.5 33.2 86 850 +1968 11 25 12 24 NADINE 40.2 180.6 20 159 +1955 9 26 6 9 PATTY 61.2 126.0 128 438 +1963 2 13 0 27 PATTY 37.5 18.2 72 220 +1962 6 22 18 2 TONY 38.7 49.3 116 629 +1976 12 25 0 10 ALBERTO 42.0 144.0 156 665 +1982 6 17 6 20 MICHAEL 52.4 310.3 109 627 +1977 12 5 0 27 JOYCE 18.1 280.4 28 147 +1976 8 24 0 19 FLORENCE 32.6 18.5 49 771 +1955 11 11 6 1 DEBBY 14.5 299.9 30 809 +1965 6 6 12 24 VALERIE 14.2 321.4 90 835 +1979 6 3 18 19 LESLIE 45.6 30.1 147 277 +2002 3 5 18 28 ISAAC 57.5 59.6 54 556 +1965 5 20 6 18 BERYL 64.0 186.1 98 86 +1964 8 16 6 17 LESLIE 18.1 106.7 139 559 +1984 10 4 0 28 ISAAC 12.6 319.9 131 442 +1953 3 7 12 13 WILLIAM 35.5 321.0 26 609 +1968 6 27 12 25 GORDON 38.7 261.9 34 718 +2003 12 11 12 8 ISAAC 29.0 278.5 162 138 +1987 2 5 18 18 PATTY 58.1 138.3 149 285 +1960 8 9 18 24 ALBERTO 56.1 37.5 51 74 +1961 5 17 12 4 LESLIE 39.2 295.7 61 518 +1958 9 23 0 19 RAFAEL 25.7 94.7 142 342 +1968 5 8 6 18 LESLIE 53.0 42.1 97 421 +1993 6 19 6 7 HELENE 8.3 219.4 11 736 +1990 5 8 18 3 PATTY 54.1 100.4 90 183 +1969 6 17 6 26 ALBERTO 44.3 295.9 151 307 +2001 3 6 0 16 BERYL 65.7 174.6 28 310 +1954 10 23 12 3 ERNESTO 67.3 121.5 84 114 +1993 6 17 0 11 KIRK 35.2 158.6 40 260 +1963 6 5 6 25 LESLIE 62.7 34.6 77 312 +1978 9 10 6 27 WILLIAM 69.6 31.9 98 75 +1968 5 5 18 2 KIRK 23.7 244.9 86 10 +1989 11 20 12 12 ISAAC 62.5 110.7 118 133 +2001 2 27 18 22 ERNESTO 41.5 205.2 11 5 +1967 7 8 18 18 KIRK 40.6 349.4 135 329 +1955 10 18 6 21 DEBBY 53.2 280.4 144 133 +1979 10 10 18 26 WILLIAM 34.2 218.8 31 820 +1989 12 18 0 21 VALERIE 55.1 26.3 87 531 +2004 12 19 0 21 FLORENCE 43.5 80.6 121 627 +1958 11 18 12 11 VALERIE 16.9 122.5 159 638 +1965 10 23 18 16 ALBERTO 32.0 2.4 11 326 +1976 7 23 18 23 OSCAR 42.4 37.3 75 649 +1985 12 14 18 24 TONY 8.4 153.2 116 15 +1957 3 16 6 3 BERYL 64.6 37.0 138 456 +1986 5 3 6 4 RAFAEL 21.8 197.3 132 328 +1979 11 5 6 7 SANDY 24.9 92.1 52 188 +1950 4 17 6 10 LESLIE 47.3 82.0 135 242 +1963 12 24 18 4 ISAAC 27.1 286.6 60 801 +1985 4 3 12 28 SANDY 54.5 234.6 62 869 +1952 9 26 0 24 OSCAR 11.4 129.7 17 537 +1963 8 7 0 28 ISAAC 21.7 285.8 26 880 +1992 12 15 12 27 TONY 67.5 241.0 67 548 +1978 2 13 0 28 MICHAEL 16.6 165.2 70 506 +1951 8 6 12 24 LESLIE 17.5 159.5 90 451 +1990 7 11 12 16 FLORENCE 63.8 235.5 19 666 +1993 7 25 6 11 TONY 16.7 13.3 120 741 +1963 4 7 0 20 VALERIE 9.5 247.7 17 422 +1994 5 21 12 7 SANDY 56.6 318.0 11 826 +2002 3 2 0 7 RAFAEL 49.7 347.8 118 896 +1957 1 9 0 7 WILLIAM 68.6 207.0 143 240 +1984 2 6 0 11 ERNESTO 27.1 298.5 72 768 +2003 4 22 12 28 FLORENCE 39.4 105.9 142 701 +1978 3 20 12 1 PATTY 29.4 111.5 16 280 +1984 11 26 12 14 DEBBY 12.1 315.6 50 554 +1985 11 14 6 21 TONY 47.2 13.1 19 579 +1962 2 25 0 14 ALBERTO 28.9 189.6 11 400 +1985 10 28 0 26 MICHAEL 28.6 264.7 64 686 +1980 9 28 18 16 FLORENCE 24.9 178.1 55 427 +1988 10 1 12 24 HELENE 62.6 229.0 38 514 +1997 3 7 18 14 WILLIAM 20.8 282.2 26 339 +1964 1 26 6 4 FLORENCE 21.7 94.0 107 83 +2004 9 12 6 11 BERYL 46.0 39.6 126 826 +1982 6 5 18 19 BERYL 14.8 354.9 34 302 +1997 11 14 12 24 HELENE 30.5 89.8 134 529 +1987 6 6 0 1 ISAAC 55.2 48.6 51 361 +1990 5 7 18 8 ALBERTO 22.2 84.7 108 150 +1971 1 3 0 17 DEBBY 46.0 263.7 60 5 +1972 7 20 12 14 KIRK 54.6 63.5 99 672 +1957 8 19 0 14 ALBERTO 55.1 310.4 134 634 +1993 5 27 0 16 OSCAR 14.3 195.3 140 64 +1960 2 11 18 19 VALERIE 45.9 149.4 75 416 +1956 3 20 6 27 ALBERTO 12.7 237.4 25 516 +1975 4 24 12 5 ISAAC 41.3 316.9 37 612 +1952 10 13 0 23 MICHAEL 18.4 20.8 160 228 +1969 3 19 18 12 RAFAEL 14.4 55.8 157 4 +1994 9 3 12 2 LESLIE 13.4 146.0 157 843 +1952 1 6 12 5 CHRIS 51.0 179.2 21 577 +1977 1 20 0 24 VALERIE 17.5 336.5 117 790 +1983 9 10 18 24 OSCAR 33.5 351.7 148 133 +1994 8 16 6 20 LESLIE 43.3 77.0 163 16 +2003 5 13 12 27 LESLIE 39.6 37.2 60 72 +1993 8 24 18 28 HELENE 25.7 82.8 142 130 +1997 3 7 6 16 HELENE 33.9 334.9 70 536 +2003 1 10 6 11 SANDY 63.2 313.1 129 593 +1954 4 13 12 28 ISAAC 29.9 300.6 100 505 +1962 4 8 12 18 ISAAC 69.6 323.4 39 425 +1995 8 14 0 25 TONY 65.1 308.7 11 411 +1951 8 4 18 22 GORDON 39.5 162.7 111 870 +1987 8 4 12 13 HELENE 24.8 296.4 104 476 +1959 4 13 6 1 NADINE 18.2 342.7 91 799 +2004 2 18 12 21 ISAAC 19.7 293.2 114 217 +1986 9 9 0 14 WILLIAM 47.6 318.0 162 110 +1981 10 25 12 11 HELENE 11.5 333.6 34 650 +1960 6 2 18 21 FLORENCE 69.5 236.3 79 868 +1953 7 12 6 24 GORDON 43.9 121.5 26 411 +1961 1 11 6 25 LESLIE 22.6 239.4 134 398 +1994 10 27 6 10 ISAAC 19.3 325.2 155 477 +1999 2 14 0 9 LESLIE 13.4 20.5 96 680 +2000 10 2 18 23 WILLIAM 45.3 311.8 120 716 +1990 3 26 6 19 KIRK 33.2 249.7 102 40 +1958 3 5 12 17 PATTY 50.1 316.9 15 830 +1987 4 27 6 28 ALBERTO 50.4 302.6 82 49 +1981 2 8 0 25 SANDY 51.9 279.2 74 95 +1987 5 22 18 5 FLORENCE 66.4 146.7 51 317 +1966 1 16 12 4 OSCAR 56.0 309.0 134 805 +1956 10 5 18 11 SANDY 14.5 211.9 156 645 +1970 7 20 6 11 KIRK 38.3 83.4 36 270 +1993 9 27 6 28 CHRIS 14.8 7.2 106 845 +1963 2 12 6 3 LESLIE 61.5 216.2 94 421 +1994 6 16 0 8 DEBBY 34.0 257.2 160 536 +1971 1 24 12 24 SANDY 31.3 289.4 117 285 +1993 4 27 6 15 TONY 64.5 105.2 137 134 +1996 6 20 18 18 ERNESTO 42.6 193.7 68 380 +1996 6 8 12 16 ISAAC 22.1 55.7 64 485 +1973 10 5 12 3 PATTY 58.7 272.6 80 481 +1987 3 22 12 5 ERNESTO 39.0 33.6 70 59 +1968 7 6 12 1 ISAAC 53.0 267.5 141 227 +1972 8 5 0 16 VALERIE 58.0 200.7 24 774 +2000 10 7 0 17 ALBERTO 33.0 329.3 44 179 +1976 5 15 6 17 GORDON 9.0 37.3 74 14 +1994 10 15 12 16 SANDY 36.6 81.0 52 102 +1992 9 2 18 14 RAFAEL 17.5 227.4 116 9 +1970 5 26 6 10 OSCAR 60.6 81.5 21 341 +1975 6 6 6 1 NADINE 20.9 273.9 16 552 +1990 12 22 0 21 WILLIAM 35.7 206.6 15 525 +1952 11 8 0 21 PATTY 8.6 68.5 30 64 +1986 9 22 0 10 PATTY 26.5 203.6 148 337 +1965 10 27 18 5 CHRIS 55.5 357.6 108 151 +1967 10 11 12 13 ISAAC 12.8 97.6 104 184 +1963 3 13 18 21 WILLIAM 56.2 54.9 144 442 +1964 11 2 18 19 WILLIAM 47.4 29.2 94 577 +1974 11 4 6 11 JOYCE 21.1 1.3 154 620 +1987 2 4 6 1 BERYL 64.0 75.2 29 869 +1972 10 23 12 14 FLORENCE 31.1 31.8 75 833 +1974 4 23 18 2 ERNESTO 51.7 232.9 63 88 +1992 9 17 12 1 GORDON 48.2 114.9 69 517 +1986 11 1 12 18 OSCAR 31.0 304.8 106 514 +1978 7 3 6 1 CHRIS 24.5 82.4 122 233 +1952 3 7 0 13 NADINE 44.6 263.6 114 476 +1982 9 2 18 3 BERYL 60.7 155.4 28 763 +1996 10 20 0 23 GORDON 25.1 355.4 143 419 +1992 12 19 0 18 OSCAR 57.3 141.2 138 6 +1956 2 6 6 10 GORDON 55.5 89.1 36 786 +1978 4 9 18 23 RAFAEL 55.4 276.7 125 399 +1963 8 24 18 18 TONY 23.1 182.4 94 177 +1982 1 11 0 1 FLORENCE 21.2 150.9 57 145 +1998 3 25 0 24 NADINE 60.5 318.5 89 855 +1984 7 27 12 2 VALERIE 62.1 266.0 25 355 +2000 12 24 18 11 ISAAC 47.9 316.4 139 393 +1982 12 20 6 19 WILLIAM 14.3 223.6 150 724 +1987 2 19 6 23 HELENE 20.7 329.8 159 721 +1982 6 1 6 6 HELENE 26.2 205.2 147 705 +1957 8 6 12 3 ALBERTO 19.5 242.5 76 190 +1956 2 21 18 14 WILLIAM 8.9 327.7 95 561 +2004 12 14 18 5 FLORENCE 9.5 84.5 76 649 +1984 12 22 0 17 ISAAC 34.8 172.1 27 501 +1971 4 14 0 16 ALBERTO 14.1 315.5 108 722 +1973 1 10 6 22 FLORENCE 44.9 159.5 137 625 +1984 10 10 18 13 DEBBY 16.9 129.0 88 227 +1984 12 28 12 3 KIRK 55.2 0.1 58 740 +1999 12 7 0 16 ALBERTO 27.7 221.8 159 673 +1960 10 27 18 16 HELENE 18.1 103.8 51 325 +1962 6 6 12 19 NADINE 48.3 190.3 42 181 +1966 5 28 12 12 CHRIS 45.1 192.3 43 211 +1971 10 8 6 12 WILLIAM 45.3 332.4 53 492 +2003 9 15 6 1 LESLIE 7.0 208.3 28 747 +1998 5 4 12 11 NADINE 67.9 107.4 83 630 +1985 10 2 18 14 WILLIAM 24.5 188.0 75 507 +1986 1 14 6 7 VALERIE 31.3 141.5 54 279 +1952 8 21 6 21 JOYCE 51.0 324.9 25 705 +1965 8 18 18 22 MICHAEL 26.0 187.2 156 249 +1956 6 26 12 10 MICHAEL 27.9 145.7 116 247 +1996 5 1 6 15 JOYCE 47.4 323.8 118 500 +1966 2 28 0 10 KIRK 62.4 52.4 156 821 +1977 2 21 12 12 CHRIS 48.2 257.7 65 227 +1964 12 14 0 27 ISAAC 38.9 108.6 120 525 +1986 11 16 18 27 ERNESTO 59.6 205.3 152 272 +1983 9 10 6 22 BERYL 7.5 253.0 41 860 +1962 4 13 12 20 MICHAEL 42.5 43.6 75 721 +1970 10 15 18 22 WILLIAM 10.3 175.7 84 186 +1959 5 21 6 7 TONY 22.7 310.3 19 714 +1988 2 1 18 13 OSCAR 25.4 341.1 156 189 +1985 7 8 12 24 OSCAR 49.2 282.9 94 768 +1971 3 17 12 9 WILLIAM 7.1 294.4 63 266 +1961 8 18 12 15 WILLIAM 59.1 317.0 34 352 +1958 2 3 18 19 VALERIE 49.8 6.8 87 601 +1973 10 10 0 11 RAFAEL 30.1 343.3 159 766 +1950 4 26 18 27 DEBBY 34.0 213.1 102 346 +1973 11 17 6 19 ERNESTO 57.4 51.7 82 449 +1974 3 28 12 11 WILLIAM 62.9 260.4 93 344 +1962 4 4 18 10 KIRK 16.0 216.3 36 163 +2002 10 8 12 13 TONY 44.6 331.9 134 647 +1952 7 21 0 16 CHRIS 11.4 9.8 12 689 +1967 4 12 12 5 RAFAEL 24.1 347.3 65 371 +1965 6 19 6 8 TONY 25.5 237.5 135 593 +1958 10 9 0 2 SANDY 60.4 295.9 110 465 +1978 8 18 6 25 BERYL 28.9 69.7 97 683 +1968 2 1 18 18 FLORENCE 51.5 66.9 135 476 +1989 12 28 18 20 ERNESTO 56.8 25.9 10 409 +1993 11 9 18 5 ISAAC 48.9 14.4 164 719 +1995 5 22 12 1 CHRIS 25.8 308.4 16 113 +1989 3 11 0 16 FLORENCE 49.6 20.1 92 534 +1997 2 5 0 1 MICHAEL 11.9 141.4 58 45 +1996 12 21 18 6 MICHAEL 39.2 11.4 111 291 +1989 2 15 12 19 BERYL 36.4 199.9 17 803 +1990 2 15 12 12 CHRIS 38.1 61.2 122 100 +1975 5 9 6 17 PATTY 68.4 125.4 132 668 +1992 4 18 18 21 VALERIE 42.2 152.4 135 683 +1988 9 12 0 5 SANDY 59.1 317.6 83 735 +1986 8 28 18 26 BERYL 9.1 219.1 131 149 +1969 7 16 12 4 KIRK 48.3 254.6 63 585 +1988 9 12 12 18 HELENE 54.5 67.8 127 562 +2004 9 5 12 25 NADINE 42.5 149.7 64 838 +1991 8 10 0 16 WILLIAM 18.3 288.0 115 766 +1967 6 1 18 22 BERYL 52.0 272.6 149 879 +1962 10 23 6 26 DEBBY 61.5 138.3 83 502 +1964 6 1 12 26 BERYL 70.0 76.7 93 172 +1972 9 8 6 26 NADINE 36.7 248.9 126 751 +1999 12 20 0 13 HELENE 17.2 185.9 157 35 +1998 9 19 12 14 OSCAR 19.5 89.7 142 202 +1975 11 19 0 10 FLORENCE 52.9 246.7 151 874 +1977 11 4 0 2 SANDY 34.9 214.6 97 365 +1979 7 3 18 12 CHRIS 53.3 204.4 69 295 +1962 5 3 0 16 MICHAEL 68.3 54.6 119 297 +1974 9 27 6 3 OSCAR 66.6 81.1 151 11 +1992 11 17 18 23 DEBBY 33.2 348.7 29 669 +1952 12 24 18 22 SANDY 53.5 305.2 61 163 +1951 8 24 18 9 HELENE 49.9 39.7 125 111 +1972 5 13 18 6 RAFAEL 49.7 2.1 107 658 +1978 2 18 6 12 OSCAR 51.2 261.5 54 121 +1993 10 4 6 25 HELENE 47.8 148.3 54 293 +1983 7 11 12 27 VALERIE 35.5 88.7 104 535 +1968 9 16 18 13 DEBBY 37.1 355.9 110 700 +1998 2 18 0 7 KIRK 18.5 286.9 131 694 +1963 2 14 18 11 WILLIAM 64.6 41.2 161 730 +1977 2 15 18 10 GORDON 45.9 18.7 125 786 +1950 12 7 18 12 DEBBY 40.0 111.6 83 223 +1972 4 13 6 22 VALERIE 31.5 310.7 159 356 +1960 3 18 6 20 ERNESTO 40.7 174.4 63 485 +1969 12 4 12 3 LESLIE 17.2 247.6 141 412 +1961 8 18 6 18 RAFAEL 58.1 177.6 111 774 +2003 11 13 0 8 MICHAEL 64.5 1.3 39 539 +1958 1 7 18 3 WILLIAM 7.2 267.2 69 630 +2000 1 9 0 4 OSCAR 9.7 76.3 49 804 +1982 3 9 6 15 CHRIS 66.7 5.6 113 513 +1973 2 19 12 11 JOYCE 57.6 180.9 32 767 +1991 8 21 18 6 KIRK 32.8 133.2 77 565 +1990 8 20 12 6 SANDY 9.7 82.9 56 437 +1958 1 6 12 18 ERNESTO 33.9 42.8 75 246 +1989 8 4 18 12 KIRK 35.8 263.7 148 74 +1956 12 1 18 25 BERYL 29.8 105.3 72 806 +1996 2 3 18 20 GORDON 35.7 294.5 59 99 +1984 11 26 0 23 NADINE 67.8 88.1 23 388 +1992 4 15 0 9 PATTY 8.8 165.0 145 429 +1954 9 17 12 18 MICHAEL 21.4 71.6 161 757 +1953 4 1 6 15 DEBBY 52.5 142.2 120 10 +1996 5 11 0 22 WILLIAM 64.2 103.8 118 475 +2001 8 4 12 4 SANDY 65.9 221.0 112 785 +2002 8 15 6 4 LESLIE 20.1 231.6 54 782 +1956 11 22 0 5 RAFAEL 66.4 302.8 45 57 +1998 10 26 12 23 KIRK 28.7 54.2 43 805 +1976 4 19 18 18 DEBBY 68.7 58.5 138 642 +1994 1 2 12 28 ISAAC 60.3 356.5 41 538 +1962 8 20 6 9 OSCAR 54.6 161.8 127 818 +1955 11 19 12 17 ERNESTO 42.9 147.4 68 406 +1979 12 13 0 28 DEBBY 44.5 39.6 163 219 +1976 7 11 6 20 JOYCE 15.3 180.2 139 122 +1962 7 4 0 17 PATTY 54.2 84.7 89 53 +2003 11 21 6 4 LESLIE 28.7 55.8 44 576 +1971 10 1 0 16 CHRIS 13.5 90.6 42 564 +1964 9 9 18 11 NADINE 8.2 67.0 107 886 +1959 12 26 12 23 PATTY 39.5 35.6 74 887 +1998 5 21 6 16 HELENE 63.7 57.3 102 552 +1983 10 2 6 3 GORDON 20.3 59.8 130 381 +1973 12 19 12 22 LESLIE 48.0 72.1 161 495 +1965 9 5 0 19 ALBERTO 16.7 73.3 40 383 +1988 2 26 0 10 HELENE 40.1 225.5 162 322 +1954 5 5 0 15 DEBBY 58.2 2.6 89 886 +1976 11 4 6 28 DEBBY 21.0 48.4 113 784 +1988 11 21 0 3 KIRK 59.4 180.9 42 590 +1978 3 8 18 27 CHRIS 14.3 36.0 109 714 +1974 12 27 6 6 SANDY 44.5 239.9 31 859 +1980 5 22 6 20 SANDY 55.0 224.0 133 548 +1973 12 12 6 1 GORDON 28.9 230.5 21 103 +1999 5 4 6 19 ALBERTO 43.7 182.8 15 244 +1992 12 3 18 10 OSCAR 30.9 205.6 28 247 +1994 4 14 18 2 CHRIS 63.2 306.0 118 675 +1997 12 23 12 10 ALBERTO 30.8 339.7 33 830 +1955 1 27 0 12 ERNESTO 44.3 310.0 27 511 +2000 10 5 18 27 FLORENCE 67.7 349.9 128 604 +1970 6 7 6 19 ISAAC 34.6 203.3 86 498 +1982 11 11 12 28 HELENE 45.8 164.5 32 245 +1983 7 2 0 16 FLORENCE 39.8 244.5 98 532 +1992 12 25 0 25 HELENE 50.7 260.8 120 333 +1996 12 10 6 18 CHRIS 36.6 207.3 30 586 +1965 11 21 12 17 NADINE 49.3 9.9 128 771 +1999 1 9 0 19 RAFAEL 57.6 2.6 55 611 +1993 6 14 18 14 FLORENCE 64.0 323.4 154 637 +1984 12 23 0 3 ISAAC 58.6 254.7 12 862 +1964 11 20 0 10 BERYL 23.3 110.8 71 671 +1958 10 22 0 24 ISAAC 35.1 274.6 12 722 +1963 10 27 18 6 WILLIAM 35.1 248.4 45 7 +1976 12 2 0 25 HELENE 59.0 321.9 51 454 +2002 10 19 6 22 PATTY 67.2 80.5 145 193 +1972 1 18 18 5 ERNESTO 46.2 40.0 128 384 +1989 10 1 0 26 HELENE 19.9 187.6 125 122 +1967 1 7 6 23 HELENE 20.0 157.1 143 25 +1957 3 20 6 11 LESLIE 58.4 145.2 108 855 +1951 11 23 18 16 BERYL 42.6 342.2 92 496 +1974 4 13 18 4 PATTY 24.1 265.7 129 639 +1978 3 7 6 24 WILLIAM 24.9 281.9 32 440 +1957 2 9 18 14 NADINE 42.8 323.0 122 648 +2003 3 16 0 7 PATTY 14.7 314.2 18 713 +1986 5 3 6 3 SANDY 22.3 166.3 78 345 +1957 4 1 0 8 DEBBY 52.3 97.9 102 587 +1989 10 2 12 7 TONY 55.4 186.2 25 703 +1953 2 15 0 20 ERNESTO 53.1 266.2 71 71 +1999 8 18 12 20 VALERIE 68.9 322.3 146 251 +1950 10 2 18 4 CHRIS 17.7 188.2 40 801 +1977 3 24 12 25 BERYL 68.7 138.5 97 797 +1995 5 2 18 11 LESLIE 25.4 101.6 158 22 +1960 7 11 18 15 ALBERTO 63.5 218.0 131 712 +1973 2 23 0 1 ERNESTO 56.1 258.0 50 632 +1958 10 2 0 14 ERNESTO 50.0 195.8 52 494 +1950 10 19 18 26 VALERIE 66.5 10.9 37 175 +1973 5 23 6 12 ERNESTO 65.3 113.1 52 836 +1996 4 4 0 9 NADINE 66.7 206.4 134 119 +1960 11 15 0 16 TONY 34.4 339.3 85 568 +1973 2 5 12 25 DEBBY 53.5 64.0 160 873 +1951 11 25 0 24 BERYL 55.8 157.2 158 660 +1964 2 28 0 28 LESLIE 48.9 255.9 26 499 +1950 9 17 12 3 HELENE 42.3 67.1 18 818 +1953 9 4 0 11 SANDY 17.3 227.1 129 224 +1975 6 4 6 11 FLORENCE 55.5 284.4 108 246 +1985 11 7 0 27 VALERIE 57.1 304.9 134 78 +1963 2 27 18 26 JOYCE 54.7 44.4 98 150 +1960 2 27 18 19 CHRIS 11.7 136.9 16 772 +1992 8 10 18 25 HELENE 19.2 292.7 157 677 +1962 3 5 12 10 SANDY 15.3 254.7 103 516 +1954 1 5 6 16 ERNESTO 44.3 135.0 77 748 +1994 3 12 12 7 CHRIS 10.7 281.2 49 684 +1995 4 5 6 7 FLORENCE 18.7 153.3 96 746 +1989 5 10 18 1 BERYL 17.5 26.0 130 307 +1997 8 4 18 23 ISAAC 55.1 48.8 102 312 +1977 6 26 6 8 NADINE 49.4 206.5 30 600 +1988 11 23 0 14 BERYL 9.6 283.7 110 839 +1976 8 13 18 23 FLORENCE 20.2 298.9 27 408 +1953 6 20 18 26 SANDY 16.6 258.4 77 181 +1972 8 20 0 19 BERYL 67.6 53.6 32 505 +1974 10 27 0 2 GORDON 31.2 220.8 129 110 +1971 12 11 0 14 OSCAR 64.6 130.3 21 896 +1961 5 8 18 21 PATTY 51.6 4.3 117 479 +1973 5 13 18 12 FLORENCE 57.4 47.8 88 716 +1995 7 18 6 16 NADINE 46.5 120.3 120 475 +1969 1 12 6 16 ISAAC 23.5 162.0 147 758 +1995 6 22 0 22 SANDY 33.1 15.4 121 358 +1998 3 3 12 20 VALERIE 15.2 29.7 152 148 +1981 12 2 12 8 OSCAR 23.9 157.7 86 24 +1989 5 9 12 3 VALERIE 37.5 268.3 59 317 +1970 1 12 6 21 ISAAC 55.4 296.5 43 576 +1996 10 5 0 8 KIRK 7.5 72.0 117 846 +1953 2 5 18 13 BERYL 64.4 98.5 150 392 +1998 11 21 12 26 PATTY 48.7 205.3 141 526 +1982 11 9 12 11 ALBERTO 34.6 56.3 52 854 +1987 5 12 0 21 PATTY 64.8 339.5 29 880 +1973 10 22 6 20 TONY 9.3 233.4 126 827 +1966 10 8 12 23 GORDON 63.4 50.2 116 474 +1984 5 24 18 26 SANDY 24.1 310.8 120 652 +2003 5 26 0 1 MICHAEL 56.2 132.6 152 252 +1952 3 28 18 11 WILLIAM 12.5 172.6 17 415 +1984 1 11 0 1 BERYL 48.4 92.1 93 280 +1979 5 1 6 16 ALBERTO 60.9 186.7 93 590 +1950 5 5 6 14 HELENE 24.0 177.8 145 554 +1997 5 3 12 7 FLORENCE 52.9 249.9 125 686 +2003 9 20 0 2 FLORENCE 27.4 281.5 108 216 +1956 2 21 12 13 ALBERTO 65.4 277.3 61 251 +1962 7 9 0 13 SANDY 30.2 73.4 56 577 +1971 8 10 18 12 CHRIS 21.9 310.1 24 644 +1975 8 3 12 2 ISAAC 53.9 214.7 98 460 +1986 10 13 0 3 HELENE 39.9 232.8 112 463 +1967 1 28 12 25 PATTY 36.1 119.8 11 586 +1988 9 26 0 3 FLORENCE 43.3 76.9 152 227 +1974 2 10 18 21 GORDON 8.5 239.8 93 547 +1968 12 21 6 18 NADINE 41.4 112.8 109 764 +1975 11 12 0 1 BERYL 63.1 352.9 81 480 +1970 1 11 18 3 SANDY 29.8 150.3 39 319 +2001 7 13 0 12 BERYL 28.9 262.3 83 816 +1972 8 19 18 5 TONY 41.2 248.2 149 554 +1991 3 13 6 22 VALERIE 66.7 77.7 100 412 +1991 12 28 12 12 LESLIE 35.8 146.6 139 58 +1997 1 7 0 18 VALERIE 26.5 180.1 42 393 +1983 12 1 18 16 SANDY 11.3 131.1 54 786 +1989 10 6 0 3 RAFAEL 29.4 117.4 77 124 +1967 2 6 6 17 NADINE 38.0 165.8 59 198 +1978 5 25 12 4 GORDON 62.8 291.6 135 451 +1950 8 6 18 20 HELENE 23.7 280.4 11 718 +1993 2 8 0 1 CHRIS 8.8 348.7 130 291 +1982 3 9 18 24 HELENE 49.2 232.6 60 783 +1953 3 8 12 8 VALERIE 56.7 318.9 126 539 +1971 3 23 18 26 ERNESTO 40.9 111.0 154 173 +1965 1 18 18 16 SANDY 61.6 97.2 150 516 +1987 2 25 12 2 ISAAC 36.7 173.9 17 16 +1954 3 24 6 14 FLORENCE 53.1 181.3 143 608 +1993 11 17 6 9 TONY 11.3 63.5 60 500 +2001 4 13 6 11 NADINE 34.9 209.9 26 652 +1968 11 21 12 3 SANDY 41.8 281.9 49 567 +1985 5 24 18 15 LESLIE 56.1 74.2 156 499 +1987 5 2 18 5 NADINE 42.2 81.6 24 225 +1988 8 12 18 11 SANDY 9.4 167.9 69 25 +1955 3 3 0 19 SANDY 63.8 11.9 63 245 +1988 2 20 0 26 GORDON 29.8 57.5 38 870 +1956 9 18 12 4 TONY 16.1 145.6 134 459 +1974 12 27 0 12 GORDON 64.5 265.8 31 511 +1987 7 6 6 16 DEBBY 13.3 229.5 102 230 +1956 6 14 6 12 KIRK 13.1 301.1 147 151 +1995 6 8 0 12 KIRK 50.4 132.5 128 793 +1998 9 8 6 1 MICHAEL 63.5 69.7 15 557 +2000 6 1 0 13 VALERIE 55.0 73.5 125 492 +1976 6 25 6 10 VALERIE 32.0 320.4 70 651 +1964 2 8 18 6 KIRK 14.8 43.1 139 537 +1988 7 21 6 14 KIRK 43.0 104.5 116 369 +1979 12 6 12 22 TONY 12.5 10.1 35 805 +1984 4 5 6 8 TONY 60.4 79.8 10 575 +1985 2 28 6 16 ERNESTO 12.3 152.1 155 393 +1976 10 13 18 22 DEBBY 69.1 290.9 65 161 +2004 11 26 6 6 ISAAC 49.1 135.7 155 458 +1951 8 9 6 8 PATTY 57.5 312.1 78 416 +1964 12 14 0 25 NADINE 69.3 224.1 51 511 +1999 11 15 18 7 KIRK 14.9 221.4 144 84 +1994 9 28 6 8 MICHAEL 62.5 185.8 139 110 +1958 1 11 12 4 TONY 61.0 323.8 86 473 +1982 2 18 12 12 FLORENCE 57.2 204.8 54 473 +1996 2 4 12 21 OSCAR 32.8 72.7 56 66 +1981 12 11 12 27 ERNESTO 59.7 256.4 61 749 +1998 10 16 0 1 JOYCE 27.7 50.1 115 32 +2000 11 16 12 14 ALBERTO 49.4 324.4 88 390 +1996 6 11 12 11 LESLIE 43.3 128.1 161 234 +1957 8 8 12 5 DEBBY 48.5 80.5 87 669 +1978 7 18 12 17 KIRK 29.2 9.0 78 146 +1970 2 16 18 9 GORDON 34.8 85.6 133 275 +1986 7 4 12 28 CHRIS 58.3 189.2 85 827 +1962 2 12 18 18 CHRIS 13.3 73.8 43 337 +1968 3 16 0 15 SANDY 61.4 23.5 140 465 +1954 6 20 0 22 JOYCE 63.1 105.2 137 798 +1983 11 24 0 8 LESLIE 52.9 92.1 47 448 +1980 4 22 12 15 RAFAEL 53.9 261.1 117 58 +1983 3 4 18 18 LESLIE 25.4 163.3 70 656 +1960 3 21 12 5 WILLIAM 28.2 35.9 10 382 +1996 8 2 0 18 BERYL 39.1 150.6 54 539 +1978 8 16 12 9 RAFAEL 57.4 207.0 104 642 +1986 3 16 6 11 HELENE 18.2 316.4 103 747 +2003 10 24 18 28 NADINE 66.6 99.3 139 105 +1972 1 22 0 7 HELENE 51.2 178.0 138 836 +1992 6 11 18 18 FLORENCE 68.6 67.7 63 680 +1954 8 17 0 18 OSCAR 47.4 46.3 107 32 +1981 12 5 12 14 GORDON 30.3 4.7 84 496 +1973 10 3 6 8 TONY 62.5 146.1 74 844 +1968 6 4 6 5 WILLIAM 22.4 204.2 133 24 +1971 9 28 6 9 MICHAEL 46.4 93.9 42 474 +1985 9 22 6 6 HELENE 44.7 174.9 152 130 +1972 9 2 12 26 ERNESTO 68.7 21.0 17 511 +1964 12 17 12 12 ERNESTO 41.4 277.6 51 24 +1957 4 26 6 17 GORDON 33.2 352.7 107 397 +1960 6 7 12 27 WILLIAM 45.8 293.7 105 238 +1956 1 17 0 3 VALERIE 59.9 294.1 111 86 +2003 2 15 12 6 WILLIAM 57.1 311.7 160 48 +1962 2 18 6 9 ISAAC 16.0 265.7 26 87 +1963 4 13 0 10 PATTY 12.9 264.0 59 684 +1995 7 22 12 5 CHRIS 49.6 324.2 89 814 +1957 9 25 12 5 LESLIE 11.6 65.1 61 530 +1978 6 19 12 27 GORDON 16.0 47.8 156 36 +1965 9 15 18 9 ALBERTO 20.6 276.5 102 58 +1955 5 10 6 18 MICHAEL 37.3 25.2 126 707 +1973 9 11 12 9 LESLIE 69.6 158.7 23 136 +1956 12 14 12 6 HELENE 52.7 98.2 85 285 +1992 10 18 18 4 BERYL 57.6 117.8 21 468 +1985 8 14 6 9 DEBBY 47.5 331.0 13 450 +1967 7 24 12 25 FLORENCE 9.5 281.6 160 506 +1951 8 14 12 21 VALERIE 12.5 289.3 135 850 +1963 8 7 0 18 CHRIS 43.9 38.8 80 186 +2001 1 25 12 5 JOYCE 19.4 234.0 155 627 +1982 1 17 6 21 OSCAR 30.9 177.4 129 882 +1959 2 6 0 16 TONY 55.7 244.6 47 86 +1964 11 10 12 5 VALERIE 45.8 233.0 134 187 +1973 6 6 12 11 PATTY 65.2 257.9 52 808 +1982 7 27 18 18 CHRIS 68.6 337.6 106 689 +1953 9 18 6 12 VALERIE 9.4 0.3 85 338 +2000 8 3 18 23 RAFAEL 58.2 152.0 16 234 +1959 5 11 12 13 HELENE 52.0 211.9 11 548 +1970 1 17 0 27 HELENE 60.7 290.0 162 440 +1982 7 24 6 17 SANDY 53.9 18.8 152 90 +1973 12 13 12 22 LESLIE 61.2 123.4 56 779 +1996 2 21 18 7 OSCAR 47.4 190.0 132 122 +2002 11 4 6 8 OSCAR 46.4 202.8 75 611 +1989 3 21 6 9 CHRIS 36.7 137.8 11 154 +1985 12 21 12 26 OSCAR 21.6 190.9 30 714 +1973 3 24 0 23 GORDON 51.3 332.1 112 325 +1975 2 15 6 19 RAFAEL 9.2 6.9 109 636 +1988 10 14 12 14 GORDON 44.4 71.3 35 551 +1972 7 23 12 22 WILLIAM 25.2 283.1 59 241 +2004 9 20 18 17 ERNESTO 30.9 236.0 94 75 +1951 4 15 6 16 RAFAEL 63.6 335.2 59 700 +1979 12 17 0 26 OSCAR 25.2 277.8 92 278 +1985 6 23 18 26 NADINE 30.3 285.5 121 732 +1976 9 10 0 24 VALERIE 26.1 149.0 153 284 +1990 6 11 18 26 ERNESTO 12.0 163.8 141 858 +1952 8 17 12 20 ALBERTO 8.8 155.5 46 498 +1995 10 19 18 2 LESLIE 12.5 209.1 108 204 +1970 8 12 18 19 ALBERTO 9.2 194.3 84 615 +1961 8 21 18 23 ISAAC 51.9 321.1 161 487 +1994 9 15 0 7 OSCAR 60.8 91.1 164 369 +1975 6 22 0 23 BERYL 48.2 290.1 24 844 +1976 5 27 12 4 LESLIE 9.1 238.6 115 622 +1961 7 16 12 19 OSCAR 54.9 95.7 92 422 +1976 8 26 6 8 ALBERTO 25.9 201.9 88 871 +1973 8 5 18 15 VALERIE 54.5 38.7 130 682 +1973 7 2 18 8 OSCAR 23.1 118.8 48 300 +1952 9 21 6 17 RAFAEL 47.3 255.0 44 219 +1982 6 13 6 15 BERYL 65.4 319.7 138 860 +1994 7 27 18 1 TONY 23.7 252.8 134 530 +1986 7 11 12 19 LESLIE 21.0 275.1 147 686 +1966 6 17 6 8 DEBBY 29.6 117.9 125 391 +1962 4 21 0 7 TONY 33.3 157.9 64 704 +2003 7 13 12 8 GORDON 10.3 37.6 164 574 +1955 4 8 0 8 WILLIAM 26.2 75.6 162 862 +2000 9 26 0 6 NADINE 57.9 355.9 157 505 +1967 12 21 6 12 PATTY 46.8 60.6 146 372 +1968 6 2 12 6 ISAAC 26.3 41.4 124 744 +1957 2 17 12 10 ERNESTO 19.4 161.6 21 429 +1995 12 11 6 15 GORDON 12.3 76.2 147 809 +2003 11 10 6 9 PATTY 45.3 195.0 144 668 +1982 2 9 6 18 NADINE 66.6 212.1 29 306 +1975 2 23 0 21 TONY 39.4 59.3 120 755 +1964 1 5 0 2 ERNESTO 45.3 16.3 101 349 +1957 12 28 6 20 BERYL 67.1 159.6 128 207 +1982 5 26 12 20 WILLIAM 25.5 42.9 161 585 +1989 2 27 0 14 PATTY 29.5 167.4 127 446 +1977 3 14 12 5 RAFAEL 8.6 121.4 148 368 +1986 3 14 0 24 BERYL 23.5 278.4 96 8 +2002 1 7 12 25 KIRK 40.1 278.2 79 328 +1980 7 16 18 14 NADINE 66.6 267.9 115 229 +2002 11 1 6 19 OSCAR 68.1 274.6 148 585 +1990 4 9 12 26 JOYCE 64.2 341.1 51 453 +1966 8 11 12 13 GORDON 23.0 279.8 41 371 +1980 6 9 0 25 LESLIE 17.4 251.2 90 92 +1968 7 1 12 9 SANDY 10.0 177.5 118 196 +1967 4 16 6 28 WILLIAM 60.8 320.2 44 764 +1992 2 19 0 7 VALERIE 14.6 1.6 81 473 +1955 3 19 0 20 BERYL 44.8 186.9 80 139 +1977 6 23 12 28 CHRIS 31.3 149.7 71 509 +1954 1 11 6 22 DEBBY 18.2 273.6 99 638 +1985 4 26 12 24 VALERIE 38.8 217.1 149 454 +1958 4 3 6 1 BERYL 49.2 235.1 56 180 +2000 12 24 12 28 ALBERTO 66.7 151.8 78 668 +1999 9 11 18 1 JOYCE 58.8 177.7 109 665 +1991 7 11 12 20 TONY 41.8 125.5 44 298 +1999 9 20 6 23 ERNESTO 14.4 247.1 31 899 +1988 4 19 12 25 GORDON 30.3 143.7 160 150 +1982 12 1 0 10 VALERIE 58.0 81.1 137 1 +1971 8 20 0 19 ERNESTO 62.4 160.9 78 400 +2003 3 4 12 13 ISAAC 28.4 122.5 147 565 +1966 2 6 0 25 PATTY 52.0 64.1 97 640 +1977 9 13 12 11 NADINE 14.1 23.2 122 862 +1980 1 5 18 18 LESLIE 37.1 18.8 102 172 +1996 12 22 12 5 JOYCE 26.1 58.9 28 572 +1957 9 26 0 23 BERYL 19.4 315.1 138 531 +1976 9 10 0 23 HELENE 36.7 70.2 146 407 +1978 1 14 12 16 GORDON 10.0 84.7 92 41 +1999 1 23 12 27 CHRIS 53.8 205.9 62 353 +1963 12 1 0 26 RAFAEL 14.9 355.5 15 484 +1964 6 23 6 6 GORDON 25.0 322.3 129 426 +1955 11 14 18 9 VALERIE 22.2 321.3 21 660 +1964 10 14 18 10 SANDY 63.1 332.9 156 469 +1991 5 16 18 14 ISAAC 51.8 150.5 106 714 +1951 3 9 12 16 LESLIE 38.7 323.2 56 253 +1981 8 22 18 2 KIRK 54.4 126.7 36 689 +1983 1 8 12 4 DEBBY 34.3 214.4 87 285 +1997 11 7 18 18 HELENE 7.5 211.8 88 359 +1986 6 24 6 6 DEBBY 50.4 314.4 26 657 +1979 10 16 0 16 HELENE 9.7 326.5 149 414 +1957 12 23 12 2 JOYCE 27.0 59.3 19 89 +1987 8 12 6 14 RAFAEL 25.8 189.7 127 200 +1971 1 28 0 4 VALERIE 53.3 244.4 21 553 +1984 9 21 18 5 MICHAEL 36.6 13.8 135 456 +1993 11 28 18 21 BERYL 54.3 60.7 153 637 +1956 12 2 0 1 ISAAC 49.0 309.1 115 508 +1996 7 24 6 10 JOYCE 49.3 159.2 153 9 +1952 12 22 0 26 BERYL 23.4 189.4 115 461 +1970 9 21 6 23 FLORENCE 63.4 325.6 126 583 +1953 3 24 0 15 HELENE 15.3 165.5 93 103 +1967 10 25 12 8 RAFAEL 58.5 16.3 129 776 +1957 11 25 0 27 RAFAEL 20.4 297.8 85 165 +1960 9 14 12 4 MICHAEL 19.0 30.7 131 121 +2002 12 11 18 16 BERYL 34.6 278.2 68 568 +1988 3 19 6 21 HELENE 55.6 176.5 32 591 +1973 2 1 0 20 NADINE 42.9 169.7 23 130 +1972 11 25 6 19 SANDY 44.6 168.2 115 577 +1952 12 27 18 20 ALBERTO 51.5 194.6 55 335 +1954 3 28 12 19 SANDY 33.8 113.2 124 715 +1996 8 20 18 12 RAFAEL 22.3 86.3 97 755 +1950 10 21 6 9 ISAAC 57.9 192.0 100 830 +1964 4 12 0 16 DEBBY 13.9 56.9 129 131 +1975 11 7 18 22 CHRIS 24.6 159.8 59 213 +2001 6 18 6 23 ALBERTO 38.4 113.6 46 870 +2004 9 10 18 8 SANDY 57.1 325.1 103 347 +1992 6 23 12 2 LESLIE 33.4 210.0 95 378 +1954 11 24 0 9 MICHAEL 8.9 252.5 158 124 +1962 2 20 0 27 CHRIS 49.9 79.6 64 500 +1992 6 11 18 11 KIRK 27.0 55.2 138 535 +2000 10 27 6 10 WILLIAM 45.2 54.2 63 624 +1954 3 17 0 28 GORDON 23.5 160.7 89 0 +2001 5 24 12 5 KIRK 48.4 224.8 89 697 +1996 8 9 12 4 OSCAR 36.7 22.4 91 266 +1981 2 26 12 1 JOYCE 50.5 297.1 103 300 +1958 4 18 6 16 RAFAEL 20.7 98.1 77 705 +1988 8 22 6 11 PATTY 33.6 247.0 128 868 +1973 8 24 18 15 SANDY 56.0 337.0 144 392 +2000 3 20 6 1 OSCAR 34.1 211.6 141 609 +1960 4 12 12 28 CHRIS 9.9 193.1 39 481 +1980 1 25 0 17 WILLIAM 21.0 118.9 152 715 +1953 7 3 12 15 ISAAC 12.4 197.8 66 568 +1969 5 23 18 6 MICHAEL 43.1 56.0 151 185 +1976 1 9 0 12 DEBBY 26.6 335.4 84 593 +1984 10 22 0 21 BERYL 46.7 203.3 100 589 +1979 8 18 18 1 FLORENCE 39.9 174.0 83 342 +1997 2 25 6 3 CHRIS 16.2 24.3 151 59 +1998 2 28 18 4 JOYCE 41.1 17.4 160 438 +1977 2 9 12 2 RAFAEL 62.8 49.3 133 765 +1950 3 27 0 11 ERNESTO 48.5 174.8 58 663 +1978 10 14 12 19 HELENE 24.4 269.4 59 769 +1966 9 5 6 5 ERNESTO 48.0 88.4 99 653 +1977 7 20 18 26 FLORENCE 57.8 69.5 126 203 +1963 8 6 12 16 VALERIE 20.2 31.8 105 174 +1993 9 25 6 5 JOYCE 24.1 274.1 84 95 +1978 6 13 12 26 ERNESTO 37.5 17.3 36 11 +1993 5 17 12 8 SANDY 26.1 357.8 163 660 +1973 7 8 12 21 NADINE 36.0 9.3 109 184 +2004 11 24 6 22 KIRK 25.3 283.9 136 641 +1995 6 16 18 11 CHRIS 10.5 50.2 119 354 +1999 12 4 0 26 MICHAEL 56.0 65.9 10 19 +1987 10 18 12 11 GORDON 69.8 8.7 139 154 +1953 10 2 0 5 ERNESTO 66.8 86.3 13 479 +1974 2 15 12 25 ALBERTO 67.8 113.0 61 181 +1984 3 12 6 17 PATTY 25.6 214.5 16 570 +1979 5 16 12 19 NADINE 37.9 261.8 55 509 +1964 4 23 6 11 KIRK 26.2 163.6 83 224 +1986 6 3 6 23 PATTY 9.0 83.5 34 351 +1998 4 15 18 7 RAFAEL 61.4 353.1 56 781 +1961 2 25 0 24 TONY 37.0 86.1 37 713 +1954 1 5 6 15 VALERIE 19.3 166.8 94 255 +1994 10 20 12 6 TONY 11.2 6.8 150 766 +1996 8 10 0 19 MICHAEL 18.2 79.3 96 664 +1998 9 26 18 9 ERNESTO 7.6 223.5 117 744 +1996 10 27 6 6 SANDY 51.8 43.8 151 85 +1990 1 20 18 6 ALBERTO 48.6 39.2 139 219 +1954 5 16 6 3 SANDY 53.1 323.0 44 380 +1985 11 28 18 7 BERYL 28.8 170.8 60 291 +1974 8 23 12 1 HELENE 36.7 73.4 89 495 +1975 5 9 0 12 MICHAEL 42.5 143.5 27 67 +1959 3 25 18 19 RAFAEL 57.3 237.1 19 351 +1972 2 10 18 3 RAFAEL 64.7 210.9 53 47 +1950 6 3 18 18 NADINE 26.3 65.3 94 459 +1961 1 13 12 22 JOYCE 41.0 287.6 67 436 +1982 3 21 0 18 JOYCE 33.6 299.9 67 612 +1975 11 23 18 22 NADINE 62.7 287.2 126 26 +1956 10 7 0 1 BERYL 26.8 138.0 146 116 +2000 10 1 6 8 NADINE 23.3 52.8 110 0 +1996 7 17 6 22 PATTY 49.6 282.4 150 413 +1956 10 2 12 15 CHRIS 12.1 43.3 72 642 +1993 8 8 6 20 HELENE 48.7 108.8 58 5 +2003 10 6 12 24 JOYCE 49.8 305.2 160 497 +1982 12 6 12 23 TONY 51.1 293.6 65 450 +1997 9 3 18 3 PATTY 15.7 231.7 77 9 +1978 1 4 18 26 MICHAEL 60.5 151.6 131 389 +1996 4 11 0 28 FLORENCE 13.0 304.5 91 86 +2002 6 3 12 4 BERYL 22.9 288.4 84 253 +1960 3 6 12 21 ERNESTO 19.1 77.7 120 30 +1991 12 9 12 13 FLORENCE 24.8 340.0 54 894 +1970 8 27 12 23 NADINE 66.7 217.5 143 695 +1993 7 21 12 20 HELENE 56.3 346.6 92 269 +1974 12 19 12 3 DEBBY 28.4 346.3 135 684 +1976 6 19 12 6 FLORENCE 59.4 168.0 91 847 +1992 1 13 12 26 HELENE 61.2 169.9 106 433 +2001 4 10 12 18 CHRIS 66.2 49.0 148 5 +1986 4 18 12 9 BERYL 16.3 206.2 60 278 +1958 1 3 6 15 HELENE 44.7 46.0 39 861 +1995 5 7 12 18 LESLIE 14.8 188.5 18 732 +1951 5 20 6 28 NADINE 33.2 68.2 41 175 +1975 9 15 18 16 RAFAEL 13.4 60.5 76 273 +1986 7 6 18 15 ERNESTO 43.3 296.7 114 299 +1989 9 17 18 3 GORDON 7.4 232.2 57 309 +1975 2 15 18 8 TONY 9.7 201.9 103 806 +1990 10 2 18 12 GORDON 42.9 293.3 137 589 +2003 8 4 0 24 RAFAEL 17.2 14.8 164 528 +1959 4 3 6 22 VALERIE 29.6 85.1 94 312 +1986 10 19 12 21 NADINE 48.3 182.2 107 693 +1991 8 5 12 8 GORDON 7.6 179.9 100 458 +1983 6 11 12 22 DEBBY 9.7 355.8 151 399 +1973 3 10 18 25 LESLIE 19.3 239.1 43 890 +1966 4 28 18 9 VALERIE 33.3 142.7 125 660 +1997 11 17 6 28 LESLIE 47.6 207.1 150 17 +1956 4 21 0 12 NADINE 23.9 70.5 47 709 +1994 4 3 12 13 KIRK 8.1 68.1 77 275 +1998 12 3 18 26 DEBBY 13.7 256.9 85 391 +1982 11 26 12 14 FLORENCE 18.6 74.2 12 622 +1970 11 13 18 18 DEBBY 29.7 107.6 145 716 +1992 7 16 12 4 ISAAC 40.9 303.0 75 870 +1950 10 28 0 8 WILLIAM 68.9 181.4 95 26 +1959 9 14 12 26 LESLIE 21.6 291.5 153 0 +1955 12 2 12 11 RAFAEL 62.4 249.1 128 780 +1965 4 7 0 20 ALBERTO 53.5 11.3 100 190 +1960 11 7 0 21 CHRIS 44.6 60.3 95 436 +1976 10 25 12 10 RAFAEL 55.7 212.9 23 459 +1996 9 22 12 20 ERNESTO 29.5 102.4 57 736 +1988 3 15 0 17 ALBERTO 37.5 95.1 44 860 +1986 10 22 18 26 HELENE 50.7 153.4 87 138 +1992 10 1 6 12 OSCAR 57.8 241.3 58 149 +1957 4 15 6 1 ERNESTO 23.9 182.2 60 559 +1995 9 3 6 17 TONY 43.5 103.1 107 659 +1968 2 5 18 2 BERYL 51.3 241.1 30 242 +1968 7 18 6 22 HELENE 15.4 271.2 128 280 +1962 4 7 6 28 MICHAEL 48.8 55.8 11 376 +1959 11 21 0 13 CHRIS 67.0 4.1 67 831 +1952 3 11 12 2 SANDY 66.0 260.4 23 801 +1994 9 8 0 13 MICHAEL 21.1 275.3 43 219 +1988 7 24 0 15 TONY 24.9 291.0 13 685 +1999 5 17 12 9 FLORENCE 54.6 316.5 100 208 +2000 4 25 18 17 JOYCE 62.1 122.2 108 472 +1977 10 6 18 4 DEBBY 36.6 112.4 103 756 +2003 3 3 0 3 BERYL 35.9 20.2 29 29 +1971 10 24 18 16 GORDON 52.1 196.7 15 446 +1982 3 19 0 19 LESLIE 38.2 331.6 132 625 +1988 3 28 0 24 ALBERTO 55.1 28.3 128 550 +1950 11 22 0 3 JOYCE 7.8 261.1 160 791 +1988 4 18 18 3 WILLIAM 48.6 93.4 47 596 +1988 9 25 0 5 RAFAEL 12.5 272.3 56 763 +1955 5 10 18 17 ERNESTO 45.8 235.2 105 429 +1972 1 20 18 5 FLORENCE 19.5 309.9 164 102 +1965 9 1 18 8 HELENE 7.5 338.1 80 494 +1955 3 3 12 14 VALERIE 34.9 25.9 154 379 +1989 7 2 6 3 CHRIS 15.8 29.5 102 794 +1974 3 12 18 6 SANDY 54.7 1.4 55 238 +1985 8 10 6 22 BERYL 26.1 332.2 113 497 +1958 11 3 6 23 OSCAR 55.9 108.6 89 269 +1992 1 19 0 25 DEBBY 7.7 239.5 101 546 +2003 10 21 18 25 GORDON 67.9 69.3 78 491 +1993 4 20 0 12 RAFAEL 57.5 156.8 87 307 +1952 10 27 18 15 ALBERTO 31.1 320.0 141 596 +1952 6 11 12 28 BERYL 43.3 187.9 91 128 +1989 10 23 6 6 MICHAEL 64.4 0.2 23 88 +1954 12 19 0 2 DEBBY 19.0 267.1 41 169 +1961 6 21 6 26 WILLIAM 35.0 75.8 157 42 +1969 6 2 6 12 DEBBY 58.8 126.5 105 863 +1966 9 14 6 4 ERNESTO 59.0 273.0 150 531 +1996 6 8 0 5 GORDON 61.4 49.1 134 184 +1968 7 24 0 11 ALBERTO 63.9 160.5 94 687 +1980 7 15 18 10 ALBERTO 37.8 265.2 96 47 +1982 11 7 12 18 NADINE 65.9 148.4 139 524 +1977 1 12 6 22 LESLIE 22.4 35.6 107 83 +1994 4 4 18 17 VALERIE 7.9 156.5 160 408 +1993 6 8 12 20 KIRK 57.6 3.7 49 880 +1996 10 24 12 20 ALBERTO 18.8 36.9 10 592 +1974 9 7 18 13 PATTY 45.1 37.8 111 346 +1985 2 19 6 15 GORDON 15.4 68.5 116 199 +1973 7 11 6 7 RAFAEL 14.9 154.8 161 284 +1998 6 6 0 20 FLORENCE 35.7 104.9 133 227 +1973 10 15 18 19 ISAAC 68.5 111.8 35 591 +1982 12 15 0 16 SANDY 19.8 13.8 41 221 +1991 4 15 12 9 OSCAR 48.6 180.7 24 816 +1963 2 5 18 11 ISAAC 29.2 126.8 25 63 +1969 1 16 18 3 GORDON 27.1 197.0 116 688 +1950 11 24 12 26 MICHAEL 47.7 234.6 43 566 +1994 6 9 0 3 LESLIE 25.9 107.2 13 481 +2000 7 10 18 10 KIRK 62.7 283.0 124 602 +1978 7 15 6 22 HELENE 37.8 33.5 96 67 +1971 9 12 12 20 CHRIS 68.3 14.8 68 401 +1964 5 27 0 23 JOYCE 62.4 300.4 83 825 +1961 12 16 18 12 HELENE 22.4 79.0 126 424 +1994 9 3 18 18 FLORENCE 60.2 83.4 64 13 +1968 5 10 18 6 ALBERTO 23.1 41.3 46 48 +1994 5 7 6 15 GORDON 11.5 89.3 73 640 +1983 9 22 6 19 MICHAEL 28.1 285.0 99 269 +1959 7 1 12 11 OSCAR 60.4 222.6 152 336 +1984 10 10 12 2 OSCAR 62.3 75.1 52 143 +1998 5 26 12 17 TONY 27.2 16.4 110 758 +1979 3 17 0 28 WILLIAM 16.8 192.5 162 527 +1959 7 11 6 15 ALBERTO 43.8 197.6 40 631 +2002 12 6 18 12 RAFAEL 28.1 253.5 11 638 +1970 6 9 0 28 LESLIE 41.0 75.2 22 497 +1962 9 20 6 22 KIRK 39.3 334.5 62 277 +1960 7 19 12 21 TONY 24.1 177.0 84 870 +1974 11 2 0 17 KIRK 21.7 286.1 49 774 +1999 4 16 12 22 CHRIS 17.5 185.1 103 309 +1980 7 5 0 24 GORDON 64.5 59.2 106 334 +1952 8 9 0 1 DEBBY 19.0 230.8 129 391 +1964 3 16 12 13 BERYL 25.2 138.4 126 633 +1972 4 7 0 24 DEBBY 7.2 312.8 77 98 +1990 3 27 0 8 JOYCE 27.5 131.7 70 619 +1976 4 13 6 4 KIRK 69.8 97.1 142 392 +1967 6 24 12 8 BERYL 42.5 60.1 22 120 +1990 5 21 6 20 WILLIAM 46.8 294.9 28 25 +1995 7 16 0 24 OSCAR 64.4 169.3 139 230 +1969 2 20 12 28 FLORENCE 39.2 41.0 101 568 +1978 9 7 0 27 TONY 12.9 308.3 91 839 +1970 10 24 12 13 ALBERTO 20.8 124.8 88 237 +1997 10 12 12 21 VALERIE 50.2 109.6 106 393 +1985 9 15 6 23 DEBBY 40.8 182.9 136 544 +1965 10 15 12 10 VALERIE 63.7 331.0 90 579 +2003 3 6 12 27 DEBBY 62.8 18.8 84 786 +1958 3 8 12 19 DEBBY 27.3 26.8 57 98 +1964 2 9 6 10 NADINE 13.1 191.4 114 694 +1998 2 3 0 24 KIRK 7.9 46.3 12 356 +1977 2 12 12 2 TONY 67.0 216.3 33 635 +1962 9 12 6 10 SANDY 20.9 51.2 60 204 +1993 6 10 12 20 GORDON 10.0 200.6 81 198 +1960 11 22 12 12 TONY 45.1 241.0 123 896 +1985 1 15 12 22 VALERIE 10.0 95.1 138 532 +2003 4 26 0 27 JOYCE 27.0 242.9 149 765 +1960 10 26 0 6 MICHAEL 11.7 219.1 161 129 +1951 1 12 0 1 JOYCE 34.0 193.1 148 605 +1958 2 11 18 10 ALBERTO 51.6 167.2 74 892 +1991 11 12 0 13 DEBBY 46.0 103.0 97 568 +1986 4 4 12 14 CHRIS 61.2 186.2 128 381 +2001 2 21 18 23 FLORENCE 43.5 55.7 94 237 +1951 9 1 12 25 CHRIS 7.8 5.7 125 316 +1993 2 27 6 8 OSCAR 50.5 100.8 146 338 +1952 7 10 12 5 TONY 7.7 48.3 120 880 +1952 1 1 18 27 JOYCE 54.6 195.2 23 203 +1986 12 19 0 7 GORDON 17.9 47.7 36 43 +2000 11 3 6 20 ALBERTO 38.8 280.7 44 822 +1970 6 26 18 11 TONY 38.9 117.9 15 491 +1971 5 24 0 25 ALBERTO 38.7 32.4 13 643 +1985 8 3 12 2 ISAAC 17.1 335.2 97 387 +1971 6 14 0 7 WILLIAM 32.9 312.6 112 364 +1978 5 18 6 27 ERNESTO 70.0 115.7 144 52 +1984 9 13 6 26 SANDY 28.0 185.9 117 803 +1982 5 24 12 28 NADINE 24.6 135.6 89 9 +1971 7 3 12 23 ALBERTO 56.9 180.1 133 355 +1958 9 17 0 8 DEBBY 65.6 52.1 12 811 +2001 6 4 6 26 NADINE 14.3 17.5 119 381 +1985 3 28 6 10 RAFAEL 48.0 158.0 161 142 +1980 9 8 6 4 ISAAC 19.3 318.4 50 681 +1998 6 11 6 27 BERYL 38.2 251.0 153 633 +1950 3 14 0 28 MICHAEL 44.4 269.0 148 681 +1954 3 12 6 20 CHRIS 46.2 10.4 112 724 +1995 1 2 18 27 PATTY 15.3 302.1 48 513 +1990 7 10 0 18 ALBERTO 59.5 15.2 138 564 +1951 6 25 6 15 LESLIE 11.6 212.2 113 428 +1987 5 16 0 26 ISAAC 32.9 215.9 42 662 +1967 3 25 12 16 OSCAR 21.3 140.6 59 855 +1966 5 13 12 12 WILLIAM 46.6 85.8 134 291 +1962 1 8 6 3 HELENE 49.9 354.3 11 569 +1976 8 4 12 27 WILLIAM 9.3 47.4 39 490 +1996 12 1 0 2 PATTY 56.1 229.7 138 721 +1982 2 6 0 1 SANDY 35.1 56.3 124 20 +1975 11 15 12 25 HELENE 41.6 69.0 144 144 +1966 8 18 18 26 LESLIE 35.3 95.0 139 640 +1978 2 27 12 7 WILLIAM 59.7 44.7 123 520 +1987 2 4 18 11 JOYCE 9.3 80.2 41 371 +1997 8 4 18 2 WILLIAM 7.9 247.8 154 329 +1992 4 16 0 17 PATTY 19.9 62.1 61 222 +1960 4 2 6 17 HELENE 69.3 149.7 25 409 +2001 3 28 12 21 HELENE 52.8 140.2 94 858 +1989 10 16 6 15 ERNESTO 16.0 332.9 18 830 +1997 1 11 6 9 ALBERTO 48.3 85.9 128 215 +1986 5 28 18 15 CHRIS 7.3 335.8 109 831 +1958 6 6 12 4 ALBERTO 16.2 96.4 131 580 +2001 12 15 18 17 RAFAEL 8.2 17.5 20 617 +1994 6 22 18 7 CHRIS 35.8 258.9 142 275 +2001 9 17 0 11 TONY 16.3 43.6 115 449 +1983 4 11 0 10 LESLIE 46.8 84.6 103 826 +1977 11 4 18 7 ERNESTO 61.2 235.6 144 761 +1987 7 16 6 1 BERYL 23.1 324.1 84 381 +1994 1 6 18 9 BERYL 34.9 186.9 128 172 +1951 1 19 18 3 NADINE 48.2 64.2 114 274 +1988 3 1 0 4 OSCAR 52.3 119.5 76 203 +1995 8 7 6 21 JOYCE 65.0 41.1 160 222 +1965 1 9 6 17 BERYL 59.3 278.2 101 105 +1971 8 4 12 15 LESLIE 36.3 259.9 72 81 +1966 8 23 18 3 TONY 24.6 167.3 134 449 +1971 10 11 18 18 BERYL 49.9 86.4 154 484 +1974 6 18 12 14 JOYCE 41.4 218.1 73 168 +1953 1 2 6 23 ISAAC 52.2 356.2 60 338 +2004 4 15 6 24 HELENE 38.3 199.0 37 31 +1971 12 13 18 10 HELENE 26.8 6.2 159 346 +1961 1 6 0 6 OSCAR 62.7 153.0 162 771 +1964 8 25 0 23 JOYCE 24.6 89.6 138 493 +1968 11 11 18 24 RAFAEL 25.2 30.1 24 209 +1978 9 3 18 14 JOYCE 67.2 133.5 71 781 +1983 4 6 18 28 NADINE 66.2 178.2 11 885 +1959 9 5 12 8 TONY 19.0 99.5 68 700 +1974 2 4 6 17 CHRIS 43.3 304.3 129 229 +1954 4 1 12 6 ERNESTO 43.2 27.9 46 694 +1954 6 1 6 8 ALBERTO 12.7 209.4 127 316 +1991 7 17 6 11 RAFAEL 18.0 338.7 95 835 +1967 9 11 6 25 CHRIS 41.9 207.6 68 736 +1968 3 3 6 19 ALBERTO 43.1 101.4 145 801 +1965 6 24 12 9 NADINE 62.0 232.9 145 348 +1987 3 4 0 26 SANDY 10.6 22.4 92 492 +1988 7 11 12 13 VALERIE 40.3 155.4 19 849 +1989 9 16 12 17 LESLIE 65.1 178.8 61 418 +1988 12 10 0 27 LESLIE 14.9 75.3 47 749 +1990 12 18 0 3 HELENE 18.1 257.5 20 657 +1960 1 25 0 15 DEBBY 12.5 16.3 16 836 +1977 2 3 18 24 CHRIS 36.4 257.2 22 835 +1977 10 4 18 7 RAFAEL 26.8 176.0 129 640 +1974 6 2 12 26 BERYL 16.1 292.6 64 298 +1961 5 25 0 19 TONY 48.9 74.7 112 595 +1983 1 14 12 14 BERYL 66.0 226.9 95 619 +1994 2 16 0 26 PATTY 30.4 307.7 131 41 +1987 12 26 12 11 VALERIE 35.4 14.1 134 31 +1959 1 16 6 13 WILLIAM 56.7 29.8 25 564 +1958 1 13 12 19 PATTY 41.8 42.2 63 330 +1987 1 18 0 4 ERNESTO 47.9 161.2 99 408 +1985 2 19 0 11 KIRK 22.6 216.4 108 170 +1951 8 4 6 13 NADINE 12.1 48.6 162 578 +1997 8 18 0 23 BERYL 46.3 263.6 76 861 +1973 8 15 12 1 HELENE 27.8 170.5 113 798 +1997 12 26 0 26 HELENE 28.4 34.0 18 206 +1981 2 18 18 16 RAFAEL 18.2 243.5 18 888 +1974 1 7 18 16 MICHAEL 42.1 175.2 10 666 +1974 8 20 0 27 GORDON 10.4 152.8 121 242 +1959 7 8 18 10 ALBERTO 22.3 59.3 40 302 +1992 9 12 18 9 NADINE 49.1 269.2 158 145 +1952 12 13 0 28 ALBERTO 43.9 276.5 155 26 +1998 1 26 0 10 CHRIS 61.9 190.3 131 744 +1965 10 9 12 3 ERNESTO 50.8 71.5 118 244 +1970 4 7 12 18 SANDY 37.2 112.5 74 870 +1958 9 23 0 27 VALERIE 54.7 322.8 83 600 +1958 3 5 18 11 NADINE 15.0 228.1 38 717 +1957 2 24 12 7 PATTY 18.0 293.7 84 420 +2004 9 2 12 18 OSCAR 13.6 342.2 24 52 +1996 11 1 0 25 HELENE 45.8 5.6 158 653 +1965 2 21 18 5 GORDON 10.2 346.1 151 537 +1972 6 9 12 14 ERNESTO 9.6 184.8 125 862 +1997 4 18 18 25 PATTY 9.3 235.2 141 763 +1962 12 24 6 24 SANDY 31.1 55.7 159 248 +1961 2 7 0 25 ERNESTO 65.5 113.9 85 539 +1958 2 6 6 7 RAFAEL 25.0 221.8 23 492 +1975 5 21 12 16 ALBERTO 56.5 207.0 89 75 +1952 6 8 0 10 SANDY 37.0 224.2 126 627 +1977 2 28 18 11 CHRIS 45.2 72.7 42 583 +1990 6 2 0 10 FLORENCE 19.3 90.2 89 749 +1966 2 21 18 7 ALBERTO 22.6 218.0 135 232 +1957 7 13 12 3 BERYL 39.2 98.9 45 545 +1961 8 16 6 7 GORDON 45.6 261.5 118 441 +1978 3 6 6 24 KIRK 16.5 162.2 49 628 +1959 9 1 0 19 TONY 45.9 111.1 121 254 +1987 1 8 12 19 DEBBY 33.9 129.2 30 880 +1978 8 17 12 14 GORDON 62.8 199.7 42 697 +1991 1 14 12 6 VALERIE 7.4 141.5 163 61 +1988 2 4 18 10 ISAAC 45.1 15.7 94 514 +1950 12 24 12 19 LESLIE 22.7 3.8 26 75 +1976 9 24 18 24 TONY 15.9 255.9 101 657 +1996 6 11 12 14 JOYCE 38.3 219.1 48 75 +1968 6 1 12 11 CHRIS 17.4 326.8 32 363 +1993 11 18 12 14 RAFAEL 46.2 297.0 109 261 +1999 1 18 12 17 NADINE 41.1 338.9 155 47 +1967 10 6 12 11 PATTY 31.6 173.5 72 486 +1987 8 2 12 2 BERYL 33.6 272.3 21 314 +1954 6 16 18 8 KIRK 67.4 215.1 52 853 +1951 9 3 0 20 MICHAEL 9.9 263.7 96 738 +1958 7 16 18 23 LESLIE 9.5 260.1 94 855 +1961 4 5 12 24 WILLIAM 49.5 233.7 41 443 +1974 2 25 6 17 ERNESTO 24.6 244.7 163 129 +1958 6 11 6 18 ALBERTO 40.3 115.7 88 74 +1989 10 10 18 24 JOYCE 36.0 268.6 53 617 +1950 8 3 6 15 PATTY 54.2 86.5 142 222 +1991 2 23 18 7 TONY 8.2 98.0 105 545 +1967 11 17 12 6 ERNESTO 22.0 166.6 58 78 +1953 3 3 6 24 ERNESTO 39.2 276.2 160 246 +1963 8 13 18 15 KIRK 65.2 59.7 27 340 +1953 11 28 12 25 RAFAEL 31.6 132.1 11 485 +2003 11 5 12 24 PATTY 67.6 16.4 33 848 +1983 1 5 0 5 BERYL 56.0 14.3 134 372 +1963 1 6 12 12 CHRIS 63.7 214.5 108 721 +1977 12 19 0 16 WILLIAM 39.6 148.9 94 311 +2004 9 10 18 9 PATTY 50.7 169.9 117 304 +1963 10 2 18 10 WILLIAM 30.6 54.1 127 298 +1988 5 23 0 2 VALERIE 38.3 347.7 18 447 +1956 4 12 18 18 OSCAR 35.5 175.1 83 478 +1971 8 3 12 27 TONY 49.3 70.7 12 719 +1998 9 24 6 10 JOYCE 7.2 41.0 145 319 +1970 2 19 12 14 VALERIE 14.2 245.2 82 221 +1959 1 11 18 28 DEBBY 24.2 253.8 117 620 +2004 5 28 18 5 VALERIE 55.1 345.8 66 707 +1985 8 21 0 2 VALERIE 24.8 341.1 40 736 +1984 12 15 12 6 JOYCE 69.1 55.9 91 585 +1993 6 18 18 15 ERNESTO 29.3 27.1 129 644 +1962 9 11 0 21 PATTY 18.0 41.8 25 432 +1981 12 8 6 1 HELENE 67.8 65.0 129 620 +1985 9 28 12 4 LESLIE 63.6 338.3 82 34 +2003 9 6 0 20 RAFAEL 13.6 266.1 64 669 +1978 3 8 12 15 NADINE 57.2 58.8 102 617 +1997 12 1 12 17 RAFAEL 48.9 292.8 49 512 +1971 11 24 18 6 JOYCE 44.3 202.7 141 860 +2004 12 19 18 1 HELENE 26.2 211.6 131 85 +1968 11 16 12 1 TONY 34.5 94.2 35 712 +1957 8 11 0 24 BERYL 37.3 335.5 44 746 +1988 6 23 6 11 NADINE 57.4 188.3 95 142 +1973 9 14 6 2 OSCAR 24.1 287.9 141 674 +1991 8 19 18 15 WILLIAM 49.4 217.6 71 258 +1999 4 11 6 10 WILLIAM 45.5 67.0 108 93 +1971 2 21 0 1 LESLIE 52.9 235.4 126 201 +1961 7 24 18 18 ISAAC 19.0 286.2 147 135 +1979 10 16 18 28 WILLIAM 57.6 131.5 40 317 +1961 4 20 18 5 RAFAEL 13.1 208.1 102 11 +1963 5 16 12 16 JOYCE 62.4 62.5 20 473 +2004 6 15 6 3 CHRIS 40.8 94.8 161 151 +1981 4 28 6 8 KIRK 54.8 240.4 51 121 +1953 3 28 18 15 DEBBY 22.8 289.6 23 52 +1955 11 16 0 25 GORDON 54.2 262.1 33 867 +1950 1 19 12 1 KIRK 8.0 332.0 27 123 +1999 6 10 0 25 VALERIE 25.9 71.2 75 403 +1975 3 6 6 2 CHRIS 12.5 237.6 124 165 +1968 8 3 6 27 DEBBY 34.7 312.3 157 36 +1998 5 20 12 4 MICHAEL 61.3 70.9 29 213 +1954 6 24 0 21 LESLIE 23.8 282.8 52 644 +1969 12 26 12 2 OSCAR 52.0 222.9 24 85 +1952 8 14 0 2 GORDON 64.8 204.5 28 612 +1950 4 18 12 19 LESLIE 32.7 220.9 130 231 +1979 6 28 18 27 WILLIAM 31.0 214.1 23 314 +1950 12 12 0 13 FLORENCE 59.5 127.8 134 394 +1980 1 19 18 12 OSCAR 52.7 220.7 97 680 +1985 5 11 0 7 ISAAC 38.3 332.6 27 176 +1976 4 8 6 22 NADINE 63.6 82.0 101 392 +1950 5 10 6 8 MICHAEL 42.1 174.3 28 554 +1994 3 18 0 8 JOYCE 38.4 189.0 150 512 +1959 7 3 12 21 SANDY 16.9 41.0 141 571 +1975 3 15 0 23 SANDY 22.7 294.7 25 539 +1959 12 14 18 8 LESLIE 16.0 146.3 34 383 +1957 10 27 18 13 ERNESTO 47.0 237.8 139 491 +1990 5 14 18 9 ISAAC 22.2 104.1 84 687 +1970 12 13 12 19 MICHAEL 46.4 37.3 163 348 +1977 11 5 18 28 RAFAEL 58.2 181.8 132 693 +1990 8 6 0 20 SANDY 59.3 354.8 12 186 +1996 2 20 12 22 PATTY 16.1 352.8 76 323 +1965 2 26 6 18 CHRIS 10.9 108.9 117 733 +1972 7 4 12 15 BERYL 59.8 159.1 128 262 +1999 2 23 12 8 CHRIS 50.2 224.9 99 48 +2001 1 11 0 5 KIRK 48.1 227.4 127 301 +1985 1 7 12 25 LESLIE 38.5 10.6 164 422 +2001 11 26 12 19 BERYL 48.2 114.2 36 303 +1963 2 22 18 26 CHRIS 42.6 5.4 21 873 +1952 1 4 18 12 BERYL 22.7 228.3 29 52 +1996 11 17 0 15 RAFAEL 30.4 269.4 73 811 +1984 8 14 12 4 WILLIAM 58.3 283.6 116 344 +1997 6 24 12 5 FLORENCE 21.9 44.1 51 108 +1986 5 4 6 1 ALBERTO 26.7 199.4 154 852 +2000 9 5 18 4 SANDY 60.5 95.0 115 753 +1958 8 15 0 19 NADINE 13.6 160.8 12 249 +1967 8 3 0 1 MICHAEL 52.7 282.6 116 78 +1995 2 26 12 5 RAFAEL 33.9 302.0 72 416 +2002 1 3 12 14 ERNESTO 59.4 204.3 39 604 +1963 9 19 12 14 OSCAR 48.9 91.1 99 369 +1992 4 9 6 1 NADINE 15.0 130.5 111 537 +2000 8 2 0 13 RAFAEL 57.7 175.0 78 697 +1978 4 24 12 14 BERYL 67.1 198.6 113 883 +1988 11 6 6 26 TONY 60.4 260.0 39 228 +1967 10 14 0 8 WILLIAM 50.0 13.1 70 808 +1968 4 2 18 9 WILLIAM 59.5 51.3 146 862 +1969 1 5 0 20 VALERIE 67.0 15.8 118 2 +1960 3 20 6 12 BERYL 42.0 68.9 11 470 +1952 7 28 12 7 ISAAC 37.4 40.8 146 888 +1971 9 24 6 3 LESLIE 57.0 213.7 158 693 +1969 12 18 6 11 WILLIAM 59.7 284.9 54 178 +1982 8 9 18 9 RAFAEL 52.8 203.7 72 845 +1997 5 18 0 13 ISAAC 52.1 18.6 104 637 +1951 12 22 0 2 LESLIE 23.2 229.0 139 583 +2001 8 23 6 27 MICHAEL 50.0 247.3 107 851 +1978 7 23 12 21 VALERIE 11.3 34.0 101 106 +1973 7 3 12 10 JOYCE 39.3 50.9 119 304 +1968 4 18 18 9 ERNESTO 13.5 196.7 139 821 +2002 9 22 12 13 ISAAC 28.9 132.1 77 125 +1959 9 13 18 14 MICHAEL 39.8 312.2 81 680 +1954 7 25 0 3 JOYCE 50.5 158.1 29 230 +1988 8 23 6 15 ALBERTO 28.5 187.3 78 538 +1969 4 8 6 2 TONY 33.6 84.4 144 271 +1963 12 28 6 19 MICHAEL 13.9 82.3 68 552 +1952 4 13 0 4 RAFAEL 22.6 141.2 30 712 +2001 3 18 6 24 GORDON 50.2 356.1 88 312 +1994 8 12 0 22 DEBBY 47.6 320.0 13 726 +1960 4 14 0 2 JOYCE 10.7 280.2 40 139 +1993 8 11 18 11 TONY 26.4 36.8 88 25 +1957 6 6 6 27 JOYCE 53.4 147.5 103 67 +1978 5 6 12 8 OSCAR 19.3 201.2 127 125 +1992 8 15 12 11 LESLIE 66.7 151.7 111 797 +1991 1 13 0 9 MICHAEL 41.1 300.4 101 411 +1983 8 1 18 12 ERNESTO 48.1 111.6 87 177 +1982 3 18 6 24 PATTY 52.8 330.4 95 559 +1962 11 7 18 8 NADINE 67.1 248.0 108 714 +1996 5 12 12 20 DEBBY 63.2 175.8 135 744 +1973 5 12 12 28 JOYCE 33.3 194.8 87 251 +1998 9 4 12 24 KIRK 38.7 88.5 95 461 +1960 6 10 18 3 VALERIE 59.4 139.3 117 466 +1961 3 25 6 19 BERYL 45.0 128.1 96 301 +1985 8 5 0 12 FLORENCE 30.9 306.5 48 452 +1989 10 20 0 17 GORDON 43.4 243.0 151 792 +1981 9 14 12 9 NADINE 32.9 168.9 63 107 +1962 4 22 12 14 RAFAEL 55.6 212.9 27 825 +1979 7 27 0 17 BERYL 42.5 313.8 117 101 +1952 11 20 18 18 JOYCE 17.1 44.3 158 530 +1960 8 10 18 14 FLORENCE 18.5 272.8 43 455 +1978 10 16 12 20 ISAAC 49.3 188.7 149 729 +1996 9 20 6 17 TONY 22.9 183.4 112 453 +1984 8 21 18 11 LESLIE 51.2 47.0 150 73 +1961 5 12 18 16 BERYL 59.2 49.2 68 109 +1984 4 25 0 24 LESLIE 23.9 53.7 106 555 +1967 6 7 18 19 OSCAR 15.9 163.0 129 765 +1982 3 22 12 12 JOYCE 26.2 343.5 137 300 +2001 1 21 18 11 RAFAEL 54.2 196.1 69 639 +1950 9 14 6 5 OSCAR 49.3 131.6 97 524 +1988 7 8 12 6 ALBERTO 10.0 101.1 130 365 +1963 1 22 18 9 WILLIAM 65.2 301.6 156 217 +1996 9 27 18 9 LESLIE 35.7 209.3 121 180 +1994 12 11 6 27 WILLIAM 69.0 200.1 91 732 +1968 4 17 12 12 MICHAEL 17.8 187.1 87 369 +2004 8 7 6 6 PATTY 18.6 239.3 33 524 +1957 11 22 18 15 MICHAEL 38.8 208.2 75 125 +1960 9 27 12 6 MICHAEL 47.7 309.9 85 110 +2003 6 2 6 22 NADINE 41.8 274.4 38 670 +1961 5 27 18 1 WILLIAM 26.3 258.3 21 61 +2003 3 22 6 16 TONY 55.9 313.9 106 784 +1990 7 21 18 18 VALERIE 51.1 28.7 49 216 +1999 4 14 18 10 VALERIE 9.7 120.4 136 574 +1954 8 6 12 26 NADINE 64.7 97.3 115 126 +1978 5 26 18 13 VALERIE 13.2 115.9 22 24 +1965 3 23 0 17 ISAAC 62.9 154.0 130 206 +1963 8 23 18 14 JOYCE 31.7 260.9 11 342 +1958 9 2 12 26 JOYCE 36.9 205.6 73 489 +1992 11 9 6 3 PATTY 45.0 126.7 145 222 +1992 11 23 6 7 ISAAC 47.7 146.1 61 244 +1995 8 8 6 21 RAFAEL 9.9 128.8 124 736 +1965 9 22 6 15 VALERIE 27.2 198.3 58 662 +1985 8 9 12 20 WILLIAM 64.5 17.3 101 843 +1969 11 16 18 14 RAFAEL 63.7 277.3 62 491 +1982 11 22 0 12 DEBBY 39.8 140.2 17 843 +1968 5 11 6 3 DEBBY 61.4 103.2 41 790 +1981 4 21 12 14 GORDON 13.8 159.2 48 205 +1958 8 21 0 18 OSCAR 38.1 187.8 163 645 +1996 7 26 6 20 VALERIE 44.2 140.1 128 337 +1979 8 27 6 23 HELENE 48.5 345.5 22 287 +1963 11 12 0 9 BERYL 31.9 201.7 137 390 +1972 11 23 6 27 MICHAEL 20.6 325.5 95 810 +1999 3 21 0 14 BERYL 39.4 117.5 58 581 +1996 2 18 12 6 ALBERTO 41.2 103.3 116 236 +1983 10 23 6 18 LESLIE 52.8 351.5 156 710 +1987 5 10 0 28 GORDON 25.4 268.5 71 451 +1958 5 18 18 15 TONY 21.2 324.7 73 6 +1987 6 19 6 6 LESLIE 64.9 94.4 19 531 +1972 2 2 6 28 CHRIS 36.6 265.2 164 867 +1998 5 16 6 23 NADINE 26.6 215.1 133 590 +1994 9 23 6 27 ALBERTO 64.7 95.7 125 471 +1987 7 17 18 8 FLORENCE 47.8 330.8 131 4 +1970 6 20 18 16 BERYL 56.3 274.5 118 662 +1953 12 12 12 17 ALBERTO 63.1 306.0 31 70 +1987 10 3 6 7 WILLIAM 39.3 74.6 150 545 +1987 11 23 12 7 ALBERTO 53.3 226.7 99 572 +1988 10 20 12 4 RAFAEL 42.6 305.1 113 645 +1966 7 11 6 5 MICHAEL 40.7 276.0 44 490 +1951 9 5 12 28 GORDON 56.1 165.3 154 881 +1977 11 1 18 22 SANDY 26.2 229.4 98 775 +1966 6 17 6 8 SANDY 59.3 204.8 42 475 +1977 8 4 6 2 LESLIE 8.9 1.1 32 545 +1959 11 23 6 6 SANDY 69.6 184.4 63 13 +1968 8 19 6 7 ERNESTO 35.1 19.6 88 799 +1952 6 18 0 20 LESLIE 58.1 353.1 155 86 +1985 4 6 6 13 TONY 17.9 109.9 154 258 +1980 12 13 6 23 SANDY 16.6 302.5 145 323 +1972 5 25 0 16 RAFAEL 17.8 223.4 14 679 +2002 7 10 0 8 ISAAC 24.7 326.3 163 449 +1987 1 21 6 10 TONY 35.7 195.3 161 374 +1985 9 9 18 13 LESLIE 21.8 245.3 147 422 +1956 11 26 6 21 WILLIAM 12.6 255.2 40 182 +1965 11 12 0 28 CHRIS 55.8 34.5 132 340 +2000 5 9 12 25 WILLIAM 17.3 157.5 84 620 +1991 12 2 6 2 PATTY 57.2 52.2 123 677 +1970 11 25 18 26 OSCAR 27.9 145.8 99 475 +1977 5 3 0 27 CHRIS 16.9 235.2 92 35 +1983 1 27 0 20 VALERIE 20.1 185.4 16 352 +1965 9 14 18 24 SANDY 47.0 20.6 83 582 +1966 9 14 0 2 SANDY 53.8 62.0 134 28 +2003 9 15 12 7 SANDY 57.2 23.1 134 246 +1989 2 27 0 22 DEBBY 57.8 282.3 81 588 +1964 5 4 6 7 ALBERTO 20.5 30.1 31 625 +1963 7 17 6 19 OSCAR 48.1 117.3 60 429 +1988 10 22 18 25 KIRK 66.8 331.2 148 41 +1994 1 19 18 24 CHRIS 44.7 316.7 30 414 +1998 12 2 12 7 WILLIAM 22.1 80.1 59 393 +2001 11 19 12 17 CHRIS 20.0 326.6 89 748 +2000 9 3 12 25 BERYL 29.6 71.9 79 347 +1962 8 15 12 21 BERYL 16.0 356.3 86 499 +1966 1 13 12 22 JOYCE 31.1 176.7 132 636 +1964 8 15 12 2 RAFAEL 41.8 242.4 76 358 +1977 8 6 12 17 MICHAEL 22.3 241.0 76 99 +1990 3 28 6 15 PATTY 9.7 196.8 103 805 +1986 8 16 6 24 HELENE 60.5 121.8 103 604 +2001 4 23 12 21 RAFAEL 62.5 172.6 105 446 +1973 6 26 12 14 CHRIS 20.0 239.7 64 606 +1990 10 26 12 16 TONY 20.9 235.1 154 418 +1992 8 25 12 13 HELENE 45.0 74.9 127 149 +1979 12 22 0 11 GORDON 40.1 176.3 117 831 +1984 5 27 18 5 CHRIS 59.9 65.4 121 172 +1989 9 7 6 15 LESLIE 40.1 290.2 136 208 +1980 6 26 18 13 ERNESTO 55.7 304.6 149 820 +1994 6 8 6 23 OSCAR 41.8 142.8 40 402 +1966 3 2 6 7 BERYL 36.1 235.6 77 85 +1950 5 19 12 26 LESLIE 51.5 210.3 103 787 +2001 6 15 6 17 LESLIE 24.3 32.6 152 147 +1963 2 21 6 17 CHRIS 40.4 203.4 130 35 +1991 3 15 0 17 OSCAR 17.6 185.2 37 683 +1951 2 27 18 14 HELENE 53.7 314.6 162 576 +1998 9 15 12 25 WILLIAM 12.6 128.4 161 396 +1974 8 14 0 1 ALBERTO 7.6 144.5 146 93 +1981 10 23 0 1 WILLIAM 8.2 16.8 152 65 +1955 8 2 6 7 JOYCE 44.8 138.3 153 524 +1971 12 8 18 14 MICHAEL 49.9 89.0 40 82 +1966 7 24 0 22 OSCAR 23.1 97.1 117 311 +1958 1 24 18 16 DEBBY 56.1 275.3 80 834 +1951 6 17 12 5 WILLIAM 63.7 336.3 130 581 +1974 9 16 12 19 NADINE 34.8 153.7 63 352 +1951 12 3 0 26 VALERIE 28.4 27.5 20 727 +1998 8 16 6 28 JOYCE 55.7 69.3 124 809 +2002 4 20 6 1 ERNESTO 47.2 67.9 38 132 +1989 11 22 6 2 VALERIE 55.6 66.7 49 319 +1954 4 16 6 10 ERNESTO 39.4 356.9 105 384 +1958 8 28 0 15 DEBBY 53.0 321.0 64 523 +1990 4 22 18 16 OSCAR 7.5 208.5 87 445 +2004 11 3 12 25 FLORENCE 29.8 349.0 23 97 +1970 8 6 18 26 CHRIS 36.3 206.8 132 753 +1975 10 12 6 15 ISAAC 63.5 326.7 80 700 +1971 11 18 18 21 DEBBY 35.8 270.2 38 716 +1978 12 9 18 11 ISAAC 17.7 125.4 115 532 +1953 9 5 12 14 LESLIE 69.5 347.5 151 334 +2004 1 5 6 27 OSCAR 28.4 14.9 163 214 +1977 8 15 18 4 TONY 49.5 94.0 146 332 +1989 10 10 6 22 GORDON 47.2 174.1 120 204 +1985 4 4 0 26 GORDON 47.6 5.3 162 113 +1980 11 23 12 15 JOYCE 62.4 71.8 132 596 +1991 6 9 0 25 OSCAR 60.9 285.5 140 818 +1982 12 26 0 16 ERNESTO 60.9 41.5 84 95 +2003 5 10 6 21 ALBERTO 28.8 69.4 98 5 +1952 4 3 6 25 KIRK 42.2 71.4 41 581 +1973 8 9 6 12 JOYCE 25.7 355.7 88 625 +1971 8 4 12 10 JOYCE 12.8 250.0 71 285 +1996 10 5 6 26 MICHAEL 65.1 244.6 19 389 +2002 11 18 6 8 OSCAR 58.4 184.1 152 115 +1979 3 5 12 20 PATTY 39.3 159.7 15 28 +1956 12 9 0 19 JOYCE 38.1 212.9 64 623 +1996 11 5 18 2 SANDY 57.8 104.1 121 196 +1958 8 20 18 11 SANDY 33.0 306.1 150 834 +1981 10 13 12 17 HELENE 68.4 110.1 144 243 +1958 12 21 0 27 PATTY 68.6 239.8 15 793 +1957 10 23 0 26 CHRIS 57.0 55.0 44 204 +1957 8 22 0 9 CHRIS 10.1 58.7 72 732 +2003 10 19 12 10 KIRK 20.2 48.1 58 303 +1967 6 16 0 8 ISAAC 20.1 289.8 82 872 +1974 1 25 12 5 FLORENCE 41.7 129.8 102 128 +2002 7 15 18 25 RAFAEL 65.0 270.0 97 585 +1997 6 8 12 20 JOYCE 56.6 95.5 48 501 +1985 2 5 18 23 KIRK 22.9 162.3 59 784 +1992 3 10 6 9 SANDY 40.0 281.2 146 407 +1968 7 12 18 22 VALERIE 29.8 98.2 13 104 +1996 12 21 18 2 WILLIAM 42.7 139.4 135 325 +2000 5 28 12 6 OSCAR 21.1 78.6 69 687 +1975 3 21 0 4 WILLIAM 40.1 306.1 162 253 +1986 2 19 6 27 ALBERTO 19.9 329.1 137 869 +1999 6 21 0 7 ALBERTO 44.9 245.5 19 460 +1950 10 23 0 19 ALBERTO 9.5 337.6 135 796 +1952 6 2 18 28 WILLIAM 14.8 293.2 41 433 +1963 1 6 6 9 JOYCE 58.6 147.1 117 553 +1956 12 17 6 28 HELENE 30.3 277.8 15 412 +1996 10 5 18 3 PATTY 63.9 249.2 107 49 +1973 1 2 12 21 DEBBY 31.7 123.2 144 140 +1983 4 28 0 15 KIRK 54.0 208.5 133 896 +1990 7 22 12 17 CHRIS 38.8 92.2 36 832 +1994 9 5 6 17 PATTY 23.2 82.3 19 410 +1993 4 26 18 16 JOYCE 43.1 269.3 112 821 +1980 4 5 0 13 ISAAC 10.8 60.3 154 738 +1992 11 2 12 19 GORDON 55.4 273.3 24 314 +1990 6 8 12 7 BERYL 67.7 328.4 53 874 +1981 8 18 0 5 LESLIE 57.5 250.8 118 850 +1995 10 11 12 4 DEBBY 35.6 282.7 144 284 +2000 8 3 6 16 GORDON 65.6 295.6 62 301 +1960 4 12 12 3 OSCAR 52.3 173.4 133 160 +2003 1 26 6 21 ALBERTO 56.1 7.8 144 626 +1994 8 17 12 8 KIRK 66.2 153.9 103 111 +1984 10 2 18 9 RAFAEL 49.9 58.6 11 104 +1969 8 20 18 20 ALBERTO 32.1 26.0 39 746 +1999 7 5 0 6 DEBBY 41.6 278.1 101 586 +1954 6 3 12 11 PATTY 26.6 147.2 132 546 +1976 1 19 0 15 ALBERTO 32.9 274.2 160 21 +1977 7 9 0 20 GORDON 47.1 119.9 56 833 +1977 2 5 0 16 KIRK 33.6 104.7 57 400 +1967 3 10 12 13 FLORENCE 17.6 131.7 97 872 +1982 7 22 6 17 HELENE 18.4 332.9 85 783 +1994 1 1 12 18 CHRIS 69.3 349.4 57 703 +1962 3 3 6 14 NADINE 68.8 118.1 143 412 +1954 7 27 12 6 JOYCE 44.8 154.3 153 534 +1994 7 15 6 3 FLORENCE 18.6 313.0 79 124 +1994 1 12 12 20 RAFAEL 37.8 319.9 59 90 +1986 2 17 6 4 SANDY 59.8 310.8 74 353 +1982 9 4 0 5 WILLIAM 17.9 216.6 98 673 +1971 11 27 18 23 OSCAR 62.5 303.9 90 267 +1961 12 22 0 13 JOYCE 54.2 213.6 151 773 +1981 2 19 6 9 KIRK 44.5 264.4 62 814 +1994 9 18 12 27 JOYCE 24.1 88.7 94 176 +1951 11 11 0 7 DEBBY 50.3 276.0 46 61 +2001 9 9 6 18 ISAAC 23.8 233.0 146 76 +1979 1 9 18 12 OSCAR 53.6 102.3 73 333 +1994 12 11 12 3 FLORENCE 39.6 106.7 35 370 +2000 2 15 0 24 NADINE 19.6 90.8 34 529 +1952 10 4 18 24 ISAAC 34.2 88.8 60 66 +1973 12 15 12 16 ERNESTO 52.1 315.7 28 800 +1997 10 11 12 18 NADINE 66.3 151.0 109 845 +1993 6 7 18 24 FLORENCE 15.0 23.3 46 212 +1969 9 27 12 4 PATTY 26.7 63.6 83 738 +1993 6 13 12 25 DEBBY 32.0 292.5 111 473 +1977 10 11 0 26 PATTY 64.0 200.1 92 877 +1988 7 13 18 16 JOYCE 20.3 34.3 31 648 +2004 7 4 12 1 CHRIS 66.9 39.4 36 809 +1986 4 12 12 19 DEBBY 56.2 19.8 24 525 +1967 5 22 12 27 LESLIE 30.6 269.2 56 515 +1957 12 19 18 18 LESLIE 39.0 98.4 10 714 +2001 7 11 0 23 WILLIAM 33.8 54.2 91 160 +1975 9 7 12 2 KIRK 48.8 276.2 150 147 +1986 10 2 0 2 DEBBY 28.9 177.3 90 521 +1974 1 6 6 28 SANDY 32.8 257.3 131 340 +1981 2 7 0 17 DEBBY 13.7 190.3 36 601 +1955 12 22 0 14 LESLIE 42.3 79.5 162 700 +1996 11 3 0 23 JOYCE 53.4 61.7 45 151 +1978 6 28 12 15 VALERIE 28.8 145.9 22 600 +1953 7 13 12 21 CHRIS 46.3 93.4 111 170 +1982 4 12 6 15 HELENE 27.6 175.0 95 848 +1971 4 25 12 5 LESLIE 25.0 349.1 97 723 +2000 11 26 12 24 MICHAEL 48.6 119.1 148 866 +1982 4 27 12 4 RAFAEL 39.7 216.1 155 508 +2000 7 23 18 9 NADINE 60.9 338.4 73 723 +1953 11 2 18 18 ISAAC 43.1 117.2 96 754 +1965 3 1 12 18 LESLIE 15.5 32.2 141 34 +1988 11 22 18 15 KIRK 17.6 213.4 48 870 +1951 12 25 18 4 CHRIS 27.8 51.2 93 46 +1978 6 24 6 3 BERYL 10.0 225.0 55 200 +1970 3 24 6 26 BERYL 21.9 125.0 117 0 +1977 6 6 0 16 MICHAEL 12.7 217.6 158 19 +1954 11 9 0 20 LESLIE 54.6 42.0 162 511 +1953 5 21 6 12 MICHAEL 61.0 215.7 13 653 +1997 3 8 18 5 OSCAR 40.4 296.6 119 288 +2004 4 4 0 7 NADINE 27.2 16.7 93 411 +1975 2 7 0 4 MICHAEL 21.2 321.3 48 131 +1970 8 15 18 27 LESLIE 7.3 103.6 94 454 +1995 9 22 12 28 WILLIAM 63.9 320.0 113 117 +1988 9 19 0 9 HELENE 67.3 52.6 142 608 +1956 2 18 6 28 JOYCE 48.1 14.7 126 545 +1979 3 24 18 7 ALBERTO 48.6 32.9 138 354 +1955 4 22 18 21 KIRK 40.8 46.8 74 584 +1988 8 7 12 25 GORDON 43.1 315.1 73 75 +2003 2 28 18 21 DEBBY 19.3 191.7 31 310 +1961 8 17 18 17 KIRK 46.6 182.2 142 148 +1954 6 6 0 25 PATTY 42.1 95.0 97 596 +1958 3 22 18 6 WILLIAM 23.3 6.1 81 677 +1963 6 22 12 19 JOYCE 56.4 292.9 65 477 +1980 11 23 12 10 WILLIAM 50.6 229.7 145 750 +2000 12 2 0 5 KIRK 20.8 333.8 133 408 +2002 3 15 12 27 MICHAEL 67.8 323.5 109 536 +1968 5 20 6 28 FLORENCE 19.6 327.0 14 73 +1956 10 24 12 20 NADINE 47.5 322.6 151 748 +1997 11 5 0 8 DEBBY 22.5 34.0 40 841 +1950 6 17 12 27 LESLIE 59.8 233.6 55 504 +1982 5 22 6 17 RAFAEL 36.7 336.4 150 90 +1964 7 7 18 19 MICHAEL 7.4 6.8 78 654 +1997 9 18 12 24 CHRIS 10.3 23.3 81 755 +2000 9 26 18 19 KIRK 44.7 206.6 111 622 +1950 7 27 18 24 ALBERTO 33.2 280.3 27 215 +1993 9 9 6 17 CHRIS 19.9 193.1 145 509 +2000 2 12 0 25 FLORENCE 51.9 301.7 83 858 +1961 12 19 0 23 GORDON 32.8 162.3 111 741 +1998 2 15 12 12 TONY 31.6 313.4 28 51 +1985 7 6 12 16 PATTY 27.1 302.8 120 328 +1964 1 1 18 17 KIRK 68.5 108.7 29 609 +1962 9 13 18 11 HELENE 15.4 188.6 120 218 +1988 6 23 0 4 ERNESTO 37.8 172.1 16 790 +1952 10 2 0 16 BERYL 30.8 158.9 77 61 +2001 9 12 0 16 LESLIE 64.8 32.2 112 264 +1978 12 11 6 24 PATTY 48.8 214.4 148 763 +1961 7 7 12 21 ERNESTO 32.8 326.2 112 803 +1958 10 18 12 19 KIRK 68.4 2.0 65 318 +1976 11 24 18 9 ALBERTO 46.5 63.6 11 851 +1983 11 19 0 9 WILLIAM 52.6 124.7 160 848 +1963 8 2 0 9 ALBERTO 58.5 180.1 74 814 +1984 2 15 12 11 MICHAEL 21.9 187.1 42 467 +1989 12 23 18 1 CHRIS 29.5 40.0 33 62 +2003 2 19 18 1 KIRK 31.7 42.7 39 144 +1956 3 4 0 7 KIRK 16.5 195.6 83 189 +1952 10 4 18 27 PATTY 65.4 345.4 80 535 +2004 9 19 18 18 CHRIS 55.9 264.0 122 236 +1987 4 11 12 18 NADINE 16.4 229.8 72 899 +1992 12 23 0 24 TONY 12.1 256.0 69 658 +1953 1 13 0 4 DEBBY 10.6 258.7 126 635 +1957 6 18 18 25 ALBERTO 64.2 350.7 76 626 +1987 7 19 12 5 SANDY 35.6 194.1 151 613 +1964 7 14 12 26 DEBBY 22.5 207.4 162 737 +1989 2 24 6 27 PATTY 54.0 299.6 146 483 +1961 10 19 12 14 HELENE 60.6 185.6 79 544 +1982 3 24 12 10 VALERIE 57.6 262.8 100 746 +1996 9 10 12 22 HELENE 20.9 30.0 136 60 +1961 1 15 18 26 GORDON 36.8 102.9 102 721 +1977 1 22 6 3 JOYCE 19.7 26.4 119 256 +1964 11 2 6 23 FLORENCE 51.6 33.2 94 375 +1985 3 26 12 26 CHRIS 9.8 170.4 156 884 +1972 8 7 12 25 PATTY 29.0 39.8 124 516 +1953 7 12 12 23 TONY 30.8 49.6 27 92 +2001 6 28 18 7 ISAAC 58.4 52.2 101 426 +1956 3 26 12 14 KIRK 52.5 169.2 32 645 +1994 3 2 12 22 TONY 48.8 298.0 98 411 +1973 2 2 18 8 WILLIAM 60.0 305.7 127 872 +1979 2 28 18 27 ISAAC 27.3 356.8 60 528 +1990 8 19 0 14 JOYCE 47.7 283.0 101 472 +1999 8 21 0 3 OSCAR 31.2 239.1 154 170 +1976 2 16 12 11 KIRK 15.9 336.8 74 799 +2001 3 14 12 20 GORDON 14.0 6.2 113 197 +1970 11 24 0 15 ALBERTO 68.4 106.2 20 81 +1970 12 20 18 17 HELENE 65.7 324.0 133 456 +1997 2 13 12 12 CHRIS 69.8 307.7 134 45 +1963 6 24 12 16 WILLIAM 33.2 71.6 123 863 +1985 7 25 12 8 PATTY 37.2 31.0 32 755 +1955 4 15 18 3 NADINE 52.4 259.1 58 614 +1956 7 7 18 6 FLORENCE 34.0 220.2 104 807 +1957 11 3 6 21 HELENE 64.4 326.1 72 736 +1981 6 10 0 14 VALERIE 51.7 135.0 144 192 +1965 5 19 0 19 KIRK 25.2 124.7 12 313 +2004 11 6 12 18 ISAAC 41.4 92.2 77 296 +1967 10 15 0 12 TONY 36.1 357.3 54 306 +1955 7 23 12 8 RAFAEL 43.1 349.6 94 26 +1950 4 21 0 4 JOYCE 13.6 0.8 163 895 +1961 1 23 6 12 ISAAC 43.0 264.6 118 254 +1957 10 2 12 3 ISAAC 20.9 138.6 56 225 +1970 2 10 6 24 JOYCE 44.0 324.3 133 759 +1989 3 17 6 1 MICHAEL 56.0 26.7 98 414 +1997 9 19 12 19 GORDON 34.6 237.5 89 391 +1956 5 13 12 27 MICHAEL 10.3 274.6 153 94 +1989 7 8 0 20 MICHAEL 62.3 3.5 85 405 +2004 7 16 12 12 PATTY 59.6 53.9 88 585 +1993 1 4 18 10 ISAAC 21.9 80.3 47 488 +1987 12 20 6 20 CHRIS 38.5 7.6 12 870 +1963 10 28 0 3 NADINE 30.0 35.3 43 447 +1997 8 21 18 12 FLORENCE 37.7 225.4 142 593 +1991 7 20 18 5 VALERIE 49.1 122.7 68 50 +1968 7 3 0 28 GORDON 21.8 170.6 100 603 +1958 8 22 18 11 ALBERTO 23.1 189.3 100 787 +1968 12 5 12 13 PATTY 61.2 91.6 114 706 +1980 11 5 18 6 LESLIE 53.3 274.4 66 862 +1971 11 1 0 10 KIRK 56.8 317.7 26 893 +1995 2 5 18 1 VALERIE 25.9 97.0 154 83 +1983 1 19 12 21 PATTY 13.8 296.7 121 867 +1955 9 11 18 24 PATTY 38.1 244.1 97 356 +1982 6 16 12 8 OSCAR 19.1 190.5 23 674 +1995 1 1 6 26 OSCAR 21.8 324.4 100 61 +1988 11 10 6 8 GORDON 64.8 295.1 151 632 +2003 8 18 6 7 SANDY 30.5 26.9 25 315 +1959 11 23 18 21 ISAAC 43.2 135.0 63 62 +1989 9 7 12 19 RAFAEL 7.6 257.2 81 17 +1963 2 27 18 10 KIRK 51.8 140.4 69 210 +1954 10 24 18 12 TONY 48.4 76.8 12 760 +1994 6 18 12 6 ALBERTO 18.5 50.5 45 49 +1999 2 12 18 18 MICHAEL 7.2 10.8 51 385 +1979 11 22 18 10 DEBBY 32.0 158.4 69 295 +1971 10 27 0 7 DEBBY 21.6 132.8 44 231 +1959 8 6 18 12 ALBERTO 26.2 331.0 74 485 +1955 12 10 0 21 CHRIS 25.4 180.7 19 238 +1962 2 6 6 19 HELENE 18.5 294.1 143 77 +1950 4 11 6 14 ISAAC 54.2 285.4 161 21 +1985 9 6 0 16 MICHAEL 39.5 353.2 39 415 +1984 10 8 12 24 GORDON 47.1 83.5 12 375 +1952 10 28 6 6 LESLIE 32.6 244.6 114 239 +1953 6 2 12 10 NADINE 20.7 202.4 84 850 +1953 1 11 0 3 DEBBY 56.2 229.9 68 219 +1966 3 17 6 7 HELENE 19.4 171.4 23 245 +1970 11 7 12 4 ERNESTO 60.6 196.9 89 644 +2000 1 3 0 15 KIRK 53.5 150.6 108 671 +1966 7 11 12 25 LESLIE 23.4 155.9 144 476 +1998 2 23 12 25 TONY 35.5 92.9 115 322 +1989 8 23 0 4 PATTY 35.9 168.3 72 346 +1994 3 22 6 13 GORDON 37.7 32.5 151 88 +1970 2 20 18 4 GORDON 48.3 202.5 95 577 +1970 2 3 12 23 GORDON 33.2 241.0 156 784 +1986 7 1 6 7 VALERIE 57.0 110.3 154 651 +1974 12 19 12 28 NADINE 11.6 72.9 14 396 +1971 4 12 0 18 HELENE 68.6 279.9 29 223 +1986 2 21 6 4 ISAAC 24.4 172.6 60 112 +1994 2 17 6 20 RAFAEL 53.0 111.3 59 542 +1996 2 9 0 23 BERYL 49.1 355.9 102 772 +1996 9 17 12 20 VALERIE 35.5 93.9 50 123 +1968 5 3 12 2 OSCAR 46.6 45.5 110 326 +1986 5 26 12 17 OSCAR 30.5 329.4 160 196 +1956 3 11 0 1 RAFAEL 12.6 58.1 85 87 +1980 4 16 0 17 FLORENCE 34.7 333.5 85 685 +1982 7 4 6 10 FLORENCE 41.1 125.7 142 241 +1991 11 7 0 25 BERYL 29.7 281.1 72 331 +1956 4 21 0 19 SANDY 27.4 46.8 67 24 +1972 6 7 12 11 VALERIE 55.1 46.6 90 724 +1960 4 22 6 18 RAFAEL 11.6 19.1 156 479 +2004 3 6 0 12 ALBERTO 15.2 36.2 12 480 +1986 10 13 0 11 ALBERTO 14.7 99.9 35 425 +1971 8 18 12 25 HELENE 19.4 238.9 131 291 +1999 7 7 12 5 CHRIS 44.3 93.7 141 239 +1968 10 25 18 24 DEBBY 47.1 295.2 42 437 +1978 4 8 0 3 FLORENCE 32.6 177.7 42 72 +1991 8 21 12 20 JOYCE 16.9 152.6 16 765 +1993 4 9 6 14 SANDY 63.0 167.7 111 827 +1968 9 22 18 18 RAFAEL 18.6 129.7 56 780 +1985 4 8 12 14 RAFAEL 48.5 112.0 28 237 +1978 10 3 18 24 OSCAR 8.1 303.9 37 561 +1972 5 17 6 21 VALERIE 62.2 45.7 34 666 +2002 11 21 12 11 VALERIE 33.5 51.9 154 162 +1964 10 26 6 9 JOYCE 8.6 121.3 69 707 +2003 1 8 6 9 OSCAR 23.9 240.0 71 267 +1978 2 13 6 24 GORDON 15.4 169.5 18 641 +1981 6 3 12 13 FLORENCE 70.0 13.3 99 825 +2002 9 9 0 9 ALBERTO 31.4 156.3 129 5 +1964 8 24 0 17 LESLIE 64.4 157.2 120 843 +1952 9 12 12 6 KIRK 20.7 226.0 78 621 +1994 6 28 18 6 WILLIAM 63.6 218.1 111 146 +1980 4 15 6 20 WILLIAM 55.4 33.4 127 330 +1962 12 7 6 12 ERNESTO 45.2 250.9 23 273 +1963 5 23 12 12 ERNESTO 14.5 42.6 21 633 +1968 7 27 6 23 ERNESTO 38.8 305.2 43 477 +1995 12 14 6 25 FLORENCE 62.7 89.5 65 672 +2004 4 14 12 3 TONY 29.1 64.3 88 648 +1998 11 28 6 12 ERNESTO 25.2 83.0 93 75 +1978 2 13 12 19 FLORENCE 25.6 25.1 124 123 +1975 8 26 6 10 ALBERTO 32.6 152.8 50 722 +1980 2 15 0 6 MICHAEL 14.1 251.8 40 327 +1961 4 6 0 16 PATTY 38.3 189.9 11 270 +1959 7 5 0 16 VALERIE 58.0 8.4 153 2 +1974 6 9 12 26 DEBBY 8.6 151.0 52 95 +2002 12 2 12 9 RAFAEL 48.9 355.8 150 607 +1974 9 5 0 9 OSCAR 39.1 269.6 25 496 +1953 7 25 18 6 CHRIS 60.9 160.7 57 456 +1985 2 11 6 2 ERNESTO 9.0 300.1 67 157 +1981 8 11 0 6 KIRK 57.7 122.3 23 98 +1957 12 9 12 28 RAFAEL 26.0 236.6 138 67 +1990 6 13 12 10 SANDY 62.3 252.9 149 110 +1977 9 24 0 7 PATTY 22.1 272.5 132 769 +1958 1 23 12 2 JOYCE 58.7 13.3 113 598 +1995 9 26 0 14 RAFAEL 22.9 293.1 34 491 +1962 1 12 18 28 ALBERTO 59.1 84.4 97 547 +1953 4 11 18 18 KIRK 45.9 77.1 77 537 +2002 7 19 6 24 GORDON 35.6 257.1 35 804 +1982 8 13 0 23 SANDY 19.5 310.4 58 237 +1968 5 15 6 28 ALBERTO 7.9 331.4 115 672 +1954 3 17 12 11 LESLIE 14.1 143.5 156 353 +1959 1 26 0 19 KIRK 51.9 216.0 118 684 +1989 3 16 18 16 CHRIS 63.8 32.6 63 737 +1977 5 26 18 4 ISAAC 20.6 6.1 100 124 +1968 10 4 6 2 TONY 62.2 254.1 54 769 +1954 12 26 0 25 KIRK 68.8 288.4 158 867 +1993 4 15 12 9 GORDON 35.4 325.3 32 4 +2000 1 5 0 6 ALBERTO 54.3 221.1 118 535 +2000 12 24 18 23 DEBBY 65.7 35.6 106 565 +1970 4 11 0 2 DEBBY 57.1 341.5 157 298 +1972 3 21 6 18 RAFAEL 23.3 26.0 18 584 +2002 2 8 0 2 BERYL 50.0 287.6 98 381 +1992 1 13 12 15 KIRK 13.3 346.5 53 864 +1962 6 5 12 26 WILLIAM 61.2 55.1 74 559 +2003 6 11 6 18 FLORENCE 43.5 238.4 95 460 +1985 1 16 6 5 OSCAR 16.9 313.9 117 218 +1992 9 26 18 15 FLORENCE 50.1 132.7 13 223 +1991 11 14 0 22 KIRK 15.1 83.8 136 465 +1985 12 10 0 18 CHRIS 42.9 295.0 157 394 +2000 2 14 18 26 KIRK 64.3 242.0 74 257 +1975 8 26 6 28 OSCAR 46.3 26.5 34 71 +1960 6 3 18 22 TONY 64.5 213.2 23 71 +1980 12 15 6 15 VALERIE 67.1 231.5 115 656 +1989 7 16 6 27 VALERIE 39.4 141.5 128 85 +1992 7 20 0 2 FLORENCE 63.5 170.7 28 75 +1969 12 22 6 20 PATTY 21.1 157.9 90 309 +1970 2 19 12 8 FLORENCE 57.3 76.8 111 351 +1952 11 15 0 13 FLORENCE 56.6 286.0 140 388 +1964 5 16 6 2 VALERIE 61.7 286.0 146 148 +1950 3 8 12 2 ERNESTO 57.8 344.2 57 433 +1988 10 18 12 23 MICHAEL 24.3 315.7 146 548 +1966 4 1 18 8 RAFAEL 53.6 319.3 67 494 +1986 8 28 6 7 ALBERTO 10.9 353.4 78 387 +1983 2 24 18 1 CHRIS 48.6 37.2 17 263 +1950 7 11 0 10 CHRIS 9.7 55.4 57 757 +1965 3 2 18 23 ISAAC 25.3 209.8 74 857 +1984 5 5 12 5 HELENE 43.0 156.5 147 661 +1977 10 4 12 7 ALBERTO 22.6 198.0 100 322 +1965 2 13 18 24 ERNESTO 36.5 14.2 111 748 +1984 1 20 12 9 MICHAEL 33.7 11.2 40 469 +1954 3 14 6 4 MICHAEL 42.5 36.3 56 327 +1963 9 6 6 2 WILLIAM 38.1 167.9 23 409 +2003 6 1 18 5 CHRIS 55.6 36.5 17 820 +1997 7 6 6 15 WILLIAM 10.5 53.9 148 402 +1989 10 11 18 15 JOYCE 14.4 155.6 69 689 +1953 10 23 0 20 ISAAC 59.3 9.9 53 554 +1989 3 18 18 1 ALBERTO 68.5 72.3 109 773 +1999 8 16 6 17 FLORENCE 42.6 147.3 94 20 +1954 8 17 12 17 PATTY 8.1 310.9 60 81 +1976 5 9 0 13 ALBERTO 23.7 302.0 33 349 +1984 1 6 12 19 OSCAR 40.5 285.0 54 788 +1989 11 16 6 8 JOYCE 46.1 235.8 112 377 +1993 4 6 12 25 RAFAEL 44.5 335.5 153 85 +1982 6 26 6 5 JOYCE 43.0 80.3 69 254 +1974 10 12 18 16 DEBBY 53.6 141.2 96 417 +1956 12 2 12 17 KIRK 65.4 121.4 85 509 +1991 2 27 18 3 VALERIE 33.9 277.7 115 329 +2004 8 10 18 1 CHRIS 50.2 167.0 71 699 +1957 2 6 18 7 PATTY 39.1 347.3 101 267 +1965 5 8 0 18 KIRK 53.1 241.8 37 593 +1965 1 9 12 19 JOYCE 39.5 184.2 74 342 +1967 12 19 0 10 BERYL 45.7 23.5 20 847 +1951 9 28 6 16 OSCAR 9.0 266.5 119 756 +1954 11 5 6 22 CHRIS 60.5 308.1 74 115 +1952 12 16 0 26 RAFAEL 40.6 17.2 154 98 +1976 5 21 18 4 TONY 51.2 287.7 146 664 diff --git a/benchmarks/new_opencl/nearn/clutils.cpp b/benchmarks/new_opencl/nearn/clutils.cpp new file mode 100755 index 00000000..6bc42304 --- /dev/null +++ b/benchmarks/new_opencl/nearn/clutils.cpp @@ -0,0 +1,1443 @@ +/****************************************************************************\ + * Copyright (c) 2011, Advanced Micro Devices, Inc. * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or without * + * modification, are permitted provided that the following conditions * + * are met: * + * * + * Redistributions of source code must retain the above copyright notice, * + * this list of conditions and the following disclaimer. * + * * + * Redistributions in binary form must reproduce the above copyright notice, * + * this list of conditions and the following disclaimer in the documentation * + * and/or other materials provided with the distribution. * + * * + * Neither the name of the copyright holder nor the names of its contributors * + * may be used to endorse or promote products derived from this software * + * without specific prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * + * * + * If you use the software (in whole or in part), you shall adhere to all * + * applicable U.S., European, and other export laws, including but not * + * limited to the U.S. Export Administration Regulations (“EAR”), (15 C.F.R. * + * Sections 730 through 774), and E.U. Council Regulation (EC) No 1334/2000 * + * of 22 June 2000. Further, pursuant to Section 740.6 of the EAR, you * + * hereby certify that, except pursuant to a license granted by the United * + * States Department of Commerce Bureau of Industry and Security or as * + * otherwise permitted pursuant to a License Exception under the U.S. Export * + * Administration Regulations ("EAR"), you will not (1) export, re-export or * + * release to a national of a country in Country Groups D:1, E:1 or E:2 any * + * restricted technology, software, or source code you receive hereunder, * + * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such * + * technology or software, if such foreign produced direct product is subject * + * to national security controls as identified on the Commerce Control List * + *(currently found in Supplement 1 to Part 774 of EAR). For the most current * + * Country Group listings, or for additional information about the EAR or * + * your obligations under those regulations, please refer to the U.S. Bureau * + * of Industry and Security’s website at http://www.bis.doc.gov/. * + \****************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "clutils.h" +#include "utils.h" + + +// The following variables have file scope to simplify +// the utility functions + +//! All discoverable OpenCL platforms +static cl_platform_id* platforms = NULL; +static cl_uint numPlatforms; + +//! All discoverable OpenCL devices (one pointer per platform) +static cl_device_id* devices = NULL; +static cl_uint* numDevices; + +//! The chosen OpenCL platform +static cl_platform_id platform = NULL; + +//! The chosen OpenCL device +static cl_device_id device = NULL; + +//! OpenCL context +static cl_context context = NULL; + +//! OpenCL command queue +static cl_command_queue commandQueue = NULL; +static cl_command_queue commandQueueProf = NULL; +static cl_command_queue commandQueueNoProf = NULL; + +//! Global status of events +static bool eventsEnabled = false; + +//------------------------------------------------------- +// Initialization and Cleanup +//------------------------------------------------------- + +//! Initialize OpenCl environment on one device +/*! + Init function for one device. Looks for supported devices and creates a context + \return returns a context initialized +*/ +/*cl_context cl_init(char devicePreference) +{ + cl_int status; + + // Discover and populate the platforms + status = clGetPlatformIDs(0, NULL, &numPlatforms); + cl_errChk(status, "Getting platform IDs", true); + if (numPlatforms > 0) + { + // Get all the platforms + platforms = (cl_platform_id*)alloc(numPlatforms * + sizeof(cl_platform_id)); + + status = clGetPlatformIDs(numPlatforms, platforms, NULL); + cl_errChk(status, "Getting platform IDs", true); + } + else + { + // If no platforms are available, we shouldn't continue + printf("No OpenCL platforms found\n"); + exit(-1); + } + + // Allocate space for the device lists and lengths + numDevices = (cl_uint*)alloc(sizeof(cl_uint)*numPlatforms); + devices = (cl_device_id**)alloc(sizeof(cl_device_id*)*numPlatforms); + + // If a device preference was supplied, we'll limit the search of devices + // based on type + cl_device_type deviceType = CL_DEVICE_TYPE_ALL; + if(devicePreference == 'c') { + deviceType = CL_DEVICE_TYPE_CPU; + } + if(devicePreference == 'g') { + deviceType = CL_DEVICE_TYPE_GPU; + } + + // Traverse the platforms array printing information and + // populating devices + for(unsigned int i = 0; i < numPlatforms ; i++) + { + // Print out some basic info about the platform + char* platformName = NULL; + char* platformVendor = NULL; + + platformName = cl_getPlatformName(platforms[i]); + platformVendor = cl_getPlatformVendor(platforms[i]); + + status = clGetDeviceIDs(platforms[i], deviceType, 0, NULL, &numDevices[i]); + cl_errChk(status, "Getting device IDs", false); + if(status != CL_SUCCESS) { + printf("This is a known NVIDIA bug (if platform == AMD then die)\n"); + printf("Setting number of devices to 0 and continuing\n"); + numDevices[i] = 0; + } + + printf("Platform %d (%d devices):\n", i, numDevices[i]); + printf("\tName: %s\n", platformName); + printf("\tVendor: %s\n", platformVendor); + + free(platformName); + free(platformVendor); + + // Populate OpenCL devices if any exist + if(numDevices[i] != 0) + { + // Allocate an array of devices of size "numDevices" + devices[i] = (cl_device_id*)alloc(sizeof(cl_device_id)*numDevices[i]); + + // Populate Arrray with devices + status = clGetDeviceIDs(platforms[i], deviceType, numDevices[i], + devices[i], NULL); + cl_errChk(status, "Getting device IDs", true); + } + + // Print some information about each device + for( unsigned int j = 0; j < numDevices[i]; j++) + { + char* deviceName = NULL; + char* deviceVendor = NULL; + + printf("\tDevice %d:\n", j); + + deviceName = cl_getDeviceName(devices[i][j]); + deviceVendor = cl_getDeviceVendor(devices[i][j]); + + printf("\t\tName: %s\n", deviceName); + printf("\t\tVendor: %s\n", deviceVendor); + + free(deviceName); + free(deviceVendor); + } + } + + // Hard-code in the platform/device to use, or uncomment 'scanf' + // to decide at runtime + cl_uint chosen_platform, chosen_device; + // UNCOMMENT the following two lines to manually select device each time + //printf("Enter Platform and Device No (Seperated by Space) \n"); + //scanf("%d %d", &chosen_platform, &chosen_device); + chosen_platform = 0; + chosen_device = 0; + printf("Using Platform %d, Device %d \n", chosen_platform, chosen_device); + + // Do a sanity check of platform/device selection + if(chosen_platform >= numPlatforms || + chosen_device >= numDevices[chosen_platform]) { + printf("Invalid platform/device combination\n"); + exit(-1); + } + + // Set the selected platform and device + platform = platforms[chosen_platform]; + device = devices[chosen_platform][chosen_device]; + + // Create the context + cl_context_properties cps[3] = {CL_CONTEXT_PLATFORM, + (cl_context_properties)(platform), 0}; + context = clCreateContext(cps, 1, &device, NULL, NULL, &status); + cl_errChk(status, "Creating context", true); + + // Create the command queue + commandQueueProf = clCreateCommandQueue(context, device, + CL_QUEUE_PROFILING_ENABLE, &status); + cl_errChk(status, "creating command queue", true); + + commandQueueNoProf = clCreateCommandQueue(context, device, 0, &status); + cl_errChk(status, "creating command queue", true); + + if(eventsEnabled) { + printf("Profiling enabled\n"); + commandQueue = commandQueueProf; + } + else { + printf("Profiling disabled\n"); + commandQueue = commandQueueNoProf; + } + + return context; +}*/ + +static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) { + if (nullptr == filename || nullptr == data || 0 == size) + return -1; + + FILE* fp = fopen(filename, "r"); + if (NULL == fp) { + fprintf(stderr, "Failed to load kernel."); + return -1; + } + fseek(fp , 0 , SEEK_END); + long fsize = ftell(fp); + rewind(fp); + + *data = (uint8_t*)malloc(fsize); + *size = fread(*data, 1, fsize, fp); + + fclose(fp); + + return 0; +} + + +cl_context cl_init_context(int platform, int dev,int quiet) { + int printInfo=1; + if (platform >= 0 && dev >= 0) printInfo = 0; + cl_int status; + // Used to iterate through the platforms and devices, respectively + cl_uint numPlatforms; + cl_uint numDevices; + + // These will hold the platform and device we select (can potentially be + // multiple, but we're just doing one for now) + // cl_platform_id platform = NULL; + + /*status = clGetPlatformIDs(0, NULL, &numPlatforms); + if (printInfo) printf("Number of platforms detected:%d\n", numPlatforms); + + // Print some information about the available platforms + cl_platform_id *platforms = NULL; + cl_device_id * devices = NULL; + if (numPlatforms > 0) + { + // get all the platforms + platforms = (cl_platform_id*)malloc(numPlatforms * + sizeof(cl_platform_id)); + status = clGetPlatformIDs(numPlatforms, platforms, NULL); + + // Traverse the platforms array + if (printInfo) printf("Checking For OpenCl Compatible Devices\n"); + for(unsigned int i = 0; i < numPlatforms ; i++) + { + char pbuf[100]; + if (printInfo) printf("Platform %d:\t", i); + status = clGetPlatformInfo(platforms[i], CL_PLATFORM_VENDOR, + sizeof(pbuf), pbuf, NULL); + if (printInfo) printf("Vendor: %s\n", pbuf); + + //unsigned int numDevices; + + status = clGetDeviceIDs(platforms[i], CL_DEVICE_TYPE_ALL, 0, NULL, &numDevices); + if(cl_errChk(status, "checking for devices",true)) + exit(1); + if(numDevices == 0) { + printf("There are no devices for Platform %d\n",i); + exit(0); + } + else + { + if (printInfo) printf("\tNo of devices for Platform %d is %u\n",i, numDevices); + //! Allocate an array of devices of size "numDevices" + devices = (cl_device_id*)malloc(sizeof(cl_device_id)*numDevices); + //! Populate Arrray with devices + status = clGetDeviceIDs(platforms[i], CL_DEVICE_TYPE_ALL, numDevices, + devices, NULL); + if(cl_errChk(status, "getting device IDs",true)) { + exit(1); + } + } + for( unsigned int j = 0; j < numDevices; j++) + { + char dbuf[100]; + char deviceStr[100]; + if (printInfo) printf("\tDevice: %d\t", j); + status = clGetDeviceInfo(devices[j], CL_DEVICE_VENDOR, sizeof(dbuf), + deviceStr, NULL); + cl_errChk(status, "Getting Device Info\n",true); + if (printInfo) printf("Vendor: %s", deviceStr); + status = clGetDeviceInfo(devices[j], CL_DEVICE_NAME, sizeof(dbuf), + dbuf, NULL); + if (printInfo) printf("\n\t\tName: %s\n", dbuf); + } + } + } + else + { + // If no platforms are available, we're sunk! + printf("No OpenCL platforms found\n"); + exit(0); + } + + int platform_touse; + unsigned int device_touse; + if (printInfo) printf("Enter Platform and Device No (Seperated by Space) \n"); + if (printInfo) scanf("%d %d", &platform_touse, &device_touse); + else { + platform_touse = platform; + device_touse = dev; + } + if (!quiet) printf("Using Platform %d \t Device No %d \n",platform_touse, device_touse); + + //! Recheck how many devices does our chosen platform have + status = clGetDeviceIDs(platforms[platform_touse], CL_DEVICE_TYPE_ALL, 0, NULL, &numDevices); + + if(device_touse > numDevices) + { + printf("Invalid Device Number\n"); + exit(1); + } + + //! Populate devices array with all the visible devices of our chosen platform + devices = (cl_device_id *)malloc(sizeof(cl_device_id)*numDevices); + status = clGetDeviceIDs(platforms[platform_touse], + CL_DEVICE_TYPE_ALL, numDevices, + devices, NULL); + if(cl_errChk(status,"Error in Getting Devices\n",true)) exit(1); + + + //!Check if Device requested is a CPU or a GPU + cl_device_type dtype; + device = devices[device_touse]; + status = clGetDeviceInfo(devices[device_touse], + CL_DEVICE_TYPE, + sizeof(dtype), + (void *)&dtype, + NULL); + if(cl_errChk(status,"Error in Getting Device Info\n",true)) exit(1); + if(dtype == CL_DEVICE_TYPE_GPU) { + if (!quiet) printf("Creating GPU Context\n\n"); + } + else if (dtype == CL_DEVICE_TYPE_CPU) { + if (!quiet) printf("Creating CPU Context\n\n"); + } + else perror("This Context Type Not Supported\n"); + + cl_context_properties cps[3] = {CL_CONTEXT_PLATFORM, + (cl_context_properties)(platforms[platform_touse]), 0}; + + cl_context_properties *cprops = cps; + + context = clCreateContextFromType( + cprops, (cl_device_type)dtype, + NULL, NULL, &status); + if(cl_errChk(status, "creating Context",true)) { + exit(1); + }*/ + + // Getting platform and device information + + numPlatforms = 1; + numDevices = 1; + int platform_touse = 0; + int device_touse = 0; + platforms = (cl_platform_id*)malloc(numPlatforms * sizeof(cl_platform_id)); + devices = (cl_device_id*)malloc(sizeof(cl_device_id)*numDevices); + + status = clGetPlatformIDs(1, platforms, NULL); + cl_errChk(status, "Oops!", true); + status = clGetDeviceIDs(platforms[0], CL_DEVICE_TYPE_DEFAULT, 1, devices, NULL); + cl_errChk(status, "Oops!", true); + context = clCreateContext(NULL, 1, devices, NULL, NULL, &status); + cl_errChk(status, "Oops!", true); + + device=devices[device_touse]; + +#define PROFILING + +#ifdef PROFILING + + commandQueue = clCreateCommandQueue(context, + devices[device_touse], CL_QUEUE_PROFILING_ENABLE, &status); + +#else + + clCommandQueue = clCreateCommandQueue(clGPUContext, + devices[device_touse], NULL, &status); + +#endif // PROFILING + + if(cl_errChk(status, "creating command queue",true)) { + exit(1); + } + return context; +} +/*! + Release all resources that the user doesn't have access to. +*/ +void cl_cleanup() +{ + // Free the command queue + if(commandQueue) { + clReleaseCommandQueue(commandQueue); + } + + // Free the context + if(context) { + clReleaseContext(context); + } + + free(devices); + free(numDevices); + + // Free the platforms + free(platforms); +} + +//! Release a kernel object +/*! + \param mem The kernel object to release +*/ +void cl_freeKernel(cl_kernel kernel) +{ + cl_int status; + + if(kernel != NULL) { + status = clReleaseKernel(kernel); + cl_errChk(status, "Releasing kernel object", true); + } +} + +//! Release memory allocated on the device +/*! + \param mem The device pointer to release +*/ +void cl_freeMem(cl_mem mem) +{ + cl_int status; + + if(mem != NULL) { + status = clReleaseMemObject(mem); + cl_errChk(status, "Releasing mem object", true); + } +} + +//! Release a program object +/*! + \param mem The program object to release +*/ +void cl_freeProgram(cl_program program) +{ + cl_int status; + + if(program != NULL) { + status = clReleaseProgram(program); + cl_errChk(status, "Releasing program object", true); + } +} + +//! Returns a reference to the command queue +/*! + Returns a reference to the command queue \n + Used for any OpenCl call that needs the command queue declared in clutils.cpp +*/ +cl_command_queue cl_getCommandQueue() +{ + return commandQueue; +} + +//------------------------------------------------------- +// Synchronization functions +//------------------------------------------------------- + +/*! + Wait till all pending commands in queue are finished +*/ +void cl_sync() +{ + clFinish(commandQueue); +} + + +//------------------------------------------------------- +// Memory allocation +//------------------------------------------------------- + +//! Allocate a buffer on a device +/*! + \param mem_size Size of memory in bytes + \param flags Optional cl_mem_flags + \return Returns a cl_mem object that points to device memory +*/ +cl_mem cl_allocBuffer(size_t mem_size, cl_mem_flags flags) +{ + cl_mem mem; + cl_int status; + + /*! + Logging information for keeping track of device memory + */ + static int allocationCount = 1; + static size_t allocationSize = 0; + + allocationCount++; + allocationSize += mem_size; + + mem = clCreateBuffer(context, flags, mem_size, NULL, &status); + + cl_errChk(status, "creating buffer", true); + + return mem; +} + +//! Allocate constant memory on device +/*! + \param mem_size Size of memory in bytes + \param host_ptr Host pointer that contains the data + \return Returns a cl_mem object that points to device memory +*/ +cl_mem cl_allocBufferConst(size_t mem_size, void* host_ptr) +{ + cl_mem mem; + cl_int status; + + mem = clCreateBuffer(context, CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR, + mem_size, host_ptr, &status); + cl_errChk(status, "Error creating const mem buffer", true); + + return mem; +} + +//! Allocate a buffer on device pinning the host memory at host_ptr +/*! + \param mem_size Size of memory in bytes + \return Returns a cl_mem object that points to pinned memory on the host +*/ +cl_mem cl_allocBufferPinned(size_t mem_size) +{ + cl_mem mem; + cl_int status; + + mem = clCreateBuffer(context, CL_MEM_READ_WRITE | CL_MEM_ALLOC_HOST_PTR, + mem_size, NULL, &status); + cl_errChk(status, "Error allocating pinned memory", true); + + return mem; +} + +//! Allocate an image on a device +/*! + \param height Number of rows in the image + \param width Number of columns in the image + \param elemSize Size of the elements in the image + \param flags Optional cl_mem_flags + \return Returns a cl_mem object that points to device memory +*/ +cl_mem cl_allocImage(size_t height, size_t width, char type, cl_mem_flags flags) +{ + cl_mem mem; + cl_int status; + + size_t elemSize = 0; + + cl_image_format format; + format.image_channel_order = CL_R; + + switch(type) { + case 'f': + elemSize = sizeof(float); + format.image_channel_data_type = CL_FLOAT; + break; + case 'i': + elemSize = sizeof(int); + format.image_channel_data_type = CL_SIGNED_INT32; + break; + default: + printf("Error creating image: Unsupported image type.\n"); + exit(-1); + } + + /*! + Logging information for keeping track of device memory + */ + static int allocationCount = 1; + static size_t allocationSize = 0; + + allocationCount++; + allocationSize += height*width*elemSize; + + // Create the image + mem = clCreateImage2D(context, flags, &format, width, height, 0, NULL, &status); + + //cl_errChk(status, "creating image", true); + if(status != CL_SUCCESS) { + printf("Error creating image: Images may not be supported for this device.\n"); + printSupportedImageFormats(); + getchar(); + exit(-1); + } + + return mem; +} + + +//------------------------------------------------------- +// Data transfers +//------------------------------------------------------- + + +// Copy and map a buffer +void* cl_copyAndMapBuffer(cl_mem dst, cl_mem src, size_t size) { + + void* ptr; // Pointer to the pinned memory that will be returned + + cl_copyBufferToBuffer(dst, src, size); + + ptr = cl_mapBuffer(dst, size, CL_MAP_READ); + + return ptr; +} + +// Copy a buffer +void cl_copyBufferToBuffer(cl_mem dst, cl_mem src, size_t size) +{ + cl_int status; + status = clEnqueueCopyBuffer(commandQueue, src, dst, 0, 0, size, 0, NULL, + NULL); + cl_errChk(status, "Copying buffer", true); + +} + +//! Copy a buffer to the device +/*! + \param dst Valid device pointer + \param src Host pointer that contains the data + \param mem_size Size of data to copy + \param blocking Blocking or non-blocking operation +*/ +void cl_copyBufferToDevice(cl_mem dst, void* src, size_t mem_size, cl_bool blocking) +{ + cl_int status; + status = clEnqueueWriteBuffer(commandQueue, dst, blocking, 0, + mem_size, src, 0, NULL, NULL); + cl_errChk(status, "Writing buffer", true); + +} + +//! Copy a buffer to the host +/*! + \param dst Valid host pointer + \param src Device pointer that contains the data + \param mem_size Size of data to copy + \param blocking Blocking or non-blocking operation +*/ +void cl_copyBufferToHost(void* dst, cl_mem src, size_t mem_size, cl_bool blocking) +{ + cl_int status; + status = clEnqueueReadBuffer(commandQueue, src, blocking, 0, + mem_size, dst, 0, NULL, NULL); + cl_errChk(status, "Reading buffer", true); + +} + +//! Copy a buffer to a 2D image +/*! + \param src Valid device buffer + \param dst Empty device image + \param mem_size Size of data to copy +*/ +void cl_copyBufferToImage(cl_mem buffer, cl_mem image, int height, int width) +{ + size_t origin[3] = {0, 0, 0}; + size_t region[3] = {width, height, 1}; + + cl_int status; + status = clEnqueueCopyBufferToImage(commandQueue, buffer, image, 0, + origin, region, 0, NULL, NULL); + cl_errChk(status, "Copying buffer to image", true); + +} + +// Copy data to an image on the device +/*! + \param dst Valid device pointer + \param src Host pointer that contains the data + \param height Height of the image + \param width Width of the image +*/ +void cl_copyImageToDevice(cl_mem dst, void* src, size_t height, size_t width) +{ + cl_int status; + size_t origin[3] = {0, 0, 0}; + size_t region[3] = {width, height, 1}; + + status = clEnqueueWriteImage(commandQueue, dst, CL_TRUE, origin, + region, 0, 0, src, 0, NULL, NULL); + cl_errChk(status, "Writing image", true); +} + +//! Copy an image to the host +/*! + \param dst Valid host pointer + \param src Device pointer that contains the data + \param height Height of the image + \param width Width of the image +*/ +void cl_copyImageToHost(void* dst, cl_mem src, size_t height, size_t width) +{ + cl_int status; + size_t origin[3] = {0, 0, 0}; + size_t region[3] = {width, height, 1}; + + status = clEnqueueReadImage(commandQueue, src, CL_TRUE, origin, + region, 0, 0, dst, 0, NULL, NULL); + cl_errChk(status, "Reading image", true); +} + +//! Map a buffer into a host address +/*! + \param mem cl_mem object + \param mem_size Size of memory in bytes + \param flags Optional cl_mem_flags + \return Returns a host pointer that points to the mapped region +*/ +void *cl_mapBuffer(cl_mem mem, size_t mem_size, cl_mem_flags flags) +{ + cl_int status; + void *ptr; + + ptr = (void *)clEnqueueMapBuffer(commandQueue, mem, CL_TRUE, flags, + 0, mem_size, 0, NULL, NULL, &status); + + cl_errChk(status, "Error mapping a buffer", true); + + return ptr; +} + +//! Unmap a buffer or image +/*! + \param mem cl_mem object + \param ptr A host pointer that points to the mapped region +*/ +void cl_unmapBuffer(cl_mem mem, void *ptr) +{ + + // TODO It looks like AMD doesn't support profiling unmapping yet. Leaving the + // commented code here until it's supported + + cl_int status; + + status = clEnqueueUnmapMemObject(commandQueue, mem, ptr, 0, NULL, NULL); + + cl_errChk(status, "Error unmapping a buffer or image", true); +} + +void cl_writeToZCBuffer(cl_mem mem, void* data, size_t size) +{ + + void* ptr; + + ptr = cl_mapBuffer(mem, size, CL_MAP_WRITE); + + memcpy(ptr, data, size); + + cl_unmapBuffer(mem, ptr); +} + +//------------------------------------------------------- +// Program and kernels +//------------------------------------------------------- + +//! Convert source code file into cl_program +/*! +Compile Opencl source file into a cl_program. The cl_program will be made into a kernel in PrecompileKernels() + +\param kernelPath Filename of OpenCl code +\param compileoptions Compilation options +\param verbosebuild Switch to enable verbose Output +*/ +cl_program cl_compileProgram(char* kernelPath, char* compileoptions, bool verbosebuild ) +{ + cl_int status; + FILE *fp = NULL; + char *source = NULL; + long int size; + + /*printf("\t%s\n", kernelPath); + + // Determine the size of the source file +#ifdef _WIN32 + fopen_s(&fp, kernelPath, "rb"); +#else + fp = fopen(kernelPath, "rb"); +#endif + if(!fp) { + printf("Could not open kernel file\n"); + exit(-1); + } + status = fseek(fp, 0, SEEK_END); + if(status != 0) { + printf("Error seeking to end of file\n"); + exit(-1); + } + size = ftell(fp); + if(size < 0) { + printf("Error getting file position\n"); + exit(-1); + } + rewind(fp); + + // Allocate enough space for the source code + source = (char *)alloc(size + 1); + + // fill with NULLs (just for fun) + for (int i = 0; i < size+1; i++) { + source[i] = '\0'; + } + + // Read in the source code + fread(source, 1, size, fp); + source[size] = '\0';*/ + + // read kernel binary from file + uint8_t *kernel_bin = NULL; + size_t kernel_size; + cl_int binary_status = 0; + int err = read_kernel_file("kernel.pocl", &kernel_bin, &kernel_size); + cl_errChk(err, "read_kernel_file", true); + + // Create the program object + //cl_program clProgramReturn = clCreateProgramWithSource(context, 1, (const char **)&source, NULL, &status); + cl_program clProgramReturn = clCreateProgramWithBinary( + context, 1, devices, &kernel_size, &kernel_bin, &binary_status, &status); + free(kernel_bin); + cl_errChk(status, "Creating program", true); + + //free(source); + //fclose(fp); + + // Try to compile the program + status = clBuildProgram(clProgramReturn, 0, NULL, compileoptions, NULL, NULL); + if(cl_errChk(status, "Building program", false) || verbosebuild == 1) + { + + cl_build_status build_status; + + clGetProgramBuildInfo(clProgramReturn, device, CL_PROGRAM_BUILD_STATUS, + sizeof(cl_build_status), &build_status, NULL); + + if(build_status == CL_SUCCESS && verbosebuild == 0) { + return clProgramReturn; + } + + //char *build_log; + size_t ret_val_size; + printf("Device: %p",device); + clGetProgramBuildInfo(clProgramReturn, device, CL_PROGRAM_BUILD_LOG, 0, + NULL, &ret_val_size); + + char *build_log = (char*)alloc(ret_val_size+1); + + clGetProgramBuildInfo(clProgramReturn, device, CL_PROGRAM_BUILD_LOG, + ret_val_size+1, build_log, NULL); + + // to be careful, terminate with \0 + // there's no information in the reference whether the string is 0 + // terminated or not + build_log[ret_val_size] = '\0'; + + printf("Build log:\n %s...\n", build_log); + if(build_status != CL_SUCCESS) { + getchar(); + exit(-1); + } + else + return clProgramReturn; + } + + // print the ptx information + // printBinaries(clProgram); + + return clProgramReturn; +} + +//! Create a kernel from compiled source +/*! +Create a kernel from compiled source + +\param program Compiled OpenCL program +\param kernel_name Name of the kernel in the program +\return Returns a cl_kernel object for the specified kernel +*/ +cl_kernel cl_createKernel(cl_program program, const char* kernel_name) { + + cl_kernel kernel; + cl_int status; + + kernel = clCreateKernel(program, kernel_name, &status); + cl_errChk(status, "Creating kernel", true); + + return kernel; +} + +//! Set an argument for a OpenCL kernel +/*! +Set an argument for a OpenCL kernel + +\param kernel The kernel for which the argument is being set +\param index The argument index +\param size The size of the argument +\param data A pointer to the argument +*/ +void cl_setKernelArg(cl_kernel kernel, unsigned int index, size_t size, + void* data) +{ + cl_int status; + status = clSetKernelArg(kernel, index, size, data); + + cl_errChk(status, "Setting kernel arg", true); +} + + +//------------------------------------------------------- +// Profiling/events +//------------------------------------------------------- + + +//! Time kernel execution using cl_event +/*! + Prints out the time taken between the start and end of an event + \param event_time +*/ +double cl_computeExecTime(cl_event event_time) +{ + cl_int status; + cl_ulong starttime; + cl_ulong endtime; + + double elapsed; + + status = clGetEventProfilingInfo(event_time, CL_PROFILING_COMMAND_START, + sizeof(cl_ulong), &starttime, NULL); + cl_errChk(status, "profiling start", true); + + status = clGetEventProfilingInfo(event_time, CL_PROFILING_COMMAND_END, + sizeof(cl_ulong), &endtime, NULL); + cl_errChk(status, "profiling end", true); + + // Convert to ms + elapsed = (double)(endtime-starttime)/1000000.0; + + return elapsed; +} + +//! Compute the elapsed time between two timer values +double cl_computeTime(cl_time start, cl_time end) +{ +#ifdef _WIN32 + __int64 freq; + int status; + + status = QueryPerformanceFrequency((LARGE_INTEGER*)&freq); + if(status == 0) { + perror("QueryPerformanceFrequency"); + exit(-1); + } + + // Return time in ms + return double(end-start)/(double(freq)/1000.0); +#else + + return end-start; +#endif +} + +//! Grab the current time using a system-specific timer +void cl_getTime(cl_time* time) +{ + +#ifdef _WIN32 + int status = QueryPerformanceCounter((LARGE_INTEGER*)time); + if(status == 0) { + perror("QueryPerformanceCounter"); + exit(-1); + } +#else + // Use gettimeofday to get the current time + struct timeval curTime; + gettimeofday(&curTime, NULL); + + // Convert timeval into double + *time = curTime.tv_sec * 1000 + (double)curTime.tv_usec/1000; +#endif +} + + + +//------------------------------------------------------- +// Error handling +//------------------------------------------------------- + +//! OpenCl error code list +/*! + An array of character strings used to give the error corresponding to the error code \n + + The error code is the index within this array +*/ +char *cl_errs[MAX_ERR_VAL] = { + (char *)"CL_SUCCESS", // 0 + (char *)"CL_DEVICE_NOT_FOUND", //-1 + (char *)"CL_DEVICE_NOT_AVAILABLE", //-2 + (char *)"CL_COMPILER_NOT_AVAILABLE", //-3 + (char *)"CL_MEM_OBJECT_ALLOCATION_FAILURE", //-4 + (char *)"CL_OUT_OF_RESOURCES", //-5 + (char *)"CL_OUT_OF_HOST_MEMORY", //-6 + (char *)"CL_PROFILING_INFO_NOT_AVAILABLE", //-7 + (char *)"CL_MEM_COPY_OVERLAP", //-8 + (char *)"CL_IMAGE_FORMAT_MISMATCH", //-9 + (char *)"CL_IMAGE_FORMAT_NOT_SUPPORTED", //-10 + (char *)"CL_BUILD_PROGRAM_FAILURE", //-11 + (char *)"CL_MAP_FAILURE", //-12 + (char *)"", //-13 + (char *)"", //-14 + (char *)"", //-15 + (char *)"", //-16 + (char *)"", //-17 + (char *)"", //-18 + (char *)"", //-19 + (char *)"", //-20 + (char *)"", //-21 + (char *)"", //-22 + (char *)"", //-23 + (char *)"", //-24 + (char *)"", //-25 + (char *)"", //-26 + (char *)"", //-27 + (char *)"", //-28 + (char *)"", //-29 + (char *)"CL_INVALID_VALUE", //-30 + (char *)"CL_INVALID_DEVICE_TYPE", //-31 + (char *)"CL_INVALID_PLATFORM", //-32 + (char *)"CL_INVALID_DEVICE", //-33 + (char *)"CL_INVALID_CONTEXT", //-34 + (char *)"CL_INVALID_QUEUE_PROPERTIES", //-35 + (char *)"CL_INVALID_COMMAND_QUEUE", //-36 + (char *)"CL_INVALID_HOST_PTR", //-37 + (char *)"CL_INVALID_MEM_OBJECT", //-38 + (char *)"CL_INVALID_IMAGE_FORMAT_DESCRIPTOR", //-39 + (char *)"CL_INVALID_IMAGE_SIZE", //-40 + (char *)"CL_INVALID_SAMPLER", //-41 + (char *)"CL_INVALID_BINARY", //-42 + (char *)"CL_INVALID_BUILD_OPTIONS", //-43 + (char *)"CL_INVALID_PROGRAM", //-44 + (char *)"CL_INVALID_PROGRAM_EXECUTABLE", //-45 + (char *)"CL_INVALID_KERNEL_NAME", //-46 + (char *)"CL_INVALID_KERNEL_DEFINITION", //-47 + (char *)"CL_INVALID_KERNEL", //-48 + (char *)"CL_INVALID_ARG_INDEX", //-49 + (char *)"CL_INVALID_ARG_VALUE", //-50 + (char *)"CL_INVALID_ARG_SIZE", //-51 + (char *)"CL_INVALID_KERNEL_ARGS", //-52 + (char *)"CL_INVALID_WORK_DIMENSION ", //-53 + (char *)"CL_INVALID_WORK_GROUP_SIZE", //-54 + (char *)"CL_INVALID_WORK_ITEM_SIZE", //-55 + (char *)"CL_INVALID_GLOBAL_OFFSET", //-56 + (char *)"CL_INVALID_EVENT_WAIT_LIST", //-57 + (char *)"CL_INVALID_EVENT", //-58 + (char *)"CL_INVALID_OPERATION", //-59 + (char *)"CL_INVALID_GL_OBJECT", //-60 + (char *)"CL_INVALID_BUFFER_SIZE", //-61 + (char *)"CL_INVALID_MIP_LEVEL", //-62 + (char *)"CL_INVALID_GLOBAL_WORK_SIZE"}; //-63 + +//! OpenCl Error checker +/*! +Checks for error code as per cl_int returned by OpenCl +\param status Error value as cl_int +\param msg User provided error message +\return True if Error Seen, False if no error +*/ +int cl_errChk(const cl_int status, const char * msg, bool exitOnErr) +{ + + if(status != CL_SUCCESS) { + printf("OpenCL Error: %d %s %s\n", status, cl_errs[-status], msg); + + if(exitOnErr) { + exit(-1); + } + + return true; + } + return false; +} + +// Queries the supported image formats for the device and prints +// them to the screen + void printSupportedImageFormats() +{ + cl_uint numFormats; + cl_int status; + + status = clGetSupportedImageFormats(context, 0, CL_MEM_OBJECT_IMAGE2D, + 0, NULL, &numFormats); + cl_errChk(status, "getting supported image formats", true); + + cl_image_format* imageFormats = NULL; + imageFormats = (cl_image_format*)alloc(sizeof(cl_image_format)*numFormats); + + status = clGetSupportedImageFormats(context, 0, CL_MEM_OBJECT_IMAGE2D, + numFormats, imageFormats, NULL); + + printf("There are %d supported image formats\n", numFormats); + + cl_uint orders[]={CL_R, CL_A, CL_INTENSITY, CL_LUMINANCE, CL_RG, + CL_RA, CL_RGB, CL_RGBA, CL_ARGB, CL_BGRA}; + char *orderstr[]={(char *)"CL_R", (char *)"CL_A",(char *)"CL_INTENSITY", (char *)"CL_LUMINANCE", (char *)"CL_RG", + (char *)"CL_RA", (char *)"CL_RGB", (char *)"CL_RGBA", (char *)"CL_ARGB", (char *)"CL_BGRA"}; + + cl_uint types[]={ + CL_SNORM_INT8 , CL_SNORM_INT16, CL_UNORM_INT8, CL_UNORM_INT16, + CL_UNORM_SHORT_565, CL_UNORM_SHORT_555, CL_UNORM_INT_101010,CL_SIGNED_INT8, + CL_SIGNED_INT16, CL_SIGNED_INT32, CL_UNSIGNED_INT8, CL_UNSIGNED_INT16, + CL_UNSIGNED_INT32, CL_HALF_FLOAT, CL_FLOAT}; + + char * typesstr[]={ + (char *)"CL_SNORM_INT8" ,(char *)"CL_SNORM_INT16",(char *)"CL_UNORM_INT8",(char *)"CL_UNORM_INT16", + (char *)"CL_UNORM_SHORT_565",(char *)"CL_UNORM_SHORT_555",(char *)"CL_UNORM_INT_101010", + (char *)"CL_SIGNED_INT8",(char *)"CL_SIGNED_INT16",(char *)"CL_SIGNED_INT32",(char *)"CL_UNSIGNED_INT8", + (char *)"CL_UNSIGNED_INT16",(char *)"CL_UNSIGNED_INT32",(char *)"CL_HALF_FLOAT",(char *)"CL_FLOAT"}; + + printf("Supported Formats:\n"); + for(int i = 0; i < (int)numFormats; i++) { + printf("\tFormat %d: ", i); + + for(int j = 0; j < (int)(sizeof(orders)/sizeof(cl_int)); j++) { + if(imageFormats[i].image_channel_order == orders[j]) { + printf("%s, ", orderstr[j]); + } + } + for(int j = 0; j < (int)(sizeof(types)/sizeof(cl_int)); j++) { + if(imageFormats[i].image_channel_data_type == types[j]) { + printf("%s, ", typesstr[j]); + } + } + printf("\n"); + } + + free(imageFormats); +} + + +//------------------------------------------------------- +// Platform and device information +//------------------------------------------------------- + +//! Returns true if AMD is the device vendor +bool cl_deviceIsAMD(cl_device_id dev) { + + bool retval = false; + + char* vendor = cl_getDeviceVendor(dev); + + if(strncmp(vendor, "Advanced", 8) == 0) { + retval = true; + } + + free(vendor); + + return retval; +} + +//! Returns true if NVIDIA is the device vendor +bool cl_deviceIsNVIDIA(cl_device_id dev) { + + bool retval = false; + + char* vendor = cl_getDeviceVendor(dev); + + if(strncmp(vendor, "NVIDIA", 6) == 0) { + retval = true; + } + + free(vendor); + + return retval; +} + +//! Returns true if NVIDIA is the device vendor +bool cl_platformIsNVIDIA(cl_platform_id plat) { + + bool retval = false; + + char* vendor = cl_getPlatformVendor(plat); + + if(strncmp(vendor, "NVIDIA", 6) == 0) { + retval = true; + } + + free(vendor); + + return retval; +} + +//! Get the name of the vendor for a device +char* cl_getDeviceDriverVersion(cl_device_id dev) +{ + cl_int status; + size_t devInfoSize; + char* devInfoStr = NULL; + + // If dev is NULL, set it to the default device + if(dev == NULL) { + dev = device; + } + + // Print the vendor + status = clGetDeviceInfo(dev, CL_DRIVER_VERSION, 0, + NULL, &devInfoSize); + cl_errChk(status, "Getting vendor name", true); + + devInfoStr = (char*)alloc(devInfoSize); + + status = clGetDeviceInfo(dev, CL_DRIVER_VERSION, devInfoSize, + devInfoStr, NULL); + cl_errChk(status, "Getting vendor name", true); + + return devInfoStr; +} + +//! The the name of the device as supplied by the OpenCL implementation +char* cl_getDeviceName(cl_device_id dev) +{ + cl_int status; + size_t devInfoSize; + char* devInfoStr = NULL; + + // If dev is NULL, set it to the default device + if(dev == NULL) { + dev = device; + } + + // Print the name + status = clGetDeviceInfo(dev, CL_DEVICE_NAME, 0, + NULL, &devInfoSize); + cl_errChk(status, "Getting device name", true); + + devInfoStr = (char*)alloc(devInfoSize); + + status = clGetDeviceInfo(dev, CL_DEVICE_NAME, devInfoSize, + devInfoStr, NULL); + cl_errChk(status, "Getting device name", true); + + return(devInfoStr); +} + +//! Get the name of the vendor for a device +char* cl_getDeviceVendor(cl_device_id dev) +{ + cl_int status; + size_t devInfoSize; + char* devInfoStr = NULL; + + // If dev is NULL, set it to the default device + if(dev == NULL) { + dev = device; + } + + // Print the vendor + status = clGetDeviceInfo(dev, CL_DEVICE_VENDOR, 0, + NULL, &devInfoSize); + cl_errChk(status, "Getting vendor name", true); + + devInfoStr = (char*)alloc(devInfoSize); + + status = clGetDeviceInfo(dev, CL_DEVICE_VENDOR, devInfoSize, + devInfoStr, NULL); + cl_errChk(status, "Getting vendor name", true); + + return devInfoStr; +} + +//! Get the name of the vendor for a device +char* cl_getDeviceVersion(cl_device_id dev) +{ + cl_int status; + size_t devInfoSize; + char* devInfoStr = NULL; + + // If dev is NULL, set it to the default device + if(dev == NULL) { + dev = device; + } + + // Print the vendor + status = clGetDeviceInfo(dev, CL_DEVICE_VERSION, 0, + NULL, &devInfoSize); + cl_errChk(status, "Getting vendor name", true); + + devInfoStr = (char*)alloc(devInfoSize); + + status = clGetDeviceInfo(dev, CL_DEVICE_VERSION, devInfoSize, + devInfoStr, NULL); + cl_errChk(status, "Getting vendor name", true); + + return devInfoStr; +} + +//! The the name of the device as supplied by the OpenCL implementation +char* cl_getPlatformName(cl_platform_id platform) +{ + cl_int status; + size_t platformInfoSize; + char* platformInfoStr = NULL; + + // Print the name + status = clGetPlatformInfo(platform, CL_PLATFORM_NAME, 0, + NULL, &platformInfoSize); + cl_errChk(status, "Getting platform name", true); + + platformInfoStr = (char*)alloc(platformInfoSize); + + status = clGetPlatformInfo(platform, CL_PLATFORM_NAME, platformInfoSize, + platformInfoStr, NULL); + cl_errChk(status, "Getting platform name", true); + + return(platformInfoStr); +} + +//! The the name of the device as supplied by the OpenCL implementation +char* cl_getPlatformVendor(cl_platform_id platform) +{ + cl_int status; + size_t platformInfoSize; + char* platformInfoStr = NULL; + + // Print the name + status = clGetPlatformInfo(platform, CL_PLATFORM_VENDOR, 0, + NULL, &platformInfoSize); + cl_errChk(status, "Getting platform name", true); + + platformInfoStr = (char*)alloc(platformInfoSize); + + status = clGetPlatformInfo(platform, CL_PLATFORM_VENDOR, platformInfoSize, + platformInfoStr, NULL); + cl_errChk(status, "Getting platform name", true); + + return(platformInfoStr); +} + +//------------------------------------------------------- +// Utility functions +//------------------------------------------------------- + +//! Take a string and an int, and return a string +char* catStringWithInt(const char* string, int integer) { + + if(integer > 99999) { + printf("Can't handle event identifiers with 6 digits\n"); + exit(-1); + } + + // 5 characters for the identifier, 1 for the null terminator + int strLen = strlen(string)+5+1; + char* eventStr = (char*)alloc(sizeof(char)*strLen); + + char tmp[6]; + + strcpy(eventStr, string); + strncat(eventStr, itoa_portable(integer, tmp, 10), 5); + + return eventStr; +} + +/** + ** C++ version 0.4 char* style "itoa": + ** Written by Lukás Chmela + ** Released under GPLv3. + **/ +//portable itoa function +char* itoa_portable(int value, char* result, int base) { + // check that the base if valid + if (base < 2 || base > 36) { *result = '\0'; return result; } + + char* ptr = result, *ptr1 = result, tmp_char; + int tmp_value; + + do { + tmp_value = value; + value /= base; + *ptr++ = "zyxwvutsrqponmlkjihgfedcba9876543210123456789abcdefghijklmnopqrstuvwxyz" [35 + (tmp_value - value * base)]; + } while ( value ); + + //Apply negative sign + if (tmp_value < 0) *ptr++ = '-'; + *ptr-- = '\0'; + + while(ptr1 < ptr) { + tmp_char = *ptr; + *ptr--= *ptr1; + *ptr1++ = tmp_char; + } + + return result; +} \ No newline at end of file diff --git a/benchmarks/new_opencl/nearn/clutils.h b/benchmarks/new_opencl/nearn/clutils.h new file mode 100755 index 00000000..51177d07 --- /dev/null +++ b/benchmarks/new_opencl/nearn/clutils.h @@ -0,0 +1,281 @@ +/****************************************************************************\ + * Copyright (c) 2011, Advanced Micro Devices, Inc. * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or without * + * modification, are permitted provided that the following conditions * + * are met: * + * * + * Redistributions of source code must retain the above copyright notice, * + * this list of conditions and the following disclaimer. * + * * + * Redistributions in binary form must reproduce the above copyright notice, * + * this list of conditions and the following disclaimer in the documentation * + * and/or other materials provided with the distribution. * + * * + * Neither the name of the copyright holder nor the names of its contributors * + * may be used to endorse or promote products derived from this software * + * without specific prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * + * * + * If you use the software (in whole or in part), you shall adhere to all * + * applicable U.S., European, and other export laws, including but not * + * limited to the U.S. Export Administration Regulations (“EAR”), (15 C.F.R. * + * Sections 730 through 774), and E.U. Council Regulation (EC) No 1334/2000 * + * of 22 June 2000. Further, pursuant to Section 740.6 of the EAR, you * + * hereby certify that, except pursuant to a license granted by the United * + * States Department of Commerce Bureau of Industry and Security or as * + * otherwise permitted pursuant to a License Exception under the U.S. Export * + * Administration Regulations ("EAR"), you will not (1) export, re-export or * + * release to a national of a country in Country Groups D:1, E:1 or E:2 any * + * restricted technology, software, or source code you receive hereunder, * + * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such * + * technology or software, if such foreign produced direct product is subject * + * to national security controls as identified on the Commerce Control List * + *(currently found in Supplement 1 to Part 774 of EAR). For the most current * + * Country Group listings, or for additional information about the EAR or * + * your obligations under those regulations, please refer to the U.S. Bureau * + * of Industry and Security’s website at http://www.bis.doc.gov/. * + \****************************************************************************/ + +#ifndef __CL_UTILS_H__ +#define __CL_UTILS_H__ + +#include + +// The cl_time type is OS specific +#ifdef _WIN32 +#include +#include +typedef __int64 cl_time; +#else +#include +typedef double cl_time; +#endif + +//------------------------------------------------------- +// Initialization and Cleanup +//------------------------------------------------------- + +// Detects platforms and devices, creates context and command queue +cl_context cl_init(char devicePreference='\0'); + +// Creates a context given a platform and a device +cl_context cl_init_context(int platform,int dev,int quiet=0); + +// Releases resources used by clutils +void cl_cleanup(); + +// Releases a kernel object +void cl_freeKernel(cl_kernel kernel); + +// Releases a memory object +void cl_freeMem(cl_mem mem); + +// Releases a program object +void cl_freeProgram(cl_program program); + +// Returns the global command queue +cl_command_queue cl_getCommandQueue(); + + +//------------------------------------------------------- +// Synchronization functions +//------------------------------------------------------- + +// Performs a clFinish on the command queue +void cl_sync(); + + +//------------------------------------------------------- +// Memory allocation +//------------------------------------------------------- + +// Allocates a regular buffer on the device +cl_mem cl_allocBuffer(size_t mem_size, + cl_mem_flags flags = CL_MEM_READ_WRITE); + +// XXX I don't think this does exactly what we want it to do +// Allocates a read-only buffer and transfers the data +cl_mem cl_allocBufferConst(size_t mem_size, void* host_ptr); + +// Allocates pinned memory on the host +cl_mem cl_allocBufferPinned(size_t mem_size); + +// Allocates an image on the device +cl_mem cl_allocImage(size_t height, size_t width, char type, + cl_mem_flags flags = CL_MEM_READ_WRITE); + + + +//------------------------------------------------------- +// Data transfers +//------------------------------------------------------- + +// Copies a buffer from the device to pinned memory on the host and +// maps it so it can be read +void* cl_copyAndMapBuffer(cl_mem dst, cl_mem src, size_t size); + +// Copies from one buffer to another +void cl_copyBufferToBuffer(cl_mem dst, cl_mem src, size_t size); + +// Copies data to a buffer on the device +void cl_copyBufferToDevice(cl_mem dst, void *src, size_t mem_size, + cl_bool blocking = CL_TRUE); + +// Copies data to an image on the device +void cl_copyImageToDevice(cl_mem dst, void* src, size_t height, size_t width); + +// Copies an image from the device to the host +void cl_copyImageToHost(void* dst, cl_mem src, size_t height, size_t width); + +// Copies data from a device buffer to the host +void cl_copyBufferToHost(void *dst, cl_mem src, size_t mem_size, + cl_bool blocking = CL_TRUE); + +// Copies data from a buffer on the device to an image on the device +void cl_copyBufferToImage(cl_mem src, cl_mem dst, int height, int width); + +// Maps a buffer +void* cl_mapBuffer(cl_mem mem, size_t mem_size, cl_mem_flags flags); + +// Unmaps a buffer +void cl_unmapBuffer(cl_mem mem, void *ptr); + +// Writes data to a zero-copy buffer on the device +void cl_writeToZCBuffer(cl_mem mem, void* data, size_t size); + +//------------------------------------------------------- +// Program and kernels +//------------------------------------------------------- + +// Compiles a program +cl_program cl_compileProgram(char* kernelPath, char* compileoptions, + bool verboseoptions = 0); + +// Creates a kernel +cl_kernel cl_createKernel(cl_program program, const char* kernelName); + + +// Sets a kernel argument +void cl_setKernelArg(cl_kernel kernel, unsigned int index, size_t size, + void* data); + + +//------------------------------------------------------- +// Profiling/events +//------------------------------------------------------- + +// Computes the execution time (start to end) for an event +double cl_computeExecTime(cl_event); + +// Compute the elapsed time between two CPU timer values +double cl_computeTime(cl_time start, cl_time end); + +// Creates an event from CPU timers +void cl_createUserEvent(cl_time start, cl_time end, char* desc); + +// Disable logging of events +void cl_disableEvents(); + +// Enable logging of events +void cl_enableEvents(); + +// Query the current system time +void cl_getTime(cl_time* time); + +// Calls a function which prints events to the terminal +void cl_printEvents(); + +// Calls a function which writes the events to a file +void cl_writeEventsToFile(char* path); + + +//------------------------------------------------------- +// Error handling +//------------------------------------------------------- + +// Compare a status value to CL_SUCCESS and optionally exit on error +int cl_errChk(const cl_int status, const char *msg, bool exitOnErr); + +// Queries the supported image formats for the device and prints +// them to the screen +void printSupportedImageFormats(); + +//------------------------------------------------------- +// Platform and device information +//------------------------------------------------------- + +bool cl_deviceIsAMD(cl_device_id dev=NULL); +bool cl_deviceIsNVIDIA(cl_device_id dev=NULL); +bool cl_platformIsNVIDIA(cl_platform_id plat=NULL); +char* cl_getDeviceDriverVersion(cl_device_id dev=NULL); +char* cl_getDeviceName(cl_device_id dev=NULL); +char* cl_getDeviceVendor(cl_device_id dev=NULL); +char* cl_getDeviceVersion(cl_device_id dev=NULL); +char* cl_getPlatformName(cl_platform_id platform); +char* cl_getPlatformVendor(cl_platform_id platform); + +//------------------------------------------------------- +// Utility functions +//------------------------------------------------------- + +char* catStringWithInt(const char* str, int integer); + +char* itoa_portable(int value, char* result, int base); + +//------------------------------------------------------- +// Data types +//------------------------------------------------------- +typedef struct{ + int x; + int y; +} int2; + +typedef struct{ + float x; + float y; +}float2; + +typedef struct{ + float x; + float y; + float z; + float w; +}float4; + +//------------------------------------------------------- +// Defines +//------------------------------------------------------- + +#define MAX_ERR_VAL 64 + +#define NUM_PROGRAMS 7 + +#define NUM_KERNELS 13 +#define KERNEL_INIT_DET 0 +#define KERNEL_BUILD_DET 1 +#define KERNEL_SURF_DESC 2 +#define KERNEL_NORM_DESC 3 +#define KERNEL_NON_MAX_SUP 4 +#define KERNEL_GET_ORIENT1 5 +#define KERNEL_GET_ORIENT2 6 +#define KERNEL_NN 7 +#define KERNEL_SCAN 8 +#define KERNEL_SCAN4 9 +#define KERNEL_TRANSPOSE 10 +#define KERNEL_SCANIMAGE 11 +#define KERNEL_TRANSPOSEIMAGE 12 + +#endif diff --git a/benchmarks/new_opencl/nearn/filelist.txt b/benchmarks/new_opencl/nearn/filelist.txt new file mode 100755 index 00000000..393d440b --- /dev/null +++ b/benchmarks/new_opencl/nearn/filelist.txt @@ -0,0 +1,4 @@ +cane4_0.db +cane4_1.db +cane4_2.db +cane4_3.db \ No newline at end of file diff --git a/benchmarks/new_opencl/nearn/ipoint.h b/benchmarks/new_opencl/nearn/ipoint.h new file mode 100755 index 00000000..3a56adae --- /dev/null +++ b/benchmarks/new_opencl/nearn/ipoint.h @@ -0,0 +1,29 @@ +/*********************************************************** +* --- OpenSURF --- * +* This library is distributed under the GNU GPL. Please * +* contact chris.evans@irisys.co.uk for more information. * +* * +* C. Evans, Research Into Robust Visual Features, * +* MSc University of Bristol, 2008. * +* * +************************************************************/ + +#ifndef IPOINT_H +#define IPOINT_H + +#include +#include + + + +//------------------------------------------------------- +typedef struct{ + int x; + int y; + float descriptor[64]; + } Ipoint; + +//------------------------------------------------------- + + typedef std::vector IpVec; +#endif diff --git a/benchmarks/new_opencl/nearn/kernel.cl b/benchmarks/new_opencl/nearn/kernel.cl new file mode 100755 index 00000000..42a70388 --- /dev/null +++ b/benchmarks/new_opencl/nearn/kernel.cl @@ -0,0 +1,22 @@ +//#pragma OPENCL EXTENSION cl_khr_byte_addressable_store : enable + +typedef struct latLong + { + float lat; + float lng; + } LatLong; + +__kernel void NearestNeighbor(__global LatLong *d_locations, + __global float *d_distances, + const int numRecords, + const float lat, + const float lng) { + int globalId = get_global_id(0); + + if (globalId < numRecords) { + __global LatLong *latLong = d_locations+globalId; + + __global float *dist=d_distances+globalId; + *dist = (float)sqrt((lat-latLong->lat)*(lat-latLong->lat)+(lng-latLong->lng)*(lng-latLong->lng)); + } +} \ No newline at end of file diff --git a/benchmarks/new_opencl/nearn/kernel.pocl b/benchmarks/new_opencl/nearn/kernel.pocl new file mode 100644 index 0000000000000000000000000000000000000000..72ca8cba4647f34e40938ba5d7c83d2a8aafaaf3 GIT binary patch literal 193922 zcmeFae|S~Zndraw*=O&4@`EI@LxPATutS2BQtYv&x6j<$a~yuCbp$&I+WHjfw$j?U z7wxprb~?9-J3jzHq8o`?Zv%ovosOe(rlxb-nIRR3wYG!~Bvc)N9!Rh{CbT4x06E{! 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+ float *recordDistances; + // LatLong locations[REC_WINDOW]; + std::vector locations; + int i; + // args + char filename[100]; + int resultsCount = 5, quiet = 0, timing = 0, platform = -1, device = -1; + float lat = 30, lng = 90; + + // parse command line + if (parseCommandline(argc, argv, filename, &resultsCount, &lat, &lng, &quiet, + &timing, &platform, &device)) { + printUsage(); + return 0; + } + + int numRecords = loadData(filename, records, locations); + + // for(i=0;i numRecords) + resultsCount = numRecords; + + context = cl_init_context(platform, device, quiet); + + recordDistances = OpenClFindNearestNeighbors(context, numRecords, locations, + lat, lng, timing); + + // find the resultsCount least distances + findLowest(records, recordDistances, numRecords, resultsCount); + + // print out results + if (!quiet) + for (i = 0; i < resultsCount; i++) { + printf("%s --> Distance=%f\n", records[i].recString, records[i].distance); + } + free(recordDistances); + return 0; +} + +float *OpenClFindNearestNeighbors(cl_context context, int numRecords, + std::vector &locations, float lat, + float lng, int timing) { + + // 1. set up kernel + cl_kernel NN_kernel; + cl_int status; + cl_program cl_NN_program; + cl_NN_program = cl_compileProgram((char *)"nearestNeighbor_kernel.cl", NULL); + + NN_kernel = clCreateKernel(cl_NN_program, "NearestNeighbor", &status); + status = + cl_errChk(status, (char *)"Error Creating Nearest Neighbor kernel", true); + if (status) + exit(1); + // 2. set up memory on device and send ipts data to device + // copy ipts(1,2) to device + // also need to alloate memory for the distancePoints + cl_mem d_locations; + cl_mem d_distances; + + cl_int error = 0; + + d_locations = clCreateBuffer(context, CL_MEM_READ_ONLY, + sizeof(LatLong) * numRecords, NULL, &error); + + d_distances = clCreateBuffer(context, CL_MEM_READ_WRITE, + sizeof(float) * numRecords, NULL, &error); + + cl_command_queue command_queue = cl_getCommandQueue(); + cl_event writeEvent, kernelEvent, readEvent; + error = clEnqueueWriteBuffer(command_queue, d_locations, + 1, // change to 0 for nonblocking write + 0, // offset + sizeof(LatLong) * numRecords, &locations[0], 0, + NULL, &writeEvent); + + // 3. send arguments to device + cl_int argchk; + argchk = clSetKernelArg(NN_kernel, 0, sizeof(cl_mem), (void *)&d_locations); + argchk |= clSetKernelArg(NN_kernel, 1, sizeof(cl_mem), (void *)&d_distances); + argchk |= clSetKernelArg(NN_kernel, 2, sizeof(int), (void *)&numRecords); + argchk |= clSetKernelArg(NN_kernel, 3, sizeof(float), (void *)&lat); + argchk |= clSetKernelArg(NN_kernel, 4, sizeof(float), (void *)&lng); + + cl_errChk(argchk, "ERROR in Setting Nearest Neighbor kernel args", true); + + // 4. enqueue kernel + size_t globalWorkSize[1]; + globalWorkSize[0] = numRecords; + if (numRecords % 64) + globalWorkSize[0] += 64 - (numRecords % 64); + // printf("Global Work Size: %zu\n",globalWorkSize[0]); + + error = clEnqueueNDRangeKernel(command_queue, NN_kernel, 1, 0, globalWorkSize, + NULL, 0, NULL, &kernelEvent); + + cl_errChk(error, "ERROR in Executing Kernel NearestNeighbor", true); + + // 5. transfer data off of device + + // create distances std::vector + float *distances = (float *)malloc(sizeof(float) * numRecords); + + error = clEnqueueReadBuffer(command_queue, d_distances, + 1, // change to 0 for nonblocking write + 0, // offset + sizeof(float) * numRecords, distances, 0, NULL, + &readEvent); + + cl_errChk(error, "ERROR with clEnqueueReadBuffer", true); + if (timing) { + clFinish(command_queue); + cl_ulong eventStart, eventEnd, totalTime = 0; + printf("# Records\tWrite(s) [size]\t\tKernel(s)\tRead(s) " + "[size]\t\tTotal(s)\n"); + printf("%d \t", numRecords); + // Write Buffer + error = clGetEventProfilingInfo(writeEvent, CL_PROFILING_COMMAND_START, + sizeof(cl_ulong), &eventStart, NULL); + cl_errChk(error, "ERROR in Event Profiling (Write Start)", true); + error = clGetEventProfilingInfo(writeEvent, CL_PROFILING_COMMAND_END, + sizeof(cl_ulong), &eventEnd, NULL); + cl_errChk(error, "ERROR in Event Profiling (Write End)", true); + + printf("%f [%.2fMB]\t", (float)((eventEnd - eventStart) / 1e9), + (float)((sizeof(LatLong) * numRecords) / 1e6)); + totalTime += eventEnd - eventStart; + // Kernel + error = clGetEventProfilingInfo(kernelEvent, CL_PROFILING_COMMAND_START, + sizeof(cl_ulong), &eventStart, NULL); + cl_errChk(error, "ERROR in Event Profiling (Kernel Start)", true); + error = clGetEventProfilingInfo(kernelEvent, CL_PROFILING_COMMAND_END, + sizeof(cl_ulong), &eventEnd, NULL); + cl_errChk(error, "ERROR in Event Profiling (Kernel End)", true); + + printf("%f\t", (float)((eventEnd - eventStart) / 1e9)); + totalTime += eventEnd - eventStart; + // Read Buffer + error = clGetEventProfilingInfo(readEvent, CL_PROFILING_COMMAND_START, + sizeof(cl_ulong), &eventStart, NULL); + cl_errChk(error, "ERROR in Event Profiling (Read Start)", true); + error = clGetEventProfilingInfo(readEvent, CL_PROFILING_COMMAND_END, + sizeof(cl_ulong), &eventEnd, NULL); + cl_errChk(error, "ERROR in Event Profiling (Read End)", true); + + printf("%f [%.2fMB]\t", (float)((eventEnd - eventStart) / 1e9), + (float)((sizeof(float) * numRecords) / 1e6)); + totalTime += eventEnd - eventStart; + + printf("%f\n\n", (float)(totalTime / 1e9)); + } + // 6. return finalized data and release buffers + clReleaseMemObject(d_locations); + clReleaseMemObject(d_distances); + return distances; +} + +int loadData(char *filename, std::vector &records, + std::vector &locations) { + FILE *flist, *fp; + int i = 0; + char dbname[64]; + int recNum = 0; + + /**Main processing **/ + + int q = 0; + + flist = fopen(filename, "r"); + while (!feof(flist)) { + /** + * Read in REC_WINDOW records of length REC_LENGTH + * If this is the last file in the filelist, then done + * else open next file to be read next iteration + */ + if (fscanf(flist, "%s\n", dbname) != 1) { + printf("error reading filelist\n"); + exit(0); + } + printf("loading db: %s\n", dbname); + fp = fopen(dbname, "r"); + if (!fp) { + printf("error opening a db\n"); + exit(1); + } + // read each record + while (!feof(fp)) { + Record record; + LatLong latLong; + fgets(record.recString, 49, fp); + fgetc(fp); // newline + if (feof(fp)) + break; + + // parse for lat and long + char substr[6]; + + for (i = 0; i < 5; i++) + substr[i] = *(record.recString + i + 28); + substr[5] = '\0'; + latLong.lat = atof(substr); + + for (i = 0; i < 5; i++) + substr[i] = *(record.recString + i + 33); + substr[5] = '\0'; + latLong.lng = atof(substr); + + locations.push_back(latLong); + records.push_back(record); + recNum++; + if (0 == (recNum % 500)) + break; + } + + if (++q == 3) + break; + fclose(fp); + } + fclose(flist); + return recNum; +} + +void findLowest(std::vector &records, float *distances, int numRecords, + int topN) { + int i, j; + float val; + int minLoc; + Record *tempRec; + float tempDist; + + for (i = 0; i < topN; i++) { + minLoc = i; + for (j = i; j < numRecords; j++) { + val = distances[j]; + if (val < distances[minLoc]) + minLoc = j; + } + // swap locations and distances + tempRec = &records[i]; + records[i] = records[minLoc]; + records[minLoc] = *tempRec; + + tempDist = distances[i]; + distances[i] = distances[minLoc]; + distances[minLoc] = tempDist; + + // add distance to the min we just found + records[i].distance = distances[i]; + } +} + +int parseCommandline(int argc, char *argv[], char *filename, int *r, float *lat, + float *lng, int *q, int *t, int *p, int *d) { + int i; + // if (argc < 2) return 1; // error + strncpy(filename, "filelist.txt", 100); + char flag; + + for (i = 1; i < argc; i++) { + if (argv[i][0] == '-') { // flag + flag = argv[i][1]; + switch (flag) { + case 'r': // number of results + i++; + *r = atoi(argv[i]); + break; + case 'l': // lat or lng + if (argv[i][2] == 'a') { // lat + *lat = atof(argv[i + 1]); + } else { // lng + *lng = atof(argv[i + 1]); + } + i++; + break; + case 'h': // help + return 1; + break; + case 'q': // quiet + *q = 1; + break; + case 't': // timing + *t = 1; + break; + case 'p': // platform + i++; + *p = atoi(argv[i]); + break; + case 'd': // device + i++; + *d = atoi(argv[i]); + break; + } + } + } + if ((*d >= 0 && *p < 0) || + (*p >= 0 && + *d < 0)) // both p and d must be specified if either are specified + return 1; + return 0; +} + +void printUsage() { + printf("Nearest Neighbor Usage\n"); + printf("\n"); + printf("nearestNeighbor [filename] -r [int] -lat [float] -lng [float] [-hqt] " + "[-p [int] -d [int]]\n"); + printf("\n"); + printf("example:\n"); + printf("$ ./nearestNeighbor filelist.txt -r 5 -lat 30 -lng 90\n"); + printf("\n"); + printf("filename the filename that lists the data input files\n"); + printf("-r [int] the number of records to return (default: 10)\n"); + printf("-lat [float] the latitude for nearest neighbors (default: 0)\n"); + printf("-lng [float] the longitude for nearest neighbors (default: 0)\n"); + printf("\n"); + printf("-h, --help Display the help file\n"); + printf("-q Quiet mode. Suppress all text output.\n"); + printf("-t Print timing information.\n"); + printf("\n"); + printf("-p [int] Choose the platform (must choose both platform and " + "device)\n"); + printf("-d [int] Choose the device (must choose both platform and " + "device)\n"); + printf("\n"); + printf("\n"); + printf("Notes: 1. The filename is required as the first parameter.\n"); + printf(" 2. If you declare either the device or the platform,\n"); + printf(" you must declare both.\n\n"); +} + +#endif diff --git a/benchmarks/new_opencl/nearn/nearestNeighbor.h b/benchmarks/new_opencl/nearn/nearestNeighbor.h new file mode 100755 index 00000000..3954a750 --- /dev/null +++ b/benchmarks/new_opencl/nearn/nearestNeighbor.h @@ -0,0 +1,50 @@ +#ifndef _NEARESTNEIGHBOR +#define _NEARESTNEIGHBOR + +#include +#include +#include +#include +#include +#include + +// All OpenCL headers +#if defined (__APPLE__) || defined(MACOSX) + #include +#else + #include +#endif + +#include "clutils.h" +//#include "utils.h" + +#include + + + +#define REC_LENGTH 49 // size of a record in db + +typedef struct latLong +{ + float lat; + float lng; +} LatLong; + +typedef struct record +{ + char recString[REC_LENGTH]; + float distance; +} Record; + +float *OpenClFindNearestNeighbors( + cl_context context, + int numRecords, + std::vector &locations,float lat,float lng, + int timing); + +int loadData(char *filename,std::vector &records,std::vector &locations); +void findLowest(std::vector &records,float *distances,int numRecords,int topN); +void printUsage(); +int parseCommandline(int argc, char *argv[], char* filename,int *r,float *lat,float *lng, + int *q, int *t, int *p, int *d); +#endif diff --git a/benchmarks/new_opencl/nearn/run b/benchmarks/new_opencl/nearn/run new file mode 100755 index 00000000..e4d2f27e --- /dev/null +++ b/benchmarks/new_opencl/nearn/run @@ -0,0 +1 @@ +./nn filelist.txt -r 5 -lat 30 -lng 90 \ No newline at end of file diff --git a/benchmarks/new_opencl/nearn/utils.cpp b/benchmarks/new_opencl/nearn/utils.cpp new file mode 100755 index 00000000..b0f9115f --- /dev/null +++ b/benchmarks/new_opencl/nearn/utils.cpp @@ -0,0 +1,204 @@ +/****************************************************************************\ + * Copyright (c) 2011, Advanced Micro Devices, Inc. * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or without * + * modification, are permitted provided that the following conditions * + * are met: * + * * + * Redistributions of source code must retain the above copyright notice, * + * this list of conditions and the following disclaimer. * + * * + * Redistributions in binary form must reproduce the above copyright notice, * + * this list of conditions and the following disclaimer in the documentation * + * and/or other materials provided with the distribution. * + * * + * Neither the name of the copyright holder nor the names of its contributors * + * may be used to endorse or promote products derived from this software * + * without specific prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * + * * + * If you use the software (in whole or in part), you shall adhere to all * + * applicable U.S., European, and other export laws, including but not * + * limited to the U.S. Export Administration Regulations (“EAR”), (15 C.F.R. * + * Sections 730 through 774), and E.U. Council Regulation (EC) No 1334/2000 * + * of 22 June 2000. Further, pursuant to Section 740.6 of the EAR, you * + * hereby certify that, except pursuant to a license granted by the United * + * States Department of Commerce Bureau of Industry and Security or as * + * otherwise permitted pursuant to a License Exception under the U.S. Export * + * Administration Regulations ("EAR"), you will not (1) export, re-export or * + * release to a national of a country in Country Groups D:1, E:1 or E:2 any * + * restricted technology, software, or source code you receive hereunder, * + * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such * + * technology or software, if such foreign produced direct product is subject * + * to national security controls as identified on the Commerce Control List * + *(currently found in Supplement 1 to Part 774 of EAR). For the most current * + * Country Group listings, or for additional information about the EAR or * + * your obligations under those regulations, please refer to the U.S. Bureau * + * of Industry and Security’s website at http://www.bis.doc.gov/. * + \****************************************************************************/ + +#include +#include +#include +#include + +#include "utils.h" + +static bool usingImages = true; + +//! A wrapper for malloc that checks the return value +void* alloc(size_t size) { + + void* ptr = NULL; + ptr = malloc(size); + if(ptr == NULL) { + perror("malloc"); + exit(-1); + } + + return ptr; +} + +// This function checks to make sure a file exists before we open it +void checkFile(char* filename) +{ + + struct stat fileStatus; + if(stat(filename, &fileStatus) != 0) { + printf("Error opening file: %s\n", filename); + exit(-1); + } + else { + if(!(S_IFREG & fileStatus.st_mode)) { + printf("File %s is not a regular file\n", filename); + exit(-1); + } + } +} + + +// This function checks to make sure a directory exists +void checkDir(char* dirpath) +{ + + struct stat fileStatus; + if(stat(dirpath, &fileStatus) != 0) { + printf("Directory does not exist: %s\n", dirpath); + exit(-1); + } + else { + if(!(S_IFDIR & fileStatus.st_mode)) { + printf("Directory was not provided: %s\n", dirpath); + exit(-1); + } + } +} + +// Parse the command line arguments +void parseArguments(int argc, char** argv, char** input, char** events, + char** ipts, char* devicePref, bool* verifyResults) +{ + + for(int i = 2; i < argc; i++) { + if(strcmp(argv[i], "-d") == 0) { // Event dump found + if(i == argc-1) { + printf("Usage: -e Needs directory path\n"); + exit(-1); + } + devicePref[0] = argv[i+1][0]; + i++; + continue; + } + if(strcmp(argv[i], "-e") == 0) { // Event dump found + if(i == argc-1) { + printf("Usage: -e Needs directory path\n"); + exit(-1); + } + *events = argv[i+1]; + i++; + continue; + } + if(strcmp(argv[i], "-i") == 0) { // Input found + if(i == argc-1) { + printf("Usage: -i Needs directory path\n"); + exit(-1); + } + *input = argv[i+1]; + i++; + continue; + } + if(strcmp(argv[i], "-l") == 0) { // Ipts dump found + if(i == argc-1) { + printf("Usage: -l Needs directory path\n"); + exit(-1); + } + *ipts = argv[i+1]; + i++; + continue; + } + if(strcmp(argv[i], "-n") == 0) { // Don't use OpenCL images + setUsingImages(false); + continue; + } + if(strcmp(argv[i], "-v") == 0) { // Verify results + *verifyResults = true; + continue; + } + } +} + + +// This function that takes a positive integer 'value' and returns +// the nearest multiple of 'multiple' (used for padding columns) +unsigned int roundUp(unsigned int value, unsigned int multiple) { + + unsigned int remainder = value % multiple; + + // Make the value a multiple of multiple + if(remainder != 0) { + value += (multiple-remainder); + } + + return value; +} + + +// Concatenate two strings and return a pointer to the new string +char* smartStrcat(char* str1, char* str2) +{ + char* newStr = NULL; + + newStr = (char*)alloc((strlen(str1)+strlen(str2)+1)*sizeof(char)); + + strcpy(newStr, str1); + strcat(newStr, str2); + + return newStr; +} + + +// Set the value of using images to true if they are being +// used, or false if they are not +void setUsingImages(bool val) +{ + usingImages = val; +} + + +// Return whether or not images are being used +bool isUsingImages() +{ + return usingImages; +} diff --git a/benchmarks/new_opencl/nearn/utils.h b/benchmarks/new_opencl/nearn/utils.h new file mode 100755 index 00000000..1e901ced --- /dev/null +++ b/benchmarks/new_opencl/nearn/utils.h @@ -0,0 +1,84 @@ +/****************************************************************************\ + * Copyright (c) 2011, Advanced Micro Devices, Inc. * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or without * + * modification, are permitted provided that the following conditions * + * are met: * + * * + * Redistributions of source code must retain the above copyright notice, * + * this list of conditions and the following disclaimer. * + * * + * Redistributions in binary form must reproduce the above copyright notice, * + * this list of conditions and the following disclaimer in the documentation * + * and/or other materials provided with the distribution. * + * * + * Neither the name of the copyright holder nor the names of its contributors * + * may be used to endorse or promote products derived from this software * + * without specific prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * + * * + * If you use the software (in whole or in part), you shall adhere to all * + * applicable U.S., European, and other export laws, including but not * + * limited to the U.S. Export Administration Regulations (“EAR”), (15 C.F.R. * + * Sections 730 through 774), and E.U. Council Regulation (EC) No 1334/2000 * + * of 22 June 2000. Further, pursuant to Section 740.6 of the EAR, you * + * hereby certify that, except pursuant to a license granted by the United * + * States Department of Commerce Bureau of Industry and Security or as * + * otherwise permitted pursuant to a License Exception under the U.S. Export * + * Administration Regulations ("EAR"), you will not (1) export, re-export or * + * release to a national of a country in Country Groups D:1, E:1 or E:2 any * + * restricted technology, software, or source code you receive hereunder, * + * or (2) export to Country Groups D:1, E:1 or E:2 the direct product of such * + * technology or software, if such foreign produced direct product is subject * + * to national security controls as identified on the Commerce Control List * + *(currently found in Supplement 1 to Part 774 of EAR). For the most current * + * Country Group listings, or for additional information about the EAR or * + * your obligations under those regulations, please refer to the U.S. Bureau * + * of Industry and Security’s website at http://www.bis.doc.gov/. * + \****************************************************************************/ + +#ifndef _UTILS_ +#define _UTILS_ + +// Wrapper for malloc +void* alloc(size_t size); + +// Checks for existence of directory +void checkDir(char* dirpath); + +// Check for existence of file +void checkFile(char* filename); + +// Parse the input command line options to the program +void parseArguments(int argc, char** argv, char** input, char** events, + char** ipts, char* devicePref, bool* verifyResults); + + +// Print the program usage information +void printUsage(); + +// Rounds up size to the nearest multiple of multiple +unsigned int roundUp(unsigned int value, unsigned int multiple); + +// Concatenate two strings, creating a new one +char* smartStrcat(char* str1, char* str2); + +// Set the value of usingImages +void setUsingImages(bool val); + +// Return whether or not images are being used +bool isUsingImages(); + +#endif diff --git a/benchmarks/new_opencl/results.txt b/benchmarks/new_opencl/results.txt new file mode 100644 index 00000000..54e40ece --- /dev/null +++ b/benchmarks/new_opencl/results.txt @@ -0,0 +1,7 @@ +# Dynamic Instructions: -1 +# of total cycles: 2519 +# of forwarding stalls: 0 +# of branch stalls: 0 +# CPI: -2519 +# time to simulate: 4.94066e-323 milliseconds +# GRADE: Failed on test: 0 diff --git a/benchmarks/new_opencl/saxpy/Makefile b/benchmarks/new_opencl/saxpy/Makefile new file mode 100644 index 00000000..6a90cbf8 --- /dev/null +++ b/benchmarks/new_opencl/saxpy/Makefile @@ -0,0 +1,44 @@ +RISCV_TOOL_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) +POCLCC_PATH ?= $(wildcard ~/dev/pocl/drops_vortex_cc) +POCLRT_PATH ?= $(wildcard ..) +DRIVER_PATH ?= $(wildcard ../../../driver/sw) + +CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I$(POCLRT_PATH)/include + +LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex + +PROJECT = saxpy + +SRCS = main.cc + +all: $(PROJECT) + +kernel.pocl: kernel.cl + POCL_DEBUG=all POCL_DEBUG_LLVM_PASSES=1 LD_LIBRARY_PATH=$(RISCV_TOOL_PATH)/lib:$(POCLCC_PATH)/lib:$(DRIVER_PATH)/simx $(POCLCC_PATH)/bin/poclcc -o kernel.pocl kernel.cl + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +run-fpga: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-ase: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-simx: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-rtlsim: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/benchmarks/new_opencl/saxpy/README b/benchmarks/new_opencl/saxpy/README new file mode 100644 index 00000000..e69de29b diff --git a/benchmarks/new_opencl/saxpy/kernel.cl b/benchmarks/new_opencl/saxpy/kernel.cl new file mode 100644 index 00000000..97c903c5 --- /dev/null +++ b/benchmarks/new_opencl/saxpy/kernel.cl @@ -0,0 +1,5 @@ +__kernel void saxpy(__global float *src, __global float *dst, float factor) +{ + long i = get_global_id(0); + dst[i] += src[i] * factor; +} diff --git a/benchmarks/new_opencl/saxpy/kernel.pocl b/benchmarks/new_opencl/saxpy/kernel.pocl new file mode 100644 index 0000000000000000000000000000000000000000..4883291ea924dcfd5c757c420286ba2743286952 GIT binary patch literal 185600 zcmeFaeS8$xmFHd6)m_zkL6RvUFvdtwdclMcoOY~iKC_!{hZo!N7?K5KCw_uSIVLZ& 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b/benchmarks/new_opencl/saxpy/main.cc new file mode 100644 index 00000000..dd952d46 --- /dev/null +++ b/benchmarks/new_opencl/saxpy/main.cc @@ -0,0 +1,221 @@ +/* + * Simple OpenCL demo program + * + * Copyright (C) 2009 Clifford Wolf + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * gcc -o cldemo -std=gnu99 -Wall -I/usr/include/nvidia-current cldemo.c + * -lOpenCL + * + */ + +#include +#include +#include +#include +#include +#include +#include + +//#define NUM_DATA 65536 +#define NUM_DATA 4096 + +#define CL_CHECK(_expr) \ + do { \ + cl_int _err = _expr; \ + if (_err == CL_SUCCESS) \ + break; \ + fprintf(stderr, "OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + abort(); \ + } while (0) + +#define CL_CHECK_ERR(_expr) \ + ({ \ + cl_int _err = CL_INVALID_VALUE; \ + decltype(_expr) _ret = _expr; \ + if (_err != CL_SUCCESS) { \ + fprintf(stderr, "OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + abort(); \ + } \ + _ret; \ + }) + +void pfn_notify(const char *errinfo, const void *private_info, size_t cb, + void *user_data) { + fprintf(stderr, "OpenCL Error (via pfn_notify): %s\n", errinfo); +} + +static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) { + if (nullptr == filename || nullptr == data || 0 == size) + return -1; + + FILE* fp = fopen(filename, "r"); + if (NULL == fp) { + fprintf(stderr, "Failed to load kernel."); + return -1; + } + fseek(fp , 0 , SEEK_END); + long fsize = ftell(fp); + rewind(fp); + + *data = (uint8_t*)malloc(fsize); + *size = fread(*data, 1, fsize, fp); + + fclose(fp); + + return 0; +} + +uint8_t *kernel_bin = NULL; + +/// +// Cleanup any created OpenCL resources +// +void Cleanup(cl_context context, cl_command_queue commandQueue, + cl_program program, cl_kernel kernel, cl_mem memObjects[3]) { + for (int i = 0; i < 3; i++) { + if (memObjects[i] != 0) + clReleaseMemObject(memObjects[i]); + } + if (commandQueue != 0) + clReleaseCommandQueue(commandQueue); + + if (kernel != 0) + clReleaseKernel(kernel); + + if (program != 0) + clReleaseProgram(program); + + if (context != 0) + clReleaseContext(context); + + if (kernel_bin) free(kernel_bin); +} + +int main(int argc, char **argv) { + printf("enter demo main\n"); + + cl_platform_id platform_id; + cl_device_id device_id; + size_t kernel_size; + cl_int binary_status = 0; + int i; + + // read kernel binary from file + if (0 != read_kernel_file("kernel.pocl", &kernel_bin, &kernel_size)) + return -1; + + // Getting platform and device information + CL_CHECK(clGetPlatformIDs(1, &platform_id, NULL)); + CL_CHECK(clGetDeviceIDs(platform_id, CL_DEVICE_TYPE_DEFAULT, 1, &device_id, NULL)); + + cl_context context; + context = CL_CHECK_ERR(clCreateContext(NULL, 1, &device_id, &pfn_notify, NULL, &_err)); + + cl_command_queue queue; + queue = CL_CHECK_ERR(clCreateCommandQueue(context, device_id, CL_QUEUE_PROFILING_ENABLE, &_err)); + + cl_kernel kernel = 0; + cl_mem memObjects[2] = {0, 0}; + + // Create OpenCL program - first attempt to load cached binary. + // If that is not available, then create the program from source + // and store the binary for future use. + std::cout << "Attempting to create program from binary..." << std::endl; + cl_program program = CL_CHECK_ERR(clCreateProgramWithBinary( + context, 1, &device_id, &kernel_size, &kernel_bin, &binary_status, &_err)); + if (program == NULL) { + std::cerr << "Failed to write program binary" << std::endl; + Cleanup(context, queue, program, kernel, memObjects); + return 1; + } else { + std::cout << "Read program from binary." << std::endl; + } + + // Build program + CL_CHECK(clBuildProgram(program, 1, &device_id, NULL, NULL, NULL)); + + printf("attempting to create input buffer\n"); + fflush(stdout); + cl_mem input_buffer; + input_buffer = CL_CHECK_ERR(clCreateBuffer( + context, CL_MEM_READ_ONLY, sizeof(float) * NUM_DATA, NULL, &_err)); + + printf("attempting to create output buffer\n"); + fflush(stdout); + cl_mem output_buffer; + output_buffer = CL_CHECK_ERR(clCreateBuffer( + context, CL_MEM_WRITE_ONLY, sizeof(float) * NUM_DATA, NULL, &_err)); + + memObjects[0] = input_buffer; + memObjects[1] = output_buffer; + + float factor = ((float)rand() / (float)(RAND_MAX)) * 100.0; + + printf("attempting to create kernel\n"); + fflush(stdout); + kernel = CL_CHECK_ERR(clCreateKernel(program, "saxpy", &_err)); + printf("setting up kernel args cl_mem:%lx \n", input_buffer); + fflush(stdout); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(input_buffer), &input_buffer)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(output_buffer), &output_buffer)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(factor), &factor)); + + printf("attempting to enqueue write buffer\n"); + fflush(stdout); + for (int i = 0; i < NUM_DATA; i++) { + float in = ((float)rand() / (float)(RAND_MAX)) * 100.0; + CL_CHECK(clEnqueueWriteBuffer(queue, input_buffer, CL_TRUE, + i * sizeof(float), 4, &in, 0, NULL, NULL)); + } + + cl_event kernel_completion; + size_t global_work_size[] = {NUM_DATA/2,NUM_DATA/2}; + printf("attempting to enqueue kernel\n"); + fflush(stdout); + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, global_work_size, + NULL, 0, NULL, &kernel_completion)); + printf("Enqueue'd kerenel\n"); + fflush(stdout); + cl_ulong time_start, time_end; + CL_CHECK(clWaitForEvents(1, &kernel_completion)); + CL_CHECK(clGetEventProfilingInfo(kernel_completion, + CL_PROFILING_COMMAND_START, + sizeof(time_start), &time_start, NULL)); + CL_CHECK(clGetEventProfilingInfo(kernel_completion, CL_PROFILING_COMMAND_END, + sizeof(time_end), &time_end, NULL)); + double elapsed = time_end - time_start; + printf("time(ns):%lg\n", elapsed); + CL_CHECK(clReleaseEvent(kernel_completion)); + + printf("Result:"); + for (int i = 0; i < NUM_DATA; i++) { + float data; + CL_CHECK(clEnqueueReadBuffer(queue, output_buffer, CL_TRUE, + i * sizeof(float), 4, &data, 0, NULL, NULL)); + // printf(" %f", data); + } + printf("\n"); + + CL_CHECK(clReleaseMemObject(memObjects[0])); + CL_CHECK(clReleaseMemObject(memObjects[1])); + + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(program)); + CL_CHECK(clReleaseContext(context)); + + return 0; +} diff --git a/benchmarks/new_opencl/sfilter/Makefile b/benchmarks/new_opencl/sfilter/Makefile new file mode 100644 index 00000000..89f710e8 --- /dev/null +++ b/benchmarks/new_opencl/sfilter/Makefile @@ -0,0 +1,44 @@ +RISCV_TOOL_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) +POCLCC_PATH ?= $(wildcard ~/dev/pocl/drops_vortex_cc) +POCLRT_PATH ?= $(wildcard ..) +DRIVER_PATH ?= $(wildcard ../../../driver/sw) + +CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I$(POCLRT_PATH)/include + +LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex + +PROJECT = sfilter + +SRCS = main.cc + +all: $(PROJECT) + +kernel.pocl: kernel.cl + POCL_DEBUG=all POCL_DEBUG_LLVM_PASSES=1 LD_LIBRARY_PATH=$(RISCV_TOOL_PATH)/lib:$(POCLCC_PATH)/lib:$(DRIVER_PATH)/simx $(POCLCC_PATH)/bin/poclcc -o kernel.pocl kernel.cl + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +run-fpga: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-ase: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-simx: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-rtlsim: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/benchmarks/new_opencl/sfilter/README b/benchmarks/new_opencl/sfilter/README new file mode 100644 index 00000000..e69de29b diff --git a/benchmarks/new_opencl/sfilter/kernel.cl b/benchmarks/new_opencl/sfilter/kernel.cl new file mode 100644 index 00000000..afa26ac6 --- /dev/null +++ b/benchmarks/new_opencl/sfilter/kernel.cl @@ -0,0 +1,21 @@ +// m0 m1 m2 +// m3 m4 m5 +// m6 m7 m8 +__kernel void sfilter(__global float *src, __global float *dst, long ldc, + float m0, float m1, float m2, float m3, float m4, float m5, float m6, float m7, float m8) +{ + long x = get_global_id(0); + long y = get_global_id(1); + + float i0 = src[(x-1)+(y-1)*ldc]*m0; + float i1 = src[(x) +(y-1)*ldc]*m1; + float i2 = src[(x+1)+(y-1)*ldc]*m2; + float i3 = src[(x-1)+(y) *ldc]*m3; + float i4 = src[(x) + y * ldc]*m4; + float i5 = src[(x+1)+(y) *ldc]*m5; + float i6 = src[(x-1)+(y+1)*ldc]*m6; + float i7 = src[(x) +(y+1)*ldc]*m7; + float i8 = src[(x+1)+(y+1)*ldc]*m8; + + dst[x+y*ldc] = i0 + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8; +} diff --git a/benchmarks/new_opencl/sfilter/kernel.pocl b/benchmarks/new_opencl/sfilter/kernel.pocl new file mode 100644 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program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * gcc -o cldemo -std=gnu99 -Wall -I/usr/include/nvidia-current cldemo.c + * -lOpenCL + * + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NUM_DATA 66 + +#define CL_CHECK(_expr) \ + do { \ + cl_int _err = _expr; \ + if (_err == CL_SUCCESS) \ + break; \ + fprintf(stderr, "OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + abort(); \ + } while (0) + +#define CL_CHECK_ERR(_expr) \ + ({ \ + cl_int _err = CL_INVALID_VALUE; \ + decltype(_expr) _ret = _expr; \ + if (_err != CL_SUCCESS) { \ + fprintf(stderr, "OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + abort(); \ + } \ + _ret; \ + }) + +void pfn_notify(const char *errinfo, const void *private_info, size_t cb, + void *user_data) { + fprintf(stderr, "OpenCL Error (via pfn_notify): %s\n", errinfo); +} + +static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) { + if (nullptr == filename || nullptr == data || 0 == size) + return -1; + + FILE* fp = fopen(filename, "r"); + if (NULL == fp) { + fprintf(stderr, "Failed to load kernel."); + return -1; + } + fseek(fp , 0 , SEEK_END); + long fsize = ftell(fp); + rewind(fp); + + *data = (uint8_t*)malloc(fsize); + *size = fread(*data, 1, fsize, fp); + + fclose(fp); + + return 0; +} + +uint8_t *kernel_bin = NULL; + +// inlcude pocl float to half conversions +typedef union { + int32_t i; + float f; +} FloatConvUnion; +cl_half poclu_float_to_cl_half(float value) { + FloatConvUnion u; + u.f = value; + cl_half half = (u.i >> 16) & 0x8000; // sign + cl_half fraction = + (u.i >> 12) & 0x007ff; // fraction with extra bit for rounding + cl_half exponent = (u.i >> 23) & 0xff; // exponent + + if (exponent < 0x0067) // Return signed zero if zero or value is too small for + // denormal half + return half; + + if (exponent > 0x008e) { // value was NaN or Inf + half |= 0x7c00u; // Make into inf + half |= exponent == 255 && + (u.i & 0x007fffffu); // If value was NaN make this into NaN + return half; + } + + if (exponent < 0x0071) { // Denormal + fraction |= 0x0800u; + + // rounding + half |= (fraction >> (0x0072 - exponent)) + + ((fraction >> (0x0071 - exponent)) & 1); + return half; + } + + half |= ((exponent - 0x0070) << 10) | (fraction >> 1); + half += fraction & 1; // rounding + return half; +} +#ifndef INFINITY +#define INFINITY 1.0 / 0.0 +#endif + +#ifndef NAN +#define NAN 0.0 / 0.0 +#endif + +float poclu_cl_half_to_float(cl_half value) { + if (value == 0xFC00) { + return -INFINITY; + } + if (value == 0x7C00) { + return INFINITY; + } + + int sgn = ((value & 0x8000) >> 15); + int exp = (value & 0x7C00) >> 10; + int mant = value & 0x03FF; + + if (exp == 0x1F && mant != 0) { + return NAN; + } + + float v = (exp == 0) ? mant : mant | 0x0400; // 1.x if not denormal + v /= 0x400; + float mul = exp2((float)exp - 15); + v *= mul; + if (sgn) { + v *= -1; + } + return v; +} + +/// +// Cleanup any created OpenCL resources +// +void Cleanup(cl_context context, cl_command_queue commandQueue, + cl_program program, cl_kernel kernel, cl_mem memObjects[3]) { + for (int i = 0; i < 3; i++) { + if (memObjects[i] != 0) + clReleaseMemObject(memObjects[i]); + } + if (commandQueue != 0) + clReleaseCommandQueue(commandQueue); + + if (kernel != 0) + clReleaseKernel(kernel); + + if (program != 0) + clReleaseProgram(program); + + if (context != 0) + clReleaseContext(context); + + if (kernel_bin) free(kernel_bin); +} + +int main(int argc, char **argv) { + printf("enter demo main\n"); + + cl_platform_id platform_id; + cl_device_id device_id; + size_t kernel_size; + cl_int binary_status = 0; + int i; + + // read kernel binary from file + if (0 != read_kernel_file("kernel.pocl", &kernel_bin, &kernel_size)) + return -1; + + // Getting platform and device information + CL_CHECK(clGetPlatformIDs(1, &platform_id, NULL)); + CL_CHECK(clGetDeviceIDs(platform_id, CL_DEVICE_TYPE_DEFAULT, 1, &device_id, NULL)); + + cl_context context; + context = CL_CHECK_ERR(clCreateContext(NULL, 1, &device_id, &pfn_notify, NULL, &_err)); + + cl_command_queue queue; + queue = CL_CHECK_ERR(clCreateCommandQueue(context, device_id, CL_QUEUE_PROFILING_ENABLE, &_err)); + + cl_kernel kernel = 0; + cl_mem memObjects[2] = {0, 0}; + + // Create OpenCL program - first attempt to load cached binary. + // If that is not available, then create the program from source + // and store the binary for future use. + std::cout << "Attempting to create program from binary..." << std::endl; + cl_program program = CL_CHECK_ERR(clCreateProgramWithBinary( + context, 1, &device_id, &kernel_size, &kernel_bin, &binary_status, &_err)); + if (program == NULL) { + std::cerr << "Failed to write program binary" << std::endl; + Cleanup(context, queue, program, kernel, memObjects); + return 1; + } else { + std::cout << "Read program from binary." << std::endl; + } + + // Build program + CL_CHECK(clBuildProgram(program, 1, &device_id, NULL, NULL, NULL)); + + printf("attempting to create input buffer\n"); + fflush(stdout); + cl_mem input_buffer; + input_buffer = CL_CHECK_ERR( + clCreateBuffer(context, CL_MEM_READ_ONLY, + sizeof(float) * NUM_DATA * NUM_DATA, NULL, &_err)); + + printf("attempting to create output buffer\n"); + fflush(stdout); + cl_mem output_buffer; + output_buffer = CL_CHECK_ERR( + clCreateBuffer(context, CL_MEM_WRITE_ONLY, + sizeof(float) * NUM_DATA * NUM_DATA, NULL, &_err)); + + memObjects[0] = input_buffer; + memObjects[1] = output_buffer; + + long long ldc = NUM_DATA; + + float m0 = 1.0; + float m1 = 1.0; + float m2 = 1.0; + float m3 = 1.0; + float m4 = 1.0; + float m5 = 1.0; + float m6 = 1.0; + float m7 = 1.0; + float m8 = 1.0; + + printf("attempting to create kernel\n"); + fflush(stdout); + kernel = CL_CHECK_ERR(clCreateKernel(program, "sfilter", &_err)); + printf("setting up kernel args cl_mem:%lx \n", input_buffer); + fflush(stdout); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(input_buffer), &input_buffer)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(output_buffer), &output_buffer)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(ldc), (&ldc))); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(m0), (&m0))); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(m1), (&m1))); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(m2), (&m2))); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(m3), (&m3))); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(m4), (&m4))); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(m5), (&m5))); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(m6), (&m6))); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(m7), (&m7))); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(m8), (&m8))); + + printf("attempting to enqueue write buffer\n"); + fflush(stdout); + for (int i = 0; i < NUM_DATA * NUM_DATA; i++) { + float in = ((float)rand() / (float)(RAND_MAX)) * 100.0; + CL_CHECK(clEnqueueWriteBuffer(queue, input_buffer, CL_TRUE, + i * sizeof(float), 4, &in, 0, NULL, NULL)); + } + + cl_event kernel_completion; + size_t global_offset[2] = {1, 1}; + size_t global_work_size[2] = {NUM_DATA - 2, NUM_DATA - 2}; // avoid the edges + const size_t local_work_size[2] = {64, 1}; + printf("attempting to enqueue kernel\n"); + fflush(stdout); + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 2, global_offset, + global_work_size, local_work_size, 0, NULL, + &kernel_completion)); + printf("Enqueue'd kerenel\n"); + fflush(stdout); + cl_ulong time_start, time_end; + CL_CHECK(clWaitForEvents(1, &kernel_completion)); + CL_CHECK(clGetEventProfilingInfo(kernel_completion, + CL_PROFILING_COMMAND_START, + sizeof(time_start), &time_start, NULL)); + CL_CHECK(clGetEventProfilingInfo(kernel_completion, CL_PROFILING_COMMAND_END, + sizeof(time_end), &time_end, NULL)); + double elapsed = time_end - time_start; + printf("time(ns):%lg\n", elapsed); + CL_CHECK(clReleaseEvent(kernel_completion)); + + printf("Result:"); + for (int i = 0; i < NUM_DATA * NUM_DATA; i++) { + float data; + CL_CHECK(clEnqueueReadBuffer(queue, output_buffer, CL_TRUE, + i * sizeof(float), 4, &data, 0, NULL, NULL)); + // printf(" %f", data); + } + printf("\n"); + + CL_CHECK(clReleaseMemObject(memObjects[0])); + CL_CHECK(clReleaseMemObject(memObjects[1])); + + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(program)); + CL_CHECK(clReleaseContext(context)); + + return 0; +} diff --git a/benchmarks/new_opencl/sgemm/Makefile b/benchmarks/new_opencl/sgemm/Makefile new file mode 100644 index 00000000..95f0f290 --- /dev/null +++ b/benchmarks/new_opencl/sgemm/Makefile @@ -0,0 +1,44 @@ +RISCV_TOOL_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) +POCLCC_PATH ?= $(wildcard ~/dev/pocl/drops_vortex_cc) +POCLRT_PATH ?= $(wildcard ..) +DRIVER_PATH ?= $(wildcard ../../../driver/sw) + +CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I$(POCLRT_PATH)/include + +LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex + +PROJECT = sgemm + +SRCS = main.cc + +all: $(PROJECT) + +kernel.pocl: kernel.cl + POCL_DEBUG=all POCL_DEBUG_LLVM_PASSES=1 LD_LIBRARY_PATH=$(RISCV_TOOL_PATH)/lib:$(POCLCC_PATH)/lib:$(DRIVER_PATH)/simx $(POCLCC_PATH)/bin/poclcc -o kernel.pocl kernel.cl + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +run-fpga: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-ase: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-simx: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-rtlsim: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/benchmarks/new_opencl/sgemm/README b/benchmarks/new_opencl/sgemm/README new file mode 100644 index 00000000..e69de29b diff --git a/benchmarks/new_opencl/sgemm/kernel.cl b/benchmarks/new_opencl/sgemm/kernel.cl new file mode 100644 index 00000000..17ece1d1 --- /dev/null +++ b/benchmarks/new_opencl/sgemm/kernel.cl @@ -0,0 +1,9 @@ +__kernel void sgemm(__global float *A, __global float *B, __global float *C, int ldc) +{ + long i = get_global_id(0); + long m = get_global_id(1); + long n = get_global_id(2); + float a = A[m+n*ldc]; + float b = B[m*ldc+i]; + C[i+n*ldc] = C[i+n*ldc] + a * b; +} diff --git a/benchmarks/new_opencl/sgemm/kernel.pocl b/benchmarks/new_opencl/sgemm/kernel.pocl new file mode 100644 index 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Copyright (C) 2009 Clifford Wolf + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * gcc -o cldemo -std=gnu99 -Wall -I/usr/include/nvidia-current cldemo.c + * -lOpenCL + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NUM_DATA 64 + +#define CL_CHECK(_expr) \ + do { \ + cl_int _err = _expr; \ + if (_err == CL_SUCCESS) \ + break; \ + fprintf(stderr, "OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + abort(); \ + } while (0) + +#define CL_CHECK_ERR(_expr) \ + ({ \ + cl_int _err = CL_INVALID_VALUE; \ + decltype(_expr) _ret = _expr; \ + if (_err != CL_SUCCESS) { \ + fprintf(stderr, "OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + abort(); \ + } \ + _ret; \ + }) + +void pfn_notify(const char *errinfo, const void *private_info, size_t cb, + void *user_data) { + fprintf(stderr, "OpenCL Error (via pfn_notify): %s\n", errinfo); +} + +static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) { + if (nullptr == filename || nullptr == data || 0 == size) + return -1; + + FILE* fp = fopen(filename, "r"); + if (NULL == fp) { + fprintf(stderr, "Failed to load kernel."); + return -1; + } + fseek(fp , 0 , SEEK_END); + long fsize = ftell(fp); + rewind(fp); + + *data = (uint8_t*)malloc(fsize); + *size = fread(*data, 1, fsize, fp); + + fclose(fp); + + return 0; +} + +uint8_t *kernel_bin = NULL; + +/// +// Cleanup any created OpenCL resources +// +void Cleanup(cl_context context, cl_command_queue commandQueue, + cl_program program, cl_kernel kernel, cl_mem memObjects[3]) { + for (int i = 0; i < 3; i++) { + if (memObjects[i] != 0) + clReleaseMemObject(memObjects[i]); + } + if (commandQueue != 0) + clReleaseCommandQueue(commandQueue); + + if (kernel != 0) + clReleaseKernel(kernel); + + if (program != 0) + clReleaseProgram(program); + + if (context != 0) + clReleaseContext(context); + + if (kernel_bin) free(kernel_bin); +} + +int main(int argc, char **argv) { + printf("enter demo main\n"); + + cl_platform_id platform_id; + cl_device_id device_id; + size_t kernel_size; + cl_int binary_status = 0; + int i; + + // read kernel binary from file + if (0 != read_kernel_file("kernel.pocl", &kernel_bin, &kernel_size)) + return -1; + + // Getting platform and device information + CL_CHECK(clGetPlatformIDs(1, &platform_id, NULL)); + CL_CHECK(clGetDeviceIDs(platform_id, CL_DEVICE_TYPE_DEFAULT, 1, &device_id, NULL)); + + cl_context context; + context = CL_CHECK_ERR( + clCreateContext(NULL, 1, &device_id, &pfn_notify, NULL, &_err)); + + cl_command_queue queue; + queue = CL_CHECK_ERR(clCreateCommandQueue(context, device_id, + CL_QUEUE_PROFILING_ENABLE, &_err)); + + cl_kernel kernel = 0; + cl_mem memObjects[3] = {0, 0, 0}; + + // Create OpenCL program - first attempt to load cached binary. + // If that is not available, then create the program from source + // and store the binary for future use. + std::cout << "Attempting to create program from binary..." << std::endl; + // cl_program program = CreateProgramFromBinary(context, device_id, + // "kernel.cl.bin"); + cl_program program = CL_CHECK_ERR(clCreateProgramWithBinary( + context, 1, &device_id, &kernel_size, &kernel_bin, &binary_status, &_err)); + if (program == NULL) { + std::cerr << "Failed to write program binary" << std::endl; + Cleanup(context, queue, program, kernel, memObjects); + return 1; + } else { + std::cout << "Read program from binary." << std::endl; + } + + // Build program + CL_CHECK(clBuildProgram(program, 1, &device_id, NULL, NULL, NULL)); + + printf("attempting to create input buffer\n"); + fflush(stdout); + cl_mem input_bufferA; + input_bufferA = CL_CHECK_ERR( + clCreateBuffer(context, CL_MEM_READ_ONLY, + sizeof(float) * NUM_DATA * NUM_DATA, NULL, &_err)); + + cl_mem input_bufferB; + input_bufferB = CL_CHECK_ERR( + clCreateBuffer(context, CL_MEM_READ_ONLY, + sizeof(float) * NUM_DATA * NUM_DATA, NULL, &_err)); + + printf("attempting to create output buffer\n"); + fflush(stdout); + cl_mem output_buffer; + output_buffer = CL_CHECK_ERR( + clCreateBuffer(context, CL_MEM_WRITE_ONLY, + sizeof(float) * NUM_DATA * NUM_DATA, NULL, &_err)); + + memObjects[0] = input_bufferA; + memObjects[1] = input_bufferB; + memObjects[2] = output_buffer; + + int width = NUM_DATA; + + printf("attempting to create kernel\n"); + fflush(stdout); + kernel = CL_CHECK_ERR(clCreateKernel(program, "sgemm", &_err)); + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(input_bufferA), &input_bufferA)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(input_bufferB), &input_bufferB)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(output_buffer), &output_buffer)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(width), &width)); + + printf("attempting to enqueue write buffer\n"); + fflush(stdout); + for (int i = 0; i < NUM_DATA * NUM_DATA; i++) { + + float in = ((float)rand() / (float)(RAND_MAX)) * 100.0; + CL_CHECK(clEnqueueWriteBuffer(queue, input_bufferA, CL_TRUE, + i * sizeof(float), 4, &in, 0, NULL, NULL)); + in = ((float)rand() / (float)(RAND_MAX)) * 100.0; + CL_CHECK(clEnqueueWriteBuffer(queue, input_bufferB, CL_TRUE, + i * sizeof(float), 4, &in, 0, NULL, NULL)); + } + + printf("Done enqueueing\n"); + + cl_event kernel_completion; + const size_t local_work_size[3] = {1, 1, 1}; + // a_offset + size_t global_work_size[3] = {NUM_DATA, NUM_DATA, NUM_DATA}; + printf("attempting to enqueue kernel\n"); + fflush(stdout); + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, + local_work_size, 0, NULL, + &kernel_completion)); + printf("Enqueue'd kerenel\n"); + fflush(stdout); + cl_ulong time_start, time_end; + CL_CHECK(clWaitForEvents(1, &kernel_completion)); + CL_CHECK(clGetEventProfilingInfo(kernel_completion, + CL_PROFILING_COMMAND_START, + sizeof(time_start), &time_start, NULL)); + CL_CHECK(clGetEventProfilingInfo(kernel_completion, CL_PROFILING_COMMAND_END, + sizeof(time_end), &time_end, NULL)); + double elapsed = time_end - time_start; + printf("time(ns):%lg\n", elapsed); + CL_CHECK(clReleaseEvent(kernel_completion)); + + printf("Result:"); + for (int i = 0; i < NUM_DATA * NUM_DATA; i++) { + float data; + CL_CHECK(clEnqueueReadBuffer(queue, output_buffer, CL_TRUE, + i * sizeof(float), 4, &data, 0, NULL, NULL)); + // printf(" %f", data); + } + printf("\n"); + + CL_CHECK(clReleaseMemObject(memObjects[0])); + CL_CHECK(clReleaseMemObject(memObjects[1])); + CL_CHECK(clReleaseMemObject(memObjects[2])); + + CL_CHECK(clReleaseKernel(kernel)); + CL_CHECK(clReleaseProgram(program)); + CL_CHECK(clReleaseContext(context)); + + return 0; +} diff --git a/benchmarks/new_opencl/sgemm/sgemm b/benchmarks/new_opencl/sgemm/sgemm new file mode 100755 index 0000000000000000000000000000000000000000..cbede8ed0365736e8bff9f1b3e7acb2d9c9491f5 GIT binary patch literal 51840 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a/benchmarks/new_opencl/vecadd/Makefile b/benchmarks/new_opencl/vecadd/Makefile new file mode 100644 index 00000000..f3469442 --- /dev/null +++ b/benchmarks/new_opencl/vecadd/Makefile @@ -0,0 +1,44 @@ +RISCV_TOOL_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) +POCLCC_PATH ?= $(wildcard ~/dev/pocl/drops_vortex_cc) +POCLRT_PATH ?= $(wildcard ..) +DRIVER_PATH ?= $(wildcard ../../../driver/sw) + +CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I$(POCLRT_PATH)/include + +LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex + +PROJECT = vecadd + +SRCS = main.cc + +all: $(PROJECT) + +kernel.pocl: kernel.cl + POCL_DEBUG=all POCL_DEBUG_LLVM_PASSES=1 LD_LIBRARY_PATH=$(RISCV_TOOL_PATH)/lib:$(POCLCC_PATH)/lib:$(DRIVER_PATH)/simx $(POCLCC_PATH)/bin/poclcc -o kernel.pocl kernel.cl + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +run-fpga: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-ase: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-simx: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-rtlsim: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/benchmarks/new_opencl/vecadd/README b/benchmarks/new_opencl/vecadd/README new file mode 100644 index 00000000..e69de29b diff --git a/benchmarks/new_opencl/vecadd/kernel.cl b/benchmarks/new_opencl/vecadd/kernel.cl new file mode 100644 index 00000000..16b243d5 --- /dev/null +++ b/benchmarks/new_opencl/vecadd/kernel.cl @@ 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z9jU-ZA6_CA*zCg=Qh^;l>>?GY^+DD%zwYn<_vcTZVXgIJPe*!XqF&Jd7QNu$&EE{| s7yNM$trq+7=o@bM8dQDL^Nv5gI9_Gq=*>2CrfKtlE^;l^Yg$12UskovjsO4v literal 0 HcmV?d00001 diff --git a/benchmarks/new_opencl/vecadd/main.cc b/benchmarks/new_opencl/vecadd/main.cc new file mode 100644 index 00000000..68c9675a --- /dev/null +++ b/benchmarks/new_opencl/vecadd/main.cc @@ -0,0 +1,187 @@ +#include +#include +#include +#include +#include + +#define SIZE 4 +#define NUM_WORK_GROUPS 2 +#define KERNEL_NAME "vecadd" + +#define CL_CHECK(_expr) \ + do { \ + cl_int _err = _expr; \ + if (_err == CL_SUCCESS) \ + break; \ + printf("OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + cleanup(); \ + exit(-1); \ + } while (0) + +#define CL_CHECK2(_expr) \ + ({ \ + cl_int _err = CL_INVALID_VALUE; \ + decltype(_expr) _ret = _expr; \ + if (_err != CL_SUCCESS) { \ + printf("OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + cleanup(); \ + exit(-1); \ + } \ + _ret; \ + }) + +int exitcode = 0; +cl_context context = NULL; +cl_command_queue commandQueue = NULL; +cl_program program = NULL; +cl_kernel kernel = NULL; +cl_mem a_memobj = NULL; +cl_mem b_memobj = NULL; +cl_mem c_memobj = NULL; +cl_int *A = NULL; +cl_int *B = NULL; +cl_int *C = NULL; +uint8_t *kernel_bin = NULL; + +static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) { + if (nullptr == filename || nullptr == data || 0 == size) + return -1; + + FILE* fp = fopen(filename, "r"); + if (NULL == fp) { + fprintf(stderr, "Failed to load kernel."); + return -1; + } + fseek(fp , 0 , SEEK_END); + long fsize = ftell(fp); + rewind(fp); + + *data = (uint8_t*)malloc(fsize); + *size = fread(*data, 1, fsize, fp); + + fclose(fp); + + return 0; +} + +static void cleanup() { + if (commandQueue) clReleaseCommandQueue(commandQueue); + if (kernel) clReleaseKernel(kernel); + if (program) clReleaseProgram(program); + if (a_memobj) clReleaseMemObject(a_memobj); + if (b_memobj) clReleaseMemObject(b_memobj); + if (c_memobj) clReleaseMemObject(c_memobj); + if (context) clReleaseContext(context); + if (kernel_bin) free(kernel_bin); + if (A) free(A); + if (B) free(B); + if (C) free(C); +} + +static int find_device(char* name, cl_platform_id platform_id, cl_device_id *device_id) { + cl_device_id device_ids[64]; + cl_uint num_devices = 0; + + CL_CHECK(clGetDeviceIDs(platform_id, CL_DEVICE_TYPE_ALL, 64, device_ids, &num_devices)); + + for (int i=0; i $(PROJECT).dump + +run: $(PROJECT).hex + POCL_DEBUG=all $(VX_SIMX_PATH)/Vcache_simX -E -a rv32i --core $(PROJECT).hex -s -b 1> emulator.debug + +qemu: $(PROJECT).qemu + POCL_DEBUG=all $(RISCV_TOOL_PATH)/bin/qemu-riscv32 -d in_asm -D debug.log $(PROJECT).qemu + +gdb-s: $(PROJECT).qemu + POCL_DEBUG=all $(RISCV_TOOL_PATH)/bin/qemu-riscv32 -g 1234 -d in_asm -D debug.log $(PROJECT).qemu + +gdb-c: $(PROJECT).qemu + $(GDB) $(PROJECT).qemu + +clean: + rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug diff --git a/benchmarks/opencl/convolution/input.bmp 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z?z05$TXaJ^n7x!2^fy>d`Jm4xra=$uNBb8!9N>bsUpXJ>%lEN;iQllN_8s&Y80hQk G`}%(cy4YR- literal 0 HcmV?d00001 diff --git a/benchmarks/opencl/convolution/kernel.cl b/benchmarks/opencl/convolution/kernel.cl new file mode 100755 index 00000000..e0e4da3a --- /dev/null +++ b/benchmarks/opencl/convolution/kernel.cl @@ -0,0 +1,54 @@ +__kernel +void convolution( + __read_only image2d_t sourceImage, + __write_only image2d_t outputImage, + int rows, + int cols, + __constant float* filter, + int filterWidth, + sampler_t sampler) +{ + // Store each work-item’s unique row and column + int column = get_global_id(0); + int row = get_global_id(1); + + // Half the width of the filter is needed for indexing + // memory later + int halfWidth = (int)(filterWidth/2); + + // All accesses to images return data as four-element vector + // (i.e., float4), although only the 'x' component will contain + // meaningful data in this code + float4 sum = {0.0f, 0.0f, 0.0f, 0.0f}; + + // Iterator for the filter + int filterIdx = 0; + + // Each work-item iterates around its local area based on the + // size of the filter + int2 coords; // Coordinates for accessing the image + // Iterate the filter rows + for(int i = -halfWidth; i <= halfWidth; i++) { + coords.y = row + i; + + // Iterate over the filter columns + for(int j = -halfWidth; j <= halfWidth; j++) { + coords.x = column + j; + + float4 pixel; + // Read a pixel from the image. A single channel image + // stores the pixel in the 'x' coordinate of the returned + // vector. + pixel = read_imagef(sourceImage, sampler, coords); + sum.x += pixel.x * filter[filterIdx++]; + } + } + + // Copy the data to the output image if the + // work-item is in bounds + if(row < rows && column < cols) { + coords.x = column; + coords.y = row; + write_imagef(outputImage, coords, sum); + } +} \ No newline at end of file diff --git a/benchmarks/opencl/convolution/main.cpp b/benchmarks/opencl/convolution/main.cpp new file mode 100755 index 00000000..5db2ae57 --- /dev/null +++ b/benchmarks/opencl/convolution/main.cpp @@ -0,0 +1,261 @@ +#include +#include +#include + +#include "utils.h" + +// This function takes a positive integer and rounds it up to +// the nearest multiple of another provided integer +unsigned int roundUp(unsigned int value, unsigned int multiple) { + + // Determine how far past the nearest multiple the value is + unsigned int remainder = value % multiple; + + // Add the difference to make the value a multiple + if(remainder != 0) { + value += (multiple-remainder); + } + + return value; +} + +// This function reads in a text file and stores it as a char pointer +char* readSource(char* kernelPath) { + + cl_int status; + FILE *fp; + char *source; + long int size; + + printf("Program file is: %s\n", kernelPath); + + fp = fopen(kernelPath, "rb"); + if(!fp) { + printf("Could not open kernel file\n"); + exit(-1); + } + status = fseek(fp, 0, SEEK_END); + if(status != 0) { + printf("Error seeking to end of file\n"); + exit(-1); + } + size = ftell(fp); + if(size < 0) { + printf("Error getting file position\n"); + exit(-1); + } + + rewind(fp); + + source = (char *)malloc(size + 1); + + int i; + for (i = 0; i < size+1; i++) { + source[i]='\0'; + } + + if(source == NULL) { + printf("Error allocating space for the kernel source\n"); + exit(-1); + } + + fread(source, 1, size, fp); + source[size] = '\0'; + + return source; +} + +void chk(cl_int status, const char* cmd) { + + if(status != CL_SUCCESS) { + printf("%s failed (%d)\n", cmd, status); + exit(-1); + } +} + +int main() { + + int i, j, k, l; + + // Rows and columns in the input image + int imageHeight; + int imageWidth; + + const char* inputFile = "input.bmp"; + const char* outputFile = "output.bmp"; + + // Homegrown function to read a BMP from file + float* inputImage = readImage(inputFile, &imageWidth, + &imageHeight); + + // Size of the input and output images on the host + int dataSize = imageHeight*imageWidth*sizeof(float); + + // Output image on the host + float* outputImage = NULL; + outputImage = (float*)malloc(dataSize); + float* refImage = NULL; + refImage = (float*)malloc(dataSize); + + // 45 degree motion blur + float filter[49] = + {0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + 0, 0, -1, 0, 1, 0, 0, + 0, 0, -2, 0, 2, 0, 0, + 0, 0, -1, 0, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0}; + + // The convolution filter is 7x7 + int filterWidth = 7; + int filterSize = filterWidth*filterWidth; // Assume a square kernel + + // Set up the OpenCL environment + cl_int status; + + // Discovery platform + cl_platform_id platform; + status = clGetPlatformIDs(1, &platform, NULL); + chk(status, "clGetPlatformIDs"); + + // Discover device + cl_device_id device; + clGetDeviceIDs(platform, CL_DEVICE_TYPE_ALL, 1, &device, NULL); + chk(status, "clGetDeviceIDs"); + + // Create context + cl_context_properties props[3] = {CL_CONTEXT_PLATFORM, + (cl_context_properties)(platform), 0}; + cl_context context; + context = clCreateContext(props, 1, &device, NULL, NULL, &status); + chk(status, "clCreateContext"); + + // Create command queue + cl_command_queue queue; + queue = clCreateCommandQueue(context, device, 0, &status); + chk(status, "clCreateCommandQueue"); + + // The image format describes how the data will be stored in memory + cl_image_format format; + format.image_channel_order = CL_R; // single channel + format.image_channel_data_type = CL_FLOAT; // float data type + + // Create space for the source image on the device + cl_mem d_inputImage = clCreateImage2D(context, 0, &format, imageWidth, + imageHeight, 0, NULL, &status); + chk(status, "clCreateImage2D"); + + // Create space for the output image on the device + cl_mem d_outputImage = clCreateImage2D(context, 0, &format, imageWidth, + imageHeight, 0, NULL, &status); + chk(status, "clCreateImage2D"); + + // Create space for the 7x7 filter on the device + cl_mem d_filter = clCreateBuffer(context, 0, filterSize*sizeof(float), + NULL, &status); + chk(status, "clCreateBuffer"); + + // Copy the source image to the device + size_t origin[3] = {0, 0, 0}; // Offset within the image to copy from + size_t region[3] = {imageWidth, imageHeight, 1}; // Elements to per dimension + status = clEnqueueWriteImage(queue, d_inputImage, CL_FALSE, origin, region, + 0, 0, inputImage, 0, NULL, NULL); + chk(status, "clEnqueueWriteImage"); + + // Copy the 7x7 filter to the device + status = clEnqueueWriteBuffer(queue, d_filter, CL_FALSE, 0, + filterSize*sizeof(float), filter, 0, NULL, NULL); + chk(status, "clEnqueueWriteBuffer"); + + // Create the image sampler + cl_sampler sampler = clCreateSampler(context, CL_FALSE, + CL_ADDRESS_CLAMP_TO_EDGE, CL_FILTER_NEAREST, &status); + chk(status, "clCreateSampler"); + + const char* source = readSource("kernel.cl"); + + // Create a program object with source and build it + cl_program program; + program = clCreateProgramWithSource(context, 1, &source, NULL, NULL); + chk(status, "clCreateProgramWithSource"); + status = clBuildProgram(program, 1, &device, NULL, NULL, NULL); + chk(status, "clBuildProgram"); + + // Create the kernel object + cl_kernel kernel; + kernel = clCreateKernel(program, "convolution", &status); + chk(status, "clCreateKernel"); + + // Set the kernel arguments + status = clSetKernelArg(kernel, 0, sizeof(cl_mem), &d_inputImage); + status |= clSetKernelArg(kernel, 1, sizeof(cl_mem), &d_outputImage); + status |= clSetKernelArg(kernel, 2, sizeof(int), &imageHeight); + status |= clSetKernelArg(kernel, 3, sizeof(int), &imageWidth); + status |= clSetKernelArg(kernel, 4, sizeof(cl_mem), &d_filter); + status |= clSetKernelArg(kernel, 5, sizeof(int), &filterWidth); + status |= clSetKernelArg(kernel, 6, sizeof(cl_sampler), &sampler); + chk(status, "clSetKernelArg"); + + // Set the work item dimensions + size_t globalSize[2] = {imageWidth, imageHeight}; + status = clEnqueueNDRangeKernel(queue, kernel, 2, NULL, globalSize, NULL, 0, + NULL, NULL); + chk(status, "clEnqueueNDRange"); + + // Read the image back to the host + status = clEnqueueReadImage(queue, d_outputImage, CL_TRUE, origin, + region, 0, 0, outputImage, 0, NULL, NULL); + chk(status, "clEnqueueReadImage"); + + // Write the output image to file + storeImage(outputImage, outputFile, imageHeight, imageWidth, inputFile); + + // Compute the reference image + for(i = 0; i < imageHeight; i++) { + for(j = 0; j < imageWidth; j++) { + refImage[i*imageWidth+j] = 0; + } + } + + // Iterate over the rows of the source image + int halfFilterWidth = filterWidth/2; + float sum; + for(i = 0; i < imageHeight; i++) { + // Iterate over the columns of the source image + for(j = 0; j < imageWidth; j++) { + sum = 0; // Reset sum for new source pixel + // Apply the filter to the neighborhood + for(k = - halfFilterWidth; k <= halfFilterWidth; k++) { + for(l = - halfFilterWidth; l <= halfFilterWidth; l++) { + if(i+k >= 0 && i+k < imageHeight && + j+l >= 0 && j+l < imageWidth) { + sum += inputImage[(i+k)*imageWidth + j+l] * + filter[(k+halfFilterWidth)*filterWidth + + l+halfFilterWidth]; + } + } + } + refImage[i*imageWidth+j] = sum; + } + } + + int failed = 0; + for(i = 0; i < imageHeight; i++) { + for(j = 0; j < imageWidth; j++) { + if(abs(outputImage[i*imageWidth+j]-refImage[i*imageWidth+j]) > 0.01) { + printf("Results are INCORRECT\n"); + printf("Pixel mismatch at <%d,%d> (%f vs. %f)\n", i, j, + outputImage[i*imageWidth+j], refImage[i*imageWidth+j]); + failed = 1; + } + if(failed) break; + } + if(failed) break; + } + if(!failed) { + printf("Results are correct\n"); + } + + return 0; +} \ No newline at end of file diff --git a/benchmarks/opencl/convolution/utils.cpp b/benchmarks/opencl/convolution/utils.cpp new file mode 100644 index 00000000..74ca6dad --- /dev/null +++ b/benchmarks/opencl/convolution/utils.cpp @@ -0,0 +1,180 @@ +#include +#include + +#include "utils.h" + +void storeImage(float *imageOut, + const char *filename, + int rows, + int cols, + const char* refFilename) { + + FILE *ifp, *ofp; + unsigned char tmp; + int offset; + unsigned char *buffer; + int i, j; + + int bytes; + + int height, width; + + ifp = fopen(refFilename, "rb"); + if(ifp == NULL) { + perror(filename); + exit(-1); + } + + fseek(ifp, 10, SEEK_SET); + fread(&offset, 4, 1, ifp); + + fseek(ifp, 18, SEEK_SET); + fread(&width, 4, 1, ifp); + fread(&height, 4, 1, ifp); + + fseek(ifp, 0, SEEK_SET); + + buffer = (unsigned char *)malloc(offset); + if(buffer == NULL) { + perror("malloc"); + exit(-1); + } + + fread(buffer, 1, offset, ifp); + + printf("Writing output image to %s\n", filename); + ofp = fopen(filename, "wb"); + if(ofp == NULL) { + perror("opening output file"); + exit(-1); + } + bytes = fwrite(buffer, 1, offset, ofp); + if(bytes != offset) { + printf("error writing header!\n"); + exit(-1); + } + + // NOTE bmp formats store data in reverse raster order (see comment in + // readImage function), so we need to flip it upside down here. + int mod = width % 4; + if(mod != 0) { + mod = 4 - mod; + } + // printf("mod = %d\n", mod); + for(i = height-1; i >= 0; i--) { + for(j = 0; j < width; j++) { + tmp = (unsigned char)imageOut[i*cols+j]; + fwrite(&tmp, sizeof(char), 1, ofp); + } + // In bmp format, rows must be a multiple of 4-bytes. + // So if we're not at a multiple of 4, add junk padding. + for(j = 0; j < mod; j++) { + fwrite(&tmp, sizeof(char), 1, ofp); + } + } + + fclose(ofp); + fclose(ifp); + + free(buffer); +} + +/* + * Read bmp image and convert to byte array. Also output the width and height + */ +float* readImage(const char *filename, int* widthOut, int* heightOut) { + + uchar* imageData; + + int height, width; + uchar tmp; + int offset; + int i, j; + + printf("Reading input image from %s\n", filename); + FILE *fp = fopen(filename, "rb"); + if(fp == NULL) { + perror(filename); + exit(-1); + } + + fseek(fp, 10, SEEK_SET); + fread(&offset, 4, 1, fp); + + fseek(fp, 18, SEEK_SET); + fread(&width, 4, 1, fp); + fread(&height, 4, 1, fp); + + printf("width = %d\n", width); + printf("height = %d\n", height); + + *widthOut = width; + *heightOut = height; + + imageData = (uchar*)malloc(width*height); + if(imageData == NULL) { + perror("malloc"); + exit(-1); + } + + fseek(fp, offset, SEEK_SET); + fflush(NULL); + + int mod = width % 4; + if(mod != 0) { + mod = 4 - mod; + } + + // NOTE bitmaps are stored in upside-down raster order. So we begin + // reading from the bottom left pixel, then going from left-to-right, + // read from the bottom to the top of the image. For image analysis, + // we want the image to be right-side up, so we'll modify it here. + + // First we read the image in upside-down + + // Read in the actual image + for(i = 0; i < height; i++) { + + // add actual data to the image + for(j = 0; j < width; j++) { + fread(&tmp, sizeof(char), 1, fp); + imageData[i*width + j] = tmp; + } + // For the bmp format, each row has to be a multiple of 4, + // so I need to read in the junk data and throw it away + for(j = 0; j < mod; j++) { + fread(&tmp, sizeof(char), 1, fp); + } + } + + // Then we flip it over + int flipRow; + for(i = 0; i < height/2; i++) { + flipRow = height - (i+1); + for(j = 0; j < width; j++) { + tmp = imageData[i*width+j]; + imageData[i*width+j] = imageData[flipRow*width+j]; + imageData[flipRow*width+j] = tmp; + } + } + + fclose(fp); + + // Input image on the host + float* floatImage = NULL; + floatImage = (float*)malloc(sizeof(float)*width*height); + if(floatImage == NULL) { + perror("malloc"); + exit(-1); + } + + // Convert the BMP image to float (not required) + for(i = 0; i < height; i++) { + for(j = 0; j < width; j++) { + floatImage[i*width+j] = (float)imageData[i*width+j]; + } + } + + free(imageData); + return floatImage; +} \ No newline at end of file diff --git a/benchmarks/opencl/convolution/utils.h b/benchmarks/opencl/convolution/utils.h new file mode 100644 index 00000000..2686de50 --- /dev/null +++ b/benchmarks/opencl/convolution/utils.h @@ -0,0 +1,11 @@ +#ifndef __UTILS__ +#define __UTILS__ + +typedef unsigned char uchar; + +float* readImage(const char *filename, int* widthOut, int* heightOut); + +void storeImage(float *imageOut, const char *filename, int rows, int cols, + const char* refFilename); + +#endif \ No newline at end of file diff --git a/benchmarks/opencl/cutcp/Makefile b/benchmarks/opencl/cutcp/Makefile index df30c817..938c4797 100644 --- a/benchmarks/opencl/cutcp/Makefile +++ b/benchmarks/opencl/cutcp/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) -I. VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = cutcp diff --git a/benchmarks/opencl/guassian/Makefile b/benchmarks/opencl/guassian/Makefile index ac7faffd..5e90ec3f 100644 --- a/benchmarks/opencl/guassian/Makefile +++ b/benchmarks/opencl/guassian/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = gaussian diff --git a/benchmarks/opencl/kmeans/Makefile b/benchmarks/opencl/kmeans/Makefile index cae2a36d..50413ab0 100644 --- a/benchmarks/opencl/kmeans/Makefile +++ b/benchmarks/opencl/kmeans/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = kmeans SRCS = main.cc read_input.c rmse.c cluster.c kmeans_clustering.c diff --git a/benchmarks/opencl/lbm/Makefile b/benchmarks/opencl/lbm/Makefile index 5e516c3c..092a6b9a 100644 --- a/benchmarks/opencl/lbm/Makefile +++ b/benchmarks/opencl/lbm/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) -I. VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = lbm diff --git a/benchmarks/opencl/mri-q/Makefile b/benchmarks/opencl/mri-q/Makefile index 6255a35b..c8d3a784 100644 --- a/benchmarks/opencl/mri-q/Makefile +++ b/benchmarks/opencl/mri-q/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) -I. VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = mri-q diff --git a/benchmarks/opencl/nearn/Makefile b/benchmarks/opencl/nearn/Makefile index f8109b16..adde7a1d 100644 --- a/benchmarks/opencl/nearn/Makefile +++ b/benchmarks/opencl/nearn/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = nearn diff --git a/benchmarks/opencl/reduce0/Makefile b/benchmarks/opencl/reduce0/Makefile index c44d6254..580ae60c 100644 --- a/benchmarks/opencl/reduce0/Makefile +++ b/benchmarks/opencl/reduce0/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) -I. VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT=reduce0 diff --git a/benchmarks/opencl/sad/Makefile b/benchmarks/opencl/sad/Makefile index 3f6d74c3..d3757322 100644 --- a/benchmarks/opencl/sad/Makefile +++ b/benchmarks/opencl/sad/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) -I. VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = sad diff --git a/benchmarks/opencl/saxpy/Makefile b/benchmarks/opencl/saxpy/Makefile index 5c65cf4a..2847eb0f 100644 --- a/benchmarks/opencl/saxpy/Makefile +++ b/benchmarks/opencl/saxpy/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = saxpy diff --git a/benchmarks/opencl/sfilter/Makefile b/benchmarks/opencl/sfilter/Makefile index cff97eb4..d0c6fcdc 100644 --- a/benchmarks/opencl/sfilter/Makefile +++ b/benchmarks/opencl/sfilter/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = sfilter diff --git a/benchmarks/opencl/sgemm/Makefile b/benchmarks/opencl/sgemm/Makefile index 1575d3cf..36054ba6 100644 --- a/benchmarks/opencl/sgemm/Makefile +++ b/benchmarks/opencl/sgemm/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = sgemm diff --git a/benchmarks/opencl/spmv/Makefile b/benchmarks/opencl/spmv/Makefile index 9360d606..b554251e 100644 --- a/benchmarks/opencl/spmv/Makefile +++ b/benchmarks/opencl/spmv/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) -I. VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = spmv diff --git a/benchmarks/opencl/stencil/Makefile b/benchmarks/opencl/stencil/Makefile index b1b0a8e9..85166079 100644 --- a/benchmarks/opencl/stencil/Makefile +++ b/benchmarks/opencl/stencil/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) -I. VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = stencil diff --git a/benchmarks/opencl/transpose/Makefile b/benchmarks/opencl/transpose/Makefile index cdbe7da1..c2195ac4 100644 --- a/benchmarks/opencl/transpose/Makefile +++ b/benchmarks/opencl/transpose/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) -I. VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT=transpose diff --git a/benchmarks/opencl/vecadd/Makefile b/benchmarks/opencl/vecadd/Makefile index 59023862..63b9ae44 100644 --- a/benchmarks/opencl/vecadd/Makefile +++ b/benchmarks/opencl/vecadd/Makefile @@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions CXXFLAGS += -I$(POCL_INC_PATH) VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a -QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a +QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a PROJECT = vecadd diff --git a/driver/dogfood/Memcpy/hw/rtl/_hdr b/driver/dogfood/Memcpy/hw/rtl/_hdr new file mode 100644 index 00000000..39a1dd9e --- /dev/null +++ b/driver/dogfood/Memcpy/hw/rtl/_hdr @@ -0,0 +1,603 @@ +// +// Copyright (c) 2017, Intel Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + +// Read from the memory locations first and then write to the memory locations + +`include "platform_if.vh" +`include "afu_json_info.vh" + + +module ccip_std_afu + ( + // CCI-P Clocks and Resets + input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock + input logic pClkDiv2, // 200MHz - CCI-P clock domain. + input logic pClkDiv4, // 100MHz - CCI-P clock domain. + input logic uClk_usr, // User clock domain. Refer to clock programming guide ** Currently provides fixed 300MHz clock ** + input logic uClk_usrDiv2, // User clock domain. Half the programmed frequency ** Currently provides fixed 150MHz clock ** + input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset + input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State + input logic pck_cp2af_error, // CCI-P Protocol Error Detected + + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port + output t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port + ); + + + // + // Run the entire design at the standard CCI-P frequency (400 MHz). + // + logic clk; + assign clk = pClk; + + logic reset; + assign reset = pck_cp2af_softReset; + + logic [511:0] wr_data; + logic [511:0] rd_data; + + logic get_write_addr; + logic do_update; + logic rd_end_of_list; + logic rd_needed; + logic wr_needed; + logic [15:0] cnt_list_length; + + // ========================================================================= + // + // Register requests. + // + // ========================================================================= + + // + // The incoming pck_cp2af_sRx and outgoing pck_af2cp_sTx must both be + // registered. Here we register pck_cp2af_sRx and assign it to sRx. + // We also assign pck_af2cp_sTx to sTx here but don't register it. + // The code below never uses combinational logic to write sTx. + // + + t_if_ccip_Rx sRx; + always_ff @(posedge clk) + begin + sRx <= pck_cp2af_sRx; + end + + t_if_ccip_Tx sTx; + assign pck_af2cp_sTx = sTx; + + + // ========================================================================= + // + // CSR (MMIO) handling. + // + // ========================================================================= + + // The AFU ID is a unique ID for a given program. Here we generated + // one with the "uuidgen" program and stored it in the AFU's JSON file. + // ASE and synthesis setup scripts automatically invoke afu_json_mgr + // to extract the UUID into afu_json_info.vh. + logic [127:0] afu_id = `AFU_ACCEL_UUID; + + // + // A valid AFU must implement a device feature list, starting at MMIO + // address 0. Every entry in the feature list begins with 5 64-bit + // words: a device feature header, two AFU UUID words and two reserved + // words. + // + + // Is a CSR read request active this cycle? + logic is_csr_read; + assign is_csr_read = sRx.c0.mmioRdValid; + + // Is a CSR write request active this cycle? + logic is_csr_write; + assign is_csr_write = sRx.c0.mmioWrValid; + + // The MMIO request header is overlayed on the normal c0 memory read + // response data structure. Cast the c0Rx header to an MMIO request + // header. + t_ccip_c0_ReqMmioHdr mmio_req_hdr; + assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(sRx.c0.hdr); + + + // + // Implement the device feature list by responding to MMIO reads. + // + + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c2.mmioRdValid <= 1'b0; + end + else + begin + // Always respond with something for every read request + sTx.c2.mmioRdValid <= is_csr_read; + + // The unique transaction ID matches responses to requests + sTx.c2.hdr.tid <= mmio_req_hdr.tid; + + // Addresses are of 32-bit objects in MMIO space. Addresses + // of 64-bit objects are thus multiples of 2. + case (mmio_req_hdr.address) + 0: // AFU DFH (device feature header) + begin + // Here we define a trivial feature list. In this + // example, our AFU is the only entry in this list. + sTx.c2.data <= t_ccip_mmioData'(0); + // Feature type is AFU + sTx.c2.data[63:60] <= 4'h1; + // End of list (last entry in list) + sTx.c2.data[40] <= 1'b1; + end + + // AFU_ID_L + 2: sTx.c2.data <= afu_id[63:0]; + + // AFU_ID_H + 4: sTx.c2.data <= afu_id[127:64]; + + // DFH_RSVD0 + 6: sTx.c2.data <= t_ccip_mmioData'(0); + + // DFH_RSVD1 + 8: sTx.c2.data <= t_ccip_mmioData'(0); + + default: sTx.c2.data <= t_ccip_mmioData'(0); + endcase + end + end + + + // + // CSR write handling. Host software must tell the AFU the memory address + // to which it should be writing. The address is set by writing a CSR. + // + + // We use MMIO address 0 to set the memory address. The read and + // write MMIO spaces are logically separate so we are free to use + // whatever we like. This may not be good practice for cleanly + // organizing the MMIO address space, but it is legal. + logic is_mem_addr_csr_write; + assign is_mem_addr_csr_write = get_write_addr && is_csr_write && + (mmio_req_hdr.address == t_ccip_mmioAddr'(0)); + + // Memory address to which this AFU will write. + t_ccip_clAddr write_mem_addr; + + always_ff @(posedge clk) + begin + if (reset) + begin + get_write_addr <= 1'b1; + end + else if (is_mem_addr_csr_write) + begin + write_mem_addr <= t_ccip_clAddr'(sRx.c0.data); + get_write_addr <= 1'b0; + end + end + + + // We use MMIO address 0 to set the memory address for reading data. + logic is_mem_addr_csr_read; + assign is_mem_addr_csr_read = !get_write_addr && is_csr_write && + (mmio_req_hdr.address == t_ccip_mmioAddr'(0)); + + // Memory address from which this AFU will read. + logic start_read; + t_ccip_clAddr read_mem_addr; + + //logic start_traversal = 'b0; + //t_ccip_clAddr start_traversal_addr; + + always_ff @(posedge clk) + begin + if (reset) + begin + start_read <= 1'b0; + end + else if (is_mem_addr_csr_read) + begin + read_mem_addr <= t_ccip_clAddr'(sRx.c0.data); + start_read <= 'b1; + end + end + + + // ========================================================================= + // + // Main AFU logic + // + // ========================================================================= + + // + // States in our simple example. + // + //typedef enum logic [0:0] + typedef enum logic [1:0] + { + STATE_IDLE, + STATE_READ, + STATE_UPDATE, + STATE_WRITE + } + t_state; + + t_state state; + + // + // State machine + // + always_ff @(posedge clk) + begin + if (reset) + begin + state <= STATE_IDLE; + rd_end_of_list <= 1'b0; + end + else + begin + case (state) + STATE_IDLE: + begin + // Traversal begins when CSR 1 is written + if (start_read) + begin + state <= STATE_READ; + $display("AFU starting traversal at 0x%x", t_ccip_clAddr'(read_mem_addr)); + end + end + + STATE_READ: + begin + if (rd_needed) + begin + // Read data from the address and update address + state <= STATE_UPDATE; + start_read <= 'b0; + $display("AFU reading data and pointing to next read address..."); + end + end + + STATE_UPDATE: + begin + // Update the read value to be written back + if (do_update) + begin + state <= STATE_WRITE; + $display("AFU performing comutations on the read values..."); + end + end + + STATE_WRITE: + begin + // Write the updated value to the address + // Point to new address after that + // if done then point to IDLE; else read new values + if (rd_end_of_list) + begin + state <= STATE_IDLE; + $display("AFU done..."); + end + else + begin + if (wr_needed) + begin + state <= STATE_READ; + $display("AFU reading again from read address..."); + end + end + end + endcase + end + end + + + // ========================================================================= + // + // Read logic. + // + // ========================================================================= + + // + // READ REQUEST + // + + // Did a write response just arrive + logic addr_next_valid; + + // Next read address + t_ccip_clAddr addr_next; + + always_ff @(posedge clk) + begin + // Next read address is valid when we have got the write response back + // and channel is not full + //addr_next_valid <= sRx.c0TxAlmFull; + addr_next_valid <= sRx.c1.rspValid; + + // Next address is current address plus address length + // Apurve + //addr_next <= addr_next + addr_size; + addr_next <= addr_next + 0; + + // End of list reached if we have read 10 times + rd_end_of_list <= (cnt_list_length == 'h10); + end + + // + // Since back pressure may prevent an immediate read request, we must + // record whether a read is needed and hold it until the request can + // be sent to the FIU. + // + t_ccip_clAddr rd_addr; + + always_ff @(posedge clk) + begin + if (reset) + begin + rd_needed <= 1'b0; + end + else + begin + // If reads are allowed this cycle then we can safely clear + // any previously requested reads. This simple AFU has only + // one read in flight at a time since it is walking a pointer + // chain. + if (rd_needed) + begin + rd_needed <= sRx.c0TxAlmFull; + end + else + begin + // Need a read under two conditions: + // - Starting a new walk + // - A read response just arrived from a line containing + // a next pointer. + rd_needed <= (start_read || (addr_next_valid && ! rd_end_of_list)); + rd_addr <= (start_read ? read_mem_addr : addr_next); + end + end + end + + // + // Emit read requests to the FIU. + // + + // Read header defines the request to the FIU + t_cci_c0_ReqMemHdr rd_hdr; + + always_comb + begin + rd_hdr = t_cci_c0_ReqMemHdr'(0); + + // Read request type + rd_hdr.req_type = eREQ_RDLINE_I; + // Virtual address (MPF virtual addressing is enabled) + rd_hdr.address = rd_addr; + // Let the FIU pick the channel + rd_hdr.vc_sel = eVC_VA; + // Read 4 lines (the size of an entry in the list) + rd_hdr.cl_len = eCL_LEN_4; + end + + // Send read requests to the FIU + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c0.valid <= 1'b0; + cnt_list_length <= 0; + end + else + begin + // Generate a read request when needed and the FIU isn't full + sTx.c0.valid <= (rd_needed && ! sRx.c0TxAlmFull); + sTx.c0.hdr <= rd_hdr; + + if (rd_needed && ! sRx.c0TxAlmFull) + begin + cnt_list_length <= cnt_list_length + 1; + //$display(" Reading from VA 0x%x", clAddrToByteAddr(rd_addr)); + $display("Incrementing read count..."); + end + end + end + + // + // READ RESPONSE HANDLING + // + + // + // Receive data (read responses). + // + always_ff @(posedge clk) + begin + if (reset) + begin + do_update <= 1'b0; + end + else + begin + if (state == STATE_READ) + begin + rd_data <= sRx.c0.data; + do_update <= 1'b1; + end + if (state == STATE_UPDATE) + begin + // Update the read data and put it in the write data to be written + wr_data <= rd_data + 1; + do_update <= 1'b0; + end + end + end + + + // ========================================================================= + // + // Write logic. + // + // ========================================================================= + + + // + // WRITE REQUEST + // + + // Did a write response just arrive + logic wr_addr_next_valid; + + // Next write address + t_ccip_clAddr wr_addr_next; + + always_ff @(posedge clk) + begin + // Next write address is valid when we have got the read response back + // and channel is not full + //wr_addr_next_valid <= sRx.c1TxAlmFull; + wr_addr_next_valid <= sRx.c0.rspValid; + + // Next address is current address plus address length + // Apurve + //wr_addr_next <= wr_addr_next + addr_size; + wr_addr_next <= wr_addr_next + 0; + end + + // + // Since back pressure may prevent an immediate write request, we must + // record whether a write is needed and hold it until the request can + // be sent to the FIU. + // + t_ccip_clAddr wr_addr; + + always_ff @(posedge clk) + begin + if (reset) + begin + wr_needed <= 1'b0; + end + else + begin + // If writes are allowed this cycle then we can safely clear + // any previously requested writes. This simple AFU has only + // one write in flight at a time since it is walking a pointer + // chain. + if (wr_needed) + begin + wr_needed <= sRx.c1TxAlmFull; + end + else + begin + // Need a write under two conditions: + // - Starting a new walk + // - A write response just arrived from a line containing + // a next pointer. + //wr_needed <= (start_write || (wr_addr_next_valid && ! rd_end_of_list)); + wr_needed <= (start_write || wr_addr_next_valid); + wr_addr <= (start_write ? write_mem_addr : wr_addr_next); + end + end + end + + // + // Emit write requests to the FIU. + // + + // Write header defines the request to the FIU + t_ccip_c1_ReqMemHdr wr_hdr; + + always_comb + begin + wr_hdr = t_cci_c1_ReqMemHdr'(0); + + // Write request type + wr_hdr.req_type = eREQ_RDLINE_I; + // Virtual address (MPF virtual addressing is enabled) + wr_hdr.address = wr_addr; + // Let the FIU pick the channel + wr_hdr.vc_sel = eVC_VA; + // Write 4 lines (the size of an entry in the list) + wr_hdr.cl_len = eCL_LEN_4; + // Start of packet is true (single line write) + wr_hdr.sop = 1'b1; + end + + // Send write requests to the FIU + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c1.valid <= 1'b0; + //cnt_list_length <= 0; + end + else + begin + // Generate a write request when needed and the FIU isn't full + sTx.c1.valid <= (wr_needed && ! sRx.c1TxAlmFull); + sTx.c1.hdr <= wr_hdr; + sTx.c1.data = t_ccip_clData'(wr_data); + + //if (wr_needed && ! sRx.c1TxAlmFull) + //begin + // cnt_list_length <= cnt_list_length + 1; + // //$display(" Writing from VA 0x%x", clAddrToByteAddr(rd_addr)); + // $display("Incrementing write count..."); + //end + end + end + + // + // WRITE RESPONSE HANDLING + // + + // Apurve: Check if a signal is to be sent to read to start reading in case + // write response does not work + // + // Send data (write requests). + // + //always_ff @(posedge clk) + //begin + // if (state == STATE_WRITE) + // begin + // rd_data <= sRx.c0.data; + // end + // if (state == STATE_UPDATE) + // begin + // // Update the write data and put it in the write data to be written + // wr_data <= rd_data + 1; + // end + //end + +endmodule diff --git a/driver/dogfood/Memcpy/hw/rtl/cci_hello.json b/driver/dogfood/Memcpy/hw/rtl/cci_hello.json new file mode 100644 index 00000000..85d7a529 --- /dev/null +++ b/driver/dogfood/Memcpy/hw/rtl/cci_hello.json @@ -0,0 +1,18 @@ +{ + "version": 1, + "afu-image": { + "power": 0, + "afu-top-interface": + { + "name": "ccip_std_afu" + }, + "accelerator-clusters": + [ + { + "name": "cci_hello", + "total-contexts": 1, + "accelerator-type-uuid": "c6aa954a-9b91-4a37-abc1-1d9f0709dcc3" + } + ] + } +} diff --git a/driver/dogfood/Memcpy/hw/rtl/cci_hello_afu.sv b/driver/dogfood/Memcpy/hw/rtl/cci_hello_afu.sv new file mode 100644 index 00000000..eaee72da --- /dev/null +++ b/driver/dogfood/Memcpy/hw/rtl/cci_hello_afu.sv @@ -0,0 +1,653 @@ +// +// Copyright (c) 2017, Intel Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + +// Read from the memory locations first and then write to the memory locations + +`include "platform_if.vh" +`include "afu_json_info.vh" + + +module ccip_std_afu + ( + // CCI-P Clocks and Resets + input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock + input logic pClkDiv2, // 200MHz - CCI-P clock domain. + input logic pClkDiv4, // 100MHz - CCI-P clock domain. + input logic uClk_usr, // User clock domain. Refer to clock programming guide ** Currently provides fixed 300MHz clock ** + input logic uClk_usrDiv2, // User clock domain. Half the programmed frequency ** Currently provides fixed 150MHz clock ** + input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset + input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State + input logic pck_cp2af_error, // CCI-P Protocol Error Detected + + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port + output t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port + ); + + + // + // Run the entire design at the standard CCI-P frequency (400 MHz). + // + logic clk; + assign clk = pClk; + + logic reset; + assign reset = pck_cp2af_softReset; + + logic [511:0] wr_data; + logic [511:0] rd_data; + + logic do_update; + logic start_read; + logic start_write; + logic wr_addr_next_valid; + logic addr_next_valid; + logic rd_end_of_list; + logic rd_needed; + logic wr_needed; + logic read_req; + logic write_req; + logic [15:0] cnt_list_length; + t_ccip_clAddr rd_addr; + t_ccip_clAddr wr_addr; + t_ccip_clAddr addr_next; + t_ccip_clAddr wr_addr_next; + + // ========================================================================= + // + // Register requests. + // + // ========================================================================= + + // + // The incoming pck_cp2af_sRx and outgoing pck_af2cp_sTx must both be + // registered. Here we register pck_cp2af_sRx and assign it to sRx. + // We also assign pck_af2cp_sTx to sTx here but don't register it. + // The code below never uses combinational logic to write sTx. + // + + t_if_ccip_Rx sRx; + always_ff @(posedge clk) + begin + sRx <= pck_cp2af_sRx; + end + + t_if_ccip_Tx sTx; + assign pck_af2cp_sTx = sTx; + + + // ========================================================================= + // + // CSR (MMIO) handling. + // + // ========================================================================= + + // The AFU ID is a unique ID for a given program. Here we generated + // one with the "uuidgen" program and stored it in the AFU's JSON file. + // ASE and synthesis setup scripts automatically invoke afu_json_mgr + // to extract the UUID into afu_json_info.vh. + logic [127:0] afu_id = `AFU_ACCEL_UUID; + + // + // A valid AFU must implement a device feature list, starting at MMIO + // address 0. Every entry in the feature list begins with 5 64-bit + // words: a device feature header, two AFU UUID words and two reserved + // words. + // + + // Is a CSR read request active this cycle? + logic is_csr_read; + assign is_csr_read = sRx.c0.mmioRdValid; + + // Is a CSR write request active this cycle? + logic is_csr_write; + assign is_csr_write = sRx.c0.mmioWrValid; + + // The MMIO request header is overlayed on the normal c0 memory read + // response data structure. Cast the c0Rx header to an MMIO request + // header. + t_ccip_c0_ReqMmioHdr mmio_req_hdr; + assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(sRx.c0.hdr); + + + // + // Implement the device feature list by responding to MMIO reads. + // + + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c2.mmioRdValid <= 1'b0; + end + else + begin + // Always respond with something for every read request + sTx.c2.mmioRdValid <= is_csr_read; + + // The unique transaction ID matches responses to requests + sTx.c2.hdr.tid <= mmio_req_hdr.tid; + + // Addresses are of 32-bit objects in MMIO space. Addresses + // of 64-bit objects are thus multiples of 2. + case (mmio_req_hdr.address) + 0: // AFU DFH (device feature header) + begin + // Here we define a trivial feature list. In this + // example, our AFU is the only entry in this list. + sTx.c2.data <= t_ccip_mmioData'(0); + // Feature type is AFU + sTx.c2.data[63:60] <= 4'h1; + // End of list (last entry in list) + sTx.c2.data[40] <= 1'b1; + end + + // AFU_ID_L + 2: sTx.c2.data <= afu_id[63:0]; + + // AFU_ID_H + 4: sTx.c2.data <= afu_id[127:64]; + + // DFH_RSVD0 + 6: sTx.c2.data <= t_ccip_mmioData'(0); + + // DFH_RSVD1 + 8: sTx.c2.data <= t_ccip_mmioData'(0); + + // Updated by apurve to check fpgaReadMMIO + 10: sTx.c2.data <= t_ccip_mmioData'(start_read); + + default: sTx.c2.data <= t_ccip_mmioData'(0); + endcase + end + end + + + // + // CSR write handling. Host software must tell the AFU the memory address + // to which it should be writing. The address is set by writing a CSR. + // + + // We use MMIO address 0 to set the memory address. The read and + // write MMIO spaces are logically separate so we are free to use + // whatever we like. This may not be good practice for cleanly + // organizing the MMIO address space, but it is legal. + logic is_mem_addr_csr_write; + assign is_mem_addr_csr_write = is_csr_write && + (mmio_req_hdr.address == t_ccip_mmioAddr'(0)); + + // Memory address to which this AFU will write. + t_ccip_clAddr write_mem_addr; + + always_ff @(posedge clk) + begin + if (reset) + begin + start_write <= 1'b0; + end + else if (is_mem_addr_csr_write) + begin + write_mem_addr <= t_ccip_clAddr'(sRx.c0.data); + start_write <= 1'b1; + //$display("Write mem address is 0x%x", t_ccip_clAddr'(write_mem_addr)); + end + end + + + // We use MMIO address 8 to set the memory address for reading data. + logic is_mem_addr_csr_read; + assign is_mem_addr_csr_read = is_csr_write && + (mmio_req_hdr.address == t_ccip_mmioAddr'(2)); + + // Memory address from which this AFU will read. + t_ccip_clAddr read_mem_addr; + + //logic start_traversal = 'b0; + //t_ccip_clAddr start_traversal_addr; + + always_ff @(posedge clk) + begin + if (reset) + begin + start_read <= 1'b0; + end + else if (is_mem_addr_csr_read) + begin + read_mem_addr <= t_ccip_clAddr'(sRx.c0.data); + start_read <= 1'b1; + //$display("Read mem address is 0x%x", t_ccip_clAddr'(read_mem_addr)); + end + end + + + // ========================================================================= + // + // Main AFU logic + // + // ========================================================================= + + // + // States in our simple example. + // + //typedef enum logic [0:0] + typedef enum logic [1:0] + { + STATE_IDLE, + STATE_READ, + STATE_UPDATE, + STATE_WRITE + } + t_state; + + t_state state; + + // + // State machine + // + always_ff @(posedge clk) + begin + if (reset) + begin + state <= STATE_IDLE; + rd_end_of_list <= 1'b0; + end + else + begin + case (state) + STATE_IDLE: + begin + // Traversal begins when CSR 1 is written + if (start_read) + begin + state <= STATE_READ; + $display("AFU starting traversal at 0x%x", t_ccip_clAddr'(read_mem_addr)); + end + end + + STATE_READ: + begin + $display("AFU in READ..."); + $display("do_update is %d...",do_update); + $display("addr_next_valid is %d...",addr_next_valid); + $display("rd_needed is %d...",rd_needed); + if (!rd_needed && do_update) + begin + state <= STATE_UPDATE; + $display("AFU moving to UPDATE..."); + end + end + + STATE_UPDATE: + begin + // Update the read value to be written back + $display("AFU in UPDATE..."); + if (!do_update) + begin + state <= STATE_WRITE; + wr_needed <= 1'b1; + $display("AFU moving to WRITE..."); + end + end + + STATE_WRITE: + begin + // Write the updated value to the address + // Point to new address after that + // if done then point to IDLE; else read new values + $display("AFU in WRITE..."); + if (rd_end_of_list) + begin + state <= STATE_IDLE; + $display("AFU done..."); + end + else if (!wr_needed) + begin + state <= STATE_READ; + $display("AFU moving to READ from WRITE..."); + start_write <= 1'b0; + write_req <= 1'b0; + end + end + endcase + end + end + + + // ========================================================================= + // + // Read logic. + // + // ========================================================================= + + // + // READ REQUEST + // + + // Did a write response just arrive + + // Next read address + + always_ff @(posedge clk) + begin + // Next read address is valid when we have got the write response back + if (sRx.c1.rspValid) + begin + addr_next_valid <= sRx.c1.rspValid; + + //if (state == STATE_READ && !rd_needed) + //begin + // Apurve: Next address is current address plus address length + //addr_next <= addr_next + addr_size; + addr_next <= (addr_next_valid ? rd_addr + 0 : rd_addr); + + // End of list reached if we have read 5 times + rd_end_of_list <= (cnt_list_length == 'h5); + //end + end + end + + // + // Since back pressure may prevent an immediate read request, we must + // record whether a read is needed and hold it until the request can + // be sent to the FIU. + // + + always_ff @(posedge clk) + begin + if (reset) + begin + rd_needed <= 1'b0; + end + else + begin + // If reads are allowed this cycle then we can safely clear + // any previously requested reads. This simple AFU has only + // one read in flight at a time since it is walking a pointer + // chain. + if (rd_needed) + begin + //rd_needed <= sRx.c0TxAlmFull; + //rd_needed <= (!sRx.c0TxAlmFull && !sRx.c0.rspValid); + rd_needed <= !sRx.c0.rspValid; + end + else if (state == STATE_READ) + begin + // Need a read under two conditions: + // - Starting a new walk + // - A read response just arrived from a line containing + // a next pointer. + rd_needed <= (start_read || (!sRx.c0TxAlmFull && (addr_next_valid && ! rd_end_of_list))); + rd_addr <= (start_read ? read_mem_addr : addr_next); + //$display("rd_addr is 0x%x", t_ccip_clAddr'(rd_addr)); + //$display("read mem addr is 0x%x", t_ccip_clAddr'(read_mem_addr)); + //$display("start read is %d", start_read); + end + end + end + + // + // Emit read requests to the FIU. + // + + // Read header defines the request to the FIU + t_ccip_c0_ReqMemHdr rd_hdr; + + always_comb + begin + rd_hdr = t_ccip_c0_ReqMemHdr'(0); + + // Read request type (No intention to cache) + //rd_hdr.req_type = 4'h0; + + // Virtual address (MPF virtual addressing is enabled) + rd_hdr.address = rd_addr; + + // Read over channel VA + //rd_hdr.vc_sel = 2'h0; + + // Read one cache line (64 bytes) + //rd_hdr.cl_len = 2'h0; + end + + // Send read requests to the FIU + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c0.valid <= 1'b0; + cnt_list_length <= 0; + read_req <= 1'b0; + end + else + begin + // Generate a read request when needed and the FIU isn't full + if (state == STATE_READ) + begin + sTx.c0.valid <= (rd_needed && !sRx.c0TxAlmFull && !read_req); + + if (rd_needed && !sRx.c0TxAlmFull && !read_req) + begin + sTx.c0.hdr <= rd_hdr; + cnt_list_length <= cnt_list_length + 1; + read_req <= 1'b1; + $display("Incrementing read count...%d",cnt_list_length); + $display("Read address is 0x%x...",rd_hdr.address); + addr_next_valid <= 1'b0; + // Apurve: Add something to stop read once this section has been accessed + //rd_needed <= 1'b0; + end + end + end + end + + // + // READ RESPONSE HANDLING + // + + // + // Receive data (read responses). + // + always_ff @(posedge clk) + begin + if (reset) + begin + do_update <= 1'b0; + end + else + begin + if (!do_update && sRx.c0.rspValid) + begin + rd_data <= sRx.c0.data; + do_update <= 1'b1; + $display("rd data is %d...",rd_data); + end + + if ((state == STATE_UPDATE) && (do_update == 1'b1)) + begin + // Update the read data and put it in the write data to be written + wr_data <= rd_data + 2; + do_update <= 1'b0; + read_req <= 1'b0; + $display("write data is %d...",wr_data); + + // First read done. Next reads should be from the updated addresses + start_read <= 1'b0; + end + end + end + + + // ========================================================================= + // + // Write logic. + // + // ========================================================================= + + + // + // WRITE REQUEST + // + + // Did a write response just arrive + + // Next write address + + always_ff @(posedge clk) + begin + if (sRx.c0.rspValid) + begin + // Next write address is valid when we have got the read response back + wr_addr_next_valid <= sRx.c0.rspValid; + //wr_addr_next_valid <= (!start_write && sRx.c0.rspValid); + + //if (state == STATE_WRITE && !wr_needed) + //begin + // Apurve: Next address is current address plus address length + //wr_addr_next <= wr_addr + 0; + wr_addr_next <= (wr_addr_next_valid ? wr_addr + 0 : wr_addr); + //end + end + end + + // + // Since back pressure may prevent an immediate write request, we must + // record whether a write is needed and hold it until the request can + // be sent to the FIU. + // + + always_ff @(posedge clk) + begin + if (reset) + begin + wr_needed <= 1'b0; + end + else + begin + // If writes are allowed this cycle then we can safely clear + // any previously requested writes. This simple AFU has only + // one write in flight at a time since it is walking a pointer + // chain. + if (wr_needed) + begin + //wr_needed <= sRx.c1TxAlmFull; + //wr_needed <= (!sRx.c1TxAlmFull && !sRx.c1.rspValid); + wr_needed <= !sRx.c1.rspValid; + end + else + begin + // Need a write under two conditions: + // - Starting a new walk + // - A write response just arrived from a line containing + // a next pointer. + wr_needed <= (start_write || (!sRx.c1TxAlmFull && wr_addr_next_valid)); + wr_addr <= (start_write ? write_mem_addr : wr_addr_next); + //$display("Write mem address later is 0x%x", t_ccip_clAddr'(write_mem_addr)); + end + end + end + + // + // Emit write requests to the FIU. + // + + // Write header defines the request to the FIU + t_ccip_c1_ReqMemHdr wr_hdr; + + always_comb + begin + wr_hdr = t_ccip_c1_ReqMemHdr'(0); + + // Write request type + //wr_hdr.req_type = 4'h0; + + // Virtual address (MPF virtual addressing is enabled) + wr_hdr.address = wr_addr; + + // Let the FIU pick the channel + //wr_hdr.vc_sel = 2'h2; + + // Write 1 cache line (64 bytes) + //wr_hdr.cl_len = 2'h0; + + // Start of packet is true (single line write) + wr_hdr.sop = 1'b1; + end + + // Send write requests to the FIU + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c1.valid <= 1'b0; + write_req <= 1'b0; + end + else + begin + // Generate a write request when needed and the FIU isn't full + if (state == STATE_WRITE) + begin + sTx.c1.valid <= (wr_needed && !sRx.c1TxAlmFull && !write_req); + if (wr_needed && !sRx.c1TxAlmFull && !write_req) + begin + sTx.c1.hdr <= wr_hdr; + sTx.c1.data <= t_ccip_clData'(wr_data); + write_req <= 1'b1; + wr_addr_next_valid <= 1'b0; + $display("Write address is 0x%x...", wr_hdr.address); + end + end + end + end + + + // + // WRITE RESPONSE HANDLING + // + + // Apurve: Check if a signal is to be sent to read to start reading in case + // write response does not work + // + // Send data (write requests). + // + //always_ff @(posedge clk) + //begin + // if (state == STATE_WRITE) + // begin + // rd_data <= sRx.c0.data; + // end + // if (state == STATE_UPDATE) + // begin + // // Update the write data and put it in the write data to be written + // wr_data <= rd_data + 1; + // end + //end + +endmodule diff --git a/driver/dogfood/Memcpy/hw/rtl/cci_hello_afu_working.sv b/driver/dogfood/Memcpy/hw/rtl/cci_hello_afu_working.sv new file mode 100644 index 00000000..144b430e --- /dev/null +++ b/driver/dogfood/Memcpy/hw/rtl/cci_hello_afu_working.sv @@ -0,0 +1,621 @@ +// +// Copyright (c) 2017, Intel Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + +// Read from the memory locations first and then write to the memory locations + +`include "platform_if.vh" +`include "afu_json_info.vh" + + +module ccip_std_afu + ( + // CCI-P Clocks and Resets + input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock + input logic pClkDiv2, // 200MHz - CCI-P clock domain. + input logic pClkDiv4, // 100MHz - CCI-P clock domain. + input logic uClk_usr, // User clock domain. Refer to clock programming guide ** Currently provides fixed 300MHz clock ** + input logic uClk_usrDiv2, // User clock domain. Half the programmed frequency ** Currently provides fixed 150MHz clock ** + input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset + input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State + input logic pck_cp2af_error, // CCI-P Protocol Error Detected + + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port + output t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port + ); + + + // + // Run the entire design at the standard CCI-P frequency (400 MHz). + // + logic clk; + assign clk = pClk; + + logic reset; + assign reset = pck_cp2af_softReset; + + logic [511:0] wr_data; + logic [511:0] rd_data; + + logic do_update; + logic start_read; + logic start_write; + logic wr_addr_next_valid; + logic addr_next_valid; + logic rd_end_of_list; + logic rd_needed; + logic wr_needed; + logic [15:0] cnt_list_length; + t_ccip_clAddr rd_addr; + t_ccip_clAddr wr_addr; + t_ccip_clAddr addr_next; + t_ccip_clAddr wr_addr_next; + + // ========================================================================= + // + // Register requests. + // + // ========================================================================= + + // + // The incoming pck_cp2af_sRx and outgoing pck_af2cp_sTx must both be + // registered. Here we register pck_cp2af_sRx and assign it to sRx. + // We also assign pck_af2cp_sTx to sTx here but don't register it. + // The code below never uses combinational logic to write sTx. + // + + t_if_ccip_Rx sRx; + always_ff @(posedge clk) + begin + sRx <= pck_cp2af_sRx; + end + + t_if_ccip_Tx sTx; + assign pck_af2cp_sTx = sTx; + + + // ========================================================================= + // + // CSR (MMIO) handling. + // + // ========================================================================= + + // The AFU ID is a unique ID for a given program. Here we generated + // one with the "uuidgen" program and stored it in the AFU's JSON file. + // ASE and synthesis setup scripts automatically invoke afu_json_mgr + // to extract the UUID into afu_json_info.vh. + logic [127:0] afu_id = `AFU_ACCEL_UUID; + + // + // A valid AFU must implement a device feature list, starting at MMIO + // address 0. Every entry in the feature list begins with 5 64-bit + // words: a device feature header, two AFU UUID words and two reserved + // words. + // + + // Is a CSR read request active this cycle? + logic is_csr_read; + assign is_csr_read = sRx.c0.mmioRdValid; + + // Is a CSR write request active this cycle? + logic is_csr_write; + assign is_csr_write = sRx.c0.mmioWrValid; + + // The MMIO request header is overlayed on the normal c0 memory read + // response data structure. Cast the c0Rx header to an MMIO request + // header. + t_ccip_c0_ReqMmioHdr mmio_req_hdr; + assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(sRx.c0.hdr); + + + // + // Implement the device feature list by responding to MMIO reads. + // + + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c2.mmioRdValid <= 1'b0; + end + else + begin + // Always respond with something for every read request + sTx.c2.mmioRdValid <= is_csr_read; + + // The unique transaction ID matches responses to requests + sTx.c2.hdr.tid <= mmio_req_hdr.tid; + + // Addresses are of 32-bit objects in MMIO space. Addresses + // of 64-bit objects are thus multiples of 2. + case (mmio_req_hdr.address) + 0: // AFU DFH (device feature header) + begin + // Here we define a trivial feature list. In this + // example, our AFU is the only entry in this list. + sTx.c2.data <= t_ccip_mmioData'(0); + // Feature type is AFU + sTx.c2.data[63:60] <= 4'h1; + // End of list (last entry in list) + sTx.c2.data[40] <= 1'b1; + end + + // AFU_ID_L + 2: sTx.c2.data <= afu_id[63:0]; + + // AFU_ID_H + 4: sTx.c2.data <= afu_id[127:64]; + + // DFH_RSVD0 + 6: sTx.c2.data <= t_ccip_mmioData'(0); + + // DFH_RSVD1 + 8: sTx.c2.data <= t_ccip_mmioData'(0); + + // Updated by apurve to check fpgaReadMMIO + 10: sTx.c2.data <= t_ccip_mmioData'(start_read); + + default: sTx.c2.data <= t_ccip_mmioData'(0); + endcase + end + end + + + // + // CSR write handling. Host software must tell the AFU the memory address + // to which it should be writing. The address is set by writing a CSR. + // + + // We use MMIO address 0 to set the memory address. The read and + // write MMIO spaces are logically separate so we are free to use + // whatever we like. This may not be good practice for cleanly + // organizing the MMIO address space, but it is legal. + logic is_mem_addr_csr_write; + assign is_mem_addr_csr_write = is_csr_write && + (mmio_req_hdr.address == t_ccip_mmioAddr'(0)); + + // Memory address to which this AFU will write. + t_ccip_clAddr write_mem_addr; + + always_ff @(posedge clk) + begin + if (reset) + begin + start_write <= 1'b0; + end + else if (is_mem_addr_csr_write) + begin + write_mem_addr <= t_ccip_clAddr'(sRx.c0.data); + start_write <= 1'b1; + //$display("Write mem address is 0x%x", t_ccip_clAddr'(write_mem_addr)); + end + end + + + // We use MMIO address 8 to set the memory address for reading data. + logic is_mem_addr_csr_read; + assign is_mem_addr_csr_read = is_csr_write && + (mmio_req_hdr.address == t_ccip_mmioAddr'(2)); + + // Memory address from which this AFU will read. + t_ccip_clAddr read_mem_addr; + + //logic start_traversal = 'b0; + //t_ccip_clAddr start_traversal_addr; + + always_ff @(posedge clk) + begin + if (reset) + begin + start_read <= 1'b0; + end + else if (is_mem_addr_csr_read) + begin + read_mem_addr <= t_ccip_clAddr'(sRx.c0.data); + start_read <= 1'b1; + //$display("Read mem address is 0x%x", t_ccip_clAddr'(read_mem_addr)); + end + end + + + // ========================================================================= + // + // Main AFU logic + // + // ========================================================================= + + // + // States in our simple example. + // + //typedef enum logic [0:0] + typedef enum logic [1:0] + { + STATE_IDLE, + STATE_READ, + STATE_UPDATE, + STATE_WRITE + } + t_state; + + t_state state; + + // + // State machine + // + always_ff @(posedge clk) + begin + if (reset) + begin + state <= STATE_IDLE; + rd_end_of_list <= 1'b0; + end + else + begin + case (state) + STATE_IDLE: + begin + // Traversal begins when CSR 1 is written + if (start_read) + begin + state <= STATE_READ; + $display("AFU starting traversal at 0x%x", t_ccip_clAddr'(read_mem_addr)); + end + end + + STATE_READ: + begin + $display("AFU in READ..."); + if (!rd_needed && do_update) + begin + state <= STATE_UPDATE; + $display("AFU moving to UPDATE..."); + end + end + + STATE_UPDATE: + begin + // Update the read value to be written back + $display("AFU in UPDATE..."); + if (!do_update) + begin + state <= STATE_WRITE; + wr_needed <= 1'b1; + $display("AFU moving to WRITE..."); + end + end + + STATE_WRITE: + begin + // Write the updated value to the address + // Point to new address after that + // if done then point to IDLE; else read new values + $display("AFU in WRITE..."); + if (rd_end_of_list) + begin + state <= STATE_IDLE; + $display("AFU done..."); + end + else if (!wr_needed) + begin + state <= STATE_READ; + $display("AFU moving to READ from WRITE..."); + start_write <= 1'b0; + end + end + endcase + end + end + + + // ========================================================================= + // + // Read logic. + // + // ========================================================================= + + // + // READ REQUEST + // + + // Did a write response just arrive + + // Next read address + + always_ff @(posedge clk) + begin + // Next read address is valid when we have got the write response back + addr_next_valid <= sRx.c1.rspValid; + + // Apurve: Next address is current address plus address length + //addr_next <= addr_next + addr_size; + addr_next <= rd_addr + 0; + + // End of list reached if we have read 5 times + rd_end_of_list <= (cnt_list_length == 'h5); + end + + // + // Since back pressure may prevent an immediate read request, we must + // record whether a read is needed and hold it until the request can + // be sent to the FIU. + // + + always_ff @(posedge clk) + begin + if (reset) + begin + rd_needed <= 1'b0; + end + else + begin + // If reads are allowed this cycle then we can safely clear + // any previously requested reads. This simple AFU has only + // one read in flight at a time since it is walking a pointer + // chain. + if (rd_needed) + begin + rd_needed <= sRx.c0TxAlmFull; + end + else + begin + // Need a read under two conditions: + // - Starting a new walk + // - A read response just arrived from a line containing + // a next pointer. + rd_needed <= (start_read || (!sRx.c0TxAlmFull && (addr_next_valid && ! rd_end_of_list))); + rd_addr <= (start_read ? read_mem_addr : addr_next); + //$display("rd_addr is 0x%x", t_ccip_clAddr'(rd_addr)); + //$display("read mem addr is 0x%x", t_ccip_clAddr'(read_mem_addr)); + //$display("start read is %d", start_read); + end + end + end + + // + // Emit read requests to the FIU. + // + + // Read header defines the request to the FIU + t_ccip_c0_ReqMemHdr rd_hdr; + + always_comb + begin + rd_hdr = t_ccip_c0_ReqMemHdr'(0); + + // Read request type (No intention to cache) + //rd_hdr.req_type = 4'h0; + + // Virtual address (MPF virtual addressing is enabled) + rd_hdr.address = rd_addr; + + // Read over channel VA + //rd_hdr.vc_sel = 2'h0; + + // Read one cache line (64 bytes) + //rd_hdr.cl_len = 2'h0; + end + + // Send read requests to the FIU + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c0.valid <= 1'b0; + cnt_list_length <= 0; + end + else + begin + // Generate a read request when needed and the FIU isn't full + if (state == STATE_READ) + begin + sTx.c0.valid <= (rd_needed && !sRx.c0TxAlmFull); + + if (rd_needed && !sRx.c0TxAlmFull) + begin + sTx.c0.hdr <= rd_hdr; + cnt_list_length <= cnt_list_length + 1; + $display("Incrementing read count...%d",cnt_list_length); + $display("Read address is 0x%x...",rd_hdr.address); + // Apurve: Add something to stop read once this section has been accessed + end + end + end + end + + // + // READ RESPONSE HANDLING + // + + // + // Receive data (read responses). + // + always_ff @(posedge clk) + begin + if (reset) + begin + do_update <= 1'b0; + end + else + begin + if (sRx.c0.rspValid) + begin + rd_data <= sRx.c0.data; + do_update <= 1'b1; + //$display("rd data is %d...",rd_data); + end + + if (state == STATE_UPDATE) + begin + // Update the read data and put it in the write data to be written + wr_data <= rd_data + 2; + do_update <= 1'b0; + $display("write data is %d...",wr_data); + + // First read done. Next reads should be from the updated addresses + start_read <= 1'b0; + end + end + end + + + // ========================================================================= + // + // Write logic. + // + // ========================================================================= + + + // + // WRITE REQUEST + // + + // Did a write response just arrive + + // Next write address + + always_ff @(posedge clk) + begin + // Next write address is valid when we have got the read response back + wr_addr_next_valid <= sRx.c0.rspValid; + + // Apurve: Next address is current address plus address length + wr_addr_next <= wr_addr + 0; + + end + + // + // Since back pressure may prevent an immediate write request, we must + // record whether a write is needed and hold it until the request can + // be sent to the FIU. + // + + always_ff @(posedge clk) + begin + if (reset) + begin + wr_needed <= 1'b0; + end + else + begin + // If writes are allowed this cycle then we can safely clear + // any previously requested writes. This simple AFU has only + // one write in flight at a time since it is walking a pointer + // chain. + if (wr_needed) + begin + wr_needed <= sRx.c1TxAlmFull; + end + else + begin + // Need a write under two conditions: + // - Starting a new walk + // - A write response just arrived from a line containing + // a next pointer. + wr_needed <= (start_write || (!sRx.c1TxAlmFull && wr_addr_next_valid)); + wr_addr <= (start_write ? write_mem_addr : wr_addr_next); + //$display("Write mem address later is 0x%x", t_ccip_clAddr'(write_mem_addr)); + end + end + end + + // + // Emit write requests to the FIU. + // + + // Write header defines the request to the FIU + t_ccip_c1_ReqMemHdr wr_hdr; + + always_comb + begin + wr_hdr = t_ccip_c1_ReqMemHdr'(0); + + // Write request type + //wr_hdr.req_type = 4'h0; + + // Virtual address (MPF virtual addressing is enabled) + wr_hdr.address = wr_addr; + + // Let the FIU pick the channel + //wr_hdr.vc_sel = 2'h2; + + // Write 1 cache line (64 bytes) + //wr_hdr.cl_len = 2'h0; + + // Start of packet is true (single line write) + wr_hdr.sop = 1'b1; + end + + // Send write requests to the FIU + always_ff @(posedge clk) + begin + if (reset) + begin + sTx.c1.valid <= 1'b0; + end + else + begin + // Generate a write request when needed and the FIU isn't full + if (state == STATE_WRITE) + begin + sTx.c1.valid <= (wr_needed && !sRx.c1TxAlmFull); + if (wr_needed && !sRx.c1TxAlmFull) + begin + sTx.c1.hdr <= wr_hdr; + sTx.c1.data <= t_ccip_clData'(wr_data); + end + end + end + end + + + // + // WRITE RESPONSE HANDLING + // + + // Apurve: Check if a signal is to be sent to read to start reading in case + // write response does not work + // + // Send data (write requests). + // + //always_ff @(posedge clk) + //begin + // if (state == STATE_WRITE) + // begin + // rd_data <= sRx.c0.data; + // end + // if (state == STATE_UPDATE) + // begin + // // Update the write data and put it in the write data to be written + // wr_data <= rd_data + 1; + // end + //end + +endmodule diff --git a/driver/dogfood/Memcpy/hw/rtl/sources.txt b/driver/dogfood/Memcpy/hw/rtl/sources.txt new file mode 100644 index 00000000..8a73008b --- /dev/null +++ b/driver/dogfood/Memcpy/hw/rtl/sources.txt @@ -0,0 +1,2 @@ +cci_hello.json +cci_hello_afu.sv diff --git a/driver/dogfood/Memcpy/hw/sim/setup_ase b/driver/dogfood/Memcpy/hw/sim/setup_ase new file mode 100755 index 00000000..a8414ac0 --- /dev/null +++ b/driver/dogfood/Memcpy/hw/sim/setup_ase @@ -0,0 +1,11 @@ +#!/bin/sh + +## +## Setup ASE environment using ../rtl/sources.txt. +## + +# Absolute path to this script +SCRIPT=$(readlink -f "$0") +SCRIPT_PATH=$(dirname "$SCRIPT") + +afu_sim_setup --sources="${SCRIPT_PATH}/../rtl/sources.txt" $@ diff --git a/driver/dogfood/Memcpy/sw/Makefile b/driver/dogfood/Memcpy/sw/Makefile new file mode 100644 index 00000000..f3b66c12 --- /dev/null +++ b/driver/dogfood/Memcpy/sw/Makefile @@ -0,0 +1,41 @@ +include ../../common/sw/common_include.mk + +# Primary test name +TEST = cci_hello + +# Build directory +OBJDIR = obj +CFLAGS += -I./$(OBJDIR) +CPPFLAGS += -I./$(OBJDIR) + +# Files and folders +SRCS = $(TEST).c +OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.c,%.o,$(SRCS))) + +# Targets (build only $(TEST)_ase by default) +all: $(TEST) $(TEST)_ase + +# AFU info from JSON file, including AFU UUID +AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h + +$(AFU_JSON_INFO): ../hw/rtl/$(TEST).json | objdir + afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ + +$(OBJS): $(AFU_JSON_INFO) + +$(TEST): $(OBJS) + $(CC) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) + +$(TEST)_ase: $(OBJS) + $(CC) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) + +$(OBJDIR)/%.o: %.c | objdir + $(CC) $(CFLAGS) -c $< -o $@ + +clean: + rm -rf $(TEST) $(TEST)_ase $(OBJDIR) + +objdir: + @mkdir -p $(OBJDIR) + +.PHONY: all clean diff --git a/driver/dogfood/Memcpy/sw/cci_hello.c b/driver/dogfood/Memcpy/sw/cci_hello.c new file mode 100644 index 00000000..f12d95c2 --- /dev/null +++ b/driver/dogfood/Memcpy/sw/cci_hello.c @@ -0,0 +1,210 @@ +// +// Copyright (c) 2017, Intel Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include +#include +#include +#include +#include +#include + +#include + +// State from the AFU's JSON file, extracted using OPAE's afu_json_mgr script +#include "afu_json_info.h" + +#define CACHELINE_BYTES 64 +#define CL(x) ((x) * CACHELINE_BYTES) + + +// +// Search for an accelerator matching the requested UUID and connect to it. +// +static fpga_handle connect_to_accel(const char *accel_uuid) +{ + fpga_properties filter = NULL; + fpga_guid guid; + fpga_token accel_token; + uint32_t num_matches; + fpga_handle accel_handle; + fpga_result r; + + // Don't print verbose messages in ASE by default + //setenv("ASE_LOG", "0", 0); + + // Set up a filter that will search for an accelerator + fpgaGetProperties(NULL, &filter); + fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); + + // Add the desired UUID to the filter + uuid_parse(accel_uuid, guid); + fpgaPropertiesSetGUID(filter, guid); + + // Do the search across the available FPGA contexts + num_matches = 1; + fpgaEnumerate(&filter, 1, &accel_token, 1, &num_matches); + + // Not needed anymore + fpgaDestroyProperties(&filter); + + if (num_matches < 1) + { + fprintf(stderr, "Accelerator %s not found!\n", accel_uuid); + return 0; + } + + // Open accelerator + r = fpgaOpen(accel_token, &accel_handle, 0); + assert(FPGA_OK == r); + + // Done with token + fpgaDestroyToken(&accel_token); + + return accel_handle; +} + + +// +// Allocate a buffer in I/O memory, shared with the FPGA. +// +static volatile void* alloc_buffer(fpga_handle accel_handle, + ssize_t size, + uint64_t *wsid, + uint64_t *io_addr) +{ + fpga_result r; + volatile void* buf; + + r = fpgaPrepareBuffer(accel_handle, size, (void*)&buf, wsid, 0); + if (FPGA_OK != r) return NULL; + + // Get the physical address of the buffer in the accelerator + r = fpgaGetIOAddress(accel_handle, *wsid, io_addr); + assert(FPGA_OK == r); + + return buf; +} + + +int main(int argc, char *argv[]) +{ + fpga_handle accel_handle; + volatile char *buf; + volatile char *buf_r; + uint64_t wsid1; + uint64_t wsid2; + uint64_t buf_pa; + uint64_t ret_buf_pa; + uint64_t buf_rpa; + uint64_t ret_buf_rpa; + fpga_result r; + + // Find and connect to the accelerator + accel_handle = connect_to_accel(AFU_ACCEL_UUID); + + // Allocate a single page memory buffer for write + buf = (volatile char*)alloc_buffer(accel_handle, 4 * getpagesize(), + &wsid1, &buf_pa); + // Allocate a single page memory buffer for read + buf_r = (volatile char*)alloc_buffer(accel_handle, 4 * getpagesize(), + &wsid2, &buf_rpa); + assert(NULL != buf); + + //// Set the low byte of the shared buffer to 0. The FPGA will write + //// a non-zero value to it. + //buf[0] = 0; + + // Set the low byte of the shared buffer buf_r to 0. The FPGA will read + // the values and write to buf address + buf[0] = 5; + buf_r[0] = 5; + + // Tell the accelerator the address of the buffer using cache line + // addresses. The accelerator will respond by writing to the buffer. + r = fpgaWriteMMIO64(accel_handle, 0, 0, buf_pa / CL(1)); + printf("Write address is %08lx\n", buf_pa); + printf("Write address div 64 is %08lx\n", buf_pa/ CL(1)); + assert(FPGA_OK == r); + + // Wait for response from FPGA. Check using fpgaReadMMIO + //r = fpgaReadMMIO64(accel_handle, 0, 0, &ret_buf_pa); + //printf("Returned write is %08lx\n", ret_buf_pa); + //assert(FPGA_OK == r); + +///////////////////// Added to check fpgaRead + // Wait for response from FPGA. Check using fpgaReadMMIO + r = fpgaReadMMIO64(accel_handle, 0, 5 * sizeof(uint64_t), &ret_buf_rpa); + printf("Returned read at 10 is %08lx\n", ret_buf_rpa); + assert(FPGA_OK == r); +/////////////////////////////////////////////// + + + // Tell the accelerator the address of the buffer using cache line + // addresses. The accelerator will read from the buffer. + // Write the address to MMIO 1 + r = fpgaWriteMMIO64(accel_handle, 0, sizeof(uint64_t), buf_rpa / CL(1)); + printf("Read address is %08lx\n", buf_rpa); + printf("Read address div64 is %08lx\n", buf_rpa / CL(1)); + assert(FPGA_OK == r); + + // Wait for response from FPGA. Check using fpgaReadMMIO + //r = fpgaReadMMIO64(accel_handle, 0, sizeof(uint64_t), &ret_buf_rpa); + //printf("Returned write is %08lx\n", ret_buf_rpa); + //assert(FPGA_OK == r); + + + + + + + + + // Update this + // Spin, waiting for the value in memory to change to something non-zero. + while (5 == buf[0]) + { + // A well-behaved program would use _mm_pause(), nanosleep() or + // equivalent to save power here. + }; + + // Print the string written by the FPGA + printf("%d\n", buf[0]); + + do { + //printf("%d\n", buf[0]); + } while (10 != buf[0]); + + // Done + fpgaReleaseBuffer(accel_handle, wsid1); + fpgaReleaseBuffer(accel_handle, wsid2); + fpgaClose(accel_handle); + + return 0; +} diff --git a/driver/dogfood/Memcpy/sw/obj/afu_json_info.h b/driver/dogfood/Memcpy/sw/obj/afu_json_info.h new file mode 100644 index 00000000..e16a5349 --- /dev/null +++ b/driver/dogfood/Memcpy/sw/obj/afu_json_info.h @@ -0,0 +1,13 @@ +// +// Generated by afu_json_mgr from ../hw/rtl/cci_hello.json +// + +#ifndef __AFU_JSON_INFO__ +#define __AFU_JSON_INFO__ + +#define AFU_ACCEL_NAME "cci_hello" +#define AFU_ACCEL_UUID "C6AA954A-9B91-4A37-ABC1-1D9F0709DCC3" +#define AFU_IMAGE_POWER 0 +#define AFU_TOP_IFC "ccip_std_afu" + +#endif // __AFU_JSON_INFO__ diff --git a/driver/dogfood/Memcpy/sw/obj/cci_hello.o b/driver/dogfood/Memcpy/sw/obj/cci_hello.o new file mode 100644 index 0000000000000000000000000000000000000000..a6d79f493c77264d59167e9a913e3aeedecb5e59 GIT binary patch literal 5336 zcmbW4e`p*<6vyY1CaLLlea%UXnZ83S2J2%|#B9OpjAS-r1CCH`8V_*+5E3P)Yr+O#aoQq$Z}r zN_tJzZg46odD%Oo%*u19RHo!PC3W>%Y%fxfmgg?wBuZ-50#m`8N?M*)QopPs&?tyA zXjYz~gQmJ>z%!3wJ5qDsAQPhDd{*SNJoCy-a*vWOvL+@Y|}ijX^ToK35yIaD5_O{83x)KkZfIuQkg5_=EN)6e@nkGqQA$Fgh&rN2qj7hLwDq+6)WFlyfdi63 zNBSFlzNY#*Uv*PUlefCgSKC%ly{%1co<>hotKVNsx`UmaQpEvjFgZjH8xd2N zv~bwa6A3Ajkg7cUqT{7Jk8F21a!hKdv#EM@Gik*1uw>|3Skg?%>&fyW%n98~wG2bZ ztcX=%I(H}@i|HX#HRGy=Tfy_uVBH}V5+BkHGO9)37u)XlKPl}F4klw}QmS{?yFJz3 znk4OdU-UM(J#~95EY*0tjb4w}1HrbifUXn0#5G>-+P=PI?J2k-9|4X9tsbvT-^TKj z1^x}ig&r43sBb^@67mMt++UDFH}yZm{GkGyzwo&NDqudb!l~AfzgI+#{ldI&8svrf zf7Xdvc2F71&jnGCt*U>!y)(Qpn+nAo-{=lAPyozyq z28E;qyt!6L@E4wIg`_wK9s^RILkW4^fxqv-@y5&-=X(eKs{{YTf#bpEi(d@;l8>>Tp zI4qbD4?a|2cypCOxeMPzXg-8s$np8+ybmE5a=e>3A4Uj4^CxWlVH+Q|@$EMLmW|_kk;nOvah}f>*8f!C zJpV5R&hw}LmOxxF|DOeY9ca*QF^+nCNAY}$F%dA4*D%iWtYG603Y_OD3%uV7OP*p} z%<}~s-vL^l&y)}cpK-LeZF&j%Tz^K;zl>tAFC6qUf}XGI2Z8f-{U~t0{|mPG_UGr0 zjaNV(JkR1nn%3%b_>t8m<&5M0NKm-`Q9;l1+#_(Fr$^wGEPg%X;{NyBxPAYR2yrg4 zIHpZ+&-0|9Uts!E4*K^5Jzv)uf%A2JF7Qeg|0~ADb^Rph?=byuHoZOnyEeWPw0!@| zFfbTacD~)lE5XP06136q_}L>s`_1%khV$>g0fF=H1L95`A2qc>s7=GFM|jK7qng{) z$4%l6YoijR)!G4R3vJi5ERJ6KKMO(4Kw`iMGYXruh+#Ad(uN`j$y zC5T^^&A`xhv3;_7tDnQXOYp8lN%JbP8UyRB`c-^MfMFNs;a|4+TSMCg1vxuDMAU|a zc{xX|-5!Sy#=O_@UKoop?Pm>LGREfLD@-VUV>Yqz{QZq%(N42<^LyK(nf>EoTfo8F zT!Zy>Hr~##Eou)lCgwlS#*YgD`2KU;3ypl|x5yT%Fd?2Fj^*R|`Qf*Rxc4~3!~S8? ouwyeZf9#97qg-JROel28f4TqVVE_OC literal 0 HcmV?d00001 diff --git a/driver/hw/Makefile b/driver/hw/Makefile new file mode 100644 index 00000000..cd91bd11 --- /dev/null +++ b/driver/hw/Makefile @@ -0,0 +1,24 @@ + +BUILD_DIR=build_sim + +all: ase fpga + +ase: build-setup + make -C $(BUILD_DIR) + +fpga: build-setup + # TODO + +build-setup: $(BUILD_DIR)/Makefile + +$(BUILD_DIR)/Makefile: + afu_sim_setup --sources=sources.txt --platform discrete_pcie3 $(BUILD_DIR) -f + +run-ase: + cd $(BUILD_DIR) && MENT_VSIM_OPT="-dpicpppath /usr/bin/gcc" make sim + +run-fpga: + # TODO + +clean: + rm -rf $(BUILD_DIR) \ No newline at end of file diff --git a/driver/hw/ccip_interface_reg.sv b/driver/hw/ccip_interface_reg.sv new file mode 100644 index 00000000..c61e843e --- /dev/null +++ b/driver/hw/ccip_interface_reg.sv @@ -0,0 +1,48 @@ +// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex + +// Register all interface signals + +import ccip_if_pkg::*; +module ccip_interface_reg( + // CCI-P Clocks and Resets + input logic pClk, // 400MHz - CC-P clock domain. Primary Clock + input logic pck_cp2af_softReset_T0, // CCI-P ACTIVE HIGH Soft Reset + input logic [1:0] pck_cp2af_pwrState_T0, // CCI-P AFU Power State + input logic pck_cp2af_error_T0, // CCI-P Protocol Error Detected + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx_T0, // CCI-P Rx Port + input t_if_ccip_Tx pck_af2cp_sTx_T0, // CCI-P Tx Port + + output logic pck_cp2af_softReset_T1, + output logic [1:0] pck_cp2af_pwrState_T1, + output logic pck_cp2af_error_T1, + + output t_if_ccip_Rx pck_cp2af_sRx_T1, + output t_if_ccip_Tx pck_af2cp_sTx_T1 + +); +(* preserve *) logic pck_cp2af_softReset_T0_q; +(* preserve *) logic [1:0] pck_cp2af_pwrState_T0_q; +(* preserve *) logic pck_cp2af_error_T0_q; +(* preserve *) t_if_ccip_Rx pck_cp2af_sRx_T0_q; +(* preserve *) t_if_ccip_Tx pck_af2cp_sTx_T0_q; + +always@(posedge pClk) +begin + pck_cp2af_softReset_T0_q <= pck_cp2af_softReset_T0; + pck_cp2af_pwrState_T0_q <= pck_cp2af_pwrState_T0; + pck_cp2af_error_T0_q <= pck_cp2af_error_T0; + pck_cp2af_sRx_T0_q <= pck_cp2af_sRx_T0; + pck_af2cp_sTx_T0_q <= pck_af2cp_sTx_T0; +end + +always_comb +begin + pck_cp2af_softReset_T1 = pck_cp2af_softReset_T0_q; + pck_cp2af_pwrState_T1 = pck_cp2af_pwrState_T0_q; + pck_cp2af_error_T1 = pck_cp2af_error_T0_q; + pck_cp2af_sRx_T1 = pck_cp2af_sRx_T0_q; + pck_af2cp_sTx_T1 = pck_af2cp_sTx_T0_q; +end + +endmodule \ No newline at end of file diff --git a/driver/hw/ccip_std_afu.sv b/driver/hw/ccip_std_afu.sv new file mode 100644 index 00000000..aaf4cd23 --- /dev/null +++ b/driver/hw/ccip_std_afu.sv @@ -0,0 +1,172 @@ +// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex + +// Top Level Vortex Driver + +// To be done: +// Check how to run this with OPAE. Looks like setup issue + + +`include "platform_if.vh" + +import local_mem_cfg_pkg::*; + +module ccip_std_afu + #( + parameter NUM_LOCAL_MEM_BANKS = 2 + ) + ( + // CCI-P Clocks and Resets + input logic pClk, // Primary CCI-P interface clock. + input logic pClkDiv2, // Aligned, pClk divided by 2. + input logic pClkDiv4, // Aligned, pClk divided by 4. + input logic uClk_usr, // User clock domain. Refer to clock programming guide. + input logic uClk_usrDiv2, // Aligned, user clock divided by 2. + input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset + + input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State + input logic pck_cp2af_error, // CCI-P Protocol Error Detected + + // CCI-P structures + input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port + output t_if_ccip_Tx pck_af2cp_sTx, // CCI-P Tx Port + + // Local memory interface + avalon_mem_if.to_fiu local_mem[NUM_LOCAL_MEM_BANKS] +); + + // ==================================================================== + // Pick the proper clk and reset, as chosen by the AFU's JSON file + // ==================================================================== + + // The platform may transform the CCI-P clock from pClk to a clock + // chosen in the AFU's JSON file. + logic clk; + assign clk = `PLATFORM_PARAM_CCI_P_CLOCK; + + logic reset; + assign reset = `PLATFORM_PARAM_CCI_P_RESET; + + + // ==================================================================== + // Register signals at interface before consuming them + // ==================================================================== + + (* noprune *) logic [1:0] cp2af_pwrState_T1; + (* noprune *) logic cp2af_error_T1; + + logic reset_T1; + t_if_ccip_Rx cp2af_sRx_T1; + t_if_ccip_Tx af2cp_sTx_T0; + + ccip_interface_reg inst_green_ccip_interface_reg + ( + .pClk (clk), + .pck_cp2af_softReset_T0 (reset), + .pck_cp2af_pwrState_T0 (pck_cp2af_pwrState), + .pck_cp2af_error_T0 (pck_cp2af_error), + .pck_cp2af_sRx_T0 (pck_cp2af_sRx), + .pck_af2cp_sTx_T0 (af2cp_sTx_T0), + + .pck_cp2af_softReset_T1 (reset_T1), + .pck_cp2af_pwrState_T1 (cp2af_pwrState_T1), + .pck_cp2af_error_T1 (cp2af_error_T1), + .pck_cp2af_sRx_T1 (cp2af_sRx_T1), + .pck_af2cp_sTx_T1 (pck_af2cp_sTx) + ); + + + // ==================================================================== + // User AFU goes here + // ==================================================================== + + // + // vortex_afu depends on CCI-P and local memory being in the same + // clock domain. This is accomplished by choosing a common clock + // in the AFU's JSON description. The platform instantiates clock- + // crossing shims automatically, as needed. + // + + // + // Memory banks are used very simply here. Only bank is active at + // a time, selected by mem_bank_select. mem_bank_select is set + // by a CSR from the host. + // + t_local_mem_byte_mask avs_byteenable; + logic avs_waitrequest; + t_local_mem_data avs_readdata; + logic avs_readdatavalid; + t_local_mem_burst_cnt avs_burstcount; + t_local_mem_data avs_writedata; + t_local_mem_addr avs_address; + logic avs_write; + logic avs_read; + + // choose which memory bank to test + logic [$clog2(NUM_LOCAL_MEM_BANKS)-1:0] mem_bank_select; + + vortex_afu + #( + .NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS) + ) + hello_mem_afu_inst + ( + .clk (clk), + .SoftReset (reset_T1), + + .avs_writedata (avs_writedata), + .avs_readdata (avs_readdata), + .avs_address (avs_address), + .avs_waitrequest (avs_waitrequest), + .avs_write (avs_write), + .avs_read (avs_read), + .avs_byteenable (avs_byteenable), + .avs_burstcount (avs_burstcount), + .avs_readdatavalid (avs_readdatavalid), + .mem_bank_select (mem_bank_select), + + .cp2af_sRxPort (cp2af_sRx_T1), + .af2cp_sTxPort (af2cp_sTx_T0) + ); + + // + // Export the local memory interface signals as vectors so that bank + // selection can use array syntax. + // + logic avs_waitrequest_v[NUM_LOCAL_MEM_BANKS]; + t_local_mem_data avs_readdata_v[NUM_LOCAL_MEM_BANKS]; + logic avs_readdatavalid_v[NUM_LOCAL_MEM_BANKS]; + + genvar b; + generate + for (b = 0; b < NUM_LOCAL_MEM_BANKS; b = b + 1) + begin : lmb + always_comb + begin + // Local memory to AFU signals + avs_waitrequest_v[b] = local_mem[b].waitrequest; + avs_readdata_v[b] = local_mem[b].readdata; + avs_readdatavalid_v[b] = local_mem[b].readdatavalid; + + // Replicate address and write data to all banks. Only + // the request signals have to be bank-specific. + local_mem[b].burstcount = avs_burstcount; + local_mem[b].writedata = avs_writedata; + local_mem[b].address = avs_address; + local_mem[b].byteenable = avs_byteenable; + + // Request a write to this bank? + local_mem[b].write = avs_write && + ($bits(mem_bank_select)'(b) == mem_bank_select); + + // Request a read from this bank? + local_mem[b].read = avs_read && + ($bits(mem_bank_select)'(b) == mem_bank_select); + end + end + endgenerate + + assign avs_waitrequest = avs_waitrequest_v[mem_bank_select]; + assign avs_readdata = avs_readdata_v[mem_bank_select]; + assign avs_readdatavalid = avs_readdatavalid_v[mem_bank_select]; + +endmodule diff --git a/driver/hw/sources.txt b/driver/hw/sources.txt new file mode 100644 index 00000000..23d2cbf7 --- /dev/null +++ b/driver/hw/sources.txt @@ -0,0 +1,116 @@ +vortex_afu.json + ++incdir+. ++incdir+../../rtl ++incdir+../../rtl/shared_memory ++incdir+../../rtl/cache ++incdir+../../rtl/VX_cache ++incdir+../../rtl/interfaces ++incdir+../../rtl/pipe_regs ++incdir+../../rtl/compat + +../../rtl/VX_define_synth.v +../../rtl/VX_define.v +../../rtl/VX_cache/VX_cache_config.v +../../rtl/Vortex_SOC.v +../../rtl/Vortex.v +../../rtl/VX_front_end.v +../../rtl/VX_back_end.v +../../rtl/VX_fetch.v +../../rtl/VX_scheduler.v +../../rtl/VX_execute_unit.v +../../rtl/VX_warp.v +../../rtl/VX_icache_stage.v +../../rtl/VX_gpr_wrapper.v +../../rtl/byte_enabled_simple_dual_port_ram.v +../../rtl/VX_gpgpu_inst.v +../../rtl/VX_writeback.v +../../rtl/VX_countones.v +../../rtl/VX_csr_handler.v +../../rtl/VX_csr_pipe.v +../../rtl/VX_generic_queue_ll.v +../../rtl/VX_warp_scheduler.v +../../rtl/VX_priority_encoder.v +../../rtl/VX_generic_queue.v +../../rtl/pipe_regs/VX_f_d_reg.v +../../rtl/pipe_regs/VX_i_d_reg.v +../../rtl/pipe_regs/VX_d_e_reg.v +../../rtl/VX_gpr.v +../../rtl/VX_gpr_stage.v +../../rtl/VX_dmem_controller.v +../../rtl/VX_alu.v +../../rtl/VX_generic_stack.v +../../rtl/VX_generic_priority_encoder.v +../../rtl/VX_csr_data.v +../../rtl/VX_lsu.v +../../rtl/VX_decode.v +../../rtl/VX_inst_multiplex.v +../../rtl/VX_csr_wrapper.v +../../rtl/VX_priority_encoder_w_mask.v +../../rtl/VX_generic_register.v +../../rtl/VX_lsu_addr_gen.v +../../rtl/compat/VX_mult.v +../../rtl/compat/VX_divide.v +../../rtl/VX_cache/VX_snp_fwd_arb.v +../../rtl/VX_cache/VX_cache_dram_req_arb.v +../../rtl/VX_cache/VX_cache_dfq_queue.v +../../rtl/VX_cache/VX_cache_wb_sel_merge.v +../../rtl/VX_cache/VX_mrv_queue.v +../../rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v +../../rtl/VX_cache/VX_tag_data_access.v +../../rtl/VX_cache/VX_cache.v +../../rtl/VX_cache/VX_cache_core_req_bank_sel.v +../../rtl/VX_cache/VX_cache_req_queue.v +../../rtl/VX_cache/VX_bank.v +../../rtl/VX_cache/VX_cache_miss_resrv.v +../../rtl/VX_cache/VX_fill_invalidator.v +../../rtl/VX_cache/VX_tag_data_structure.v +../../rtl/cache/VX_generic_pe.v +../../rtl/cache/cache_set.v +../../rtl/cache/VX_d_cache.v +../../rtl/cache/VX_Cache_Bank.v +../../rtl/cache/VX_cache_data_per_index.v +../../rtl/cache/VX_d_cache_encapsulate.v +../../rtl/cache/VX_cache_bank_valid.v +../../rtl/cache/VX_cache_data.v +../../rtl/shared_memory/VX_shared_memory_block.v +../../rtl/shared_memory/VX_priority_encoder_sm.v +../../rtl/shared_memory/VX_shared_memory.v +../../rtl/shared_memory/VX_bank_valids.v +../../rtl/interfaces/VX_exec_unit_req_inter.v +../../rtl/interfaces/VX_branch_response_inter.v +../../rtl/interfaces/VX_inst_meta_inter.v +../../rtl/interfaces/VX_join_inter.v +../../rtl/interfaces/VX_icache_response_inter.v +../../rtl/interfaces/VX_gpr_wspawn_inter.v +../../rtl/interfaces/VX_inst_exec_wb_inter.v +../../rtl/interfaces/VX_gpu_dcache_dram_req_inter.v +../../rtl/interfaces/VX_csr_req_inter.v +../../rtl/interfaces/VX_icache_request_inter.v +../../rtl/interfaces/VX_gpu_dcache_res_inter.v +../../rtl/interfaces/VX_frE_to_bckE_req_inter.v +../../rtl/interfaces/VX_dram_req_rsp_inter.v +../../rtl/interfaces/VX_dcache_request_inter.v +../../rtl/interfaces/VX_gpr_data_inter.v +../../rtl/interfaces/VX_dcache_response_inter.v +../../rtl/interfaces/VX_csr_wb_inter.v +../../rtl/interfaces/VX_gpu_dcache_req_inter.v +../../rtl/interfaces/VX_lsu_req_inter.v +../../rtl/interfaces/VX_gpu_snp_req_rsp.v +../../rtl/interfaces/VX_mw_wb_inter.v +../../rtl/interfaces/VX_gpr_jal_inter.v +../../rtl/interfaces/VX_gpu_inst_req_inter.v +../../rtl/interfaces/VX_wstall_inter.v +../../rtl/interfaces/VX_wb_inter.v +../../rtl/interfaces/VX_gpr_clone_inter.v +../../rtl/interfaces/VX_gpr_read_inter.v +../../rtl/interfaces/VX_mem_req_inter.v +../../rtl/interfaces/VX_jal_response_inter.v +../../rtl/interfaces/VX_warp_ctl_inter.v +../../rtl/interfaces/VX_gpu_dcache_snp_req_inter.v +../../rtl/interfaces/VX_gpu_dcache_dram_res_inter.v +../../rtl/interfaces/VX_inst_mem_wb_inter.v + +ccip_interface_reg.sv +ccip_std_afu.sv +vortex_afu.sv \ No newline at end of file diff --git a/driver/hw/vortex_afu.json b/driver/hw/vortex_afu.json new file mode 100644 index 00000000..3c9b3bb3 --- /dev/null +++ b/driver/hw/vortex_afu.json @@ -0,0 +1,37 @@ +{ + "version": 1, + "afu-image": { + "power": 0, + "clock-frequency-high": "auto", + "clock-frequency-low": "auto", + "afu-top-interface": + { + "class": "ccip_std_afu_avalon_mm", + "module-ports" : + [ + { + "class": "cci-p", + "params": + { + "clock": "uClk_usr" + } + }, + { + "class": "local-memory", + "params": + { + "clock": "uClk_usr" + } + } + ] + }, + "accelerator-clusters": + [ + { + "name": "vortex_afu", + "total-contexts": 1, + "accelerator-type-uuid": "35f9452b-25c2-434c-93d5-6f8c60db361c" + } + ] + } +} diff --git a/driver/hw/vortex_afu.sv b/driver/hw/vortex_afu.sv new file mode 100644 index 00000000..0ef03275 --- /dev/null +++ b/driver/hw/vortex_afu.sv @@ -0,0 +1,638 @@ +// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex + +// Interface between CSR and FSM +// All the MMIOs read/write are done from CSR and passed to the FSM for state transitions + +// To be done: +// Change address size to buffer's address size and data size based on IO address size. Check from hello_world + +`include "platform_if.vh" +import local_mem_cfg_pkg::*; +`include "afu_json_info.vh" + +module vortex_afu #( + parameter NUM_LOCAL_MEM_BANKS = 2 +) ( + // global signals + input clk, + input SoftReset, + + // IF signals between CCI and AFU + input t_if_ccip_Rx cp2af_sRxPort, + output t_if_ccip_Tx af2cp_sTxPort, + + // Avalong signals for local memory access + output t_local_mem_data avs_writedata, + input t_local_mem_data avs_readdata, + output t_local_mem_addr avs_address, + input logic avs_waitrequest, + output logic avs_write, + output logic avs_read, + output t_local_mem_byte_mask avs_byteenable, + output t_local_mem_burst_cnt avs_burstcount, + input avs_readdatavalid, + + output logic [$clog2(NUM_LOCAL_MEM_BANKS)-1:0] mem_bank_select +); + +localparam AFU_ID_L = 16'h0002; // AFU ID Lower +localparam AFU_ID_H = 16'h0004; // AFU ID Higher +localparam MEM_ADDRESS = 16'h0040; // AVMM Master Address +localparam MEM_BURSTCOUNT = 16'h0042; // AVMM Master Burst Count +localparam MEM_RDWR = 16'h0044; // AVMM Master Read/Write +localparam MEM_BANK_SELECT = 16'h0064; // Memory bank selection register +localparam READY_FOR_SW_CMD = 16'h0066; // "Ready for sw cmd" register. S/w must poll this register before issuing a read/write command to fsm +localparam MEM_BYTEENABLE = 16'h0068; // Test byteenable + +// Added by Apurve to supporead and writeChange address size to buffer's address size +localparam DATA_SIZE = 16'h0046; // MMIO set by SW to denote the size od data to read/write +localparam BUFFER_IO_ADDRESS = 16'h0048; // MMIO set by SW to denote the buffer address space + +logic [127:0] afu_id = `AFU_ACCEL_UUID; + +// cast c0 header into ReqMmioHdr +t_ccip_c0_ReqMmioHdr mmioHdr; +assign mmioHdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr); + +logic [2:0] mem_RDWR = '0; + +//-- +logic ready_for_sw_cmd; +logic run_vortex; + +logic [15:0] avm_data_size; +t_ccip_clAddr avm_write_buffer_address; +t_ccip_clAddr avm_read_buffer_address; +logic avm_read; +logic avm_write; +t_local_mem_addr avm_address; +t_local_mem_burst_cnt avm_burstcount; +t_local_mem_byte_mask avm_byteenable; + +// Vortex signals + +logic vx_reset; +logic vx_dram_req; +logic vx_dram_req_write; +logic vx_dram_req_read; +logic vx_ebreak; +logic [31:0] vx_dram_req_addr; +logic [31:0] vx_local_addr; +logic [31:0] vx_dram_req_size; +logic [31:0] vx_count; +logic vx_dram_fill_rsp; + +logic [31:0] vx_dram_req_data[15:0]; +logic [31:0] vx_dram_fill_rsp_data[15:0]; +logic vx_dram_fill_accept; +logic [31:0] vx_dram_fill_rsp_addr; +logic [31:0] vx_dram_expected_lat; + +// +// MMIO control threads +// +always@(posedge clk) begin + if(SoftReset) begin + af2cp_sTxPort.c2.hdr <= '0; + af2cp_sTxPort.c2.data <= '0; + af2cp_sTxPort.c2.mmioRdValid <= '0; + avm_address <= '0; + avm_read <= '0; + avm_write <= '0; + avm_burstcount <= 12'd1; + mem_RDWR <= '0; + mem_bank_select <= 1'b1; + + // Change address size to buffer's address size + avm_data_size <= '0; + avm_write_buffer_address <= '0; + avm_read_buffer_address <= '0; + run_vortex <= '0; + end + else begin + af2cp_sTxPort.c2.mmioRdValid <= 0; + avm_read <= mem_RDWR[0] & mem_RDWR[1]; //[0] enable [1] 0-WR,1-RD + avm_write <= mem_RDWR[0] & !mem_RDWR[1]; + + // Added by Apurve. Run vortex whem RDWR is 7 + run_vortex <= mem_RDWR[0] & mem_RDWR[1] & mem_RDWR[2]; + + // set the registers on MMIO write request + // these are user-defined AFU registers at offset 0x40 and 0x41 + if(cp2af_sRxPort.c0.mmioWrValid == 1) + begin + case(mmioHdr.address) + MEM_ADDRESS: avm_address <= t_local_mem_addr'(cp2af_sRxPort.c0.data); + MEM_BURSTCOUNT: avm_burstcount <= cp2af_sRxPort.c0.data[11:0]; + MEM_RDWR: mem_RDWR <= cp2af_sRxPort.c0.data[2:0]; + MEM_BANK_SELECT: mem_bank_select <= $bits(mem_bank_select)'(cp2af_sRxPort.c0.data); + // Added by Apurve to support read and write buffers. Change address size to buffer's address size + DATA_SIZE:avm_data_size <= cp2af_sRxPort.c0.data[15:0]; + + BUFFER_IO_ADDRESS: begin + avm_write_buffer_address <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); + avm_read_buffer_address <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); + end + endcase + end + + // serve MMIO read requests + if(cp2af_sRxPort.c0.mmioRdValid == 1) + begin + af2cp_sTxPort.c2.hdr.tid <= mmioHdr.tid; // copy TID + case(mmioHdr.address) + // AFU header + 16'h0000: af2cp_sTxPort.c2.data <= { + 4'b0001, // Feature type = AFU + 8'b0, // reserved + 4'b0, // afu minor revision = 0 + 7'b0, // reserved + 1'b1, // end of DFH list = 1 + 24'b0, // next DFH offset = 0 + 4'b0, // afu major revision = 0 + 12'b0 // feature ID = 0 + }; + AFU_ID_L: af2cp_sTxPort.c2.data <= afu_id[63:0]; // afu id low + AFU_ID_H: af2cp_sTxPort.c2.data <= afu_id[127:64]; // afu id hi + 16'h0006: af2cp_sTxPort.c2.data <= 64'h0; // next AFU + 16'h0008: af2cp_sTxPort.c2.data <= 64'h0; // reserved + MEM_ADDRESS: af2cp_sTxPort.c2.data <= 64'(avm_address); + MEM_BURSTCOUNT: af2cp_sTxPort.c2.data <= 64'(avm_burstcount); + MEM_RDWR: af2cp_sTxPort.c2.data <= {62'd0, mem_RDWR}; + READY_FOR_SW_CMD: af2cp_sTxPort.c2.data <= ready_for_sw_cmd; + MEM_BANK_SELECT: af2cp_sTxPort.c2.data <= 64'(mem_bank_select); + default: af2cp_sTxPort.c2.data <= 64'h0; + endcase + af2cp_sTxPort.c2.mmioRdValid <= 1; // post response + end else + begin + if (avm_read | avm_write | run_vortex) mem_RDWR[0] <= 0; + end + end +end + + + + + +// FSM + +// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex + +// Interface between CSR and FSM +// All the MMIOs read/write passed from csr are used for state transitions +// Read: local memory to shared buffer +// Write: shared buffer to local memory + +// To be done: +// Review the FSM and implement read/write to shared buffer +// Vortex on/off signal +// check on byteenable and burst signals + +//cp2af_sRxPort -> sRx +//af2cp_sTxPort -> sTx + + +typedef enum logic[3:0] { IDLE, + VX_REQ, + VX_WR_REQ, + VX_RD_REQ, + VX_RSP, + RD_REQ, + RD_RSP, + WR_REQ, + WR_RSP } state_t; + + +// Added by Apurve for shared memory space write/read +t_ccip_clAddr wr_addr; +t_ccip_clAddr rd_addr; +logic [15:0] count; +logic [15:0] count_rsp; +logic start_read; +logic start_write; +t_local_mem_addr local_address; +logic init_avs_read; + +parameter ADDRESS_MAX_BIT = 10; +state_t state; + +assign avs_burstcount = avm_burstcount; +t_local_mem_burst_cnt burstcount; + +assign avs_byteenable = avm_byteenable; + +always_ff @(posedge clk) begin + if(SoftReset) begin + local_address <= '0; + avs_write <= '0; + avs_read <= '0; + state <= IDLE; + burstcount <= 1; + ready_for_sw_cmd <= 0; + count <= 0; + count_rsp <= 0; + vx_reset <= 1'b0; + vx_count <= 0; + end + else begin + case(state) + IDLE: begin + ready_for_sw_cmd <= 1; + + if (avm_write) begin + state <= WR_REQ; + ready_for_sw_cmd <= 0; + count <= 0; + count_rsp <= 0; + end else if (avm_read) begin + init_avs_read <= 1; + state <= RD_REQ; + ready_for_sw_cmd <= 0; + count <= 0; + count_rsp <= 0; + end else if (run_vortex) begin + state <= VX_REQ; + vx_reset <= 1'b1; + ready_for_sw_cmd <= 0; + end + end + + WR_REQ: begin //AVL MM Posted Write + af2cp_sTxPort.c0.valid <= 1'b0; + avs_write <= 0; + if (~avs_waitrequest) + begin + if (count_rsp >= avm_data_size) + begin + state <= WR_RSP; + avs_write <= 0; + end + end + end + + WR_RSP: begin // wait for write response + avm_byteenable <= 64'hffffffffffffffff; + state <= IDLE; + end + + RD_REQ: begin // AVL MM Read non-posted + af2cp_sTxPort.c1.valid <= 1'b0; + if (~avs_waitrequest) begin + if (count_rsp >= avm_data_size) + begin + state <= RD_RSP; + avs_read <= 0; + end + end + end + + RD_RSP: begin + state <= IDLE; + end + + VX_REQ: begin + vx_reset <= 1'b0; + if (vx_dram_req_write) begin + vx_count <= 0; + avs_write <= 1'b1; + state <= VX_WR_REQ; + end + + if (vx_dram_req_read) begin + vx_count <= 0; + avs_read <= 1'b1; + state <= VX_RD_REQ; + end + + if (vx_ebreak) begin + state <= VX_RSP; + end + end + + VX_WR_REQ: begin + avs_write <= 1'b0; + if (vx_count >= vx_dram_req_size) + begin + state <= VX_REQ; + vx_count <= 0; + end + end + + VX_RD_REQ: begin + avs_read <= 1'b0; + vx_dram_fill_rsp <= 1'b0; + if (vx_count >= vx_dram_req_size) + begin + state <= VX_REQ; + vx_count <= 0; + end + end + + VX_RSP: begin + vx_count <= 0; + state <= IDLE; + end + + endcase + end // end else reset +end // posedge clk + + +// Vortex call + Vortex_SOC #() + vx_soc ( + .clk (clk), + .reset (vx_reset), + + // IO + //.io_valid[`NUMBER_CORES-1:0] (), + //.io_data [`NUMBER_CORES-1:0] (), + //.number_cores (), + + // DRAM Dcache Req + .out_dram_req (vx_dram_req), + .out_dram_req_write (vx_dram_req_write), + .out_dram_req_read (vx_dram_req_read), + .out_dram_req_addr (vx_dram_req_addr), + .out_dram_req_size (vx_dram_req_size), + .out_dram_req_data (vx_dram_req_data), + .out_dram_expected_lat (vx_dram_expected_lat), + + // DRAM Dcache Res + .out_dram_fill_accept (vx_dram_fill_accept), + .out_dram_fill_rsp (vx_dram_fill_rsp), + .out_dram_fill_rsp_addr (vx_dram_fill_rsp_addr), + .out_dram_fill_rsp_data (vx_dram_fill_rsp_data), + + //.l3c_snp_req (), + //.l3c_snp_req_addr (), + //.l3c_snp_req_delay (), + + .out_ebreak (vx_ebreak) + ); + + +// Local memory read/write address +//assign avs_address = (vx_dram_req ? (vx_count ? vx_local_addr : vx_dram_req_addr) : (count ? local_address : avm_address)); +assign avs_address = (((state == VX_WR_REQ) || (state == VX_RD_REQ)) ? (vx_count ? vx_local_addr : vx_dram_req_addr) : (count ? local_address : avm_address)); + + + +// Vortex DRAM requests and responses +// Handling of read/write data and vx_dram_req_size +// Is vx_dram_fill_accept for backpressure? +always_ff @(posedge clk) begin + if (state == VX_WR_REQ) begin + if (!avs_waitrequest & (vx_count < vx_dram_req_size)) begin + avs_write <= 1'b1; + //avs_writedata <= vx_dram_req_data; + avs_writedata[31:0] = vx_dram_req_data[0]; + avs_writedata[63:32] = vx_dram_req_data[1]; + avs_writedata[95:64] = vx_dram_req_data[2]; + avs_writedata[127:96] = vx_dram_req_data[3]; + avs_writedata[159:128] = vx_dram_req_data[4]; + avs_writedata[191:160] = vx_dram_req_data[5]; + avs_writedata[223:192] = vx_dram_req_data[6]; + avs_writedata[255:224] = vx_dram_req_data[7]; + avs_writedata[287:256] = vx_dram_req_data[8]; + avs_writedata[319:288] = vx_dram_req_data[9]; + avs_writedata[351:320] = vx_dram_req_data[10]; + avs_writedata[383:352] = vx_dram_req_data[11]; + avs_writedata[415:384] = vx_dram_req_data[12]; + avs_writedata[447:416] = vx_dram_req_data[13]; + avs_writedata[479:448] = vx_dram_req_data[14]; + avs_writedata[511:480] = vx_dram_req_data[15]; + + vx_local_addr <= (vx_count ? vx_local_addr + 1 : vx_dram_req_addr + 1); + + // Update the count value based on the number of bytes written + vx_count <= vx_count + 64; + + if ((vx_dram_req_size - vx_count) < 64) + begin + avm_byteenable <= 64'hffffffffffffffff >> (64 - (vx_dram_req_size - vx_count)); + end else + begin + avm_byteenable <= 64'hffffffffffffffff; + end + + end + end +end + +always_ff @(posedge clk) begin + //if (SoftReset) begin + if (vx_reset) begin + vx_dram_fill_rsp <= 1'b0; + //vx_dram_fill_rsp_data <= 0; + vx_dram_fill_rsp_data[0] <= 0; + vx_dram_fill_rsp_data[1] <= 0; + vx_dram_fill_rsp_data[2] <= 0; + vx_dram_fill_rsp_data[3] <= 0; + vx_dram_fill_rsp_data[4] <= 0; + vx_dram_fill_rsp_data[5] <= 0; + vx_dram_fill_rsp_data[6] <= 0; + vx_dram_fill_rsp_data[7] <= 0; + vx_dram_fill_rsp_data[8] <= 0; + vx_dram_fill_rsp_data[9] <= 0; + vx_dram_fill_rsp_data[10] <= 0; + vx_dram_fill_rsp_data[11] <= 0; + vx_dram_fill_rsp_data[12] <= 0; + vx_dram_fill_rsp_data[13] <= 0; + vx_dram_fill_rsp_data[14] <= 0; + vx_dram_fill_rsp_data[15] <= 0; + end + + if (state == VX_RD_REQ) begin + if (avs_readdatavalid & vx_dram_fill_accept) begin + avs_read <= 1'b1; + vx_dram_fill_rsp <= 1'b1; + //vx_dram_fill_rsp_data <= avs_readdata; + vx_dram_fill_rsp_data[0] <= avs_readdata[31:0]; + vx_dram_fill_rsp_data[1] <= avs_readdata[63:32]; + vx_dram_fill_rsp_data[2] <= avs_readdata[95:64]; + vx_dram_fill_rsp_data[3] <= avs_readdata[127:96]; + vx_dram_fill_rsp_data[4] <= avs_readdata[159:128]; + vx_dram_fill_rsp_data[5] <= avs_readdata[191:160]; + vx_dram_fill_rsp_data[6] <= avs_readdata[223:192]; + vx_dram_fill_rsp_data[7] <= avs_readdata[255:224]; + vx_dram_fill_rsp_data[8] <= avs_readdata[287:256]; + vx_dram_fill_rsp_data[9] <= avs_readdata[319:288]; + vx_dram_fill_rsp_data[10] <= avs_readdata[351:320]; + vx_dram_fill_rsp_data[11] <= avs_readdata[383:352]; + vx_dram_fill_rsp_data[12] <= avs_readdata[415:384]; + vx_dram_fill_rsp_data[13] <= avs_readdata[447:416]; + vx_dram_fill_rsp_data[14] <= avs_readdata[479:448]; + vx_dram_fill_rsp_data[15] <= avs_readdata[511:480]; + vx_local_addr <= (vx_count ? vx_local_addr + 1 : vx_dram_req_addr + 1); + vx_dram_fill_rsp_addr <= vx_local_addr; + // Update the count value based on the number of bytes written + vx_count <= vx_count + 64; + + end + end +end + + + + +// Read from local memory (avs_readdata) and write to shared space +// Implement write header +always_ff @(posedge clk) begin + if (state == RD_REQ & avs_readdatavalid & !cp2af_sRxPort.c1TxAlmFull & count < avm_data_size & !avs_waitrequest & start_write) + begin + wr_addr <= (count? wr_addr + 1 : avm_write_buffer_address + 1); + local_address <= (count? local_address + 1 : avm_address + 1); + start_write <= 1'b0; + end +end + +// Write header defines the request to the FIU +t_ccip_c1_ReqMemHdr wr_hdr; + +always_comb +begin + wr_hdr = t_ccip_c1_ReqMemHdr'(0); + + // Virtual address (MPF virtual addressing is enabled) + wr_hdr.address = (count? wr_addr: avm_write_buffer_address); + + // Start of packet is true (single line write) + wr_hdr.sop = 1'b1; +end + +// Send write requests to the FIU +always_ff @(posedge clk) +begin + if (SoftReset) + begin + af2cp_sTxPort.c1.hdr <= '0; + af2cp_sTxPort.c1.data <= '0; + af2cp_sTxPort.c1.valid <= '0; + end + + // Generate a write request when needed and the FIU isn't full + if (state == RD_REQ & avs_readdatavalid & !cp2af_sRxPort.c1TxAlmFull & count < avm_data_size & !avs_waitrequest & start_write) + begin + af2cp_sTxPort.c1.hdr <= wr_hdr; + af2cp_sTxPort.c1.data <= t_ccip_clData'(avs_readdata); + af2cp_sTxPort.c1.valid <= 1'b1; + start_write <= 1'b0; + count <= count + 64; + end +end + +// Write response +always_ff @(posedge clk) +begin + if (SoftReset) + begin + start_write <= 1'b1; + end + + // Generate a read request when needed and the FIU isn't full + if (state == RD_REQ & cp2af_sRxPort.c1.rspValid) + begin + count_rsp <= count_rsp + 64; + start_write <= 1'b1; + init_avs_read <= 1'b1; + end +end + + +// avs_read control + +always_ff @(posedge clk) +begin + if (SoftReset) + begin + init_avs_read <= 1'b0; + end + + if (init_avs_read & state <= RD_REQ) + begin + avs_read <= 1'b1; + init_avs_read <= 1'b0; + end else + begin + avs_read <= 1'b0; + end +end + + + + +// Write to local memory (avs_writedata) and read from shared space +// Implement read header +always_ff @(posedge clk) begin + if (SoftReset) + begin + rd_addr <= 0; + local_address <= 0; + end + + if (state == WR_REQ & !cp2af_sRxPort.c0TxAlmFull & count < avm_data_size & !avs_waitrequest & start_read) + begin + // Read address + 1 gives address for next block. Each block is 64B + rd_addr <= (count? rd_addr + 1 : avm_read_buffer_address + 1); + local_address <= (count? local_address + 1 : avm_address); + start_read <= 1'b0; + end +end + +// Read header defines the request to the FIU +t_ccip_c0_ReqMemHdr rd_hdr; + +always_comb +begin + rd_hdr = t_ccip_c0_ReqMemHdr'(0); + rd_hdr.address = (count? rd_addr : avm_read_buffer_address); +end + +// Send read requests to the FIU +always_ff @(posedge clk) +begin + if (SoftReset) + begin + af2cp_sTxPort.c0.hdr <= '0; + af2cp_sTxPort.c0.valid <= '0; + end + + // Generate a read request when needed and the FIU isn't full + if (state == WR_REQ & !cp2af_sRxPort.c0TxAlmFull & count < avm_data_size & !avs_waitrequest & start_read) + begin + af2cp_sTxPort.c0.hdr <= rd_hdr; + af2cp_sTxPort.c0.valid <= 1'b1; + start_read <= 1'b0; + count <= count + 64; + end +end + +// Read response +always_ff @(posedge clk) +begin + if (SoftReset) + begin + start_read <= 1'b1; + avm_byteenable <= 64'hffffffffffffffff; + end + + // Generate a read request when needed and the FIU isn't full + if (state == WR_REQ & cp2af_sRxPort.c0.rspValid) + begin + if ((avm_data_size - count_rsp) < 64) + begin + avm_byteenable <= 64'hffffffffffffffff >> (64 - (avm_data_size - count_rsp)); + end else + begin + avm_byteenable <= 64'hffffffffffffffff; + end + avs_writedata <= cp2af_sRxPort.c0.data; + avs_write <= 1; + count_rsp <= count_rsp + 64; + start_read <= 1'b1; + end +end + +endmodule diff --git a/opae/opae_setup.sh b/driver/opae_setup.sh similarity index 100% rename from opae/opae_setup.sh rename to driver/opae_setup.sh diff --git a/driver/set_env.sh b/driver/set_env.sh new file mode 100644 index 00000000..8d94b148 --- /dev/null +++ b/driver/set_env.sh @@ -0,0 +1,6 @@ +source /tools/reconfig/intel/19.3/rg_intel_fpga_end_19.3.sh +export PATH=/tools/opae/1.4.0/bin:/tools/reconfig/intel/19.3/modelsim_ase/bin:$PATH +export LD_LIBRARY_PATH=/tools/opae/1.4.0/lib:$PATH +export QUARTUS_HOME=$QUARTUS_ROOTDIR +export MTI_HOME=/tools/reconfig/intel/19.3/modelsim_ase +export FPGA_FAMILY=arria10 diff --git a/driver/sw/Makefile b/driver/sw/Makefile new file mode 100644 index 00000000..5811f3c3 --- /dev/null +++ b/driver/sw/Makefile @@ -0,0 +1,19 @@ + + +all: opae rtlsim simx + +opae: + $(MAKE) -C opae + +rtlsim: + $(MAKE) -C rtlsim + +simx: + $(MAKE) -C simx + +clean: + $(MAKE) clean -C opae + $(MAKE) clean -C rtlsim + $(MAKE) clean -C simx + +.PHONY: all opae rtlsim simx clean \ No newline at end of file diff --git a/driver/sw/include/vortex.h b/driver/sw/include/vortex.h new file mode 100644 index 00000000..6d852382 --- /dev/null +++ b/driver/sw/include/vortex.h @@ -0,0 +1,67 @@ +#ifndef __VX_DRIVER_H__ +#define __VX_DRIVER_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void* vx_device_h; + +typedef void* vx_buffer_h; + +#define VX_LOCAL_MEM_SIZE 0xffffffff + +#define VX_ALLOC_BASE_ADDR 0x10000000 + +#define VX_KERNEL_BASE_ADDR 0x80000000 + +#define VX_CACHE_LINESIZE 64 + +// open the device and connect to it +int vx_dev_open(vx_device_h* hdevice); + +// Close the device when all the operations are done +int vx_dev_close(vx_device_h hdevice); + +// Allocate shared buffer with device +int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hbuffer); + +// Get host pointer address +volatile void* vx_host_ptr(vx_buffer_h hbuffer); + +// release buffer +int vx_buf_release(vx_buffer_h hbuffer); + +// allocate device memory and return address +int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr); + +// Copy bytes from device local memory to buffer +int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size); + +// Copy bytes from buffer to device local memory +int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t src_offset); + +// Copy bytes from device local memory to buffer +int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t dst_offset); + +// Start device execution +int vx_start(vx_device_h hdevice); + +// Wait for device ready with milliseconds timeout +int vx_ready_wait(vx_device_h hdevice, long long timeout); + +////////////////////////////// UTILITY FUNCIONS /////////////////////////////// + +// upload kernel bytes to device +int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_t size); + +// upload kernel file to device +int vx_upload_kernel_file(vx_device_h device, const char* filename); + +#ifdef __cplusplus +} +#endif + +#endif // __VX_DRIVER_H__ diff --git a/driver/sw/opae/Makefile b/driver/sw/opae/Makefile new file mode 100644 index 00000000..05694604 --- /dev/null +++ b/driver/sw/opae/Makefile @@ -0,0 +1,66 @@ + +CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I../include -I/tools/opae/1.4.0/include + +LDFLAGS += -L/tools/opae/1.4.0/lib + +# stack execution protection +LDFLAGS +=-z noexecstack + +# data relocation and projection +LDFLAGS +=-z relro -z now + +# stack buffer overrun detection +CXXFLAGS +=-fstack-protector + +# Position independent code +CXXFLAGS += -fPIC + +LDFLAGS += -luuid + +LDFLAGS += -shared + +FPGA_LIBS += -lopae-c + +ASE_LIBS += -lopae-c-ase + +LIB_DIR=../lib + +ASE_DIR = ase + +PROJECT = libvortex.so + +PROJECT_ASE = $(ASE_DIR)/libvortex.so + +AFU_JSON_INFO = vortex_afu.h + +SRCS = vortex.cpp ../vx_utils.cpp + +all: $(PROJECT) $(PROJECT_ASE) + +# AFU info from JSON file, including AFU UUID +$(AFU_JSON_INFO): ../../hw/vortex_afu.json + afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) $(FPGA_LIBS) -o $@ + +$(PROJECT_ASE): $(SRCS) $(ASE_DIR) + $(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) $(ASE_LIBS) -o $@ + +vortex.o: vortex.cpp $(AFU_JSON_INFO) + $(CC) $(CXXFLAGS) -c vortex.cpp -o $@ + +$(ASE_DIR): + mkdir -p ase + +.depend: $(SRCS) $(AFU_JSON_INFO) + $(CXX) $(CXXFLAGS) -MM $(SRCS) > .depend; + +clean: + rm -rf $(PROJECT) $(PROJECT_ASE) $(AFU_JSON_INFO) *.o .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/driver/sw/opae/vortex.cpp b/driver/sw/opae/vortex.cpp new file mode 100755 index 00000000..f2bf80d8 --- /dev/null +++ b/driver/sw/opae/vortex.cpp @@ -0,0 +1,349 @@ +#include +#include +#include +#include +#include +#include + +#include +#include +#include "vortex_afu.h" + +// MMIO Address Mappings +#define MMIO_COPY_IO_ADDRESS 0X120 +#define MMIO_COPY_AVM_ADDRESS 0x100 +#define MMIO_COPY_DATA_SIZE 0X118 + +#define MMIO_CMD_TYPE 0X110 +#define MMIO_READY_FOR_CMD 0X198 + +#define MMIO_CMD_TYPE_READ 0 +#define MMIO_CMD_TYPE_WRITE 1 +#define MMIO_CMD_TYPE_START 2 +#define MMIO_CMD_TYPE_SNOOP 3 + +#define CHECK_RES(_expr) \ + do { \ + fpga_result res = _expr; \ + if (res == FPGA_OK) \ + break; \ + printf("OPAE Error: '%s' returned %d!\n", #_expr, (int)res); \ + return -1; \ + } while (false) + +/////////////////////////////////////////////////////////////////////////////// + +typedef struct vx_device_ { + fpga_handle fpga; + size_t mem_allocation; +} vx_device_t; + +typedef struct vx_buffer_ { + uint64_t wsid; + volatile void* host_ptr; + uint64_t io_addr; + fpga_handle fpga; + size_t size; +} vx_buffer_t; + +static size_t align_size(size_t size) { + return VX_CACHE_LINESIZE * ((size + VX_CACHE_LINESIZE - 1) / VX_CACHE_LINESIZE); +} + +/////////////////////////////////////////////////////////////////////////////// + +// Search for an accelerator matching the requested UUID and connect to it +// Convert this to void if required as storing the fpga_handle to params variable +extern int vx_dev_open(vx_device_h* hdevice) { + fpga_properties filter = NULL; + fpga_result res; + fpga_guid guid; + fpga_token accel_token; + uint32_t num_matches; + fpga_handle accel_handle; + vx_device_t* device; + + if (NULL == hdevice) + return -1; + + // Set up a filter that will search for an accelerator + fpgaGetProperties(NULL, &filter); + fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); + + // Add the desired UUID to the filter + uuid_parse(AFU_ACCEL_UUID, guid); + fpgaPropertiesSetGUID(filter, guid); + + // Do the search across the available FPGA contexts + num_matches = 1; + fpgaEnumerate(&filter, 1, &accel_token, 1, &num_matches); + + // Not needed anymore + fpgaDestroyProperties(&filter); + + if (num_matches < 1) { + fprintf(stderr, "Accelerator %s not found!\n", AFU_ACCEL_UUID); + return NULL; + } + + // Open accelerator + res = fpgaOpen(accel_token, &accel_handle, 0); + if (FPGA_OK != res) { + return NULL; + } + + // Done with token + fpgaDestroyToken(&accel_token); + + // allocate device object + device = (vx_device_t*)malloc(sizeof(vx_device_t)); + if (NULL == device) { + fpgaClose(accel_handle); + return NULL; + } + + device->fpga = accel_handle; + device->mem_allocation = VX_ALLOC_BASE_ADDR; + + *hdevice = device; + + return 0; +} + +// Close the fpga when all the operations are done +extern int vx_dev_close(vx_device_h hdevice) { + if (NULL == hdevice) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + fpgaClose(device->fpga); + + free(device); + + return 0; +} + +extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr) { + if (NULL == hdevice + || NULL == dev_maddr + || 0 >= size) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + size_t asize = align_size(size); + if (device->mem_allocation + asize > VX_ALLOC_BASE_ADDR) + return -1; + + *dev_maddr = device->mem_allocation; + device->mem_allocation += asize; + + return 0; +} + +extern int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hbuffer) { + fpga_result res; + void* host_ptr; + uint64_t wsid; + uint64_t io_addr; + vx_buffer_t* buffer; + + if (NULL == hdevice + || 0 >= size + || NULL == hbuffer) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + size_t asize = align_size(size); + + res = fpgaPrepareBuffer(device->fpga, asize, &host_ptr, &wsid, 0); + if (FPGA_OK != res) { + return -1; + } + + // Get the physical address of the buffer in the accelerator + res = fpgaGetIOAddress(device->fpga, wsid, &io_addr); + if (FPGA_OK != res) { + fpgaReleaseBuffer(device->fpga, wsid); + return -1; + } + + // allocate buffer object + buffer = (vx_buffer_t*)malloc(sizeof(vx_buffer_t)); + if (NULL == buffer) { + fpgaReleaseBuffer(device->fpga, wsid); + return -1; + } + + buffer->wsid = wsid; + buffer->host_ptr = host_ptr; + buffer->io_addr = io_addr; + buffer->fpga = device->fpga; + buffer->size = size; + + *hbuffer = buffer; + + return 0; +} + +extern volatile void* vx_host_ptr(vx_buffer_h hbuffer) { + vx_buffer_t* buffer = ((vx_buffer_t*)hbuffer); + if (NULL == buffer) + return NULL; + + return buffer->host_ptr; +} + +extern int vx_buf_release(vx_buffer_h hbuffer) { + vx_buffer_t* buffer = ((vx_buffer_t*)hbuffer); + if (NULL == buffer) + return -1; + + fpgaReleaseBuffer(buffer->fpga, buffer->wsid); + + free(buffer); + + return 0; +} + +// Check if HW is ready for SW +static int ready_for_sw(fpga_handle hdevice) { + uint64_t data = 0; + struct timespec sleep_time; + +#ifdef USE_ASE + sleep_time.tv_sec = 1; + sleep_time.tv_nsec = 0; +#else + sleep_time.tv_sec = 0; + sleep_time.tv_nsec = 1000000; +#endif + + do { + CHECK_RES(fpgaReadMMIO64(hdevice, 0, MMIO_READY_FOR_CMD, &data)); + nanosleep(&sleep_time, NULL); + } while (data != 0x1); + + return 0; +} + +extern int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t src_offset) { + if (NULL == hbuffer + || 0 >= size) + return -1; + + vx_buffer_t* buffer = ((vx_buffer_t*)hbuffer); + + // bound checking + if (size + src_offset > buffer->size) + return -1; + + // Ensure ready for new command + if (ready_for_sw(buffer->fpga) != 0) + return -1; + + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_AVM_ADDRESS, dev_maddr)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_IO_ADDRESS, (buffer->io_addr + src_offset)/VX_CACHE_LINESIZE)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_DATA_SIZE, size)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_CMD_TYPE, MMIO_CMD_TYPE_WRITE)); + + // Wait for the write operation to finish + return ready_for_sw(buffer->fpga); +} + +extern int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t dest_offset) { + if (NULL == hbuffer + || 0 >= size) + return -1; + + vx_buffer_t* buffer = ((vx_buffer_t*)hbuffer); + + // bound checking + if (size + dest_offset > buffer->size) + return -1; + + // Ensure ready for new command + if (ready_for_sw(buffer->fpga) != 0) + return -1; + + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_AVM_ADDRESS, dev_maddr)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_IO_ADDRESS, (buffer->io_addr + dest_offset)/VX_CACHE_LINESIZE)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_DATA_SIZE, size)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_CMD_TYPE, MMIO_CMD_TYPE_READ)); + + // Wait for the write operation to finish + return ready_for_sw(buffer->fpga); +} + +extern int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size) { + if (NULL == hbuffer + || 0 >= size) + return -1; + + vx_buffer_t* buffer = ((vx_buffer_t*)hbuffer); + + // bound checking + if (size + src_offset > buffer->size) + return -1; + + // Ensure ready for new command + if (ready_for_sw(buffer->fpga) != 0) + return -1; + + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_AVM_ADDRESS, dev_maddr)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_IO_ADDRESS, (buffer->io_addr + src_offset)/VX_CACHE_LINESIZE)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_COPY_DATA_SIZE, size)); + CHECK_RES(fpgaWriteMMIO64(buffer->fpga, 0, MMIO_CMD_TYPE, MMIO_CMD_TYPE_SNOOP)); + + // Wait for the write operation to finish + return ready_for_sw(buffer->fpga); + return 0; +} + +extern int vx_start(vx_device_h hdevice) { + if (NULL == hdevice) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + // Ensure ready for new command + if (ready_for_sw(device->fpga) != 0) + return -1; + + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, MMIO_CMD_TYPE_START)); + + return 0; +} + +extern int vx_ready_wait(vx_device_h hdevice, long long timeout) { + if (NULL == hdevice) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + uint64_t data = 0; + struct timespec sleep_time; + +#ifdef USE_ASE + sleep_time.tv_sec = 1; + sleep_time.tv_nsec = 0; +#else + sleep_time.tv_sec = 0; + sleep_time.tv_nsec = 1000000; +#endif + + // to milliseconds + long long sleep_time_ms = (sleep_time.tv_sec * 1000) + (sleep_time.tv_nsec / 1000000); + + do { + CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_READY_FOR_CMD, &data)); + nanosleep(&sleep_time, NULL); + sleep_time_ms -= sleep_time_ms; + if (timeout <= sleep_time_ms) + break; + } while (data != 0x1); + + return 0; +} \ No newline at end of file diff --git a/driver/sw/rtlsim/Makefile b/driver/sw/rtlsim/Makefile new file mode 100644 index 00000000..4a1e82de --- /dev/null +++ b/driver/sw/rtlsim/Makefile @@ -0,0 +1,49 @@ +#CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors +CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors + +#USE_MULTICORE=1 + +CFLAGS += -I../../include -I../../../../rtl/simulate + +CFLAGS += -fPIC + +CFLAGS += -DUSE_RTLSIM + +LDFLAGS += -shared -pthread + +ifdef USE_MULTICORE + CFLAGS += -DUSE_MULTICORE + RTL_TOP = Vortex_SOC +else + RTL_TOP = Vortex +endif + +SRCS = vortex.cpp ../vx_utils.cpp ../../../rtl/simulate/$(RTL_TOP).cpp + +RTL_INCLUDE = -I../../../rtl -I../../../rtl/interfaces -I../../../rtl/cache -I../../../rtl/VX_cache -I../../../rtl/shared_memory -I../../../rtl/pipe_regs -I../../../rtl/compat + +THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') +VL_FLAGS += --threads $(THREADS) + +VL_FLAGS += -Wno-UNOPTFLAT -Wno-WIDTH + +VL_FLAGS += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN + +# Debugigng +VL_FLAGS += --trace -DVL_DEBUG=1 +CFLAGS += -DVCD_OUTPUT + +PROJECT = libvortex.so + +all: $(PROJECT) + +.PHONY: build_config +build_config: + (cd ../../../rtl && ./gen_config.py --rtl_locations) + +$(PROJECT): $(SRCS) build_config + verilator --exe --cc $(RTL_TOP).v $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) + make -j -C obj_dir -f V$(RTL_TOP).mk + +clean: + rm -rf $(PROJECT) obj_dir \ No newline at end of file diff --git a/driver/sw/rtlsim/vortex.cpp b/driver/sw/rtlsim/vortex.cpp new file mode 100644 index 00000000..50f2c599 --- /dev/null +++ b/driver/sw/rtlsim/vortex.cpp @@ -0,0 +1,327 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef USE_MULTICORE +#include +#else +#include +#endif + +#define PAGE_SIZE 4096 + +#define CHECK_RES(_expr) \ + do { \ + fpga_result res = _expr; \ + if (res == FPGA_OK) \ + break; \ + printf("OPAE Error: '%s' returned %d!\n", #_expr, (int)res); \ + return -1; \ + } while (false) + +/////////////////////////////////////////////////////////////////////////////// + +static size_t align_size(size_t size) { + return VX_CACHE_LINESIZE * ((size + VX_CACHE_LINESIZE - 1) / VX_CACHE_LINESIZE); +} + +/////////////////////////////////////////////////////////////////////////////// + +class vx_device; + +class vx_buffer { +public: + vx_buffer(size_t size, vx_device* device) + : size_(size) + , device_(device) { + auto aligned_asize = align_size(size); + data_ = malloc(aligned_asize); + } + + ~vx_buffer() { + if (data_) { + free(data_); + } + } + + void* data() const { + return data_; + } + + size_t size() const { + return size_; + } + + vx_device* device() const { + return device_; + } + +private: + size_t size_; + vx_device* device_; + void* data_; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class vx_device { +public: + vx_device() + : is_done_(false) + , mem_allocation_(VX_ALLOC_BASE_ADDR) + , vortex_(&ram_) { + thread_ = new std::thread(__thread_proc__, this); + } + + ~vx_device() { + if (thread_) { + mutex_.lock(); + is_done_ = true; + mutex_.unlock(); + + thread_->join(); + delete thread_; + } + } + + int alloc_local_mem(size_t size, size_t* dev_maddr) { + size_t asize = align_size(size); + if (mem_allocation_ + asize > VX_LOCAL_MEM_SIZE) + return -1; + *dev_maddr = mem_allocation_; + mem_allocation_ += asize; + return 0; + } + + int upload(void* src, size_t dest_addr, size_t size, size_t src_offset) { + size_t asize = align_size(size); + if (dest_addr + asize > ram_.size()) + return -1; + + /*printf("VXDRV: upload %d bytes to 0x%x\n", size, dest_addr); + for (int i = 0; i < size; i += 4) { + printf("mem-write: 0x%x <- 0x%x\n", dest_addr + i, *(uint32_t*)((uint8_t*)src + src_offset + i)); + }*/ + + ram_.write(dest_addr, asize, (uint8_t*)src + src_offset); + return 0; + } + + int download(const void* dest, size_t src_addr, size_t size, size_t dest_offset) { + size_t asize = align_size(size); + if (src_addr + asize > ram_.size()) + return -1; + + ram_.read(src_addr, asize, (uint8_t*)dest + dest_offset); + + /*printf("VXDRV: download %d bytes from 0x%x\n", size, src_addr); + for (int i = 0; i < size; i += 4) { + printf("mem-read: 0x%x -> 0x%x\n", src_addr + i, *(uint32_t*)((uint8_t*)dest + dest_offset + i)); + }*/ + + return 0; + } + + int flush_caches(size_t dev_maddr, size_t size) { + + mutex_.lock(); + vortex_.flush_caches(dev_maddr, size); + mutex_.unlock(); + + return 0; + } + + int start() { + + mutex_.lock(); + vortex_.reset(); + mutex_.unlock(); + + return 0; + } + + int wait(long long timeout) { + auto timeout_sec = (timeout < 0) ? timeout : (timeout / 1000); + for (;;) { + mutex_.lock(); + bool is_busy = vortex_.is_busy(); + mutex_.unlock(); + + if (!is_busy || 0 == timeout_sec--) + break; + + std::this_thread::sleep_for(std::chrono::seconds(1)); + } + return 0; + } + +private: + + void thread_proc() { + std::cout << "Device ready..." << std::endl; + + for (;;) { + mutex_.lock(); + bool is_done = is_done_; + mutex_.unlock(); + + if (is_done) + break; + + mutex_.lock(); + vortex_.step(); + mutex_.unlock(); + } + + std::cout << "Device shutdown..." << std::endl; + } + + static void __thread_proc__(vx_device* device) { + device->thread_proc(); + } + + bool is_done_; + size_t mem_allocation_; + RAM ram_; +#ifdef USE_MULTICORE + Vortex_SOC vortex_; +#else + Vortex vortex_; +#endif + std::thread* thread_; + std::mutex mutex_; +}; + +/////////////////////////////////////////////////////////////////////////////// + +extern int vx_dev_open(vx_device_h* hdevice) { + if (NULL == hdevice) + return -1; + + *hdevice = new vx_device(); + + return 0; +} + +extern int vx_dev_close(vx_device_h hdevice) { + if (nullptr == hdevice) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + delete device; + + return 0; +} + +extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr) { + if (NULL == hdevice + || NULL == dev_maddr + || 0 >= size) + return -1; + + vx_device *device = ((vx_device*)hdevice); + return device->alloc_local_mem(size, dev_maddr); +} + +extern int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size) { + if (NULL == hdevice + || 0 >= size) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + return device->flush_caches(dev_maddr, size); +} + + +extern int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hbuffer) { + if (nullptr == hdevice + || 0 >= size + || NULL == hbuffer) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + auto buffer = new vx_buffer(size, device); + if (nullptr == buffer->data()) { + delete buffer; + return -1; + } + + *hbuffer = buffer; + + return 0; +} + +extern volatile void* vx_host_ptr(vx_buffer_h hbuffer) { + if (nullptr == hbuffer) + return nullptr; + + vx_buffer* buffer = ((vx_buffer*)hbuffer); + + return buffer->data(); +} + +extern int vx_buf_release(vx_buffer_h hbuffer) { + if (nullptr == hbuffer) + return -1; + + vx_buffer* buffer = ((vx_buffer*)hbuffer); + + delete buffer; + + return 0; +} + +extern int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t src_offset) { + if (nullptr == hbuffer + || 0 >= size) + return -1; + + auto buffer = (vx_buffer*)hbuffer; + + if (size + src_offset > buffer->size()) + return -1; + + return buffer->device()->upload(buffer->data(), dev_maddr, size, src_offset); +} + +extern int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t dest_offset) { + if (nullptr == hbuffer + || 0 >= size) + return -1; + + auto buffer = (vx_buffer*)hbuffer; + + if (size + dest_offset > buffer->size()) + return -1; + + return buffer->device()->download(buffer->data(), dev_maddr, size, dest_offset); +} + +extern int vx_start(vx_device_h hdevice) { + if (nullptr == hdevice) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + return device->start(); +} + +extern int vx_ready_wait(vx_device_h hdevice, long long timeout) { + if (nullptr == hdevice) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + return device->wait(timeout); +} diff --git a/driver/sw/simx/Makefile b/driver/sw/simx/Makefile new file mode 100644 index 00000000..7b07b3e0 --- /dev/null +++ b/driver/sw/simx/Makefile @@ -0,0 +1,37 @@ +CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors +#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors + +MAX_WARPS ?= 8 +MAX_THREADS ?= 4 + +CFLAGS += -I../../include -I../../../../simX/include + +CFLAGS += -fPIC + +CFLAGS += -DUSE_SIMX + +CFLAGS += -DMAX_WARPS=$(MAX_WARPS) -DMAX_THREADS=$(MAX_THREADS) + +LDFLAGS += -shared -pthread + +SRCS = vortex.cpp ../vx_utils.cpp ../../../simX/args.cpp ../../../simX/mem.cpp ../../../simX/core.cpp ../../../simX/instruction.cpp ../../../simX/enc.cpp ../../../simX/util.cpp + +RTL_TOP = ../../../simX/cache_simX.v + +RTL_INCLUDE = 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VX_CACHE_LINESIZE); +} + +/////////////////////////////////////////////////////////////////////////////// + +class vx_device; + +class vx_buffer { +public: + vx_buffer(size_t size, vx_device* device) + : size_(size) + , device_(device) { + auto aligned_asize = align_size(size); + data_ = malloc(aligned_asize); + } + + ~vx_buffer() { + if (data_) { + free(data_); + } + } + + void* data() const { + return data_; + } + + size_t size() const { + return size_; + } + + vx_device* device() const { + return device_; + } + +private: + size_t size_; + vx_device* device_; + void* data_; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class vx_device { +public: + vx_device() + : is_done_(false) + , is_running_(false) + , mem_allocation_(VX_ALLOC_BASE_ADDR) + , thread_(__thread_proc__, this) + {} + + ~vx_device() { + mutex_.lock(); + is_done_ = true; + mutex_.unlock(); + + thread_.join(); + } + + int alloc_local_mem(size_t size, size_t* dev_maddr) { + size_t asize = align_size(size); + if (mem_allocation_ + asize > VX_LOCAL_MEM_SIZE) + return -1; + *dev_maddr = mem_allocation_; + mem_allocation_ += asize; + return 0; + } + + int upload(void* src, size_t dest_addr, size_t size, size_t src_offset) { + size_t asize = align_size(size); + if (dest_addr + asize > ram_.size()) + return -1; + + /*printf("VXDRV: upload %d bytes to 0x%x\n", size, dest_addr); + for (int i = 0; i < size; i += 4) { + printf("mem-write: 0x%x <- 0x%x\n", dest_addr + i, *(uint32_t*)((uint8_t*)src + src_offset + i)); + }*/ + + ram_.write(dest_addr, asize, (uint8_t*)src + src_offset); + return 0; + } + + int download(const void* dest, size_t src_addr, size_t size, size_t dest_offset) { + size_t asize = align_size(size); + if (src_addr + asize > ram_.size()) + return -1; + + ram_.read(src_addr, asize, (uint8_t*)dest + dest_offset); + + /*printf("VXDRV: download %d bytes from 0x%x\n", size, src_addr); + for (int i = 0; i < size; i += 4) { + printf("mem-read: 0x%x -> 0x%x\n", src_addr + i, *(uint32_t*)((uint8_t*)dest + dest_offset + i)); + }*/ + + return 0; + } + + int start() { + + mutex_.lock(); + is_running_ = true; + mutex_.unlock(); + + return 0; + } + + int wait(long long timeout) { + auto timeout_sec = (timeout < 0) ? timeout : (timeout / 1000); + for (;;) { + mutex_.lock(); + bool is_running = is_running_; + mutex_.unlock(); + + if (!is_running || 0 == timeout_sec--) + break; + + std::this_thread::sleep_for(std::chrono::seconds(1)); + } + return 0; + } + +private: + + void run() { + Harp::ArchDef arch("rv32i", false, MAX_WARPS, MAX_THREADS); + Harp::WordDecoder dec(arch); + Harp::MemoryUnit mu(PAGE_SIZE, arch.getWordSize(), true); + Harp::Core core(arch, dec, mu); + mu.attach(ram_, 0); + + while (core.running()) { + core.step(); + } + core.printStats(); + } + + void thread_proc() { + std::cout << "Device ready..." << std::endl; + + for (;;) { + mutex_.lock(); + bool is_done = is_done_; + bool is_running = is_running_; + mutex_.unlock(); + + if (is_done) + break; + + if (is_running) { + std::cout << "Device running..." << std::endl; + + this->run(); + + mutex_.lock(); + is_running_ = false; + mutex_.unlock(); + + std::cout << "Device ready..." << std::endl; + } + } + + std::cout << "Device shutdown..." << std::endl; + } + + static void __thread_proc__(vx_device* device) { + device->thread_proc(); + } + + bool is_done_; + bool is_running_; + size_t mem_allocation_; + std::thread thread_; + Harp::RAM ram_; + std::mutex mutex_; +}; + +/////////////////////////////////////////////////////////////////////////////// + +extern int vx_dev_open(vx_device_h* hdevice) { + if (NULL == hdevice) + return -1; + + *hdevice = new vx_device(); + + return 0; +} + +extern int vx_dev_close(vx_device_h hdevice) { + if (nullptr == hdevice) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + delete device; + + return 0; +} + +extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr) { + if (NULL == hdevice + || NULL == dev_maddr + || 0 >= size) + return -1; + + vx_device *device = ((vx_device*)hdevice); + return device->alloc_local_mem(size, dev_maddr); +} + +extern int vx_flush_caches(vx_device_h hdevice, size_t /*dev_maddr*/, size_t size) { + if (NULL == hdevice + || 0 >= size) + return -1; + // this functionality is not need by simX + return 0; +} + +extern int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hbuffer) { + if (nullptr == hdevice + || 0 >= size + || NULL == hbuffer) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + auto buffer = new vx_buffer(size, device); + if (nullptr == buffer->data()) { + delete buffer; + return -1; + } + + *hbuffer = buffer; + + return 0; +} + +extern volatile void* vx_host_ptr(vx_buffer_h hbuffer) { + if (nullptr == hbuffer) + return nullptr; + + vx_buffer* buffer = ((vx_buffer*)hbuffer); + + return buffer->data(); +} + +extern int vx_buf_release(vx_buffer_h hbuffer) { + if (nullptr == hbuffer) + return -1; + + vx_buffer* buffer = ((vx_buffer*)hbuffer); + + delete buffer; + + return 0; +} + +extern int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t src_offset) { + if (nullptr == hbuffer + || 0 >= size) + return -1; + + auto buffer = (vx_buffer*)hbuffer; + + if (size + src_offset > buffer->size()) + return -1; + + return buffer->device()->upload(buffer->data(), dev_maddr, size, src_offset); +} + +extern int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t dest_offset) { + if (nullptr == hbuffer + || 0 >= size) + return -1; + + auto buffer = (vx_buffer*)hbuffer; + + if (size + dest_offset > buffer->size()) + return -1; + + return buffer->device()->download(buffer->data(), dev_maddr, size, dest_offset); +} + +extern int vx_start(vx_device_h hdevice) { + if (nullptr == hdevice) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + return device->start(); +} + +extern int vx_ready_wait(vx_device_h hdevice, long long timeout) { + if (nullptr == hdevice) + return -1; + + vx_device *device = ((vx_device*)hdevice); + + return device->wait(timeout); +} diff --git a/driver/sw/vx_utils.cpp b/driver/sw/vx_utils.cpp new file mode 100644 index 00000000..12ebafd3 --- /dev/null +++ b/driver/sw/vx_utils.cpp @@ -0,0 +1,91 @@ +#include +#include +#include +#include + +int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_t size) { + int err = 0; + + if (NULL == content || 0 == size) + return -1; + + static constexpr uint32_t TRANSFER_SIZE = 4096; + + // allocate device buffer + vx_buffer_h buffer; + err = vx_alloc_shared_mem(device, TRANSFER_SIZE, &buffer); + if (err != 0) + return -1; + + // get buffer address + auto buf_ptr = (uint8_t*)vx_host_ptr(buffer); + + #if defined(USE_SIMX) + // default startup routine + ((uint32_t*)buf_ptr)[0] = 0xf1401073; + ((uint32_t*)buf_ptr)[1] = 0xf1401073; + ((uint32_t*)buf_ptr)[2] = 0x30101073; + ((uint32_t*)buf_ptr)[3] = 0x800000b7; + ((uint32_t*)buf_ptr)[4] = 0x000080e7; + err = vx_copy_to_dev(buffer, 0, 5 * 4, 0); + if (err != 0) { + vx_buf_release(buffer); + return err; + } + + // newlib io simulator trap + ((uint32_t*)buf_ptr)[0] = 0x00008067; + err = vx_copy_to_dev(buffer, 0x70000000, 4, 0); + if (err != 0) { + vx_buf_release(buffer); + return err; + } +#endif + + // + // upload content + // + + size_t offset = 0; + while (offset < size) { + auto chunk_size = std::min(TRANSFER_SIZE, size - offset); + std::memcpy(buf_ptr, (uint8_t*)content + offset, chunk_size); + err = vx_copy_to_dev(buffer, VX_KERNEL_BASE_ADDR + offset, chunk_size, 0); + if (err != 0) { + vx_buf_release(buffer); + return err; + } + offset += chunk_size; + } + + vx_buf_release(buffer); + + return 0; +} + +int vx_upload_kernel_file(vx_device_h device, const char* filename) { + std::ifstream ifs(filename); + if (!ifs) { + std::cout << "error: " << filename << " not found" << std::endl; + return -1; + } + + // get length of file: + ifs.seekg(0, ifs.end); + auto size = ifs.tellg(); + ifs.seekg(0, ifs.beg); + + // allocate buffer + auto content = new char [size]; + + // read file content + ifs.read(content, size); + + // upload + int err = vx_upload_kernel_bytes(device, content, size); + + // release buffer + delete[] content; + + return err; +} \ No newline at end of file diff --git a/driver/tests/basic/Makefile b/driver/tests/basic/Makefile new file mode 100644 index 00000000..089739a1 --- /dev/null +++ b/driver/tests/basic/Makefile @@ -0,0 +1,37 @@ + +CXXFLAGS += -std=c++17 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I../../sw/include + +LDFLAGS += + +PROJECT = basic + +SRCS = basic.cpp + +all: $(PROJECT) + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../sw/simx -lvortex -o $@ + +run-fpga: $(PROJECT) + LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-ase: $(PROJECT) + LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + +run-rtlsim: $(PROJECT) + LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) 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parse_args(int argc, char **argv) { + int c; + while ((c = getopt(argc, argv, "?")) != -1) { + switch (c) { + case '?': { + printf("Test.\n"); + printf("Usage: [-h: help]\n"); + exit(0); + } break; + default: + exit(-1); + } + } +} + +uint64_t shuffle(int i, uint64_t value) { + return (value << i) | (value & ((1 << i)-1));; +} + +int run_test(vx_buffer_h sbuf, vx_buffer_h dbuf, uint32_t address, uint64_t value, int num_blocks) { + int err; + int num_failures = 0; + + // write sbuf data + for (int i = 0; i < 8 * num_blocks; ++i) { + ((uint64_t*)vx_host_ptr(sbuf))[i] = shuffle(i, value); + } + + // write buffer to local memory + err = vx_copy_to_dev(sbuf, address, 64 * num_blocks, 0); + if (err != 0) + return -1; + + // read buffer from local memory + err = vx_copy_from_dev(dbuf, address, 64 * num_blocks, 0); + if (err != 0) + return -1; + + // verify result + for (int i = 0; i < 8 * num_blocks; ++i) { + auto curr = ((uint64_t*)vx_host_ptr(dbuf))[i]; + auto ref = shuffle(i, value); + if (curr != ref) { + printf("error @ %x: actual %ld, expected %ld\n", address + 64 * i, curr, ref); + ++num_failures; + } + } + return num_failures; +} + +int main(int argc, char *argv[]) { + int err; + int num_failures = 0; + + // parse command arguments + parse_args(argc, argv); + + // open device connection + vx_device_h device; + err = vx_dev_open(&device); + if (err != 0) + return -1; + + // create source buffer + vx_buffer_h sbuf; + err = vx_alloc_shared_mem(device, 4096, &sbuf); + if (err != 0) { + vx_dev_close(device); + return -1; + } + + // create destination buffer + vx_buffer_h dbuf; + err = vx_alloc_shared_mem(device, 4096, &dbuf); + if (err != 0) { + vx_buf_release(sbuf); + vx_dev_close(device); + return -1; + } + + // run tests + num_failures += run_test(sbuf, dbuf, 0x10000000, 0x0badf00d00ff00ff, 1); + num_failures += run_test(sbuf, dbuf, 0x10000000, 0x0badf00d00ff00ff, 2); + num_failures += run_test(sbuf, dbuf, 0x20000000, 0xff00ff00ff00ff00, 4); + num_failures += run_test(sbuf, dbuf, 0x20000000, 0x0badf00d40ff40ff, 8); + + // releae buffers + vx_buf_release(sbuf); + vx_buf_release(dbuf); + + // close device + vx_dev_close(device); + + if (0 == num_failures) { + printf("Test PASSED\n"); + } else { + printf("Test FAILED\n"); + } + + return num_failures; +} diff --git a/driver/tests/demo/Makefile b/driver/tests/demo/Makefile new file mode 100644 index 00000000..eb603a56 --- /dev/null +++ b/driver/tests/demo/Makefile @@ -0,0 +1,70 @@ +RISCV_TOOL_PATH ?= $(wildcard ~/dev/riscv-gnu-toolchain/drops) +VX_RT_PATH ?= $(wildcard ../../../runtime) + +MAX_WARPS ?= 8 +MAX_THREADS ?= 4 + +VX_CC = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-gcc +VX_CXX = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-g++ +VX_DMP = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-objdump +VX_CPY = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-objcopy + +VX_NEWLIB = $(VX_RT_PATH)/newlib/newlib.c +VX_STR = $(VX_RT_PATH)/startup/vx_start.s +VX_INT = $(VX_RT_PATH)/intrinsics/vx_intrinsics.s +VX_IO = $(VX_RT_PATH)/io/vx_io.s $(VX_RT_PATH)/io/vx_io.c +VX_API = $(VX_RT_PATH)/vx_api/vx_api.c +VX_FIO = $(VX_RT_PATH)/fileio/fileio.s + +VX_CFLAGS = -v -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/mains/vortex_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections + +VX_CFLAGS += -DMAX_WARPS=$(MAX_WARPS) -DMAX_THREADS=$(MAX_THREADS) + +VX_SRCS = kernel.c + +CXXFLAGS += -std=c++17 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I../../sw/include + +PROJECT = demo + +SRCS = demo.cpp + +all: $(PROJECT) + +$(PROJECT).dump: $(PROJECT).elf + $(VX_DMP) -D $(PROJECT).elf > $(PROJECT).dump + +$(PROJECT).hex: $(PROJECT).elf + $(VX_CPY) -O ihex $(PROJECT).elf $(PROJECT).hex + +$(PROJECT).bin: $(PROJECT).elf + $(VX_CPY) -O binary $(PROJECT).elf $(PROJECT).bin + +$(PROJECT).elf: $(SRCS) + $(VX_CC) $(VX_CFLAGS) $(VX_STR) $(VX_FIO) $(VX_NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_SRCS) -I$(VX_RT_PATH) -o $(PROJECT).elf + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../sw/simx -lvortex -o $@ + +run-fpga: $(PROJECT) + LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -f $(PROJECT).bin + +run-ase: $(PROJECT) + LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -f $(PROJECT).bin + +run-rtlsim: $(PROJECT) + LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -f $(PROJECT).bin + +run-simx: $(PROJECT) + LD_LIBRARY_PATH=../../sw/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) -f $(PROJECT).bin + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/driver/tests/demo/demo b/driver/tests/demo/demo new file mode 100755 index 0000000000000000000000000000000000000000..cb6cc5fc7c8861a3a8693cb8168de0ce650ad740 GIT binary patch literal 105576 zcmeFad3;S*`#!w)IhiDK9Abzui5RviB!ZZOgaipO#&|>$NysEQA+)BN8ZlQ@Rg0Qh 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00000000..8902e352 --- /dev/null +++ b/driver/tests/demo/demo.cpp @@ -0,0 +1,75 @@ +#include +#include +#include + +const char* program_file = nullptr; + +static void show_usage() { + std::cout << "Vortex Driver Test." << std::endl; + std::cout << "Usage: -f: program [-h: help]" << std::endl; +} + +static void parse_args(int argc, char **argv) { + int c; + while ((c = getopt(argc, argv, "f:h?")) != -1) { + switch (c) { + case 'f': { + program_file = optarg; + } break; + case 'h': + case '?': { + show_usage(); + exit(0); + } break; + default: + show_usage(); + exit(-1); + } + } + + if (nullptr == program_file) { + show_usage(); + exit(-1); + } +} + +int main(int argc, char *argv[]) { + int err; + + // parse command arguments + parse_args(argc, argv); + + // open device connection + vx_device_h device; + err = vx_dev_open(&device); + if (err != 0) + return -1; + + // upload program + err = vx_upload_kernel_file(device, program_file); + if (err != 0) { + vx_dev_close(device); + return -1; + } + + // start device + err = vx_start(device); + if (err != 0) { + vx_dev_close(device); + return -1; + } + + // wait for completion + err = vx_ready_wait(device, -1); + if (err != 0) { + vx_dev_close(device); + return -1; + } + + // close device + vx_dev_close(device); + + printf("done!\n"); + + return 0; +} \ No newline at end of file diff --git a/driver/tests/demo/demo.elf b/driver/tests/demo/demo.elf new file mode 100755 index 0000000000000000000000000000000000000000..4e27beab86c610cf5d38d9dc7e813858485c55e8 GIT binary patch literal 36456 zcmeHw34B!5z5ls$?<~oLBrpjR5Fs#O5lI3hA=GLOvbR(b1?f{eOeO=Fl1$=ELcpa2 zBZRu!XhCDFjfgukJ zd0@x`Lmn9Nzz64n8}Ok$yZP~8$lD;+7JpB?A|A;Pd5gtbe3}n!eso7@i}qNJ@6LuS z_+Am$hQg&nguIXUyduQLSH#Z(uZV8ZCb~C156-zIwQ^b38mU-XneDs;$!Hoa!^HnH9RtcaBF6VR!x>4trN zA>v#8qP|pgqwXzjqM?iBA+PYz&KrhT@9z&SDihhABSonG2C;qhb0V}bENZ%*6>-BKsM+&?2zAwq z_*lO$w0>uQwik8u21HHZ0om?s??UKUC?ZwQzPcUtdl`us17o+*!tkn}@wFti1JxbJZx{m^@`KeS+^%MZVF{NSS>yqfewu|E*n|3rVt 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zyICxjgKxZr;7%SM8JreOd>!~22$+XOyA-$ulXM^WUczY|7LDsQ3nuL=i-q{ET82wj zi}sa4d`r&|;?H>FhjmzdcbR-vdrxY_pU6 +#include +#include "intrinsics/vx_intrinsics.h" + +void main() { + unsigned *x = (unsigned*)0x10000000; + unsigned *y = (unsigned*)0x20000000; + unsigned *z = (unsigned*)0x30000000; + + unsigned wid = vx_warpID(); + + unsigned tid = vx_threadID(); + + unsigned i = (wid * MAX_THREADS) + tid; + + //if (i == 0) { + // printf("begin\n"); + //} + + z[i] = x[i] + y[i]; + + //if (i == 0) { + // printf("end\n"); + //} +} \ No newline at end of file diff --git a/driver/tests/demo/run.log b/driver/tests/demo/run.log new file mode 100644 index 00000000..2e3de7ad --- /dev/null +++ b/driver/tests/demo/run.log @@ -0,0 +1,372144 @@ +LD_LIBRARY_PATH=../../sim/obj_dir:/home/blaise/dev/cash/build/lib:/opt/systemc/lib:/home/blaise/dev/cash/build/lib:/opt/systemc/lib: ./demo_sim -f demo.bin +Device ready... +VXDRV: upload 20 bytes to 0x0 +mem-write: 0x0 <- 0xf1401073 +mem-write: 0x4 <- 0xf1401073 +mem-write: 0x8 <- 0x30101073 +mem-write: 0xc <- 0x800000b7 +mem-write: 0x10 <- 0x80e7 +VXDRV: upload 4 bytes to 0x70000000 +mem-write: 0x70000000 <- 0x8067 +VXDRV: upload 1024 bytes to 0x80000000 +mem-write: 0x80000000 <- 0x597 +mem-write: 0x80000004 <- 0xd458593 +mem-write: 0x80000008 <- 0x2000513 +mem-write: 0x8000000c <- 0xb5106b +mem-write: 0x80000010 <- 0xc4000ef +mem-write: 0x80000014 <- 0x100513 +mem-write: 0x80000018 <- 0x5006b +mem-write: 0x8000001c <- 0x1e418513 +mem-write: 0x80000020 <- 0x24c18613 +mem-write: 0x80000024 <- 0x40a60633 +mem-write: 0x80000028 <- 0x593 +mem-write: 0x8000002c <- 0x5ed000ef +mem-write: 0x80000030 <- 0x1517 +mem-write: 0x80000034 <- 0xcf050513 +mem-write: 0x80000038 <- 0x4a5000ef +mem-write: 0x8000003c <- 0x541000ef +mem-write: 0x80000040 <- 0x8000ef +mem-write: 0x80000044 <- 0x4ad0006f +mem-write: 0x80000048 <- 0xfd010113 +mem-write: 0x8000004c <- 0x100513 +mem-write: 0x80000050 <- 0x2112623 +mem-write: 0x80000054 <- 0x72c000ef +mem-write: 0x80000058 <- 0x80015537 +mem-write: 0x8000005c <- 0xa0450513 +mem-write: 0x80000060 <- 0x6d5000ef +mem-write: 0x80000064 <- 0x1d41a883 +mem-write: 0x80000068 <- 0x1d01a803 +mem-write: 0x8000006c <- 0x1cc1a703 +mem-write: 0x80000070 <- 0x80001637 +mem-write: 0x80000074 <- 0x40000793 +mem-write: 0x80000078 <- 0xc10693 +mem-write: 0x8000007c <- 0xc2c60613 +mem-write: 0x80000080 <- 0x400593 +mem-write: 0x80000084 <- 0x400513 +mem-write: 0x80000088 <- 0x1112623 +mem-write: 0x8000008c <- 0x1012823 +mem-write: 0x80000090 <- 0xe12a23 +mem-write: 0x80000094 <- 0xf12c23 +mem-write: 0x80000098 <- 0xf12e23 +mem-write: 0x8000009c <- 0x245000ef +mem-write: 0x800000a0 <- 0x80015537 +mem-write: 0x800000a4 <- 0xa1c50513 +mem-write: 0x800000a8 <- 0x68d000ef +mem-write: 0x800000ac <- 0x2c12083 +mem-write: 0x800000b0 <- 0x513 +mem-write: 0x800000b4 <- 0x3010113 +mem-write: 0x800000b8 <- 0x8067 +mem-write: 0x800000bc <- 0x793 +mem-write: 0x800000c0 <- 0x78863 +mem-write: 0x800000c4 <- 0x80001537 +mem-write: 0x800000c8 <- 0xd2050513 +mem-write: 0x800000cc <- 0x4110006f +mem-write: 0x800000d0 <- 0x8067 +mem-write: 0x800000d4 <- 0x2000513 +mem-write: 0x800000d8 <- 0x5006b +mem-write: 0x800000dc <- 0x16197 +mem-write: 0x800000e0 <- 0x72c18193 +mem-write: 0x800000e4 <- 0x21026f3 +mem-write: 0x800000e8 <- 0x1a69693 +mem-write: 0x800000ec <- 0x2002673 +mem-write: 0x800000f0 <- 0xa61593 +mem-write: 0x800000f4 <- 0x261613 +mem-write: 0x800000f8 <- 0x6ffff137 +mem-write: 0x800000fc <- 0x40b10133 +mem-write: 0x80000100 <- 0x40d10133 +mem-write: 0x80000104 <- 0xc10133 +mem-write: 0x80000108 <- 0x21026f3 +mem-write: 0x8000010c <- 0x68663 +mem-write: 0x80000110 <- 0x513 +mem-write: 0x80000114 <- 0x5006b +mem-write: 0x80000118 <- 0x8067 +mem-write: 0x8000011c <- 0x52783 +mem-write: 0x80000120 <- 0x865813 +mem-write: 0x80000124 <- 0x1065693 +mem-write: 0x80000128 <- 0x1865713 +mem-write: 0x8000012c <- 0xc78023 +mem-write: 0x80000130 <- 0x10780a3 +mem-write: 0x80000134 <- 0xd78123 +mem-write: 0x80000138 <- 0xe781a3 +mem-write: 0x8000013c <- 0x478893 +mem-write: 0x80000140 <- 0xac05263 +mem-write: 0x80000144 <- 0x878813 +mem-write: 0x80000148 <- 0x105b833 +mem-write: 0x8000014c <- 0xb7b6b3 +mem-write: 0x80000150 <- 0xfff60713 +mem-write: 0x80000154 <- 0x184813 +mem-write: 0x80000158 <- 0x16c693 +mem-write: 0x8000015c <- 0x973713 +mem-write: 0x80000160 <- 0xd866b3 +mem-write: 0x80000164 <- 0x174713 +mem-write: 0x80000168 <- 0xd77733 +mem-write: 0x8000016c <- 0x8070463 +mem-write: 0x80000170 <- 0xb8e733 +mem-write: 0x80000174 <- 0x377713 +mem-write: 0x80000178 <- 0x6071e63 +mem-write: 0x8000017c <- 0xffc67813 +mem-write: 0x80000180 <- 0x58793 +mem-write: 0x80000184 <- 0x88713 +mem-write: 0x80000188 <- 0xb80833 +mem-write: 0x8000018c <- 0x7a683 +mem-write: 0x80000190 <- 0x478793 +mem-write: 0x80000194 <- 0x470713 +mem-write: 0x80000198 <- 0xfed72e23 +mem-write: 0x8000019c <- 0xff0798e3 +mem-write: 0x800001a0 <- 0xffc67793 +mem-write: 0x800001a4 <- 0xf886b3 +mem-write: 0x800001a8 <- 0x2f60c63 +mem-write: 0x800001ac <- 0xf58733 +mem-write: 0x800001b0 <- 0x74803 +mem-write: 0x800001b4 <- 0x178713 +mem-write: 0x800001b8 <- 0x1068023 +mem-write: 0x800001bc <- 0x2c75263 +mem-write: 0x800001c0 <- 0xe58733 +mem-write: 0x800001c4 <- 0x74703 +mem-write: 0x800001c8 <- 0x278793 +mem-write: 0x800001cc <- 0xe680a3 +mem-write: 0x800001d0 <- 0xc7d863 +mem-write: 0x800001d4 <- 0xf587b3 +mem-write: 0x800001d8 <- 0x7c783 +mem-write: 0x800001dc <- 0xf68123 +mem-write: 0x800001e0 <- 0xc888b3 +mem-write: 0x800001e4 <- 0x38f793 +mem-write: 0x800001e8 <- 0x11788b3 +mem-write: 0x800001ec <- 0x1152023 +mem-write: 0x800001f0 <- 0x8067 +mem-write: 0x800001f4 <- 0x460713 +mem-write: 0x800001f8 <- 0xe787b3 +mem-write: 0x800001fc <- 0x88713 +mem-write: 0x80000200 <- 0x5c683 +mem-write: 0x80000204 <- 0x170713 +mem-write: 0x80000208 <- 0x158593 +mem-write: 0x8000020c <- 0xfed70fa3 +mem-write: 0x80000210 <- 0xfef718e3 +mem-write: 0x80000214 <- 0xfcdff06f +mem-write: 0x80000218 <- 0x52783 +mem-write: 0x8000021c <- 0xff010113 +mem-write: 0x80000220 <- 0x7c803 +mem-write: 0x80000224 <- 0x17c603 +mem-write: 0x80000228 <- 0x27c683 +mem-write: 0x8000022c <- 0x37c703 +mem-write: 0x80000230 <- 0x1010623 +mem-write: 0x80000234 <- 0xc106a3 +mem-write: 0x80000238 <- 0xd10723 +mem-write: 0x8000023c <- 0xe107a3 +mem-write: 0x80000240 <- 0xc12883 +mem-write: 0x80000244 <- 0x478813 +mem-write: 0x80000248 <- 0xb105263 +mem-write: 0x8000024c <- 0x878613 +mem-write: 0x80000250 <- 0xc5b633 +mem-write: 0x80000254 <- 0xb7b6b3 +mem-write: 0x80000258 <- 0xfff88713 +mem-write: 0x8000025c <- 0x164613 +mem-write: 0x80000260 <- 0x16c693 +mem-write: 0x80000264 <- 0x973713 +mem-write: 0x80000268 <- 0xd666b3 +mem-write: 0x8000026c <- 0x174713 +mem-write: 0x80000270 <- 0xd77733 +mem-write: 0x80000274 <- 0x8070663 +mem-write: 0x80000278 <- 0x105e733 +mem-write: 0x8000027c <- 0x377713 +mem-write: 0x80000280 <- 0x8071063 +mem-write: 0x80000284 <- 0xffc8f613 +mem-write: 0x80000288 <- 0x80713 +mem-write: 0x8000028c <- 0x58793 +mem-write: 0x80000290 <- 0xb60633 +mem-write: 0x80000294 <- 0x72683 +mem-write: 0x80000298 <- 0x478793 +mem-write: 0x8000029c <- 0x470713 +mem-write: 0x800002a0 <- 0xfed7ae23 +mem-write: 0x800002a4 <- 0xfec798e3 +mem-write: 0x800002a8 <- 0xffc8f793 +mem-write: 0x800002ac <- 0xf806b3 +mem-write: 0x800002b0 <- 0x2f88c63 +mem-write: 0x800002b4 <- 0x6c303 +mem-write: 0x800002b8 <- 0xf58633 +mem-write: 0x800002bc <- 0x178713 +mem-write: 0x800002c0 <- 0x660023 +mem-write: 0x800002c4 <- 0x3175263 +mem-write: 0x800002c8 <- 0x16c603 +mem-write: 0x800002cc <- 0xe58733 +mem-write: 0x800002d0 <- 0x278793 +mem-write: 0x800002d4 <- 0xc70023 +mem-write: 0x800002d8 <- 0x117d863 +mem-write: 0x800002dc <- 0x26c703 +mem-write: 0x800002e0 <- 0xf587b3 +mem-write: 0x800002e4 <- 0xe78023 +mem-write: 0x800002e8 <- 0x1180833 +mem-write: 0x800002ec <- 0x387793 +mem-write: 0x800002f0 <- 0x1078833 +mem-write: 0x800002f4 <- 0x1052023 +mem-write: 0x800002f8 <- 0x1010113 +mem-write: 0x800002fc <- 0x8067 +mem-write: 0x80000300 <- 0x488713 +mem-write: 0x80000304 <- 0xe787b3 +mem-write: 0x80000308 <- 0x80713 +mem-write: 0x8000030c <- 0x74683 +mem-write: 0x80000310 <- 0x170713 +mem-write: 0x80000314 <- 0x158593 +mem-write: 0x80000318 <- 0xfed58fa3 +mem-write: 0x8000031c <- 0xfef718e3 +mem-write: 0x80000320 <- 0xfc9ff06f +mem-write: 0x80000324 <- 0x8067 +mem-write: 0x80000328 <- 0x27b7 +mem-write: 0x8000032c <- 0xf5a223 +mem-write: 0x80000330 <- 0x513 +mem-write: 0x80000334 <- 0x8067 +mem-write: 0x80000338 <- 0x100513 +mem-write: 0x8000033c <- 0x8067 +mem-write: 0x80000340 <- 0xfe010113 +mem-write: 0x80000344 <- 0x112e23 +mem-write: 0x80000348 <- 0x710007b7 +mem-write: 0x8000034c <- 0x400713 +mem-write: 0x80000350 <- 0x865893 +mem-write: 0x80000354 <- 0x1065813 +mem-write: 0x80000358 <- 0x1865693 +mem-write: 0x8000035c <- 0x85de93 +mem-write: 0x80000360 <- 0x105de13 +mem-write: 0x80000364 <- 0x185d313 +mem-write: 0x80000368 <- 0x300f13 +mem-write: 0x8000036c <- 0xe7a023 +mem-write: 0x80000370 <- 0xe78823 +mem-write: 0x80000374 <- 0xe7a423 +mem-write: 0x80000378 <- 0xe78c23 +mem-write: 0x8000037c <- 0x1e78223 +mem-write: 0x80000380 <- 0x782a3 +mem-write: 0x80000384 <- 0x79323 +mem-write: 0x80000388 <- 0xa7a623 +mem-write: 0x8000038c <- 0x788a3 +mem-write: 0x80000390 <- 0x78923 +mem-write: 0x80000394 <- 0x789a3 +mem-write: 0x80000398 <- 0x78ca3 +mem-write: 0x8000039c <- 0x78d23 +mem-write: 0x800003a0 <- 0x78da3 +mem-write: 0x800003a4 <- 0xc78e23 +mem-write: 0x800003a8 <- 0xb78a23 +mem-write: 0x800003ac <- 0x1d78aa3 +mem-write: 0x800003b0 <- 0x1c78b23 +mem-write: 0x800003b4 <- 0x678ba3 +mem-write: 0x800003b8 <- 0x1178ea3 +mem-write: 0x800003bc <- 0x1078f23 +mem-write: 0x800003c0 <- 0xd78fa3 +mem-write: 0x800003c4 <- 0x1c81a783 +mem-write: 0x800003c8 <- 0x780e7 +mem-write: 0x800003cc <- 0x720007b7 +mem-write: 0x800003d0 <- 0x7c703 +mem-write: 0x800003d4 <- 0xe10623 +mem-write: 0x800003d8 <- 0x17c703 +mem-write: 0x800003dc <- 0xe106a3 +mem-write: 0x800003e0 <- 0x27c703 +mem-write: 0x800003e4 <- 0xe10723 +mem-write: 0x800003e8 <- 0x37c703 +mem-write: 0x800003ec <- 0xe107a3 +mem-write: 0x800003f0 <- 0xc12603 +mem-write: 0x800003f4 <- 0x2c05863 +mem-write: 0x800003f8 <- 0x478793 +mem-write: 0x800003fc <- 0x8e0005b7 +VXDRV: upload 1024 bytes to 0x80000400 +mem-write: 0x80000400 <- 0xf60633 +mem-write: 0x80000404 <- 0xffc58593 +mem-write: 0x80000408 <- 0x7c683 +mem-write: 0x8000040c <- 0xb78733 +mem-write: 0x80000410 <- 0x810513 +mem-write: 0x80000414 <- 0xe50733 +mem-write: 0x80000418 <- 0xd70023 +mem-write: 0x8000041c <- 0x178793 +mem-write: 0x80000420 <- 0xfec794e3 +mem-write: 0x80000424 <- 0x1c12083 +mem-write: 0x80000428 <- 0x812503 +mem-write: 0x8000042c <- 0x2010113 +mem-write: 0x80000430 <- 0x8067 +mem-write: 0x80000434 <- 0xff010113 +mem-write: 0x80000438 <- 0x812423 +mem-write: 0x8000043c <- 0x60413 +mem-write: 0x80000440 <- 0x112623 +mem-write: 0x80000444 <- 0x710007b7 +mem-write: 0x80000448 <- 0x400713 +mem-write: 0x8000044c <- 0x865813 +mem-write: 0x80000450 <- 0x1845693 +mem-write: 0x80000454 <- 0x85de13 +mem-write: 0x80000458 <- 0x105d313 +mem-write: 0x8000045c <- 0x185d893 +mem-write: 0x80000460 <- 0x1065613 +mem-write: 0x80000464 <- 0xa7a623 +mem-write: 0x80000468 <- 0xe7a023 +mem-write: 0x8000046c <- 0xe78223 +mem-write: 0x80000470 <- 0x782a3 +mem-write: 0x80000474 <- 0xe78823 +mem-write: 0x80000478 <- 0x79323 +mem-write: 0x8000047c <- 0xe7a423 +mem-write: 0x80000480 <- 0x788a3 +mem-write: 0x80000484 <- 0x78923 +mem-write: 0x80000488 <- 0x789a3 +mem-write: 0x8000048c <- 0xe78c23 +mem-write: 0x80000490 <- 0x78ca3 +mem-write: 0x80000494 <- 0x78d23 +mem-write: 0x80000498 <- 0x78da3 +mem-write: 0x8000049c <- 0x878e23 +mem-write: 0x800004a0 <- 0xb78a23 +mem-write: 0x800004a4 <- 0x1c78aa3 +mem-write: 0x800004a8 <- 0x678b23 +mem-write: 0x800004ac <- 0x1178ba3 +mem-write: 0x800004b0 <- 0x1078ea3 +mem-write: 0x800004b4 <- 0xc78f23 +mem-write: 0x800004b8 <- 0xd78fa3 +mem-write: 0x800004bc <- 0x1c81a783 +mem-write: 0x800004c0 <- 0x780e7 +mem-write: 0x800004c4 <- 0xc12083 +mem-write: 0x800004c8 <- 0x40513 +mem-write: 0x800004cc <- 0x812403 +mem-write: 0x800004d0 <- 0x1010113 +mem-write: 0x800004d4 <- 0x8067 +mem-write: 0x800004d8 <- 0xff010113 +mem-write: 0x800004dc <- 0x812423 +mem-write: 0x800004e0 <- 0x710007b7 +mem-write: 0x800004e4 <- 0x112623 +mem-write: 0x800004e8 <- 0x60413 +mem-write: 0x800004ec <- 0x400713 +mem-write: 0x800004f0 <- 0x500313 +mem-write: 0x800004f4 <- 0x1078813 +mem-write: 0x800004f8 <- 0xe7a023 +mem-write: 0x800004fc <- 0x678223 +mem-write: 0x80000500 <- 0x782a3 +mem-write: 0x80000504 <- 0x878823 +mem-write: 0x80000508 <- 0x865893 +mem-write: 0x8000050c <- 0x1845693 +mem-write: 0x80000510 <- 0x1065613 +mem-write: 0x80000514 <- 0x11800a3 +mem-write: 0x80000518 <- 0xc80123 +mem-write: 0x8000051c <- 0xd801a3 +mem-write: 0x80000520 <- 0x79323 +mem-write: 0x80000524 <- 0xe7a423 +mem-write: 0x80000528 <- 0xa7a623 +mem-write: 0x8000052c <- 0xa805263 +mem-write: 0x80000530 <- 0x1478693 +mem-write: 0x80000534 <- 0x1878793 +mem-write: 0x80000538 <- 0xf5b7b3 +mem-write: 0x8000053c <- 0xb83533 +mem-write: 0x80000540 <- 0xfff40613 +mem-write: 0x80000544 <- 0x17c713 +mem-write: 0x80000548 <- 0x963613 +mem-write: 0x8000054c <- 0x154793 +mem-write: 0x80000550 <- 0xf767b3 +mem-write: 0x80000554 <- 0x164713 +mem-write: 0x80000558 <- 0xf777b3 +mem-write: 0x8000055c <- 0x8078863 +mem-write: 0x80000560 <- 0xb6e7b3 +mem-write: 0x80000564 <- 0x37f793 +mem-write: 0x80000568 <- 0x8079263 +mem-write: 0x8000056c <- 0xffc47513 +mem-write: 0x80000570 <- 0xb50533 +mem-write: 0x80000574 <- 0x58793 +mem-write: 0x80000578 <- 0x40b68833 +mem-write: 0x8000057c <- 0x7a603 +mem-write: 0x80000580 <- 0xf80733 +mem-write: 0x80000584 <- 0x478793 +mem-write: 0x80000588 <- 0xc72023 +mem-write: 0x8000058c <- 0xfef518e3 +mem-write: 0x80000590 <- 0xffc47793 +mem-write: 0x80000594 <- 0xf686b3 +mem-write: 0x80000598 <- 0x2f40c63 +mem-write: 0x8000059c <- 0xf58733 +mem-write: 0x800005a0 <- 0x74603 +mem-write: 0x800005a4 <- 0x178713 +mem-write: 0x800005a8 <- 0xc68023 +mem-write: 0x800005ac <- 0x2875263 +mem-write: 0x800005b0 <- 0xe58733 +mem-write: 0x800005b4 <- 0x74703 +mem-write: 0x800005b8 <- 0x278793 +mem-write: 0x800005bc <- 0xe680a3 +mem-write: 0x800005c0 <- 0x87d863 +mem-write: 0x800005c4 <- 0xf587b3 +mem-write: 0x800005c8 <- 0x7c783 +mem-write: 0x800005cc <- 0xf68123 +mem-write: 0x800005d0 <- 0x1c81a783 +mem-write: 0x800005d4 <- 0x780e7 +mem-write: 0x800005d8 <- 0xc12083 +mem-write: 0x800005dc <- 0x40513 +mem-write: 0x800005e0 <- 0x812403 +mem-write: 0x800005e4 <- 0x1010113 +mem-write: 0x800005e8 <- 0x8067 +mem-write: 0x800005ec <- 0x480713 +mem-write: 0x800005f0 <- 0x870733 +mem-write: 0x800005f4 <- 0x410687b3 +mem-write: 0x800005f8 <- 0xf587b3 +mem-write: 0x800005fc <- 0xffc7c783 +mem-write: 0x80000600 <- 0x168693 +mem-write: 0x80000604 <- 0xfef68fa3 +mem-write: 0x80000608 <- 0xfed716e3 +mem-write: 0x8000060c <- 0xfc5ff06f +mem-write: 0x80000610 <- 0x50793 +mem-write: 0x80000614 <- 0x1c41a503 +mem-write: 0x80000618 <- 0x41f7d693 +mem-write: 0x8000061c <- 0xf6c7b3 +mem-write: 0x80000620 <- 0x40d787b3 +mem-write: 0x80000624 <- 0xa787b3 +mem-write: 0x80000628 <- 0x1cf1a223 +mem-write: 0x8000062c <- 0x8067 +mem-write: 0x80000630 <- 0x513 +mem-write: 0x80000634 <- 0x14c0006f +mem-write: 0x80000638 <- 0xfe010113 +mem-write: 0x8000063c <- 0x112e23 +mem-write: 0x80000640 <- 0x710007b7 +mem-write: 0x80000644 <- 0x400713 +mem-write: 0x80000648 <- 0x865893 +mem-write: 0x8000064c <- 0x1065813 +mem-write: 0x80000650 <- 0x1865693 +mem-write: 0x80000654 <- 0x855293 +mem-write: 0x80000658 <- 0x1055f93 +mem-write: 0x8000065c <- 0x1855f13 +mem-write: 0x80000660 <- 0x85de93 +mem-write: 0x80000664 <- 0x105de13 +mem-write: 0x80000668 <- 0x185d313 +mem-write: 0x8000066c <- 0x700393 +mem-write: 0x80000670 <- 0xe7a023 +mem-write: 0x80000674 <- 0xe78823 +mem-write: 0x80000678 <- 0xe7a423 +mem-write: 0x8000067c <- 0xe78c23 +mem-write: 0x80000680 <- 0x778223 +mem-write: 0x80000684 <- 0x782a3 +mem-write: 0x80000688 <- 0x79323 +mem-write: 0x8000068c <- 0xa78623 +mem-write: 0x80000690 <- 0x5786a3 +mem-write: 0x80000694 <- 0x1f78723 +mem-write: 0x80000698 <- 0x1e787a3 +mem-write: 0x8000069c <- 0x788a3 +mem-write: 0x800006a0 <- 0x78923 +mem-write: 0x800006a4 <- 0x789a3 +mem-write: 0x800006a8 <- 0x78ca3 +mem-write: 0x800006ac <- 0x78d23 +mem-write: 0x800006b0 <- 0x78da3 +mem-write: 0x800006b4 <- 0xc78e23 +mem-write: 0x800006b8 <- 0xb78a23 +mem-write: 0x800006bc <- 0x1d78aa3 +mem-write: 0x800006c0 <- 0x1c78b23 +mem-write: 0x800006c4 <- 0x678ba3 +mem-write: 0x800006c8 <- 0x1178ea3 +mem-write: 0x800006cc <- 0x1078f23 +mem-write: 0x800006d0 <- 0xd78fa3 +mem-write: 0x800006d4 <- 0x1c81a783 +mem-write: 0x800006d8 <- 0x780e7 +mem-write: 0x800006dc <- 0x720007b7 +mem-write: 0x800006e0 <- 0x7c703 +mem-write: 0x800006e4 <- 0xe10623 +mem-write: 0x800006e8 <- 0x17c703 +mem-write: 0x800006ec <- 0xe106a3 +mem-write: 0x800006f0 <- 0x27c703 +mem-write: 0x800006f4 <- 0xe10723 +mem-write: 0x800006f8 <- 0x37c703 +mem-write: 0x800006fc <- 0xe107a3 +mem-write: 0x80000700 <- 0xc12603 +mem-write: 0x80000704 <- 0x2c05863 +mem-write: 0x80000708 <- 0x478793 +mem-write: 0x8000070c <- 0x8e0005b7 +mem-write: 0x80000710 <- 0xf60633 +mem-write: 0x80000714 <- 0xffc58593 +mem-write: 0x80000718 <- 0x7c683 +mem-write: 0x8000071c <- 0xb78733 +mem-write: 0x80000720 <- 0x810513 +mem-write: 0x80000724 <- 0xe50733 +mem-write: 0x80000728 <- 0xd70023 +mem-write: 0x8000072c <- 0x178793 +mem-write: 0x80000730 <- 0xfec794e3 +mem-write: 0x80000734 <- 0x1c12083 +mem-write: 0x80000738 <- 0x812503 +mem-write: 0x8000073c <- 0x2010113 +mem-write: 0x80000740 <- 0x8067 +mem-write: 0x80000744 <- 0x513 +mem-write: 0x80000748 <- 0x380006f +mem-write: 0x8000074c <- 0x5c0006f +mem-write: 0x80000750 <- 0x80015537 +mem-write: 0x80000754 <- 0x93850513 +mem-write: 0x80000758 <- 0xa80006f +mem-write: 0x8000075c <- 0x1e41a503 +mem-write: 0x80000760 <- 0x150713 +mem-write: 0x80000764 <- 0x1ee1a223 +mem-write: 0x80000768 <- 0x8067 +mem-write: 0x8000076c <- 0x80015537 +mem-write: 0x80000770 <- 0x95c50513 +mem-write: 0x80000774 <- 0x8c0006f +mem-write: 0x80000778 <- 0xb5106b +mem-write: 0x8000077c <- 0x8067 +mem-write: 0x80000780 <- 0x5006b +mem-write: 0x80000784 <- 0x8067 +mem-write: 0x80000788 <- 0xb5406b +mem-write: 0x8000078c <- 0x8067 +mem-write: 0x80000790 <- 0x5206b +mem-write: 0x80000794 <- 0x8067 +mem-write: 0x80000798 <- 0x306b +mem-write: 0x8000079c <- 0x8067 +mem-write: 0x800007a0 <- 0x2102573 +mem-write: 0x800007a4 <- 0x8067 +mem-write: 0x800007a8 <- 0x2002573 +mem-write: 0x800007ac <- 0x8067 +mem-write: 0x800007b0 <- 0x2602573 +mem-write: 0x800007b4 <- 0x8067 +mem-write: 0x800007b8 <- 0x2502573 +mem-write: 0x800007bc <- 0x8067 +mem-write: 0x800007c0 <- 0x400513 +mem-write: 0x800007c4 <- 0x5006b +mem-write: 0x800007c8 <- 0x21026f3 +mem-write: 0x800007cc <- 0xf69693 +mem-write: 0x800007d0 <- 0x2002673 +mem-write: 0x800007d4 <- 0xa61593 +mem-write: 0x800007d8 <- 0x261613 +mem-write: 0x800007dc <- 0x6ffff137 +mem-write: 0x800007e0 <- 0x40b10133 +mem-write: 0x800007e4 <- 0x40d10133 +mem-write: 0x800007e8 <- 0xc10133 +mem-write: 0x800007ec <- 0x21026f3 +mem-write: 0x800007f0 <- 0x68663 +mem-write: 0x800007f4 <- 0x513 +mem-write: 0x800007f8 <- 0x5006b +mem-write: 0x800007fc <- 0x8067 +VXDRV: upload 1024 bytes to 0x80000800 +mem-write: 0x80000800 <- 0xff410113 +mem-write: 0x80000804 <- 0x112023 +mem-write: 0x80000808 <- 0xb12223 +mem-write: 0x8000080c <- 0x54583 +mem-write: 0x80000810 <- 0x58863 +mem-write: 0x80000814 <- 0x1c000ef +mem-write: 0x80000818 <- 0x150513 +mem-write: 0x8000081c <- 0xff1ff06f +mem-write: 0x80000820 <- 0x12083 +mem-write: 0x80000824 <- 0x412583 +mem-write: 0x80000828 <- 0xc10113 +mem-write: 0x8000082c <- 0x8067 +mem-write: 0x80000830 <- 0x15297 +mem-write: 0x80000834 <- 0x7dc28293 +mem-write: 0x80000838 <- 0xb2a023 +mem-write: 0x8000083c <- 0x8067 +mem-write: 0x80000840 <- 0xff010113 +mem-write: 0x80000844 <- 0x912223 +mem-write: 0x80000848 <- 0x112623 +mem-write: 0x8000084c <- 0x812423 +mem-write: 0x80000850 <- 0x1212023 +mem-write: 0x80000854 <- 0xf00793 +mem-write: 0x80000858 <- 0x50493 +mem-write: 0x8000085c <- 0x4a7fc63 +mem-write: 0x80000860 <- 0x80015937 +mem-write: 0x80000864 <- 0x693 +mem-write: 0x80000868 <- 0x2000413 +mem-write: 0x8000086c <- 0x9c090913 +mem-write: 0x80000870 <- 0xffc40413 +mem-write: 0x80000874 <- 0x84d7b3 +mem-write: 0x80000878 <- 0xf7f793 +mem-write: 0x8000087c <- 0x279713 +mem-write: 0x80000880 <- 0xe90733 +mem-write: 0x80000884 <- 0x79463 +mem-write: 0x80000888 <- 0x68863 +mem-write: 0x8000088c <- 0x72503 +mem-write: 0x80000890 <- 0xf71ff0ef +mem-write: 0x80000894 <- 0x100693 +mem-write: 0x80000898 <- 0xfc041ce3 +mem-write: 0x8000089c <- 0xc12083 +mem-write: 0x800008a0 <- 0x812403 +mem-write: 0x800008a4 <- 0x412483 +mem-write: 0x800008a8 <- 0x12903 +mem-write: 0x800008ac <- 0x1010113 +mem-write: 0x800008b0 <- 0x8067 +mem-write: 0x800008b4 <- 0x800157b7 +mem-write: 0x800008b8 <- 0x251493 +mem-write: 0x800008bc <- 0x9c078793 +mem-write: 0x800008c0 <- 0x812403 +mem-write: 0x800008c4 <- 0x9784b3 +mem-write: 0x800008c8 <- 0x4a503 +mem-write: 0x800008cc <- 0xc12083 +mem-write: 0x800008d0 <- 0x412483 +mem-write: 0x800008d4 <- 0x12903 +mem-write: 0x800008d8 <- 0x1010113 +mem-write: 0x800008dc <- 0xf25ff06f +mem-write: 0x800008e0 <- 0xff010113 +mem-write: 0x800008e4 <- 0x812423 +mem-write: 0x800008e8 <- 0x112623 +mem-write: 0x800008ec <- 0x912223 +mem-write: 0x800008f0 <- 0x1212023 +mem-write: 0x800008f4 <- 0x58413 +mem-write: 0x800008f8 <- 0xf09ff0ef +mem-write: 0x800008fc <- 0xf00793 +mem-write: 0x80000900 <- 0x687f063 +mem-write: 0x80000904 <- 0x80015937 +mem-write: 0x80000908 <- 0x693 +mem-write: 0x8000090c <- 0x2000493 +mem-write: 0x80000910 <- 0x9c090913 +mem-write: 0x80000914 <- 0xffc48493 +mem-write: 0x80000918 <- 0x9457b3 +mem-write: 0x8000091c <- 0xf7f793 +mem-write: 0x80000920 <- 0x279713 +mem-write: 0x80000924 <- 0xe90733 +mem-write: 0x80000928 <- 0x79463 +mem-write: 0x8000092c <- 0x68863 +mem-write: 0x80000930 <- 0x72503 +mem-write: 0x80000934 <- 0xecdff0ef +mem-write: 0x80000938 <- 0x100693 +mem-write: 0x8000093c <- 0xfc049ce3 +mem-write: 0x80000940 <- 0x812403 +mem-write: 0x80000944 <- 0xc12083 +mem-write: 0x80000948 <- 0x412483 +mem-write: 0x8000094c <- 0x12903 +mem-write: 0x80000950 <- 0x80015537 +mem-write: 0x80000954 <- 0xa2850513 +mem-write: 0x80000958 <- 0x1010113 +mem-write: 0x8000095c <- 0xea5ff06f +mem-write: 0x80000960 <- 0x800157b7 +mem-write: 0x80000964 <- 0x9c078793 +mem-write: 0x80000968 <- 0x241413 +mem-write: 0x8000096c <- 0x878433 +mem-write: 0x80000970 <- 0x42503 +mem-write: 0x80000974 <- 0xe8dff0ef +mem-write: 0x80000978 <- 0xfc9ff06f +mem-write: 0x8000097c <- 0x2441a503 +mem-write: 0x80000980 <- 0xff010113 +mem-write: 0x80000984 <- 0x112623 +mem-write: 0x80000988 <- 0xdf9ff0ef +mem-write: 0x8000098c <- 0x2241a503 +mem-write: 0x80000990 <- 0x22c1a783 +mem-write: 0x80000994 <- 0x780e7 +mem-write: 0x80000998 <- 0xe09ff0ef +mem-write: 0x8000099c <- 0x50a63 +mem-write: 0x800009a0 <- 0xc12083 +mem-write: 0x800009a4 <- 0x513 +mem-write: 0x800009a8 <- 0x1010113 +mem-write: 0x800009ac <- 0xdd5ff06f +mem-write: 0x800009b0 <- 0xc12083 +mem-write: 0x800009b4 <- 0x100513 +mem-write: 0x800009b8 <- 0x1010113 +mem-write: 0x800009bc <- 0xdc5ff06f +mem-write: 0x800009c0 <- 0x2341a503 +mem-write: 0x800009c4 <- 0xfb010113 +mem-write: 0x800009c8 <- 0x4112623 +mem-write: 0x800009cc <- 0x3712623 +mem-write: 0x800009d0 <- 0x3a12023 +mem-write: 0x800009d4 <- 0x4812423 +mem-write: 0x800009d8 <- 0x4912223 +mem-write: 0x800009dc <- 0x5212023 +mem-write: 0x800009e0 <- 0x3312e23 +mem-write: 0x800009e4 <- 0x3412c23 +mem-write: 0x800009e8 <- 0x3512a23 +mem-write: 0x800009ec <- 0x3612823 +mem-write: 0x800009f0 <- 0x3812423 +mem-write: 0x800009f4 <- 0x3912223 +mem-write: 0x800009f8 <- 0x1b12e23 +mem-write: 0x800009fc <- 0xd85ff0ef +mem-write: 0x80000a00 <- 0xda9ff0ef +mem-write: 0x80000a04 <- 0xa12623 +mem-write: 0x80000a08 <- 0xd99ff0ef +mem-write: 0x80000a0c <- 0x2301a783 +mem-write: 0x80000a10 <- 0x50b93 +mem-write: 0x80000a14 <- 0x6078863 +mem-write: 0x80000a18 <- 0x2381a703 +mem-write: 0x80000a1c <- 0xd93 +mem-write: 0x80000a20 <- 0xa070463 +mem-write: 0x80000a24 <- 0x2281a783 +mem-write: 0x80000a28 <- 0xc12903 +mem-write: 0x80000a2c <- 0xb13 +mem-write: 0x80000a30 <- 0xb8493 +mem-write: 0x80000a34 <- 0x413 +mem-write: 0x80000a38 <- 0x2078a63 +mem-write: 0x80000a3c <- 0x2201a783 +mem-write: 0x80000a40 <- 0x2401a583 +mem-write: 0x80000a44 <- 0x23c1a503 +mem-write: 0x80000a48 <- 0x48693 +mem-write: 0x80000a4c <- 0xd8713 +mem-write: 0x80000a50 <- 0x90613 +mem-write: 0x80000a54 <- 0x780e7 +mem-write: 0x80000a58 <- 0x2281a783 +mem-write: 0x80000a5c <- 0x140413 +mem-write: 0x80000a60 <- 0x448493 +mem-write: 0x80000a64 <- 0xfcf46ce3 +mem-write: 0x80000a68 <- 0x2381a703 +mem-write: 0x80000a6c <- 0x1b0b13 +mem-write: 0x80000a70 <- 0x490913 +mem-write: 0x80000a74 <- 0xfaeb6ee3 +mem-write: 0x80000a78 <- 0x2301a783 +mem-write: 0x80000a7c <- 0x1d8d93 +mem-write: 0x80000a80 <- 0xfafde0e3 +mem-write: 0x80000a84 <- 0x40b9863 +mem-write: 0x80000a88 <- 0x4812403 +mem-write: 0x80000a8c <- 0x4c12083 +mem-write: 0x80000a90 <- 0x4412483 +mem-write: 0x80000a94 <- 0x4012903 +mem-write: 0x80000a98 <- 0x3c12983 +mem-write: 0x80000a9c <- 0x3812a03 +mem-write: 0x80000aa0 <- 0x3412a83 +mem-write: 0x80000aa4 <- 0x3012b03 +mem-write: 0x80000aa8 <- 0x2c12b83 +mem-write: 0x80000aac <- 0x2812c03 +mem-write: 0x80000ab0 <- 0x2412c83 +mem-write: 0x80000ab4 <- 0x2012d03 +mem-write: 0x80000ab8 <- 0x1c12d83 +mem-write: 0x80000abc <- 0x100513 +mem-write: 0x80000ac0 <- 0x5010113 +mem-write: 0x80000ac4 <- 0xcbdff06f +mem-write: 0x80000ac8 <- 0x1d8d93 +mem-write: 0x80000acc <- 0xfafde8e3 +mem-write: 0x80000ad0 <- 0xfa0b8ce3 +mem-write: 0x80000ad4 <- 0x513 +mem-write: 0x80000ad8 <- 0xca9ff0ef +mem-write: 0x80000adc <- 0xfadff06f +mem-write: 0x80000ae0 <- 0xff010113 +mem-write: 0x80000ae4 <- 0x58793 +mem-write: 0x80000ae8 <- 0x800015b7 +mem-write: 0x80000aec <- 0x812423 +mem-write: 0x80000af0 <- 0x912223 +mem-write: 0x80000af4 <- 0x1212023 +mem-write: 0x80000af8 <- 0x97c58593 +mem-write: 0x80000afc <- 0x112623 +mem-write: 0x80000b00 <- 0x22c1a623 +mem-write: 0x80000b04 <- 0x22d1a223 +mem-write: 0x80000b08 <- 0x24f1a223 +mem-write: 0x80000b0c <- 0xc6dff0ef +mem-write: 0x80000b10 <- 0x2441a503 +mem-write: 0x80000b14 <- 0xc6dff0ef +mem-write: 0x80000b18 <- 0x2241a503 +mem-write: 0x80000b1c <- 0x22c1a783 +mem-write: 0x80000b20 <- 0x780e7 +mem-write: 0x80000b24 <- 0xc7dff0ef +mem-write: 0x80000b28 <- 0x2050063 +mem-write: 0x80000b2c <- 0x812403 +mem-write: 0x80000b30 <- 0xc12083 +mem-write: 0x80000b34 <- 0x412483 +mem-write: 0x80000b38 <- 0x12903 +mem-write: 0x80000b3c <- 0x513 +mem-write: 0x80000b40 <- 0x1010113 +mem-write: 0x80000b44 <- 0xc3dff06f +mem-write: 0x80000b48 <- 0x812403 +mem-write: 0x80000b4c <- 0xc12083 +mem-write: 0x80000b50 <- 0x412483 +mem-write: 0x80000b54 <- 0x12903 +mem-write: 0x80000b58 <- 0x100513 +mem-write: 0x80000b5c <- 0x1010113 +mem-write: 0x80000b60 <- 0xc21ff06f +mem-write: 0x80000b64 <- 0x52703 +mem-write: 0x80000b68 <- 0xff010113 +mem-write: 0x80000b6c <- 0x50793 +mem-write: 0x80000b70 <- 0x112623 +mem-write: 0x80000b74 <- 0x812423 +mem-write: 0x80000b78 <- 0x912223 +mem-write: 0x80000b7c <- 0x400513 +mem-write: 0x80000b80 <- 0x100693 +mem-write: 0x80000b84 <- 0xe57663 +mem-write: 0x80000b88 <- 0x275693 +mem-write: 0x80000b8c <- 0x400713 +mem-write: 0x80000b90 <- 0x87a803 +mem-write: 0x80000b94 <- 0x22d1ac23 +mem-write: 0x80000b98 <- 0x22e1aa23 +mem-write: 0x80000b9c <- 0x2301a823 +mem-write: 0x80000ba0 <- 0x47a503 +mem-write: 0x80000ba4 <- 0x22b1a023 +mem-write: 0x80000ba8 <- 0x24f1a023 +mem-write: 0x80000bac <- 0x22c1ae23 +mem-write: 0x80000bb0 <- 0x100793 +mem-write: 0x80000bb4 <- 0x2a7f263 +mem-write: 0x80000bb8 <- 0x400713 +mem-write: 0x80000bbc <- 0x800015b7 +mem-write: 0x80000bc0 <- 0x4a77e63 +mem-write: 0x80000bc4 <- 0x255793 +mem-write: 0x80000bc8 <- 0x9c058593 +mem-write: 0x80000bcc <- 0x400513 +mem-write: 0x80000bd0 <- 0x22f1a423 +mem-write: 0x80000bd4 <- 0xba5ff0ef +mem-write: 0x80000bd8 <- 0xbd9ff0ef +mem-write: 0x80000bdc <- 0x50413 +mem-write: 0x80000be0 <- 0xbd9ff0ef +mem-write: 0x80000be4 <- 0xdddff0ef +mem-write: 0x80000be8 <- 0xbc9ff0ef +mem-write: 0x80000bec <- 0x50493 +mem-write: 0x80000bf0 <- 0xbc9ff0ef +mem-write: 0x80000bf4 <- 0x80015537 +mem-write: 0x80000bf8 <- 0x408485b3 +mem-write: 0x80000bfc <- 0xa0050513 +VXDRV: upload 1024 bytes to 0x80000c00 +mem-write: 0x80000c00 <- 0x334000ef +mem-write: 0x80000c04 <- 0x812403 +mem-write: 0x80000c08 <- 0xc12083 +mem-write: 0x80000c0c <- 0x412483 +mem-write: 0x80000c10 <- 0x513 +mem-write: 0x80000c14 <- 0x1010113 +mem-write: 0x80000c18 <- 0xb69ff06f +mem-write: 0x80000c1c <- 0x9c058593 +mem-write: 0x80000c20 <- 0x22f1a423 +mem-write: 0x80000c24 <- 0xb55ff0ef +mem-write: 0x80000c28 <- 0xfb1ff06f +mem-write: 0x80000c2c <- 0xff010113 +mem-write: 0x80000c30 <- 0x112623 +mem-write: 0x80000c34 <- 0x812423 +mem-write: 0x80000c38 <- 0x912223 +mem-write: 0x80000c3c <- 0x1212023 +mem-write: 0x80000c40 <- 0x50493 +mem-write: 0x80000c44 <- 0xb5dff0ef +mem-write: 0x80000c48 <- 0x50413 +mem-write: 0x80000c4c <- 0xb5dff0ef +mem-write: 0x80000c50 <- 0x104a783 +mem-write: 0x80000c54 <- 0xf47863 +mem-write: 0x80000c58 <- 0xc4a783 +mem-write: 0x80000c5c <- 0x50913 +mem-write: 0x80000c60 <- 0x2f56263 +mem-write: 0x80000c64 <- 0x513 +mem-write: 0x80000c68 <- 0xb29ff0ef +mem-write: 0x80000c6c <- 0x812403 +mem-write: 0x80000c70 <- 0xc12083 +mem-write: 0x80000c74 <- 0x412483 +mem-write: 0x80000c78 <- 0x12903 +mem-write: 0x80000c7c <- 0x1010113 +mem-write: 0x80000c80 <- 0xb19ff06f +mem-write: 0x80000c84 <- 0x100513 +mem-write: 0x80000c88 <- 0xb09ff0ef +mem-write: 0x80000c8c <- 0xc4a503 +mem-write: 0x80000c90 <- 0x4a703 +mem-write: 0x80000c94 <- 0x44a683 +mem-write: 0x80000c98 <- 0x2a40433 +mem-write: 0x80000c9c <- 0x84a783 +mem-write: 0x80000ca0 <- 0xc12083 +mem-write: 0x80000ca4 <- 0x412483 +mem-write: 0x80000ca8 <- 0x1240433 +mem-write: 0x80000cac <- 0x241413 +mem-write: 0x80000cb0 <- 0x870733 +mem-write: 0x80000cb4 <- 0x8686b3 +mem-write: 0x80000cb8 <- 0x72703 +mem-write: 0x80000cbc <- 0x6a683 +mem-write: 0x80000cc0 <- 0x878433 +mem-write: 0x80000cc4 <- 0x12903 +mem-write: 0x80000cc8 <- 0xd707b3 +mem-write: 0x80000ccc <- 0xf42023 +mem-write: 0x80000cd0 <- 0x812403 +mem-write: 0x80000cd4 <- 0x1010113 +mem-write: 0x80000cd8 <- 0xac1ff06f +mem-write: 0x80000cdc <- 0x50593 +mem-write: 0x80000ce0 <- 0x693 +mem-write: 0x80000ce4 <- 0x613 +mem-write: 0x80000ce8 <- 0x513 +mem-write: 0x80000cec <- 0x7590206f +mem-write: 0x80000cf0 <- 0xff010113 +mem-write: 0x80000cf4 <- 0x593 +mem-write: 0x80000cf8 <- 0x812423 +mem-write: 0x80000cfc <- 0x112623 +mem-write: 0x80000d00 <- 0x50413 +mem-write: 0x80000d04 <- 0x7d9020ef +mem-write: 0x80000d08 <- 0x1c01a503 +mem-write: 0x80000d0c <- 0x3c52783 +mem-write: 0x80000d10 <- 0x78463 +mem-write: 0x80000d14 <- 0x780e7 +mem-write: 0x80000d18 <- 0x40513 +mem-write: 0x80000d1c <- 0x915ff0ef +mem-write: 0x80000d20 <- 0xff010113 +mem-write: 0x80000d24 <- 0x812423 +mem-write: 0x80000d28 <- 0x800167b7 +mem-write: 0x80000d2c <- 0x80016437 +mem-write: 0x80000d30 <- 0x440413 +mem-write: 0x80000d34 <- 0x478793 +mem-write: 0x80000d38 <- 0x408787b3 +mem-write: 0x80000d3c <- 0x912223 +mem-write: 0x80000d40 <- 0x112623 +mem-write: 0x80000d44 <- 0x4027d493 +mem-write: 0x80000d48 <- 0x2048063 +mem-write: 0x80000d4c <- 0xffc78793 +mem-write: 0x80000d50 <- 0x878433 +mem-write: 0x80000d54 <- 0x42783 +mem-write: 0x80000d58 <- 0xfff48493 +mem-write: 0x80000d5c <- 0xffc40413 +mem-write: 0x80000d60 <- 0x780e7 +mem-write: 0x80000d64 <- 0xfe0498e3 +mem-write: 0x80000d68 <- 0xc12083 +mem-write: 0x80000d6c <- 0x812403 +mem-write: 0x80000d70 <- 0x412483 +mem-write: 0x80000d74 <- 0x1010113 +mem-write: 0x80000d78 <- 0x8067 +mem-write: 0x80000d7c <- 0xff010113 +mem-write: 0x80000d80 <- 0x812423 +mem-write: 0x80000d84 <- 0x1212023 +mem-write: 0x80000d88 <- 0x80016437 +mem-write: 0x80000d8c <- 0x80016937 +mem-write: 0x80000d90 <- 0x40793 +mem-write: 0x80000d94 <- 0x90913 +mem-write: 0x80000d98 <- 0x40f90933 +mem-write: 0x80000d9c <- 0x112623 +mem-write: 0x80000da0 <- 0x912223 +mem-write: 0x80000da4 <- 0x40295913 +mem-write: 0x80000da8 <- 0x2090063 +mem-write: 0x80000dac <- 0x40413 +mem-write: 0x80000db0 <- 0x493 +mem-write: 0x80000db4 <- 0x42783 +mem-write: 0x80000db8 <- 0x148493 +mem-write: 0x80000dbc <- 0x440413 +mem-write: 0x80000dc0 <- 0x780e7 +mem-write: 0x80000dc4 <- 0xfe9918e3 +mem-write: 0x80000dc8 <- 0x80016437 +mem-write: 0x80000dcc <- 0x80016937 +mem-write: 0x80000dd0 <- 0x40793 +mem-write: 0x80000dd4 <- 0x490913 +mem-write: 0x80000dd8 <- 0x40f90933 +mem-write: 0x80000ddc <- 0x40295913 +mem-write: 0x80000de0 <- 0x2090063 +mem-write: 0x80000de4 <- 0x40413 +mem-write: 0x80000de8 <- 0x493 +mem-write: 0x80000dec <- 0x42783 +mem-write: 0x80000df0 <- 0x148493 +mem-write: 0x80000df4 <- 0x440413 +mem-write: 0x80000df8 <- 0x780e7 +mem-write: 0x80000dfc <- 0xfe9918e3 +mem-write: 0x80000e00 <- 0xc12083 +mem-write: 0x80000e04 <- 0x812403 +mem-write: 0x80000e08 <- 0x412483 +mem-write: 0x80000e0c <- 0x12903 +mem-write: 0x80000e10 <- 0x1010113 +mem-write: 0x80000e14 <- 0x8067 +mem-write: 0x80000e18 <- 0xf00313 +mem-write: 0x80000e1c <- 0x50713 +mem-write: 0x80000e20 <- 0x2c37e63 +mem-write: 0x80000e24 <- 0xf77793 +mem-write: 0x80000e28 <- 0xa079063 +mem-write: 0x80000e2c <- 0x8059263 +mem-write: 0x80000e30 <- 0xff067693 +mem-write: 0x80000e34 <- 0xf67613 +mem-write: 0x80000e38 <- 0xe686b3 +mem-write: 0x80000e3c <- 0xb72023 +mem-write: 0x80000e40 <- 0xb72223 +mem-write: 0x80000e44 <- 0xb72423 +mem-write: 0x80000e48 <- 0xb72623 +mem-write: 0x80000e4c <- 0x1070713 +mem-write: 0x80000e50 <- 0xfed766e3 +mem-write: 0x80000e54 <- 0x61463 +mem-write: 0x80000e58 <- 0x8067 +mem-write: 0x80000e5c <- 0x40c306b3 +mem-write: 0x80000e60 <- 0x269693 +mem-write: 0x80000e64 <- 0x297 +mem-write: 0x80000e68 <- 0x5686b3 +mem-write: 0x80000e6c <- 0xc68067 +mem-write: 0x80000e70 <- 0xb70723 +mem-write: 0x80000e74 <- 0xb706a3 +mem-write: 0x80000e78 <- 0xb70623 +mem-write: 0x80000e7c <- 0xb705a3 +mem-write: 0x80000e80 <- 0xb70523 +mem-write: 0x80000e84 <- 0xb704a3 +mem-write: 0x80000e88 <- 0xb70423 +mem-write: 0x80000e8c <- 0xb703a3 +mem-write: 0x80000e90 <- 0xb70323 +mem-write: 0x80000e94 <- 0xb702a3 +mem-write: 0x80000e98 <- 0xb70223 +mem-write: 0x80000e9c <- 0xb701a3 +mem-write: 0x80000ea0 <- 0xb70123 +mem-write: 0x80000ea4 <- 0xb700a3 +mem-write: 0x80000ea8 <- 0xb70023 +mem-write: 0x80000eac <- 0x8067 +mem-write: 0x80000eb0 <- 0xff5f593 +mem-write: 0x80000eb4 <- 0x859693 +mem-write: 0x80000eb8 <- 0xd5e5b3 +mem-write: 0x80000ebc <- 0x1059693 +mem-write: 0x80000ec0 <- 0xd5e5b3 +mem-write: 0x80000ec4 <- 0xf6dff06f +mem-write: 0x80000ec8 <- 0x279693 +mem-write: 0x80000ecc <- 0x297 +mem-write: 0x80000ed0 <- 0x5686b3 +mem-write: 0x80000ed4 <- 0x8293 +mem-write: 0x80000ed8 <- 0xfa0680e7 +mem-write: 0x80000edc <- 0x28093 +mem-write: 0x80000ee0 <- 0xff078793 +mem-write: 0x80000ee4 <- 0x40f70733 +mem-write: 0x80000ee8 <- 0xf60633 +mem-write: 0x80000eec <- 0xf6c378e3 +mem-write: 0x80000ef0 <- 0xf3dff06f +mem-write: 0x80000ef4 <- 0xfc010113 +mem-write: 0x80000ef8 <- 0x2c12423 +mem-write: 0x80000efc <- 0x2d12623 +mem-write: 0x80000f00 <- 0x2e12823 +mem-write: 0x80000f04 <- 0x2f12a23 +mem-write: 0x80000f08 <- 0x3012c23 +mem-write: 0x80000f0c <- 0x3112e23 +mem-write: 0x80000f10 <- 0x58613 +mem-write: 0x80000f14 <- 0x852583 +mem-write: 0x80000f18 <- 0x2810693 +mem-write: 0x80000f1c <- 0x112e23 +mem-write: 0x80000f20 <- 0xd12623 +mem-write: 0x80000f24 <- 0x5c000ef +mem-write: 0x80000f28 <- 0x1c12083 +mem-write: 0x80000f2c <- 0x4010113 +mem-write: 0x80000f30 <- 0x8067 +mem-write: 0x80000f34 <- 0x1d81a303 +mem-write: 0x80000f38 <- 0xfc010113 +mem-write: 0x80000f3c <- 0x2c12423 +mem-write: 0x80000f40 <- 0x2d12623 +mem-write: 0x80000f44 <- 0x2b12223 +mem-write: 0x80000f48 <- 0x2e12823 +mem-write: 0x80000f4c <- 0x2f12a23 +mem-write: 0x80000f50 <- 0x3012c23 +mem-write: 0x80000f54 <- 0x3112e23 +mem-write: 0x80000f58 <- 0x832583 +mem-write: 0x80000f5c <- 0x2410693 +mem-write: 0x80000f60 <- 0x50613 +mem-write: 0x80000f64 <- 0x30513 +mem-write: 0x80000f68 <- 0x112e23 +mem-write: 0x80000f6c <- 0xd12623 +mem-write: 0x80000f70 <- 0x10000ef +mem-write: 0x80000f74 <- 0x1c12083 +mem-write: 0x80000f78 <- 0x4010113 +mem-write: 0x80000f7c <- 0x8067 +mem-write: 0x80000f80 <- 0xe1010113 +mem-write: 0x80000f84 <- 0x1e112623 +mem-write: 0x80000f88 <- 0x1f212023 +mem-write: 0x80000f8c <- 0x1d812423 +mem-write: 0x80000f90 <- 0x1da12023 +mem-write: 0x80000f94 <- 0x58c13 +mem-write: 0x80000f98 <- 0x60913 +mem-write: 0x80000f9c <- 0xd12a23 +mem-write: 0x80000fa0 <- 0x1e812423 +mem-write: 0x80000fa4 <- 0x1e912223 +mem-write: 0x80000fa8 <- 0x1d312e23 +mem-write: 0x80000fac <- 0x1d412c23 +mem-write: 0x80000fb0 <- 0x1d512a23 +mem-write: 0x80000fb4 <- 0x1d612823 +mem-write: 0x80000fb8 <- 0x1d712623 +mem-write: 0x80000fbc <- 0x1d912223 +mem-write: 0x80000fc0 <- 0x1bb12e23 +mem-write: 0x80000fc4 <- 0x50d13 +mem-write: 0x80000fc8 <- 0x570060ef +mem-write: 0x80000fcc <- 0x52783 +mem-write: 0x80000fd0 <- 0x78513 +mem-write: 0x80000fd4 <- 0x2f12823 +mem-write: 0x80000fd8 <- 0x514080ef +mem-write: 0x80000fdc <- 0x2a12623 +mem-write: 0x80000fe0 <- 0xe012823 +mem-write: 0x80000fe4 <- 0xe012a23 +mem-write: 0x80000fe8 <- 0xe012c23 +mem-write: 0x80000fec <- 0xe012e23 +mem-write: 0x80000ff0 <- 0xd0663 +mem-write: 0x80000ff4 <- 0x38d2703 +mem-write: 0x80000ff8 <- 0xa0708e3 +mem-write: 0x80000ffc <- 0xcc1683 +VXDRV: upload 1024 bytes to 0x80001000 +mem-write: 0x80001000 <- 0x1069713 +mem-write: 0x80001004 <- 0x1269793 +mem-write: 0x80001008 <- 0x1075713 +mem-write: 0x8000100c <- 0x207ca63 +mem-write: 0x80001010 <- 0x2737 +mem-write: 0x80001014 <- 0x64c2603 +mem-write: 0x80001018 <- 0xe6e733 +mem-write: 0x8000101c <- 0x1071713 +mem-write: 0x80001020 <- 0xffffe6b7 +mem-write: 0x80001024 <- 0x41075713 +mem-write: 0x80001028 <- 0xfff68693 +mem-write: 0x8000102c <- 0xd676b3 +mem-write: 0x80001030 <- 0xec1623 +mem-write: 0x80001034 <- 0x1071713 +mem-write: 0x80001038 <- 0x6dc2223 +mem-write: 0x8000103c <- 0x1075713 +mem-write: 0x80001040 <- 0x877693 +mem-write: 0x80001044 <- 0x2e068863 +mem-write: 0x80001048 <- 0x10c2683 +mem-write: 0x8000104c <- 0x2e068463 +mem-write: 0x80001050 <- 0x1a77713 +mem-write: 0x80001054 <- 0xa00693 +mem-write: 0x80001058 <- 0x30d70063 +mem-write: 0x8000105c <- 0x10c10793 +mem-write: 0x80001060 <- 0x80015737 +mem-write: 0x80001064 <- 0xef12223 +mem-write: 0x80001068 <- 0x78893 +mem-write: 0x8000106c <- 0xa6c70793 +mem-write: 0x80001070 <- 0x80015737 +mem-write: 0x80001074 <- 0xf12c23 +mem-write: 0x80001078 <- 0x90b13 +mem-write: 0x8000107c <- 0xbe870793 +mem-write: 0x80001080 <- 0xf12423 +mem-write: 0x80001084 <- 0xb4783 +mem-write: 0x80001088 <- 0xe012623 +mem-write: 0x8000108c <- 0xe012423 +mem-write: 0x80001090 <- 0x2012023 +mem-write: 0x80001094 <- 0x2012a23 +mem-write: 0x80001098 <- 0x2012c23 +mem-write: 0x8000109c <- 0x2012e23 +mem-write: 0x800010a0 <- 0x4012423 +mem-write: 0x800010a4 <- 0x4012623 +mem-write: 0x800010a8 <- 0x12623 +mem-write: 0x800010ac <- 0x22078663 +mem-write: 0x800010b0 <- 0xb0413 +mem-write: 0x800010b4 <- 0x2500693 +mem-write: 0x800010b8 <- 0x30d78a63 +mem-write: 0x800010bc <- 0x144783 +mem-write: 0x800010c0 <- 0x140413 +mem-write: 0x800010c4 <- 0xfe079ae3 +mem-write: 0x800010c8 <- 0x416404b3 +mem-write: 0x800010cc <- 0x21640663 +mem-write: 0x800010d0 <- 0xec12683 +mem-write: 0x800010d4 <- 0xe812783 +mem-write: 0x800010d8 <- 0x168a023 +mem-write: 0x800010dc <- 0x9686b3 +mem-write: 0x800010e0 <- 0x178793 +mem-write: 0x800010e4 <- 0x98a223 +mem-write: 0x800010e8 <- 0xed12623 +mem-write: 0x800010ec <- 0xef12423 +mem-write: 0x800010f0 <- 0x700693 +mem-write: 0x800010f4 <- 0x888893 +mem-write: 0x800010f8 <- 0x2ef6c263 +mem-write: 0x800010fc <- 0xc12703 +mem-write: 0x80001100 <- 0x44783 +mem-write: 0x80001104 <- 0x970733 +mem-write: 0x80001108 <- 0xe12623 +mem-write: 0x8000110c <- 0x1c078663 +mem-write: 0x80001110 <- 0x144483 +mem-write: 0x80001114 <- 0xc0103a3 +mem-write: 0x80001118 <- 0x140413 +mem-write: 0x8000111c <- 0xfff00d93 +mem-write: 0x80001120 <- 0x993 +mem-write: 0x80001124 <- 0xa13 +mem-write: 0x80001128 <- 0x5a00913 +mem-write: 0x8000112c <- 0x900a93 +mem-write: 0x80001130 <- 0x2a00b93 +mem-write: 0x80001134 <- 0x88c93 +mem-write: 0x80001138 <- 0x140413 +mem-write: 0x8000113c <- 0xfe048793 +mem-write: 0x80001140 <- 0x4f96463 +mem-write: 0x80001144 <- 0x1812703 +mem-write: 0x80001148 <- 0x279793 +mem-write: 0x8000114c <- 0xe787b3 +mem-write: 0x80001150 <- 0x7a783 +mem-write: 0x80001154 <- 0x78067 +mem-write: 0x80001158 <- 0x993 +mem-write: 0x8000115c <- 0xfd048693 +mem-write: 0x80001160 <- 0x44483 +mem-write: 0x80001164 <- 0x299793 +mem-write: 0x80001168 <- 0x13787b3 +mem-write: 0x8000116c <- 0x179793 +mem-write: 0x80001170 <- 0xf689b3 +mem-write: 0x80001174 <- 0xfd048693 +mem-write: 0x80001178 <- 0x140413 +mem-write: 0x8000117c <- 0xfedaf2e3 +mem-write: 0x80001180 <- 0xfe048793 +mem-write: 0x80001184 <- 0xfcf970e3 +mem-write: 0x80001188 <- 0xc8893 +mem-write: 0x8000118c <- 0x14048663 +mem-write: 0x80001190 <- 0x14910623 +mem-write: 0x80001194 <- 0xc0103a3 +mem-write: 0x80001198 <- 0x100a93 +mem-write: 0x8000119c <- 0x100c93 +mem-write: 0x800011a0 <- 0x14c10b13 +mem-write: 0x800011a4 <- 0x12823 +mem-write: 0x800011a8 <- 0xd93 +mem-write: 0x800011ac <- 0x2012423 +mem-write: 0x800011b0 <- 0x2012223 +mem-write: 0x800011b4 <- 0x12e23 +mem-write: 0x800011b8 <- 0x2a7b93 +mem-write: 0x800011bc <- 0xb8463 +mem-write: 0x800011c0 <- 0x2a8a93 +mem-write: 0x800011c4 <- 0x84a7913 +mem-write: 0x800011c8 <- 0xec12783 +mem-write: 0x800011cc <- 0x91663 +mem-write: 0x800011d0 <- 0x41598833 +mem-write: 0x800011d4 <- 0x710046e3 +mem-write: 0x800011d8 <- 0xc714683 +mem-write: 0x800011dc <- 0x2068a63 +mem-write: 0x800011e0 <- 0xe812683 +mem-write: 0x800011e4 <- 0xc710613 +mem-write: 0x800011e8 <- 0xc8a023 +mem-write: 0x800011ec <- 0x178793 +mem-write: 0x800011f0 <- 0x100613 +mem-write: 0x800011f4 <- 0x168693 +mem-write: 0x800011f8 <- 0xc8a223 +mem-write: 0x800011fc <- 0xef12623 +mem-write: 0x80001200 <- 0xed12423 +mem-write: 0x80001204 <- 0x700613 +mem-write: 0x80001208 <- 0x888893 +mem-write: 0x8000120c <- 0x52d64263 +mem-write: 0x80001210 <- 0x20b8c63 +mem-write: 0x80001214 <- 0xe812683 +mem-write: 0x80001218 <- 0xc810613 +mem-write: 0x8000121c <- 0xc8a023 +mem-write: 0x80001220 <- 0x278793 +mem-write: 0x80001224 <- 0x200613 +mem-write: 0x80001228 <- 0x168693 +mem-write: 0x8000122c <- 0xc8a223 +mem-write: 0x80001230 <- 0xef12623 +mem-write: 0x80001234 <- 0xed12423 +mem-write: 0x80001238 <- 0x700613 +mem-write: 0x8000123c <- 0x888893 +mem-write: 0x80001240 <- 0xd65463 +mem-write: 0x80001244 <- 0x78d0006f +mem-write: 0x80001248 <- 0x8000693 +mem-write: 0x8000124c <- 0x3cd90ee3 +mem-write: 0x80001250 <- 0x419d8db3 +mem-write: 0x80001254 <- 0x49b04ae3 +mem-write: 0x80001258 <- 0x100a7693 +mem-write: 0x8000125c <- 0x280698e3 +mem-write: 0x80001260 <- 0xe812703 +mem-write: 0x80001264 <- 0x19787b3 +mem-write: 0x80001268 <- 0x168a023 +mem-write: 0x8000126c <- 0x170713 +mem-write: 0x80001270 <- 0x198a223 +mem-write: 0x80001274 <- 0xef12623 +mem-write: 0x80001278 <- 0xee12423 +mem-write: 0x8000127c <- 0x700693 +mem-write: 0x80001280 <- 0x54e6c863 +mem-write: 0x80001284 <- 0x888893 +mem-write: 0x80001288 <- 0x4a7a13 +mem-write: 0x8000128c <- 0xa0663 +mem-write: 0x80001290 <- 0x415984b3 +mem-write: 0x80001294 <- 0x54904e63 +mem-write: 0x80001298 <- 0x159d463 +mem-write: 0x8000129c <- 0xa8993 +mem-write: 0x800012a0 <- 0xc12703 +mem-write: 0x800012a4 <- 0x1370733 +mem-write: 0x800012a8 <- 0xe12623 +mem-write: 0x800012ac <- 0x4e0798e3 +mem-write: 0x800012b0 <- 0x1012783 +mem-write: 0x800012b4 <- 0xe012423 +mem-write: 0x800012b8 <- 0x78863 +mem-write: 0x800012bc <- 0x1012583 +mem-write: 0x800012c0 <- 0xd0513 +mem-write: 0x800012c4 <- 0x2a0030ef +mem-write: 0x800012c8 <- 0x10c10893 +mem-write: 0x800012cc <- 0x40b13 +mem-write: 0x800012d0 <- 0xb4783 +mem-write: 0x800012d4 <- 0xdc079ee3 +mem-write: 0x800012d8 <- 0xec12783 +mem-write: 0x800012dc <- 0x78463 +mem-write: 0x800012e0 <- 0x3250106f +mem-write: 0x800012e4 <- 0xcc5783 +mem-write: 0x800012e8 <- 0x407f793 +mem-write: 0x800012ec <- 0x78463 +mem-write: 0x800012f0 <- 0x2300206f +mem-write: 0x800012f4 <- 0x1ec12083 +mem-write: 0x800012f8 <- 0x1e812403 +mem-write: 0x800012fc <- 0xc12503 +mem-write: 0x80001300 <- 0x1e412483 +mem-write: 0x80001304 <- 0x1e012903 +mem-write: 0x80001308 <- 0x1dc12983 +mem-write: 0x8000130c <- 0x1d812a03 +mem-write: 0x80001310 <- 0x1d412a83 +mem-write: 0x80001314 <- 0x1d012b03 +mem-write: 0x80001318 <- 0x1cc12b83 +mem-write: 0x8000131c <- 0x1c812c03 +mem-write: 0x80001320 <- 0x1c412c83 +mem-write: 0x80001324 <- 0x1c012d03 +mem-write: 0x80001328 <- 0x1bc12d83 +mem-write: 0x8000132c <- 0x1f010113 +mem-write: 0x80001330 <- 0x8067 +mem-write: 0x80001334 <- 0xc0593 +mem-write: 0x80001338 <- 0xd0513 +mem-write: 0x8000133c <- 0x7ac020ef +mem-write: 0x80001340 <- 0x50463 +mem-write: 0x80001344 <- 0x1dc0206f +mem-write: 0x80001348 <- 0xcc5703 +mem-write: 0x8000134c <- 0xa00693 +mem-write: 0x80001350 <- 0x1a77713 +mem-write: 0x80001354 <- 0xd0d714e3 +mem-write: 0x80001358 <- 0xec1703 +mem-write: 0x8000135c <- 0xd00740e3 +mem-write: 0x80001360 <- 0x1412683 +mem-write: 0x80001364 <- 0x90613 +mem-write: 0x80001368 <- 0xc0593 +mem-write: 0x8000136c <- 0xd0513 +mem-write: 0x80001370 <- 0x6b8020ef +mem-write: 0x80001374 <- 0xa12623 +mem-write: 0x80001378 <- 0xf7dff06f +mem-write: 0x8000137c <- 0xd0513 +mem-write: 0x80001380 <- 0x1b8060ef +mem-write: 0x80001384 <- 0x452783 +mem-write: 0x80001388 <- 0x78513 +mem-write: 0x8000138c <- 0x4f12623 +mem-write: 0x80001390 <- 0x15c080ef +mem-write: 0x80001394 <- 0x50793 +mem-write: 0x80001398 <- 0xd0513 +mem-write: 0x8000139c <- 0x78493 +mem-write: 0x800013a0 <- 0x4f12423 +mem-write: 0x800013a4 <- 0x194060ef +mem-write: 0x800013a8 <- 0x852783 +mem-write: 0x800013ac <- 0x2f12e23 +mem-write: 0x800013b0 <- 0x48463 +mem-write: 0x800013b4 <- 0x12c0106f +mem-write: 0x800013b8 <- 0x44483 +mem-write: 0x800013bc <- 0xd7dff06f +mem-write: 0x800013c0 <- 0x44483 +mem-write: 0x800013c4 <- 0x20a6a13 +mem-write: 0x800013c8 <- 0xd71ff06f +mem-write: 0x800013cc <- 0x416404b3 +mem-write: 0x800013d0 <- 0xd16410e3 +mem-write: 0x800013d4 <- 0x44783 +mem-write: 0x800013d8 <- 0xd35ff06f +mem-write: 0x800013dc <- 0xe410613 +mem-write: 0x800013e0 <- 0xc0593 +mem-write: 0x800013e4 <- 0xd0513 +mem-write: 0x800013e8 <- 0x53d0a0ef +mem-write: 0x800013ec <- 0xee051ce3 +mem-write: 0x800013f0 <- 0x10c10893 +mem-write: 0x800013f4 <- 0xd09ff06f +mem-write: 0x800013f8 <- 0x8a7793 +mem-write: 0x800013fc <- 0xc8893 +VXDRV: upload 1024 bytes to 0x80001400 +mem-write: 0x80001400 <- 0x78463 +mem-write: 0x80001404 <- 0x12c0106f +mem-write: 0x80001408 <- 0x1412783 +mem-write: 0x8000140c <- 0xb010513 +mem-write: 0x80001410 <- 0x1912823 +mem-write: 0x80001414 <- 0x778793 +mem-write: 0x80001418 <- 0xff87f793 +mem-write: 0x8000141c <- 0x7a583 +mem-write: 0x80001420 <- 0x47a603 +mem-write: 0x80001424 <- 0x878793 +mem-write: 0x80001428 <- 0xf12a23 +mem-write: 0x8000142c <- 0x781120ef +mem-write: 0x80001430 <- 0xb012783 +mem-write: 0x80001434 <- 0x1012883 +mem-write: 0x80001438 <- 0xef12823 +mem-write: 0x8000143c <- 0xb412783 +mem-write: 0x80001440 <- 0xef12a23 +mem-write: 0x80001444 <- 0xb812783 +mem-write: 0x80001448 <- 0xef12c23 +mem-write: 0x8000144c <- 0xbc12783 +mem-write: 0x80001450 <- 0xef12e23 +mem-write: 0x80001454 <- 0xf010513 +mem-write: 0x80001458 <- 0x1112823 +mem-write: 0x8000145c <- 0x70060ef +mem-write: 0x80001460 <- 0xca12623 +mem-write: 0x80001464 <- 0x200793 +mem-write: 0x80001468 <- 0x1012883 +mem-write: 0x8000146c <- 0xf51463 +mem-write: 0x80001470 <- 0x4fc0106f +mem-write: 0x80001474 <- 0x100793 +mem-write: 0x80001478 <- 0xf51463 +mem-write: 0x8000147c <- 0x6440106f +mem-write: 0x80001480 <- 0x6100793 +mem-write: 0x80001484 <- 0xf49463 +mem-write: 0x80001488 <- 0x1c40206f +mem-write: 0x8000148c <- 0x4100793 +mem-write: 0x80001490 <- 0xf49463 +mem-write: 0x80001494 <- 0x1910106f +mem-write: 0x80001498 <- 0xfdf4fb93 +mem-write: 0x8000149c <- 0xfff00793 +mem-write: 0x800014a0 <- 0x5712223 +mem-write: 0x800014a4 <- 0xfd9463 +mem-write: 0x800014a8 <- 0x2800206f +mem-write: 0x800014ac <- 0x4700793 +mem-write: 0x800014b0 <- 0xfb9463 +mem-write: 0x800014b4 <- 0x1e00206f +mem-write: 0x800014b8 <- 0xfc12303 +mem-write: 0x800014bc <- 0x3412423 +mem-write: 0x800014c0 <- 0xf012e03 +mem-write: 0x800014c4 <- 0xf412e83 +mem-write: 0x800014c8 <- 0xf812f03 +mem-write: 0x800014cc <- 0x100a6793 +mem-write: 0x800014d0 <- 0x35463 +mem-write: 0x800014d4 <- 0x3e00206f +mem-write: 0x800014d8 <- 0x4012c23 +mem-write: 0x800014dc <- 0x78a13 +mem-write: 0x800014e0 <- 0x12823 +mem-write: 0x800014e4 <- 0x4600793 +mem-write: 0x800014e8 <- 0xfb9463 +mem-write: 0x800014ec <- 0x6990106f +mem-write: 0x800014f0 <- 0x4500793 +mem-write: 0x800014f4 <- 0x5112823 +mem-write: 0x800014f8 <- 0xfb8463 +mem-write: 0x800014fc <- 0x6090106f +mem-write: 0x80001500 <- 0x1d8913 +mem-write: 0x80001504 <- 0xb010a93 +mem-write: 0x80001508 <- 0x90693 +mem-write: 0x8000150c <- 0xdc10813 +mem-write: 0x80001510 <- 0xd010793 +mem-write: 0x80001514 <- 0xcc10713 +mem-write: 0x80001518 <- 0x200613 +mem-write: 0x8000151c <- 0xa8593 +mem-write: 0x80001520 <- 0xd0513 +mem-write: 0x80001524 <- 0xbc12823 +mem-write: 0x80001528 <- 0x5c12023 +mem-write: 0x8000152c <- 0xbd12a23 +mem-write: 0x80001530 <- 0x3d12223 +mem-write: 0x80001534 <- 0xbe12c23 +mem-write: 0x80001538 <- 0x3e12023 +mem-write: 0x8000153c <- 0xa612e23 +mem-write: 0x80001540 <- 0x612e23 +mem-write: 0x80001544 <- 0x4f1040ef +mem-write: 0x80001548 <- 0x1c12303 +mem-write: 0x8000154c <- 0x2012f03 +mem-write: 0x80001550 <- 0x2412e83 +mem-write: 0x80001554 <- 0x4012e03 +mem-write: 0x80001558 <- 0x5012883 +mem-write: 0x8000155c <- 0x50b13 +mem-write: 0x80001560 <- 0x1250933 +mem-write: 0x80001564 <- 0xa010c93 +mem-write: 0x80001568 <- 0xc8593 +mem-write: 0x8000156c <- 0xa8513 +mem-write: 0x80001570 <- 0x1112e23 +mem-write: 0x80001574 <- 0xbc12823 +mem-write: 0x80001578 <- 0xbd12a23 +mem-write: 0x8000157c <- 0xbe12c23 +mem-write: 0x80001580 <- 0xa612e23 +mem-write: 0x80001584 <- 0xa012023 +mem-write: 0x80001588 <- 0xa012223 +mem-write: 0x8000158c <- 0xa012423 +mem-write: 0x80001590 <- 0xa012623 +mem-write: 0x80001594 <- 0x33c100ef +mem-write: 0x80001598 <- 0x1c12883 +mem-write: 0x8000159c <- 0x90713 +mem-write: 0x800015a0 <- 0x2050263 +mem-write: 0x800015a4 <- 0xdc12703 +mem-write: 0x800015a8 <- 0x1277e63 +mem-write: 0x800015ac <- 0x3000693 +mem-write: 0x800015b0 <- 0x170793 +mem-write: 0x800015b4 <- 0xcf12e23 +mem-write: 0x800015b8 <- 0xd70023 +mem-write: 0x800015bc <- 0xdc12703 +mem-write: 0x800015c0 <- 0xff2768e3 +mem-write: 0x800015c4 <- 0x416707b3 +mem-write: 0x800015c8 <- 0x2f12023 +mem-write: 0x800015cc <- 0xcc12703 +mem-write: 0x800015d0 <- 0x4700793 +mem-write: 0x800015d4 <- 0xe12e23 +mem-write: 0x800015d8 <- 0x4412703 +mem-write: 0x800015dc <- 0xf71463 +mem-write: 0x800015e0 <- 0x43d0106f +mem-write: 0x800015e4 <- 0x4412703 +mem-write: 0x800015e8 <- 0x4600793 +mem-write: 0x800015ec <- 0xf71463 +mem-write: 0x800015f0 <- 0x67d0106f +mem-write: 0x800015f4 <- 0x1c12783 +mem-write: 0x800015f8 <- 0x4412703 +mem-write: 0x800015fc <- 0x4100593 +mem-write: 0x80001600 <- 0xfff78793 +mem-write: 0x80001604 <- 0xcf12623 +mem-write: 0x80001608 <- 0xff4f693 +mem-write: 0x8000160c <- 0x613 +mem-write: 0x80001610 <- 0xb71863 +mem-write: 0x80001614 <- 0xf68693 +mem-write: 0x80001618 <- 0xff6f693 +mem-write: 0x8000161c <- 0x100613 +mem-write: 0x80001620 <- 0xcd10a23 +mem-write: 0x80001624 <- 0x2b00693 +mem-write: 0x80001628 <- 0x7da63 +mem-write: 0x8000162c <- 0x1c12703 +mem-write: 0x80001630 <- 0x100793 +mem-write: 0x80001634 <- 0x2d00693 +mem-write: 0x80001638 <- 0x40e787b3 +mem-write: 0x8000163c <- 0xcd10aa3 +mem-write: 0x80001640 <- 0x900693 +mem-write: 0x80001644 <- 0xf6c463 +mem-write: 0x80001648 <- 0x28c0206f +mem-write: 0x8000164c <- 0xe310813 +mem-write: 0x80001650 <- 0x80513 +mem-write: 0x80001654 <- 0xa00613 +mem-write: 0x80001658 <- 0x6300e13 +mem-write: 0x8000165c <- 0x2c7e733 +mem-write: 0x80001660 <- 0x50593 +mem-write: 0x80001664 <- 0x78693 +mem-write: 0x80001668 <- 0xfff50513 +mem-write: 0x8000166c <- 0x3070713 +mem-write: 0x80001670 <- 0xfee58fa3 +mem-write: 0x80001674 <- 0x2c7c7b3 +mem-write: 0x80001678 <- 0xfede42e3 +mem-write: 0x8000167c <- 0x3078793 +mem-write: 0x80001680 <- 0xff7f613 +mem-write: 0x80001684 <- 0xfec50fa3 +mem-write: 0x80001688 <- 0xffe58793 +mem-write: 0x8000168c <- 0x107e463 +mem-write: 0x80001690 <- 0x3740206f +mem-write: 0x80001694 <- 0xd610693 +mem-write: 0x80001698 <- 0x80006f +mem-write: 0x8000169c <- 0x7c603 +mem-write: 0x800016a0 <- 0xc68023 +mem-write: 0x800016a4 <- 0x178793 +mem-write: 0x800016a8 <- 0x168693 +mem-write: 0x800016ac <- 0xff0798e3 +mem-write: 0x800016b0 <- 0xe510793 +mem-write: 0x800016b4 <- 0x40b787b3 +mem-write: 0x800016b8 <- 0xd610713 +mem-write: 0x800016bc <- 0xf707b3 +mem-write: 0x800016c0 <- 0xd410693 +mem-write: 0x800016c4 <- 0x40d787b3 +mem-write: 0x800016c8 <- 0x2f12c23 +mem-write: 0x800016cc <- 0x2012703 +mem-write: 0x800016d0 <- 0x3812683 +mem-write: 0x800016d4 <- 0x100793 +mem-write: 0x800016d8 <- 0xd70cb3 +mem-write: 0x800016dc <- 0xe7c463 +mem-write: 0x800016e0 <- 0x2940206f +mem-write: 0x800016e4 <- 0x2c12783 +mem-write: 0x800016e8 <- 0xfc8cb3 +mem-write: 0x800016ec <- 0x2812783 +mem-write: 0x800016f0 <- 0xfffcca93 +mem-write: 0x800016f4 <- 0x41fada93 +mem-write: 0x800016f8 <- 0xbff7fa13 +mem-write: 0x800016fc <- 0x100a6a13 +mem-write: 0x80001700 <- 0x15cfab3 +mem-write: 0x80001704 <- 0x2012423 +mem-write: 0x80001708 <- 0x2012223 +mem-write: 0x8000170c <- 0x12e23 +mem-write: 0x80001710 <- 0x5812783 +mem-write: 0x80001714 <- 0x79463 +mem-write: 0x80001718 <- 0x3790106f +mem-write: 0x8000171c <- 0x2d00793 +mem-write: 0x80001720 <- 0xcf103a3 +mem-write: 0x80001724 <- 0xd93 +mem-write: 0x80001728 <- 0x1a8a93 +mem-write: 0x8000172c <- 0xa8dff06f +mem-write: 0x80001730 <- 0xe410613 +mem-write: 0x80001734 <- 0xc0593 +mem-write: 0x80001738 <- 0xd0513 +mem-write: 0x8000173c <- 0x1e90a0ef +mem-write: 0x80001740 <- 0x60518e3 +mem-write: 0x80001744 <- 0xec12783 +mem-write: 0x80001748 <- 0x10c10893 +mem-write: 0x8000174c <- 0xac5ff06f +mem-write: 0x80001750 <- 0x3012683 +mem-write: 0x80001754 <- 0x2c12703 +mem-write: 0x80001758 <- 0x700613 +mem-write: 0x8000175c <- 0xd8a023 +mem-write: 0x80001760 <- 0xe812683 +mem-write: 0x80001764 <- 0xf707b3 +mem-write: 0x80001768 <- 0xe8a223 +mem-write: 0x8000176c <- 0x168693 +mem-write: 0x80001770 <- 0xef12623 +mem-write: 0x80001774 <- 0xed12423 +mem-write: 0x80001778 <- 0x888893 +mem-write: 0x8000177c <- 0x2d65463 +mem-write: 0x80001780 <- 0xe410613 +mem-write: 0x80001784 <- 0xc0593 +mem-write: 0x80001788 <- 0xd0513 +mem-write: 0x8000178c <- 0x1990a0ef +mem-write: 0x80001790 <- 0x20510e3 +mem-write: 0x80001794 <- 0xcc12583 +mem-write: 0x80001798 <- 0xec12783 +mem-write: 0x8000179c <- 0xe812683 +mem-write: 0x800017a0 <- 0x10c10893 +mem-write: 0x800017a4 <- 0x5d463 +mem-write: 0x800017a8 <- 0x5850106f +mem-write: 0x800017ac <- 0x2012703 +mem-write: 0x800017b0 <- 0x168693 +mem-write: 0x800017b4 <- 0x168a023 +mem-write: 0x800017b8 <- 0xf707b3 +mem-write: 0x800017bc <- 0xe8a223 +mem-write: 0x800017c0 <- 0xef12623 +mem-write: 0x800017c4 <- 0xed12423 +mem-write: 0x800017c8 <- 0x700713 +mem-write: 0x800017cc <- 0xaad75ce3 +mem-write: 0x800017d0 <- 0xe410613 +mem-write: 0x800017d4 <- 0xc0593 +mem-write: 0x800017d8 <- 0xd0513 +mem-write: 0x800017dc <- 0x1490a0ef +mem-write: 0x800017e0 <- 0x7c051863 +mem-write: 0x800017e4 <- 0xec12783 +mem-write: 0x800017e8 <- 0x10c10893 +mem-write: 0x800017ec <- 0xa9dff06f +mem-write: 0x800017f0 <- 0x1000693 +mem-write: 0x800017f4 <- 0xe812703 +mem-write: 0x800017f8 <- 0x96c463 +mem-write: 0x800017fc <- 0x5190106f +VXDRV: upload 1024 bytes to 0x80001800 +mem-write: 0x80001800 <- 0x800156b7 +mem-write: 0x80001804 <- 0xbd868e93 +mem-write: 0x80001808 <- 0x1000913 +mem-write: 0x8000180c <- 0x700a13 +mem-write: 0x80001810 <- 0xe8b13 +mem-write: 0x80001814 <- 0xc0006f +mem-write: 0x80001818 <- 0xff048493 +mem-write: 0x8000181c <- 0x4995663 +mem-write: 0x80001820 <- 0x1078793 +mem-write: 0x80001824 <- 0x170713 +mem-write: 0x80001828 <- 0x168a023 +mem-write: 0x8000182c <- 0x128a223 +mem-write: 0x80001830 <- 0xef12623 +mem-write: 0x80001834 <- 0xee12423 +mem-write: 0x80001838 <- 0x888893 +mem-write: 0x8000183c <- 0xfcea5ee3 +mem-write: 0x80001840 <- 0xe410613 +mem-write: 0x80001844 <- 0xc0593 +mem-write: 0x80001848 <- 0xd0513 +mem-write: 0x8000184c <- 0xd90a0ef +mem-write: 0x80001850 <- 0x76051063 +mem-write: 0x80001854 <- 0xff048493 +mem-write: 0x80001858 <- 0xec12783 +mem-write: 0x8000185c <- 0xe812703 +mem-write: 0x80001860 <- 0x10c10893 +mem-write: 0x80001864 <- 0xfa994ee3 +mem-write: 0x80001868 <- 0xb0e93 +mem-write: 0x8000186c <- 0x9787b3 +mem-write: 0x80001870 <- 0x170713 +mem-write: 0x80001874 <- 0x1d8a023 +mem-write: 0x80001878 <- 0x98a223 +mem-write: 0x8000187c <- 0xef12623 +mem-write: 0x80001880 <- 0xee12423 +mem-write: 0x80001884 <- 0x700693 +mem-write: 0x80001888 <- 0xa0e6d8e3 +mem-write: 0x8000188c <- 0xe410613 +mem-write: 0x80001890 <- 0xc0593 +mem-write: 0x80001894 <- 0xd0513 +mem-write: 0x80001898 <- 0x8d0a0ef +mem-write: 0x8000189c <- 0x70051a63 +mem-write: 0x800018a0 <- 0xec12783 +mem-write: 0x800018a4 <- 0x9f5ff06f +mem-write: 0x800018a8 <- 0xd0513 +mem-write: 0x800018ac <- 0x349020ef +mem-write: 0x800018b0 <- 0xf4cff06f +mem-write: 0x800018b4 <- 0x1412703 +mem-write: 0x800018b8 <- 0xc8893 +mem-write: 0x800018bc <- 0xc0103a3 +mem-write: 0x800018c0 <- 0x72783 +mem-write: 0x800018c4 <- 0x470713 +mem-write: 0x800018c8 <- 0xe12a23 +mem-write: 0x800018cc <- 0x14f10623 +mem-write: 0x800018d0 <- 0x100a93 +mem-write: 0x800018d4 <- 0x100c93 +mem-write: 0x800018d8 <- 0x14c10b13 +mem-write: 0x800018dc <- 0x8c9ff06f +mem-write: 0x800018e0 <- 0x1412783 +mem-write: 0x800018e4 <- 0xc0103a3 +mem-write: 0x800018e8 <- 0xc8893 +mem-write: 0x800018ec <- 0x7ab03 +mem-write: 0x800018f0 <- 0x478913 +mem-write: 0x800018f4 <- 0x5a0b0ee3 +mem-write: 0x800018f8 <- 0xfff00793 +mem-write: 0x800018fc <- 0xfd9463 +mem-write: 0x80001900 <- 0x1000106f +mem-write: 0x80001904 <- 0xd8613 +mem-write: 0x80001908 <- 0x593 +mem-write: 0x8000190c <- 0xb0513 +mem-write: 0x80001910 <- 0x1912a23 +mem-write: 0x80001914 <- 0x5bc060ef +mem-write: 0x80001918 <- 0xa12823 +mem-write: 0x8000191c <- 0x1412883 +mem-write: 0x80001920 <- 0x51463 +mem-write: 0x80001924 <- 0x31d0106f +mem-write: 0x80001928 <- 0x1012783 +mem-write: 0x8000192c <- 0x1212a23 +mem-write: 0x80001930 <- 0x12823 +mem-write: 0x80001934 <- 0x41678cb3 +mem-write: 0x80001938 <- 0xc714783 +mem-write: 0x8000193c <- 0xfffcca93 +mem-write: 0x80001940 <- 0x41fada93 +mem-write: 0x80001944 <- 0x2012423 +mem-write: 0x80001948 <- 0x2012223 +mem-write: 0x8000194c <- 0x12e23 +mem-write: 0x80001950 <- 0x15cfab3 +mem-write: 0x80001954 <- 0xd93 +mem-write: 0x80001958 <- 0x860780e3 +mem-write: 0x8000195c <- 0x1a8a93 +mem-write: 0x80001960 <- 0x859ff06f +mem-write: 0x80001964 <- 0x44483 +mem-write: 0x80001968 <- 0x4a6a13 +mem-write: 0x8000196c <- 0xfccff06f +mem-write: 0x80001970 <- 0x1412683 +mem-write: 0x80001974 <- 0x20a7793 +mem-write: 0x80001978 <- 0xc8893 +mem-write: 0x8000197c <- 0x6a703 +mem-write: 0x80001980 <- 0x468693 +mem-write: 0x80001984 <- 0xd12a23 +mem-write: 0x80001988 <- 0x36079ee3 +mem-write: 0x8000198c <- 0x10a7793 +mem-write: 0x80001990 <- 0x78463 +mem-write: 0x80001994 <- 0x5c0106f +mem-write: 0x80001998 <- 0x40a7793 +mem-write: 0x8000199c <- 0x78463 +mem-write: 0x800019a0 <- 0x3fc0106f +mem-write: 0x800019a4 <- 0x200a7a13 +mem-write: 0x800019a8 <- 0xa1463 +mem-write: 0x800019ac <- 0x440106f +mem-write: 0x800019b0 <- 0xc12783 +mem-write: 0x800019b4 <- 0x40b13 +mem-write: 0x800019b8 <- 0xf70023 +mem-write: 0x800019bc <- 0x915ff06f +mem-write: 0x800019c0 <- 0x44483 +mem-write: 0x800019c4 <- 0x6c00793 +mem-write: 0x800019c8 <- 0x4cf484e3 +mem-write: 0x800019cc <- 0x10a6a13 +mem-write: 0x800019d0 <- 0xf68ff06f +mem-write: 0x800019d4 <- 0x1412703 +mem-write: 0x800019d8 <- 0xffff87b7 +mem-write: 0x800019dc <- 0x8307c793 +mem-write: 0x800019e0 <- 0xcf11423 +mem-write: 0x800019e4 <- 0x470793 +mem-write: 0x800019e8 <- 0xf12a23 +mem-write: 0x800019ec <- 0x72903 +mem-write: 0x800019f0 <- 0x800157b7 +mem-write: 0x800019f4 <- 0xa3c78793 +mem-write: 0x800019f8 <- 0xc8893 +mem-write: 0x800019fc <- 0x2f12a23 +mem-write: 0x80001a00 <- 0xc93 +mem-write: 0x80001a04 <- 0x2a6b93 +mem-write: 0x80001a08 <- 0x200793 +mem-write: 0x80001a0c <- 0x7800493 +mem-write: 0x80001a10 <- 0xc0103a3 +mem-write: 0x80001a14 <- 0xfff00713 +mem-write: 0x80001a18 <- 0x20ed8663 +mem-write: 0x80001a1c <- 0x1996733 +mem-write: 0x80001a20 <- 0xf7fbfa13 +mem-write: 0x80001a24 <- 0x1e071e63 +mem-write: 0x80001a28 <- 0x260d9463 +mem-write: 0x80001a2c <- 0x1c079063 +mem-write: 0x80001a30 <- 0x1bfc93 +mem-write: 0x80001a34 <- 0x1b010b13 +mem-write: 0x80001a38 <- 0x280c9ce3 +mem-write: 0x80001a3c <- 0xc8a93 +mem-write: 0x80001a40 <- 0x1bcd463 +mem-write: 0x80001a44 <- 0xd8a93 +mem-write: 0x80001a48 <- 0xc714783 +mem-write: 0x80001a4c <- 0x12823 +mem-write: 0x80001a50 <- 0x2012423 +mem-write: 0x80001a54 <- 0x2012223 +mem-write: 0x80001a58 <- 0x12e23 +mem-write: 0x80001a5c <- 0xf00790e3 +mem-write: 0x80001a60 <- 0xf58ff06f +mem-write: 0x80001a64 <- 0x44483 +mem-write: 0x80001a68 <- 0x6800793 +mem-write: 0x80001a6c <- 0x42f48ae3 +mem-write: 0x80001a70 <- 0x40a6a13 +mem-write: 0x80001a74 <- 0xec4ff06f +mem-write: 0x80001a78 <- 0x2b00793 +mem-write: 0x80001a7c <- 0x44483 +mem-write: 0x80001a80 <- 0xcf103a3 +mem-write: 0x80001a84 <- 0xeb4ff06f +mem-write: 0x80001a88 <- 0x44483 +mem-write: 0x80001a8c <- 0x80a6a13 +mem-write: 0x80001a90 <- 0xea8ff06f +mem-write: 0x80001a94 <- 0x44483 +mem-write: 0x80001a98 <- 0x140713 +mem-write: 0x80001a9c <- 0x1749463 +mem-write: 0x80001aa0 <- 0x7250106f +mem-write: 0x80001aa4 <- 0xfd048693 +mem-write: 0x80001aa8 <- 0x70413 +mem-write: 0x80001aac <- 0xd93 +mem-write: 0x80001ab0 <- 0xe8dae663 +mem-write: 0x80001ab4 <- 0x44483 +mem-write: 0x80001ab8 <- 0x2d9793 +mem-write: 0x80001abc <- 0x1b787b3 +mem-write: 0x80001ac0 <- 0x179793 +mem-write: 0x80001ac4 <- 0xd78db3 +mem-write: 0x80001ac8 <- 0xfd048693 +mem-write: 0x80001acc <- 0x140413 +mem-write: 0x80001ad0 <- 0xfedaf2e3 +mem-write: 0x80001ad4 <- 0xe68ff06f +mem-write: 0x80001ad8 <- 0x1412783 +mem-write: 0x80001adc <- 0x44483 +mem-write: 0x80001ae0 <- 0x7a983 +mem-write: 0x80001ae4 <- 0x478793 +mem-write: 0x80001ae8 <- 0xf12a23 +mem-write: 0x80001aec <- 0xe409d663 +mem-write: 0x80001af0 <- 0x413009b3 +mem-write: 0x80001af4 <- 0x4a6a13 +mem-write: 0x80001af8 <- 0xe40ff06f +mem-write: 0x80001afc <- 0x44483 +mem-write: 0x80001b00 <- 0x1a6a13 +mem-write: 0x80001b04 <- 0xe34ff06f +mem-write: 0x80001b08 <- 0xc714783 +mem-write: 0x80001b0c <- 0x44483 +mem-write: 0x80001b10 <- 0xe2079463 +mem-write: 0x80001b14 <- 0x2000793 +mem-write: 0x80001b18 <- 0xcf103a3 +mem-write: 0x80001b1c <- 0xe1cff06f +mem-write: 0x80001b20 <- 0xc8893 +mem-write: 0x80001b24 <- 0x10a6a13 +mem-write: 0x80001b28 <- 0x20a7793 +mem-write: 0x80001b2c <- 0xc078ee3 +mem-write: 0x80001b30 <- 0x1412783 +mem-write: 0x80001b34 <- 0x778b13 +mem-write: 0x80001b38 <- 0xff8b7b13 +mem-write: 0x80001b3c <- 0xb2903 +mem-write: 0x80001b40 <- 0x4b2c83 +mem-write: 0x80001b44 <- 0x8b0793 +mem-write: 0x80001b48 <- 0xf12a23 +mem-write: 0x80001b4c <- 0xbffa7b93 +mem-write: 0x80001b50 <- 0x793 +mem-write: 0x80001b54 <- 0xebdff06f +mem-write: 0x80001b58 <- 0xc8893 +mem-write: 0x80001b5c <- 0x10a6b93 +mem-write: 0x80001b60 <- 0x20bf793 +mem-write: 0x80001b64 <- 0xc0788e3 +mem-write: 0x80001b68 <- 0x1412783 +mem-write: 0x80001b6c <- 0x778b13 +mem-write: 0x80001b70 <- 0xff8b7b13 +mem-write: 0x80001b74 <- 0x8b0793 +mem-write: 0x80001b78 <- 0xf12a23 +mem-write: 0x80001b7c <- 0xb2903 +mem-write: 0x80001b80 <- 0x4b2c83 +mem-write: 0x80001b84 <- 0x100793 +mem-write: 0x80001b88 <- 0xe89ff06f +mem-write: 0x80001b8c <- 0x44483 +mem-write: 0x80001b90 <- 0x8a6a13 +mem-write: 0x80001b94 <- 0xda4ff06f +mem-write: 0x80001b98 <- 0xc8893 +mem-write: 0x80001b9c <- 0x10a6a13 +mem-write: 0x80001ba0 <- 0x20a7793 +mem-write: 0x80001ba4 <- 0xc0780e3 +mem-write: 0x80001ba8 <- 0x1412783 +mem-write: 0x80001bac <- 0x778b13 +mem-write: 0x80001bb0 <- 0xff8b7b13 +mem-write: 0x80001bb4 <- 0x4b2783 +mem-write: 0x80001bb8 <- 0xb2903 +mem-write: 0x80001bbc <- 0x8b0713 +mem-write: 0x80001bc0 <- 0xe12a23 +mem-write: 0x80001bc4 <- 0x78c93 +mem-write: 0x80001bc8 <- 0xc07c6e3 +mem-write: 0x80001bcc <- 0xfff00793 +mem-write: 0x80001bd0 <- 0xa0b93 +mem-write: 0x80001bd4 <- 0x2fd8463 +mem-write: 0x80001bd8 <- 0x19967b3 +mem-write: 0x80001bdc <- 0xf7fa7b93 +mem-write: 0x80001be0 <- 0x79e63 +mem-write: 0x80001be4 <- 0x20d9263 +mem-write: 0x80001be8 <- 0xb8a13 +mem-write: 0x80001bec <- 0xd93 +mem-write: 0x80001bf0 <- 0xc93 +mem-write: 0x80001bf4 <- 0x1b010b13 +mem-write: 0x80001bf8 <- 0xe45ff06f +mem-write: 0x80001bfc <- 0x3a0c92e3 +VXDRV: upload 1023 bytes to 0x80001c00 +mem-write: 0x80001c00 <- 0x900793 +mem-write: 0x80001c04 <- 0x3927eee3 +mem-write: 0x80001c08 <- 0x3090913 +mem-write: 0x80001c0c <- 0x1b2107a3 +mem-write: 0x80001c10 <- 0xb8a13 +mem-write: 0x80001c14 <- 0x100c93 +mem-write: 0x80001c18 <- 0x1af10b13 +mem-write: 0x80001c1c <- 0xe21ff06f +mem-write: 0x80001c20 <- 0xa0b93 +mem-write: 0x80001c24 <- 0x100713 +mem-write: 0x80001c28 <- 0xfce78ae3 +mem-write: 0x80001c2c <- 0x200713 +mem-write: 0x80001c30 <- 0x6e78c63 +mem-write: 0x80001c34 <- 0x1b010b13 +mem-write: 0x80001c38 <- 0x1dc9713 +mem-write: 0x80001c3c <- 0x797793 +mem-write: 0x80001c40 <- 0x395913 +mem-write: 0x80001c44 <- 0x3078793 +mem-write: 0x80001c48 <- 0x1276933 +mem-write: 0x80001c4c <- 0x3cdc93 +mem-write: 0x80001c50 <- 0xfefb0fa3 +mem-write: 0x80001c54 <- 0x1996733 +mem-write: 0x80001c58 <- 0xb0613 +mem-write: 0x80001c5c <- 0xfffb0b13 +mem-write: 0x80001c60 <- 0xfc071ce3 +mem-write: 0x80001c64 <- 0x1bf693 +mem-write: 0x80001c68 <- 0x6068a63 +mem-write: 0x80001c6c <- 0x3000693 +mem-write: 0x80001c70 <- 0x6d78663 +mem-write: 0x80001c74 <- 0xffe60613 +mem-write: 0x80001c78 <- 0x1b010793 +mem-write: 0x80001c7c <- 0xfedb0fa3 +mem-write: 0x80001c80 <- 0x40c78cb3 +mem-write: 0x80001c84 <- 0xb8a13 +mem-write: 0x80001c88 <- 0x60b13 +mem-write: 0x80001c8c <- 0xdb1ff06f +mem-write: 0x80001c90 <- 0x100713 +mem-write: 0x80001c94 <- 0xe79463 +mem-write: 0x80001c98 <- 0x14d0106f +mem-write: 0x80001c9c <- 0x200713 +mem-write: 0x80001ca0 <- 0xa0b93 +mem-write: 0x80001ca4 <- 0xf8e798e3 +mem-write: 0x80001ca8 <- 0x3412683 +mem-write: 0x80001cac <- 0x1b010b13 +mem-write: 0x80001cb0 <- 0xf97793 +mem-write: 0x80001cb4 <- 0xf687b3 +mem-write: 0x80001cb8 <- 0x7c703 +mem-write: 0x80001cbc <- 0x495913 +mem-write: 0x80001cc0 <- 0x1cc9793 +mem-write: 0x80001cc4 <- 0x127e933 +mem-write: 0x80001cc8 <- 0x4cdc93 +mem-write: 0x80001ccc <- 0xfeeb0fa3 +mem-write: 0x80001cd0 <- 0x19967b3 +mem-write: 0x80001cd4 <- 0xfffb0b13 +mem-write: 0x80001cd8 <- 0xfc079ce3 +mem-write: 0x80001cdc <- 0x1b010793 +mem-write: 0x80001ce0 <- 0x41678cb3 +mem-write: 0x80001ce4 <- 0xb8a13 +mem-write: 0x80001ce8 <- 0xd55ff06f +mem-write: 0x80001cec <- 0x6500693 +mem-write: 0x80001cf0 <- 0x2c96dc63 +mem-write: 0x80001cf4 <- 0xf012683 +mem-write: 0x80001cf8 <- 0xa010593 +mem-write: 0x80001cfc <- 0xb010513 +mem-write: 0x80001d00 <- 0xad12823 +mem-write: 0x80001d04 <- 0xf412683 +mem-write: 0x80001d08 <- 0x5112223 +mem-write: 0x80001d0c <- 0x4f12023 +mem-write: 0x80001d10 <- 0xad12a23 +mem-write: 0x80001d14 <- 0xf812683 +mem-write: 0x80001d18 <- 0xa012023 +mem-write: 0x80001d1c <- 0xa012223 +mem-write: 0x80001d20 <- 0xad12c23 +mem-write: 0x80001d24 <- 0xfc12683 +mem-write: 0x80001d28 <- 0xa012423 +mem-write: 0x80001d2c <- 0xa012623 +mem-write: 0x80001d30 <- 0xad12e23 +mem-write: 0x80001d34 <- 0x39d0f0ef +mem-write: 0x80001d38 <- 0x4012783 +mem-write: 0x80001d3c <- 0x4412883 +mem-write: 0x80001d40 <- 0x4a051863 +mem-write: 0x80001d44 <- 0xe812703 +mem-write: 0x80001d48 <- 0x800156b7 +mem-write: 0x80001d4c <- 0x98068693 +mem-write: 0x80001d50 <- 0xd8a023 +mem-write: 0x80001d54 <- 0x178793 +mem-write: 0x80001d58 <- 0x100693 +mem-write: 0x80001d5c <- 0x170713 +mem-write: 0x80001d60 <- 0xd8a223 +mem-write: 0x80001d64 <- 0xef12623 +mem-write: 0x80001d68 <- 0xee12423 +mem-write: 0x80001d6c <- 0x700693 +mem-write: 0x80001d70 <- 0x888893 +mem-write: 0x80001d74 <- 0x3ae6c6e3 +mem-write: 0x80001d78 <- 0xcc12703 +mem-write: 0x80001d7c <- 0x2012683 +mem-write: 0x80001d80 <- 0x72d75c63 +mem-write: 0x80001d84 <- 0x3012703 +mem-write: 0x80001d88 <- 0x2c12683 +mem-write: 0x80001d8c <- 0x888893 +mem-write: 0x80001d90 <- 0xfee8ac23 +mem-write: 0x80001d94 <- 0xe812703 +mem-write: 0x80001d98 <- 0xd787b3 +mem-write: 0x80001d9c <- 0xfed8ae23 +mem-write: 0x80001da0 <- 0x170713 +mem-write: 0x80001da4 <- 0xef12623 +mem-write: 0x80001da8 <- 0xee12423 +mem-write: 0x80001dac <- 0x700693 +mem-write: 0x80001db0 <- 0xce6c0e3 +mem-write: 0x80001db4 <- 0x2012703 +mem-write: 0x80001db8 <- 0xfff70493 +mem-write: 0x80001dbc <- 0xcc905663 +mem-write: 0x80001dc0 <- 0x1000693 +mem-write: 0x80001dc4 <- 0xe812703 +mem-write: 0x80001dc8 <- 0x3696dce3 +mem-write: 0x80001dcc <- 0x1000913 +mem-write: 0x80001dd0 <- 0x700c93 +mem-write: 0x80001dd4 <- 0xc0006f +mem-write: 0x80001dd8 <- 0xff048493 +mem-write: 0x80001ddc <- 0x369952e3 +mem-write: 0x80001de0 <- 0x812683 +mem-write: 0x80001de4 <- 0x1078793 +mem-write: 0x80001de8 <- 0x170713 +mem-write: 0x80001dec <- 0xd8a023 +mem-write: 0x80001df0 <- 0x128a223 +mem-write: 0x80001df4 <- 0xef12623 +mem-write: 0x80001df8 <- 0xee12423 +mem-write: 0x80001dfc <- 0x888893 +mem-write: 0x80001e00 <- 0xfcecdce3 +mem-write: 0x80001e04 <- 0xe410613 +mem-write: 0x80001e08 <- 0xc0593 +mem-write: 0x80001e0c <- 0xd0513 +mem-write: 0x80001e10 <- 0x3140a0ef +mem-write: 0x80001e14 <- 0x18051e63 +mem-write: 0x80001e18 <- 0xec12783 +mem-write: 0x80001e1c <- 0xe812703 +mem-write: 0x80001e20 <- 0x10c10893 +mem-write: 0x80001e24 <- 0xfb5ff06f +mem-write: 0x80001e28 <- 0x41598933 +mem-write: 0x80001e2c <- 0xc3205263 +mem-write: 0x80001e30 <- 0x1000613 +mem-write: 0x80001e34 <- 0xe812683 +mem-write: 0x80001e38 <- 0x7265463 +mem-write: 0x80001e3c <- 0x1000e13 +mem-write: 0x80001e40 <- 0x700b93 +mem-write: 0x80001e44 <- 0xc0006f +mem-write: 0x80001e48 <- 0xff090913 +mem-write: 0x80001e4c <- 0x52e5a63 +mem-write: 0x80001e50 <- 0x812703 +mem-write: 0x80001e54 <- 0x1078793 +mem-write: 0x80001e58 <- 0x168693 +mem-write: 0x80001e5c <- 0xe8a023 +mem-write: 0x80001e60 <- 0x1c8a223 +mem-write: 0x80001e64 <- 0xef12623 +mem-write: 0x80001e68 <- 0xed12423 +mem-write: 0x80001e6c <- 0x888893 +mem-write: 0x80001e70 <- 0xfcdbdce3 +mem-write: 0x80001e74 <- 0xe410613 +mem-write: 0x80001e78 <- 0xc0593 +mem-write: 0x80001e7c <- 0xd0513 +mem-write: 0x80001e80 <- 0x2a40a0ef +mem-write: 0x80001e84 <- 0x12051663 +mem-write: 0x80001e88 <- 0x1000e13 +mem-write: 0x80001e8c <- 0xff090913 +mem-write: 0x80001e90 <- 0xec12783 +mem-write: 0x80001e94 <- 0xe812683 +mem-write: 0x80001e98 <- 0x10c10893 +mem-write: 0x80001e9c <- 0xfb2e4ae3 +mem-write: 0x80001ea0 <- 0x812703 +mem-write: 0x80001ea4 <- 0x12787b3 +mem-write: 0x80001ea8 <- 0x168693 +mem-write: 0x80001eac <- 0xe8a023 +mem-write: 0x80001eb0 <- 0x128a223 +mem-write: 0x80001eb4 <- 0xef12623 +mem-write: 0x80001eb8 <- 0xed12423 +mem-write: 0x80001ebc <- 0x700613 +mem-write: 0x80001ec0 <- 0x888893 +mem-write: 0x80001ec4 <- 0xb8d65663 +mem-write: 0x80001ec8 <- 0xe410613 +mem-write: 0x80001ecc <- 0xc0593 +mem-write: 0x80001ed0 <- 0xd0513 +mem-write: 0x80001ed4 <- 0x2500a0ef +mem-write: 0x80001ed8 <- 0xc051c63 +mem-write: 0x80001edc <- 0xec12783 +mem-write: 0x80001ee0 <- 0x10c10893 +mem-write: 0x80001ee4 <- 0xb6cff06f +mem-write: 0x80001ee8 <- 0x1000613 +mem-write: 0x80001eec <- 0xe812683 +mem-write: 0x80001ef0 <- 0x7b65263 +mem-write: 0x80001ef4 <- 0x1000b93 +mem-write: 0x80001ef8 <- 0x700913 +mem-write: 0x80001efc <- 0xc0006f +mem-write: 0x80001f00 <- 0xff0d8d93 +mem-write: 0x80001f04 <- 0x5bbd863 +mem-write: 0x80001f08 <- 0x812703 +mem-write: 0x80001f0c <- 0x1078793 +mem-write: 0x80001f10 <- 0x168693 +mem-write: 0x80001f14 <- 0xe8a023 +mem-write: 0x80001f18 <- 0x178a223 +mem-write: 0x80001f1c <- 0xef12623 +mem-write: 0x80001f20 <- 0xed12423 +mem-write: 0x80001f24 <- 0x888893 +mem-write: 0x80001f28 <- 0xfcd95ce3 +mem-write: 0x80001f2c <- 0xe410613 +mem-write: 0x80001f30 <- 0xc0593 +mem-write: 0x80001f34 <- 0xd0513 +mem-write: 0x80001f38 <- 0x1ec0a0ef +mem-write: 0x80001f3c <- 0x6051a63 +mem-write: 0x80001f40 <- 0xff0d8d93 +mem-write: 0x80001f44 <- 0xec12783 +mem-write: 0x80001f48 <- 0xe812683 +mem-write: 0x80001f4c <- 0x10c10893 +mem-write: 0x80001f50 <- 0xfbbbcce3 +mem-write: 0x80001f54 <- 0x812703 +mem-write: 0x80001f58 <- 0x1b787b3 +mem-write: 0x80001f5c <- 0x168693 +mem-write: 0x80001f60 <- 0xe8a023 +mem-write: 0x80001f64 <- 0x1b8a223 +mem-write: 0x80001f68 <- 0xef12623 +mem-write: 0x80001f6c <- 0xed12423 +mem-write: 0x80001f70 <- 0x700613 +mem-write: 0x80001f74 <- 0x888893 +mem-write: 0x80001f78 <- 0xaed65063 +mem-write: 0x80001f7c <- 0xe410613 +mem-write: 0x80001f80 <- 0xc0593 +mem-write: 0x80001f84 <- 0xd0513 +mem-write: 0x80001f88 <- 0x19c0a0ef +mem-write: 0x80001f8c <- 0x2051263 +mem-write: 0x80001f90 <- 0xec12783 +mem-write: 0x80001f94 <- 0x10c10893 +mem-write: 0x80001f98 <- 0xac0ff06f +mem-write: 0x80001f9c <- 0xe410613 +mem-write: 0x80001fa0 <- 0xc0593 +mem-write: 0x80001fa4 <- 0xd0513 +mem-write: 0x80001fa8 <- 0x17c0a0ef +mem-write: 0x80001fac <- 0xb0050263 +mem-write: 0x80001fb0 <- 0x1012b83 +mem-write: 0x80001fb4 <- 0xb20b8863 +mem-write: 0x80001fb8 <- 0xb8593 +mem-write: 0x80001fbc <- 0xd0513 +mem-write: 0x80001fc0 <- 0x5a4020ef +mem-write: 0x80001fc4 <- 0xb20ff06f +mem-write: 0x80001fc8 <- 0xe812683 +mem-write: 0x80001fcc <- 0x178c93 +mem-write: 0x80001fd0 <- 0x2012783 +mem-write: 0x80001fd4 <- 0x100613 +mem-write: 0x80001fd8 <- 0x168a023 +mem-write: 0x80001fdc <- 0x168493 +mem-write: 0x80001fe0 <- 0x888913 +mem-write: 0x80001fe4 <- 0x38f65663 +mem-write: 0x80001fe8 <- 0x100793 +mem-write: 0x80001fec <- 0xf8a223 +mem-write: 0x80001ff0 <- 0xf912623 +mem-write: 0x80001ff4 <- 0xe912423 +mem-write: 0x80001ff8 <- 0x700793 +mem-write: 0x80001ffc <- 0x3a97ce63 +VXDRV: upload 1024 bytes to 0x80001fff +mem-write: 0x80001fff <- 0xc1278374 +mem-write: 0x80002003 <- 0x1270302 +mem-write: 0x80002007 <- 0x14849303 +mem-write: 0x8000200b <- 0xfc8cb300 +mem-write: 0x8000200f <- 0xf9222300 +mem-write: 0x80002013 <- 0xe9202300 +mem-write: 0x80002017 <- 0x91262300 +mem-write: 0x8000201b <- 0x9124230f +mem-write: 0x8000201f <- 0x7007930e +mem-write: 0x80002023 <- 0x89091300 +mem-write: 0x80002027 <- 0x97ca6300 +mem-write: 0x8000202b <- 0x1278374 +mem-write: 0x8000202f <- 0x1486130f +mem-write: 0x80002033 <- 0x1059300 +mem-write: 0x80002037 <- 0xf128230a +mem-write: 0x8000203b <- 0x4127830a +mem-write: 0x8000203f <- 0x105130f +mem-write: 0x80002043 <- 0xc12e230b +mem-write: 0x80002047 <- 0xf12a2300 +mem-write: 0x8000204b <- 0x8127830a +mem-write: 0x8000204f <- 0x120230f +mem-write: 0x80002053 <- 0x122230a +mem-write: 0x80002057 <- 0xf12c230a +mem-write: 0x8000205b <- 0xc127830a +mem-write: 0x8000205f <- 0x124230f +mem-write: 0x80002063 <- 0x126230a +mem-write: 0x80002067 <- 0xf12e230a +mem-write: 0x8000206b <- 0x50f0ef0a +mem-write: 0x8000206f <- 0xc1260306 +mem-write: 0x80002073 <- 0x1278301 +mem-write: 0x80002077 <- 0x89089302 +mem-write: 0x8000207b <- 0x6069300 +mem-write: 0x8000207f <- 0xf78d9300 +mem-write: 0x80002083 <- 0x50a63ff +mem-write: 0x80002087 <- 0x1b071330 +mem-write: 0x8000208b <- 0xbc8cb300 +mem-write: 0x8000208f <- 0xe9202301 +mem-write: 0x80002093 <- 0xb9222300 +mem-write: 0x80002097 <- 0x91262301 +mem-write: 0x8000209b <- 0xc124230f +mem-write: 0x8000209f <- 0x7007930e +mem-write: 0x800020a3 <- 0xc7cc6300 +mem-write: 0x800020a7 <- 0x9079350 +mem-write: 0x800020ab <- 0x24869301 +mem-write: 0x800020af <- 0x8891300 +mem-write: 0x800020b3 <- 0x7889300 +mem-write: 0x800020b7 <- 0x81260300 +mem-write: 0x800020bb <- 0x41071303 +mem-write: 0x800020bf <- 0xe920230d +mem-write: 0x800020c3 <- 0x9607b300 +mem-write: 0x800020c7 <- 0xc9222301 +mem-write: 0x800020cb <- 0xf1262300 +mem-write: 0x800020cf <- 0xd124230e +mem-write: 0x800020d3 <- 0x7007130e +mem-write: 0x800020d7 <- 0xd7586300 +mem-write: 0x800020db <- 0x4ff06f9a +mem-write: 0x800020df <- 0x15737ef +mem-write: 0x800020e3 <- 0x61380 +mem-write: 0x800020e7 <- 0x81268301 +mem-write: 0x800020eb <- 0x870e930e +mem-write: 0x800020ef <- 0x65c63bd +mem-write: 0x800020f3 <- 0x81202309 +mem-write: 0x800020f7 <- 0x91222304 +mem-write: 0x800020fb <- 0xd041304 +mem-write: 0x800020ff <- 0xc049300 +mem-write: 0x80002103 <- 0xe1300 +mem-write: 0x80002107 <- 0x70029301 +mem-write: 0x8000210b <- 0x80c1300 +mem-write: 0x8000210f <- 0xe8d1300 +mem-write: 0x80002113 <- 0xc0006f00 +mem-write: 0x80002117 <- 0xc0c1300 +mem-write: 0x8000211b <- 0x8e5a63ff +mem-write: 0x8000211f <- 0x7879305 +mem-write: 0x80002123 <- 0x16869301 +mem-write: 0x80002127 <- 0xa8a02300 +mem-write: 0x8000212b <- 0xc8a22301 +mem-write: 0x8000212f <- 0xf1262301 +mem-write: 0x80002133 <- 0xd124230e +mem-write: 0x80002137 <- 0x8888930e +mem-write: 0x8000213b <- 0xd2dee300 +mem-write: 0x8000213f <- 0x410613fc +mem-write: 0x80002143 <- 0x485930e +mem-write: 0x80002147 <- 0x4051300 +mem-write: 0x8000214b <- 0x9090ef00 +mem-write: 0x8000214f <- 0x512637d +mem-write: 0x80002153 <- 0xe137a +mem-write: 0x80002157 <- 0xc0c1301 +mem-write: 0x8000215b <- 0xc12783ff +mem-write: 0x8000215f <- 0x8126830e +mem-write: 0x80002163 <- 0xc108930e +mem-write: 0x80002167 <- 0x70029310 +mem-write: 0x8000216b <- 0x8e4ae300 +mem-write: 0x8000216f <- 0xc0813fb +mem-write: 0x80002173 <- 0xd0e9300 +mem-write: 0x80002177 <- 0x48c1300 +mem-write: 0x8000217b <- 0x40d1300 +mem-write: 0x8000217f <- 0x41248300 +mem-write: 0x80002183 <- 0x1240304 +mem-write: 0x80002187 <- 0x787b304 +mem-write: 0x8000218b <- 0x16869301 +mem-write: 0x8000218f <- 0xd8a02300 +mem-write: 0x80002193 <- 0x8a22301 +mem-write: 0x80002197 <- 0xf1262301 +mem-write: 0x8000219b <- 0xd124230e +mem-write: 0x8000219f <- 0x7006130e +mem-write: 0x800021a3 <- 0x88889300 +mem-write: 0x800021a7 <- 0xd6446300 +mem-write: 0x800021ab <- 0xcff06f00 +mem-write: 0x800021af <- 0x41061382 +mem-write: 0x800021b3 <- 0xc05930e +mem-write: 0x800021b7 <- 0xd051300 +mem-write: 0x800021bb <- 0x9090ef00 +mem-write: 0x800021bf <- 0x518e376 +mem-write: 0x800021c3 <- 0xc12783de +mem-write: 0x800021c7 <- 0xc108930e +mem-write: 0x800021cb <- 0xcff06f10 +mem-write: 0x800021cf <- 0x41061380 +mem-write: 0x800021d3 <- 0xc05930e +mem-write: 0x800021d7 <- 0xd051300 +mem-write: 0x800021db <- 0x9090ef00 +mem-write: 0x800021df <- 0x518e374 +mem-write: 0x800021e3 <- 0xc12783dc +mem-write: 0x800021e7 <- 0xc108930e +mem-write: 0x800021eb <- 0xcff06f10 +mem-write: 0x800021ef <- 0xc1258385 +mem-write: 0x800021f3 <- 0xb05c630c +mem-write: 0x800021f7 <- 0xc1270366 +mem-write: 0x800021fb <- 0x1268301 +mem-write: 0x800021ff <- 0x7049302 +mem-write: 0x80002203 <- 0xe6c26300 +mem-write: 0x80002207 <- 0x90566338 +mem-write: 0x8000220b <- 0x81268302 +mem-write: 0x8000220f <- 0x9787b30e +mem-write: 0x80002213 <- 0x68a02300 +mem-write: 0x80002217 <- 0x16869301 +mem-write: 0x8000221b <- 0x98a22300 +mem-write: 0x8000221f <- 0xf1262300 +mem-write: 0x80002223 <- 0xd124230e +mem-write: 0x80002227 <- 0x7006130e +mem-write: 0x8000222b <- 0x88889300 +mem-write: 0x8000222f <- 0xd642e300 +mem-write: 0x80002233 <- 0xf4c69332 +mem-write: 0x80002237 <- 0xc12703ff +mem-write: 0x8000223b <- 0xf6d69301 +mem-write: 0x8000223f <- 0xd4f4b341 +mem-write: 0x80002243 <- 0x9704b300 +mem-write: 0x80002247 <- 0x90446340 +mem-write: 0x8000224b <- 0xc1270348 +mem-write: 0x8000224f <- 0xa769301 +mem-write: 0x80002253 <- 0xeb0db340 +mem-write: 0x80002257 <- 0x698e300 +mem-write: 0x8000225b <- 0xc124830c +mem-write: 0x8000225f <- 0x127030c +mem-write: 0x80002263 <- 0xe4c66302 +mem-write: 0x80002267 <- 0x1a769300 +mem-write: 0x8000226b <- 0x688e300 +mem-write: 0x8000226f <- 0x1268330 +mem-write: 0x80002273 <- 0xc1270303 +mem-write: 0x80002277 <- 0x70061302 +mem-write: 0x8000227b <- 0xd8a02300 +mem-write: 0x8000227f <- 0x81268300 +mem-write: 0x80002283 <- 0xe787b30e +mem-write: 0x80002287 <- 0xe8a22300 +mem-write: 0x8000228b <- 0x16869300 +mem-write: 0x8000228f <- 0xf1262300 +mem-write: 0x80002293 <- 0xd124230e +mem-write: 0x80002297 <- 0x8888930e +mem-write: 0x8000229b <- 0xd6546300 +mem-write: 0x8000229f <- 0x80106f00 +mem-write: 0x800022a3 <- 0x1268317 +mem-write: 0x800022a7 <- 0xdb073302 +mem-write: 0x800022ab <- 0x9684b300 +mem-write: 0x800022af <- 0xb7073340 +mem-write: 0x800022b3 <- 0x4891341 +mem-write: 0x800022b7 <- 0x97546300 +mem-write: 0x800022bb <- 0x7091300 +mem-write: 0x800022bf <- 0x20586300 +mem-write: 0x800022c3 <- 0x81270303 +mem-write: 0x800022c7 <- 0x2787b30e +mem-write: 0x800022cb <- 0xb8a02301 +mem-write: 0x800022cf <- 0x17071301 +mem-write: 0x800022d3 <- 0x28a22300 +mem-write: 0x800022d7 <- 0xf1262301 +mem-write: 0x800022db <- 0xe124230e +mem-write: 0x800022df <- 0x7006930e +mem-write: 0x800022e3 <- 0x88889300 +mem-write: 0x800022e7 <- 0xe6d46300 +mem-write: 0x800022eb <- 0x80106f00 +mem-write: 0x800022ef <- 0xf947131c +mem-write: 0x800022f3 <- 0xf75713ff +mem-write: 0x800022f7 <- 0xe9773341 +mem-write: 0x800022fb <- 0xe484b300 +mem-write: 0x800022ff <- 0x90446340 +mem-write: 0x80002303 <- 0x5fe06f00 +mem-write: 0x80002307 <- 0x693f8 +mem-write: 0x8000230b <- 0x81270301 +mem-write: 0x8000230f <- 0x96d8630e +mem-write: 0x80002313 <- 0x91362 +mem-write: 0x80002317 <- 0x700c9301 +mem-write: 0x8000231b <- 0xc0006f00 +mem-write: 0x8000231f <- 0x4849300 +mem-write: 0x80002323 <- 0x995e63ff +mem-write: 0x80002327 <- 0x81268360 +mem-write: 0x8000232b <- 0x7879300 +mem-write: 0x8000232f <- 0x17071301 +mem-write: 0x80002333 <- 0xd8a02300 +mem-write: 0x80002337 <- 0x28a22300 +mem-write: 0x8000233b <- 0xf1262301 +mem-write: 0x8000233f <- 0xe124230e +mem-write: 0x80002343 <- 0x8888930e +mem-write: 0x80002347 <- 0xecdce300 +mem-write: 0x8000234b <- 0x410613fc +mem-write: 0x8000234f <- 0xc05930e +mem-write: 0x80002353 <- 0xd051300 +mem-write: 0x80002357 <- 0xd090ef00 +mem-write: 0x8000235b <- 0x51ae35c +mem-write: 0x8000235f <- 0xc12783c4 +mem-write: 0x80002363 <- 0x8127030e +mem-write: 0x80002367 <- 0xc108930e +mem-write: 0x8000236b <- 0x5ff06f10 +mem-write: 0x8000236f <- 0x1a7793fb +mem-write: 0x80002373 <- 0x79ae300 +mem-write: 0x80002377 <- 0xc8a223c6 +mem-write: 0x8000237b <- 0x91262300 +mem-write: 0x8000237f <- 0x9124230f +mem-write: 0x80002383 <- 0x7007930e +mem-write: 0x80002387 <- 0x97ca6300 +mem-write: 0x8000238b <- 0x26869322 +mem-write: 0x8000238f <- 0x8889300 +mem-write: 0x80002393 <- 0x5ff06f01 +mem-write: 0x80002397 <- 0xb050e3d2 +mem-write: 0x8000239b <- 0x713d3 +mem-write: 0x8000239f <- 0xb7446301 +mem-write: 0x800023a3 <- 0x80106f01 +mem-write: 0x800023a7 <- 0x700b1361 +mem-write: 0x800023ab <- 0x6049300 +mem-write: 0x800023af <- 0x6f00 +mem-write: 0x800023b3 <- 0xd8d9301 +mem-write: 0x800023b7 <- 0xb75e63ff +mem-write: 0x800023bb <- 0x1484931d +mem-write: 0x800023bf <- 0x81278300 +mem-write: 0x800023c3 <- 0xc8c9300 +mem-write: 0x800023c7 <- 0xe9222301 +mem-write: 0x800023cb <- 0xf9202300 +mem-write: 0x800023cf <- 0x91262300 +mem-write: 0x800023d3 <- 0x9124230f +mem-write: 0x800023d7 <- 0x8909130e +mem-write: 0x800023db <- 0x9b5ce300 +mem-write: 0x800023df <- 0x410613fc +mem-write: 0x800023e3 <- 0xc05930e +mem-write: 0x800023e7 <- 0xd051300 +mem-write: 0x800023eb <- 0x9090ef00 +mem-write: 0x800023ef <- 0x510e353 +mem-write: 0x800023f3 <- 0xc12c83bc +mem-write: 0x800023f7 <- 0x8124830e +mem-write: 0x800023fb <- 0xc109130e +VXDRV: upload 1024 bytes to 0x800023ff +mem-write: 0x800023ff <- 0x71310 +mem-write: 0x80002403 <- 0x1ff06f01 +mem-write: 0x80002407 <- 0x412683fb +mem-write: 0x8000240b <- 0xa779301 +mem-write: 0x8000240f <- 0x46871301 +mem-write: 0x80002413 <- 0x7926300 +mem-write: 0x80002417 <- 0xa779316 +mem-write: 0x8000241b <- 0x7846304 +mem-write: 0x8000241f <- 0x41278368 +mem-write: 0x80002423 <- 0xc9301 +mem-write: 0x80002427 <- 0xe12a2300 +mem-write: 0x8000242b <- 0x7d90300 +mem-write: 0x8000242f <- 0xcff06f00 +mem-write: 0x80002433 <- 0x412683f1 +mem-write: 0x80002437 <- 0xbf79301 +mem-write: 0x8000243b <- 0x46871301 +mem-write: 0x8000243f <- 0x79e6300 +mem-write: 0x80002443 <- 0xbf7930c +mem-write: 0x80002447 <- 0x78e6304 +mem-write: 0x8000244b <- 0x41278360 +mem-write: 0x8000244f <- 0xc9301 +mem-write: 0x80002453 <- 0xe12a2300 +mem-write: 0x80002457 <- 0x7d90300 +mem-write: 0x8000245b <- 0x10079300 +mem-write: 0x8000245f <- 0xff06f00 +mem-write: 0x80002463 <- 0x412683db +mem-write: 0x80002467 <- 0xa779301 +mem-write: 0x8000246b <- 0x46871301 +mem-write: 0x8000246f <- 0x79a6300 +mem-write: 0x80002473 <- 0xa77930e +mem-write: 0x80002477 <- 0x7866304 +mem-write: 0x8000247b <- 0x41278360 +mem-write: 0x8000247f <- 0xe12a2301 +mem-write: 0x80002483 <- 0x7990300 +mem-write: 0x80002487 <- 0xf95c9300 +mem-write: 0x8000248b <- 0xc879341 +mem-write: 0x8000248f <- 0x7de6300 +mem-write: 0x80002493 <- 0x2037b3f2 +mem-write: 0x80002497 <- 0x900cb301 +mem-write: 0x8000249b <- 0xfc8cb341 +mem-write: 0x8000249f <- 0xd0079340 +mem-write: 0x800024a3 <- 0xf103a302 +mem-write: 0x800024a7 <- 0x2009330c +mem-write: 0x800024ab <- 0xa0b9341 +mem-write: 0x800024af <- 0x10079300 +mem-write: 0x800024b3 <- 0xff06f00 +mem-write: 0x800024b7 <- 0x1a7713d6 +mem-write: 0x800024bb <- 0x7146300 +mem-write: 0x800024bf <- 0x9fe06f00 +mem-write: 0x800024c3 <- 0x1ff06fdc +mem-write: 0x800024c7 <- 0xc88938c +mem-write: 0x800024cb <- 0x4ff06f00 +mem-write: 0x800024cf <- 0x793ed +mem-write: 0x800024d3 <- 0xf107a303 +mem-write: 0x800024d7 <- 0xf10b131a +mem-write: 0x800024db <- 0xff06f1a +mem-write: 0x800024df <- 0xc12783d6 +mem-write: 0x800024e3 <- 0x4448303 +mem-write: 0x800024e7 <- 0x7946300 +mem-write: 0x800024eb <- 0xdfe06f00 +mem-write: 0x800024ef <- 0x7c783c4 +mem-write: 0x800024f3 <- 0x7946300 +mem-write: 0x800024f7 <- 0x1fe06f00 +mem-write: 0x800024fb <- 0xa6a13c4 +mem-write: 0x800024ff <- 0x9fe06f40 +mem-write: 0x80002503 <- 0xc12683c3 +mem-write: 0x80002507 <- 0x40b1300 +mem-write: 0x8000250b <- 0xf6d79300 +mem-write: 0x8000250f <- 0xd7202341 +mem-write: 0x80002513 <- 0xf7222300 +mem-write: 0x80002517 <- 0x9fe06f00 +mem-write: 0x8000251b <- 0x6a903db +mem-write: 0x8000251f <- 0xc9300 +mem-write: 0x80002523 <- 0xe12a2300 +mem-write: 0x80002527 <- 0x10079300 +mem-write: 0x8000252b <- 0x4ff06f00 +mem-write: 0x8000252f <- 0x412703ce +mem-write: 0x80002533 <- 0x7278301 +mem-write: 0x80002537 <- 0x47071300 +mem-write: 0x8000253b <- 0xe12a2300 +mem-write: 0x8000253f <- 0x7a58300 +mem-write: 0x80002543 <- 0x47a60300 +mem-write: 0x80002547 <- 0x87a68300 +mem-write: 0x8000254b <- 0xc7a78300 +mem-write: 0x8000254f <- 0xb1282300 +mem-write: 0x80002553 <- 0xc12a230e +mem-write: 0x80002557 <- 0xd12c230e +mem-write: 0x8000255b <- 0xf12e230e +mem-write: 0x8000255f <- 0x5fe06f0e +mem-write: 0x80002563 <- 0x6a903ef +mem-write: 0x80002567 <- 0xe12a2300 +mem-write: 0x8000256b <- 0xf95c9300 +mem-write: 0x8000256f <- 0xc879341 +mem-write: 0x80002573 <- 0x4ff06f00 +mem-write: 0x80002577 <- 0x6a903e5 +mem-write: 0x8000257b <- 0xc9300 +mem-write: 0x8000257f <- 0xe12a2300 +mem-write: 0x80002583 <- 0x8ff06f00 +mem-write: 0x80002587 <- 0x68493dc +mem-write: 0x8000258b <- 0x9040e300 +mem-write: 0x8000258f <- 0x5ff06fc8 +mem-write: 0x80002593 <- 0x148693ca +mem-write: 0x80002597 <- 0x89071300 +mem-write: 0x8000259b <- 0x81278300 +mem-write: 0x8000259f <- 0xbc8cb300 +mem-write: 0x800025a3 <- 0xb9222301 +mem-write: 0x800025a7 <- 0xf9202301 +mem-write: 0x800025ab <- 0x91262300 +mem-write: 0x800025af <- 0xd124230f +mem-write: 0x800025b3 <- 0x7007930e +mem-write: 0x800025b7 <- 0xd7de6300 +mem-write: 0x800025bb <- 0x41061374 +mem-write: 0x800025bf <- 0xc05930e +mem-write: 0x800025c3 <- 0xd051300 +mem-write: 0x800025c7 <- 0xd090ef00 +mem-write: 0x800025cb <- 0x512e335 +mem-write: 0x800025cf <- 0x8126839e +mem-write: 0x800025d3 <- 0xc12c830e +mem-write: 0x800025d7 <- 0x4108930e +mem-write: 0x800025db <- 0x16869311 +mem-write: 0x800025df <- 0xc1091300 +mem-write: 0x800025e3 <- 0x5ff06f10 +mem-write: 0x800025e7 <- 0xc8893ad +mem-write: 0x800025eb <- 0xa0b9300 +mem-write: 0x800025ef <- 0xff06f00 +mem-write: 0x800025f3 <- 0x157b7d7 +mem-write: 0x800025f7 <- 0xc7879380 +mem-write: 0x800025fb <- 0xc8893a3 +mem-write: 0x800025ff <- 0xf12a2300 +mem-write: 0x80002603 <- 0xa779302 +mem-write: 0x80002607 <- 0x7886302 +mem-write: 0x8000260b <- 0x41278312 +mem-write: 0x8000260f <- 0x778b1301 +mem-write: 0x80002613 <- 0x8b7b1300 +mem-write: 0x80002617 <- 0xb2903ff +mem-write: 0x8000261b <- 0x4b2c8300 +mem-write: 0x8000261f <- 0x8b079300 +mem-write: 0x80002623 <- 0xf12a2300 +mem-write: 0x80002627 <- 0x1a779300 +mem-write: 0x8000262b <- 0x78e6300 +mem-write: 0x8000262f <- 0x9967b300 +mem-write: 0x80002633 <- 0x78a6301 +mem-write: 0x80002637 <- 0x79300 +mem-write: 0x8000263b <- 0xf1042303 +mem-write: 0x8000263f <- 0x9104a30c +mem-write: 0x80002643 <- 0x2a6a130c +mem-write: 0x80002647 <- 0xfa7b9300 +mem-write: 0x8000264b <- 0x200793bf +mem-write: 0x8000264f <- 0xff06f00 +mem-write: 0x80002653 <- 0x157b7bc +mem-write: 0x80002657 <- 0x7879380 +mem-write: 0x8000265b <- 0xc8893a5 +mem-write: 0x8000265f <- 0xf12a2300 +mem-write: 0x80002663 <- 0x1ff06f02 +mem-write: 0x80002667 <- 0xc8893fa +mem-write: 0x8000266b <- 0xcff06f00 +mem-write: 0x8000266f <- 0x410613cb +mem-write: 0x80002673 <- 0xc05930e +mem-write: 0x80002677 <- 0xd051300 +mem-write: 0x8000267b <- 0x9090ef00 +mem-write: 0x8000267f <- 0x518e32a +mem-write: 0x80002683 <- 0xc1278392 +mem-write: 0x80002687 <- 0xc108930e +mem-write: 0x8000268b <- 0x8ff06f10 +mem-write: 0x8000268f <- 0x144483f2 +mem-write: 0x80002693 <- 0xa6a1300 +mem-write: 0x80002697 <- 0x14041302 +mem-write: 0x8000269b <- 0xdfe06f00 +mem-write: 0x8000269f <- 0x144483a9 +mem-write: 0x800026a3 <- 0xa6a1300 +mem-write: 0x800026a7 <- 0x14041320 +mem-write: 0x800026ab <- 0xdfe06f00 +mem-write: 0x800026af <- 0x600793a8 +mem-write: 0x800026b3 <- 0xd8c9300 +mem-write: 0x800026b7 <- 0xb7ee6300 +mem-write: 0x800026bb <- 0x157376b +mem-write: 0x800026bf <- 0xc8a9380 +mem-write: 0x800026c3 <- 0x212a2300 +mem-write: 0x800026c7 <- 0x470b1301 +mem-write: 0x800026cb <- 0x9fe06fa6 +mem-write: 0x800026cf <- 0x613ad +mem-write: 0x800026d3 <- 0x81268301 +mem-write: 0x800026d7 <- 0x9654630e +mem-write: 0x800026db <- 0xc9340 +mem-write: 0x800026df <- 0x700d9301 +mem-write: 0x800026e3 <- 0xc0006f00 +mem-write: 0x800026e7 <- 0x4849300 +mem-write: 0x800026eb <- 0x9cda63ff +mem-write: 0x800026ef <- 0x8127033e +mem-write: 0x800026f3 <- 0x7879300 +mem-write: 0x800026f7 <- 0x16869301 +mem-write: 0x800026fb <- 0xe8a02300 +mem-write: 0x800026ff <- 0x98a22300 +mem-write: 0x80002703 <- 0xf1262301 +mem-write: 0x80002707 <- 0xd124230e +mem-write: 0x8000270b <- 0x8888930e +mem-write: 0x8000270f <- 0xdddce300 +mem-write: 0x80002713 <- 0x410613fc +mem-write: 0x80002717 <- 0xc05930e +mem-write: 0x8000271b <- 0xd051300 +mem-write: 0x8000271f <- 0x5090ef00 +mem-write: 0x80002723 <- 0x516e320 +mem-write: 0x80002727 <- 0xc1278388 +mem-write: 0x8000272b <- 0x8126830e +mem-write: 0x8000272f <- 0xc108930e +mem-write: 0x80002733 <- 0x5ff06f10 +mem-write: 0x80002737 <- 0x412683fb +mem-write: 0x8000273b <- 0xa779301 +mem-write: 0x8000273f <- 0x46871301 +mem-write: 0x80002743 <- 0x7806300 +mem-write: 0x80002747 <- 0x6a9031c +mem-write: 0x8000274b <- 0xc9300 +mem-write: 0x8000274f <- 0xe12a2300 +mem-write: 0x80002753 <- 0x5ff06f00 +mem-write: 0x80002757 <- 0x410613ed +mem-write: 0x8000275b <- 0xc05930e +mem-write: 0x8000275f <- 0xd051300 +mem-write: 0x80002763 <- 0x1090ef00 +mem-write: 0x80002767 <- 0x514e31c +mem-write: 0x8000276b <- 0xc12c8384 +mem-write: 0x8000276f <- 0x8124830e +mem-write: 0x80002773 <- 0xc109130e +mem-write: 0x80002777 <- 0x9ff06f10 +mem-write: 0x8000277b <- 0x41061388 +mem-write: 0x8000277f <- 0xc05930e +mem-write: 0x80002783 <- 0xd051300 +mem-write: 0x80002787 <- 0xd090ef00 +mem-write: 0x8000278b <- 0x512e319 +mem-write: 0x8000278f <- 0xc12c8382 +mem-write: 0x80002793 <- 0x8124830e +mem-write: 0x80002797 <- 0xc109130e +mem-write: 0x8000279b <- 0x1ff06f10 +mem-write: 0x8000279f <- 0x10b1389 +mem-write: 0x800027a3 <- 0x7931b +mem-write: 0x800027a7 <- 0x81282300 +mem-write: 0x800027ab <- 0x912e2300 +mem-write: 0x800027af <- 0xb041300 +mem-write: 0x800027b3 <- 0x31222300 +mem-write: 0x800027b7 <- 0xc0b1303 +mem-write: 0x800027bb <- 0x9049300 +mem-write: 0x800027bf <- 0xc899300 +mem-write: 0x800027c3 <- 0xbfa1300 +mem-write: 0x800027c7 <- 0xc12c8340 +mem-write: 0x800027cb <- 0xf00a9303 +mem-write: 0x800027cf <- 0x88c130f +mem-write: 0x800027d3 <- 0x7891300 +mem-write: 0x800027d7 <- 0x40006f00 +mem-write: 0x800027db <- 0xa0061302 +mem-write: 0x800027df <- 0x69300 +mem-write: 0x800027e3 <- 0x4851300 +mem-write: 0x800027e7 <- 0x9859300 +mem-write: 0x800027eb <- 0xd0d0ef00 +mem-write: 0x800027ef <- 0x98ae33f +mem-write: 0x800027f3 <- 0x504932a +mem-write: 0x800027f7 <- 0x5899300 +mem-write: 0x800027fb <- 0xa0061300 +VXDRV: upload 1024 bytes to 0x800027ff +mem-write: 0x800027ff <- 0x69300 +mem-write: 0x80002803 <- 0x4851300 +mem-write: 0x80002807 <- 0x9859300 +mem-write: 0x8000280b <- 0xe0ef00 +mem-write: 0x8000280f <- 0x5051301 +mem-write: 0x80002813 <- 0xa40fa303 +mem-write: 0x80002817 <- 0x190913fe +mem-write: 0x8000281b <- 0xf4041300 +mem-write: 0x8000281f <- 0xa0ee3ff +mem-write: 0x80002823 <- 0xcc683fa +mem-write: 0x80002827 <- 0xd91ae300 +mem-write: 0x8000282b <- 0x5908e3fa +mem-write: 0x8000282f <- 0x99263fb +mem-write: 0x80002833 <- 0x9007934a +mem-write: 0x80002837 <- 0x97ee6300 +mem-write: 0x8000283b <- 0xc089348 +mem-write: 0x8000283f <- 0x1079300 +mem-write: 0x80002843 <- 0xb0c131b +mem-write: 0x80002847 <- 0x40b1300 +mem-write: 0x8000284b <- 0x912e2300 +mem-write: 0x8000284f <- 0xc1248303 +mem-write: 0x80002853 <- 0x41298301 +mem-write: 0x80002857 <- 0x1240302 +mem-write: 0x8000285b <- 0x21202301 +mem-write: 0x8000285f <- 0x678cb303 +mem-write: 0x80002863 <- 0xb8a1341 +mem-write: 0x80002867 <- 0x4ff06f00 +mem-write: 0x8000286b <- 0x8126839d +mem-write: 0x8000286f <- 0x156370e +mem-write: 0x80002873 <- 0x6061380 +mem-write: 0x80002877 <- 0xc8a02398 +mem-write: 0x8000287b <- 0x17879300 +mem-write: 0x8000287f <- 0x10061300 +mem-write: 0x80002883 <- 0x16869300 +mem-write: 0x80002887 <- 0xc8a22300 +mem-write: 0x8000288b <- 0xf1262300 +mem-write: 0x8000288f <- 0xd124230e +mem-write: 0x80002893 <- 0x7006130e +mem-write: 0x80002897 <- 0x88889300 +mem-write: 0x8000289b <- 0xd6446300 +mem-write: 0x8000289f <- 0x5846348 +mem-write: 0x800028a3 <- 0xdfe06f00 +mem-write: 0x800028a7 <- 0x12703ea +mem-write: 0x800028ab <- 0x1a769302 +mem-write: 0x800028af <- 0xe6e6b300 +mem-write: 0x800028b3 <- 0x6946300 +mem-write: 0x800028b7 <- 0x1fe06f00 +mem-write: 0x800028bb <- 0x126839d +mem-write: 0x800028bf <- 0xc1270303 +mem-write: 0x800028c3 <- 0x70061302 +mem-write: 0x800028c7 <- 0xd8a02300 +mem-write: 0x800028cb <- 0x81268300 +mem-write: 0x800028cf <- 0xf707b30e +mem-write: 0x800028d3 <- 0xe8a22300 +mem-write: 0x800028d7 <- 0x16869300 +mem-write: 0x800028db <- 0xf1262300 +mem-write: 0x800028df <- 0xd124230e +mem-write: 0x800028e3 <- 0xd654630e +mem-write: 0x800028e7 <- 0x9fe06f00 +mem-write: 0x800028eb <- 0x888893e9 +mem-write: 0x800028ef <- 0xdfe06f00 +mem-write: 0x800028f3 <- 0x12b83eb +mem-write: 0x800028f7 <- 0x40d1301 +mem-write: 0x800028fb <- 0x48c1300 +mem-write: 0x800028ff <- 0x4ff06f00 +mem-write: 0x80002903 <- 0xa7793eb +mem-write: 0x80002907 <- 0x7806304 +mem-write: 0x8000290b <- 0x41278314 +mem-write: 0x8000290f <- 0xc9301 +mem-write: 0x80002913 <- 0xe12a2300 +mem-write: 0x80002917 <- 0x7d90300 +mem-write: 0x8000291b <- 0xdff06f00 +mem-write: 0x8000291f <- 0x410613d0 +mem-write: 0x80002923 <- 0xc05930e +mem-write: 0x80002927 <- 0xd051300 +mem-write: 0x8000292b <- 0x8090ef00 +mem-write: 0x8000292f <- 0x510637f +mem-write: 0x80002933 <- 0xc12783e8 +mem-write: 0x80002937 <- 0xc108930e +mem-write: 0x8000293b <- 0xcff06f10 +mem-write: 0x8000293f <- 0x812683c3 +mem-write: 0x80002943 <- 0x9787b300 +mem-write: 0x80002947 <- 0x98a22300 +mem-write: 0x8000294b <- 0xd8a02300 +mem-write: 0x8000294f <- 0x17071300 +mem-write: 0x80002953 <- 0xf1262300 +mem-write: 0x80002957 <- 0xe124230e +mem-write: 0x8000295b <- 0x7006930e +mem-write: 0x8000295f <- 0xe6c46300 +mem-write: 0x80002963 <- 0x1fe06f00 +mem-write: 0x80002967 <- 0x9fe06f92 +mem-write: 0x8000296b <- 0x12783e6 +mem-write: 0x8000296f <- 0x105930f +mem-write: 0x80002973 <- 0x105130a +mem-write: 0x80002977 <- 0xf128230b +mem-write: 0x8000297b <- 0x4127830a +mem-write: 0x8000297f <- 0x120230f +mem-write: 0x80002983 <- 0x122230a +mem-write: 0x80002987 <- 0xf12a230a +mem-write: 0x8000298b <- 0x8127830a +mem-write: 0x8000298f <- 0x124230f +mem-write: 0x80002993 <- 0x126230a +mem-write: 0x80002997 <- 0xf12c230a +mem-write: 0x8000299b <- 0xc127830a +mem-write: 0x8000299f <- 0xf12e230f +mem-write: 0x800029a3 <- 0xc0f0ef0a +mem-write: 0x800029a7 <- 0x1288313 +mem-write: 0x800029ab <- 0x540e301 +mem-write: 0x800029af <- 0x71478326 +mem-write: 0x800029b3 <- 0x7007130c +mem-write: 0x800029b7 <- 0x97586304 +mem-write: 0x800029bb <- 0x1573738 +mem-write: 0x800029bf <- 0x70b1380 +mem-write: 0x800029c3 <- 0x12823a3 +mem-write: 0x800029c7 <- 0x1242300 +mem-write: 0x800029cb <- 0x1222302 +mem-write: 0x800029cf <- 0x12e2302 +mem-write: 0x800029d3 <- 0xfa7a1300 +mem-write: 0x800029d7 <- 0x300a93f7 +mem-write: 0x800029db <- 0x300c9300 +mem-write: 0x800029df <- 0xd9300 +mem-write: 0x800029e3 <- 0x7846300 +mem-write: 0x800029e7 <- 0x5fe06f00 +mem-write: 0x800029eb <- 0xcfe06ff7 +mem-write: 0x800029ef <- 0xc12783fc +mem-write: 0x800029f3 <- 0x40b1300 +mem-write: 0x800029f7 <- 0xf7202300 +mem-write: 0x800029fb <- 0x5fe06f00 +mem-write: 0x800029ff <- 0xb05138d +mem-write: 0x80002a03 <- 0x91202300 +mem-write: 0x80002a07 <- 0x5060ef05 +mem-write: 0x80002a0b <- 0x7147832e +mem-write: 0x80002a0f <- 0xf54a930c +mem-write: 0x80002a13 <- 0xfada93ff +mem-write: 0x80002a17 <- 0x212a2341 +mem-write: 0x80002a1b <- 0x1282301 +mem-write: 0x80002a1f <- 0x1242300 +mem-write: 0x80002a23 <- 0x1222302 +mem-write: 0x80002a27 <- 0x12e2302 +mem-write: 0x80002a2b <- 0x1288300 +mem-write: 0x80002a2f <- 0x50c9304 +mem-write: 0x80002a33 <- 0x557ab300 +mem-write: 0x80002a37 <- 0xd9301 +mem-write: 0x80002a3b <- 0x7846300 +mem-write: 0x80002a3f <- 0xdfe06f00 +mem-write: 0x80002a43 <- 0x4fe06ff1 +mem-write: 0x80002a47 <- 0xa7793f7 +mem-write: 0x80002a4b <- 0x7826320 +mem-write: 0x80002a4f <- 0x4127833a +mem-write: 0x80002a53 <- 0xc9301 +mem-write: 0x80002a57 <- 0xe12a2300 +mem-write: 0x80002a5b <- 0x7c90300 +mem-write: 0x80002a5f <- 0x9ff06f00 +mem-write: 0x80002a63 <- 0xbf793bc +mem-write: 0x80002a67 <- 0x7886320 +mem-write: 0x80002a6b <- 0x41278336 +mem-write: 0x80002a6f <- 0xc9301 +mem-write: 0x80002a73 <- 0xe12a2300 +mem-write: 0x80002a77 <- 0x7c90300 +mem-write: 0x80002a7b <- 0x10079300 +mem-write: 0x80002a7f <- 0x1fe06f00 +mem-write: 0x80002a83 <- 0xa7793f9 +mem-write: 0x80002a87 <- 0x78c6320 +mem-write: 0x80002a8b <- 0x41278332 +mem-write: 0x80002a8f <- 0xe12a2301 +mem-write: 0x80002a93 <- 0x7890300 +mem-write: 0x80002a97 <- 0xf95c9300 +mem-write: 0x80002a9b <- 0xc879341 +mem-write: 0x80002a9f <- 0x8ff06f00 +mem-write: 0x80002aa3 <- 0xa779392 +mem-write: 0x80002aa7 <- 0x7826320 +mem-write: 0x80002aab <- 0x41278330 +mem-write: 0x80002aaf <- 0xc9301 +mem-write: 0x80002ab3 <- 0xe12a2300 +mem-write: 0x80002ab7 <- 0x7c90300 +mem-write: 0x80002abb <- 0xff06f00 +mem-write: 0x80002abf <- 0xc1278389 +mem-write: 0x80002ac3 <- 0x7ca630f +mem-write: 0x80002ac7 <- 0x71478334 +mem-write: 0x80002acb <- 0x7007130c +mem-write: 0x80002acf <- 0x975ce304 +mem-write: 0x80002ad3 <- 0x157371c +mem-write: 0x80002ad7 <- 0x870b1380 +mem-write: 0x80002adb <- 0x9ff06fa3 +mem-write: 0x80002adf <- 0x812703ee +mem-write: 0x80002ae3 <- 0x9787b300 +mem-write: 0x80002ae7 <- 0x16869300 +mem-write: 0x80002aeb <- 0xe8a02300 +mem-write: 0x80002aef <- 0x98a22300 +mem-write: 0x80002af3 <- 0xf1262300 +mem-write: 0x80002af7 <- 0xd124230e +mem-write: 0x80002afb <- 0x7006130e +mem-write: 0x80002aff <- 0x88889300 +mem-write: 0x80002b03 <- 0xd6546300 +mem-write: 0x80002b07 <- 0x410613f4 +mem-write: 0x80002b0b <- 0xc05930e +mem-write: 0x80002b0f <- 0xd051300 +mem-write: 0x80002b13 <- 0x90ef00 +mem-write: 0x80002b17 <- 0x51c6361 +mem-write: 0x80002b1b <- 0xc12783c8 +mem-write: 0x80002b1f <- 0xc108930e +mem-write: 0x80002b23 <- 0x8ff06f10 +mem-write: 0x80002b27 <- 0x12703f2 +mem-write: 0x80002b2b <- 0x412c8302 +mem-write: 0x80002b2f <- 0x412e2302 +mem-write: 0x80002b33 <- 0x81202301 +mem-write: 0x80002b37 <- 0x31222304 +mem-write: 0x80002b3b <- 0x51222305 +mem-write: 0x80002b3f <- 0x81298303 +mem-write: 0x80002b43 <- 0x61242302 +mem-write: 0x80002b47 <- 0xeb0bb303 +mem-write: 0x80002b4b <- 0xc1240300 +mem-write: 0x80002b4f <- 0x812a0303 +mem-write: 0x80002b53 <- 0xc12a8304 +mem-write: 0x80002b57 <- 0x70049304 +mem-write: 0x80002b5b <- 0x91300 +mem-write: 0x80002b5f <- 0xc0b1301 +mem-write: 0x80002b63 <- 0xc886300 +mem-write: 0x80002b67 <- 0x9986308 +mem-write: 0x80002b6b <- 0xf4041308 +mem-write: 0x80002b6f <- 0xfc8c93ff +mem-write: 0x80002b73 <- 0x812703ff +mem-write: 0x80002b77 <- 0x4787b30e +mem-write: 0x80002b7b <- 0x58a02301 +mem-write: 0x80002b7f <- 0x17071301 +mem-write: 0x80002b83 <- 0x48a22300 +mem-write: 0x80002b87 <- 0xf1262301 +mem-write: 0x80002b8b <- 0xe124230e +mem-write: 0x80002b8f <- 0x8888930e +mem-write: 0x80002b93 <- 0xe4ce6300 +mem-write: 0x80002b97 <- 0x446830e +mem-write: 0x80002b9b <- 0xbb863300 +mem-write: 0x80002b9f <- 0x68c1341 +mem-write: 0x80002ba3 <- 0xd6546300 +mem-write: 0x80002ba7 <- 0x60c1300 +mem-write: 0x80002bab <- 0x80566300 +mem-write: 0x80002baf <- 0x81268303 +mem-write: 0x80002bb3 <- 0x8787b30e +mem-write: 0x80002bb7 <- 0xb8a02301 +mem-write: 0x80002bbb <- 0x16869301 +mem-write: 0x80002bbf <- 0x88a22300 +mem-write: 0x80002bc3 <- 0xf1262301 +mem-write: 0x80002bc7 <- 0xd124230e +mem-write: 0x80002bcb <- 0xd4c2630e +mem-write: 0x80002bcf <- 0x446830e +mem-write: 0x80002bd3 <- 0x88889300 +mem-write: 0x80002bd7 <- 0xfc461300 +mem-write: 0x80002bdb <- 0xf65613ff +mem-write: 0x80002bdf <- 0xcc773341 +mem-write: 0x80002be3 <- 0xe68c3300 +mem-write: 0x80002be7 <- 0x804c6340 +mem-write: 0x80002beb <- 0xdd8db301 +mem-write: 0x80002bef <- 0xc9ce300 +mem-write: 0x80002bf3 <- 0x98a63f6 +mem-write: 0x80002bf7 <- 0xf989935e +mem-write: 0x80002bfb <- 0x9ff06fff +VXDRV: upload 1024 bytes to 0x80002bff +mem-write: 0x80002bff <- 0x812683f7 +mem-write: 0x80002c03 <- 0x8948630e +mem-write: 0x80002c07 <- 0x80006f01 +mem-write: 0x80002c0b <- 0xc0c1305 +mem-write: 0x80002c0f <- 0x895863ff +mem-write: 0x80002c13 <- 0x81270305 +mem-write: 0x80002c17 <- 0x7879300 +mem-write: 0x80002c1b <- 0x16869301 +mem-write: 0x80002c1f <- 0xe8a02300 +mem-write: 0x80002c23 <- 0x28a22300 +mem-write: 0x80002c27 <- 0xf1262301 +mem-write: 0x80002c2b <- 0xd124230e +mem-write: 0x80002c2f <- 0x8888930e +mem-write: 0x80002c33 <- 0xd4dce300 +mem-write: 0x80002c37 <- 0x410613fc +mem-write: 0x80002c3b <- 0xb05930e +mem-write: 0x80002c3f <- 0xd051300 +mem-write: 0x80002c43 <- 0x90ef00 +mem-write: 0x80002c47 <- 0x514634e +mem-write: 0x80002c4b <- 0xc0c1366 +mem-write: 0x80002c4f <- 0xc12783ff +mem-write: 0x80002c53 <- 0x8126830e +mem-write: 0x80002c57 <- 0xc108930e +mem-write: 0x80002c5b <- 0x894ce310 +mem-write: 0x80002c5f <- 0x812703fb +mem-write: 0x80002c63 <- 0x8787b300 +mem-write: 0x80002c67 <- 0x16869301 +mem-write: 0x80002c6b <- 0xe8a02300 +mem-write: 0x80002c6f <- 0x88a22300 +mem-write: 0x80002c73 <- 0xf1262301 +mem-write: 0x80002c77 <- 0xd124230e +mem-write: 0x80002c7b <- 0xd4c0630e +mem-write: 0x80002c7f <- 0x4468366 +mem-write: 0x80002c83 <- 0x88889300 +mem-write: 0x80002c87 <- 0xdd8db300 +mem-write: 0x80002c8b <- 0x5ff06f00 +mem-write: 0x80002c8f <- 0x410613f6 +mem-write: 0x80002c93 <- 0xb05930e +mem-write: 0x80002c97 <- 0xd051300 +mem-write: 0x80002c9b <- 0x8090ef00 +mem-write: 0x80002c9f <- 0x5186348 +mem-write: 0x80002ca3 <- 0xc1278360 +mem-write: 0x80002ca7 <- 0xc108930e +mem-write: 0x80002cab <- 0xdff06f10 +mem-write: 0x80002caf <- 0x410613ee +mem-write: 0x80002cb3 <- 0xb05930e +mem-write: 0x80002cb7 <- 0xd051300 +mem-write: 0x80002cbb <- 0x8090ef00 +mem-write: 0x80002cbf <- 0x5186346 +mem-write: 0x80002cc3 <- 0x446835e +mem-write: 0x80002cc7 <- 0xc1278300 +mem-write: 0x80002ccb <- 0xc108930e +mem-write: 0x80002ccf <- 0x9ff06f10 +mem-write: 0x80002cd3 <- 0x812783f0 +mem-write: 0x80002cd7 <- 0xc1258304 +mem-write: 0x80002cdb <- 0x91304 +mem-write: 0x80002cdf <- 0xf4043300 +mem-write: 0x80002ce3 <- 0x7861340 +mem-write: 0x80002ce7 <- 0x4051300 +mem-write: 0x80002ceb <- 0xd060ef00 +mem-write: 0x80002cef <- 0x1cc58308 +mem-write: 0x80002cf3 <- 0xa0061300 +mem-write: 0x80002cf7 <- 0x69300 +mem-write: 0x80002cfb <- 0xb0383300 +mem-write: 0x80002cff <- 0x4851300 +mem-write: 0x80002d03 <- 0x9859300 +mem-write: 0x80002d07 <- 0xc8cb300 +mem-write: 0x80002d0b <- 0xc0d0ef01 +mem-write: 0x80002d0f <- 0x5ff06f6d +mem-write: 0x80002d13 <- 0x168693ae +mem-write: 0x80002d17 <- 0x87089300 +mem-write: 0x80002d1b <- 0x7091300 +mem-write: 0x80002d1f <- 0x8ff06f00 +mem-write: 0x80002d23 <- 0x410613b9 +mem-write: 0x80002d27 <- 0xc05930e +mem-write: 0x80002d2b <- 0xd051300 +mem-write: 0x80002d2f <- 0x4090ef00 +mem-write: 0x80002d33 <- 0x51e633f +mem-write: 0x80002d37 <- 0xc12583a6 +mem-write: 0x80002d3b <- 0xc127830c +mem-write: 0x80002d3f <- 0xc108930e +mem-write: 0x80002d43 <- 0xdff06f10 +mem-write: 0x80002d47 <- 0x15737b5 +mem-write: 0x80002d4b <- 0xc70b1380 +mem-write: 0x80002d4f <- 0x5ff06fa2 +mem-write: 0x80002d53 <- 0x410613c7 +mem-write: 0x80002d57 <- 0xc05930e +mem-write: 0x80002d5b <- 0xd051300 +mem-write: 0x80002d5f <- 0x4090ef00 +mem-write: 0x80002d63 <- 0x516633c +mem-write: 0x80002d67 <- 0xc12783a4 +mem-write: 0x80002d6b <- 0xc108930e +mem-write: 0x80002d6f <- 0x4ff06f10 +mem-write: 0x80002d73 <- 0x600c93cc +mem-write: 0x80002d77 <- 0x5ff06f00 +mem-write: 0x80002d7b <- 0x1268394 +mem-write: 0x80002d7f <- 0xdb073302 +mem-write: 0x80002d83 <- 0x9684b300 +mem-write: 0x80002d87 <- 0xb7083340 +mem-write: 0x80002d8b <- 0x4891341 +mem-write: 0x80002d8f <- 0x98506300 +mem-write: 0x80002d93 <- 0x80913d6 +mem-write: 0x80002d97 <- 0x8ff06f00 +mem-write: 0x80002d9b <- 0xc12783d5 +mem-write: 0x80002d9f <- 0x40b1300 +mem-write: 0x80002da3 <- 0xf7102300 +mem-write: 0x80002da7 <- 0x8fe06f00 +mem-write: 0x80002dab <- 0x412783d2 +mem-write: 0x80002daf <- 0xc9301 +mem-write: 0x80002db3 <- 0xe12a2300 +mem-write: 0x80002db7 <- 0x7a90300 +mem-write: 0x80002dbb <- 0x1fe06f00 +mem-write: 0x80002dbf <- 0x412783d9 +mem-write: 0x80002dc3 <- 0xe12a2301 +mem-write: 0x80002dc7 <- 0x7a90300 +mem-write: 0x80002dcb <- 0xf95c9300 +mem-write: 0x80002dcf <- 0xc879341 +mem-write: 0x80002dd3 <- 0x5fe06f00 +mem-write: 0x80002dd7 <- 0x412783df +mem-write: 0x80002ddb <- 0xc9301 +mem-write: 0x80002ddf <- 0xe12a2300 +mem-write: 0x80002de3 <- 0x7a90300 +mem-write: 0x80002de7 <- 0x10079300 +mem-write: 0x80002deb <- 0x5fe06f00 +mem-write: 0x80002def <- 0x412783c2 +mem-write: 0x80002df3 <- 0xc9301 +mem-write: 0x80002df7 <- 0xe12a2300 +mem-write: 0x80002dfb <- 0x7a90300 +mem-write: 0x80002dff <- 0x9ff06f00 +mem-write: 0x80002e03 <- 0x41061382 +mem-write: 0x80002e07 <- 0xc05930e +mem-write: 0x80002e0b <- 0xd051300 +mem-write: 0x80002e0f <- 0x4090ef00 +mem-write: 0x80002e13 <- 0xfe06f31 +mem-write: 0x80002e17 <- 0xd00793cd +mem-write: 0x80002e1b <- 0xf103a302 +mem-write: 0x80002e1f <- 0xdff06f0c +mem-write: 0x80002e23 <- 0x793ca +mem-write: 0x80002e27 <- 0xf1042303 +mem-write: 0x80002e2b <- 0x8007930c +mem-write: 0x80002e2f <- 0x2a671305 +mem-write: 0x80002e33 <- 0xf104a300 +mem-write: 0x80002e37 <- 0xe124230c +mem-write: 0x80002e3b <- 0x30079302 +mem-write: 0x80002e3f <- 0x1282306 +mem-write: 0x80002e43 <- 0xc10b1300 +mem-write: 0x80002e47 <- 0xb7c4e314 +mem-write: 0x80002e4b <- 0xc1230303 +mem-write: 0x80002e4f <- 0xf4fb930f +mem-write: 0x80002e53 <- 0x712223fd +mem-write: 0x80002e57 <- 0x12c2305 +mem-write: 0x80002e5b <- 0x12e0304 +mem-write: 0x80002e5f <- 0x412e830f +mem-write: 0x80002e63 <- 0x812f030f +mem-write: 0x80002e67 <- 0x2a6a130f +mem-write: 0x80002e6b <- 0x34e6310 +mem-write: 0x80002e6f <- 0x10079344 +mem-write: 0x80002e73 <- 0xf48ee306 +mem-write: 0x80002e77 <- 0x1007930a +mem-write: 0x80002e7b <- 0xf4846304 +mem-write: 0x80002e7f <- 0x4fe06f00 +mem-write: 0x80002e83 <- 0x10a93e6 +mem-write: 0x80002e87 <- 0xa85130b +mem-write: 0x80002e8b <- 0x112a2300 +mem-write: 0x80002e8f <- 0xc1282305 +mem-write: 0x80002e93 <- 0xd12a230b +mem-write: 0x80002e97 <- 0xe12c230b +mem-write: 0x80002e9b <- 0x612e230b +mem-write: 0x80002e9f <- 0x110ef0a +mem-write: 0x80002ea3 <- 0xc1061370 +mem-write: 0x80002ea7 <- 0x60ef0c +mem-write: 0x80002eab <- 0x5861325 +mem-write: 0x80002eaf <- 0x5059300 +mem-write: 0x80002eb3 <- 0xa851300 +mem-write: 0x80002eb7 <- 0x4110ef00 +mem-write: 0x80002ebb <- 0x127834f +mem-write: 0x80002ebf <- 0x10c930b +mem-write: 0x80002ec3 <- 0x109130a +mem-write: 0x80002ec7 <- 0xf1282309 +mem-write: 0x80002ecb <- 0x41278308 +mem-write: 0x80002ecf <- 0x106130b +mem-write: 0x80002ed3 <- 0x9059308 +mem-write: 0x80002ed7 <- 0xf12a2300 +mem-write: 0x80002edb <- 0x81278308 +mem-write: 0x80002edf <- 0xc85130b +mem-write: 0x80002ee3 <- 0xc1202300 +mem-write: 0x80002ee7 <- 0xf12c2304 +mem-write: 0x80002eeb <- 0xc1278308 +mem-write: 0x80002eef <- 0x120230b +mem-write: 0x80002ef3 <- 0x1222308 +mem-write: 0x80002ef7 <- 0xf12e2308 +mem-write: 0x80002efb <- 0xfc07b708 +mem-write: 0x80002eff <- 0xf126233f +mem-write: 0x80002f03 <- 0x1242308 +mem-write: 0x80002f07 <- 0xd0e0ef08 +mem-write: 0x80002f0b <- 0x1280351 +mem-write: 0x80002f0f <- 0x412e030a +mem-write: 0x80002f13 <- 0x812e830a +mem-write: 0x80002f17 <- 0xc12f030a +mem-write: 0x80002f1b <- 0xc85930a +mem-write: 0x80002f1f <- 0xa851300 +mem-write: 0x80002f23 <- 0x1282300 +mem-write: 0x80002f27 <- 0x128230b +mem-write: 0x80002f2b <- 0xc12a2305 +mem-write: 0x80002f2f <- 0xc122230b +mem-write: 0x80002f33 <- 0xd12c2303 +mem-write: 0x80002f37 <- 0xd120230b +mem-write: 0x80002f3b <- 0xe12e2303 +mem-write: 0x80002f3f <- 0xe12e230b +mem-write: 0x80002f43 <- 0x1202301 +mem-write: 0x80002f47 <- 0x122230a +mem-write: 0x80002f4b <- 0x124230a +mem-write: 0x80002f4f <- 0x126230a +mem-write: 0x80002f53 <- 0xd0e0ef0a +mem-write: 0x80002f57 <- 0xc12f0317 +mem-write: 0x80002f5b <- 0x12e8301 +mem-write: 0x80002f5f <- 0x412e0302 +mem-write: 0x80002f63 <- 0x1280302 +mem-write: 0x80002f67 <- 0x41288305 +mem-write: 0x80002f6b <- 0x5166305 +mem-write: 0x80002f6f <- 0x10079300 +mem-write: 0x80002f73 <- 0xf1262300 +mem-write: 0x80002f77 <- 0x157b70c +mem-write: 0x80002f7b <- 0x7879380 +mem-write: 0x80002f7f <- 0xf12223a5 +mem-write: 0x80002f83 <- 0xfd869302 +mem-write: 0x80002f87 <- 0x412e23ff +mem-write: 0x80002f8b <- 0x91222305 +mem-write: 0x80002f8f <- 0xb1262306 +mem-write: 0x80002f93 <- 0xa12a2307 +mem-write: 0x80002f97 <- 0x812c2307 +mem-write: 0x80002f9b <- 0x81202307 +mem-write: 0x80002f9f <- 0x31242306 +mem-write: 0x80002fa3 <- 0x11282307 +mem-write: 0x80002fa7 <- 0xb0c1307 +mem-write: 0x80002fab <- 0x68b9300 +mem-write: 0x80002faf <- 0x612e2300 +mem-write: 0x80002fb3 <- 0x80d1307 +mem-write: 0x80002fb7 <- 0xe0d9300 +mem-write: 0x80002fbb <- 0xe849300 +mem-write: 0x80002fbf <- 0xf0a1300 +mem-write: 0x80002fc3 <- 0x80006f00 +mem-write: 0x80002fc7 <- 0xc859304 +mem-write: 0x80002fcb <- 0xa851300 +mem-write: 0x80002fcf <- 0xc1202300 +mem-write: 0x80002fd3 <- 0xf12e2302 +mem-write: 0x80002fd7 <- 0xf12c2301 +mem-write: 0x80002fdb <- 0xc12e230b +mem-write: 0x80002fdf <- 0x6128230a +mem-write: 0x80002fe3 <- 0x312a230b +mem-write: 0x80002fe7 <- 0x120230b +mem-write: 0x80002feb <- 0x122230a +mem-write: 0x80002fef <- 0x124230a +mem-write: 0x80002ff3 <- 0x126230a +mem-write: 0x80002ff7 <- 0x90e0ef0a +mem-write: 0x80002ffb <- 0xc12f830d +VXDRV: upload 1024 bytes to 0x80002fff +mem-write: 0x80002fff <- 0x1260301 +mem-write: 0x80003003 <- 0xfb8b9302 +mem-write: 0x80003007 <- 0x50263ff +mem-write: 0x8000300b <- 0x307b70e +mem-write: 0x8000300f <- 0x9061340 +mem-write: 0x80003013 <- 0xc859300 +mem-write: 0x80003017 <- 0xa851300 +mem-write: 0x8000301b <- 0xf12e2300 +mem-write: 0x8000301f <- 0xa1202308 +mem-write: 0x80003023 <- 0xb122230b +mem-write: 0x80003027 <- 0x9124230b +mem-write: 0x8000302b <- 0x4126230a +mem-write: 0x8000302f <- 0x128230b +mem-write: 0x80003033 <- 0x12a2308 +mem-write: 0x80003037 <- 0x12c2308 +mem-write: 0x8000303b <- 0x90e0ef08 +mem-write: 0x8000303f <- 0xa85133e +mem-write: 0x80003043 <- 0x4110ef00 +mem-write: 0x80003047 <- 0x5059310 +mem-write: 0x8000304b <- 0x5041300 +mem-write: 0x8000304f <- 0xa851300 +mem-write: 0x80003053 <- 0x1298300 +mem-write: 0x80003057 <- 0x4124830b +mem-write: 0x8000305b <- 0x812b030b +mem-write: 0x8000305f <- 0xc12a030b +mem-write: 0x80003063 <- 0x8110ef0b +mem-write: 0x80003067 <- 0x127031f +mem-write: 0x8000306b <- 0x126030b +mem-write: 0x8000306f <- 0x9059304 +mem-write: 0x80003073 <- 0xe1202300 +mem-write: 0x80003077 <- 0x41270308 +mem-write: 0x8000307b <- 0xc85130b +mem-write: 0x8000307f <- 0x31282300 +mem-write: 0x80003083 <- 0xe1222309 +mem-write: 0x80003087 <- 0x81270308 +mem-write: 0x8000308b <- 0x912a230b +mem-write: 0x8000308f <- 0x612c2308 +mem-write: 0x80003093 <- 0xe1242309 +mem-write: 0x80003097 <- 0xc1270308 +mem-write: 0x8000309b <- 0x412e230b +mem-write: 0x8000309f <- 0xe1262309 +mem-write: 0x800030a3 <- 0x50f0ef08 +mem-write: 0x800030a7 <- 0x41278338 +mem-write: 0x800030ab <- 0x12b0302 +mem-write: 0x800030af <- 0x4129830a +mem-write: 0x800030b3 <- 0x8787330a +mem-write: 0x800030b7 <- 0x7470300 +mem-write: 0x800030bb <- 0x812f8300 +mem-write: 0x800030bf <- 0xc126030a +mem-write: 0x800030c3 <- 0x812a230a +mem-write: 0x800030c7 <- 0xec002305 +mem-write: 0x800030cb <- 0x71282300 +mem-write: 0x800030cf <- 0xf0079305 +mem-write: 0x800030d3 <- 0x1c0c13ff +mem-write: 0x800030d7 <- 0xb0d1300 +mem-write: 0x800030db <- 0x98d9300 +mem-write: 0x800030df <- 0xf849300 +mem-write: 0x800030e3 <- 0x60a1300 +mem-write: 0x800030e7 <- 0xfb90e300 +mem-write: 0x800030eb <- 0x12883ee +mem-write: 0x800030ef <- 0xb039307 +mem-write: 0x800030f3 <- 0x9829300 +mem-write: 0x800030f7 <- 0xfe093700 +mem-write: 0x800030fb <- 0xc85933f +mem-write: 0x800030ff <- 0xa851300 +mem-write: 0x80003103 <- 0x11202300 +mem-write: 0x80003107 <- 0x812e2303 +mem-write: 0x8000310b <- 0xc12a0300 +mem-write: 0x8000310f <- 0x41248305 +mem-write: 0x80003113 <- 0x1240306 +mem-write: 0x80003117 <- 0x71282306 +mem-write: 0x8000311b <- 0x7122230a +mem-write: 0x8000311f <- 0x512a2306 +mem-write: 0x80003123 <- 0x5120230a +mem-write: 0x80003127 <- 0xf12c2306 +mem-write: 0x8000312b <- 0xf12e230b +mem-write: 0x8000312f <- 0xc12e2305 +mem-write: 0x80003133 <- 0xc120230a +mem-write: 0x80003137 <- 0x1202304 +mem-write: 0x8000313b <- 0x122230a +mem-write: 0x8000313f <- 0x124230a +mem-write: 0x80003143 <- 0x2126230a +mem-write: 0x80003147 <- 0x50e0ef0b +mem-write: 0x8000314b <- 0xc0b9305 +mem-write: 0x8000314f <- 0xc12d8300 +mem-write: 0x80003153 <- 0x412d0306 +mem-write: 0x80003157 <- 0x812c0307 +mem-write: 0x8000315b <- 0xc12b0307 +mem-write: 0x8000315f <- 0x81298307 +mem-write: 0x80003163 <- 0x1288306 +mem-write: 0x80003167 <- 0xa0426302 +mem-write: 0x8000316b <- 0x41238348 +mem-write: 0x8000316f <- 0x1228306 +mem-write: 0x80003173 <- 0xc12f8306 +mem-write: 0x80003177 <- 0x1260305 +mem-write: 0x8000317b <- 0xc859304 +mem-write: 0x8000317f <- 0xa851300 +mem-write: 0x80003183 <- 0x71282300 +mem-write: 0x80003187 <- 0x512a230a +mem-write: 0x8000318b <- 0xf12c230a +mem-write: 0x8000318f <- 0xc12e230b +mem-write: 0x80003193 <- 0x120230a +mem-write: 0x80003197 <- 0x122230a +mem-write: 0x8000319b <- 0x124230a +mem-write: 0x8000319f <- 0x2126230a +mem-write: 0x800031a3 <- 0xc0e0ef0b +mem-write: 0x800031a7 <- 0x1288372 +mem-write: 0x800031ab <- 0x5186302 +mem-write: 0x800031af <- 0xc1278300 +mem-write: 0x800031b3 <- 0x17fc9301 +mem-write: 0x800031b7 <- 0xc9a6300 +mem-write: 0x800031bb <- 0x1278342 +mem-write: 0x800031bf <- 0x61305 +mem-write: 0x800031c3 <- 0x17869303 +mem-write: 0x800031c7 <- 0xdb86b300 +mem-write: 0x800031cb <- 0x7c86300 +mem-write: 0x800031cf <- 0x1b8b9300 +mem-write: 0x800031d3 <- 0xcb8fa300 +mem-write: 0x800031d7 <- 0x769ce3fe +mem-write: 0x800031db <- 0x6b87b3ff +mem-write: 0x800031df <- 0xf1202341 +mem-write: 0x800031e3 <- 0x8fe06f02 +mem-write: 0x800031e7 <- 0x12703be +mem-write: 0x800031eb <- 0xb0c1302 +mem-write: 0x800031ef <- 0x812b0300 +mem-write: 0x800031f3 <- 0x812e2302 +mem-write: 0x800031f7 <- 0xc12a0302 +mem-write: 0x800031fb <- 0xeb06b301 +mem-write: 0x800031ff <- 0x1240300 +mem-write: 0x80003203 <- 0x41298304 +mem-write: 0x80003207 <- 0x412a8304 +mem-write: 0x8000320b <- 0xb6e46302 +mem-write: 0x8000320f <- 0xcff06f01 +mem-write: 0x80003213 <- 0x68d9384 +mem-write: 0x80003217 <- 0x4ff06f00 +mem-write: 0x8000321b <- 0xc1270384 +mem-write: 0x8000321f <- 0xd0079301 +mem-write: 0x80003223 <- 0xf74463ff +mem-write: 0x80003227 <- 0xedda6300 +mem-write: 0x8000322b <- 0xe4849300 +mem-write: 0x8000322f <- 0xf4f793ff +mem-write: 0x80003233 <- 0xf12223fd +mem-write: 0x80003237 <- 0xcfe06f04 +mem-write: 0x8000323b <- 0x12783bb +mem-write: 0x8000323f <- 0xc1270302 +mem-write: 0x80003243 <- 0xf7406301 +mem-write: 0x80003247 <- 0x8127832a +mem-write: 0x8000324b <- 0x70c9302 +mem-write: 0x8000324f <- 0x17f79300 +mem-write: 0x80003253 <- 0x7866300 +mem-write: 0x80003257 <- 0xc1278300 +mem-write: 0x8000325b <- 0xf70cb302 +mem-write: 0x8000325f <- 0x81278300 +mem-write: 0x80003263 <- 0x7f79302 +mem-write: 0x80003267 <- 0x7866340 +mem-write: 0x8000326b <- 0xc1278300 +mem-write: 0x8000326f <- 0xf0426301 +mem-write: 0x80003273 <- 0xfcca935c +mem-write: 0x80003277 <- 0xfada93ff +mem-write: 0x8000327b <- 0x5cfab341 +mem-write: 0x8000327f <- 0x70049301 +mem-write: 0x80003283 <- 0x1242306 +mem-write: 0x80003287 <- 0x1222302 +mem-write: 0x8000328b <- 0x4fe06f02 +mem-write: 0x8000328f <- 0x714783c8 +mem-write: 0x80003293 <- 0xd930c +mem-write: 0x80003297 <- 0x7846300 +mem-write: 0x8000329b <- 0xfe06f00 +mem-write: 0x8000329f <- 0x9fd06fec +mem-write: 0x800032a3 <- 0x900793f1 +mem-write: 0x800032a7 <- 0x97e66300 +mem-write: 0x800032ab <- 0xff06fd4 +mem-write: 0x800032af <- 0x12b83d9 +mem-write: 0x800032b3 <- 0xb0c1301 +mem-write: 0x800032b7 <- 0xdfe06f00 +mem-write: 0x800032bb <- 0x412423cf +mem-write: 0x800032bf <- 0x1282303 +mem-write: 0x800032c3 <- 0x90a1300 +mem-write: 0x800032c7 <- 0x7b700 +mem-write: 0x800032cb <- 0x67c33380 +mem-write: 0x800032cf <- 0xd0079300 +mem-write: 0x800032d3 <- 0xf12c2302 +mem-write: 0x800032d7 <- 0x9ff06f04 +mem-write: 0x800032db <- 0x410613b9 +mem-write: 0x800032df <- 0xb05930e +mem-write: 0x800032e3 <- 0xd051300 +mem-write: 0x800032e7 <- 0xd080ef00 +mem-write: 0x800032eb <- 0x512e363 +mem-write: 0x800032ef <- 0x44683fc +mem-write: 0x800032f3 <- 0xc1278300 +mem-write: 0x800032f7 <- 0xc108930e +mem-write: 0x800032fb <- 0xdd8db310 +mem-write: 0x800032ff <- 0x1ff06f00 +mem-write: 0x80003303 <- 0x10a938f +mem-write: 0x80003307 <- 0x107930b +mem-write: 0x8000330b <- 0xc108130d +mem-write: 0x8000330f <- 0xc107130d +mem-write: 0x80003313 <- 0xd86930c +mem-write: 0x80003317 <- 0x20061300 +mem-write: 0x8000331b <- 0xa859300 +mem-write: 0x8000331f <- 0xd051300 +mem-write: 0x80003323 <- 0xc1282300 +mem-write: 0x80003327 <- 0xc120230b +mem-write: 0x8000332b <- 0xd12a2305 +mem-write: 0x8000332f <- 0xd122230b +mem-write: 0x80003333 <- 0xe12c2303 +mem-write: 0x80003337 <- 0xe120230b +mem-write: 0x8000333b <- 0x612e2303 +mem-write: 0x8000333f <- 0x612e230a +mem-write: 0x80003343 <- 0x1020ef00 +mem-write: 0x80003347 <- 0x7007936f +mem-write: 0x8000334b <- 0xc1230304 +mem-write: 0x8000334f <- 0x12f0301 +mem-write: 0x80003353 <- 0x412e8302 +mem-write: 0x80003357 <- 0x12e0302 +mem-write: 0x8000335b <- 0x1288304 +mem-write: 0x8000335f <- 0x50b1305 +mem-write: 0x80003363 <- 0xfb906300 +mem-write: 0x80003367 <- 0x81278308 +mem-write: 0x8000336b <- 0x17f79302 +mem-write: 0x8000336f <- 0x7966300 +mem-write: 0x80003373 <- 0x7007932e +mem-write: 0x80003377 <- 0xc1270304 +mem-write: 0x8000337b <- 0xf122230d +mem-write: 0x8000337f <- 0x4fe06f04 +mem-write: 0x80003383 <- 0x10a93a4 +mem-write: 0x80003387 <- 0xc108130b +mem-write: 0x8000338b <- 0x107930d +mem-write: 0x8000338f <- 0xc107130d +mem-write: 0x80003393 <- 0xd86930c +mem-write: 0x80003397 <- 0x30061300 +mem-write: 0x8000339b <- 0xa859300 +mem-write: 0x8000339f <- 0xd051300 +mem-write: 0x800033a3 <- 0x11282300 +mem-write: 0x800033a7 <- 0xc1282305 +mem-write: 0x800033ab <- 0xc120230b +mem-write: 0x800033af <- 0xd12a2305 +mem-write: 0x800033b3 <- 0xd122230b +mem-write: 0x800033b7 <- 0xe12c2303 +mem-write: 0x800033bb <- 0xe120230b +mem-write: 0x800033bf <- 0x612e2303 +mem-write: 0x800033c3 <- 0x612e230a +mem-write: 0x800033c7 <- 0xd020ef00 +mem-write: 0x800033cb <- 0xc1230366 +mem-write: 0x800033cf <- 0x12f0301 +mem-write: 0x800033d3 <- 0x412e8302 +mem-write: 0x800033d7 <- 0x12e0302 +mem-write: 0x800033db <- 0x1288304 +mem-write: 0x800033df <- 0x50b1305 +mem-write: 0x800033e3 <- 0x60079300 +mem-write: 0x800033e7 <- 0xbb093304 +mem-write: 0x800033eb <- 0xfb9e6301 +mem-write: 0x800033ef <- 0xb468326 +mem-write: 0x800033f3 <- 0x79300 +mem-write: 0x800033f7 <- 0xf6866303 +mem-write: 0x800033fb <- 0x10c9350 +VXDRV: upload 1024 bytes to 0x800033ff +mem-write: 0x800033ff <- 0xc127830a +mem-write: 0x80003403 <- 0xf909330c +mem-write: 0x80003407 <- 0xfe06f00 +mem-write: 0x8000340b <- 0xd0079396 +mem-write: 0x8000340f <- 0xf103a302 +mem-write: 0x80003413 <- 0xff06f0c +mem-write: 0x80003417 <- 0x410613da +mem-write: 0x8000341b <- 0xc05930e +mem-write: 0x8000341f <- 0xd051300 +mem-write: 0x80003423 <- 0x1080ef00 +mem-write: 0x80003427 <- 0x5046350 +mem-write: 0x8000342b <- 0x5fe06f00 +mem-write: 0x8000342f <- 0xc12483b8 +mem-write: 0x80003433 <- 0xc127830c +mem-write: 0x80003437 <- 0xc108930e +mem-write: 0x8000343b <- 0x9fe06f10 +mem-write: 0x8000343f <- 0x714783e6 +mem-write: 0x80003443 <- 0x212a230c +mem-write: 0x80003447 <- 0x1242301 +mem-write: 0x8000344b <- 0x1222302 +mem-write: 0x8000344f <- 0x12e2302 +mem-write: 0x80003453 <- 0xd8a9300 +mem-write: 0x80003457 <- 0xd8c9300 +mem-write: 0x8000345b <- 0xd9300 +mem-write: 0x8000345f <- 0x7846300 +mem-write: 0x80003463 <- 0x8fe06f00 +mem-write: 0x80003467 <- 0x1fd06fcf +mem-write: 0x8000346b <- 0x812783d5 +mem-write: 0x8000346f <- 0xc1270302 +mem-write: 0x80003473 <- 0x17f79301 +mem-write: 0x80003477 <- 0xb7e7b300 +mem-write: 0x8000347b <- 0xe0566301 +mem-write: 0x8000347f <- 0x7906350 +mem-write: 0x80003483 <- 0xc12c8344 +mem-write: 0x80003487 <- 0x60049301 +mem-write: 0x8000348b <- 0x81278306 +mem-write: 0x8000348f <- 0x7f79302 +mem-write: 0x80003493 <- 0x7926340 +mem-write: 0x80003497 <- 0xfcca933a +mem-write: 0x8000349b <- 0xfada93ff +mem-write: 0x8000349f <- 0x5cfab341 +mem-write: 0x800034a3 <- 0x1ff06f01 +mem-write: 0x800034a7 <- 0x15737de +mem-write: 0x800034ab <- 0x470b1380 +mem-write: 0x800034af <- 0x4ff06fa3 +mem-write: 0x800034b3 <- 0x410613d1 +mem-write: 0x800034b7 <- 0xc05930e +mem-write: 0x800034bb <- 0xd051300 +mem-write: 0x800034bf <- 0x5080ef00 +mem-write: 0x800034c3 <- 0x5046346 +mem-write: 0x800034c7 <- 0x9fe06f00 +mem-write: 0x800034cb <- 0xc12483ae +mem-write: 0x800034cf <- 0x127030c +mem-write: 0x800034d3 <- 0xc1278302 +mem-write: 0x800034d7 <- 0xc108930e +mem-write: 0x800034db <- 0x9704b310 +mem-write: 0x800034df <- 0x1fe06f40 +mem-write: 0x800034e3 <- 0x12783e1 +mem-write: 0x800034e7 <- 0xc1270302 +mem-write: 0x800034eb <- 0x70049302 +mem-write: 0x800034ef <- 0xe78cb306 +mem-write: 0x800034f3 <- 0xc1278300 +mem-write: 0x800034f7 <- 0xf04ae301 +mem-write: 0x800034fb <- 0xfc8cb3f8 +mem-write: 0x800034ff <- 0x1c8c9340 +mem-write: 0x80003503 <- 0xfcca9300 +mem-write: 0x80003507 <- 0xfada93ff +mem-write: 0x8000350b <- 0x5cfab341 +mem-write: 0x8000350f <- 0x5ff06f01 +mem-write: 0x80003513 <- 0x156b7d7 +mem-write: 0x80003517 <- 0x868e9380 +mem-write: 0x8000351b <- 0xfe06fbd +mem-write: 0x8000351f <- 0xf00793b5 +mem-write: 0x80003523 <- 0xf12623ff +mem-write: 0x80003527 <- 0xdfd06f00 +mem-write: 0x8000352b <- 0x613dc +mem-write: 0x8000352f <- 0xb004b3ff +mem-write: 0x80003533 <- 0xc5d26340 +mem-write: 0x80003537 <- 0x91306 +mem-write: 0x8000353b <- 0x700c9301 +mem-write: 0x8000353f <- 0xc0006f00 +mem-write: 0x80003543 <- 0x4849300 +mem-write: 0x80003547 <- 0x995863ff +mem-write: 0x8000354b <- 0x81270304 +mem-write: 0x8000354f <- 0x7879300 +mem-write: 0x80003553 <- 0x16869301 +mem-write: 0x80003557 <- 0xe8a02300 +mem-write: 0x8000355b <- 0x28a22300 +mem-write: 0x8000355f <- 0xf1262301 +mem-write: 0x80003563 <- 0xd124230e +mem-write: 0x80003567 <- 0x8888930e +mem-write: 0x8000356b <- 0xdcdce300 +mem-write: 0x8000356f <- 0x410613fc +mem-write: 0x80003573 <- 0xc05930e +mem-write: 0x80003577 <- 0xd051300 +mem-write: 0x8000357b <- 0x9080ef00 +mem-write: 0x8000357f <- 0x504633a +mem-write: 0x80003583 <- 0xdfe06f00 +mem-write: 0x80003587 <- 0xc12783a2 +mem-write: 0x8000358b <- 0x8126830e +mem-write: 0x8000358f <- 0xc108930e +mem-write: 0x80003593 <- 0x1ff06f10 +mem-write: 0x80003597 <- 0x812703fb +mem-write: 0x8000359b <- 0x9787b300 +mem-write: 0x8000359f <- 0x16869300 +mem-write: 0x800035a3 <- 0xe8a02300 +mem-write: 0x800035a7 <- 0x98a22300 +mem-write: 0x800035ab <- 0xf1262300 +mem-write: 0x800035af <- 0xd124230e +mem-write: 0x800035b3 <- 0x7006130e +mem-write: 0x800035b7 <- 0xd65a6300 +mem-write: 0x800035bb <- 0x410613b2 +mem-write: 0x800035bf <- 0xc05930e +mem-write: 0x800035c3 <- 0xd051300 +mem-write: 0x800035c7 <- 0xd080ef00 +mem-write: 0x800035cb <- 0x5046335 +mem-write: 0x800035cf <- 0x1fe06f00 +mem-write: 0x800035d3 <- 0xc127839e +mem-write: 0x800035d7 <- 0x8126830e +mem-write: 0x800035db <- 0xc108930e +mem-write: 0x800035df <- 0xcfe06f10 +mem-write: 0x800035e3 <- 0xa0b939c +mem-write: 0x800035e7 <- 0xfe06f00 +mem-write: 0x800035eb <- 0x412783e2 +mem-write: 0x800035ef <- 0xb869305 +mem-write: 0x800035f3 <- 0xf12e2300 +mem-write: 0x800035f7 <- 0x4127830c +mem-write: 0x800035fb <- 0xfbc60302 +mem-write: 0x800035ff <- 0xf7c583ff +mem-write: 0x80003603 <- 0xb6106300 +mem-write: 0x80003607 <- 0x51302 +mem-write: 0x8000360b <- 0xa68fa303 +mem-write: 0x8000360f <- 0xc12683fe +mem-write: 0x80003613 <- 0xf687930d +mem-write: 0x80003617 <- 0xf12e23ff +mem-write: 0x8000361b <- 0xf6c6030c +mem-write: 0x8000361f <- 0xc586e3ff +mem-write: 0x80003623 <- 0x160593fe +mem-write: 0x80003627 <- 0x90051300 +mem-write: 0x8000362b <- 0xf5f59303 +mem-write: 0x8000362f <- 0xa606630f +mem-write: 0x80003633 <- 0xb68fa300 +mem-write: 0x80003637 <- 0x5ff06ffe +mem-write: 0x8000363b <- 0x412783ba +mem-write: 0x8000363f <- 0xa7c58302 +mem-write: 0x80003643 <- 0xb68fa300 +mem-write: 0x80003647 <- 0x5ff06ffe +mem-write: 0x8000364b <- 0x793b9 +mem-write: 0x8000364f <- 0xf1042303 +mem-write: 0x80003653 <- 0x8007930c +mem-write: 0x80003657 <- 0x8ff06f07 +mem-write: 0x8000365b <- 0x700793fd +mem-write: 0x8000365f <- 0xbb093304 +mem-write: 0x80003663 <- 0xf1222301 +mem-write: 0x80003667 <- 0x10c9304 +mem-write: 0x8000366b <- 0xdfd06f0a +mem-write: 0x8000366f <- 0x1d8593ef +mem-write: 0x80003673 <- 0xd051300 +mem-write: 0x80003677 <- 0x11282300 +mem-write: 0x8000367b <- 0xc040ef01 +mem-write: 0x8000367f <- 0x128830b +mem-write: 0x80003683 <- 0x50b1301 +mem-write: 0x80003687 <- 0x5006300 +mem-write: 0x8000368b <- 0xa1282336 +mem-write: 0x8000368f <- 0xcff06f00 +mem-write: 0x80003693 <- 0xd9463fb +mem-write: 0x80003697 <- 0x100d9300 +mem-write: 0x8000369b <- 0xc1230300 +mem-write: 0x8000369f <- 0x12e030f +mem-write: 0x800036a3 <- 0x412e830f +mem-write: 0x800036a7 <- 0x812f030f +mem-write: 0x800036ab <- 0xa69130f +mem-write: 0x800036af <- 0x346e310 +mem-write: 0x800036b3 <- 0x10a93c0 +mem-write: 0x800036b7 <- 0xc108130b +mem-write: 0x800036bb <- 0x107930d +mem-write: 0x800036bf <- 0xc107130d +mem-write: 0x800036c3 <- 0xd86930c +mem-write: 0x800036c7 <- 0x20061300 +mem-write: 0x800036cb <- 0xa859300 +mem-write: 0x800036cf <- 0xd051300 +mem-write: 0x800036d3 <- 0x11222300 +mem-write: 0x800036d7 <- 0xc1282305 +mem-write: 0x800036db <- 0xc120230b +mem-write: 0x800036df <- 0xd12a2305 +mem-write: 0x800036e3 <- 0xd122230b +mem-write: 0x800036e7 <- 0xe12c2303 +mem-write: 0x800036eb <- 0xe120230b +mem-write: 0x800036ef <- 0x612e2303 +mem-write: 0x800036f3 <- 0x612e230a +mem-write: 0x800036f7 <- 0xd020ef00 +mem-write: 0x800036fb <- 0xc1230333 +mem-write: 0x800036ff <- 0x41242301 +mem-write: 0x80003703 <- 0x12f0303 +mem-write: 0x80003707 <- 0x412e8302 +mem-write: 0x8000370b <- 0x12e0302 +mem-write: 0x8000370f <- 0x41288304 +mem-write: 0x80003713 <- 0x50b1304 +mem-write: 0x80003717 <- 0x90a1300 +mem-write: 0x8000371b <- 0x12c2300 +mem-write: 0x8000371f <- 0x1282304 +mem-write: 0x80003723 <- 0x5ff06f00 +mem-write: 0x80003727 <- 0x600d93c4 +mem-write: 0x8000372b <- 0xdfd06f00 +mem-write: 0x8000372f <- 0x10a93d8 +mem-write: 0x80003733 <- 0xa85130b +mem-write: 0x80003737 <- 0x112a2300 +mem-write: 0x8000373b <- 0xc1282305 +mem-write: 0x8000373f <- 0xd12a230b +mem-write: 0x80003743 <- 0xe12c230b +mem-write: 0x80003747 <- 0x612e230b +mem-write: 0x8000374b <- 0x5100ef0a +mem-write: 0x8000374f <- 0xc1061365 +mem-write: 0x80003753 <- 0x5050ef0c +mem-write: 0x80003757 <- 0x586131a +mem-write: 0x8000375b <- 0x5059300 +mem-write: 0x8000375f <- 0xa851300 +mem-write: 0x80003763 <- 0x9100ef00 +mem-write: 0x80003767 <- 0x1278344 +mem-write: 0x8000376b <- 0x10c930b +mem-write: 0x8000376f <- 0x109130a +mem-write: 0x80003773 <- 0xf1282309 +mem-write: 0x80003777 <- 0x41278308 +mem-write: 0x8000377b <- 0x106130b +mem-write: 0x8000377f <- 0x9059308 +mem-write: 0x80003783 <- 0xf12a2300 +mem-write: 0x80003787 <- 0x81278308 +mem-write: 0x8000378b <- 0xc85130b +mem-write: 0x8000378f <- 0xc1202300 +mem-write: 0x80003793 <- 0xf12c2304 +mem-write: 0x80003797 <- 0xc1278308 +mem-write: 0x8000379b <- 0x120230b +mem-write: 0x8000379f <- 0x1222308 +mem-write: 0x800037a3 <- 0xf12e2308 +mem-write: 0x800037a7 <- 0xfc07b708 +mem-write: 0x800037ab <- 0xf126233f +mem-write: 0x800037af <- 0x1242308 +mem-write: 0x800037b3 <- 0xe0ef08 +mem-write: 0x800037b7 <- 0x1280347 +mem-write: 0x800037bb <- 0x412e030a +mem-write: 0x800037bf <- 0x812e830a +mem-write: 0x800037c3 <- 0xc12f030a +mem-write: 0x800037c7 <- 0xc85930a +mem-write: 0x800037cb <- 0xa851300 +mem-write: 0x800037cf <- 0x1282300 +mem-write: 0x800037d3 <- 0x128230b +mem-write: 0x800037d7 <- 0xc12a2305 +mem-write: 0x800037db <- 0xc122230b +mem-write: 0x800037df <- 0xd12c2303 +mem-write: 0x800037e3 <- 0xd120230b +mem-write: 0x800037e7 <- 0xe12e2303 +mem-write: 0x800037eb <- 0xe12e230b +mem-write: 0x800037ef <- 0x1202301 +mem-write: 0x800037f3 <- 0x122230a +mem-write: 0x800037f7 <- 0x124230a +mem-write: 0x800037fb <- 0x126230a +VXDRV: upload 1024 bytes to 0x800037ff +mem-write: 0x800037ff <- 0xe0ef0a +mem-write: 0x80003803 <- 0xc12f030d +mem-write: 0x80003807 <- 0x12e8301 +mem-write: 0x8000380b <- 0x412e0302 +mem-write: 0x8000380f <- 0x1280302 +mem-write: 0x80003813 <- 0x41288305 +mem-write: 0x80003817 <- 0x5166305 +mem-write: 0x8000381b <- 0x10079300 +mem-write: 0x8000381f <- 0xf1262300 +mem-write: 0x80003823 <- 0x157b70c +mem-write: 0x80003827 <- 0xc7879380 +mem-write: 0x8000382b <- 0xf12223a3 +mem-write: 0x8000382f <- 0x4ff06f02 +mem-write: 0x80003833 <- 0x700493f5 +mem-write: 0x80003837 <- 0xc1260306 +mem-write: 0x8000383b <- 0xf0069303 +mem-write: 0x8000383f <- 0x647830f +mem-write: 0x80003843 <- 0xd78a6300 +mem-write: 0x80003847 <- 0xc127031a +mem-write: 0x8000384b <- 0x51301 +mem-write: 0x8000384f <- 0x59300 +mem-write: 0x80003853 <- 0xe7de6300 +mem-write: 0x80003857 <- 0xf7073300 +mem-write: 0x8000385b <- 0x16478340 +mem-write: 0x8000385f <- 0x7846300 +mem-write: 0x80003863 <- 0x15859304 +mem-write: 0x80003867 <- 0x16061300 +mem-write: 0x8000386b <- 0xd794e300 +mem-write: 0x8000386f <- 0xc12e23fe +mem-write: 0x80003873 <- 0xe12e2302 +mem-write: 0x80003877 <- 0xb1222300 +mem-write: 0x8000387b <- 0xa1242302 +mem-write: 0x8000387f <- 0x81270302 +mem-write: 0x80003883 <- 0x41278302 +mem-write: 0x80003887 <- 0xe787b302 +mem-write: 0x8000388b <- 0x81270300 +mem-write: 0x8000388f <- 0xe787b304 +mem-write: 0x80003893 <- 0x978cb302 +mem-write: 0x80003897 <- 0xfcca9301 +mem-write: 0x8000389b <- 0xfada93ff +mem-write: 0x8000389f <- 0x5cfab341 +mem-write: 0x800038a3 <- 0xdfd06f01 +mem-write: 0x800038a7 <- 0x64783e6 +mem-write: 0x800038ab <- 0x15051300 +mem-write: 0x800038af <- 0xdff06f00 +mem-write: 0x800038b3 <- 0x12823fb +mem-write: 0x800038b7 <- 0x78a1300 +mem-write: 0x800038bb <- 0xdff06f00 +mem-write: 0x800038bf <- 0xc12783a0 +mem-write: 0x800038c3 <- 0x60049302 +mem-write: 0x800038c7 <- 0xf70cb306 +mem-write: 0x800038cb <- 0xbc8cb300 +mem-write: 0x800038cf <- 0xdff06f01 +mem-write: 0x800038d3 <- 0x610693bb +mem-write: 0x800038d7 <- 0x618630d +mem-write: 0x800038db <- 0x69300 +mem-write: 0x800038df <- 0xd10b2303 +mem-write: 0x800038e3 <- 0x7106930c +mem-write: 0x800038e7 <- 0x107130d +mem-write: 0x800038eb <- 0x787931b +mem-write: 0x800038ef <- 0xe6863303 +mem-write: 0x800038f3 <- 0xf6802340 +mem-write: 0x800038f7 <- 0xd6079300 +mem-write: 0x800038fb <- 0xf12c230d +mem-write: 0x800038ff <- 0xdfd06f02 +mem-write: 0x80003903 <- 0x10c93dc +mem-write: 0x80003907 <- 0xc85930a +mem-write: 0x8000390b <- 0xa851300 +mem-write: 0x8000390f <- 0x11282300 +mem-write: 0x80003913 <- 0xc1282305 +mem-write: 0x80003917 <- 0xc120230b +mem-write: 0x8000391b <- 0xd12a2305 +mem-write: 0x8000391f <- 0xd122230b +mem-write: 0x80003923 <- 0xe12c2303 +mem-write: 0x80003927 <- 0xe120230b +mem-write: 0x8000392b <- 0x612e2303 +mem-write: 0x8000392f <- 0x612e230a +mem-write: 0x80003933 <- 0x1202300 +mem-write: 0x80003937 <- 0x122230a +mem-write: 0x8000393b <- 0x124230a +mem-write: 0x8000393f <- 0x126230a +mem-write: 0x80003943 <- 0xd0d0ef0a +mem-write: 0x80003947 <- 0xc1230378 +mem-write: 0x8000394b <- 0x12f0301 +mem-write: 0x8000394f <- 0x412e8302 +mem-write: 0x80003953 <- 0x12e0302 +mem-write: 0x80003957 <- 0x1288304 +mem-write: 0x8000395b <- 0x502e305 +mem-write: 0x8000395f <- 0x100793aa +mem-write: 0x80003963 <- 0xb787b300 +mem-write: 0x80003967 <- 0xf1262341 +mem-write: 0x8000396b <- 0xf909330c +mem-write: 0x8000396f <- 0x9fd06f00 +mem-write: 0x80003973 <- 0x812783bf +mem-write: 0x80003977 <- 0x17f79302 +mem-write: 0x8000397b <- 0x7946300 +mem-write: 0x8000397f <- 0xdfd06f00 +mem-write: 0x80003983 <- 0x1fd06fd6 +mem-write: 0x80003987 <- 0x79a63d6 +mem-write: 0x8000398b <- 0x100a9300 +mem-write: 0x8000398f <- 0x60049300 +mem-write: 0x80003993 <- 0x100c9306 +mem-write: 0x80003997 <- 0xdff06f00 +mem-write: 0x8000399b <- 0xc127838e +mem-write: 0x8000399f <- 0x60049302 +mem-write: 0x800039a3 <- 0x178c9306 +mem-write: 0x800039a7 <- 0xbc8cb300 +mem-write: 0x800039ab <- 0xfcca9301 +mem-write: 0x800039af <- 0xfada93ff +mem-write: 0x800039b3 <- 0x5cfab341 +mem-write: 0x800039b7 <- 0xdff06f01 +mem-write: 0x800039bb <- 0x887138c +mem-write: 0x800039bf <- 0xdfe06f00 +mem-write: 0x800039c3 <- 0x412783bd +mem-write: 0x800039c7 <- 0x7ad8301 +mem-write: 0x800039cb <- 0x47879300 +mem-write: 0x800039cf <- 0xdd46300 +mem-write: 0x800039d3 <- 0xf00d9300 +mem-write: 0x800039d7 <- 0x144483ff +mem-write: 0x800039db <- 0xf12a2300 +mem-write: 0x800039df <- 0x7041300 +mem-write: 0x800039e3 <- 0x4fd06f00 +mem-write: 0x800039e7 <- 0xcc5783f5 +mem-write: 0x800039eb <- 0x7e79300 +mem-write: 0x800039ef <- 0xfc162304 +mem-write: 0x800039f3 <- 0x1fd06f00 +mem-write: 0x800039f7 <- 0x124238f +mem-write: 0x800039fb <- 0x1222302 +mem-write: 0x800039ff <- 0x1ff06f02 +mem-write: 0x80003a03 <- 0x200793e8 +mem-write: 0x80003a07 <- 0xf12c2300 +mem-write: 0x80003a0b <- 0x1fd06f02 +mem-write: 0x80003a0f <- 0x50793cc +mem-write: 0x80003a13 <- 0x81a50300 +mem-write: 0x80003a17 <- 0x606931d +mem-write: 0x80003a1b <- 0x5861300 +mem-write: 0x80003a1f <- 0x7859300 +mem-write: 0x80003a23 <- 0xcfd06f00 +mem-write: 0x80003a27 <- 0xc5d783d5 +mem-write: 0x80003a2b <- 0x45ae0300 +mem-write: 0x80003a2f <- 0xe5d30306 +mem-write: 0x80003a33 <- 0xc5a88300 +mem-write: 0x80003a37 <- 0x45a80301 +mem-write: 0x80003a3b <- 0x1011302 +mem-write: 0x80003a3f <- 0xd7f793b8 +mem-write: 0x80003a43 <- 0x713ff +mem-write: 0x80003a47 <- 0x812c2340 +mem-write: 0x80003a4b <- 0xf11a2346 +mem-write: 0x80003a4f <- 0x5841300 +mem-write: 0x80003a53 <- 0x1079300 +mem-write: 0x80003a57 <- 0x81059307 +mem-write: 0x80003a5b <- 0x912a2300 +mem-write: 0x80003a5f <- 0x21282346 +mem-write: 0x80003a63 <- 0x112e2347 +mem-write: 0x80003a67 <- 0x5091346 +mem-write: 0x80003a6b <- 0xc1262300 +mem-write: 0x80003a6f <- 0x611b2307 +mem-write: 0x80003a73 <- 0x11222300 +mem-write: 0x80003a77 <- 0x1262303 +mem-write: 0x80003a7b <- 0xf1242303 +mem-write: 0x80003a7f <- 0xf12c2300 +mem-write: 0x80003a83 <- 0xe1282300 +mem-write: 0x80003a87 <- 0xe12e2300 +mem-write: 0x80003a8b <- 0x1202300 +mem-write: 0x80003a8f <- 0xfd0ef02 +mem-write: 0x80003a93 <- 0x50493cf +mem-write: 0x80003a97 <- 0x55c6300 +mem-write: 0x80003a9b <- 0x41578302 +mem-write: 0x80003a9f <- 0x7f79301 +mem-write: 0x80003aa3 <- 0x7886304 +mem-write: 0x80003aa7 <- 0xc4578300 +mem-write: 0x80003aab <- 0x7e79300 +mem-write: 0x80003aaf <- 0xf4162304 +mem-write: 0x80003ab3 <- 0xc1208300 +mem-write: 0x80003ab7 <- 0x81240347 +mem-write: 0x80003abb <- 0x1290347 +mem-write: 0x80003abf <- 0x4851347 +mem-write: 0x80003ac3 <- 0x41248300 +mem-write: 0x80003ac7 <- 0x1011347 +mem-write: 0x80003acb <- 0x806748 +mem-write: 0x80003acf <- 0x81059300 +mem-write: 0x80003ad3 <- 0x9051300 +mem-write: 0x80003ad7 <- 0xef00 +mem-write: 0x80003adb <- 0x500e358 +mem-write: 0x80003adf <- 0xf00493fc +mem-write: 0x80003ae3 <- 0x9ff06fff +mem-write: 0x80003ae7 <- 0x81a783fb +mem-write: 0x80003aeb <- 0x101131d +mem-write: 0x80003aef <- 0x812423ff +mem-write: 0x80003af3 <- 0x91222300 +mem-write: 0x80003af7 <- 0x11262300 +mem-write: 0x80003afb <- 0x5049300 +mem-write: 0x80003aff <- 0x5841300 +mem-write: 0x80003b03 <- 0x7866300 +mem-write: 0x80003b07 <- 0x87a70300 +mem-write: 0x80003b0b <- 0x7006303 +mem-write: 0x80003b0f <- 0xc417030e +mem-write: 0x80003b13 <- 0x7179300 +mem-write: 0x80003b17 <- 0x87769301 +mem-write: 0x80003b1b <- 0x7d79300 +mem-write: 0x80003b1f <- 0x6806301 +mem-write: 0x80003b23 <- 0x4268304 +mem-write: 0x80003b27 <- 0x6806301 +mem-write: 0x80003b2b <- 0x17f61306 +mem-write: 0x80003b2f <- 0x6046300 +mem-write: 0x80003b33 <- 0x44260308 +mem-write: 0x80003b37 <- 0x4242301 +mem-write: 0x80003b3b <- 0x51300 +mem-write: 0x80003b3f <- 0xc0063300 +mem-write: 0x80003b43 <- 0xc42c2340 +mem-write: 0x80003b47 <- 0x6866300 +mem-write: 0x80003b4b <- 0xc1208308 +mem-write: 0x80003b4f <- 0x81240300 +mem-write: 0x80003b53 <- 0x41248300 +mem-write: 0x80003b57 <- 0x1011300 +mem-write: 0x80003b5b <- 0x806701 +mem-write: 0x80003b5f <- 0x7f69300 +mem-write: 0x80003b63 <- 0x6846301 +mem-write: 0x80003b67 <- 0x47f7930c +mem-write: 0x80003b6b <- 0x7966300 +mem-write: 0x80003b6f <- 0x4268308 +mem-write: 0x80003b73 <- 0x87671301 +mem-write: 0x80003b77 <- 0x7179300 +mem-write: 0x80003b7b <- 0xe4162301 +mem-write: 0x80003b7f <- 0x7d79300 +mem-write: 0x80003b83 <- 0x694e301 +mem-write: 0x80003b87 <- 0x7f613fa +mem-write: 0x80003b8b <- 0x59328 +mem-write: 0x80003b8f <- 0xb60ee320 +mem-write: 0x80003b93 <- 0x40593f8 +mem-write: 0x80003b97 <- 0x4851300 +mem-write: 0x80003b9b <- 0xd030ef00 +mem-write: 0x80003b9f <- 0xc4170327 +mem-write: 0x80003ba3 <- 0x4268300 +mem-write: 0x80003ba7 <- 0x7179301 +mem-write: 0x80003bab <- 0x7d79301 +mem-write: 0x80003baf <- 0x17f61301 +mem-write: 0x80003bb3 <- 0x610e300 +mem-write: 0x80003bb7 <- 0x27f613f8 +mem-write: 0x80003bbb <- 0x59300 +mem-write: 0x80003bbf <- 0x6146300 +mem-write: 0x80003bc3 <- 0x44258300 +mem-write: 0x80003bc7 <- 0xb4242301 +mem-write: 0x80003bcb <- 0x51300 +mem-write: 0x80003bcf <- 0x69ee300 +mem-write: 0x80003bd3 <- 0x7f793f6 +mem-write: 0x80003bd7 <- 0x78ae308 +mem-write: 0x80003bdb <- 0x76713f6 +mem-write: 0x80003bdf <- 0xe4162304 +mem-write: 0x80003be3 <- 0xf0051300 +mem-write: 0x80003be7 <- 0x5ff06fff +mem-write: 0x80003beb <- 0x78513f6 +mem-write: 0x80003bef <- 0x5000ef00 +mem-write: 0x80003bf3 <- 0xdff06f00 +mem-write: 0x80003bf7 <- 0x42583f1 +mem-write: 0x80003bfb <- 0x58e6303 +VXDRV: upload 1023 bytes to 0x80003bff +mem-write: 0x80003bff <- 0x4079300 +mem-write: 0x80003c03 <- 0xf5886304 +mem-write: 0x80003c07 <- 0x4851300 +mem-write: 0x80003c0b <- 0x9000ef00 +mem-write: 0x80003c0f <- 0xc4170315 +mem-write: 0x80003c13 <- 0x4282300 +mem-write: 0x80003c17 <- 0x4268302 +mem-write: 0x80003c1b <- 0xb7771301 +mem-write: 0x80003c1f <- 0x42223fd +mem-write: 0x80003c23 <- 0xd4202300 +mem-write: 0x80003c27 <- 0xdff06f00 +mem-write: 0x80003c2b <- 0x900793f4 +mem-write: 0x80003c2f <- 0xf4a02300 +mem-write: 0x80003c33 <- 0x7671300 +mem-write: 0x80003c37 <- 0xe4162304 +mem-write: 0x80003c3b <- 0xf0051300 +mem-write: 0x80003c3f <- 0xdff06fff +mem-write: 0x80003c43 <- 0x1a703f0 +mem-write: 0x80003c47 <- 0x8727831c +mem-write: 0x80003c4b <- 0x78c6314 +mem-write: 0x80003c4f <- 0x47a70304 +mem-write: 0x80003c53 <- 0xf0081300 +mem-write: 0x80003c57 <- 0xe84e6301 +mem-write: 0x80003c5b <- 0x27181306 +mem-write: 0x80003c5f <- 0x5066300 +mem-write: 0x80003c63 <- 0x7833302 +mem-write: 0x80003c67 <- 0xc3242301 +mem-write: 0x80003c6b <- 0x87a88308 +mem-write: 0x80003c6f <- 0x10061318 +mem-write: 0x80003c73 <- 0xe6163300 +mem-write: 0x80003c77 <- 0xc8e8b300 +mem-write: 0x80003c7b <- 0x17a42300 +mem-write: 0x80003c7f <- 0xd3242319 +mem-write: 0x80003c83 <- 0x20069310 +mem-write: 0x80003c87 <- 0xd5046300 +mem-write: 0x80003c8b <- 0x17071302 +mem-write: 0x80003c8f <- 0xe7a22300 +mem-write: 0x80003c93 <- 0x787b300 +mem-write: 0x80003c97 <- 0xb7a42301 +mem-write: 0x80003c9b <- 0x51300 +mem-write: 0x80003c9f <- 0x806700 +mem-write: 0x80003ca3 <- 0xc7079300 +mem-write: 0x80003ca7 <- 0xf7242314 +mem-write: 0x80003cab <- 0x5ff06f14 +mem-write: 0x80003caf <- 0xc7a683fa +mem-write: 0x80003cb3 <- 0x17071318 +mem-write: 0x80003cb7 <- 0xe7a22300 +mem-write: 0x80003cbb <- 0xc6e63300 +mem-write: 0x80003cbf <- 0xc7a62300 +mem-write: 0x80003cc3 <- 0x787b318 +mem-write: 0x80003cc7 <- 0xb7a42301 +mem-write: 0x80003ccb <- 0x51300 +mem-write: 0x80003ccf <- 0x806700 +mem-write: 0x80003cd3 <- 0xf0051300 +mem-write: 0x80003cd7 <- 0x8067ff +mem-write: 0x80003cdb <- 0x1011300 +mem-write: 0x80003cdf <- 0x412c23fd +mem-write: 0x80003ce3 <- 0x1aa0301 +mem-write: 0x80003ce7 <- 0x2120231c +mem-write: 0x80003ceb <- 0x11262303 +mem-write: 0x80003cef <- 0x8a290302 +mem-write: 0x80003cf3 <- 0x81242314 +mem-write: 0x80003cf7 <- 0x91222302 +mem-write: 0x80003cfb <- 0x312e2302 +mem-write: 0x80003cff <- 0x512a2301 +mem-write: 0x80003d03 <- 0x61282301 +mem-write: 0x80003d07 <- 0x71262301 +mem-write: 0x80003d0b <- 0x81242301 +mem-write: 0x80003d0f <- 0x9006301 +mem-write: 0x80003d13 <- 0x50b1304 +mem-write: 0x80003d17 <- 0x58b9300 +mem-write: 0x80003d1b <- 0x100a9300 +mem-write: 0x80003d1f <- 0xf0099300 +mem-write: 0x80003d23 <- 0x492483ff +mem-write: 0x80003d27 <- 0xf4841300 +mem-write: 0x80003d2b <- 0x44263ff +mem-write: 0x80003d2f <- 0x24949302 +mem-write: 0x80003d33 <- 0x9904b300 +mem-write: 0x80003d37 <- 0xb846300 +mem-write: 0x80003d3b <- 0x44a78304 +mem-write: 0x80003d3f <- 0x77806310 +mem-write: 0x80003d43 <- 0xf4041305 +mem-write: 0x80003d47 <- 0xc48493ff +mem-write: 0x80003d4b <- 0x3416e3ff +mem-write: 0x80003d4f <- 0xc12083ff +mem-write: 0x80003d53 <- 0x81240302 +mem-write: 0x80003d57 <- 0x41248302 +mem-write: 0x80003d5b <- 0x1290302 +mem-write: 0x80003d5f <- 0xc1298302 +mem-write: 0x80003d63 <- 0x812a0301 +mem-write: 0x80003d67 <- 0x412a8301 +mem-write: 0x80003d6b <- 0x12b0301 +mem-write: 0x80003d6f <- 0xc12b8301 +mem-write: 0x80003d73 <- 0x812c0300 +mem-write: 0x80003d77 <- 0x1011300 +mem-write: 0x80003d7b <- 0x806703 +mem-write: 0x80003d7f <- 0x49278300 +mem-write: 0x80003d83 <- 0x44a68300 +mem-write: 0x80003d87 <- 0xf7879300 +mem-write: 0x80003d8b <- 0x878e63ff +mem-write: 0x80003d8f <- 0x4a22304 +mem-write: 0x80003d93 <- 0x688e300 +mem-write: 0x80003d97 <- 0x892783fa +mem-write: 0x80003d9b <- 0x8a973318 +mem-write: 0x80003d9f <- 0x492c0300 +mem-write: 0x80003da3 <- 0xf777b300 +mem-write: 0x80003da7 <- 0x7926300 +mem-write: 0x80003dab <- 0x680e702 +mem-write: 0x80003daf <- 0x49270300 +mem-write: 0x80003db3 <- 0x8a278300 +mem-write: 0x80003db7 <- 0x87146314 +mem-write: 0x80003dbb <- 0xf904e301 +mem-write: 0x80003dbf <- 0x788e3f8 +mem-write: 0x80003dc3 <- 0x78913f8 +mem-write: 0x80003dc7 <- 0xdff06f00 +mem-write: 0x80003dcb <- 0xc92783f5 +mem-write: 0x80003dcf <- 0x44a58318 +mem-write: 0x80003dd3 <- 0xf7773308 +mem-write: 0x80003dd7 <- 0x71c6300 +mem-write: 0x80003ddb <- 0xb051300 +mem-write: 0x80003ddf <- 0x680e700 +mem-write: 0x80003de3 <- 0xdff06f00 +mem-write: 0x80003de7 <- 0x892223fc +mem-write: 0x80003deb <- 0x9ff06f00 +mem-write: 0x80003def <- 0x58513fa +mem-write: 0x80003df3 <- 0x680e700 +mem-write: 0x80003df7 <- 0x9ff06f00 +mem-write: 0x80003dfb <- 0xc59783fb +mem-write: 0x80003dff <- 0x1011300 +mem-write: 0x80003e03 <- 0x812c23fe +mem-write: 0x80003e07 <- 0x31262300 +mem-write: 0x80003e0b <- 0x112e2301 +mem-write: 0x80003e0f <- 0x912a2300 +mem-write: 0x80003e13 <- 0x21282300 +mem-write: 0x80003e17 <- 0x87f69301 +mem-write: 0x80003e1b <- 0x5841300 +mem-write: 0x80003e1f <- 0x5099300 +mem-write: 0x80003e23 <- 0x69a6300 +mem-write: 0x80003e27 <- 0x173710 +mem-write: 0x80003e2b <- 0x7071300 +mem-write: 0x80003e2f <- 0x45a68380 +mem-write: 0x80003e33 <- 0xe7e7b300 +mem-write: 0x80003e37 <- 0xf5962300 +mem-write: 0x80003e3b <- 0xd0546300 +mem-write: 0x80003e3f <- 0x84270318 +mem-write: 0x80003e43 <- 0x70a6302 +mem-write: 0x80003e47 <- 0x9a4830c +mem-write: 0x80003e4b <- 0x7969300 +mem-write: 0x80003e4f <- 0x9a02301 +mem-write: 0x80003e53 <- 0x37961300 +mem-write: 0x80003e57 <- 0xc4258301 +mem-write: 0x80003e5b <- 0x6d69301 +mem-write: 0x80003e5f <- 0x6486301 +mem-write: 0x80003e63 <- 0x10069316 +mem-write: 0x80003e67 <- 0x61300 +mem-write: 0x80003e6b <- 0x9851300 +mem-write: 0x80003e6f <- 0x700e700 +mem-write: 0x80003e73 <- 0xf0079300 +mem-write: 0x80003e77 <- 0xf50c63ff +mem-write: 0x80003e7b <- 0xc4568318 +mem-write: 0x80003e7f <- 0x84270300 +mem-write: 0x80003e83 <- 0xc4258302 +mem-write: 0x80003e87 <- 0x46f69301 +mem-write: 0x80003e8b <- 0x68e6300 +mem-write: 0x80003e8f <- 0x44268300 +mem-write: 0x80003e93 <- 0x4278300 +mem-write: 0x80003e97 <- 0xd5053303 +mem-write: 0x80003e9b <- 0x7866340 +mem-write: 0x80003e9f <- 0xc4278300 +mem-write: 0x80003ea3 <- 0xf5053303 +mem-write: 0x80003ea7 <- 0x5061340 +mem-write: 0x80003eab <- 0x69300 +mem-write: 0x80003eaf <- 0x9851300 +mem-write: 0x80003eb3 <- 0x700e700 +mem-write: 0x80003eb7 <- 0xf0079300 +mem-write: 0x80003ebb <- 0xf51e63ff +mem-write: 0x80003ebf <- 0x9a70310 +mem-write: 0x80003ec3 <- 0xc4178300 +mem-write: 0x80003ec7 <- 0x7086300 +mem-write: 0x80003ecb <- 0xd0069316 +mem-write: 0x80003ecf <- 0xd7066301 +mem-write: 0x80003ed3 <- 0x60069300 +mem-write: 0x80003ed7 <- 0xd7146301 +mem-write: 0x80003edb <- 0x426830c +mem-write: 0x80003edf <- 0xfff73701 +mem-write: 0x80003ee3 <- 0xf70713ff +mem-write: 0x80003ee7 <- 0xe7f7b37f +mem-write: 0x80003eeb <- 0xf4162300 +mem-write: 0x80003eef <- 0x4222300 +mem-write: 0x80003ef3 <- 0xd4202300 +mem-write: 0x80003ef7 <- 0x4258300 +mem-write: 0x80003efb <- 0x99a02303 +mem-write: 0x80003eff <- 0x58c6300 +mem-write: 0x80003f03 <- 0x4079300 +mem-write: 0x80003f07 <- 0xf5866304 +mem-write: 0x80003f0b <- 0x9851300 +mem-write: 0x80003f0f <- 0x4000ef00 +mem-write: 0x80003f13 <- 0x4282365 +mem-write: 0x80003f17 <- 0x51302 +mem-write: 0x80003f1b <- 0xc1208300 +mem-write: 0x80003f1f <- 0x81240301 +mem-write: 0x80003f23 <- 0x41248301 +mem-write: 0x80003f27 <- 0x1290301 +mem-write: 0x80003f2b <- 0xc1298301 +mem-write: 0x80003f2f <- 0x1011300 +mem-write: 0x80003f33 <- 0x806702 +mem-write: 0x80003f37 <- 0x5a90300 +mem-write: 0x80003f3b <- 0x90ee301 +mem-write: 0x80003f3f <- 0x5a483fc +mem-write: 0x80003f43 <- 0x7971300 +mem-write: 0x80003f47 <- 0x7571301 +mem-write: 0x80003f4b <- 0x37771301 +mem-write: 0x80003f4f <- 0x25a02300 +mem-write: 0x80003f53 <- 0x2484b301 +mem-write: 0x80003f57 <- 0x79341 +mem-write: 0x80003f5b <- 0x7146300 +mem-write: 0x80003f5f <- 0x45a78300 +mem-write: 0x80003f63 <- 0xf4242301 +mem-write: 0x80003f67 <- 0x90486300 +mem-write: 0x80003f6b <- 0xdff06f00 +mem-write: 0x80003f6f <- 0xa90933fa +mem-write: 0x80003f73 <- 0x9052e300 +mem-write: 0x80003f77 <- 0x442783fa +mem-write: 0x80003f7b <- 0xc4258302 +mem-write: 0x80003f7f <- 0x4869301 +mem-write: 0x80003f83 <- 0x9061300 +mem-write: 0x80003f87 <- 0x9851300 +mem-write: 0x80003f8b <- 0x780e700 +mem-write: 0x80003f8f <- 0xa484b300 +mem-write: 0x80003f93 <- 0xa04ee340 +mem-write: 0x80003f97 <- 0xc45783fc +mem-write: 0x80003f9b <- 0xf0051300 +mem-write: 0x80003f9f <- 0x7e793ff +mem-write: 0x80003fa3 <- 0xc1208304 +mem-write: 0x80003fa7 <- 0xf4162301 +mem-write: 0x80003fab <- 0x81240300 +mem-write: 0x80003faf <- 0x41248301 +mem-write: 0x80003fb3 <- 0x1290301 +mem-write: 0x80003fb7 <- 0xc1298301 +mem-write: 0x80003fbb <- 0x1011300 +mem-write: 0x80003fbf <- 0x806702 +mem-write: 0x80003fc3 <- 0xc5a70300 +mem-write: 0x80003fc7 <- 0xe04ce303 +mem-write: 0x80003fcb <- 0xdff06fe6 +mem-write: 0x80003fcf <- 0x42503f4 +mem-write: 0x80003fd3 <- 0x5ff06f05 +mem-write: 0x80003fd7 <- 0xc45783eb +mem-write: 0x80003fdb <- 0xfff73700 +mem-write: 0x80003fdf <- 0xf70713ff +mem-write: 0x80003fe3 <- 0xe7f7b37f +mem-write: 0x80003fe7 <- 0x4268300 +mem-write: 0x80003feb <- 0x7979301 +mem-write: 0x80003fef <- 0x7d79301 +mem-write: 0x80003ff3 <- 0xf4162341 +mem-write: 0x80003ff7 <- 0x4222300 +mem-write: 0x80003ffb <- 0x5202300 +VXDRV: upload 1024 bytes to 0x80003ffe +mem-write: 0x80003ffe <- 0x971300d4 +mem-write: 0x80004002 <- 0x5ae30137 +mem-write: 0x80004006 <- 0x2823ee07 +mem-write: 0x8000400a <- 0xf06f04a4 +mem-write: 0x8000400e <- 0xa783eedf +mem-write: 0x80004012 <- 0x84e30009 +mem-write: 0x80004016 <- 0x713e607 +mem-write: 0x8000401a <- 0x886301d0 +mem-write: 0x8000401e <- 0x71302e7 +mem-write: 0x80004022 <- 0x84630160 +mem-write: 0x80004026 <- 0x578302e7 +mem-write: 0x8000402a <- 0xe79300c4 +mem-write: 0x8000402e <- 0x16230407 +mem-write: 0x80004032 <- 0xf06f00f4 +mem-write: 0x80004036 <- 0xf737ee9f +mem-write: 0x8000403a <- 0x713ffff +mem-write: 0x8000403e <- 0x26837ff7 +mem-write: 0x80004042 <- 0xf7b30104 +mem-write: 0x80004046 <- 0xf06f00e7 +mem-write: 0x8000404a <- 0xa023fadf +mem-write: 0x8000404e <- 0x5130099 +mem-write: 0x80004052 <- 0xf06f0000 +mem-write: 0x80004056 <- 0x113ec9f +mem-write: 0x8000405a <- 0x2c23fe01 +mem-write: 0x8000405e <- 0x2e230081 +mem-write: 0x80004062 <- 0x4130011 +mem-write: 0x80004066 <- 0x6630005 +mem-write: 0x8000406a <- 0x27830005 +mem-write: 0x8000406e <- 0x80630385 +mem-write: 0x80004072 <- 0x97830207 +mem-write: 0x80004076 <- 0x966300c5 +mem-write: 0x8000407a <- 0x20830207 +mem-write: 0x8000407e <- 0x240301c1 +mem-write: 0x80004082 <- 0x5130181 +mem-write: 0x80004086 <- 0x1130000 +mem-write: 0x8000408a <- 0x80670201 +mem-write: 0x8000408e <- 0x26230000 +mem-write: 0x80004092 <- 0xef00b1 +mem-write: 0x80004096 <- 0x25833600 +mem-write: 0x8000409a <- 0x978300c1 +mem-write: 0x8000409e <- 0x8ee300c5 +mem-write: 0x800040a2 <- 0x513fc07 +mem-write: 0x800040a6 <- 0x24030004 +mem-write: 0x800040aa <- 0x20830181 +mem-write: 0x800040ae <- 0x11301c1 +mem-write: 0x800040b2 <- 0xf06f0201 +mem-write: 0x800040b6 <- 0x593d49f +mem-write: 0x800040ba <- 0x6630005 +mem-write: 0x800040be <- 0xa5030005 +mem-write: 0x800040c2 <- 0xf06f1d81 +mem-write: 0x800040c6 <- 0xa503f95f +mem-write: 0x800040ca <- 0x45b71c01 +mem-write: 0x800040ce <- 0x85938000 +mem-write: 0x800040d2 <- 0x6f0585 +mem-write: 0x800040d6 <- 0x5130350 +mem-write: 0x800040da <- 0x80670000 +mem-write: 0x800040de <- 0xd5b70000 +mem-write: 0x800040e2 <- 0x85938000 +mem-write: 0x800040e6 <- 0x6f6345 +mem-write: 0x800040ea <- 0x1130210 +mem-write: 0x800040ee <- 0x47b7fe01 +mem-write: 0x800040f2 <- 0x2e238000 +mem-write: 0x800040f6 <- 0x2c230011 +mem-write: 0x800040fa <- 0x2a230081 +mem-write: 0x800040fe <- 0x28230091 +mem-write: 0x80004102 <- 0x26230121 +mem-write: 0x80004106 <- 0x24230131 +mem-write: 0x8000410a <- 0x22230141 +mem-write: 0x8000410e <- 0x20230151 +mem-write: 0x80004112 <- 0x24030161 +mem-write: 0x80004116 <- 0x87930045 +mem-write: 0x8000411a <- 0x2e230e07 +mem-write: 0x8000411e <- 0x71302f5 +mem-write: 0x80004122 <- 0x7932ec5 +mem-write: 0x80004126 <- 0x24230030 +mem-write: 0x8000412a <- 0x22232ee5 +mem-write: 0x8000412e <- 0x20232ef5 +mem-write: 0x80004132 <- 0x7932e05 +mem-write: 0x80004136 <- 0x9130040 +mem-write: 0x8000413a <- 0x26230005 +mem-write: 0x8000413e <- 0x61300f4 +mem-write: 0x80004142 <- 0x5930080 +mem-write: 0x80004146 <- 0x22230000 +mem-write: 0x8000414a <- 0x20230604 +mem-write: 0x8000414e <- 0x22230004 +mem-write: 0x80004152 <- 0x24230004 +mem-write: 0x80004156 <- 0x28230004 +mem-write: 0x8000415a <- 0x2a230004 +mem-write: 0x8000415e <- 0x2c230004 +mem-write: 0x80004162 <- 0x5130004 +mem-write: 0x80004166 <- 0xc0ef05c4 +mem-write: 0x8000416a <- 0x9b37cb1f +mem-write: 0x8000416e <- 0x24838000 +mem-write: 0x80004172 <- 0x9ab70089 +mem-write: 0x80004176 <- 0x9a378000 +mem-write: 0x8000417a <- 0x99b78000 +mem-write: 0x8000417e <- 0xb138000 +mem-write: 0x80004182 <- 0x8a932e0b +mem-write: 0x80004186 <- 0xa13344a +mem-write: 0x8000418a <- 0x89933cca +mem-write: 0x8000418e <- 0x7b74349 +mem-write: 0x80004192 <- 0x20230001 +mem-write: 0x80004196 <- 0x22230364 +mem-write: 0x8000419a <- 0x24230354 +mem-write: 0x8000419e <- 0x26230344 +mem-write: 0x800041a2 <- 0x2e230334 +mem-write: 0x800041a6 <- 0x87930084 +mem-write: 0x800041aa <- 0xa6230097 +mem-write: 0x800041ae <- 0x61300f4 +mem-write: 0x800041b2 <- 0x5930080 +mem-write: 0x800041b6 <- 0xa2230000 +mem-write: 0x800041ba <- 0xa0230604 +mem-write: 0x800041be <- 0xa2230004 +mem-write: 0x800041c2 <- 0xa4230004 +mem-write: 0x800041c6 <- 0xa8230004 +mem-write: 0x800041ca <- 0xaa230004 +mem-write: 0x800041ce <- 0xac230004 +mem-write: 0x800041d2 <- 0x85130004 +mem-write: 0x800041d6 <- 0xc0ef05c4 +mem-write: 0x800041da <- 0x2403c41f +mem-write: 0x800041de <- 0x7b700c9 +mem-write: 0x800041e2 <- 0xa0230002 +mem-write: 0x800041e6 <- 0xa2230364 +mem-write: 0x800041ea <- 0xa4230354 +mem-write: 0x800041ee <- 0xa6230344 +mem-write: 0x800041f2 <- 0xae230334 +mem-write: 0x800041f6 <- 0x87930094 +mem-write: 0x800041fa <- 0x26230127 +mem-write: 0x800041fe <- 0x222300f4 +mem-write: 0x80004202 <- 0x20230604 +mem-write: 0x80004206 <- 0x22230004 +mem-write: 0x8000420a <- 0x24230004 +mem-write: 0x8000420e <- 0x28230004 +mem-write: 0x80004212 <- 0x2a230004 +mem-write: 0x80004216 <- 0x2c230004 +mem-write: 0x8000421a <- 0x5130004 +mem-write: 0x8000421e <- 0x61305c4 +mem-write: 0x80004222 <- 0x5930080 +mem-write: 0x80004226 <- 0xc0ef0000 +mem-write: 0x8000422a <- 0x2083bf1f +mem-write: 0x8000422e <- 0x202301c1 +mem-write: 0x80004232 <- 0x22230364 +mem-write: 0x80004236 <- 0x24230354 +mem-write: 0x8000423a <- 0x26230344 +mem-write: 0x8000423e <- 0x2e230334 +mem-write: 0x80004242 <- 0x24030084 +mem-write: 0x80004246 <- 0x7930181 +mem-write: 0x8000424a <- 0x2c230010 +mem-write: 0x8000424e <- 0x248302f9 +mem-write: 0x80004252 <- 0x29030141 +mem-write: 0x80004256 <- 0x29830101 +mem-write: 0x8000425a <- 0x2a0300c1 +mem-write: 0x8000425e <- 0x2a830081 +mem-write: 0x80004262 <- 0x2b030041 +mem-write: 0x80004266 <- 0x1130001 +mem-write: 0x8000426a <- 0x80670201 +mem-write: 0x8000426e <- 0x5130000 +mem-write: 0x80004272 <- 0x80670000 +mem-write: 0x80004276 <- 0x1130000 +mem-write: 0x8000427a <- 0x2223ff01 +mem-write: 0x8000427e <- 0x6130091 +mem-write: 0x80004282 <- 0x84930680 +mem-write: 0x80004286 <- 0x84b3fff5 +mem-write: 0x8000428a <- 0x202302c4 +mem-write: 0x8000428e <- 0x89130121 +mem-write: 0x80004292 <- 0x24230005 +mem-write: 0x80004296 <- 0x26230081 +mem-write: 0x8000429a <- 0x85930011 +mem-write: 0x8000429e <- 0x30ef0744 +mem-write: 0x800042a2 <- 0x4134980 +mem-write: 0x800042a6 <- 0x630005 +mem-write: 0x800042aa <- 0x5130205 +mem-write: 0x800042ae <- 0x202300c5 +mem-write: 0x800042b2 <- 0x22230004 +mem-write: 0x800042b6 <- 0x24230124 +mem-write: 0x800042ba <- 0x861300a4 +mem-write: 0x800042be <- 0x5930684 +mem-write: 0x800042c2 <- 0xc0ef0000 +mem-write: 0x800042c6 <- 0x2083b55f +mem-write: 0x800042ca <- 0x51300c1 +mem-write: 0x800042ce <- 0x24030004 +mem-write: 0x800042d2 <- 0x24830081 +mem-write: 0x800042d6 <- 0x29030041 +mem-write: 0x800042da <- 0x1130001 +mem-write: 0x800042de <- 0x80670101 +mem-write: 0x800042e2 <- 0x1130000 +mem-write: 0x800042e6 <- 0x2823fe01 +mem-write: 0x800042ea <- 0xa9030121 +mem-write: 0x800042ee <- 0x26231c01 +mem-write: 0x800042f2 <- 0x2e230131 +mem-write: 0x800042f6 <- 0x27830011 +mem-write: 0x800042fa <- 0x2c230389 +mem-write: 0x800042fe <- 0x2a230081 +mem-write: 0x80004302 <- 0x9930091 +mem-write: 0x80004306 <- 0x86630005 +mem-write: 0x8000430a <- 0x9130a07 +mem-write: 0x8000430e <- 0x4932e09 +mem-write: 0x80004312 <- 0x2783fff0 +mem-write: 0x80004316 <- 0x24030049 +mem-write: 0x8000431a <- 0x87930089 +mem-write: 0x8000431e <- 0xd863fff7 +mem-write: 0x80004322 <- 0x6f0007 +mem-write: 0x80004326 <- 0x4130800 +mem-write: 0x8000432a <- 0x8c630684 +mem-write: 0x8000432e <- 0x17030697 +mem-write: 0x80004332 <- 0x879300c4 +mem-write: 0x80004336 <- 0x18e3fff7 +mem-write: 0x8000433a <- 0x7b7fe07 +mem-write: 0x8000433e <- 0x8793ffff +mem-write: 0x80004342 <- 0x22230017 +mem-write: 0x80004346 <- 0x20230604 +mem-write: 0x8000434a <- 0x22230004 +mem-write: 0x8000434e <- 0x24230004 +mem-write: 0x80004352 <- 0x26230004 +mem-write: 0x80004356 <- 0x282300f4 +mem-write: 0x8000435a <- 0x2a230004 +mem-write: 0x8000435e <- 0x2c230004 +mem-write: 0x80004362 <- 0x6130004 +mem-write: 0x80004366 <- 0x5930080 +mem-write: 0x8000436a <- 0x5130000 +mem-write: 0x8000436e <- 0xc0ef05c4 +mem-write: 0x80004372 <- 0x2823aa9f +mem-write: 0x80004376 <- 0x2a230204 +mem-write: 0x8000437a <- 0x22230204 +mem-write: 0x8000437e <- 0x24230404 +mem-write: 0x80004382 <- 0x20830404 +mem-write: 0x80004386 <- 0x51301c1 +mem-write: 0x8000438a <- 0x24030004 +mem-write: 0x8000438e <- 0x24830181 +mem-write: 0x80004392 <- 0x29030141 +mem-write: 0x80004396 <- 0x29830101 +mem-write: 0x8000439a <- 0x11300c1 +mem-write: 0x8000439e <- 0x80670201 +mem-write: 0x800043a2 <- 0x24030000 +mem-write: 0x800043a6 <- 0xc630009 +mem-write: 0x800043aa <- 0x9130004 +mem-write: 0x800043ae <- 0xf06f0004 +mem-write: 0x800043b2 <- 0x513f65f +mem-write: 0x800043b6 <- 0xf0ef0009 +mem-write: 0x800043ba <- 0xf06fd35f +mem-write: 0x800043be <- 0x593f51f +mem-write: 0x800043c2 <- 0x85130040 +mem-write: 0x800043c6 <- 0xf0ef0009 +mem-write: 0x800043ca <- 0x2023eb1f +mem-write: 0x800043ce <- 0x41300a9 +mem-write: 0x800043d2 <- 0x1ce30005 +mem-write: 0x800043d6 <- 0x793fc05 +mem-write: 0x800043da <- 0xa02300c0 +mem-write: 0x800043de <- 0xf06f00f9 +mem-write: 0x800043e2 <- 0xa503fa5f +mem-write: 0x800043e6 <- 0xd5b71c01 +mem-write: 0x800043ea <- 0x85938000 +mem-write: 0x800043ee <- 0x6f6345 +mem-write: 0x800043f2 <- 0x27835180 +mem-write: 0x800043f6 <- 0x84630385 +mem-write: 0x800043fa <- 0x80670007 +VXDRV: upload 1024 bytes to 0x800043fe +mem-write: 0x800043fe <- 0xf06f0000 +mem-write: 0x80004402 <- 0x8067cedf +mem-write: 0x80004406 <- 0x80670000 +mem-write: 0x8000440a <- 0x80670000 +mem-write: 0x8000440e <- 0x80670000 +mem-write: 0x80004412 <- 0xa5030000 +mem-write: 0x80004416 <- 0x45b71d81 +mem-write: 0x8000441a <- 0x85938000 +mem-write: 0x8000441e <- 0x6f0d85 +mem-write: 0x80004422 <- 0xa5034440 +mem-write: 0x80004426 <- 0x45b71d81 +mem-write: 0x8000442a <- 0x85938000 +mem-write: 0x8000442e <- 0x6f2705 +mem-write: 0x80004432 <- 0x1134340 +mem-write: 0x80004436 <- 0x2623fe01 +mem-write: 0x8000443a <- 0x2c230131 +mem-write: 0x8000443e <- 0x2a230081 +mem-write: 0x80004442 <- 0x28230091 +mem-write: 0x80004446 <- 0x24230121 +mem-write: 0x8000444a <- 0x2e230141 +mem-write: 0x8000444e <- 0x8a130011 +mem-write: 0x80004452 <- 0x9130005 +mem-write: 0x80004456 <- 0x89930005 +mem-write: 0x8000445a <- 0x30efc301 +mem-write: 0x8000445e <- 0xa7033490 +mem-write: 0x80004462 <- 0x17b70089 +mem-write: 0x80004466 <- 0x84130000 +mem-write: 0x8000446a <- 0x2483fef7 +mem-write: 0x8000446e <- 0x4330047 +mem-write: 0x80004472 <- 0xf4934144 +mem-write: 0x80004476 <- 0x433ffc4 +mem-write: 0x8000447a <- 0x54130094 +mem-write: 0x8000447e <- 0x41300c4 +mem-write: 0x80004482 <- 0x1413fff4 +mem-write: 0x80004486 <- 0x4e6300c4 +mem-write: 0x8000448a <- 0x59300f4 +mem-write: 0x8000448e <- 0x5130000 +mem-write: 0x80004492 <- 0x40ef0009 +mem-write: 0x80004496 <- 0xa78350d0 +mem-write: 0x8000449a <- 0x87b30089 +mem-write: 0x8000449e <- 0x8630097 +mem-write: 0x800044a2 <- 0x51302f5 +mem-write: 0x800044a6 <- 0x30ef0009 +mem-write: 0x800044aa <- 0x20833010 +mem-write: 0x800044ae <- 0x240301c1 +mem-write: 0x800044b2 <- 0x24830181 +mem-write: 0x800044b6 <- 0x29030141 +mem-write: 0x800044ba <- 0x29830101 +mem-write: 0x800044be <- 0x2a0300c1 +mem-write: 0x800044c2 <- 0x5130081 +mem-write: 0x800044c6 <- 0x1130000 +mem-write: 0x800044ca <- 0x80670201 +mem-write: 0x800044ce <- 0x5b30000 +mem-write: 0x800044d2 <- 0x5134080 +mem-write: 0x800044d6 <- 0x40ef0009 +mem-write: 0x800044da <- 0x7934c90 +mem-write: 0x800044de <- 0x863fff0 +mem-write: 0x800044e2 <- 0x879304f5 +mem-write: 0x800044e6 <- 0xa7031f81 +mem-write: 0x800044ea <- 0xa6830007 +mem-write: 0x800044ee <- 0x84b30089 +mem-write: 0x800044f2 <- 0xe4934084 +mem-write: 0x800044f6 <- 0x4330014 +mem-write: 0x800044fa <- 0x5134087 +mem-write: 0x800044fe <- 0xa2230009 +mem-write: 0x80004502 <- 0xa0230096 +mem-write: 0x80004506 <- 0x30ef0087 +mem-write: 0x8000450a <- 0x20832a10 +mem-write: 0x8000450e <- 0x240301c1 +mem-write: 0x80004512 <- 0x24830181 +mem-write: 0x80004516 <- 0x29030141 +mem-write: 0x8000451a <- 0x29830101 +mem-write: 0x8000451e <- 0x2a0300c1 +mem-write: 0x80004522 <- 0x5130081 +mem-write: 0x80004526 <- 0x1130010 +mem-write: 0x8000452a <- 0x80670201 +mem-write: 0x8000452e <- 0x5930000 +mem-write: 0x80004532 <- 0x5130000 +mem-write: 0x80004536 <- 0x40ef0009 +mem-write: 0x8000453a <- 0xa7034690 +mem-write: 0x8000453e <- 0x6930089 +mem-write: 0x80004542 <- 0x7b300f0 +mem-write: 0x80004546 <- 0xdee340e5 +mem-write: 0x8000454a <- 0xa683f4f6 +mem-write: 0x8000454e <- 0xe7931dc1 +mem-write: 0x80004552 <- 0x22230017 +mem-write: 0x80004556 <- 0x53300f7 +mem-write: 0x8000455a <- 0xac2340d5 +mem-write: 0x8000455e <- 0xf06f1ea1 +mem-write: 0x80004562 <- 0x8463f45f +mem-write: 0x80004566 <- 0x1131205 +mem-write: 0x8000456a <- 0x2423ff01 +mem-write: 0x8000456e <- 0x22230081 +mem-write: 0x80004572 <- 0x84130091 +mem-write: 0x80004576 <- 0x4930005 +mem-write: 0x8000457a <- 0x26230005 +mem-write: 0x8000457e <- 0x30ef0011 +mem-write: 0x80004582 <- 0x28032250 +mem-write: 0x80004586 <- 0x713ffc4 +mem-write: 0x8000458a <- 0x7793ff84 +mem-write: 0x8000458e <- 0x633ffe8 +mem-write: 0x80004592 <- 0x859300f7 +mem-write: 0x80004596 <- 0x2683c301 +mem-write: 0x8000459a <- 0xa5030046 +mem-write: 0x8000459e <- 0xf6930085 +mem-write: 0x800045a2 <- 0x663ffc6 +mem-write: 0x800045a6 <- 0x22231ac5 +mem-write: 0x800045aa <- 0x781300d6 +mem-write: 0x800045ae <- 0x5330018 +mem-write: 0x800045b2 <- 0x1e6300d6 +mem-write: 0x800045b6 <- 0x23030808 +mem-write: 0x800045ba <- 0x2803ff84 +mem-write: 0x800045be <- 0x7330045 +mem-write: 0x800045c2 <- 0x28834067 +mem-write: 0x800045c6 <- 0x85130087 +mem-write: 0x800045ca <- 0x87b3c381 +mem-write: 0x800045ce <- 0x78130067 +mem-write: 0x800045d2 <- 0x8e630018 +mem-write: 0x800045d6 <- 0x230312a8 +mem-write: 0x800045da <- 0xa62300c7 +mem-write: 0x800045de <- 0x24230068 +mem-write: 0x800045e2 <- 0xe630113 +mem-write: 0x800045e6 <- 0xe6931c08 +mem-write: 0x800045ea <- 0x22230017 +mem-write: 0x800045ee <- 0x202300d7 +mem-write: 0x800045f2 <- 0x69300f6 +mem-write: 0x800045f6 <- 0xe6631ff0 +mem-write: 0x800045fa <- 0xf6930af6 +mem-write: 0x800045fe <- 0x8693ff87 +mem-write: 0x80004602 <- 0xa5030086 +mem-write: 0x80004606 <- 0x86b30045 +mem-write: 0x8000460a <- 0xa60300d5 +mem-write: 0x8000460e <- 0xd8130006 +mem-write: 0x80004612 <- 0x7930057 +mem-write: 0x80004616 <- 0x97b30010 +mem-write: 0x8000461a <- 0xe7b30107 +mem-write: 0x8000461e <- 0x851300a7 +mem-write: 0x80004622 <- 0x2623ff86 +mem-write: 0x80004626 <- 0x242300a7 +mem-write: 0x8000462a <- 0xa22300c7 +mem-write: 0x8000462e <- 0xa02300f5 +mem-write: 0x80004632 <- 0x262300e6 +mem-write: 0x80004636 <- 0x240300e6 +mem-write: 0x8000463a <- 0x20830081 +mem-write: 0x8000463e <- 0x851300c1 +mem-write: 0x80004642 <- 0x24830004 +mem-write: 0x80004646 <- 0x1130041 +mem-write: 0x8000464a <- 0x306f0101 +mem-write: 0x8000464e <- 0x250315d0 +mem-write: 0x80004652 <- 0x75130045 +mem-write: 0x80004656 <- 0x1c630015 +mem-write: 0x8000465a <- 0x87b30205 +mem-write: 0x8000465e <- 0x851300d7 +mem-write: 0x80004662 <- 0x2683c381 +mem-write: 0x80004666 <- 0xe8930086 +mem-write: 0x8000466a <- 0x8330017 +mem-write: 0x8000466e <- 0x846300f7 +mem-write: 0x80004672 <- 0x260316a6 +mem-write: 0x80004676 <- 0xa62300c6 +mem-write: 0x8000467a <- 0x242300c6 +mem-write: 0x8000467e <- 0x222300d6 +mem-write: 0x80004682 <- 0x20230117 +mem-write: 0x80004686 <- 0xf06f00f8 +mem-write: 0x8000468a <- 0x8067f6df +mem-write: 0x8000468e <- 0xe6930000 +mem-write: 0x80004692 <- 0x2e230017 +mem-write: 0x80004696 <- 0x2023fed4 +mem-write: 0x8000469a <- 0x69300f6 +mem-write: 0x8000469e <- 0xfee31ff0 +mem-write: 0x800046a2 <- 0xd693f4f6 +mem-write: 0x800046a6 <- 0x6130097 +mem-write: 0x800046aa <- 0x68630040 +mem-write: 0x800046ae <- 0xd6930ed6 +mem-write: 0x800046b2 <- 0x88130067 +mem-write: 0x800046b6 <- 0x86130396 +mem-write: 0x800046ba <- 0x18130386 +mem-write: 0x800046be <- 0x88330038 +mem-write: 0x800046c2 <- 0x26830105 +mem-write: 0x800046c6 <- 0x8130008 +mem-write: 0x800046ca <- 0x463ff88 +mem-write: 0x800046ce <- 0xa60312d8 +mem-write: 0x800046d2 <- 0x76130046 +mem-write: 0x800046d6 <- 0xf663ffc6 +mem-write: 0x800046da <- 0xa68300c7 +mem-write: 0x800046de <- 0x18e30086 +mem-write: 0x800046e2 <- 0xa803fed8 +mem-write: 0x800046e6 <- 0x262300c6 +mem-write: 0x800046ea <- 0x24230107 +mem-write: 0x800046ee <- 0x240300d7 +mem-write: 0x800046f2 <- 0x20830081 +mem-write: 0x800046f6 <- 0x242300c1 +mem-write: 0x800046fa <- 0x851300e8 +mem-write: 0x800046fe <- 0x24830004 +mem-write: 0x80004702 <- 0xa6230041 +mem-write: 0x80004706 <- 0x11300e6 +mem-write: 0x8000470a <- 0x306f0101 +mem-write: 0x8000470e <- 0x126309d0 +mem-write: 0x80004712 <- 0x25831408 +mem-write: 0x80004716 <- 0x260300c6 +mem-write: 0x8000471a <- 0x87b30086 +mem-write: 0x8000471e <- 0x240300f6 +mem-write: 0x80004722 <- 0x26230081 +mem-write: 0x80004726 <- 0xa42300b6 +mem-write: 0x8000472a <- 0xe69300c5 +mem-write: 0x8000472e <- 0x20830017 +mem-write: 0x80004732 <- 0x222300c1 +mem-write: 0x80004736 <- 0x851300d7 +mem-write: 0x8000473a <- 0x7330004 +mem-write: 0x8000473e <- 0x248300f7 +mem-write: 0x80004742 <- 0x20230041 +mem-write: 0x80004746 <- 0x11300f7 +mem-write: 0x8000474a <- 0x306f0101 +mem-write: 0x8000474e <- 0x781305d0 +mem-write: 0x80004752 <- 0x87b30018 +mem-write: 0x80004756 <- 0x106300d7 +mem-write: 0x8000475a <- 0x25030208 +mem-write: 0x8000475e <- 0x733ff84 +mem-write: 0x80004762 <- 0x268340a7 +mem-write: 0x80004766 <- 0x260300c7 +mem-write: 0x8000476a <- 0x87b30087 +mem-write: 0x8000476e <- 0x262300a7 +mem-write: 0x80004772 <- 0xa42300d6 +mem-write: 0x80004776 <- 0xe61300c6 +mem-write: 0x8000477a <- 0xa6830017 +mem-write: 0x8000477e <- 0x22231e01 +mem-write: 0x80004782 <- 0xa42300c7 +mem-write: 0x80004786 <- 0xe8e300e5 +mem-write: 0x8000478a <- 0xa583ead7 +mem-write: 0x8000478e <- 0x85131f01 +mem-write: 0x80004792 <- 0xf0ef0004 +mem-write: 0x80004796 <- 0xf06fca1f +mem-write: 0x8000479a <- 0x613ea1f +mem-write: 0x8000479e <- 0x74630140 +mem-write: 0x800047a2 <- 0x61302d6 +mem-write: 0x800047a6 <- 0x64630540 +mem-write: 0x800047aa <- 0xd69306d6 +mem-write: 0x800047ae <- 0x881300c7 +mem-write: 0x800047b2 <- 0x861306f6 +mem-write: 0x800047b6 <- 0x181306e6 +mem-write: 0x800047ba <- 0xf06f0038 +mem-write: 0x800047be <- 0x87b3f05f +mem-write: 0x800047c2 <- 0xf06f00d7 +mem-write: 0x800047c6 <- 0x8813ea1f +mem-write: 0x800047ca <- 0x861305c6 +mem-write: 0x800047ce <- 0x181305b6 +mem-write: 0x800047d2 <- 0xf06f0038 +mem-write: 0x800047d6 <- 0xaa23eedf +mem-write: 0x800047da <- 0xa82300e5 +mem-write: 0x800047de <- 0x262300e5 +mem-write: 0x800047e2 <- 0x242300a7 +mem-write: 0x800047e6 <- 0x222300a7 +mem-write: 0x800047ea <- 0x20230117 +mem-write: 0x800047ee <- 0xf06f00f8 +mem-write: 0x800047f2 <- 0xa503e49f +mem-write: 0x800047f6 <- 0x56130045 +mem-write: 0x800047fa <- 0x7934026 +VXDRV: upload 1024 bytes to 0x800047fe +mem-write: 0x800047fe <- 0x96330010 +mem-write: 0x80004802 <- 0x663300c7 +mem-write: 0x80004806 <- 0xa22300a6 +mem-write: 0x8000480a <- 0xf06f00c5 +mem-write: 0x8000480e <- 0x613eddf +mem-write: 0x80004812 <- 0x6c631540 +mem-write: 0x80004816 <- 0xd69300d6 +mem-write: 0x8000481a <- 0x881300f7 +mem-write: 0x8000481e <- 0x86130786 +mem-write: 0x80004822 <- 0x18130776 +mem-write: 0x80004826 <- 0xf06f0038 +mem-write: 0x8000482a <- 0x613e99f +mem-write: 0x8000482e <- 0x6c635540 +mem-write: 0x80004832 <- 0xd69300d6 +mem-write: 0x80004836 <- 0x88130127 +mem-write: 0x8000483a <- 0x861307d6 +mem-write: 0x8000483e <- 0x181307c6 +mem-write: 0x80004842 <- 0xf06f0038 +mem-write: 0x80004846 <- 0x813e7df +mem-write: 0x8000484a <- 0x6133f80 +mem-write: 0x8000484e <- 0xf06f07e0 +mem-write: 0x80004852 <- 0xe693e71f +mem-write: 0x80004856 <- 0x22230017 +mem-write: 0x8000485a <- 0x202300d7 +mem-write: 0x8000485e <- 0xf06f00f6 +mem-write: 0x80004862 <- 0x113dd9f +mem-write: 0x80004866 <- 0x2823fe01 +mem-write: 0x8000486a <- 0x26230121 +mem-write: 0x8000486e <- 0x24230131 +mem-write: 0x80004872 <- 0x22230141 +mem-write: 0x80004876 <- 0x20230151 +mem-write: 0x8000487a <- 0x2e230161 +mem-write: 0x8000487e <- 0x2c230011 +mem-write: 0x80004882 <- 0x2a230081 +mem-write: 0x80004886 <- 0x8b130091 +mem-write: 0x8000488a <- 0xa930005 +mem-write: 0x8000488e <- 0xa132e05 +mem-write: 0x80004892 <- 0x9930000 +mem-write: 0x80004896 <- 0x9130010 +mem-write: 0x8000489a <- 0xa483fff0 +mem-write: 0x8000489e <- 0xa403004a +mem-write: 0x800048a2 <- 0x8493008a +mem-write: 0x800048a6 <- 0xc663fff4 +mem-write: 0x800048aa <- 0x57830204 +mem-write: 0x800048ae <- 0x849300c4 +mem-write: 0x800048b2 <- 0xfc63fff4 +mem-write: 0x800048b6 <- 0x178300f9 +mem-write: 0x800048ba <- 0x51300e4 +mem-write: 0x800048be <- 0x86630004 +mem-write: 0x800048c2 <- 0xe70127 +mem-write: 0x800048c6 <- 0x6a33000b +mem-write: 0x800048ca <- 0x41300aa +mem-write: 0x800048ce <- 0x9ee30684 +mem-write: 0x800048d2 <- 0xaa83fd24 +mem-write: 0x800048d6 <- 0x92e3000a +mem-write: 0x800048da <- 0x2083fc0a +mem-write: 0x800048de <- 0x240301c1 +mem-write: 0x800048e2 <- 0x24830181 +mem-write: 0x800048e6 <- 0x29030141 +mem-write: 0x800048ea <- 0x29830101 +mem-write: 0x800048ee <- 0x2a8300c1 +mem-write: 0x800048f2 <- 0x2b030041 +mem-write: 0x800048f6 <- 0x5130001 +mem-write: 0x800048fa <- 0x2a03000a +mem-write: 0x800048fe <- 0x1130081 +mem-write: 0x80004902 <- 0x80670201 +mem-write: 0x80004906 <- 0x1130000 +mem-write: 0x8000490a <- 0x2023fd01 +mem-write: 0x8000490e <- 0x2e230321 +mem-write: 0x80004912 <- 0x2c230131 +mem-write: 0x80004916 <- 0x2a230141 +mem-write: 0x8000491a <- 0x28230151 +mem-write: 0x8000491e <- 0x26230161 +mem-write: 0x80004922 <- 0x26230171 +mem-write: 0x80004926 <- 0x24230211 +mem-write: 0x8000492a <- 0x22230281 +mem-write: 0x8000492e <- 0xa930291 +mem-write: 0x80004932 <- 0x8b930005 +mem-write: 0x80004936 <- 0xb130005 +mem-write: 0x8000493a <- 0xa132e05 +mem-write: 0x8000493e <- 0x9930000 +mem-write: 0x80004942 <- 0x9130010 +mem-write: 0x80004946 <- 0x2483fff0 +mem-write: 0x8000494a <- 0x2403004b +mem-write: 0x8000494e <- 0x8493008b +mem-write: 0x80004952 <- 0xc863fff4 +mem-write: 0x80004956 <- 0x57830204 +mem-write: 0x8000495a <- 0x849300c4 +mem-write: 0x8000495e <- 0xfe63fff4 +mem-write: 0x80004962 <- 0x178300f9 +mem-write: 0x80004966 <- 0x59300e4 +mem-write: 0x8000496a <- 0x85130004 +mem-write: 0x8000496e <- 0x8663000a +mem-write: 0x80004972 <- 0x80e70127 +mem-write: 0x80004976 <- 0x6a33000b +mem-write: 0x8000497a <- 0x41300aa +mem-write: 0x8000497e <- 0x9ce30684 +mem-write: 0x80004982 <- 0x2b03fd24 +mem-write: 0x80004986 <- 0x10e3000b +mem-write: 0x8000498a <- 0x2083fc0b +mem-write: 0x8000498e <- 0x240302c1 +mem-write: 0x80004992 <- 0x24830281 +mem-write: 0x80004996 <- 0x29030241 +mem-write: 0x8000499a <- 0x29830201 +mem-write: 0x8000499e <- 0x2a8301c1 +mem-write: 0x800049a2 <- 0x2b030141 +mem-write: 0x800049a6 <- 0x2b830101 +mem-write: 0x800049aa <- 0x51300c1 +mem-write: 0x800049ae <- 0x2a03000a +mem-write: 0x800049b2 <- 0x1130181 +mem-write: 0x800049b6 <- 0x80670301 +mem-write: 0x800049ba <- 0x6930000 +mem-write: 0x800049be <- 0x7930045 +mem-write: 0x800049c2 <- 0x5130000 +mem-write: 0x800049c6 <- 0x883701a5 +mem-write: 0x800049ca <- 0x6fffff +mem-write: 0x800049ce <- 0x979301c0 +mem-write: 0x800049d2 <- 0x90230017 +mem-write: 0x800049d6 <- 0x979300e6 +mem-write: 0x800049da <- 0x86930107 +mem-write: 0x800049de <- 0xd7930026 +mem-write: 0x800049e2 <- 0xe630107 +mem-write: 0x800049e6 <- 0xd70302d5 +mem-write: 0x800049ea <- 0x76130006 +mem-write: 0x800049ee <- 0x4630017 +mem-write: 0x800049f2 <- 0xe7930006 +mem-write: 0x800049f6 <- 0x57130017 +mem-write: 0x800049fa <- 0xf6130017 +mem-write: 0x800049fe <- 0x65b30027 +mem-write: 0x80004a02 <- 0x6e30107 +mem-write: 0x80004a06 <- 0x9793fc06 +mem-write: 0x80004a0a <- 0x90230017 +mem-write: 0x80004a0e <- 0x979300b6 +mem-write: 0x80004a12 <- 0x86930107 +mem-write: 0x80004a16 <- 0xd7930026 +mem-write: 0x80004a1a <- 0x16e30107 +mem-write: 0x80004a1e <- 0x8067fcd5 +mem-write: 0x80004a22 <- 0x6930000 +mem-write: 0x80004a26 <- 0x7130185 +mem-write: 0x80004a2a <- 0x5130000 +mem-write: 0x80004a2e <- 0x6f0025 +mem-write: 0x80004a32 <- 0x171301c0 +mem-write: 0x80004a36 <- 0x90230017 +mem-write: 0x80004a3a <- 0x171300f6 +mem-write: 0x80004a3e <- 0x86930107 +mem-write: 0x80004a42 <- 0x5713ffe6 +mem-write: 0x80004a46 <- 0x4630107 +mem-write: 0x80004a4a <- 0xd78304d5 +mem-write: 0x80004a4e <- 0x96130006 +mem-write: 0x80004a52 <- 0x56130107 +mem-write: 0x80004a56 <- 0x97934106 +mem-write: 0x80004a5a <- 0x54630017 +mem-write: 0x80004a5e <- 0x67130006 +mem-write: 0x80004a62 <- 0x97930017 +mem-write: 0x80004a66 <- 0xd7930107 +mem-write: 0x80004a6a <- 0x76130107 +mem-write: 0x80004a6e <- 0xe5930027 +mem-write: 0x80004a72 <- 0xe30017 +mem-write: 0x80004a76 <- 0x1713fc06 +mem-write: 0x80004a7a <- 0x90230017 +mem-write: 0x80004a7e <- 0x171300b6 +mem-write: 0x80004a82 <- 0x86930107 +mem-write: 0x80004a86 <- 0x5713ffe6 +mem-write: 0x80004a8a <- 0x10e30107 +mem-write: 0x80004a8e <- 0x8067fcd5 +mem-write: 0x80004a92 <- 0x1130000 +mem-write: 0x80004a96 <- 0xe37fe01 +mem-write: 0x80004a9a <- 0x1d230001 +mem-write: 0x80004a9e <- 0x1e230001 +mem-write: 0x80004aa2 <- 0x85930001 +mem-write: 0x80004aa6 <- 0x7930185 +mem-write: 0x80004aaa <- 0x81301c1 +mem-write: 0x80004aae <- 0xe130081 +mem-write: 0x80004ab2 <- 0xd703fffe +mem-write: 0x80004ab6 <- 0x87930005 +mem-write: 0x80004aba <- 0x8593ffe7 +mem-write: 0x80004abe <- 0x1863ffe5 +mem-write: 0x80004ac2 <- 0x9f230207 +mem-write: 0x80004ac6 <- 0x96e3fe07 +mem-write: 0x80004aca <- 0x613ff07 +mem-write: 0x80004ace <- 0x6930046 +mem-write: 0x80004ad2 <- 0xd70301e1 +mem-write: 0x80004ad6 <- 0x87930007 +mem-write: 0x80004ada <- 0x6130027 +mem-write: 0x80004ade <- 0x1f230026 +mem-write: 0x80004ae2 <- 0x98e3fee6 +mem-write: 0x80004ae6 <- 0x113fed7 +mem-write: 0x80004aea <- 0x80670201 +mem-write: 0x80004aee <- 0x7330000 +mem-write: 0x80004af2 <- 0xd88302a7 +mem-write: 0x80004af6 <- 0xd3030027 +mem-write: 0x80004afa <- 0x76b30007 +mem-write: 0x80004afe <- 0x86b301c7 +mem-write: 0x80004b02 <- 0x57130116 +mem-write: 0x80004b06 <- 0xd8930107 +mem-write: 0x80004b0a <- 0x7330106 +mem-write: 0x80004b0e <- 0x7330067 +mem-write: 0x80004b12 <- 0x58930117 +mem-write: 0x80004b16 <- 0x91230107 +mem-write: 0x80004b1a <- 0x902300d7 +mem-write: 0x80004b1e <- 0x9f2300e7 +mem-write: 0x80004b22 <- 0x98e3ff17 +mem-write: 0x80004b26 <- 0xf06ff907 +mem-write: 0x80004b2a <- 0x713fa5f +mem-write: 0x80004b2e <- 0x57830125 +mem-write: 0x80004b32 <- 0x5130005 +mem-write: 0x80004b36 <- 0x98630025 +mem-write: 0x80004b3a <- 0x1ae30007 +mem-write: 0x80004b3e <- 0x513fee5 +mem-write: 0x80004b42 <- 0x80670000 +mem-write: 0x80004b46 <- 0x5130000 +mem-write: 0x80004b4a <- 0x80670010 +mem-write: 0x80004b4e <- 0x1130000 +mem-write: 0x80004b52 <- 0x2223ff01 +mem-write: 0x80004b56 <- 0x54830091 +mem-write: 0x80004b5a <- 0x24230125 +mem-write: 0x80004b5e <- 0x26230081 +mem-write: 0x80004b62 <- 0xc7930011 +mem-write: 0x80004b66 <- 0x9713fff4 +mem-write: 0x80004b6a <- 0x4130117 +mem-write: 0x80004b6e <- 0x16630005 +mem-write: 0x80004b72 <- 0xf0ef0007 +mem-write: 0x80004b76 <- 0x1863fb9f +mem-write: 0x80004b7a <- 0x87b70005 +mem-write: 0x80004b7e <- 0xc4b3ffff +mem-write: 0x80004b82 <- 0x192300f4 +mem-write: 0x80004b86 <- 0x20830094 +mem-write: 0x80004b8a <- 0x240300c1 +mem-write: 0x80004b8e <- 0x24830081 +mem-write: 0x80004b92 <- 0x1130041 +mem-write: 0x80004b96 <- 0x80670101 +mem-write: 0x80004b9a <- 0x1130000 +mem-write: 0x80004b9e <- 0x2423ff01 +mem-write: 0x80004ba2 <- 0x54030081 +mem-write: 0x80004ba6 <- 0x26230125 +mem-write: 0x80004baa <- 0x47930011 +mem-write: 0x80004bae <- 0x9713fff4 +mem-write: 0x80004bb2 <- 0x1a630117 +mem-write: 0x80004bb6 <- 0xf0ef0007 +mem-write: 0x80004bba <- 0x793f75f +mem-write: 0x80004bbe <- 0x5130005 +mem-write: 0x80004bc2 <- 0x94630000 +mem-write: 0x80004bc6 <- 0x55130007 +mem-write: 0x80004bca <- 0x208300f4 +mem-write: 0x80004bce <- 0x240300c1 +mem-write: 0x80004bd2 <- 0x1130081 +mem-write: 0x80004bd6 <- 0x80670101 +mem-write: 0x80004bda <- 0x57830000 +mem-write: 0x80004bde <- 0x1130125 +mem-write: 0x80004be2 <- 0x2423fd01 +mem-write: 0x80004be6 <- 0xd7930281 +mem-write: 0x80004bea <- 0x222300f7 +mem-write: 0x80004bee <- 0x26230291 +mem-write: 0x80004bf2 <- 0x20230211 +mem-write: 0x80004bf6 <- 0x2e230321 +mem-write: 0x80004bfa <- 0x7b30131 +VXDRV: upload 1024 bytes to 0x80004bfe +mem-write: 0x80004bfe <- 0x902340f0 +mem-write: 0x80004c02 <- 0x578300f5 +mem-write: 0x80004c06 <- 0x87370125 +mem-write: 0x80004c0a <- 0x7130000 +mem-write: 0x80004c0e <- 0x77b3fff7 +mem-write: 0x80004c12 <- 0x912300f7 +mem-write: 0x80004c16 <- 0x49300f5 +mem-write: 0x80004c1a <- 0x4130005 +mem-write: 0x80004c1e <- 0x82630105 +mem-write: 0x80004c22 <- 0x879304e7 +mem-write: 0x80004c26 <- 0x92230065 +mem-write: 0x80004c2a <- 0x5130005 +mem-write: 0x80004c2e <- 0x5703ffe5 +mem-write: 0x80004c32 <- 0x4130004 +mem-write: 0x80004c36 <- 0x8793ffe4 +mem-write: 0x80004c3a <- 0x9f230027 +mem-write: 0x80004c3e <- 0x18e3fee7 +mem-write: 0x80004c42 <- 0x9c23fe85 +mem-write: 0x80004c46 <- 0x20830005 +mem-write: 0x80004c4a <- 0x240302c1 +mem-write: 0x80004c4e <- 0x24830281 +mem-write: 0x80004c52 <- 0x29030241 +mem-write: 0x80004c56 <- 0x29830201 +mem-write: 0x80004c5a <- 0x11301c1 +mem-write: 0x80004c5e <- 0x80670301 +mem-write: 0x80004c62 <- 0x57030000 +mem-write: 0x80004c66 <- 0x89130125 +mem-write: 0x80004c6a <- 0xf7330045 +mem-write: 0x80004c6e <- 0x1c6300e7 +mem-write: 0x80004c72 <- 0x262302f7 +mem-write: 0x80004c76 <- 0xf0ef00b1 +mem-write: 0x80004c7a <- 0x2583eb5f +mem-write: 0x80004c7e <- 0x46300c1 +mem-write: 0x80004c82 <- 0x87930205 +mem-write: 0x80004c86 <- 0x92230065 +mem-write: 0x80004c8a <- 0x85130005 +mem-write: 0x80004c8e <- 0x5703ffc4 +mem-write: 0x80004c92 <- 0x4130004 +mem-write: 0x80004c96 <- 0x8793ffe4 +mem-write: 0x80004c9a <- 0x9f230027 +mem-write: 0x80004c9e <- 0x18e3fee7 +mem-write: 0x80004ca2 <- 0xf06ffe85 +mem-write: 0x80004ca6 <- 0x8993fa5f +mem-write: 0x80004caa <- 0x91301a5 +mem-write: 0x80004cae <- 0x1f230029 +mem-write: 0x80004cb2 <- 0x9ce3fe09 +mem-write: 0x80004cb6 <- 0x2083ff29 +mem-write: 0x80004cba <- 0x240302c1 +mem-write: 0x80004cbe <- 0x24830281 +mem-write: 0x80004cc2 <- 0x29030241 +mem-write: 0x80004cc6 <- 0x29830201 +mem-write: 0x80004cca <- 0x11301c1 +mem-write: 0x80004cce <- 0x80670301 +mem-write: 0x80004cd2 <- 0x57830000 +mem-write: 0x80004cd6 <- 0x1130125 +mem-write: 0x80004cda <- 0x2423fb01 +mem-write: 0x80004cde <- 0xc7930481 +mem-write: 0x80004ce2 <- 0x2223fff7 +mem-write: 0x80004ce6 <- 0x26230491 +mem-write: 0x80004cea <- 0x97130411 +mem-write: 0x80004cee <- 0x4930117 +mem-write: 0x80004cf2 <- 0x84130005 +mem-write: 0x80004cf6 <- 0x16630005 +mem-write: 0x80004cfa <- 0xf0ef0007 +mem-write: 0x80004cfe <- 0x1263e31f +mem-write: 0x80004d02 <- 0x57830805 +mem-write: 0x80004d06 <- 0xc7930124 +mem-write: 0x80004d0a <- 0x9713fff7 +mem-write: 0x80004d0e <- 0x4630117 +mem-write: 0x80004d12 <- 0x5930607 +mem-write: 0x80004d16 <- 0x85130081 +mem-write: 0x80004d1a <- 0xf0ef0004 +mem-write: 0x80004d1e <- 0x593ec1f +mem-write: 0x80004d22 <- 0x5130241 +mem-write: 0x80004d26 <- 0xf0ef0004 +mem-write: 0x80004d2a <- 0x5583eb5f +mem-write: 0x80004d2e <- 0x55030081 +mem-write: 0x80004d32 <- 0xc630241 +mem-write: 0x80004d36 <- 0x79304b5 +mem-write: 0x80004d3a <- 0x71300a1 +mem-write: 0x80004d3e <- 0x6130261 +mem-write: 0x80004d42 <- 0xd6830201 +mem-write: 0x80004d46 <- 0x87930007 +mem-write: 0x80004d4a <- 0x9a630027 +mem-write: 0x80004d4e <- 0x56830806 +mem-write: 0x80004d52 <- 0x7130007 +mem-write: 0x80004d56 <- 0x94630027 +mem-write: 0x80004d5a <- 0x94e30806 +mem-write: 0x80004d5e <- 0x513fec7 +mem-write: 0x80004d62 <- 0x20830000 +mem-write: 0x80004d66 <- 0x240304c1 +mem-write: 0x80004d6a <- 0x24830481 +mem-write: 0x80004d6e <- 0x1130441 +mem-write: 0x80004d72 <- 0x80670501 +mem-write: 0x80004d76 <- 0x5130000 +mem-write: 0x80004d7a <- 0xf0ef0004 +mem-write: 0x80004d7e <- 0xae3db1f +mem-write: 0x80004d82 <- 0x513f805 +mem-write: 0x80004d86 <- 0xf06fffe0 +mem-write: 0x80004d8a <- 0x3513fddf +mem-write: 0x80004d8e <- 0x56030015 +mem-write: 0x80004d92 <- 0x568300a1 +mem-write: 0x80004d96 <- 0x5330261 +mem-write: 0x80004d9a <- 0x71340a0 +mem-write: 0x80004d9e <- 0x79300a1 +mem-write: 0x80004da2 <- 0x75130261 +mem-write: 0x80004da6 <- 0x5130025 +mem-write: 0x80004daa <- 0x593fff5 +mem-write: 0x80004dae <- 0x879303c1 +mem-write: 0x80004db2 <- 0x7130027 +mem-write: 0x80004db6 <- 0x1e630027 +mem-write: 0x80004dba <- 0x82e300d6 +mem-write: 0x80004dbe <- 0x5603fab7 +mem-write: 0x80004dc2 <- 0xd6830007 +mem-write: 0x80004dc6 <- 0x7130007 +mem-write: 0x80004dca <- 0x87930027 +mem-write: 0x80004dce <- 0x6e30027 +mem-write: 0x80004dd2 <- 0xe8e3fed6 +mem-write: 0x80004dd6 <- 0x533f8c6 +mem-write: 0x80004dda <- 0xf06f40a0 +mem-write: 0x80004dde <- 0x513f89f +mem-write: 0x80004de2 <- 0x80e30010 +mem-write: 0x80004de6 <- 0x513f805 +mem-write: 0x80004dea <- 0xf06ffff0 +mem-write: 0x80004dee <- 0x113f79f +mem-write: 0x80004df2 <- 0x2623ff01 +mem-write: 0x80004df6 <- 0xf0ef0011 +mem-write: 0x80004dfa <- 0x2083d35f +mem-write: 0x80004dfe <- 0x351300c1 +mem-write: 0x80004e02 <- 0x1130015 +mem-write: 0x80004e06 <- 0x80670101 +mem-write: 0x80004e0a <- 0x1130000 +mem-write: 0x80004e0e <- 0x2c23fe01 +mem-write: 0x80004e12 <- 0x2a230081 +mem-write: 0x80004e16 <- 0x2e230091 +mem-write: 0x80004e1a <- 0x28230011 +mem-write: 0x80004e1e <- 0x26230121 +mem-write: 0x80004e22 <- 0x84930131 +mem-write: 0x80004e26 <- 0x4130005 +mem-write: 0x80004e2a <- 0xc4630005 +mem-write: 0x80004e2e <- 0x7930a05 +mem-write: 0x80004e32 <- 0x861300f0 +mem-write: 0x80004e36 <- 0x5130005 +mem-write: 0x80004e3a <- 0x6930045 +mem-write: 0x80004e3e <- 0x5930184 +mem-write: 0x80004e42 <- 0xd46300f0 +mem-write: 0x80004e46 <- 0x7930297 +mem-write: 0x80004e4a <- 0xd7030005 +mem-write: 0x80004e4e <- 0x87930027 +mem-write: 0x80004e52 <- 0x9f230027 +mem-write: 0x80004e56 <- 0x9ae3fee7 +mem-write: 0x80004e5a <- 0x1c23fed7 +mem-write: 0x80004e5e <- 0x6130004 +mem-write: 0x80004e62 <- 0xc2e3ff06 +mem-write: 0x80004e66 <- 0xf493fec5 +mem-write: 0x80004e6a <- 0x79300f4 +mem-write: 0x80004e6e <- 0xd8630070 +mem-write: 0x80004e72 <- 0x7130297 +mem-write: 0x80004e76 <- 0x5930184 +mem-write: 0x80004e7a <- 0x7930024 +mem-write: 0x80004e7e <- 0x56830000 +mem-write: 0x80004e82 <- 0x7130007 +mem-write: 0x80004e86 <- 0x9613ffe7 +mem-write: 0x80004e8a <- 0xe7b30086 +mem-write: 0x80004e8e <- 0x112300c7 +mem-write: 0x80004e92 <- 0xd79300f7 +mem-write: 0x80004e96 <- 0x14e30086 +mem-write: 0x80004e9a <- 0x8493feb7 +mem-write: 0x80004e9e <- 0x8a63ff84 +mem-write: 0x80004ea2 <- 0x84930004 +mem-write: 0x80004ea6 <- 0x513fff4 +mem-write: 0x80004eaa <- 0xf0ef0004 +mem-write: 0x80004eae <- 0x9ae3b79f +mem-write: 0x80004eb2 <- 0x513fe04 +mem-write: 0x80004eb6 <- 0x20830000 +mem-write: 0x80004eba <- 0x240301c1 +mem-write: 0x80004ebe <- 0x24830181 +mem-write: 0x80004ec2 <- 0x29030141 +mem-write: 0x80004ec6 <- 0x29830101 +mem-write: 0x80004eca <- 0x11300c1 +mem-write: 0x80004ece <- 0x80670201 +mem-write: 0x80004ed2 <- 0x7930000 +mem-write: 0x80004ed6 <- 0x933ff10 +mem-write: 0x80004eda <- 0xdc6340b0 +mem-write: 0x80004ede <- 0x59312f5 +mem-write: 0x80004ee2 <- 0x9930185 +mem-write: 0x80004ee6 <- 0x6930000 +mem-write: 0x80004eea <- 0x6130045 +mem-write: 0x80004eee <- 0x570300f0 +mem-write: 0x80004ef2 <- 0x87930184 +mem-write: 0x80004ef6 <- 0xe9b30005 +mem-write: 0x80004efa <- 0xd70300e9 +mem-write: 0x80004efe <- 0x8793ffe7 +mem-write: 0x80004f02 <- 0x9123ffe7 +mem-write: 0x80004f06 <- 0x9ae300e7 +mem-write: 0x80004f0a <- 0x1223fed7 +mem-write: 0x80004f0e <- 0x9130004 +mem-write: 0x80004f12 <- 0x4ee3ff09 +mem-write: 0x80004f16 <- 0x793fd26 +mem-write: 0x80004f1a <- 0x713ff00 +mem-write: 0x80004f1e <- 0x87b3ff10 +mem-write: 0x80004f22 <- 0x9134097 +mem-write: 0x80004f26 <- 0xc4630000 +mem-write: 0x80004f2a <- 0x9330ae4 +mem-write: 0x80004f2e <- 0x79300f9 +mem-write: 0x80004f32 <- 0xd6630070 +mem-write: 0x80004f36 <- 0x99930527 +mem-write: 0x80004f3a <- 0xd9930109 +mem-write: 0x80004f3e <- 0x47834109 +mem-write: 0x80004f42 <- 0x5930184 +mem-write: 0x80004f46 <- 0xe9b301a4 +mem-write: 0x80004f4a <- 0x999300f9 +mem-write: 0x80004f4e <- 0xd9930109 +mem-write: 0x80004f52 <- 0x7930109 +mem-write: 0x80004f56 <- 0xd6030000 +mem-write: 0x80004f5a <- 0x86930006 +mem-write: 0x80004f5e <- 0x57130026 +mem-write: 0x80004f62 <- 0xe7330086 +mem-write: 0x80004f66 <- 0x179300e7 +mem-write: 0x80004f6a <- 0x97930086 +mem-write: 0x80004f6e <- 0x9f230107 +mem-write: 0x80004f72 <- 0xd793fee6 +mem-write: 0x80004f76 <- 0x90e30107 +mem-write: 0x80004f7a <- 0x913feb6 +mem-write: 0x80004f7e <- 0xc63ff89 +mem-write: 0x80004f82 <- 0x57830609 +mem-write: 0x80004f86 <- 0x9130184 +mem-write: 0x80004f8a <- 0x513fff9 +mem-write: 0x80004f8e <- 0xf7930004 +mem-write: 0x80004f92 <- 0xe9b30017 +mem-write: 0x80004f96 <- 0xf0ef0137 +mem-write: 0x80004f9a <- 0x14e3a25f +mem-write: 0x80004f9e <- 0x9793fe09 +mem-write: 0x80004fa2 <- 0xd7930109 +mem-write: 0x80004fa6 <- 0x90634107 +mem-write: 0x80004faa <- 0x95130407 +mem-write: 0x80004fae <- 0x55130109 +mem-write: 0x80004fb2 <- 0x20830105 +mem-write: 0x80004fb6 <- 0x240301c1 +mem-write: 0x80004fba <- 0x24830181 +mem-write: 0x80004fbe <- 0x29030141 +mem-write: 0x80004fc2 <- 0x29830101 +mem-write: 0x80004fc6 <- 0x11300c1 +mem-write: 0x80004fca <- 0x80670201 +mem-write: 0x80004fce <- 0xf9130000 +mem-write: 0x80004fd2 <- 0x933ff07 +mem-write: 0x80004fd6 <- 0x9334120 +mem-write: 0x80004fda <- 0x79300f9 +mem-write: 0x80004fde <- 0xd0e30070 +mem-write: 0x80004fe2 <- 0xf06ffb27 +mem-write: 0x80004fe6 <- 0x993f55f +mem-write: 0x80004fea <- 0x95130010 +mem-write: 0x80004fee <- 0x55130109 +mem-write: 0x80004ff2 <- 0xf06f0105 +mem-write: 0x80004ff6 <- 0x8513fc1f +mem-write: 0x80004ffa <- 0x98630009 +VXDRV: upload 1024 bytes to 0x80004ffe +mem-write: 0x80004ffe <- 0x15130009 +mem-write: 0x80005002 <- 0x55130105 +mem-write: 0x80005006 <- 0xf06f0105 +mem-write: 0x8000500a <- 0x513eb1f +mem-write: 0x8000500e <- 0xf06f0010 +mem-write: 0x80005012 <- 0x793ff1f +mem-write: 0x80005016 <- 0x993ff90 +mem-write: 0x8000501a <- 0xd4e30000 +mem-write: 0x8000501e <- 0x693f6f5 +mem-write: 0x80005022 <- 0xf06f0044 +mem-write: 0x80005026 <- 0x5783f1df +mem-write: 0x8000502a <- 0x1130045 +mem-write: 0x8000502e <- 0x2223ff01 +mem-write: 0x80005032 <- 0x26230091 +mem-write: 0x80005036 <- 0x24230011 +mem-write: 0x8000503a <- 0x20230081 +mem-write: 0x8000503e <- 0x4930121 +mem-write: 0x80005042 <- 0x9c630005 +mem-write: 0x80005046 <- 0x57030c07 +mem-write: 0x8000504a <- 0x4130065 +mem-write: 0x8000504e <- 0x17930000 +mem-write: 0x80005052 <- 0xd7930107 +mem-write: 0x80005056 <- 0xc4634107 +mem-write: 0x8000505a <- 0x6930a07 +mem-write: 0x8000505e <- 0x61301a5 +mem-write: 0x80005062 <- 0x18630a00 +mem-write: 0x80005066 <- 0x87930207 +mem-write: 0x8000506a <- 0x6f0064 +mem-write: 0x8000506e <- 0xd7030080 +mem-write: 0x80005072 <- 0x87930007 +mem-write: 0x80005076 <- 0x9e230027 +mem-write: 0x8000507a <- 0x9ae3fee7 +mem-write: 0x8000507e <- 0x9c23fef6 +mem-write: 0x80005082 <- 0x4130004 +mem-write: 0x80005086 <- 0xc630104 +mem-write: 0x8000508a <- 0xd70306c4 +mem-write: 0x8000508e <- 0xce30064 +mem-write: 0x80005092 <- 0x7793fc07 +mem-write: 0x80005096 <- 0x9063f007 +mem-write: 0x8000509a <- 0x85130407 +mem-write: 0x8000509e <- 0x85930184 +mem-write: 0x800050a2 <- 0x7930024 +mem-write: 0x800050a6 <- 0x7130000 +mem-write: 0x800050aa <- 0x56830005 +mem-write: 0x800050ae <- 0x7130007 +mem-write: 0x800050b2 <- 0x9613ffe7 +mem-write: 0x800050b6 <- 0xe7b30086 +mem-write: 0x800050ba <- 0x112300c7 +mem-write: 0x800050be <- 0xd79300f7 +mem-write: 0x800050c2 <- 0x94e30086 +mem-write: 0x800050c6 <- 0xd703fee5 +mem-write: 0x800050ca <- 0x4130064 +mem-write: 0x800050ce <- 0x77930084 +mem-write: 0x800050d2 <- 0x88e3f007 +mem-write: 0x800050d6 <- 0x913fc07 +mem-write: 0x800050da <- 0x6f0a00 +mem-write: 0x800050de <- 0x4130140 +mem-write: 0x800050e2 <- 0xf0ef0014 +mem-write: 0x800050e6 <- 0x4c63941f +mem-write: 0x800050ea <- 0xd7030089 +mem-write: 0x800050ee <- 0x17130064 +mem-write: 0x800050f2 <- 0x57130107 +mem-write: 0x800050f6 <- 0x85134107 +mem-write: 0x800050fa <- 0x52e30004 +mem-write: 0x800050fe <- 0x2083fe07 +mem-write: 0x80005102 <- 0x51300c1 +mem-write: 0x80005106 <- 0x24030004 +mem-write: 0x8000510a <- 0x24830081 +mem-write: 0x8000510e <- 0x29030041 +mem-write: 0x80005112 <- 0x1130001 +mem-write: 0x80005116 <- 0x80670101 +mem-write: 0x8000511a <- 0xf7130000 +mem-write: 0x8000511e <- 0x413f007 +mem-write: 0x80005122 <- 0x10630000 +mem-write: 0x80005126 <- 0x9130407 +mem-write: 0x8000512a <- 0x6ff6f0 +mem-write: 0x8000512e <- 0x4130140 +mem-write: 0x80005132 <- 0xf0effff4 +mem-write: 0x80005136 <- 0x4e3889f +mem-write: 0x8000513a <- 0xd783fd24 +mem-write: 0x8000513e <- 0x85130044 +mem-write: 0x80005142 <- 0x96e30004 +mem-write: 0x80005146 <- 0x2083fe07 +mem-write: 0x8000514a <- 0x51300c1 +mem-write: 0x8000514e <- 0x24030004 +mem-write: 0x80005152 <- 0x24830081 +mem-write: 0x80005156 <- 0x29030041 +mem-write: 0x8000515a <- 0x1130001 +mem-write: 0x8000515e <- 0x80670101 +mem-write: 0x80005162 <- 0x6930000 +mem-write: 0x80005166 <- 0x5930045 +mem-write: 0x8000516a <- 0x71301a5 +mem-write: 0x8000516e <- 0x6f0000 +mem-write: 0x80005172 <- 0xd7830080 +mem-write: 0x80005176 <- 0xd6130006 +mem-write: 0x8000517a <- 0x67330087 +mem-write: 0x8000517e <- 0x979300c7 +mem-write: 0x80005182 <- 0x90230087 +mem-write: 0x80005186 <- 0x971300e6 +mem-write: 0x8000518a <- 0x86930107 +mem-write: 0x8000518e <- 0x57130026 +mem-write: 0x80005192 <- 0x90e30107 +mem-write: 0x80005196 <- 0xd783feb6 +mem-write: 0x8000519a <- 0x4130044 +mem-write: 0x8000519e <- 0xf06fff80 +mem-write: 0x800051a2 <- 0x113f89f +mem-write: 0x800051a6 <- 0x2c23fe01 +mem-write: 0x800051aa <- 0x2a230081 +mem-write: 0x800051ae <- 0x28230091 +mem-write: 0x800051b2 <- 0x26230121 +mem-write: 0x800051b6 <- 0x24230131 +mem-write: 0x800051ba <- 0x22230141 +mem-write: 0x800051be <- 0x89130151 +mem-write: 0x800051c2 <- 0x84930006 +mem-write: 0x800051c6 <- 0x2e230007 +mem-write: 0x800051ca <- 0x4130011 +mem-write: 0x800051ce <- 0x89930005 +mem-write: 0x800051d2 <- 0xa130005 +mem-write: 0x800051d6 <- 0xa930006 +mem-write: 0x800051da <- 0xf0ef0007 +mem-write: 0x800051de <- 0x793e4df +mem-write: 0x800051e2 <- 0x9330900 +mem-write: 0x800051e6 <- 0xdc6340a9 +mem-write: 0x800051ea <- 0x87b716a7 +mem-write: 0x800051ee <- 0x87930000 +mem-write: 0x800051f2 <- 0xda63ffe7 +mem-write: 0x800051f6 <- 0x84631f27 +mem-write: 0x800051fa <- 0xa5031c0a +mem-write: 0x800051fe <- 0xa7830044 +mem-write: 0x80005202 <- 0xa630004 +mem-write: 0x80005206 <- 0x871306f5 +mem-write: 0x8000520a <- 0x879301a4 +mem-write: 0x8000520e <- 0x7130344 +mem-write: 0x80005212 <- 0x1f230027 +mem-write: 0x80005216 <- 0x1ce3fe07 +mem-write: 0x8000521a <- 0x793fef7 +mem-write: 0x8000521e <- 0xc630380 +mem-write: 0x80005222 <- 0xd06332f5 +mem-write: 0x80005226 <- 0x79316a7 +mem-write: 0x8000522a <- 0xc630400 +mem-write: 0x8000522e <- 0x7932ef5 +mem-write: 0x80005232 <- 0x18630710 +mem-write: 0x80005236 <- 0x87b734f5 +mem-write: 0x8000523a <- 0x87934000 +mem-write: 0x8000523e <- 0x713fff7 +mem-write: 0x80005242 <- 0xaa2300a0 +mem-write: 0x80005246 <- 0x87b700f4 +mem-write: 0x8000524a <- 0xa423ffff +mem-write: 0x8000524e <- 0x9c2300e4 +mem-write: 0x80005252 <- 0xa62300f4 +mem-write: 0x80005256 <- 0x79300e4 +mem-write: 0x8000525a <- 0x873700a0 +mem-write: 0x8000525e <- 0x87930000 +mem-write: 0x80005262 <- 0x97930087 +mem-write: 0x80005266 <- 0x87b30017 +mem-write: 0x8000526a <- 0x952300f4 +mem-write: 0x8000526e <- 0xa02300e7 +mem-write: 0x80005272 <- 0x586300a4 +mem-write: 0x80005276 <- 0xa5831b20 +mem-write: 0x8000527a <- 0xd7830084 +mem-write: 0x8000527e <- 0x8130144 +mem-write: 0x80005282 <- 0x961308f0 +mem-write: 0x80005286 <- 0x6330015 +mem-write: 0x8000528a <- 0x570300c4 +mem-write: 0x8000528e <- 0x76b30006 +mem-write: 0x80005292 <- 0x4a6300f7 +mem-write: 0x80005296 <- 0x81302a8 +mem-write: 0x8000529a <- 0x466300b0 +mem-write: 0x8000529e <- 0x79302b8 +mem-write: 0x800052a2 <- 0x5930006 +mem-write: 0x800052a6 <- 0xd7030184 +mem-write: 0x800052aa <- 0x4630027 +mem-write: 0x800052ae <- 0xe6930007 +mem-write: 0x800052b2 <- 0x91230016 +mem-write: 0x800052b6 <- 0x87930007 +mem-write: 0x800052ba <- 0x96e30027 +mem-write: 0x800052be <- 0x5703fef5 +mem-write: 0x800052c2 <- 0xd7830006 +mem-write: 0x800052c6 <- 0xc7930144 +mem-write: 0x800052ca <- 0xf7b3fff7 +mem-write: 0x800052ce <- 0x102300e7 +mem-write: 0x800052d2 <- 0xd78300f6 +mem-write: 0x800052d6 <- 0xf7330164 +mem-write: 0x800052da <- 0x6300d7 +mem-write: 0x800052de <- 0x84630407 +mem-write: 0x800052e2 <- 0x86131ad7 +mem-write: 0x800052e6 <- 0x6930324 +mem-write: 0x800052ea <- 0x84930184 +mem-write: 0x800052ee <- 0x71301c4 +mem-write: 0x800052f2 <- 0x57830000 +mem-write: 0x800052f6 <- 0xd5830006 +mem-write: 0x800052fa <- 0x86930006 +mem-write: 0x800052fe <- 0x613ffe6 +mem-write: 0x80005302 <- 0x87b3ffe6 +mem-write: 0x80005306 <- 0x87b300b7 +mem-write: 0x8000530a <- 0xd71300e7 +mem-write: 0x8000530e <- 0x91230107 +mem-write: 0x80005312 <- 0x771300f6 +mem-write: 0x80005316 <- 0x1ee30017 +mem-write: 0x8000531a <- 0x5863fc96 +mem-write: 0x8000531e <- 0x57831920 +mem-write: 0x80005322 <- 0x9e630044 +mem-write: 0x80005326 <- 0x87b71207 +mem-write: 0x8000532a <- 0x1c230000 +mem-write: 0x8000532e <- 0x87930004 +mem-write: 0x80005332 <- 0xc863ffe7 +mem-write: 0x80005336 <- 0x11230927 +mem-write: 0x8000533a <- 0x20830124 +mem-write: 0x8000533e <- 0x240301c1 +mem-write: 0x80005342 <- 0x24830181 +mem-write: 0x80005346 <- 0x29030141 +mem-write: 0x8000534a <- 0x29830101 +mem-write: 0x8000534e <- 0x2a0300c1 +mem-write: 0x80005352 <- 0x2a830081 +mem-write: 0x80005356 <- 0x1130041 +mem-write: 0x8000535a <- 0x80670201 +mem-write: 0x8000535e <- 0x54630000 +mem-write: 0x80005362 <- 0x7930e09 +mem-write: 0x80005366 <- 0x5c63f700 +mem-write: 0x8000536a <- 0x79308f9 +mem-write: 0x8000536e <- 0x4130024 +mem-write: 0x80005372 <- 0x879301a4 +mem-write: 0x80005376 <- 0x9f230027 +mem-write: 0x8000537a <- 0x9ce3fe07 +mem-write: 0x8000537e <- 0xf06ffe87 +mem-write: 0x80005382 <- 0x793fbdf +mem-write: 0x80005386 <- 0x8630180 +mem-write: 0x8000538a <- 0x79316f5 +mem-write: 0x8000538e <- 0x1a630350 +mem-write: 0x80005392 <- 0x17371ef5 +mem-write: 0x80005396 <- 0x7b70000 +mem-write: 0x8000539a <- 0x6930400 +mem-write: 0x8000539e <- 0x87930060 +mem-write: 0x800053a2 <- 0x7137ff7 +mem-write: 0x800053a6 <- 0xaa238007 +mem-write: 0x800053aa <- 0xa42300f4 +mem-write: 0x800053ae <- 0x9c2300d4 +mem-write: 0x800053b2 <- 0xa62300e4 +mem-write: 0x800053b6 <- 0x79300d4 +mem-write: 0x800053ba <- 0xf06f0060 +mem-write: 0x800053be <- 0x1c23ea5f +mem-write: 0x800053c2 <- 0x87b70004 +mem-write: 0x800053c6 <- 0xc793ffff +mem-write: 0x800053ca <- 0x1123fff7 +mem-write: 0x800053ce <- 0x79300f4 +mem-write: 0x800053d2 <- 0x4130044 +mem-write: 0x800053d6 <- 0x90230184 +mem-write: 0x800053da <- 0x87930007 +mem-write: 0x800053de <- 0x1ce30027 +mem-write: 0x800053e2 <- 0xf06ffef4 +mem-write: 0x800053e6 <- 0x793f59f +mem-write: 0x800053ea <- 0x4130024 +mem-write: 0x800053ee <- 0x879301a4 +mem-write: 0x800053f2 <- 0x9f230027 +mem-write: 0x800053f6 <- 0x9ce3fe07 +mem-write: 0x800053fa <- 0xf06ffe87 +VXDRV: upload 1024 bytes to 0x800053fe +mem-write: 0x800053fe <- 0x593f41f +mem-write: 0x80005402 <- 0x5130009 +mem-write: 0x80005406 <- 0xf0ef0004 +mem-write: 0x8000540a <- 0x463a05f +mem-write: 0x8000540e <- 0x9930005 +mem-write: 0x80005412 <- 0x8c630010 +mem-write: 0x80005416 <- 0xa5030c0a +mem-write: 0x8000541a <- 0xa7830044 +mem-write: 0x8000541e <- 0x14e30004 +mem-write: 0x80005422 <- 0x793def5 +mem-write: 0x80005426 <- 0x4630900 +mem-write: 0x8000542a <- 0x57830af5 +mem-write: 0x8000542e <- 0x5130184 +mem-write: 0x80005432 <- 0xf7930004 +mem-write: 0x80005436 <- 0xe9b30017 +mem-write: 0x8000543a <- 0xf0ef00f9 +mem-write: 0x8000543e <- 0xa503d80f +mem-write: 0x80005442 <- 0xf06f0044 +mem-write: 0x80005446 <- 0x80e3e35f +mem-write: 0x8000544a <- 0xa503ee0a +mem-write: 0x8000544e <- 0xa7830044 +mem-write: 0x80005452 <- 0x1ae30004 +mem-write: 0x80005456 <- 0x40e3daf5 +mem-write: 0x8000545a <- 0xf06fe320 +mem-write: 0x8000545e <- 0x513fc9f +mem-write: 0x80005462 <- 0xf0ef0004 +mem-write: 0x80005466 <- 0x87b7d58f +mem-write: 0x8000546a <- 0x9130000 +mem-write: 0x8000546e <- 0x1c230019 +mem-write: 0x80005472 <- 0x87930004 +mem-write: 0x80005476 <- 0xc6e3ffe7 +mem-write: 0x8000547a <- 0x5ee3f527 +mem-write: 0x8000547e <- 0x1123ea09 +mem-write: 0x80005482 <- 0xf06f0004 +mem-write: 0x80005486 <- 0x9463eb9f +mem-write: 0x8000548a <- 0xa7830c09 +mem-write: 0x8000548e <- 0xd70300c4 +mem-write: 0x80005492 <- 0x97930184 +mem-write: 0x80005496 <- 0x7b30017 +mem-write: 0x8000549a <- 0xd78300f4 +mem-write: 0x8000549e <- 0xf7b30007 +mem-write: 0x800054a2 <- 0x90e300e7 +mem-write: 0x800054a6 <- 0x4ce3e407 +mem-write: 0x800054aa <- 0x793e720 +mem-write: 0x800054ae <- 0x6630900 +mem-write: 0x800054b2 <- 0x51300f5 +mem-write: 0x800054b6 <- 0xf0ef0004 +mem-write: 0x800054ba <- 0x5783d6cf +mem-write: 0x800054be <- 0x90e30044 +mem-write: 0x800054c2 <- 0x1c23fa07 +mem-write: 0x800054c6 <- 0x4ce30004 +mem-write: 0x800054ca <- 0xf06ffa09 +mem-write: 0x800054ce <- 0xa603e6df +mem-write: 0x800054d2 <- 0xd7830084 +mem-write: 0x800054d6 <- 0x16130144 +mem-write: 0x800054da <- 0x6330016 +mem-write: 0x800054de <- 0x570300c4 +mem-write: 0x800054e2 <- 0xf6b30006 +mem-write: 0x800054e6 <- 0xf06f00e7 +mem-write: 0x800054ea <- 0x1c23de1f +mem-write: 0x800054ee <- 0x11230004 +mem-write: 0x800054f2 <- 0xf06f0004 +mem-write: 0x800054f6 <- 0x7b7e49f +mem-write: 0x800054fa <- 0x87930080 +mem-write: 0x800054fe <- 0x7130ff7 +mem-write: 0x80005502 <- 0xaa230040 +mem-write: 0x80005506 <- 0x79300f4 +mem-write: 0x8000550a <- 0xa4231000 +mem-write: 0x8000550e <- 0x9c2300e4 +mem-write: 0x80005512 <- 0xa62300f4 +mem-write: 0x80005516 <- 0x79300e4 +mem-write: 0x8000551a <- 0x7130040 +mem-write: 0x8000551e <- 0xf06f1000 +mem-write: 0x80005522 <- 0x793d41f +mem-write: 0x80005526 <- 0xa4230070 +mem-write: 0x8000552a <- 0x7b700f4 +mem-write: 0x8000552e <- 0x87938001 +mem-write: 0x80005532 <- 0xaa23fff7 +mem-write: 0x80005536 <- 0x79300f4 +mem-write: 0x8000553a <- 0x9c230010 +mem-write: 0x8000553e <- 0x79300f4 +mem-write: 0x80005542 <- 0xa6230060 +mem-write: 0x80005546 <- 0x71300f4 +mem-write: 0x8000554a <- 0xf06f0010 +mem-write: 0x8000554e <- 0xae3d15f +mem-write: 0x80005552 <- 0xf06fd80a +mem-write: 0x80005556 <- 0x7b7dc9f +mem-write: 0x8000555a <- 0x87930080 +mem-write: 0x8000555e <- 0x7130ff7 +mem-write: 0x80005562 <- 0xaa230060 +mem-write: 0x80005566 <- 0x79300f4 +mem-write: 0x8000556a <- 0xa4231000 +mem-write: 0x8000556e <- 0x9c2300e4 +mem-write: 0x80005572 <- 0xa62300f4 +mem-write: 0x80005576 <- 0x79300e4 +mem-write: 0x8000557a <- 0x7130060 +mem-write: 0x8000557e <- 0xf06f1000 +mem-write: 0x80005582 <- 0x793ce1f +mem-write: 0x80005586 <- 0xa42300c0 +mem-write: 0x8000558a <- 0x7b700f4 +mem-write: 0x8000558e <- 0x87938001 +mem-write: 0x80005592 <- 0xaa23fff7 +mem-write: 0x80005596 <- 0x79300f4 +mem-write: 0x8000559a <- 0x9c230010 +mem-write: 0x8000559e <- 0x79300f4 +mem-write: 0x800055a2 <- 0xa62300b0 +mem-write: 0x800055a6 <- 0x71300f4 +mem-write: 0x800055aa <- 0xf06f0010 +mem-write: 0x800055ae <- 0x113cb5f +mem-write: 0x800055b2 <- 0x2223fd01 +mem-write: 0x800055b6 <- 0x2e230291 +mem-write: 0x800055ba <- 0x84930131 +mem-write: 0x800055be <- 0x59830005 +mem-write: 0x800055c2 <- 0x26230025 +mem-write: 0x800055c6 <- 0x24230211 +mem-write: 0x800055ca <- 0x20230281 +mem-write: 0x800055ce <- 0x2c230321 +mem-write: 0x800055d2 <- 0x9130141 +mem-write: 0x800055d6 <- 0x2a230006 +mem-write: 0x800055da <- 0x28230151 +mem-write: 0x800055de <- 0x26230161 +mem-write: 0x800055e2 <- 0x24230171 +mem-write: 0x800055e6 <- 0x22230181 +mem-write: 0x800055ea <- 0x20230191 +mem-write: 0x800055ee <- 0xa1301a1 +mem-write: 0x800055f2 <- 0xf0ef0005 +mem-write: 0x800055f6 <- 0xd403a35f +mem-write: 0x800055fa <- 0x7930024 +mem-write: 0x800055fe <- 0x85130005 +mem-write: 0x80005602 <- 0x89b30004 +mem-write: 0x80005606 <- 0xa9340f9 +mem-write: 0x8000560a <- 0xf0ef0349 +mem-write: 0x8000560e <- 0x433a1df +mem-write: 0x80005612 <- 0x71340a4 +mem-write: 0x80005616 <- 0x879304e9 +mem-write: 0x8000561a <- 0x8793000a +mem-write: 0x8000561e <- 0x9f230027 +mem-write: 0x80005622 <- 0x9ce3fe07 +mem-write: 0x80005626 <- 0x4a63fee7 +mem-write: 0x8000562a <- 0xb930934 +mem-write: 0x8000562e <- 0x8b13004a +mem-write: 0x80005632 <- 0x89930044 +mem-write: 0x80005636 <- 0xc93fff9 +mem-write: 0x8000563a <- 0x8c1301aa +mem-write: 0x8000563e <- 0x7130024 +mem-write: 0x80005642 <- 0x8793000b +mem-write: 0x80005646 <- 0xd603000b +mem-write: 0x8000564a <- 0x56830007 +mem-write: 0x8000564e <- 0x87930007 +mem-write: 0x80005652 <- 0x7130027 +mem-write: 0x80005656 <- 0x1a630027 +mem-write: 0x8000565a <- 0x96e30ad6 +mem-write: 0x8000565e <- 0x613ff97 +mem-write: 0x80005662 <- 0x8713018a +mem-write: 0x80005666 <- 0x6930184 +mem-write: 0x8000566a <- 0x57830000 +mem-write: 0x8000566e <- 0x55830007 +mem-write: 0x80005672 <- 0x7130006 +mem-write: 0x80005676 <- 0x87b3ffe7 +mem-write: 0x8000567a <- 0x87b340d7 +mem-write: 0x8000567e <- 0xd69340b7 +mem-write: 0x80005682 <- 0x11230107 +mem-write: 0x80005686 <- 0xf69300f7 +mem-write: 0x8000568a <- 0x6130016 +mem-write: 0x8000568e <- 0x1ee3ffe6 +mem-write: 0x80005692 <- 0xd13fcec +mem-write: 0x80005696 <- 0x85130010 +mem-write: 0x8000569a <- 0xf0ef000a +mem-write: 0x8000569e <- 0x5783b88f +mem-write: 0x800056a2 <- 0x41304c9 +mem-write: 0x800056a6 <- 0x8513fff4 +mem-write: 0x800056aa <- 0x6d330004 +mem-write: 0x800056ae <- 0x162300fd +mem-write: 0x800056b2 <- 0xf0ef05a9 +mem-write: 0x800056b6 <- 0x14e3b70f +mem-write: 0x800056ba <- 0x693f934 +mem-write: 0x800056be <- 0x24030004 +mem-write: 0x800056c2 <- 0x20830281 +mem-write: 0x800056c6 <- 0x298302c1 +mem-write: 0x800056ca <- 0x2a0301c1 +mem-write: 0x800056ce <- 0x2a830181 +mem-write: 0x800056d2 <- 0x2b030141 +mem-write: 0x800056d6 <- 0x2b830101 +mem-write: 0x800056da <- 0x2c0300c1 +mem-write: 0x800056de <- 0x2c830081 +mem-write: 0x800056e2 <- 0x2d030041 +mem-write: 0x800056e6 <- 0x7930001 +mem-write: 0x800056ea <- 0x85130009 +mem-write: 0x800056ee <- 0x29030004 +mem-write: 0x800056f2 <- 0x24830201 +mem-write: 0x800056f6 <- 0x7130241 +mem-write: 0x800056fa <- 0x6130000 +mem-write: 0x800056fe <- 0x5930000 +mem-write: 0x80005702 <- 0x1130000 +mem-write: 0x80005706 <- 0xf06f0301 +mem-write: 0x8000570a <- 0xd13a9df +mem-write: 0x8000570e <- 0xe4e30000 +mem-write: 0x80005712 <- 0xf06ff8c6 +mem-write: 0x80005716 <- 0x5703f4df +mem-write: 0x8000571a <- 0x57830005 +mem-write: 0x8000571e <- 0x6630025 +mem-write: 0x80005722 <- 0x87370007 +mem-write: 0x80005726 <- 0xe7b30000 +mem-write: 0x8000572a <- 0x992300e7 +mem-write: 0x8000572e <- 0x570300f5 +mem-write: 0x80005732 <- 0x87b70025 +mem-write: 0x80005736 <- 0x87930000 +mem-write: 0x8000573a <- 0x463fff7 +mem-write: 0x8000573e <- 0x79302f7 +mem-write: 0x80005742 <- 0x85930065 +mem-write: 0x80005746 <- 0x5130105 +mem-write: 0x8000574a <- 0xd7030185 +mem-write: 0x8000574e <- 0x87930007 +mem-write: 0x80005752 <- 0x85930027 +mem-write: 0x80005756 <- 0x9123ffe5 +mem-write: 0x8000575a <- 0x98e300e5 +mem-write: 0x8000575e <- 0x8067fea7 +mem-write: 0x80005762 <- 0x7930000 +mem-write: 0x80005766 <- 0x5130065 +mem-write: 0x8000576a <- 0xd70301a5 +mem-write: 0x8000576e <- 0x87930007 +mem-write: 0x80005772 <- 0x1a630027 +mem-write: 0x80005776 <- 0x9ae30207 +mem-write: 0x8000577a <- 0x8713fea7 +mem-write: 0x8000577e <- 0x87930125 +mem-write: 0x80005782 <- 0x87930005 +mem-write: 0x80005786 <- 0x9f230027 +mem-write: 0x8000578a <- 0x1ce3fe07 +mem-write: 0x8000578e <- 0xd783fef7 +mem-write: 0x80005792 <- 0x87370125 +mem-write: 0x80005796 <- 0x7130000 +mem-write: 0x8000579a <- 0xe7b3fff7 +mem-write: 0x8000579e <- 0x992300e7 +mem-write: 0x800057a2 <- 0x806700f5 +mem-write: 0x800057a6 <- 0x87130000 +mem-write: 0x800057aa <- 0x87930105 +mem-write: 0x800057ae <- 0x87930005 +mem-write: 0x800057b2 <- 0x9f230027 +mem-write: 0x800057b6 <- 0x1ce3fe07 +mem-write: 0x800057ba <- 0xc7b7fef7 +mem-write: 0x800057be <- 0xa8237fff +mem-write: 0x800057c2 <- 0x806700f5 +mem-write: 0x800057c6 <- 0x1130000 +mem-write: 0x800057ca <- 0x2823f701 +mem-write: 0x800057ce <- 0x5b030761 +mem-write: 0x800057d2 <- 0x87b70125 +mem-write: 0x800057d6 <- 0x87930000 +mem-write: 0x800057da <- 0x2c23fff7 +mem-write: 0x800057de <- 0xfa330741 +mem-write: 0x800057e2 <- 0x1a130167 +mem-write: 0x800057e6 <- 0x2423010a +mem-write: 0x800057ea <- 0x22230881 +mem-write: 0x800057ee <- 0x20230891 +mem-write: 0x800057f2 <- 0x2e230921 +mem-write: 0x800057f6 <- 0x26230731 +mem-write: 0x800057fa <- 0x2a230811 +VXDRV: upload 1024 bytes to 0x800057fe +mem-write: 0x800057fe <- 0x26230751 +mem-write: 0x80005802 <- 0x24230771 +mem-write: 0x80005806 <- 0x22230781 +mem-write: 0x8000580a <- 0x5a130791 +mem-write: 0x8000580e <- 0x493010a +mem-write: 0x80005812 <- 0x89130005 +mem-write: 0x80005816 <- 0x4130005 +mem-write: 0x8000581a <- 0x89930006 +mem-write: 0x8000581e <- 0x12630006 +mem-write: 0x80005822 <- 0xf0ef10fa +mem-write: 0x80005826 <- 0x1a63b08f +mem-write: 0x8000582a <- 0x5a832805 +mem-write: 0x8000582e <- 0x77b30129 +mem-write: 0x80005832 <- 0x8263015a +mem-write: 0x80005836 <- 0x85132b47 +mem-write: 0x8000583a <- 0xf0ef0004 +mem-write: 0x8000583e <- 0xe63db4f +mem-write: 0x80005842 <- 0x55b72e05 +mem-write: 0x80005846 <- 0x85938001 +mem-write: 0x8000584a <- 0x513c205 +mem-write: 0x8000584e <- 0xf0ef0009 +mem-write: 0x80005852 <- 0x663c84f +mem-write: 0x80005856 <- 0x5a833605 +mem-write: 0x8000585a <- 0x87b70129 +mem-write: 0x8000585e <- 0x87930000 +mem-write: 0x80005862 <- 0xfab3fff7 +mem-write: 0x80005866 <- 0x9a930157 +mem-write: 0x8000586a <- 0xda93010a +mem-write: 0x8000586e <- 0x9463010a +mem-write: 0x80005872 <- 0x5132cfa +mem-write: 0x80005876 <- 0xf0ef0009 +mem-write: 0x8000587a <- 0x1063d78f +mem-write: 0x8000587e <- 0xd7833205 +mem-write: 0x80005882 <- 0xf7b30124 +mem-write: 0x80005886 <- 0x986300fa +mem-write: 0x8000588a <- 0x85130b57 +mem-write: 0x8000588e <- 0xf0ef0004 +mem-write: 0x80005892 <- 0x1863d60f +mem-write: 0x80005896 <- 0x5130005 +mem-write: 0x8000589a <- 0xf0ef0009 +mem-write: 0x8000589e <- 0xc63d54f +mem-write: 0x800058a2 <- 0x85130805 +mem-write: 0x800058a6 <- 0xf0ef0004 +mem-write: 0x800058aa <- 0x493af4f +mem-write: 0x800058ae <- 0x5130005 +mem-write: 0x800058b2 <- 0xf0ef0009 +mem-write: 0x800058b6 <- 0x84b3ae8f +mem-write: 0x800058ba <- 0x34b340a4 +mem-write: 0x800058be <- 0x94930090 +mem-write: 0x800058c2 <- 0x192300f4 +mem-write: 0x800058c6 <- 0x7130094 +mem-write: 0x800058ca <- 0x7930124 +mem-write: 0x800058ce <- 0x87930004 +mem-write: 0x800058d2 <- 0x9f230027 +mem-write: 0x800058d6 <- 0x1ce3fe07 +mem-write: 0x800058da <- 0x5783fef7 +mem-write: 0x800058de <- 0x87370124 +mem-write: 0x800058e2 <- 0x7130000 +mem-write: 0x800058e6 <- 0xe7b3fff7 +mem-write: 0x800058ea <- 0x192300e7 +mem-write: 0x800058ee <- 0x208300f4 +mem-write: 0x800058f2 <- 0x240308c1 +mem-write: 0x800058f6 <- 0x24830881 +mem-write: 0x800058fa <- 0x29030841 +mem-write: 0x800058fe <- 0x29830801 +mem-write: 0x80005902 <- 0x2a0307c1 +mem-write: 0x80005906 <- 0x2a830781 +mem-write: 0x8000590a <- 0x2b030741 +mem-write: 0x8000590e <- 0x2b830701 +mem-write: 0x80005912 <- 0x2c0306c1 +mem-write: 0x80005916 <- 0x2c830681 +mem-write: 0x8000591a <- 0x1130641 +mem-write: 0x8000591e <- 0x80670901 +mem-write: 0x80005922 <- 0xda830000 +mem-write: 0x80005926 <- 0xf7330125 +mem-write: 0x8000592a <- 0x17130157 +mem-write: 0x8000592e <- 0x57130107 +mem-write: 0x80005932 <- 0xa630107 +mem-write: 0x80005936 <- 0x851304f7 +mem-write: 0x8000593a <- 0x5930004 +mem-write: 0x8000593e <- 0xf0ef00c1 +mem-write: 0x80005942 <- 0x513a9cf +mem-write: 0x80005946 <- 0x5930009 +mem-write: 0x8000594a <- 0xf0ef0281 +mem-write: 0x8000594e <- 0x5483a90f +mem-write: 0x80005952 <- 0x590300e1 +mem-write: 0x80005956 <- 0x9c6302a1 +mem-write: 0x8000595a <- 0x7930404 +mem-write: 0x8000595e <- 0x6930101 +mem-write: 0x80005962 <- 0x88630241 +mem-write: 0x80005966 <- 0xd70320d7 +mem-write: 0x8000596a <- 0x87930007 +mem-write: 0x8000596e <- 0xae30027 +mem-write: 0x80005972 <- 0x513fe07 +mem-write: 0x80005976 <- 0xf0ef00c1 +mem-write: 0x8000597a <- 0x5703eb0f +mem-write: 0x8000597e <- 0x4b302a1 +mem-write: 0x80005982 <- 0x6f40a0 +mem-write: 0x80005986 <- 0x85130300 +mem-write: 0x8000598a <- 0xf0ef0005 +mem-write: 0x8000598e <- 0x6e39a0f +mem-write: 0x80005992 <- 0x713ec05 +mem-write: 0x80005996 <- 0x57830149 +mem-write: 0x8000599a <- 0x9130009 +mem-write: 0x8000599e <- 0x4130029 +mem-write: 0x800059a2 <- 0x1f230024 +mem-write: 0x800059a6 <- 0x18e3fef4 +mem-write: 0x800059aa <- 0xf06ffee9 +mem-write: 0x800059ae <- 0x713f45f +mem-write: 0x800059b2 <- 0xa930009 +mem-write: 0x800059b6 <- 0x7930009 +mem-write: 0x800059ba <- 0x69302c1 +mem-write: 0x800059be <- 0x12630401 +mem-write: 0x800059c2 <- 0x82630207 +mem-write: 0x800059c6 <- 0xd7031cf6 +mem-write: 0x800059ca <- 0x87930007 +mem-write: 0x800059ce <- 0xae30027 +mem-write: 0x800059d2 <- 0x513fe07 +mem-write: 0x800059d6 <- 0xf0ef0281 +mem-write: 0x800059da <- 0x5703e50f +mem-write: 0x800059de <- 0xab302a1 +mem-write: 0x800059e2 <- 0x578340a9 +mem-write: 0x800059e6 <- 0x8c130281 +mem-write: 0x800059ea <- 0x9b230389 +mem-write: 0x800059ee <- 0x9a2302e9 +mem-write: 0x800059f2 <- 0x871302f9 +mem-write: 0x800059f6 <- 0x79304e9 +mem-write: 0x800059fa <- 0x9023000c +mem-write: 0x800059fe <- 0x87930007 +mem-write: 0x80005a02 <- 0x1ce30027 +mem-write: 0x80005a06 <- 0x8a13fef7 +mem-write: 0x80005a0a <- 0xb9304c9 +mem-write: 0x80005a0e <- 0x9130000 +mem-write: 0x80005a12 <- 0xc930241 +mem-write: 0x80005a16 <- 0xb130101 +mem-write: 0x80005a1a <- 0x55030461 +mem-write: 0x80005a1e <- 0x9130009 +mem-write: 0x80005a22 <- 0x1863ffe9 +mem-write: 0x80005a26 <- 0xd7030c05 +mem-write: 0x80005a2a <- 0x79304c9 +mem-write: 0x80005a2e <- 0xebb3000a +mem-write: 0x80005a32 <- 0xd70300eb +mem-write: 0x80005a36 <- 0x8793ffe7 +mem-write: 0x80005a3a <- 0x9123ffe7 +mem-write: 0x80005a3e <- 0x9ae300e7 +mem-write: 0x80005a42 <- 0x9c23ff87 +mem-write: 0x80005a46 <- 0x1ae30209 +mem-write: 0x80005a4a <- 0x8713fd99 +mem-write: 0x80005a4e <- 0x7930349 +mem-write: 0x80005a52 <- 0x5930281 +mem-write: 0x80005a56 <- 0x56030421 +mem-write: 0x80005a5a <- 0x87930007 +mem-write: 0x80005a5e <- 0x7130027 +mem-write: 0x80005a62 <- 0x9f230027 +mem-write: 0x80005a66 <- 0x98e3fec7 +mem-write: 0x80005a6a <- 0xc6b7fef5 +mem-write: 0x80005a6e <- 0x84b3ffff +mem-write: 0x80005a72 <- 0x86930154 +mem-write: 0x80005a76 <- 0x85930026 +mem-write: 0x80005a7a <- 0x513000b +mem-write: 0x80005a7e <- 0x87930281 +mem-write: 0x80005a82 <- 0x7130009 +mem-write: 0x80005a86 <- 0x86b30400 +mem-write: 0x80005a8a <- 0x61300d4 +mem-write: 0x80005a8e <- 0xf0ef0000 +mem-write: 0x80005a92 <- 0x5703f14f +mem-write: 0x80005a96 <- 0x57830281 +mem-write: 0x80005a9a <- 0x59300c1 +mem-write: 0x80005a9e <- 0x5130004 +mem-write: 0x80005aa2 <- 0x87b30281 +mem-write: 0x80005aa6 <- 0x37b340e7 +mem-write: 0x80005aaa <- 0x7b300f0 +mem-write: 0x80005aae <- 0x142340f0 +mem-write: 0x80005ab2 <- 0xf0ef02f1 +mem-write: 0x80005ab6 <- 0xf06fc65f +mem-write: 0x80005aba <- 0x8713e39f +mem-write: 0x80005abe <- 0xd7830144 +mem-write: 0x80005ac2 <- 0x84930004 +mem-write: 0x80005ac6 <- 0x4130024 +mem-write: 0x80005aca <- 0x1f230024 +mem-write: 0x80005ace <- 0x98e3fef4 +mem-write: 0x80005ad2 <- 0xf06ffee4 +mem-write: 0x80005ad6 <- 0x513e1df +mem-write: 0x80005ada <- 0xf0ef0009 +mem-write: 0x80005ade <- 0x1ae3850f +mem-write: 0x80005ae2 <- 0x8513ea05 +mem-write: 0x80005ae6 <- 0xf0ef0004 +mem-write: 0x80005aea <- 0x8e3b08f +mem-write: 0x80005aee <- 0xf06fd605 +mem-write: 0x80005af2 <- 0x613d55f +mem-write: 0x80005af6 <- 0x5930441 +mem-write: 0x80005afa <- 0xe0ef0281 +mem-write: 0x80005afe <- 0x593f99f +mem-write: 0x80005b02 <- 0x613000a +mem-write: 0x80005b06 <- 0x7130000 +mem-write: 0x80005b0a <- 0xd80305c1 +mem-write: 0x80005b0e <- 0x57830005 +mem-write: 0x80005b12 <- 0x85930007 +mem-write: 0x80005b16 <- 0x713ffe5 +mem-write: 0x80005b1a <- 0x87b3ffe7 +mem-write: 0x80005b1e <- 0x87b30107 +mem-write: 0x80005b22 <- 0xd61300c7 +mem-write: 0x80005b26 <- 0x91230107 +mem-write: 0x80005b2a <- 0x761300f5 +mem-write: 0x80005b2e <- 0x1ee30016 +mem-write: 0x80005b32 <- 0xf06ffd67 +mem-write: 0x80005b36 <- 0xdb03ef5f +mem-write: 0x80005b3a <- 0x87b70124 +mem-write: 0x80005b3e <- 0x87930000 +mem-write: 0x80005b42 <- 0xfb33fff7 +mem-write: 0x80005b46 <- 0x1b130167 +mem-write: 0x80005b4a <- 0x5b13010b +mem-write: 0x80005b4e <- 0x14e3010b +mem-write: 0x80005b52 <- 0x8513defb +mem-write: 0x80005b56 <- 0xf0ef0004 +mem-write: 0x80005b5a <- 0x14e3a98f +mem-write: 0x80005b5e <- 0x5783d405 +mem-write: 0x80005b62 <- 0xc7930129 +mem-write: 0x80005b66 <- 0x9713fff7 +mem-write: 0x80005b6a <- 0x16e30117 +mem-write: 0x80005b6e <- 0xf06fdc07 +mem-write: 0x80005b72 <- 0x793d29f +mem-write: 0x80005b76 <- 0x4130144 +mem-write: 0x80005b7a <- 0x1f230024 +mem-write: 0x80005b7e <- 0x9ce3fe04 +mem-write: 0x80005b82 <- 0xf06ffe87 +mem-write: 0x80005b86 <- 0x793d6df +mem-write: 0x80005b8a <- 0x4130144 +mem-write: 0x80005b8e <- 0x1f230024 +mem-write: 0x80005b92 <- 0x1ce3fe04 +mem-write: 0x80005b96 <- 0xf06ffef4 +mem-write: 0x80005b9a <- 0x55b7d59f +mem-write: 0x80005b9e <- 0x85938001 +mem-write: 0x80005ba2 <- 0x8513c205 +mem-write: 0x80005ba6 <- 0xf0ef0004 +mem-write: 0x80005baa <- 0xa6392cf +mem-write: 0x80005bae <- 0xd7830005 +mem-write: 0x80005bb2 <- 0xf7b30124 +mem-write: 0x80005bb6 <- 0x8ee300fa +mem-write: 0x80005bba <- 0xf06ff957 +mem-write: 0x80005bbe <- 0x713fa5f +mem-write: 0x80005bc2 <- 0x7930104 +mem-write: 0x80005bc6 <- 0x87930004 +mem-write: 0x80005bca <- 0x9f230027 +mem-write: 0x80005bce <- 0x9ce3fe07 +mem-write: 0x80005bd2 <- 0xc7b7fee7 +mem-write: 0x80005bd6 <- 0x28237fff +mem-write: 0x80005bda <- 0xf06f00f4 +mem-write: 0x80005bde <- 0x5783d15f +mem-write: 0x80005be2 <- 0x1130125 +mem-write: 0x80005be6 <- 0x2423f501 +mem-write: 0x80005bea <- 0xc7930a81 +mem-write: 0x80005bee <- 0x2223fff7 +mem-write: 0x80005bf2 <- 0x20230a91 +mem-write: 0x80005bf6 <- 0x2e230b21 +mem-write: 0x80005bfa <- 0x26230931 +VXDRV: upload 1023 bytes to 0x80005bfe +mem-write: 0x80005bfe <- 0x2c230a11 +mem-write: 0x80005c02 <- 0x2a230941 +mem-write: 0x80005c06 <- 0x28230951 +mem-write: 0x80005c0a <- 0x26230961 +mem-write: 0x80005c0e <- 0x24230971 +mem-write: 0x80005c12 <- 0x22230981 +mem-write: 0x80005c16 <- 0x20230991 +mem-write: 0x80005c1a <- 0x2e2309a1 +mem-write: 0x80005c1e <- 0x971307b1 +mem-write: 0x80005c22 <- 0x9130117 +mem-write: 0x80005c26 <- 0x89930005 +mem-write: 0x80005c2a <- 0x4130005 +mem-write: 0x80005c2e <- 0x84930006 +mem-write: 0x80005c32 <- 0x16630006 +mem-write: 0x80005c36 <- 0xe0ef0007 +mem-write: 0x80005c3a <- 0x1863ef5f +mem-write: 0x80005c3e <- 0xd7833805 +mem-write: 0x80005c42 <- 0xc7930129 +mem-write: 0x80005c46 <- 0x9713fff7 +mem-write: 0x80005c4a <- 0xe630117 +mem-write: 0x80005c4e <- 0x5a370807 +mem-write: 0x80005c52 <- 0x5938001 +mem-write: 0x80005c56 <- 0x513c20a +mem-write: 0x80005c5a <- 0xf0ef0009 +mem-write: 0x80005c5e <- 0x463878f +mem-write: 0x80005c62 <- 0x5a031005 +mem-write: 0x80005c66 <- 0xd7030129 +mem-write: 0x80005c6a <- 0x87b70129 +mem-write: 0x80005c6e <- 0x87930000 +mem-write: 0x80005c72 <- 0xfa33fff7 +mem-write: 0x80005c76 <- 0xfab30147 +mem-write: 0x80005c7a <- 0x1a6300e7 +mem-write: 0x80005c7e <- 0x51308fa +mem-write: 0x80005c82 <- 0xf0ef0009 +mem-write: 0x80005c86 <- 0x86396cf +mem-write: 0x80005c8a <- 0x98631005 +mem-write: 0x80005c8e <- 0x8513014a +mem-write: 0x80005c92 <- 0xf0ef0009 +mem-write: 0x80005c96 <- 0x106395cf +mem-write: 0x80005c9a <- 0x7930e05 +mem-write: 0x80005c9e <- 0x4130144 +mem-write: 0x80005ca2 <- 0x1f230024 +mem-write: 0x80005ca6 <- 0x1ce3fe04 +mem-write: 0x80005caa <- 0x2083fef4 +mem-write: 0x80005cae <- 0x24030ac1 +mem-write: 0x80005cb2 <- 0x24830a81 +mem-write: 0x80005cb6 <- 0x29030a41 +mem-write: 0x80005cba <- 0x29830a01 +mem-write: 0x80005cbe <- 0x2a0309c1 +mem-write: 0x80005cc2 <- 0x2a830981 +mem-write: 0x80005cc6 <- 0x2b030941 +mem-write: 0x80005cca <- 0x2b830901 +mem-write: 0x80005cce <- 0x2c0308c1 +mem-write: 0x80005cd2 <- 0x2c830881 +mem-write: 0x80005cd6 <- 0x2d030841 +mem-write: 0x80005cda <- 0x2d830801 +mem-write: 0x80005cde <- 0x11307c1 +mem-write: 0x80005ce2 <- 0x80670b01 +mem-write: 0x80005ce6 <- 0x85130000 +mem-write: 0x80005cea <- 0xe0ef0009 +mem-write: 0x80005cee <- 0xe3e41f +mem-write: 0x80005cf2 <- 0x8713f605 +mem-write: 0x80005cf6 <- 0xd7830149 +mem-write: 0x80005cfa <- 0x89930009 +mem-write: 0x80005cfe <- 0x4130029 +mem-write: 0x80005d02 <- 0x1f230024 +mem-write: 0x80005d06 <- 0x98e3fef4 +mem-write: 0x80005d0a <- 0xf06ffee9 +mem-write: 0x80005d0e <- 0x8663fa1f +mem-write: 0x80005d12 <- 0x51308fa +mem-write: 0x80005d16 <- 0x5930009 +mem-write: 0x80005d1a <- 0xe0ef01c1 +mem-write: 0x80005d1e <- 0x593ec1f +mem-write: 0x80005d22 <- 0x85130381 +mem-write: 0x80005d26 <- 0xe0ef0009 +mem-write: 0x80005d2a <- 0x5b83eb5f +mem-write: 0x80005d2e <- 0x590303a1 +mem-write: 0x80005d32 <- 0x926301e1 +mem-write: 0x80005d36 <- 0x7930c0b +mem-write: 0x80005d3a <- 0xd9303c1 +mem-write: 0x80005d3e <- 0x8e630501 +mem-write: 0x80005d42 <- 0xd70334fd +mem-write: 0x80005d46 <- 0x87930007 +mem-write: 0x80005d4a <- 0xae30027 +mem-write: 0x80005d4e <- 0x513fe07 +mem-write: 0x80005d52 <- 0xf0ef0381 +mem-write: 0x80005d56 <- 0x7b3ad4f +mem-write: 0x80005d5a <- 0x560340a0 +mem-write: 0x80005d5e <- 0x262301e1 +mem-write: 0x80005d62 <- 0x6f00f1 +mem-write: 0x80005d66 <- 0x59309c0 +mem-write: 0x80005d6a <- 0x8513c20a +mem-write: 0x80005d6e <- 0xe0ef0009 +mem-write: 0x80005d72 <- 0x18e3f65f +mem-write: 0x80005d76 <- 0x713ee05 +mem-write: 0x80005d7a <- 0x7930104 +mem-write: 0x80005d7e <- 0x87930004 +mem-write: 0x80005d82 <- 0x9f230027 +mem-write: 0x80005d86 <- 0x9ce3fe07 +mem-write: 0x80005d8a <- 0xc7b7fee7 +mem-write: 0x80005d8e <- 0x28237fff +mem-write: 0x80005d92 <- 0xf06f00f4 +mem-write: 0x80005d96 <- 0x9ee3f19f +mem-write: 0x80005d9a <- 0x8513f74a +mem-write: 0x80005d9e <- 0xf0ef0009 +mem-write: 0x80005da2 <- 0x8e3850f +mem-write: 0x80005da6 <- 0x513f605 +mem-write: 0x80005daa <- 0xe0ef0009 +mem-write: 0x80005dae <- 0x493df1f +mem-write: 0x80005db2 <- 0x85130005 +mem-write: 0x80005db6 <- 0xe0ef0009 +mem-write: 0x80005dba <- 0x87b3de5f +mem-write: 0x80005dbe <- 0x37b340a4 +mem-write: 0x80005dc2 <- 0x979300f0 +mem-write: 0x80005dc6 <- 0x192300f7 +mem-write: 0x80005dca <- 0x71300f4 +mem-write: 0x80005dce <- 0x7930124 +mem-write: 0x80005dd2 <- 0x87930004 +mem-write: 0x80005dd6 <- 0x9f230027 +mem-write: 0x80005dda <- 0x9ce3fe07 +mem-write: 0x80005dde <- 0x5783fee7 +mem-write: 0x80005de2 <- 0x87370124 +mem-write: 0x80005de6 <- 0x7130000 +mem-write: 0x80005dea <- 0xe7b3fff7 +mem-write: 0x80005dee <- 0x192300e7 +mem-write: 0x80005df2 <- 0xf06f00f4 +mem-write: 0x80005df6 <- 0x2623eb9f +mem-write: 0x80005dfa <- 0x6130171 +mem-write: 0x80005dfe <- 0x24230009 +mem-write: 0x80005e02 <- 0x7930121 +mem-write: 0x80005e06 <- 0x6930201 +mem-write: 0x80005e0a <- 0x12630341 +mem-write: 0x80005e0e <- 0x80630206 +mem-write: 0x80005e12 <- 0xd7032af6 +mem-write: 0x80005e16 <- 0x87930007 +mem-write: 0x80005e1a <- 0xae30027 +mem-write: 0x80005e1e <- 0x513fe07 +mem-write: 0x80005e22 <- 0xf0ef01c1 +mem-write: 0x80005e26 <- 0x7b3a04f +mem-write: 0x80005e2a <- 0x242340a9 +mem-write: 0x80005e2e <- 0x270300f1 +mem-write: 0x80005e32 <- 0x8d130381 +mem-write: 0x80005e36 <- 0x7930384 +mem-write: 0x80005e3a <- 0xaa23000d +mem-write: 0x80005e3e <- 0x891302e4 +mem-write: 0x80005e42 <- 0x879304e4 +mem-write: 0x80005e46 <- 0x9f230027 +mem-write: 0x80005e4a <- 0x1ce3fe07 +mem-write: 0x80005e4e <- 0x513fef9 +mem-write: 0x80005e52 <- 0xe0ef0381 +mem-write: 0x80005e56 <- 0x5c03b69f +mem-write: 0x80005e5a <- 0xa370221 +mem-write: 0x80005e5e <- 0xd930001 +mem-write: 0x80005e62 <- 0x1a930501 +mem-write: 0x80005e66 <- 0x8ab3010c +mem-write: 0x80005e6a <- 0xb13418a +mem-write: 0x80005e6e <- 0xa1303a1 +mem-write: 0x80005e72 <- 0xc93fffa +mem-write: 0x80005e76 <- 0x99306e1 +mem-write: 0x80005e7a <- 0x57830561 +mem-write: 0x80005e7e <- 0x570303c1 +mem-write: 0x80005e82 <- 0xb9303e1 +mem-write: 0x80005e86 <- 0x9793000a +mem-write: 0x80005e8a <- 0x87b30107 +mem-write: 0x80005e8e <- 0xe86300e7 +mem-write: 0x80005e92 <- 0xd7b300fa +mem-write: 0x80005e96 <- 0x9b930387 +mem-write: 0x80005e9a <- 0xdb930107 +mem-write: 0x80005e9e <- 0x613010b +mem-write: 0x80005ea2 <- 0x5930541 +mem-write: 0x80005ea6 <- 0x851301c1 +mem-write: 0x80005eaa <- 0xe0ef000b +mem-write: 0x80005eae <- 0x713be9f +mem-write: 0x80005eb2 <- 0x79303c1 +mem-write: 0x80005eb6 <- 0xd5830581 +mem-write: 0x80005eba <- 0x56030007 +mem-write: 0x80005ebe <- 0x87930007 +mem-write: 0x80005ec2 <- 0x7130027 +mem-write: 0x80005ec6 <- 0x90630027 +mem-write: 0x80005eca <- 0x96e312c5 +mem-write: 0x80005ece <- 0x793ff97 +mem-write: 0x80005ed2 <- 0x5930000 +mem-write: 0x80005ed6 <- 0x861306c1 +mem-write: 0x80005eda <- 0x5703000d +mem-write: 0x80005ede <- 0xd8030006 +mem-write: 0x80005ee2 <- 0x6130005 +mem-write: 0x80005ee6 <- 0x733ffe6 +mem-write: 0x80005eea <- 0x73340f7 +mem-write: 0x80005eee <- 0x57934107 +mem-write: 0x80005ef2 <- 0x11230107 +mem-write: 0x80005ef6 <- 0xf79300e6 +mem-write: 0x80005efa <- 0x85930017 +mem-write: 0x80005efe <- 0x1ee3ffe5 +mem-write: 0x80005f02 <- 0x1023fd66 +mem-write: 0x80005f06 <- 0x793017d +mem-write: 0x80005f0a <- 0xd70303c1 +mem-write: 0x80005f0e <- 0x87930027 +mem-write: 0x80005f12 <- 0x9f230027 +mem-write: 0x80005f16 <- 0x9ae3fee7 +mem-write: 0x80005f1a <- 0x1823ffb7 +mem-write: 0x80005f1e <- 0xd130401 +mem-write: 0x80005f22 <- 0x1ce3002d +mem-write: 0x80005f26 <- 0x593f5a9 +mem-write: 0x80005f2a <- 0x7930000 +mem-write: 0x80005f2e <- 0x69303c1 +mem-write: 0x80005f32 <- 0xd7030521 +mem-write: 0x80005f36 <- 0x87930007 +mem-write: 0x80005f3a <- 0xe5b30027 +mem-write: 0x80005f3e <- 0x9ae300e5 +mem-write: 0x80005f42 <- 0x9793fed7 +mem-write: 0x80005f46 <- 0xd7930105 +mem-write: 0x80005f4a <- 0x84634107 +mem-write: 0x80005f4e <- 0x5930007 +mem-write: 0x80005f52 <- 0x95930010 +mem-write: 0x80005f56 <- 0xd5930105 +mem-write: 0x80005f5a <- 0x87130105 +mem-write: 0x80005f5e <- 0x7930344 +mem-write: 0x80005f62 <- 0x56030381 +mem-write: 0x80005f66 <- 0x87930007 +mem-write: 0x80005f6a <- 0x7130027 +mem-write: 0x80005f6e <- 0x9f230027 +mem-write: 0x80005f72 <- 0x98e3fec7 +mem-write: 0x80005f76 <- 0x2783fef6 +mem-write: 0x80005f7a <- 0x270300c1 +mem-write: 0x80005f7e <- 0x46b70081 +mem-write: 0x80005f82 <- 0x86930000 +mem-write: 0x80005f86 <- 0x8bb3fff6 +mem-write: 0x80005f8a <- 0x51340e7 +mem-write: 0x80005f8e <- 0x87930381 +mem-write: 0x80005f92 <- 0x7130004 +mem-write: 0x80005f96 <- 0x86b30400 +mem-write: 0x80005f9a <- 0x61300db +mem-write: 0x80005f9e <- 0xf0ef0000 +mem-write: 0x80005fa2 <- 0x5703a04f +mem-write: 0x80005fa6 <- 0x57830381 +mem-write: 0x80005faa <- 0x59301c1 +mem-write: 0x80005fae <- 0x5130004 +mem-write: 0x80005fb2 <- 0x87b30381 +mem-write: 0x80005fb6 <- 0x37b340e7 +mem-write: 0x80005fba <- 0x7b300f0 +mem-write: 0x80005fbe <- 0x1c2340f0 +mem-write: 0x80005fc2 <- 0xf0ef02f1 +mem-write: 0x80005fc6 <- 0xf06ff54f +mem-write: 0x80005fca <- 0x713ce5f +mem-write: 0x80005fce <- 0x57830149 +mem-write: 0x80005fd2 <- 0x9130009 +mem-write: 0x80005fd6 <- 0x4130029 +mem-write: 0x80005fda <- 0x1f230024 +mem-write: 0x80005fde <- 0x18e3fef4 +mem-write: 0x80005fe2 <- 0xf06ffee9 +mem-write: 0x80005fe6 <- 0x74e3cc9f +mem-write: 0x80005fea <- 0x8793eeb6 +mem-write: 0x80005fee <- 0x9893fffb +mem-write: 0x80005ff2 <- 0xd8930107 +mem-write: 0x80005ff6 <- 0x7930108 +mem-write: 0x80005ffa <- 0x26930000 +VXDRV: upload 1024 bytes to 0x80005ffd +mem-write: 0x80005ffd <- 0x13034105 +mem-write: 0x80006001 <- 0x306c106 +mem-write: 0x80006005 <- 0x3000657 +mem-write: 0x80006009 <- 0x130005d8 +mem-write: 0x8000600d <- 0x33ffe606 +mem-write: 0x80006011 <- 0x3340f707 +mem-write: 0x80006015 <- 0x93410707 +mem-write: 0x80006019 <- 0x23010757 +mem-write: 0x8000601d <- 0x9300e611 +mem-write: 0x80006021 <- 0x930017f7 +mem-write: 0x80006025 <- 0xe3ffe585 +mem-write: 0x80006029 <- 0x13fd361e +mem-write: 0x8000602d <- 0x9303c107 +mem-write: 0x80006031 <- 0x83058107 +mem-write: 0x80006035 <- 0x30007d5 +mem-write: 0x80006039 <- 0x93000756 +mem-write: 0x8000603d <- 0x13002787 +mem-write: 0x80006041 <- 0x63002707 +mem-write: 0x80006045 <- 0xe300c598 +mem-write: 0x80006049 <- 0x93ff9796 +mem-write: 0x8000604d <- 0x6f00088b +mem-write: 0x80006051 <- 0xe3e81ff0 +mem-write: 0x80006055 <- 0x93feb67c +mem-write: 0x80006059 <- 0x93ffeb87 +mem-write: 0x8000605d <- 0x9301079b +mem-write: 0x80006061 <- 0x13010bdb +mem-write: 0x80006065 <- 0x93000006 +mem-write: 0x80006069 <- 0x13034105 +mem-write: 0x8000606d <- 0x8306c107 +mem-write: 0x80006071 <- 0x3000757 +mem-write: 0x80006075 <- 0x130005d8 +mem-write: 0x80006079 <- 0xb3ffe707 +mem-write: 0x8000607d <- 0xb340c787 +mem-write: 0x80006081 <- 0x13410787 +mem-write: 0x80006085 <- 0x230107d6 +mem-write: 0x80006089 <- 0x1300f711 +mem-write: 0x8000608d <- 0x93001676 +mem-write: 0x80006091 <- 0xe3ffe585 +mem-write: 0x80006095 <- 0x6ffd371e +mem-write: 0x80006099 <- 0x93e39ff0 +mem-write: 0x8000609d <- 0x13014407 +mem-write: 0x800060a1 <- 0x23002404 +mem-write: 0x800060a5 <- 0xe3fe041f +mem-write: 0x800060a9 <- 0x6ffe879c +mem-write: 0x800060ad <- 0x3c01ff0 +mem-write: 0x800060b1 <- 0x8301c157 +mem-write: 0x800060b5 <- 0x63038157 +mem-write: 0x800060b9 <- 0x3700f704 +mem-write: 0x800060bd <- 0x23000086 +mem-write: 0x800060c1 <- 0x1300c419 +mem-write: 0x800060c5 <- 0x93012407 +mem-write: 0x800060c9 <- 0x93000407 +mem-write: 0x800060cd <- 0x23002787 +mem-write: 0x800060d1 <- 0xe3fe079f +mem-write: 0x800060d5 <- 0x83fef71c +mem-write: 0x800060d9 <- 0x37012457 +mem-write: 0x800060dd <- 0x13000087 +mem-write: 0x800060e1 <- 0xb3fff707 +mem-write: 0x800060e5 <- 0x2300e7e7 +mem-write: 0x800060e9 <- 0x6f00f419 +mem-write: 0x800060ed <- 0x13bc1ff0 +mem-write: 0x800060f1 <- 0x23fd0101 +mem-write: 0x800060f5 <- 0x23028124 +mem-write: 0x800060f9 <- 0x13021126 +mem-write: 0x800060fd <- 0x93000584 +mem-write: 0x80006101 <- 0x13004107 +mem-write: 0x80006105 <- 0x9301e107 +mem-write: 0x80006109 <- 0x23002787 +mem-write: 0x8000610d <- 0xe3fe079f +mem-write: 0x80006111 <- 0x3fee79c +mem-write: 0x80006115 <- 0x9300e556 +mem-write: 0x80006119 <- 0x93010617 +mem-write: 0x8000611d <- 0x634107d7 +mem-write: 0x80006121 <- 0xb70607ca +mem-write: 0x80006125 <- 0x93000087 +mem-write: 0x80006129 <- 0x23fff787 +mem-write: 0x8000612d <- 0x33000112 +mem-write: 0x80006131 <- 0x6300f676 +mem-write: 0x80006135 <- 0x9306f60c +mem-write: 0x80006139 <- 0x2300e507 +mem-write: 0x8000613d <- 0x1300c113 +mem-write: 0x80006141 <- 0x8300a107 +mem-write: 0x80006145 <- 0x93ffe7d6 +mem-write: 0x80006149 <- 0x13ffe787 +mem-write: 0x8000614d <- 0x23002707 +mem-write: 0x80006151 <- 0xe3fed71f +mem-write: 0x80006155 <- 0x63fef518 +mem-write: 0x80006159 <- 0x23020612 +mem-write: 0x8000615d <- 0x93000114 +mem-write: 0x80006161 <- 0x13000405 +mem-write: 0x80006165 <- 0xef004105 +mem-write: 0x80006169 <- 0x83db0ff0 +mem-write: 0x8000616d <- 0x302c120 +mem-write: 0x80006171 <- 0x13028124 +mem-write: 0x80006175 <- 0x67030101 +mem-write: 0x80006179 <- 0x93000080 +mem-write: 0x8000617d <- 0x93001007 +mem-write: 0x80006181 <- 0x13fff005 +mem-write: 0x80006185 <- 0x23004105 +mem-write: 0x80006189 <- 0xef00f114 +mem-write: 0x8000618d <- 0x6fc81fe0 +mem-write: 0x80006191 <- 0x93fd1ff0 +mem-write: 0x80006195 <- 0x23fff007 +mem-write: 0x80006199 <- 0xb700f112 +mem-write: 0x8000619d <- 0x93000087 +mem-write: 0x800061a1 <- 0x33fff787 +mem-write: 0x800061a5 <- 0xe300f676 +mem-write: 0x800061a9 <- 0x93f8f618 +mem-write: 0x800061ad <- 0x93000507 +mem-write: 0x800061b1 <- 0x300e506 +mem-write: 0x800061b5 <- 0x930007d7 +mem-write: 0x800061b9 <- 0x63002787 +mem-write: 0x800061bd <- 0xe304071c +mem-write: 0x800061c1 <- 0x13fed79a +mem-write: 0x800061c5 <- 0x93014407 +mem-write: 0x800061c9 <- 0x93000407 +mem-write: 0x800061cd <- 0x23002787 +mem-write: 0x800061d1 <- 0xe3fe079f +mem-write: 0x800061d5 <- 0x13fef71c +mem-write: 0x800061d9 <- 0x93012407 +mem-write: 0x800061dd <- 0x93000407 +mem-write: 0x800061e1 <- 0x23002787 +mem-write: 0x800061e5 <- 0xe3fe079f +mem-write: 0x800061e9 <- 0x83fef71c +mem-write: 0x800061ed <- 0x37012457 +mem-write: 0x800061f1 <- 0x13000087 +mem-write: 0x800061f5 <- 0xb3fff707 +mem-write: 0x800061f9 <- 0x2300e7e7 +mem-write: 0x800061fd <- 0x8300f419 +mem-write: 0x80006201 <- 0xe300e517 +mem-write: 0x80006205 <- 0x13f607d4 +mem-write: 0x80006209 <- 0xef000405 +mem-write: 0x8000620d <- 0x6f945fe0 +mem-write: 0x80006211 <- 0x13f5dff0 +mem-write: 0x80006215 <- 0x93010407 +mem-write: 0x80006219 <- 0x93000407 +mem-write: 0x8000621d <- 0x23002787 +mem-write: 0x80006221 <- 0xe3fe079f +mem-write: 0x80006225 <- 0xb7fef71c +mem-write: 0x80006229 <- 0x237fffc7 +mem-write: 0x8000622d <- 0x6f00f428 +mem-write: 0x80006231 <- 0x83f3dff0 +mem-write: 0x80006235 <- 0x1300c5a8 +mem-write: 0x80006239 <- 0x83e10101 +mem-write: 0x8000623d <- 0x30005ae +mem-write: 0x80006241 <- 0x30045ae +mem-write: 0x80006245 <- 0x230085a3 +mem-write: 0x80006249 <- 0x8303112e +mem-write: 0x8000624d <- 0x93040525 +mem-write: 0x80006251 <- 0x23fff008 +mem-write: 0x80006255 <- 0x93171120 +mem-write: 0x80006259 <- 0x23090008 +mem-write: 0x8000625d <- 0x231e8124 +mem-write: 0x80006261 <- 0x231d412c +mem-write: 0x80006265 <- 0x231e1126 +mem-write: 0x80006269 <- 0x231e9122 +mem-write: 0x8000626d <- 0x231f2120 +mem-write: 0x80006271 <- 0x231d312e +mem-write: 0x80006275 <- 0x231d512a +mem-write: 0x80006279 <- 0x231d6128 +mem-write: 0x8000627d <- 0x231d7126 +mem-write: 0x80006281 <- 0x231d8124 +mem-write: 0x80006285 <- 0x231d9122 +mem-write: 0x80006289 <- 0x231da120 +mem-write: 0x8000628d <- 0x231bb12e +mem-write: 0x80006291 <- 0x2303d128 +mem-write: 0x80006295 <- 0x2303c12a +mem-write: 0x80006299 <- 0x2302612c +mem-write: 0x8000629d <- 0x23171122 +mem-write: 0x800062a1 <- 0x2300c120 +mem-write: 0x800062a5 <- 0x2300d124 +mem-write: 0x800062a9 <- 0x2300e126 +mem-write: 0x800062ad <- 0x1301012c +mem-write: 0x800062b1 <- 0x1300050a +mem-write: 0x800062b5 <- 0x63000784 +mem-write: 0x800062b9 <- 0x3020580 +mem-write: 0x800062bd <- 0x93044527 +mem-write: 0x800062c1 <- 0xb3001007 +mem-write: 0x800062c5 <- 0x2300e797 +mem-write: 0x800062c9 <- 0x2300e5a2 +mem-write: 0x800062cd <- 0xef00f5a4 +mem-write: 0x800062d1 <- 0x23585010 +mem-write: 0x800062d5 <- 0x93040a20 +mem-write: 0x800062d9 <- 0x93060109 +mem-write: 0x800062dd <- 0x13000985 +mem-write: 0x800062e1 <- 0xef030105 +mem-write: 0x800062e5 <- 0x13e0dff0 +mem-write: 0x800062e9 <- 0xef000985 +mem-write: 0x800062ed <- 0x38b1fe0 +mem-write: 0x800062f1 <- 0x33000127 +mem-write: 0x800062f5 <- 0x2300a035 +mem-write: 0x800062f9 <- 0x9300a420 +mem-write: 0x800062fd <- 0xe3003007 +mem-write: 0x80006301 <- 0x9314f702 +mem-write: 0x80006305 <- 0x23014007 +mem-write: 0x80006309 <- 0xe300f122 +mem-write: 0x8000630d <- 0x835e0718 +mem-write: 0x80006311 <- 0x3072157 +mem-write: 0x80006315 <- 0x93164127 +mem-write: 0x80006319 <- 0x23fff7c7 +mem-write: 0x8000631d <- 0x1300e12a +mem-write: 0x80006321 <- 0x63011797 +mem-write: 0x80006325 <- 0x13000718 +mem-write: 0x80006329 <- 0xef000985 +mem-write: 0x8000632d <- 0xe3801fe0 +mem-write: 0x80006331 <- 0x93400514 +mem-write: 0x80006335 <- 0x23090007 +mem-write: 0x80006339 <- 0x1316f122 +mem-write: 0x8000633d <- 0x9307c107 +mem-write: 0x80006341 <- 0x13000987 +mem-write: 0x80006345 <- 0x83074106 +mem-write: 0x80006349 <- 0x930007d6 +mem-write: 0x8000634d <- 0x13002787 +mem-write: 0x80006351 <- 0x23002707 +mem-write: 0x80006355 <- 0xe3fed71f +mem-write: 0x80006359 <- 0x3fec798 +mem-write: 0x8000635d <- 0x2308e156 +mem-write: 0x80006361 <- 0x93000128 +mem-write: 0x80006365 <- 0x93010617 +mem-write: 0x80006369 <- 0x634107d7 +mem-write: 0x8000636d <- 0x130007de +mem-write: 0x80006371 <- 0xb7011616 +mem-write: 0x80006375 <- 0x13000107 +mem-write: 0x80006379 <- 0x93011656 +mem-write: 0x8000637d <- 0x23fff787 +mem-write: 0x80006381 <- 0x2308c117 +mem-write: 0x80006385 <- 0x3700f128 +mem-write: 0x80006389 <- 0x9380015b +mem-write: 0x8000638d <- 0x13c20b0d +mem-write: 0x80006391 <- 0x93014d8c +mem-write: 0x80006395 <- 0x93000006 +mem-write: 0x80006399 <- 0x13098107 +mem-write: 0x8000639d <- 0x13000c07 +mem-write: 0x800063a1 <- 0x6f0ac10d +mem-write: 0x800063a5 <- 0x83008000 +mem-write: 0x800063a9 <- 0x93000756 +mem-write: 0x800063ad <- 0x23002787 +mem-write: 0x800063b1 <- 0x13fed79f +mem-write: 0x800063b5 <- 0xe3002707 +mem-write: 0x800063b9 <- 0x63ffa798 +mem-write: 0x800063bd <- 0xb7140608 +mem-write: 0x800063c1 <- 0x93000087 +mem-write: 0x800063c5 <- 0xe3fff787 +mem-write: 0x800063c9 <- 0x8356f606 +mem-write: 0x800063cd <- 0xe308c117 +mem-write: 0x800063d1 <- 0x935a07d8 +mem-write: 0x800063d5 <- 0x1307c105 +mem-write: 0x800063d9 <- 0xef000c05 +mem-write: 0x800063dd <- 0x638f9fe0 +mem-write: 0x800063e1 <- 0xe3140502 +mem-write: 0x800063e5 <- 0x830c054c +mem-write: 0x800063e9 <- 0xe308e157 +mem-write: 0x800063ed <- 0x8362079c +mem-write: 0x800063f1 <- 0x9308c117 +mem-write: 0x800063f5 <- 0x13000004 +mem-write: 0x800063f9 <- 0x63160109 +VXDRV: upload 1024 bytes to 0x800063fd +mem-write: 0x800063fd <- 0x130207c4 +mem-write: 0x80006401 <- 0x13118d84 +mem-write: 0x80006405 <- 0x9307c106 +mem-write: 0x80006409 <- 0x93000906 +mem-write: 0x8000640d <- 0x13000605 +mem-write: 0x80006411 <- 0xef000405 +mem-write: 0x80006415 <- 0x83bb4ff0 +mem-write: 0x80006419 <- 0x9308c117 +mem-write: 0x8000641d <- 0xe3fff484 +mem-write: 0x80006421 <- 0x13fe07d2 +mem-write: 0x80006425 <- 0x930d0104 +mem-write: 0x80006429 <- 0x130e810b +mem-write: 0x8000642d <- 0x93000407 +mem-write: 0x80006431 <- 0x1307c107 +mem-write: 0x80006435 <- 0x83090106 +mem-write: 0x80006439 <- 0x930007d6 +mem-write: 0x8000643d <- 0x13002787 +mem-write: 0x80006441 <- 0x23002707 +mem-write: 0x80006445 <- 0xe3fed71f +mem-write: 0x80006449 <- 0x93fec798 +mem-write: 0x8000644d <- 0x93000006 +mem-write: 0x80006451 <- 0x13098107 +mem-write: 0x80006455 <- 0x6f000c07 +mem-write: 0x80006459 <- 0x83008000 +mem-write: 0x8000645d <- 0x93000756 +mem-write: 0x80006461 <- 0x23002787 +mem-write: 0x80006465 <- 0x13fed79f +mem-write: 0x80006469 <- 0xe3002707 +mem-write: 0x8000646d <- 0x93ffa798 +mem-write: 0x80006471 <- 0x13028d8c +mem-write: 0x80006475 <- 0xb712cd8d +mem-write: 0x80006479 <- 0x93fffffa +mem-write: 0x8000647d <- 0x6f118d8d +mem-write: 0x80006481 <- 0x1300c000 +mem-write: 0x80006485 <- 0x93014d0d +mem-write: 0x80006489 <- 0x93014c8c +mem-write: 0x8000648d <- 0x13000405 +mem-write: 0x80006491 <- 0xef000c05 +mem-write: 0x80006495 <- 0x93841fe0 +mem-write: 0x80006499 <- 0x93000507 +mem-write: 0x8000649d <- 0x13000405 +mem-write: 0x800064a1 <- 0x63000d05 +mem-write: 0x800064a5 <- 0xef04f056 +mem-write: 0x800064a9 <- 0x9382dfe0 +mem-write: 0x800064ad <- 0x93000507 +mem-write: 0x800064b1 <- 0x13000906 +mem-write: 0x800064b5 <- 0x93000406 +mem-write: 0x800064b9 <- 0x13000405 +mem-write: 0x800064bd <- 0x63000c85 +mem-write: 0x800064c1 <- 0xef0207c0 +mem-write: 0x800064c5 <- 0x13b04ff0 +mem-write: 0x800064c9 <- 0x93098106 +mem-write: 0x800064cd <- 0x93000906 +mem-write: 0x800064d1 <- 0x13000605 +mem-write: 0x800064d5 <- 0xef000c85 +mem-write: 0x800064d9 <- 0xb3af0ff0 +mem-write: 0x800064dd <- 0x93015484 +mem-write: 0x800064e1 <- 0xb301fad7 +mem-write: 0x800064e5 <- 0x93015787 +mem-write: 0x800064e9 <- 0xe34017da +mem-write: 0x800064ed <- 0x13f9bc9c +mem-write: 0x800064f1 <- 0x93098106 +mem-write: 0x800064f5 <- 0x93000906 +mem-write: 0x800064f9 <- 0x13000c05 +mem-write: 0x800064fd <- 0xef000605 +mem-write: 0x80006501 <- 0x93ee0ff0 +mem-write: 0x80006505 <- 0x6f12410a +mem-write: 0x80006509 <- 0x93030000 +mem-write: 0x8000650d <- 0x9307c107 +mem-write: 0x80006511 <- 0x308e106 +mem-write: 0x80006515 <- 0x930007d7 +mem-write: 0x80006519 <- 0xe3002787 +mem-write: 0x8000651d <- 0xe3ea071c +mem-write: 0x80006521 <- 0x93fed79a +mem-write: 0x80006525 <- 0x93000004 +mem-write: 0x80006529 <- 0x1312410a +mem-write: 0x8000652d <- 0x13160109 +mem-write: 0x80006531 <- 0x930d0104 +mem-write: 0x80006535 <- 0x930e810b +mem-write: 0x80006539 <- 0x13000405 +mem-write: 0x8000653d <- 0xef098105 +mem-write: 0x80006541 <- 0x13e9cfe0 +mem-write: 0x80006545 <- 0x93098107 +mem-write: 0x80006549 <- 0x83000407 +mem-write: 0x8000654d <- 0x930007d6 +mem-write: 0x80006551 <- 0x13002787 +mem-write: 0x80006555 <- 0x23002707 +mem-write: 0x80006559 <- 0xe3fed71f +mem-write: 0x8000655d <- 0x93ff7798 +mem-write: 0x80006561 <- 0x13000405 +mem-write: 0x80006565 <- 0x2307c105 +mem-write: 0x80006569 <- 0xef0a0118 +mem-write: 0x8000656d <- 0x93e70fe0 +mem-write: 0x80006571 <- 0x307c107 +mem-write: 0x80006575 <- 0x13000457 +mem-write: 0x80006579 <- 0x93002404 +mem-write: 0x8000657d <- 0x23002787 +mem-write: 0x80006581 <- 0xe3fee79f +mem-write: 0x80006585 <- 0x13ff7418 +mem-write: 0x80006589 <- 0x13098105 +mem-write: 0x8000658d <- 0x93000906 +mem-write: 0x80006591 <- 0x2307c105 +mem-write: 0x80006595 <- 0xef08011a +mem-write: 0x80006599 <- 0x3818ff0 +mem-write: 0x8000659d <- 0x631ac155 +mem-write: 0x800065a1 <- 0x931c0514 +mem-write: 0x800065a5 <- 0x1309410c +mem-write: 0x800065a9 <- 0x1307e104 +mem-write: 0x800065ad <- 0x930b610c +mem-write: 0x800065b1 <- 0x13c20b05 +mem-write: 0x800065b5 <- 0xef07c105 +mem-write: 0x800065b9 <- 0x63f1cfe0 +mem-write: 0x800065bd <- 0x131a0506 +mem-write: 0x800065c1 <- 0x93000007 +mem-write: 0x800065c5 <- 0x6f000c86 +mem-write: 0x800065c9 <- 0x1301c000 +mem-write: 0x800065cd <- 0x23001717 +mem-write: 0x800065d1 <- 0x1300f690 +mem-write: 0x800065d5 <- 0x93010717 +mem-write: 0x800065d9 <- 0x13ffe686 +mem-write: 0x800065dd <- 0x63010757 +mem-write: 0x800065e1 <- 0x83048684 +mem-write: 0x800065e5 <- 0x130006d7 +mem-write: 0x800065e9 <- 0x13010796 +mem-write: 0x800065ed <- 0x93410656 +mem-write: 0x800065f1 <- 0x63001797 +mem-write: 0x800065f5 <- 0x13000654 +mem-write: 0x800065f9 <- 0x93001767 +mem-write: 0x800065fd <- 0x93010797 +mem-write: 0x80006601 <- 0x130107d7 +mem-write: 0x80006605 <- 0x93002776 +mem-write: 0x80006609 <- 0xe30017e5 +mem-write: 0x8000660d <- 0x13fc0600 +mem-write: 0x80006611 <- 0x23001717 +mem-write: 0x80006615 <- 0x1300b690 +mem-write: 0x80006619 <- 0x93010717 +mem-write: 0x8000661d <- 0x13ffe686 +mem-write: 0x80006621 <- 0xe3010757 +mem-write: 0x80006625 <- 0x13fc8690 +mem-write: 0x80006629 <- 0x930b4107 +mem-write: 0x8000662d <- 0x8307c107 +mem-write: 0x80006631 <- 0x930007d6 +mem-write: 0x80006635 <- 0x13002787 +mem-write: 0x80006639 <- 0x23002707 +mem-write: 0x8000663d <- 0xe3fed71f +mem-write: 0x80006641 <- 0x23ff9798 +mem-write: 0x80006645 <- 0x130c0116 +mem-write: 0x80006649 <- 0x93000007 +mem-write: 0x8000664d <- 0x6f0cc106 +mem-write: 0x80006651 <- 0x1301c000 +mem-write: 0x80006655 <- 0x23001717 +mem-write: 0x80006659 <- 0x1300f690 +mem-write: 0x8000665d <- 0x93010717 +mem-write: 0x80006661 <- 0x13ffe686 +mem-write: 0x80006665 <- 0x63010757 +mem-write: 0x80006669 <- 0x83058684 +mem-write: 0x8000666d <- 0x130006d7 +mem-write: 0x80006671 <- 0x13010796 +mem-write: 0x80006675 <- 0x93410656 +mem-write: 0x80006679 <- 0x63001797 +mem-write: 0x8000667d <- 0x13000654 +mem-write: 0x80006681 <- 0x93001767 +mem-write: 0x80006685 <- 0x93010797 +mem-write: 0x80006689 <- 0x130107d7 +mem-write: 0x8000668d <- 0x93002776 +mem-write: 0x80006691 <- 0xe30017e5 +mem-write: 0x80006695 <- 0x13fc0600 +mem-write: 0x80006699 <- 0x23001717 +mem-write: 0x8000669d <- 0x1300b690 +mem-write: 0x800066a1 <- 0x93010717 +mem-write: 0x800066a5 <- 0x13ffe686 +mem-write: 0x800066a9 <- 0xe3010757 +mem-write: 0x800066ad <- 0x13fd8690 +mem-write: 0x800066b1 <- 0x93000007 +mem-write: 0x800066b5 <- 0x6f0cc106 +mem-write: 0x800066b9 <- 0x1301c000 +mem-write: 0x800066bd <- 0x23001717 +mem-write: 0x800066c1 <- 0x1300f690 +mem-write: 0x800066c5 <- 0x93010717 +mem-write: 0x800066c9 <- 0x13ffe686 +mem-write: 0x800066cd <- 0x63010757 +mem-write: 0x800066d1 <- 0x83058684 +mem-write: 0x800066d5 <- 0x130006d7 +mem-write: 0x800066d9 <- 0x13010796 +mem-write: 0x800066dd <- 0x93410656 +mem-write: 0x800066e1 <- 0x63001797 +mem-write: 0x800066e5 <- 0x13000654 +mem-write: 0x800066e9 <- 0x93001767 +mem-write: 0x800066ed <- 0x93010797 +mem-write: 0x800066f1 <- 0x130107d7 +mem-write: 0x800066f5 <- 0x93002776 +mem-write: 0x800066f9 <- 0xe30017e5 +mem-write: 0x800066fd <- 0x13fc0600 +mem-write: 0x80006701 <- 0x23001717 +mem-write: 0x80006705 <- 0x1300b690 +mem-write: 0x80006709 <- 0x93010717 +mem-write: 0x8000670d <- 0x13ffe686 +mem-write: 0x80006711 <- 0xe3010757 +mem-write: 0x80006715 <- 0x13fd8690 +mem-write: 0x80006719 <- 0x93000006 +mem-write: 0x8000671d <- 0x13000c86 +mem-write: 0x80006721 <- 0x830cc107 +mem-write: 0x80006725 <- 0x830006d5 +mem-write: 0x80006729 <- 0x93000757 +mem-write: 0x8000672d <- 0x13ffe686 +mem-write: 0x80006731 <- 0xb3ffe707 +mem-write: 0x80006735 <- 0xb300b787 +mem-write: 0x80006739 <- 0x1300c787 +mem-write: 0x8000673d <- 0x230107d6 +mem-write: 0x80006741 <- 0x1300f691 +mem-write: 0x80006745 <- 0xe3001676 +mem-write: 0x80006749 <- 0x13fd871e +mem-write: 0x8000674d <- 0x13098105 +mem-write: 0x80006751 <- 0x93000906 +mem-write: 0x80006755 <- 0xef07c105 +mem-write: 0x80006759 <- 0x3e59fe0 +mem-write: 0x8000675d <- 0x931ac155 +mem-write: 0x80006761 <- 0xe3fff484 +mem-write: 0x80006765 <- 0x83e40506 +mem-write: 0x80006769 <- 0x83010127 +mem-write: 0x8000676d <- 0x13000126 +mem-write: 0x80006771 <- 0xb3003007 +mem-write: 0x80006775 <- 0xb300f037 +mem-write: 0x80006779 <- 0x9340f007 +mem-write: 0x8000677d <- 0x9300d7f7 +mem-write: 0x80006781 <- 0x23020787 +mem-write: 0x80006785 <- 0x8312f102 +mem-write: 0x80006789 <- 0x63004127 +mem-write: 0x8000678d <- 0xb300e694 +mem-write: 0x80006791 <- 0x13009787 +mem-write: 0x80006795 <- 0x1302a007 +mem-write: 0x80006799 <- 0x63000784 +mem-write: 0x8000679d <- 0x1300f754 +mem-write: 0x800067a1 <- 0x1302a004 +mem-write: 0x800067a5 <- 0x6300a007 +mem-write: 0x800067a9 <- 0x134ee502 +mem-write: 0x800067ad <- 0x13030505 +mem-write: 0x800067b1 <- 0xa302e007 +mem-write: 0x800067b5 <- 0x2312a102 +mem-write: 0x800067b9 <- 0xe312e103 +mem-write: 0x800067bd <- 0x931e07c2 +mem-write: 0x800067c1 <- 0x23127107 +mem-write: 0x800067c5 <- 0x1300f128 +mem-write: 0x800067c9 <- 0x2300000c +mem-write: 0x800067cd <- 0x9300912e +mem-write: 0x800067d1 <- 0x13000c04 +mem-write: 0x800067d5 <- 0x300090c +mem-write: 0x800067d9 <- 0x93010129 +mem-write: 0x800067dd <- 0x930b410c +mem-write: 0x800067e1 <- 0x9309410d +mem-write: 0x800067e5 <- 0x1307e10b +mem-write: 0x800067e9 <- 0x130b610d +mem-write: 0x800067ed <- 0x13000007 +mem-write: 0x800067f1 <- 0x6f000d86 +mem-write: 0x800067f5 <- 0x1301c000 +mem-write: 0x800067f9 <- 0x23001717 +VXDRV: upload 1024 bytes to 0x800067fd +mem-write: 0x800067fd <- 0x1300f610 +mem-write: 0x80006801 <- 0x13010717 +mem-write: 0x80006805 <- 0x13ffe606 +mem-write: 0x80006809 <- 0x63010757 +mem-write: 0x8000680d <- 0x83057604 +mem-write: 0x80006811 <- 0x93000657 +mem-write: 0x80006815 <- 0x93010795 +mem-write: 0x80006819 <- 0x934105d5 +mem-write: 0x8000681d <- 0x63001797 +mem-write: 0x80006821 <- 0x130005d4 +mem-write: 0x80006825 <- 0x93001767 +mem-write: 0x80006829 <- 0x93010797 +mem-write: 0x8000682d <- 0x930107d7 +mem-write: 0x80006831 <- 0x13002775 +mem-write: 0x80006835 <- 0xe30017e5 +mem-write: 0x80006839 <- 0x13fc0580 +mem-write: 0x8000683d <- 0x23001717 +mem-write: 0x80006841 <- 0x1300a610 +mem-write: 0x80006845 <- 0x13010717 +mem-write: 0x80006849 <- 0x13ffe606 +mem-write: 0x8000684d <- 0xe3010757 +mem-write: 0x80006851 <- 0x13fd7610 +mem-write: 0x80006855 <- 0x93000c87 +mem-write: 0x80006859 <- 0x307c107 +mem-write: 0x8000685d <- 0x930007d6 +mem-write: 0x80006861 <- 0x13002787 +mem-write: 0x80006865 <- 0x23002707 +mem-write: 0x80006869 <- 0xe3fec71f +mem-write: 0x8000686d <- 0x23ffb798 +mem-write: 0x80006871 <- 0x130c0116 +mem-write: 0x80006875 <- 0x13000007 +mem-write: 0x80006879 <- 0x6f0cc106 +mem-write: 0x8000687d <- 0x1301c000 +mem-write: 0x80006881 <- 0x23001717 +mem-write: 0x80006885 <- 0x1300f610 +mem-write: 0x80006889 <- 0x13010717 +mem-write: 0x8000688d <- 0x13ffe606 +mem-write: 0x80006891 <- 0x63010757 +mem-write: 0x80006895 <- 0x8305a604 +mem-write: 0x80006899 <- 0x93000657 +mem-write: 0x8000689d <- 0x93010795 +mem-write: 0x800068a1 <- 0x934105d5 +mem-write: 0x800068a5 <- 0x63001797 +mem-write: 0x800068a9 <- 0x130005d4 +mem-write: 0x800068ad <- 0x93001767 +mem-write: 0x800068b1 <- 0x93010797 +mem-write: 0x800068b5 <- 0x930107d7 +mem-write: 0x800068b9 <- 0x13002775 +mem-write: 0x800068bd <- 0xe30017e5 +mem-write: 0x800068c1 <- 0x13fc0580 +mem-write: 0x800068c5 <- 0x23001717 +mem-write: 0x800068c9 <- 0x1300a610 +mem-write: 0x800068cd <- 0x13010717 +mem-write: 0x800068d1 <- 0x13ffe606 +mem-write: 0x800068d5 <- 0xe3010757 +mem-write: 0x800068d9 <- 0x13fda610 +mem-write: 0x800068dd <- 0x13000007 +mem-write: 0x800068e1 <- 0x6f0cc106 +mem-write: 0x800068e5 <- 0x1301c000 +mem-write: 0x800068e9 <- 0x23001717 +mem-write: 0x800068ed <- 0x1300f610 +mem-write: 0x800068f1 <- 0x13010717 +mem-write: 0x800068f5 <- 0x13ffe606 +mem-write: 0x800068f9 <- 0x63010757 +mem-write: 0x800068fd <- 0x8305a604 +mem-write: 0x80006901 <- 0x93000657 +mem-write: 0x80006905 <- 0x93010795 +mem-write: 0x80006909 <- 0x934105d5 +mem-write: 0x8000690d <- 0x63001797 +mem-write: 0x80006911 <- 0x130005d4 +mem-write: 0x80006915 <- 0x93001767 +mem-write: 0x80006919 <- 0x93010797 +mem-write: 0x8000691d <- 0x930107d7 +mem-write: 0x80006921 <- 0x13002775 +mem-write: 0x80006925 <- 0xe30017e5 +mem-write: 0x80006929 <- 0x13fc0580 +mem-write: 0x8000692d <- 0x23001717 +mem-write: 0x80006931 <- 0x1300a610 +mem-write: 0x80006935 <- 0x13010717 +mem-write: 0x80006939 <- 0x13ffe606 +mem-write: 0x8000693d <- 0xe3010757 +mem-write: 0x80006941 <- 0x93fda610 +mem-write: 0x80006945 <- 0x13000005 +mem-write: 0x80006949 <- 0x13000d86 +mem-write: 0x8000694d <- 0x30cc107 +mem-write: 0x80006951 <- 0x83000655 +mem-write: 0x80006955 <- 0x13000757 +mem-write: 0x80006959 <- 0x13ffe606 +mem-write: 0x8000695d <- 0xb3ffe707 +mem-write: 0x80006961 <- 0xb300a787 +mem-write: 0x80006965 <- 0x9300b787 +mem-write: 0x80006969 <- 0x230107d5 +mem-write: 0x8000696d <- 0x9300f611 +mem-write: 0x80006971 <- 0xe30015f5 +mem-write: 0x80006975 <- 0x13fda71e +mem-write: 0x80006979 <- 0x93000c06 +mem-write: 0x8000697d <- 0x1307c105 +mem-write: 0x80006981 <- 0xef098105 +mem-write: 0x80006985 <- 0x83c2dfe0 +mem-write: 0x80006989 <- 0x331ac157 +mem-write: 0x8000698d <- 0x93009907 +mem-write: 0x80006991 <- 0x13001484 +mem-write: 0x80006995 <- 0x23030786 +mem-write: 0x80006999 <- 0xe300c700 +mem-write: 0x8000699d <- 0x13e49458 +mem-write: 0x800069a1 <- 0x3fff445 +mem-write: 0x800069a5 <- 0x13010127 +mem-write: 0x800069a9 <- 0x3341f555 +mem-write: 0x800069ad <- 0x8300a475 +mem-write: 0x800069b1 <- 0x1301c124 +mem-write: 0x800069b5 <- 0x33001509 +mem-write: 0x800069b9 <- 0x33012709 +mem-write: 0x800069bd <- 0x1300a70c +mem-write: 0x800069c1 <- 0x63004007 +mem-write: 0x800069c5 <- 0x1304f75e +mem-write: 0x800069c9 <- 0xe3005007 +mem-write: 0x800069cd <- 0x8300e780 +mem-write: 0x800069d1 <- 0x13ffe947 +mem-write: 0x800069d5 <- 0x93ffe907 +mem-write: 0x800069d9 <- 0x6307f7f7 +mem-write: 0x800069dd <- 0x93780444 +mem-write: 0x800069e1 <- 0x1302e006 +mem-write: 0x800069e5 <- 0x93038006 +mem-write: 0x800069e9 <- 0x63030005 +mem-write: 0x800069ed <- 0x6300d78e +mem-write: 0x800069f1 <- 0x8378f652 +mem-write: 0x800069f5 <- 0x23fff747 +mem-write: 0x800069f9 <- 0x1300b700 +mem-write: 0x800069fd <- 0x93fff707 +mem-write: 0x80006a01 <- 0x6f07f7f7 +mem-write: 0x80006a05 <- 0x83fe9ff0 +mem-write: 0x80006a09 <- 0x93fff747 +mem-write: 0x80006a0d <- 0xe3038006 +mem-write: 0x80006a11 <- 0x9300f6f4 +mem-write: 0x80006a15 <- 0x93031007 +mem-write: 0x80006a19 <- 0xa3001484 +mem-write: 0x80006a1d <- 0xb7fef70f +mem-write: 0x80006a21 <- 0x13800155 +mem-write: 0x80006a25 <- 0x93000486 +mem-write: 0x80006a29 <- 0x13c1c585 +mem-write: 0x80006a2d <- 0xef000c05 +mem-write: 0x80006a31 <- 0x83039020 +mem-write: 0x80006a35 <- 0x3072157 +mem-write: 0x80006a39 <- 0x23014127 +mem-write: 0x80006a3d <- 0x93169128 +mem-write: 0x80006a41 <- 0x23fff7c7 +mem-write: 0x80006a45 <- 0x1316e122 +mem-write: 0x80006a49 <- 0x63011797 +mem-write: 0x80006a4d <- 0x1300071e +mem-write: 0x80006a51 <- 0xef000985 +mem-write: 0x80006a55 <- 0x63b9cfe0 +mem-write: 0x80006a59 <- 0x13220510 +mem-write: 0x80006a5d <- 0xef000985 +mem-write: 0x80006a61 <- 0x638ccfe0 +mem-write: 0x80006a65 <- 0x8320051a +mem-write: 0x80006a69 <- 0x300c126 +mem-write: 0x80006a6d <- 0x93124147 +mem-write: 0x80006a71 <- 0x23001487 +mem-write: 0x80006a75 <- 0x9300f6a0 +mem-write: 0x80006a79 <- 0x63000a87 +mem-write: 0x80006a7d <- 0x9302070a +mem-write: 0x80006a81 <- 0x6302e006 +mem-write: 0x80006a85 <- 0x31cd70c +mem-write: 0x80006a89 <- 0x930017c7 +mem-write: 0x80006a8d <- 0xe3001787 +mem-write: 0x80006a91 <- 0x93fe071a +mem-write: 0x80006a95 <- 0x63045006 +mem-write: 0x80006a99 <- 0x6f00fae6 +mem-write: 0x80006a9d <- 0x63014000 +mem-write: 0x80006aa1 <- 0x3015788 +mem-write: 0x80006aa5 <- 0x93fff7c7 +mem-write: 0x80006aa9 <- 0xe3fff787 +mem-write: 0x80006aad <- 0x23fed71a +mem-write: 0x80006ab1 <- 0x93000780 +mem-write: 0x80006ab5 <- 0x93000a87 +mem-write: 0x80006ab9 <- 0x13020006 +mem-write: 0x80006abd <- 0x302d006 +mem-write: 0x80006ac1 <- 0x630007c7 +mem-write: 0x80006ac5 <- 0x6300d704 +mem-write: 0x80006ac9 <- 0x9300c716 +mem-write: 0x80006acd <- 0x6f001787 +mem-write: 0x80006ad1 <- 0x13ff1ff0 +mem-write: 0x80006ad5 <- 0x6f000a84 +mem-write: 0x80006ad9 <- 0x300c000 +mem-write: 0x80006add <- 0x130007c7 +mem-write: 0x80006ae1 <- 0x23000684 +mem-write: 0x80006ae5 <- 0x9300e400 +mem-write: 0x80006ae9 <- 0x93001406 +mem-write: 0x80006aed <- 0xe3001787 +mem-write: 0x80006af1 <- 0x83fe0716 +mem-write: 0x80006af5 <- 0x93000126 +mem-write: 0x80006af9 <- 0x3002007 +mem-write: 0x80006afd <- 0x63fff447 +mem-write: 0x80006b01 <- 0x8312f686 +mem-write: 0x80006b05 <- 0x93004127 +mem-write: 0x80006b09 <- 0x63000786 +mem-write: 0x80006b0d <- 0x930097d4 +mem-write: 0x80006b11 <- 0x93000486 +mem-write: 0x80006b15 <- 0x63030007 +mem-write: 0x80006b19 <- 0xb302f716 +mem-write: 0x80006b1d <- 0x63415407 +mem-write: 0x80006b21 <- 0x1302f6d2 +mem-write: 0x80006b25 <- 0x6f030006 +mem-write: 0x80006b29 <- 0x63008000 +mem-write: 0x80006b2d <- 0x8300e6dc +mem-write: 0x80006b31 <- 0xa3ffe447 +mem-write: 0x80006b35 <- 0x13fe040f +mem-write: 0x80006b39 <- 0x33fff404 +mem-write: 0x80006b3d <- 0xe3415407 +mem-write: 0x80006b41 <- 0x3fec786 +mem-write: 0x80006b45 <- 0x93000127 +mem-write: 0x80006b49 <- 0x63003007 +mem-write: 0x80006b4d <- 0x830af702 +mem-write: 0x80006b51 <- 0x23008127 +mem-write: 0x80006b55 <- 0x93040a22 +mem-write: 0x80006b59 <- 0x93009786 +mem-write: 0x80006b5d <- 0x63017007 +mem-write: 0x80006b61 <- 0x130cd7f2 +mem-write: 0x80006b65 <- 0x93001007 +mem-write: 0x80006b69 <- 0x93004007 +mem-write: 0x80006b6d <- 0x13001797 +mem-write: 0x80006b71 <- 0x93014786 +mem-write: 0x80006b75 <- 0x13000705 +mem-write: 0x80006b79 <- 0xe3001707 +mem-write: 0x80006b7d <- 0x23fec6f8 +mem-write: 0x80006b81 <- 0x1304ba22 +mem-write: 0x80006b85 <- 0xef000a05 +mem-write: 0x80006b89 <- 0x23424010 +mem-write: 0x80006b8d <- 0x9304aa20 +mem-write: 0x80006b91 <- 0x93000a85 +mem-write: 0x80006b95 <- 0xef000504 +mem-write: 0x80006b99 <- 0x830a5020 +mem-write: 0x80006b9d <- 0x63018127 +mem-write: 0x80006ba1 <- 0x33000788 +mem-write: 0x80006ba5 <- 0x33415404 +mem-write: 0x80006ba9 <- 0x23008484 +mem-write: 0x80006bad <- 0x830087a0 +mem-write: 0x80006bb1 <- 0x31ec120 +mem-write: 0x80006bb5 <- 0x31e8124 +mem-write: 0x80006bb9 <- 0x831e0129 +mem-write: 0x80006bbd <- 0x31dc129 +mem-write: 0x80006bc1 <- 0x831d812a +mem-write: 0x80006bc5 <- 0x31d412a +mem-write: 0x80006bc9 <- 0x831d012b +mem-write: 0x80006bcd <- 0x31cc12b +mem-write: 0x80006bd1 <- 0x831c812c +mem-write: 0x80006bd5 <- 0x31c412c +mem-write: 0x80006bd9 <- 0x831c012d +mem-write: 0x80006bdd <- 0x131bc12d +mem-write: 0x80006be1 <- 0x83000485 +mem-write: 0x80006be5 <- 0x131e4124 +mem-write: 0x80006be9 <- 0x671f0101 +mem-write: 0x80006bed <- 0x83000080 +mem-write: 0x80006bf1 <- 0xb3004127 +mem-write: 0x80006bf5 <- 0x63009784 +mem-write: 0x80006bf9 <- 0x835004c8 +VXDRV: upload 1024 bytes to 0x80006bfd +mem-write: 0x80006bfd <- 0x300c127 +mem-write: 0x80006c01 <- 0x83008127 +mem-write: 0x80006c05 <- 0xb30007a7 +mem-write: 0x80006c09 <- 0x2300f707 +mem-write: 0x80006c0d <- 0x8300f124 +mem-write: 0x80006c11 <- 0x23008127 +mem-write: 0x80006c15 <- 0x93040a22 +mem-write: 0x80006c19 <- 0x93003786 +mem-write: 0x80006c1d <- 0xe3017007 +mem-write: 0x80006c21 <- 0x93f4d7e2 +mem-write: 0x80006c25 <- 0x6f000005 +mem-write: 0x80006c29 <- 0x93f5dff0 +mem-write: 0x80006c2d <- 0xe3030007 +mem-write: 0x80006c31 <- 0xb3f2f710 +mem-write: 0x80006c35 <- 0x93415407 +mem-write: 0x80006c39 <- 0xe3001006 +mem-write: 0x80006c3d <- 0x6feef6c4 +mem-write: 0x80006c41 <- 0x83f11ff0 +mem-write: 0x80006c45 <- 0x23008124 +mem-write: 0x80006c49 <- 0x93009122 +mem-write: 0x80006c4d <- 0x6302a007 +mem-write: 0x80006c51 <- 0x23ec97d0 +mem-write: 0x80006c55 <- 0x6f00f122 +mem-write: 0x80006c59 <- 0x3eb8ff0 +mem-write: 0x80006c5d <- 0xe30007c7 +mem-write: 0x80006c61 <- 0x3e2070a +mem-write: 0x80006c65 <- 0x930017c7 +mem-write: 0x80006c69 <- 0xa3001787 +mem-write: 0x80006c6d <- 0xe3fee78f +mem-write: 0x80006c71 <- 0x6ffe071a +mem-write: 0x80006c75 <- 0x3e21ff0 +mem-write: 0x80006c79 <- 0xb700c127 +mem-write: 0x80006c7d <- 0x93000027 +mem-write: 0x80006c81 <- 0x2370f787 +mem-write: 0x80006c85 <- 0x6f00f720 +mem-write: 0x80006c89 <- 0x13e2dff0 +mem-write: 0x80006c8d <- 0xa3031007 +mem-write: 0x80006c91 <- 0x1312e102 +mem-write: 0x80006c95 <- 0x2302e007 +mem-write: 0x80006c99 <- 0x9312e103 +mem-write: 0x80006c9d <- 0x63001484 +mem-write: 0x80006ca1 <- 0x932af05c +mem-write: 0x80006ca5 <- 0xa3030007 +mem-write: 0x80006ca9 <- 0x9312f103 +mem-write: 0x80006cad <- 0x13128107 +mem-write: 0x80006cb1 <- 0x23fff404 +mem-write: 0x80006cb5 <- 0x6f00f128 +mem-write: 0x80006cb9 <- 0x93b11ff0 +mem-write: 0x80006cbd <- 0x130b410c +mem-write: 0x80006cc1 <- 0x93000c87 +mem-write: 0x80006cc5 <- 0x1307c107 +mem-write: 0x80006cc9 <- 0x83090106 +mem-write: 0x80006ccd <- 0x930007d6 +mem-write: 0x80006cd1 <- 0x13002787 +mem-write: 0x80006cd5 <- 0x23002707 +mem-write: 0x80006cd9 <- 0xe3fed71f +mem-write: 0x80006cdd <- 0xb7fec798 +mem-write: 0x80006ce1 <- 0x93000047 +mem-write: 0x80006ce5 <- 0x2308e787 +mem-write: 0x80006ce9 <- 0xb70cf113 +mem-write: 0x80006ced <- 0x93000087 +mem-write: 0x80006cf1 <- 0x23fff787 +mem-write: 0x80006cf5 <- 0xb700f12e +mem-write: 0x80006cf9 <- 0x93ffffc7 +mem-write: 0x80006cfd <- 0x1312410a +mem-write: 0x80006d01 <- 0x130d0104 +mem-write: 0x80006d05 <- 0x1301000e +mem-write: 0x80006d09 <- 0x930c8d83 +mem-write: 0x80006d0d <- 0x23002787 +mem-write: 0x80006d11 <- 0x23034124 +mem-write: 0x80006d15 <- 0x93035122 +mem-write: 0x80006d19 <- 0x93000004 +mem-write: 0x80006d1d <- 0x13000c8a +mem-write: 0x80006d21 <- 0x93160109 +mem-write: 0x80006d25 <- 0x9300040c +mem-write: 0x80006d29 <- 0x230aa10b +mem-write: 0x80006d2d <- 0x1302f120 +mem-write: 0x80006d31 <- 0x13000e0a +mem-write: 0x80006d35 <- 0x93000304 +mem-write: 0x80006d39 <- 0x13000906 +mem-write: 0x80006d3d <- 0x93098106 +mem-write: 0x80006d41 <- 0x13000a85 +mem-write: 0x80006d45 <- 0xef000405 +mem-write: 0x80006d49 <- 0x13e99fe0 +mem-write: 0x80006d4d <- 0x9304c107 +mem-write: 0x80006d51 <- 0x83098107 +mem-write: 0x80006d55 <- 0x930007d6 +mem-write: 0x80006d59 <- 0x13002787 +mem-write: 0x80006d5d <- 0x23002707 +mem-write: 0x80006d61 <- 0xe3fed71f +mem-write: 0x80006d65 <- 0x83ffa798 +mem-write: 0x80006d69 <- 0x8301c127 +mem-write: 0x80006d6d <- 0x3305e155 +mem-write: 0x80006d71 <- 0x8300f5f6 +mem-write: 0x80006d75 <- 0x33020127 +mem-write: 0x80006d79 <- 0x6300f605 +mem-write: 0x80006d7d <- 0x133aa050 +mem-write: 0x80006d81 <- 0x33090006 +mem-write: 0x80006d85 <- 0x1340a606 +mem-write: 0x80006d89 <- 0x93000c87 +mem-write: 0x80006d8d <- 0x8304c107 +mem-write: 0x80006d91 <- 0x930007d6 +mem-write: 0x80006d95 <- 0x13002787 +mem-write: 0x80006d99 <- 0x23002707 +mem-write: 0x80006d9d <- 0xe3fed71f +mem-write: 0x80006da1 <- 0x63ff3798 +mem-write: 0x80006da5 <- 0x9306c054 +mem-write: 0x80006da9 <- 0x1300f007 +mem-write: 0x80006dad <- 0x63000c87 +mem-write: 0x80006db1 <- 0x1302c7dc +mem-write: 0x80006db5 <- 0x93ff0606 +mem-write: 0x80006db9 <- 0x13004656 +mem-write: 0x80006dbd <- 0x13001687 +mem-write: 0x80006dc1 <- 0x33001717 +mem-write: 0x80006dc5 <- 0x9300ec87 +mem-write: 0x80006dc9 <- 0x93000c87 +mem-write: 0x80006dcd <- 0x23002787 +mem-write: 0x80006dd1 <- 0xe3fe079f +mem-write: 0x80006dd5 <- 0x13fee79c +mem-write: 0x80006dd9 <- 0x33080006 +mem-write: 0x80006ddd <- 0x9340a606 +mem-write: 0x80006de1 <- 0x33004696 +mem-write: 0x80006de5 <- 0x1340d606 +mem-write: 0x80006de9 <- 0x33001616 +mem-write: 0x80006ded <- 0x8300cd86 +mem-write: 0x80006df1 <- 0x83000757 +mem-write: 0x80006df5 <- 0xb3230656 +mem-write: 0x80006df9 <- 0x2300d7f7 +mem-write: 0x80006dfd <- 0x9300f710 +mem-write: 0x80006e01 <- 0x93010595 +mem-write: 0x80006e05 <- 0x634105d5 +mem-write: 0x80006e09 <- 0x931605c0 +mem-write: 0x80006e0d <- 0x13098107 +mem-write: 0x80006e11 <- 0x3000c87 +mem-write: 0x80006e15 <- 0x830007d6 +mem-write: 0x80006e19 <- 0x93000756 +mem-write: 0x80006e1d <- 0x13002787 +mem-write: 0x80006e21 <- 0x63002707 +mem-write: 0x80006e25 <- 0xe302d614 +mem-write: 0x80006e29 <- 0x13fefb96 +mem-write: 0x80006e2d <- 0x93000a87 +mem-write: 0x80006e31 <- 0x83098107 +mem-write: 0x80006e35 <- 0x930007d6 +mem-write: 0x80006e39 <- 0x13002787 +mem-write: 0x80006e3d <- 0x23002707 +mem-write: 0x80006e41 <- 0xe3fed71f +mem-write: 0x80006e45 <- 0xb3ffa798 +mem-write: 0x80006e49 <- 0x13014484 +mem-write: 0x80006e4d <- 0x93014404 +mem-write: 0x80006e51 <- 0x1312cd87 +mem-write: 0x80006e55 <- 0xe3001a5a +mem-write: 0x80006e59 <- 0x83eef410 +mem-write: 0x80006e5d <- 0x30c6157 +mem-write: 0x80006e61 <- 0x1308e157 +mem-write: 0x80006e65 <- 0x3000c84 +mem-write: 0x80006e69 <- 0xb302812a +mem-write: 0x80006e6d <- 0x3700e787 +mem-write: 0x80006e71 <- 0x93ffffc7 +mem-write: 0x80006e75 <- 0x13000a8c +mem-write: 0x80006e79 <- 0x83f72707 +mem-write: 0x80006e7d <- 0xb302412a +mem-write: 0x80006e81 <- 0x2300e787 +mem-write: 0x80006e85 <- 0x130cf113 +mem-write: 0x80006e89 <- 0x9307c107 +mem-write: 0x80006e8d <- 0x13000c87 +mem-write: 0x80006e91 <- 0x830c8106 +mem-write: 0x80006e95 <- 0x930007d6 +mem-write: 0x80006e99 <- 0x13002787 +mem-write: 0x80006e9d <- 0x23002707 +mem-write: 0x80006ea1 <- 0xe3fed71f +mem-write: 0x80006ea5 <- 0x13fec798 +mem-write: 0x80006ea9 <- 0x93000007 +mem-write: 0x80006ead <- 0x6f098107 +mem-write: 0x80006eb1 <- 0x3008000 +mem-write: 0x80006eb5 <- 0x93000c57 +mem-write: 0x80006eb9 <- 0x23002787 +mem-write: 0x80006ebd <- 0x13fee79f +mem-write: 0x80006ec1 <- 0xe3002c0c +mem-write: 0x80006ec5 <- 0x13ffa798 +mem-write: 0x80006ec9 <- 0x37028d8d +mem-write: 0x80006ecd <- 0x9300001c +mem-write: 0x80006ed1 <- 0x6f118d8d +mem-write: 0x80006ed5 <- 0x13010000 +mem-write: 0x80006ed9 <- 0x63001c5c +mem-write: 0x80006edd <- 0x1329bd00 +mem-write: 0x80006ee1 <- 0x93014d0d +mem-write: 0x80006ee5 <- 0x13000c85 +mem-write: 0x80006ee9 <- 0xef000d85 +mem-write: 0x80006eed <- 0x93de9fd0 +mem-write: 0x80006ef1 <- 0x93000507 +mem-write: 0x80006ef5 <- 0x13000c85 +mem-write: 0x80006ef9 <- 0x63000d05 +mem-write: 0x80006efd <- 0xef26f040 +mem-write: 0x80006f01 <- 0xe3dd5fd0 +mem-write: 0x80006f05 <- 0x93fca04a +mem-write: 0x80006f09 <- 0x13000906 +mem-write: 0x80006f0d <- 0x93000c86 +mem-write: 0x80006f11 <- 0x13000c85 +mem-write: 0x80006f15 <- 0xef000d05 +mem-write: 0x80006f19 <- 0x13cc9fe0 +mem-write: 0x80006f1d <- 0x93098106 +mem-write: 0x80006f21 <- 0x93000906 +mem-write: 0x80006f25 <- 0x13000605 +mem-write: 0x80006f29 <- 0xef000d05 +mem-write: 0x80006f2d <- 0xb389dfe0 +mem-write: 0x80006f31 <- 0x6f018484 +mem-write: 0x80006f35 <- 0x93fa5ff0 +mem-write: 0x80006f39 <- 0xb712410a +mem-write: 0x80006f3d <- 0x93800155 +mem-write: 0x80006f41 <- 0x13bf8585 +mem-write: 0x80006f45 <- 0xb7000a85 +mem-write: 0x80006f49 <- 0xef000024 +mem-write: 0x80006f4d <- 0x9331c020 +mem-write: 0x80006f51 <- 0x6f70f484 +mem-write: 0x80006f55 <- 0x13ae1ff0 +mem-write: 0x80006f59 <- 0xe312710c +mem-write: 0x80006f5d <- 0x23ac0792 +mem-write: 0x80006f61 <- 0x6f018128 +mem-write: 0x80006f65 <- 0x93865ff0 +mem-write: 0x80006f69 <- 0x1304c107 +mem-write: 0x80006f6d <- 0x6f000c87 +mem-write: 0x80006f71 <- 0x9300c000 +mem-write: 0x80006f75 <- 0xe305e106 +mem-write: 0x80006f79 <- 0x3e8f68a +mem-write: 0x80006f7d <- 0x830007d6 +mem-write: 0x80006f81 <- 0x93000756 +mem-write: 0x80006f85 <- 0x13002787 +mem-write: 0x80006f89 <- 0xe3002707 +mem-write: 0x80006f8d <- 0x83fed604 +mem-write: 0x80006f91 <- 0x30e2157 +mem-write: 0x80006f95 <- 0xb301c127 +mem-write: 0x80006f99 <- 0x6300f777 +mem-write: 0x80006f9d <- 0x1300e79e +mem-write: 0x80006fa1 <- 0xef000c85 +mem-write: 0x80006fa5 <- 0xe3b89fd0 +mem-write: 0x80006fa9 <- 0x13e60512 +mem-write: 0x80006fad <- 0xef000c85 +mem-write: 0x80006fb1 <- 0xe3e41fd0 +mem-write: 0x80006fb5 <- 0x93e4051c +mem-write: 0x80006fb9 <- 0x130ec105 +mem-write: 0x80006fbd <- 0xef000c05 +mem-write: 0x80006fc1 <- 0x93c1dfd0 +mem-write: 0x80006fc5 <- 0x13108105 +mem-write: 0x80006fc9 <- 0xef000c85 +mem-write: 0x80006fcd <- 0x3c11fd0 +mem-write: 0x80006fd1 <- 0x30ec156 +mem-write: 0x80006fd5 <- 0x8310a155 +mem-write: 0x80006fd9 <- 0x130ee158 +mem-write: 0x80006fdd <- 0x13fff646 +mem-write: 0x80006fe1 <- 0x13010616 +mem-write: 0x80006fe5 <- 0x23010656 +mem-write: 0x80006fe9 <- 0xb30ec116 +mem-write: 0x80006fed <- 0x9340a885 +mem-write: 0x80006ff1 <- 0x63000506 +mem-write: 0x80006ff5 <- 0x8306b05e +mem-write: 0x80006ff9 <- 0x13024126 +VXDRV: upload 1024 bytes to 0x80006ffd +mem-write: 0x80006ffd <- 0x93108107 +mem-write: 0x80007001 <- 0x83120107 +mem-write: 0x80007005 <- 0x13000755 +mem-write: 0x80007009 <- 0x93002707 +mem-write: 0x8000700d <- 0x23002686 +mem-write: 0x80007011 <- 0xe3feb69f +mem-write: 0x80007015 <- 0x23fef718 +mem-write: 0x80007019 <- 0x1312011e +mem-write: 0x8000701d <- 0x93108107 +mem-write: 0x80007021 <- 0x6f0ec106 +mem-write: 0x80007025 <- 0x3008000 +mem-write: 0x80007029 <- 0x130006d6 +mem-write: 0x8000702d <- 0x23002707 +mem-write: 0x80007031 <- 0x93fec71f +mem-write: 0x80007035 <- 0xe3002686 +mem-write: 0x80007039 <- 0x83fef718 +mem-write: 0x8000703d <- 0x23024127 +mem-write: 0x80007041 <- 0x13120110 +mem-write: 0x80007045 <- 0x130ec107 +mem-write: 0x80007049 <- 0x8313c106 +mem-write: 0x8000704d <- 0x930007d6 +mem-write: 0x80007051 <- 0x13002787 +mem-write: 0x80007055 <- 0x23002707 +mem-write: 0x80007059 <- 0xe3fed71f +mem-write: 0x8000705d <- 0x83fec798 +mem-write: 0x80007061 <- 0xb310a156 +mem-write: 0x80007065 <- 0x23411505 +mem-write: 0x80007069 <- 0x13100112 +mem-write: 0x8000706d <- 0x63000685 +mem-write: 0x80007071 <- 0x232c0586 +mem-write: 0x80007075 <- 0x9302d126 +mem-write: 0x80007079 <- 0x63f6f007 +mem-write: 0x8000707d <- 0x1306f5c8 +mem-write: 0x80007081 <- 0xef0ec105 +mem-write: 0x80007085 <- 0x83d89fd0 +mem-write: 0x80007089 <- 0x9302c126 +mem-write: 0x8000708d <- 0x93000505 +mem-write: 0x80007091 <- 0x13120107 +mem-write: 0x80007095 <- 0x3104105 +mem-write: 0x80007099 <- 0x30ec156 +mem-write: 0x8000709d <- 0x63108157 +mem-write: 0x800070a1 <- 0x132ee60a +mem-write: 0x800070a5 <- 0x13000007 +mem-write: 0x800070a9 <- 0x3000706 +mem-write: 0x800070ad <- 0x30007d7 +mem-write: 0x800070b1 <- 0x93000558 +mem-write: 0x800070b5 <- 0x33ffe787 +mem-write: 0x800070b9 <- 0x3340c707 +mem-write: 0x800070bd <- 0x13410707 +mem-write: 0x800070c1 <- 0x23010756 +mem-write: 0x800070c5 <- 0x1300e791 +mem-write: 0x800070c9 <- 0x1310a107 +mem-write: 0x800070cd <- 0x13001676 +mem-write: 0x800070d1 <- 0xe3ffe505 +mem-write: 0x800070d5 <- 0x13fce79c +mem-write: 0x800070d9 <- 0x93001006 +mem-write: 0x800070dd <- 0x13000907 +mem-write: 0x800070e1 <- 0x13040007 +mem-write: 0x800070e5 <- 0xef108105 +mem-write: 0x800070e9 <- 0x938bcfe0 +mem-write: 0x800070ed <- 0x13000c85 +mem-write: 0x800070f1 <- 0xef108105 +mem-write: 0x800070f5 <- 0x6fe24fe0 +mem-write: 0x800070f9 <- 0x83d15ff0 +mem-write: 0x800070fd <- 0x93008127 +mem-write: 0x80007101 <- 0x6ffff784 +mem-write: 0x80007105 <- 0x83b45ff0 +mem-write: 0x80007109 <- 0x2300c127 +mem-write: 0x8000710d <- 0x13120102 +mem-write: 0x80007111 <- 0x23000a84 +mem-write: 0x80007115 <- 0x6f0007a0 +mem-write: 0x80007119 <- 0x93af9ff0 +mem-write: 0x8000711d <- 0x13000c87 +mem-write: 0x80007121 <- 0x930e4107 +mem-write: 0x80007125 <- 0x23002787 +mem-write: 0x80007129 <- 0xe3fe079f +mem-write: 0x8000712d <- 0x6ffee79c +mem-write: 0x80007131 <- 0x83cd1ff0 +mem-write: 0x80007135 <- 0x93010127 +mem-write: 0x80007139 <- 0x6312410a +mem-write: 0x8000713d <- 0xb706078a +mem-write: 0x80007141 <- 0x93800155 +mem-write: 0x80007145 <- 0x13c00585 +mem-write: 0x80007149 <- 0xb7000a85 +mem-write: 0x8000714d <- 0xef000024 +mem-write: 0x80007151 <- 0x93118020 +mem-write: 0x80007155 <- 0x6f70f484 +mem-write: 0x80007159 <- 0x938ddff0 +mem-write: 0x8000715d <- 0x6f0e810b +mem-write: 0x80007161 <- 0x93bd8ff0 +mem-write: 0x80007165 <- 0x23031007 +mem-write: 0x80007169 <- 0x93fef90f +mem-write: 0x8000716d <- 0x6f001484 +mem-write: 0x80007171 <- 0x938b1ff0 +mem-write: 0x80007175 <- 0x23001787 +mem-write: 0x80007179 <- 0x6f00f700 +mem-write: 0x8000717d <- 0x938a5ff0 +mem-write: 0x80007181 <- 0xb712410a +mem-write: 0x80007185 <- 0x93800155 +mem-write: 0x80007189 <- 0x13c18585 +mem-write: 0x8000718d <- 0xb7000a85 +mem-write: 0x80007191 <- 0xef000024 +mem-write: 0x80007195 <- 0x930d4020 +mem-write: 0x80007199 <- 0x6f70f484 +mem-write: 0x8000719d <- 0x83899ff0 +mem-write: 0x800071a1 <- 0x131ac157 +mem-write: 0x800071a5 <- 0x1312610c +mem-write: 0x800071a9 <- 0x6f127109 +mem-write: 0x800071ad <- 0xb7815ff0 +mem-write: 0x800071b1 <- 0x93800155 +mem-write: 0x800071b5 <- 0x13c0c585 +mem-write: 0x800071b9 <- 0xb7000a85 +mem-write: 0x800071bd <- 0xef000024 +mem-write: 0x800071c1 <- 0x930a8020 +mem-write: 0x800071c5 <- 0x6f70f484 +mem-write: 0x800071c9 <- 0x9386dff0 +mem-write: 0x800071cd <- 0x13098105 +mem-write: 0x800071d1 <- 0xef07c105 +mem-write: 0x800071d5 <- 0x93d44fe0 +mem-write: 0x800071d9 <- 0x13c20b05 +mem-write: 0x800071dd <- 0xef098105 +mem-write: 0x800071e1 <- 0x63af5fd0 +mem-write: 0x800071e5 <- 0xe3fe0516 +mem-write: 0x800071e9 <- 0x8382044c +mem-write: 0x800071ed <- 0x13ffe947 +mem-write: 0x800071f1 <- 0x13fd2787 +mem-write: 0x800071f5 <- 0x13001737 +mem-write: 0x800071f9 <- 0x33fff747 +mem-write: 0x800071fd <- 0x300ec07 +mem-write: 0x80007201 <- 0x13000747 +mem-write: 0x80007205 <- 0xe3001777 +mem-write: 0x80007209 <- 0x1380070c +mem-write: 0x8000720d <- 0x93ffe907 +mem-write: 0x80007211 <- 0x6f07f7f7 +mem-write: 0x80007215 <- 0x93fccff0 +mem-write: 0x80007219 <- 0xa3001787 +mem-write: 0x8000721d <- 0x6ffef70f +mem-write: 0x80007221 <- 0x13801ff0 +mem-write: 0x80007225 <- 0x930d0104 +mem-write: 0x80007229 <- 0x13000405 +mem-write: 0x8000722d <- 0xb707c105 +mem-write: 0x80007231 <- 0xef00004c +mem-write: 0x80007235 <- 0x939a9fd0 +mem-write: 0x80007239 <- 0x93000004 +mem-write: 0x8000723d <- 0x130e810b +mem-write: 0x80007241 <- 0x930cc109 +mem-write: 0x80007245 <- 0x930d210a +mem-write: 0x80007249 <- 0x83ffec8c +mem-write: 0x8000724d <- 0x930e8157 +mem-write: 0x80007251 <- 0x630077f7 +mem-write: 0x80007255 <- 0x130c079a +mem-write: 0x80007259 <- 0x930b4107 +mem-write: 0x8000725d <- 0x83000407 +mem-write: 0x80007261 <- 0x930007d6 +mem-write: 0x80007265 <- 0x13002787 +mem-write: 0x80007269 <- 0x23002707 +mem-write: 0x8000726d <- 0xe3fed71f +mem-write: 0x80007271 <- 0x13ff7798 +mem-write: 0x80007275 <- 0x230b4105 +mem-write: 0x80007279 <- 0xef0c0116 +mem-write: 0x8000727d <- 0x13f40fd0 +mem-write: 0x80007281 <- 0xef0b4105 +mem-write: 0x80007285 <- 0x13f38fd0 +mem-write: 0x80007289 <- 0x93000006 +mem-write: 0x8000728d <- 0x13000906 +mem-write: 0x80007291 <- 0x83000b87 +mem-write: 0x80007295 <- 0x830006d5 +mem-write: 0x80007299 <- 0x93000757 +mem-write: 0x8000729d <- 0x13ffe686 +mem-write: 0x800072a1 <- 0xb3ffe707 +mem-write: 0x800072a5 <- 0xb300b787 +mem-write: 0x800072a9 <- 0x1300c787 +mem-write: 0x800072ad <- 0x230107d6 +mem-write: 0x800072b1 <- 0x1300f691 +mem-write: 0x800072b5 <- 0xe3001676 +mem-write: 0x800072b9 <- 0x83fd571e +mem-write: 0x800072bd <- 0x30b6157 +mem-write: 0x800072c1 <- 0x930b8157 +mem-write: 0x800072c5 <- 0x23003787 +mem-write: 0x800072c9 <- 0x630af11b +mem-write: 0x800072cd <- 0x13020700 +mem-write: 0x800072d1 <- 0xef0b4105 +mem-write: 0x800072d5 <- 0x83ee8fd0 +mem-write: 0x800072d9 <- 0x30b6157 +mem-write: 0x800072dd <- 0x930b8157 +mem-write: 0x800072e1 <- 0x23001787 +mem-write: 0x800072e5 <- 0xe30af11b +mem-write: 0x800072e9 <- 0x83fe0714 +mem-write: 0x800072ed <- 0x630cc157 +mem-write: 0x800072f1 <- 0x8302079c +mem-write: 0x800072f5 <- 0x630b6157 +mem-write: 0x800072f9 <- 0x1302fce8 +mem-write: 0x800072fd <- 0x93000407 +mem-write: 0x80007301 <- 0x830b4107 +mem-write: 0x80007305 <- 0x930007d6 +mem-write: 0x80007309 <- 0x13002787 +mem-write: 0x8000730d <- 0x23002707 +mem-write: 0x80007311 <- 0xe3fed71f +mem-write: 0x80007315 <- 0x23ff2798 +mem-write: 0x80007319 <- 0x930e0114 +mem-write: 0x8000731d <- 0x93fff484 +mem-write: 0x80007321 <- 0xe3fd5007 +mem-write: 0x80007325 <- 0x93f2f494 +mem-write: 0x80007329 <- 0x1307c105 +mem-write: 0x8000732d <- 0xef000405 +mem-write: 0x80007331 <- 0x13be8fe0 +mem-write: 0x80007335 <- 0x6f160109 +mem-write: 0x80007339 <- 0x138f4ff0 +mem-write: 0x8000733d <- 0x9310c107 +mem-write: 0x80007341 <- 0x830f0107 +mem-write: 0x80007345 <- 0x30007d8 +mem-write: 0x80007349 <- 0x93000756 +mem-write: 0x8000734d <- 0x13002787 +mem-write: 0x80007351 <- 0x63002707 +mem-write: 0x80007355 <- 0x1302c898 +mem-write: 0x80007359 <- 0xe3106106 +mem-write: 0x8000735d <- 0x3fec794 +mem-write: 0x80007361 <- 0x830ec157 +mem-write: 0x80007365 <- 0x63108157 +mem-write: 0x80007369 <- 0x9306f702 +mem-write: 0x8000736d <- 0x13000c87 +mem-write: 0x80007371 <- 0x930e4107 +mem-write: 0x80007375 <- 0x23002787 +mem-write: 0x80007379 <- 0xe3fe079f +mem-write: 0x8000737d <- 0x6ffee79c +mem-write: 0x80007381 <- 0x63a8dff0 +mem-write: 0x80007385 <- 0x930d1666 +mem-write: 0x80007389 <- 0x13120107 +mem-write: 0x8000738d <- 0x6f104105 +mem-write: 0x80007391 <- 0x13d09ff0 +mem-write: 0x80007395 <- 0x13000007 +mem-write: 0x80007399 <- 0x30ee103 +mem-write: 0x8000739d <- 0x30007d8 +mem-write: 0x800073a1 <- 0x93000556 +mem-write: 0x800073a5 <- 0x13ffe787 +mem-write: 0x800073a9 <- 0x33ffe505 +mem-write: 0x800073ad <- 0x33010606 +mem-write: 0x800073b1 <- 0x1300e607 +mem-write: 0x800073b5 <- 0x23010756 +mem-write: 0x800073b9 <- 0x1300e791 +mem-write: 0x800073bd <- 0xe3001677 +mem-write: 0x800073c1 <- 0x13fc651e +mem-write: 0x800073c5 <- 0x6f000006 +mem-write: 0x800073c9 <- 0x13d15ff0 +mem-write: 0x800073cd <- 0x63000687 +mem-write: 0x800073d1 <- 0x83060692 +mem-write: 0x800073d5 <- 0x6310e117 +mem-write: 0x800073d9 <- 0x930407ce +mem-write: 0x800073dd <- 0x6f120106 +mem-write: 0x800073e1 <- 0x23020000 +mem-write: 0x800073e5 <- 0x1300f690 +mem-write: 0x800073e9 <- 0x13001717 +mem-write: 0x800073ed <- 0x93010717 +mem-write: 0x800073f1 <- 0x93ffe686 +mem-write: 0x800073f5 <- 0x1310a107 +mem-write: 0x800073f9 <- 0xe3010757 +VXDRV: upload 1024 bytes to 0x800073fd +mem-write: 0x800073fd <- 0x83cef688 +mem-write: 0x80007401 <- 0x130006d7 +mem-write: 0x80007405 <- 0x13010796 +mem-write: 0x80007409 <- 0x93410656 +mem-write: 0x8000740d <- 0x63001797 +mem-write: 0x80007411 <- 0x13000654 +mem-write: 0x80007415 <- 0x93001767 +mem-write: 0x80007419 <- 0x93010797 +mem-write: 0x8000741d <- 0x130107d7 +mem-write: 0x80007421 <- 0x93002776 +mem-write: 0x80007425 <- 0xe30017e5 +mem-write: 0x80007429 <- 0x23fa060e +mem-write: 0x8000742d <- 0x6f00b690 +mem-write: 0x80007431 <- 0x13fb9ff0 +mem-write: 0x80007435 <- 0x9310c106 +mem-write: 0x80007439 <- 0x63120107 +mem-write: 0x8000743d <- 0x63080712 +mem-write: 0x80007441 <- 0x308c782 +mem-write: 0x80007445 <- 0x13000657 +mem-write: 0x80007449 <- 0x6f002606 +mem-write: 0x8000744d <- 0x3ff1ff0 +mem-write: 0x80007451 <- 0x13024126 +mem-write: 0x80007455 <- 0x93108107 +mem-write: 0x80007459 <- 0x3120107 +mem-write: 0x8000745d <- 0x13000755 +mem-write: 0x80007461 <- 0x13002707 +mem-write: 0x80007465 <- 0x23002606 +mem-write: 0x80007469 <- 0xe3fea61f +mem-write: 0x8000746d <- 0x23fef718 +mem-write: 0x80007471 <- 0x1312011e +mem-write: 0x80007475 <- 0x13108106 +mem-write: 0x80007479 <- 0x130ec107 +mem-write: 0x8000747d <- 0x3104105 +mem-write: 0x80007481 <- 0x13000758 +mem-write: 0x80007485 <- 0x13002707 +mem-write: 0x80007489 <- 0x23002606 +mem-write: 0x8000748d <- 0xe3ff061f +mem-write: 0x80007491 <- 0x3fea718 +mem-write: 0x80007495 <- 0x23024127 +mem-write: 0x80007499 <- 0x93120110 +mem-write: 0x8000749d <- 0x130ec108 +mem-write: 0x800074a1 <- 0x313c106 +mem-write: 0x800074a5 <- 0x13000758 +mem-write: 0x800074a9 <- 0x93002707 +mem-write: 0x800074ad <- 0x23002888 +mem-write: 0x800074b1 <- 0xe3ff089f +mem-write: 0x800074b5 <- 0x23fec718 +mem-write: 0x800074b9 <- 0x6f100112 +mem-write: 0x800074bd <- 0x13bddff0 +mem-write: 0x800074c1 <- 0x23001685 +mem-write: 0x800074c5 <- 0x6f10a115 +mem-write: 0x800074c9 <- 0x3c25ff0 +mem-write: 0x800074cd <- 0x83008527 +mem-write: 0x800074d1 <- 0x300c527 +mem-write: 0x800074d5 <- 0x83000526 +mem-write: 0x800074d9 <- 0x13004526 +mem-write: 0x800074dd <- 0x13fc0101 +mem-write: 0x800074e1 <- 0x93000105 +mem-write: 0x800074e5 <- 0x23014105 +mem-write: 0x800074e9 <- 0x2300e124 +mem-write: 0x800074ed <- 0x2300f126 +mem-write: 0x800074f1 <- 0x2302112e +mem-write: 0x800074f5 <- 0x2300c120 +mem-write: 0x800074f9 <- 0xef00d122 +mem-write: 0x800074fd <- 0x83bf5fe0 +mem-write: 0x80007501 <- 0x13026157 +mem-write: 0x80007505 <- 0x93000005 +mem-write: 0x80007509 <- 0x13fff7c7 +mem-write: 0x8000750d <- 0x63011797 +mem-write: 0x80007511 <- 0x1300071a +mem-write: 0x80007515 <- 0xef014105 +mem-write: 0x80007519 <- 0x13e14fd0 +mem-write: 0x8000751d <- 0x13001535 +mem-write: 0x80007521 <- 0x83001505 +mem-write: 0x80007525 <- 0x1303c120 +mem-write: 0x80007529 <- 0x67040101 +mem-write: 0x8000752d <- 0x13000080 +mem-write: 0x80007531 <- 0x670f0505 +mem-write: 0x80007535 <- 0x13000080 +mem-write: 0x80007539 <- 0x67128185 +mem-write: 0x8000753d <- 0x13000080 +mem-write: 0x80007541 <- 0x67128185 +mem-write: 0x80007545 <- 0x13000080 +mem-write: 0x80007549 <- 0x23f90101 +mem-write: 0x8000754d <- 0x13068124 +mem-write: 0x80007551 <- 0x83000584 +mem-write: 0x80007555 <- 0x2300e595 +mem-write: 0x80007559 <- 0x23069122 +mem-write: 0x8000755d <- 0x23072120 +mem-write: 0x80007561 <- 0x93061126 +mem-write: 0x80007565 <- 0x13000604 +mem-write: 0x80007569 <- 0x63000689 +mem-write: 0x8000756d <- 0x130405ca +mem-write: 0x80007571 <- 0xef008106 +mem-write: 0x80007575 <- 0x63434060 +mem-write: 0x80007579 <- 0x3040544 +mem-write: 0x8000757d <- 0xb700c127 +mem-write: 0x80007581 <- 0x830000f7 +mem-write: 0x80007585 <- 0xb306c120 +mem-write: 0x80007589 <- 0x3700e7f7 +mem-write: 0x8000758d <- 0xb3ffffe7 +mem-write: 0x80007591 <- 0x300e787 +mem-write: 0x80007595 <- 0x93068124 +mem-write: 0x80007599 <- 0x230017b7 +mem-write: 0x8000759d <- 0x9300f920 +mem-write: 0x800075a1 <- 0x23400007 +mem-write: 0x800075a5 <- 0x3700f4a0 +mem-write: 0x800075a9 <- 0x83000015 +mem-write: 0x800075ad <- 0x3064124 +mem-write: 0x800075b1 <- 0x13060129 +mem-write: 0x800075b5 <- 0x13800505 +mem-write: 0x800075b9 <- 0x67070101 +mem-write: 0x800075bd <- 0x83000080 +mem-write: 0x800075c1 <- 0x2300c457 +mem-write: 0x800075c5 <- 0x93000920 +mem-write: 0x800075c9 <- 0x630807f7 +mem-write: 0x800075cd <- 0x83020784 +mem-write: 0x800075d1 <- 0x306c120 +mem-write: 0x800075d5 <- 0x93068124 +mem-write: 0x800075d9 <- 0x23040007 +mem-write: 0x800075dd <- 0x300f4a0 +mem-write: 0x800075e1 <- 0x83060129 +mem-write: 0x800075e5 <- 0x13064124 +mem-write: 0x800075e9 <- 0x13000005 +mem-write: 0x800075ed <- 0x67070101 +mem-write: 0x800075f1 <- 0x83000080 +mem-write: 0x800075f5 <- 0x306c120 +mem-write: 0x800075f9 <- 0x93068124 +mem-write: 0x800075fd <- 0x23400007 +mem-write: 0x80007601 <- 0x300f4a0 +mem-write: 0x80007605 <- 0x83060129 +mem-write: 0x80007609 <- 0x13064124 +mem-write: 0x8000760d <- 0x13000005 +mem-write: 0x80007611 <- 0x67070101 +mem-write: 0x80007615 <- 0x83000080 +mem-write: 0x80007619 <- 0x1300c5d7 +mem-write: 0x8000761d <- 0x23fe0101 +mem-write: 0x80007621 <- 0x2300812c +mem-write: 0x80007625 <- 0x2300112e +mem-write: 0x80007629 <- 0x2300912a +mem-write: 0x8000762d <- 0x93012128 +mem-write: 0x80007631 <- 0x130027f7 +mem-write: 0x80007635 <- 0x63000584 +mem-write: 0x80007639 <- 0x93020788 +mem-write: 0x8000763d <- 0x23043587 +mem-write: 0x80007641 <- 0x2300f5a0 +mem-write: 0x80007645 <- 0x9300f5a8 +mem-write: 0x80007649 <- 0x23001007 +mem-write: 0x8000764d <- 0x8300f5aa +mem-write: 0x80007651 <- 0x301c120 +mem-write: 0x80007655 <- 0x83018124 +mem-write: 0x80007659 <- 0x3014124 +mem-write: 0x8000765d <- 0x13010129 +mem-write: 0x80007661 <- 0x67020101 +mem-write: 0x80007665 <- 0x93000080 +mem-write: 0x80007669 <- 0x1300c106 +mem-write: 0x8000766d <- 0x93008106 +mem-write: 0x80007671 <- 0xef000504 +mem-write: 0x80007675 <- 0x83ed5ff0 +mem-write: 0x80007679 <- 0x13008125 +mem-write: 0x8000767d <- 0x13000509 +mem-write: 0x80007681 <- 0xef000485 +mem-write: 0x80007685 <- 0x830b4000 +mem-write: 0x80007689 <- 0x6300c417 +mem-write: 0x8000768d <- 0x37040508 +mem-write: 0x80007691 <- 0x13800047 +mem-write: 0x80007695 <- 0x230e0707 +mem-write: 0x80007699 <- 0x302e4ae +mem-write: 0x8000769d <- 0x83008127 +mem-write: 0x800076a1 <- 0x9300c126 +mem-write: 0x800076a5 <- 0x230807e7 +mem-write: 0x800076a9 <- 0x2300f416 +mem-write: 0x800076ad <- 0x2300a420 +mem-write: 0x800076b1 <- 0x2300a428 +mem-write: 0x800076b5 <- 0x6300e42a +mem-write: 0x800076b9 <- 0xb3040698 +mem-write: 0x800076bd <- 0x830127e7 +mem-write: 0x800076c1 <- 0x2301c120 +mem-write: 0x800076c5 <- 0x300f416 +mem-write: 0x800076c9 <- 0x83018124 +mem-write: 0x800076cd <- 0x3014124 +mem-write: 0x800076d1 <- 0x13010129 +mem-write: 0x800076d5 <- 0x67020101 +mem-write: 0x800076d9 <- 0x13000080 +mem-write: 0x800076dd <- 0xe32007f7 +mem-write: 0x800076e1 <- 0x93f60718 +mem-write: 0x800076e5 <- 0x93ffc7f7 +mem-write: 0x800076e9 <- 0x130027e7 +mem-write: 0x800076ed <- 0x23043407 +mem-write: 0x800076f1 <- 0x9300f416 +mem-write: 0x800076f5 <- 0x23001007 +mem-write: 0x800076f9 <- 0x2300e420 +mem-write: 0x800076fd <- 0x2300e428 +mem-write: 0x80007701 <- 0x6f00f42a +mem-write: 0x80007705 <- 0x83f4dff0 +mem-write: 0x80007709 <- 0x1300e415 +mem-write: 0x8000770d <- 0xef000485 +mem-write: 0x80007711 <- 0x637a4060 +mem-write: 0x80007715 <- 0x83000516 +mem-write: 0x80007719 <- 0x6f00c417 +mem-write: 0x8000771d <- 0x3fa1ff0 +mem-write: 0x80007721 <- 0x1300c457 +mem-write: 0x80007725 <- 0x13ffc777 +mem-write: 0x80007729 <- 0x93001767 +mem-write: 0x8000772d <- 0x93010717 +mem-write: 0x80007731 <- 0x6f4107d7 +mem-write: 0x80007735 <- 0x13f89ff0 +mem-write: 0x80007739 <- 0x23fd0101 +mem-write: 0x8000773d <- 0x2301312e +mem-write: 0x80007741 <- 0x23021126 +mem-write: 0x80007745 <- 0x23028124 +mem-write: 0x80007749 <- 0x23029122 +mem-write: 0x8000774d <- 0x23032120 +mem-write: 0x80007751 <- 0x2301412c +mem-write: 0x80007755 <- 0x2301512a +mem-write: 0x80007759 <- 0x23016128 +mem-write: 0x8000775d <- 0x23017126 +mem-write: 0x80007761 <- 0x23018124 +mem-write: 0x80007765 <- 0x93019122 +mem-write: 0x80007769 <- 0x1300b587 +mem-write: 0x8000776d <- 0x93016007 +mem-write: 0x80007771 <- 0x63000509 +mem-write: 0x80007775 <- 0x9306f764 +mem-write: 0x80007779 <- 0x63010007 +mem-write: 0x8000777d <- 0xef1eb7e2 +mem-write: 0x80007781 <- 0x93025000 +mem-write: 0x80007785 <- 0x13010004 +mem-write: 0x80007789 <- 0x93002006 +mem-write: 0x8000778d <- 0x13018007 +mem-write: 0x80007791 <- 0xb3c30189 +mem-write: 0x80007795 <- 0x300f907 +mem-write: 0x80007799 <- 0x130047a4 +mem-write: 0x8000779d <- 0x63ff8787 +mem-write: 0x800077a1 <- 0x8320e408 +mem-write: 0x800077a5 <- 0x83004427 +mem-write: 0x800077a9 <- 0x300c426 +mem-write: 0x800077ad <- 0x93008426 +mem-write: 0x800077b1 <- 0xb3ffc7f7 +mem-write: 0x800077b5 <- 0x300f407 +mem-write: 0x800077b9 <- 0x230047a7 +mem-write: 0x800077bd <- 0x2300d626 +mem-write: 0x800077c1 <- 0x1300c6a4 +mem-write: 0x800077c5 <- 0x13001767 +mem-write: 0x800077c9 <- 0x23000985 +mem-write: 0x800077cd <- 0xef00e7a2 +mem-write: 0x800077d1 <- 0x137d8000 +mem-write: 0x800077d5 <- 0x6f008405 +mem-write: 0x800077d9 <- 0x93194000 +mem-write: 0x800077dd <- 0x63ff87f4 +mem-write: 0x800077e1 <- 0x631807c0 +mem-write: 0x800077e5 <- 0xef16b4ee +mem-write: 0x800077e9 <- 0x937bc000 +mem-write: 0x800077ed <- 0x631f7007 +mem-write: 0x800077f1 <- 0x934497fa +mem-write: 0x800077f5 <- 0x630094d7 +mem-write: 0x800077f9 <- 0x131a0784 +VXDRV: upload 1024 bytes to 0x800077fd +mem-write: 0x800077fd <- 0x63004007 +mem-write: 0x80007801 <- 0x933cf760 +mem-write: 0x80007805 <- 0x130064d7 +mem-write: 0x80007809 <- 0x13039786 +mem-write: 0x8000780d <- 0x93038785 +mem-write: 0x80007811 <- 0x13003616 +mem-write: 0x80007815 <- 0xb3c30189 +mem-write: 0x80007819 <- 0x300d906 +mem-write: 0x8000781d <- 0x930046a4 +mem-write: 0x80007821 <- 0x63ff8686 +mem-write: 0x80007825 <- 0x93028686 +mem-write: 0x80007829 <- 0x6f00f005 +mem-write: 0x8000782d <- 0x63010000 +mem-write: 0x80007831 <- 0x3320752 +mem-write: 0x80007835 <- 0x6300c424 +mem-write: 0x80007839 <- 0x8300868c +mem-write: 0x8000783d <- 0x93004427 +mem-write: 0x80007841 <- 0x33ffc7f7 +mem-write: 0x80007845 <- 0xe3409787 +mem-write: 0x80007849 <- 0x13fee5d4 +mem-write: 0x8000784d <- 0x3000506 +mem-write: 0x80007851 <- 0x93010924 +mem-write: 0x80007855 <- 0x63008908 +mem-write: 0x80007859 <- 0x3171408 +mem-write: 0x8000785d <- 0x93004425 +mem-write: 0x80007861 <- 0x1300f006 +mem-write: 0x80007865 <- 0xb3ffc575 +mem-write: 0x80007869 <- 0x63409507 +mem-write: 0x8000786d <- 0x2340f6c2 +mem-write: 0x80007871 <- 0x2301192a +mem-write: 0x80007875 <- 0x63011928 +mem-write: 0x80007879 <- 0x933c07dc +mem-write: 0x8000787d <- 0x631ff007 +mem-write: 0x80007881 <- 0x932ea7e0 +mem-write: 0x80007885 <- 0x93ff8577 +mem-write: 0x80007889 <- 0x83008787 +mem-write: 0x8000788d <- 0xb3004925 +mem-write: 0x80007891 <- 0x8300f907 +mem-write: 0x80007895 <- 0x130007a6 +mem-write: 0x80007899 <- 0x13005555 +mem-write: 0x8000789d <- 0x33001007 +mem-write: 0x800078a1 <- 0x3300a717 +mem-write: 0x800078a5 <- 0x9300b767 +mem-write: 0x800078a9 <- 0x23ff8785 +mem-write: 0x800078ad <- 0x2300b426 +mem-write: 0x800078b1 <- 0x2300d424 +mem-write: 0x800078b5 <- 0x2300e922 +mem-write: 0x800078b9 <- 0x230087a0 +mem-write: 0x800078bd <- 0x930086a6 +mem-write: 0x800078c1 <- 0x93402657 +mem-write: 0x800078c5 <- 0xb3001005 +mem-write: 0x800078c9 <- 0x6300f595 +mem-write: 0x800078cd <- 0xb310b768 +mem-write: 0x800078d1 <- 0x6300e5f7 +mem-write: 0x800078d5 <- 0x93020794 +mem-write: 0x800078d9 <- 0x13001595 +mem-write: 0x800078dd <- 0xb3ffc676 +mem-write: 0x800078e1 <- 0x1300e5f7 +mem-write: 0x800078e5 <- 0x63004606 +mem-write: 0x800078e9 <- 0x9300079a +mem-write: 0x800078ed <- 0xb3001595 +mem-write: 0x800078f1 <- 0x1300e5f7 +mem-write: 0x800078f5 <- 0xe3004606 +mem-write: 0x800078f9 <- 0x13fe078a +mem-write: 0x800078fd <- 0x1300f008 +mem-write: 0x80007901 <- 0x33003613 +mem-write: 0x80007905 <- 0x13006903 +mem-write: 0x80007909 <- 0x83000305 +mem-write: 0x8000790d <- 0x1300c527 +mem-write: 0x80007911 <- 0x6300060e +mem-write: 0x80007915 <- 0x32cf508 +mem-write: 0x80007919 <- 0x130047a7 +mem-write: 0x8000791d <- 0x83000784 +mem-write: 0x80007921 <- 0x1300c7a7 +mem-write: 0x80007925 <- 0xb3ffc777 +mem-write: 0x80007929 <- 0x63409706 +mem-write: 0x8000792d <- 0xe32cd848 +mem-write: 0x80007931 <- 0x33fe06c2 +mem-write: 0x80007935 <- 0x8300e407 +mem-write: 0x80007939 <- 0x3004726 +mem-write: 0x8000793d <- 0x13008426 +mem-write: 0x80007941 <- 0x93000985 +mem-write: 0x80007945 <- 0x230016e6 +mem-write: 0x80007949 <- 0x2300d722 +mem-write: 0x8000794d <- 0x2300f626 +mem-write: 0x80007951 <- 0xef00c7a4 +mem-write: 0x80007955 <- 0x13654000 +mem-write: 0x80007959 <- 0x6f008405 +mem-write: 0x8000795d <- 0x93010000 +mem-write: 0x80007961 <- 0x2300c007 +mem-write: 0x80007965 <- 0x1300f9a0 +mem-write: 0x80007969 <- 0x83000005 +mem-write: 0x8000796d <- 0x302c120 +mem-write: 0x80007971 <- 0x83028124 +mem-write: 0x80007975 <- 0x3024124 +mem-write: 0x80007979 <- 0x83020129 +mem-write: 0x8000797d <- 0x301c129 +mem-write: 0x80007981 <- 0x8301812a +mem-write: 0x80007985 <- 0x301412a +mem-write: 0x80007989 <- 0x8301012b +mem-write: 0x8000798d <- 0x300c12b +mem-write: 0x80007991 <- 0x8300812c +mem-write: 0x80007995 <- 0x1300412c +mem-write: 0x80007999 <- 0x67030101 +mem-write: 0x8000799d <- 0x93000080 +mem-write: 0x800079a1 <- 0x13200006 +mem-write: 0x800079a5 <- 0x13040006 +mem-write: 0x800079a9 <- 0x6f03f005 +mem-write: 0x800079ad <- 0x3e69ff0 +mem-write: 0x800079b1 <- 0x1300c7a4 +mem-write: 0x800079b5 <- 0xe3002606 +mem-write: 0x800079b9 <- 0x3de8796 +mem-write: 0x800079bd <- 0x93010924 +mem-write: 0x800079c1 <- 0xe3008908 +mem-write: 0x800079c5 <- 0x3e9141c +mem-write: 0x800079c9 <- 0x93004927 +mem-write: 0x800079cd <- 0x93402657 +mem-write: 0x800079d1 <- 0xb3001005 +mem-write: 0x800079d5 <- 0xe300f595 +mem-write: 0x800079d9 <- 0x3eeb77c +mem-write: 0x800079dd <- 0x83008924 +mem-write: 0x800079e1 <- 0x1300442a +mem-write: 0x800079e5 <- 0x63ffcafb +mem-write: 0x800079e9 <- 0xb3009b68 +mem-write: 0x800079ed <- 0x13409b07 +mem-write: 0x800079f1 <- 0x6300f007 +mem-write: 0x800079f5 <- 0x8312f74c +mem-write: 0x800079f9 <- 0x31f01aa +mem-write: 0x800079fd <- 0x931dc1a7 +mem-write: 0x80007a01 <- 0x33fff007 +mem-write: 0x80007a05 <- 0xb301640a +mem-write: 0x80007a09 <- 0x6301548a +mem-write: 0x80007a0d <- 0xb734f704 +mem-write: 0x80007a11 <- 0x93000017 +mem-write: 0x80007a15 <- 0xb300f787 +mem-write: 0x80007a19 <- 0xb700fa8a +mem-write: 0x80007a1d <- 0xb3fffff7 +mem-write: 0x80007a21 <- 0x9300fafa +mem-write: 0x80007a25 <- 0x13000a85 +mem-write: 0x80007a29 <- 0xef000985 +mem-write: 0x80007a2d <- 0x93774010 +mem-write: 0x80007a31 <- 0x93fff007 +mem-write: 0x80007a35 <- 0x6300050b +mem-write: 0x80007a39 <- 0x6328f506 +mem-write: 0x80007a3d <- 0x13294562 +mem-write: 0x80007a41 <- 0x831f818c +mem-write: 0x80007a45 <- 0xb3000c25 +mem-write: 0x80007a49 <- 0x2300ba85 +mem-write: 0x80007a4d <- 0x9300bc20 +mem-write: 0x80007a51 <- 0x63000587 +mem-write: 0x80007a55 <- 0x8338aa0e +mem-write: 0x80007a59 <- 0x131dc1a6 +mem-write: 0x80007a5d <- 0x63fff007 +mem-write: 0x80007a61 <- 0x333ae686 +mem-write: 0x80007a65 <- 0xb3414b8a +mem-write: 0x80007a69 <- 0x2300fa07 +mem-write: 0x80007a6d <- 0x9300fc20 +mem-write: 0x80007a71 <- 0x63007bfc +mem-write: 0x80007a75 <- 0xb7300c82 +mem-write: 0x80007a79 <- 0xb3000017 +mem-write: 0x80007a7d <- 0x93419b8b +mem-write: 0x80007a81 <- 0x93008785 +mem-write: 0x80007a85 <- 0xb3008b8b +mem-write: 0x80007a89 <- 0xb3419585 +mem-write: 0x80007a8d <- 0x93015b8a +mem-write: 0x80007a91 <- 0xb3fff787 +mem-write: 0x80007a95 <- 0x33415585 +mem-write: 0x80007a99 <- 0x9300f5fa +mem-write: 0x80007a9d <- 0x13000a05 +mem-write: 0x80007aa1 <- 0xef000985 +mem-write: 0x80007aa5 <- 0x936fc010 +mem-write: 0x80007aa9 <- 0x63fff007 +mem-write: 0x80007aad <- 0x333af50a +mem-write: 0x80007ab1 <- 0xb3417505 +mem-write: 0x80007ab5 <- 0x8301450a +mem-write: 0x80007ab9 <- 0x23000c25 +mem-write: 0x80007abd <- 0x93017924 +mem-write: 0x80007ac1 <- 0xb3001aea +mem-write: 0x80007ac5 <- 0x2300ba05 +mem-write: 0x80007ac9 <- 0x2300bc20 +mem-write: 0x80007acd <- 0x63015ba2 +mem-write: 0x80007ad1 <- 0x93352402 +mem-write: 0x80007ad5 <- 0x6300f006 +mem-write: 0x80007ad9 <- 0x33566f2 +mem-write: 0x80007add <- 0x93004427 +mem-write: 0x80007ae1 <- 0x93ff4b07 +mem-write: 0x80007ae5 <- 0x13ff87f7 +mem-write: 0x80007ae9 <- 0x33001777 +mem-write: 0x80007aed <- 0x2300f767 +mem-write: 0x80007af1 <- 0x1300e422 +mem-write: 0x80007af5 <- 0x33005006 +mem-write: 0x80007af9 <- 0x2300f407 +mem-write: 0x80007afd <- 0x2300c722 +mem-write: 0x80007b01 <- 0x6300c724 +mem-write: 0x80007b05 <- 0x8336f6e8 +mem-write: 0x80007b09 <- 0x13004baa +mem-write: 0x80007b0d <- 0x3000b84 +mem-write: 0x80007b11 <- 0x631ec1a7 +mem-write: 0x80007b15 <- 0x2300b774 +mem-write: 0x80007b19 <- 0x31eb1a6 +mem-write: 0x80007b1d <- 0x631e81a7 +mem-write: 0x80007b21 <- 0x231ab776 +mem-write: 0x80007b25 <- 0x6f1eb1a4 +mem-write: 0x80007b29 <- 0x131a4000 +mem-write: 0x80007b2d <- 0x230014e7 +mem-write: 0x80007b31 <- 0xb300e422 +mem-write: 0x80007b35 <- 0x23009404 +mem-write: 0x80007b39 <- 0x93009924 +mem-write: 0x80007b3d <- 0x130017e7 +mem-write: 0x80007b41 <- 0x23000985 +mem-write: 0x80007b45 <- 0xef00f4a2 +mem-write: 0x80007b49 <- 0x13460000 +mem-write: 0x80007b4d <- 0x6f008405 +mem-write: 0x80007b51 <- 0x83e1dff0 +mem-write: 0x80007b55 <- 0x300c426 +mem-write: 0x80007b59 <- 0x6f008426 +mem-write: 0x80007b5d <- 0x93c59ff0 +mem-write: 0x80007b61 <- 0x13009557 +mem-write: 0x80007b65 <- 0x63004007 +mem-write: 0x80007b69 <- 0x1314f772 +mem-write: 0x80007b6d <- 0x63014007 +mem-write: 0x80007b71 <- 0x9322f76a +mem-write: 0x80007b75 <- 0x9305c786 +mem-write: 0x80007b79 <- 0x9305b785 +mem-write: 0x80007b7d <- 0xb3003696 +mem-write: 0x80007b81 <- 0x8300d906 +mem-write: 0x80007b85 <- 0x930006a7 +mem-write: 0x80007b89 <- 0x63ff8686 +mem-write: 0x80007b8d <- 0x31cf688 +mem-write: 0x80007b91 <- 0x130047a7 +mem-write: 0x80007b95 <- 0x63ffc777 +mem-write: 0x80007b99 <- 0x8300e576 +mem-write: 0x80007b9d <- 0xe30087a7 +mem-write: 0x80007ba1 <- 0x83fef698 +mem-write: 0x80007ba5 <- 0x300c7a6 +mem-write: 0x80007ba9 <- 0x23004927 +mem-write: 0x80007bad <- 0x2300d426 +mem-write: 0x80007bb1 <- 0x2300f424 +mem-write: 0x80007bb5 <- 0x230086a4 +mem-write: 0x80007bb9 <- 0x6f0087a6 +mem-write: 0x80007bbd <- 0x13d05ff0 +mem-write: 0x80007bc1 <- 0x63014007 +mem-write: 0x80007bc5 <- 0x1312f776 +mem-write: 0x80007bc9 <- 0x63054007 +mem-write: 0x80007bcd <- 0x931ef76a +mem-write: 0x80007bd1 <- 0x1300c4d7 +mem-write: 0x80007bd5 <- 0x1306f786 +mem-write: 0x80007bd9 <- 0x9306e785 +mem-write: 0x80007bdd <- 0x6f003616 +mem-write: 0x80007be1 <- 0x13c35ff0 +mem-write: 0x80007be5 <- 0x93001e0e +mem-write: 0x80007be9 <- 0x13003e77 +mem-write: 0x80007bed <- 0x63008505 +mem-write: 0x80007bf1 <- 0x8310078e +mem-write: 0x80007bf5 <- 0x6f00c527 +mem-write: 0x80007bf9 <- 0x3d1dff0 +VXDRV: upload 1023 bytes to 0x80007bfd +mem-write: 0x80007bfd <- 0x93008426 +mem-write: 0x80007c01 <- 0x230014e5 +mem-write: 0x80007c05 <- 0x2300b422 +mem-write: 0x80007c09 <- 0x2300f626 +mem-write: 0x80007c0d <- 0xb300c7a4 +mem-write: 0x80007c11 <- 0x23009404 +mem-write: 0x80007c15 <- 0x2300992a +mem-write: 0x80007c19 <- 0x93009928 +mem-write: 0x80007c1d <- 0x230016e7 +mem-write: 0x80007c21 <- 0x230114a6 +mem-write: 0x80007c25 <- 0x230114a4 +mem-write: 0x80007c29 <- 0x3300f4a2 +mem-write: 0x80007c2d <- 0x1300e407 +mem-write: 0x80007c31 <- 0x23000985 +mem-write: 0x80007c35 <- 0xef00d720 +mem-write: 0x80007c39 <- 0x13370000 +mem-write: 0x80007c3d <- 0x6f008405 +mem-write: 0x80007c41 <- 0x13d2dff0 +mem-write: 0x80007c45 <- 0x930034d6 +mem-write: 0x80007c49 <- 0x6f008487 +mem-write: 0x80007c4d <- 0x33b45ff0 +mem-write: 0x80007c51 <- 0x8300a407 +mem-write: 0x80007c55 <- 0x13004727 +mem-write: 0x80007c59 <- 0x93000985 +mem-write: 0x80007c5d <- 0x230017e7 +mem-write: 0x80007c61 <- 0xef00f722 +mem-write: 0x80007c65 <- 0x13344000 +mem-write: 0x80007c69 <- 0x6f008405 +mem-write: 0x80007c6d <- 0x13d01ff0 +mem-write: 0x80007c71 <- 0x230014e7 +mem-write: 0x80007c75 <- 0xb300e422 +mem-write: 0x80007c79 <- 0x23009404 +mem-write: 0x80007c7d <- 0x2300992a +mem-write: 0x80007c81 <- 0x13009928 +mem-write: 0x80007c85 <- 0x230017e7 +mem-write: 0x80007c89 <- 0x230114a6 +mem-write: 0x80007c8d <- 0x230114a4 +mem-write: 0x80007c91 <- 0x3300e4a2 +mem-write: 0x80007c95 <- 0x2300a405 +mem-write: 0x80007c99 <- 0x1300f520 +mem-write: 0x80007c9d <- 0xef000985 +mem-write: 0x80007ca1 <- 0x13308000 +mem-write: 0x80007ca5 <- 0x6f008405 +mem-write: 0x80007ca9 <- 0x93cc5ff0 +mem-write: 0x80007cad <- 0x93006557 +mem-write: 0x80007cb1 <- 0x93039786 +mem-write: 0x80007cb5 <- 0x93038785 +mem-write: 0x80007cb9 <- 0x6f003696 +mem-write: 0x80007cbd <- 0x63ec5ff0 +mem-write: 0x80007cc1 <- 0x311240e +mem-write: 0x80007cc5 <- 0x83008924 +mem-write: 0x80007cc9 <- 0x9300442a +mem-write: 0x80007ccd <- 0xb3ffcafa +mem-write: 0x80007cd1 <- 0x63409a87 +mem-write: 0x80007cd5 <- 0x13009ae6 +mem-write: 0x80007cd9 <- 0xe300f007 +mem-write: 0x80007cdd <- 0x13e4f748 +mem-write: 0x80007ce1 <- 0xef000985 +mem-write: 0x80007ce5 <- 0x132c4000 +mem-write: 0x80007ce9 <- 0x6f000005 +mem-write: 0x80007ced <- 0x13c81ff0 +mem-write: 0x80007cf1 <- 0x1305c786 +mem-write: 0x80007cf5 <- 0x9305b785 +mem-write: 0x80007cf9 <- 0x6f003616 +mem-write: 0x80007cfd <- 0x83b19ff0 +mem-write: 0x80007d01 <- 0x13008327 +mem-write: 0x80007d05 <- 0x63fff606 +mem-write: 0x80007d09 <- 0x931c6790 +mem-write: 0x80007d0d <- 0x13003677 +mem-write: 0x80007d11 <- 0xe3ff8303 +mem-write: 0x80007d15 <- 0x3fe0796 +mem-write: 0x80007d19 <- 0x93004927 +mem-write: 0x80007d1d <- 0xb3fff5c7 +mem-write: 0x80007d21 <- 0x2300e7f7 +mem-write: 0x80007d25 <- 0x9300f922 +mem-write: 0x80007d29 <- 0xe3001595 +mem-write: 0x80007d2d <- 0xe3cab7e8 +mem-write: 0x80007d31 <- 0x33ca0586 +mem-write: 0x80007d35 <- 0x6300f5f7 +mem-write: 0x80007d39 <- 0x9300071a +mem-write: 0x80007d3d <- 0x33001595 +mem-write: 0x80007d41 <- 0x1300f5f7 +mem-write: 0x80007d45 <- 0xe3004e0e +mem-write: 0x80007d49 <- 0x13fe070a +mem-write: 0x80007d4d <- 0x6f000e06 +mem-write: 0x80007d51 <- 0x93bb1ff0 +mem-write: 0x80007d55 <- 0x6f010a8a +mem-write: 0x80007d59 <- 0x3ccdff0 +mem-write: 0x80007d5d <- 0x93004925 +mem-write: 0x80007d61 <- 0x134025d5 +mem-write: 0x80007d65 <- 0x33001007 +mem-write: 0x80007d69 <- 0x3300b717 +mem-write: 0x80007d6d <- 0x2300a767 +mem-write: 0x80007d71 <- 0x6f00e922 +mem-write: 0x80007d75 <- 0xb3e39ff0 +mem-write: 0x80007d79 <- 0xb3015b85 +mem-write: 0x80007d7d <- 0x9340b005 +mem-write: 0x80007d81 <- 0x13014595 +mem-write: 0x80007d85 <- 0x930145da +mem-write: 0x80007d89 <- 0x13000a05 +mem-write: 0x80007d8d <- 0xef000985 +mem-write: 0x80007d91 <- 0x93410010 +mem-write: 0x80007d95 <- 0xe3fff007 +mem-write: 0x80007d99 <- 0x13d0f51c +mem-write: 0x80007d9d <- 0x6f00000a +mem-write: 0x80007da1 <- 0x13d19ff0 +mem-write: 0x80007da5 <- 0x63054007 +mem-write: 0x80007da9 <- 0x9308f760 +mem-write: 0x80007dad <- 0x9300c557 +mem-write: 0x80007db1 <- 0x9306f786 +mem-write: 0x80007db5 <- 0x9306e785 +mem-write: 0x80007db9 <- 0x6f003696 +mem-write: 0x80007dbd <- 0x13dc5ff0 +mem-write: 0x80007dc1 <- 0x63154007 +mem-write: 0x80007dc5 <- 0x9308f760 +mem-write: 0x80007dc9 <- 0x1300f4d7 +mem-write: 0x80007dcd <- 0x13078786 +mem-write: 0x80007dd1 <- 0x93077785 +mem-write: 0x80007dd5 <- 0x6f003616 +mem-write: 0x80007dd9 <- 0x13a3dff0 +mem-write: 0x80007ddd <- 0x831f818c +mem-write: 0x80007de1 <- 0xb3000c27 +mem-write: 0x80007de5 <- 0x2300fa87 +mem-write: 0x80007de9 <- 0x6f00fc20 +mem-write: 0x80007ded <- 0x13c6dff0 +mem-write: 0x80007df1 <- 0xe3014a17 +mem-write: 0x80007df5 <- 0x3c60712 +mem-write: 0x80007df9 <- 0xb3008924 +mem-write: 0x80007dfd <- 0x93015b0a +mem-write: 0x80007e01 <- 0x23001aea +mem-write: 0x80007e05 <- 0x6f015422 +mem-write: 0x80007e09 <- 0x23d09ff0 +mem-write: 0x80007e0d <- 0x6f1d71ae +mem-write: 0x80007e11 <- 0x13c61ff0 +mem-write: 0x80007e15 <- 0x6f000b84 +mem-write: 0x80007e19 <- 0x93cf9ff0 +mem-write: 0x80007e1d <- 0x23001007 +mem-write: 0x80007e21 <- 0x6f00fba2 +mem-write: 0x80007e25 <- 0x13ebdff0 +mem-write: 0x80007e29 <- 0x63154007 +mem-write: 0x80007e2d <- 0x9306f762 +mem-write: 0x80007e31 <- 0x9300f557 +mem-write: 0x80007e35 <- 0x93078786 +mem-write: 0x80007e39 <- 0x93077785 +mem-write: 0x80007e3d <- 0x6f003696 +mem-write: 0x80007e41 <- 0x13d41ff0 +mem-write: 0x80007e45 <- 0x63554007 +mem-write: 0x80007e49 <- 0x9306f762 +mem-write: 0x80007e4d <- 0x130124d7 +mem-write: 0x80007e51 <- 0x1307d786 +mem-write: 0x80007e55 <- 0x9307c785 +mem-write: 0x80007e59 <- 0x6f003616 +mem-write: 0x80007e5d <- 0x939b9ff0 +mem-write: 0x80007e61 <- 0xb3ff8c8c +mem-write: 0x80007e65 <- 0xb3019a8a +mem-write: 0x80007e69 <- 0x13417a8a +mem-write: 0x80007e6d <- 0x6f00000a +mem-write: 0x80007e71 <- 0x93c49ff0 +mem-write: 0x80007e75 <- 0x13008405 +mem-write: 0x80007e79 <- 0xef000985 +mem-write: 0x80007e7d <- 0x3ee8fc0 +mem-write: 0x80007e81 <- 0x83008924 +mem-write: 0x80007e85 <- 0x83000c25 +mem-write: 0x80007e89 <- 0x6f00442a +mem-write: 0x80007e8d <- 0x13c85ff0 +mem-write: 0x80007e91 <- 0x63554007 +mem-write: 0x80007e95 <- 0x9302f764 +mem-write: 0x80007e99 <- 0x93012557 +mem-write: 0x80007e9d <- 0x9307d786 +mem-write: 0x80007ea1 <- 0x9307c785 +mem-write: 0x80007ea5 <- 0x6f003696 +mem-write: 0x80007ea9 <- 0x93cd9ff0 +mem-write: 0x80007ead <- 0x133f8006 +mem-write: 0x80007eb1 <- 0x1307f006 +mem-write: 0x80007eb5 <- 0x6f07e005 +mem-write: 0x80007eb9 <- 0x9395dff0 +mem-write: 0x80007ebd <- 0x933f8006 +mem-write: 0x80007ec1 <- 0x6f07e005 +mem-write: 0x80007ec5 <- 0x83cbdff0 +mem-write: 0x80007ec9 <- 0x6f004927 +mem-write: 0x80007ecd <- 0x93e5dff0 +mem-write: 0x80007ed1 <- 0x93003577 +mem-write: 0x80007ed5 <- 0x630ff5f6 +mem-write: 0x80007ed9 <- 0x9302078a +mem-write: 0x80007edd <- 0x63fff607 +mem-write: 0x80007ee1 <- 0x1302060e +mem-write: 0x80007ee5 <- 0x6ffff006 +mem-write: 0x80007ee9 <- 0x13018000 +mem-write: 0x80007eed <- 0x13001505 +mem-write: 0x80007ef1 <- 0x63003577 +mem-write: 0x80007ef5 <- 0x9300070e +mem-write: 0x80007ef9 <- 0x63fff787 +mem-write: 0x80007efd <- 0x302c780 +mem-write: 0x80007f01 <- 0xe3000547 +mem-write: 0x80007f05 <- 0x67fed714 +mem-write: 0x80007f09 <- 0x93000080 +mem-write: 0x80007f0d <- 0x13000607 +mem-write: 0x80007f11 <- 0x63003007 +mem-write: 0x80007f15 <- 0x6302f766 +mem-write: 0x80007f19 <- 0x13000796 +mem-write: 0x80007f1d <- 0x67000005 +mem-write: 0x80007f21 <- 0xb3000080 +mem-write: 0x80007f25 <- 0x6f00f507 +mem-write: 0x80007f29 <- 0x1300c000 +mem-write: 0x80007f2d <- 0xe3001505 +mem-write: 0x80007f31 <- 0x3fea786 +mem-write: 0x80007f35 <- 0xe3000547 +mem-write: 0x80007f39 <- 0x67fed71a +mem-write: 0x80007f3d <- 0x37000080 +mem-write: 0x80007f41 <- 0x93000107 +mem-write: 0x80007f45 <- 0x13008598 +mem-write: 0x80007f49 <- 0xb3fff707 +mem-write: 0x80007f4d <- 0x9300e8f8 +mem-write: 0x80007f51 <- 0xb30ff5f5 +mem-write: 0x80007f55 <- 0x9300b8e5 +mem-write: 0x80007f59 <- 0xb3010598 +mem-write: 0x80007f5d <- 0x3700b8e8 +mem-write: 0x80007f61 <- 0xb7feff08 +mem-write: 0x80007f65 <- 0x13808085 +mem-write: 0x80007f69 <- 0x93eff808 +mem-write: 0x80007f6d <- 0x13080585 +mem-write: 0x80007f71 <- 0x3003003 +mem-write: 0x80007f75 <- 0x33000527 +mem-write: 0x80007f79 <- 0x3300e8c7 +mem-write: 0x80007f7d <- 0x13010706 +mem-write: 0x80007f81 <- 0x33fff747 +mem-write: 0x80007f85 <- 0x3300e677 +mem-write: 0x80007f89 <- 0xe300b777 +mem-write: 0x80007f8d <- 0x93f8071c +mem-write: 0x80007f91 <- 0x13ffc787 +mem-write: 0x80007f95 <- 0xe3004505 +mem-write: 0x80007f99 <- 0xe3fcf36e +mem-write: 0x80007f9d <- 0x6ff80794 +mem-write: 0x80007fa1 <- 0x67f7dff0 +mem-write: 0x80007fa5 <- 0x67000080 +mem-write: 0x80007fa9 <- 0x83000080 +mem-write: 0x80007fad <- 0x1304c527 +mem-write: 0x80007fb1 <- 0x23ff0101 +mem-write: 0x80007fb5 <- 0x23008124 +mem-write: 0x80007fb9 <- 0x23009122 +mem-write: 0x80007fbd <- 0x23001126 +mem-write: 0x80007fc1 <- 0x13012120 +mem-write: 0x80007fc5 <- 0x93000504 +mem-write: 0x80007fc9 <- 0x63000584 +mem-write: 0x80007fcd <- 0x1302078e +mem-write: 0x80007fd1 <- 0xb3002495 +mem-write: 0x80007fd5 <- 0x300a787 +mem-write: 0x80007fd9 <- 0x630007a5 +mem-write: 0x80007fdd <- 0x3040506 +mem-write: 0x80007fe1 <- 0x23000527 +mem-write: 0x80007fe5 <- 0x2300e7a0 +mem-write: 0x80007fe9 <- 0x23000528 +mem-write: 0x80007fed <- 0x83000526 +mem-write: 0x80007ff1 <- 0x300c120 +mem-write: 0x80007ff5 <- 0x83008124 +mem-write: 0x80007ff9 <- 0x3004124 +VXDRV: upload 1024 bytes to 0x80007ffc +mem-write: 0x80007ffc <- 0x12903 +mem-write: 0x80008000 <- 0x1010113 +mem-write: 0x80008004 <- 0x8067 +mem-write: 0x80008008 <- 0x2100613 +mem-write: 0x8000800c <- 0x400593 +mem-write: 0x80008010 <- 0x518050ef +mem-write: 0x80008014 <- 0x4a42623 +mem-write: 0x80008018 <- 0x50793 +mem-write: 0x8000801c <- 0xfa051ae3 +mem-write: 0x80008020 <- 0x513 +mem-write: 0x80008024 <- 0xfcdff06f +mem-write: 0x80008028 <- 0x100913 +mem-write: 0x8000802c <- 0x991933 +mem-write: 0x80008030 <- 0x590613 +mem-write: 0x80008034 <- 0x261613 +mem-write: 0x80008038 <- 0x100593 +mem-write: 0x8000803c <- 0x40513 +mem-write: 0x80008040 <- 0x4e8050ef +mem-write: 0x80008044 <- 0xfc050ee3 +mem-write: 0x80008048 <- 0x952223 +mem-write: 0x8000804c <- 0x1252423 +mem-write: 0x80008050 <- 0xf99ff06f +mem-write: 0x80008054 <- 0x2058063 +mem-write: 0x80008058 <- 0x45a703 +mem-write: 0x8000805c <- 0x4c52783 +mem-write: 0x80008060 <- 0x271713 +mem-write: 0x80008064 <- 0xe787b3 +mem-write: 0x80008068 <- 0x7a703 +mem-write: 0x8000806c <- 0xe5a023 +mem-write: 0x80008070 <- 0xb7a023 +mem-write: 0x80008074 <- 0x8067 +mem-write: 0x80008078 <- 0xfe010113 +mem-write: 0x8000807c <- 0x912a23 +mem-write: 0x80008080 <- 0x105a483 +mem-write: 0x80008084 <- 0x10337 +mem-write: 0x80008088 <- 0x812c23 +mem-write: 0x8000808c <- 0x1212823 +mem-write: 0x80008090 <- 0x1312623 +mem-write: 0x80008094 <- 0x112e23 +mem-write: 0x80008098 <- 0x1412423 +mem-write: 0x8000809c <- 0x58913 +mem-write: 0x800080a0 <- 0x50993 +mem-write: 0x800080a4 <- 0x68413 +mem-write: 0x800080a8 <- 0x1458813 +mem-write: 0x800080ac <- 0x893 +mem-write: 0x800080b0 <- 0xfff30313 +mem-write: 0x800080b4 <- 0x82783 +mem-write: 0x800080b8 <- 0x480813 +mem-write: 0x800080bc <- 0x188893 +mem-write: 0x800080c0 <- 0x67f6b3 +mem-write: 0x800080c4 <- 0x2c686b3 +mem-write: 0x800080c8 <- 0x107d793 +mem-write: 0x800080cc <- 0x2c787b3 +mem-write: 0x800080d0 <- 0x8686b3 +mem-write: 0x800080d4 <- 0x106de13 +mem-write: 0x800080d8 <- 0x66f733 +mem-write: 0x800080dc <- 0x1c786b3 +mem-write: 0x800080e0 <- 0x1069793 +mem-write: 0x800080e4 <- 0xe78733 +mem-write: 0x800080e8 <- 0xfee82e23 +mem-write: 0x800080ec <- 0x106d413 +mem-write: 0x800080f0 <- 0xfc98c2e3 +mem-write: 0x800080f4 <- 0x2040263 +mem-write: 0x800080f8 <- 0x892783 +mem-write: 0x800080fc <- 0x4f4d063 +mem-write: 0x80008100 <- 0x448793 +mem-write: 0x80008104 <- 0x279793 +mem-write: 0x80008108 <- 0xf907b3 +mem-write: 0x8000810c <- 0x87a223 +mem-write: 0x80008110 <- 0x148493 +mem-write: 0x80008114 <- 0x992823 +mem-write: 0x80008118 <- 0x1c12083 +mem-write: 0x8000811c <- 0x1812403 +mem-write: 0x80008120 <- 0x1412483 +mem-write: 0x80008124 <- 0xc12983 +mem-write: 0x80008128 <- 0x812a03 +mem-write: 0x8000812c <- 0x90513 +mem-write: 0x80008130 <- 0x1012903 +mem-write: 0x80008134 <- 0x2010113 +mem-write: 0x80008138 <- 0x8067 +mem-write: 0x8000813c <- 0x492583 +mem-write: 0x80008140 <- 0x98513 +mem-write: 0x80008144 <- 0x158593 +mem-write: 0x80008148 <- 0xe65ff0ef +mem-write: 0x8000814c <- 0x50a13 +mem-write: 0x80008150 <- 0x4050c63 +mem-write: 0x80008154 <- 0x1092603 +mem-write: 0x80008158 <- 0xc90593 +mem-write: 0x8000815c <- 0xc50513 +mem-write: 0x80008160 <- 0x260613 +mem-write: 0x80008164 <- 0x261613 +mem-write: 0x80008168 <- 0x719050ef +mem-write: 0x8000816c <- 0x492703 +mem-write: 0x80008170 <- 0x4c9a783 +mem-write: 0x80008174 <- 0x271713 +mem-write: 0x80008178 <- 0xe787b3 +mem-write: 0x8000817c <- 0x7a703 +mem-write: 0x80008180 <- 0xe92023 +mem-write: 0x80008184 <- 0x127a023 +mem-write: 0x80008188 <- 0x448793 +mem-write: 0x8000818c <- 0xa0913 +mem-write: 0x80008190 <- 0x279793 +mem-write: 0x80008194 <- 0xf907b3 +mem-write: 0x80008198 <- 0x87a223 +mem-write: 0x8000819c <- 0x148493 +mem-write: 0x800081a0 <- 0x992823 +mem-write: 0x800081a4 <- 0xf75ff06f +mem-write: 0x800081a8 <- 0x800156b7 +mem-write: 0x800081ac <- 0x80015537 +mem-write: 0x800081b0 <- 0xe7468693 +mem-write: 0x800081b4 <- 0x613 +mem-write: 0x800081b8 <- 0xb500593 +mem-write: 0x800081bc <- 0xe8850513 +mem-write: 0x800081c0 <- 0x300050ef +mem-write: 0x800081c4 <- 0xfe010113 +mem-write: 0x800081c8 <- 0x812c23 +mem-write: 0x800081cc <- 0x912a23 +mem-write: 0x800081d0 <- 0x1212823 +mem-write: 0x800081d4 <- 0x1312623 +mem-write: 0x800081d8 <- 0x1412423 +mem-write: 0x800081dc <- 0x868813 +mem-write: 0x800081e0 <- 0x900793 +mem-write: 0x800081e4 <- 0x112e23 +mem-write: 0x800081e8 <- 0x1512223 +mem-write: 0x800081ec <- 0x2f84833 +mem-write: 0x800081f0 <- 0x68993 +mem-write: 0x800081f4 <- 0x50913 +mem-write: 0x800081f8 <- 0x58413 +mem-write: 0x800081fc <- 0x60a13 +mem-write: 0x80008200 <- 0x70493 +mem-write: 0x80008204 <- 0xcd7d863 +mem-write: 0x80008208 <- 0x100793 +mem-write: 0x8000820c <- 0x593 +mem-write: 0x80008210 <- 0x179793 +mem-write: 0x80008214 <- 0x158593 +mem-write: 0x80008218 <- 0xff07cce3 +mem-write: 0x8000821c <- 0x90513 +mem-write: 0x80008220 <- 0xd8dff0ef +mem-write: 0x80008224 <- 0x50593 +mem-write: 0x80008228 <- 0xa050a63 +mem-write: 0x8000822c <- 0x100793 +mem-write: 0x80008230 <- 0xf52823 +mem-write: 0x80008234 <- 0x952a23 +mem-write: 0x80008238 <- 0x900793 +mem-write: 0x8000823c <- 0x947d663 +mem-write: 0x80008240 <- 0x940a93 +mem-write: 0x80008244 <- 0xa8493 +mem-write: 0x80008248 <- 0x1440433 +mem-write: 0x8000824c <- 0x4c683 +mem-write: 0x80008250 <- 0xa00613 +mem-write: 0x80008254 <- 0x90513 +mem-write: 0x80008258 <- 0xfd068693 +mem-write: 0x8000825c <- 0xe1dff0ef +mem-write: 0x80008260 <- 0x148493 +mem-write: 0x80008264 <- 0x50593 +mem-write: 0x80008268 <- 0xfe8492e3 +mem-write: 0x8000826c <- 0xff8a0413 +mem-write: 0x80008270 <- 0x8a8433 +mem-write: 0x80008274 <- 0x33a5663 +mem-write: 0x80008278 <- 0x414989b3 +mem-write: 0x8000827c <- 0x13409b3 +mem-write: 0x80008280 <- 0x44683 +mem-write: 0x80008284 <- 0xa00613 +mem-write: 0x80008288 <- 0x90513 +mem-write: 0x8000828c <- 0xfd068693 +mem-write: 0x80008290 <- 0xde9ff0ef +mem-write: 0x80008294 <- 0x140413 +mem-write: 0x80008298 <- 0x50593 +mem-write: 0x8000829c <- 0xfe8992e3 +mem-write: 0x800082a0 <- 0x1c12083 +mem-write: 0x800082a4 <- 0x1812403 +mem-write: 0x800082a8 <- 0x1412483 +mem-write: 0x800082ac <- 0x1012903 +mem-write: 0x800082b0 <- 0xc12983 +mem-write: 0x800082b4 <- 0x812a03 +mem-write: 0x800082b8 <- 0x412a83 +mem-write: 0x800082bc <- 0x58513 +mem-write: 0x800082c0 <- 0x2010113 +mem-write: 0x800082c4 <- 0x8067 +mem-write: 0x800082c8 <- 0xa40413 +mem-write: 0x800082cc <- 0x900a13 +mem-write: 0x800082d0 <- 0xfa5ff06f +mem-write: 0x800082d4 <- 0x593 +mem-write: 0x800082d8 <- 0xf45ff06f +mem-write: 0x800082dc <- 0x800156b7 +mem-write: 0x800082e0 <- 0x80015537 +mem-write: 0x800082e4 <- 0xe7468693 +mem-write: 0x800082e8 <- 0x613 +mem-write: 0x800082ec <- 0xce00593 +mem-write: 0x800082f0 <- 0xe8850513 +mem-write: 0x800082f4 <- 0x1cc050ef +mem-write: 0x800082f8 <- 0xffff0737 +mem-write: 0x800082fc <- 0xe57733 +mem-write: 0x80008300 <- 0x50793 +mem-write: 0x80008304 <- 0x513 +mem-write: 0x80008308 <- 0x71663 +mem-write: 0x8000830c <- 0x1079793 +mem-write: 0x80008310 <- 0x1000513 +mem-write: 0x80008314 <- 0xff000737 +mem-write: 0x80008318 <- 0xe7f733 +mem-write: 0x8000831c <- 0x71663 +mem-write: 0x80008320 <- 0x850513 +mem-write: 0x80008324 <- 0x879793 +mem-write: 0x80008328 <- 0xf0000737 +mem-write: 0x8000832c <- 0xe7f733 +mem-write: 0x80008330 <- 0x71663 +mem-write: 0x80008334 <- 0x450513 +mem-write: 0x80008338 <- 0x479793 +mem-write: 0x8000833c <- 0xc0000737 +mem-write: 0x80008340 <- 0xe7f733 +mem-write: 0x80008344 <- 0x71663 +mem-write: 0x80008348 <- 0x250513 +mem-write: 0x8000834c <- 0x279793 +mem-write: 0x80008350 <- 0x7c863 +mem-write: 0x80008354 <- 0x179713 +mem-write: 0x80008358 <- 0x150513 +mem-write: 0x8000835c <- 0x75463 +mem-write: 0x80008360 <- 0x8067 +mem-write: 0x80008364 <- 0x2000513 +mem-write: 0x80008368 <- 0x8067 +mem-write: 0x8000836c <- 0x52783 +mem-write: 0x80008370 <- 0x50713 +mem-write: 0x80008374 <- 0x77f693 +mem-write: 0x80008378 <- 0x2068463 +mem-write: 0x8000837c <- 0x17f693 +mem-write: 0x80008380 <- 0x513 +mem-write: 0x80008384 <- 0x6069e63 +mem-write: 0x80008388 <- 0x27f693 +mem-write: 0x8000838c <- 0x8068063 +mem-write: 0x80008390 <- 0x17d793 +mem-write: 0x80008394 <- 0xf72023 +mem-write: 0x80008398 <- 0x100513 +mem-write: 0x8000839c <- 0x8067 +mem-write: 0x800083a0 <- 0x1079693 +mem-write: 0x800083a4 <- 0x106d693 +mem-write: 0x800083a8 <- 0x513 +mem-write: 0x800083ac <- 0x69663 +mem-write: 0x800083b0 <- 0x107d793 +mem-write: 0x800083b4 <- 0x1000513 +mem-write: 0x800083b8 <- 0xff7f693 +mem-write: 0x800083bc <- 0x69663 +mem-write: 0x800083c0 <- 0x850513 +mem-write: 0x800083c4 <- 0x87d793 +mem-write: 0x800083c8 <- 0xf7f693 +mem-write: 0x800083cc <- 0x69663 +mem-write: 0x800083d0 <- 0x450513 +mem-write: 0x800083d4 <- 0x47d793 +mem-write: 0x800083d8 <- 0x37f693 +mem-write: 0x800083dc <- 0x69663 +mem-write: 0x800083e0 <- 0x250513 +mem-write: 0x800083e4 <- 0x27d793 +mem-write: 0x800083e8 <- 0x17f693 +mem-write: 0x800083ec <- 0x69c63 +mem-write: 0x800083f0 <- 0x17d793 +mem-write: 0x800083f4 <- 0x150513 +mem-write: 0x800083f8 <- 0x79663 +VXDRV: upload 1024 bytes to 0x800083fc +mem-write: 0x800083fc <- 0x2000513 +mem-write: 0x80008400 <- 0x8067 +mem-write: 0x80008404 <- 0xf72023 +mem-write: 0x80008408 <- 0x8067 +mem-write: 0x8000840c <- 0x27d793 +mem-write: 0x80008410 <- 0xf72023 +mem-write: 0x80008414 <- 0x200513 +mem-write: 0x80008418 <- 0x8067 +mem-write: 0x8000841c <- 0xff010113 +mem-write: 0x80008420 <- 0x812423 +mem-write: 0x80008424 <- 0x58413 +mem-write: 0x80008428 <- 0x100593 +mem-write: 0x8000842c <- 0x112623 +mem-write: 0x80008430 <- 0xb7dff0ef +mem-write: 0x80008434 <- 0x2050063 +mem-write: 0x80008438 <- 0xc12083 +mem-write: 0x8000843c <- 0x852a23 +mem-write: 0x80008440 <- 0x812403 +mem-write: 0x80008444 <- 0x100713 +mem-write: 0x80008448 <- 0xe52823 +mem-write: 0x8000844c <- 0x1010113 +mem-write: 0x80008450 <- 0x8067 +mem-write: 0x80008454 <- 0x800156b7 +mem-write: 0x80008458 <- 0x80015537 +mem-write: 0x8000845c <- 0xe7468693 +mem-write: 0x80008460 <- 0x613 +mem-write: 0x80008464 <- 0x14000593 +mem-write: 0x80008468 <- 0xe8850513 +mem-write: 0x8000846c <- 0x54050ef +mem-write: 0x80008470 <- 0xfe010113 +mem-write: 0x80008474 <- 0x1212823 +mem-write: 0x80008478 <- 0x1312623 +mem-write: 0x8000847c <- 0x105a903 +mem-write: 0x80008480 <- 0x1062983 +mem-write: 0x80008484 <- 0x912a23 +mem-write: 0x80008488 <- 0x1412423 +mem-write: 0x8000848c <- 0x112e23 +mem-write: 0x80008490 <- 0x812c23 +mem-write: 0x80008494 <- 0x58a13 +mem-write: 0x80008498 <- 0x60493 +mem-write: 0x8000849c <- 0x1394c63 +mem-write: 0x800084a0 <- 0x98713 +mem-write: 0x800084a4 <- 0x58493 +mem-write: 0x800084a8 <- 0x90993 +mem-write: 0x800084ac <- 0x60a13 +mem-write: 0x800084b0 <- 0x70913 +mem-write: 0x800084b4 <- 0x84a783 +mem-write: 0x800084b8 <- 0x44a583 +mem-write: 0x800084bc <- 0x1298433 +mem-write: 0x800084c0 <- 0x87a7b3 +mem-write: 0x800084c4 <- 0xf585b3 +mem-write: 0x800084c8 <- 0xae5ff0ef +mem-write: 0x800084cc <- 0x1a050c63 +mem-write: 0x800084d0 <- 0x1450313 +mem-write: 0x800084d4 <- 0x241893 +mem-write: 0x800084d8 <- 0x11308b3 +mem-write: 0x800084dc <- 0x30793 +mem-write: 0x800084e0 <- 0x1137863 +mem-write: 0x800084e4 <- 0x7a023 +mem-write: 0x800084e8 <- 0x478793 +mem-write: 0x800084ec <- 0xff17ece3 +mem-write: 0x800084f0 <- 0x14a0813 +mem-write: 0x800084f4 <- 0x291e13 +mem-write: 0x800084f8 <- 0x1448e93 +mem-write: 0x800084fc <- 0x299593 +mem-write: 0x80008500 <- 0x1c80e33 +mem-write: 0x80008504 <- 0xbe85b3 +mem-write: 0x80008508 <- 0xbc87c63 +mem-write: 0x8000850c <- 0x1548793 +mem-write: 0x80008510 <- 0x400f13 +mem-write: 0x80008514 <- 0x14f5fe63 +mem-write: 0x80008518 <- 0x10637 +mem-write: 0x8000851c <- 0xfff60613 +mem-write: 0x80008520 <- 0x100006f +mem-write: 0x80008524 <- 0x480813 +mem-write: 0x80008528 <- 0x430313 +mem-write: 0x8000852c <- 0x9c87a63 +mem-write: 0x80008530 <- 0x82f83 +mem-write: 0x80008534 <- 0xcff4b3 +mem-write: 0x80008538 <- 0xc049463 +mem-write: 0x8000853c <- 0x10fdf93 +mem-write: 0x80008540 <- 0xfe0f82e3 +mem-write: 0x80008544 <- 0x32703 +mem-write: 0x80008548 <- 0x30293 +mem-write: 0x8000854c <- 0xe8693 +mem-write: 0x80008550 <- 0x70493 +mem-write: 0x80008554 <- 0x393 +mem-write: 0x80008558 <- 0x6a783 +mem-write: 0x8000855c <- 0x104d993 +mem-write: 0x80008560 <- 0xc77733 +mem-write: 0x80008564 <- 0xc7f7b3 +mem-write: 0x80008568 <- 0x3f787b3 +mem-write: 0x8000856c <- 0x42a483 +mem-write: 0x80008570 <- 0x428293 +mem-write: 0x80008574 <- 0x468693 +mem-write: 0x80008578 <- 0xc4f933 +mem-write: 0x8000857c <- 0x13787b3 +mem-write: 0x80008580 <- 0x7787b3 +mem-write: 0x80008584 <- 0x1079393 +mem-write: 0x80008588 <- 0xe3e733 +mem-write: 0x8000858c <- 0xfee2ae23 +mem-write: 0x80008590 <- 0xffe6d703 +mem-write: 0x80008594 <- 0x107d793 +mem-write: 0x80008598 <- 0x3f70733 +mem-write: 0x8000859c <- 0x1270733 +mem-write: 0x800085a0 <- 0xf70733 +mem-write: 0x800085a4 <- 0x1075393 +mem-write: 0x800085a8 <- 0xfab6e8e3 +mem-write: 0x800085ac <- 0x1e307b3 +mem-write: 0x800085b0 <- 0xe7a023 +mem-write: 0x800085b4 <- 0x480813 +mem-write: 0x800085b8 <- 0x430313 +mem-write: 0x800085bc <- 0xf7c86ae3 +mem-write: 0x800085c0 <- 0x804863 +mem-write: 0x800085c4 <- 0x180006f +mem-write: 0x800085c8 <- 0xfff40413 +mem-write: 0x800085cc <- 0x40863 +mem-write: 0x800085d0 <- 0xffc8a783 +mem-write: 0x800085d4 <- 0xffc88893 +mem-write: 0x800085d8 <- 0xfe0788e3 +mem-write: 0x800085dc <- 0x1c12083 +mem-write: 0x800085e0 <- 0x852823 +mem-write: 0x800085e4 <- 0x1812403 +mem-write: 0x800085e8 <- 0x1412483 +mem-write: 0x800085ec <- 0x1012903 +mem-write: 0x800085f0 <- 0xc12983 +mem-write: 0x800085f4 <- 0x812a03 +mem-write: 0x800085f8 <- 0x2010113 +mem-write: 0x800085fc <- 0x8067 +mem-write: 0x80008600 <- 0x30393 +mem-write: 0x80008604 <- 0xe8293 +mem-write: 0x80008608 <- 0x913 +mem-write: 0x8000860c <- 0x2a703 +mem-write: 0x80008610 <- 0x3af83 +mem-write: 0x80008614 <- 0x438393 +mem-write: 0x80008618 <- 0xc776b3 +mem-write: 0x8000861c <- 0x29686b3 +mem-write: 0x80008620 <- 0x1075793 +mem-write: 0x80008624 <- 0xcff733 +mem-write: 0x80008628 <- 0x10fdf93 +mem-write: 0x8000862c <- 0x428293 +mem-write: 0x80008630 <- 0x29787b3 +mem-write: 0x80008634 <- 0xe686b3 +mem-write: 0x80008638 <- 0x12686b3 +mem-write: 0x8000863c <- 0x106d713 +mem-write: 0x80008640 <- 0xc6f6b3 +mem-write: 0x80008644 <- 0x1f787b3 +mem-write: 0x80008648 <- 0xe787b3 +mem-write: 0x8000864c <- 0x1079713 +mem-write: 0x80008650 <- 0xd766b3 +mem-write: 0x80008654 <- 0xfed3ae23 +mem-write: 0x80008658 <- 0x107d913 +mem-write: 0x8000865c <- 0xfab2e8e3 +mem-write: 0x80008660 <- 0x1e307b3 +mem-write: 0x80008664 <- 0x127a023 +mem-write: 0x80008668 <- 0x82f83 +mem-write: 0x8000866c <- 0xed1ff06f +mem-write: 0x80008670 <- 0x40958f33 +mem-write: 0x80008674 <- 0xfebf0f13 +mem-write: 0x80008678 <- 0xffcf7f13 +mem-write: 0x8000867c <- 0x4f0f13 +mem-write: 0x80008680 <- 0xe99ff06f +mem-write: 0x80008684 <- 0x800156b7 +mem-write: 0x80008688 <- 0x80015537 +mem-write: 0x8000868c <- 0xe7468693 +mem-write: 0x80008690 <- 0x613 +mem-write: 0x80008694 <- 0x15d00593 +mem-write: 0x80008698 <- 0xe8850513 +mem-write: 0x8000869c <- 0x625040ef +mem-write: 0x800086a0 <- 0xfe010113 +mem-write: 0x800086a4 <- 0x812c23 +mem-write: 0x800086a8 <- 0x1312623 +mem-write: 0x800086ac <- 0x1412423 +mem-write: 0x800086b0 <- 0x112e23 +mem-write: 0x800086b4 <- 0x912a23 +mem-write: 0x800086b8 <- 0x1212823 +mem-write: 0x800086bc <- 0x367793 +mem-write: 0x800086c0 <- 0x60413 +mem-write: 0x800086c4 <- 0x50993 +mem-write: 0x800086c8 <- 0x58a13 +mem-write: 0x800086cc <- 0xc079463 +mem-write: 0x800086d0 <- 0x40245413 +mem-write: 0x800086d4 <- 0xa0913 +mem-write: 0x800086d8 <- 0x6040863 +mem-write: 0x800086dc <- 0x489a483 +mem-write: 0x800086e0 <- 0xc048e63 +mem-write: 0x800086e4 <- 0x147793 +mem-write: 0x800086e8 <- 0xa0913 +mem-write: 0x800086ec <- 0x2079063 +mem-write: 0x800086f0 <- 0x40145413 +mem-write: 0x800086f4 <- 0x4040a63 +mem-write: 0x800086f8 <- 0x4a503 +mem-write: 0x800086fc <- 0x6050863 +mem-write: 0x80008700 <- 0x50493 +mem-write: 0x80008704 <- 0x147793 +mem-write: 0x80008708 <- 0xfe0784e3 +mem-write: 0x8000870c <- 0x48613 +mem-write: 0x80008710 <- 0x90593 +mem-write: 0x80008714 <- 0x98513 +mem-write: 0x80008718 <- 0xd59ff0ef +mem-write: 0x8000871c <- 0x6090863 +mem-write: 0x80008720 <- 0x492703 +mem-write: 0x80008724 <- 0x4c9a783 +mem-write: 0x80008728 <- 0x40145413 +mem-write: 0x8000872c <- 0x271713 +mem-write: 0x80008730 <- 0xe787b3 +mem-write: 0x80008734 <- 0x7a703 +mem-write: 0x80008738 <- 0xe92023 +mem-write: 0x8000873c <- 0x127a023 +mem-write: 0x80008740 <- 0x50913 +mem-write: 0x80008744 <- 0xfa041ae3 +mem-write: 0x80008748 <- 0x1c12083 +mem-write: 0x8000874c <- 0x1812403 +mem-write: 0x80008750 <- 0x1412483 +mem-write: 0x80008754 <- 0xc12983 +mem-write: 0x80008758 <- 0x812a03 +mem-write: 0x8000875c <- 0x90513 +mem-write: 0x80008760 <- 0x1012903 +mem-write: 0x80008764 <- 0x2010113 +mem-write: 0x80008768 <- 0x8067 +mem-write: 0x8000876c <- 0x48613 +mem-write: 0x80008770 <- 0x48593 +mem-write: 0x80008774 <- 0x98513 +mem-write: 0x80008778 <- 0xcf9ff0ef +mem-write: 0x8000877c <- 0xa4a023 +mem-write: 0x80008780 <- 0x52023 +mem-write: 0x80008784 <- 0x50493 +mem-write: 0x80008788 <- 0xf7dff06f +mem-write: 0x8000878c <- 0x50913 +mem-write: 0x80008790 <- 0xf61ff06f +mem-write: 0x80008794 <- 0xfff78793 +mem-write: 0x80008798 <- 0x80015737 +mem-write: 0x8000879c <- 0xee070713 +mem-write: 0x800087a0 <- 0x279793 +mem-write: 0x800087a4 <- 0xf707b3 +mem-write: 0x800087a8 <- 0x7a603 +mem-write: 0x800087ac <- 0x693 +mem-write: 0x800087b0 <- 0x8c9ff0ef +mem-write: 0x800087b4 <- 0x50a13 +mem-write: 0x800087b8 <- 0xf19ff06f +mem-write: 0x800087bc <- 0x27100593 +mem-write: 0x800087c0 <- 0x98513 +mem-write: 0x800087c4 <- 0xc59ff0ef +mem-write: 0x800087c8 <- 0x4a9a423 +mem-write: 0x800087cc <- 0x50493 +mem-write: 0x800087d0 <- 0x52023 +mem-write: 0x800087d4 <- 0xf11ff06f +mem-write: 0x800087d8 <- 0xfe010113 +mem-write: 0x800087dc <- 0x1412423 +mem-write: 0x800087e0 <- 0x105aa03 +mem-write: 0x800087e4 <- 0x85a783 +mem-write: 0x800087e8 <- 0x1312623 +mem-write: 0x800087ec <- 0x40565993 +mem-write: 0x800087f0 <- 0x1498a33 +mem-write: 0x800087f4 <- 0x812c23 +mem-write: 0x800087f8 <- 0x912a23 +VXDRV: upload 1024 bytes to 0x800087fc +mem-write: 0x800087fc <- 0x1212823 +mem-write: 0x80008800 <- 0x1512223 +mem-write: 0x80008804 <- 0x112e23 +mem-write: 0x80008808 <- 0x1a0913 +mem-write: 0x8000880c <- 0x58493 +mem-write: 0x80008810 <- 0x60413 +mem-write: 0x80008814 <- 0x45a583 +mem-write: 0x80008818 <- 0x50a93 +mem-write: 0x8000881c <- 0x127d863 +mem-write: 0x80008820 <- 0x179793 +mem-write: 0x80008824 <- 0x158593 +mem-write: 0x80008828 <- 0xff27cce3 +mem-write: 0x8000882c <- 0xa8513 +mem-write: 0x80008830 <- 0xf7cff0ef +mem-write: 0x80008834 <- 0x10050c63 +mem-write: 0x80008838 <- 0x1450813 +mem-write: 0x8000883c <- 0x3305463 +mem-write: 0x80008840 <- 0x598993 +mem-write: 0x80008844 <- 0x299993 +mem-write: 0x80008848 <- 0x1350733 +mem-write: 0x8000884c <- 0x80793 +mem-write: 0x80008850 <- 0x478793 +mem-write: 0x80008854 <- 0xfe07ae23 +mem-write: 0x80008858 <- 0xfee79ce3 +mem-write: 0x8000885c <- 0xfec98993 +mem-write: 0x80008860 <- 0x1380833 +mem-write: 0x80008864 <- 0x104a703 +mem-write: 0x80008868 <- 0x1448793 +mem-write: 0x8000886c <- 0x1f47313 +mem-write: 0x80008870 <- 0x271613 +mem-write: 0x80008874 <- 0xc78633 +mem-write: 0x80008878 <- 0xa030463 +mem-write: 0x8000887c <- 0x2000593 +mem-write: 0x80008880 <- 0x406585b3 +mem-write: 0x80008884 <- 0x80893 +mem-write: 0x80008888 <- 0x693 +mem-write: 0x8000888c <- 0x7a703 +mem-write: 0x80008890 <- 0x488893 +mem-write: 0x80008894 <- 0x478793 +mem-write: 0x80008898 <- 0x671733 +mem-write: 0x8000889c <- 0xd76733 +mem-write: 0x800088a0 <- 0xfee8ae23 +mem-write: 0x800088a4 <- 0xffc7a703 +mem-write: 0x800088a8 <- 0xb756b3 +mem-write: 0x800088ac <- 0xfec7e0e3 +mem-write: 0x800088b0 <- 0x1548713 +mem-write: 0x800088b4 <- 0x400793 +mem-write: 0x800088b8 <- 0xe66a63 +mem-write: 0x800088bc <- 0x409607b3 +mem-write: 0x800088c0 <- 0xfeb78793 +mem-write: 0x800088c4 <- 0xffc7f793 +mem-write: 0x800088c8 <- 0x478793 +mem-write: 0x800088cc <- 0xf80833 +mem-write: 0x800088d0 <- 0xd82023 +mem-write: 0x800088d4 <- 0x68463 +mem-write: 0x800088d8 <- 0x90a13 +mem-write: 0x800088dc <- 0x44a703 +mem-write: 0x800088e0 <- 0x4caa783 +mem-write: 0x800088e4 <- 0x1c12083 +mem-write: 0x800088e8 <- 0x271713 +mem-write: 0x800088ec <- 0xe787b3 +mem-write: 0x800088f0 <- 0x7a703 +mem-write: 0x800088f4 <- 0x1452823 +mem-write: 0x800088f8 <- 0x1812403 +mem-write: 0x800088fc <- 0xe4a023 +mem-write: 0x80008900 <- 0x97a023 +mem-write: 0x80008904 <- 0x1012903 +mem-write: 0x80008908 <- 0x1412483 +mem-write: 0x8000890c <- 0xc12983 +mem-write: 0x80008910 <- 0x812a03 +mem-write: 0x80008914 <- 0x412a83 +mem-write: 0x80008918 <- 0x2010113 +mem-write: 0x8000891c <- 0x8067 +mem-write: 0x80008920 <- 0x7a703 +mem-write: 0x80008924 <- 0x478793 +mem-write: 0x80008928 <- 0x480813 +mem-write: 0x8000892c <- 0xfee82e23 +mem-write: 0x80008930 <- 0xfac7f6e3 +mem-write: 0x80008934 <- 0x7a703 +mem-write: 0x80008938 <- 0x478793 +mem-write: 0x8000893c <- 0x480813 +mem-write: 0x80008940 <- 0xfee82e23 +mem-write: 0x80008944 <- 0xfcc7eee3 +mem-write: 0x80008948 <- 0xf95ff06f +mem-write: 0x8000894c <- 0x800156b7 +mem-write: 0x80008950 <- 0x80015537 +mem-write: 0x80008954 <- 0xe7468693 +mem-write: 0x80008958 <- 0x613 +mem-write: 0x8000895c <- 0x1d900593 +mem-write: 0x80008960 <- 0xe8850513 +mem-write: 0x80008964 <- 0x35d040ef +mem-write: 0x80008968 <- 0x1052703 +mem-write: 0x8000896c <- 0x105a783 +mem-write: 0x80008970 <- 0x50813 +mem-write: 0x80008974 <- 0x40f70533 +mem-write: 0x80008978 <- 0x4f71463 +mem-write: 0x8000897c <- 0x279793 +mem-write: 0x80008980 <- 0x1480813 +mem-write: 0x80008984 <- 0x1458593 +mem-write: 0x80008988 <- 0xf80733 +mem-write: 0x8000898c <- 0xf587b3 +mem-write: 0x80008990 <- 0x80006f +mem-write: 0x80008994 <- 0x2e87663 +mem-write: 0x80008998 <- 0xffc72683 +mem-write: 0x8000899c <- 0xffc7a603 +mem-write: 0x800089a0 <- 0xffc70713 +mem-write: 0x800089a4 <- 0xffc78793 +mem-write: 0x800089a8 <- 0xfec686e3 +mem-write: 0x800089ac <- 0xc6b6b3 +mem-write: 0x800089b0 <- 0x40d00533 +mem-write: 0x800089b4 <- 0xffe57513 +mem-write: 0x800089b8 <- 0x150513 +mem-write: 0x800089bc <- 0x8067 +mem-write: 0x800089c0 <- 0x8067 +mem-write: 0x800089c4 <- 0x105a783 +mem-write: 0x800089c8 <- 0x1062703 +mem-write: 0x800089cc <- 0xff010113 +mem-write: 0x800089d0 <- 0x812423 +mem-write: 0x800089d4 <- 0x912223 +mem-write: 0x800089d8 <- 0x1212023 +mem-write: 0x800089dc <- 0x112623 +mem-write: 0x800089e0 <- 0x58493 +mem-write: 0x800089e4 <- 0x60413 +mem-write: 0x800089e8 <- 0x40e78933 +mem-write: 0x800089ec <- 0x1ae79463 +mem-write: 0x800089f0 <- 0x271693 +mem-write: 0x800089f4 <- 0x1458593 +mem-write: 0x800089f8 <- 0x1460713 +mem-write: 0x800089fc <- 0xd587b3 +mem-write: 0x80008a00 <- 0xd70733 +mem-write: 0x80008a04 <- 0x80006f +mem-write: 0x80008a08 <- 0x18f5fc63 +mem-write: 0x80008a0c <- 0xffc7a603 +mem-write: 0x80008a10 <- 0xffc72683 +mem-write: 0x80008a14 <- 0xffc78793 +mem-write: 0x80008a18 <- 0xffc70713 +mem-write: 0x80008a1c <- 0xfed606e3 +mem-write: 0x80008a20 <- 0x16d66063 +mem-write: 0x80008a24 <- 0x44a583 +mem-write: 0x80008a28 <- 0xd84ff0ef +mem-write: 0x80008a2c <- 0x1a050263 +mem-write: 0x80008a30 <- 0x104ae03 +mem-write: 0x80008a34 <- 0x1042283 +mem-write: 0x80008a38 <- 0x1448f93 +mem-write: 0x80008a3c <- 0x2e1e93 +mem-write: 0x80008a40 <- 0x1440813 +mem-write: 0x80008a44 <- 0x229293 +mem-write: 0x80008a48 <- 0x1450393 +mem-write: 0x80008a4c <- 0x108b7 +mem-write: 0x80008a50 <- 0x1252623 +mem-write: 0x80008a54 <- 0x1df8eb3 +mem-write: 0x80008a58 <- 0x5802b3 +mem-write: 0x80008a5c <- 0x38f13 +mem-write: 0x80008a60 <- 0xf8313 +mem-write: 0x80008a64 <- 0x793 +mem-write: 0x80008a68 <- 0xfff88893 +mem-write: 0x80008a6c <- 0x32703 +mem-write: 0x80008a70 <- 0x82583 +mem-write: 0x80008a74 <- 0x4f0f13 +mem-write: 0x80008a78 <- 0x11776b3 +mem-write: 0x80008a7c <- 0xf686b3 +mem-write: 0x80008a80 <- 0x115f7b3 +mem-write: 0x80008a84 <- 0x40f686b3 +mem-write: 0x80008a88 <- 0x105d593 +mem-write: 0x80008a8c <- 0x1075793 +mem-write: 0x80008a90 <- 0x40b787b3 +mem-write: 0x80008a94 <- 0x4106d713 +mem-write: 0x80008a98 <- 0xe787b3 +mem-write: 0x80008a9c <- 0x1079713 +mem-write: 0x80008aa0 <- 0x116f6b3 +mem-write: 0x80008aa4 <- 0xd766b3 +mem-write: 0x80008aa8 <- 0x480813 +mem-write: 0x80008aac <- 0xfedf2e23 +mem-write: 0x80008ab0 <- 0x430313 +mem-write: 0x80008ab4 <- 0x4107d793 +mem-write: 0x80008ab8 <- 0xfa586ae3 +mem-write: 0x80008abc <- 0x408285b3 +mem-write: 0x80008ac0 <- 0xfeb58593 +mem-write: 0x80008ac4 <- 0x1540413 +mem-write: 0x80008ac8 <- 0x25d593 +mem-write: 0x80008acc <- 0x713 +mem-write: 0x80008ad0 <- 0x82e463 +mem-write: 0x80008ad4 <- 0x259713 +mem-write: 0x80008ad8 <- 0xe38733 +mem-write: 0x80008adc <- 0x400813 +mem-write: 0x80008ae0 <- 0x82e663 +mem-write: 0x80008ae4 <- 0x158593 +mem-write: 0x80008ae8 <- 0x259813 +mem-write: 0x80008aec <- 0x10f8fb3 +mem-write: 0x80008af0 <- 0x10383b3 +mem-write: 0x80008af4 <- 0x5dffe63 +mem-write: 0x80008af8 <- 0x108b7 +mem-write: 0x80008afc <- 0x38813 +mem-write: 0x80008b00 <- 0xf8593 +mem-write: 0x80008b04 <- 0xfff88893 +mem-write: 0x80008b08 <- 0x5a703 +mem-write: 0x80008b0c <- 0x480813 +mem-write: 0x80008b10 <- 0x458593 +mem-write: 0x80008b14 <- 0x1177633 +mem-write: 0x80008b18 <- 0xf60633 +mem-write: 0x80008b1c <- 0x41065693 +mem-write: 0x80008b20 <- 0x1075793 +mem-write: 0x80008b24 <- 0xd787b3 +mem-write: 0x80008b28 <- 0x1079693 +mem-write: 0x80008b2c <- 0x1167633 +mem-write: 0x80008b30 <- 0xc6e6b3 +mem-write: 0x80008b34 <- 0xfed82e23 +mem-write: 0x80008b38 <- 0x4107d793 +mem-write: 0x80008b3c <- 0xfdd5e6e3 +mem-write: 0x80008b40 <- 0xfffe8713 +mem-write: 0x80008b44 <- 0x41f70fb3 +mem-write: 0x80008b48 <- 0xffcff713 +mem-write: 0x80008b4c <- 0xe38733 +mem-write: 0x80008b50 <- 0x69a63 +mem-write: 0x80008b54 <- 0xffc72783 +mem-write: 0x80008b58 <- 0xfffe0e13 +mem-write: 0x80008b5c <- 0xffc70713 +mem-write: 0x80008b60 <- 0xfe078ae3 +mem-write: 0x80008b64 <- 0xc12083 +mem-write: 0x80008b68 <- 0x812403 +mem-write: 0x80008b6c <- 0x1c52823 +mem-write: 0x80008b70 <- 0x412483 +mem-write: 0x80008b74 <- 0x12903 +mem-write: 0x80008b78 <- 0x1010113 +mem-write: 0x80008b7c <- 0x8067 +mem-write: 0x80008b80 <- 0x48793 +mem-write: 0x80008b84 <- 0x100913 +mem-write: 0x80008b88 <- 0x40493 +mem-write: 0x80008b8c <- 0x78413 +mem-write: 0x80008b90 <- 0xe95ff06f +mem-write: 0x80008b94 <- 0xfe0946e3 +mem-write: 0x80008b98 <- 0x913 +mem-write: 0x80008b9c <- 0xe89ff06f +mem-write: 0x80008ba0 <- 0x593 +mem-write: 0x80008ba4 <- 0xc08ff0ef +mem-write: 0x80008ba8 <- 0x4050263 +mem-write: 0x80008bac <- 0xc12083 +mem-write: 0x80008bb0 <- 0x812403 +mem-write: 0x80008bb4 <- 0x100793 +mem-write: 0x80008bb8 <- 0xf52823 +mem-write: 0x80008bbc <- 0x52a23 +mem-write: 0x80008bc0 <- 0x412483 +mem-write: 0x80008bc4 <- 0x12903 +mem-write: 0x80008bc8 <- 0x1010113 +mem-write: 0x80008bcc <- 0x8067 +mem-write: 0x80008bd0 <- 0x800156b7 +mem-write: 0x80008bd4 <- 0x80015537 +mem-write: 0x80008bd8 <- 0xe7468693 +mem-write: 0x80008bdc <- 0x613 +mem-write: 0x80008be0 <- 0x24000593 +mem-write: 0x80008be4 <- 0xe8850513 +mem-write: 0x80008be8 <- 0xd9040ef +mem-write: 0x80008bec <- 0x800156b7 +mem-write: 0x80008bf0 <- 0x80015537 +mem-write: 0x80008bf4 <- 0xe7468693 +mem-write: 0x80008bf8 <- 0x613 +VXDRV: upload 1024 bytes to 0x80008bfc +mem-write: 0x80008bfc <- 0x23200593 +mem-write: 0x80008c00 <- 0xe8850513 +mem-write: 0x80008c04 <- 0xbd040ef +mem-write: 0x80008c08 <- 0x7ff007b7 +mem-write: 0x80008c0c <- 0xb7f5b3 +mem-write: 0x80008c10 <- 0xfcc007b7 +mem-write: 0x80008c14 <- 0xf585b3 +mem-write: 0x80008c18 <- 0xb05863 +mem-write: 0x80008c1c <- 0x793 +mem-write: 0x80008c20 <- 0x78513 +mem-write: 0x80008c24 <- 0x8067 +mem-write: 0x80008c28 <- 0x40b005b3 +mem-write: 0x80008c2c <- 0x4145d593 +mem-write: 0x80008c30 <- 0x1300793 +mem-write: 0x80008c34 <- 0xb7c863 +mem-write: 0x80008c38 <- 0x807b7 +mem-write: 0x80008c3c <- 0x40b7d5b3 +mem-write: 0x80008c40 <- 0xfddff06f +mem-write: 0x80008c44 <- 0xfec58713 +mem-write: 0x80008c48 <- 0x1e00693 +mem-write: 0x80008c4c <- 0x593 +mem-write: 0x80008c50 <- 0x100793 +mem-write: 0x80008c54 <- 0xfce6c6e3 +mem-write: 0x80008c58 <- 0x800007b7 +mem-write: 0x80008c5c <- 0xe7d7b3 +mem-write: 0x80008c60 <- 0x78513 +mem-write: 0x80008c64 <- 0x8067 +mem-write: 0x80008c68 <- 0xfe010113 +mem-write: 0x80008c6c <- 0x912a23 +mem-write: 0x80008c70 <- 0x1052483 +mem-write: 0x80008c74 <- 0x812c23 +mem-write: 0x80008c78 <- 0x1450413 +mem-write: 0x80008c7c <- 0x249493 +mem-write: 0x80008c80 <- 0x9404b3 +mem-write: 0x80008c84 <- 0x1212823 +mem-write: 0x80008c88 <- 0xffc4a903 +mem-write: 0x80008c8c <- 0x1312623 +mem-write: 0x80008c90 <- 0x1412423 +mem-write: 0x80008c94 <- 0x90513 +mem-write: 0x80008c98 <- 0x58993 +mem-write: 0x80008c9c <- 0x112e23 +mem-write: 0x80008ca0 <- 0xe58ff0ef +mem-write: 0x80008ca4 <- 0x2000713 +mem-write: 0x80008ca8 <- 0x40a707b3 +mem-write: 0x80008cac <- 0xf9a023 +mem-write: 0x80008cb0 <- 0xa00793 +mem-write: 0x80008cb4 <- 0xffc48a13 +mem-write: 0x80008cb8 <- 0x8a7d063 +mem-write: 0x80008cbc <- 0xff550513 +mem-write: 0x80008cc0 <- 0x5447063 +mem-write: 0x80008cc4 <- 0xff84a783 +mem-write: 0x80008cc8 <- 0x4050063 +mem-write: 0x80008ccc <- 0x40a706b3 +mem-write: 0x80008cd0 <- 0xd7d733 +mem-write: 0x80008cd4 <- 0xa91933 +mem-write: 0x80008cd8 <- 0xe96933 +mem-write: 0x80008cdc <- 0xff848613 +mem-write: 0x80008ce0 <- 0x3ff00737 +mem-write: 0x80008ce4 <- 0xe96733 +mem-write: 0x80008ce8 <- 0xa797b3 +mem-write: 0x80008cec <- 0x2c47263 +mem-write: 0x80008cf0 <- 0xff44a603 +mem-write: 0x80008cf4 <- 0xd656b3 +mem-write: 0x80008cf8 <- 0xd7e7b3 +mem-write: 0x80008cfc <- 0x140006f +mem-write: 0x80008d00 <- 0x793 +mem-write: 0x80008d04 <- 0x6051463 +mem-write: 0x80008d08 <- 0x3ff00737 +mem-write: 0x80008d0c <- 0xe96733 +mem-write: 0x80008d10 <- 0x1c12083 +mem-write: 0x80008d14 <- 0x1812403 +mem-write: 0x80008d18 <- 0x1412483 +mem-write: 0x80008d1c <- 0x1012903 +mem-write: 0x80008d20 <- 0xc12983 +mem-write: 0x80008d24 <- 0x812a03 +mem-write: 0x80008d28 <- 0x78513 +mem-write: 0x80008d2c <- 0x70593 +mem-write: 0x80008d30 <- 0x2010113 +mem-write: 0x80008d34 <- 0x8067 +mem-write: 0x80008d38 <- 0xb00693 +mem-write: 0x80008d3c <- 0x40a686b3 +mem-write: 0x80008d40 <- 0x3ff007b7 +mem-write: 0x80008d44 <- 0xd95733 +mem-write: 0x80008d48 <- 0xf76733 +mem-write: 0x80008d4c <- 0x793 +mem-write: 0x80008d50 <- 0x1447663 +mem-write: 0x80008d54 <- 0xff84a783 +mem-write: 0x80008d58 <- 0xd7d7b3 +mem-write: 0x80008d5c <- 0x1550513 +mem-write: 0x80008d60 <- 0xa91533 +mem-write: 0x80008d64 <- 0xf567b3 +mem-write: 0x80008d68 <- 0xfa9ff06f +mem-write: 0x80008d6c <- 0xa91533 +mem-write: 0x80008d70 <- 0x3ff00737 +mem-write: 0x80008d74 <- 0xe56733 +mem-write: 0x80008d78 <- 0x793 +mem-write: 0x80008d7c <- 0xf95ff06f +mem-write: 0x80008d80 <- 0xfd010113 +mem-write: 0x80008d84 <- 0x1412c23 +mem-write: 0x80008d88 <- 0x58a13 +mem-write: 0x80008d8c <- 0x100593 +mem-write: 0x80008d90 <- 0x2912223 +mem-write: 0x80008d94 <- 0x3212023 +mem-write: 0x80008d98 <- 0x1312e23 +mem-write: 0x80008d9c <- 0x2112623 +mem-write: 0x80008da0 <- 0x2812423 +mem-write: 0x80008da4 <- 0x1512a23 +mem-write: 0x80008da8 <- 0x60493 +mem-write: 0x80008dac <- 0x68993 +mem-write: 0x80008db0 <- 0x70913 +mem-write: 0x80008db4 <- 0x9f8ff0ef +mem-write: 0x80008db8 <- 0x10050a63 +mem-write: 0x80008dbc <- 0x144d793 +mem-write: 0x80008dc0 <- 0x100737 +mem-write: 0x80008dc4 <- 0xfff70613 +mem-write: 0x80008dc8 <- 0x1579693 +mem-write: 0x80008dcc <- 0x50413 +mem-write: 0x80008dd0 <- 0x967633 +mem-write: 0x80008dd4 <- 0x7ff7fa93 +mem-write: 0x80008dd8 <- 0x68463 +mem-write: 0x80008ddc <- 0xe66633 +mem-write: 0x80008de0 <- 0xc12623 +mem-write: 0x80008de4 <- 0x80a0863 +mem-write: 0x80008de8 <- 0x810513 +mem-write: 0x80008dec <- 0x1412423 +mem-write: 0x80008df0 <- 0xd7cff0ef +mem-write: 0x80008df4 <- 0xc12703 +mem-write: 0x80008df8 <- 0x50793 +mem-write: 0x80008dfc <- 0xc050263 +mem-write: 0x80008e00 <- 0x812603 +mem-write: 0x80008e04 <- 0x2000693 +mem-write: 0x80008e08 <- 0x40a686b3 +mem-write: 0x80008e0c <- 0xd716b3 +mem-write: 0x80008e10 <- 0xc6e6b3 +mem-write: 0x80008e14 <- 0xa75733 +mem-write: 0x80008e18 <- 0xd42a23 +mem-write: 0x80008e1c <- 0xe12623 +mem-write: 0x80008e20 <- 0xe034b3 +mem-write: 0x80008e24 <- 0x148493 +mem-write: 0x80008e28 <- 0xe42c23 +mem-write: 0x80008e2c <- 0x942823 +mem-write: 0x80008e30 <- 0x60a8463 +mem-write: 0x80008e34 <- 0xbcda8a93 +mem-write: 0x80008e38 <- 0xfa8ab3 +mem-write: 0x80008e3c <- 0x3500513 +mem-write: 0x80008e40 <- 0x159a023 +mem-write: 0x80008e44 <- 0x40f507b3 +mem-write: 0x80008e48 <- 0xf92023 +mem-write: 0x80008e4c <- 0x2c12083 +mem-write: 0x80008e50 <- 0x40513 +mem-write: 0x80008e54 <- 0x2812403 +mem-write: 0x80008e58 <- 0x2412483 +mem-write: 0x80008e5c <- 0x2012903 +mem-write: 0x80008e60 <- 0x1c12983 +mem-write: 0x80008e64 <- 0x1812a03 +mem-write: 0x80008e68 <- 0x1412a83 +mem-write: 0x80008e6c <- 0x3010113 +mem-write: 0x80008e70 <- 0x8067 +mem-write: 0x80008e74 <- 0xc10513 +mem-write: 0x80008e78 <- 0xcf4ff0ef +mem-write: 0x80008e7c <- 0x100793 +mem-write: 0x80008e80 <- 0xf42823 +mem-write: 0x80008e84 <- 0xc12783 +mem-write: 0x80008e88 <- 0x100493 +mem-write: 0x80008e8c <- 0xf42a23 +mem-write: 0x80008e90 <- 0x2050793 +mem-write: 0x80008e94 <- 0xfa0a90e3 +mem-write: 0x80008e98 <- 0x249713 +mem-write: 0x80008e9c <- 0xe40733 +mem-write: 0x80008ea0 <- 0x1072503 +mem-write: 0x80008ea4 <- 0xbce78793 +mem-write: 0x80008ea8 <- 0xf9a023 +mem-write: 0x80008eac <- 0xc4cff0ef +mem-write: 0x80008eb0 <- 0x549493 +mem-write: 0x80008eb4 <- 0x40a484b3 +mem-write: 0x80008eb8 <- 0x992023 +mem-write: 0x80008ebc <- 0xf91ff06f +mem-write: 0x80008ec0 <- 0x812683 +mem-write: 0x80008ec4 <- 0xd42a23 +mem-write: 0x80008ec8 <- 0xf59ff06f +mem-write: 0x80008ecc <- 0x800156b7 +mem-write: 0x80008ed0 <- 0x80015537 +mem-write: 0x80008ed4 <- 0xe7468693 +mem-write: 0x80008ed8 <- 0x613 +mem-write: 0x80008edc <- 0x30a00593 +mem-write: 0x80008ee0 <- 0xe8850513 +mem-write: 0x80008ee4 <- 0x5dc040ef +mem-write: 0x80008ee8 <- 0xfd010113 +mem-write: 0x80008eec <- 0x3212023 +mem-write: 0x80008ef0 <- 0x58913 +mem-write: 0x80008ef4 <- 0x810593 +mem-write: 0x80008ef8 <- 0x2112623 +mem-write: 0x80008efc <- 0x2812423 +mem-write: 0x80008f00 <- 0x2912223 +mem-write: 0x80008f04 <- 0x1312e23 +mem-write: 0x80008f08 <- 0x50993 +mem-write: 0x80008f0c <- 0xd5dff0ef +mem-write: 0x80008f10 <- 0x50493 +mem-write: 0x80008f14 <- 0x58413 +mem-write: 0x80008f18 <- 0x90513 +mem-write: 0x80008f1c <- 0xc10593 +mem-write: 0x80008f20 <- 0xd49ff0ef +mem-write: 0x80008f24 <- 0x1092783 +mem-write: 0x80008f28 <- 0x109a703 +mem-write: 0x80008f2c <- 0xc12683 +mem-write: 0x80008f30 <- 0x40f70733 +mem-write: 0x80008f34 <- 0x812783 +mem-write: 0x80008f38 <- 0x571713 +mem-write: 0x80008f3c <- 0x40d787b3 +mem-write: 0x80008f40 <- 0xf707b3 +mem-write: 0x80008f44 <- 0x50693 +mem-write: 0x80008f48 <- 0x2f05e63 +mem-write: 0x80008f4c <- 0x1479793 +mem-write: 0x80008f50 <- 0x878433 +mem-write: 0x80008f54 <- 0x68613 +mem-write: 0x80008f58 <- 0x48513 +mem-write: 0x80008f5c <- 0x58693 +mem-write: 0x80008f60 <- 0x40593 +mem-write: 0x80008f64 <- 0x4c9070ef +mem-write: 0x80008f68 <- 0x2c12083 +mem-write: 0x80008f6c <- 0x2812403 +mem-write: 0x80008f70 <- 0x2412483 +mem-write: 0x80008f74 <- 0x2012903 +mem-write: 0x80008f78 <- 0x1c12983 +mem-write: 0x80008f7c <- 0x3010113 +mem-write: 0x80008f80 <- 0x8067 +mem-write: 0x80008f84 <- 0x1479713 +mem-write: 0x80008f88 <- 0x40e585b3 +mem-write: 0x80008f8c <- 0xfc9ff06f +mem-write: 0x80008f90 <- 0xff010113 +mem-write: 0x80008f94 <- 0x1212023 +mem-write: 0x80008f98 <- 0x112623 +mem-write: 0x80008f9c <- 0x812423 +mem-write: 0x80008fa0 <- 0x912223 +mem-write: 0x80008fa4 <- 0x1700793 +mem-write: 0x80008fa8 <- 0x50913 +mem-write: 0x80008fac <- 0x4a7d663 +mem-write: 0x80008fb0 <- 0x1a81a783 +mem-write: 0x80008fb4 <- 0x1ac1a583 +mem-write: 0x80008fb8 <- 0x1b01a403 +mem-write: 0x80008fbc <- 0x1b41a483 +mem-write: 0x80008fc0 <- 0x78513 +mem-write: 0x80008fc4 <- 0x40613 +mem-write: 0x80008fc8 <- 0x48693 +mem-write: 0x80008fcc <- 0x340080ef +mem-write: 0x80008fd0 <- 0xfff90913 +mem-write: 0x80008fd4 <- 0x50793 +mem-write: 0x80008fd8 <- 0xfe0914e3 +mem-write: 0x80008fdc <- 0xc12083 +mem-write: 0x80008fe0 <- 0x812403 +mem-write: 0x80008fe4 <- 0x412483 +mem-write: 0x80008fe8 <- 0x12903 +mem-write: 0x80008fec <- 0x78513 +mem-write: 0x80008ff0 <- 0x1010113 +mem-write: 0x80008ff4 <- 0x8067 +mem-write: 0x80008ff8 <- 0x800157b7 +VXDRV: upload 1024 bytes to 0x80008ffc +mem-write: 0x80008ffc <- 0x351913 +mem-write: 0x80009000 <- 0xee078793 +mem-write: 0x80009004 <- 0x1278933 +mem-write: 0x80009008 <- 0x1092783 +mem-write: 0x8000900c <- 0xc12083 +mem-write: 0x80009010 <- 0x812403 +mem-write: 0x80009014 <- 0x1492583 +mem-write: 0x80009018 <- 0x412483 +mem-write: 0x8000901c <- 0x12903 +mem-write: 0x80009020 <- 0x78513 +mem-write: 0x80009024 <- 0x1010113 +mem-write: 0x80009028 <- 0x8067 +mem-write: 0x8000902c <- 0x1062683 +mem-write: 0x80009030 <- 0xfff58593 +mem-write: 0x80009034 <- 0x4055d593 +mem-write: 0x80009038 <- 0x158593 +mem-write: 0x8000903c <- 0x1460793 +mem-write: 0x80009040 <- 0x269693 +mem-write: 0x80009044 <- 0x259593 +mem-write: 0x80009048 <- 0xd786b3 +mem-write: 0x8000904c <- 0xb505b3 +mem-write: 0x80009050 <- 0x2d7f863 +mem-write: 0x80009054 <- 0x50713 +mem-write: 0x80009058 <- 0x7a803 +mem-write: 0x8000905c <- 0x478793 +mem-write: 0x80009060 <- 0x470713 +mem-write: 0x80009064 <- 0xff072e23 +mem-write: 0x80009068 <- 0xfed7e8e3 +mem-write: 0x8000906c <- 0x40c687b3 +mem-write: 0x80009070 <- 0xfeb78793 +mem-write: 0x80009074 <- 0xffc7f793 +mem-write: 0x80009078 <- 0x478793 +mem-write: 0x8000907c <- 0xf50533 +mem-write: 0x80009080 <- 0xb57863 +mem-write: 0x80009084 <- 0x450513 +mem-write: 0x80009088 <- 0xfe052e23 +mem-write: 0x8000908c <- 0xfeb56ce3 +mem-write: 0x80009090 <- 0x8067 +mem-write: 0x80009094 <- 0x1052703 +mem-write: 0x80009098 <- 0x4055d613 +mem-write: 0x8000909c <- 0x1450693 +mem-write: 0x800090a0 <- 0x2c75263 +mem-write: 0x800090a4 <- 0x271793 +mem-write: 0x800090a8 <- 0xf687b3 +mem-write: 0x800090ac <- 0x4f6f263 +mem-write: 0x800090b0 <- 0xffc7a703 +mem-write: 0x800090b4 <- 0xffc78793 +mem-write: 0x800090b8 <- 0xfe070ae3 +mem-write: 0x800090bc <- 0x100513 +mem-write: 0x800090c0 <- 0x8067 +mem-write: 0x800090c4 <- 0x261793 +mem-write: 0x800090c8 <- 0xf687b3 +mem-write: 0x800090cc <- 0xfee650e3 +mem-write: 0x800090d0 <- 0x1f5f593 +mem-write: 0x800090d4 <- 0xfc058ce3 +mem-write: 0x800090d8 <- 0x7a603 +mem-write: 0x800090dc <- 0x100513 +mem-write: 0x800090e0 <- 0xb65733 +mem-write: 0x800090e4 <- 0xb715b3 +mem-write: 0x800090e8 <- 0xfcb602e3 +mem-write: 0x800090ec <- 0x8067 +mem-write: 0x800090f0 <- 0x513 +mem-write: 0x800090f4 <- 0x8067 +mem-write: 0x800090f8 <- 0xff010113 +mem-write: 0x800090fc <- 0x912223 +mem-write: 0x80009100 <- 0x800004b7 +mem-write: 0x80009104 <- 0x812423 +mem-write: 0x80009108 <- 0x112623 +mem-write: 0x8000910c <- 0xfff4c493 +mem-write: 0x80009110 <- 0x60413 +mem-write: 0x80009114 <- 0x62023 +mem-write: 0x80009118 <- 0xb4f6b3 +mem-write: 0x8000911c <- 0x7ff00637 +mem-write: 0x80009120 <- 0x58793 +mem-write: 0x80009124 <- 0x50713 +mem-write: 0x80009128 <- 0x4c6de63 +mem-write: 0x8000912c <- 0xa6e8b3 +mem-write: 0x80009130 <- 0x4088a63 +mem-write: 0x80009134 <- 0xc5f633 +mem-write: 0x80009138 <- 0x58813 +mem-write: 0x8000913c <- 0x893 +mem-write: 0x80009140 <- 0x2061063 +mem-write: 0x80009144 <- 0x1bc1a683 +mem-write: 0x80009148 <- 0x1b81a603 +mem-write: 0x8000914c <- 0x1c0080ef +mem-write: 0x80009150 <- 0x50713 +mem-write: 0x80009154 <- 0x58813 +mem-write: 0x80009158 <- 0xb4f6b3 +mem-write: 0x8000915c <- 0xfca00893 +mem-write: 0x80009160 <- 0x4146d693 +mem-write: 0x80009164 <- 0x801007b7 +mem-write: 0x80009168 <- 0xfff78793 +mem-write: 0x8000916c <- 0xc0268693 +mem-write: 0x80009170 <- 0xf87833 +mem-write: 0x80009174 <- 0x11686b3 +mem-write: 0x80009178 <- 0x3fe007b7 +mem-write: 0x8000917c <- 0xf867b3 +mem-write: 0x80009180 <- 0xd42023 +mem-write: 0x80009184 <- 0xc12083 +mem-write: 0x80009188 <- 0x812403 +mem-write: 0x8000918c <- 0x412483 +mem-write: 0x80009190 <- 0x70513 +mem-write: 0x80009194 <- 0x78593 +mem-write: 0x80009198 <- 0x1010113 +mem-write: 0x8000919c <- 0x8067 +mem-write: 0x800091a0 <- 0xff010113 +mem-write: 0x800091a4 <- 0x812423 +mem-write: 0x800091a8 <- 0x912223 +mem-write: 0x800091ac <- 0x50413 +mem-write: 0x800091b0 <- 0x58513 +mem-write: 0x800091b4 <- 0x112623 +mem-write: 0x800091b8 <- 0x2401a423 +mem-write: 0x800091bc <- 0xc54f70ef +mem-write: 0x800091c0 <- 0xfff00793 +mem-write: 0x800091c4 <- 0xf50c63 +mem-write: 0x800091c8 <- 0xc12083 +mem-write: 0x800091cc <- 0x812403 +mem-write: 0x800091d0 <- 0x412483 +mem-write: 0x800091d4 <- 0x1010113 +mem-write: 0x800091d8 <- 0x8067 +mem-write: 0x800091dc <- 0x2481a783 +mem-write: 0x800091e0 <- 0xfe0784e3 +mem-write: 0x800091e4 <- 0xc12083 +mem-write: 0x800091e8 <- 0xf42023 +mem-write: 0x800091ec <- 0x812403 +mem-write: 0x800091f0 <- 0x412483 +mem-write: 0x800091f4 <- 0x1010113 +mem-write: 0x800091f8 <- 0x8067 +mem-write: 0x800091fc <- 0xf6010113 +mem-write: 0x80009200 <- 0x8c10e93 +mem-write: 0x80009204 <- 0x8f12a23 +mem-write: 0x80009208 <- 0x80000337 +mem-write: 0x8000920c <- 0xffff07b7 +mem-write: 0x80009210 <- 0x58e13 +mem-write: 0x80009214 <- 0xfff34313 +mem-write: 0x80009218 <- 0x8d12623 +mem-write: 0x8000921c <- 0x20878793 +mem-write: 0x80009220 <- 0x810593 +mem-write: 0x80009224 <- 0xe8693 +mem-write: 0x80009228 <- 0x6112e23 +mem-write: 0x8000922c <- 0xf12a23 +mem-write: 0x80009230 <- 0x8e12823 +mem-write: 0x80009234 <- 0x9012c23 +mem-write: 0x80009238 <- 0x9112e23 +mem-write: 0x8000923c <- 0x1c12423 +mem-write: 0x80009240 <- 0x1c12c23 +mem-write: 0x80009244 <- 0x612e23 +mem-write: 0x80009248 <- 0x612823 +mem-write: 0x8000924c <- 0x1d12223 +mem-write: 0x80009250 <- 0x3d0000ef +mem-write: 0x80009254 <- 0x812783 +mem-write: 0x80009258 <- 0x78023 +mem-write: 0x8000925c <- 0x7c12083 +mem-write: 0x80009260 <- 0xa010113 +mem-write: 0x80009264 <- 0x8067 +mem-write: 0x80009268 <- 0x50e13 +mem-write: 0x8000926c <- 0xf6010113 +mem-write: 0x80009270 <- 0x1d81a503 +mem-write: 0x80009274 <- 0x8810e93 +mem-write: 0x80009278 <- 0x8f12a23 +mem-write: 0x8000927c <- 0x80000337 +mem-write: 0x80009280 <- 0xffff07b7 +mem-write: 0x80009284 <- 0xfff34313 +mem-write: 0x80009288 <- 0x8c12423 +mem-write: 0x8000928c <- 0x8d12623 +mem-write: 0x80009290 <- 0x20878793 +mem-write: 0x80009294 <- 0x58613 +mem-write: 0x80009298 <- 0xe8693 +mem-write: 0x8000929c <- 0x810593 +mem-write: 0x800092a0 <- 0x6112e23 +mem-write: 0x800092a4 <- 0xf12a23 +mem-write: 0x800092a8 <- 0x8e12823 +mem-write: 0x800092ac <- 0x9012c23 +mem-write: 0x800092b0 <- 0x9112e23 +mem-write: 0x800092b4 <- 0x1c12423 +mem-write: 0x800092b8 <- 0x1c12c23 +mem-write: 0x800092bc <- 0x612e23 +mem-write: 0x800092c0 <- 0x612823 +mem-write: 0x800092c4 <- 0x1d12223 +mem-write: 0x800092c8 <- 0x358000ef +mem-write: 0x800092cc <- 0x812783 +mem-write: 0x800092d0 <- 0x78023 +mem-write: 0x800092d4 <- 0x7c12083 +mem-write: 0x800092d8 <- 0xa010113 +mem-write: 0x800092dc <- 0x8067 +mem-write: 0x800092e0 <- 0xff010113 +mem-write: 0x800092e4 <- 0x812423 +mem-write: 0x800092e8 <- 0x58413 +mem-write: 0x800092ec <- 0xe59583 +mem-write: 0x800092f0 <- 0x112623 +mem-write: 0x800092f4 <- 0x7c9040ef +mem-write: 0x800092f8 <- 0x2054063 +mem-write: 0x800092fc <- 0x5042783 +mem-write: 0x80009300 <- 0xc12083 +mem-write: 0x80009304 <- 0xa787b3 +mem-write: 0x80009308 <- 0x4f42823 +mem-write: 0x8000930c <- 0x812403 +mem-write: 0x80009310 <- 0x1010113 +mem-write: 0x80009314 <- 0x8067 +mem-write: 0x80009318 <- 0xc45783 +mem-write: 0x8000931c <- 0xfffff737 +mem-write: 0x80009320 <- 0xfff70713 +mem-write: 0x80009324 <- 0xe7f7b3 +mem-write: 0x80009328 <- 0xc12083 +mem-write: 0x8000932c <- 0xf41623 +mem-write: 0x80009330 <- 0x812403 +mem-write: 0x80009334 <- 0x1010113 +mem-write: 0x80009338 <- 0x8067 +mem-write: 0x8000933c <- 0x513 +mem-write: 0x80009340 <- 0x8067 +mem-write: 0x80009344 <- 0xc59783 +mem-write: 0x80009348 <- 0xfe010113 +mem-write: 0x8000934c <- 0x812c23 +mem-write: 0x80009350 <- 0x912a23 +mem-write: 0x80009354 <- 0x1212823 +mem-write: 0x80009358 <- 0x1312623 +mem-write: 0x8000935c <- 0x112e23 +mem-write: 0x80009360 <- 0x1007f713 +mem-write: 0x80009364 <- 0x58413 +mem-write: 0x80009368 <- 0x50493 +mem-write: 0x8000936c <- 0xe59583 +mem-write: 0x80009370 <- 0x60913 +mem-write: 0x80009374 <- 0x68993 +mem-write: 0x80009378 <- 0x2071e63 +mem-write: 0x8000937c <- 0xfffff737 +mem-write: 0x80009380 <- 0xfff70713 +mem-write: 0x80009384 <- 0xe7f7b3 +mem-write: 0x80009388 <- 0xf41623 +mem-write: 0x8000938c <- 0x1812403 +mem-write: 0x80009390 <- 0x1c12083 +mem-write: 0x80009394 <- 0x98693 +mem-write: 0x80009398 <- 0x90613 +mem-write: 0x8000939c <- 0xc12983 +mem-write: 0x800093a0 <- 0x1012903 +mem-write: 0x800093a4 <- 0x48513 +mem-write: 0x800093a8 <- 0x1412483 +mem-write: 0x800093ac <- 0x2010113 +mem-write: 0x800093b0 <- 0xa80406f +mem-write: 0x800093b4 <- 0x200693 +mem-write: 0x800093b8 <- 0x613 +mem-write: 0x800093bc <- 0x3ed040ef +mem-write: 0x800093c0 <- 0xc41783 +mem-write: 0x800093c4 <- 0xe41583 +mem-write: 0x800093c8 <- 0xfb5ff06f +mem-write: 0x800093cc <- 0xff010113 +mem-write: 0x800093d0 <- 0x812423 +mem-write: 0x800093d4 <- 0x58413 +mem-write: 0x800093d8 <- 0xe59583 +mem-write: 0x800093dc <- 0x112623 +mem-write: 0x800093e0 <- 0x3c9040ef +mem-write: 0x800093e4 <- 0xfff00793 +mem-write: 0x800093e8 <- 0x2f50463 +mem-write: 0x800093ec <- 0xc45783 +mem-write: 0x800093f0 <- 0x1737 +mem-write: 0x800093f4 <- 0xc12083 +mem-write: 0x800093f8 <- 0xe7e7b3 +VXDRV: upload 1024 bytes to 0x800093fc +mem-write: 0x800093fc <- 0x4a42823 +mem-write: 0x80009400 <- 0xf41623 +mem-write: 0x80009404 <- 0x812403 +mem-write: 0x80009408 <- 0x1010113 +mem-write: 0x8000940c <- 0x8067 +mem-write: 0x80009410 <- 0xc45783 +mem-write: 0x80009414 <- 0xfffff737 +mem-write: 0x80009418 <- 0xfff70713 +mem-write: 0x8000941c <- 0xe7f7b3 +mem-write: 0x80009420 <- 0xc12083 +mem-write: 0x80009424 <- 0xf41623 +mem-write: 0x80009428 <- 0x812403 +mem-write: 0x8000942c <- 0x1010113 +mem-write: 0x80009430 <- 0x8067 +mem-write: 0x80009434 <- 0xe59583 +mem-write: 0x80009438 <- 0x1a00406f +mem-write: 0x8000943c <- 0xb567b3 +mem-write: 0x80009440 <- 0x37f793 +mem-write: 0x80009444 <- 0x8079263 +mem-write: 0x80009448 <- 0x5a703 +mem-write: 0x8000944c <- 0x7f7f86b7 +mem-write: 0x80009450 <- 0xf7f68693 +mem-write: 0x80009454 <- 0xd777b3 +mem-write: 0x80009458 <- 0xd787b3 +mem-write: 0x8000945c <- 0xe7e7b3 +mem-write: 0x80009460 <- 0xd7e7b3 +mem-write: 0x80009464 <- 0xfff00613 +mem-write: 0x80009468 <- 0x6c79e63 +mem-write: 0x8000946c <- 0x50613 +mem-write: 0x80009470 <- 0xfff00813 +mem-write: 0x80009474 <- 0xe62023 +mem-write: 0x80009478 <- 0x45a703 +mem-write: 0x8000947c <- 0x458593 +mem-write: 0x80009480 <- 0x460613 +mem-write: 0x80009484 <- 0xd777b3 +mem-write: 0x80009488 <- 0xd787b3 +mem-write: 0x8000948c <- 0xe7e7b3 +mem-write: 0x80009490 <- 0xd7e7b3 +mem-write: 0x80009494 <- 0xff0780e3 +mem-write: 0x80009498 <- 0x5c783 +mem-write: 0x8000949c <- 0x15c703 +mem-write: 0x800094a0 <- 0x25c683 +mem-write: 0x800094a4 <- 0xf60023 +mem-write: 0x800094a8 <- 0x78a63 +mem-write: 0x800094ac <- 0xe600a3 +mem-write: 0x800094b0 <- 0x70663 +mem-write: 0x800094b4 <- 0xd60123 +mem-write: 0x800094b8 <- 0x69463 +mem-write: 0x800094bc <- 0x8067 +mem-write: 0x800094c0 <- 0x601a3 +mem-write: 0x800094c4 <- 0x8067 +mem-write: 0x800094c8 <- 0x50793 +mem-write: 0x800094cc <- 0x5c703 +mem-write: 0x800094d0 <- 0x178793 +mem-write: 0x800094d4 <- 0x158593 +mem-write: 0x800094d8 <- 0xfee78fa3 +mem-write: 0x800094dc <- 0xfe0718e3 +mem-write: 0x800094e0 <- 0x8067 +mem-write: 0x800094e4 <- 0x50613 +mem-write: 0x800094e8 <- 0xfb1ff06f +mem-write: 0x800094ec <- 0x357793 +mem-write: 0x800094f0 <- 0x50713 +mem-write: 0x800094f4 <- 0x4079c63 +mem-write: 0x800094f8 <- 0x7f7f86b7 +mem-write: 0x800094fc <- 0xf7f68693 +mem-write: 0x80009500 <- 0xfff00593 +mem-write: 0x80009504 <- 0x72603 +mem-write: 0x80009508 <- 0x470713 +mem-write: 0x8000950c <- 0xd677b3 +mem-write: 0x80009510 <- 0xd787b3 +mem-write: 0x80009514 <- 0xc7e7b3 +mem-write: 0x80009518 <- 0xd7e7b3 +mem-write: 0x8000951c <- 0xfeb784e3 +mem-write: 0x80009520 <- 0xffc74683 +mem-write: 0x80009524 <- 0xffd74603 +mem-write: 0x80009528 <- 0xffe74783 +mem-write: 0x8000952c <- 0x40a70733 +mem-write: 0x80009530 <- 0x4068063 +mem-write: 0x80009534 <- 0x2060a63 +mem-write: 0x80009538 <- 0xf03533 +mem-write: 0x8000953c <- 0xe50533 +mem-write: 0x80009540 <- 0xffe50513 +mem-write: 0x80009544 <- 0x8067 +mem-write: 0x80009548 <- 0xfa0688e3 +mem-write: 0x8000954c <- 0x74783 +mem-write: 0x80009550 <- 0x170713 +mem-write: 0x80009554 <- 0x377693 +mem-write: 0x80009558 <- 0xfe0798e3 +mem-write: 0x8000955c <- 0x40a70733 +mem-write: 0x80009560 <- 0xfff70513 +mem-write: 0x80009564 <- 0x8067 +mem-write: 0x80009568 <- 0xffd70513 +mem-write: 0x8000956c <- 0x8067 +mem-write: 0x80009570 <- 0xffc70513 +mem-write: 0x80009574 <- 0x8067 +mem-write: 0x80009578 <- 0xa5e7b3 +mem-write: 0x8000957c <- 0x37f793 +mem-write: 0x80009580 <- 0x50713 +mem-write: 0x80009584 <- 0x6079863 +mem-write: 0x80009588 <- 0x300793 +mem-write: 0x8000958c <- 0x6c7f463 +mem-write: 0x80009590 <- 0xfeff0337 +mem-write: 0x80009594 <- 0x808088b7 +mem-write: 0x80009598 <- 0xeff30313 +mem-write: 0x8000959c <- 0x8088893 +mem-write: 0x800095a0 <- 0x300e13 +mem-write: 0x800095a4 <- 0x5a683 +mem-write: 0x800095a8 <- 0x6687b3 +mem-write: 0x800095ac <- 0xfff6c813 +mem-write: 0x800095b0 <- 0x107f7b3 +mem-write: 0x800095b4 <- 0x117f7b3 +mem-write: 0x800095b8 <- 0x2079e63 +mem-write: 0x800095bc <- 0xd72023 +mem-write: 0x800095c0 <- 0xffc60613 +mem-write: 0x800095c4 <- 0x470713 +mem-write: 0x800095c8 <- 0x458593 +mem-write: 0x800095cc <- 0xfcce6ce3 +mem-write: 0x800095d0 <- 0x158593 +mem-write: 0x800095d4 <- 0x170793 +mem-write: 0x800095d8 <- 0x2060463 +mem-write: 0x800095dc <- 0xfff5c683 +mem-write: 0x800095e0 <- 0xfff60813 +mem-write: 0x800095e4 <- 0xfed78fa3 +mem-write: 0x800095e8 <- 0x68e63 +mem-write: 0x800095ec <- 0x78713 +mem-write: 0x800095f0 <- 0x80613 +mem-write: 0x800095f4 <- 0x158593 +mem-write: 0x800095f8 <- 0x170793 +mem-write: 0x800095fc <- 0xfe0610e3 +mem-write: 0x80009600 <- 0x8067 +mem-write: 0x80009604 <- 0xc70633 +mem-write: 0x80009608 <- 0x80a63 +mem-write: 0x8000960c <- 0x178793 +mem-write: 0x80009610 <- 0xfe078fa3 +mem-write: 0x80009614 <- 0xfec79ce3 +mem-write: 0x80009618 <- 0x8067 +mem-write: 0x8000961c <- 0x8067 +mem-write: 0x80009620 <- 0xe1010113 +mem-write: 0x80009624 <- 0x1e112623 +mem-write: 0x80009628 <- 0x1f212023 +mem-write: 0x8000962c <- 0x1d812423 +mem-write: 0x80009630 <- 0x1da12023 +mem-write: 0x80009634 <- 0x58c13 +mem-write: 0x80009638 <- 0x60913 +mem-write: 0x8000963c <- 0xd12a23 +mem-write: 0x80009640 <- 0x1e812423 +mem-write: 0x80009644 <- 0x1e912223 +mem-write: 0x80009648 <- 0x1d312e23 +mem-write: 0x8000964c <- 0x1d412c23 +mem-write: 0x80009650 <- 0x1d512a23 +mem-write: 0x80009654 <- 0x1d612823 +mem-write: 0x80009658 <- 0x1d712623 +mem-write: 0x8000965c <- 0x1d912223 +mem-write: 0x80009660 <- 0x1bb12e23 +mem-write: 0x80009664 <- 0x50d13 +mem-write: 0x80009668 <- 0xed1fd0ef +mem-write: 0x8000966c <- 0x52783 +mem-write: 0x80009670 <- 0x78513 +mem-write: 0x80009674 <- 0x2f12823 +mem-write: 0x80009678 <- 0xe75ff0ef +mem-write: 0x8000967c <- 0xcc5703 +mem-write: 0x80009680 <- 0xe012823 +mem-write: 0x80009684 <- 0xe012a23 +mem-write: 0x80009688 <- 0xe012c23 +mem-write: 0x8000968c <- 0xe012e23 +mem-write: 0x80009690 <- 0x8077713 +mem-write: 0x80009694 <- 0x2a12623 +mem-write: 0x80009698 <- 0x70863 +mem-write: 0x8000969c <- 0x10c2703 +mem-write: 0x800096a0 <- 0x71463 +mem-write: 0x800096a4 <- 0x56c0106f +mem-write: 0x800096a8 <- 0x10c10793 +mem-write: 0x800096ac <- 0x80015737 +mem-write: 0x800096b0 <- 0xef12223 +mem-write: 0x800096b4 <- 0x78893 +mem-write: 0x800096b8 <- 0x870793 +mem-write: 0x800096bc <- 0x80015737 +mem-write: 0x800096c0 <- 0xf12c23 +mem-write: 0x800096c4 <- 0x90b13 +mem-write: 0x800096c8 <- 0x18470793 +mem-write: 0x800096cc <- 0xf12423 +mem-write: 0x800096d0 <- 0xb4783 +mem-write: 0x800096d4 <- 0xe012623 +mem-write: 0x800096d8 <- 0xe012423 +mem-write: 0x800096dc <- 0x2012023 +mem-write: 0x800096e0 <- 0x2012a23 +mem-write: 0x800096e4 <- 0x2012c23 +mem-write: 0x800096e8 <- 0x2012e23 +mem-write: 0x800096ec <- 0x4012423 +mem-write: 0x800096f0 <- 0x4012623 +mem-write: 0x800096f4 <- 0x12623 +mem-write: 0x800096f8 <- 0x22078463 +mem-write: 0x800096fc <- 0xb0413 +mem-write: 0x80009700 <- 0x2500693 +mem-write: 0x80009704 <- 0x2cd78463 +mem-write: 0x80009708 <- 0x144783 +mem-write: 0x8000970c <- 0x140413 +mem-write: 0x80009710 <- 0xfe079ae3 +mem-write: 0x80009714 <- 0x416404b3 +mem-write: 0x80009718 <- 0x21640463 +mem-write: 0x8000971c <- 0xec12683 +mem-write: 0x80009720 <- 0xe812783 +mem-write: 0x80009724 <- 0x168a023 +mem-write: 0x80009728 <- 0x9686b3 +mem-write: 0x8000972c <- 0x178793 +mem-write: 0x80009730 <- 0x98a223 +mem-write: 0x80009734 <- 0xed12623 +mem-write: 0x80009738 <- 0xef12423 +mem-write: 0x8000973c <- 0x700693 +mem-write: 0x80009740 <- 0x888893 +mem-write: 0x80009744 <- 0x28f6cc63 +mem-write: 0x80009748 <- 0xc12703 +mem-write: 0x8000974c <- 0x44783 +mem-write: 0x80009750 <- 0x970733 +mem-write: 0x80009754 <- 0xe12623 +mem-write: 0x80009758 <- 0x1c078463 +mem-write: 0x8000975c <- 0x144483 +mem-write: 0x80009760 <- 0xc0103a3 +mem-write: 0x80009764 <- 0x140413 +mem-write: 0x80009768 <- 0xfff00d93 +mem-write: 0x8000976c <- 0x993 +mem-write: 0x80009770 <- 0xa13 +mem-write: 0x80009774 <- 0x5a00913 +mem-write: 0x80009778 <- 0x900a93 +mem-write: 0x8000977c <- 0x2a00b93 +mem-write: 0x80009780 <- 0x88c93 +mem-write: 0x80009784 <- 0x140413 +mem-write: 0x80009788 <- 0xfe048793 +mem-write: 0x8000978c <- 0x4f96463 +mem-write: 0x80009790 <- 0x1812703 +mem-write: 0x80009794 <- 0x279793 +mem-write: 0x80009798 <- 0xe787b3 +mem-write: 0x8000979c <- 0x7a783 +mem-write: 0x800097a0 <- 0x78067 +mem-write: 0x800097a4 <- 0x993 +mem-write: 0x800097a8 <- 0xfd048693 +mem-write: 0x800097ac <- 0x44483 +mem-write: 0x800097b0 <- 0x299793 +mem-write: 0x800097b4 <- 0x13787b3 +mem-write: 0x800097b8 <- 0x179793 +mem-write: 0x800097bc <- 0xf689b3 +mem-write: 0x800097c0 <- 0xfd048693 +mem-write: 0x800097c4 <- 0x140413 +mem-write: 0x800097c8 <- 0xfedaf2e3 +mem-write: 0x800097cc <- 0xfe048793 +mem-write: 0x800097d0 <- 0xfcf970e3 +mem-write: 0x800097d4 <- 0xc8893 +mem-write: 0x800097d8 <- 0x14048463 +mem-write: 0x800097dc <- 0x14910623 +mem-write: 0x800097e0 <- 0xc0103a3 +mem-write: 0x800097e4 <- 0x100a93 +mem-write: 0x800097e8 <- 0x100c93 +mem-write: 0x800097ec <- 0x14c10b13 +mem-write: 0x800097f0 <- 0x12823 +mem-write: 0x800097f4 <- 0xd93 +mem-write: 0x800097f8 <- 0x2012423 +VXDRV: upload 1024 bytes to 0x800097fc +mem-write: 0x800097fc <- 0x2012223 +mem-write: 0x80009800 <- 0x12e23 +mem-write: 0x80009804 <- 0x2a7b93 +mem-write: 0x80009808 <- 0xb8463 +mem-write: 0x8000980c <- 0x2a8a93 +mem-write: 0x80009810 <- 0x84a7913 +mem-write: 0x80009814 <- 0xec12783 +mem-write: 0x80009818 <- 0x91663 +mem-write: 0x8000981c <- 0x41598833 +mem-write: 0x80009820 <- 0x63004ce3 +mem-write: 0x80009824 <- 0xc714683 +mem-write: 0x80009828 <- 0x2068a63 +mem-write: 0x8000982c <- 0xe812683 +mem-write: 0x80009830 <- 0xc710613 +mem-write: 0x80009834 <- 0xc8a023 +mem-write: 0x80009838 <- 0x178793 +mem-write: 0x8000983c <- 0x100613 +mem-write: 0x80009840 <- 0x168693 +mem-write: 0x80009844 <- 0xc8a223 +mem-write: 0x80009848 <- 0xef12623 +mem-write: 0x8000984c <- 0xed12423 +mem-write: 0x80009850 <- 0x700613 +mem-write: 0x80009854 <- 0x888893 +mem-write: 0x80009858 <- 0x4cd64c63 +mem-write: 0x8000985c <- 0x20b8a63 +mem-write: 0x80009860 <- 0xe812683 +mem-write: 0x80009864 <- 0xc810613 +mem-write: 0x80009868 <- 0xc8a023 +mem-write: 0x8000986c <- 0x278793 +mem-write: 0x80009870 <- 0x200613 +mem-write: 0x80009874 <- 0x168693 +mem-write: 0x80009878 <- 0xc8a223 +mem-write: 0x8000987c <- 0xef12623 +mem-write: 0x80009880 <- 0xed12423 +mem-write: 0x80009884 <- 0x700613 +mem-write: 0x80009888 <- 0x888893 +mem-write: 0x8000988c <- 0x6ad64ce3 +mem-write: 0x80009890 <- 0x8000693 +mem-write: 0x80009894 <- 0x42d900e3 +mem-write: 0x80009898 <- 0x419d8db3 +mem-write: 0x8000989c <- 0x4db04ee3 +mem-write: 0x800098a0 <- 0x100a7693 +mem-write: 0x800098a4 <- 0x2c069ae3 +mem-write: 0x800098a8 <- 0xe812703 +mem-write: 0x800098ac <- 0x19787b3 +mem-write: 0x800098b0 <- 0x168a023 +mem-write: 0x800098b4 <- 0x170713 +mem-write: 0x800098b8 <- 0x198a223 +mem-write: 0x800098bc <- 0xef12623 +mem-write: 0x800098c0 <- 0xee12423 +mem-write: 0x800098c4 <- 0x700693 +mem-write: 0x800098c8 <- 0x5ae6c063 +mem-write: 0x800098cc <- 0x888893 +mem-write: 0x800098d0 <- 0x4a7a13 +mem-write: 0x800098d4 <- 0xa0663 +mem-write: 0x800098d8 <- 0x415984b3 +mem-write: 0x800098dc <- 0x5a904663 +mem-write: 0x800098e0 <- 0x159d463 +mem-write: 0x800098e4 <- 0xa8993 +mem-write: 0x800098e8 <- 0xc12703 +mem-write: 0x800098ec <- 0x1370733 +mem-write: 0x800098f0 <- 0xe12623 +mem-write: 0x800098f4 <- 0x52079ce3 +mem-write: 0x800098f8 <- 0x1012783 +mem-write: 0x800098fc <- 0xe012423 +mem-write: 0x80009900 <- 0x78863 +mem-write: 0x80009904 <- 0x1012583 +mem-write: 0x80009908 <- 0xd0513 +mem-write: 0x8000990c <- 0xc59fa0ef +mem-write: 0x80009910 <- 0x10c10893 +mem-write: 0x80009914 <- 0x40b13 +mem-write: 0x80009918 <- 0xb4783 +mem-write: 0x8000991c <- 0xde0790e3 +mem-write: 0x80009920 <- 0xec12783 +mem-write: 0x80009924 <- 0x78463 +mem-write: 0x80009928 <- 0x3450106f +mem-write: 0x8000992c <- 0xcc5703 +mem-write: 0x80009930 <- 0x4077713 +mem-write: 0x80009934 <- 0x70463 +mem-write: 0x80009938 <- 0x3f80206f +mem-write: 0x8000993c <- 0x1ec12083 +mem-write: 0x80009940 <- 0x1e812403 +mem-write: 0x80009944 <- 0xc12503 +mem-write: 0x80009948 <- 0x1e412483 +mem-write: 0x8000994c <- 0x1e012903 +mem-write: 0x80009950 <- 0x1dc12983 +mem-write: 0x80009954 <- 0x1d812a03 +mem-write: 0x80009958 <- 0x1d412a83 +mem-write: 0x8000995c <- 0x1d012b03 +mem-write: 0x80009960 <- 0x1cc12b83 +mem-write: 0x80009964 <- 0x1c812c03 +mem-write: 0x80009968 <- 0x1c412c83 +mem-write: 0x8000996c <- 0x1c012d03 +mem-write: 0x80009970 <- 0x1bc12d83 +mem-write: 0x80009974 <- 0x1f010113 +mem-write: 0x80009978 <- 0x8067 +mem-write: 0x8000997c <- 0xd0513 +mem-write: 0x80009980 <- 0xbb9fd0ef +mem-write: 0x80009984 <- 0x452783 +mem-write: 0x80009988 <- 0x78513 +mem-write: 0x8000998c <- 0x4f12623 +mem-write: 0x80009990 <- 0xb5dff0ef +mem-write: 0x80009994 <- 0x50793 +mem-write: 0x80009998 <- 0xd0513 +mem-write: 0x8000999c <- 0x78493 +mem-write: 0x800099a0 <- 0x4f12423 +mem-write: 0x800099a4 <- 0xb95fd0ef +mem-write: 0x800099a8 <- 0x852783 +mem-write: 0x800099ac <- 0x2f12e23 +mem-write: 0x800099b0 <- 0x48463 +mem-write: 0x800099b4 <- 0x1640106f +mem-write: 0x800099b8 <- 0x44483 +mem-write: 0x800099bc <- 0xdc9ff06f +mem-write: 0x800099c0 <- 0x44483 +mem-write: 0x800099c4 <- 0x20a6a13 +mem-write: 0x800099c8 <- 0xdbdff06f +mem-write: 0x800099cc <- 0x416404b3 +mem-write: 0x800099d0 <- 0xd56416e3 +mem-write: 0x800099d4 <- 0x44783 +mem-write: 0x800099d8 <- 0xd81ff06f +mem-write: 0x800099dc <- 0xe410613 +mem-write: 0x800099e0 <- 0xc0593 +mem-write: 0x800099e4 <- 0xd0513 +mem-write: 0x800099e8 <- 0x174050ef +mem-write: 0x800099ec <- 0xf40510e3 +mem-write: 0x800099f0 <- 0x10c10893 +mem-write: 0x800099f4 <- 0xd55ff06f +mem-write: 0x800099f8 <- 0x8a7793 +mem-write: 0x800099fc <- 0xc8893 +mem-write: 0x80009a00 <- 0x78463 +mem-write: 0x80009a04 <- 0xa80106f +mem-write: 0x80009a08 <- 0x1412783 +mem-write: 0x80009a0c <- 0xb010513 +mem-write: 0x80009a10 <- 0x1912823 +mem-write: 0x80009a14 <- 0x778793 +mem-write: 0x80009a18 <- 0xff87f793 +mem-write: 0x80009a1c <- 0x7a583 +mem-write: 0x80009a20 <- 0x47a603 +mem-write: 0x80009a24 <- 0x878793 +mem-write: 0x80009a28 <- 0xf12a23 +mem-write: 0x80009a2c <- 0x1810a0ef +mem-write: 0x80009a30 <- 0xb012783 +mem-write: 0x80009a34 <- 0x1012883 +mem-write: 0x80009a38 <- 0xef12823 +mem-write: 0x80009a3c <- 0xb412783 +mem-write: 0x80009a40 <- 0xef12a23 +mem-write: 0x80009a44 <- 0xb812783 +mem-write: 0x80009a48 <- 0xef12c23 +mem-write: 0x80009a4c <- 0xbc12783 +mem-write: 0x80009a50 <- 0xef12e23 +mem-write: 0x80009a54 <- 0xf010513 +mem-write: 0x80009a58 <- 0x1112823 +mem-write: 0x80009a5c <- 0xa71fd0ef +mem-write: 0x80009a60 <- 0xca12623 +mem-write: 0x80009a64 <- 0x200793 +mem-write: 0x80009a68 <- 0x1012883 +mem-write: 0x80009a6c <- 0xf51463 +mem-write: 0x80009a70 <- 0x6580106f +mem-write: 0x80009a74 <- 0x100793 +mem-write: 0x80009a78 <- 0xf51463 +mem-write: 0x80009a7c <- 0x750106f +mem-write: 0x80009a80 <- 0x6100793 +mem-write: 0x80009a84 <- 0xf49463 +mem-write: 0x80009a88 <- 0x19c0206f +mem-write: 0x80009a8c <- 0x4100793 +mem-write: 0x80009a90 <- 0xf49463 +mem-write: 0x80009a94 <- 0x52d0106f +mem-write: 0x80009a98 <- 0xfdf4fb93 +mem-write: 0x80009a9c <- 0xfff00793 +mem-write: 0x80009aa0 <- 0x5712a23 +mem-write: 0x80009aa4 <- 0xfd9463 +mem-write: 0x80009aa8 <- 0x2150106f +mem-write: 0x80009aac <- 0x4700793 +mem-write: 0x80009ab0 <- 0xfb9463 +mem-write: 0x80009ab4 <- 0x1e80206f +mem-write: 0x80009ab8 <- 0xfc12303 +mem-write: 0x80009abc <- 0x3412423 +mem-write: 0x80009ac0 <- 0xf012e03 +mem-write: 0x80009ac4 <- 0xf412e83 +mem-write: 0x80009ac8 <- 0xf812f03 +mem-write: 0x80009acc <- 0x100a6793 +mem-write: 0x80009ad0 <- 0x35463 +mem-write: 0x80009ad4 <- 0x39c0206f +mem-write: 0x80009ad8 <- 0x4012c23 +mem-write: 0x80009adc <- 0x78a13 +mem-write: 0x80009ae0 <- 0x12823 +mem-write: 0x80009ae4 <- 0x4600793 +mem-write: 0x80009ae8 <- 0xfb9463 +mem-write: 0x80009aec <- 0x2b90106f +mem-write: 0x80009af0 <- 0x4500793 +mem-write: 0x80009af4 <- 0x5112223 +mem-write: 0x80009af8 <- 0xfb8463 +mem-write: 0x80009afc <- 0x33d0106f +mem-write: 0x80009b00 <- 0x1d8913 +mem-write: 0x80009b04 <- 0xb010a93 +mem-write: 0x80009b08 <- 0x90693 +mem-write: 0x80009b0c <- 0xdc10813 +mem-write: 0x80009b10 <- 0xd010793 +mem-write: 0x80009b14 <- 0xcc10713 +mem-write: 0x80009b18 <- 0x200613 +mem-write: 0x80009b1c <- 0xa8593 +mem-write: 0x80009b20 <- 0xd0513 +mem-write: 0x80009b24 <- 0xbc12823 +mem-write: 0x80009b28 <- 0x5c12023 +mem-write: 0x80009b2c <- 0xbd12a23 +mem-write: 0x80009b30 <- 0x3d12223 +mem-write: 0x80009b34 <- 0xbe12c23 +mem-write: 0x80009b38 <- 0x3e12023 +mem-write: 0x80009b3c <- 0xa612e23 +mem-write: 0x80009b40 <- 0x612e23 +mem-write: 0x80009b44 <- 0xef0fc0ef +mem-write: 0x80009b48 <- 0x1c12303 +mem-write: 0x80009b4c <- 0x2012f03 +mem-write: 0x80009b50 <- 0x2412e83 +mem-write: 0x80009b54 <- 0x4012e03 +mem-write: 0x80009b58 <- 0x4412883 +mem-write: 0x80009b5c <- 0x50b13 +mem-write: 0x80009b60 <- 0x1250933 +mem-write: 0x80009b64 <- 0xa010c93 +mem-write: 0x80009b68 <- 0xc8593 +mem-write: 0x80009b6c <- 0xa8513 +mem-write: 0x80009b70 <- 0x1112e23 +mem-write: 0x80009b74 <- 0xbc12823 +mem-write: 0x80009b78 <- 0xbd12a23 +mem-write: 0x80009b7c <- 0xbe12c23 +mem-write: 0x80009b80 <- 0xa612e23 +mem-write: 0x80009b84 <- 0xa012023 +mem-write: 0x80009b88 <- 0xa012223 +mem-write: 0x80009b8c <- 0xa012423 +mem-write: 0x80009b90 <- 0xa012623 +mem-write: 0x80009b94 <- 0x53d070ef +mem-write: 0x80009b98 <- 0x1c12883 +mem-write: 0x80009b9c <- 0x90713 +mem-write: 0x80009ba0 <- 0x2050263 +mem-write: 0x80009ba4 <- 0xdc12703 +mem-write: 0x80009ba8 <- 0x1277e63 +mem-write: 0x80009bac <- 0x3000693 +mem-write: 0x80009bb0 <- 0x170793 +mem-write: 0x80009bb4 <- 0xcf12e23 +mem-write: 0x80009bb8 <- 0xd70023 +mem-write: 0x80009bbc <- 0xdc12703 +mem-write: 0x80009bc0 <- 0xff2768e3 +mem-write: 0x80009bc4 <- 0x416707b3 +mem-write: 0x80009bc8 <- 0x2f12023 +mem-write: 0x80009bcc <- 0xcc12703 +mem-write: 0x80009bd0 <- 0x4700793 +mem-write: 0x80009bd4 <- 0xe12e23 +mem-write: 0x80009bd8 <- 0x5412703 +mem-write: 0x80009bdc <- 0xf71463 +mem-write: 0x80009be0 <- 0x1150106f +mem-write: 0x80009be4 <- 0x5412703 +mem-write: 0x80009be8 <- 0x4600793 +mem-write: 0x80009bec <- 0xf71463 +mem-write: 0x80009bf0 <- 0x34d0106f +mem-write: 0x80009bf4 <- 0x1c12783 +mem-write: 0x80009bf8 <- 0x5412703 +VXDRV: upload 1023 bytes to 0x80009bfc +mem-write: 0x80009bfc <- 0x4100593 +mem-write: 0x80009c00 <- 0xfff78793 +mem-write: 0x80009c04 <- 0xcf12623 +mem-write: 0x80009c08 <- 0xff4f693 +mem-write: 0x80009c0c <- 0x613 +mem-write: 0x80009c10 <- 0xb71863 +mem-write: 0x80009c14 <- 0xf68693 +mem-write: 0x80009c18 <- 0xff6f693 +mem-write: 0x80009c1c <- 0x100613 +mem-write: 0x80009c20 <- 0xcd10a23 +mem-write: 0x80009c24 <- 0x2b00693 +mem-write: 0x80009c28 <- 0x7da63 +mem-write: 0x80009c2c <- 0x1c12703 +mem-write: 0x80009c30 <- 0x100793 +mem-write: 0x80009c34 <- 0x2d00693 +mem-write: 0x80009c38 <- 0x40e787b3 +mem-write: 0x80009c3c <- 0xcd10aa3 +mem-write: 0x80009c40 <- 0x900693 +mem-write: 0x80009c44 <- 0xf6c463 +mem-write: 0x80009c48 <- 0xf40206f +mem-write: 0x80009c4c <- 0xe310813 +mem-write: 0x80009c50 <- 0x80513 +mem-write: 0x80009c54 <- 0xa00613 +mem-write: 0x80009c58 <- 0x6300e13 +mem-write: 0x80009c5c <- 0x2c7e733 +mem-write: 0x80009c60 <- 0x50593 +mem-write: 0x80009c64 <- 0x78693 +mem-write: 0x80009c68 <- 0xfff50513 +mem-write: 0x80009c6c <- 0x3070713 +mem-write: 0x80009c70 <- 0xfee58fa3 +mem-write: 0x80009c74 <- 0x2c7c7b3 +mem-write: 0x80009c78 <- 0xfede42e3 +mem-write: 0x80009c7c <- 0x3078793 +mem-write: 0x80009c80 <- 0xff7f613 +mem-write: 0x80009c84 <- 0xfec50fa3 +mem-write: 0x80009c88 <- 0xffe58793 +mem-write: 0x80009c8c <- 0x107e463 +mem-write: 0x80009c90 <- 0x3980206f +mem-write: 0x80009c94 <- 0xd610693 +mem-write: 0x80009c98 <- 0x80006f +mem-write: 0x80009c9c <- 0x7c603 +mem-write: 0x80009ca0 <- 0xc68023 +mem-write: 0x80009ca4 <- 0x178793 +mem-write: 0x80009ca8 <- 0x168693 +mem-write: 0x80009cac <- 0xff0798e3 +mem-write: 0x80009cb0 <- 0xe510793 +mem-write: 0x80009cb4 <- 0x40b787b3 +mem-write: 0x80009cb8 <- 0xd610713 +mem-write: 0x80009cbc <- 0xf707b3 +mem-write: 0x80009cc0 <- 0xd410693 +mem-write: 0x80009cc4 <- 0x40d787b3 +mem-write: 0x80009cc8 <- 0x2f12c23 +mem-write: 0x80009ccc <- 0x2012703 +mem-write: 0x80009cd0 <- 0x3812683 +mem-write: 0x80009cd4 <- 0x100793 +mem-write: 0x80009cd8 <- 0xd70cb3 +mem-write: 0x80009cdc <- 0xe7c463 +mem-write: 0x80009ce0 <- 0x2300206f +mem-write: 0x80009ce4 <- 0x2c12783 +mem-write: 0x80009ce8 <- 0xfc8cb3 +mem-write: 0x80009cec <- 0x2812783 +mem-write: 0x80009cf0 <- 0xfffcca93 +mem-write: 0x80009cf4 <- 0x41fada93 +mem-write: 0x80009cf8 <- 0xbff7fa13 +mem-write: 0x80009cfc <- 0x100a6a13 +mem-write: 0x80009d00 <- 0x15cfab3 +mem-write: 0x80009d04 <- 0x2012423 +mem-write: 0x80009d08 <- 0x2012223 +mem-write: 0x80009d0c <- 0x12e23 +mem-write: 0x80009d10 <- 0x5812783 +mem-write: 0x80009d14 <- 0x79463 +mem-write: 0x80009d18 <- 0x510106f +mem-write: 0x80009d1c <- 0x2d00793 +mem-write: 0x80009d20 <- 0xcf103a3 +mem-write: 0x80009d24 <- 0xd93 +mem-write: 0x80009d28 <- 0x1a8a93 +mem-write: 0x80009d2c <- 0xad9ff06f +mem-write: 0x80009d30 <- 0xe410613 +mem-write: 0x80009d34 <- 0xc0593 +mem-write: 0x80009d38 <- 0xd0513 +mem-write: 0x80009d3c <- 0x621040ef +mem-write: 0x80009d40 <- 0x100510e3 +mem-write: 0x80009d44 <- 0xec12783 +mem-write: 0x80009d48 <- 0x10c10893 +mem-write: 0x80009d4c <- 0xb11ff06f +mem-write: 0x80009d50 <- 0xe812683 +mem-write: 0x80009d54 <- 0x178c93 +mem-write: 0x80009d58 <- 0x2012783 +mem-write: 0x80009d5c <- 0x100613 +mem-write: 0x80009d60 <- 0x168a023 +mem-write: 0x80009d64 <- 0x168493 +mem-write: 0x80009d68 <- 0x888913 +mem-write: 0x80009d6c <- 0x36f658e3 +mem-write: 0x80009d70 <- 0x100793 +mem-write: 0x80009d74 <- 0xf8a223 +mem-write: 0x80009d78 <- 0xf912623 +mem-write: 0x80009d7c <- 0xe912423 +mem-write: 0x80009d80 <- 0x700793 +mem-write: 0x80009d84 <- 0x4a97c0e3 +mem-write: 0x80009d88 <- 0x2c12783 +mem-write: 0x80009d8c <- 0x3012703 +mem-write: 0x80009d90 <- 0x148493 +mem-write: 0x80009d94 <- 0xfc8cb3 +mem-write: 0x80009d98 <- 0xf92223 +mem-write: 0x80009d9c <- 0xe92023 +mem-write: 0x80009da0 <- 0xf912623 +mem-write: 0x80009da4 <- 0xe912423 +mem-write: 0x80009da8 <- 0x700793 +mem-write: 0x80009dac <- 0x890913 +mem-write: 0x80009db0 <- 0x4897cce3 +mem-write: 0x80009db4 <- 0xf012783 +mem-write: 0x80009db8 <- 0x148613 +mem-write: 0x80009dbc <- 0xa010593 +mem-write: 0x80009dc0 <- 0xaf12823 +mem-write: 0x80009dc4 <- 0xf412783 +mem-write: 0x80009dc8 <- 0xb010513 +mem-write: 0x80009dcc <- 0xc12e23 +mem-write: 0x80009dd0 <- 0xaf12a23 +mem-write: 0x80009dd4 <- 0xf812783 +mem-write: 0x80009dd8 <- 0xa012023 +mem-write: 0x80009ddc <- 0xa012223 +mem-write: 0x80009de0 <- 0xaf12c23 +mem-write: 0x80009de4 <- 0xfc12783 +mem-write: 0x80009de8 <- 0xa012423 +mem-write: 0x80009dec <- 0xa012623 +mem-write: 0x80009df0 <- 0xaf12e23 +mem-write: 0x80009df4 <- 0x2dd070ef +mem-write: 0x80009df8 <- 0x1c12603 +mem-write: 0x80009dfc <- 0x2012783 +mem-write: 0x80009e00 <- 0x890893 +mem-write: 0x80009e04 <- 0x60693 +mem-write: 0x80009e08 <- 0xfff78d93 +mem-write: 0x80009e0c <- 0x2e050ce3 +mem-write: 0x80009e10 <- 0x1b0713 +mem-write: 0x80009e14 <- 0x1bc8cb3 +mem-write: 0x80009e18 <- 0xe92023 +mem-write: 0x80009e1c <- 0x1b92223 +mem-write: 0x80009e20 <- 0xf912623 +mem-write: 0x80009e24 <- 0xec12423 +mem-write: 0x80009e28 <- 0x700793 +mem-write: 0x80009e2c <- 0xc7d463 +mem-write: 0x80009e30 <- 0x180106f +mem-write: 0x80009e34 <- 0x1090793 +mem-write: 0x80009e38 <- 0x248693 +mem-write: 0x80009e3c <- 0x88913 +mem-write: 0x80009e40 <- 0x78893 +mem-write: 0x80009e44 <- 0x3812603 +mem-write: 0x80009e48 <- 0xd410713 +mem-write: 0x80009e4c <- 0xe92023 +mem-write: 0x80009e50 <- 0x19607b3 +mem-write: 0x80009e54 <- 0xc92223 +mem-write: 0x80009e58 <- 0xef12623 +mem-write: 0x80009e5c <- 0xed12423 +mem-write: 0x80009e60 <- 0x700713 +mem-write: 0x80009e64 <- 0xa6d756e3 +mem-write: 0x80009e68 <- 0xe410613 +mem-write: 0x80009e6c <- 0xc0593 +mem-write: 0x80009e70 <- 0xd0513 +mem-write: 0x80009e74 <- 0x4e9040ef +mem-write: 0x80009e78 <- 0x7c051463 +mem-write: 0x80009e7c <- 0xec12783 +mem-write: 0x80009e80 <- 0x10c10893 +mem-write: 0x80009e84 <- 0xa4dff06f +mem-write: 0x80009e88 <- 0x1000693 +mem-write: 0x80009e8c <- 0xe812703 +mem-write: 0x80009e90 <- 0x96c463 +mem-write: 0x80009e94 <- 0x1210106f +mem-write: 0x80009e98 <- 0x800156b7 +mem-write: 0x80009e9c <- 0x17468e93 +mem-write: 0x80009ea0 <- 0x1000913 +mem-write: 0x80009ea4 <- 0x700a13 +mem-write: 0x80009ea8 <- 0xe8b13 +mem-write: 0x80009eac <- 0xc0006f +mem-write: 0x80009eb0 <- 0xff048493 +mem-write: 0x80009eb4 <- 0x4995663 +mem-write: 0x80009eb8 <- 0x1078793 +mem-write: 0x80009ebc <- 0x170713 +mem-write: 0x80009ec0 <- 0x168a023 +mem-write: 0x80009ec4 <- 0x128a223 +mem-write: 0x80009ec8 <- 0xef12623 +mem-write: 0x80009ecc <- 0xee12423 +mem-write: 0x80009ed0 <- 0x888893 +mem-write: 0x80009ed4 <- 0xfcea5ee3 +mem-write: 0x80009ed8 <- 0xe410613 +mem-write: 0x80009edc <- 0xc0593 +mem-write: 0x80009ee0 <- 0xd0513 +mem-write: 0x80009ee4 <- 0x479040ef +mem-write: 0x80009ee8 <- 0x74051c63 +mem-write: 0x80009eec <- 0xff048493 +mem-write: 0x80009ef0 <- 0xec12783 +mem-write: 0x80009ef4 <- 0xe812703 +mem-write: 0x80009ef8 <- 0x10c10893 +mem-write: 0x80009efc <- 0xfa994ee3 +mem-write: 0x80009f00 <- 0xb0e93 +mem-write: 0x80009f04 <- 0x9787b3 +mem-write: 0x80009f08 <- 0x170713 +mem-write: 0x80009f0c <- 0x1d8a023 +mem-write: 0x80009f10 <- 0x98a223 +mem-write: 0x80009f14 <- 0xef12623 +mem-write: 0x80009f18 <- 0xee12423 +mem-write: 0x80009f1c <- 0x700693 +mem-write: 0x80009f20 <- 0x9ce6d0e3 +mem-write: 0x80009f24 <- 0xe410613 +mem-write: 0x80009f28 <- 0xc0593 +mem-write: 0x80009f2c <- 0xd0513 +mem-write: 0x80009f30 <- 0x42d040ef +mem-write: 0x80009f34 <- 0x70051663 +mem-write: 0x80009f38 <- 0xec12783 +mem-write: 0x80009f3c <- 0x9a5ff06f +mem-write: 0x80009f40 <- 0x1412783 +mem-write: 0x80009f44 <- 0xc0103a3 +mem-write: 0x80009f48 <- 0xc8893 +mem-write: 0x80009f4c <- 0x7ab03 +mem-write: 0x80009f50 <- 0x478913 +mem-write: 0x80009f54 <- 0x4e0b02e3 +mem-write: 0x80009f58 <- 0xfff00793 +mem-write: 0x80009f5c <- 0xfd9463 +mem-write: 0x80009f60 <- 0x1fc0106f +mem-write: 0x80009f64 <- 0xd8613 +mem-write: 0x80009f68 <- 0x593 +mem-write: 0x80009f6c <- 0xb0513 +mem-write: 0x80009f70 <- 0x1912a23 +mem-write: 0x80009f74 <- 0xf5dfd0ef +mem-write: 0x80009f78 <- 0xa12823 +mem-write: 0x80009f7c <- 0x1412883 +mem-write: 0x80009f80 <- 0x51463 +mem-write: 0x80009f84 <- 0x75c0106f +mem-write: 0x80009f88 <- 0x1012783 +mem-write: 0x80009f8c <- 0x1212a23 +mem-write: 0x80009f90 <- 0x12823 +mem-write: 0x80009f94 <- 0x41678cb3 +mem-write: 0x80009f98 <- 0xc714783 +mem-write: 0x80009f9c <- 0xfffcca93 +mem-write: 0x80009fa0 <- 0x41fada93 +mem-write: 0x80009fa4 <- 0x2012423 +mem-write: 0x80009fa8 <- 0x2012223 +mem-write: 0x80009fac <- 0x12e23 +mem-write: 0x80009fb0 <- 0x15cfab3 +mem-write: 0x80009fb4 <- 0xd93 +mem-write: 0x80009fb8 <- 0x840786e3 +mem-write: 0x80009fbc <- 0x1a8a93 +mem-write: 0x80009fc0 <- 0x845ff06f +mem-write: 0x80009fc4 <- 0x1412703 +mem-write: 0x80009fc8 <- 0xc8893 +mem-write: 0x80009fcc <- 0xc0103a3 +mem-write: 0x80009fd0 <- 0x72783 +mem-write: 0x80009fd4 <- 0x470713 +mem-write: 0x80009fd8 <- 0xe12a23 +mem-write: 0x80009fdc <- 0x14f10623 +mem-write: 0x80009fe0 <- 0x100a93 +mem-write: 0x80009fe4 <- 0x100c93 +mem-write: 0x80009fe8 <- 0x14c10b13 +mem-write: 0x80009fec <- 0x805ff06f +mem-write: 0x80009ff0 <- 0x44483 +mem-write: 0x80009ff4 <- 0x4a6a13 +mem-write: 0x80009ff8 <- 0x5cff06f +VXDRV: upload 1024 bytes to 0x80009ffb +mem-write: 0x80009ffb <- 0x412683f8 +mem-write: 0x80009fff <- 0xa779301 +mem-write: 0x8000a003 <- 0xc889302 +mem-write: 0x8000a007 <- 0x6a70300 +mem-write: 0x8000a00b <- 0x46869300 +mem-write: 0x8000a00f <- 0xd12a2300 +mem-write: 0x8000a013 <- 0x790e300 +mem-write: 0x8000a017 <- 0xa779328 +mem-write: 0x8000a01b <- 0x7846301 +mem-write: 0x8000a01f <- 0xc0106f00 +mem-write: 0x8000a023 <- 0xa779312 +mem-write: 0x8000a027 <- 0x7846304 +mem-write: 0x8000a02b <- 0x80106f00 +mem-write: 0x8000a02f <- 0xa7a133d +mem-write: 0x8000a033 <- 0xa146320 +mem-write: 0x8000a037 <- 0x40106f00 +mem-write: 0x8000a03b <- 0xc1278311 +mem-write: 0x8000a03f <- 0x40b1300 +mem-write: 0x8000a043 <- 0xf7002300 +mem-write: 0x8000a047 <- 0x1ff06f00 +mem-write: 0x8000a04b <- 0x444838d +mem-write: 0x8000a04f <- 0xc0079300 +mem-write: 0x8000a053 <- 0xf48ee306 +mem-write: 0x8000a057 <- 0xa6a1338 +mem-write: 0x8000a05b <- 0x8ff06f01 +mem-write: 0x8000a05f <- 0x412703f2 +mem-write: 0x8000a063 <- 0xff87b701 +mem-write: 0x8000a067 <- 0x7c793ff +mem-write: 0x8000a06b <- 0xf1142383 +mem-write: 0x8000a06f <- 0x4707930c +mem-write: 0x8000a073 <- 0xf12a2300 +mem-write: 0x8000a077 <- 0x7290300 +mem-write: 0x8000a07b <- 0x157b700 +mem-write: 0x8000a07f <- 0xc7879380 +mem-write: 0x8000a083 <- 0xc8893a3 +mem-write: 0x8000a087 <- 0xf12a2300 +mem-write: 0x8000a08b <- 0xc9302 +mem-write: 0x8000a08f <- 0x2a6b9300 +mem-write: 0x8000a093 <- 0x20079300 +mem-write: 0x8000a097 <- 0x80049300 +mem-write: 0x8000a09b <- 0x103a307 +mem-write: 0x8000a09f <- 0xf007130c +mem-write: 0x8000a0a3 <- 0xed8663ff +mem-write: 0x8000a0a7 <- 0x99673320 +mem-write: 0x8000a0ab <- 0xfbfa1301 +mem-write: 0x8000a0af <- 0x71e63f7 +mem-write: 0x8000a0b3 <- 0xd94631e +mem-write: 0x8000a0b7 <- 0x7906326 +mem-write: 0x8000a0bb <- 0x1bfc931c +mem-write: 0x8000a0bf <- 0x10b1300 +mem-write: 0x8000a0c3 <- 0xc90e31b +mem-write: 0x8000a0c7 <- 0xc8a931c +mem-write: 0x8000a0cb <- 0xbcd46300 +mem-write: 0x8000a0cf <- 0xd8a9301 +mem-write: 0x8000a0d3 <- 0x71478300 +mem-write: 0x8000a0d7 <- 0x128230c +mem-write: 0x8000a0db <- 0x1242300 +mem-write: 0x8000a0df <- 0x1222302 +mem-write: 0x8000a0e3 <- 0x12e2302 +mem-write: 0x8000a0e7 <- 0x79ae300 +mem-write: 0x8000a0eb <- 0x8ff06fec +mem-write: 0x8000a0ef <- 0xc8893f1 +mem-write: 0x8000a0f3 <- 0xa6a1300 +mem-write: 0x8000a0f7 <- 0xa779301 +mem-write: 0x8000a0fb <- 0x78ce302 +mem-write: 0x8000a0ff <- 0x41278306 +mem-write: 0x8000a103 <- 0x778b1301 +mem-write: 0x8000a107 <- 0x8b7b1300 +mem-write: 0x8000a10b <- 0xb2903ff +mem-write: 0x8000a10f <- 0x4b2c8300 +mem-write: 0x8000a113 <- 0x8b079300 +mem-write: 0x8000a117 <- 0xf12a2300 +mem-write: 0x8000a11b <- 0xfa7b9300 +mem-write: 0x8000a11f <- 0x793bf +mem-write: 0x8000a123 <- 0x9ff06f00 +mem-write: 0x8000a127 <- 0x44483f7 +mem-write: 0x8000a12b <- 0x80079300 +mem-write: 0x8000a12f <- 0xf488e306 +mem-write: 0x8000a133 <- 0xa6a132c +mem-write: 0x8000a137 <- 0xcff06f04 +mem-write: 0x8000a13b <- 0xc8893e4 +mem-write: 0x8000a13f <- 0xa6b9300 +mem-write: 0x8000a143 <- 0xbf79301 +mem-write: 0x8000a147 <- 0x78ce302 +mem-write: 0x8000a14b <- 0x41278304 +mem-write: 0x8000a14f <- 0x778b1301 +mem-write: 0x8000a153 <- 0x8b7b1300 +mem-write: 0x8000a157 <- 0x8b0793ff +mem-write: 0x8000a15b <- 0xf12a2300 +mem-write: 0x8000a15f <- 0xb290300 +mem-write: 0x8000a163 <- 0x4b2c8300 +mem-write: 0x8000a167 <- 0x10079300 +mem-write: 0x8000a16b <- 0x1ff06f00 +mem-write: 0x8000a16f <- 0x44483f3 +mem-write: 0x8000a173 <- 0x8a6a1300 +mem-write: 0x8000a177 <- 0xcff06f00 +mem-write: 0x8000a17b <- 0x412783e0 +mem-write: 0x8000a17f <- 0x4448301 +mem-write: 0x8000a183 <- 0x7a98300 +mem-write: 0x8000a187 <- 0x47879300 +mem-write: 0x8000a18b <- 0xf12a2300 +mem-write: 0x8000a18f <- 0x9da6300 +mem-write: 0x8000a193 <- 0x3009b3de +mem-write: 0x8000a197 <- 0x4a6a1341 +mem-write: 0x8000a19b <- 0x8ff06f00 +mem-write: 0x8000a19f <- 0x44483de +mem-write: 0x8000a1a3 <- 0x1a6a1300 +mem-write: 0x8000a1a7 <- 0xcff06f00 +mem-write: 0x8000a1ab <- 0x714783dd +mem-write: 0x8000a1af <- 0x444830c +mem-write: 0x8000a1b3 <- 0x7986300 +mem-write: 0x8000a1b7 <- 0x793dc +mem-write: 0x8000a1bb <- 0xf103a302 +mem-write: 0x8000a1bf <- 0x4ff06f0c +mem-write: 0x8000a1c3 <- 0x44483dc +mem-write: 0x8000a1c7 <- 0xa6a1300 +mem-write: 0x8000a1cb <- 0x8ff06f08 +mem-write: 0x8000a1cf <- 0x44483db +mem-write: 0x8000a1d3 <- 0x14071300 +mem-write: 0x8000a1d7 <- 0x74946300 +mem-write: 0x8000a1db <- 0x50106f01 +mem-write: 0x8000a1df <- 0x486935f +mem-write: 0x8000a1e3 <- 0x70413fd +mem-write: 0x8000a1e7 <- 0xd9300 +mem-write: 0x8000a1eb <- 0xdaee6300 +mem-write: 0x8000a1ef <- 0x44483d8 +mem-write: 0x8000a1f3 <- 0x2d979300 +mem-write: 0x8000a1f7 <- 0xb787b300 +mem-write: 0x8000a1fb <- 0x17979301 +mem-write: 0x8000a1ff <- 0xd78db300 +mem-write: 0x8000a203 <- 0x4869300 +mem-write: 0x8000a207 <- 0x140413fd +mem-write: 0x8000a20b <- 0xdaf2e300 +mem-write: 0x8000a20f <- 0x8ff06ffe +mem-write: 0x8000a213 <- 0xb00793d7 +mem-write: 0x8000a217 <- 0x4448302 +mem-write: 0x8000a21b <- 0xf103a300 +mem-write: 0x8000a21f <- 0x4ff06f0c +mem-write: 0x8000a223 <- 0xc8893d6 +mem-write: 0x8000a227 <- 0xa6a1300 +mem-write: 0x8000a22b <- 0xa779301 +mem-write: 0x8000a22f <- 0x7806302 +mem-write: 0x8000a233 <- 0x4127837a +mem-write: 0x8000a237 <- 0x778b1301 +mem-write: 0x8000a23b <- 0x8b7b1300 +mem-write: 0x8000a23f <- 0x4b2783ff +mem-write: 0x8000a243 <- 0xb290300 +mem-write: 0x8000a247 <- 0x8b071300 +mem-write: 0x8000a24b <- 0xe12a2300 +mem-write: 0x8000a24f <- 0x78c9300 +mem-write: 0x8000a253 <- 0x7c66300 +mem-write: 0x8000a257 <- 0xf007937a +mem-write: 0x8000a25b <- 0xa0b93ff +mem-write: 0x8000a25f <- 0xfd846300 +mem-write: 0x8000a263 <- 0x9967b302 +mem-write: 0x8000a267 <- 0xfa7b9301 +mem-write: 0x8000a26b <- 0x79e63f7 +mem-write: 0x8000a26f <- 0xd926300 +mem-write: 0x8000a273 <- 0xb8a1302 +mem-write: 0x8000a277 <- 0xd9300 +mem-write: 0x8000a27b <- 0xc9300 +mem-write: 0x8000a27f <- 0x10b1300 +mem-write: 0x8000a283 <- 0x5ff06f1b +mem-write: 0x8000a287 <- 0xc96e3e4 +mem-write: 0x8000a28b <- 0x90079340 +mem-write: 0x8000a28f <- 0x27e2e300 +mem-write: 0x8000a293 <- 0x9091341 +mem-write: 0x8000a297 <- 0x2107a303 +mem-write: 0x8000a29b <- 0xb8a131b +mem-write: 0x8000a29f <- 0x100c9300 +mem-write: 0x8000a2a3 <- 0xf10b1300 +mem-write: 0x8000a2a7 <- 0x1ff06f1a +mem-write: 0x8000a2ab <- 0xa0b93e2 +mem-write: 0x8000a2af <- 0x10071300 +mem-write: 0x8000a2b3 <- 0xe78ae300 +mem-write: 0x8000a2b7 <- 0x200713fc +mem-write: 0x8000a2bb <- 0xe78c6300 +mem-write: 0x8000a2bf <- 0x10b1306 +mem-write: 0x8000a2c3 <- 0xdc97131b +mem-write: 0x8000a2c7 <- 0x79779301 +mem-write: 0x8000a2cb <- 0x39591300 +mem-write: 0x8000a2cf <- 0x7879300 +mem-write: 0x8000a2d3 <- 0x27693303 +mem-write: 0x8000a2d7 <- 0x3cdc9301 +mem-write: 0x8000a2db <- 0xfb0fa300 +mem-write: 0x8000a2df <- 0x996733fe +mem-write: 0x8000a2e3 <- 0xb061301 +mem-write: 0x8000a2e7 <- 0xfb0b1300 +mem-write: 0x8000a2eb <- 0x71ce3ff +mem-write: 0x8000a2ef <- 0x1bf693fc +mem-write: 0x8000a2f3 <- 0x68a6300 +mem-write: 0x8000a2f7 <- 0x69306 +mem-write: 0x8000a2fb <- 0xd7866303 +mem-write: 0x8000a2ff <- 0xe6061306 +mem-write: 0x8000a303 <- 0x10793ff +mem-write: 0x8000a307 <- 0xdb0fa31b +mem-write: 0x8000a30b <- 0xc78cb3fe +mem-write: 0x8000a30f <- 0xb8a1340 +mem-write: 0x8000a313 <- 0x60b1300 +mem-write: 0x8000a317 <- 0x1ff06f00 +mem-write: 0x8000a31b <- 0x100713db +mem-write: 0x8000a31f <- 0xe7946300 +mem-write: 0x8000a323 <- 0x10106f00 +mem-write: 0x8000a327 <- 0x20071317 +mem-write: 0x8000a32b <- 0xa0b9300 +mem-write: 0x8000a32f <- 0xe798e300 +mem-write: 0x8000a333 <- 0x412683f8 +mem-write: 0x8000a337 <- 0x10b1303 +mem-write: 0x8000a33b <- 0xf977931b +mem-write: 0x8000a33f <- 0xf687b300 +mem-write: 0x8000a343 <- 0x7c70300 +mem-write: 0x8000a347 <- 0x49591300 +mem-write: 0x8000a34b <- 0xcc979300 +mem-write: 0x8000a34f <- 0x27e93301 +mem-write: 0x8000a353 <- 0x4cdc9301 +mem-write: 0x8000a357 <- 0xeb0fa300 +mem-write: 0x8000a35b <- 0x9967b3fe +mem-write: 0x8000a35f <- 0xfb0b1301 +mem-write: 0x8000a363 <- 0x79ce3ff +mem-write: 0x8000a367 <- 0x10793fc +mem-write: 0x8000a36b <- 0x678cb31b +mem-write: 0x8000a36f <- 0xb8a1341 +mem-write: 0x8000a373 <- 0x5ff06f00 +mem-write: 0x8000a377 <- 0x500693d5 +mem-write: 0x8000a37b <- 0x96dae306 +mem-write: 0x8000a37f <- 0x126839c +mem-write: 0x8000a383 <- 0x105930f +mem-write: 0x8000a387 <- 0x105130a +mem-write: 0x8000a38b <- 0xd128230b +mem-write: 0x8000a38f <- 0x4126830a +mem-write: 0x8000a393 <- 0x1122230f +mem-write: 0x8000a397 <- 0xf1202305 +mem-write: 0x8000a39b <- 0xd12a2304 +mem-write: 0x8000a39f <- 0x8126830a +mem-write: 0x8000a3a3 <- 0x120230f +mem-write: 0x8000a3a7 <- 0x122230a +mem-write: 0x8000a3ab <- 0xd12c230a +mem-write: 0x8000a3af <- 0xc126830a +mem-write: 0x8000a3b3 <- 0x124230f +mem-write: 0x8000a3b7 <- 0x126230a +mem-write: 0x8000a3bb <- 0xd12e230a +mem-write: 0x8000a3bf <- 0x70ef0a +mem-write: 0x8000a3c3 <- 0x1278351 +mem-write: 0x8000a3c7 <- 0x41288304 +mem-write: 0x8000a3cb <- 0x51c6304 +mem-write: 0x8000a3cf <- 0x81270338 +mem-write: 0x8000a3d3 <- 0x156b70e +mem-write: 0x8000a3d7 <- 0x6869380 +mem-write: 0x8000a3db <- 0xd8a02398 +mem-write: 0x8000a3df <- 0x17879300 +mem-write: 0x8000a3e3 <- 0x10069300 +mem-write: 0x8000a3e7 <- 0x17071300 +mem-write: 0x8000a3eb <- 0xd8a22300 +mem-write: 0x8000a3ef <- 0xf1262300 +mem-write: 0x8000a3f3 <- 0xe124230e +mem-write: 0x8000a3f7 <- 0x7006930e +VXDRV: upload 1024 bytes to 0x8000a3fb +mem-write: 0x8000a3fb <- 0x88889300 +mem-write: 0x8000a3ff <- 0xe6cce300 +mem-write: 0x8000a403 <- 0xc1270344 +mem-write: 0x8000a407 <- 0x126830c +mem-write: 0x8000a40b <- 0xd7506302 +mem-write: 0x8000a40f <- 0x1270366 +mem-write: 0x8000a413 <- 0xc1268303 +mem-write: 0x8000a417 <- 0x88889302 +mem-write: 0x8000a41b <- 0xe8ac2300 +mem-write: 0x8000a41f <- 0x812703fe +mem-write: 0x8000a423 <- 0xd787b30e +mem-write: 0x8000a427 <- 0xd8ae2300 +mem-write: 0x8000a42b <- 0x170713fe +mem-write: 0x8000a42f <- 0xf1262300 +mem-write: 0x8000a433 <- 0xe124230e +mem-write: 0x8000a437 <- 0x7006930e +mem-write: 0x8000a43b <- 0xe6cc6300 +mem-write: 0x8000a43f <- 0x1270376 +mem-write: 0x8000a443 <- 0xf7049302 +mem-write: 0x8000a447 <- 0x905463ff +mem-write: 0x8000a44b <- 0x693c8 +mem-write: 0x8000a44f <- 0x81270301 +mem-write: 0x8000a453 <- 0x96d2e30e +mem-write: 0x8000a457 <- 0x91342 +mem-write: 0x8000a45b <- 0x700c9301 +mem-write: 0x8000a45f <- 0xc0006f00 +mem-write: 0x8000a463 <- 0x4849300 +mem-write: 0x8000a467 <- 0x9958e3ff +mem-write: 0x8000a46b <- 0x81268340 +mem-write: 0x8000a46f <- 0x7879300 +mem-write: 0x8000a473 <- 0x17071301 +mem-write: 0x8000a477 <- 0xd8a02300 +mem-write: 0x8000a47b <- 0x28a22300 +mem-write: 0x8000a47f <- 0xf1262301 +mem-write: 0x8000a483 <- 0xe124230e +mem-write: 0x8000a487 <- 0x8888930e +mem-write: 0x8000a48b <- 0xecdce300 +mem-write: 0x8000a48f <- 0x410613fc +mem-write: 0x8000a493 <- 0xc05930e +mem-write: 0x8000a497 <- 0xd051300 +mem-write: 0x8000a49b <- 0x40ef00 +mem-write: 0x8000a49f <- 0x510636c +mem-write: 0x8000a4a3 <- 0xc127831a +mem-write: 0x8000a4a7 <- 0x8127030e +mem-write: 0x8000a4ab <- 0xc108930e +mem-write: 0x8000a4af <- 0x5ff06f10 +mem-write: 0x8000a4b3 <- 0x598933fb +mem-write: 0x8000a4b7 <- 0x20506341 +mem-write: 0x8000a4bb <- 0x613bf +mem-write: 0x8000a4bf <- 0x81268301 +mem-write: 0x8000a4c3 <- 0x2654630e +mem-write: 0x8000a4c7 <- 0xe1307 +mem-write: 0x8000a4cb <- 0x700b9301 +mem-write: 0x8000a4cf <- 0xc0006f00 +mem-write: 0x8000a4d3 <- 0x9091300 +mem-write: 0x8000a4d7 <- 0x2e5a63ff +mem-write: 0x8000a4db <- 0x81270305 +mem-write: 0x8000a4df <- 0x7879300 +mem-write: 0x8000a4e3 <- 0x16869301 +mem-write: 0x8000a4e7 <- 0xe8a02300 +mem-write: 0x8000a4eb <- 0xc8a22300 +mem-write: 0x8000a4ef <- 0xf1262301 +mem-write: 0x8000a4f3 <- 0xd124230e +mem-write: 0x8000a4f7 <- 0x8888930e +mem-write: 0x8000a4fb <- 0xdbdce300 +mem-write: 0x8000a4ff <- 0x410613fc +mem-write: 0x8000a503 <- 0xc05930e +mem-write: 0x8000a507 <- 0xd051300 +mem-write: 0x8000a50b <- 0x40ef00 +mem-write: 0x8000a50f <- 0x5186365 +mem-write: 0x8000a513 <- 0xe1312 +mem-write: 0x8000a517 <- 0x9091301 +mem-write: 0x8000a51b <- 0xc12783ff +mem-write: 0x8000a51f <- 0x8126830e +mem-write: 0x8000a523 <- 0xc108930e +mem-write: 0x8000a527 <- 0x2e4ae310 +mem-write: 0x8000a52b <- 0x812703fb +mem-write: 0x8000a52f <- 0x2787b300 +mem-write: 0x8000a533 <- 0x16869301 +mem-write: 0x8000a537 <- 0xe8a02300 +mem-write: 0x8000a53b <- 0x28a22300 +mem-write: 0x8000a53f <- 0xf1262301 +mem-write: 0x8000a543 <- 0xd124230e +mem-write: 0x8000a547 <- 0x7006130e +mem-write: 0x8000a54b <- 0x88889300 +mem-write: 0x8000a54f <- 0xd6546300 +mem-write: 0x8000a553 <- 0x410613b4 +mem-write: 0x8000a557 <- 0xc05930e +mem-write: 0x8000a55b <- 0xd051300 +mem-write: 0x8000a55f <- 0xc040ef00 +mem-write: 0x8000a563 <- 0x51e635f +mem-write: 0x8000a567 <- 0x9d8db30c +mem-write: 0x8000a56b <- 0xc1278341 +mem-write: 0x8000a56f <- 0xc108930e +mem-write: 0x8000a573 <- 0xb0566310 +mem-write: 0x8000a577 <- 0x613b3 +mem-write: 0x8000a57b <- 0x81268301 +mem-write: 0x8000a57f <- 0xb652630e +mem-write: 0x8000a583 <- 0xb9307 +mem-write: 0x8000a587 <- 0x70091301 +mem-write: 0x8000a58b <- 0xc0006f00 +mem-write: 0x8000a58f <- 0xd8d9300 +mem-write: 0x8000a593 <- 0xbbd863ff +mem-write: 0x8000a597 <- 0x81270305 +mem-write: 0x8000a59b <- 0x7879300 +mem-write: 0x8000a59f <- 0x16869301 +mem-write: 0x8000a5a3 <- 0xe8a02300 +mem-write: 0x8000a5a7 <- 0x78a22300 +mem-write: 0x8000a5ab <- 0xf1262301 +mem-write: 0x8000a5af <- 0xd124230e +mem-write: 0x8000a5b3 <- 0x8888930e +mem-write: 0x8000a5b7 <- 0xd95ce300 +mem-write: 0x8000a5bb <- 0x410613fc +mem-write: 0x8000a5bf <- 0xc05930e +mem-write: 0x8000a5c3 <- 0xd051300 +mem-write: 0x8000a5c7 <- 0x4040ef00 +mem-write: 0x8000a5cb <- 0x51a6359 +mem-write: 0x8000a5cf <- 0xd8d9306 +mem-write: 0x8000a5d3 <- 0xc12783ff +mem-write: 0x8000a5d7 <- 0x8126830e +mem-write: 0x8000a5db <- 0xc108930e +mem-write: 0x8000a5df <- 0xbbcce310 +mem-write: 0x8000a5e3 <- 0x812703fb +mem-write: 0x8000a5e7 <- 0xb787b300 +mem-write: 0x8000a5eb <- 0x16869301 +mem-write: 0x8000a5ef <- 0xe8a02300 +mem-write: 0x8000a5f3 <- 0xb8a22300 +mem-write: 0x8000a5f7 <- 0xf1262301 +mem-write: 0x8000a5fb <- 0xd124230e +mem-write: 0x8000a5ff <- 0x7006130e +mem-write: 0x8000a603 <- 0x88889300 +mem-write: 0x8000a607 <- 0xd65c6300 +mem-write: 0x8000a60b <- 0x410613a8 +mem-write: 0x8000a60f <- 0xc05930e +mem-write: 0x8000a613 <- 0xd051300 +mem-write: 0x8000a617 <- 0x4040ef00 +mem-write: 0x8000a61b <- 0x5126354 +mem-write: 0x8000a61f <- 0xc1278302 +mem-write: 0x8000a623 <- 0xc108930e +mem-write: 0x8000a627 <- 0x8ff06f10 +mem-write: 0x8000a62b <- 0x410613a7 +mem-write: 0x8000a62f <- 0xc05930e +mem-write: 0x8000a633 <- 0xd051300 +mem-write: 0x8000a637 <- 0x4040ef00 +mem-write: 0x8000a63b <- 0x50e6352 +mem-write: 0x8000a63f <- 0x12b83aa +mem-write: 0x8000a643 <- 0xb846301 +mem-write: 0x8000a647 <- 0xb8593ae +mem-write: 0x8000a64b <- 0xd051300 +mem-write: 0x8000a64f <- 0x5f90ef00 +mem-write: 0x8000a653 <- 0x8ff06ff1 +mem-write: 0x8000a657 <- 0x15737ad +mem-write: 0x8000a65b <- 0x61380 +mem-write: 0x8000a65f <- 0x81268301 +mem-write: 0x8000a663 <- 0x470e930e +mem-write: 0x8000a667 <- 0x65c6317 +mem-write: 0x8000a66b <- 0x81202309 +mem-write: 0x8000a66f <- 0x91222304 +mem-write: 0x8000a673 <- 0xd041304 +mem-write: 0x8000a677 <- 0xc049300 +mem-write: 0x8000a67b <- 0xe1300 +mem-write: 0x8000a67f <- 0x70029301 +mem-write: 0x8000a683 <- 0x80c1300 +mem-write: 0x8000a687 <- 0xe8d1300 +mem-write: 0x8000a68b <- 0xc0006f00 +mem-write: 0x8000a68f <- 0xc0c1300 +mem-write: 0x8000a693 <- 0x8e5a63ff +mem-write: 0x8000a697 <- 0x7879305 +mem-write: 0x8000a69b <- 0x16869301 +mem-write: 0x8000a69f <- 0xa8a02300 +mem-write: 0x8000a6a3 <- 0xc8a22301 +mem-write: 0x8000a6a7 <- 0xf1262301 +mem-write: 0x8000a6ab <- 0xd124230e +mem-write: 0x8000a6af <- 0x8888930e +mem-write: 0x8000a6b3 <- 0xd2dee300 +mem-write: 0x8000a6b7 <- 0x410613fc +mem-write: 0x8000a6bb <- 0x485930e +mem-write: 0x8000a6bf <- 0x4051300 +mem-write: 0x8000a6c3 <- 0x8040ef00 +mem-write: 0x8000a6c7 <- 0x512e349 +mem-write: 0x8000a6cb <- 0xe1316 +mem-write: 0x8000a6cf <- 0xc0c1301 +mem-write: 0x8000a6d3 <- 0xc12783ff +mem-write: 0x8000a6d7 <- 0x8126830e +mem-write: 0x8000a6db <- 0xc108930e +mem-write: 0x8000a6df <- 0x70029310 +mem-write: 0x8000a6e3 <- 0x8e4ae300 +mem-write: 0x8000a6e7 <- 0xc0813fb +mem-write: 0x8000a6eb <- 0xd0e9300 +mem-write: 0x8000a6ef <- 0x48c1300 +mem-write: 0x8000a6f3 <- 0x40d1300 +mem-write: 0x8000a6f7 <- 0x41248300 +mem-write: 0x8000a6fb <- 0x1240304 +mem-write: 0x8000a6ff <- 0x787b304 +mem-write: 0x8000a703 <- 0x16869301 +mem-write: 0x8000a707 <- 0xd8a02300 +mem-write: 0x8000a70b <- 0x8a22301 +mem-write: 0x8000a70f <- 0xf1262301 +mem-write: 0x8000a713 <- 0xd124230e +mem-write: 0x8000a717 <- 0x7006130e +mem-write: 0x8000a71b <- 0x88889300 +mem-write: 0x8000a71f <- 0xd6526300 +mem-write: 0x8000a723 <- 0x41061390 +mem-write: 0x8000a727 <- 0xc05930e +mem-write: 0x8000a72b <- 0xd051300 +mem-write: 0x8000a72f <- 0xc040ef00 +mem-write: 0x8000a733 <- 0x516e342 +mem-write: 0x8000a737 <- 0xc12783f0 +mem-write: 0x8000a73b <- 0xc108930e +mem-write: 0x8000a73f <- 0x4ff06f10 +mem-write: 0x8000a743 <- 0x4106138e +mem-write: 0x8000a747 <- 0xc05930e +mem-write: 0x8000a74b <- 0xd051300 +mem-write: 0x8000a74f <- 0xc040ef00 +mem-write: 0x8000a753 <- 0x516e340 +mem-write: 0x8000a757 <- 0xc12783ee +mem-write: 0x8000a75b <- 0xc108930e +mem-write: 0x8000a75f <- 0xff06f10 +mem-write: 0x8000a763 <- 0xc1258393 +mem-write: 0x8000a767 <- 0xb05c630c +mem-write: 0x8000a76b <- 0xc127037e +mem-write: 0x8000a76f <- 0x1268301 +mem-write: 0x8000a773 <- 0x7049302 +mem-write: 0x8000a777 <- 0xe6c26300 +mem-write: 0x8000a77b <- 0x9056633c +mem-write: 0x8000a77f <- 0x81268302 +mem-write: 0x8000a783 <- 0x9787b30e +mem-write: 0x8000a787 <- 0x68a02300 +mem-write: 0x8000a78b <- 0x16869301 +mem-write: 0x8000a78f <- 0x98a22300 +mem-write: 0x8000a793 <- 0xf1262300 +mem-write: 0x8000a797 <- 0xd124230e +mem-write: 0x8000a79b <- 0x7006130e +mem-write: 0x8000a79f <- 0x88889300 +mem-write: 0x8000a7a3 <- 0xd64ce300 +mem-write: 0x8000a7a7 <- 0xf4c69340 +mem-write: 0x8000a7ab <- 0xc12703ff +mem-write: 0x8000a7af <- 0xf6d69301 +mem-write: 0x8000a7b3 <- 0xd4f4b341 +mem-write: 0x8000a7b7 <- 0x9704b300 +mem-write: 0x8000a7bb <- 0x904e6340 +mem-write: 0x8000a7bf <- 0xc1270348 +mem-write: 0x8000a7c3 <- 0xa769301 +mem-write: 0x8000a7c7 <- 0xeb0db340 +mem-write: 0x8000a7cb <- 0x69a6300 +mem-write: 0x8000a7cf <- 0xc124834e +mem-write: 0x8000a7d3 <- 0x127030c +mem-write: 0x8000a7d7 <- 0xe4c66302 +mem-write: 0x8000a7db <- 0x1a769300 +mem-write: 0x8000a7df <- 0x682e300 +mem-write: 0x8000a7e3 <- 0x1268340 +mem-write: 0x8000a7e7 <- 0xc1270303 +mem-write: 0x8000a7eb <- 0x70061302 +mem-write: 0x8000a7ef <- 0xd8a02300 +mem-write: 0x8000a7f3 <- 0x81268300 +mem-write: 0x8000a7f7 <- 0xe787b30e +VXDRV: upload 1024 bytes to 0x8000a7fb +mem-write: 0x8000a7fb <- 0xe8a22300 +mem-write: 0x8000a7ff <- 0x16869300 +mem-write: 0x8000a803 <- 0xf1262300 +mem-write: 0x8000a807 <- 0xd124230e +mem-write: 0x8000a80b <- 0x8888930e +mem-write: 0x8000a80f <- 0xd644e300 +mem-write: 0x8000a813 <- 0x126836a +mem-write: 0x8000a817 <- 0xdb073302 +mem-write: 0x8000a81b <- 0x9684b300 +mem-write: 0x8000a81f <- 0xb7073340 +mem-write: 0x8000a823 <- 0x4891341 +mem-write: 0x8000a827 <- 0x97546300 +mem-write: 0x8000a82b <- 0x7091300 +mem-write: 0x8000a82f <- 0x20566300 +mem-write: 0x8000a833 <- 0x81270303 +mem-write: 0x8000a837 <- 0x2787b30e +mem-write: 0x8000a83b <- 0xb8a02301 +mem-write: 0x8000a83f <- 0x17071301 +mem-write: 0x8000a843 <- 0x28a22300 +mem-write: 0x8000a847 <- 0xf1262301 +mem-write: 0x8000a84b <- 0xe124230e +mem-write: 0x8000a84f <- 0x7006930e +mem-write: 0x8000a853 <- 0x88889300 +mem-write: 0x8000a857 <- 0xe6cae300 +mem-write: 0x8000a85b <- 0xf947136a +mem-write: 0x8000a85f <- 0xf75713ff +mem-write: 0x8000a863 <- 0xe9773341 +mem-write: 0x8000a867 <- 0xe484b300 +mem-write: 0x8000a86b <- 0x90446340 +mem-write: 0x8000a86f <- 0xff06f00 +mem-write: 0x8000a873 <- 0x69386 +mem-write: 0x8000a877 <- 0x81270301 +mem-write: 0x8000a87b <- 0x96de630e +mem-write: 0x8000a87f <- 0x9137e +mem-write: 0x8000a883 <- 0x700c9301 +mem-write: 0x8000a887 <- 0xc0006f00 +mem-write: 0x8000a88b <- 0x4849300 +mem-write: 0x8000a88f <- 0x995463ff +mem-write: 0x8000a893 <- 0x8126837e +mem-write: 0x8000a897 <- 0x7879300 +mem-write: 0x8000a89b <- 0x17071301 +mem-write: 0x8000a89f <- 0xd8a02300 +mem-write: 0x8000a8a3 <- 0x28a22300 +mem-write: 0x8000a8a7 <- 0xf1262301 +mem-write: 0x8000a8ab <- 0xe124230e +mem-write: 0x8000a8af <- 0x8888930e +mem-write: 0x8000a8b3 <- 0xecdce300 +mem-write: 0x8000a8b7 <- 0x410613fc +mem-write: 0x8000a8bb <- 0xc05930e +mem-write: 0x8000a8bf <- 0xd051300 +mem-write: 0x8000a8c3 <- 0x8040ef00 +mem-write: 0x8000a8c7 <- 0x51ce329 +mem-write: 0x8000a8cb <- 0xc12783d6 +mem-write: 0x8000a8cf <- 0x8127030e +mem-write: 0x8000a8d3 <- 0xc108930e +mem-write: 0x8000a8d7 <- 0x5ff06f10 +mem-write: 0x8000a8db <- 0x1a7793fb +mem-write: 0x8000a8df <- 0x7986300 +mem-write: 0x8000a8e3 <- 0xc8a223c8 +mem-write: 0x8000a8e7 <- 0x91262300 +mem-write: 0x8000a8eb <- 0x9124230f +mem-write: 0x8000a8ef <- 0x7007930e +mem-write: 0x8000a8f3 <- 0x97ca6300 +mem-write: 0x8000a8f7 <- 0x26869354 +mem-write: 0x8000a8fb <- 0x8889300 +mem-write: 0x8000a8ff <- 0x4ff06f01 +mem-write: 0x8000a903 <- 0xb05063d4 +mem-write: 0x8000a907 <- 0x713d5 +mem-write: 0x8000a90b <- 0xb7446301 +mem-write: 0x8000a90f <- 0x80106f01 +mem-write: 0x8000a913 <- 0x700b136b +mem-write: 0x8000a917 <- 0x6049300 +mem-write: 0x8000a91b <- 0x6f00 +mem-write: 0x8000a91f <- 0xd8d9301 +mem-write: 0x8000a923 <- 0xb75ee3ff +mem-write: 0x8000a927 <- 0x14849311 +mem-write: 0x8000a92b <- 0x81278300 +mem-write: 0x8000a92f <- 0xc8c9300 +mem-write: 0x8000a933 <- 0xe9222301 +mem-write: 0x8000a937 <- 0xf9202300 +mem-write: 0x8000a93b <- 0x91262300 +mem-write: 0x8000a93f <- 0x9124230f +mem-write: 0x8000a943 <- 0x8909130e +mem-write: 0x8000a947 <- 0x9b5ce300 +mem-write: 0x8000a94b <- 0x410613fc +mem-write: 0x8000a94f <- 0xc05930e +mem-write: 0x8000a953 <- 0xd051300 +mem-write: 0x8000a957 <- 0x4040ef00 +mem-write: 0x8000a95b <- 0x512e320 +mem-write: 0x8000a95f <- 0xc12c83ce +mem-write: 0x8000a963 <- 0x8124830e +mem-write: 0x8000a967 <- 0xc109130e +mem-write: 0x8000a96b <- 0x71310 +mem-write: 0x8000a96f <- 0x1ff06f01 +mem-write: 0x8000a973 <- 0x412683fb +mem-write: 0x8000a977 <- 0xa779301 +mem-write: 0x8000a97b <- 0x46871301 +mem-write: 0x8000a97f <- 0x7946300 +mem-write: 0x8000a983 <- 0xa779318 +mem-write: 0x8000a987 <- 0x786e304 +mem-write: 0x8000a98b <- 0x41278314 +mem-write: 0x8000a98f <- 0xc9301 +mem-write: 0x8000a993 <- 0xe12a2300 +mem-write: 0x8000a997 <- 0x7d90300 +mem-write: 0x8000a99b <- 0xff06f00 +mem-write: 0x8000a99f <- 0x412683f8 +mem-write: 0x8000a9a3 <- 0xbf79301 +mem-write: 0x8000a9a7 <- 0x46871301 +mem-write: 0x8000a9ab <- 0x7946300 +mem-write: 0x8000a9af <- 0xbf79314 +mem-write: 0x8000a9b3 <- 0x780e304 +mem-write: 0x8000a9b7 <- 0x41278310 +mem-write: 0x8000a9bb <- 0xc9301 +mem-write: 0x8000a9bf <- 0xe12a2300 +mem-write: 0x8000a9c3 <- 0x7d90300 +mem-write: 0x8000a9c7 <- 0x10079300 +mem-write: 0x8000a9cb <- 0xff06f00 +mem-write: 0x8000a9cf <- 0x412683ed +mem-write: 0x8000a9d3 <- 0xa779301 +mem-write: 0x8000a9d7 <- 0x46871301 +mem-write: 0x8000a9db <- 0x7926300 +mem-write: 0x8000a9df <- 0xa779310 +mem-write: 0x8000a9e3 <- 0x788e304 +mem-write: 0x8000a9e7 <- 0x4127830a +mem-write: 0x8000a9eb <- 0xe12a2301 +mem-write: 0x8000a9ef <- 0x7990300 +mem-write: 0x8000a9f3 <- 0xf95c9300 +mem-write: 0x8000a9f7 <- 0xc879341 +mem-write: 0x8000a9fb <- 0x7dee300 +mem-write: 0x8000a9ff <- 0x2037b384 +mem-write: 0x8000aa03 <- 0x900cb301 +mem-write: 0x8000aa07 <- 0xfc8cb341 +mem-write: 0x8000aa0b <- 0xd0079340 +mem-write: 0x8000aa0f <- 0xf103a302 +mem-write: 0x8000aa13 <- 0x2009330c +mem-write: 0x8000aa17 <- 0xa0b9341 +mem-write: 0x8000aa1b <- 0x10079300 +mem-write: 0x8000aa1f <- 0xff06f00 +mem-write: 0x8000aa23 <- 0x410613e8 +mem-write: 0x8000aa27 <- 0xc05930e +mem-write: 0x8000aa2b <- 0xd051300 +mem-write: 0x8000aa2f <- 0xc040ef00 +mem-write: 0x8000aa33 <- 0x516e312 +mem-write: 0x8000aa37 <- 0xc12c83c0 +mem-write: 0x8000aa3b <- 0x8124830e +mem-write: 0x8000aa3f <- 0xc109130e +mem-write: 0x8000aa43 <- 0x4ff06f10 +mem-write: 0x8000aa47 <- 0x410613b4 +mem-write: 0x8000aa4b <- 0xc05930e +mem-write: 0x8000aa4f <- 0xd051300 +mem-write: 0x8000aa53 <- 0x8040ef00 +mem-write: 0x8000aa57 <- 0x514e310 +mem-write: 0x8000aa5b <- 0xc12c83be +mem-write: 0x8000aa5f <- 0x8124830e +mem-write: 0x8000aa63 <- 0xc109130e +mem-write: 0x8000aa67 <- 0xcff06f10 +mem-write: 0x8000aa6b <- 0x1a7713b4 +mem-write: 0x8000aa6f <- 0x7146300 +mem-write: 0x8000aa73 <- 0xdfe06f00 +mem-write: 0x8000aa77 <- 0x9ff06fe5 +mem-write: 0x8000aa7b <- 0xc889399 +mem-write: 0x8000aa7f <- 0xcff06f00 +mem-write: 0x8000aa83 <- 0x793fa +mem-write: 0x8000aa87 <- 0xf107a303 +mem-write: 0x8000aa8b <- 0xf10b131a +mem-write: 0x8000aa8f <- 0x8ff06f1a +mem-write: 0x8000aa93 <- 0xc12683e3 +mem-write: 0x8000aa97 <- 0x40b1300 +mem-write: 0x8000aa9b <- 0xf6d79300 +mem-write: 0x8000aa9f <- 0xd7202341 +mem-write: 0x8000aaa3 <- 0xf7222300 +mem-write: 0x8000aaa7 <- 0x1fe06f00 +mem-write: 0x8000aaab <- 0x412703e7 +mem-write: 0x8000aaaf <- 0x7278301 +mem-write: 0x8000aab3 <- 0x47071300 +mem-write: 0x8000aab7 <- 0xe12a2300 +mem-write: 0x8000aabb <- 0x7a58300 +mem-write: 0x8000aabf <- 0x47a60300 +mem-write: 0x8000aac3 <- 0x87a68300 +mem-write: 0x8000aac7 <- 0xc7a78300 +mem-write: 0x8000aacb <- 0xb1282300 +mem-write: 0x8000aacf <- 0xc12a230e +mem-write: 0x8000aad3 <- 0xd12c230e +mem-write: 0x8000aad7 <- 0xf12e230e +mem-write: 0x8000aadb <- 0x9fe06f0e +mem-write: 0x8000aadf <- 0x6a903f7 +mem-write: 0x8000aae3 <- 0xe12a2300 +mem-write: 0x8000aae7 <- 0xf95c9300 +mem-write: 0x8000aaeb <- 0xc879341 +mem-write: 0x8000aaef <- 0x4ff06f00 +mem-write: 0x8000aaf3 <- 0x6a903f6 +mem-write: 0x8000aaf7 <- 0xc9300 +mem-write: 0x8000aafb <- 0xe12a2300 +mem-write: 0x8000aaff <- 0x10079300 +mem-write: 0x8000ab03 <- 0x8ff06f00 +mem-write: 0x8000ab07 <- 0x6a903d9 +mem-write: 0x8000ab0b <- 0xc9300 +mem-write: 0x8000ab0f <- 0xe12a2300 +mem-write: 0x8000ab13 <- 0x8ff06f00 +mem-write: 0x8000ab17 <- 0xc12783e0 +mem-write: 0x8000ab1b <- 0x4448303 +mem-write: 0x8000ab1f <- 0x7946300 +mem-write: 0x8000ab23 <- 0x1fe06f00 +mem-write: 0x8000ab27 <- 0x7c783c6 +mem-write: 0x8000ab2b <- 0x7946300 +mem-write: 0x8000ab2f <- 0x5fe06f00 +mem-write: 0x8000ab33 <- 0xa6a13c5 +mem-write: 0x8000ab37 <- 0xdfe06f40 +mem-write: 0x8000ab3b <- 0x68493c4 +mem-write: 0x8000ab3f <- 0x9040e300 +mem-write: 0x8000ab43 <- 0x5ff06fc4 +mem-write: 0x8000ab47 <- 0xc8893c6 +mem-write: 0x8000ab4b <- 0xa0b9300 +mem-write: 0x8000ab4f <- 0x4ff06f00 +mem-write: 0x8000ab53 <- 0x157b7df +mem-write: 0x8000ab57 <- 0xc7879380 +mem-write: 0x8000ab5b <- 0xc8893a3 +mem-write: 0x8000ab5f <- 0xf12a2300 +mem-write: 0x8000ab63 <- 0xa779302 +mem-write: 0x8000ab67 <- 0x7806302 +mem-write: 0x8000ab6b <- 0x4127832c +mem-write: 0x8000ab6f <- 0x778b1301 +mem-write: 0x8000ab73 <- 0x8b7b1300 +mem-write: 0x8000ab77 <- 0xb2903ff +mem-write: 0x8000ab7b <- 0x4b2c8300 +mem-write: 0x8000ab7f <- 0x8b079300 +mem-write: 0x8000ab83 <- 0xf12a2300 +mem-write: 0x8000ab87 <- 0x1a779300 +mem-write: 0x8000ab8b <- 0x78e6300 +mem-write: 0x8000ab8f <- 0x9967b300 +mem-write: 0x8000ab93 <- 0x78a6301 +mem-write: 0x8000ab97 <- 0x79300 +mem-write: 0x8000ab9b <- 0xf1042303 +mem-write: 0x8000ab9f <- 0x9104a30c +mem-write: 0x8000aba3 <- 0x2a6a130c +mem-write: 0x8000aba7 <- 0xfa7b9300 +mem-write: 0x8000abab <- 0x200793bf +mem-write: 0x8000abaf <- 0xcff06f00 +mem-write: 0x8000abb3 <- 0x410613ce +mem-write: 0x8000abb7 <- 0xc05930e +mem-write: 0x8000abbb <- 0xd051300 +mem-write: 0x8000abbf <- 0xd030ef00 +mem-write: 0x8000abc3 <- 0x51ee379 +mem-write: 0x8000abc7 <- 0xc12783a6 +mem-write: 0x8000abcb <- 0xc108930e +mem-write: 0x8000abcf <- 0x1ff06f10 +mem-write: 0x8000abd3 <- 0x157b787 +mem-write: 0x8000abd7 <- 0x7879380 +mem-write: 0x8000abdb <- 0xc8893a5 +mem-write: 0x8000abdf <- 0xf12a2300 +mem-write: 0x8000abe3 <- 0x1ff06f02 +mem-write: 0x8000abe7 <- 0xc8893f8 +mem-write: 0x8000abeb <- 0xcff06f00 +mem-write: 0x8000abef <- 0x144483d0 +mem-write: 0x8000abf3 <- 0xa6a1300 +mem-write: 0x8000abf7 <- 0x14041302 +VXDRV: upload 1024 bytes to 0x8000abfb +mem-write: 0x8000abfb <- 0x9fe06f00 +mem-write: 0x8000abff <- 0x144483b8 +mem-write: 0x8000ac03 <- 0xa6a1300 +mem-write: 0x8000ac07 <- 0x14041320 +mem-write: 0x8000ac0b <- 0x9fe06f00 +mem-write: 0x8000ac0f <- 0x593b7 +mem-write: 0x8000ac13 <- 0xd051304 +mem-write: 0x8000ac17 <- 0x1fc0ef00 +mem-write: 0x8000ac1b <- 0xac2023b2 +mem-write: 0x8000ac1f <- 0xac282300 +mem-write: 0x8000ac23 <- 0x5146300 +mem-write: 0x8000ac27 <- 0xc0106f00 +mem-write: 0x8000ac2b <- 0x7133c +mem-write: 0x8000ac2f <- 0xec2a2304 +mem-write: 0x8000ac33 <- 0x5fe06f00 +mem-write: 0x8000ac37 <- 0x600793a7 +mem-write: 0x8000ac3b <- 0xd8c9300 +mem-write: 0x8000ac3f <- 0xb7ee6300 +mem-write: 0x8000ac43 <- 0x1573779 +mem-write: 0x8000ac47 <- 0xc8a9380 +mem-write: 0x8000ac4b <- 0x212a2300 +mem-write: 0x8000ac4f <- 0x470b1301 +mem-write: 0x8000ac53 <- 0xdfe06fa6 +mem-write: 0x8000ac57 <- 0x613b9 +mem-write: 0x8000ac5b <- 0x81268301 +mem-write: 0x8000ac5f <- 0x9658630e +mem-write: 0x8000ac63 <- 0xc936a +mem-write: 0x8000ac67 <- 0x700d9301 +mem-write: 0x8000ac6b <- 0xc0006f00 +mem-write: 0x8000ac6f <- 0x4849300 +mem-write: 0x8000ac73 <- 0x9cde63ff +mem-write: 0x8000ac77 <- 0x81270368 +mem-write: 0x8000ac7b <- 0x7879300 +mem-write: 0x8000ac7f <- 0x16869301 +mem-write: 0x8000ac83 <- 0xe8a02300 +mem-write: 0x8000ac87 <- 0x98a22300 +mem-write: 0x8000ac8b <- 0xf1262301 +mem-write: 0x8000ac8f <- 0xd124230e +mem-write: 0x8000ac93 <- 0x8888930e +mem-write: 0x8000ac97 <- 0xdddce300 +mem-write: 0x8000ac9b <- 0x410613fc +mem-write: 0x8000ac9f <- 0xc05930e +mem-write: 0x8000aca3 <- 0xd051300 +mem-write: 0x8000aca7 <- 0x5030ef00 +mem-write: 0x8000acab <- 0x51ae36b +mem-write: 0x8000acaf <- 0xc1278398 +mem-write: 0x8000acb3 <- 0x8126830e +mem-write: 0x8000acb7 <- 0xc108930e +mem-write: 0x8000acbb <- 0x5ff06f10 +mem-write: 0x8000acbf <- 0x12703fb +mem-write: 0x8000acc3 <- 0x412c8302 +mem-write: 0x8000acc7 <- 0x412e2302 +mem-write: 0x8000accb <- 0x81202301 +mem-write: 0x8000accf <- 0x31222304 +mem-write: 0x8000acd3 <- 0x51222305 +mem-write: 0x8000acd7 <- 0x81298303 +mem-write: 0x8000acdb <- 0x61242302 +mem-write: 0x8000acdf <- 0xeb0bb303 +mem-write: 0x8000ace3 <- 0xc1240300 +mem-write: 0x8000ace7 <- 0x812a0303 +mem-write: 0x8000aceb <- 0xc12a8304 +mem-write: 0x8000acef <- 0x70049304 +mem-write: 0x8000acf3 <- 0x91300 +mem-write: 0x8000acf7 <- 0xc0b1301 +mem-write: 0x8000acfb <- 0xc886300 +mem-write: 0x8000acff <- 0x9986308 +mem-write: 0x8000ad03 <- 0xf4041308 +mem-write: 0x8000ad07 <- 0xfc8c93ff +mem-write: 0x8000ad0b <- 0x812703ff +mem-write: 0x8000ad0f <- 0x4787b30e +mem-write: 0x8000ad13 <- 0x58a02301 +mem-write: 0x8000ad17 <- 0x17071301 +mem-write: 0x8000ad1b <- 0x48a22300 +mem-write: 0x8000ad1f <- 0xf1262301 +mem-write: 0x8000ad23 <- 0xe124230e +mem-write: 0x8000ad27 <- 0x8888930e +mem-write: 0x8000ad2b <- 0xe4c46300 +mem-write: 0x8000ad2f <- 0x4468314 +mem-write: 0x8000ad33 <- 0xbb863300 +mem-write: 0x8000ad37 <- 0x68c1341 +mem-write: 0x8000ad3b <- 0xd6546300 +mem-write: 0x8000ad3f <- 0x60c1300 +mem-write: 0x8000ad43 <- 0x80566300 +mem-write: 0x8000ad47 <- 0x81268303 +mem-write: 0x8000ad4b <- 0x8787b30e +mem-write: 0x8000ad4f <- 0xb8a02301 +mem-write: 0x8000ad53 <- 0x16869301 +mem-write: 0x8000ad57 <- 0x88a22300 +mem-write: 0x8000ad5b <- 0xf1262301 +mem-write: 0x8000ad5f <- 0xd124230e +mem-write: 0x8000ad63 <- 0xd4c0630e +mem-write: 0x8000ad67 <- 0x4468334 +mem-write: 0x8000ad6b <- 0x88889300 +mem-write: 0x8000ad6f <- 0xfc461300 +mem-write: 0x8000ad73 <- 0xf65613ff +mem-write: 0x8000ad77 <- 0xcc773341 +mem-write: 0x8000ad7b <- 0xe68c3300 +mem-write: 0x8000ad7f <- 0x804c6340 +mem-write: 0x8000ad83 <- 0xdd8db301 +mem-write: 0x8000ad87 <- 0xc9ce300 +mem-write: 0x8000ad8b <- 0x98c63f6 +mem-write: 0x8000ad8f <- 0xf9899372 +mem-write: 0x8000ad93 <- 0x9ff06fff +mem-write: 0x8000ad97 <- 0x812683f7 +mem-write: 0x8000ad9b <- 0x8948630e +mem-write: 0x8000ad9f <- 0x80006f01 +mem-write: 0x8000ada3 <- 0xc0c1305 +mem-write: 0x8000ada7 <- 0x895863ff +mem-write: 0x8000adab <- 0x81270305 +mem-write: 0x8000adaf <- 0x7879300 +mem-write: 0x8000adb3 <- 0x16869301 +mem-write: 0x8000adb7 <- 0xe8a02300 +mem-write: 0x8000adbb <- 0x28a22300 +mem-write: 0x8000adbf <- 0xf1262301 +mem-write: 0x8000adc3 <- 0xd124230e +mem-write: 0x8000adc7 <- 0x8888930e +mem-write: 0x8000adcb <- 0xd4dce300 +mem-write: 0x8000adcf <- 0x410613fc +mem-write: 0x8000add3 <- 0xb05930e +mem-write: 0x8000add7 <- 0xd051300 +mem-write: 0x8000addb <- 0x1030ef00 +mem-write: 0x8000addf <- 0x51c6358 +mem-write: 0x8000ade3 <- 0xc0c135a +mem-write: 0x8000ade7 <- 0xc12783ff +mem-write: 0x8000adeb <- 0x8126830e +mem-write: 0x8000adef <- 0xc108930e +mem-write: 0x8000adf3 <- 0x894ce310 +mem-write: 0x8000adf7 <- 0x812703fb +mem-write: 0x8000adfb <- 0x8787b300 +mem-write: 0x8000adff <- 0x16869301 +mem-write: 0x8000ae03 <- 0xe8a02300 +mem-write: 0x8000ae07 <- 0x88a22300 +mem-write: 0x8000ae0b <- 0xf1262301 +mem-write: 0x8000ae0f <- 0xd124230e +mem-write: 0x8000ae13 <- 0xd4c4630e +mem-write: 0x8000ae17 <- 0x4468376 +mem-write: 0x8000ae1b <- 0x88889300 +mem-write: 0x8000ae1f <- 0xdd8db300 +mem-write: 0x8000ae23 <- 0x5ff06f00 +mem-write: 0x8000ae27 <- 0x412683f6 +mem-write: 0x8000ae2b <- 0xa779301 +mem-write: 0x8000ae2f <- 0x46871301 +mem-write: 0x8000ae33 <- 0x7846300 +mem-write: 0x8000ae37 <- 0x6a90320 +mem-write: 0x8000ae3b <- 0xc9300 +mem-write: 0x8000ae3f <- 0xe12a2300 +mem-write: 0x8000ae43 <- 0x5ff06f00 +mem-write: 0x8000ae47 <- 0x410613d4 +mem-write: 0x8000ae4b <- 0xc05930e +mem-write: 0x8000ae4f <- 0xd051300 +mem-write: 0x8000ae53 <- 0x9030ef00 +mem-write: 0x8000ae57 <- 0x5146350 +mem-write: 0x8000ae5b <- 0x812683fe +mem-write: 0x8000ae5f <- 0xc12c830e +mem-write: 0x8000ae63 <- 0x4108930e +mem-write: 0x8000ae67 <- 0x16869311 +mem-write: 0x8000ae6b <- 0xc1091300 +mem-write: 0x8000ae6f <- 0x5fe06f10 +mem-write: 0x8000ae73 <- 0x410613fd +mem-write: 0x8000ae77 <- 0xb05930e +mem-write: 0x8000ae7b <- 0xd051300 +mem-write: 0x8000ae7f <- 0xd030ef00 +mem-write: 0x8000ae83 <- 0x51a634d +mem-write: 0x8000ae87 <- 0xc1278350 +mem-write: 0x8000ae8b <- 0xc108930e +mem-write: 0x8000ae8f <- 0x1ff06f10 +mem-write: 0x8000ae93 <- 0x10b13ea +mem-write: 0x8000ae97 <- 0x7931b +mem-write: 0x8000ae9b <- 0x81282300 +mem-write: 0x8000ae9f <- 0x912e2300 +mem-write: 0x8000aea3 <- 0xb041300 +mem-write: 0x8000aea7 <- 0x31222300 +mem-write: 0x8000aeab <- 0xc0b1303 +mem-write: 0x8000aeaf <- 0x9049300 +mem-write: 0x8000aeb3 <- 0xc899300 +mem-write: 0x8000aeb7 <- 0xbfa1300 +mem-write: 0x8000aebb <- 0xc12c8340 +mem-write: 0x8000aebf <- 0xf00a9303 +mem-write: 0x8000aec3 <- 0x88c130f +mem-write: 0x8000aec7 <- 0x7891300 +mem-write: 0x8000aecb <- 0x40006f00 +mem-write: 0x8000aecf <- 0xa0061302 +mem-write: 0x8000aed3 <- 0x69300 +mem-write: 0x8000aed7 <- 0x4851300 +mem-write: 0x8000aedb <- 0x9859300 +mem-write: 0x8000aedf <- 0x8050ef00 +mem-write: 0x8000aee3 <- 0x9806350 +mem-write: 0x8000aee7 <- 0x504934c +mem-write: 0x8000aeeb <- 0x5899300 +mem-write: 0x8000aeef <- 0xa0061300 +mem-write: 0x8000aef3 <- 0x69300 +mem-write: 0x8000aef7 <- 0x4851300 +mem-write: 0x8000aefb <- 0x9859300 +mem-write: 0x8000aeff <- 0xd050ef00 +mem-write: 0x8000af03 <- 0x5051311 +mem-write: 0x8000af07 <- 0xa40fa303 +mem-write: 0x8000af0b <- 0x190913fe +mem-write: 0x8000af0f <- 0xf4041300 +mem-write: 0x8000af13 <- 0xa0ee3ff +mem-write: 0x8000af17 <- 0xcc683fa +mem-write: 0x8000af1b <- 0xd91ae300 +mem-write: 0x8000af1f <- 0x5908e3fa +mem-write: 0x8000af23 <- 0x99a63fb +mem-write: 0x8000af27 <- 0x90079342 +mem-write: 0x8000af2b <- 0x97e66300 +mem-write: 0x8000af2f <- 0xc089342 +mem-write: 0x8000af33 <- 0x1079300 +mem-write: 0x8000af37 <- 0xb0c131b +mem-write: 0x8000af3b <- 0x40b1300 +mem-write: 0x8000af3f <- 0x912e2300 +mem-write: 0x8000af43 <- 0xc1248303 +mem-write: 0x8000af47 <- 0x41298301 +mem-write: 0x8000af4b <- 0x1240302 +mem-write: 0x8000af4f <- 0x21202301 +mem-write: 0x8000af53 <- 0x678cb303 +mem-write: 0x8000af57 <- 0xb8a1341 +mem-write: 0x8000af5b <- 0xcff06f00 +mem-write: 0x8000af5f <- 0x81268396 +mem-write: 0x8000af63 <- 0x156370e +mem-write: 0x8000af67 <- 0x6061380 +mem-write: 0x8000af6b <- 0xc8a02398 +mem-write: 0x8000af6f <- 0x17879300 +mem-write: 0x8000af73 <- 0x10061300 +mem-write: 0x8000af77 <- 0x16869300 +mem-write: 0x8000af7b <- 0xc8a22300 +mem-write: 0x8000af7f <- 0xf1262300 +mem-write: 0x8000af83 <- 0xd124230e +mem-write: 0x8000af87 <- 0x7006130e +mem-write: 0x8000af8b <- 0x88889300 +mem-write: 0x8000af8f <- 0xd64c6300 +mem-write: 0x8000af93 <- 0x5986306 +mem-write: 0x8000af97 <- 0x1270320 +mem-write: 0x8000af9b <- 0x1a769302 +mem-write: 0x8000af9f <- 0xe6e6b300 +mem-write: 0x8000afa3 <- 0x6946300 +mem-write: 0x8000afa7 <- 0x9fe06f00 +mem-write: 0x8000afab <- 0x1268392 +mem-write: 0x8000afaf <- 0xc1270303 +mem-write: 0x8000afb3 <- 0x70061302 +mem-write: 0x8000afb7 <- 0xd8a02300 +mem-write: 0x8000afbb <- 0x81268300 +mem-write: 0x8000afbf <- 0xe787b30e +mem-write: 0x8000afc3 <- 0xe8a22300 +mem-write: 0x8000afc7 <- 0x16869300 +mem-write: 0x8000afcb <- 0xf1262300 +mem-write: 0x8000afcf <- 0xd124230e +mem-write: 0x8000afd3 <- 0xd64e630e +mem-write: 0x8000afd7 <- 0x8888934a +mem-write: 0x8000afdb <- 0x1270300 +mem-write: 0x8000afdf <- 0x16869302 +mem-write: 0x8000afe3 <- 0x68a02300 +mem-write: 0x8000afe7 <- 0xe787b301 +mem-write: 0x8000afeb <- 0xe8a22300 +mem-write: 0x8000afef <- 0xf1262300 +mem-write: 0x8000aff3 <- 0xd124230e +mem-write: 0x8000aff7 <- 0x7007130e +VXDRV: upload 1024 bytes to 0x8000affb +mem-write: 0x8000affb <- 0xd7446300 +mem-write: 0x8000afff <- 0xdfe06f00 +mem-write: 0x8000b003 <- 0x5fe06f8c +mem-write: 0x8000b007 <- 0x410613e6 +mem-write: 0x8000b00b <- 0xc05930e +mem-write: 0x8000b00f <- 0xd051300 +mem-write: 0x8000b013 <- 0x9030ef00 +mem-write: 0x8000b017 <- 0x5146334 +mem-write: 0x8000b01b <- 0xc12583e2 +mem-write: 0x8000b01f <- 0xc127830c +mem-write: 0x8000b023 <- 0xc108930e +mem-write: 0x8000b027 <- 0xdff06f10 +mem-write: 0x8000b02b <- 0x12b83f6 +mem-write: 0x8000b02f <- 0x40d1301 +mem-write: 0x8000b033 <- 0x48c1300 +mem-write: 0x8000b037 <- 0xcff06f00 +mem-write: 0x8000b03b <- 0xa7793e0 +mem-write: 0x8000b03f <- 0x78c6304 +mem-write: 0x8000b043 <- 0x41278322 +mem-write: 0x8000b047 <- 0xc9301 +mem-write: 0x8000b04b <- 0xe12a2300 +mem-write: 0x8000b04f <- 0x7d90300 +mem-write: 0x8000b053 <- 0x5ff06f00 +mem-write: 0x8000b057 <- 0x410613b3 +mem-write: 0x8000b05b <- 0xc05930e +mem-write: 0x8000b05f <- 0xd051300 +mem-write: 0x8000b063 <- 0x9030ef00 +mem-write: 0x8000b067 <- 0x51c632f +mem-write: 0x8000b06b <- 0xc12783dc +mem-write: 0x8000b06f <- 0xc108930e +mem-write: 0x8000b073 <- 0xff06f10 +mem-write: 0x8000b077 <- 0x812683b9 +mem-write: 0x8000b07b <- 0x9787b300 +mem-write: 0x8000b07f <- 0x98a22300 +mem-write: 0x8000b083 <- 0xd8a02300 +mem-write: 0x8000b087 <- 0x17071300 +mem-write: 0x8000b08b <- 0xf1262300 +mem-write: 0x8000b08f <- 0xe124230e +mem-write: 0x8000b093 <- 0x7006930e +mem-write: 0x8000b097 <- 0xe6c46300 +mem-write: 0x8000b09b <- 0x1fe06f00 +mem-write: 0x8000b09f <- 0x9fe06f83 +mem-write: 0x8000b0a3 <- 0x410613dc +mem-write: 0x8000b0a7 <- 0xb05930e +mem-write: 0x8000b0ab <- 0xd051300 +mem-write: 0x8000b0af <- 0xd030ef00 +mem-write: 0x8000b0b3 <- 0x512632a +mem-write: 0x8000b0b7 <- 0x446832e +mem-write: 0x8000b0bb <- 0xc1278300 +mem-write: 0x8000b0bf <- 0xc108930e +mem-write: 0x8000b0c3 <- 0xdff06f10 +mem-write: 0x8000b0c7 <- 0x12783ca +mem-write: 0x8000b0cb <- 0x105930f +mem-write: 0x8000b0cf <- 0x105130a +mem-write: 0x8000b0d3 <- 0xf128230b +mem-write: 0x8000b0d7 <- 0x4127830a +mem-write: 0x8000b0db <- 0x120230f +mem-write: 0x8000b0df <- 0x122230a +mem-write: 0x8000b0e3 <- 0xf12a230a +mem-write: 0x8000b0e7 <- 0x8127830a +mem-write: 0x8000b0eb <- 0x124230f +mem-write: 0x8000b0ef <- 0x126230a +mem-write: 0x8000b0f3 <- 0xf12c230a +mem-write: 0x8000b0f7 <- 0xc127830a +mem-write: 0x8000b0fb <- 0xf12e230f +mem-write: 0x8000b0ff <- 0x1060ef0a +mem-write: 0x8000b103 <- 0x128831e +mem-write: 0x8000b107 <- 0x5426301 +mem-write: 0x8000b10b <- 0x71478352 +mem-write: 0x8000b10f <- 0x7007130c +mem-write: 0x8000b113 <- 0x975e6304 +mem-write: 0x8000b117 <- 0x1573728 +mem-write: 0x8000b11b <- 0x70b1380 +mem-write: 0x8000b11f <- 0x12823a3 +mem-write: 0x8000b123 <- 0x1242300 +mem-write: 0x8000b127 <- 0x1222302 +mem-write: 0x8000b12b <- 0x12e2302 +mem-write: 0x8000b12f <- 0xfa7a1300 +mem-write: 0x8000b133 <- 0x300a93f7 +mem-write: 0x8000b137 <- 0x300c9300 +mem-write: 0x8000b13b <- 0xd9300 +mem-write: 0x8000b13f <- 0x7846300 +mem-write: 0x8000b143 <- 0x9fe06f00 +mem-write: 0x8000b147 <- 0xcfe06fe7 +mem-write: 0x8000b14b <- 0xc12783eb +mem-write: 0x8000b14f <- 0x40b1300 +mem-write: 0x8000b153 <- 0xf7202300 +mem-write: 0x8000b157 <- 0xfe06f00 +mem-write: 0x8000b15b <- 0xb0513fc +mem-write: 0x8000b15f <- 0x91202300 +mem-write: 0x8000b163 <- 0x8fe0ef05 +mem-write: 0x8000b167 <- 0x714783b8 +mem-write: 0x8000b16b <- 0xf54a930c +mem-write: 0x8000b16f <- 0xfada93ff +mem-write: 0x8000b173 <- 0x212a2341 +mem-write: 0x8000b177 <- 0x1282301 +mem-write: 0x8000b17b <- 0x1242300 +mem-write: 0x8000b17f <- 0x1222302 +mem-write: 0x8000b183 <- 0x12e2302 +mem-write: 0x8000b187 <- 0x1288300 +mem-write: 0x8000b18b <- 0x50c9304 +mem-write: 0x8000b18f <- 0x557ab300 +mem-write: 0x8000b193 <- 0xd9301 +mem-write: 0x8000b197 <- 0x7846300 +mem-write: 0x8000b19b <- 0x1fe06f00 +mem-write: 0x8000b19f <- 0x4fe06fe2 +mem-write: 0x8000b1a3 <- 0x12683e6 +mem-write: 0x8000b1a7 <- 0xc1270303 +mem-write: 0x8000b1ab <- 0x70061302 +mem-write: 0x8000b1af <- 0xd8a02300 +mem-write: 0x8000b1b3 <- 0x81268300 +mem-write: 0x8000b1b7 <- 0xe787b30e +mem-write: 0x8000b1bb <- 0xe8a22300 +mem-write: 0x8000b1bf <- 0x16869300 +mem-write: 0x8000b1c3 <- 0xf1262300 +mem-write: 0x8000b1c7 <- 0xd124230e +mem-write: 0x8000b1cb <- 0x8888930e +mem-write: 0x8000b1cf <- 0xd6406300 +mem-write: 0x8000b1d3 <- 0x5d4e32c +mem-write: 0x8000b1d7 <- 0x613e0 +mem-write: 0x8000b1db <- 0xb004b3ff +mem-write: 0x8000b1df <- 0xc5d4e340 +mem-write: 0x8000b1e3 <- 0x91326 +mem-write: 0x8000b1e7 <- 0x700c9301 +mem-write: 0x8000b1eb <- 0xc0006f00 +mem-write: 0x8000b1ef <- 0x4849300 +mem-write: 0x8000b1f3 <- 0x995ae3ff +mem-write: 0x8000b1f7 <- 0x81270324 +mem-write: 0x8000b1fb <- 0x7879300 +mem-write: 0x8000b1ff <- 0x16869301 +mem-write: 0x8000b203 <- 0xe8a02300 +mem-write: 0x8000b207 <- 0x28a22300 +mem-write: 0x8000b20b <- 0xf1262301 +mem-write: 0x8000b20f <- 0xd124230e +mem-write: 0x8000b213 <- 0x8888930e +mem-write: 0x8000b217 <- 0xdcdce300 +mem-write: 0x8000b21b <- 0x410613fc +mem-write: 0x8000b21f <- 0xc05930e +mem-write: 0x8000b223 <- 0xd051300 +mem-write: 0x8000b227 <- 0x5030ef00 +mem-write: 0x8000b22b <- 0x51a6313 +mem-write: 0x8000b22f <- 0xc12783c0 +mem-write: 0x8000b233 <- 0x8126830e +mem-write: 0x8000b237 <- 0xc108930e +mem-write: 0x8000b23b <- 0x5ff06f10 +mem-write: 0x8000b23f <- 0x148693fb +mem-write: 0x8000b243 <- 0x89071300 +mem-write: 0x8000b247 <- 0x81278300 +mem-write: 0x8000b24b <- 0xbc8cb300 +mem-write: 0x8000b24f <- 0xb9222301 +mem-write: 0x8000b253 <- 0xf9202301 +mem-write: 0x8000b257 <- 0x91262300 +mem-write: 0x8000b25b <- 0xd124230f +mem-write: 0x8000b25f <- 0x7007930e +mem-write: 0x8000b263 <- 0xd7c2e300 +mem-write: 0x8000b267 <- 0x168693be +mem-write: 0x8000b26b <- 0x87089300 +mem-write: 0x8000b26f <- 0x7091300 +mem-write: 0x8000b273 <- 0x1fe06f00 +mem-write: 0x8000b277 <- 0xa7793bd +mem-write: 0x8000b27b <- 0x78e6320 +mem-write: 0x8000b27f <- 0x4127831c +mem-write: 0x8000b283 <- 0xc9301 +mem-write: 0x8000b287 <- 0xe12a2300 +mem-write: 0x8000b28b <- 0x7c90300 +mem-write: 0x8000b28f <- 0x9ff06f00 +mem-write: 0x8000b293 <- 0xa77938f +mem-write: 0x8000b297 <- 0x7846320 +mem-write: 0x8000b29b <- 0x4127831a +mem-write: 0x8000b29f <- 0xe12a2301 +mem-write: 0x8000b2a3 <- 0x7890300 +mem-write: 0x8000b2a7 <- 0xf95c9300 +mem-write: 0x8000b2ab <- 0xc879341 +mem-write: 0x8000b2af <- 0x5fe06f00 +mem-write: 0x8000b2b3 <- 0xbf793fa +mem-write: 0x8000b2b7 <- 0x7886320 +mem-write: 0x8000b2bb <- 0x41278316 +mem-write: 0x8000b2bf <- 0xc9301 +mem-write: 0x8000b2c3 <- 0xe12a2300 +mem-write: 0x8000b2c7 <- 0x7c90300 +mem-write: 0x8000b2cb <- 0x10079300 +mem-write: 0x8000b2cf <- 0xdfe06f00 +mem-write: 0x8000b2d3 <- 0xa7793dc +mem-write: 0x8000b2d7 <- 0x78e6320 +mem-write: 0x8000b2db <- 0x41278312 +mem-write: 0x8000b2df <- 0xc9301 +mem-write: 0x8000b2e3 <- 0xe12a2300 +mem-write: 0x8000b2e7 <- 0x7c90300 +mem-write: 0x8000b2eb <- 0x1fe06f00 +mem-write: 0x8000b2ef <- 0xc12783e3 +mem-write: 0x8000b2f3 <- 0x7c8630f +mem-write: 0x8000b2f7 <- 0x71478318 +mem-write: 0x8000b2fb <- 0x7007130c +mem-write: 0x8000b2ff <- 0x975c6304 +mem-write: 0x8000b303 <- 0x1573746 +mem-write: 0x8000b307 <- 0x870b1380 +mem-write: 0x8000b30b <- 0x5ff06fa3 +mem-write: 0x8000b30f <- 0x812703e1 +mem-write: 0x8000b313 <- 0x9787b300 +mem-write: 0x8000b317 <- 0x16869300 +mem-write: 0x8000b31b <- 0xe8a02300 +mem-write: 0x8000b31f <- 0x98a22300 +mem-write: 0x8000b323 <- 0xf1262300 +mem-write: 0x8000b327 <- 0xd124230e +mem-write: 0x8000b32b <- 0x7006130e +mem-write: 0x8000b32f <- 0x88889300 +mem-write: 0x8000b333 <- 0xd6566300 +mem-write: 0x8000b337 <- 0x410613c8 +mem-write: 0x8000b33b <- 0xc05930e +mem-write: 0x8000b33f <- 0xd051300 +mem-write: 0x8000b343 <- 0x9030ef00 +mem-write: 0x8000b347 <- 0x51c6301 +mem-write: 0x8000b34b <- 0xc12783ae +mem-write: 0x8000b34f <- 0xc108930e +mem-write: 0x8000b353 <- 0xcff06f10 +mem-write: 0x8000b357 <- 0x812783c6 +mem-write: 0x8000b35b <- 0xc1258304 +mem-write: 0x8000b35f <- 0x91304 +mem-write: 0x8000b363 <- 0xf4043300 +mem-write: 0x8000b367 <- 0x7861340 +mem-write: 0x8000b36b <- 0x4051300 +mem-write: 0x8000b36f <- 0x8fe0ef00 +mem-write: 0x8000b373 <- 0x1cc583a0 +mem-write: 0x8000b377 <- 0xa0061300 +mem-write: 0x8000b37b <- 0x69300 +mem-write: 0x8000b37f <- 0xb0383300 +mem-write: 0x8000b383 <- 0x4851300 +mem-write: 0x8000b387 <- 0x9859300 +mem-write: 0x8000b38b <- 0xc8cb300 +mem-write: 0x8000b38f <- 0x8050ef01 +mem-write: 0x8000b393 <- 0x5ff06f05 +mem-write: 0x8000b397 <- 0x12b83b5 +mem-write: 0x8000b39b <- 0xb0c1301 +mem-write: 0x8000b39f <- 0x4ff06f00 +mem-write: 0x8000b3a3 <- 0x900793aa +mem-write: 0x8000b3a7 <- 0x97e0e300 +mem-write: 0x8000b3ab <- 0x5ff06fb4 +mem-write: 0x8000b3af <- 0x15737b8 +mem-write: 0x8000b3b3 <- 0xc70b1380 +mem-write: 0x8000b3b7 <- 0x9ff06fa2 +mem-write: 0x8000b3bb <- 0x410613d6 +mem-write: 0x8000b3bf <- 0xc05930e +mem-write: 0x8000b3c3 <- 0xd051300 +mem-write: 0x8000b3c7 <- 0x4030ef00 +mem-write: 0x8000b3cb <- 0x51a6379 +mem-write: 0x8000b3cf <- 0xc12783a6 +mem-write: 0x8000b3d3 <- 0xc108930e +mem-write: 0x8000b3d7 <- 0xff06f10 +mem-write: 0x8000b3db <- 0x600c93bd +mem-write: 0x8000b3df <- 0x5ff06f00 +mem-write: 0x8000b3e3 <- 0x1268386 +mem-write: 0x8000b3e7 <- 0xdb073302 +mem-write: 0x8000b3eb <- 0x9684b300 +mem-write: 0x8000b3ef <- 0xb7083340 +mem-write: 0x8000b3f3 <- 0x4891341 +mem-write: 0x8000b3f7 <- 0x98526300 +VXDRV: upload 1024 bytes to 0x8000b3fb +mem-write: 0x8000b3fb <- 0x80913c6 +mem-write: 0x8000b3ff <- 0xcff06f00 +mem-write: 0x8000b403 <- 0xc12783c5 +mem-write: 0x8000b407 <- 0x40b1300 +mem-write: 0x8000b40b <- 0xf7102300 +mem-write: 0x8000b40f <- 0x8fe06f00 +mem-write: 0x8000b413 <- 0x412783d0 +mem-write: 0x8000b417 <- 0xc9301 +mem-write: 0x8000b41b <- 0xe12a2300 +mem-write: 0x8000b41f <- 0x7a90300 +mem-write: 0x8000b423 <- 0x9fe06f00 +mem-write: 0x8000b427 <- 0x412783cf +mem-write: 0x8000b42b <- 0xc9301 +mem-write: 0x8000b42f <- 0xe12a2300 +mem-write: 0x8000b433 <- 0x7a90300 +mem-write: 0x8000b437 <- 0x10079300 +mem-write: 0x8000b43b <- 0x1fe06f00 +mem-write: 0x8000b43f <- 0x412783c6 +mem-write: 0x8000b443 <- 0xe12a2301 +mem-write: 0x8000b447 <- 0x7a90300 +mem-write: 0x8000b44b <- 0xf95c9300 +mem-write: 0x8000b44f <- 0xc879341 +mem-write: 0x8000b453 <- 0x1fe06f00 +mem-write: 0x8000b457 <- 0x412783e0 +mem-write: 0x8000b45b <- 0xc9301 +mem-write: 0x8000b45f <- 0xe12a2300 +mem-write: 0x8000b463 <- 0x7a90300 +mem-write: 0x8000b467 <- 0xff06f00 +mem-write: 0x8000b46b <- 0x410613f2 +mem-write: 0x8000b46f <- 0xc05930e +mem-write: 0x8000b473 <- 0xd051300 +mem-write: 0x8000b477 <- 0x4030ef00 +mem-write: 0x8000b47b <- 0xcc57036e +mem-write: 0x8000b47f <- 0xfe06f00 +mem-write: 0x8000b483 <- 0xd00793cb +mem-write: 0x8000b487 <- 0xf103a302 +mem-write: 0x8000b48b <- 0x1ff06f0c +mem-write: 0x8000b48f <- 0x410613e7 +mem-write: 0x8000b493 <- 0xc05930e +mem-write: 0x8000b497 <- 0xd051300 +mem-write: 0x8000b49b <- 0x30ef00 +mem-write: 0x8000b49f <- 0x510636c +mem-write: 0x8000b4a3 <- 0xc125839a +mem-write: 0x8000b4a7 <- 0xc127830c +mem-write: 0x8000b4ab <- 0x8126830e +mem-write: 0x8000b4af <- 0xc108930e +mem-write: 0x8000b4b3 <- 0x5d4e310 +mem-write: 0x8000b4b7 <- 0x1ff06fb2 +mem-write: 0x8000b4bb <- 0x600d93d2 +mem-write: 0x8000b4bf <- 0x8fe06f00 +mem-write: 0x8000b4c3 <- 0x12703df +mem-write: 0x8000b4c7 <- 0xb0c1302 +mem-write: 0x8000b4cb <- 0x812b0300 +mem-write: 0x8000b4cf <- 0x812e2302 +mem-write: 0x8000b4d3 <- 0xc12a0302 +mem-write: 0x8000b4d7 <- 0xeb06b301 +mem-write: 0x8000b4db <- 0x1240300 +mem-write: 0x8000b4df <- 0x41298304 +mem-write: 0x8000b4e3 <- 0x412a8304 +mem-write: 0x8000b4e7 <- 0xb6f46302 +mem-write: 0x8000b4eb <- 0x68d93af +mem-write: 0x8000b4ef <- 0xff06f00 +mem-write: 0x8000b4f3 <- 0xc12703ae +mem-write: 0x8000b4f7 <- 0xd0079301 +mem-write: 0x8000b4fb <- 0xf74463ff +mem-write: 0x8000b4ff <- 0xedda6300 +mem-write: 0x8000b503 <- 0xe4849300 +mem-write: 0x8000b507 <- 0xf4f793ff +mem-write: 0x8000b50b <- 0xf12a23fd +mem-write: 0x8000b50f <- 0x4fe06f04 +mem-write: 0x8000b513 <- 0x12783ee +mem-write: 0x8000b517 <- 0xc1270302 +mem-write: 0x8000b51b <- 0xf7446301 +mem-write: 0x8000b51f <- 0x81278326 +mem-write: 0x8000b523 <- 0x70c9302 +mem-write: 0x8000b527 <- 0x17f79300 +mem-write: 0x8000b52b <- 0x7866300 +mem-write: 0x8000b52f <- 0xc1278300 +mem-write: 0x8000b533 <- 0xf70cb302 +mem-write: 0x8000b537 <- 0x81278300 +mem-write: 0x8000b53b <- 0x7f79302 +mem-write: 0x8000b53f <- 0x7866340 +mem-write: 0x8000b543 <- 0xc1278300 +mem-write: 0x8000b547 <- 0xf04ae301 +mem-write: 0x8000b54b <- 0xfcca9312 +mem-write: 0x8000b54f <- 0xfada93ff +mem-write: 0x8000b553 <- 0x5cfab341 +mem-write: 0x8000b557 <- 0x70049301 +mem-write: 0x8000b55b <- 0x1242306 +mem-write: 0x8000b55f <- 0x1222302 +mem-write: 0x8000b563 <- 0xcfe06f02 +mem-write: 0x8000b567 <- 0x714783fa +mem-write: 0x8000b56b <- 0xd930c +mem-write: 0x8000b56f <- 0x7846300 +mem-write: 0x8000b573 <- 0x9fe06f00 +mem-write: 0x8000b577 <- 0xcfe06fa4 +mem-write: 0x8000b57b <- 0x410613a8 +mem-write: 0x8000b57f <- 0xb05930e +mem-write: 0x8000b583 <- 0xd051300 +mem-write: 0x8000b587 <- 0x4030ef00 +mem-write: 0x8000b58b <- 0x516e35d +mem-write: 0x8000b58f <- 0x44683e0 +mem-write: 0x8000b593 <- 0xc1278300 +mem-write: 0x8000b597 <- 0xc108930e +mem-write: 0x8000b59b <- 0xdd8db310 +mem-write: 0x8000b59f <- 0x8ff06f00 +mem-write: 0x8000b5a3 <- 0x10a93fe +mem-write: 0x8000b5a7 <- 0xc108130b +mem-write: 0x8000b5ab <- 0x107930d +mem-write: 0x8000b5af <- 0xc107130d +mem-write: 0x8000b5b3 <- 0xd86930c +mem-write: 0x8000b5b7 <- 0x30061300 +mem-write: 0x8000b5bb <- 0xa859300 +mem-write: 0x8000b5bf <- 0xd051300 +mem-write: 0x8000b5c3 <- 0x11222300 +mem-write: 0x8000b5c7 <- 0xc1282305 +mem-write: 0x8000b5cb <- 0xc120230b +mem-write: 0x8000b5cf <- 0xd12a2305 +mem-write: 0x8000b5d3 <- 0xd122230b +mem-write: 0x8000b5d7 <- 0xe12c2303 +mem-write: 0x8000b5db <- 0xe120230b +mem-write: 0x8000b5df <- 0x612e2303 +mem-write: 0x8000b5e3 <- 0x612e230a +mem-write: 0x8000b5e7 <- 0xdfa0ef00 +mem-write: 0x8000b5eb <- 0xc12303c4 +mem-write: 0x8000b5ef <- 0x12f0301 +mem-write: 0x8000b5f3 <- 0x412e8302 +mem-write: 0x8000b5f7 <- 0x12e0302 +mem-write: 0x8000b5fb <- 0x41288304 +mem-write: 0x8000b5ff <- 0x50b1304 +mem-write: 0x8000b603 <- 0x60079300 +mem-write: 0x8000b607 <- 0xbb093304 +mem-write: 0x8000b60b <- 0xfb9a6301 +mem-write: 0x8000b60f <- 0xb468362 +mem-write: 0x8000b613 <- 0x79300 +mem-write: 0x8000b617 <- 0xf686e303 +mem-write: 0x8000b61b <- 0x10c9310 +mem-write: 0x8000b61f <- 0xc127830a +mem-write: 0x8000b623 <- 0xf909330c +mem-write: 0x8000b627 <- 0xfe06f00 +mem-write: 0x8000b62b <- 0xd00793d4 +mem-write: 0x8000b62f <- 0xf103a302 +mem-write: 0x8000b633 <- 0xdff06f0c +mem-write: 0x8000b637 <- 0x10a93ad +mem-write: 0x8000b63b <- 0x107930b +mem-write: 0x8000b63f <- 0xc108130d +mem-write: 0x8000b643 <- 0xc107130d +mem-write: 0x8000b647 <- 0xd86930c +mem-write: 0x8000b64b <- 0x20061300 +mem-write: 0x8000b64f <- 0xa859300 +mem-write: 0x8000b653 <- 0xd051300 +mem-write: 0x8000b657 <- 0xc1282300 +mem-write: 0x8000b65b <- 0xc120230b +mem-write: 0x8000b65f <- 0xd12a2305 +mem-write: 0x8000b663 <- 0xd122230b +mem-write: 0x8000b667 <- 0xe12c2303 +mem-write: 0x8000b66b <- 0xe120230b +mem-write: 0x8000b66f <- 0x612e2303 +mem-write: 0x8000b673 <- 0x612e230a +mem-write: 0x8000b677 <- 0xdfa0ef00 +mem-write: 0x8000b67b <- 0x700793bb +mem-write: 0x8000b67f <- 0xc1230304 +mem-write: 0x8000b683 <- 0x12f0301 +mem-write: 0x8000b687 <- 0x412e8302 +mem-write: 0x8000b68b <- 0x12e0302 +mem-write: 0x8000b68f <- 0x41288304 +mem-write: 0x8000b693 <- 0x50b1304 +mem-write: 0x8000b697 <- 0xfb96e300 +mem-write: 0x8000b69b <- 0x812783f6 +mem-write: 0x8000b69f <- 0x17f79302 +mem-write: 0x8000b6a3 <- 0x7986300 +mem-write: 0x8000b6a7 <- 0x70079358 +mem-write: 0x8000b6ab <- 0xc1270304 +mem-write: 0x8000b6af <- 0xf12a230d +mem-write: 0x8000b6b3 <- 0xfe06f04 +mem-write: 0x8000b6b7 <- 0x410613d1 +mem-write: 0x8000b6bb <- 0xc05930e +mem-write: 0x8000b6bf <- 0xd051300 +mem-write: 0x8000b6c3 <- 0x8030ef00 +mem-write: 0x8000b6c7 <- 0x5046349 +mem-write: 0x8000b6cb <- 0x5fe06f00 +mem-write: 0x8000b6cf <- 0xc12483f7 +mem-write: 0x8000b6d3 <- 0xc127830c +mem-write: 0x8000b6d7 <- 0xc108930e +mem-write: 0x8000b6db <- 0x8ff06f10 +mem-write: 0x8000b6df <- 0x71478393 +mem-write: 0x8000b6e3 <- 0x212a230c +mem-write: 0x8000b6e7 <- 0x1242301 +mem-write: 0x8000b6eb <- 0x1222302 +mem-write: 0x8000b6ef <- 0x12e2302 +mem-write: 0x8000b6f3 <- 0xd8a9300 +mem-write: 0x8000b6f7 <- 0xd8c9300 +mem-write: 0x8000b6fb <- 0xd9300 +mem-write: 0x8000b6ff <- 0x7846300 +mem-write: 0x8000b703 <- 0x9fe06f00 +mem-write: 0x8000b707 <- 0xcfe06f8b +mem-write: 0x8000b70b <- 0x4106138f +mem-write: 0x8000b70f <- 0xc05930e +mem-write: 0x8000b713 <- 0xd051300 +mem-write: 0x8000b717 <- 0x4030ef00 +mem-write: 0x8000b71b <- 0x5046344 +mem-write: 0x8000b71f <- 0x1fe06f00 +mem-write: 0x8000b723 <- 0xc12483f2 +mem-write: 0x8000b727 <- 0x127030c +mem-write: 0x8000b72b <- 0xc1278302 +mem-write: 0x8000b72f <- 0xc108930e +mem-write: 0x8000b733 <- 0x9704b310 +mem-write: 0x8000b737 <- 0x4ff06f40 +mem-write: 0x8000b73b <- 0x81278392 +mem-write: 0x8000b73f <- 0xc1270302 +mem-write: 0x8000b743 <- 0x17f79301 +mem-write: 0x8000b747 <- 0xb7e7b300 +mem-write: 0x8000b74b <- 0xe054e301 +mem-write: 0x8000b74f <- 0x7966304 +mem-write: 0x8000b753 <- 0xc12c837a +mem-write: 0x8000b757 <- 0x60049301 +mem-write: 0x8000b75b <- 0x81278306 +mem-write: 0x8000b75f <- 0x7f79302 +mem-write: 0x8000b763 <- 0x79e6340 +mem-write: 0x8000b767 <- 0xfcca9370 +mem-write: 0x8000b76b <- 0xfada93ff +mem-write: 0x8000b76f <- 0x5cfab341 +mem-write: 0x8000b773 <- 0x9ff06f01 +mem-write: 0x8000b777 <- 0x15737de +mem-write: 0x8000b77b <- 0x470b1380 +mem-write: 0x8000b77f <- 0x1ff06fa3 +mem-write: 0x8000b783 <- 0x127839a +mem-write: 0x8000b787 <- 0xc1270302 +mem-write: 0x8000b78b <- 0x70049302 +mem-write: 0x8000b78f <- 0xe78cb306 +mem-write: 0x8000b793 <- 0xc1278300 +mem-write: 0x8000b797 <- 0xf042e301 +mem-write: 0x8000b79b <- 0xfc8cb3fc +mem-write: 0x8000b79f <- 0x1c8c9340 +mem-write: 0x8000b7a3 <- 0xfcca9300 +mem-write: 0x8000b7a7 <- 0xfada93ff +mem-write: 0x8000b7ab <- 0x5cfab341 +mem-write: 0x8000b7af <- 0xdff06f01 +mem-write: 0x8000b7b3 <- 0x156b7da +mem-write: 0x8000b7b7 <- 0x468e9380 +mem-write: 0x8000b7bb <- 0x8fe06f17 +mem-write: 0x8000b7bf <- 0x793f4 +mem-write: 0x8000b7c3 <- 0xf1042303 +mem-write: 0x8000b7c7 <- 0x8007930c +mem-write: 0x8000b7cb <- 0x2a671305 +mem-write: 0x8000b7cf <- 0xf104a300 +mem-write: 0x8000b7d3 <- 0xe124230c +mem-write: 0x8000b7d7 <- 0x30079302 +mem-write: 0x8000b7db <- 0x1282306 +mem-write: 0x8000b7df <- 0xc10b1300 +mem-write: 0x8000b7e3 <- 0xb7ce6314 +mem-write: 0x8000b7e7 <- 0xc1230341 +mem-write: 0x8000b7eb <- 0xf4fb930f +mem-write: 0x8000b7ef <- 0x712a23fd +mem-write: 0x8000b7f3 <- 0x12c2305 +mem-write: 0x8000b7f7 <- 0x12e0304 +VXDRV: upload 1024 bytes to 0x8000b7fb +mem-write: 0x8000b7fb <- 0x412e830f +mem-write: 0x8000b7ff <- 0x812f030f +mem-write: 0x8000b803 <- 0x2a6a130f +mem-write: 0x8000b807 <- 0x3426310 +mem-write: 0x8000b80b <- 0x10079338 +mem-write: 0x8000b80f <- 0xf48e6306 +mem-write: 0x8000b813 <- 0x10079354 +mem-write: 0x8000b817 <- 0xf4846304 +mem-write: 0x8000b81b <- 0x8fe06f00 +mem-write: 0x8000b81f <- 0x10a93ac +mem-write: 0x8000b823 <- 0xa85130b +mem-write: 0x8000b827 <- 0x11282300 +mem-write: 0x8000b82b <- 0xc1282305 +mem-write: 0x8000b82f <- 0xd12a230b +mem-write: 0x8000b833 <- 0xe12c230b +mem-write: 0x8000b837 <- 0x612e230b +mem-write: 0x8000b83b <- 0x5080ef0a +mem-write: 0x8000b83f <- 0xc1061356 +mem-write: 0x8000b843 <- 0x5fd0ef0c +mem-write: 0x8000b847 <- 0x586138b +mem-write: 0x8000b84b <- 0x5059300 +mem-write: 0x8000b84f <- 0xa851300 +mem-write: 0x8000b853 <- 0x9080ef00 +mem-write: 0x8000b857 <- 0x1278335 +mem-write: 0x8000b85b <- 0x10c930b +mem-write: 0x8000b85f <- 0x109130a +mem-write: 0x8000b863 <- 0xf1282309 +mem-write: 0x8000b867 <- 0x41278308 +mem-write: 0x8000b86b <- 0x106130b +mem-write: 0x8000b86f <- 0x9059308 +mem-write: 0x8000b873 <- 0xf12a2300 +mem-write: 0x8000b877 <- 0x81278308 +mem-write: 0x8000b87b <- 0xc85130b +mem-write: 0x8000b87f <- 0xc1202300 +mem-write: 0x8000b883 <- 0xf12c2304 +mem-write: 0x8000b887 <- 0xc1278308 +mem-write: 0x8000b88b <- 0x120230b +mem-write: 0x8000b88f <- 0x1222308 +mem-write: 0x8000b893 <- 0xf12e2308 +mem-write: 0x8000b897 <- 0xfc07b708 +mem-write: 0x8000b89b <- 0xf126233f +mem-write: 0x8000b89f <- 0x1242308 +mem-write: 0x8000b8a3 <- 0x60ef08 +mem-write: 0x8000b8a7 <- 0x1280338 +mem-write: 0x8000b8ab <- 0x412e030a +mem-write: 0x8000b8af <- 0x812e830a +mem-write: 0x8000b8b3 <- 0xc12f030a +mem-write: 0x8000b8b7 <- 0xc85930a +mem-write: 0x8000b8bb <- 0xa851300 +mem-write: 0x8000b8bf <- 0x1282300 +mem-write: 0x8000b8c3 <- 0x122230b +mem-write: 0x8000b8c7 <- 0xc12a2305 +mem-write: 0x8000b8cb <- 0xc122230b +mem-write: 0x8000b8cf <- 0xd12c2303 +mem-write: 0x8000b8d3 <- 0xd120230b +mem-write: 0x8000b8d7 <- 0xe12e2303 +mem-write: 0x8000b8db <- 0xe12e230b +mem-write: 0x8000b8df <- 0x1202301 +mem-write: 0x8000b8e3 <- 0x122230a +mem-write: 0x8000b8e7 <- 0x124230a +mem-write: 0x8000b8eb <- 0x126230a +mem-write: 0x8000b8ef <- 0x1050ef0a +mem-write: 0x8000b8f3 <- 0xc12f037e +mem-write: 0x8000b8f7 <- 0x12e8301 +mem-write: 0x8000b8fb <- 0x412e0302 +mem-write: 0x8000b8ff <- 0x41280302 +mem-write: 0x8000b903 <- 0x1288304 +mem-write: 0x8000b907 <- 0x5166305 +mem-write: 0x8000b90b <- 0x10079300 +mem-write: 0x8000b90f <- 0xf1262300 +mem-write: 0x8000b913 <- 0x157b70c +mem-write: 0x8000b917 <- 0x7879380 +mem-write: 0x8000b91b <- 0xf12223a5 +mem-write: 0x8000b91f <- 0xfd869302 +mem-write: 0x8000b923 <- 0x412e23ff +mem-write: 0x8000b927 <- 0x91222305 +mem-write: 0x8000b92b <- 0xb1262306 +mem-write: 0x8000b92f <- 0xa12a2307 +mem-write: 0x8000b933 <- 0x812c2307 +mem-write: 0x8000b937 <- 0xb0b9307 +mem-write: 0x8000b93b <- 0x81202300 +mem-write: 0x8000b93f <- 0x31242306 +mem-write: 0x8000b943 <- 0x11282307 +mem-write: 0x8000b947 <- 0x68c1307 +mem-write: 0x8000b94b <- 0x612e2300 +mem-write: 0x8000b94f <- 0x80d1307 +mem-write: 0x8000b953 <- 0xe0d9300 +mem-write: 0x8000b957 <- 0xe849300 +mem-write: 0x8000b95b <- 0xf0a1300 +mem-write: 0x8000b95f <- 0x80006f00 +mem-write: 0x8000b963 <- 0xc859304 +mem-write: 0x8000b967 <- 0xa851300 +mem-write: 0x8000b96b <- 0xc1202300 +mem-write: 0x8000b96f <- 0xf12e2302 +mem-write: 0x8000b973 <- 0xf12c2301 +mem-write: 0x8000b977 <- 0xc12e230b +mem-write: 0x8000b97b <- 0x6128230a +mem-write: 0x8000b97f <- 0x312a230b +mem-write: 0x8000b983 <- 0x120230b +mem-write: 0x8000b987 <- 0x122230a +mem-write: 0x8000b98b <- 0x124230a +mem-write: 0x8000b98f <- 0x126230a +mem-write: 0x8000b993 <- 0xd050ef0a +mem-write: 0x8000b997 <- 0xc12f8373 +mem-write: 0x8000b99b <- 0x1260301 +mem-write: 0x8000b99f <- 0xfc0c1302 +mem-write: 0x8000b9a3 <- 0x50263ff +mem-write: 0x8000b9a7 <- 0x307b70e +mem-write: 0x8000b9ab <- 0x9061340 +mem-write: 0x8000b9af <- 0xc859300 +mem-write: 0x8000b9b3 <- 0xa851300 +mem-write: 0x8000b9b7 <- 0xf12e2300 +mem-write: 0x8000b9bb <- 0xa1202308 +mem-write: 0x8000b9bf <- 0xb122230b +mem-write: 0x8000b9c3 <- 0x9124230b +mem-write: 0x8000b9c7 <- 0x4126230a +mem-write: 0x8000b9cb <- 0x128230b +mem-write: 0x8000b9cf <- 0x12a2308 +mem-write: 0x8000b9d3 <- 0x12c2308 +mem-write: 0x8000b9d7 <- 0xc060ef08 +mem-write: 0x8000b9db <- 0xa851324 +mem-write: 0x8000b9df <- 0x8080ef00 +mem-write: 0x8000b9e3 <- 0x5059376 +mem-write: 0x8000b9e7 <- 0x5041300 +mem-write: 0x8000b9eb <- 0xa851300 +mem-write: 0x8000b9ef <- 0x1298300 +mem-write: 0x8000b9f3 <- 0x4124830b +mem-write: 0x8000b9f7 <- 0x812b030b +mem-write: 0x8000b9fb <- 0xc12a030b +mem-write: 0x8000b9ff <- 0xd080ef0b +mem-write: 0x8000ba03 <- 0x1270305 +mem-write: 0x8000ba07 <- 0x126030b +mem-write: 0x8000ba0b <- 0x9059304 +mem-write: 0x8000ba0f <- 0xe1202300 +mem-write: 0x8000ba13 <- 0x41270308 +mem-write: 0x8000ba17 <- 0xc85130b +mem-write: 0x8000ba1b <- 0x31282300 +mem-write: 0x8000ba1f <- 0xe1222309 +mem-write: 0x8000ba23 <- 0x81270308 +mem-write: 0x8000ba27 <- 0x912a230b +mem-write: 0x8000ba2b <- 0x612c2308 +mem-write: 0x8000ba2f <- 0xe1242309 +mem-write: 0x8000ba33 <- 0xc1270308 +mem-write: 0x8000ba37 <- 0x412e230b +mem-write: 0x8000ba3b <- 0xe1262309 +mem-write: 0x8000ba3f <- 0x8070ef08 +mem-write: 0x8000ba43 <- 0x4127831e +mem-write: 0x8000ba47 <- 0x12b0302 +mem-write: 0x8000ba4b <- 0x4129830a +mem-write: 0x8000ba4f <- 0x8787330a +mem-write: 0x8000ba53 <- 0x7470300 +mem-write: 0x8000ba57 <- 0x812f8300 +mem-write: 0x8000ba5b <- 0xc126030a +mem-write: 0x8000ba5f <- 0x7128230a +mem-write: 0x8000ba63 <- 0xeb802305 +mem-write: 0x8000ba67 <- 0x81222300 +mem-write: 0x8000ba6b <- 0xf0079305 +mem-write: 0x8000ba6f <- 0x1b8b93ff +mem-write: 0x8000ba73 <- 0xb0d1300 +mem-write: 0x8000ba77 <- 0x98d9300 +mem-write: 0x8000ba7b <- 0xf849300 +mem-write: 0x8000ba7f <- 0x60a1300 +mem-write: 0x8000ba83 <- 0xfc10e300 +mem-write: 0x8000ba87 <- 0x12883ee +mem-write: 0x8000ba8b <- 0xb039307 +mem-write: 0x8000ba8f <- 0x9829300 +mem-write: 0x8000ba93 <- 0xfe093700 +mem-write: 0x8000ba97 <- 0xc85933f +mem-write: 0x8000ba9b <- 0xa851300 +mem-write: 0x8000ba9f <- 0x11202300 +mem-write: 0x8000baa3 <- 0x812e2303 +mem-write: 0x8000baa7 <- 0xc12a0300 +mem-write: 0x8000baab <- 0x41248305 +mem-write: 0x8000baaf <- 0x1240306 +mem-write: 0x8000bab3 <- 0x71282306 +mem-write: 0x8000bab7 <- 0x7122230a +mem-write: 0x8000babb <- 0x512a2306 +mem-write: 0x8000babf <- 0x5120230a +mem-write: 0x8000bac3 <- 0xf12c2306 +mem-write: 0x8000bac7 <- 0xf12e230b +mem-write: 0x8000bacb <- 0xc12e2305 +mem-write: 0x8000bacf <- 0xc120230a +mem-write: 0x8000bad3 <- 0x1202304 +mem-write: 0x8000bad7 <- 0x122230a +mem-write: 0x8000badb <- 0x124230a +mem-write: 0x8000badf <- 0x2126230a +mem-write: 0x8000bae3 <- 0x9050ef0b +mem-write: 0x8000bae7 <- 0xc12d836b +mem-write: 0x8000baeb <- 0x412d0306 +mem-write: 0x8000baef <- 0x812c0307 +mem-write: 0x8000baf3 <- 0xc12b0307 +mem-write: 0x8000baf7 <- 0x81298307 +mem-write: 0x8000bafb <- 0x1288306 +mem-write: 0x8000baff <- 0xa0406302 +mem-write: 0x8000bb03 <- 0x4123830a +mem-write: 0x8000bb07 <- 0x1228306 +mem-write: 0x8000bb0b <- 0xc12f8306 +mem-write: 0x8000bb0f <- 0x1260305 +mem-write: 0x8000bb13 <- 0xc859304 +mem-write: 0x8000bb17 <- 0xa851300 +mem-write: 0x8000bb1b <- 0x71282300 +mem-write: 0x8000bb1f <- 0x512a230a +mem-write: 0x8000bb23 <- 0xf12c230a +mem-write: 0x8000bb27 <- 0xc12e230b +mem-write: 0x8000bb2b <- 0x120230a +mem-write: 0x8000bb2f <- 0x122230a +mem-write: 0x8000bb33 <- 0x124230a +mem-write: 0x8000bb37 <- 0x2126230a +mem-write: 0x8000bb3b <- 0x5050ef0b +mem-write: 0x8000bb3f <- 0x1288359 +mem-write: 0x8000bb43 <- 0x5186302 +mem-write: 0x8000bb47 <- 0xc1278300 +mem-write: 0x8000bb4b <- 0x17fc9301 +mem-write: 0x8000bb4f <- 0xc986300 +mem-write: 0x8000bb53 <- 0x41278304 +mem-write: 0x8000bb57 <- 0x61304 +mem-write: 0x8000bb5b <- 0x17869303 +mem-write: 0x8000bb5f <- 0xdb86b300 +mem-write: 0x8000bb63 <- 0x7c86300 +mem-write: 0x8000bb67 <- 0x1b8b9300 +mem-write: 0x8000bb6b <- 0xcb8fa300 +mem-write: 0x8000bb6f <- 0xdb9ce3fe +mem-write: 0x8000bb73 <- 0x6b87b3fe +mem-write: 0x8000bb77 <- 0xf1202341 +mem-write: 0x8000bb7b <- 0xfe06f02 +mem-write: 0x8000bb7f <- 0x41242385 +mem-write: 0x8000bb83 <- 0x1282303 +mem-write: 0x8000bb87 <- 0x90a1300 +mem-write: 0x8000bb8b <- 0x7b700 +mem-write: 0x8000bb8f <- 0x67c33380 +mem-write: 0x8000bb93 <- 0xd0079300 +mem-write: 0x8000bb97 <- 0xf12c2302 +mem-write: 0x8000bb9b <- 0x1ff06f04 +mem-write: 0x8000bb9f <- 0x12783c7 +mem-write: 0x8000bba3 <- 0xb869305 +mem-write: 0x8000bba7 <- 0xf12e2300 +mem-write: 0x8000bbab <- 0x4127830c +mem-write: 0x8000bbaf <- 0xfbc60302 +mem-write: 0x8000bbb3 <- 0xf7c583ff +mem-write: 0x8000bbb7 <- 0xb6106300 +mem-write: 0x8000bbbb <- 0x51302 +mem-write: 0x8000bbbf <- 0xa68fa303 +mem-write: 0x8000bbc3 <- 0xc12683fe +mem-write: 0x8000bbc7 <- 0xf687930d +mem-write: 0x8000bbcb <- 0xf12e23ff +mem-write: 0x8000bbcf <- 0xf6c6030c +mem-write: 0x8000bbd3 <- 0xc586e3ff +mem-write: 0x8000bbd7 <- 0x160593fe +mem-write: 0x8000bbdb <- 0x90051300 +mem-write: 0x8000bbdf <- 0xf5f59303 +mem-write: 0x8000bbe3 <- 0xa606630f +mem-write: 0x8000bbe7 <- 0xb68fa300 +mem-write: 0x8000bbeb <- 0x9ff06ffe +mem-write: 0x8000bbef <- 0x412783f8 +mem-write: 0x8000bbf3 <- 0xa7c58302 +mem-write: 0x8000bbf7 <- 0xb68fa300 +VXDRV: upload 1023 bytes to 0x8000bbfb +mem-write: 0x8000bbfb <- 0x9ff06ffe +mem-write: 0x8000bbff <- 0x1d8593f7 +mem-write: 0x8000bc03 <- 0xd051300 +mem-write: 0x8000bc07 <- 0x11282300 +mem-write: 0x8000bc0b <- 0xdfb0ef01 +mem-write: 0x8000bc0f <- 0x12883b2 +mem-write: 0x8000bc13 <- 0x50b1301 +mem-write: 0x8000bc17 <- 0x5086300 +mem-write: 0x8000bc1b <- 0xa128233e +mem-write: 0x8000bc1f <- 0x9ff06f00 +mem-write: 0x8000bc23 <- 0x793bc +mem-write: 0x8000bc27 <- 0xf1042303 +mem-write: 0x8000bc2b <- 0x8007930c +mem-write: 0x8000bc2f <- 0xdff06f07 +mem-write: 0x8000bc33 <- 0x700793b9 +mem-write: 0x8000bc37 <- 0xbb093304 +mem-write: 0x8000bc3b <- 0xf12a2301 +mem-write: 0x8000bc3f <- 0x10c9304 +mem-write: 0x8000bc43 <- 0x5fd06f0a +mem-write: 0x8000bc47 <- 0x812703f2 +mem-write: 0x8000bc4b <- 0x9787b300 +mem-write: 0x8000bc4f <- 0x16869300 +mem-write: 0x8000bc53 <- 0xe8a02300 +mem-write: 0x8000bc57 <- 0x98a22300 +mem-write: 0x8000bc5b <- 0xf1262300 +mem-write: 0x8000bc5f <- 0xd124230e +mem-write: 0x8000bc63 <- 0x7006130e +mem-write: 0x8000bc67 <- 0xd6586300 +mem-write: 0x8000bc6b <- 0x410613b6 +mem-write: 0x8000bc6f <- 0xc05930e +mem-write: 0x8000bc73 <- 0xd051300 +mem-write: 0x8000bc77 <- 0x5020ef00 +mem-write: 0x8000bc7b <- 0x504636e +mem-write: 0x8000bc7f <- 0x1fe06f00 +mem-write: 0x8000bc83 <- 0xc127839c +mem-write: 0x8000bc87 <- 0x8126830e +mem-write: 0x8000bc8b <- 0xc108930e +mem-write: 0x8000bc8f <- 0xcff06f10 +mem-write: 0x8000bc93 <- 0xa0b93b4 +mem-write: 0x8000bc97 <- 0xcfe06f00 +mem-write: 0x8000bc9b <- 0xd9463df +mem-write: 0x8000bc9f <- 0x100d9300 +mem-write: 0x8000bca3 <- 0xc1230300 +mem-write: 0x8000bca7 <- 0x12e030f +mem-write: 0x8000bcab <- 0x412e830f +mem-write: 0x8000bcaf <- 0x812f030f +mem-write: 0x8000bcb3 <- 0xa69130f +mem-write: 0x8000bcb7 <- 0x344e310 +mem-write: 0x8000bcbb <- 0x10a93ec +mem-write: 0x8000bcbf <- 0xc108130b +mem-write: 0x8000bcc3 <- 0x107930d +mem-write: 0x8000bcc7 <- 0xc107130d +mem-write: 0x8000bccb <- 0xd86930c +mem-write: 0x8000bccf <- 0x20061300 +mem-write: 0x8000bcd3 <- 0xa859300 +mem-write: 0x8000bcd7 <- 0xd051300 +mem-write: 0x8000bcdb <- 0x11222300 +mem-write: 0x8000bcdf <- 0xc1282305 +mem-write: 0x8000bce3 <- 0xc120230b +mem-write: 0x8000bce7 <- 0xd12a2305 +mem-write: 0x8000bceb <- 0xd122230b +mem-write: 0x8000bcef <- 0xe12c2303 +mem-write: 0x8000bcf3 <- 0xe120230b +mem-write: 0x8000bcf7 <- 0x612e2303 +mem-write: 0x8000bcfb <- 0x612e230a +mem-write: 0x8000bcff <- 0x4fa0ef00 +mem-write: 0x8000bd03 <- 0xc12303d3 +mem-write: 0x8000bd07 <- 0x41242301 +mem-write: 0x8000bd0b <- 0x12f0303 +mem-write: 0x8000bd0f <- 0x412e8302 +mem-write: 0x8000bd13 <- 0x12e0302 +mem-write: 0x8000bd17 <- 0x41288304 +mem-write: 0x8000bd1b <- 0x50b1304 +mem-write: 0x8000bd1f <- 0x90a1300 +mem-write: 0x8000bd23 <- 0x1282300 +mem-write: 0x8000bd27 <- 0x12c2300 +mem-write: 0x8000bd2b <- 0x1ff06f04 +mem-write: 0x8000bd2f <- 0xf0079397 +mem-write: 0x8000bd33 <- 0xf12623ff +mem-write: 0x8000bd37 <- 0x5fd06f00 +mem-write: 0x8000bd3b <- 0x610693c0 +mem-write: 0x8000bd3f <- 0x618630d +mem-write: 0x8000bd43 <- 0x69300 +mem-write: 0x8000bd47 <- 0xd10b2303 +mem-write: 0x8000bd4b <- 0x7106930c +mem-write: 0x8000bd4f <- 0x107130d +mem-write: 0x8000bd53 <- 0x787931b +mem-write: 0x8000bd57 <- 0xe6863303 +mem-write: 0x8000bd5b <- 0xf6802340 +mem-write: 0x8000bd5f <- 0xd6079300 +mem-write: 0x8000bd63 <- 0xf12c230d +mem-write: 0x8000bd67 <- 0x5fd06f02 +mem-write: 0x8000bd6b <- 0x10a93f6 +mem-write: 0x8000bd6f <- 0xa85130b +mem-write: 0x8000bd73 <- 0x11282300 +mem-write: 0x8000bd77 <- 0xc1282305 +mem-write: 0x8000bd7b <- 0xd12a230b +mem-write: 0x8000bd7f <- 0xe12c230b +mem-write: 0x8000bd83 <- 0x612e230b +mem-write: 0x8000bd87 <- 0x9080ef0a +mem-write: 0x8000bd8b <- 0xc1061301 +mem-write: 0x8000bd8f <- 0x8fd0ef0c +mem-write: 0x8000bd93 <- 0x58613b6 +mem-write: 0x8000bd97 <- 0x5059300 +mem-write: 0x8000bd9b <- 0xa851300 +mem-write: 0x8000bd9f <- 0xc080ef00 +mem-write: 0x8000bda3 <- 0x1278360 +mem-write: 0x8000bda7 <- 0x10c930b +mem-write: 0x8000bdab <- 0x109130a +mem-write: 0x8000bdaf <- 0xf1282309 +mem-write: 0x8000bdb3 <- 0x41278308 +mem-write: 0x8000bdb7 <- 0x106130b +mem-write: 0x8000bdbb <- 0x9059308 +mem-write: 0x8000bdbf <- 0xf12a2300 +mem-write: 0x8000bdc3 <- 0x81278308 +mem-write: 0x8000bdc7 <- 0xc85130b +mem-write: 0x8000bdcb <- 0xc1202300 +mem-write: 0x8000bdcf <- 0xf12c2304 +mem-write: 0x8000bdd3 <- 0xc1278308 +mem-write: 0x8000bdd7 <- 0x120230b +mem-write: 0x8000bddb <- 0x1222308 +mem-write: 0x8000bddf <- 0xf12e2308 +mem-write: 0x8000bde3 <- 0xfc07b708 +mem-write: 0x8000bde7 <- 0xf126233f +mem-write: 0x8000bdeb <- 0x1242308 +mem-write: 0x8000bdef <- 0x5050ef08 +mem-write: 0x8000bdf3 <- 0x1280363 +mem-write: 0x8000bdf7 <- 0x412e030a +mem-write: 0x8000bdfb <- 0x812e830a +mem-write: 0x8000bdff <- 0xc12f030a +mem-write: 0x8000be03 <- 0xc85930a +mem-write: 0x8000be07 <- 0xa851300 +mem-write: 0x8000be0b <- 0x1282300 +mem-write: 0x8000be0f <- 0x122230b +mem-write: 0x8000be13 <- 0xc12a2305 +mem-write: 0x8000be17 <- 0xc122230b +mem-write: 0x8000be1b <- 0xd12c2303 +mem-write: 0x8000be1f <- 0xd120230b +mem-write: 0x8000be23 <- 0xe12e2303 +mem-write: 0x8000be27 <- 0xe12e230b +mem-write: 0x8000be2b <- 0x1202301 +mem-write: 0x8000be2f <- 0x122230a +mem-write: 0x8000be33 <- 0x124230a +mem-write: 0x8000be37 <- 0x126230a +mem-write: 0x8000be3b <- 0x5050ef0a +mem-write: 0x8000be3f <- 0xc12f0329 +mem-write: 0x8000be43 <- 0x12e8301 +mem-write: 0x8000be47 <- 0x412e0302 +mem-write: 0x8000be4b <- 0x41280302 +mem-write: 0x8000be4f <- 0x1288304 +mem-write: 0x8000be53 <- 0x5166305 +mem-write: 0x8000be57 <- 0x10079300 +mem-write: 0x8000be5b <- 0xf1262300 +mem-write: 0x8000be5f <- 0x157b70c +mem-write: 0x8000be63 <- 0xc7879380 +mem-write: 0x8000be67 <- 0xf12223a3 +mem-write: 0x8000be6b <- 0x5ff06f02 +mem-write: 0x8000be6f <- 0x12823ab +mem-write: 0x8000be73 <- 0x78a1300 +mem-write: 0x8000be77 <- 0x5ff06f00 +mem-write: 0x8000be7b <- 0x700493d1 +mem-write: 0x8000be7f <- 0xc1260306 +mem-write: 0x8000be83 <- 0xf0069303 +mem-write: 0x8000be87 <- 0x647830f +mem-write: 0x8000be8b <- 0xd7886300 +mem-write: 0x8000be8f <- 0xc1270318 +mem-write: 0x8000be93 <- 0x51301 +mem-write: 0x8000be97 <- 0x59300 +mem-write: 0x8000be9b <- 0xe7de6300 +mem-write: 0x8000be9f <- 0xf7073300 +mem-write: 0x8000bea3 <- 0x16478340 +mem-write: 0x8000bea7 <- 0x7846300 +mem-write: 0x8000beab <- 0x15859304 +mem-write: 0x8000beaf <- 0x16061300 +mem-write: 0x8000beb3 <- 0xd794e300 +mem-write: 0x8000beb7 <- 0xc12e23fe +mem-write: 0x8000bebb <- 0xe12e2302 +mem-write: 0x8000bebf <- 0xb1222300 +mem-write: 0x8000bec3 <- 0xa1242302 +mem-write: 0x8000bec7 <- 0x81270302 +mem-write: 0x8000becb <- 0x41278302 +mem-write: 0x8000becf <- 0xe787b302 +mem-write: 0x8000bed3 <- 0x81270300 +mem-write: 0x8000bed7 <- 0xe787b304 +mem-write: 0x8000bedb <- 0x978cb302 +mem-write: 0x8000bedf <- 0xfcca9301 +mem-write: 0x8000bee3 <- 0xfada93ff +mem-write: 0x8000bee7 <- 0x5cfab341 +mem-write: 0x8000beeb <- 0x5fd06f01 +mem-write: 0x8000beef <- 0x64783e2 +mem-write: 0x8000bef3 <- 0x15051300 +mem-write: 0x8000bef7 <- 0xdff06f00 +mem-write: 0x8000befb <- 0xc12783fb +mem-write: 0x8000beff <- 0x60049302 +mem-write: 0x8000bf03 <- 0xf70cb306 +mem-write: 0x8000bf07 <- 0xbc8cb300 +mem-write: 0x8000bf0b <- 0x1ff06f01 +mem-write: 0x8000bf0f <- 0x81278385 +mem-write: 0x8000bf13 <- 0x17f79302 +mem-write: 0x8000bf17 <- 0x7946300 +mem-write: 0x8000bf1b <- 0x1fd06f00 +mem-write: 0x8000bf1f <- 0x5fd06fdd +mem-write: 0x8000bf23 <- 0x10c93dc +mem-write: 0x8000bf27 <- 0xc85930a +mem-write: 0x8000bf2b <- 0xa851300 +mem-write: 0x8000bf2f <- 0x11222300 +mem-write: 0x8000bf33 <- 0xc1282305 +mem-write: 0x8000bf37 <- 0xc120230b +mem-write: 0x8000bf3b <- 0xd12a2305 +mem-write: 0x8000bf3f <- 0xd122230b +mem-write: 0x8000bf43 <- 0xe12c2303 +mem-write: 0x8000bf47 <- 0xe120230b +mem-write: 0x8000bf4b <- 0x612e2303 +mem-write: 0x8000bf4f <- 0x612e230a +mem-write: 0x8000bf53 <- 0x1202300 +mem-write: 0x8000bf57 <- 0x122230a +mem-write: 0x8000bf5b <- 0x124230a +mem-write: 0x8000bf5f <- 0x126230a +mem-write: 0x8000bf63 <- 0xd050ef0a +mem-write: 0x8000bf67 <- 0xc1230316 +mem-write: 0x8000bf6b <- 0x12f0301 +mem-write: 0x8000bf6f <- 0x412e8302 +mem-write: 0x8000bf73 <- 0x12e0302 +mem-write: 0x8000bf77 <- 0x41288304 +mem-write: 0x8000bf7b <- 0x5026304 +mem-write: 0x8000bf7f <- 0x100793ea +mem-write: 0x8000bf83 <- 0xb787b300 +mem-write: 0x8000bf87 <- 0xf1262341 +mem-write: 0x8000bf8b <- 0xf909330c +mem-write: 0x8000bf8f <- 0x9fd06f00 +mem-write: 0x8000bf93 <- 0x79a63bd +mem-write: 0x8000bf97 <- 0x100a9300 +mem-write: 0x8000bf9b <- 0x60049300 +mem-write: 0x8000bf9f <- 0x100c9306 +mem-write: 0x8000bfa3 <- 0x8ff06f00 +mem-write: 0x8000bfa7 <- 0xc12783db +mem-write: 0x8000bfab <- 0x60049302 +mem-write: 0x8000bfaf <- 0x178c9306 +mem-write: 0x8000bfb3 <- 0xbc8cb300 +mem-write: 0x8000bfb7 <- 0xfcca9301 +mem-write: 0x8000bfbb <- 0xfada93ff +mem-write: 0x8000bfbf <- 0x5cfab341 +mem-write: 0x8000bfc3 <- 0x8ff06f01 +mem-write: 0x8000bfc7 <- 0x88713d9 +mem-write: 0x8000bfcb <- 0xcff06f00 +mem-write: 0x8000bfcf <- 0x412783a7 +mem-write: 0x8000bfd3 <- 0x7ad8301 +mem-write: 0x8000bfd7 <- 0x47879300 +mem-write: 0x8000bfdb <- 0xdd46300 +mem-write: 0x8000bfdf <- 0xf00d9300 +mem-write: 0x8000bfe3 <- 0x144483ff +mem-write: 0x8000bfe7 <- 0xf12a2300 +mem-write: 0x8000bfeb <- 0x7041300 +mem-write: 0x8000bfef <- 0x4fd06f00 +mem-write: 0x8000bff3 <- 0xc00793f9 +mem-write: 0x8000bff7 <- 0xb6202300 +VXDRV: upload 1024 bytes to 0x8000bffa +mem-write: 0x8000bffa <- 0x79300fd +mem-write: 0x8000bffe <- 0x2623fff0 +mem-write: 0x8000c002 <- 0xd06f00f1 +mem-write: 0x8000c006 <- 0x5703939f +mem-write: 0x8000c00a <- 0x679300cc +mem-write: 0x8000c00e <- 0x87130407 +mem-write: 0x8000c012 <- 0x16230007 +mem-write: 0x8000c016 <- 0xd06f00fc +mem-write: 0x8000c01a <- 0x2423919f +mem-write: 0x8000c01e <- 0x22230201 +mem-write: 0x8000c022 <- 0xf06f0201 +mem-write: 0x8000c026 <- 0x793ea5f +mem-write: 0x8000c02a <- 0x2c230020 +mem-write: 0x8000c02e <- 0xd06f02f1 +mem-write: 0x8000c032 <- 0xa783c9df +mem-write: 0x8000c036 <- 0x1130645 +mem-write: 0x8000c03a <- 0x2823fd01 +mem-write: 0x8000c03e <- 0x26230161 +mem-write: 0x8000c042 <- 0x24230211 +mem-write: 0x8000c046 <- 0x22230281 +mem-write: 0x8000c04a <- 0x20230291 +mem-write: 0x8000c04e <- 0x2e230321 +mem-write: 0x8000c052 <- 0x2c230131 +mem-write: 0x8000c056 <- 0x2a230141 +mem-write: 0x8000c05a <- 0x26230151 +mem-write: 0x8000c05e <- 0x24230171 +mem-write: 0x8000c062 <- 0x97130181 +mem-write: 0x8000c066 <- 0xb130127 +mem-write: 0x8000c06a <- 0x58630006 +mem-write: 0x8000c06e <- 0x27830a07 +mem-write: 0x8000c072 <- 0x2b830086 +mem-write: 0x8000c076 <- 0x89130006 +mem-write: 0x8000c07a <- 0x9930005 +mem-write: 0x8000c07e <- 0xa930005 +mem-write: 0x8000c082 <- 0x8863fff0 +mem-write: 0x8000c086 <- 0xac030807 +mem-write: 0x8000c08a <- 0xa403004b +mem-write: 0x8000c08e <- 0x5a13000b +mem-write: 0x8000c092 <- 0x663002c +mem-write: 0x8000c096 <- 0x493060a +mem-write: 0x8000c09a <- 0x6f0000 +mem-write: 0x8000c09e <- 0x41300c0 +mem-write: 0x8000c0a2 <- 0xc630044 +mem-write: 0x8000c0a6 <- 0x2583049a +mem-write: 0x8000c0aa <- 0x6130004 +mem-write: 0x8000c0ae <- 0x85130009 +mem-write: 0x8000c0b2 <- 0x10ef0009 +mem-write: 0x8000c0b6 <- 0x849304d0 +mem-write: 0x8000c0ba <- 0x12e30014 +mem-write: 0x8000c0be <- 0x513ff55 +mem-write: 0x8000c0c2 <- 0x2083fff0 +mem-write: 0x8000c0c6 <- 0x240302c1 +mem-write: 0x8000c0ca <- 0x24230281 +mem-write: 0x8000c0ce <- 0x2223000b +mem-write: 0x8000c0d2 <- 0x2483000b +mem-write: 0x8000c0d6 <- 0x29030241 +mem-write: 0x8000c0da <- 0x29830201 +mem-write: 0x8000c0de <- 0x2a0301c1 +mem-write: 0x8000c0e2 <- 0x2a830181 +mem-write: 0x8000c0e6 <- 0x2b030141 +mem-write: 0x8000c0ea <- 0x2b830101 +mem-write: 0x8000c0ee <- 0x2c0300c1 +mem-write: 0x8000c0f2 <- 0x1130081 +mem-write: 0x8000c0f6 <- 0x80670301 +mem-write: 0x8000c0fa <- 0x27830000 +mem-write: 0x8000c0fe <- 0x7c13008b +mem-write: 0x8000c102 <- 0x87b3ffcc +mem-write: 0x8000c106 <- 0x24234187 +mem-write: 0x8000c10a <- 0x8b9300fb +mem-write: 0x8000c10e <- 0x9ce3008b +mem-write: 0x8000c112 <- 0x513f607 +mem-write: 0x8000c116 <- 0xf06f0000 +mem-write: 0x8000c11a <- 0x10effadf +mem-write: 0x8000c11e <- 0xf06f0f10 +mem-write: 0x8000c122 <- 0x2703fa5f +mem-write: 0x8000c126 <- 0x4630086 +mem-write: 0x8000c12a <- 0xf06f0007 +mem-write: 0x8000c12e <- 0x2223f09f +mem-write: 0x8000c132 <- 0x5130006 +mem-write: 0x8000c136 <- 0x80670000 +mem-write: 0x8000c13a <- 0x1130000 +mem-write: 0x8000c13e <- 0x2e23ed01 +mem-write: 0x8000c142 <- 0x2c231131 +mem-write: 0x8000c146 <- 0x26231141 +mem-write: 0x8000c14a <- 0x26231171 +mem-write: 0x8000c14e <- 0x24231211 +mem-write: 0x8000c152 <- 0x22231281 +mem-write: 0x8000c156 <- 0x20231291 +mem-write: 0x8000c15a <- 0x2a231321 +mem-write: 0x8000c15e <- 0x28231151 +mem-write: 0x8000c162 <- 0x24231161 +mem-write: 0x8000c166 <- 0x22231181 +mem-write: 0x8000c16a <- 0x20231191 +mem-write: 0x8000c16e <- 0x2e2311a1 +mem-write: 0x8000c172 <- 0x28230fb1 +mem-write: 0x8000c176 <- 0xa1300d1 +mem-write: 0x8000c17a <- 0x89930005 +mem-write: 0x8000c17e <- 0xb930005 +mem-write: 0x8000c182 <- 0x6630006 +mem-write: 0x8000c186 <- 0x27830005 +mem-write: 0x8000c18a <- 0x8e630385 +mem-write: 0x8000c18e <- 0x97035e07 +mem-write: 0x8000c192 <- 0x179300c9 +mem-write: 0x8000c196 <- 0x16930107 +mem-write: 0x8000c19a <- 0xd7930127 +mem-write: 0x8000c19e <- 0xca630107 +mem-write: 0x8000c1a2 <- 0x27b70206 +mem-write: 0x8000c1a6 <- 0xa6830000 +mem-write: 0x8000c1aa <- 0x67b30649 +mem-write: 0x8000c1ae <- 0x979300f7 +mem-write: 0x8000c1b2 <- 0xe7370107 +mem-write: 0x8000c1b6 <- 0xd793ffff +mem-write: 0x8000c1ba <- 0x7134107 +mem-write: 0x8000c1be <- 0xf733fff7 +mem-write: 0x8000c1c2 <- 0x962300e6 +mem-write: 0x8000c1c6 <- 0x979300f9 +mem-write: 0x8000c1ca <- 0xa2230107 +mem-write: 0x8000c1ce <- 0xd79306e9 +mem-write: 0x8000c1d2 <- 0xf7130107 +mem-write: 0x8000c1d6 <- 0x630087 +mem-write: 0x8000c1da <- 0xa7034007 +mem-write: 0x8000c1de <- 0xc630109 +mem-write: 0x8000c1e2 <- 0xf7933e07 +mem-write: 0x8000c1e6 <- 0x71301a7 +mem-write: 0x8000c1ea <- 0x866300a0 +mem-write: 0x8000c1ee <- 0x57b740e7 +mem-write: 0x8000c1f2 <- 0x87938001 +mem-write: 0x8000c1f6 <- 0x5b371947 +mem-write: 0x8000c1fa <- 0x4938001 +mem-write: 0x8000c1fe <- 0x2a2304c1 +mem-write: 0x8000c202 <- 0x593700f1 +mem-write: 0x8000c206 <- 0x7938001 +mem-write: 0x8000c20a <- 0x8c13300b +mem-write: 0x8000c20e <- 0x2023000b +mem-write: 0x8000c212 <- 0x24230491 +mem-write: 0x8000c216 <- 0x22230401 +mem-write: 0x8000c21a <- 0x2c230401 +mem-write: 0x8000c21e <- 0x2e230001 +mem-write: 0x8000c222 <- 0x22230001 +mem-write: 0x8000c226 <- 0x20230201 +mem-write: 0x8000c22a <- 0x26230201 +mem-write: 0x8000c22e <- 0x24230001 +mem-write: 0x8000c232 <- 0x91300f1 +mem-write: 0x8000c236 <- 0x8b933109 +mem-write: 0x8000c23a <- 0x47830004 +mem-write: 0x8000c23e <- 0x8863000c +mem-write: 0x8000c242 <- 0x4132607 +mem-write: 0x8000c246 <- 0x713000c +mem-write: 0x8000c24a <- 0x8e630250 +mem-write: 0x8000c24e <- 0x478342e7 +mem-write: 0x8000c252 <- 0x4130014 +mem-write: 0x8000c256 <- 0x9ae30014 +mem-write: 0x8000c25a <- 0xcb3fe07 +mem-write: 0x8000c25e <- 0x8634184 +mem-write: 0x8000c262 <- 0x27032584 +mem-write: 0x8000c266 <- 0x27830481 +mem-write: 0x8000c26a <- 0xa0230441 +mem-write: 0x8000c26e <- 0x8733018b +mem-write: 0x8000c272 <- 0x879300ec +mem-write: 0x8000c276 <- 0xa2230017 +mem-write: 0x8000c27a <- 0x2423019b +mem-write: 0x8000c27e <- 0x222304e1 +mem-write: 0x8000c282 <- 0x69304f1 +mem-write: 0x8000c286 <- 0x8b930070 +mem-write: 0x8000c28a <- 0xd063008b +mem-write: 0x8000c28e <- 0xae302f6 +mem-write: 0x8000c292 <- 0x6133a07 +mem-write: 0x8000c296 <- 0x85930401 +mem-write: 0x8000c29a <- 0x5130009 +mem-write: 0x8000c29e <- 0xf0ef000a +mem-write: 0x8000c2a2 <- 0x1a63d95f +mem-write: 0x8000c2a6 <- 0x8b932005 +mem-write: 0x8000c2aa <- 0x27030004 +mem-write: 0x8000c2ae <- 0x478300c1 +mem-write: 0x8000c2b2 <- 0x7330004 +mem-write: 0x8000c2b6 <- 0x26230197 +mem-write: 0x8000c2ba <- 0x8a6300e1 +mem-write: 0x8000c2be <- 0x47031e07 +mem-write: 0x8000c2c2 <- 0xc130014 +mem-write: 0x8000c2c6 <- 0xda30014 +mem-write: 0x8000c2ca <- 0xa930201 +mem-write: 0x8000c2ce <- 0x2223fff0 +mem-write: 0x8000c2d2 <- 0xb130001 +mem-write: 0x8000c2d6 <- 0xc930000 +mem-write: 0x8000c2da <- 0xd1305a0 +mem-write: 0x8000c2de <- 0x6130090 +mem-write: 0x8000c2e2 <- 0xc1302a0 +mem-write: 0x8000c2e6 <- 0x793001c +mem-write: 0x8000c2ea <- 0xe863fe07 +mem-write: 0x8000c2ee <- 0x268304fc +mem-write: 0x8000c2f2 <- 0x97930141 +mem-write: 0x8000c2f6 <- 0x87b30027 +mem-write: 0x8000c2fa <- 0xa78300d7 +mem-write: 0x8000c2fe <- 0x80670007 +mem-write: 0x8000c302 <- 0x22230007 +mem-write: 0x8000c306 <- 0x7930001 +mem-write: 0x8000c30a <- 0x2583fd07 +mem-write: 0x8000c30e <- 0x47030041 +mem-write: 0x8000c312 <- 0xc13000c +mem-write: 0x8000c316 <- 0x9693001c +mem-write: 0x8000c31a <- 0x86b30025 +mem-write: 0x8000c31e <- 0x969300b6 +mem-write: 0x8000c322 <- 0x87b30016 +mem-write: 0x8000c326 <- 0x222300d7 +mem-write: 0x8000c32a <- 0x79300f1 +mem-write: 0x8000c32e <- 0x7ee3fd07 +mem-write: 0x8000c332 <- 0x793fcfd +mem-write: 0x8000c336 <- 0xfce3fe07 +mem-write: 0x8000c33a <- 0xa63fafc +mem-write: 0x8000c33e <- 0x6231607 +mem-write: 0x8000c342 <- 0xda308e1 +mem-write: 0x8000c346 <- 0xc930201 +mem-write: 0x8000c34a <- 0xd130010 +mem-write: 0x8000c34e <- 0x4130010 +mem-write: 0x8000c352 <- 0xa9308c1 +mem-write: 0x8000c356 <- 0x7f930000 +mem-write: 0x8000c35a <- 0x8463002b +mem-write: 0x8000c35e <- 0x8c93000f +mem-write: 0x8000c362 <- 0x2703002c +mem-write: 0x8000c366 <- 0x7f130441 +mem-write: 0x8000c36a <- 0x2783084b +mem-write: 0x8000c36e <- 0x6930481 +mem-write: 0x8000c372 <- 0x86130017 +mem-write: 0x8000c376 <- 0x18630006 +mem-write: 0x8000c37a <- 0x2583000f +mem-write: 0x8000c37e <- 0x8db30041 +mem-write: 0x8000c382 <- 0x42e34195 +mem-write: 0x8000c386 <- 0x458309b0 +mem-write: 0x8000c38a <- 0x869303b1 +mem-write: 0x8000c38e <- 0x8c63008b +mem-write: 0x8000c392 <- 0x7130205 +mem-write: 0x8000c396 <- 0x879303b1 +mem-write: 0x8000c39a <- 0xa0230017 +mem-write: 0x8000c39e <- 0x71300eb +mem-write: 0x8000c3a2 <- 0xa2230010 +mem-write: 0x8000c3a6 <- 0x242300eb +mem-write: 0x8000c3aa <- 0x222304f1 +mem-write: 0x8000c3ae <- 0x71304c1 +mem-write: 0x8000c3b2 <- 0x40630070 +mem-write: 0x8000c3b6 <- 0x7137ec7 +mem-write: 0x8000c3ba <- 0x8b930006 +mem-write: 0x8000c3be <- 0x6130006 +mem-write: 0x8000c3c2 <- 0x86930016 +mem-write: 0x8000c3c6 <- 0x8e630086 +mem-write: 0x8000c3ca <- 0x713040f +mem-write: 0x8000c3ce <- 0x879303c1 +mem-write: 0x8000c3d2 <- 0xa0230027 +mem-write: 0x8000c3d6 <- 0x71300eb +mem-write: 0x8000c3da <- 0xa2230020 +mem-write: 0x8000c3de <- 0x242300eb +mem-write: 0x8000c3e2 <- 0x222304f1 +mem-write: 0x8000c3e6 <- 0x71304c1 +mem-write: 0x8000c3ea <- 0x50e30070 +mem-write: 0x8000c3ee <- 0x84e300c7 +mem-write: 0x8000c3f2 <- 0x6132a07 +mem-write: 0x8000c3f6 <- 0x85930401 +VXDRV: upload 1024 bytes to 0x8000c3fa +mem-write: 0x8000c3fa <- 0x5130009 +mem-write: 0x8000c3fe <- 0x2423000a +mem-write: 0x8000c402 <- 0xf0ef03e1 +mem-write: 0x8000c406 <- 0x1863c31f +mem-write: 0x8000c40a <- 0x27030a05 +mem-write: 0x8000c40e <- 0x27830441 +mem-write: 0x8000c412 <- 0x2f030481 +mem-write: 0x8000c416 <- 0x6930281 +mem-write: 0x8000c41a <- 0x6130541 +mem-write: 0x8000c41e <- 0x8b930017 +mem-write: 0x8000c422 <- 0x5930004 +mem-write: 0x8000c426 <- 0x6630800 +mem-write: 0x8000c42a <- 0x8ab35abf +mem-write: 0x8000c42e <- 0x426341aa +mem-write: 0x8000c432 <- 0x7b36950 +mem-write: 0x8000c436 <- 0xa02300fd +mem-write: 0x8000c43a <- 0xa223008b +mem-write: 0x8000c43e <- 0x242301ab +mem-write: 0x8000c442 <- 0x222304f1 +mem-write: 0x8000c446 <- 0x71304c1 +mem-write: 0x8000c44a <- 0x52630070 +mem-write: 0x8000c44e <- 0x8ee302c7 +mem-write: 0x8000c452 <- 0x6130a07 +mem-write: 0x8000c456 <- 0x85930401 +mem-write: 0x8000c45a <- 0x5130009 +mem-write: 0x8000c45e <- 0xf0ef000a +mem-write: 0x8000c462 <- 0x1a63bd5f +mem-write: 0x8000c466 <- 0x27830405 +mem-write: 0x8000c46a <- 0x86930481 +mem-write: 0x8000c46e <- 0x73130004 +mem-write: 0x8000c472 <- 0x863004b +mem-write: 0x8000c476 <- 0x27030003 +mem-write: 0x8000c47a <- 0xbb30041 +mem-write: 0x8000c47e <- 0x44e34197 +mem-write: 0x8000c482 <- 0x24030b70 +mem-write: 0x8000c486 <- 0x54630041 +mem-write: 0x8000c48a <- 0x84130194 +mem-write: 0x8000c48e <- 0x2703000c +mem-write: 0x8000c492 <- 0x73300c1 +mem-write: 0x8000c496 <- 0x26230087 +mem-write: 0x8000c49a <- 0x986300e1 +mem-write: 0x8000c49e <- 0x47836c07 +mem-write: 0x8000c4a2 <- 0x2223000c +mem-write: 0x8000c4a6 <- 0x8b930401 +mem-write: 0x8000c4aa <- 0x9ce30004 +mem-write: 0x8000c4ae <- 0x2783d807 +mem-write: 0x8000c4b2 <- 0x9ae30481 +mem-write: 0x8000c4b6 <- 0xd7836407 +mem-write: 0x8000c4ba <- 0xf79300c9 +mem-write: 0x8000c4be <- 0x92e30407 +mem-write: 0x8000c4c2 <- 0x20836807 +mem-write: 0x8000c4c6 <- 0x240312c1 +mem-write: 0x8000c4ca <- 0x25031281 +mem-write: 0x8000c4ce <- 0x248300c1 +mem-write: 0x8000c4d2 <- 0x29031241 +mem-write: 0x8000c4d6 <- 0x29831201 +mem-write: 0x8000c4da <- 0x2a0311c1 +mem-write: 0x8000c4de <- 0x2a831181 +mem-write: 0x8000c4e2 <- 0x2b031141 +mem-write: 0x8000c4e6 <- 0x2b831101 +mem-write: 0x8000c4ea <- 0x2c0310c1 +mem-write: 0x8000c4ee <- 0x2c831081 +mem-write: 0x8000c4f2 <- 0x2d031041 +mem-write: 0x8000c4f6 <- 0x2d831001 +mem-write: 0x8000c4fa <- 0x1130fc1 +mem-write: 0x8000c4fe <- 0x80671301 +mem-write: 0x8000c502 <- 0x5130000 +mem-write: 0x8000c506 <- 0xb0ef000a +mem-write: 0x8000c50a <- 0x2783830f +mem-write: 0x8000c50e <- 0x85130045 +mem-write: 0x8000c512 <- 0x20230007 +mem-write: 0x8000c516 <- 0xc0ef02f1 +mem-write: 0x8000c51a <- 0x793fd5f +mem-write: 0x8000c51e <- 0x5130005 +mem-write: 0x8000c522 <- 0x8413000a +mem-write: 0x8000c526 <- 0x22230007 +mem-write: 0x8000c52a <- 0xb0ef02f1 +mem-write: 0x8000c52e <- 0x278380cf +mem-write: 0x8000c532 <- 0x6130085 +mem-write: 0x8000c536 <- 0x2e2302a0 +mem-write: 0x8000c53a <- 0x18e300f1 +mem-write: 0x8000c53e <- 0x47032a04 +mem-write: 0x8000c542 <- 0xf06f000c +mem-write: 0x8000c546 <- 0x4703da1f +mem-write: 0x8000c54a <- 0x6b13000c +mem-write: 0x8000c54e <- 0xf06f020b +mem-write: 0x8000c552 <- 0x6b13d95f +mem-write: 0x8000c556 <- 0x7793010b +mem-write: 0x8000c55a <- 0x8463020b +mem-write: 0x8000c55e <- 0x27831607 +mem-write: 0x8000c562 <- 0x87930101 +mem-write: 0x8000c566 <- 0xf7930077 +mem-write: 0x8000c56a <- 0xa703ff87 +mem-write: 0x8000c56e <- 0xad030047 +mem-write: 0x8000c572 <- 0x87930007 +mem-write: 0x8000c576 <- 0x28230087 +mem-write: 0x8000c57a <- 0xc9300f1 +mem-write: 0x8000c57e <- 0x4a630007 +mem-write: 0x8000c582 <- 0x7131607 +mem-write: 0x8000c586 <- 0xd93fff0 +mem-write: 0x8000c58a <- 0x8863000b +mem-write: 0x8000c58e <- 0x673300ea +mem-write: 0x8000c592 <- 0x7d93019d +mem-write: 0x8000c596 <- 0xce3f7fb +mem-write: 0x8000c59a <- 0x96e30a07 +mem-write: 0x8000c59e <- 0x713160c +mem-write: 0x8000c5a2 <- 0x62e30090 +mem-write: 0x8000c5a6 <- 0x79317a7 +mem-write: 0x8000c5aa <- 0x7a3030d +mem-write: 0x8000c5ae <- 0x8b130ef1 +mem-write: 0x8000c5b2 <- 0xd13000d +mem-write: 0x8000c5b6 <- 0x4130010 +mem-write: 0x8000c5ba <- 0x8c930ef1 +mem-write: 0x8000c5be <- 0xd463000a +mem-write: 0x8000c5c2 <- 0xc9301aa +mem-write: 0x8000c5c6 <- 0x4783000d +mem-write: 0x8000c5ca <- 0x37b303b1 +mem-write: 0x8000c5ce <- 0x8cb300f0 +mem-write: 0x8000c5d2 <- 0xf06f00fc +mem-write: 0x8000c5d6 <- 0x8593d85f +mem-write: 0x8000c5da <- 0x5130009 +mem-write: 0x8000c5de <- 0x70ef000a +mem-write: 0x8000c5e2 <- 0x10e3d08f +mem-write: 0x8000c5e6 <- 0xd7835605 +mem-write: 0x8000c5ea <- 0x71300c9 +mem-write: 0x8000c5ee <- 0xf79300a0 +mem-write: 0x8000c5f2 <- 0x9ee301a7 +mem-write: 0x8000c5f6 <- 0x9783bee7 +mem-write: 0x8000c5fa <- 0xcae300e9 +mem-write: 0x8000c5fe <- 0x2683be07 +mem-write: 0x8000c602 <- 0x86130101 +mem-write: 0x8000c606 <- 0x8593000b +mem-write: 0x8000c60a <- 0x5130009 +mem-write: 0x8000c60e <- 0xef000a +mem-write: 0x8000c612 <- 0x26235890 +mem-write: 0x8000c616 <- 0xf06f00a1 +mem-write: 0x8000c61a <- 0x6b13eadf +mem-write: 0x8000c61e <- 0x7793010b +mem-write: 0x8000c622 <- 0x8a63020b +mem-write: 0x8000c626 <- 0x27830607 +mem-write: 0x8000c62a <- 0x87930101 +mem-write: 0x8000c62e <- 0xf7930077 +mem-write: 0x8000c632 <- 0xad03ff87 +mem-write: 0x8000c636 <- 0xac830007 +mem-write: 0x8000c63a <- 0x87930047 +mem-write: 0x8000c63e <- 0x28230087 +mem-write: 0x8000c642 <- 0x7d9300f1 +mem-write: 0x8000c646 <- 0x713bffb +mem-write: 0x8000c64a <- 0xda30000 +mem-write: 0x8000c64e <- 0x6930201 +mem-write: 0x8000c652 <- 0x8463fff0 +mem-write: 0x8000c656 <- 0x66b30cda +mem-write: 0x8000c65a <- 0xfb13019d +mem-write: 0x8000c65e <- 0x9063f7fd +mem-write: 0x8000c662 <- 0x9c635a06 +mem-write: 0x8000c666 <- 0x1863300a +mem-write: 0x8000c66a <- 0xfd137e07 +mem-write: 0x8000c66e <- 0x413001d +mem-write: 0x8000c672 <- 0x4e30f01 +mem-write: 0x8000c676 <- 0x793f40d +mem-write: 0x8000c67a <- 0x7a30300 +mem-write: 0x8000c67e <- 0x4130ef1 +mem-write: 0x8000c682 <- 0xf06f0ef1 +mem-write: 0x8000c686 <- 0xcb3f39f +mem-write: 0x8000c68a <- 0x1ce34184 +mem-write: 0x8000c68e <- 0x4783bd84 +mem-write: 0x8000c692 <- 0xf06f0004 +mem-write: 0x8000c696 <- 0x2683c29f +mem-write: 0x8000c69a <- 0x77930101 +mem-write: 0x8000c69e <- 0x8713010b +mem-write: 0x8000c6a2 <- 0x9ce30046 +mem-write: 0x8000c6a6 <- 0x77931607 +mem-write: 0x8000c6aa <- 0x88e3040b +mem-write: 0x8000c6ae <- 0x27833807 +mem-write: 0x8000c6b2 <- 0xc930101 +mem-write: 0x8000c6b6 <- 0x28230000 +mem-write: 0x8000c6ba <- 0xdd0300e1 +mem-write: 0x8000c6be <- 0xf06f0007 +mem-write: 0x8000c6c2 <- 0x2683f85f +mem-write: 0x8000c6c6 <- 0x77930101 +mem-write: 0x8000c6ca <- 0x8713010b +mem-write: 0x8000c6ce <- 0x94e30046 +mem-write: 0x8000c6d2 <- 0x77931007 +mem-write: 0x8000c6d6 <- 0x82e3040b +mem-write: 0x8000c6da <- 0x27833207 +mem-write: 0x8000c6de <- 0x28230101 +mem-write: 0x8000c6e2 <- 0x9d0300e1 +mem-write: 0x8000c6e6 <- 0x5c930007 +mem-write: 0x8000c6ea <- 0x871341fd +mem-write: 0x8000c6ee <- 0x5ae3000c +mem-write: 0x8000c6f2 <- 0x3733e807 +mem-write: 0x8000c6f6 <- 0xeb301a0 +mem-write: 0x8000c6fa <- 0x8cb34190 +mem-write: 0x8000c6fe <- 0x71340ee +mem-write: 0x8000c702 <- 0xda302d0 +mem-write: 0x8000c706 <- 0x69302e1 +mem-write: 0x8000c70a <- 0xd33fff0 +mem-write: 0x8000c70e <- 0xd9341a0 +mem-write: 0x8000c712 <- 0x713000b +mem-write: 0x8000c716 <- 0x90e30010 +mem-write: 0x8000c71a <- 0x693f4da +mem-write: 0x8000c71e <- 0xee30010 +mem-write: 0x8000c722 <- 0x693e6d7 +mem-write: 0x8000c726 <- 0x4630020 +mem-write: 0x8000c72a <- 0x41326d7 +mem-write: 0x8000c72e <- 0x97930f01 +mem-write: 0x8000c732 <- 0x771301dc +mem-write: 0x8000c736 <- 0x5d13007d +mem-write: 0x8000c73a <- 0x713003d +mem-write: 0x8000c73e <- 0xed330307 +mem-write: 0x8000c742 <- 0xdc9301a7 +mem-write: 0x8000c746 <- 0xfa3003c +mem-write: 0x8000c74a <- 0x67b3fee4 +mem-write: 0x8000c74e <- 0x613019d +mem-write: 0x8000c752 <- 0x4130004 +mem-write: 0x8000c756 <- 0x9ce3fff4 +mem-write: 0x8000c75a <- 0xf793fc07 +mem-write: 0x8000c75e <- 0x8263001d +mem-write: 0x8000c762 <- 0x7932607 +mem-write: 0x8000c766 <- 0xe630300 +mem-write: 0x8000c76a <- 0x61324f7 +mem-write: 0x8000c76e <- 0xfa3ffe6 +mem-write: 0x8000c772 <- 0x793fef4 +mem-write: 0x8000c776 <- 0x8d330f01 +mem-write: 0x8000c77a <- 0x8b1340c7 +mem-write: 0x8000c77e <- 0x413000d +mem-write: 0x8000c782 <- 0xf06f0006 +mem-write: 0x8000c786 <- 0x70efe39f +mem-write: 0x8000c78a <- 0xf06fc6df +mem-write: 0x8000c78e <- 0x2783a05f +mem-write: 0x8000c792 <- 0xda30101 +mem-write: 0x8000c796 <- 0xa4030201 +mem-write: 0x8000c79a <- 0x8d930007 +mem-write: 0x8000c79e <- 0xe30047 +mem-write: 0x8000c7a2 <- 0x7932204 +mem-write: 0x8000c7a6 <- 0x88e3fff0 +mem-write: 0x8000c7aa <- 0x861312fa +mem-write: 0x8000c7ae <- 0x593000a +mem-write: 0x8000c7b2 <- 0x5130000 +mem-write: 0x8000c7b6 <- 0xb0ef0004 +mem-write: 0x8000c7ba <- 0xe3f18f +mem-write: 0x8000c7be <- 0xd333605 +mem-write: 0x8000c7c2 <- 0x28234085 +mem-write: 0x8000c7c6 <- 0xa9301b1 +mem-write: 0x8000c7ca <- 0xf06f0000 +mem-write: 0x8000c7ce <- 0x2703df1f +mem-write: 0x8000c7d2 <- 0xda30101 +mem-write: 0x8000c7d6 <- 0xc930201 +mem-write: 0x8000c7da <- 0x27830010 +mem-write: 0x8000c7de <- 0x7130007 +mem-write: 0x8000c7e2 <- 0x28230047 +mem-write: 0x8000c7e6 <- 0x62300e1 +mem-write: 0x8000c7ea <- 0xd1308f1 +mem-write: 0x8000c7ee <- 0x4130010 +mem-write: 0x8000c7f2 <- 0xf06f08c1 +mem-write: 0x8000c7f6 <- 0x2783b61f +VXDRV: upload 1024 bytes to 0x8000c7fa +mem-write: 0x8000c7fa <- 0x87370101 +mem-write: 0x8000c7fe <- 0x4713ffff +mem-write: 0x8000c802 <- 0xad038307 +mem-write: 0x8000c806 <- 0x87930007 +mem-write: 0x8000c80a <- 0x28230047 +mem-write: 0x8000c80e <- 0x57b700f1 +mem-write: 0x8000c812 <- 0x87938001 +mem-write: 0x8000c816 <- 0x1e23a3c7 +mem-write: 0x8000c81a <- 0xc9302e1 +mem-write: 0x8000c81e <- 0x6d930000 +mem-write: 0x8000c822 <- 0x2c23002b +mem-write: 0x8000c826 <- 0x71300f1 +mem-write: 0x8000c82a <- 0xf06f0020 +mem-write: 0x8000c82e <- 0x4703e21f +mem-write: 0x8000c832 <- 0x793000c +mem-write: 0x8000c836 <- 0x6e306c0 +mem-write: 0x8000c83a <- 0x6b1316f7 +mem-write: 0x8000c83e <- 0xf06f010b +mem-write: 0x8000c842 <- 0x4703aa5f +mem-write: 0x8000c846 <- 0x793000c +mem-write: 0x8000c84a <- 0x4e30680 +mem-write: 0x8000c84e <- 0x6b1314f7 +mem-write: 0x8000c852 <- 0xf06f040b +mem-write: 0x8000c856 <- 0x6d93a91f +mem-write: 0x8000c85a <- 0xf793010b +mem-write: 0x8000c85e <- 0x8463020d +mem-write: 0x8000c862 <- 0x27836007 +mem-write: 0x8000c866 <- 0x7130101 +mem-write: 0x8000c86a <- 0x87930010 +mem-write: 0x8000c86e <- 0xf7930077 +mem-write: 0x8000c872 <- 0xad03ff87 +mem-write: 0x8000c876 <- 0xac830007 +mem-write: 0x8000c87a <- 0x87930047 +mem-write: 0x8000c87e <- 0x28230087 +mem-write: 0x8000c882 <- 0xf06f00f1 +mem-write: 0x8000c886 <- 0x4703dc9f +mem-write: 0x8000c88a <- 0x6b13000c +mem-write: 0x8000c88e <- 0xf06f080b +mem-write: 0x8000c892 <- 0x2683a55f +mem-write: 0x8000c896 <- 0x47030101 +mem-write: 0x8000c89a <- 0xa783000c +mem-write: 0x8000c89e <- 0x86930006 +mem-write: 0x8000c8a2 <- 0x28230046 +mem-write: 0x8000c8a6 <- 0x222300d1 +mem-write: 0x8000c8aa <- 0xdce300f1 +mem-write: 0x8000c8ae <- 0x7b3a207 +mem-write: 0x8000c8b2 <- 0x222340f0 +mem-write: 0x8000c8b6 <- 0x6b1300f1 +mem-write: 0x8000c8ba <- 0xf06f004b +mem-write: 0x8000c8be <- 0x4703a29f +mem-write: 0x8000c8c2 <- 0x6b13000c +mem-write: 0x8000c8c6 <- 0xf06f001b +mem-write: 0x8000c8ca <- 0x4783a1df +mem-write: 0x8000c8ce <- 0x470303b1 +mem-write: 0x8000c8d2 <- 0x98e3000c +mem-write: 0x8000c8d6 <- 0x793a007 +mem-write: 0x8000c8da <- 0xda30200 +mem-write: 0x8000c8de <- 0xf06f02f1 +mem-write: 0x8000c8e2 <- 0x4703a05f +mem-write: 0x8000c8e6 <- 0x6b13000c +mem-write: 0x8000c8ea <- 0xf06f004b +mem-write: 0x8000c8ee <- 0x7939f9f +mem-write: 0x8000c8f2 <- 0x470302b0 +mem-write: 0x8000c8f6 <- 0xda3000c +mem-write: 0x8000c8fa <- 0xf06f02f1 +mem-write: 0x8000c8fe <- 0x47039e9f +mem-write: 0x8000c902 <- 0x693000c +mem-write: 0x8000c906 <- 0xae3001c +mem-write: 0x8000c90a <- 0x79324c7 +mem-write: 0x8000c90e <- 0x8c13fd07 +mem-write: 0x8000c912 <- 0xa930006 +mem-write: 0x8000c916 <- 0x68e30000 +mem-write: 0x8000c91a <- 0x47039cfd +mem-write: 0x8000c91e <- 0x9693000c +mem-write: 0x8000c922 <- 0x8ab3002a +mem-write: 0x8000c926 <- 0x9a930156 +mem-write: 0x8000c92a <- 0x8ab3001a +mem-write: 0x8000c92e <- 0x79300fa +mem-write: 0x8000c932 <- 0xc13fd07 +mem-write: 0x8000c936 <- 0x72e3001c +mem-write: 0x8000c93a <- 0xf06ffefd +mem-write: 0x8000c93e <- 0x26839adf +mem-write: 0x8000c942 <- 0x77930101 +mem-write: 0x8000c946 <- 0xa703020b +mem-write: 0x8000c94a <- 0x86930006 +mem-write: 0x8000c94e <- 0x28230046 +mem-write: 0x8000c952 <- 0x9a6300d1 +mem-write: 0x8000c956 <- 0x77936a07 +mem-write: 0x8000c95a <- 0x9ce3010b +mem-write: 0x8000c95e <- 0x77930407 +mem-write: 0x8000c962 <- 0x90e3040b +mem-write: 0x8000c966 <- 0x73131407 +mem-write: 0x8000c96a <- 0x4e3200b +mem-write: 0x8000c96e <- 0x27830403 +mem-write: 0x8000c972 <- 0x2300c1 +mem-write: 0x8000c976 <- 0xf06f00f7 +mem-write: 0x8000c97a <- 0x6938c5f +mem-write: 0x8000c97e <- 0xee30010 +mem-write: 0x8000c982 <- 0x6931ad7 +mem-write: 0x8000c986 <- 0xd930020 +mem-write: 0x8000c98a <- 0x10e3000b +mem-write: 0x8000c98e <- 0x2683dad7 +mem-write: 0x8000c992 <- 0x4130181 +mem-write: 0x8000c996 <- 0x77930f01 +mem-write: 0x8000c99a <- 0x87b300fd +mem-write: 0x8000c99e <- 0xc70300f6 +mem-write: 0x8000c9a2 <- 0x5d130007 +mem-write: 0x8000c9a6 <- 0x9793004d +mem-write: 0x8000c9aa <- 0xed3301cc +mem-write: 0x8000c9ae <- 0xdc9301a7 +mem-write: 0x8000c9b2 <- 0xfa3004c +mem-write: 0x8000c9b6 <- 0x67b3fee4 +mem-write: 0x8000c9ba <- 0x413019d +mem-write: 0x8000c9be <- 0x9ce3fff4 +mem-write: 0x8000c9c2 <- 0x793fc07 +mem-write: 0x8000c9c6 <- 0x8d330f01 +mem-write: 0x8000c9ca <- 0x8b134087 +mem-write: 0x8000c9ce <- 0xf06f000d +mem-write: 0x8000c9d2 <- 0x2583bedf +mem-write: 0x8000c9d6 <- 0x8db30041 +mem-write: 0x8000c9da <- 0x58e34195 +mem-write: 0x8000c9de <- 0x593a5b0 +mem-write: 0x8000c9e2 <- 0xd6e30100 +mem-write: 0x8000c9e6 <- 0xe9317b5 +mem-write: 0x8000c9ea <- 0xf130100 +mem-write: 0x8000c9ee <- 0x6f0070 +mem-write: 0x8000c9f2 <- 0x6130180 +mem-write: 0x8000c9f6 <- 0x8b930027 +mem-write: 0x8000c9fa <- 0x8713008b +mem-write: 0x8000c9fe <- 0x8d930006 +mem-write: 0x8000ca02 <- 0xdc63ff0d +mem-write: 0x8000ca06 <- 0x879305be +mem-write: 0x8000ca0a <- 0x6930107 +mem-write: 0x8000ca0e <- 0xa0230017 +mem-write: 0x8000ca12 <- 0xa223012b +mem-write: 0x8000ca16 <- 0x242301db +mem-write: 0x8000ca1a <- 0x222304f1 +mem-write: 0x8000ca1e <- 0x5ae304d1 +mem-write: 0x8000ca22 <- 0x8063fcdf +mem-write: 0x8000ca26 <- 0x6131607 +mem-write: 0x8000ca2a <- 0x85930401 +mem-write: 0x8000ca2e <- 0x5130009 +mem-write: 0x8000ca32 <- 0xf0ef000a +mem-write: 0x8000ca36 <- 0x10e3e00f +mem-write: 0x8000ca3a <- 0x2703a805 +mem-write: 0x8000ca3e <- 0xe930441 +mem-write: 0x8000ca42 <- 0x8d930100 +mem-write: 0x8000ca46 <- 0x2783ff0d +mem-write: 0x8000ca4a <- 0x8b930481 +mem-write: 0x8000ca4e <- 0x6130004 +mem-write: 0x8000ca52 <- 0xf130017 +mem-write: 0x8000ca56 <- 0xc8e30070 +mem-write: 0x8000ca5a <- 0x593fbbe +mem-write: 0x8000ca5e <- 0x85130006 +mem-write: 0x8000ca62 <- 0x87b3008b +mem-write: 0x8000ca66 <- 0xa02301b7 +mem-write: 0x8000ca6a <- 0xa223012b +mem-write: 0x8000ca6e <- 0x242301bb +mem-write: 0x8000ca72 <- 0x222304f1 +mem-write: 0x8000ca76 <- 0x71304b1 +mem-write: 0x8000ca7a <- 0x5a630070 +mem-write: 0x8000ca7e <- 0x866352b7 +mem-write: 0x8000ca82 <- 0x6137e07 +mem-write: 0x8000ca86 <- 0x85930401 +mem-write: 0x8000ca8a <- 0x5130009 +mem-write: 0x8000ca8e <- 0xf0ef000a +mem-write: 0x8000ca92 <- 0x12e3da4f +mem-write: 0x8000ca96 <- 0x2703a205 +mem-write: 0x8000ca9a <- 0x8ab30441 +mem-write: 0x8000ca9e <- 0x278341aa +mem-write: 0x8000caa2 <- 0x6930481 +mem-write: 0x8000caa6 <- 0x6130541 +mem-write: 0x8000caaa <- 0x8b930017 +mem-write: 0x8000caae <- 0x52e30004 +mem-write: 0x8000cab2 <- 0x5939950 +mem-write: 0x8000cab6 <- 0xd0630100 +mem-write: 0x8000caba <- 0x8937b55 +mem-write: 0x8000cabe <- 0xd930100 +mem-write: 0x8000cac2 <- 0x6f0070 +mem-write: 0x8000cac6 <- 0x6130180 +mem-write: 0x8000caca <- 0x8b930027 +mem-write: 0x8000cace <- 0x8713008b +mem-write: 0x8000cad2 <- 0x8a930006 +mem-write: 0x8000cad6 <- 0xda63ff0a +mem-write: 0x8000cada <- 0x87930558 +mem-write: 0x8000cade <- 0x6930107 +mem-write: 0x8000cae2 <- 0xa0230017 +mem-write: 0x8000cae6 <- 0xa223012b +mem-write: 0x8000caea <- 0x2423011b +mem-write: 0x8000caee <- 0x222304f1 +mem-write: 0x8000caf2 <- 0xdae304d1 +mem-write: 0x8000caf6 <- 0x8263fcdd +mem-write: 0x8000cafa <- 0x6130607 +mem-write: 0x8000cafe <- 0x85930401 +mem-write: 0x8000cb02 <- 0x5130009 +mem-write: 0x8000cb06 <- 0xf0ef000a +mem-write: 0x8000cb0a <- 0x16e3d2cf +mem-write: 0x8000cb0e <- 0x27039a05 +mem-write: 0x8000cb12 <- 0x8930441 +mem-write: 0x8000cb16 <- 0x8a930100 +mem-write: 0x8000cb1a <- 0x2783ff0a +mem-write: 0x8000cb1e <- 0x8b930481 +mem-write: 0x8000cb22 <- 0x6130004 +mem-write: 0x8000cb26 <- 0xcae30017 +mem-write: 0x8000cb2a <- 0x8593fb58 +mem-write: 0x8000cb2e <- 0x87b3008b +mem-write: 0x8000cb32 <- 0xa0230157 +mem-write: 0x8000cb36 <- 0xa223012b +mem-write: 0x8000cb3a <- 0x2423015b +mem-write: 0x8000cb3e <- 0x222304f1 +mem-write: 0x8000cb42 <- 0x71304c1 +mem-write: 0x8000cb46 <- 0x46630070 +mem-write: 0x8000cb4a <- 0x6132cc7 +mem-write: 0x8000cb4e <- 0x86930016 +mem-write: 0x8000cb52 <- 0x8b930085 +mem-write: 0x8000cb56 <- 0xf06f0005 +mem-write: 0x8000cb5a <- 0x6138ddf +mem-write: 0x8000cb5e <- 0x7130010 +mem-write: 0x8000cb62 <- 0x8b930000 +mem-write: 0x8000cb66 <- 0xf06f0004 +mem-write: 0x8000cb6a <- 0x613f6df +mem-write: 0x8000cb6e <- 0x85930401 +mem-write: 0x8000cb72 <- 0x5130009 +mem-write: 0x8000cb76 <- 0xf0ef000a +mem-write: 0x8000cb7a <- 0x2e3cbcf +mem-write: 0x8000cb7e <- 0xf06f9205 +mem-write: 0x8000cb82 <- 0x613939f +mem-write: 0x8000cb86 <- 0x7130010 +mem-write: 0x8000cb8a <- 0x8b930000 +mem-write: 0x8000cb8e <- 0xf06f0004 +mem-write: 0x8000cb92 <- 0x8c63e71f +mem-write: 0x8000cb96 <- 0x6133007 +mem-write: 0x8000cb9a <- 0x85930401 +mem-write: 0x8000cb9e <- 0x5130009 +mem-write: 0x8000cba2 <- 0x2623000a +mem-write: 0x8000cba6 <- 0x242303e1 +mem-write: 0x8000cbaa <- 0xf0ef03f1 +mem-write: 0x8000cbae <- 0x14e3c88f +mem-write: 0x8000cbb2 <- 0x27039005 +mem-write: 0x8000cbb6 <- 0x27830441 +mem-write: 0x8000cbba <- 0x2f030481 +mem-write: 0x8000cbbe <- 0x2f8302c1 +mem-write: 0x8000cbc2 <- 0x6930281 +mem-write: 0x8000cbc6 <- 0x6130541 +mem-write: 0x8000cbca <- 0x8b930017 +mem-write: 0x8000cbce <- 0xf06f0004 +mem-write: 0x8000cbd2 <- 0x793ff8f +mem-write: 0x8000cbd6 <- 0x262303c1 +mem-write: 0x8000cbda <- 0x79304f1 +mem-write: 0x8000cbde <- 0x28230020 +mem-write: 0x8000cbe2 <- 0x61304f1 +mem-write: 0x8000cbe6 <- 0x6930010 +mem-write: 0x8000cbea <- 0x7130541 +mem-write: 0x8000cbee <- 0x8b930006 +mem-write: 0x8000cbf2 <- 0x6130006 +mem-write: 0x8000cbf6 <- 0x86930017 +VXDRV: upload 1024 bytes to 0x8000cbfa +mem-write: 0x8000cbfa <- 0xf06f008b +mem-write: 0x8000cbfe <- 0xd93829f +mem-write: 0x8000cc02 <- 0xf06f000b +mem-write: 0x8000cc06 <- 0x613b19f +mem-write: 0x8000cc0a <- 0x50630100 +mem-write: 0x8000cc0e <- 0x861373b6 +mem-write: 0x8000cc12 <- 0xe93000b +mem-write: 0x8000cc16 <- 0xb930100 +mem-write: 0x8000cc1a <- 0x2930004 +mem-write: 0x8000cc1e <- 0x84130070 +mem-write: 0x8000cc22 <- 0x24230009 +mem-write: 0x8000cc26 <- 0x899303f1 +mem-write: 0x8000cc2a <- 0xd93000d +mem-write: 0x8000cc2e <- 0x8c13000c +mem-write: 0x8000cc32 <- 0xa93000a +mem-write: 0x8000cc36 <- 0x6f000f +mem-write: 0x8000cc3a <- 0x51301c0 +mem-write: 0x8000cc3e <- 0x6130027 +mem-write: 0x8000cc42 <- 0x87130086 +mem-write: 0x8000cc46 <- 0x89930006 +mem-write: 0x8000cc4a <- 0xde63ff09 +mem-write: 0x8000cc4e <- 0x693053e +mem-write: 0x8000cc52 <- 0x25830017 +mem-write: 0x8000cc56 <- 0x87930081 +mem-write: 0x8000cc5a <- 0x22230107 +mem-write: 0x8000cc5e <- 0x202301d6 +mem-write: 0x8000cc62 <- 0x242300b6 +mem-write: 0x8000cc66 <- 0x222304f1 +mem-write: 0x8000cc6a <- 0xd8e304d1 +mem-write: 0x8000cc6e <- 0x8663fcd2 +mem-write: 0x8000cc72 <- 0x6130807 +mem-write: 0x8000cc76 <- 0x5930401 +mem-write: 0x8000cc7a <- 0x5130004 +mem-write: 0x8000cc7e <- 0xf0ef000a +mem-write: 0x8000cc82 <- 0x1663bb4f +mem-write: 0x8000cc86 <- 0x27034c05 +mem-write: 0x8000cc8a <- 0xe930441 +mem-write: 0x8000cc8e <- 0x89930100 +mem-write: 0x8000cc92 <- 0x2783ff09 +mem-write: 0x8000cc96 <- 0x86130481 +mem-write: 0x8000cc9a <- 0x5130004 +mem-write: 0x8000cc9e <- 0x2930017 +mem-write: 0x8000cca2 <- 0xc6e30070 +mem-write: 0x8000cca6 <- 0x2f83fb3e +mem-write: 0x8000ccaa <- 0x8f130281 +mem-write: 0x8000ccae <- 0x593000a +mem-write: 0x8000ccb2 <- 0xa930005 +mem-write: 0x8000ccb6 <- 0x8c13000c +mem-write: 0x8000ccba <- 0x8d93000d +mem-write: 0x8000ccbe <- 0x9930009 +mem-write: 0x8000ccc2 <- 0x84130004 +mem-write: 0x8000ccc6 <- 0xb93000b +mem-write: 0x8000ccca <- 0x27030006 +mem-write: 0x8000ccce <- 0x87b30081 +mem-write: 0x8000ccd2 <- 0xa22301b7 +mem-write: 0x8000ccd6 <- 0xa02301bb +mem-write: 0x8000ccda <- 0x242300eb +mem-write: 0x8000ccde <- 0x222304f1 +mem-write: 0x8000cce2 <- 0x71304b1 +mem-write: 0x8000cce6 <- 0x42630070 +mem-write: 0x8000ccea <- 0x8b931eb7 +mem-write: 0x8000ccee <- 0x8613008b +mem-write: 0x8000ccf2 <- 0x87130015 +mem-write: 0x8000ccf6 <- 0xf06f0005 +mem-write: 0x8000ccfa <- 0x713e90f +mem-write: 0x8000ccfe <- 0x5130000 +mem-write: 0x8000cd02 <- 0x86130010 +mem-write: 0x8000cd06 <- 0xf06f0004 +mem-write: 0x8000cd0a <- 0x2223f41f +mem-write: 0x8000cd0e <- 0x73130401 +mem-write: 0x8000cd12 <- 0x263004b +mem-write: 0x8000cd16 <- 0x27030e03 +mem-write: 0x8000cd1a <- 0xbb30041 +mem-write: 0x8000cd1e <- 0x5c634197 +mem-write: 0x8000cd22 <- 0x86930d70 +mem-write: 0x8000cd26 <- 0x7130004 +mem-write: 0x8000cd2a <- 0x26030100 +mem-write: 0x8000cd2e <- 0x52630441 +mem-write: 0x8000cd32 <- 0xd136177 +mem-write: 0x8000cd36 <- 0xd930100 +mem-write: 0x8000cd3a <- 0x6f0070 +mem-write: 0x8000cd3e <- 0x5130180 +mem-write: 0x8000cd42 <- 0x86930026 +mem-write: 0x8000cd46 <- 0x6130086 +mem-write: 0x8000cd4a <- 0x8b930007 +mem-write: 0x8000cd4e <- 0x5a63ff0b +mem-write: 0x8000cd52 <- 0x2583057d +mem-write: 0x8000cd56 <- 0x87930081 +mem-write: 0x8000cd5a <- 0x7130107 +mem-write: 0x8000cd5e <- 0xa0230016 +mem-write: 0x8000cd62 <- 0xa22300b6 +mem-write: 0x8000cd66 <- 0x242301a6 +mem-write: 0x8000cd6a <- 0x222304f1 +mem-write: 0x8000cd6e <- 0xd8e304e1 +mem-write: 0x8000cd72 <- 0x8a63fced +mem-write: 0x8000cd76 <- 0x6130607 +mem-write: 0x8000cd7a <- 0x85930401 +mem-write: 0x8000cd7e <- 0x5130009 +mem-write: 0x8000cd82 <- 0xf0ef000a +mem-write: 0x8000cd86 <- 0x1863ab0f +mem-write: 0x8000cd8a <- 0x2603f205 +mem-write: 0x8000cd8e <- 0x8b930441 +mem-write: 0x8000cd92 <- 0x2783ff0b +mem-write: 0x8000cd96 <- 0x86930481 +mem-write: 0x8000cd9a <- 0x5130004 +mem-write: 0x8000cd9e <- 0x4ae30016 +mem-write: 0x8000cda2 <- 0x593fb7d +mem-write: 0x8000cda6 <- 0x27030005 +mem-write: 0x8000cdaa <- 0x87b30081 +mem-write: 0x8000cdae <- 0xa2230177 +mem-write: 0x8000cdb2 <- 0xa0230176 +mem-write: 0x8000cdb6 <- 0x242300e6 +mem-write: 0x8000cdba <- 0x222304f1 +mem-write: 0x8000cdbe <- 0x71304b1 +mem-write: 0x8000cdc2 <- 0x50630070 +mem-write: 0x8000cdc6 <- 0x8863ecb7 +mem-write: 0x8000cdca <- 0x6130207 +mem-write: 0x8000cdce <- 0x85930401 +mem-write: 0x8000cdd2 <- 0x5130009 +mem-write: 0x8000cdd6 <- 0xf0ef000a +mem-write: 0x8000cdda <- 0x1e63a5cf +mem-write: 0x8000cdde <- 0x2783ec05 +mem-write: 0x8000cde2 <- 0xf06f0481 +mem-write: 0x8000cde6 <- 0x513ea0f +mem-write: 0x8000cdea <- 0x6130010 +mem-write: 0x8000cdee <- 0x86930000 +mem-write: 0x8000cdf2 <- 0xf06f0004 +mem-write: 0x8000cdf6 <- 0x2403f59f +mem-write: 0x8000cdfa <- 0x54630041 +mem-write: 0x8000cdfe <- 0x84130194 +mem-write: 0x8000ce02 <- 0x2783000c +mem-write: 0x8000ce06 <- 0x87b300c1 +mem-write: 0x8000ce0a <- 0x26230087 +mem-write: 0x8000ce0e <- 0xf06f00f1 +mem-write: 0x8000ce12 <- 0x8263e90f +mem-write: 0x8000ce16 <- 0x6133407 +mem-write: 0x8000ce1a <- 0x85930401 +mem-write: 0x8000ce1e <- 0x5130009 +mem-write: 0x8000ce22 <- 0xf0ef000a +mem-write: 0x8000ce26 <- 0x1863a10f +mem-write: 0x8000ce2a <- 0x2603e805 +mem-write: 0x8000ce2e <- 0x27830441 +mem-write: 0x8000ce32 <- 0x6930481 +mem-write: 0x8000ce36 <- 0x6130541 +mem-write: 0x8000ce3a <- 0x8b930016 +mem-write: 0x8000ce3e <- 0xf06f0004 +mem-write: 0x8000ce42 <- 0x2223df4f +mem-write: 0x8000ce46 <- 0x8b930401 +mem-write: 0x8000ce4a <- 0xf06f0004 +mem-write: 0x8000ce4e <- 0x9c63c60f +mem-write: 0x8000ce52 <- 0x8b13f40a +mem-write: 0x8000ce56 <- 0xa93000d +mem-write: 0x8000ce5a <- 0xd130000 +mem-write: 0x8000ce5e <- 0x4130000 +mem-write: 0x8000ce62 <- 0xf06f0f01 +mem-write: 0x8000ce66 <- 0x2683f58f +mem-write: 0x8000ce6a <- 0xf7930101 +mem-write: 0x8000ce6e <- 0x8713010d +mem-write: 0x8000ce72 <- 0x98630046 +mem-write: 0x8000ce76 <- 0xf7931407 +mem-write: 0x8000ce7a <- 0x8063040d +mem-write: 0x8000ce7e <- 0x27833a07 +mem-write: 0x8000ce82 <- 0xc930101 +mem-write: 0x8000ce86 <- 0x28230000 +mem-write: 0x8000ce8a <- 0xdd0300e1 +mem-write: 0x8000ce8e <- 0x7130007 +mem-write: 0x8000ce92 <- 0xf06f0010 +mem-write: 0x8000ce96 <- 0x693fb8f +mem-write: 0x8000ce9a <- 0x6130541 +mem-write: 0x8000ce9e <- 0x7130010 +mem-write: 0x8000cea2 <- 0x8b930000 +mem-write: 0x8000cea6 <- 0xf06f0004 +mem-write: 0x8000ceaa <- 0x8063d7cf +mem-write: 0x8000ceae <- 0x793180f +mem-write: 0x8000ceb2 <- 0x262303c1 +mem-write: 0x8000ceb6 <- 0x79304f1 +mem-write: 0x8000ceba <- 0x28230020 +mem-write: 0x8000cebe <- 0x71304f1 +mem-write: 0x8000cec2 <- 0xb930010 +mem-write: 0x8000cec6 <- 0xf06f0541 +mem-write: 0x8000ceca <- 0x8263d2df +mem-write: 0x8000cece <- 0x6132207 +mem-write: 0x8000ced2 <- 0x85930401 +mem-write: 0x8000ced6 <- 0x5130009 +mem-write: 0x8000ceda <- 0x2623000a +mem-write: 0x8000cede <- 0x242303e1 +mem-write: 0x8000cee2 <- 0xf0ef03f1 +mem-write: 0x8000cee6 <- 0x1863950f +mem-write: 0x8000ceea <- 0x2703dc05 +mem-write: 0x8000ceee <- 0x27830441 +mem-write: 0x8000cef2 <- 0x2f030481 +mem-write: 0x8000cef6 <- 0x2f8302c1 +mem-write: 0x8000cefa <- 0x8b930281 +mem-write: 0x8000cefe <- 0x6130004 +mem-write: 0x8000cf02 <- 0xf06f0017 +mem-write: 0x8000cf06 <- 0xf793c84f +mem-write: 0x8000cf0a <- 0x2423400d +mem-write: 0x8000cf0e <- 0x26230341 +mem-write: 0x8000cf12 <- 0x8a130331 +mem-write: 0x8000cf16 <- 0x993000c +mem-write: 0x8000cf1a <- 0xb13000d +mem-write: 0x8000cf1e <- 0x2d030000 +mem-write: 0x8000cf22 <- 0x41301c1 +mem-write: 0x8000cf26 <- 0x8c930f01 +mem-write: 0x8000cf2a <- 0x6f0007 +mem-write: 0x8000cf2e <- 0x6130240 +mem-write: 0x8000cf32 <- 0x69300a0 +mem-write: 0x8000cf36 <- 0x85130000 +mem-write: 0x8000cf3a <- 0x5930009 +mem-write: 0x8000cf3e <- 0x30ef000a +mem-write: 0x8000cf42 <- 0xe634a80 +mem-write: 0x8000cf46 <- 0x993300a +mem-write: 0x8000cf4a <- 0x8a130005 +mem-write: 0x8000cf4e <- 0x6130005 +mem-write: 0x8000cf52 <- 0x69300a0 +mem-write: 0x8000cf56 <- 0x85130000 +mem-write: 0x8000cf5a <- 0x5930009 +mem-write: 0x8000cf5e <- 0x30ef000a +mem-write: 0x8000cf62 <- 0x5130bd0 +mem-write: 0x8000cf66 <- 0xfa30305 +mem-write: 0x8000cf6a <- 0xb13fea4 +mem-write: 0x8000cf6e <- 0x413001b +mem-write: 0x8000cf72 <- 0x8ee3fff4 +mem-write: 0x8000cf76 <- 0x4683fa0c +mem-write: 0x8000cf7a <- 0x9ae3000d +mem-write: 0x8000cf7e <- 0x793fb66 +mem-write: 0x8000cf82 <- 0x6e30ff0 +mem-write: 0x8000cf86 <- 0x1463fafb +mem-write: 0x8000cf8a <- 0x793180a +mem-write: 0x8000cf8e <- 0xe0630090 +mem-write: 0x8000cf92 <- 0x7931937 +mem-write: 0x8000cf96 <- 0x2e230f01 +mem-write: 0x8000cf9a <- 0x2a0301a1 +mem-write: 0x8000cf9e <- 0x29830281 +mem-write: 0x8000cfa2 <- 0x8d3302c1 +mem-write: 0x8000cfa6 <- 0x8b134087 +mem-write: 0x8000cfaa <- 0xf06f000d +mem-write: 0x8000cfae <- 0x8613e10f +mem-write: 0x8000cfb2 <- 0x6930015 +mem-write: 0x8000cfb6 <- 0x87130085 +mem-write: 0x8000cfba <- 0xb930005 +mem-write: 0x8000cfbe <- 0xf06f0005 +mem-write: 0x8000cfc2 <- 0x2823c6cf +mem-write: 0x8000cfc6 <- 0xad0300e1 +mem-write: 0x8000cfca <- 0xc930006 +mem-write: 0x8000cfce <- 0x7130000 +mem-write: 0x8000cfd2 <- 0xf06f0010 +mem-write: 0x8000cfd6 <- 0xad03e78f +mem-write: 0x8000cfda <- 0x28230006 +mem-write: 0x8000cfde <- 0x5c9300e1 +mem-write: 0x8000cfe2 <- 0x871341fd +mem-write: 0x8000cfe6 <- 0xf06f000c +mem-write: 0x8000cfea <- 0x2783d98f +mem-write: 0x8000cfee <- 0x470301c1 +mem-write: 0x8000cff2 <- 0x8863000c +mem-write: 0x8000cff6 <- 0xc783ae07 +VXDRV: upload 1024 bytes to 0x8000cffa +mem-write: 0x8000cffa <- 0x84630007 +mem-write: 0x8000cffe <- 0x6b13ae07 +mem-write: 0x8000d002 <- 0xf06f400b +mem-write: 0x8000d006 <- 0x2683ae0f +mem-write: 0x8000d00a <- 0xd79300c1 +mem-write: 0x8000d00e <- 0x202341f6 +mem-write: 0x8000d012 <- 0x222300d7 +mem-write: 0x8000d016 <- 0xf06f00f7 +mem-write: 0x8000d01a <- 0xad03a24f +mem-write: 0x8000d01e <- 0xc930006 +mem-write: 0x8000d022 <- 0x28230000 +mem-write: 0x8000d026 <- 0xf06f00e1 +mem-write: 0x8000d02a <- 0x713e1cf +mem-write: 0x8000d02e <- 0x6930000 +mem-write: 0x8000d032 <- 0x6130541 +mem-write: 0x8000d036 <- 0x8b930010 +mem-write: 0x8000d03a <- 0xf06f0004 +mem-write: 0x8000d03e <- 0xd93be8f +mem-write: 0x8000d042 <- 0xf06f000b +mem-write: 0x8000d046 <- 0x57b7819f +mem-write: 0x8000d04a <- 0x87938001 +mem-write: 0x8000d04e <- 0x2c23a507 +mem-write: 0x8000d052 <- 0x779300f1 +mem-write: 0x8000d056 <- 0x8063020b +mem-write: 0x8000d05a <- 0x27830607 +mem-write: 0x8000d05e <- 0x87930101 +mem-write: 0x8000d062 <- 0xf7930077 +mem-write: 0x8000d066 <- 0xad03ff87 +mem-write: 0x8000d06a <- 0xac830007 +mem-write: 0x8000d06e <- 0x87930047 +mem-write: 0x8000d072 <- 0x28230087 +mem-write: 0x8000d076 <- 0x769300f1 +mem-write: 0x8000d07a <- 0x8e63001b +mem-write: 0x8000d07e <- 0x66b30006 +mem-write: 0x8000d082 <- 0x8a63019d +mem-write: 0x8000d086 <- 0x6930006 +mem-write: 0x8000d08a <- 0xe230300 +mem-write: 0x8000d08e <- 0xea302d1 +mem-write: 0x8000d092 <- 0x6b1302e1 +mem-write: 0x8000d096 <- 0x7d93002b +mem-write: 0x8000d09a <- 0x713bffb +mem-write: 0x8000d09e <- 0xf06f0020 +mem-write: 0x8000d0a2 <- 0x57b7dacf +mem-write: 0x8000d0a6 <- 0x87938001 +mem-write: 0x8000d0aa <- 0x2c23a3c7 +mem-write: 0x8000d0ae <- 0x779300f1 +mem-write: 0x8000d0b2 <- 0x94e3020b +mem-write: 0x8000d0b6 <- 0x2603fa07 +mem-write: 0x8000d0ba <- 0x77930101 +mem-write: 0x8000d0be <- 0x693010b +mem-write: 0x8000d0c2 <- 0x8a630046 +mem-write: 0x8000d0c6 <- 0x2d030a07 +mem-write: 0x8000d0ca <- 0xc930006 +mem-write: 0x8000d0ce <- 0x28230000 +mem-write: 0x8000d0d2 <- 0xf06f00d1 +mem-write: 0x8000d0d6 <- 0x513fa5f +mem-write: 0x8000d0da <- 0xc0ef0004 +mem-write: 0x8000d0de <- 0xd13c10f +mem-write: 0x8000d0e2 <- 0x28230005 +mem-write: 0x8000d0e6 <- 0xa9301b1 +mem-write: 0x8000d0ea <- 0xf06f0000 +mem-write: 0x8000d0ee <- 0x4703cd0f +mem-write: 0x8000d0f2 <- 0x1a6303b1 +mem-write: 0x8000d0f6 <- 0x9ee31807 +mem-write: 0x8000d0fa <- 0x713ac0f +mem-write: 0x8000d0fe <- 0x6130000 +mem-write: 0x8000d102 <- 0x6930010 +mem-write: 0x8000d106 <- 0x8b930541 +mem-write: 0x8000d10a <- 0xf06f0004 +mem-write: 0x8000d10e <- 0x2783b18f +mem-write: 0x8000d112 <- 0x25830241 +mem-write: 0x8000d116 <- 0xb130201 +mem-write: 0x8000d11a <- 0x4330000 +mem-write: 0x8000d11e <- 0x861340f4 +mem-write: 0x8000d122 <- 0x5130007 +mem-write: 0x8000d126 <- 0xc0ef0004 +mem-write: 0x8000d12a <- 0x4583c50f +mem-write: 0x8000d12e <- 0x613001d +mem-write: 0x8000d132 <- 0x69300a0 +mem-write: 0x8000d136 <- 0x37330000 +mem-write: 0x8000d13a <- 0x851300b0 +mem-write: 0x8000d13e <- 0x5930009 +mem-write: 0x8000d142 <- 0xd33000a +mem-write: 0x8000d146 <- 0x30ef00ed +mem-write: 0x8000d14a <- 0xf06f2a00 +mem-write: 0x8000d14e <- 0x993dfdf +mem-write: 0x8000d152 <- 0xf06f0004 +mem-write: 0x8000d156 <- 0x713b64f +mem-write: 0x8000d15a <- 0x7930010 +mem-write: 0x8000d15e <- 0x2623000d +mem-write: 0x8000d162 <- 0x28230481 +mem-write: 0x8000d166 <- 0x242305a1 +mem-write: 0x8000d16a <- 0x222305a1 +mem-write: 0x8000d16e <- 0x69304e1 +mem-write: 0x8000d172 <- 0xf06f0541 +mem-write: 0x8000d176 <- 0x7793afcf +mem-write: 0x8000d17a <- 0x8263040b +mem-write: 0x8000d17e <- 0x27830607 +mem-write: 0x8000d182 <- 0xc930101 +mem-write: 0x8000d186 <- 0x28230000 +mem-write: 0x8000d18a <- 0xdd0300d1 +mem-write: 0x8000d18e <- 0xf06f0007 +mem-write: 0x8000d192 <- 0x4703ee9f +mem-write: 0x8000d196 <- 0x6b13001c +mem-write: 0x8000d19a <- 0xc13200b +mem-write: 0x8000d19e <- 0xf06f001c +mem-write: 0x8000d1a2 <- 0x4703944f +mem-write: 0x8000d1a6 <- 0x6b13001c +mem-write: 0x8000d1aa <- 0xc13020b +mem-write: 0x8000d1ae <- 0xf06f001c +mem-write: 0x8000d1b2 <- 0x2783934f +mem-write: 0x8000d1b6 <- 0x202300c1 +mem-write: 0x8000d1ba <- 0xf06f00f7 +mem-write: 0x8000d1be <- 0x793880f +mem-write: 0x8000d1c2 <- 0x8d130060 +mem-write: 0x8000d1c6 <- 0xec63000a +mem-write: 0x8000d1ca <- 0x5e370b57 +mem-write: 0x8000d1ce <- 0xc938001 +mem-write: 0x8000d1d2 <- 0x2823000d +mem-write: 0x8000d1d6 <- 0x41301b1 +mem-write: 0x8000d1da <- 0xf06fa64e +mem-write: 0x8000d1de <- 0x7793978f +mem-write: 0x8000d1e2 <- 0x8863200b +mem-write: 0x8000d1e6 <- 0x27831007 +mem-write: 0x8000d1ea <- 0xc930101 +mem-write: 0x8000d1ee <- 0x28230000 +mem-write: 0x8000d1f2 <- 0xcd0300d1 +mem-write: 0x8000d1f6 <- 0xf06f0007 +mem-write: 0x8000d1fa <- 0x7793e81f +mem-write: 0x8000d1fe <- 0x8e63200b +mem-write: 0x8000d202 <- 0x27830c07 +mem-write: 0x8000d206 <- 0x28230101 +mem-write: 0x8000d20a <- 0x8d0300e1 +mem-write: 0x8000d20e <- 0x5c930007 +mem-write: 0x8000d212 <- 0x871341fd +mem-write: 0x8000d216 <- 0xf06f000c +mem-write: 0x8000d21a <- 0xf793b68f +mem-write: 0x8000d21e <- 0x8263200d +mem-write: 0x8000d222 <- 0x27830a07 +mem-write: 0x8000d226 <- 0xc930101 +mem-write: 0x8000d22a <- 0x28230000 +mem-write: 0x8000d22e <- 0xcd0300e1 +mem-write: 0x8000d232 <- 0x7130007 +mem-write: 0x8000d236 <- 0xf06f0010 +mem-write: 0x8000d23a <- 0x7793c14f +mem-write: 0x8000d23e <- 0x8863200b +mem-write: 0x8000d242 <- 0x27830607 +mem-write: 0x8000d246 <- 0xc930101 +mem-write: 0x8000d24a <- 0x28230000 +mem-write: 0x8000d24e <- 0xcd0300e1 +mem-write: 0x8000d252 <- 0xf06f0007 +mem-write: 0x8000d256 <- 0x8593bf0f +mem-write: 0x8000d25a <- 0xf06f0006 +mem-write: 0x8000d25e <- 0x7938d5f +mem-write: 0x8000d262 <- 0xe2e30090 +mem-write: 0x8000d266 <- 0xf06fcf37 +mem-write: 0x8000d26a <- 0x693d2df +mem-write: 0x8000d26e <- 0x6130541 +mem-write: 0x8000d272 <- 0x7130010 +mem-write: 0x8000d276 <- 0x8b930000 +mem-write: 0x8000d27a <- 0xf06f0004 +mem-write: 0x8000d27e <- 0xd139b0f +mem-write: 0x8000d282 <- 0xf06f0060 +mem-write: 0x8000d286 <- 0x793f49f +mem-write: 0x8000d28a <- 0x262303b1 +mem-write: 0x8000d28e <- 0x79304f1 +mem-write: 0x8000d292 <- 0x28230010 +mem-write: 0x8000d296 <- 0x61304f1 +mem-write: 0x8000d29a <- 0x6930010 +mem-write: 0x8000d29e <- 0xf06f0541 +mem-write: 0x8000d2a2 <- 0x2783918f +mem-write: 0x8000d2a6 <- 0x102300c1 +mem-write: 0x8000d2aa <- 0xe06f00f7 +mem-write: 0x8000d2ae <- 0x2783f91f +mem-write: 0x8000d2b2 <- 0xc930101 +mem-write: 0x8000d2b6 <- 0x28230000 +mem-write: 0x8000d2ba <- 0xad0300e1 +mem-write: 0x8000d2be <- 0xf06f0007 +mem-write: 0x8000d2c2 <- 0x2783b84f +mem-write: 0x8000d2c6 <- 0xc930101 +mem-write: 0x8000d2ca <- 0x28230000 +mem-write: 0x8000d2ce <- 0xad0300e1 +mem-write: 0x8000d2d2 <- 0x7130007 +mem-write: 0x8000d2d6 <- 0xf06f0010 +mem-write: 0x8000d2da <- 0x2783b74f +mem-write: 0x8000d2de <- 0x28230101 +mem-write: 0x8000d2e2 <- 0xad0300e1 +mem-write: 0x8000d2e6 <- 0x5c930007 +mem-write: 0x8000d2ea <- 0x871341fd +mem-write: 0x8000d2ee <- 0xf06f000c +mem-write: 0x8000d2f2 <- 0x2783a90f +mem-write: 0x8000d2f6 <- 0xc930101 +mem-write: 0x8000d2fa <- 0x28230000 +mem-write: 0x8000d2fe <- 0xad0300d1 +mem-write: 0x8000d302 <- 0xf06f0007 +mem-write: 0x8000d306 <- 0x613d75f +mem-write: 0x8000d30a <- 0x85930401 +mem-write: 0x8000d30e <- 0x5130009 +mem-write: 0x8000d312 <- 0xe0ef000a +mem-write: 0x8000d316 <- 0xf06fd21f +mem-write: 0x8000d31a <- 0x8d139a0f +mem-write: 0x8000d31e <- 0x2823000a +mem-write: 0x8000d322 <- 0xa9301b1 +mem-write: 0x8000d326 <- 0xf06f0000 +mem-write: 0x8000d32a <- 0x8593a94f +mem-write: 0x8000d32e <- 0xf06f0006 +mem-write: 0x8000d332 <- 0x59399df +mem-write: 0x8000d336 <- 0xf06f0016 +mem-write: 0x8000d33a <- 0xd93a71f +mem-write: 0x8000d33e <- 0xf06f000b +mem-write: 0x8000d342 <- 0x793a68f +mem-write: 0x8000d346 <- 0x2623fff0 +mem-write: 0x8000d34a <- 0xf06f00f1 +mem-write: 0x8000d34e <- 0x8513978f +mem-write: 0x8000d352 <- 0x5930006 +mem-write: 0x8000d356 <- 0xf06f0006 +mem-write: 0x8000d35a <- 0x2783f0cf +mem-write: 0x8000d35e <- 0xaa830101 +mem-write: 0x8000d362 <- 0x87930007 +mem-write: 0x8000d366 <- 0xd4630047 +mem-write: 0x8000d36a <- 0xa93000a +mem-write: 0x8000d36e <- 0x4703fff0 +mem-write: 0x8000d372 <- 0x2823001c +mem-write: 0x8000d376 <- 0x8c1300f1 +mem-write: 0x8000d37a <- 0xe06f0006 +mem-write: 0x8000d37e <- 0x793f69f +mem-write: 0x8000d382 <- 0xa5030005 +mem-write: 0x8000d386 <- 0x6931d81 +mem-write: 0x8000d38a <- 0x86130006 +mem-write: 0x8000d38e <- 0x85930005 +mem-write: 0x8000d392 <- 0xe06f0007 +mem-write: 0x8000d396 <- 0xd783da9f +mem-write: 0x8000d39a <- 0xae0300c5 +mem-write: 0x8000d39e <- 0xd3030645 +mem-write: 0x8000d3a2 <- 0xa88300e5 +mem-write: 0x8000d3a6 <- 0xa80301c5 +mem-write: 0x8000d3aa <- 0x1130245 +mem-write: 0x8000d3ae <- 0xf793b801 +mem-write: 0x8000d3b2 <- 0x713ffd7 +mem-write: 0x8000d3b6 <- 0x2c234000 +mem-write: 0x8000d3ba <- 0x1a234681 +mem-write: 0x8000d3be <- 0x841300f1 +mem-write: 0x8000d3c2 <- 0x7930005 +mem-write: 0x8000d3c6 <- 0x5930701 +mem-write: 0x8000d3ca <- 0x2a230081 +mem-write: 0x8000d3ce <- 0x28234691 +mem-write: 0x8000d3d2 <- 0x2e234721 +mem-write: 0x8000d3d6 <- 0x9134611 +mem-write: 0x8000d3da <- 0x26230005 +mem-write: 0x8000d3de <- 0x1b2307c1 +mem-write: 0x8000d3e2 <- 0x22230061 +mem-write: 0x8000d3e6 <- 0x26230311 +mem-write: 0x8000d3ea <- 0x24230301 +mem-write: 0x8000d3ee <- 0x2c2300f1 +mem-write: 0x8000d3f2 <- 0x282300f1 +mem-write: 0x8000d3f6 <- 0x2e2300e1 +VXDRV: upload 1024 bytes to 0x8000d3fa +mem-write: 0x8000d3fa <- 0x202300e1 +mem-write: 0x8000d3fe <- 0xe0ef0201 +mem-write: 0x8000d402 <- 0x493d3df +mem-write: 0x8000d406 <- 0x5c630005 +mem-write: 0x8000d40a <- 0x57830205 +mem-write: 0x8000d40e <- 0xf7930141 +mem-write: 0x8000d412 <- 0x88630407 +mem-write: 0x8000d416 <- 0x57830007 +mem-write: 0x8000d41a <- 0xe79300c4 +mem-write: 0x8000d41e <- 0x16230407 +mem-write: 0x8000d422 <- 0x208300f4 +mem-write: 0x8000d426 <- 0x240347c1 +mem-write: 0x8000d42a <- 0x29034781 +mem-write: 0x8000d42e <- 0x85134701 +mem-write: 0x8000d432 <- 0x24830004 +mem-write: 0x8000d436 <- 0x1134741 +mem-write: 0x8000d43a <- 0x80674801 +mem-write: 0x8000d43e <- 0x5930000 +mem-write: 0x8000d442 <- 0x5130081 +mem-write: 0x8000d446 <- 0x60ef0009 +mem-write: 0x8000d44a <- 0xe3c11f +mem-write: 0x8000d44e <- 0x493fc05 +mem-write: 0x8000d452 <- 0xf06ffff0 +mem-write: 0x8000d456 <- 0x113fb9f +mem-write: 0x8000d45a <- 0x8713ff01 +mem-write: 0x8000d45e <- 0x24230005 +mem-write: 0x8000d462 <- 0x22230081 +mem-write: 0x8000d466 <- 0x5930091 +mem-write: 0x8000d46a <- 0x4130006 +mem-write: 0x8000d46e <- 0x86130005 +mem-write: 0x8000d472 <- 0x5130006 +mem-write: 0x8000d476 <- 0x26230007 +mem-write: 0x8000d47a <- 0xa4230011 +mem-write: 0x8000d47e <- 0x30ef2401 +mem-write: 0x8000d482 <- 0x793858f +mem-write: 0x8000d486 <- 0xc63fff0 +mem-write: 0x8000d48a <- 0x208300f5 +mem-write: 0x8000d48e <- 0x240300c1 +mem-write: 0x8000d492 <- 0x24830081 +mem-write: 0x8000d496 <- 0x1130041 +mem-write: 0x8000d49a <- 0x80670101 +mem-write: 0x8000d49e <- 0xa7830000 +mem-write: 0x8000d4a2 <- 0x84e32481 +mem-write: 0x8000d4a6 <- 0x2083fe07 +mem-write: 0x8000d4aa <- 0x202300c1 +mem-write: 0x8000d4ae <- 0x240300f4 +mem-write: 0x8000d4b2 <- 0x24830081 +mem-write: 0x8000d4b6 <- 0x1130041 +mem-write: 0x8000d4ba <- 0x80670101 +mem-write: 0x8000d4be <- 0xa7030000 +mem-write: 0x8000d4c2 <- 0x1131d81 +mem-write: 0x8000d4c6 <- 0x8793ff01 +mem-write: 0x8000d4ca <- 0x8130006 +mem-write: 0x8000d4ce <- 0x26230006 +mem-write: 0x8000d4d2 <- 0x28830011 +mem-write: 0x8000d4d6 <- 0x69300c7 +mem-write: 0x8000d4da <- 0x87130005 +mem-write: 0x8000d4de <- 0x86130005 +mem-write: 0x8000d4e2 <- 0x630007 +mem-write: 0x8000d4e6 <- 0x57b70208 +mem-write: 0x8000d4ea <- 0x87938001 +mem-write: 0x8000d4ee <- 0x55b73207 +mem-write: 0x8000d4f2 <- 0x85938001 +mem-write: 0x8000d4f6 <- 0x85133305 +mem-write: 0x8000d4fa <- 0xef0008 +mem-write: 0x8000d4fe <- 0x20ef28c0 +mem-write: 0x8000d502 <- 0x58373a50 +mem-write: 0x8000d506 <- 0x7938001 +mem-write: 0x8000d50a <- 0x813a188 +mem-write: 0x8000d50e <- 0xf06fa188 +mem-write: 0x8000d512 <- 0x113fe1f +mem-write: 0x8000d516 <- 0x693ff01 +mem-write: 0x8000d51a <- 0x6130006 +mem-write: 0x8000d51e <- 0x26230000 +mem-write: 0x8000d522 <- 0xf0ef0011 +mem-write: 0x8000d526 <- 0x85b3f9df +mem-write: 0x8000d52a <- 0x11302c5 +mem-write: 0x8000d52e <- 0x2423ff01 +mem-write: 0x8000d532 <- 0x26230081 +mem-write: 0x8000d536 <- 0xa0ef0011 +mem-write: 0x8000d53a <- 0x413a00f +mem-write: 0x8000d53e <- 0x8630005 +mem-write: 0x8000d542 <- 0x26030205 +mem-write: 0x8000d546 <- 0x713ffc5 +mem-write: 0x8000d54a <- 0x76130240 +mem-write: 0x8000d54e <- 0x613ffc6 +mem-write: 0x8000d552 <- 0x6063ffc6 +mem-write: 0x8000d556 <- 0x69306c7 +mem-write: 0x8000d55a <- 0x7930130 +mem-write: 0x8000d55e <- 0xe2630005 +mem-write: 0x8000d562 <- 0xa02302c6 +mem-write: 0x8000d566 <- 0xa2230007 +mem-write: 0x8000d56a <- 0xa4230007 +mem-write: 0x8000d56e <- 0x20830007 +mem-write: 0x8000d572 <- 0x51300c1 +mem-write: 0x8000d576 <- 0x24030004 +mem-write: 0x8000d57a <- 0x1130081 +mem-write: 0x8000d57e <- 0x80670101 +mem-write: 0x8000d582 <- 0x20230000 +mem-write: 0x8000d586 <- 0x22230005 +mem-write: 0x8000d58a <- 0x7930005 +mem-write: 0x8000d58e <- 0xf06301b0 +mem-write: 0x8000d592 <- 0x242304c7 +mem-write: 0x8000d596 <- 0x26230005 +mem-write: 0x8000d59a <- 0x7930005 +mem-write: 0x8000d59e <- 0x12e30105 +mem-write: 0x8000d5a2 <- 0x2823fce6 +mem-write: 0x8000d5a6 <- 0x7930005 +mem-write: 0x8000d5aa <- 0x2a230185 +mem-write: 0x8000d5ae <- 0xf06f0005 +mem-write: 0x8000d5b2 <- 0x593fb5f +mem-write: 0x8000d5b6 <- 0x30ef0000 +mem-write: 0x8000d5ba <- 0x2083861f +mem-write: 0x8000d5be <- 0x51300c1 +mem-write: 0x8000d5c2 <- 0x24030004 +mem-write: 0x8000d5c6 <- 0x1130081 +mem-write: 0x8000d5ca <- 0x80670101 +mem-write: 0x8000d5ce <- 0x7930000 +mem-write: 0x8000d5d2 <- 0xf06f0085 +mem-write: 0x8000d5d6 <- 0x113f91f +mem-write: 0x8000d5da <- 0x2423ff01 +mem-write: 0x8000d5de <- 0x22230081 +mem-write: 0x8000d5e2 <- 0x4130091 +mem-write: 0x8000d5e6 <- 0x85130005 +mem-write: 0x8000d5ea <- 0x26230005 +mem-write: 0x8000d5ee <- 0xa4230011 +mem-write: 0x8000d5f2 <- 0x20ef2401 +mem-write: 0x8000d5f6 <- 0x793d31f +mem-write: 0x8000d5fa <- 0xc63fff0 +mem-write: 0x8000d5fe <- 0x208300f5 +mem-write: 0x8000d602 <- 0x240300c1 +mem-write: 0x8000d606 <- 0x24830081 +mem-write: 0x8000d60a <- 0x1130041 +mem-write: 0x8000d60e <- 0x80670101 +mem-write: 0x8000d612 <- 0xa7830000 +mem-write: 0x8000d616 <- 0x84e32481 +mem-write: 0x8000d61a <- 0x2083fe07 +mem-write: 0x8000d61e <- 0x202300c1 +mem-write: 0x8000d622 <- 0x240300f4 +mem-write: 0x8000d626 <- 0x24830081 +mem-write: 0x8000d62a <- 0x1130041 +mem-write: 0x8000d62e <- 0x80670101 +mem-write: 0x8000d632 <- 0x1130000 +mem-write: 0x8000d636 <- 0x2623ff01 +mem-write: 0x8000d63a <- 0x24230011 +mem-write: 0x8000d63e <- 0x22230081 +mem-write: 0x8000d642 <- 0x20230091 +mem-write: 0x8000d646 <- 0x80630121 +mem-write: 0x8000d64a <- 0x84130205 +mem-write: 0x8000d64e <- 0x4930005 +mem-write: 0x8000d652 <- 0x6630005 +mem-write: 0x8000d656 <- 0x27830005 +mem-write: 0x8000d65a <- 0x8c630385 +mem-write: 0x8000d65e <- 0x17830a07 +mem-write: 0x8000d662 <- 0x926300c4 +mem-write: 0x8000d666 <- 0x20830207 +mem-write: 0x8000d66a <- 0x240300c1 +mem-write: 0x8000d66e <- 0x9130081 +mem-write: 0x8000d672 <- 0x24830000 +mem-write: 0x8000d676 <- 0x5130041 +mem-write: 0x8000d67a <- 0x29030009 +mem-write: 0x8000d67e <- 0x1130001 +mem-write: 0x8000d682 <- 0x80670101 +mem-write: 0x8000d686 <- 0x5930000 +mem-write: 0x8000d68a <- 0x85130004 +mem-write: 0x8000d68e <- 0x60ef0004 +mem-write: 0x8000d692 <- 0x2783f6cf +mem-write: 0x8000d696 <- 0x91302c4 +mem-write: 0x8000d69a <- 0x8a630005 +mem-write: 0x8000d69e <- 0x25830007 +mem-write: 0x8000d6a2 <- 0x851301c4 +mem-write: 0x8000d6a6 <- 0x80e70004 +mem-write: 0x8000d6aa <- 0x4c630007 +mem-write: 0x8000d6ae <- 0x57830605 +mem-write: 0x8000d6b2 <- 0xf79300c4 +mem-write: 0x8000d6b6 <- 0x9e630807 +mem-write: 0x8000d6ba <- 0x25830607 +mem-write: 0x8000d6be <- 0x8c630304 +mem-write: 0x8000d6c2 <- 0x7930005 +mem-write: 0x8000d6c6 <- 0x86630404 +mem-write: 0x8000d6ca <- 0x851300f5 +mem-write: 0x8000d6ce <- 0x60ef0004 +mem-write: 0x8000d6d2 <- 0x2823e95f +mem-write: 0x8000d6d6 <- 0x25830204 +mem-write: 0x8000d6da <- 0x88630444 +mem-write: 0x8000d6de <- 0x85130005 +mem-write: 0x8000d6e2 <- 0x60ef0004 +mem-write: 0x8000d6e6 <- 0x2223e81f +mem-write: 0x8000d6ea <- 0x60ef0404 +mem-write: 0x8000d6ee <- 0x1623d19f +mem-write: 0x8000d6f2 <- 0x60ef0004 +mem-write: 0x8000d6f6 <- 0x2083d15f +mem-write: 0x8000d6fa <- 0x240300c1 +mem-write: 0x8000d6fe <- 0x24830081 +mem-write: 0x8000d702 <- 0x5130041 +mem-write: 0x8000d706 <- 0x29030009 +mem-write: 0x8000d70a <- 0x1130001 +mem-write: 0x8000d70e <- 0x80670101 +mem-write: 0x8000d712 <- 0x60ef0000 +mem-write: 0x8000d716 <- 0x1783ce1f +mem-write: 0x8000d71a <- 0x86e300c4 +mem-write: 0x8000d71e <- 0xf06ff407 +mem-write: 0x8000d722 <- 0x5783f69f +mem-write: 0x8000d726 <- 0x91300c4 +mem-write: 0x8000d72a <- 0xf793fff0 +mem-write: 0x8000d72e <- 0x86e30807 +mem-write: 0x8000d732 <- 0x2583f807 +mem-write: 0x8000d736 <- 0x85130104 +mem-write: 0x8000d73a <- 0x60ef0004 +mem-write: 0x8000d73e <- 0xf06fe29f +mem-write: 0x8000d742 <- 0x593f7df +mem-write: 0x8000d746 <- 0xa5030005 +mem-write: 0x8000d74a <- 0xf06f1d81 +mem-write: 0x8000d74e <- 0x113ee9f +mem-write: 0x8000d752 <- 0x313fc01 +mem-write: 0x8000d756 <- 0x262302c1 +mem-write: 0x8000d75a <- 0x69302d1 +mem-write: 0x8000d75e <- 0x2e230003 +mem-write: 0x8000d762 <- 0x28230011 +mem-write: 0x8000d766 <- 0x2a2302e1 +mem-write: 0x8000d76a <- 0x2c2302f1 +mem-write: 0x8000d76e <- 0x2e230301 +mem-write: 0x8000d772 <- 0x26230311 +mem-write: 0x8000d776 <- 0xe0ef0061 +mem-write: 0x8000d77a <- 0x20839c5f +mem-write: 0x8000d77e <- 0x11301c1 +mem-write: 0x8000d782 <- 0x80670401 +mem-write: 0x8000d786 <- 0xe130000 +mem-write: 0x8000d78a <- 0x1130005 +mem-write: 0x8000d78e <- 0xa503fc01 +mem-write: 0x8000d792 <- 0x3131d81 +mem-write: 0x8000d796 <- 0x24230281 +mem-write: 0x8000d79a <- 0x262302c1 +mem-write: 0x8000d79e <- 0x861302d1 +mem-write: 0x8000d7a2 <- 0x6930005 +mem-write: 0x8000d7a6 <- 0x5930003 +mem-write: 0x8000d7aa <- 0x2e23000e +mem-write: 0x8000d7ae <- 0x28230011 +mem-write: 0x8000d7b2 <- 0x2a2302e1 +mem-write: 0x8000d7b6 <- 0x2c2302f1 +mem-write: 0x8000d7ba <- 0x2e230301 +mem-write: 0x8000d7be <- 0x26230311 +mem-write: 0x8000d7c2 <- 0xe0ef0061 +mem-write: 0x8000d7c6 <- 0x2083979f +mem-write: 0x8000d7ca <- 0x11301c1 +mem-write: 0x8000d7ce <- 0x80670401 +mem-write: 0x8000d7d2 <- 0x1130000 +mem-write: 0x8000d7d6 <- 0x2423fd01 +mem-write: 0x8000d7da <- 0x2e230281 +mem-write: 0x8000d7de <- 0x28230131 +mem-write: 0x8000d7e2 <- 0x26230161 +mem-write: 0x8000d7e6 <- 0x22230211 +mem-write: 0x8000d7ea <- 0x20230291 +mem-write: 0x8000d7ee <- 0x2c230321 +mem-write: 0x8000d7f2 <- 0x2a230141 +mem-write: 0x8000d7f6 <- 0xb130151 +VXDRV: upload 1024 bytes to 0x8000d7fa +mem-write: 0x8000d7fa <- 0x89930005 +mem-write: 0x8000d7fe <- 0x4130005 +mem-write: 0x8000d802 <- 0xef0006 +mem-write: 0x8000d806 <- 0x7937880 +mem-write: 0x8000d80a <- 0x10630010 +mem-write: 0x8000d80e <- 0x879302f5 +mem-write: 0x8000d812 <- 0x713fff9 +mem-write: 0x8000d816 <- 0x6a630fe0 +mem-write: 0x8000d81a <- 0xf71300f7 +mem-write: 0x8000d81e <- 0x6230ff9 +mem-write: 0x8000d822 <- 0x91300e1 +mem-write: 0x8000d826 <- 0x6f0010 +mem-write: 0x8000d82a <- 0x69302c0 +mem-write: 0x8000d82e <- 0x861305c4 +mem-write: 0x8000d832 <- 0x5930009 +mem-write: 0x8000d836 <- 0x51300c1 +mem-write: 0x8000d83a <- 0x20ef000b +mem-write: 0x8000d83e <- 0x7937300 +mem-write: 0x8000d842 <- 0x913fff0 +mem-write: 0x8000d846 <- 0x4630005 +mem-write: 0x8000d84a <- 0xe630af5 +mem-write: 0x8000d84e <- 0x47030805 +mem-write: 0x8000d852 <- 0x49300c1 +mem-write: 0x8000d856 <- 0xa130000 +mem-write: 0x8000d85a <- 0xa93fff0 +mem-write: 0x8000d85e <- 0x6f00a0 +mem-write: 0x8000d862 <- 0x27830280 +mem-write: 0x8000d866 <- 0x86930004 +mem-write: 0x8000d86a <- 0x20230017 +mem-write: 0x8000d86e <- 0x802300d4 +mem-write: 0x8000d872 <- 0x849300e7 +mem-write: 0x8000d876 <- 0x7930014 +mem-write: 0x8000d87a <- 0x87b300c1 +mem-write: 0x8000d87e <- 0xf4630097 +mem-write: 0x8000d882 <- 0xc7030724 +mem-write: 0x8000d886 <- 0x27830007 +mem-write: 0x8000d88a <- 0x87930084 +mem-write: 0x8000d88e <- 0x2423fff7 +mem-write: 0x8000d892 <- 0xd8e300f4 +mem-write: 0x8000d896 <- 0x2683fc07 +mem-write: 0x8000d89a <- 0x5930184 +mem-write: 0x8000d89e <- 0x6130007 +mem-write: 0x8000d8a2 <- 0x5130004 +mem-write: 0x8000d8a6 <- 0xc463000b +mem-write: 0x8000d8aa <- 0x1ce300d7 +mem-write: 0x8000d8ae <- 0x20effb57 +mem-write: 0x8000d8b2 <- 0x10e35240 +mem-write: 0x8000d8b6 <- 0x913fd45 +mem-write: 0x8000d8ba <- 0x2083fff0 +mem-write: 0x8000d8be <- 0x240302c1 +mem-write: 0x8000d8c2 <- 0x24830281 +mem-write: 0x8000d8c6 <- 0x29830241 +mem-write: 0x8000d8ca <- 0x2a0301c1 +mem-write: 0x8000d8ce <- 0x2a830181 +mem-write: 0x8000d8d2 <- 0x2b030141 +mem-write: 0x8000d8d6 <- 0x5130101 +mem-write: 0x8000d8da <- 0x29030009 +mem-write: 0x8000d8de <- 0x1130201 +mem-write: 0x8000d8e2 <- 0x80670301 +mem-write: 0x8000d8e6 <- 0x89130000 +mem-write: 0x8000d8ea <- 0xf06f0009 +mem-write: 0x8000d8ee <- 0x5783fd1f +mem-write: 0x8000d8f2 <- 0xe79300c4 +mem-write: 0x8000d8f6 <- 0x16230407 +mem-write: 0x8000d8fa <- 0xf06f00f4 +mem-write: 0x8000d8fe <- 0x1783fc1f +mem-write: 0x8000d902 <- 0x971300c6 +mem-write: 0x8000d906 <- 0x40630127 +mem-write: 0x8000d90a <- 0x27030207 +mem-write: 0x8000d90e <- 0x26b70646 +mem-write: 0x8000d912 <- 0xe7b30000 +mem-write: 0x8000d916 <- 0x26b700d7 +mem-write: 0x8000d91a <- 0x67330000 +mem-write: 0x8000d91e <- 0x162300d7 +mem-write: 0x8000d922 <- 0x222300f6 +mem-write: 0x8000d926 <- 0xf06f06e6 +mem-write: 0x8000d92a <- 0x113eadf +mem-write: 0x8000d92e <- 0x2c23fe01 +mem-write: 0x8000d932 <- 0xa4030081 +mem-write: 0x8000d936 <- 0x2e231d81 +mem-write: 0x8000d93a <- 0x86130011 +mem-write: 0x8000d93e <- 0x5930005 +mem-write: 0x8000d942 <- 0x6630005 +mem-write: 0x8000d946 <- 0x27830004 +mem-write: 0x8000d94a <- 0x80630384 +mem-write: 0x8000d94e <- 0x17830407 +mem-write: 0x8000d952 <- 0x971300c6 +mem-write: 0x8000d956 <- 0x40630127 +mem-write: 0x8000d95a <- 0x27030207 +mem-write: 0x8000d95e <- 0x26b70646 +mem-write: 0x8000d962 <- 0xe7b30000 +mem-write: 0x8000d966 <- 0x26b700d7 +mem-write: 0x8000d96a <- 0x67330000 +mem-write: 0x8000d96e <- 0x162300d7 +mem-write: 0x8000d972 <- 0x222300f6 +mem-write: 0x8000d976 <- 0x51306e6 +mem-write: 0x8000d97a <- 0x24030004 +mem-write: 0x8000d97e <- 0x20830181 +mem-write: 0x8000d982 <- 0x11301c1 +mem-write: 0x8000d986 <- 0xf06f0201 +mem-write: 0x8000d98a <- 0x2423e4df +mem-write: 0x8000d98e <- 0x51300a1 +mem-write: 0x8000d992 <- 0x26230004 +mem-write: 0x8000d996 <- 0x60ef00c1 +mem-write: 0x8000d99a <- 0x2603a5df +mem-write: 0x8000d99e <- 0x258300c1 +mem-write: 0x8000d9a2 <- 0xf06f0081 +mem-write: 0x8000d9a6 <- 0x113fadf +mem-write: 0x8000d9aa <- 0x8713ff01 +mem-write: 0x8000d9ae <- 0x24230005 +mem-write: 0x8000d9b2 <- 0x22230081 +mem-write: 0x8000d9b6 <- 0x4130091 +mem-write: 0x8000d9ba <- 0x5930005 +mem-write: 0x8000d9be <- 0x5130006 +mem-write: 0x8000d9c2 <- 0x26230007 +mem-write: 0x8000d9c6 <- 0xa4230011 +mem-write: 0x8000d9ca <- 0x20ef2401 +mem-write: 0x8000d9ce <- 0x79395df +mem-write: 0x8000d9d2 <- 0xc63fff0 +mem-write: 0x8000d9d6 <- 0x208300f5 +mem-write: 0x8000d9da <- 0x240300c1 +mem-write: 0x8000d9de <- 0x24830081 +mem-write: 0x8000d9e2 <- 0x1130041 +mem-write: 0x8000d9e6 <- 0x80670101 +mem-write: 0x8000d9ea <- 0xa7830000 +mem-write: 0x8000d9ee <- 0x84e32481 +mem-write: 0x8000d9f2 <- 0x2083fe07 +mem-write: 0x8000d9f6 <- 0x202300c1 +mem-write: 0x8000d9fa <- 0x240300f4 +mem-write: 0x8000d9fe <- 0x24830081 +mem-write: 0x8000da02 <- 0x1130041 +mem-write: 0x8000da06 <- 0x80670101 +mem-write: 0x8000da0a <- 0x27830000 +mem-write: 0x8000da0e <- 0x8e630086 +mem-write: 0x8000da12 <- 0xd7833207 +mem-write: 0x8000da16 <- 0x11300c5 +mem-write: 0x8000da1a <- 0x2423fd01 +mem-write: 0x8000da1e <- 0x2c230281 +mem-write: 0x8000da22 <- 0x2a230141 +mem-write: 0x8000da26 <- 0x26230151 +mem-write: 0x8000da2a <- 0x22230211 +mem-write: 0x8000da2e <- 0x20230291 +mem-write: 0x8000da32 <- 0x2e230321 +mem-write: 0x8000da36 <- 0x28230131 +mem-write: 0x8000da3a <- 0x26230161 +mem-write: 0x8000da3e <- 0x24230171 +mem-write: 0x8000da42 <- 0x22230181 +mem-write: 0x8000da46 <- 0x20230191 +mem-write: 0x8000da4a <- 0xf71301a1 +mem-write: 0x8000da4e <- 0xa130087 +mem-write: 0x8000da52 <- 0xa930006 +mem-write: 0x8000da56 <- 0x84130005 +mem-write: 0x8000da5a <- 0x6630005 +mem-write: 0x8000da5e <- 0xa7030807 +mem-write: 0x8000da62 <- 0x2630105 +mem-write: 0x8000da66 <- 0xf7130807 +mem-write: 0x8000da6a <- 0x24830027 +mem-write: 0x8000da6e <- 0xc63000a +mem-write: 0x8000da72 <- 0x27830807 +mem-write: 0x8000da76 <- 0x25830244 +mem-write: 0x8000da7a <- 0xb3701c4 +mem-write: 0x8000da7e <- 0x9938000 +mem-write: 0x8000da82 <- 0x9130000 +mem-write: 0x8000da86 <- 0x4b130000 +mem-write: 0x8000da8a <- 0x8613c00b +mem-write: 0x8000da8e <- 0x85130009 +mem-write: 0x8000da92 <- 0x263000a +mem-write: 0x8000da96 <- 0x6930409 +mem-write: 0x8000da9a <- 0x74630009 +mem-write: 0x8000da9e <- 0x693012b +mem-write: 0x8000daa2 <- 0x80e7000b +mem-write: 0x8000daa6 <- 0x58630007 +mem-write: 0x8000daaa <- 0x278328a0 +mem-write: 0x8000daae <- 0x89b3008a +mem-write: 0x8000dab2 <- 0x93300a9 +mem-write: 0x8000dab6 <- 0x853340a9 +mem-write: 0x8000daba <- 0x242340a7 +mem-write: 0x8000dabe <- 0xa6300aa +mem-write: 0x8000dac2 <- 0x27832005 +mem-write: 0x8000dac6 <- 0x25830244 +mem-write: 0x8000daca <- 0x861301c4 +mem-write: 0x8000dace <- 0x85130009 +mem-write: 0x8000dad2 <- 0x12e3000a +mem-write: 0x8000dad6 <- 0xa983fc09 +mem-write: 0x8000dada <- 0xa9030004 +mem-write: 0x8000dade <- 0x84930044 +mem-write: 0x8000dae2 <- 0xf06f0084 +mem-write: 0x8000dae6 <- 0x593fa9f +mem-write: 0x8000daea <- 0x85130004 +mem-write: 0x8000daee <- 0x50ef000a +mem-write: 0x8000daf2 <- 0x1c63ff9f +mem-write: 0x8000daf6 <- 0x57833a05 +mem-write: 0x8000dafa <- 0x248300c4 +mem-write: 0x8000dafe <- 0xf713000a +mem-write: 0x8000db02 <- 0x18e30027 +mem-write: 0x8000db06 <- 0xf713f607 +mem-write: 0x8000db0a <- 0x14630017 +mem-write: 0x8000db0e <- 0x2c832407 +mem-write: 0x8000db12 <- 0x25030084 +mem-write: 0x8000db16 <- 0xb370004 +mem-write: 0x8000db1a <- 0x4b938000 +mem-write: 0x8000db1e <- 0xc13ffeb +mem-write: 0x8000db22 <- 0x9130000 +mem-write: 0x8000db26 <- 0x4b130000 +mem-write: 0x8000db2a <- 0xe63fffb +mem-write: 0x8000db2e <- 0xf7130e09 +mem-write: 0x8000db32 <- 0xc632007 +mem-write: 0x8000db36 <- 0x8d132407 +mem-write: 0x8000db3a <- 0x6263000c +mem-write: 0x8000db3e <- 0xf7132f99 +mem-write: 0x8000db42 <- 0xa634807 +mem-write: 0x8000db46 <- 0x29830807 +mem-write: 0x8000db4a <- 0x25830144 +mem-write: 0x8000db4e <- 0x7130104 +mem-write: 0x8000db52 <- 0x96930019 +mem-write: 0x8000db56 <- 0x86b30019 +mem-write: 0x8000db5a <- 0xd9930136 +mem-write: 0x8000db5e <- 0xd3301f6 +mem-write: 0x8000db62 <- 0x89b340b5 +mem-write: 0x8000db66 <- 0xd99300d9 +mem-write: 0x8000db6a <- 0x7334019 +mem-write: 0x8000db6e <- 0x861301a7 +mem-write: 0x8000db72 <- 0xf6630009 +mem-write: 0x8000db76 <- 0x99300e9 +mem-write: 0x8000db7a <- 0x6130007 +mem-write: 0x8000db7e <- 0xf7930007 +mem-write: 0x8000db82 <- 0x84634007 +mem-write: 0x8000db86 <- 0x5932e07 +mem-write: 0x8000db8a <- 0x85130006 +mem-write: 0x8000db8e <- 0x90ef000a +mem-write: 0x8000db92 <- 0xc93ba9f +mem-write: 0x8000db96 <- 0x2630005 +mem-write: 0x8000db9a <- 0x25833005 +mem-write: 0x8000db9e <- 0x6130104 +mem-write: 0x8000dba2 <- 0xef000d +mem-write: 0x8000dba6 <- 0x57834dc0 +mem-write: 0x8000dbaa <- 0xf79300c4 +mem-write: 0x8000dbae <- 0xe793b7f7 +mem-write: 0x8000dbb2 <- 0x16230807 +mem-write: 0x8000dbb6 <- 0x853300f4 +mem-write: 0x8000dbba <- 0x87b301ac +mem-write: 0x8000dbbe <- 0x282341a9 +mem-write: 0x8000dbc2 <- 0x20230194 +mem-write: 0x8000dbc6 <- 0x2a2300a4 +mem-write: 0x8000dbca <- 0xc930134 +mem-write: 0x8000dbce <- 0x24230009 +mem-write: 0x8000dbd2 <- 0xd1300f4 +mem-write: 0x8000dbd6 <- 0x6130009 +mem-write: 0x8000dbda <- 0x593000d +mem-write: 0x8000dbde <- 0xef000c +mem-write: 0x8000dbe2 <- 0x27035bc0 +mem-write: 0x8000dbe6 <- 0x27830084 +mem-write: 0x8000dbea <- 0x9930004 +mem-write: 0x8000dbee <- 0xcb30009 +mem-write: 0x8000dbf2 <- 0x87b34197 +mem-write: 0x8000dbf6 <- 0x242301a7 +VXDRV: upload 1023 bytes to 0x8000dbfa +mem-write: 0x8000dbfa <- 0x20230194 +mem-write: 0x8000dbfe <- 0x91300f4 +mem-write: 0x8000dc02 <- 0x26030000 +mem-write: 0x8000dc06 <- 0xc33008a +mem-write: 0x8000dc0a <- 0x9b3013c +mem-write: 0x8000dc0e <- 0x24234136 +mem-write: 0x8000dc12 <- 0x8063013a +mem-write: 0x8000dc16 <- 0x2c830c09 +mem-write: 0x8000dc1a <- 0x25030084 +mem-write: 0x8000dc1e <- 0x57830004 +mem-write: 0x8000dc22 <- 0x16e300c4 +mem-write: 0x8000dc26 <- 0xac03f009 +mem-write: 0x8000dc2a <- 0xa9030004 +mem-write: 0x8000dc2e <- 0x84930044 +mem-write: 0x8000dc32 <- 0xf06f0084 +mem-write: 0x8000dc36 <- 0xa983ef9f +mem-write: 0x8000dc3a <- 0xac030044 +mem-write: 0x8000dc3e <- 0x84930004 +mem-write: 0x8000dc42 <- 0x8ae30084 +mem-write: 0x8000dc46 <- 0x8613fe09 +mem-write: 0x8000dc4a <- 0x5930009 +mem-write: 0x8000dc4e <- 0x51300a0 +mem-write: 0x8000dc52 <- 0xa0ef000c +mem-write: 0x8000dc56 <- 0x463a7cf +mem-write: 0x8000dc5a <- 0x5131205 +mem-write: 0x8000dc5e <- 0xb330015 +mem-write: 0x8000dc62 <- 0x7934185 +mem-write: 0x8000dc66 <- 0x8b93000b +mem-write: 0x8000dc6a <- 0xf4630009 +mem-write: 0x8000dc6e <- 0x8b930137 +mem-write: 0x8000dc72 <- 0x25030007 +mem-write: 0x8000dc76 <- 0x27830004 +mem-write: 0x8000dc7a <- 0x26830104 +mem-write: 0x8000dc7e <- 0xf8630144 +mem-write: 0x8000dc82 <- 0x290300a7 +mem-write: 0x8000dc86 <- 0x89330084 +mem-write: 0x8000dc8a <- 0x42630126 +mem-write: 0x8000dc8e <- 0xc8630979 +mem-write: 0x8000dc92 <- 0x27831adb +mem-write: 0x8000dc96 <- 0x25830244 +mem-write: 0x8000dc9a <- 0x61301c4 +mem-write: 0x8000dc9e <- 0x8513000c +mem-write: 0x8000dca2 <- 0x80e7000a +mem-write: 0x8000dca6 <- 0x9130007 +mem-write: 0x8000dcaa <- 0x56630005 +mem-write: 0x8000dcae <- 0xb3308a0 +mem-write: 0x8000dcb2 <- 0x513412b +mem-write: 0x8000dcb6 <- 0xa630010 +mem-write: 0x8000dcba <- 0x2603160b +mem-write: 0x8000dcbe <- 0xc33008a +mem-write: 0x8000dcc2 <- 0x89b3012c +mem-write: 0x8000dcc6 <- 0x9334129 +mem-write: 0x8000dcca <- 0x24234126 +mem-write: 0x8000dcce <- 0x1a63012a +mem-write: 0x8000dcd2 <- 0x5130809 +mem-write: 0x8000dcd6 <- 0x20830000 +mem-write: 0x8000dcda <- 0x240302c1 +mem-write: 0x8000dcde <- 0x24830281 +mem-write: 0x8000dce2 <- 0x29030241 +mem-write: 0x8000dce6 <- 0x29830201 +mem-write: 0x8000dcea <- 0x2a0301c1 +mem-write: 0x8000dcee <- 0x2a830181 +mem-write: 0x8000dcf2 <- 0x2b030141 +mem-write: 0x8000dcf6 <- 0x2b830101 +mem-write: 0x8000dcfa <- 0x2c0300c1 +mem-write: 0x8000dcfe <- 0x2c830081 +mem-write: 0x8000dd02 <- 0x2d030041 +mem-write: 0x8000dd06 <- 0x1130001 +mem-write: 0x8000dd0a <- 0x80670301 +mem-write: 0x8000dd0e <- 0x5930000 +mem-write: 0x8000dd12 <- 0x613000c +mem-write: 0x8000dd16 <- 0xef0009 +mem-write: 0x8000dd1a <- 0x27834840 +mem-write: 0x8000dd1e <- 0x5930004 +mem-write: 0x8000dd22 <- 0x85130004 +mem-write: 0x8000dd26 <- 0x87b3000a +mem-write: 0x8000dd2a <- 0x20230127 +mem-write: 0x8000dd2e <- 0x60ef00f4 +mem-write: 0x8000dd32 <- 0xee3b28f +mem-write: 0x8000dd36 <- 0x1783f605 +mem-write: 0x8000dd3a <- 0xe79300c4 +mem-write: 0x8000dd3e <- 0x16230407 +mem-write: 0x8000dd42 <- 0x51300f4 +mem-write: 0x8000dd46 <- 0xf06ffff0 +mem-write: 0x8000dd4a <- 0x513f91f +mem-write: 0x8000dd4e <- 0x80670000 +mem-write: 0x8000dd52 <- 0xb130000 +mem-write: 0x8000dd56 <- 0x5130000 +mem-write: 0x8000dd5a <- 0xc130000 +mem-write: 0x8000dd5e <- 0x9930000 +mem-write: 0x8000dd62 <- 0x8ae30000 +mem-write: 0x8000dd66 <- 0x1ee3ec09 +mem-write: 0x8000dd6a <- 0x8613ee05 +mem-write: 0x8000dd6e <- 0x5930009 +mem-write: 0x8000dd72 <- 0x51300a0 +mem-write: 0x8000dd76 <- 0xa0ef000c +mem-write: 0x8000dd7a <- 0x10e3958f +mem-write: 0x8000dd7e <- 0x8793ee05 +mem-write: 0x8000dd82 <- 0x8b130019 +mem-write: 0x8000dd86 <- 0xf06f0007 +mem-write: 0x8000dd8a <- 0x2783ee1f +mem-write: 0x8000dd8e <- 0xe2630104 +mem-write: 0x8000dd92 <- 0x278304a7 +mem-write: 0x8000dd96 <- 0x6e630144 +mem-write: 0x8000dd9a <- 0x69302f9 +mem-write: 0x8000dd9e <- 0xf4630009 +mem-write: 0x8000dda2 <- 0x693012b +mem-write: 0x8000dda6 <- 0xc6b3000b +mem-write: 0x8000ddaa <- 0x270302f6 +mem-write: 0x8000ddae <- 0x25830244 +mem-write: 0x8000ddb2 <- 0x61301c4 +mem-write: 0x8000ddb6 <- 0x8513000c +mem-write: 0x8000ddba <- 0x86b3000a +mem-write: 0x8000ddbe <- 0xe702f6 +mem-write: 0x8000ddc2 <- 0x9930007 +mem-write: 0x8000ddc6 <- 0x58e30005 +mem-write: 0x8000ddca <- 0x933f6a0 +mem-write: 0x8000ddce <- 0xf06f4139 +mem-write: 0x8000ddd2 <- 0x8993e35f +mem-write: 0x8000ddd6 <- 0x7463000c +mem-write: 0x8000ddda <- 0x9930199 +mem-write: 0x8000ddde <- 0x86130009 +mem-write: 0x8000dde2 <- 0x5930009 +mem-write: 0x8000dde6 <- 0xef000c +mem-write: 0x8000ddea <- 0x27833b40 +mem-write: 0x8000ddee <- 0x27030084 +mem-write: 0x8000ddf2 <- 0x87b30004 +mem-write: 0x8000ddf6 <- 0x7334137 +mem-write: 0x8000ddfa <- 0x24230137 +mem-write: 0x8000ddfe <- 0x202300f4 +mem-write: 0x8000de02 <- 0x94e300e4 +mem-write: 0x8000de06 <- 0x593fc07 +mem-write: 0x8000de0a <- 0x85130004 +mem-write: 0x8000de0e <- 0x60ef000a +mem-write: 0x8000de12 <- 0x12e3a48f +mem-write: 0x8000de16 <- 0x933f205 +mem-write: 0x8000de1a <- 0xf06f4139 +mem-write: 0x8000de1e <- 0xc93de9f +mem-write: 0x8000de22 <- 0xd130009 +mem-write: 0x8000de26 <- 0xf06f0009 +mem-write: 0x8000de2a <- 0x593db1f +mem-write: 0x8000de2e <- 0x85130004 +mem-write: 0x8000de32 <- 0x60ef000a +mem-write: 0x8000de36 <- 0x2e3a24f +mem-write: 0x8000de3a <- 0xf06fe805 +mem-write: 0x8000de3e <- 0x8613efdf +mem-write: 0x8000de42 <- 0x593000b +mem-write: 0x8000de46 <- 0xef000c +mem-write: 0x8000de4a <- 0x27833540 +mem-write: 0x8000de4e <- 0x26030084 +mem-write: 0x8000de52 <- 0x89130004 +mem-write: 0x8000de56 <- 0x87b3000b +mem-write: 0x8000de5a <- 0x6334177 +mem-write: 0x8000de5e <- 0x24230176 +mem-write: 0x8000de62 <- 0x202300f4 +mem-write: 0x8000de66 <- 0xf06f00c4 +mem-write: 0x8000de6a <- 0x8513e49f +mem-write: 0x8000de6e <- 0xef000a +mem-write: 0x8000de72 <- 0xc934b40 +mem-write: 0x8000de76 <- 0x10e30005 +mem-write: 0x8000de7a <- 0x2583d405 +mem-write: 0x8000de7e <- 0x85130104 +mem-write: 0x8000de82 <- 0x60ef000a +mem-write: 0x8000de86 <- 0x1783ee0f +mem-write: 0x8000de8a <- 0x71300c4 +mem-write: 0x8000de8e <- 0xa02300c0 +mem-write: 0x8000de92 <- 0xf79300ea +mem-write: 0x8000de96 <- 0xf06ff7f7 +mem-write: 0x8000de9a <- 0x713ea5f +mem-write: 0x8000de9e <- 0x178300c0 +mem-write: 0x8000dea2 <- 0xa02300c4 +mem-write: 0x8000dea6 <- 0xf06f00ea +mem-write: 0x8000deaa <- 0x513e95f +mem-write: 0x8000deae <- 0xf06ffff0 +mem-write: 0x8000deb2 <- 0x113e29f +mem-write: 0x8000deb6 <- 0x2423ff01 +mem-write: 0x8000deba <- 0x22230081 +mem-write: 0x8000debe <- 0x4130091 +mem-write: 0x8000dec2 <- 0x85130005 +mem-write: 0x8000dec6 <- 0x26230005 +mem-write: 0x8000deca <- 0xa4230011 +mem-write: 0x8000dece <- 0x20ef2401 +mem-write: 0x8000ded2 <- 0x793c68f +mem-write: 0x8000ded6 <- 0xc63fff0 +mem-write: 0x8000deda <- 0x208300f5 +mem-write: 0x8000dede <- 0x240300c1 +mem-write: 0x8000dee2 <- 0x24830081 +mem-write: 0x8000dee6 <- 0x1130041 +mem-write: 0x8000deea <- 0x80670101 +mem-write: 0x8000deee <- 0xa7830000 +mem-write: 0x8000def2 <- 0x84e32481 +mem-write: 0x8000def6 <- 0x2083fe07 +mem-write: 0x8000defa <- 0x202300c1 +mem-write: 0x8000defe <- 0x240300f4 +mem-write: 0x8000df02 <- 0x24830081 +mem-write: 0x8000df06 <- 0x1130041 +mem-write: 0x8000df0a <- 0x80670101 +mem-write: 0x8000df0e <- 0x1130000 +mem-write: 0x8000df12 <- 0x2623ff01 +mem-write: 0x8000df16 <- 0x24230011 +mem-write: 0x8000df1a <- 0x22230081 +mem-write: 0x8000df1e <- 0xc630091 +mem-write: 0x8000df22 <- 0x55b70206 +mem-write: 0x8000df26 <- 0x85938001 +mem-write: 0x8000df2a <- 0x5133645 +mem-write: 0x8000df2e <- 0x4130006 +mem-write: 0x8000df32 <- 0xef0006 +mem-write: 0x8000df36 <- 0x54b72ad0 +mem-write: 0x8000df3a <- 0x12638001 +mem-write: 0x8000df3e <- 0x85130205 +mem-write: 0x8000df42 <- 0x20833604 +mem-write: 0x8000df46 <- 0x240300c1 +mem-write: 0x8000df4a <- 0x24830081 +mem-write: 0x8000df4e <- 0x1130041 +mem-write: 0x8000df52 <- 0x80670101 +mem-write: 0x8000df56 <- 0x54b70000 +mem-write: 0x8000df5a <- 0xf06f8001 +mem-write: 0x8000df5e <- 0x8593fe5f +mem-write: 0x8000df62 <- 0x5133604 +mem-write: 0x8000df66 <- 0xef0004 +mem-write: 0x8000df6a <- 0xae32790 +mem-write: 0x8000df6e <- 0x55b7fc05 +mem-write: 0x8000df72 <- 0x85938001 +mem-write: 0x8000df76 <- 0x513a185 +mem-write: 0x8000df7a <- 0xef0004 +mem-write: 0x8000df7e <- 0xe32650 +mem-write: 0x8000df82 <- 0x513fc05 +mem-write: 0x8000df86 <- 0xf06f0000 +mem-write: 0x8000df8a <- 0xc503fbdf +mem-write: 0x8000df8e <- 0x80671601 +mem-write: 0x8000df92 <- 0x7930000 +mem-write: 0x8000df96 <- 0xa5030005 +mem-write: 0x8000df9a <- 0x86131d81 +mem-write: 0x8000df9e <- 0x85930005 +mem-write: 0x8000dfa2 <- 0xf06f0007 +mem-write: 0x8000dfa6 <- 0x113f6df +mem-write: 0x8000dfaa <- 0x8713ff01 +mem-write: 0x8000dfae <- 0x24230005 +mem-write: 0x8000dfb2 <- 0x22230081 +mem-write: 0x8000dfb6 <- 0x5930091 +mem-write: 0x8000dfba <- 0x4130006 +mem-write: 0x8000dfbe <- 0x86130005 +mem-write: 0x8000dfc2 <- 0x5130006 +mem-write: 0x8000dfc6 <- 0x26230007 +mem-write: 0x8000dfca <- 0xa4230011 +mem-write: 0x8000dfce <- 0x20ef2401 +mem-write: 0x8000dfd2 <- 0x793b70f +mem-write: 0x8000dfd6 <- 0xc63fff0 +mem-write: 0x8000dfda <- 0x208300f5 +mem-write: 0x8000dfde <- 0x240300c1 +mem-write: 0x8000dfe2 <- 0x24830081 +mem-write: 0x8000dfe6 <- 0x1130041 +mem-write: 0x8000dfea <- 0x80670101 +mem-write: 0x8000dfee <- 0xa7830000 +mem-write: 0x8000dff2 <- 0x84e32481 +mem-write: 0x8000dff6 <- 0x2483fe07 +VXDRV: upload 1024 bytes to 0x8000dff9 +mem-write: 0x8000dff9 <- 0x2300c120 +mem-write: 0x8000dffd <- 0x300f420 +mem-write: 0x8000e001 <- 0x83008124 +mem-write: 0x8000e005 <- 0x13004124 +mem-write: 0x8000e009 <- 0x67010101 +mem-write: 0x8000e00d <- 0x3000080 +mem-write: 0x8000e011 <- 0x6711c1a3 +mem-write: 0x8000e015 <- 0x63000300 +mem-write: 0x8000e019 <- 0x63020580 +mem-write: 0x8000e01d <- 0x63040602 +mem-write: 0x8000e021 <- 0x83040688 +mem-write: 0x8000e025 <- 0x23000647 +mem-write: 0x8000e029 <- 0x300f5a0 +mem-write: 0x8000e02d <- 0x33000645 +mem-write: 0x8000e031 <- 0x6700a035 +mem-write: 0x8000e035 <- 0x13000080 +mem-write: 0x8000e039 <- 0x93ff0101 +mem-write: 0x8000e03d <- 0x6300c105 +mem-write: 0x8000e041 <- 0x63020604 +mem-write: 0x8000e045 <- 0x8302068a +mem-write: 0x8000e049 <- 0x23000647 +mem-write: 0x8000e04d <- 0x300f5a0 +mem-write: 0x8000e051 <- 0x33000645 +mem-write: 0x8000e055 <- 0x1300a035 +mem-write: 0x8000e059 <- 0x67010101 +mem-write: 0x8000e05d <- 0x13000080 +mem-write: 0x8000e061 <- 0x67000005 +mem-write: 0x8000e065 <- 0x13000080 +mem-write: 0x8000e069 <- 0x6f000005 +mem-write: 0x8000e06d <- 0x13fedff0 +mem-write: 0x8000e071 <- 0x67ffe005 +mem-write: 0x8000e075 <- 0x13000080 +mem-write: 0x8000e079 <- 0x6fffe005 +mem-write: 0x8000e07d <- 0xb3fddff0 +mem-write: 0x8000e081 <- 0x9300a5c7 +mem-write: 0x8000e085 <- 0xb30037f7 +mem-write: 0x8000e089 <- 0x6300c508 +mem-write: 0x8000e08d <- 0x93060792 +mem-write: 0x8000e091 <- 0x63003007 +mem-write: 0x8000e095 <- 0x9304c7fe +mem-write: 0x8000e099 <- 0x13003577 +mem-write: 0x8000e09d <- 0x63000507 +mem-write: 0x8000e0a1 <- 0x13060798 +mem-write: 0x8000e0a5 <- 0x93ffc8f6 +mem-write: 0x8000e0a9 <- 0x63fe0607 +mem-write: 0x8000e0ad <- 0x6308f76c +mem-write: 0x8000e0b1 <- 0x9302c77c +mem-write: 0x8000e0b5 <- 0x93000586 +mem-write: 0x8000e0b9 <- 0x3000707 +mem-write: 0x8000e0bd <- 0x930006a8 +mem-write: 0x8000e0c1 <- 0x93004787 +mem-write: 0x8000e0c5 <- 0x23004686 +mem-write: 0x8000e0c9 <- 0xe3ff07ae +mem-write: 0x8000e0cd <- 0x93fec7e8 +mem-write: 0x8000e0d1 <- 0xb3fff607 +mem-write: 0x8000e0d5 <- 0x9340e787 +mem-write: 0x8000e0d9 <- 0x93ffc7f7 +mem-write: 0x8000e0dd <- 0x33004787 +mem-write: 0x8000e0e1 <- 0xb300f707 +mem-write: 0x8000e0e5 <- 0x6300f585 +mem-write: 0x8000e0e9 <- 0x67011768 +mem-write: 0x8000e0ed <- 0x13000080 +mem-write: 0x8000e0f1 <- 0xe3000507 +mem-write: 0x8000e0f5 <- 0x83ff157c +mem-write: 0x8000e0f9 <- 0x130005c7 +mem-write: 0x8000e0fd <- 0x93001707 +mem-write: 0x8000e101 <- 0xa3001585 +mem-write: 0x8000e105 <- 0xe3fef70f +mem-write: 0x8000e109 <- 0x67ff1768 +mem-write: 0x8000e10d <- 0x83000080 +mem-write: 0x8000e111 <- 0x130005c6 +mem-write: 0x8000e115 <- 0x93001707 +mem-write: 0x8000e119 <- 0xa3003777 +mem-write: 0x8000e11d <- 0x93fed70f +mem-write: 0x8000e121 <- 0xe3001585 +mem-write: 0x8000e125 <- 0x83f80780 +mem-write: 0x8000e129 <- 0x130005c6 +mem-write: 0x8000e12d <- 0x93001707 +mem-write: 0x8000e131 <- 0xa3003777 +mem-write: 0x8000e135 <- 0x93fed70f +mem-write: 0x8000e139 <- 0xe3001585 +mem-write: 0x8000e13d <- 0x6ffc079a +mem-write: 0x8000e141 <- 0x83f65ff0 +mem-write: 0x8000e145 <- 0x830045a6 +mem-write: 0x8000e149 <- 0x830005a2 +mem-write: 0x8000e14d <- 0x30085af +mem-write: 0x8000e151 <- 0x8300c5af +mem-write: 0x8000e155 <- 0x30105ae +mem-write: 0x8000e159 <- 0x30145ae +mem-write: 0x8000e15d <- 0x30185a3 +mem-write: 0x8000e161 <- 0x2301c5a8 +mem-write: 0x8000e165 <- 0x8300d722 +mem-write: 0x8000e169 <- 0x230205a6 +mem-write: 0x8000e16d <- 0x23005720 +mem-write: 0x8000e171 <- 0x2301f724 +mem-write: 0x8000e175 <- 0x2301e726 +mem-write: 0x8000e179 <- 0x2301d728 +mem-write: 0x8000e17d <- 0x2301c72a +mem-write: 0x8000e181 <- 0x2300672c +mem-write: 0x8000e185 <- 0x2301072e +mem-write: 0x8000e189 <- 0x1302d720 +mem-write: 0x8000e18d <- 0x93024707 +mem-write: 0x8000e191 <- 0xe3024585 +mem-write: 0x8000e195 <- 0x6ffaf768 +mem-write: 0x8000e199 <- 0x63f19ff0 +mem-write: 0x8000e19d <- 0xb302a5f6 +mem-write: 0x8000e1a1 <- 0x6300c587 +mem-write: 0x8000e1a5 <- 0x3302f572 +mem-write: 0x8000e1a9 <- 0x6300c507 +mem-write: 0x8000e1ad <- 0x830e060a +mem-write: 0x8000e1b1 <- 0x93fff7c6 +mem-write: 0x8000e1b5 <- 0x13fff787 +mem-write: 0x8000e1b9 <- 0x23fff707 +mem-write: 0x8000e1bd <- 0xe300d700 +mem-write: 0x8000e1c1 <- 0x67fef598 +mem-write: 0x8000e1c5 <- 0x93000080 +mem-write: 0x8000e1c9 <- 0x6300f007 +mem-write: 0x8000e1cd <- 0x9302c7e8 +mem-write: 0x8000e1d1 <- 0x93000507 +mem-write: 0x8000e1d5 <- 0x63fff606 +mem-write: 0x8000e1d9 <- 0x930c060c +mem-write: 0x8000e1dd <- 0xb3001686 +mem-write: 0x8000e1e1 <- 0x300d786 +mem-write: 0x8000e1e5 <- 0x930005c7 +mem-write: 0x8000e1e9 <- 0x93001787 +mem-write: 0x8000e1ed <- 0xa3001585 +mem-write: 0x8000e1f1 <- 0xe3fee78f +mem-write: 0x8000e1f5 <- 0x67fed798 +mem-write: 0x8000e1f9 <- 0xb3000080 +mem-write: 0x8000e1fd <- 0x9300a5e7 +mem-write: 0x8000e201 <- 0x630037f7 +mem-write: 0x8000e205 <- 0x930a0790 +mem-write: 0x8000e209 <- 0x93ff0608 +mem-write: 0x8000e20d <- 0x93ff08f8 +mem-write: 0x8000e211 <- 0x33010888 +mem-write: 0x8000e215 <- 0x13011508 +mem-write: 0x8000e219 <- 0x93000587 +mem-write: 0x8000e21d <- 0x83000507 +mem-write: 0x8000e221 <- 0x13000726 +mem-write: 0x8000e225 <- 0x93010707 +mem-write: 0x8000e229 <- 0x23010787 +mem-write: 0x8000e22d <- 0x83fed7a8 +mem-write: 0x8000e231 <- 0x23ff4726 +mem-write: 0x8000e235 <- 0x83fed7aa +mem-write: 0x8000e239 <- 0x23ff8726 +mem-write: 0x8000e23d <- 0x83fed7ac +mem-write: 0x8000e241 <- 0x23ffc726 +mem-write: 0x8000e245 <- 0xe3fed7ae +mem-write: 0x8000e249 <- 0x13fcf81c +mem-write: 0x8000e24d <- 0xb300c677 +mem-write: 0x8000e251 <- 0x13011585 +mem-write: 0x8000e255 <- 0x6300f678 +mem-write: 0x8000e259 <- 0x1304070e +mem-write: 0x8000e25d <- 0x93000587 +mem-write: 0x8000e261 <- 0x13000788 +mem-write: 0x8000e265 <- 0x300300e +mem-write: 0x8000e269 <- 0x13000723 +mem-write: 0x8000e26d <- 0xb3004707 +mem-write: 0x8000e271 <- 0x2340e806 +mem-write: 0x8000e275 <- 0xb30068a0 +mem-write: 0x8000e279 <- 0x9300d586 +mem-write: 0x8000e27d <- 0xe3004888 +mem-write: 0x8000e281 <- 0x13fede64 +mem-write: 0x8000e285 <- 0x13ffc807 +mem-write: 0x8000e289 <- 0x13ffc777 +mem-write: 0x8000e28d <- 0x13004707 +mem-write: 0x8000e291 <- 0xb3003676 +mem-write: 0x8000e295 <- 0xb300e787 +mem-write: 0x8000e299 <- 0x6f00e585 +mem-write: 0x8000e29d <- 0x67f39ff0 +mem-write: 0x8000e2a1 <- 0x93000080 +mem-write: 0x8000e2a5 <- 0x93fff606 +mem-write: 0x8000e2a9 <- 0x6f000507 +mem-write: 0x8000e2ad <- 0x67f31ff0 +mem-write: 0x8000e2b1 <- 0x13000080 +mem-write: 0x8000e2b5 <- 0x6f000806 +mem-write: 0x8000e2b9 <- 0x13f1dff0 +mem-write: 0x8000e2bd <- 0x13ff0101 +mem-write: 0x8000e2c1 <- 0x23000587 +mem-write: 0x8000e2c5 <- 0x23008124 +mem-write: 0x8000e2c9 <- 0x93009122 +mem-write: 0x8000e2cd <- 0x13000605 +mem-write: 0x8000e2d1 <- 0x13000504 +mem-write: 0x8000e2d5 <- 0x13000686 +mem-write: 0x8000e2d9 <- 0x23000705 +mem-write: 0x8000e2dd <- 0x23001126 +mem-write: 0x8000e2e1 <- 0xef2401a4 +mem-write: 0x8000e2e5 <- 0x93950f20 +mem-write: 0x8000e2e9 <- 0x63fff007 +mem-write: 0x8000e2ed <- 0x8300f50c +mem-write: 0x8000e2f1 <- 0x300c120 +mem-write: 0x8000e2f5 <- 0x83008124 +mem-write: 0x8000e2f9 <- 0x13004124 +mem-write: 0x8000e2fd <- 0x67010101 +mem-write: 0x8000e301 <- 0x83000080 +mem-write: 0x8000e305 <- 0xe32481a7 +mem-write: 0x8000e309 <- 0x83fe0784 +mem-write: 0x8000e30d <- 0x2300c120 +mem-write: 0x8000e311 <- 0x300f420 +mem-write: 0x8000e315 <- 0x83008124 +mem-write: 0x8000e319 <- 0x13004124 +mem-write: 0x8000e31d <- 0x67010101 +mem-write: 0x8000e321 <- 0x13000080 +mem-write: 0x8000e325 <- 0x23fd0101 +mem-write: 0x8000e329 <- 0x23032120 +mem-write: 0x8000e32d <- 0x23021126 +mem-write: 0x8000e331 <- 0x23028124 +mem-write: 0x8000e335 <- 0x23029122 +mem-write: 0x8000e339 <- 0x2301312e +mem-write: 0x8000e33d <- 0x2301412c +mem-write: 0x8000e341 <- 0x2301512a +mem-write: 0x8000e345 <- 0x23016128 +mem-write: 0x8000e349 <- 0x23017126 +mem-write: 0x8000e34d <- 0x13018124 +mem-write: 0x8000e351 <- 0x63000609 +mem-write: 0x8000e355 <- 0x13220582 +mem-write: 0x8000e359 <- 0x93000584 +mem-write: 0x8000e35d <- 0xef000509 +mem-write: 0x8000e361 <- 0x93c45f90 +mem-write: 0x8000e365 <- 0x9300b904 +mem-write: 0x8000e369 <- 0x63016007 +mem-write: 0x8000e36d <- 0x930e97fc +mem-write: 0x8000e371 <- 0x13ff84f4 +mem-write: 0x8000e375 <- 0x63000487 +mem-write: 0x8000e379 <- 0x630e04cc +mem-write: 0x8000e37d <- 0x830f24ea +mem-write: 0x8000e381 <- 0x93ffc427 +mem-write: 0x8000e385 <- 0x13ff840a +mem-write: 0x8000e389 <- 0x33ffc7fa +mem-write: 0x8000e38d <- 0x63014a8b +mem-write: 0x8000e391 <- 0x9318ea5a +mem-write: 0x8000e395 <- 0x3c3018b +mem-write: 0x8000e399 <- 0x83008ba6 +mem-write: 0x8000e39d <- 0x63004b26 +mem-write: 0x8000e3a1 <- 0x1323660e +mem-write: 0x8000e3a5 <- 0x33ffe6f6 +mem-write: 0x8000e3a9 <- 0x300cb06 +mem-write: 0x8000e3ad <- 0x13004626 +mem-write: 0x8000e3b1 <- 0x63001676 +mem-write: 0x8000e3b5 <- 0x931a0614 +mem-write: 0x8000e3b9 <- 0x33ffc6f6 +mem-write: 0x8000e3bd <- 0x6300da06 +mem-write: 0x8000e3c1 <- 0x9332e65e +mem-write: 0x8000e3c5 <- 0x630017f7 +mem-write: 0x8000e3c9 <- 0x3020794 +mem-write: 0x8000e3cd <- 0x33ff842c +mem-write: 0x8000e3d1 <- 0x83418a8c +mem-write: 0x8000e3d5 <- 0x93004c27 +mem-write: 0x8000e3d9 <- 0xb3ffc7f7 +mem-write: 0x8000e3dd <- 0xb300d786 +mem-write: 0x8000e3e1 <- 0x6301468b +mem-write: 0x8000e3e5 <- 0xb334ebda +mem-write: 0x8000e3e9 <- 0x6300fa0b +mem-write: 0x8000e3ed <- 0x930cebd2 +mem-write: 0x8000e3f1 <- 0x13000905 +mem-write: 0x8000e3f5 <- 0xef000985 +VXDRV: upload 1024 bytes to 0x8000e3f9 +mem-write: 0x8000e3f9 <- 0x13b40f90 +mem-write: 0x8000e3fd <- 0x63000509 +mem-write: 0x8000e401 <- 0x8304050c +mem-write: 0x8000e405 <- 0x13ffc427 +mem-write: 0x8000e409 <- 0x93ff8507 +mem-write: 0x8000e40d <- 0xb3ffe7f7 +mem-write: 0x8000e411 <- 0x6300fa87 +mem-write: 0x8000e415 <- 0x1330e782 +mem-write: 0x8000e419 <- 0x93ffca06 +mem-write: 0x8000e41d <- 0x63024007 +mem-write: 0x8000e421 <- 0x1330c7e6 +mem-write: 0x8000e425 <- 0x83013007 +mem-write: 0x8000e429 <- 0x63000426 +mem-write: 0x8000e42d <- 0x9326c76c +mem-write: 0x8000e431 <- 0x13000507 +mem-write: 0x8000e435 <- 0x23000407 +mem-write: 0x8000e439 <- 0x8300d7a0 +mem-write: 0x8000e43d <- 0x23004726 +mem-write: 0x8000e441 <- 0x300d7a2 +mem-write: 0x8000e445 <- 0x23008727 +mem-write: 0x8000e449 <- 0x9300e7a4 +mem-write: 0x8000e44d <- 0x13000405 +mem-write: 0x8000e451 <- 0xef000985 +mem-write: 0x8000e455 <- 0x13910f60 +mem-write: 0x8000e459 <- 0xef000985 +mem-write: 0x8000e45d <- 0x6fb4df90 +mem-write: 0x8000e461 <- 0x9301c000 +mem-write: 0x8000e465 <- 0x13010004 +mem-write: 0x8000e469 <- 0xe3010007 +mem-write: 0x8000e46d <- 0x93f124fa +mem-write: 0x8000e471 <- 0x2300c007 +mem-write: 0x8000e475 <- 0x1300f9a0 +mem-write: 0x8000e479 <- 0x83000009 +mem-write: 0x8000e47d <- 0x302c120 +mem-write: 0x8000e481 <- 0x83028124 +mem-write: 0x8000e485 <- 0x83024124 +mem-write: 0x8000e489 <- 0x301c129 +mem-write: 0x8000e48d <- 0x8301812a +mem-write: 0x8000e491 <- 0x301412a +mem-write: 0x8000e495 <- 0x8301012b +mem-write: 0x8000e499 <- 0x300c12b +mem-write: 0x8000e49d <- 0x1300812c +mem-write: 0x8000e4a1 <- 0x3000905 +mem-write: 0x8000e4a5 <- 0x13020129 +mem-write: 0x8000e4a9 <- 0x67030101 +mem-write: 0x8000e4ad <- 0x83000080 +mem-write: 0x8000e4b1 <- 0x300cc27 +mem-write: 0x8000e4b5 <- 0x13008c27 +mem-write: 0x8000e4b9 <- 0x93ffca06 +mem-write: 0x8000e4bd <- 0x23024006 +mem-write: 0x8000e4c1 <- 0x2300f726 +mem-write: 0x8000e4c5 <- 0x1300e7a4 +mem-write: 0x8000e4c9 <- 0x33008c09 +mem-write: 0x8000e4cd <- 0x63017c0b +mem-write: 0x8000e4d1 <- 0x932ec6e4 +mem-write: 0x8000e4d5 <- 0x3013005 +mem-write: 0x8000e4d9 <- 0x93000427 +mem-write: 0x8000e4dd <- 0x63000907 +mem-write: 0x8000e4e1 <- 0x2302c5f2 +mem-write: 0x8000e4e5 <- 0x300ec24 +mem-write: 0x8000e4e9 <- 0x93004427 +mem-write: 0x8000e4ed <- 0x2301b007 +mem-write: 0x8000e4f1 <- 0x6300ec26 +mem-write: 0x8000e4f5 <- 0x330c7e2 +mem-write: 0x8000e4f9 <- 0x93008427 +mem-write: 0x8000e4fd <- 0x13010c07 +mem-write: 0x8000e501 <- 0x23008404 +mem-write: 0x8000e505 <- 0x300e7a0 +mem-write: 0x8000e509 <- 0x13004427 +mem-write: 0x8000e50d <- 0x93000b8a +mem-write: 0x8000e511 <- 0x23000c0a +mem-write: 0x8000e515 <- 0x300e7a2 +mem-write: 0x8000e519 <- 0x13008427 +mem-write: 0x8000e51d <- 0x23000904 +mem-write: 0x8000e521 <- 0x8300e7a4 +mem-write: 0x8000e525 <- 0x33004aa7 +mem-write: 0x8000e529 <- 0x93409a07 +mem-write: 0x8000e52d <- 0x9300f006 +mem-write: 0x8000e531 <- 0x630017f7 +mem-write: 0x8000e535 <- 0xb306e6ec +mem-write: 0x8000e539 <- 0x2300fa67 +mem-write: 0x8000e53d <- 0x8300faa2 +mem-write: 0x8000e541 <- 0x93004b27 +mem-write: 0x8000e545 <- 0x230017e7 +mem-write: 0x8000e549 <- 0x1300fb22 +mem-write: 0x8000e54d <- 0xef000985 +mem-write: 0x8000e551 <- 0x13a59f90 +mem-write: 0x8000e555 <- 0x6f000409 +mem-write: 0x8000e559 <- 0x93f25ff0 +mem-write: 0x8000e55d <- 0xe30017f7 +mem-write: 0x8000e561 <- 0x3e80798 +mem-write: 0x8000e565 <- 0x33ff842c +mem-write: 0x8000e569 <- 0x83418a8c +mem-write: 0x8000e56d <- 0x93004c27 +mem-write: 0x8000e571 <- 0x6fffc7f7 +mem-write: 0x8000e575 <- 0x3e75ff0 +mem-write: 0x8000e579 <- 0x83028124 +mem-write: 0x8000e57d <- 0x8302c120 +mem-write: 0x8000e581 <- 0x3024124 +mem-write: 0x8000e585 <- 0x83020129 +mem-write: 0x8000e589 <- 0x301c129 +mem-write: 0x8000e58d <- 0x8301812a +mem-write: 0x8000e591 <- 0x301412a +mem-write: 0x8000e595 <- 0x8301012b +mem-write: 0x8000e599 <- 0x300c12b +mem-write: 0x8000e59d <- 0x9300812c +mem-write: 0x8000e5a1 <- 0x13000605 +mem-write: 0x8000e5a5 <- 0x6f030101 +mem-write: 0x8000e5a9 <- 0xb3990f90 +mem-write: 0x8000e5ad <- 0x230097e7 +mem-write: 0x8000e5b1 <- 0xb300faa2 +mem-write: 0x8000e5b5 <- 0x13009a85 +mem-write: 0x8000e5b9 <- 0x23001767 +mem-write: 0x8000e5bd <- 0x8300e5a2 +mem-write: 0x8000e5c1 <- 0x93004b27 +mem-write: 0x8000e5c5 <- 0x13008585 +mem-write: 0x8000e5c9 <- 0x93000985 +mem-write: 0x8000e5cd <- 0x230017e7 +mem-write: 0x8000e5d1 <- 0xef00fb22 +mem-write: 0x8000e5d5 <- 0x6ff91f50 +mem-write: 0x8000e5d9 <- 0x93f75ff0 +mem-write: 0x8000e5dd <- 0x33ffc6f6 +mem-write: 0x8000e5e1 <- 0x9300da06 +mem-write: 0x8000e5e5 <- 0x63010485 +mem-write: 0x8000e5e9 <- 0x930eb650 +mem-write: 0x8000e5ed <- 0xe30017f7 +mem-write: 0x8000e5f1 <- 0x3e00790 +mem-write: 0x8000e5f5 <- 0x33ff842c +mem-write: 0x8000e5f9 <- 0x83418a8c +mem-write: 0x8000e5fd <- 0x93004c27 +mem-write: 0x8000e601 <- 0xb3ffc7f7 +mem-write: 0x8000e605 <- 0x3300d786 +mem-write: 0x8000e609 <- 0xe301468b +mem-write: 0x8000e60d <- 0x83dcbb4e +mem-write: 0x8000e611 <- 0x300cc27 +mem-write: 0x8000e615 <- 0x13008c27 +mem-write: 0x8000e619 <- 0x93ffca06 +mem-write: 0x8000e61d <- 0x23024006 +mem-write: 0x8000e621 <- 0x2300f726 +mem-write: 0x8000e625 <- 0x1300e7a4 +mem-write: 0x8000e629 <- 0x63008c09 +mem-write: 0x8000e62d <- 0x9320c6ee +mem-write: 0x8000e631 <- 0x3013005 +mem-write: 0x8000e635 <- 0x93000427 +mem-write: 0x8000e639 <- 0x63000907 +mem-write: 0x8000e63d <- 0x2302c5f2 +mem-write: 0x8000e641 <- 0x300ec24 +mem-write: 0x8000e645 <- 0x93004427 +mem-write: 0x8000e649 <- 0x2301b007 +mem-write: 0x8000e64d <- 0x6300ec26 +mem-write: 0x8000e651 <- 0x320c7e4 +mem-write: 0x8000e655 <- 0x93008427 +mem-write: 0x8000e659 <- 0x13010c07 +mem-write: 0x8000e65d <- 0x23008404 +mem-write: 0x8000e661 <- 0x300e7a0 +mem-write: 0x8000e665 <- 0x23004427 +mem-write: 0x8000e669 <- 0x300e7a2 +mem-write: 0x8000e66d <- 0x23008427 +mem-write: 0x8000e671 <- 0x3300e7a4 +mem-write: 0x8000e675 <- 0xb3009c07 +mem-write: 0x8000e679 <- 0x23409b07 +mem-write: 0x8000e67d <- 0x9300eba4 +mem-write: 0x8000e681 <- 0x230017e7 +mem-write: 0x8000e685 <- 0x8300f722 +mem-write: 0x8000e689 <- 0x13004c27 +mem-write: 0x8000e68d <- 0x93000985 +mem-write: 0x8000e691 <- 0xb30017f7 +mem-write: 0x8000e695 <- 0x230097e4 +mem-write: 0x8000e699 <- 0xef009c22 +mem-write: 0x8000e69d <- 0x6f90df90 +mem-write: 0x8000e6a1 <- 0x23dddff0 +mem-write: 0x8000e6a5 <- 0x8300d520 +mem-write: 0x8000e6a9 <- 0x13004426 +mem-write: 0x8000e6ad <- 0x2301b007 +mem-write: 0x8000e6b1 <- 0x6300d522 +mem-write: 0x8000e6b5 <- 0x8312c760 +mem-write: 0x8000e6b9 <- 0x13008426 +mem-write: 0x8000e6bd <- 0x93008407 +mem-write: 0x8000e6c1 <- 0x6f008507 +mem-write: 0x8000e6c5 <- 0xb3d75ff0 +mem-write: 0x8000e6c9 <- 0xb3009a8a +mem-write: 0x8000e6cd <- 0x23409607 +mem-write: 0x8000e6d1 <- 0x93015ba4 +mem-write: 0x8000e6d5 <- 0x230017e7 +mem-write: 0x8000e6d9 <- 0x8300faa2 +mem-write: 0x8000e6dd <- 0x13ffc427 +mem-write: 0x8000e6e1 <- 0x13000985 +mem-write: 0x8000e6e5 <- 0x93000409 +mem-write: 0x8000e6e9 <- 0xb30017f7 +mem-write: 0x8000e6ed <- 0x230097e4 +mem-write: 0x8000e6f1 <- 0xeffe942e +mem-write: 0x8000e6f5 <- 0x6f8b5f90 +mem-write: 0x8000e6f9 <- 0x83d85ff0 +mem-write: 0x8000e6fd <- 0x300cb27 +mem-write: 0x8000e701 <- 0x13008b27 +mem-write: 0x8000e705 <- 0x3300060a +mem-write: 0x8000e709 <- 0x2300ca8b +mem-write: 0x8000e70d <- 0x2300f726 +mem-write: 0x8000e711 <- 0x6f00e7a4 +mem-write: 0x8000e715 <- 0x83e11ff0 +mem-write: 0x8000e719 <- 0x93ffc527 +mem-write: 0x8000e71d <- 0x33ffc7f7 +mem-write: 0x8000e721 <- 0x3300fa0a +mem-write: 0x8000e725 <- 0x6f014a8b +mem-write: 0x8000e729 <- 0x93dfdff0 +mem-write: 0x8000e72d <- 0xef000405 +mem-write: 0x8000e731 <- 0x6fa6dff0 +mem-write: 0x8000e735 <- 0x83d19ff0 +mem-write: 0x8000e739 <- 0x300cb27 +mem-write: 0x8000e73d <- 0x13008b27 +mem-write: 0x8000e741 <- 0x93ffca06 +mem-write: 0x8000e745 <- 0x23024006 +mem-write: 0x8000e749 <- 0x2300f726 +mem-write: 0x8000e74d <- 0x300e7a4 +mem-write: 0x8000e751 <- 0x83008c27 +mem-write: 0x8000e755 <- 0x1300cc27 +mem-write: 0x8000e759 <- 0x33008c09 +mem-write: 0x8000e75d <- 0x23017c0b +mem-write: 0x8000e761 <- 0x2300f726 +mem-write: 0x8000e765 <- 0x6300e7a4 +mem-write: 0x8000e769 <- 0x9304c6e8 +mem-write: 0x8000e76d <- 0x3013006 +mem-write: 0x8000e771 <- 0x93000427 +mem-write: 0x8000e775 <- 0xe3000907 +mem-write: 0x8000e779 <- 0x23d8c6f6 +mem-write: 0x8000e77d <- 0x300ec24 +mem-write: 0x8000e781 <- 0x93004427 +mem-write: 0x8000e785 <- 0x2301b007 +mem-write: 0x8000e789 <- 0x300ec26 +mem-write: 0x8000e78d <- 0xe3008427 +mem-write: 0x8000e791 <- 0x23d6c7f6 +mem-write: 0x8000e795 <- 0x300ec28 +mem-write: 0x8000e799 <- 0x9300c427 +mem-write: 0x8000e79d <- 0x23024007 +mem-write: 0x8000e7a1 <- 0x300ec2a +mem-write: 0x8000e7a5 <- 0x63010427 +mem-write: 0x8000e7a9 <- 0x9306f604 +mem-write: 0x8000e7ad <- 0x13018c07 +mem-write: 0x8000e7b1 <- 0x6f010404 +mem-write: 0x8000e7b5 <- 0x93d51ff0 +mem-write: 0x8000e7b9 <- 0x13000405 +mem-write: 0x8000e7bd <- 0xef000905 +mem-write: 0x8000e7c1 <- 0x139ddff0 +mem-write: 0x8000e7c5 <- 0x13000904 +mem-write: 0x8000e7c9 <- 0x93000b8a +mem-write: 0x8000e7cd <- 0x6f000c0a +mem-write: 0x8000e7d1 <- 0x3d55ff0 +mem-write: 0x8000e7d5 <- 0x23008427 +mem-write: 0x8000e7d9 <- 0x300e524 +mem-write: 0x8000e7dd <- 0x2300c427 +mem-write: 0x8000e7e1 <- 0x8300e526 +mem-write: 0x8000e7e5 <- 0x63010426 +mem-write: 0x8000e7e9 <- 0x1304f602 +mem-write: 0x8000e7ed <- 0x93010407 +mem-write: 0x8000e7f1 <- 0x6f010507 +mem-write: 0x8000e7f5 <- 0x83c45ff0 +VXDRV: upload 1024 bytes to 0x8000e7f9 +mem-write: 0x8000e7f9 <- 0x23008427 +mem-write: 0x8000e7fd <- 0x8300fc28 +mem-write: 0x8000e801 <- 0x2300c427 +mem-write: 0x8000e805 <- 0x300fc2a +mem-write: 0x8000e809 <- 0xe3010427 +mem-write: 0x8000e80d <- 0x23fad610 +mem-write: 0x8000e811 <- 0x300ec2c +mem-write: 0x8000e815 <- 0x93014427 +mem-write: 0x8000e819 <- 0x13020c07 +mem-write: 0x8000e81d <- 0x23018404 +mem-write: 0x8000e821 <- 0x300ec2e +mem-write: 0x8000e825 <- 0x6f000427 +mem-write: 0x8000e829 <- 0x23cddff0 +mem-write: 0x8000e82d <- 0x8300d528 +mem-write: 0x8000e831 <- 0x13014426 +mem-write: 0x8000e835 <- 0x93018407 +mem-write: 0x8000e839 <- 0x23018507 +mem-write: 0x8000e83d <- 0x8300d52a +mem-write: 0x8000e841 <- 0x6f018426 +mem-write: 0x8000e845 <- 0x93bf5ff0 +mem-write: 0x8000e849 <- 0x13000405 +mem-write: 0x8000e84d <- 0xef000905 +mem-write: 0x8000e851 <- 0x6f94dff0 +mem-write: 0x8000e855 <- 0x83e21ff0 +mem-write: 0x8000e859 <- 0x23008427 +mem-write: 0x8000e85d <- 0x8300fc28 +mem-write: 0x8000e861 <- 0x2300c427 +mem-write: 0x8000e865 <- 0x300fc2a +mem-write: 0x8000e869 <- 0x63010427 +mem-write: 0x8000e86d <- 0x9300d608 +mem-write: 0x8000e871 <- 0x13018c07 +mem-write: 0x8000e875 <- 0x6f010404 +mem-write: 0x8000e879 <- 0x23de9ff0 +mem-write: 0x8000e87d <- 0x300ec2c +mem-write: 0x8000e881 <- 0x93014427 +mem-write: 0x8000e885 <- 0x13020c07 +mem-write: 0x8000e889 <- 0x23018404 +mem-write: 0x8000e88d <- 0x300ec2e +mem-write: 0x8000e891 <- 0x6f000427 +mem-write: 0x8000e895 <- 0x13dcdff0 +mem-write: 0x8000e899 <- 0x23ff0101 +mem-write: 0x8000e89d <- 0x13008124 +mem-write: 0x8000e8a1 <- 0x83000584 +mem-write: 0x8000e8a5 <- 0x230005a5 +mem-write: 0x8000e8a9 <- 0x23009122 +mem-write: 0x8000e8ad <- 0x93001126 +mem-write: 0x8000e8b1 <- 0x63000504 +mem-write: 0x8000e8b5 <- 0xef000584 +mem-write: 0x8000e8b9 <- 0x93fe1ff0 +mem-write: 0x8000e8bd <- 0x3000405 +mem-write: 0x8000e8c1 <- 0x83008124 +mem-write: 0x8000e8c5 <- 0x1300c120 +mem-write: 0x8000e8c9 <- 0x83000485 +mem-write: 0x8000e8cd <- 0x13004124 +mem-write: 0x8000e8d1 <- 0x6f010101 +mem-write: 0x8000e8d5 <- 0x83c91f50 +mem-write: 0x8000e8d9 <- 0x631d81a7 +mem-write: 0x8000e8dd <- 0x8310a780 +mem-write: 0x8000e8e1 <- 0x1304c525 +mem-write: 0x8000e8e5 <- 0x23fe0101 +mem-write: 0x8000e8e9 <- 0x2300912a +mem-write: 0x8000e8ed <- 0x2300112e +mem-write: 0x8000e8f1 <- 0x2300812c +mem-write: 0x8000e8f5 <- 0x23012128 +mem-write: 0x8000e8f9 <- 0x93013126 +mem-write: 0x8000e8fd <- 0x63000504 +mem-write: 0x8000e901 <- 0x13040580 +mem-write: 0x8000e905 <- 0x93000009 +mem-write: 0x8000e909 <- 0xb3080009 +mem-write: 0x8000e90d <- 0x3012587 +mem-write: 0x8000e911 <- 0x630007a4 +mem-write: 0x8000e915 <- 0x9300040e +mem-write: 0x8000e919 <- 0x3000405 +mem-write: 0x8000e91d <- 0x13000424 +mem-write: 0x8000e921 <- 0xef000485 +mem-write: 0x8000e925 <- 0xe3c41f50 +mem-write: 0x8000e929 <- 0x83fe0418 +mem-write: 0x8000e92d <- 0x1304c4a5 +mem-write: 0x8000e931 <- 0xe3004909 +mem-write: 0x8000e935 <- 0x13fd391c +mem-write: 0x8000e939 <- 0xef000485 +mem-write: 0x8000e93d <- 0x83c29f50 +mem-write: 0x8000e941 <- 0x630404a5 +mem-write: 0x8000e945 <- 0x13000586 +mem-write: 0x8000e949 <- 0xef000485 +mem-write: 0x8000e94d <- 0x3c19f50 +mem-write: 0x8000e951 <- 0x631484a4 +mem-write: 0x8000e955 <- 0x13020400 +mem-write: 0x8000e959 <- 0x6314c489 +mem-write: 0x8000e95d <- 0x9301240c +mem-write: 0x8000e961 <- 0x3000405 +mem-write: 0x8000e965 <- 0x13000424 +mem-write: 0x8000e969 <- 0xef000485 +mem-write: 0x8000e96d <- 0xe3bf9f50 +mem-write: 0x8000e971 <- 0x83fe8918 +mem-write: 0x8000e975 <- 0x630544a5 +mem-write: 0x8000e979 <- 0x13000586 +mem-write: 0x8000e97d <- 0xef000485 +mem-write: 0x8000e981 <- 0x83be5f50 +mem-write: 0x8000e985 <- 0x630384a7 +mem-write: 0x8000e989 <- 0x8302078c +mem-write: 0x8000e98d <- 0x1303c4a7 +mem-write: 0x8000e991 <- 0xe7000485 +mem-write: 0x8000e995 <- 0x83000780 +mem-write: 0x8000e999 <- 0x632e04a5 +mem-write: 0x8000e99d <- 0x3020582 +mem-write: 0x8000e9a1 <- 0x83018124 +mem-write: 0x8000e9a5 <- 0x301c120 +mem-write: 0x8000e9a9 <- 0x83010129 +mem-write: 0x8000e9ad <- 0x1300c129 +mem-write: 0x8000e9b1 <- 0x83000485 +mem-write: 0x8000e9b5 <- 0x13014124 +mem-write: 0x8000e9b9 <- 0x6f020101 +mem-write: 0x8000e9bd <- 0x83eddff0 +mem-write: 0x8000e9c1 <- 0x301c120 +mem-write: 0x8000e9c5 <- 0x83018124 +mem-write: 0x8000e9c9 <- 0x3014124 +mem-write: 0x8000e9cd <- 0x83010129 +mem-write: 0x8000e9d1 <- 0x1300c129 +mem-write: 0x8000e9d5 <- 0x67020101 +mem-write: 0x8000e9d9 <- 0x67000080 +mem-write: 0x8000e9dd <- 0x33000080 +mem-write: 0x8000e9e1 <- 0x9300b567 +mem-write: 0x8000e9e5 <- 0x13fff003 +mem-write: 0x8000e9e9 <- 0x63003777 +mem-write: 0x8000e9ed <- 0xb7100710 +mem-write: 0x8000e9f1 <- 0x937f7f87 +mem-write: 0x8000e9f5 <- 0x3f7f787 +mem-write: 0x8000e9f9 <- 0x83000526 +mem-write: 0x8000e9fd <- 0xb30005a6 +mem-write: 0x8000ea01 <- 0x3300f672 +mem-write: 0x8000ea05 <- 0xb300f663 +mem-write: 0x8000ea09 <- 0xb300f282 +mem-write: 0x8000ea0d <- 0x630062e2 +mem-write: 0x8000ea11 <- 0x63107292 +mem-write: 0x8000ea15 <- 0x308d616 +mem-write: 0x8000ea19 <- 0x83004526 +mem-write: 0x8000ea1d <- 0xb30045a6 +mem-write: 0x8000ea21 <- 0x3300f672 +mem-write: 0x8000ea25 <- 0xb300f663 +mem-write: 0x8000ea29 <- 0xb300f282 +mem-write: 0x8000ea2d <- 0x630062e2 +mem-write: 0x8000ea31 <- 0x630c729e +mem-write: 0x8000ea35 <- 0x306d616 +mem-write: 0x8000ea39 <- 0x83008526 +mem-write: 0x8000ea3d <- 0xb30085a6 +mem-write: 0x8000ea41 <- 0x3300f672 +mem-write: 0x8000ea45 <- 0xb300f663 +mem-write: 0x8000ea49 <- 0xb300f282 +mem-write: 0x8000ea4d <- 0x630062e2 +mem-write: 0x8000ea51 <- 0x630c7298 +mem-write: 0x8000ea55 <- 0x304d616 +mem-write: 0x8000ea59 <- 0x8300c526 +mem-write: 0x8000ea5d <- 0xb300c5a6 +mem-write: 0x8000ea61 <- 0x3300f672 +mem-write: 0x8000ea65 <- 0xb300f663 +mem-write: 0x8000ea69 <- 0xb300f282 +mem-write: 0x8000ea6d <- 0x630062e2 +mem-write: 0x8000ea71 <- 0x630c7292 +mem-write: 0x8000ea75 <- 0x302d616 +mem-write: 0x8000ea79 <- 0x83010526 +mem-write: 0x8000ea7d <- 0xb30105a6 +mem-write: 0x8000ea81 <- 0x3300f672 +mem-write: 0x8000ea85 <- 0xb300f663 +mem-write: 0x8000ea89 <- 0xb300f282 +mem-write: 0x8000ea8d <- 0x630062e2 +mem-write: 0x8000ea91 <- 0x130a729c +mem-write: 0x8000ea95 <- 0x93014505 +mem-write: 0x8000ea99 <- 0xe3014585 +mem-write: 0x8000ea9d <- 0x13f4d60e +mem-write: 0x8000eaa1 <- 0x93010617 +mem-write: 0x8000eaa5 <- 0x63010697 +mem-write: 0x8000eaa9 <- 0x1300f71e +mem-write: 0x8000eaad <- 0x93010657 +mem-write: 0x8000eab1 <- 0x330106d7 +mem-write: 0x8000eab5 <- 0x9340f705 +mem-write: 0x8000eab9 <- 0x630ff575 +mem-write: 0x8000eabd <- 0x67020590 +mem-write: 0x8000eac1 <- 0x13000080 +mem-write: 0x8000eac5 <- 0x93010757 +mem-write: 0x8000eac9 <- 0x330107d7 +mem-write: 0x8000eacd <- 0x9340f705 +mem-write: 0x8000ead1 <- 0x630ff575 +mem-write: 0x8000ead5 <- 0x67000594 +mem-write: 0x8000ead9 <- 0x13000080 +mem-write: 0x8000eadd <- 0x930ff777 +mem-write: 0x8000eae1 <- 0x330ff7f7 +mem-write: 0x8000eae5 <- 0x6740f705 +mem-write: 0x8000eae9 <- 0x3000080 +mem-write: 0x8000eaed <- 0x83000546 +mem-write: 0x8000eaf1 <- 0x130005c6 +mem-write: 0x8000eaf5 <- 0x93001505 +mem-write: 0x8000eaf9 <- 0x63001585 +mem-write: 0x8000eafd <- 0xe300d614 +mem-write: 0x8000eb01 <- 0x33fe0616 +mem-write: 0x8000eb05 <- 0x6740d605 +mem-write: 0x8000eb09 <- 0x13000080 +mem-write: 0x8000eb0d <- 0x93004505 +mem-write: 0x8000eb11 <- 0xe3004585 +mem-write: 0x8000eb15 <- 0x13fcd61c +mem-write: 0x8000eb19 <- 0x67000005 +mem-write: 0x8000eb1d <- 0x13000080 +mem-write: 0x8000eb21 <- 0x93008505 +mem-write: 0x8000eb25 <- 0xe3008585 +mem-write: 0x8000eb29 <- 0x13fcd612 +mem-write: 0x8000eb2d <- 0x67000005 +mem-write: 0x8000eb31 <- 0x13000080 +mem-write: 0x8000eb35 <- 0x9300c505 +mem-write: 0x8000eb39 <- 0xe300c585 +mem-write: 0x8000eb3d <- 0x13fad618 +mem-write: 0x8000eb41 <- 0x67000005 +mem-write: 0x8000eb45 <- 0x13000080 +mem-write: 0x8000eb49 <- 0x93010505 +mem-write: 0x8000eb4d <- 0xe3010585 +mem-write: 0x8000eb51 <- 0x13f8d61e +mem-write: 0x8000eb55 <- 0x67000005 +mem-write: 0x8000eb59 <- 0x83000080 +mem-write: 0x8000eb5d <- 0x13008627 +mem-write: 0x8000eb61 <- 0x23fd0101 +mem-write: 0x8000eb65 <- 0x2301512a +mem-write: 0x8000eb69 <- 0x23021126 +mem-write: 0x8000eb6d <- 0x23028124 +mem-write: 0x8000eb71 <- 0x23029122 +mem-write: 0x8000eb75 <- 0x23032120 +mem-write: 0x8000eb79 <- 0x2301312e +mem-write: 0x8000eb7d <- 0x2301412c +mem-write: 0x8000eb81 <- 0x23016128 +mem-write: 0x8000eb85 <- 0x23017126 +mem-write: 0x8000eb89 <- 0x93018124 +mem-write: 0x8000eb8d <- 0x6300060a +mem-write: 0x8000eb91 <- 0x13140788 +mem-write: 0x8000eb95 <- 0x8300050b +mem-write: 0x8000eb99 <- 0x3000629 +mem-write: 0x8000eb9d <- 0x830005a5 +mem-write: 0x8000eba1 <- 0x130085a4 +mem-write: 0x8000eba5 <- 0x6f000584 +mem-write: 0x8000eba9 <- 0x830d4000 +mem-write: 0x8000ebad <- 0x1300c457 +mem-write: 0x8000ebb1 <- 0x634807f7 +mem-write: 0x8000ebb5 <- 0x8308070a +mem-write: 0x8000ebb9 <- 0x83014426 +mem-write: 0x8000ebbd <- 0x13010425 +mem-write: 0x8000ebc1 <- 0x93001907 +mem-write: 0x8000ebc5 <- 0xb3001694 +mem-write: 0x8000ebc9 <- 0x9300d486 +mem-write: 0x8000ebcd <- 0x3301f6d4 +mem-write: 0x8000ebd1 <- 0xb340b50a +mem-write: 0x8000ebd5 <- 0x9300d484 +mem-write: 0x8000ebd9 <- 0x334014d4 +mem-write: 0x8000ebdd <- 0x13014707 +mem-write: 0x8000ebe1 <- 0x63000486 +mem-write: 0x8000ebe5 <- 0x9300e4f6 +mem-write: 0x8000ebe9 <- 0x13000704 +mem-write: 0x8000ebed <- 0x93000706 +mem-write: 0x8000ebf1 <- 0x634007f7 +mem-write: 0x8000ebf5 <- 0x930a0786 +VXDRV: upload 1024 bytes to 0x8000ebf9 +mem-write: 0x8000ebf9 <- 0x13000605 +mem-write: 0x8000ebfd <- 0xef000b05 +mem-write: 0x8000ec01 <- 0x13b39f80 +mem-write: 0x8000ec05 <- 0x6300050c +mem-write: 0x8000ec09 <- 0x830a050a +mem-write: 0x8000ec0d <- 0x13010425 +mem-write: 0x8000ec11 <- 0xef000a06 +mem-write: 0x8000ec15 <- 0x83c6cff0 +mem-write: 0x8000ec19 <- 0x9300c457 +mem-write: 0x8000ec1d <- 0x93b7f7f7 +mem-write: 0x8000ec21 <- 0x230807e7 +mem-write: 0x8000ec25 <- 0x3300f416 +mem-write: 0x8000ec29 <- 0x33014c05 +mem-write: 0x8000ec2d <- 0x2341448a +mem-write: 0x8000ec31 <- 0x2300942a +mem-write: 0x8000ec35 <- 0x23014424 +mem-write: 0x8000ec39 <- 0x23018428 +mem-write: 0x8000ec3d <- 0x9300a420 +mem-write: 0x8000ec41 <- 0x13000904 +mem-write: 0x8000ec45 <- 0x1300090a +mem-write: 0x8000ec49 <- 0x93000a06 +mem-write: 0x8000ec4d <- 0xef000b85 +mem-write: 0x8000ec51 <- 0x3d4cff0 +mem-write: 0x8000ec55 <- 0x3008427 +mem-write: 0x8000ec59 <- 0x83000425 +mem-write: 0x8000ec5d <- 0xb3008aa7 +mem-write: 0x8000ec61 <- 0x33409704 +mem-write: 0x8000ec65 <- 0x23014505 +mem-write: 0x8000ec69 <- 0x23009424 +mem-write: 0x8000ec6d <- 0x3300a420 +mem-write: 0x8000ec71 <- 0x23412789 +mem-write: 0x8000ec75 <- 0x63012aa4 +mem-write: 0x8000ec79 <- 0x3060904 +mem-write: 0x8000ec7d <- 0x830049a9 +mem-write: 0x8000ec81 <- 0x130009ab +mem-write: 0x8000ec85 <- 0x9300048a +mem-write: 0x8000ec89 <- 0xe3008989 +mem-write: 0x8000ec8d <- 0xe3fe0908 +mem-write: 0x8000ec91 <- 0x93f0997e +mem-write: 0x8000ec95 <- 0x13000904 +mem-write: 0x8000ec99 <- 0x6f00090a +mem-write: 0x8000ec9d <- 0x13fadff0 +mem-write: 0x8000eca1 <- 0xef000b05 +mem-write: 0x8000eca5 <- 0x13e80ff0 +mem-write: 0x8000eca9 <- 0xe300050c +mem-write: 0x8000ecad <- 0x83f6051e +mem-write: 0x8000ecb1 <- 0x13010425 +mem-write: 0x8000ecb5 <- 0xef000b05 +mem-write: 0x8000ecb9 <- 0x938adf50 +mem-write: 0x8000ecbd <- 0x2300c007 +mem-write: 0x8000ecc1 <- 0x8300fb20 +mem-write: 0x8000ecc5 <- 0x1300c457 +mem-write: 0x8000ecc9 <- 0x93fff005 +mem-write: 0x8000eccd <- 0x230407e7 +mem-write: 0x8000ecd1 <- 0x2300f416 +mem-write: 0x8000ecd5 <- 0x23000aa4 +mem-write: 0x8000ecd9 <- 0x6f000aa2 +mem-write: 0x8000ecdd <- 0x2300c000 +mem-write: 0x8000ece1 <- 0x13000aa2 +mem-write: 0x8000ece5 <- 0x83000005 +mem-write: 0x8000ece9 <- 0x302c120 +mem-write: 0x8000eced <- 0x83028124 +mem-write: 0x8000ecf1 <- 0x3024124 +mem-write: 0x8000ecf5 <- 0x83020129 +mem-write: 0x8000ecf9 <- 0x301c129 +mem-write: 0x8000ecfd <- 0x8301812a +mem-write: 0x8000ed01 <- 0x301412a +mem-write: 0x8000ed05 <- 0x8301012b +mem-write: 0x8000ed09 <- 0x300c12b +mem-write: 0x8000ed0d <- 0x1300812c +mem-write: 0x8000ed11 <- 0x67030101 +mem-write: 0x8000ed15 <- 0x83000080 +mem-write: 0x8000ed19 <- 0x1300c5d7 +mem-write: 0x8000ed1d <- 0x23ed0101 +mem-write: 0x8000ed21 <- 0x2311412c +mem-write: 0x8000ed25 <- 0x23116128 +mem-write: 0x8000ed29 <- 0x2311a120 +mem-write: 0x8000ed2d <- 0x23121126 +mem-write: 0x8000ed31 <- 0x23128124 +mem-write: 0x8000ed35 <- 0x23129122 +mem-write: 0x8000ed39 <- 0x23132120 +mem-write: 0x8000ed3d <- 0x2311312e +mem-write: 0x8000ed41 <- 0x2311512a +mem-write: 0x8000ed45 <- 0x23117126 +mem-write: 0x8000ed49 <- 0x23118124 +mem-write: 0x8000ed4d <- 0x23119122 +mem-write: 0x8000ed51 <- 0x930fb12e +mem-write: 0x8000ed55 <- 0x230807f7 +mem-write: 0x8000ed59 <- 0x1300d126 +mem-write: 0x8000ed5d <- 0x1300058a +mem-write: 0x8000ed61 <- 0x1300050b +mem-write: 0x8000ed65 <- 0x6300060d +mem-write: 0x8000ed69 <- 0x83000786 +mem-write: 0x8000ed6d <- 0xe30105a7 +mem-write: 0x8000ed71 <- 0xb75e0784 +mem-write: 0x8000ed75 <- 0x93800157 +mem-write: 0x8000ed79 <- 0x9304c10a +mem-write: 0x8000ed7d <- 0xb7370787 +mem-write: 0x8000ed81 <- 0xb780015b +mem-write: 0x8000ed85 <- 0x93800154 +mem-write: 0x8000ed89 <- 0x23000d09 +mem-write: 0x8000ed8d <- 0x23055120 +mem-write: 0x8000ed91 <- 0x23040124 +mem-write: 0x8000ed95 <- 0x23040122 +mem-write: 0x8000ed99 <- 0x2300012a +mem-write: 0x8000ed9d <- 0x2300012c +mem-write: 0x8000eda1 <- 0x23020120 +mem-write: 0x8000eda5 <- 0x2300012e +mem-write: 0x8000eda9 <- 0x23000124 +mem-write: 0x8000edad <- 0x9300f128 +mem-write: 0x8000edb1 <- 0x934dcb8b +mem-write: 0x8000edb5 <- 0x134ec484 +mem-write: 0x8000edb9 <- 0x83000a8d +mem-write: 0x8000edbd <- 0x630009c7 +mem-write: 0x8000edc1 <- 0x1320078c +mem-write: 0x8000edc5 <- 0x93000984 +mem-write: 0x8000edc9 <- 0x63025006 +mem-write: 0x8000edcd <- 0x832ad788 +mem-write: 0x8000edd1 <- 0x13001447 +mem-write: 0x8000edd5 <- 0xe3001404 +mem-write: 0x8000edd9 <- 0x33fe079a +mem-write: 0x8000eddd <- 0x6341340c +mem-write: 0x8000ede1 <- 0x831f340c +mem-write: 0x8000ede5 <- 0x83048126 +mem-write: 0x8000ede9 <- 0x23044127 +mem-write: 0x8000eded <- 0xb3013d20 +mem-write: 0x8000edf1 <- 0x93018686 +mem-write: 0x8000edf5 <- 0x23001787 +mem-write: 0x8000edf9 <- 0x23018d22 +mem-write: 0x8000edfd <- 0x2304d124 +mem-write: 0x8000ee01 <- 0x9304f122 +mem-write: 0x8000ee05 <- 0x13007006 +mem-write: 0x8000ee09 <- 0x63008d0d +mem-write: 0x8000ee0d <- 0x328f6c0 +mem-write: 0x8000ee11 <- 0x83008127 +mem-write: 0x8000ee15 <- 0x33000447 +mem-write: 0x8000ee19 <- 0x23018707 +mem-write: 0x8000ee1d <- 0x6300e124 +mem-write: 0x8000ee21 <- 0x931a078c +mem-write: 0x8000ee25 <- 0x83fff008 +mem-write: 0x8000ee29 <- 0x93001446 +mem-write: 0x8000ee2d <- 0xa3001409 +mem-write: 0x8000ee31 <- 0x2302010d +mem-write: 0x8000ee35 <- 0x13000122 +mem-write: 0x8000ee39 <- 0x13000009 +mem-write: 0x8000ee3d <- 0x9305a00c +mem-write: 0x8000ee41 <- 0x9300900c +mem-write: 0x8000ee45 <- 0x1302a005 +mem-write: 0x8000ee49 <- 0x93000884 +mem-write: 0x8000ee4d <- 0x93001989 +mem-write: 0x8000ee51 <- 0x63fe0687 +mem-write: 0x8000ee55 <- 0x304fc68 +mem-write: 0x8000ee59 <- 0x93010127 +mem-write: 0x8000ee5d <- 0xb3002797 +mem-write: 0x8000ee61 <- 0x8300e787 +mem-write: 0x8000ee65 <- 0x670007a7 +mem-write: 0x8000ee69 <- 0x23000780 +mem-write: 0x8000ee6d <- 0x93000122 +mem-write: 0x8000ee71 <- 0x3fd0687 +mem-write: 0x8000ee75 <- 0x83004126 +mem-write: 0x8000ee79 <- 0x930009c6 +mem-write: 0x8000ee7d <- 0x13001989 +mem-write: 0x8000ee81 <- 0x33002617 +mem-write: 0x8000ee85 <- 0x1300c707 +mem-write: 0x8000ee89 <- 0xb3001717 +mem-write: 0x8000ee8d <- 0x2300e787 +mem-write: 0x8000ee91 <- 0x9300f122 +mem-write: 0x8000ee95 <- 0xe3fd0687 +mem-write: 0x8000ee99 <- 0x93fcfcfe +mem-write: 0x8000ee9d <- 0xe3fe0687 +mem-write: 0x8000eea1 <- 0x63fafc7c +mem-write: 0x8000eea5 <- 0x2312068a +mem-write: 0x8000eea9 <- 0xa308d106 +mem-write: 0x8000eead <- 0x1302010d +mem-write: 0x8000eeb1 <- 0x9300100c +mem-write: 0x8000eeb5 <- 0x1300100c +mem-write: 0x8000eeb9 <- 0x9308c104 +mem-write: 0x8000eebd <- 0x13000008 +mem-write: 0x8000eec1 <- 0x6300297f +mem-write: 0x8000eec5 <- 0x13000f04 +mem-write: 0x8000eec9 <- 0x93002c0c +mem-write: 0x8000eecd <- 0x8308497e +mem-write: 0x8000eed1 <- 0x3048127 +mem-write: 0x8000eed5 <- 0x63044126 +mem-write: 0x8000eed9 <- 0x3000e98 +mem-write: 0x8000eedd <- 0xb3004127 +mem-write: 0x8000eee1 <- 0x6341870d +mem-write: 0x8000eee5 <- 0x37bb04a +mem-write: 0x8000eee9 <- 0x9303b145 +mem-write: 0x8000eeed <- 0x93001605 +mem-write: 0x8000eef1 <- 0x63008d06 +mem-write: 0x8000eef5 <- 0x13040500 +mem-write: 0x8000eef9 <- 0x9303b105 +mem-write: 0x8000eefd <- 0x23001787 +mem-write: 0x8000ef01 <- 0x1300ad20 +mem-write: 0x8000ef05 <- 0x23001005 +mem-write: 0x8000ef09 <- 0x2300ad22 +mem-write: 0x8000ef0d <- 0x2304f124 +mem-write: 0x8000ef11 <- 0x1304b122 +mem-write: 0x8000ef15 <- 0xe3007005 +mem-write: 0x8000ef19 <- 0x930ab540 +mem-write: 0x8000ef1d <- 0x1300260f +mem-write: 0x8000ef21 <- 0x13010d05 +mem-write: 0x8000ef25 <- 0x13000586 +mem-write: 0x8000ef29 <- 0x9300068d +mem-write: 0x8000ef2d <- 0x93000f85 +mem-write: 0x8000ef31 <- 0x63000506 +mem-write: 0x8000ef35 <- 0x13020f0c +mem-write: 0x8000ef39 <- 0x9303c106 +mem-write: 0x8000ef3d <- 0x23002787 +mem-write: 0x8000ef41 <- 0x1300cd20 +mem-write: 0x8000ef45 <- 0x23002006 +mem-write: 0x8000ef49 <- 0x2300cd22 +mem-write: 0x8000ef4d <- 0x2304f124 +mem-write: 0x8000ef51 <- 0x1304b122 +mem-write: 0x8000ef55 <- 0xe3007007 +mem-write: 0x8000ef59 <- 0x130ab742 +mem-write: 0x8000ef5d <- 0x13000586 +mem-write: 0x8000ef61 <- 0x9300068d +mem-write: 0x8000ef65 <- 0x93001585 +mem-write: 0x8000ef69 <- 0x13008686 +mem-write: 0x8000ef6d <- 0x63080005 +mem-write: 0x8000ef71 <- 0xb354ae8c +mem-write: 0x8000ef75 <- 0x6341988d +mem-write: 0x8000ef79 <- 0xb363b044 +mem-write: 0x8000ef7d <- 0x2300fc87 +mem-write: 0x8000ef81 <- 0x23008d20 +mem-write: 0x8000ef85 <- 0x23019d22 +mem-write: 0x8000ef89 <- 0x2304f124 +mem-write: 0x8000ef8d <- 0x1304b122 +mem-write: 0x8000ef91 <- 0x63007007 +mem-write: 0x8000ef95 <- 0x136cb742 +mem-write: 0x8000ef99 <- 0x63004973 +mem-write: 0x8000ef9d <- 0x3000308 +mem-write: 0x8000efa1 <- 0xb3004127 +mem-write: 0x8000efa5 <- 0xe341870c +mem-write: 0x8000efa9 <- 0x3099048 +mem-write: 0x8000efad <- 0x63004124 +mem-write: 0x8000efb1 <- 0x13018454 +mem-write: 0x8000efb5 <- 0x3000c04 +mem-write: 0x8000efb9 <- 0x33008127 +mem-write: 0x8000efbd <- 0x23008707 +mem-write: 0x8000efc1 <- 0x6300e124 +mem-write: 0x8000efc5 <- 0x836a079a +mem-write: 0x8000efc9 <- 0x230009c7 +mem-write: 0x8000efcd <- 0x13040122 +mem-write: 0x8000efd1 <- 0xe3000a8d +mem-write: 0x8000efd5 <- 0x83de0798 +mem-write: 0x8000efd9 <- 0xe3048127 +mem-write: 0x8000efdd <- 0x8356079e +mem-write: 0x8000efe1 <- 0x9300ca57 +mem-write: 0x8000efe5 <- 0xe30407f7 +mem-write: 0x8000efe9 <- 0x835a0794 +mem-write: 0x8000efed <- 0x312c120 +mem-write: 0x8000eff1 <- 0x3128124 +mem-write: 0x8000eff5 <- 0x83008125 +VXDRV: upload 1024 bytes to 0x8000eff9 +mem-write: 0x8000eff9 <- 0x3124124 +mem-write: 0x8000effd <- 0x83120129 +mem-write: 0x8000f001 <- 0x311c129 +mem-write: 0x8000f005 <- 0x8311812a +mem-write: 0x8000f009 <- 0x311412a +mem-write: 0x8000f00d <- 0x8311012b +mem-write: 0x8000f011 <- 0x310c12b +mem-write: 0x8000f015 <- 0x8310812c +mem-write: 0x8000f019 <- 0x310412c +mem-write: 0x8000f01d <- 0x8310012d +mem-write: 0x8000f021 <- 0x130fc12d +mem-write: 0x8000f025 <- 0x67130101 +mem-write: 0x8000f029 <- 0x13000080 +mem-write: 0x8000f02d <- 0xef000b05 +mem-write: 0x8000f031 <- 0x83d08f80 +mem-write: 0x8000f035 <- 0x13004527 +mem-write: 0x8000f039 <- 0x23000785 +mem-write: 0x8000f03d <- 0xef00f12e +mem-write: 0x8000f041 <- 0x93cacfa0 +mem-write: 0x8000f045 <- 0x13000507 +mem-write: 0x8000f049 <- 0x93000b05 +mem-write: 0x8000f04d <- 0x2300078d +mem-write: 0x8000f051 <- 0xef02f120 +mem-write: 0x8000f055 <- 0x83ce4f80 +mem-write: 0x8000f059 <- 0x93008527 +mem-write: 0x8000f05d <- 0x2302a005 +mem-write: 0x8000f061 <- 0xe300f12c +mem-write: 0x8000f065 <- 0x831e0d98 +mem-write: 0x8000f069 <- 0x6f0009c6 +mem-write: 0x8000f06d <- 0x83de1ff0 +mem-write: 0x8000f071 <- 0x130009c6 +mem-write: 0x8000f075 <- 0x6f020969 +mem-write: 0x8000f079 <- 0x33dd5ff0 +mem-write: 0x8000f07d <- 0xe341340c +mem-write: 0x8000f081 <- 0x83d73412 +mem-write: 0x8000f085 <- 0x6f000447 +mem-write: 0x8000f089 <- 0x13d99ff0 +mem-write: 0x8000f08d <- 0x93040106 +mem-write: 0x8000f091 <- 0x13000a05 +mem-write: 0x8000f095 <- 0xef000b05 +mem-write: 0x8000f099 <- 0xe3ac5ff0 +mem-write: 0x8000f09d <- 0x13f40512 +mem-write: 0x8000f0a1 <- 0x6f000a8d +mem-write: 0x8000f0a5 <- 0x83d6dff0 +mem-write: 0x8000f0a9 <- 0x9300c127 +mem-write: 0x8000f0ad <- 0xa3000408 +mem-write: 0x8000f0b1 <- 0x302010d +mem-write: 0x8000f0b5 <- 0x930007a4 +mem-write: 0x8000f0b9 <- 0xe300478d +mem-write: 0x8000f0bd <- 0x93380404 +mem-write: 0x8000f0c1 <- 0xe3fff007 +mem-write: 0x8000f0c5 <- 0x1326f88e +mem-write: 0x8000f0c9 <- 0x93000886 +mem-write: 0x8000f0cd <- 0x13000005 +mem-write: 0x8000f0d1 <- 0x23000405 +mem-write: 0x8000f0d5 <- 0xef011126 +mem-write: 0x8000f0d9 <- 0x83df9f80 +mem-write: 0x8000f0dd <- 0xe300c128 +mem-write: 0x8000f0e1 <- 0xb3480506 +mem-write: 0x8000f0e5 <- 0x2340850c +mem-write: 0x8000f0e9 <- 0x9301b126 +mem-write: 0x8000f0ed <- 0x6f000008 +mem-write: 0x8000f0f1 <- 0x3094000 +mem-write: 0x8000f0f5 <- 0xa300c127 +mem-write: 0x8000f0f9 <- 0x1302010d +mem-write: 0x8000f0fd <- 0x8300100c +mem-write: 0x8000f101 <- 0x13000727 +mem-write: 0x8000f105 <- 0x23004707 +mem-write: 0x8000f109 <- 0x2300e126 +mem-write: 0x8000f10d <- 0x9308f106 +mem-write: 0x8000f111 <- 0x1300100c +mem-write: 0x8000f115 <- 0x6f08c104 +mem-write: 0x8000f119 <- 0x93da5ff0 +mem-write: 0x8000f11d <- 0x93020977 +mem-write: 0x8000f121 <- 0x63000408 +mem-write: 0x8000f125 <- 0x830e078e +mem-write: 0x8000f129 <- 0x9300c127 +mem-write: 0x8000f12d <- 0x93007787 +mem-write: 0x8000f131 <- 0x83ff87f7 +mem-write: 0x8000f135 <- 0x830047a6 +mem-write: 0x8000f139 <- 0x930007ac +mem-write: 0x8000f13d <- 0x23008787 +mem-write: 0x8000f141 <- 0x1300f126 +mem-write: 0x8000f145 <- 0x6300068c +mem-write: 0x8000f149 <- 0x931006c4 +mem-write: 0x8000f14d <- 0x93fff006 +mem-write: 0x8000f151 <- 0x6300090d +mem-write: 0x8000f155 <- 0xb300d888 +mem-write: 0x8000f159 <- 0x93018ce6 +mem-write: 0x8000f15d <- 0x63f7f97d +mem-write: 0x8000f161 <- 0xe376068e +mem-write: 0x8000f165 <- 0x93000c1c +mem-write: 0x8000f169 <- 0xe3009006 +mem-write: 0x8000f16d <- 0x930196e8 +mem-write: 0x8000f171 <- 0xa3030c87 +mem-write: 0x8000f175 <- 0x130ef107 +mem-write: 0x8000f179 <- 0x93000d89 +mem-write: 0x8000f17d <- 0x1300100c +mem-write: 0x8000f181 <- 0x130ef104 +mem-write: 0x8000f185 <- 0x6300088c +mem-write: 0x8000f189 <- 0x130198d4 +mem-write: 0x8000f18d <- 0x83000c8c +mem-write: 0x8000f191 <- 0xb303b147 +mem-write: 0x8000f195 <- 0x3300f037 +mem-write: 0x8000f199 <- 0x6f00fc0c +mem-write: 0x8000f19d <- 0x93d25ff0 +mem-write: 0x8000f1a1 <- 0x13000408 +mem-write: 0x8000f1a5 <- 0x93010969 +mem-write: 0x8000f1a9 <- 0x63020977 +mem-write: 0x8000f1ad <- 0x83740784 +mem-write: 0x8000f1b1 <- 0x9300c127 +mem-write: 0x8000f1b5 <- 0x93007787 +mem-write: 0x8000f1b9 <- 0x83ff87f7 +mem-write: 0x8000f1bd <- 0x30007ac +mem-write: 0x8000f1c1 <- 0x930047ac +mem-write: 0x8000f1c5 <- 0x23008787 +mem-write: 0x8000f1c9 <- 0x9300f126 +mem-write: 0x8000f1cd <- 0x93bff97d +mem-write: 0x8000f1d1 <- 0xa3000006 +mem-write: 0x8000f1d5 <- 0x1302010d +mem-write: 0x8000f1d9 <- 0x63fff006 +mem-write: 0x8000f1dd <- 0x3308c88e +mem-write: 0x8000f1e1 <- 0x13018ce6 +mem-write: 0x8000f1e5 <- 0x63f7fdf9 +mem-write: 0x8000f1e9 <- 0x634a0614 +mem-write: 0x8000f1ed <- 0x63280892 +mem-write: 0x8000f1f1 <- 0x936e069a +mem-write: 0x8000f1f5 <- 0x13001dfc +mem-write: 0x8000f1f9 <- 0xe30f0104 +mem-write: 0x8000f1fd <- 0x93f80c84 +mem-write: 0x8000f201 <- 0xa3030007 +mem-write: 0x8000f205 <- 0x130ef107 +mem-write: 0x8000f209 <- 0x6f0ef104 +mem-write: 0x8000f20d <- 0x13f79ff0 +mem-write: 0x8000f211 <- 0x93010969 +mem-write: 0x8000f215 <- 0x93020977 +mem-write: 0x8000f219 <- 0xe3000408 +mem-write: 0x8000f21d <- 0x3f00796 +mem-write: 0x8000f221 <- 0x9300c127 +mem-write: 0x8000f225 <- 0x93010977 +mem-write: 0x8000f229 <- 0xe3004706 +mem-write: 0x8000f22d <- 0x93040792 +mem-write: 0x8000f231 <- 0xe3040977 +mem-write: 0x8000f235 <- 0x83260786 +mem-write: 0x8000f239 <- 0x2300c127 +mem-write: 0x8000f23d <- 0x8300d126 +mem-write: 0x8000f241 <- 0x1300079c +mem-write: 0x8000f245 <- 0x9341fcdc +mem-write: 0x8000f249 <- 0xe3000c06 +mem-write: 0x8000f24d <- 0xb3f006d0 +mem-write: 0x8000f251 <- 0xb3019036 +mem-write: 0x8000f255 <- 0x3341800e +mem-write: 0x8000f259 <- 0x9340de8c +mem-write: 0x8000f25d <- 0xa302d006 +mem-write: 0x8000f261 <- 0x1302d10d +mem-write: 0x8000f265 <- 0xb3fff006 +mem-write: 0x8000f269 <- 0x9341900c +mem-write: 0x8000f26d <- 0x9300090d +mem-write: 0x8000f271 <- 0xe3001006 +mem-write: 0x8000f275 <- 0x13f6c896 +mem-write: 0x8000f279 <- 0xe3001006 +mem-write: 0x8000f27d <- 0x13eec684 +mem-write: 0x8000f281 <- 0x63002006 +mem-write: 0x8000f285 <- 0x1320c680 +mem-write: 0x8000f289 <- 0x930f0104 +mem-write: 0x8000f28d <- 0x9301dc17 +mem-write: 0x8000f291 <- 0x93007cf6 +mem-write: 0x8000f295 <- 0x93003cdc +mem-write: 0x8000f299 <- 0xb3030686 +mem-write: 0x8000f29d <- 0x130197ec +mem-write: 0x8000f2a1 <- 0xa3003c5c +mem-write: 0x8000f2a5 <- 0xb3fed40f +mem-write: 0x8000f2a9 <- 0x93018ce7 +mem-write: 0x8000f2ad <- 0x13000405 +mem-write: 0x8000f2b1 <- 0xe3fff404 +mem-write: 0x8000f2b5 <- 0x93fc079c +mem-write: 0x8000f2b9 <- 0x63001df7 +mem-write: 0x8000f2bd <- 0x931e078e +mem-write: 0x8000f2c1 <- 0x63030007 +mem-write: 0x8000f2c5 <- 0x931ef68a +mem-write: 0x8000f2c9 <- 0xa3ffe585 +mem-write: 0x8000f2cd <- 0x93fef40f +mem-write: 0x8000f2d1 <- 0xb30f0107 +mem-write: 0x8000f2d5 <- 0x1340b78c +mem-write: 0x8000f2d9 <- 0x13000d89 +mem-write: 0x8000f2dd <- 0x6f000584 +mem-write: 0x8000f2e1 <- 0x93ea5ff0 +mem-write: 0x8000f2e5 <- 0x93000408 +mem-write: 0x8000f2e9 <- 0x9301096d +mem-write: 0x8000f2ed <- 0x63020df7 +mem-write: 0x8000f2f1 <- 0x83620788 +mem-write: 0x8000f2f5 <- 0x9300c127 +mem-write: 0x8000f2f9 <- 0x13001006 +mem-write: 0x8000f2fd <- 0x13007789 +mem-write: 0x8000f301 <- 0x93ff8979 +mem-write: 0x8000f305 <- 0x83008907 +mem-write: 0x8000f309 <- 0x300092c +mem-write: 0x8000f30d <- 0x2300492c +mem-write: 0x8000f311 <- 0x6f00f126 +mem-write: 0x8000f315 <- 0x83ec1ff0 +mem-write: 0x8000f319 <- 0xb700c127 +mem-write: 0x8000f31d <- 0x93ffff86 +mem-write: 0x8000f321 <- 0x838306c6 +mem-write: 0x8000f325 <- 0x930007ac +mem-write: 0x8000f329 <- 0x23004787 +mem-write: 0x8000f32d <- 0xb700f126 +mem-write: 0x8000f331 <- 0x93800157 +mem-write: 0x8000f335 <- 0x23a3c787 +mem-write: 0x8000f339 <- 0x9302d11e +mem-write: 0x8000f33d <- 0x13000408 +mem-write: 0x8000f341 <- 0x9300000c +mem-write: 0x8000f345 <- 0x2300296d +mem-write: 0x8000f349 <- 0x9300f12a +mem-write: 0x8000f34d <- 0x6f002006 +mem-write: 0x8000f351 <- 0x83e85ff0 +mem-write: 0x8000f355 <- 0x130009c6 +mem-write: 0x8000f359 <- 0x6f080969 +mem-write: 0x8000f35d <- 0x83af1ff0 +mem-write: 0x8000f361 <- 0x130009c6 +mem-write: 0x8000f365 <- 0xe3001987 +mem-write: 0x8000f369 <- 0x9322b68a +mem-write: 0x8000f36d <- 0x93fd0687 +mem-write: 0x8000f371 <- 0x13000709 +mem-write: 0x8000f375 <- 0xe3000004 +mem-write: 0x8000f379 <- 0x83acfcec +mem-write: 0x8000f37d <- 0x130009c6 +mem-write: 0x8000f381 <- 0xb3002417 +mem-write: 0x8000f385 <- 0x93008708 +mem-write: 0x8000f389 <- 0x33001898 +mem-write: 0x8000f38d <- 0x9300f884 +mem-write: 0x8000f391 <- 0x93fd0687 +mem-write: 0x8000f395 <- 0xe3001989 +mem-write: 0x8000f399 <- 0x6ffefcf2 +mem-write: 0x8000f39d <- 0x83ab5ff0 +mem-write: 0x8000f3a1 <- 0x130009c6 +mem-write: 0x8000f3a5 <- 0x6f004969 +mem-write: 0x8000f3a9 <- 0x93aa5ff0 +mem-write: 0x8000f3ad <- 0x8302b007 +mem-write: 0x8000f3b1 <- 0xa30009c6 +mem-write: 0x8000f3b5 <- 0x6f02f10d +mem-write: 0x8000f3b9 <- 0x3a95ff0 +mem-write: 0x8000f3bd <- 0x8300c127 +mem-write: 0x8000f3c1 <- 0x830009c6 +mem-write: 0x8000f3c5 <- 0x13000727 +mem-write: 0x8000f3c9 <- 0x23004707 +mem-write: 0x8000f3cd <- 0x2300e126 +mem-write: 0x8000f3d1 <- 0xe300f122 +mem-write: 0x8000f3d5 <- 0xb3a607dc +mem-write: 0x8000f3d9 <- 0x2340f007 +mem-write: 0x8000f3dd <- 0x1300f122 +mem-write: 0x8000f3e1 <- 0x6f004969 +mem-write: 0x8000f3e5 <- 0x83a69ff0 +mem-write: 0x8000f3e9 <- 0x130009c6 +mem-write: 0x8000f3ed <- 0x6f001969 +mem-write: 0x8000f3f1 <- 0x83a5dff0 +mem-write: 0x8000f3f5 <- 0x8303b147 +VXDRV: upload 1024 bytes to 0x8000f3f9 +mem-write: 0x8000f3f9 <- 0xe30009c6 +mem-write: 0x8000f3fd <- 0x93a40798 +mem-write: 0x8000f401 <- 0xa3020007 +mem-write: 0x8000f405 <- 0x6f02f10d +mem-write: 0x8000f409 <- 0x83a45ff0 +mem-write: 0x8000f40d <- 0x930009c6 +mem-write: 0x8000f411 <- 0x63068007 +mem-write: 0x8000f415 <- 0x137ef68e +mem-write: 0x8000f419 <- 0x6f040969 +mem-write: 0x8000f41d <- 0x3a31ff0 +mem-write: 0x8000f421 <- 0x9300c127 +mem-write: 0x8000f425 <- 0x83020977 +mem-write: 0x8000f429 <- 0x13000726 +mem-write: 0x8000f42d <- 0x23004707 +mem-write: 0x8000f431 <- 0x6300e126 +mem-write: 0x8000f435 <- 0x935e079c +mem-write: 0x8000f439 <- 0x63010977 +mem-write: 0x8000f43d <- 0x937e079e +mem-write: 0x8000f441 <- 0xe3040977 +mem-write: 0x8000f445 <- 0x13100794 +mem-write: 0x8000f449 <- 0x63200973 +mem-write: 0x8000f44d <- 0x837e0306 +mem-write: 0x8000f451 <- 0x23008127 +mem-write: 0x8000f455 <- 0x6f00f680 +mem-write: 0x8000f459 <- 0x83965ff0 +mem-write: 0x8000f45d <- 0x930009c6 +mem-write: 0x8000f461 <- 0x6306c007 +mem-write: 0x8000f465 <- 0x137af68e +mem-write: 0x8000f469 <- 0x6f010969 +mem-write: 0x8000f46d <- 0x139e1ff0 +mem-write: 0x8000f471 <- 0xe3001006 +mem-write: 0x8000f475 <- 0x1310c684 +mem-write: 0x8000f479 <- 0x93002006 +mem-write: 0x8000f47d <- 0xe300090d +mem-write: 0x8000f481 <- 0x83e0c694 +mem-write: 0x8000f485 <- 0x13014126 +mem-write: 0x8000f489 <- 0x930f0104 +mem-write: 0x8000f48d <- 0xb300fcf7 +mem-write: 0x8000f491 <- 0x300f687 +mem-write: 0x8000f495 <- 0x930007c7 +mem-write: 0x8000f499 <- 0x93004cdc +mem-write: 0x8000f49d <- 0xb301cc17 +mem-write: 0x8000f4a1 <- 0x130197ec +mem-write: 0x8000f4a5 <- 0xa3004c5c +mem-write: 0x8000f4a9 <- 0xb3fee40f +mem-write: 0x8000f4ad <- 0x13018ce7 +mem-write: 0x8000f4b1 <- 0xe3fff404 +mem-write: 0x8000f4b5 <- 0x93fc079c +mem-write: 0x8000f4b9 <- 0xb30f0107 +mem-write: 0x8000f4bd <- 0x1340878c +mem-write: 0x8000f4c1 <- 0x6f000d89 +mem-write: 0x8000f4c5 <- 0x3cc1ff0 +mem-write: 0x8000f4c9 <- 0xb3004127 +mem-write: 0x8000f4cd <- 0xe341870d +mem-write: 0x8000f4d1 <- 0x13abb052 +mem-write: 0x8000f4d5 <- 0xe3010005 +mem-write: 0x8000f4d9 <- 0x230bb556 +mem-write: 0x8000f4dd <- 0x93028122 +mem-write: 0x8000f4e1 <- 0x13010006 +mem-write: 0x8000f4e5 <- 0x93000a04 +mem-write: 0x8000f4e9 <- 0x1300700e +mem-write: 0x8000f4ed <- 0x93000d8a +mem-write: 0x8000f4f1 <- 0x9300098d +mem-write: 0x8000f4f5 <- 0x6f000889 +mem-write: 0x8000f4f9 <- 0x1300c000 +mem-write: 0x8000f4fd <- 0x63ff0a0a +mem-write: 0x8000f501 <- 0x930546da +mem-write: 0x8000f505 <- 0x13010787 +mem-write: 0x8000f509 <- 0x23001606 +mem-write: 0x8000f50d <- 0x23009d20 +mem-write: 0x8000f511 <- 0x2300dd22 +mem-write: 0x8000f515 <- 0x2304f124 +mem-write: 0x8000f519 <- 0x1304c122 +mem-write: 0x8000f51d <- 0xe3008d0d +mem-write: 0x8000f521 <- 0x13fccede +mem-write: 0x8000f525 <- 0x93040106 +mem-write: 0x8000f529 <- 0x13000405 +mem-write: 0x8000f52d <- 0xef000b05 +mem-write: 0x8000f531 <- 0x63e2cff0 +mem-write: 0x8000f535 <- 0x936e051e +mem-write: 0x8000f539 <- 0x13010006 +mem-write: 0x8000f53d <- 0x83ff0a0a +mem-write: 0x8000f541 <- 0x3048127 +mem-write: 0x8000f545 <- 0x13044126 +mem-write: 0x8000f549 <- 0x93000a8d +mem-write: 0x8000f54d <- 0xe300700e +mem-write: 0x8000f551 <- 0x93fb46ca +mem-write: 0x8000f555 <- 0x93000988 +mem-write: 0x8000f559 <- 0x93000d89 +mem-write: 0x8000f55d <- 0x13000a0d +mem-write: 0x8000f561 <- 0x300040a +mem-write: 0x8000f565 <- 0x13024124 +mem-write: 0x8000f569 <- 0x13001606 +mem-write: 0x8000f56d <- 0xb3008d05 +mem-write: 0x8000f571 <- 0x2301b787 +mem-write: 0x8000f575 <- 0x23009d20 +mem-write: 0x8000f579 <- 0x2301bd22 +mem-write: 0x8000f57d <- 0x2304f124 +mem-write: 0x8000f581 <- 0x1304c122 +mem-write: 0x8000f585 <- 0x63007007 +mem-write: 0x8000f589 <- 0xb364c74a +mem-write: 0x8000f58d <- 0x9341988d +mem-write: 0x8000f591 <- 0x93001605 +mem-write: 0x8000f595 <- 0x13008506 +mem-write: 0x8000f599 <- 0xe300050d +mem-write: 0x8000f59d <- 0x139fb050 +mem-write: 0x8000f5a1 <- 0x63010005 +mem-write: 0x8000f5a5 <- 0x9373b55e +mem-write: 0x8000f5a9 <- 0x93010006 +mem-write: 0x8000f5ad <- 0x6f007008 +mem-write: 0x8000f5b1 <- 0x9300c000 +mem-write: 0x8000f5b5 <- 0x63ff0d8d +mem-write: 0x8000f5b9 <- 0x9305b6da +mem-write: 0x8000f5bd <- 0x13010787 +mem-write: 0x8000f5c1 <- 0x23001606 +mem-write: 0x8000f5c5 <- 0x23009d20 +mem-write: 0x8000f5c9 <- 0x2300dd22 +mem-write: 0x8000f5cd <- 0x2304f124 +mem-write: 0x8000f5d1 <- 0x1304c122 +mem-write: 0x8000f5d5 <- 0xe3008d0d +mem-write: 0x8000f5d9 <- 0x13fcc8de +mem-write: 0x8000f5dd <- 0x93040106 +mem-write: 0x8000f5e1 <- 0x13000a05 +mem-write: 0x8000f5e5 <- 0xef000b05 +mem-write: 0x8000f5e9 <- 0xe3d74ff0 +mem-write: 0x8000f5ed <- 0x939e051a +mem-write: 0x8000f5f1 <- 0x93010006 +mem-write: 0x8000f5f5 <- 0x83ff0d8d +mem-write: 0x8000f5f9 <- 0x3048127 +mem-write: 0x8000f5fd <- 0x13044126 +mem-write: 0x8000f601 <- 0x93000a8d +mem-write: 0x8000f605 <- 0xe3007008 +mem-write: 0x8000f609 <- 0x93fbb6ca +mem-write: 0x8000f60d <- 0x13001605 +mem-write: 0x8000f611 <- 0xb3008d06 +mem-write: 0x8000f615 <- 0x2301b787 +mem-write: 0x8000f619 <- 0x23009d20 +mem-write: 0x8000f61d <- 0x2301bd22 +mem-write: 0x8000f621 <- 0x2304f124 +mem-write: 0x8000f625 <- 0x1304b122 +mem-write: 0x8000f629 <- 0x63007007 +mem-write: 0x8000f62d <- 0x1332b742 +mem-write: 0x8000f631 <- 0x9300060d +mem-write: 0x8000f635 <- 0xb3001585 +mem-write: 0x8000f639 <- 0x2300fc87 +mem-write: 0x8000f63d <- 0x23008d20 +mem-write: 0x8000f641 <- 0x23019d22 +mem-write: 0x8000f645 <- 0x2304f124 +mem-write: 0x8000f649 <- 0x1304b122 +mem-write: 0x8000f64d <- 0x93007007 +mem-write: 0x8000f651 <- 0xe3008606 +mem-write: 0x8000f655 <- 0x1394b752 +mem-write: 0x8000f659 <- 0x93040106 +mem-write: 0x8000f65d <- 0x13000a05 +mem-write: 0x8000f661 <- 0xef000b05 +mem-write: 0x8000f665 <- 0xe3cf8ff0 +mem-write: 0x8000f669 <- 0x8396051c +mem-write: 0x8000f66d <- 0x93048127 +mem-write: 0x8000f671 <- 0x6f000a86 +mem-write: 0x8000f675 <- 0x13925ff0 +mem-write: 0x8000f679 <- 0x93040106 +mem-write: 0x8000f67d <- 0x13000a05 +mem-write: 0x8000f681 <- 0xef000b05 +mem-write: 0x8000f685 <- 0xe3cd8ff0 +mem-write: 0x8000f689 <- 0x6f940500 +mem-write: 0x8000f68d <- 0x93955ff0 +mem-write: 0x8000f691 <- 0x6f00090d +mem-write: 0x8000f695 <- 0x93be5ff0 +mem-write: 0x8000f699 <- 0x63010006 +mem-write: 0x8000f69d <- 0x130bb6de +mem-write: 0x8000f6a1 <- 0x93000d07 +mem-write: 0x8000f6a5 <- 0x1300700f +mem-write: 0x8000f6a9 <- 0x23000c0d +mem-write: 0x8000f6ad <- 0x1303e122 +mem-write: 0x8000f6b1 <- 0x2300090c +mem-write: 0x8000f6b5 <- 0x1303d124 +mem-write: 0x8000f6b9 <- 0x13000a09 +mem-write: 0x8000f6bd <- 0x9300098a +mem-write: 0x8000f6c1 <- 0x13000409 +mem-write: 0x8000f6c5 <- 0x93000d84 +mem-write: 0x8000f6c9 <- 0x93000c8d +mem-write: 0x8000f6cd <- 0x6f00088c +mem-write: 0x8000f6d1 <- 0x1300c000 +mem-write: 0x8000f6d5 <- 0x63ff0404 +mem-write: 0x8000f6d9 <- 0x930486da +mem-write: 0x8000f6dd <- 0x13010787 +mem-write: 0x8000f6e1 <- 0x23001606 +mem-write: 0x8000f6e5 <- 0x23017720 +mem-write: 0x8000f6e9 <- 0x2300d722 +mem-write: 0x8000f6ed <- 0x2304f124 +mem-write: 0x8000f6f1 <- 0x1304c122 +mem-write: 0x8000f6f5 <- 0xe3008707 +mem-write: 0x8000f6f9 <- 0x13fccfde +mem-write: 0x8000f6fd <- 0x93040106 +mem-write: 0x8000f701 <- 0x13000905 +mem-write: 0x8000f705 <- 0xef000b05 +mem-write: 0x8000f709 <- 0x63c54ff0 +mem-write: 0x8000f70d <- 0x934a0516 +mem-write: 0x8000f711 <- 0x13010006 +mem-write: 0x8000f715 <- 0x83ff0404 +mem-write: 0x8000f719 <- 0x3048127 +mem-write: 0x8000f71d <- 0x13044126 +mem-write: 0x8000f721 <- 0x93000a87 +mem-write: 0x8000f725 <- 0xe300700f +mem-write: 0x8000f729 <- 0x3fa86ca +mem-write: 0x8000f72d <- 0x8302412f +mem-write: 0x8000f731 <- 0x9302812e +mem-write: 0x8000f735 <- 0x93000c88 +mem-write: 0x8000f739 <- 0x93000d8c +mem-write: 0x8000f73d <- 0x1300040d +mem-write: 0x8000f741 <- 0x93000984 +mem-write: 0x8000f745 <- 0x13000a09 +mem-write: 0x8000f749 <- 0x1300090a +mem-write: 0x8000f74d <- 0x13000c09 +mem-write: 0x8000f751 <- 0x13000d0c +mem-write: 0x8000f755 <- 0xb300070d +mem-write: 0x8000f759 <- 0x1301b787 +mem-write: 0x8000f75d <- 0x23001606 +mem-write: 0x8000f761 <- 0x23017d20 +mem-write: 0x8000f765 <- 0x2301bd22 +mem-write: 0x8000f769 <- 0x2304f124 +mem-write: 0x8000f76d <- 0x9304c122 +mem-write: 0x8000f771 <- 0x13007006 +mem-write: 0x8000f775 <- 0x63008d0d +mem-write: 0x8000f779 <- 0x13f6c6d8 +mem-write: 0x8000f77d <- 0x93040106 +mem-write: 0x8000f781 <- 0x13000a05 +mem-write: 0x8000f785 <- 0x23000b05 +mem-write: 0x8000f789 <- 0x23031126 +mem-write: 0x8000f78d <- 0x2303d124 +mem-write: 0x8000f791 <- 0xef03e122 +mem-write: 0x8000f795 <- 0xe3bc8ff0 +mem-write: 0x8000f799 <- 0x83840514 +mem-write: 0x8000f79d <- 0x3048127 +mem-write: 0x8000f7a1 <- 0x83044126 +mem-write: 0x8000f7a5 <- 0x8302c128 +mem-write: 0x8000f7a9 <- 0x302812e +mem-write: 0x8000f7ad <- 0x1302412f +mem-write: 0x8000f7b1 <- 0x6f000a8d +mem-write: 0x8000f7b5 <- 0x13f34ff0 +mem-write: 0x8000f7b9 <- 0x93040106 +mem-write: 0x8000f7bd <- 0x13000a05 +mem-write: 0x8000f7c1 <- 0x23000b05 +mem-write: 0x8000f7c5 <- 0x23031126 +mem-write: 0x8000f7c9 <- 0x2303d124 +mem-write: 0x8000f7cd <- 0xef03e122 +mem-write: 0x8000f7d1 <- 0xe3b8cff0 +mem-write: 0x8000f7d5 <- 0x3800516 +mem-write: 0x8000f7d9 <- 0x83044126 +mem-write: 0x8000f7dd <- 0x83048127 +mem-write: 0x8000f7e1 <- 0x8302c128 +mem-write: 0x8000f7e5 <- 0x302812e +mem-write: 0x8000f7e9 <- 0x9302412f +mem-write: 0x8000f7ed <- 0x93054106 +mem-write: 0x8000f7f1 <- 0x13001605 +mem-write: 0x8000f7f5 <- 0x6f000a8d +VXDRV: upload 1024 bytes to 0x8000f7f9 +mem-write: 0x8000f7f9 <- 0x13f3cff0 +mem-write: 0x8000f7fd <- 0x93040106 +mem-write: 0x8000f801 <- 0x13000a05 +mem-write: 0x8000f805 <- 0x23000b05 +mem-write: 0x8000f809 <- 0x23031124 +mem-write: 0x8000f80d <- 0xef03d122 +mem-write: 0x8000f811 <- 0x63b4cff0 +mem-write: 0x8000f815 <- 0x3fc0516 +mem-write: 0x8000f819 <- 0x83044126 +mem-write: 0x8000f81d <- 0x83048127 +mem-write: 0x8000f821 <- 0x83028128 +mem-write: 0x8000f825 <- 0x9302412e +mem-write: 0x8000f829 <- 0x93054106 +mem-write: 0x8000f82d <- 0x13001605 +mem-write: 0x8000f831 <- 0x6f000a8d +mem-write: 0x8000f835 <- 0x13f38ff0 +mem-write: 0x8000f839 <- 0x3010006 +mem-write: 0x8000f83d <- 0x63044127 +mem-write: 0x8000f841 <- 0x93079650 +mem-write: 0x8000f845 <- 0x1301000d +mem-write: 0x8000f849 <- 0x6f007004 +mem-write: 0x8000f84d <- 0x9300c000 +mem-write: 0x8000f851 <- 0x63ff0c8c +mem-write: 0x8000f855 <- 0x93059dd6 +mem-write: 0x8000f859 <- 0x13010787 +mem-write: 0x8000f85d <- 0x23001707 +mem-write: 0x8000f861 <- 0x230176a0 +mem-write: 0x8000f865 <- 0x2301b6a2 +mem-write: 0x8000f869 <- 0x2304f124 +mem-write: 0x8000f86d <- 0x9304e122 +mem-write: 0x8000f871 <- 0xe3008686 +mem-write: 0x8000f875 <- 0x13fce45e +mem-write: 0x8000f879 <- 0x93040106 +mem-write: 0x8000f87d <- 0x13000a05 +mem-write: 0x8000f881 <- 0xef000b05 +mem-write: 0x8000f885 <- 0x63ad8ff0 +mem-write: 0x8000f889 <- 0x93f4051c +mem-write: 0x8000f88d <- 0x83ff0c8c +mem-write: 0x8000f891 <- 0x3048127 +mem-write: 0x8000f895 <- 0x93044127 +mem-write: 0x8000f899 <- 0xe3000a86 +mem-write: 0x8000f89d <- 0xb3fb9dce +mem-write: 0x8000f8a1 <- 0x13019787 +mem-write: 0x8000f8a5 <- 0x23001707 +mem-write: 0x8000f8a9 <- 0x230176a0 +mem-write: 0x8000f8ad <- 0x230196a2 +mem-write: 0x8000f8b1 <- 0x2304f124 +mem-write: 0x8000f8b5 <- 0x9304e122 +mem-write: 0x8000f8b9 <- 0x63007006 +mem-write: 0x8000f8bd <- 0x13eee6d8 +mem-write: 0x8000f8c1 <- 0x93040106 +mem-write: 0x8000f8c5 <- 0x13000a05 +mem-write: 0x8000f8c9 <- 0xef000b05 +mem-write: 0x8000f8cd <- 0x63a90ff0 +mem-write: 0x8000f8d1 <- 0x83f00518 +mem-write: 0x8000f8d5 <- 0x6f048127 +mem-write: 0x8000f8d9 <- 0xe3ed4ff0 +mem-write: 0x8000f8dd <- 0x1388089a +mem-write: 0x8000f8e1 <- 0x93000d89 +mem-write: 0x8000f8e5 <- 0x93000008 +mem-write: 0x8000f8e9 <- 0x1300000c +mem-write: 0x8000f8ed <- 0x6f0f0104 +mem-write: 0x8000f8f1 <- 0x3895ff0 +mem-write: 0x8000f8f5 <- 0x9300c127 +mem-write: 0x8000f8f9 <- 0x93010977 +mem-write: 0x8000f8fd <- 0x63004706 +mem-write: 0x8000f901 <- 0x93180792 +mem-write: 0x8000f905 <- 0x63040977 +mem-write: 0x8000f909 <- 0x8336078e +mem-write: 0x8000f90d <- 0x1300c127 +mem-write: 0x8000f911 <- 0x2300000c +mem-write: 0x8000f915 <- 0x8300d126 +mem-write: 0x8000f919 <- 0x6f0007dc +mem-write: 0x8000f91d <- 0x38b1ff0 +mem-write: 0x8000f921 <- 0x9300c127 +mem-write: 0x8000f925 <- 0x93010df7 +mem-write: 0x8000f929 <- 0x63004706 +mem-write: 0x8000f92d <- 0x9310079a +mem-write: 0x8000f931 <- 0x63040df7 +mem-write: 0x8000f935 <- 0x83380786 +mem-write: 0x8000f939 <- 0x1300c127 +mem-write: 0x8000f93d <- 0x2300000c +mem-write: 0x8000f941 <- 0x8300d126 +mem-write: 0x8000f945 <- 0x930007dc +mem-write: 0x8000f949 <- 0x6f001006 +mem-write: 0x8000f94d <- 0x13889ff0 +mem-write: 0x8000f951 <- 0x93040106 +mem-write: 0x8000f955 <- 0x13000a05 +mem-write: 0x8000f959 <- 0xef000b05 +mem-write: 0x8000f95d <- 0x63a00ff0 +mem-write: 0x8000f961 <- 0x83e80510 +mem-write: 0x8000f965 <- 0x83044125 +mem-write: 0x8000f969 <- 0x93048127 +mem-write: 0x8000f96d <- 0x93054106 +mem-write: 0x8000f971 <- 0x13001585 +mem-write: 0x8000f975 <- 0x6f000a8d +mem-write: 0x8000f979 <- 0x93e04ff0 +mem-write: 0x8000f97d <- 0x23400df7 +mem-write: 0x8000f981 <- 0x23034124 +mem-write: 0x8000f985 <- 0x13033126 +mem-write: 0x8000f989 <- 0x93000c0a +mem-write: 0x8000f98d <- 0x13000c89 +mem-write: 0x8000f991 <- 0x83000009 +mem-write: 0x8000f995 <- 0x1301812c +mem-write: 0x8000f999 <- 0x230f0104 +mem-write: 0x8000f99d <- 0x13031122 +mem-write: 0x8000f9a1 <- 0x6f00078c +mem-write: 0x8000f9a5 <- 0x13024000 +mem-write: 0x8000f9a9 <- 0x9300a006 +mem-write: 0x8000f9ad <- 0x13000006 +mem-write: 0x8000f9b1 <- 0x93000985 +mem-write: 0x8000f9b5 <- 0xef000a05 +mem-write: 0x8000f9b9 <- 0x63231000 +mem-write: 0x8000f9bd <- 0x93320a06 +mem-write: 0x8000f9c1 <- 0x13000509 +mem-write: 0x8000f9c5 <- 0x1300058a +mem-write: 0x8000f9c9 <- 0x9300a006 +mem-write: 0x8000f9cd <- 0x13000006 +mem-write: 0x8000f9d1 <- 0x93000985 +mem-write: 0x8000f9d5 <- 0xef000a05 +mem-write: 0x8000f9d9 <- 0x13645000 +mem-write: 0x8000f9dd <- 0xa3030505 +mem-write: 0x8000f9e1 <- 0x13fea40f +mem-write: 0x8000f9e5 <- 0x13001909 +mem-write: 0x8000f9e9 <- 0xe3fff404 +mem-write: 0x8000f9ed <- 0x83fa0c0e +mem-write: 0x8000f9f1 <- 0xe3000cc6 +mem-write: 0x8000f9f5 <- 0x93fb269a +mem-write: 0x8000f9f9 <- 0xe30ff007 +mem-write: 0x8000f9fd <- 0x63faf906 +mem-write: 0x8000fa01 <- 0x93160a1c +mem-write: 0x8000fa05 <- 0x63009007 +mem-write: 0x8000fa09 <- 0x931737e8 +mem-write: 0x8000fa0d <- 0x230f0107 +mem-write: 0x8000fa11 <- 0x8301912c +mem-write: 0x8000fa15 <- 0x3024128 +mem-write: 0x8000fa19 <- 0x8302812a +mem-write: 0x8000fa1d <- 0xb302c129 +mem-write: 0x8000fa21 <- 0x1340878c +mem-write: 0x8000fa25 <- 0x6f000d89 +mem-write: 0x8000fa29 <- 0x3f5cff0 +mem-write: 0x8000fa2d <- 0x93008127 +mem-write: 0x8000fa31 <- 0x2341f757 +mem-write: 0x8000fa35 <- 0x2300e6a0 +mem-write: 0x8000fa39 <- 0x6f00f6a2 +mem-write: 0x8000fa3d <- 0x23b80ff0 +mem-write: 0x8000fa41 <- 0x8300d126 +mem-write: 0x8000fa45 <- 0x1300072c +mem-write: 0x8000fa49 <- 0x9300000c +mem-write: 0x8000fa4d <- 0x6f001006 +mem-write: 0x8000fa51 <- 0x83f84ff0 +mem-write: 0x8000fa55 <- 0x83018127 +mem-write: 0x8000fa59 <- 0x630009c6 +mem-write: 0x8000fa5d <- 0x83be0788 +mem-write: 0x8000fa61 <- 0x630007c7 +mem-write: 0x8000fa65 <- 0x13be0784 +mem-write: 0x8000fa69 <- 0x6f400969 +mem-write: 0x8000fa6d <- 0x83be0ff0 +mem-write: 0x8000fa71 <- 0x2300072c +mem-write: 0x8000fa75 <- 0x1300d126 +mem-write: 0x8000fa79 <- 0x9341fcdc +mem-write: 0x8000fa7d <- 0x6f000c06 +mem-write: 0x8000fa81 <- 0x83ec8ff0 +mem-write: 0x8000fa85 <- 0x1300072c +mem-write: 0x8000fa89 <- 0x2300000c +mem-write: 0x8000fa8d <- 0x6f00d126 +mem-write: 0x8000fa91 <- 0xb7f3cff0 +mem-write: 0x8000fa95 <- 0x93800157 +mem-write: 0x8000fa99 <- 0x23a50787 +mem-write: 0x8000fa9d <- 0x9300f12a +mem-write: 0x8000faa1 <- 0x93020977 +mem-write: 0x8000faa5 <- 0x63000408 +mem-write: 0x8000faa9 <- 0x8306078c +mem-write: 0x8000faad <- 0x9300c127 +mem-write: 0x8000fab1 <- 0x93007787 +mem-write: 0x8000fab5 <- 0x83ff87f7 +mem-write: 0x8000fab9 <- 0x30007ac +mem-write: 0x8000fabd <- 0x930047ac +mem-write: 0x8000fac1 <- 0x23008787 +mem-write: 0x8000fac5 <- 0x1300f126 +mem-write: 0x8000fac9 <- 0x63001976 +mem-write: 0x8000facd <- 0x3300060e +mem-write: 0x8000fad1 <- 0x63018ce6 +mem-write: 0x8000fad5 <- 0x1300060a +mem-write: 0x8000fad9 <- 0x23030006 +mem-write: 0x8000fadd <- 0xa302c10e +mem-write: 0x8000fae1 <- 0x1302d10e +mem-write: 0x8000fae5 <- 0x93002969 +mem-write: 0x8000fae9 <- 0x93bff97d +mem-write: 0x8000faed <- 0x6f002006 +mem-write: 0x8000faf1 <- 0x93ee4ff0 +mem-write: 0x8000faf5 <- 0x93000408 +mem-write: 0x8000faf9 <- 0x6f00090d +mem-write: 0x8000fafd <- 0x93ff0ff0 +mem-write: 0x8000fb01 <- 0x6f000408 +mem-write: 0x8000fb05 <- 0xb7ea4ff0 +mem-write: 0x8000fb09 <- 0x93800157 +mem-write: 0x8000fb0d <- 0x23a3c787 +mem-write: 0x8000fb11 <- 0x9300f12a +mem-write: 0x8000fb15 <- 0x93020977 +mem-write: 0x8000fb19 <- 0xe3000408 +mem-write: 0x8000fb1d <- 0x3f80798 +mem-write: 0x8000fb21 <- 0x9300c127 +mem-write: 0x8000fb25 <- 0x13010977 +mem-write: 0x8000fb29 <- 0x63004706 +mem-write: 0x8000fb2d <- 0x8308078a +mem-write: 0x8000fb31 <- 0x1300072c +mem-write: 0x8000fb35 <- 0x2300000c +mem-write: 0x8000fb39 <- 0x6f00c126 +mem-write: 0x8000fb3d <- 0x13f8dff0 +mem-write: 0x8000fb41 <- 0xef000405 +mem-write: 0x8000fb45 <- 0x939a9f90 +mem-write: 0x8000fb49 <- 0x2300050c +mem-write: 0x8000fb4d <- 0x9301b126 +mem-write: 0x8000fb51 <- 0x6f000008 +mem-write: 0x8000fb55 <- 0x93e30ff0 +mem-write: 0x8000fb59 <- 0xef040005 +mem-write: 0x8000fb5d <- 0x23bddf70 +mem-write: 0x8000fb61 <- 0x2300aa20 +mem-write: 0x8000fb65 <- 0x6300aa28 +mem-write: 0x8000fb69 <- 0x9324050c +mem-write: 0x8000fb6d <- 0x23040007 +mem-write: 0x8000fb71 <- 0x6f00fa2a +mem-write: 0x8000fb75 <- 0x83a00ff0 +mem-write: 0x8000fb79 <- 0x83020127 +mem-write: 0x8000fb7d <- 0x1301c125 +mem-write: 0x8000fb81 <- 0x33000009 +mem-write: 0x8000fb85 <- 0x1340f404 +mem-write: 0x8000fb89 <- 0x13000786 +mem-write: 0x8000fb8d <- 0xef000405 +mem-write: 0x8000fb91 <- 0x839e9f90 +mem-write: 0x8000fb95 <- 0x13001cc5 +mem-write: 0x8000fb99 <- 0x9300a006 +mem-write: 0x8000fb9d <- 0x33000006 +mem-write: 0x8000fba1 <- 0x1300b038 +mem-write: 0x8000fba5 <- 0x93000985 +mem-write: 0x8000fba9 <- 0xb3000a05 +mem-write: 0x8000fbad <- 0xef010c8c +mem-write: 0x8000fbb1 <- 0x6f039000 +mem-write: 0x8000fbb5 <- 0x13e0dff0 +mem-write: 0x8000fbb9 <- 0x6f00090a +mem-write: 0x8000fbbd <- 0x93c24ff0 +mem-write: 0x8000fbc1 <- 0x63040977 +mem-write: 0x8000fbc5 <- 0x830a0782 +mem-write: 0x8000fbc9 <- 0x1300c127 +mem-write: 0x8000fbcd <- 0x2300000c +mem-write: 0x8000fbd1 <- 0x8300c126 +mem-write: 0x8000fbd5 <- 0x6f0007dc +mem-write: 0x8000fbd9 <- 0x13ef1ff0 +mem-write: 0x8000fbdd <- 0x93040106 +mem-write: 0x8000fbe1 <- 0x13000a05 +mem-write: 0x8000fbe5 <- 0x23000b05 +mem-write: 0x8000fbe9 <- 0xef031122 +mem-write: 0x8000fbed <- 0x63f71fe0 +mem-write: 0x8000fbf1 <- 0x3be0518 +mem-write: 0x8000fbf5 <- 0x83044126 +VXDRV: upload 1023 bytes to 0x8000fbf9 +mem-write: 0x8000fbf9 <- 0x83048127 +mem-write: 0x8000fbfd <- 0x93024128 +mem-write: 0x8000fc01 <- 0x93054106 +mem-write: 0x8000fc05 <- 0x13001605 +mem-write: 0x8000fc09 <- 0x6f000a8d +mem-write: 0x8000fc0d <- 0x83b68ff0 +mem-write: 0x8000fc11 <- 0x130019c6 +mem-write: 0x8000fc15 <- 0x93200969 +mem-write: 0x8000fc19 <- 0x6f001989 +mem-write: 0x8000fc1d <- 0x83a30ff0 +mem-write: 0x8000fc21 <- 0x130019c6 +mem-write: 0x8000fc25 <- 0x93020969 +mem-write: 0x8000fc29 <- 0x6f001989 +mem-write: 0x8000fc2d <- 0x13a20ff0 +mem-write: 0x8000fc31 <- 0x6f00040a +mem-write: 0x8000fc35 <- 0x83bacff0 +mem-write: 0x8000fc39 <- 0x23008127 +mem-write: 0x8000fc3d <- 0x6f00f6a0 +mem-write: 0x8000fc41 <- 0x9397cff0 +mem-write: 0x8000fc45 <- 0x93006007 +mem-write: 0x8000fc49 <- 0x6300088c +mem-write: 0x8000fc4d <- 0x930117f4 +mem-write: 0x8000fc51 <- 0x3700600c +mem-write: 0x8000fc55 <- 0x1380015e +mem-write: 0x8000fc59 <- 0x23000c8c +mem-write: 0x8000fc5d <- 0x1301b126 +mem-write: 0x8000fc61 <- 0x6fa64e04 +mem-write: 0x8000fc65 <- 0x93a58ff0 +mem-write: 0x8000fc69 <- 0x63200977 +mem-write: 0x8000fc6d <- 0x830c0786 +mem-write: 0x8000fc71 <- 0x1300c127 +mem-write: 0x8000fc75 <- 0x2300000c +mem-write: 0x8000fc79 <- 0x8300c126 +mem-write: 0x8000fc7d <- 0x6f0007cc +mem-write: 0x8000fc81 <- 0x93e49ff0 +mem-write: 0x8000fc85 <- 0x63200977 +mem-write: 0x8000fc89 <- 0x8308078e +mem-write: 0x8000fc8d <- 0x1300c127 +mem-write: 0x8000fc91 <- 0x2300000c +mem-write: 0x8000fc95 <- 0x8300d126 +mem-write: 0x8000fc99 <- 0x6f0007cc +mem-write: 0x8000fc9d <- 0x93d30ff0 +mem-write: 0x8000fca1 <- 0x63200977 +mem-write: 0x8000fca5 <- 0x83060784 +mem-write: 0x8000fca9 <- 0x2300c127 +mem-write: 0x8000fcad <- 0x8300d126 +mem-write: 0x8000fcb1 <- 0x1300078c +mem-write: 0x8000fcb5 <- 0x9341fcdc +mem-write: 0x8000fcb9 <- 0x6f000c06 +mem-write: 0x8000fcbd <- 0x93c8cff0 +mem-write: 0x8000fcc1 <- 0x63200df7 +mem-write: 0x8000fcc5 <- 0x83020788 +mem-write: 0x8000fcc9 <- 0x1300c127 +mem-write: 0x8000fccd <- 0x2300000c +mem-write: 0x8000fcd1 <- 0x8300d126 +mem-write: 0x8000fcd5 <- 0x930007cc +mem-write: 0x8000fcd9 <- 0x6f001006 +mem-write: 0x8000fcdd <- 0x13cf8ff0 +mem-write: 0x8000fce1 <- 0x6f000686 +mem-write: 0x8000fce5 <- 0x93931ff0 +mem-write: 0x8000fce9 <- 0xe3009007 +mem-write: 0x8000fced <- 0x6fcd37ea +mem-write: 0x8000fcf1 <- 0x83d1dff0 +mem-write: 0x8000fcf5 <- 0x1300c127 +mem-write: 0x8000fcf9 <- 0x2300000c +mem-write: 0x8000fcfd <- 0x8300d126 +mem-write: 0x8000fd01 <- 0x930007ac +mem-write: 0x8000fd05 <- 0x6f001006 +mem-write: 0x8000fd09 <- 0x83cccff0 +mem-write: 0x8000fd0d <- 0x2300c127 +mem-write: 0x8000fd11 <- 0x8300d126 +mem-write: 0x8000fd15 <- 0x130007ac +mem-write: 0x8000fd19 <- 0x9341fcdc +mem-write: 0x8000fd1d <- 0x6f000c06 +mem-write: 0x8000fd21 <- 0x83c28ff0 +mem-write: 0x8000fd25 <- 0x1300c127 +mem-write: 0x8000fd29 <- 0x2300000c +mem-write: 0x8000fd2d <- 0x8300d126 +mem-write: 0x8000fd31 <- 0x6f0007ac +mem-write: 0x8000fd35 <- 0x83c98ff0 +mem-write: 0x8000fd39 <- 0x1300c127 +mem-write: 0x8000fd3d <- 0x2300000c +mem-write: 0x8000fd41 <- 0x8300c126 +mem-write: 0x8000fd45 <- 0x6f0007ac +mem-write: 0x8000fd49 <- 0x83d81ff0 +mem-write: 0x8000fd4d <- 0x23008127 +mem-write: 0x8000fd51 <- 0x6f00f690 +mem-write: 0x8000fd55 <- 0x13868ff0 +mem-write: 0x8000fd59 <- 0x93040106 +mem-write: 0x8000fd5d <- 0x13000a05 +mem-write: 0x8000fd61 <- 0xef000b05 +mem-write: 0x8000fd65 <- 0x6fdf9fe0 +mem-write: 0x8000fd69 <- 0x93a78ff0 +mem-write: 0x8000fd6d <- 0x2300088c +mem-write: 0x8000fd71 <- 0x9301b126 +mem-write: 0x8000fd75 <- 0x6f000008 +mem-write: 0x8000fd79 <- 0x93c0cff0 +mem-write: 0x8000fd7d <- 0x6f00090d +mem-write: 0x8000fd81 <- 0x13bf0ff0 +mem-write: 0x8000fd85 <- 0x13000685 +mem-write: 0x8000fd89 <- 0x6f000586 +mem-write: 0x8000fd8d <- 0x93fe4ff0 +mem-write: 0x8000fd91 <- 0x23fff007 +mem-write: 0x8000fd95 <- 0x6f00f124 +mem-write: 0x8000fd99 <- 0x83a54ff0 +mem-write: 0x8000fd9d <- 0x300c127 +mem-write: 0x8000fda1 <- 0x930007a4 +mem-write: 0x8000fda5 <- 0x63004787 +mem-write: 0x8000fda9 <- 0x13000454 +mem-write: 0x8000fdad <- 0x83fff004 +mem-write: 0x8000fdb1 <- 0x230019c6 +mem-write: 0x8000fdb5 <- 0x9300f126 +mem-write: 0x8000fdb9 <- 0x6f000709 +mem-write: 0x8000fdbd <- 0x93890ff0 +mem-write: 0x8000fdc1 <- 0x2300c007 +mem-write: 0x8000fdc5 <- 0x9300fb20 +mem-write: 0x8000fdc9 <- 0x23fff007 +mem-write: 0x8000fdcd <- 0x6f00f124 +mem-write: 0x8000fdd1 <- 0x13a1cff0 +mem-write: 0x8000fdd5 <- 0x23fe0101 +mem-write: 0x8000fdd9 <- 0x2300812c +mem-write: 0x8000fddd <- 0x2300912a +mem-write: 0x8000fde1 <- 0x23012128 +mem-write: 0x8000fde5 <- 0x2300112e +mem-write: 0x8000fde9 <- 0x13013126 +mem-write: 0x8000fded <- 0x93000509 +mem-write: 0x8000fdf1 <- 0x13000584 +mem-write: 0x8000fdf5 <- 0x63000604 +mem-write: 0x8000fdf9 <- 0x83000506 +mem-write: 0x8000fdfd <- 0x63038527 +mem-write: 0x8000fe01 <- 0x3140788 +mem-write: 0x8000fe05 <- 0x8300c417 +mem-write: 0x8000fe09 <- 0x93018426 +mem-write: 0x8000fe0d <- 0x23008777 +mem-write: 0x8000fe11 <- 0x9300d424 +mem-write: 0x8000fe15 <- 0x93010716 +mem-write: 0x8000fe19 <- 0x630106d6 +mem-write: 0x8000fe1d <- 0x83080782 +mem-write: 0x8000fe21 <- 0x63010427 +mem-write: 0x8000fe25 <- 0x1306078e +mem-write: 0x8000fe29 <- 0x93012696 +mem-write: 0x8000fe2d <- 0x930ff4f9 +mem-write: 0x8000fe31 <- 0x630ff4f4 +mem-write: 0x8000fe35 <- 0x308065e +mem-write: 0x8000fe39 <- 0x83000427 +mem-write: 0x8000fe3d <- 0xb3014426 +mem-write: 0x8000fe41 <- 0x6340f707 +mem-write: 0x8000fe45 <- 0x830ad7de +mem-write: 0x8000fe49 <- 0x13008426 +mem-write: 0x8000fe4d <- 0x23001706 +mem-write: 0x8000fe51 <- 0x9300c420 +mem-write: 0x8000fe55 <- 0x23fff686 +mem-write: 0x8000fe59 <- 0x2300d424 +mem-write: 0x8000fe5d <- 0x3013700 +mem-write: 0x8000fe61 <- 0x93014427 +mem-write: 0x8000fe65 <- 0x63001787 +mem-write: 0x8000fe69 <- 0x830cf708 +mem-write: 0x8000fe6d <- 0x9300c457 +mem-write: 0x8000fe71 <- 0x630017f7 +mem-write: 0x8000fe75 <- 0x93000786 +mem-write: 0x8000fe79 <- 0x6300a007 +mem-write: 0x8000fe7d <- 0x830af48e +mem-write: 0x8000fe81 <- 0x301c120 +mem-write: 0x8000fe85 <- 0x3018124 +mem-write: 0x8000fe89 <- 0x83010129 +mem-write: 0x8000fe8d <- 0x1300c129 +mem-write: 0x8000fe91 <- 0x83000485 +mem-write: 0x8000fe95 <- 0x13014124 +mem-write: 0x8000fe99 <- 0x67020101 +mem-write: 0x8000fe9d <- 0x93000080 +mem-write: 0x8000fea1 <- 0x13000405 +mem-write: 0x8000fea5 <- 0xef000905 +mem-write: 0x8000fea9 <- 0x63c41f30 +mem-write: 0x8000fead <- 0x308051e +mem-write: 0x8000feb1 <- 0x9300c417 +mem-write: 0x8000feb5 <- 0x830ff4f9 +mem-write: 0x8000feb9 <- 0x93010427 +mem-write: 0x8000febd <- 0x93010716 +mem-write: 0x8000fec1 <- 0x130106d6 +mem-write: 0x8000fec5 <- 0x93012696 +mem-write: 0x8000fec9 <- 0xe30ff4f4 +mem-write: 0x8000fecd <- 0x83f60646 +mem-write: 0x8000fed1 <- 0x37064426 +mem-write: 0x8000fed5 <- 0x33000026 +mem-write: 0x8000fed9 <- 0x3700c767 +mem-write: 0x8000fedd <- 0x13ffffe6 +mem-write: 0x8000fee1 <- 0xb3fff606 +mem-write: 0x8000fee5 <- 0x2300c6f6 +mem-write: 0x8000fee9 <- 0x300e416 +mem-write: 0x8000feed <- 0x23000427 +mem-write: 0x8000fef1 <- 0x8306d422 +mem-write: 0x8000fef5 <- 0xb3014426 +mem-write: 0x8000fef9 <- 0xe340f707 +mem-write: 0x8000fefd <- 0x93f4d7c6 +mem-write: 0x8000ff01 <- 0x13000405 +mem-write: 0x8000ff05 <- 0xef000905 +mem-write: 0x8000ff09 <- 0x63950f40 +mem-write: 0x8000ff0d <- 0x302051e +mem-write: 0x8000ff11 <- 0x83000427 +mem-write: 0x8000ff15 <- 0x93008426 +mem-write: 0x8000ff19 <- 0x13001007 +mem-write: 0x8000ff1d <- 0x93001706 +mem-write: 0x8000ff21 <- 0x23fff686 +mem-write: 0x8000ff25 <- 0x2300c420 +mem-write: 0x8000ff29 <- 0x2300d424 +mem-write: 0x8000ff2d <- 0x3013700 +mem-write: 0x8000ff31 <- 0xe3014427 +mem-write: 0x8000ff35 <- 0x93f2f71c +mem-write: 0x8000ff39 <- 0x13000405 +mem-write: 0x8000ff3d <- 0xef000905 +mem-write: 0x8000ff41 <- 0xe3918f40 +mem-write: 0x8000ff45 <- 0x93f2050e +mem-write: 0x8000ff49 <- 0x6ffff004 +mem-write: 0x8000ff4d <- 0xeff35ff0 +mem-write: 0x8000ff51 <- 0x6fca4f40 +mem-write: 0x8000ff55 <- 0x93eb1ff0 +mem-write: 0x8000ff59 <- 0x3000507 +mem-write: 0x8000ff5d <- 0x131d81a5 +mem-write: 0x8000ff61 <- 0x93000586 +mem-write: 0x8000ff65 <- 0x6f000785 +mem-write: 0x8000ff69 <- 0x13e6dff0 +mem-write: 0x8000ff6d <- 0x23fe0101 +mem-write: 0x8000ff71 <- 0x2300812c +mem-write: 0x8000ff75 <- 0x2300912a +mem-write: 0x8000ff79 <- 0x8300112e +mem-write: 0x8000ff7d <- 0x131181a7 +mem-write: 0x8000ff81 <- 0x93000504 +mem-write: 0x8000ff85 <- 0x63000684 +mem-write: 0x8000ff89 <- 0xe7020582 +mem-write: 0x8000ff8d <- 0x93000780 +mem-write: 0x8000ff91 <- 0x63fff007 +mem-write: 0x8000ff95 <- 0x8302f506 +mem-write: 0x8000ff99 <- 0x301c120 +mem-write: 0x8000ff9d <- 0x83018124 +mem-write: 0x8000ffa1 <- 0x13014124 +mem-write: 0x8000ffa5 <- 0x67020101 +mem-write: 0x8000ffa9 <- 0x13000080 +mem-write: 0x8000ffad <- 0x93000006 +mem-write: 0x8000ffb1 <- 0xe7004105 +mem-write: 0x8000ffb5 <- 0x93000780 +mem-write: 0x8000ffb9 <- 0xe3fff007 +mem-write: 0x8000ffbd <- 0x23fcf51e +mem-write: 0x8000ffc1 <- 0x930004a0 +mem-write: 0x8000ffc5 <- 0x8308a007 +mem-write: 0x8000ffc9 <- 0x2301c120 +mem-write: 0x8000ffcd <- 0x300f420 +mem-write: 0x8000ffd1 <- 0x83018124 +mem-write: 0x8000ffd5 <- 0x13014124 +mem-write: 0x8000ffd9 <- 0x67020101 +mem-write: 0x8000ffdd <- 0x13000080 +mem-write: 0x8000ffe1 <- 0x23fe0101 +mem-write: 0x8000ffe5 <- 0x2300812c +mem-write: 0x8000ffe9 <- 0x2300912a +mem-write: 0x8000ffed <- 0x8300112e +mem-write: 0x8000fff1 <- 0x831d81a4 +mem-write: 0x8000fff5 <- 0x831181a7 +VXDRV: upload 1024 bytes to 0x8000fff8 +mem-write: 0x8000fff8 <- 0x60413 +mem-write: 0x8000fffc <- 0x2050a63 +mem-write: 0x80010000 <- 0x58613 +mem-write: 0x80010004 <- 0x40693 +mem-write: 0x80010008 <- 0x50593 +mem-write: 0x8001000c <- 0x48513 +mem-write: 0x80010010 <- 0x780e7 +mem-write: 0x80010014 <- 0xfff00793 +mem-write: 0x80010018 <- 0x2f50a63 +mem-write: 0x8001001c <- 0x1c12083 +mem-write: 0x80010020 <- 0x1812403 +mem-write: 0x80010024 <- 0x1412483 +mem-write: 0x80010028 <- 0x2010113 +mem-write: 0x8001002c <- 0x8067 +mem-write: 0x80010030 <- 0x60693 +mem-write: 0x80010034 <- 0x410593 +mem-write: 0x80010038 <- 0x613 +mem-write: 0x8001003c <- 0x48513 +mem-write: 0x80010040 <- 0x780e7 +mem-write: 0x80010044 <- 0xfff00793 +mem-write: 0x80010048 <- 0xfcf51ae3 +mem-write: 0x8001004c <- 0x42023 +mem-write: 0x80010050 <- 0x1c12083 +mem-write: 0x80010054 <- 0x1812403 +mem-write: 0x80010058 <- 0x8a00793 +mem-write: 0x8001005c <- 0xf4a023 +mem-write: 0x80010060 <- 0x1412483 +mem-write: 0x80010064 <- 0x2010113 +mem-write: 0x80010068 <- 0x8067 +mem-write: 0x8001006c <- 0x1181a303 +mem-write: 0x80010070 <- 0x30067 +mem-write: 0x80010074 <- 0x2058463 +mem-write: 0x80010078 <- 0xff00793 +mem-write: 0x8001007c <- 0xc7e863 +mem-write: 0x80010080 <- 0xc58023 +mem-write: 0x80010084 <- 0x100513 +mem-write: 0x80010088 <- 0x8067 +mem-write: 0x8001008c <- 0x8a00793 +mem-write: 0x80010090 <- 0xf52023 +mem-write: 0x80010094 <- 0xfff00513 +mem-write: 0x80010098 <- 0x8067 +mem-write: 0x8001009c <- 0x513 +mem-write: 0x800100a0 <- 0x8067 +mem-write: 0x800100a4 <- 0xff010113 +mem-write: 0x800100a8 <- 0x600513 +mem-write: 0x800100ac <- 0x112623 +mem-write: 0x800100b0 <- 0x28c000ef +mem-write: 0x800100b4 <- 0x100513 +mem-write: 0x800100b8 <- 0xd78f00ef +mem-write: 0x800100bc <- 0xff010113 +mem-write: 0x800100c0 <- 0x8000593 +mem-write: 0x800100c4 <- 0x812423 +mem-write: 0x800100c8 <- 0x112623 +mem-write: 0x800100cc <- 0x50413 +mem-write: 0x800100d0 <- 0xe68f70ef +mem-write: 0x800100d4 <- 0x2ca42e23 +mem-write: 0x800100d8 <- 0x2050463 +mem-write: 0x800100dc <- 0x8050793 +mem-write: 0x800100e0 <- 0x52023 +mem-write: 0x800100e4 <- 0x450513 +mem-write: 0x800100e8 <- 0xfef51ce3 +mem-write: 0x800100ec <- 0x513 +mem-write: 0x800100f0 <- 0xc12083 +mem-write: 0x800100f4 <- 0x812403 +mem-write: 0x800100f8 <- 0x1010113 +mem-write: 0x800100fc <- 0x8067 +mem-write: 0x80010100 <- 0xfff00513 +mem-write: 0x80010104 <- 0xfedff06f +mem-write: 0x80010108 <- 0x2dc52783 +mem-write: 0x8001010c <- 0x78663 +mem-write: 0x80010110 <- 0x513 +mem-write: 0x80010114 <- 0x8067 +mem-write: 0x80010118 <- 0xfa5ff06f +mem-write: 0x8001011c <- 0xfe010113 +mem-write: 0x80010120 <- 0x912a23 +mem-write: 0x80010124 <- 0x112e23 +mem-write: 0x80010128 <- 0x812c23 +mem-write: 0x8001012c <- 0x1f00793 +mem-write: 0x80010130 <- 0x50493 +mem-write: 0x80010134 <- 0x2b7ea63 +mem-write: 0x80010138 <- 0x58413 +mem-write: 0x8001013c <- 0x2dc52583 +mem-write: 0x80010140 <- 0x4058463 +mem-write: 0x80010144 <- 0x241413 +mem-write: 0x80010148 <- 0x858433 +mem-write: 0x8001014c <- 0x42503 +mem-write: 0x80010150 <- 0xc42023 +mem-write: 0x80010154 <- 0x1c12083 +mem-write: 0x80010158 <- 0x1812403 +mem-write: 0x8001015c <- 0x1412483 +mem-write: 0x80010160 <- 0x2010113 +mem-write: 0x80010164 <- 0x8067 +mem-write: 0x80010168 <- 0x1c12083 +mem-write: 0x8001016c <- 0x1812403 +mem-write: 0x80010170 <- 0x1600793 +mem-write: 0x80010174 <- 0xf52023 +mem-write: 0x80010178 <- 0x1412483 +mem-write: 0x8001017c <- 0xfff00513 +mem-write: 0x80010180 <- 0x2010113 +mem-write: 0x80010184 <- 0x8067 +mem-write: 0x80010188 <- 0xc12623 +mem-write: 0x8001018c <- 0xf31ff0ef +mem-write: 0x80010190 <- 0x50793 +mem-write: 0x80010194 <- 0xfff00513 +mem-write: 0x80010198 <- 0xfa079ee3 +mem-write: 0x8001019c <- 0x2dc4a583 +mem-write: 0x800101a0 <- 0xc12603 +mem-write: 0x800101a4 <- 0xfa1ff06f +mem-write: 0x800101a8 <- 0xff010113 +mem-write: 0x800101ac <- 0x912223 +mem-write: 0x800101b0 <- 0x112623 +mem-write: 0x800101b4 <- 0x812423 +mem-write: 0x800101b8 <- 0x1f00793 +mem-write: 0x800101bc <- 0x50493 +mem-write: 0x800101c0 <- 0xab7ea63 +mem-write: 0x800101c4 <- 0x2dc52783 +mem-write: 0x800101c8 <- 0x58413 +mem-write: 0x800101cc <- 0x4078463 +mem-write: 0x800101d0 <- 0x259713 +mem-write: 0x800101d4 <- 0xe787b3 +mem-write: 0x800101d8 <- 0x7a703 +mem-write: 0x800101dc <- 0x2070c63 +mem-write: 0x800101e0 <- 0x100693 +mem-write: 0x800101e4 <- 0x6d70c63 +mem-write: 0x800101e8 <- 0xfff00693 +mem-write: 0x800101ec <- 0x4d70863 +mem-write: 0x800101f0 <- 0x58513 +mem-write: 0x800101f4 <- 0x7a023 +mem-write: 0x800101f8 <- 0x700e7 +mem-write: 0x800101fc <- 0x513 +mem-write: 0x80010200 <- 0xc12083 +mem-write: 0x80010204 <- 0x812403 +mem-write: 0x80010208 <- 0x412483 +mem-write: 0x8001020c <- 0x1010113 +mem-write: 0x80010210 <- 0x8067 +mem-write: 0x80010214 <- 0x48513 +mem-write: 0x80010218 <- 0x1cc000ef +mem-write: 0x8001021c <- 0x40613 +mem-write: 0x80010220 <- 0x812403 +mem-write: 0x80010224 <- 0xc12083 +mem-write: 0x80010228 <- 0x50593 +mem-write: 0x8001022c <- 0x48513 +mem-write: 0x80010230 <- 0x412483 +mem-write: 0x80010234 <- 0x1010113 +mem-write: 0x80010238 <- 0x1480006f +mem-write: 0x8001023c <- 0xc12083 +mem-write: 0x80010240 <- 0x812403 +mem-write: 0x80010244 <- 0x1600793 +mem-write: 0x80010248 <- 0xf52023 +mem-write: 0x8001024c <- 0x412483 +mem-write: 0x80010250 <- 0x100513 +mem-write: 0x80010254 <- 0x1010113 +mem-write: 0x80010258 <- 0x8067 +mem-write: 0x8001025c <- 0xc12083 +mem-write: 0x80010260 <- 0x812403 +mem-write: 0x80010264 <- 0x412483 +mem-write: 0x80010268 <- 0x513 +mem-write: 0x8001026c <- 0x1010113 +mem-write: 0x80010270 <- 0x8067 +mem-write: 0x80010274 <- 0x1600793 +mem-write: 0x80010278 <- 0xf52023 +mem-write: 0x8001027c <- 0xfff00513 +mem-write: 0x80010280 <- 0xf81ff06f +mem-write: 0x80010284 <- 0x1f00793 +mem-write: 0x80010288 <- 0xab7e663 +mem-write: 0x8001028c <- 0x2dc52783 +mem-write: 0x80010290 <- 0xfe010113 +mem-write: 0x80010294 <- 0x912c23 +mem-write: 0x80010298 <- 0x112e23 +mem-write: 0x8001029c <- 0x50493 +mem-write: 0x800102a0 <- 0x4078c63 +mem-write: 0x800102a4 <- 0x259713 +mem-write: 0x800102a8 <- 0xe787b3 +mem-write: 0x800102ac <- 0x7a703 +mem-write: 0x800102b0 <- 0x2070a63 +mem-write: 0x800102b4 <- 0xfff00693 +mem-write: 0x800102b8 <- 0x6d70663 +mem-write: 0x800102bc <- 0x100693 +mem-write: 0x800102c0 <- 0x4d70863 +mem-write: 0x800102c4 <- 0x58513 +mem-write: 0x800102c8 <- 0x7a023 +mem-write: 0x800102cc <- 0x700e7 +mem-write: 0x800102d0 <- 0x513 +mem-write: 0x800102d4 <- 0x1c12083 +mem-write: 0x800102d8 <- 0x1812483 +mem-write: 0x800102dc <- 0x2010113 +mem-write: 0x800102e0 <- 0x8067 +mem-write: 0x800102e4 <- 0x1c12083 +mem-write: 0x800102e8 <- 0x1812483 +mem-write: 0x800102ec <- 0x100513 +mem-write: 0x800102f0 <- 0x2010113 +mem-write: 0x800102f4 <- 0x8067 +mem-write: 0x800102f8 <- 0xb12623 +mem-write: 0x800102fc <- 0xdc1ff0ef +mem-write: 0x80010300 <- 0x2051663 +mem-write: 0x80010304 <- 0x2dc4a783 +mem-write: 0x80010308 <- 0xc12583 +mem-write: 0x8001030c <- 0xf99ff06f +mem-write: 0x80010310 <- 0x1c12083 +mem-write: 0x80010314 <- 0x1812483 +mem-write: 0x80010318 <- 0x300513 +mem-write: 0x8001031c <- 0x2010113 +mem-write: 0x80010320 <- 0x8067 +mem-write: 0x80010324 <- 0x200513 +mem-write: 0x80010328 <- 0xfadff06f +mem-write: 0x8001032c <- 0xfff00513 +mem-write: 0x80010330 <- 0xfa5ff06f +mem-write: 0x80010334 <- 0xfff00513 +mem-write: 0x80010338 <- 0x8067 +mem-write: 0x8001033c <- 0x50593 +mem-write: 0x80010340 <- 0x1d81a503 +mem-write: 0x80010344 <- 0xe65ff06f +mem-write: 0x80010348 <- 0x50793 +mem-write: 0x8001034c <- 0x1d81a503 +mem-write: 0x80010350 <- 0x58613 +mem-write: 0x80010354 <- 0x78593 +mem-write: 0x80010358 <- 0xdc5ff06f +mem-write: 0x8001035c <- 0x1d81a503 +mem-write: 0x80010360 <- 0x2dc52783 +mem-write: 0x80010364 <- 0x78663 +mem-write: 0x80010368 <- 0x513 +mem-write: 0x8001036c <- 0x8067 +mem-write: 0x80010370 <- 0xd4dff06f +mem-write: 0x80010374 <- 0x50593 +mem-write: 0x80010378 <- 0x1d81a503 +mem-write: 0x8001037c <- 0xf09ff06f +mem-write: 0x80010380 <- 0xff010113 +mem-write: 0x80010384 <- 0x58713 +mem-write: 0x80010388 <- 0x812423 +mem-write: 0x8001038c <- 0x912223 +mem-write: 0x80010390 <- 0x50413 +mem-write: 0x80010394 <- 0x60593 +mem-write: 0x80010398 <- 0x70513 +mem-write: 0x8001039c <- 0x112623 +mem-write: 0x800103a0 <- 0x2401a423 +mem-write: 0x800103a4 <- 0xba0f00ef +mem-write: 0x800103a8 <- 0xfff00793 +mem-write: 0x800103ac <- 0xf50c63 +mem-write: 0x800103b0 <- 0xc12083 +mem-write: 0x800103b4 <- 0x812403 +mem-write: 0x800103b8 <- 0x412483 +mem-write: 0x800103bc <- 0x1010113 +mem-write: 0x800103c0 <- 0x8067 +mem-write: 0x800103c4 <- 0x2481a783 +mem-write: 0x800103c8 <- 0xfe0784e3 +mem-write: 0x800103cc <- 0xc12083 +mem-write: 0x800103d0 <- 0xf42023 +mem-write: 0x800103d4 <- 0x812403 +mem-write: 0x800103d8 <- 0x412483 +mem-write: 0x800103dc <- 0x1010113 +mem-write: 0x800103e0 <- 0x8067 +mem-write: 0x800103e4 <- 0xb68f006f +mem-write: 0x800103e8 <- 0x50893 +mem-write: 0x800103ec <- 0x58793 +mem-write: 0x800103f0 <- 0x60813 +mem-write: 0x800103f4 <- 0x68513 +VXDRV: upload 1024 bytes to 0x800103f8 +mem-write: 0x800103f8 <- 0x88313 +mem-write: 0x800103fc <- 0x28069463 +mem-write: 0x80010400 <- 0x800156b7 +mem-write: 0x80010404 <- 0x6b468693 +mem-write: 0x80010408 <- 0xec5f663 +mem-write: 0x8001040c <- 0x10737 +mem-write: 0x80010410 <- 0xce67863 +mem-write: 0x80010414 <- 0xff00713 +mem-write: 0x80010418 <- 0xc73733 +mem-write: 0x8001041c <- 0x371713 +mem-write: 0x80010420 <- 0xe65533 +mem-write: 0x80010424 <- 0xa686b3 +mem-write: 0x80010428 <- 0x6c683 +mem-write: 0x8001042c <- 0x2000513 +mem-write: 0x80010430 <- 0xe68733 +mem-write: 0x80010434 <- 0x40e506b3 +mem-write: 0x80010438 <- 0xe50c63 +mem-write: 0x8001043c <- 0xd797b3 +mem-write: 0x80010440 <- 0xe8d733 +mem-write: 0x80010444 <- 0xd61833 +mem-write: 0x80010448 <- 0xf765b3 +mem-write: 0x8001044c <- 0xd89333 +mem-write: 0x80010450 <- 0x1085893 +mem-write: 0x80010454 <- 0x315d7b3 +mem-write: 0x80010458 <- 0x1081613 +mem-write: 0x8001045c <- 0x1065613 +mem-write: 0x80010460 <- 0x1035713 +mem-write: 0x80010464 <- 0x315f6b3 +mem-write: 0x80010468 <- 0x78513 +mem-write: 0x8001046c <- 0x2f605b3 +mem-write: 0x80010470 <- 0x1069693 +mem-write: 0x80010474 <- 0xe6e733 +mem-write: 0x80010478 <- 0xb77e63 +mem-write: 0x8001047c <- 0x1070733 +mem-write: 0x80010480 <- 0xfff78513 +mem-write: 0x80010484 <- 0x1076863 +mem-write: 0x80010488 <- 0xb77663 +mem-write: 0x8001048c <- 0xffe78513 +mem-write: 0x80010490 <- 0x1070733 +mem-write: 0x80010494 <- 0x40b70733 +mem-write: 0x80010498 <- 0x31777b3 +mem-write: 0x8001049c <- 0x1031313 +mem-write: 0x800104a0 <- 0x1035313 +mem-write: 0x800104a4 <- 0x3175733 +mem-write: 0x800104a8 <- 0x1079793 +mem-write: 0x800104ac <- 0x67e333 +mem-write: 0x800104b0 <- 0x2e606b3 +mem-write: 0x800104b4 <- 0x70613 +mem-write: 0x800104b8 <- 0xd37c63 +mem-write: 0x800104bc <- 0x680333 +mem-write: 0x800104c0 <- 0xfff70613 +mem-write: 0x800104c4 <- 0x1036663 +mem-write: 0x800104c8 <- 0xd37463 +mem-write: 0x800104cc <- 0xffe70613 +mem-write: 0x800104d0 <- 0x1051513 +mem-write: 0x800104d4 <- 0xc56533 +mem-write: 0x800104d8 <- 0x593 +mem-write: 0x800104dc <- 0xe40006f +mem-write: 0x800104e0 <- 0x1000537 +mem-write: 0x800104e4 <- 0x1000713 +mem-write: 0x800104e8 <- 0xf2a66ce3 +mem-write: 0x800104ec <- 0x1800713 +mem-write: 0x800104f0 <- 0xf31ff06f +mem-write: 0x800104f4 <- 0x61663 +mem-write: 0x800104f8 <- 0x100713 +mem-write: 0x800104fc <- 0x2c75833 +mem-write: 0x80010500 <- 0x10737 +mem-write: 0x80010504 <- 0xce87063 +mem-write: 0x80010508 <- 0xff00713 +mem-write: 0x8001050c <- 0x1077463 +mem-write: 0x80010510 <- 0x800513 +mem-write: 0x80010514 <- 0xa85733 +mem-write: 0x80010518 <- 0xe686b3 +mem-write: 0x8001051c <- 0x6c703 +mem-write: 0x80010520 <- 0x2000613 +mem-write: 0x80010524 <- 0xa70733 +mem-write: 0x80010528 <- 0x40e606b3 +mem-write: 0x8001052c <- 0xae61663 +mem-write: 0x80010530 <- 0x410787b3 +mem-write: 0x80010534 <- 0x100593 +mem-write: 0x80010538 <- 0x1085893 +mem-write: 0x8001053c <- 0x1081613 +mem-write: 0x80010540 <- 0x1065613 +mem-write: 0x80010544 <- 0x1035713 +mem-write: 0x80010548 <- 0x317f6b3 +mem-write: 0x8001054c <- 0x317d7b3 +mem-write: 0x80010550 <- 0x1069693 +mem-write: 0x80010554 <- 0xe6e733 +mem-write: 0x80010558 <- 0x2f60e33 +mem-write: 0x8001055c <- 0x78513 +mem-write: 0x80010560 <- 0x1c77e63 +mem-write: 0x80010564 <- 0x1070733 +mem-write: 0x80010568 <- 0xfff78513 +mem-write: 0x8001056c <- 0x1076863 +mem-write: 0x80010570 <- 0x1c77663 +mem-write: 0x80010574 <- 0xffe78513 +mem-write: 0x80010578 <- 0x1070733 +mem-write: 0x8001057c <- 0x41c70733 +mem-write: 0x80010580 <- 0x31777b3 +mem-write: 0x80010584 <- 0x1031313 +mem-write: 0x80010588 <- 0x1035313 +mem-write: 0x8001058c <- 0x3175733 +mem-write: 0x80010590 <- 0x1079793 +mem-write: 0x80010594 <- 0x67e333 +mem-write: 0x80010598 <- 0x2e606b3 +mem-write: 0x8001059c <- 0x70613 +mem-write: 0x800105a0 <- 0xd37c63 +mem-write: 0x800105a4 <- 0x680333 +mem-write: 0x800105a8 <- 0xfff70613 +mem-write: 0x800105ac <- 0x1036663 +mem-write: 0x800105b0 <- 0xd37463 +mem-write: 0x800105b4 <- 0xffe70613 +mem-write: 0x800105b8 <- 0x1051513 +mem-write: 0x800105bc <- 0xc56533 +mem-write: 0x800105c0 <- 0x8067 +mem-write: 0x800105c4 <- 0x1000737 +mem-write: 0x800105c8 <- 0x1000513 +mem-write: 0x800105cc <- 0xf4e864e3 +mem-write: 0x800105d0 <- 0x1800513 +mem-write: 0x800105d4 <- 0xf41ff06f +mem-write: 0x800105d8 <- 0xd81833 +mem-write: 0x800105dc <- 0xe7d5b3 +mem-write: 0x800105e0 <- 0xd89333 +mem-write: 0x800105e4 <- 0xd797b3 +mem-write: 0x800105e8 <- 0xe8d733 +mem-write: 0x800105ec <- 0x1085893 +mem-write: 0x800105f0 <- 0xf76633 +mem-write: 0x800105f4 <- 0x315f733 +mem-write: 0x800105f8 <- 0x1081793 +mem-write: 0x800105fc <- 0x107d793 +mem-write: 0x80010600 <- 0x1065513 +mem-write: 0x80010604 <- 0x315d5b3 +mem-write: 0x80010608 <- 0x1071713 +mem-write: 0x8001060c <- 0xa76733 +mem-write: 0x80010610 <- 0x2b786b3 +mem-write: 0x80010614 <- 0x58513 +mem-write: 0x80010618 <- 0xd77e63 +mem-write: 0x8001061c <- 0x1070733 +mem-write: 0x80010620 <- 0xfff58513 +mem-write: 0x80010624 <- 0x1076863 +mem-write: 0x80010628 <- 0xd77663 +mem-write: 0x8001062c <- 0xffe58513 +mem-write: 0x80010630 <- 0x1070733 +mem-write: 0x80010634 <- 0x40d706b3 +mem-write: 0x80010638 <- 0x316f733 +mem-write: 0x8001063c <- 0x1061613 +mem-write: 0x80010640 <- 0x1065613 +mem-write: 0x80010644 <- 0x316d6b3 +mem-write: 0x80010648 <- 0x1071713 +mem-write: 0x8001064c <- 0x2d788b3 +mem-write: 0x80010650 <- 0xc767b3 +mem-write: 0x80010654 <- 0x68713 +mem-write: 0x80010658 <- 0x117fe63 +mem-write: 0x8001065c <- 0x10787b3 +mem-write: 0x80010660 <- 0xfff68713 +mem-write: 0x80010664 <- 0x107e863 +mem-write: 0x80010668 <- 0x117f663 +mem-write: 0x8001066c <- 0xffe68713 +mem-write: 0x80010670 <- 0x10787b3 +mem-write: 0x80010674 <- 0x1051593 +mem-write: 0x80010678 <- 0x411787b3 +mem-write: 0x8001067c <- 0xe5e5b3 +mem-write: 0x80010680 <- 0xeb9ff06f +mem-write: 0x80010684 <- 0x18d5e663 +mem-write: 0x80010688 <- 0x10737 +mem-write: 0x8001068c <- 0x4e6f463 +mem-write: 0x80010690 <- 0xff00713 +mem-write: 0x80010694 <- 0xd735b3 +mem-write: 0x80010698 <- 0x359593 +mem-write: 0x8001069c <- 0x80015737 +mem-write: 0x800106a0 <- 0xb6d533 +mem-write: 0x800106a4 <- 0x6b470713 +mem-write: 0x800106a8 <- 0xa70733 +mem-write: 0x800106ac <- 0x74703 +mem-write: 0x800106b0 <- 0x2000513 +mem-write: 0x800106b4 <- 0xb70733 +mem-write: 0x800106b8 <- 0x40e505b3 +mem-write: 0x800106bc <- 0x2e51663 +mem-write: 0x800106c0 <- 0x100513 +mem-write: 0x800106c4 <- 0xeef6eee3 +mem-write: 0x800106c8 <- 0xc8b533 +mem-write: 0x800106cc <- 0x154513 +mem-write: 0x800106d0 <- 0xef1ff06f +mem-write: 0x800106d4 <- 0x1000737 +mem-write: 0x800106d8 <- 0x1000593 +mem-write: 0x800106dc <- 0xfce6e0e3 +mem-write: 0x800106e0 <- 0x1800593 +mem-write: 0x800106e4 <- 0xfb9ff06f +mem-write: 0x800106e8 <- 0xe65333 +mem-write: 0x800106ec <- 0xb696b3 +mem-write: 0x800106f0 <- 0xd36333 +mem-write: 0x800106f4 <- 0x1035513 +mem-write: 0x800106f8 <- 0xb61eb3 +mem-write: 0x800106fc <- 0xe7d633 +mem-write: 0x80010700 <- 0x2a676b3 +mem-write: 0x80010704 <- 0xb797b3 +mem-write: 0x80010708 <- 0xe8d733 +mem-write: 0x8001070c <- 0xf76833 +mem-write: 0x80010710 <- 0x1031793 +mem-write: 0x80010714 <- 0x107d793 +mem-write: 0x80010718 <- 0x1085713 +mem-write: 0x8001071c <- 0x2a65633 +mem-write: 0x80010720 <- 0x1069693 +mem-write: 0x80010724 <- 0xe6e733 +mem-write: 0x80010728 <- 0x2c78f33 +mem-write: 0x8001072c <- 0x60e13 +mem-write: 0x80010730 <- 0x1e77e63 +mem-write: 0x80010734 <- 0x670733 +mem-write: 0x80010738 <- 0xfff60e13 +mem-write: 0x8001073c <- 0x676863 +mem-write: 0x80010740 <- 0x1e77663 +mem-write: 0x80010744 <- 0xffe60e13 +mem-write: 0x80010748 <- 0x670733 +mem-write: 0x8001074c <- 0x41e70733 +mem-write: 0x80010750 <- 0x2a776b3 +mem-write: 0x80010754 <- 0x2a75733 +mem-write: 0x80010758 <- 0x1069693 +mem-write: 0x8001075c <- 0x2e78633 +mem-write: 0x80010760 <- 0x1081793 +mem-write: 0x80010764 <- 0x107d793 +mem-write: 0x80010768 <- 0xf6e7b3 +mem-write: 0x8001076c <- 0x70693 +mem-write: 0x80010770 <- 0xc7fe63 +mem-write: 0x80010774 <- 0x6787b3 +mem-write: 0x80010778 <- 0xfff70693 +mem-write: 0x8001077c <- 0x67e863 +mem-write: 0x80010780 <- 0xc7f663 +mem-write: 0x80010784 <- 0xffe70693 +mem-write: 0x80010788 <- 0x6787b3 +mem-write: 0x8001078c <- 0x10e1513 +mem-write: 0x80010790 <- 0x10e37 +mem-write: 0x80010794 <- 0xd56533 +mem-write: 0x80010798 <- 0xfffe0693 +mem-write: 0x8001079c <- 0xd57833 +mem-write: 0x800107a0 <- 0x40c787b3 +mem-write: 0x800107a4 <- 0xdef6b3 +mem-write: 0x800107a8 <- 0x1055613 +mem-write: 0x800107ac <- 0x10ede93 +mem-write: 0x800107b0 <- 0x2d80333 +mem-write: 0x800107b4 <- 0x2d606b3 +mem-write: 0x800107b8 <- 0x1035713 +mem-write: 0x800107bc <- 0x3d80833 +mem-write: 0x800107c0 <- 0xd80833 +mem-write: 0x800107c4 <- 0x1070733 +mem-write: 0x800107c8 <- 0x3d60633 +mem-write: 0x800107cc <- 0xd77463 +mem-write: 0x800107d0 <- 0x1c60633 +mem-write: 0x800107d4 <- 0x1075693 +mem-write: 0x800107d8 <- 0xc68633 +mem-write: 0x800107dc <- 0x2c7e663 +mem-write: 0x800107e0 <- 0xcec79ce3 +mem-write: 0x800107e4 <- 0x107b7 +mem-write: 0x800107e8 <- 0xfff78793 +mem-write: 0x800107ec <- 0xf77733 +mem-write: 0x800107f0 <- 0x1071713 +mem-write: 0x800107f4 <- 0xf37333 +VXDRV: upload 1024 bytes to 0x800107f8 +mem-write: 0x800107f8 <- 0xb898b3 +mem-write: 0x800107fc <- 0x670733 +mem-write: 0x80010800 <- 0x593 +mem-write: 0x80010804 <- 0xdae8fee3 +mem-write: 0x80010808 <- 0xfff50513 +mem-write: 0x8001080c <- 0xccdff06f +mem-write: 0x80010810 <- 0x593 +mem-write: 0x80010814 <- 0x513 +mem-write: 0x80010818 <- 0xda9ff06f +mem-write: 0x8001081c <- 0x60893 +mem-write: 0x80010820 <- 0x68713 +mem-write: 0x80010824 <- 0x50793 +mem-write: 0x80010828 <- 0x58813 +mem-write: 0x8001082c <- 0x22069c63 +mem-write: 0x80010830 <- 0x800156b7 +mem-write: 0x80010834 <- 0x6b468693 +mem-write: 0x80010838 <- 0xcc5fc63 +mem-write: 0x8001083c <- 0x10337 +mem-write: 0x80010840 <- 0xa667e63 +mem-write: 0x80010844 <- 0xff00313 +mem-write: 0x80010848 <- 0xc37463 +mem-write: 0x8001084c <- 0x800713 +mem-write: 0x80010850 <- 0xe65333 +mem-write: 0x80010854 <- 0x6686b3 +mem-write: 0x80010858 <- 0x6ce03 +mem-write: 0x8001085c <- 0xee0e33 +mem-write: 0x80010860 <- 0x2000713 +mem-write: 0x80010864 <- 0x41c70333 +mem-write: 0x80010868 <- 0x1c70c63 +mem-write: 0x8001086c <- 0x6595b3 +mem-write: 0x80010870 <- 0x1c55e33 +mem-write: 0x80010874 <- 0x6618b3 +mem-write: 0x80010878 <- 0xbe6833 +mem-write: 0x8001087c <- 0x6517b3 +mem-write: 0x80010880 <- 0x108d613 +mem-write: 0x80010884 <- 0x2c87733 +mem-write: 0x80010888 <- 0x1089513 +mem-write: 0x8001088c <- 0x1055513 +mem-write: 0x80010890 <- 0x107d693 +mem-write: 0x80010894 <- 0x2c85833 +mem-write: 0x80010898 <- 0x1071713 +mem-write: 0x8001089c <- 0xd766b3 +mem-write: 0x800108a0 <- 0x3050833 +mem-write: 0x800108a4 <- 0x106fa63 +mem-write: 0x800108a8 <- 0x11686b3 +mem-write: 0x800108ac <- 0x116e663 +mem-write: 0x800108b0 <- 0x106f463 +mem-write: 0x800108b4 <- 0x11686b3 +mem-write: 0x800108b8 <- 0x410686b3 +mem-write: 0x800108bc <- 0x2c6f733 +mem-write: 0x800108c0 <- 0x1079793 +mem-write: 0x800108c4 <- 0x107d793 +mem-write: 0x800108c8 <- 0x2c6d6b3 +mem-write: 0x800108cc <- 0x2d506b3 +mem-write: 0x800108d0 <- 0x1071513 +mem-write: 0x800108d4 <- 0xf567b3 +mem-write: 0x800108d8 <- 0xd7fa63 +mem-write: 0x800108dc <- 0x11787b3 +mem-write: 0x800108e0 <- 0x117e663 +mem-write: 0x800108e4 <- 0xd7f463 +mem-write: 0x800108e8 <- 0x11787b3 +mem-write: 0x800108ec <- 0x40d787b3 +mem-write: 0x800108f0 <- 0x67d533 +mem-write: 0x800108f4 <- 0x593 +mem-write: 0x800108f8 <- 0x8067 +mem-write: 0x800108fc <- 0x1000337 +mem-write: 0x80010900 <- 0x1000713 +mem-write: 0x80010904 <- 0xf46666e3 +mem-write: 0x80010908 <- 0x1800713 +mem-write: 0x8001090c <- 0xf45ff06f +mem-write: 0x80010910 <- 0x61663 +mem-write: 0x80010914 <- 0x100613 +mem-write: 0x80010918 <- 0x31658b3 +mem-write: 0x8001091c <- 0x10637 +mem-write: 0x80010920 <- 0xac8f263 +mem-write: 0x80010924 <- 0xff00613 +mem-write: 0x80010928 <- 0x1167463 +mem-write: 0x8001092c <- 0x800713 +mem-write: 0x80010930 <- 0xe8d633 +mem-write: 0x80010934 <- 0xc686b3 +mem-write: 0x80010938 <- 0x6ce03 +mem-write: 0x8001093c <- 0xee0e33 +mem-write: 0x80010940 <- 0x2000713 +mem-write: 0x80010944 <- 0x41c70333 +mem-write: 0x80010948 <- 0x9c71863 +mem-write: 0x8001094c <- 0x411585b3 +mem-write: 0x80010950 <- 0x108d713 +mem-write: 0x80010954 <- 0x1089513 +mem-write: 0x80010958 <- 0x1055513 +mem-write: 0x8001095c <- 0x107d613 +mem-write: 0x80010960 <- 0x2e5f6b3 +mem-write: 0x80010964 <- 0x2e5d5b3 +mem-write: 0x80010968 <- 0x1069693 +mem-write: 0x8001096c <- 0xc6e6b3 +mem-write: 0x80010970 <- 0x2b505b3 +mem-write: 0x80010974 <- 0xb6fa63 +mem-write: 0x80010978 <- 0x11686b3 +mem-write: 0x8001097c <- 0x116e663 +mem-write: 0x80010980 <- 0xb6f463 +mem-write: 0x80010984 <- 0x11686b3 +mem-write: 0x80010988 <- 0x40b685b3 +mem-write: 0x8001098c <- 0x2e5f6b3 +mem-write: 0x80010990 <- 0x1079793 +mem-write: 0x80010994 <- 0x107d793 +mem-write: 0x80010998 <- 0x2e5d5b3 +mem-write: 0x8001099c <- 0x2b505b3 +mem-write: 0x800109a0 <- 0x1069513 +mem-write: 0x800109a4 <- 0xf567b3 +mem-write: 0x800109a8 <- 0xb7fa63 +mem-write: 0x800109ac <- 0x11787b3 +mem-write: 0x800109b0 <- 0x117e663 +mem-write: 0x800109b4 <- 0xb7f463 +mem-write: 0x800109b8 <- 0x11787b3 +mem-write: 0x800109bc <- 0x40b787b3 +mem-write: 0x800109c0 <- 0xf31ff06f +mem-write: 0x800109c4 <- 0x1000637 +mem-write: 0x800109c8 <- 0x1000713 +mem-write: 0x800109cc <- 0xf6c8e2e3 +mem-write: 0x800109d0 <- 0x1800713 +mem-write: 0x800109d4 <- 0xf5dff06f +mem-write: 0x800109d8 <- 0x6898b3 +mem-write: 0x800109dc <- 0x1c5d733 +mem-write: 0x800109e0 <- 0x6517b3 +mem-write: 0x800109e4 <- 0x1c55e33 +mem-write: 0x800109e8 <- 0x108d513 +mem-write: 0x800109ec <- 0x2a776b3 +mem-write: 0x800109f0 <- 0x6595b3 +mem-write: 0x800109f4 <- 0xbe6e33 +mem-write: 0x800109f8 <- 0x1089593 +mem-write: 0x800109fc <- 0x105d593 +mem-write: 0x80010a00 <- 0x10e5613 +mem-write: 0x80010a04 <- 0x2a75733 +mem-write: 0x80010a08 <- 0x1069693 +mem-write: 0x80010a0c <- 0xc6e6b3 +mem-write: 0x80010a10 <- 0x2e58733 +mem-write: 0x80010a14 <- 0xe6fa63 +mem-write: 0x80010a18 <- 0x11686b3 +mem-write: 0x80010a1c <- 0x116e663 +mem-write: 0x80010a20 <- 0xe6f463 +mem-write: 0x80010a24 <- 0x11686b3 +mem-write: 0x80010a28 <- 0x40e68633 +mem-write: 0x80010a2c <- 0x2a676b3 +mem-write: 0x80010a30 <- 0x10e1e13 +mem-write: 0x80010a34 <- 0x10e5e13 +mem-write: 0x80010a38 <- 0x2a65633 +mem-write: 0x80010a3c <- 0x1069693 +mem-write: 0x80010a40 <- 0x2c58633 +mem-write: 0x80010a44 <- 0x1c6e5b3 +mem-write: 0x80010a48 <- 0xc5fa63 +mem-write: 0x80010a4c <- 0x11585b3 +mem-write: 0x80010a50 <- 0x115e663 +mem-write: 0x80010a54 <- 0xc5f463 +mem-write: 0x80010a58 <- 0x11585b3 +mem-write: 0x80010a5c <- 0x40c585b3 +mem-write: 0x80010a60 <- 0xef1ff06f +mem-write: 0x80010a64 <- 0xe8d5eae3 +mem-write: 0x80010a68 <- 0x10737 +mem-write: 0x80010a6c <- 0x4e6fc63 +mem-write: 0x80010a70 <- 0xff00e13 +mem-write: 0x80010a74 <- 0xde3733 +mem-write: 0x80010a78 <- 0x371713 +mem-write: 0x80010a7c <- 0x800158b7 +mem-write: 0x80010a80 <- 0xe6d333 +mem-write: 0x80010a84 <- 0x6b488893 +mem-write: 0x80010a88 <- 0x6888b3 +mem-write: 0x80010a8c <- 0x8ce03 +mem-write: 0x80010a90 <- 0xee0e33 +mem-write: 0x80010a94 <- 0x2000713 +mem-write: 0x80010a98 <- 0x41c70333 +mem-write: 0x80010a9c <- 0x3c71e63 +mem-write: 0x80010aa0 <- 0xb6e463 +mem-write: 0x80010aa4 <- 0xc56a63 +mem-write: 0x80010aa8 <- 0x40c507b3 +mem-write: 0x80010aac <- 0x40d585b3 +mem-write: 0x80010ab0 <- 0xf53533 +mem-write: 0x80010ab4 <- 0x40a58833 +mem-write: 0x80010ab8 <- 0x78513 +mem-write: 0x80010abc <- 0x80593 +mem-write: 0x80010ac0 <- 0xe39ff06f +mem-write: 0x80010ac4 <- 0x10008b7 +mem-write: 0x80010ac8 <- 0x1000713 +mem-write: 0x80010acc <- 0xfb16e8e3 +mem-write: 0x80010ad0 <- 0x1800713 +mem-write: 0x80010ad4 <- 0xfa9ff06f +mem-write: 0x80010ad8 <- 0x1c65733 +mem-write: 0x80010adc <- 0x6696b3 +mem-write: 0x80010ae0 <- 0xd76f33 +mem-write: 0x80010ae4 <- 0x1c5d7b3 +mem-write: 0x80010ae8 <- 0x10f5713 +mem-write: 0x80010aec <- 0x2e7f8b3 +mem-write: 0x80010af0 <- 0x6595b3 +mem-write: 0x80010af4 <- 0x1c55833 +mem-write: 0x80010af8 <- 0xb86833 +mem-write: 0x80010afc <- 0x10f1593 +mem-write: 0x80010b00 <- 0x105d593 +mem-write: 0x80010b04 <- 0x1085693 +mem-write: 0x80010b08 <- 0x661633 +mem-write: 0x80010b0c <- 0x651533 +mem-write: 0x80010b10 <- 0x2e7d7b3 +mem-write: 0x80010b14 <- 0x1089893 +mem-write: 0x80010b18 <- 0xd8e6b3 +mem-write: 0x80010b1c <- 0x2f58eb3 +mem-write: 0x80010b20 <- 0x78893 +mem-write: 0x80010b24 <- 0x1d6fe63 +mem-write: 0x80010b28 <- 0x1e686b3 +mem-write: 0x80010b2c <- 0xfff78893 +mem-write: 0x80010b30 <- 0x1e6e863 +mem-write: 0x80010b34 <- 0x1d6f663 +mem-write: 0x80010b38 <- 0xffe78893 +mem-write: 0x80010b3c <- 0x1e686b3 +mem-write: 0x80010b40 <- 0x41d686b3 +mem-write: 0x80010b44 <- 0x2e6feb3 +mem-write: 0x80010b48 <- 0x1081813 +mem-write: 0x80010b4c <- 0x1085813 +mem-write: 0x80010b50 <- 0x2e6d6b3 +mem-write: 0x80010b54 <- 0x10e9e93 +mem-write: 0x80010b58 <- 0x10eeeb3 +mem-write: 0x80010b5c <- 0x2d585b3 +mem-write: 0x80010b60 <- 0x68793 +mem-write: 0x80010b64 <- 0xbefe63 +mem-write: 0x80010b68 <- 0x1ee8eb3 +mem-write: 0x80010b6c <- 0xfff68793 +mem-write: 0x80010b70 <- 0x1eee863 +mem-write: 0x80010b74 <- 0xbef663 +mem-write: 0x80010b78 <- 0xffe68793 +mem-write: 0x80010b7c <- 0x1ee8eb3 +mem-write: 0x80010b80 <- 0x40be85b3 +mem-write: 0x80010b84 <- 0x1089893 +mem-write: 0x80010b88 <- 0x10eb7 +mem-write: 0x80010b8c <- 0xf8e8b3 +mem-write: 0x80010b90 <- 0xfffe8793 +mem-write: 0x80010b94 <- 0xf8f833 +mem-write: 0x80010b98 <- 0x1065693 +mem-write: 0x80010b9c <- 0x108d893 +mem-write: 0x80010ba0 <- 0xf677b3 +mem-write: 0x80010ba4 <- 0x2f80733 +mem-write: 0x80010ba8 <- 0x2f887b3 +mem-write: 0x80010bac <- 0x2d80833 +mem-write: 0x80010bb0 <- 0x2d888b3 +mem-write: 0x80010bb4 <- 0xf80833 +mem-write: 0x80010bb8 <- 0x1075693 +mem-write: 0x80010bbc <- 0x10686b3 +mem-write: 0x80010bc0 <- 0xf6f463 +mem-write: 0x80010bc4 <- 0x1d888b3 +mem-write: 0x80010bc8 <- 0x107b7 +mem-write: 0x80010bcc <- 0xfff78793 +mem-write: 0x80010bd0 <- 0x106d813 +mem-write: 0x80010bd4 <- 0xf6f6b3 +mem-write: 0x80010bd8 <- 0x1069693 +mem-write: 0x80010bdc <- 0xf77733 +mem-write: 0x80010be0 <- 0x11808b3 +mem-write: 0x80010be4 <- 0xe68733 +mem-write: 0x80010be8 <- 0x115e663 +mem-write: 0x80010bec <- 0x1159e63 +mem-write: 0x80010bf0 <- 0xe57c63 +mem-write: 0x80010bf4 <- 0x40c70633 +VXDRV: upload 1024 bytes to 0x80010bf8 +mem-write: 0x80010bf8 <- 0xc73733 +mem-write: 0x80010bfc <- 0x1e70733 +mem-write: 0x80010c00 <- 0x40e888b3 +mem-write: 0x80010c04 <- 0x60713 +mem-write: 0x80010c08 <- 0x40e50733 +mem-write: 0x80010c0c <- 0xe53533 +mem-write: 0x80010c10 <- 0x411585b3 +mem-write: 0x80010c14 <- 0x40a585b3 +mem-write: 0x80010c18 <- 0x1c597b3 +mem-write: 0x80010c1c <- 0x675733 +mem-write: 0x80010c20 <- 0xe7e533 +mem-write: 0x80010c24 <- 0x65d5b3 +mem-write: 0x80010c28 <- 0xcd1ff06f +mem-write: 0x80010c2c <- 0xfd010113 +mem-write: 0x80010c30 <- 0x145d793 +mem-write: 0x80010c34 <- 0x2912223 +mem-write: 0x80010c38 <- 0x3212023 +mem-write: 0x80010c3c <- 0x1412c23 +mem-write: 0x80010c40 <- 0x1612823 +mem-write: 0x80010c44 <- 0x1812423 +mem-write: 0x80010c48 <- 0xc59493 +mem-write: 0x80010c4c <- 0x2112623 +mem-write: 0x80010c50 <- 0x2812423 +mem-write: 0x80010c54 <- 0x1312e23 +mem-write: 0x80010c58 <- 0x1512a23 +mem-write: 0x80010c5c <- 0x1712623 +mem-write: 0x80010c60 <- 0x1579713 +mem-write: 0x80010c64 <- 0x50913 +mem-write: 0x80010c68 <- 0x60b13 +mem-write: 0x80010c6c <- 0x68c13 +mem-write: 0x80010c70 <- 0xc4d493 +mem-write: 0x80010c74 <- 0x1f5da13 +mem-write: 0x80010c78 <- 0xa070463 +mem-write: 0x80010c7c <- 0x7ff7fa93 +mem-write: 0x80010c80 <- 0x7ff00793 +mem-write: 0x80010c84 <- 0x10fa8063 +mem-write: 0x80010c88 <- 0x1d55993 +mem-write: 0x80010c8c <- 0x349493 +mem-write: 0x80010c90 <- 0x99e4b3 +mem-write: 0x80010c94 <- 0x8009b7 +mem-write: 0x80010c98 <- 0x134e9b3 +mem-write: 0x80010c9c <- 0x351413 +mem-write: 0x80010ca0 <- 0xc01a8a93 +mem-write: 0x80010ca4 <- 0xb93 +mem-write: 0x80010ca8 <- 0x14c5793 +mem-write: 0x80010cac <- 0xcc1513 +mem-write: 0x80010cb0 <- 0x1579713 +mem-write: 0x80010cb4 <- 0xc55493 +mem-write: 0x80010cb8 <- 0x7ff7f593 +mem-write: 0x80010cbc <- 0x1fc5c13 +mem-write: 0x80010cc0 <- 0x10070063 +mem-write: 0x80010cc4 <- 0x7ff00793 +mem-write: 0x80010cc8 <- 0x16f58263 +mem-write: 0x80010ccc <- 0x349513 +mem-write: 0x80010cd0 <- 0x1db5793 +mem-write: 0x80010cd4 <- 0xa7e533 +mem-write: 0x80010cd8 <- 0x8004b7 +mem-write: 0x80010cdc <- 0x9564b3 +mem-write: 0x80010ce0 <- 0x3b1f93 +mem-write: 0x80010ce4 <- 0xc0158513 +mem-write: 0x80010ce8 <- 0x613 +mem-write: 0x80010cec <- 0x2b9793 +mem-write: 0x80010cf0 <- 0xc7e7b3 +mem-write: 0x80010cf4 <- 0xfff78793 +mem-write: 0x80010cf8 <- 0xe00713 +mem-write: 0x80010cfc <- 0x18a46b3 +mem-write: 0x80010d00 <- 0x40aa85b3 +mem-write: 0x80010d04 <- 0x16f76063 +mem-write: 0x80010d08 <- 0x80015737 +mem-write: 0x80010d0c <- 0x279793 +mem-write: 0x80010d10 <- 0x60070713 +mem-write: 0x80010d14 <- 0xe787b3 +mem-write: 0x80010d18 <- 0x7a783 +mem-write: 0x80010d1c <- 0x78067 +mem-write: 0x80010d20 <- 0xa4e9b3 +mem-write: 0x80010d24 <- 0x6098e63 +mem-write: 0x80010d28 <- 0x4048063 +mem-write: 0x80010d2c <- 0x48513 +mem-write: 0x80010d30 <- 0x3bd030ef +mem-write: 0x80010d34 <- 0xff550793 +mem-write: 0x80010d38 <- 0x1c00713 +mem-write: 0x80010d3c <- 0x2f74c63 +mem-write: 0x80010d40 <- 0x1d00993 +mem-write: 0x80010d44 <- 0xff850413 +mem-write: 0x80010d48 <- 0x40f989b3 +mem-write: 0x80010d4c <- 0x8494b3 +mem-write: 0x80010d50 <- 0x13959b3 +mem-write: 0x80010d54 <- 0x99e9b3 +mem-write: 0x80010d58 <- 0x891433 +mem-write: 0x80010d5c <- 0xc0d00593 +mem-write: 0x80010d60 <- 0x40a58ab3 +mem-write: 0x80010d64 <- 0xf41ff06f +mem-write: 0x80010d68 <- 0x385030ef +mem-write: 0x80010d6c <- 0x2050513 +mem-write: 0x80010d70 <- 0xfc5ff06f +mem-write: 0x80010d74 <- 0xfd850493 +mem-write: 0x80010d78 <- 0x9919b3 +mem-write: 0x80010d7c <- 0x413 +mem-write: 0x80010d80 <- 0xfddff06f +mem-write: 0x80010d84 <- 0xa4e9b3 +mem-write: 0x80010d88 <- 0x2098463 +mem-write: 0x80010d8c <- 0x50413 +mem-write: 0x80010d90 <- 0x48993 +mem-write: 0x80010d94 <- 0x7ff00a93 +mem-write: 0x80010d98 <- 0x300b93 +mem-write: 0x80010d9c <- 0xf0dff06f +mem-write: 0x80010da0 <- 0x413 +mem-write: 0x80010da4 <- 0xa93 +mem-write: 0x80010da8 <- 0x100b93 +mem-write: 0x80010dac <- 0xefdff06f +mem-write: 0x80010db0 <- 0x413 +mem-write: 0x80010db4 <- 0x7ff00a93 +mem-write: 0x80010db8 <- 0x200b93 +mem-write: 0x80010dbc <- 0xeedff06f +mem-write: 0x80010dc0 <- 0x164efb3 +mem-write: 0x80010dc4 <- 0x80f8063 +mem-write: 0x80010dc8 <- 0x4048263 +mem-write: 0x80010dcc <- 0x48513 +mem-write: 0x80010dd0 <- 0x31d030ef +mem-write: 0x80010dd4 <- 0x50593 +mem-write: 0x80010dd8 <- 0xff558793 +mem-write: 0x80010ddc <- 0x1c00713 +mem-write: 0x80010de0 <- 0x2f74e63 +mem-write: 0x80010de4 <- 0x1d00693 +mem-write: 0x80010de8 <- 0xff858f93 +mem-write: 0x80010dec <- 0x40f686b3 +mem-write: 0x80010df0 <- 0x1f49533 +mem-write: 0x80010df4 <- 0xdb56b3 +mem-write: 0x80010df8 <- 0xa6e4b3 +mem-write: 0x80010dfc <- 0x1fb1fb3 +mem-write: 0x80010e00 <- 0xc0d00713 +mem-write: 0x80010e04 <- 0x40b70533 +mem-write: 0x80010e08 <- 0xee1ff06f +mem-write: 0x80010e0c <- 0xb0513 +mem-write: 0x80010e10 <- 0x2dd030ef +mem-write: 0x80010e14 <- 0x2050593 +mem-write: 0x80010e18 <- 0xfc1ff06f +mem-write: 0x80010e1c <- 0xfd858513 +mem-write: 0x80010e20 <- 0xab14b3 +mem-write: 0x80010e24 <- 0xf93 +mem-write: 0x80010e28 <- 0xfd9ff06f +mem-write: 0x80010e2c <- 0x164efb3 +mem-write: 0x80010e30 <- 0x20f8263 +mem-write: 0x80010e34 <- 0xb0f93 +mem-write: 0x80010e38 <- 0x7ff00513 +mem-write: 0x80010e3c <- 0x300613 +mem-write: 0x80010e40 <- 0xeadff06f +mem-write: 0x80010e44 <- 0x493 +mem-write: 0x80010e48 <- 0x513 +mem-write: 0x80010e4c <- 0x100613 +mem-write: 0x80010e50 <- 0xe9dff06f +mem-write: 0x80010e54 <- 0x493 +mem-write: 0x80010e58 <- 0x7ff00513 +mem-write: 0x80010e5c <- 0x200613 +mem-write: 0x80010e60 <- 0xe8dff06f +mem-write: 0x80010e64 <- 0x134e663 +mem-write: 0x80010e68 <- 0x34999c63 +mem-write: 0x80010e6c <- 0x35f46a63 +mem-write: 0x80010e70 <- 0x1f99613 +mem-write: 0x80010e74 <- 0x145713 +mem-write: 0x80010e78 <- 0x1f41793 +mem-write: 0x80010e7c <- 0x19d993 +mem-write: 0x80010e80 <- 0xe66433 +mem-write: 0x80010e84 <- 0x849513 +mem-write: 0x80010e88 <- 0x18fd893 +mem-write: 0x80010e8c <- 0xa8e8b3 +mem-write: 0x80010e90 <- 0x1055513 +mem-write: 0x80010e94 <- 0x2a9d833 +mem-write: 0x80010e98 <- 0x1089e93 +mem-write: 0x80010e9c <- 0x10ede93 +mem-write: 0x80010ea0 <- 0x1045713 +mem-write: 0x80010ea4 <- 0x8f9313 +mem-write: 0x80010ea8 <- 0x2a9f4b3 +mem-write: 0x80010eac <- 0x80f93 +mem-write: 0x80010eb0 <- 0x30e8633 +mem-write: 0x80010eb4 <- 0x1049993 +mem-write: 0x80010eb8 <- 0x1376733 +mem-write: 0x80010ebc <- 0xc77e63 +mem-write: 0x80010ec0 <- 0x1170733 +mem-write: 0x80010ec4 <- 0xfff80f93 +mem-write: 0x80010ec8 <- 0x1176863 +mem-write: 0x80010ecc <- 0xc77663 +mem-write: 0x80010ed0 <- 0xffe80f93 +mem-write: 0x80010ed4 <- 0x1170733 +mem-write: 0x80010ed8 <- 0x40c70733 +mem-write: 0x80010edc <- 0x2a75e33 +mem-write: 0x80010ee0 <- 0x1041413 +mem-write: 0x80010ee4 <- 0x1045413 +mem-write: 0x80010ee8 <- 0x2a77733 +mem-write: 0x80010eec <- 0xe0613 +mem-write: 0x80010ef0 <- 0x3ce8833 +mem-write: 0x80010ef4 <- 0x1071713 +mem-write: 0x80010ef8 <- 0xe46733 +mem-write: 0x80010efc <- 0x1077e63 +mem-write: 0x80010f00 <- 0x1170733 +mem-write: 0x80010f04 <- 0xfffe0613 +mem-write: 0x80010f08 <- 0x1176863 +mem-write: 0x80010f0c <- 0x1077663 +mem-write: 0x80010f10 <- 0xffee0613 +mem-write: 0x80010f14 <- 0x1170733 +mem-write: 0x80010f18 <- 0x41070433 +mem-write: 0x80010f1c <- 0x10f9f93 +mem-write: 0x80010f20 <- 0x10837 +mem-write: 0x80010f24 <- 0xcfefb3 +mem-write: 0x80010f28 <- 0xfff80e13 +mem-write: 0x80010f2c <- 0x10fd613 +mem-write: 0x80010f30 <- 0x1cff733 +mem-write: 0x80010f34 <- 0x1035f13 +mem-write: 0x80010f38 <- 0x1c37e33 +mem-write: 0x80010f3c <- 0x2ee03b3 +mem-write: 0x80010f40 <- 0x3c604b3 +mem-write: 0x80010f44 <- 0x2ef0733 +mem-write: 0x80010f48 <- 0x3e602b3 +mem-write: 0x80010f4c <- 0x970633 +mem-write: 0x80010f50 <- 0x103d713 +mem-write: 0x80010f54 <- 0xc70733 +mem-write: 0x80010f58 <- 0x977463 +mem-write: 0x80010f5c <- 0x10282b3 +mem-write: 0x80010f60 <- 0x1075613 +mem-write: 0x80010f64 <- 0x560633 +mem-write: 0x80010f68 <- 0x102b7 +mem-write: 0x80010f6c <- 0xfff28293 +mem-write: 0x80010f70 <- 0x577833 +mem-write: 0x80010f74 <- 0x1081813 +mem-write: 0x80010f78 <- 0x53f3b3 +mem-write: 0x80010f7c <- 0x780833 +mem-write: 0x80010f80 <- 0xc46863 +mem-write: 0x80010f84 <- 0xf8493 +mem-write: 0x80010f88 <- 0x4c41463 +mem-write: 0x80010f8c <- 0x507f263 +mem-write: 0x80010f90 <- 0x6787b3 +mem-write: 0x80010f94 <- 0x67b733 +mem-write: 0x80010f98 <- 0x1170733 +mem-write: 0x80010f9c <- 0xe40433 +mem-write: 0x80010fa0 <- 0xffff8493 +mem-write: 0x80010fa4 <- 0x88e663 +mem-write: 0x80010fa8 <- 0x2889463 +mem-write: 0x80010fac <- 0x267e263 +mem-write: 0x80010fb0 <- 0xc46663 +mem-write: 0x80010fb4 <- 0x861e63 +mem-write: 0x80010fb8 <- 0x107fc63 +mem-write: 0x80010fbc <- 0x6787b3 +mem-write: 0x80010fc0 <- 0x67b733 +mem-write: 0x80010fc4 <- 0x1170733 +mem-write: 0x80010fc8 <- 0xffef8493 +mem-write: 0x80010fcc <- 0xe40433 +mem-write: 0x80010fd0 <- 0x41078833 +mem-write: 0x80010fd4 <- 0x40c40433 +mem-write: 0x80010fd8 <- 0x107b7b3 +mem-write: 0x80010fdc <- 0x40f40433 +mem-write: 0x80010fe0 <- 0xfff00f93 +mem-write: 0x80010fe4 <- 0x12888463 +mem-write: 0x80010fe8 <- 0x2a45fb3 +mem-write: 0x80010fec <- 0x1085713 +mem-write: 0x80010ff0 <- 0x2a47433 +mem-write: 0x80010ff4 <- 0xf8613 +VXDRV: upload 1024 bytes to 0x80010ff8 +mem-write: 0x80010ff8 <- 0x3fe87b3 +mem-write: 0x80010ffc <- 0x1041413 +mem-write: 0x80011000 <- 0x876433 +mem-write: 0x80011004 <- 0xf47e63 +mem-write: 0x80011008 <- 0x1140433 +mem-write: 0x8001100c <- 0xffff8613 +mem-write: 0x80011010 <- 0x1146863 +mem-write: 0x80011014 <- 0xf47663 +mem-write: 0x80011018 <- 0xffef8613 +mem-write: 0x8001101c <- 0x1140433 +mem-write: 0x80011020 <- 0x40f40433 +mem-write: 0x80011024 <- 0x2a45733 +mem-write: 0x80011028 <- 0x1081813 +mem-write: 0x8001102c <- 0x1085813 +mem-write: 0x80011030 <- 0x2a47433 +mem-write: 0x80011034 <- 0x70793 +mem-write: 0x80011038 <- 0x2ee8eb3 +mem-write: 0x8001103c <- 0x1041413 +mem-write: 0x80011040 <- 0x886433 +mem-write: 0x80011044 <- 0x1d47e63 +mem-write: 0x80011048 <- 0x1140433 +mem-write: 0x8001104c <- 0xfff70793 +mem-write: 0x80011050 <- 0x1146863 +mem-write: 0x80011054 <- 0x1d47663 +mem-write: 0x80011058 <- 0xffe70793 +mem-write: 0x8001105c <- 0x1140433 +mem-write: 0x80011060 <- 0x1061613 +mem-write: 0x80011064 <- 0xf66633 +mem-write: 0x80011068 <- 0x1061793 +mem-write: 0x8001106c <- 0x107d793 +mem-write: 0x80011070 <- 0x1065713 +mem-write: 0x80011074 <- 0x2ef0833 +mem-write: 0x80011078 <- 0x41d40433 +mem-write: 0x8001107c <- 0x2ff0f33 +mem-write: 0x80011080 <- 0x3c78eb3 +mem-write: 0x80011084 <- 0x3c70e33 +mem-write: 0x80011088 <- 0x10ed793 +mem-write: 0x8001108c <- 0x1cf0f33 +mem-write: 0x80011090 <- 0x1e787b3 +mem-write: 0x80011094 <- 0x1c7f663 +mem-write: 0x80011098 <- 0x10737 +mem-write: 0x8001109c <- 0xe80833 +mem-write: 0x800110a0 <- 0x107d713 +mem-write: 0x800110a4 <- 0x1070733 +mem-write: 0x800110a8 <- 0x10837 +mem-write: 0x800110ac <- 0xfff80813 +mem-write: 0x800110b0 <- 0x107f533 +mem-write: 0x800110b4 <- 0x1051513 +mem-write: 0x800110b8 <- 0x10efeb3 +mem-write: 0x800110bc <- 0x1d50533 +mem-write: 0x800110c0 <- 0xe46863 +mem-write: 0x800110c4 <- 0x24e41063 +mem-write: 0x800110c8 <- 0x60f93 +mem-write: 0x800110cc <- 0x4050063 +mem-write: 0x800110d0 <- 0x888433 +mem-write: 0x800110d4 <- 0xfff60f93 +mem-write: 0x800110d8 <- 0x3146463 +mem-write: 0x800110dc <- 0xe46663 +mem-write: 0x800110e0 <- 0x22e41063 +mem-write: 0x800110e4 <- 0x2a37063 +mem-write: 0x800110e8 <- 0x131793 +mem-write: 0x800110ec <- 0x67b333 +mem-write: 0x800110f0 <- 0x11308b3 +mem-write: 0x800110f4 <- 0xffe60f93 +mem-write: 0x800110f8 <- 0x1140433 +mem-write: 0x800110fc <- 0x78313 +mem-write: 0x80011100 <- 0xe41463 +mem-write: 0x80011104 <- 0x650463 +mem-write: 0x80011108 <- 0x1fef93 +mem-write: 0x8001110c <- 0x3ff58793 +mem-write: 0x80011110 <- 0x10f05863 +mem-write: 0x80011114 <- 0x7ff713 +mem-write: 0x80011118 <- 0x2070063 +mem-write: 0x8001111c <- 0xfff713 +mem-write: 0x80011120 <- 0x400613 +mem-write: 0x80011124 <- 0xc70a63 +mem-write: 0x80011128 <- 0x4f8613 +mem-write: 0x8001112c <- 0x1f63fb3 +mem-write: 0x80011130 <- 0x1f484b3 +mem-write: 0x80011134 <- 0x60f93 +mem-write: 0x80011138 <- 0x749713 +mem-write: 0x8001113c <- 0x75a63 +mem-write: 0x80011140 <- 0xff0007b7 +mem-write: 0x80011144 <- 0xfff78793 +mem-write: 0x80011148 <- 0xf4f4b3 +mem-write: 0x8001114c <- 0x40058793 +mem-write: 0x80011150 <- 0x7fe00713 +mem-write: 0x80011154 <- 0xaf74063 +mem-write: 0x80011158 <- 0x3fdf93 +mem-write: 0x8001115c <- 0x1d49713 +mem-write: 0x80011160 <- 0x1f76733 +mem-write: 0x80011164 <- 0x34d513 +mem-write: 0x80011168 <- 0x1479793 +mem-write: 0x8001116c <- 0x7ff00637 +mem-write: 0x80011170 <- 0xc51513 +mem-write: 0x80011174 <- 0x2c12083 +mem-write: 0x80011178 <- 0x2812403 +mem-write: 0x8001117c <- 0xc7f7b3 +mem-write: 0x80011180 <- 0xc55513 +mem-write: 0x80011184 <- 0xa7e533 +mem-write: 0x80011188 <- 0x1f69693 +mem-write: 0x8001118c <- 0xd567b3 +mem-write: 0x80011190 <- 0x2412483 +mem-write: 0x80011194 <- 0x2012903 +mem-write: 0x80011198 <- 0x1c12983 +mem-write: 0x8001119c <- 0x1812a03 +mem-write: 0x800111a0 <- 0x1412a83 +mem-write: 0x800111a4 <- 0x1012b03 +mem-write: 0x800111a8 <- 0xc12b83 +mem-write: 0x800111ac <- 0x812c03 +mem-write: 0x800111b0 <- 0x70513 +mem-write: 0x800111b4 <- 0x78593 +mem-write: 0x800111b8 <- 0x3010113 +mem-write: 0x800111bc <- 0x8067 +mem-write: 0x800111c0 <- 0xfff58593 +mem-write: 0x800111c4 <- 0x793 +mem-write: 0x800111c8 <- 0xcbdff06f +mem-write: 0x800111cc <- 0xa0693 +mem-write: 0x800111d0 <- 0x98493 +mem-write: 0x800111d4 <- 0x40f93 +mem-write: 0x800111d8 <- 0xb8613 +mem-write: 0x800111dc <- 0x300793 +mem-write: 0x800111e0 <- 0xef60863 +mem-write: 0x800111e4 <- 0x100793 +mem-write: 0x800111e8 <- 0xef60e63 +mem-write: 0x800111ec <- 0x200793 +mem-write: 0x800111f0 <- 0xf0f61ee3 +mem-write: 0x800111f4 <- 0x513 +mem-write: 0x800111f8 <- 0x713 +mem-write: 0x800111fc <- 0x7ff00793 +mem-write: 0x80011200 <- 0xf69ff06f +mem-write: 0x80011204 <- 0xc0693 +mem-write: 0x80011208 <- 0xfd5ff06f +mem-write: 0x8001120c <- 0x804b7 +mem-write: 0x80011210 <- 0xf93 +mem-write: 0x80011214 <- 0x693 +mem-write: 0x80011218 <- 0x300613 +mem-write: 0x8001121c <- 0xfc1ff06f +mem-write: 0x80011220 <- 0x100513 +mem-write: 0x80011224 <- 0x40f50533 +mem-write: 0x80011228 <- 0x3800713 +mem-write: 0x8001122c <- 0xaa74c63 +mem-write: 0x80011230 <- 0x1f00713 +mem-write: 0x80011234 <- 0x6a74463 +mem-write: 0x80011238 <- 0x41e58593 +mem-write: 0x8001123c <- 0xb497b3 +mem-write: 0x80011240 <- 0xafd733 +mem-write: 0x80011244 <- 0xbf95b3 +mem-write: 0x80011248 <- 0xe7e7b3 +mem-write: 0x8001124c <- 0xb035b3 +mem-write: 0x80011250 <- 0xb7e7b3 +mem-write: 0x80011254 <- 0xa4d533 +mem-write: 0x80011258 <- 0x77f713 +mem-write: 0x8001125c <- 0x2070063 +mem-write: 0x80011260 <- 0xf7f713 +mem-write: 0x80011264 <- 0x400613 +mem-write: 0x80011268 <- 0xc70a63 +mem-write: 0x8001126c <- 0x478713 +mem-write: 0x80011270 <- 0xf737b3 +mem-write: 0x80011274 <- 0xf50533 +mem-write: 0x80011278 <- 0x70793 +mem-write: 0x8001127c <- 0x851713 +mem-write: 0x80011280 <- 0x6074863 +mem-write: 0x80011284 <- 0x1d51713 +mem-write: 0x80011288 <- 0x37d793 +mem-write: 0x8001128c <- 0xf76733 +mem-write: 0x80011290 <- 0x355513 +mem-write: 0x80011294 <- 0x793 +mem-write: 0x80011298 <- 0xed1ff06f +mem-write: 0x8001129c <- 0xfe100713 +mem-write: 0x800112a0 <- 0x40f707b3 +mem-write: 0x800112a4 <- 0x2000613 +mem-write: 0x800112a8 <- 0xf4d7b3 +mem-write: 0x800112ac <- 0x713 +mem-write: 0x800112b0 <- 0xc50663 +mem-write: 0x800112b4 <- 0x43e58593 +mem-write: 0x800112b8 <- 0xb49733 +mem-write: 0x800112bc <- 0x1f76fb3 +mem-write: 0x800112c0 <- 0x1f03fb3 +mem-write: 0x800112c4 <- 0x1f7e7b3 +mem-write: 0x800112c8 <- 0x513 +mem-write: 0x800112cc <- 0xf8dff06f +mem-write: 0x800112d0 <- 0x80537 +mem-write: 0x800112d4 <- 0x713 +mem-write: 0x800112d8 <- 0x7ff00793 +mem-write: 0x800112dc <- 0x693 +mem-write: 0x800112e0 <- 0xe89ff06f +mem-write: 0x800112e4 <- 0x513 +mem-write: 0x800112e8 <- 0x713 +mem-write: 0x800112ec <- 0xfa9ff06f +mem-write: 0x800112f0 <- 0x513 +mem-write: 0x800112f4 <- 0x713 +mem-write: 0x800112f8 <- 0x100793 +mem-write: 0x800112fc <- 0xe6dff06f +mem-write: 0x80011300 <- 0xf8613 +mem-write: 0x80011304 <- 0x60f93 +mem-write: 0x80011308 <- 0xe01ff06f +mem-write: 0x8001130c <- 0xfd010113 +mem-write: 0x80011310 <- 0x145d793 +mem-write: 0x80011314 <- 0x2812423 +mem-write: 0x80011318 <- 0x2912223 +mem-write: 0x8001131c <- 0x1312e23 +mem-write: 0x80011320 <- 0x1412c23 +mem-write: 0x80011324 <- 0x1512a23 +mem-write: 0x80011328 <- 0xc59493 +mem-write: 0x8001132c <- 0x2112623 +mem-write: 0x80011330 <- 0x3212023 +mem-write: 0x80011334 <- 0x1612823 +mem-write: 0x80011338 <- 0x1712623 +mem-write: 0x8001133c <- 0x1579713 +mem-write: 0x80011340 <- 0x50413 +mem-write: 0x80011344 <- 0x60993 +mem-write: 0x80011348 <- 0x68a93 +mem-write: 0x8001134c <- 0xc4d493 +mem-write: 0x80011350 <- 0x1f5da13 +mem-write: 0x80011354 <- 0xa070663 +mem-write: 0x80011358 <- 0x7ff7fb13 +mem-write: 0x8001135c <- 0x7ff00793 +mem-write: 0x80011360 <- 0x10fb0263 +mem-write: 0x80011364 <- 0x1d55793 +mem-write: 0x80011368 <- 0x349493 +mem-write: 0x8001136c <- 0x97e4b3 +mem-write: 0x80011370 <- 0x8007b7 +mem-write: 0x80011374 <- 0xf4e4b3 +mem-write: 0x80011378 <- 0x351913 +mem-write: 0x8001137c <- 0xc01b0b13 +mem-write: 0x80011380 <- 0xb93 +mem-write: 0x80011384 <- 0x14ad793 +mem-write: 0x80011388 <- 0xca9413 +mem-write: 0x8001138c <- 0x1579713 +mem-write: 0x80011390 <- 0xc45413 +mem-write: 0x80011394 <- 0x7ff7f513 +mem-write: 0x80011398 <- 0x1fada93 +mem-write: 0x8001139c <- 0x10070063 +mem-write: 0x800113a0 <- 0x7ff00793 +mem-write: 0x800113a4 <- 0x16f50063 +mem-write: 0x800113a8 <- 0x1d9d793 +mem-write: 0x800113ac <- 0x341413 +mem-write: 0x800113b0 <- 0x87e433 +mem-write: 0x800113b4 <- 0x8007b7 +mem-write: 0x800113b8 <- 0xf46433 +mem-write: 0x800113bc <- 0xc0150513 +mem-write: 0x800113c0 <- 0x399793 +mem-write: 0x800113c4 <- 0x713 +mem-write: 0x800113c8 <- 0x2b9693 +mem-write: 0x800113cc <- 0xe6e6b3 +mem-write: 0x800113d0 <- 0xab0533 +mem-write: 0x800113d4 <- 0xfff68693 +mem-write: 0x800113d8 <- 0xe00813 +mem-write: 0x800113dc <- 0x15a4633 +mem-write: 0x800113e0 <- 0x150593 +mem-write: 0x800113e4 <- 0x14d86c63 +mem-write: 0x800113e8 <- 0x80015537 +mem-write: 0x800113ec <- 0x269693 +mem-write: 0x800113f0 <- 0x63c50513 +mem-write: 0x800113f4 <- 0xa686b3 +VXDRV: upload 1024 bytes to 0x800113f8 +mem-write: 0x800113f8 <- 0x6a683 +mem-write: 0x800113fc <- 0x68067 +mem-write: 0x80011400 <- 0xa4e933 +mem-write: 0x80011404 <- 0x6090c63 +mem-write: 0x80011408 <- 0x4048063 +mem-write: 0x8001140c <- 0x48513 +mem-write: 0x80011410 <- 0x4dc030ef +mem-write: 0x80011414 <- 0xff550713 +mem-write: 0x80011418 <- 0x1c00793 +mem-write: 0x8001141c <- 0x2e7cc63 +mem-write: 0x80011420 <- 0x1d00793 +mem-write: 0x80011424 <- 0xff850913 +mem-write: 0x80011428 <- 0x40e787b3 +mem-write: 0x8001142c <- 0x12494b3 +mem-write: 0x80011430 <- 0xf457b3 +mem-write: 0x80011434 <- 0x97e4b3 +mem-write: 0x80011438 <- 0x1241933 +mem-write: 0x8001143c <- 0xc0d00b13 +mem-write: 0x80011440 <- 0x40ab0b33 +mem-write: 0x80011444 <- 0xf3dff06f +mem-write: 0x80011448 <- 0x4a4030ef +mem-write: 0x8001144c <- 0x2050513 +mem-write: 0x80011450 <- 0xfc5ff06f +mem-write: 0x80011454 <- 0xfd850493 +mem-write: 0x80011458 <- 0x9414b3 +mem-write: 0x8001145c <- 0x913 +mem-write: 0x80011460 <- 0xfddff06f +mem-write: 0x80011464 <- 0xa4e933 +mem-write: 0x80011468 <- 0x2090263 +mem-write: 0x8001146c <- 0x50913 +mem-write: 0x80011470 <- 0x7ff00b13 +mem-write: 0x80011474 <- 0x300b93 +mem-write: 0x80011478 <- 0xf0dff06f +mem-write: 0x8001147c <- 0x493 +mem-write: 0x80011480 <- 0xb13 +mem-write: 0x80011484 <- 0x100b93 +mem-write: 0x80011488 <- 0xefdff06f +mem-write: 0x8001148c <- 0x493 +mem-write: 0x80011490 <- 0x7ff00b13 +mem-write: 0x80011494 <- 0x200b93 +mem-write: 0x80011498 <- 0xeedff06f +mem-write: 0x8001149c <- 0x13467b3 +mem-write: 0x800114a0 <- 0x6078e63 +mem-write: 0x800114a4 <- 0x4040063 +mem-write: 0x800114a8 <- 0x40513 +mem-write: 0x800114ac <- 0x440030ef +mem-write: 0x800114b0 <- 0xff550693 +mem-write: 0x800114b4 <- 0x1c00793 +mem-write: 0x800114b8 <- 0x2d7ce63 +mem-write: 0x800114bc <- 0x1d00713 +mem-write: 0x800114c0 <- 0xff850793 +mem-write: 0x800114c4 <- 0x40d70733 +mem-write: 0x800114c8 <- 0xf41433 +mem-write: 0x800114cc <- 0xe9d733 +mem-write: 0x800114d0 <- 0x876433 +mem-write: 0x800114d4 <- 0xf997b3 +mem-write: 0x800114d8 <- 0xc0d00713 +mem-write: 0x800114dc <- 0x40a70533 +mem-write: 0x800114e0 <- 0xee5ff06f +mem-write: 0x800114e4 <- 0x98513 +mem-write: 0x800114e8 <- 0x404030ef +mem-write: 0x800114ec <- 0x2050513 +mem-write: 0x800114f0 <- 0xfc1ff06f +mem-write: 0x800114f4 <- 0xfd850413 +mem-write: 0x800114f8 <- 0x899433 +mem-write: 0x800114fc <- 0x793 +mem-write: 0x80011500 <- 0xfd9ff06f +mem-write: 0x80011504 <- 0x13467b3 +mem-write: 0x80011508 <- 0x2078263 +mem-write: 0x8001150c <- 0x98793 +mem-write: 0x80011510 <- 0x7ff00513 +mem-write: 0x80011514 <- 0x300713 +mem-write: 0x80011518 <- 0xeb1ff06f +mem-write: 0x8001151c <- 0x413 +mem-write: 0x80011520 <- 0x513 +mem-write: 0x80011524 <- 0x100713 +mem-write: 0x80011528 <- 0xea1ff06f +mem-write: 0x8001152c <- 0x413 +mem-write: 0x80011530 <- 0x7ff00513 +mem-write: 0x80011534 <- 0x200713 +mem-write: 0x80011538 <- 0xe91ff06f +mem-write: 0x8001153c <- 0x10f37 +mem-write: 0x80011540 <- 0xffff0713 +mem-write: 0x80011544 <- 0x1095693 +mem-write: 0x80011548 <- 0x107d313 +mem-write: 0x8001154c <- 0xe97933 +mem-write: 0x80011550 <- 0xe7f7b3 +mem-write: 0x80011554 <- 0x32308b3 +mem-write: 0x80011558 <- 0x2f90833 +mem-write: 0x8001155c <- 0x2f68fb3 +mem-write: 0x80011560 <- 0x1f88eb3 +mem-write: 0x80011564 <- 0x1085893 +mem-write: 0x80011568 <- 0x1d888b3 +mem-write: 0x8001156c <- 0x2668e33 +mem-write: 0x80011570 <- 0x1f8f463 +mem-write: 0x80011574 <- 0x1ee0e33 +mem-write: 0x80011578 <- 0x108d293 +mem-write: 0x8001157c <- 0xe8f8b3 +mem-write: 0x80011580 <- 0xe87833 +mem-write: 0x80011584 <- 0x1045f13 +mem-write: 0x80011588 <- 0x1089893 +mem-write: 0x8001158c <- 0xe47433 +mem-write: 0x80011590 <- 0x10888b3 +mem-write: 0x80011594 <- 0x2868733 +mem-write: 0x80011598 <- 0x2890833 +mem-write: 0x8001159c <- 0x32f0933 +mem-write: 0x800115a0 <- 0xe90eb3 +mem-write: 0x800115a4 <- 0x1085913 +mem-write: 0x800115a8 <- 0x1d90933 +mem-write: 0x800115ac <- 0x3e686b3 +mem-write: 0x800115b0 <- 0xe97663 +mem-write: 0x800115b4 <- 0x10737 +mem-write: 0x800115b8 <- 0xe686b3 +mem-write: 0x800115bc <- 0x1095e93 +mem-write: 0x800115c0 <- 0xde8eb3 +mem-write: 0x800115c4 <- 0x106b7 +mem-write: 0x800115c8 <- 0xfff68f93 +mem-write: 0x800115cc <- 0x1f97933 +mem-write: 0x800115d0 <- 0x1f87833 +mem-write: 0x800115d4 <- 0x104d713 +mem-write: 0x800115d8 <- 0x1091913 +mem-write: 0x800115dc <- 0x1f4f4b3 +mem-write: 0x800115e0 <- 0x29783b3 +mem-write: 0x800115e4 <- 0x1090933 +mem-write: 0x800115e8 <- 0x12282b3 +mem-write: 0x800115ec <- 0x2930833 +mem-write: 0x800115f0 <- 0x2f707b3 +mem-write: 0x800115f4 <- 0x2e30fb3 +mem-write: 0x800115f8 <- 0xf80333 +mem-write: 0x800115fc <- 0x103d813 +mem-write: 0x80011600 <- 0x680833 +mem-write: 0x80011604 <- 0xf87463 +mem-write: 0x80011608 <- 0xdf8fb3 +mem-write: 0x8001160c <- 0x1085793 +mem-write: 0x80011610 <- 0x106b7 +mem-write: 0x80011614 <- 0x1f78fb3 +mem-write: 0x80011618 <- 0xfff68793 +mem-write: 0x8001161c <- 0xf87833 +mem-write: 0x80011620 <- 0xf3f7b3 +mem-write: 0x80011624 <- 0x29403b3 +mem-write: 0x80011628 <- 0x1081813 +mem-write: 0x8001162c <- 0xf80833 +mem-write: 0x80011630 <- 0x2870433 +mem-write: 0x80011634 <- 0x29f04b3 +mem-write: 0x80011638 <- 0x2ef0333 +mem-write: 0x8001163c <- 0x8484b3 +mem-write: 0x80011640 <- 0x103d713 +mem-write: 0x80011644 <- 0x9704b3 +mem-write: 0x80011648 <- 0x84f463 +mem-write: 0x8001164c <- 0xd30333 +mem-write: 0x80011650 <- 0x107b7 +mem-write: 0x80011654 <- 0xfff78793 +mem-write: 0x80011658 <- 0xf4f6b3 +mem-write: 0x8001165c <- 0x1069693 +mem-write: 0x80011660 <- 0xf3f7b3 +mem-write: 0x80011664 <- 0x5e0e33 +mem-write: 0x80011668 <- 0xf686b3 +mem-write: 0x8001166c <- 0x12e3933 +mem-write: 0x80011670 <- 0x1d686b3 +mem-write: 0x80011674 <- 0x1268733 +mem-write: 0x80011678 <- 0x10e0e33 +mem-write: 0x8001167c <- 0x10e3833 +mem-write: 0x80011680 <- 0x1f70f33 +mem-write: 0x80011684 <- 0x10f02b3 +mem-write: 0x80011688 <- 0x1d6b6b3 +mem-write: 0x8001168c <- 0x1273733 +mem-write: 0x80011690 <- 0xe6e733 +mem-write: 0x80011694 <- 0x102b833 +mem-write: 0x80011698 <- 0x104d493 +mem-write: 0x8001169c <- 0x1ff3fb3 +mem-write: 0x800116a0 <- 0x970733 +mem-write: 0x800116a4 <- 0x10fe833 +mem-write: 0x800116a8 <- 0x9e1793 +mem-write: 0x800116ac <- 0x1070733 +mem-write: 0x800116b0 <- 0x670733 +mem-write: 0x800116b4 <- 0x117e7b3 +mem-write: 0x800116b8 <- 0x971713 +mem-write: 0x800116bc <- 0xf037b3 +mem-write: 0x800116c0 <- 0x17e5e13 +mem-write: 0x800116c4 <- 0x172d413 +mem-write: 0x800116c8 <- 0x1c7e7b3 +mem-write: 0x800116cc <- 0x929293 +mem-write: 0x800116d0 <- 0x771693 +mem-write: 0x800116d4 <- 0x876433 +mem-write: 0x800116d8 <- 0x57e7b3 +mem-write: 0x800116dc <- 0x1006d463 +mem-write: 0x800116e0 <- 0x17d713 +mem-write: 0x800116e4 <- 0x17f793 +mem-write: 0x800116e8 <- 0xf767b3 +mem-write: 0x800116ec <- 0x1f41713 +mem-write: 0x800116f0 <- 0xe7e7b3 +mem-write: 0x800116f4 <- 0x145413 +mem-write: 0x800116f8 <- 0x3ff58693 +mem-write: 0x800116fc <- 0xed05863 +mem-write: 0x80011700 <- 0x77f713 +mem-write: 0x80011704 <- 0x2070063 +mem-write: 0x80011708 <- 0xf7f713 +mem-write: 0x8001170c <- 0x400513 +mem-write: 0x80011710 <- 0xa70a63 +mem-write: 0x80011714 <- 0x478713 +mem-write: 0x80011718 <- 0xf737b3 +mem-write: 0x8001171c <- 0xf40433 +mem-write: 0x80011720 <- 0x70793 +mem-write: 0x80011724 <- 0x741713 +mem-write: 0x80011728 <- 0x75a63 +mem-write: 0x8001172c <- 0xff000737 +mem-write: 0x80011730 <- 0xfff70713 +mem-write: 0x80011734 <- 0xe47433 +mem-write: 0x80011738 <- 0x40058693 +mem-write: 0x8001173c <- 0x7fe00713 +mem-write: 0x80011740 <- 0x16d74863 +mem-write: 0x80011744 <- 0x37d713 +mem-write: 0x80011748 <- 0x1d41793 +mem-write: 0x8001174c <- 0xe7e7b3 +mem-write: 0x80011750 <- 0x345413 +mem-write: 0x80011754 <- 0x1469713 +mem-write: 0x80011758 <- 0xc41413 +mem-write: 0x8001175c <- 0x7ff006b7 +mem-write: 0x80011760 <- 0xd77733 +mem-write: 0x80011764 <- 0xc45413 +mem-write: 0x80011768 <- 0x876433 +mem-write: 0x8001176c <- 0x1f61613 +mem-write: 0x80011770 <- 0x2c12083 +mem-write: 0x80011774 <- 0xc46733 +mem-write: 0x80011778 <- 0x2812403 +mem-write: 0x8001177c <- 0x2412483 +mem-write: 0x80011780 <- 0x2012903 +mem-write: 0x80011784 <- 0x1c12983 +mem-write: 0x80011788 <- 0x1812a03 +mem-write: 0x8001178c <- 0x1412a83 +mem-write: 0x80011790 <- 0x1012b03 +mem-write: 0x80011794 <- 0xc12b83 +mem-write: 0x80011798 <- 0x78513 +mem-write: 0x8001179c <- 0x70593 +mem-write: 0x800117a0 <- 0x3010113 +mem-write: 0x800117a4 <- 0x8067 +mem-write: 0x800117a8 <- 0xa0613 +mem-write: 0x800117ac <- 0x48413 +mem-write: 0x800117b0 <- 0x90793 +mem-write: 0x800117b4 <- 0xb8713 +mem-write: 0x800117b8 <- 0x200693 +mem-write: 0x800117bc <- 0xed70a63 +mem-write: 0x800117c0 <- 0x300693 +mem-write: 0x800117c4 <- 0xcd70c63 +mem-write: 0x800117c8 <- 0x100693 +mem-write: 0x800117cc <- 0xf2d716e3 +mem-write: 0x800117d0 <- 0x413 +mem-write: 0x800117d4 <- 0x793 +mem-write: 0x800117d8 <- 0x880006f +mem-write: 0x800117dc <- 0xa8613 +mem-write: 0x800117e0 <- 0xfd9ff06f +mem-write: 0x800117e4 <- 0x50593 +mem-write: 0x800117e8 <- 0xf11ff06f +mem-write: 0x800117ec <- 0x100513 +mem-write: 0x800117f0 <- 0x40d50533 +mem-write: 0x800117f4 <- 0x3800713 +VXDRV: upload 1024 bytes to 0x800117f8 +mem-write: 0x800117f8 <- 0xfca74ce3 +mem-write: 0x800117fc <- 0x1f00713 +mem-write: 0x80011800 <- 0x6a74463 +mem-write: 0x80011804 <- 0x41e58593 +mem-write: 0x80011808 <- 0xb41733 +mem-write: 0x8001180c <- 0xa7d6b3 +mem-write: 0x80011810 <- 0xb797b3 +mem-write: 0x80011814 <- 0xd76733 +mem-write: 0x80011818 <- 0xf037b3 +mem-write: 0x8001181c <- 0xf767b3 +mem-write: 0x80011820 <- 0xa45433 +mem-write: 0x80011824 <- 0x77f713 +mem-write: 0x80011828 <- 0x2070063 +mem-write: 0x8001182c <- 0xf7f713 +mem-write: 0x80011830 <- 0x400693 +mem-write: 0x80011834 <- 0xd70a63 +mem-write: 0x80011838 <- 0x478713 +mem-write: 0x8001183c <- 0xf737b3 +mem-write: 0x80011840 <- 0xf40433 +mem-write: 0x80011844 <- 0x70793 +mem-write: 0x80011848 <- 0x841713 +mem-write: 0x8001184c <- 0x6074a63 +mem-write: 0x80011850 <- 0x1d41713 +mem-write: 0x80011854 <- 0x37d793 +mem-write: 0x80011858 <- 0xf767b3 +mem-write: 0x8001185c <- 0x345413 +mem-write: 0x80011860 <- 0x693 +mem-write: 0x80011864 <- 0xef1ff06f +mem-write: 0x80011868 <- 0xfe100713 +mem-write: 0x8001186c <- 0x40d70733 +mem-write: 0x80011870 <- 0x2000813 +mem-write: 0x80011874 <- 0xe45733 +mem-write: 0x80011878 <- 0x693 +mem-write: 0x8001187c <- 0x1050663 +mem-write: 0x80011880 <- 0x43e58593 +mem-write: 0x80011884 <- 0xb416b3 +mem-write: 0x80011888 <- 0xf6e7b3 +mem-write: 0x8001188c <- 0xf037b3 +mem-write: 0x80011890 <- 0xf767b3 +mem-write: 0x80011894 <- 0x413 +mem-write: 0x80011898 <- 0xf8dff06f +mem-write: 0x8001189c <- 0x80437 +mem-write: 0x800118a0 <- 0x793 +mem-write: 0x800118a4 <- 0x7ff00693 +mem-write: 0x800118a8 <- 0x613 +mem-write: 0x800118ac <- 0xea9ff06f +mem-write: 0x800118b0 <- 0x413 +mem-write: 0x800118b4 <- 0x793 +mem-write: 0x800118b8 <- 0x7ff00693 +mem-write: 0x800118bc <- 0xe99ff06f +mem-write: 0x800118c0 <- 0x413 +mem-write: 0x800118c4 <- 0x793 +mem-write: 0x800118c8 <- 0x100693 +mem-write: 0x800118cc <- 0xe89ff06f +mem-write: 0x800118d0 <- 0xc52783 +mem-write: 0x800118d4 <- 0x5af03 +mem-write: 0x800118d8 <- 0x45af83 +mem-write: 0x800118dc <- 0x85a283 +mem-write: 0x800118e0 <- 0xc5a583 +mem-write: 0x800118e4 <- 0x8737 +mem-write: 0x800118e8 <- 0x107d693 +mem-write: 0x800118ec <- 0xfff70713 +mem-write: 0x800118f0 <- 0x1079813 +mem-write: 0x800118f4 <- 0x1059e93 +mem-write: 0x800118f8 <- 0x1f7d613 +mem-write: 0x800118fc <- 0xe6f6b3 +mem-write: 0x80011900 <- 0x105d793 +mem-write: 0x80011904 <- 0x52883 +mem-write: 0x80011908 <- 0x452303 +mem-write: 0x8001190c <- 0x852e03 +mem-write: 0x80011910 <- 0xff010113 +mem-write: 0x80011914 <- 0x1085813 +mem-write: 0x80011918 <- 0x10ede93 +mem-write: 0x8001191c <- 0xe7f7b3 +mem-write: 0x80011920 <- 0x1f5d593 +mem-write: 0x80011924 <- 0x2e69063 +mem-write: 0x80011928 <- 0x68e733 +mem-write: 0x8001192c <- 0x1c76733 +mem-write: 0x80011930 <- 0x1076733 +mem-write: 0x80011934 <- 0x100513 +mem-write: 0x80011938 <- 0x4071a63 +mem-write: 0x8001193c <- 0x4d79863 +mem-write: 0x80011940 <- 0x80006f +mem-write: 0x80011944 <- 0xe79c63 +mem-write: 0x80011948 <- 0x1ff6733 +mem-write: 0x8001194c <- 0x576733 +mem-write: 0x80011950 <- 0x1d76733 +mem-write: 0x80011954 <- 0x100513 +mem-write: 0x80011958 <- 0x2071a63 +mem-write: 0x8001195c <- 0x100513 +mem-write: 0x80011960 <- 0x2d79663 +mem-write: 0x80011964 <- 0x3e89463 +mem-write: 0x80011968 <- 0x3f31263 +mem-write: 0x8001196c <- 0x25e1063 +mem-write: 0x80011970 <- 0x1d81e63 +mem-write: 0x80011974 <- 0x2b60063 +mem-write: 0x80011978 <- 0x79a63 +mem-write: 0x8001197c <- 0x68e533 +mem-write: 0x80011980 <- 0x1c56533 +mem-write: 0x80011984 <- 0x1056533 +mem-write: 0x80011988 <- 0xa03533 +mem-write: 0x8001198c <- 0x1010113 +mem-write: 0x80011990 <- 0x8067 +mem-write: 0x80011994 <- 0x513 +mem-write: 0x80011998 <- 0xff5ff06f +mem-write: 0x8001199c <- 0x52f83 +mem-write: 0x800119a0 <- 0x452803 +mem-write: 0x800119a4 <- 0x852e03 +mem-write: 0x800119a8 <- 0xc52503 +mem-write: 0x800119ac <- 0xc5a683 +mem-write: 0x800119b0 <- 0x87b7 +mem-write: 0x800119b4 <- 0x1055613 +mem-write: 0x800119b8 <- 0xfff78793 +mem-write: 0x800119bc <- 0x1069313 +mem-write: 0x800119c0 <- 0x106d713 +mem-write: 0x800119c4 <- 0x5a283 +mem-write: 0x800119c8 <- 0x45a883 +mem-write: 0x800119cc <- 0x85ae83 +mem-write: 0x800119d0 <- 0xf67633 +mem-write: 0x800119d4 <- 0x1051593 +mem-write: 0x800119d8 <- 0xff010113 +mem-write: 0x800119dc <- 0x105d593 +mem-write: 0x800119e0 <- 0x1f55513 +mem-write: 0x800119e4 <- 0x1035313 +mem-write: 0x800119e8 <- 0xf77733 +mem-write: 0x800119ec <- 0x1f6d693 +mem-write: 0x800119f0 <- 0xf61e63 +mem-write: 0x800119f4 <- 0x10fe7b3 +mem-write: 0x800119f8 <- 0x1c7e7b3 +mem-write: 0x800119fc <- 0xb7e7b3 +mem-write: 0x80011a00 <- 0xc078863 +mem-write: 0x80011a04 <- 0xffe00513 +mem-write: 0x80011a08 <- 0x640006f +mem-write: 0x80011a0c <- 0xf71a63 +mem-write: 0x80011a10 <- 0x112e7b3 +mem-write: 0x80011a14 <- 0x1d7e7b3 +mem-write: 0x80011a18 <- 0x67e7b3 +mem-write: 0x80011a1c <- 0xfe0794e3 +mem-write: 0x80011a20 <- 0xa061a63 +mem-write: 0x80011a24 <- 0x10fe7b3 +mem-write: 0x80011a28 <- 0x1c7e7b3 +mem-write: 0x80011a2c <- 0xb7e7b3 +mem-write: 0x80011a30 <- 0x17b793 +mem-write: 0x80011a34 <- 0x71a63 +mem-write: 0x80011a38 <- 0x112ef33 +mem-write: 0x80011a3c <- 0x1df6f33 +mem-write: 0x80011a40 <- 0x6f6f33 +mem-write: 0x80011a44 <- 0x60f0a63 +mem-write: 0x80011a48 <- 0x79c63 +mem-write: 0x80011a4c <- 0xa69463 +mem-write: 0x80011a50 <- 0x2c75263 +mem-write: 0x80011a54 <- 0x4050e63 +mem-write: 0x80011a58 <- 0xfff00513 +mem-write: 0x80011a5c <- 0x100006f +mem-write: 0x80011a60 <- 0xfff00513 +mem-write: 0x80011a64 <- 0x68463 +mem-write: 0x80011a68 <- 0x68513 +mem-write: 0x80011a6c <- 0x1010113 +mem-write: 0x80011a70 <- 0x8067 +mem-write: 0x80011a74 <- 0xe65663 +mem-write: 0x80011a78 <- 0xfe051ae3 +mem-write: 0x80011a7c <- 0xfddff06f +mem-write: 0x80011a80 <- 0xfcb36ae3 +mem-write: 0x80011a84 <- 0x2659e63 +mem-write: 0x80011a88 <- 0xfdcee6e3 +mem-write: 0x80011a8c <- 0x3de1e63 +mem-write: 0x80011a90 <- 0xfd08e2e3 +mem-write: 0x80011a94 <- 0x1181463 +mem-write: 0x80011a98 <- 0xfbf2eee3 +mem-write: 0x80011a9c <- 0xfd186ee3 +mem-write: 0x80011aa0 <- 0x1181463 +mem-write: 0x80011aa4 <- 0xfc5feae3 +mem-write: 0x80011aa8 <- 0x513 +mem-write: 0x80011aac <- 0xfc1ff06f +mem-write: 0x80011ab0 <- 0x100513 +mem-write: 0x80011ab4 <- 0xfb9ff06f +mem-write: 0x80011ab8 <- 0xfe0798e3 +mem-write: 0x80011abc <- 0xf99ff06f +mem-write: 0x80011ac0 <- 0xfa65ece3 +mem-write: 0x80011ac4 <- 0xfe5ff06f +mem-write: 0x80011ac8 <- 0xfbde68e3 +mem-write: 0x80011acc <- 0xfddff06f +mem-write: 0x80011ad0 <- 0xf4c700e3 +mem-write: 0x80011ad4 <- 0xf6071ce3 +mem-write: 0x80011ad8 <- 0x793 +mem-write: 0x80011adc <- 0xf5dff06f +mem-write: 0x80011ae0 <- 0x52f83 +mem-write: 0x80011ae4 <- 0x452803 +mem-write: 0x80011ae8 <- 0x852e03 +mem-write: 0x80011aec <- 0xc52503 +mem-write: 0x80011af0 <- 0xc5a683 +mem-write: 0x80011af4 <- 0x87b7 +mem-write: 0x80011af8 <- 0x1055613 +mem-write: 0x80011afc <- 0xfff78793 +mem-write: 0x80011b00 <- 0x1069313 +mem-write: 0x80011b04 <- 0x106d713 +mem-write: 0x80011b08 <- 0x5a283 +mem-write: 0x80011b0c <- 0x45a883 +mem-write: 0x80011b10 <- 0x85ae83 +mem-write: 0x80011b14 <- 0xf67633 +mem-write: 0x80011b18 <- 0x1051593 +mem-write: 0x80011b1c <- 0xff010113 +mem-write: 0x80011b20 <- 0x105d593 +mem-write: 0x80011b24 <- 0x1f55513 +mem-write: 0x80011b28 <- 0x1035313 +mem-write: 0x80011b2c <- 0xf77733 +mem-write: 0x80011b30 <- 0x1f6d693 +mem-write: 0x80011b34 <- 0xf61e63 +mem-write: 0x80011b38 <- 0x10fe7b3 +mem-write: 0x80011b3c <- 0x1c7e7b3 +mem-write: 0x80011b40 <- 0xb7e7b3 +mem-write: 0x80011b44 <- 0xc078863 +mem-write: 0x80011b48 <- 0x200513 +mem-write: 0x80011b4c <- 0x640006f +mem-write: 0x80011b50 <- 0xf71a63 +mem-write: 0x80011b54 <- 0x112e7b3 +mem-write: 0x80011b58 <- 0x1d7e7b3 +mem-write: 0x80011b5c <- 0x67e7b3 +mem-write: 0x80011b60 <- 0xfe0794e3 +mem-write: 0x80011b64 <- 0xa061a63 +mem-write: 0x80011b68 <- 0x10fe7b3 +mem-write: 0x80011b6c <- 0x1c7e7b3 +mem-write: 0x80011b70 <- 0xb7e7b3 +mem-write: 0x80011b74 <- 0x17b793 +mem-write: 0x80011b78 <- 0x71a63 +mem-write: 0x80011b7c <- 0x112ef33 +mem-write: 0x80011b80 <- 0x1df6f33 +mem-write: 0x80011b84 <- 0x6f6f33 +mem-write: 0x80011b88 <- 0x60f0a63 +mem-write: 0x80011b8c <- 0x79c63 +mem-write: 0x80011b90 <- 0xa69463 +mem-write: 0x80011b94 <- 0x2c75263 +mem-write: 0x80011b98 <- 0x4050e63 +mem-write: 0x80011b9c <- 0xfff00513 +mem-write: 0x80011ba0 <- 0x100006f +mem-write: 0x80011ba4 <- 0xfff00513 +mem-write: 0x80011ba8 <- 0x68463 +mem-write: 0x80011bac <- 0x68513 +mem-write: 0x80011bb0 <- 0x1010113 +mem-write: 0x80011bb4 <- 0x8067 +mem-write: 0x80011bb8 <- 0xe65663 +mem-write: 0x80011bbc <- 0xfe051ae3 +mem-write: 0x80011bc0 <- 0xfddff06f +mem-write: 0x80011bc4 <- 0xfcb36ae3 +mem-write: 0x80011bc8 <- 0x2659e63 +mem-write: 0x80011bcc <- 0xfdcee6e3 +mem-write: 0x80011bd0 <- 0x3de1e63 +mem-write: 0x80011bd4 <- 0xfd08e2e3 +mem-write: 0x80011bd8 <- 0x1181463 +mem-write: 0x80011bdc <- 0xfbf2eee3 +mem-write: 0x80011be0 <- 0xfd186ee3 +mem-write: 0x80011be4 <- 0x1181463 +mem-write: 0x80011be8 <- 0xfc5feae3 +mem-write: 0x80011bec <- 0x513 +mem-write: 0x80011bf0 <- 0xfc1ff06f +mem-write: 0x80011bf4 <- 0x100513 +VXDRV: upload 1023 bytes to 0x80011bf8 +mem-write: 0x80011bf8 <- 0xfb9ff06f +mem-write: 0x80011bfc <- 0xfe0798e3 +mem-write: 0x80011c00 <- 0xf99ff06f +mem-write: 0x80011c04 <- 0xfa65ece3 +mem-write: 0x80011c08 <- 0xfe5ff06f +mem-write: 0x80011c0c <- 0xfbde68e3 +mem-write: 0x80011c10 <- 0xfddff06f +mem-write: 0x80011c14 <- 0xf4c700e3 +mem-write: 0x80011c18 <- 0xf6071ce3 +mem-write: 0x80011c1c <- 0x793 +mem-write: 0x80011c20 <- 0xf5dff06f +mem-write: 0x80011c24 <- 0xf4010113 +mem-write: 0x80011c28 <- 0xa912a23 +mem-write: 0x80011c2c <- 0xc5a483 +mem-write: 0x80011c30 <- 0x5a683 +mem-write: 0x80011c34 <- 0x45a783 +mem-write: 0x80011c38 <- 0xa12423 +mem-write: 0x80011c3c <- 0x85a503 +mem-write: 0x80011c40 <- 0x1049713 +mem-write: 0x80011c44 <- 0xb212823 +mem-write: 0x80011c48 <- 0xb312623 +mem-write: 0x80011c4c <- 0xc62903 +mem-write: 0x80011c50 <- 0x62983 +mem-write: 0x80011c54 <- 0xb412423 +mem-write: 0x80011c58 <- 0xb512223 +mem-write: 0x80011c5c <- 0x862a03 +mem-write: 0x80011c60 <- 0x462a83 +mem-write: 0x80011c64 <- 0x8637 +mem-write: 0x80011c68 <- 0xa812c23 +mem-write: 0x80011c6c <- 0x1075713 +mem-write: 0x80011c70 <- 0x104d413 +mem-write: 0x80011c74 <- 0xfff60613 +mem-write: 0x80011c78 <- 0x6912623 +mem-write: 0x80011c7c <- 0xa112e23 +mem-write: 0x80011c80 <- 0xb612023 +mem-write: 0x80011c84 <- 0x9712e23 +mem-write: 0x80011c88 <- 0x9812c23 +mem-write: 0x80011c8c <- 0x9912a23 +mem-write: 0x80011c90 <- 0x9a12823 +mem-write: 0x80011c94 <- 0x9b12623 +mem-write: 0x80011c98 <- 0x6d12023 +mem-write: 0x80011c9c <- 0x6f12223 +mem-write: 0x80011ca0 <- 0x6a12423 +mem-write: 0x80011ca4 <- 0x2d12823 +mem-write: 0x80011ca8 <- 0x2f12a23 +mem-write: 0x80011cac <- 0x2a12c23 +mem-write: 0x80011cb0 <- 0x2e12e23 +mem-write: 0x80011cb4 <- 0xc47433 +mem-write: 0x80011cb8 <- 0x1f4d493 +mem-write: 0x80011cbc <- 0x12040863 +mem-write: 0x80011cc0 <- 0x24c40663 +mem-write: 0x80011cc4 <- 0x107b7 +mem-write: 0x80011cc8 <- 0xf767b3 +mem-write: 0x80011ccc <- 0x2f12e23 +mem-write: 0x80011cd0 <- 0x3010613 +mem-write: 0x80011cd4 <- 0x3c10793 +mem-write: 0x80011cd8 <- 0x7a703 +mem-write: 0x80011cdc <- 0xffc7a683 +mem-write: 0x80011ce0 <- 0xffc78793 +mem-write: 0x80011ce4 <- 0x371713 +mem-write: 0x80011ce8 <- 0x1d6d693 +mem-write: 0x80011cec <- 0xd76733 +mem-write: 0x80011cf0 <- 0xe7a223 +mem-write: 0x80011cf4 <- 0xfef612e3 +mem-write: 0x80011cf8 <- 0x3012783 +mem-write: 0x80011cfc <- 0xffffc537 +mem-write: 0x80011d00 <- 0x150513 +mem-write: 0x80011d04 <- 0x379793 +mem-write: 0x80011d08 <- 0x2f12823 +mem-write: 0x80011d0c <- 0xa40433 +mem-write: 0x80011d10 <- 0xb13 +mem-write: 0x80011d14 <- 0x1091513 +mem-write: 0x80011d18 <- 0x8737 +mem-write: 0x80011d1c <- 0x1095793 +mem-write: 0x80011d20 <- 0x1055513 +mem-write: 0x80011d24 <- 0xfff70713 +mem-write: 0x80011d28 <- 0x7212623 +mem-write: 0x80011d2c <- 0x7312023 +mem-write: 0x80011d30 <- 0x7512223 +mem-write: 0x80011d34 <- 0x7412423 +mem-write: 0x80011d38 <- 0x5312023 +mem-write: 0x80011d3c <- 0x5512223 +mem-write: 0x80011d40 <- 0x5412423 +mem-write: 0x80011d44 <- 0x4a12623 +mem-write: 0x80011d48 <- 0xe7f7b3 +mem-write: 0x80011d4c <- 0x1f95913 +mem-write: 0x80011d50 <- 0x1e078263 +mem-write: 0x80011d54 <- 0x30e78063 +mem-write: 0x80011d58 <- 0x10a37 +mem-write: 0x80011d5c <- 0x1456a33 +mem-write: 0x80011d60 <- 0x5412623 +mem-write: 0x80011d64 <- 0x4010593 +mem-write: 0x80011d68 <- 0x4c10713 +mem-write: 0x80011d6c <- 0x72683 +mem-write: 0x80011d70 <- 0xffc72603 +mem-write: 0x80011d74 <- 0xffc70713 +mem-write: 0x80011d78 <- 0x369693 +mem-write: 0x80011d7c <- 0x1d65613 +mem-write: 0x80011d80 <- 0xc6e6b3 +mem-write: 0x80011d84 <- 0xd72223 +mem-write: 0x80011d88 <- 0xfee592e3 +mem-write: 0x80011d8c <- 0x4012703 +mem-write: 0x80011d90 <- 0xffffc537 +mem-write: 0x80011d94 <- 0x150513 +mem-write: 0x80011d98 <- 0x371713 +mem-write: 0x80011d9c <- 0x4e12023 +mem-write: 0x80011da0 <- 0xa787b3 +mem-write: 0x80011da4 <- 0x713 +mem-write: 0x80011da8 <- 0x8787b3 +mem-write: 0x80011dac <- 0xf12e23 +mem-write: 0x80011db0 <- 0x178793 +mem-write: 0x80011db4 <- 0xf12c23 +mem-write: 0x80011db8 <- 0x2b1793 +mem-write: 0x80011dbc <- 0x124c6b3 +mem-write: 0x80011dc0 <- 0xe7e7b3 +mem-write: 0x80011dc4 <- 0xd12623 +mem-write: 0x80011dc8 <- 0xfff78793 +mem-write: 0x80011dcc <- 0xe00693 +mem-write: 0x80011dd0 <- 0x2af6e663 +mem-write: 0x80011dd4 <- 0x800156b7 +mem-write: 0x80011dd8 <- 0x279793 +mem-write: 0x80011ddc <- 0x67868693 +mem-write: 0x80011de0 <- 0xd787b3 +mem-write: 0x80011de4 <- 0x7a783 +mem-write: 0x80011de8 <- 0x78067 +mem-write: 0x80011dec <- 0xd7e633 +mem-write: 0x80011df0 <- 0xa66633 +mem-write: 0x80011df4 <- 0xe66633 +mem-write: 0x80011df8 <- 0x12060863 +mem-write: 0x80011dfc <- 0x6070063 +mem-write: 0x80011e00 <- 0x70513 +mem-write: 0x80011e04 <- 0x2e9020ef +mem-write: 0x80011e08 <- 0xff450693 +mem-write: 0x80011e0c <- 0x4056d793 +mem-write: 0x80011e10 <- 0x1f6f693 +mem-write: 0x80011e14 <- 0x6068e63 +mem-write: 0x80011e18 <- 0xffc00713 +mem-write: 0x80011e1c <- 0x2e78733 +mem-write: 0x80011e20 <- 0x3010313 +mem-write: 0x80011e24 <- 0x2000813 +mem-write: 0x80011e28 <- 0x279593 +mem-write: 0x80011e2c <- 0x40d80833 +mem-write: 0x80011e30 <- 0xc70713 +mem-write: 0x80011e34 <- 0xe30733 +mem-write: 0x80011e38 <- 0x8e31463 +mem-write: 0x80011e3c <- 0x8010713 +mem-write: 0x80011e40 <- 0xb705b3 +mem-write: 0x80011e44 <- 0x3012703 +mem-write: 0x80011e48 <- 0xfff78793 +mem-write: 0x80011e4c <- 0xd716b3 +mem-write: 0x80011e50 <- 0xfad5a823 +mem-write: 0x80011e54 <- 0xfff00693 +mem-write: 0x80011e58 <- 0xa00006f +mem-write: 0x80011e5c <- 0x50863 +mem-write: 0x80011e60 <- 0x28d020ef +mem-write: 0x80011e64 <- 0x2050513 +mem-write: 0x80011e68 <- 0xfa1ff06f +mem-write: 0x80011e6c <- 0x78a63 +mem-write: 0x80011e70 <- 0x78513 +mem-write: 0x80011e74 <- 0x279020ef +mem-write: 0x80011e78 <- 0x4050513 +mem-write: 0x80011e7c <- 0xf8dff06f +mem-write: 0x80011e80 <- 0x68513 +mem-write: 0x80011e84 <- 0x269020ef +mem-write: 0x80011e88 <- 0x6050513 +mem-write: 0x80011e8c <- 0xf7dff06f +mem-write: 0x80011e90 <- 0xffc00613 +mem-write: 0x80011e94 <- 0x2c78633 +mem-write: 0x80011e98 <- 0x3c10713 +mem-write: 0x80011e9c <- 0x300693 +mem-write: 0x80011ea0 <- 0xc705b3 +mem-write: 0x80011ea4 <- 0x5a583 +mem-write: 0x80011ea8 <- 0xfff68693 +mem-write: 0x80011eac <- 0xffc70713 +mem-write: 0x80011eb0 <- 0xb72223 +mem-write: 0x80011eb4 <- 0xfef6d6e3 +mem-write: 0x80011eb8 <- 0xfff78793 +mem-write: 0x80011ebc <- 0xf99ff06f +mem-write: 0x80011ec0 <- 0xffc72603 +mem-write: 0x80011ec4 <- 0x72883 +mem-write: 0x80011ec8 <- 0xb70e33 +mem-write: 0x80011ecc <- 0x1065633 +mem-write: 0x80011ed0 <- 0xd898b3 +mem-write: 0x80011ed4 <- 0x1166633 +mem-write: 0x80011ed8 <- 0xce2023 +mem-write: 0x80011edc <- 0xffc70713 +mem-write: 0x80011ee0 <- 0xf59ff06f +mem-write: 0x80011ee4 <- 0x279713 +mem-write: 0x80011ee8 <- 0x3010613 +mem-write: 0x80011eec <- 0xe60733 +mem-write: 0x80011ef0 <- 0x72023 +mem-write: 0x80011ef4 <- 0xfff78793 +mem-write: 0x80011ef8 <- 0xfed796e3 +mem-write: 0x80011efc <- 0xffffc437 +mem-write: 0x80011f00 <- 0x1140413 +mem-write: 0x80011f04 <- 0x40a40433 +mem-write: 0x80011f08 <- 0xe09ff06f +mem-write: 0x80011f0c <- 0xd7e7b3 +mem-write: 0x80011f10 <- 0xa7e7b3 +mem-write: 0x80011f14 <- 0xe7e7b3 +mem-write: 0x80011f18 <- 0x300b13 +mem-write: 0x80011f1c <- 0xde079ce3 +mem-write: 0x80011f20 <- 0x200b13 +mem-write: 0x80011f24 <- 0xdf1ff06f +mem-write: 0x80011f28 <- 0x413 +mem-write: 0x80011f2c <- 0x100b13 +mem-write: 0x80011f30 <- 0xde5ff06f +mem-write: 0x80011f34 <- 0x159e7b3 +mem-write: 0x80011f38 <- 0x147e7b3 +mem-write: 0x80011f3c <- 0xa7e7b3 +mem-write: 0x80011f40 <- 0x12078863 +mem-write: 0x80011f44 <- 0x4050e63 +mem-write: 0x80011f48 <- 0x1a5020ef +mem-write: 0x80011f4c <- 0xff450693 +mem-write: 0x80011f50 <- 0x4056d793 +mem-write: 0x80011f54 <- 0x1f6f693 +mem-write: 0x80011f58 <- 0x8068063 +mem-write: 0x80011f5c <- 0xffc00713 +mem-write: 0x80011f60 <- 0x2e78733 +mem-write: 0x80011f64 <- 0x4010313 +mem-write: 0x80011f68 <- 0x2000813 +mem-write: 0x80011f6c <- 0x279593 +mem-write: 0x80011f70 <- 0x40d80833 +mem-write: 0x80011f74 <- 0xc70713 +mem-write: 0x80011f78 <- 0xe30733 +mem-write: 0x80011f7c <- 0x8e31663 +mem-write: 0x80011f80 <- 0x8010713 +mem-write: 0x80011f84 <- 0xb705b3 +mem-write: 0x80011f88 <- 0x4012703 +mem-write: 0x80011f8c <- 0xfff78793 +mem-write: 0x80011f90 <- 0xd716b3 +mem-write: 0x80011f94 <- 0xfcd5a023 +mem-write: 0x80011f98 <- 0xfff00693 +mem-write: 0x80011f9c <- 0xa40006f +mem-write: 0x80011fa0 <- 0xa0a63 +mem-write: 0x80011fa4 <- 0xa0513 +mem-write: 0x80011fa8 <- 0x145020ef +mem-write: 0x80011fac <- 0x2050513 +mem-write: 0x80011fb0 <- 0xf9dff06f +mem-write: 0x80011fb4 <- 0xa8a63 +mem-write: 0x80011fb8 <- 0xa8513 +mem-write: 0x80011fbc <- 0x131020ef +mem-write: 0x80011fc0 <- 0x4050513 +mem-write: 0x80011fc4 <- 0xf89ff06f +mem-write: 0x80011fc8 <- 0x98513 +mem-write: 0x80011fcc <- 0x121020ef +mem-write: 0x80011fd0 <- 0x6050513 +mem-write: 0x80011fd4 <- 0xf79ff06f +mem-write: 0x80011fd8 <- 0xffc00613 +mem-write: 0x80011fdc <- 0x2c78633 +mem-write: 0x80011fe0 <- 0x4c10713 +mem-write: 0x80011fe4 <- 0x300693 +mem-write: 0x80011fe8 <- 0xc705b3 +mem-write: 0x80011fec <- 0x5a583 +mem-write: 0x80011ff0 <- 0xfff68693 +mem-write: 0x80011ff4 <- 0xc70713 +VXDRV: upload 1024 bytes to 0x80011ff7 +mem-write: 0x80011ff7 <- 0xb72223ff +mem-write: 0x80011ffb <- 0xf6d6e300 +mem-write: 0x80011fff <- 0xf78793fe +mem-write: 0x80012003 <- 0x5ff06fff +mem-write: 0x80012007 <- 0xc72603f9 +mem-write: 0x8001200b <- 0x72883ff +mem-write: 0x8001200f <- 0xb70e3300 +mem-write: 0x80012013 <- 0x6563300 +mem-write: 0x80012017 <- 0xd898b301 +mem-write: 0x8001201b <- 0x16663300 +mem-write: 0x8001201f <- 0xce202301 +mem-write: 0x80012023 <- 0xc7071300 +mem-write: 0x80012027 <- 0x5ff06fff +mem-write: 0x8001202b <- 0x279713f5 +mem-write: 0x8001202f <- 0x1061300 +mem-write: 0x80012033 <- 0xe6073304 +mem-write: 0x80012037 <- 0x7202300 +mem-write: 0x8001203b <- 0xf7879300 +mem-write: 0x8001203f <- 0xd796e3ff +mem-write: 0x80012043 <- 0xffc7b7fe +mem-write: 0x80012047 <- 0x178793ff +mem-write: 0x8001204b <- 0xa787b301 +mem-write: 0x8001204f <- 0x5ff06f40 +mem-write: 0x80012053 <- 0x59e9b3d5 +mem-write: 0x80012057 <- 0x49ea3301 +mem-write: 0x8001205b <- 0xaa6a3301 +mem-write: 0x8001205f <- 0x30071300 +mem-write: 0x80012063 <- 0xa12e300 +mem-write: 0x80012067 <- 0x200713d4 +mem-write: 0x8001206b <- 0xdff06f00 +mem-write: 0x8001206f <- 0x793d3 +mem-write: 0x80012073 <- 0x10071300 +mem-write: 0x80012077 <- 0x1ff06f00 +mem-write: 0x8001207b <- 0x12703d3 +mem-write: 0x8001207f <- 0x12e0303 +mem-write: 0x80012083 <- 0x1053704 +mem-write: 0x80012087 <- 0xf5069300 +mem-write: 0x8001208b <- 0x75f93ff +mem-write: 0x8001208f <- 0xe5a9301 +mem-write: 0x80012093 <- 0xd7773301 +mem-write: 0x80012097 <- 0xde7e3300 +mem-write: 0x8001209b <- 0xea87b300 +mem-write: 0x8001209f <- 0xee063302 +mem-write: 0x800120a3 <- 0xcf883302 +mem-write: 0x800120a7 <- 0x785b303 +mem-write: 0x800120ab <- 0x6579301 +mem-write: 0x800120af <- 0xb787b301 +mem-write: 0x800120b3 <- 0x5f8bb300 +mem-write: 0x800120b7 <- 0x7f46303 +mem-write: 0x800120bb <- 0xab8bb301 +mem-write: 0x800120bf <- 0x412f0300 +mem-write: 0x800120c3 <- 0x7d99304 +mem-write: 0x800120c7 <- 0xd7f7b301 +mem-write: 0x800120cb <- 0xd6763300 +mem-write: 0x800120cf <- 0x7979300 +mem-write: 0x800120d3 <- 0xc787b301 +mem-write: 0x800120d7 <- 0xf549300 +mem-write: 0x800120db <- 0xdf7f3301 +mem-write: 0x800120df <- 0xef06b300 +mem-write: 0x800120e3 <- 0xf1202302 +mem-write: 0x800120e7 <- 0xf1202302 +mem-write: 0x800120eb <- 0xef863306 +mem-write: 0x800120ef <- 0xe487b303 +mem-write: 0x800120f3 <- 0xc7853302 +mem-write: 0x800120f7 <- 0x6d79300 +mem-write: 0x800120fb <- 0xa787b301 +mem-write: 0x800120ff <- 0x9f8b3300 +mem-write: 0x80012103 <- 0xc7f66302 +mem-write: 0x80012107 <- 0x1063700 +mem-write: 0x8001210b <- 0xcb0b3300 +mem-write: 0x8001210f <- 0x1063700 +mem-write: 0x80012113 <- 0xf6059300 +mem-write: 0x80012117 <- 0xb7f533ff +mem-write: 0x8001211b <- 0x7d29300 +mem-write: 0x8001211f <- 0x41278301 +mem-write: 0x80012123 <- 0xb6f6b303 +mem-write: 0x80012127 <- 0x5151300 +mem-write: 0x8001212b <- 0x7d91301 +mem-write: 0x8001212f <- 0xb7f5b301 +mem-write: 0x80012133 <- 0xba87b300 +mem-write: 0x80012137 <- 0xd5053302 +mem-write: 0x8001213b <- 0xa989b300 +mem-write: 0x8001213f <- 0xc586b300 +mem-write: 0x80012143 <- 0xc9033303 +mem-write: 0x80012147 <- 0x67883303 +mem-write: 0x8001214b <- 0x6d79300 +mem-write: 0x8001214f <- 0x787b301 +mem-write: 0x80012153 <- 0x2a88b301 +mem-write: 0x80012157 <- 0x67f46303 +mem-write: 0x8001215b <- 0xc888b300 +mem-write: 0x8001215f <- 0x1033700 +mem-write: 0x80012163 <- 0xf3061300 +mem-write: 0x80012167 <- 0x7da13ff +mem-write: 0x8001216b <- 0xc7f83301 +mem-write: 0x8001216f <- 0xc6f6b300 +mem-write: 0x80012173 <- 0x1a0a3300 +mem-write: 0x80012177 <- 0x8181301 +mem-write: 0x8001217b <- 0xe588b301 +mem-write: 0x8001217f <- 0xd8083303 +mem-write: 0x80012183 <- 0xe9063300 +mem-write: 0x80012187 <- 0x8d69303 +mem-write: 0x8001218b <- 0xb487b301 +mem-write: 0x8001218f <- 0xc787b302 +mem-write: 0x80012193 <- 0xf687b300 +mem-write: 0x80012197 <- 0x248eb300 +mem-write: 0x8001219b <- 0xc7f46303 +mem-write: 0x8001219f <- 0x6e8eb300 +mem-write: 0x800121a3 <- 0x7d69300 +mem-write: 0x800121a7 <- 0xd686b301 +mem-write: 0x800121ab <- 0x1043701 +mem-write: 0x800121af <- 0x812e8300 +mem-write: 0x800121b3 <- 0xf4061304 +mem-write: 0x800121b7 <- 0xd12223ff +mem-write: 0x800121bb <- 0xc7f6b302 +mem-write: 0x800121bf <- 0xc8f8b300 +mem-write: 0x800121c3 <- 0xed39300 +mem-write: 0x800121c7 <- 0x6969301 +mem-write: 0x800121cb <- 0xcefeb301 +mem-write: 0x800121cf <- 0xee833300 +mem-write: 0x800121d3 <- 0x1686b302 +mem-write: 0x800121d7 <- 0xdf8c3301 +mem-write: 0x800121db <- 0xe388b303 +mem-write: 0x800121df <- 0x8887b302 +mem-write: 0x800121e3 <- 0x3589301 +mem-write: 0x800121e7 <- 0xf888b301 +mem-write: 0x800121eb <- 0x7f863300 +mem-write: 0x800121ef <- 0x88f46302 +mem-write: 0x800121f3 <- 0x86063301 +mem-write: 0x800121f7 <- 0x8d79300 +mem-write: 0x800121fb <- 0x10cb701 +mem-write: 0x800121ff <- 0xc787b300 +mem-write: 0x80012203 <- 0xfc861300 +mem-write: 0x80012207 <- 0xf12423ff +mem-write: 0x8001220b <- 0xc8f7b302 +mem-write: 0x8001220f <- 0x81288300 +mem-write: 0x80012213 <- 0xc3733303 +mem-write: 0x80012217 <- 0x7979300 +mem-write: 0x8001221b <- 0x8d41301 +mem-write: 0x8001221f <- 0xc8f63301 +mem-write: 0x80012223 <- 0xc608b300 +mem-write: 0x80012227 <- 0x6787b303 +mem-write: 0x8001222b <- 0xc40d3300 +mem-write: 0x8001222f <- 0x8dd9303 +mem-write: 0x80012233 <- 0xca833301 +mem-write: 0x80012237 <- 0xa3033302 +mem-write: 0x8001223b <- 0x6d833301 +mem-write: 0x8001223f <- 0x8a8c3300 +mem-write: 0x80012243 <- 0xa3746302 +mem-write: 0x80012247 <- 0x9c0c3301 +mem-write: 0x8001224b <- 0x35c9301 +mem-write: 0x8001224f <- 0x8c8c3301 +mem-write: 0x80012253 <- 0x10cb701 +mem-write: 0x80012257 <- 0x3b89b300 +mem-write: 0x8001225b <- 0xfc8d1301 +mem-write: 0x8001225f <- 0xa9b533ff +mem-write: 0x80012263 <- 0xa3733300 +mem-write: 0x80012267 <- 0xa282b301 +mem-write: 0x8001226b <- 0x3131300 +mem-write: 0x8001226f <- 0xa8f8b301 +mem-write: 0x80012273 <- 0x628b3301 +mem-write: 0x80012277 <- 0x1308b301 +mem-write: 0x8001227b <- 0x9833301 +mem-write: 0x8001227f <- 0x3383301 +mem-write: 0x80012283 <- 0x61282301 +mem-write: 0x80012287 <- 0x61222300 +mem-write: 0x8001228b <- 0x4b033306 +mem-write: 0x8001228f <- 0x302b301 +mem-write: 0x80012293 <- 0x433a3301 +mem-write: 0x80012297 <- 0x2b83301 +mem-write: 0x8001229b <- 0xd289b301 +mem-write: 0x8001229f <- 0xa683300 +mem-write: 0x800122a3 <- 0xab353301 +mem-write: 0x800122a7 <- 0xd9b6b300 +mem-write: 0x800122ab <- 0xa8053300 +mem-write: 0x800122af <- 0xf989b300 +mem-write: 0x800122b3 <- 0x41280300 +mem-write: 0x800122b7 <- 0x19833302 +mem-write: 0x800122bb <- 0x1338b301 +mem-write: 0x800122bf <- 0x612a2301 +mem-write: 0x800122c3 <- 0x61242300 +mem-write: 0x800122c7 <- 0x41230306 +mem-write: 0x800122cb <- 0x5053302 +mem-write: 0x800122cf <- 0x81280301 +mem-write: 0x800122d3 <- 0xd50db302 +mem-write: 0x800122d7 <- 0xddb6b300 +mem-write: 0x800122db <- 0x65353300 +mem-write: 0x800122df <- 0xf9b7b300 +mem-write: 0x800122e3 <- 0xd8bb300 +mem-write: 0x800122e7 <- 0xd566b301 +mem-write: 0x800122eb <- 0x81250300 +mem-write: 0x800122ef <- 0xfb883302 +mem-write: 0x800122f3 <- 0xc1230300 +mem-write: 0x800122f7 <- 0x8809b304 +mem-write: 0x800122fb <- 0x198b3301 +mem-write: 0x800122ff <- 0xabbbb301 +mem-write: 0x80012303 <- 0xf837b300 +mem-write: 0x80012307 <- 0xfbe7b300 +mem-write: 0x8001230b <- 0x1b38b300 +mem-write: 0x8001230f <- 0x89bc3301 +mem-write: 0x80012313 <- 0xf686b301 +mem-write: 0x80012317 <- 0x3529300 +mem-write: 0x8001231b <- 0x1c6a3301 +mem-write: 0x8001231f <- 0xa3733301 +mem-write: 0x80012323 <- 0xe307b301 +mem-write: 0x80012327 <- 0x468a3302 +mem-write: 0x8001232b <- 0xe2873301 +mem-write: 0x8001232f <- 0x7d89302 +mem-write: 0x80012333 <- 0x6f86b301 +mem-write: 0x80012337 <- 0xd7073302 +mem-write: 0x8001233b <- 0xe888b300 +mem-write: 0x8001233f <- 0x5f8fb300 +mem-write: 0x80012343 <- 0xd8f46302 +mem-write: 0x80012347 <- 0x9f8fb300 +mem-write: 0x8001234b <- 0xc1298301 +mem-write: 0x8001234f <- 0x106b703 +mem-write: 0x80012353 <- 0xf6851300 +mem-write: 0x80012357 <- 0x8dd13ff +mem-write: 0x8001235b <- 0xa8f8b301 +mem-write: 0x8001235f <- 0xa7f7b300 +mem-write: 0x80012363 <- 0xfd0d3300 +mem-write: 0x80012367 <- 0x8989301 +mem-write: 0x8001236b <- 0x9df9301 +mem-write: 0x8001236f <- 0xa9f9b301 +mem-write: 0x80012373 <- 0xfa8cb300 +mem-write: 0x80012377 <- 0xf888b303 +mem-write: 0x8001237b <- 0x3a8ab300 +mem-write: 0x8001237f <- 0xc987b303 +mem-write: 0x80012383 <- 0xcf8e3303 +mem-write: 0x80012387 <- 0x7d81303 +mem-write: 0x8001238b <- 0xca8ab301 +mem-write: 0x8001238f <- 0x580ab301 +mem-write: 0x80012393 <- 0xcaf46301 +mem-write: 0x80012397 <- 0xdc8cb301 +mem-write: 0x8001239b <- 0x10bb700 +mem-write: 0x8001239f <- 0xfb871300 +mem-write: 0x800123a3 <- 0xad813ff +mem-write: 0x800123a7 <- 0x980cb301 +mem-write: 0x800123ab <- 0xeaf83301 +mem-write: 0x800123af <- 0xe7f7b300 +mem-write: 0x800123b3 <- 0x8181300 +mem-write: 0x800123b7 <- 0xbe86b301 +mem-write: 0x800123bb <- 0xf8083302 +mem-write: 0x800123bf <- 0xd90e3300 +mem-write: 0x800123c3 <- 0x6d51303 +mem-write: 0x800123c7 <- 0xb387b301 +mem-write: 0x800123cb <- 0xc787b302 +mem-write: 0x800123cf <- 0xf507b301 +mem-write: 0x800123d3 <- 0x79073300 +mem-write: 0x800123d7 <- 0xc7f46302 +mem-write: 0x800123db <- 0x77073301 +mem-write: 0x800123df <- 0x7d51301 +mem-write: 0x800123e3 <- 0xe5073301 +mem-write: 0x800123e7 <- 0x10bb700 +mem-write: 0x800123eb <- 0xe1222300 +mem-write: 0x800123ef <- 0xfb871302 +mem-write: 0x800123f3 <- 0xe7f533ff +VXDRV: upload 1024 bytes to 0x800123f7 +mem-write: 0x800123f7 <- 0xe6f6b300 +mem-write: 0x800123fb <- 0xe40e3300 +mem-write: 0x800123ff <- 0x5151303 +mem-write: 0x80012403 <- 0xd5053301 +mem-write: 0x80012407 <- 0xe6073300 +mem-write: 0x8001240b <- 0xc487b303 +mem-write: 0x8001240f <- 0x7569302 +mem-write: 0x80012413 <- 0xc787b301 +mem-write: 0x80012417 <- 0xf687b301 +mem-write: 0x8001241b <- 0x848ab300 +mem-write: 0x8001241f <- 0xc7f46302 +mem-write: 0x80012423 <- 0x7a8ab301 +mem-write: 0x80012427 <- 0x10db701 +mem-write: 0x8001242b <- 0xfd8e1300 +mem-write: 0x8001242f <- 0xc7f6b3ff +mem-write: 0x80012433 <- 0x7db9301 +mem-write: 0x80012437 <- 0x1b07b301 +mem-write: 0x8001243b <- 0xc7773301 +mem-write: 0x8001243f <- 0x17b8b301 +mem-write: 0x80012443 <- 0xaa0a3301 +mem-write: 0x80012447 <- 0x6969301 +mem-write: 0x8001244b <- 0xe686b301 +mem-write: 0x8001244f <- 0x1a073300 +mem-write: 0x80012453 <- 0xe1242301 +mem-write: 0x80012457 <- 0x787b302 +mem-write: 0x8001245b <- 0xaa3a3301 +mem-write: 0x8001245f <- 0x812d0301 +mem-write: 0x80012463 <- 0x7b83302 +mem-write: 0x80012467 <- 0x970b3301 +mem-write: 0x8001246b <- 0xb073301 +mem-write: 0x8001246f <- 0xe1262301 +mem-write: 0x80012473 <- 0x1d38b302 +mem-write: 0x80012477 <- 0x1a6a3301 +mem-write: 0x8001247b <- 0xc1288301 +mem-write: 0x8001247f <- 0x412e0302 +mem-write: 0x80012483 <- 0xa787b302 +mem-write: 0x80012487 <- 0x8b83300 +mem-write: 0x8001248b <- 0x9b3b3301 +mem-write: 0x8001248f <- 0xa7b53301 +mem-write: 0x80012493 <- 0xc7073300 +mem-write: 0x80012497 <- 0xb6b3301 +mem-write: 0x8001249b <- 0x41280301 +mem-write: 0x8001249f <- 0xa70c3302 +mem-write: 0x800124a3 <- 0x5b8bb300 +mem-write: 0x800124a7 <- 0xd787b301 +mem-write: 0x800124ab <- 0xd7b6b300 +mem-write: 0x800124af <- 0x7c0ab300 +mem-write: 0x800124b3 <- 0xda8e3301 +mem-write: 0x800124b7 <- 0x7373300 +mem-write: 0x800124bb <- 0xac353301 +mem-write: 0x800124bf <- 0xa7673300 +mem-write: 0x800124c3 <- 0xde36b300 +mem-write: 0x800124c7 <- 0x6a0a3300 +mem-write: 0x800124cb <- 0x7abab301 +mem-write: 0x800124cf <- 0xea0a3301 +mem-write: 0x800124d3 <- 0xdaeab300 +mem-write: 0x800124d7 <- 0xce883300 +mem-write: 0x800124db <- 0x5a06b302 +mem-write: 0x800124df <- 0xf1262301 +mem-write: 0x800124e3 <- 0xd40a3306 +mem-write: 0x800124e7 <- 0x8551303 +mem-write: 0x800124eb <- 0xc3873301 +mem-write: 0x800124ef <- 0x47073302 +mem-write: 0x800124f3 <- 0xe5073301 +mem-write: 0x800124f7 <- 0x8388b300 +mem-write: 0x800124fb <- 0x47746302 +mem-write: 0x800124ff <- 0xb888b301 +mem-write: 0x80012503 <- 0x10a3701 +mem-write: 0x80012507 <- 0x7551300 +mem-write: 0x8001250b <- 0xfa0a9301 +mem-write: 0x8001250f <- 0x1508b3ff +mem-write: 0x80012513 <- 0x57753301 +mem-write: 0x80012517 <- 0x58783301 +mem-write: 0x8001251b <- 0x5151301 +mem-write: 0x8001251f <- 0x690ab301 +mem-write: 0x80012523 <- 0x5053302 +mem-write: 0x80012527 <- 0xb3083301 +mem-write: 0x8001252b <- 0xb285b302 +mem-write: 0x8001252f <- 0x8571302 +mem-write: 0x80012533 <- 0x5585b301 +mem-write: 0x80012537 <- 0xb7073301 +mem-write: 0x8001253b <- 0x59093300 +mem-write: 0x8001253f <- 0x57746302 +mem-write: 0x80012543 <- 0x49093301 +mem-write: 0x80012547 <- 0x10ab701 +mem-write: 0x8001254b <- 0x7559300 +mem-write: 0x8001254f <- 0xfa8a1301 +mem-write: 0x80012553 <- 0x487833ff +mem-write: 0x80012557 <- 0x25893301 +mem-write: 0x8001255b <- 0x4775b301 +mem-write: 0x8001255f <- 0x5959301 +mem-write: 0x80012563 <- 0xe9873301 +mem-write: 0x80012567 <- 0x585b303 +mem-write: 0x8001256b <- 0xef8f3301 +mem-write: 0x8001256f <- 0x7581303 +mem-write: 0x80012573 <- 0xf48a3301 +mem-write: 0x80012577 <- 0x3484b303 +mem-write: 0x8001257b <- 0xe484b303 +mem-write: 0x8001257f <- 0x9804b301 +mem-write: 0x80012583 <- 0xe4f46300 +mem-write: 0x80012587 <- 0x5a0a3301 +mem-write: 0x8001258b <- 0x4db1301 +mem-write: 0x8001258f <- 0x4b0b3301 +mem-write: 0x80012593 <- 0x10a3701 +mem-write: 0x80012597 <- 0xfa0f1300 +mem-write: 0x8001259b <- 0xe4f833ff +mem-write: 0x8001259f <- 0xe7773301 +mem-write: 0x800125a3 <- 0x6404b301 +mem-write: 0x800125a7 <- 0x8181302 +mem-write: 0x800125ab <- 0xe8083301 +mem-write: 0x800125af <- 0x660f3300 +mem-write: 0x800125b3 <- 0xc2863302 +mem-write: 0x800125b7 <- 0xf571302 +mem-write: 0x800125bb <- 0x96063301 +mem-write: 0x800125bf <- 0xc7063300 +mem-write: 0x800125c3 <- 0x54043300 +mem-write: 0x800125c7 <- 0x96746302 +mem-write: 0x800125cb <- 0x44043300 +mem-write: 0x800125cf <- 0x10a3701 +mem-write: 0x800125d3 <- 0x6571300 +mem-write: 0x800125d7 <- 0xfa049301 +mem-write: 0x800125db <- 0x870433ff +mem-write: 0x800125df <- 0x96773300 +mem-write: 0x800125e3 <- 0x9f7f3300 +mem-write: 0x800125e7 <- 0x7171300 +mem-write: 0x800125eb <- 0xf384b301 +mem-write: 0x800125ef <- 0xe7073303 +mem-write: 0x800125f3 <- 0x3383b301 +mem-write: 0x800125f7 <- 0xd98f3303 +mem-write: 0x800125fb <- 0xdf8eb303 +mem-write: 0x800125ff <- 0xf561303 +mem-write: 0x80012603 <- 0xd383b301 +mem-write: 0x80012607 <- 0x76063301 +mem-write: 0x8001260b <- 0xd6746300 +mem-write: 0x8001260f <- 0x4484b301 +mem-write: 0x80012613 <- 0x65c1301 +mem-write: 0x80012617 <- 0x10cb701 +mem-write: 0x8001261b <- 0x9c0c3300 +mem-write: 0x8001261f <- 0xae0e3300 +mem-write: 0x80012623 <- 0xfc849300 +mem-write: 0x80012627 <- 0xae3533ff +mem-write: 0x8001262b <- 0x1686b300 +mem-write: 0x8001262f <- 0x96763301 +mem-write: 0x80012633 <- 0xa68d3300 +mem-write: 0x80012637 <- 0x9f7f3300 +mem-write: 0x8001263b <- 0xbe0e3300 +mem-write: 0x8001263f <- 0x6161300 +mem-write: 0x80012643 <- 0xe6063301 +mem-write: 0x80012647 <- 0xbe35b301 +mem-write: 0x8001264b <- 0x2d0f3300 +mem-write: 0x8001264f <- 0xe0e3301 +mem-write: 0x80012653 <- 0xbf03b301 +mem-write: 0x80012657 <- 0x638eb300 +mem-write: 0x8001265b <- 0xc1282301 +mem-write: 0x8001265f <- 0xe3e3307 +mem-write: 0x80012663 <- 0xce8db301 +mem-write: 0x80012667 <- 0x16b6b301 +mem-write: 0x8001266b <- 0xb3b5b301 +mem-write: 0x8001266f <- 0xad353300 +mem-write: 0x80012673 <- 0x2f393300 +mem-write: 0x80012677 <- 0xa6e53301 +mem-write: 0x8001267b <- 0xb9693300 +mem-write: 0x8001267f <- 0x6ebeb300 +mem-write: 0x80012683 <- 0xcdbe3301 +mem-write: 0x80012687 <- 0x25053301 +mem-write: 0x8001268b <- 0xceeeb301 +mem-write: 0x8001268f <- 0xed883301 +mem-write: 0x80012693 <- 0xd5053300 +mem-write: 0x80012697 <- 0xe8373301 +mem-write: 0x8001269b <- 0x85053300 +mem-write: 0x8001269f <- 0xe506b300 +mem-write: 0x800126a3 <- 0x85343300 +mem-write: 0x800126a7 <- 0x69853300 +mem-write: 0x800126ab <- 0xc8083302 +mem-write: 0x800126af <- 0xe6b73300 +mem-write: 0x800126b3 <- 0xc8363300 +mem-write: 0x800126b7 <- 0x8686b300 +mem-write: 0x800126bb <- 0xc685b301 +mem-write: 0x800126bf <- 0x86bc3300 +mem-write: 0x800126c3 <- 0xc5b63301 +mem-write: 0x800126c7 <- 0x12a2300 +mem-write: 0x800126cb <- 0xe4673307 +mem-write: 0x800126cf <- 0x6f833300 +mem-write: 0x800126d3 <- 0x5569302 +mem-write: 0x800126d7 <- 0xcc663301 +mem-write: 0x800126db <- 0x3289b300 +mem-write: 0x800126df <- 0x6989b303 +mem-write: 0x800126e3 <- 0xf28fb300 +mem-write: 0x800126e7 <- 0x3682b303 +mem-write: 0x800126eb <- 0x62f46301 +mem-write: 0x800126ef <- 0x9f8fb300 +mem-write: 0x800126f3 <- 0x92f6b301 +mem-write: 0x800126f7 <- 0x6969300 +mem-write: 0x800126fb <- 0x9574b301 +mem-write: 0x800126ff <- 0x2d29300 +mem-write: 0x80012703 <- 0x9684b301 +mem-write: 0x80012707 <- 0xe282b300 +mem-write: 0x8001270b <- 0x1268300 +mem-write: 0x8001270f <- 0x1270301 +mem-write: 0x80012713 <- 0x9585b302 +mem-write: 0x80012717 <- 0x95b4b300 +mem-write: 0x8001271b <- 0xd769b300 +mem-write: 0x8001271f <- 0x41270300 +mem-write: 0x80012723 <- 0xc282b301 +mem-write: 0x80012727 <- 0x9282b300 +mem-write: 0x8001272b <- 0x3769b300 +mem-write: 0x8001272f <- 0xf28fb301 +mem-write: 0x80012733 <- 0xd7979301 +mem-write: 0x80012737 <- 0xb12c2300 +mem-write: 0x8001273b <- 0xf12e2306 +mem-write: 0x8001273f <- 0x37e7b307 +mem-write: 0x80012743 <- 0x1071301 +mem-write: 0x80012747 <- 0x1059306 +mem-write: 0x8001274b <- 0xc7268307 +mem-write: 0x8001274f <- 0x7260300 +mem-write: 0x80012753 <- 0x47071301 +mem-write: 0x80012757 <- 0x36d69300 +mem-write: 0x8001275b <- 0xd6161301 +mem-write: 0x8001275f <- 0xc6e6b300 +mem-write: 0x80012763 <- 0xd72e2300 +mem-write: 0x80012767 <- 0xe592e3fe +mem-write: 0x8001276b <- 0x12703fe +mem-write: 0x8001276f <- 0x81268306 +mem-write: 0x80012773 <- 0xf037b306 +mem-write: 0x80012777 <- 0xe7e7b300 +mem-write: 0x8001277b <- 0xd12c2300 +mem-write: 0x8001277f <- 0xc1270304 +mem-write: 0x80012783 <- 0x41268306 +mem-write: 0x80012787 <- 0xf1282306 +mem-write: 0x8001278b <- 0xe12e2304 +mem-write: 0x8001278f <- 0xd12a2304 +mem-write: 0x80012793 <- 0xb7169304 +mem-write: 0x80012797 <- 0x6dc6300 +mem-write: 0x8001279b <- 0xf7979320 +mem-write: 0x8001279f <- 0x1071301 +mem-write: 0x800127a3 <- 0xc1059305 +mem-write: 0x800127a7 <- 0x7268305 +mem-write: 0x800127ab <- 0x47260300 +mem-write: 0x800127af <- 0x47071300 +mem-write: 0x800127b3 <- 0x16d69300 +mem-write: 0x800127b7 <- 0xf6161300 +mem-write: 0x800127bb <- 0xc6e6b301 +mem-write: 0x800127bf <- 0xd72e2300 +mem-write: 0x800127c3 <- 0xe592e3fe +mem-write: 0x800127c7 <- 0xc12703fe +mem-write: 0x800127cb <- 0xf037b305 +mem-write: 0x800127cf <- 0x17571300 +mem-write: 0x800127d3 <- 0xe12e2300 +mem-write: 0x800127d7 <- 0x1270304 +mem-write: 0x800127db <- 0xf767b305 +mem-write: 0x800127df <- 0xf1282300 +mem-write: 0x800127e3 <- 0x81270304 +mem-write: 0x800127e7 <- 0x47b701 +mem-write: 0x800127eb <- 0xf7879300 +mem-write: 0x800127ef <- 0xf707b3ff +mem-write: 0x800127f3 <- 0xf0506300 +VXDRV: upload 1024 bytes to 0x800127f7 +mem-write: 0x800127f7 <- 0x127031e +mem-write: 0x800127fb <- 0x77769305 +mem-write: 0x800127ff <- 0x6846300 +mem-write: 0x80012803 <- 0xf7769304 +mem-write: 0x80012807 <- 0x40061300 +mem-write: 0x8001280b <- 0xc68e6300 +mem-write: 0x8001280f <- 0x41268302 +mem-write: 0x80012813 <- 0x47071305 +mem-write: 0x80012817 <- 0xe1282300 +mem-write: 0x8001281b <- 0x47371304 +mem-write: 0x8001281f <- 0xd706b300 +mem-write: 0x80012823 <- 0xe6b73300 +mem-write: 0x80012827 <- 0xd12a2300 +mem-write: 0x8001282b <- 0x81268304 +mem-write: 0x8001282f <- 0xd706b305 +mem-write: 0x80012833 <- 0xd12c2300 +mem-write: 0x80012837 <- 0xe6b6b304 +mem-write: 0x8001283b <- 0xc1270300 +mem-write: 0x8001283f <- 0xe686b305 +mem-write: 0x80012843 <- 0xd12e2300 +mem-write: 0x80012847 <- 0xc1270304 +mem-write: 0x8001284b <- 0xb7169305 +mem-write: 0x8001284f <- 0x6d06300 +mem-write: 0x80012853 <- 0xf007b702 +mem-write: 0x80012857 <- 0xf78793ff +mem-write: 0x8001285b <- 0xf77733ff +mem-write: 0x8001285f <- 0xe12e2300 +mem-write: 0x80012863 <- 0x81270304 +mem-write: 0x80012867 <- 0x47b701 +mem-write: 0x8001286b <- 0xf707b300 +mem-write: 0x8001286f <- 0x1071300 +mem-write: 0x80012873 <- 0xc1059305 +mem-write: 0x80012877 <- 0x7268305 +mem-write: 0x8001287b <- 0x47260300 +mem-write: 0x8001287f <- 0x47071300 +mem-write: 0x80012883 <- 0x36d69300 +mem-write: 0x80012887 <- 0xd6161300 +mem-write: 0x8001288b <- 0xc6e6b301 +mem-write: 0x8001288f <- 0xd72e2300 +mem-write: 0x80012893 <- 0xb712e3fe +mem-write: 0x80012897 <- 0x8737fe +mem-write: 0x8001289b <- 0xe7069300 +mem-write: 0x8001289f <- 0xf6ce63ff +mem-write: 0x800128a3 <- 0xc1270310 +mem-write: 0x800128a7 <- 0x37571305 +mem-write: 0x800128ab <- 0xe12e2300 +mem-write: 0x800128af <- 0xc1270304 +mem-write: 0x800128b3 <- 0x17979305 +mem-write: 0x800128b7 <- 0x17d79301 +mem-write: 0x800128bb <- 0xe1162301 +mem-write: 0x800128bf <- 0xc1270306 +mem-write: 0x800128c3 <- 0xc1208300 +mem-write: 0x800128c7 <- 0x8124030b +mem-write: 0x800128cb <- 0xf717130b +mem-write: 0x800128cf <- 0xf767b300 +mem-write: 0x800128d3 <- 0xf1172300 +mem-write: 0x800128d7 <- 0x81270306 +mem-write: 0x800128db <- 0x1278300 +mem-write: 0x800128df <- 0x41248305 +mem-write: 0x800128e3 <- 0x129030b +mem-write: 0x800128e7 <- 0xf720230b +mem-write: 0x800128eb <- 0x41278300 +mem-write: 0x800128ef <- 0xc1298305 +mem-write: 0x800128f3 <- 0x812a030a +mem-write: 0x800128f7 <- 0xf722230a +mem-write: 0x800128fb <- 0x81278300 +mem-write: 0x800128ff <- 0x412a8305 +mem-write: 0x80012903 <- 0x12b030a +mem-write: 0x80012907 <- 0xf724230a +mem-write: 0x8001290b <- 0xc1278300 +mem-write: 0x8001290f <- 0xc12b8306 +mem-write: 0x80012913 <- 0x812c0309 +mem-write: 0x80012917 <- 0xf7262309 +mem-write: 0x8001291b <- 0x412c8300 +mem-write: 0x8001291f <- 0x12d0309 +mem-write: 0x80012923 <- 0xc12d8309 +mem-write: 0x80012927 <- 0x7051308 +mem-write: 0x8001292b <- 0x1011300 +mem-write: 0x8001292f <- 0x80670c +mem-write: 0x80012933 <- 0x91262300 +mem-write: 0x80012937 <- 0x1278300 +mem-write: 0x8001293b <- 0xf1282303 +mem-write: 0x8001293f <- 0x41278304 +mem-write: 0x80012943 <- 0xf12a2303 +mem-write: 0x80012947 <- 0x81278304 +mem-write: 0x8001294b <- 0xf12c2303 +mem-write: 0x8001294f <- 0xc1278304 +mem-write: 0x80012953 <- 0xf12e2303 +mem-write: 0x80012957 <- 0x20079304 +mem-write: 0x8001295b <- 0xfb086300 +mem-write: 0x8001295f <- 0x30079328 +mem-write: 0x80012963 <- 0xfb026300 +mem-write: 0x80012967 <- 0x1007932a +mem-write: 0x8001296b <- 0xfb1ce300 +mem-write: 0x8001296f <- 0x12e23e6 +mem-write: 0x80012973 <- 0x12c2304 +mem-write: 0x80012977 <- 0x12a2304 +mem-write: 0x8001297b <- 0x1282304 +mem-write: 0x8001297f <- 0xc0006f04 +mem-write: 0x80012983 <- 0x21262322 +mem-write: 0x80012987 <- 0x1278301 +mem-write: 0x8001298b <- 0x70b1304 +mem-write: 0x8001298f <- 0xf1282300 +mem-write: 0x80012993 <- 0x41278304 +mem-write: 0x80012997 <- 0xf12a2304 +mem-write: 0x8001299b <- 0x81278304 +mem-write: 0x8001299f <- 0xf12c2304 +mem-write: 0x800129a3 <- 0xc1278304 +mem-write: 0x800129a7 <- 0xf12e2304 +mem-write: 0x800129ab <- 0xdff06f04 +mem-write: 0x800129af <- 0xc12783fa +mem-write: 0x800129b3 <- 0xf12c2301 +mem-write: 0x800129b7 <- 0xdff06f00 +mem-write: 0x800129bb <- 0x12e23e2 +mem-write: 0x800129bf <- 0x12c2304 +mem-write: 0x800129c3 <- 0x12a2304 +mem-write: 0x800129c7 <- 0x1282304 +mem-write: 0x800129cb <- 0xf7079304 +mem-write: 0x800129cf <- 0x1ff06fff +mem-write: 0x800129d3 <- 0x100693ee +mem-write: 0x800129d7 <- 0xf686b300 +mem-write: 0x800129db <- 0x40079340 +mem-write: 0x800129df <- 0xd7ca6307 +mem-write: 0x800129e3 <- 0x56d5131c +mem-write: 0x800129e7 <- 0x79340 +mem-write: 0x800129eb <- 0x71300 +mem-write: 0x800129ef <- 0xa7166300 +mem-write: 0x800129f3 <- 0xf6f69304 +mem-write: 0x800129f7 <- 0x25159301 +mem-write: 0x800129fb <- 0x69e6300 +mem-write: 0x800129ff <- 0x30061304 +mem-write: 0x80012a03 <- 0x1071300 +mem-write: 0x80012a07 <- 0xa6063305 +mem-write: 0x80012a0b <- 0xb7083340 +mem-write: 0x80012a0f <- 0x8280300 +mem-write: 0x80012a13 <- 0x16869300 +mem-write: 0x80012a17 <- 0x47071300 +mem-write: 0x80012a1b <- 0x72e2300 +mem-write: 0x80012a1f <- 0xd656e3ff +mem-write: 0x80012a23 <- 0x400713fe +mem-write: 0x80012a27 <- 0xa7053300 +mem-write: 0x80012a2b <- 0x10071340 +mem-write: 0x80012a2f <- 0xa0506300 +mem-write: 0x80012a33 <- 0x5071308 +mem-write: 0x80012a37 <- 0x80006f00 +mem-write: 0x80012a3b <- 0x27161307 +mem-write: 0x80012a3f <- 0x1059300 +mem-write: 0x80012a43 <- 0xc5863305 +mem-write: 0x80012a47 <- 0x6260300 +mem-write: 0x80012a4b <- 0x17071300 +mem-write: 0x80012a4f <- 0xc7e7b300 +mem-write: 0x80012a53 <- 0xdff06f00 +mem-write: 0x80012a57 <- 0x10713f9 +mem-write: 0x80012a5b <- 0xb7073308 +mem-write: 0x80012a5f <- 0x7270300 +mem-write: 0x80012a63 <- 0x893fd +mem-write: 0x80012a67 <- 0xd888b302 +mem-write: 0x80012a6b <- 0x17173340 +mem-write: 0x80012a6f <- 0xe7e7b301 +mem-write: 0x80012a73 <- 0x30061300 +mem-write: 0x80012a77 <- 0x1071300 +mem-write: 0x80012a7b <- 0xb705b305 +mem-write: 0x80012a7f <- 0x81300 +mem-write: 0x80012a83 <- 0xa6063300 +mem-write: 0x80012a87 <- 0x45859340 +mem-write: 0x80012a8b <- 0xc8466300 +mem-write: 0x80012a8f <- 0x1059302 +mem-write: 0x80012a93 <- 0x26161308 +mem-write: 0x80012a97 <- 0xc5863300 +mem-write: 0x80012a9b <- 0xc1258300 +mem-write: 0x80012a9f <- 0x40071305 +mem-write: 0x80012aa3 <- 0xa7073300 +mem-write: 0x80012aa7 <- 0xd5d6b340 +mem-write: 0x80012aab <- 0xd6282300 +mem-write: 0x80012aaf <- 0x400613fc +mem-write: 0x80012ab3 <- 0x40006f00 +mem-write: 0x80012ab7 <- 0x28131304 +mem-write: 0x80012abb <- 0x1071300 +mem-write: 0x80012abf <- 0x5ae0305 +mem-write: 0x80012ac3 <- 0x67033300 +mem-write: 0x80012ac7 <- 0xc5a70300 +mem-write: 0x80012acb <- 0x1e1e33ff +mem-write: 0x80012acf <- 0x18081301 +mem-write: 0x80012ad3 <- 0xd7573300 +mem-write: 0x80012ad7 <- 0xc7673300 +mem-write: 0x80012adb <- 0xe3202301 +mem-write: 0x80012adf <- 0x9ff06f00 +mem-write: 0x80012ae3 <- 0x271693fa +mem-write: 0x80012ae7 <- 0x1059300 +mem-write: 0x80012aeb <- 0xd586b305 +mem-write: 0x80012aef <- 0x6a02300 +mem-write: 0x80012af3 <- 0x17071300 +mem-write: 0x80012af7 <- 0xc716e300 +mem-write: 0x80012afb <- 0x12683fe +mem-write: 0x80012aff <- 0xf037b305 +mem-write: 0x80012b03 <- 0xd7e7b300 +mem-write: 0x80012b07 <- 0xf1282300 +mem-write: 0x80012b0b <- 0x77f69304 +mem-write: 0x80012b0f <- 0x6826300 +mem-write: 0x80012b13 <- 0xf7f69304 +mem-write: 0x80012b17 <- 0xe68e6300 +mem-write: 0x80012b1b <- 0x41270302 +mem-write: 0x80012b1f <- 0x47879305 +mem-write: 0x80012b23 <- 0xf1282300 +mem-write: 0x80012b27 <- 0x47b79304 +mem-write: 0x80012b2b <- 0xe7873300 +mem-write: 0x80012b2f <- 0xf737b300 +mem-write: 0x80012b33 <- 0xe12a2300 +mem-write: 0x80012b37 <- 0x81270304 +mem-write: 0x80012b3b <- 0xe7873305 +mem-write: 0x80012b3f <- 0xe12c2300 +mem-write: 0x80012b43 <- 0xf7373304 +mem-write: 0x80012b47 <- 0xc1278300 +mem-write: 0x80012b4b <- 0xf7073305 +mem-write: 0x80012b4f <- 0xe12e2300 +mem-write: 0x80012b53 <- 0xc1278304 +mem-write: 0x80012b57 <- 0xc7971305 +mem-write: 0x80012b5b <- 0x75e6300 +mem-write: 0x80012b5f <- 0x12e2300 +mem-write: 0x80012b63 <- 0x12c2304 +mem-write: 0x80012b67 <- 0x12a2304 +mem-write: 0x80012b6b <- 0x1282304 +mem-write: 0x80012b6f <- 0x10079304 +mem-write: 0x80012b73 <- 0xdff06f00 +mem-write: 0x80012b77 <- 0x10793d3 +mem-write: 0x80012b7b <- 0xc1061305 +mem-write: 0x80012b7f <- 0x7a70305 +mem-write: 0x80012b83 <- 0x47a68300 +mem-write: 0x80012b87 <- 0x47879300 +mem-write: 0x80012b8b <- 0x37571300 +mem-write: 0x80012b8f <- 0xd6969300 +mem-write: 0x80012b93 <- 0xd7673301 +mem-write: 0x80012b97 <- 0xe7ae2300 +mem-write: 0x80012b9b <- 0xf612e3fe +mem-write: 0x80012b9f <- 0xc12783fe +mem-write: 0x80012ba3 <- 0x37d79305 +mem-write: 0x80012ba7 <- 0xf12e2300 +mem-write: 0x80012bab <- 0x79304 +mem-write: 0x80012baf <- 0x1ff06f00 +mem-write: 0x80012bb3 <- 0x412783d0 +mem-write: 0x80012bb7 <- 0x1270305 +mem-write: 0x80012bbb <- 0xf7673305 +mem-write: 0x80012bbf <- 0x81278300 +mem-write: 0x80012bc3 <- 0xf7673305 +mem-write: 0x80012bc7 <- 0xc1278300 +mem-write: 0x80012bcb <- 0xf7673305 +mem-write: 0x80012bcf <- 0x79300 +mem-write: 0x80012bd3 <- 0x70ee300 +mem-write: 0x80012bd7 <- 0x12e23cc +mem-write: 0x80012bdb <- 0x12c2304 +mem-write: 0x80012bdf <- 0x12a2304 +mem-write: 0x80012be3 <- 0x1282304 +mem-write: 0x80012be7 <- 0x9ff06f04 +mem-write: 0x80012beb <- 0x87b7cc +mem-write: 0x80012bef <- 0x12e2300 +mem-write: 0x80012bf3 <- 0x12c2304 +VXDRV: upload 1024 bytes to 0x80012bf7 +mem-write: 0x80012bf7 <- 0x12a2304 +mem-write: 0x80012bfb <- 0x1282304 +mem-write: 0x80012bff <- 0xf7879304 +mem-write: 0x80012c03 <- 0xdff06fff +mem-write: 0x80012c07 <- 0x87b7ca +mem-write: 0x80012c0b <- 0xf12e2300 +mem-write: 0x80012c0f <- 0x12c2304 +mem-write: 0x80012c13 <- 0x12a2304 +mem-write: 0x80012c17 <- 0x1282304 +mem-write: 0x80012c1b <- 0xf7879304 +mem-write: 0x80012c1f <- 0x12623ff +mem-write: 0x80012c23 <- 0xdff06f00 +mem-write: 0x80012c27 <- 0x10113c8 +mem-write: 0x80012c2b <- 0x85a783fa +mem-write: 0x80012c2f <- 0x21282300 +mem-write: 0x80012c33 <- 0xc5a90305 +mem-write: 0x80012c37 <- 0x5a88300 +mem-write: 0x80012c3b <- 0x45a70300 +mem-write: 0x80012c3f <- 0x912a2300 +mem-write: 0x80012c43 <- 0xf12c2304 +mem-write: 0x80012c47 <- 0x5049302 +mem-write: 0x80012c4b <- 0xf12c2300 +mem-write: 0x80012c4f <- 0x6280300 +mem-write: 0x80012c53 <- 0x9179300 +mem-write: 0x80012c57 <- 0x46250301 +mem-write: 0x80012c5b <- 0x86268300 +mem-write: 0x80012c5f <- 0xc62e0300 +mem-write: 0x80012c63 <- 0x812c2300 +mem-write: 0x80012c67 <- 0x7d79304 +mem-write: 0x80012c6b <- 0x19141301 +mem-write: 0x80012c6f <- 0x212e2300 +mem-write: 0x80012c73 <- 0x112e2303 +mem-write: 0x80012c77 <- 0x31262304 +mem-write: 0x80012c7b <- 0x41242305 +mem-write: 0x80012c7f <- 0x51222305 +mem-write: 0x80012c83 <- 0x61202305 +mem-write: 0x80012c87 <- 0x11282305 +mem-write: 0x80012c8b <- 0xe12a2303 +mem-write: 0x80012c8f <- 0x11282302 +mem-write: 0x80012c93 <- 0xe12a2301 +mem-write: 0x80012c97 <- 0xf12e2300 +mem-write: 0x80012c9b <- 0x14541300 +mem-write: 0x80012c9f <- 0xf9591301 +mem-write: 0x80012ca3 <- 0x10f1301 +mem-write: 0x80012ca7 <- 0xc1059301 +mem-write: 0x80012cab <- 0x5a78301 +mem-write: 0x80012caf <- 0xc5a70300 +mem-write: 0x80012cb3 <- 0xc58593ff +mem-write: 0x80012cb7 <- 0x379793ff +mem-write: 0x80012cbb <- 0xd7571300 +mem-write: 0x80012cbf <- 0xe7e7b301 +mem-write: 0x80012cc3 <- 0xf5a22300 +mem-write: 0x80012cc7 <- 0xbf12e300 +mem-write: 0x80012ccb <- 0x12703fe +mem-write: 0x80012ccf <- 0xe179301 +mem-write: 0x80012cd3 <- 0x1e1e9301 +mem-write: 0x80012cd7 <- 0x37171300 +mem-write: 0x80012cdb <- 0x7d79300 +mem-write: 0x80012cdf <- 0x1282301 +mem-write: 0x80012ce3 <- 0xd12c2303 +mem-write: 0x80012ce7 <- 0xc12e2302 +mem-write: 0x80012ceb <- 0x1202303 +mem-write: 0x80012cef <- 0xd1242303 +mem-write: 0x80012cf3 <- 0xe1282302 +mem-write: 0x80012cf7 <- 0xa12a2300 +mem-write: 0x80012cfb <- 0xa1222302 +mem-write: 0x80012cff <- 0xf1262302 +mem-write: 0x80012d03 <- 0x1ede9302 +mem-write: 0x80012d07 <- 0xfe5e1301 +mem-write: 0x80012d0b <- 0x1081301 +mem-write: 0x80012d0f <- 0xc1069302 +mem-write: 0x80012d13 <- 0x6a78302 +mem-write: 0x80012d17 <- 0xc6a60300 +mem-write: 0x80012d1b <- 0xc68693ff +mem-write: 0x80012d1f <- 0x379793ff +mem-write: 0x80012d23 <- 0xd6561300 +mem-write: 0x80012d27 <- 0xc7e7b301 +mem-write: 0x80012d2b <- 0xf6a22300 +mem-write: 0x80012d2f <- 0xd812e300 +mem-write: 0x80012d33 <- 0x12783fe +mem-write: 0x80012d37 <- 0x863702 +mem-write: 0x80012d3b <- 0xf6061300 +mem-write: 0x80012d3f <- 0x379793ff +mem-write: 0x80012d43 <- 0xf1202300 +mem-write: 0x80012d47 <- 0xce906302 +mem-write: 0x80012d4b <- 0x81250302 +mem-write: 0x80012d4f <- 0x41260302 +mem-write: 0x80012d53 <- 0xa6663302 +mem-write: 0x80012d57 <- 0xc1250300 +mem-write: 0x80012d5b <- 0xa6663302 +mem-write: 0x80012d5f <- 0xf6663300 +mem-write: 0x80012d63 <- 0x6146300 +mem-write: 0x80012d67 <- 0x1e4e1300 +mem-write: 0x80012d6b <- 0xd4033300 +mem-write: 0x80012d6f <- 0x2e1ee341 +mem-write: 0x80012d73 <- 0x605a630f +mem-write: 0x80012d77 <- 0x412f0344 +mem-write: 0x80012d7b <- 0x812e0301 +mem-write: 0x80012d7f <- 0xc1288301 +mem-write: 0x80012d83 <- 0xe9c6301 +mem-write: 0x80012d87 <- 0x4125030a +mem-write: 0x80012d8b <- 0x81260302 +mem-write: 0x80012d8f <- 0xc12e8302 +mem-write: 0x80012d93 <- 0xc565b302 +mem-write: 0x80012d97 <- 0xd5e5b300 +mem-write: 0x80012d9b <- 0xf5e5b301 +mem-write: 0x80012d9f <- 0x59e6300 +mem-write: 0x80012da3 <- 0xe1282300 +mem-write: 0x80012da7 <- 0xe12a2302 +mem-write: 0x80012dab <- 0xc12c2303 +mem-write: 0x80012daf <- 0x112e2303 +mem-write: 0x80012db3 <- 0x3041303 +mem-write: 0x80012db7 <- 0x6f00 +mem-write: 0x80012dbb <- 0xf305930a +mem-write: 0x80012dbf <- 0x59a63ff +mem-write: 0x80012dc3 <- 0xf707b304 +mem-write: 0x80012dc7 <- 0xe7b73300 +mem-write: 0x80012dcb <- 0xe505b300 +mem-write: 0x80012dcf <- 0xf1282301 +mem-write: 0x80012dd3 <- 0xe587b302 +mem-write: 0x80012dd7 <- 0xe7b73300 +mem-write: 0x80012ddb <- 0xe5b5b300 +mem-write: 0x80012ddf <- 0xe5e73301 +mem-write: 0x80012de3 <- 0xf12a2300 +mem-write: 0x80012de7 <- 0xc607b302 +mem-write: 0x80012deb <- 0xe786b301 +mem-write: 0x80012def <- 0xe6b73300 +mem-write: 0x80012df3 <- 0xc7b7b300 +mem-write: 0x80012df7 <- 0xe7e7b301 +mem-write: 0x80012dfb <- 0x1e88b300 +mem-write: 0x80012dff <- 0x1787b301 +mem-write: 0x80012e03 <- 0xd12c2301 +mem-write: 0x80012e07 <- 0xf12e2302 +mem-write: 0x80012e0b <- 0x10041302 +mem-write: 0x80012e0f <- 0xc0006f00 +mem-write: 0x80012e13 <- 0x87b732 +mem-write: 0x80012e17 <- 0xf7879300 +mem-write: 0x80012e1b <- 0xf304e3ff +mem-write: 0x80012e1f <- 0x400793f8 +mem-write: 0x80012e23 <- 0xb7d46307 +mem-write: 0x80012e27 <- 0x126231a +mem-write: 0x80012e2b <- 0x1242302 +mem-write: 0x80012e2f <- 0x1222302 +mem-write: 0x80012e33 <- 0x10079302 +mem-write: 0x80012e37 <- 0x80006f00 +mem-write: 0x80012e3b <- 0x87b72a +mem-write: 0x80012e3f <- 0xf7879300 +mem-write: 0x80012e43 <- 0xf41663ff +mem-write: 0x80012e47 <- 0xe1282316 +mem-write: 0x80012e4b <- 0xe12a2302 +mem-write: 0x80012e4f <- 0xc12c2303 +mem-write: 0x80012e53 <- 0x112e2303 +mem-write: 0x80012e57 <- 0x1278303 +mem-write: 0x80012e5b <- 0x77f71303 +mem-write: 0x80012e5f <- 0x7046300 +mem-write: 0x80012e63 <- 0xf7f71304 +mem-write: 0x80012e67 <- 0x40069300 +mem-write: 0x80012e6b <- 0xd70e6300 +mem-write: 0x80012e6f <- 0x41270302 +mem-write: 0x80012e73 <- 0x47879303 +mem-write: 0x80012e77 <- 0xf1282300 +mem-write: 0x80012e7b <- 0x47b79302 +mem-write: 0x80012e7f <- 0xe7873300 +mem-write: 0x80012e83 <- 0xf737b300 +mem-write: 0x80012e87 <- 0xe12a2300 +mem-write: 0x80012e8b <- 0x81270302 +mem-write: 0x80012e8f <- 0xe7873303 +mem-write: 0x80012e93 <- 0xe12c2300 +mem-write: 0x80012e97 <- 0xf7373302 +mem-write: 0x80012e9b <- 0xc1278300 +mem-write: 0x80012e9f <- 0xf7073303 +mem-write: 0x80012ea3 <- 0xe12e2300 +mem-write: 0x80012ea7 <- 0xc1278302 +mem-write: 0x80012eab <- 0xc7971303 +mem-write: 0x80012eaf <- 0x7546300 +mem-write: 0x80012eb3 <- 0x873702 +mem-write: 0x80012eb7 <- 0x14041300 +mem-write: 0x80012ebb <- 0xf7071300 +mem-write: 0x80012ebf <- 0xe41463ff +mem-write: 0x80012ec3 <- 0x106f00 +mem-write: 0x80012ec7 <- 0xf8073727 +mem-write: 0x80012ecb <- 0xf70713ff +mem-write: 0x80012ecf <- 0xe7f7b3ff +mem-write: 0x80012ed3 <- 0xf12e2300 +mem-write: 0x80012ed7 <- 0x1079302 +mem-write: 0x80012edb <- 0xc1061303 +mem-write: 0x80012edf <- 0x7a70303 +mem-write: 0x80012ee3 <- 0x47a68300 +mem-write: 0x80012ee7 <- 0x47879300 +mem-write: 0x80012eeb <- 0x37571300 +mem-write: 0x80012eef <- 0xd6969300 +mem-write: 0x80012ef3 <- 0xd7673301 +mem-write: 0x80012ef7 <- 0xe7ae2300 +mem-write: 0x80012efb <- 0xf612e3fe +mem-write: 0x80012eff <- 0xc12783fe +mem-write: 0x80012f03 <- 0x86b703 +mem-write: 0x80012f07 <- 0x37d71300 +mem-write: 0x80012f0b <- 0xe12e2300 +mem-write: 0x80012f0f <- 0xf6879302 +mem-write: 0x80012f13 <- 0xf41a63ff +mem-write: 0x80012f17 <- 0x41260302 +mem-write: 0x80012f1b <- 0x1278303 +mem-write: 0x80012f1f <- 0xc7e7b303 +mem-write: 0x80012f23 <- 0x81260300 +mem-write: 0x80012f27 <- 0xc7e7b303 +mem-write: 0x80012f2b <- 0xe7e7b300 +mem-write: 0x80012f2f <- 0x78c6300 +mem-write: 0x80012f33 <- 0xd12e2300 +mem-write: 0x80012f37 <- 0x12c2302 +mem-write: 0x80012f3b <- 0x12a2302 +mem-write: 0x80012f3f <- 0x1282302 +mem-write: 0x80012f43 <- 0x91302 +mem-write: 0x80012f47 <- 0xc1278300 +mem-write: 0x80012f4b <- 0x14141303 +mem-write: 0x80012f4f <- 0x14541301 +mem-write: 0x80012f53 <- 0xf1162301 +mem-write: 0x80012f57 <- 0x1278300 +mem-write: 0x80012f5b <- 0xf9191303 +mem-write: 0x80012f5f <- 0x89693300 +mem-write: 0x80012f63 <- 0xf4a02300 +mem-write: 0x80012f67 <- 0x41278300 +mem-write: 0x80012f6b <- 0x21172303 +mem-write: 0x80012f6f <- 0xc1208301 +mem-write: 0x80012f73 <- 0xf4a22305 +mem-write: 0x80012f77 <- 0x81278300 +mem-write: 0x80012f7b <- 0x81240303 +mem-write: 0x80012f7f <- 0x1290305 +mem-write: 0x80012f83 <- 0xf4a42305 +mem-write: 0x80012f87 <- 0xc1278300 +mem-write: 0x80012f8b <- 0xc1298300 +mem-write: 0x80012f8f <- 0x812a0304 +mem-write: 0x80012f93 <- 0xf4a62304 +mem-write: 0x80012f97 <- 0x412a8300 +mem-write: 0x80012f9b <- 0x12b0304 +mem-write: 0x80012f9f <- 0x4851304 +mem-write: 0x80012fa3 <- 0x41248300 +mem-write: 0x80012fa7 <- 0x1011305 +mem-write: 0x80012fab <- 0x806706 +mem-write: 0x80012faf <- 0xc1278300 +mem-write: 0x80012fb3 <- 0x8063702 +mem-write: 0x80012fb7 <- 0xc7e7b300 +mem-write: 0x80012fbb <- 0xf1262300 +mem-write: 0x80012fbf <- 0x40079302 +mem-write: 0x80012fc3 <- 0x67c2e307 +mem-write: 0x80012fc7 <- 0x30593e6 +mem-write: 0x80012fcb <- 0x55de9300 +mem-write: 0x80012fcf <- 0x79340 +mem-write: 0x80012fd3 <- 0x61300 +mem-write: 0x80012fd7 <- 0xd6166300 +mem-write: 0x80012fdb <- 0xf5f59305 +mem-write: 0x80012fdf <- 0x2e931301 +mem-write: 0x80012fe3 <- 0x59c6300 +mem-write: 0x80012fe7 <- 0x30059304 +mem-write: 0x80012feb <- 0x61300 +mem-write: 0x80012fef <- 0xd585b300 +mem-write: 0x80012ff3 <- 0x66853341 +VXDRV: upload 1024 bytes to 0x80012ff7 +mem-write: 0x80012ff7 <- 0x5250300 +mem-write: 0x80012ffb <- 0x16061300 +mem-write: 0x80012fff <- 0x46869300 +mem-write: 0x80013003 <- 0xa6ae2300 +mem-write: 0x80013007 <- 0xc5d6e3fe +mem-write: 0x8001300b <- 0x400613fe +mem-write: 0x8001300f <- 0xd60eb300 +mem-write: 0x80013013 <- 0x10061341 +mem-write: 0x80013017 <- 0xd05c6300 +mem-write: 0x8001301b <- 0xe861307 +mem-write: 0x8001301f <- 0x6f00 +mem-write: 0x80013023 <- 0x26151307 +mem-write: 0x80013027 <- 0xa8053300 +mem-write: 0x8001302b <- 0x5250300 +mem-write: 0x8001302f <- 0x16061300 +mem-write: 0x80013033 <- 0xa7e7b300 +mem-write: 0x80013037 <- 0x1ff06f00 +mem-write: 0x8001303b <- 0x10693fa +mem-write: 0x8001303f <- 0x6686b304 +mem-write: 0x80013043 <- 0x6a68300 +mem-write: 0x80013047 <- 0xf93fe +mem-write: 0x8001304b <- 0xbf8fb302 +mem-write: 0x8001304f <- 0xf696b340 +mem-write: 0x80013053 <- 0x30051301 +mem-write: 0x80013057 <- 0xd7e7b300 +mem-write: 0x8001305b <- 0x68033300 +mem-write: 0x8001305f <- 0x61300 +mem-write: 0x80013063 <- 0xd5053300 +mem-write: 0x80013067 <- 0x43031341 +mem-write: 0x8001306b <- 0xa6466300 +mem-write: 0x8001306f <- 0x1069302 +mem-write: 0x80013073 <- 0x25151304 +mem-write: 0x80013077 <- 0xa6853300 +mem-write: 0x8001307b <- 0xc1268300 +mem-write: 0x8001307f <- 0x40061302 +mem-write: 0x80013083 <- 0xd6063300 +mem-write: 0x80013087 <- 0xb6d5b341 +mem-write: 0x8001308b <- 0xb5202300 +mem-write: 0x8001308f <- 0x400593fe +mem-write: 0x80013093 <- 0xc0006f00 +mem-write: 0x80013097 <- 0xc3268303 +mem-write: 0x8001309b <- 0x32383ff +mem-write: 0x8001309f <- 0x26129300 +mem-write: 0x800130a3 <- 0xb6d6b300 +mem-write: 0x800130a7 <- 0xf393b300 +mem-write: 0x800130ab <- 0x5802b301 +mem-write: 0x800130af <- 0x76e6b300 +mem-write: 0x800130b3 <- 0xd2a02300 +mem-write: 0x800130b7 <- 0x16061300 +mem-write: 0x800130bb <- 0xdff06f00 +mem-write: 0x800130bf <- 0x261693fa +mem-write: 0x800130c3 <- 0xd806b300 +mem-write: 0x800130c7 <- 0x6a02300 +mem-write: 0x800130cb <- 0x16061300 +mem-write: 0x800130cf <- 0xb618e300 +mem-write: 0x800130d3 <- 0x12683fe +mem-write: 0x800130d7 <- 0xf037b302 +mem-write: 0x800130db <- 0xf6e7b300 +mem-write: 0x800130df <- 0xf1202300 +mem-write: 0x800130e3 <- 0x1258302 +mem-write: 0x800130e7 <- 0x41260302 +mem-write: 0x800130eb <- 0xb705b302 +mem-write: 0x800130ef <- 0xe5b73300 +mem-write: 0x800130f3 <- 0xcf063300 +mem-write: 0x800130f7 <- 0xe606b300 +mem-write: 0x800130fb <- 0xb1282300 +mem-write: 0x800130ff <- 0xe635b302 +mem-write: 0x80013103 <- 0x81260301 +mem-write: 0x80013107 <- 0xe6b73302 +mem-write: 0x8001310b <- 0xe5e5b300 +mem-write: 0x8001310f <- 0xd12a2300 +mem-write: 0x80013113 <- 0xce06b302 +mem-write: 0x80013117 <- 0xb687b300 +mem-write: 0x8001311b <- 0xb7b5b300 +mem-write: 0x8001311f <- 0xf12c2300 +mem-write: 0x80013123 <- 0xc1278302 +mem-write: 0x80013127 <- 0xc6b6b302 +mem-write: 0x8001312b <- 0xb6e6b301 +mem-write: 0x8001312f <- 0xf888b300 +mem-write: 0x80013133 <- 0x1686b300 +mem-write: 0x80013137 <- 0xd12e2301 +mem-write: 0x8001313b <- 0xc1278302 +mem-write: 0x8001313f <- 0xc7971303 +mem-write: 0x80013143 <- 0x75ae300 +mem-write: 0x80013147 <- 0xf80737d0 +mem-write: 0x8001314b <- 0xf70713ff +mem-write: 0x8001314f <- 0xe7f7b3ff +mem-write: 0x80013153 <- 0xf12e2300 +mem-write: 0x80013157 <- 0x1278302 +mem-write: 0x8001315b <- 0x14041303 +mem-write: 0x8001315f <- 0xc1059300 +mem-write: 0x80013163 <- 0xf7971303 +mem-write: 0x80013167 <- 0x1079301 +mem-write: 0x8001316b <- 0x7a68303 +mem-write: 0x8001316f <- 0x47a60300 +mem-write: 0x80013173 <- 0x47879300 +mem-write: 0x80013177 <- 0x16d69300 +mem-write: 0x8001317b <- 0xf6161300 +mem-write: 0x8001317f <- 0xc6e6b301 +mem-write: 0x80013183 <- 0xd7ae2300 +mem-write: 0x80013187 <- 0xf592e3fe +mem-write: 0x8001318b <- 0xc12783fe +mem-write: 0x8001318f <- 0x17d79303 +mem-write: 0x80013193 <- 0xf12e2300 +mem-write: 0x80013197 <- 0xe037b302 +mem-write: 0x8001319b <- 0x1270300 +mem-write: 0x8001319f <- 0xf767b303 +mem-write: 0x800131a3 <- 0xf1282300 +mem-write: 0x800131a7 <- 0x87b702 +mem-write: 0x800131ab <- 0xf7879300 +mem-write: 0x800131af <- 0xf414e3ff +mem-write: 0x800131b3 <- 0x12e23ca +mem-write: 0x800131b7 <- 0x12c2302 +mem-write: 0x800131bb <- 0x12a2302 +mem-write: 0x800131bf <- 0x1282302 +mem-write: 0x800131c3 <- 0x5ff06f02 +mem-write: 0x800131c7 <- 0x412683c9 +mem-write: 0x800131cb <- 0x81260302 +mem-write: 0x800131cf <- 0xc1250302 +mem-write: 0x800131d3 <- 0x3046302 +mem-write: 0x800131d7 <- 0x8e8e3328 +mem-write: 0x800131db <- 0x41a6340 +mem-write: 0x800131df <- 0x4128830a +mem-write: 0x800131e3 <- 0x81280301 +mem-write: 0x800131e7 <- 0xc12f8301 +mem-write: 0x800131eb <- 0x8e33301 +mem-write: 0x800131ef <- 0xf3633301 +mem-write: 0x800131f3 <- 0xe3633301 +mem-write: 0x800131f7 <- 0x31e6300 +mem-write: 0x800131fb <- 0xf1282300 +mem-write: 0x800131ff <- 0xd12a2302 +mem-write: 0x80013203 <- 0xc12c2302 +mem-write: 0x80013207 <- 0xa12e2302 +mem-write: 0x8001320b <- 0xe041302 +mem-write: 0x8001320f <- 0x9ff06f00 +mem-write: 0x80013213 <- 0xfe0313c4 +mem-write: 0x80013217 <- 0x31863ff +mem-write: 0x8001321b <- 0xf7073304 +mem-write: 0x8001321f <- 0xf737b300 +mem-write: 0x80013223 <- 0xd885b300 +mem-write: 0x80013227 <- 0xe1282300 +mem-write: 0x8001322b <- 0xf5873302 +mem-write: 0x8001322f <- 0xf737b300 +mem-write: 0x80013233 <- 0xd5b6b300 +mem-write: 0x80013237 <- 0xf6e6b300 +mem-write: 0x8001323b <- 0xe12a2300 +mem-write: 0x8001323f <- 0xc8073302 +mem-write: 0x80013243 <- 0xd707b300 +mem-write: 0x80013247 <- 0xd7b6b300 +mem-write: 0x8001324b <- 0xc7373300 +mem-write: 0x8001324f <- 0xd7673300 +mem-write: 0x80013253 <- 0xaf853300 +mem-write: 0x80013257 <- 0xa7053300 +mem-write: 0x8001325b <- 0xf12c2300 +mem-write: 0x8001325f <- 0xa12e2302 +mem-write: 0x80013263 <- 0x9ff06f02 +mem-write: 0x80013267 <- 0x8737ba +mem-write: 0x8001326b <- 0xf7071300 +mem-write: 0x8001326f <- 0xee06e3ff +mem-write: 0x80013273 <- 0x400713f8 +mem-write: 0x80013277 <- 0x675c6307 +mem-write: 0x8001327b <- 0x12e2304 +mem-write: 0x8001327f <- 0x12c2300 +mem-write: 0x80013283 <- 0x12a2300 +mem-write: 0x80013287 <- 0x10071300 +mem-write: 0x8001328b <- 0xc0006f00 +mem-write: 0x8001328f <- 0x873716 +mem-write: 0x80013293 <- 0xf7071300 +mem-write: 0x80013297 <- 0xee9e63ff +mem-write: 0x8001329b <- 0xf1282300 +mem-write: 0x8001329f <- 0xd12a2302 +mem-write: 0x800132a3 <- 0xc12c2302 +mem-write: 0x800132a7 <- 0xa12e2302 +mem-write: 0x800132ab <- 0xe841302 +mem-write: 0x800132af <- 0x9ff06f00 +mem-write: 0x800132b3 <- 0xc12703ba +mem-write: 0x800132b7 <- 0x8083701 +mem-write: 0x800132bb <- 0x7673300 +mem-write: 0x800132bf <- 0xe12e2301 +mem-write: 0x800132c3 <- 0x40071300 +mem-write: 0x800132c7 <- 0xc74ae307 +mem-write: 0x800132cb <- 0xe0313fb +mem-write: 0x800132cf <- 0x71300 +mem-write: 0x800132d3 <- 0xe34e3302 +mem-write: 0x800132d7 <- 0xf9302 +mem-write: 0x800132db <- 0x71300 +mem-write: 0x800132df <- 0xc74a6300 +mem-write: 0x800132e3 <- 0xe089305 +mem-write: 0x800132e7 <- 0xe546300 +mem-write: 0x800132eb <- 0x89300 +mem-write: 0x800132ef <- 0xf3771300 +mem-write: 0x800132f3 <- 0x2e181301 +mem-write: 0x800132f7 <- 0x71a6300 +mem-write: 0x800132fb <- 0x30089304 +mem-write: 0x800132ff <- 0xc888b300 +mem-write: 0x80013303 <- 0x5833341 +mem-write: 0x80013307 <- 0x3230301 +mem-write: 0x8001330b <- 0x17071300 +mem-write: 0x8001330f <- 0x45859300 +mem-write: 0x80013313 <- 0x65ae2300 +mem-write: 0x80013317 <- 0xe8d6e3fe +mem-write: 0x8001331b <- 0x400713fe +mem-write: 0x8001331f <- 0xc70e3300 +mem-write: 0x80013323 <- 0x10071341 +mem-write: 0x80013327 <- 0xc0506300 +mem-write: 0x8001332b <- 0xe071309 +mem-write: 0x8001332f <- 0x80006f00 +mem-write: 0x80013333 <- 0x27181307 +mem-write: 0x80013337 <- 0xf083300 +mem-write: 0x8001333b <- 0x8280301 +mem-write: 0x8001333f <- 0x17071300 +mem-write: 0x80013343 <- 0xfefb300 +mem-write: 0x80013347 <- 0x9ff06f01 +mem-write: 0x8001334b <- 0x713f9 +mem-write: 0x8001334f <- 0xe3633302 +mem-write: 0x80013353 <- 0x1059302 +mem-write: 0x80013357 <- 0x28989304 +mem-write: 0x8001335b <- 0x1588b300 +mem-write: 0x8001335f <- 0x8a58301 +mem-write: 0x80013363 <- 0xf0833fd +mem-write: 0x80013367 <- 0x29301 +mem-write: 0x8001336b <- 0x67073300 +mem-write: 0x8001336f <- 0xe595b340 +mem-write: 0x80013373 <- 0xbfefb300 +mem-write: 0x80013377 <- 0x30059300 +mem-write: 0x8001337b <- 0xc585b300 +mem-write: 0x8001337f <- 0x48081341 +mem-write: 0x80013383 <- 0xb2c66300 +mem-write: 0x80013387 <- 0x1081302 +mem-write: 0x8001338b <- 0x25959304 +mem-write: 0x8001338f <- 0xb805b300 +mem-write: 0x80013393 <- 0xc1280300 +mem-write: 0x80013397 <- 0x40071301 +mem-write: 0x8001339b <- 0xc7073300 +mem-write: 0x8001339f <- 0x68533341 +mem-write: 0x800133a3 <- 0x65a82300 +mem-write: 0x800133a7 <- 0x300813fc +mem-write: 0x800133ab <- 0xc0006f00 +mem-write: 0x800133af <- 0xc8288303 +mem-write: 0x800133b3 <- 0x82403ff +mem-write: 0x800133b7 <- 0x22939300 +mem-write: 0x800133bb <- 0x68d8b300 +mem-write: 0x800133bf <- 0xe4143300 +mem-write: 0x800133c3 <- 0x7f03b300 +mem-write: 0x800133c7 <- 0x88e8b300 +mem-write: 0x800133cb <- 0x13a02300 +mem-write: 0x800133cf <- 0x12829301 +mem-write: 0x800133d3 <- 0xdff06f00 +mem-write: 0x800133d7 <- 0x271593fa +mem-write: 0x800133db <- 0xbf05b300 +mem-write: 0x800133df <- 0x5a02300 +mem-write: 0x800133e3 <- 0x17071300 +mem-write: 0x800133e7 <- 0xe858e300 +mem-write: 0x800133eb <- 0x12583fe +mem-write: 0x800133ef <- 0xf0373301 +mem-write: 0x800133f3 <- 0xe5e73301 +VXDRV: upload 1024 bytes to 0x800133f7 +mem-write: 0x800133f7 <- 0xe1282300 +mem-write: 0x800133fb <- 0x1270300 +mem-write: 0x800133ff <- 0x41258301 +mem-write: 0x80013403 <- 0xe841301 +mem-write: 0x80013407 <- 0xe7873300 +mem-write: 0x8001340b <- 0xf737b300 +mem-write: 0x8001340f <- 0xb685b300 +mem-write: 0x80013413 <- 0xe1282300 +mem-write: 0x80013417 <- 0xf5873302 +mem-write: 0x8001341b <- 0xf737b300 +mem-write: 0x8001341f <- 0xe12a2300 +mem-write: 0x80013423 <- 0x81270302 +mem-write: 0x80013427 <- 0xd5b6b301 +mem-write: 0x8001342b <- 0xf6e6b300 +mem-write: 0x8001342f <- 0xe6073300 +mem-write: 0x80013433 <- 0xd707b300 +mem-write: 0x80013437 <- 0xc7373300 +mem-write: 0x8001343b <- 0xc1260300 +mem-write: 0x8001343f <- 0xd7b6b301 +mem-write: 0x80013443 <- 0xd7673300 +mem-write: 0x80013447 <- 0xc5053300 +mem-write: 0x8001344b <- 0xa7053300 +mem-write: 0x8001344f <- 0xf12c2300 +mem-write: 0x80013453 <- 0xa12e2302 +mem-write: 0x80013457 <- 0x5ff06f02 +mem-write: 0x8001345b <- 0x8fb7ce +mem-write: 0x8001345f <- 0x14059300 +mem-write: 0x80013463 <- 0xef881300 +mem-write: 0x80013467 <- 0x5f833ff +mem-write: 0x8001346b <- 0x412f0301 +mem-write: 0x8001346f <- 0x812e8301 +mem-write: 0x80013473 <- 0xc12e0301 +mem-write: 0x80013477 <- 0x1089301 +mem-write: 0x8001347b <- 0xc1031303 +mem-write: 0x8001347f <- 0x8166303 +mem-write: 0x80013483 <- 0xdf683314 +mem-write: 0x80013487 <- 0xc8683301 +mem-write: 0x8001348b <- 0xe8683301 +mem-write: 0x8001348f <- 0x4166300 +mem-write: 0x80013493 <- 0x81c630a +mem-write: 0x80013497 <- 0xf1282300 +mem-write: 0x8001349b <- 0xd12a2302 +mem-write: 0x8001349f <- 0xc12c2302 +mem-write: 0x800134a3 <- 0xa12e2302 +mem-write: 0x800134a7 <- 0x1ff06f02 +mem-write: 0x800134ab <- 0xc6e5b39b +mem-write: 0x800134af <- 0xa5e5b300 +mem-write: 0x800134b3 <- 0xf5e5b300 +mem-write: 0x800134b7 <- 0x59c6300 +mem-write: 0x800134bb <- 0xe1282300 +mem-write: 0x800134bf <- 0xe12a2302 +mem-write: 0x800134c3 <- 0xd12c2303 +mem-write: 0x800134c7 <- 0xc12e2303 +mem-write: 0x800134cb <- 0xdff06f03 +mem-write: 0x800134cf <- 0xf707b398 +mem-write: 0x800134d3 <- 0xe7b73300 +mem-write: 0x800134d7 <- 0xdf05b300 +mem-write: 0x800134db <- 0xf1282300 +mem-write: 0x800134df <- 0xe587b302 +mem-write: 0x800134e3 <- 0xe5b6b300 +mem-write: 0x800134e7 <- 0xe7b73301 +mem-write: 0x800134eb <- 0xe6e73300 +mem-write: 0x800134ef <- 0xce863300 +mem-write: 0x800134f3 <- 0xe606b300 +mem-write: 0x800134f7 <- 0xe6b73300 +mem-write: 0x800134fb <- 0xd6363300 +mem-write: 0x800134ff <- 0xe6663301 +mem-write: 0x80013503 <- 0xae053300 +mem-write: 0x80013507 <- 0xa6063300 +mem-write: 0x8001350b <- 0xf12a2300 +mem-write: 0x8001350f <- 0xd12c2302 +mem-write: 0x80013513 <- 0xc6179302 +mem-write: 0x80013517 <- 0x7c66300 +mem-write: 0x8001351b <- 0xc12e2300 +mem-write: 0x8001351f <- 0x9ff06f02 +mem-write: 0x80013523 <- 0xf807b793 +mem-write: 0x80013527 <- 0xf78793ff +mem-write: 0x8001352b <- 0xf67633ff +mem-write: 0x8001352f <- 0xc12e2300 +mem-write: 0x80013533 <- 0x10041302 +mem-write: 0x80013537 <- 0x1ff06f00 +mem-write: 0x8001353b <- 0x81e6392 +mem-write: 0x8001353f <- 0xf1282300 +mem-write: 0x80013543 <- 0xd12a2302 +mem-write: 0x80013547 <- 0xc12c2302 +mem-write: 0x8001354b <- 0xa12e2302 +mem-write: 0x8001354f <- 0xff841302 +mem-write: 0x80013553 <- 0x5ff06fff +mem-write: 0x80013557 <- 0xc6e6b390 +mem-write: 0x8001355b <- 0xa6e53300 +mem-write: 0x8001355f <- 0xf567b300 +mem-write: 0x80013563 <- 0x79c6300 +mem-write: 0x80013567 <- 0xe1282300 +mem-write: 0x8001356b <- 0xe12a2302 +mem-write: 0x8001356f <- 0xd12c2303 +mem-write: 0x80013573 <- 0xc12e2303 +mem-write: 0x80013577 <- 0x9ff06f03 +mem-write: 0x8001357b <- 0xf12e23fd +mem-write: 0x8001357f <- 0x12c2303 +mem-write: 0x80013583 <- 0x12a2302 +mem-write: 0x80013587 <- 0x1282302 +mem-write: 0x8001358b <- 0x3071302 +mem-write: 0x8001358f <- 0x7278300 +mem-write: 0x80013593 <- 0xc7268300 +mem-write: 0x80013597 <- 0xc70713ff +mem-write: 0x8001359b <- 0x379793ff +mem-write: 0x8001359f <- 0xd6d69300 +mem-write: 0x800135a3 <- 0xd7e7b301 +mem-write: 0x800135a7 <- 0xf7222300 +mem-write: 0x800135ab <- 0xe892e300 +mem-write: 0x800135af <- 0x12783fe +mem-write: 0x800135b3 <- 0x843703 +mem-write: 0x800135b7 <- 0x91300 +mem-write: 0x800135bb <- 0x37979300 +mem-write: 0x800135bf <- 0xf1282300 +mem-write: 0x800135c3 <- 0xf4041302 +mem-write: 0x800135c7 <- 0x1ff06fff +mem-write: 0x800135cb <- 0xf707b389 +mem-write: 0x800135cf <- 0xe7b73300 +mem-write: 0x800135d3 <- 0xdf06b300 +mem-write: 0x800135d7 <- 0xf1282300 +mem-write: 0x800135db <- 0xe687b302 +mem-write: 0x800135df <- 0xe7b73300 +mem-write: 0x800135e3 <- 0xe6b6b300 +mem-write: 0x800135e7 <- 0xe6e73301 +mem-write: 0x800135eb <- 0xce86b300 +mem-write: 0x800135ef <- 0xf12a2300 +mem-write: 0x800135f3 <- 0xe687b302 +mem-write: 0x800135f7 <- 0xd6b63300 +mem-write: 0x800135fb <- 0xe7b6b301 +mem-write: 0x800135ff <- 0xd666b300 +mem-write: 0x80013603 <- 0xae053300 +mem-write: 0x80013607 <- 0xa6853300 +mem-write: 0x8001360b <- 0xf12c2300 +mem-write: 0x8001360f <- 0xa12e2302 +mem-write: 0x80013613 <- 0x8879302 +mem-write: 0x80013617 <- 0x7a70300 +mem-write: 0x8001361b <- 0x47a68300 +mem-write: 0x8001361f <- 0x47879300 +mem-write: 0x80013623 <- 0x17571300 +mem-write: 0x80013627 <- 0xf6969300 +mem-write: 0x8001362b <- 0xd7673301 +mem-write: 0x8001362f <- 0xe7ae2300 +mem-write: 0x80013633 <- 0xf312e3fe +mem-write: 0x80013637 <- 0x87b7fe +mem-write: 0x8001363b <- 0xf7879300 +mem-write: 0x8001363f <- 0xf58c63ff +mem-write: 0x80013643 <- 0xc1278300 +mem-write: 0x80013647 <- 0x17d79303 +mem-write: 0x8001364b <- 0xf12e2300 +mem-write: 0x8001364f <- 0x5841302 +mem-write: 0x80013653 <- 0x5ff06f00 +mem-write: 0x80013657 <- 0x12e2380 +mem-write: 0x8001365b <- 0x12c2302 +mem-write: 0x8001365f <- 0x12a2302 +mem-write: 0x80013663 <- 0x1282302 +mem-write: 0x80013667 <- 0x9ff06f02 +mem-write: 0x8001366b <- 0x605e63fe +mem-write: 0x8001366f <- 0x4128832a +mem-write: 0x80013673 <- 0x812e0301 +mem-write: 0x80013677 <- 0xc12f0301 +mem-write: 0x8001367b <- 0xe946301 +mem-write: 0x8001367f <- 0x412e830c +mem-write: 0x80013683 <- 0x81250302 +mem-write: 0x80013687 <- 0xc1258302 +mem-write: 0x8001368b <- 0xaee63302 +mem-write: 0x8001368f <- 0xb6663300 +mem-write: 0x80013693 <- 0xf6663300 +mem-write: 0x80013697 <- 0x61c6300 +mem-write: 0x8001369b <- 0xe1282300 +mem-write: 0x8001369f <- 0x112a2302 +mem-write: 0x800136a3 <- 0xc12c2303 +mem-write: 0x800136a7 <- 0xe12e2303 +mem-write: 0x800136ab <- 0x8ff06f03 +mem-write: 0x800136af <- 0xf30613f0 +mem-write: 0x800136b3 <- 0x61463ff +mem-write: 0x800136b7 <- 0xf707b306 +mem-write: 0x800136bb <- 0xd886b340 +mem-write: 0x800136bf <- 0xf7383341 +mem-write: 0x800136c3 <- 0xd8b33300 +mem-write: 0x800136c7 <- 0x6883300 +mem-write: 0x800136cb <- 0x69341 +mem-write: 0x800136cf <- 0xf7766300 +mem-write: 0x800136d3 <- 0x1e88b300 +mem-write: 0x800136d7 <- 0x18b69341 +mem-write: 0x800136db <- 0x66e8b300 +mem-write: 0x800136df <- 0xae073300 +mem-write: 0x800136e3 <- 0xee36b340 +mem-write: 0x800136e7 <- 0x17073300 +mem-write: 0x800136eb <- 0x8866341 +mem-write: 0x800136ef <- 0xc50e3300 +mem-write: 0x800136f3 <- 0x1e361341 +mem-write: 0x800136f7 <- 0xbf05b300 +mem-write: 0x800136fb <- 0xd6663340 +mem-write: 0x800136ff <- 0xc585b300 +mem-write: 0x80013703 <- 0xb12e2340 +mem-write: 0x80013707 <- 0xe12c2302 +mem-write: 0x8001370b <- 0x12a2302 +mem-write: 0x8001370f <- 0xf1282303 +mem-write: 0x80013713 <- 0x10041302 +mem-write: 0x80013717 <- 0x6f00 +mem-write: 0x8001371b <- 0x87b71f +mem-write: 0x8001371f <- 0xf7879300 +mem-write: 0x80013723 <- 0xf30ce3ff +mem-write: 0x80013727 <- 0x400793f6 +mem-write: 0x8001372b <- 0xc7da6307 +mem-write: 0x8001372f <- 0x1262304 +mem-write: 0x80013733 <- 0x1242302 +mem-write: 0x80013737 <- 0x1222302 +mem-write: 0x8001373b <- 0x10079302 +mem-write: 0x8001373f <- 0x40006f00 +mem-write: 0x80013743 <- 0x87b715 +mem-write: 0x80013747 <- 0xf7879300 +mem-write: 0x8001374b <- 0xf41c63ff +mem-write: 0x8001374f <- 0xe1282300 +mem-write: 0x80013753 <- 0x112a2302 +mem-write: 0x80013757 <- 0xc12c2303 +mem-write: 0x8001375b <- 0xe12e2303 +mem-write: 0x8001375f <- 0x8ff06f03 +mem-write: 0x80013763 <- 0xc12783ef +mem-write: 0x80013767 <- 0x8063702 +mem-write: 0x8001376b <- 0xc7e7b300 +mem-write: 0x8001376f <- 0xf1262300 +mem-write: 0x80013773 <- 0x40079302 +mem-write: 0x80013777 <- 0x67cce307 +mem-write: 0x8001377b <- 0x30613fa +mem-write: 0x8001377f <- 0x56551300 +mem-write: 0x80013783 <- 0x31340 +mem-write: 0x80013787 <- 0x79300 +mem-write: 0x8001378b <- 0xa7966300 +mem-write: 0x8001378f <- 0xf6759304 +mem-write: 0x80013793 <- 0x25161301 +mem-write: 0x80013797 <- 0x59c6300 +mem-write: 0x8001379b <- 0x30059304 +mem-write: 0x8001379f <- 0x79300 +mem-write: 0x800137a3 <- 0xa585b300 +mem-write: 0x800137a7 <- 0xc68eb340 +mem-write: 0x800137ab <- 0xeae8300 +mem-write: 0x800137af <- 0x17879300 +mem-write: 0x800137b3 <- 0x46869300 +mem-write: 0x800137b7 <- 0xd6ae2300 +mem-write: 0x800137bb <- 0xf5d6e3ff +mem-write: 0x800137bf <- 0x400793fe +mem-write: 0x800137c3 <- 0xa7853300 +mem-write: 0x800137c7 <- 0x10079340 +mem-write: 0x800137cb <- 0xa05c6300 +mem-write: 0x800137cf <- 0x5079306 +mem-write: 0x800137d3 <- 0x6f00 +mem-write: 0x800137d7 <- 0x27959307 +mem-write: 0x800137db <- 0xb805b300 +mem-write: 0x800137df <- 0x5a58300 +mem-write: 0x800137e3 <- 0x17879300 +mem-write: 0x800137e7 <- 0xb3633300 +mem-write: 0x800137eb <- 0x1ff06f00 +mem-write: 0x800137ef <- 0x10793fa +mem-write: 0x800137f3 <- 0xc787b304 +VXDRV: upload 1024 bytes to 0x800137f7 +mem-write: 0x800137f7 <- 0x7a78300 +mem-write: 0x800137fb <- 0xf93fe +mem-write: 0x800137ff <- 0xbf8fb302 +mem-write: 0x80013803 <- 0xf797b340 +mem-write: 0x80013807 <- 0x30069301 +mem-write: 0x8001380b <- 0xf3633300 +mem-write: 0x8001380f <- 0xc8063300 +mem-write: 0x80013813 <- 0xe9300 +mem-write: 0x80013817 <- 0xa686b300 +mem-write: 0x8001381b <- 0x46061340 +mem-write: 0x8001381f <- 0xdec66300 +mem-write: 0x80013823 <- 0x1061302 +mem-write: 0x80013827 <- 0x26969304 +mem-write: 0x8001382b <- 0xd606b300 +mem-write: 0x8001382f <- 0xc1260300 +mem-write: 0x80013833 <- 0x40079302 +mem-write: 0x80013837 <- 0xa787b300 +mem-write: 0x8001383b <- 0xb6563340 +mem-write: 0x8001383f <- 0xc6a02300 +mem-write: 0x80013843 <- 0x400613fe +mem-write: 0x80013847 <- 0xc0006f00 +mem-write: 0x8001384b <- 0xc6278303 +mem-write: 0x8001384f <- 0x62383ff +mem-write: 0x80013853 <- 0x2e929300 +mem-write: 0x80013857 <- 0xb7d7b300 +mem-write: 0x8001385b <- 0xf393b300 +mem-write: 0x8001385f <- 0x5802b301 +mem-write: 0x80013863 <- 0x77e7b300 +mem-write: 0x80013867 <- 0xf2a02300 +mem-write: 0x8001386b <- 0x1e8e9300 +mem-write: 0x8001386f <- 0xdff06f00 +mem-write: 0x80013873 <- 0x279693fa +mem-write: 0x80013877 <- 0xd806b300 +mem-write: 0x8001387b <- 0x6a02300 +mem-write: 0x8001387f <- 0x17879300 +mem-write: 0x80013883 <- 0xc798e300 +mem-write: 0x80013887 <- 0x12683fe +mem-write: 0x8001388b <- 0x6037b302 +mem-write: 0x8001388f <- 0xf6e7b300 +mem-write: 0x80013893 <- 0xf1202300 +mem-write: 0x80013897 <- 0x1278302 +mem-write: 0x8001389b <- 0x41258302 +mem-write: 0x8001389f <- 0xf707b302 +mem-write: 0x800138a3 <- 0xb8863340 +mem-write: 0x800138a7 <- 0xf736b340 +mem-write: 0x800138ab <- 0xc8b53300 +mem-write: 0x800138af <- 0xd6063300 +mem-write: 0x800138b3 <- 0x69340 +mem-write: 0x800138b7 <- 0xf7766300 +mem-write: 0x800138bb <- 0x1588b300 +mem-write: 0x800138bf <- 0x18b69341 +mem-write: 0x800138c3 <- 0xa6e8b300 +mem-write: 0x800138c7 <- 0x81250300 +mem-write: 0x800138cb <- 0x69302 +mem-write: 0x800138cf <- 0xae073300 +mem-write: 0x800138d3 <- 0xee383340 +mem-write: 0x800138d7 <- 0x17073300 +mem-write: 0x800138db <- 0x8866341 +mem-write: 0x800138df <- 0xc50e3300 +mem-write: 0x800138e3 <- 0x1e369341 +mem-write: 0x800138e7 <- 0xc1258300 +mem-write: 0x800138eb <- 0x6e6b302 +mem-write: 0x800138ef <- 0xe12c2301 +mem-write: 0x800138f3 <- 0xbf05b302 +mem-write: 0x800138f7 <- 0xd585b340 +mem-write: 0x800138fb <- 0xb12e2340 +mem-write: 0x800138ff <- 0xc12a2302 +mem-write: 0x80013903 <- 0xf1282302 +mem-write: 0x80013907 <- 0xc1278302 +mem-write: 0x8001390b <- 0xc7971303 +mem-write: 0x8001390f <- 0x7546300 +mem-write: 0x80013913 <- 0x80737d4 +mem-write: 0x80013917 <- 0xf7071300 +mem-write: 0x8001391b <- 0xe7f7b3ff +mem-write: 0x8001391f <- 0xf12e2300 +mem-write: 0x80013923 <- 0x6f02 +mem-write: 0x80013927 <- 0x41280358 +mem-write: 0x8001392b <- 0x81288302 +mem-write: 0x8001392f <- 0xc1268302 +mem-write: 0x80013933 <- 0x3026302 +mem-write: 0x80013937 <- 0x8e83332c +mem-write: 0x8001393b <- 0x4126340 +mem-write: 0x8001393f <- 0x4122830c +mem-write: 0x80013943 <- 0x812f8301 +mem-write: 0x80013947 <- 0xc1250301 +mem-write: 0x8001394b <- 0xf2e63301 +mem-write: 0x8001394f <- 0xa6663301 +mem-write: 0x80013953 <- 0xe6663300 +mem-write: 0x80013957 <- 0x6106300 +mem-write: 0x8001395b <- 0xf1282302 +mem-write: 0x8001395f <- 0x12a2302 +mem-write: 0x80013963 <- 0x112c2303 +mem-write: 0x80013967 <- 0xd12e2303 +mem-write: 0x8001396b <- 0x3041302 +mem-write: 0x8001396f <- 0xe091300 +mem-write: 0x80013973 <- 0x4ff06f00 +mem-write: 0x80013977 <- 0xf30613ce +mem-write: 0x8001397b <- 0x61463ff +mem-write: 0x8001397f <- 0xe7873306 +mem-write: 0x80013983 <- 0x5805b340 +mem-write: 0x80013987 <- 0xe7b33340 +mem-write: 0x8001398b <- 0xb83eb300 +mem-write: 0x8001398f <- 0x65833300 +mem-write: 0x80013993 <- 0x59340 +mem-write: 0x80013997 <- 0xe7f66300 +mem-write: 0x8001399b <- 0x2883300 +mem-write: 0x8001399f <- 0x18359341 +mem-write: 0x800139a3 <- 0xd5e83300 +mem-write: 0x800139a7 <- 0xf885b301 +mem-write: 0x800139ab <- 0xb8b7b341 +mem-write: 0x800139af <- 0x585b300 +mem-write: 0x800139b3 <- 0x8066341 +mem-write: 0x800139b7 <- 0x1f88b300 +mem-write: 0x800139bb <- 0x18b61341 +mem-write: 0x800139bf <- 0xa6853300 +mem-write: 0x800139c3 <- 0xf6663340 +mem-write: 0x800139c7 <- 0xc5053300 +mem-write: 0x800139cb <- 0xa12e2340 +mem-write: 0x800139cf <- 0xb12c2302 +mem-write: 0x800139d3 <- 0x612a2302 +mem-write: 0x800139d7 <- 0xe1282302 +mem-write: 0x800139db <- 0xe091302 +mem-write: 0x800139df <- 0x5ff06f00 +mem-write: 0x800139e3 <- 0x8737d3 +mem-write: 0x800139e7 <- 0xf7071300 +mem-write: 0x800139eb <- 0xe308e3ff +mem-write: 0x800139ef <- 0x400713f6 +mem-write: 0x800139f3 <- 0xc7486307 +mem-write: 0x800139f7 <- 0x603131e +mem-write: 0x800139fb <- 0x6f00 +mem-write: 0x800139ff <- 0x873704 +mem-write: 0x80013a03 <- 0xf7071300 +mem-write: 0x80013a07 <- 0xee9e63ff +mem-write: 0x80013a0b <- 0xf1282300 +mem-write: 0x80013a0f <- 0x12a2302 +mem-write: 0x80013a13 <- 0x112c2303 +mem-write: 0x80013a17 <- 0xd12e2303 +mem-write: 0x80013a1b <- 0xe841302 +mem-write: 0x80013a1f <- 0x1ff06f00 +mem-write: 0x80013a23 <- 0xc12703f5 +mem-write: 0x80013a27 <- 0x8063701 +mem-write: 0x80013a2b <- 0xc7673300 +mem-write: 0x80013a2f <- 0xe12e2300 +mem-write: 0x80013a33 <- 0x40071300 +mem-write: 0x80013a37 <- 0x67466307 +mem-write: 0x80013a3b <- 0x7131a +mem-write: 0x80013a3f <- 0xe34fb302 +mem-write: 0x80013a43 <- 0x29302 +mem-write: 0x80013a47 <- 0x71300 +mem-write: 0x80013a4b <- 0xf74a6300 +mem-write: 0x80013a4f <- 0xf851305 +mem-write: 0x80013a53 <- 0xfd46300 +mem-write: 0x80013a57 <- 0x51300 +mem-write: 0x80013a5b <- 0xf3771300 +mem-write: 0x80013a5f <- 0x2f961301 +mem-write: 0x80013a63 <- 0x71a6300 +mem-write: 0x80013a67 <- 0x30051304 +mem-write: 0x80013a6b <- 0xf5053300 +mem-write: 0x80013a6f <- 0xc5833341 +mem-write: 0x80013a73 <- 0x3230300 +mem-write: 0x80013a77 <- 0x17071300 +mem-write: 0x80013a7b <- 0x45859300 +mem-write: 0x80013a7f <- 0x65ae2300 +mem-write: 0x80013a83 <- 0xe556e3fe +mem-write: 0x80013a87 <- 0x400713fe +mem-write: 0x80013a8b <- 0xf70fb300 +mem-write: 0x80013a8f <- 0x10071341 +mem-write: 0x80013a93 <- 0xf0506300 +mem-write: 0x80013a97 <- 0xf871309 +mem-write: 0x80013a9b <- 0x80006f00 +mem-write: 0x80013a9f <- 0x27161307 +mem-write: 0x80013aa3 <- 0xcf063300 +mem-write: 0x80013aa7 <- 0x6260300 +mem-write: 0x80013aab <- 0x17071300 +mem-write: 0x80013aaf <- 0xc2e2b300 +mem-write: 0x80013ab3 <- 0x9ff06f00 +mem-write: 0x80013ab7 <- 0x713f9 +mem-write: 0x80013abb <- 0xe3633302 +mem-write: 0x80013abf <- 0x1059302 +mem-write: 0x80013ac3 <- 0x25151304 +mem-write: 0x80013ac7 <- 0xa5853300 +mem-write: 0x80013acb <- 0x5258300 +mem-write: 0x80013acf <- 0x393fd +mem-write: 0x80013ad3 <- 0x67073300 +mem-write: 0x80013ad7 <- 0xe595b340 +mem-write: 0x80013adb <- 0xb2e2b300 +mem-write: 0x80013adf <- 0xcf05b300 +mem-write: 0x80013ae3 <- 0x30061300 +mem-write: 0x80013ae7 <- 0xf6063300 +mem-write: 0x80013aeb <- 0x45859341 +mem-write: 0x80013aef <- 0xc3c66300 +mem-write: 0x80013af3 <- 0x1059302 +mem-write: 0x80013af7 <- 0x26161304 +mem-write: 0x80013afb <- 0xc5863300 +mem-write: 0x80013aff <- 0xc1258300 +mem-write: 0x80013b03 <- 0x40071301 +mem-write: 0x80013b07 <- 0xf7073300 +mem-write: 0x80013b0b <- 0x65d33341 +mem-write: 0x80013b0f <- 0x66282300 +mem-write: 0x80013b13 <- 0x300593fc +mem-write: 0x80013b17 <- 0xc0006f00 +mem-write: 0x80013b1b <- 0xc5a50303 +mem-write: 0x80013b1f <- 0x5a903ff +mem-write: 0x80013b23 <- 0x23941300 +mem-write: 0x80013b27 <- 0x65553300 +mem-write: 0x80013b2b <- 0xe9193300 +mem-write: 0x80013b2f <- 0x8f043300 +mem-write: 0x80013b33 <- 0x25653300 +mem-write: 0x80013b37 <- 0xa4202301 +mem-write: 0x80013b3b <- 0x13839300 +mem-write: 0x80013b3f <- 0xdff06f00 +mem-write: 0x80013b43 <- 0x271613fa +mem-write: 0x80013b47 <- 0xcf063300 +mem-write: 0x80013b4b <- 0x6202300 +mem-write: 0x80013b4f <- 0x17071300 +mem-write: 0x80013b53 <- 0xe5d8e300 +mem-write: 0x80013b57 <- 0x12603fe +mem-write: 0x80013b5b <- 0x50373301 +mem-write: 0x80013b5f <- 0xe6673300 +mem-write: 0x80013b63 <- 0xe1282300 +mem-write: 0x80013b67 <- 0x1270300 +mem-write: 0x80013b6b <- 0x41250301 +mem-write: 0x80013b6f <- 0xe7873301 +mem-write: 0x80013b73 <- 0xa805b340 +mem-write: 0x80013b77 <- 0xe7b63340 +mem-write: 0x80013b7b <- 0xb8333300 +mem-write: 0x80013b7f <- 0xc585b300 +mem-write: 0x80013b83 <- 0x61340 +mem-write: 0x80013b87 <- 0xe7f66300 +mem-write: 0x80013b8b <- 0x5083300 +mem-write: 0x80013b8f <- 0x18361341 +mem-write: 0x80013b93 <- 0x81250300 +mem-write: 0x80013b97 <- 0x66683301 +mem-write: 0x80013b9b <- 0x61300 +mem-write: 0x80013b9f <- 0xa887b300 +mem-write: 0x80013ba3 <- 0xf8b33340 +mem-write: 0x80013ba7 <- 0x787b300 +mem-write: 0x80013bab <- 0x8066341 +mem-write: 0x80013baf <- 0x1508b300 +mem-write: 0x80013bb3 <- 0x18b61341 +mem-write: 0x80013bb7 <- 0xc1250300 +mem-write: 0x80013bbb <- 0x66663301 +mem-write: 0x80013bbf <- 0xf12c2300 +mem-write: 0x80013bc3 <- 0xa686b302 +mem-write: 0x80013bc7 <- 0xc686b340 +mem-write: 0x80013bcb <- 0xd12e2340 +mem-write: 0x80013bcf <- 0xb12a2302 +mem-write: 0x80013bd3 <- 0xe1282302 +mem-write: 0x80013bd7 <- 0xe841302 +mem-write: 0x80013bdb <- 0xe091300 +mem-write: 0x80013bdf <- 0x9ff06f00 +mem-write: 0x80013be3 <- 0x12e23d2 +mem-write: 0x80013be7 <- 0x12c2300 +mem-write: 0x80013beb <- 0x12a2300 +mem-write: 0x80013bef <- 0x10071300 +mem-write: 0x80013bf3 <- 0x1ff06f00 +VXDRV: upload 1023 bytes to 0x80013bf7 +mem-write: 0x80013bf7 <- 0x8f37f7 +mem-write: 0x80013bfb <- 0xef061300 +mem-write: 0x80013bff <- 0x140e93ff +mem-write: 0x80013c03 <- 0xcefeb300 +mem-write: 0x80013c07 <- 0x81258300 +mem-write: 0x80013c0b <- 0x41260301 +mem-write: 0x80013c0f <- 0xc1250301 +mem-write: 0x80013c13 <- 0xe9c6301 +mem-write: 0x80013c17 <- 0x1863331c +mem-write: 0x80013c1b <- 0xb66eb301 +mem-write: 0x80013c1f <- 0xd3633300 +mem-write: 0x80013c23 <- 0xaeeeb300 +mem-write: 0x80013c27 <- 0xf3633300 +mem-write: 0x80013c2b <- 0xeeeeb300 +mem-write: 0x80013c2f <- 0x4166300 +mem-write: 0x80013c33 <- 0xe946310 +mem-write: 0x80013c37 <- 0xf1282302 +mem-write: 0x80013c3b <- 0x12a2302 +mem-write: 0x80013c3f <- 0x112c2303 +mem-write: 0x80013c43 <- 0xd12e2303 +mem-write: 0x80013c47 <- 0xe091302 +mem-write: 0x80013c4b <- 0x3166300 +mem-write: 0x80013c4f <- 0x413a0 +mem-write: 0x80013c53 <- 0x91300 +mem-write: 0x80013c57 <- 0xff06f00 +mem-write: 0x80013c5b <- 0x31a63a0 +mem-write: 0x80013c5f <- 0xe1282300 +mem-write: 0x80013c63 <- 0xc12a2302 +mem-write: 0x80013c67 <- 0xb12c2302 +mem-write: 0x80013c6b <- 0x9ff06f02 +mem-write: 0x80013c6f <- 0xf7033383 +mem-write: 0x80013c73 <- 0x603b340 +mem-write: 0x80013c77 <- 0x673fb341 +mem-write: 0x80013c7b <- 0x763eb300 +mem-write: 0x80013c7f <- 0xf38fb300 +mem-write: 0x80013c83 <- 0xf1341 +mem-write: 0x80013c87 <- 0x67746300 +mem-write: 0x80013c8b <- 0x13bf1300 +mem-write: 0x80013c8f <- 0x1582b300 +mem-write: 0x80013c93 <- 0xdf6f3341 +mem-write: 0x80013c97 <- 0x55bab301 +mem-write: 0x80013c9b <- 0xe28a3300 +mem-write: 0x80013c9f <- 0x99341 +mem-write: 0x80013ca3 <- 0xf046300 +mem-write: 0x80013ca7 <- 0x12b99300 +mem-write: 0x80013cab <- 0xd50eb300 +mem-write: 0x80013caf <- 0x59e9b340 +mem-write: 0x80013cb3 <- 0x3e8eb301 +mem-write: 0x80013cb7 <- 0xd12e2341 +mem-write: 0x80013cbb <- 0x412c2303 +mem-write: 0x80013cbf <- 0xf12a2303 +mem-write: 0x80013cc3 <- 0x61282303 +mem-write: 0x80013cc7 <- 0xce9f1302 +mem-write: 0x80013ccb <- 0xf506300 +mem-write: 0x80013ccf <- 0xc8063306 +mem-write: 0x80013cd3 <- 0xe7873340 +mem-write: 0x80013cd7 <- 0xc8333340 +mem-write: 0x80013cdb <- 0xe7b83300 +mem-write: 0x80013cdf <- 0x6063300 +mem-write: 0x80013ce3 <- 0x81341 +mem-write: 0x80013ce7 <- 0xe7f46300 +mem-write: 0x80013ceb <- 0x13b81300 +mem-write: 0x80013cef <- 0x68683300 +mem-write: 0x80013cf3 <- 0xb885b300 +mem-write: 0x80013cf7 <- 0xb8b8b340 +mem-write: 0x80013cfb <- 0x31300 +mem-write: 0x80013cff <- 0x585b300 +mem-write: 0x80013d03 <- 0x8046341 +mem-write: 0x80013d07 <- 0x12b31300 +mem-write: 0x80013d0b <- 0xa6853300 +mem-write: 0x80013d0f <- 0x13633340 +mem-write: 0x80013d13 <- 0x65033301 +mem-write: 0x80013d17 <- 0x612e2340 +mem-write: 0x80013d1b <- 0xb12c2302 +mem-write: 0x80013d1f <- 0xc12a2302 +mem-write: 0x80013d23 <- 0xe1282302 +mem-write: 0x80013d27 <- 0x9ff06f02 +mem-write: 0x80013d2b <- 0xf36333c4 +mem-write: 0x80013d2f <- 0x43633301 +mem-write: 0x80013d33 <- 0xd3633301 +mem-write: 0x80013d37 <- 0x5ff06f01 +mem-write: 0x80013d3b <- 0x10f93f1 +mem-write: 0x80013d3f <- 0xe9e6303 +mem-write: 0x80013d43 <- 0x31e6304 +mem-write: 0x80013d47 <- 0xe12e2302 +mem-write: 0x80013d4b <- 0x12c2303 +mem-write: 0x80013d4f <- 0x12a2302 +mem-write: 0x80013d53 <- 0x1282302 +mem-write: 0x80013d57 <- 0xc1079302 +mem-write: 0x80013d5b <- 0x7a70303 +mem-write: 0x80013d5f <- 0xc7a68300 +mem-write: 0x80013d63 <- 0xc78793ff +mem-write: 0x80013d67 <- 0x371713ff +mem-write: 0x80013d6b <- 0xd6d69300 +mem-write: 0x80013d6f <- 0xd7673301 +mem-write: 0x80013d73 <- 0xe7a22300 +mem-write: 0x80013d77 <- 0xff92e300 +mem-write: 0x80013d7b <- 0x5ff06ffe +mem-write: 0x80013d7f <- 0xf1282383 +mem-write: 0x80013d83 <- 0x12a2302 +mem-write: 0x80013d87 <- 0x112c2303 +mem-write: 0x80013d8b <- 0xd12e2303 +mem-write: 0x80013d8f <- 0xe091302 +mem-write: 0x80013d93 <- 0xff041300 +mem-write: 0x80013d97 <- 0xff06fff +mem-write: 0x80013d9b <- 0x31c638c +mem-write: 0x80013d9f <- 0xe1282300 +mem-write: 0x80013da3 <- 0xc12a2302 +mem-write: 0x80013da7 <- 0xb12c2302 +mem-write: 0x80013dab <- 0xa12e2302 +mem-write: 0x80013daf <- 0x5ff06f02 +mem-write: 0x80013db3 <- 0xe12e23fe +mem-write: 0x80013db7 <- 0x12c2303 +mem-write: 0x80013dbb <- 0x12a2302 +mem-write: 0x80013dbf <- 0x1282302 +mem-write: 0x80013dc3 <- 0xc1079302 +mem-write: 0x80013dc7 <- 0x7a70303 +mem-write: 0x80013dcb <- 0xc7a68300 +mem-write: 0x80013dcf <- 0xc78793ff +mem-write: 0x80013dd3 <- 0x371713ff +mem-write: 0x80013dd7 <- 0xd6d69300 +mem-write: 0x80013ddb <- 0xd7673301 +mem-write: 0x80013ddf <- 0xe7a22300 +mem-write: 0x80013de3 <- 0xff92e300 +mem-write: 0x80013de7 <- 0x8ff06ffe +mem-write: 0x80013deb <- 0xf70eb3fc +mem-write: 0x80013def <- 0x609b340 +mem-write: 0x80013df3 <- 0xd732b341 +mem-write: 0x80013df7 <- 0x363f3301 +mem-write: 0x80013dfb <- 0x5982b301 +mem-write: 0x80013dff <- 0xf9340 +mem-write: 0x80013e03 <- 0xd7746300 +mem-write: 0x80013e07 <- 0x19bf9301 +mem-write: 0x80013e0b <- 0x1583b300 +mem-write: 0x80013e0f <- 0xefefb341 +mem-write: 0x80013e13 <- 0x75bb3301 +mem-write: 0x80013e17 <- 0xf38ab300 +mem-write: 0x80013e1b <- 0xa1341 +mem-write: 0x80013e1f <- 0xf846300 +mem-write: 0x80013e23 <- 0x13ba1300 +mem-write: 0x80013e27 <- 0xd50f3300 +mem-write: 0x80013e2b <- 0x6a6a3340 +mem-write: 0x80013e2f <- 0x4f0f3301 +mem-write: 0x80013e33 <- 0xe12e2341 +mem-write: 0x80013e37 <- 0x512c2303 +mem-write: 0x80013e3b <- 0x512a2303 +mem-write: 0x80013e3f <- 0xd1282302 +mem-write: 0x80013e43 <- 0xcf1f9303 +mem-write: 0x80013e47 <- 0xfd06300 +mem-write: 0x80013e4b <- 0xc806330c +mem-write: 0x80013e4f <- 0xe7873340 +mem-write: 0x80013e53 <- 0xc83eb340 +mem-write: 0x80013e57 <- 0xe7b83300 +mem-write: 0x80013e5b <- 0x6063300 +mem-write: 0x80013e5f <- 0x81341 +mem-write: 0x80013e63 <- 0xe7f46300 +mem-write: 0x80013e67 <- 0x19b81300 +mem-write: 0x80013e6b <- 0xb885b300 +mem-write: 0x80013e6f <- 0xd8683340 +mem-write: 0x80013e73 <- 0xb8b8b301 +mem-write: 0x80013e77 <- 0x585b300 +mem-write: 0x80013e7b <- 0x8046341 +mem-write: 0x80013e7f <- 0x13b31300 +mem-write: 0x80013e83 <- 0xa6853300 +mem-write: 0x80013e87 <- 0x1366b340 +mem-write: 0x80013e8b <- 0xd506b301 +mem-write: 0x80013e8f <- 0xd12e2340 +mem-write: 0x80013e93 <- 0xb12c2302 +mem-write: 0x80013e97 <- 0xc12a2302 +mem-write: 0x80013e9b <- 0xe1282302 +mem-write: 0x80013e9f <- 0xe091302 +mem-write: 0x80013ea3 <- 0xc1250300 +mem-write: 0x80013ea7 <- 0x50a6303 +mem-write: 0x80013eab <- 0x1000ef06 +mem-write: 0x80013eaf <- 0x45079324 +mem-write: 0x80013eb3 <- 0x613ff +mem-write: 0x80013eb7 <- 0xf7f69302 +mem-write: 0x80013ebb <- 0xc7c73301 +mem-write: 0x80013ebf <- 0x68a6302 +mem-write: 0x80013ec3 <- 0xc0069308 +mem-write: 0x80013ec7 <- 0x10313ff +mem-write: 0x80013ecb <- 0x27151303 +mem-write: 0x80013ecf <- 0xc7e83300 +mem-write: 0x80013ed3 <- 0xd706b302 +mem-write: 0x80013ed7 <- 0x6063302 +mem-write: 0x80013edb <- 0xc6869341 +mem-write: 0x80013edf <- 0xd306b300 +mem-write: 0x80013ee3 <- 0xd3106300 +mem-write: 0x80013ee7 <- 0x106930a +mem-write: 0x80013eeb <- 0xa6853304 +mem-write: 0x80013eef <- 0x1268300 +mem-write: 0x80013ef3 <- 0xf7071303 +mem-write: 0x80013ef7 <- 0x696b3ff +mem-write: 0x80013efb <- 0xd5282301 +mem-write: 0x80013eff <- 0xf00613fe +mem-write: 0x80013f03 <- 0x80006fff +mem-write: 0x80013f07 <- 0x5eeeb30b +mem-write: 0x80013f0b <- 0x5eeeb300 +mem-write: 0x80013f0f <- 0xeeeeb301 +mem-write: 0x80013f13 <- 0xe8ee301 +mem-write: 0x80013f17 <- 0xdff06fd2 +mem-write: 0x80013f1b <- 0x812503f8 +mem-write: 0x80013f1f <- 0x5086303 +mem-write: 0x80013f23 <- 0x9000ef00 +mem-write: 0x80013f27 <- 0x505131c +mem-write: 0x80013f2b <- 0x5ff06f02 +mem-write: 0x80013f2f <- 0x412503f8 +mem-write: 0x80013f33 <- 0x5086303 +mem-write: 0x80013f37 <- 0x5000ef00 +mem-write: 0x80013f3b <- 0x505131b +mem-write: 0x80013f3f <- 0x1ff06f04 +mem-write: 0x80013f43 <- 0x12503f7 +mem-write: 0x80013f47 <- 0x5000ef03 +mem-write: 0x80013f4b <- 0x505131a +mem-write: 0x80013f4f <- 0x1ff06f06 +mem-write: 0x80013f53 <- 0xc00593f6 +mem-write: 0x80013f57 <- 0xb705b3ff +mem-write: 0x80013f5b <- 0xc1069302 +mem-write: 0x80013f5f <- 0x30061303 +mem-write: 0x80013f63 <- 0xb6853300 +mem-write: 0x80013f67 <- 0x5250300 +mem-write: 0x80013f6b <- 0xf6061300 +mem-write: 0x80013f6f <- 0xc68693ff +mem-write: 0x80013f73 <- 0xa6a223ff +mem-write: 0x80013f77 <- 0xe656e300 +mem-write: 0x80013f7b <- 0xf70713fe +mem-write: 0x80013f7f <- 0x1ff06fff +mem-write: 0x80013f83 <- 0xc6a583f8 +mem-write: 0x80013f87 <- 0x6a883ff +mem-write: 0x80013f8b <- 0xa68e3300 +mem-write: 0x80013f8f <- 0xc5d5b300 +mem-write: 0x80013f93 <- 0x898b300 +mem-write: 0x80013f97 <- 0x15e5b301 +mem-write: 0x80013f9b <- 0xbe202301 +mem-write: 0x80013f9f <- 0xc6869300 +mem-write: 0x80013fa3 <- 0x1ff06fff +mem-write: 0x80013fa7 <- 0x271693f4 +mem-write: 0x80013fab <- 0x1059300 +mem-write: 0x80013faf <- 0xd586b303 +mem-write: 0x80013fb3 <- 0x6a02300 +mem-write: 0x80013fb7 <- 0xf7071300 +mem-write: 0x80013fbb <- 0xc716e3ff +mem-write: 0x80013fbf <- 0x87cc63fe +mem-write: 0x80013fc3 <- 0x87843314 +mem-write: 0x80013fc7 <- 0x14041340 +mem-write: 0x80013fcb <- 0x71300 +mem-write: 0x80013fcf <- 0xe4453302 +mem-write: 0x80013fd3 <- 0x81302 +mem-write: 0x80013fd7 <- 0x79300 +mem-write: 0x80013fdb <- 0xa7ce6300 +mem-write: 0x80013fdf <- 0x5061304 +mem-write: 0x80013fe3 <- 0x5546300 +mem-write: 0x80013fe7 <- 0x61300 +mem-write: 0x80013feb <- 0xf4779300 +mem-write: 0x80013fef <- 0x25169301 +mem-write: 0x80013ff3 <- 0x1f906300 +VXDRV: upload 1024 bytes to 0x80013ff6 +mem-write: 0x80013ff6 <- 0x6130607 +mem-write: 0x80013ffa <- 0x7930030 +mem-write: 0x80013ffe <- 0x7130301 +mem-write: 0x80014002 <- 0x6330000 +mem-write: 0x80014006 <- 0x85b340a6 +mem-write: 0x8001400a <- 0xa58300d7 +mem-write: 0x8001400e <- 0x7130005 +mem-write: 0x80014012 <- 0x87930017 +mem-write: 0x80014016 <- 0xae230047 +mem-write: 0x8001401a <- 0x56e3feb7 +mem-write: 0x8001401e <- 0x713fee6 +mem-write: 0x80014022 <- 0x5330040 +mem-write: 0x80014026 <- 0x71340a7 +mem-write: 0x8001402a <- 0x54630010 +mem-write: 0x8001402e <- 0x71308a0 +mem-write: 0x80014032 <- 0x6f0005 +mem-write: 0x80014036 <- 0x97130800 +mem-write: 0x8001403a <- 0x6930027 +mem-write: 0x8001403e <- 0x87330301 +mem-write: 0x80014042 <- 0x270300e6 +mem-write: 0x80014046 <- 0x87930007 +mem-write: 0x8001404a <- 0x68330017 +mem-write: 0x8001404e <- 0xf06f00e8 +mem-write: 0x80014052 <- 0x593f8df +mem-write: 0x80014056 <- 0x64330200 +mem-write: 0x8001405a <- 0x79302b4 +mem-write: 0x8001405e <- 0x16130401 +mem-write: 0x80014062 <- 0x86330026 +mem-write: 0x80014066 <- 0x278300c7 +mem-write: 0x8001406a <- 0x713ff06 +mem-write: 0x8001406e <- 0x85b30000 +mem-write: 0x80014072 <- 0x97b34085 +mem-write: 0x80014076 <- 0x683300b7 +mem-write: 0x8001407a <- 0x79300f8 +mem-write: 0x8001407e <- 0x86b30301 +mem-write: 0x80014082 <- 0x79300d7 +mem-write: 0x80014086 <- 0x87b30030 +mem-write: 0x8001408a <- 0x869340a7 +mem-write: 0x8001408e <- 0x46630046 +mem-write: 0x80014092 <- 0x69302f7 +mem-write: 0x80014096 <- 0x97930401 +mem-write: 0x8001409a <- 0x87b30027 +mem-write: 0x8001409e <- 0x268300f6 +mem-write: 0x800140a2 <- 0x71303c1 +mem-write: 0x800140a6 <- 0x7330040 +mem-write: 0x800140aa <- 0xd43340a7 +mem-write: 0x800140ae <- 0xa8230086 +mem-write: 0x800140b2 <- 0x693fe87 +mem-write: 0x800140b6 <- 0x6f0030 +mem-write: 0x800140ba <- 0x18930440 +mem-write: 0x800140be <- 0x6130027 +mem-write: 0x800140c2 <- 0xa3030301 +mem-write: 0x800140c6 <- 0x8b30006 +mem-write: 0x800140ca <- 0xa6030116 +mem-write: 0x800140ce <- 0x1333ffc6 +mem-write: 0x800140d2 <- 0x71300b3 +mem-write: 0x800140d6 <- 0x56330017 +mem-write: 0x800140da <- 0x66330086 +mem-write: 0x800140de <- 0xa0230066 +mem-write: 0x800140e2 <- 0xf06f00c8 +mem-write: 0x800140e6 <- 0x1793fa9f +mem-write: 0x800140ea <- 0x6130027 +mem-write: 0x800140ee <- 0x7b30301 +mem-write: 0x800140f2 <- 0xa02300f6 +mem-write: 0x800140f6 <- 0x7130007 +mem-write: 0x800140fa <- 0xd6e30017 +mem-write: 0x800140fe <- 0x2703fee6 +mem-write: 0x80014102 <- 0x37b30301 +mem-write: 0x80014106 <- 0x4130100 +mem-write: 0x8001410a <- 0x67b30000 +mem-write: 0x8001410e <- 0x282300f7 +mem-write: 0x80014112 <- 0xe06f02f1 +mem-write: 0x80014116 <- 0x433d45f +mem-write: 0x8001411a <- 0x278340f4 +mem-write: 0x8001411e <- 0x73703c1 +mem-write: 0x80014122 <- 0x713fff8 +mem-write: 0x80014126 <- 0xf7b3fff7 +mem-write: 0x8001412a <- 0x2e2300e7 +mem-write: 0x8001412e <- 0xe06f02f1 +mem-write: 0x80014132 <- 0x2e23d29f +mem-write: 0x80014136 <- 0x2c230201 +mem-write: 0x8001413a <- 0x2a230201 +mem-write: 0x8001413e <- 0x28230201 +mem-write: 0x80014142 <- 0xe06f0201 +mem-write: 0x80014146 <- 0x2783d95f +mem-write: 0x8001414a <- 0x27030085 +mem-write: 0x8001414e <- 0x26830045 +mem-write: 0x80014152 <- 0x260300c5 +mem-write: 0x80014156 <- 0x1130005 +mem-write: 0x8001415a <- 0x2223fe01 +mem-write: 0x8001415e <- 0x242300e1 +mem-write: 0x80014162 <- 0x2c2300f1 +mem-write: 0x80014166 <- 0x473700f1 +mem-write: 0x8001416a <- 0x97930000 +mem-write: 0x8001416e <- 0xd5930016 +mem-write: 0x80014172 <- 0x20230117 +mem-write: 0x80014176 <- 0x262300c1 +mem-write: 0x8001417a <- 0x282300d1 +mem-write: 0x8001417e <- 0x79300c1 +mem-write: 0x80014182 <- 0x513ffe7 +mem-write: 0x80014186 <- 0xde630000 +mem-write: 0x8001418a <- 0x79300b7 +mem-write: 0x8001418e <- 0xd81301d7 +mem-write: 0x80014192 <- 0xdc6301f6 +mem-write: 0x80014196 <- 0x53700b7 +mem-write: 0x8001419a <- 0x45138000 +mem-write: 0x8001419e <- 0x533fff5 +mem-write: 0x800141a2 <- 0x11300a8 +mem-write: 0x800141a6 <- 0x80670201 +mem-write: 0x800141aa <- 0x96930000 +mem-write: 0x800141ae <- 0x7b70106 +mem-write: 0x800141b2 <- 0xd6930001 +mem-write: 0x800141b6 <- 0xe6b30106 +mem-write: 0x800141ba <- 0x79300f6 +mem-write: 0x800141be <- 0x87b306f7 +mem-write: 0x800141c2 <- 0xd71340b7 +mem-write: 0x800141c6 <- 0x2e234057 +mem-write: 0x800141ca <- 0xf79300d1 +mem-write: 0x800141ce <- 0x886301f7 +mem-write: 0x800141d2 <- 0x5130407 +mem-write: 0x800141d6 <- 0x8930200 +mem-write: 0x800141da <- 0x533ffe7 +mem-write: 0x800141de <- 0x171340f5 +mem-write: 0x800141e2 <- 0xe130027 +mem-write: 0x800141e6 <- 0x95330201 +mem-write: 0x800141ea <- 0x31300a6 +mem-write: 0x800141ee <- 0x5930000 +mem-write: 0x800141f2 <- 0xb8930000 +mem-write: 0x800141f6 <- 0x7330018 +mem-write: 0x800141fa <- 0xc46300ee +mem-write: 0x800141fe <- 0x4630515 +mem-write: 0x80014202 <- 0x28230003 +mem-write: 0x80014206 <- 0x959300c1 +mem-write: 0x8001420a <- 0x7130025 +mem-write: 0x8001420e <- 0x5b30201 +mem-write: 0x80014212 <- 0xd6b300b7 +mem-write: 0x80014216 <- 0xa82300f6 +mem-write: 0x8001421a <- 0x6ffed5 +mem-write: 0x8001421e <- 0x7930180 +mem-write: 0x80014222 <- 0x17130201 +mem-write: 0x80014226 <- 0x87330027 +mem-write: 0x8001422a <- 0x278300e7 +mem-write: 0x8001422e <- 0x2823ff07 +mem-write: 0x80014232 <- 0x250300f1 +mem-write: 0x80014236 <- 0x6e30101 +mem-write: 0x8001423a <- 0x533f608 +mem-write: 0x8001423e <- 0xf06f40a0 +mem-write: 0x80014242 <- 0x2603f65f +mem-write: 0x80014246 <- 0x313ff07 +mem-write: 0x8001424a <- 0x5930010 +mem-write: 0x8001424e <- 0x56330010 +mem-write: 0x80014252 <- 0x663300f6 +mem-write: 0x80014256 <- 0xf06f00a6 +mem-write: 0x8001425a <- 0x113fa5f +mem-write: 0x8001425e <- 0x2223fd01 +mem-write: 0x80014262 <- 0x26230291 +mem-write: 0x80014266 <- 0x24230211 +mem-write: 0x8001426a <- 0x20230281 +mem-write: 0x8001426e <- 0x4930321 +mem-write: 0x80014272 <- 0x80630005 +mem-write: 0x80014276 <- 0xd7931205 +mem-write: 0x8001427a <- 0xc43341f5 +mem-write: 0x8001427e <- 0x43300b7 +mem-write: 0x80014282 <- 0x51340f4 +mem-write: 0x80014286 <- 0xd9130004 +mem-write: 0x8001428a <- 0xef01f5 +mem-write: 0x8001428e <- 0x47376600 +mem-write: 0x80014292 <- 0x7130000 +mem-write: 0x80014296 <- 0x79301e7 +mem-write: 0x8001429a <- 0x5b30515 +mem-write: 0x8001429e <- 0x282340a7 +mem-write: 0x800142a2 <- 0xd7130081 +mem-write: 0x800142a6 <- 0x2a234057 +mem-write: 0x800142aa <- 0x2c230001 +mem-write: 0x800142ae <- 0x2e230001 +mem-write: 0x800142b2 <- 0xf7930001 +mem-write: 0x800142b6 <- 0x8c6301f7 +mem-write: 0x800142ba <- 0x6930207 +mem-write: 0x800142be <- 0x16630020 +mem-write: 0x800142c2 <- 0x6930cd7 +mem-write: 0x800142c6 <- 0x86b30200 +mem-write: 0x800142ca <- 0x56b340f6 +mem-write: 0x800142ce <- 0x2e2300d4 +mem-write: 0x800142d2 <- 0x69300d1 +mem-write: 0x800142d6 <- 0x613fff7 +mem-write: 0x800142da <- 0x17130201 +mem-write: 0x800142de <- 0x7330027 +mem-write: 0x800142e2 <- 0x17b300e6 +mem-write: 0x800142e6 <- 0x282300f4 +mem-write: 0x800142ea <- 0x6ffef7 +mem-write: 0x800142ee <- 0x7930340 +mem-write: 0x800142f2 <- 0x87b30030 +mem-write: 0x800142f6 <- 0x69340e7 +mem-write: 0x800142fa <- 0x97930201 +mem-write: 0x800142fe <- 0x87b30027 +mem-write: 0x80014302 <- 0xa78300f6 +mem-write: 0x80014306 <- 0x693ff07 +mem-write: 0x8001430a <- 0x2e230020 +mem-write: 0x8001430e <- 0x79300f1 +mem-write: 0x80014312 <- 0x16630020 +mem-write: 0x80014316 <- 0x2c2300f7 +mem-write: 0x8001431a <- 0x6930081 +mem-write: 0x8001431e <- 0x7930010 +mem-write: 0x80014322 <- 0x9713fff0 +mem-write: 0x80014326 <- 0x6130026 +mem-write: 0x8001432a <- 0x7330101 +mem-write: 0x8001432e <- 0x202300e6 +mem-write: 0x80014332 <- 0x86930007 +mem-write: 0x80014336 <- 0x96e3fff6 +mem-write: 0x8001433a <- 0x2783fef6 +mem-write: 0x8001433e <- 0x208301c1 +mem-write: 0x80014342 <- 0x240302c1 +mem-write: 0x80014346 <- 0x16230281 +mem-write: 0x8001434a <- 0x179300f1 +mem-write: 0x8001434e <- 0xe5b300f9 +mem-write: 0x80014352 <- 0x278300b7 +mem-write: 0x80014356 <- 0x17230101 +mem-write: 0x8001435a <- 0x290300b1 +mem-write: 0x8001435e <- 0xa0230201 +mem-write: 0x80014362 <- 0x278300f4 +mem-write: 0x80014366 <- 0x85130141 +mem-write: 0x8001436a <- 0xa2230004 +mem-write: 0x8001436e <- 0x278300f4 +mem-write: 0x80014372 <- 0xa4230181 +mem-write: 0x80014376 <- 0x278300f4 +mem-write: 0x8001437a <- 0xa62300c1 +mem-write: 0x8001437e <- 0x248300f4 +mem-write: 0x80014382 <- 0x1130241 +mem-write: 0x80014386 <- 0x80670301 +mem-write: 0x8001438a <- 0x7130000 +mem-write: 0x8001438e <- 0xf06f0030 +mem-write: 0x80014392 <- 0x2e23f45f +mem-write: 0x80014396 <- 0x2c230001 +mem-write: 0x8001439a <- 0x2a230001 +mem-write: 0x8001439e <- 0x28230001 +mem-write: 0x800143a2 <- 0x9130001 +mem-write: 0x800143a6 <- 0xf06f0000 +mem-write: 0x800143aa <- 0x5793f95f +mem-write: 0x800143ae <- 0x17130146 +mem-write: 0x800143b2 <- 0xf79300c6 +mem-write: 0x800143b6 <- 0x1137ff7 +mem-write: 0x800143ba <- 0x5713fd01 +mem-write: 0x800143be <- 0x869300c7 +mem-write: 0x800143c2 <- 0x24230017 +mem-write: 0x800143c6 <- 0x22230281 +mem-write: 0x800143ca <- 0x20230291 +mem-write: 0x800143ce <- 0x26230321 +mem-write: 0x800143d2 <- 0x28230211 +mem-write: 0x800143d6 <- 0x2a2300b1 +mem-write: 0x800143da <- 0x2e2300e1 +mem-write: 0x800143de <- 0x2c230001 +mem-write: 0x800143e2 <- 0xf6930001 +mem-write: 0x800143e6 <- 0x9137fe6 +mem-write: 0x800143ea <- 0x84130005 +mem-write: 0x800143ee <- 0x54930005 +mem-write: 0x800143f2 <- 0x826301f6 +VXDRV: upload 1024 bytes to 0x800143f6 +mem-write: 0x800143f6 <- 0x46b70806 +mem-write: 0x800143fa <- 0x86930000 +mem-write: 0x800143fe <- 0x87b3c006 +mem-write: 0x80014402 <- 0xd51300d7 +mem-write: 0x80014406 <- 0x56930045 +mem-write: 0x8001440a <- 0x17130047 +mem-write: 0x8001440e <- 0x673301c7 +mem-write: 0x80014412 <- 0x941300a7 +mem-write: 0x80014416 <- 0x2e2301c5 +mem-write: 0x8001441a <- 0x2c2300d1 +mem-write: 0x8001441e <- 0x2a2300e1 +mem-write: 0x80014422 <- 0x28230081 +mem-write: 0x80014426 <- 0x94930001 +mem-write: 0x8001442a <- 0xe7b300f4 +mem-write: 0x8001442e <- 0x172300f4 +mem-write: 0x80014432 <- 0x278300f1 +mem-write: 0x80014436 <- 0x27030101 +mem-write: 0x8001443a <- 0x208301c1 +mem-write: 0x8001443e <- 0x202302c1 +mem-write: 0x80014442 <- 0x278300f9 +mem-write: 0x80014446 <- 0x16230141 +mem-write: 0x8001444a <- 0x240300e1 +mem-write: 0x8001444e <- 0x22230281 +mem-write: 0x80014452 <- 0x278300f9 +mem-write: 0x80014456 <- 0x24830181 +mem-write: 0x8001445a <- 0x5130241 +mem-write: 0x8001445e <- 0x24230009 +mem-write: 0x80014462 <- 0x278300f9 +mem-write: 0x80014466 <- 0x262300c1 +mem-write: 0x8001446a <- 0x290300f9 +mem-write: 0x8001446e <- 0x1130201 +mem-write: 0x80014472 <- 0x80670301 +mem-write: 0x80014476 <- 0x65330000 +mem-write: 0x8001447a <- 0x946300b7 +mem-write: 0x8001447e <- 0x4e30e07 +mem-write: 0x80014482 <- 0xc63fa05 +mem-write: 0x80014486 <- 0x5130407 +mem-write: 0x8001448a <- 0xef0007 +mem-write: 0x8001448e <- 0x5934600 +mem-write: 0x80014492 <- 0xd7130315 +mem-write: 0x80014496 <- 0xf5934055 +mem-write: 0x8001449a <- 0x866301f5 +mem-write: 0x8001449e <- 0x6930405 +mem-write: 0x800144a2 <- 0x6b3ffc0 +mem-write: 0x800144a6 <- 0x31302d7 +mem-write: 0x800144aa <- 0x8130101 +mem-write: 0x800144ae <- 0x16130200 +mem-write: 0x800144b2 <- 0x8330027 +mem-write: 0x800144b6 <- 0x869340b8 +mem-write: 0x800144ba <- 0x6b300c6 +mem-write: 0x800144be <- 0x106300d3 +mem-write: 0x800144c2 <- 0x79308d3 +mem-write: 0x800144c6 <- 0x86330201 +mem-write: 0x800144ca <- 0x15b300c7 +mem-write: 0x800144ce <- 0x71300b4 +mem-write: 0x800144d2 <- 0x2823fff7 +mem-write: 0x800144d6 <- 0x6ffeb6 +mem-write: 0x800144da <- 0xef03c0 +mem-write: 0x800144de <- 0x5134100 +mem-write: 0x800144e2 <- 0xf06f0205 +mem-write: 0x800144e6 <- 0x613fadf +mem-write: 0x800144ea <- 0x633ffc0 +mem-write: 0x800144ee <- 0x79302c7 +mem-write: 0x800144f2 <- 0x69301c1 +mem-write: 0x800144f6 <- 0x85b30030 +mem-write: 0x800144fa <- 0xa58300c7 +mem-write: 0x800144fe <- 0x86930005 +mem-write: 0x80014502 <- 0x8793fff6 +mem-write: 0x80014506 <- 0xa223ffc7 +mem-write: 0x8001450a <- 0xd6e300b7 +mem-write: 0x8001450e <- 0x713fee6 +mem-write: 0x80014512 <- 0x693fff7 +mem-write: 0x80014516 <- 0x1793fff0 +mem-write: 0x8001451a <- 0x6130027 +mem-write: 0x8001451e <- 0x7b30101 +mem-write: 0x80014522 <- 0xa02300f6 +mem-write: 0x80014526 <- 0x7130007 +mem-write: 0x8001452a <- 0x16e3fff7 +mem-write: 0x8001452e <- 0x47b7fed7 +mem-write: 0x80014532 <- 0x87930000 +mem-write: 0x80014536 <- 0x87b3c0c7 +mem-write: 0x8001453a <- 0xf06f40a7 +mem-write: 0x8001453e <- 0xa783eedf +mem-write: 0x80014542 <- 0xa883ffc6 +mem-write: 0x80014546 <- 0x8e330006 +mem-write: 0x8001454a <- 0xd7b300c6 +mem-write: 0x8001454e <- 0x98b30107 +mem-write: 0x80014552 <- 0xe7b300b8 +mem-write: 0x80014556 <- 0x20230117 +mem-write: 0x8001455a <- 0x869300fe +mem-write: 0x8001455e <- 0xf06fffc6 +mem-write: 0x80014562 <- 0x87b7f61f +mem-write: 0x80014566 <- 0x8630000 +mem-write: 0x8001456a <- 0x17930205 +mem-write: 0x8001456e <- 0xd69301c7 +mem-write: 0x80014572 <- 0xe7b30045 +mem-write: 0x80014576 <- 0x2c2300d7 +mem-write: 0x8001457a <- 0x571300f1 +mem-write: 0x8001457e <- 0x87b70047 +mem-write: 0x80014582 <- 0x94130000 +mem-write: 0x80014586 <- 0x673301c5 +mem-write: 0x8001458a <- 0x2a2300f7 +mem-write: 0x8001458e <- 0x28230081 +mem-write: 0x80014592 <- 0x2e230001 +mem-write: 0x80014596 <- 0x879300e1 +mem-write: 0x8001459a <- 0xf06ffff7 +mem-write: 0x8001459e <- 0x2583e8df +mem-write: 0x800145a2 <- 0x278300c5 +mem-write: 0x800145a6 <- 0x27030085 +mem-write: 0x800145aa <- 0x1130045 +mem-write: 0x800145ae <- 0x2683fe01 +mem-write: 0x800145b2 <- 0x24230005 +mem-write: 0x800145b6 <- 0x2c2300f1 +mem-write: 0x800145ba <- 0x979300f1 +mem-write: 0x800145be <- 0x22230105 +mem-write: 0x800145c2 <- 0x2a2300e1 +mem-write: 0x800145c6 <- 0xd79300e1 +mem-write: 0x800145ca <- 0x97130107 +mem-write: 0x800145ce <- 0x26230015 +mem-write: 0x800145d2 <- 0x202300b1 +mem-write: 0x800145d6 <- 0x282300d1 +mem-write: 0x800145da <- 0x2e2300d1 +mem-write: 0x800145de <- 0x571300f1 +mem-write: 0x800145e2 <- 0xd5930117 +mem-write: 0x800145e6 <- 0x81301f5 +mem-write: 0x800145ea <- 0x6130101 +mem-write: 0x800145ee <- 0x278301c1 +mem-write: 0x800145f2 <- 0x26830006 +mem-write: 0x800145f6 <- 0x613ffc6 +mem-write: 0x800145fa <- 0x9793ffc6 +mem-write: 0x800145fe <- 0xd6930037 +mem-write: 0x80014602 <- 0xe7b301d6 +mem-write: 0x80014606 <- 0x222300d7 +mem-write: 0x8001460a <- 0x12e300f6 +mem-write: 0x8001460e <- 0x2683fec8 +mem-write: 0x80014612 <- 0x7930101 +mem-write: 0x80014616 <- 0x95130017 +mem-write: 0x8001461a <- 0x86b70036 +mem-write: 0x8001461e <- 0x86930000 +mem-write: 0x80014622 <- 0x2823ffe6 +mem-write: 0x80014626 <- 0xf7b300a1 +mem-write: 0x8001462a <- 0x846300d7 +mem-write: 0x8001462e <- 0xc7b71c07 +mem-write: 0x80014632 <- 0x8793ffff +mem-write: 0x80014636 <- 0x7334007 +mem-write: 0x8001463a <- 0x79300f7 +mem-write: 0x8001463e <- 0xc6637fe0 +mem-write: 0x80014642 <- 0x586320e7 +mem-write: 0x80014646 <- 0x280306e0 +mem-write: 0x8001464a <- 0x26030181 +mem-write: 0x8001464e <- 0x278301c1 +mem-write: 0x80014652 <- 0x56930141 +mem-write: 0x80014656 <- 0x161301c8 +mem-write: 0x8001465a <- 0x66330046 +mem-write: 0x8001465e <- 0x969300d6 +mem-write: 0x80014662 <- 0xe6b30047 +mem-write: 0x80014666 <- 0xd79300a6 +mem-write: 0x8001466a <- 0x181301c7 +mem-write: 0x8001466e <- 0x36b30048 +mem-write: 0x80014672 <- 0xe7b300d0 +mem-write: 0x80014676 <- 0xe6b30107 +mem-write: 0x8001467a <- 0x2a2300f6 +mem-write: 0x8001467e <- 0x282300c1 +mem-write: 0x80014682 <- 0x268300d1 +mem-write: 0x80014686 <- 0x27830101 +mem-write: 0x8001468a <- 0xf6130141 +mem-write: 0x8001468e <- 0x4630076 +mem-write: 0x80014692 <- 0xf6131c06 +mem-write: 0x80014696 <- 0x51300f6 +mem-write: 0x8001469a <- 0xe630040 +mem-write: 0x8001469e <- 0x86131aa6 +mem-write: 0x800146a2 <- 0x36b30046 +mem-write: 0x800146a6 <- 0x87b300d6 +mem-write: 0x800146aa <- 0x69300d7 +mem-write: 0x800146ae <- 0x6f0006 +mem-write: 0x800146b2 <- 0x7931a80 +mem-write: 0x800146b6 <- 0x5c63fcc0 +mem-write: 0x800146ba <- 0x2a2300f7 +mem-write: 0x800146be <- 0x7930001 +mem-write: 0x800146c2 <- 0x28230010 +mem-write: 0x800146c6 <- 0x71300f1 +mem-write: 0x800146ca <- 0xf06f0000 +mem-write: 0x800146ce <- 0x2783fb9f +mem-write: 0x800146d2 <- 0xf3701c1 +mem-write: 0x800146d6 <- 0x6930008 +mem-write: 0x800146da <- 0x6f3303d0 +mem-write: 0x800146de <- 0x86b300ff +mem-write: 0x800146e2 <- 0x2e2340e6 +mem-write: 0x800146e6 <- 0xde9301e1 +mem-write: 0x800146ea <- 0x7134056 +mem-write: 0x800146ee <- 0x7930008 +mem-write: 0x800146f2 <- 0xe130000 +mem-write: 0x800146f6 <- 0x25030000 +mem-write: 0x800146fa <- 0x87930007 +mem-write: 0x800146fe <- 0x7130017 +mem-write: 0x80014702 <- 0x6e330047 +mem-write: 0x80014706 <- 0x98e300ae +mem-write: 0x8001470a <- 0xf713fefe +mem-write: 0x8001470e <- 0x969301f6 +mem-write: 0x80014712 <- 0x1063002e +mem-write: 0x80014716 <- 0x7130407 +mem-write: 0x8001471a <- 0x7930030 +mem-write: 0x8001471e <- 0x7330000 +mem-write: 0x80014722 <- 0x53341d7 +mem-write: 0x80014726 <- 0x250300d6 +mem-write: 0x8001472a <- 0x87930005 +mem-write: 0x8001472e <- 0x6130017 +mem-write: 0x80014732 <- 0x2e230046 +mem-write: 0x80014736 <- 0x56e3fea6 +mem-write: 0x8001473a <- 0x713fef7 +mem-write: 0x8001473e <- 0x7330040 +mem-write: 0x80014742 <- 0x79341d7 +mem-write: 0x80014746 <- 0x5e630010 +mem-write: 0x8001474a <- 0x79304e0 +mem-write: 0x8001474e <- 0x6f0007 +mem-write: 0x80014752 <- 0x7930540 +mem-write: 0x80014756 <- 0x87b30201 +mem-write: 0x8001475a <- 0xa78300d7 +mem-write: 0x8001475e <- 0x313ff07 +mem-write: 0x80014762 <- 0x3330200 +mem-write: 0x80014766 <- 0x97b340e3 +mem-write: 0x8001476a <- 0x6330067 +mem-write: 0x8001476e <- 0x69300d8 +mem-write: 0x80014772 <- 0x6e330030 +mem-write: 0x80014776 <- 0x89300fe +mem-write: 0x8001477a <- 0x86b30000 +mem-write: 0x8001477e <- 0x61341d6 +mem-write: 0x80014782 <- 0xc4630046 +mem-write: 0x80014786 <- 0x969304d8 +mem-write: 0x8001478a <- 0x6130026 +mem-write: 0x8001478e <- 0x7930201 +mem-write: 0x80014792 <- 0x6b30040 +mem-write: 0x80014796 <- 0x573300d6 +mem-write: 0x8001479a <- 0x87b300ef +mem-write: 0x8001479e <- 0xa82341d7 +mem-write: 0x800147a2 <- 0x693fee6 +mem-write: 0x800147a6 <- 0x97130040 +mem-write: 0x800147aa <- 0x7330027 +mem-write: 0x800147ae <- 0x202300e8 +mem-write: 0x800147b2 <- 0x87930007 +mem-write: 0x800147b6 <- 0x98e30017 +mem-write: 0x800147ba <- 0x2703fed7 +mem-write: 0x800147be <- 0x37b30101 +mem-write: 0x800147c2 <- 0x67b301c0 +mem-write: 0x800147c6 <- 0xf06f00f7 +mem-write: 0x800147ca <- 0x2503efdf +mem-write: 0x800147ce <- 0x2f83ffc6 +mem-write: 0x800147d2 <- 0x97930006 +mem-write: 0x800147d6 <- 0x55330028 +mem-write: 0x800147da <- 0x9fb300e5 +mem-write: 0x800147de <- 0x7b3006f +mem-write: 0x800147e2 <- 0x653300f8 +mem-write: 0x800147e6 <- 0xa02301f5 +mem-write: 0x800147ea <- 0x889300a7 +mem-write: 0x800147ee <- 0xf06f0018 +mem-write: 0x800147f2 <- 0x2603f91f +VXDRV: upload 1024 bytes to 0x800147f6 +mem-write: 0x800147f6 <- 0x27830141 +mem-write: 0x800147fa <- 0x28030181 +mem-write: 0x800147fe <- 0x66b301c1 +mem-write: 0x80014802 <- 0xe6b300f6 +mem-write: 0x80014806 <- 0xe6b30106 +mem-write: 0x8001480a <- 0x186300a6 +mem-write: 0x8001480e <- 0x36b30007 +mem-write: 0x80014812 <- 0x79300d0 +mem-write: 0x80014816 <- 0xf06f0000 +mem-write: 0x8001481a <- 0x8e63e75f +mem-write: 0x8001481e <- 0x56930a06 +mem-write: 0x80014822 <- 0x181301c6 +mem-write: 0x80014826 <- 0x96130048 +mem-write: 0x8001482a <- 0xd7930047 +mem-write: 0x8001482e <- 0x73701c7 +mem-write: 0x80014832 <- 0xe6b30040 +mem-write: 0x80014836 <- 0xe7b300c6 +mem-write: 0x8001483a <- 0xe7b30107 +mem-write: 0x8001483e <- 0xf69300e7 +mem-write: 0x80014842 <- 0x713ff86 +mem-write: 0x80014846 <- 0xf06f7ff0 +mem-write: 0x8001484a <- 0x793e45f +mem-write: 0x8001484e <- 0x6930000 +mem-write: 0x80014852 <- 0x7130000 +mem-write: 0x80014856 <- 0x96137ff0 +mem-write: 0x8001485a <- 0x5e630087 +mem-write: 0x8001485e <- 0x7130006 +mem-write: 0x80014862 <- 0x6130017 +mem-write: 0x80014866 <- 0xc637ff0 +mem-write: 0x8001486a <- 0x63706c7 +mem-write: 0x8001486e <- 0x613ff80 +mem-write: 0x80014872 <- 0xf7b3fff6 +mem-write: 0x80014876 <- 0x961300c7 +mem-write: 0x8001487a <- 0xd69301d7 +mem-write: 0x8001487e <- 0x66b30036 +mem-write: 0x80014882 <- 0x61300d6 +mem-write: 0x80014886 <- 0xd7937ff0 +mem-write: 0x8001488a <- 0x1e630037 +mem-write: 0x8001488e <- 0xe6b300c7 +mem-write: 0x80014892 <- 0x79300f6 +mem-write: 0x80014896 <- 0x88630000 +mem-write: 0x8001489a <- 0x7b70006 +mem-write: 0x8001489e <- 0x6930008 +mem-write: 0x800148a2 <- 0x5930000 +mem-write: 0x800148a6 <- 0x17130000 +mem-write: 0x800148aa <- 0x6370147 +mem-write: 0x800148ae <- 0x97937ff0 +mem-write: 0x800148b2 <- 0x773300c7 +mem-write: 0x800148b6 <- 0xd79300c7 +mem-write: 0x800148ba <- 0x959300c7 +mem-write: 0x800148be <- 0x67b301f5 +mem-write: 0x800148c2 <- 0xe73300f7 +mem-write: 0x800148c6 <- 0x851300b7 +mem-write: 0x800148ca <- 0x5930006 +mem-write: 0x800148ce <- 0x1130007 +mem-write: 0x800148d2 <- 0x80670201 +mem-write: 0x800148d6 <- 0x7930000 +mem-write: 0x800148da <- 0xf06f0000 +mem-write: 0x800148de <- 0x793f79f +mem-write: 0x800148e2 <- 0x6930000 +mem-write: 0x800148e6 <- 0xf06f0000 +mem-write: 0x800148ea <- 0x7b7f91f +mem-write: 0x800148ee <- 0x7a630001 +mem-write: 0x800148f2 <- 0x79302f5 +mem-write: 0x800148f6 <- 0xb7b30ff0 +mem-write: 0x800148fa <- 0x979300a7 +mem-write: 0x800148fe <- 0x57370037 +mem-write: 0x80014902 <- 0x6938001 +mem-write: 0x80014906 <- 0x86b30200 +mem-write: 0x8001490a <- 0x553340f6 +mem-write: 0x8001490e <- 0x79300f5 +mem-write: 0x80014912 <- 0x85336b47 +mem-write: 0x80014916 <- 0x450300a7 +mem-write: 0x8001491a <- 0x85330005 +mem-write: 0x8001491e <- 0x806740a6 +mem-write: 0x80014922 <- 0x7370000 +mem-write: 0x80014926 <- 0x7930100 +mem-write: 0x8001492a <- 0x6ae30100 +mem-write: 0x8001492e <- 0x793fce5 +mem-write: 0x80014932 <- 0xf06f0180 +mem-write: 0x80014936 <- 0x5245fcdf +mem-write: 0x8001493a <- 0x3a524f52 +mem-write: 0x8001493e <- 0x6e755f20 +mem-write: 0x80014942 <- 0x6b6e696c +mem-write: 0x80014946 <- 0x746f6e20 +mem-write: 0x8001494a <- 0x74657920 +mem-write: 0x8001494e <- 0x706d6920 +mem-write: 0x80014952 <- 0x656d656c +mem-write: 0x80014956 <- 0x6465746e +mem-write: 0x8001495a <- 0x5245000a +mem-write: 0x8001495e <- 0x3a524f52 +mem-write: 0x80014962 <- 0x696c5f20 +mem-write: 0x80014966 <- 0x6e206b6e +mem-write: 0x8001496a <- 0x7920746f +mem-write: 0x8001496e <- 0x69207465 +mem-write: 0x80014972 <- 0x656c706d +mem-write: 0x80014976 <- 0x746e656d +mem-write: 0x8001497a <- 0xa6465 +mem-write: 0x8001497e <- 0x300000 +mem-write: 0x80014982 <- 0x310000 +mem-write: 0x80014986 <- 0x320000 +mem-write: 0x8001498a <- 0x330000 +mem-write: 0x8001498e <- 0x340000 +mem-write: 0x80014992 <- 0x350000 +mem-write: 0x80014996 <- 0x360000 +mem-write: 0x8001499a <- 0x370000 +mem-write: 0x8001499e <- 0x380000 +mem-write: 0x800149a2 <- 0x390000 +mem-write: 0x800149a6 <- 0x610000 +mem-write: 0x800149aa <- 0x620000 +mem-write: 0x800149ae <- 0x630000 +mem-write: 0x800149b2 <- 0x640000 +mem-write: 0x800149b6 <- 0x650000 +mem-write: 0x800149ba <- 0x660000 +mem-write: 0x800149be <- 0x49800000 +mem-write: 0x800149c2 <- 0x49848001 +mem-write: 0x800149c6 <- 0x49888001 +mem-write: 0x800149ca <- 0x498c8001 +mem-write: 0x800149ce <- 0x49908001 +mem-write: 0x800149d2 <- 0x49948001 +mem-write: 0x800149d6 <- 0x49988001 +mem-write: 0x800149da <- 0x499c8001 +mem-write: 0x800149de <- 0x49a08001 +mem-write: 0x800149e2 <- 0x49a48001 +mem-write: 0x800149e6 <- 0x49a88001 +mem-write: 0x800149ea <- 0x49ac8001 +mem-write: 0x800149ee <- 0x49b08001 +mem-write: 0x800149f2 <- 0x49b48001 +mem-write: 0x800149f6 <- 0x49b88001 +mem-write: 0x800149fa <- 0x49bc8001 +mem-write: 0x800149fe <- 0x64258001 +mem-write: 0x80014a02 <- 0x656b000a +mem-write: 0x80014a06 <- 0x6c656e72 +mem-write: 0x80014a0a <- 0x65786520 +mem-write: 0x80014a0e <- 0x69747563 +mem-write: 0x80014a12 <- 0x2e2e676e +mem-write: 0x80014a16 <- 0xa2e +mem-write: 0x80014a1a <- 0x656b0000 +mem-write: 0x80014a1e <- 0x6c656e72 +mem-write: 0x80014a22 <- 0x6e6f6420 +mem-write: 0x80014a26 <- 0xa2e65 +mem-write: 0x80014a2a <- 0x4e490000 +mem-write: 0x80014a2e <- 0x6e690046 +mem-write: 0x80014a32 <- 0x414e0066 +mem-write: 0x80014a36 <- 0x616e004e +mem-write: 0x80014a3a <- 0x3130006e +mem-write: 0x80014a3e <- 0x35343332 +mem-write: 0x80014a42 <- 0x39383736 +mem-write: 0x80014a46 <- 0x64636261 +mem-write: 0x80014a4a <- 0x6665 +mem-write: 0x80014a4e <- 0x31300000 +mem-write: 0x80014a52 <- 0x35343332 +mem-write: 0x80014a56 <- 0x39383736 +mem-write: 0x80014a5a <- 0x44434241 +mem-write: 0x80014a5e <- 0x4645 +mem-write: 0x80014a62 <- 0x6e280000 +mem-write: 0x80014a66 <- 0x296c6c75 +mem-write: 0x80014a6a <- 0x1b080000 +mem-write: 0x80014a6e <- 0x11888000 +mem-write: 0x80014a72 <- 0x11888000 +mem-write: 0x80014a76 <- 0x1afc8000 +mem-write: 0x80014a7a <- 0x11888000 +mem-write: 0x80014a7e <- 0x11888000 +mem-write: 0x80014a82 <- 0x11888000 +mem-write: 0x80014a86 <- 0x137c8000 +mem-write: 0x80014a8a <- 0x11888000 +mem-write: 0x80014a8e <- 0x11888000 +mem-write: 0x80014a92 <- 0x1ad88000 +mem-write: 0x80014a96 <- 0x1a788000 +mem-write: 0x80014a9a <- 0x11888000 +mem-write: 0x80014a9e <- 0x19648000 +mem-write: 0x80014aa2 <- 0x1a948000 +mem-write: 0x80014aa6 <- 0x11888000 +mem-write: 0x80014aaa <- 0x1a888000 +mem-write: 0x80014aae <- 0x11588000 +mem-write: 0x80014ab2 <- 0x11588000 +mem-write: 0x80014ab6 <- 0x11588000 +mem-write: 0x80014aba <- 0x11588000 +mem-write: 0x80014abe <- 0x11588000 +mem-write: 0x80014ac2 <- 0x11588000 +mem-write: 0x80014ac6 <- 0x11588000 +mem-write: 0x80014aca <- 0x11588000 +mem-write: 0x80014ace <- 0x11588000 +mem-write: 0x80014ad2 <- 0x11888000 +mem-write: 0x80014ad6 <- 0x11888000 +mem-write: 0x80014ada <- 0x11888000 +mem-write: 0x80014ade <- 0x11888000 +mem-write: 0x80014ae2 <- 0x11888000 +mem-write: 0x80014ae6 <- 0x11888000 +mem-write: 0x80014aea <- 0x11888000 +mem-write: 0x80014aee <- 0x13f88000 +mem-write: 0x80014af2 <- 0x11888000 +mem-write: 0x80014af6 <- 0x18b48000 +mem-write: 0x80014afa <- 0x1b988000 +mem-write: 0x80014afe <- 0x13f88000 +mem-write: 0x80014b02 <- 0x13f88000 +mem-write: 0x80014b06 <- 0x13f88000 +mem-write: 0x80014b0a <- 0x11888000 +mem-write: 0x80014b0e <- 0x11888000 +mem-write: 0x80014b12 <- 0x11888000 +mem-write: 0x80014b16 <- 0x11888000 +mem-write: 0x80014b1a <- 0x1b8c8000 +mem-write: 0x80014b1e <- 0x11888000 +mem-write: 0x80014b22 <- 0x11888000 +mem-write: 0x80014b26 <- 0x1b208000 +mem-write: 0x80014b2a <- 0x11888000 +mem-write: 0x80014b2e <- 0x11888000 +mem-write: 0x80014b32 <- 0x11888000 +mem-write: 0x80014b36 <- 0x18e08000 +mem-write: 0x80014b3a <- 0x11888000 +mem-write: 0x80014b3e <- 0x1b588000 +mem-write: 0x80014b42 <- 0x11888000 +mem-write: 0x80014b46 <- 0x11888000 +mem-write: 0x80014b4a <- 0x26548000 +mem-write: 0x80014b4e <- 0x11888000 +mem-write: 0x80014b52 <- 0x11888000 +mem-write: 0x80014b56 <- 0x11888000 +mem-write: 0x80014b5a <- 0x11888000 +mem-write: 0x80014b5e <- 0x11888000 +mem-write: 0x80014b62 <- 0x11888000 +mem-write: 0x80014b66 <- 0x11888000 +mem-write: 0x80014b6a <- 0x11888000 +mem-write: 0x80014b6e <- 0x13f88000 +mem-write: 0x80014b72 <- 0x11888000 +mem-write: 0x80014b76 <- 0x18b48000 +mem-write: 0x80014b7a <- 0x24c88000 +mem-write: 0x80014b7e <- 0x13f88000 +mem-write: 0x80014b82 <- 0x13f88000 +mem-write: 0x80014b86 <- 0x13f88000 +mem-write: 0x80014b8a <- 0x1a648000 +mem-write: 0x80014b8e <- 0x24c88000 +mem-write: 0x80014b92 <- 0x13c08000 +mem-write: 0x80014b96 <- 0x11888000 +mem-write: 0x80014b9a <- 0x19c08000 +mem-write: 0x80014b9e <- 0x11888000 +mem-write: 0x80014ba2 <- 0x19708000 +mem-write: 0x80014ba6 <- 0x26688000 +mem-write: 0x80014baa <- 0x19d48000 +mem-write: 0x80014bae <- 0x13c08000 +mem-write: 0x80014bb2 <- 0x11888000 +mem-write: 0x80014bb6 <- 0x18e08000 +mem-write: 0x80014bba <- 0x13b88000 +mem-write: 0x80014bbe <- 0x25e88000 +mem-write: 0x80014bc2 <- 0x11888000 +mem-write: 0x80014bc6 <- 0x11888000 +mem-write: 0x80014bca <- 0x25f48000 +mem-write: 0x80014bce <- 0x11888000 +mem-write: 0x80014bd2 <- 0x13b88000 +mem-write: 0x80014bd6 <- 0x20208000 +mem-write: 0x80014bda <- 0x20202020 +mem-write: 0x80014bde <- 0x20202020 +mem-write: 0x80014be2 <- 0x20202020 +mem-write: 0x80014be6 <- 0x30302020 +mem-write: 0x80014bea <- 0x30303030 +mem-write: 0x80014bee <- 0x30303030 +mem-write: 0x80014bf2 <- 0x30303030 +VXDRV: upload 1024 bytes to 0x80014bf6 +mem-write: 0x80014bf6 <- 0x4e203030 +mem-write: 0x80014bfa <- 0x204e61 +mem-write: 0x80014bfe <- 0x2d200000 +mem-write: 0x80014c02 <- 0x69666e49 +mem-write: 0x80014c06 <- 0x7974696e +mem-write: 0x80014c0a <- 0x49200020 +mem-write: 0x80014c0e <- 0x6e69666e +mem-write: 0x80014c12 <- 0x20797469 +mem-write: 0x80014c16 <- 0x614e0000 +mem-write: 0x80014c1a <- 0x2545004e +mem-write: 0x80014c1e <- 0x64 +mem-write: 0x80014c22 <- 0x0 +mem-write: 0x80014c26 <- 0x0 +mem-write: 0x80014c2a <- 0x0 +mem-write: 0x80014c2e <- 0x0 +mem-write: 0x80014c32 <- 0x0 +mem-write: 0x80014c36 <- 0x0 +mem-write: 0x80014c3a <- 0x0 +mem-write: 0x80014c3e <- 0x0 +mem-write: 0x80014c42 <- 0x80000000 +mem-write: 0x80014c46 <- 0x65763fff +mem-write: 0x80014c4a <- 0x804a4a92 +mem-write: 0x80014c4e <- 0xc94c153f +mem-write: 0x80014c52 <- 0x8a20979a +mem-write: 0x80014c56 <- 0xc4605202 +mem-write: 0x80014c5a <- 0x6a327525 +mem-write: 0x80014c5e <- 0x329ace52 +mem-write: 0x80014c62 <- 0xa74d28ce +mem-write: 0x80014c66 <- 0xc53d5de4 +mem-write: 0x80014c6a <- 0x9e8b3b5d +mem-write: 0x80014c6e <- 0x526c5a92 +mem-write: 0x80014c72 <- 0xf18b50ce +mem-write: 0x80014c76 <- 0x650d3d28 +mem-write: 0x80014c7a <- 0x81750c17 +mem-write: 0x80014c7e <- 0xc9767586 +mem-write: 0x80014c82 <- 0x9c664d48 +mem-write: 0x80014c86 <- 0xbc5058f8 +mem-write: 0x80014c8a <- 0xcc655c54 +mem-write: 0x80014c8e <- 0xa60e91c6 +mem-write: 0x80014c92 <- 0xe319a0ae +mem-write: 0x80014c96 <- 0x851e46a3 +mem-write: 0x80014c9a <- 0x98feeab7 +mem-write: 0x80014c9e <- 0xddbb901b +mem-write: 0x80014ca2 <- 0x9df9de8d +mem-write: 0x80014ca6 <- 0xaa7eebfb +mem-write: 0x80014caa <- 0x2354351 +mem-write: 0x80014cae <- 0x36b10137 +mem-write: 0x80014cb2 <- 0xc66f336c +mem-write: 0x80014cb6 <- 0x80e98cdf +mem-write: 0x80014cba <- 0x93ba47c9 +mem-write: 0x80014cbe <- 0x50f841a8 +mem-write: 0x80014cc2 <- 0xc76b25fb +mem-write: 0x80014cc6 <- 0x3cbf6b71 +mem-write: 0x80014cca <- 0xffcfa6d5 +mem-write: 0x80014cce <- 0xc2781f49 +mem-write: 0x80014cd2 <- 0x40d3 +mem-write: 0x80014cd6 <- 0x0 +mem-write: 0x80014cda <- 0xf0200000 +mem-write: 0x80014cde <- 0x2b70b59d +mem-write: 0x80014ce2 <- 0x9dc5ada8 +mem-write: 0x80014ce6 <- 0x4069 +mem-write: 0x80014cea <- 0x0 +mem-write: 0x80014cee <- 0x0 +mem-write: 0x80014cf2 <- 0x4000000 +mem-write: 0x80014cf6 <- 0x8e1bc9bf +mem-write: 0x80014cfa <- 0x4034 +mem-write: 0x80014cfe <- 0x0 +mem-write: 0x80014d02 <- 0x0 +mem-write: 0x80014d06 <- 0x0 +mem-write: 0x80014d0a <- 0xbebc2000 +mem-write: 0x80014d0e <- 0x4019 +mem-write: 0x80014d12 <- 0x0 +mem-write: 0x80014d16 <- 0x0 +mem-write: 0x80014d1a <- 0x0 +mem-write: 0x80014d1e <- 0x9c400000 +mem-write: 0x80014d22 <- 0x400c +mem-write: 0x80014d26 <- 0x0 +mem-write: 0x80014d2a <- 0x0 +mem-write: 0x80014d2e <- 0x0 +mem-write: 0x80014d32 <- 0xc8000000 +mem-write: 0x80014d36 <- 0x4005 +mem-write: 0x80014d3a <- 0x0 +mem-write: 0x80014d3e <- 0x0 +mem-write: 0x80014d42 <- 0x0 +mem-write: 0x80014d46 <- 0xa0000000 +mem-write: 0x80014d4a <- 0x20304002 +mem-write: 0x80014d4e <- 0xa1c3cffc +mem-write: 0x80014d52 <- 0x2de38123 +mem-write: 0x80014d56 <- 0xd2ce9fde +mem-write: 0x80014d5a <- 0xa6dd04c8 +mem-write: 0x80014d5e <- 0x82640ad8 +mem-write: 0x80014d62 <- 0xf2ead2cb +mem-write: 0x80014d66 <- 0x492512d4 +mem-write: 0x80014d6a <- 0x34362de4 +mem-write: 0x80014d6e <- 0xceae534f +mem-write: 0x80014d72 <- 0xf53f256b +mem-write: 0x80014d76 <- 0x6bd3f698 +mem-write: 0x80014d7a <- 0x87a60158 +mem-write: 0x80014d7e <- 0xda57c0bd +mem-write: 0x80014d82 <- 0xa2a682a5 +mem-write: 0x80014d86 <- 0xe73132b5 +mem-write: 0x80014d8a <- 0xe3f204d4 +mem-write: 0x80014d8e <- 0x7132d332 +mem-write: 0x80014d92 <- 0xdb23d21c +mem-write: 0x80014d96 <- 0x9049ee32 +mem-write: 0x80014d9a <- 0xa23e395a +mem-write: 0x80014d9e <- 0xfefb5308 +mem-write: 0x80014da2 <- 0xfa911155 +mem-write: 0x80014da6 <- 0x637a1939 +mem-write: 0x80014daa <- 0xc0314325 +mem-write: 0x80014dae <- 0xe26d3cac +mem-write: 0x80014db2 <- 0xd05ddbde +mem-write: 0x80014db6 <- 0xac7cb3f6 +mem-write: 0x80014dba <- 0x64bce4a0 +mem-write: 0x80014dbe <- 0xddd0467c +mem-write: 0x80014dc2 <- 0x2a203e55 +mem-write: 0x80014dc6 <- 0x47b36224 +mem-write: 0x80014dca <- 0x3f2398d7 +mem-write: 0x80014dce <- 0xa539e9a5 +mem-write: 0x80014dd2 <- 0xa87fea27 +mem-write: 0x80014dd6 <- 0xb5b3f2a +mem-write: 0x80014dda <- 0xa5814af2 +mem-write: 0x80014dde <- 0x67de18ed +mem-write: 0x80014de2 <- 0x453994ba +mem-write: 0x80014de6 <- 0xcfb11ead +mem-write: 0x80014dea <- 0xbf713f94 +mem-write: 0x80014dee <- 0x7989a9b3 +mem-write: 0x80014df2 <- 0x4c2ebe68 +mem-write: 0x80014df6 <- 0xc44de15b +mem-write: 0x80014dfa <- 0xe69594be +mem-write: 0x80014dfe <- 0x3d4d3fc9 +mem-write: 0x80014e02 <- 0x36ba7c3d +mem-write: 0x80014e06 <- 0xfdc20d2b +mem-write: 0x80014e0a <- 0x8461cefc +mem-write: 0x80014e0e <- 0xabcc7711 +mem-write: 0x80014e12 <- 0xc1553fe4 +mem-write: 0x80014e16 <- 0x404ea4a8 +mem-write: 0x80014e1a <- 0xd3c36113 +mem-write: 0x80014e1e <- 0xe219652b +mem-write: 0x80014e22 <- 0xd1b71758 +mem-write: 0x80014e26 <- 0xd70a3ff1 +mem-write: 0x80014e2a <- 0xa3d70a3 +mem-write: 0x80014e2e <- 0x3d70a3d7 +mem-write: 0x80014e32 <- 0x70a3d70a +mem-write: 0x80014e36 <- 0xa3d70a3d +mem-write: 0x80014e3a <- 0xcccd3ff8 +mem-write: 0x80014e3e <- 0xcccccccc +mem-write: 0x80014e42 <- 0xcccccccc +mem-write: 0x80014e46 <- 0xcccccccc +mem-write: 0x80014e4a <- 0xcccccccc +mem-write: 0x80014e4e <- 0xffff3ffb +mem-write: 0x80014e52 <- 0xfffcfffe +mem-write: 0x80014e56 <- 0xfff0fff8 +mem-write: 0x80014e5a <- 0xffc0ffe0 +mem-write: 0x80014e5e <- 0xff00ff80 +mem-write: 0x80014e62 <- 0xfc00fe00 +mem-write: 0x80014e66 <- 0xf000f800 +mem-write: 0x80014e6a <- 0xc000e000 +mem-write: 0x80014e6e <- 0x8000 +mem-write: 0x80014e72 <- 0x61420000 +mem-write: 0x80014e76 <- 0x636f6c6c +mem-write: 0x80014e7a <- 0x63757320 +mem-write: 0x80014e7e <- 0x64656563 +mem-write: 0x80014e82 <- 0x6465 +mem-write: 0x80014e86 <- 0x682f0000 +mem-write: 0x80014e8a <- 0x2f656d6f +mem-write: 0x80014e8e <- 0x69616c62 +mem-write: 0x80014e92 <- 0x642f6573 +mem-write: 0x80014e96 <- 0x722f7665 +mem-write: 0x80014e9a <- 0x76637369 +mem-write: 0x80014e9e <- 0x756e672d +mem-write: 0x80014ea2 <- 0x6f6f742d +mem-write: 0x80014ea6 <- 0x6168636c +mem-write: 0x80014eaa <- 0x2f326e69 +mem-write: 0x80014eae <- 0x6c697562 +mem-write: 0x80014eb2 <- 0x2e2e2f64 +mem-write: 0x80014eb6 <- 0x7369722f +mem-write: 0x80014eba <- 0x6e2d7663 +mem-write: 0x80014ebe <- 0x696c7765 +mem-write: 0x80014ec2 <- 0x656e2f62 +mem-write: 0x80014ec6 <- 0x62696c77 +mem-write: 0x80014eca <- 0x62696c2f +mem-write: 0x80014ece <- 0x74732f63 +mem-write: 0x80014ed2 <- 0x62696c64 +mem-write: 0x80014ed6 <- 0x72706d2f +mem-write: 0x80014eda <- 0x632e6365 +mem-write: 0x80014ede <- 0x50000 +mem-write: 0x80014ee2 <- 0x190000 +mem-write: 0x80014ee6 <- 0x7d0000 +mem-write: 0x80014eea <- 0x0 +mem-write: 0x80014eee <- 0x0 +mem-write: 0x80014ef2 <- 0x0 +mem-write: 0x80014ef6 <- 0x3ff0 +mem-write: 0x80014efa <- 0x0 +mem-write: 0x80014efe <- 0x4024 +mem-write: 0x80014f02 <- 0x0 +mem-write: 0x80014f06 <- 0x4059 +mem-write: 0x80014f0a <- 0x40000000 +mem-write: 0x80014f0e <- 0x408f +mem-write: 0x80014f12 <- 0x88000000 +mem-write: 0x80014f16 <- 0x40c3 +mem-write: 0x80014f1a <- 0x6a000000 +mem-write: 0x80014f1e <- 0x40f8 +mem-write: 0x80014f22 <- 0x84800000 +mem-write: 0x80014f26 <- 0x412e +mem-write: 0x80014f2a <- 0x12d00000 +mem-write: 0x80014f2e <- 0x4163 +mem-write: 0x80014f32 <- 0xd7840000 +mem-write: 0x80014f36 <- 0x4197 +mem-write: 0x80014f3a <- 0xcd650000 +mem-write: 0x80014f3e <- 0x41cd +mem-write: 0x80014f42 <- 0xa05f2000 +mem-write: 0x80014f46 <- 0x4202 +mem-write: 0x80014f4a <- 0x4876e800 +mem-write: 0x80014f4e <- 0x4237 +mem-write: 0x80014f52 <- 0x1a94a200 +mem-write: 0x80014f56 <- 0x426d +mem-write: 0x80014f5a <- 0x309ce540 +mem-write: 0x80014f5e <- 0x42a2 +mem-write: 0x80014f62 <- 0xbcc41e90 +mem-write: 0x80014f66 <- 0x42d6 +mem-write: 0x80014f6a <- 0x6bf52634 +mem-write: 0x80014f6e <- 0x8000430c +mem-write: 0x80014f72 <- 0xc37937e0 +mem-write: 0x80014f76 <- 0xa0004341 +mem-write: 0x80014f7a <- 0x345785d8 +mem-write: 0x80014f7e <- 0xc8004376 +mem-write: 0x80014f82 <- 0xc16d674e +mem-write: 0x80014f86 <- 0x3d0043ab +mem-write: 0x80014f8a <- 0x58e46091 +mem-write: 0x80014f8e <- 0x8c4043e1 +mem-write: 0x80014f92 <- 0xaf1d78b5 +mem-write: 0x80014f96 <- 0xef504415 +mem-write: 0x80014f9a <- 0x1ae4d6e2 +mem-write: 0x80014f9e <- 0xd592444b +mem-write: 0x80014fa2 <- 0xf0cf064d +mem-write: 0x80014fa6 <- 0x4af64480 +mem-write: 0x80014faa <- 0x2d02c7e1 +mem-write: 0x80014fae <- 0x9db444b5 +mem-write: 0x80014fb2 <- 0x784379d9 +mem-write: 0x80014fb6 <- 0x89bc44ea +mem-write: 0x80014fba <- 0xd2b297d8 +mem-write: 0x80014fbe <- 0xa7333c9c +mem-write: 0x80014fc2 <- 0xf623d5a8 +mem-write: 0x80014fc6 <- 0xa73d3949 +mem-write: 0x80014fca <- 0xffd44f4 +mem-write: 0x80014fce <- 0x979d32a5 +mem-write: 0x80014fd2 <- 0xba08cf8c +mem-write: 0x80014fd6 <- 0x6f43255b +mem-write: 0x80014fda <- 0x62864ac +mem-write: 0x80014fde <- 0x80000ac8 +mem-write: 0x80014fe2 <- 0xc37937e0 +mem-write: 0x80014fe6 <- 0x6e174341 +mem-write: 0x80014fea <- 0xb8b5b505 +mem-write: 0x80014fee <- 0xf9f54693 +mem-write: 0x80014ff2 <- 0x4f03e93f +VXDRV: upload 1024 bytes to 0x80014ff6 +mem-write: 0x80014ff6 <- 0x1d324d38 +mem-write: 0x80014ffa <- 0x7748f930 +mem-write: 0x80014ffe <- 0xbf3c5a82 +mem-write: 0x80015002 <- 0x4fdd7f73 +mem-write: 0x80015006 <- 0xa1ac7515 +mem-write: 0x8001500a <- 0x97d48000 +mem-write: 0x8001500e <- 0x97d48000 +mem-write: 0x80015012 <- 0xa1a08000 +mem-write: 0x80015016 <- 0x97d48000 +mem-write: 0x8001501a <- 0x97d48000 +mem-write: 0x8001501e <- 0x97d48000 +mem-write: 0x80015022 <- 0x997c8000 +mem-write: 0x80015026 <- 0x97d48000 +mem-write: 0x8001502a <- 0x97d48000 +mem-write: 0x8001502e <- 0xa17c8000 +mem-write: 0x80015032 <- 0xa2148000 +mem-write: 0x80015036 <- 0x97d48000 +mem-write: 0x8001503a <- 0x9ff08000 +mem-write: 0x8001503e <- 0xa1d08000 +mem-write: 0x80015042 <- 0x97d48000 +mem-write: 0x80015046 <- 0xa1c48000 +mem-write: 0x8001504a <- 0x97a48000 +mem-write: 0x8001504e <- 0x97a48000 +mem-write: 0x80015052 <- 0x97a48000 +mem-write: 0x80015056 <- 0x97a48000 +mem-write: 0x8001505a <- 0x97a48000 +mem-write: 0x8001505e <- 0x97a48000 +mem-write: 0x80015062 <- 0x97a48000 +mem-write: 0x80015066 <- 0x97a48000 +mem-write: 0x8001506a <- 0x97a48000 +mem-write: 0x8001506e <- 0x97d48000 +mem-write: 0x80015072 <- 0x97d48000 +mem-write: 0x80015076 <- 0x97d48000 +mem-write: 0x8001507a <- 0x97d48000 +mem-write: 0x8001507e <- 0x97d48000 +mem-write: 0x80015082 <- 0x97d48000 +mem-write: 0x80015086 <- 0x97d48000 +mem-write: 0x8001508a <- 0x99f88000 +mem-write: 0x8001508e <- 0x97d48000 +mem-write: 0x80015092 <- 0x9fc48000 +mem-write: 0x80015096 <- 0xa2248000 +mem-write: 0x8001509a <- 0x99f88000 +mem-write: 0x8001509e <- 0x99f88000 +mem-write: 0x800150a2 <- 0x99f88000 +mem-write: 0x800150a6 <- 0x97d48000 +mem-write: 0x800150aa <- 0x97d48000 +mem-write: 0x800150ae <- 0x97d48000 +mem-write: 0x800150b2 <- 0x97d48000 +mem-write: 0x800150b6 <- 0xa1708000 +mem-write: 0x800150ba <- 0x97d48000 +mem-write: 0x800150be <- 0x97d48000 +mem-write: 0x800150c2 <- 0xa0f08000 +mem-write: 0x800150c6 <- 0x97d48000 +mem-write: 0x800150ca <- 0x97d48000 +mem-write: 0x800150ce <- 0x97d48000 +mem-write: 0x800150d2 <- 0x9f408000 +mem-write: 0x800150d6 <- 0x97d48000 +mem-write: 0x800150da <- 0xa13c8000 +mem-write: 0x800150de <- 0x97d48000 +mem-write: 0x800150e2 <- 0x97d48000 +mem-write: 0x800150e6 <- 0xabd48000 +mem-write: 0x800150ea <- 0x97d48000 +mem-write: 0x800150ee <- 0x97d48000 +mem-write: 0x800150f2 <- 0x97d48000 +mem-write: 0x800150f6 <- 0x97d48000 +mem-write: 0x800150fa <- 0x97d48000 +mem-write: 0x800150fe <- 0x97d48000 +mem-write: 0x80015102 <- 0x97d48000 +mem-write: 0x80015106 <- 0x97d48000 +mem-write: 0x8001510a <- 0x99f88000 +mem-write: 0x8001510e <- 0x97d48000 +mem-write: 0x80015112 <- 0x9fc48000 +mem-write: 0x80015116 <- 0xaa7c8000 +mem-write: 0x8001511a <- 0x99f88000 +mem-write: 0x8001511e <- 0x99f88000 +mem-write: 0x80015122 <- 0x99f88000 +mem-write: 0x80015126 <- 0xa1288000 +mem-write: 0x8001512a <- 0xaa7c8000 +mem-write: 0x8001512e <- 0x99c08000 +mem-write: 0x80015132 <- 0x97d48000 +mem-write: 0x80015136 <- 0xa04c8000 +mem-write: 0x8001513a <- 0x97d48000 +mem-write: 0x8001513e <- 0x9ffc8000 +mem-write: 0x80015142 <- 0xabe88000 +mem-write: 0x80015146 <- 0xa0608000 +mem-write: 0x8001514a <- 0x99c08000 +mem-write: 0x8001514e <- 0x97d48000 +mem-write: 0x80015152 <- 0x9f408000 +mem-write: 0x80015156 <- 0x99b88000 +mem-write: 0x8001515a <- 0xab488000 +mem-write: 0x8001515e <- 0x97d48000 +mem-write: 0x80015162 <- 0x97d48000 +mem-write: 0x80015166 <- 0xab548000 +mem-write: 0x8001516a <- 0x97d48000 +mem-write: 0x8001516e <- 0x99b88000 +mem-write: 0x80015172 <- 0x20208000 +mem-write: 0x80015176 <- 0x20202020 +mem-write: 0x8001517a <- 0x20202020 +mem-write: 0x8001517e <- 0x20202020 +mem-write: 0x80015182 <- 0x30302020 +mem-write: 0x80015186 <- 0x30303030 +mem-write: 0x8001518a <- 0x30303030 +mem-write: 0x8001518e <- 0x30303030 +mem-write: 0x80015192 <- 0xc8cc3030 +mem-write: 0x80015196 <- 0xc33c8000 +mem-write: 0x8001519a <- 0xc33c8000 +mem-write: 0x8001519e <- 0xc8c08000 +mem-write: 0x800151a2 <- 0xc33c8000 +mem-write: 0x800151a6 <- 0xc33c8000 +mem-write: 0x800151aa <- 0xc33c8000 +mem-write: 0x800151ae <- 0xc5048000 +mem-write: 0x800151b2 <- 0xc33c8000 +mem-write: 0x800151b6 <- 0xc33c8000 +mem-write: 0x800151ba <- 0xc8948000 +mem-write: 0x800151be <- 0xc8f08000 +mem-write: 0x800151c2 <- 0xc33c8000 +mem-write: 0x800151c6 <- 0xc8e48000 +mem-write: 0x800151ca <- 0xc9008000 +mem-write: 0x800151ce <- 0xc33c8000 +mem-write: 0x800151d2 <- 0xc8888000 +mem-write: 0x800151d6 <- 0xc3048000 +mem-write: 0x800151da <- 0xc3048000 +mem-write: 0x800151de <- 0xc3048000 +mem-write: 0x800151e2 <- 0xc3048000 +mem-write: 0x800151e6 <- 0xc3048000 +mem-write: 0x800151ea <- 0xc3048000 +mem-write: 0x800151ee <- 0xc3048000 +mem-write: 0x800151f2 <- 0xc3048000 +mem-write: 0x800151f6 <- 0xc3048000 +mem-write: 0x800151fa <- 0xc33c8000 +mem-write: 0x800151fe <- 0xc33c8000 +mem-write: 0x80015202 <- 0xc33c8000 +mem-write: 0x80015206 <- 0xc33c8000 +mem-write: 0x8001520a <- 0xc33c8000 +mem-write: 0x8001520e <- 0xc33c8000 +mem-write: 0x80015212 <- 0xc33c8000 +mem-write: 0x80015216 <- 0xc33c8000 +mem-write: 0x8001521a <- 0xc33c8000 +mem-write: 0x8001521e <- 0xc7d08000 +mem-write: 0x80015222 <- 0xc5548000 +mem-write: 0x80015226 <- 0xc33c8000 +mem-write: 0x8001522a <- 0xc33c8000 +mem-write: 0x8001522e <- 0xc33c8000 +mem-write: 0x80015232 <- 0xc33c8000 +mem-write: 0x80015236 <- 0xc33c8000 +mem-write: 0x8001523a <- 0xc33c8000 +mem-write: 0x8001523e <- 0xc33c8000 +mem-write: 0x80015242 <- 0xc33c8000 +mem-write: 0x80015246 <- 0xc33c8000 +mem-write: 0x8001524a <- 0xc33c8000 +mem-write: 0x8001524e <- 0xc61c8000 +mem-write: 0x80015252 <- 0xc33c8000 +mem-write: 0x80015256 <- 0xc33c8000 +mem-write: 0x8001525a <- 0xc33c8000 +mem-write: 0x8001525e <- 0xc7908000 +mem-write: 0x80015262 <- 0xc33c8000 +mem-write: 0x80015266 <- 0xc8588000 +mem-write: 0x8001526a <- 0xc33c8000 +mem-write: 0x8001526e <- 0xc33c8000 +mem-write: 0x80015272 <- 0xd0488000 +mem-write: 0x80015276 <- 0xc33c8000 +mem-write: 0x8001527a <- 0xc33c8000 +mem-write: 0x8001527e <- 0xc33c8000 +mem-write: 0x80015282 <- 0xc33c8000 +mem-write: 0x80015286 <- 0xc33c8000 +mem-write: 0x8001528a <- 0xc33c8000 +mem-write: 0x8001528e <- 0xc33c8000 +mem-write: 0x80015292 <- 0xc33c8000 +mem-write: 0x80015296 <- 0xc33c8000 +mem-write: 0x8001529a <- 0xc33c8000 +mem-write: 0x8001529e <- 0xc7d08000 +mem-write: 0x800152a2 <- 0xc5588000 +mem-write: 0x800152a6 <- 0xc33c8000 +mem-write: 0x800152aa <- 0xc33c8000 +mem-write: 0x800152ae <- 0xc33c8000 +mem-write: 0x800152b2 <- 0xc8448000 +mem-write: 0x800152b6 <- 0xc5588000 +mem-write: 0x800152ba <- 0xc5488000 +mem-write: 0x800152be <- 0xc33c8000 +mem-write: 0x800152c2 <- 0xc8308000 +mem-write: 0x800152c6 <- 0xc33c8000 +mem-write: 0x800152ca <- 0xc9408000 +mem-write: 0x800152ce <- 0xc6208000 +mem-write: 0x800152d2 <- 0xc7f88000 +mem-write: 0x800152d6 <- 0xc5488000 +mem-write: 0x800152da <- 0xc33c8000 +mem-write: 0x800152de <- 0xc7908000 +mem-write: 0x800152e2 <- 0xc5408000 +mem-write: 0x800152e6 <- 0xd0408000 +mem-write: 0x800152ea <- 0xc33c8000 +mem-write: 0x800152ee <- 0xc33c8000 +mem-write: 0x800152f2 <- 0xd0a48000 +mem-write: 0x800152f6 <- 0xc33c8000 +mem-write: 0x800152fa <- 0xc5408000 +mem-write: 0x800152fe <- 0x20208000 +mem-write: 0x80015302 <- 0x20202020 +mem-write: 0x80015306 <- 0x20202020 +mem-write: 0x8001530a <- 0x20202020 +mem-write: 0x8001530e <- 0x30302020 +mem-write: 0x80015312 <- 0x30303030 +mem-write: 0x80015316 <- 0x30303030 +mem-write: 0x8001531a <- 0x30303030 +mem-write: 0x8001531e <- 0x202c3030 +mem-write: 0x80015322 <- 0x636e7566 +mem-write: 0x80015326 <- 0x6e6f6974 +mem-write: 0x8001532a <- 0x203a +mem-write: 0x8001532e <- 0x73610000 +mem-write: 0x80015332 <- 0x74726573 +mem-write: 0x80015336 <- 0x206e6f69 +mem-write: 0x8001533a <- 0x22732522 +mem-write: 0x8001533e <- 0x69616620 +mem-write: 0x80015342 <- 0x3a64656c +mem-write: 0x80015346 <- 0x6c696620 +mem-write: 0x8001534a <- 0x25222065 +mem-write: 0x8001534e <- 0x202c2273 +mem-write: 0x80015352 <- 0x656e696c +mem-write: 0x80015356 <- 0x25642520 +mem-write: 0x8001535a <- 0xa732573 +mem-write: 0x8001535e <- 0x430000 +mem-write: 0x80015362 <- 0x4f500000 +mem-write: 0x80015366 <- 0x584953 +mem-write: 0x8001536a <- 0x2e0000 +mem-write: 0x8001536e <- 0xf3f40000 +mem-write: 0x80015372 <- 0xeea48000 +mem-write: 0x80015376 <- 0xeea48000 +mem-write: 0x8001537a <- 0xf3e88000 +mem-write: 0x8001537e <- 0xeea48000 +mem-write: 0x80015382 <- 0xeea48000 +mem-write: 0x80015386 <- 0xeea48000 +mem-write: 0x8001538a <- 0xf02c8000 +mem-write: 0x8001538e <- 0xeea48000 +mem-write: 0x80015392 <- 0xeea48000 +mem-write: 0x80015396 <- 0xf3bc8000 +mem-write: 0x8001539a <- 0xf3ac8000 +mem-write: 0x8001539e <- 0xeea48000 +mem-write: 0x800153a2 <- 0xf3a08000 +mem-write: 0x800153a6 <- 0xf3608000 +mem-write: 0x800153aa <- 0xeea48000 +mem-write: 0x800153ae <- 0xf3548000 +mem-write: 0x800153b2 <- 0xee6c8000 +mem-write: 0x800153b6 <- 0xee6c8000 +mem-write: 0x800153ba <- 0xee6c8000 +mem-write: 0x800153be <- 0xee6c8000 +mem-write: 0x800153c2 <- 0xee6c8000 +mem-write: 0x800153c6 <- 0xee6c8000 +mem-write: 0x800153ca <- 0xee6c8000 +mem-write: 0x800153ce <- 0xee6c8000 +mem-write: 0x800153d2 <- 0xee6c8000 +mem-write: 0x800153d6 <- 0xeea48000 +mem-write: 0x800153da <- 0xeea48000 +mem-write: 0x800153de <- 0xeea48000 +mem-write: 0x800153e2 <- 0xeea48000 +mem-write: 0x800153e6 <- 0xeea48000 +mem-write: 0x800153ea <- 0xeea48000 +mem-write: 0x800153ee <- 0xeea48000 +mem-write: 0x800153f2 <- 0xeea48000 +VXDRV: upload 1024 bytes to 0x800153f6 +mem-write: 0x800153f6 <- 0xeea48000 +mem-write: 0x800153fa <- 0xf0f48000 +mem-write: 0x800153fe <- 0xf2108000 +mem-write: 0x80015402 <- 0xeea48000 +mem-write: 0x80015406 <- 0xeea48000 +mem-write: 0x8001540a <- 0xeea48000 +mem-write: 0x8001540e <- 0xeea48000 +mem-write: 0x80015412 <- 0xeea48000 +mem-write: 0x80015416 <- 0xeea48000 +mem-write: 0x8001541a <- 0xeea48000 +mem-write: 0x8001541e <- 0xeea48000 +mem-write: 0x80015422 <- 0xeea48000 +mem-write: 0x80015426 <- 0xeea48000 +mem-write: 0x8001542a <- 0xf1a08000 +mem-write: 0x8001542e <- 0xeea48000 +mem-write: 0x80015432 <- 0xeea48000 +mem-write: 0x80015436 <- 0xeea48000 +mem-write: 0x8001543a <- 0xf0a88000 +mem-write: 0x8001543e <- 0xeea48000 +mem-write: 0x80015442 <- 0xf2e48000 +mem-write: 0x80015446 <- 0xeea48000 +mem-write: 0x8001544a <- 0xeea48000 +mem-write: 0x8001544e <- 0xfa948000 +mem-write: 0x80015452 <- 0xeea48000 +mem-write: 0x80015456 <- 0xeea48000 +mem-write: 0x8001545a <- 0xeea48000 +mem-write: 0x8001545e <- 0xeea48000 +mem-write: 0x80015462 <- 0xeea48000 +mem-write: 0x80015466 <- 0xeea48000 +mem-write: 0x8001546a <- 0xeea48000 +mem-write: 0x8001546e <- 0xeea48000 +mem-write: 0x80015472 <- 0xeea48000 +mem-write: 0x80015476 <- 0xeea48000 +mem-write: 0x8001547a <- 0xf0f48000 +mem-write: 0x8001547e <- 0xf11c8000 +mem-write: 0x80015482 <- 0xeea48000 +mem-write: 0x80015486 <- 0xeea48000 +mem-write: 0x8001548a <- 0xeea48000 +mem-write: 0x8001548e <- 0xf40c8000 +mem-write: 0x80015492 <- 0xf11c8000 +mem-write: 0x80015496 <- 0xf0708000 +mem-write: 0x8001549a <- 0xeea48000 +mem-write: 0x8001549e <- 0xf45c8000 +mem-write: 0x800154a2 <- 0xeea48000 +mem-write: 0x800154a6 <- 0xf4208000 +mem-write: 0x800154aa <- 0xfb008000 +mem-write: 0x800154ae <- 0xf3188000 +mem-write: 0x800154b2 <- 0xf0708000 +mem-write: 0x800154b6 <- 0xeea48000 +mem-write: 0x800154ba <- 0xf0a88000 +mem-write: 0x800154be <- 0xf0688000 +mem-write: 0x800154c2 <- 0xfaf48000 +mem-write: 0x800154c6 <- 0xeea48000 +mem-write: 0x800154ca <- 0xeea48000 +mem-write: 0x800154ce <- 0xfb088000 +mem-write: 0x800154d2 <- 0xeea48000 +mem-write: 0x800154d6 <- 0xf0688000 +mem-write: 0x800154da <- 0x20208000 +mem-write: 0x800154de <- 0x20202020 +mem-write: 0x800154e2 <- 0x20202020 +mem-write: 0x800154e6 <- 0x20202020 +mem-write: 0x800154ea <- 0x30302020 +mem-write: 0x800154ee <- 0x30303030 +mem-write: 0x800154f2 <- 0x30303030 +mem-write: 0x800154f6 <- 0x30303030 +mem-write: 0x800154fa <- 0x20003030 +mem-write: 0x800154fe <- 0x20202020 +mem-write: 0x80015502 <- 0x20202020 +mem-write: 0x80015506 <- 0x28282828 +mem-write: 0x8001550a <- 0x20202028 +mem-write: 0x8001550e <- 0x20202020 +mem-write: 0x80015512 <- 0x20202020 +mem-write: 0x80015516 <- 0x20202020 +mem-write: 0x8001551a <- 0x88202020 +mem-write: 0x8001551e <- 0x10101010 +mem-write: 0x80015522 <- 0x10101010 +mem-write: 0x80015526 <- 0x10101010 +mem-write: 0x8001552a <- 0x4101010 +mem-write: 0x8001552e <- 0x4040404 +mem-write: 0x80015532 <- 0x4040404 +mem-write: 0x80015536 <- 0x10101004 +mem-write: 0x8001553a <- 0x10101010 +mem-write: 0x8001553e <- 0x41414141 +mem-write: 0x80015542 <- 0x1014141 +mem-write: 0x80015546 <- 0x1010101 +mem-write: 0x8001554a <- 0x1010101 +mem-write: 0x8001554e <- 0x1010101 +mem-write: 0x80015552 <- 0x1010101 +mem-write: 0x80015556 <- 0x10100101 +mem-write: 0x8001555a <- 0x10101010 +mem-write: 0x8001555e <- 0x42424242 +mem-write: 0x80015562 <- 0x2024242 +mem-write: 0x80015566 <- 0x2020202 +mem-write: 0x8001556a <- 0x2020202 +mem-write: 0x8001556e <- 0x2020202 +mem-write: 0x80015572 <- 0x2020202 +mem-write: 0x80015576 <- 0x10100202 +mem-write: 0x8001557a <- 0x201010 +mem-write: 0x8001557e <- 0x0 +mem-write: 0x80015582 <- 0x0 +mem-write: 0x80015586 <- 0x0 +mem-write: 0x8001558a <- 0x0 +mem-write: 0x8001558e <- 0x0 +mem-write: 0x80015592 <- 0x0 +mem-write: 0x80015596 <- 0x0 +mem-write: 0x8001559a <- 0x0 +mem-write: 0x8001559e <- 0x0 +mem-write: 0x800155a2 <- 0x0 +mem-write: 0x800155a6 <- 0x0 +mem-write: 0x800155aa <- 0x0 +mem-write: 0x800155ae <- 0x0 +mem-write: 0x800155b2 <- 0x0 +mem-write: 0x800155b6 <- 0x0 +mem-write: 0x800155ba <- 0x0 +mem-write: 0x800155be <- 0x0 +mem-write: 0x800155c2 <- 0x0 +mem-write: 0x800155c6 <- 0x0 +mem-write: 0x800155ca <- 0x0 +mem-write: 0x800155ce <- 0x0 +mem-write: 0x800155d2 <- 0x0 +mem-write: 0x800155d6 <- 0x0 +mem-write: 0x800155da <- 0x0 +mem-write: 0x800155de <- 0x0 +mem-write: 0x800155e2 <- 0x0 +mem-write: 0x800155e6 <- 0x0 +mem-write: 0x800155ea <- 0x0 +mem-write: 0x800155ee <- 0x0 +mem-write: 0x800155f2 <- 0x0 +mem-write: 0x800155f6 <- 0x0 +mem-write: 0x800155fa <- 0x0 +mem-write: 0x800155fe <- 0x11f40000 +mem-write: 0x80015602 <- 0x12e48001 +mem-write: 0x80015606 <- 0x12048001 +mem-write: 0x8001560a <- 0x12e48001 +mem-write: 0x8001560e <- 0x12d08001 +mem-write: 0x80015612 <- 0x12e48001 +mem-write: 0x80015616 <- 0x12048001 +mem-write: 0x8001561a <- 0x11f48001 +mem-write: 0x8001561e <- 0x11f48001 +mem-write: 0x80015622 <- 0x12d08001 +mem-write: 0x80015626 <- 0x12048001 +mem-write: 0x8001562a <- 0x11cc8001 +mem-write: 0x8001562e <- 0x11cc8001 +mem-write: 0x80015632 <- 0x11cc8001 +mem-write: 0x80015636 <- 0x120c8001 +mem-write: 0x8001563a <- 0x17b88001 +mem-write: 0x8001563e <- 0x17b88001 +mem-write: 0x80015642 <- 0x17dc8001 +mem-write: 0x80015646 <- 0x17ac8001 +mem-write: 0x8001564a <- 0x17ac8001 +mem-write: 0x8001564e <- 0x189c8001 +mem-write: 0x80015652 <- 0x17dc8001 +mem-write: 0x80015656 <- 0x17ac8001 +mem-write: 0x8001565a <- 0x189c8001 +mem-write: 0x8001565e <- 0x17ac8001 +mem-write: 0x80015662 <- 0x17dc8001 +mem-write: 0x80015666 <- 0x17a88001 +mem-write: 0x8001566a <- 0x17a88001 +mem-write: 0x8001566e <- 0x17a88001 +mem-write: 0x80015672 <- 0x189c8001 +mem-write: 0x80015676 <- 0x29888001 +mem-write: 0x8001567a <- 0x29888001 +mem-write: 0x8001567e <- 0x29848001 +mem-write: 0x80015682 <- 0x29388001 +mem-write: 0x80015686 <- 0x29388001 +mem-write: 0x8001568a <- 0x2c088001 +mem-write: 0x8001568e <- 0x29848001 +mem-write: 0x80015692 <- 0x29388001 +mem-write: 0x80015696 <- 0x2c088001 +mem-write: 0x8001569a <- 0x29388001 +mem-write: 0x8001569e <- 0x29848001 +mem-write: 0x800156a2 <- 0x29348001 +mem-write: 0x800156a6 <- 0x29348001 +mem-write: 0x800156aa <- 0x29348001 +mem-write: 0x800156ae <- 0x2c088001 +mem-write: 0x800156b2 <- 0x1008001 +mem-write: 0x800156b6 <- 0x3030202 +mem-write: 0x800156ba <- 0x4040303 +mem-write: 0x800156be <- 0x4040404 +mem-write: 0x800156c2 <- 0x5050404 +mem-write: 0x800156c6 <- 0x5050505 +mem-write: 0x800156ca <- 0x5050505 +mem-write: 0x800156ce <- 0x5050505 +mem-write: 0x800156d2 <- 0x6060505 +mem-write: 0x800156d6 <- 0x6060606 +mem-write: 0x800156da <- 0x6060606 +mem-write: 0x800156de <- 0x6060606 +mem-write: 0x800156e2 <- 0x6060606 +mem-write: 0x800156e6 <- 0x6060606 +mem-write: 0x800156ea <- 0x6060606 +mem-write: 0x800156ee <- 0x6060606 +mem-write: 0x800156f2 <- 0x7070606 +mem-write: 0x800156f6 <- 0x7070707 +mem-write: 0x800156fa <- 0x7070707 +mem-write: 0x800156fe <- 0x7070707 +mem-write: 0x80015702 <- 0x7070707 +mem-write: 0x80015706 <- 0x7070707 +mem-write: 0x8001570a <- 0x7070707 +mem-write: 0x8001570e <- 0x7070707 +mem-write: 0x80015712 <- 0x7070707 +mem-write: 0x80015716 <- 0x7070707 +mem-write: 0x8001571a <- 0x7070707 +mem-write: 0x8001571e <- 0x7070707 +mem-write: 0x80015722 <- 0x7070707 +mem-write: 0x80015726 <- 0x7070707 +mem-write: 0x8001572a <- 0x7070707 +mem-write: 0x8001572e <- 0x7070707 +mem-write: 0x80015732 <- 0x8080707 +mem-write: 0x80015736 <- 0x8080808 +mem-write: 0x8001573a <- 0x8080808 +mem-write: 0x8001573e <- 0x8080808 +mem-write: 0x80015742 <- 0x8080808 +mem-write: 0x80015746 <- 0x8080808 +mem-write: 0x8001574a <- 0x8080808 +mem-write: 0x8001574e <- 0x8080808 +mem-write: 0x80015752 <- 0x8080808 +mem-write: 0x80015756 <- 0x8080808 +mem-write: 0x8001575a <- 0x8080808 +mem-write: 0x8001575e <- 0x8080808 +mem-write: 0x80015762 <- 0x8080808 +mem-write: 0x80015766 <- 0x8080808 +mem-write: 0x8001576a <- 0x8080808 +mem-write: 0x8001576e <- 0x8080808 +mem-write: 0x80015772 <- 0x8080808 +mem-write: 0x80015776 <- 0x8080808 +mem-write: 0x8001577a <- 0x8080808 +mem-write: 0x8001577e <- 0x8080808 +mem-write: 0x80015782 <- 0x8080808 +mem-write: 0x80015786 <- 0x8080808 +mem-write: 0x8001578a <- 0x8080808 +mem-write: 0x8001578e <- 0x8080808 +mem-write: 0x80015792 <- 0x8080808 +mem-write: 0x80015796 <- 0x8080808 +mem-write: 0x8001579a <- 0x8080808 +mem-write: 0x8001579e <- 0x8080808 +mem-write: 0x800157a2 <- 0x8080808 +mem-write: 0x800157a6 <- 0x8080808 +mem-write: 0x800157aa <- 0x8080808 +mem-write: 0x800157ae <- 0x8080808 +mem-write: 0x800157b2 <- 0x100808 +mem-write: 0x800157b6 <- 0x0 +mem-write: 0x800157ba <- 0x7a030000 +mem-write: 0x800157be <- 0x7c010052 +mem-write: 0x800157c2 <- 0xd1b0101 +mem-write: 0x800157c6 <- 0x100002 +mem-write: 0x800157ca <- 0x180000 +mem-write: 0x800157ce <- 0xac180000 +mem-write: 0x800157d2 <- 0x434ffff +mem-write: 0x800157d6 <- 0x0 +mem-write: 0x800157da <- 0x100000 +mem-write: 0x800157de <- 0x2c0000 +mem-write: 0x800157e2 <- 0xb0380000 +mem-write: 0x800157e6 <- 0x410ffff +mem-write: 0x800157ea <- 0x0 +mem-write: 0x800157ee <- 0x0 +mem-write: 0x800157f2 <- 0x0 +VXDRV: upload 1024 bytes to 0x800157f6 +mem-write: 0x800157f6 <- 0x0 +mem-write: 0x800157fa <- 0x0 +mem-write: 0x800157fe <- 0x0 +mem-write: 0x80015802 <- 0x0 +mem-write: 0x80015806 <- 0x0 +mem-write: 0x8001580a <- 0x0 +mem-write: 0x8001580e <- 0x0 +mem-write: 0x80015812 <- 0x0 +mem-write: 0x80015816 <- 0x0 +mem-write: 0x8001581a <- 0x0 +mem-write: 0x8001581e <- 0x0 +mem-write: 0x80015822 <- 0x0 +mem-write: 0x80015826 <- 0x0 +mem-write: 0x8001582a <- 0x0 +mem-write: 0x8001582e <- 0x0 +mem-write: 0x80015832 <- 0x0 +mem-write: 0x80015836 <- 0x0 +mem-write: 0x8001583a <- 0x0 +mem-write: 0x8001583e <- 0x0 +mem-write: 0x80015842 <- 0x0 +mem-write: 0x80015846 <- 0x0 +mem-write: 0x8001584a <- 0x0 +mem-write: 0x8001584e <- 0x0 +mem-write: 0x80015852 <- 0x0 +mem-write: 0x80015856 <- 0x0 +mem-write: 0x8001585a <- 0x0 +mem-write: 0x8001585e <- 0x0 +mem-write: 0x80015862 <- 0x0 +mem-write: 0x80015866 <- 0x0 +mem-write: 0x8001586a <- 0x0 +mem-write: 0x8001586e <- 0x0 +mem-write: 0x80015872 <- 0x0 +mem-write: 0x80015876 <- 0x0 +mem-write: 0x8001587a <- 0x0 +mem-write: 0x8001587e <- 0x0 +mem-write: 0x80015882 <- 0x0 +mem-write: 0x80015886 <- 0x0 +mem-write: 0x8001588a <- 0x0 +mem-write: 0x8001588e <- 0x0 +mem-write: 0x80015892 <- 0x0 +mem-write: 0x80015896 <- 0x0 +mem-write: 0x8001589a <- 0x0 +mem-write: 0x8001589e <- 0x0 +mem-write: 0x800158a2 <- 0x0 +mem-write: 0x800158a6 <- 0x0 +mem-write: 0x800158aa <- 0x0 +mem-write: 0x800158ae <- 0x0 +mem-write: 0x800158b2 <- 0x0 +mem-write: 0x800158b6 <- 0x0 +mem-write: 0x800158ba <- 0x0 +mem-write: 0x800158be <- 0x0 +mem-write: 0x800158c2 <- 0x0 +mem-write: 0x800158c6 <- 0x0 +mem-write: 0x800158ca <- 0x0 +mem-write: 0x800158ce <- 0x0 +mem-write: 0x800158d2 <- 0x0 +mem-write: 0x800158d6 <- 0x0 +mem-write: 0x800158da <- 0x0 +mem-write: 0x800158de <- 0x0 +mem-write: 0x800158e2 <- 0x0 +mem-write: 0x800158e6 <- 0x0 +mem-write: 0x800158ea <- 0x0 +mem-write: 0x800158ee <- 0x0 +mem-write: 0x800158f2 <- 0x0 +mem-write: 0x800158f6 <- 0x0 +mem-write: 0x800158fa <- 0x0 +mem-write: 0x800158fe <- 0x0 +mem-write: 0x80015902 <- 0x0 +mem-write: 0x80015906 <- 0x0 +mem-write: 0x8001590a <- 0x0 +mem-write: 0x8001590e <- 0x0 +mem-write: 0x80015912 <- 0x0 +mem-write: 0x80015916 <- 0x0 +mem-write: 0x8001591a <- 0x0 +mem-write: 0x8001591e <- 0x0 +mem-write: 0x80015922 <- 0x0 +mem-write: 0x80015926 <- 0x0 +mem-write: 0x8001592a <- 0x0 +mem-write: 0x8001592e <- 0x0 +mem-write: 0x80015932 <- 0x0 +mem-write: 0x80015936 <- 0x0 +mem-write: 0x8001593a <- 0x0 +mem-write: 0x8001593e <- 0x0 +mem-write: 0x80015942 <- 0x0 +mem-write: 0x80015946 <- 0x0 +mem-write: 0x8001594a <- 0x0 +mem-write: 0x8001594e <- 0x0 +mem-write: 0x80015952 <- 0x0 +mem-write: 0x80015956 <- 0x0 +mem-write: 0x8001595a <- 0x0 +mem-write: 0x8001595e <- 0x0 +mem-write: 0x80015962 <- 0x0 +mem-write: 0x80015966 <- 0x0 +mem-write: 0x8001596a <- 0x0 +mem-write: 0x8001596e <- 0x0 +mem-write: 0x80015972 <- 0x0 +mem-write: 0x80015976 <- 0x0 +mem-write: 0x8001597a <- 0x0 +mem-write: 0x8001597e <- 0x0 +mem-write: 0x80015982 <- 0x0 +mem-write: 0x80015986 <- 0x0 +mem-write: 0x8001598a <- 0x0 +mem-write: 0x8001598e <- 0x0 +mem-write: 0x80015992 <- 0x0 +mem-write: 0x80015996 <- 0x0 +mem-write: 0x8001599a <- 0x0 +mem-write: 0x8001599e <- 0x0 +mem-write: 0x800159a2 <- 0x0 +mem-write: 0x800159a6 <- 0x0 +mem-write: 0x800159aa <- 0x0 +mem-write: 0x800159ae <- 0x0 +mem-write: 0x800159b2 <- 0x0 +mem-write: 0x800159b6 <- 0x0 +mem-write: 0x800159ba <- 0x0 +mem-write: 0x800159be <- 0x0 +mem-write: 0x800159c2 <- 0x0 +mem-write: 0x800159c6 <- 0x0 +mem-write: 0x800159ca <- 0x0 +mem-write: 0x800159ce <- 0x0 +mem-write: 0x800159d2 <- 0x0 +mem-write: 0x800159d6 <- 0x0 +mem-write: 0x800159da <- 0x0 +mem-write: 0x800159de <- 0x0 +mem-write: 0x800159e2 <- 0x0 +mem-write: 0x800159e6 <- 0x0 +mem-write: 0x800159ea <- 0x0 +mem-write: 0x800159ee <- 0x0 +mem-write: 0x800159f2 <- 0x0 +mem-write: 0x800159f6 <- 0x0 +mem-write: 0x800159fa <- 0x0 +mem-write: 0x800159fe <- 0x0 +mem-write: 0x80015a02 <- 0x0 +mem-write: 0x80015a06 <- 0x0 +mem-write: 0x80015a0a <- 0x0 +mem-write: 0x80015a0e <- 0x0 +mem-write: 0x80015a12 <- 0x0 +mem-write: 0x80015a16 <- 0x0 +mem-write: 0x80015a1a <- 0x0 +mem-write: 0x80015a1e <- 0x0 +mem-write: 0x80015a22 <- 0x0 +mem-write: 0x80015a26 <- 0x0 +mem-write: 0x80015a2a <- 0x0 +mem-write: 0x80015a2e <- 0x0 +mem-write: 0x80015a32 <- 0x0 +mem-write: 0x80015a36 <- 0x0 +mem-write: 0x80015a3a <- 0x0 +mem-write: 0x80015a3e <- 0x0 +mem-write: 0x80015a42 <- 0x0 +mem-write: 0x80015a46 <- 0x0 +mem-write: 0x80015a4a <- 0x0 +mem-write: 0x80015a4e <- 0x0 +mem-write: 0x80015a52 <- 0x0 +mem-write: 0x80015a56 <- 0x0 +mem-write: 0x80015a5a <- 0x0 +mem-write: 0x80015a5e <- 0x0 +mem-write: 0x80015a62 <- 0x0 +mem-write: 0x80015a66 <- 0x0 +mem-write: 0x80015a6a <- 0x0 +mem-write: 0x80015a6e <- 0x0 +mem-write: 0x80015a72 <- 0x0 +mem-write: 0x80015a76 <- 0x0 +mem-write: 0x80015a7a <- 0x0 +mem-write: 0x80015a7e <- 0x0 +mem-write: 0x80015a82 <- 0x0 +mem-write: 0x80015a86 <- 0x0 +mem-write: 0x80015a8a <- 0x0 +mem-write: 0x80015a8e <- 0x0 +mem-write: 0x80015a92 <- 0x0 +mem-write: 0x80015a96 <- 0x0 +mem-write: 0x80015a9a <- 0x0 +mem-write: 0x80015a9e <- 0x0 +mem-write: 0x80015aa2 <- 0x0 +mem-write: 0x80015aa6 <- 0x0 +mem-write: 0x80015aaa <- 0x0 +mem-write: 0x80015aae <- 0x0 +mem-write: 0x80015ab2 <- 0x0 +mem-write: 0x80015ab6 <- 0x0 +mem-write: 0x80015aba <- 0x0 +mem-write: 0x80015abe <- 0x0 +mem-write: 0x80015ac2 <- 0x0 +mem-write: 0x80015ac6 <- 0x0 +mem-write: 0x80015aca <- 0x0 +mem-write: 0x80015ace <- 0x0 +mem-write: 0x80015ad2 <- 0x0 +mem-write: 0x80015ad6 <- 0x0 +mem-write: 0x80015ada <- 0x0 +mem-write: 0x80015ade <- 0x0 +mem-write: 0x80015ae2 <- 0x0 +mem-write: 0x80015ae6 <- 0x0 +mem-write: 0x80015aea <- 0x0 +mem-write: 0x80015aee <- 0x0 +mem-write: 0x80015af2 <- 0x0 +mem-write: 0x80015af6 <- 0x0 +mem-write: 0x80015afa <- 0x0 +mem-write: 0x80015afe <- 0x0 +mem-write: 0x80015b02 <- 0x0 +mem-write: 0x80015b06 <- 0x0 +mem-write: 0x80015b0a <- 0x0 +mem-write: 0x80015b0e <- 0x0 +mem-write: 0x80015b12 <- 0x0 +mem-write: 0x80015b16 <- 0x0 +mem-write: 0x80015b1a <- 0x0 +mem-write: 0x80015b1e <- 0x0 +mem-write: 0x80015b22 <- 0x0 +mem-write: 0x80015b26 <- 0x0 +mem-write: 0x80015b2a <- 0x0 +mem-write: 0x80015b2e <- 0x0 +mem-write: 0x80015b32 <- 0x0 +mem-write: 0x80015b36 <- 0x0 +mem-write: 0x80015b3a <- 0x0 +mem-write: 0x80015b3e <- 0x0 +mem-write: 0x80015b42 <- 0x0 +mem-write: 0x80015b46 <- 0x0 +mem-write: 0x80015b4a <- 0x0 +mem-write: 0x80015b4e <- 0x0 +mem-write: 0x80015b52 <- 0x0 +mem-write: 0x80015b56 <- 0x0 +mem-write: 0x80015b5a <- 0x0 +mem-write: 0x80015b5e <- 0x0 +mem-write: 0x80015b62 <- 0x0 +mem-write: 0x80015b66 <- 0x0 +mem-write: 0x80015b6a <- 0x0 +mem-write: 0x80015b6e <- 0x0 +mem-write: 0x80015b72 <- 0x0 +mem-write: 0x80015b76 <- 0x0 +mem-write: 0x80015b7a <- 0x0 +mem-write: 0x80015b7e <- 0x0 +mem-write: 0x80015b82 <- 0x0 +mem-write: 0x80015b86 <- 0x0 +mem-write: 0x80015b8a <- 0x0 +mem-write: 0x80015b8e <- 0x0 +mem-write: 0x80015b92 <- 0x0 +mem-write: 0x80015b96 <- 0x0 +mem-write: 0x80015b9a <- 0x0 +mem-write: 0x80015b9e <- 0x0 +mem-write: 0x80015ba2 <- 0x0 +mem-write: 0x80015ba6 <- 0x0 +mem-write: 0x80015baa <- 0x0 +mem-write: 0x80015bae <- 0x0 +mem-write: 0x80015bb2 <- 0x0 +mem-write: 0x80015bb6 <- 0x0 +mem-write: 0x80015bba <- 0x0 +mem-write: 0x80015bbe <- 0x0 +mem-write: 0x80015bc2 <- 0x0 +mem-write: 0x80015bc6 <- 0x0 +mem-write: 0x80015bca <- 0x0 +mem-write: 0x80015bce <- 0x0 +mem-write: 0x80015bd2 <- 0x0 +mem-write: 0x80015bd6 <- 0x0 +mem-write: 0x80015bda <- 0x0 +mem-write: 0x80015bde <- 0x0 +mem-write: 0x80015be2 <- 0x0 +mem-write: 0x80015be6 <- 0x0 +mem-write: 0x80015bea <- 0x0 +mem-write: 0x80015bee <- 0x0 +mem-write: 0x80015bf2 <- 0x0 +VXDRV: upload 1023 bytes to 0x80015bf6 +mem-write: 0x80015bf6 <- 0x0 +mem-write: 0x80015bfa <- 0x0 +mem-write: 0x80015bfe <- 0x0 +mem-write: 0x80015c02 <- 0x0 +mem-write: 0x80015c06 <- 0x0 +mem-write: 0x80015c0a <- 0x0 +mem-write: 0x80015c0e <- 0x0 +mem-write: 0x80015c12 <- 0x0 +mem-write: 0x80015c16 <- 0x0 +mem-write: 0x80015c1a <- 0x0 +mem-write: 0x80015c1e <- 0x0 +mem-write: 0x80015c22 <- 0x0 +mem-write: 0x80015c26 <- 0x0 +mem-write: 0x80015c2a <- 0x0 +mem-write: 0x80015c2e <- 0x0 +mem-write: 0x80015c32 <- 0x0 +mem-write: 0x80015c36 <- 0x0 +mem-write: 0x80015c3a <- 0x0 +mem-write: 0x80015c3e <- 0x0 +mem-write: 0x80015c42 <- 0x0 +mem-write: 0x80015c46 <- 0x0 +mem-write: 0x80015c4a <- 0x0 +mem-write: 0x80015c4e <- 0x0 +mem-write: 0x80015c52 <- 0x0 +mem-write: 0x80015c56 <- 0x0 +mem-write: 0x80015c5a <- 0x0 +mem-write: 0x80015c5e <- 0x0 +mem-write: 0x80015c62 <- 0x0 +mem-write: 0x80015c66 <- 0x0 +mem-write: 0x80015c6a <- 0x0 +mem-write: 0x80015c6e <- 0x0 +mem-write: 0x80015c72 <- 0x0 +mem-write: 0x80015c76 <- 0x0 +mem-write: 0x80015c7a <- 0x0 +mem-write: 0x80015c7e <- 0x0 +mem-write: 0x80015c82 <- 0x0 +mem-write: 0x80015c86 <- 0x0 +mem-write: 0x80015c8a <- 0x0 +mem-write: 0x80015c8e <- 0x0 +mem-write: 0x80015c92 <- 0x0 +mem-write: 0x80015c96 <- 0x0 +mem-write: 0x80015c9a <- 0x0 +mem-write: 0x80015c9e <- 0x0 +mem-write: 0x80015ca2 <- 0x0 +mem-write: 0x80015ca6 <- 0x0 +mem-write: 0x80015caa <- 0x0 +mem-write: 0x80015cae <- 0x0 +mem-write: 0x80015cb2 <- 0x0 +mem-write: 0x80015cb6 <- 0x0 +mem-write: 0x80015cba <- 0x0 +mem-write: 0x80015cbe <- 0x0 +mem-write: 0x80015cc2 <- 0x0 +mem-write: 0x80015cc6 <- 0x0 +mem-write: 0x80015cca <- 0x0 +mem-write: 0x80015cce <- 0x0 +mem-write: 0x80015cd2 <- 0x0 +mem-write: 0x80015cd6 <- 0x0 +mem-write: 0x80015cda <- 0x0 +mem-write: 0x80015cde <- 0x0 +mem-write: 0x80015ce2 <- 0x0 +mem-write: 0x80015ce6 <- 0x0 +mem-write: 0x80015cea <- 0x0 +mem-write: 0x80015cee <- 0x0 +mem-write: 0x80015cf2 <- 0x0 +mem-write: 0x80015cf6 <- 0x0 +mem-write: 0x80015cfa <- 0x0 +mem-write: 0x80015cfe <- 0x0 +mem-write: 0x80015d02 <- 0x0 +mem-write: 0x80015d06 <- 0x0 +mem-write: 0x80015d0a <- 0x0 +mem-write: 0x80015d0e <- 0x0 +mem-write: 0x80015d12 <- 0x0 +mem-write: 0x80015d16 <- 0x0 +mem-write: 0x80015d1a <- 0x0 +mem-write: 0x80015d1e <- 0x0 +mem-write: 0x80015d22 <- 0x0 +mem-write: 0x80015d26 <- 0x0 +mem-write: 0x80015d2a <- 0x0 +mem-write: 0x80015d2e <- 0x0 +mem-write: 0x80015d32 <- 0x0 +mem-write: 0x80015d36 <- 0x0 +mem-write: 0x80015d3a <- 0x0 +mem-write: 0x80015d3e <- 0x0 +mem-write: 0x80015d42 <- 0x0 +mem-write: 0x80015d46 <- 0x0 +mem-write: 0x80015d4a <- 0x0 +mem-write: 0x80015d4e <- 0x0 +mem-write: 0x80015d52 <- 0x0 +mem-write: 0x80015d56 <- 0x0 +mem-write: 0x80015d5a <- 0x0 +mem-write: 0x80015d5e <- 0x0 +mem-write: 0x80015d62 <- 0x0 +mem-write: 0x80015d66 <- 0x0 +mem-write: 0x80015d6a <- 0x0 +mem-write: 0x80015d6e <- 0x0 +mem-write: 0x80015d72 <- 0x0 +mem-write: 0x80015d76 <- 0x0 +mem-write: 0x80015d7a <- 0x0 +mem-write: 0x80015d7e <- 0x0 +mem-write: 0x80015d82 <- 0x0 +mem-write: 0x80015d86 <- 0x0 +mem-write: 0x80015d8a <- 0x0 +mem-write: 0x80015d8e <- 0x0 +mem-write: 0x80015d92 <- 0x0 +mem-write: 0x80015d96 <- 0x0 +mem-write: 0x80015d9a <- 0x0 +mem-write: 0x80015d9e <- 0x0 +mem-write: 0x80015da2 <- 0x0 +mem-write: 0x80015da6 <- 0x0 +mem-write: 0x80015daa <- 0x0 +mem-write: 0x80015dae <- 0x0 +mem-write: 0x80015db2 <- 0x0 +mem-write: 0x80015db6 <- 0x0 +mem-write: 0x80015dba <- 0x0 +mem-write: 0x80015dbe <- 0x0 +mem-write: 0x80015dc2 <- 0x0 +mem-write: 0x80015dc6 <- 0x0 +mem-write: 0x80015dca <- 0x0 +mem-write: 0x80015dce <- 0x0 +mem-write: 0x80015dd2 <- 0x0 +mem-write: 0x80015dd6 <- 0x0 +mem-write: 0x80015dda <- 0x0 +mem-write: 0x80015dde <- 0x0 +mem-write: 0x80015de2 <- 0x0 +mem-write: 0x80015de6 <- 0x0 +mem-write: 0x80015dea <- 0x0 +mem-write: 0x80015dee <- 0x0 +mem-write: 0x80015df2 <- 0x0 +mem-write: 0x80015df6 <- 0x0 +mem-write: 0x80015dfa <- 0x0 +mem-write: 0x80015dfe <- 0x0 +mem-write: 0x80015e02 <- 0x0 +mem-write: 0x80015e06 <- 0x0 +mem-write: 0x80015e0a <- 0x0 +mem-write: 0x80015e0e <- 0x0 +mem-write: 0x80015e12 <- 0x0 +mem-write: 0x80015e16 <- 0x0 +mem-write: 0x80015e1a <- 0x0 +mem-write: 0x80015e1e <- 0x0 +mem-write: 0x80015e22 <- 0x0 +mem-write: 0x80015e26 <- 0x0 +mem-write: 0x80015e2a <- 0x0 +mem-write: 0x80015e2e <- 0x0 +mem-write: 0x80015e32 <- 0x0 +mem-write: 0x80015e36 <- 0x0 +mem-write: 0x80015e3a <- 0x0 +mem-write: 0x80015e3e <- 0x0 +mem-write: 0x80015e42 <- 0x0 +mem-write: 0x80015e46 <- 0x0 +mem-write: 0x80015e4a <- 0x0 +mem-write: 0x80015e4e <- 0x0 +mem-write: 0x80015e52 <- 0x0 +mem-write: 0x80015e56 <- 0x0 +mem-write: 0x80015e5a <- 0x0 +mem-write: 0x80015e5e <- 0x0 +mem-write: 0x80015e62 <- 0x0 +mem-write: 0x80015e66 <- 0x0 +mem-write: 0x80015e6a <- 0x0 +mem-write: 0x80015e6e <- 0x0 +mem-write: 0x80015e72 <- 0x0 +mem-write: 0x80015e76 <- 0x0 +mem-write: 0x80015e7a <- 0x0 +mem-write: 0x80015e7e <- 0x0 +mem-write: 0x80015e82 <- 0x0 +mem-write: 0x80015e86 <- 0x0 +mem-write: 0x80015e8a <- 0x0 +mem-write: 0x80015e8e <- 0x0 +mem-write: 0x80015e92 <- 0x0 +mem-write: 0x80015e96 <- 0x0 +mem-write: 0x80015e9a <- 0x0 +mem-write: 0x80015e9e <- 0x0 +mem-write: 0x80015ea2 <- 0x0 +mem-write: 0x80015ea6 <- 0x0 +mem-write: 0x80015eaa <- 0x0 +mem-write: 0x80015eae <- 0x0 +mem-write: 0x80015eb2 <- 0x0 +mem-write: 0x80015eb6 <- 0x0 +mem-write: 0x80015eba <- 0x0 +mem-write: 0x80015ebe <- 0x0 +mem-write: 0x80015ec2 <- 0x0 +mem-write: 0x80015ec6 <- 0x0 +mem-write: 0x80015eca <- 0x0 +mem-write: 0x80015ece <- 0x0 +mem-write: 0x80015ed2 <- 0x0 +mem-write: 0x80015ed6 <- 0x0 +mem-write: 0x80015eda <- 0x0 +mem-write: 0x80015ede <- 0x0 +mem-write: 0x80015ee2 <- 0x0 +mem-write: 0x80015ee6 <- 0x0 +mem-write: 0x80015eea <- 0x0 +mem-write: 0x80015eee <- 0x0 +mem-write: 0x80015ef2 <- 0x0 +mem-write: 0x80015ef6 <- 0x0 +mem-write: 0x80015efa <- 0x0 +mem-write: 0x80015efe <- 0x0 +mem-write: 0x80015f02 <- 0x0 +mem-write: 0x80015f06 <- 0x0 +mem-write: 0x80015f0a <- 0x0 +mem-write: 0x80015f0e <- 0x0 +mem-write: 0x80015f12 <- 0x0 +mem-write: 0x80015f16 <- 0x0 +mem-write: 0x80015f1a <- 0x0 +mem-write: 0x80015f1e <- 0x0 +mem-write: 0x80015f22 <- 0x0 +mem-write: 0x80015f26 <- 0x0 +mem-write: 0x80015f2a <- 0x0 +mem-write: 0x80015f2e <- 0x0 +mem-write: 0x80015f32 <- 0x0 +mem-write: 0x80015f36 <- 0x0 +mem-write: 0x80015f3a <- 0x0 +mem-write: 0x80015f3e <- 0x0 +mem-write: 0x80015f42 <- 0x0 +mem-write: 0x80015f46 <- 0x0 +mem-write: 0x80015f4a <- 0x0 +mem-write: 0x80015f4e <- 0x0 +mem-write: 0x80015f52 <- 0x0 +mem-write: 0x80015f56 <- 0x0 +mem-write: 0x80015f5a <- 0x0 +mem-write: 0x80015f5e <- 0x0 +mem-write: 0x80015f62 <- 0x0 +mem-write: 0x80015f66 <- 0x0 +mem-write: 0x80015f6a <- 0x0 +mem-write: 0x80015f6e <- 0x0 +mem-write: 0x80015f72 <- 0x0 +mem-write: 0x80015f76 <- 0x0 +mem-write: 0x80015f7a <- 0x0 +mem-write: 0x80015f7e <- 0x0 +mem-write: 0x80015f82 <- 0x0 +mem-write: 0x80015f86 <- 0x0 +mem-write: 0x80015f8a <- 0x0 +mem-write: 0x80015f8e <- 0x0 +mem-write: 0x80015f92 <- 0x0 +mem-write: 0x80015f96 <- 0x0 +mem-write: 0x80015f9a <- 0x0 +mem-write: 0x80015f9e <- 0x0 +mem-write: 0x80015fa2 <- 0x0 +mem-write: 0x80015fa6 <- 0x0 +mem-write: 0x80015faa <- 0x0 +mem-write: 0x80015fae <- 0x0 +mem-write: 0x80015fb2 <- 0x0 +mem-write: 0x80015fb6 <- 0x0 +mem-write: 0x80015fba <- 0x0 +mem-write: 0x80015fbe <- 0x0 +mem-write: 0x80015fc2 <- 0x0 +mem-write: 0x80015fc6 <- 0x0 +mem-write: 0x80015fca <- 0x0 +mem-write: 0x80015fce <- 0x0 +mem-write: 0x80015fd2 <- 0x0 +mem-write: 0x80015fd6 <- 0x0 +mem-write: 0x80015fda <- 0x0 +mem-write: 0x80015fde <- 0x0 +mem-write: 0x80015fe2 <- 0x0 +mem-write: 0x80015fe6 <- 0x0 +mem-write: 0x80015fea <- 0x0 +mem-write: 0x80015fee <- 0x0 +mem-write: 0x80015ff2 <- 0x0 +VXDRV: upload 1024 bytes to 0x80015ff5 +mem-write: 0x80015ff5 <- 0x0 +mem-write: 0x80015ff9 <- 0x0 +mem-write: 0x80015ffd <- 0xbc000000 +mem-write: 0x80016001 <- 0x800000 +mem-write: 0x80016005 <- 0x0 +mem-write: 0x80016009 <- 0x0 +mem-write: 0x8001600d <- 0x100 +mem-write: 0x80016011 <- 0xfc000000 +mem-write: 0x80016015 <- 0x64800162 +mem-write: 0x80016019 <- 0xcc800163 +mem-write: 0x8001601d <- 0x800163 +mem-write: 0x80016021 <- 0x0 +mem-write: 0x80016025 <- 0x0 +mem-write: 0x80016029 <- 0x0 +mem-write: 0x8001602d <- 0x0 +mem-write: 0x80016031 <- 0x0 +mem-write: 0x80016035 <- 0x0 +mem-write: 0x80016039 <- 0x0 +mem-write: 0x8001603d <- 0x0 +mem-write: 0x80016041 <- 0x0 +mem-write: 0x80016045 <- 0x0 +mem-write: 0x80016049 <- 0x0 +mem-write: 0x8001604d <- 0x0 +mem-write: 0x80016051 <- 0x0 +mem-write: 0x80016055 <- 0x0 +mem-write: 0x80016059 <- 0x0 +mem-write: 0x8001605d <- 0x0 +mem-write: 0x80016061 <- 0x0 +mem-write: 0x80016065 <- 0x0 +mem-write: 0x80016069 <- 0x0 +mem-write: 0x8001606d <- 0x0 +mem-write: 0x80016071 <- 0x0 +mem-write: 0x80016075 <- 0x0 +mem-write: 0x80016079 <- 0x0 +mem-write: 0x8001607d <- 0x0 +mem-write: 0x80016081 <- 0x0 +mem-write: 0x80016085 <- 0x0 +mem-write: 0x80016089 <- 0x0 +mem-write: 0x8001608d <- 0x0 +mem-write: 0x80016091 <- 0x0 +mem-write: 0x80016095 <- 0x0 +mem-write: 0x80016099 <- 0x0 +mem-write: 0x8001609d <- 0x0 +mem-write: 0x800160a1 <- 0x0 +mem-write: 0x800160a5 <- 0x0 +mem-write: 0x800160a9 <- 0x0 +mem-write: 0x800160ad <- 0x0 +mem-write: 0x800160b1 <- 0x0 +mem-write: 0x800160b5 <- 0x1000000 +mem-write: 0x800160b9 <- 0x0 +mem-write: 0x800160bd <- 0xe000000 +mem-write: 0x800160c1 <- 0x34abcd33 +mem-write: 0x800160c5 <- 0xece66d12 +mem-write: 0x800160c9 <- 0xb0005de +mem-write: 0x800160cd <- 0x0 +mem-write: 0x800160d1 <- 0x0 +mem-write: 0x800160d5 <- 0x0 +mem-write: 0x800160d9 <- 0x0 +mem-write: 0x800160dd <- 0x0 +mem-write: 0x800160e1 <- 0x0 +mem-write: 0x800160e5 <- 0x0 +mem-write: 0x800160e9 <- 0x0 +mem-write: 0x800160ed <- 0x0 +mem-write: 0x800160f1 <- 0x0 +mem-write: 0x800160f5 <- 0x0 +mem-write: 0x800160f9 <- 0x0 +mem-write: 0x800160fd <- 0x0 +mem-write: 0x80016101 <- 0x0 +mem-write: 0x80016105 <- 0x0 +mem-write: 0x80016109 <- 0x0 +mem-write: 0x8001610d <- 0x0 +mem-write: 0x80016111 <- 0x0 +mem-write: 0x80016115 <- 0x0 +mem-write: 0x80016119 <- 0x0 +mem-write: 0x8001611d <- 0x0 +mem-write: 0x80016121 <- 0x0 +mem-write: 0x80016125 <- 0x0 +mem-write: 0x80016129 <- 0x0 +mem-write: 0x8001612d <- 0x0 +mem-write: 0x80016131 <- 0x0 +mem-write: 0x80016135 <- 0x0 +mem-write: 0x80016139 <- 0x0 +mem-write: 0x8001613d <- 0x0 +mem-write: 0x80016141 <- 0x0 +mem-write: 0x80016145 <- 0x0 +mem-write: 0x80016149 <- 0x0 +mem-write: 0x8001614d <- 0x0 +mem-write: 0x80016151 <- 0x0 +mem-write: 0x80016155 <- 0x0 +mem-write: 0x80016159 <- 0x0 +mem-write: 0x8001615d <- 0x0 +mem-write: 0x80016161 <- 0x0 +mem-write: 0x80016165 <- 0x0 +mem-write: 0x80016169 <- 0x0 +mem-write: 0x8001616d <- 0x0 +mem-write: 0x80016171 <- 0x0 +mem-write: 0x80016175 <- 0x0 +mem-write: 0x80016179 <- 0x0 +mem-write: 0x8001617d <- 0x0 +mem-write: 0x80016181 <- 0x0 +mem-write: 0x80016185 <- 0x0 +mem-write: 0x80016189 <- 0x0 +mem-write: 0x8001618d <- 0x0 +mem-write: 0x80016191 <- 0x0 +mem-write: 0x80016195 <- 0x0 +mem-write: 0x80016199 <- 0x0 +mem-write: 0x8001619d <- 0x0 +mem-write: 0x800161a1 <- 0x0 +mem-write: 0x800161a5 <- 0x0 +mem-write: 0x800161a9 <- 0x0 +mem-write: 0x800161ad <- 0x0 +mem-write: 0x800161b1 <- 0x0 +mem-write: 0x800161b5 <- 0x0 +mem-write: 0x800161b9 <- 0x0 +mem-write: 0x800161bd <- 0x0 +mem-write: 0x800161c1 <- 0x0 +mem-write: 0x800161c5 <- 0x0 +mem-write: 0x800161c9 <- 0x0 +mem-write: 0x800161cd <- 0x0 +mem-write: 0x800161d1 <- 0x0 +mem-write: 0x800161d5 <- 0x0 +mem-write: 0x800161d9 <- 0x0 +mem-write: 0x800161dd <- 0x0 +mem-write: 0x800161e1 <- 0x0 +mem-write: 0x800161e5 <- 0x0 +mem-write: 0x800161e9 <- 0x0 +mem-write: 0x800161ed <- 0x0 +mem-write: 0x800161f1 <- 0x0 +mem-write: 0x800161f5 <- 0x0 +mem-write: 0x800161f9 <- 0x0 +mem-write: 0x800161fd <- 0x0 +mem-write: 0x80016201 <- 0x0 +mem-write: 0x80016205 <- 0x0 +mem-write: 0x80016209 <- 0x0 +mem-write: 0x8001620d <- 0x0 +mem-write: 0x80016211 <- 0x0 +mem-write: 0x80016215 <- 0x0 +mem-write: 0x80016219 <- 0x0 +mem-write: 0x8001621d <- 0x0 +mem-write: 0x80016221 <- 0x0 +mem-write: 0x80016225 <- 0x0 +mem-write: 0x80016229 <- 0x0 +mem-write: 0x8001622d <- 0x0 +mem-write: 0x80016231 <- 0x0 +mem-write: 0x80016235 <- 0x0 +mem-write: 0x80016239 <- 0x0 +mem-write: 0x8001623d <- 0x0 +mem-write: 0x80016241 <- 0x0 +mem-write: 0x80016245 <- 0x0 +mem-write: 0x80016249 <- 0x0 +mem-write: 0x8001624d <- 0x0 +mem-write: 0x80016251 <- 0x0 +mem-write: 0x80016255 <- 0x0 +mem-write: 0x80016259 <- 0x0 +mem-write: 0x8001625d <- 0x0 +mem-write: 0x80016261 <- 0x0 +mem-write: 0x80016265 <- 0x0 +mem-write: 0x80016269 <- 0x0 +mem-write: 0x8001626d <- 0x0 +mem-write: 0x80016271 <- 0x0 +mem-write: 0x80016275 <- 0x0 +mem-write: 0x80016279 <- 0x0 +mem-write: 0x8001627d <- 0x0 +mem-write: 0x80016281 <- 0x0 +mem-write: 0x80016285 <- 0x0 +mem-write: 0x80016289 <- 0x0 +mem-write: 0x8001628d <- 0x0 +mem-write: 0x80016291 <- 0x0 +mem-write: 0x80016295 <- 0x0 +mem-write: 0x80016299 <- 0x0 +mem-write: 0x8001629d <- 0x0 +mem-write: 0x800162a1 <- 0x0 +mem-write: 0x800162a5 <- 0x0 +mem-write: 0x800162a9 <- 0x0 +mem-write: 0x800162ad <- 0x0 +mem-write: 0x800162b1 <- 0x0 +mem-write: 0x800162b5 <- 0x0 +mem-write: 0x800162b9 <- 0x0 +mem-write: 0x800162bd <- 0x0 +mem-write: 0x800162c1 <- 0x0 +mem-write: 0x800162c5 <- 0x0 +mem-write: 0x800162c9 <- 0x0 +mem-write: 0x800162cd <- 0x0 +mem-write: 0x800162d1 <- 0x0 +mem-write: 0x800162d5 <- 0x0 +mem-write: 0x800162d9 <- 0x0 +mem-write: 0x800162dd <- 0x0 +mem-write: 0x800162e1 <- 0x0 +mem-write: 0x800162e5 <- 0x0 +mem-write: 0x800162e9 <- 0x0 +mem-write: 0x800162ed <- 0x0 +mem-write: 0x800162f1 <- 0x0 +mem-write: 0x800162f5 <- 0x0 +mem-write: 0x800162f9 <- 0x0 +mem-write: 0x800162fd <- 0x0 +mem-write: 0x80016301 <- 0x0 +mem-write: 0x80016305 <- 0x0 +mem-write: 0x80016309 <- 0x0 +mem-write: 0x8001630d <- 0x0 +mem-write: 0x80016311 <- 0x0 +mem-write: 0x80016315 <- 0x0 +mem-write: 0x80016319 <- 0x0 +mem-write: 0x8001631d <- 0x0 +mem-write: 0x80016321 <- 0x0 +mem-write: 0x80016325 <- 0x0 +mem-write: 0x80016329 <- 0x0 +mem-write: 0x8001632d <- 0x0 +mem-write: 0x80016331 <- 0x0 +mem-write: 0x80016335 <- 0x0 +mem-write: 0x80016339 <- 0x0 +mem-write: 0x8001633d <- 0x0 +mem-write: 0x80016341 <- 0x0 +mem-write: 0x80016345 <- 0x0 +mem-write: 0x80016349 <- 0x0 +mem-write: 0x8001634d <- 0x0 +mem-write: 0x80016351 <- 0x0 +mem-write: 0x80016355 <- 0x0 +mem-write: 0x80016359 <- 0x0 +mem-write: 0x8001635d <- 0x0 +mem-write: 0x80016361 <- 0x0 +mem-write: 0x80016365 <- 0x0 +mem-write: 0x80016369 <- 0x0 +mem-write: 0x8001636d <- 0x0 +mem-write: 0x80016371 <- 0x0 +mem-write: 0x80016375 <- 0x0 +mem-write: 0x80016379 <- 0x0 +mem-write: 0x8001637d <- 0x0 +mem-write: 0x80016381 <- 0x0 +mem-write: 0x80016385 <- 0x0 +mem-write: 0x80016389 <- 0x0 +mem-write: 0x8001638d <- 0x0 +mem-write: 0x80016391 <- 0x0 +mem-write: 0x80016395 <- 0x0 +mem-write: 0x80016399 <- 0x0 +mem-write: 0x8001639d <- 0x0 +mem-write: 0x800163a1 <- 0x0 +mem-write: 0x800163a5 <- 0x0 +mem-write: 0x800163a9 <- 0x0 +mem-write: 0x800163ad <- 0x0 +mem-write: 0x800163b1 <- 0x0 +mem-write: 0x800163b5 <- 0x0 +mem-write: 0x800163b9 <- 0x0 +mem-write: 0x800163bd <- 0x0 +mem-write: 0x800163c1 <- 0x0 +mem-write: 0x800163c5 <- 0x0 +mem-write: 0x800163c9 <- 0x0 +mem-write: 0x800163cd <- 0x0 +mem-write: 0x800163d1 <- 0x0 +mem-write: 0x800163d5 <- 0x0 +mem-write: 0x800163d9 <- 0x0 +mem-write: 0x800163dd <- 0x0 +mem-write: 0x800163e1 <- 0x0 +mem-write: 0x800163e5 <- 0x0 +mem-write: 0x800163e9 <- 0x0 +mem-write: 0x800163ed <- 0x0 +mem-write: 0x800163f1 <- 0x0 +VXDRV: upload 1024 bytes to 0x800163f5 +mem-write: 0x800163f5 <- 0x0 +mem-write: 0x800163f9 <- 0x0 +mem-write: 0x800163fd <- 0x0 +mem-write: 0x80016401 <- 0x0 +mem-write: 0x80016405 <- 0x0 +mem-write: 0x80016409 <- 0x0 +mem-write: 0x8001640d <- 0x0 +mem-write: 0x80016411 <- 0x0 +mem-write: 0x80016415 <- 0x0 +mem-write: 0x80016419 <- 0x0 +mem-write: 0x8001641d <- 0x0 +mem-write: 0x80016421 <- 0x0 +mem-write: 0x80016425 <- 0x0 +mem-write: 0x80016429 <- 0x0 +mem-write: 0x8001642d <- 0x0 +mem-write: 0x80016431 <- 0x0 +mem-write: 0x80016435 <- 0x0 +mem-write: 0x80016439 <- 0x0 +mem-write: 0x8001643d <- 0x38000000 +mem-write: 0x80016441 <- 0x38800164 +mem-write: 0x80016445 <- 0x40800164 +mem-write: 0x80016449 <- 0x40800164 +mem-write: 0x8001644d <- 0x48800164 +mem-write: 0x80016451 <- 0x48800164 +mem-write: 0x80016455 <- 0x50800164 +mem-write: 0x80016459 <- 0x50800164 +mem-write: 0x8001645d <- 0x58800164 +mem-write: 0x80016461 <- 0x58800164 +mem-write: 0x80016465 <- 0x60800164 +mem-write: 0x80016469 <- 0x60800164 +mem-write: 0x8001646d <- 0x68800164 +mem-write: 0x80016471 <- 0x68800164 +mem-write: 0x80016475 <- 0x70800164 +mem-write: 0x80016479 <- 0x70800164 +mem-write: 0x8001647d <- 0x78800164 +mem-write: 0x80016481 <- 0x78800164 +mem-write: 0x80016485 <- 0x80800164 +mem-write: 0x80016489 <- 0x80800164 +mem-write: 0x8001648d <- 0x88800164 +mem-write: 0x80016491 <- 0x88800164 +mem-write: 0x80016495 <- 0x90800164 +mem-write: 0x80016499 <- 0x90800164 +mem-write: 0x8001649d <- 0x98800164 +mem-write: 0x800164a1 <- 0x98800164 +mem-write: 0x800164a5 <- 0xa0800164 +mem-write: 0x800164a9 <- 0xa0800164 +mem-write: 0x800164ad <- 0xa8800164 +mem-write: 0x800164b1 <- 0xa8800164 +mem-write: 0x800164b5 <- 0xb0800164 +mem-write: 0x800164b9 <- 0xb0800164 +mem-write: 0x800164bd <- 0xb8800164 +mem-write: 0x800164c1 <- 0xb8800164 +mem-write: 0x800164c5 <- 0xc0800164 +mem-write: 0x800164c9 <- 0xc0800164 +mem-write: 0x800164cd <- 0xc8800164 +mem-write: 0x800164d1 <- 0xc8800164 +mem-write: 0x800164d5 <- 0xd0800164 +mem-write: 0x800164d9 <- 0xd0800164 +mem-write: 0x800164dd <- 0xd8800164 +mem-write: 0x800164e1 <- 0xd8800164 +mem-write: 0x800164e5 <- 0xe0800164 +mem-write: 0x800164e9 <- 0xe0800164 +mem-write: 0x800164ed <- 0xe8800164 +mem-write: 0x800164f1 <- 0xe8800164 +mem-write: 0x800164f5 <- 0xf0800164 +mem-write: 0x800164f9 <- 0xf0800164 +mem-write: 0x800164fd <- 0xf8800164 +mem-write: 0x80016501 <- 0xf8800164 +mem-write: 0x80016505 <- 0x800164 +mem-write: 0x80016509 <- 0x800165 +mem-write: 0x8001650d <- 0x8800165 +mem-write: 0x80016511 <- 0x8800165 +mem-write: 0x80016515 <- 0x10800165 +mem-write: 0x80016519 <- 0x10800165 +mem-write: 0x8001651d <- 0x18800165 +mem-write: 0x80016521 <- 0x18800165 +mem-write: 0x80016525 <- 0x20800165 +mem-write: 0x80016529 <- 0x20800165 +mem-write: 0x8001652d <- 0x28800165 +mem-write: 0x80016531 <- 0x28800165 +mem-write: 0x80016535 <- 0x30800165 +mem-write: 0x80016539 <- 0x30800165 +mem-write: 0x8001653d <- 0x38800165 +mem-write: 0x80016541 <- 0x38800165 +mem-write: 0x80016545 <- 0x40800165 +mem-write: 0x80016549 <- 0x40800165 +mem-write: 0x8001654d <- 0x48800165 +mem-write: 0x80016551 <- 0x48800165 +mem-write: 0x80016555 <- 0x50800165 +mem-write: 0x80016559 <- 0x50800165 +mem-write: 0x8001655d <- 0x58800165 +mem-write: 0x80016561 <- 0x58800165 +mem-write: 0x80016565 <- 0x60800165 +mem-write: 0x80016569 <- 0x60800165 +mem-write: 0x8001656d <- 0x68800165 +mem-write: 0x80016571 <- 0x68800165 +mem-write: 0x80016575 <- 0x70800165 +mem-write: 0x80016579 <- 0x70800165 +mem-write: 0x8001657d <- 0x78800165 +mem-write: 0x80016581 <- 0x78800165 +mem-write: 0x80016585 <- 0x80800165 +mem-write: 0x80016589 <- 0x80800165 +mem-write: 0x8001658d <- 0x88800165 +mem-write: 0x80016591 <- 0x88800165 +mem-write: 0x80016595 <- 0x90800165 +mem-write: 0x80016599 <- 0x90800165 +mem-write: 0x8001659d <- 0x98800165 +mem-write: 0x800165a1 <- 0x98800165 +mem-write: 0x800165a5 <- 0xa0800165 +mem-write: 0x800165a9 <- 0xa0800165 +mem-write: 0x800165ad <- 0xa8800165 +mem-write: 0x800165b1 <- 0xa8800165 +mem-write: 0x800165b5 <- 0xb0800165 +mem-write: 0x800165b9 <- 0xb0800165 +mem-write: 0x800165bd <- 0xb8800165 +mem-write: 0x800165c1 <- 0xb8800165 +mem-write: 0x800165c5 <- 0xc0800165 +mem-write: 0x800165c9 <- 0xc0800165 +mem-write: 0x800165cd <- 0xc8800165 +mem-write: 0x800165d1 <- 0xc8800165 +mem-write: 0x800165d5 <- 0xd0800165 +mem-write: 0x800165d9 <- 0xd0800165 +mem-write: 0x800165dd <- 0xd8800165 +mem-write: 0x800165e1 <- 0xd8800165 +mem-write: 0x800165e5 <- 0xe0800165 +mem-write: 0x800165e9 <- 0xe0800165 +mem-write: 0x800165ed <- 0xe8800165 +mem-write: 0x800165f1 <- 0xe8800165 +mem-write: 0x800165f5 <- 0xf0800165 +mem-write: 0x800165f9 <- 0xf0800165 +mem-write: 0x800165fd <- 0xf8800165 +mem-write: 0x80016601 <- 0xf8800165 +mem-write: 0x80016605 <- 0x800165 +mem-write: 0x80016609 <- 0x800166 +mem-write: 0x8001660d <- 0x8800166 +mem-write: 0x80016611 <- 0x8800166 +mem-write: 0x80016615 <- 0x10800166 +mem-write: 0x80016619 <- 0x10800166 +mem-write: 0x8001661d <- 0x18800166 +mem-write: 0x80016621 <- 0x18800166 +mem-write: 0x80016625 <- 0x20800166 +mem-write: 0x80016629 <- 0x20800166 +mem-write: 0x8001662d <- 0x28800166 +mem-write: 0x80016631 <- 0x28800166 +mem-write: 0x80016635 <- 0x30800166 +mem-write: 0x80016639 <- 0x30800166 +mem-write: 0x8001663d <- 0x38800166 +mem-write: 0x80016641 <- 0x38800166 +mem-write: 0x80016645 <- 0x40800166 +mem-write: 0x80016649 <- 0x40800166 +mem-write: 0x8001664d <- 0x48800166 +mem-write: 0x80016651 <- 0x48800166 +mem-write: 0x80016655 <- 0x50800166 +mem-write: 0x80016659 <- 0x50800166 +mem-write: 0x8001665d <- 0x58800166 +mem-write: 0x80016661 <- 0x58800166 +mem-write: 0x80016665 <- 0x60800166 +mem-write: 0x80016669 <- 0x60800166 +mem-write: 0x8001666d <- 0x68800166 +mem-write: 0x80016671 <- 0x68800166 +mem-write: 0x80016675 <- 0x70800166 +mem-write: 0x80016679 <- 0x70800166 +mem-write: 0x8001667d <- 0x78800166 +mem-write: 0x80016681 <- 0x78800166 +mem-write: 0x80016685 <- 0x80800166 +mem-write: 0x80016689 <- 0x80800166 +mem-write: 0x8001668d <- 0x88800166 +mem-write: 0x80016691 <- 0x88800166 +mem-write: 0x80016695 <- 0x90800166 +mem-write: 0x80016699 <- 0x90800166 +mem-write: 0x8001669d <- 0x98800166 +mem-write: 0x800166a1 <- 0x98800166 +mem-write: 0x800166a5 <- 0xa0800166 +mem-write: 0x800166a9 <- 0xa0800166 +mem-write: 0x800166ad <- 0xa8800166 +mem-write: 0x800166b1 <- 0xa8800166 +mem-write: 0x800166b5 <- 0xb0800166 +mem-write: 0x800166b9 <- 0xb0800166 +mem-write: 0x800166bd <- 0xb8800166 +mem-write: 0x800166c1 <- 0xb8800166 +mem-write: 0x800166c5 <- 0xc0800166 +mem-write: 0x800166c9 <- 0xc0800166 +mem-write: 0x800166cd <- 0xc8800166 +mem-write: 0x800166d1 <- 0xc8800166 +mem-write: 0x800166d5 <- 0xd0800166 +mem-write: 0x800166d9 <- 0xd0800166 +mem-write: 0x800166dd <- 0xd8800166 +mem-write: 0x800166e1 <- 0xd8800166 +mem-write: 0x800166e5 <- 0xe0800166 +mem-write: 0x800166e9 <- 0xe0800166 +mem-write: 0x800166ed <- 0xe8800166 +mem-write: 0x800166f1 <- 0xe8800166 +mem-write: 0x800166f5 <- 0xf0800166 +mem-write: 0x800166f9 <- 0xf0800166 +mem-write: 0x800166fd <- 0xf8800166 +mem-write: 0x80016701 <- 0xf8800166 +mem-write: 0x80016705 <- 0x800166 +mem-write: 0x80016709 <- 0x800167 +mem-write: 0x8001670d <- 0x8800167 +mem-write: 0x80016711 <- 0x8800167 +mem-write: 0x80016715 <- 0x10800167 +mem-write: 0x80016719 <- 0x10800167 +mem-write: 0x8001671d <- 0x18800167 +mem-write: 0x80016721 <- 0x18800167 +mem-write: 0x80016725 <- 0x20800167 +mem-write: 0x80016729 <- 0x20800167 +mem-write: 0x8001672d <- 0x28800167 +mem-write: 0x80016731 <- 0x28800167 +mem-write: 0x80016735 <- 0x30800167 +mem-write: 0x80016739 <- 0x30800167 +mem-write: 0x8001673d <- 0x38800167 +mem-write: 0x80016741 <- 0x38800167 +mem-write: 0x80016745 <- 0x40800167 +mem-write: 0x80016749 <- 0x40800167 +mem-write: 0x8001674d <- 0x48800167 +mem-write: 0x80016751 <- 0x48800167 +mem-write: 0x80016755 <- 0x50800167 +mem-write: 0x80016759 <- 0x50800167 +mem-write: 0x8001675d <- 0x58800167 +mem-write: 0x80016761 <- 0x58800167 +mem-write: 0x80016765 <- 0x60800167 +mem-write: 0x80016769 <- 0x60800167 +mem-write: 0x8001676d <- 0x68800167 +mem-write: 0x80016771 <- 0x68800167 +mem-write: 0x80016775 <- 0x70800167 +mem-write: 0x80016779 <- 0x70800167 +mem-write: 0x8001677d <- 0x78800167 +mem-write: 0x80016781 <- 0x78800167 +mem-write: 0x80016785 <- 0x80800167 +mem-write: 0x80016789 <- 0x80800167 +mem-write: 0x8001678d <- 0x88800167 +mem-write: 0x80016791 <- 0x88800167 +mem-write: 0x80016795 <- 0x90800167 +mem-write: 0x80016799 <- 0x90800167 +mem-write: 0x8001679d <- 0x98800167 +mem-write: 0x800167a1 <- 0x98800167 +mem-write: 0x800167a5 <- 0xa0800167 +mem-write: 0x800167a9 <- 0xa0800167 +mem-write: 0x800167ad <- 0xa8800167 +mem-write: 0x800167b1 <- 0xa8800167 +mem-write: 0x800167b5 <- 0xb0800167 +mem-write: 0x800167b9 <- 0xb0800167 +mem-write: 0x800167bd <- 0xb8800167 +mem-write: 0x800167c1 <- 0xb8800167 +mem-write: 0x800167c5 <- 0xc0800167 +mem-write: 0x800167c9 <- 0xc0800167 +mem-write: 0x800167cd <- 0xc8800167 +mem-write: 0x800167d1 <- 0xc8800167 +mem-write: 0x800167d5 <- 0xd0800167 +mem-write: 0x800167d9 <- 0xd0800167 +mem-write: 0x800167dd <- 0xd8800167 +mem-write: 0x800167e1 <- 0xd8800167 +mem-write: 0x800167e5 <- 0xe0800167 +mem-write: 0x800167e9 <- 0xe0800167 +mem-write: 0x800167ed <- 0xe8800167 +mem-write: 0x800167f1 <- 0xe8800167 +VXDRV: upload 503 bytes to 0x800167f5 +mem-write: 0x800167f5 <- 0xf0800167 +mem-write: 0x800167f9 <- 0xf0800167 +mem-write: 0x800167fd <- 0xf8800167 +mem-write: 0x80016801 <- 0xf8800167 +mem-write: 0x80016805 <- 0x800167 +mem-write: 0x80016809 <- 0x800168 +mem-write: 0x8001680d <- 0x8800168 +mem-write: 0x80016811 <- 0x8800168 +mem-write: 0x80016815 <- 0x10800168 +mem-write: 0x80016819 <- 0x10800168 +mem-write: 0x8001681d <- 0x18800168 +mem-write: 0x80016821 <- 0x18800168 +mem-write: 0x80016825 <- 0x20800168 +mem-write: 0x80016829 <- 0x20800168 +mem-write: 0x8001682d <- 0x28800168 +mem-write: 0x80016831 <- 0x28800168 +mem-write: 0x80016835 <- 0x30800168 +mem-write: 0x80016839 <- 0x30800168 +mem-write: 0x8001683d <- 0x43800168 +mem-write: 0x80016841 <- 0x0 +mem-write: 0x80016845 <- 0x0 +mem-write: 0x80016849 <- 0x0 +mem-write: 0x8001684d <- 0x0 +mem-write: 0x80016851 <- 0x0 +mem-write: 0x80016855 <- 0x0 +mem-write: 0x80016859 <- 0x0 +mem-write: 0x8001685d <- 0x43000000 +mem-write: 0x80016861 <- 0x0 +mem-write: 0x80016865 <- 0x0 +mem-write: 0x80016869 <- 0x0 +mem-write: 0x8001686d <- 0x0 +mem-write: 0x80016871 <- 0x0 +mem-write: 0x80016875 <- 0x0 +mem-write: 0x80016879 <- 0x0 +mem-write: 0x8001687d <- 0x43000000 +mem-write: 0x80016881 <- 0x0 +mem-write: 0x80016885 <- 0x0 +mem-write: 0x80016889 <- 0x0 +mem-write: 0x8001688d <- 0x0 +mem-write: 0x80016891 <- 0x0 +mem-write: 0x80016895 <- 0x0 +mem-write: 0x80016899 <- 0x0 +mem-write: 0x8001689d <- 0x43000000 +mem-write: 0x800168a1 <- 0x0 +mem-write: 0x800168a5 <- 0x0 +mem-write: 0x800168a9 <- 0x0 +mem-write: 0x800168ad <- 0x0 +mem-write: 0x800168b1 <- 0x0 +mem-write: 0x800168b5 <- 0x0 +mem-write: 0x800168b9 <- 0x0 +mem-write: 0x800168bd <- 0x43000000 +mem-write: 0x800168c1 <- 0x0 +mem-write: 0x800168c5 <- 0x0 +mem-write: 0x800168c9 <- 0x0 +mem-write: 0x800168cd <- 0x0 +mem-write: 0x800168d1 <- 0x0 +mem-write: 0x800168d5 <- 0x0 +mem-write: 0x800168d9 <- 0x0 +mem-write: 0x800168dd <- 0x43000000 +mem-write: 0x800168e1 <- 0x0 +mem-write: 0x800168e5 <- 0x0 +mem-write: 0x800168e9 <- 0x0 +mem-write: 0x800168ed <- 0x0 +mem-write: 0x800168f1 <- 0x0 +mem-write: 0x800168f5 <- 0x0 +mem-write: 0x800168f9 <- 0x0 +mem-write: 0x800168fd <- 0x43000000 +mem-write: 0x80016901 <- 0x0 +mem-write: 0x80016905 <- 0x0 +mem-write: 0x80016909 <- 0x0 +mem-write: 0x8001690d <- 0x0 +mem-write: 0x80016911 <- 0x0 +mem-write: 0x80016915 <- 0x0 +mem-write: 0x80016919 <- 0x0 +mem-write: 0x8001691d <- 0x74000000 +mem-write: 0x80016921 <- 0x18800100 +mem-write: 0x80016925 <- 0x8000e0 +mem-write: 0x80016929 <- 0xfc000000 +mem-write: 0x8001692d <- 0x6c800154 +mem-write: 0x80016931 <- 0x18800153 +mem-write: 0x80016935 <- 0x1880014a +mem-write: 0x80016939 <- 0x1880014a +mem-write: 0x8001693d <- 0x1880014a +mem-write: 0x80016941 <- 0x1880014a +mem-write: 0x80016945 <- 0x1880014a +mem-write: 0x80016949 <- 0x1880014a +mem-write: 0x8001694d <- 0x1880014a +mem-write: 0x80016951 <- 0x1880014a +mem-write: 0x80016955 <- 0xff80014a +mem-write: 0x80016959 <- 0xffffffff +mem-write: 0x8001695d <- 0xffffffff +mem-write: 0x80016961 <- 0xffffffff +mem-write: 0x80016965 <- 0x10000ff +mem-write: 0x80016969 <- 0x43534100 +mem-write: 0x8001696d <- 0x4949 +mem-write: 0x80016971 <- 0x0 +mem-write: 0x80016975 <- 0x0 +mem-write: 0x80016979 <- 0x0 +mem-write: 0x8001697d <- 0x0 +mem-write: 0x80016981 <- 0x0 +mem-write: 0x80016985 <- 0x0 +mem-write: 0x80016989 <- 0x43534100 +mem-write: 0x8001698d <- 0x4949 +mem-write: 0x80016991 <- 0x0 +mem-write: 0x80016995 <- 0x0 +mem-write: 0x80016999 <- 0x0 +mem-write: 0x8001699d <- 0x0 +mem-write: 0x800169a1 <- 0x0 +mem-write: 0x800169a5 <- 0x0 +mem-write: 0x800169a9 <- 0x0 +mem-write: 0x800169ad <- 0x0 +mem-write: 0x800169b1 <- 0x0 +mem-write: 0x800169b5 <- 0x3ff000 +mem-write: 0x800169b9 <- 0x0 +mem-write: 0x800169bd <- 0x402400 +mem-write: 0x800169c1 <- 0x0 +mem-write: 0x800169c5 <- 0x10435000 +mem-write: 0x800169c9 <- 0x800160 +mem-write: 0x800169cd <- 0x100000 +mem-write: 0x800169d1 <- 0x700000 +mem-write: 0x800169d5 <- 0x100200 +mem-write: 0x800169d9 <- 0x100100 +mem-write: 0x800169dd <- 0x10100000 +mem-write: 0x800169e1 <- 0xff800160 +mem-write: 0x800169e5 <- 0xffffff +mem-write: 0x800169e9 <- 0xe0000200 +Device running... +DEBUG ../../../simX/core.cpp:732: Creating a new thread with PC: 80000000 + +DEBUG ../../../simX/core.cpp:732: Creating a new thread with PC: 80000000 + +DEBUG ../../../simX/core.cpp:732: Creating a new thread with PC: 80000000 + +DEBUG ../../../simX/core.cpp:732: Creating a new thread with PC: 80000000 + +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000000 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 597 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x597 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000000: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000004 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d458593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd458593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000004: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 800000d4 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000004 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000008 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2000513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2000513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000008: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000020 (0) + %r11: 800000d4 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000008 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 7 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000000c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5106b +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5106b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000000c: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:961: WSPAWN +DEBUG ../../../simX/instruction.cpp:969: Spawning 4 new warps at PC: 800000d4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000020 (0) + %r11: 800000d4 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000000c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 1 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 8 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000000c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 1 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 9 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2000513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2000513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000020 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 10 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 11 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 12 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 13 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2000513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2000513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000020 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 14 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2000513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2000513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000020 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 15 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000010 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000010: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800000d4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000014 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000020 (0) + %r11: 800000d4 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000010 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 16 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d8: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 17 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d8: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 18 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d8: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 19 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 20 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 21 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2000513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2000513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000014 (0) + %r 2: 00000000 (0) + %r 3: 00000000 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000020 (0) + %r11: 800000d4 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 22 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 16197 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x16197 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000dc: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 800160dc 800160dc 800160dc 800160dc (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000dc +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 3 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 23 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 16197 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x16197 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000dc: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 800160dc 800160dc 800160dc 800160dc (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000dc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 3 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 24 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 16197 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x16197 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000dc: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 800160dc 800160dc 800160dc 800160dc (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000dc +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 3 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 25 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d8: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 00000000 00000000 00000000 00000000 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 800000d4 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 26 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72c18193 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72c18193 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 3 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 27 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72c18193 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72c18193 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 3 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 28 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72c18193 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72c18193 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 3 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 29 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21026f3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21026f3 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e4: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 30 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21026f3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21026f3 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e4: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 31 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21026f3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21026f3 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e4: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 32 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 16197 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x16197 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000dc: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 800160dc 800160dc 800160dc 800160dc (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 800000d4 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 3 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 33 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a69693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a69693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 04000000 04000000 04000000 04000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 34 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a69693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a69693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 08000000 08000000 08000000 08000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 35 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a69693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a69693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 36 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72c18193 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72c18193 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 800000d4 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 3 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 37 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2002673 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2002673 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000ec: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 0 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 1 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 2 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 (0) + %r13: 04000000 04000000 04000000 04000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000ec +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 38 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2002673 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2002673 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000ec: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 0 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 1 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 2 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 (0) + %r13: 08000000 08000000 08000000 08000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000ec +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 39 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2002673 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2002673 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000ec: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 0 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 1 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 2 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000ec +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 40 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21026f3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21026f3 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e4: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 800000d4 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 41 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a61593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa61593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000001 00000002 00000003 (0) + %r13: 04000000 04000000 04000000 04000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 42 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a61593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa61593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000001 00000002 00000003 (0) + %r13: 08000000 08000000 08000000 08000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 43 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a61593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa61593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000001 00000002 00000003 (0) + %r13: 0c000000 0c000000 0c000000 0c000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 44 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a69693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a69693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 800000d4 00000000 00000000 00000000 (0) + %r12: 00000000 00000000 00000000 00000000 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 45 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 261613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x261613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 04000000 04000000 04000000 04000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 46 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 261613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x261613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 08000000 08000000 08000000 08000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 47 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 261613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x261613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 0c000000 0c000000 0c000000 0c000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 48 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2002673 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2002673 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000ec: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 0 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 1 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 2 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 800000d4 00000000 00000000 00000000 (0) + %r12: 00000000 00000001 00000002 00000003 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 49 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6ffff137 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6ffff137 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 04000000 04000000 04000000 04000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 50 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6ffff137 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6ffff137 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 08000000 08000000 08000000 08000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 51 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6ffff137 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6ffff137 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 0c000000 0c000000 0c000000 0c000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 52 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a61593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa61593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000001 00000002 00000003 (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 53 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40b10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40b10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000fc: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 04000000 04000000 04000000 04000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000fc +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 54 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40b10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40b10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000fc: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 08000000 08000000 08000000 08000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000fc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 55 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40b10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40b10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000fc: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 0c000000 0c000000 0c000000 0c000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000fc +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 56 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 261613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x261613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 00000000 00000000 00000000 00000000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 57 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000100 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40d10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40d10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000100: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec00 6bffe800 6bffe400 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 04000000 04000000 04000000 04000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000100 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 58 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000100 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 59 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000100 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 60 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000100 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 61 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000100 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40d10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40d10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000100: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec00 67ffe800 67ffe400 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 08000000 08000000 08000000 08000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000100 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 62 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000100 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40d10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40d10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000100: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec00 63ffe800 63ffe400 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 0c000000 0c000000 0c000000 0c000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000100 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 63 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6ffff137 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6ffff137 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000f8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6ffff000 6ffff000 6ffff000 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 64 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000104 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000104: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 04000000 04000000 04000000 04000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000104 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 65 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000104 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000104: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 08000000 08000000 08000000 08000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000104 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 66 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000104 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000104: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 0c000000 0c000000 0c000000 0c000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000104 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 67 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40b10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40b10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000fc: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 68 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000108 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21026f3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21026f3 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000108: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000108 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 69 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000108 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21026f3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21026f3 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000108: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000108 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 70 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000108 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21026f3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21026f3 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000108: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000108 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 71 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000100 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40d10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40d10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000100: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec00 6fffe800 6fffe400 (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 72 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000010c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000010c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000010c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 73 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000010c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000010c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000010c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 74 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000010c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000010c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000010c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 75 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000104 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c10133 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc10133 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000104: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000104 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 76 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000108 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21026f3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21026f3 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000108: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000108 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 77 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000010c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000010c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000118 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000010c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 78 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000110 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000110: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 6bfff000 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000110 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 79 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000110 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000110: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 67fff000 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000110 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 80 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000110 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 81 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000110 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000110: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 00000000 00000000 00000000 (0) + %r 2: 63fff000 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000110 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 82 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000114 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000114: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0:(0) + %r 1:(0) + %r 2:(0) + %r 3:(0) + %r 4:(0) + %r 5:(0) + %r 6:(0) + %r 7:(0) + %r 8:(0) + %r 9:(0) + %r10:(0) + %r11:(0) + %r12:(0) + %r13:(0) + %r14:(0) + %r15:(0) + %r16:(0) + %r17:(0) + %r18:(0) + %r19:(0) + %r20:(0) + %r21:(0) + %r22:(0) + %r23:(0) + %r24:(0) + %r25:(0) + %r26:(0) + %r27:(0) + %r28:(0) + %r29:(0) + %r30:(0) + %r31:(0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 0 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 0 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000114 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 83 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000114 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000114: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0:(0) + %r 1:(0) + %r 2:(0) + %r 3:(0) + %r 4:(0) + %r 5:(0) + %r 6:(0) + %r 7:(0) + %r 8:(0) + %r 9:(0) + %r10:(0) + %r11:(0) + %r12:(0) + %r13:(0) + %r14:(0) + %r15:(0) + %r16:(0) + %r17:(0) + %r18:(0) + %r19:(0) + %r20:(0) + %r21:(0) + %r22:(0) + %r23:(0) + %r24:(0) + %r25:(0) + %r26:(0) + %r27:(0) + %r28:(0) + %r29:(0) + %r30:(0) + %r31:(0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 0 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 0 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000114 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 84 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000114 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000114: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0:(0) + %r 1:(0) + %r 2:(0) + %r 3:(0) + %r 4:(0) + %r 5:(0) + %r 6:(0) + %r 7:(0) + %r 8:(0) + %r 9:(0) + %r10:(0) + %r11:(0) + %r12:(0) + %r13:(0) + %r14:(0) + %r15:(0) + %r16:(0) + %r17:(0) + %r18:(0) + %r19:(0) + %r20:(0) + %r21:(0) + %r22:(0) + %r23:(0) + %r24:(0) + %r25:(0) + %r26:(0) + %r27:(0) + %r28:(0) + %r29:(0) + %r30:(0) + %r31:(0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 0 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 0 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000114 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 85 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000118 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000118: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000014, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000014 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000020 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000118 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 86 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 87 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 88 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 89 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 90 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 91 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000014 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000014: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000014 00000000 00000000 00000000 (0) + %r 2: 6ffff000 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000000 00000000 00000000 00000000 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000014 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 92 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000018 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000018: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000014 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000018 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 93 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 94 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 95 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 96 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 97 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 98 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 99 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000001c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e418513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e418513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000001c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000014 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000001c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 100 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000020 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 24c18613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x24c18613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000020: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000014 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 80016a54 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000020 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 101 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000024 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40a60633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40a60633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000024: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000014 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000024 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 102 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000028 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000028: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000014 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000028 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 103 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000002c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5ed000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5ed000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000002c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000002c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 104 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000002c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 105 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 106 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 107 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 108 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 109 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 110 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f00313 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf00313 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 111 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 112 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 113 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 114 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000000 (0) + %r14: 800169ec (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 115 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c37e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c37e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e20: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000000 (0) + %r14: 800169ec (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 116 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 117 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 118 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 119 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 120 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 121 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f77793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf77793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e24: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000000 (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 122 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a079063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa079063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e28: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 12 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000ec8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000000 (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 123 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 124 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 125 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 126 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 127 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 128 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 129 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ec8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 279693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x279693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ec8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000030 (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ec8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 130 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ec8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 131 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ec8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 132 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ec8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 133 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ecc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 297 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x297 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ecc: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000ecc (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 00000030 (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ecc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 5 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 134 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ed0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ed0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000ecc (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ed0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 135 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ed4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8293 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8293 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ed4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ed4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 5 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 136 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ed8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa0680e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa0680e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ed8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r13=80000efc, imm=4294967200 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e9c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000edc (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ed8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 137 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ed8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 138 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 139 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 140 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 141 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 142 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 143 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b701a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb701a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e9c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800169ec, rb=0, imm=3 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169ef +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000edc (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 144 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 145 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 146 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 147 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70123 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70123 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800169ec, rb=0, imm=2 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169ee +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000edc (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 148 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b700a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb700a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800169ec, rb=0, imm=1 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169ed +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000edc (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 149 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800169ec, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169ec +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000edc (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 150 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000eac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000eac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000edc, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000edc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000edc (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000eac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 151 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 152 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 153 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 154 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 155 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 156 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000edc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 28093 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x28093 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000edc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: 0000000c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000edc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 5 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 157 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ee0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff078793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff078793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ee0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169ec (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ee0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 158 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ee4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40f70733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40f70733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ee4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000068 (0) + %r13: 80000efc (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ee4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 159 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ee8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f60633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf60633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ee8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000064 (0) + %r13: 80000efc (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ee8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 160 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000eec +DEBUG ../../../simX/enc.cpp:105: Curr Code: f6c378e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf6c378e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000eec: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000064 (0) + %r13: 80000efc (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000eec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 161 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000eec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 162 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 163 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 164 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 165 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 166 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 167 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 168 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ef0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f3dff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf3dff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ef0: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000064 (0) + %r13: 80000efc (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ef0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 169 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 170 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 171 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 172 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 173 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 174 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8059263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8059263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e2c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000064 (0) + %r13: 80000efc (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 175 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 176 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 177 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 178 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 179 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 180 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff067693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff067693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000064 (0) + %r13: 00000060 (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 181 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f67613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf67613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e34: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 00000060 (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 182 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e38: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 183 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800169f0, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169f0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 184 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800169f0, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169f4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 185 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 186 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 187 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 188 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800169f0, rb=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169f8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 189 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800169f0, rb=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 800169f0 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 190 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a00 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 191 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed766e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed766e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e50: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e3c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a00 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 192 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 193 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 194 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 195 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 196 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 197 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 198 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a00, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a00 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a00 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 199 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a00, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a04 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a00 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 200 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a00, rb=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a08 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a00 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 201 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a00, rb=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a0c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a00 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 202 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a10 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 203 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed766e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed766e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e50: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e3c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a10 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 204 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 205 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 206 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 207 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 208 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 209 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 210 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a10, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a10 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a10 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 211 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a10, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a10 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 212 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a10, rb=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a18 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a10 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 213 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a10, rb=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a10 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 214 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a20 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 215 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed766e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed766e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e50: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e3c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a20 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 216 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 217 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 218 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 219 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 220 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 221 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 222 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a20, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a20 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a20 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 223 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a20, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a24 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a20 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 224 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a20, rb=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a28 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a20 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 225 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a20, rb=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a20 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 226 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a30 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 227 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed766e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed766e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e50: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e3c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a30 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 228 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 229 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 230 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 231 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 232 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 233 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 234 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a30, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a30 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a30 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 235 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a30, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a30 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 236 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a30, rb=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a30 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 237 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a30, rb=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a3c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a30 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 238 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a40 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 239 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed766e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed766e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e50: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e3c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a40 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 240 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 241 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 242 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 243 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 244 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 245 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 246 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a40, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a40 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a40 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 247 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a40, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a44 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a40 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 248 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a40, rb=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a48 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a40 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 249 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b72623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb72623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a40, rb=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a4c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a40 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 250 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 251 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed766e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed766e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e50: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 252 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 253 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 254 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 255 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 256 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 257 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 258 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 61463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x61463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e54: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 4 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e5c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80016a50 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 12 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 259 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 260 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 261 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 262 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 263 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 264 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40c306b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40c306b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e5c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 0000000b (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 265 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 269693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x269693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e60: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000030 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 0000002c (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 266 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 297 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x297 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e64: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 0000002c (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 5 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 267 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e68: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 268 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 269 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c68067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc68067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e6c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r13=80000e90, imm=12 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e9c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 270 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 271 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 272 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 273 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 274 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 275 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 276 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 277 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b701a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb701a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e9c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a50, rb=0, imm=3 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a53 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 278 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70123 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70123 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a50, rb=0, imm=2 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a52 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 279 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b700a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb700a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a50, rb=0, imm=1 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a51 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 280 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016a50, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 281 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000eac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000eac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000030, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000030 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 800169ec (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000eac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 282 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 283 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 284 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 285 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 286 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 287 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000030 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1517 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1517 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000030: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80001030 (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000030 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 288 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000034 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cf050513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcf050513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000034: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000030 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80000d20 (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000034 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 289 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000038 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a5000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a5000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000038: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000cdc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80000d20 (0) + %r11: 00000000 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000038 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 290 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 291 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 292 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 293 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 294 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 295 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 296 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cdc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cdc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80000d20 (0) + %r11: 80000d20 (0) + %r12: 00000004 (0) + %r13: 80000e90 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 297 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 298 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 299 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 300 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ce0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ce0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80000d20 (0) + %r11: 80000d20 (0) + %r12: 00000004 (0) + %r13: 00000000 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ce0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 301 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ce4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ce4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80000d20 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ce4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 302 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ce8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ce8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ce8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 303 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7590206f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7590206f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cec: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003c44 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016a50 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 304 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 305 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 306 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 307 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 308 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 309 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c01a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c01a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c44: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=448 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169c8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016010 (0) + %r15: fffffffc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 310 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 311 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 312 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 313 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 14872783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x14872783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c48: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80016010, imm=328 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016158 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016010 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 314 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4078c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4078c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c4c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003ca4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016010 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 315 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 316 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 317 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 318 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 319 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 320 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 321 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 322 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 323 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 324 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ca4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 14c70793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x14c70793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ca4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016010 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 325 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 326 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 327 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 328 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ca8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 14f72423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x14f72423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ca8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016010, rf=8001615c, imm=328 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016158 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016010 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 329 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003cac +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa5ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa5ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003cac: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003c50 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80016010 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 330 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 331 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 332 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 333 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 334 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 335 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 336 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 47a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x47a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=8001615c, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016160 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 337 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1f00813 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1f00813 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c54: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 0000001f (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 338 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6e84e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6e84e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c58: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 0000001f (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 339 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 340 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 341 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 342 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 343 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 344 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 345 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 271813 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x271813 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 346 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2050663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2050663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c60: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003c8c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 347 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 348 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 349 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 350 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 351 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 352 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 170713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x170713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c8c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 353 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c90: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=8001615c, re=1, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016160 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 354 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c94: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 355 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b7a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb7a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c98: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=8001615c, rb=80000d20, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016164 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 356 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 357 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003c9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003c9c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003c9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 358 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ca0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ca0: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000003c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000003c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000003c (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ca0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 359 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ca0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 360 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 361 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 362 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 363 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 364 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 365 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000003c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 541000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x541000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000003c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000d7c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000003c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 366 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 367 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 368 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 369 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 370 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 371 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d7c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 372 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 373 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 374 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 375 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d80: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeff0, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeff8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 376 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 377 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 378 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 379 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d84: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeff0, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeff0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 380 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80016437 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80016437 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d88: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 381 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80016937 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80016937 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d8c: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 8001615c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 382 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d90: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 383 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 384 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40f90933 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40f90933 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d98: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 18 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 385 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d9c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeff0, r1=80000040, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeffc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 386 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000da0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000da0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeff0, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeff4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000da0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 387 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000da0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 388 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000da4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40295913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40295913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000da4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000da4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 389 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000da8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2090063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2090063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000da8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000dc8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000da8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 390 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 391 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 392 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 393 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 394 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 395 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 396 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000dc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80016437 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80016437 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000dc8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 397 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 398 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 399 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 400 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000dcc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80016937 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80016937 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000dcc: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dcc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 401 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000dd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000dd0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dd0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 402 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000dd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 490913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x490913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000dd4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016004 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 403 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000dd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40f90933 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40f90933 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000dd8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000004 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 18 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 404 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ddc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40295913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40295913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ddc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ddc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 405 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000de0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2090063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2090063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000de0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000de0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 406 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000de0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 407 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 408 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 409 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 410 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 411 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 412 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 413 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 414 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000de4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000de4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000de4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 415 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000de8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000de8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000de8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 416 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000dec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000dec: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800000bc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 800000bc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 417 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000df0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 148493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x148493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000df0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 800000bc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000df0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 418 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000df4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 440413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x440413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000df4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 800000bc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000df4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 419 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000df8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000df8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=800000bc, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800000bc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000dfc (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 800000bc (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000df8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 420 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 421 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 422 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 423 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 424 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 425 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 426 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 427 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000bc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000dfc (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 428 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 429 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 430 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 431 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000c0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800000d0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000dfc (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 432 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 433 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 434 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 435 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 436 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 437 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 438 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000d0: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000dfc, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000dfc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000dfc (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 439 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 440 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 441 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 442 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 443 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 444 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000dfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe9918e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe9918e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000dfc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 1 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000dfc (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 445 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 446 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 447 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 448 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 449 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 450 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e00: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeff0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeffc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000040 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 451 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e04: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeff0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeff8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 452 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e08: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeff0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeff4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000001 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 453 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e0c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeff0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeff0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 454 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e10: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 455 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e14: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000040, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000040 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000040 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 456 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 457 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 458 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 459 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 460 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 461 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000040 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000040: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000048 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 462 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 463 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 464 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 465 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 466 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 467 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 468 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 469 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 470 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000048 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000048: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000048 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 471 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000004c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000004c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000004c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 472 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000050 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000050: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefd0, r1=80000044, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeffc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000050 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 473 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000054 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72c000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72c000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000054: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000058 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000054 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 474 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 475 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 476 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 477 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 478 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 479 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000058 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 480 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 481 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 482 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 483 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 484 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 485 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 486 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 487 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 488 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000784 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000784: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000058, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000058 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000058 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000784 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 489 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 490 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 491 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 492 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 493 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 494 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000058 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80015537 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80015537 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000058: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000058 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80015000 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 495 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000005c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a0450513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa0450513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000005c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000058 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000005c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 496 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000060 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6d5000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6d5000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000060: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000f34 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000060 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 497 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 498 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 499 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 500 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 501 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 502 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 503 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d81a303 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d81a303 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f34: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=472 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169e0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 504 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 505 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 506 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 507 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fc010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfc010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f38: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 508 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rc=0, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 509 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2d12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2d12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rd=0, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 510 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 511 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 512 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 513 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2b12223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2b12223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rb=80000d20, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 514 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e12823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e12823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, re=1, imm=48 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 515 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f12a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f12a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f4c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rf=0, imm=52 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 516 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3012c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3012c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f50: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r10=0, imm=56 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 517 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f54: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r11=0, imm=60 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefcc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80000d20 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 518 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 832583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x832583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f58: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r6=80016010, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016018 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 6 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 519 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2410693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2410693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 520 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f60: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a04 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 521 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f64: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 6 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 522 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f68: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r1=80000064, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 523 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f6c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rd=6fffefb4, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 524 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f70: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000f80 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 525 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 526 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 527 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 528 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 529 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 530 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 531 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 532 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 533 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 534 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f84: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r1=80000f74, imm=492 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 535 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1f212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1f212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f88: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r12=0, imm=480 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef80 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 536 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f8c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r18=0, imm=456 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef68 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 537 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 538 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1da12023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1da12023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f90: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r1a=0, imm=448 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef60 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 26 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 539 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58c13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58c13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 540 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f98: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 541 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d12a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd12a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f9c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rd=6fffefb4, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 542 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fa0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fa0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r8=0, imm=488 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fa0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 543 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fa4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fa4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r9=0, imm=484 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 544 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fa8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fa8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r13=0, imm=476 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef7c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fa8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 545 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fac: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r14=0, imm=472 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef78 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 546 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fb0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r15=0, imm=468 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef74 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fb0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 547 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fb4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r16=0, imm=464 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef70 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 548 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fb8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r17=0, imm=460 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef6c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fb8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 549 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fbc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r19=0, imm=452 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef64 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 25 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 550 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1bb12e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1bb12e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fc0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r1b=0, imm=444 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef5c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 27 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 551 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 27 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 552 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 27 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 553 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 27 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 554 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50d13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50d13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fc4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 26 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 555 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 570060ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x570060ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fc8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007538 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 556 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 557 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 558 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 559 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 560 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 561 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007538 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12818513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12818513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007538: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016930 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 562 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 563 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 564 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 565 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000753c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000753c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000fcc, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000fcc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016930 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000753c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 566 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 567 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 568 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 569 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 570 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 571 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fcc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fcc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016930, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016930 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8001536c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016930 (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 8001536c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fcc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 572 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fd0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 8001536c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 573 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f12823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f12823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fd4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=8001536c, imm=48 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedd0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 8001536c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 574 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 514080ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x514080ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fd8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800094ec +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 8001536c (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 575 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 576 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 577 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 578 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 579 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 580 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 581 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 582 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 583 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 357793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x357793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 584 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 585 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 586 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 587 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 588 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4079c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4079c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 6fffefb4 (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 589 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 590 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 591 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 592 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 593 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 594 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7f7f86b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7f7f86b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094f8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 7f7f8000 (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 595 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f7f68693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf7f68693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094fc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a04 (0) + %r13: 7f7f7f7f (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 596 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009500 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009500: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 80014a04 (0) + %r13: 7f7f7f7f (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 597 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 598 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 599 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 600 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009504 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009504: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=8001536c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001536c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009504 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 601 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009508 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 470713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x470713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009508: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009508 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 602 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000950c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d677b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd677b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000950c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000950c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 603 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009510 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009510: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 7f7f7fad (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009510 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 604 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009514 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c7e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc7e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009514: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 7f7f7faf (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009514 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 605 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009514 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 606 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009514 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 607 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009518 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d7e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd7e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009518: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 7f7f7fff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009518 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 608 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009518 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 609 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000951c +DEBUG ../../../simX/enc.cpp:105: Curr Code: feb784e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfeb784e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000951c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 7f7f7fff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000951c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 610 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000951c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 611 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 612 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 613 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 614 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 615 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 616 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 617 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 618 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009520 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc74683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc74683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009520: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80015370, imm=4294967292 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001536c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 0000002e (0) + %r14: 80015370 (0) + %r15: 7f7f7fff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009520 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 619 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009524 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffd74603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffd74603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009524: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80015370, imm=4294967293 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001536c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 80015370 (0) + %r15: 7f7f7fff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009524 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 620 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009528 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffe74783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffe74783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009528: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80015370, imm=4294967294 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001536c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 80015370 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009528 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 621 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000952c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40a70733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40a70733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000952c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000952c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 622 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009530 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4068063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4068063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009530: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009530 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 623 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 624 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 625 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 626 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 627 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 628 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009534 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2060a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2060a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009534: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80009568 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009534 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 12 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 629 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 630 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 631 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 632 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 633 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 634 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009568 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffd70513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffd70513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009568: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 635 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 636 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 637 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 638 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000956c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000956c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000fdc, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000fdc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000956c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 639 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 640 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 641 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 642 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 643 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 644 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fdc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2a12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2a12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fdc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, ra=1, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedcc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 645 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fe0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fe0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=240 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fe0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 646 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fe4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fe4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=244 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee94 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fe4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 647 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fe8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fe8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=248 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee98 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fe8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 648 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fec +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=252 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 649 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ff0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d0663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd0663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ff0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ff0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 26 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 650 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 651 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 652 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 653 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 654 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 655 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ff4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 38d2703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x38d2703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ff4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r26=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ff4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 656 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ff8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a0708e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa0708e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ff8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800018a8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ff8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 657 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 658 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 659 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 660 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 661 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 662 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 663 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 664 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 665 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800018a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d0513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd0513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800018a8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800018a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 666 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800018a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 667 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800018a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 668 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800018a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 669 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800018ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 349020ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x349020ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800018ac: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800043f4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800018ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 670 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 671 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 672 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 673 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 674 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 675 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800043f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3852783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3852783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800043f4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800043f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 676 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800043f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 677 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800043f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 678 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800043f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 679 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800043f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800043f8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004400 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800043f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 680 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 681 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 682 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 683 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 684 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 685 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 686 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004400 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cedff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcedff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004400: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800040ec +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004400 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 687 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004400 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 688 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004400 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 689 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004400 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 690 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 691 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 692 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 693 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 694 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 695 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 696 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 697 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 698 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 699 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 800047b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x800047b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040f0: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 700 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040f4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed80, r1=800018b0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 701 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040f8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed80, r8=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed98 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 702 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040fc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed80, r9=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed94 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 703 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004100 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004100: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed80, r12=80014a04, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 704 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 705 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 706 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 707 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004104 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004104: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed80, r13=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004104 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 708 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004108 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004108: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed80, r14=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004108 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 709 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000410c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1512223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1512223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000410c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed80, r15=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000410c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 710 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004110 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1612023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1612023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004110: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed80, r16=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed80 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004110 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 711 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004114 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 452403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x452403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004114: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016010, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016014 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800162fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 80004000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004114 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 712 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004118 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e078793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe078793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004118: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004118 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 713 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000411c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f52e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f52e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000411c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r10=80016010, rf=800040e0, imm=60 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001604c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000411c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 714 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004120 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2ec50713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2ec50713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004120: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 800040e0 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004120 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 715 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004124 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 300793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x300793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004124: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000003 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004124 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 716 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004124 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 717 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004128 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2ee52423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2ee52423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004128: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r10=80016010, re=800162fc, imm=744 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800162f8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000003 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004128 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 718 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000412c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2ef52223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2ef52223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000412c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r10=80016010, rf=3, imm=740 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800162f4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000003 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000412c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 719 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004130 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e052023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e052023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004130: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r10=80016010, r0=0, imm=736 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800162f0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000003 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004130 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 720 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004134 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 400793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x400793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004134: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004134 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 721 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004138 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004138: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004138 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 722 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000413c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000413c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, rf=4, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000413c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 723 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004140 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 800613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x800613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004140: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: ffffffff (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004140 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 724 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004140 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 725 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004140 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 726 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004140 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 727 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004144 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004144: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004144 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 728 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004148 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6042223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6042223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004148: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r0=0, imm=100 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016360 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004148 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 729 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000414c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000414c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r0=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800162fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000414c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 730 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004150 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004150: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r0=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016300 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004150 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 731 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004154 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004154: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r0=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016304 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004154 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 732 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004158 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004158: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r0=0, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001630c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004158 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 733 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000415c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000415c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r0=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016310 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000415c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 734 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004160 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004160: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r0=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016314 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004160 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 735 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004164 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c40513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c40513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004164: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004164 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 736 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004168 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cb1fc0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcb1fc0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004168: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004168 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 737 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 738 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 739 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 740 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 741 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 742 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f00313 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf00313 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 800162fc (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 743 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 744 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c37e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c37e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e20: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e5c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000002e (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 745 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 746 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 747 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 748 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 749 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 750 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40c306b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40c306b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e5c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000007 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 751 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 269693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x269693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e60: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000001c (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 752 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 297 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x297 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e64: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000001c (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 5 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 753 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e68: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 754 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 755 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c68067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc68067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e6c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r13=80000e80, imm=12 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e8c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 756 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 757 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 758 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 759 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 760 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 761 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 762 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 763 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b703a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb703a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e8c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016358, rb=0, imm=7 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001635f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 764 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70323 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70323 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e90: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016358, rb=0, imm=6 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001635e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 765 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b702a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb702a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e94: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016358, rb=0, imm=5 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001635d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 766 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e98: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016358, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001635c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 767 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b701a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb701a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e9c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016358, rb=0, imm=3 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001635b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 768 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70123 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70123 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016358, rb=0, imm=2 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001635a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 769 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b700a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb700a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016358, rb=0, imm=1 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016359 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 770 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016358, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016358 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 771 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000eac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000eac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000416c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000416c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000eac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 772 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 773 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 774 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 775 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 776 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 777 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000416c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80009b37 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80009b37 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000416c: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000000 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80009000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000416c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 778 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004170 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 892483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x892483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004170: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=80016010, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016018 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80009000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004170 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 779 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004174 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80009ab7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80009ab7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004174: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80009000 (0) + %r22: 80009000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004174 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 780 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004178 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80009a37 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80009a37 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004178: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 00000000 (0) + %r20: 80009000 (0) + %r21: 80009000 (0) + %r22: 80009000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004178 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 781 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000417c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 800099b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x800099b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000417c: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009000 (0) + %r20: 80009000 (0) + %r21: 80009000 (0) + %r22: 80009000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000417c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 782 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004180 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e0b0b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e0b0b13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004180: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009000 (0) + %r20: 80009000 (0) + %r21: 80009000 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004180 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 783 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004180 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 784 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004180 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 785 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004180 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 786 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004184 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 344a8a93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x344a8a93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004184: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009000 (0) + %r20: 80009000 (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004184 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 787 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004188 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3cca0a13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3cca0a13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004188: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009000 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004188 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 788 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000418c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 43498993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x43498993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000418c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00000004 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000418c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 789 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004190 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 107b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x107b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004190: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004190 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 790 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004194 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3642023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3642023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004194: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r16=800092e0, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001631c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004194 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 791 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004198 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3542223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3542223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004198: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r15=80009344, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016320 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004198 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 792 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000419c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3442423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3442423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000419c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r14=800093cc, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016324 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000419c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 793 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3342623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3342623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041a0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r13=80009434, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016328 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 794 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 842e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x842e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041a4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r8=800162fc, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016318 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 795 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 978793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x978793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041a8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 796 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: f4a623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf4a623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041ac: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, rf=10009, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 797 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 800613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x800613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041b0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 798 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 799 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 800 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 604a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x604a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041b8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r0=0, imm=100 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 801 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041bc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r0=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 802 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041c0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r0=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016368 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 803 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 804 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 805 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 806 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041c4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r0=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 807 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041c8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r0=0, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 808 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4aa23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4aa23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041cc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r0=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016378 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 809 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4ac23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4ac23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041d0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r0=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001637c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 80016358 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 810 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000416c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 811 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c41fc0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc41fc0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041d8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 812 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 813 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 814 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 815 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 816 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 817 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f00313 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf00313 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016358 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 818 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 819 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c37e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c37e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e20: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e5c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 820 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 821 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 822 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 823 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 824 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 825 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40c306b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40c306b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e5c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000007 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 826 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 269693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x269693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e60: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000001c (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 827 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 297 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x297 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e64: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000001c (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 5 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 828 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e68: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 829 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 830 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c68067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc68067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e6c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r13=80000e80, imm=12 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e8c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 831 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 832 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 833 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 834 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 835 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 836 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 837 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 838 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b703a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb703a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e8c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800163c0, rb=0, imm=7 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c7 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 839 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70323 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70323 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e90: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800163c0, rb=0, imm=6 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c6 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 840 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b702a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb702a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e94: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800163c0, rb=0, imm=5 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c5 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 841 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e98: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800163c0, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 842 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b701a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb701a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e9c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800163c0, rb=0, imm=3 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 843 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70123 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70123 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800163c0, rb=0, imm=2 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c2 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 844 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b700a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb700a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800163c0, rb=0, imm=1 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 845 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=800163c0, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 846 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000eac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000eac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800041dc, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800041dc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000eac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 847 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 848 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 849 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 850 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 851 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 852 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c92403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc92403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041dc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=80016010, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001601c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800163cc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00010009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 853 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 207b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x207b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041e0: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 854 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 364a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x364a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041e4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r16=800092e0, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016384 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 855 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 354a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x354a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041e8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r15=80009344, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016388 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 856 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 344a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x344a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041ec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r14=800093cc, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001638c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 857 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 334a623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x334a623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r13=80009434, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016390 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 858 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 94ae23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x94ae23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041f4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016364, r9=80016364, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016380 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 859 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1278793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1278793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041f8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 860 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800041fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800041fc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, rf=20012, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800041fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 861 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004200 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6042223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6042223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004200: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r0=0, imm=100 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016430 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004200 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 862 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004200 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 863 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004200 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 864 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004200 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 865 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004204 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004204: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r0=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163cc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004204 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 866 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004208 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004208: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r0=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163d0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004208 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 867 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000420c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000420c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r0=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163d4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000420c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 868 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004210 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004210: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r0=0, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163dc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004210 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 869 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004214 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004214: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r0=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163e0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004214 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 870 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004218 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004218: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r0=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163e4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 800163c0 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004218 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 871 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000421c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c40513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c40513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000421c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000421c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 872 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004220 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 800613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x800613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004220: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004220 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 873 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004224 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004224: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800041dc (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004224 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 874 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004228 +DEBUG ../../../simX/enc.cpp:105: Curr Code: bf1fc0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xbf1fc0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004228: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004228 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 875 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 876 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 877 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 878 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 879 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 880 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f00313 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf00313 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 800163c0 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 881 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 882 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c37e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c37e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e20: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e5c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 883 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 884 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 885 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 886 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 887 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 888 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40c306b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40c306b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e5c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000007 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 6 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 889 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 269693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x269693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e60: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000001c (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 890 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 297 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x297 into: auipc + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e64: auipc +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:814: AUIPC_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 0000001c (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 5 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 891 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e68: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 892 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 5 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 893 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c68067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc68067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e6c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r13=80000e80, imm=12 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000e8c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 894 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 895 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 896 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 897 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 898 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 899 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 900 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 901 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b703a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb703a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e8c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016428, rb=0, imm=7 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001642f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 902 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70323 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70323 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e90: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016428, rb=0, imm=6 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001642e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 903 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b702a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb702a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e94: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016428, rb=0, imm=5 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001642d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 904 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e98: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016428, rb=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001642c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 905 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000e9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b701a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb701a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000e9c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016428, rb=0, imm=3 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001642b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000e9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 906 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70123 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70123 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016428, rb=0, imm=2 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001642a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 907 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b700a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb700a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016428, rb=0, imm=1 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016429 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 908 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ea8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b70023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb70023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ea8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=80016428, rb=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016428 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ea8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 909 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000eac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000eac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000422c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000422c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000422c (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000eac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 910 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 911 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 912 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 913 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 914 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 915 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000422c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000422c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed80, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed9c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800018b0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000422c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 916 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004230 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3642023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3642023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004230: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r16=800092e0, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163ec +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004230 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 917 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004234 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3542223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3542223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004234: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r15=80009344, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163f0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004234 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 918 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004238 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3442423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3442423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004238: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r14=800093cc, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163f4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004238 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 919 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000423c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3342623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3342623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000423c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r13=80009434, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163f8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000423c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 920 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004240 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 842e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x842e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004240: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r8=800163cc, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163e8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004240 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 921 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004240 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 922 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004240 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 923 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004240 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 924 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004244 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004244: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed80, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed98 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00020012 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004244 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 925 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004248 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004248: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004248 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 926 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000424c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f92c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f92c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000424c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r18=80016010, rf=1, imm=56 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016364 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000424c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 927 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004250 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004250: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed80, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed94 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016010 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004250 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 928 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004254 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004254: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed80, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed90 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a04 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 80009434 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004254 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 929 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004254 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 930 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004258 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004258: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed80, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 800093cc (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004258 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 931 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000425c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000425c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed80, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed88 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80009344 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000425c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 932 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004260 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004260: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed80, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed84 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 800092e0 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004260 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 933 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004264 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004264: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed80, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed80 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffed80 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004264 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 934 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004268 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004268: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004268 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 935 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000426c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000426c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800018b0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800018b0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000426c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 936 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 937 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 938 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 939 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 940 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 941 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800018b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f4cff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf4cff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800018b0: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000ffc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 80000e80 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800018b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 942 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 943 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 944 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 945 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 946 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 947 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ffc +DEBUG ../../../simX/enc.cpp:105: Curr Code: cc1683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcc1683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ffc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10009 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000009 (0) + %r14: 80016428 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ffc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 948 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001000 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1069713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1069713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001000: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000009 (0) + %r14: 00090000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 949 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 950 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 951 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 952 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001004 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1269793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1269793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001004: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000009 (0) + %r14: 00090000 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001004 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 953 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001008 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1075713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1075713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001008: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000009 (0) + %r14: 00000009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001008 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 954 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000100c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 207ca63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x207ca63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000100c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000009 (0) + %r14: 00000009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000100c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 955 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 956 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 957 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 958 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 959 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 960 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001010 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001010: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000008 (0) + %r13: 00000009 (0) + %r14: 00002000 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001010 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 961 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001014 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 64c2603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x64c2603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001014: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016364, imm=100 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163c8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000009 (0) + %r14: 00002000 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001014 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 962 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001018 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e6e733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe6e733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001018: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000009 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001018 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 963 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000101c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1071713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1071713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000101c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000009 (0) + %r14: 20090000 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000101c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 964 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001020 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffffe6b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffffe6b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001020: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: ffffe000 (0) + %r14: 20090000 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001020 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 965 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001024 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41075713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41075713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001024: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: ffffe000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001024 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 966 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001024 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 967 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001028 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff68693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff68693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001028: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: ffffdfff (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001028 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 968 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000102c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d676b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd676b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000102c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000102c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 12 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 969 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001030 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ec1623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xec1623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001030: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r24=80016364, re=2009, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001030 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 24 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 970 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001034 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1071713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1071713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001034: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 20090000 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001034 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 971 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001034 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 972 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001038 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6dc2223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6dc2223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001038: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r24=80016364, rd=0, imm=100 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163c8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 20090000 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001038 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 24 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 973 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000103c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1075713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1075713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000103c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000103c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 974 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001040 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 877693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x877693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001040: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000008 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 975 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 976 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 977 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 978 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001044 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e068863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e068863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001044: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000008 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001044 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 979 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 980 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 981 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 982 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 983 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 984 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 985 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001048 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10c2683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10c2683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001048: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001048 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 986 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000104c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e068463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e068463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000104c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80001334 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000104c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 987 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 988 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 989 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 990 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 991 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 992 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 993 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001334 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001334: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016428 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001334 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 994 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001334 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 995 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001334 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 996 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001334 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 997 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001338 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d0513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd0513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001338: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800018b0 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001338 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 998 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000133c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7ac020ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7ac020ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000133c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003ae8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00240000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000133c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 999 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1000 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1001 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1002 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1003 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1004 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ae8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d81a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d81a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ae8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=472 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169e0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ae8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1005 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ae8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1006 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ae8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1007 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ae8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1008 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003aec +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003aec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003aec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1009 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003af0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003af0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed90, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed98 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003af0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1010 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003af4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003af4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed90, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed94 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003af4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1011 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003af8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003af8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed90, r1=80001340, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003af8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1012 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003af8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1013 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003afc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003afc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003afc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1014 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b00: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1015 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1016 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1017 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1018 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b04: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1019 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1020 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1021 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1022 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1023 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1024 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 387a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x387a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b08: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1025 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: e070063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe070063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b0c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000001 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1026 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1027 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1028 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1029 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1030 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1031 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1032 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c41703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc41703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b10: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12009 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 80016010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1033 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1071793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1071793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b14: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 20090000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1034 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 877693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x877693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000008 (0) + %r14: 00002009 (0) + %r15: 20090000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1035 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 107d793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x107d793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000008 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1036 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1037 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4068063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4068063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b20: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000008 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1038 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1039 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1040 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1041 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1042 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1043 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1042683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1042683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b24: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1044 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6068063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6068063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b28: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003b88 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1045 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1046 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1047 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1048 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1049 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1050 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1051 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2807f613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2807f613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b88: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1052 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1053 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1054 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1055 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 20000593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x20000593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b8c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000200 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1056 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8b60ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8b60ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b90: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000200 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 12 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1057 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1058 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1059 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1060 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1061 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1062 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1063 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1064 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b98: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1065 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 27d030ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x27d030ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b9c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007618 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1066 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1067 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1068 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1069 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1070 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1071 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007618 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c5d783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc5d783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007618: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12009 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007618 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1072 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007618 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1073 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007618 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1074 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007618 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1075 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000761c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000761c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000761c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1076 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007620 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007620: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r8=80016364, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007620 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1077 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007624 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007624: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r1=80003ba0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007624 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1078 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007628 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007628: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r9=80016010, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007628 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1079 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007628 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1080 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000762c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000762c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r12=80014a04, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed80 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000762c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1081 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007630 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 27f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x27f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007630: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007630 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1082 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007634 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007634: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1083 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007638 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2078863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2078863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007638: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007668 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007638 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1084 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1085 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1086 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1087 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1088 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1089 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007668 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c10693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc10693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007668: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 00000000 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007668 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1090 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007668 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1091 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007668 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1092 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007668 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1093 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000766c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 810613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x810613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000766c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000766c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1094 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007670 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007670: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007670 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1095 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007674 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ed5ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xed5ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007674: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007548 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007674 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1096 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1097 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1098 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1099 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1100 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1101 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007548 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f9010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf9010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007548: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007548 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1102 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007548 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1103 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007548 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1104 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007548 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1105 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000754c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000754c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r8=80016364, imm=104 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000754c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1106 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007550 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007550: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007550 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1107 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007554 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e59583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe59583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007554: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12009 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007554 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1108 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007554 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1109 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007558 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007558: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r9=80016010, imm=100 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007558 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1110 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000755c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000755c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r12=80014a04, imm=96 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed60 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000755c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1111 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007560 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007560: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r1=80007678, imm=108 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007560 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1112 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007564 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007564: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007564 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1113 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007568 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007568: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1114 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000756c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 405ca63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x405ca63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000756c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed78 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000756c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1115 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1116 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1117 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1118 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1119 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1120 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007570 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 810613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x810613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007570: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007570 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1121 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007574 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 434060ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x434060ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007574: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d9a8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007574 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1122 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1123 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1124 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1125 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1126 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1127 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9a8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00002009 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1128 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1129 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1130 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1131 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9ac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1132 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9b0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffecf0, r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffecf8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1133 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9b4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffecf0, r9=6fffed78, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffecf4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1134 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9b8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1135 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9bc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 80016010 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1136 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 70513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x70513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000001 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1137 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1138 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1139 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1140 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9c4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffecf0, r1=80007578, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffecfc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000001 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1141 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9c8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000001 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1142 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 95df20ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x95df20ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9cc: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000328 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d9d0 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000001 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1143 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1144 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1145 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1146 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1147 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1148 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000328 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 27b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x27b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000328: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d9d0 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000001 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00002000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000328 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1149 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000328 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1150 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000328 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1151 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000328 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1152 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000032c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f5a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf5a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000032c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r11=6fffed08, rf=2000, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d9d0 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000001 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00002000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000032c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1153 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000330 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000330: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d9d0 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00002000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000330 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1154 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000334 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000334: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d9d0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d9d0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d9d0 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: 00002000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000334 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1155 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000334 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1156 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1157 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1158 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1159 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1160 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1161 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9d0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d9d0 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1162 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9d4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d9d0 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1163 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1164 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1165 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1166 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1167 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1168 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1169 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffecf0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffecfc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80007578 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1170 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9dc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffecf0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffecf8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1171 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9e0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffecf0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffecf4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffed78 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffecf0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1172 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9e4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1173 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d9e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d9e8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80007578, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007578 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d9e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1174 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1175 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1176 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1177 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1178 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1179 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007578 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4054463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4054463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007578: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007578 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1180 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1181 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1182 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1183 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1184 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1185 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000757c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000757c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00002000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000757c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1186 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f7b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf7b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007580: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007578 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00002000 (0) + %r15: 0000f000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1187 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1188 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1189 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1190 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007584: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=108 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80007678 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00002000 (0) + %r15: 0000f000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1191 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7f7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7f7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007588: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00002000 (0) + %r15: 00002000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1192 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000758c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffffe737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffffe737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000758c: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00002000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000758c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1193 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007590 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007590: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007590 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1194 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007594 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007594: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=104 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007594 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1195 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007598 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17b793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17b793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007598: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007598 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1196 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007598 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1197 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000759c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f92023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf92023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000759c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r18=6fffed7c, rf=1, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed7c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000759c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1198 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800075a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40000793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40000793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800075a0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1199 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800075a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f4a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf4a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800075a4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=6fffed78, rf=400, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed78 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00000000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1200 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1201 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800075a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1537 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1537 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800075a8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffed78 (0) + %r10: 00001000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1202 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800075ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800075ac: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=100 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00001000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 6fffed7c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1203 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1204 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800075b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800075b0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=96 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed60 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a04 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00001000 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1205 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800075b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80050513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80050513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800075b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000800 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1206 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800075b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800075b8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000800 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1207 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800075bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800075bc: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80007678, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007678 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000800 (0) + %r11: 6fffed08 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800075bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1208 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1209 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1210 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1211 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1212 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1213 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007678 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007678: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed78 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000800 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007678 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1214 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000767c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000767c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000800 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000767c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1215 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007680 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007680: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007678 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007680 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1216 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007680 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1217 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007680 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1218 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007680 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1219 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007684 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b4000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb4000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007684: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007738 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007684 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1220 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1221 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1222 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1223 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1224 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1225 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007738 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007738: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007738 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1226 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007738 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1227 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007738 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1228 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007738 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1229 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000773c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000773c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r13=0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed5c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000773c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1230 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007740 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007740: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r1=80007688, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007740 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1231 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007740 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1232 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007740 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1233 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007740 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1234 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007744 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007744: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r8=80016364, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007744 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1235 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007748 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007748: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r9=80016010, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007748 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1236 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000774c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000774c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r12=800, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed60 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000774c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1237 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007750 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007750: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r14=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed58 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007750 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1238 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007754 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007754: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r15=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed54 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007754 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1239 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007758 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007758: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r16=0, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007758 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1240 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000775c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000775c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r17=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed4c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000775c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1241 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007760 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007760: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r18=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed48 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007760 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1242 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007764 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007764: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r19=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed44 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 00000400 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007764 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 25 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1243 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007768 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b58793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb58793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007768: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: ffffe000 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007768 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1244 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000776c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1600713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1600713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000776c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000776c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1245 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007770 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007770: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007770 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1246 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007774 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6f76463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6f76463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007774: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800077dc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007774 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1247 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1248 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1249 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1250 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1251 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1252 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff87f493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff87f493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077dc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1253 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1254 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1255 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1256 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1807c063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1807c063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077e0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1257 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1258 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1259 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1260 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1261 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1262 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 16b4ee63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x16b4ee63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077e4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1263 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1264 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1265 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1266 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1267 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1268 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7bc000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7bc000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077e8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007fa4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1269 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1270 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1271 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1272 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1273 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1274 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007fa4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007fa4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800077ec, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800077ec +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 0000040b (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1275 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1276 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1277 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1278 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1279 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1280 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1281 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1282 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1283 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1f700793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1f700793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 000001f7 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1284 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4497fa63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4497fa63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077f0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 000001f7 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1285 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1286 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1287 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1288 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1289 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1290 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1291 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 94d793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x94d793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 00000002 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1292 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a078463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a078463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077f8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000016 (0) + %r15: 00000002 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1293 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1294 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1295 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1296 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1297 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1298 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1299 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800077fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 400713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x400713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800077fc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000004 (0) + %r15: 00000002 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800077fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1300 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007800 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3cf76063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3cf76063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007800: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000004 (0) + %r15: 00000002 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007800 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1301 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007800 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1302 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007800 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1303 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007800 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1304 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1305 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1306 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1307 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1308 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1309 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007804 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 64d793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x64d793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007804: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 6fffed08 (0) + %r13: 6fffed7c (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007804 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1310 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007808 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3978613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3978613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007808: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 6fffed7c (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007808 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1311 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000780c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3878513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3878513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000780c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 6fffed7c (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000780c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1312 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007810 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 361693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x361693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007810: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 00000248 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007810 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1313 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007810 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1314 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007814 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c3018913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc3018913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007814: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 00000248 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007814 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1315 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007818 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d906b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd906b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007818: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016680 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007818 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 18 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1316 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000781c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 46a403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x46a403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000781c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=80016680, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016684 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016678 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016678 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016680 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000781c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1317 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007820 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff868693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff868693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007820: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016678 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007820 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1318 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007820 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1319 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007824 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2868663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2868663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007824: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007850 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016678 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007824 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1320 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007824 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1321 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1322 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1323 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1324 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1325 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1326 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1327 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1328 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007850 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1092403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1092403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007850: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=80016438, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016448 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016440 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016440 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007850 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1329 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007850 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1330 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007850 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1331 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007850 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1332 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007854 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 890893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x890893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007854: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016440 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007854 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1333 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007858 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17140863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17140863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007858: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800079c8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016440 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000004 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007858 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1334 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1335 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1336 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1337 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1338 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1339 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1340 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1341 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 492703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x492703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079c8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=80016438, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001643c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016440 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000010 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1342 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1343 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1344 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1345 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40265793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40265793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079cc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016440 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000400 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1346 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079d0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016440 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1347 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f595b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf595b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079d4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016440 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1348 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: eeb77ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xeeb77ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079d8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016440 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1349 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1350 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1351 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1352 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1353 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1354 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1355 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1356 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 892403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x892403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079dc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=80016438, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016440 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016438 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1357 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 442a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x442a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079e0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016438, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001643c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1358 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffcafb13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffcafb13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079e4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1359 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 9b6863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x9b6863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079e8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800079f8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1360 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1361 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1362 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1363 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1364 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1365 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1366 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1367 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1368 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1f01aa83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1f01aa83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079f8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=496 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169f8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: 00000000 (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1369 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800079fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1dc1a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1dc1a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800079fc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=476 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169e4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: 00000012 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800079fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1370 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a00: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1371 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1372 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1373 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1374 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1640a33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1640a33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a04: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 8 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1375 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1548ab3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1548ab3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a08: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000408 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 9 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1376 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 34f70463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x34f70463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a0c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007d54 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000408 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1377 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1378 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1379 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1380 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1381 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1382 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10a8a93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10a8a93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d54: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1383 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1384 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1385 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1386 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ccdff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xccdff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d58: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007a24 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00040000 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1387 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1388 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1389 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1390 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1391 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1392 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a8593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa8593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a24: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000048 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1393 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a28: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800077ec (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1394 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 774010ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x774010ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a2c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800091a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1395 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1396 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1397 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1398 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1399 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1400 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091a0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1401 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1402 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1403 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1404 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091a4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed30, r8=80016438, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1405 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091a8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed30, r9=408, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed34 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1406 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091ac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1407 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1408 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091b0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1409 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091b4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed30, r1=80007a30, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1410 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091b8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1411 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c54f70ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc54f70ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091bc: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000610 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1412 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1413 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1414 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1415 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1416 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1417 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000610 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000610: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000610 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1418 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000610 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1419 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000610 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1420 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000610 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1421 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000614 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c41a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c41a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000614: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=452 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169cc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 80016678 (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000614 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1422 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000618 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41f7d693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41f7d693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000618: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000618 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1423 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000061c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f6c7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf6c7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000061c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000061c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 13 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1424 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000620 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40d787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40d787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000620: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000620 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1425 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000624 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000624: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 10000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000624 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1426 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000624 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1427 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000628 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1cf1a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1cf1a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000628: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, rf=10000418, imm=452 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169cc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 10000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000628 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1428 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000628 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1429 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000062c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000062c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800091c0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800091c0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 10000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000062c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1430 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000062c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1431 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1432 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1433 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1434 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1435 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1436 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1437 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1438 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1439 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1440 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1441 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1442 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1443 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1444 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1445 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1446 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1447 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1448 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091c8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed30, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80007a30 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1449 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091cc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed30, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016438 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1450 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091d0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed30, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 408 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1451 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1452 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091d8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80007a30, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007a30 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1453 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1454 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1455 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1456 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1457 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1458 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1459 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50b93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50b93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a34: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1460 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 28f50663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x28f50663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1461 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1462 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1463 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1464 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1465 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1466 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 29456263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x29456263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a3c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007cc0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1467 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1468 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1469 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1470 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1471 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1472 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007cc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 11240e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x11240e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007cc0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007ddc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1473 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1474 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1475 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1476 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1477 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1478 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1479 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1480 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1481 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ddc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1f818c13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1f818c13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ddc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ddc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1482 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ddc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1483 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ddc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1484 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ddc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1485 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007de0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c2783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc2783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007de0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016a00, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a00 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007de0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1486 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007de4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa87b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa87b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007de4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007de4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 21 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1487 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007de8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fc2023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfc2023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007de8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r24=80016a00, rf=418, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a00 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007de8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 24 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1488 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007de8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 24 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1489 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007dec +DEBUG ../../../simX/enc.cpp:105: Curr Code: c6dff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc6dff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007dec: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007a58 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007dec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1490 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007dec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1491 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1492 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1493 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1494 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1495 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1496 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1497 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1dc1a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1dc1a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a58: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=476 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169e4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1498 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1499 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1500 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1501 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1502 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3ae68663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3ae68663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a60: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007e0c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1503 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1504 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1505 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1506 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1507 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1508 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1509 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d71ae23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d71ae23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007e0c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r17=10000000, imm=476 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169e4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1510 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1511 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1512 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1513 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c61ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc61ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007e10: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007a70 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1514 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1515 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1516 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1517 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1518 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1519 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7bfc93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7bfc93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a70: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1520 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007a74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 300c8263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x300c8263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007a74: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007d78 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007a74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 25 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1521 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1522 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1523 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1524 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1525 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1526 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1527 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 15b85b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x15b85b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 10000418 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 23 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1528 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40b005b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40b005b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: effffbe8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1529 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1459593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1459593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: be800000 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 80016438 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1530 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1531 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1532 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1533 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 145da13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x145da13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d84: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: be800000 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1534 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a0593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa0593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d88: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000000 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1535 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d8c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007a30 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1536 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1537 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 410010ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x410010ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d90: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800091a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1538 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1539 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1540 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1541 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1542 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1543 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1544 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091a0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1545 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091a4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed30, r8=80016438, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1546 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091a8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed30, r9=408, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed34 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1547 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091ac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 80016010 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1548 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1549 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091b0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000be8 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1550 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091b4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed30, r1=80007d94, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000be8 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1551 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091b8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000be8 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1552 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c54f70ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc54f70ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091bc: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000610 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000be8 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000418 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1553 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1554 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1555 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1556 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1557 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1558 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000610 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000610: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 00000be8 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000be8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000610 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1559 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000614 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c41a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c41a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000614: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=452 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169cc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000418 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: ffffffff (0) + %r14: ffffffff (0) + %r15: 00000be8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000614 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1560 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000618 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41f7d693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41f7d693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000618: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000be8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000618 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1561 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000061c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f6c7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf6c7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000061c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000be8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000061c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 13 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1562 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000620 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40d787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40d787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000620: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 00000be8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000620 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1563 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000624 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000624: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 10001000 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000624 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1564 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000624 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1565 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000628 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1cf1a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1cf1a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000628: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, rf=10001000, imm=452 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169cc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 10001000 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000628 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1566 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000628 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1567 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000062c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000062c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800091c0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800091c0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: 10001000 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000062c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1568 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000062c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1569 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1570 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1571 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1572 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1573 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1574 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1575 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1576 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800091c0 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1577 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1578 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1579 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1580 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1581 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1582 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1583 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091c8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed30, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80007d94 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1584 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091cc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed30, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016438 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1585 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091d0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed30, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 408 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed30 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1586 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1587 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800091d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800091d8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80007d94, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007d94 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800091d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1588 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1589 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1590 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1591 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1592 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1593 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1594 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007d98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d0f51ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd0f51ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007d98: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268436504 rsrc1 : 4294967295 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007ab0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 10000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007d98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1595 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1596 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1597 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1598 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1599 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1600 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1601 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ab0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41750533 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41750533 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ab0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00000418 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ab0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1602 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ab0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1603 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ab0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1604 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ab0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1605 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ab4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1450ab3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1450ab3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ab4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000be8 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ab4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 10 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1606 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ab8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c2583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc2583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ab8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016a00, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a00 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 418 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ab8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1607 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007abc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1792423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1792423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007abc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r18=80016438, r17=10000000, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016440 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007abc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1608 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007abc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1609 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ac0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1aea93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1aea93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ac0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00000418 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ac0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1610 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ac0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1611 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ac0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1612 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ac0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1613 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ac4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ba05b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xba05b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ac4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ac4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 20 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1614 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ac8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: bc2023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xbc2023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ac8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r24=80016a00, rb=1000, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a00 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ac8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 24 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1615 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007acc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 15ba223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x15ba223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007acc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r23=10000000, r15=1001, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000004 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007acc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 23 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1616 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ad0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 35240263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x35240263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ad0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007e14 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016438 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ad0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1617 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ad0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1618 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1619 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1620 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1621 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1622 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1623 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007e14: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1624 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cf9ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcf9ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007e18: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007b10 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: ffffffff (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1625 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1626 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1627 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1628 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1629 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1630 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1ec1a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1ec1a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b10: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=492 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169f4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1631 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1632 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1633 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1634 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b14: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1635 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1636 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1637 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1638 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1639 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1640 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1641 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1eb1a623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1eb1a623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b18: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, rb=1000, imm=492 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169f4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1642 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e81a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e81a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b1c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=488 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169f0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1643 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1ab77663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1ab77663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b20: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1644 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1645 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1646 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1647 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1648 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1649 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1650 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1eb1a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1eb1a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b24: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, rb=1000, imm=488 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800169f0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1651 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a40006f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a40006f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b28: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007ccc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001001 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1652 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1653 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1654 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1655 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1656 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1657 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ccc +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffcafa93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffcafa93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ccc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ccc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1658 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007cd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 409a87b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x409a87b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007cd0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000bf8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007cd0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 21 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1659 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007cd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 9ae663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x9ae663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007cd4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000bf8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 21 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1660 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1661 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1662 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1663 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1664 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1665 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1666 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007cd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f00713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf00713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007cd8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 0000000f (0) + %r15: 00000bf8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007cd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1667 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007cdc +DEBUG ../../../simX/enc.cpp:105: Curr Code: e4f748e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe4f748e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007cdc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007b2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 0000000f (0) + %r15: 00000bf8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1668 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1669 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1670 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1671 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1672 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1673 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1674 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 14e713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x14e713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1675 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e42223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe42223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b30: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10000000, re=409, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000004 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 00000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1676 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 9404b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x9404b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b34: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 8 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1677 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 992423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x992423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r18=80016438, r9=10000408, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016440 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf8 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1678 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1679 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17e793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17e793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b3c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 00000418 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1680 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 80016010 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1681 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1682 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1683 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1684 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f4a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf4a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=10000408, rf=bf9, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1000040c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007d94 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 80016010 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1685 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 460000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x460000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b48: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007fa8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007b4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 80016010 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1686 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1687 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1688 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1689 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1690 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1691 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007fa8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007fa8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80007b4c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007b4c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007b4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 80016010 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1692 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1693 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1694 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1695 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1696 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1697 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 840513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x840513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007b4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1698 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007b50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e1dff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe1dff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007b50: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000796c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007b4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007b50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1699 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1700 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1701 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1702 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1703 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1704 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000796c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000796c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80007688 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 10000000 (0) + %r 9: 10000408 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000796c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1705 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000796c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1706 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000796c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1707 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000796c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1708 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007970 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007970: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=40 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000408 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007970 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1709 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007974 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007974: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80016438 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007974 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1710 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007978 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007978: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=32 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed60 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 80016010 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007978 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1711 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000797c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000797c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed5c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000be8 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000797c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1712 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007980 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007980: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed58 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00001000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1713 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1714 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1715 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1716 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007984 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007984: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed54 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007984 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1717 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007988 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007988: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed50 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 10000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007988 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1718 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000798c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000798c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed4c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016a00 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000798c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1719 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007990 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007990: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed48 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007990 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1720 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007994 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412c83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412c83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007994: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed44 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007994 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1721 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007998 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007998: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007998 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1722 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000799c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000799c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80007688, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007688 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00000bf9 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000799c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1723 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1724 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1725 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1726 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1727 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1728 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007688 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c41783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc41783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007688: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12009 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007688 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1729 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000768c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4050863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4050863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000768c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000409 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000768c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1730 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1731 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1732 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1733 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1734 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1735 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007690 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80004737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80004737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007690: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 80004000 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007690 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1736 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007694 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007694: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 800040e0 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007694 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1737 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007698 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e4ae23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e4ae23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007698: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r9=80016010, re=800040e0, imm=60 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001604c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 800040e0 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007698 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1738 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000769c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000769c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed78 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000000 (0) + %r14: 00000400 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000769c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1739 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000769c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1740 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed7c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002009 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1741 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1742 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 807e793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x807e793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1743 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f41623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf41623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076a8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=2089, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1744 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: a42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076ac: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, ra=10000008, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1745 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a42823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa42823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076b0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, ra=10000008, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1746 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1747 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e42a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe42a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076b4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, re=400, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016378 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1748 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4069863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4069863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007708 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00001000 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1749 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1750 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1751 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1752 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1753 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1754 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007708 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e41583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe41583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007708: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12089 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000008 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007708 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1755 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000770c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000770c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007688 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000770c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1756 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007710 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a4060ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a4060ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007710: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000deb4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007710 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1757 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1758 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1759 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1760 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1761 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1762 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000deb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000deb4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000deb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1763 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000deb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1764 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000deb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1765 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000deb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1766 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000deb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000deb8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed60, r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000deb8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1767 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000debc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000debc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed60, r9=80016010, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000debc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1768 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dec0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dec0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dec0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1769 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dec0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1770 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dec0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1771 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dec0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1772 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dec4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dec4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dec4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1773 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dec8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dec8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed60, r1=80007714, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dec8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1774 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000decc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000decc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000decc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1775 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000ded0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c68f20ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc68f20ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000ded0: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000338 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000ded4 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000ded0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1776 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1777 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1778 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1779 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1780 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1781 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000338 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000338: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000ded4 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000338 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1782 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000338 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1783 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000338 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1784 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000338 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1785 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000033c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000033c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000ded4, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000ded4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000ded4 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000033c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1786 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1787 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1788 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1789 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1790 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1791 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000ded4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000ded4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000ded4 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000ded4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1792 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000ded8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000ded8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000ded4 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000ded8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1793 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1794 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1795 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1796 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1797 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1798 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1799 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dedc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dedc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed60, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80007714 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dedc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1800 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dee0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dee0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed60, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dee0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1801 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dee4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dee4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed60, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed60 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dee4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1802 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dee8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dee8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dee8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1803 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000deec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000deec: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80007714, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007714 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000deec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1804 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1805 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1806 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1807 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1808 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1809 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007714 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 51663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x51663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007714: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007720 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00000400 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007714 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1810 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1811 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1812 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1813 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1814 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1815 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007720 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c45703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc45703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007720: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12089 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007720 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1816 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007724 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc77713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc77713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007724: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002088 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007724 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1817 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007728 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 176713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x176713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007728: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: ffffffff (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007728 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1818 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000772c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1071793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1071793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000772c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 20890000 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000772c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1819 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000772c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1820 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007730 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4107d793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4107d793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007730: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007730 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1821 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007730 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1822 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007734 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f89ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf89ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007734: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800076bc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002089 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007734 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1823 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007734 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1824 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1825 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1826 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1827 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1828 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1829 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1830 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 127e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x127e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076bc: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80007714 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1831 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1832 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1833 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1834 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076c0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80003ba0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1835 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1836 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1837 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1838 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f41623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf41623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076c4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=2889, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1839 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076c8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed88 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1840 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076cc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed84 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 00000800 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1841 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076d0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed80 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a04 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1842 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1843 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800076d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800076d8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80003ba0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003ba0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002089 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800076d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1844 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1845 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1846 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1847 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1848 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1849 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ba0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c41703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc41703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ba0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 00000001 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ba0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1850 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ba4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1042683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1042683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ba4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ba4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1851 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ba8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1071793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1071793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ba8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 28890000 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ba8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1852 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003bac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 107d793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x107d793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003bac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000049 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003bac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1853 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003bb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17f613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17f613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003bb0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000001 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003bb0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1854 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003bb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80610e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80610e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003bb4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003b34 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000001 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003bb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 12 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1855 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003bb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 12 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1856 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1857 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1858 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1859 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1860 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1861 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1862 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1863 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1442603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1442603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b34: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016378 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000400 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1864 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, r0=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 00000400 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1865 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b3c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: 00000400 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1866 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40c00633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40c00633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b40: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1867 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1868 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1869 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 0 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1870 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c42c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc42c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rc=fffffc00, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001637c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1871 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8068663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8068663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b48: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003ba0 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1872 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1873 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1874 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1875 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1876 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1877 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1878 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b4c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed90, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed9c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80001340 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1879 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed90, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed98 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1880 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b54: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed90, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed94 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffed90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1881 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1882 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003b5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003b5c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80001340, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80001340 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003b5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1883 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1884 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1885 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1886 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1887 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1888 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001340 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001340: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80001348 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001340 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1889 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001340 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1890 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001340 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1891 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001340 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1892 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1893 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1894 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1895 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1896 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1897 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001348 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cc5703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcc5703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001348: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001348 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1898 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000134c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a00693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa00693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000134c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000134c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1899 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001350 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a77713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a77713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001350: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001350 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1900 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001354 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d0d714e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd0d714e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001354: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 8 rsrc1 : 10 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000105c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001354 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1901 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1902 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1903 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1904 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1905 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1906 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1907 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000105c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10c10793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10c10793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000105c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 00000008 (0) + %r15: 6fffeeac (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000105c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1908 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000105c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1909 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000105c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1910 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000105c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1911 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001060 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80015737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80015737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001060: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 6fffeeac (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001060 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1912 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001064 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ef12223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xef12223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001064: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=6fffeeac, imm=228 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 6fffeeac (0) + %r16: 00000000 (0) + %r17: 80016440 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1913 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001068 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001068: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 6fffeeac (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001068 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1914 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000106c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a6c70793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa6c70793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000106c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014a6c (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000106c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1915 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001070 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80015737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80015737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001070: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014a6c (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001070 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1916 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001074 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f12c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf12c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001074: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=80014a6c, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedb8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014a6c (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001074 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1917 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001078 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90b13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001078: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014a6c (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001078 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1918 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000107c +DEBUG ../../../simX/enc.cpp:105: Curr Code: be870793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xbe870793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000107c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014be8 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000107c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1919 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001080 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f12423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf12423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001080: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=80014be8, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeda8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014be8 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1920 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1921 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1922 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1923 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001084 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b4783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb4783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001084: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r22=80014a04, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a04 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001084 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1924 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001088 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001088: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=236 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001088 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1925 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000108c +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000108c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=232 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000108c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1926 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001090 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001090: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedc0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001090 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1927 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001090 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1928 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001090 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1929 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001094 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001094: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=52 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedd4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001094 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1930 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001098 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001098: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=56 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedd8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001098 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1931 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000109c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000109c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=60 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeddc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000109c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1932 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4012423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4012423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010a0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=72 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffede8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1933 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4012623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4012623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010a4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=76 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedec +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1934 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010a8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1935 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 22078663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x22078663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010ac: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1936 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1937 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1938 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1939 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1940 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1941 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b0413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb0413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a04 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1942 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2500693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2500693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a04 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1943 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a04 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1944 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1945 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1946 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1947 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1948 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1949 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1950 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a04, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a04 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a04 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1951 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a05 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1952 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1953 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1954 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1955 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 101 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a05 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1956 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1957 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1958 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1959 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1960 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1961 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a05 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1962 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1963 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1964 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1965 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1966 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1967 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a05, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a04 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a05 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000072 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1968 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a06 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000072 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1969 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 114 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a06 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000072 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1970 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1971 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1972 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1973 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1974 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1975 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a06 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000072 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1976 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1977 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1978 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1979 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1980 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1981 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a06, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a04 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a06 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1982 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a07 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1983 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 110 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a07 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1984 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1985 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1986 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1987 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1988 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1989 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a07 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1990 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1991 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1992 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1993 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1994 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1995 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a07, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 65206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a07 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1996 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a08 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1997 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 101 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a08 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1998 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 1999 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2000 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2001 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2002 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2003 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a08 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2004 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2005 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2006 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2007 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2008 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2009 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a08, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 65206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a08 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006c (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2010 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a09 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006c (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2011 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 108 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a09 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006c (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2012 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2013 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2014 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2015 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2016 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2017 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a09 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006c (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2018 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2019 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2020 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2021 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2022 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2023 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a09, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 65206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a09 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000020 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2024 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0a (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000020 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2025 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 32 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0a (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000020 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2026 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2027 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2028 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2029 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2030 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2031 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0a (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000020 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2032 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2033 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2034 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2035 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2036 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2037 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a0a, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 65206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0a (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2038 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0b (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2039 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 101 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0b (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2040 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2041 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2042 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2043 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2044 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2045 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0b (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2046 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2047 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2048 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2049 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2050 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2051 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a0b, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 75636578 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0b (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000078 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2052 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0c (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000078 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2053 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 120 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0c (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000078 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2054 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2055 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2056 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2057 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2058 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2059 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0c (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000078 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2060 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2061 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2062 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2063 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2064 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2065 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a0c, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 75636578 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0c (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2066 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0d (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2067 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 101 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0d (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2068 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2069 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2070 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2071 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2072 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2073 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0d (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2074 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2075 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2076 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2077 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2078 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2079 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a0d, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 75636578 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0d (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000063 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2080 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0e (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000063 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2081 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 99 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0e (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000063 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2082 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2083 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2084 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2085 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2086 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2087 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0e (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000063 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2088 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2089 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2090 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2091 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2092 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2093 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a0e, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 75636578 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0e (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000075 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2094 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0f (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000075 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2095 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 117 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0f (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000075 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2096 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2097 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2098 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2099 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2100 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2101 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0f (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000075 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2102 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2103 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2104 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2105 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2106 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2107 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a0f, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 676e6974 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a0f (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000074 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2108 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a10 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000074 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2109 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 116 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a10 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000074 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2110 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2111 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2112 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2113 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2114 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2115 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a10 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000074 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2116 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2117 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2118 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2119 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2120 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2121 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a10, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 676e6974 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a10 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000069 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2122 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a11 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000069 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2123 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 105 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a11 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000069 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2124 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2125 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2126 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2127 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2128 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2129 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a11 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000069 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2130 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2131 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2132 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2133 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2134 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2135 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a11, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 676e6974 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a11 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2136 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a12 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2137 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 110 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a12 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2138 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2139 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2140 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2141 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2142 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2143 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a12 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2144 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2145 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2146 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2147 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2148 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2149 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a12, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 676e6974 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a12 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000067 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2150 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a13 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000067 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2151 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 103 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a13 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000067 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2152 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2153 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2154 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2155 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2156 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2157 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a13 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000067 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2158 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2159 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2160 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2161 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2162 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2163 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a13, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a13 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2164 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a14 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2165 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 46 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a14 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2166 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2167 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2168 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2169 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2170 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2171 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a14 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2172 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2173 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2174 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2175 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2176 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2177 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a14, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a14 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2178 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a15 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2179 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 46 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a15 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2180 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2181 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2182 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2183 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2184 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2185 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a15 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2186 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2187 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2188 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2189 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2190 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2191 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a15, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a15 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2192 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a16 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2193 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 46 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a16 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2194 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2195 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2196 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2197 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2198 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2199 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a16 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2200 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2201 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2202 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2203 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2204 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2205 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a16, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a16 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000000a (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2206 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a17 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000000a (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2207 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 10 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a17 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000000a (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2208 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2209 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2210 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2211 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2212 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2213 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a17 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000000a (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2214 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2215 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2216 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2217 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2218 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2219 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a17, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a18 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a17 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2220 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2221 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2222 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2223 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2224 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2225 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2226 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2227 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 416404b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x416404b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 8 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2228 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21640663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21640663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010cc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2229 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2230 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2231 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2232 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2233 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2234 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ec12683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xec12683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010d0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=236 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000000 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2235 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e812783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe812783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010d4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=232 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee88 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000000 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2236 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 168a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x168a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010d8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r17=6fffeeac, r16=80014a04, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeeac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000000 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 17 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2237 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 9686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x9686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010dc: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000014 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2238 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010e0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000014 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2239 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010e4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r17=6fffeeac, r9=14, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeeb0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000014 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 17 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2240 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ed12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xed12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010e8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rd=14, imm=236 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000014 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2241 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: ef12423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xef12423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010ec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=1, imm=232 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000014 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2242 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 700693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x700693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 6fffeeac (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2243 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 888893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x888893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2244 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2ef6c263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2ef6c263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010f8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2245 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2246 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2247 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2248 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2249 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2250 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010fc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffedac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2251 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001100 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001100: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a18, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a18 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2252 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2253 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2254 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2255 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001104 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 970733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x970733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001104: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001104 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2256 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001108 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001108: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, re=14, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001108 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2257 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000110c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c078663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c078663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000110c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800012d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000110c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2258 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2259 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2260 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2261 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2262 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2263 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2264 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ec12783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xec12783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=236 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2265 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2266 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2267 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2268 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012dc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2269 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2270 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2271 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2272 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2273 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2274 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2275 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3250106f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3250106f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012e0: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80002e04 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: fffffc00 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2276 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2277 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2278 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2279 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2280 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2281 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e410613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe410613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e04: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 00000001 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2282 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2283 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2284 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2285 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e08: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2286 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d0513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd0513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e0c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80001340 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2287 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 314090ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x314090ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e10: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c124 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2288 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2289 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2290 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2291 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2292 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2293 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c124 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 862703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x862703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c124: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r12=6fffee84, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c124 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2294 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c124 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2295 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c124 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2296 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c124 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2297 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c128 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 70463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x70463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c128: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c128 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2298 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2299 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2300 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2301 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2302 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2303 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2304 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c12c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f09ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf09ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c12c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c034 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c12c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2305 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2306 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2307 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2308 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2309 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2310 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c034 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 645a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x645a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c034: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=100 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163c8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c034 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2311 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c034 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2312 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c034 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2313 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c034 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2314 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c038 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c038: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c038 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2315 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c03c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c03c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r16=80014a04, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed80 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c03c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2316 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c040 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c040: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r1=80002e14, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2317 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2318 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2319 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2320 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c044 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c044: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r8=80014a18, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed98 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c044 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2321 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c048 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c048: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r9=14, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed94 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c048 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2322 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c04c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c04c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r12=80014a04, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c04c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2323 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c050 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c050: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r13=0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c050 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2324 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c054 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c054: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r14=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c054 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2325 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c058 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c058: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r15=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2326 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c05c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c05c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r17=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed7c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c05c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2327 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c060 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c060: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r18=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed78 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000014 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c060 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2328 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c064 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1279713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1279713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c064: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2329 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c068 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60b13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c068: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c068 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2330 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c06c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a075863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa075863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c06c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c11c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c06c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2331 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2332 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2333 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2334 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2335 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2336 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c11c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f1010ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf1010ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c11c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000da0c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c11c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2337 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2338 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2339 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2340 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2341 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2342 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 862783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x862783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da0c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r12=6fffee84, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2343 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2344 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2345 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2346 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 32078e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x32078e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da10: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2347 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2348 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2349 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2350 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2351 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2352 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2353 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c5d783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc5d783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da14: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2354 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2355 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da1c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r8=80014a18, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2356 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da20: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r14=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed58 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2357 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da24: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r15=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed54 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2358 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2359 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da28: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r1=8000c120, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2360 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da2c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r9=14, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2361 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da30: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r12=80014a04, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed60 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2362 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da34: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r13=0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed5c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2363 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r16=6fffee84, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2364 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r17=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed4c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2365 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r18=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed48 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2366 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2367 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2368 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2369 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r19=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed44 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 25 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2370 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a12023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a12023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r1a=80016010, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed40 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 26 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2371 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 87f713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x87f713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2372 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60a13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60a13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da50: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2373 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50a93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50a93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da54: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2374 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2375 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8070663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8070663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da5c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2376 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2377 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2378 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2379 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2380 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2381 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 105a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x105a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da60: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 10000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2382 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8070263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8070263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da64: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 10000008 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2383 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2384 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2385 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2386 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2387 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2388 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2389 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 27f713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x27f713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da68: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2390 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a2483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa2483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da6c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r20=6fffee84, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee84 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffeeac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2391 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8070c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8070c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da70: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000db08 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2392 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2393 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2394 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2395 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2396 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2397 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000db08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17f713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17f713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000db08: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2398 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2399 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2400 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2401 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000db0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 24071463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x24071463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000db0c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dd54 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2402 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2403 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2404 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2405 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2406 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2407 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2408 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd54: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2409 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2410 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2411 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2412 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2413 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2414 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd60: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2415 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ec098ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xec098ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd64: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dc38 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 19 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2416 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2417 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2418 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2419 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2420 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2421 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2422 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44a983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44a983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc38: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffeeac, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeeb0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2423 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2424 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2425 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2426 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4ac03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4ac03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc3c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffeeac, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeeac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a04 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2427 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 848493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x848493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2428 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2429 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2430 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2431 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe098ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe098ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc44: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 19 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2432 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2433 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2434 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2435 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2436 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2437 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 00000014 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2438 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a00593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa00593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2439 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc50: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2440 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a7cfa0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa7cfa0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc54: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007ed0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2441 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2442 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2443 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2444 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2445 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2446 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ed0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 357793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x357793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ed0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2447 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2448 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2449 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2450 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ed4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff5f693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff5f693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ed4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2451 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ed8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2078a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2078a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ed8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f0c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2452 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2453 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2454 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2455 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2456 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2457 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f0c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 00000001 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2458 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2459 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2460 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2461 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 300713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x300713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f10: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 00000003 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2462 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f76663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f76663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f14: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f40 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 00000003 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2463 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2464 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2465 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2466 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2467 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2468 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2469 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f40: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 00010000 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2470 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2471 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2472 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2473 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 859893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x859893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 00010000 (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 00000a00 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2474 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff70713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff70713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 00000a00 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2475 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8f8b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8f8b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f4c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 00000a00 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2476 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff5f593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff5f593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f50: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 0000000a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 00000a00 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2477 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8e5b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8e5b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f54: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 00000a0a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 00000a00 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 17 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2478 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 17 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2479 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1059893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1059893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 00000a0a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 0a0a0000 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2480 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8e8b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8e8b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f5c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 00000a0a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: 00000000 (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2481 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2482 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: feff0837 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfeff0837 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f60: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 00000a0a (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: feff0000 (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2483 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2484 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 808085b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x808085b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f64: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808000 (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: feff0000 (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2485 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2486 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: eff80813 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xeff80813 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f68: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808000 (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 16 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2487 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8058593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8058593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f6c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0000000f (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2488 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 300313 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x300313 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f70: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2489 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a04, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a04 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 6e72656b (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2490 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8c733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8c733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 00000014 (0) + %r13: 0000000a (0) + %r14: 64786f61 (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2491 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 64786f61 (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2492 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff74713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff74713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 9b87909e (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2493 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2494 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e67733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe67733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f84: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 03070000 (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2495 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2496 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f88: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2497 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8071ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8071ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2498 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2499 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2500 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2501 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2502 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2503 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2504 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2505 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2506 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc78793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc78793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f90: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a04 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2507 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 450513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x450513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2508 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fcf36ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfcf36ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f98: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2509 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2510 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2511 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2512 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2513 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2514 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a08, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 65206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 65206c65 (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2515 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8c733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8c733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 6f2a666f (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2516 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 6f2a666f (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2517 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff74713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff74713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 90d59990 (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2518 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2519 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e67733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe67733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f84: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 00010100 (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2520 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2521 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f88: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2522 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8071ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8071ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2523 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2524 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2525 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2526 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2527 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2528 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2529 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2530 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2531 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc78793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc78793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f90: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a08 (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2532 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 450513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x450513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2533 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fcf36ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfcf36ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f98: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2534 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2535 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2536 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2537 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2538 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2539 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a0c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 75636578 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 75636578 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2540 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8c733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8c733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 6e29656e (0) + %r13: 0000000a (0) + %r14: 7f696f72 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2541 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 7f696f72 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2542 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff74713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff74713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 8096908d (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2543 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2544 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e67733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe67733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f84: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 00000001 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2545 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2546 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f88: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2547 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8071ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8071ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 0000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2548 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2549 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2550 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2551 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2552 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2553 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2554 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2555 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2556 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc78793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc78793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f90: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a0c (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2557 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 450513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x450513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2558 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fcf36ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfcf36ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f98: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2559 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2560 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2561 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2562 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2563 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2564 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a10, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 676e6974 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 676e6974 (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2565 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8c733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8c733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 7e686e71 (0) + %r13: 0000000a (0) + %r14: 6d64637e (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2566 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 6d64637e (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2567 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff74713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff74713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 929b9c81 (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2568 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2569 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e67733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe67733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f84: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 00030001 (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2570 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2571 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f88: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2572 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8071ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8071ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2573 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2574 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2575 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2576 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2577 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2578 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2579 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2580 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2581 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc78793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc78793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f90: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a10 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2582 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 450513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x450513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2583 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fcf36ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfcf36ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f98: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2584 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2585 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2586 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2587 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2588 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2589 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a14, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 0a2e2e2e (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2590 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8c733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8c733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: 6c63627d (0) + %r13: 0000000a (0) + %r14: 00242424 (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2591 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 00242424 (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2592 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff74713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff74713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: ffdbdbdb (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2593 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2594 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e67733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe67733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f84: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: ff030303 (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2595 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2596 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f88: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 80000000 (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2597 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8071ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8071ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 2147483648 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f24 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 80000000 (0) + %r15: 00000004 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2598 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2599 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2600 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2601 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2602 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2603 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2604 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2605 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2606 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f507b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf507b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f24: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 80000000 (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2607 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0006f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0006f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f28: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f34 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 80000000 (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2608 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2609 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2610 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2611 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2612 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2613 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 54703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x54703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f34: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a14, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2614 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed71ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed71ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 46 rsrc1 : 10 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a14 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2615 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2616 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2617 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2618 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2619 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2620 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2621 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 150513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x150513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a15 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2622 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fea786e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfea786e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f30: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a15 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2623 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2624 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2625 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2626 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2627 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2628 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2629 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 54703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x54703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f34: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a15, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a15 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2630 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed71ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed71ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 46 rsrc1 : 10 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a15 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2631 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2632 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2633 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2634 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2635 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2636 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2637 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 150513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x150513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a16 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2638 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fea786e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfea786e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f30: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a16 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2639 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2640 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2641 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2642 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2643 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2644 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2645 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 54703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x54703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f34: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a16, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a16 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2646 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed71ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed71ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 46 rsrc1 : 10 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a16 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2647 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2648 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2649 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2650 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2651 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2652 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2653 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 150513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x150513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a17 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2654 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fea786e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfea786e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f30: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a17 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000002e (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2655 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2656 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2657 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2658 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2659 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2660 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2661 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 54703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x54703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f34: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a17, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a17 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2662 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed71ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed71ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 10 rsrc1 : 10 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a17 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2663 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2664 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2665 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2666 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2667 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2668 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2669 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f3c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000dc58, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dc58 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a17 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2670 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2671 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2672 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2673 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2674 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2675 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12050463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12050463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc58: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a17 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2676 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2677 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2678 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2679 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2680 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2681 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 150513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x150513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a18 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2682 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41850b33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41850b33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc60: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a18 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a18 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 10 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2683 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b0793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb0793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc64: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a18 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000000 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2684 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98b93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98b93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc68: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a18 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2685 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2686 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 137f463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x137f463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc6c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dc74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a18 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2687 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2688 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2689 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2690 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2691 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2692 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2693 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 00000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2694 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1042783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1042783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc78: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2695 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1442683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1442683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc7c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016378 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2696 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a7f863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa7f863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc80: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dc90 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2697 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2698 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2699 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2700 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2701 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2702 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2703 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2704 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2705 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1adbc863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1adbc863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc90: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000de40 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: ff232323 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 23 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2706 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2707 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2708 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2709 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2710 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2711 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2712 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2713 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2714 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2715 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2716 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 354000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x354000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de48: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e19c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2717 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2718 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2719 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2720 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2721 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2722 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e19c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2a5f663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2a5f663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e19c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1c8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e19c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2723 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e19c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2724 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e19c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2725 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e19c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2726 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2727 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2728 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2729 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2730 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2731 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1c8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 0000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2732 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2733 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2734 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2735 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c7e863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c7e863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1cc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1fc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 0000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2736 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2737 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2738 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2739 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2740 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2741 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2742 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: a5e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa5e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1fc: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 90014a0c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2743 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e200 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 37f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x37f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e200: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e200 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2744 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e200 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2745 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e200 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2746 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e200 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2747 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e204 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a079063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa079063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e204: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e204 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2748 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2749 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2750 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2751 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2752 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2753 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2754 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e208 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff060893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff060893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e208: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 00000004 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e208 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2755 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e20c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff08f893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff08f893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e20c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e20c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2756 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e210 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1088893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1088893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e210: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e210 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2757 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e214 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1150833 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1150833 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e214: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e214 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 10 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2758 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e214 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 10 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2759 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e218 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e218: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 80014a04 (0) + %r15: 00000000 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e218 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2760 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e218 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2761 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e21c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e21c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 00000400 (0) + %r14: 80014a04 (0) + %r15: 10000008 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e21c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2762 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e21c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2763 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e220 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e220: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80014a04, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a04 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 6e72656b (0) + %r14: 80014a04 (0) + %r15: 10000008 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e220 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2764 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e224 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e224: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 6e72656b (0) + %r14: 80014a14 (0) + %r15: 10000008 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e224 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2765 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e228 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1078793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1078793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e228: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 6e72656b (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e228 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2766 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e22c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed7a823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed7a823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e22c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000018, rd=6e72656b, imm=4294967280 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 6e72656b (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e22c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2767 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e230 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff472683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff472683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e230: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80014a14, imm=4294967284 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 65206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 65206c65 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e230 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2768 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e234 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed7aa23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed7aa23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e234: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000018, rd=65206c65, imm=4294967284 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1000000c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 65206c65 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e234 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2769 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e234 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2770 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e238 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff872683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff872683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e238: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80014a14, imm=4294967288 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 75636578 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 75636578 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e238 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2771 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e23c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed7ac23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed7ac23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e23c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000018, rd=75636578, imm=4294967288 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 75636578 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e23c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2772 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e23c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2773 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e240 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc72683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc72683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e240: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80014a14, imm=4294967292 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 676e6974 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e240 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2774 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e240 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2775 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e240 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2776 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e240 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2777 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e244 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed7ae23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed7ae23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e244: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000018, rd=676e6974, imm=4294967292 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000014 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e244 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2778 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e248 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fcf81ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfcf81ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e248: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435480 rsrc1 : 268435480 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e248 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2779 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2780 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2781 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2782 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2783 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2784 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2785 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e24c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c67713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc67713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e24c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a04 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 00000004 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e24c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2786 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e250 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 11585b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x11585b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e250: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 00000004 (0) + %r15: 10000018 (0) + %r16: 10000018 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e250 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2787 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e254 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f67813 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf67813 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e254: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 00000004 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e254 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2788 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e258 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4070e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4070e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e258: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 00000004 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e258 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2789 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2790 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2791 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2792 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2793 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2794 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e25c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e25c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 00000010 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e25c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2795 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e260 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e260: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 10000018 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e260 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2796 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e264 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 300e13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x300e13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e264: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 10000018 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e264 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 28 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2797 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e268 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72303 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72303 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e268: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80014a14, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 80014a14 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 10000018 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e268 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2798 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e26c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 470713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x470713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e26c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 676e6974 (0) + %r14: 80014a18 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 10000018 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e26c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2799 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e270 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40e806b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40e806b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e270: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 7ffeb5ec (0) + %r14: 80014a18 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 10000018 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e270 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 16 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2800 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e274 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e274: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r17=10000018, r6=a2e2e2e, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000018 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 7ffeb5ec (0) + %r14: 80014a18 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 10000018 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e274 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 17 rs2: 6 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2801 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e278 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d586b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd586b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e278: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 00000000 (0) + %r14: 80014a18 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 10000018 (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e278 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 11 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2802 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e278 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 11 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2803 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e27c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 488893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x488893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e27c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 00000000 (0) + %r14: 80014a18 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e27c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2804 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e280 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fede64e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfede64e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e280: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 00000000 (0) + %r14: 80014a18 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e280 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 28 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2805 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e280 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 28 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2806 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e280 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 28 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2807 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e280 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 28 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2808 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2809 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2810 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2811 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2812 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2813 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e284 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc80713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc80713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e284: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e284 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2814 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e288 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc77713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc77713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e288: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e288 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2815 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e28c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 470713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x470713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e28c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000014 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e28c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2816 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e290 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 367613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x367613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e290: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 10000018 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e290 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2817 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e290 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2818 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e294 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e294: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a14 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 1000001c (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e294 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2819 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e294 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2820 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e298 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e585b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe585b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e298: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 1000001c (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e298 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2821 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e29c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f39ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf39ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e29c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1d4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 1000001c (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e29c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2822 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2823 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2824 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2825 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2826 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2827 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff60693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff60693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 00000000 (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 1000001c (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2828 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c060c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc060c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1d8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e2b0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 00000000 (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 1000001c (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 12 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2829 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2830 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2831 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2832 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2833 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2834 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e2b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e2b0: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000de4c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000de4c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 00000000 (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 1000001c (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e2b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2835 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2836 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2837 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2838 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2839 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2840 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 842783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x842783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de4c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 00000000 (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2841 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 10000008 (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 80014a04 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2842 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de54: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 10000008 (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2843 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 417787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x417787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de58: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 10000008 (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2844 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1760633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1760633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de5c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2845 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de60: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=ffffffec, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2846 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de64: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rc=1000001c, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2847 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e49ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe49ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de68: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dcb0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000014 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2848 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2849 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2850 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2851 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2852 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2853 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412b0b33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412b0b33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcb0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a18 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcb0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 22 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2854 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcb4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000001 (0) + %r11: 80014a18 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2855 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 160b0a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x160b0a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcb8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000de2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000001 (0) + %r11: 80014a18 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcb8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2856 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2857 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2858 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2859 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2860 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2861 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000001 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2862 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2863 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2864 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2865 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a8513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa8513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2866 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a24f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa24f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de34: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004058 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2867 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2868 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2869 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2870 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2871 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2872 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004058 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004058: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2873 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2874 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2875 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2876 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000405c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000405c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r8=80016364, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000405c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2877 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004060 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004060: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r1=8000de38, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004060 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2878 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004064 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004064: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2879 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2880 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004068 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004068: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: ffffffec (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004068 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2881 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2882 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2883 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2884 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2885 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2886 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000406c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3852783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3852783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000406c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00000001 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000406c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2887 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004070 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2078063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2078063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004070: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00000001 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004070 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2888 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2889 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2890 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2891 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2892 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2893 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2894 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004074 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004074: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004074 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2895 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004078 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2079663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2079663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004078: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 10377 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800040a4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004078 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2896 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2897 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2898 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2899 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2900 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2901 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2902 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2903 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2904 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2905 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2906 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040a8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2907 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040ac: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000de38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2908 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040b0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2909 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d49ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd49ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040b4: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003dfc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2910 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2911 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2912 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2913 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2914 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2915 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003dfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003dfc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2916 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2917 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2918 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2919 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e00: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2920 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2921 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2922 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2923 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e04: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r8=80016364, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2924 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e08: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r13=14, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed2c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2925 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e0c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r1=8000de38, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2926 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2927 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e10: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r9=6fffeeb4, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed34 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2928 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e14: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r12=14, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed30 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: ffffffff (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2929 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 87f693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x87f693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2930 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2931 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e20: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2932 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10069a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10069a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e24: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 8 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f38 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 00000014 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2933 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2934 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2935 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2936 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2937 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2938 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 105a903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x105a903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f38: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2939 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2940 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2941 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2942 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fc090ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfc090ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f3c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2943 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2944 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2945 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2946 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2947 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2948 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2949 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5a483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5a483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f40: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1000001c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 1000001c (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000004 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2950 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2951 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2952 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2953 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1079713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1079713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 1000001c (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 28890000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2954 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1075713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1075713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 1000001c (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2955 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 377713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x377713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 1000001c (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2956 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 125a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x125a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f50: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r11=80016364, r12=10000008, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 1000001c (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2957 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2958 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412484b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412484b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f54: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2959 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2960 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2961 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 71463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x71463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f5c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f64 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2962 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2963 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2964 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2965 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2966 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2967 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f64: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2968 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 904863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x904863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f68: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f78 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2969 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2970 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2971 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2972 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2973 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2974 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2442783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2442783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f78: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016388 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80009344 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2975 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c42583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c42583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f7c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016380 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2976 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 1000001c (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2977 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2978 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2979 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2980 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f84: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2981 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f88: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2982 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f8c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80009344, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80009344 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2983 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2984 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2985 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2986 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2987 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2988 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009344 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009344: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009344 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2989 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009344 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2990 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009344 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2991 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009344 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2992 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009348 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009348: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009348 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2993 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000934c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000934c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r8=80016364, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed18 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000934c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2994 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009350 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009350: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r9=14, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009350 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2995 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009354 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009354: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r12=10000008, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed10 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009354 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2996 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009354 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2997 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009358 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009358: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r13=80016010, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009358 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2998 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000935c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000935c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r1=80003f90, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000935c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 2999 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009360 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1007f713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1007f713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009360: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009360 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3000 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009364 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009364: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009364 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3001 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009368 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009368: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009368 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3002 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000936c +DEBUG ../../../simX/enc.cpp:105: Curr Code: e59583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe59583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000936c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000936c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3003 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009370 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009370: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009370 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3004 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009374 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009374: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009374 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3005 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009378 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2071e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2071e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009378: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009378 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3006 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3007 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3008 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3009 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3010 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3011 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000937c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fffff737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfffff737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000937c: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: fffff000 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000937c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3012 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009380 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff70713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff70713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009380: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009380 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3013 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009380 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3014 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009380 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3015 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009380 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3016 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009384 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7f7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7f7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009384: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009384 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3017 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009388 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f41623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf41623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009388: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=2889, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009388 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3018 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000938c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000938c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed18 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000938c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3019 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000938c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3020 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009390 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009390: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80003f90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009390 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3021 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009390 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3022 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009394 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009394: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009394 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3023 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009398 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009398: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009398 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3024 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000939c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000939c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000939c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3025 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3026 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3027 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093a8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3028 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093ac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3029 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a80406f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa80406f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093b0: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d458 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3030 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3031 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3032 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3033 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3034 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3035 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d458 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d458: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d458 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3036 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d458 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3037 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d458 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3038 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d458 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3039 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d45c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d45c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d45c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3040 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d460 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d460: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed10, r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed18 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d460 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3041 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d464 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d464: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed10, r9=14, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d464 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3042 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d468 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d468: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d468 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3043 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d46c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d46c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 10000008 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d46c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3044 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d470 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d470: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d470 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3045 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d474 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 70513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x70513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d474: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d474 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3046 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d478 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d478: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed10, r1=80003f90, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d478 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3047 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d47c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d47c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d47c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3048 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d480 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 858f30ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x858f30ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d480: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800004d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d480 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3049 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d480 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3050 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d480 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3051 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d480 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3052 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3053 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3054 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3055 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3056 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3057 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004d8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3058 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3059 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3060 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3061 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004dc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r8=80016010, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed08 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3062 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 710007b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x710007b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004e0: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 71000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3063 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004e4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r1=8000d484, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 71000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3064 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3065 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000001 (0) + %r15: 71000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3066 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 400713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x400713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 0a2e2e2e (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3067 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 500313 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x500313 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 00000004 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3068 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1078813 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1078813 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3069 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004f8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, re=4, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3070 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 678223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x678223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004fc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, r6=5, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000004 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 6 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3071 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000500 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 782a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x782a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000500: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, r0=0, imm=5 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000005 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3072 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3073 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3074 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3075 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000504 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 878823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x878823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000504: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, r8=14, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 1000001c (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000504 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3076 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000508 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 865893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x865893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000508: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000508 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3077 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000050c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1845693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1845693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000050c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000050c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3078 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000510 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1065613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1065613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000510: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000510 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3079 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000514 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 11800a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x11800a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000514: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r16=71000010, r11=0, imm=1 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000011 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000514 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3080 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000518 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c80123 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc80123 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000518: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r16=71000010, rc=0, imm=2 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000012 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000518 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3081 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000051c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d801a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd801a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000051c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r16=71000010, rd=0, imm=3 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000013 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000051c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3082 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000520 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 79323 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x79323 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000520: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, r0=0, imm=6 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000006 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000520 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3083 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000524 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000524: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, re=4, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000524 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3084 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000528 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a7a623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa7a623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000528: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, ra=1, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 7100000c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000528 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3085 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000052c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a805263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa805263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000052c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000052c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3086 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3087 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3088 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3089 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3090 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3091 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000530 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1478693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1478693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000530: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000530 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3092 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000534 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1878793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1878793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000534: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 71000018 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000534 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3093 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000538 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f5b7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf5b7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000538: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3094 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000053c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b83533 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb83533 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000053c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000053c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 16 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3095 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000540 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff40613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff40613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000540: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000013 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000540 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3096 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000540 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3097 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000540 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3098 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000540 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3099 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000544 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17c713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17c713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000544: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000013 (0) + %r13: 71000014 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000544 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3100 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000548 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 963613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x963613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000548: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000548 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3101 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000054c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 154793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x154793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000054c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000054c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3102 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000550 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f767b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf767b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000550: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000550 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3103 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000554 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 164713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x164713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000554: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000554 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3104 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000558 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f777b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf777b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000558: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000558 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3105 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000558 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3106 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000055c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8078863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8078863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000055c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000055c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3107 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3108 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3109 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3110 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3111 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3112 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3113 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3114 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000560 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b6e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb6e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000560: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 7100001c (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000560 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 13 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3115 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000564 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 37f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x37f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000564: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000564 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3116 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000568 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8079263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8079263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000568: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3117 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3118 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3119 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3120 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3121 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3122 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3123 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3124 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000056c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc47513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc47513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000056c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000056c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3125 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000570 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b50533 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb50533 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000570: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000570 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3126 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000574 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000574: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 10000008 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000574 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3127 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000578 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40b68833 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40b68833 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000578: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 10000008 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000578 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 13 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3128 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000578 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 13 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3129 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000057c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000057c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=10000008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 10000008 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000057c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3130 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000580: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 10000008 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3131 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3132 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3133 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3134 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000584: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3135 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000588: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=71000014, rc=6e72656b, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000014 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3136 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000058c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fef518e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfef518e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000058c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435484 rsrc1 : 268435468 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000057c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000058c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3137 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3138 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3139 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3140 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3141 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3142 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000057c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000057c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=1000000c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1000000c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 65206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 65206c65 (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000057c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3143 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000580: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 65206c65 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3144 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000584: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 65206c65 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3145 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000588: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=71000018, rc=65206c65, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000018 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 65206c65 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3146 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000058c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fef518e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfef518e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000058c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435484 rsrc1 : 268435472 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000057c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 65206c65 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000058c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3147 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3148 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3149 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3150 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3151 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3152 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000057c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000057c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=10000010, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000010 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 75636578 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 75636578 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000057c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3153 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000580: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 75636578 (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3154 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000584: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 75636578 (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3155 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000588: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=7100001c, rc=75636578, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 7100001c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 75636578 (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3156 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000058c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fef518e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfef518e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000058c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435484 rsrc1 : 268435476 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000057c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 75636578 (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000058c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3157 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3158 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3159 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3160 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3161 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3162 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000057c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000057c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=10000014, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000014 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 676e6974 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 676e6974 (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000057c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3163 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000580: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 676e6974 (0) + %r13: 71000014 (0) + %r14: 71000020 (0) + %r15: 10000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3164 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000584: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 676e6974 (0) + %r13: 71000014 (0) + %r14: 71000020 (0) + %r15: 10000018 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3165 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000588: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=71000020, rc=676e6974, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000020 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 676e6974 (0) + %r13: 71000014 (0) + %r14: 71000020 (0) + %r15: 10000018 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3166 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000058c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fef518e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfef518e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000058c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435484 rsrc1 : 268435480 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000057c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 676e6974 (0) + %r13: 71000014 (0) + %r14: 71000020 (0) + %r15: 10000018 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000058c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3167 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3168 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3169 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3170 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3171 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3172 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000057c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000057c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=10000018, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000018 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a2e2e2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000014 (0) + %r14: 71000020 (0) + %r15: 10000018 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000057c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3173 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000580: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000014 (0) + %r14: 71000024 (0) + %r15: 10000018 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3174 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000584: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000014 (0) + %r14: 71000024 (0) + %r15: 1000001c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3175 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000588: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=71000024, rc=a2e2e2e, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000024 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000014 (0) + %r14: 71000024 (0) + %r15: 1000001c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3176 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000058c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fef518e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfef518e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000058c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435484 rsrc1 : 268435484 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000014 (0) + %r14: 71000024 (0) + %r15: 1000001c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000058c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3177 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3178 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3179 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3180 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3181 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3182 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000590 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc47793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc47793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000590: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000014 (0) + %r14: 71000024 (0) + %r15: 00000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000590 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3183 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000594 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000594: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000594 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3184 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000598 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f40c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f40c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000598: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800005d0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000598 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3185 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3186 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3187 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3188 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3189 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3190 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3191 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c81a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c81a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005d0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=456 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169d0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 70000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3192 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3193 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3194 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3195 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005d4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=70000000, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 70000000 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800005d8 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3196 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3197 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3198 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3199 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3200 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3201 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3202 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x70000000 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x70000000: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +kernel executing... +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800005d8, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800005d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800005d8 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 70000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3203 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 70000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3204 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 70000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3205 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 70000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3206 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3207 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3208 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3209 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3210 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3211 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d484 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 1000001c (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3212 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005dc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000014 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3213 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005e0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3214 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005e4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3215 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005e8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d484, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d484 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3216 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3217 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3218 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3219 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3220 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3221 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d484 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d484: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d484 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3222 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d488 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d488: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d488 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3223 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3224 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3225 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3226 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3227 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3228 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3229 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d48c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d48c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed10, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80003f90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d48c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3230 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d490 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d490: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed10, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed18 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d490 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3231 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d494 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d494: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed10, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d494 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3232 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d498 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d498: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d498 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3233 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d49c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d49c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80003f90, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f90 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d49c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3234 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3235 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3236 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3237 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3238 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3239 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40a484b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40a484b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f90: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3240 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fca04ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfca04ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f94: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f70 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3241 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3242 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3243 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3244 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3245 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3246 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a90933 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa90933 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f70: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 1000001c (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 18 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3247 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa9052e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa9052e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f74: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 1000001c (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3248 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3249 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3250 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3251 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3252 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3253 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 1000001c (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3254 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f1c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000de38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 1000001c (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3255 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f20: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 1000001c (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3256 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f24: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffeeb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 1000001c (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3257 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f28: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed30 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000014 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3258 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f2c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3259 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3260 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f34: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000de38, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000de38 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3261 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3262 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3263 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3264 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3265 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3266 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e80502e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe80502e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dcbc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0a2e2e2e (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3267 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3268 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3269 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3270 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3271 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3272 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3273 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3274 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3275 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8a2603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8a2603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcbc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r20=6fffee84, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a04 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3276 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3277 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3278 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3279 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12c0c33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12c0c33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcc0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000014 (0) + %r19: 00000014 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 24 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3280 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 24 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3281 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 24 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3282 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 24 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3283 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412989b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412989b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcc4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000014 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 19 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3284 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41260933 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41260933 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcc8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 12 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3285 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dccc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12a2423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12a2423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dccc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r20=6fffee84, r12=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dccc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 20 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3286 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8091a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8091a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcd0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcd0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3287 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3288 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3289 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3290 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3291 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3292 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3293 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcd4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3294 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcd8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000c120 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3295 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcdc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcdc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=40 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a18 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3296 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dce0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dce0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dce0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3297 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dce4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dce4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=32 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed60 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a04 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dce4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3298 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dce8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dce8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed5c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dce8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3299 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcec: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed58 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3300 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcf0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcf0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed54 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcf0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3301 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcf4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcf4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed50 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffee84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000014 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcf4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3302 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcf8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcf8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed4c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80014a18 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcf8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3303 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcfc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed48 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3304 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412c83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412c83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd00: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed44 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3305 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3306 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3307 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3308 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12d03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12d03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd04: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed40 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 26 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3309 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd08: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3310 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd0c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000c120, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c120 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3311 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3312 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3313 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3314 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3315 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3316 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c120 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa5ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa5ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c120: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c0c4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c120 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3317 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3318 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3319 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3320 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3321 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3322 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0c4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed9c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80002e14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3323 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3324 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3325 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3326 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0c8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=40 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed98 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a18 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3327 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: b2423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb2423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0cc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r22=6fffee84, r0=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3328 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b2223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb2223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0d0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r22=6fffee84, r0=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3329 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0d4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed94 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3330 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=32 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed90 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a04 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3331 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0dc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3332 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0e0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed88 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3333 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed84 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3334 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0e8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed80 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a04 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3335 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0ec: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed7c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3336 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0f0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed78 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3337 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3338 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0f8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80002e14, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80002e14 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3339 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3340 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3341 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3342 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3343 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3344 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cd0fe06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcd0fe06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e14: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800012e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3345 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3346 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3347 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3348 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3349 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3350 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3351 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3352 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3353 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cc5783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcc5783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3354 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 407f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x407f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3355 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012ec: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800012f4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3356 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3357 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3358 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3359 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3360 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3361 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3362 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3363 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1ec12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1ec12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012f4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=492 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000f74 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a18 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3364 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012f8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=488 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef88 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000014 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3365 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012fc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffedac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000014 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3366 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001300 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001300: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=484 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef84 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a04 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001300 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3367 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001300 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3368 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001300 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3369 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001300 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3370 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001304 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001304: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=480 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef80 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001304 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3371 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001308 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1dc12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1dc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001308: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=476 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef7c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001308 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3372 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000130c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000130c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=472 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef78 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000130c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3373 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001310 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001310: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=468 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef74 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a04 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001310 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3374 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001314 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001314: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=464 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef70 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001314 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3375 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001318 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1cc12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1cc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001318: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=460 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef6c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001318 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3376 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000131c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c812c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c812c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000131c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=456 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef68 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000131c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3377 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001320 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c412c83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c412c83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001320: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=452 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef64 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001320 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3378 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001324 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c012d03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c012d03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001324: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=448 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef60 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001324 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 26 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3379 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001328 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1bc12d83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1bc12d83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001328: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=444 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef5c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001328 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 27 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3380 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000132c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1f010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1f010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000132c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000132c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3381 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001330 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001330: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000f74, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000f74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001330 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3382 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3383 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3384 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3385 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3386 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3387 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000064 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3388 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3389 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3390 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3391 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f78: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3392 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f7c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000064, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000064 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3393 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3394 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3395 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3396 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3397 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3398 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000064 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d41a883 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d41a883 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000064: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=468 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169dc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3399 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3400 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3401 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3402 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000068 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d01a803 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d01a803 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000068: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=464 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169d8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 71000024 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000068 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3403 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000006c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1cc1a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1cc1a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000006c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=460 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169d4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 00000014 (0) + %r13: 71000028 (0) + %r14: 10020000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000006c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3404 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000070 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80001637 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80001637 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000070: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 80001000 (0) + %r13: 71000028 (0) + %r14: 10020000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000070 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3405 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000074 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40000793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40000793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000074: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 80001000 (0) + %r13: 71000028 (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000074 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3406 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000078 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c10693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc10693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000078: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 80001000 (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000078 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3407 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000007c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c2c60613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc2c60613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000007c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 10000008 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000007c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3408 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000080 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 400593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x400593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000080: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000014 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3409 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3410 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3411 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3412 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000084 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 400513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x400513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000084: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000084 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3413 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000088 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000088: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefd0, r11=10000000, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000088 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3414 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000008c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000008c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefd0, r10=10010000, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000008c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3415 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000090 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e12a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe12a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000090: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefd0, re=10020000, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000090 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3416 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000094 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f12c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf12c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000094: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefd0, rf=400, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000094 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3417 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000098 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f12e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf12e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000098: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefd0, rf=400, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000064 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000098 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3418 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000009c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 245000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x245000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000009c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000ae0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000009c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3419 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3420 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3421 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3422 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3423 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3424 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ae0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ae0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000400 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ae0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3425 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ae0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3426 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ae0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3427 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ae0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3428 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ae4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ae4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000004 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ae4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3429 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ae8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 800015b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x800015b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ae8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 80001000 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ae8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3430 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000aec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000aec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 80001000 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000aec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3431 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000af0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000af0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 80001000 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000af0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3432 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000af4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000af4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 80001000 (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000af4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3433 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000af8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 97c58593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x97c58593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000af8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000af8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3434 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000afc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000afc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r1=800000a0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefcc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000afc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3435 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 22c1a623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x22c1a623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b00: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, rc=80000c2c, imm=556 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3436 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3437 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3438 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3439 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 22d1a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x22d1a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b04: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, rd=6fffefdc, imm=548 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3440 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 24f1a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x24f1a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b08: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, rf=4, imm=580 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a4c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3441 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c6dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc6dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b0c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000778 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000b10 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3442 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3443 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3444 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3445 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3446 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3447 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000778 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5106b +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5106b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000778: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:961: WSPAWN +DEBUG ../../../simX/instruction.cpp:969: Spawning 4 new warps at PC: 8000097c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000b10 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000778 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 1 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3448 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000778 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 1 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3449 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000778 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 1 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3450 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000778 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 1 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3451 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000097c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2441a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2441a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000097c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=580 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a4c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 6bfff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000001 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000097c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3452 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000097c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3453 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000097c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3454 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000097c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3455 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000097c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2441a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2441a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000097c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=580 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a4c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 67fff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000002 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000097c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3456 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000097c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2441a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2441a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000097c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=580 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a4c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 63fff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000003 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000097c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3457 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000077c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000077c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b10, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000b10 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000b10 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000077c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3458 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000980 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000980: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 6bffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000001 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000980 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3459 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000980 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3460 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000980 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3461 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000980 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3462 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000980 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000980: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 67ffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000002 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000980 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3463 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000980 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000980: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 63ffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000003 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000980 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3464 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2441a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2441a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b10: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=580 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a4c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000b10 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3465 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000984 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000984: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffeff0, r1=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffeffc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 6bffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000001 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000984 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3466 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000984 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000984: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffeff0, r1=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffeffc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 67ffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000002 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000984 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3467 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000984 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000984: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffeff0, r1=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffeffc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 00000000 (0) + %r 2: 63ffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000003 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000984 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3468 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c6dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc6dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b14: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000b18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: 6fffefdc (0) + %r14: 10020000 (0) + %r15: 00000004 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3469 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000988 +DEBUG ../../../simX/enc.cpp:105: Curr Code: df9ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xdf9ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000988: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000098c (0) + %r 2: 6bffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000001 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000988 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3470 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000988 +DEBUG ../../../simX/enc.cpp:105: Curr Code: df9ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xdf9ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000988: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000098c (0) + %r 2: 67ffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000002 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000988 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3471 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000988 +DEBUG ../../../simX/enc.cpp:105: Curr Code: df9ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xdf9ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000988: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000098c (0) + %r 2: 63ffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 00000000 (0) + %r 6: 00000000 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000004 (0) + %r11: 00000000 (0) + %r12: 00000000 (0) + %r13: 00000003 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000000 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000000 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000988 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3472 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3473 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3474 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b18 00000000 00000000 00000000 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000004 00000000 00000000 00000000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3475 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3476 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3477 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3478 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3479 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3480 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3481 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3482 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3483 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000784 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000784: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b18, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000b18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b18 00000000 00000000 00000000 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000004 00000000 00000000 00000000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000784 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3484 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000784 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000784: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000098c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000098c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000784 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3485 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000784 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000784: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000098c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000098c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000784 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3486 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000784 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000784: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000098c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000098c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000004 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000784 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3487 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3488 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3489 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2241a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2241a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b18: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b18 00000000 00000000 00000000 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000004 00000000 00000000 00000000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3490 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000098c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2241a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2241a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000098c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000098c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3491 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000098c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2241a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2241a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000098c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000098c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3492 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000098c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2241a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2241a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000098c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=548 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffefdc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000000 00000000 00000000 00000000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000098c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3493 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000098c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3494 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000098c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3495 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 22c1a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x22c1a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b1c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b18 00000000 00000000 00000000 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3496 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3497 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3498 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000990 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 22c1a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x22c1a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000990: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3499 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3500 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3501 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000990 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 22c1a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x22c1a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000990: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3502 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3503 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3504 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000990 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 22c1a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x22c1a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000990: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=556 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016a34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000c2c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000098c 00000000 00000000 00000000 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3505 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3506 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000990 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3507 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b20: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3508 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3509 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3510 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000994 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000994: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000994 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3511 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000994 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3512 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000994 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3513 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000994 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000994: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000994 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3514 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000994 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000994: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80000c2c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000994 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3515 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3516 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3517 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3518 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3519 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3520 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3521 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3522 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3523 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c2c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3524 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c2c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3525 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c2c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3526 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c30: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r1=80000b24, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffebf4, r1=80000b24, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffec00 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffe7f8, r1=80000b24, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffe804 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffe3fc, r1=80000b24, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffe408 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3527 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c30: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffefe0, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffefec +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffebf4, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffec00 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffe7f8, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffe804 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffe3fc, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffe408 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c30 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3528 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c30: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffefe0, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffefec +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffebf4, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffec00 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffe7f8, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffe804 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffe3fc, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffe408 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c30 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3529 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c30: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffefe0, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffefec +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffebf4, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffec00 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffe7f8, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffe804 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffe3fc, r1=80000998, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffe408 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c30 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3530 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c34: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffebf4, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffebfc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffe7f8, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffe800 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffe3fc, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffe404 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3531 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c34: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffefe0, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffefe8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffebf4, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffebfc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffe7f8, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffe800 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffe3fc, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffe404 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c34 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3532 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c34: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffefe0, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffefe8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffebf4, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffebfc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffe7f8, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffe800 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffe3fc, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffe404 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c34 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3533 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c34: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffefe0, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffefe8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffebf4, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffebfc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffe7f8, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffe800 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffe3fc, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffe404 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c34 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3534 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffebf4, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffebf8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffe7f8, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffe7fc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffe3fc, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffe400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3535 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffefe0, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffefe4 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffebf4, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffebf8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffe7f8, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffe7fc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffe3fc, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffe400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c38 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3536 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffefe0, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffefe4 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffebf4, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffebf8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffe7f8, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffe7fc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffe3fc, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffe400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c38 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3537 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffefe0, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffefe4 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffebf4, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffebf8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffe7f8, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffe7fc +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffe3fc, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffe400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c38 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3538 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb0 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffebf4, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffebf4 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffe7f8, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffe7f8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffe3fc, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffe3fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3539 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffefe0, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffefe0 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffebf4, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffebf4 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffe7f8, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffe7f8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6bffe3fc, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6bffe3fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c3c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3540 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffefe0, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffefe0 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffebf4, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffebf4 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffe7f8, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffe7f8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=67ffe3fc, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 67ffe3fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c3c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3541 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffefe0, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffefe0 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffebf4, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffebf4 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffe7f8, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffe7f8 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=63ffe3fc, r12=0, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 63ffe3fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c3c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3542 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3543 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3544 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3545 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3546 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c40 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3547 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c40 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3548 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c40 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3549 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c44: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3550 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c44: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c44 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3551 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c44: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c44 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3552 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c44: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c44 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3553 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3554 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3555 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2102573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2102573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a0: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3556 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2102573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2102573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a0: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3557 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2102573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2102573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a0: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000002 00000002 00000002 00000002 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3558 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2102573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2102573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a0: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000003 00000003 00000003 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3559 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c48 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3560 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c48 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3561 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c48 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000002 00000002 00000002 00000002 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3562 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c48, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c48 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000003 00000003 00000003 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3563 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3564 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3565 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3566 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c48 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3567 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000002 00000002 00000002 00000002 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c48 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3568 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c48 80000c48 80000c48 80000c48 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000003 00000003 00000003 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c48 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3569 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c4c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3570 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c4c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c4c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3571 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c4c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000002 00000002 00000002 00000002 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c4c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3572 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b5dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb5dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c4c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000003 00000003 00000003 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c4c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3573 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3574 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3575 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2002573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2002573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a8: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 0 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 1 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 2 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3576 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2002573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2002573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a8: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 0 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 1 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 2 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3577 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2002573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2002573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a8: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 0 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 1 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 2 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3578 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2002573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2002573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a8: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 0 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 1 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 2 +DEBUG ../../../simX/instruction.cpp:850: CSR Reading tid 20 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3579 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007ac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c50 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3580 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007ac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c50 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007ac +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3581 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007ac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c50 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007ac +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3582 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007ac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c50, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c50 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 80000c2c 80000c2c 80000c2c 80000c2c (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007ac +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3583 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3584 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3585 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 104a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x104a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3586 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 104a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x104a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3587 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 104a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x104a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3588 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 104a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x104a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3589 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3590 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3591 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3592 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3593 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c50 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3594 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f47863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf47863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c54: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3595 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3596 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3597 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f47863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf47863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c54: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c54 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3598 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c54 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3599 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c54 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3600 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f47863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf47863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c54: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c54 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3601 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f47863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf47863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c54: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c54 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3602 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3603 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3604 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3605 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3606 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c58: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3607 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c58: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c58 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3608 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c58: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c58 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3609 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c58: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c58 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3610 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c58 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3611 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c58 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3612 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3613 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3614 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3615 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c5c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3616 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c5c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3617 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c5c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3618 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c5c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3619 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c5c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3620 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f56263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f56263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c60: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c84 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3621 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f56263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f56263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c60: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c84 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c60 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3622 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f56263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f56263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c60: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c84 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c60 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3623 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f56263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f56263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c60: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c84 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000000 00000001 00000002 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c60 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3624 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3625 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3626 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3627 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3628 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c84: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3629 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3630 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3631 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3632 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c84: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c84 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3633 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c84: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c84 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3634 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c84: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c50 80000c50 80000c50 80000c50 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c84 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3635 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b09ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb09ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c88: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000790 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3636 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b09ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb09ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c88: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000790 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c88 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3637 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b09ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb09ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c88: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000790 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c88 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3638 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b09ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb09ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c88: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000790 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c88 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3639 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3640 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3641 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000790 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5206b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5206b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000790: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1009: Unanimous pred: 10 val: 1 + +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000790 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3642 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000790 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5206b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5206b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000790: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1009: Unanimous pred: 10 val: 1 + +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000790 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3643 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000790 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5206b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5206b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000790: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1009: Unanimous pred: 10 val: 1 + +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000790 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3644 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000790 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5206b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5206b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000790: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1009: Unanimous pred: 10 val: 1 + +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:1003: SPLIT +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000790 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3645 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3646 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3647 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000794 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000794: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c8c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000794 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3648 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000794 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000794: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c8c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000794 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3649 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000794 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000794: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c8c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000794 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3650 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000794 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000794: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000c8c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000c8c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000794 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3651 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3652 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3653 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c8c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10020000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3654 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c8c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c8c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3655 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c8c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c8c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3656 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c4a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc4a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c8c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 00000000 00000000 00000000 00000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c8c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3657 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c8c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3658 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c8c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3659 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c90: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 6fffefdc 00000000 00000000 00000000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3660 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3661 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3662 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c90: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000001 00000001 00000001 00000001 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3663 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3664 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3665 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c90: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000002 00000002 00000002 00000002 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3666 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3667 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3668 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c90: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 00000003 00000003 00000003 00000003 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3669 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3670 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c90 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3671 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c94: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3672 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3673 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3674 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c94: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000001 00000001 00000001 00000001 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3675 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3676 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3677 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c94: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000002 00000002 00000002 00000002 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3678 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3679 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3680 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c94: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10010000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000003 00000003 00000003 00000003 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3681 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3682 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c94 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3683 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2a40433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2a40433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c98: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3684 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3685 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3686 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2a40433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2a40433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c98: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000400 00000400 00000400 00000400 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c98 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3687 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c98 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3688 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c98 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3689 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2a40433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2a40433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c98: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000800 00000800 00000800 00000800 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c98 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3690 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2a40433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2a40433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c98: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000c00 00000c00 00000c00 00000c00 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 00000400 00000400 00000400 00000400 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c98 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3691 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 84a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x84a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c9c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3692 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 84a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x84a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c9c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000400 00000400 00000400 00000400 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c9c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3693 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 84a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x84a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c9c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000800 00000800 00000800 00000800 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c9c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3694 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c9c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3695 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000c9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 84a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x84a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000c9c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffefdc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10020000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000c8c 80000c8c 80000c8c 80000c8c (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000c00 00000c00 00000c00 00000c00 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c9c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3696 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c9c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3697 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000c9c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3698 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000b24 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffebf4, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffec00 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000b24 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe7f8, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe804 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000b24 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe3fc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe408 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000b24 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3699 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3700 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3701 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffefe0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffebf4, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffec00 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe7f8, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe804 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe3fc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe408 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000400 00000400 00000400 00000400 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3702 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3703 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3704 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffefe0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffebf4, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffec00 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe7f8, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe804 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe3fc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe408 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000800 00000800 00000800 00000800 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3705 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3706 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3707 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffefe0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffebf4, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffec00 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe7f8, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe804 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe3fc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe408 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000998 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000c00 00000c00 00000c00 00000c00 (0) + %r 9: 6fffefdc 6fffefdc 6fffefdc 6fffefdc (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3708 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3709 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3710 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3711 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3712 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3713 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffebf4, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffebf8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe7f8, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe7fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe3fc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe400 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3714 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3715 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3716 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3717 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3718 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3719 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3720 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3721 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3722 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffefe0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffebf4, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffebf8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe7f8, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe7fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe3fc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe400 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000400 00000400 00000400 00000400 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3723 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3724 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3725 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3726 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3727 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3728 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3729 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3730 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3731 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffefe0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffebf4, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffebf8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe7f8, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe7fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe3fc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe400 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000800 00000800 00000800 00000800 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3732 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3733 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3734 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3735 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3736 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3737 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3738 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3739 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3740 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3741 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3742 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3743 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffefe0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffebf4, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffebf8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe7f8, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe7fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe3fc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe400 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000c00 00000c00 00000c00 00000c00 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3744 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3745 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3746 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3747 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3748 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3749 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3750 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3751 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3752 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1240433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1240433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000001 00000002 00000003 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3753 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3754 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3755 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3756 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3757 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3758 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3759 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3760 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3761 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3762 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3763 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3764 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1240433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1240433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000400 00000401 00000402 00000403 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3765 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3766 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3767 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3768 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3769 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3770 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3771 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3772 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3773 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3774 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3775 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3776 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1240433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1240433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000800 00000801 00000802 00000803 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3777 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ca8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1240433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1240433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ca8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000c00 00000c01 00000c02 00000c03 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ca8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3778 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 241413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x241413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000004 00000008 0000000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3779 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 241413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x241413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00001000 00001004 00001008 0000100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cac +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3780 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 241413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x241413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00002000 00002004 00002008 0000200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cac +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3781 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 241413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x241413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00003000 00003004 00003008 0000300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000000 10000000 10000000 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cac +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3782 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 870733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x870733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000004 00000008 0000000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10000000 10000004 10000008 1000000c (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3783 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 870733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x870733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00001000 00001004 00001008 0000100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10001000 10001004 10001008 1000100c (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3784 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 870733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x870733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00002000 00002004 00002008 0000200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10002000 10002004 10002008 1000200c (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3785 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 870733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x870733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00003000 00003004 00003008 0000300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10010000 10010000 10010000 10010000 (0) + %r14: 10003000 10003004 10003008 1000300c (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3786 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000004 00000008 0000000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010004 10010008 1001000c (0) + %r14: 10000000 10000004 10000008 1000000c (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3787 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00001000 00001004 00001008 0000100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10011000 10011004 10011008 1001100c (0) + %r14: 10001000 10001004 10001008 1000100c (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3788 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00002000 00002004 00002008 0000200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10012000 10012004 10012008 1001200c (0) + %r14: 10002000 10002004 10002008 1000200c (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3789 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00003000 00003004 00003008 0000300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10013000 10013004 10013008 1001300c (0) + %r14: 10003000 10003004 10003008 1000300c (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3790 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10000000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10000004, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 409 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10000008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=1000000c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1000000c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 65206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000004 00000008 0000000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: 10010000 10010004 10010008 1001000c (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3791 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10001000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10001000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10001004, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10001004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10001008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10001008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=1000100c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1000100c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00001000 00001004 00001008 0000100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10011000 10011004 10011008 1001100c (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3792 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10002000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10002000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10002004, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10002004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10002008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10002008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=1000200c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1000200c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00002000 00002004 00002008 0000200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10012000 10012004 10012008 1001200c (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3793 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3794 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cb8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10003000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10003000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10003004, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10003004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10003008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10003008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=1000300c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1000300c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00003000 00003004 00003008 0000300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: 10013000 10013004 10013008 1001300c (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3795 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3796 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cb8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3797 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cbc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10010000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10010000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10010004, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10010004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10010008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10010008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=1001000c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1001000c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000004 00000008 0000000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3798 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3799 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3800 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cbc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10011000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10011000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10011004, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10011004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10011008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10011008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=1001100c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1001100c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00001000 00001004 00001008 0000100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3801 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3802 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3803 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cbc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10012000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10012000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10012004, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10012004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10012008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10012008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=1001200c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1001200c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00002000 00002004 00002008 0000200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3804 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3805 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3806 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cbc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10013000, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10013000 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10013004, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10013004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=10013008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10013008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r13=1001300c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1001300c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00003000 00003004 00003008 0000300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3807 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3808 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cbc +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3809 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 878433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x878433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10020000 10020004 10020008 1002000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3810 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3811 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3812 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3813 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3814 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3815 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 878433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x878433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10021000 10021004 10021008 1002100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3816 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 878433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x878433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10022000 10022004 10022008 1002200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3817 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 878433 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x878433 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10023000 10023004 10023008 1002300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000001 00000002 00000003 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3818 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffebf4, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffebf4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe7f8, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe7f8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe3fc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe3fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10020000 10020004 10020008 1002000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3819 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffefe0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffebf4, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffebf4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe7f8, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe7f8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe3fc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe3fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10021000 10021004 10021008 1002100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3820 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffefe0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffebf4, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffebf4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe7f8, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe7f8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe3fc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe3fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10022000 10022004 10022008 1002200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3821 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3822 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffefe0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffebf4, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffebf4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe7f8, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe7f8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe3fc, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe3fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10023000 10023004 10023008 1002300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: 10020000 10020000 10020000 10020000 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3823 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3824 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3825 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3826 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3827 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3828 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3829 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3830 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3831 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d707b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd707b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10020000 10020004 10020008 1002000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3832 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3833 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3834 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3835 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3836 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3837 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3838 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3839 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3840 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3841 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3842 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3843 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d707b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd707b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10021000 10021004 10021008 1002100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3844 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3845 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3846 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3847 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3848 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3849 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d707b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd707b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10022000 10022004 10022008 1002200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3850 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d707b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd707b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cc8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10023000 10023004 10023008 1002300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cc8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3851 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ccc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ccc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10020000, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10020000 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10020004, rf=ddccbfb3, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10020004 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10020008, rf=4c3f2115, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10020008 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=1002000c, rf=42ed280f, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1002000c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10020000 10020004 10020008 1002000c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3852 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ccc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ccc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10021000, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10021000 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10021004, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10021004 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10021008, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10021008 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=1002100c, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1002100c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10021000 10021004 10021008 1002100c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3853 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ccc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ccc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10022000, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10022000 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10022004, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10022004 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10022008, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10022008 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=1002200c, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1002200c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10022000 10022004 10022008 1002200c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3854 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3855 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3856 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3857 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3858 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3859 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3860 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3861 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ccc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ccc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10023000, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10023000 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10023004, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10023004 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=10023008, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10023008 +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=1002300c, rf=bb997754, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1002300c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 10023000 10023004 10023008 1002300c (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ccc +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3862 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffebf4, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffebfc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe7f8, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe800 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe3fc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe404 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefb0 6fffebf4 6fffe7f8 6fffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 6 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3863 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffefe0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffebf4, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffebfc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe7f8, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe800 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe3fc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe404 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffefe0 6bffebf4 6bffe7f8 6bffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3864 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffefe0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffebf4, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffebfc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe7f8, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe800 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe3fc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe404 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffefe0 67ffebf4 67ffe7f8 67ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3865 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffefe0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffebf4, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffebfc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe7f8, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe800 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe3fc, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe404 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffefe0 63ffebf4 63ffe7f8 63ffe3fc (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3866 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3867 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3868 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3869 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3870 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 9 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3871 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3872 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3873 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3874 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3875 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3876 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3877 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3878 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3879 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3880 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3881 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3882 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3883 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3884 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3885 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3886 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3887 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3888 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3889 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3890 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3891 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3892 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3893 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3894 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ac1ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xac1ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000798 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3895 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ac1ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xac1ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000798 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3896 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ac1ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xac1ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000798 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3897 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ac1ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xac1ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cd8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000798 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cd8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3898 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3899 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3900 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000798 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 306b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x306b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000798: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1041: Uni branch at join +NEW DOMESTACK: +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000798 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 0 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3901 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000798 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 306b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x306b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000798: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1041: Uni branch at join +NEW DOMESTACK: +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000798 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 0 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3902 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000798 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 306b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x306b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000798: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1041: Uni branch at join +NEW DOMESTACK: +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000798 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 0 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3903 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000798 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 306b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x306b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000798: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1041: Uni branch at join +NEW DOMESTACK: +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:1036: JOIN +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000798 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 0 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3904 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000079c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000079c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b24, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b24, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b24, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b24, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000b24 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b24 80000b24 80000b24 80000b24 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000079c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3905 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000079c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000079c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000998 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000079c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3906 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000079c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000079c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000998 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000079c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3907 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000079c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000079c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000998, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000998 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000998 80000998 80000998 80000998 (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000079c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3908 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3909 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3910 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c7dff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc7dff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b24: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b28 80000b28 80000b28 80000b28 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3911 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000998 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e09ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe09ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000998: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000998 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3912 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000998 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e09ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe09ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000998: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000998 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3913 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000998 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e09ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe09ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000998: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800007a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000400 00000400 00000400 00000400 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000998 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3914 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3915 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3916 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2102573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2102573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a0: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b28 80000b28 80000b28 80000b28 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3917 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2102573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2102573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a0: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3918 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2102573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2102573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a0: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 2 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000002 00000002 00000002 00000002 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3919 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2102573 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2102573 into: SYS + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a0: SYS +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:855: CSR Reading wid 21 and returning 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000003 00000003 00000003 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3920 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b28, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b28, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b28, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000b28, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000b28 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b28 80000b28 80000b28 80000b28 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3921 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000099c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3922 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000099c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000002 00000002 00000002 00000002 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3923 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800007a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800007a4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000099c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000099c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000003 00000003 00000003 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800007a4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3924 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3925 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3926 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2050063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2050063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b28: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000b48 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b28 80000b28 80000b28 80000b28 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3927 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000099c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000099c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000099c +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3928 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000099c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000099c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000002 00000002 00000002 00000002 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000099c +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3929 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000099c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000099c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 8000099c 8000099c 8000099c 8000099c (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000003 00000003 00000003 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000099c +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3930 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3931 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3932 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b48: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefc8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffec04, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffec0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe808, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe810 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe40c, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe414 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 80000b28 80000b28 80000b28 80000b28 (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3933 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3934 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3935 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3936 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffeff0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffeffc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffec04, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffec10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe808, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe814 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6bffe40c, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6bffe418 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3937 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffeff0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffeffc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffec04, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffec10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe808, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe814 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=67ffe40c, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 67ffe418 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000002 00000002 00000002 00000002 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3938 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffeff0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffeffc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffec04, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffec10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe808, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe814 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=63ffe40c, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 63ffe418 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000003 00000003 00000003 00000003 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3939 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3940 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3941 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3942 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3943 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3944 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3945 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3946 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3947 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3948 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3949 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 12 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3950 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b4c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefcc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800000a0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffec04, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffec10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe808, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe814 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe40c, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe418 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 800000a0 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3951 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3952 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3953 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3954 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3955 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3956 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3957 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3958 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3959 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3960 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3961 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3962 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6bffeff0 6bffec04 6bffe808 6bffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3963 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3964 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3965 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3966 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3967 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3968 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3969 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3970 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3971 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3972 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3973 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3974 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 67ffeff0 67ffec04 67ffe808 67ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3975 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3976 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3977 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3978 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3979 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3980 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3981 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3982 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3983 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3984 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3985 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3986 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 63ffeff0 63ffec04 63ffe808 63ffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a4 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3987 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefc4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffec04, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffec08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe808, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe80c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe40c, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe410 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 800000a0 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3988 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6bfff000 6bffec14 6bffe818 6bffe41c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a8 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3989 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 67fff000 67ffec14 67ffe818 67ffe41c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3990 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a8 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3991 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009a8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 63fff000 63ffec14 63ffe818 63ffe41c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009a8 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3992 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b54: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefc0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffec04, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffec04 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe808, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe808 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffe40c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffe40c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ddccbbaa +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 800000a0 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3993 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: dd5ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xdd5ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009ac: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6bfff000 6bffec14 6bffe818 6bffe41c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009ac +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3994 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: dd5ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xdd5ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009ac: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 67fff000 67ffec14 67ffe818 67ffe41c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009ac +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3995 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800009ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: dd5ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xdd5ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800009ac: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 63fff000 63ffec14 63ffe818 63ffe41c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 00000000 00000000 00000000 00000000 (0) + %r 6: 00000000 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 00000000 00000000 00000000 (0) + %r 9: 00000000 00000000 00000000 00000000 (0) + %r10: 00000000 00000000 00000000 00000000 (0) + %r11: 00000000 00000400 00000800 00000c00 (0) + %r12: 00000000 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r15: bb997754 bb997754 bb997754 bb997754 (0) + %r16: 00000000 00000000 00000000 00000000 (0) + %r17: 00000000 00000000 00000000 00000000 (0) + %r18: 00000000 00000000 00000000 00000000 (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000000 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800009ac +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3996 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 800000a0 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6fffefc0 6fffec04 6fffe808 6fffe40c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3997 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 800000a0 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6fffefd0 6fffec14 6fffe818 6fffe41c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3998 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000b60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c21ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc21ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000b60: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 00000000 00000000 00000000 (0) + %r 1: 800000a0 ddccbbaa ddccbbaa ddccbbaa (0) + %r 2: 6fffefd0 6fffec14 6fffe818 6fffe41c (0) + %r 3: 80016808 80016808 80016808 80016808 (0) + %r 4: 00000000 00000000 00000000 00000000 (0) + %r 5: 80000e64 00000000 00000000 00000000 (0) + %r 6: 00000005 00000000 00000000 00000000 (0) + %r 7: 00000000 00000000 00000000 00000000 (0) + %r 8: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r 9: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r10: 00000001 00000001 00000001 00000001 (0) + %r11: 8000097c 00000400 00000800 00000c00 (0) + %r12: 80000c2c 00000004 00000008 0000000c (0) + %r13: ddccbbaa ddccbbaa ddccbbaa ddccbbaa (0) + %r14: ddccbbaa 00000409 6e72656b 65206c65 (0) + %r15: bb997754 ddccbfb3 4c3f2115 42ed280f (0) + %r16: 10010000 00000000 00000000 00000000 (0) + %r17: 10000000 00000000 00000000 00000000 (0) + %r18: 00000000 ddccbbaa ddccbbaa ddccbbaa (0) + %r19: 00000000 00000000 00000000 00000000 (0) + %r20: 00000000 00000000 00000000 00000000 (0) + %r21: 00000000 00000000 00000000 00000000 (0) + %r22: 00000000 00000000 00000000 00000000 (0) + %r23: 00000000 00000000 00000000 00000000 (0) + %r24: 00000000 00000000 00000000 00000000 (0) + %r25: 00000000 00000000 00000000 00000000 (0) + %r26: 00000000 00000000 00000000 00000000 (0) + %r27: 00000000 00000000 00000000 00000000 (0) + %r28: 00000003 00000000 00000000 00000000 (0) + %r29: 00000000 00000000 00000000 00000000 (0) + %r30: 00000000 00000000 00000000 00000000 (0) + %r31: 00000000 00000000 00000000 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 1 1 1 + + +DEBUG ../../../simX/core.cpp:421: Now 4 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000b60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 3999 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 1[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0:(0) + %r 1:(0) + %r 2:(0) + %r 3:(0) + %r 4:(0) + %r 5:(0) + %r 6:(0) + %r 7:(0) + %r 8:(0) + %r 9:(0) + %r10:(0) + %r11:(0) + %r12:(0) + %r13:(0) + %r14:(0) + %r15:(0) + %r16:(0) + %r17:(0) + %r18:(0) + %r19:(0) + %r20:(0) + %r21:(0) + %r22:(0) + %r23:(0) + %r24:(0) + %r25:(0) + %r26:(0) + %r27:(0) + %r28:(0) + %r29:(0) + %r30:(0) + %r31:(0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 0 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 0 active threads in 1 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4000 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 2[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0:(0) + %r 1:(0) + %r 2:(0) + %r 3:(0) + %r 4:(0) + %r 5:(0) + %r 6:(0) + %r 7:(0) + %r 8:(0) + %r 9:(0) + %r10:(0) + %r11:(0) + %r12:(0) + %r13:(0) + %r14:(0) + %r15:(0) + %r16:(0) + %r17:(0) + %r18:(0) + %r19:(0) + %r20:(0) + %r21:(0) + %r22:(0) + %r23:(0) + %r24:(0) + %r25:(0) + %r26:(0) + %r27:(0) + %r28:(0) + %r29:(0) + %r30:(0) + %r31:(0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 0 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 0 active threads in 2 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4001 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 3[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0:(0) + %r 1:(0) + %r 2:(0) + %r 3:(0) + %r 4:(0) + %r 5:(0) + %r 6:(0) + %r 7:(0) + %r 8:(0) + %r 9:(0) + %r10:(0) + %r11:(0) + %r12:(0) + %r13:(0) + %r14:(0) + %r15:(0) + %r16:(0) + %r17:(0) + %r18:(0) + %r19:(0) + %r20:(0) + %r21:(0) + %r22:(0) + %r23:(0) + %r24:(0) + %r25:(0) + %r26:(0) + %r27:(0) + %r28:(0) + %r29:(0) + %r30:(0) + %r31:(0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 0 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 0 active threads in 3 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4002 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4003 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 1, 1, 1, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4004 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 1 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[4] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4005 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 1 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4006 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 1 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4007 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4008 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4009 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4010 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000784 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000784: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800000a0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800000a0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000784 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4011 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4012 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4013 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4014 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4015 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4016 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80015537 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80015537 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000a0: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80015000 (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4017 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a1c50513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa1c50513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000a0 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4018 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68d000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68d000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000a8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000f34 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4019 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4020 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4021 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4022 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4023 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4024 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4025 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d81a303 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d81a303 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f34: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=472 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169e0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4026 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4027 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4028 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4029 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fc010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfc010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f38: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4030 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rc=80000c2c, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4031 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2d12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2d12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rd=ddccbbaa, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4032 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2b12223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2b12223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rb=8000097c, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4033 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4034 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e12823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e12823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, re=ddccbbaa, imm=48 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4035 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f12a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f12a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f4c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rf=bb997754, imm=52 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4036 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3012c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3012c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f50: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r10=10010000, imm=56 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4037 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f54: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r11=10000000, imm=60 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefcc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 8000097c (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4038 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 832583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x832583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f58: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r6=80016010, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016018 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 80016364 (0) + %r12: 80000c2c (0) + %r13: ddccbbaa (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 6 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4039 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2410693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2410693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 80016364 (0) + %r12: 80000c2c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4040 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f60: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80014a1c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4041 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f64: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 6 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4042 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f68: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r1=800000ac, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4043 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f6c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, rd=6fffefb4, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4044 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f70: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000f80 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4045 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:663: $$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4046 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4047 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4048 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4049 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4050 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4051 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4052 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4053 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4054 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4055 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f84: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r1=80000f74, imm=492 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4056 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1f212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1f212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f88: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r12=0, imm=480 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef80 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4057 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f8c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r18=0, imm=456 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef68 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4058 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4059 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1da12023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1da12023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f90: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r1a=0, imm=448 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef60 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 26 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4060 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58c13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58c13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4061 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f98: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4062 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d12a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd12a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f9c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rd=6fffefb4, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4063 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fa0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fa0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r8=0, imm=488 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fa0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4064 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fa4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fa4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r9=0, imm=484 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4065 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fa8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fa8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r13=0, imm=476 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef7c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fa8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4066 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fac: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r14=0, imm=472 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef78 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4067 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fb0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r15=0, imm=468 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef74 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fb0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4068 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fb4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r16=0, imm=464 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef70 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4069 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fb8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r17=0, imm=460 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef6c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fb8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4070 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fbc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r19=0, imm=452 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef64 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 25 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4071 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1bb12e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1bb12e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fc0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r1b=0, imm=444 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef5c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 27 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4072 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50d13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50d13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fc4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 26 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4073 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 570060ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x570060ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fc8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007538 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4074 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4075 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4076 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4077 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4078 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4079 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007538 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12818513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12818513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007538: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016930 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4080 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4081 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4082 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4083 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000753c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000753c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000fcc, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000fcc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016930 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: bb997754 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000753c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4084 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4085 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4086 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4087 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4088 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4089 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fcc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fcc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016930, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016930 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8001536c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016930 (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: 8001536c (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fcc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4090 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fd0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: 8001536c (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4091 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f12823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f12823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fd4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=8001536c, imm=48 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedd0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fcc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: 8001536c (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4092 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 514080ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x514080ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fd8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800094ec +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: 8001536c (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4093 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4094 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4095 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4096 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4097 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4098 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4099 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 357793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x357793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: ddccbbaa (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4100 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4101 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4102 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4103 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4104 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4079c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4079c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 6fffefb4 (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4105 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4106 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4107 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4108 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4109 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4110 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7f7f86b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7f7f86b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094f8: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 7f7f8000 (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4111 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800094fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f7f68693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf7f68693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800094fc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: 80016364 (0) + %r12: 80014a1c (0) + %r13: 7f7f7f7f (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800094fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4112 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009500 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009500: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 80014a1c (0) + %r13: 7f7f7f7f (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4113 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4114 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4115 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4116 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009504 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 72603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x72603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009504: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=8001536c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001536c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 8001536c (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009504 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4117 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009508 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 470713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x470713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009508: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009508 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4118 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000950c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d677b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd677b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000950c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 0000002e (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000950c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4119 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009510 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009510: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 7f7f7fad (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009510 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4120 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009514 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c7e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc7e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009514: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 7f7f7faf (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009514 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4121 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009518 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d7e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd7e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009518: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 7f7f7fff (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009518 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4122 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009518 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4123 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000951c +DEBUG ../../../simX/enc.cpp:105: Curr Code: feb784e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfeb784e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000951c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 7f7f7f7f (0) + %r14: 80015370 (0) + %r15: 7f7f7fff (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000951c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4124 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000951c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4125 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4126 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4127 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4128 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4129 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4130 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4131 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4132 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009520 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc74683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc74683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009520: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80015370, imm=4294967292 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001536c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 0000002e (0) + %r13: 0000002e (0) + %r14: 80015370 (0) + %r15: 7f7f7fff (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009520 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4133 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009524 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffd74603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffd74603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009524: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80015370, imm=4294967293 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001536c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 80015370 (0) + %r15: 7f7f7fff (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009524 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4134 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009528 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffe74783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffe74783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009528: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=80015370, imm=4294967294 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001536c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 80015370 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009528 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4135 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000952c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40a70733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40a70733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000952c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000952c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4136 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009530 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4068063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4068063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009530: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009530 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4137 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4138 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4139 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4140 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4141 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4142 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009534 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2060a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2060a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009534: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80009568 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 8001536c (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009534 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 12 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4143 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4144 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4145 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4146 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4147 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4148 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009568 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffd70513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffd70513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009568: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4149 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4150 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4151 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4152 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000956c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000956c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000fdc, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000fdc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000956c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4153 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4154 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4155 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4156 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4157 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4158 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fdc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2a12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2a12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fdc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, ra=1, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedcc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4159 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fe0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fe0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=240 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fe0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4160 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fe4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fe4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=244 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee94 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fe4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4161 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fe8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fe8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=248 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee98 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fe8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4162 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000fec +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000fec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=252 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000fec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4163 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ff0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d0663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd0663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ff0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000004 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ff0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 26 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4164 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4165 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4166 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4167 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4168 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4169 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ff4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 38d2703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x38d2703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ff4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r26=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ff4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4170 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ff8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a0708e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa0708e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ff8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000002e (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ff8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4171 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4172 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4173 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4174 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4175 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4176 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4177 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000ffc +DEBUG ../../../simX/enc.cpp:105: Curr Code: cc1683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcc1683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000ffc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00002889 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000ffc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4178 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001000 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1069713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1069713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001000: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00002889 (0) + %r14: 28890000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4179 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4180 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4181 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4182 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001004 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1269793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1269793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001004: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00002889 (0) + %r14: 28890000 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001004 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4183 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001008 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1075713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1075713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001008: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00002889 (0) + %r14: 00002889 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001008 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4184 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000100c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 207ca63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x207ca63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000100c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80001040 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00002889 (0) + %r14: 00002889 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000100c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4185 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4186 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4187 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4188 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4189 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4190 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001040 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 877693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x877693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001040: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000008 (0) + %r14: 00002889 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4191 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4192 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4193 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4194 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001044 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e068863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e068863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001044: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000008 (0) + %r14: 00002889 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001044 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4195 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4196 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4197 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4198 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4199 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4200 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4201 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001048 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10c2683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10c2683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001048: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001048 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4202 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000104c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e068463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e068463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000104c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 10000008 (0) + %r14: 00002889 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000104c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4203 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4204 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4205 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4206 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4207 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4208 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4209 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001050 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a77713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a77713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001050: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 10000008 (0) + %r14: 00000008 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001050 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4210 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001054 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a00693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa00693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001054: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 00000008 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001054 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4211 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001058 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d70063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d70063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001058: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 00000008 (0) + %r15: a2240000 (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4212 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4213 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4214 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4215 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4216 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4217 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4218 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000105c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10c10793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10c10793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000105c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 00000008 (0) + %r15: 6fffeeac (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000105c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4219 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001060 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80015737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80015737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001060: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 6fffeeac (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001060 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4220 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001064 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ef12223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xef12223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001064: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=6fffeeac, imm=228 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 6fffeeac (0) + %r16: 10010000 (0) + %r17: 10000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4221 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001068 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001068: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 6fffeeac (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001068 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4222 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000106c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a6c70793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa6c70793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000106c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014a6c (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000106c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4223 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001070 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80015737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80015737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001070: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014a6c (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001070 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4224 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001074 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f12c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf12c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001074: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=80014a6c, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedb8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014a6c (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001074 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4225 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001078 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90b13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001078: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014a6c (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001078 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4226 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000107c +DEBUG ../../../simX/enc.cpp:105: Curr Code: be870793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xbe870793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000107c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014be8 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000107c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4227 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001080 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f12423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf12423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001080: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=80014be8, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeda8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 80014be8 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4228 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4229 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4230 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001080 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4231 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001084 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b4783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb4783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001084: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r22=80014a1c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001084 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4232 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001088 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001088: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=236 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001088 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4233 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000108c +DEBUG ../../../simX/enc.cpp:105: Curr Code: e012423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe012423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000108c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=232 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000108c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4234 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001090 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001090: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedc0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001090 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4235 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001090 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4236 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001090 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4237 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001094 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001094: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=52 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedd4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001094 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4238 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001098 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001098: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=56 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedd8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001098 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4239 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000109c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000109c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=60 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeddc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000109c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4240 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4012423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4012423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010a0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=72 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffede8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4241 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4012623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4012623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010a4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=76 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedec +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4242 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010a8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, r0=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4243 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 22078663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x22078663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010ac: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4244 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4245 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4246 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4247 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4248 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4249 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b0413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb0413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1c (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000a (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4250 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2500693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2500693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1c (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4251 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1c (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006b (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4252 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4253 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4254 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4255 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4256 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4257 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4258 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a1c, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1c (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4259 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1d (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4260 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 101 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1d (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4261 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4262 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4263 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4264 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4265 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4266 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1d (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4267 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4268 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4269 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4270 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4271 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4272 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a1d, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1d (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000072 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4273 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1e (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000072 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4274 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 114 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1e (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000072 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4275 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4276 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4277 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4278 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4279 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4280 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1e (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000072 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4281 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4282 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4283 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4284 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4285 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4286 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a1e, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1e (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4287 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1f (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4288 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 110 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1f (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4289 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4290 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4291 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4292 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4293 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4294 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1f (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4295 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4296 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4297 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4298 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4299 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4300 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a1f, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a1f (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4301 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a20 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4302 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 101 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a20 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4303 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4304 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4305 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4306 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4307 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4308 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a20 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4309 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4310 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4311 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4312 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4313 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4314 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a20, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a20 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006c (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4315 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a21 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006c (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4316 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 108 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a21 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006c (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4317 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4318 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4319 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4320 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4321 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4322 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a21 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006c (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4323 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4324 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4325 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4326 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4327 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4328 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a21, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a21 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000020 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4329 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a22 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000020 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4330 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 32 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a22 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000020 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4331 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4332 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4333 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4334 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4335 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4336 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a22 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000020 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4337 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4338 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4339 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4340 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4341 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4342 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a22, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a22 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000064 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4343 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a23 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000064 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4344 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 100 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a23 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000064 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4345 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4346 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4347 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4348 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4349 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4350 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a23 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000064 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4351 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4352 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4353 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4354 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4355 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4356 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a23, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a23 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006f (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4357 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a24 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006f (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4358 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 111 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a24 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006f (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4359 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4360 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4361 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4362 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4363 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4364 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a24 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006f (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4365 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4366 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4367 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4368 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4369 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4370 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a24, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a24 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4371 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a25 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4372 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 110 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a25 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4373 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4374 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4375 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4376 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4377 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4378 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a25 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000006e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4379 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4380 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4381 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4382 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4383 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4384 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a25, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a25 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4385 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a26 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4386 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 101 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a26 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4387 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4388 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4389 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4390 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4391 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4392 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a26 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000065 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4393 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4394 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4395 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4396 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4397 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4398 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a26, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a26 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4399 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a27 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4400 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 46 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a27 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4401 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4402 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4403 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4404 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4405 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4406 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a27 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000002e (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4407 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4408 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4409 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4410 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4411 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4412 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a27, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a28 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a27 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000000a (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4413 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a28 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000000a (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4414 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 10 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800010b8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a28 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000000a (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4415 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4416 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4417 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4418 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4419 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4420 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 30d78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x30d78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a28 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 0000000a (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4421 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4422 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4423 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4424 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4425 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4426 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 144783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x144783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a28, imm=1 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a28 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a28 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4427 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 140413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x140413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4428 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe079ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe079ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 00000000 (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4429 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4430 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4431 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4432 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4433 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4434 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 416404b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x416404b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010c8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 8 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4435 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 21640663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x21640663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010cc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000025 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4436 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4437 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4438 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4439 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4440 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4441 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ec12683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xec12683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010d0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=236 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4442 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e812783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe812783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010d4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=232 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee88 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4443 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 168a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x168a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010d8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r17=6fffeeac, r16=80014a1c, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeeac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 17 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4444 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 9686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x9686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010dc: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000d (0) + %r14: 80015000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4445 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010e0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000d (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4446 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98a223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98a223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010e4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r17=6fffeeac, r9=d, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeeb0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000d (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 17 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4447 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ed12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xed12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010e8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rd=d, imm=236 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000d (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4448 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: ef12423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xef12423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010ec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, rf=1, imm=232 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 0000000d (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4449 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 700693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x700693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 10010000 (0) + %r17: 6fffeeac (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4450 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 888893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x888893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4451 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2ef6c263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2ef6c263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010f8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 80015000 (0) + %r15: 00000001 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4452 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4453 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4454 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4455 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4456 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4457 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800010fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800010fc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffedac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800010fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4458 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001100 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001100: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80014a29, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a28 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001100 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4459 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001104 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 970733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x970733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001104: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001104 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4460 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001108 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e12623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe12623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001108: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeda0, re=d, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffedac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001108 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4461 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000110c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c078663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c078663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000110c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800012d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000110c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4462 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4463 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4464 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4465 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4466 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4467 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4468 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ec12783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xec12783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=236 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4469 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012dc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4470 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4471 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4472 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4473 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4474 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4475 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4476 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3250106f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3250106f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012e0: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80002e04 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 00000000 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4477 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4478 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4479 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4480 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4481 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4482 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e410613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe410613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e04: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: ffffffff (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4483 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e08: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4484 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d0513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd0513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e0c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000fdc (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 26 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4485 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 314090ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x314090ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e10: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c124 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4486 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4487 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4488 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4489 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4490 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4491 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c124 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 862703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x862703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c124: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r12=6fffee84, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c124 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4492 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c128 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 70463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x70463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c128: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c128 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4493 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4494 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4495 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4496 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4497 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4498 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4499 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c12c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f09ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf09ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c12c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c034 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c12c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4500 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4501 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4502 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4503 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4504 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4505 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c034 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 645a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x645a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c034: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=100 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163c8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c034 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4506 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c038 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c038: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c038 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4507 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c03c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c03c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r16=80014a1c, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed80 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c03c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4508 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c040 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c040: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r1=80002e14, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4509 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4510 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4511 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c040 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4512 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c044 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c044: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r8=80014a29, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed98 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c044 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4513 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c048 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c048: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r9=d, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed94 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c048 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4514 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c04c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c04c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r12=80014a1c, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c04c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4515 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c050 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c050: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r13=0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c050 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4516 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c054 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c054: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r14=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c054 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4517 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c058 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c058: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r15=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4518 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c05c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c05c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r17=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed7c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c05c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4519 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c060 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c060: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed70, r18=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed78 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c060 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4520 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c064 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1279713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1279713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c064: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4521 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c068 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60b13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c068: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c068 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4522 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c06c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a075863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa075863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c06c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c11c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c06c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4523 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4524 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4525 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4526 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4527 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4528 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c11c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f1010ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf1010ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c11c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000da0c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c11c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4529 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4530 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4531 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4532 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4533 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4534 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 862783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x862783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da0c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r12=6fffee84, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4535 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 32078e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x32078e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da10: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4536 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4537 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4538 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4539 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4540 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4541 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4542 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c5d783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc5d783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da14: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4543 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4544 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da1c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r8=80014a29, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4545 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da20: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r14=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed58 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4546 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da24: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r15=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed54 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4547 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4548 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da28: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r1=8000c120, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4549 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da2c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r9=d, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4550 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da30: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r12=80014a1c, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed60 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4551 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da34: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r13=0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed5c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4552 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r16=6fffee84, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4553 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r17=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed4c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4554 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r18=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed48 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4555 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da44: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r19=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed44 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 25 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4556 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a12023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a12023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da48: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed40, r1a=80016010, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed40 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 26 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4557 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 87f713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x87f713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4558 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60a13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60a13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da50: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4559 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50a93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50a93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da54: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4560 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4561 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8070663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8070663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da5c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000008 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4562 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4563 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4564 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4565 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4566 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4567 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 105a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x105a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da60: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 10000008 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4568 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8070263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8070263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da64: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 10000008 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4569 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4570 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4571 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4572 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4573 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4574 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4575 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 27f713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x27f713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da68: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4576 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a2483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa2483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da6c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r20=6fffee84, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee84 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffeeac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4577 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000da70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8070c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8070c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000da70: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000db08 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000da70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4578 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4579 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4580 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4581 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4582 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4583 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000db08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17f713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17f713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000db08: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4584 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4585 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4586 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4587 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000db0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 24071463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x24071463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000db0c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dd54 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000db0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4588 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4589 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4590 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4591 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4592 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4593 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4594 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd54: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4595 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4596 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4597 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd60: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4598 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ec098ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xec098ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd64: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dc38 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 19 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4599 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4600 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4601 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4602 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4603 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4604 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4605 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44a983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44a983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc38: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffeeac, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeeb0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4606 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4607 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4608 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4609 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4ac03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4ac03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc3c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=6fffeeac, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeeac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeac (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4610 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 848493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x848493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4611 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4612 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4613 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4614 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe098ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe098ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc44: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 6fffee84 (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 19 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4615 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4616 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4617 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4618 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4619 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4620 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4621 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a00593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa00593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4622 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc50: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4623 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a7cfa0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa7cfa0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc54: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007ed0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4624 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4625 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4626 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4627 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4628 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4629 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ed0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 357793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x357793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ed0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 00000007 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4630 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ed4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff5f693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff5f693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ed4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4631 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007ed8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2078a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2078a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007ed8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f0c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007ed8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4632 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4633 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4634 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4635 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4636 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4637 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f0c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 00000001 (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4638 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4639 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4640 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4641 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 300713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x300713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f10: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 00000003 (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4642 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f76663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f76663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f14: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f40 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 00000003 (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4643 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4644 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4645 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4646 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4647 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4648 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4649 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f40: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 00010000 (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 6fffeeb4 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4650 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4651 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4652 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4653 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 859893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x859893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 00010000 (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 00000a00 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4654 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff70713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff70713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 00000a00 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4655 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8f8b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8f8b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f4c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 00000a00 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4656 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff5f593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff5f593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f50: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 0000000a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 00000a00 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4657 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8e5b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8e5b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f54: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 00000a0a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 00000a00 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 17 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4658 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 17 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4659 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1059893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1059893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 00000a0a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 0a0a0000 (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4660 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8e8b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8e8b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f5c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 00000a0a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: 10010000 (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4661 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 17 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4662 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: feff0837 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfeff0837 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f60: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 00000a0a (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: feff0000 (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4663 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4664 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 808085b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x808085b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f64: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808000 (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: feff0000 (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4665 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4666 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: eff80813 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xeff80813 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f68: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808000 (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 16 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4667 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8058593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8058593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f6c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 80016010 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4668 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 300313 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x300313 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f70: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 0000ffff (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4669 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a1c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 6e72656b (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4670 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8c733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8c733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 0000000d (0) + %r13: 0000000a (0) + %r14: 64786f61 (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4671 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 64786f61 (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4672 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff74713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff74713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 9b87909e (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4673 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4674 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4675 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4676 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e67733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe67733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f84: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 03070000 (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4677 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f88: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4678 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8071ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8071ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4679 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4680 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4681 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4682 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4683 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4684 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4685 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4686 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4687 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc78793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc78793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f90: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a1c (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4688 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 450513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x450513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4689 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fcf36ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfcf36ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f98: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4690 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4691 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4692 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4693 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4694 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4695 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a20, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 64206c65 (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4696 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8c733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8c733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 63776e60 (0) + %r13: 0000000a (0) + %r14: 6e2a666f (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4697 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 6e2a666f (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4698 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff74713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff74713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 91d59990 (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4699 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4700 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e67733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe67733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f84: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 01010100 (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4701 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4702 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f88: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4703 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8071ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8071ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4704 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4705 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4706 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4707 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4708 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4709 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4710 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4711 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4712 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc78793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc78793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f90: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a20 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4713 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 450513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x450513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4714 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fcf36ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfcf36ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f98: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4715 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4716 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4717 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4718 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4719 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4720 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 52703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x52703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a24, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 2e656e6f (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4721 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e8c733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe8c733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f78: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 6d29656e (0) + %r13: 0000000a (0) + %r14: 246f6465 (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 17 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4722 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1070633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1070633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f7c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 246f6465 (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 16 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4723 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff74713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff74713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: db909b9a (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4724 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4725 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e67733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe67733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f84: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 03000300 (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4726 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4727 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b77733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb77733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f88: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4728 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8071ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8071ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000005 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4729 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4730 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4731 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4732 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4733 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4734 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4735 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4736 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4737 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc78793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc78793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f90: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a24 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4738 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 450513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x450513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f94: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4739 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fcf36ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfcf36ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f98: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 6 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4740 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4741 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4742 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4743 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4744 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4745 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80794e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80794e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f9c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f24 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4746 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4747 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4748 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4749 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4750 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4751 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f507b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf507b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f24: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 80014a29 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4752 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0006f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0006f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f28: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007f34 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 00000000 (0) + %r15: 80014a29 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4753 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4754 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4755 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4756 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4757 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4758 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 54703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x54703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f34: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80014a28, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a28 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a29 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4759 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed71ae3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed71ae3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 10 rsrc1 : 10 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a29 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4760 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4761 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4762 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4763 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4764 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4765 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4766 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007f3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007f3c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000dc58, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dc58 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a29 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007f3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4767 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4768 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4769 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4770 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4771 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4772 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12050463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12050463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc58: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a28 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a29 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4773 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4774 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4775 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4776 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4777 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4778 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 150513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x150513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc5c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a29 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a29 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4779 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41850b33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41850b33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc60: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a29 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 80014a29 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 10 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4780 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b0793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb0793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc64: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a29 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 00000000 (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4781 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98b93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98b93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc68: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a29 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4782 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4783 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 137f463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x137f463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc6c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dc74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80014a29 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4784 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4785 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4786 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4787 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4788 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4789 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4790 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 0000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4791 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1042783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1042783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc78: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 0000000a (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4792 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1442683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1442683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc7c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016378 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 400 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4793 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a7f863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa7f863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc80: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dc90 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4794 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4795 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4796 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4797 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4798 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4799 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dc90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1adbc863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1adbc863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dc90: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000de40 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: 236e6364 (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dc90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 23 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4800 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4801 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4802 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4803 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4804 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4805 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de40: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80808080 (0) + %r12: 0000000d (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4806 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c0593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc0593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000dc58 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4807 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 354000ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x354000ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de48: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e19c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4808 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4809 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4810 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4811 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4812 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4813 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e19c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2a5f663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2a5f663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e19c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1c8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e19c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4814 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4815 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4816 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4817 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4818 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4819 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1c8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 0000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4820 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c7e863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c7e863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1cc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 0000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4821 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4822 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4823 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4824 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4825 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4826 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4827 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1d0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 00000400 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4828 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff60693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff60693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1d4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 0000000c (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4829 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c060c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc060c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1d8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 0000000c (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 12 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4830 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4831 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4832 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4833 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4834 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4835 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 168693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x168693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1dc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4836 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d786b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd786b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4837 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a1c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006b (0) + %r15: 10000008 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4838 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1c (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006b (0) + %r15: 10000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4839 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4840 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1d (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006b (0) + %r15: 10000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4841 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000009, re=6b, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1d (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006b (0) + %r15: 10000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4842 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435465 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1d (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006b (0) + %r15: 10000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4843 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4844 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4845 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4846 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4847 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4848 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a1d, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1d (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 10000009 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4849 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1d (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000a (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4850 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1e (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000a (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4851 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=1000000a, re=65, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000009 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1e (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000a (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4852 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435466 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1e (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000a (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4853 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4854 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4855 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4856 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4857 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4858 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a1e, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1e (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000072 (0) + %r15: 1000000a (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4859 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1e (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000072 (0) + %r15: 1000000b (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4860 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1f (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000072 (0) + %r15: 1000000b (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4861 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=1000000b, re=72, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1000000a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1f (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000072 (0) + %r15: 1000000b (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4862 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435467 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1f (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000072 (0) + %r15: 1000000b (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4863 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4864 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4865 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4866 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4867 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4868 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a1f, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1f (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 1000000b (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4869 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a1f (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 1000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4870 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a20 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 1000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4871 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=1000000c, re=6e, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1000000b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a20 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 1000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4872 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435468 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a20 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 1000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4873 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4874 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4875 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4876 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4877 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4878 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a20, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a20 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000c (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4879 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a20 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4880 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a21 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4881 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=1000000d, re=65, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1000000c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a21 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4882 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435469 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a21 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 1000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4883 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4884 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4885 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4886 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4887 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4888 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a21, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a21 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006c (0) + %r15: 1000000d (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4889 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a21 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006c (0) + %r15: 1000000e (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4890 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a22 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006c (0) + %r15: 1000000e (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4891 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=1000000e, re=6c, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1000000d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a22 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006c (0) + %r15: 1000000e (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4892 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435470 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a22 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006c (0) + %r15: 1000000e (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4893 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4894 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4895 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4896 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4897 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4898 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a22, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a22 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000020 (0) + %r15: 1000000e (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4899 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a22 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000020 (0) + %r15: 1000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4900 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a23 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000020 (0) + %r15: 1000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4901 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=1000000f, re=20, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1000000e +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a23 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000020 (0) + %r15: 1000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4902 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435471 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a23 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000020 (0) + %r15: 1000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4903 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4904 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4905 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4906 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4907 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4908 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a23, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a20 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a23 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000064 (0) + %r15: 1000000f (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4909 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a23 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000064 (0) + %r15: 10000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4910 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a24 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000064 (0) + %r15: 10000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4911 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000010, re=64, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 1000000f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a24 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000064 (0) + %r15: 10000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4912 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435472 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a24 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000064 (0) + %r15: 10000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4913 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4914 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4915 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4916 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4917 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4918 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a24, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a24 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006f (0) + %r15: 10000010 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4919 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a24 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006f (0) + %r15: 10000011 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4920 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a25 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006f (0) + %r15: 10000011 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4921 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000011, re=6f, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a25 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006f (0) + %r15: 10000011 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4922 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435473 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a25 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006f (0) + %r15: 10000011 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4923 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4924 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4925 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4926 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4927 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4928 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a25, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a25 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 10000011 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4929 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a25 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 10000012 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4930 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a26 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 10000012 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4931 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000012, re=6e, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000011 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a26 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 10000012 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4932 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435474 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a26 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000006e (0) + %r15: 10000012 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4933 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4934 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4935 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4936 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4937 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4938 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a26, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a26 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 10000012 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4939 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a26 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 10000013 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4940 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a27 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 10000013 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4941 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000013, re=65, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000012 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a27 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 10000013 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4942 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435475 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a27 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 00000065 (0) + %r15: 10000013 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4943 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4944 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4945 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4946 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4947 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4948 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a27, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a24 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a27 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000002e (0) + %r15: 10000013 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4949 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a27 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000002e (0) + %r15: 10000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4950 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a28 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000002e (0) + %r15: 10000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4951 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000014, re=2e, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000013 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a28 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000002e (0) + %r15: 10000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4952 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435476 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a28 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000002e (0) + %r15: 10000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4953 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4954 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4955 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4956 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4957 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4958 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5c703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5c703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80014a28, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80014a28 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a28 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 10000014 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4959 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a28 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 10000015 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4960 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 158593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x158593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 10000015 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4961 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fee78fa3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfee78fa3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=10000015, re=a, imm=4294967295 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000014 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 10000015 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4962 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fed798e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfed798e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435477 rsrc1 : 268435477 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 10000015 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4963 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4964 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4965 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4966 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4967 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4968 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000e1f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000e1f8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000de4c, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000de4c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 10000015 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000e1f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4969 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4970 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4971 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4972 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4973 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4974 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 842783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x842783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de4c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 0000000d (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4975 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 42603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x42603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 10000008 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 80014a1c (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4976 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b8913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb8913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de54: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 10000008 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4977 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 417787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x417787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de58: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 10000008 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4978 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1760633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1760633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de5c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4979 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de60: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=fffffff3, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4980 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c42023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc42023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de64: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rc=10000015, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4981 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e49ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe49ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de68: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dcb0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 0000000d (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4982 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4983 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4984 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4985 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4986 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4987 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcb0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412b0b33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412b0b33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcb0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 10000008 (0) + %r11: 80014a29 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcb0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 22 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4988 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcb4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcb4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000001 (0) + %r11: 80014a29 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcb4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4989 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcb8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 160b0a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x160b0a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcb8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000de2c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000001 (0) + %r11: 80014a29 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcb8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4990 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4991 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4992 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4993 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4994 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4995 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000001 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4996 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a8513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa8513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de4c (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4997 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a24f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa24f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de34: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004058 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4998 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 4999 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5000 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5001 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5002 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5003 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004058 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004058: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004058 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5004 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000405c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000405c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r8=80016364, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000405c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5005 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004060 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004060: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r1=8000de38, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004060 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5006 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004064 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004064: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5007 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004064 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5008 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004068 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004068: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: fffffff3 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004068 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5009 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5010 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5011 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5012 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5013 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5014 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000406c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3852783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3852783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000406c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00000001 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000406c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5015 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004070 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2078063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2078063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004070: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00000001 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004070 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5016 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5017 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5018 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5019 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5020 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5021 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5022 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004074 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004074: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004074 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5023 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004078 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2079663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2079663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004078: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 10377 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800040a4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004078 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5024 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5025 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5026 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5027 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5028 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5029 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5030 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5031 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040a8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5032 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040ac: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000de38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5033 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040b0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5034 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d49ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd49ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040b4: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003dfc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5035 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5036 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5037 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5038 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5039 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5040 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003dfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003dfc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5041 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e00: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5042 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5043 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5044 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5045 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e04: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r8=80016364, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5046 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e08: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r13=d, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed2c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5047 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e0c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r1=8000de38, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5048 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5049 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e10: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r9=6fffeeb4, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed34 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5050 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e14: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed20, r12=d, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed30 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 10000015 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5051 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 87f693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x87f693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5052 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5053 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e20: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5054 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10069a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10069a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e24: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 8 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f38 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 0000000d (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5055 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5056 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5057 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5058 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5059 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5060 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 105a903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x105a903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f38: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5061 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5062 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5063 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5064 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fc090ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfc090ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f3c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5065 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5066 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5067 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5068 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5069 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5070 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5071 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5a483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5a483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f40: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000015 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000015 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 0000000a (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5072 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5073 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5074 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5075 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1079713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1079713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000015 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 28890000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5076 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1075713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1075713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000015 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5077 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 377713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x377713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000015 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5078 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 125a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x125a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f50: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r11=80016364, r12=10000008, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000015 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5079 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5080 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412484b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412484b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f54: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5081 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5082 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5083 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 71463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x71463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f5c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f64 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5084 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5085 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5086 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5087 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5088 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5089 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f64: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5090 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 904863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x904863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f68: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f78 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5091 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5092 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5093 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5094 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5095 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5096 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2442783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2442783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f78: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016388 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80009344 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5097 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c42583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c42583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f7c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016380 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5098 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f80: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000015 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5099 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5100 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5101 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5102 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f84: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5103 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f88: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5104 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f8c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80009344, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80009344 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 80009344 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5105 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5106 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5107 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5108 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5109 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5110 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009344 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009344: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009344 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5111 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009344 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5112 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009344 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5113 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009344 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5114 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009348 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009348: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009348 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5115 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000934c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000934c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r8=80016364, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed18 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000934c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5116 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009350 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009350: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r9=d, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009350 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5117 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009354 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009354: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r12=10000008, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed10 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009354 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5118 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009354 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5119 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009358 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009358: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r13=80016010, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009358 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5120 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000935c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000935c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r1=80003f90, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000935c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5121 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009360 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1007f713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1007f713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009360: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009360 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5122 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009364 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009364: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009364 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5123 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009368 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009368: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009368 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5124 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000936c +DEBUG ../../../simX/enc.cpp:105: Curr Code: e59583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe59583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000936c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000936c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5125 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009370 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009370: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009370 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5126 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009374 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009374: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009374 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5127 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009378 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2071e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2071e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009378: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009378 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5128 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5129 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5130 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5131 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5132 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5133 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000937c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fffff737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfffff737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000937c: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: fffff000 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000937c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5134 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009380 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff70713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff70713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009380: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009380 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5135 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009384 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7f7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7f7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009384: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009384 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5136 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009388 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f41623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf41623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009388: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=2889, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009388 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5137 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009388 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5138 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000938c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000938c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed18 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000938c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5139 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000938c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5140 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009390 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009390: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80003f90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009390 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5141 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009390 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5142 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009394 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 98693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x98693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009394: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009394 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 19 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5143 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009398 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009398: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009398 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5144 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000939c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000939c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000939c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5145 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed10 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5146 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5147 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093a8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5148 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093ac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5149 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800093b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a80406f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa80406f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800093b0: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d458 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800093b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5150 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5151 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5152 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5153 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5154 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5155 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d458 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d458: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: ffffefff (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d458 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5156 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d45c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d45c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d45c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5157 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d460 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d460: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed10, r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed18 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d460 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5158 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d464 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d464: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed10, r9=d, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d464 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5159 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d468 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d468: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d468 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5160 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d46c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d46c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 10000008 (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d46c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5161 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d470 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 68613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x68613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d470: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d470 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5162 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d474 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 70513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x70513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d474: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d474 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5163 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d478 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d478: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed10, r1=80003f90, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d478 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5164 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d47c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d47c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d47c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5165 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d480 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 858f30ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x858f30ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d480: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800004d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d480 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5166 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d480 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5167 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d480 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5168 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d480 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5169 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5170 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5171 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5172 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5173 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5174 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004d8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5175 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5176 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5177 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5178 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004dc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r8=80016010, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed08 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5179 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 710007b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x710007b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004e0: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 71000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5180 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004e4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffed00, r1=8000d484, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 71000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5181 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5182 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 60413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x60413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000001 (0) + %r15: 71000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5183 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 400713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x400713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004ec: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000003 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5184 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 500313 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x500313 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004f0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: fefefeff (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 6 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5185 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1078813 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1078813 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5186 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004f8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, re=4, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5187 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800004fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 678223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x678223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800004fc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, r6=5, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000004 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800004fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 6 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5188 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000500 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 782a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x782a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000500: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, r0=0, imm=5 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000005 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5189 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5190 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5191 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000500 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5192 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000504 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 878823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x878823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000504: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, r8=d, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 0a0a0a0a (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000504 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5193 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000508 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 865893 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x865893 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000508: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 0000000d (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000508 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 17 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5194 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000050c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1845693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1845693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000050c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000050c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5195 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000510 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1065613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1065613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000510: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000510 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5196 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000514 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 11800a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x11800a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000514: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r16=71000010, r11=0, imm=1 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000011 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000514 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 17 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5197 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000518 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c80123 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc80123 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000518: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r16=71000010, rc=0, imm=2 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000012 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000518 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5198 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000051c +DEBUG ../../../simX/enc.cpp:105: Curr Code: d801a3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd801a3 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000051c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r16=71000010, rd=0, imm=3 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000013 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000051c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5199 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000520 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 79323 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x79323 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000520: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, r0=0, imm=6 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000006 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000520 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5200 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000524 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000524: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, re=4, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000524 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5201 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000528 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a7a623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa7a623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000528: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r15=71000000, ra=1, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 7100000c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000528 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5202 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000052c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a805263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa805263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000052c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 00000000 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000052c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5203 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5204 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5205 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5206 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5207 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5208 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000530 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1478693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1478693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000530: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 71000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000530 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5209 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000534 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1878793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1878793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000534: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 71000018 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000534 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5210 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000538 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f5b7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf5b7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000538: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000538 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5211 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000053c +DEBUG ../../../simX/enc.cpp:105: Curr Code: b83533 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb83533 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000053c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000053c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 16 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5212 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000540 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff40613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff40613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000540: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000c (0) + %r13: 71000014 (0) + %r14: 00000004 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000540 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5213 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000540 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5214 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000540 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5215 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000540 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5216 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000544 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17c713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17c713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000544: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000c (0) + %r13: 71000014 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000544 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5217 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000548 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 963613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x963613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000548: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000548 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5218 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000054c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 154793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x154793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000054c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000054c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5219 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000550 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f767b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf767b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000550: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000550 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5220 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000554 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 164713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x164713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000554: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000554 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5221 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000558 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f777b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf777b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000558: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000558 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5222 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000558 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5223 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000055c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8078863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8078863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000055c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000001 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000055c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5224 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5225 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5226 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5227 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5228 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5229 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5230 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5231 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000560 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b6e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb6e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000560: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 7100001c (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000560 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 13 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5232 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000564 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 37f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x37f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000564: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000564 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5233 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000568 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8079263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8079263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000568: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5234 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5235 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5236 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5237 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5238 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5239 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5240 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5241 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000056c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc47513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc47513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000056c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 0000000c (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000056c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5242 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000570 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b50533 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb50533 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000570: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000570 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 10 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5243 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000574 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000574: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 10000008 (0) + %r16: 71000010 (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000574 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5244 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000578 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40b68833 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40b68833 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000578: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 00000000 (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 10000008 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000578 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 13 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5245 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000578 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 13 rs2: 11 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5246 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000057c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000057c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=10000008, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000008 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6e72656b +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 00000001 (0) + %r15: 10000008 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000057c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5247 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000580: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 10000008 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5248 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000584: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5249 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000588: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=71000014, rc=6e72656b, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000014 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5250 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000058c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fef518e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfef518e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000058c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435476 rsrc1 : 268435468 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000057c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 6e72656b (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000058c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5251 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5252 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5253 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5254 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5255 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5256 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000057c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000057c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=1000000c, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1000000c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 64206c65 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 64206c65 (0) + %r13: 71000014 (0) + %r14: 71000014 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000057c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5257 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000580: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 64206c65 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 1000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5258 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000584: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 64206c65 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5259 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000588: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=71000018, rc=64206c65, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000018 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 64206c65 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5260 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000058c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fef518e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfef518e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000058c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435476 rsrc1 : 268435472 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000057c +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 64206c65 (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000058c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5261 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5262 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5263 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5264 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5265 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5266 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000057c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7a603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7a603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000057c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r15=10000010, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000010 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 2e656e6f +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000014 (0) + %r14: 71000018 (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000057c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5267 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f80733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf80733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000580: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000010 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 16 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5268 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000584: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5269 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000588: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=7100001c, rc=2e656e6f, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 7100001c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5270 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000058c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fef518e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfef518e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000058c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 268435476 rsrc1 : 268435476 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 10000014 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000058c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5271 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5272 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5273 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5274 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5275 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5276 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000590 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc47793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc47793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000590: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000014 (0) + %r14: 7100001c (0) + %r15: 0000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000590 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5277 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000594 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f686b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf686b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000594: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000020 (0) + %r14: 7100001c (0) + %r15: 0000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000594 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5278 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000598 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2f40c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2f40c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000598: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000020 (0) + %r14: 7100001c (0) + %r15: 0000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000598 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5279 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5280 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5281 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5282 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5283 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5284 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5285 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000059c +DEBUG ../../../simX/enc.cpp:105: Curr Code: f58733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf58733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000059c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 2e656e6f (0) + %r13: 71000020 (0) + %r14: 10000014 (0) + %r15: 0000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000059c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5286 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 74603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x74603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r14=10000014, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000014 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 676e690a +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 10000014 (0) + %r15: 0000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5287 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 178713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x178713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 0000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5288 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c68023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc68023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005a8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r13=71000020, rc=a, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 71000020 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 0000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5289 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5290 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2875263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2875263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005ac: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800005d0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 0000000c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5291 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5292 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5293 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5294 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5295 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5296 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c81a783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c81a783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005d0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=456 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169d0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 70000000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5297 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005d4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=70000000, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 70000000 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800005d8 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5298 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5299 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5300 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5301 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5302 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5303 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5304 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x70000000 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x70000000: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +kernel done. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800005d8, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800005d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800005d8 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 70000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5305 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 70000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5306 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 70000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5307 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 70000000 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5308 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5309 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5310 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5311 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5312 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5313 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed0c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d484 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 10000014 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5314 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005dc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 0000000d (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5315 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005e0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed00, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed08 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed00 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5316 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005e4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5317 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800005e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800005e8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d484, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d484 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 70000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800005e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5318 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5319 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5320 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5321 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5322 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5323 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d484 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d484: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d484 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5324 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d488 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d488: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d484 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d488 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5325 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5326 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5327 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5328 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5329 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5330 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5331 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d48c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d48c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed10, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed1c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80003f90 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d48c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5332 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d490 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d490: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed10, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed18 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d490 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5333 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d494 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d494: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed10, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed14 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed10 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d494 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5334 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d498 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d498: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d498 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5335 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d49c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d49c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80003f90, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f90 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d49c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5336 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5337 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5338 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5339 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5340 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5341 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f90 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40a484b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40a484b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f90: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f90 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5342 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fca04ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfca04ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f94: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f70 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5343 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5344 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5345 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5346 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5347 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5348 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: a90933 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa90933 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f70: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000015 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 18 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5349 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa9052e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa9052e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f74: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000015 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5350 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5351 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5352 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5353 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5354 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5355 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003f90 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000015 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5356 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f1c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed3c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000de38 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000015 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5357 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f20: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed38 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000015 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5358 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f24: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed34 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffeeb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000015 (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5359 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f28: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed30 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 0000000d (0) + %r19: 80016010 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5360 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f2c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed20, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed2c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed20 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5361 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5362 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f34: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000de38, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000de38 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5363 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5364 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5365 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5366 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5367 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5368 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000de38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e80502e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe80502e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000de38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000dcbc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000a (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000de38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5369 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5370 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5371 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5372 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5373 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5374 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8a2603 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8a2603 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcbc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r20=6fffee84, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a1c (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5375 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcc0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12c0c33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12c0c33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcc0: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 0000000d (0) + %r19: 0000000d (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 24 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5376 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 24 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5377 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 24 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5378 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 24 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5379 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412989b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412989b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcc4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 0000000d (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 19 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5380 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41260933 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41260933 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcc8: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 12 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5381 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dccc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12a2423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12a2423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dccc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r20=6fffee84, r12=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dccc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 20 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5382 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcd0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8091a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8091a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcd0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcd0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5383 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5384 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5385 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5386 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5387 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5388 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5389 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcd4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcd4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000de38 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcd4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5390 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcd8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcd8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed6c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000c120 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcd8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5391 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcdc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcdc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=40 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed68 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a29 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 6fffeeb4 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5392 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dce0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dce0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed64 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dce0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5393 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dce4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dce4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=32 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed60 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dce4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5394 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dce8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dce8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed5c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 6fffee84 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dce8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5395 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcec: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed58 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5396 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcf0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcf0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed54 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcf0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5397 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcf4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcf4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed50 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 6fffee84 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 0000000d (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcf4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5398 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcf8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcf8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed4c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80014a29 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcf8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5399 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dcfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dcfc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed48 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dcfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5400 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412c83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412c83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd00: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed44 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5401 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5402 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5403 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5404 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12d03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12d03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd04: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed40, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed40 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed40 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 26 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5405 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd08: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5406 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000dd0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000dd0c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000c120, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c120 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000dd0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5407 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5408 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5409 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5410 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5411 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5412 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c120 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa5ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa5ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c120: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000c0c4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000c120 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c120 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5413 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5414 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5415 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5416 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5417 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5418 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0c4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0c4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed9c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80002e14 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0c4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5419 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0c8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0c8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=40 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed98 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a29 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0c8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5420 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0cc +DEBUG ../../../simX/enc.cpp:105: Curr Code: b2423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb2423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0cc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r22=6fffee84, r0=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee8c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0cc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5421 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0d0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b2223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb2223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0d0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r22=6fffee84, r0=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffee88 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0d0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5422 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0d4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0d4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed94 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0d4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5423 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=32 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed90 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5424 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0dc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5425 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0e0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed88 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5426 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed84 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 6fffee84 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5427 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0e8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed80 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80014a1c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5428 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0ec: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed7c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5429 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0f0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffed70, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffed78 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffed70 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5430 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0f4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5431 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000c0f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000c0f8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80002e14, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80002e14 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000c0f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5432 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5433 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5434 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5435 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5436 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5437 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80002e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cd0fe06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcd0fe06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80002e14: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800012e4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5438 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5439 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5440 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80002e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5441 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5442 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5443 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5444 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5445 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5446 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: cc5783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xcc5783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012e4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r24=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 24 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5447 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 407f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x407f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5448 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012ec: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800012f4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80002e14 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5449 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5450 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5451 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5452 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5453 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5454 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5455 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5456 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1ec12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1ec12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012f4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=492 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef8c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000f74 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80014a29 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5457 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012f8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=488 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef88 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 0000000d (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5458 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800012fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800012fc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffedac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: d +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 0000000d (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800012fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5459 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001300 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001300: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=484 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef84 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 80014a1c (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001300 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5460 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001304 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001304: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=480 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef80 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001304 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5461 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001308 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1dc12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1dc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001308: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=476 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef7c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001308 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5462 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000130c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000130c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=472 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef78 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000130c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5463 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001310 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001310: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=468 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef74 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 80014a1c (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001310 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5464 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001314 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1d012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1d012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001314: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=464 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef70 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001314 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5465 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001318 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1cc12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1cc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001318: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=460 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef6c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 80016364 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001318 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5466 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000131c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c812c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c812c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000131c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=456 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef68 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000131c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5467 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001320 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c412c83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c412c83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001320: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=452 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef64 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 80016010 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001320 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 25 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5468 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001324 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c012d03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c012d03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001324: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=448 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef60 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001324 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 26 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5469 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001328 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1bc12d83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1bc12d83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001328: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffeda0, imm=444 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef5c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffeda0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001328 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 27 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5470 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000132c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1f010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1f010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000132c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000132c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5471 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80001330 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80001330: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000f74, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000f74 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000f74 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80001330 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5472 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5473 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5474 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5475 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5476 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5477 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800000ac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5478 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5479 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5480 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5481 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f78: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5482 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000f7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000f7c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=800000ac, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800000ac +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 800000ac (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000f7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5483 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5484 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5485 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5486 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5487 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5488 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000ac: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefd0, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffeffc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000044 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 0000000d (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5489 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5490 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5491 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5492 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000b0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffefd0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5493 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5494 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800000b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800000b8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000044, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000044 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800000b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5495 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5496 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5497 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5498 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5499 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5500 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000044 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4ad0006f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4ad0006f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000044: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000cf0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6ffff000 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000044 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5501 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000044 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5502 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000044 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5503 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000044 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5504 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5505 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5506 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5507 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5508 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5509 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cf0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cf0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cf0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5510 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cf0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5511 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cf0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5512 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cf0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5513 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cf4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cf4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cf4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5514 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cf8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cf8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeff0, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeff8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cf8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5515 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000cfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000cfc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffeff0, r1=80000044, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffeffc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000cfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5516 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d00: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000044 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5517 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5518 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5519 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5520 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 7d9020ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x7d9020ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d04: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003cdc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5521 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5522 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5523 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5524 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5525 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5526 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003cdc +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003cdc: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5527 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5528 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5529 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cdc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5530 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ce0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ce0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r14=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefd8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ce0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5531 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ce4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c01aa03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c01aa03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ce4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=448 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169c8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ce4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5532 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003ce8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003ce8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r12=0, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ce8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5533 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003ce8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5534 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003cec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003cec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r1=80000d08, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5535 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003cf0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 148a2903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x148a2903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003cf0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r20=80016010, imm=328 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016158 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8001615c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cf0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5536 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003cf4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003cf4: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r8=0, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cf4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5537 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003cf8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003cf8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r9=0, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cf8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5538 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003cfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003cfc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r13=0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003cfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5539 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d00: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r15=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefd4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5540 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5541 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5542 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5543 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d04: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r16=0, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefd0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5544 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d08: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r17=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefcc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5545 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d0c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r18=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefc8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5546 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4090063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4090063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d10: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5547 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5548 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5549 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5550 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5551 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5552 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50b13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d14: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5553 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58b93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58b93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5554 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100a93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100a93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5555 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d20: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5556 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 492483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x492483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d24: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=8001615c, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016160 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5557 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff48413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff48413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d28: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5558 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2044263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2044263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d2c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5559 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5560 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5561 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5562 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5563 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5564 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5565 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5566 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 249493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x249493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000004 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5567 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 9904b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x9904b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d34: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 18 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5568 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40b8463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40b8463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d38: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003d80 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 23 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5569 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5570 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5571 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5572 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5573 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5574 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5575 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d80 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 492783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x492783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d80: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=8001615c, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016160 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 71000020 (0) + %r14: 0000000d (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5576 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5577 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5578 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d80 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5579 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d84 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 44a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x44a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d84: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r9=80016160, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016164 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000d20 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 0000000d (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d84 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5580 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d88 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff78793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff78793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d88: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d88 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5581 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d8c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4878e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4878e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d8c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003de8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d8c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5582 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5583 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5584 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5585 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5586 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5587 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5588 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003de8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 892223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x892223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003de8: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r18=8001615c, r8=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016160 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003de8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5589 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003dec +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa9ff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa9ff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003dec: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003d94 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5590 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5591 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5592 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5593 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5594 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5595 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d94 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fa0688e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfa0688e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d94: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d94 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5596 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5597 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5598 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5599 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5600 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5601 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d98 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 18892783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x18892783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d98: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=8001615c, imm=392 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800162e4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 0000000d (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d98 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5602 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d9c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8a9733 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8a9733 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d9c: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d9c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 21 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5603 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003da0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 492c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x492c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003da0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=8001615c, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016160 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003da0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5604 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003da4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f777b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf777b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003da4: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003da4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5605 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003da8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2079263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2079263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003da8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003da8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5606 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5607 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5608 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5609 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5610 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5611 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5612 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003dac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 680e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x680e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003dac: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r13=80000d20, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000d20 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5613 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5614 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5615 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5616 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5617 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5618 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d20: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5619 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5620 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5621 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5622 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d24: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r8=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5623 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 800167b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x800167b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d28: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5624 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80016437 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80016437 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d2c: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5625 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5626 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 440413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x440413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 80016000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5627 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 478793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x478793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d34: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 80016004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5628 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 408787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x408787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d38: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5629 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5630 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d3c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r9=80016160, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5631 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d40: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r1=80003db0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5632 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5633 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5634 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5635 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4027d493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4027d493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5636 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2048063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2048063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d48: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000d68 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5637 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5638 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5639 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5640 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5641 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5642 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5643 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d68: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80003db0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016004 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5644 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d6c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5645 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d70: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016160 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5646 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d74: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5647 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d78: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80003db0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003db0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5648 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5649 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5650 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5651 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5652 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5653 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003db0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 492703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x492703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003db0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r18=8001615c, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016160 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003db0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5654 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003db4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 148a2783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x148a2783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003db4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r20=80016010, imm=328 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016158 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8001615c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003db4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5655 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003db8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1871463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1871463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003db8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003db8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 24 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5656 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5657 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5658 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5659 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5660 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5661 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003dbc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f8f904e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf8f904e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003dbc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003d44 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dbc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5662 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5663 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5664 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5665 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5666 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5667 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff40413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff40413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: ffffffff (0) + %r 9: 80016160 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5668 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5669 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5670 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5671 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc48493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc48493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: ffffffff (0) + %r 9: 8001615c (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5672 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff3416e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff3416e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d4c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 4294967295 rsrc1 : 4294967295 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80003db0 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: ffffffff (0) + %r 9: 8001615c (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5673 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5674 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5675 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5676 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5677 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5678 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d50: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000d08 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: ffffffff (0) + %r 9: 8001615c (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5679 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d54: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=40 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 8001615c (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5680 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d58: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 8001615c (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5681 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d5c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=32 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: ffffffff (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5682 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d60 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d60: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 80016010 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d60 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5683 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d64: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefd8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000001 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5684 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d68: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefd4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5685 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d6c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefd0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5686 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d70 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d70: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefcc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d70 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5687 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d74 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d74: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefc8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d74 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 24 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5688 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d78 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d78: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d78 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5689 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003d7c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003d7c: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000d08, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000d08 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003d7c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5690 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5691 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5692 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5693 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5694 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5695 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c01a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c01a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d08: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=448 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169c8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 8001615c (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5696 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3c52783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3c52783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d0c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016010, imm=60 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001604c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800040e0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5697 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d10: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d08 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5698 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5699 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5700 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5701 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5702 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5703 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5704 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5705 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d14: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=800040e0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 800040e0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5706 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5707 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5708 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5709 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5710 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5711 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8000d5b7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8000d5b7 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040e0: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d000 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5712 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5713 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5714 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5715 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 63458593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x63458593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040e4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5716 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800040e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 210006f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x210006f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800040e8: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004908 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800040e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5717 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5718 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5719 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5720 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5721 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5722 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5723 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004908 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004908: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004908 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5724 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004908 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5725 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004908 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5726 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004908 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5727 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000490c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000490c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r12=0, imm=32 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000490c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5728 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004910 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004910: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r13=0, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004910 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5729 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004914 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004914: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r14=0, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefd8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004914 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5730 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004914 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 20 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5731 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004918 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1512a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1512a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004918: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r15=0, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefd4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004918 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 21 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5732 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000491c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1612823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1612823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000491c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r16=0, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefd0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000491c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 22 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5733 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004920 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1712623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1712623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004920: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r17=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefcc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004920 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 23 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5734 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004924 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004924: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r1=80000d18, imm=44 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004924 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5735 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004928 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004928: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r8=0, imm=40 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004928 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5736 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000492c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000492c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefc0, r9=0, imm=36 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000492c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5737 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004930 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50a93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50a93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004930: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004930 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5738 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004934 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58b93 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58b93 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004934: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004934 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5739 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004938 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2e050b13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2e050b13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004938: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004938 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5740 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000493c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a13 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa13 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000493c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000493c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5741 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004940 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 100993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x100993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004940: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004940 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5742 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004940 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5743 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004940 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5744 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004940 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5745 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004944 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004944: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004944 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5746 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004948 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4b2483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4b2483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004948: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r22=800162f0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800162f4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 3 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000003 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004948 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5747 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000494c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8b2403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8b2403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000494c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r22=800162f0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800162f8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800162fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000003 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000494c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5748 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004950 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff48493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff48493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004950: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000002 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004950 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5749 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004954 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 204c863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x204c863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004954: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000002 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 800040e0 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004954 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5750 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5751 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5752 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5753 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5754 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5755 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5756 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004958 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c45783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc45783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004958: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800162fc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000002 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004958 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5757 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000495c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff48493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff48493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000495c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000495c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5758 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004960 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f9fe63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf9fe63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004960: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004960 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 19 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5759 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5760 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5761 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5762 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5763 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5764 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004964 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e41783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe41783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004964: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800162fc, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 8000d634 (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004964 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5765 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004968 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004968: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004968 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5766 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000496c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a8513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa8513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000496c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000496c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5767 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004970 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1278663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1278663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004970: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004970 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5768 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5769 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5770 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5771 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5772 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5773 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004974 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b80e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb80e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004974: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r23=8000d634, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d634 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004974 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5774 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5775 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5776 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5777 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5778 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5779 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d634 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d634: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5780 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5781 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5782 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5783 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d638 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d638: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r1=80004978, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d638 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5784 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d63c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d63c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r8=800162fc, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d63c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5785 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d640 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d640: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r9=1, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5786 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5787 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5788 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5789 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d644 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d644: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r12=ffffffff, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d644 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5790 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d648 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2058063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2058063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d648: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d648 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5791 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5792 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5793 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5794 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5795 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5796 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d64c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d64c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d64c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5797 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d650 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d650: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d650 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5798 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d654 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d654: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d654 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5799 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5800 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5801 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5802 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5803 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5804 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d658 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3852783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3852783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d658: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d658 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5805 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d65c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a078c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa078c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d65c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d65c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5806 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5807 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5808 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5809 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5810 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5811 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5812 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d660 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c41783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc41783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d660: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800162fc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d660 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5813 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d664 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2079263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2079263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d664: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 4 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d688 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d664 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5814 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5815 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5816 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5817 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5818 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5819 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5820 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d688 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d688: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d688 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5821 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d688 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5822 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d688 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5823 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d688 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5824 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d68c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d68c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d68c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5825 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d690 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f6cf60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf6cf60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d690: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003dfc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d690 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5826 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5827 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5828 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5829 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5830 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5831 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003dfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003dfc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=800162fc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5832 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e00: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5833 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5834 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5835 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5836 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e04: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r8=800162fc, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5837 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e08: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r13=1, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5838 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e0c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r1=8000d694, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5839 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5840 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e10: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r9=80016010, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5841 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e14: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r12=ffffffff, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 80000d20 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5842 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 87f693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x87f693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5843 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5844 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e20: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5845 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10069a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10069a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e24: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5846 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5847 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5848 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5849 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5850 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5851 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e28: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00001000 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5852 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5853 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 45a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x45a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e30: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=800162fc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016300 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000004 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5854 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e34: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5855 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5856 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f59623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf59623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r11=800162fc, rf=804, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5857 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 18d05463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x18d05463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e3c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003fc4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5858 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5859 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5860 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5861 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5862 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5863 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5864 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003fc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3c5a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3c5a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003fc4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=800162fc, imm=60 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016338 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5865 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5866 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5867 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5868 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003fc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e6e04ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe6e04ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003fc8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5869 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5870 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5871 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5872 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5873 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5874 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5875 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003fcc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f4dff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf4dff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003fcc: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fcc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5876 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5877 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5878 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5879 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5880 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5881 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5882 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f1c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d694 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5883 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f20: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800162fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5884 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f24: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5885 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f28: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5886 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f2c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef9c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5887 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5888 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f34: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d694, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d694 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5889 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5890 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5891 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5892 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5893 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5894 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d694 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c42783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c42783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d694: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800162fc, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016328 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80009434 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d694 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5895 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d698 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d698: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d698 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5896 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d69c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d69c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d69c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5897 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5898 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5899 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5900 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5901 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5902 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c42583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c42583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800162fc, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016318 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800162fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5903 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5904 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80009434, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80009434 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800162fc (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5905 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5906 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5907 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5908 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5909 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5910 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009434 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e59583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe59583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009434: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=800162fc, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 804 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5911 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5912 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5913 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5914 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009438 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a00406f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a00406f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009438: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009438 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5915 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5916 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5917 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5918 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5919 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5920 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5d8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5921 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5922 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5923 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5924 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5dc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r8=800162fc, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5925 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r9=80016010, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5926 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5927 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5928 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5929 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5ec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r1=8000d6ac, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5930 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5931 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d31f20ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd31f20ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f4: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000324 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5932 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5933 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5934 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5935 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5936 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5937 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000324 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000324: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d5f8, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d5f8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000324 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5938 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000324 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5939 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000324 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5940 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000324 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5941 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5942 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5943 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5944 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5945 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5946 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5947 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5fc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5948 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5949 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5950 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5951 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5952 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5953 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5954 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d600 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d600: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d6ac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d600 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5955 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d604 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d604: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800162fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d604 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5956 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d608 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d608: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d608 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5957 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d60c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d60c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d60c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5958 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d610 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d610: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6ac, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6ac +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d610 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5959 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5960 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5961 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5962 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5963 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5964 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6054c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6054c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6ac: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5965 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5966 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5967 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5968 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5969 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5970 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c45783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc45783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800162fc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 804 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000804 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5971 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 807f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x807f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5972 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6079e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6079e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5973 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5974 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5975 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5976 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5977 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5978 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5979 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5980 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3042583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3042583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800162fc, imm=48 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 8001632c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5981 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6c0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5982 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5983 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5984 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5985 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5986 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5987 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5988 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5989 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5990 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4442583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4442583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800162fc, imm=68 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016340 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5991 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6dc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6ec +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5992 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5993 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5994 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5995 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5996 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5997 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5998 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: d19f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd19f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6ec: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004404 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 5999 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6000 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6001 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6002 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6003 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6004 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004404 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004404: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6f0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6f0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6005 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6006 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6007 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6008 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6009 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6010 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6011 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6012 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6013 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800162fc, r0=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016308 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6014 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d15f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd15f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f4: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004408 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f8 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6015 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6016 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6017 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6018 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6019 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6020 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004408 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004408: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6f8, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6f8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f8 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004408 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6021 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6022 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6023 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6024 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6025 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6026 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80004978 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6027 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6fc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800162fc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6028 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d700 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d700: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6029 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6030 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6031 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6032 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d704 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d704: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d704 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6033 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d708 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d708: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d708 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6034 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d70c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d70c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d70c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6035 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d710 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d710: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80004978, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004978 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d710 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6036 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6037 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6038 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6039 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6040 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6041 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004978 +DEBUG ../../../simX/enc.cpp:105: Curr Code: aa6a33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xaa6a33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004978: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800162fc (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004978 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 20 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6042 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000497c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6840413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6840413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000497c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000497c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6043 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004980 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd249ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd249ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004980: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 4294967295 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004958 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6044 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6045 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6046 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6047 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6048 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6049 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6050 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6051 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6052 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004958 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c45783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc45783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004958: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000001 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004958 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6053 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000495c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff48493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff48493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000495c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000495c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6054 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004960 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f9fe63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf9fe63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004960: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004960 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 19 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6055 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6056 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6057 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6058 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6059 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6060 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004964 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e41783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe41783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004964: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004964 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6061 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004968 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004968: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004968 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6062 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000496c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a8513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa8513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000496c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000496c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6063 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004970 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1278663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1278663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004970: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004970 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6064 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6065 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6066 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6067 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6068 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6069 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004974 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b80e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb80e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004974: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r23=8000d634, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d634 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004974 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6070 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6071 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6072 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6073 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6074 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6075 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d634 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d634: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6076 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d638 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d638: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r1=80004978, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d638 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6077 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d63c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d63c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d63c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6078 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d640 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d640: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r9=0, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6079 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6080 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d644 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d644: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r12=ffffffff, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d644 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6081 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d648 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2058063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2058063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d648: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d648 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6082 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6083 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6084 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6085 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6086 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6087 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d64c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d64c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d64c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6088 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d650 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d650: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d650 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6089 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d654 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d654: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d654 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6090 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6091 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6092 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6093 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6094 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6095 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d658 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3852783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3852783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d658: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d658 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6096 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d65c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a078c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa078c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d65c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000001 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d65c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6097 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6098 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6099 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6100 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6101 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6102 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6103 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d660 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c41783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc41783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d660: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d660 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6104 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d664 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2079263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2079263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d664: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 10377 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d688 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d664 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6105 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6106 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6107 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6108 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6109 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6110 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6111 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d688 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d688: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d688 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6112 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d68c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d68c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d68c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6113 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d690 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f6cf60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf6cf60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d690: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003dfc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d690 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6114 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6115 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6116 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6117 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6118 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6119 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003dfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003dfc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6120 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e00: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6121 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e04: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r8=80016364, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6122 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e08: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r13=1, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6123 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e0c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r1=8000d694, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6124 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6125 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e10: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r9=80016010, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6126 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e14: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r12=ffffffff, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6127 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 87f693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x87f693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6128 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6129 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e20: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6130 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10069a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10069a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e24: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 8 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f38 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6131 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6132 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6133 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6134 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6135 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6136 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 105a903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x105a903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f38: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6137 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6138 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6139 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6140 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fc090ee3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfc090ee3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f3c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 18 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6141 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6142 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6143 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6144 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6145 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6146 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6147 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f40 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5a483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5a483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f40: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000008 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f40 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6148 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f44 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1079713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1079713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f44: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000008 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 28890000 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f44 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6149 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f48 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1075713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1075713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f48: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000008 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00002889 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f48 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6150 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f4c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 377713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x377713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f4c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000008 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f4c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6151 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f50 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 125a023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x125a023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f50: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r11=80016364, r12=10000008, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 10000008 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6152 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f50 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6153 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f54 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412484b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412484b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f54: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6154 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f54 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6155 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f58 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f58: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f58 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6156 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f5c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 71463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x71463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f5c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f64 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f5c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6157 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6158 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6159 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6160 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6161 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6162 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f64 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f42423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf42423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f64: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, rf=0, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 8001636c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f64 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6163 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f68 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 904863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x904863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f68: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f68 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6164 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6165 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6166 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6167 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6168 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6169 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f6c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fadff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfadff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f6c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f6c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6170 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6171 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6172 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6173 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6174 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6175 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6176 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f1c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d694 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6177 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f20: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6178 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f24: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 10000008 (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6179 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f28: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6180 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f2c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef9c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6181 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6182 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f34: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d694, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d694 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000000 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6183 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6184 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6185 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6186 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6187 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6188 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d694 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c42783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c42783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d694: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016390 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80009434 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d694 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6189 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d698 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d698: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d698 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6190 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d69c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d69c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d69c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6191 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6192 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6193 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6194 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6195 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6196 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c42583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c42583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016380 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6197 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6198 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80009434, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80009434 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016364 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6199 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6200 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6201 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6202 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6203 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6204 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009434 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e59583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe59583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009434: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016364, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6205 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6206 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6207 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6208 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009438 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a00406f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a00406f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009438: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009438 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6209 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6210 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6211 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6212 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6213 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6214 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5d8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6215 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5dc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6216 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r9=80016010, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6217 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6218 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6219 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6220 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5ec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r1=8000d6ac, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6221 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6222 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d31f20ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd31f20ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f4: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000324 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6223 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6224 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6225 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6226 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6227 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6228 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000324 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000324: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d5f8, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d5f8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 80009434 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000324 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6229 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6230 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6231 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6232 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6233 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6234 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6235 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5fc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6236 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6237 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6238 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6239 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6240 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6241 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6242 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d600 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d600: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d6ac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d600 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6243 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d604 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d604: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d604 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6244 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d608 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d608: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d608 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6245 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d60c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d60c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d60c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6246 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d610 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d610: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6ac, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6ac +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d610 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6247 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6248 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6249 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6250 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6251 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6252 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6054c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6054c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6ac: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: ffffffff (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6253 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6254 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6255 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6256 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6257 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6258 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c45783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc45783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 12889 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00002889 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6259 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 807f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x807f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6260 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6079e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6079e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 128 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d734 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 00000001 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6261 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6262 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6263 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6264 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6265 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6266 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6267 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6268 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d734 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1042583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1042583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d734: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016374 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000008 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 00000001 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d734 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6269 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d734 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6270 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d734 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6271 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d734 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6272 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d738 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d738: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d738 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6273 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d73c +DEBUG ../../../simX/enc.cpp:105: Curr Code: e29f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe29f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d73c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004564 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d73c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6274 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6275 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6276 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6277 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6278 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6279 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004564 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12058463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12058463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004564: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004564 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6280 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004564 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6281 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004564 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6282 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004564 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6283 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6284 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6285 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6286 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6287 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6288 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004568 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004568: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004568 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6289 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000456c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000456c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r8=80016364, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000456c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6290 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004570 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004570: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r9=80016010, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004570 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6291 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004574 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004574: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004574 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6292 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004574 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6293 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004578 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004578: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004578 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6294 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000457c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000457c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r1=8000d740, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000457c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6295 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004580 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 225030ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x225030ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004580: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007fa4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6296 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6297 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6298 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004580 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6299 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6300 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6301 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6302 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6303 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6304 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007fa4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007fa4: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80004584, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004584 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 6100000c (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6305 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6306 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6307 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6308 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6309 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6310 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6311 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6312 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6313 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004584 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc42803 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc42803 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004584: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=10000008, imm=4294967292 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 10000004 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 409 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 00000001 (0) + %r15: 00000080 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004584 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6314 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004588 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff840713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff840713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004588: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 10000000 (0) + %r15: 00000080 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004588 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6315 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000458c +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffe87793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffe87793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000458c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 0000000d (0) + %r13: 00000008 (0) + %r14: 10000000 (0) + %r15: 00000408 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000458c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 16 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6316 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004590 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f70633 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf70633 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004590: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 10000008 (0) + %r12: 10000408 (0) + %r13: 00000008 (0) + %r14: 10000000 (0) + %r15: 00000408 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004590 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 14 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6317 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004594 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c3018593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc3018593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004594: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016438 (0) + %r12: 10000408 (0) + %r13: 00000008 (0) + %r14: 10000000 (0) + %r15: 00000408 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004594 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6318 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004598 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 462683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x462683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004598: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r12=10000408, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 1000040c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: bf9 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016438 (0) + %r12: 10000408 (0) + %r13: 00000bf9 (0) + %r14: 10000000 (0) + %r15: 00000408 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004598 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6319 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004598 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 12 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6320 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000459c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 85a503 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x85a503 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000459c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=80016438, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016440 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 10000408 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 10000408 (0) + %r13: 00000bf9 (0) + %r14: 10000000 (0) + %r15: 00000408 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000459c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6321 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800045a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ffc6f693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xffc6f693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800045a0: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 10000408 (0) + %r13: 00000bf8 (0) + %r14: 10000000 (0) + %r15: 00000408 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800045a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 13 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6322 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800045a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1ac50663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1ac50663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800045a4: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004750 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 10000408 (0) + %r13: 00000bf8 (0) + %r14: 10000000 (0) + %r15: 00000408 (0) + %r16: 00000409 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800045a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6323 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800045a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6324 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800045a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6325 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6326 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6327 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6328 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6329 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6330 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004750 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 187813 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x187813 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004750: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 10000408 (0) + %r13: 00000bf8 (0) + %r14: 10000000 (0) + %r15: 00000408 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004750 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 16 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6331 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004750 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 16 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6332 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004750 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 16 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6333 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004750 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 16 rs1: 16 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6334 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004754 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d787b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd787b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004754: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 10000408 (0) + %r13: 00000bf8 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004754 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6335 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004758 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2081063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2081063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004758: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 1 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004778 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 10000408 (0) + %r13: 00000bf8 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004758 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 16 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6336 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6337 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6338 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6339 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6340 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6341 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004778 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 17e613 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x17e613 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004778: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00000bf8 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004778 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 12 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6342 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000477c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1e01a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1e01a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000477c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r3=80016808, imm=480 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800169e8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 20000 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000477c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 3 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6343 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c72223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc72223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004780: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r14=10000000, rc=1001, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 10000004 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6344 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6345 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6346 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 14 rs2: 12 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6347 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004784 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e5a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe5a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004784: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r11=80016438, re=10000000, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016440 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004784 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6348 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004788 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ead7e8e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xead7e8e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004788: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:6 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004638 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 10000008 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004788 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6349 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6350 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6351 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6352 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6353 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6354 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004638 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004638: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004584 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004638 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6355 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004638 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6356 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004638 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6357 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004638 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6358 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000463c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000463c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d740 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 10000408 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000463c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6359 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004640 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004640: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6360 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6361 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6362 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6363 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004644 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004644: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004644 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6364 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004648 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004648: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004648 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6365 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000464c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 15d0306f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x15d0306f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000464c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80007fa8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000464c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6366 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6367 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6368 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6369 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6370 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6371 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80007fa8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80007fa8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d740, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d740 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6372 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6373 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6374 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80007fa8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6375 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6376 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6377 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6378 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6379 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6380 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d740 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f7dff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf7dff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d740: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6bc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 80016438 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d740 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6381 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d740 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6382 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d740 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6383 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d740 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6384 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6385 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6386 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6387 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6388 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6389 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3042583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3042583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=48 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016394 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6390 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6c0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6391 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6392 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6393 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6394 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6395 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6396 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6397 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4442583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4442583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=80016364, imm=68 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163a8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6398 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6dc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6ec +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d740 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6399 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6400 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6401 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6402 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6403 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6404 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6405 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: d19f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd19f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6ec: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004404 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6406 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6407 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6408 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6409 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6410 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6411 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004404 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004404: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6f0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6f0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6412 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6413 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6414 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6415 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6416 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6417 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6418 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6419 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6420 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=80016364, r0=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016370 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6421 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d15f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd15f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f4: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004408 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f8 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6422 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6423 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6424 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6425 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6426 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6427 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004408 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004408: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6f8, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6f8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f8 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004408 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6428 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6429 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6430 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6431 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6432 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6433 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80004978 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6434 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6fc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016364 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6435 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d700 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d700: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 80016010 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6436 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d704 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d704: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d704 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6437 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d708 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d708: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d708 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6438 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d70c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d70c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d70c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6439 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d710 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d710: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80004978, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004978 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d710 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6440 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6441 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6442 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6443 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6444 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6445 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004978 +DEBUG ../../../simX/enc.cpp:105: Curr Code: aa6a33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xaa6a33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004978: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016364 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004978 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 20 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6446 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000497c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6840413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6840413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000497c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000497c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6447 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004980 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd249ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd249ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004980: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 4294967295 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004958 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00001000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6448 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6449 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6450 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6451 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6452 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6453 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004958 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c45783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc45783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004958: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800163cc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 20012 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004958 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6454 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000495c +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff48493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff48493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000495c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000495c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6455 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004960 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f9fe63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf9fe63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004960: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:7 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004960 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 19 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6456 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6457 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6458 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6459 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6460 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6461 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004964 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e41783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe41783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004964: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800163cc, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 20012 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004964 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6462 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004968 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004968: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004968 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6463 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000496c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a8513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa8513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000496c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000496c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 21 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6464 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004970 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1278663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1278663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004970: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004970 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6465 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6466 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6467 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6468 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6469 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6470 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004974 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b80e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb80e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004974: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r23=8000d634, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d634 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004974 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 23 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6471 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6472 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6473 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6474 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6475 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6476 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d634 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d634: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6477 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6478 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6479 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6480 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d638 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d638: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r1=80004978, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d638 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6481 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d63c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d63c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r8=800163cc, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d63c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6482 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d640 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d640: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r9=ffffffff, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6483 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6484 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6485 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d640 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6486 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d644 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212023 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212023 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d644: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefb0, r12=ffffffff, imm=0 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefb0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d644 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6487 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d648 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2058063 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2058063 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d648: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d648 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6488 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6489 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6490 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6491 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6492 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6493 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d64c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d64c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d64c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6494 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d650 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50493 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50493 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d650: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d650 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6495 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d654 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50663 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50663 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d654: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000002 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d654 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6496 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6497 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6498 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6499 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6500 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6501 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d658 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3852783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3852783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d658: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r10=80016010, imm=56 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016048 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000001 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d658 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6502 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d65c +DEBUG ../../../simX/enc.cpp:105: Curr Code: a078c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa078c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d65c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000001 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d65c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6503 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6504 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6505 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6506 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6507 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6508 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6509 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d660 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c41783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc41783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d660: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800163cc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 20012 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d660 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6510 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d664 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2079263 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2079263 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d664: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 18 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d688 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d664 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6511 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6512 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6513 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6514 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6515 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6516 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6517 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d688 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40593 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40593 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d688: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d688 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6518 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d68c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d68c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d68c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6519 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d690 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f6cf60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf6cf60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d690: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003dfc +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d690 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6520 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6521 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6522 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6523 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6524 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6525 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003dfc +DEBUG ../../../simX/enc.cpp:105: Curr Code: c59783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc59783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003dfc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=800163cc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 20012 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003dfc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6526 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e00 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fe010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfe010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e00: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6527 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6528 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6529 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e00 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6530 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e04 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812c23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812c23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e04: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r8=800163cc, imm=24 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e04 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6531 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e08 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1312623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1312623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e08: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r13=1, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffef9c +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e08 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 19 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6532 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e0c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112e23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112e23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e0c: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r1=8000d694, imm=28 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6533 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e0c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6534 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e10 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912a23 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912a23 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e10: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r9=80016010, imm=20 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e10 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6535 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e14 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1212823 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1212823 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e14: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffef90, r12=ffffffff, imm=16 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00020000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e14 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6536 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 87f693 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x87f693 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6537 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e1c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6538 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50993 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50993 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e20: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6539 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 10069a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x10069a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e24: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 10000000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 13 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6540 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6541 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6542 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6543 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6544 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6545 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1737 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1737 into: lui + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e28: lui +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:810: LUI_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00001000 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6546 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 80070713 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x80070713 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e2c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 14 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6547 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 45a683 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x45a683 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e30: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=800163cc, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163d0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000012 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 13 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6548 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e7e7b3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe7e7b3 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e34: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6549 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6550 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e38 +DEBUG ../../../simX/enc.cpp:105: Curr Code: f59623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf59623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e38: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r11=800163cc, rf=812, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e38 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6551 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003e3c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 18d05463 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x18d05463 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003e3c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:5 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003fc4 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000800 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003e3c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 13 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6552 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6553 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6554 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6555 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6556 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6557 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6558 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003fc4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3c5a703 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3c5a703 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003fc4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=800163cc, imm=60 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016408 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fc4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 14 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6559 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003fc8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e6e04ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe6e04ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003fc8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fc8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 0 rs2: 14 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6560 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6561 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6562 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6563 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6564 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6565 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6566 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6567 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6568 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003fcc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f4dff06f +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf4dff06f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003fcc: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80003f18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003fcc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6569 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6570 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6571 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6572 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6573 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6574 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6575 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6576 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6577 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6578 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f1c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d694 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6579 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f20 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f20: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800163cc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f20 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6580 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f24 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f24: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f24 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6581 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f28 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f28: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 80016010 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f28 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6582 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f2c +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f2c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffef90, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffef9c +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 1 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffef90 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f2c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6583 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f30 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f30: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f30 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6584 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80003f34 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80003f34: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d694, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d694 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80003f34 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6585 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6586 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6587 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6588 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6589 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6590 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d694 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c42783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c42783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d694: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800163cc, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163f8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80009434 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d694 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6591 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d698 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50913 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50913 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d698: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d698 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6592 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d69c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 78a63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x78a63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d69c: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d69c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6593 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6594 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6595 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6596 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6597 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6598 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c42583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c42583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800163cc, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163e8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800163cc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000000 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6599 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 48513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x48513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d694 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 9 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6600 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 780e7 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x780e7 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6a8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r15=80009434, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80009434 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 800163cc (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6601 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6602 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6603 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6604 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6605 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6606 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009434 +DEBUG ../../../simX/enc.cpp:105: Curr Code: e59583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xe59583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009434: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r11=800163cc, imm=14 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 20812 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009434 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6607 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80009438 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1a00406f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1a00406f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80009438: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80009438 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6608 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6609 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6610 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6611 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6612 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6613 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: ff010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xff010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5d8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6614 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5dc: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r8=800163cc, imm=8 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 8 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6615 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 912223 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x912223 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r9=80016010, imm=4 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 9 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6616 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 50413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x50413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 80016010 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6617 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 10 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6618 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5e8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5e8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5e8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 11 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6619 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: 112623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x112623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5ec: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r2=6fffefa0, r1=8000d6ac, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 2 rs2: 1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6620 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2401a423 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2401a423 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r3=80016808, r0=0, imm=584 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 80016a50 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 3 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6621 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d31f20ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd31f20ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f4: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000324 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6622 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6623 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6624 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6625 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6626 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6627 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000324 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000324: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d5f8, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d5f8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 80009434 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000324 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6628 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6629 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6630 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6631 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6632 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6633 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fff00793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfff00793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5f8: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6634 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d5fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: f50c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xf50c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d5fc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d5f8 (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d5fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 15 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6635 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6636 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6637 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6638 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6639 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6640 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6641 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d600 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d600: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefac +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 8000d6ac +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016010 (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d600 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6642 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d600 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6643 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d600 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6644 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d600 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6645 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d604 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d604: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800163cc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d604 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6646 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d608 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d608: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefa0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefa4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80016010 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefa0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d608 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6647 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d60c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d60c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d60c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6648 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d610 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d610: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6ac, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6ac +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d610 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6649 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6650 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6651 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6652 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6653 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6654 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6054c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6054c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6ac: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:4 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: ffffffff (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6655 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6656 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6657 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6658 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6659 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6660 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c45783 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc45783 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800163cc, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 20812 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000812 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6661 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 807f793 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x807f793 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 15 rs1: 15 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6662 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6079e63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6079e63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6b8: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000002 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 15 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6663 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6664 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6665 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6666 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6667 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6668 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6669 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6670 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6bc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3042583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3042583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6bc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800163cc, imm=48 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800163fc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6bc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6671 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6c0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58c63 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58c63 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6c0: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6d8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6c0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6672 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6673 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6674 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6675 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6676 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6677 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6678 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6d8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 4442583 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x4442583 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6d8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r8=800163cc, imm=68 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 80016410 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6d8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 11 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6679 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6dc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 58863 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x58863 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6dc: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6ec +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6ac (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6dc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 11 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6680 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6681 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6682 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6683 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6684 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6685 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6686 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6ec +DEBUG ../../../simX/enc.cpp:105: Curr Code: d19f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd19f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6ec: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004404 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6ec +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6687 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6688 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6689 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6690 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6691 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6692 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004404 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004404: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6f0, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6f0 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004404 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6693 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6694 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6695 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6696 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6697 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6698 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 41623 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x41623 into: store + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f0: store +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:715: S_INST: r8=800163cc, r0=0, imm=12 +DEBUG ../../../simX/instruction.cpp:718: STORE MEM ADDRESS: 800163d8 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f0 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 8 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 1 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6699 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: d15f60ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0xd15f60ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f4: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004408 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f8 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6700 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6701 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6702 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6703 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6704 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6705 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004408 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004408: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=8000d6f8, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 8000d6f8 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 8000d6f8 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004408 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6706 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6707 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6708 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6709 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6710 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6711 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6f8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6f8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefbc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80004978 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6f8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6712 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d6fc +DEBUG ../../../simX/enc.cpp:105: Curr Code: 812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d6fc: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=8 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 800163cc +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: 80016010 (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d6fc +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6713 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d700 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d700: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=4 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000002 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6714 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6715 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6716 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d700 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6717 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d704 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 90513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x90513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d704: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d704 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 18 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6718 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d708 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 12903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x12903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d708: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefb0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefb0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: ffffffff +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefb0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d708 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6719 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d70c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d70c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d70c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6720 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000d710 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000d710: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80004978, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80004978 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000d710 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6721 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6722 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6723 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6724 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6725 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6726 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004978 +DEBUG ../../../simX/enc.cpp:105: Curr Code: aa6a33 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xaa6a33 into: r_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004978: r_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 800163cc (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004978 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 20 rs2: 10 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6727 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000497c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 6840413 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x6840413 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000497c: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016434 (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000497c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6728 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004980 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fd249ce3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfd249ce3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004980: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 4294967295 rsrc1 : 4294967295 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016434 (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 800162f0 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004980 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 9 rs2: 18 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6729 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6730 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6731 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6732 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6733 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6734 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004984 +DEBUG ../../../simX/enc.cpp:105: Curr Code: b2b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xb2b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004984: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r22=800162f0, imm=0 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 800162f0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016434 (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004984 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 22 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6735 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004988 +DEBUG ../../../simX/enc.cpp:105: Curr Code: fc0b10e3 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xfc0b10e3 into: branch + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004988: branch +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:755: func3:1 + +DEBUG ../../../simX/instruction.cpp:768: rsrc0: 0 rsrc1 : 0 + +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80004978 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016434 (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004988 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: 22 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6736 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6737 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6738 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:610: &&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6739 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6740 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6741 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6742 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000498c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2c12083 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2c12083 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000498c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=44 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefec +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 80000d18 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 80016434 (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000498c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6743 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004990 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2812403 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2812403 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004990: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=40 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: ffffffff (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004990 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 8 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6744 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004994 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2412483 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2412483 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004994: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=36 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: ffffffff (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004994 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 9 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6745 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80004998 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 2012903 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x2012903 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80004998: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=32 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefe0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000001 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80004998 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 18 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6746 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x8000499c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1c12983 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1c12983 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x8000499c: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=28 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefdc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 80016010 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 8000499c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 19 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6747 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800049a0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1412a83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1412a83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800049a0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=20 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefd4 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800049a0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 21 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6748 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800049a4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1012b03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1012b03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800049a4: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=16 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefd0 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 8000d634 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800049a4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 22 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6749 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800049a8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: c12b83 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xc12b83 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800049a8: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=12 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefcc +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800049a8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 23 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6750 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800049ac +DEBUG ../../../simX/enc.cpp:105: Curr Code: a0513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0xa0513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800049ac: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800049ac +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 20 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6751 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800049b0 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 1812a03 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x1812a03 into: load + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800049b0: load +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:589: L_INST: r2=6fffefc0, imm=24 +DEBUG ../../../simX/instruction.cpp:597: LOAD MEM ADDRESS: 6fffefd8 +DEBUG ../../../simX/instruction.cpp:598: LOAD MEM DATA: 0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffefc0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800049b0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 20 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 1 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6752 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800049b4 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 3010113 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x3010113 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800049b4: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800049b4 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 2 rs1: 2 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6753 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x800049b8 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 8067 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x8067 into: jalr + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x800049b8: jalr +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:829: JALR_INST: r1=80000d18, imm=0 +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000d18 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 800049b8 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6754 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6755 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6756 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6757 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6758 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6759 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d18 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 40513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x40513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d18: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d18 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d18 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 8 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6760 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000d1c +DEBUG ../../../simX/enc.cpp:105: Curr Code: 915ff0ef +DEBUG ../../../simX/enc.cpp:327: Decoded 0x915ff0ef into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000d1c: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000630 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d20 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000d1c +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6761 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6762 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6763 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6764 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6765 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6766 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000630 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 513 +DEBUG ../../../simX/enc.cpp:327: Decoded 0x513 into: i_type + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000630: i_type +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d20 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000630 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6767 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000630 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6768 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000630 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6769 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000630 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 10 rs1: 0 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6770 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000634 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 14c0006f +DEBUG ../../../simX/enc.cpp:327: Decoded 0x14c0006f into: jal + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000634: jal +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:818: JAL_INST +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/instruction.cpp:2449: Next PC: 80000780 +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0: 00000000 (0) + %r 1: 80000d20 (0) + %r 2: 6fffeff0 (0) + %r 3: 80016808 (0) + %r 4: 00000000 (0) + %r 5: 80000e64 (0) + %r 6: 00000005 (0) + %r 7: 00000000 (0) + %r 8: 00000000 (0) + %r 9: 00000000 (0) + %r10: 00000000 (0) + %r11: 00000000 (0) + %r12: 00001001 (0) + %r13: 00000000 (0) + %r14: 00000000 (0) + %r15: 00000000 (0) + %r16: 00000001 (0) + %r17: 00000000 (0) + %r18: 00000000 (0) + %r19: 00000000 (0) + %r20: 00000000 (0) + %r21: 00000000 (0) + %r22: 00000000 (0) + %r23: 00000000 (0) + %r24: 00000000 (0) + %r25: 00000000 (0) + %r26: 00000000 (0) + %r27: 00000000 (0) + %r28: 00000003 (0) + %r29: 00000000 (0) + %r30: 00000000 (0) + %r31: 00000000 (0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 1 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 1 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000634 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6771 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6772 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6773 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6774 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6775 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 1, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:692: Warp ID 0 is running +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6776 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 0 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:417: Core step stepping warp 0[1] +DEBUG ../../../simX/core.cpp:770: in step pc=0x80000780 +DEBUG ../../../simX/enc.cpp:105: Curr Code: 5006b +DEBUG ../../../simX/enc.cpp:327: Decoded 0x5006b into: gpgpu + +DEBUG ../../../simX/core.cpp:790: Fetched at 0x80000780: gpgpu +DEBUG ../../../simX/instruction.cpp:350: Begin instruction execute. +DEBUG ../../../simX/instruction.cpp:1072: TMC +DEBUG ../../../simX/instruction.cpp:2428: End instruction execute. +DEBUG ../../../simX/core.cpp:803: Register state: + %r 0:(0) + %r 1:(0) + %r 2:(0) + %r 3:(0) + %r 4:(0) + %r 5:(0) + %r 6:(0) + %r 7:(0) + %r 8:(0) + %r 9:(0) + %r10:(0) + %r11:(0) + %r12:(0) + %r13:(0) + %r14:(0) + %r15:(0) + %r16:(0) + %r17:(0) + %r18:(0) + %r19:(0) + %r20:(0) + %r21:(0) + %r22:(0) + %r23:(0) + %r24:(0) + %r25:(0) + %r26:(0) + %r27:(0) + %r28:(0) + %r29:(0) + %r30:(0) + %r31:(0) +DEBUG ../../../simX/core.cpp:812: Thread mask: + 0 0 0 0 + + +DEBUG ../../../simX/core.cpp:421: Now 0 active threads in 0 +DEBUG ../../../simX/core.cpp:424: Got cache delays +DEBUG ../../../simX/core.cpp:429: staled warps + +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 3 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6777 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 2 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6778 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 1 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6779 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 1 +DEBUG ../../../simX/core.cpp:85: PC: 80000780 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: 0 rs1: 10 rs2: 0 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 1 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6780 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6781 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 2 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0 +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6782 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 3 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6783 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 0 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +DEBUG ../../../simX/core.cpp:172: + + +------------------------------------------------------ +DEBUG ../../../simX/core.cpp:174: Started core::step +DEBUG ../../../simX/core.cpp:178: CYCLE: 6784 +DEBUG ../../../simX/core.cpp:180: Stalled Warps: 1 0 0 0 +DEBUG ../../../simX/core.cpp:557: $$$$$$$$$$$$$$$$$$$ EXE START + +DEBUG ../../../simX/core.cpp:624: EXECUTE END +DEBUG ../../../simX/core.cpp:402: Threads: +DEBUG ../../../simX/core.cpp:431: About to schedule warp + +DEBUG ../../../simX/core.cpp:433: Scheduled warp +DEBUG ../../../simX/core.cpp:442: Printing trace +DEBUG ../../../simX/core.cpp:83: ********************************** Fetch ********************************* +DEBUG ../../../simX/core.cpp:84: valid: 0 +DEBUG ../../../simX/core.cpp:85: PC: 0 +DEBUG ../../../simX/core.cpp:86: wid: 1 +DEBUG ../../../simX/core.cpp:87: rd: -1 rs1: -1 rs2: -1 +DEBUG ../../../simX/core.cpp:88: is_lw: 0 +DEBUG ../../../simX/core.cpp:89: is_sw: 0 +DEBUG ../../../simX/core.cpp:90: fetch_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:91: mem_stall_cycles: 0 +DEBUG ../../../simX/core.cpp:93: stall_warp: 0 +DEBUG ../../../simX/core.cpp:94: wspawn: 0 +DEBUG ../../../simX/core.cpp:95: stalled: 0 +DEBUG ../../../simX/core.cpp:444: printed trace +DEBUG ../../../simX/core.cpp:447: active threads: 0, 0, 0, 0, +DEBUG ../../../simX/core.cpp:214: released warp +DEBUG ../../../simX/core.cpp:215: Finished core::step +Device ready... +Device shutdown... diff --git a/driver/tests/results.txt b/driver/tests/results.txt new file mode 100644 index 00000000..e69de29b diff --git a/old_rtl/Makefile b/old_rtl/Makefile new file mode 100644 index 00000000..9d64eacf --- /dev/null +++ b/old_rtl/Makefile @@ -0,0 +1,52 @@ +all: RUNFILE + +# /rf2_256x128_wm1/ +BaseMEM=../models/memory/cln28hpm + +INCLUDE=-I. -Ishared_memory -Icache -I$(BaseMEM)/rf2_128x128_wm1/ -I$(BaseMEM)/rf2_256x128_wm1/ -I$(BaseMEM)/rf2_256x19_wm0/ -I$(BaseMEM)/rf2_32x128_wm1/ -Iinterfaces/ -Ipipe_regs/ -Isimulate + +FILE=Vortex.v + +EXE=--exe ./simulate/test_bench.cpp + +COMP=--compiler gcc + +WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT +# WNO= + +# LIGHTW= +LIGHTW=-Wno-UNOPTFLAT +# LIB=-LDFLAGS '-L/usr/local/systemc/' +LIB= + +CF=-CFLAGS '-std=c++11 -O3' + +DEB=--trace --prof-cfuncs -DVL_DEBUG=1 + + +MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) + +# -LDFLAGS '-lsystemc' +VERILATOR: + echo "#define VCD_OFF" > simulate/tb_debug.h + verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW) + +VERILATORnoWarnings: + echo "#define VCD_OFF" > simulate/tb_debug.h + verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB) + +compdebug: + echo "#define VCD_OUTPUT" > simulate/tb_debug.h + verilator_bin_dbg $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB) + +RUNFILE: VERILATOR + $(MAKECPP) + +debug: compdebug + $(MAKECPP) + +w: VERILATORnoWarnings + $(MAKECPP) + +clean: + rm -rf obj_dir \ No newline at end of file diff --git a/old_rtl/VX_alu.v b/old_rtl/VX_alu.v new file mode 100644 index 00000000..9688aad2 --- /dev/null +++ b/old_rtl/VX_alu.v @@ -0,0 +1,139 @@ +`include "VX_define.v" + +module VX_alu( + input wire[31:0] in_1, + input wire[31:0] in_2, + input wire in_rs2_src, + input wire[31:0] in_itype_immed, + input wire[19:0] in_upper_immed, + input wire[4:0] in_alu_op, + input wire[31:0] in_curr_PC, + output reg[31:0] out_alu_result + ); + + + `ifdef SYN_FUNC + wire which_in2; + + wire[31:0] ALU_in1; + wire[31:0] ALU_in2; + wire[63:0] ALU_in1_mult; + wire[63:0] ALU_in2_mult; + wire[31:0] upper_immed; + wire[31:0] div_result; + wire[31:0] rem_result; + + + assign which_in2 = in_rs2_src == `RS2_IMMED; + + assign ALU_in1 = in_1; + + assign ALU_in2 = which_in2 ? in_itype_immed : in_2; + + + assign upper_immed = {in_upper_immed, {12{1'b0}}}; + + + + //always @(posedge `MUL) begin + + + /* verilator lint_off UNUSED */ + + + wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; + wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2}; + assign ALU_in1_mult = (in_alu_op == `MULHU || in_alu_op == `DIVU || in_alu_op == `REMU) ? {32'b0, ALU_in1} : alu_in1_signed; + assign ALU_in2_mult = (in_alu_op == `MULHU || in_alu_op == `MULHSU || in_alu_op == `DIVU || in_alu_op == `REMU) ? {32'b0, ALU_in2} : alu_in2_signed; + wire[63:0] mult_result = ALU_in1_mult * ALU_in2_mult; + + /* verilator lint_on UNUSED */ + + always @(in_alu_op or ALU_in1 or ALU_in2) begin + case(in_alu_op) + `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); + `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); + `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0]; + `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; + `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; + `XOR: out_alu_result = ALU_in1 ^ ALU_in2; + `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0]; + `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; + `OR: out_alu_result = ALU_in1 | ALU_in2; + `AND: out_alu_result = ALU_in2 & ALU_in1; + `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; + `LUI_ALU: out_alu_result = upper_immed; + `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); + `MUL: out_alu_result = mult_result[31:0]; + `MULH: out_alu_result = mult_result[63:32]; + `MULHSU: out_alu_result = mult_result[63:32]; + `MULHU: out_alu_result = mult_result[63:32]; + `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : $signed($signed(ALU_in1) / $signed(ALU_in2)); + `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : ALU_in1 / ALU_in2; + `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : $signed($signed(ALU_in1) % $signed(ALU_in2)); + `REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2; + default: out_alu_result = 32'h0; + endcase // in_alu_op + end + + `else + wire which_in2; + + wire[31:0] ALU_in1; + wire[31:0] ALU_in2; + wire[31:0] upper_immed; + + + assign which_in2 = in_rs2_src == `RS2_IMMED; + + assign ALU_in1 = in_1; + + assign ALU_in2 = which_in2 ? in_itype_immed : in_2; + + + assign upper_immed = {in_upper_immed, {12{1'b0}}}; + + + + // always @(*) begin + // $display("EXECUTE CURR_PC: %h",in_curr_PC); + // end + + /* verilator lint_off UNUSED */ + wire[63:0] mult_unsigned_result = ALU_in1 * ALU_in2; + wire[63:0] mult_signed_result = $signed(ALU_in1) * $signed(ALU_in2); + + wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; + + wire[63:0] mult_signed_un_result = alu_in1_signed * ALU_in2; + /* verilator lint_on UNUSED */ + + always @(in_alu_op or ALU_in1 or ALU_in2) begin + case(in_alu_op) + `ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2); + `SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); + `SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0]; + `SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; + `SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; + `XOR: out_alu_result = ALU_in1 ^ ALU_in2; + `SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0]; + `SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; + `OR: out_alu_result = ALU_in1 | ALU_in2; + `AND: out_alu_result = ALU_in2 & ALU_in1; + `SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; + `LUI_ALU: out_alu_result = upper_immed; + `AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed); + `MUL: begin out_alu_result = mult_signed_result[31:0]; end + `MULH: out_alu_result = mult_signed_result[63:32]; + `MULHSU: out_alu_result = mult_signed_un_result[63:32]; + `MULHU: out_alu_result = mult_unsigned_result[63:32]; + `DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : $signed($signed(ALU_in1) / $signed(ALU_in2)); + `DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : ALU_in1 / ALU_in2; + `REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : $signed($signed(ALU_in1) % $signed(ALU_in2)); + `REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2; + default: out_alu_result = 32'h0; + endcase // in_alu_op + end + `endif + +endmodule // VX_alu \ No newline at end of file diff --git a/old_rtl/VX_back_end.v b/old_rtl/VX_back_end.v new file mode 100644 index 00000000..640def5f --- /dev/null +++ b/old_rtl/VX_back_end.v @@ -0,0 +1,133 @@ +`include "VX_define.v" + +module VX_back_end ( + input wire clk, + input wire reset, + input wire schedule_delay, + + output wire out_mem_delay, + output wire gpr_stage_delay, + VX_jal_response_inter VX_jal_rsp, + VX_branch_response_inter VX_branch_rsp, + + VX_frE_to_bckE_req_inter VX_bckE_req, + VX_wb_inter VX_writeback_inter, + + VX_warp_ctl_inter VX_warp_ctl, + + VX_dcache_response_inter VX_dcache_rsp, + VX_dcache_request_inter VX_dcache_req + +); + + +VX_wb_inter VX_writeback_temp(); +assign VX_writeback_inter.wb = VX_writeback_temp.wb; +assign VX_writeback_inter.rd = VX_writeback_temp.rd; +assign VX_writeback_inter.write_data = VX_writeback_temp.write_data; +assign VX_writeback_inter.wb_valid = VX_writeback_temp.wb_valid; +assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num; + +// assign VX_writeback_inter(VX_writeback_temp); + + +VX_mw_wb_inter VX_mw_wb(); +wire no_slot_mem; + + +VX_mem_req_inter VX_exe_mem_req(); +VX_mem_req_inter VX_mem_req(); + + + +// LSU input + output +VX_lsu_req_inter VX_lsu_req(); +VX_inst_mem_wb_inter VX_mem_wb(); + +// Exec unit input + output +VX_exec_unit_req_inter VX_exec_unit_req(); +VX_inst_exec_wb_inter VX_inst_exec_wb(); + + +// GPU unit input +VX_gpu_inst_req_inter VX_gpu_inst_req(); + +// CSR unit inputs +VX_csr_req_inter VX_csr_req(); +VX_csr_wb_inter VX_csr_wb(); +wire no_slot_csr; +wire stall_gpr_csr; + +VX_gpr_stage VX_gpr_stage( + .clk (clk), + .reset (reset), + .schedule_delay (schedule_delay), + .VX_writeback_inter(VX_writeback_temp), + .VX_bckE_req (VX_bckE_req), + // New + .VX_exec_unit_req(VX_exec_unit_req), + .VX_lsu_req (VX_lsu_req), + .VX_gpu_inst_req (VX_gpu_inst_req), + .VX_csr_req (VX_csr_req), + .stall_gpr_csr (stall_gpr_csr), + // End new + .memory_delay (out_mem_delay), + .gpr_stage_delay (gpr_stage_delay) + ); + + +VX_lsu load_store_unit( + .clk (clk), + .reset (reset), + .VX_lsu_req (VX_lsu_req), + .VX_mem_wb (VX_mem_wb), + .VX_dcache_rsp(VX_dcache_rsp), + .VX_dcache_req(VX_dcache_req), + .out_delay (out_mem_delay), + .no_slot_mem (no_slot_mem) + ); + + +VX_execute_unit VX_execUnit( + .clk (clk), + .reset (reset), + .VX_exec_unit_req(VX_exec_unit_req), + .VX_inst_exec_wb (VX_inst_exec_wb), + .VX_jal_rsp (VX_jal_rsp), + .VX_branch_rsp (VX_branch_rsp) + ); + + +VX_gpgpu_inst VX_gpgpu_inst( + .VX_gpu_inst_req(VX_gpu_inst_req), + .VX_warp_ctl (VX_warp_ctl) + ); + +// VX_csr_wrapper VX_csr_wrapper( +// .VX_csr_req(VX_csr_req), +// .VX_csr_wb (VX_csr_wb) +// ); + +VX_csr_pipe VX_csr_pipe( + .clk (clk), + .reset (reset), + .no_slot_csr (no_slot_csr), + .VX_csr_req (VX_csr_req), + .VX_writeback(VX_writeback_temp), + .VX_csr_wb (VX_csr_wb), + .stall_gpr_csr(stall_gpr_csr) + ); + +VX_writeback VX_wb( + .clk (clk), + .reset (reset), + .VX_mem_wb (VX_mem_wb), + .VX_inst_exec_wb (VX_inst_exec_wb), + .VX_csr_wb (VX_csr_wb), + + .VX_writeback_inter(VX_writeback_temp), + .no_slot_mem (no_slot_mem), + .no_slot_csr (no_slot_csr) + ); + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_countones.v b/old_rtl/VX_countones.v new file mode 100644 index 00000000..62f20e16 --- /dev/null +++ b/old_rtl/VX_countones.v @@ -0,0 +1,22 @@ +module VX_countones + #( + parameter N = 10 + ) + ( + + input wire[N-1:0] valids, + output reg[$clog2(N):0] count + +); + + integer i; + always @(*) begin + count = 0; + for (i = N-1; i >= 0; i = i - 1) begin + if (valids[i]) begin + count = count + 1; + end + end + end + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_csr_data.v b/old_rtl/VX_csr_data.v new file mode 100644 index 00000000..ab62aa23 --- /dev/null +++ b/old_rtl/VX_csr_data.v @@ -0,0 +1,82 @@ +`include "../VX_define.v" + +module VX_csr_data ( + input wire clk, // Clock + input wire reset, + + input wire[11:0] in_read_csr_address, + + input wire in_write_valid, + input wire[31:0] in_write_csr_data, + input wire[11:0] in_write_csr_address, + + output wire[31:0] out_read_csr_data, + + // For instruction retire counting + input wire in_writeback_valid + +); + + + // wire[`NT_M1:0][31:0] thread_ids; + // wire[`NT_M1:0][31:0] warp_ids; + + // genvar cur_t; + // for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin + // assign thread_ids[cur_t] = cur_t; + // end + + // genvar cur_tw; + // for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin + // assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, in_read_warp_num}; + // end + + reg[11:0] csr[1023:0]; + reg[63:0] cycle; + reg[63:0] instret; + + + wire read_cycle; + wire read_cycleh; + wire read_instret; + wire read_instreth; + + assign read_cycle = in_read_csr_address == 12'hC00; + assign read_cycleh = in_read_csr_address == 12'hC80; + assign read_instret = in_read_csr_address == 12'hC02; + assign read_instreth = in_read_csr_address == 12'hC82; + + // wire thread_select = in_read_csr_address == 12'h20; + // wire warp_select = in_read_csr_address == 12'h21; + + // assign out_read_csr_data = thread_select ? thread_ids : + // warp_select ? warp_ids : + // 0; + + integer curr_e; + always @(posedge clk or posedge reset) begin + if (reset) begin + for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin + assign csr[curr_e] = 0; + end + cycle <= 0; + instret <= 0; + end else begin + cycle <= cycle + 1; + if (in_write_valid) begin + csr[in_write_csr_address] <= in_write_csr_data[11:0]; + end + if (in_writeback_valid) begin + instret <= instret + 1; + end + end + end + + + assign out_read_csr_data = read_cycle ? cycle[31:0] : + read_cycleh ? cycle[63:32] : + read_instret ? instret[31:0] : + read_instreth ? instret[63:32] : + {{20{1'b0}}, csr[in_read_csr_address]}; + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_csr_handler.v b/old_rtl/VX_csr_handler.v new file mode 100644 index 00000000..b6b4e84a --- /dev/null +++ b/old_rtl/VX_csr_handler.v @@ -0,0 +1,84 @@ + + +module VX_csr_handler ( + input wire clk, + input wire[11:0] in_decode_csr_address, // done + VX_csr_write_request_inter VX_csr_w_req, + input wire in_wb_valid, + output wire[31:0] out_decode_csr_data // done + ); + + wire in_mem_is_csr; + wire[11:0] in_mem_csr_address; + /* verilator lint_off UNUSED */ + wire[31:0] in_mem_csr_result; + /* verilator lint_on UNUSED */ + + + assign in_mem_is_csr = VX_csr_w_req.is_csr; + assign in_mem_csr_address = VX_csr_w_req.csr_address; + assign in_mem_csr_result = VX_csr_w_req.csr_result; + + + reg[1024:0][11:0] csr; + reg[63:0] cycle; + reg[63:0] instret; + reg[11:0] decode_csr_address; + + + wire read_cycle; + wire read_cycleh; + wire read_instret; + wire read_instreth; + + initial begin + cycle = 0; + instret = 0; + decode_csr_address = 0; + end + + + always @(posedge clk) begin + cycle <= cycle + 1; + decode_csr_address <= in_decode_csr_address; + if (in_wb_valid) begin + instret <= instret + 1; + end + end + + reg[11:0] data_read; + always @(posedge clk) begin + if(in_mem_is_csr) begin + csr[in_mem_csr_address] <= in_mem_csr_result[11:0]; + end + end + + assign data_read = csr[decode_csr_address]; + + + assign read_cycle = decode_csr_address == 12'hC00; + assign read_cycleh = decode_csr_address == 12'hC80; + assign read_instret = decode_csr_address == 12'hC02; + assign read_instreth = decode_csr_address == 12'hC82; + + + /* verilator lint_off WIDTH */ + assign out_decode_csr_data = read_cycle ? cycle[31:0] : + read_cycleh ? cycle[63:32] : + read_instret ? instret[31:0] : + read_instreth ? instret[63:32] : + {{20{1'b0}}, data_read}; + /* verilator lint_on WIDTH */ + + + + + +endmodule // VX_csr_handler + + + + + + + diff --git a/old_rtl/VX_csr_pipe.v b/old_rtl/VX_csr_pipe.v new file mode 100644 index 00000000..a5727c60 --- /dev/null +++ b/old_rtl/VX_csr_pipe.v @@ -0,0 +1,105 @@ + +module VX_csr_pipe ( + input wire clk, // Clock + input wire reset, + input wire no_slot_csr, + VX_csr_req_inter VX_csr_req, + VX_wb_inter VX_writeback, + VX_csr_wb_inter VX_csr_wb, + output wire stall_gpr_csr + +); + + wire[`NT_M1:0] valid_s2; + wire[`NW_M1:0] warp_num_s2; + wire[4:0] rd_s2; + wire[1:0] wb_s2; + wire[4:0] alu_op_s2; + wire is_csr_s2; + wire[11:0] csr_address_s2; + wire[31:0] csr_read_data_s2; + wire[31:0] csr_updated_data_s2; + + wire[31:0] csr_read_data_unqual; + wire[31:0] csr_read_data; + + assign stall_gpr_csr = no_slot_csr && VX_csr_req.is_csr && |(VX_csr_req.valid); + + assign csr_read_data = (csr_address_s2 == VX_csr_req.csr_address) ? csr_updated_data_s2 : csr_read_data_unqual; + + wire writeback = |VX_writeback.wb_valid; + VX_csr_data VX_csr_data( + .clk (clk), + .reset (reset), + .in_read_csr_address (VX_csr_req.csr_address), + + .in_write_valid (is_csr_s2), + .in_write_csr_data (csr_updated_data_s2), + .in_write_csr_address(csr_address_s2), + + .out_read_csr_data (csr_read_data_unqual), + + .in_writeback_valid (writeback) + ); + + + + reg[31:0] csr_updated_data; + always @(*) begin + case(VX_csr_req.alu_op) + `CSR_ALU_RW: csr_updated_data = VX_csr_req.csr_mask; + `CSR_ALU_RS: csr_updated_data = csr_read_data | VX_csr_req.csr_mask; + `CSR_ALU_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - VX_csr_req.csr_mask); + default: csr_updated_data = 32'hdeadbeef; + endcase + end + + wire zero = 0; + + VX_generic_register #(.N(`NT + `NW_M1 + 1 + 5 + 2 + 5 + 12 + 64)) csr_reg_s2 ( + .clk (clk), + .reset(reset), + .stall(no_slot_csr), + .flush(zero), + .in ({VX_csr_req.valid, VX_csr_req.warp_num, VX_csr_req.rd, VX_csr_req.wb, VX_csr_req.is_csr, VX_csr_req.csr_address, csr_read_data , csr_updated_data }), + .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2}) + ); + + + wire[`NT_M1:0][31:0] final_csr_data; + + wire[`NT_M1:0][31:0] thread_ids; + wire[`NT_M1:0][31:0] warp_ids; + wire[`NT_M1:0][31:0] csr_vec_read_data_s2; + + genvar cur_t; + for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin + assign thread_ids[cur_t] = cur_t; + end + + genvar cur_tw; + for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin + assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, warp_num_s2}; + end + + genvar cur_v; + for (cur_v = 0; cur_v < `NT; cur_v = cur_v + 1) begin + assign csr_vec_read_data_s2[cur_v] = csr_read_data_s2; + end + + wire thread_select = csr_address_s2 == 12'h20; + wire warp_select = csr_address_s2 == 12'h21; + + assign final_csr_data = thread_select ? thread_ids : + warp_select ? warp_ids : + csr_vec_read_data_s2; + + + + assign VX_csr_wb.valid = valid_s2; + assign VX_csr_wb.warp_num = warp_num_s2; + assign VX_csr_wb.rd = rd_s2; + assign VX_csr_wb.wb = wb_s2; + assign VX_csr_wb.csr_result = final_csr_data; + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_csr_wrapper.v b/old_rtl/VX_csr_wrapper.v new file mode 100644 index 00000000..0988ca67 --- /dev/null +++ b/old_rtl/VX_csr_wrapper.v @@ -0,0 +1,38 @@ + +`include "VX_define.v" + +module VX_csr_wrapper ( + VX_csr_req_inter VX_csr_req, + + VX_csr_wb_inter VX_csr_wb +); + + + wire[`NT_M1:0][31:0] thread_ids; + wire[`NT_M1:0][31:0] warp_ids; + + genvar cur_t; + for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin + assign thread_ids[cur_t] = cur_t; + end + + genvar cur_tw; + for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin + assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, VX_csr_req.warp_num}; + end + + + assign VX_csr_wb.valid = VX_csr_req.valid; + assign VX_csr_wb.warp_num = VX_csr_req.warp_num; + assign VX_csr_wb.rd = VX_csr_req.rd; + assign VX_csr_wb.wb = VX_csr_req.wb; + + + wire thread_select = VX_csr_req.csr_address == 12'h20; + wire warp_select = VX_csr_req.csr_address == 12'h21; + + assign VX_csr_wb.csr_result = thread_select ? thread_ids : + warp_select ? warp_ids : + 0; + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_decode.v b/old_rtl/VX_decode.v new file mode 100644 index 00000000..4f33bbd1 --- /dev/null +++ b/old_rtl/VX_decode.v @@ -0,0 +1,361 @@ + +`include "VX_define.v" + +module VX_decode( + // Fetch Inputs + VX_inst_meta_inter fd_inst_meta_de, + + // Outputs + VX_frE_to_bckE_req_inter VX_frE_to_bckE_req, + VX_wstall_inter VX_wstall, + VX_join_inter VX_join, + + output wire terminate_sim + +); + + wire[31:0] in_instruction = fd_inst_meta_de.instruction; + wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc; + wire[`NW_M1:0] in_warp_num = fd_inst_meta_de.warp_num; + + assign VX_frE_to_bckE_req.curr_PC = in_curr_PC; + + wire[`NT_M1:0] in_valid = fd_inst_meta_de.valid; + + wire[6:0] curr_opcode; + + wire is_itype; + wire is_rtype; + wire is_stype; + wire is_btype; + wire is_linst; + wire is_jal; + wire is_jalr; + wire is_lui; + wire is_auipc; + wire is_csr; + wire is_csr_immed; + wire is_e_inst; + + wire is_gpgpu; + wire is_wspawn; + wire is_tmc; + wire is_split; + wire is_join; + wire is_barrier; + + wire[2:0] func3; + wire[6:0] func7; + wire[11:0] u_12; + + + wire[7:0] jal_b_19_to_12; + wire jal_b_11; + wire[9:0] jal_b_10_to_1; + wire jal_b_20; + wire jal_b_0; + wire[20:0] jal_unsigned_offset; + wire[31:0] jal_1_offset; + + wire[11:0] jalr_immed; + wire[31:0] jal_2_offset; + + wire jal_sys_cond1; + wire jal_sys_cond2; + wire jal_sys_jal; + wire[31:0] jal_sys_off; + + wire csr_cond1; + wire csr_cond2; + + wire[11:0] alu_tempp; + wire alu_shift_i; + wire[11:0] alu_shift_i_immed; + + wire[1:0] csr_type; + + reg[4:0] csr_alu; + reg[4:0] alu_op; + reg[4:0] mul_alu; + reg[19:0] temp_upper_immed; + reg temp_jal; + reg[31:0] temp_jal_offset; + reg[31:0] temp_itype_immed; + reg[2:0] temp_branch_type; + reg temp_branch_stall; + + // always @(posedge reset) begin + + // end + + assign VX_frE_to_bckE_req.valid = fd_inst_meta_de.valid; + + assign VX_frE_to_bckE_req.warp_num = in_warp_num; + + + assign curr_opcode = in_instruction[6:0]; + + + assign VX_frE_to_bckE_req.rd = in_instruction[11:7]; + assign VX_frE_to_bckE_req.rs1 = in_instruction[19:15]; + assign VX_frE_to_bckE_req.rs2 = in_instruction[24:20]; + assign func3 = in_instruction[14:12]; + assign func7 = in_instruction[31:25]; + assign u_12 = in_instruction[31:20]; + + + assign VX_frE_to_bckE_req.PC_next = in_curr_PC + 32'h4; + + + // Write Back sigal + assign is_rtype = (curr_opcode == `R_INST); + assign is_linst = (curr_opcode == `L_INST); + assign is_itype = (curr_opcode == `ALU_INST) || is_linst; + assign is_stype = (curr_opcode == `S_INST); + assign is_btype = (curr_opcode == `B_INST); + assign is_jal = (curr_opcode == `JAL_INST); + assign is_jalr = (curr_opcode == `JALR_INST); + assign is_lui = (curr_opcode == `LUI_INST); + assign is_auipc = (curr_opcode == `AUIPC_INST); + assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0); + assign is_csr_immed = (is_csr) && (func3[2] == 1); + // assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0); + assign is_e_inst = in_instruction == 32'h00000073; + + assign is_gpgpu = (curr_opcode == `GPGPU_INST); + + assign is_tmc = is_gpgpu && (func3 == 0); // Goes to BE + assign is_wspawn = is_gpgpu && (func3 == 1); // Goes to BE + assign is_barrier = is_gpgpu && (func3 == 4); // Goes to BE + assign is_split = is_gpgpu && (func3 == 2); // Goes to BE + assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE + + + assign VX_join.is_join = is_join; + assign VX_join.join_warp_num = in_warp_num; + + + assign VX_frE_to_bckE_req.is_wspawn = is_wspawn; + assign VX_frE_to_bckE_req.is_tmc = is_tmc; + assign VX_frE_to_bckE_req.is_split = is_split; + assign VX_frE_to_bckE_req.is_barrier = is_barrier; + + + + assign VX_frE_to_bckE_req.csr_immed = is_csr_immed; + assign VX_frE_to_bckE_req.is_csr = is_csr; + + + assign VX_frE_to_bckE_req.wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL : + is_linst ? `WB_MEM : + (is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU : + `NO_WB; + + + assign VX_frE_to_bckE_req.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG; + + // MEM signals + assign VX_frE_to_bckE_req.mem_read = (is_linst) ? func3 : `NO_MEM_READ; + assign VX_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE; + + // UPPER IMMEDIATE + always @(*) begin + case(curr_opcode) + `LUI_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3}; + `AUIPC_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3}; + default: temp_upper_immed = 20'h0; + endcase // curr_opcode + end + + assign VX_frE_to_bckE_req.upper_immed = temp_upper_immed; + + + assign jal_b_19_to_12 = in_instruction[19:12]; + assign jal_b_11 = in_instruction[20]; + assign jal_b_10_to_1 = in_instruction[30:21]; + assign jal_b_20 = in_instruction[31]; + assign jal_b_0 = 1'b0; + assign jal_unsigned_offset = {jal_b_20, jal_b_19_to_12, jal_b_11, jal_b_10_to_1, jal_b_0}; + assign jal_1_offset = {{11{jal_b_20}}, jal_unsigned_offset}; + + + assign jalr_immed = {func7, VX_frE_to_bckE_req.rs2}; + assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed}; + + + assign jal_sys_cond1 = func3 == 3'h0; + assign jal_sys_cond2 = u_12 < 12'h2; + + assign jal_sys_jal = (jal_sys_cond1 && jal_sys_cond2) ? 1'b1 : 1'b0; + assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef; + + // JAL + always @(*) begin + case(curr_opcode) + `JAL_INST: + begin + temp_jal = 1'b1 && (|in_valid); + temp_jal_offset = jal_1_offset; + end + `JALR_INST: + begin + temp_jal = 1'b1 && (|in_valid); + temp_jal_offset = jal_2_offset; + end + `SYS_INST: + begin + // $display("SYS EBREAK %h", (jal_sys_jal && (|in_valid)) ); + temp_jal = jal_sys_jal && (|in_valid); + temp_jal_offset = jal_sys_off; + end + default: + begin + temp_jal = 1'b0 && (|in_valid); + temp_jal_offset = 32'hdeadbeef; + end + endcase + end + + assign VX_frE_to_bckE_req.jalQual = is_jal; + assign VX_frE_to_bckE_req.jal = temp_jal; + assign VX_frE_to_bckE_req.jal_offset = temp_jal_offset; + + // wire is_ebreak; + + + // assign is_ebreak = is_e_inst; + wire ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && (|in_valid)); + assign VX_frE_to_bckE_req.ebreak = ebreak; + wire out_ebreak = ebreak; + assign terminate_sim = is_e_inst; + + + // CSR + + assign csr_cond1 = func3 != 3'h0; + assign csr_cond2 = u_12 >= 12'h2; + + assign VX_frE_to_bckE_req.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; + + + // ITYPE IMEED + assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5); + assign alu_shift_i_immed = {{7{1'b0}}, VX_frE_to_bckE_req.rs2}; + assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12; + + + always @(*) begin + case(curr_opcode) + `ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp}; + `S_INST: temp_itype_immed = {{20{func7[6]}}, func7, VX_frE_to_bckE_req.rd}; + `L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12}; + `B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]}; + default: temp_itype_immed = 32'hdeadbeef; + endcase + end + + assign VX_frE_to_bckE_req.itype_immed = temp_itype_immed; + + + + always @(*) begin + case(curr_opcode) + `B_INST: + begin + // $display("BRANCH IN DECODE"); + temp_branch_stall = 1'b1 && (|in_valid); + case(func3) + 3'h0: temp_branch_type = `BEQ; + 3'h1: temp_branch_type = `BNE; + 3'h4: temp_branch_type = `BLT; + 3'h5: temp_branch_type = `BGT; + 3'h6: temp_branch_type = `BLTU; + 3'h7: temp_branch_type = `BGTU; + default: temp_branch_type = `NO_BRANCH; + endcase + end + + `JAL_INST: + begin + temp_branch_type = `NO_BRANCH; + temp_branch_stall = 1'b1 && (|in_valid); + end + `JALR_INST: + begin + temp_branch_type = `NO_BRANCH; + temp_branch_stall = 1'b1 && (|in_valid); + end + default: + begin + temp_branch_type = `NO_BRANCH; + temp_branch_stall = 1'b0 && (|in_valid); + end + endcase + end + + assign VX_frE_to_bckE_req.branch_type = temp_branch_type; + + assign VX_wstall.wstall = (temp_branch_stall || is_tmc || is_split || is_barrier) && (|in_valid); + assign VX_wstall.warp_num = in_warp_num; + + always @(*) begin + // ALU OP + case(func3) + 3'h0: alu_op = (curr_opcode == `ALU_INST) ? `ADD : (func7 == 7'h0 ? `ADD : `SUB); + 3'h1: alu_op = `SLLA; + 3'h2: alu_op = `SLT; + 3'h3: alu_op = `SLTU; + 3'h4: alu_op = `XOR; + 3'h5: alu_op = (func7 == 7'h0) ? `SRL : `SRA; + 3'h6: alu_op = `OR; + 3'h7: alu_op = `AND; + default: alu_op = `NO_ALU; + endcase + end + + always @(*) begin + // ALU OP + case(func3) + 3'h0: mul_alu = `MUL; + 3'h1: mul_alu = `MULH; + 3'h2: mul_alu = `MULHSU; + 3'h3: mul_alu = `MULHU; + 3'h4: mul_alu = `DIV; + 3'h5: mul_alu = `DIVU; + 3'h6: mul_alu = `REM; + 3'h7: mul_alu = `REMU; + default: mul_alu = `NO_ALU; + endcase + end + + assign csr_type = func3[1:0]; + + always @(*) begin + case(csr_type) + 2'h1: csr_alu = `CSR_ALU_RW; + 2'h2: csr_alu = `CSR_ALU_RS; + 2'h3: csr_alu = `CSR_ALU_RC; + default: csr_alu = `NO_ALU; + endcase + end + + wire[4:0] temp_final_alu; + + assign temp_final_alu = is_btype ? ((VX_frE_to_bckE_req.branch_type < `BLTU) ? `SUB : `SUBU) : + is_lui ? `LUI_ALU : + is_auipc ? `AUIPC_ALU : + is_csr ? csr_alu : + (is_stype || is_linst) ? `ADD : + alu_op; + + assign VX_frE_to_bckE_req.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu; + +endmodule + + + + + + + + diff --git a/old_rtl/VX_define.v b/old_rtl/VX_define.v new file mode 100644 index 00000000..f177fbfb --- /dev/null +++ b/old_rtl/VX_define.v @@ -0,0 +1,269 @@ +`include "./VX_define_synth.v" + + + +`define NT_M1 (`NT-1) + +// NW_M1 is actually log2(NW) +`define NW_M1 (`CLOG2(`NW)) + +// Uncomment the below line if NW=1 +// `define ONLY + +// `define SYN 1 +// `define ASIC 1 +// `define SYN_FUNC 1 + +`define NUM_BARRIERS 4 + +`define R_INST 7'd51 +`define L_INST 7'd3 +`define ALU_INST 7'd19 +`define S_INST 7'd35 +`define B_INST 7'd99 +`define LUI_INST 7'd55 +`define AUIPC_INST 7'd23 +`define JAL_INST 7'd111 +`define JALR_INST 7'd103 +`define SYS_INST 7'd115 +`define GPGPU_INST 7'h6b + + +`define WB_ALU 2'h1 +`define WB_MEM 2'h2 +`define WB_JAL 2'h3 +`define NO_WB 2'h0 + + +`define RS2_IMMED 1 +`define RS2_REG 0 + + +`define NO_MEM_READ 3'h7 +`define LB_MEM_READ 3'h0 +`define LH_MEM_READ 3'h1 +`define LW_MEM_READ 3'h2 +`define LBU_MEM_READ 3'h4 +`define LHU_MEM_READ 3'h5 + + +`define NO_MEM_WRITE 3'h7 +`define SB_MEM_WRITE 3'h0 +`define SH_MEM_WRITE 3'h1 +`define SW_MEM_WRITE 3'h2 + + +`define NO_BRANCH 3'h0 +`define BEQ 3'h1 +`define BNE 3'h2 +`define BLT 3'h3 +`define BGT 3'h4 +`define BLTU 3'h5 +`define BGTU 3'h6 + + +`define NO_ALU 5'd15 +`define ADD 5'd0 +`define SUB 5'd1 +`define SLLA 5'd2 +`define SLT 5'd3 +`define SLTU 5'd4 +`define XOR 5'd5 +`define SRL 5'd6 +`define SRA 5'd7 +`define OR 5'd8 +`define AND 5'd9 +`define SUBU 5'd10 +`define LUI_ALU 5'd11 +`define AUIPC_ALU 5'd12 +`define CSR_ALU_RW 5'd13 +`define CSR_ALU_RS 5'd14 +`define CSR_ALU_RC 5'd15 +`define MUL 5'd16 +`define MULH 5'd17 +`define MULHSU 5'd18 +`define MULHU 5'd19 +`define DIV 5'd20 +`define DIVU 5'd21 +`define REM 5'd22 +`define REMU 5'd23 + + + +// WRITEBACK +`define WB_ALU 2'h1 +`define WB_MEM 2'h2 +`define WB_JAL 2'h3 +`define NO_WB 2'h0 + + +// JAL +`define JUMP 1'h1 +`define NO_JUMP 1'h0 + +// STALLS +`define STALL 1'h1 +`define NO_STALL 1'h0 + + +`define TAKEN 1'b1 +`define NOT_TAKEN 1'b0 + + +`define ZERO_REG 5'h0 + +`define CLOG2(x) \ + (x <= 2) ? 1 : \ + (x <= 4) ? 2 : \ + (x <= 8) ? 3 : \ + (x <= 16) ? 4 : \ + (x <= 32) ? 5 : \ + (x <= 64) ? 6 : \ + (x <= 128) ? 7 : \ + (x <= 256) ? 8 : \ + (x <= 512) ? 9 : \ + (x <= 1024) ? 10 : \ + -199 + + +// `define PARAM + +// oooooo + +//Cache configurations +//Cache configurations + //Bytes +`define ICACHE_SIZE 4096 +`define ICACHE_WAYS 2 +//Bytes +`define ICACHE_BLOCK 64 +`define ICACHE_BANKS 4 +`define ICACHE_LOG_NUM_BANKS `CLOG2(`ICACHE_BANKS) + +`define ICACHE_NUM_WORDS_PER_BLOCK (`ICACHE_BLOCK / (`ICACHE_BANKS * 4)) +`define ICACHE_NUM_REQ 1 +`define ICACHE_LOG_NUM_REQ `CLOG2(`ICACHE_NUM_REQ) + + //set this to 1 if CACHE_WAYS is 1 +`define ICACHE_WAY_INDEX `CLOG2(`ICACHE_WAYS) +//`define ICACHE_WAY_INDEX 1 +`define ICACHE_BLOCK_PER_BANK (`ICACHE_BLOCK / `ICACHE_BANKS) + +// Offset +`define ICACHE_OFFSET_NB (`CLOG2(`ICACHE_NUM_WORDS_PER_BLOCK)) + +`define ICACHE_ADDR_OFFSET_ST (2+$clog2(`ICACHE_BANKS)) +`define ICACHE_ADDR_OFFSET_ED (`ICACHE_ADDR_OFFSET_ST+(`ICACHE_OFFSET_NB)-1) + + +`define ICACHE_ADDR_OFFSET_RNG `ICACHE_ADDR_OFFSET_ED:`ICACHE_ADDR_OFFSET_ST +`define ICACHE_OFFSET_SIZE_RNG (`CLOG2(`ICACHE_NUM_WORDS_PER_BLOCK)-1):0 +`define ICACHE_OFFSET_ST 0 +`define ICACHE_OFFSET_ED ($clog2(`ICACHE_NUM_WORDS_PER_BLOCK)-1) + +// Index +// `define ICACHE_NUM_IND (`ICACHE_SIZE / (`ICACHE_WAYS * `ICACHE_BLOCK_PER_BANK)) +`define ICACHE_NUM_IND (`ICACHE_SIZE / (`ICACHE_WAYS * `ICACHE_BLOCK)) +`define ICACHE_IND_NB ($clog2(`ICACHE_NUM_IND)) + +`define ICACHE_IND_ST (`ICACHE_ADDR_OFFSET_ED+1) +`define ICACHE_IND_ED (`ICACHE_IND_ST+`ICACHE_IND_NB-1) + +`define ICACHE_ADDR_IND_RNG `ICACHE_IND_ED:`ICACHE_IND_ST +`define ICACHE_IND_SIZE_RNG `ICACHE_IND_NB-1:0 + +`define ICACHE_IND_SIZE_START 0 +`define ICACHE_IND_SIZE_END `ICACHE_IND_NB-1 + + +// Tag +`define ICACHE_ADDR_TAG_RNG 31:(`ICACHE_IND_ED+1) +`define ICACHE_TAG_SIZE_RNG (32-(`ICACHE_IND_ED+1)-1):0 +`define ICACHE_TAG_SIZE_START 0 +`define ICACHE_TAG_SIZE_END (32-(`ICACHE_IND_ED+1)-1) +`define ICACHE_ADDR_TAG_START (`ICACHE_IND_ED+1) +`define ICACHE_ADDR_TAG_END 31 + +//Cache configurations +//Bytes +`define DCACHE_SIZE 4096 +`define DCACHE_WAYS 2 + +//Bytes +`define DCACHE_BLOCK 64 +`define DCACHE_BANKS 4 +`define DCACHE_LOG_NUM_BANKS $clog2(`DCACHE_BANKS) +`define DCACHE_NUM_WORDS_PER_BLOCK (`DCACHE_BLOCK / (`DCACHE_BANKS * 4)) +`define DCACHE_NUM_REQ `NT +`define DCACHE_LOG_NUM_REQ $clog2(`DCACHE_NUM_REQ) + +//set this to 1 if CACHE_WAYS is 1 +`define DCACHE_WAY_INDEX $clog2(`DCACHE_WAYS) +//`define DCACHE_WAY_INDEX 1 +`define DCACHE_BLOCK_PER_BANK (`DCACHE_BLOCK / `DCACHE_BANKS) + +// Offset +`define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)) + +`define DCACHE_ADDR_OFFSET_ST (2+$clog2(`DCACHE_BANKS)) +`define DCACHE_ADDR_OFFSET_ED (`DCACHE_ADDR_OFFSET_ST+(`DCACHE_OFFSET_NB)-1) + + +`define DCACHE_ADDR_OFFSET_RNG `DCACHE_ADDR_OFFSET_ED:`DCACHE_ADDR_OFFSET_ST +`define DCACHE_OFFSET_SIZE_RNG ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1):0 +`define DCACHE_OFFSET_ST 0 +`define DCACHE_OFFSET_ED ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1) + +// Index +// `define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK_PER_BANK)) +`define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK)) +`define DCACHE_IND_NB ($clog2(`DCACHE_NUM_IND)) + +`define DCACHE_IND_ST (`DCACHE_ADDR_OFFSET_ED+1) +`define DCACHE_IND_ED (`DCACHE_IND_ST+`DCACHE_IND_NB-1) + +`define DCACHE_ADDR_IND_RNG `DCACHE_IND_ED:`DCACHE_IND_ST +`define DCACHE_IND_SIZE_RNG `DCACHE_IND_NB-1:0 + +`define DCACHE_IND_SIZE_START 0 +`define DCACHE_IND_SIZE_END `DCACHE_IND_NB-1 + + +// Tag +`define DCACHE_ADDR_TAG_RNG 31:(`DCACHE_IND_ED+1) +`define DCACHE_TAG_SIZE_RNG (32-(`DCACHE_IND_ED+1)-1):0 +`define DCACHE_TAG_SIZE_START 0 +`define DCACHE_TAG_SIZE_END (32-(`DCACHE_IND_ED+1)-1) +`define DCACHE_ADDR_TAG_START (`DCACHE_IND_ED+1) +`define DCACHE_ADDR_TAG_END 31 + +// Mask +`define DCACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`DCACHE_BLOCK-1)) +`define ICACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`ICACHE_BLOCK-1)) + + + +/////// + +//`define SHARED_MEMORY_SIZE 4096 +`define SHARED_MEMORY_SIZE 8192 +`define SHARED_MEMORY_BANKS 4 +//`define SHARED_MEMORY_BYTES_PER_READ 16 +//`define SHARED_MEMORY_HEIGHT ((`SHARED_MEMORY_SIZE) / (`SHARED_MEMORY_BANKS * `SHARED_MEMORY_BYTES_PER_READ)) + +//`define SHARED_MEMORY_SIZE 16384 +//`define SHARED_MEMORY_BANKS 8 +`define SHARED_MEMORY_BYTES_PER_READ 16 +//`define SHARED_MEMORY_BITS_PER_BANK 3 +`define SHARED_MEMORY_BITS_PER_BANK `CLOG2(`SHARED_MEMORY_BANKS) +`define SHARED_MEMORY_NUM_REQ `NT +`define SHARED_MEMORY_WORDS_PER_READ (`SHARED_MEMORY_BYTES_PER_READ / 4) +`define SHARED_MEMORY_LOG_WORDS_PER_READ $clog2(`SHARED_MEMORY_WORDS_PER_READ) +`define SHARED_MEMORY_HEIGHT ((`SHARED_MEMORY_SIZE) / (`SHARED_MEMORY_BANKS * `SHARED_MEMORY_BYTES_PER_READ)) + +`define SHARED_MEMORY_BANK_OFFSET_ST (2) +`define SHARED_MEMORY_BANK_OFFSET_ED (2+$clog2(`SHARED_MEMORY_BANKS)-1) +`define SHARED_MEMORY_BLOCK_OFFSET_ST (`SHARED_MEMORY_BANK_OFFSET_ED + 1) +`define SHARED_MEMORY_BLOCK_OFFSET_ED (`SHARED_MEMORY_BLOCK_OFFSET_ST +`SHARED_MEMORY_LOG_WORDS_PER_READ-1) +`define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1) +`define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1) diff --git a/old_rtl/VX_define_synth.v b/old_rtl/VX_define_synth.v new file mode 100644 index 00000000..0444fe94 --- /dev/null +++ b/old_rtl/VX_define_synth.v @@ -0,0 +1,2 @@ +`define NT 4 +`define NW 8 diff --git a/old_rtl/VX_dmem_controller.v b/old_rtl/VX_dmem_controller.v new file mode 100644 index 00000000..39d10b64 --- /dev/null +++ b/old_rtl/VX_dmem_controller.v @@ -0,0 +1,188 @@ + +`include "VX_define.v" + +module VX_dmem_controller ( + input wire clk, + input wire reset, + // MEM-RAM + VX_dram_req_rsp_inter VX_dram_req_rsp, + VX_dram_req_rsp_inter VX_dram_req_rsp_icache, + // MEM-Processor + VX_icache_request_inter VX_icache_req, + VX_icache_response_inter VX_icache_rsp, + VX_dcache_request_inter VX_dcache_req, + VX_dcache_response_inter VX_dcache_rsp +); + + + wire to_shm = VX_dcache_req.out_cache_driver_in_address[0][31:24] == 8'hFF; + + wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{to_shm}}; + wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{~to_shm}}; + + wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|cache_driver_in_valid); + + + + wire[`NT_M1:0][31:0] cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address; + wire[2:0] cache_driver_in_mem_read = !(|cache_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.out_cache_driver_in_mem_read; + wire[2:0] cache_driver_in_mem_write = !(|cache_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.out_cache_driver_in_mem_write; + wire[`NT_M1:0][31:0] cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data; + + + wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.out_cache_driver_in_mem_read; + wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.out_cache_driver_in_mem_write; + + + wire[`NT_M1:0][31:0] cache_driver_out_data; + wire[`NT_M1:0][31:0] sm_driver_out_data; + wire[`NT_M1:0] cache_driver_out_valid; // Not used for now + wire sm_delay; + wire cache_delay; + + + // I_Cache Signals + + wire[31:0] icache_instruction_out; + wire icache_delay; + wire icache_driver_in_valid = VX_icache_req.out_cache_driver_in_valid; + wire[31:0] icache_driver_in_address = VX_icache_req.pc_address; + wire[2:0] icache_driver_in_mem_read = !(|icache_driver_in_valid) ? `NO_MEM_READ : VX_icache_req.out_cache_driver_in_mem_read; + wire[2:0] icache_driver_in_mem_write = !(|icache_driver_in_valid) ? `NO_MEM_WRITE : VX_icache_req.out_cache_driver_in_mem_write; + wire[31:0] icache_driver_in_data = VX_icache_req.out_cache_driver_in_data; + wire read_or_write_ic = (VX_icache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|icache_driver_in_valid); + + wire valid_read_cache = !cache_delay && cache_driver_in_valid[0]; + + + VX_shared_memory #( + .SM_SIZE (`SHARED_MEMORY_SIZE), + .SM_BANKS (`SHARED_MEMORY_BANKS), + .SM_BYTES_PER_READ (`SHARED_MEMORY_BYTES_PER_READ), + .SM_WORDS_PER_READ (`SHARED_MEMORY_WORDS_PER_READ), + .SM_LOG_WORDS_PER_READ (`SHARED_MEMORY_LOG_WORDS_PER_READ), + .SM_BANK_OFFSET_START (`SHARED_MEMORY_BANK_OFFSET_ST), + .SM_BANK_OFFSET_END (`SHARED_MEMORY_BANK_OFFSET_ED), + .SM_BLOCK_OFFSET_START (`SHARED_MEMORY_BLOCK_OFFSET_ST), + .SM_BLOCK_OFFSET_END (`SHARED_MEMORY_BLOCK_OFFSET_ED), + .SM_INDEX_START (`SHARED_MEMORY_INDEX_OFFSET_ST), + .SM_INDEX_END (`SHARED_MEMORY_INDEX_OFFSET_ED), + .SM_HEIGHT (`SHARED_MEMORY_HEIGHT), + .NUM_REQ (`SHARED_MEMORY_NUM_REQ), + .BITS_PER_BANK (`SHARED_MEMORY_BITS_PER_BANK) + ) + shared_memory + ( + .clk (clk), + .reset (reset), + .in_valid (sm_driver_in_valid), + .in_address(cache_driver_in_address), + .in_data (cache_driver_in_data), + .mem_read (sm_driver_in_mem_read), + .mem_write (sm_driver_in_mem_write), + .out_valid (cache_driver_out_valid), + .out_data (sm_driver_out_data), + .stall (sm_delay) + ); + + + VX_d_cache#( + .CACHE_SIZE (`DCACHE_SIZE), + .CACHE_WAYS (`DCACHE_WAYS), + .CACHE_BLOCK (`DCACHE_BLOCK), + .CACHE_BANKS (`DCACHE_BANKS), + .LOG_NUM_BANKS (`DCACHE_LOG_NUM_BANKS), + .NUM_REQ (`DCACHE_NUM_REQ), + .LOG_NUM_REQ (`DCACHE_LOG_NUM_REQ), + .NUM_IND (`DCACHE_NUM_IND), + .CACHE_WAY_INDEX (`DCACHE_WAY_INDEX), + .NUM_WORDS_PER_BLOCK (`DCACHE_NUM_WORDS_PER_BLOCK), + .OFFSET_SIZE_START (`DCACHE_OFFSET_ST), + .OFFSET_SIZE_END (`DCACHE_OFFSET_ED), + .TAG_SIZE_START (`DCACHE_TAG_SIZE_START), + .TAG_SIZE_END (`DCACHE_TAG_SIZE_END), + .IND_SIZE_START (`DCACHE_IND_SIZE_START), + .IND_SIZE_END (`DCACHE_IND_SIZE_END), + .ADDR_TAG_START (`DCACHE_ADDR_TAG_START), + .ADDR_TAG_END (`DCACHE_ADDR_TAG_END), + .ADDR_OFFSET_START (`DCACHE_ADDR_OFFSET_ST), + .ADDR_OFFSET_END (`DCACHE_ADDR_OFFSET_ED), + .ADDR_IND_START (`DCACHE_IND_ST), + .ADDR_IND_END (`DCACHE_IND_ED), + .MEM_ADDR_REQ_MASK (`DCACHE_MEM_REQ_ADDR_MASK) + ) + dcache + ( + .clk (clk), + .rst (reset), + .i_p_valid (cache_driver_in_valid), + .i_p_addr (cache_driver_in_address), + .i_p_writedata (cache_driver_in_data), + .i_p_read_or_write (read_or_write), + .i_p_mem_read (cache_driver_in_mem_read), + .i_p_mem_write (cache_driver_in_mem_write), + .o_p_readdata (cache_driver_out_data), + .o_p_delay (cache_delay), + .o_m_evict_addr (VX_dram_req_rsp.o_m_evict_addr), + .o_m_read_addr (VX_dram_req_rsp.o_m_read_addr), + .o_m_valid (VX_dram_req_rsp.o_m_valid), + .o_m_writedata (VX_dram_req_rsp.o_m_writedata), + .o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write), + .i_m_readdata (VX_dram_req_rsp.i_m_readdata), + .i_m_ready (VX_dram_req_rsp.i_m_ready) + ); + + +VX_d_cache#( + .CACHE_SIZE (`ICACHE_SIZE), + .CACHE_WAYS (`ICACHE_WAYS), + .CACHE_BLOCK (`ICACHE_BLOCK), + .CACHE_BANKS (`ICACHE_BANKS), + .LOG_NUM_BANKS (`ICACHE_LOG_NUM_BANKS), + .NUM_REQ (`ICACHE_NUM_REQ), + .LOG_NUM_REQ (`ICACHE_LOG_NUM_REQ), + .NUM_IND (`ICACHE_NUM_IND), + .CACHE_WAY_INDEX (`ICACHE_WAY_INDEX), + .NUM_WORDS_PER_BLOCK (`ICACHE_NUM_WORDS_PER_BLOCK), + .OFFSET_SIZE_START (`ICACHE_OFFSET_ST), + .OFFSET_SIZE_END (`ICACHE_OFFSET_ED), + .TAG_SIZE_START (`ICACHE_TAG_SIZE_START), + .TAG_SIZE_END (`ICACHE_TAG_SIZE_END), + .IND_SIZE_START (`ICACHE_IND_SIZE_START), + .IND_SIZE_END (`ICACHE_IND_SIZE_END), + .ADDR_TAG_START (`ICACHE_ADDR_TAG_START), + .ADDR_TAG_END (`ICACHE_ADDR_TAG_END), + .ADDR_OFFSET_START (`ICACHE_ADDR_OFFSET_ST), + .ADDR_OFFSET_END (`ICACHE_ADDR_OFFSET_ED), + .ADDR_IND_START (`ICACHE_IND_ST), + .ADDR_IND_END (`ICACHE_IND_ED), + .MEM_ADDR_REQ_MASK (`ICACHE_MEM_REQ_ADDR_MASK) + ) icache + ( + .clk (clk), + .rst (reset), + .i_p_valid (icache_driver_in_valid), + .i_p_addr (icache_driver_in_address), + .i_p_writedata (icache_driver_in_data), + .i_p_read_or_write (read_or_write_ic), + .i_p_mem_read (icache_driver_in_mem_read), + .i_p_mem_write (icache_driver_in_mem_write), + .o_p_readdata (icache_instruction_out), + .o_p_delay (icache_delay), + .o_m_evict_addr (VX_dram_req_rsp_icache.o_m_evict_addr), + .o_m_read_addr (VX_dram_req_rsp_icache.o_m_read_addr), + .o_m_valid (VX_dram_req_rsp_icache.o_m_valid), + .o_m_writedata (VX_dram_req_rsp_icache.o_m_writedata), + .o_m_read_or_write (VX_dram_req_rsp_icache.o_m_read_or_write), + .i_m_readdata (VX_dram_req_rsp_icache.i_m_readdata), + .i_m_ready (VX_dram_req_rsp_icache.i_m_ready) + ); + + assign VX_dcache_rsp.in_cache_driver_out_data = to_shm ? sm_driver_out_data : cache_driver_out_data; + assign VX_dcache_rsp.delay = sm_delay || cache_delay; + + assign VX_icache_rsp.instruction = icache_instruction_out; + assign VX_icache_rsp.delay = icache_delay; + + +endmodule diff --git a/old_rtl/VX_execute_unit.v b/old_rtl/VX_execute_unit.v new file mode 100644 index 00000000..c64c1181 --- /dev/null +++ b/old_rtl/VX_execute_unit.v @@ -0,0 +1,168 @@ +`include "VX_define.v" + +module VX_execute_unit ( + input wire clk, + input wire reset, + // Request + VX_exec_unit_req_inter VX_exec_unit_req, + + // Output + // Writeback + VX_inst_exec_wb_inter VX_inst_exec_wb, + // JAL Response + VX_jal_response_inter VX_jal_rsp, + // Branch Response + VX_branch_response_inter VX_branch_rsp +); + + + + wire[`NT_M1:0][31:0] in_a_reg_data; + wire[`NT_M1:0][31:0] in_b_reg_data; + wire[4:0] in_alu_op; + wire in_rs2_src; + wire[31:0] in_itype_immed; + wire[2:0] in_branch_type; + wire[19:0] in_upper_immed; + wire in_jal; + wire[31:0] in_jal_offset; + wire[31:0] in_curr_PC; + + assign in_a_reg_data = VX_exec_unit_req.a_reg_data; + assign in_b_reg_data = VX_exec_unit_req.b_reg_data; + assign in_alu_op = VX_exec_unit_req.alu_op; + assign in_rs2_src = VX_exec_unit_req.rs2_src; + assign in_itype_immed = VX_exec_unit_req.itype_immed; + assign in_branch_type = VX_exec_unit_req.branch_type; + assign in_upper_immed = VX_exec_unit_req.upper_immed; + assign in_jal = VX_exec_unit_req.jal; + assign in_jal_offset = VX_exec_unit_req.jal_offset; + assign in_curr_PC = VX_exec_unit_req.curr_PC; + + + wire[`NT_M1:0][31:0] alu_result; + genvar index_out_reg; + generate + for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) + begin + VX_alu vx_alu( + // .in_reg_data (in_reg_data[1:0]), + .in_1 (in_a_reg_data[index_out_reg]), + .in_2 (in_b_reg_data[index_out_reg]), + .in_rs2_src (in_rs2_src), + .in_itype_immed(in_itype_immed), + .in_upper_immed(in_upper_immed), + .in_alu_op (in_alu_op), + .in_curr_PC (in_curr_PC), + .out_alu_result(alu_result[index_out_reg]) + ); + end + endgenerate + + + wire [$clog2(`NT)-1:0] jal_branch_use_index; + wire jal_branch_found_valid; + VX_generic_priority_encoder #(.N(`NT)) choose_alu_result( + .valids(VX_exec_unit_req.valid), + .index (jal_branch_use_index), + .found (jal_branch_found_valid) + ); + + wire[31:0] branch_use_alu_result = alu_result[jal_branch_use_index]; + + reg temp_branch_dir; + always @(*) + begin + case(VX_exec_unit_req.branch_type) + `BEQ: temp_branch_dir = (branch_use_alu_result == 0) ? `TAKEN : `NOT_TAKEN; + `BNE: temp_branch_dir = (branch_use_alu_result == 0) ? `NOT_TAKEN : `TAKEN; + `BLT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; + `BGT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; + `BLTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; + `BGTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; + `NO_BRANCH: temp_branch_dir = `NOT_TAKEN; + default: temp_branch_dir = `NOT_TAKEN; + endcase // in_branch_type + end + + + wire[`NT_M1:0][31:0] duplicate_PC_data; + genvar i; + generate + for (i = 0; i < `NT; i=i+1) + begin + assign duplicate_PC_data[i] = VX_exec_unit_req.PC_next; + end + endgenerate + + + // VX_inst_exec_wb_inter VX_inst_exec_wb_temp(); + // JAL Response + VX_jal_response_inter VX_jal_rsp_temp(); + // Branch Response + VX_branch_response_inter VX_branch_rsp_temp(); + + // Actual Writeback + assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd; + assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb; + assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid; + assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num; + assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result; + + assign VX_inst_exec_wb.exec_wb_pc = in_curr_PC; + // Jal rsp + assign VX_jal_rsp_temp.jal = in_jal; + assign VX_jal_rsp_temp.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); + assign VX_jal_rsp_temp.jal_warp_num = VX_exec_unit_req.warp_num; + + // Branch rsp + assign VX_branch_rsp_temp.valid_branch = (VX_exec_unit_req.branch_type != `NO_BRANCH) && (|VX_exec_unit_req.valid); + assign VX_branch_rsp_temp.branch_dir = temp_branch_dir; + assign VX_branch_rsp_temp.branch_warp_num = VX_exec_unit_req.warp_num; + assign VX_branch_rsp_temp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset + + + wire zero = 0; + + // VX_generic_register #(.N(174)) exec_reg( + // .clk (clk), + // .reset(reset), + // .stall(zero), + // .flush(zero), + // .in ({VX_inst_exec_wb_temp.rd, VX_inst_exec_wb_temp.wb, VX_inst_exec_wb_temp.wb_valid, VX_inst_exec_wb_temp.wb_warp_num, VX_inst_exec_wb_temp.alu_result, VX_inst_exec_wb_temp.exec_wb_pc}), + // .out ({VX_inst_exec_wb.rd , VX_inst_exec_wb.wb , VX_inst_exec_wb.wb_valid , VX_inst_exec_wb.wb_warp_num , VX_inst_exec_wb.alu_result , VX_inst_exec_wb.exec_wb_pc }) + // ); + + VX_generic_register #(.N(33 + `NW_M1 + 1)) jal_reg( + .clk (clk), + .reset(reset), + .stall(zero), + .flush(zero), + .in ({VX_jal_rsp_temp.jal, VX_jal_rsp_temp.jal_dest, VX_jal_rsp_temp.jal_warp_num}), + .out ({VX_jal_rsp.jal , VX_jal_rsp.jal_dest , VX_jal_rsp.jal_warp_num}) + ); + + VX_generic_register #(.N(34 + `NW_M1 + 1)) branch_reg( + .clk (clk), + .reset(reset), + .stall(zero), + .flush(zero), + .in ({VX_branch_rsp_temp.valid_branch, VX_branch_rsp_temp.branch_dir, VX_branch_rsp_temp.branch_warp_num, VX_branch_rsp_temp.branch_dest}), + .out ({VX_branch_rsp.valid_branch , VX_branch_rsp.branch_dir , VX_branch_rsp.branch_warp_num , VX_branch_rsp.branch_dest }) + ); + + // always @(*) begin + // case(in_alu_op) + // `CSR_ALU_RW: out_csr_result = in_csr_mask; + // `CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask; + // `CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask); + // default: out_csr_result = 32'hdeadbeef; + // endcase + + // end + + + // assign out_is_csr = VX_exec_unit_req.is_csr; + // assign out_csr_address = VX_exec_unit_req.csr_address; + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_fetch.v b/old_rtl/VX_fetch.v new file mode 100644 index 00000000..d71df00f --- /dev/null +++ b/old_rtl/VX_fetch.v @@ -0,0 +1,103 @@ + +`include "VX_define.v" + +module VX_fetch ( + input wire clk, + input wire reset, + VX_wstall_inter VX_wstall, + VX_join_inter VX_join, + input wire schedule_delay, + VX_icache_response_inter icache_response, + VX_icache_request_inter icache_request, + + output wire out_ebreak, + VX_jal_response_inter VX_jal_rsp, + VX_branch_response_inter VX_branch_rsp, + VX_inst_meta_inter fe_inst_meta_fd, + VX_warp_ctl_inter VX_warp_ctl +); + + // Locals + wire pipe_stall; + + + assign pipe_stall = schedule_delay || icache_response.delay; + + wire[`NT_M1:0] thread_mask; + wire[`NW_M1:0] warp_num; + wire[31:0] warp_pc; + wire scheduled_warp; + VX_warp_scheduler warp_scheduler( + .clk (clk), + .reset (reset), + .stall (pipe_stall), + + .is_barrier (VX_warp_ctl.is_barrier), + .barrier_id (VX_warp_ctl.barrier_id), + .num_warps (VX_warp_ctl.num_warps), + .barrier_warp_num (VX_warp_ctl.warp_num), + + // Wspawn + .wspawn (VX_warp_ctl.wspawn), + .wsapwn_pc (VX_warp_ctl.wspawn_pc), + .wspawn_new_active(VX_warp_ctl.wspawn_new_active), + // CTM + .ctm (VX_warp_ctl.change_mask), + .ctm_mask (VX_warp_ctl.thread_mask), + .ctm_warp_num (VX_warp_ctl.warp_num), + // WHALT + .whalt (VX_warp_ctl.ebreak), + .whalt_warp_num (VX_warp_ctl.warp_num), + // Wstall + .wstall (VX_wstall.wstall), + .wstall_warp_num (VX_wstall.warp_num), + + // Join + .is_join (VX_join.is_join), + .join_warp_num (VX_join.join_warp_num), + + // Split + .is_split (VX_warp_ctl.is_split), + .dont_split (VX_warp_ctl.dont_split), + .split_new_mask (VX_warp_ctl.split_new_mask), + .split_later_mask (VX_warp_ctl.split_later_mask), + .split_save_pc (VX_warp_ctl.split_save_pc), + .split_warp_num (VX_warp_ctl.warp_num), + + // JAL + .jal (VX_jal_rsp.jal), + .jal_dest (VX_jal_rsp.jal_dest), + .jal_warp_num (VX_jal_rsp.jal_warp_num), + + // Branch + .branch_valid (VX_branch_rsp.valid_branch), + .branch_dir (VX_branch_rsp.branch_dir), + .branch_dest (VX_branch_rsp.branch_dest), + .branch_warp_num (VX_branch_rsp.branch_warp_num), + + // Outputs + .thread_mask (thread_mask), + .warp_num (warp_num), + .warp_pc (warp_pc), + .out_ebreak (out_ebreak), + .scheduled_warp (scheduled_warp) + ); + + // always @(*) begin + // $display("Inside verilog instr: %h, pc: %h", icache_response.instruction, warp_pc); + // end + + assign icache_request.pc_address = warp_pc; + assign icache_request.out_cache_driver_in_valid = !schedule_delay && scheduled_warp; + assign icache_request.out_cache_driver_in_mem_read = `LW_MEM_READ; + assign icache_request.out_cache_driver_in_mem_write = `NO_MEM_WRITE; + assign icache_request.out_cache_driver_in_data = 32'b0; + + assign fe_inst_meta_fd.warp_num = warp_num; + assign fe_inst_meta_fd.valid = thread_mask; + + assign fe_inst_meta_fd.instruction = (thread_mask == 0) ? 32'b0 : icache_response.instruction; + assign fe_inst_meta_fd.inst_pc = warp_pc; + + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_front_end.v b/old_rtl/VX_front_end.v new file mode 100644 index 00000000..eaf5e8c9 --- /dev/null +++ b/old_rtl/VX_front_end.v @@ -0,0 +1,89 @@ +`include "VX_define.v" + +module VX_front_end ( + input wire clk, + input wire reset, + + input wire schedule_delay, + + VX_warp_ctl_inter VX_warp_ctl, + + VX_icache_response_inter icache_response_fe, + VX_icache_request_inter icache_request_fe, + + VX_jal_response_inter VX_jal_rsp, + VX_branch_response_inter VX_branch_rsp, + + VX_frE_to_bckE_req_inter VX_bckE_req, + + output wire fetch_ebreak +); + + +VX_inst_meta_inter fe_inst_meta_fd(); + +VX_frE_to_bckE_req_inter VX_frE_to_bckE_req(); +VX_inst_meta_inter fd_inst_meta_de(); + +wire total_freeze = schedule_delay; + +/* verilator lint_off UNUSED */ +// wire real_fetch_ebreak; +/* verilator lint_on UNUSED */ + +wire vortex_ebreak; +wire terminate_sim; + +assign fetch_ebreak = vortex_ebreak || terminate_sim; + + +VX_wstall_inter VX_wstall(); +VX_join_inter VX_join(); + +VX_fetch vx_fetch( + .clk (clk), + .reset (reset), + .VX_wstall (VX_wstall), + .VX_join (VX_join), + .schedule_delay (schedule_delay), + .VX_jal_rsp (VX_jal_rsp), + .icache_response (icache_response_fe), + .VX_warp_ctl (VX_warp_ctl), + + .icache_request (icache_request_fe), + .VX_branch_rsp (VX_branch_rsp), + .out_ebreak (vortex_ebreak), // fetch_ebreak + .fe_inst_meta_fd (fe_inst_meta_fd) + ); + +VX_f_d_reg vx_f_d_reg( + .clk (clk), + .reset (reset), + .in_freeze (total_freeze), + .fe_inst_meta_fd(fe_inst_meta_fd), + .fd_inst_meta_de(fd_inst_meta_de) + ); + + +VX_decode vx_decode( + .fd_inst_meta_de (fd_inst_meta_de), + .VX_frE_to_bckE_req(VX_frE_to_bckE_req), + .VX_wstall (VX_wstall), + .VX_join (VX_join), + .terminate_sim (terminate_sim) + ); + +wire no_br_stall = 0; + +VX_d_e_reg vx_d_e_reg( + .clk (clk), + .reset (reset), + .in_branch_stall(no_br_stall), + .in_freeze (total_freeze), + .VX_frE_to_bckE_req(VX_frE_to_bckE_req), + .VX_bckE_req (VX_bckE_req) + ); + +endmodule + + diff --git a/old_rtl/VX_generic_priority_encoder.v b/old_rtl/VX_generic_priority_encoder.v new file mode 100644 index 00000000..6bef1a4f --- /dev/null +++ b/old_rtl/VX_generic_priority_encoder.v @@ -0,0 +1,27 @@ +`include "../VX_define.v" + +module VX_generic_priority_encoder + #( + parameter N = 1 + ) + ( + input wire[N-1:0] valids, + //output reg[$clog2(N)-1:0] index, + output reg[(`CLOG2(N))-1:0] index, + //output reg[`CLOG2(N):0] index, // eh + output reg found + ); + + integer i; + always @(*) begin + index = 0; + found = 0; + for (i = N-1; i >= 0; i = i - 1) begin + if (valids[i]) begin + //index = i[$clog2(N)-1:0]; + index = i[(`CLOG2(N))-1:0]; + found = 1; + end + end + end +endmodule \ No newline at end of file diff --git a/old_rtl/VX_generic_register.v b/old_rtl/VX_generic_register.v new file mode 100644 index 00000000..7a1a023d --- /dev/null +++ b/old_rtl/VX_generic_register.v @@ -0,0 +1,34 @@ + + +module VX_generic_register + #( + parameter N = 1 + ) + ( + input clk, + input reset, + input stall, + input flush, + input[N-1:0] in, + output [N-1:0] out + ); + + + reg[N-1:0] value; + + + + always @(posedge clk or posedge reset) begin + if (reset) begin + value <= 0; + end else if (flush) begin + value <= 0; + end else if (~stall) begin + value <= in; + end + end + + + assign out = value; + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_generic_stack.v b/old_rtl/VX_generic_stack.v new file mode 100644 index 00000000..cdac974f --- /dev/null +++ b/old_rtl/VX_generic_stack.v @@ -0,0 +1,38 @@ +module VX_generic_stack + #( + parameter WIDTH = 40, + parameter DEPTH = 2 + ) + ( + input wire clk, + input wire reset, + input wire push, + input wire pop, + input reg [WIDTH - 1:0] q1, + input reg [WIDTH - 1:0] q2, + output wire[WIDTH - 1:0] d + ); + + + reg [DEPTH - 1:0] ptr; + reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1]; + + integer i; + always @(posedge clk) begin + if (reset) begin + ptr <= 0; + for (i = 0; i < (1 << DEPTH); i=i+1) stack[i] <= 0; + end else if (push) begin + stack[ptr] <= q1; + stack[ptr+1] <= q2; + ptr <= ptr + 2; + end else if (pop) begin + ptr <= ptr - 1; + end + + end + + + assign d = stack[ptr - 1]; + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_gpgpu_inst.v b/old_rtl/VX_gpgpu_inst.v new file mode 100644 index 00000000..01a50515 --- /dev/null +++ b/old_rtl/VX_gpgpu_inst.v @@ -0,0 +1,85 @@ +`include "VX_define.v" + +module VX_gpgpu_inst ( + // Input + VX_gpu_inst_req_inter VX_gpu_inst_req, + + // Output + VX_warp_ctl_inter VX_warp_ctl +); + + + wire[`NT_M1:0] curr_valids = VX_gpu_inst_req.valid; + wire is_split = (VX_gpu_inst_req.is_split); + + wire[`NT_M1:0] tmc_new_mask; + genvar curr_t; + for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) + begin + assign tmc_new_mask[curr_t] = curr_t < VX_gpu_inst_req.a_reg_data[0]; + end + + wire valid_inst = (|curr_valids); + + assign VX_warp_ctl.warp_num = VX_gpu_inst_req.warp_num; + assign VX_warp_ctl.change_mask = (VX_gpu_inst_req.is_tmc) && valid_inst; + assign VX_warp_ctl.thread_mask = VX_gpu_inst_req.is_tmc ? tmc_new_mask : 0; + + // assign VX_warp_ctl.ebreak = (VX_gpu_inst_req.a_reg_data[0] == 0) && valid_inst; + assign VX_warp_ctl.ebreak = VX_warp_ctl.change_mask && (VX_warp_ctl.thread_mask == 0); + + + wire wspawn = VX_gpu_inst_req.is_wspawn; + wire[31:0] wspawn_pc = VX_gpu_inst_req.rd2; + wire[`NW-1:0] wspawn_new_active; + genvar curr_w; + for (curr_w = 0; curr_w < `NW; curr_w=curr_w+1) + begin + assign wspawn_new_active[curr_w] = curr_w < VX_gpu_inst_req.a_reg_data[0]; + end + + + assign VX_warp_ctl.is_barrier = VX_gpu_inst_req.is_barrier && valid_inst; + assign VX_warp_ctl.barrier_id = VX_gpu_inst_req.a_reg_data[0]; + + wire[31:0] num_warps_m1 = VX_gpu_inst_req.rd2 - 1; + assign VX_warp_ctl.num_warps = num_warps_m1[$clog2(`NW):0]; + + assign VX_warp_ctl.wspawn = wspawn; + assign VX_warp_ctl.wspawn_pc = wspawn_pc; + assign VX_warp_ctl.wspawn_new_active = wspawn_new_active; + + wire[`NT_M1:0] split_new_use_mask; + wire[`NT_M1:0] split_new_later_mask; + + // VX_gpu_inst_req.pc + genvar curr_s_t; + for (curr_s_t = 0; curr_s_t < `NT; curr_s_t=curr_s_t+1) begin + wire curr_bool = (VX_gpu_inst_req.a_reg_data[curr_s_t] == 32'b1); + + assign split_new_use_mask[curr_s_t] = curr_valids[curr_s_t] & (curr_bool); + assign split_new_later_mask[curr_s_t] = curr_valids[curr_s_t] & (!curr_bool); + end + + wire[$clog2(`NT):0] num_valids; + + VX_countones #(.N(`NT)) valids_counter ( + .valids(curr_valids), + .count (num_valids) + ); + + // wire[`NW_M1:0] num_valids = $countones(curr_valids); + + + assign VX_warp_ctl.is_split = is_split && (num_valids > 1); + assign VX_warp_ctl.dont_split = VX_warp_ctl.is_split && ((split_new_use_mask == 0) || (split_new_use_mask == {`NT{1'b1}})); + assign VX_warp_ctl.split_new_mask = split_new_use_mask; + assign VX_warp_ctl.split_later_mask = split_new_later_mask; + assign VX_warp_ctl.split_save_pc = VX_gpu_inst_req.pc_next; + assign VX_warp_ctl.split_warp_num = VX_gpu_inst_req.warp_num; + + // VX_gpu_inst_req.is_wspawn + // VX_gpu_inst_req.is_split + // VX_gpu_inst_req.is_barrier + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_gpr.v b/old_rtl/VX_gpr.v new file mode 100644 index 00000000..6f239c51 --- /dev/null +++ b/old_rtl/VX_gpr.v @@ -0,0 +1,172 @@ + +`include "VX_define.v" + +module VX_gpr ( + input wire clk, + input wire reset, + input wire valid_write_request, + VX_gpr_read_inter VX_gpr_read, + VX_wb_inter VX_writeback_inter, + + output reg[`NT_M1:0][31:0] out_a_reg_data, + output reg[`NT_M1:0][31:0] out_b_reg_data +); + + + + wire write_enable; + + + `ifndef ASIC + assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0)) && (VX_writeback_inter.rd != 0); + + byte_enabled_simple_dual_port_ram first_ram( + .we (write_enable), + .clk (clk), + .reset (reset), + .waddr (VX_writeback_inter.rd), + .raddr1(VX_gpr_read.rs1), + .raddr2(VX_gpr_read.rs2), + .be (VX_writeback_inter.wb_valid), + .wdata (VX_writeback_inter.write_data), + .q1 (out_a_reg_data), + .q2 (out_b_reg_data) + ); + + `else + + assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0)); + + + wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid); + + + wire[`NT_M1:0][31:0] write_bit_mask; + + genvar curr_t; + for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin + wire local_write = write_enable & VX_writeback_inter.wb_valid[curr_t]; + assign write_bit_mask[curr_t] = {32{~local_write}}; + end + + + + // wire cenb = !going_to_write; + wire cenb = 0; + + // wire cena_1 = (VX_gpr_read.rs1 == 0); + // wire cena_2 = (VX_gpr_read.rs2 == 0); + wire cena_1 = 0; + wire cena_2 = 0; + + wire[`NT_M1:0][31:0] temp_a; + wire[`NT_M1:0][31:0] temp_b; + + + `ifndef SYN + genvar thread; + genvar curr_bit; + for (thread = 0; thread < `NT; thread = thread + 1) + begin + for (curr_bit = 0; curr_bit < 32; curr_bit=curr_bit+1) + begin + assign out_a_reg_data[thread][curr_bit] = ((temp_a[thread][curr_bit] === 1'dx) || cena_1 )? 1'b0 : temp_a[thread][curr_bit]; + assign out_b_reg_data[thread][curr_bit] = ((temp_b[thread][curr_bit] === 1'dx) || cena_2) ? 1'b0 : temp_b[thread][curr_bit]; + end + end + + `else + + assign out_a_reg_data = temp_a; + assign out_b_reg_data = temp_b; + + `endif + + + wire[`NT_M1:0][31:0] to_write = (VX_writeback_inter.rd != 0) ? VX_writeback_inter.write_data : 0; + + genvar curr_base_thread; + for (curr_base_thread = 0; curr_base_thread < 'NT; curr_base_thread=curr_base_thread+4) + begin + /* verilator lint_off PINCONNECTEMPTY */ + rf2_32x128_wm1 first_ram ( + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(temp_a[(curr_base_thread+3):(curr_base_thread)]), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena_1), + .AA(VX_gpr_read.rs1[(curr_base_thread+3):(curr_base_thread)]), + .CLKB(clk), + .CENB(cenb), + .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), + .AB(VX_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), + .DB(to_write[(curr_base_thread+3):(curr_base_thread)]), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(5'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + /* verilator lint_on PINCONNECTEMPTY */ + + /* verilator lint_off PINCONNECTEMPTY */ + rf2_32x128_wm1 second_ram ( + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(temp_b[(curr_base_thread+3):(curr_base_thread)]), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena_2), + .AA(VX_gpr_read.rs2[(curr_base_thread+3):(curr_base_thread)]), + .CLKB(clk), + .CENB(cenb), + .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), + .AB(VX_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), + .DB(to_write[(curr_base_thread+3):(curr_base_thread)]), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(5'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + /* verilator lint_on PINCONNECTEMPTY */ + end + + `endif + +endmodule diff --git a/old_rtl/VX_gpr_stage.v b/old_rtl/VX_gpr_stage.v new file mode 100644 index 00000000..22fea9d6 --- /dev/null +++ b/old_rtl/VX_gpr_stage.v @@ -0,0 +1,223 @@ + +`include "VX_define.v" + +module VX_gpr_stage ( + input wire clk, + input wire reset, + input wire schedule_delay, + + input wire memory_delay, + input wire stall_gpr_csr, + output wire gpr_stage_delay, + + // inputs + // Instruction Information + VX_frE_to_bckE_req_inter VX_bckE_req, + + // WriteBack inputs + VX_wb_inter VX_writeback_inter, + + + + + // Outputs + VX_exec_unit_req_inter VX_exec_unit_req, + VX_lsu_req_inter VX_lsu_req, + VX_gpu_inst_req_inter VX_gpu_inst_req, + VX_csr_req_inter VX_csr_req +); + + + wire[31:0] curr_PC = VX_bckE_req.curr_PC; + wire[2:0] branchType = VX_bckE_req.branch_type; + + wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE); + wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ); + + + wire jalQual = VX_bckE_req.jalQual; + + VX_gpr_read_inter VX_gpr_read(); + assign VX_gpr_read.rs1 = VX_bckE_req.rs1; + assign VX_gpr_read.rs2 = VX_bckE_req.rs2; + assign VX_gpr_read.warp_num = VX_bckE_req.warp_num; + + `ifndef ASIC + VX_gpr_jal_inter VX_gpr_jal(); + assign VX_gpr_jal.is_jal = VX_bckE_req.jalQual; + assign VX_gpr_jal.curr_PC = VX_bckE_req.curr_PC; + `else + VX_gpr_jal_inter VX_gpr_jal(); + assign VX_gpr_jal.is_jal = VX_exec_unit_req.jalQual; + assign VX_gpr_jal.curr_PC = VX_exec_unit_req.curr_PC; + `endif + + + VX_gpr_data_inter VX_gpr_datf(); + + + VX_gpr_wrapper vx_grp_wrapper( + .clk (clk), + .reset (reset), + .VX_writeback_inter(VX_writeback_inter), + .VX_gpr_read (VX_gpr_read), + .VX_gpr_jal (VX_gpr_jal), + + .out_a_reg_data (VX_gpr_datf.a_reg_data), + .out_b_reg_data (VX_gpr_datf.b_reg_data) + ); + + // assign VX_bckE_req.is_csr = is_csr; + // assign VX_bckE_req_out.csr_mask = (VX_bckE_req.sr_immed == 1'b1) ? {27'h0, VX_bckE_req.rs1} : VX_gpr_data.a_reg_data[0]; + + // Outputs + VX_exec_unit_req_inter VX_exec_unit_req_temp(); + VX_lsu_req_inter VX_lsu_req_temp(); + VX_gpu_inst_req_inter VX_gpu_inst_req_temp(); + VX_csr_req_inter VX_csr_req_temp(); + + VX_inst_multiplex VX_inst_mult( + .VX_bckE_req (VX_bckE_req), + .VX_gpr_data (VX_gpr_datf), + .VX_exec_unit_req(VX_exec_unit_req_temp), + .VX_lsu_req (VX_lsu_req_temp), + .VX_gpu_inst_req (VX_gpu_inst_req_temp), + .VX_csr_req (VX_csr_req_temp) + ); + + wire is_lsu = (|VX_lsu_req_temp.valid); + + wire stall_rest = 0; + wire flush_rest = schedule_delay; + + + wire stall_lsu = memory_delay; + wire flush_lsu = schedule_delay && !stall_lsu; + + assign gpr_stage_delay = stall_lsu || (stall_gpr_csr && VX_bckE_req.is_csr && (|VX_bckE_req.valid)); + + `ifdef ASIC + wire delayed_lsu_last_cycle; + + VX_generic_register #(.N(1)) delayed_reg ( + .clk (clk), + .reset(reset), + .stall(stall_rest), + .flush(stall_rest), + .in (stall_lsu), + .out (delayed_lsu_last_cycle) + ); + + + wire[`NT_M1:0][31:0] temp_store_data; + wire[`NT_M1:0][31:0] temp_base_address; // A reg data + + wire[`NT_M1:0][31:0] real_store_data; + wire[`NT_M1:0][31:0] real_base_address; // A reg data + + wire store_curr_real = !delayed_lsu_last_cycle && stall_lsu; + + VX_generic_register #(.N(`NT*32*2)) lsu_data( + .clk (clk), + .reset(reset), + .stall(!store_curr_real), + .flush(stall_rest), + .in ({real_store_data, real_base_address}), + .out ({temp_store_data, temp_base_address}) + ); + + assign real_store_data = VX_lsu_req_temp.store_data; + assign real_base_address = VX_lsu_req_temp.base_address; + + + assign VX_lsu_req.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data; + assign VX_lsu_req.base_address = (delayed_lsu_last_cycle) ? temp_base_address : real_base_address; + + + VX_generic_register #(.N(77 + `NW_M1 + 1 + (`NT))) lsu_reg( + .clk (clk), + .reset(reset), + .stall(stall_lsu), + .flush(flush_lsu), + .in ({VX_lsu_req_temp.valid, VX_lsu_req_temp.lsu_pc, VX_lsu_req_temp.warp_num, VX_lsu_req_temp.offset, VX_lsu_req_temp.mem_read, VX_lsu_req_temp.mem_write, VX_lsu_req_temp.rd, VX_lsu_req_temp.wb}), + .out ({VX_lsu_req.valid , VX_lsu_req.lsu_pc ,VX_lsu_req.warp_num , VX_lsu_req.offset , VX_lsu_req.mem_read , VX_lsu_req.mem_write , VX_lsu_req.rd , VX_lsu_req.wb }) + ); + + VX_generic_register #(.N(224 + `NW_M1 + 1 + (`NT))) exec_unit_reg( + .clk (clk), + .reset(reset), + .stall(stall_rest), + .flush(flush_rest), + .in ({VX_exec_unit_req_temp.valid, VX_exec_unit_req_temp.warp_num, VX_exec_unit_req_temp.curr_PC, VX_exec_unit_req_temp.PC_next, VX_exec_unit_req_temp.rd, VX_exec_unit_req_temp.wb, VX_exec_unit_req_temp.alu_op, VX_exec_unit_req_temp.rs1, VX_exec_unit_req_temp.rs2, VX_exec_unit_req_temp.rs2_src, VX_exec_unit_req_temp.itype_immed, VX_exec_unit_req_temp.upper_immed, VX_exec_unit_req_temp.branch_type, VX_exec_unit_req_temp.jalQual, VX_exec_unit_req_temp.jal, VX_exec_unit_req_temp.jal_offset, VX_exec_unit_req_temp.ebreak, VX_exec_unit_req_temp.wspawn, VX_exec_unit_req_temp.is_csr, VX_exec_unit_req_temp.csr_address, VX_exec_unit_req_temp.csr_immed, VX_exec_unit_req_temp.csr_mask}), + .out ({VX_exec_unit_req.valid , VX_exec_unit_req.warp_num , VX_exec_unit_req.curr_PC , VX_exec_unit_req.PC_next , VX_exec_unit_req.rd , VX_exec_unit_req.wb , VX_exec_unit_req.alu_op , VX_exec_unit_req.rs1 , VX_exec_unit_req.rs2 , VX_exec_unit_req.rs2_src , VX_exec_unit_req.itype_immed , VX_exec_unit_req.upper_immed , VX_exec_unit_req.branch_type , VX_exec_unit_req.jalQual , VX_exec_unit_req.jal , VX_exec_unit_req.jal_offset , VX_exec_unit_req.ebreak , VX_exec_unit_req.wspawn , VX_exec_unit_req.is_csr , VX_exec_unit_req.csr_address , VX_exec_unit_req.csr_immed , VX_exec_unit_req.csr_mask }) + ); + + assign VX_exec_unit_req.a_reg_data = real_base_address; + assign VX_exec_unit_req.b_reg_data = real_store_data; + + VX_generic_register #(.N(36 + `NW_M1 + 1 + (`NT))) gpu_inst_reg( + .clk (clk), + .reset(reset), + .stall(stall_rest), + .flush(flush_rest), + .in ({VX_gpu_inst_req_temp.valid, VX_gpu_inst_req_temp.warp_num, VX_gpu_inst_req_temp.is_wspawn, VX_gpu_inst_req_temp.is_tmc, VX_gpu_inst_req_temp.is_split, VX_gpu_inst_req_temp.is_barrier, VX_gpu_inst_req_temp.pc_next}), + .out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next }) + ); + + assign VX_gpu_inst_req.a_reg_data = real_base_address; + assign VX_gpu_inst_req.rd2 = real_store_data; + + VX_generic_register #(.N(`NW_M1 + 1 + `NT + 58)) csr_reg( + .clk (clk), + .reset(reset), + .stall(stall_gpr_csr), + .flush(flush_rest), + .in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}), + .out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask }) + ); + + + // assign + + `else + + // 341 + VX_generic_register #(.N(77 + `NW_M1 + 1 + 65*(`NT))) lsu_reg( + .clk (clk), + .reset(reset), + .stall(stall_lsu), + .flush(flush_lsu), + .in ({VX_lsu_req_temp.valid, VX_lsu_req_temp.lsu_pc, VX_lsu_req_temp.warp_num, VX_lsu_req_temp.store_data, VX_lsu_req_temp.base_address, VX_lsu_req_temp.offset, VX_lsu_req_temp.mem_read, VX_lsu_req_temp.mem_write, VX_lsu_req_temp.rd, VX_lsu_req_temp.wb}), + .out ({VX_lsu_req.valid , VX_lsu_req.lsu_pc , VX_lsu_req.warp_num , VX_lsu_req.store_data , VX_lsu_req.base_address , VX_lsu_req.offset , VX_lsu_req.mem_read , VX_lsu_req.mem_write , VX_lsu_req.rd , VX_lsu_req.wb }) + ); + + VX_generic_register #(.N(224 + `NW_M1 + 1 + 65*(`NT))) exec_unit_reg( + .clk (clk), + .reset(reset), + .stall(stall_rest), + .flush(flush_rest), + .in ({VX_exec_unit_req_temp.valid, VX_exec_unit_req_temp.warp_num, VX_exec_unit_req_temp.curr_PC, VX_exec_unit_req_temp.PC_next, VX_exec_unit_req_temp.rd, VX_exec_unit_req_temp.wb, VX_exec_unit_req_temp.a_reg_data, VX_exec_unit_req_temp.b_reg_data, VX_exec_unit_req_temp.alu_op, VX_exec_unit_req_temp.rs1, VX_exec_unit_req_temp.rs2, VX_exec_unit_req_temp.rs2_src, VX_exec_unit_req_temp.itype_immed, VX_exec_unit_req_temp.upper_immed, VX_exec_unit_req_temp.branch_type, VX_exec_unit_req_temp.jalQual, VX_exec_unit_req_temp.jal, VX_exec_unit_req_temp.jal_offset, VX_exec_unit_req_temp.ebreak, VX_exec_unit_req_temp.wspawn, VX_exec_unit_req_temp.is_csr, VX_exec_unit_req_temp.csr_address, VX_exec_unit_req_temp.csr_immed, VX_exec_unit_req_temp.csr_mask}), + .out ({VX_exec_unit_req.valid , VX_exec_unit_req.warp_num , VX_exec_unit_req.curr_PC , VX_exec_unit_req.PC_next , VX_exec_unit_req.rd , VX_exec_unit_req.wb , VX_exec_unit_req.a_reg_data , VX_exec_unit_req.b_reg_data , VX_exec_unit_req.alu_op , VX_exec_unit_req.rs1 , VX_exec_unit_req.rs2 , VX_exec_unit_req.rs2_src , VX_exec_unit_req.itype_immed , VX_exec_unit_req.upper_immed , VX_exec_unit_req.branch_type , VX_exec_unit_req.jalQual , VX_exec_unit_req.jal , VX_exec_unit_req.jal_offset , VX_exec_unit_req.ebreak , VX_exec_unit_req.wspawn , VX_exec_unit_req.is_csr , VX_exec_unit_req.csr_address , VX_exec_unit_req.csr_immed , VX_exec_unit_req.csr_mask }) + ); + + VX_generic_register #(.N(68 + `NW_M1 + 1 + 33*(`NT))) gpu_inst_reg( + .clk (clk), + .reset(reset), + .stall(stall_rest), + .flush(flush_rest), + .in ({VX_gpu_inst_req_temp.valid, VX_gpu_inst_req_temp.warp_num, VX_gpu_inst_req_temp.is_wspawn, VX_gpu_inst_req_temp.is_tmc, VX_gpu_inst_req_temp.is_split, VX_gpu_inst_req_temp.is_barrier, VX_gpu_inst_req_temp.pc_next, VX_gpu_inst_req_temp.a_reg_data, VX_gpu_inst_req_temp.rd2}), + .out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next , VX_gpu_inst_req.a_reg_data , VX_gpu_inst_req.rd2 }) + ); + + VX_generic_register #(.N(`NW_M1 + 1 + `NT + 58)) csr_reg( + .clk (clk), + .reset(reset), + .stall(stall_gpr_csr), + .flush(flush_rest), + .in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}), + .out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask }) + ); + + `endif + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_gpr_wrapper.v b/old_rtl/VX_gpr_wrapper.v new file mode 100644 index 00000000..2f2ec4e0 --- /dev/null +++ b/old_rtl/VX_gpr_wrapper.v @@ -0,0 +1,70 @@ +`include "VX_define.v" + +module VX_gpr_wrapper ( + input wire clk, + input wire reset, + VX_gpr_read_inter VX_gpr_read, + VX_wb_inter VX_writeback_inter, + VX_gpr_jal_inter VX_gpr_jal, + + output wire[`NT_M1:0][31:0] out_a_reg_data, + output wire[`NT_M1:0][31:0] out_b_reg_data + +); + + wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data; + wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data; + + wire[`NT_M1:0][31:0] jal_data; + genvar index; + for (index = 0; index <= `NT_M1; index = index + 1) begin + assign jal_data[index] = VX_gpr_jal.curr_PC; + end + + + `ifndef ASIC + assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[VX_gpr_read.warp_num])); + assign out_b_reg_data = (temp_b_reg_data[VX_gpr_read.warp_num]); + `else + + wire zer = 0; + + wire[`NW_M1:0] old_warp_num; + VX_generic_register #(`NW_M1+1) store_wn( + .clk (clk), + .reset(reset), + .stall(zer), + .flush(zer), + .in (VX_gpr_read.warp_num), + .out (old_warp_num) + ); + + assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[old_warp_num])); + assign out_b_reg_data = (temp_b_reg_data[old_warp_num]); + + `endif + + genvar warp_index; + generate + + for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin + + wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num; + VX_gpr vx_gpr( + .clk (clk), + .reset (reset), + .valid_write_request(valid_write_request), + .VX_gpr_read (VX_gpr_read), + .VX_writeback_inter (VX_writeback_inter), + .out_a_reg_data (temp_a_reg_data[warp_index]), + .out_b_reg_data (temp_b_reg_data[warp_index]) + ); + + end + + endgenerate + + +endmodule + + diff --git a/old_rtl/VX_inst_multiplex.v b/old_rtl/VX_inst_multiplex.v new file mode 100644 index 00000000..86da67de --- /dev/null +++ b/old_rtl/VX_inst_multiplex.v @@ -0,0 +1,95 @@ +`include "VX_define.v" + +module VX_inst_multiplex ( + // Inputs + VX_frE_to_bckE_req_inter VX_bckE_req, + VX_gpr_data_inter VX_gpr_data, + + // Outputs + VX_exec_unit_req_inter VX_exec_unit_req, + VX_lsu_req_inter VX_lsu_req, + VX_gpu_inst_req_inter VX_gpu_inst_req, + VX_csr_req_inter VX_csr_req +); + + wire[`NT_M1:0] is_mem_mask; + wire[`NT_M1:0] is_gpu_mask; + wire[`NT_M1:0] is_csr_mask; + + wire is_mem = (VX_bckE_req.mem_write != `NO_MEM_WRITE) || (VX_bckE_req.mem_read != `NO_MEM_READ); + wire is_gpu = (VX_bckE_req.is_wspawn || VX_bckE_req.is_tmc || VX_bckE_req.is_barrier || VX_bckE_req.is_split); + wire is_csr = VX_bckE_req.is_csr; + // wire is_gpu = 0; + + genvar currT; + for (currT = 0; currT < `NT; currT = currT + 1) begin + assign is_mem_mask[currT] = is_mem; + assign is_gpu_mask[currT] = is_gpu; + assign is_csr_mask[currT] = is_csr; + end + + // LSU Unit + assign VX_lsu_req.valid = VX_bckE_req.valid & is_mem_mask; + assign VX_lsu_req.warp_num = VX_bckE_req.warp_num; + assign VX_lsu_req.base_address = VX_gpr_data.a_reg_data; + assign VX_lsu_req.store_data = VX_gpr_data.b_reg_data; + + assign VX_lsu_req.offset = VX_bckE_req.itype_immed; + + assign VX_lsu_req.mem_read = VX_bckE_req.mem_read; + assign VX_lsu_req.mem_write = VX_bckE_req.mem_write; + assign VX_lsu_req.rd = VX_bckE_req.rd; + assign VX_lsu_req.wb = VX_bckE_req.wb; + assign VX_lsu_req.lsu_pc = VX_bckE_req.curr_PC; + + + // Execute Unit + assign VX_exec_unit_req.valid = VX_bckE_req.valid & (~is_mem_mask & ~is_gpu_mask & ~is_csr_mask); + assign VX_exec_unit_req.warp_num = VX_bckE_req.warp_num; + assign VX_exec_unit_req.curr_PC = VX_bckE_req.curr_PC; + assign VX_exec_unit_req.PC_next = VX_bckE_req.PC_next; + assign VX_exec_unit_req.rd = VX_bckE_req.rd; + assign VX_exec_unit_req.wb = VX_bckE_req.wb; + assign VX_exec_unit_req.a_reg_data = VX_gpr_data.a_reg_data; + assign VX_exec_unit_req.b_reg_data = VX_gpr_data.b_reg_data; + assign VX_exec_unit_req.alu_op = VX_bckE_req.alu_op; + assign VX_exec_unit_req.rs1 = VX_bckE_req.rs1; + assign VX_exec_unit_req.rs2 = VX_bckE_req.rs2; + assign VX_exec_unit_req.rs2_src = VX_bckE_req.rs2_src; + assign VX_exec_unit_req.itype_immed = VX_bckE_req.itype_immed; + assign VX_exec_unit_req.upper_immed = VX_bckE_req.upper_immed; + assign VX_exec_unit_req.branch_type = VX_bckE_req.branch_type; + assign VX_exec_unit_req.jalQual = VX_bckE_req.jalQual; + assign VX_exec_unit_req.jal = VX_bckE_req.jal; + assign VX_exec_unit_req.jal_offset = VX_bckE_req.jal_offset; + assign VX_exec_unit_req.ebreak = VX_bckE_req.ebreak; + + + // GPR Req + assign VX_gpu_inst_req.valid = VX_bckE_req.valid & is_gpu_mask; + assign VX_gpu_inst_req.warp_num = VX_bckE_req.warp_num; + assign VX_gpu_inst_req.is_wspawn = VX_bckE_req.is_wspawn; + assign VX_gpu_inst_req.is_tmc = VX_bckE_req.is_tmc; + assign VX_gpu_inst_req.is_split = VX_bckE_req.is_split; + assign VX_gpu_inst_req.is_barrier = VX_bckE_req.is_barrier; + assign VX_gpu_inst_req.a_reg_data = VX_gpr_data.a_reg_data; + assign VX_gpu_inst_req.rd2 = VX_gpr_data.b_reg_data[0]; + assign VX_gpu_inst_req.pc_next = VX_bckE_req.PC_next; + + + // CSR Req + assign VX_csr_req.valid = VX_bckE_req.valid & is_csr_mask; + assign VX_csr_req.warp_num = VX_bckE_req.warp_num; + assign VX_csr_req.rd = VX_bckE_req.rd; + assign VX_csr_req.wb = VX_bckE_req.wb; + assign VX_csr_req.alu_op = VX_bckE_req.alu_op; + assign VX_csr_req.is_csr = VX_bckE_req.is_csr; + assign VX_csr_req.csr_address = VX_bckE_req.csr_address; + assign VX_csr_req.csr_immed = VX_bckE_req.csr_immed; + assign VX_csr_req.csr_mask = VX_bckE_req.csr_mask; + +endmodule + + + + diff --git a/old_rtl/VX_lsu.v b/old_rtl/VX_lsu.v new file mode 100644 index 00000000..05def072 --- /dev/null +++ b/old_rtl/VX_lsu.v @@ -0,0 +1,106 @@ + +`include "VX_define.v" + + +module VX_lsu ( + input wire clk, + input wire reset, + input wire no_slot_mem, + VX_lsu_req_inter VX_lsu_req, + + // Write back to GPR + VX_inst_mem_wb_inter VX_mem_wb, + + VX_dcache_response_inter VX_dcache_rsp, + VX_dcache_request_inter VX_dcache_req, + output wire out_delay + ); + + // VX_inst_mem_wb_inter VX_mem_wb_temp(); + + assign out_delay = VX_dcache_rsp.delay || no_slot_mem; + + + // Generate Addresses + wire[`NT_M1:0][31:0] address; + VX_lsu_addr_gen VX_lsu_addr_gen + ( + .base_address(VX_lsu_req.base_address), + .offset (VX_lsu_req.offset), + .address (address) + ); + + + wire[`NT_M1:0][31:0] use_address; + wire[`NT_M1:0][31:0] use_store_data; + wire[`NT_M1:0] use_valid; + wire[2:0] use_mem_read; + wire[2:0] use_mem_write; + wire[4:0] use_rd; + wire[`NW_M1:0] use_warp_num; + wire[1:0] use_wb; + wire[31:0] use_pc; + + + + wire zero = 0; + + VX_generic_register #(.N(45 + `NW_M1 + 1 + `NT*65)) lsu_buffer( + .clk (clk), + .reset(reset), + .stall(out_delay), + .flush(zero), + .in ({address , VX_lsu_req.store_data, VX_lsu_req.valid, VX_lsu_req.mem_read, VX_lsu_req.mem_write, VX_lsu_req.rd, VX_lsu_req.warp_num, VX_lsu_req.wb, VX_lsu_req.lsu_pc}), + .out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc }) + ); + + + genvar index; + for (index = 0; index <= `NT_M1; index = index + 1) begin + assign VX_dcache_req.out_cache_driver_in_address[index] = use_address[index]; + assign VX_dcache_req.out_cache_driver_in_data[index] = use_store_data[index]; + assign VX_dcache_req.out_cache_driver_in_valid[index] = (use_valid[index]); + + assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index]; + end + + assign VX_dcache_req.out_cache_driver_in_mem_read = use_mem_read; + assign VX_dcache_req.out_cache_driver_in_mem_write = use_mem_write; + + + assign VX_mem_wb.rd = use_rd; + assign VX_mem_wb.wb = use_wb & {!VX_dcache_rsp.delay, !VX_dcache_rsp.delay}; + assign VX_mem_wb.wb_valid = use_valid; + assign VX_mem_wb.wb_warp_num = use_warp_num; + + assign VX_mem_wb.mem_wb_pc = use_pc; + + // integer curr_t; + // always @(negedge clk) begin + // for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1) + // if ((VX_dcache_req.out_cache_driver_in_valid[curr_t]) && !out_delay) begin + // if (VX_dcache_req.out_cache_driver_in_mem_read != `NO_MEM_READ) begin + // $display("Reading addr: %x val: %x", address[0], VX_mem_wb.loaded_data[0]); + // end + + // if (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) begin + // $display("Writing addr: %x val: %x", address[0], VX_dcache_req.out_cache_driver_in_data[0]); + // end + // end + // end + + // wire zero_temp = 0; + // VX_generic_register #(.N(142)) register_wb_data + // ( + // .clk (clk), + // .reset(reset), + // .stall(zero_temp), + // .flush(out_delay), + // .in ({VX_mem_wb_temp.loaded_data, VX_mem_wb_temp.rd, VX_mem_wb_temp.wb, VX_mem_wb_temp.wb_valid, VX_mem_wb_temp.wb_warp_num}), + // .out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num }) + // ); + + +endmodule // Memory + + diff --git a/old_rtl/VX_lsu_addr_gen.v b/old_rtl/VX_lsu_addr_gen.v new file mode 100644 index 00000000..85811da5 --- /dev/null +++ b/old_rtl/VX_lsu_addr_gen.v @@ -0,0 +1,17 @@ +`include "VX_define.v" + +module VX_lsu_addr_gen ( + input wire[`NT_M1:0][31:0] base_address, + input wire[31:0] offset, + output wire[`NT_M1:0][31:0] address + +); + + + genvar index; + for (index = 0; index < `NT; index = index + 1) + begin + assign address[index] = base_address[index] + offset; + end + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_priority_encoder.v b/old_rtl/VX_priority_encoder.v new file mode 100644 index 00000000..a0f7934f --- /dev/null +++ b/old_rtl/VX_priority_encoder.v @@ -0,0 +1,20 @@ +`include "VX_define.v" + +module VX_priority_encoder ( + input wire[`NW-1:0] valids, + output reg[`NW_M1:0] index, + output reg found + ); + + integer i; + always @(*) begin + index = 0; + found = 0; + for (i = `NW-1; i >= 0; i = i - 1) begin + if (valids[i]) begin + index = i[`NW_M1:0]; + found = 1; + end + end + end +endmodule \ No newline at end of file diff --git a/old_rtl/VX_priority_encoder_w_mask.v b/old_rtl/VX_priority_encoder_w_mask.v new file mode 100644 index 00000000..fcd9d865 --- /dev/null +++ b/old_rtl/VX_priority_encoder_w_mask.v @@ -0,0 +1,32 @@ +`include "../VX_define.v" +module VX_priority_encoder_w_mask + #( + parameter N = 10 + ) + ( + input wire[N-1:0] valids, + output reg [N-1:0] mask, + //output reg[$clog2(N)-1:0] index, + output reg[(`CLOG2(N))-1:0] index, + //output reg[`CLOG2(N):0] index, // eh + output reg found + ); + + integer i; + always @(valids) begin + index = 0; + found = 0; + // mask = 0; + for (i = 0; i < N; i=i+1) begin + if (valids[i]) begin + //index = i[$clog2(N)-1:0]; + index = i[(`CLOG2(N))-1:0]; + found = 1; + // mask[index] = (1 << i); + // $display("%h",(1 << i)); + end + end + end + + assign mask = found ? (1 << index) : 0; +endmodule \ No newline at end of file diff --git a/old_rtl/VX_scheduler.v b/old_rtl/VX_scheduler.v new file mode 100644 index 00000000..ce54db63 --- /dev/null +++ b/old_rtl/VX_scheduler.v @@ -0,0 +1,69 @@ + + +`include "VX_define.v" + +module VX_scheduler ( + input wire clk, + input wire reset, + input wire memory_delay, + input wire gpr_stage_delay, + VX_frE_to_bckE_req_inter VX_bckE_req, + VX_wb_inter VX_writeback_inter, + + output wire schedule_delay + +); + + + + reg[31:0] rename_table[`NW-1:0]; + + wire valid_wb = (VX_writeback_inter.wb != 0) && (|VX_writeback_inter.wb_valid) && (VX_writeback_inter.rd != 0); + wire wb_inc = (VX_bckE_req.wb != 0) && (VX_bckE_req.rd != 0); + + wire rs1_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs1]; + wire rs2_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs2]; + + wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE); + wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ); + + wire is_mem = is_store || is_load; + + + wire rs1_pass = ((valid_wb && (VX_writeback_inter.rd == VX_bckE_req.rs1))); + wire rs2_pass = ((valid_wb && (VX_writeback_inter.rd == VX_bckE_req.rs2))); + + // wire rs1_pass = 0; + // wire rs2_pass = 0; + + wire using_rs2 = (VX_bckE_req.rs2_src == `RS2_REG) || is_store || VX_bckE_req.is_barrier || VX_bckE_req.is_wspawn; + + wire rs1_rename_qual = ((rs1_rename || (rs1_pass && 0)) && (VX_bckE_req.rs1 != 0)); + wire rs2_rename_qual = ((rs2_rename || (rs2_pass && 0)) && (VX_bckE_req.rs2 != 0 && using_rs2)); + + + wire rename_valid = rs1_rename_qual || rs2_rename_qual ; + + + assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid)) || (memory_delay && (is_mem)) || (gpr_stage_delay && is_mem); + + integer i; + integer w; + always @(posedge clk or posedge reset) begin + + if (reset) begin + for (w = 0; w < `NW; w=w+1) + begin + for (i = 0; i < 32; i = i + 1) + begin + rename_table[w][i] <= 0; + end + end + end else begin + if (valid_wb ) rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] <= 0; + if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.warp_num ][VX_bckE_req.rd] <= 1; + end + end + + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_warp.v b/old_rtl/VX_warp.v new file mode 100644 index 00000000..05712c8f --- /dev/null +++ b/old_rtl/VX_warp.v @@ -0,0 +1,86 @@ +`include "VX_define.v" + + +module VX_warp ( + input wire clk, + input wire reset, + input wire stall, + input wire remove, + input wire[`NT_M1:0] in_thread_mask, + input wire in_change_mask, + input wire in_jal, + input wire[31:0] in_jal_dest, + input wire in_branch_dir, + input wire[31:0] in_branch_dest, + input wire in_wspawn, + input wire[31:0] in_wspawn_pc, + + output wire[31:0] out_PC, + output wire[`NT_M1:0] out_valid +); + + reg[31:0] real_PC; + var[31:0] temp_PC; + var[31:0] use_PC; + reg[`NT_M1:0] valid; + + reg[`NT_M1:0] valid_zero; + + integer ini_cur_th = 0; + initial begin + real_PC = 0; + for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1) begin + valid[ini_cur_th] = 0; // Thread 1 active + valid_zero[ini_cur_th] = 0; + end + valid[0] = 1; + valid_zero[0] = 0; + end + + + always @(posedge clk, posedge reset) begin + if (remove) begin + valid <= valid_zero; + end else if (in_change_mask) begin + valid <= in_thread_mask; + end + end + + + genvar out_cur_th; + generate + for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1) + assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th]; + endgenerate + + + always @(*) begin + if (in_jal == 1'b1) begin + temp_PC = in_jal_dest; + // $display("LINKING TO %h", temp_PC); + end else if (in_branch_dir == 1'b1) begin + temp_PC = in_branch_dest; + end else begin + temp_PC = real_PC; + end + end + + assign use_PC = temp_PC; + assign out_PC = temp_PC; + + always @(posedge clk or posedge reset) begin + if (reset) begin + real_PC <= 0; + end else if (in_wspawn == 1'b1) begin + // $display("Inside warp ***** Spawn @ %H",in_wspawn_pc); + real_PC <= in_wspawn_pc; + end else if (!stall) begin + real_PC <= use_PC + 32'h4; + end else begin + real_PC <= use_PC; + end + + end + + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_warp_scheduler.v b/old_rtl/VX_warp_scheduler.v new file mode 100644 index 00000000..0ee34940 --- /dev/null +++ b/old_rtl/VX_warp_scheduler.v @@ -0,0 +1,321 @@ +`include "VX_define.v" + +module VX_warp_scheduler ( + input wire clk, // Clock + input wire reset, + input wire stall, + // Wspawn + input wire wspawn, + input wire[31:0] wsapwn_pc, + input wire[`NW-1:0] wspawn_new_active, + + // CTM + input wire ctm, + input wire[`NT_M1:0] ctm_mask, + input wire[`NW_M1:0] ctm_warp_num, + + // WHALT + input wire whalt, + input wire[`NW_M1:0] whalt_warp_num, + + input wire is_barrier, + input wire[31:0] barrier_id, + input wire[$clog2(`NW):0] num_warps, + input wire[`NW_M1:0] barrier_warp_num, + + // WSTALL + input wire wstall, + input wire[`NW_M1:0] wstall_warp_num, + + // Split + input wire is_split, + input wire dont_split, + input wire[`NT_M1:0] split_new_mask, + input wire[`NT_M1:0] split_later_mask, + input wire[31:0] split_save_pc, + input wire[`NW_M1:0] split_warp_num, + + // Join + input wire is_join, + input wire[`NW_M1:0] join_warp_num, + + // JAL + input wire jal, + input wire[31:0] jal_dest, + input wire[`NW_M1:0] jal_warp_num, + + // Branch + input wire branch_valid, + input wire branch_dir, + input wire[31:0] branch_dest, + input wire[`NW_M1:0] branch_warp_num, + + output wire[`NT_M1:0] thread_mask, + output wire[`NW_M1:0] warp_num, + output wire[31:0] warp_pc, + output wire out_ebreak, + output wire scheduled_warp + +); + + wire update_use_wspawn; + + wire update_visible_active; + + wire[(1+32+`NT_M1):0] d[`NW-1:0]; + + wire join_fall; + wire[31:0] join_pc; + wire[`NT_M1:0] join_tm; + + wire in_wspawn = wspawn; + wire in_ctm = ctm; + wire in_whalt = whalt; + wire in_wstall = wstall; + + reg[`NW-1:0] warp_active; + reg[`NW-1:0] warp_stalled; + + reg[`NW-1:0] visible_active; + wire[`NW-1:0] use_active; + + wire wstall_this_cycle; + + reg[`NT_M1:0] thread_masks[`NW-1:0]; + reg[31:0] warp_pcs[`NW-1:0]; + + // barriers + reg[`NW-1:0] barrier_stall_mask[(`NUM_BARRIERS-1):0]; + wire reached_barrier_limit; + wire[`NW-1:0] curr_barrier_mask; + wire[$clog2(`NW):0] curr_barrier_count; + + // wsapwn + reg[31:0] use_wsapwn_pc; + reg[`NW-1:0] use_wsapwn; + + wire[`NW_M1:0] warp_to_schedule; + wire schedule; + + wire hazard; + wire global_stall; + + wire real_schedule; + + wire[31:0] new_pc; + + reg[`NW-1:0] total_barrier_stall; + + reg didnt_split; + + /* verilator lint_off UNUSED */ + // wire[$clog2(`NW):0] num_active; + /* verilator lint_on UNUSED */ + + integer curr_w_help; + integer curr_barrier; + always @(posedge clk or posedge reset) begin + if (reset) begin + for (curr_barrier = 0; curr_barrier < `NUM_BARRIERS; curr_barrier=curr_barrier+1) begin + barrier_stall_mask[curr_barrier] <= 0; + end + use_wsapwn_pc <= 0; + use_wsapwn <= 0; + warp_pcs[0] <= (32'h80000000 - 4); + warp_active[0] <= 1; // Activating first warp + visible_active[0] <= 1; // Activating first warp + thread_masks[0] <= 1; // Activating first thread in first warp + warp_stalled <= 0; + didnt_split <= 0; + // total_barrier_stall = 0; + for (curr_w_help = 1; curr_w_help < `NW; curr_w_help=curr_w_help+1) begin + warp_pcs[curr_w_help] <= 0; + warp_active[curr_w_help] <= 0; // Activating first warp + visible_active[curr_w_help] <= 0; // Activating first warp + thread_masks[curr_w_help] <= 1; // Activating first thread in first warp + end + + end else begin + // Wsapwning warps + if (wspawn) begin + warp_active <= wspawn_new_active; + use_wsapwn_pc <= wsapwn_pc; + use_wsapwn <= wspawn_new_active & (~`NW'b1); + end + + if (is_barrier) begin + warp_stalled[barrier_warp_num] <= 0; + if (reached_barrier_limit) begin + barrier_stall_mask[barrier_id] <= 0; + end else begin + barrier_stall_mask[barrier_id][barrier_warp_num] <= 1; + end + end else if (ctm) begin + thread_masks[ctm_warp_num] <= ctm_mask; + warp_stalled[ctm_warp_num] <= 0; + end else if (is_join && !didnt_split) begin + if (!join_fall) begin + warp_pcs[join_warp_num] <= join_pc; + end + thread_masks[join_warp_num] <= join_tm; + didnt_split <= 0; + end else if (is_split) begin + warp_stalled[split_warp_num] <= 0; + if (!dont_split) begin + thread_masks[split_warp_num] <= split_new_mask; + didnt_split <= 0; + end else begin + didnt_split <= 1; + end + end + + if (whalt) begin + warp_active[whalt_warp_num] <= 0; + visible_active[whalt_warp_num] <= 0; + end + + if (update_use_wspawn) begin + use_wsapwn[warp_to_schedule] <= 0; + thread_masks[warp_to_schedule] <= 1; + end + + + // Stalling the scheduling of warps + if (wstall) begin + warp_stalled[wstall_warp_num] <= 1; + visible_active[wstall_warp_num] <= 0; + end + + // Refilling active warps + if (update_visible_active) begin + visible_active <= warp_active & (~warp_stalled) & (~total_barrier_stall); + end + + // Don't change state if stall + if (!global_stall && real_schedule && (thread_mask != 0)) begin + visible_active[warp_to_schedule] <= 0; + warp_pcs[warp_to_schedule] <= new_pc; + end + + // Jal + if (jal) begin + warp_pcs[jal_warp_num] <= jal_dest; + warp_stalled[jal_warp_num] <= 0; + end + + // Branch + if (branch_valid) begin + if (branch_dir) warp_pcs[branch_warp_num] <= branch_dest; + warp_stalled[branch_warp_num] <= 0; + end + end + end + + VX_countones #(.N(`NW)) barrier_count( + .valids(curr_barrier_mask), + .count (curr_barrier_count) + ); + + wire[$clog2(`NW):0] count_visible_active; + VX_countones #(.N(`NW)) num_visible( + .valids(visible_active), + .count (count_visible_active) + ); + + // assign curr_barrier_count = $countones(curr_barrier_mask); + + assign curr_barrier_mask = barrier_stall_mask[barrier_id][`NW-1:0]; + assign reached_barrier_limit = curr_barrier_count == (num_warps); + + assign wstall_this_cycle = wstall && (wstall_warp_num == warp_to_schedule); // Maybe bug + + assign total_barrier_stall = barrier_stall_mask[0] | barrier_stall_mask[1] | barrier_stall_mask[2] | barrier_stall_mask[3]; + // integer curr_b; + // always @(*) begin + // total_barrier_stall = 0; + // for (curr_b = 0; curr_b < `NUM_BARRIERS; curr_b=curr_b+1) + // begin + // total_barrier_stall[`NW-1:0] = total_barrier_stall[`NW-1:0] | barrier_stall_mask[curr_b]; + // end + // end + + + assign update_visible_active = (count_visible_active < 1) && !(stall || wstall_this_cycle || hazard || is_join); + + wire[(1+32+`NT_M1):0] q1 = {1'b1, 32'b0 , thread_masks[split_warp_num]}; + wire[(1+32+`NT_M1):0] q2 = {1'b0, split_save_pc , split_later_mask}; + + + assign {join_fall, join_pc, join_tm} = d[join_warp_num]; + + + + genvar curr_warp; + for (curr_warp = 0; curr_warp < `NW; curr_warp = curr_warp + 1) begin + wire correct_warp_s = (curr_warp == split_warp_num); + wire correct_warp_j = (curr_warp == join_warp_num); + + wire push = (is_split && !dont_split) && correct_warp_s; + wire pop = is_join && correct_warp_j; + VX_generic_stack #(.WIDTH(1+32+`NT), .DEPTH($clog2(`NT)+1)) ipdom_stack( + .clk (clk), + .reset(reset), + .push (push), + .pop (pop), + .d (d[curr_warp]), + .q1 (q1), + .q2 (q2) + ); + end + + // wire should_stall = stall || (jal && (warp_to_schedule == jal_warp_num)) || (branch_dir && (warp_to_schedule == branch_warp_num)); + + wire should_jal = (jal && (warp_to_schedule == jal_warp_num)); + wire should_bra = (branch_dir && (warp_to_schedule == branch_warp_num)); + + assign hazard = (should_jal || should_bra) && schedule; + + assign real_schedule = schedule && !warp_stalled[warp_to_schedule] && !total_barrier_stall[warp_to_schedule]; + + assign global_stall = (stall || wstall_this_cycle || hazard || !real_schedule || is_join); + + assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || is_join); + + wire real_use_wspawn = use_wsapwn[warp_to_schedule]; + + assign warp_pc = real_use_wspawn ? use_wsapwn_pc : warp_pcs[warp_to_schedule]; + assign thread_mask = (global_stall) ? 0 : (real_use_wspawn ? `NT'b1 : thread_masks[warp_to_schedule]); + assign warp_num = warp_to_schedule; + + assign update_use_wspawn = use_wsapwn[warp_to_schedule] && !global_stall; + + assign new_pc = warp_pc + 4; + + + assign use_active = (count_visible_active < 1) ? (warp_active & (~warp_stalled) & (~total_barrier_stall)) : visible_active; + + // Choosing a warp to schedule + VX_priority_encoder choose_schedule( + .valids(use_active), + .index (warp_to_schedule), + .found (schedule) + ); + + // always @(*) begin + // $display("WarpPC: %h",warp_pc); + // $display("real_schedule: %d, schedule: %d, warp_stalled: %d, warp_to_schedule: %d, total_barrier_stall: %d",real_schedule, schedule, warp_stalled[warp_to_schedule], warp_to_schedule, total_barrier_stall[warp_to_schedule]); + // end + + + // Valid counter + // assign num_active = $countones(visible_active); + // VX_one_counter valid_counter( + // .valids(visible_active), + // .ones_found() + // ); + + + wire ebreak = (warp_active == 0); + assign out_ebreak = ebreak; + +endmodule \ No newline at end of file diff --git a/old_rtl/VX_writeback.v b/old_rtl/VX_writeback.v new file mode 100644 index 00000000..2f684bae --- /dev/null +++ b/old_rtl/VX_writeback.v @@ -0,0 +1,111 @@ + +`include "VX_define.v" + + +module VX_writeback ( + input wire clk, + input wire reset, + // Mem WB info + VX_inst_mem_wb_inter VX_mem_wb, + // EXEC Unit WB info + VX_inst_exec_wb_inter VX_inst_exec_wb, + // CSR Unit WB info + VX_csr_wb_inter VX_csr_wb, + + // Actual WB to GPR + VX_wb_inter VX_writeback_inter, + output wire no_slot_mem, + output wire no_slot_csr + ); + + + VX_wb_inter VX_writeback_tempp(); + + wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid); + wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid); + wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid); + + + assign no_slot_mem = mem_wb && (exec_wb || csr_wb); + assign no_slot_csr = csr_wb && (exec_wb); + + assign VX_writeback_tempp.write_data = exec_wb ? VX_inst_exec_wb.alu_result : + csr_wb ? VX_csr_wb.csr_result : + mem_wb ? VX_mem_wb.loaded_data : + 0; + + + assign VX_writeback_tempp.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid : + csr_wb ? VX_csr_wb.valid : + mem_wb ? VX_mem_wb.wb_valid : + 0; + + assign VX_writeback_tempp.rd = exec_wb ? VX_inst_exec_wb.rd : + csr_wb ? VX_csr_wb.rd : + mem_wb ? VX_mem_wb.rd : + 0; + + assign VX_writeback_tempp.wb = exec_wb ? VX_inst_exec_wb.wb : + csr_wb ? VX_csr_wb.wb : + mem_wb ? VX_mem_wb.wb : + 0; + + assign VX_writeback_tempp.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num : + csr_wb ? VX_csr_wb.warp_num : + mem_wb ? VX_mem_wb.wb_warp_num : + 0; + + + + assign VX_writeback_tempp.wb_pc = exec_wb ? VX_inst_exec_wb.exec_wb_pc : + csr_wb ? 32'hdeadbeef : + mem_wb ? VX_mem_wb.mem_wb_pc : + 32'hdeadbeef; + + + wire zero = 0; + + wire[`NT-1:0][31:0] use_wb_data; + + reg prev_is_mem; + + always @(posedge clk, posedge reset) begin + if (reset) + begin + prev_is_mem = 0; + end begin + prev_is_mem = mem_wb && !no_slot_mem; + end + end + + VX_generic_register #(.N(39 + `NW_M1 + 1 + `NT*33)) wb_register( + .clk (clk), + .reset(reset), + .stall(zero), + .flush(zero), + .in ({VX_writeback_tempp.write_data, VX_writeback_tempp.wb_valid, VX_writeback_tempp.rd, VX_writeback_tempp.wb, VX_writeback_tempp.wb_warp_num, VX_writeback_tempp.wb_pc}), + .out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc}) + ); + + reg[31:0] last_data_wb; + always @(posedge clk) begin + if ((|VX_writeback_inter.wb_valid) && (VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd == 28)) begin + last_data_wb <= use_wb_data[0]; + end + end + + `ifdef SYN + assign VX_writeback_inter.write_data = prev_is_mem ? VX_writeback_tempp.write_data : use_wb_data; + `else + assign VX_writeback_inter.write_data = use_wb_data; + `endif + + +endmodule // VX_writeback + + + + + + + diff --git a/old_rtl/Vortex.v b/old_rtl/Vortex.v new file mode 100644 index 00000000..f4b13e7d --- /dev/null +++ b/old_rtl/Vortex.v @@ -0,0 +1,249 @@ + +`include "../VX_define.v" + + +module Vortex + /*#( + parameter CACHE_SIZE = 4096, // Bytes + parameter CACHE_WAYS = 2, + parameter CACHE_BLOCK = 128, // Bytes + parameter CACHE_BANKS = 8, + parameter NUM_WORDS_PER_BLOCK = 4 + )*/ + ( + input wire clk, + input wire reset, + input wire[31:0] icache_response_instruction, + output wire[31:0] icache_request_pc_address, + // IO + output wire io_valid, + output wire[31:0] io_data, + + // Req D Mem + output reg [31:0] o_m_read_addr_d, + output reg [31:0] o_m_evict_addr_d, + output reg o_m_valid_d, + output reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0], + output reg o_m_read_or_write_d, + + // Rsp D Mem + input wire [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0], + input wire i_m_ready_d, + + // Req I Mem + output reg [31:0] o_m_read_addr_i, + output reg [31:0] o_m_evict_addr_i, + output reg o_m_valid_i, + output reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], + output reg o_m_read_or_write_i, + + // Rsp I Mem + input wire [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], + input wire i_m_ready_i, + output wire out_ebreak + ); + + +reg[31:0] icache_banks = `ICACHE_BANKS; +reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK; + + +reg[31:0] dcache_banks = `DCACHE_BANKS; +reg[31:0] dcache_num_words_per_block = `DCACHE_NUM_WORDS_PER_BLOCK; + +reg[31:0] number_threads = `NT; +reg[31:0] number_warps = `NW; + +always @(posedge clk) begin + icache_banks <= icache_banks; + icache_num_words_per_block <= icache_num_words_per_block; + + dcache_banks <= dcache_banks; + dcache_num_words_per_block <= dcache_num_words_per_block; + + number_threads <= number_threads; + number_warps <= number_warps; +end + +wire memory_delay; +wire gpr_stage_delay; +wire schedule_delay; + + +// Dcache Interface +VX_dcache_response_inter VX_dcache_rsp(); +VX_dcache_request_inter VX_dcache_req(); + +wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.out_cache_driver_in_valid) && (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.out_cache_driver_in_address[0] == 32'h00010000); +wire[31:0] temp_io_data = VX_dcache_req.out_cache_driver_in_data[0]; +assign io_valid = temp_io_valid; +assign io_data = temp_io_data; + + +VX_dram_req_rsp_inter #( + .NUMBER_BANKS(`DCACHE_BANKS), + .NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)) VX_dram_req_rsp(); + + VX_icache_response_inter icache_response_fe(); + VX_icache_request_inter icache_request_fe(); + VX_dram_req_rsp_inter #( + .NUMBER_BANKS(`ICACHE_BANKS), + .NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK)) VX_dram_req_rsp_icache(); + + //assign icache_response_fe.instruction = icache_response_instruction; + assign icache_request_pc_address = icache_request_fe.pc_address; + + // Need to fix this so that it is only 1 set of outputs + // o_m Values + + // L2 Cache + /* + assign VX_L2cache_req.out_cache_driver_in_valid = VX_dram_req_rsp.o_m_valid || VX_dram_req_rsp_icache.o_m_valid; // Ask about this (width) + // Ask about the adress + assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? icache_request_fe.pc_address: VX_dcache_req.out_cache_driver_in_address; + //assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_read_addr: VX_dram_req_rsp.o_m_read_addr; + //assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_evict_addr : VX_dram_req_rsp.o_m_evict_addr; + assign VX_L2cache_req.out_cache_driver_in_mem_read = (VX_dram_req_rsp_icache.o_m_valid) ? (VX_dram_req_rsp_icache.o_m_read_or_write ? icache_request_fe.out_cache_driver_in_mem_write : icache_request_fe.out_cache_driver_in_mem_read) + : (VX_dram_req_rsp.o_m_read_or_write ? VX_dcache_req.out_cache_driver_in_mem_write : VX_dcache_req.out_cache_driver_in_mem_read); + //assign VX_dram_req_rsp.i_m_ready = i_m_ready && !VX_dram_req_rsp_icache.o_m_valid && VX_dram_req_rsp.o_m_valid; + //assign VX_dram_req_rsp_icache.i_m_ready = i_m_ready && VX_dram_req_rsp_icache.o_m_valid; + genvar cur_bank; + genvar cur_word; + for (cur_bank = 0; cur_bank < CACHE_BANKS; cur_bank = cur_bank + 1) begin + for (cur_word = 0; cur_word < NUM_WORDS_PER_BLOCK; cur_word = cur_word + 1) begin + assign VX_L2cache_req.out_cache_driver_in_data[cur_bank][cur_word] = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_writedata[cur_bank][cur_word] + : VX_dram_req_rsp.o_m_writedata[cur_bank][cur_word]; + assign VX_dram_req_rsp.i_m_readdata[cur_bank][cur_word] = VX_dram_req_rsp_L2.i_m_readdata[cur_bank][cur_word]; // fill in correct response data + assign VX_dram_req_rsp_icache.i_m_readdata[cur_bank][cur_word] = VX_dram_req_rsp_L2.i_m_readdata[cur_bank][cur_word]; // fill in correct response data + end + end + */ + + + assign o_m_valid_i = VX_dram_req_rsp_icache.o_m_valid; + assign o_m_valid_d = VX_dram_req_rsp.o_m_valid; + assign o_m_read_addr_i = VX_dram_req_rsp_icache.o_m_read_addr; + assign o_m_read_addr_d = VX_dram_req_rsp.o_m_read_addr; + assign o_m_evict_addr_i = VX_dram_req_rsp_icache.o_m_evict_addr; + assign o_m_evict_addr_d = VX_dram_req_rsp.o_m_evict_addr; + assign o_m_read_or_write_i = VX_dram_req_rsp_icache.o_m_read_or_write; + assign o_m_read_or_write_d = VX_dram_req_rsp.o_m_read_or_write; + assign VX_dram_req_rsp.i_m_ready = i_m_ready_d; + assign VX_dram_req_rsp_icache.i_m_ready = i_m_ready_i; + genvar curr_bank; + genvar curr_word; + /* + for (curr_bank = 0; curr_bank < CACHE_BANKS; curr_bank = curr_bank + 1) begin + for (curr_word = 0; curr_word < NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin + assign o_m_writedata_i[curr_bank][curr_word] = VX_dram_req_rsp_icache.o_m_writedata[curr_bank][curr_word]; + assign o_m_writedata_d[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word]; + assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata_d[curr_bank][curr_word]; // fixed + assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed + end + end + */ + +for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin + for (curr_word = 0; curr_word < `DCACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin + + assign o_m_writedata_d[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word]; + assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata_d[curr_bank][curr_word]; // fixed + + end +end + + +for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin + for (curr_word = 0; curr_word < `ICACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin + assign o_m_writedata_i[curr_bank][curr_word] = VX_dram_req_rsp_icache.o_m_writedata[curr_bank][curr_word]; + assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed + end +end + + +///////////////////////////////////////////////////////////////////////// + + + +// Front-end to Back-end +VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM + +// Back-end to Front-end +VX_wb_inter VX_writeback_inter(); // Writeback to GPRs +VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch +VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch + +// CSR Buses +// VX_csr_write_request_inter VX_csr_w_req(); + + +VX_warp_ctl_inter VX_warp_ctl(); + + +VX_front_end vx_front_end( + .clk (clk), + .reset (reset), + .VX_warp_ctl (VX_warp_ctl), + .VX_bckE_req (VX_bckE_req), + .schedule_delay (schedule_delay), + .icache_response_fe (icache_response_fe), + .icache_request_fe (icache_request_fe), + .VX_jal_rsp (VX_jal_rsp), + .VX_branch_rsp (VX_branch_rsp), + .fetch_ebreak (out_ebreak) + ); + +VX_scheduler schedule( + .clk (clk), + .reset (reset), + .memory_delay (memory_delay), + .gpr_stage_delay (gpr_stage_delay), + .VX_bckE_req (VX_bckE_req), + .VX_writeback_inter(VX_writeback_inter), + .schedule_delay (schedule_delay) + ); + +VX_back_end vx_back_end( + .clk (clk), + .reset (reset), + .schedule_delay (schedule_delay), + .VX_warp_ctl (VX_warp_ctl), + .VX_bckE_req (VX_bckE_req), + .VX_jal_rsp (VX_jal_rsp), + .VX_branch_rsp (VX_branch_rsp), + .VX_dcache_rsp (VX_dcache_rsp), + .VX_dcache_req (VX_dcache_req), + .VX_writeback_inter (VX_writeback_inter), + .out_mem_delay (memory_delay), + .gpr_stage_delay (gpr_stage_delay) + ); + + +VX_dmem_controller VX_dmem_controller( + .clk (clk), + .reset (reset), + .VX_dram_req_rsp (VX_dram_req_rsp), + .VX_dram_req_rsp_icache (VX_dram_req_rsp_icache), + .VX_icache_req (icache_request_fe), + .VX_icache_rsp (icache_response_fe), + .VX_dcache_req (VX_dcache_req), + .VX_dcache_rsp (VX_dcache_rsp) + ); +// VX_csr_handler vx_csr_handler( +// .clk (clk), +// .in_decode_csr_address(decode_csr_address), +// .VX_csr_w_req (VX_csr_w_req), +// .in_wb_valid (VX_writeback_inter.wb_valid[0]), + +// .out_decode_csr_data (csr_decode_csr_data) +// ); + + + + +endmodule // Vortex + + + + + diff --git a/old_rtl/byte_enabled_simple_dual_port_ram.v b/old_rtl/byte_enabled_simple_dual_port_ram.v new file mode 100644 index 00000000..7a1173d5 --- /dev/null +++ b/old_rtl/byte_enabled_simple_dual_port_ram.v @@ -0,0 +1,53 @@ + +`include "VX_define.v" + + +module byte_enabled_simple_dual_port_ram +( + input we, clk, + input wire reset, + input wire[4:0] waddr, raddr1, raddr2, + input wire[`NT_M1:0] be, + input wire[`NT_M1:0][31:0] wdata, + output reg[`NT_M1:0][31:0] q1, q2 +); + + // integer regi; + // integer threadi; + + // Thread Byte Bit + logic [`NT_M1:0][3:0][7:0] GPR[31:0]; + + // initial begin + // for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0; + // end + + integer ini; + always@(posedge clk, posedge reset) begin + if (reset) begin + for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0; + end else if(we) begin + integer thread_ind; + for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin + if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0]; + if(be[thread_ind]) GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8]; + if(be[thread_ind]) GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16]; + if(be[thread_ind]) GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24]; + end + end + // $display("^^^^^^^^^^^^^^^^^^^^^^^"); + // for (regi = 0; regi <= 31; regi = regi + 1) begin + // for (threadi = 0; threadi <= `NT_M1; threadi = threadi + 1) begin + // if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]); + // end + // end + + end + + assign q1 = GPR[raddr1]; + assign q2 = GPR[raddr2]; + + // assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1]; + // assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2]; + +endmodule diff --git a/old_rtl/cache/Makefile b/old_rtl/cache/Makefile new file mode 100644 index 00000000..3e92307a --- /dev/null +++ b/old_rtl/cache/Makefile @@ -0,0 +1,12 @@ +all: RUNFILE + + +VERILATOR: + verilator --compiler gcc --Wno-UNOPTFLAT -Wall --trace -cc VX_d_cache_encapsulate.v -Irtl --exe d_cache_test_bench.cpp -CFLAGS -std=c++11 + +RUNFILE: VERILATOR + (cd obj_dir && make -j -f VVX_d_cache_encapsulate.mk) + +clean: + rm ./obj_dir/* + diff --git a/old_rtl/cache/Notes b/old_rtl/cache/Notes new file mode 100644 index 00000000..0458c659 --- /dev/null +++ b/old_rtl/cache/Notes @@ -0,0 +1,46 @@ +Notes + + +8 kB L1 Data Cache | 16 kB L1 I cache (maybe) +[tag index offset_remaining_block bank wordOffset], use a blocksize of 128 bytes between memory and cache. So each bank gets 16 bytes. + total offset is b its + 4 bits new offset, 2 bits block, 2 bits word offset + xxxxxxxIIIIIIIIoobbbyy + 9876543210 + bbbyyyyy + o = index into block offset + b = bank + y = word offset + I = index into cach + 6 bits indexes (64 indeces) No ways || 16 indexes with 4 ways + Rest of the bits are tag bits + +blocks / banks = 16 bytes, 8 banks. 128 bytes. 256 indexes (height). width is 16 bytes. 4 words per block (per bank). 17 bit tag + +gtkwave ___.vcd + + +// Splitting it up + +// word byte +wire[127:0][3:0] data_from_ram; + + +// word byte bank +wire[15:0][3:0] bank_data_n[3:0] + +integer i; +for (i = 0; i < something; i+=8) +{ + bank_data_n[0][i/8] = data_from_ram[i+0] + bank_data_n[1][i/8] = data_from_ram[i+1] + bank_data_n[2][i/8] = data_from_ram[i+2] + bank_data_n[3][i/8] = data_from_ram[i+3] + bank_data_n[4][i/8] = data_from_ram[i+4] + bank_data_n[5][i/8] = data_from_ram[i+5] + bank_data_n[6][i/8] = data_from_ram[i+6] + bank_data_n[7][i/8] = data_from_ram[i+7] +} + + +With Cache. If miss. Go to memory, grab all data, replace that data in the cache. Generate a new request, feed that into the cache (this one will hit), return that diff --git a/old_rtl/cache/VX_Cache_Bank.v b/old_rtl/cache/VX_Cache_Bank.v new file mode 100644 index 00000000..e3251e72 --- /dev/null +++ b/old_rtl/cache/VX_Cache_Bank.v @@ -0,0 +1,253 @@ +// To Do: Change way_id_out to an internal register which holds when in between access and finished. +// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default +// Also make sure all possible output states are transmitted back to the bank correctly + +`include "../VX_define.v" +// `include "VX_cache_data.v" + + +module VX_Cache_Bank + #( + parameter CACHE_SIZE = 4096, // Bytes + parameter CACHE_WAYS = 1, + parameter CACHE_BLOCK = 128, // Bytes + parameter CACHE_BANKS = 8, + parameter LOG_NUM_BANKS = 3, + parameter NUM_REQ = 8, + parameter LOG_NUM_REQ = 3, + parameter NUM_IND = 8, + parameter CACHE_WAY_INDEX = 1, + parameter NUM_WORDS_PER_BLOCK = 4, + parameter OFFSET_SIZE_START = 0, + parameter OFFSET_SIZE_END = 1, + parameter TAG_SIZE_START = 0, + parameter TAG_SIZE_END = 16, + parameter IND_SIZE_START = 0, + parameter IND_SIZE_END = 7, + parameter ADDR_TAG_START = 15, + parameter ADDR_TAG_END = 31, + parameter ADDR_OFFSET_START = 5, + parameter ADDR_OFFSET_END = 6, + parameter ADDR_IND_START = 7, + parameter ADDR_IND_END = 14 + ) + ( + clk, + rst, + state, + read_or_write, // Read = 0 | Write = 1 + i_p_mem_read, + i_p_mem_write, + valid_in, + //write_from_mem, + actual_index, + o_tag, + block_offset, + writedata, + fetched_writedata, + + byte_select, + + readdata, + hit, + //miss, + + eviction_wb, // Need to evict + eviction_addr, // What's the eviction tag + + data_evicted, + evicted_way + ); + + // localparam NUMBER_BANKS = `CACHE_BANKS; + // localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS); + // localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4); + // localparam NUMBER_INDEXES = `NUM_IND; + + localparam CACHE_IDLE = 0; // Idle + localparam SEND_MEM_REQ = 1; // Write back this block into memory + localparam RECIV_MEM_RSP = 2; + + + localparam BLOCK_NUM_BITS = `CLOG2(CACHE_BLOCK); + // Inputs + input wire rst; + input wire clk; + input wire [3:0] state; +//input wire write_from_mem; + + // Reading Data + input wire[IND_SIZE_END:IND_SIZE_START] actual_index; + + + input wire[TAG_SIZE_END:TAG_SIZE_START] o_tag; // When write_from_mem = 1, o_tag is the new tag + input wire[OFFSET_SIZE_END:OFFSET_SIZE_START] block_offset; + + + input wire[31:0] writedata; + input wire valid_in; + input wire read_or_write; // Specifies if it is a read or write operation + + input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata; + input wire[2:0] i_p_mem_read; + input wire[2:0] i_p_mem_write; + input wire[1:0] byte_select; + + + input wire[CACHE_WAY_INDEX-1:0] evicted_way; + + // Outputs + // Normal shit + output wire[31:0] readdata; + output wire hit; + //output wire miss; + + // Eviction Data (Notice) + output wire eviction_wb; // Need to evict + output wire[31:0] eviction_addr; // What's the eviction tag + + // Eviction Data (Extraction) + output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted; + + + + wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use; + wire[TAG_SIZE_END:TAG_SIZE_START] tag_use; + wire[TAG_SIZE_END:TAG_SIZE_START] eviction_tag; + wire valid_use; + wire dirty_use; + wire access; + wire write_from_mem; + wire miss; // -10/21 + + + + wire[CACHE_WAY_INDEX-1:0] way_to_update; + + assign miss = (tag_use != o_tag) && valid_use && valid_in; + + + assign data_evicted = data_use; + + // assign eviction_wb = miss && (dirty_use != 1'b0) && valid_use; + assign eviction_wb = (dirty_use != 1'b0); + assign eviction_tag = tag_use; + assign access = (state == CACHE_IDLE) && valid_in; + assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in; // TODO + assign hit = (access && (tag_use == o_tag) && valid_use); + //assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data + assign eviction_addr = {eviction_tag, actual_index, {(BLOCK_NUM_BITS){1'b0}}}; // Fix with actual data + + + + wire lw = (i_p_mem_read == `LW_MEM_READ); + wire lb = (i_p_mem_read == `LB_MEM_READ); + wire lh = (i_p_mem_read == `LH_MEM_READ); + wire lhu = (i_p_mem_read == `LHU_MEM_READ); + wire lbu = (i_p_mem_read == `LBU_MEM_READ); + + wire sw = (i_p_mem_write == `SW_MEM_WRITE); + wire sb = (i_p_mem_write == `SB_MEM_WRITE); + wire sh = (i_p_mem_write == `SH_MEM_WRITE); + + wire b0 = (byte_select == 0); + wire b1 = (byte_select == 1); + wire b2 = (byte_select == 2); + wire b3 = (byte_select == 3); + + wire[31:0] data_unQual = (b0 || lw) ? (data_use[block_offset] ) : + b1 ? (data_use[block_offset] >> 8) : + b2 ? (data_use[block_offset] >> 16) : + (data_use[block_offset] >> 24); + + + wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF); + wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF); + wire[31:0] lbu_data = (data_unQual & 32'hFF); + wire[31:0] lhu_data = (data_unQual & 32'hFFFF); + wire[31:0] lw_data = (data_unQual); + + + wire[31:0] sw_data = writedata; + + wire[31:0] sb_data = b1 ? {{16{1'b0}}, writedata[7:0], { 8{1'b0}}} : + b2 ? {{ 8{1'b0}}, writedata[7:0], {16{1'b0}}} : + b3 ? {{ 0{1'b0}}, writedata[7:0], {24{1'b0}}} : + writedata; + + wire[31:0] sh_data = b2 ? {writedata[15:0], {16{1'b0}}} : writedata; + + + + wire[31:0] use_write_data = sb ? sb_data : + sh ? sh_data : + sw_data; + + + wire[31:0] data_Qual = lb ? lb_data : + lh ? lh_data : + lhu ? lhu_data : + lbu ? lbu_data : + lw_data; + + + assign readdata = (access) ? data_Qual : 32'b0; // Fix with actual data + + + wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); + wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); + + + wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we; + wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write; + genvar g; + for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin + wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss); + + assign we[g] = (write_from_mem) ? 4'b1111 : + (normal_write && sw) ? 4'b1111 : + (normal_write && sb) ? sb_mask : + (normal_write && sh) ? sh_mask : + 4'b0000; + + + // assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0; + assign data_write[g] = write_from_mem ? fetched_writedata[g] : use_write_data; + assign way_to_update = evicted_way; + end + + + VX_cache_data_per_index #( + .CACHE_WAYS (CACHE_WAYS), + .NUM_IND (NUM_IND), + .CACHE_WAY_INDEX (CACHE_WAY_INDEX), + .NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK), + .TAG_SIZE_START (TAG_SIZE_START), + .TAG_SIZE_END (TAG_SIZE_END), + .IND_SIZE_START (IND_SIZE_START), + .IND_SIZE_END (IND_SIZE_END)) data_structures( + .clk (clk), + .rst (rst), + .valid_in (valid_in), + .state (state), + // Inputs + .addr (actual_index), + .we (we), + .evict (write_from_mem), + .data_write (data_write), + .tag_write (o_tag), + .way_to_update(way_to_update), + // Outputs + .tag_use (tag_use), + .data_use (data_use), + .valid_use (valid_use), + .dirty_use (dirty_use) + ); + + + +endmodule + + + + diff --git a/old_rtl/cache/VX_cache_bank_valid.v b/old_rtl/cache/VX_cache_bank_valid.v new file mode 100644 index 00000000..48759b77 --- /dev/null +++ b/old_rtl/cache/VX_cache_bank_valid.v @@ -0,0 +1,30 @@ +`include "../VX_define.v" + +module VX_cache_bank_valid +#( + parameter NUMBER_BANKS = 8, + parameter LOG_NUM_BANKS = 3, + parameter NUM_REQ = 1 +) +( + input wire [NUM_REQ-1:0] i_p_valid, + input wire [NUM_REQ-1:0][31:0] i_p_addr, + output reg [NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks +); + + generate + integer t_id; + always @(*) begin + thread_track_banks = 0; + for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1) + begin + if (NUMBER_BANKS != 1) begin + thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id]; + end else begin + thread_track_banks[0][t_id] = i_p_valid[t_id]; + end + end + end + endgenerate + +endmodule diff --git a/old_rtl/cache/VX_cache_data.v b/old_rtl/cache/VX_cache_data.v new file mode 100644 index 00000000..6b6c91b1 --- /dev/null +++ b/old_rtl/cache/VX_cache_data.v @@ -0,0 +1,233 @@ + + +`include "../VX_define.v" + +module VX_cache_data + #( + parameter NUM_IND = 8, + parameter NUM_WORDS_PER_BLOCK = 4, + parameter TAG_SIZE_START = 0, + parameter TAG_SIZE_END = 16, + parameter IND_SIZE_START = 0, + parameter IND_SIZE_END = 7 + ) + ( + input wire clk, rst, // Clock + + // `ifdef PARAM + // Addr + input wire[IND_SIZE_END:IND_SIZE_START] addr, + // WE + input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + input wire evict, + // Data + input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, + input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write, + + + output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use, + output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, + output wire valid_use, + output wire dirty_use + // `else + // // Addr + // input wire[7:0] addr, + // // WE + // input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + // input wire evict, + // // Data + // input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data + // input wire[16:0] tag_write, + + + // output wire[16:0] tag_use, + // output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, + // output wire valid_use, + // output wire dirty_use + // `endif + +); + + //localparam NUMBER_BANKS = CACHE_BANKS; + //localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS); + // localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4); + //localparam NUMBER_INDEXES = NUM_IND; + + wire currently_writing = (|we); + wire update_dirty = ((!dirty_use) && currently_writing) || (evict); + + wire dirt_new = evict ? 0 : (|we); + + + `ifndef SYN + + // (3:0) 4 bytes + reg[NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUM_IND-1:0]; // Actual Data + reg[TAG_SIZE_END:TAG_SIZE_START] tag[NUM_IND-1:0]; + reg valid[NUM_IND-1:0]; + reg dirty[NUM_IND-1:0]; + + + // 16 bytes + assign data_use = data[addr]; // Read Port + assign tag_use = tag[addr]; + assign valid_use = valid[addr]; + assign dirty_use = dirty[addr]; + + integer f; + integer ini_ind; + always @(posedge clk, posedge rst) begin : update_all + if (rst) begin + for (ini_ind = 0; ini_ind < NUM_IND; ini_ind=ini_ind+1) begin + data[ini_ind] <= 0; + tag[ini_ind] <= 0; + valid[ini_ind] <= 0; + dirty[ini_ind] <= 0; + end + end else begin + if (update_dirty) dirty[addr] <= dirt_new; // WRite Port + if (evict) tag[addr] <= tag_write; + if (evict) valid[addr] <= 1; + + for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin + if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ]; + if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ]; + if (we[f][2]) data[addr][f][2] <= data_write[f][23:16]; + if (we[f][3]) data[addr][f][3] <= data_write[f][31:24]; + end + end + end + + `else + + wire[IND_SIZE_END:IND_SIZE_START] use_addr = addr; + + wire cena = 1; + + wire cenb_d = (|we); + wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write; + wire[NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d; + wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d; + genvar cur_b; + for (cur_b = 0; cur_b < NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin + assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}}; + end + assign data_use = data_out_d; + + + // Using ASIC MEM + /* verilator lint_off PINCONNECTEMPTY */ + rf2_32x128_wm1 data ( + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(data_out_d), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena), + .AA(use_addr), + .CLKB(clk), + .CENB(cenb_d), + .WENB(write_bit_mask_d), + .AB(use_addr), + .DB(wdata_d), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(5'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + /* verilator lint_on PINCONNECTEMPTY */ + + + + + + wire[16:0] old_tag; + wire old_valid; + wire old_dirty; + + wire[16:0] new_tag = evict ? tag_write : old_tag; + wire new_valid = evict ? 1 : old_valid; + wire new_dirty = update_dirty ? dirt_new : old_dirty; + + + wire cenb_m = (evict || update_dirty); + wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1; + + + + // Try to fix the error in memory conneciton, modified by Lingjun Zhu on Oct. 28 2019 + // wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid}; + // wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m; + + wire[19-1:0] wdata_m = {new_tag, new_dirty, new_valid}; + + wire[19-1:0] data_out_m; + + assign {old_tag, old_dirty, old_valid} = data_out_m; + + + assign dirty_use = old_dirty; + assign valid_use = old_valid; + assign tag_use = old_tag; + + /* verilator lint_off PINCONNECTEMPTY */ + rf2_32x19_wm0 meta ( + .CENYA(), + .AYA(), + .CENYB(), + // .WENYB(), + .AYB(), + .QA(data_out_m), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena), + .AA(use_addr), + .CLKB(clk), + .CENB(cenb_m), + // .WENB(write_bit_mask_m), + .AB(use_addr), + .DB(wdata_m), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(5'b0), + .TENB(1'b1), + .TCENB(1'b0), + // .TWENB(128'b0), + .TAB(5'b0), + .TDB(19'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + /* verilator lint_on PINCONNECTEMPTY */ + + + `endif + +endmodule diff --git a/old_rtl/cache/VX_cache_data_per_index.v b/old_rtl/cache/VX_cache_data_per_index.v new file mode 100644 index 00000000..4e95a42d --- /dev/null +++ b/old_rtl/cache/VX_cache_data_per_index.v @@ -0,0 +1,163 @@ + + +`include "../VX_define.v" + +module VX_cache_data_per_index + #( + parameter CACHE_WAYS = 1, + parameter NUM_IND = 8, + parameter CACHE_WAY_INDEX = 1, + parameter NUM_WORDS_PER_BLOCK = 4, + parameter TAG_SIZE_START = 0, + parameter TAG_SIZE_END = 16, + parameter IND_SIZE_START = 0, + parameter IND_SIZE_END = 7 + ) + ( + input wire clk, // Clock + input wire rst, + input wire valid_in, + input wire [3:0] state, + // Addr + input wire[IND_SIZE_END:IND_SIZE_START] addr, + // WE + input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + input wire evict, + input wire[CACHE_WAY_INDEX-1:0] way_to_update, + // Data + input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data + input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write, + + + output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use, + output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, + output wire valid_use, + output wire dirty_use + +); + //localparam NUMBER_BANKS = CACHE_BANKS; + //localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS); + // localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4); + //localparam NUMBER_INDEXES = `DCACHE_NUM_IND; + + wire [CACHE_WAYS-1:0][TAG_SIZE_END:TAG_SIZE_START] tag_use_per_way; + wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way; + wire [CACHE_WAYS-1:0] valid_use_per_way; + wire [CACHE_WAYS-1:0] dirty_use_per_way; + wire [CACHE_WAYS-1:0] hit_per_way; + // reg [CACHE_WAY_INDEX-1:0] eviction_way_index; + wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way; + wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way; + wire [CACHE_WAYS-1:0] write_from_mem_per_way; + wire invalid_found; + + wire [CACHE_WAY_INDEX-1:0] way_index; + wire [CACHE_WAY_INDEX-1:0] invalid_index; + + + localparam CACHE_IDLE = 0; // Idle + localparam SEND_MEM_REQ = 1; // Write back this block into memory + localparam RECIV_MEM_RSP = 2; + + if(CACHE_WAYS != 1) begin + VX_generic_priority_encoder #(.N(CACHE_WAYS)) valid_index + ( + .valids(~valid_use_per_way), + .index (invalid_index), + .found (invalid_found) + ); + + VX_generic_priority_encoder #(.N(CACHE_WAYS)) way_indexing + ( + .valids(hit_per_way), + .index (way_index), + .found () + ); + end + else begin + assign way_index = 0; + assign invalid_found = (valid_use_per_way == 1'b0) ? 1 : 0; + assign invalid_index = 0; + end + + + + + // wire hit = |hit_per_way; + // wire miss = ~hit; + // wire update = |we && !miss; + // wire valid = &valid_use_per_way; + + wire[CACHE_WAY_INDEX-1:0] way_use_Qual; + + assign way_use_Qual = (state != CACHE_IDLE) ? way_to_update : way_index; + + assign tag_use = tag_use_per_way[way_use_Qual]; + assign data_use = data_use_per_way[way_use_Qual]; + assign valid_use = valid_use_per_way[way_use_Qual]; + assign dirty_use = dirty_use_per_way[way_use_Qual]; + + // assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index] : (invalid_found ? tag_use_per_way[invalid_index] : 0)); + // assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index] : (invalid_found ? data_use_per_way[invalid_index] : 0)); + // assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index] : (invalid_found ? valid_use_per_way[invalid_index] : 0)); + // assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index] : (invalid_found ? dirty_use_per_way[invalid_index] : 0)); + + + + genvar ways; + for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin : each_way + + + assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0; + + + assign write_from_mem_per_way[ways] = evict && (ways == way_use_Qual); + assign we_per_way[ways] = (ways == way_use_Qual) ? (we) : 0; + assign data_write_per_way[ways] = data_write; + + + // assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0; + + // assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_use_Qual) ? (we) : 0) : 0; + // assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_use_Qual) ? data_write : 0) : 0; + // assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_use_Qual) ? 1 : 0) : 0; + + VX_cache_data #( + .NUM_IND (NUM_IND), + .NUM_WORDS_PER_BLOCK (NUM_WORDS_PER_BLOCK), + .TAG_SIZE_START (TAG_SIZE_START), + .TAG_SIZE_END (TAG_SIZE_END), + .IND_SIZE_START (IND_SIZE_START), + .IND_SIZE_END (IND_SIZE_END)) data_structures( + .clk (clk), + .rst (rst), + // Inputs + .addr (addr), + .we (we_per_way[ways]), + .evict (write_from_mem_per_way[ways]), + .data_write(data_write_per_way[ways]), + .tag_write (tag_write), + // Outputs + .tag_use (tag_use_per_way[ways]), + .data_use (data_use_per_way[ways]), + .valid_use (valid_use_per_way[ways]), + .dirty_use (dirty_use_per_way[ways]) + ); + end + + // always @(posedge clk or posedge rst) begin + // if (rst) begin + // eviction_way_index <= 0; + // end else begin + // // if((miss && dirty_use && valid_use && !evict && valid_in)) begin // can be either evict or invalid cache entries + // if((state == SEND_MEM_REQ)) begin // can be either evict or invalid cache entries + // if((eviction_way_index+1) == CACHE_WAYS) begin + // eviction_way_index <= 0; + // end else begin + // eviction_way_index <= (eviction_way_index + 1); + // end + // end + // end + // end + +endmodule diff --git a/old_rtl/cache/VX_d_cache.v b/old_rtl/cache/VX_d_cache.v new file mode 100644 index 00000000..78b407f7 --- /dev/null +++ b/old_rtl/cache/VX_d_cache.v @@ -0,0 +1,387 @@ +// Cache Memory (8way 4word) // +// i_ means input port // +// o_ means output port // +// _p_ means data exchange with processor // +// _m_ means data exchange with memory // + + +// TO DO: +// - Send in a response from memory of what the data is from the test bench + +`include "../VX_define.v" +//`include "VX_priority_encoder.v" +// `include "VX_Cache_Bank.v" +//`include "cache_set.v" + +module VX_d_cache + #( + parameter CACHE_SIZE = 4096, // Bytes + parameter CACHE_WAYS = 1, + parameter CACHE_BLOCK = 128, // Bytes + parameter CACHE_BANKS = 8, + parameter LOG_NUM_BANKS = 3, + parameter NUM_REQ = 8, + parameter LOG_NUM_REQ = 3, + parameter NUM_IND = 8, + parameter CACHE_WAY_INDEX = 1, + parameter NUM_WORDS_PER_BLOCK = 4, + parameter OFFSET_SIZE_START = 0, + parameter OFFSET_SIZE_END = 1, + parameter TAG_SIZE_START = 0, + parameter TAG_SIZE_END = 16, + parameter IND_SIZE_START = 0, + parameter IND_SIZE_END = 7, + parameter ADDR_TAG_START = 15, + parameter ADDR_TAG_END = 31, + parameter ADDR_OFFSET_START = 5, + parameter ADDR_OFFSET_END = 6, + parameter ADDR_IND_START = 7, + parameter ADDR_IND_END = 14, + parameter MEM_ADDR_REQ_MASK = 32'hffffffc0 + ) + ( + clk, + rst, + i_p_addr, + //i_p_byte_en, + i_p_writedata, + i_p_read_or_write, // 0 = Read | 1 = Write + i_p_mem_read, + i_p_mem_write, + i_p_valid, + //i_p_write, + o_p_readdata, + o_p_delay, // 0 = all threads done | 1 = Still threads that need to + + o_m_evict_addr, + o_m_read_addr, + + o_m_writedata, + + o_m_read_or_write, // 0 = Read | 1 = Write + o_m_valid, + i_m_readdata, + + i_m_ready + ); + + //parameter NUMBER_BANKS = `CACHE_BANKS; + //localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4); + + //localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS); + + localparam CACHE_IDLE = 0; // Idle + localparam SEND_MEM_REQ = 1; // Write back this block into memory + localparam RECIV_MEM_RSP = 2; + + + //parameter cache_entry = 9; + input wire clk, rst; + input wire [NUM_REQ-1:0] i_p_valid; + input wire [NUM_REQ-1:0][31:0] i_p_addr; // FIXME + input wire [NUM_REQ-1:0][31:0] i_p_writedata; + input wire i_p_read_or_write; //, i_p_write; + output reg [NUM_REQ-1:0][31:0] o_p_readdata; + output wire o_p_delay; + output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy + output reg [31:0] o_m_read_addr; + output reg o_m_valid; + output reg[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; + output reg o_m_read_or_write; //, o_m_write; + input wire[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; + input wire i_m_ready; + + input wire[2:0] i_p_mem_read; + input wire[2:0] i_p_mem_write; + + + // Buffer for final data + reg [NUM_REQ-1:0][31:0] final_data_read; + reg [NUM_REQ-1:0][31:0] new_final_data_read; + wire[NUM_REQ-1:0][31:0] new_final_data_read_Qual; + + assign o_p_readdata = new_final_data_read_Qual; + + + reg[CACHE_WAY_INDEX-1:0] global_way_to_evict; + + + wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank + wire[CACHE_BANKS - 1 : 0][LOG_NUM_REQ-1:0] index_per_bank; // Index of thread each bank will try to service + wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank + wire[CACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank + wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank + + wire[CACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank + wire[CACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss + wire[CACHE_BANKS-1:0] eviction_wb; + reg[CACHE_BANKS-1:0] eviction_wb_old; + + + // wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_new; + // reg [CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_old; + // wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] way_used; + + // Internal State + reg [3:0] state; + wire[3:0] new_state; + + wire[NUM_REQ-1:0] use_valid; // Valid used throught the code + reg[NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss) + wire[NUM_REQ-1:0] new_stored_valid; // New stored valid + + + + reg[CACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank; + + reg[31:0] miss_addr; + // reg[31:0] evict_addr; + + wire curr_processor_request_valid = (|i_p_valid); + + + assign use_valid = (stored_valid == 0) ? i_p_valid : stored_valid; + + + + + + + VX_cache_bank_valid #(.NUMBER_BANKS (CACHE_BANKS), + .LOG_NUM_BANKS (LOG_NUM_BANKS), + .NUM_REQ (NUM_REQ)) multip_banks( + .i_p_valid (use_valid), + .i_p_addr (i_p_addr), + .thread_track_banks(thread_track_banks) + ); + + + reg[NUM_REQ-1:0] threads_serviced_Qual; + + reg[NUM_REQ-1:0] debug_hit_per_bank_mask[CACHE_BANKS-1:0]; + + genvar bid; + for (bid = 0; bid < CACHE_BANKS; bid=bid+1) + begin + wire[NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid]; + wire[LOG_NUM_REQ-1:0] use_thread_index = index_per_bank[bid]; + wire use_write_final_data = hit_per_bank[bid]; + wire[31:0] use_data_final_data = readdata_per_bank[bid]; + VX_priority_encoder_w_mask #(.N(NUM_REQ)) choose_thread( + .valids(use_threads_track_banks), + .mask (use_mask_per_bank[bid]), + .index (index_per_bank[bid]), + .found (valid_per_bank[bid]) + ); + + assign debug_hit_per_bank_mask[bid] = {NUM_REQ{hit_per_bank[bid]}}; + assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid]; + end + + integer test_bid; + always @(*) begin + new_final_data_read = 0; + for (test_bid=0; test_bid < CACHE_BANKS; test_bid=test_bid+1) + begin + if (hit_per_bank[test_bid]) begin + new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid]; + end + end + end + + + wire[CACHE_BANKS - 1 : 0] detect_bank_miss; + //assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | + // threads_serviced_per_bank[2] | threads_serviced_per_bank[3] | + // threads_serviced_per_bank[4] | threads_serviced_per_bank[5] | + // threads_serviced_per_bank[6] | threads_serviced_per_bank[7]; + integer bbid; + always @(*) begin + threads_serviced_Qual = 0; + for (bbid = 0; bbid < CACHE_BANKS; bbid=bbid+1) + begin + threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid]; + end + end + + + + genvar tid; + for (tid = 0; tid < NUM_REQ; tid =tid+1) + begin + assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid]; + end + + + assign detect_bank_miss = (valid_per_bank & ~hit_per_bank); + + wire delay; + assign delay = (new_stored_valid != 0) || (state != CACHE_IDLE); // add other states + + assign o_p_delay = delay; + + wire[CACHE_BANKS - 1 : 0][LOG_NUM_REQ-1:0] send_index_to_bank = index_per_bank; + + + wire[LOG_NUM_BANKS-1:0] miss_bank_index; + wire miss_found; + VX_generic_priority_encoder #(.N(CACHE_BANKS)) get_miss_index + ( + .valids(detect_bank_miss), + .index (miss_bank_index), + .found (miss_found) + ); + + + + assign new_state = ((state == CACHE_IDLE) && (|detect_bank_miss)) ? SEND_MEM_REQ : + (state == SEND_MEM_REQ) ? RECIV_MEM_RSP : + ((state == RECIV_MEM_RSP) && !i_m_ready) ? RECIV_MEM_RSP : + CACHE_IDLE; + + // Handle if there is more than one miss + assign new_stored_valid = use_valid & (~threads_serviced_Qual); + + + wire update_global_way_to_evict = ((state == RECIV_MEM_RSP) && (new_state == CACHE_IDLE)) && (CACHE_WAYS > 1); + +/////////////////////////////////////////////////////////////////////// + genvar cur_t; + integer init_b; + always @(posedge clk, posedge rst) begin + if (rst) begin + final_data_read <= 0; + // new_final_data_read = 0; + state <= 0; + stored_valid <= 0; + // eviction_addr_per_bank <= 0; + miss_addr <= 0; + // evict_addr <= 0; + // threads_serviced_Qual = 0; + // for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1) + // begin + // debug_hit_per_bank_mask[init_b] <= 0; + // end + // evicted_way_old <= 0; + // eviction_wb_old <= 0; + global_way_to_evict <= 0; + + end else begin + + global_way_to_evict <= (update_global_way_to_evict) ? (global_way_to_evict+1) : global_way_to_evict; + + state <= new_state; + + stored_valid <= new_stored_valid; + + if (state == CACHE_IDLE) begin + if (miss_found) begin + miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]]; + // evict_addr <= eviction_addr_per_bank[miss_bank_index]; + end else begin + miss_addr <= 0; + // evict_addr <= 0; + end + end + + final_data_read <= new_final_data_read_Qual; + // evicted_way_old <= evicted_way_new; + // eviction_wb_old <= eviction_wb; + end + end + + + genvar bank_id; + generate + for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1) + begin + wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? miss_addr : + (state == RECIV_MEM_RSP) ? miss_addr : + i_p_addr[send_index_to_bank[bank_id]]; + + // assign evicted_way_new[bank_id] = (state == SEND_MEM_REQ) ? way_used[bank_id] : + // (state == RECIV_MEM_RSP) ? evicted_way_old[bank_id] : + // 0; + + wire[1:0] byte_select = bank_addr[1:0]; + wire[TAG_SIZE_END:TAG_SIZE_START] cache_tag = bank_addr[ADDR_TAG_END:ADDR_TAG_START]; + + `ifdef SYN_FUNC + wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = 0; + wire[IND_SIZE_END:IND_SIZE_START] cache_index = 0; + `else + wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = bank_addr[ADDR_OFFSET_END:ADDR_OFFSET_START]; + wire[IND_SIZE_END:IND_SIZE_START] cache_index = bank_addr[ADDR_IND_END:ADDR_IND_START]; + `endif + + + wire normal_valid_in = valid_per_bank[bank_id]; + wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 : + ((state == RECIV_MEM_RSP) && !i_m_ready) ? 1'b0 : + ((state == SEND_MEM_REQ)) ? 1'b0 : + normal_valid_in; + + + VX_Cache_Bank #( + .CACHE_SIZE (CACHE_SIZE), + .CACHE_WAYS (CACHE_WAYS), + .CACHE_BLOCK (CACHE_BLOCK), + .CACHE_BANKS (CACHE_BANKS), + .LOG_NUM_BANKS (LOG_NUM_BANKS), + .NUM_REQ (NUM_REQ), + .LOG_NUM_REQ (LOG_NUM_REQ), + .NUM_IND (NUM_IND), + .CACHE_WAY_INDEX (CACHE_WAY_INDEX), + .NUM_WORDS_PER_BLOCK (NUM_WORDS_PER_BLOCK), + .OFFSET_SIZE_START (OFFSET_SIZE_START), + .OFFSET_SIZE_END (OFFSET_SIZE_END), + .TAG_SIZE_START (TAG_SIZE_START), + .TAG_SIZE_END (TAG_SIZE_END), + .IND_SIZE_START (IND_SIZE_START), + .IND_SIZE_END (IND_SIZE_END), + .ADDR_TAG_START (ADDR_TAG_START), + .ADDR_TAG_END (ADDR_TAG_END), + .ADDR_OFFSET_START (ADDR_OFFSET_START), + .ADDR_OFFSET_END (ADDR_OFFSET_END), + .ADDR_IND_START (ADDR_IND_START), + .ADDR_IND_END (ADDR_IND_END) + ) bank_structure ( + .clk (clk), + .rst (rst), + .state (state), + .valid_in (use_valid_in), + .actual_index (cache_index), + .o_tag (cache_tag), + .block_offset (cache_offset), + .writedata (i_p_writedata[send_index_to_bank[bank_id]]), + .read_or_write (i_p_read_or_write), + .i_p_mem_read (i_p_mem_read), + .i_p_mem_write (i_p_mem_write), + .byte_select (byte_select), + .hit (hit_per_bank[bank_id]), + .readdata (readdata_per_bank[bank_id]), // Data read + .eviction_addr (eviction_addr_per_bank[bank_id]), + .data_evicted (o_m_writedata[bank_id]), + .eviction_wb (eviction_wb[bank_id]), // Something needs to be written back + .fetched_writedata(i_m_readdata[bank_id]), // Data From memory + .evicted_way (global_way_to_evict) + ); + + end + endgenerate + + // Mem Rsp + + // Req to mem: + assign o_m_evict_addr = (eviction_addr_per_bank[0]) & MEM_ADDR_REQ_MASK; // Could be anything because tag+index are same + assign o_m_read_addr = miss_addr & MEM_ADDR_REQ_MASK; + assign o_m_valid = (state == SEND_MEM_REQ); + assign o_m_read_or_write = (state == SEND_MEM_REQ) && (|eviction_wb); + //end + +endmodule + + + + + diff --git a/old_rtl/cache/VX_d_cache_encapsulate.v b/old_rtl/cache/VX_d_cache_encapsulate.v new file mode 100644 index 00000000..a35c322a --- /dev/null +++ b/old_rtl/cache/VX_d_cache_encapsulate.v @@ -0,0 +1,118 @@ + +`include "../VX_define.v" + +// `define NUM_WORDS_PER_BLOCK 4 + +module VX_d_cache_encapsulate ( + clk, + rst, + + i_p_initial_request, + i_p_addr, + i_p_writedata, + i_p_read_or_write, + i_p_valid, + + o_p_readdata, + o_p_readdata_valid, + o_p_waitrequest, + + o_m_addr, + o_m_writedata, + o_m_read_or_write, + o_m_valid, + + i_m_readdata, + i_m_ready +); + + parameter NUMBER_BANKS = 8; + + + + + //parameter cache_entry = 9; + input wire clk, rst; + + input wire i_p_valid[`NT_M1:0]; + input wire [31:0] i_p_addr[`NT_M1:0]; + input wire i_p_initial_request; + input wire [31:0] i_p_writedata[`NT_M1:0]; + input wire i_p_read_or_write; + + input wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0]; + input wire i_m_ready; + + output reg [31:0] o_p_readdata[`NT_M1:0]; + output reg o_p_readdata_valid[`NT_M1:0] ; + output reg o_p_waitrequest; + + output reg [31:0] o_m_addr; + output reg o_m_valid; + output reg [31:0] o_m_writedata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0]; + output reg o_m_read_or_write; + + + // Inter + wire [`NT_M1:0] i_p_valid_inter; + wire [`NT_M1:0][31:0] i_p_addr_inter; + wire [`NT_M1:0][31:0] i_p_writedata_inter; + + reg [`NT_M1:0][31:0] o_p_readdata_inter; + reg [`NT_M1:0] o_p_readdata_valid_inter; + + reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter; + wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter; + + + genvar curr_thraed; + for (curr_thraed = 0; curr_thraed < `NT; curr_thraed = curr_thraed + 1) begin + assign i_p_valid_inter[curr_thraed] = i_p_valid[curr_thraed]; + assign i_p_addr_inter[curr_thraed] = i_p_addr[curr_thraed]; + assign i_p_writedata_inter[curr_thraed] = i_p_writedata[curr_thraed]; + assign o_p_readdata[curr_thraed] = o_p_readdata_inter[curr_thraed]; + assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed]; + end + + + genvar curr_bank; + genvar curr_word; + for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin + + for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin + + assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word]; + assign i_m_readdata_inter[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word]; + + end + end + +VX_d_cache dcache( + .clk (clk), + .rst (rst), + .i_p_valid (i_p_valid_inter), + .i_p_addr (i_p_addr_inter), + .i_p_initial_request(i_p_initial_request), + .i_p_writedata (i_p_writedata_inter), + .i_p_read_or_write (i_p_read_or_write), + .o_p_readdata (o_p_readdata_inter), + .o_p_readdata_valid (o_p_readdata_valid_inter), + .o_p_waitrequest (o_p_waitrequest), + .o_m_addr (o_m_addr), + .o_m_valid (o_m_valid), + .o_m_writedata (o_m_writedata_inter), + .o_m_read_or_write (o_m_read_or_write), + .i_m_readdata (i_m_readdata_inter), + .i_m_ready (i_m_ready) + ); + + +endmodule + + + + + + + + diff --git a/old_rtl/cache/VX_d_cache_tb.v b/old_rtl/cache/VX_d_cache_tb.v new file mode 100644 index 00000000..4f5681c3 --- /dev/null +++ b/old_rtl/cache/VX_d_cache_tb.v @@ -0,0 +1,58 @@ +`include "VX_define.v" +`include "VX_d_cache.v" + +module VX_d_cache_tb; + + parameter NUMBER_BANKS = 8; + + reg clk, reset, im_ready; + reg [`NT_M1:0] i_p_valid; + reg [`NT_M1:0][13:0] i_p_addr; // FIXME + reg i_p_initial_request; + reg [`NT_M1:0][31:0] i_p_writedata; + reg i_p_read_or_write; //, i_p_write; + reg [`NT_M1:0][31:0] o_p_readdata; + reg [`NT_M1:0] o_p_readdata_valid; + reg o_p_waitrequest; + reg [13:0] o_m_addr; // Only one address is sent out at a time to memory + reg o_m_valid; + reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata; + reg o_m_read_or_write; //, o_m_write; + reg [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller + + + VX_d_cache d_cache(.clk(clk), + .rst(reset), + .i_p_initial_request(i_p_initial_request), + .i_p_addr(i_p_addr), + .i_p_writedata(i_p_writedata), + .i_p_read_or_write(i_p_read_or_write), // 0 = Read | 1 = Write + .i_p_valid(i_p_valid), + .o_p_readdata(o_p_readdata), + .o_p_readdata_valid(o_p_readdata_valid), + .o_p_waitrequest(o_p_waitrequest), // 0 = all threads done | 1 = Still threads that need to + .o_m_addr(o_m_addr), + .o_m_writedata(o_m_writedata), + .o_m_read_or_write(o_m_read_or_write), // 0 = Read | 1 = Write + .o_m_valid(o_m_valid), + .i_m_readdata(i_m_readdata), + .i_m_ready(im_ready) + //cnt_r, + //cnt_w, + //cnt_hit_r, + //cnt_hit_w + ); + + + + initial + begin + clk = 0; + reset = 0; + + end + + always + #5 clk = ! clk; + +endmodule \ No newline at end of file diff --git a/old_rtl/cache/VX_generic_pe.v b/old_rtl/cache/VX_generic_pe.v new file mode 100644 index 00000000..4ff3cc17 --- /dev/null +++ b/old_rtl/cache/VX_generic_pe.v @@ -0,0 +1,24 @@ +module VX_generic_pe + #( + parameter N = 8 + ) + ( + input wire[N-1:0] valids, + output reg[$clog2(N)-1:0] index, + output reg found + ); + +parameter my_secret = 0; + + integer i; + always @(*) begin + index = 0; + found = 0; + for (i = N-1; i >= 0; i = i - 1) begin + if (valids[i]) begin + index = i[$clog2(N)-1:0]; + found = 1; + end + end + end +endmodule \ No newline at end of file diff --git a/old_rtl/cache/cache_set.v b/old_rtl/cache/cache_set.v new file mode 100644 index 00000000..4f2445ea --- /dev/null +++ b/old_rtl/cache/cache_set.v @@ -0,0 +1,233 @@ +// To Do: Change way_id_out to an internal register which holds when in between access and finished. +// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default +// Also make sure all possible output states are transmitted back to the bank correctly + +// `include "VX_define.v" +module cache_set(clk, + rst, + // These next 4 are possible modes that the Set could be in, I am making them 4 different variables for indexing purposes + access, // First + find_evict, + write_from_mem, + idle, + // entry, + o_tag, + writedata, + //byte_en, + write, + //word_en, + //way_id_in, + //way_id_out, + readdata, + //wb_addr, + hit, + eviction_wb, + eviction_tag, + //eviction_data, + //modify, + miss + //valid_data + //read_miss + ); + + parameter cache_entry = 14; + parameter ways_per_set = 4; + + input wire clk, rst; + input wire access; + input wire find_evict; + input wire write_from_mem; + input wire idle; + //input wire [cache_entry-1:0] entry; + input wire [1:0] o_tag; + input wire [31:0] writedata; + //input wire [3:0] byte_en; + input wire write; // 0 == False + //input wire [3:0] word_en; + //input wire read_miss; + //input wire [1:0] way_id_in; + //output reg [1:0] way_id_out; + output reg [31:0] readdata; + //output reg [3:0] hit; + output reg hit; + output reg miss; + output wire eviction_wb; + output wire [1:0] eviction_tag; + reg [31:0] eviction_data; + //output wire [22:0] wb_addr; + //output wire modify, valid_data; + + + + //wire [2:0] i_tag; + //wire dirty; + //wire [24-cache_entry:0] write_tag_data; + + // Table for one set + reg [2:0] counter; // Determines which to evict + reg valid [ways_per_set-1:0]; + reg [1:0] tag [ways_per_set-1:0]; + reg clean [ways_per_set-1:0]; + reg [31:0] data [ways_per_set-1:0]; + + + assign eviction_wb = miss && clean[counter[1:0]] != 1'b1 && valid[counter[1:0]] == 1'b1; + assign eviction_tag = tag[counter[1:0]]; + //assign eviction_data = data[counter[1:0]]; + //assign hit = valid_data && (o_tag == i_tag); + //assign modify = valid_data && (o_tag != i_tag) && dirty; + //assign miss = !valid_data || ((o_tag != i_tag) && !dirty); + + //assign wb_addr = {i_tag, entry}; + always @(posedge clk) begin + if (rst) begin + + end + if (find_evict) begin + if (tag[0] == o_tag && valid[0]) begin + readdata <= data[0]; + end else if (tag[1] == o_tag && valid[1]) begin + readdata <= data[1]; + end else if (tag[2] == o_tag && valid[2]) begin + readdata <= data[2]; + end else if (tag[3] == o_tag && valid[3]) begin + readdata <= data[3]; + end + end else if (access) begin + //tag[`NT_M1:0] <= i_p_addr[`NT_M1:0][13:12]; + counter <= ((counter + 1) ^ 3'b100); // Counter determining which to evict in the event of miss only increment when miss !!! NEED TO FIX LOGIC + // Hit in First Column + if (tag[0] == o_tag && valid[0]) begin + if (write == 1'b0) begin // if it is a read + if (clean[0] == 1'b1 ) begin + //hit <= 4'b0001; + hit <= 1'b1; + readdata <= data[0]; + miss <= 1'b0; + end else begin + //hit <= 4'b0000; // SHOULD PROBABLY TRACK WHERE THIS MISS IS IN A DIFFERENT VARIABLE + hit <= 1'b0; + readdata <= 32'b0; + miss <= 1'b1; + end + end else if (write == 1'b1) begin + data[0] <= writedata; + clean[0] <= 1'b0; + //hit <= 4'b0001; + hit <= 1'b1; + end + end + // Hit in Second Column + else if (tag[1] == o_tag && valid[1]) begin + if (write == 1'b0) begin // if it is a read + if (clean[1] == 1'b1 ) begin + //hit <= 4'b0010; + hit <= 1'b1; + readdata <= data[1]; + miss <= 1'b0; + end else begin + //hit <= 4'b0000; + hit <= 1'b0; + readdata <= 32'b0; + miss <= 1'b1; + end + end else if (write == 1'b1) begin + data[1] <= writedata; + clean[1] <= 1'b0; + //hit <= 4'b0010; + hit <= 1'b1; + end + end + // Hit in Third Column + else if (tag[2] == o_tag && valid[2]) begin + if (write == 1'b0) begin // if it is a read + if (clean[2] == 1'b1 ) begin + //hit <= 4'b0100; + hit <= 1'b1; + readdata <= data[2]; + miss <= 1'b0; + end else begin + //hit <= 4'b0000; + hit <= 1'b0; + readdata <= 32'b0; + miss <= 1'b1; + end + end else if (write == 1'b1) begin + data[2] <= writedata; + clean[2] <= 1'b0; + //hit <= 4'b0100; + hit <= 1'b1; + end + end + // Hit in Fourth Column + else if (tag[3] == o_tag && valid[3]) begin + if (write == 1'b0) begin // if it is a read + if (clean[3] == 1'b1 ) begin + //hit <= 4'b1000; + hit <= 1'b1; + readdata <= data[3]; + miss <= 1'b0; + end else begin + //hit <= 4'b0000; + hit <= 1'b0; + readdata <= 32'b0; + miss <= 1'b1; + end + end else if (write == 1'b1) begin + data[3] <= writedata; + clean[3] <= 1'b0; + //hit <= 4'b1000; + hit <= 1'b1; + end + end + // Miss + else begin + //way_id_out <= counter; + miss <= 1'b1; + if (write == 1'b0) begin // Read Miss + clean[counter[1:0]] <= 1'b1; + data[counter[1:0]] <= 32'h7FF; // FIX WITH ACTUAL MEMORY ACCESS + end else if (write == 1'b1) begin // Write Miss + clean[counter[1:0]] <= 1'b1; + data[counter[1:0]] <= writedata; + end + end + + end + if (write_from_mem) begin + tag[counter[1:0]] <= o_tag; + valid[counter[1:0]] <= 1'b1; + hit <= 1'b1; + if (write == 1'b0) begin // Read Miss + clean[counter[1:0]] <= 1'b1; + data[counter[1:0]] <= 32'h7FF; // FIX WITH ACTUAL MEMORY ACCESS + end else if (write == 1'b1) begin // Write Miss + clean[counter[1:0]] <= 1'b0; + data[counter[1:0]] <= writedata; + end + end + if (idle) begin // Set "way" register equal to invalid value + hit <= 1'b1; // set to know it is ready + miss <= 1'b0; + readdata <= 32'hFFFFFFFF; + end + if (find_evict) begin // Keep "way" value the same !!!! Fix. Need to send back data with matching tag. Also need to ensure evicted data doesnt get lost + if (tag[3] == o_tag && valid[3]) begin + readdata <= data[3]; + end else if (tag[1] == o_tag && valid[1]) begin + readdata <= data[1]; + end else if (tag[2] == o_tag && valid[2]) begin + readdata <= data[2]; + end else if (tag[0] == o_tag && valid[0]) begin + readdata <= data[0]; + end else begin + readdata <= eviction_data; + end + hit <= 1'b1; + miss <= 1'b0; + end + counter <= ((counter + 1) ^ 3'b100); // Counter determining which to evict in the event of miss only increment when miss !!! NEED TO FIX LOGIC + eviction_data <= data[counter[1:0]]; + end + +endmodule \ No newline at end of file diff --git a/old_rtl/cache/d_cache_test_bench.cpp b/old_rtl/cache/d_cache_test_bench.cpp new file mode 100644 index 00000000..e7fb3214 --- /dev/null +++ b/old_rtl/cache/d_cache_test_bench.cpp @@ -0,0 +1,29 @@ + + +#include "d_cache_test_bench.h" + +//#define NUM_TESTS 46 + +int main(int argc, char **argv) +{ + + Verilated::commandArgs(argc, argv); + + Verilated::traceEverOn(true); + + + VX_d_cache v; + + + bool curr = v.simulate(); + //if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; + //if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; + if ( curr) std::cerr << GREEN << "Test Passed: " << std::endl; + if (!curr) std::cerr << RED << "Test Failed: " << std::endl; + + return 0; + +} + + + diff --git a/old_rtl/cache/d_cache_test_bench.h b/old_rtl/cache/d_cache_test_bench.h new file mode 100644 index 00000000..112aeb9a --- /dev/null +++ b/old_rtl/cache/d_cache_test_bench.h @@ -0,0 +1,355 @@ +// C++ libraries +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "VX_define.h" +#include "VVX_d_cache_encapsulate.h" +#include "verilated.h" + +#include "d_cache_test_bench_debug.h" + + +#ifdef VCD_OUTPUT +#include +#endif + +// void set_Index (auto & var, int index, int size, auto val) +// { +// int real_shift +// } + +class VX_d_cache +{ + public: + VX_d_cache(); + ~VX_d_cache(); + bool simulate(); + bool operation(int, bool); + + VVX_d_cache_encapsulate * vx_d_cache_; + long int curr_cycle; + int stats_total_cycles = 0; + int stats_dram_accesses = 0; + #ifdef VCD_OUTPUT + VerilatedVcdC *m_trace; + #endif +}; + + + +VX_d_cache::VX_d_cache() : curr_cycle(0), stats_total_cycles(0), stats_dram_accesses(0) +{ + + this->vx_d_cache_ = new VVX_d_cache_encapsulate; + #ifdef VCD_OUTPUT + this->m_trace = new VerilatedVcdC; + this->vx_d_cache_->trace(m_trace, 99); + this->m_trace->open("trace.vcd"); + #endif + //this->results.open("../results.txt"); +} + +VX_d_cache::~VX_d_cache() +{ + + + delete this->vx_d_cache_; + #ifdef VCD_OUTPUT + m_trace->close(); + #endif +} + +bool VX_d_cache::operation(int counter_value, bool do_op) { + if (do_op) { + vx_d_cache_->i_p_initial_request = 1; + } else { + vx_d_cache_->i_p_initial_request = 0; + } + + if (counter_value == 0 && do_op) { // Write to bank 1-4 at index 64 + vx_d_cache_->i_p_initial_request = 1; + vx_d_cache_->i_p_read_or_write = 1; + vx_d_cache_->i_m_ready = 0; + for (int j = 0; j < NT; j++) { + vx_d_cache_->i_p_valid[j] = 1; + vx_d_cache_->i_p_writedata[j] = 0x7f6f8f6f; + vx_d_cache_->i_m_readdata[j][0] = 1; + if (j == 0) { + vx_d_cache_->i_p_addr[0] = 0x30001004; // bank 1 + } else if (j == 1) { + vx_d_cache_->i_p_addr[1] = 0x30001008; // bank 2 + } else if (j == 2) { + vx_d_cache_->i_p_addr[2] = 0x3000100c; // bank 3 + } else { + vx_d_cache_->i_p_addr[3] = 0x30010010; // bank 4 -- This is serviced 1st, then the other 3 banks are at once + } + } + + } else if (counter_value == 1 && do_op) { // Write to bank 4-7 at index 108 + vx_d_cache_->i_p_initial_request = 1; + vx_d_cache_->i_p_read_or_write = 1; + vx_d_cache_->i_m_ready = 0; + for (int j = 0; j < NT; j++) { + vx_d_cache_->i_p_valid[j] = 1; + vx_d_cache_->i_p_writedata[j] = 0xd1d2d2d3; + vx_d_cache_->i_m_readdata[j][0] = 1; + if (j == 0) { + vx_d_cache_->i_p_addr[0] = 0x30001c14; // bank 5 + } else if (j == 1) { + vx_d_cache_->i_p_addr[1] = 0x30001c18; // bank 6 + } else if (j == 2) { + vx_d_cache_->i_p_addr[2] = 0x30001c1c; // bank 7 + } else { + vx_d_cache_->i_p_addr[3] = 0x30001c10; // bank 4 + } + } + + } else if (counter_value == 2 && do_op) { // Read from bank 1-4 at those indexes + for (int j = 0; j < NT; j++) { + vx_d_cache_->i_p_initial_request = 1; + vx_d_cache_->i_p_read_or_write = 0; + vx_d_cache_->i_m_ready = 0; + for (int j = 0; j < NT; j++) { + vx_d_cache_->i_p_valid[j] = 1; + vx_d_cache_->i_p_writedata[j] = 0x23232332; + vx_d_cache_->i_m_readdata[j][0] = 1; + if (j == 0) { + vx_d_cache_->i_p_addr[0] = 0x30001004; // bank 1 + } else if (j == 1) { + vx_d_cache_->i_p_addr[1] = 0x30001c18; // bank 5 + } else if (j == 2) { + vx_d_cache_->i_p_addr[2] = 0x3000100c; // bank 3 + } else { + vx_d_cache_->i_p_addr[3] = 0x30001c1c;; // bank 7 + } + } + } + } else if (counter_value == 3 && do_op) { // Write to Bank 1-5 (evictions will need to take place) + vx_d_cache_->i_p_initial_request = 1; + vx_d_cache_->i_p_read_or_write = 1; + vx_d_cache_->i_m_ready = 0; + for (int j = 0; j < NT; j++) { + vx_d_cache_->i_p_valid[j] = 1; + vx_d_cache_->i_m_readdata[j][0] = 1; + if (j == 0) { + vx_d_cache_->i_p_addr[0] = 0x20001004; // bank 1 + vx_d_cache_->i_p_writedata[j] = 0xaaaabbb0; + } else if (j == 1) { + vx_d_cache_->i_p_addr[1] = 0x20001008; // bank 2 + vx_d_cache_->i_p_writedata[j] = 0xaaaabbb1; + } else if (j == 2) { + vx_d_cache_->i_p_addr[2] = 0x2000100c; // bank 3 + vx_d_cache_->i_p_writedata[j] = 0xaaaabbb2; + } else { + vx_d_cache_->i_p_addr[3] = 0x20001c14; // bank 5 + vx_d_cache_->i_p_writedata[j] = 0xaaaabbb3; + } + } + } else if (counter_value == 4 && do_op) { // Read from addresses that were just overwritten above ^^^ + vx_d_cache_->i_p_initial_request = 1; + vx_d_cache_->i_p_read_or_write = 0; + vx_d_cache_->i_m_ready = 0; + for (int j = 0; j < NT; j++) { + vx_d_cache_->i_p_valid[j] = 1; + vx_d_cache_->i_p_writedata[j] = 0x23232332; + vx_d_cache_->i_m_readdata[j][0] = 1; + if (j == 0) { + vx_d_cache_->i_p_addr[0] = 0x20001004; // bank 1 + } else if (j == 1) { + vx_d_cache_->i_p_addr[1] = 0x20001008; // bank 2 + } else if (j == 2) { + vx_d_cache_->i_p_addr[2] = 0x2000100c; // bank 3 + } else { + vx_d_cache_->i_p_addr[3] = 0x20001c14; // bank 5 + } + } + } + /* These will check writing multiple threads writing to the same block + } else if (counter_value == 3 && do_op) { // Write to Bank 0 + vx_d_cache_->i_p_initial_request = 1; + vx_d_cache_->i_p_read_or_write = 1; + vx_d_cache_->i_m_ready = 0; + for (int j = 0; j < NT; j++) { + vx_d_cache_->i_p_valid[j] = 1; + vx_d_cache_->i_m_readdata[j][0] = 1; + if (j == 0) { + vx_d_cache_->i_p_addr[0] = 0x30001f00; // bank 0 + vx_d_cache_->i_p_writedata[j] = 0xaaaabbb0; + } else if (j == 1) { + vx_d_cache_->i_p_addr[1] = 0x30001c00; // bank 0 + vx_d_cache_->i_p_writedata[j] = 0xaaaabbb1; + } else if (j == 2) { + vx_d_cache_->i_p_addr[2] = 0x30001a00; // bank 0 + vx_d_cache_->i_p_writedata[j] = 0xaaaabbb2; + } else { + vx_d_cache_->i_p_addr[3] = 0x30001904; // bank 1 + vx_d_cache_->i_p_writedata[j] = 0xaaaabbb3; + } + } + } else if (counter_value == 4 && do_op) { // Read from Bank 0 + vx_d_cache_->i_p_initial_request = 1; + vx_d_cache_->i_p_read_or_write = 0; + vx_d_cache_->i_m_ready = 0; + for (int j = 0; j < NT; j++) { + vx_d_cache_->i_p_valid[j] = 1; + vx_d_cache_->i_p_writedata[j] = 0x23232332; + vx_d_cache_->i_m_readdata[j][0] = 1; + if (j == 0) { + vx_d_cache_->i_p_addr[0] = 0x30001f00; // bank 0 + } else if (j == 1) { + vx_d_cache_->i_p_addr[1] = 0x30001c00; // bank 0 + } else if (j == 2) { + vx_d_cache_->i_p_addr[2] = 0x30001a00; // bank 0 + } else { + vx_d_cache_->i_p_addr[3] = 0x30001904; // bank 1 + } + } + } + */ + // Handle Memory Accesses + unsigned int read_data_from_mem = 0x1111 + counter_value + this->stats_total_cycles; + + if (vx_d_cache_->o_m_valid) { + this->stats_dram_accesses = this->stats_dram_accesses + 1; // (assuming memory access takes 20 cycles) + + this->stats_total_cycles += 1; + vx_d_cache_->clk = 0; + vx_d_cache_->eval(); + #ifdef VCD_OUTPUT + m_trace->dump(2*this->stats_total_cycles); + #endif + vx_d_cache_->clk = 1; + vx_d_cache_->eval(); + #ifdef VCD_OUTPUT + m_trace->dump((2*this->stats_total_cycles)+1); + #endif + + vx_d_cache_->i_m_ready = 1; + for (int j1 = 0; j1 < 8; j1++) { + for (int j2 = 0; j2 < 4; j2++) { + vx_d_cache_->i_m_readdata[j1][j2] = read_data_from_mem; + } + } + } else { + vx_d_cache_->i_m_ready = 0; + } + + + if (vx_d_cache_->o_p_waitrequest == 0) { + return true; + } else { + return false; + } + + +} + + +bool VX_d_cache::simulate() +{ + +// this->instruction_file_name = file_to_simulate; + // this->results << "\n****************\t" << file_to_simulate << "\t****************\n"; + +// this->ProcessFile(); + + // auto start_time = std::chrono::high_resolution_clock::now(); + + + //static bool stop = false; + //static int counter = 0; + //counter = 0; + //stop = false; + + // auto start_time = clock(); + + + vx_d_cache_->clk = 0; + vx_d_cache_->rst = 1; + //vortex->eval(); + //counter = 0; + vx_d_cache_->rst = 0; + + bool cont = false; + bool out_operation = false; + bool do_operation = true; + int other_counter = 0; + //while (this->stop && ((other_counter < 5))) + while (other_counter < 5) + { + + // std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n"; + // istop = ibus_driver(); + // dstop = !dbus_driver(); + + vx_d_cache_->clk = 1; + vx_d_cache_->eval(); + #ifdef VCD_OUTPUT + m_trace->dump(2*this->stats_total_cycles); + #endif + + //vortex->eval(); + //dstop = !dbus_driver(); + + out_operation = operation(other_counter, do_operation); + vx_d_cache_->clk = 0; + vx_d_cache_->eval(); + #ifdef VCD_OUTPUT + m_trace->dump((2*this->stats_total_cycles)+1); + #endif + //vortex->eval(); + + /* + // stop = istop && dstop; + stop = vortex->out_ebreak; + if (stop || cont) + { + cont = true; + counter++; + } else + { + counter = 0; + } + */ + if (out_operation) { + other_counter++; + do_operation = true; + } else { + do_operation = false; + } + ++(this->stats_total_cycles); + + if (this->stats_total_cycles > 5000) { + break; + } + + } + + std::cerr << "New Total Cycles: " << (this->stats_total_cycles + (this->stats_dram_accesses * 20)) << "\n"; + + //uint32_t status; + //ram.getWord(0, &status); + + //this->print_stats(); + + + + return (true); +} + + + + + + + + + diff --git a/old_rtl/cache/d_cache_test_bench_debug.h b/old_rtl/cache/d_cache_test_bench_debug.h new file mode 100644 index 00000000..54afa11a --- /dev/null +++ b/old_rtl/cache/d_cache_test_bench_debug.h @@ -0,0 +1 @@ +#define VCD_OUTPUT \ No newline at end of file diff --git a/old_rtl/interfaces/VX_branch_response_inter.v b/old_rtl/interfaces/VX_branch_response_inter.v new file mode 100644 index 00000000..b25b47c9 --- /dev/null +++ b/old_rtl/interfaces/VX_branch_response_inter.v @@ -0,0 +1,18 @@ + +`include "../VX_define.v" + +`ifndef VX_BRANCH_RSP + +`define VX_BRANCH_RSP + +interface VX_branch_response_inter (); + wire valid_branch; + wire branch_dir; + wire[31:0] branch_dest; + wire[`NW_M1:0] branch_warp_num; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_csr_req_inter.v b/old_rtl/interfaces/VX_csr_req_inter.v new file mode 100644 index 00000000..9080f0e1 --- /dev/null +++ b/old_rtl/interfaces/VX_csr_req_inter.v @@ -0,0 +1,24 @@ + +`include "../VX_define.v" + +`ifndef VX_CSR_REQ + +`define VX_CSR_REQ + +interface VX_csr_req_inter (); + + wire[`NT_M1:0] valid; + wire[`NW_M1:0] warp_num; + wire[4:0] rd; + wire[1:0] wb; + wire[4:0] alu_op; + wire is_csr; + wire[11:0] csr_address; + wire csr_immed; + wire[31:0] csr_mask; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_csr_wb_inter.v b/old_rtl/interfaces/VX_csr_wb_inter.v new file mode 100644 index 00000000..d8389cdb --- /dev/null +++ b/old_rtl/interfaces/VX_csr_wb_inter.v @@ -0,0 +1,21 @@ + +`include "../VX_define.v" + +`ifndef VX_CSR_WB_REQ + +`define VX_CSR_WB_REQ + +interface VX_csr_wb_inter (); + + wire[`NT_M1:0] valid; + wire[`NW_M1:0] warp_num; + wire[4:0] rd; + wire[1:0] wb; + + wire[`NT_M1:0][31:0] csr_result; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_dcache_request_inter.v b/old_rtl/interfaces/VX_dcache_request_inter.v new file mode 100644 index 00000000..ac841a76 --- /dev/null +++ b/old_rtl/interfaces/VX_dcache_request_inter.v @@ -0,0 +1,19 @@ + +`include "../VX_define.v" + +`ifndef VX_DCACHE_REQ + +`define VX_DCACHE_REQ + +interface VX_dcache_request_inter (); + + wire[`NT_M1:0][31:0] out_cache_driver_in_address; + wire[2:0] out_cache_driver_in_mem_read; + wire[2:0] out_cache_driver_in_mem_write; + wire[`NT_M1:0] out_cache_driver_in_valid; + wire[`NT_M1:0][31:0] out_cache_driver_in_data; + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_dcache_response_inter.v b/old_rtl/interfaces/VX_dcache_response_inter.v new file mode 100644 index 00000000..98ed58a3 --- /dev/null +++ b/old_rtl/interfaces/VX_dcache_response_inter.v @@ -0,0 +1,16 @@ + +`include "../VX_define.v" + +`ifndef VX_DCACHE_RSP + +`define VX_DCACHE_RSP + +interface VX_dcache_response_inter (); + + wire[`NT_M1:0][31:0] in_cache_driver_out_data; + wire delay; + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_dram_req_rsp_inter.v b/old_rtl/interfaces/VX_dram_req_rsp_inter.v new file mode 100644 index 00000000..f4d7012d --- /dev/null +++ b/old_rtl/interfaces/VX_dram_req_rsp_inter.v @@ -0,0 +1,27 @@ + +`include "../VX_define.v" + +`ifndef VX_DRAM_REQ_RSP_INTER + +`define VX_DRAM_REQ_RSP_INTER + +interface VX_dram_req_rsp_inter #( + parameter NUMBER_BANKS = 8, + parameter NUM_WORDS_PER_BLOCK = 4) (); + + // Req + wire [31:0] o_m_evict_addr; + wire [31:0] o_m_read_addr; + wire o_m_valid; + wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; + wire o_m_read_or_write; + + // Rsp + wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; + wire i_m_ready; + + +endinterface + + +`endif diff --git a/old_rtl/interfaces/VX_exec_unit_req_inter.v b/old_rtl/interfaces/VX_exec_unit_req_inter.v new file mode 100644 index 00000000..aab6c130 --- /dev/null +++ b/old_rtl/interfaces/VX_exec_unit_req_inter.v @@ -0,0 +1,51 @@ + +`include "../VX_define.v" + +`ifndef VX_EXE_UNIT_REQ_INTER + +`define VX_EXE_UNIT_REQ_INTER + +interface VX_exec_unit_req_inter (); + + // Meta + wire[`NT_M1:0] valid; + wire[`NW_M1:0] warp_num; + wire[31:0] curr_PC; + wire[31:0] PC_next; + + // Write Back Info + wire[4:0] rd; + wire[1:0] wb; + + // Data and alu op + wire[`NT_M1:0][31:0] a_reg_data; + wire[`NT_M1:0][31:0] b_reg_data; + wire[4:0] alu_op; + wire[4:0] rs1; + wire[4:0] rs2; + wire rs2_src; + wire[31:0] itype_immed; + wire[19:0] upper_immed; + + // Branch type + wire[2:0] branch_type; + + // Jal info + wire jalQual; + wire jal; + wire[31:0] jal_offset; + + /* verilator lint_off UNUSED */ + wire ebreak; + wire wspawn; + /* verilator lint_on UNUSED */ + + // CSR info + wire is_csr; + wire[11:0] csr_address; + wire csr_immed; + wire[31:0] csr_mask; +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_frE_to_bckE_req_inter.v b/old_rtl/interfaces/VX_frE_to_bckE_req_inter.v new file mode 100644 index 00000000..610d3525 --- /dev/null +++ b/old_rtl/interfaces/VX_frE_to_bckE_req_inter.v @@ -0,0 +1,46 @@ + +`include "../VX_define.v" + +`ifndef VX_FrE_to_BE_INTER + +`define VX_FrE_to_BE_INTER + +interface VX_frE_to_bckE_req_inter (); + + wire[11:0] csr_address; + wire is_csr; + wire csr_immed; + wire[31:0] csr_mask; + wire[4:0] rd; + wire[4:0] rs1; + wire[4:0] rs2; + wire[4:0] alu_op; + wire[1:0] wb; + wire rs2_src; + wire[31:0] itype_immed; + wire[2:0] mem_read; + wire[2:0] mem_write; + wire[2:0] branch_type; + wire[19:0] upper_immed; + wire[31:0] curr_PC; + /* verilator lint_off UNUSED */ + wire ebreak; + /* verilator lint_on UNUSED */ + wire jalQual; + wire jal; + wire[31:0] jal_offset; + wire[31:0] PC_next; + wire[`NT_M1:0] valid; + wire[`NW_M1:0] warp_num; + + // GPGPU stuff + wire is_wspawn; + wire is_tmc; + wire is_split; + wire is_barrier; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_gpr_clone_inter.v b/old_rtl/interfaces/VX_gpr_clone_inter.v new file mode 100644 index 00000000..26053ac9 --- /dev/null +++ b/old_rtl/interfaces/VX_gpr_clone_inter.v @@ -0,0 +1,18 @@ + +`include "../VX_define.v" + +`ifndef VX_GPR_CLONE_INTER + +`define VX_GPR_CLONE_INTER + + +interface VX_gpr_clone_inter (); +/* verilator lint_off UNUSED */ +wire is_clone; +wire[`NW_M1:0] warp_num; +/* verilator lint_on UNUSED */ +endinterface + + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_gpr_data_inter.v b/old_rtl/interfaces/VX_gpr_data_inter.v new file mode 100644 index 00000000..912f04a1 --- /dev/null +++ b/old_rtl/interfaces/VX_gpr_data_inter.v @@ -0,0 +1,14 @@ + +`include "../VX_define.v" + +`ifndef VX_gpr_data_INTER + +`define VX_gpr_data_INTER + +interface VX_gpr_data_inter (); + wire[`NT_M1:0][31:0] a_reg_data; + wire[`NT_M1:0][31:0] b_reg_data; +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_gpr_jal_inter.v b/old_rtl/interfaces/VX_gpr_jal_inter.v new file mode 100644 index 00000000..0c4b7afb --- /dev/null +++ b/old_rtl/interfaces/VX_gpr_jal_inter.v @@ -0,0 +1,14 @@ +`include "../VX_define.v" +`ifndef VX_GPR_JAL_INTER + +`define VX_GPR_JAL_INTER + + +interface VX_gpr_jal_inter (); + wire is_jal; + wire[31:0] curr_PC; +endinterface + + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_gpr_read_inter.v b/old_rtl/interfaces/VX_gpr_read_inter.v new file mode 100644 index 00000000..ccac96c0 --- /dev/null +++ b/old_rtl/interfaces/VX_gpr_read_inter.v @@ -0,0 +1,17 @@ +`include "../VX_define.v" +`ifndef VX_GPR_READ + +`define VX_GPR_READ + + +interface VX_gpr_read_inter (); + + wire[4:0] rs1; + wire[4:0] rs2; + wire[`NW_M1:0] warp_num; + +endinterface + + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_gpr_wspawn_inter.v b/old_rtl/interfaces/VX_gpr_wspawn_inter.v new file mode 100644 index 00000000..dfa0fc4c --- /dev/null +++ b/old_rtl/interfaces/VX_gpr_wspawn_inter.v @@ -0,0 +1,18 @@ +`include "../VX_define.v" +`ifndef VX_GPR_WSPAWN_INTER + +`define VX_GPR_WSPAWN_INTER + + +interface VX_gpr_wspawn_inter (); + /* verilator lint_off UNUSED */ + wire is_wspawn; + wire[`NW_M1:0] which_wspawn; + // wire[`NW_M1:0] warp_num; + /* verilator lint_on UNUSED */ + +endinterface + + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_gpu_inst_req_inter.v b/old_rtl/interfaces/VX_gpu_inst_req_inter.v new file mode 100644 index 00000000..1d24c960 --- /dev/null +++ b/old_rtl/interfaces/VX_gpu_inst_req_inter.v @@ -0,0 +1,27 @@ +`include "../VX_define.v" + +`ifndef VX_GPU_INST_REQ_IN + +`define VX_GPU_INST_REQ_IN + +interface VX_gpu_inst_req_inter(); + + wire[`NT_M1:0] valid; + wire[`NW_M1:0] warp_num; + wire is_wspawn; + wire is_tmc; + wire is_split; + + wire is_barrier; + + wire[31:0] pc_next; + + wire[`NT_M1:0][31:0] a_reg_data; + wire[31:0] rd2; + + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_icache_request_inter.v b/old_rtl/interfaces/VX_icache_request_inter.v new file mode 100644 index 00000000..9de1312b --- /dev/null +++ b/old_rtl/interfaces/VX_icache_request_inter.v @@ -0,0 +1,19 @@ + +`include "../VX_define.v" + +`ifndef VX_ICACHE_REQ + +`define VX_ICACHE_REQ + +interface VX_icache_request_inter (); + + wire[31:0] pc_address; + wire[2:0] out_cache_driver_in_mem_read; + wire[2:0] out_cache_driver_in_mem_write; + wire out_cache_driver_in_valid; + wire[31:0] out_cache_driver_in_data; + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_icache_response_inter.v b/old_rtl/interfaces/VX_icache_response_inter.v new file mode 100644 index 00000000..2373046b --- /dev/null +++ b/old_rtl/interfaces/VX_icache_response_inter.v @@ -0,0 +1,18 @@ +`include "../VX_define.v" + +`ifndef VX_ICACHE_RSP + +`define VX_ICACHE_RSP + +interface VX_icache_response_inter (); + + // wire ready; + // wire stall; + wire[31:0] instruction; + wire delay; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_inst_exec_wb_inter.v b/old_rtl/interfaces/VX_inst_exec_wb_inter.v new file mode 100644 index 00000000..929ba88d --- /dev/null +++ b/old_rtl/interfaces/VX_inst_exec_wb_inter.v @@ -0,0 +1,21 @@ + +`include "../VX_define.v" + +`ifndef VX_EXEC_UNIT_WB_INST_INTER + +`define VX_EXEC_UNIT_WB_INST_INTER + +interface VX_inst_exec_wb_inter (); + + wire[`NT_M1:0][31:0] alu_result; + wire[31:0] exec_wb_pc; + wire[4:0] rd; + wire[1:0] wb; + wire[`NT_M1:0] wb_valid; + wire[`NW_M1:0] wb_warp_num; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_inst_mem_wb_inter.v b/old_rtl/interfaces/VX_inst_mem_wb_inter.v new file mode 100644 index 00000000..d752a3a6 --- /dev/null +++ b/old_rtl/interfaces/VX_inst_mem_wb_inter.v @@ -0,0 +1,21 @@ + +`include "../VX_define.v" + +`ifndef VX_MEM_WB_INST_INTER + +`define VX_MEM_WB_INST_INTER + +interface VX_inst_mem_wb_inter (); + + wire[`NT_M1:0][31:0] loaded_data; + wire[31:0] mem_wb_pc; + wire[4:0] rd; + wire[1:0] wb; + wire[`NT_M1:0] wb_valid; + wire[`NW_M1:0] wb_warp_num; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_inst_meta_inter.v b/old_rtl/interfaces/VX_inst_meta_inter.v new file mode 100644 index 00000000..2fd68625 --- /dev/null +++ b/old_rtl/interfaces/VX_inst_meta_inter.v @@ -0,0 +1,16 @@ +`include "../VX_define.v" + +`ifndef VX_F_D_INTER + +`define VX_F_D_INTER + +interface VX_inst_meta_inter (); + wire[31:0] instruction; + wire[31:0] inst_pc; + wire[`NW_M1:0] warp_num; + wire[`NT_M1:0] valid; + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_jal_response_inter.v b/old_rtl/interfaces/VX_jal_response_inter.v new file mode 100644 index 00000000..e93a2d0a --- /dev/null +++ b/old_rtl/interfaces/VX_jal_response_inter.v @@ -0,0 +1,17 @@ + +`include "../VX_define.v" + +`ifndef VX_JAL_RSP + +`define VX_JAL_RSP + +interface VX_jal_response_inter (); + + wire jal; + wire[31:0] jal_dest; + wire[`NW_M1:0] jal_warp_num; + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_join_inter.v b/old_rtl/interfaces/VX_join_inter.v new file mode 100644 index 00000000..a465bf65 --- /dev/null +++ b/old_rtl/interfaces/VX_join_inter.v @@ -0,0 +1,17 @@ + +`include "../VX_define.v" + +`ifndef VX_JOIN_INTER + +`define VX_JOIN_INTER + +interface VX_join_inter (); + + wire is_join; + wire[`NW_M1:0] join_warp_num; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_lsu_req_inter.v b/old_rtl/interfaces/VX_lsu_req_inter.v new file mode 100644 index 00000000..408791f6 --- /dev/null +++ b/old_rtl/interfaces/VX_lsu_req_inter.v @@ -0,0 +1,24 @@ + +`include "../VX_define.v" + +`ifndef VX_LSU_REQ_INTER + +`define VX_LSU_REQ_INTER + +interface VX_lsu_req_inter (); + + wire[`NT_M1:0] valid; + wire[31:0] lsu_pc; + wire[`NW_M1:0] warp_num; + wire[`NT_M1:0][31:0] store_data; + wire[`NT_M1:0][31:0] base_address; // A reg data + wire[31:0] offset; // itype_immed + wire[2:0] mem_read; + wire[2:0] mem_write; + wire[4:0] rd; + wire[1:0] wb; + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_mem_req_inter.v b/old_rtl/interfaces/VX_mem_req_inter.v new file mode 100644 index 00000000..ee2a975d --- /dev/null +++ b/old_rtl/interfaces/VX_mem_req_inter.v @@ -0,0 +1,28 @@ +`include "../VX_define.v" + +`ifndef VX_MEM_REQ_IN + +`define VX_MEM_REQ_IN + +interface VX_mem_req_inter (); + + wire[`NT_M1:0][31:0] alu_result; + wire[2:0] mem_read; + wire[2:0] mem_write; + wire[4:0] rd; + wire[1:0] wb; + wire[4:0] rs1; + wire[4:0] rs2; + wire[`NT_M1:0][31:0] rd2; + wire[31:0] PC_next; + wire[31:0] curr_PC; + wire[31:0] branch_offset; + wire[2:0] branch_type; + wire[`NT_M1:0] valid; + wire[`NW_M1:0] warp_num; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_mw_wb_inter.v b/old_rtl/interfaces/VX_mw_wb_inter.v new file mode 100644 index 00000000..bbf4733e --- /dev/null +++ b/old_rtl/interfaces/VX_mw_wb_inter.v @@ -0,0 +1,22 @@ + +`include "../VX_define.v" + +`ifndef VX_MW_WB_INTER + +`define VX_MW_WB_INTER + +interface VX_mw_wb_inter (); + + wire[`NT_M1:0][31:0] alu_result; + wire[`NT_M1:0][31:0] mem_result; + wire[4:0] rd; + wire[1:0] wb; + wire[31:0] PC_next; + wire[`NT_M1:0] valid; + wire [`NW_M1:0] warp_num; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_warp_ctl_inter.v b/old_rtl/interfaces/VX_warp_ctl_inter.v new file mode 100644 index 00000000..53dec2a1 --- /dev/null +++ b/old_rtl/interfaces/VX_warp_ctl_inter.v @@ -0,0 +1,36 @@ + +`include "../VX_define.v" + +`ifndef VX_WARP_CTL_INTER + +`define VX_WARP_CTL_INTER + +interface VX_warp_ctl_inter (); + + wire[`NW_M1:0] warp_num; + wire change_mask; + wire[`NT_M1:0] thread_mask; + + wire wspawn; + wire[31:0] wspawn_pc; + wire[`NW-1:0] wspawn_new_active; + + wire ebreak; + + // barrier + wire is_barrier; + wire[31:0] barrier_id; + wire[$clog2(`NW):0] num_warps; + + wire is_split; + wire dont_split; + wire[`NW_M1:0] split_warp_num; + wire[`NT_M1:0] split_new_mask; + wire[`NT_M1:0] split_later_mask; + wire[31:0] split_save_pc; + + +endinterface + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_wb_inter.v b/old_rtl/interfaces/VX_wb_inter.v new file mode 100644 index 00000000..c40cf4fe --- /dev/null +++ b/old_rtl/interfaces/VX_wb_inter.v @@ -0,0 +1,21 @@ +`include "../VX_define.v" + +`ifndef VX_WB_INTER + +`define VX_WB_INTER + + +interface VX_wb_inter (); + + wire[`NT_M1:0][31:0] write_data; + wire[31:0] wb_pc; + wire[4:0] rd; + wire[1:0] wb; + wire[`NT_M1:0] wb_valid; + wire[`NW_M1:0] wb_warp_num; + +endinterface + + + +`endif \ No newline at end of file diff --git a/old_rtl/interfaces/VX_wstall_inter.v b/old_rtl/interfaces/VX_wstall_inter.v new file mode 100644 index 00000000..8699b022 --- /dev/null +++ b/old_rtl/interfaces/VX_wstall_inter.v @@ -0,0 +1,15 @@ +`include "../VX_define.v" + +`ifndef VX_WSTALL_INTER + +`define VX_WSTALL_INTER + + +interface VX_wstall_inter(); + wire wstall; + wire[`NW_M1:0] warp_num; +endinterface + + + +`endif \ No newline at end of file diff --git a/old_rtl/modelsim/Makefile b/old_rtl/modelsim/Makefile new file mode 100644 index 00000000..7a3a4efd --- /dev/null +++ b/old_rtl/modelsim/Makefile @@ -0,0 +1,124 @@ + + +ALL:sim + +#TOOL INPUT +SRC = \ + vortex_dpi.cpp \ + vortex_tb.v \ +../VX_define.v \ +../VX_define_synth.v \ +../interfaces/VX_branch_response_inter.v \ +../interfaces/VX_csr_req_inter.v \ +../interfaces/VX_csr_wb_inter.v \ +../interfaces/VX_dcache_request_inter.v \ +../interfaces/VX_dcache_response_inter.v \ +../interfaces/VX_dram_req_rsp_inter.v \ +../interfaces/VX_exec_unit_req_inter.v \ +../interfaces/VX_frE_to_bckE_req_inter.v \ +../interfaces/VX_gpr_clone_inter.v \ +../interfaces/VX_gpr_data_inter.v \ +../interfaces/VX_gpr_jal_inter.v \ +../interfaces/VX_gpr_read_inter.v \ +../interfaces/VX_gpr_wspawn_inter.v \ +../interfaces/VX_gpu_inst_req_inter.v \ +../interfaces/VX_icache_request_inter.v \ +../interfaces/VX_icache_response_inter.v \ +../interfaces/VX_inst_exec_wb_inter.v \ +../interfaces/VX_inst_mem_wb_inter.v \ +../interfaces/VX_inst_meta_inter.v \ +../interfaces/VX_jal_response_inter.v \ +../interfaces/VX_join_inter.v \ +../interfaces/VX_lsu_req_inter.v \ +../interfaces/VX_mem_req_inter.v \ +../interfaces/VX_mw_wb_inter.v \ +../interfaces/VX_warp_ctl_inter.v \ +../interfaces/VX_wb_inter.v \ +../interfaces/VX_wstall_inter.v \ +../VX_alu.v \ +../VX_back_end.v \ +../VX_csr_handler.v \ +../VX_csr_wrapper.v \ +../VX_decode.v \ +../VX_dmem_controller.v \ +../VX_execute_unit.v \ +../VX_fetch.v \ +../VX_front_end.v \ +../VX_generic_priority_encoder.v \ +../VX_generic_register.v \ +../VX_generic_stack.v \ +../VX_gpgpu_inst.v \ +../VX_gpr.v \ +../VX_gpr_stage.v \ +../VX_gpr_wrapper.v \ +../VX_inst_multiplex.v \ +../VX_lsu.v \ +../VX_lsu_addr_gen.v \ +../VX_priority_encoder.v \ +../VX_priority_encoder_w_mask.v \ +../VX_scheduler.v \ +../VX_warp.v \ +../VX_countones.v \ +../VX_warp_scheduler.v \ +../VX_writeback.v \ +../Vortex.v \ +../byte_enabled_simple_dual_port_ram.v \ +../cache/VX_Cache_Bank.v \ +../cache/VX_cache_bank_valid.v \ +../cache/VX_cache_data.v \ +../cache/VX_d_cache.v \ +../cache/VX_generic_pe.v \ +../cache/cache_set.v \ +../cache/VX_cache_data_per_index.v \ +../pipe_regs/VX_d_e_reg.v \ +../pipe_regs/VX_f_d_reg.v \ +../shared_memory/VX_bank_valids.v \ +../shared_memory/VX_priority_encoder_sm.v \ +../shared_memory/VX_shared_memory.v \ +../shared_memory/VX_shared_memory_block.v \ +../../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \ +../../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \ +../../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \ +../../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v \ +../../models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v + +# ../../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v + +# vortex_dpi.h + + +CMD= \ +-do "VoptFlow = 0; \ + vcd file vortex.vcd; \ + vcd add -r /vortex_tb/*; \ + vcd add -r /vortex/*; \ + run -all; \ + quit -f" + + +OPT=-sv -sv12compat + +LIB = vortex_lib + +# LOG=-logfile vortex_tb.log +LOG= + +# setup: source cshrc.modelsim +# vlib + +lib: + vlib vortex_lib + +comp: + vlog $(OPT) -work $(LIB) $(SRC) + # vlog -O0 -dpiheader vortex_dpi.h $(OPT) -work $(LIB) $(SRC) + + +sim: comp + # vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log + vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log + + + + + diff --git a/old_rtl/modelsim/cshrc.modelsim b/old_rtl/modelsim/cshrc.modelsim new file mode 100644 index 00000000..8f9133d7 --- /dev/null +++ b/old_rtl/modelsim/cshrc.modelsim @@ -0,0 +1,8 @@ + setenv PATH "${PATH}:/tools/mentor/modelsim/ms106a/modeltech/bin" + setenv MTI_VCO_MODE 1 +if (${?LM_LICENSE_FILE}) then + setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu:${LM_LICENSE_FILE}" + else + setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu" +endif +setenv MGLS_LICENSE_FILE 1717@ece-linlic.ece.gatech.edu \ No newline at end of file diff --git a/old_rtl/modelsim/modelsim.mpf b/old_rtl/modelsim/modelsim.mpf new file mode 100644 index 00000000..b1898d0c --- /dev/null +++ b/old_rtl/modelsim/modelsim.mpf @@ -0,0 +1,2275 @@ +; vsim modelsim.ini file, version 10.4 +[Version] +INIVersion = "10.6a" + +; Copyright 1991-2017 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +vital2000 = $MODEL_TECH/../vital2000 +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; +verilog = $MODEL_TECH/../verilog +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std +mtiAvm = $MODEL_TECH/../avm +mtiRnm = $MODEL_TECH/../rnm +mtiOvm = $MODEL_TECH/../ovm-2.1.2 +mtiUvm = $MODEL_TECH/../uvm-1.1d +mtiUPF = $MODEL_TECH/../upf_lib +mtiPA = $MODEL_TECH/../pa_lib +floatfixlib = $MODEL_TECH/../floatfixlib +mc2_lib = $MODEL_TECH/../mc2_lib +osvvm = $MODEL_TECH/../osvvm + +; added mapping for ADMS +mgc_ams = $MODEL_TECH/../mgc_ams +ieee_env = $MODEL_TECH/../ieee_env + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib +infact = $MODEL_TECH/../infact +vhdlopt_lib = $MODEL_TECH/../vhdlopt_lib + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command “vopt -L ./path/to/lib1 –o opttop top”, +; vopt automatically performs the mapping “lib1 -> ./path/to/lib1”. +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = work +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset " syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.3.3, 4.5.0 +; CppInstall = 4.5.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = [ ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCover = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for checkpointing foreign C++ libraries. +; The valid arguments are: 1 and 0. +; 1 : turn on the support +; 0 : turn off the support (default) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 1 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify if the solver should attempt to ignore overflow/underflow semantics +; for arithmetic constraints (multiply, addition, subtraction) in order to +; improve performance. The "solveignoreoverflow" attribute can be specified on +; a per-call basis to randomize() to override this setting. +; The default value is 0 (overflow/underflow is not ignored). Set to 1 to +; ignore overflow/underflow. +; SolveIgnoreOverflow = 0 + +; Specifies the maximum size that a dynamic array may be resized to by the +; solver. If the solver attempts to resize a dynamic array to a size greater +; than the specified limit, the solver will abort with an error. +; The default value is 10000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 10000 + +; Error message severity when randomize() failure is detected. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; The default is 0 (no error). +; SolveFailSeverity = 0 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable debug information for randomize() failures. +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; The default is 0 (disabled). Set to 1 to enable basic debug (with no +; performance penalty). Set to 2 for enhanced debug (will result in slower +; runtime performance). +; SolveFailDebug = 0 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify the maximum number of tests that the ACT solver may evaluate before +; abandoning an attempt to solve a particular constraint scenario. +; The default value is 2000000. A value of 0 indicates no limit. +; SolveACTMaxTests = 2000000 + +; Specify the maximum number of operations that the ACT solver may perform +; before abandoning an attempt to solve a particular constraint scenario. The +; value is specified in 1000000s of operations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveACTMaxOps = 10000 + +; Specify the number of times the ACT solver will retry to evaluate a constraint +; scenario that fails due to the SolveACTMax[Tests|Ops] threshold. +; The default value is 0 (no retry). +; SolveACTRetryCount = 0 + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Specify the memory threshold for the System Verilog garbage collector. +; The value is the number of megabytes of class objects that must accumulate +; before the garbage collector is run. +; The GCThreshold setting is used when class debug mode is disabled to allow +; less frequent garbage collection and better simulation performance. +; The GCThresholdClassDebug setting is used when class debug mode is enabled +; to allow for more frequent garbage collection. +; GCThreshold = 100 +; GCThresholdClassDebug = 5 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +MvcHome = $MODEL_TECH/.. + +; Location of InFact installation. The default is $MODEL_TECH/../../infact +; +; InFactHome = $MODEL_TECH/../../infact + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +; Suppress file type registration. +; SuppressFileTypeReg = 1 + +; Enable/disable non-LRM compliant SystemVerilog language extensions. +; Valid extensions are: +; cfce - generate an error if $cast fails as a function +; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks +; expdfmt - enable format string extensions for $display/$sformatf +; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) +; fmtcap - prints capital hex digits with %X/%H in display calls +; iddp - ignore DPI disable protocol check +; noexptc - ignore DPI export type name overloading check +; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") +; realrand - support randomize() with real variables and constraints (Default) +; SvExtensions = [+|-][,[+|-]*] + +; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. +; Valid extensions are: +; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles +; forkjoinstab - preserve parent thread random stability when seeding fork/join sub-threads (Default) +; nonrandstab - disable seeding of "non-random" class instances (Default) +; nodist - interpret 'dist' constraint as 'inside' (ACT only) +; noorder - ignore solve/before ordering constraints (ACT only) +; packrandidx - allow random index for packed variable in constraint (Default) +; promotedist - promote priority of 'dist' constraint if LHS has no solve/before +; randskew - skew randomize results (ACT only) +; SvRandExtensions = [+|-][,[+|-]*] + +; Controls the formatting of '%p' and '%P' conversion specification, used in $display +; and similar system tasks. +; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. +; The 'I' flag when present causes relevant data types to be expanded and indented into +; a more readable format. +; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). +; 2. SVPrettyPrintFlags=L limits the output to lines. +; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). +; 3. SVPrettyPrintFlags=C limits the output to characters. +; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). +; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes +; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). +; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes +; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). +; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . +; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). +; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. +; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). +; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. +; 8. Items 1-7 above can be combined as a comma separated list. +; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) +; SVPrettyPrintFlags=I4S + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +suppress = 8780 ;an explanation can be had by running: verror 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3601 +; suppress = 3009,CNNODP,3601,TFMPC +; suppress = 8683,8684 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear only in the transcript. The other settings +; are to send messages to the wlf file only (messages that are +; recorded in the wlf file can be viewed in the MsgViewer) or to both +; the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; msgmode = tran + +; Controls number of displays of a particluar message +; default value is 5 +; MsgLimitCount = 5 + +[utils] +; Default Library Type (while creating a library with "vlib") +; 0 - legacy library using subdirectories for design units +; 2 - flat library +; DefaultLibType = 2 + +; Flat Library Page Size (while creating a library with "vlib") +; Set the size in bytes for flat library file pages. Libraries containing +; very large files may benefit from a larger value. +; FlatLibPageSize = 8192 + +; Flat Library Page Cleanup Percentage (while creating a library with "vlib") +; Set the percentage of total pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeleteThreshold. +; FlatLibPageDeletePercentage = 50 + +; Flat Library Page Cleanup Threshold (while creating a library with "vlib") +; Set the number of pages deleted before library cleanup can occur. +; This setting is applied together with FlatLibPageDeletePercentage. +; FlatLibPageDeleteThreshold = 1000 + +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 56 +Project_File_0 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_shared_memory.v +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 54 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_clone_inter.v +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 31 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_2 = /nethome/felsabbagh3/research/Vortex/rtl/icarus/vortex_tb.v +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_3 = /nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v +Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_4 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v +Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 44 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_5 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v +Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_6 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v +Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 49 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_7 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v +Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 35 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_8 = /nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v +Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1572058635 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_9 = /nethome/felsabbagh3/research/Vortex/rtl/cache/cache_set.v +Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_10 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v +Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 39 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_11 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_cache_bank_valid.v +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_12 = /nethome/felsabbagh3/research/Vortex/rtl/VX_alu.v +Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1571845660 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_13 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v +Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 51 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_14 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_join_inter.v +Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 43 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_15 = /nethome/felsabbagh3/research/Vortex/rtl/VX_csr_handler.v +Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_16 = /nethome/felsabbagh3/research/Vortex/rtl/VX_dmem_controller.v +Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_17 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v +Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_18 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_exec_unit_req_inter.v +Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 29 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_19 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_cache_data.v +Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_20 = /nethome/felsabbagh3/research/Vortex/rtl/VX_generic_register.v +Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1571845660 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_21 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v +Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 42 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_22 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_Cache_Bank.v +Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_23 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_wb_inter.v +Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_24 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v +Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 36 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_25 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wb_inter.v +Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 48 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_26 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v +Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 38 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_27 = /nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v +Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572061058 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_28 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_read_inter.v +Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 34 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_29 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mw_wb_inter.v +Project_File_P_29 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 46 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_30 = /nethome/felsabbagh3/research/Vortex/rtl/byte_enabled_simple_dual_port_ram.v +Project_File_P_30 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_31 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v +Project_File_P_31 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 26 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_32 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_data_inter.v +Project_File_P_32 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 32 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_33 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_set_bit.v +Project_File_P_33 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 53 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_34 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v +Project_File_P_34 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 27 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_35 = /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v +Project_File_P_35 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1572058635 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_36 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_req_inter.v +Project_File_P_36 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 24 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_37 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v +Project_File_P_37 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 40 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_38 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v +Project_File_P_38 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 37 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_39 = /nethome/felsabbagh3/research/Vortex/rtl/VX_execute_unit.v +Project_File_P_39 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_40 = /nethome/felsabbagh3/research/Vortex/rtl/cache/bank.v +Project_File_P_40 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_41 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v +Project_File_P_41 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 45 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_42 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dram_req_rsp_inter.v +Project_File_P_42 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1572058636 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_43 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_priority_encoder_sm.v +Project_File_P_43 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 52 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_44 = /nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v +Project_File_P_44 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_45 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_warp_ctl_inter.v +Project_File_P_45 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 47 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_46 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_Cache_Block_DM.v +Project_File_P_46 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_47 = /nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v +Project_File_P_47 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_48 = /nethome/felsabbagh3/research/Vortex/rtl/Vortex.v +Project_File_P_48 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_49 = /nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v +Project_File_P_49 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_50 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache_encapsulate.v +Project_File_P_50 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_51 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_shared_memory_block.v +Project_File_P_51 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1571845660 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 55 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_52 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v +Project_File_P_52 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 41 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_53 = /nethome/felsabbagh3/research/Vortex/rtl/pipe_regs/VX_d_e_reg.v +Project_File_P_53 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 50 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_54 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v +Project_File_P_54 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1572058635 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_55 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_jal_inter.v +Project_File_P_55 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 33 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 10 +Project_Minor_Version = 6 diff --git a/old_rtl/modelsim/vortex_dpi.cpp b/old_rtl/modelsim/vortex_dpi.cpp new file mode 100644 index 00000000..67af68ab --- /dev/null +++ b/old_rtl/modelsim/vortex_dpi.cpp @@ -0,0 +1,328 @@ + +// #include + +// #include "VX_define.h" + + +#include <../simulate/ram.h> +#include +#include +#include "svdpi.h" + +#include "../simulate/VX_define.h" + +// #include "vortex_dpi.h" + +extern "C" { + void load_file (char * filename); + void ibus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); + void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); + void io_handler (bool clk, bool io_valid, unsigned io_data); + void gracefulExit(int); +} + +RAM ram; +bool refill; +unsigned refill_addr; +bool i_refill; +unsigned i_refill_addr; + +unsigned num_cycles; + +unsigned getIndex(int, int, int); +unsigned calculate_bits_per_bank_num(int); + +unsigned getIndex(int r, int c, int numCols) +{ + return (r * numCols) + c; +} + +unsigned calculate_bits_per_bank_num(int num) +{ + int shifted_num = 0; + for(int i = 0; i < num; i++){ + shifted_num = (shifted_num << 1)| 1 ; + } + return shifted_num; +} + + +void load_file(char * filename) +{ + num_cycles = 0; + // printf("\n\n\n\n**********************\n"); + // printf("Inside load_file\n"); + + fprintf(stderr, "\n\n\n\n**********************\n"); + loadHexImpl(filename, &ram); + // printf("Filename: %s\n", filename); + refill = false; + i_refill = false; +} + +void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready) +{ + + + // Default values + { + s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; + (*i_m_ready) = false; + for (int i = 0; i < cache_banks; i++) + { + for (int j = 0; j < num_words_per_block; j++) + { + + unsigned index = getIndex(i,j, num_words_per_block); + + real_i_m_readdata[index].aval = 0x506070; + + // svGetArrElemPtr2(i_m_readdata, i, j); + // svPutLogicArrElem2VecVal(i_m_readdata, i, j); + // i_m_readdata[getIndex(i,j, num_words_per_block)] = 0; + } + } + } + + + if (clk) + { + // Do nothing on positive edge + } + else + { + + if (i_refill) + { + // svGetArrElemPtr2((*i_m_readdata), 0,0); + // fprintf(stderr, "--------------------------------\n"); + i_refill = false; + + + *i_m_ready = true; + s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; + for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) + { + unsigned new_addr = i_refill_addr + (4*curr_e); + + + unsigned addr_without_byte = new_addr >> 2; + + unsigned bits_per_bank = (int)log2(cache_banks); + // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); + unsigned maskbits_per_bank = cache_banks - 1; + unsigned bank_num = addr_without_byte & maskbits_per_bank; + unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; + unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); + + unsigned value; + ram.getWord(new_addr, &value); + + fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value); + unsigned index = getIndex(bank_num,offset_num, num_words_per_block); + + // fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value); + + real_i_m_readdata[index].aval = value; + + } + } + else + { + if (o_m_valid) + { + + s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata; + + if (o_m_read_or_write) + { + // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); + + for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) + { + unsigned new_addr = (o_m_evict_addr) + (4*curr_e); + + + unsigned addr_without_byte = new_addr >> 2; + unsigned bits_per_bank = (int)log2(cache_banks); + // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); + unsigned maskbits_per_bank = cache_banks - 1; + unsigned bank_num = addr_without_byte & maskbits_per_bank; + unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; + unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); + // unsigned offset_num = addr_wihtout_bank & 0x3; + unsigned index = getIndex(bank_num,offset_num, num_words_per_block); + + + + unsigned new_value = real_o_m_writedata[index].aval; + + // new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num); + // new_value = getElem(o_m_writedata, index); + // unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)]; + + + ram.writeWord( new_addr, &new_value); + + fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value); + } + + } + + // Respond next cycle + i_refill = true; + i_refill_addr = o_m_read_addr; + } + } + + } +} + + +void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready) +{ + + + // Default values + { + s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; + (*i_m_ready) = false; + for (int i = 0; i < cache_banks; i++) + { + for (int j = 0; j < num_words_per_block; j++) + { + + unsigned index = getIndex(i,j, num_words_per_block); + + real_i_m_readdata[index].aval = 0x506070; + + // svGetArrElemPtr2(i_m_readdata, i, j); + // svPutLogicArrElem2VecVal(i_m_readdata, i, j); + // i_m_readdata[getIndex(i,j, num_words_per_block)] = 0; + } + } + } + + + if (clk) + { + // Do nothing on positive edge + } + else + { + + if (refill) + { + // svGetArrElemPtr2((*i_m_readdata), 0,0); + // fprintf(stderr, "--------------------------------\n"); + refill = false; + + + *i_m_ready = true; + s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; + for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) + { + unsigned new_addr = refill_addr + (4*curr_e); + + + unsigned addr_without_byte = new_addr >> 2; + + unsigned bits_per_bank = (int)log2(cache_banks); + // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); + unsigned maskbits_per_bank = cache_banks - 1; + unsigned bank_num = addr_without_byte & maskbits_per_bank; + unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; + unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); + + unsigned value; + ram.getWord(new_addr, &value); + + fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value); + unsigned index = getIndex(bank_num,offset_num, num_words_per_block); + + // fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value); + + real_i_m_readdata[index].aval = value; + + } + } + else + { + if (o_m_valid) + { + + s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata; + + if (o_m_read_or_write) + { + // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); + + for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) + { + unsigned new_addr = (o_m_evict_addr) + (4*curr_e); + + + unsigned addr_without_byte = new_addr >> 2; + unsigned bits_per_bank = (int)log2(cache_banks); + // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); + unsigned maskbits_per_bank = cache_banks - 1; + unsigned bank_num = addr_without_byte & maskbits_per_bank; + unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; + unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); + // unsigned offset_num = addr_wihtout_bank & 0x3; + unsigned index = getIndex(bank_num,offset_num, num_words_per_block); + + + + unsigned new_value = real_o_m_writedata[index].aval; + + // new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num); + // new_value = getElem(o_m_writedata, index); + // unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)]; + + + ram.writeWord( new_addr, &new_value); + + fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value); + } + + } + + // Respond next cycle + refill = true; + refill_addr = o_m_read_addr; + } + } + + } +} + + +void io_handler(bool clk, bool io_valid, unsigned io_data) +{ + // printf("Inside io_handler\n"); + if (clk) + { + // Do nothing + } + else + { + if (io_valid) + { + uint32_t data_write = (uint32_t) (io_data); + + fprintf(stderr, "%c", (char) data_write); + fflush(stderr); + } + } +} + +void gracefulExit(int cycles) +{ + fprintf(stderr, "*********************\n\n"); + fprintf(stderr, "DPI Cycle Num: %d\tVerilog Cycle Num: %d\n", num_cycles, cycles); +} + + + + diff --git a/old_rtl/modelsim/vortex_dpi.h b/old_rtl/modelsim/vortex_dpi.h new file mode 100644 index 00000000..4a3509d0 --- /dev/null +++ b/old_rtl/modelsim/vortex_dpi.h @@ -0,0 +1,8 @@ + +extern "C" { + void load_file (char * filename); + void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); + void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); + void io_handler (bool clk, bool io_valid, unsigned io_data); + void gracefulExit(); +} \ No newline at end of file diff --git a/old_rtl/modelsim/vortex_tb.v b/old_rtl/modelsim/vortex_tb.v new file mode 100644 index 00000000..1db58aed --- /dev/null +++ b/old_rtl/modelsim/vortex_tb.v @@ -0,0 +1,160 @@ + +`include "../VX_define.v" + +//`define NUMBER_BANKS 8 +//`define NUM_WORDS_PER_BLOCK 4 + +`define ARM_UD_MODEL + +`timescale 1ns/1ps + +import "DPI-C" load_file = function void load_file(input string filename); + +/* +import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr, + output int instruction); + */ + +import "DPI-C" ibus_driver = function void ibus_driver( input logic clk, + input int o_m_read_addr, + input int o_m_evict_addr, + input logic o_m_valid, + input reg[31:0] o_m_writedata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], + input logic o_m_read_or_write, + input int cache_banks, + input int words_per_block, + // Rsp + output reg[31:0] i_m_readdata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], + output logic i_m_ready); + +import "DPI-C" dbus_driver = function void dbus_driver( input logic clk, + input int o_m_read_addr, + input int o_m_evict_addr, + input logic o_m_valid, + input reg[31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0], + input logic o_m_read_or_write, + input int cache_banks, + input int words_per_block, + // Rsp + output reg[31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0], + output logic i_m_ready); + + +import "DPI-C" io_handler = function void io_handler(input logic clk, input logic io_valid, input int io_data); + +import "DPI-C" gracefulExit = function void gracefulExit(input int cycle_num); + +module vortex_tb ( + +); + + int cycle_num; + +reg clk; +reg reset; +reg[31:0] icache_response_instruction; +reg[31:0] icache_request_pc_address; +// IO +reg io_valid; +reg[31:0] io_data; +// Req + reg [31:0] o_m_read_addr_d; + reg [31:0] o_m_evict_addr_d; + reg o_m_valid_d; + reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0]; + reg o_m_read_or_write_d; + + // Rsp + reg [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0]; + reg i_m_ready_d; + +// Req + reg [31:0] o_m_read_addr_i; + reg [31:0] o_m_evict_addr_i; + reg o_m_valid_i; + reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0]; + reg o_m_read_or_write_i; + + // Rsp + reg [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0]; + reg i_m_ready_i; +reg out_ebreak; + + + reg[31:0] hi; + + integer temp; + + initial begin + // $fdumpfile("vortex1.vcd"); + load_file("../../runtime/mains/simple/vx_simple_main.hex"); + // load_file("../../emulator/riscv_tests/rv32ui-p-add.hex"); + //load_file("../../kernel/vortex_test.hex"); + $dumpvars(0, vortex_tb); + reset = 1; + clk = 0; + #5 reset = 1; + clk = 1; + cycle_num = 0; + end + + Vortex vortex( + .clk (clk), + .reset (reset), + .icache_response_instruction (icache_response_instruction), + .icache_request_pc_address (icache_request_pc_address), + .io_valid (io_valid), + .io_data (io_data), + .o_m_read_addr_d (o_m_read_addr_d), + .o_m_evict_addr_d (o_m_evict_addr_d), + .o_m_valid_d (o_m_valid_d), + .o_m_writedata_d (o_m_writedata_d), + .o_m_read_or_write_d (o_m_read_or_write_d), + .i_m_readdata_d (i_m_readdata_d), + .i_m_ready_d (i_m_ready_d), + .o_m_read_addr_i (o_m_read_addr_i), + .o_m_evict_addr_i (o_m_evict_addr_i), + .o_m_valid_i (o_m_valid_i), + .o_m_writedata_i (o_m_writedata_i), + .o_m_read_or_write_i (o_m_read_or_write_i), + .i_m_readdata_i (i_m_readdata_i), + .i_m_ready_i (i_m_ready_i), + .out_ebreak (out_ebreak) + ); + + always @(negedge clk) begin + ibus_driver(clk, o_m_read_addr_i, o_m_evict_addr_i, o_m_valid_i, o_m_writedata_i, o_m_read_or_write_i, `ICACHE_BANKS, `ICACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_i, i_m_ready_i); + dbus_driver(clk, o_m_read_addr_d, o_m_evict_addr_d, o_m_valid_d, o_m_writedata_d, o_m_read_or_write_d, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_d, i_m_ready_d); + io_handler (clk, io_valid, io_data); + + end + + always @(posedge clk) begin + if (out_ebreak) begin + gracefulExit(cycle_num); + #40 $finish; + end + end + + always @(posedge clk) begin + cycle_num = cycle_num + 1; + end + + always @(clk, posedge reset) begin + if (reset) begin + reset = 0; + clk = 0; + end + + #5 clk <= ~clk; + + end + +endmodule + + + + + + + diff --git a/old_rtl/modelsim/work/_info b/old_rtl/modelsim/work/_info new file mode 100644 index 00000000..00edac9f --- /dev/null +++ b/old_rtl/modelsim/work/_info @@ -0,0 +1,1084 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +d/nethome/felsabbagh3 +vbyte_enabled_simple_dual_port_ram +Z0 DXx6 sv_std 3 std 0 22 AD7iAPLo6nTIKk>?2fFo2 +R2 +!s105 VX_back_end_v_unit +S1 +R3 +R9 +8/nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v +F/nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v +L0 1 +R5 +r1 +!s85 0 +31 +!s108 1572060852.000000 +!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v| +!i113 0 +R7 +R8 +n@v@x_back_end +vVX_bank_valids +R0 +!s110 1572060870 +!i10b 1 +!s100 8J^J:@i9Meh3ejJzoMNRl1 +IVMcgc?onFY87NP^=[feO_0 +R2 +!s105 VX_bank_valids_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v +F/nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v +L0 4 +R5 +r1 +!s85 0 +31 +!s108 1572060870.000000 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v| +!i113 0 +R7 +R8 +n@v@x_bank_valids +YVX_branch_response_inter +R0 +Z11 !s110 1572060860 +!i10b 1 +!s100 ?IdSOM2]VFSUk;4?QYfAj1 +IRZ9enLe49LL`mLAeG1dL41 +R2 +!s105 VX_branch_response_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +Z12 !s108 1572060860.000000 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v| +!i113 0 +R7 +R8 +n@v@x_branch_response_inter +vVX_Cache_Bank +R0 +!s110 1572060857 +!i10b 1 +!s100 j9_Ic?]NV;A]SX?YSN022 +R2 +!s105 VX_csr_req_inter_v_unit +S1 +R3 +R4 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-reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_wb_inter.v| +!i113 0 +R7 +R8 +n@v@x_csr_wb_inter +vVX_csr_wrapper +R0 +!s110 1572061082 +!i10b 1 +!s100 LbYbMNCf=0AzhCB>CP4gV1 +ImWJ;a=;GMB9KeJ;cTDEl30 +R2 +!s105 VX_csr_wrapper_v_unit +S1 +R3 +w1572061058 +8/nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v +F/nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v +L0 3 +R5 +r1 +!s85 0 +31 +!s108 1572061081.000000 +!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v| +!i113 0 +R7 +R8 +n@v@x_csr_wrapper +vVX_d_cache +R0 +!s110 1572060859 +!i10b 1 +!s100 OI>VY^XI_AKKhz`Z>2kf=0 +Ih:mHKdjd9hE?1H5WRS>;:2 +R2 +!s105 VX_d_cache_v_unit +S1 +R3 +R9 +8/nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v +F/nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v +L0 16 +R5 +r1 +!s85 0 +31 +!s108 1572060859.000000 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v| +!i113 0 +R7 +R8 +n@v@x_d_cache +YVX_dcache_request_inter +R0 +!s110 1572060862 +!i10b 1 +!s100 7cnI6Rc92LVQ67`57EET>1 +IMzzF:AXEm?=JAV9ceXl713 +R2 +!s105 VX_dcache_request_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +Z13 !s108 1572060862.000000 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v| +!i113 0 +R7 +R8 +n@v@x_dcache_request_inter +YVX_dcache_response_inter +R0 +Z14 !s110 1572060863 +!i10b 1 +!s100 H9LFf[:T8ZFdGUznKiDN_2 +IZ1aNoi`DU3KPgF;LQFF[`3 +R2 +!s105 VX_dcache_response_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +R13 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v| +!i113 0 +R7 +R8 +n@v@x_dcache_response_inter +vVX_decode +R0 +Z15 !s110 1572060854 +!i10b 1 +!s100 NVHcmOEV]oO`:ha0UUMGZ2 +I_H?4Go:N4bjfOHiN=@mYC3 +R2 +!s105 VX_decode_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v +F/nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v +L0 4 +R5 +r1 +!s85 0 +31 +Z16 !s108 1572060854.000000 +!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v| +!i113 0 +R7 +R8 +n@v@x_decode +vVX_dmem_controller +R0 +R15 +!i10b 1 +!s100 RPQH;KGJ9lb=hPcTmNSPlAOAD3 +R2 +!s105 VX_fetch_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v +F/nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v +L0 4 +R5 +r1 +!s85 0 +31 +!s108 1572060855.000000 +!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v| +!i113 0 +R7 +R8 +n@v@x_fetch +YVX_frE_to_bckE_req_inter +R0 +R14 +!i10b 1 +!s100 9@N3T^SL_K01m@5jA4Nh31 +IFoT0^;QA;]9WTCkS<5_TH2 +R2 +!s105 VX_frE_to_bckE_req_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +R17 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v| +!i113 0 +R7 +R8 +n@v@x_fr@e_to_bck@e_req_inter +vVX_front_end +R0 +Z18 !s110 1572060856 +!i10b 1 +!s100 7;7EOV3``ei]nDZMQlPGk0 +I@SFf;nk4B=?86`VOB^@0O0 +R2 +!s105 VX_front_end_v_unit +S1 +R3 +R9 +8/nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v +F/nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v +L0 3 +R5 +r1 +!s85 0 +31 +Z19 !s108 1572060856.000000 +!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v| +!i113 0 +R7 +R8 +n@v@x_front_end +vVX_generic_priority_encoder +R0 +R18 +!i10b 1 +!s100 :aK28Kh=@lT9ZCaTamzg>3 +IMZRCchbF_@P0IooMfHhlR3 +R2 +!s105 VX_generic_priority_encoder_v_unit +S1 +R3 +R9 +8/nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v +F/nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v +L0 1 +R5 +r1 +!s85 0 +31 +R19 +!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v| +!i113 0 +R7 +R8 +n@v@x_generic_priority_encoder +vVX_generic_register +R0 +R18 +!i10b 1 +!s100 fL2^LczAkWP@cTbY69kFO3 +I@OIJ[h;oQlY1Z]md:O]Ce0 +R2 +!s105 VX_gpr_wspawn_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v +L0 7 +R5 +r1 +!s85 0 +31 +R23 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v| +!i113 0 +R7 +R8 +n@v@x_gpr_wspawn_inter +YVX_gpu_inst_req_inter +R0 +R22 +!i10b 1 +!s100 jcVnabg7Ze4Un5[R73S4^3 +IjoUY9Bcc6eGJkkOZN11l21 +R2 +!s105 VX_gpu_inst_req_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v +L0 7 +R5 +r1 +!s85 0 +31 +R23 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v| +!i113 0 +R7 +R8 +n@v@x_gpu_inst_req_inter +YVX_icache_request_inter +R0 +R22 +!i10b 1 +!s100 0hM8K@;[W3:=Oz64H8G_31 +IaObkPk42UFP9UNAH78DbT1 +R2 +!s105 VX_icache_request_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +R23 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v| +!i113 0 +R7 +R8 +n@v@x_icache_request_inter +YVX_icache_response_inter +R0 +Z24 !s110 1572060867 +!i10b 1 +!s100 EB8b2:S0:KXlokE5O?dK70 +IVc;fhnJfHN`bdcOCabTaL2 +R2 +!s105 VX_icache_response_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +Z25 !s108 1572060867.000000 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v| +!i113 0 +R7 +R8 +n@v@x_icache_response_inter +YVX_inst_exec_wb_inter +R0 +R24 +!i10b 1 +!s100 nOge=]_K`4;kMhR7eddR60 +I=THghFo4g^GNl149SNfhR0 +R2 +!s105 VX_inst_exec_wb_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +R25 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v| +!i113 0 +R7 +R8 +n@v@x_inst_exec_wb_inter +YVX_inst_mem_wb_inter +R0 +R24 +!i10b 1 +!s100 8:P3XhBMD@mALW[^O64lH0 +IeJ;ki1@RDNUj1 +R2 +!s105 VX_inst_mem_wb_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +R25 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v| +!i113 0 +R7 +R8 +n@v@x_inst_mem_wb_inter +YVX_inst_meta_inter +R0 +R24 +!i10b 1 +!s100 dUY[BFW==7aoDdYzOfX4T0 +I_jRGl<^:B27il66X2?N?M2 +R2 +!s105 VX_inst_meta_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v +L0 7 +R5 +r1 +!s85 0 +31 +R25 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v| +!i113 0 +R7 +R8 +n@v@x_inst_meta_inter +YVX_jal_response_inter +R0 +Z26 !s110 1572060868 +!i10b 1 +!s100 a2a9H52CnaVl9oW5Ta^3L1 +Im?4OnRiS;gYggKBh2NDQM0 +R2 +!s105 VX_jal_response_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +Z27 !s108 1572060868.000000 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v| +!i113 0 +R7 +R8 +n@v@x_jal_response_inter +YVX_join_inter +R0 +R26 +!i10b 1 +!s100 nCBXlS2G:6=Q[XaVm;MOX2 +INlTJiDP]L4?d^[:lobD6Be0CP2 +I`l^EVY@lSGhGG6g9@;0 +R2 +!s105 VX_lsu_req_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +R27 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v| +!i113 0 +R7 +R8 +n@v@x_lsu_req_inter +YVX_mem_req_inter +R0 +R26 +!i10b 1 +!s100 FO>D61ZR=8=Q2 +R2 +!s105 VX_mem_req_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v +L0 7 +R5 +r1 +!s85 0 +31 +R27 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v| +!i113 0 +R7 +R8 +n@v@x_mem_req_inter +YVX_mw_wb_inter +R0 +Z28 !s110 1572060869 +!i10b 1 +!s100 [0[Le^MnRRZA8ZL;OHdo3z8B05JoaadD_3 +R2 +!s105 VX_wstall_inter_v_unit +S1 +R3 +R4 +8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v +F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v +L0 8 +R5 +r1 +!s85 0 +31 +R29 +!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v| +!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v| +!i113 0 +R7 +R8 +n@v@x_wstall_inter diff --git a/old_rtl/modelsim/work/_lib.qdb b/old_rtl/modelsim/work/_lib.qdb new file mode 100644 index 0000000000000000000000000000000000000000..4c2a9642259d8e73c964b52e3ad1ff0b5ef8a80e GIT binary patch literal 49152 zcmeI5d2AfleaCmmA!U&@&%JkN-clk(F7KP7NQ#HFqNrOUDNzTtn%NzZl$M9~Eh*7O z3aD_A!wHPYK!Q3+5!cOus7Vm1P8>wCm7{6mq6u81t<$ECjkGReAU*6hkc$BBZ+r&3^_YL9bSxTF+MjRh^jMzwty{Q69n5(AYilEuEF2+ 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initialization +$(PROJECT_FILES): + /tools/reconfig/intel/18.0/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc + +syn.chg: + $(STAMP) syn.chg + +fit.chg: + $(STAMP) fit.chg + +sta.chg: + $(STAMP) sta.chg + +asm.chg: + $(STAMP) asm.chg + +program: $(PROJECT).sof + quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" + +clean: + rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox diff --git a/old_rtl/quartus/VX_gpr_syn.qpf b/old_rtl/quartus/VX_gpr_syn.qpf new file mode 100644 index 00000000..8938d2a9 --- /dev/null +++ b/old_rtl/quartus/VX_gpr_syn.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition +# Date created = 00:18:19 September 11, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.0" +DATE = "00:18:19 September 11, 2019" + +# Revisions + +PROJECT_REVISION = "VX_gpr_syn" diff --git a/old_rtl/quartus/VX_gpr_syn.qsf b/old_rtl/quartus/VX_gpr_syn.qsf new file mode 100644 index 00000000..26b4649b --- /dev/null +++ b/old_rtl/quartus/VX_gpr_syn.qsf @@ -0,0 +1,63 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:18:19 SEPTEMBER 11, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition" +set_global_assignment -name FAMILY "Arria 10" +set_global_assignment -name DEVICE 10AX115N4F45I3SG +set_global_assignment -name TOP_LEVEL_ENTITY VX_gpr_syn +set_global_assignment -name SEARCH_PATH ../ +set_global_assignment -name VERILOG_FILE ../VX_define.v +set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v +set_global_assignment -name VERILOG_FILE ../VX_alu.v +set_global_assignment -name VERILOG_FILE ../VX_back_end.v +set_global_assignment -name VERILOG_FILE ../VX_context.v +set_global_assignment -name VERILOG_FILE ../VX_context_slave.v +set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v +set_global_assignment -name VERILOG_FILE ../VX_decode.v +set_global_assignment -name VERILOG_FILE ../VX_execute.v +set_global_assignment -name VERILOG_FILE ../VX_fetch.v +set_global_assignment -name VERILOG_FILE ../VX_forwarding.v +set_global_assignment -name VERILOG_FILE ../VX_front_end.v +set_global_assignment -name VERILOG_FILE ../VX_generic_register.v +set_global_assignment -name VERILOG_FILE ../VX_gpr.v +set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v +set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v +set_global_assignment -name VERILOG_FILE ../VX_memory.v +set_global_assignment -name VERILOG_FILE ../VX_register_file.v +set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v +set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v +set_global_assignment -name VERILOG_FILE ../VX_warp.v +set_global_assignment -name VERILOG_FILE ../VX_writeback.v +set_global_assignment -name VERILOG_FILE ../Vortex.v +set_global_assignment -name SDC_FILE vortex.sdc +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL diff --git a/old_rtl/quartus/asm.chg b/old_rtl/quartus/asm.chg new file mode 100644 index 00000000..19f86f49 --- /dev/null +++ b/old_rtl/quartus/asm.chg @@ -0,0 +1 @@ +done diff --git a/old_rtl/quartus/fit.chg b/old_rtl/quartus/fit.chg new file mode 100644 index 00000000..19f86f49 --- /dev/null +++ b/old_rtl/quartus/fit.chg @@ -0,0 +1 @@ +done diff --git a/old_rtl/quartus/map.chg b/old_rtl/quartus/map.chg new file mode 100644 index 00000000..d155914e --- /dev/null +++ b/old_rtl/quartus/map.chg @@ -0,0 +1 @@ +Wed Sep 11 00:18:22 2019 diff --git a/old_rtl/quartus/project.tcl b/old_rtl/quartus/project.tcl new file mode 100644 index 00000000..49e1d8ac --- /dev/null +++ b/old_rtl/quartus/project.tcl @@ -0,0 +1,88 @@ +package require cmdline + +set options { \ + { "project.arg" "" "Project name" } \ + { "family.arg" "" "Device family name" } \ + { "device.arg" "" "Device name" } \ + { "top.arg" "" "Top level module" } \ + { "sdc.arg" "" "Timing Design Constraints file" } \ + { "src.arg" "" "Verilog source file" } \ +} + +array set opts [::cmdline::getoptions quartus(args) $options] + +project_new $opts(project) -overwrite + +set_global_assignment -name FAMILY $opts(family) +set_global_assignment -name DEVICE $opts(device) +set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) + +set_global_assignment -name SEARCH_PATH ../ + +set_global_assignment -name VERILOG_FILE ../VX_define.v + +set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v + +set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v + +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v + +set_global_assignment -name VERILOG_FILE ../VX_alu.v +set_global_assignment -name VERILOG_FILE ../VX_back_end.v +set_global_assignment -name VERILOG_FILE ../VX_context.v +set_global_assignment -name VERILOG_FILE ../VX_context_slave.v +set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v +set_global_assignment -name VERILOG_FILE ../VX_decode.v +set_global_assignment -name VERILOG_FILE ../VX_define.v +set_global_assignment -name VERILOG_FILE ../VX_execute.v +set_global_assignment -name VERILOG_FILE ../VX_fetch.v +set_global_assignment -name VERILOG_FILE ../VX_forwarding.v +set_global_assignment -name VERILOG_FILE ../VX_front_end.v +set_global_assignment -name VERILOG_FILE ../VX_generic_register.v +set_global_assignment -name VERILOG_FILE ../VX_gpr.v +set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v +set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v +set_global_assignment -name VERILOG_FILE ../VX_memory.v +set_global_assignment -name VERILOG_FILE ../VX_register_file.v +set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v +set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v +set_global_assignment -name VERILOG_FILE ../VX_warp.v +set_global_assignment -name VERILOG_FILE ../VX_writeback.v +set_global_assignment -name VERILOG_FILE ../Vortex.v + +set_global_assignment -name SDC_FILE vortex.sdc +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL + +project_close + +# set_global_assignment -name VERILOG_FILE $opts(src) + diff --git a/old_rtl/quartus/smart.log b/old_rtl/quartus/smart.log new file mode 100644 index 00000000..540778b5 --- /dev/null +++ b/old_rtl/quartus/smart.log @@ -0,0 +1,27 @@ +Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support. +Info: ******************************************************************* +Info: Running Quartus Prime Shell + Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition + Info: Copyright (C) 2018 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel FPGA IP License Agreement, or other applicable license + Info: agreement, including, without limitation, that your use is for + Info: the sole purpose of programming logic devices manufactured by + Info: Intel and sold by Intel or its authorized distributors. Please + Info: refer to the applicable agreement for further details. + Info: Processing started: Wed Sep 11 00:18:22 2019 +Info: Command: quartus_sh --determine_smart_action VX_gpr_syn +Info: Quartus(args): VX_gpr_syn +Info: SMART_ACTION = SOURCE +Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 687 megabytes + Info: Processing ended: Wed Sep 11 00:18:22 2019 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 diff --git a/old_rtl/quartus/sta.chg b/old_rtl/quartus/sta.chg new file mode 100644 index 00000000..19f86f49 --- /dev/null +++ b/old_rtl/quartus/sta.chg @@ -0,0 +1 @@ +done diff --git a/old_rtl/quartus/syn.chg b/old_rtl/quartus/syn.chg new file mode 100644 index 00000000..19f86f49 --- /dev/null +++ b/old_rtl/quartus/syn.chg @@ -0,0 +1 @@ +done diff --git a/old_rtl/quartus/vortex.ini b/old_rtl/quartus/vortex.ini new file mode 100644 index 00000000..e2fb4516 --- /dev/null +++ b/old_rtl/quartus/vortex.ini @@ -0,0 +1,40 @@ +load_package flow + + +set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v +set_global_assignment -name VERILOG_FILE ../VX_gpr.v +set_global_assignment -name SDC_FILE vortex.sdc +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL + +# pins configuration +package require cmdline + +proc make_all_pins_virtual { args } { + + set options {\ + { "exclude.arg" "" "List of signals to exclude" } \ + } + array set opts [::cmdline::getoptions quartus(args) $options] + + remove_all_instance_assignments -name VIRTUAL_PIN + execute_module -tool map + set name_ids [get_names -filter * -node_type pin] + + foreach_in_collection name_id $name_ids { + set pin_name [get_name_info -info full_path $name_id] + + if { -1 == [lsearch -exact $opts(excludes) $pin_name] } { + post_message "Making VIRTUAL_PIN assignment to $pin_name" + set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON + } else { + post_message "Skipping VIRTUAL_PIN assignment to $pin_name" + } + } + export_assignments +} + + +make_all_pins_virtual -exclude { clk, reset } \ No newline at end of file diff --git a/old_rtl/quartus/vortex.sdc b/old_rtl/quartus/vortex.sdc new file mode 100644 index 00000000..eafe4ff7 --- /dev/null +++ b/old_rtl/quartus/vortex.sdc @@ -0,0 +1 @@ +create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] diff --git a/old_rtl/results.txt b/old_rtl/results.txt new file mode 100644 index 00000000..083332ec --- /dev/null +++ b/old_rtl/results.txt @@ -0,0 +1,7 @@ +# Dynamic Instructions: 51711 +# of total cycles: 51728 +# of forwarding stalls: 0 +# of branch stalls: 0 +# CPI: 1.00033 +# time to simulate: 0 milliseconds +# GRADE: Failed on test: 4294967295 diff --git a/old_rtl/shared_memory/VX_bank_valids.v b/old_rtl/shared_memory/VX_bank_valids.v new file mode 100644 index 00000000..3b1e63ab --- /dev/null +++ b/old_rtl/shared_memory/VX_bank_valids.v @@ -0,0 +1,36 @@ +`include "../VX_define.v" + +// Converts in_valids to bank_valids +module VX_bank_valids + #( + parameter NB = 4, + parameter BITS_PER_BANK = 3 + ) + ( + input wire[`NT_M1:0] in_valids, + input wire[`NT_M1:0][31:0] in_addr, + output reg[NB:0][`NT_M1:0] bank_valids + ); + + + integer i, j; + always@(*) begin + for(j = 0; j <= NB; j = j+1 ) begin + for(i = 0; i <= `NT_M1; i = i+1) begin + if(in_valids[i]) begin + if(in_addr[i][(2+BITS_PER_BANK-1):2] == j[BITS_PER_BANK-1:0]) begin + bank_valids[j][i] = 1'b1; + end + else begin + bank_valids[j][i] = 1'b0; + end + + end + else begin + bank_valids[j][i] = 1'b0; + end + end + end + end + +endmodule \ No newline at end of file diff --git a/old_rtl/shared_memory/VX_priority_encoder_sm.v b/old_rtl/shared_memory/VX_priority_encoder_sm.v new file mode 100644 index 00000000..ba571fd3 --- /dev/null +++ b/old_rtl/shared_memory/VX_priority_encoder_sm.v @@ -0,0 +1,115 @@ +`include "../VX_define.v" + +module VX_priority_encoder_sm + #( + parameter NB = 4, + parameter BITS_PER_BANK = 3, + parameter NUM_REQ = 3 + ) + ( + //INPUTS + input wire clk, + input wire reset, + input wire[`NT_M1:0] in_valid, + input wire[`NT_M1:0][31:0] in_address, + input wire[`NT_M1:0][31:0] in_data, + // OUTPUTS + // To SM Module + output reg[NB:0] out_valid, + output reg[NB:0][31:0] out_address, + output reg[NB:0][31:0] out_data, + + // To Processor + output wire[NB:0][`CLOG2(NUM_REQ) - 1:0] req_num, + output reg stall, + output wire send_data // Finished all of the requests +); + + reg[`NT_M1:0] left_requests; + reg[`NT_M1:0] serviced; + + + wire[`NT_M1:0] use_valid; + + + wire requests_left = (|left_requests); + + assign use_valid = (requests_left) ? left_requests : in_valid; + + + wire[NB:0][`NT_M1:0] bank_valids; + VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid( + .in_valids(use_valid), + .in_addr(in_address), + .bank_valids(bank_valids) + ); + + wire[NB:0] more_than_one_valid; + + genvar curr_bank; + generate + for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1) + begin + wire[`CLOG2(`NT):0] num_valids; + + VX_countones #(.N(`NT)) valids_counter ( + .valids(bank_valids[curr_bank]), + .count (num_valids) + ); + assign more_than_one_valid[curr_bank] = num_valids > 1; + // assign more_than_one_valid[curr_bank] = $countones(bank_valids[curr_bank]) > 1; + end + endgenerate + + + assign stall = (|more_than_one_valid); + assign send_data = (!stall) && (|in_valid); // change + + wire[NB:0][(`CLOG2(NUM_REQ)) - 1:0] internal_req_num; + wire[NB:0] internal_out_valid; + + + // There's one or less valid per bank + genvar curr_bank_o; + for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1) + begin + + VX_generic_priority_encoder #(.N(NUM_REQ)) vx_priority_encoder( + .valids(bank_valids[curr_bank_o]), + .index(internal_req_num[curr_bank_o]), + .found(internal_out_valid[curr_bank_o]) + ); + assign out_address[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_address[internal_req_num[curr_bank_o]] : 0; + assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0; + end + + integer curr_b; + always @(*) begin + serviced = 0; + for (curr_b = 0; curr_b <= NB; curr_b=curr_b+1) begin + serviced[internal_req_num[curr_b]] = 1; + end + end + + + assign req_num = internal_req_num; + assign out_valid = internal_out_valid; + + + wire[`NT_M1:0] serviced_qual = in_valid & (serviced); + + wire[`NT_M1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual); + + // wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual); + + always @(posedge clk, posedge reset) begin + if (reset) begin + left_requests <= 0; + // serviced = 0; + end else begin + if (!stall) left_requests <= 0; + else left_requests <= new_left_requests; + end + end + +endmodule \ No newline at end of file diff --git a/old_rtl/shared_memory/VX_shared_memory.v b/old_rtl/shared_memory/VX_shared_memory.v new file mode 100644 index 00000000..bd9cce36 --- /dev/null +++ b/old_rtl/shared_memory/VX_shared_memory.v @@ -0,0 +1,178 @@ +`include "../VX_define.v" + +module VX_shared_memory + #( + parameter SM_SIZE = 4096, // Bytes + parameter SM_BANKS = 4, + parameter SM_BYTES_PER_READ = 16, + parameter SM_WORDS_PER_READ = 4, + parameter SM_LOG_WORDS_PER_READ = 2, + parameter SM_HEIGHT = 128, // Bytes + parameter SM_BANK_OFFSET_START = 2, + parameter SM_BANK_OFFSET_END = 4, + parameter SM_BLOCK_OFFSET_START = 5, + parameter SM_BLOCK_OFFSET_END = 6, + parameter SM_INDEX_START = 7, + parameter SM_INDEX_END = 13, + parameter NUM_REQ = 4, + parameter BITS_PER_BANK = 3 + ) + ( + //INPUTS + input wire clk, + input wire reset, + input wire[`NT_M1:0] in_valid, + input wire[`NT_M1:0][31:0] in_address, + input wire[`NT_M1:0][31:0] in_data, + input wire[2:0] mem_read, + input wire[2:0] mem_write, + //OUTPUTS + output wire[`NT_M1:0] out_valid, + output wire[`NT_M1:0][31:0] out_data, + output wire stall + ); + +//reg[NB:0][31:0] temp_address; +//reg[NB:0][31:0] temp_in_data; +//reg[NB:0] temp_in_valid; +reg[SM_BANKS - 1:0][31:0] temp_address; +reg[SM_BANKS - 1:0][31:0] temp_in_data; +reg[SM_BANKS - 1:0] temp_in_valid; + +reg[`NT_M1:0] temp_out_valid; +reg[`NT_M1:0][31:0] temp_out_data; + +//reg [NB:0][6:0] block_addr; +//reg [NB:0][3:0][31:0] block_wdata; +//reg [NB:0][3:0][31:0] block_rdata; +//reg [NB:0][1:0] block_we; +reg [SM_BANKS - 1:0][$clog2(SM_HEIGHT) - 1:0] block_addr; +reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_wdata; +reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_rdata; +reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ-1:0] block_we; + +wire send_data; + +//reg[NB:0][1:0] req_num; +reg[SM_BANKS - 1:0][`CLOG2(NUM_REQ) - 1:0] req_num; // not positive about this + +wire [`NT_M1:0] orig_in_valid; + + +genvar f; + generate + for(f = 0; f < `NT; f = f+1) begin + assign orig_in_valid[f] = in_valid[f]; + end + + assign out_valid = send_data ? temp_out_valid : 0; + assign out_data = send_data ? temp_out_data : 0; + endgenerate + + +//VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm( +VX_priority_encoder_sm #(.NB(SM_BANKS - 1), .BITS_PER_BANK(BITS_PER_BANK), .NUM_REQ(NUM_REQ)) vx_priority_encoder_sm( + .clk(clk), + .reset(reset), + .in_valid(orig_in_valid), + .in_address(in_address), + .in_data(in_data), + + .out_valid(temp_in_valid), + .out_address(temp_address), + .out_data(temp_in_data), + + .req_num(req_num), + .stall(stall), + .send_data(send_data) + ); + + +genvar j; +integer i; +generate +//for(j=0; j<= NB; j=j+1) begin : sm_mem_block +for(j=0; j<= SM_BANKS - 1; j=j+1) begin + + wire shm_write = (mem_write != `NO_MEM_WRITE) && temp_in_valid[j]; + + VX_shared_memory_block# + ( + .SMB_HEIGHT(SM_HEIGHT), + .SMB_WORDS_PER_READ(SM_WORDS_PER_READ), + .SMB_LOG_WORDS_PER_READ(SM_LOG_WORDS_PER_READ) + ) vx_shared_memory_block + ( + .clk (clk), + .reset (reset), + .addr (block_addr[j]), + .wdata (block_wdata[j]), + .we (block_we[j]), + .shm_write(shm_write), + .data_out (block_rdata[j]) + ); +end + + +always @(*) begin + block_addr = 0; + block_we = 0; + block_wdata = 0; + //for(i = 0; i <= NB; i = i+1) begin + for(i = 0; i <= SM_BANKS - 1; i = i+1) begin + if(temp_in_valid[i] == 1'b1) begin + //1. Check if the request is actually to the shared memory + if((temp_address[i][31:24]) == 8'hFF) begin + // STORES + if(mem_write != `NO_MEM_WRITE) begin + if(mem_write == `SB_MEM_WRITE) begin + //TODO + end + else if(mem_write == `SH_MEM_WRITE) begin + //TODO + end + else if(mem_write == `SW_MEM_WRITE) begin + //block_addr[i] = temp_address[i][13:7]; + //block_we[i] = temp_address[i][6:5]; + //block_wdata[i][temp_address[i][6:5]] = temp_in_data[i]; + block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START]; + block_we[i] = temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]; + block_wdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]] = temp_in_data[i]; + end + end + //LOADS + else if(mem_read != `NO_MEM_READ) begin + if(mem_read == `LB_MEM_READ) begin + //TODO + end + else if (mem_read == `LH_MEM_READ) + begin + //TODO + end + else if (mem_read == `LW_MEM_READ) + begin + //block_addr[i] = temp_address[i][13:7]; + //temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][6:5]]; + //temp_out_valid[req_num[i]] = 1'b1; + block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START]; + temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]]; + temp_out_valid[req_num[i]] = 1'b1; + end + else if (mem_read == `LBU_MEM_READ) + begin + //TODO + end + else if (mem_read == `LHU_MEM_READ) + begin + //TODO + end + end + end + end + end +end + +endgenerate + + +endmodule diff --git a/old_rtl/shared_memory/VX_shared_memory_block.v b/old_rtl/shared_memory/VX_shared_memory_block.v new file mode 100644 index 00000000..9a37b6fe --- /dev/null +++ b/old_rtl/shared_memory/VX_shared_memory_block.v @@ -0,0 +1,115 @@ +module VX_shared_memory_block +#( + parameter SMB_SIZE = 4096, // Bytes + parameter SMB_BYTES_PER_READ = 16, + parameter SMB_WORDS_PER_READ = 4, + parameter SMB_LOG_WORDS_PER_READ = 2, + parameter SMB_HEIGHT = 128, // Bytes + parameter BITS_PER_BANK = 3 +) +( + input wire clk, // Clock + input wire reset, + //input wire[6:0] addr, + //input wire[3:0][31:0] wdata, + //input wire[1:0] we, + //input wire shm_write, + + //output wire[3:0][31:0] data_out + input wire[$clog2(SMB_HEIGHT) - 1:0] addr, + input wire[SMB_WORDS_PER_READ-1:0][31:0] wdata, + input wire[SMB_LOG_WORDS_PER_READ-1:0] we, + input wire shm_write, + + output wire[SMB_WORDS_PER_READ-1:0][31:0] data_out + +); + + + `ifndef SYN + + //reg[3:0][31:0] shared_memory[127:0]; + reg[SMB_WORDS_PER_READ-1:0][31:0] shared_memory[SMB_HEIGHT-1:0]; + + //wire need_to_write = (|we); + integer curr_ind; + always @(posedge clk, posedge reset) begin + if (reset) begin + //for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1) + for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1) + begin + shared_memory[curr_ind] = 0; + end + end else if(shm_write) begin + shared_memory[addr][we][31:0] = wdata[we][31:0]; // - Ethan's addition + //if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0]; + //if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0]; + //if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0]; + //if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0]; + end + end + + + assign data_out = shm_write ? 0 : shared_memory[addr]; + + `else + + wire cena = 0; + wire cenb = !shm_write; + + wire[3:0][31:0] write_bit_mask; + + //assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}}; + //assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}}; + //assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}}; + //assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}}; + genvar curr_word; + for (curr_word = 0; curr_word < SMB_WORDS_PER_READ; curr_word = curr_word + 1) + begin + assign write_bit_mask[curr_word] = (we == curr_word) ? 1 : {32{1'b0}}; + end + + // Using ASIC MEM + /* verilator lint_off PINCONNECTEMPTY */ + rf2_128x128_wm1 first_ram ( + .CENYA(), + .AYA(), + .CENYB(), + .WENYB(), + .AYB(), + .QA(data_out), + .SOA(), + .SOB(), + .CLKA(clk), + .CENA(cena), + .AA(addr), + .CLKB(clk), + .CENB(cenb), + .WENB(write_bit_mask), + .AB(addr), + .DB(wdata), + .EMAA(3'b011), + .EMASA(1'b0), + .EMAB(3'b011), + .TENA(1'b1), + .TCENA(1'b0), + .TAA(7'b0), + .TENB(1'b1), + .TCENB(1'b0), + .TWENB(128'b0), + .TAB(7'b0), + .TDB(128'b0), + .RET1N(1'b1), + .SIA(2'b0), + .SEA(1'b0), + .DFTRAMBYP(1'b0), + .SIB(2'b0), + .SEB(1'b0), + .COLLDISN(1'b1) + ); + /* verilator lint_on PINCONNECTEMPTY */ + + + `endif + +endmodule diff --git a/old_rtl/simulate/VX_define.h b/old_rtl/simulate/VX_define.h new file mode 100644 index 00000000..ed10c77f --- /dev/null +++ b/old_rtl/simulate/VX_define.h @@ -0,0 +1,100 @@ +#define NT 4 +#define NT_M1 (NT-1) + +#define NW 8 + +#define CACHE_NUM_BANKS 8 +#define CACHE_WORDS_PER_BLOCK 4 + +#define R_INST 51 +#define L_INST 3 +#define ALU_INST 19 +#define S_INST 35 +#define B_INST 99 +#define LUI_INST 55 +#define AUIPC_INST 23 +#define JAL_INST 111 +#define JALR_INST 103 +#define SYS_INST 115 + + +#define WB_ALU 1 +#define WB_MEM 2 +#define WB_JAL 3 +#define NO_WB 0 + + +#define RS2_IMMED 1 +#define RS2_REG 0 + + +#define NO_MEM_READ 7 +#define LB_MEM_READ 0 +#define LH_MEM_READ 1 +#define LW_MEM_READ 2 +#define LBU_MEM_READ 4 +#define LHU_MEM_READ 5 + + +#define NO_MEM_WRITE 7 +#define SB_MEM_WRITE 0 +#define SH_MEM_WRITE 1 +#define SW_MEM_WRITE 2 + + +#define NO_BRANCH 0 +#define BEQ 1 +#define BNE 2 +#define BLT 3 +#define BGT 4 +#define BLTU 5 +#define BGTU 6 + + +#define NO_ALU 15 +#define ADD 0 +#define SUB 1 +#define SLLA 2 +#define SLT 3 +#define SLTU 4 +#define XOR 5 +#define SRL 6 +#define SRA 7 +#define OR 8 +#define AND 9 +#define SUBU 10 +#define LUI_ALU 11 +#define AUIPC_ALU 12 +#define CSR_ALU_RW 13 +#define CSR_ALU_RS 14 +#define CSR_ALU_RC 15 + + + +// WRITEBACK +#define WB_ALU 1 +#define WB_MEM 2 +#define WB_JAL 3 +#define NO_WB 0 + + +// JAL +#define JUMP 1 +#define NO_JUMP 0 + +// STALLS +#define STALL 1 +#define NO_STALL 0 + + +#define TAKEN 1 +#define NOT_TAKEN 0 + + +#define ZERO_REG 0 + + +// COLORS +#define GREEN "\033[32m" +#define RED "\033[31m" +#define DEFAULT "\033[39m" diff --git a/old_rtl/simulate/ram.h b/old_rtl/simulate/ram.h new file mode 100644 index 00000000..13f78e94 --- /dev/null +++ b/old_rtl/simulate/ram.h @@ -0,0 +1,245 @@ +#ifndef __RAM__ + +#define __RAM__ + +// #include "string.h" +#include +#include +// #include + +// #define NULL 0 + +class RAM; + +uint32_t hti(char); +uint32_t hToI(char *, uint32_t); +void loadHexImpl(char *,RAM*); + +class RAM{ +public: + uint8_t* mem[1 << 12]; + + RAM(){ + for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL; + } + ~RAM(){ + for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i]; + } + + void clear(){ + for(uint32_t i = 0;i < (1 << 12);i++) + { + if(mem[i]) + { + delete mem[i]; + mem[i] = NULL; + } + } + } + + uint8_t* get(uint32_t address){ + + if(mem[address >> 20] == NULL) { + uint8_t* ptr = new uint8_t[1024*1024]; + for(uint32_t i = 0;i < 1024*1024;i+=4) { + ptr[i + 0] = 0x00; + ptr[i + 1] = 0x00; + ptr[i + 2] = 0x00; + ptr[i + 3] = 0x00; + } + mem[address >> 20] = ptr; + } + return &mem[address >> 20][address & 0xFFFFF]; + } + + void read(uint32_t address,uint32_t length, uint8_t *data){ + for(unsigned i = 0;i < length;i++){ + data[i] = (*this)[address + i]; + } + } + + void write(uint32_t address,uint32_t length, uint8_t *data){ + for(unsigned i = 0;i < length;i++){ + (*this)[address + i] = data[i]; + } + } + + void getBlock(uint32_t address, uint8_t *data) + { + uint32_t block_number = address & 0xffffff00; // To zero out block offset + uint32_t bytes_num = 256; + + this->read(block_number, bytes_num, data); + } + + void getWord(uint32_t address, uint32_t * data) + { + data[0] = 0; + + uint8_t first = *get(address + 0); + uint8_t second = *get(address + 1); + uint8_t third = *get(address + 2); + uint8_t fourth = *get(address + 3); + + // uint8_t hi = (uint8_t) *get(address + 0); + // std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n"; + // hi = (uint8_t) *get(address + 1); + // std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n"; + // hi = (uint8_t) *get(address + 2); + // std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n"; + // hi = (uint8_t) *get(address + 3); + // std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n"; + + data[0] = (data[0] << 0) | fourth; + data[0] = (data[0] << 8) | third; + data[0] = (data[0] << 8) | second; + data[0] = (data[0] << 8) | first; + + } + + void writeWord(uint32_t address, uint32_t * data) + { + uint32_t data_to_write = *data; + + uint32_t byte_mask = 0xFF; + + for (int i = 0; i < 4; i++) + { + // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n"; + // std::cout << "RAM: DATA TO MASK " << byte_mask << "\n"; + // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n"; + (*this)[address + i] = data_to_write & byte_mask; + data_to_write = data_to_write >> 8; + } + } + + void writeHalf(uint32_t address, uint32_t * data) + { + uint32_t data_to_write = *data; + + uint32_t byte_mask = 0xFF; + + for (int i = 0; i < 2; i++) + { + // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n"; + // std::cout << "RAM: DATA TO MASK " << byte_mask << "\n"; + // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n"; + (*this)[address + i] = data_to_write & byte_mask; + data_to_write = data_to_write >> 8; + } + } + + void writeByte(uint32_t address, uint32_t * data) + { + uint32_t data_to_write = *data; + + uint32_t byte_mask = 0xFF; + + (*this)[address] = data_to_write & byte_mask; + data_to_write = data_to_write >> 8; + + } + + uint8_t& operator [](uint32_t address) { + return *get(address); + } + +}; + + +// MEMORY UTILS + +uint32_t hti(char c) { + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return c - '0'; +} + +uint32_t hToI(char *c, uint32_t size) { + uint32_t value = 0; + for (uint32_t i = 0; i < size; i++) { + value += hti(c[i]) << ((size - i - 1) * 4); + } + return value; +} + + + +void loadHexImpl(const char *path, RAM* mem) { + mem->clear(); + FILE *fp = fopen(path, "r"); + if(fp == 0){ + printf("Path not found %s\n", path); + return; + // std::cout << path << " not found" << std::endl; + } + //Preload 0x0 <-> 0x80000000 jumps + ((uint32_t*)mem->get(0))[1] = 0xf1401073; + + ((uint32_t*)mem->get(0))[2] = 0x30101073; + + ((uint32_t*)mem->get(0))[3] = 0x800000b7; + ((uint32_t*)mem->get(0))[4] = 0x000080e7; + + ((uint32_t*)mem->get(0x80000000))[0] = 0x00000097; + + ((uint32_t*)mem->get(0xb0000000))[0] = 0x01C02023; + // F00FFF10 + ((uint32_t*)mem->get(0xf00fff10))[0] = 0x12345678; + + + + + fseek(fp, 0, SEEK_END); + uint32_t size = ftell(fp); + fseek(fp, 0, SEEK_SET); + char* content = new char[size]; + fread(content, 1, size, fp); + + int offset = 0; + char* line = content; + // std::cout << "WHTA\n"; + while (1) { + if (line[0] == ':') { + uint32_t byteCount = hToI(line + 1, 2); + uint32_t nextAddr = hToI(line + 3, 4) + offset; + uint32_t key = hToI(line + 7, 2); + switch (key) { + case 0: + for (uint32_t i = 0; i < byteCount; i++) { + + unsigned add = nextAddr + i; + + *(mem->get(add)) = hToI(line + 9 + i * 2, 2); + } + break; + case 2: +// cout << offset << endl; + offset = hToI(line + 9, 4) << 4; + break; + case 4: +// cout << offset << endl; + offset = hToI(line + 9, 4) << 16; + break; + default: +// cout << "??? " << key << endl; + break; + } + } + + while (*line != '\n' && size != 0) { + line++; + size--; + } + if (size <= 1) + break; + line++; + size--; + } + + if (content) delete[] content; +} + +#endif \ No newline at end of file diff --git a/rtl/simulate/tb_debug.h b/old_rtl/simulate/tb_debug.h similarity index 100% rename from rtl/simulate/tb_debug.h rename to old_rtl/simulate/tb_debug.h diff --git a/old_rtl/simulate/test_bench.cpp b/old_rtl/simulate/test_bench.cpp new file mode 100644 index 00000000..2becfb89 --- /dev/null +++ b/old_rtl/simulate/test_bench.cpp @@ -0,0 +1,105 @@ +#include "test_bench.h" + +#define NUM_TESTS 46 + +int main(int argc, char **argv) +{ + + // Verilated::debug(1); + + Verilated::commandArgs(argc, argv); + + Verilated::traceEverOn(true); + + +#define ALL_TESTS +#ifdef ALL_TESTS + bool passed = true; + std::string tests[NUM_TESTS] = { + "../../emulator/riscv_tests/rv32ui-p-add.hex", + "../../emulator/riscv_tests/rv32ui-p-addi.hex", + "../../emulator/riscv_tests/rv32ui-p-and.hex", + "../../emulator/riscv_tests/rv32ui-p-andi.hex", + "../../emulator/riscv_tests/rv32ui-p-auipc.hex", + "../../emulator/riscv_tests/rv32ui-p-beq.hex", + "../../emulator/riscv_tests/rv32ui-p-bge.hex", + "../../emulator/riscv_tests/rv32ui-p-bgeu.hex", + "../../emulator/riscv_tests/rv32ui-p-blt.hex", + "../../emulator/riscv_tests/rv32ui-p-bltu.hex", + "../../emulator/riscv_tests/rv32ui-p-bne.hex", + "../../emulator/riscv_tests/rv32ui-p-jal.hex", + "../../emulator/riscv_tests/rv32ui-p-jalr.hex", + "../../emulator/riscv_tests/rv32ui-p-lb.hex", + "../../emulator/riscv_tests/rv32ui-p-lbu.hex", + "../../emulator/riscv_tests/rv32ui-p-lh.hex", + "../../emulator/riscv_tests/rv32ui-p-lhu.hex", + "../../emulator/riscv_tests/rv32ui-p-lui.hex", + "../../emulator/riscv_tests/rv32ui-p-lw.hex", + "../../emulator/riscv_tests/rv32ui-p-or.hex", + "../../emulator/riscv_tests/rv32ui-p-ori.hex", + "../../emulator/riscv_tests/rv32ui-p-sb.hex", + "../../emulator/riscv_tests/rv32ui-p-sh.hex", + "../../emulator/riscv_tests/rv32ui-p-simple.hex", + "../../emulator/riscv_tests/rv32ui-p-sll.hex", + "../../emulator/riscv_tests/rv32ui-p-slli.hex", + "../../emulator/riscv_tests/rv32ui-p-slt.hex", + "../../emulator/riscv_tests/rv32ui-p-slti.hex", + "../../emulator/riscv_tests/rv32ui-p-sltiu.hex", + "../../emulator/riscv_tests/rv32ui-p-sltu.hex", + "../../emulator/riscv_tests/rv32ui-p-sra.hex", + "../../emulator/riscv_tests/rv32ui-p-srai.hex", + "../../emulator/riscv_tests/rv32ui-p-srl.hex", + "../../emulator/riscv_tests/rv32ui-p-srli.hex", + "../../emulator/riscv_tests/rv32ui-p-sub.hex", + "../../emulator/riscv_tests/rv32ui-p-sw.hex", + "../../emulator/riscv_tests/rv32ui-p-xor.hex", + "../../emulator/riscv_tests/rv32ui-p-xori.hex", + "../../emulator/riscv_tests/rv32um-p-div.hex", + "../../emulator/riscv_tests/rv32um-p-divu.hex", + "../../emulator/riscv_tests/rv32um-p-mul.hex", + "../../emulator/riscv_tests/rv32um-p-mulh.hex", + "../../emulator/riscv_tests/rv32um-p-mulhsu.hex", + "../../emulator/riscv_tests/rv32um-p-mulhu.hex", + "../../emulator/riscv_tests/rv32um-p-rem.hex", + "../../emulator/riscv_tests/rv32um-p-remu.hex" + }; + + for (std::string s : tests) { + Vortex v; + + std::cerr << s << std::endl; + + bool curr = v.simulate(s); + if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl; + if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl; + passed = passed && curr; + } + + if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n"; + if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n"; + + return !passed; + + #else + + char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; + Vortex v; + const char *testing; + + if (argc >= 2) { + testing = argv[1]; + } else { + testing = "../../kernel/vortex_test.hex"; + } + + std::cerr << testing << std::endl; + + + bool curr = v.simulate(testing); + if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; + if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; + + return !curr; + +#endif +} diff --git a/old_rtl/simulate/test_bench.h b/old_rtl/simulate/test_bench.h new file mode 100644 index 00000000..3a001377 --- /dev/null +++ b/old_rtl/simulate/test_bench.h @@ -0,0 +1,433 @@ +// C++ libraries +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "VX_define.h" +#include "ram.h" +#include "VVortex.h" +#include "verilated.h" + +#include "tb_debug.h" + +#ifdef VCD_OUTPUT +#include +#endif + +unsigned long time_stamp = 0; + +double sc_time_stamp() +{ + return time_stamp / 1000.0; +} + +class Vortex +{ + public: + Vortex(); + ~Vortex(); + bool simulate(std::string); + private: + void ProcessFile(void); + void print_stats(bool = true); + bool ibus_driver(); + bool dbus_driver(); + void io_handler(); + + RAM ram; + + VVortex * vortex; + + unsigned start_pc; + bool refill_d; + unsigned refill_addr_d; + bool refill_i; + unsigned refill_addr_i; + long int curr_cycle; + bool stop; + bool unit_test; + std::string instruction_file_name; + std::ofstream results; + int stats_static_inst; + int stats_dynamic_inst; + int stats_total_cycles; + int stats_fwd_stalls; + int stats_branch_stalls; + int debug_state; + int ibus_state; + int dbus_state; + int debug_return; + int debug_wait_num; + int debug_inst_num; + int debug_end_wait; + int debug_debugAddr; + double stats_sim_time; + #ifdef VCD_OUTPUT + VerilatedVcdC *m_trace; + #endif +}; + + + +Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), + stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), + debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), + debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) +{ + this->vortex = new VVortex; + #ifdef VCD_OUTPUT + this->m_trace = new VerilatedVcdC; + this->vortex->trace(m_trace, 99); + this->m_trace->open("trace.vcd"); + #endif + this->results.open("../results.txt"); +} + +Vortex::~Vortex() +{ + #ifdef VCD_OUTPUT + m_trace->close(); + #endif + this->results.close(); + delete this->vortex; +} + + +void Vortex::ProcessFile(void) +{ + loadHexImpl(this->instruction_file_name.c_str(), &this->ram); +} + +void Vortex::print_stats(bool cycle_test) +{ + + if (cycle_test) + { + this->results << std::left; + // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; + this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; + this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; + this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } + else + { + this->results << std::left; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } + + + uint32_t status; + ram.getWord(0, &status); + + if (this->unit_test) + { + if (status == 1) + { + this->results << std::setw(24) << "# GRADE:" << "PASSING\n"; + } else + { + this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n"; + } + } + else + { + this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n"; + } + + this->stats_static_inst = 0; + this->stats_dynamic_inst = -1; + this->stats_total_cycles = 0; + this->stats_fwd_stalls = 0; + this->stats_branch_stalls = 0; + +} + +bool Vortex::ibus_driver() +{ + + vortex->i_m_ready_i = false; + + { + + // int dcache_num_words_per_block + + if (refill_i) + { + refill_i = false; + vortex->i_m_ready_i = true; + + for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++) + { + for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++) + { + unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank; + unsigned curr_addr = refill_addr_i + (4*curr_index); + + unsigned curr_value; + ram.getWord(curr_addr, &curr_value); + + vortex->i_m_readdata_i[curr_bank][curr_word] = curr_value; + + } + } + } + else + { + if (vortex->o_m_valid_i) + { + + if (vortex->o_m_read_or_write_i) + { + // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); + unsigned base_addr = vortex->o_m_evict_addr_i; + + for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++) + { + for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++) + { + unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank; + unsigned curr_addr = base_addr + (4*curr_index); + + unsigned curr_value = vortex->o_m_writedata_i[curr_bank][curr_word]; + + ram.writeWord( curr_addr, &curr_value); + } + } + } + + // Respond next cycle + refill_i = true; + refill_addr_i = vortex->o_m_read_addr_i; + } + } + + } + + + return false; + +} + +void Vortex::io_handler() +{ + if (vortex->io_valid) + { + uint32_t data_write = (uint32_t) vortex->io_data; + + char c = (char) data_write; + std::cerr << c; + // std::cout << c; + } +} + + +bool Vortex::dbus_driver() +{ + + vortex->i_m_ready_d = false; + + { + + // int dcache_num_words_per_block + + if (refill_d) + { + refill_d = false; + vortex->i_m_ready_d = true; + + for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++) + { + for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++) + { + unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank; + unsigned curr_addr = refill_addr_d + (4*curr_index); + + unsigned curr_value; + ram.getWord(curr_addr, &curr_value); + + vortex->i_m_readdata_d[curr_bank][curr_word] = curr_value; + + } + } + } + else + { + if (vortex->o_m_valid_d) + { + + if (vortex->o_m_read_or_write_d) + { + // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); + unsigned base_addr = vortex->o_m_evict_addr_d; + + for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++) + { + for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++) + { + unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank; + unsigned curr_addr = base_addr + (4*curr_index); + + unsigned curr_value = vortex->o_m_writedata_d[curr_bank][curr_word]; + + ram.writeWord( curr_addr, &curr_value); + } + } + } + + // Respond next cycle + refill_d = true; + refill_addr_d = vortex->o_m_read_addr_d; + } + } + + } + + + return false; +} + + + +bool Vortex::simulate(std::string file_to_simulate) +{ + + this->instruction_file_name = file_to_simulate; + // this->results << "\n****************\t" << file_to_simulate << "\t****************\n"; + + this->ProcessFile(); + + // auto start_time = std::chrono::high_resolution_clock::now(); + + + static bool stop = false; + static int counter = 0; + counter = 0; + stop = false; + + // auto start_time = clock(); + + + // vortex->reset = 1; + + + // vortex->reset = 0; + + unsigned curr_inst; + unsigned new_PC; + + // while (this->stop && (!(stop && (counter > 5)))) + // { + + // // std::cout << "************* Cycle: " << cycle << "\n"; + // bool istop = ibus_driver(); + // bool dstop = !dbus_driver(); + + // vortex->clk = 1; + // vortex->eval(); + + + + // vortex->clk = 0; + // vortex->eval(); + + + // stop = istop && dstop; + + // if (stop) + // { + // counter++; + // } else + // { + // counter = 0; + // } + + // cycle++; + // } + + bool istop; + bool dstop; + bool cont = false; + // for (int i = 0; i < 500; i++) + + vortex->reset = 1; + vortex->clk = 0; + vortex->eval(); + // m_trace->dump(10); + vortex->reset = 1; + vortex->clk = 1; + vortex->eval(); + // m_trace->dump(11); + vortex->reset = 0; + vortex->clk = 0; + + // unsigned cycles; + counter = 0; + this->stats_total_cycles = 12; + while (this->stop && ((counter < 5))) + // while (this->stats_total_cycles < 10) + { + + // printf("-------------------------\n"); + // std::cout << "Counter: " << counter << "\n"; + // if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n"; + // dstop = !dbus_driver(); + #ifdef VCD_OUTPUT + m_trace->dump(2*this->stats_total_cycles); + #endif + vortex->clk = 1; + vortex->eval(); + istop = ibus_driver(); + dstop = !dbus_driver(); + io_handler(); + + #ifdef VCD_OUTPUT + m_trace->dump((2*this->stats_total_cycles)+1); + #endif + vortex->clk = 0; + vortex->eval(); + // stop = istop && dstop; + stop = vortex->out_ebreak; + + if (stop || cont) + // if (istop) + { + cont = true; + counter++; + } else + { + counter = 0; + } + + ++time_stamp; + ++stats_total_cycles; + } + + std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; + + int status = (unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf; + + // std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n"; + + // std::cout << "Something: " << result << '\n'; + + // uint32_t status; + // ram.getWord(0, &status); + + this->print_stats(); + + + + return (status == 1); + // return (1 == 1); +} \ No newline at end of file diff --git a/rtl/simulate/Vortex.cpp b/rtl/simulate/Vortex.cpp new file mode 100644 index 00000000..80b6c964 --- /dev/null +++ b/rtl/simulate/Vortex.cpp @@ -0,0 +1,315 @@ +#include "Vortex.h" + +unsigned long time_stamp = 0; + +double sc_time_stamp() { + return time_stamp / 1000.0; +} + +Vortex::Vortex(RAM *ram) + : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), + stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), + debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), + debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) { + this->ram = ram; + this->vortex = new VVortex; +#ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + this->m_trace = new VerilatedVcdC; + this->vortex->trace(m_trace, 99); + this->m_trace->open("trace.vcd"); +#endif + this->results.open("../results.txt"); +} + +Vortex::~Vortex() { +#ifdef VCD_OUTPUT + m_trace->close(); +#endif + this->results.close(); + delete this->vortex; +} + +void Vortex::print_stats(bool cycle_test) { + if (cycle_test) { + this->results << std::left; + // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; + this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; + this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; + this->results << std::setw(24) << "# CPI:" << std::dec << (double)this->stats_total_cycles / (double)this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } else { + this->results << std::left; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } + + uint32_t status; + ram->getWord(0, &status); + + if (this->unit_test) { + if (status == 1) { + this->results << std::setw(24) << "# GRADE:" + << "PASSING\n"; + } else { + this->results << std::setw(24) << "# GRADE:" + << "Failed on test: " << status << "\n"; + } + } else { + this->results << std::setw(24) << "# GRADE:" + << "N/A [NOT A UNIT TEST]\n"; + } + + this->stats_static_inst = 0; + this->stats_dynamic_inst = -1; + this->stats_total_cycles = 0; + this->stats_fwd_stalls = 0; + this->stats_branch_stalls = 0; +} + +bool Vortex::ibus_driver() { + // Iterate through each element, and get pop index + int dequeue_index = -1; + bool dequeue_valid = false; + for (int i = 0; i < this->I_dram_req_vec.size(); i++) { + if (this->I_dram_req_vec[i].cycles_left > 0) { + this->I_dram_req_vec[i].cycles_left -= 1; + } + + if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) { + dequeue_index = i; + dequeue_valid = true; + } + } + + if (vortex->I_dram_req) { + // std::cout << "Icache Dram Request received!\n"; + if (vortex->I_dram_req_read) { + // std::cout << "Icache Dram Request is read!\n"; + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = vortex->I_dram_expected_lat; + dram_req.data_length = vortex->I_dram_req_size / 4; + dram_req.base_addr = vortex->I_dram_req_addr; + dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned)); + + for (int i = 0; i < dram_req.data_length; i++) { + unsigned curr_addr = dram_req.base_addr + (i * 4); + unsigned data_rd; + ram->getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; + this->I_dram_req_vec.push_back(dram_req); + } + + if (vortex->I_dram_req_write) { + unsigned base_addr = vortex->I_dram_req_addr; + unsigned data_length = vortex->I_dram_req_size / 4; + + for (int i = 0; i < data_length; i++) { + unsigned curr_addr = base_addr + (i * 4); + unsigned data_wr = vortex->I_dram_req_data[i]; + ram->writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex->I_dram_fill_accept && dequeue_valid) { + // std::cout << "Icache Dram Response Sending...!\n"; + + vortex->I_dram_fill_rsp = 1; + vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr; + // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; + + for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++) { + vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i]; + } + free(this->I_dram_req_vec[dequeue_index].data); + + this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index); + } else { + vortex->I_dram_fill_rsp = 0; + vortex->I_dram_fill_rsp_addr = 0; + } + + return false; +} + +void Vortex::io_handler() { + // std::cout << "Checking\n"; + if (vortex->io_valid) { + uint32_t data_write = (uint32_t)vortex->io_data; + // std::cout << "IO VALID!\n"; + char c = (char)data_write; + std::cerr << c; + // std::cout << c; + + std::cout << std::flush; + } +} + +bool Vortex::dbus_driver() { + // Iterate through each element, and get pop index + int dequeue_index = -1; + bool dequeue_valid = false; + for (int i = 0; i < this->dram_req_vec.size(); i++) { + if (this->dram_req_vec[i].cycles_left > 0) { + this->dram_req_vec[i].cycles_left -= 1; + } + + if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) { + dequeue_index = i; + dequeue_valid = true; + } + } + + if (vortex->dram_req) { + if (vortex->dram_req_read) { + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = vortex->dram_expected_lat; + dram_req.data_length = vortex->dram_req_size / 4; + dram_req.base_addr = vortex->dram_req_addr; + dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned)); + + for (int i = 0; i < dram_req.data_length; i++) { + unsigned curr_addr = dram_req.base_addr + (i * 4); + unsigned data_rd; + ram->getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; + this->dram_req_vec.push_back(dram_req); + } + + if (vortex->dram_req_write) { + unsigned base_addr = vortex->dram_req_addr; + unsigned data_length = vortex->dram_req_size / 4; + + for (int i = 0; i < data_length; i++) { + unsigned curr_addr = base_addr + (i * 4); + unsigned data_wr = vortex->dram_req_data[i]; + ram->writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex->dram_fill_accept && dequeue_valid) { + vortex->dram_fill_rsp = 1; + vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; + // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; + + for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) { + vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; + } + free(this->dram_req_vec[dequeue_index].data); + + this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index); + } else { + vortex->dram_fill_rsp = 0; + vortex->dram_fill_rsp_addr = 0; + } + + return false; +} + +void Vortex::reset() { + vortex->reset = 1; + this->step(); + vortex->reset = 0; +} + +void Vortex::step() { + vortex->clk = 0; + vortex->eval(); + +#ifdef VCD_OUTPUT + m_trace->dump(2 * this->stats_total_cycles + 0); +#endif + + vortex->clk = 1; + vortex->eval(); + + ibus_driver(); + dbus_driver(); + io_handler(); + +#ifdef VCD_OUTPUT + m_trace->dump(2 * this->stats_total_cycles + 1); +#endif + + ++time_stamp; + ++stats_total_cycles; +} + +void Vortex::wait(uint32_t cycles) { + for (int i = 0; i < cycles; ++i) { + this->step(); + } +} + +bool Vortex::is_busy() { + return (0 == vortex->out_ebreak); +} + +void Vortex::send_snoops(uint32_t mem_addr, uint32_t size) { + // align address to LLC block boundaries + auto aligned_addr_start = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES); + auto aligned_addr_end = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + size + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES); + + // submit snoop requests for the needed blocks + vortex->snp_req_addr = aligned_addr_start; + vortex->snp_req = false; + for (;;) { + this->step(); + if (vortex->snp_req) { + vortex->snp_req = false; + if (vortex->snp_req_addr >= aligned_addr_end) + break; + vortex->snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES; + } + if (!vortex->snp_req_delay) { + vortex->snp_req = true; + } + } +} + +void Vortex::flush_caches(uint32_t mem_addr, uint32_t size) { + // send snoops for L1 flush + this->send_snoops(mem_addr, size); + +#if NUMBER_CORES != 1 + // send snoops for L2 flush + this->send_snoops(mem_addr, size); +#endif + + // wait 50 cycles to ensure that the request has committed + this->wait(50); +} + +bool Vortex::simulate() { + this->wait(50); + + // reset the device + this->reset(); + + // execute program + while (!vortex->out_ebreak) { + this->step(); + } + + // wait 5 cycles to flush the pipeline + this->wait(5); + + std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; + + this->print_stats(); + + // check riscv-tests PASSED/FAILED status + int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf; + + return (status == 1); +} \ No newline at end of file diff --git a/rtl/simulate/Vortex_SOC.cpp b/rtl/simulate/Vortex_SOC.cpp new file mode 100644 index 00000000..d12c2d40 --- /dev/null +++ b/rtl/simulate/Vortex_SOC.cpp @@ -0,0 +1,248 @@ +#include "Vortex_SOC.h" + +unsigned long time_stamp = 0; + +double sc_time_stamp() { + return time_stamp / 1000.0; +} + +Vortex_SOC::Vortex_SOC(RAM *ram) + : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), + stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), + debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), + debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) { + this->ram = ram; + this->vortex = new VVortex_SOC; +#ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + this->m_trace = new VerilatedVcdC; + this->vortex->trace(m_trace, 99); + this->m_trace->open("trace.vcd"); +#endif + this->results.open("../results.txt"); +} + +Vortex_SOC::~Vortex_SOC() { +#ifdef VCD_OUTPUT + m_trace->close(); +#endif + this->results.close(); + delete this->vortex; +} + +void Vortex_SOC::print_stats(bool cycle_test) { + + if (cycle_test) { + this->results << std::left; + // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; + this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; + this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; + this->results << std::setw(24) << "# CPI:" << std::dec << (double)this->stats_total_cycles / (double)this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } else { + this->results << std::left; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } + + uint32_t status; + ram->getWord(0, &status); + + if (this->unit_test) { + if (status == 1) { + this->results << std::setw(24) << "# GRADE:" + << "PASSING\n"; + } else { + this->results << std::setw(24) << "# GRADE:" + << "Failed on test: " << status << "\n"; + } + } else { + this->results << std::setw(24) << "# GRADE:" + << "N/A [NOT A UNIT TEST]\n"; + } + + this->stats_static_inst = 0; + this->stats_dynamic_inst = -1; + this->stats_total_cycles = 0; + this->stats_fwd_stalls = 0; + this->stats_branch_stalls = 0; +} + +bool Vortex_SOC::ibus_driver() { + return false; +} + +void Vortex_SOC::io_handler() { + // std::cout << "Checking\n"; + for (int c = 0; c < vortex->number_cores; c++) { + if (vortex->io_valid[c]) { + uint32_t data_write = (uint32_t)vortex->io_data[c]; + // std::cout << "IO VALID!\n"; + char c = (char)data_write; + std::cerr << c; + // std::cout << c; + + std::cout << std::flush; + } + } +} + +bool Vortex_SOC::dbus_driver() { + // Iterate through each element, and get pop index + int dequeue_index = -1; + bool dequeue_valid = false; + for (int i = 0; i < this->dram_req_vec.size(); i++) { + if (this->dram_req_vec[i].cycles_left > 0) { + this->dram_req_vec[i].cycles_left -= 1; + } + + if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) { + dequeue_index = i; + dequeue_valid = true; + } + } + + if (vortex->out_dram_req) { + if (vortex->out_dram_req_read) { + // Need to add an element + dram_req_t dram_req; + dram_req.cycles_left = vortex->out_dram_expected_lat; + dram_req.data_length = vortex->out_dram_req_size / 4; + dram_req.base_addr = vortex->out_dram_req_addr; + dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned)); + + for (int i = 0; i < dram_req.data_length; i++) { + unsigned curr_addr = dram_req.base_addr + (i * 4); + unsigned data_rd; + ram->getWord(curr_addr, &data_rd); + dram_req.data[i] = data_rd; + } + // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; + this->dram_req_vec.push_back(dram_req); + } + + if (vortex->out_dram_req_write) { + unsigned base_addr = vortex->out_dram_req_addr; + unsigned data_length = vortex->out_dram_req_size / 4; + + for (int i = 0; i < data_length; i++) { + unsigned curr_addr = base_addr + (i * 4); + unsigned data_wr = vortex->out_dram_req_data[i]; + ram->writeWord(curr_addr, &data_wr); + } + } + } + + if (vortex->out_dram_fill_accept && dequeue_valid) { + vortex->out_dram_fill_rsp = 1; + vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; + // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; + + for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) { + vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; + } + free(this->dram_req_vec[dequeue_index].data); + + this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index); + } else { + vortex->out_dram_fill_rsp = 0; + vortex->out_dram_fill_rsp_addr = 0; + } + + return false; +} + +void Vortex_SOC::reset() { + vortex->reset = 1; + this->step(); + vortex->reset = 0; +} + +void Vortex_SOC::step() { + vortex->clk = 0; + vortex->eval(); + +#ifdef VCD_OUTPUT + m_trace->dump(2 * this->stats_total_cycles + 0); +#endif + + vortex->clk = 1; + vortex->eval(); + + ibus_driver(); + dbus_driver(); + io_handler(); + +#ifdef VCD_OUTPUT + m_trace->dump(2 * this->stats_total_cycles + 1); +#endif + + ++time_stamp; + ++stats_total_cycles; +} + +void Vortex_SOC::wait(uint32_t cycles) { + for (int i = 0; i < cycles; ++i) { + this->step(); + } +} + +bool Vortex_SOC::is_busy() { + return (0 == vortex->out_ebreak); +} + +void Vortex_SOC::send_snoops(uint32_t mem_addr, uint32_t size) { + // align address to LLC block boundaries + auto aligned_addr_start = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES); + auto aligned_addr_end = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + size + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES); + + // submit snoop requests for the needed blocks + vortex->llc_snp_req_addr = aligned_addr_start; + vortex->llc_snp_req = false; + for (;;) { + this->step(); + if (vortex->llc_snp_req) { + vortex->llc_snp_req = false; + if (vortex->llc_snp_req_addr >= aligned_addr_end) + break; + vortex->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES; + } + if (!vortex->llc_snp_req_delay) { + vortex->llc_snp_req = true; + } + } +} + +void Vortex_SOC::flush_caches(uint32_t mem_addr, uint32_t size) { + // send snoops for L1 flush + this->send_snoops(mem_addr, size); + +#if NUMBER_CORES != 1 + // send snoops for L2 flush + this->send_snoops(mem_addr, size); +#endif + + // wait 50 cycles to ensure that the request has committed + this->wait(50); +} + +bool Vortex_SOC::simulate() { + // reset the device + this->reset(); + + // execute program + while (!vortex->out_ebreak) { + this->step(); + } + + // wait 5 cycles to flush the pipeline + this->wait(5); + + std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; + + this->print_stats(); + + return false; +} \ No newline at end of file diff --git a/runtime/qemu/vx_api.c b/runtime/qemu/vx_api.c new file mode 100644 index 00000000..16bb493c --- /dev/null +++ b/runtime/qemu/vx_api.c @@ -0,0 +1,27 @@ +#include +#include +#include "../vx_api/vx_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*pocl_workgroup_func) ( + void * /* args */, + void * /* pocl_context */, + uint32_t /* group_x */, + uint32_t /* group_y */, + uint32_t /* group_z */ +); + +void pocl_spawn(struct pocl_context_t * ctx, pocl_workgroup_func pfn, const void * args) { + uint32_t x, y, z; + for (z = 0; z < ctx->num_groups[2]; ++z) + for (y = 0; y < ctx->num_groups[1]; ++y) + for (x = 0; x < ctx->num_groups[0]; ++x) + (pfn)(arguments, ctx, x, y, z); +} + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/simX/out b/simX/out deleted file mode 100644 index 40a41b45..00000000 --- a/simX/out +++ /dev/null @@ -1,2 +0,0 @@ -verilator --compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS '-std=c++11 -fPIC -O3' -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1 -Makefile:26: recipe for target 'simX' failed diff --git a/simX/reading_data.txt b/simX/reading_data.txt deleted file mode 100644 index f9ca6812..00000000 --- a/simX/reading_data.txt +++ /dev/null @@ -1 +0,0 @@ -hello this is the data read from a file! diff --git a/simX/results.txt b/simX/results.txt deleted file mode 100644 index d44e18fb..00000000 --- a/simX/results.txt +++ /dev/null @@ -1 +0,0 @@ -start diff --git a/simX/test.sh b/simX/test.sh deleted file mode 100644 index 066bc487..00000000 --- a/simX/test.sh +++ /dev/null @@ -1,143 +0,0 @@ -echo start > results.txt - -echo ./riscv_tests/rv32ui-p-add.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-add.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-and.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-and.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-or.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-or.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt - -echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt - - - - -echo ./riscv_tests/rv32um-p-div.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32um-p-div.hex -s -b >> results.txt - -echo ./riscv_tests/rv32um-p-divu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32um-p-divu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32um-p-mul.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32um-p-mul.hex -s -b >> results.txt - -echo ./riscv_tests/rv32um-p-mulh.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt - -echo ./riscv_tests/rv32um-p-mulhsu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32um-p-mulhu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt - -echo ./riscv_tests/rv32um-p-rem.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32um-p-rem.hex -s -b >> results.txt - -echo ./riscv_tests/rv32um-p-remu.hex >> results.txt -./harptool -E -a rv32i --core ./riscv_tests/rv32um-p-remu.hex -s -b >> results.txt - diff --git a/simX/test_runtime.sh b/simX/test_runtime.sh new file mode 100755 index 00000000..cbf80793 --- /dev/null +++ b/simX/test_runtime.sh @@ -0,0 +1,17 @@ +make +make -C ../runtime/mains/dev +make -C ../runtime/mains/hello +make -C ../runtime/mains/nativevecadd +make -C ../runtime/mains/simple +make -C ../runtime/mains/vecadd + +cd obj_dir +echo start > results.txt + +printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n" + +#./Vcache_simX -E -a rv32i --core ../../runtime/mains/dev/vx_dev_main.hex -s -b 1> emulator.debug +#./Vcache_simX -E -a rv32i --core ../../runtime/mains/hello/hello.hex -s -b 1> emulator.debug +./Vcache_simX -E -a rv32i --core ../../runtime/mains/nativevecadd/vx_pocl_main.hex -s -b 1> emulator.debug +./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug +./Vcache_simX -E -a rv32i --core ../../runtime/mains/vecadd/vx_pocl_main.hex -s -b 1> emulator.debug \ No newline at end of file From 51fd8974a9b0c5cd9e5a9cc3dd33b6a20c302348 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 20:56:18 -0400 Subject: [PATCH 61/66] minor build fixes --- driver/sw/rtlsim/Makefile | 2 +- driver/tests/demo/demo | Bin 105576 -> 105576 bytes rtl/Makefile | 4 +- rtl/simulate/Vortex.cpp | 2 - rtl/simulate/Vortex.h | 398 +------------------------------------- rtl/simulate/Vortex_SOC.h | 326 +------------------------------ 6 files changed, 18 insertions(+), 714 deletions(-) diff --git a/driver/sw/rtlsim/Makefile b/driver/sw/rtlsim/Makefile index 4a1e82de..6765578e 100644 --- a/driver/sw/rtlsim/Makefile +++ b/driver/sw/rtlsim/Makefile @@ -1,7 +1,7 @@ #CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors -#USE_MULTICORE=1 +USE_MULTICORE=1 CFLAGS += -I../../include -I../../../../rtl/simulate diff --git a/driver/tests/demo/demo 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-Icache -IVX_cache -IVX_cache/interfaces -Iinterface SINGLE_CORE=Vortex.v MULTI_CORE=Vortex_SOC.v -EXE=--exe ./simulate/test_bench.cpp -MULTI_EXE=--exe ./simulate/multi_test_bench.cpp +EXE=--exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp +MULTI_EXE=--exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp COMP=--compiler gcc --language 1800-2009 diff --git a/rtl/simulate/Vortex.cpp b/rtl/simulate/Vortex.cpp index 80b6c964..050b4fd1 100644 --- a/rtl/simulate/Vortex.cpp +++ b/rtl/simulate/Vortex.cpp @@ -291,8 +291,6 @@ void Vortex::flush_caches(uint32_t mem_addr, uint32_t size) { } bool Vortex::simulate() { - this->wait(50); - // reset the device this->reset(); diff --git a/rtl/simulate/Vortex.h b/rtl/simulate/Vortex.h index 1a9d5883..17f87b3b 100644 --- a/rtl/simulate/Vortex.h +++ b/rtl/simulate/Vortex.h @@ -20,13 +20,6 @@ #include #endif -unsigned long time_stamp = 0; - -double sc_time_stamp() -{ - return time_stamp / 1000.0; -} - typedef struct { int cycles_left; @@ -41,11 +34,17 @@ class Vortex Vortex(RAM* ram); ~Vortex(); bool simulate(); + void step(); + void reset(); + void flush_caches(uint32_t mem_addr, uint32_t size); + bool is_busy(); private: void print_stats(bool = true); bool ibus_driver(); bool dbus_driver(); void io_handler(); + void send_snoops(uint32_t mem_addr, uint32_t size); + void wait(uint32_t cycles); RAM* ram; @@ -79,387 +78,4 @@ class Vortex #ifdef VCD_OUTPUT VerilatedVcdC *m_trace; #endif -}; - - - -Vortex::Vortex(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), - stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), - debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), - debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) -{ - this->ram = ram; - this->vortex = new VVortex; - #ifdef VCD_OUTPUT - this->m_trace = new VerilatedVcdC; - this->vortex->trace(m_trace, 99); - this->m_trace->open("trace.vcd"); - #endif - this->results.open("../results.txt"); -} - -Vortex::~Vortex() -{ - #ifdef VCD_OUTPUT - m_trace->close(); - #endif - this->results.close(); - delete this->vortex; -} - -void Vortex::print_stats(bool cycle_test) -{ - - if (cycle_test) - { - this->results << std::left; - // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; - this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; - this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; - this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - else - { - this->results << std::left; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - - - uint32_t status; - ram->getWord(0, &status); - - if (this->unit_test) - { - if (status == 1) - { - this->results << std::setw(24) << "# GRADE:" << "PASSING\n"; - } else - { - this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n"; - } - } - else - { - this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n"; - } - - this->stats_static_inst = 0; - this->stats_dynamic_inst = -1; - this->stats_total_cycles = 0; - this->stats_fwd_stalls = 0; - this->stats_branch_stalls = 0; - -} - -bool Vortex::ibus_driver() -{ - - // Iterate through each element, and get pop index - int dequeue_index = -1; - bool dequeue_valid = false; - for (int i = 0; i < this->I_dram_req_vec.size(); i++) - { - if (this->I_dram_req_vec[i].cycles_left > 0) - { - this->I_dram_req_vec[i].cycles_left -= 1; - } - - if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) - { - dequeue_index = i; - dequeue_valid = true; - } - } - - - if (vortex->I_dram_req) - { - // std::cout << "Icache Dram Request received!\n"; - if (vortex->I_dram_req_read) - { - // std::cout << "Icache Dram Request is read!\n"; - // Need to add an element - dram_req_t dram_req; - dram_req.cycles_left = vortex->I_dram_expected_lat; - dram_req.data_length = vortex->I_dram_req_size / 4; - dram_req.base_addr = vortex->I_dram_req_addr; - dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); - - for (int i = 0; i < dram_req.data_length; i++) - { - unsigned curr_addr = dram_req.base_addr + (i*4); - unsigned data_rd; - ram->getWord(curr_addr, &data_rd); - dram_req.data[i] = data_rd; - } - // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; - this->I_dram_req_vec.push_back(dram_req); - } - - if (vortex->I_dram_req_write) - { - unsigned base_addr = vortex->I_dram_req_addr; - unsigned data_length = vortex->I_dram_req_size / 4; - - for (int i = 0; i < data_length; i++) - { - unsigned curr_addr = base_addr + (i*4); - unsigned data_wr = vortex->I_dram_req_data[i]; - ram->writeWord(curr_addr, &data_wr); - } - } - } - - if (vortex->I_dram_fill_accept && dequeue_valid) - { - // std::cout << "Icache Dram Response Sending...!\n"; - - vortex->I_dram_fill_rsp = 1; - vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr; - // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; - - for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++) - { - vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i]; - } - free(this->I_dram_req_vec[dequeue_index].data); - - this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index); - } - else - { - vortex->I_dram_fill_rsp = 0; - vortex->I_dram_fill_rsp_addr = 0; - } - - return false; - -} - -void Vortex::io_handler() -{ - // std::cout << "Checking\n"; - if (vortex->io_valid) - { - uint32_t data_write = (uint32_t) vortex->io_data; - // std::cout << "IO VALID!\n"; - char c = (char) data_write; - std::cerr << c; - // std::cout << c; - - std::cout << std::flush; - } -} - - -bool Vortex::dbus_driver() -{ - - // Iterate through each element, and get pop index - int dequeue_index = -1; - bool dequeue_valid = false; - for (int i = 0; i < this->dram_req_vec.size(); i++) - { - if (this->dram_req_vec[i].cycles_left > 0) - { - this->dram_req_vec[i].cycles_left -= 1; - } - - if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) - { - dequeue_index = i; - dequeue_valid = true; - } - } - - - if (vortex->dram_req) - { - if (vortex->dram_req_read) - { - // Need to add an element - dram_req_t dram_req; - dram_req.cycles_left = vortex->dram_expected_lat; - dram_req.data_length = vortex->dram_req_size / 4; - dram_req.base_addr = vortex->dram_req_addr; - dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); - - for (int i = 0; i < dram_req.data_length; i++) - { - unsigned curr_addr = dram_req.base_addr + (i*4); - unsigned data_rd; - ram->getWord(curr_addr, &data_rd); - dram_req.data[i] = data_rd; - } - // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; - this->dram_req_vec.push_back(dram_req); - } - - if (vortex->dram_req_write) - { - unsigned base_addr = vortex->dram_req_addr; - unsigned data_length = vortex->dram_req_size / 4; - - for (int i = 0; i < data_length; i++) - { - unsigned curr_addr = base_addr + (i*4); - unsigned data_wr = vortex->dram_req_data[i]; - ram->writeWord(curr_addr, &data_wr); - } - } - } - - if (vortex->dram_fill_accept && dequeue_valid) - { - vortex->dram_fill_rsp = 1; - vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; - // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; - - for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) - { - vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; - } - free(this->dram_req_vec[dequeue_index].data); - - this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index); - } - else - { - vortex->dram_fill_rsp = 0; - vortex->dram_fill_rsp_addr = 0; - } - - return false; -} - - - -bool Vortex::simulate() -{ - // auto start_time = std::chrono::high_resolution_clock::now(); - - static bool stop = false; - static int counter = 0; - counter = 0; - stop = false; - - // auto start_time = clock(); - - - // vortex->reset = 1; - - - // vortex->reset = 0; - - unsigned curr_inst; - unsigned new_PC; - - // while (this->stop && (!(stop && (counter > 5)))) - // { - - // // std::cout << "************* Cycle: " << cycle << "\n"; - // bool istop = ibus_driver(); - // bool dstop = !dbus_driver(); - - // vortex->clk = 1; - // vortex->eval(); - - - - // vortex->clk = 0; - // vortex->eval(); - - - // stop = istop && dstop; - - // if (stop) - // { - // counter++; - // } else - // { - // counter = 0; - // } - - // cycle++; - // } - - bool istop; - bool dstop; - bool cont = false; - // for (int i = 0; i < 500; i++) - - vortex->reset = 1; - vortex->clk = 0; - vortex->eval(); - // m_trace->dump(10); - vortex->reset = 1; - vortex->clk = 1; - vortex->eval(); - // m_trace->dump(11); - vortex->reset = 0; - vortex->clk = 0; - - // unsigned cycles; - counter = 0; - this->stats_total_cycles = 12; - while (this->stop && ((counter < 5))) - // while (this->stats_total_cycles < 10) - { - - // printf("-------------------------\n"); - // std::cout << "Counter: " << counter << "\n"; - // if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n"; - // dstop = !dbus_driver(); - #ifdef VCD_OUTPUT - m_trace->dump(2*this->stats_total_cycles); - #endif - vortex->clk = 1; - vortex->eval(); - istop = ibus_driver(); - dstop = !dbus_driver(); - io_handler(); - - #ifdef VCD_OUTPUT - m_trace->dump((2*this->stats_total_cycles)+1); - #endif - vortex->clk = 0; - vortex->eval(); - // stop = istop && dstop; - stop = vortex->out_ebreak; - - if (stop || cont) - // if (istop) - { - cont = true; - counter++; - } else - { - counter = 0; - } - - ++time_stamp; - ++stats_total_cycles; - } - - std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; - - int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf; - - // std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n"; - - // std::cout << "Something: " << result << '\n'; - - // uint32_t status; - // ram->getWord(0, &status); - - this->print_stats(); - - - - return (status == 1); - // return (1 == 1); -} \ No newline at end of file +}; \ No newline at end of file diff --git a/rtl/simulate/Vortex_SOC.h b/rtl/simulate/Vortex_SOC.h index 374693f8..df45fa6d 100644 --- a/rtl/simulate/Vortex_SOC.h +++ b/rtl/simulate/Vortex_SOC.h @@ -19,13 +19,6 @@ #include #endif -unsigned long time_stamp = 0; - -double sc_time_stamp() -{ - return time_stamp / 1000.0; -} - typedef struct { int cycles_left; @@ -40,11 +33,17 @@ class Vortex_SOC Vortex_SOC(RAM* ram); ~Vortex_SOC(); bool simulate(); + void step(); + void reset(); + void flush_caches(uint32_t mem_addr, uint32_t size); + bool is_busy(); private: void print_stats(bool = true); bool ibus_driver(); bool dbus_driver(); - void io_handler(); + void io_handler(); + void send_snoops(uint32_t mem_addr, uint32_t size); + void wait(uint32_t cycles); RAM* ram; @@ -77,313 +76,4 @@ class Vortex_SOC #ifdef VCD_OUTPUT VerilatedVcdC *m_trace; #endif -}; - - - -Vortex_SOC::Vortex_SOC(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), - stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), - debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), - debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) -{ - this->ram = ram; - this->vortex = new VVortex_SOC; - #ifdef VCD_OUTPUT - this->m_trace = new VerilatedVcdC; - this->vortex->trace(m_trace, 99); - this->m_trace->open("trace.vcd"); - #endif - this->results.open("../results.txt"); -} - -Vortex_SOC::~Vortex_SOC() -{ - #ifdef VCD_OUTPUT - m_trace->close(); - #endif - this->results.close(); - delete this->vortex; -} - -void Vortex_SOC::print_stats(bool cycle_test) -{ - - if (cycle_test) - { - this->results << std::left; - // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; - this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; - this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; - this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - else - { - this->results << std::left; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - - - uint32_t status; - ram->getWord(0, &status); - - if (this->unit_test) - { - if (status == 1) - { - this->results << std::setw(24) << "# GRADE:" << "PASSING\n"; - } else - { - this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n"; - } - } - else - { - this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n"; - } - - this->stats_static_inst = 0; - this->stats_dynamic_inst = -1; - this->stats_total_cycles = 0; - this->stats_fwd_stalls = 0; - this->stats_branch_stalls = 0; - -} - -bool Vortex_SOC::ibus_driver() -{ - - return false; - -} - -void Vortex_SOC::io_handler() -{ - // std::cout << "Checking\n"; - for (int c = 0; c < vortex->number_cores; c++) - { - if (vortex->io_valid[c]) - { - uint32_t data_write = (uint32_t) vortex->io_data[c]; - // std::cout << "IO VALID!\n"; - char c = (char) data_write; - std::cerr << c; - // std::cout << c; - - std::cout << std::flush; - } - } -} - - -bool Vortex_SOC::dbus_driver() -{ - - // Iterate through each element, and get pop index - int dequeue_index = -1; - bool dequeue_valid = false; - for (int i = 0; i < this->dram_req_vec.size(); i++) - { - if (this->dram_req_vec[i].cycles_left > 0) - { - this->dram_req_vec[i].cycles_left -= 1; - } - - if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) - { - dequeue_index = i; - dequeue_valid = true; - } - } - - - if (vortex->out_dram_req) - { - if (vortex->out_dram_req_read) - { - // Need to add an element - dram_req_t dram_req; - dram_req.cycles_left = vortex->out_dram_expected_lat; - dram_req.data_length = vortex->out_dram_req_size / 4; - dram_req.base_addr = vortex->out_dram_req_addr; - dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned)); - - for (int i = 0; i < dram_req.data_length; i++) - { - unsigned curr_addr = dram_req.base_addr + (i*4); - unsigned data_rd; - ram->getWord(curr_addr, &data_rd); - dram_req.data[i] = data_rd; - } - // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n"; - this->dram_req_vec.push_back(dram_req); - } - - if (vortex->out_dram_req_write) - { - unsigned base_addr = vortex->out_dram_req_addr; - unsigned data_length = vortex->out_dram_req_size / 4; - - for (int i = 0; i < data_length; i++) - { - unsigned curr_addr = base_addr + (i*4); - unsigned data_wr = vortex->out_dram_req_data[i]; - ram->writeWord(curr_addr, &data_wr); - } - } - } - - if (vortex->out_dram_fill_accept && dequeue_valid) - { - vortex->out_dram_fill_rsp = 1; - vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr; - // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n"; - - for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) - { - vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i]; - } - free(this->dram_req_vec[dequeue_index].data); - - this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index); - } - else - { - vortex->out_dram_fill_rsp = 0; - vortex->out_dram_fill_rsp_addr = 0; - } - - return false; -} - - - -bool Vortex_SOC::simulate() -{ - // auto start_time = std::chrono::high_resolution_clock::now(); - - static bool stop = false; - static int counter = 0; - counter = 0; - stop = false; - - // auto start_time = clock(); - - - // vortex->reset = 1; - - - // vortex->reset = 0; - - unsigned curr_inst; - unsigned new_PC; - - // while (this->stop && (!(stop && (counter > 5)))) - // { - - // // std::cout << "************* Cycle: " << cycle << "\n"; - // bool istop = ibus_driver(); - // bool dstop = !dbus_driver(); - - // vortex->clk = 1; - // vortex->eval(); - - - - // vortex->clk = 0; - // vortex->eval(); - - - // stop = istop && dstop; - - // if (stop) - // { - // counter++; - // } else - // { - // counter = 0; - // } - - // cycle++; - // } - - bool istop; - bool dstop; - bool cont = false; - // for (int i = 0; i < 500; i++) - - vortex->reset = 1; - vortex->clk = 0; - vortex->eval(); - // m_trace->dump(10); - vortex->reset = 1; - vortex->clk = 1; - vortex->eval(); - // m_trace->dump(11); - vortex->reset = 0; - vortex->clk = 0; - - // unsigned cycles; - counter = 0; - this->stats_total_cycles = 12; - while (this->stop && ((counter < 5))) - // while (this->stats_total_cycles < 10) - { - - // printf("-------------------------\n"); - // std::cout << "Counter: " << counter << "\n"; - // if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n"; - // dstop = !dbus_driver(); - #ifdef VCD_OUTPUT - m_trace->dump(2*this->stats_total_cycles); - #endif - vortex->clk = 1; - vortex->eval(); - istop = ibus_driver(); - dstop = !dbus_driver(); - io_handler(); - - #ifdef VCD_OUTPUT - m_trace->dump((2*this->stats_total_cycles)+1); - #endif - vortex->clk = 0; - vortex->eval(); - // stop = istop && dstop; - stop = vortex->out_ebreak; - - if (stop || cont) - // if (istop) - { - cont = true; - counter++; - } else - { - counter = 0; - } - - ++time_stamp; - ++stats_total_cycles; - } - - std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; - - int status = 0; - // int status = (unsigned int) vortex->Vortex_SOC__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf; - - // std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n"; - - // std::cout << "Something: " << result << '\n'; - - // uint32_t status; - // ram->getWord(0, &status); - - this->print_stats(); - - - - return (status == 1); - // return (1 == 1); -} \ No newline at end of file +}; \ No newline at end of file From 5d320a93130a100dd09452e2cabdc42725153f13 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 21:04:23 -0400 Subject: [PATCH 62/66] fixed multicore build --- rtl/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/Makefile b/rtl/Makefile index 30f3224c..7a4aa7e6 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -46,7 +46,7 @@ VERILATORnoWarningsRel: build_config VERILATORMULTInoWarnings: build_config - verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) $(DEB) --threads $(THREADS) + verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB) compdebug: build_config verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) From 550d96a73c3b61ddb5019a57b7cbbf08ce54e1af Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 21:54:55 -0400 Subject: [PATCH 63/66] rtlsim driver works with Vortex! --- driver/sw/rtlsim/Makefile | 6 +++--- driver/sw/rtlsim/vortex.cpp | 1 + rtl/VX_warp_scheduler.v | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/driver/sw/rtlsim/Makefile b/driver/sw/rtlsim/Makefile index 6765578e..5fedbe94 100644 --- a/driver/sw/rtlsim/Makefile +++ b/driver/sw/rtlsim/Makefile @@ -1,7 +1,7 @@ #CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors -USE_MULTICORE=1 +#USE_MULTICORE=1 CFLAGS += -I../../include -I../../../../rtl/simulate @@ -30,8 +30,8 @@ VL_FLAGS += -Wno-UNOPTFLAT -Wno-WIDTH VL_FLAGS += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN # Debugigng -VL_FLAGS += --trace -DVL_DEBUG=1 -CFLAGS += -DVCD_OUTPUT +#VL_FLAGS += --trace -DVL_DEBUG=1 +#CFLAGS += -DVCD_OUTPUT PROJECT = libvortex.so diff --git a/driver/sw/rtlsim/vortex.cpp b/driver/sw/rtlsim/vortex.cpp index 50f2c599..a2b7e107 100644 --- a/driver/sw/rtlsim/vortex.cpp +++ b/driver/sw/rtlsim/vortex.cpp @@ -78,6 +78,7 @@ public: : is_done_(false) , mem_allocation_(VX_ALLOC_BASE_ADDR) , vortex_(&ram_) { + vortex_.reset(); thread_ = new std::thread(__thread_proc__, this); } diff --git a/rtl/VX_warp_scheduler.v b/rtl/VX_warp_scheduler.v index a20af31e..22ad21da 100644 --- a/rtl/VX_warp_scheduler.v +++ b/rtl/VX_warp_scheduler.v @@ -298,7 +298,7 @@ module VX_warp_scheduler ( assign global_stall = (stall || wstall_this_cycle || hazard || !real_schedule || is_join); - assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || is_join); + assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || is_join) && !reset; wire real_use_wspawn = use_wsapwn[warp_to_schedule]; From e80fa7f2333cce067c0dac0e05b7294f01c44e43 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 22:37:35 -0400 Subject: [PATCH 64/66] missing rtl changes from OPAE --- rtl/Makefile | 44 +++++---- rtl/Vortex.v | 22 ++++- rtl/Vortex_SOC.v | 8 +- rtl/shared_memory/VX_shared_memory_block.v | 5 +- rtl/simulate/Vortex.h | 109 ++++++++++----------- rtl/simulate/Vortex_SOC.h | 108 ++++++++++---------- rtl/simulate/multi_test_bench.cpp | 8 +- rtl/simulate/test_bench.cpp | 5 +- 8 files changed, 160 insertions(+), 149 deletions(-) diff --git a/rtl/Makefile b/rtl/Makefile index 7a4aa7e6..348bdb62 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -1,32 +1,35 @@ all: RUNFILE -INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate +INCLUDE = -I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate -SINGLE_CORE=Vortex.v -MULTI_CORE=Vortex_SOC.v +SINGLE_CORE = Vortex.v -EXE=--exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp -MULTI_EXE=--exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp +MULTI_CORE = Vortex_SOC.v -COMP=--compiler gcc --language 1800-2009 +EXE += --exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp -WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN +MULTI_EXE += --exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp + +VF += -compiler gcc --language 1800-2009 + +WNO += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN # WNO= # LIGHTW= -LIGHTW=-Wno-UNOPTFLAT +LIGHTW += -Wno-UNOPTFLAT + # LIB=-LDFLAGS '-L/usr/local/systemc/' -LIB= +LIB += -CF = -std=c++11 -fms-extensions +CF += -std=c++11 -fms-extensions -DEB=--trace -DVL_DEBUG=1 +DEB += --trace -DVL_DEBUG=1 -MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) +MAKECPP += (cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) -MAKECPPRel=(cd obj_dir && make -j -f VVortex.mk) +MAKECPPRel += (cd obj_dir && make -j -f VVortex.mk) -MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) +MAKEMULTICPP += (cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') @@ -36,23 +39,22 @@ build_config: # -LDFLAGS '-lsystemc' VERILATOR: build_config - verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(LIGHTW) + verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(LIGHTW) VERILATORnoWarnings: build_config - verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB) + verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(WNO) $(DEB) VERILATORnoWarningsRel: build_config - verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) --threads $(THREADS) - + verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) --threads $(THREADS) VERILATORMULTInoWarnings: build_config - verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB) + verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) $(DEB) --threads $(THREADS) compdebug: build_config - verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) + verilator_bin_dbg $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) compdebugmulti: build_config - verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) + verilator_bin_dbg $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) RUNFILE: VERILATOR $(MAKECPP) diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 8660861f..670f9eb0 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -30,11 +30,31 @@ module Vortex input wire [31:0] dram_fill_rsp_addr, input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], - // LLC Snooping + // DRAM Icache Req + output wire I_dram_req, + output wire I_dram_req_write, + output wire I_dram_req_read, + output wire [31:0] I_dram_req_addr, + output wire [31:0] I_dram_req_size, + output wire [31:0] I_dram_req_data[`IBANK_LINE_SIZE_RNG], + output wire [31:0] I_dram_expected_lat, + + // DRAM Icache Res + output wire I_dram_fill_accept, + input wire I_dram_fill_rsp, + input wire [31:0] I_dram_fill_rsp_addr, + input wire [31:0] I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG], + + // Dcache Snooping input wire snp_req, input wire [31:0] snp_req_addr, output wire snp_req_delay, + // Icache Snooping + input wire I_snp_req, + input wire [31:0] I_snp_req_addr, + output wire I_snp_req_delay, + output wire out_ebreak `else diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v index f2630c90..a58b6830 100644 --- a/rtl/Vortex_SOC.v +++ b/rtl/Vortex_SOC.v @@ -369,11 +369,11 @@ module Vortex_SOC ( assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; - assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; - assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; + assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; + assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; - assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; - assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; + assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; + assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; end // endgenerate diff --git a/rtl/shared_memory/VX_shared_memory_block.v b/rtl/shared_memory/VX_shared_memory_block.v index 0783583c..1452004d 100644 --- a/rtl/shared_memory/VX_shared_memory_block.v +++ b/rtl/shared_memory/VX_shared_memory_block.v @@ -29,6 +29,8 @@ module VX_shared_memory_block `ifndef SYN reg[SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0]; + + wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr; //wire need_to_write = (|we); integer curr_ind; @@ -48,8 +50,7 @@ module VX_shared_memory_block if (we == 2'b11) shared_memory[reg_addr][3] <= wdata[3]; end end - - wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr; + assign reg_addr = addr; // always @(posedge clk) // reg_addr <= addr; diff --git a/rtl/simulate/Vortex.h b/rtl/simulate/Vortex.h index 17f87b3b..a8cd9b0a 100644 --- a/rtl/simulate/Vortex.h +++ b/rtl/simulate/Vortex.h @@ -1,7 +1,7 @@ // C++ libraries -#include +#include #include -#include +#include #include #include #include @@ -20,62 +20,61 @@ #include #endif -typedef struct -{ - int cycles_left; - int data_length; - unsigned base_addr; - unsigned * data; +typedef struct { + int cycles_left; + int data_length; + unsigned base_addr; + unsigned *data; } dram_req_t; -class Vortex -{ - public: - Vortex(RAM* ram); - ~Vortex(); - bool simulate(); - void step(); - void reset(); - void flush_caches(uint32_t mem_addr, uint32_t size); - bool is_busy(); - private: - void print_stats(bool = true); - bool ibus_driver(); - bool dbus_driver(); - void io_handler(); - void send_snoops(uint32_t mem_addr, uint32_t size); - void wait(uint32_t cycles); +class Vortex { +public: + Vortex(RAM *ram); + ~Vortex(); + bool is_busy(); + void reset(); + void step(); + void flush_caches(uint32_t mem_addr, uint32_t size); + bool simulate(); - RAM* ram; +private: + void print_stats(bool cycle_test = true); + bool ibus_driver(); + bool dbus_driver(); + void io_handler(); + void send_snoops(uint32_t mem_addr, uint32_t size); + void wait(uint32_t cycles); - VVortex * vortex; + RAM *ram; - unsigned start_pc; - bool refill_d; - unsigned refill_addr_d; - bool refill_i; - unsigned refill_addr_i; - long int curr_cycle; - bool stop; - bool unit_test; - std::ofstream results; - int stats_static_inst; - int stats_dynamic_inst; - int stats_total_cycles; - int stats_fwd_stalls; - int stats_branch_stalls; - int debug_state; - int ibus_state; - int dbus_state; - int debug_return; - int debug_wait_num; - int debug_inst_num; - int debug_end_wait; - int debug_debugAddr; - double stats_sim_time; - std::vector dram_req_vec; - std::vector I_dram_req_vec; - #ifdef VCD_OUTPUT - VerilatedVcdC *m_trace; - #endif + VVortex *vortex; + + unsigned start_pc; + bool refill_d; + unsigned refill_addr_d; + bool refill_i; + unsigned refill_addr_i; + long int curr_cycle; + bool stop; + bool unit_test; + std::ofstream results; + int stats_static_inst; + int stats_dynamic_inst; + int stats_total_cycles; + int stats_fwd_stalls; + int stats_branch_stalls; + int debug_state; + int ibus_state; + int dbus_state; + int debug_return; + int debug_wait_num; + int debug_inst_num; + int debug_end_wait; + int debug_debugAddr; + double stats_sim_time; + std::vector dram_req_vec; + std::vector I_dram_req_vec; +#ifdef VCD_OUTPUT + VerilatedVcdC *m_trace; +#endif }; \ No newline at end of file diff --git a/rtl/simulate/Vortex_SOC.h b/rtl/simulate/Vortex_SOC.h index df45fa6d..5ccbe044 100644 --- a/rtl/simulate/Vortex_SOC.h +++ b/rtl/simulate/Vortex_SOC.h @@ -1,7 +1,7 @@ // C++ libraries -#include +#include #include -#include +#include #include #include #include @@ -19,61 +19,59 @@ #include #endif -typedef struct -{ - int cycles_left; - int data_length; - unsigned base_addr; - unsigned * data; +typedef struct { + int cycles_left; + int data_length; + unsigned base_addr; + unsigned *data; } dram_req_t; -class Vortex_SOC -{ - public: - Vortex_SOC(RAM* ram); - ~Vortex_SOC(); - bool simulate(); - void step(); - void reset(); - void flush_caches(uint32_t mem_addr, uint32_t size); - bool is_busy(); - private: - void print_stats(bool = true); - bool ibus_driver(); - bool dbus_driver(); - void io_handler(); - void send_snoops(uint32_t mem_addr, uint32_t size); - void wait(uint32_t cycles); +class Vortex_SOC { +public: + Vortex_SOC(RAM *ram); + ~Vortex_SOC(); + bool is_busy(); + void reset(); + void step(); + void flush_caches(uint32_t mem_addr, uint32_t size); + bool simulate(); +private: + void print_stats(bool cycle_test = true); + bool ibus_driver(); + bool dbus_driver(); + void io_handler(); + void send_snoops(uint32_t mem_addr, uint32_t size); + void wait(uint32_t cycles); - RAM* ram; + RAM *ram; - VVortex_SOC * vortex; + VVortex_SOC *vortex; - unsigned start_pc; - bool refill_d; - unsigned refill_addr_d; - bool refill_i; - unsigned refill_addr_i; - long int curr_cycle; - bool stop; - bool unit_test; - std::ofstream results; - int stats_static_inst; - int stats_dynamic_inst; - int stats_total_cycles; - int stats_fwd_stalls; - int stats_branch_stalls; - int debug_state; - int ibus_state; - int dbus_state; - int debug_return; - int debug_wait_num; - int debug_inst_num; - int debug_end_wait; - int debug_debugAddr; - double stats_sim_time; - std::vector dram_req_vec; - #ifdef VCD_OUTPUT - VerilatedVcdC *m_trace; - #endif -}; \ No newline at end of file + unsigned start_pc; + bool refill_d; + unsigned refill_addr_d; + bool refill_i; + unsigned refill_addr_i; + long int curr_cycle; + bool stop; + bool unit_test; + std::ofstream results; + int stats_static_inst; + int stats_dynamic_inst; + int stats_total_cycles; + int stats_fwd_stalls; + int stats_branch_stalls; + int debug_state; + int ibus_state; + int dbus_state; + int debug_return; + int debug_wait_num; + int debug_inst_num; + int debug_end_wait; + int debug_debugAddr; + double stats_sim_time; + std::vector dram_req_vec; +#ifdef VCD_OUTPUT + VerilatedVcdC *m_trace; +#endif +}; diff --git a/rtl/simulate/multi_test_bench.cpp b/rtl/simulate/multi_test_bench.cpp index 7dcc0436..8e4a6e05 100644 --- a/rtl/simulate/multi_test_bench.cpp +++ b/rtl/simulate/multi_test_bench.cpp @@ -3,16 +3,10 @@ #define NUM_TESTS 46 int main(int argc, char **argv) -{ - - // Verilated::debug(1); Verilated::commandArgs(argc, argv); - Verilated::traceEverOn(true); - - -// #define ALL_TESTS +#define ALL_TESTS #ifdef ALL_TESTS bool passed = true; std::string tests[NUM_TESTS] = { diff --git a/rtl/simulate/test_bench.cpp b/rtl/simulate/test_bench.cpp index 391c93db..2882b7f6 100644 --- a/rtl/simulate/test_bench.cpp +++ b/rtl/simulate/test_bench.cpp @@ -9,10 +9,7 @@ int main(int argc, char **argv) Verilated::commandArgs(argc, argv); - Verilated::traceEverOn(true); - - -// #define ALL_TESTS +#define ALL_TESTS #ifdef ALL_TESTS bool passed = true; From 89d5bfbef1d8b9d4e23a44a5b0f54d29044a4d11 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 22:44:16 -0400 Subject: [PATCH 65/66] missing simX changes from OPAE --- simX/Makefile | 6 +- simX/cache_simX.v | 2 +- simX/core.cpp | 138 ++++++---------- simX/enc.cpp | 5 +- simX/include/archdef.h | 12 +- simX/include/debug.h | 22 ++- simX/include/mem.h | 140 +---------------- simX/instruction.cpp | 346 +++++++++++++++++++++-------------------- simX/mem.cpp | 114 ++++++++++++++ simX/simX.cpp | 48 +++--- simX/test_riscv.sh | 144 ++++++++++++++++- 11 files changed, 552 insertions(+), 425 deletions(-) diff --git a/simX/Makefile b/simX/Makefile index 68fe7414..1672b056 100644 --- a/simX/Makefile +++ b/simX/Makefile @@ -2,13 +2,13 @@ # HARPtools by Chad D. Kersey, Summer 2011 # ################################################################################ -CXXFLAGS ?= -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS -# CXXFLAGS ?= -std=c++11 -fPIC -O0 -g -Wall -Wextra -pedantic # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS +CXXFLAGS ?= -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS +#CXXFLAGS ?= -std=c++11 -fPIC -g -O0 -Wall -Wextra -pedantic -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS LIB_OBJS=simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -INCLUDE=-I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl +INCLUDE=-I. -I../old_rtl -I../old_rtl/interfaces -I../old_rtl/cache -I../old_rtl/shared_memory -Isimulate FILE=cache_simX.v COMP=--compiler gcc LIB= diff --git a/simX/cache_simX.v b/simX/cache_simX.v index 249d7d2e..2183864b 100644 --- a/simX/cache_simX.v +++ b/simX/cache_simX.v @@ -1,5 +1,5 @@ -`include "../rtl/VX_define.v" +`include "../old_rtl/VX_define.v" module cache_simX ( input wire clk, // Clock diff --git a/simX/core.cpp b/simX/core.cpp index 7ba684a4..bc4a5ffa 100644 --- a/simX/core.cpp +++ b/simX/core.cpp @@ -80,19 +80,17 @@ using namespace std; void printTrace(trace_inst_t * trace, const char * stage_name) { - D(3, "********************************** " << stage_name << " *********************************"); - D(3, "valid: " << trace->valid_inst); - D(3, "PC: " << hex << trace->pc << dec); - D(3, "wid: " << trace->wid); - D(3, "rd: " << trace->rd << "\trs1: " << trace->rs1 << "\trs2: " << trace->rs2); - D(3, "is_lw: " << trace->is_lw); - D(3, "is_sw: " << trace->is_sw); - D(3, "fetch_stall_cycles: " << trace->fetch_stall_cycles); - D(3, "mem_stall_cycles: " << trace->mem_stall_cycles); - - D(3, "stall_warp: " << trace->stall_warp); - D(3, "wspawn: " << trace->wspawn); - D(3, "stalled: " << trace->stalled); + D(3, stage_name << ": valid=" << trace->valid_inst); + D(3, stage_name << ": PC=" << hex << trace->pc << dec); + D(3, stage_name << ": wid=" << trace->wid); + D(3, stage_name << ": rd=" << trace->rd << ", rs1=" << trace->rs1 << ", trs2=" << trace->rs2); + D(3, stage_name << ": is_lw=" << trace->is_lw); + D(3, stage_name << ": is_sw=" << trace->is_sw); + D(3, stage_name << ": fetch_stall_cycles=" << trace->fetch_stall_cycles); + D(3, stage_name << ": mem_stall_cycles=" << trace->mem_stall_cycles); + D(3, stage_name << ": stall_warp=" << trace->stall_warp); + D(3, stage_name << ": wspawn=" << trace->wspawn); + D(3, stage_name << ": stalled=" << trace->stalled); } #ifdef EMU_INSTRUMENTATION @@ -126,17 +124,14 @@ Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id): INIT_TRACE(inst_in_lsu); INIT_TRACE(inst_in_wb); - for (int i = 0; i < 32; i++) - { + for (int i = 0; i < 32; i++) { stallWarp[i] = false; - for (int j = 0; j < 32; j++) - { + for (int j = 0; j < 32; j++) { renameTable[i][j] = true; } } - for(int i = 0; i < 32; i++) - { + for(int i = 0; i < 32; i++) { vecRenameTable[i] = true; } @@ -157,8 +152,9 @@ Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id): cache_simulator->reset = 0; cache_simulator->clk = 0; - for (unsigned i = 0; i < a.getNWarps(); ++i) + for (unsigned i = 0; i < a.getNWarps(); ++i) { w.push_back(Warp(this, i)); + } w[0].activeThreads = 1; w[0].spawned = true; @@ -171,19 +167,17 @@ bool Core::interrupt(Word r0) { void Core::step() { - D(3, "\n\n\n------------------------------------------------------"); - - D(3, "Started core::step" << flush); + D(3, "###########################################################"); steps++; this->num_cycles++; - D(3, "CYCLE: " << this->num_cycles); + D(3, "cycle: " << this->num_cycles); - D(3, "Stalled Warps:"); - for (int widd = 0; widd < a.getNWarps(); widd++) - { - D(3, stallWarp[widd] << " "); + DPH(3, "stalled warps:"); + for (int widd = 0; widd < a.getNWarps(); widd++) { + DPN(3, " " << stallWarp[widd]); } + DPN(3, "\n"); // cout << "Rename table\n"; // for (int regii = 0; regii < 32; regii++) @@ -213,8 +207,7 @@ void Core::step() stallWarp[release_warp_num] = false; } - D(3, "released warp" << flush); - D(3, "Finished core::step" << flush); + DPN(3, flush); } void Core::getCacheDelays(trace_inst_t * trace_inst) @@ -400,11 +393,7 @@ void Core::warpScheduler() void Core::fetch() { - // #ifdef PRINT_ACTIVE_THREADS - D(3, "Threads:"); - // #endif - - // D(-1, "Found schedule: " << foundSchedule); + // D(-1, "Found schedule: " << foundSchedule); if ((!inst_in_scheduler.stalled) && (inst_in_fetch.fetch_stall_cycles == 0)) { @@ -416,23 +405,24 @@ void Core::fetch() if (foundSchedule) { - D(3, "Core step stepping warp " << schedule_w << '[' << w[schedule_w].activeThreads << ']'); + auto active_threads_b = w[schedule_w].activeThreads; + this->num_instructions = this->num_instructions + w[schedule_w].activeThreads; // this->num_instructions++; w[schedule_w].step(&inst_in_fetch); - D(3, "Now " << w[schedule_w].activeThreads << " active threads in " << schedule_w << flush); + + auto active_threads_a = w[schedule_w].activeThreads; + if (active_threads_b != active_threads_a) { + D(3, "** warp #" << schedule_w << " active threads changed from " << active_threads_b << " to " << active_threads_a); + } this->getCacheDelays(&inst_in_fetch); - D(3, "Got cache delays" << flush); - if (inst_in_fetch.stall_warp) - { + + if (inst_in_fetch.stall_warp) { stallWarp[inst_in_fetch.wid] = true; } - D(3, "staled warps\n" << flush); } - D(3, "About to schedule warp\n" << flush); warpScheduler(); - D(3, "Scheduled warp" << flush); } } else @@ -441,30 +431,19 @@ void Core::fetch() if (inst_in_fetch.fetch_stall_cycles > 0) inst_in_fetch.fetch_stall_cycles--; } - D(3, "Printing trace" << flush); printTrace(&inst_in_fetch, "Fetch"); - D(3, "printed trace" << flush); - + // #ifdef PRINT_ACTIVE_THREADS - D(3, "About to print active threads" << flush << "\n"); + DPH(3, "active threads:"); for (unsigned j = 0; j < w[schedule_w].tmask.size(); ++j) { - if (w[schedule_w].activeThreads > j && w[schedule_w].tmask[j]) - { - D(3, " 1"); - } - else - { - D(3, " 0"); + if (w[schedule_w].activeThreads > j && w[schedule_w].tmask[j]) { + DPN(3, " 1"); + } else { + DPN(3, " 0"); } - if (j != w[schedule_w].tmask.size()-1 || schedule_w != w.size()-1) - { - D(3, ','); - } - } - D(3, "\nPrinted active threads" << flush); - // #endif - - + } + DPN(3, "\n"); + // #endif // #ifdef PRINT_ACTIVE_THREADS // #endif @@ -472,9 +451,6 @@ void Core::fetch() void Core::decode() { - - - if ((inst_in_fetch.fetch_stall_cycles == 0) && !inst_in_scheduler.stalled) { CPY_TRACE(inst_in_decode, inst_in_fetch); @@ -493,7 +469,7 @@ void Core::scheduler() INIT_TRACE(inst_in_decode); } - //printTrace(&inst_in_scheduler, "scheduler"); + //printTrace(&inst_in_scheduler, "Scheduler"); } void Core::load_store() @@ -562,7 +538,6 @@ void Core::load_store() void Core::execute_unit() { - D(3, "$$$$$$$$$$$$$$$$$$$ EXE START\n" << flush); bool do_nothing = false; // EXEC is always not busy if (inst_in_scheduler.is_lw || inst_in_scheduler.is_sw) @@ -615,7 +590,7 @@ void Core::execute_unit() } else { - D(3, "&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY"); + D(3, "Execute: srcs not ready!"); inst_in_scheduler.stalled = true; // INIT_TRACE(inst_in_exe); do_nothing = true; @@ -627,15 +602,12 @@ void Core::execute_unit() // } - //printTrace(&inst_in_exe, "execute_unit"); + //printTrace(&inst_in_exe, "EXE"); // INIT_TRACE(inst_in_exe); - D(3, "EXECUTE END" << flush); } void Core::writeback() { - - if (inst_in_wb.rd > 0) renameTable[inst_in_wb.wid][inst_in_wb.rd] = true; if (inst_in_wb.vd > 0) vecRenameTable[inst_in_wb.vd] = true; @@ -697,9 +669,7 @@ bool Core::running() const { if (stages_have_valid) return true; for (unsigned i = 0; i < w.size(); ++i) - if (w[i].running()) - { - D(3, "Warp ID " << i << " is running"); + if (w[i].running()) { return true; } return false; @@ -777,8 +747,7 @@ void Warp::step(trace_inst_t * trace_inst) { // ++steps; - D(3, "in step pc=0x" << hex << pc); - D(3, "help: in PC: " << hex << pc << dec); + D(3, "current PC=0x" << hex << pc); // std::cout << "pc: " << hex << pc << "\n"; @@ -798,9 +767,6 @@ void Warp::step(trace_inst_t * trace_inst) { decPos = 0; inst = core->iDec.decode(fetchBuffer, decPos, trace_inst); - D(3, "Fetched at 0x" << hex << pc); - D(3, "0x" << hex << pc << ": " << *inst); - // Update pc pc += decPos; @@ -821,12 +787,10 @@ void Warp::step(trace_inst_t * trace_inst) { } - D(3, "Thread mask:"); - D_RAW(" "); - for (unsigned i = 0; i < tmask.size(); ++i) D_RAW(tmask[i] << ' '); - D_RAW(endl); - D_RAW(endl); - D_RAW(endl); + DPH(3, "Thread mask:"); + for (unsigned i = 0; i < tmask.size(); ++i) DPN(3, " " << tmask[i]); + DPN(3, "\n"); + // } // #endif diff --git a/simX/enc.cpp b/simX/enc.cpp index 6a7d81a2..a19a99e8 100644 --- a/simX/enc.cpp +++ b/simX/enc.cpp @@ -101,9 +101,6 @@ Instruction *WordDecoder::decode(const std::vector &v, Size &idx, trace_in bool predicated = false; if (predicated) { inst.setPred((code>>(inst_s-p-1))&pMask); } - // printf("CUrrent CODE: %x\n", code); - D(3, "Curr Code: " << hex << code << dec); - Opcode op = (Opcode)((code>>shift_opcode)&opcode_mask); // std::cout << "opcode: " << op << "\n"; inst.setOpcode(op); @@ -324,7 +321,7 @@ Instruction *WordDecoder::decode(const std::vector &v, Size &idx, trace_in // inst.setImmRef(*r); } - D(2, "Decoded 0x" << hex << code << " into: " << inst << '\n'); + D(2, "Decoded instr 0x" << hex << code << " into: " << inst); return &inst; } diff --git a/simX/include/archdef.h b/simX/include/archdef.h index fa284aad..b2e871e2 100644 --- a/simX/include/archdef.h +++ b/simX/include/archdef.h @@ -16,15 +16,16 @@ namespace Harp { public: struct Undefined {}; - ArchDef(const std::string &s) { + ArchDef(const std::string &s, bool cpu_mode = false, int num_warps =32, int num_threads = 32) + : cpu_mode_(cpu_mode) { std::istringstream iss(s.c_str()); wordSize = 4; encChar = 'w'; nRegs = 32; nPRegs = 0; - nThds = 32; - nWarps = 32; + nThds = num_warps; + nWarps = num_threads; extent = EXT_WARPS; @@ -98,6 +99,10 @@ namespace Harp { ThdNum getNWarps() const { if (extent < EXT_WARPS) throw Undefined(); else return nWarps; } + + bool is_cpu_mode() const { + return cpu_mode_; + } private: enum Extent { @@ -110,6 +115,7 @@ namespace Harp { ThdNum nThds, nWarps; RegNum nRegs, nPRegs; char encChar; + bool cpu_mode_; }; } diff --git a/simX/include/debug.h b/simX/include/debug.h index 78018e41..81b428e7 100644 --- a/simX/include/debug.h +++ b/simX/include/debug.h @@ -4,20 +4,34 @@ #ifndef __DEBUG_H #define __DEBUG_H -// #define USE_DEBUG 9 -// #define USE_DEBUG 3 +//#define USE_DEBUG 9 #ifdef USE_DEBUG #include #define D(lvl, x) do { \ using namespace std; \ - if ((lvl) == USE_DEBUG) { \ + if ((lvl) <= USE_DEBUG) { \ cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \ << x << endl; \ } \ } while(0) +#define DPH(lvl, x) do { \ + using namespace std; \ + if ((lvl) <= USE_DEBUG) { \ + cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \ + << x; \ + } \ +} while(0) + +#define DPN(lvl, x) do { \ + using namespace std; \ + if ((lvl) <= USE_DEBUG) { \ + cout << x; \ + } \ +} while(0) + #define D_RAW(x) do { \ std::cout << x; \ } while (0) @@ -25,6 +39,8 @@ #else #define D(lvl, x) do {} while(0) +#define DPH(lvl, x) do {} while(0) +#define DPN(lvl, x) do {} while(0) #define D_RAW(x) do {} while(0) #endif diff --git a/simX/include/mem.h b/simX/include/mem.h index f0f340e7..96d1d38c 100644 --- a/simX/include/mem.h +++ b/simX/include/mem.h @@ -168,16 +168,18 @@ namespace Harp { bool disableVm; }; - class RAM : public MemDevice { public: uint8_t* mem[1 << 12]; RAM(){ - for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL; + for(uint32_t i = 0;i < (1 << 12);i++) + mem[i] = NULL; } ~RAM(){ - for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i]; + for(uint32_t i = 0;i < (1 << 12);i++) + if(mem[i]) + delete [] mem[i]; } void clear(){ @@ -218,7 +220,7 @@ namespace Harp { } } - virtual Size size() const { return (1<<31); }; + virtual Size size() const { return -1; } void getBlock(uint32_t address, uint8_t *data) { @@ -325,137 +327,9 @@ namespace Harp { // MEMORY UTILS - uint32_t hti_old(char c) { - if (c >= 'A' && c <= 'F') - return c - 'A' + 10; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return c - '0'; - } - - uint32_t hToI_old(char *c, uint32_t size) { - uint32_t value = 0; - for (uint32_t i = 0; i < size; i++) { - value += hti_old(c[i]) << ((size - i - 1) * 4); - } - return value; - } - - - - void loadHexImpl(std::string path) { - this->clear(); - FILE *fp = fopen(&path[0], "r"); - if(fp == 0){ - std::cout << path << " not found" << std::endl; - } - //Preload 0x0 <-> 0x80000000 jumps - ((uint32_t*)this->get(0))[0] = 0xf1401073; - ((uint32_t*)this->get(0))[1] = 0xf1401073; - - // ((uint32_t*)this->get(0))[1] = 0xf1401073; - ((uint32_t*)this->get(0))[2] = 0x30101073; - - ((uint32_t*)this->get(0))[3] = 0x800000b7; - ((uint32_t*)this->get(0))[4] = 0x000080e7; - - ((uint32_t*)this->get(0x80000000))[0] = 0x00000097; - - ((uint32_t*)this->get(0xb0000000))[0] = 0x01C02023; - // F00FFF10 - ((uint32_t*)this->get(0xf00fff10))[0] = 0x12345678; - - - - ((uint32_t*)this->get(0x70000000))[0] = 0x00008067; - - { - uint32_t init_addr = 0x70000004; - for (int off = 0; off < 1024; off+=4) - { - uint32_t new_addr = init_addr+off; - ((uint32_t*)this->get(new_addr))[0] = 0x00000000; - } - } - - { - uint32_t init_addr = 0x71000000; - for (int off = 0; off < 1024; off+=4) - { - uint32_t new_addr = init_addr+off; - ((uint32_t*)this->get(new_addr))[0] = 0x00000000; - } - } - - { - uint32_t init_addr = 0x72000000; - for (int off = 0; off < 1024; off+=4) - { - uint32_t new_addr = init_addr+off; - ((uint32_t*)this->get(new_addr))[0] = 0x00000000; - } - } - - - fseek(fp, 0, SEEK_END); - uint32_t size = ftell(fp); - fseek(fp, 0, SEEK_SET); - char* content = new char[size]; - int x = fread(content, 1, size, fp); - - if (!x) { std::cout << "COULD NOT READ FILE\n"; std::abort();} - - int offset = 0; - char* line = content; - // std::cout << "WHTA\n"; - while (1) { - if (line[0] == ':') { - uint32_t byteCount = hToI_old(line + 1, 2); - uint32_t nextAddr = hToI_old(line + 3, 4) + offset; - uint32_t key = hToI_old(line + 7, 2); - switch (key) { - case 0: - for (uint32_t i = 0; i < byteCount; i++) { - - unsigned add = nextAddr + i; - - *(this->get(add)) = hToI_old(line + 9 + i * 2, 2); - // std::cout << "lhi: Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI_old(line + 9 + i * 2, 2) << std::endl; - } - break; - case 2: - // cout << offset << endl; - offset = hToI_old(line + 9, 4) << 4; - break; - case 4: - // cout << offset << endl; - offset = hToI_old(line + 9, 4) << 16; - break; - default: - // cout << "??? " << key << endl; - break; - } - } - - while (*line != '\n' && size != 0) { - line++; - size--; - } - if (size <= 1) - break; - line++; - size--; - } - - - if (content) delete[] content; - } + void loadHexImpl(std::string path); }; - - - - } diff --git a/simX/instruction.cpp b/simX/instruction.cpp index 60d23682..47272b0e 100644 --- a/simX/instruction.cpp +++ b/simX/instruction.cpp @@ -45,7 +45,7 @@ ostream &Harp::operator<<(ostream& os, Instruction &inst) { // else os << "#0x" << hex << inst.immsrc; // } - D(3, instTable[inst.op].opString << ';\n'); + os << instTable[inst.op].opString; return os; } @@ -347,8 +347,6 @@ void trap_to_simulator(Warp & c) } void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { - D(3, "Begin instruction execute."); - /* If I try to execute a privileged instruction in user mode, throw an exception 3. */ if (instTable[op].privileged && !c.supervisorMode) { @@ -357,11 +355,8 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { return; } - bool is_vec = false; - - Size nextActiveThreads = c.activeThreads; Size wordSz = c.core->a.getWordSize(); Word nextPc = c.pc; @@ -425,7 +420,6 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { case R_INST: // std::cout << "R_INST\n"; m_exten = func7 & 0x1; - if (m_exten) { // std::cout << "FOUND A MUL/DIV\n"; @@ -434,11 +428,12 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { { case 0: // MUL - // cout << "MUL\n"; + D(3, "MUL: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); reg[rdest] = ((int) reg[rsrc[0]]) * ((int) reg[rsrc[1]]); break; case 1: // MULH + D(3, "MULH: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); { int64_t first = (int64_t) reg[rsrc[0]]; if (reg[rsrc[0]] & 0x80000000) @@ -458,6 +453,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 2: // MULHSU + D(3, "MULHSU: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); { int64_t first = (int64_t) reg[rsrc[0]]; if (reg[rsrc[0]] & 0x80000000) @@ -470,6 +466,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 3: // MULHU + D(3, "MULHU: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); { uint64_t first = (uint64_t) reg[rsrc[0]]; uint64_t second = (uint64_t) reg[rsrc[1]]; @@ -479,6 +476,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 4: // DIV + D(3, "DIV: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); if (reg[rsrc[1]] == 0) { reg[rdest] = -1; @@ -490,6 +488,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 5: // DIVU + D(3, "DIVU: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); if (reg[rsrc[1]] == 0) { reg[rdest] = -1; @@ -499,6 +498,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 6: // REM + D(3, "REM: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); if (reg[rsrc[1]] == 0) { reg[rdest] = reg[rsrc[0]]; @@ -508,6 +508,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 7: // REMU + D(3, "REMU: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); if (reg[rsrc[1]] == 0) { reg[rdest] = reg[rsrc[0]]; @@ -528,20 +529,24 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { case 0: if (func7) { + D(3, "SUBI: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); reg[rdest] = reg[rsrc[0]] - reg[rsrc[1]]; reg[rdest].trunc(wordSz); } else { + D(3, "ADDI: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]]; reg[rdest].trunc(wordSz); } break; case 1: - reg[rdest] = reg[rsrc[0]] << reg[rsrc[1]]; - reg[rdest].trunc(wordSz); + D(3, "SLLI: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); + reg[rdest] = reg[rsrc[0]] << reg[rsrc[1]]; + reg[rdest].trunc(wordSz); break; case 2: + D(3, "SLTI: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); if ( int(reg[rsrc[0]]) < int(reg[rsrc[1]])) { reg[rdest] = 1; @@ -552,7 +557,8 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { } break; case 3: - if ( Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]])) + D(3, "SLTU: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); + if (Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]])) { reg[rdest] = 1; } @@ -562,24 +568,29 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { } break; case 4: + D(3, "XORI: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); reg[rdest] = reg[rsrc[0]] ^ reg[rsrc[1]]; break; case 5: if (func7) - { + { + D(3, "SRLI: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); reg[rdest] = int(reg[rsrc[0]]) >> int(reg[rsrc[1]]); reg[rdest].trunc(wordSz); } else { + D(3, "SRLU: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); reg[rdest] = Word_u(reg[rsrc[0]]) >> Word_u(reg[rsrc[1]]); reg[rdest].trunc(wordSz); } break; case 6: + D(3, "ORI: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); reg[rdest] = reg[rsrc[0]] | reg[rsrc[1]]; break; case 7: + D(3, "ANDI: r" << rdest << " <- r" << rsrc[0] << ", r" << rsrc[1]); reg[rdest] = reg[rsrc[0]] & reg[rsrc[1]]; break; default: @@ -589,35 +600,35 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { } break; case L_INST: - //std::cout << "L_INST\n"; - - memAddr = ((reg[rsrc[0]] + immsrc) & 0xFFFFFFFC); - shift_by = ((reg[rsrc[0]] + immsrc) & 0x00000003) * 8; - data_read = c.core->mem.read(memAddr, c.supervisorMode); - trace_inst->is_lw = true; - trace_inst->mem_addresses[t] = memAddr; - // //std::cout < data_read: " << data_read << "\n"; - - switch (func3) - { - + memAddr = ((reg[rsrc[0]] + immsrc) & 0xFFFFFFFC); + shift_by = ((reg[rsrc[0]] + immsrc) & 0x00000003) * 8; + data_read = c.core->mem.read(memAddr, c.supervisorMode); + trace_inst->is_lw = true; + trace_inst->mem_addresses[t] = memAddr; + switch (func3) { case 0: - // LB + // LBI + D(3, "LBI: r" << rdest << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); reg[rdest] = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF); break; case 1: - // LH - // //std::cout << "shifting by: " << shift_by << " final data: " << ((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF) << "\n"; + // LWI + D(3, "LWI: r" << rdest << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); reg[rdest] = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF); break; case 2: + // LDI + D(3, "LDI: r" << rdest << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); reg[rdest] = int(data_read & 0xFFFFFFFF); break; case 4: // LBU + D(3, "LBU: r" << rdest << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); reg[rdest] = unsigned((data_read >> shift_by) & 0xFF); break; case 5: + // LWU + D(3, "LWU: r" << rdest << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); reg[rdest] = unsigned((data_read >> shift_by) & 0xFFFF); break; default: @@ -625,19 +636,22 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { std::abort(); c.memAccesses.push_back(Warp::MemAccess(false, memAddr)); } + D(3, "LOAD MEM ADDRESS: " << std::hex << memAddr); + D(3, "LOAD MEM DATA: " << std::hex << data_read); break; case I_INST: //std::cout << "I_INST\n"; switch (func3) { - case 0: // ADDI + D(3, "ADDI: r" << rdest << " <- r" << rsrc[0] << ", imm=" << immsrc); reg[rdest] = reg[rsrc[0]] + immsrc; reg[rdest].trunc(wordSz); break; case 2: // SLTI + D(3, "SLTI: r" << rdest << " <- r" << rsrc[0] << ", imm=" << immsrc); if ( int(reg[rsrc[0]]) < int(immsrc)) { reg[rdest] = 1; @@ -649,6 +663,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 3: // SLTIU + D(3, "SLTIU: r" << rdest << " <- r" << rsrc[0] << ", imm=" << immsrc); op1 = (unsigned) reg[rsrc[0]]; if ( unsigned(reg[rsrc[0]]) < unsigned(immsrc)) { @@ -661,18 +676,22 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 4: // XORI + D(3, "XORI: r" << rdest << " <- r" << rsrc[0] << ", imm=0x" << hex << immsrc); reg[rdest] = reg[rsrc[0]] ^ immsrc; break; case 6: - // ORI; + // ORI + D(3, "ORI: r" << rdest << " <- r" << rsrc[0] << ", imm=0x" << hex << immsrc); reg[rdest] = reg[rsrc[0]] | immsrc; break; case 7: // ANDI + D(3, "ANDI: r" << rdest << " <- r" << rsrc[0] << ", imm=0x" << hex << immsrc); reg[rdest] = reg[rsrc[0]] & immsrc; break; case 1: // SLLI + D(3, "SLLI: r" << rdest << " <- r" << rsrc[0] << ", imm=0x" << hex << immsrc); reg[rdest] = reg[rsrc[0]] << immsrc; reg[rdest].trunc(wordSz); break; @@ -680,31 +699,20 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { if ((func7 == 0)) { // SRLI - // //std::cout << "WTF\n"; - bool isNeg = ((0x80000000 & reg[rsrc[0]])) > 0; - Word result = Word_u(reg[rsrc[0]]) >> Word_u(immsrc); - // if (isNeg) - // { - // Word mask = 0x80000000; - // for (int i = 32; i < Word_u(immsrc); i++) - // { - // result |= mask; - // mask = mask >> 1; - // } - // } - - reg[rdest] = result; - - reg[rdest].trunc(wordSz); + D(3, "SRLI: r" << rdest << " <- r" << rsrc[0] << ", imm=" << immsrc); + bool isNeg = ((0x80000000 & reg[rsrc[0]])) > 0; + Word result = Word_u(reg[rsrc[0]]) >> Word_u(immsrc); + reg[rdest] = result; + reg[rdest].trunc(wordSz); } else { - // SRAI - // //std::cout << "WOHOOOOO\n"; - op1 = reg[rsrc[0]]; - op2 = immsrc; - reg[rdest] = op1 >> op2; - reg[rdest].trunc(wordSz); + // SRAI + D(3, "SRAI: r" << rdest << " <- r" << rsrc[0] << ", imm=" << immsrc); + op1 = reg[rsrc[0]]; + op2 = immsrc; + reg[rdest] = op1 >> op2; + reg[rdest].trunc(wordSz); } break; default: @@ -713,11 +721,8 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { } break; case S_INST: - //std::cout << "S_INST\n"; ++c.stores; - memAddr = reg[rsrc[0]] + immsrc; - D(3, "STORE MEM ADDRESS: " << std::hex << reg[rsrc[0]] << " + " << immsrc << "\n"); - D(3, "STORE MEM ADDRESS: " << std::hex << memAddr); + memAddr = reg[rsrc[0]] + immsrc; trace_inst->is_sw = true; trace_inst->mem_addresses[t] = memAddr; // //std::cout << "FUNC3: " << func3 << "\n"; @@ -730,21 +735,25 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { switch (func3) { case 0: - // //std::cout << "SB\n"; + // SB + D(3, "SB: r" << rsrc[1] << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); c.core->mem.write(memAddr, reg[rsrc[1]] & 0x000000FF, c.supervisorMode, 1); break; case 1: - // //std::cout << "SH\n"; + // SH + D(3, "SH: r" << rsrc[1] << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 2); break; case 2: - // //std::cout << std::hex << "SW: about to write: " << reg[rsrc[1]] << " to " << memAddr << "\n"; + // SD + D(3, "SD: r" << rsrc[1] << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 4); break; default: cout << "ERROR: UNSUPPORTED S INST\n"; std::abort(); } + D(3, "STORE MEM ADDRESS: " << std::hex << memAddr); c.memAccesses.push_back(Warp::MemAccess(true, memAddr)); #ifdef EMU_INSTRUMENTATION Harp::OSDomain::osDomain-> @@ -752,13 +761,12 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { #endif break; case B_INST: - //std::cout << "B_INST\n"; - trace_inst->stall_warp = true; - D(3,"func3:" << func3 << endl); + trace_inst->stall_warp = true; switch (func3) { case 0: // BEQ + D(3,"BEQ: r" << rsrc[0] << ", r" << rsrc[1] << ", imm=" << (int)immsrc); if (int(reg[rsrc[0]]) == int(reg[rsrc[1]])) { if (!pcSet) nextPc = (c.pc - 4) + immsrc; @@ -767,7 +775,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 1: // BNE - D(3, "rsrc0: " << reg[rsrc[0]] << " rsrc1 : " << reg[rsrc[1]] << endl); + D(3,"BNE: r" << rsrc[0] << ", r" << rsrc[1] << ", imm=" << (int)immsrc); if (int(reg[rsrc[0]]) != int(reg[rsrc[1]])) { if (!pcSet) nextPc = (c.pc - 4) + immsrc; @@ -776,6 +784,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 4: // BLT + D(3,"BLT: r" << rsrc[0] << ", r" << rsrc[1] << ", imm=" << (int)immsrc); if (int(reg[rsrc[0]]) < int(reg[rsrc[1]])) { if (!pcSet) nextPc = (c.pc - 4) + immsrc; @@ -784,6 +793,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 5: // BGE + D(3,"BGE: r" << rsrc[0] << ", r" << rsrc[1] << ", imm=" << (int)immsrc); if (int(reg[rsrc[0]]) >= int(reg[rsrc[1]])) { if (!pcSet) nextPc = (c.pc - 4) + immsrc; @@ -792,6 +802,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 6: // BLTU + D(3,"BLTU: r" << rsrc[0] << ", r" << rsrc[1] << ", imm=" << (int)immsrc); if (Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]])) { if (!pcSet) nextPc = (c.pc - 4) + immsrc; @@ -800,6 +811,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 7: // BGEU + D(3,"BGEU: r" << rsrc[0] << ", r" << rsrc[1] << ", imm=" << (int)immsrc); if (Word_u(reg[rsrc[0]]) >= Word_u(reg[rsrc[1]])) { if (!pcSet) nextPc = (c.pc - 4) + immsrc; @@ -809,26 +821,25 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { } break; case LUI_INST: - //std::cout << "LUI_INST\n"; + D(3, "LUI: r" << rdest << " <- imm=0x" << hex << immsrc); reg[rdest] = (immsrc << 12) & 0xfffff000; break; case AUIPC_INST: - //std::cout << "AUIPC_INST\n"; + D(3, "AUIPC: r" << rdest << " <- imm=0x" << hex << immsrc); reg[rdest] = ((immsrc << 12) & 0xfffff000) + (c.pc - 4); break; case JAL_INST: - //std::cout << "JAL_INST\n"; + D(3, "JAL: r" << rdest << " <- imm=" << (int)immsrc); trace_inst->stall_warp = true; if (!pcSet) nextPc = (c.pc - 4) + immsrc; if (!pcSet) {/*std::cout << "JAL... SETTING PC: " << nextPc << "\n"; */} - if (rdest != 0) - { + if (rdest != 0) { reg[rdest] = c.pc; } pcSet = true; break; case JALR_INST: - D(3, "JALR_INST\n"); + D(3, "JALR: r" << rdest << " <- r" << rsrc[0] << ", imm=" << (int)immsrc); trace_inst->stall_warp = true; if (!pcSet) nextPc = reg[rsrc[0]] + immsrc; if (!pcSet) {/*std::cout << "JALR... SETTING PC: " << nextPc << "\n";*/ } @@ -841,99 +852,109 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { case SYS_INST: //std::cout << "SYS_INST\n"; temp = reg[rsrc[0]]; - if (immsrc == 0x20) // ThreadID - { - reg[rdest] = t; - D(2, "CSR Reading tid " << hex << immsrc << dec << " and returning " << reg[rdest]); - } else if (immsrc == 0x21) // WarpID - { - reg[rdest] = c.id; - D(2, "CSR Reading wid " << hex << immsrc << dec << " and returning " << reg[rdest]); - } else if (immsrc == 0x25) - { - reg[rdest] = c.core->num_instructions; - } else if (immsrc == 0x26) - { - reg[rdest] = c.core->num_cycles; + + if (!c.core->a.is_cpu_mode()) { + // + // GPGPU CSR extension + // + if (immsrc == 0x20) // ThreadID + { + reg[rdest] = t; + D(2, "CSR Reading tid " << hex << immsrc << dec << " and returning " << reg[rdest]); + } + else if (immsrc == 0x21) // WarpID + { + reg[rdest] = c.id; + D(2, "CSR Reading wid " << hex << immsrc << dec << " and returning " << reg[rdest]); + } + else if (immsrc == 0x25) + { + reg[rdest] = c.core->num_instructions; + } + else if (immsrc == 0x26) + { + reg[rdest] = c.core->num_cycles; + } + } else { + switch (func3) + { + case 1: + // printf("Case 1\n"); + if (rdest != 0) + { + reg[rdest] = c.csr[immsrc & 0x00000FFF]; + } + c.csr[immsrc & 0x00000FFF] = temp; + + break; + case 2: + // printf("Case 2\n"); + if (rdest != 0) + { + // printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]); + reg[rdest] = c.csr[immsrc & 0x00000FFF]; + } + // printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF])); + c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF]; + + break; + case 3: + // printf("Case 3\n"); + if (rdest != 0) + { + reg[rdest] = c.csr[immsrc & 0x00000FFF]; + } + c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]); + + break; + case 5: + // printf("Case 5\n"); + if (rdest != 0) + { + reg[rdest] = c.csr[immsrc & 0x00000FFF]; + } + c.csr[immsrc & 0x00000FFF] = rsrc[0]; + + break; + case 6: + // printf("Case 6\n"); + if (rdest != 0) + { + reg[rdest] = c.csr[immsrc & 0x00000FFF]; + } + c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF]; + + break; + case 7: + // printf("Case 7\n"); + if (rdest != 0) + { + reg[rdest] = c.csr[immsrc & 0x00000FFF]; + } + c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]); + + break; + case 0: + if (immsrc < 2) + { + //std::cout << "INTERRUPT ECALL/EBREAK\n"; + nextActiveThreads = 0; + c.spawned = false; + // c.interrupt(0); + } + break; + default: + break; + } } - // switch (func3) - // { - // case 1: - // // printf("Case 1\n"); - // if (rdest != 0) - // { - // reg[rdest] = c.csr[immsrc & 0x00000FFF]; - // } - // c.csr[immsrc & 0x00000FFF] = temp; - - // break; - // case 2: - // // printf("Case 2\n"); - // if (rdest != 0) - // { - // // printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]); - // reg[rdest] = c.csr[immsrc & 0x00000FFF]; - // } - // // printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF])); - // c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF]; - - // break; - // case 3: - // // printf("Case 3\n"); - // if (rdest != 0) - // { - // reg[rdest] = c.csr[immsrc & 0x00000FFF]; - // } - // c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]); - - // break; - // case 5: - // // printf("Case 5\n"); - // if (rdest != 0) - // { - // reg[rdest] = c.csr[immsrc & 0x00000FFF]; - // } - // c.csr[immsrc & 0x00000FFF] = rsrc[0]; - - // break; - // case 6: - // // printf("Case 6\n"); - // if (rdest != 0) - // { - // reg[rdest] = c.csr[immsrc & 0x00000FFF]; - // } - // c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF]; - - // break; - // case 7: - // // printf("Case 7\n"); - // if (rdest != 0) - // { - // reg[rdest] = c.csr[immsrc & 0x00000FFF]; - // } - // c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]); - - // break; - // case 0: - // if (immsrc < 2) - // { - // //std::cout << "INTERRUPT ECALL/EBREAK\n"; - // nextActiveThreads = 0; - // c.spawned = false; - // // c.interrupt(0); - // } - // break; - // default: - // break; - // } break; case TRAP: - //std::cout << "INTERRUPT TRAP\n"; + D(3, "TRAP"); nextActiveThreads = 0; c.interrupt(0); break; case FENCE: - //std::cout << "FENCE_INST\n"; + D(3, "FENCE"); break; case PJ_INST: // pred jump reg @@ -950,13 +971,13 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { { case 1: // WSPAWN - D(3, "WSPAWN\n"); + D(3, "WSPAWN"); trace_inst->wspawn = true; if (sjOnce) { sjOnce = false; // //std::cout << "SIZE: " << c.core->w.size() << "\n"; - num_to_wspawn = reg[rsrc[0]]; + num_to_wspawn = std::min(reg[rsrc[0]], c.core->a.getNWarps()); D(0, "Spawning " << num_to_wspawn << " new warps at PC: " << hex << reg[rsrc[1]]); for (unsigned i = 1; i < num_to_wspawn; ++i) @@ -992,7 +1013,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { case 2: { // SPLIT - //std::cout << "SPLIT\n"; + D(3, "SPLIT"); trace_inst->stall_warp = true; if (sjOnce) { @@ -1025,8 +1046,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { } case 3: // JOIN - //std::cout << "JOIN\n"; - D(3, "JOIN INSTRUCTION"); + D(3, "JOIN"); if (sjOnce) { sjOnce = false; @@ -1062,9 +1082,9 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { break; case 0: // TMC - //std::cout << "JALRS\n"; + D(3, "TMC"); trace_inst->stall_warp = true; - nextActiveThreads = reg[rsrc[0]]; + nextActiveThreads = std::min(reg[rsrc[0]], c.core->a.getNThds()); { for (int ff = 0; ff < c.tmask.size(); ff++) { @@ -2418,8 +2438,6 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { // std::cout << "finished instruction" << endl << flush; - D(3, "End instruction execute." << flush); - c.activeThreads = nextActiveThreads; // if (nextActiveThreads != 0) @@ -2430,8 +2448,6 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) { // } // } - - // //std::cout << "new thread mask: "; // for (int i = 0; i < c.tmask.size(); ++i) //std::cout << " " << c.tmask[i]; // //std::cout << "\n"; diff --git a/simX/mem.cpp b/simX/mem.cpp index b39a0ee4..870f9946 100644 --- a/simX/mem.cpp +++ b/simX/mem.cpp @@ -280,6 +280,120 @@ void DiskControllerMemDevice::write(Addr a, Word w) { } } +static uint32_t hti_old(char c) { + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return c - '0'; + } +static uint32_t hToI_old(char *c, uint32_t size) { + uint32_t value = 0; + for (uint32_t i = 0; i < size; i++) { + value += hti_old(c[i]) << ((size - i - 1) * 4); + } + return value; +} +void RAM::loadHexImpl(std::string path) { + this->clear(); + FILE *fp = fopen(&path[0], "r"); + if(fp == 0){ + std::cout << path << " not found" << std::endl; + } + //Preload 0x0 <-> 0x80000000 jumps + ((uint32_t*)this->get(0))[0] = 0xf1401073; + ((uint32_t*)this->get(0))[1] = 0xf1401073; + ((uint32_t*)this->get(0))[2] = 0x30101073; + ((uint32_t*)this->get(0))[3] = 0x800000b7; + ((uint32_t*)this->get(0))[4] = 0x000080e7; + + ((uint32_t*)this->get(0x80000000))[0] = 0x00000097; + + ((uint32_t*)this->get(0xb0000000))[0] = 0x01C02023; + + ((uint32_t*)this->get(0xf00fff10))[0] = 0x12345678; + + ((uint32_t*)this->get(0x70000000))[0] = 0x00008067; + + { + uint32_t init_addr = 0x70000004; + for (int off = 0; off < 1024; off+=4) { + uint32_t new_addr = init_addr+off; + ((uint32_t*)this->get(new_addr))[0] = 0x00000000; + } + } + + { + uint32_t init_addr = 0x71000000; + for (int off = 0; off < 1024; off+=4) { + uint32_t new_addr = init_addr+off; + ((uint32_t*)this->get(new_addr))[0] = 0x00000000; + } + } + + { + uint32_t init_addr = 0x72000000; + for (int off = 0; off < 1024; off+=4) { + uint32_t new_addr = init_addr+off; + ((uint32_t*)this->get(new_addr))[0] = 0x00000000; + } + } + + fseek(fp, 0, SEEK_END); + uint32_t size = ftell(fp); + fseek(fp, 0, SEEK_SET); + char* content = new char[size]; + int x = fread(content, 1, size, fp); + + if (!x) { + std::cout << "COULD NOT READ FILE\n"; std::abort(); + } + + int offset = 0; + char* line = content; + // std::cout << "WHTA\n"; + while (1) { + if (line[0] == ':') { + uint32_t byteCount = hToI_old(line + 1, 2); + uint32_t nextAddr = hToI_old(line + 3, 4) + offset; + uint32_t key = hToI_old(line + 7, 2); + switch (key) { + case 0: + for (uint32_t i = 0; i < byteCount; i++) { + unsigned add = nextAddr + i; + *(this->get(add)) = hToI_old(line + 9 + i * 2, 2); + // std::cout << "lhi: Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI_old(line + 9 + i * 2, 2) << std::endl; + } + break; + case 2: + // cout << offset << endl; + offset = hToI_old(line + 9, 4) << 4; + break; + case 4: + // cout << offset << endl; + offset = hToI_old(line + 9, 4) << 16; + break; + default: + // cout << "??? " << key << endl; + break; + } + } + + while (*line != '\n' && size != 0) { + line++; + size--; + } + + if (size <= 1) + break; + + line++; + size--; + } + + if (content) + delete[] content; + } \ No newline at end of file diff --git a/simX/simX.cpp b/simX/simX.cpp index 1db16a5c..00e86d52 100644 --- a/simX/simX.cpp +++ b/simX/simX.cpp @@ -55,40 +55,46 @@ HarpToolMode findMode(int argc, char** argv) { } int emu_main(int argc, char **argv) { - string archString("rv32i"), imgFileName("a.dsfsdout.bin"); - bool showHelp, showStats, basicMachine, batch; + string archString("rv32i"); + string imgFileName("a.dsfsdout.bin"); + bool showHelp(false), showStats(false), basicMachine(true); + bool cpu_mode(false); + int max_warps(32); + int max_threads(32); - /* Read the command line arguments. */ - CommandLineArgFlag fh("-h", "--help", "", showHelp); - CommandLineArgSetterfc("-c", "--core", "", imgFileName); - CommandLineArgSetterfa("-a", "--arch", "", archString); - CommandLineArgFlag fs("-s", "--stats", "", showStats); - CommandLineArgFlag fb("-b", "--basic", "", basicMachine); - CommandLineArgFlag fi("-i", "--batch", "", batch); - - CommandLineArg::readArgs(argc, argv); - if (showHelp) { - cout << Help::emuHelp; - return 0; - } + /* Read the command line arguments. */ + CommandLineArgFlag fh("-h", "--help", "", showHelp); + CommandLineArgSetterfc("-c", "--core", "", imgFileName); + CommandLineArgSetterfa("-a", "--arch", "", archString); + CommandLineArgFlag fs("-s", "--stats", "", showStats); + CommandLineArgFlag fb("-b", "--basic", "", basicMachine); + CommandLineArgFlag fx("-x", "--cpu", "", cpu_mode); + CommandLineArgSetter fw("-w", "--warps", "", max_warps); + CommandLineArgSetter ft("-t", "--threads", "", max_threads); + + CommandLineArg::readArgs(argc, argv); + + if (showHelp) { + cout << Help::emuHelp; + return 0; + } - /* Instantiate a Core, RAM, and console output. */ - ArchDef arch(archString); + /* Instantiate a Core, RAM, and console output. */ + ArchDef arch(archString, cpu_mode, max_warps, max_threads); - Decoder *dec; + Decoder *dec; - switch (arch.getEncChar()) { + switch (arch.getEncChar()) { case 'b': dec = new WordDecoder(arch); break; case 'w': dec = new WordDecoder(arch); break; case 'r': dec = new WordDecoder(arch); break; default: cout << "Unrecognized decoder type: '" << arch.getEncChar() << "'.\n"; return 1; - } + } // std::cout << "TESTING: " << tests[t] << "\n"; - MemoryUnit mu(4096, arch.getWordSize(), basicMachine); Core core(arch, *dec, mu/*, ID in multicore implementations*/); diff --git a/simX/test_riscv.sh b/simX/test_riscv.sh index c0d8a628..77ebb254 100755 --- a/simX/test_riscv.sh +++ b/simX/test_riscv.sh @@ -1,7 +1,141 @@ +make +cd obj_dir echo start > results.txt -# echo ../kernel/vortex_test.hex -make -printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n" -#cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug -cd obj_dir && ./Vcache_simX -E -a rv32i --core /home/priya/Desktop/new_vortex/Vortex/rvvector/benchmark_temp/vx_vec_benchmark.hex -s -b 1> emulator.debug +echo ./riscv_tests/rv32ui-p-add.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-add.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-and.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-and.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-or.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-or.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt + +echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt +./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt + +# echo ./riscv_tests/rv32um-p-div.hex >> results.txt +# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-div.hex -s -b >> results.txt + +# echo ./riscv_tests/rv32um-p-divu.hex >> results.txt +# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-divu.hex -s -b >> results.txt + +# echo ./riscv_tests/rv32um-p-mul.hex >> results.txt +# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mul.hex -s -b >> results.txt + +# echo ./riscv_tests/rv32um-p-mulh.hex >> results.txt +# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt + +# echo ./riscv_tests/rv32um-p-mulhsu.hex >> results.txt +# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt + +# echo ./riscv_tests/rv32um-p-mulhu.hex >> results.txt +# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt + +# echo ./riscv_tests/rv32um-p-rem.hex >> results.txt +# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-rem.hex -s -b >> results.txt + +# echo ./riscv_tests/rv32um-p-remu.hex >> results.txt +# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-remu.hex -s -b >> results.txt \ No newline at end of file From f7e0d1e4913cc7748c5d487eb3f444de3daa0fe5 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 27 Mar 2020 22:51:54 -0400 Subject: [PATCH 66/66] missing runtime changes from OPAE --- runtime/io/vx_io.c | 2 +- runtime/io/vx_io.h | 4 +- runtime/io/vx_io.s | 6 +- runtime/vx_api/vx_api.c | 161 +++++++--------------------------------- runtime/vx_api/vx_api.h | 33 ++------ 5 files changed, 40 insertions(+), 166 deletions(-) diff --git a/runtime/io/vx_io.c b/runtime/io/vx_io.c index 79f5f8ca..8da5a8c0 100644 --- a/runtime/io/vx_io.c +++ b/runtime/io/vx_io.c @@ -26,7 +26,7 @@ void vx_print_hex(unsigned f) } -void vx_printf(char * c, unsigned f) +void vx_printf(const char * c, unsigned f) { vx_print_str(c); vx_print_hex(f); diff --git a/runtime/io/vx_io.h b/runtime/io/vx_io.h index faf73d6d..f4c69c57 100644 --- a/runtime/io/vx_io.h +++ b/runtime/io/vx_io.h @@ -9,9 +9,9 @@ extern "C" { static char * hextoa[] = {"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "a", "b", "c", "d", "e", "f"}; void vx_print_hex(unsigned); -void vx_printf(char *, unsigned); +void vx_printf(const char *, unsigned); -void vx_print_str(char *); +void vx_print_str(const char *); void vx_printc(unsigned, char c); diff --git a/runtime/io/vx_io.s b/runtime/io/vx_io.s index 806f2790..86d90ed0 100644 --- a/runtime/io/vx_io.s +++ b/runtime/io/vx_io.s @@ -22,9 +22,11 @@ be: .type vx_printc, @function .global vx_printc vx_printc: - la t0, 0x00010000 + la t0, print_addr sw a1, 0(t0) ret - +.section .data +print_addr: + .word 0x00010000 diff --git a/runtime/vx_api/vx_api.c b/runtime/vx_api/vx_api.c index aeba2c10..98fa136a 100644 --- a/runtime/vx_api/vx_api.c +++ b/runtime/vx_api/vx_api.c @@ -1,182 +1,75 @@ -#pragma once - #include "../intrinsics/vx_intrinsics.h" #include "vx_api.h" #include -#include "../config.h" - #ifdef __cplusplus extern "C" { #endif func_t global_function_pointer; -// void (func_t)(void *) - -void * global_argument_struct; - +void * global_argument_struct; unsigned global_num_threads; -void setup_call() -{ + +void setup_call() { vx_tmc(global_num_threads); global_function_pointer(global_argument_struct); unsigned wid = vx_warpID(); - if (wid != 0) - { + if (wid != 0) { vx_tmc(0); // Halt Warp Execution - } - else - { + } else { vx_tmc(1); // Only activate one thread } } -void vx_spawnWarps(unsigned numWarps, unsigned numThreads, func_t func_ptr, void * args) -{ +void vx_spawnWarps(unsigned numWarps, unsigned numThreads, func_t func_ptr, void * args) { global_function_pointer = func_ptr; global_argument_struct = args; global_num_threads = numThreads; vx_wspawn(numWarps, (unsigned) setup_call); setup_call(); - } - unsigned pocl_threads; -uint8_t * pocl_args; -uint8_t * pocl_ctx; +struct context_t * pocl_ctx; vx_pocl_workgroup_func pocl_pfn; +const void * pocl_args; -unsigned global_z; -unsigned global_y; -unsigned global_x; - - -void pocl_spawn_real() -{ +void pocl_spawn_runonce() { + vx_tmc(pocl_threads); - int base_x = vx_threadID(); - int base_y = vx_warpID(); - int local_x; - int local_y; + int x = vx_threadID(); + int y = vx_warpID(); - for (int iter_z = 0; iter_z < global_z; iter_z++) - { - for (int iter_x = 0; iter_x < global_x; iter_x++) - { - for (int iter_y = 0; iter_y < global_y; iter_y++) - { + (pocl_pfn)(pocl_args, pocl_ctx, x, y, 0); - local_x = (iter_x * TOTAL_THREADS) + base_x; - local_y = (iter_y * TOTAL_WARPS ) + base_y; - - (pocl_pfn)( pocl_args, pocl_ctx, local_x, local_y, iter_z); - - } - } - } - - // (pocl_pfn)( pocl_args, pocl_ctx, x, y, 0); - - if (base_y != 0) - { + if (y != 0) { vx_tmc(0); } + vx_tmc(1); } - -void pocl_spawn(struct context_t * ctx, const void * pfn, void * arguments) -{ - - - // printf("ctx->num_groups[0]: %d\n", ctx->num_groups[0]); - // printf("ctx->num_groups[1]: %d\n", ctx->num_groups[1]); - // printf("ctx->num_groups[2]: %d\n", ctx->num_groups[2]); - - // printf("\n\n"); - - // printf("ctx->local_size[0]: %d\n", ctx->local_size[0]); - // printf("ctx->local_size[1]: %d\n", ctx->local_size[1]); - // printf("ctx->local_size[2]: %d\n", ctx->local_size[2]); - if (ctx->num_groups[0] > TOTAL_THREADS) - { - pocl_threads = TOTAL_THREADS; - global_x = ctx->num_groups[0] / TOTAL_THREADS; - // printf("pocl_threads: %d\n", pocl_threads); - // printf("global_x: %d\n", global_x); - } - else - { - pocl_threads = ctx->num_groups[0]; - global_x = 1; - // printf("pocl_threads: %d\n", pocl_threads); - // printf("global_x: %d\n", global_x); +void pocl_spawn(struct context_t * ctx, vx_pocl_workgroup_func pfn, const void * args) { + if (ctx->num_groups[2] > 1) { + printf("ERROR: pocl_spawn doesn't support Z dimension yet!\n"); + return; } + pocl_threads = ctx->num_groups[0]; + pocl_ctx = ctx; + pocl_pfn = pfn; + pocl_args = args; - global_z = ctx->num_groups[2]; - pocl_pfn = (vx_pocl_workgroup_func) pfn; - pocl_ctx = (uint8_t *) ctx; - pocl_args = (uint8_t *) arguments; - - if (ctx->num_groups[1] > 1) - { - if (ctx->num_groups[1] > TOTAL_WARPS) - { - global_y = ctx->num_groups[1] / TOTAL_WARPS; - vx_wspawn(TOTAL_WARPS, (unsigned) &pocl_spawn_real); - // printf("global_y: %d\n", global_y); - // printf("Warps: %d\n", TOTAL_WARPS); - } - else - { - global_y = 1; - vx_wspawn(ctx->num_groups[1], (unsigned) &pocl_spawn_real); - // printf("global_y: %d\n", global_y); - // printf("Warps: %d\n", ctx->num_groups[1]); - } + if (ctx->num_groups[1] > 1) { + vx_wspawn(ctx->num_groups[1], (unsigned)&pocl_spawn_runonce); } - unsigned starting_cycles = vx_getCycles(); - unsigned starting_inst = vx_getInst(); - - pocl_spawn_real(); - - unsigned end_cycles = vx_getCycles(); - unsigned end_inst = vx_getInst(); - - - unsigned total_cycles = (unsigned) (end_cycles - starting_cycles); - // float total_inst = (float) (end_inst - starting_inst ); - - // float ipc = total_inst/total_cycles; - - printf("%d\n", total_cycles); - - vx_tmc(0); - - // printf("pocl_spawn: Total Cycles: %d\n", ); - // printf("pocl_spawn: Total Inst : %d\n", (end_inst - starting_inst )); - - // int z; - // int y; - // int x; - // for (z = 0; z < ctx->num_groups[2]; ++z) - // { - // for (y = 0; y < ctx->num_groups[1]; ++y) - // { - // for (x = 0; x < ctx->num_groups[0]; ++x) - // { - // (use_pfn)((uint8_t *)arguments, (uint8_t *)ctx, x, y, z); - // } - // } - // } + pocl_spawn_runonce(); } #ifdef __cplusplus } -#endif +#endif \ No newline at end of file diff --git a/runtime/vx_api/vx_api.h b/runtime/vx_api/vx_api.h index 6737fac1..a4ffcb44 100644 --- a/runtime/vx_api/vx_api.h +++ b/runtime/vx_api/vx_api.h @@ -1,6 +1,5 @@ #ifndef VX_API_ - #define VX_API_ #include @@ -14,47 +13,27 @@ typedef void (*func_t)(void *); void vx_spawnWarps(unsigned numWarps, unsigned numThreads, func_t func_ptr , void * args); -// struct context_t { - -// unsigned num_groups[3]; // use {2, 1, 1} for vecadd - -// unsigned global_offset[3]; // use {0, 0, 0} for vecadd - -// unsigned local_size[3]; // use {2, 1, 1} for vecadd - -// unsigned char *printf_buffer; // zero for now - -// unsigned *printf_buffer_position; // initialized to zero - -// unsigned printf_buffer_capacity; // zero for now - -// unsigned work_dim; // use ‘1’ for vecadd - -// }; - struct context_t { uint32_t num_groups[3]; uint32_t global_offset[3]; - uint32_t local_size[3]; - uint8_t *printf_buffer; + uint32_t local_size[3]; + char * printf_buffer; uint32_t *printf_buffer_position; - uint32_t printf_buffer_capacity; + uint32_t printf_buffer_capacity; uint32_t work_dim; }; - /* The default work-group function prototype as generated by Workgroup.cc. */ -typedef void (*vx_pocl_workgroup_func) (uint8_t * /* args */, - uint8_t * /* pocl_context */, +typedef void (*vx_pocl_workgroup_func) (const void * /* args */, + const struct context_t * /* context */, uint32_t /* group_x */, uint32_t /* group_y */, uint32_t /* group_z */); -void pocl_spawn(struct context_t * ctx, const void * pfn, void * arguments); +void pocl_spawn(struct context_t * ctx, vx_pocl_workgroup_func pfn, const void * args); #ifdef __cplusplus } #endif - #endif \ No newline at end of file